diff --git a/.gitignore b/.gitignore
index 2627597efc..fe742afbf8 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,6 @@
 target/
+# `target/` above is for cargo build dirs; this source module is real code.
+!crates/cuda-oxide-codegen/src/target/
 .smoketest-logs/
 *.ptx
 *.ltoir
@@ -18,6 +20,7 @@ target/
 .vscode/
 .claude/
 .codex/
+.codex-work/
 .agents/
 AGENTS.md
 .mcp/
diff --git a/crates/cargo-oxide/src/commands.rs b/crates/cargo-oxide/src/commands.rs
deleted file mode 100644
index 4e36ec4afa..0000000000
--- a/crates/cargo-oxide/src/commands.rs
+++ /dev/null
@@ -1,11297 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-//! Command implementations for cargo-oxide.
-//!
-//! These port the xtask commands with improvements:
-//! - Backend path resolved via discovery chain instead of hardcoded relative path
-//! - Workspace root resolved by walking up from CWD instead of assuming CWD
-
-use crate::backend;
-use sha2::Digest as _;
-use std::collections::BTreeMap;
-use std::fs;
-use std::path::{Path, PathBuf};
-use std::process::Command;
-
-const MATERIALIZE_ENV: &str = reserved_oxide_symbols::MATERIALIZE_CUBIN_ENV;
-const EXPECTED_PROVENANCE_ENV: &str = reserved_oxide_symbols::MATERIALIZER_PROVENANCE_ENV;
-const MATERIALIZER_HANDSHAKE_ENV: &str = reserved_oxide_symbols::MATERIALIZER_HANDSHAKE_ENV;
-const CODEGEN_FINGERPRINT_ENV: &str = reserved_oxide_symbols::CODEGEN_FINGERPRINT_ENV;
-const DEVICE_CODEGEN_CRATE_ENV: &str = reserved_oxide_symbols::DEVICE_CODEGEN_CRATE_ENV;
-const BACKEND_IDENTITY_CFG: &str = "cuda_oxide_internal_backend_identity";
-const LEGACY_CODEGEN_FINGERPRINT_CFG: &str = "cuda_oxide_internal_codegen_env";
-const LEGACY_MATERIALIZER_PROVENANCE_CFG: &str = "cuda_oxide_internal_materializer_provenance";
-const MATERIALIZER_HANDSHAKE_CACHE: &str = ".oxide-artifacts/materializer-handshake/v1.json";
-
-#[derive(Clone, Debug, Default, Eq, PartialEq)]
-struct MaterializationMode {
-    prepared: Option<PreparedMaterialization>,
-}
-
-#[derive(Clone, Debug, Eq, PartialEq)]
-struct PreparedMaterialization {
-    provenance_sha256_hex: String,
-    tool_identity_handshake_json: String,
-}
-
-impl MaterializationMode {
-    fn enabled(&self) -> bool {
-        self.prepared.is_some()
-    }
-
-    fn apply(&self, cmd: &mut Command) {
-        if let Some(prepared) = &self.prepared {
-            // These override inherited/project values: they are a single
-            // wrapper-generated handshake tied to this Cargo invocation.
-            cmd.env(MATERIALIZE_ENV, "1")
-                .env(EXPECTED_PROVENANCE_ENV, &prepared.provenance_sha256_hex)
-                .env(
-                    MATERIALIZER_HANDSHAKE_ENV,
-                    &prepared.tool_identity_handshake_json,
-                )
-                .env("CUDA_OXIDE_EMIT_NVVM_IR", "1");
-        }
-    }
-}
-
-fn prepare_materialization(
-    ctx: &Context,
-    cli_requested: bool,
-    cli_arch: Option<&str>,
-    emit_nvvm_ir: bool,
-) -> MaterializationMode {
-    prepare_materialization_result(ctx, cli_requested, cli_arch, emit_nvvm_ir).unwrap_or_else(
-        |error| {
-            eprintln!("Error: {error}");
-            std::process::exit(2);
-        },
-    )
-}
-
-/// `prepare_materialization` with the ambient `CUDA_OXIDE_MATERIALIZE_CUBIN`
-/// injected, so `cargo_passthrough_command_with_env` can reach
-/// `materialization_requested_with_env`.
-///
-/// Note this still exits the process on error, which inside a unit test aborts
-/// the whole test binary rather than failing one case -- a further reason tests
-/// must not reach the ambient read.
-fn prepare_materialization_with_env(
-    ctx: &Context,
-    cli_requested: bool,
-    cli_arch: Option<&str>,
-    emit_nvvm_ir: bool,
-    materialize_env: Option<std::ffi::OsString>,
-) -> MaterializationMode {
-    prepare_materialization_result_with_env(
-        ctx,
-        cli_requested,
-        cli_arch,
-        emit_nvvm_ir,
-        materialize_env,
-    )
-    .unwrap_or_else(|error| {
-        eprintln!("Error: {error}");
-        std::process::exit(2);
-    })
-}
-
-const EMIT_NVVM_IR_ENV: &str = "CUDA_OXIDE_EMIT_NVVM_IR";
-
-fn nvvm_ir_requested(ctx: &Context) -> Result<bool, String> {
-    nvvm_ir_requested_with_env(ctx, std::env::var_os(EMIT_NVVM_IR_ENV))
-}
-
-/// `nvvm_ir_requested` with the ambient `CUDA_OXIDE_EMIT_NVVM_IR` injected.
-///
-/// The process value outranks project config, so resolution has to be
-/// injectable for unit tests: an exported `CUDA_OXIDE_EMIT_NVVM_IR` would
-/// otherwise decide the answer before the configured value is consulted.
-fn nvvm_ir_requested_with_env(
-    ctx: &Context,
-    env_value: Option<std::ffi::OsString>,
-) -> Result<bool, String> {
-    if let Some(value) = env_value {
-        let value = value
-            .into_string()
-            .map_err(|_| format!("{EMIT_NVVM_IR_ENV} is not valid Unicode"))?;
-        return parse_strict_bool(EMIT_NVVM_IR_ENV, &value);
-    }
-
-    if let Some(value) = project_config_env(ctx, EMIT_NVVM_IR_ENV) {
-        return parse_strict_bool(EMIT_NVVM_IR_ENV, value);
-    }
-
-    Ok(false)
-}
-
-fn materialization_requested(ctx: &Context, cli_requested: bool) -> Result<bool, String> {
-    materialization_requested_with_env(ctx, cli_requested, std::env::var_os(MATERIALIZE_ENV))
-}
-
-/// `materialization_requested` with the ambient `CUDA_OXIDE_MATERIALIZE_CUBIN`
-/// injected.
-///
-/// The process value outranks project config, so resolution has to be
-/// injectable for unit tests: an exported value would otherwise turn
-/// materialization on for tests that pass `materialize_cubin: false`, sending
-/// them into `discover_materializer_provenance`. Same rationale as
-/// `nvvm_ir_requested_with_env`.
-fn materialization_requested_with_env(
-    ctx: &Context,
-    cli_requested: bool,
-    env_value: Option<std::ffi::OsString>,
-) -> Result<bool, String> {
-    if cli_requested {
-        return Ok(true);
-    }
-
-    if let Some(value) = env_value {
-        let value = value
-            .into_string()
-            .map_err(|_| format!("{MATERIALIZE_ENV} is not valid Unicode"))?;
-        return parse_strict_bool(MATERIALIZE_ENV, &value);
-    }
-
-    if let Some(value) = project_config_env(ctx, MATERIALIZE_ENV) {
-        return parse_strict_bool(MATERIALIZE_ENV, value);
-    }
-
-    Ok(false)
-}
-
-fn prepare_materialization_result(
-    ctx: &Context,
-    cli_requested: bool,
-    cli_arch: Option<&str>,
-    emit_nvvm_ir: bool,
-) -> Result<MaterializationMode, String> {
-    prepare_materialization_result_with_env(
-        ctx,
-        cli_requested,
-        cli_arch,
-        emit_nvvm_ir,
-        std::env::var_os(MATERIALIZE_ENV),
-    )
-}
-
-/// `prepare_materialization_result` with the ambient
-/// `CUDA_OXIDE_MATERIALIZE_CUBIN` injected, forwarded to
-/// `materialization_requested_with_env`.
-fn prepare_materialization_result_with_env(
-    ctx: &Context,
-    cli_requested: bool,
-    cli_arch: Option<&str>,
-    emit_nvvm_ir: bool,
-    materialize_env: Option<std::ffi::OsString>,
-) -> Result<MaterializationMode, String> {
-    let enabled = materialization_requested_with_env(ctx, cli_requested, materialize_env)?;
-    if !enabled {
-        return Ok(MaterializationMode::default());
-    }
-    if emit_nvvm_ir {
-        return Err(
-            "--materialize-cubin cannot be combined with --emit-nvvm-ir; one requests a final cubin and the other requests NVVM IR"
-                .to_string(),
-        );
-    }
-
-    let arch = configured_arch_label(ctx, cli_arch).ok_or_else(|| {
-        "--materialize-cubin requires --arch, CUDA_OXIDE_TARGET, or a configured default-arch"
-            .to_string()
-    })?;
-    let _: cuda_artifact_finalizer::CudaArch = arch
-        .parse()
-        .map_err(|error| format!("invalid materialization target {arch:?}: {error}"))?;
-
-    let handshake = discover_materializer_handshake(ctx)?;
-    let handshake_json = serde_json::to_string(&handshake)
-        .map_err(|error| format!("could not encode materializer handshake: {error}"))?;
-    Ok(MaterializationMode {
-        prepared: Some(PreparedMaterialization {
-            provenance_sha256_hex: digest_hex(&handshake.provenance_sha256),
-            tool_identity_handshake_json: handshake_json,
-        }),
-    })
-}
-
-fn discover_materializer_handshake(
-    ctx: &Context,
-) -> Result<cuda_artifact_finalizer::MaterializerHandshakeV1, String> {
-    let executable = std::env::current_exe()
-        .map_err(|error| format!("could not locate cargo-oxide executable: {error}"))?;
-    let mut command = materializer_discovery_command(ctx, &executable);
-    if let Some(cached) = read_materializer_handshake_cache(ctx) {
-        command.env(MATERIALIZER_HANDSHAKE_ENV, cached);
-    }
-    let output = command
-        .output()
-        .map_err(|error| format!("could not start CUDA materializer discovery: {error}"))?;
-    if !output.status.success() {
-        let stderr = String::from_utf8_lossy(&output.stderr);
-        return Err(format!(
-            "CUDA materializer discovery failed: {}",
-            stderr.trim()
-        ));
-    }
-    let handshake = String::from_utf8(output.stdout)
-        .map_err(|_| "CUDA materializer discovery returned non-UTF-8 output".to_string())?;
-    let handshake: cuda_artifact_finalizer::MaterializerHandshakeV1 =
-        serde_json::from_str(handshake.trim()).map_err(|error| {
-            format!("CUDA materializer discovery returned an invalid v1 handshake: {error}")
-        })?;
-    if !handshake.has_consistent_provenance() {
-        return Err(format!(
-            "CUDA materializer discovery returned an inconsistent handshake version {}",
-            handshake.version
-        ));
-    }
-    write_materializer_handshake_cache(ctx, &handshake);
-    Ok(handshake)
-}
-
-fn materializer_discovery_command(ctx: &Context, executable: &Path) -> Command {
-    let mut command = Command::new(executable);
-    command.arg("__materializer-handshake");
-    apply_config_env(&mut command, ctx);
-    apply_ld_library_path(&mut command, ctx);
-    // Only the local cache explicitly installed by the caller may seed the
-    // helper; never consume an inherited or project-provided internal value.
-    command.env_remove(MATERIALIZER_HANDSHAKE_ENV);
-    command
-}
-
-fn materializer_handshake_cache_path(ctx: &Context) -> PathBuf {
-    ctx.workspace_root.join(MATERIALIZER_HANDSHAKE_CACHE)
-}
-
-fn read_materializer_handshake_cache(ctx: &Context) -> Option<String> {
-    let json = fs::read_to_string(materializer_handshake_cache_path(ctx)).ok()?;
-    let handshake: cuda_artifact_finalizer::MaterializerHandshakeV1 =
-        serde_json::from_str(json.trim()).ok()?;
-    handshake.has_consistent_provenance().then_some(json)
-}
-
-fn write_materializer_handshake_cache(
-    ctx: &Context,
-    handshake: &cuda_artifact_finalizer::MaterializerHandshakeV1,
-) {
-    let path = materializer_handshake_cache_path(ctx);
-    let Some(parent) = path.parent() else {
-        return;
-    };
-    if fs::create_dir_all(parent).is_err() {
-        return;
-    }
-    let Ok(json) = serde_json::to_string(handshake) else {
-        return;
-    };
-    let temporary = parent.join(format!("v1.{}.tmp", std::process::id()));
-    if fs::write(&temporary, json).is_ok() {
-        let _ = fs::rename(&temporary, &path);
-    }
-}
-
-pub fn print_materializer_handshake() {
-    let cached = std::env::var(MATERIALIZER_HANDSHAKE_ENV)
-        .ok()
-        .and_then(|json| serde_json::from_str(&json).ok())
-        .filter(cuda_artifact_finalizer::MaterializerHandshakeV1::has_consistent_provenance);
-    let finalizer = cached
-        .as_ref()
-        .map_or_else(
-            cuda_artifact_finalizer::Finalizer::discover,
-            cuda_artifact_finalizer::Finalizer::discover_with_handshake,
-        )
-        .unwrap_or_else(|error| {
-            eprintln!("could not discover CUDA artifact finalizer: {error}");
-            std::process::exit(1);
-        });
-    let handshake = finalizer.materializer_handshake().unwrap_or_else(|| {
-        eprintln!(
-            "the loaded libNVVM or nvJitLink library cannot be tied to an exact file; refusing materialization because Cargo could not fingerprint the compiler inputs"
-        );
-        std::process::exit(1);
-    });
-    println!(
-        "{}",
-        serde_json::to_string(&handshake).unwrap_or_else(|error| {
-            eprintln!("could not encode CUDA materializer handshake: {error}");
-            std::process::exit(1);
-        })
-    );
-}
-
-fn parse_strict_bool(name: &str, value: &str) -> Result<bool, String> {
-    match value.trim().to_ascii_lowercase().as_str() {
-        "1" | "true" | "yes" | "on" => Ok(true),
-        "0" | "false" | "no" | "off" => Ok(false),
-        _ => Err(format!(
-            "{name} must be a boolean (accepted true values: 1, true, yes, on; false values: 0, false, no, off), got {value:?}"
-        )),
-    }
-}
-
-fn digest_hex(digest: &[u8; 32]) -> String {
-    use std::fmt::Write;
-    let mut hex = String::with_capacity(64);
-    for byte in digest {
-        write!(&mut hex, "{byte:02x}").expect("writing to String cannot fail");
-    }
-    hex
-}
-
-/// Project-local cuda-oxide defaults loaded from `.cargo/cuda-oxide.toml`.
-#[derive(Debug, Clone, Default, PartialEq, Eq)]
-pub struct OxideConfig {
-    /// Explicit backend shared object path.
-    pub backend: Option<PathBuf>,
-    /// Default CUDA architecture for codegen commands.
-    pub default_arch: Option<String>,
-    /// Additional rustflags appended after cuda-oxide's required flags.
-    pub extra_rustflags: Vec<String>,
-    /// Environment variables applied to child Cargo invocations.
-    pub env: Vec<(String, String)>,
-}
-
-/// Pre-resolved context shared across all commands.
-///
-/// Built once at startup by [`resolve_context`] and passed by reference to
-/// every command handler. Avoids repeated filesystem walks and backend builds.
-pub struct Context {
-    /// Absolute path to the workspace root (contains top-level `Cargo.toml`).
-    pub workspace_root: PathBuf,
-    /// Path to `crates/rustc-codegen-cuda` (backend source tree).
-    pub codegen_crate: PathBuf,
-    /// Path to `crates/rustc-codegen-cuda/examples/`.
-    pub examples_dir: PathBuf,
-    /// Path to the built `librustc_codegen_cuda.so` shared object.
-    pub backend_so: PathBuf,
-    /// True when running from inside the cuda-oxide workspace; false for
-    /// standalone projects scaffolded by `cargo oxide new`.
-    pub is_workspace: bool,
-    /// Project-local cuda-oxide defaults.
-    pub config: OxideConfig,
-}
-
-/// Resolve the workspace root and backend, or exit with a helpful error.
-///
-/// Supports two modes:
-/// - **Workspace mode**: CWD is inside the cuda-oxide repo (detected by
-///   `crates/rustc-codegen-cuda` directory). Examples are resolved from the
-///   workspace examples directory.
-/// - **Standalone mode**: CWD has a `Cargo.toml` but is not inside the
-///   workspace. The backend is located via cache or auto-fetch. Commands
-///   like `run` operate on the current directory directly.
-pub fn resolve_context() -> Context {
-    if let Some(workspace_root) = backend::find_workspace_root() {
-        let codegen_crate = workspace_root.join("crates/rustc-codegen-cuda");
-        let examples_dir = codegen_crate.join("examples");
-        let config = load_oxide_config(&workspace_root);
-        let backend_so = backend::find_or_build_backend(&workspace_root, config.backend.as_deref());
-        return Context {
-            workspace_root,
-            codegen_crate,
-            examples_dir,
-            backend_so,
-            is_workspace: true,
-            config,
-        };
-    }
-
-    let cwd = std::env::current_dir().unwrap_or_else(|e| {
-        eprintln!("Error: cannot determine current directory: {}", e);
-        std::process::exit(1);
-    });
-
-    if cwd.join("Cargo.toml").is_file() {
-        let config = load_oxide_config(&cwd);
-        let backend_so = backend::find_or_build_backend(&cwd, config.backend.as_deref());
-        return Context {
-            workspace_root: cwd.clone(),
-            codegen_crate: cwd.clone(),
-            examples_dir: cwd.clone(),
-            backend_so,
-            is_workspace: false,
-            config,
-        };
-    }
-
-    eprintln!("Error: Could not find cuda-oxide workspace or a standalone Cargo.toml.");
-    eprintln!();
-    eprintln!("Run from inside the cuda-oxide repository, or from a project created");
-    eprintln!("with `cargo oxide new <name>`.");
-    std::process::exit(1);
-}
-
-/// Resolve a context for commands that must not build or fetch the backend.
-///
-/// Identical discovery to [`resolve_context`], except the backend `.so` is
-/// only located via [`backend::backend_so_candidate`], never built and never
-/// cloned, and an invalid `.cargo/cuda-oxide.toml` degrades to defaults with
-/// a warning instead of exiting (so `doctor` can report it as a failed
-/// check). Passive commands such as `doctor` and `clean` must remain usable
-/// without triggering backend setup or network access.
-/// `run`/`build`/`pipeline`/`setup` still build the backend on demand.
-pub fn resolve_passive_context() -> Context {
-    if let Some(workspace_root) = backend::find_workspace_root() {
-        let codegen_crate = workspace_root.join("crates/rustc-codegen-cuda");
-        let examples_dir = codegen_crate.join("examples");
-        let config = load_oxide_config_lenient(&workspace_root);
-        let backend_so = backend::backend_so_candidate(&workspace_root, config.backend.as_deref());
-        return Context {
-            workspace_root,
-            codegen_crate,
-            examples_dir,
-            backend_so,
-            is_workspace: true,
-            config,
-        };
-    }
-
-    let cwd = std::env::current_dir().unwrap_or_else(|e| {
-        eprintln!("Error: cannot determine current directory: {}", e);
-        std::process::exit(1);
-    });
-
-    if cwd.join("Cargo.toml").is_file() {
-        let config = load_oxide_config_lenient(&cwd);
-        let backend_so = backend::backend_so_candidate(&cwd, config.backend.as_deref());
-        return Context {
-            workspace_root: cwd.clone(),
-            codegen_crate: cwd.clone(),
-            examples_dir: cwd.clone(),
-            backend_so,
-            is_workspace: false,
-            config,
-        };
-    }
-
-    eprintln!("Error: Could not find cuda-oxide workspace or a standalone Cargo.toml.");
-    eprintln!();
-    eprintln!("Run from inside the cuda-oxide repository, or from a project created");
-    eprintln!("with `cargo oxide new <name>`.");
-    std::process::exit(1);
-}
-
-#[derive(Debug, Clone, Eq, PartialEq)]
-struct ExampleInfo {
-    name: String,
-    title: String,
-    description: String,
-    requirements: Vec<String>,
-}
-
-#[derive(Debug, Default, Eq, PartialEq)]
-struct ParsedReadme {
-    title: Option<String>,
-    description: Option<String>,
-    requirements: Vec<String>,
-}
-
-#[derive(Debug, Default, Eq, PartialEq)]
-struct ManifestInfo {
-    description: Option<String>,
-}
-
-pub fn list_examples(ctx: &Context, json: bool) {
-    if !ctx.is_workspace {
-        eprintln!("Error: `cargo oxide list` must be run from inside a cuda-oxide checkout.");
-        eprintln!();
-        eprintln!("The command lists examples under crates/rustc-codegen-cuda/examples/.");
-        std::process::exit(1);
-    }
-
-    let examples = discover_examples(&ctx.examples_dir).unwrap_or_else(|error| {
-        eprintln!("Error: {error}");
-        std::process::exit(1);
-    });
-
-    let output = if json {
-        format_examples_json(&examples).unwrap_or_else(|error| {
-            eprintln!("Error: could not serialize example list: {error}");
-            std::process::exit(1);
-        })
-    } else {
-        format_examples_human(&examples)
-    };
-
-    print!("{output}");
-}
-
-fn discover_examples(examples_dir: &Path) -> Result<Vec<ExampleInfo>, String> {
-    let entries = fs::read_dir(examples_dir).map_err(|error| {
-        format!(
-            "could not read examples directory {}: {error}",
-            examples_dir.display()
-        )
-    })?;
-
-    let mut examples = Vec::new();
-
-    for entry in entries {
-        let entry = entry.map_err(|error| {
-            format!(
-                "could not read an entry under {}: {error}",
-                examples_dir.display()
-            )
-        })?;
-
-        let file_type = entry
-            .file_type()
-            .map_err(|error| format!("could not inspect {}: {error}", entry.path().display()))?;
-
-        if !file_type.is_dir() {
-            continue;
-        }
-
-        let example_dir = entry.path();
-        let name = entry.file_name().into_string().map_err(|name| {
-            format!(
-                "example directory name is not valid UTF-8: {}",
-                name.to_string_lossy()
-            )
-        })?;
-
-        // A directory without a manifest is not an example (scratch dirs,
-        // checked-out tooling, ...). Skip it instead of failing the listing.
-        let manifest_path = example_dir.join("Cargo.toml");
-        if !manifest_path.is_file() {
-            eprintln!(
-                "Warning: skipping {}: no top-level Cargo.toml",
-                example_dir.display()
-            );
-            continue;
-        }
-
-        let manifest = parse_example_manifest(&manifest_path)?;
-
-        let readme_path = example_dir.join("README.md");
-        let parsed_readme = if readme_path.is_file() {
-            let contents = fs::read_to_string(&readme_path)
-                .map_err(|error| format!("could not read {}: {error}", readme_path.display()))?;
-            parse_example_readme(&name, &contents)
-        } else {
-            ParsedReadme::default()
-        };
-
-        let ParsedReadme {
-            title,
-            description,
-            requirements,
-        } = parsed_readme;
-
-        let title = title.unwrap_or_else(|| name.clone());
-
-        let description = description.or(manifest.description).unwrap_or_else(|| {
-            if title != name {
-                title.clone()
-            } else {
-                "No description documented.".to_string()
-            }
-        });
-
-        examples.push(ExampleInfo {
-            name,
-            title,
-            description,
-            requirements,
-        });
-    }
-
-    examples.sort_by(|left, right| left.name.cmp(&right.name));
-
-    if examples.is_empty() {
-        return Err(format!(
-            "no examples found under {}",
-            examples_dir.display()
-        ));
-    }
-
-    Ok(examples)
-}
-
-fn parse_example_manifest(path: &Path) -> Result<ManifestInfo, String> {
-    let contents = fs::read_to_string(path)
-        .map_err(|error| format!("could not read {}: {error}", path.display()))?;
-
-    let manifest: toml::Value = toml::from_str(&contents)
-        .map_err(|error| format!("could not parse {}: {error}", path.display()))?;
-
-    let package = manifest
-        .get("package")
-        .and_then(toml::Value::as_table)
-        .ok_or_else(|| format!("{} has no [package] table", path.display()))?;
-
-    let description = package
-        .get("description")
-        .and_then(toml::Value::as_str)
-        .map(str::trim)
-        .filter(|description| !description.is_empty())
-        .map(str::to_owned);
-
-    Ok(ManifestInfo { description })
-}
-
-fn parse_example_readme(crate_name: &str, contents: &str) -> ParsedReadme {
-    let lines: Vec<&str> = contents.lines().collect();
-    let mut headings = Vec::new();
-    let mut in_code_fence = false;
-
-    for (index, line) in lines.iter().enumerate() {
-        if is_code_fence(line) {
-            in_code_fence = !in_code_fence;
-            continue;
-        }
-
-        if in_code_fence {
-            continue;
-        }
-
-        if let Some((level, title)) = parse_markdown_heading(line) {
-            headings.push((index, level, title));
-        }
-    }
-
-    let crate_heading = normalize_heading(crate_name);
-
-    let selected_heading = match headings.first() {
-        Some(first) if normalize_heading(&first.2) == crate_heading => headings
-            .get(1)
-            .filter(|heading| {
-                heading.1 == 2
-                    && first_prose_paragraph_in_range(&lines, first.0 + 1, heading.0).is_none()
-                    && !is_generic_section_heading(&normalize_heading(&heading.2))
-            })
-            .or(Some(first)),
-        Some(first) => Some(first),
-        None => None,
-    };
-
-    let title = selected_heading
-        .map(|(_, _, title)| strip_inline_markdown(title))
-        .filter(|title| !title.is_empty());
-
-    let description_start = selected_heading.map(|(index, _, _)| index + 1).unwrap_or(0);
-
-    let description_end = headings
-        .iter()
-        .find(|(index, _, _)| *index >= description_start)
-        .map(|(index, _, _)| *index)
-        .unwrap_or(lines.len());
-
-    let description = first_prose_paragraph_in_range(&lines, description_start, description_end);
-    let requirements = extract_requirements(&lines);
-
-    ParsedReadme {
-        title,
-        description,
-        requirements,
-    }
-}
-
-fn parse_markdown_heading(line: &str) -> Option<(usize, String)> {
-    let trimmed = line.trim_start();
-    let level = trimmed.bytes().take_while(|byte| *byte == b'#').count();
-
-    if !(1..=6).contains(&level) {
-        return None;
-    }
-
-    let remainder = &trimmed[level..];
-    if !remainder.chars().next().is_some_and(char::is_whitespace) {
-        return None;
-    }
-
-    let title = remainder.trim().trim_end_matches('#').trim();
-
-    if title.is_empty() {
-        None
-    } else {
-        Some((level, title.to_string()))
-    }
-}
-
-fn is_code_fence(line: &str) -> bool {
-    let trimmed = line.trim_start();
-    trimmed.starts_with("```") || trimmed.starts_with("~~~")
-}
-
-fn strip_inline_markdown(value: &str) -> String {
-    value
-        .replace("**", "")
-        .replace("__", "")
-        .replace('`', "")
-        .trim()
-        .to_string()
-}
-
-fn normalize_heading(value: &str) -> String {
-    strip_inline_markdown(value)
-        .trim_matches(|character: char| {
-            character == ':' || character == '-' || character.is_whitespace()
-        })
-        .to_ascii_lowercase()
-}
-
-fn is_generic_section_heading(heading: &str) -> bool {
-    matches!(
-        heading,
-        "overview"
-            | "what this example does"
-            | "key concepts"
-            | "key concepts demonstrated"
-            | "build"
-            | "build and run"
-            | "usage"
-            | "expected output"
-            | "requirements"
-            | "hardware requirements"
-            | "prerequisites"
-            | "potential errors"
-            | "how it works"
-            | "how it works under the hood"
-            | "generated ptx"
-            | "run"
-            | "test"
-            | "tests"
-            | "correctness"
-            | "trigger"
-            | "kernels"
-            | "features tested"
-            | "what this tests"
-            | "what it tests"
-            | "what this demonstrates"
-            | "why this exists"
-            | "the bug"
-            | "final design"
-    )
-}
-
-fn first_prose_paragraph_in_range(lines: &[&str], start: usize, end: usize) -> Option<String> {
-    let end = end.min(lines.len());
-    let start = start.min(end);
-    let mut paragraph = Vec::new();
-    let mut in_code_fence = false;
-
-    for line in &lines[start..end] {
-        if is_code_fence(line) {
-            if !paragraph.is_empty() {
-                break;
-            }
-            in_code_fence = !in_code_fence;
-            continue;
-        }
-
-        if in_code_fence {
-            continue;
-        }
-
-        let trimmed = line.trim();
-
-        if parse_markdown_heading(trimmed).is_some() {
-            break;
-        }
-
-        if trimmed.is_empty() {
-            if !paragraph.is_empty() {
-                break;
-            }
-            continue;
-        }
-
-        if is_non_prose_markdown(trimmed) {
-            if !paragraph.is_empty() {
-                break;
-            }
-            continue;
-        }
-
-        paragraph.push(trimmed);
-    }
-
-    if paragraph.is_empty() {
-        None
-    } else {
-        Some(paragraph.join(" "))
-    }
-}
-
-fn is_non_prose_markdown(line: &str) -> bool {
-    line.starts_with("- ")
-        || line.starts_with("* ")
-        || line.starts_with("+ ")
-        || line.starts_with('>')
-        || line.starts_with('|')
-        || line.starts_with("![")
-        || line.starts_with("<!--")
-        || is_ordered_list_item(line)
-}
-
-fn is_ordered_list_item(line: &str) -> bool {
-    strip_ordered_list_marker(line).is_some()
-}
-
-/// Strip a `1. ` / `42. ` ordered-list marker, returning the item text.
-fn strip_ordered_list_marker(line: &str) -> Option<&str> {
-    let (marker, item) = line.split_once(". ")?;
-    if !marker.is_empty() && marker.bytes().all(|byte| byte.is_ascii_digit()) {
-        Some(item.trim_start())
-    } else {
-        None
-    }
-}
-
-/// Collect the requirement entries documented under a requirements-style
-/// heading ([`is_requirements_heading`]).
-///
-/// Recognized forms:
-/// - unordered list items (`- ` / `* ` / `+ `), with indented
-///   wrap-continuation lines joined onto the item;
-/// - ordered list items (`1. `), same continuation rule;
-/// - two-column markdown tables, emitted as `name: value` per data row.
-///
-/// Tables with any other column count are skipped whole: without knowing
-/// which columns carry the requirement, half-parsing them would produce
-/// garbage entries.
-fn extract_requirements(lines: &[&str]) -> Vec<String> {
-    let mut requirements = Vec::new();
-    let mut current_requirement: Option<String> = None;
-    let mut table_rows: Vec<Vec<String>> = Vec::new();
-    let mut requirement_level = None;
-    let mut in_code_fence = false;
-
-    for line in lines {
-        if is_code_fence(line) {
-            if let Some(requirement) = current_requirement.take() {
-                requirements.push(requirement);
-            }
-            flush_requirement_table(&mut table_rows, &mut requirements);
-            in_code_fence = !in_code_fence;
-            continue;
-        }
-
-        if in_code_fence {
-            continue;
-        }
-
-        if let Some((level, heading)) = parse_markdown_heading(line) {
-            if let Some(requirement) = current_requirement.take() {
-                requirements.push(requirement);
-            }
-            flush_requirement_table(&mut table_rows, &mut requirements);
-
-            let normalized = normalize_heading(&heading);
-
-            if is_requirements_heading(&normalized) {
-                requirement_level = Some(level);
-            } else if requirement_level.is_some_and(|active| level <= active) {
-                requirement_level = None;
-            }
-
-            continue;
-        }
-
-        if requirement_level.is_none() {
-            continue;
-        }
-
-        let trimmed = line.trim();
-
-        // A blank line terminates the current list item or table. Whatever
-        // follows is a new paragraph (prose, a code fence, ...), not a
-        // wrapped continuation of the bullet above it.
-        if trimmed.is_empty() {
-            if let Some(requirement) = current_requirement.take() {
-                requirements.push(requirement);
-            }
-            flush_requirement_table(&mut table_rows, &mut requirements);
-            continue;
-        }
-
-        if trimmed.starts_with('|') {
-            if let Some(requirement) = current_requirement.take() {
-                requirements.push(requirement);
-            }
-            table_rows.push(split_table_row(trimmed));
-            continue;
-        }
-        flush_requirement_table(&mut table_rows, &mut requirements);
-
-        let item = trimmed
-            .strip_prefix("- ")
-            .or_else(|| trimmed.strip_prefix("* "))
-            .or_else(|| trimmed.strip_prefix("+ "))
-            .or_else(|| strip_ordered_list_marker(trimmed));
-
-        if let Some(item) = item {
-            if let Some(requirement) = current_requirement.take() {
-                requirements.push(requirement);
-            }
-
-            let item = strip_inline_markdown(item);
-            if !item.is_empty() {
-                current_requirement = Some(item);
-            }
-        } else if let Some(requirement) = &mut current_requirement {
-            requirement.push(' ');
-            requirement.push_str(&strip_inline_markdown(trimmed));
-        }
-    }
-
-    if let Some(requirement) = current_requirement {
-        requirements.push(requirement);
-    }
-    flush_requirement_table(&mut table_rows, &mut requirements);
-
-    requirements.dedup();
-    requirements
-}
-
-/// Split a markdown table row into trimmed cells, honoring `\|` escapes and
-/// dropping the empty leading/trailing cells produced by the outer pipes.
-fn split_table_row(row: &str) -> Vec<String> {
-    let mut cells = Vec::new();
-    let mut cell = String::new();
-    let mut characters = row.chars().peekable();
-
-    while let Some(character) = characters.next() {
-        match character {
-            '\\' if characters.peek() == Some(&'|') => {
-                cell.push('|');
-                characters.next();
-            }
-            '|' => {
-                cells.push(cell.trim().to_string());
-                cell.clear();
-            }
-            _ => cell.push(character),
-        }
-    }
-    cells.push(cell.trim().to_string());
-
-    if cells.first().is_some_and(|first| first.is_empty()) {
-        cells.remove(0);
-    }
-    if cells.last().is_some_and(|last| last.is_empty()) {
-        cells.pop();
-    }
-
-    cells
-}
-
-/// The `|---|:---:|` row separating a table header from its data rows.
-fn is_table_separator_row(cells: &[String]) -> bool {
-    !cells.is_empty()
-        && cells.iter().all(|cell| {
-            !cell.is_empty()
-                && cell
-                    .chars()
-                    .all(|character| character == '-' || character == ':')
-        })
-}
-
-/// Convert a buffered `| name | value |` requirements table into one
-/// `name: value` entry per data row. Tables whose header or data rows are
-/// not exactly two columns are dropped whole rather than half-parsed.
-fn flush_requirement_table(table_rows: &mut Vec<Vec<String>>, requirements: &mut Vec<String>) {
-    let rows = std::mem::take(table_rows);
-
-    // Header, separator, and at least one data row.
-    if rows.len() < 3 || !is_table_separator_row(&rows[1]) {
-        return;
-    }
-
-    if !rows.iter().all(|row| row.len() == 2) {
-        return;
-    }
-
-    for row in &rows[2..] {
-        let name = strip_inline_markdown(&row[0]);
-        let value = strip_inline_markdown(&row[1]);
-        if !name.is_empty() && !value.is_empty() {
-            requirements.push(format!("{name}: {value}"));
-        }
-    }
-}
-
-fn is_requirements_heading(heading: &str) -> bool {
-    matches!(
-        heading,
-        "requirements"
-            | "hardware requirements"
-            | "software requirements"
-            | "system requirements"
-            | "toolkit requirements"
-            | "build requirements"
-            | "prerequisites"
-    )
-}
-
-fn format_examples_human(examples: &[ExampleInfo]) -> String {
-    let mut output = String::new();
-
-    for (index, example) in examples.iter().enumerate() {
-        if index != 0 {
-            output.push('\n');
-        }
-
-        output.push_str(&example.name);
-        output.push('\n');
-
-        if example.title != example.name {
-            output.push_str("  ");
-            output.push_str(&example.title);
-            output.push('\n');
-        }
-
-        output.push_str("  ");
-        output.push_str(&example.description);
-        output.push('\n');
-
-        if !example.requirements.is_empty() {
-            output.push_str("  Requirements:\n");
-            for requirement in &example.requirements {
-                output.push_str("    - ");
-                output.push_str(requirement);
-                output.push('\n');
-            }
-        }
-    }
-
-    output
-}
-
-fn format_examples_json(examples: &[ExampleInfo]) -> Result<String, serde_json::Error> {
-    let examples = examples
-        .iter()
-        .map(|example| {
-            serde_json::json!({
-                "name": example.name,
-                "title": example.title,
-                "description": example.description,
-                "requirements": example.requirements,
-            })
-        })
-        .collect::<Vec<_>>();
-
-    let document = serde_json::json!({
-        "schema_version": 1,
-        "examples": examples,
-    });
-
-    let mut output = serde_json::to_string_pretty(&document)?;
-    output.push('\n');
-    Ok(output)
-}
-
-// =============================================================================
-// Run command
-// =============================================================================
-
-/// Build and run an example with the custom codegen backend.
-///
-/// Cleans stale artifacts, sets encoded rustc flags to point at the backend `.so`,
-/// and invokes `cargo run --release` from the example directory. Environment
-/// variables control output format (PTX / NVVM IR) and verbosity. Trailing
-/// `app_args` are forwarded to the example binary after `--`.
-#[allow(clippy::too_many_arguments)]
-pub fn codegen_run(
-    ctx: &Context,
-    example: &str,
-    verbose: bool,
-    emit_nvvm_ir: bool,
-    arch: Option<&str>,
-    features: Option<&str>,
-    device_features: Option<&str>,
-    bin: Option<&str>,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-    materialize_cubin: bool,
-    app_args: &[String],
-) {
-    let example_dir = if ctx.is_workspace {
-        resolve_example_dir(ctx, example)
-    } else {
-        ctx.workspace_root.clone()
-    };
-
-    let interop = load_interop_config(&example_dir);
-
-    let output_format = format_label(emit_nvvm_ir);
-    let target_arch = configured_arch(ctx, arch);
-    let materialization = prepare_materialization(ctx, materialize_cubin, arch, emit_nvvm_ir);
-    // Target precedence for `cargo oxide run` (highest first):
-    //   1. --arch <sm_XX>            explicit user override   -> CUDA_OXIDE_TARGET
-    //   2. CUDA_OXIDE_TARGET=<sm_XX> explicit env override (from the parent)
-    //   3. detected GPU arch (via nvidia-smi) -> CUDA_OXIDE_DEVICE_ARCH (a hint)
-    //   4. backend feature-based default (`select_target` in mir-importer)
-    //
-    // Slot 3 is a HINT, not an override: the backend builds for the detected
-    // GPU only when that GPU can run the kernel. If the kernel needs a newer
-    // arch (tcgen05 needs sm_100a even on a consumer sm_120 GPU), the backend
-    // builds for the required arch and the module simply skips at load time.
-    // We only detect for `run`, not `build`/`pipeline`: `run` loads the cubin
-    // on the local GPU, whereas those may legitimately cross-compile for
-    // another machine.
-    let detected_device_arch =
-        detect_run_target_arch(target_arch, emit_nvvm_ir || materialization.enabled());
-
-    if let Some(interop) = interop.filter(|config| !config.device_crates.is_empty()) {
-        codegen_run_interop(
-            ctx,
-            example,
-            &example_dir,
-            &interop,
-            verbose,
-            emit_nvvm_ir,
-            target_arch,
-            detected_device_arch.as_deref(),
-            features,
-            device_features,
-            bin,
-            no_fmad,
-            unchecked_indexing,
-            &materialization,
-            app_args,
-        );
-        return;
-    }
-    if device_features.is_some() {
-        eprintln!("Error: --device-features requires metadata-declared interop device crates.");
-        std::process::exit(2);
-    }
-
-    clean_generated_files(&example_dir, example);
-
-    println!("=========================================");
-    println!("RUSTC-CODEGEN-CUDA: {}", example);
-    println!("=========================================");
-    println!();
-    if materialization.enabled() {
-        println!("Output format: materialized cubin");
-        println!(
-            "Target arch: {}",
-            configured_arch_label(ctx, arch)
-                .expect("materialization requires a configured architecture")
-        );
-        println!();
-    } else if emit_nvvm_ir {
-        println!("Output format: {}", output_format);
-        println!(
-            "Target arch: {}",
-            configured_arch_label(ctx, arch)
-                .expect("--emit-nvvm-ir requires a configured architecture")
-        );
-        println!();
-    } else if let Some(dev) = detected_device_arch.as_deref() {
-        // Surface the detected GPU so it isn't silent magic. It is a hint, not
-        // a hard target: the backend builds for it unless a kernel needs a
-        // newer arch (e.g. tcgen05 forces sm_100a even on a consumer sm_120
-        // GPU), so the final PTX target may differ.
-        println!("Detected GPU arch: {dev} (via nvidia-smi)");
-        println!();
-    }
-    println!("This is the proper cargo workflow:");
-    println!("  CARGO_ENCODED_RUSTFLAGS=<cuda-oxide flags> cargo run");
-    println!();
-
-    touch_main_rs(&example_dir);
-
-    let mut cmd = Command::new("cargo");
-    cmd.args(["run", "--release"]).current_dir(&example_dir);
-
-    if let Some(bin) = bin {
-        cmd.args(["--bin", bin]);
-    }
-    if let Some(features) = features {
-        cmd.args(["--features", features]);
-    }
-    if !app_args.is_empty() {
-        cmd.arg("--").args(app_args);
-    }
-
-    apply_common_codegen_env(
-        &mut cmd,
-        ctx,
-        verbose,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-    );
-    let fingerprint = standard_codegen_fingerprint(
-        ctx,
-        verbose,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-        emit_nvvm_ir,
-        target_arch,
-        detected_device_arch.as_deref(),
-        &materialization,
-    );
-    apply_codegen_configuration_or_exit(
-        &mut cmd,
-        ctx,
-        CodegenProfilePolicy::ReleaseLike,
-        &[],
-        &fingerprint,
-    );
-    apply_output_mode(&mut cmd, emit_nvvm_ir, target_arch, &materialization);
-    apply_device_arch_hint(&mut cmd, target_arch, detected_device_arch.as_deref());
-
-    if let Some(bin) = bin {
-        println!("Building and running {} (bin: {})...", example, bin);
-    } else {
-        println!("Building and running {}...", example);
-    }
-    println!();
-
-    let status = cmd.status().expect("Failed to run cargo");
-    if !status.success() {
-        eprintln!("\nFailed with exit code: {:?}", status.code());
-        std::process::exit(status.code().unwrap_or(1));
-    }
-}
-
-// =============================================================================
-// Sanitize command
-// =============================================================================
-
-/// Build an example and run the produced host binary under NVIDIA Compute
-/// Sanitizer.
-#[allow(clippy::too_many_arguments)]
-pub fn codegen_sanitize(
-    ctx: &Context,
-    example: &str,
-    tool: &str,
-    sanitizer_args: &[String],
-    application_args: &[String],
-    verbose: bool,
-    arch: Option<&str>,
-    features: Option<&str>,
-    bin: Option<&str>,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-    materialize_cubin: bool,
-) {
-    let example_dir = if ctx.is_workspace {
-        resolve_example_dir(ctx, example)
-    } else {
-        ctx.workspace_root.clone()
-    };
-
-    let interop = load_interop_config(&example_dir);
-    let target_arch = configured_arch(ctx, arch);
-    let materialization = prepare_materialization(ctx, materialize_cubin, arch, false);
-    let detected_device_arch = detect_run_target_arch(target_arch, materialization.enabled());
-
-    if let Some(interop) = interop.filter(|config| !config.device_crates.is_empty()) {
-        reject_interop_output_mode(false, &materialization);
-        println!("=========================================");
-        println!("RUSTC-CODEGEN-CUDA SANITIZE INTEROP: {}", example);
-        println!("=========================================");
-        if let Some(kind) = &interop.kind {
-            println!("Interop kind: {}", kind);
-        }
-        if let Some(dev) = detected_device_arch.as_deref() {
-            println!("Detected GPU arch: {dev} (via nvidia-smi)");
-        }
-        println!("Compute Sanitizer tool: {tool}");
-        println!();
-
-        build_interop_device_crates(
-            ctx,
-            &example_dir,
-            &interop,
-            verbose,
-            target_arch,
-            detected_device_arch.as_deref(),
-            None,
-            InteropDeviceBuildOptions {
-                no_fmad,
-                unchecked_indexing,
-                sanitizer_line_tables: true,
-            },
-            &materialization,
-        );
-        let binary = build_host_cargo(ctx, example, &example_dir, features, bin, verbose);
-        run_compute_sanitizer(
-            ctx,
-            &example_dir,
-            tool,
-            sanitizer_args,
-            application_args,
-            &binary,
-        );
-        return;
-    }
-
-    clean_generated_files(&example_dir, example);
-
-    println!("=========================================");
-    println!("RUSTC-CODEGEN-CUDA SANITIZE: {}", example);
-    println!("=========================================");
-    if let Some(dev) = detected_device_arch.as_deref() {
-        println!("Detected GPU arch: {dev} (via nvidia-smi)");
-    }
-    println!("Compute Sanitizer tool: {tool}");
-    println!();
-
-    touch_main_rs(&example_dir);
-    let binary = codegen_build_host_binary(
-        ctx,
-        example,
-        &example_dir,
-        verbose,
-        target_arch,
-        detected_device_arch.as_deref(),
-        features,
-        bin,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-        &materialization,
-    );
-    run_compute_sanitizer(
-        ctx,
-        &example_dir,
-        tool,
-        sanitizer_args,
-        application_args,
-        &binary,
-    );
-}
-
-// =============================================================================
-// Interop host/device workflow
-// =============================================================================
-
-#[derive(Debug, Clone)]
-struct InteropConfig {
-    kind: Option<String>,
-    device_crates: Vec<DeviceCrateConfig>,
-}
-
-#[derive(Debug, Clone)]
-struct DeviceCrateConfig {
-    manifest_path: PathBuf,
-    artifact_dir: PathBuf,
-    artifact_name: Option<String>,
-    artifact_kind: InteropArtifactKind,
-    source_identity: bool,
-    bin: Option<String>,
-}
-
-#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
-enum InteropArtifactKind {
-    #[default]
-    Ptx,
-    Cubin,
-}
-
-impl InteropArtifactKind {
-    fn extension(self) -> &'static str {
-        match self {
-            Self::Ptx => "ptx",
-            Self::Cubin => "cubin",
-        }
-    }
-
-    fn emits_nvvm_ir(self) -> bool {
-        self == Self::Cubin
-    }
-}
-
-#[derive(Debug, Clone, Eq, PartialEq)]
-struct InteropBinaryTarget {
-    source_path: PathBuf,
-}
-
-#[derive(Clone, Copy, Debug, Default)]
-struct InteropDeviceBuildOptions {
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    sanitizer_line_tables: bool,
-}
-
-impl InteropDeviceBuildOptions {
-    fn standard(no_fmad: bool, unchecked_indexing: bool) -> Self {
-        Self {
-            no_fmad,
-            unchecked_indexing,
-            sanitizer_line_tables: false,
-        }
-    }
-}
-
-#[allow(clippy::too_many_arguments)]
-fn codegen_run_interop(
-    ctx: &Context,
-    example: &str,
-    example_dir: &Path,
-    interop: &InteropConfig,
-    verbose: bool,
-    emit_nvvm_ir: bool,
-    arch: Option<&str>,
-    detected_device_arch: Option<&str>,
-    features: Option<&str>,
-    device_features: Option<&str>,
-    bin: Option<&str>,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    materialization: &MaterializationMode,
-    app_args: &[String],
-) {
-    reject_interop_output_mode(emit_nvvm_ir, materialization);
-
-    println!("=========================================");
-    println!("RUSTC-CODEGEN-CUDA INTEROP: {}", example);
-    println!("=========================================");
-    if let Some(kind) = &interop.kind {
-        println!("Interop kind: {}", kind);
-    }
-    if let Some(dev) = detected_device_arch {
-        println!("Detected GPU arch: {dev} (via nvidia-smi)");
-    }
-    println!();
-
-    build_interop_device_crates(
-        ctx,
-        example_dir,
-        interop,
-        verbose,
-        arch,
-        detected_device_arch,
-        device_features,
-        InteropDeviceBuildOptions::standard(no_fmad, unchecked_indexing),
-        materialization,
-    );
-    run_host_cargo(
-        ctx,
-        example,
-        example_dir,
-        "run",
-        features,
-        bin,
-        verbose,
-        app_args,
-    );
-}
-
-#[allow(clippy::too_many_arguments)]
-fn codegen_build_interop(
-    ctx: &Context,
-    example: &str,
-    example_dir: &Path,
-    interop: &InteropConfig,
-    verbose: bool,
-    emit_nvvm_ir: bool,
-    arch: Option<&str>,
-    features: Option<&str>,
-    device_features: Option<&str>,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    materialization: &MaterializationMode,
-) {
-    reject_interop_output_mode(emit_nvvm_ir, materialization);
-
-    println!("=========================================");
-    println!("RUSTC-CODEGEN-CUDA INTEROP BUILD: {}", example);
-    println!("=========================================");
-    if let Some(kind) = &interop.kind {
-        println!("Interop kind: {}", kind);
-    }
-    println!();
-
-    // `build` may cross-compile for another machine, so no device-arch hint:
-    // only an explicit `--arch` pins the target here.
-    build_interop_device_crates(
-        ctx,
-        example_dir,
-        interop,
-        verbose,
-        arch,
-        None,
-        device_features,
-        InteropDeviceBuildOptions::standard(no_fmad, unchecked_indexing),
-        materialization,
-    );
-    run_host_cargo(
-        ctx,
-        example,
-        example_dir,
-        "build",
-        features,
-        None,
-        verbose,
-        &[],
-    );
-}
-
-fn reject_interop_output_mode(emit_nvvm_ir: bool, materialization: &MaterializationMode) {
-    if materialization.enabled() {
-        eprintln!("Error: --materialize-cubin is not supported for metadata interop examples yet.");
-        eprintln!(
-            "Declare `artifact-kind = \"cubin\"` on each device crate that requires native output."
-        );
-        std::process::exit(2);
-    }
-    if emit_nvvm_ir {
-        eprintln!("Error: --emit-nvvm-ir is not supported for metadata interop examples yet.");
-        eprintln!("Interop device output is selected by each metadata `artifact-kind`.");
-        std::process::exit(2);
-    }
-}
-
-#[allow(clippy::too_many_arguments)]
-fn build_interop_device_crates(
-    ctx: &Context,
-    example_dir: &Path,
-    interop: &InteropConfig,
-    verbose: bool,
-    arch: Option<&str>,
-    detected_device_arch: Option<&str>,
-    device_features: Option<&str>,
-    options: InteropDeviceBuildOptions,
-    materialization: &MaterializationMode,
-) {
-    for device_crate in &interop.device_crates {
-        build_interop_device_crate(
-            ctx,
-            example_dir,
-            device_crate,
-            verbose,
-            arch,
-            detected_device_arch,
-            device_features,
-            options,
-            materialization,
-        );
-    }
-}
-
-fn interop_device_artifact_name(manifest_path: &Path, device_crate: &DeviceCrateConfig) -> String {
-    device_crate.artifact_name.clone().unwrap_or_else(|| {
-        normalize_crate_name(&interop_device_cargo_target_name(
-            manifest_path,
-            device_crate,
-        ))
-    })
-}
-
-fn interop_device_cargo_target_name(
-    manifest_path: &Path,
-    device_crate: &DeviceCrateConfig,
-) -> String {
-    device_crate
-        .bin
-        .clone()
-        .unwrap_or_else(|| package_name_from_manifest(manifest_path))
-}
-
-fn interop_device_artifact_path(
-    example_dir: &Path,
-    device_crate: &DeviceCrateConfig,
-    artifact_name: &str,
-) -> PathBuf {
-    example_dir.join(&device_crate.artifact_dir).join(format!(
-        "{}.{}",
-        artifact_stem(artifact_name),
-        device_crate.artifact_kind.extension()
-    ))
-}
-
-/// Pre-build requirement check for `artifact-kind = "cubin"` device crates.
-///
-/// A native cubin needs a deliberate target, so require one from `--arch`,
-/// `CUDA_OXIDE_TARGET`, project configuration, or the device detected by
-/// `run` before spending a device build. This is a requirement check only:
-/// the arch the finalizer actually compiles for comes from the
-/// backend-recorded `.target` sidecar (see
-/// [`read_interop_recorded_target`]), because the backend may resolve a
-/// different arch than the hint (e.g. escalate a detected `sm_120a` to the
-/// `sm_90a` WGMMA floor).
-fn interop_cubin_target(
-    arch: Option<&str>,
-    detected_device_arch: Option<&str>,
-) -> Result<cuda_artifact_finalizer::CudaArch, String> {
-    let target = arch
-        .map(str::to_owned)
-        .or_else(|| std::env::var("CUDA_OXIDE_TARGET").ok())
-        .or_else(|| detected_device_arch.map(str::to_owned))
-        .ok_or_else(|| {
-            "cubin interop artifacts require --arch, CUDA_OXIDE_TARGET, a configured target, or a detected run device"
-                .to_string()
-        })?;
-    parse_nvvm_arch(&target)
-        .map_err(|error| format!("invalid cubin interop target {target:?}: {error}"))
-}
-
-/// Path of the NVVM IR a cubin-kind device crate emits into its artifact dir.
-fn interop_device_ir_path(
-    example_dir: &Path,
-    device_crate: &DeviceCrateConfig,
-    artifact_name: &str,
-) -> PathBuf {
-    example_dir
-        .join(&device_crate.artifact_dir)
-        .join(format!("{}.ll", artifact_stem(artifact_name)))
-}
-
-/// Read the CUDA target the backend recorded next to an emitted NVVM IR.
-///
-/// The backend publishes `<name>.target` last, after the `.ll` and
-/// `.options`: it is both the authoritative arch record (NVVM IR does not
-/// encode its target) and the completion marker saying the sibling
-/// `.options` file is present and required (see
-/// `write_nvvm_target_sidecar` in mir-importer). A missing or malformed
-/// sidecar therefore means the device build did not complete its artifact
-/// contract, never that some other arch should be guessed.
-fn read_interop_recorded_target(ir_path: &Path) -> Result<String, String> {
-    let path = ir_path.with_extension("target");
-    let text = std::fs::read_to_string(&path).map_err(|error| {
-        format!(
-            "device build did not record its CUDA target at {} ({error}); \
-             the .target sidecar is the backend's completion marker, so the \
-             emitted NVVM IR cannot be trusted without it",
-            path.display()
-        )
-    })?;
-    let mut lines = text.lines();
-    let target = lines.next().unwrap_or_default().trim();
-    if target.is_empty() {
-        return Err(format!("recorded CUDA target {} is empty", path.display()));
-    }
-    match (lines.next(), lines.next()) {
-        (None, None) => Ok(target.to_string()),
-        (Some(marker), None) if marker == oxide_artifacts::COMPILE_OPTIONS_TARGET_MARKER => {
-            let options_path = ir_path.with_extension("options");
-            if !options_path.is_file() {
-                return Err(format!(
-                    "recorded CUDA target {} requires the sibling compile options {}, which is missing",
-                    path.display(),
-                    options_path.display()
-                ));
-            }
-            Ok(target.to_string())
-        }
-        _ => Err(format!(
-            "recorded CUDA target {} has an unrecognized format: {:?}",
-            path.display(),
-            text.trim()
-        )),
-    }
-}
-
-/// Read the `.target sm_XX` directive from an emitted PTX artifact.
-///
-/// PTX carries its own target record, so the identity sidecar can state the
-/// arch the artifact was actually compiled for instead of echoing a request
-/// hint (which the backend is allowed to override).
-fn ptx_recorded_target(ptx_path: &Path) -> Result<String, String> {
-    let text = std::fs::read_to_string(ptx_path).map_err(|error| {
-        format!(
-            "could not read emitted PTX at {}: {error}",
-            ptx_path.display()
-        )
-    })?;
-    let document = ptx_parse::Document::parse(&text).map_err(|error| {
-        format!(
-            "could not parse emitted PTX {} to read its target: {error}",
-            ptx_path.display()
-        )
-    })?;
-    document
-        .directives()
-        .iter()
-        .find(|directive| directive.name() == ".target")
-        .and_then(|directive| ptx_parse::split_top_level(directive.arguments()))
-        .and_then(|arguments| arguments.first().copied())
-        .map(str::to_string)
-        .filter(|target| !target.is_empty())
-        .ok_or_else(|| {
-            format!(
-                "emitted PTX {} does not declare a .target directive",
-                ptx_path.display()
-            )
-        })
-}
-
-/// The CUDA target an interop device artifact was actually built for, read
-/// from the emitted artifact itself: the backend `.target` sidecar for
-/// cubin (the same record the finalizer compiled with) and the `.target`
-/// directive for PTX.
-fn interop_artifact_recorded_target(
-    example_dir: &Path,
-    device_crate: &DeviceCrateConfig,
-    artifact_name: &str,
-) -> Result<String, String> {
-    match device_crate.artifact_kind {
-        InteropArtifactKind::Ptx => ptx_recorded_target(&interop_device_artifact_path(
-            example_dir,
-            device_crate,
-            artifact_name,
-        )),
-        InteropArtifactKind::Cubin => read_interop_recorded_target(&interop_device_ir_path(
-            example_dir,
-            device_crate,
-            artifact_name,
-        )),
-    }
-}
-
-fn finalize_interop_device_artifact(
-    example_dir: &Path,
-    device_crate: &DeviceCrateConfig,
-    artifact_name: &str,
-) -> PathBuf {
-    let artifact_path = interop_device_artifact_path(example_dir, device_crate, artifact_name);
-    match device_crate.artifact_kind {
-        InteropArtifactKind::Ptx => artifact_path,
-        InteropArtifactKind::Cubin => {
-            let ir_path = interop_device_ir_path(example_dir, device_crate, artifact_name);
-            // The backend-recorded target, not the CLI/env/detected hint:
-            // the backend may have resolved a different arch, and this
-            // sidecar doubles as the completion marker for the .ll/.options
-            // pair consumed below.
-            let recorded_target = read_interop_recorded_target(&ir_path).unwrap_or_else(|error| {
-                eprintln!("Error: {error}");
-                std::process::exit(1);
-            });
-            let target = parse_nvvm_arch(&recorded_target).unwrap_or_else(|error| {
-                eprintln!(
-                    "Error: invalid recorded CUDA target {recorded_target:?} next to {}: {error}",
-                    ir_path.display()
-                );
-                std::process::exit(1);
-            });
-            let ir = std::fs::read(&ir_path).unwrap_or_else(|error| {
-                eprintln!(
-                    "Error: could not read emitted NVVM IR at {}: {error}",
-                    ir_path.display()
-                );
-                std::process::exit(1);
-            });
-            let options_path = ir_path.with_extension("options");
-            let options_text = std::fs::read_to_string(&options_path).unwrap_or_else(|error| {
-                eprintln!(
-                    "Error: could not read emitted compile options at {}: {error}",
-                    options_path.display()
-                );
-                std::process::exit(1);
-            });
-            let compile_options =
-                oxide_artifacts::ArtifactCompileOptions::from_sidecar_text(&options_text)
-                    .unwrap_or_else(|error| {
-                        eprintln!(
-                            "Error: invalid emitted compile options at {}: {error}",
-                            options_path.display()
-                        );
-                        std::process::exit(1);
-                    });
-            let finalizer = cuda_artifact_finalizer::Finalizer::discover().unwrap_or_else(|error| {
-                eprintln!("Error: could not initialize the CUDA artifact finalizer: {error}");
-                eprintln!(
-                    "libNVVM and nvJitLink ship with the CUDA Toolkit; run `cargo oxide doctor` to check discovery."
-                );
-                std::process::exit(1);
-            });
-            let options = finalization_options_from_artifact(&target, compile_options);
-            let cubin = finalizer
-                .materialize_nvvm_ir(artifact_name, &ir, &options)
-                .unwrap_or_else(|error| {
-                    eprintln!(
-                        "Error: could not finalize {} for {}: {error}",
-                        ir_path.display(),
-                        target.sm()
-                    );
-                    std::process::exit(1);
-                });
-            let temporary_path = artifact_path.with_extension("cubin.tmp");
-            std::fs::write(&temporary_path, cubin).unwrap_or_else(|error| {
-                eprintln!(
-                    "Error: could not write temporary cubin {}: {error}",
-                    temporary_path.display()
-                );
-                std::process::exit(1);
-            });
-            std::fs::rename(&temporary_path, &artifact_path).unwrap_or_else(|error| {
-                eprintln!(
-                    "Error: could not install cubin {}: {error}",
-                    artifact_path.display()
-                );
-                std::process::exit(1);
-            });
-            artifact_path
-        }
-    }
-}
-
-#[allow(clippy::too_many_arguments)]
-fn build_interop_device_crate(
-    ctx: &Context,
-    example_dir: &Path,
-    device_crate: &DeviceCrateConfig,
-    verbose: bool,
-    arch: Option<&str>,
-    detected_device_arch: Option<&str>,
-    device_features: Option<&str>,
-    options: InteropDeviceBuildOptions,
-    materialization: &MaterializationMode,
-) {
-    let manifest_path = example_dir.join(&device_crate.manifest_path);
-    let manifest_path = manifest_path.canonicalize().unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not resolve device crate manifest {}: {}",
-            manifest_path.display(),
-            e
-        );
-        std::process::exit(1);
-    });
-    let device_dir = manifest_path.parent().unwrap_or(example_dir);
-    // One `cargo metadata` invocation answers both consumers: bin-target
-    // resolution before the build and the uplifted depfile location after
-    // it. Skip it entirely when neither feature is requested.
-    let cargo_metadata = (device_crate.bin.is_some() || device_crate.source_identity).then(|| {
-        interop_cargo_metadata(ctx, device_dir, &manifest_path).unwrap_or_else(|error| {
-            eprintln!("Error: could not query cargo metadata for the device crate: {error}");
-            std::process::exit(1);
-        })
-    });
-    let binary_target = device_crate.bin.as_deref().map(|bin| {
-        let metadata = cargo_metadata
-            .as_ref()
-            .expect("cargo metadata is fetched whenever a bin target is configured");
-        interop_binary_target_from_metadata(metadata, &manifest_path, bin).unwrap_or_else(|error| {
-            eprintln!("Error: could not resolve device binary target: {error}");
-            std::process::exit(1);
-        })
-    });
-    let artifact_dir = example_dir.join(&device_crate.artifact_dir);
-    std::fs::create_dir_all(&artifact_dir).unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not create device artifact directory {}: {}",
-            artifact_dir.display(),
-            e
-        );
-        std::process::exit(1);
-    });
-
-    if device_crate.artifact_kind == InteropArtifactKind::Cubin
-        && let Err(error) = interop_cubin_target(arch, detected_device_arch)
-    {
-        eprintln!("Error: {error}");
-        std::process::exit(2);
-    }
-
-    let artifact_name = interop_device_artifact_name(&manifest_path, device_crate);
-    clean_generated_files(&artifact_dir, &artifact_name);
-    if let Some(target) = &binary_target {
-        touch_source_file(&target.source_path);
-    } else {
-        touch_main_rs(device_dir);
-    }
-
-    println!("Building device crate {}...", manifest_path.display());
-
-    let mut cmd = Command::new("cargo");
-    cmd.args(["build", "--release", "--manifest-path"])
-        .arg(&manifest_path)
-        .current_dir(device_dir);
-    if let Some(device_features) = device_features {
-        cmd.args(["--features", device_features]);
-    }
-    if let Some(bin) = &device_crate.bin {
-        cmd.args(["--bin", bin]);
-    }
-
-    apply_interop_device_codegen_options(&mut cmd, ctx, verbose, options);
-    let fingerprint = interop_codegen_fingerprint(
-        ctx,
-        verbose,
-        options.no_fmad,
-        options.unchecked_indexing,
-        DeviceDebug::Off,
-        arch,
-        detected_device_arch,
-        &artifact_dir,
-        device_crate.artifact_kind.emits_nvvm_ir(),
-        device_features,
-        options.sanitizer_line_tables,
-        materialization,
-    );
-    apply_codegen_configuration_or_exit(
-        &mut cmd,
-        ctx,
-        CodegenProfilePolicy::ReleaseLike,
-        &[],
-        &fingerprint,
-    );
-    // This is an internal artifact contract, so it must override a project
-    // `[env]` default for the same variable.
-    cmd.env("CUDA_OXIDE_PTX_DIR", &artifact_dir);
-    apply_output_mode(
-        &mut cmd,
-        device_crate.artifact_kind.emits_nvvm_ir(),
-        arch,
-        materialization,
-    );
-    apply_device_arch_hint(&mut cmd, arch, detected_device_arch);
-
-    let status = cmd.status().expect("Failed to build interop device crate");
-    if !status.success() {
-        eprintln!(
-            "\nDevice crate build failed with exit code: {:?}",
-            status.code()
-        );
-        std::process::exit(status.code().unwrap_or(1));
-    }
-
-    let artifact_path = finalize_interop_device_artifact(example_dir, device_crate, &artifact_name);
-    if !artifact_path.exists() {
-        eprintln!(
-            "Error: device crate build succeeded but did not produce {}",
-            artifact_path.display()
-        );
-        std::process::exit(1);
-    }
-    println!(
-        "{} written: {}",
-        device_crate.artifact_kind.extension().to_ascii_uppercase(),
-        artifact_path.display()
-    );
-    if device_crate.source_identity {
-        // The identity records the arch the artifact was actually built
-        // for, read back from the emitted artifact, never the request hint.
-        let artifact_target =
-            interop_artifact_recorded_target(example_dir, device_crate, &artifact_name)
-                .unwrap_or_else(|error| {
-                    eprintln!(
-                        "Error: could not determine the built CUDA target for {}: {error}",
-                        artifact_path.display()
-                    );
-                    std::process::exit(1);
-                });
-        let cargo_target_name = interop_device_cargo_target_name(&manifest_path, device_crate);
-        let metadata = cargo_metadata
-            .as_ref()
-            .expect("cargo metadata is fetched whenever source-identity is configured");
-        let cargo_target_dir = cargo_target_directory(metadata).unwrap_or_else(|error| {
-            eprintln!("Error: could not locate the device cargo target directory: {error}");
-            std::process::exit(1);
-        });
-        let depfile_path = release_depfile_path(&cargo_target_dir, &cargo_target_name);
-        if !depfile_path.is_file() {
-            eprintln!(
-                "Error: device crate build succeeded but did not produce dependency file {}",
-                depfile_path.display()
-            );
-            std::process::exit(1);
-        }
-        let identity_base = artifact_path.parent().unwrap_or(example_dir);
-        let identity_path = crate::artifact_identity::write(
-            &artifact_path,
-            &depfile_path,
-            &manifest_path,
-            identity_base,
-            &cargo_target_dir,
-            &artifact_target,
-            device_features,
-        )
-        .unwrap_or_else(|error| {
-            eprintln!(
-                "Error: could not write source identity for {}: {error}",
-                artifact_path.display()
-            );
-            std::process::exit(1);
-        });
-        println!("Artifact identity written: {}", identity_path.display());
-    }
-}
-
-#[allow(clippy::too_many_arguments)]
-fn run_host_cargo(
-    ctx: &Context,
-    example: &str,
-    example_dir: &Path,
-    cargo_subcommand: &str,
-    features: Option<&str>,
-    bin: Option<&str>,
-    verbose: bool,
-    app_args: &[String],
-) {
-    let mut cmd = Command::new("cargo");
-    cmd.arg(cargo_subcommand)
-        .arg("--release")
-        .current_dir(example_dir);
-
-    if cargo_subcommand == "run"
-        && let Some(bin) = bin
-    {
-        cmd.args(["--bin", bin]);
-    }
-    if let Some(features) = features {
-        cmd.args(["--features", features]);
-    }
-    if cargo_subcommand == "run" && !app_args.is_empty() {
-        cmd.arg("--").args(app_args);
-    }
-
-    apply_config_env(&mut cmd, ctx);
-    apply_ld_library_path(&mut cmd, ctx);
-
-    if cargo_subcommand == "run" {
-        if let Some(bin) = bin {
-            println!("Building and running {} (bin: {})...", example, bin);
-        } else {
-            println!("Building and running {}...", example);
-        }
-    } else {
-        println!("Building host crate {}...", example);
-    }
-    println!();
-
-    if verbose {
-        cmd.env("CUDA_OXIDE_VERBOSE", "1");
-    }
-
-    let status = cmd.status().expect("Failed to run host cargo command");
-    if !status.success() {
-        eprintln!(
-            "\nHost cargo command failed with exit code: {:?}",
-            status.code()
-        );
-        std::process::exit(status.code().unwrap_or(1));
-    }
-}
-
-#[allow(clippy::too_many_arguments)]
-fn codegen_build_host_binary(
-    ctx: &Context,
-    example: &str,
-    example_dir: &Path,
-    verbose: bool,
-    arch: Option<&str>,
-    detected_device_arch: Option<&str>,
-    features: Option<&str>,
-    bin: Option<&str>,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-    materialization: &MaterializationMode,
-) -> PathBuf {
-    let mut cmd = Command::new("cargo");
-    cmd.args(["build", "--release"]).current_dir(example_dir);
-
-    if let Some(bin) = bin {
-        cmd.args(["--bin", bin]);
-    }
-    if let Some(features) = features {
-        cmd.args(["--features", features]);
-    }
-
-    apply_common_codegen_env(
-        &mut cmd,
-        ctx,
-        verbose,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-    );
-    apply_default_sanitizer_line_tables(&mut cmd, ctx, device_debug);
-    let fingerprint = sanitize_codegen_fingerprint(
-        ctx,
-        verbose,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-        arch,
-        detected_device_arch,
-        None,
-        materialization,
-    );
-    apply_codegen_configuration_or_exit(
-        &mut cmd,
-        ctx,
-        CodegenProfilePolicy::ReleaseLike,
-        &[],
-        &fingerprint,
-    );
-    apply_output_mode(&mut cmd, false, arch, materialization);
-    apply_device_arch_hint(&mut cmd, arch, detected_device_arch);
-
-    if let Some(bin) = bin {
-        println!("Building {} (bin: {})...", example, bin);
-    } else {
-        println!("Building {}...", example);
-    }
-    println!();
-
-    run_cargo_build_for_executable(&mut cmd, example_dir, bin).unwrap_or_else(|message| {
-        eprintln!("\nBuild failed: {message}");
-        std::process::exit(1);
-    })
-}
-
-fn build_host_cargo(
-    ctx: &Context,
-    example: &str,
-    example_dir: &Path,
-    features: Option<&str>,
-    bin: Option<&str>,
-    verbose: bool,
-) -> PathBuf {
-    let mut cmd = Command::new("cargo");
-    cmd.args(["build", "--release"]).current_dir(example_dir);
-
-    if let Some(bin) = bin {
-        cmd.args(["--bin", bin]);
-    }
-    if let Some(features) = features {
-        cmd.args(["--features", features]);
-    }
-
-    apply_config_env(&mut cmd, ctx);
-    apply_ld_library_path(&mut cmd, ctx);
-
-    if let Some(bin) = bin {
-        println!("Building host crate {} (bin: {})...", example, bin);
-    } else {
-        println!("Building host crate {}...", example);
-    }
-    println!();
-
-    if verbose {
-        cmd.env("CUDA_OXIDE_VERBOSE", "1");
-    }
-
-    run_cargo_build_for_executable(&mut cmd, example_dir, bin).unwrap_or_else(|message| {
-        eprintln!("\nHost cargo build failed: {message}");
-        std::process::exit(1);
-    })
-}
-
-fn run_cargo_build_for_executable(
-    cmd: &mut Command,
-    manifest_dir: &Path,
-    explicit_bin: Option<&str>,
-) -> Result<PathBuf, String> {
-    let selection = cargo_executable_selection(manifest_dir, explicit_bin)?;
-
-    cmd.arg("--message-format=json-render-diagnostics");
-    let output = cmd
-        .output()
-        .map_err(|error| format!("could not start Cargo: {error}"))?;
-
-    let stderr = String::from_utf8_lossy(&output.stderr);
-    if !stderr.is_empty() {
-        eprint!("{stderr}");
-    }
-
-    let mut executables = Vec::<CargoExecutableArtifact>::new();
-    for line in String::from_utf8_lossy(&output.stdout).lines() {
-        let message: serde_json::Value = match serde_json::from_str(line) {
-            Ok(message) => message,
-            Err(_) => {
-                if !line.is_empty() {
-                    println!("{line}");
-                }
-                continue;
-            }
-        };
-
-        if let Some(rendered) = message
-            .get("message")
-            .and_then(|message| message.get("rendered"))
-            .and_then(|rendered| rendered.as_str())
-        {
-            eprint!("{rendered}");
-        }
-
-        if message.get("reason").and_then(|reason| reason.as_str()) != Some("compiler-artifact") {
-            continue;
-        }
-        let is_binary = message
-            .get("target")
-            .and_then(|target| target.get("kind"))
-            .and_then(|kind| kind.as_array())
-            .is_some_and(|kinds| kinds.iter().any(|kind| kind.as_str() == Some("bin")));
-        if !is_binary {
-            continue;
-        }
-        let Some(path) = message.get("executable").and_then(|path| path.as_str()) else {
-            continue;
-        };
-        let Some(package_id) = message
-            .get("package_id")
-            .and_then(|package_id| package_id.as_str())
-        else {
-            continue;
-        };
-        let Some(name) = message
-            .get("target")
-            .and_then(|target| target.get("name"))
-            .and_then(|name| name.as_str())
-        else {
-            continue;
-        };
-        executables.push(CargoExecutableArtifact {
-            package_id: package_id.to_string(),
-            target_name: name.to_string(),
-            path: PathBuf::from(path),
-        });
-    }
-
-    if !output.status.success() {
-        return Err(format!("Cargo exited with status {}", output.status));
-    }
-
-    select_cargo_executable_artifact(&selection, &executables)
-}
-
-#[derive(Debug, PartialEq, Eq)]
-struct CargoExecutableSelection {
-    packages: Vec<CargoSelectedPackage>,
-    explicit_bin: Option<String>,
-}
-
-#[derive(Debug, PartialEq, Eq)]
-struct CargoSelectedPackage {
-    package_id: String,
-    package_name: String,
-    default_run: Option<String>,
-}
-
-#[derive(Debug, PartialEq, Eq)]
-struct CargoExecutableArtifact {
-    package_id: String,
-    target_name: String,
-    path: PathBuf,
-}
-
-fn cargo_executable_selection(
-    manifest_dir: &Path,
-    explicit_bin: Option<&str>,
-) -> Result<CargoExecutableSelection, String> {
-    let metadata = cargo_metadata(manifest_dir)?;
-    let manifest_path = manifest_dir.join("Cargo.toml");
-    let manifest_path = manifest_path
-        .canonicalize()
-        .map_err(|error| format!("could not resolve {}: {error}", manifest_path.display()))?;
-
-    let packages = metadata
-        .get("packages")
-        .and_then(|packages| packages.as_array())
-        .ok_or_else(|| "Cargo metadata did not include packages".to_string())?;
-
-    let selected_packages = cargo_selected_packages(&metadata, packages, &manifest_path)?;
-    let packages = selected_packages
-        .into_iter()
-        .map(cargo_selected_package)
-        .collect::<Result<Vec<_>, _>>()?;
-    Ok(CargoExecutableSelection {
-        packages,
-        explicit_bin: explicit_bin.map(str::to_owned),
-    })
-}
-
-/// Return the packages Cargo selects for a command launched from
-/// `manifest_path`.
-///
-/// At a workspace root, Cargo uses `workspace.default-members` even when the
-/// root manifest also contains a `[package]`. Inside a member directory, Cargo
-/// instead selects that member. `cargo metadata` has already resolved the
-/// workspace defaults for us, so mirror that distinction here.
-fn cargo_selected_packages<'a>(
-    metadata: &serde_json::Value,
-    packages: &'a [serde_json::Value],
-    manifest_path: &Path,
-) -> Result<Vec<&'a serde_json::Value>, String> {
-    let workspace_root = metadata
-        .get("workspace_root")
-        .and_then(|path| path.as_str())
-        .ok_or_else(|| "Cargo metadata did not include workspace_root".to_string())?;
-    let workspace_manifest = PathBuf::from(workspace_root).join("Cargo.toml");
-    let workspace_manifest = workspace_manifest.canonicalize().map_err(|error| {
-        format!(
-            "could not resolve workspace manifest {}: {error}",
-            workspace_manifest.display()
-        )
-    })?;
-
-    if manifest_path != workspace_manifest {
-        let package = packages
-            .iter()
-            .find(|package| cargo_package_manifest_matches(package, manifest_path))
-            .ok_or_else(|| {
-                format!(
-                    "could not determine the Cargo package for {}",
-                    manifest_path.display()
-                )
-            })?;
-        return Ok(vec![package]);
-    }
-
-    let default_members = metadata
-        .get("workspace_default_members")
-        .and_then(|members| members.as_array())
-        .ok_or_else(|| "Cargo metadata did not include workspace_default_members".to_string())?;
-    if default_members.is_empty() {
-        return Err("Cargo selected no workspace default members".to_string());
-    }
-
-    default_members
-        .iter()
-        .map(|member| {
-            let package_id = member.as_str().ok_or_else(|| {
-                "Cargo metadata contained a non-string workspace default member".to_string()
-            })?;
-            packages
-                .iter()
-                .find(|package| cargo_package_id(package).ok() == Some(package_id))
-                .ok_or_else(|| {
-                    format!(
-                        "Cargo workspace default member `{package_id}` was missing from metadata packages"
-                    )
-                })
-        })
-        .collect()
-}
-
-fn cargo_package_manifest_matches(package: &serde_json::Value, manifest_path: &Path) -> bool {
-    package
-        .get("manifest_path")
-        .and_then(|path| path.as_str())
-        .and_then(|path| PathBuf::from(path).canonicalize().ok())
-        .is_some_and(|path| path == manifest_path)
-}
-
-fn cargo_metadata(manifest_dir: &Path) -> Result<serde_json::Value, String> {
-    let output = Command::new("cargo")
-        .args(["metadata", "--format-version=1", "--no-deps"])
-        .current_dir(manifest_dir)
-        .output()
-        .map_err(|error| format!("could not start cargo metadata: {error}"))?;
-
-    if !output.status.success() {
-        let stderr = String::from_utf8_lossy(&output.stderr);
-        return Err(format!(
-            "cargo metadata failed with status {}{}{}",
-            output.status,
-            if stderr.is_empty() { "" } else { ": " },
-            stderr.trim()
-        ));
-    }
-
-    serde_json::from_slice(&output.stdout)
-        .map_err(|error| format!("could not parse cargo metadata JSON: {error}"))
-}
-
-fn cargo_package_id(package: &serde_json::Value) -> Result<&str, String> {
-    package
-        .get("id")
-        .and_then(|id| id.as_str())
-        .ok_or_else(|| "Cargo metadata package is missing id".to_string())
-}
-
-fn cargo_package_name(package: &serde_json::Value) -> Result<&str, String> {
-    package
-        .get("name")
-        .and_then(|name| name.as_str())
-        .ok_or_else(|| "Cargo metadata package is missing name".to_string())
-}
-
-fn cargo_selected_package(package: &serde_json::Value) -> Result<CargoSelectedPackage, String> {
-    Ok(CargoSelectedPackage {
-        package_id: cargo_package_id(package)?.to_string(),
-        package_name: cargo_package_name(package)?.to_string(),
-        default_run: package
-            .get("default_run")
-            .and_then(|name| name.as_str())
-            .map(str::to_owned),
-    })
-}
-
-fn select_cargo_executable_artifact(
-    selection: &CargoExecutableSelection,
-    executables: &[CargoExecutableArtifact],
-) -> Result<PathBuf, String> {
-    if let Some(explicit_bin) = selection.explicit_bin.as_deref() {
-        let matches = selection
-            .packages
-            .iter()
-            .flat_map(|package| {
-                executables
-                    .iter()
-                    .filter(move |artifact| {
-                        artifact.package_id == package.package_id
-                            && artifact.target_name == explicit_bin
-                    })
-                    .map(move |artifact| (package, artifact))
-            })
-            .collect::<Vec<_>>();
-        return match matches.as_slice() {
-            [(_, artifact)] => Ok(artifact.path.clone()),
-            [] => Err(format!(
-                "Cargo produced no executable artifact for target `{explicit_bin}` in selected packages {}",
-                selected_package_names(selection)
-            )),
-            matches => Err(format!(
-                "Cargo produced executable target `{explicit_bin}` for multiple selected packages: {}; run from a package directory",
-                matches
-                    .iter()
-                    .map(|(package, _)| package.package_name.as_str())
-                    .collect::<Vec<_>>()
-                    .join(", ")
-            )),
-        };
-    }
-
-    let mut candidates = Vec::new();
-    for package in &selection.packages {
-        let artifacts = executables
-            .iter()
-            .filter(|artifact| artifact.package_id == package.package_id)
-            .collect::<Vec<_>>();
-
-        if let Some(default_run) = package.default_run.as_deref() {
-            let matches = artifacts
-                .iter()
-                .copied()
-                .filter(|artifact| artifact.target_name == default_run)
-                .collect::<Vec<_>>();
-            match matches.as_slice() {
-                [artifact] => candidates.push((package, *artifact)),
-                [] => {
-                    return Err(format!(
-                        "Cargo produced no executable artifact for package `{}` default-run target `{default_run}`",
-                        package.package_name
-                    ));
-                }
-                _ => {
-                    return Err(format!(
-                        "Cargo produced multiple executable artifacts for package `{}` default-run `{default_run}`",
-                        package.package_name
-                    ));
-                }
-            }
-            continue;
-        }
-
-        // A selected package without an emitted binary may simply be a
-        // library-only workspace member. A package with `default-run` is
-        // handled above: silently skipping its missing target could launch a
-        // different default member's program instead.
-        if artifacts.is_empty() {
-            continue;
-        }
-
-        match artifacts.as_slice() {
-            [artifact] => candidates.push((package, *artifact)),
-            artifacts => {
-                let choices = artifacts
-                    .iter()
-                    .map(|artifact| artifact.target_name.as_str())
-                    .collect::<Vec<_>>()
-                    .join(", ");
-                return Err(format!(
-                    "Cargo produced multiple executable targets for package `{}`: {choices}; pass --bin <name>",
-                    package.package_name
-                ));
-            }
-        }
-    }
-
-    match candidates.as_slice() {
-        [(_, artifact)] => Ok(artifact.path.clone()),
-        [] => Err(format!(
-            "Cargo produced no executable artifact for selected packages {}",
-            selected_package_names(selection)
-        )),
-        candidates => Err(format!(
-            "Cargo produced executables for multiple selected packages: {}; pass --bin <name> that is unique among them",
-            candidates
-                .iter()
-                .map(|(package, _)| package.package_name.as_str())
-                .collect::<Vec<_>>()
-                .join(", ")
-        )),
-    }
-}
-
-fn selected_package_names(selection: &CargoExecutableSelection) -> String {
-    selection
-        .packages
-        .iter()
-        .map(|package| package.package_name.as_str())
-        .collect::<Vec<_>>()
-        .join(", ")
-}
-
-const DEFAULT_SANITIZER_ERROR_EXITCODE: &str = "86";
-
-#[derive(Debug, PartialEq, Eq)]
-struct SanitizerInvocationArgs {
-    args: Vec<String>,
-    uses_default_error_exitcode: bool,
-    status_checks_weakened: bool,
-}
-
-fn sanitizer_invocation_args(sanitizer_args: &[String]) -> SanitizerInvocationArgs {
-    let has_explicit_error_exitcode = sanitizer_args
-        .iter()
-        .any(|arg| arg == "--error-exitcode" || arg.starts_with("--error-exitcode="));
-    if has_explicit_error_exitcode {
-        return SanitizerInvocationArgs {
-            args: sanitizer_args.to_vec(),
-            uses_default_error_exitcode: false,
-            status_checks_weakened: sanitizer_option_is_no(sanitizer_args, "check-exit-code")
-                || sanitizer_option_is_no(sanitizer_args, "require-cuda-init"),
-        };
-    }
-
-    let mut args = Vec::with_capacity(sanitizer_args.len() + 2);
-    args.extend([
-        "--error-exitcode".to_string(),
-        DEFAULT_SANITIZER_ERROR_EXITCODE.to_string(),
-    ]);
-    args.extend_from_slice(sanitizer_args);
-    SanitizerInvocationArgs {
-        args,
-        uses_default_error_exitcode: true,
-        status_checks_weakened: sanitizer_option_is_no(sanitizer_args, "check-exit-code")
-            || sanitizer_option_is_no(sanitizer_args, "require-cuda-init"),
-    }
-}
-
-fn sanitizer_option_is_no(args: &[String], name: &str) -> bool {
-    let option = format!("--{name}");
-    let equals_prefix = format!("{option}=");
-    args.iter().enumerate().any(|(index, arg)| {
-        arg.strip_prefix(&equals_prefix)
-            .is_some_and(|value| value.eq_ignore_ascii_case("no"))
-            || (arg == &option
-                && args
-                    .get(index + 1)
-                    .is_some_and(|value| value.eq_ignore_ascii_case("no")))
-    })
-}
-
-/// Fallback locations probed for `compute-sanitizer` when it is neither on
-/// PATH nor under the configured CUDA toolkit root. Shared by `sanitize`
-/// (`run_compute_sanitizer`) and `doctor` so both use the same discovery
-/// order by construction.
-const COMPUTE_SANITIZER_FALLBACK_PATHS: &[&str] = &[
-    "/usr/local/cuda/bin/compute-sanitizer",
-    "/opt/cuda/bin/compute-sanitizer",
-    "/usr/bin/compute-sanitizer",
-];
-
-/// Fallback locations probed for `nvcc`, in the same idiom and for the same
-/// reason as the list above. `nvcc` ships in the toolkit's `bin/` beside
-/// `compute-sanitizer` and `cuda-gdb`, so it has to be found the same way.
-const NVCC_FALLBACK_PATHS: &[&str] = &[
-    "/usr/local/cuda/bin/nvcc",
-    "/opt/cuda/bin/nvcc",
-    "/usr/bin/nvcc",
-];
-
-/// Fallback locations probed for `cuda-gdb`. Shared by `debug`
-/// (`codegen_debug`) and `doctor` so both use the same discovery order by
-/// construction -- doctor exists to predict whether `debug` will work, so the
-/// two answering differently is the bug this list prevents.
-const CUDA_GDB_FALLBACK_PATHS: &[&str] = &[
-    "/usr/local/cuda/bin/cuda-gdb",
-    "/opt/cuda/bin/cuda-gdb",
-    "/usr/bin/cuda-gdb",
-];
-
-/// Every CUDA toolkit executable `doctor` probes, with its fallbacks.
-///
-/// One table so a fourth tool cannot be added with a different discovery rule.
-/// Before this existed, `compute-sanitizer` resolved through the toolkit root
-/// while `nvcc` and `cuda-gdb` used a bare PATH lookup, so doctor reported the
-/// toolkit missing on an install where it had already found `cuda.h`, libNVVM,
-/// nvJitLink and libdevice under that same root.
-const DOCTOR_TOOLKIT_TOOLS: [(&str, &[&str]); 3] = [
-    ("nvcc", NVCC_FALLBACK_PATHS),
-    ("cuda-gdb", CUDA_GDB_FALLBACK_PATHS),
-    ("compute-sanitizer", COMPUTE_SANITIZER_FALLBACK_PATHS),
-];
-
-/// Resolve one of [`DOCTOR_TOOLKIT_TOOLS`] the way the command that uses it
-/// does: PATH first, then the configured toolkit root, then the standard
-/// install roots.
-/// The standard install roots to try for `name`, or none if the table does not
-/// know it. Split out so the pairing can be checked without a filesystem or an
-/// ambient environment, neither of which a test can control here: the PATH
-/// probe inside `find_cuda_toolkit_executable` shells out to `which` and has no
-/// injection point.
-fn toolkit_tool_fallbacks(name: &str) -> &'static [&'static str] {
-    DOCTOR_TOOLKIT_TOOLS
-        .iter()
-        .find(|(tool, _)| *tool == name)
-        .map(|(_, paths)| *paths)
-        .unwrap_or(&[])
-}
-
-fn doctor_toolkit_tool(ctx: &Context, name: &str) -> Option<PathBuf> {
-    find_cuda_toolkit_executable(ctx, name, toolkit_tool_fallbacks(name))
-}
-
-fn run_compute_sanitizer(
-    ctx: &Context,
-    example_dir: &Path,
-    tool: &str,
-    sanitizer_args: &[String],
-    application_args: &[String],
-    binary: &Path,
-) {
-    let compute_sanitizer = find_cuda_toolkit_executable(
-        ctx,
-        "compute-sanitizer",
-        COMPUTE_SANITIZER_FALLBACK_PATHS,
-    )
-    .unwrap_or_else(|| {
-        eprintln!("Error: compute-sanitizer not found.");
-        eprintln!(
-            "It is installed with the CUDA Toolkit; run `cargo oxide doctor` to check CUDA setup."
-        );
-        std::process::exit(1);
-    });
-
-    let invocation_args = sanitizer_invocation_args(sanitizer_args);
-    let mut cmd = Command::new(compute_sanitizer);
-    cmd.args(["--tool", tool])
-        .args(&invocation_args.args)
-        .arg(binary)
-        .args(application_args)
-        .current_dir(example_dir);
-    apply_config_env(&mut cmd, ctx);
-    apply_ld_library_path(&mut cmd, ctx);
-
-    let forwarded_args = if invocation_args.args.is_empty() {
-        String::new()
-    } else {
-        format!(" {}", invocation_args.args.join(" "))
-    };
-    let displayed_application_args = if application_args.is_empty() {
-        String::new()
-    } else {
-        format!(" {}", application_args.join(" "))
-    };
-    println!(
-        "Running compute-sanitizer --tool {tool}{forwarded_args} {}{displayed_application_args}...",
-        binary.display()
-    );
-    println!();
-
-    let status = cmd.status().expect("Failed to run compute-sanitizer");
-    if !status.success() {
-        eprintln!(
-            "\nCompute Sanitizer failed with exit code: {:?}",
-            status.code()
-        );
-        std::process::exit(status.code().unwrap_or(1));
-    }
-
-    println!();
-    println!("Compute Sanitizer completed with exit code 0.");
-    if !invocation_args.uses_default_error_exitcode {
-        println!(
-            "An explicit --error-exitcode was supplied, so it controls whether findings fail the command."
-        );
-    }
-    if invocation_args.status_checks_weakened {
-        println!(
-            "The supplied sanitizer options can allow target or CUDA-initialization failures to exit 0."
-        );
-    }
-    println!(
-        "Inspect the sanitizer report above; exit status alone is not a clean-report assertion."
-    );
-}
-
-// =============================================================================
-// Build command (compile only, don't run)
-// =============================================================================
-
-/// Compile an example without running it.
-///
-/// Same as [`codegen_run`] but uses `cargo build --release` instead of
-/// `cargo run`. Useful for cross-compilation or when the target hardware
-/// (e.g., Blackwell tensor cores) isn't available on the build machine.
-#[allow(clippy::too_many_arguments)]
-pub fn codegen_build(
-    ctx: &Context,
-    example: &str,
-    verbose: bool,
-    emit_nvvm_ir: bool,
-    arch: Option<&str>,
-    features: Option<&str>,
-    device_features: Option<&str>,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-    materialize_cubin: bool,
-) {
-    let target_arch = configured_arch(ctx, arch);
-    let materialization = prepare_materialization(ctx, materialize_cubin, arch, emit_nvvm_ir);
-    let example_dir = if ctx.is_workspace {
-        resolve_example_dir(ctx, example)
-    } else {
-        ctx.workspace_root.clone()
-    };
-
-    if let Some(interop) =
-        load_interop_config(&example_dir).filter(|config| !config.device_crates.is_empty())
-    {
-        codegen_build_interop(
-            ctx,
-            example,
-            &example_dir,
-            &interop,
-            verbose,
-            emit_nvvm_ir,
-            target_arch,
-            features,
-            device_features,
-            no_fmad,
-            unchecked_indexing,
-            &materialization,
-        );
-        return;
-    }
-    if device_features.is_some() {
-        eprintln!("Error: --device-features requires metadata-declared interop device crates.");
-        std::process::exit(2);
-    }
-
-    clean_generated_files(&example_dir, example);
-
-    println!("=========================================");
-    println!("RUSTC-CODEGEN-CUDA BUILD: {}", example);
-    println!("=========================================");
-    println!();
-
-    touch_main_rs(&example_dir);
-
-    let mut cmd = Command::new("cargo");
-    cmd.args(["build", "--release"]).current_dir(&example_dir);
-
-    if let Some(features) = features {
-        cmd.args(["--features", features]);
-    }
-
-    apply_common_codegen_env(
-        &mut cmd,
-        ctx,
-        verbose,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-    );
-    let fingerprint = standard_codegen_fingerprint(
-        ctx,
-        verbose,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-        emit_nvvm_ir,
-        target_arch,
-        None,
-        &materialization,
-    );
-    apply_codegen_configuration_or_exit(
-        &mut cmd,
-        ctx,
-        CodegenProfilePolicy::ReleaseLike,
-        &[],
-        &fingerprint,
-    );
-    apply_output_mode(&mut cmd, emit_nvvm_ir, target_arch, &materialization);
-
-    println!("Building {}...", example);
-    println!();
-
-    let status = cmd.status().expect("Failed to run cargo");
-    if !status.success() {
-        eprintln!("\nBuild failed with exit code: {:?}", status.code());
-        std::process::exit(status.code().unwrap_or(1));
-    }
-}
-
-// =============================================================================
-// Inspect command
-// =============================================================================
-
-/// Build an example as PTX and print the generated artifact.
-#[allow(clippy::too_many_arguments)]
-pub fn codegen_inspect_ptx(
-    ctx: &Context,
-    example: &str,
-    arch: Option<&str>,
-    features: Option<&str>,
-    verbose: bool,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-) {
-    let materialization_enabled = materialization_requested(ctx, false).unwrap_or_else(|error| {
-        eprintln!("Error: {error}");
-        std::process::exit(2);
-    });
-
-    if materialization_enabled {
-        eprintln!("Error: inspect requires PTX output, but {MATERIALIZE_ENV} is enabled");
-        std::process::exit(2);
-    }
-
-    let nvvm_ir_enabled = nvvm_ir_requested(ctx).unwrap_or_else(|error| {
-        eprintln!("Error: {error}");
-        std::process::exit(2);
-    });
-
-    if nvvm_ir_enabled {
-        eprintln!("Error: inspect requires PTX output, but CUDA_OXIDE_EMIT_NVVM_IR is enabled");
-        std::process::exit(2);
-    }
-
-    let example_dir = if ctx.is_workspace {
-        resolve_example_dir(ctx, example)
-    } else {
-        ctx.workspace_root.clone()
-    };
-    if load_interop_config(&example_dir).is_some_and(|interop| {
-        interop
-            .device_crates
-            .iter()
-            .any(|device_crate| device_crate.artifact_kind != InteropArtifactKind::Ptx)
-    }) {
-        eprintln!(
-            "Error: inspect requires PTX output, but metadata declares a non-PTX device artifact."
-        );
-        std::process::exit(2);
-    }
-
-    codegen_build(
-        ctx,
-        example,
-        verbose,
-        false,
-        arch,
-        features,
-        None,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-        false,
-    );
-
-    for path in ptx_artifact_paths(&example_dir, example) {
-        print_ptx_artifact(&path).unwrap_or_else(|error| {
-            eprintln!("Error: {error}");
-            std::process::exit(1);
-        });
-    }
-}
-
-// =============================================================================
-// emit-ltoir command
-// =============================================================================
-
-/// Compile a crate's device code to a binary LTOIR artifact in one step.
-///
-/// `cargo oxide build --emit-nvvm-ir` produces NVVM IR, which a consumer then
-/// has to run through libNVVM separately to get linkable LTOIR. This folds both
-/// halves into one command for the Tile-to-SIMT interop workflow (#96): it
-/// builds the crate in NVVM IR mode, then compiles the emitted `<crate>.ll`
-/// with libNVVM `-gen-lto` and writes `<crate>.ltoir` (or `output`) plus the
-/// matching `.target` and `.options` files used for runtime loading and final
-/// nvJitLink policy.
-///
-/// `arch` is required because LTOIR is architecture-specific. It accepts
-/// `sm_XX`, `compute_XX`, or a bare `XX`, all mapped to libNVVM's
-/// `-arch=compute_XX`.
-#[allow(clippy::too_many_arguments)]
-pub fn emit_ltoir(
-    ctx: &Context,
-    example: &str,
-    arch: &str,
-    features: Option<&str>,
-    output: Option<&Path>,
-    verbose: bool,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-) {
-    let example_dir = if ctx.is_workspace {
-        resolve_example_dir(ctx, example)
-    } else {
-        ctx.workspace_root.clone()
-    };
-
-    if load_interop_config(&example_dir).is_some_and(|config| !config.device_crates.is_empty()) {
-        eprintln!("Error: emit-ltoir does not support metadata interop examples.");
-        eprintln!("Point it at a single SIMT device crate instead.");
-        std::process::exit(1);
-    }
-
-    // Normalize once: libNVVM consumes compute_XX, while the compiler records
-    // and nvJitLink consumes the equivalent sm_XX spelling.
-    let parsed_arch = parse_nvvm_arch(arch).unwrap_or_else(|error| {
-        eprintln!("Error: {error}");
-        std::process::exit(1);
-    });
-    let sm_arch = parsed_arch.sm();
-
-    // Step 1: build in NVVM IR mode so the backend writes `<crate>.ll` as
-    // libNVVM-ready NVVM IR. codegen_build exits on build failure. Pass
-    // quiet=true so the intermediate "✓ Build succeeded" line is suppressed;
-    // emit_ltoir prints its own unified summary at the end.
-    codegen_build(
-        ctx,
-        example,
-        verbose,
-        true,
-        Some(&sm_arch),
-        features,
-        None,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-        false,
-    );
-
-    // Step 2: compile that NVVM IR to LTOIR via libNVVM -gen-lto.
-    let ll_path = emitted_ll_path(&example_dir, example);
-    let ir = std::fs::read(&ll_path).unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not read emitted NVVM IR at {}: {e}",
-            ll_path.display()
-        );
-        std::process::exit(1);
-    });
-    let source_options_path = ll_path.with_extension("options");
-    let source_options = std::fs::read_to_string(&source_options_path).unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not read emitted compile options at {}: {e}",
-            source_options_path.display()
-        );
-        std::process::exit(1);
-    });
-    let compile_options = oxide_artifacts::ArtifactCompileOptions::from_sidecar_text(
-        &source_options,
-    )
-    .unwrap_or_else(|e| {
-        eprintln!(
-            "Error: invalid emitted compile options at {}: {e}",
-            source_options_path.display()
-        );
-        std::process::exit(1);
-    });
-
-    let compute_arch = parsed_arch.compute();
-    let ltoir = compile_nvvm_to_ltoir(&ir, example, &parsed_arch, compile_options);
-
-    // Step 3: write the artifact.
-    let out_path = output
-        .map(Path::to_path_buf)
-        .unwrap_or_else(|| default_ltoir_path(&example_dir, example));
-    for metadata_path in [
-        out_path.with_extension("target"),
-        out_path.with_extension("options"),
-    ] {
-        match std::fs::remove_file(&metadata_path) {
-            Ok(()) => {}
-            Err(error) if error.kind() == std::io::ErrorKind::NotFound => {}
-            Err(error) => {
-                eprintln!(
-                    "Error: could not clear stale LTOIR metadata {}: {error}",
-                    metadata_path.display()
-                );
-                std::process::exit(1);
-            }
-        }
-    }
-    std::fs::write(&out_path, &ltoir).unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not write LTOIR to {}: {e}",
-            out_path.display()
-        );
-        std::process::exit(1);
-    });
-    let options_path = out_path.with_extension("options");
-    std::fs::write(&options_path, compile_options.sidecar_text()).unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not write LTOIR compile options to {}: {e}",
-            options_path.display()
-        );
-        std::process::exit(1);
-    });
-    let target_path = out_path.with_extension("target");
-    std::fs::write(
-        &target_path,
-        format!(
-            "{sm_arch}\n{}\n",
-            oxide_artifacts::COMPILE_OPTIONS_TARGET_MARKER
-        ),
-    )
-    .unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not write LTOIR target metadata to {}: {e}",
-            target_path.display()
-        );
-        std::process::exit(1);
-    });
-
-    println!();
-    println!(
-        "✓ LTOIR written to {} ({} bytes, {compute_arch})",
-        out_path.display(),
-        ltoir.len()
-    );
-}
-
-/// Normalize a target architecture to libNVVM's `compute_XX` form.
-///
-/// Accepts `sm_XX` (the form `--arch` and the rest of cargo-oxide use),
-/// `compute_XX` (passed through), or a bare `XX`.
-fn parse_nvvm_arch(
-    arch: &str,
-) -> Result<cuda_artifact_finalizer::CudaArch, cuda_artifact_finalizer::CudaArchParseError> {
-    let normalized = if arch.starts_with("sm_") || arch.starts_with("compute_") {
-        arch.to_string()
-    } else {
-        format!("compute_{arch}")
-    };
-    normalized.parse()
-}
-
-/// Compile NVVM IR text to binary LTOIR with libNVVM `-gen-lto`. Exits with a
-/// diagnostic on any libNVVM failure (the program log is attached to the error).
-///
-fn compile_nvvm_to_ltoir(
-    ir: &[u8],
-    name: &str,
-    arch: &cuda_artifact_finalizer::CudaArch,
-    compile_options: oxide_artifacts::ArtifactCompileOptions,
-) -> Vec<u8> {
-    let compiler = cuda_artifact_finalizer::NvvmCompiler::discover().unwrap_or_else(|e| {
-        eprintln!("Error: could not initialize the CUDA artifact compiler: {e}");
-        eprintln!("libNVVM ships with the CUDA Toolkit at <CUDA>/nvvm/lib64/libnvvm.so.");
-        eprintln!("Run `cargo oxide doctor` to check your toolkit setup.");
-        std::process::exit(1);
-    });
-    let options = finalization_options_from_artifact(arch, compile_options);
-    compiler
-        .compile_nvvm_ir_to_ltoir(name, ir, &options)
-        .unwrap_or_else(|e| {
-            eprintln!("Error: libNVVM -gen-lto compilation failed: {e}");
-            std::process::exit(1);
-        })
-}
-
-fn finalization_options_from_artifact(
-    arch: &cuda_artifact_finalizer::CudaArch,
-    compile_options: oxide_artifacts::ArtifactCompileOptions,
-) -> cuda_artifact_finalizer::FinalizationOptions {
-    let debug = match compile_options.debug_policy() {
-        oxide_artifacts::ArtifactDebugPolicy::None => cuda_artifact_finalizer::DebugPolicy::None,
-        oxide_artifacts::ArtifactDebugPolicy::LineTables => {
-            cuda_artifact_finalizer::DebugPolicy::LineTables
-        }
-        oxide_artifacts::ArtifactDebugPolicy::Full => cuda_artifact_finalizer::DebugPolicy::Full,
-    };
-    cuda_artifact_finalizer::FinalizationOptions::new(arch.clone())
-        .with_fma_contraction(compile_options.fma_contraction_enabled())
-        .with_debug_policy(debug)
-}
-
-/// Device debug-information policy requested on the command line.
-///
-/// Mirrors nvcc: `--lineinfo` is `-lineinfo` (line tables, optimization intact)
-/// and `--device-debug` is `-G` (full debug, libNVVM optimization disabled).
-/// The two are ordered, not exclusive: asking for both yields [`Self::Full`],
-/// because full debug already carries line tables.
-///
-/// This is the CLI surface for a policy that already exists end to end --
-/// `CUDA_OXIDE_DEBUG`, `ArtifactCompileOptions`'s debug bits, and
-/// `FinalizationOptions::with_debug_policy` all predate it.
-#[derive(Clone, Copy, Debug, Default, PartialEq, Eq)]
-pub enum DeviceDebug {
-    /// Request no device debug information (the default).
-    #[default]
-    Off,
-    /// Preserve source line mappings without disabling optimization.
-    LineTables,
-    /// Emit full debug information; MIR optimization is disabled and libNVVM finalization runs unoptimized.
-    Full,
-}
-
-impl DeviceDebug {
-    /// Resolve the two independent CLI booleans into one ordered policy.
-    #[must_use]
-    pub fn from_flags(lineinfo: bool, device_debug: bool) -> Self {
-        match (device_debug, lineinfo) {
-            (true, _) => Self::Full,
-            (false, true) => Self::LineTables,
-            (false, false) => Self::Off,
-        }
-    }
-
-    /// Value for `CUDA_OXIDE_DEBUG`, or `None` when nothing must be exported.
-    ///
-    /// `Off` deliberately returns `None` rather than `"off"`: exporting `off`
-    /// would override a debug level the surrounding environment had already
-    /// asked for, turning an absent flag into an active opt-out.
-    #[must_use]
-    pub fn env_value(self) -> Option<&'static str> {
-        match self {
-            Self::Off => None,
-            Self::LineTables => Some("line"),
-            Self::Full => Some("full"),
-        }
-    }
-}
-
-/// Options for `cargo oxide build -- ...` / `cargo oxide test -- ...`.
-#[derive(Clone, Copy)]
-pub struct CargoPassthroughOptions<'a> {
-    pub verbose: bool,
-    pub emit_nvvm_ir: bool,
-    pub arch: Option<&'a str>,
-    pub features: Option<&'a str>,
-    pub cargo_target_dir: Option<&'a Path>,
-    pub device_codegen_crate: Option<&'a str>,
-    pub device_cfgs: &'a [String],
-    pub no_fmad: bool,
-    pub unchecked_indexing: bool,
-    pub materialize_cubin: bool,
-    pub device_debug: DeviceDebug,
-}
-
-/// Cargo operations supported by the passthrough path.
-///
-/// The subcommand determines who owns profile-related rustc flags: regular
-/// builds retain cuda-oxide's release-like defaults, while tests leave the
-/// selected Cargo profile intact (including `--release` and `--profile`).
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
-pub enum CargoPassthroughSubcommand {
-    Build,
-    Test,
-}
-
-impl CargoPassthroughSubcommand {
-    fn as_str(self) -> &'static str {
-        match self {
-            Self::Build => "build",
-            Self::Test => "test",
-        }
-    }
-
-    fn codegen_profile(self) -> CodegenProfilePolicy {
-        match self {
-            Self::Build => CodegenProfilePolicy::ReleaseLike,
-            Self::Test => CodegenProfilePolicy::CargoSelected,
-        }
-    }
-}
-
-fn normalize_device_codegen_crates(raw: &str) -> Result<String, String> {
-    let mut normalized = Vec::new();
-    for item in raw.split(',') {
-        let name = item.trim().replace('-', "_");
-        if name.is_empty() {
-            return Err(
-                "--device-codegen-crate requires a comma-separated list without empty entries"
-                    .to_string(),
-            );
-        }
-        if !name
-            .chars()
-            .all(|character| character.is_ascii_alphanumeric() || character == '_')
-        {
-            return Err(format!(
-                "invalid device-codegen crate name `{item}`; use Cargo crate names separated by commas"
-            ));
-        }
-        if !normalized.contains(&name) {
-            normalized.push(name);
-        }
-    }
-    Ok(normalized.join(","))
-}
-
-fn project_config_env<'a>(ctx: &'a Context, key: &str) -> Option<&'a str> {
-    ctx.config
-        .env
-        .iter()
-        .find(|(configured_key, _)| configured_key == key)
-        .map(|(_, value)| value.as_str())
-}
-
-fn configured_device_codegen_crates(
-    ctx: &Context,
-    explicit: Option<&str>,
-) -> Result<Option<String>, String> {
-    let inherited = std::env::var(DEVICE_CODEGEN_CRATE_ENV).ok();
-    resolve_device_codegen_crates(
-        explicit,
-        inherited.as_deref(),
-        project_config_env(ctx, DEVICE_CODEGEN_CRATE_ENV),
-    )
-}
-
-fn resolve_device_codegen_crates(
-    explicit: Option<&str>,
-    inherited: Option<&str>,
-    configured: Option<&str>,
-) -> Result<Option<String>, String> {
-    if let Some(explicit) = explicit {
-        return normalize_device_codegen_crates(explicit).map(Some);
-    }
-
-    inherited
-        .or(configured)
-        .filter(|value| !value.trim().is_empty())
-        .map(normalize_device_codegen_crates)
-        .transpose()
-}
-
-/// The ambient environment, in the shape the fingerprint helpers consume.
-///
-/// Split out so both fingerprint wrappers share one collection, and so their
-/// `_with_env` counterparts stay the only entry points a unit test needs.
-fn inherited_process_env() -> BTreeMap<String, Vec<u8>> {
-    std::env::vars_os()
-        .filter_map(|(key, value)| {
-            key.into_string()
-                .ok()
-                .map(|key| (key, value.as_encoded_bytes().to_vec()))
-        })
-        .collect()
-}
-
-fn passthrough_codegen_fingerprint(
-    ctx: &Context,
-    opts: &CargoPassthroughOptions<'_>,
-    owner_filter: Option<&str>,
-    target_arch: Option<&str>,
-    materialization: &MaterializationMode,
-) -> String {
-    passthrough_codegen_fingerprint_with_env(
-        ctx,
-        opts,
-        owner_filter,
-        target_arch,
-        materialization,
-        &inherited_process_env(),
-    )
-}
-
-fn passthrough_codegen_fingerprint_with_env(
-    ctx: &Context,
-    opts: &CargoPassthroughOptions<'_>,
-    owner_filter: Option<&str>,
-    target_arch: Option<&str>,
-    materialization: &MaterializationMode,
-    inherited_env: &BTreeMap<String, Vec<u8>>,
-) -> String {
-    let mut effective_env = BTreeMap::new();
-
-    // Project-configured CUDA_OXIDE_* variables are defaults. Mirror the same
-    // parent override rule as `apply_config_env` so changes that can affect
-    // codegen also change Cargo's rustflags fingerprint.
-    for (key, configured_value) in &ctx.config.env {
-        if !key.starts_with("CUDA_OXIDE_") {
-            continue;
-        }
-        if let Some(value) = inherited_env.get(key) {
-            // Keep the platform encoding. Presence-only backend switches such
-            // as CUDA_OXIDE_NO_FMA remain effective even when their value is
-            // not Unicode, so dropping those bytes could reuse stale code.
-            effective_env.insert(key.clone(), value.clone());
-        } else {
-            effective_env.insert(key.clone(), configured_value.as_bytes().to_vec());
-        }
-    }
-    // Capture backend settings inherited outside project config, including
-    // current and future CUDA_OXIDE_* switches.
-    for (key, value) in inherited_env.iter().filter(|(key, _)| {
-        key.starts_with("CUDA_OXIDE_") && key.as_str() != CODEGEN_FINGERPRINT_ENV
-    }) {
-        effective_env.insert(key.clone(), value.clone());
-    }
-
-    // These are wrapper-owned semantic values. Normalize away inherited
-    // false/stale handshakes before inserting the effective materialization
-    // state below, so no-op values do not create distinct Cargo identities.
-    effective_env.remove(CODEGEN_FINGERPRINT_ENV);
-    effective_env.remove(MATERIALIZE_ENV);
-    effective_env.remove(EXPECTED_PROVENANCE_ENV);
-    // Descriptor identity only accelerates verification; artifact identity is
-    // already represented by the content-derived provenance above.
-    effective_env.remove(MATERIALIZER_HANDSHAKE_ENV);
-
-    if opts.verbose {
-        effective_env.insert("CUDA_OXIDE_VERBOSE".to_string(), b"1".to_vec());
-    }
-    if opts.no_fmad {
-        effective_env.insert("CUDA_OXIDE_NO_FMA".to_string(), b"1".to_vec());
-    }
-    if opts.unchecked_indexing {
-        effective_env.insert("CUDA_OXIDE_UNCHECKED_INDEXING".to_string(), b"1".to_vec());
-    }
-    if let Some(level) = opts.device_debug.env_value() {
-        effective_env.insert("CUDA_OXIDE_DEBUG".to_string(), level.as_bytes().to_vec());
-    }
-    if opts.emit_nvvm_ir || materialization.enabled() {
-        effective_env.insert("CUDA_OXIDE_EMIT_NVVM_IR".to_string(), b"1".to_vec());
-    }
-    if let Some(prepared) = &materialization.prepared {
-        effective_env.insert(MATERIALIZE_ENV.to_string(), b"1".to_vec());
-        effective_env.insert(
-            EXPECTED_PROVENANCE_ENV.to_string(),
-            prepared.provenance_sha256_hex.as_bytes().to_vec(),
-        );
-    }
-    if let Some(target_arch) = target_arch {
-        effective_env.insert(
-            "CUDA_OXIDE_TARGET".to_string(),
-            target_arch.as_bytes().to_vec(),
-        );
-    }
-    if let Some(owner_filter) = owner_filter {
-        effective_env.insert(
-            DEVICE_CODEGEN_CRATE_ENV.to_string(),
-            owner_filter.as_bytes().to_vec(),
-        );
-    }
-
-    // SHA-256 over length-delimited key/value pairs. The complete digest is
-    // tracked by device-owning procedural macros, so settings are neither
-    // exposed verbatim in diagnostics nor reduced to a small collision space.
-    let mut hash = sha2::Sha256::new();
-    for (key, value) in effective_env {
-        update_codegen_fingerprint_hash(&mut hash, key.as_bytes());
-        update_codegen_fingerprint_hash(&mut hash, &value);
-    }
-    finish_codegen_fingerprint(hash)
-}
-
-fn update_codegen_fingerprint_hash(hash: &mut sha2::Sha256, bytes: &[u8]) {
-    use sha2::Digest as _;
-
-    hash.update((bytes.len() as u64).to_le_bytes());
-    hash.update(bytes);
-}
-
-fn finish_codegen_fingerprint(hash: sha2::Sha256) -> String {
-    use sha2::Digest as _;
-
-    let digest: [u8; 32] = hash.finalize().into();
-    digest_hex(&digest)
-}
-
-/// Track sanitizer-only device output settings in crates that declare device
-/// code, without invalidating their host-only dependency graph.
-#[allow(clippy::too_many_arguments)]
-fn sanitize_codegen_fingerprint(
-    ctx: &Context,
-    verbose: bool,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-    target_arch: Option<&str>,
-    detected_device_arch: Option<&str>,
-    ptx_dir: Option<&Path>,
-    materialization: &MaterializationMode,
-) -> String {
-    sanitize_codegen_fingerprint_with_env(
-        ctx,
-        verbose,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-        target_arch,
-        detected_device_arch,
-        ptx_dir,
-        materialization,
-        &inherited_process_env(),
-    )
-}
-
-/// `sanitize_codegen_fingerprint` with the inherited environment injected, the
-/// counterpart to `passthrough_codegen_fingerprint_with_env`.
-#[allow(clippy::too_many_arguments)]
-fn sanitize_codegen_fingerprint_with_env(
-    ctx: &Context,
-    verbose: bool,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-    target_arch: Option<&str>,
-    detected_device_arch: Option<&str>,
-    ptx_dir: Option<&Path>,
-    materialization: &MaterializationMode,
-    inherited_env: &BTreeMap<String, Vec<u8>>,
-) -> String {
-    let opts = CargoPassthroughOptions {
-        verbose,
-        emit_nvvm_ir: false,
-        arch: target_arch,
-        features: None,
-        cargo_target_dir: None,
-        device_codegen_crate: None,
-        device_cfgs: &[],
-        no_fmad,
-        unchecked_indexing,
-        materialize_cubin: materialization.enabled(),
-        device_debug,
-    };
-    let base = passthrough_codegen_fingerprint_with_env(
-        ctx,
-        &opts,
-        None,
-        target_arch,
-        materialization,
-        inherited_env,
-    );
-    let mut hash = sha2::Sha256::new();
-    for bytes in [
-        "sanitize-line-tables-v1".as_bytes(),
-        base.as_bytes(),
-        detected_device_arch.unwrap_or("").as_bytes(),
-    ] {
-        update_codegen_fingerprint_hash(&mut hash, bytes);
-    }
-    if let Some(ptx_dir) = ptx_dir {
-        update_codegen_fingerprint_hash(&mut hash, ptx_dir.as_os_str().as_encoded_bytes());
-    }
-    finish_codegen_fingerprint(hash)
-}
-
-#[allow(clippy::too_many_arguments)]
-fn standard_codegen_fingerprint(
-    ctx: &Context,
-    verbose: bool,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-    emit_nvvm_ir: bool,
-    target_arch: Option<&str>,
-    detected_device_arch: Option<&str>,
-    materialization: &MaterializationMode,
-) -> String {
-    let opts = CargoPassthroughOptions {
-        verbose,
-        emit_nvvm_ir,
-        arch: target_arch,
-        features: None,
-        cargo_target_dir: None,
-        device_codegen_crate: None,
-        device_cfgs: &[],
-        no_fmad,
-        unchecked_indexing,
-        materialize_cubin: materialization.enabled(),
-        device_debug,
-    };
-    let base = passthrough_codegen_fingerprint(ctx, &opts, None, target_arch, materialization);
-    let mut hash = sha2::Sha256::new();
-    for bytes in [
-        "standard-codegen-v1".as_bytes(),
-        base.as_bytes(),
-        detected_device_arch.unwrap_or("").as_bytes(),
-    ] {
-        update_codegen_fingerprint_hash(&mut hash, bytes);
-    }
-    finish_codegen_fingerprint(hash)
-}
-
-fn pipeline_codegen_fingerprint(
-    ctx: &Context,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-    emit_nvvm_ir: bool,
-    target_arch: Option<&str>,
-    materialization: &MaterializationMode,
-) -> String {
-    let base = standard_codegen_fingerprint(
-        ctx,
-        true,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-        emit_nvvm_ir,
-        target_arch,
-        None,
-        materialization,
-    );
-    let mut hash = sha2::Sha256::new();
-    for value in [
-        base.as_str(),
-        "CUDA_OXIDE_SHOW_RUSTC_MIR=1",
-        "CUDA_OXIDE_DUMP_MIR=1",
-        "CUDA_OXIDE_DUMP_LLVM=1",
-    ] {
-        update_codegen_fingerprint_hash(&mut hash, value.as_bytes());
-    }
-    finish_codegen_fingerprint(hash)
-}
-
-#[allow(clippy::too_many_arguments)]
-fn interop_codegen_fingerprint(
-    ctx: &Context,
-    verbose: bool,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-    target_arch: Option<&str>,
-    detected_device_arch: Option<&str>,
-    artifact_dir: &Path,
-    emit_nvvm_ir: bool,
-    device_features: Option<&str>,
-    sanitizer_line_tables: bool,
-    materialization: &MaterializationMode,
-) -> String {
-    let base = standard_codegen_fingerprint(
-        ctx,
-        verbose,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-        emit_nvvm_ir,
-        target_arch,
-        detected_device_arch,
-        materialization,
-    );
-    let mut hash = sha2::Sha256::new();
-    for bytes in [
-        "interop-codegen-v1".as_bytes(),
-        base.as_bytes(),
-        if sanitizer_line_tables {
-            b"line-tables"
-        } else {
-            b"default-debug"
-        },
-        artifact_dir.as_os_str().as_encoded_bytes(),
-        device_features.unwrap_or("").as_bytes(),
-    ] {
-        update_codegen_fingerprint_hash(&mut hash, bytes);
-    }
-    finish_codegen_fingerprint(hash)
-}
-
-fn backend_artifact_digest(path: &Path) -> Result<String, String> {
-    use sha2::{Digest, Sha256};
-    use std::io::Read;
-
-    let mut hasher = Sha256::new();
-    if path == Path::new("llvm") {
-        hasher.update(b"rustc built-in LLVM backend");
-        let digest: [u8; 32] = hasher.finalize().into();
-        return Ok(digest_hex(&digest));
-    }
-
-    let canonical = path
-        .canonicalize()
-        .map_err(|error| format!("could not resolve backend {}: {error}", path.display()))?;
-    let mut file = std::fs::File::open(&canonical).map_err(|error| {
-        format!(
-            "could not open backend {} for fingerprinting: {error}",
-            canonical.display()
-        )
-    })?;
-    let mut hasher = Sha256::new();
-    let mut chunk = [0_u8; 64 * 1024];
-    loop {
-        let read = file.read(&mut chunk).map_err(|error| {
-            format!(
-                "could not read backend {} for fingerprinting: {error}",
-                canonical.display()
-            )
-        })?;
-        if read == 0 {
-            break;
-        }
-        hasher.update(&chunk[..read]);
-    }
-    let digest: [u8; 32] = hasher.finalize().into();
-    Ok(digest_hex(&digest))
-}
-
-fn cargo_passthrough_command(
-    ctx: &Context,
-    cargo_subcommand: CargoPassthroughSubcommand,
-    opts: &CargoPassthroughOptions<'_>,
-    cargo_args: &[String],
-) -> Result<Command, String> {
-    cargo_passthrough_command_with_env(
-        ctx,
-        cargo_subcommand,
-        opts,
-        cargo_args,
-        std::env::var_os(MATERIALIZE_ENV),
-    )
-}
-
-/// `cargo_passthrough_command` with the ambient
-/// `CUDA_OXIDE_MATERIALIZE_CUBIN` injected.
-///
-/// Unit tests must call this with `None`: the ambient value outranks
-/// `opts.materialize_cubin`, so an exported one turns materialization on and
-/// sends the test into `discover_materializer_provenance`, which re-executes
-/// `current_exe` -- the libtest binary under `cargo test` -- and then exits the
-/// process over the unusable digest, taking the whole suite with it.
-fn cargo_passthrough_command_with_env(
-    ctx: &Context,
-    cargo_subcommand: CargoPassthroughSubcommand,
-    opts: &CargoPassthroughOptions<'_>,
-    cargo_args: &[String],
-    materialize_env: Option<std::ffi::OsString>,
-) -> Result<Command, String> {
-    let target_arch = configured_arch(ctx, opts.arch);
-    let materialization = prepare_materialization_with_env(
-        ctx,
-        opts.materialize_cubin,
-        opts.arch,
-        opts.emit_nvvm_ir,
-        materialize_env,
-    );
-    let owner_filter = configured_device_codegen_crates(ctx, opts.device_codegen_crate)?;
-    // Device-owning macros track this identity in their crate dep-info. Keep it
-    // out of global rustflags so host-only dependencies retain one cache key.
-    let fingerprint = passthrough_codegen_fingerprint(
-        ctx,
-        opts,
-        owner_filter.as_deref(),
-        target_arch,
-        &materialization,
-    );
-    let mut cmd = Command::new("cargo");
-    cmd.arg(cargo_subcommand.as_str());
-    if let Some(features) = opts.features {
-        cmd.args(["--features", features]);
-    }
-    cmd.args(cargo_args).current_dir(&ctx.workspace_root);
-
-    // Project configuration provides defaults. Explicit wrapper flags and
-    // internal compiler requirements are applied afterward and therefore win.
-    apply_common_codegen_env(
-        &mut cmd,
-        ctx,
-        opts.verbose,
-        opts.no_fmad,
-        opts.unchecked_indexing,
-        opts.device_debug,
-    );
-    apply_codegen_configuration(
-        &mut cmd,
-        ctx,
-        cargo_subcommand.codegen_profile(),
-        opts.device_cfgs,
-        &fingerprint,
-    )?;
-
-    if let Some(cargo_target_dir) = opts.cargo_target_dir {
-        cmd.env("CARGO_TARGET_DIR", cargo_target_dir);
-    }
-    if let Some(owner_filter) = owner_filter {
-        cmd.env(DEVICE_CODEGEN_CRATE_ENV, owner_filter);
-    }
-    apply_output_mode(&mut cmd, opts.emit_nvvm_ir, target_arch, &materialization);
-    Ok(cmd)
-}
-
-/// Run an arbitrary Cargo build-like subcommand through the cuda-oxide backend.
-///
-/// Unlike example mode, this does not touch source files or clean generated
-/// artifacts. It is intended for final-target workspace builds where Cargo's
-/// incremental behavior should remain intact.
-pub fn codegen_cargo_passthrough(
-    ctx: &Context,
-    cargo_subcommand: CargoPassthroughSubcommand,
-    opts: CargoPassthroughOptions<'_>,
-    cargo_args: &[String],
-) {
-    let cargo_subcommand_name = cargo_subcommand.as_str();
-    println!("=========================================");
-    println!("RUSTC-CODEGEN-CUDA CARGO {}", cargo_subcommand_name);
-    println!("=========================================");
-    println!();
-
-    let mut cmd = cargo_passthrough_command(ctx, cargo_subcommand, &opts, cargo_args)
-        .unwrap_or_else(|error| {
-            eprintln!("Error: {error}");
-            std::process::exit(2);
-        });
-
-    let displayed_args: Vec<_> = cmd
-        .get_args()
-        .skip(1)
-        .map(|arg| arg.to_string_lossy().into_owned())
-        .collect();
-    if displayed_args.is_empty() {
-        println!("Running cargo {}...", cargo_subcommand_name);
-    } else {
-        println!(
-            "Running cargo {} {}...",
-            cargo_subcommand_name,
-            displayed_args.join(" ")
-        );
-    }
-    println!();
-
-    let status = cmd.status().expect("Failed to run cargo");
-    if !status.success() {
-        eprintln!(
-            "\nCargo {} failed with exit code: {:?}",
-            cargo_subcommand_name,
-            status.code()
-        );
-        std::process::exit(status.code().unwrap_or(1));
-    }
-
-    println!();
-    println!("✓ Cargo {} succeeded", cargo_subcommand_name);
-}
-
-// =============================================================================
-// Pipeline command
-// =============================================================================
-
-/// Show verbose pipeline progress and the available intermediate artifacts.
-///
-/// Enables all diagnostic env vars (`CUDA_OXIDE_VERBOSE`, `SHOW_RUSTC_MIR`,
-/// `DUMP_MIR`, `DUMP_LLVM`) so the user can see MIR collection, the
-/// `dialect-mir` module (pre- and post-`mem2reg`), the LLVM dialect
-/// module, textual LLVM IR, and the final PTX or NVVM IR. After the build,
-/// generated artifacts are printed to stdout.
-#[allow(clippy::too_many_arguments)]
-pub fn codegen_show_pipeline(
-    ctx: &Context,
-    example: &str,
-    emit_nvvm_ir: bool,
-    arch: Option<&str>,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-    materialize_cubin: bool,
-) {
-    let target_arch = configured_arch(ctx, arch);
-    let materialization = prepare_materialization(ctx, materialize_cubin, arch, emit_nvvm_ir);
-    let example_dir = if ctx.is_workspace {
-        resolve_example_dir(ctx, example)
-    } else {
-        ctx.workspace_root.clone()
-    };
-
-    if load_interop_config(&example_dir).is_some_and(|config| !config.device_crates.is_empty()) {
-        reject_interop_output_mode(emit_nvvm_ir, &materialization);
-    }
-
-    clean_generated_files(&example_dir, example);
-
-    println!("=========================================");
-    println!("RUSTC-CODEGEN-CUDA PIPELINE: {}", example);
-    println!("=========================================");
-    println!();
-    let target_arch_label = configured_arch_label(ctx, arch);
-    match (
-        materialization.enabled(),
-        emit_nvvm_ir,
-        target_arch_label.as_deref(),
-    ) {
-        (true, _, Some(target_arch)) => {
-            println!("Output format: materialized cubin (arch: {target_arch})")
-        }
-        (false, true, Some(target_arch)) => {
-            println!("Output format: NVVM IR (arch: {})", target_arch)
-        }
-        (false, false, Some(target_arch)) => {
-            println!("Output format: PTX (arch override: {})", target_arch)
-        }
-        (false, false, None) => println!("Output format: PTX (auto-detected arch)"),
-        (true, _, None) | (false, true, None) => {
-            unreachable!("IR/final materialization requires a configured architecture")
-        }
-    }
-    println!();
-    println!("Required flags (applied via CARGO_ENCODED_RUSTFLAGS):");
-    println!("  -C opt-level=3              MIR optimization");
-    println!("  -C debug-assertions=off     Remove debug checks");
-    println!("  -Z mir-enable-passes=-JumpThreading");
-    println!("                              Prevent barrier duplication");
-    println!("  -Z always-encode-mir        Emit MIR for all reachable device deps");
-    println!();
-    println!("Note: panic=abort is NOT required - the codegen backend treats");
-    println!("      unwind paths as unreachable (CUDA toolchain limitation, not HW).");
-    println!();
-
-    touch_main_rs(&example_dir);
-
-    let mut cmd = Command::new("cargo");
-    cmd.args(["build", "--release"]).current_dir(&example_dir);
-
-    // The shared codegen env (including the CLI debug level) must be on the
-    // command before the rustflags decision below: a full-debug request adds
-    // `-Zmir-opt-level=0`, and `apply_codegen_rustflags` reads the command's
-    // `CUDA_OXIDE_DEBUG` to see it. This is the same ordering build/run use.
-    apply_common_codegen_env(
-        &mut cmd,
-        ctx,
-        true,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-    );
-    cmd.env("CUDA_OXIDE_SHOW_RUSTC_MIR", "1");
-    cmd.env("CUDA_OXIDE_DUMP_MIR", "1");
-    cmd.env("CUDA_OXIDE_DUMP_LLVM", "1");
-    let fingerprint = pipeline_codegen_fingerprint(
-        ctx,
-        no_fmad,
-        unchecked_indexing,
-        device_debug,
-        emit_nvvm_ir,
-        target_arch,
-        &materialization,
-    );
-    apply_codegen_configuration_or_exit(
-        &mut cmd,
-        ctx,
-        CodegenProfilePolicy::ReleaseLike,
-        &[],
-        &fingerprint,
-    );
-
-    apply_output_mode(&mut cmd, emit_nvvm_ir, target_arch, &materialization);
-
-    println!("Building {}...", example);
-    println!();
-
-    let status = cmd.status().expect("Failed to run cargo");
-
-    if !status.success() {
-        eprintln!("\nBuild failed with exit code: {:?}", status.code());
-        std::process::exit(status.code().unwrap_or(1));
-    }
-
-    show_generated_artifacts(&example_dir, example);
-}
-
-// =============================================================================
-// Debug command
-// =============================================================================
-
-/// Build with debug info and launch cuda-gdb (or cgdb).
-///
-/// Compiles the example with `-C debuginfo=2` on top of the normal release
-/// flags, then launches the debugger on the resulting binary. Prints a
-/// quick-reference cheat sheet for common cuda-gdb commands before handing
-/// control to the debugger.
-#[allow(clippy::too_many_arguments)]
-pub fn codegen_debug(
-    ctx: &Context,
-    example: &str,
-    arch: Option<&str>,
-    features: Option<&str>,
-    bin: Option<&str>,
-    use_cgdb: bool,
-    use_tui: bool,
-    materialize_cubin: bool,
-) {
-    let example_dir = if ctx.is_workspace {
-        resolve_example_dir(ctx, example)
-    } else {
-        ctx.workspace_root.clone()
-    };
-    let target_arch = configured_arch(ctx, arch);
-    let materialization = prepare_materialization(ctx, materialize_cubin, arch, false);
-    if load_interop_config(&example_dir).is_some_and(|config| !config.device_crates.is_empty()) {
-        reject_interop_output_mode(false, &materialization);
-    }
-
-    let cuda_gdb = find_cuda_toolkit_executable(ctx, "cuda-gdb", CUDA_GDB_FALLBACK_PATHS)
-        .unwrap_or_else(|| {
-            eprintln!("Error: cuda-gdb not found!");
-            eprintln!();
-            eprintln!("Make sure CUDA toolkit is installed and cuda-gdb is in your PATH");
-            eprintln!("or configured CUDA toolkit root:");
-            eprintln!("  export PATH=\"/usr/local/cuda/bin:$PATH\"");
-            eprintln!("  export CUDA_TOOLKIT_PATH=/usr/local/cuda");
-            std::process::exit(1);
-        });
-
-    let cgdb_path = if use_cgdb {
-        Some(find_executable("cgdb", &[]).unwrap_or_else(|| {
-            eprintln!("Error: cgdb not found!");
-            eprintln!("Install with: sudo apt install cgdb");
-            std::process::exit(1);
-        }))
-    } else {
-        None
-    };
-
-    let detected_device_arch = detect_run_target_arch(target_arch, materialization.enabled());
-
-    if let Some(bin) = bin {
-        println!("Building {} (bin: {}) with debug info...", example, bin);
-    } else {
-        println!("Building {} with debug info...", example);
-    }
-    if let Some(dev) = detected_device_arch.as_deref() {
-        println!("Detected GPU arch: {dev} (via nvidia-smi)");
-    }
-
-    clean_generated_files(&example_dir, example);
-
-    touch_main_rs(&example_dir);
-
-    let mut cmd = Command::new("cargo");
-    cmd.args(["build", "--release"]).current_dir(&example_dir);
-
-    if let Some(bin) = bin {
-        cmd.args(["--bin", bin]);
-    }
-    if let Some(features) = features {
-        cmd.args(["--features", features]);
-    }
-
-    apply_config_env(&mut cmd, ctx);
-    let fingerprint = standard_codegen_fingerprint(
-        ctx,
-        false,
-        false,
-        false,
-        DeviceDebug::Off,
-        false,
-        target_arch,
-        detected_device_arch.as_deref(),
-        &materialization,
-    );
-    apply_codegen_configuration_or_exit(
-        &mut cmd,
-        ctx,
-        CodegenProfilePolicy::ReleaseLikeWithDebugInfo,
-        &[],
-        &fingerprint,
-    );
-    cmd.env("CARGO_PROFILE_RELEASE_DEBUG", "2");
-    apply_output_mode(&mut cmd, false, target_arch, &materialization);
-    apply_device_arch_hint(&mut cmd, target_arch, detected_device_arch.as_deref());
-    apply_ld_library_path(&mut cmd, ctx);
-
-    let binary =
-        run_cargo_build_for_executable(&mut cmd, &example_dir, bin).unwrap_or_else(|message| {
-            eprintln!("Failed to build {example}: {message}");
-            std::process::exit(1);
-        });
-    if !binary.exists() {
-        eprintln!(
-            "Error: Cargo reported executable artifact {}, but it does not exist",
-            binary.display()
-        );
-        std::process::exit(1);
-    }
-
-    if cgdb_path.is_some() {
-        println!("Launching cgdb (cuda-gdb frontend)...");
-    } else {
-        println!(
-            "Launching cuda-gdb{}...",
-            if use_tui { " (TUI mode)" } else { "" }
-        );
-    }
-    println!();
-    println!("Quick reference:");
-    println!("  set cuda break_on_launch application");
-    println!("                           - Break at start of any kernel");
-    println!("  run                      - Start the program");
-    println!("  info cuda kernels        - List active kernels");
-    println!("  info cuda threads        - List GPU threads");
-    println!("  cuda thread (0,0,0)      - Switch to thread");
-    println!("  cuda block (0,0,0)       - Switch to block");
-    println!("  print <var>              - Print variable");
-    println!("  next / step / continue   - Execution control");
-    println!("  quit                     - Exit debugger");
-    if cgdb_path.is_some() {
-        println!();
-        println!("cgdb shortcuts:");
-        println!("  Esc                      - Focus source window (vim keys work)");
-        println!("  i                        - Focus command window");
-        println!("  space                    - Set breakpoint on current line");
-        println!("  o                        - Open file dialog");
-    } else if use_tui {
-        println!();
-        println!("TUI shortcuts:");
-        println!("  Ctrl+x a                 - Toggle TUI mode");
-        println!("  Ctrl+x 2                 - Split view (source + asm)");
-        println!("  Ctrl+l                   - Refresh screen");
-    }
-    println!();
-
-    let status = if let Some(cgdb) = cgdb_path {
-        Command::new(cgdb)
-            .arg("-d")
-            .arg(&cuda_gdb)
-            .arg(&binary)
-            .current_dir(&example_dir)
-            .status()
-            .expect("Failed to launch cgdb")
-    } else {
-        let mut gdb_cmd = Command::new(&cuda_gdb);
-        if use_tui {
-            gdb_cmd.arg("--tui");
-        }
-        gdb_cmd.arg(&binary);
-        gdb_cmd.current_dir(&example_dir);
-        gdb_cmd.status().expect("Failed to launch cuda-gdb")
-    };
-
-    if !status.success() {
-        std::process::exit(status.code().unwrap_or(1));
-    }
-}
-
-// =============================================================================
-// Fmt command
-// =============================================================================
-
-/// Format (or check formatting of) every scope the `fmt` CI gate checks.
-///
-/// `.github/workflows/fmt.yml` checks four: the root workspace, the codegen
-/// backend crate, the cuda-macros device-only fixture, and every `Cargo.toml`
-/// under `examples/`, nested ones included. This mirrors that set on purpose --
-/// the reason CONTRIBUTING tells contributors to prefer this command over a
-/// bare `cargo fmt` is so the gate cannot fail on code they had no way to
-/// format, which only holds while the two cover the same ground.
-///
-/// In `check` mode, reports which files need formatting without modifying them.
-pub fn format_all(ctx: &Context, check: bool) {
-    let mode = if check { "Checking" } else { "Formatting" };
-    let mut failed = false;
-
-    println!("📦 {} root workspace...", mode);
-    if !run_cargo_fmt(&ctx.workspace_root, check) {
-        failed = true;
-    }
-
-    println!("📦 {} rustc-codegen-cuda...", mode);
-    if !run_cargo_fmt(&ctx.codegen_crate, check) {
-        failed = true;
-    }
-
-    // Its own `[workspace]`, so neither run above reaches it and the examples
-    // walk below never sees it either. The gate carries a dedicated step for
-    // exactly this reason.
-    let fixture = ctx
-        .workspace_root
-        .join("crates")
-        .join("cuda-macros")
-        .join("tests")
-        .join("device-only");
-    if fixture.join("Cargo.toml").is_file() {
-        println!("📦 {} cuda-macros device-only fixture...", mode);
-        if !run_cargo_fmt(&fixture, check) {
-            failed = true;
-        }
-    }
-
-    // One `--manifest-path` run per manifest found, rather than `cargo fmt
-    // --all` once per top-level example directory. Both reasons match the gate:
-    //
-    //   * `--all` stops at a nested `[workspace]` boundary, and two examples
-    //     declare one (`cutile_inter_kernel/simt`,
-    //     `interop_cubin_identity/device`), so neither was ever formatted here.
-    //   * `--all` also formats an example's path dependencies, which means
-    //     re-formatting the large shared workspaces once per example.
-    let mut manifests = Vec::new();
-    collect_example_manifests(&ctx.examples_dir, &mut manifests);
-    manifests.sort();
-
-    for manifest in &manifests {
-        let label = manifest
-            .parent()
-            .and_then(|dir| dir.strip_prefix(&ctx.examples_dir).ok())
-            .unwrap_or(Path::new("."))
-            .display()
-            .to_string();
-        println!("📦 {} example: {}...", mode, label);
-        if !run_cargo_fmt_manifest(manifest, check) {
-            failed = true;
-        }
-    }
-
-    if failed {
-        if check {
-            eprintln!();
-            eprintln!("❌ Some files need formatting. Run: cargo oxide fmt");
-        } else {
-            eprintln!();
-            eprintln!("⚠️  Some formatting commands failed (see above)");
-        }
-        std::process::exit(1);
-    } else {
-        println!();
-        if check {
-            println!("✅ All files are properly formatted");
-        } else {
-            println!("✅ All crates formatted");
-        }
-    }
-}
-
-/// Run `cargo fmt --all` in a single directory. Returns `true` on success.
-fn run_cargo_fmt(dir: &Path, check: bool) -> bool {
-    let mut cmd = Command::new("cargo");
-    cmd.arg("fmt").arg("--all").current_dir(dir);
-
-    if check {
-        cmd.arg("--check");
-    }
-
-    run_fmt_command(cmd)
-}
-
-/// Run `cargo fmt` for one manifest. Returns `true` on success.
-///
-/// No `--all`: the caller walks every manifest, so a workspace member is
-/// visited through its own manifest rather than through its parent's.
-fn run_cargo_fmt_manifest(manifest: &Path, check: bool) -> bool {
-    let mut cmd = Command::new("cargo");
-    cmd.arg("fmt").arg("--manifest-path").arg(manifest);
-
-    if check {
-        cmd.arg("--check");
-    }
-
-    run_fmt_command(cmd)
-}
-
-fn run_fmt_command(mut cmd: Command) -> bool {
-    match cmd.status() {
-        Ok(status) => status.success(),
-        Err(e) => {
-            eprintln!("  Failed to run cargo fmt: {}", e);
-            false
-        }
-    }
-}
-
-/// Collect every `Cargo.toml` under `dir`, recursively.
-///
-/// Mirrors the gate's `examples/**/Cargo.toml` glob, with one difference that
-/// only matters off CI: `target` directories are skipped. A fresh checkout has
-/// none, but a working tree does, and a packaged or vendored manifest under one
-/// is not a crate this repository formats.
-fn collect_example_manifests(dir: &Path, out: &mut Vec<PathBuf>) {
-    let manifest = dir.join("Cargo.toml");
-    if manifest.is_file() {
-        out.push(manifest);
-    }
-
-    let Ok(entries) = std::fs::read_dir(dir) else {
-        return;
-    };
-
-    for entry in entries.flatten() {
-        let path = entry.path();
-        if !path.is_dir() {
-            continue;
-        }
-        let name = entry.file_name();
-        let name = name.to_string_lossy();
-        if name == "target" || name.starts_with('.') {
-            continue;
-        }
-        collect_example_manifests(&path, out);
-    }
-}
-
-// =============================================================================
-// Doctor command
-// =============================================================================
-
-/// Parsed contents of a `rust-toolchain.toml` pin.
-#[derive(Clone, Debug, Eq, PartialEq)]
-struct RustToolchainPin {
-    channel: String,
-    components: Vec<String>,
-}
-
-/// Components that doctor treats as hard requirements for the cuda-oxide
-/// pipeline even if `rust-toolchain.toml` stops listing them: `rust-src`
-/// (device-side core sources), `rustc-dev` (rustc_private, required to build
-/// the codegen backend), and `llvm-tools`.
-const DOCTOR_REQUIRED_COMPONENTS: &[&str] = &["rust-src", "rustc-dev", "llvm-tools"];
-
-/// The components doctor verifies for a pin: everything the pin itself lists,
-/// plus the [`DOCTOR_REQUIRED_COMPONENTS`] floor.
-///
-/// rustup auto-installs every component named in `rust-toolchain.toml` when it
-/// installs the pinned toolchain, so a pinned component that is absent from
-/// `rustup component list --installed` means a broken or manually trimmed
-/// install and is worth failing doctor over. The floor guards against a future
-/// edit of the pin file dropping a component the pipeline genuinely needs.
-fn doctor_verified_components(pin: &RustToolchainPin) -> Vec<String> {
-    let mut required: Vec<String> = pin.components.clone();
-    for component in DOCTOR_REQUIRED_COMPONENTS {
-        if !required.iter().any(|existing| existing == component) {
-            required.push((*component).to_string());
-        }
-    }
-    required
-}
-
-/// Parse a `rust-toolchain.toml` document for channel and components.
-fn parse_rust_toolchain_toml(contents: &str) -> Result<RustToolchainPin, String> {
-    let value: toml::Value =
-        toml::from_str(contents).map_err(|error| format!("invalid TOML: {error}"))?;
-    let toolchain = value
-        .get("toolchain")
-        .ok_or_else(|| "missing [toolchain] table".to_string())?;
-    let channel = toolchain
-        .get("channel")
-        .and_then(toml::Value::as_str)
-        .map(str::trim)
-        .filter(|channel| !channel.is_empty())
-        .ok_or_else(|| "missing toolchain.channel".to_string())?
-        .to_string();
-    let components = match toolchain.get("components") {
-        None => Vec::new(),
-        Some(toml::Value::Array(items)) => items
-            .iter()
-            .map(|item| {
-                item.as_str()
-                    .map(|name| name.trim().to_string())
-                    .filter(|name| !name.is_empty())
-                    .ok_or_else(|| {
-                        "toolchain.components entries must be non-empty strings".to_string()
-                    })
-            })
-            .collect::<Result<Vec<_>, _>>()?,
-        Some(_) => {
-            return Err("toolchain.components must be an array of strings".to_string());
-        }
-    };
-    Ok(RustToolchainPin {
-        channel,
-        components,
-    })
-}
-
-/// True when `rustup show active-toolchain` output matches the pinned channel.
-///
-/// The toolchain name is the first whitespace-delimited token of the first
-/// line in every rustup output format seen so far:
-///
-/// - pre-1.28 and 1.29+: `nightly-2026-04-03-<triple> (default)` or
-///   `nightly-2026-04-03-<triple> (overridden by '<path>')` on one line
-///   (verified against rustup 1.29.0);
-/// - 1.28.x: the bare name on the first line with the reason on a second
-///   `active because: ...` line.
-fn active_toolchain_matches_channel(active_toolchain: &str, channel: &str) -> bool {
-    let active = active_toolchain
-        .lines()
-        .next()
-        .unwrap_or("")
-        .split_whitespace()
-        .next()
-        .unwrap_or("");
-    if active.is_empty() || channel.is_empty() {
-        return false;
-    }
-    active == channel || active.starts_with(&format!("{channel}-"))
-}
-
-/// Return required components that are absent from `rustup component list --installed`.
-fn missing_rustup_components<S: AsRef<str>>(installed_list: &str, required: &[S]) -> Vec<String> {
-    required
-        .iter()
-        .map(AsRef::as_ref)
-        .filter(|component| !rustup_component_installed(installed_list, component))
-        .map(str::to_string)
-        .collect()
-}
-
-fn rustup_component_installed(installed_list: &str, component: &str) -> bool {
-    installed_list.lines().any(|line| {
-        let name = line.split_whitespace().next().unwrap_or("");
-        name == component || name.starts_with(&format!("{component}-"))
-    })
-}
-
-fn doctor_report_toolchain_pin(ctx: &Context, ok: &mut bool) {
-    let toolchain_file = ctx.workspace_root.join("rust-toolchain.toml");
-    print!("rust-toolchain.toml... ");
-    if !toolchain_file.exists() {
-        println!("✗ not found at {}", toolchain_file.display());
-        *ok = false;
-        return;
-    }
-
-    let contents = match std::fs::read_to_string(&toolchain_file) {
-        Ok(contents) => contents,
-        Err(error) => {
-            println!("✗ present but unreadable ({error})");
-            *ok = false;
-            return;
-        }
-    };
-
-    let pin = match parse_rust_toolchain_toml(&contents) {
-        Ok(pin) => pin,
-        Err(error) => {
-            println!("✗ present but invalid ({error})");
-            *ok = false;
-            return;
-        }
-    };
-    println!("✓ channel {}", pin.channel);
-
-    print!("Pinned toolchain active... ");
-    match Command::new("rustup")
-        .args(["show", "active-toolchain"])
-        .output()
-    {
-        Ok(output) if output.status.success() => {
-            let active = String::from_utf8_lossy(&output.stdout);
-            let active = active.trim();
-            if active_toolchain_matches_channel(active, &pin.channel) {
-                println!("✓ {active}");
-            } else {
-                println!(
-                    "✗ active `{active}`, expected `{pin_channel}`",
-                    pin_channel = pin.channel
-                );
-                eprintln!(
-                    "  Install/select the pin with `rustup toolchain install {}` and reopen the shell",
-                    pin.channel
-                );
-                eprintln!("  in this workspace so rust-toolchain.toml can select it.");
-                *ok = false;
-            }
-        }
-        Ok(output) => {
-            let stderr = String::from_utf8_lossy(&output.stderr);
-            println!("✗ rustup show active-toolchain failed");
-            if !stderr.trim().is_empty() {
-                eprintln!("  {}", stderr.trim());
-            }
-            *ok = false;
-        }
-        Err(_) => {
-            println!("✗ rustup not found");
-            eprintln!("  Install rustup from https://rustup.rs/ so doctor can verify the pin.");
-            *ok = false;
-        }
-    }
-
-    let required = doctor_verified_components(&pin);
-
-    print!("Required rustup components... ");
-    match Command::new("rustup")
-        .args([
-            "component",
-            "list",
-            "--installed",
-            "--toolchain",
-            &pin.channel,
-        ])
-        .output()
-    {
-        Ok(output) if output.status.success() => {
-            let installed = String::from_utf8_lossy(&output.stdout);
-            let missing = missing_rustup_components(&installed, &required);
-            if missing.is_empty() {
-                println!("✓ {}", required.join(", "));
-            } else {
-                println!("✗ missing {}", missing.join(", "));
-                eprintln!(
-                    "  Install with `rustup component add --toolchain {} {}`",
-                    pin.channel,
-                    missing.join(" ")
-                );
-                *ok = false;
-            }
-        }
-        Ok(output) => {
-            let stderr = String::from_utf8_lossy(&output.stderr);
-            println!("✗ could not list components for {}", pin.channel);
-            if !stderr.trim().is_empty() {
-                eprintln!("  {}", stderr.trim());
-            }
-            eprintln!(
-                "  Try `rustup toolchain install {channel} -c {components}`",
-                channel = pin.channel,
-                components = required.join(" -c ")
-            );
-            *ok = false;
-        }
-        Err(_) => {
-            println!("✗ rustup not found");
-            *ok = false;
-        }
-    }
-}
-
-/// Validate the development environment.
-///
-/// Checks for: Rust nightly toolchain, `rust-toolchain.toml`, the codegen
-/// backend `.so` (informational), CUDA headers (`cuda.h`), CUDA toolkit
-/// (`nvcc`, libNVVM, nvJitLink, libdevice), LLVM (`llc`), clang/libclang,
-/// the NVIDIA driver / GPU (informational), and optionally `cuda-gdb` /
-/// `compute-sanitizer`.
-/// Exits non-zero if any required check fails.
-///
-/// Doctor itself needs neither the CUDA toolkit nor a driver: every check
-/// is a subprocess, a filesystem probe, or a runtime `dlopen`, and the
-/// caller resolves the context via [`resolve_passive_context`] so nothing is
-/// built first. This is what lets it diagnose a bare machine (issue #87).
-pub fn doctor(ctx: &Context) {
-    println!("cargo-oxide environment check");
-    println!("==============================");
-    println!();
-
-    let mut ok = true;
-
-    // 1. Rust toolchain
-    print!("Rust nightly toolchain... ");
-    match Command::new("rustc").args(["--version"]).output() {
-        Ok(output) if output.status.success() => {
-            let version = String::from_utf8_lossy(&output.stdout);
-            let version = version.trim();
-            if version.contains("nightly") {
-                println!("✓ {}", version);
-            } else {
-                println!("✗ expected nightly, got: {}", version);
-                ok = false;
-            }
-        }
-        _ => {
-            println!("✗ rustc not found");
-            ok = false;
-        }
-    }
-
-    // 2. rust-toolchain.toml pin + active channel + required components
-    doctor_report_toolchain_pin(ctx, &mut ok);
-
-    // 3. Backend .so. Informational, not fatal: `run`/`build`/`pipeline`
-    // build the backend on demand, so "not built yet" is a healthy state
-    // for a fresh clone.
-    print!("Codegen backend... ");
-    if ctx.backend_so.exists() {
-        println!("✓ {}", ctx.backend_so.display());
-    } else {
-        println!("- not built yet (run `cargo oxide setup`)");
-    }
-
-    // 3a. Project config (`.cargo/cuda-oxide.toml`)
-    doctor_report_oxide_config(ctx, &mut ok);
-
-    // 3b. Shared cache. The check above reports the backend this context
-    // resolves to, which inside the repository is the local build. A project
-    // outside the repository resolves to the cache instead, so the two can
-    // disagree while every other check passes.
-    print!("Shared cache (external projects)... ");
-    match backend::cached_backend_path() {
-        Some(cached) => match backend::compare_cache_to_local(&cached, &ctx.backend_so) {
-            backend::CacheReport::Absent => {
-                println!("- empty; external projects build on first use");
-            }
-            backend::CacheReport::UpToDate => {
-                println!("✓ {}", cached.display());
-            }
-            backend::CacheReport::OlderThanLocal => {
-                println!("⚠ {}", cached.display());
-                println!("  Older than the backend built here, so projects outside this");
-                println!("  repository would load a different one. Run `cargo oxide setup`");
-                println!("  to publish, or set CUDA_OXIDE_BACKEND to pin an explicit path.");
-            }
-        },
-        None => println!("- cache directory unknown (set CARGO_HOME or HOME)"),
-    }
-
-    // 4. CUDA headers (cuda.h). The host `cuda-bindings` crate cannot build
-    // without them; cargo-oxide itself deliberately can, which is what makes
-    // this check reachable on a toolkit-less machine instead of dying inside
-    // cuda-bindings' build script (issue #87).
-    print!("CUDA headers (cuda.h)... ");
-    let toolkit = cuda_toolkit_root(|var| std::env::var(var).ok());
-    let target_dir_override = std::env::var("CUDA_TOOLKIT_TARGET_DIR").ok();
-    let header_candidates = cuda_header_candidates(
-        &toolkit,
-        target_dir_override.as_deref(),
-        std::env::consts::ARCH,
-        std::env::consts::OS,
-    );
-    match header_candidates.iter().find(|path| path.is_file()) {
-        Some(found) => println!("✓ {}", found.display()),
-        None => {
-            println!("✗ not found in the CUDA toolkit at `{}`", toolkit);
-            eprintln!("  Probed:");
-            for candidate in &header_candidates {
-                eprintln!("    {}", candidate.display());
-            }
-            eprintln!("  Host crates (cuda-bindings) cannot build without cuda.h. Set");
-            eprintln!("  CUDA_TOOLKIT_PATH or CUDA_HOME to a CUDA Toolkit install root;");
-            eprintln!("  when neither is set, /usr/local/cuda is used.");
-            ok = false;
-        }
-    }
-
-    // 5. CUDA toolkit -- same discovery order as `cuda.h`, libNVVM, libdevice
-    // and `compute-sanitizer` below. `nvcc` lives in the toolkit's `bin/`, so
-    // probing PATH alone reported the toolkit missing on exactly the install
-    // this project documents: CUDA_HOME set, toolkit not on PATH.
-    print!("CUDA toolkit (nvcc)... ");
-    match doctor_toolkit_tool(ctx, "nvcc") {
-        Some(path) => match Command::new(&path).arg("--version").output() {
-            Ok(output) if output.status.success() => {
-                let version = String::from_utf8_lossy(&output.stdout);
-                if let Some(line) = version.lines().find(|l| l.contains("release")) {
-                    println!("✓ {} ({})", line.trim(), path.display());
-                } else {
-                    println!("✓ {}", path.display());
-                }
-            }
-            _ => println!("✓ {}", path.display()),
-        },
-        None => {
-            let toolkit = cuda_toolkit_root(|key| {
-                std::env::var(key)
-                    .ok()
-                    .filter(|value| !value.trim().is_empty())
-                    .or_else(|| project_config_env(ctx, key).map(str::to_owned))
-            });
-            println!("✗ nvcc not found");
-            eprintln!("  Probed PATH, {toolkit}/bin/nvcc, and the standard install roots.");
-            eprintln!("  Set CUDA_TOOLKIT_PATH or CUDA_HOME to a CUDA Toolkit install root;");
-            eprintln!("  when neither is set, /usr/local/cuda is used.");
-            ok = false;
-        }
-    }
-
-    // 5b. libNVVM + nvJitLink + libdevice (only required when a kernel uses
-    // CUDA libdevice math, e.g. sin/cos/exp/pow). All three ship with the
-    // CUDA Toolkit; checking them here surfaces missing or split packagings
-    // before a runtime failure inside `cuda_host::ltoir::load_kernel_module`.
-    print!("libNVVM (libnvvm.so)... ");
-    match libnvvm_sys::LibNvvm::load() {
-        Ok(nvvm) => match nvvm.version() {
-            Ok((major, minor)) => println!("✓ libNVVM {}.{}", major, minor),
-            Err(_) => println!("✓ (version query failed but library loaded)"),
-        },
-        Err(e) => {
-            println!("✗ {}", e);
-            eprintln!("  Required only when kernels call CUDA libdevice math");
-            eprintln!("  (sin/cos/exp/pow/...). Ships with the CUDA Toolkit at");
-            eprintln!("  <CUDA>/nvvm/lib64/libnvvm.so. No separate download.");
-            ok = false;
-        }
-    }
-
-    print!("nvJitLink (libnvJitLink.so)... ");
-    match nvjitlink_sys::LibNvJitLink::load() {
-        Ok(nvj) => match nvj.version() {
-            Some((major, minor)) => println!("✓ nvJitLink {}.{}", major, minor),
-            None => println!("✓ (version symbol not exported on this CTK)"),
-        },
-        Err(e) => {
-            println!("✗ {}", e);
-            eprintln!("  Required only when kernels call CUDA libdevice math.");
-            eprintln!("  Ships with the CUDA Toolkit at <CUDA>/lib64/libnvJitLink.so.");
-            ok = false;
-        }
-    }
-
-    print!("libdevice (libdevice.10.bc)... ");
-    match libnvvm_sys::find_libdevice() {
-        Ok(path) => println!("✓ {}", path.display()),
-        Err(e) => {
-            println!("✗ {}", e);
-            eprintln!("  Required only when kernels call CUDA libdevice math.");
-            eprintln!("  Ships with the CUDA Toolkit at");
-            eprintln!("  <CUDA>/nvvm/libdevice/libdevice.10.bc. Override the search");
-            eprintln!("  with `CUDA_OXIDE_LIBDEVICE=<path>` if you have it elsewhere.");
-            ok = false;
-        }
-    }
-
-    // 6. llc (LLVM static compiler for PTX)
-    //
-    // cuda-oxide requires LLVM 21+: earlier releases reject modern TMA /
-    // tcgen05 / WGMMA intrinsic signatures. Probe in the same order as the
-    // pipeline:
-    //   1. `CUDA_OXIDE_LLC` (caller-supplied override)
-    //   2. Rust toolchain's `llvm-tools` component (auto-installed via rustup)
-    //   3. `llc-22`, `llc-21`, `llc` on `PATH`
-    // Whatever we pick, reject if the major version is < 21.
-    print!("llc (LLVM)... ");
-
-    // The pipeline's primary entry: the `llc` bundled with the pinned Rust
-    // toolchain's `llvm-tools` component. Built with the NVPTX backend
-    // enabled, so the typical novice path is `rustup component add llvm-tools`
-    // and that's it. Surface the absolute path so doctor's output matches
-    // what the pipeline actually invokes.
-    let rustup_llc_path: Option<String> = Command::new("rustc")
-        .args(["--print", "sysroot", "--print", "host-tuple"])
-        .output()
-        .ok()
-        .filter(|o| o.status.success())
-        .and_then(|output| {
-            let stdout = String::from_utf8(output.stdout).ok()?;
-            let mut lines = stdout.lines();
-            let sysroot = lines.next()?;
-            let host = lines.next()?;
-            let path: std::path::PathBuf = [sysroot, "lib", "rustlib", host, "bin", "llc"]
-                .iter()
-                .collect();
-            path.is_file()
-                .then(|| path.to_str().map(str::to_string))
-                .flatten()
-        });
-
-    let mut candidates: Vec<String> = Vec::new();
-    if let Ok(env_llc) = std::env::var("CUDA_OXIDE_LLC") {
-        candidates.push(env_llc);
-    }
-    if let Some(rustup) = rustup_llc_path.clone() {
-        candidates.push(rustup);
-    }
-    for name in ["llc-22", "llc-21", "llc"] {
-        candidates.push(name.to_string());
-    }
-
-    let llc_pick = candidates.iter().find_map(|candidate| {
-        Command::new(candidate)
-            .arg("--version")
-            .output()
-            .ok()
-            .filter(|o| o.status.success())
-            .map(|o| {
-                (
-                    candidate.clone(),
-                    String::from_utf8_lossy(&o.stdout).into_owned(),
-                )
-            })
-    });
-    match llc_pick {
-        Some((binary, stdout)) => {
-            let banner = stdout
-                .lines()
-                .find(|l| l.contains("LLVM version"))
-                .unwrap_or("(version unknown)")
-                .trim()
-                .to_string();
-            let major = banner
-                .split("LLVM version")
-                .nth(1)
-                .and_then(|rest| rest.trim().split('.').next())
-                .and_then(|s| s.parse::<u32>().ok());
-            match major {
-                Some(v) if v >= 21 => println!("✓ {} ({})", banner, binary),
-                Some(v) => {
-                    println!("✗ {} ({}) — need LLVM 21+", banner, binary);
-                    eprintln!(
-                        "  Your `{}` reports LLVM {}, which rejects the TMA / tcgen05 /",
-                        binary, v
-                    );
-                    eprintln!("  WGMMA intrinsic signatures cuda-oxide emits. Install a newer");
-                    eprintln!("  toolchain (`rustup component add llvm-tools` is usually enough,");
-                    eprintln!("  or `sudo apt install llvm-21`) and either add it to PATH or set");
-                    eprintln!("  `CUDA_OXIDE_LLC=/path/to/llc`.");
-                    ok = false;
-                }
-                None => println!("✓ {} ({}, version could not be parsed)", banner, binary),
-            }
-        }
-        None => {
-            println!("✗ llc not found");
-            eprintln!("  cuda-oxide probes (in order): $CUDA_OXIDE_LLC, the Rust toolchain's");
-            eprintln!("  llvm-tools llc, then llc-22/llc-21/llc on PATH. Easiest fix:");
-            eprintln!("    rustup component add llvm-tools");
-            eprintln!("  Alternative: `sudo apt install llvm-21` (older versions reject");
-            eprintln!("  modern TMA / tcgen05 / WGMMA intrinsics).");
-            ok = false;
-        }
-    }
-
-    // 7. clang / libclang resource dir (host `cuda-bindings` / bindgen)
-    //
-    // The host `cuda-bindings` crate's build.rs runs bindgen, which loads
-    // libclang at runtime to parse `wrapper.h`. That parse pulls in
-    // `<stddef.h>`, which must be served from clang's own resource
-    // directory — the system/GCC copy is not compatible. Fresh installs of
-    // bare `libclang1-*` (without the matching `libclang-common-*-dev`)
-    // leave `/usr/lib/clang/*/include` empty and bindgen explodes with a
-    // mysterious "'stddef.h' file not found". Catch that up front.
-    print!("clang / libclang resource dir... ");
-    let clang_resource_dir = Command::new("clang")
-        .arg("-print-resource-dir")
-        .output()
-        .ok()
-        .filter(|o| o.status.success())
-        .map(|o| String::from_utf8_lossy(&o.stdout).trim().to_string());
-    match clang_resource_dir {
-        Some(ref dir) if std::path::Path::new(&format!("{}/include/stddef.h", dir)).exists() => {
-            println!("✓ {}", dir);
-        }
-        Some(ref dir) => {
-            println!(
-                "✗ resource dir present but `include/stddef.h` missing: {}",
-                dir
-            );
-            eprintln!("  Host `cuda-bindings` uses bindgen, which needs clang's own stddef.h.");
-            eprintln!("  Install the matching dev headers: sudo apt install clang-21");
-            eprintln!("  (or libclang-common-21-dev)");
-            ok = false;
-        }
-        None => {
-            println!("✗ clang not found");
-            eprintln!(
-                "  Host `cuda-bindings` uses bindgen, which needs clang + its resource headers."
-            );
-            eprintln!("  Install with: sudo apt install clang-21");
-            eprintln!("  (or at minimum `libclang-common-21-dev` alongside your libclang)");
-            ok = false;
-        }
-    }
-
-    // 8. NVIDIA driver / GPU. Informational, not fatal: only `cargo oxide
-    // run` (kernel execution) needs a driver. Cross-compiling and GPU-less
-    // CI boxes are supported workflows (`build`/`pipeline` work fine), and
-    // the examples-compile CI job is exactly that.
-    print!("NVIDIA driver / GPU... ");
-    match query_gpu_name_cap_and_driver() {
-        Some((name, (major, minor), driver)) => {
-            println!(
-                "✓ {} (compute capability {}.{}, driver {})",
-                name, major, minor, driver
-            );
-        }
-        None => {
-            // Some containers mount the kernel driver without shipping
-            // nvidia-smi; /proc distinguishes "driver loaded, tool broken"
-            // from "no driver at all".
-            if Path::new("/proc/driver/nvidia/version").exists() {
-                println!("- driver loaded, but nvidia-smi is missing or not reporting a GPU");
-                eprintln!("  A kernel-mode NVIDIA driver is present (/proc/driver/nvidia/");
-                eprintln!("  version), but `nvidia-smi` did not report a usable GPU.");
-                eprintln!("  `cargo oxide run` may still work; arch auto-detection will fall");
-                eprintln!("  back to the backend default (override with --arch=<sm_XX>).");
-            } else {
-                println!("- no NVIDIA driver detected");
-                eprintln!("  Only `cargo oxide run` (kernel execution) needs the driver;");
-                eprintln!("  `cargo oxide build` and `pipeline` work without one.");
-            }
-        }
-    }
-
-    // 9. cuda-gdb (optional) -- same discovery order as `debug`, which is the
-    // command this line is predicting. Probing PATH alone made doctor report a
-    // cuda-gdb missing that `cargo oxide debug` would have found.
-    print!("cuda-gdb (optional)... ");
-    match doctor_toolkit_tool(ctx, "cuda-gdb") {
-        Some(path) => match Command::new(&path).arg("--version").output() {
-            Ok(output) if output.status.success() => {
-                let version = String::from_utf8_lossy(&output.stdout);
-                if let Some(line) = version.lines().next() {
-                    println!("✓ {} ({})", line.trim(), path.display());
-                } else {
-                    println!("✓ {}", path.display());
-                }
-            }
-            _ => println!("✓ {}", path.display()),
-        },
-        None => println!("- not found (only needed for `cargo oxide debug`)"),
-    }
-
-    // 10. compute-sanitizer (optional) — same discovery order as `sanitize`
-    print!("compute-sanitizer (optional)... ");
-    match doctor_toolkit_tool(ctx, "compute-sanitizer") {
-        Some(path) => match Command::new(&path).arg("--version").output() {
-            Ok(output) if output.status.success() => {
-                let version = String::from_utf8_lossy(&output.stdout);
-                // `compute-sanitizer --version` prints a banner and a
-                // copyright line before the actual "Version ..." line.
-                let line = version
-                    .lines()
-                    .map(str::trim)
-                    .find(|line| line.starts_with("Version"))
-                    .or_else(|| version.lines().next().map(str::trim));
-                if let Some(line) = line {
-                    println!("✓ {} ({})", line, path.display());
-                } else {
-                    println!("✓ {}", path.display());
-                }
-            }
-            _ => println!("✓ {}", path.display()),
-        },
-        None => {
-            println!("- not found (only needed for `cargo oxide sanitize`)");
-        }
-    }
-
-    println!();
-    if ok {
-        println!("✅ Environment looks good!");
-    } else {
-        println!("❌ Some checks failed. Fix the issues above and re-run `cargo oxide doctor`.");
-        std::process::exit(1);
-    }
-}
-
-/// CUDA toolkit install root for doctor's `cuda.h` probe: the first set
-/// variable among `CUDA_TOOLKIT_PATH`, `CUDA_HOME`, else `/usr/local/cuda`.
-///
-/// Kept in lockstep BY HAND with `crates/cuda-bindings/build.rs`
-/// (`cuda_toolkit_dir` / `find_cuda_include_dir`): doctor cannot import that
-/// probe because build.rs logic is not a library. If the build.rs discovery
-/// changes, mirror it here.
-fn cuda_toolkit_root(mut get_env: impl FnMut(&str) -> Option<String>) -> String {
-    ["CUDA_TOOLKIT_PATH", "CUDA_HOME"]
-        .iter()
-        .find_map(|var| get_env(var).filter(|value| !value.trim().is_empty()))
-        .unwrap_or_else(|| "/usr/local/cuda".to_string())
-}
-
-/// Candidate `cuda.h` paths under `toolkit`, in probe order: the standard
-/// `include/` layout first, then the redistributable `targets/<dir>/include`
-/// layouts. CUDA names the target dirs after the GPU platform, not the Rust
-/// triple: x86_64 Linux hosts use `x86_64-linux`; aarch64 Linux is ambiguous
-/// between servers (`sbsa-linux`) and Tegra (`aarch64-linux`), so both are
-/// probed in that order. A non-blank `target_dir_override` (the
-/// `CUDA_TOOLKIT_TARGET_DIR` variable, like nvcc's `-target-dir`) replaces
-/// the table with that single directory.
-///
-/// Kept in lockstep BY HAND with the selection table in
-/// `crates/cuda-bindings/toolkit_target.rs` (`resolve_toolkit_target_dirs`):
-/// doctor cannot import it because build-script sources are not a library.
-/// If the selection there changes, mirror it here.
-///
-/// `arch` and `os` are the host CPU architecture and OS; the caller passes
-/// `std::env::consts::ARCH` / `std::env::consts::OS` (doctor runs at
-/// runtime, so there are no cargo target cfgs to consult). Injected as
-/// parameters for unit tests.
-fn cuda_header_candidates(
-    toolkit: &str,
-    target_dir_override: Option<&str>,
-    arch: &str,
-    os: &str,
-) -> Vec<PathBuf> {
-    let base = Path::new(toolkit);
-    let mut candidates = vec![base.join("include/cuda.h")];
-    let target_dirs: Vec<&str> = match target_dir_override.filter(|dir| !dir.trim().is_empty()) {
-        Some(dir) => vec![dir],
-        None => match (arch, os) {
-            ("x86_64", "linux") => vec!["x86_64-linux"],
-            ("aarch64", "linux") => vec!["sbsa-linux", "aarch64-linux"],
-            _ => vec![],
-        },
-    };
-    for dir in target_dirs {
-        candidates.push(base.join("targets").join(dir).join("include/cuda.h"));
-    }
-    candidates
-}
-
-// =============================================================================
-// Clean command
-// =============================================================================
-
-pub fn clean(ctx: &Context) {
-    match clean_context(ctx) {
-        Ok(summary) if summary.removed_directories == 0 && summary.removed_files == 0 => {
-            println!("Nothing to clean.");
-        }
-        Ok(summary) => {
-            println!(
-                "Removed {} directories and {} generated artifacts.",
-                summary.removed_directories, summary.removed_files
-            );
-        }
-        Err(error) => {
-            eprintln!("Error: {error}");
-            std::process::exit(1);
-        }
-    }
-}
-
-#[derive(Debug, Default, Eq, PartialEq)]
-struct CleanSummary {
-    removed_directories: usize,
-    removed_files: usize,
-}
-
-fn clean_context(ctx: &Context) -> Result<CleanSummary, String> {
-    let mut summary = CleanSummary::default();
-
-    if ctx.is_workspace {
-        clean_workspace(ctx, &mut summary)?;
-    } else {
-        clean_standalone_project(&ctx.workspace_root, &mut summary)?;
-    }
-
-    Ok(summary)
-}
-
-fn clean_standalone_project(project_dir: &Path, summary: &mut CleanSummary) -> Result<(), String> {
-    let manifest_path = project_dir.join("Cargo.toml");
-    let package_name = package_name_for_clean(&manifest_path)?;
-
-    if remove_local_target(project_dir)? {
-        summary.removed_directories += 1;
-    }
-
-    summary.removed_files += remove_generated_artifacts(project_dir, &package_name)?;
-
-    Ok(())
-}
-
-fn clean_workspace(ctx: &Context, summary: &mut CleanSummary) -> Result<(), String> {
-    if remove_local_target(&ctx.workspace_root)? {
-        summary.removed_directories += 1;
-    }
-
-    if remove_local_target(&ctx.codegen_crate)? {
-        summary.removed_directories += 1;
-    }
-
-    let entries = std::fs::read_dir(&ctx.examples_dir).map_err(|error| {
-        format!(
-            "could not read examples directory {}: {error}",
-            ctx.examples_dir.display()
-        )
-    })?;
-
-    let mut example_dirs = Vec::new();
-
-    for entry in entries {
-        let entry = entry.map_err(|error| {
-            format!(
-                "could not read an entry in {}: {error}",
-                ctx.examples_dir.display()
-            )
-        })?;
-
-        let file_type = entry.file_type().map_err(|error| {
-            format!(
-                "could not inspect example entry {}: {error}",
-                entry.path().display()
-            )
-        })?;
-
-        if !file_type.is_dir() {
-            continue;
-        }
-
-        let example_dir = entry.path();
-        if example_dir.join("Cargo.toml").is_file() {
-            example_dirs.push(example_dir);
-        }
-    }
-
-    example_dirs.sort();
-
-    for example_dir in example_dirs {
-        clean_example(&example_dir, summary)?;
-    }
-
-    Ok(())
-}
-
-fn clean_example(example_dir: &Path, summary: &mut CleanSummary) -> Result<(), String> {
-    let manifest_path = example_dir.join("Cargo.toml");
-    let package_name = package_name_for_clean(&manifest_path)?;
-
-    if remove_local_target(example_dir)? {
-        summary.removed_directories += 1;
-    }
-
-    summary.removed_files += remove_generated_artifacts(example_dir, &package_name)?;
-
-    Ok(())
-}
-
-fn package_name_for_clean(manifest_path: &Path) -> Result<String, String> {
-    let source = std::fs::read_to_string(manifest_path).map_err(|error| {
-        format!(
-            "could not read manifest {}: {error}",
-            manifest_path.display()
-        )
-    })?;
-
-    let document: toml::Value = toml::from_str(&source).map_err(|error| {
-        format!(
-            "could not parse manifest {}: {error}",
-            manifest_path.display()
-        )
-    })?;
-
-    document
-        .get("package")
-        .and_then(|value| value.get("name"))
-        .and_then(|value| value.as_str())
-        .map(str::to_owned)
-        .ok_or_else(|| {
-            format!(
-                "manifest {} is missing package.name",
-                manifest_path.display()
-            )
-        })
-}
-
-fn remove_local_target(project_dir: &Path) -> Result<bool, String> {
-    let target_dir = project_dir.join("target");
-
-    let metadata = match std::fs::symlink_metadata(&target_dir) {
-        Ok(metadata) => metadata,
-        Err(error) if error.kind() == std::io::ErrorKind::NotFound => {
-            return Ok(false);
-        }
-        Err(error) => {
-            return Err(format!(
-                "could not inspect {}: {error}",
-                target_dir.display()
-            ));
-        }
-    };
-
-    if metadata.file_type().is_symlink() {
-        return Err(format!(
-            "refusing to remove symlinked target directory {}",
-            target_dir.display()
-        ));
-    }
-
-    if !metadata.is_dir() {
-        return Err(format!(
-            "expected {} to be a directory",
-            target_dir.display()
-        ));
-    }
-
-    std::fs::remove_dir_all(&target_dir).map_err(|error| {
-        format!(
-            "could not remove target directory {}: {error}",
-            target_dir.display()
-        )
-    })?;
-
-    println!("Removed {}", target_dir.display());
-
-    Ok(true)
-}
-
-fn remove_generated_artifacts(project_dir: &Path, package_name: &str) -> Result<usize, String> {
-    let mut removed = 0;
-
-    for path in generated_artifact_paths(project_dir, package_name) {
-        let metadata = match std::fs::symlink_metadata(&path) {
-            Ok(metadata) => metadata,
-            Err(error) if error.kind() == std::io::ErrorKind::NotFound => {
-                continue;
-            }
-            Err(error) => {
-                return Err(format!("could not inspect {}: {error}", path.display()));
-            }
-        };
-
-        if metadata.file_type().is_symlink() {
-            return Err(format!(
-                "refusing to remove symlinked generated artifact {}",
-                path.display()
-            ));
-        }
-
-        if !metadata.is_file() {
-            return Err(format!(
-                "expected generated artifact {} to be a file",
-                path.display()
-            ));
-        }
-
-        std::fs::remove_file(&path)
-            .map_err(|error| format!("could not remove {}: {error}", path.display()))?;
-
-        println!("Removed {}", path.display());
-        removed += 1;
-    }
-
-    Ok(removed)
-}
-
-// =============================================================================
-// Setup command
-// =============================================================================
-
-/// Explicitly build (or rebuild) the codegen backend.
-///
-/// Normally the backend is built automatically on every `run`/`build`/`pipeline`
-/// invocation. `setup` exists for first-time setup, CI, or after pulling new
-/// changes when you want to rebuild without running an example.
-pub fn setup(ctx: &Context) {
-    println!("Building cuda-oxide codegen backend...");
-    println!();
-
-    let built_so = backend::build_backend_from_source(&ctx.codegen_crate);
-
-    println!();
-    println!("✓ Backend is ready. You can now use:");
-    println!("  cargo oxide run <example>");
-    println!("  cargo oxide build <example>");
-
-    // A project outside this repository resolves the backend through the
-    // shared cache, since `find_workspace_root` finds no
-    // `crates/rustc-codegen-cuda` above it. Publishing the build there keeps
-    // those projects on the backend that was just built instead of on whatever
-    // the cache last held.
-    match backend::publish_to_cache(&built_so) {
-        Some(path) => {
-            println!();
-            println!("✓ Published to {}", path.display());
-            println!("  Projects outside this repo will now use this build.");
-        }
-        None => {
-            eprintln!();
-            eprintln!("Warning: could not publish the backend to the shared cache.");
-            eprintln!("Projects outside this repo may keep using an older build.");
-            eprintln!("Set CUDA_OXIDE_BACKEND to this build to override.");
-        }
-    }
-}
-
-/// How `cargo oxide update` should behave for the current project mode.
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum UpdatePlan {
-    /// Inside the monorepo: tell the user to run `setup` (non-destructive).
-    AdviseSetup,
-    /// Inside the monorepo with `--force`: rebuild via `setup`.
-    RunSetup,
-    /// Outside the monorepo: clear and rebuild the shared cache.
-    RefreshCache,
-}
-
-pub fn plan_update(is_workspace: bool, force: bool) -> UpdatePlan {
-    match (is_workspace, force) {
-        (true, false) => UpdatePlan::AdviseSetup,
-        (true, true) => UpdatePlan::RunSetup,
-        (false, _) => UpdatePlan::RefreshCache,
-    }
-}
-
-/// Refresh the codegen backend used by this project.
-///
-/// Inside the cuda-oxide workspace the authoritative backend is the local
-/// source tree, so the default path points at `cargo oxide setup`. Outside
-/// the workspace, the shared `~/.cargo/cuda-oxide/` cache is cleared and
-/// rebuilt via the auto-fetch path.
-/// The backend pin that outranks the shared cache `update` refreshes, if any.
-///
-/// Both the `CUDA_OXIDE_BACKEND` env var and a `.cargo/cuda-oxide.toml`
-/// `backend` entry sit above the cache in backend discovery, so a refreshed
-/// cache would never be consulted while either is set. `update` refuses
-/// rather than mislead.
-fn update_pin_refusal(ctx: &Context) -> Option<String> {
-    update_pin_refusal_with_env(ctx, std::env::var_os("CUDA_OXIDE_BACKEND"))
-}
-
-/// `update_pin_refusal` with the ambient `CUDA_OXIDE_BACKEND` injected.
-///
-/// The env var is checked before the project pin, so resolution has to be
-/// injectable for unit tests: a developer with `CUDA_OXIDE_BACKEND` exported
-/// would otherwise get the env refusal for every input, including the
-/// unpinned case that must return `None`. Same rationale as
-/// `nvvm_ir_requested_with_env`.
-fn update_pin_refusal_with_env(
-    ctx: &Context,
-    backend_env: Option<std::ffi::OsString>,
-) -> Option<String> {
-    if backend_env.is_some() {
-        return Some(
-            "CUDA_OXIDE_BACKEND is set, so `cargo oxide update` will not\n\
-             modify the shared cache. Unset CUDA_OXIDE_BACKEND and re-run, or\n\
-             rebuild the pinned backend path yourself."
-                .to_string(),
-        );
-    }
-    ctx.config.backend.as_deref().map(|pinned| {
-        format!(
-            "`.cargo/cuda-oxide.toml` pins the backend to {}, so\n\
-             `cargo oxide update` will not modify the shared cache. Remove the\n\
-             `backend` entry and re-run, or rebuild the pinned path yourself.",
-            pinned.display()
-        )
-    })
-}
-
-pub fn update(ctx: &Context, force: bool) {
-    if let Some(refusal) = update_pin_refusal(ctx) {
-        eprintln!("Error: {refusal}");
-        std::process::exit(1);
-    }
-
-    match plan_update(ctx.is_workspace, force) {
-        UpdatePlan::AdviseSetup => {
-            println!("Inside the cuda-oxide workspace the codegen backend is built from");
-            println!("local source (`crates/rustc-codegen-cuda`).");
-            println!();
-            println!("Run `cargo oxide setup` to rebuild and publish to the shared cache,");
-            println!("or pass `--force` to run setup from this command.");
-        }
-        UpdatePlan::RunSetup => {
-            println!("`--force` requested inside the workspace; running setup...");
-            println!();
-            setup(ctx);
-        }
-        UpdatePlan::RefreshCache => {
-            println!("Refreshing the shared codegen backend cache for external projects...");
-            println!();
-            let so = backend::refresh_cached_backend();
-            println!();
-            println!("✓ Cached backend ready at {}", so.display());
-        }
-    }
-}
-
-// =============================================================================
-// Helpers
-// =============================================================================
-
-/// Load `.cargo/cuda-oxide.toml`, exiting on an invalid config.
-///
-/// Build commands ([`resolve_context`]) stay strict: they must not run with
-/// a config the user wrote but cargo-oxide cannot honor.
-fn load_oxide_config(workspace_root: &Path) -> OxideConfig {
-    match inspect_oxide_config(workspace_root) {
-        OxideConfigInspection::Missing => OxideConfig::default(),
-        OxideConfigInspection::Valid { config, warnings } => {
-            for warning in warnings {
-                eprintln!("Warning: {warning}");
-            }
-            config
-        }
-        OxideConfigInspection::Invalid { errors, warnings } => {
-            for warning in warnings {
-                eprintln!("Warning: {warning}");
-            }
-            for error in errors {
-                eprintln!("Error: {error}");
-            }
-            std::process::exit(1);
-        }
-    }
-}
-
-/// Load `.cargo/cuda-oxide.toml`, falling back to defaults on an invalid
-/// config instead of exiting.
-///
-/// Passive commands ([`resolve_passive_context`]: `doctor`, `clean`, ...)
-/// must stay usable with a broken config. `doctor` in particular re-inspects
-/// the file and reports the failure as a regular failed check, which it can
-/// only do if context resolution survives long enough for the scan to start.
-fn load_oxide_config_lenient(workspace_root: &Path) -> OxideConfig {
-    match inspect_oxide_config(workspace_root) {
-        OxideConfigInspection::Missing => OxideConfig::default(),
-        OxideConfigInspection::Valid { config, warnings } => {
-            for warning in warnings {
-                eprintln!("Warning: {warning}");
-            }
-            config
-        }
-        OxideConfigInspection::Invalid { errors, warnings } => {
-            for warning in warnings {
-                eprintln!("Warning: {warning}");
-            }
-            for error in errors {
-                eprintln!("Warning: {error}");
-            }
-            eprintln!("Warning: ignoring invalid cuda-oxide config and continuing with defaults");
-            OxideConfig::default()
-        }
-    }
-}
-
-/// Result of reading `.cargo/cuda-oxide.toml` without exiting the process.
-///
-/// `doctor` uses this so a bad config is reported alongside other checks
-/// instead of aborting before the rest of the environment scan runs.
-#[derive(Debug)]
-enum OxideConfigInspection {
-    Missing,
-    Valid {
-        config: OxideConfig,
-        warnings: Vec<String>,
-    },
-    Invalid {
-        errors: Vec<String>,
-        warnings: Vec<String>,
-    },
-}
-
-fn inspect_oxide_config(workspace_root: &Path) -> OxideConfigInspection {
-    let config_path = workspace_root.join(".cargo/cuda-oxide.toml");
-    if !config_path.exists() {
-        return OxideConfigInspection::Missing;
-    }
-
-    let source = match std::fs::read_to_string(&config_path) {
-        Ok(source) => source,
-        Err(error) => {
-            return OxideConfigInspection::Invalid {
-                errors: vec![format!(
-                    "could not read cuda-oxide config {}: {error}",
-                    config_path.display()
-                )],
-                warnings: Vec::new(),
-            };
-        }
-    };
-
-    let document: toml::Value = match toml::from_str(&source) {
-        Ok(document) => document,
-        Err(error) => {
-            return OxideConfigInspection::Invalid {
-                errors: vec![format!(
-                    "could not parse cuda-oxide config {}: {error}",
-                    config_path.display()
-                )],
-                warnings: Vec::new(),
-            };
-        }
-    };
-
-    let Some(table) = document.as_table() else {
-        return OxideConfigInspection::Invalid {
-            errors: vec![format!(
-                "cuda-oxide config {} must be a TOML table",
-                config_path.display()
-            )],
-            warnings: Vec::new(),
-        };
-    };
-
-    let mut errors = Vec::new();
-    let mut warnings = Vec::new();
-
-    let backend = match optional_config_string(table, "backend", &config_path) {
-        Ok(value) => value
-            .map(PathBuf::from)
-            .map(|path| absolutize_config_path(path, &config_path)),
-        Err(error) => {
-            errors.push(error);
-            None
-        }
-    };
-    let default_arch = match optional_config_string(table, "default-arch", &config_path) {
-        Ok(value) => {
-            if let Some(ref arch) = value {
-                // Validate with the same parser the consumers use
-                // (`parse_nvvm_arch` normalizes `sm_XX` / `compute_XX` / bare
-                // `XX` into a `CudaArch`), so load-time validation is exactly
-                // as permissive as what a build would accept. Non-`sm_XX`
-                // spellings work but are advisory-warned: `sm_XX` is the form
-                // `--arch` and the rest of cargo-oxide document.
-                match parse_nvvm_arch(arch) {
-                    Ok(parsed) => {
-                        if !arch.starts_with("sm_") {
-                            warnings.push(format!(
-                                "cuda-oxide config {} spells `default-arch` as `{arch}`; \
-                                 prefer the `{}` form used by `--arch`",
-                                config_path.display(),
-                                parsed.sm()
-                            ));
-                        }
-                    }
-                    Err(error) => {
-                        errors.push(format!(
-                            "cuda-oxide config {} field `default-arch`: {error}",
-                            config_path.display()
-                        ));
-                    }
-                }
-            }
-            value
-        }
-        Err(error) => {
-            errors.push(error);
-            None
-        }
-    };
-    let extra_rustflags = match optional_config_string_array(table, "extra-rustflags", &config_path)
-    {
-        Ok(value) => value,
-        Err(error) => {
-            errors.push(error);
-            Vec::new()
-        }
-    };
-    let env = match table.get("env") {
-        None => Vec::new(),
-        Some(value) => match parse_config_env(value, &config_path) {
-            Ok(env) => {
-                for (key, _) in &env {
-                    if matches!(key.as_str(), "RUSTFLAGS" | "CARGO_ENCODED_RUSTFLAGS") {
-                        warnings.push(format!(
-                            "cuda-oxide config {} `[env]` key `{key}` is ignored; \
-                             use `extra-rustflags` for project rustc defaults",
-                            config_path.display()
-                        ));
-                    }
-                }
-                env
-            }
-            Err(error) => {
-                errors.push(error);
-                Vec::new()
-            }
-        },
-    };
-
-    if !errors.is_empty() {
-        return OxideConfigInspection::Invalid { errors, warnings };
-    }
-
-    OxideConfigInspection::Valid {
-        config: OxideConfig {
-            backend,
-            default_arch,
-            extra_rustflags,
-            env,
-        },
-        warnings,
-    }
-}
-
-/// Outcome of doctor's project-config check, separated from printing so
-/// tests can assert the doctor-level behavior (headline, detail lines,
-/// pass/fail) directly.
-struct OxideConfigCheck {
-    /// Line printed after the check label.
-    headline: String,
-    /// Indented detail lines (warnings, then errors).
-    details: Vec<String>,
-    /// Whether the check failed (flips doctor to a nonzero exit).
-    failed: bool,
-}
-
-fn check_oxide_config(workspace_root: &Path) -> OxideConfigCheck {
-    let config_path = workspace_root.join(".cargo/cuda-oxide.toml");
-    match inspect_oxide_config(workspace_root) {
-        OxideConfigInspection::Missing => OxideConfigCheck {
-            headline: "- not present (using defaults)".to_string(),
-            details: Vec::new(),
-            failed: false,
-        },
-        OxideConfigInspection::Valid { config, warnings } => OxideConfigCheck {
-            headline: match &config.default_arch {
-                Some(arch) => format!("✓ {} (default-arch = {arch})", config_path.display()),
-                None => format!("✓ {}", config_path.display()),
-            },
-            details: warnings
-                .into_iter()
-                .map(|warning| format!("⚠ {warning}"))
-                .collect(),
-            failed: false,
-        },
-        OxideConfigInspection::Invalid { errors, warnings } => OxideConfigCheck {
-            headline: format!("✗ {}", config_path.display()),
-            details: warnings
-                .into_iter()
-                .map(|warning| format!("⚠ {warning}"))
-                .chain(errors.into_iter().map(|error| format!("✗ {error}")))
-                .collect(),
-            failed: true,
-        },
-    }
-}
-
-fn doctor_report_oxide_config(ctx: &Context, ok: &mut bool) {
-    print!("Project config (.cargo/cuda-oxide.toml)... ");
-    let check = check_oxide_config(&ctx.workspace_root);
-    println!("{}", check.headline);
-    for line in check.details {
-        println!("  {line}");
-    }
-    if check.failed {
-        *ok = false;
-    }
-}
-
-fn absolutize_config_path(path: PathBuf, config_path: &Path) -> PathBuf {
-    if path.is_absolute() {
-        return path;
-    }
-    config_path
-        .parent()
-        .unwrap_or_else(|| Path::new("."))
-        .join(path)
-}
-
-fn optional_config_string(
-    table: &toml::Table,
-    key: &str,
-    config_path: &Path,
-) -> Result<Option<String>, String> {
-    match table.get(key) {
-        None => Ok(None),
-        Some(value) => value.as_str().map(|s| Some(s.to_string())).ok_or_else(|| {
-            format!(
-                "cuda-oxide config {} field `{key}` must be a string",
-                config_path.display()
-            )
-        }),
-    }
-}
-
-fn optional_config_string_array(
-    table: &toml::Table,
-    key: &str,
-    config_path: &Path,
-) -> Result<Vec<String>, String> {
-    match table.get(key) {
-        None => Ok(Vec::new()),
-        Some(value) => {
-            let array = value.as_array().ok_or_else(|| {
-                format!(
-                    "cuda-oxide config {} field `{key}` must be an array of strings",
-                    config_path.display()
-                )
-            })?;
-            array
-                .iter()
-                .map(|item| {
-                    item.as_str().map(str::to_string).ok_or_else(|| {
-                        format!(
-                            "cuda-oxide config {} field `{key}` must be an array of strings",
-                            config_path.display()
-                        )
-                    })
-                })
-                .collect()
-        }
-    }
-}
-
-fn parse_config_env(
-    value: &toml::Value,
-    config_path: &Path,
-) -> Result<Vec<(String, String)>, String> {
-    let table = value.as_table().ok_or_else(|| {
-        format!(
-            "cuda-oxide config {} field `env` must be a table of strings",
-            config_path.display()
-        )
-    })?;
-    let mut env: Vec<_> = table
-        .iter()
-        .map(|(key, value)| {
-            let value = value.as_str().ok_or_else(|| {
-                format!(
-                    "cuda-oxide config {} env value `{key}` must be a string",
-                    config_path.display()
-                )
-            })?;
-            Ok((key.clone(), value.to_string()))
-        })
-        .collect::<Result<Vec<_>, String>>()?;
-    env.sort_by(|left, right| left.0.cmp(&right.0));
-    Ok(env)
-}
-
-fn load_interop_config(example_dir: &Path) -> Option<InteropConfig> {
-    let manifest_path = example_dir.join("Cargo.toml");
-    let source = std::fs::read_to_string(&manifest_path).unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not read manifest {}: {}",
-            manifest_path.display(),
-            e
-        );
-        std::process::exit(1);
-    });
-    let document: toml::Value = toml::from_str(&source).unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not parse manifest {}: {}",
-            manifest_path.display(),
-            e
-        );
-        std::process::exit(1);
-    });
-
-    let oxide = document
-        .get("package")
-        .and_then(|value| value.get("metadata"))
-        .and_then(|value| value.get("cuda-oxide"))?;
-
-    let kind = oxide.get("interop").and_then(|value| {
-        value.as_str().map(str::to_string).or_else(|| {
-            value
-                .get("kind")
-                .and_then(|kind| kind.as_str())
-                .map(str::to_string)
-        })
-    });
-
-    let device_crates = oxide
-        .get("device-crates")
-        .and_then(|value| value.as_array())
-        .map(|items| {
-            items
-                .iter()
-                .map(|item| parse_device_crate_config(item, &manifest_path))
-                .collect()
-        })
-        .unwrap_or_default();
-
-    Some(InteropConfig {
-        kind,
-        device_crates,
-    })
-}
-
-fn parse_device_crate_config(value: &toml::Value, manifest_path: &Path) -> DeviceCrateConfig {
-    let table = value.as_table().unwrap_or_else(|| {
-        eprintln!(
-            "Error: each package.metadata.cuda-oxide.device-crates entry in {} must be a table",
-            manifest_path.display()
-        );
-        std::process::exit(1);
-    });
-
-    let device_manifest = required_metadata_string(table, "manifest-path", manifest_path);
-    let artifact_dir = optional_metadata_string(table, "artifact-dir")
-        .or_else(|| optional_metadata_string(table, "ptx-dir"))
-        .map(PathBuf::from)
-        .unwrap_or_else(|| {
-            Path::new(&device_manifest)
-                .parent()
-                .unwrap_or_else(|| Path::new("."))
-                .to_path_buf()
-        });
-    let artifact_name = optional_metadata_string(table, "artifact-name");
-    let artifact_kind = match optional_metadata_string(table, "artifact-kind").as_deref() {
-        None | Some("ptx") => InteropArtifactKind::Ptx,
-        Some("cubin") => InteropArtifactKind::Cubin,
-        Some(value) => {
-            eprintln!(
-                "Error: package.metadata.cuda-oxide.device-crates `artifact-kind` in {} must be `ptx` or `cubin`, got {value:?}",
-                manifest_path.display()
-            );
-            std::process::exit(2);
-        }
-    };
-    let source_identity = match table.get("source-identity") {
-        None => false,
-        Some(value) => value.as_bool().unwrap_or_else(|| {
-            eprintln!(
-                "Error: package.metadata.cuda-oxide.device-crates `source-identity` in {} must be a boolean",
-                manifest_path.display()
-            );
-            std::process::exit(2);
-        }),
-    };
-    let bin = optional_metadata_string(table, "bin");
-
-    DeviceCrateConfig {
-        manifest_path: PathBuf::from(device_manifest),
-        artifact_dir,
-        artifact_name,
-        artifact_kind,
-        source_identity,
-        bin,
-    }
-}
-
-fn required_metadata_string(table: &toml::Table, key: &str, manifest_path: &Path) -> String {
-    optional_metadata_string(table, key).unwrap_or_else(|| {
-        eprintln!(
-            "Error: package.metadata.cuda-oxide.device-crates entry in {} is missing string field `{}`",
-            manifest_path.display(),
-            key
-        );
-        std::process::exit(1);
-    })
-}
-
-fn optional_metadata_string(table: &toml::Table, key: &str) -> Option<String> {
-    table
-        .get(key)
-        .and_then(|value| value.as_str())
-        .map(str::to_string)
-}
-
-fn package_name_from_manifest(manifest_path: &Path) -> String {
-    let source = std::fs::read_to_string(manifest_path).unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not read device manifest {}: {}",
-            manifest_path.display(),
-            e
-        );
-        std::process::exit(1);
-    });
-    let document: toml::Value = toml::from_str(&source).unwrap_or_else(|e| {
-        eprintln!(
-            "Error: could not parse device manifest {}: {}",
-            manifest_path.display(),
-            e
-        );
-        std::process::exit(1);
-    });
-
-    document
-        .get("package")
-        .and_then(|value| value.get("name"))
-        .and_then(|value| value.as_str())
-        .map(str::to_string)
-        .unwrap_or_else(|| {
-            eprintln!(
-                "Error: device manifest {} is missing package.name",
-                manifest_path.display()
-            );
-            std::process::exit(1);
-        })
-}
-
-fn normalize_crate_name(package_name: &str) -> String {
-    package_name.replace('-', "_")
-}
-
-/// The target directory cargo reports for a device crate, which locates both
-/// its uplifted build products and the build outputs the identity sidecar
-/// must exclude.
-fn cargo_target_directory(metadata: &serde_json::Value) -> Result<PathBuf, String> {
-    metadata
-        .get("target_directory")
-        .and_then(|value| value.as_str())
-        .map(PathBuf::from)
-        .ok_or_else(|| "cargo metadata omitted target_directory".to_string())
-}
-
-/// Where cargo uplifts the dep-info file for a release binary target.
-///
-/// Cargo names the uplifted copy after the bin target verbatim, hyphens
-/// preserved: building the `simt-device` target writes
-/// `target/release/simt-device` and `target/release/simt-device.d` (this
-/// repo's own build writes `target/debug/cargo-oxide.d`). Only the internal
-/// per-unit copies under `target/release/deps/` use the underscore-normalized
-/// crate name, so the stem here must NOT be `normalize_crate_name`d.
-fn release_depfile_path(cargo_target_dir: &Path, cargo_target_name: &str) -> PathBuf {
-    cargo_target_dir
-        .join("release")
-        .join(format!("{cargo_target_name}.d"))
-}
-
-fn interop_cargo_metadata(
-    ctx: &Context,
-    device_dir: &Path,
-    manifest_path: &Path,
-) -> Result<serde_json::Value, String> {
-    let mut command = Command::new("cargo");
-    command
-        .args([
-            "metadata",
-            "--format-version=1",
-            "--no-deps",
-            "--manifest-path",
-        ])
-        .arg(manifest_path)
-        .current_dir(device_dir);
-    apply_config_env(&mut command, ctx);
-    let output = command
-        .output()
-        .map_err(|error| format!("could not start cargo metadata: {error}"))?;
-    if !output.status.success() {
-        let stderr = String::from_utf8_lossy(&output.stderr);
-        return Err(format!(
-            "cargo metadata failed with status {}{}{}",
-            output.status,
-            if stderr.is_empty() { "" } else { ": " },
-            stderr.trim()
-        ));
-    }
-    serde_json::from_slice(&output.stdout)
-        .map_err(|error| format!("could not parse cargo metadata JSON: {error}"))
-}
-
-fn interop_binary_target_from_metadata(
-    metadata: &serde_json::Value,
-    manifest_path: &Path,
-    bin: &str,
-) -> Result<InteropBinaryTarget, String> {
-    let packages = metadata
-        .get("packages")
-        .and_then(serde_json::Value::as_array)
-        .ok_or_else(|| "cargo metadata omitted packages".to_string())?;
-    let package = packages
-        .iter()
-        .find(|package| {
-            package
-                .get("manifest_path")
-                .and_then(serde_json::Value::as_str)
-                .is_some_and(|path| Path::new(path) == manifest_path)
-        })
-        .ok_or_else(|| {
-            format!(
-                "cargo metadata omitted package for manifest {}",
-                manifest_path.display()
-            )
-        })?;
-    let targets = package
-        .get("targets")
-        .and_then(serde_json::Value::as_array)
-        .ok_or_else(|| "cargo metadata omitted package targets".to_string())?;
-    let is_binary = |target: &&serde_json::Value| {
-        target
-            .get("kind")
-            .and_then(serde_json::Value::as_array)
-            .is_some_and(|kinds| kinds.iter().any(|kind| kind.as_str() == Some("bin")))
-    };
-    let target = targets
-        .iter()
-        .filter(is_binary)
-        .find(|target| target.get("name").and_then(serde_json::Value::as_str) == Some(bin))
-        .ok_or_else(|| {
-            let mut available = targets
-                .iter()
-                .filter(is_binary)
-                .filter_map(|target| target.get("name").and_then(serde_json::Value::as_str))
-                .collect::<Vec<_>>();
-            available.sort_unstable();
-            format!(
-                "manifest {} has no binary target {bin:?}; available binary targets: {}",
-                manifest_path.display(),
-                if available.is_empty() {
-                    "<none>".to_string()
-                } else {
-                    available.join(", ")
-                }
-            )
-        })?;
-    let source_path = target
-        .get("src_path")
-        .and_then(serde_json::Value::as_str)
-        .map(PathBuf::from)
-        .ok_or_else(|| format!("cargo metadata omitted source path for binary target {bin:?}"))?;
-    Ok(InteropBinaryTarget { source_path })
-}
-
-/// Resolve an example name to its directory path, or exit with a list of
-/// available examples if not found.
-fn resolve_example_dir(ctx: &Context, example: &str) -> PathBuf {
-    let example_dir = ctx.examples_dir.join(example);
-    if !example_dir.exists() {
-        eprintln!("Error: Example not found: {}", example_dir.display());
-        eprintln!();
-        eprintln!("Available examples:");
-        if let Ok(entries) = std::fs::read_dir(&ctx.examples_dir) {
-            let mut names: Vec<_> = entries
-                .flatten()
-                .filter(|e| e.path().is_dir())
-                .map(|e| e.file_name().to_string_lossy().to_string())
-                .collect();
-            names.sort();
-            for name in names {
-                eprintln!("  - {}", name);
-            }
-        }
-        std::process::exit(1);
-    }
-    example_dir
-}
-
-const ENCODED_RUSTFLAGS_SEPARATOR: char = '\u{1f}';
-
-/// Profile-related rustc flags owned by cuda-oxide.
-///
-/// Backend selection and MIR/symbol invariants are always applied separately.
-/// `CargoSelected` deliberately adds no optimization, assertion, or debug-info
-/// flags so Cargo's chosen profile remains authoritative.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
-enum CodegenProfilePolicy {
-    CargoSelected,
-    ReleaseLike,
-    ReleaseLikeWithDebugInfo,
-}
-
-/// Construct boundary-preserving rustc flags for Cargo.
-///
-/// `RUSTFLAGS` is whitespace-split by Cargo, which corrupts a single flag
-/// containing spaces. `CARGO_ENCODED_RUSTFLAGS` uses unit separators and keeps
-/// every configured array element and `--device-cfg` value intact.
-fn build_encoded_rustflags(
-    ctx: &Context,
-    profile: CodegenProfilePolicy,
-    device_cfgs: &[String],
-) -> String {
-    let existing_encoded = std::env::var("CARGO_ENCODED_RUSTFLAGS").ok();
-    let existing = std::env::var("RUSTFLAGS").ok();
-    let mut explicit_rustflags = Vec::new();
-    for cfg in device_cfgs {
-        explicit_rustflags.push("--cfg".to_string());
-        explicit_rustflags.push(cfg.clone());
-    }
-    build_encoded_rustflags_with_existing(
-        &ctx.backend_so,
-        profile,
-        &ctx.config.extra_rustflags,
-        &explicit_rustflags,
-        existing_encoded.as_deref(),
-        existing.as_deref(),
-    )
-}
-
-fn build_encoded_rustflags_with_existing(
-    backend_so: &Path,
-    profile: CodegenProfilePolicy,
-    configured_rustflags: &[String],
-    explicit_rustflags: &[String],
-    existing_encoded_rustflags: Option<&str>,
-    existing_rustflags: Option<&str>,
-) -> String {
-    // Project flags are defaults, inherited flags are user overrides, and
-    // explicit wrapper flags are stronger. cuda-oxide's compiler invariants
-    // come last because rustc resolves repeated -C/-Z options last-one-wins.
-    let mut flags = configured_rustflags.to_vec();
-
-    if let Some(existing) = existing_encoded_rustflags {
-        flags.extend(
-            existing
-                .split(ENCODED_RUSTFLAGS_SEPARATOR)
-                .filter(|flag| !flag.is_empty())
-                .map(str::to_string),
-        );
-    } else if let Some(existing) = existing_rustflags {
-        // Match Cargo's legacy RUSTFLAGS behavior when converting it to the
-        // encoded representation.
-        flags.extend(existing.split_whitespace().map(str::to_string));
-    }
-    flags.extend(explicit_rustflags.iter().cloned());
-    strip_wrapper_owned_codegen_cfgs(&mut flags);
-    flags.push(format!("-Zcodegen-backend={}", backend_so.display()));
-    if matches!(
-        profile,
-        CodegenProfilePolicy::ReleaseLike | CodegenProfilePolicy::ReleaseLikeWithDebugInfo
-    ) {
-        flags.extend([
-            "-Copt-level=3".to_string(),
-            "-Cdebug-assertions=off".to_string(),
-        ]);
-    }
-    flags.extend([
-        "-Zmir-enable-passes=-JumpThreading".to_string(),
-        // Device codegen is whole-program: `collector` walks the call graph from
-        // each `#[kernel]` and must emit every reachable dependency function into
-        // one module. rustc encodes cross-crate MIR only for `#[inline]`/generic
-        // items, so a non-`#[inline]`, non-generic dependency function that cannot
-        // be inlined away (canonically: a recursive one) would be *called* but
-        // never *defined* -> LLVM verification fails with "Symbol <crate>__<fn>
-        // not found". Encode all MIR so any reachable dependency function is
-        // device-compilable. This applies build-wide (like the other required
-        // flags), so it also encodes MIR for host-only deps — an intentional,
-        // interim trade (rmeta size) until a surgical device-dep-scoped or
-        // per-crate device-link path lands. It matches the established approach
-        // for whole-program-MIR tools (e.g. Miri).
-        "-Zalways-encode-mir".to_string(),
-        "-Csymbol-mangling-version=v0".to_string(),
-    ]);
-    if profile == CodegenProfilePolicy::ReleaseLikeWithDebugInfo {
-        flags.push("-Cdebuginfo=2".to_string());
-    }
-    flags.join(&ENCODED_RUSTFLAGS_SEPARATOR.to_string())
-}
-
-fn strip_wrapper_owned_codegen_cfgs(flags: &mut Vec<String>) {
-    fn is_wrapper_owned_cfg(value: &str) -> bool {
-        [
-            LEGACY_CODEGEN_FINGERPRINT_CFG,
-            LEGACY_MATERIALIZER_PROVENANCE_CFG,
-        ]
-        .iter()
-        .any(|name| {
-            value
-                .strip_prefix(name)
-                .is_some_and(|suffix| suffix.is_empty() || suffix.starts_with('='))
-        })
-    }
-
-    let mut retained = Vec::with_capacity(flags.len());
-    let mut index = 0;
-    while index < flags.len() {
-        let flag = &flags[index];
-        if flag == "--cfg"
-            && flags
-                .get(index + 1)
-                .is_some_and(|value| is_wrapper_owned_cfg(value))
-        {
-            index += 2;
-            continue;
-        }
-        if flag
-            .strip_prefix("--cfg=")
-            .is_some_and(is_wrapper_owned_cfg)
-        {
-            index += 1;
-            continue;
-        }
-        retained.push(flag.clone());
-        index += 1;
-    }
-    *flags = retained;
-}
-
-fn command_requests_full_device_debug_with_env(
-    cmd: &Command,
-    inherited_debug: Option<&str>,
-) -> bool {
-    let effective_debug = match cmd
-        .get_envs()
-        .find(|(name, _)| *name == std::ffi::OsStr::new("CUDA_OXIDE_DEBUG"))
-    {
-        Some((_, Some(value))) => Some(value.to_string_lossy().into_owned()),
-        Some((_, None)) => None,
-        None => inherited_debug.map(str::to_owned),
-    };
-
-    // Shared alias table: the codegen backend parses `CUDA_OXIDE_DEBUG`
-    // with the same function, so every spelling the backend treats as
-    // full debug (including `2`) also disables MIR optimization here.
-    effective_debug.is_some_and(|value| {
-        cuda_artifact_finalizer::DebugPolicy::parse_env_override(&value)
-            == Some(cuda_artifact_finalizer::DebugPolicy::Full)
-    })
-}
-
-fn append_full_debug_mir_rustflag(
-    encoded: &mut String,
-    cmd: &Command,
-    inherited_debug: Option<&str>,
-) {
-    if !command_requests_full_device_debug_with_env(cmd, inherited_debug) {
-        return;
-    }
-    if !encoded.is_empty() {
-        encoded.push(ENCODED_RUSTFLAGS_SEPARATOR);
-    }
-    encoded.push_str("-Zmir-opt-level=0");
-}
-
-fn apply_codegen_rustflags(
-    cmd: &mut Command,
-    ctx: &Context,
-    profile: CodegenProfilePolicy,
-    device_cfgs: &[String],
-) {
-    let mut encoded = build_encoded_rustflags(ctx, profile, device_cfgs);
-    let inherited_debug = std::env::var("CUDA_OXIDE_DEBUG").ok();
-    append_full_debug_mir_rustflag(&mut encoded, cmd, inherited_debug.as_deref());
-
-    cmd.env("CARGO_ENCODED_RUSTFLAGS", encoded)
-        .env_remove("RUSTFLAGS");
-}
-
-/// Apply the two deliberately different Cargo cache boundaries:
-///
-/// - the exact backend binary is global because it compiles every crate;
-/// - mode/architecture/tool settings are an env dependency recorded only by
-///   CUDA macros in crates that can own or instantiate device code.
-fn apply_codegen_configuration(
-    cmd: &mut Command,
-    ctx: &Context,
-    profile: CodegenProfilePolicy,
-    user_device_cfgs: &[String],
-    codegen_fingerprint: &str,
-) -> Result<(), String> {
-    let backend_digest = backend_artifact_digest(&ctx.backend_so)?;
-    let mut global_cfgs = Vec::with_capacity(user_device_cfgs.len() + 1);
-    global_cfgs.push(format!("{BACKEND_IDENTITY_CFG}=\"{backend_digest}\""));
-    global_cfgs.extend(user_device_cfgs.iter().cloned());
-
-    apply_codegen_rustflags(cmd, ctx, profile, &global_cfgs);
-    cmd.env(CODEGEN_FINGERPRINT_ENV, codegen_fingerprint);
-    Ok(())
-}
-
-fn apply_codegen_configuration_or_exit(
-    cmd: &mut Command,
-    ctx: &Context,
-    profile: CodegenProfilePolicy,
-    user_device_cfgs: &[String],
-    codegen_fingerprint: &str,
-) {
-    apply_codegen_configuration(cmd, ctx, profile, user_device_cfgs, codegen_fingerprint)
-        .unwrap_or_else(|error| {
-            eprintln!("Error: {error}");
-            std::process::exit(1);
-        });
-}
-
-/// Set environment variables for the codegen backend.
-///
-/// `arch` is an explicit pin (`--arch`); it becomes `CUDA_OXIDE_TARGET`, the
-/// hard override the backend honors as-is. The auto-detected GPU arch is *not*
-/// routed here -- see [`apply_device_arch_hint`].
-fn apply_output_mode(
-    cmd: &mut Command,
-    emit_nvvm_ir: bool,
-    arch: Option<&str>,
-    materialization: &MaterializationMode,
-) {
-    if let Some(target_arch) = arch {
-        cmd.env("CUDA_OXIDE_TARGET", target_arch);
-    }
-    if emit_nvvm_ir || materialization.enabled() {
-        cmd.env("CUDA_OXIDE_EMIT_NVVM_IR", "1");
-    }
-    materialization.apply(cmd);
-}
-
-fn configured_arch<'a>(ctx: &'a Context, cli_arch: Option<&'a str>) -> Option<&'a str> {
-    if cli_arch.is_some() || std::env::var("CUDA_OXIDE_TARGET").is_ok() {
-        cli_arch
-    } else {
-        ctx.config
-            .default_arch
-            .as_deref()
-            .or_else(|| project_config_env(ctx, "CUDA_OXIDE_TARGET"))
-    }
-}
-
-fn configured_arch_label(ctx: &Context, cli_arch: Option<&str>) -> Option<String> {
-    cli_arch
-        .map(str::to_string)
-        .or_else(|| std::env::var("CUDA_OXIDE_TARGET").ok())
-        .or_else(|| ctx.config.default_arch.clone())
-        .or_else(|| project_config_env(ctx, "CUDA_OXIDE_TARGET").map(str::to_string))
-}
-
-pub fn has_configured_arch(ctx: &Context, cli_arch: Option<&str>) -> bool {
-    cli_arch.is_some()
-        || std::env::var("CUDA_OXIDE_TARGET").is_ok()
-        || ctx.config.default_arch.is_some()
-        || project_config_env(ctx, "CUDA_OXIDE_TARGET").is_some()
-}
-
-fn apply_config_env(cmd: &mut Command, ctx: &Context) {
-    for (key, value) in &ctx.config.env {
-        if matches!(key.as_str(), "RUSTFLAGS" | "CARGO_ENCODED_RUSTFLAGS") {
-            continue;
-        }
-        // Project values are defaults. An explicitly inherited environment is
-        // stronger, and command-specific CLI/internal settings are applied
-        // after this helper and are stronger still.
-        if std::env::var_os(key).is_none() {
-            cmd.env(key, value);
-        }
-    }
-}
-
-fn apply_common_codegen_env(
-    cmd: &mut Command,
-    ctx: &Context,
-    verbose: bool,
-    no_fmad: bool,
-    unchecked_indexing: bool,
-    device_debug: DeviceDebug,
-) {
-    apply_config_env(cmd, ctx);
-    if verbose {
-        cmd.env("CUDA_OXIDE_VERBOSE", "1");
-    }
-    if no_fmad {
-        cmd.env("CUDA_OXIDE_NO_FMA", "1");
-    }
-    if unchecked_indexing {
-        cmd.env("CUDA_OXIDE_UNCHECKED_INDEXING", "1");
-    }
-    // An explicit flag outranks an ambient `CUDA_OXIDE_DEBUG`, matching how
-    // `--no-fmad` outranks `CUDA_OXIDE_NO_FMA`. `DeviceDebug::Off` exports
-    // nothing rather than `off`, so omitting the flag cannot silently cancel a
-    // debug level the environment or project config already asked for.
-    if let Some(level) = device_debug.env_value() {
-        cmd.env("CUDA_OXIDE_DEBUG", level);
-    }
-    apply_ld_library_path(cmd, ctx);
-}
-
-/// Give Compute Sanitizer source line attribution without disabling normal
-/// device optimization. An explicit process or project setting remains
-/// authoritative, including an intentional `CUDA_OXIDE_DEBUG=off`. So does an
-/// explicit `--lineinfo` / `--device-debug` flag: `apply_common_codegen_env`
-/// has already exported its level onto `cmd`, and the default must not
-/// overwrite it.
-fn apply_default_sanitizer_line_tables(
-    cmd: &mut Command,
-    ctx: &Context,
-    device_debug: DeviceDebug,
-) {
-    apply_default_sanitizer_line_tables_with_env(
-        cmd,
-        ctx,
-        std::env::var_os("CUDA_OXIDE_DEBUG").is_some(),
-        device_debug,
-    );
-}
-
-/// `apply_default_sanitizer_line_tables` with the `CUDA_OXIDE_DEBUG` probe
-/// injected.
-///
-/// `env_debug_set` is presence-only, matching the `var_os` check it replaces.
-/// Injected so a unit test can assert the defaulting without an exported
-/// `CUDA_OXIDE_DEBUG` suppressing it. `device_debug` carries the CLI flag:
-/// any level other than [`DeviceDebug::Off`] is an explicit request that
-/// outranks the line-tables default.
-fn apply_default_sanitizer_line_tables_with_env(
-    cmd: &mut Command,
-    ctx: &Context,
-    env_debug_set: bool,
-    device_debug: DeviceDebug,
-) {
-    if device_debug == DeviceDebug::Off
-        && !env_debug_set
-        && project_config_env(ctx, "CUDA_OXIDE_DEBUG").is_none()
-    {
-        cmd.env("CUDA_OXIDE_DEBUG", "line-tables");
-    }
-}
-
-fn apply_interop_device_codegen_options(
-    cmd: &mut Command,
-    ctx: &Context,
-    verbose: bool,
-    options: InteropDeviceBuildOptions,
-) {
-    apply_interop_device_codegen_options_with_env(
-        cmd,
-        ctx,
-        verbose,
-        options,
-        std::env::var_os("CUDA_OXIDE_DEBUG").is_some(),
-    );
-}
-
-/// `apply_interop_device_codegen_options` with the `CUDA_OXIDE_DEBUG` probe
-/// injected, forwarded to `apply_default_sanitizer_line_tables_with_env`.
-fn apply_interop_device_codegen_options_with_env(
-    cmd: &mut Command,
-    ctx: &Context,
-    verbose: bool,
-    options: InteropDeviceBuildOptions,
-    env_debug_set: bool,
-) {
-    apply_common_codegen_env(
-        cmd,
-        ctx,
-        verbose,
-        options.no_fmad,
-        options.unchecked_indexing,
-        DeviceDebug::Off,
-    );
-    if options.sanitizer_line_tables {
-        apply_default_sanitizer_line_tables_with_env(cmd, ctx, env_debug_set, DeviceDebug::Off);
-    }
-}
-
-/// Forward the auto-detected GPU arch as a *hint* via `CUDA_OXIDE_DEVICE_ARCH`.
-///
-/// Unlike `CUDA_OXIDE_TARGET` (a hard override), this is advisory: the backend
-/// builds for the detected GPU only when that GPU can actually run the kernel.
-/// If the kernel needs a newer arch (e.g. tcgen05 / cta_group TMA multicast
-/// need sm_100a, which a consumer sm_120 GPU lacks), the backend builds for the
-/// required arch instead. Skipped when the user pinned `--arch` (that explicit
-/// choice already went to `CUDA_OXIDE_TARGET`).
-fn apply_device_arch_hint(
-    cmd: &mut Command,
-    explicit_arch: Option<&str>,
-    detected_device_arch: Option<&str>,
-) {
-    if let (None, Some(dev)) = (explicit_arch, detected_device_arch) {
-        cmd.env("CUDA_OXIDE_DEVICE_ARCH", dev);
-    }
-}
-
-/// Pick a runnable target for `cargo oxide run` when the user has not pinned
-/// one explicitly.
-///
-/// # Precedence
-///
-/// `cargo oxide run` resolves the target architecture in this order, highest
-/// priority first:
-///
-/// 1. `--arch <sm_XX>`            (explicit user override)
-/// 2. `CUDA_OXIDE_TARGET=<sm_XX>` (explicit env override, set in the parent
-///    process before invoking `cargo oxide run`)
-/// 3. **This function**: the compute capability of the first GPU reported by
-///    `nvidia-smi`, forwarded as the `CUDA_OXIDE_DEVICE_ARCH` *hint*. Emits
-///    the arch-specific `sm_XYa` form for cc >= 9.0 (so the backend can lower
-///    WGMMA / tcgen05 / TMA-multicast when the GPU supports them) and the
-///    plain `sm_XY` form for cc < 9.0.
-/// 4. Backend feature-based default (`select_target` in
-///    `mir-importer::pipeline`), which picks the minimum `sm_XX` required by
-///    the IR shape (e.g. `Basic -> sm_80`, `Cluster -> sm_90`, `Tma -> sm_100`).
-///
-/// Slot 3 is advisory: the backend builds for the detected GPU only when that
-/// GPU can run the kernel, otherwise it falls back to slot 4 (the arch the
-/// kernel requires). This function returns `Some(sm_XY[a])` to fill slot 3, or
-/// `None` (falling through to slot 4) when the machine has no usable GPU.
-///
-/// # Why only `run`
-///
-/// `run` immediately loads the generated module on the local GPU and launches
-/// the kernel, so a target older than the local GPU's compute capability is
-/// the only safe default. `build` and `pipeline` may legitimately
-/// cross-compile to a different machine, so they keep the backend's
-/// feature-based default untouched.
-///
-/// # Why this is needed even with the backend default
-///
-/// The backend's `select_target` picks the minimum `sm_XX` the IR requires.
-/// `Basic → sm_80` is a fine *compilation* baseline, but PTX for `sm_80` will
-/// not load on a Turing (`sm_75`) GPU because the JIT refuses
-/// forward-incompatible PTX. Detecting the device CC in `run` keeps the
-/// generated module loadable on the actual hardware that will execute it.
-///
-/// # When this returns `None`
-///
-/// - The user passed `--arch` (slot 1 wins).
-/// - `CUDA_OXIDE_TARGET` is set in the environment (slot 2 wins).
-/// - `--emit-nvvm-ir` is in effect (NVVM IR mode requires explicit `--arch`,
-///   enforced by the CLI parser).
-/// - No CUDA driver / GPU is available on the machine (CI runners without
-///   GPUs, headless build boxes), or `nvidia-smi` is missing or broken. The
-///   caller falls through to slot 4 and the backend's feature-based default
-///   applies.
-fn detect_run_target_arch(arch: Option<&str>, emit_nvvm_ir: bool) -> Option<String> {
-    detect_run_target_arch_with_env(
-        arch,
-        emit_nvvm_ir,
-        std::env::var_os("CUDA_OXIDE_TARGET").is_some(),
-    )
-}
-
-/// `detect_run_target_arch` with the `CUDA_OXIDE_TARGET` probe injected.
-///
-/// `env_target_set` is presence-only, matching the `var_os` check it replaces.
-/// Injected so a unit test can exercise the slot-2 skip without exporting the
-/// variable: `set_var` would be a data race against the `vars_os` reads the
-/// fingerprint helpers perform on other test threads.
-fn detect_run_target_arch_with_env(
-    arch: Option<&str>,
-    emit_nvvm_ir: bool,
-    env_target_set: bool,
-) -> Option<String> {
-    if arch.is_some() || emit_nvvm_ir || env_target_set {
-        return None;
-    }
-
-    query_device_compute_cap().map(format_sm_arch)
-}
-
-/// Query the compute capability of the first GPU via `nvidia-smi`.
-///
-/// Runs `nvidia-smi --query-gpu=compute_cap --format=csv,noheader` and parses
-/// the first output line. A subprocess probe (rather than the CUDA driver
-/// API) keeps cargo-oxide free of any link-time or dlopen dependency on
-/// `libcuda`, so the subcommand builds and runs on machines with no CUDA
-/// toolkit and no driver; `scripts/smoketest.sh` derives `sm_XX` from
-/// `nvidia-smi` the same way.
-///
-/// Caveat: `nvidia-smi` enumerates GPUs in PCI bus order, while CUDA's
-/// default device order is fastest-first, so on heterogeneous multi-GPU
-/// machines this may describe a different GPU than CUDA device 0. That is
-/// safe because `CUDA_OXIDE_DEVICE_ARCH` is advisory (the backend only
-/// honors a compatible hint) and `--arch` / `CUDA_OXIDE_TARGET` remain hard
-/// overrides.
-fn query_device_compute_cap() -> Option<(u32, u32)> {
-    let output = Command::new("nvidia-smi")
-        .args(["--query-gpu=compute_cap", "--format=csv,noheader"])
-        .output()
-        .ok()
-        .filter(|o| o.status.success())?;
-    parse_compute_cap(&String::from_utf8_lossy(&output.stdout))
-}
-
-/// Parse the first line of `nvidia-smi --query-gpu=compute_cap` output as a
-/// `(major, minor)` compute-capability pair. Returns `None` for anything
-/// that is not shaped `<digits>.<digits>`.
-fn parse_compute_cap(stdout: &str) -> Option<(u32, u32)> {
-    parse_compute_cap_field(stdout.lines().next()?)
-}
-
-/// Parse a single `compute_cap` CSV field (e.g. `"12.0"`).
-///
-/// Only the `<digits>.<digits>` shape is accepted: `nvidia-smi` prints its
-/// failure banners ("NVIDIA-SMI has failed ...") to *stdout*, sometimes with
-/// exit status 0, so this shape check is the real gate, not the exit status.
-fn parse_compute_cap_field(field: &str) -> Option<(u32, u32)> {
-    let (major, minor) = field.trim().split_once('.')?;
-    let all_digits = |s: &str| !s.is_empty() && s.bytes().all(|b| b.is_ascii_digit());
-    if !all_digits(major) || !all_digits(minor) {
-        return None;
-    }
-    Some((major.parse().ok()?, minor.parse().ok()?))
-}
-
-/// Query the name, compute capability, and driver version of the first GPU
-/// via `nvidia-smi`, for doctor's driver / GPU report. Same trust rules as
-/// [`query_device_compute_cap`]. The driver version matters for triage:
-/// PTX-JIT and driver-API compatibility bugs are driver-version-specific,
-/// and the bug-report template points reporters at this line.
-fn query_gpu_name_cap_and_driver() -> Option<(String, (u32, u32), String)> {
-    let output = Command::new("nvidia-smi")
-        .args([
-            "--query-gpu=name,compute_cap,driver_version",
-            "--format=csv,noheader",
-        ])
-        .output()
-        .ok()
-        .filter(|o| o.status.success())?;
-    parse_gpu_name_cap_and_driver(&String::from_utf8_lossy(&output.stdout))
-}
-
-/// Parse the first line of `nvidia-smi
-/// --query-gpu=name,compute_cap,driver_version` output into the GPU name,
-/// `(major, minor)` pair, and driver version. Splits on the LAST two commas:
-/// GPU names may contain commas in principle, `compute_cap` and
-/// `driver_version` never do.
-fn parse_gpu_name_cap_and_driver(stdout: &str) -> Option<(String, (u32, u32), String)> {
-    let line = stdout.lines().next()?;
-    let (rest, driver) = line.rsplit_once(',')?;
-    let (name, cap) = rest.rsplit_once(',')?;
-    Some((
-        name.trim().to_string(),
-        parse_compute_cap_field(cap)?,
-        driver.trim().to_string(),
-    ))
-}
-
-/// Format a `(major, minor)` compute-capability tuple as the `sm_XX` /
-/// `sm_XXX[a]` string the codegen backend expects on `CUDA_OXIDE_TARGET`.
-///
-/// Concatenates without a separator, matching CUDA conventions:
-/// `(7, 5)` → `"sm_75"`, `(12, 0)` → `"sm_120a"`.
-///
-/// # Arch-specific (`a`) suffix
-///
-/// Compute capability ≥ 9.0 always has an arch-specific PTX target (`sm_90a`,
-/// `sm_100a`, `sm_103a`, `sm_120a`, …) that is a strict superset of the plain
-/// target on that chip. The `a` form is what unlocks WGMMA on Hopper and
-/// `tcgen05` / TMA multicast / `cta_group::*` on Blackwell datacenter — and
-/// every chip that reports cc ≥ 9.0 *is* the `a`-variant chip in NVIDIA's
-/// lineup (there is no consumer Hopper, no non-`a` sm_100, and so on).
-///
-/// This helper is only used by [`detect_run_target_arch`] in `cargo oxide
-/// run`, where the local GPU is known exactly and no cross-compile is in
-/// flight. Emitting the `a` form there:
-///
-/// - **No false negatives:** kernels that need `tcgen05` / WGMMA compile and
-///   load on that GPU (was: silent fallback to `sm_100` / `sm_90` and a
-///   `ptxas: 'tcgen05.alloc' not supported on .target 'sm_100'` failure).
-/// - **No false positives:** cc < 9.0 keeps the plain `sm_XY` form, since
-///   there is no `sm_80a` / `sm_86a` / `sm_89a` target in the PTX ISA.
-/// - **Strict superset:** PTX targeting `sm_XYa` accepts every kernel that
-///   would have compiled for plain `sm_XY`; the `a` form only permits
-///   *additional* arch-specific intrinsics.
-fn format_sm_arch((major, minor): (u32, u32)) -> String {
-    if major >= 9 {
-        format!("sm_{}{}a", major, minor)
-    } else {
-        format!("sm_{}{}", major, minor)
-    }
-}
-
-fn inherited_or_configured_env(ctx: &Context, key: &str) -> Option<String> {
-    std::env::var(key).ok().or_else(|| {
-        ctx.config
-            .env
-            .iter()
-            .find(|(configured_key, _)| configured_key == key)
-            .map(|(_, value)| value.clone())
-    })
-}
-
-/// Build `LD_LIBRARY_PATH` for the child cargo process.
-///
-/// Includes the rustc sysroot lib (for `librustc_driver.so` etc.), the
-/// libmathdx lib (when `LIBMATHDX_PATH` is set), and any existing
-/// `LD_LIBRARY_PATH` from the parent environment.
-fn apply_ld_library_path(cmd: &mut Command, ctx: &Context) {
-    let mut ld_paths: Vec<String> = Vec::new();
-    if let Some(sysroot) = backend::get_rustc_sysroot() {
-        ld_paths.push(format!("{}/lib", sysroot));
-    }
-    if let Some(libmathdx_path) = inherited_or_configured_env(ctx, "LIBMATHDX_PATH") {
-        ld_paths.push(format!("{}/lib", libmathdx_path));
-    }
-    if let Some(existing) = inherited_or_configured_env(ctx, "LD_LIBRARY_PATH") {
-        ld_paths.push(existing);
-    }
-    if !ld_paths.is_empty() {
-        cmd.env("LD_LIBRARY_PATH", ld_paths.join(":"));
-    }
-}
-
-/// Touch main.rs to force recompilation (faster than cargo clean).
-fn touch_main_rs(example_dir: &Path) {
-    // Force a rebuild so the codegen backend re-runs and emits a fresh
-    // .ptx alongside the example. Touch every source file that might
-    // host `#[kernel]` items so multi-bin layouts (kernels in `lib.rs`,
-    // tests in `main.rs`, perf bench in `bin/<name>.rs`, etc.) all
-    // re-codegen on every `cargo oxide run/build` invocation.
-    for rel in ["src/main.rs", "src/lib.rs"] {
-        touch_source_file(&example_dir.join(rel));
-    }
-}
-
-fn touch_source_file(path: &Path) {
-    if path.exists()
-        && let Ok(content) = std::fs::read(path)
-    {
-        let _ = std::fs::write(path, content);
-    }
-}
-
-/// Artifacts are named after the crate, and cargo normalizes hyphens in
-/// package names to underscores (`rustlantis-smoke` emits
-/// `rustlantis_smoke.ptx`). Always go through this when deriving an
-/// artifact filename from an example name, or hyphenated examples keep
-/// stale artifacts forever.
-fn artifact_stem(example: &str) -> String {
-    example.replace('-', "_")
-}
-
-/// Return the PTX artifacts generated for a regular or metadata-interop project.
-fn ptx_artifact_paths(example_dir: &Path, example: &str) -> Vec<PathBuf> {
-    if let Some(interop) =
-        load_interop_config(example_dir).filter(|config| !config.device_crates.is_empty())
-    {
-        return interop
-            .device_crates
-            .iter()
-            .filter(|device_crate| device_crate.artifact_kind == InteropArtifactKind::Ptx)
-            .map(|device_crate| {
-                let manifest_path = example_dir.join(&device_crate.manifest_path);
-                let artifact_name = interop_device_artifact_name(&manifest_path, device_crate);
-
-                interop_device_artifact_path(example_dir, device_crate, &artifact_name)
-            })
-            .collect();
-    }
-
-    let stem = artifact_stem(example);
-    vec![example_dir.join(format!("{stem}.ptx"))]
-}
-
-fn read_ptx_artifact(path: &Path) -> Result<String, String> {
-    std::fs::read_to_string(path)
-        .map_err(|error| format!("could not read generated PTX {}: {error}", path.display()))
-}
-
-/// Print one generated PTX artifact.
-fn print_ptx_artifact(path: &Path) -> Result<(), String> {
-    let content = read_ptx_artifact(path)?;
-
-    let name = path
-        .file_name()
-        .map(|name| name.to_string_lossy().into_owned())
-        .unwrap_or_else(|| path.display().to_string());
-
-    println!();
-    println!("=========================================");
-    println!("PTX ({name})");
-    println!("=========================================");
-    print!("{content}");
-
-    if !content.ends_with('\n') {
-        println!();
-    }
-
-    Ok(())
-}
-
-/// Path to the NVVM IR (`.ll`) the backend emits for `example`. Named after the
-/// Cargo-normalized crate stem, so a hyphenated example resolves to the
-/// underscore-spelled file the build actually wrote. Route `emit-ltoir` reads
-/// through here rather than deriving the name from the raw example.
-fn emitted_ll_path(example_dir: &Path, example: &str) -> PathBuf {
-    example_dir.join(format!("{}.ll", artifact_stem(example)))
-}
-
-/// Default LTOIR output path for `example` when no explicit `--output` is given.
-/// Uses the same Cargo-normalized crate stem as [`emitted_ll_path`] so reads and
-/// writes agree on hyphenated examples.
-fn default_ltoir_path(example_dir: &Path, example: &str) -> PathBuf {
-    example_dir.join(format!("{}.ltoir", artifact_stem(example)))
-}
-
-const GENERATED_ARTIFACT_SUFFIXES: &[&str] = &[
-    "ptx",
-    "ll",
-    "opt.ll",
-    "ltoir",
-    "cubin",
-    "cubin.tmp",
-    "cubin.identity",
-    "ptx.identity",
-    "target",
-    "options",
-    "cubin.target",
-];
-
-fn generated_artifact_paths(project_dir: &Path, package_name: &str) -> Vec<PathBuf> {
-    let stem = artifact_stem(package_name);
-
-    GENERATED_ARTIFACT_SUFFIXES
-        .iter()
-        .map(|suffix| project_dir.join(format!("{stem}.{suffix}")))
-        .collect()
-}
-
-/// Remove stale generated artifacts (`.ptx`, `.ll`, `.ltoir`, `.cubin`) from a
-/// previous run so we can verify the build produces fresh output.
-fn clean_generated_files(example_dir: &Path, example: &str) {
-    for file in generated_artifact_paths(example_dir, example) {
-        if file.exists() {
-            let _ = std::fs::remove_file(file);
-        }
-    }
-}
-
-/// Human-readable label for the selected output format.
-fn format_label(emit_nvvm_ir: bool) -> &'static str {
-    if emit_nvvm_ir { "NVVM IR" } else { "PTX" }
-}
-
-/// Print generated artifacts (LLVM IR or PTX) to stdout after a pipeline build.
-fn show_generated_artifacts(example_dir: &Path, example: &str) {
-    let stem = artifact_stem(example);
-    let ll_file = example_dir.join(format!("{}.ll", stem));
-    let ptx_file = example_dir.join(format!("{}.ptx", stem));
-
-    if ll_file.exists() {
-        println!();
-        println!("=========================================");
-        println!("LLVM IR ({}.ll)", stem);
-        println!("=========================================");
-        if let Ok(content) = std::fs::read_to_string(&ll_file) {
-            println!("{}", content);
-        }
-    }
-
-    if ptx_file.exists() {
-        println!();
-        println!("=========================================");
-        println!("PTX ({}.ptx)", stem);
-        println!("=========================================");
-        if let Ok(content) = std::fs::read_to_string(&ptx_file) {
-            println!("{}", content);
-        }
-    }
-}
-
-// =========================================================================
-// cargo oxide new -- standalone project scaffolding
-// =========================================================================
-
-const GIT_REPO: &str = "https://github.com/NVlabs/cuda-oxide.git";
-
-const RUST_TOOLCHAIN_TOML: &str = r#"[toolchain]
-channel = "nightly-2026-04-03"
-components = ["rust-src", "rustc-dev", "rust-analyzer", "clippy", "rustfmt", "llvm-tools"]
-"#;
-
-const SCAFFOLD_GITIGNORE_EXTRA: &[&str] = &[
-    "/target/",
-    "**/*.bc", // bitcode leftovers not in the clean suffix list
-    ".DS_Store",
-];
-
-fn scaffold_gitignore() -> String {
-    let mut lines: Vec<String> = SCAFFOLD_GITIGNORE_EXTRA
-        .iter()
-        .map(|line| (*line).to_string())
-        .collect();
-    // Keep in lockstep with `GENERATED_ARTIFACT_SUFFIXES` so `cargo oxide new`
-    // ignores every artifact `cargo oxide clean` knows how to delete.
-    for suffix in GENERATED_ARTIFACT_SUFFIXES {
-        let pattern = format!("**/*.{suffix}");
-        if !lines.iter().any(|line| line == &pattern) {
-            lines.push(pattern);
-        }
-    }
-    // Stable order for readable diffs: keep the three fixed entries first,
-    // then sort generated patterns.
-    let (fixed, rest) = lines.split_at(SCAFFOLD_GITIGNORE_EXTRA.len());
-    let mut rest = rest.to_vec();
-    rest.sort();
-    let mut out = fixed.to_vec();
-    out.append(&mut rest);
-    out.push(String::new());
-    out.join("\n")
-}
-
-/// File contents produced by `cargo oxide new`.
-#[derive(Clone, Debug, Eq, PartialEq)]
-struct ScaffoldFiles {
-    cargo_toml: String,
-    rust_toolchain_toml: String,
-    gitignore: String,
-    readme: String,
-    main_rs: String,
-}
-
-fn scaffold_readme(name: &str, async_mode: bool) -> String {
-    let mode = if async_mode {
-        "async cuda-oxide"
-    } else {
-        "cuda-oxide"
-    };
-    let template_notes = if async_mode {
-        "The template is a vector-add kernel launched through `cuda-async`:\n\
-         `vecadd_async` returns a lazy `DeviceOperation` scheduled on the\n\
-         stream pool. See the cuda-oxide book getting-started chapter for the\n\
-         next steps."
-    } else {
-        "The template is a vector-add kernel. It uses `#[launch_contract]` and\n\
-         `PreparedLaunch` so geometry is checked before launch. See the\n\
-         cuda-oxide book getting-started chapter for the next steps."
-    };
-    format!(
-        r#"# {name}
-
-Scaffolded {mode} project.
-
-## Setup
-
-```bash
-cargo oxide doctor
-```
-
-Fix anything doctor reports before building.
-
-## Run
-
-```bash
-cargo oxide run
-```
-
-{template_notes}
-"#
-    )
-}
-
-fn scaffold_cargo_toml(name: &str, async_mode: bool) -> String {
-    if async_mode {
-        format!(
-            r#"[package]
-name = "{name}"
-version = "0.1.0"
-edition = "2024"
-
-[workspace]
-
-[dependencies]
-cuda-device = {{ git = "{GIT_REPO}" }}
-cuda-host = {{ git = "{GIT_REPO}", features = ["async"] }}
-cuda-core = {{ git = "{GIT_REPO}" }}
-cuda-async = {{ git = "{GIT_REPO}" }}
-cuda-bindings = {{ git = "{GIT_REPO}" }}
-tokio = {{ version = "1", features = ["rt", "rt-multi-thread", "macros"] }}
-"#
-        )
-    } else {
-        format!(
-            r#"[package]
-name = "{name}"
-version = "0.1.0"
-edition = "2024"
-
-[workspace]
-
-[dependencies]
-cuda-device = {{ git = "{GIT_REPO}" }}
-cuda-host = {{ git = "{GIT_REPO}" }}
-cuda-core = {{ git = "{GIT_REPO}" }}
-"#
-        )
-    }
-}
-
-fn scaffold_main_rs(async_mode: bool) -> String {
-    if async_mode {
-        r#"use cuda_device::{kernel, thread, DisjointSlice};
-use cuda_host::cuda_module;
-use cuda_async::device_context::init_device_contexts;
-use cuda_async::device_operation::DeviceOperation;
-use cuda_core::LaunchConfig;
-
-#[cuda_module]
-mod kernels {
-    use super::*;
-
-    #[kernel]
-    pub fn vecadd(a: &[f32], b: &[f32], mut c: DisjointSlice<f32>) {
-        let idx = thread::index_1d();
-        let idx_raw = idx.get();
-        if let Some(c_elem) = c.get_mut(idx) {
-            *c_elem = a[idx_raw] + b[idx_raw];
-        }
-    }
-}
-
-#[tokio::main]
-async fn main() -> Result<(), Box<dyn std::error::Error>> {
-    use cuda_async::device_box::DeviceBox;
-    use cuda_core::memory::{malloc_async, memcpy_dtoh_async, memcpy_htod_async};
-    use std::mem;
-
-    init_device_contexts(0, 1)?;
-    let module = kernels::load_async(0)?;
-
-    const N: usize = 1024;
-    let a_host: Vec<f32> = (0..N).map(|i| i as f32).collect();
-    let b_host: Vec<f32> = (0..N).map(|i| (i * 2) as f32).collect();
-
-    let (a_dev, b_dev, mut c_dev) = cuda_async::device_context::with_cuda_context(0, |ctx| {
-        let stream = ctx.default_stream();
-        let num_bytes = N * mem::size_of::<f32>();
-        unsafe {
-            let a = malloc_async(stream.cu_stream(), num_bytes).unwrap();
-            let b = malloc_async(stream.cu_stream(), num_bytes).unwrap();
-            let c = malloc_async(stream.cu_stream(), num_bytes).unwrap();
-            memcpy_htod_async(a, a_host.as_ptr(), num_bytes, stream.cu_stream()).unwrap();
-            memcpy_htod_async(b, b_host.as_ptr(), num_bytes, stream.cu_stream()).unwrap();
-            stream.synchronize().unwrap();
-            (
-                DeviceBox::<[f32]>::from_raw_parts(a, N, 0),
-                DeviceBox::<[f32]>::from_raw_parts(b, N, 0),
-                DeviceBox::<[f32]>::from_raw_parts(c, N, 0),
-            )
-        }
-    })?;
-
-    // SAFETY: this is a 1D launch and `vecadd` guards its index against the
-    // output length before writing.
-    unsafe {
-        module.vecadd_async(
-            LaunchConfig::for_num_elems(N as u32),
-            &a_dev,
-            &b_dev,
-            &mut c_dev,
-        )
-    }?
-    .sync()?;
-
-    let mut c_host = vec![0.0f32; N];
-    cuda_async::device_context::with_cuda_context(0, |ctx| {
-        let stream = ctx.default_stream();
-        unsafe {
-            memcpy_dtoh_async(
-                c_host.as_mut_ptr(),
-                c_dev.cu_deviceptr(),
-                N * mem::size_of::<f32>(),
-                stream.cu_stream(),
-            )
-            .unwrap();
-            stream.synchronize().unwrap();
-        }
-    })?;
-
-    let errors = (0..N)
-        .filter(|&i| (c_host[i] - (a_host[i] + b_host[i])).abs() > 1e-5)
-        .count();
-
-    if errors == 0 {
-        println!("PASSED: all {} elements correct", N);
-    } else {
-        eprintln!("FAILED: {} errors", errors);
-        std::process::exit(1);
-    }
-
-    Ok(())
-}
-"#
-        .to_string()
-    } else {
-        r#"use cuda_device::{kernel, launch_bounds, launch_contract, thread, DisjointSlice};
-use cuda_host::cuda_module;
-use cuda_core::{CudaContext, DeviceBuffer, LaunchConfig1D};
-
-#[cuda_module]
-mod kernels {
-    use super::*;
-
-    #[kernel]
-    #[launch_bounds(256)]
-    #[launch_contract(domain = 1, block = (256, 1, 1))]
-    pub fn vecadd(a: &[f32], b: &[f32], mut c: DisjointSlice<f32>) {
-        let idx = thread::index_1d();
-        let idx_raw = idx.get();
-        if let Some(c_elem) = c.get_mut(idx) {
-            *c_elem = a[idx_raw] + b[idx_raw];
-        }
-    }
-}
-
-fn main() -> Result<(), Box<dyn std::error::Error>> {
-    let ctx = CudaContext::new(0)?;
-    let stream = ctx.default_stream();
-
-    const N: usize = 1024;
-    let a_host: Vec<f32> = (0..N).map(|i| i as f32).collect();
-    let b_host: Vec<f32> = (0..N).map(|i| (i * 2) as f32).collect();
-
-    let a_dev = DeviceBuffer::from_host(&stream, &a_host)?;
-    let b_dev = DeviceBuffer::from_host(&stream, &b_host)?;
-    let mut c_dev = DeviceBuffer::<f32>::zeroed(&stream, N)?;
-
-    // SAFETY: this package owns the embedded device bundle produced for the
-    // kernels module above.
-    let module = unsafe { kernels::load(&ctx)? };
-    let prepared = module.prepare_vecadd(LaunchConfig1D::new((N as u32).div_ceil(256), 256, 0))?;
-    module.vecadd(&stream, &prepared, &a_dev, &b_dev, &mut c_dev)?;
-
-    let c_host = c_dev.to_host_vec(&stream)?;
-    let errors = (0..N)
-        .filter(|&i| (c_host[i] - (a_host[i] + b_host[i])).abs() > 1e-5)
-        .count();
-
-    if errors == 0 {
-        println!("PASSED: all {} elements correct", N);
-    } else {
-        eprintln!("FAILED: {} errors", errors);
-        std::process::exit(1);
-    }
-    Ok(())
-}
-"#
-        .to_string()
-    }
-}
-
-fn scaffold_files(name: &str, async_mode: bool) -> ScaffoldFiles {
-    ScaffoldFiles {
-        cargo_toml: scaffold_cargo_toml(name, async_mode),
-        rust_toolchain_toml: RUST_TOOLCHAIN_TOML.to_string(),
-        gitignore: scaffold_gitignore(),
-        readme: scaffold_readme(name, async_mode),
-        main_rs: scaffold_main_rs(async_mode),
-    }
-}
-
-/// Scaffold a new standalone cuda-oxide project.
-pub fn scaffold_new(name: &str, async_mode: bool) {
-    let project_dir = PathBuf::from(name);
-    if project_dir.exists() {
-        eprintln!("Error: directory '{}' already exists.", name);
-        std::process::exit(1);
-    }
-
-    let src_dir = project_dir.join("src");
-    std::fs::create_dir_all(&src_dir).unwrap_or_else(|e| {
-        eprintln!("Error creating directory: {}", e);
-        std::process::exit(1);
-    });
-
-    let files = scaffold_files(name, async_mode);
-    std::fs::write(project_dir.join("Cargo.toml"), files.cargo_toml)
-        .expect("Failed to write Cargo.toml");
-    std::fs::write(
-        project_dir.join("rust-toolchain.toml"),
-        files.rust_toolchain_toml,
-    )
-    .expect("Failed to write rust-toolchain.toml");
-    std::fs::write(project_dir.join(".gitignore"), files.gitignore)
-        .expect("Failed to write .gitignore");
-    std::fs::write(project_dir.join("README.md"), files.readme).expect("Failed to write README.md");
-    std::fs::write(src_dir.join("main.rs"), files.main_rs).expect("Failed to write src/main.rs");
-
-    let mode = if async_mode { " (async)" } else { "" };
-    println!("✓ Created cuda-oxide project '{}'{}", name, mode);
-    println!();
-    println!("  cd {}", name);
-    println!("  cargo oxide doctor");
-    println!("  cargo oxide run");
-}
-
-/// Locate an executable by name, first via `which` (PATH lookup), then by
-/// checking a list of common fallback absolute paths.
-fn find_executable(name: &str, fallback_paths: &[&str]) -> Option<PathBuf> {
-    if let Ok(output) = Command::new("which").arg(name).output()
-        && output.status.success()
-    {
-        let path = String::from_utf8_lossy(&output.stdout).trim().to_string();
-        if !path.is_empty() {
-            return Some(PathBuf::from(path));
-        }
-    }
-    for path in fallback_paths {
-        let p = PathBuf::from(path);
-        if p.exists() {
-            return Some(p);
-        }
-    }
-    None
-}
-
-/// Locate a CUDA Toolkit executable using the same configured toolkit roots as
-/// `doctor`, after the user's PATH and before generic system fallbacks.
-fn find_cuda_toolkit_executable(
-    ctx: &Context,
-    name: &str,
-    fallback_paths: &[&str],
-) -> Option<PathBuf> {
-    find_cuda_toolkit_executable_with_env(ctx, name, fallback_paths, |key| std::env::var(key).ok())
-}
-
-/// `find_cuda_toolkit_executable` with the ambient environment injected.
-///
-/// The process environment takes precedence over `cuda-oxide.toml`'s `env`, so
-/// resolution has to be injectable for unit tests: a developer with a real
-/// `CUDA_TOOLKIT_PATH` (or `CUDA_HOME`) exported would otherwise shadow the
-/// configured root a test is trying to assert on. Same rationale as
-/// `cuda_toolkit_root` and `cuda_header_candidates`.
-fn find_cuda_toolkit_executable_with_env(
-    ctx: &Context,
-    name: &str,
-    fallback_paths: &[&str],
-    mut get_env: impl FnMut(&str) -> Option<String>,
-) -> Option<PathBuf> {
-    if let Some(path) = find_executable(name, &[]) {
-        return Some(path);
-    }
-
-    let toolkit = cuda_toolkit_root(|key| {
-        get_env(key)
-            .filter(|value| !value.trim().is_empty())
-            .or_else(|| project_config_env(ctx, key).map(str::to_owned))
-    });
-    let configured = PathBuf::from(toolkit).join("bin").join(name);
-    if configured.exists() {
-        return Some(configured);
-    }
-
-    for path in fallback_paths {
-        let path = PathBuf::from(path);
-        if path.exists() {
-            return Some(path);
-        }
-    }
-    None
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use std::ffi::OsStr;
-
-    fn command_env(cmd: &Command, key: &str) -> Option<String> {
-        cmd.get_envs()
-            .find(|(name, _)| *name == OsStr::new(key))
-            .and_then(|(_, value)| value.map(|v| v.to_string_lossy().into_owned()))
-    }
-
-    fn decoded_rustflags(encoded: &str) -> Vec<&str> {
-        encoded.split(ENCODED_RUSTFLAGS_SEPARATOR).collect()
-    }
-
-    fn has_backend_identity_cfg(flags: &[&str]) -> bool {
-        flags.windows(2).any(|pair| {
-            pair[0] == "--cfg"
-                && pair[1].starts_with("cuda_oxide_internal_backend_identity=\"")
-                && pair[1].ends_with('"')
-        })
-    }
-
-    fn is_sha256(value: &str) -> bool {
-        value.len() == 64
-            && value
-                .bytes()
-                .all(|byte| byte.is_ascii_digit() || matches!(byte, b'a'..=b'f'))
-    }
-
-    /// `cargo_passthrough_command` with an empty ambient
-    /// `CUDA_OXIDE_MATERIALIZE_CUBIN`.
-    ///
-    /// Every test builds the command through this. Reading the real variable
-    /// would let an exported value override `opts.materialize_cubin` and drive
-    /// the test into materializer discovery, which re-executes the libtest
-    /// binary and then exits the process -- aborting the whole suite instead of
-    /// failing one case.
-    fn passthrough_command_for_test(
-        ctx: &Context,
-        cargo_subcommand: CargoPassthroughSubcommand,
-        opts: &CargoPassthroughOptions<'_>,
-        cargo_args: &[String],
-    ) -> Result<Command, String> {
-        cargo_passthrough_command_with_env(ctx, cargo_subcommand, opts, cargo_args, None)
-    }
-
-    fn cargo_artifact_freshness(
-        ctx: &Context,
-        opts: &CargoPassthroughOptions<'_>,
-        materializer_provenance: Option<&str>,
-    ) -> BTreeMap<String, bool> {
-        let mut cmd = passthrough_command_for_test(
-            ctx,
-            CargoPassthroughSubcommand::Build,
-            opts,
-            &["--message-format=json-render-diagnostics".to_string()],
-        )
-        .unwrap();
-        if let Some(provenance) = materializer_provenance {
-            // Exercise a non-canonical spelling accepted by the backend. The
-            // macro must still track exact provenance rather than keying that
-            // dependency on the wrapper's canonical `1` spelling.
-            cmd.env(MATERIALIZE_ENV, "true");
-            cmd.env(EXPECTED_PROVENANCE_ENV, provenance);
-        }
-        let output = cmd.output().expect("failed to run Cargo cache probe");
-        assert!(
-            output.status.success(),
-            "Cargo cache probe failed:\n{}",
-            String::from_utf8_lossy(&output.stderr)
-        );
-
-        String::from_utf8(output.stdout)
-            .expect("Cargo JSON must be UTF-8")
-            .lines()
-            .filter_map(|line| serde_json::from_str::<serde_json::Value>(line).ok())
-            .filter(|message| message["reason"] == "compiler-artifact")
-            .filter_map(|message| {
-                Some((
-                    message["target"]["name"].as_str()?.to_string(),
-                    message["fresh"].as_bool()?,
-                ))
-            })
-            .collect()
-    }
-
-    fn test_context(config: OxideConfig) -> Context {
-        Context {
-            workspace_root: PathBuf::from("/tmp/cargo-oxide-test-workspace"),
-            codegen_crate: PathBuf::from("/tmp/cargo-oxide-test-codegen"),
-            examples_dir: PathBuf::from("/tmp/cargo-oxide-test-examples"),
-            backend_so: PathBuf::from("llvm"),
-            is_workspace: false,
-            config,
-        }
-    }
-
-    fn unique_temp_dir(prefix: &str) -> PathBuf {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        std::env::temp_dir().join(format!("{}_{}_{}", prefix, std::process::id(), unique))
-    }
-
-    /// The examples walk backing `cargo oxide fmt` must reach nested manifests
-    /// and skip build directories.
-    ///
-    /// The gate's glob is `examples/**/Cargo.toml`, so a nested manifest is a
-    /// scope of its own; the loop this replaced read only the first level, which
-    /// is how `cutile_inter_kernel/simt` and `interop_cubin_identity/device`
-    /// went unformatted. `target` is skipped because a working tree has one and
-    /// a packaged manifest under it is not a crate this repository formats.
-    #[test]
-    fn collect_example_manifests_reaches_nested_and_skips_target() {
-        let root = unique_temp_dir("cargo_oxide_fmt_walk");
-        let write = |rel: &str| {
-            let path = root.join(rel);
-            std::fs::create_dir_all(path.parent().unwrap()).unwrap();
-            std::fs::write(&path, "[package]\nname = \"x\"\n").unwrap();
-        };
-
-        write("plain/Cargo.toml");
-        write("with_member/Cargo.toml");
-        write("with_member/kernel-lib/Cargo.toml");
-        write("own_workspace/Cargo.toml");
-        write("own_workspace/simt/Cargo.toml");
-        write("built/Cargo.toml");
-        write("built/target/package/vendored/Cargo.toml");
-        write(".hidden/Cargo.toml");
-        std::fs::create_dir_all(root.join("no_manifest_here")).unwrap();
-
-        let mut found = Vec::new();
-        collect_example_manifests(&root, &mut found);
-        let mut got: Vec<String> = found
-            .iter()
-            .map(|p| {
-                p.strip_prefix(&root)
-                    .unwrap()
-                    .to_string_lossy()
-                    .replace(std::path::MAIN_SEPARATOR, "/")
-            })
-            .collect();
-        got.sort();
-
-        assert_eq!(
-            got,
-            vec![
-                // `built` itself is a real example; only the manifest inside
-                // its `target/` is skipped.
-                "built/Cargo.toml",
-                "own_workspace/Cargo.toml",
-                "own_workspace/simt/Cargo.toml",
-                "plain/Cargo.toml",
-                "with_member/Cargo.toml",
-                "with_member/kernel-lib/Cargo.toml",
-            ],
-            "expected both nested manifests, and neither the one under target/ \
-             nor the one in a dot directory"
-        );
-
-        let _ = std::fs::remove_dir_all(&root);
-    }
-
-    fn test_materializer_handshake() -> cuda_artifact_finalizer::MaterializerHandshakeV1 {
-        let file = cuda_artifact_finalizer::ToolFileIdentity {
-            length: 123,
-            modified_seconds: 456,
-            modified_nanoseconds: 789,
-            device: Some(10),
-            inode: Some(11),
-            change_time_seconds: Some(12),
-            change_time_nanoseconds: Some(13),
-        };
-        cuda_artifact_finalizer::MaterializerHandshakeV1::new(
-            cuda_artifact_finalizer::PinnedToolProvenance {
-                sha256: [1; 32],
-                file,
-            },
-            cuda_artifact_finalizer::PinnedToolProvenance {
-                sha256: [2; 32],
-                file,
-            },
-            [3; 32],
-        )
-    }
-
-    #[test]
-    fn strict_materialization_boolean_rejects_presence_only_values() {
-        for value in ["1", "true", " YES ", "on"] {
-            assert!(parse_strict_bool(MATERIALIZE_ENV, value).unwrap());
-        }
-        for value in ["0", "false", " NO ", "off"] {
-            assert!(!parse_strict_bool(MATERIALIZE_ENV, value).unwrap());
-        }
-        for value in ["", "enabled", "2"] {
-            let error = parse_strict_bool(MATERIALIZE_ENV, value).unwrap_err();
-            assert!(error.contains("must be a boolean"), "{error}");
-        }
-    }
-
-    #[test]
-    fn materialization_rejects_nvvm_ir_as_a_competing_final_output() {
-        let error = prepare_materialization_result(
-            &test_context(OxideConfig::default()),
-            true,
-            Some("sm_90"),
-            true,
-        )
-        .expect_err("the two user-facing final output modes must conflict");
-
-        assert!(error.contains("cannot be combined with --emit-nvvm-ir"));
-    }
-
-    #[test]
-    fn materializer_discovery_uses_the_same_project_tool_environment_as_rustc() {
-        let configured_libdevice = "/configured/cuda/nvvm/libdevice/libdevice.10.bc";
-        let ctx = test_context(OxideConfig {
-            env: vec![
-                (
-                    "CUDA_OXIDE_LIBDEVICE".to_string(),
-                    configured_libdevice.to_string(),
-                ),
-                (
-                    "CUDA_TOOLKIT_PATH".to_string(),
-                    "/configured/cuda".to_string(),
-                ),
-                (
-                    "LD_LIBRARY_PATH".to_string(),
-                    "/configured/cuda/lib64".to_string(),
-                ),
-                (
-                    MATERIALIZER_HANDSHAKE_ENV.to_string(),
-                    "ambient-handshake-must-not-be-used".to_string(),
-                ),
-            ],
-            ..OxideConfig::default()
-        });
-        let discovery = materializer_discovery_command(&ctx, Path::new("/fake/cargo-oxide"));
-        let mut rustc_child = Command::new("cargo");
-        apply_common_codegen_env(
-            &mut rustc_child,
-            &ctx,
-            false,
-            false,
-            false,
-            DeviceDebug::Off,
-        );
-
-        for key in [
-            "CUDA_OXIDE_LIBDEVICE",
-            "CUDA_TOOLKIT_PATH",
-            "LD_LIBRARY_PATH",
-        ] {
-            assert_eq!(
-                command_env(&discovery, key),
-                command_env(&rustc_child, key),
-                "discovery and rustc must see the same {key}"
-            );
-        }
-        if std::env::var_os("CUDA_OXIDE_LIBDEVICE").is_none() {
-            assert_eq!(
-                command_env(&discovery, "CUDA_OXIDE_LIBDEVICE").as_deref(),
-                Some(configured_libdevice)
-            );
-        }
-        assert_eq!(command_env(&discovery, MATERIALIZER_HANDSHAKE_ENV), None);
-    }
-
-    #[test]
-    fn materializer_handshake_cache_accepts_only_consistent_v1_records() {
-        let root = unique_temp_dir("cargo_oxide_materializer_handshake");
-        fs::create_dir(&root).unwrap();
-        let mut ctx = test_context(OxideConfig::default());
-        ctx.workspace_root = root.clone();
-        let handshake = test_materializer_handshake();
-
-        write_materializer_handshake_cache(&ctx, &handshake);
-        let cached = read_materializer_handshake_cache(&ctx).unwrap();
-        assert_eq!(
-            serde_json::from_str::<cuda_artifact_finalizer::MaterializerHandshakeV1>(&cached)
-                .unwrap(),
-            handshake,
-        );
-
-        let mut inconsistent = handshake;
-        inconsistent.libnvvm.sha256[0] ^= 1;
-        fs::write(
-            materializer_handshake_cache_path(&ctx),
-            serde_json::to_string(&inconsistent).unwrap(),
-        )
-        .unwrap();
-        assert!(read_materializer_handshake_cache(&ctx).is_none());
-
-        fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn artifact_stem_normalizes_hyphens_like_cargo() {
-        assert_eq!(artifact_stem("rustlantis-smoke"), "rustlantis_smoke");
-        assert_eq!(artifact_stem("vecadd"), "vecadd");
-    }
-
-    #[test]
-    fn emit_ltoir_paths_use_normalized_crate_stem() {
-        // Regression for the emit-ltoir read/write mismatch on hyphenated
-        // crates: the backend writes `rustlantis_smoke.{ll,ltoir}`, so both the
-        // NVVM IR read and the default LTOIR write must resolve to the
-        // underscore stem rather than the raw example name.
-        let dir = Path::new("/tmp/cargo-oxide-emit-ltoir");
-        assert_eq!(
-            emitted_ll_path(dir, "rustlantis-smoke"),
-            dir.join("rustlantis_smoke.ll")
-        );
-        assert_eq!(
-            default_ltoir_path(dir, "rustlantis-smoke"),
-            dir.join("rustlantis_smoke.ltoir")
-        );
-        // A non-hyphenated example is unaffected.
-        assert_eq!(emitted_ll_path(dir, "vecadd"), dir.join("vecadd.ll"));
-        assert_eq!(default_ltoir_path(dir, "vecadd"), dir.join("vecadd.ltoir"));
-    }
-
-    #[test]
-    fn generated_file_cleanup_preserves_ltoir_cubin_cache() {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        let root = std::env::temp_dir().join(format!(
-            "cuda_oxide_clean_cache_{}_{}",
-            std::process::id(),
-            unique
-        ));
-        std::fs::create_dir_all(&root).unwrap();
-        for extension in ["ptx", "ll", "ltoir", "cubin", "target"] {
-            std::fs::write(root.join(format!("my_kernel.{extension}")), b"stale").unwrap();
-        }
-        let cached_cubin =
-            root.join(".oxide-artifacts/ltoir-cubin-cache/v1/entries/key/image.cubin");
-        std::fs::create_dir_all(cached_cubin.parent().unwrap()).unwrap();
-        std::fs::write(&cached_cubin, b"persistent cache entry").unwrap();
-
-        clean_generated_files(&root, "my-kernel");
-
-        for extension in ["ptx", "ll", "ltoir", "cubin", "target"] {
-            assert!(!root.join(format!("my_kernel.{extension}")).exists());
-        }
-        assert_eq!(
-            std::fs::read(&cached_cubin).unwrap(),
-            b"persistent cache entry"
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn clean_removes_only_local_target_and_matching_artifacts() {
-        let root = unique_temp_dir("cargo_oxide_clean_standalone");
-        std::fs::create_dir_all(root.join("target/debug")).unwrap();
-
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"
-[package]
-name = "my-kernel"
-version = "0.1.0"
-edition = "2024"
-"#,
-        )
-        .unwrap();
-
-        for suffix in GENERATED_ARTIFACT_SUFFIXES {
-            std::fs::write(root.join(format!("my_kernel.{suffix}")), b"generated").unwrap();
-        }
-
-        let unrelated_artifact = root.join("other_kernel.ptx");
-        std::fs::write(&unrelated_artifact, b"preserve").unwrap();
-
-        let cached_cubin =
-            root.join(".oxide-artifacts/ltoir-cubin-cache/v1/entries/key/image.cubin");
-        std::fs::create_dir_all(cached_cubin.parent().unwrap()).unwrap();
-        std::fs::write(&cached_cubin, b"persistent cache").unwrap();
-
-        let ctx = Context {
-            workspace_root: root.clone(),
-            codegen_crate: root.clone(),
-            examples_dir: root.clone(),
-            backend_so: root.join("unused-backend.so"),
-            is_workspace: false,
-            config: OxideConfig::default(),
-        };
-
-        let summary = clean_context(&ctx).unwrap();
-
-        assert_eq!(summary.removed_directories, 1);
-        assert_eq!(summary.removed_files, GENERATED_ARTIFACT_SUFFIXES.len());
-        assert!(!root.join("target").exists());
-
-        for suffix in GENERATED_ARTIFACT_SUFFIXES {
-            assert!(!root.join(format!("my_kernel.{suffix}")).exists());
-        }
-
-        assert_eq!(std::fs::read(&unrelated_artifact).unwrap(), b"preserve");
-        assert_eq!(std::fs::read(&cached_cubin).unwrap(), b"persistent cache");
-
-        let second_summary = clean_context(&ctx).unwrap();
-
-        assert_eq!(second_summary, CleanSummary::default());
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn workspace_clean_removes_root_backend_and_example_targets() {
-        let root = unique_temp_dir("cargo_oxide_clean_workspace");
-        let codegen_crate = root.join("crates/rustc-codegen-cuda");
-        let examples_dir = codegen_crate.join("examples");
-        let example_dir = examples_dir.join("demo");
-
-        std::fs::create_dir_all(root.join("target/debug")).unwrap();
-        std::fs::create_dir_all(codegen_crate.join("target/debug")).unwrap();
-        std::fs::create_dir_all(example_dir.join("target/debug")).unwrap();
-
-        std::fs::write(
-            example_dir.join("Cargo.toml"),
-            r#"
-[package]
-name = "demo"
-version = "0.1.0"
-edition = "2024"
-"#,
-        )
-        .unwrap();
-
-        std::fs::write(example_dir.join("demo.ptx"), b"generated").unwrap();
-
-        let ctx = Context {
-            workspace_root: root.clone(),
-            codegen_crate: codegen_crate.clone(),
-            examples_dir,
-            backend_so: root.join("unused-backend.so"),
-            is_workspace: true,
-            config: OxideConfig::default(),
-        };
-
-        let summary = clean_context(&ctx).unwrap();
-
-        assert_eq!(summary.removed_directories, 3);
-        assert_eq!(summary.removed_files, 1);
-        assert!(!root.join("target").exists());
-        assert!(!codegen_crate.join("target").exists());
-        assert!(!example_dir.join("target").exists());
-        assert!(!example_dir.join("demo.ptx").exists());
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[cfg(unix)]
-    #[test]
-    fn clean_refuses_symlinked_target_directory() {
-        use std::os::unix::fs::symlink;
-
-        let root = unique_temp_dir("cargo_oxide_clean_symlink");
-        let external = unique_temp_dir("cargo_oxide_clean_external");
-
-        std::fs::create_dir_all(&root).unwrap();
-        std::fs::create_dir_all(&external).unwrap();
-        std::fs::write(external.join("sentinel"), b"preserve").unwrap();
-
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"
-[package]
-name = "symlink-test"
-version = "0.1.0"
-edition = "2024"
-"#,
-        )
-        .unwrap();
-
-        symlink(&external, root.join("target")).unwrap();
-
-        let ctx = Context {
-            workspace_root: root.clone(),
-            codegen_crate: root.clone(),
-            examples_dir: root.clone(),
-            backend_so: root.join("unused-backend.so"),
-            is_workspace: false,
-            config: OxideConfig::default(),
-        };
-
-        let error = clean_context(&ctx).unwrap_err();
-
-        assert!(error.contains("symlinked target directory"), "{error}");
-        assert_eq!(
-            std::fs::read(external.join("sentinel")).unwrap(),
-            b"preserve"
-        );
-
-        std::fs::remove_dir_all(root).unwrap();
-        std::fs::remove_dir_all(external).unwrap();
-    }
-
-    #[test]
-    fn cargo_metadata_selection_prefers_default_run() {
-        let root = unique_temp_dir("cargo_oxide_default_run");
-        std::fs::create_dir_all(&root).unwrap();
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"
-[package]
-name = "multi-bin-package"
-default-run = "main_bin"
-version = "0.1.0"
-edition = "2024"
-
-[[bin]]
-name = "main_bin"
-path = "src/main.rs"
-
-[[bin]]
-name = "other_bin"
-path = "src/other.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::create_dir_all(root.join("src")).unwrap();
-        std::fs::write(root.join("src/main.rs"), "fn main() {}\n").unwrap();
-        std::fs::write(root.join("src/other.rs"), "fn main() {}\n").unwrap();
-
-        let selection = cargo_executable_selection(&root, None).unwrap();
-        assert_eq!(selection.packages.len(), 1);
-        let package = &selection.packages[0];
-        assert!(package.package_id.starts_with("path+file://"));
-        assert!(package.package_id.contains("multi-bin-package@0.1.0"));
-        assert_eq!(package.package_name, "multi-bin-package");
-        assert_eq!(package.default_run.as_deref(), Some("main_bin"));
-        assert_eq!(selection.explicit_bin, None);
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn cargo_json_ignores_bins_disabled_by_required_features() {
-        let root = unique_temp_dir("cargo_oxide_artifact_required_features");
-        std::fs::create_dir_all(root.join("src")).unwrap();
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"
-[package]
-name = "feature-gated-bins"
-version = "0.1.0"
-edition = "2024"
-
-[features]
-extra = []
-
-[[bin]]
-name = "always"
-path = "src/always.rs"
-
-[[bin]]
-name = "gated"
-path = "src/gated.rs"
-required-features = ["extra"]
-"#,
-        )
-        .unwrap();
-        std::fs::write(root.join("src/always.rs"), "fn main() {}\n").unwrap();
-        std::fs::write(root.join("src/gated.rs"), "fn main() {}\n").unwrap();
-
-        let mut cmd = Command::new("cargo");
-        cmd.args(["build", "--release"]).current_dir(&root);
-        let binary = run_cargo_build_for_executable(&mut cmd, &root, None).unwrap();
-
-        let expected_name = format!("always{}", std::env::consts::EXE_SUFFIX);
-        assert_eq!(
-            binary.file_name().and_then(OsStr::to_str),
-            Some(expected_name.as_str())
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn cargo_json_selects_custom_bin_in_configured_target_dir() {
-        let root = unique_temp_dir("cargo_oxide_artifact_binary");
-        std::fs::create_dir_all(&root).unwrap();
-        std::fs::create_dir_all(root.join(".cargo")).unwrap();
-        std::fs::create_dir_all(root.join("src")).unwrap();
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"
-[package]
-name = "package-bin"
-version = "0.1.0"
-edition = "2024"
-
-[[bin]]
-name = "actual-bin"
-path = "src/main.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::write(root.join("src/main.rs"), "fn main() {}\n").unwrap();
-        std::fs::write(
-            root.join(".cargo/config.toml"),
-            "[build]\ntarget-dir = \"configured-target\"\n",
-        )
-        .unwrap();
-
-        let mut cmd = Command::new("cargo");
-        cmd.args(["build", "--release"]).current_dir(&root);
-        let binary = run_cargo_build_for_executable(&mut cmd, &root, None).unwrap();
-
-        assert!(binary.exists());
-        let expected_name = format!("actual-bin{}", std::env::consts::EXE_SUFFIX);
-        assert_eq!(
-            binary.file_name().and_then(OsStr::to_str),
-            Some(expected_name.as_str())
-        );
-        assert!(
-            binary
-                .components()
-                .any(|part| part.as_os_str() == "configured-target")
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn cargo_json_selects_single_binary_from_virtual_workspace() {
-        let root = unique_temp_dir("cargo_oxide_artifact_workspace");
-        let member = root.join("member");
-        std::fs::create_dir_all(member.join("src")).unwrap();
-        std::fs::write(
-            root.join("Cargo.toml"),
-            "[workspace]\nmembers = [\"member\"]\nresolver = \"2\"\n",
-        )
-        .unwrap();
-        std::fs::write(
-            member.join("Cargo.toml"),
-            r#"
-[package]
-name = "workspace-package"
-version = "0.1.0"
-edition = "2024"
-
-[[bin]]
-name = "workspace-bin"
-path = "src/main.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::write(member.join("src/main.rs"), "fn main() {}\n").unwrap();
-
-        let mut cmd = Command::new("cargo");
-        cmd.args(["build", "--release"]).current_dir(&root);
-        let binary = run_cargo_build_for_executable(&mut cmd, &root, None).unwrap();
-
-        let expected_name = format!("workspace-bin{}", std::env::consts::EXE_SUFFIX);
-        assert_eq!(
-            binary.file_name().and_then(OsStr::to_str),
-            Some(expected_name.as_str())
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn cargo_json_honors_virtual_workspace_default_member_default_run() {
-        let root = unique_temp_dir("cargo_oxide_artifact_default_member");
-        let app = root.join("app");
-        let ignored = root.join("ignored");
-        std::fs::create_dir_all(app.join("src")).unwrap();
-        std::fs::create_dir_all(ignored.join("src")).unwrap();
-        std::fs::write(
-            root.join("Cargo.toml"),
-            "[workspace]\nmembers = [\"app\", \"ignored\"]\ndefault-members = [\"app\"]\nresolver = \"2\"\n",
-        )
-        .unwrap();
-        std::fs::write(
-            app.join("Cargo.toml"),
-            r#"
-[package]
-name = "selected-package"
-default-run = "chosen-bin"
-version = "0.1.0"
-edition = "2024"
-
-[[bin]]
-name = "chosen-bin"
-path = "src/chosen.rs"
-
-[[bin]]
-name = "other-bin"
-path = "src/other.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::write(app.join("src/chosen.rs"), "fn main() {}\n").unwrap();
-        std::fs::write(app.join("src/other.rs"), "fn main() {}\n").unwrap();
-        std::fs::write(
-            ignored.join("Cargo.toml"),
-            r#"
-[package]
-name = "ignored-package"
-version = "0.1.0"
-edition = "2024"
-"#,
-        )
-        .unwrap();
-        std::fs::write(ignored.join("src/main.rs"), "fn main() {}\n").unwrap();
-
-        let mut cmd = Command::new("cargo");
-        cmd.args(["build", "--release"]).current_dir(&root);
-        let binary = run_cargo_build_for_executable(&mut cmd, &root, None).unwrap();
-
-        let expected_name = format!("chosen-bin{}", std::env::consts::EXE_SUFFIX);
-        assert_eq!(
-            binary.file_name().and_then(OsStr::to_str),
-            Some(expected_name.as_str())
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn cargo_json_honors_nonvirtual_workspace_default_member() {
-        let root = unique_temp_dir("cargo_oxide_artifact_nonvirtual_default_member");
-        let member = root.join("member");
-        std::fs::create_dir_all(root.join("src")).unwrap();
-        std::fs::create_dir_all(member.join("src")).unwrap();
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"
-[package]
-name = "workspace-root-package"
-version = "0.1.0"
-edition = "2024"
-
-[workspace]
-members = ["member"]
-default-members = ["member"]
-resolver = "2"
-
-[[bin]]
-name = "root-bin"
-path = "src/main.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::write(root.join("src/main.rs"), "fn main() {}\n").unwrap();
-        std::fs::write(
-            member.join("Cargo.toml"),
-            r#"
-[package]
-name = "selected-member"
-version = "0.1.0"
-edition = "2024"
-
-[[bin]]
-name = "member-bin"
-path = "src/main.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::write(member.join("src/main.rs"), "fn main() {}\n").unwrap();
-
-        let mut cmd = Command::new("cargo");
-        cmd.args(["build", "--release"]).current_dir(&root);
-        let binary = run_cargo_build_for_executable(&mut cmd, &root, None).unwrap();
-
-        let expected_name = format!("member-bin{}", std::env::consts::EXE_SUFFIX);
-        assert_eq!(
-            binary.file_name().and_then(OsStr::to_str),
-            Some(expected_name.as_str())
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn cargo_json_explicit_bin_selects_one_of_multiple_default_members() {
-        let root = unique_temp_dir("cargo_oxide_artifact_multiple_default_members");
-        let first = root.join("first");
-        let second = root.join("second");
-        std::fs::create_dir_all(first.join("src")).unwrap();
-        std::fs::create_dir_all(second.join("src")).unwrap();
-        std::fs::write(
-            root.join("Cargo.toml"),
-            "[workspace]\nmembers = [\"first\", \"second\"]\ndefault-members = [\"first\", \"second\"]\nresolver = \"2\"\n",
-        )
-        .unwrap();
-        std::fs::write(
-            first.join("Cargo.toml"),
-            r#"
-[package]
-name = "first-package"
-version = "0.1.0"
-edition = "2024"
-
-[[bin]]
-name = "first-bin"
-path = "src/main.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::write(first.join("src/main.rs"), "fn main() {}\n").unwrap();
-        std::fs::write(
-            second.join("Cargo.toml"),
-            r#"
-[package]
-name = "second-package"
-version = "0.1.0"
-edition = "2024"
-
-[[bin]]
-name = "chosen-bin"
-path = "src/main.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::write(second.join("src/main.rs"), "fn main() {}\n").unwrap();
-
-        let mut cmd = Command::new("cargo");
-        cmd.args(["build", "--release", "--bin", "chosen-bin"])
-            .current_dir(&root);
-        let binary = run_cargo_build_for_executable(&mut cmd, &root, Some("chosen-bin")).unwrap();
-
-        let expected_name = format!("chosen-bin{}", std::env::consts::EXE_SUFFIX);
-        assert_eq!(
-            binary.file_name().and_then(OsStr::to_str),
-            Some(expected_name.as_str())
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn explicit_bin_must_be_unique_across_selected_packages() {
-        let selection = CargoExecutableSelection {
-            packages: vec![
-                CargoSelectedPackage {
-                    package_id: "first-package 0.1.0".to_string(),
-                    package_name: "first-package".to_string(),
-                    default_run: None,
-                },
-                CargoSelectedPackage {
-                    package_id: "second-package 0.1.0".to_string(),
-                    package_name: "second-package".to_string(),
-                    default_run: None,
-                },
-            ],
-            explicit_bin: Some("shared-bin".to_string()),
-        };
-        let artifacts = vec![
-            CargoExecutableArtifact {
-                package_id: "first-package 0.1.0".to_string(),
-                target_name: "shared-bin".to_string(),
-                path: PathBuf::from("/tmp/first/shared-bin"),
-            },
-            CargoExecutableArtifact {
-                package_id: "second-package 0.1.0".to_string(),
-                target_name: "shared-bin".to_string(),
-                path: PathBuf::from("/tmp/second/shared-bin"),
-            },
-        ];
-
-        let error = select_cargo_executable_artifact(&selection, &artifacts)
-            .expect_err("the binary name does not uniquely identify an artifact");
-
-        assert!(error.contains("multiple selected packages"), "{error}");
-        assert!(error.contains("first-package"), "{error}");
-        assert!(error.contains("second-package"), "{error}");
-    }
-
-    #[test]
-    fn one_executable_package_is_selected_alongside_library_only_defaults() {
-        let selection = CargoExecutableSelection {
-            packages: vec![
-                CargoSelectedPackage {
-                    package_id: "library-package 0.1.0".to_string(),
-                    package_name: "library-package".to_string(),
-                    default_run: None,
-                },
-                CargoSelectedPackage {
-                    package_id: "application-package 0.1.0".to_string(),
-                    package_name: "application-package".to_string(),
-                    default_run: None,
-                },
-            ],
-            explicit_bin: None,
-        };
-        let artifact = CargoExecutableArtifact {
-            package_id: "application-package 0.1.0".to_string(),
-            target_name: "application-bin".to_string(),
-            path: PathBuf::from("/tmp/application/application-bin"),
-        };
-
-        assert_eq!(
-            select_cargo_executable_artifact(&selection, &[artifact]).unwrap(),
-            PathBuf::from("/tmp/application/application-bin")
-        );
-    }
-
-    #[test]
-    fn unbuilt_default_run_is_not_skipped_for_another_selected_package() {
-        let selection = CargoExecutableSelection {
-            packages: vec![
-                CargoSelectedPackage {
-                    package_id: "first-package 0.1.0".to_string(),
-                    package_name: "first-package".to_string(),
-                    default_run: Some("gated-bin".to_string()),
-                },
-                CargoSelectedPackage {
-                    package_id: "second-package 0.1.0".to_string(),
-                    package_name: "second-package".to_string(),
-                    default_run: None,
-                },
-            ],
-            explicit_bin: None,
-        };
-        let artifacts = [CargoExecutableArtifact {
-            package_id: "second-package 0.1.0".to_string(),
-            target_name: "other-bin".to_string(),
-            path: PathBuf::from("/tmp/second/other-bin"),
-        }];
-
-        let error = select_cargo_executable_artifact(&selection, &artifacts)
-            .expect_err("a missing default-run must not fall back to another package");
-
-        assert!(error.contains("first-package"), "{error}");
-        assert!(error.contains("target `gated-bin`"), "{error}");
-    }
-
-    #[test]
-    fn cargo_json_errors_when_requested_bin_was_not_built() {
-        let root = unique_temp_dir("cargo_oxide_artifact_missing_bin");
-        std::fs::create_dir_all(root.join("src")).unwrap();
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"
-[package]
-name = "package-bin"
-version = "0.1.0"
-edition = "2024"
-
-[[bin]]
-name = "actual-bin"
-path = "src/actual.rs"
-
-[[bin]]
-name = "other-bin"
-path = "src/other.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::write(root.join("src/actual.rs"), "fn main() {}\n").unwrap();
-        std::fs::write(root.join("src/other.rs"), "fn main() {}\n").unwrap();
-
-        let mut cmd = Command::new("cargo");
-        cmd.args(["build", "--release", "--bin", "actual-bin"])
-            .current_dir(&root);
-        let error = run_cargo_build_for_executable(&mut cmd, &root, Some("other-bin"))
-            .expect_err("requested but unbuilt binary should be rejected");
-
-        assert!(error.contains("target `other-bin`"), "{error}");
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn cargo_json_errors_when_default_run_was_not_built() {
-        let root = unique_temp_dir("cargo_oxide_artifact_missing_default_run");
-        std::fs::create_dir_all(root.join("src")).unwrap();
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"
-[package]
-name = "package-bin"
-default-run = "default-bin"
-version = "0.1.0"
-edition = "2024"
-
-[[bin]]
-name = "default-bin"
-path = "src/default.rs"
-
-[[bin]]
-name = "other-bin"
-path = "src/other.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::write(root.join("src/default.rs"), "fn main() {}\n").unwrap();
-        std::fs::write(root.join("src/other.rs"), "fn main() {}\n").unwrap();
-
-        let mut cmd = Command::new("cargo");
-        cmd.args(["build", "--release", "--bin", "other-bin"])
-            .current_dir(&root);
-        let error = run_cargo_build_for_executable(&mut cmd, &root, None)
-            .expect_err("unbuilt default-run binary should be rejected");
-
-        assert!(error.contains("target `default-bin`"), "{error}");
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn artifact_selection_ignores_executable_artifacts_from_other_packages() {
-        let selection = CargoExecutableSelection {
-            packages: vec![CargoSelectedPackage {
-                package_id: "app 0.1.0".to_string(),
-                package_name: "app".to_string(),
-                default_run: None,
-            }],
-            explicit_bin: Some("app-bin".to_string()),
-        };
-        let artifacts = vec![
-            CargoExecutableArtifact {
-                package_id: "build-tool 0.1.0".to_string(),
-                target_name: "app-bin".to_string(),
-                path: PathBuf::from("/tmp/build-tool/app-bin"),
-            },
-            CargoExecutableArtifact {
-                package_id: "app 0.1.0".to_string(),
-                target_name: "helper-bin".to_string(),
-                path: PathBuf::from("/tmp/app/helper-bin"),
-            },
-        ];
-
-        let error = select_cargo_executable_artifact(&selection, &artifacts)
-            .expect_err("foreign package artifacts must not be selected");
-        assert!(error.contains("target `app-bin`"), "{error}");
-        assert!(error.contains("selected packages app"), "{error}");
-    }
-
-    #[test]
-    fn sanitizer_adds_nonzero_error_exitcode_by_default() {
-        let invocation =
-            sanitizer_invocation_args(&["--leak-check".to_string(), "full".to_string()]);
-
-        assert_eq!(
-            invocation.args,
-            ["--error-exitcode", "86", "--leak-check", "full"]
-        );
-        assert!(invocation.uses_default_error_exitcode);
-        assert!(!invocation.status_checks_weakened);
-    }
-
-    #[test]
-    fn sanitizer_preserves_explicit_zero_error_exitcode_without_claiming_detection() {
-        let separated = sanitizer_invocation_args(&[
-            "--error-exitcode".to_string(),
-            "0".to_string(),
-            "--leak-check".to_string(),
-        ]);
-        let equals = sanitizer_invocation_args(&["--error-exitcode=0".to_string()]);
-        let repeated = sanitizer_invocation_args(&[
-            "--error-exitcode=86".to_string(),
-            "--error-exitcode=0".to_string(),
-        ]);
-
-        assert_eq!(separated.args, ["--error-exitcode", "0", "--leak-check"]);
-        assert!(!separated.uses_default_error_exitcode);
-        assert!(!separated.status_checks_weakened);
-        assert_eq!(equals.args, ["--error-exitcode=0"]);
-        assert!(!equals.uses_default_error_exitcode);
-        assert_eq!(repeated.args, ["--error-exitcode=86", "--error-exitcode=0"]);
-        assert!(!repeated.uses_default_error_exitcode);
-    }
-
-    #[test]
-    fn sanitizer_detects_options_that_weaken_success_status() {
-        for args in [
-            vec!["--check-exit-code=no".to_string()],
-            vec!["--check-exit-code".to_string(), "no".to_string()],
-            vec!["--require-cuda-init=no".to_string()],
-            vec!["--require-cuda-init".to_string(), "NO".to_string()],
-        ] {
-            let invocation = sanitizer_invocation_args(&args);
-            assert!(invocation.status_checks_weakened, "{args:?}");
-        }
-    }
-
-    #[test]
-    fn sanitize_interop_codegen_defaults_to_line_tables_and_forwards_no_fmad() {
-        let ctx = test_context(OxideConfig::default());
-        let mut cmd = Command::new("cargo");
-
-        apply_interop_device_codegen_options_with_env(
-            &mut cmd,
-            &ctx,
-            false,
-            InteropDeviceBuildOptions {
-                no_fmad: true,
-                unchecked_indexing: false,
-                sanitizer_line_tables: true,
-            },
-            false,
-        );
-
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_NO_FMA").as_deref(), Some("1"));
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_DEBUG").as_deref(),
-            Some("line-tables")
-        );
-
-        let fingerprint = sanitize_codegen_fingerprint(
-            &ctx,
-            false,
-            true,
-            false,
-            DeviceDebug::Off,
-            Some("sm_80"),
-            None,
-            Some(Path::new("/tmp/generated-ptx")),
-            &MaterializationMode::default(),
-        );
-        apply_codegen_configuration(
-            &mut cmd,
-            &ctx,
-            CodegenProfilePolicy::ReleaseLike,
-            &[],
-            &fingerprint,
-        )
-        .unwrap();
-        let encoded = command_env(&cmd, "CARGO_ENCODED_RUSTFLAGS").unwrap();
-        assert!(has_backend_identity_cfg(&decoded_rustflags(&encoded)));
-        assert_eq!(
-            command_env(&cmd, CODEGEN_FINGERPRINT_ENV).as_deref(),
-            Some(fingerprint.as_str())
-        );
-    }
-
-    #[test]
-    fn sanitize_device_debug_flag_overrides_the_line_tables_default() {
-        let ctx = test_context(OxideConfig::default());
-        let mut cmd = Command::new("cargo");
-
-        // Mirror codegen_build_host_binary's ordering: the flag's level lands
-        // on `cmd` first, then the sanitizer default runs. `env_debug_set` is
-        // injected as false, so with no ambient CUDA_OXIDE_DEBUG the explicit
-        // flag alone must suppress the line-tables default.
-        apply_common_codegen_env(&mut cmd, &ctx, false, false, false, DeviceDebug::Full);
-        apply_default_sanitizer_line_tables_with_env(&mut cmd, &ctx, false, DeviceDebug::Full);
-
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_DEBUG").as_deref(),
-            Some("full")
-        );
-    }
-
-    #[test]
-    fn standard_interop_codegen_forwards_no_fmad_without_debug_override() {
-        let ctx = test_context(OxideConfig::default());
-        let mut cmd = Command::new("cargo");
-
-        apply_interop_device_codegen_options_with_env(
-            &mut cmd,
-            &ctx,
-            false,
-            InteropDeviceBuildOptions::standard(true, false),
-            false,
-        );
-
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_NO_FMA").as_deref(), Some("1"));
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_DEBUG"), None);
-    }
-
-    #[test]
-    fn interop_fingerprint_tracks_artifact_mode_and_device_features() {
-        let ctx = test_context(OxideConfig::default());
-        let fingerprint = |emit_nvvm_ir: bool, device_features: Option<&str>| {
-            interop_codegen_fingerprint(
-                &ctx,
-                false,
-                false,
-                false,
-                DeviceDebug::Off,
-                Some("sm_120a"),
-                None,
-                Path::new("/tmp/cuda-oxide-artifacts"),
-                emit_nvvm_ir,
-                device_features,
-                false,
-                &MaterializationMode::default(),
-            )
-        };
-
-        assert_ne!(fingerprint(false, None), fingerprint(true, None));
-        assert_ne!(
-            fingerprint(true, None),
-            fingerprint(true, Some("tensor-cores"))
-        );
-    }
-
-    #[test]
-    fn interop_codegen_forwards_unchecked_indexing() {
-        let ctx = test_context(OxideConfig::default());
-        let mut cmd = Command::new("cargo");
-
-        apply_interop_device_codegen_options_with_env(
-            &mut cmd,
-            &ctx,
-            false,
-            InteropDeviceBuildOptions::standard(false, true),
-            false,
-        );
-
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_UNCHECKED_INDEXING").as_deref(),
-            Some("1")
-        );
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_NO_FMA"), None);
-    }
-
-    #[test]
-    fn sanitize_fingerprint_tracks_output_affecting_settings() {
-        let ctx = test_context(OxideConfig::default());
-        // Empty inherited environment, matching
-        // `passthrough_fingerprint_tracks_output_affecting_settings`. An
-        // ambient CUDA_OXIDE_NO_FMA / CUDA_OXIDE_UNCHECKED_INDEXING is folded
-        // into the digest on its own, so reading the real environment would
-        // make toggling the corresponding argument a no-op and collapse these
-        // fingerprints onto the base.
-        let inherited_env = BTreeMap::new();
-        let fingerprint = |no_fmad: bool,
-                           unchecked_indexing: bool,
-                           target_arch: Option<&str>,
-                           detected_device_arch: Option<&str>,
-                           ptx_dir: Option<&Path>| {
-            sanitize_codegen_fingerprint_with_env(
-                &ctx,
-                false,
-                no_fmad,
-                unchecked_indexing,
-                DeviceDebug::Off,
-                target_arch,
-                detected_device_arch,
-                ptx_dir,
-                &MaterializationMode::default(),
-                &inherited_env,
-            )
-        };
-
-        let base = fingerprint(false, false, None, Some("sm_80"), None);
-
-        for changed in [
-            fingerprint(true, false, None, Some("sm_80"), None),
-            fingerprint(false, true, None, Some("sm_80"), None),
-            fingerprint(false, false, None, Some("sm_90"), None),
-            fingerprint(false, false, Some("sm_80"), None, None),
-            fingerprint(
-                false,
-                false,
-                None,
-                Some("sm_80"),
-                Some(Path::new("/tmp/generated-ptx")),
-            ),
-        ] {
-            assert_ne!(base, changed);
-        }
-    }
-
-    #[test]
-    fn pipeline_diagnostics_have_a_distinct_device_fingerprint() {
-        let ctx = test_context(OxideConfig::default());
-        let materialization = MaterializationMode::default();
-        let standard = standard_codegen_fingerprint(
-            &ctx,
-            true,
-            false,
-            false,
-            DeviceDebug::Off,
-            false,
-            Some("sm_86"),
-            None,
-            &materialization,
-        );
-        let pipeline = pipeline_codegen_fingerprint(
-            &ctx,
-            false,
-            false,
-            DeviceDebug::Off,
-            false,
-            Some("sm_86"),
-            &materialization,
-        );
-
-        assert_ne!(standard, pipeline);
-    }
-
-    /// A `Context` whose `cuda-oxide.toml` points `CUDA_TOOLKIT_PATH` at
-    /// `root`, alongside a fake executable named `name` under `root/bin`.
-    fn toolkit_context_with_tool(root: &Path, name: &str) -> (Context, PathBuf) {
-        let tool = root.join("bin").join(name);
-        std::fs::create_dir_all(tool.parent().unwrap()).unwrap();
-        std::fs::write(&tool, b"fake tool").unwrap();
-        let ctx = test_context(OxideConfig {
-            env: vec![(
-                "CUDA_TOOLKIT_PATH".to_string(),
-                root.to_string_lossy().into_owned(),
-            )],
-            ..OxideConfig::default()
-        });
-        (ctx, tool)
-    }
-
-    /// Every table entry pairs a tool with its own fallback list. Pure, so it
-    /// covers all three tools on every host: pairing `nvcc` with
-    /// `CUDA_GDB_FALLBACK_PATHS` is a one-token slip that no filesystem test
-    /// using a fabricated name could see.
-    #[test]
-    fn each_toolkit_tool_is_paired_with_its_own_fallback_paths() {
-        assert_eq!(DOCTOR_TOOLKIT_TOOLS.len(), 3);
-        for (name, fallbacks) in DOCTOR_TOOLKIT_TOOLS {
-            assert!(!fallbacks.is_empty(), "{name} has no fallback paths");
-            for path in fallbacks {
-                assert_eq!(
-                    Path::new(path).file_name().and_then(|n| n.to_str()),
-                    Some(name),
-                    "{name} lists a fallback for a different tool: {path}"
-                );
-            }
-        }
-    }
-
-    /// The lookup itself: each tool gets its own list, and an unknown name gets
-    /// none rather than another tool's. Pure, so it holds on every host.
-    #[test]
-    fn the_fallback_lookup_returns_each_tools_own_list() {
-        assert_eq!(toolkit_tool_fallbacks("nvcc"), NVCC_FALLBACK_PATHS);
-        assert_eq!(toolkit_tool_fallbacks("cuda-gdb"), CUDA_GDB_FALLBACK_PATHS);
-        assert_eq!(
-            toolkit_tool_fallbacks("compute-sanitizer"),
-            COMPUTE_SANITIZER_FALLBACK_PATHS
-        );
-        assert!(toolkit_tool_fallbacks("ptxas").is_empty());
-    }
-
-    /// Every call site names a tool the table knows. `doctor_toolkit_tool`
-    /// falls back to an empty list for an unknown name, so a typo would
-    /// silently drop the standard install roots rather than fail.
-    #[test]
-    fn every_doctor_toolkit_tool_call_names_a_tool_in_the_table() {
-        let source = include_str!("commands.rs");
-        let mut calls = 0;
-        for (index, _) in source.match_indices("doctor_toolkit_tool(ctx, \"") {
-            let rest = &source[index + "doctor_toolkit_tool(ctx, \"".len()..];
-            let name = &rest[..rest.find('"').expect("a closing quote")];
-            assert!(
-                DOCTOR_TOOLKIT_TOOLS.iter().any(|(tool, _)| *tool == name),
-                "{name} is probed but absent from DOCTOR_TOOLKIT_TOOLS, so it \
-                 would silently lose its fallback paths"
-            );
-            calls += 1;
-        }
-        assert_eq!(
-            calls,
-            DOCTOR_TOOLKIT_TOOLS.len(),
-            "every table entry is probed once"
-        );
-    }
-
-    /// Unaffected control: the configured toolkit root is preferred over the
-    /// standard install roots, so pointing `CUDA_TOOLKIT_PATH` at a toolkit does
-    /// not start picking up `/usr/local/cuda`. Discovery order is unchanged by
-    /// this fix; only which function `doctor` calls changed.
-    ///
-    /// PATH precedence is deliberately *not* asserted here. `find_executable`
-    /// shells out to `which`, so testing it would mean mutating the process
-    /// `PATH` -- `unsafe` in edition 2024 and racy across the test threads. The
-    /// end-to-end evidence in the pull request covers that case against the real
-    /// binary instead, which is the stronger check anyway.
-    #[test]
-    fn the_configured_root_is_preferred_over_the_standard_install_roots() {
-        let root = unique_temp_dir("cargo_oxide_doctor_order");
-        let name = "cuda-oxide-test-doctor-order";
-        let under_toolkit = root.join("bin").join(name);
-        std::fs::create_dir_all(under_toolkit.parent().unwrap()).unwrap();
-        std::fs::write(&under_toolkit, b"fake tool").unwrap();
-        let fallback = root.join("fallback").join(name);
-        std::fs::create_dir_all(fallback.parent().unwrap()).unwrap();
-        std::fs::write(&fallback, b"fake tool").unwrap();
-        let ctx = test_context(OxideConfig {
-            env: vec![(
-                "CUDA_TOOLKIT_PATH".to_string(),
-                root.to_string_lossy().into_owned(),
-            )],
-            ..OxideConfig::default()
-        });
-
-        let fallback_arg = fallback.to_string_lossy().into_owned();
-        assert_eq!(
-            find_cuda_toolkit_executable_with_env(&ctx, name, &[&fallback_arg], |_| None),
-            Some(under_toolkit),
-            "the configured toolkit root must win over a fallback path"
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    /// Negative: absent from PATH, from the configured root, and from the
-    /// fallbacks is still `None` -- the fix must not invent a path.
-    #[test]
-    fn a_missing_tool_is_still_missing() {
-        let root = unique_temp_dir("cargo_oxide_doctor_absent");
-        std::fs::create_dir_all(&root).unwrap();
-        let ctx = test_context(OxideConfig {
-            env: vec![(
-                "CUDA_TOOLKIT_PATH".to_string(),
-                root.to_string_lossy().into_owned(),
-            )],
-            ..OxideConfig::default()
-        });
-        assert_eq!(
-            find_cuda_toolkit_executable_with_env(
-                &ctx,
-                "cuda-oxide-test-absent-tool",
-                &["/nonexistent/bin/cuda-oxide-test-absent-tool"],
-                |_| None,
-            ),
-            None
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    /// The invariant a table alone cannot hold: no CUDA toolkit executable may
-    /// be probed with a bare `Command::new`, which is how `nvcc` and `cuda-gdb`
-    /// came to disagree with the commands they predict. Read out of the source
-    /// rather than from `DOCTOR_TOOLKIT_TOOLS`, so a tool left out of the table
-    /// is still caught.
-    #[test]
-    fn no_toolkit_executable_is_probed_by_bare_path() {
-        let source = include_str!("commands.rs");
-        for tool in [
-            "nvcc",
-            "cuda-gdb",
-            "compute-sanitizer",
-            "ptxas",
-            "nvlink",
-            "fatbinary",
-            "nvdisasm",
-            "cuobjdump",
-        ] {
-            let bare = format!("Command::new(\"{tool}\")");
-            assert!(
-                !source.contains(&bare),
-                "{tool} is probed with {bare}, bypassing the toolkit root; \
-                 route it through doctor_toolkit_tool / find_cuda_toolkit_executable"
-            );
-        }
-    }
-
-    /// `doctor` predicts whether `debug` will work, so both must consult one
-    /// list. A second inline copy is how they drifted apart.
-    #[test]
-    fn doctor_and_debug_share_one_cuda_gdb_fallback_list() {
-        let source = include_str!("commands.rs");
-        assert!(
-            source.matches("CUDA_GDB_FALLBACK_PATHS").count() >= 3,
-            "the shared list is not referenced by both call sites"
-        );
-        assert_eq!(
-            source.matches("\"/usr/local/cuda/bin/cuda-gdb\"").count(),
-            1,
-            "a second inline cuda-gdb path list has appeared"
-        );
-    }
-
-    #[test]
-    fn sanitizer_tool_lookup_uses_project_cuda_toolkit_root() {
-        let root = unique_temp_dir("cargo_oxide_sanitizer_tool");
-        let (ctx, tool) = toolkit_context_with_tool(&root, "cuda-oxide-test-sanitizer");
-
-        // `|_| None` stands in for an empty ambient environment. Reading the
-        // real one would let an exported CUDA_TOOLKIT_PATH/CUDA_HOME shadow the
-        // configured root this test asserts on.
-        assert_eq!(
-            find_cuda_toolkit_executable_with_env(&ctx, "cuda-oxide-test-sanitizer", &[], |_| None),
-            Some(tool)
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn doctor_compute_sanitizer_lookup_matches_sanitize_discovery() {
-        // Hermetic: a fake tool name keeps the user's real PATH (and any
-        // installed compute-sanitizer) out of the lookup, the injected empty
-        // environment keeps an exported toolkit root out of it, and the shared
-        // fallback const exercises the exact argument both `doctor` and
-        // `sanitize` pass. The configured toolkit root wins before any
-        // fallback path is consulted.
-        let root = unique_temp_dir("cargo_oxide_doctor_sanitizer");
-        let (ctx, tool) = toolkit_context_with_tool(&root, "cuda-oxide-test-doctor-sanitizer");
-
-        assert_eq!(
-            find_cuda_toolkit_executable_with_env(
-                &ctx,
-                "cuda-oxide-test-doctor-sanitizer",
-                COMPUTE_SANITIZER_FALLBACK_PATHS,
-                |_| None,
-            ),
-            Some(tool)
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn ambient_cuda_toolkit_path_shadows_the_project_configured_root() {
-        // The precedence the two lookups above have to be insulated from: an
-        // exported CUDA_TOOLKIT_PATH outranks `cuda-oxide.toml`, so a tool
-        // present only under the configured root is not found.
-        let root = unique_temp_dir("cargo_oxide_ambient_shadow");
-        let (ctx, _tool) = toolkit_context_with_tool(&root, "cuda-oxide-test-shadowed-sanitizer");
-        let ambient = unique_temp_dir("cargo_oxide_ambient_root");
-
-        assert_eq!(
-            find_cuda_toolkit_executable_with_env(
-                &ctx,
-                "cuda-oxide-test-shadowed-sanitizer",
-                &[],
-                |key| (key == "CUDA_TOOLKIT_PATH").then(|| ambient.to_string_lossy().into_owned()),
-            ),
-            None
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn test_passthrough_defers_profile_flags_to_cargo_and_keeps_invariants() {
-        let rustflags = build_encoded_rustflags_with_existing(
-            Path::new("/tmp/librustc_codegen_cuda.so"),
-            CargoPassthroughSubcommand::Test.codegen_profile(),
-            &[],
-            &["--cfg".to_string(), "device_test".to_string()],
-            None,
-            None,
-        );
-        let flags = decoded_rustflags(&rustflags);
-
-        assert_eq!(
-            flags,
-            [
-                "--cfg",
-                "device_test",
-                "-Zcodegen-backend=/tmp/librustc_codegen_cuda.so",
-                "-Zmir-enable-passes=-JumpThreading",
-                "-Zalways-encode-mir",
-                "-Csymbol-mangling-version=v0",
-            ]
-        );
-        assert!(!flags.iter().any(|flag| flag.starts_with("-Copt-level")));
-        assert!(
-            !flags
-                .iter()
-                .any(|flag| flag.starts_with("-Cdebug-assertions"))
-        );
-        assert!(!flags.iter().any(|flag| flag.starts_with("-Cdebuginfo")));
-
-        let ctx = test_context(OxideConfig::default());
-        let opts = CargoPassthroughOptions {
-            verbose: false,
-            emit_nvvm_ir: false,
-            arch: None,
-            features: None,
-            cargo_target_dir: None,
-            device_codegen_crate: None,
-            device_cfgs: &[],
-            no_fmad: false,
-            unchecked_indexing: false,
-            materialize_cubin: false,
-            device_debug: DeviceDebug::Off,
-        };
-        for cargo_args in [
-            vec!["--release".to_string()],
-            vec!["--profile".to_string(), "ci".to_string()],
-        ] {
-            let cmd = passthrough_command_for_test(
-                &ctx,
-                CargoPassthroughSubcommand::Test,
-                &opts,
-                &cargo_args,
-            )
-            .unwrap();
-            let mut expected = vec!["test".to_string()];
-            expected.extend(cargo_args);
-            assert_eq!(
-                cmd.get_args()
-                    .map(|arg| arg.to_string_lossy().into_owned())
-                    .collect::<Vec<_>>(),
-                expected
-            );
-        }
-    }
-
-    #[test]
-    fn build_passthrough_retains_release_profile_and_required_flags() {
-        let rustflags = build_encoded_rustflags_with_existing(
-            Path::new("/tmp/librustc_codegen_cuda.so"),
-            CargoPassthroughSubcommand::Build.codegen_profile(),
-            &[],
-            &[],
-            Some(
-                "-Lnative=/nix/store/cuda-cudart/lib\u{1f}-Copt-level=0\u{1f}-Zcodegen-backend=llvm",
-            ),
-            Some("-L native=/nix/store/cuda-cudart/lib"),
-        );
-        let flags = decoded_rustflags(&rustflags);
-
-        assert_eq!(flags[0], "-Lnative=/nix/store/cuda-cudart/lib");
-        assert!(flags.contains(&"-Copt-level=0"));
-        assert!(flags.contains(&"-Zcodegen-backend=llvm"));
-        assert_eq!(
-            &flags[flags.len() - 6..],
-            [
-                "-Zcodegen-backend=/tmp/librustc_codegen_cuda.so",
-                "-Copt-level=3",
-                "-Cdebug-assertions=off",
-                "-Zmir-enable-passes=-JumpThreading",
-                "-Zalways-encode-mir",
-                "-Csymbol-mangling-version=v0",
-            ]
-        );
-        assert!(!flags.contains(&"native=/nix/store/cuda-cudart/lib"));
-    }
-
-    #[test]
-    fn encoded_rustflags_preserve_configured_flag_boundaries_and_spaces() {
-        let rustflags = build_encoded_rustflags_with_existing(
-            Path::new("/tmp/backend path/librustc_codegen_cuda.so"),
-            CodegenProfilePolicy::ReleaseLike,
-            &["--cfg".to_string(), "model=\"alpha beta\"".to_string()],
-            &[],
-            None,
-            Some("-L native=/nix/store/cuda-cudart/lib"),
-        );
-        let flags = decoded_rustflags(&rustflags);
-
-        assert!(
-            flags
-                .windows(2)
-                .any(|pair| pair == ["--cfg", "model=\"alpha beta\""])
-        );
-        assert_eq!(&flags[2..4], ["-L", "native=/nix/store/cuda-cudart/lib"]);
-        assert_eq!(
-            flags[flags.len() - 6],
-            "-Zcodegen-backend=/tmp/backend path/librustc_codegen_cuda.so"
-        );
-    }
-
-    #[test]
-    fn encoded_rustflags_remove_legacy_global_codegen_fingerprints() {
-        let encoded = [
-            "--cfg",
-            "cuda_oxide_internal_codegen_env=\"inherited\"",
-            "--cfg=cuda_oxide_internal_materializer_provenance=\"inherited\"",
-            "--cfg",
-            "keep_inherited",
-        ]
-        .join(&ENCODED_RUSTFLAGS_SEPARATOR.to_string());
-        let rustflags = build_encoded_rustflags_with_existing(
-            Path::new("/tmp/librustc_codegen_cuda.so"),
-            CodegenProfilePolicy::ReleaseLike,
-            &[
-                "--cfg".to_string(),
-                "cuda_oxide_internal_codegen_env=\"configured\"".to_string(),
-                "--cfg".to_string(),
-                "keep_configured".to_string(),
-            ],
-            &[
-                "--cfg".to_string(),
-                "cuda_oxide_internal_materializer_provenance=\"explicit\"".to_string(),
-                "--cfg".to_string(),
-                "keep_explicit".to_string(),
-            ],
-            Some(&encoded),
-            None,
-        );
-        let flags = decoded_rustflags(&rustflags);
-
-        assert!(!flags.iter().any(|flag| {
-            flag.contains(LEGACY_CODEGEN_FINGERPRINT_CFG)
-                || flag.contains(LEGACY_MATERIALIZER_PROVENANCE_CFG)
-        }));
-        for retained in ["keep_configured", "keep_inherited", "keep_explicit"] {
-            assert!(flags.contains(&retained));
-        }
-    }
-
-    #[test]
-    fn debug_profile_retains_release_defaults_and_adds_debuginfo() {
-        let rustflags = build_encoded_rustflags_with_existing(
-            Path::new("/tmp/librustc_codegen_cuda.so"),
-            CodegenProfilePolicy::ReleaseLikeWithDebugInfo,
-            &[],
-            &[],
-            None,
-            Some(""),
-        );
-        let flags = decoded_rustflags(&rustflags);
-
-        assert!(flags.contains(&"-Copt-level=3"));
-        assert!(flags.contains(&"-Cdebug-assertions=off"));
-        assert!(flags.contains(&"-Cdebuginfo=2"));
-        assert!(flags.contains(&"-Zmir-enable-passes=-JumpThreading"));
-        assert!(flags.contains(&"-Zalways-encode-mir"));
-        assert!(flags.contains(&"-Csymbol-mangling-version=v0"));
-        assert!(!flags.contains(&""));
-    }
-
-    #[test]
-    fn project_config_parser_loads_backend_arch_flags_and_env() {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        let root = std::env::temp_dir().join(format!(
-            "cargo_oxide_config_test_{}_{}",
-            std::process::id(),
-            unique
-        ));
-        let cargo_dir = root.join(".cargo");
-        std::fs::create_dir_all(&cargo_dir).unwrap();
-        std::fs::write(
-            cargo_dir.join("cuda-oxide.toml"),
-            r#"
-backend = "../backend/librustc_codegen_cuda.so"
-default-arch = "sm_90"
-extra-rustflags = ["--cfg", "model=\"alpha beta\""]
-
-[env]
-MY_BUILD_FLAG = "configured"
-"#,
-        )
-        .unwrap();
-
-        let config = load_oxide_config(&root);
-        assert_eq!(
-            config.backend,
-            Some(cargo_dir.join("../backend/librustc_codegen_cuda.so"))
-        );
-        assert_eq!(config.default_arch.as_deref(), Some("sm_90"));
-        assert_eq!(config.extra_rustflags, ["--cfg", "model=\"alpha beta\""]);
-        assert_eq!(
-            config.env,
-            vec![("MY_BUILD_FLAG".to_string(), "configured".to_string())]
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn inspect_oxide_config_missing_is_informational() {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        let root = std::env::temp_dir().join(format!(
-            "cargo_oxide_config_missing_{}_{}",
-            std::process::id(),
-            unique
-        ));
-        std::fs::create_dir_all(&root).unwrap();
-        assert!(matches!(
-            inspect_oxide_config(&root),
-            OxideConfigInspection::Missing
-        ));
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn inspect_oxide_config_rejects_bad_toml_and_arch() {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        let root = std::env::temp_dir().join(format!(
-            "cargo_oxide_config_bad_{}_{}",
-            std::process::id(),
-            unique
-        ));
-        let cargo_dir = root.join(".cargo");
-        std::fs::create_dir_all(&cargo_dir).unwrap();
-        std::fs::write(cargo_dir.join("cuda-oxide.toml"), "default-arch = [\n").unwrap();
-        match inspect_oxide_config(&root) {
-            OxideConfigInspection::Invalid { errors, .. } => {
-                assert!(errors.iter().any(|e| e.contains("could not parse")));
-            }
-            other => panic!("expected Invalid, got {other:?}"),
-        }
-
-        std::fs::write(
-            cargo_dir.join("cuda-oxide.toml"),
-            "default-arch = \"sm_9x\"\n",
-        )
-        .unwrap();
-        match inspect_oxide_config(&root) {
-            OxideConfigInspection::Invalid { errors, .. } => {
-                assert!(errors.iter().any(|e| e.contains("default-arch")));
-            }
-            other => panic!("expected Invalid, got {other:?}"),
-        }
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    /// `default-arch` load-time validation must be exactly as permissive as
-    /// the consumers: `parse_nvvm_arch` (NVVM path) accepts `sm_XX`,
-    /// `compute_XX`, and bare `XX`, so none of those may fail the load.
-    /// Non-`sm_XX` spellings only earn an advisory warning.
-    #[test]
-    fn default_arch_validation_matches_the_real_arch_parser() {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        let root = std::env::temp_dir().join(format!(
-            "cargo_oxide_config_arch_{}_{}",
-            std::process::id(),
-            unique
-        ));
-        let cargo_dir = root.join(".cargo");
-        std::fs::create_dir_all(&cargo_dir).unwrap();
-        let config_path = cargo_dir.join("cuda-oxide.toml");
-
-        for accepted in ["sm_80", "sm_90a", "sm_100f", "sm_120"] {
-            std::fs::write(&config_path, format!("default-arch = \"{accepted}\"\n")).unwrap();
-            match inspect_oxide_config(&root) {
-                OxideConfigInspection::Valid { warnings, .. } => {
-                    assert!(warnings.is_empty(), "unexpected warnings for {accepted}");
-                }
-                other => panic!("expected {accepted} to be Valid, got {other:?}"),
-            }
-        }
-
-        // Spellings that genuinely work today (the NVVM path normalizes
-        // them) load fine but get the preferred-spelling advice.
-        for (works_with_warning, preferred) in [("compute_90", "sm_90"), ("90", "sm_90")] {
-            std::fs::write(
-                &config_path,
-                format!("default-arch = \"{works_with_warning}\"\n"),
-            )
-            .unwrap();
-            match inspect_oxide_config(&root) {
-                OxideConfigInspection::Valid { config, warnings } => {
-                    assert_eq!(config.default_arch.as_deref(), Some(works_with_warning));
-                    assert!(
-                        warnings.iter().any(|w| w.contains(preferred)),
-                        "expected a `{preferred}` spelling advisory for \
-                         {works_with_warning}, got {warnings:?}"
-                    );
-                }
-                other => panic!("expected {works_with_warning} to be Valid, got {other:?}"),
-            }
-        }
-
-        for rejected in ["sm_9", "sm_90x", "hopper"] {
-            std::fs::write(&config_path, format!("default-arch = \"{rejected}\"\n")).unwrap();
-            match inspect_oxide_config(&root) {
-                OxideConfigInspection::Invalid { errors, .. } => {
-                    assert!(
-                        errors.iter().any(|e| e.contains("default-arch")),
-                        "expected a default-arch error for {rejected}, got {errors:?}"
-                    );
-                }
-                other => panic!("expected {rejected} to be Invalid, got {other:?}"),
-            }
-        }
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn inspect_oxide_config_warns_on_forbidden_env_keys() {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        let root = std::env::temp_dir().join(format!(
-            "cargo_oxide_config_warn_{}_{}",
-            std::process::id(),
-            unique
-        ));
-        let cargo_dir = root.join(".cargo");
-        std::fs::create_dir_all(&cargo_dir).unwrap();
-        std::fs::write(
-            cargo_dir.join("cuda-oxide.toml"),
-            r#"
-default-arch = "sm_90a"
-
-[env]
-RUSTFLAGS = "-C opt-level=3"
-CARGO_ENCODED_RUSTFLAGS = "legacy"
-MY_OK = "1"
-"#,
-        )
-        .unwrap();
-
-        match inspect_oxide_config(&root) {
-            OxideConfigInspection::Valid { config, warnings } => {
-                assert_eq!(config.default_arch.as_deref(), Some("sm_90a"));
-                assert!(
-                    warnings
-                        .iter()
-                        .any(|w| w.contains("RUSTFLAGS") && w.contains("ignored"))
-                );
-                assert!(
-                    warnings
-                        .iter()
-                        .any(|w| w.contains("CARGO_ENCODED_RUSTFLAGS") && w.contains("ignored"))
-                );
-            }
-            other => panic!("expected Valid with warnings, got {other:?}"),
-        }
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn doctor_survives_malformed_config_and_reports_the_failed_check() {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        let root = std::env::temp_dir().join(format!(
-            "cargo_oxide_doctor_config_bad_{}_{}",
-            std::process::id(),
-            unique
-        ));
-        let cargo_dir = root.join(".cargo");
-        std::fs::create_dir_all(&cargo_dir).unwrap();
-        std::fs::write(cargo_dir.join("cuda-oxide.toml"), "default-arch = [\n").unwrap();
-
-        // Passive context resolution must not exit: it degrades to defaults
-        // so the doctor scan can start at all.
-        assert_eq!(load_oxide_config_lenient(&root), OxideConfig::default());
-
-        // Doctor's own check re-inspects the file and fails.
-        let check = check_oxide_config(&root);
-        assert!(check.failed);
-        assert!(check.headline.starts_with('✗'), "{}", check.headline);
-        assert!(
-            check
-                .details
-                .iter()
-                .any(|line| line.contains("could not parse")),
-            "{:?}",
-            check.details
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn doctor_reports_env_rustflags_warning_without_failing_the_check() {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        let root = std::env::temp_dir().join(format!(
-            "cargo_oxide_doctor_config_warn_{}_{}",
-            std::process::id(),
-            unique
-        ));
-        let cargo_dir = root.join(".cargo");
-        std::fs::create_dir_all(&cargo_dir).unwrap();
-        std::fs::write(
-            cargo_dir.join("cuda-oxide.toml"),
-            "default-arch = \"sm_90a\"\n\n[env]\nRUSTFLAGS = \"-C opt-level=3\"\n",
-        )
-        .unwrap();
-
-        let check = check_oxide_config(&root);
-        assert!(!check.failed);
-        assert!(check.headline.contains("default-arch = sm_90a"));
-        assert!(
-            check
-                .details
-                .iter()
-                .any(|line| line.contains("RUSTFLAGS") && line.contains("ignored")),
-            "{:?}",
-            check.details
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn doctor_reports_missing_config_as_informational() {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        let root = std::env::temp_dir().join(format!(
-            "cargo_oxide_doctor_config_missing_{}_{}",
-            std::process::id(),
-            unique
-        ));
-        std::fs::create_dir_all(&root).unwrap();
-
-        let check = check_oxide_config(&root);
-        assert!(!check.failed);
-        assert_eq!(check.headline, "- not present (using defaults)");
-        assert!(check.details.is_empty());
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn passthrough_command_preserves_argv_and_cli_overrides_config_defaults() {
-        let config = OxideConfig {
-            extra_rustflags: vec!["--cfg".to_string(), "from_config".to_string()],
-            env: vec![
-                ("CARGO_TARGET_DIR".to_string(), "config-target".to_string()),
-                (
-                    "CUDA_OXIDE_DEVICE_CODEGEN_CRATE".to_string(),
-                    "config_owner".to_string(),
-                ),
-                ("CUDA_OXIDE_VERBOSE".to_string(), "configured".to_string()),
-            ],
-            ..OxideConfig::default()
-        };
-        let ctx = test_context(config);
-        let device_cfgs = vec!["model=\"alpha beta\"".to_string()];
-        let opts = CargoPassthroughOptions {
-            verbose: true,
-            emit_nvvm_ir: false,
-            arch: Some("sm_90"),
-            features: Some("wrapper_feature"),
-            cargo_target_dir: Some(Path::new("cli-target")),
-            device_codegen_crate: Some("gpu-kernels, math_gpu"),
-            device_cfgs: &device_cfgs,
-            no_fmad: false,
-            unchecked_indexing: false,
-            materialize_cubin: false,
-            device_debug: DeviceDebug::Off,
-        };
-        let cargo_args = vec![
-            "-p".to_string(),
-            "gpu-app".to_string(),
-            "--".to_string(),
-            "--nocapture".to_string(),
-        ];
-
-        let cmd = passthrough_command_for_test(
-            &ctx,
-            CargoPassthroughSubcommand::Test,
-            &opts,
-            &cargo_args,
-        )
-        .unwrap();
-        assert_eq!(
-            cmd.get_args()
-                .map(|arg| arg.to_string_lossy().into_owned())
-                .collect::<Vec<_>>(),
-            [
-                "test",
-                "--features",
-                "wrapper_feature",
-                "-p",
-                "gpu-app",
-                "--",
-                "--nocapture",
-            ]
-        );
-        assert_eq!(
-            command_env(&cmd, "CARGO_TARGET_DIR").as_deref(),
-            Some("cli-target")
-        );
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_DEVICE_CODEGEN_CRATE").as_deref(),
-            Some("gpu_kernels,math_gpu")
-        );
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_TARGET").as_deref(),
-            Some("sm_90")
-        );
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_VERBOSE").as_deref(),
-            Some("1")
-        );
-
-        let encoded = command_env(&cmd, "CARGO_ENCODED_RUSTFLAGS").unwrap();
-        let flags = decoded_rustflags(&encoded);
-        assert!(
-            flags
-                .windows(2)
-                .any(|pair| pair == ["--cfg", "from_config"])
-        );
-        assert!(
-            flags
-                .windows(2)
-                .any(|pair| pair == ["--cfg", "model=\"alpha beta\""])
-        );
-        assert!(has_backend_identity_cfg(&flags));
-        assert!(!flags.iter().any(|flag| {
-            flag.contains("cuda_oxide_internal_codegen_env")
-                || flag.contains("cuda_oxide_internal_materializer_provenance")
-        }));
-        assert!(is_sha256(
-            &command_env(&cmd, CODEGEN_FINGERPRINT_ENV).unwrap()
-        ));
-        assert!(
-            cmd.get_envs()
-                .any(|(key, value)| key == OsStr::new("RUSTFLAGS") && value.is_none())
-        );
-    }
-
-    #[test]
-    fn passthrough_command_accepts_empty_cargo_args() {
-        let ctx = test_context(OxideConfig::default());
-        let opts = CargoPassthroughOptions {
-            verbose: false,
-            emit_nvvm_ir: false,
-            arch: None,
-            features: None,
-            cargo_target_dir: None,
-            device_codegen_crate: None,
-            device_cfgs: &[],
-            no_fmad: false,
-            unchecked_indexing: false,
-            materialize_cubin: false,
-            device_debug: DeviceDebug::Off,
-        };
-
-        let cmd = passthrough_command_for_test(&ctx, CargoPassthroughSubcommand::Test, &opts, &[])
-            .unwrap();
-        assert_eq!(
-            cmd.get_args()
-                .map(|arg| arg.to_string_lossy().into_owned())
-                .collect::<Vec<_>>(),
-            ["test"]
-        );
-    }
-
-    #[test]
-    fn architecture_and_output_mode_do_not_change_global_rustflags() {
-        let ctx = test_context(OxideConfig::default());
-        let base = CargoPassthroughOptions {
-            verbose: false,
-            emit_nvvm_ir: false,
-            arch: Some("sm_80"),
-            features: None,
-            cargo_target_dir: None,
-            device_codegen_crate: None,
-            device_cfgs: &[],
-            no_fmad: false,
-            unchecked_indexing: false,
-            materialize_cubin: false,
-            device_debug: DeviceDebug::Off,
-        };
-        let base_cmd =
-            passthrough_command_for_test(&ctx, CargoPassthroughSubcommand::Build, &base, &[])
-                .unwrap();
-        let different_mode = CargoPassthroughOptions {
-            emit_nvvm_ir: true,
-            arch: Some("sm_90"),
-            ..base
-        };
-        let different_cmd = passthrough_command_for_test(
-            &ctx,
-            CargoPassthroughSubcommand::Build,
-            &different_mode,
-            &[],
-        )
-        .unwrap();
-
-        assert_eq!(
-            command_env(&base_cmd, "CARGO_ENCODED_RUSTFLAGS"),
-            command_env(&different_cmd, "CARGO_ENCODED_RUSTFLAGS"),
-            "architecture/output switches must not invalidate every dependency"
-        );
-        assert_ne!(
-            command_env(&base_cmd, CODEGEN_FINGERPRINT_ENV),
-            command_env(&different_cmd, CODEGEN_FINGERPRINT_ENV),
-            "device owners still need a distinct Cargo identity"
-        );
-    }
-
-    #[test]
-    fn codegen_mode_changes_rebuild_only_the_tracked_device_owner() {
-        let root = unique_temp_dir("cargo_oxide_scoped_codegen_fingerprint");
-        let target = root.join("target");
-        for path in [
-            root.join("shared-dep/src"),
-            root.join("tracked-macro/src"),
-            root.join("device-owner/src"),
-            root.join("device-consumer/src"),
-        ] {
-            std::fs::create_dir_all(path).unwrap();
-        }
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"[workspace]
-resolver = "3"
-members = ["shared-dep", "tracked-macro", "device-owner", "device-consumer"]
-"#,
-        )
-        .unwrap();
-        std::fs::write(
-            root.join("shared-dep/Cargo.toml"),
-            r#"[package]
-name = "shared-dep"
-version = "0.0.0"
-edition = "2024"
-"#,
-        )
-        .unwrap();
-        std::fs::write(
-            root.join("shared-dep/src/lib.rs"),
-            "pub fn shared_value() -> u32 { 42 }\n",
-        )
-        .unwrap();
-        std::fs::write(
-            root.join("tracked-macro/Cargo.toml"),
-            r#"[package]
-name = "tracked-macro"
-version = "0.0.0"
-edition = "2024"
-
-[lib]
-proc-macro = true
-"#,
-        )
-        .unwrap();
-        std::fs::write(
-            root.join("tracked-macro/src/lib.rs"),
-            format!(
-                r#"#![feature(proc_macro_tracked_env)]
-extern crate proc_macro;
-
-#[proc_macro]
-pub fn track_codegen(_input: proc_macro::TokenStream) -> proc_macro::TokenStream {{
-    let _ = proc_macro::tracked::env_var({CODEGEN_FINGERPRINT_ENV:?});
-    let _ = proc_macro::tracked::env_var({MATERIALIZE_ENV:?});
-    let _ = proc_macro::tracked::env_var({EXPECTED_PROVENANCE_ENV:?});
-    "()".parse().unwrap()
-}}
-"#
-            ),
-        )
-        .unwrap();
-        std::fs::write(
-            root.join("device-owner/Cargo.toml"),
-            r#"[package]
-name = "device-owner"
-version = "0.0.0"
-edition = "2024"
-
-[dependencies]
-shared-dep = { path = "../shared-dep" }
-tracked-macro = { path = "../tracked-macro" }
-"#,
-        )
-        .unwrap();
-        std::fs::write(
-            root.join("device-owner/src/lib.rs"),
-            "const _: () = tracked_macro::track_codegen!();\npub fn device_value() -> u32 { shared_dep::shared_value() }\n",
-        )
-        .unwrap();
-        std::fs::write(
-            root.join("device-consumer/Cargo.toml"),
-            r#"[package]
-name = "device-consumer"
-version = "0.0.0"
-edition = "2024"
-
-[dependencies]
-device-owner = { path = "../device-owner" }
-"#,
-        )
-        .unwrap();
-        std::fs::write(
-            root.join("device-consumer/src/main.rs"),
-            "fn main() { assert_eq!(device_owner::device_value(), 42); }\n",
-        )
-        .unwrap();
-
-        let ctx = Context {
-            workspace_root: root.clone(),
-            codegen_crate: root.join("unused-codegen-source"),
-            examples_dir: root.join("unused-examples"),
-            backend_so: PathBuf::from("llvm"),
-            is_workspace: false,
-            config: OxideConfig::default(),
-        };
-        let base = CargoPassthroughOptions {
-            verbose: false,
-            emit_nvvm_ir: false,
-            arch: Some("sm_80"),
-            features: None,
-            cargo_target_dir: Some(&target),
-            device_codegen_crate: None,
-            device_cfgs: &[],
-            no_fmad: false,
-            unchecked_indexing: false,
-            materialize_cubin: false,
-            device_debug: DeviceDebug::Off,
-        };
-
-        let cold = cargo_artifact_freshness(&ctx, &base, None);
-        assert_eq!(cold.get("shared_dep"), Some(&false));
-        assert_eq!(cold.get("tracked_macro"), Some(&false));
-        assert_eq!(cold.get("device_owner"), Some(&false));
-        assert_eq!(cold.get("device-consumer"), Some(&false));
-
-        let warm = cargo_artifact_freshness(&ctx, &base, None);
-        assert_eq!(warm.get("shared_dep"), Some(&true));
-        assert_eq!(warm.get("tracked_macro"), Some(&true));
-        assert_eq!(warm.get("device_owner"), Some(&true));
-        assert_eq!(warm.get("device-consumer"), Some(&true));
-
-        let different_arch = CargoPassthroughOptions {
-            arch: Some("sm_90"),
-            ..base
-        };
-        let arch_switch = cargo_artifact_freshness(&ctx, &different_arch, None);
-        assert_eq!(arch_switch.get("shared_dep"), Some(&true));
-        assert_eq!(arch_switch.get("tracked_macro"), Some(&true));
-        assert_eq!(arch_switch.get("device_owner"), Some(&false));
-        assert_eq!(arch_switch.get("device-consumer"), Some(&false));
-
-        let different_output = CargoPassthroughOptions {
-            emit_nvvm_ir: true,
-            ..different_arch
-        };
-        let output_switch = cargo_artifact_freshness(&ctx, &different_output, None);
-        assert_eq!(output_switch.get("shared_dep"), Some(&true));
-        assert_eq!(output_switch.get("tracked_macro"), Some(&true));
-        assert_eq!(output_switch.get("device_owner"), Some(&false));
-        assert_eq!(output_switch.get("device-consumer"), Some(&false));
-
-        let repeated_output = cargo_artifact_freshness(&ctx, &different_output, None);
-        assert_eq!(repeated_output.get("shared_dep"), Some(&true));
-        assert_eq!(repeated_output.get("tracked_macro"), Some(&true));
-        assert_eq!(repeated_output.get("device_owner"), Some(&true));
-        assert_eq!(repeated_output.get("device-consumer"), Some(&true));
-
-        let provenance_switch = cargo_artifact_freshness(
-            &ctx,
-            &different_output,
-            Some("11d91fbe164094f6242d44103d0fb01968b96c6d8f48f124eac8fa73a307a657"),
-        );
-        assert_eq!(provenance_switch.get("shared_dep"), Some(&true));
-        assert_eq!(provenance_switch.get("tracked_macro"), Some(&true));
-        assert_eq!(provenance_switch.get("device_owner"), Some(&false));
-        assert_eq!(provenance_switch.get("device-consumer"), Some(&false));
-
-        let changed_provenance = cargo_artifact_freshness(
-            &ctx,
-            &different_output,
-            Some("5b11618c2e44027877d0cd4d0cfd10afed5ef262876791e483ec58f4c5569139"),
-        );
-        assert_eq!(changed_provenance.get("shared_dep"), Some(&true));
-        assert_eq!(changed_provenance.get("tracked_macro"), Some(&true));
-        assert_eq!(changed_provenance.get("device_owner"), Some(&false));
-        assert_eq!(changed_provenance.get("device-consumer"), Some(&false));
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn owner_filter_resolution_is_normalized_and_has_explicit_precedence() {
-        assert_eq!(
-            resolve_device_codegen_crates(None, None, Some("gpu-kernels, math_gpu"))
-                .unwrap()
-                .as_deref(),
-            Some("gpu_kernels,math_gpu"),
-        );
-        assert_eq!(
-            resolve_device_codegen_crates(None, Some("parent-owner"), Some("config-owner"))
-                .unwrap()
-                .as_deref(),
-            Some("parent_owner"),
-        );
-        assert!(
-            resolve_device_codegen_crates(Some(""), Some("parent-owner"), Some("config-owner"))
-                .is_err()
-        );
-    }
-
-    #[test]
-    fn passthrough_fingerprint_tracks_output_affecting_settings() {
-        let ctx = test_context(OxideConfig::default());
-        let base = CargoPassthroughOptions {
-            verbose: false,
-            emit_nvvm_ir: false,
-            arch: Some("sm_80"),
-            features: None,
-            cargo_target_dir: None,
-            device_codegen_crate: None,
-            device_cfgs: &[],
-            no_fmad: false,
-            unchecked_indexing: false,
-            materialize_cubin: false,
-            device_debug: DeviceDebug::Off,
-        };
-        let inherited_env = BTreeMap::new();
-        let base_hash = passthrough_codegen_fingerprint_with_env(
-            &ctx,
-            &base,
-            None,
-            Some("sm_80"),
-            &MaterializationMode::default(),
-            &inherited_env,
-        );
-
-        let arch = CargoPassthroughOptions {
-            arch: Some("sm_90"),
-            ..base
-        };
-        let emit = CargoPassthroughOptions {
-            emit_nvvm_ir: true,
-            ..base
-        };
-        let no_fmad = CargoPassthroughOptions {
-            no_fmad: true,
-            ..base
-        };
-        let unchecked_indexing = CargoPassthroughOptions {
-            unchecked_indexing: true,
-            ..base
-        };
-        let configured_ptx = test_context(OxideConfig {
-            env: vec![(
-                "CUDA_OXIDE_PTX_DIR".to_string(),
-                "configured-ptx".to_string(),
-            )],
-            ..OxideConfig::default()
-        });
-
-        assert_ne!(
-            base_hash,
-            passthrough_codegen_fingerprint_with_env(
-                &ctx,
-                &arch,
-                None,
-                Some("sm_90"),
-                &MaterializationMode::default(),
-                &inherited_env,
-            )
-        );
-        assert_ne!(
-            base_hash,
-            passthrough_codegen_fingerprint_with_env(
-                &ctx,
-                &emit,
-                None,
-                Some("sm_80"),
-                &MaterializationMode::default(),
-                &inherited_env,
-            )
-        );
-        assert_ne!(
-            base_hash,
-            passthrough_codegen_fingerprint_with_env(
-                &ctx,
-                &no_fmad,
-                None,
-                Some("sm_80"),
-                &MaterializationMode::default(),
-                &inherited_env,
-            )
-        );
-        assert_ne!(
-            base_hash,
-            passthrough_codegen_fingerprint_with_env(
-                &ctx,
-                &unchecked_indexing,
-                None,
-                Some("sm_80"),
-                &MaterializationMode::default(),
-                &inherited_env,
-            )
-        );
-        assert_ne!(
-            base_hash,
-            passthrough_codegen_fingerprint_with_env(
-                &ctx,
-                &base,
-                Some("gpu_kernel"),
-                Some("sm_80"),
-                &MaterializationMode::default(),
-                &inherited_env,
-            )
-        );
-        assert_ne!(
-            base_hash,
-            passthrough_codegen_fingerprint_with_env(
-                &configured_ptx,
-                &base,
-                None,
-                Some("sm_80"),
-                &MaterializationMode::default(),
-                &inherited_env,
-            )
-        );
-        let materialized = MaterializationMode {
-            prepared: Some(PreparedMaterialization {
-                provenance_sha256_hex: "ab".repeat(32),
-                tool_identity_handshake_json: "{\"version\":1}".to_string(),
-            }),
-        };
-        assert_ne!(
-            base_hash,
-            passthrough_codegen_fingerprint_with_env(
-                &ctx,
-                &base,
-                None,
-                Some("sm_80"),
-                &materialized,
-                &inherited_env,
-            ),
-            "exact CUDA-tool provenance must change Cargo's rustc fingerprint"
-        );
-    }
-
-    #[test]
-    fn passthrough_fingerprint_tracks_non_unicode_presence_switch_bytes() {
-        let ctx = test_context(OxideConfig::default());
-        let opts = CargoPassthroughOptions {
-            verbose: false,
-            emit_nvvm_ir: false,
-            arch: Some("sm_80"),
-            features: None,
-            cargo_target_dir: None,
-            device_codegen_crate: None,
-            device_cfgs: &[],
-            no_fmad: false,
-            unchecked_indexing: false,
-            materialize_cubin: false,
-            device_debug: DeviceDebug::Off,
-        };
-        let fingerprint = |inherited_env: &BTreeMap<String, Vec<u8>>| {
-            passthrough_codegen_fingerprint_with_env(
-                &ctx,
-                &opts,
-                None,
-                Some("sm_80"),
-                &MaterializationMode::default(),
-                inherited_env,
-            )
-        };
-        let absent = BTreeMap::new();
-        let first = BTreeMap::from([("CUDA_OXIDE_NO_FMA".to_string(), vec![0xff])]);
-        let second = BTreeMap::from([("CUDA_OXIDE_NO_FMA".to_string(), vec![0xfe])]);
-
-        assert_ne!(fingerprint(&absent), fingerprint(&first));
-        assert_ne!(fingerprint(&first), fingerprint(&second));
-    }
-
-    #[test]
-    fn global_backend_identity_tracks_rebuild_at_same_path() {
-        let unique = std::time::SystemTime::now()
-            .duration_since(std::time::UNIX_EPOCH)
-            .expect("system time before unix epoch")
-            .as_nanos();
-        let root = std::env::temp_dir().join(format!(
-            "cargo_oxide_backend_fingerprint_{}_{}",
-            std::process::id(),
-            unique
-        ));
-        std::fs::create_dir_all(&root).unwrap();
-        let backend = root.join("librustc_codegen_cuda.so");
-        std::fs::write(&backend, b"first").unwrap();
-        let original = std::fs::metadata(&backend).unwrap();
-        let original_modified = original.modified().unwrap();
-
-        let mut ctx = test_context(OxideConfig::default());
-        ctx.backend_so = backend.clone();
-        let fingerprint = "42".repeat(32);
-        let mut before_cmd = Command::new("cargo");
-        apply_codegen_configuration(
-            &mut before_cmd,
-            &ctx,
-            CodegenProfilePolicy::ReleaseLike,
-            &[],
-            &fingerprint,
-        )
-        .unwrap();
-        let before = command_env(&before_cmd, "CARGO_ENCODED_RUSTFLAGS").unwrap();
-        // Preserve the weak metadata identity that used to be fingerprinted:
-        // only the bytes differ.
-        std::fs::write(&backend, b"other").unwrap();
-        std::fs::File::options()
-            .write(true)
-            .open(&backend)
-            .unwrap()
-            .set_times(std::fs::FileTimes::new().set_modified(original_modified))
-            .unwrap();
-        let replacement = std::fs::metadata(&backend).unwrap();
-        assert_eq!(replacement.len(), original.len());
-        assert_eq!(replacement.modified().unwrap(), original_modified);
-        let mut after_cmd = Command::new("cargo");
-        apply_codegen_configuration(
-            &mut after_cmd,
-            &ctx,
-            CodegenProfilePolicy::ReleaseLike,
-            &[],
-            &fingerprint,
-        )
-        .unwrap();
-        let after = command_env(&after_cmd, "CARGO_ENCODED_RUSTFLAGS").unwrap();
-
-        assert_ne!(before, after);
-        assert_eq!(
-            command_env(&before_cmd, CODEGEN_FINGERPRINT_ENV),
-            command_env(&after_cmd, CODEGEN_FINGERPRINT_ENV)
-        );
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn owner_filter_rejects_empty_or_invalid_entries() {
-        assert_eq!(
-            normalize_device_codegen_crates("gpu-kernels, math_gpu").unwrap(),
-            "gpu_kernels,math_gpu"
-        );
-        assert!(normalize_device_codegen_crates("").is_err());
-        assert!(normalize_device_codegen_crates("   ").is_err());
-        assert!(normalize_device_codegen_crates("gpu,").is_err());
-        assert!(normalize_device_codegen_crates("gpu,not a crate").is_err());
-    }
-
-    #[test]
-    fn internal_ptx_directory_overrides_project_env_default() {
-        let ctx = test_context(OxideConfig {
-            env: vec![(
-                "CUDA_OXIDE_PTX_DIR".to_string(),
-                "configured-ptx".to_string(),
-            )],
-            ..OxideConfig::default()
-        });
-        let mut cmd = Command::new("cargo");
-        apply_common_codegen_env(&mut cmd, &ctx, false, false, false, DeviceDebug::Off);
-        cmd.env("CUDA_OXIDE_PTX_DIR", "internal-ptx");
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_PTX_DIR").as_deref(),
-            Some("internal-ptx")
-        );
-    }
-
-    #[test]
-    fn nvvm_arch_normalizes_all_accepted_forms() {
-        // `sm_XX` is the form `--arch` and the rest of cargo-oxide use.
-        assert_eq!(parse_nvvm_arch("sm_120").unwrap().compute(), "compute_120");
-        assert_eq!(parse_nvvm_arch("sm_90").unwrap().compute(), "compute_90");
-        // `compute_XX` passes through unchanged.
-        assert_eq!(
-            parse_nvvm_arch("compute_100").unwrap().compute(),
-            "compute_100"
-        );
-        // A bare capability is accepted too.
-        assert_eq!(parse_nvvm_arch("120").unwrap().compute(), "compute_120");
-        assert!(parse_nvvm_arch("sm_90x").is_err());
-    }
-
-    #[test]
-    fn emit_ltoir_preserves_fma_and_debug_policy_for_libnvvm() {
-        let arch = parse_nvvm_arch("sm_90").unwrap();
-        for (artifact_debug, finalizer_debug) in [
-            (
-                oxide_artifacts::ArtifactDebugPolicy::None,
-                cuda_artifact_finalizer::DebugPolicy::None,
-            ),
-            (
-                oxide_artifacts::ArtifactDebugPolicy::LineTables,
-                cuda_artifact_finalizer::DebugPolicy::LineTables,
-            ),
-            (
-                oxide_artifacts::ArtifactDebugPolicy::Full,
-                cuda_artifact_finalizer::DebugPolicy::Full,
-            ),
-        ] {
-            let artifact_options = oxide_artifacts::ArtifactCompileOptions::new()
-                .with_fma_contraction(false)
-                .with_debug_policy(artifact_debug);
-            let finalizer_options = finalization_options_from_artifact(&arch, artifact_options);
-
-            assert_eq!(finalizer_options.target(), &arch);
-            assert!(!finalizer_options.allow_fma_contraction());
-            assert_eq!(finalizer_options.debug_policy(), finalizer_debug);
-        }
-    }
-
-    #[test]
-    fn apply_output_mode_sets_target_for_arch_override() {
-        let mut cmd = Command::new("cargo");
-
-        apply_output_mode(
-            &mut cmd,
-            false,
-            Some("sm_120"),
-            &MaterializationMode::default(),
-        );
-
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_TARGET").as_deref(),
-            Some("sm_120")
-        );
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR"), None);
-    }
-
-    #[test]
-    fn apply_output_mode_sets_nvvm_ir_flag_and_target() {
-        let mut cmd = Command::new("cargo");
-
-        apply_output_mode(
-            &mut cmd,
-            true,
-            Some("sm_100a"),
-            &MaterializationMode::default(),
-        );
-
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_TARGET").as_deref(),
-            Some("sm_100a")
-        );
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR").as_deref(),
-            Some("1")
-        );
-    }
-
-    #[test]
-    fn materialization_forces_nvvm_ir_and_exact_provenance_handshake() {
-        let mut cmd = Command::new("cargo");
-        let materialization = MaterializationMode {
-            prepared: Some(PreparedMaterialization {
-                provenance_sha256_hex: "42".repeat(32),
-                tool_identity_handshake_json: "{\"version\":1}".to_string(),
-            }),
-        };
-
-        apply_output_mode(&mut cmd, false, Some("sm_90"), &materialization);
-
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR").as_deref(),
-            Some("1")
-        );
-        assert_eq!(command_env(&cmd, MATERIALIZE_ENV).as_deref(), Some("1"));
-        assert_eq!(
-            command_env(&cmd, MATERIALIZER_HANDSHAKE_ENV).as_deref(),
-            Some("{\"version\":1}")
-        );
-        assert_eq!(
-            command_env(&cmd, EXPECTED_PROVENANCE_ENV).as_deref(),
-            Some("4242424242424242424242424242424242424242424242424242424242424242")
-        );
-    }
-
-    #[test]
-    fn apply_output_mode_leaves_auto_detect_ptx_unset() {
-        let mut cmd = Command::new("cargo");
-
-        apply_output_mode(&mut cmd, false, None, &MaterializationMode::default());
-
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_TARGET"), None);
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR"), None);
-    }
-
-    #[test]
-    fn apply_device_arch_hint_sets_hint_when_no_explicit_arch() {
-        let mut cmd = Command::new("cargo");
-
-        apply_device_arch_hint(&mut cmd, None, Some("sm_120a"));
-
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_DEVICE_ARCH").as_deref(),
-            Some("sm_120a")
-        );
-        // The hint must never masquerade as the hard override.
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_TARGET"), None);
-    }
-
-    #[test]
-    fn apply_device_arch_hint_skipped_when_arch_explicit() {
-        // An explicit --arch already went to CUDA_OXIDE_TARGET; don't also
-        // emit a competing device hint.
-        let mut cmd = Command::new("cargo");
-
-        apply_device_arch_hint(&mut cmd, Some("sm_90"), Some("sm_120a"));
-
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_DEVICE_ARCH"), None);
-    }
-
-    #[test]
-    fn apply_device_arch_hint_noop_without_detection() {
-        let mut cmd = Command::new("cargo");
-
-        apply_device_arch_hint(&mut cmd, None, None);
-
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_DEVICE_ARCH"), None);
-    }
-
-    #[test]
-    fn debug_output_mode_forwards_detected_gpu_hint() {
-        let mut cmd = Command::new("cargo");
-
-        apply_output_mode(&mut cmd, false, None, &MaterializationMode::default());
-        apply_device_arch_hint(&mut cmd, None, Some("sm_120a"));
-
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_DEVICE_ARCH").as_deref(),
-            Some("sm_120a")
-        );
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_TARGET"), None);
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR"), None);
-    }
-
-    #[test]
-    fn debug_output_mode_honors_explicit_arch_override() {
-        let mut cmd = Command::new("cargo");
-
-        apply_output_mode(
-            &mut cmd,
-            false,
-            Some("sm_90"),
-            &MaterializationMode::default(),
-        );
-        apply_device_arch_hint(&mut cmd, Some("sm_90"), Some("sm_120a"));
-
-        assert_eq!(
-            command_env(&cmd, "CUDA_OXIDE_TARGET").as_deref(),
-            Some("sm_90")
-        );
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_DEVICE_ARCH"), None);
-        assert_eq!(command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR"), None);
-    }
-
-    #[test]
-    fn format_sm_arch_uses_cuda_target_spelling() {
-        // cc < 9.0 — no arch-specific target exists in the PTX ISA, so we
-        // emit the plain `sm_XY` form. Confirms we do not produce false
-        // positives like `sm_75a` / `sm_80a` / `sm_89a`.
-        assert_eq!(format_sm_arch((7, 0)), "sm_70");
-        assert_eq!(format_sm_arch((7, 5)), "sm_75");
-        assert_eq!(format_sm_arch((8, 0)), "sm_80");
-        assert_eq!(format_sm_arch((8, 6)), "sm_86");
-        assert_eq!(format_sm_arch((8, 9)), "sm_89");
-
-        // cc ≥ 9.0 — every chip that reports this CC is an arch-specific
-        // (`a`) variant. Auto-detect emits the `a` form so the codegen
-        // backend can lower WGMMA / tcgen05 / TMA-multicast / cta_group
-        // intrinsics without falling through to a plain target that ptxas
-        // would reject. Confirms we do not produce false negatives.
-        assert_eq!(format_sm_arch((9, 0)), "sm_90a"); // Hopper (H100/H200)
-        assert_eq!(format_sm_arch((10, 0)), "sm_100a"); // Blackwell DC
-        assert_eq!(format_sm_arch((10, 1)), "sm_101a");
-        assert_eq!(format_sm_arch((10, 3)), "sm_103a");
-        assert_eq!(format_sm_arch((12, 0)), "sm_120a"); // consumer Blackwell
-    }
-
-    #[test]
-    fn parse_compute_cap_accepts_real_nvidia_smi_output() {
-        assert_eq!(parse_compute_cap("12.0\n"), Some((12, 0)));
-        assert_eq!(parse_compute_cap("7.5\n"), Some((7, 5)));
-        assert_eq!(parse_compute_cap("10.3"), Some((10, 3)));
-        // End-to-end with format_sm_arch: the values the backend sees.
-        assert_eq!(
-            format_sm_arch(parse_compute_cap("12.0\n").unwrap()),
-            "sm_120a"
-        );
-        assert_eq!(format_sm_arch(parse_compute_cap("7.5\n").unwrap()), "sm_75");
-    }
-
-    #[test]
-    fn parse_compute_cap_takes_first_gpu_on_multi_gpu_machines() {
-        assert_eq!(parse_compute_cap("9.0\n12.0\n"), Some((9, 0)));
-    }
-
-    #[test]
-    fn parse_gpu_name_cap_and_driver_splits_on_last_two_commas() {
-        assert_eq!(
-            parse_gpu_name_cap_and_driver("NVIDIA GeForce RTX 5090, 12.0, 580.65.06\n"),
-            Some((
-                "NVIDIA GeForce RTX 5090".to_string(),
-                (12, 0),
-                "580.65.06".to_string()
-            ))
-        );
-        // Failure banner: no comma-separated cc/driver fields.
-        assert_eq!(
-            parse_gpu_name_cap_and_driver("NVIDIA-SMI has failed.\n"),
-            None
-        );
-        assert_eq!(parse_gpu_name_cap_and_driver(""), None);
-    }
-
-    #[test]
-    fn cuda_toolkit_root_prefers_toolkit_path_then_home_then_default() {
-        let toolkit_and_home = cuda_toolkit_root(|var| match var {
-            "CUDA_TOOLKIT_PATH" => Some("/cuda/toolkit".to_string()),
-            "CUDA_HOME" => Some("/cuda/home".to_string()),
-            _ => None,
-        });
-        assert_eq!(toolkit_and_home, "/cuda/toolkit");
-
-        let home_only =
-            cuda_toolkit_root(|var| (var == "CUDA_HOME").then(|| "/cuda/home".to_string()));
-        assert_eq!(home_only, "/cuda/home");
-
-        let empty_toolkit_path = cuda_toolkit_root(|var| match var {
-            "CUDA_TOOLKIT_PATH" => Some("  ".to_string()),
-            "CUDA_HOME" => Some("/cuda/home".to_string()),
-            _ => None,
-        });
-        assert_eq!(empty_toolkit_path, "/cuda/home");
-
-        assert_eq!(cuda_toolkit_root(|_| None), "/usr/local/cuda");
-    }
-
-    #[test]
-    fn cuda_header_candidates_cover_standard_and_redistributable_layouts() {
-        // Standard install layout first, then the matching targets/ layout.
-        assert_eq!(
-            cuda_header_candidates("/usr/local/cuda", None, "x86_64", "linux"),
-            vec![
-                PathBuf::from("/usr/local/cuda/include/cuda.h"),
-                PathBuf::from("/usr/local/cuda/targets/x86_64-linux/include/cuda.h"),
-            ]
-        );
-        // aarch64 Linux is ambiguous between servers (sbsa-linux) and Tegra
-        // (aarch64-linux), so both are probed, servers first.
-        assert_eq!(
-            cuda_header_candidates("/opt/ctk", None, "aarch64", "linux"),
-            vec![
-                PathBuf::from("/opt/ctk/include/cuda.h"),
-                PathBuf::from("/opt/ctk/targets/sbsa-linux/include/cuda.h"),
-                PathBuf::from("/opt/ctk/targets/aarch64-linux/include/cuda.h"),
-            ]
-        );
-        // Unknown host arch or non-Linux OS: only the standard layout.
-        assert_eq!(
-            cuda_header_candidates("/opt/ctk", None, "riscv64", "linux"),
-            vec![PathBuf::from("/opt/ctk/include/cuda.h")]
-        );
-        assert_eq!(
-            cuda_header_candidates("/opt/ctk", None, "aarch64", "macos"),
-            vec![PathBuf::from("/opt/ctk/include/cuda.h")]
-        );
-        // CUDA_TOOLKIT_TARGET_DIR replaces the table with one directory;
-        // a blank value means "unset".
-        assert_eq!(
-            cuda_header_candidates("/opt/ctk", Some("aarch64-linux"), "aarch64", "linux"),
-            vec![
-                PathBuf::from("/opt/ctk/include/cuda.h"),
-                PathBuf::from("/opt/ctk/targets/aarch64-linux/include/cuda.h"),
-            ]
-        );
-        assert_eq!(
-            cuda_header_candidates("/opt/ctk", Some("  "), "x86_64", "linux"),
-            vec![
-                PathBuf::from("/opt/ctk/include/cuda.h"),
-                PathBuf::from("/opt/ctk/targets/x86_64-linux/include/cuda.h"),
-            ]
-        );
-    }
-
-    #[test]
-    fn parse_rust_toolchain_toml_reads_channel_and_components() {
-        let pin = parse_rust_toolchain_toml(
-            r#"[toolchain]
-channel = "nightly-2026-04-03"
-components = ["rust-src", "rustc-dev", "llvm-tools"]
-"#,
-        )
-        .expect("pin should parse");
-        assert_eq!(pin.channel, "nightly-2026-04-03");
-        assert_eq!(
-            pin.components,
-            vec![
-                "rust-src".to_string(),
-                "rustc-dev".to_string(),
-                "llvm-tools".to_string()
-            ]
-        );
-    }
-
-    #[test]
-    fn parse_rust_toolchain_toml_rejects_missing_channel() {
-        let error = parse_rust_toolchain_toml("[toolchain]\ncomponents = [\"rust-src\"]\n")
-            .expect_err("channel is required");
-        assert!(error.contains("channel"), "{error}");
-    }
-
-    #[test]
-    fn active_toolchain_matches_channel_accepts_target_triple_suffix() {
-        assert!(active_toolchain_matches_channel(
-            "nightly-2026-04-03-aarch64-apple-darwin (default)",
-            "nightly-2026-04-03"
-        ));
-        assert!(active_toolchain_matches_channel(
-            "nightly-2026-04-03",
-            "nightly-2026-04-03"
-        ));
-        assert!(!active_toolchain_matches_channel(
-            "nightly-2026-01-01-x86_64-unknown-linux-gnu (default)",
-            "nightly-2026-04-03"
-        ));
-    }
-
-    #[test]
-    fn active_toolchain_matches_channel_accepts_rustup_128_and_129_formats() {
-        // rustup 1.29 single-line form with an override annotation, as
-        // observed verbatim on a workspace with rust-toolchain.toml.
-        assert!(active_toolchain_matches_channel(
-            "nightly-2026-04-03-x86_64-unknown-linux-gnu (overridden by \
-             '/home/user/cuda-oxide/rust-toolchain.toml')",
-            "nightly-2026-04-03"
-        ));
-        // rustup 1.28 two-line form: bare name, then the reason line.
-        assert!(active_toolchain_matches_channel(
-            "nightly-2026-04-03-x86_64-unknown-linux-gnu\nactive because: \
-             overridden by '/home/user/cuda-oxide/rust-toolchain.toml'",
-            "nightly-2026-04-03"
-        ));
-        // A mismatched pin must not be rescued by later lines.
-        assert!(!active_toolchain_matches_channel(
-            "stable-x86_64-unknown-linux-gnu\nactive because: default",
-            "nightly-2026-04-03"
-        ));
-    }
-
-    #[test]
-    fn plan_update_selects_advise_setup_or_cache_refresh() {
-        assert_eq!(plan_update(true, false), UpdatePlan::AdviseSetup);
-        assert_eq!(plan_update(true, true), UpdatePlan::RunSetup);
-        assert_eq!(plan_update(false, false), UpdatePlan::RefreshCache);
-        assert_eq!(plan_update(false, true), UpdatePlan::RefreshCache);
-    }
-
-    /// A `.cargo/cuda-oxide.toml` backend pin outranks the shared cache, so
-    /// `update` must refuse just like it does for `CUDA_OXIDE_BACKEND`.
-    #[test]
-    fn update_refuses_when_the_config_pins_a_backend() {
-        let pinned = test_context(OxideConfig {
-            backend: Some(PathBuf::from("/tmp/pinned-backend.so")),
-            ..OxideConfig::default()
-        });
-        // `None` stands in for an unset ambient `CUDA_OXIDE_BACKEND`. Reading
-        // the real one would let an exported value produce the env refusal for
-        // both inputs, including the unpinned case asserted to be `None`.
-        let refusal =
-            update_pin_refusal_with_env(&pinned, None).expect("config pin must refuse update");
-        assert!(refusal.contains("pins the backend"), "{refusal}");
-        assert!(refusal.contains("/tmp/pinned-backend.so"), "{refusal}");
-
-        let unpinned = test_context(OxideConfig::default());
-        assert_eq!(update_pin_refusal_with_env(&unpinned, None), None);
-
-        // The env var outranks the project pin: set, it refuses even unpinned.
-        let from_env = update_pin_refusal_with_env(&unpinned, Some("/tmp/env-backend.so".into()))
-            .expect("exported CUDA_OXIDE_BACKEND must refuse update");
-        assert!(from_env.contains("CUDA_OXIDE_BACKEND is set"), "{from_env}");
-    }
-
-    #[test]
-    fn doctor_verified_components_unions_pin_list_with_required_floor() {
-        // Pin lists everything: order preserved, no duplicates appended.
-        let pin = RustToolchainPin {
-            channel: "nightly-2026-04-03".to_string(),
-            components: vec![
-                "rust-src".to_string(),
-                "rustc-dev".to_string(),
-                "rust-analyzer".to_string(),
-                "clippy".to_string(),
-                "llvm-tools".to_string(),
-            ],
-        };
-        assert_eq!(
-            doctor_verified_components(&pin),
-            vec![
-                "rust-src",
-                "rustc-dev",
-                "rust-analyzer",
-                "clippy",
-                "llvm-tools"
-            ]
-        );
-
-        // A trimmed pin still gets the hard floor appended.
-        let trimmed = RustToolchainPin {
-            channel: "nightly-2026-04-03".to_string(),
-            components: vec!["clippy".to_string()],
-        };
-        assert_eq!(
-            doctor_verified_components(&trimmed),
-            vec!["clippy", "rust-src", "rustc-dev", "llvm-tools"]
-        );
-    }
-
-    #[test]
-    fn missing_rustup_components_detects_host_triple_suffixes() {
-        let installed = "\
-rust-src-aarch64-apple-darwin
-clippy-aarch64-apple-darwin
-";
-        assert_eq!(
-            missing_rustup_components(installed, &["rust-src", "llvm-tools"]),
-            vec!["llvm-tools".to_string()]
-        );
-        assert!(missing_rustup_components(installed, &["rust-src"]).is_empty());
-    }
-
-    #[test]
-    fn parse_compute_cap_rejects_failure_banners_and_garbage() {
-        // nvidia-smi prints failure text to STDOUT, not stderr.
-        assert_eq!(
-            parse_compute_cap(
-                "NVIDIA-SMI has failed because it couldn't communicate \
-                 with the NVIDIA driver.\n"
-            ),
-            None
-        );
-        assert_eq!(parse_compute_cap(""), None);
-        assert_eq!(parse_compute_cap("\n"), None);
-        assert_eq!(parse_compute_cap("N/A\n"), None);
-        assert_eq!(parse_compute_cap("12\n"), None);
-        assert_eq!(parse_compute_cap("12.\n"), None);
-        assert_eq!(parse_compute_cap(".5\n"), None);
-        assert_eq!(parse_compute_cap("12.0.1\n"), None);
-    }
-
-    // All three skip cases inject the `CUDA_OXIDE_TARGET` probe rather than
-    // reading the ambient one, so each asserts the slot it names instead of
-    // passing because the developer happens to have the variable exported.
-
-    #[test]
-    fn detect_run_target_arch_skips_when_arch_explicit() {
-        // --arch wins; never query the GPU.
-        assert_eq!(
-            detect_run_target_arch_with_env(Some("sm_120"), false, false),
-            None
-        );
-    }
-
-    #[test]
-    fn detect_run_target_arch_skips_when_emit_nvvm_ir() {
-        // NVVM IR mode requires explicit --arch; auto-detect must not run.
-        assert_eq!(detect_run_target_arch_with_env(None, true, false), None);
-    }
-
-    #[test]
-    fn detect_run_target_arch_skips_when_env_target_set() {
-        // Slot 2 wins; never query the GPU. Injected rather than exported:
-        // `set_var` is a data race against the `vars_os` reads the fingerprint
-        // helpers perform on other test threads, which the cargo test harness
-        // runs concurrently by default.
-        assert_eq!(detect_run_target_arch_with_env(None, false, true), None);
-    }
-
-    fn write_list_example(
-        examples_dir: &Path,
-        name: &str,
-        manifest_description: Option<&str>,
-        readme: Option<&str>,
-    ) {
-        let example_dir = examples_dir.join(name);
-        std::fs::create_dir_all(&example_dir).unwrap();
-
-        let description = manifest_description
-            .map(|value| format!("description = {value:?}\n"))
-            .unwrap_or_default();
-
-        std::fs::write(
-            example_dir.join("Cargo.toml"),
-            format!(
-                "[package]\nname = {name:?}\nversion = \"0.1.0\"\nedition = \"2024\"\n{description}"
-            ),
-        )
-        .unwrap();
-
-        if let Some(readme) = readme {
-            std::fs::write(example_dir.join("README.md"), readme).unwrap();
-        }
-    }
-
-    #[test]
-    fn readme_parser_extracts_title_description_and_requirements() {
-        let parsed = parse_example_readme(
-            "vecadd",
-            r#"
-# vecadd
-
-## Vector Addition
-
-Adds two vectors using one CUDA thread per element.
-
-## Hardware Requirements
-
-- **Minimum GPU**: sm_70+
-- **CUDA Toolkit**: 12.x+
-"#,
-        );
-
-        assert_eq!(parsed.title.as_deref(), Some("Vector Addition"));
-        assert_eq!(
-            parsed.description.as_deref(),
-            Some("Adds two vectors using one CUDA thread per element.")
-        );
-        assert_eq!(
-            parsed.requirements,
-            ["Minimum GPU: sm_70+", "CUDA Toolkit: 12.x+"]
-        );
-    }
-
-    #[test]
-    fn readme_parser_does_not_use_run_as_title() {
-        let parsed = parse_example_readme(
-            "cuda_module_nested",
-            r#"
-# cuda_module_nested
-
-## Run
-
-Expected output:
-
-```text
-PASS
-```
-
-"#,
-        );
-
-        assert_eq!(parsed.title.as_deref(), Some("cuda_module_nested"));
-        assert_eq!(parsed.description, None);
-    }
-
-    #[test]
-    fn readme_parser_does_not_scan_later_headings_for_title() {
-        let parsed = parse_example_readme(
-            "example",
-            r#"
-
-# example
-
-Introductory description.
-
-## Build
-
-Build instructions.
-
-## Advanced Implementation Details
-
-Internal details.
-"#,
-        );
-
-        assert_eq!(parsed.title.as_deref(), Some("example"));
-        assert_eq!(
-            parsed.description.as_deref(),
-            Some("Introductory description.")
-        );
-    }
-
-    #[test]
-    fn readme_parser_stops_description_at_next_heading() {
-        let parsed = parse_example_readme(
-            "vecadd",
-            r#"
-
-# vecadd
-
-## Vector Addition
-
-Adds two vectors on the GPU.
-
-## Run
-
-Run the example with cargo oxide.
-"#,
-        );
-
-        assert_eq!(parsed.title.as_deref(), Some("Vector Addition"));
-        assert_eq!(
-            parsed.description.as_deref(),
-            Some("Adds two vectors on the GPU.")
-        );
-    }
-
-    #[test]
-    fn requirement_parser_joins_wrapped_list_items() {
-        let parsed = parse_example_readme(
-            "example",
-            r#"
-
-# example
-
-## Requirements
-
-* CUDA Toolkit 13.1+ with nvcc and tileiras available. This example
-  also requires the CUDA development libraries.
-* Blackwell GPU with sm_100+ support.
-  "#,
-        );
-
-        assert_eq!(
-            parsed.requirements,
-            [
-                "CUDA Toolkit 13.1+ with nvcc and tileiras available. This example also requires the CUDA development libraries.",
-                "Blackwell GPU with sm_100+ support.",
-            ]
-        );
-    }
-
-    #[test]
-    fn requirement_parser_does_not_absorb_paragraph_after_blank_line() {
-        // Modeled on the cpp_consumes_rust_device README: a bullet list under
-        // the requirements heading, then a blank line, then a follow-up
-        // paragraph and a code fence. The paragraph is a new paragraph, not a
-        // wrapped continuation of the last bullet.
-        let parsed = parse_example_readme(
-            "cpp_consumes_rust_device",
-            r#"
-# cpp_consumes_rust_device
-
-## Prerequisites
-
-- CUDA Toolkit (nvcc, libNVVM, nvJitLink)
-- Blackwell+ GPU (sm_100+) — LTOIR requires NVVM 20 dialect
-
-If your default host compiler is newer than the CUDA Toolkit supports, set
-`NVCC_CCBIN` or `CUDAHOSTCXX` before running the example:
-
-```bash
-NVCC_CCBIN=/usr/bin/g++-15 cargo oxide run cpp_consumes_rust_device
-```
-"#,
-        );
-
-        assert_eq!(
-            parsed.requirements,
-            [
-                "CUDA Toolkit (nvcc, libNVVM, nvJitLink)",
-                "Blackwell+ GPU (sm_100+) — LTOIR requires NVVM 20 dialect",
-            ]
-        );
-    }
-
-    #[test]
-    fn requirement_parser_joins_wrapped_items_but_not_following_paragraphs() {
-        // Modeled on the cutile_inter_kernel README: the last bullet wraps
-        // across indented lines (joined), and the paragraph after the blank
-        // line must not be glued onto it.
-        let parsed = parse_example_readme(
-            "cutile_inter_kernel",
-            r#"
-# cutile_inter_kernel
-
-## Requirements
-
-- cuda-oxide from this repository.
-- CUDA Toolkit 13.1+ with `nvcc` and `tileiras` available. This example
-  defaults `CUDA_TOOLKIT_PATH` to `/usr/local/cuda` through its local Cargo
-  config; set `CUDA_TOOLKIT_PATH` yourself if your toolkit lives elsewhere.
-
-`cargo oxide run` targets explicit `--arch` first, then `CUDA_OXIDE_TARGET`,
-then auto-detects the local GPU.
-
-## Run
-
-Run instructions.
-"#,
-        );
-
-        assert_eq!(
-            parsed.requirements,
-            [
-                "cuda-oxide from this repository.",
-                "CUDA Toolkit 13.1+ with nvcc and tileiras available. This example \
-                 defaults CUDA_TOOLKIT_PATH to /usr/local/cuda through its local Cargo \
-                 config; set CUDA_TOOLKIT_PATH yourself if your toolkit lives elsewhere.",
-            ]
-        );
-    }
-
-    #[test]
-    fn requirement_parser_captures_ordered_list_items() {
-        // Modeled on the mathdx_ffi_test README: prerequisites written as an
-        // ordered list, followed by a paragraph that is not part of the list.
-        let parsed = parse_example_readme(
-            "mathdx_ffi_test",
-            r#"
-# mathdx_ffi_test
-
-## Prerequisites
-
-1. **CUDA Toolkit 12.x+** with nvcc
-2. **MathDx Library** - Download from: https://developer.nvidia.com/cublasdx-downloads
-3. **cuda-oxide compiler** toolchain
-
-If your default host compiler is newer than the CUDA Toolkit supports, set
-`NVCC_CCBIN` or `CUDAHOSTCXX` before running the example.
-"#,
-        );
-
-        assert_eq!(
-            parsed.requirements,
-            [
-                "CUDA Toolkit 12.x+ with nvcc",
-                "MathDx Library - Download from: https://developer.nvidia.com/cublasdx-downloads",
-                "cuda-oxide compiler toolchain",
-            ]
-        );
-    }
-
-    #[test]
-    fn requirement_parser_recognizes_build_requirements_heading() {
-        let parsed = parse_example_readme(
-            "example",
-            r#"
-# example
-
-## Build Requirements
-
-- nvcc with `--expt-relaxed-constexpr`
-"#,
-        );
-
-        assert_eq!(parsed.requirements, ["nvcc with --expt-relaxed-constexpr"]);
-    }
-
-    #[test]
-    fn requirement_parser_parses_two_column_requirement_tables() {
-        // Modeled on the abi_hmm README: requirements in a two-column table,
-        // including an escaped pipe inside a cell.
-        let parsed = parse_example_readme(
-            "abi_hmm",
-            r#"
-# abi_hmm
-
-## Requirements
-
-| Requirement   | Minimum                                           |
-|---------------|---------------------------------------------------|
-| GPU           | Turing or newer (RTX 20xx+)                       |
-| Linux Kernel  | 6.1.24+                                           |
-| HMM Support   | `nvidia-smi -q \| grep Addressing` shows "HMM"    |
-
-## Build and Run
-
-Instructions.
-"#,
-        );
-
-        assert_eq!(
-            parsed.requirements,
-            [
-                "GPU: Turing or newer (RTX 20xx+)",
-                "Linux Kernel: 6.1.24+",
-                "HMM Support: nvidia-smi -q | grep Addressing shows \"HMM\"",
-            ]
-        );
-    }
-
-    #[test]
-    fn requirement_parser_skips_tables_that_are_not_two_columns() {
-        // A three-column table has no unambiguous name/value mapping, so it
-        // must be skipped whole instead of half-parsed.
-        let parsed = parse_example_readme(
-            "example",
-            r#"
-# example
-
-## Requirements
-
-| Test  | Status | Description |
-|-------|--------|-------------|
-| alpha | Pass   | First test  |
-| beta  | Pass   | Second test |
-"#,
-        );
-
-        assert_eq!(parsed.requirements, Vec::<String>::new());
-    }
-
-    #[test]
-    fn example_discovery_is_sorted_and_uses_manifest_fallback() {
-        let root = unique_temp_dir("cargo_oxide_list_examples");
-        std::fs::create_dir_all(&root).unwrap();
-
-        write_list_example(&root, "zeta", Some("Manifest fallback description"), None);
-
-        write_list_example(
-            &root,
-            "alpha",
-            None,
-            Some("# alpha\n\n## Alpha Example\n\nREADME description.\n"),
-        );
-
-        let examples = discover_examples(&root).unwrap();
-
-        assert_eq!(
-            examples
-                .iter()
-                .map(|example| example.name.as_str())
-                .collect::<Vec<_>>(),
-            ["alpha", "zeta"]
-        );
-        assert_eq!(examples[0].description, "README description.");
-        assert_eq!(examples[1].description, "Manifest fallback description");
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn example_discovery_keeps_examples_without_readmes() {
-        let root = unique_temp_dir("cargo_oxide_list_missing_readme");
-        std::fs::create_dir_all(&root).unwrap();
-
-        write_list_example(&root, "minimal", None, None);
-
-        let examples = discover_examples(&root).unwrap();
-
-        assert_eq!(examples.len(), 1);
-        assert_eq!(examples[0].name, "minimal");
-        assert_eq!(examples[0].description, "No description documented.");
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn example_discovery_skips_directory_without_manifest() {
-        let root = unique_temp_dir("cargo_oxide_list_missing_manifest");
-        std::fs::create_dir_all(root.join("scratch")).unwrap();
-
-        write_list_example(&root, "real", Some("A real example"), None);
-
-        let examples =
-            discover_examples(&root).expect("manifest-less directories must not abort listing");
-
-        assert_eq!(
-            examples
-                .iter()
-                .map(|example| example.name.as_str())
-                .collect::<Vec<_>>(),
-            ["real"]
-        );
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn interop_metadata_selects_named_binary_artifact() {
-        let root = unique_temp_dir("cargo_oxide_named_bin_interop");
-        let device_dir = root.join("device");
-        std::fs::create_dir_all(&device_dir).unwrap();
-
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"[package]
-name = "host-app"
-version = "0.1.0"
-edition = "2024"
-
-[[package.metadata.cuda-oxide.device-crates]]
-manifest-path = "device/Cargo.toml"
-bin = "secondary-device"
-"#,
-        )
-        .unwrap();
-        std::fs::write(
-            device_dir.join("Cargo.toml"),
-            r#"[package]
-name = "kernel-package"
-version = "0.1.0"
-edition = "2024"
-"#,
-        )
-        .unwrap();
-
-        let config = load_interop_config(&root).expect("interop metadata should load");
-        let device = &config.device_crates[0];
-        assert_eq!(device.bin.as_deref(), Some("secondary-device"));
-        assert_eq!(
-            interop_device_cargo_target_name(&device_dir.join("Cargo.toml"), device),
-            "secondary-device"
-        );
-        assert_eq!(
-            interop_device_artifact_name(&device_dir.join("Cargo.toml"), device),
-            "secondary_device"
-        );
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn interop_binary_target_uses_cargo_source_path() {
-        let manifest = Path::new("/workspace/kernels/Cargo.toml");
-        let metadata = serde_json::json!({
-            "packages": [{
-                "manifest_path": "/workspace/kernels/Cargo.toml",
-                "targets": [
-                    {
-                        "name": "kernel-package",
-                        "kind": ["lib"],
-                        "src_path": "/workspace/kernels/src/lib.rs"
-                    },
-                    {
-                        "name": "secondary-device",
-                        "kind": ["bin"],
-                        "src_path": "/workspace/kernels/src/device_secondary.rs"
-                    }
-                ]
-            }]
-        });
-
-        assert_eq!(
-            interop_binary_target_from_metadata(&metadata, manifest, "secondary-device").unwrap(),
-            InteropBinaryTarget {
-                source_path: PathBuf::from("/workspace/kernels/src/device_secondary.rs"),
-            }
-        );
-    }
-
-    #[test]
-    fn interop_binary_target_rejects_unknown_name_with_available_targets() {
-        let manifest = Path::new("/workspace/kernels/Cargo.toml");
-        let metadata = serde_json::json!({
-            "packages": [{
-                "manifest_path": "/workspace/kernels/Cargo.toml",
-                "targets": [{
-                    "name": "main-device",
-                    "kind": ["bin"],
-                    "src_path": "/workspace/kernels/src/device_main.rs"
-                }]
-            }]
-        });
-
-        let error =
-            interop_binary_target_from_metadata(&metadata, manifest, "missing-device").unwrap_err();
-        assert!(error.contains("no binary target \"missing-device\""));
-        assert!(error.contains("available binary targets: main-device"));
-    }
-
-    #[test]
-    fn release_depfile_stem_preserves_hyphens_like_cargo_uplift() {
-        let target_dir = Path::new("/workspace/device/target");
-        // Regression: the stem was normalize_crate_name'd (hyphen -> underscore),
-        // but cargo uplifts dep-info named after the bin target verbatim, so
-        // every hyphenated bin/package with source-identity aborted with
-        // "did not produce dependency file".
-        assert_eq!(
-            release_depfile_path(target_dir, "simt-device"),
-            PathBuf::from("/workspace/device/target/release/simt-device.d")
-        );
-        assert_eq!(
-            release_depfile_path(target_dir, "kernels"),
-            PathBuf::from("/workspace/device/target/release/kernels.d")
-        );
-    }
-
-    /// The load-bearing claim behind `release_depfile_path` is cargo's own
-    /// uplift naming, so assert it against a real `cargo build` of a
-    /// hyphenated package with a hyphenated bin target rather than against
-    /// our expectations of it.
-    #[test]
-    fn release_depfile_path_matches_real_cargo_uplift_for_hyphenated_bin() {
-        let root = unique_temp_dir("cargo_oxide_hyphen_depfile");
-        std::fs::create_dir_all(root.join("src/bin")).unwrap();
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"[package]
-name = "probe-device"
-version = "0.1.0"
-edition = "2021"
-
-[[bin]]
-name = "hyphen-device"
-path = "src/bin/hyphen_device.rs"
-"#,
-        )
-        .unwrap();
-        std::fs::write(root.join("src/bin/hyphen_device.rs"), "fn main() {}\n").unwrap();
-        // Pin the probe's target dir inside the temp root so an ambient
-        // CARGO_TARGET_DIR (shared CI caches) cannot collide across tests.
-        let target_dir = root.join("target");
-
-        let build = Command::new("cargo")
-            .args(["build", "--release", "--bin", "hyphen-device"])
-            .env("CARGO_TARGET_DIR", &target_dir)
-            .current_dir(&root)
-            .output()
-            .expect("failed to run cargo build for the depfile probe");
-        assert!(
-            build.status.success(),
-            "depfile probe build failed:\n{}",
-            String::from_utf8_lossy(&build.stderr)
-        );
-
-        let metadata = Command::new("cargo")
-            .args(["metadata", "--format-version=1", "--no-deps"])
-            .env("CARGO_TARGET_DIR", &target_dir)
-            .current_dir(&root)
-            .output()
-            .expect("failed to run cargo metadata for the depfile probe");
-        assert!(
-            metadata.status.success(),
-            "depfile probe metadata failed:\n{}",
-            String::from_utf8_lossy(&metadata.stderr)
-        );
-        let metadata: serde_json::Value = serde_json::from_slice(&metadata.stdout).unwrap();
-
-        let depfile =
-            release_depfile_path(&cargo_target_directory(&metadata).unwrap(), "hyphen-device");
-        assert!(
-            depfile.is_file(),
-            "cargo did not uplift the dep-info where we derive it: {}",
-            depfile.display()
-        );
-        // The underscore-normalized twin must NOT be where we look.
-        assert!(
-            !depfile.with_file_name("hyphen_device.d").exists(),
-            "cargo unexpectedly uplifted an underscore-normalized dep-info file"
-        );
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn ptx_artifact_paths_normalize_hyphenated_example_names() {
-        let root = unique_temp_dir("cargo_oxide_inspect_regular");
-        std::fs::create_dir_all(&root).unwrap();
-
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"[package]
-name = "demo-app"
-version = "0.1.0"
-edition = "2024"
-"#,
-        )
-        .unwrap();
-
-        assert_eq!(
-            ptx_artifact_paths(&root, "demo-app"),
-            vec![root.join("demo_app.ptx")]
-        );
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn ptx_artifact_paths_resolve_interop_device_artifacts() {
-        let root = unique_temp_dir("cargo_oxide_inspect_interop");
-        let device_dir = root.join("device");
-        std::fs::create_dir_all(&device_dir).unwrap();
-
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"[package]
-name = "host-app"
-version = "0.1.0"
-edition = "2024"
-
-[package.metadata.cuda-oxide]
-interop = "device"
-
-[[package.metadata.cuda-oxide.device-crates]]
-manifest-path = "device/Cargo.toml"
-ptx-dir = "generated"
-artifact-name = "custom-device"
-"#,
-        )
-        .unwrap();
-
-        std::fs::write(
-            device_dir.join("Cargo.toml"),
-            r#"[package]
-name = "device-app"
-version = "0.1.0"
-edition = "2024"
-"#,
-        )
-        .unwrap();
-
-        assert_eq!(
-            ptx_artifact_paths(&root, "host-app"),
-            vec![root.join("generated/custom_device.ptx")]
-        );
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn interop_metadata_declares_cubin_and_source_identity() {
-        let root = unique_temp_dir("cargo_oxide_cubin_interop");
-        let device_dir = root.join("device");
-        std::fs::create_dir_all(&device_dir).unwrap();
-
-        std::fs::write(
-            root.join("Cargo.toml"),
-            r#"[package]
-name = "host-app"
-version = "0.1.0"
-edition = "2024"
-
-[package.metadata.cuda-oxide]
-interop = "device"
-
-[[package.metadata.cuda-oxide.device-crates]]
-manifest-path = "device/Cargo.toml"
-artifact-dir = "device"
-artifact-name = "custom-device"
-artifact-kind = "cubin"
-source-identity = true
-"#,
-        )
-        .unwrap();
-        std::fs::write(
-            device_dir.join("Cargo.toml"),
-            r#"[package]
-name = "device-app"
-version = "0.1.0"
-edition = "2024"
-"#,
-        )
-        .unwrap();
-
-        let config = load_interop_config(&root).expect("interop metadata should load");
-        assert_eq!(config.device_crates.len(), 1);
-        let device = &config.device_crates[0];
-        assert_eq!(device.artifact_kind, InteropArtifactKind::Cubin);
-        assert!(device.source_identity);
-        assert_eq!(
-            interop_device_artifact_path(&root, device, "custom-device"),
-            root.join("device/custom_device.cubin")
-        );
-        assert_eq!(
-            interop_cubin_target(Some("sm_120a"), None).unwrap().sm(),
-            "sm_120a"
-        );
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn recorded_target_sidecar_is_the_completion_marker() {
-        let root = unique_temp_dir("cargo_oxide_recorded_target");
-        std::fs::create_dir_all(&root).unwrap();
-        let ir_path = root.join("device_kernels.ll");
-
-        // No sidecar: the backend never completed its artifact contract.
-        let error = read_interop_recorded_target(&ir_path).unwrap_err();
-        assert!(error.contains("completion marker"), "{error}");
-
-        // Bare target line (pre-versioned contract) is accepted.
-        std::fs::write(root.join("device_kernels.target"), "sm_90a\n").unwrap();
-        assert_eq!(read_interop_recorded_target(&ir_path).unwrap(), "sm_90a");
-
-        // The versioned marker says the sibling .options file is required...
-        std::fs::write(
-            root.join("device_kernels.target"),
-            format!(
-                "sm_120a\n{}\n",
-                oxide_artifacts::COMPILE_OPTIONS_TARGET_MARKER
-            ),
-        )
-        .unwrap();
-        let error = read_interop_recorded_target(&ir_path).unwrap_err();
-        assert!(error.contains("compile options"), "{error}");
-
-        // ...and the record is trusted once it exists.
-        std::fs::write(root.join("device_kernels.options"), "fma=on\ndebug=none\n").unwrap();
-        assert_eq!(read_interop_recorded_target(&ir_path).unwrap(), "sm_120a");
-
-        // Unknown trailing content is rejected, not half-trusted.
-        std::fs::write(
-            root.join("device_kernels.target"),
-            "sm_120a\nmystery-marker\nrest\n",
-        )
-        .unwrap();
-        assert!(read_interop_recorded_target(&ir_path).is_err());
-        std::fs::write(root.join("device_kernels.target"), "\n").unwrap();
-        assert!(read_interop_recorded_target(&ir_path).is_err());
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn ptx_recorded_target_reads_the_target_directive() {
-        let root = unique_temp_dir("cargo_oxide_ptx_target");
-        std::fs::create_dir_all(&root).unwrap();
-        let ptx_path = root.join("kernels.ptx");
-
-        std::fs::write(
-            &ptx_path,
-            "// comment\n.version 8.7\n.target sm_120a\n.address_size 64\n",
-        )
-        .unwrap();
-        assert_eq!(ptx_recorded_target(&ptx_path).unwrap(), "sm_120a");
-
-        // Device-debug builds record `.target sm_90, debug`.
-        std::fs::write(&ptx_path, ".version 8.3\n.target sm_90, debug\n").unwrap();
-        assert_eq!(ptx_recorded_target(&ptx_path).unwrap(), "sm_90");
-
-        std::fs::write(&ptx_path, ".version 8.3\n").unwrap();
-        assert!(ptx_recorded_target(&ptx_path).is_err());
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn interop_identity_target_is_read_from_the_emitted_artifact() {
-        let root = unique_temp_dir("cargo_oxide_identity_target");
-        std::fs::create_dir_all(root.join("device")).unwrap();
-
-        let ptx_crate = DeviceCrateConfig {
-            manifest_path: PathBuf::from("device/Cargo.toml"),
-            artifact_dir: PathBuf::from("device"),
-            artifact_name: Some("kernels".to_string()),
-            artifact_kind: InteropArtifactKind::Ptx,
-            source_identity: true,
-            bin: None,
-        };
-        // Whatever the request hint said, the emitted PTX is the record.
-        std::fs::write(
-            root.join("device/kernels.ptx"),
-            ".version 8.7\n.target sm_90a\n",
-        )
-        .unwrap();
-        assert_eq!(
-            interop_artifact_recorded_target(&root, &ptx_crate, "kernels").unwrap(),
-            "sm_90a"
-        );
-
-        // Cubin identity reads the backend sidecar the finalizer compiled
-        // with, not the PTX and not any hint.
-        let cubin_crate = DeviceCrateConfig {
-            artifact_kind: InteropArtifactKind::Cubin,
-            ..ptx_crate
-        };
-        std::fs::write(root.join("device/kernels.target"), "sm_100a\n").unwrap();
-        assert_eq!(
-            interop_artifact_recorded_target(&root, &cubin_crate, "kernels").unwrap(),
-            "sm_100a"
-        );
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn read_ptx_artifact_returns_exact_contents() {
-        let root = unique_temp_dir("cargo_oxide_read_ptx");
-        std::fs::create_dir_all(&root).unwrap();
-
-        let path = root.join("demo.ptx");
-        std::fs::write(&path, ".version 8.0\n.target sm_90\n").unwrap();
-
-        assert_eq!(
-            read_ptx_artifact(&path).unwrap(),
-            ".version 8.0\n.target sm_90\n"
-        );
-
-        std::fs::remove_dir_all(root).unwrap();
-    }
-
-    #[test]
-    fn list_json_has_versioned_stable_shape() {
-        let examples = vec![ExampleInfo {
-            name: "vecadd".to_string(),
-            title: "Vector Addition".to_string(),
-            description: "Adds two vectors.".to_string(),
-            requirements: vec!["Minimum GPU: sm_70+".to_string()],
-        }];
-
-        let output = format_examples_json(&examples).unwrap();
-        let value: serde_json::Value = serde_json::from_str(&output).unwrap();
-
-        assert_eq!(value["schema_version"], 1);
-        assert_eq!(value["examples"][0]["name"], "vecadd");
-        assert_eq!(
-            value["examples"][0]["requirements"][0],
-            "Minimum GPU: sm_70+"
-        );
-        assert!(output.ends_with('\n'));
-    }
-
-    #[test]
-    fn read_ptx_artifact_reports_missing_file() {
-        let root = unique_temp_dir("cargo_oxide_missing_ptx");
-        let path = root.join("missing.ptx");
-
-        let error = read_ptx_artifact(&path).unwrap_err();
-
-        assert!(error.contains("could not read generated PTX"));
-        assert!(error.contains("missing.ptx"));
-    }
-
-    #[test]
-    fn nvvm_ir_requested_reads_project_configuration() {
-        let ctx = Context {
-            workspace_root: PathBuf::from("/tmp/project"),
-            codegen_crate: PathBuf::from("/tmp/project"),
-            examples_dir: PathBuf::from("/tmp/project"),
-            backend_so: PathBuf::from("/tmp/backend.so"),
-            is_workspace: false,
-            config: OxideConfig {
-                env: vec![("CUDA_OXIDE_EMIT_NVVM_IR".to_string(), "true".to_string())],
-                ..OxideConfig::default()
-            },
-        };
-
-        assert_eq!(nvvm_ir_requested_with_env(&ctx, None), Ok(true));
-    }
-
-    #[test]
-    fn nvvm_ir_requested_accepts_disabled_project_configuration() {
-        let ctx = Context {
-            workspace_root: PathBuf::from("/tmp/project"),
-            codegen_crate: PathBuf::from("/tmp/project"),
-            examples_dir: PathBuf::from("/tmp/project"),
-            backend_so: PathBuf::from("/tmp/backend.so"),
-            is_workspace: false,
-            config: OxideConfig {
-                env: vec![("CUDA_OXIDE_EMIT_NVVM_IR".to_string(), "false".to_string())],
-                ..OxideConfig::default()
-            },
-        };
-
-        assert_eq!(nvvm_ir_requested_with_env(&ctx, None), Ok(false));
-    }
-
-    #[test]
-    fn nvvm_ir_requested_env_disable_overrides_enabled_project_configuration() {
-        let ctx = Context {
-            workspace_root: PathBuf::from("/tmp/project"),
-            codegen_crate: PathBuf::from("/tmp/project"),
-            examples_dir: PathBuf::from("/tmp/project"),
-            backend_so: PathBuf::from("/tmp/backend.so"),
-            is_workspace: false,
-            config: OxideConfig {
-                env: vec![("CUDA_OXIDE_EMIT_NVVM_IR".to_string(), "true".to_string())],
-                ..OxideConfig::default()
-            },
-        };
-
-        // The process environment outranks `cuda-oxide.toml`: an explicit
-        // false in the environment wins over the project's `true`, in either
-        // accepted spelling.
-        for disabled in ["false", "0"] {
-            assert_eq!(
-                nvvm_ir_requested_with_env(&ctx, Some(disabled.into())),
-                Ok(false)
-            );
-        }
-    }
-
-    #[test]
-    fn scaffold_sync_template_uses_launch_contract_and_docs() {
-        let files = scaffold_files("demo_kernel", false);
-        assert!(files.cargo_toml.contains("name = \"demo_kernel\""));
-        assert!(files.readme.contains("cargo oxide doctor"));
-        assert!(files.readme.contains("cargo oxide run"));
-        assert!(files.gitignore.contains("/target/"));
-        // The template uses the launch_bounds / launch_contract attribute
-        // macros, so the cuda_device import must bring them in; a scaffolded
-        // project fails to compile without this exact line.
-        assert!(files.main_rs.starts_with(
-            "use cuda_device::{kernel, launch_bounds, launch_contract, thread, DisjointSlice};"
-        ));
-        assert!(
-            files
-                .main_rs
-                .contains("#[launch_contract(domain = 1, block = (256, 1, 1))]")
-        );
-        assert!(files.main_rs.contains("prepare_vecadd"));
-        assert!(files.main_rs.contains("LaunchConfig1D"));
-        assert!(!files.main_rs.contains("LaunchConfig::for_num_elems"));
-    }
-
-    #[test]
-    fn scaffold_async_template_keeps_async_deps_and_docs() {
-        let files = scaffold_files("async_demo", true);
-        assert!(files.cargo_toml.contains("cuda-async"));
-        assert!(files.cargo_toml.contains("tokio"));
-        assert!(files.readme.contains("async cuda-oxide"));
-        assert!(files.readme.contains("cargo oxide doctor"));
-        // The async README must stand alone: it describes the async launch
-        // path and never talks about "the sync template".
-        assert!(files.readme.contains("DeviceOperation"));
-        assert!(!files.readme.contains("sync template"));
-        assert!(files.gitignore.contains("**/*.ptx"));
-        assert!(files.main_rs.contains("vecadd_async"));
-        assert!(files.main_rs.contains("use cuda_host::cuda_module;"));
-        assert!(!files.main_rs.contains("use cuda_device::{cuda_module"));
-    }
-
-    #[test]
-    fn scaffold_gitignore_covers_every_clean_artifact_suffix() {
-        let gitignore = scaffold_gitignore();
-        assert!(gitignore.contains("/target/"));
-        assert!(gitignore.contains("**/*.bc"));
-        for suffix in GENERATED_ARTIFACT_SUFFIXES {
-            // Match whole lines, not substrings: `**/*.cubin.target` contains
-            // `**/*.cubin` as a substring, so `contains()` would keep passing
-            // even if the `cubin` pattern itself were dropped.
-            let pattern = format!("**/*.{suffix}");
-            assert!(
-                gitignore.lines().any(|line| line == pattern),
-                "scaffold .gitignore must ignore clean suffix `{suffix}`"
-            );
-        }
-    }
-
-    #[test]
-    fn device_debug_env_value_matches_the_backend_parser() {
-        // The exported strings must round-trip through the shared
-        // `CUDA_OXIDE_DEBUG` parser (the same one the codegen backend uses);
-        // a typo would silently fall through to the profile-derived default
-        // instead of failing, so check the actual parse.
-        assert_eq!(DeviceDebug::Off.env_value(), None);
-        assert_eq!(DeviceDebug::LineTables.env_value(), Some("line"));
-        assert_eq!(DeviceDebug::Full.env_value(), Some("full"));
-        assert_eq!(
-            cuda_artifact_finalizer::DebugPolicy::parse_env_override("line"),
-            Some(cuda_artifact_finalizer::DebugPolicy::LineTables)
-        );
-        assert_eq!(
-            cuda_artifact_finalizer::DebugPolicy::parse_env_override("full"),
-            Some(cuda_artifact_finalizer::DebugPolicy::Full)
-        );
-    }
-
-    #[test]
-    fn passthrough_fingerprint_separates_the_device_debug_policies() {
-        let ctx = test_context(OxideConfig::default());
-        let base = CargoPassthroughOptions {
-            verbose: false,
-            emit_nvvm_ir: false,
-            arch: None,
-            features: None,
-            cargo_target_dir: None,
-            device_codegen_crate: None,
-            device_cfgs: &[],
-            no_fmad: false,
-            unchecked_indexing: false,
-            materialize_cubin: false,
-            device_debug: DeviceDebug::Off,
-        };
-        let line_tables = CargoPassthroughOptions {
-            device_debug: DeviceDebug::LineTables,
-            ..base
-        };
-        let full = CargoPassthroughOptions {
-            device_debug: DeviceDebug::Full,
-            ..base
-        };
-        let materialization = MaterializationMode::default();
-        // Empty inherited env, for the same reason as the sibling fingerprint
-        // tests: an ambient CUDA_OXIDE_DEBUG is folded in on its own, which would
-        // collapse these onto the base.
-        let inherited_env = BTreeMap::new();
-        let fp = |opts: &CargoPassthroughOptions<'_>| {
-            passthrough_codegen_fingerprint_with_env(
-                &ctx,
-                opts,
-                None,
-                None,
-                &materialization,
-                &inherited_env,
-            )
-        };
-        // The policy changes what libNVVM and nvJitLink are asked to do (`-g`,
-        // `-opt=0`, `-lineinfo`), so it must not share a fingerprint with the
-        // default -- otherwise Cargo reuses artifacts built without it.
-        let off = fp(&base);
-        assert_ne!(off, fp(&line_tables));
-        assert_ne!(off, fp(&full));
-        assert_ne!(fp(&line_tables), fp(&full));
-    }
-
-    #[test]
-    fn full_device_debug_disables_mir_optimization() {
-        let cmd = Command::new("cargo");
-        let mut encoded = "base".to_string();
-
-        append_full_debug_mir_rustflag(&mut encoded, &cmd, Some("full"));
-
-        assert_eq!(decoded_rustflags(&encoded), ["base", "-Zmir-opt-level=0"]);
-    }
-
-    #[test]
-    fn numeric_full_debug_alias_disables_mir_optimization() {
-        // The backend accepts `CUDA_OXIDE_DEBUG=2` as full debug; the shared
-        // parser guarantees the build policy agrees, so `2` must disable MIR
-        // optimization exactly like `full`.
-        let mut cmd = Command::new("cargo");
-        cmd.env("CUDA_OXIDE_DEBUG", "2");
-        let mut encoded = "base".to_string();
-
-        append_full_debug_mir_rustflag(&mut encoded, &cmd, None);
-
-        assert_eq!(decoded_rustflags(&encoded), ["base", "-Zmir-opt-level=0"]);
-    }
-
-    #[test]
-    fn line_tables_keep_normal_mir_optimization() {
-        let mut cmd = Command::new("cargo");
-        cmd.env("CUDA_OXIDE_DEBUG", "line");
-        let mut encoded = "base".to_string();
-
-        append_full_debug_mir_rustflag(&mut encoded, &cmd, None);
-
-        assert_eq!(decoded_rustflags(&encoded), ["base"]);
-    }
-
-    #[test]
-    fn explicit_line_tables_override_inherited_full_debug_for_mir_optimization() {
-        let mut cmd = Command::new("cargo");
-        cmd.env("CUDA_OXIDE_DEBUG", "line");
-        let mut encoded = "base".to_string();
-
-        append_full_debug_mir_rustflag(&mut encoded, &cmd, Some("full"));
-
-        assert_eq!(decoded_rustflags(&encoded), ["base"]);
-    }
-}
diff --git a/crates/cargo-oxide/src/commands/artifacts.rs b/crates/cargo-oxide/src/commands/artifacts.rs
new file mode 100644
index 0000000000..85ddd2eaf1
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/artifacts.rs
@@ -0,0 +1,166 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::path::{Path, PathBuf};
+
+use super::*;
+
+/// Touch main.rs to force recompilation (faster than cargo clean).
+pub(super) fn touch_main_rs(example_dir: &Path) {
+    // Force a rebuild so the codegen backend re-runs and emits a fresh
+    // .ptx alongside the example. Touch every source file that might
+    // host `#[kernel]` items so multi-bin layouts (kernels in `lib.rs`,
+    // tests in `main.rs`, perf bench in `bin/<name>.rs`, etc.) all
+    // re-codegen on every `cargo oxide run/build` invocation.
+    for rel in ["src/main.rs", "src/lib.rs"] {
+        touch_source_file(&example_dir.join(rel));
+    }
+}
+
+pub(super) fn touch_source_file(path: &Path) {
+    if path.exists()
+        && let Ok(content) = std::fs::read(path)
+    {
+        let _ = std::fs::write(path, content);
+    }
+}
+
+/// Artifacts are named after the crate, and cargo normalizes hyphens in
+/// package names to underscores (`rustlantis-smoke` emits
+/// `rustlantis_smoke.ptx`). Always go through this when deriving an
+/// artifact filename from an example name, or hyphenated examples keep
+/// stale artifacts forever.
+pub(super) fn artifact_stem(example: &str) -> String {
+    example.replace('-', "_")
+}
+
+/// Return the PTX artifacts generated for a regular or metadata-interop project.
+pub(super) fn ptx_artifact_paths(example_dir: &Path, example: &str) -> Vec<PathBuf> {
+    if let Some(interop) =
+        load_interop_config(example_dir).filter(|config| !config.device_crates.is_empty())
+    {
+        return interop
+            .device_crates
+            .iter()
+            .filter(|device_crate| device_crate.artifact_kind == InteropArtifactKind::Ptx)
+            .map(|device_crate| {
+                let manifest_path = example_dir.join(&device_crate.manifest_path);
+                let artifact_name = interop_device_artifact_name(&manifest_path, device_crate);
+
+                interop_device_artifact_path(example_dir, device_crate, &artifact_name)
+            })
+            .collect();
+    }
+
+    let stem = artifact_stem(example);
+    vec![example_dir.join(format!("{stem}.ptx"))]
+}
+
+pub(super) fn read_ptx_artifact(path: &Path) -> Result<String, String> {
+    std::fs::read_to_string(path)
+        .map_err(|error| format!("could not read generated PTX {}: {error}", path.display()))
+}
+
+/// Print one generated PTX artifact.
+pub(super) fn print_ptx_artifact(path: &Path) -> Result<(), String> {
+    let content = read_ptx_artifact(path)?;
+
+    let name = path
+        .file_name()
+        .map(|name| name.to_string_lossy().into_owned())
+        .unwrap_or_else(|| path.display().to_string());
+
+    println!();
+    println!("=========================================");
+    println!("PTX ({name})");
+    println!("=========================================");
+    print!("{content}");
+
+    if !content.ends_with('\n') {
+        println!();
+    }
+
+    Ok(())
+}
+
+/// Path to the NVVM IR (`.ll`) the backend emits for `example`. Named after the
+/// Cargo-normalized crate stem, so a hyphenated example resolves to the
+/// underscore-spelled file the build actually wrote. Route `emit-ltoir` reads
+/// through here rather than deriving the name from the raw example.
+pub(super) fn emitted_ll_path(example_dir: &Path, example: &str) -> PathBuf {
+    example_dir.join(format!("{}.ll", artifact_stem(example)))
+}
+
+/// Default LTOIR output path for `example` when no explicit `--output` is given.
+/// Uses the same Cargo-normalized crate stem as [`emitted_ll_path`] so reads and
+/// writes agree on hyphenated examples.
+pub(super) fn default_ltoir_path(example_dir: &Path, example: &str) -> PathBuf {
+    example_dir.join(format!("{}.ltoir", artifact_stem(example)))
+}
+
+pub(super) const GENERATED_ARTIFACT_SUFFIXES: &[&str] = &[
+    "ptx",
+    "ll",
+    "opt.ll",
+    "ltoir",
+    "cubin",
+    "cubin.tmp",
+    "cubin.identity",
+    "ptx.identity",
+    "target",
+    "options",
+    "cubin.target",
+];
+
+pub(super) fn generated_artifact_paths(project_dir: &Path, package_name: &str) -> Vec<PathBuf> {
+    let stem = artifact_stem(package_name);
+
+    GENERATED_ARTIFACT_SUFFIXES
+        .iter()
+        .map(|suffix| project_dir.join(format!("{stem}.{suffix}")))
+        .collect()
+}
+
+/// Remove stale generated artifacts (`.ptx`, `.ll`, `.ltoir`, `.cubin`) from a
+/// previous run so we can verify the build produces fresh output.
+pub(super) fn clean_generated_files(example_dir: &Path, example: &str) {
+    for file in generated_artifact_paths(example_dir, example) {
+        if file.exists() {
+            let _ = std::fs::remove_file(file);
+        }
+    }
+}
+
+/// Human-readable label for the selected output format.
+pub(super) fn format_label(emit_nvvm_ir: bool) -> &'static str {
+    if emit_nvvm_ir { "NVVM IR" } else { "PTX" }
+}
+
+/// Print generated artifacts (LLVM IR or PTX) to stdout after a pipeline build.
+pub(super) fn show_generated_artifacts(example_dir: &Path, example: &str) {
+    let stem = artifact_stem(example);
+    let ll_file = example_dir.join(format!("{}.ll", stem));
+    let ptx_file = example_dir.join(format!("{}.ptx", stem));
+
+    if ll_file.exists() {
+        println!();
+        println!("=========================================");
+        println!("LLVM IR ({}.ll)", stem);
+        println!("=========================================");
+        if let Ok(content) = std::fs::read_to_string(&ll_file) {
+            println!("{}", content);
+        }
+    }
+
+    if ptx_file.exists() {
+        println!();
+        println!("=========================================");
+        println!("PTX ({}.ptx)", stem);
+        println!("=========================================");
+        if let Ok(content) = std::fs::read_to_string(&ptx_file) {
+            println!("{}", content);
+        }
+    }
+}
diff --git a/crates/cargo-oxide/src/commands/build_run.rs b/crates/cargo-oxide/src/commands/build_run.rs
new file mode 100644
index 0000000000..8d1c6548b3
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/build_run.rs
@@ -0,0 +1,472 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::process::Command;
+
+use super::*;
+
+// =============================================================================
+// Run command
+// =============================================================================
+
+/// Build and run an example with the custom codegen backend.
+///
+/// Cleans stale artifacts, sets encoded rustc flags to point at the backend `.so`,
+/// and invokes `cargo run --release` from the example directory. Environment
+/// variables control output format (PTX / NVVM IR) and verbosity. Trailing
+/// `app_args` are forwarded to the example binary after `--`.
+#[allow(clippy::too_many_arguments)]
+pub fn codegen_run(
+    ctx: &Context,
+    example: &str,
+    verbose: bool,
+    emit_nvvm_ir: bool,
+    arch: Option<&str>,
+    features: Option<&str>,
+    device_features: Option<&str>,
+    bin: Option<&str>,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+    materialize_cubin: bool,
+    app_args: &[String],
+) {
+    let example_dir = if ctx.is_workspace {
+        resolve_example_dir(ctx, example)
+    } else {
+        ctx.workspace_root.clone()
+    };
+
+    let interop = load_interop_config(&example_dir);
+
+    let output_format = format_label(emit_nvvm_ir);
+    let target_arch = configured_arch(ctx, arch);
+    let materialization = prepare_materialization(ctx, materialize_cubin, arch, emit_nvvm_ir);
+    // Target precedence for `cargo oxide run` (highest first):
+    //   1. --arch <sm_XX>            explicit user override   -> CUDA_OXIDE_TARGET
+    //   2. CUDA_OXIDE_TARGET=<sm_XX> explicit env override (from the parent)
+    //   3. detected GPU arch (via nvidia-smi) -> CUDA_OXIDE_DEVICE_ARCH (a hint)
+    //   4. backend feature-based default (`select_target` in mir-importer)
+    //
+    // Slot 3 is a HINT, not an override: the backend builds for the detected
+    // GPU only when that GPU can run the kernel. If the kernel needs a newer
+    // arch (tcgen05 needs sm_100a even on a consumer sm_120 GPU), the backend
+    // builds for the required arch and the module simply skips at load time.
+    // We only detect for `run`, not `build`/`pipeline`: `run` loads the cubin
+    // on the local GPU, whereas those may legitimately cross-compile for
+    // another machine.
+    let detected_device_arch =
+        detect_run_target_arch(target_arch, emit_nvvm_ir || materialization.enabled());
+
+    if let Some(interop) = interop.filter(|config| !config.device_crates.is_empty()) {
+        codegen_run_interop(
+            ctx,
+            example,
+            &example_dir,
+            &interop,
+            verbose,
+            emit_nvvm_ir,
+            target_arch,
+            detected_device_arch.as_deref(),
+            features,
+            device_features,
+            bin,
+            no_fmad,
+            unchecked_indexing,
+            &materialization,
+            app_args,
+        );
+        return;
+    }
+    if device_features.is_some() {
+        eprintln!("Error: --device-features requires metadata-declared interop device crates.");
+        std::process::exit(2);
+    }
+
+    clean_generated_files(&example_dir, example);
+
+    println!("=========================================");
+    println!("RUSTC-CODEGEN-CUDA: {}", example);
+    println!("=========================================");
+    println!();
+    if materialization.enabled() {
+        println!("Output format: materialized cubin");
+        println!(
+            "Target arch: {}",
+            configured_arch_label(ctx, arch)
+                .expect("materialization requires a configured architecture")
+        );
+        println!();
+    } else if emit_nvvm_ir {
+        println!("Output format: {}", output_format);
+        println!(
+            "Target arch: {}",
+            configured_arch_label(ctx, arch)
+                .expect("--emit-nvvm-ir requires a configured architecture")
+        );
+        println!();
+    } else if let Some(dev) = detected_device_arch.as_deref() {
+        // Surface the detected GPU so it isn't silent magic. It is a hint, not
+        // a hard target: the backend builds for it unless a kernel needs a
+        // newer arch (e.g. tcgen05 forces sm_100a even on a consumer sm_120
+        // GPU), so the final PTX target may differ.
+        println!("Detected GPU arch: {dev} (via nvidia-smi)");
+        println!();
+    }
+    println!("This is the proper cargo workflow:");
+    println!("  CARGO_ENCODED_RUSTFLAGS=<cuda-oxide flags> cargo run");
+    println!();
+
+    touch_main_rs(&example_dir);
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["run", "--release"]).current_dir(&example_dir);
+
+    if let Some(bin) = bin {
+        cmd.args(["--bin", bin]);
+    }
+    if let Some(features) = features {
+        cmd.args(["--features", features]);
+    }
+    if !app_args.is_empty() {
+        cmd.arg("--").args(app_args);
+    }
+
+    apply_common_codegen_env(
+        &mut cmd,
+        ctx,
+        verbose,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+    );
+    let fingerprint = standard_codegen_fingerprint(
+        ctx,
+        verbose,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+        emit_nvvm_ir,
+        target_arch,
+        detected_device_arch.as_deref(),
+        &materialization,
+    );
+    apply_codegen_configuration_or_exit(
+        &mut cmd,
+        ctx,
+        CodegenProfilePolicy::ReleaseLike,
+        &[],
+        &fingerprint,
+    );
+    apply_output_mode(&mut cmd, emit_nvvm_ir, target_arch, &materialization);
+    apply_device_arch_hint(&mut cmd, target_arch, detected_device_arch.as_deref());
+
+    if let Some(bin) = bin {
+        println!("Building and running {} (bin: {})...", example, bin);
+    } else {
+        println!("Building and running {}...", example);
+    }
+    println!();
+
+    let status = cmd.status().expect("Failed to run cargo");
+    if !status.success() {
+        eprintln!("\nFailed with exit code: {:?}", status.code());
+        std::process::exit(status.code().unwrap_or(1));
+    }
+}
+
+// =============================================================================
+// Sanitize command
+// =============================================================================
+
+/// Build an example and run the produced host binary under NVIDIA Compute
+/// Sanitizer.
+#[allow(clippy::too_many_arguments)]
+pub fn codegen_sanitize(
+    ctx: &Context,
+    example: &str,
+    tool: &str,
+    sanitizer_args: &[String],
+    application_args: &[String],
+    verbose: bool,
+    arch: Option<&str>,
+    features: Option<&str>,
+    bin: Option<&str>,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+    materialize_cubin: bool,
+) {
+    let example_dir = if ctx.is_workspace {
+        resolve_example_dir(ctx, example)
+    } else {
+        ctx.workspace_root.clone()
+    };
+
+    let interop = load_interop_config(&example_dir);
+    let target_arch = configured_arch(ctx, arch);
+    let materialization = prepare_materialization(ctx, materialize_cubin, arch, false);
+    let detected_device_arch = detect_run_target_arch(target_arch, materialization.enabled());
+
+    if let Some(interop) = interop.filter(|config| !config.device_crates.is_empty()) {
+        reject_interop_output_mode(false, &materialization);
+        println!("=========================================");
+        println!("RUSTC-CODEGEN-CUDA SANITIZE INTEROP: {}", example);
+        println!("=========================================");
+        if let Some(kind) = &interop.kind {
+            println!("Interop kind: {}", kind);
+        }
+        if let Some(dev) = detected_device_arch.as_deref() {
+            println!("Detected GPU arch: {dev} (via nvidia-smi)");
+        }
+        println!("Compute Sanitizer tool: {tool}");
+        println!();
+
+        build_interop_device_crates(
+            ctx,
+            &example_dir,
+            &interop,
+            verbose,
+            target_arch,
+            detected_device_arch.as_deref(),
+            None,
+            InteropDeviceBuildOptions {
+                no_fmad,
+                unchecked_indexing,
+                sanitizer_line_tables: true,
+            },
+            &materialization,
+        );
+        let binary = build_host_cargo(ctx, example, &example_dir, features, bin, verbose);
+        run_compute_sanitizer(
+            ctx,
+            &example_dir,
+            tool,
+            sanitizer_args,
+            application_args,
+            &binary,
+        );
+        return;
+    }
+
+    clean_generated_files(&example_dir, example);
+
+    println!("=========================================");
+    println!("RUSTC-CODEGEN-CUDA SANITIZE: {}", example);
+    println!("=========================================");
+    if let Some(dev) = detected_device_arch.as_deref() {
+        println!("Detected GPU arch: {dev} (via nvidia-smi)");
+    }
+    println!("Compute Sanitizer tool: {tool}");
+    println!();
+
+    touch_main_rs(&example_dir);
+    let binary = codegen_build_host_binary(
+        ctx,
+        example,
+        &example_dir,
+        verbose,
+        target_arch,
+        detected_device_arch.as_deref(),
+        features,
+        bin,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+        &materialization,
+    );
+    run_compute_sanitizer(
+        ctx,
+        &example_dir,
+        tool,
+        sanitizer_args,
+        application_args,
+        &binary,
+    );
+}
+
+// =============================================================================
+// Build command (compile only, don't run)
+// =============================================================================
+
+/// Compile an example without running it.
+///
+/// Same as [`codegen_run`] but uses `cargo build --release` instead of
+/// `cargo run`. Useful for cross-compilation or when the target hardware
+/// (e.g., Blackwell tensor cores) isn't available on the build machine.
+#[allow(clippy::too_many_arguments)]
+pub fn codegen_build(
+    ctx: &Context,
+    example: &str,
+    verbose: bool,
+    emit_nvvm_ir: bool,
+    arch: Option<&str>,
+    features: Option<&str>,
+    device_features: Option<&str>,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+    materialize_cubin: bool,
+) {
+    let target_arch = configured_arch(ctx, arch);
+    let materialization = prepare_materialization(ctx, materialize_cubin, arch, emit_nvvm_ir);
+    let example_dir = if ctx.is_workspace {
+        resolve_example_dir(ctx, example)
+    } else {
+        ctx.workspace_root.clone()
+    };
+
+    if let Some(interop) =
+        load_interop_config(&example_dir).filter(|config| !config.device_crates.is_empty())
+    {
+        codegen_build_interop(
+            ctx,
+            example,
+            &example_dir,
+            &interop,
+            verbose,
+            emit_nvvm_ir,
+            target_arch,
+            features,
+            device_features,
+            no_fmad,
+            unchecked_indexing,
+            &materialization,
+        );
+        return;
+    }
+    if device_features.is_some() {
+        eprintln!("Error: --device-features requires metadata-declared interop device crates.");
+        std::process::exit(2);
+    }
+
+    clean_generated_files(&example_dir, example);
+
+    println!("=========================================");
+    println!("RUSTC-CODEGEN-CUDA BUILD: {}", example);
+    println!("=========================================");
+    println!();
+
+    touch_main_rs(&example_dir);
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release"]).current_dir(&example_dir);
+
+    if let Some(features) = features {
+        cmd.args(["--features", features]);
+    }
+
+    apply_common_codegen_env(
+        &mut cmd,
+        ctx,
+        verbose,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+    );
+    let fingerprint = standard_codegen_fingerprint(
+        ctx,
+        verbose,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+        emit_nvvm_ir,
+        target_arch,
+        None,
+        &materialization,
+    );
+    apply_codegen_configuration_or_exit(
+        &mut cmd,
+        ctx,
+        CodegenProfilePolicy::ReleaseLike,
+        &[],
+        &fingerprint,
+    );
+    apply_output_mode(&mut cmd, emit_nvvm_ir, target_arch, &materialization);
+
+    println!("Building {}...", example);
+    println!();
+
+    let status = cmd.status().expect("Failed to run cargo");
+    if !status.success() {
+        eprintln!("\nBuild failed with exit code: {:?}", status.code());
+        std::process::exit(status.code().unwrap_or(1));
+    }
+}
+
+// =============================================================================
+// Inspect command
+// =============================================================================
+
+/// Build an example as PTX and print the generated artifact.
+#[allow(clippy::too_many_arguments)]
+pub fn codegen_inspect_ptx(
+    ctx: &Context,
+    example: &str,
+    arch: Option<&str>,
+    features: Option<&str>,
+    verbose: bool,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+) {
+    let materialization_enabled = materialization_requested(ctx, false).unwrap_or_else(|error| {
+        eprintln!("Error: {error}");
+        std::process::exit(2);
+    });
+
+    if materialization_enabled {
+        eprintln!("Error: inspect requires PTX output, but {MATERIALIZE_ENV} is enabled");
+        std::process::exit(2);
+    }
+
+    let nvvm_ir_enabled = nvvm_ir_requested(ctx).unwrap_or_else(|error| {
+        eprintln!("Error: {error}");
+        std::process::exit(2);
+    });
+
+    if nvvm_ir_enabled {
+        eprintln!("Error: inspect requires PTX output, but CUDA_OXIDE_EMIT_NVVM_IR is enabled");
+        std::process::exit(2);
+    }
+
+    let example_dir = if ctx.is_workspace {
+        resolve_example_dir(ctx, example)
+    } else {
+        ctx.workspace_root.clone()
+    };
+    if load_interop_config(&example_dir).is_some_and(|interop| {
+        interop
+            .device_crates
+            .iter()
+            .any(|device_crate| device_crate.artifact_kind != InteropArtifactKind::Ptx)
+    }) {
+        eprintln!(
+            "Error: inspect requires PTX output, but metadata declares a non-PTX device artifact."
+        );
+        std::process::exit(2);
+    }
+
+    codegen_build(
+        ctx,
+        example,
+        verbose,
+        false,
+        arch,
+        features,
+        None,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+        false,
+    );
+
+    for path in ptx_artifact_paths(&example_dir, example) {
+        print_ptx_artifact(&path).unwrap_or_else(|error| {
+            eprintln!("Error: {error}");
+            std::process::exit(1);
+        });
+    }
+}
diff --git a/crates/cargo-oxide/src/commands/clean.rs b/crates/cargo-oxide/src/commands/clean.rs
new file mode 100644
index 0000000000..1e6683ddc0
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/clean.rs
@@ -0,0 +1,234 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::path::Path;
+
+use super::*;
+
+// =============================================================================
+// Clean command
+// =============================================================================
+
+pub fn clean(ctx: &Context) {
+    match clean_context(ctx) {
+        Ok(summary) if summary.removed_directories == 0 && summary.removed_files == 0 => {
+            println!("Nothing to clean.");
+        }
+        Ok(summary) => {
+            println!(
+                "Removed {} directories and {} generated artifacts.",
+                summary.removed_directories, summary.removed_files
+            );
+        }
+        Err(error) => {
+            eprintln!("Error: {error}");
+            std::process::exit(1);
+        }
+    }
+}
+
+#[derive(Debug, Default, Eq, PartialEq)]
+pub(super) struct CleanSummary {
+    pub(super) removed_directories: usize,
+    pub(super) removed_files: usize,
+}
+
+pub(super) fn clean_context(ctx: &Context) -> Result<CleanSummary, String> {
+    let mut summary = CleanSummary::default();
+
+    if ctx.is_workspace {
+        clean_workspace(ctx, &mut summary)?;
+    } else {
+        clean_standalone_project(&ctx.workspace_root, &mut summary)?;
+    }
+
+    Ok(summary)
+}
+
+fn clean_standalone_project(project_dir: &Path, summary: &mut CleanSummary) -> Result<(), String> {
+    let manifest_path = project_dir.join("Cargo.toml");
+    let package_name = package_name_for_clean(&manifest_path)?;
+
+    if remove_local_target(project_dir)? {
+        summary.removed_directories += 1;
+    }
+
+    summary.removed_files += remove_generated_artifacts(project_dir, &package_name)?;
+
+    Ok(())
+}
+
+fn clean_workspace(ctx: &Context, summary: &mut CleanSummary) -> Result<(), String> {
+    if remove_local_target(&ctx.workspace_root)? {
+        summary.removed_directories += 1;
+    }
+
+    if remove_local_target(&ctx.codegen_crate)? {
+        summary.removed_directories += 1;
+    }
+
+    let entries = std::fs::read_dir(&ctx.examples_dir).map_err(|error| {
+        format!(
+            "could not read examples directory {}: {error}",
+            ctx.examples_dir.display()
+        )
+    })?;
+
+    let mut example_dirs = Vec::new();
+
+    for entry in entries {
+        let entry = entry.map_err(|error| {
+            format!(
+                "could not read an entry in {}: {error}",
+                ctx.examples_dir.display()
+            )
+        })?;
+
+        let file_type = entry.file_type().map_err(|error| {
+            format!(
+                "could not inspect example entry {}: {error}",
+                entry.path().display()
+            )
+        })?;
+
+        if !file_type.is_dir() {
+            continue;
+        }
+
+        let example_dir = entry.path();
+        if example_dir.join("Cargo.toml").is_file() {
+            example_dirs.push(example_dir);
+        }
+    }
+
+    example_dirs.sort();
+
+    for example_dir in example_dirs {
+        clean_example(&example_dir, summary)?;
+    }
+
+    Ok(())
+}
+
+fn clean_example(example_dir: &Path, summary: &mut CleanSummary) -> Result<(), String> {
+    let manifest_path = example_dir.join("Cargo.toml");
+    let package_name = package_name_for_clean(&manifest_path)?;
+
+    if remove_local_target(example_dir)? {
+        summary.removed_directories += 1;
+    }
+
+    summary.removed_files += remove_generated_artifacts(example_dir, &package_name)?;
+
+    Ok(())
+}
+
+fn package_name_for_clean(manifest_path: &Path) -> Result<String, String> {
+    let source = std::fs::read_to_string(manifest_path).map_err(|error| {
+        format!(
+            "could not read manifest {}: {error}",
+            manifest_path.display()
+        )
+    })?;
+
+    let document: toml::Value = toml::from_str(&source).map_err(|error| {
+        format!(
+            "could not parse manifest {}: {error}",
+            manifest_path.display()
+        )
+    })?;
+
+    document
+        .get("package")
+        .and_then(|value| value.get("name"))
+        .and_then(|value| value.as_str())
+        .map(str::to_owned)
+        .ok_or_else(|| {
+            format!(
+                "manifest {} is missing package.name",
+                manifest_path.display()
+            )
+        })
+}
+
+fn remove_local_target(project_dir: &Path) -> Result<bool, String> {
+    let target_dir = project_dir.join("target");
+
+    let metadata = match std::fs::symlink_metadata(&target_dir) {
+        Ok(metadata) => metadata,
+        Err(error) if error.kind() == std::io::ErrorKind::NotFound => {
+            return Ok(false);
+        }
+        Err(error) => {
+            return Err(format!(
+                "could not inspect {}: {error}",
+                target_dir.display()
+            ));
+        }
+    };
+
+    if metadata.file_type().is_symlink() {
+        return Err(format!(
+            "refusing to remove symlinked target directory {}",
+            target_dir.display()
+        ));
+    }
+
+    if !metadata.is_dir() {
+        return Err(format!(
+            "expected {} to be a directory",
+            target_dir.display()
+        ));
+    }
+
+    std::fs::remove_dir_all(&target_dir).map_err(|error| {
+        format!(
+            "could not remove target directory {}: {error}",
+            target_dir.display()
+        )
+    })?;
+
+    println!("Removed {}", target_dir.display());
+
+    Ok(true)
+}
+
+fn remove_generated_artifacts(project_dir: &Path, package_name: &str) -> Result<usize, String> {
+    let mut removed = 0;
+
+    for path in generated_artifact_paths(project_dir, package_name) {
+        let metadata = match std::fs::symlink_metadata(&path) {
+            Ok(metadata) => metadata,
+            Err(error) if error.kind() == std::io::ErrorKind::NotFound => {
+                continue;
+            }
+            Err(error) => {
+                return Err(format!("could not inspect {}: {error}", path.display()));
+            }
+        };
+
+        if metadata.file_type().is_symlink() {
+            return Err(format!(
+                "refusing to remove symlinked generated artifact {}",
+                path.display()
+            ));
+        }
+
+        if !metadata.is_file() {
+            return Err(format!(
+                "expected generated artifact {} to be a file",
+                path.display()
+            ));
+        }
+
+        std::fs::remove_file(&path)
+            .map_err(|error| format!("could not remove {}: {error}", path.display()))?;
+
+        println!("Removed {}", path.display());
+        removed += 1;
+    }
+
+    Ok(removed)
+}
diff --git a/crates/cargo-oxide/src/commands/codegen_env.rs b/crates/cargo-oxide/src/commands/codegen_env.rs
new file mode 100644
index 0000000000..d4fe2fe2f4
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/codegen_env.rs
@@ -0,0 +1,641 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::backend;
+use std::path::Path;
+use std::process::Command;
+
+use super::*;
+
+pub(super) const ENCODED_RUSTFLAGS_SEPARATOR: char = '\u{1f}';
+
+/// Profile-related rustc flags owned by cuda-oxide.
+///
+/// Backend selection and MIR/symbol invariants are always applied separately.
+/// `CargoSelected` deliberately adds no optimization, assertion, or debug-info
+/// flags so Cargo's chosen profile remains authoritative.
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub(super) enum CodegenProfilePolicy {
+    CargoSelected,
+    ReleaseLike,
+    ReleaseLikeWithDebugInfo,
+}
+
+/// Construct boundary-preserving rustc flags for Cargo.
+///
+/// `RUSTFLAGS` is whitespace-split by Cargo, which corrupts a single flag
+/// containing spaces. `CARGO_ENCODED_RUSTFLAGS` uses unit separators and keeps
+/// every configured array element and `--device-cfg` value intact.
+fn build_encoded_rustflags(
+    ctx: &Context,
+    profile: CodegenProfilePolicy,
+    device_cfgs: &[String],
+) -> String {
+    let existing_encoded = std::env::var("CARGO_ENCODED_RUSTFLAGS").ok();
+    let existing = std::env::var("RUSTFLAGS").ok();
+    let mut explicit_rustflags = Vec::new();
+    for cfg in device_cfgs {
+        explicit_rustflags.push("--cfg".to_string());
+        explicit_rustflags.push(cfg.clone());
+    }
+    build_encoded_rustflags_with_existing(
+        &ctx.backend_so,
+        profile,
+        &ctx.config.extra_rustflags,
+        &explicit_rustflags,
+        existing_encoded.as_deref(),
+        existing.as_deref(),
+    )
+}
+
+pub(super) fn build_encoded_rustflags_with_existing(
+    backend_so: &Path,
+    profile: CodegenProfilePolicy,
+    configured_rustflags: &[String],
+    explicit_rustflags: &[String],
+    existing_encoded_rustflags: Option<&str>,
+    existing_rustflags: Option<&str>,
+) -> String {
+    // Project flags are defaults, inherited flags are user overrides, and
+    // explicit wrapper flags are stronger. cuda-oxide's compiler invariants
+    // come last because rustc resolves repeated -C/-Z options last-one-wins.
+    let mut flags = configured_rustflags.to_vec();
+
+    if let Some(existing) = existing_encoded_rustflags {
+        flags.extend(
+            existing
+                .split(ENCODED_RUSTFLAGS_SEPARATOR)
+                .filter(|flag| !flag.is_empty())
+                .map(str::to_string),
+        );
+    } else if let Some(existing) = existing_rustflags {
+        // Match Cargo's legacy RUSTFLAGS behavior when converting it to the
+        // encoded representation.
+        flags.extend(existing.split_whitespace().map(str::to_string));
+    }
+    flags.extend(explicit_rustflags.iter().cloned());
+    strip_wrapper_owned_codegen_cfgs(&mut flags);
+    flags.push(format!("-Zcodegen-backend={}", backend_so.display()));
+    if matches!(
+        profile,
+        CodegenProfilePolicy::ReleaseLike | CodegenProfilePolicy::ReleaseLikeWithDebugInfo
+    ) {
+        flags.extend([
+            "-Copt-level=3".to_string(),
+            "-Cdebug-assertions=off".to_string(),
+        ]);
+    }
+    flags.extend([
+        "-Zmir-enable-passes=-JumpThreading".to_string(),
+        // Device codegen is whole-program: `collector` walks the call graph from
+        // each `#[kernel]` and must emit every reachable dependency function into
+        // one module. rustc encodes cross-crate MIR only for `#[inline]`/generic
+        // items, so a non-`#[inline]`, non-generic dependency function that cannot
+        // be inlined away (canonically: a recursive one) would be *called* but
+        // never *defined* -> LLVM verification fails with "Symbol <crate>__<fn>
+        // not found". Encode all MIR so any reachable dependency function is
+        // device-compilable. This applies build-wide (like the other required
+        // flags), so it also encodes MIR for host-only deps — an intentional,
+        // interim trade (rmeta size) until a surgical device-dep-scoped or
+        // per-crate device-link path lands. It matches the established approach
+        // for whole-program-MIR tools (e.g. Miri).
+        "-Zalways-encode-mir".to_string(),
+        "-Csymbol-mangling-version=v0".to_string(),
+    ]);
+    if profile == CodegenProfilePolicy::ReleaseLikeWithDebugInfo {
+        flags.push("-Cdebuginfo=2".to_string());
+    }
+    flags.join(&ENCODED_RUSTFLAGS_SEPARATOR.to_string())
+}
+
+fn strip_wrapper_owned_codegen_cfgs(flags: &mut Vec<String>) {
+    fn is_wrapper_owned_cfg(value: &str) -> bool {
+        [
+            LEGACY_CODEGEN_FINGERPRINT_CFG,
+            LEGACY_MATERIALIZER_PROVENANCE_CFG,
+        ]
+        .iter()
+        .any(|name| {
+            value
+                .strip_prefix(name)
+                .is_some_and(|suffix| suffix.is_empty() || suffix.starts_with('='))
+        })
+    }
+
+    let mut retained = Vec::with_capacity(flags.len());
+    let mut index = 0;
+    while index < flags.len() {
+        let flag = &flags[index];
+        if flag == "--cfg"
+            && flags
+                .get(index + 1)
+                .is_some_and(|value| is_wrapper_owned_cfg(value))
+        {
+            index += 2;
+            continue;
+        }
+        if flag
+            .strip_prefix("--cfg=")
+            .is_some_and(is_wrapper_owned_cfg)
+        {
+            index += 1;
+            continue;
+        }
+        retained.push(flag.clone());
+        index += 1;
+    }
+    *flags = retained;
+}
+
+fn command_requests_full_device_debug_with_env(
+    cmd: &Command,
+    inherited_debug: Option<&str>,
+) -> bool {
+    let effective_debug = match cmd
+        .get_envs()
+        .find(|(name, _)| *name == std::ffi::OsStr::new("CUDA_OXIDE_DEBUG"))
+    {
+        Some((_, Some(value))) => Some(value.to_string_lossy().into_owned()),
+        Some((_, None)) => None,
+        None => inherited_debug.map(str::to_owned),
+    };
+
+    // Shared alias table: the codegen backend parses `CUDA_OXIDE_DEBUG`
+    // with the same function, so every spelling the backend treats as
+    // full debug (including `2`) also disables MIR optimization here.
+    effective_debug.is_some_and(|value| {
+        cuda_artifact_finalizer::DebugPolicy::parse_env_override(&value)
+            == Some(cuda_artifact_finalizer::DebugPolicy::Full)
+    })
+}
+
+pub(super) fn append_full_debug_mir_rustflag(
+    encoded: &mut String,
+    cmd: &Command,
+    inherited_debug: Option<&str>,
+) {
+    if !command_requests_full_device_debug_with_env(cmd, inherited_debug) {
+        return;
+    }
+    if !encoded.is_empty() {
+        encoded.push(ENCODED_RUSTFLAGS_SEPARATOR);
+    }
+    encoded.push_str("-Zmir-opt-level=0");
+}
+
+fn apply_codegen_rustflags(
+    cmd: &mut Command,
+    ctx: &Context,
+    profile: CodegenProfilePolicy,
+    device_cfgs: &[String],
+) {
+    let mut encoded = build_encoded_rustflags(ctx, profile, device_cfgs);
+    let inherited_debug = std::env::var("CUDA_OXIDE_DEBUG").ok();
+    append_full_debug_mir_rustflag(&mut encoded, cmd, inherited_debug.as_deref());
+
+    cmd.env("CARGO_ENCODED_RUSTFLAGS", encoded)
+        .env_remove("RUSTFLAGS");
+}
+
+/// Apply the two deliberately different Cargo cache boundaries:
+///
+/// - the exact backend binary is global because it compiles every crate;
+/// - mode/architecture/tool settings are an env dependency recorded only by
+///   CUDA macros in crates that can own or instantiate device code.
+pub(super) fn apply_codegen_configuration(
+    cmd: &mut Command,
+    ctx: &Context,
+    profile: CodegenProfilePolicy,
+    user_device_cfgs: &[String],
+    codegen_fingerprint: &str,
+) -> Result<(), String> {
+    let backend_digest = backend_artifact_digest(&ctx.backend_so)?;
+    let mut global_cfgs = Vec::with_capacity(user_device_cfgs.len() + 1);
+    global_cfgs.push(format!("{BACKEND_IDENTITY_CFG}=\"{backend_digest}\""));
+    global_cfgs.extend(user_device_cfgs.iter().cloned());
+
+    apply_codegen_rustflags(cmd, ctx, profile, &global_cfgs);
+    cmd.env(CODEGEN_FINGERPRINT_ENV, codegen_fingerprint);
+    Ok(())
+}
+
+pub(super) fn apply_codegen_configuration_or_exit(
+    cmd: &mut Command,
+    ctx: &Context,
+    profile: CodegenProfilePolicy,
+    user_device_cfgs: &[String],
+    codegen_fingerprint: &str,
+) {
+    apply_codegen_configuration(cmd, ctx, profile, user_device_cfgs, codegen_fingerprint)
+        .unwrap_or_else(|error| {
+            eprintln!("Error: {error}");
+            std::process::exit(1);
+        });
+}
+
+/// Set environment variables for the codegen backend.
+///
+/// `arch` is an explicit pin (`--arch`); it becomes `CUDA_OXIDE_TARGET`, the
+/// hard override the backend honors as-is. The auto-detected GPU arch is *not*
+/// routed here -- see [`apply_device_arch_hint`].
+pub(super) fn apply_output_mode(
+    cmd: &mut Command,
+    emit_nvvm_ir: bool,
+    arch: Option<&str>,
+    materialization: &MaterializationMode,
+) {
+    if let Some(target_arch) = arch {
+        cmd.env("CUDA_OXIDE_TARGET", target_arch);
+    }
+    if emit_nvvm_ir || materialization.enabled() {
+        cmd.env("CUDA_OXIDE_EMIT_NVVM_IR", "1");
+    }
+    materialization.apply(cmd);
+}
+
+pub(super) fn configured_arch<'a>(ctx: &'a Context, cli_arch: Option<&'a str>) -> Option<&'a str> {
+    if cli_arch.is_some() || std::env::var("CUDA_OXIDE_TARGET").is_ok() {
+        cli_arch
+    } else {
+        ctx.config
+            .default_arch
+            .as_deref()
+            .or_else(|| project_config_env(ctx, "CUDA_OXIDE_TARGET"))
+    }
+}
+
+pub(super) fn configured_arch_label(ctx: &Context, cli_arch: Option<&str>) -> Option<String> {
+    cli_arch
+        .map(str::to_string)
+        .or_else(|| std::env::var("CUDA_OXIDE_TARGET").ok())
+        .or_else(|| ctx.config.default_arch.clone())
+        .or_else(|| project_config_env(ctx, "CUDA_OXIDE_TARGET").map(str::to_string))
+}
+
+pub fn has_configured_arch(ctx: &Context, cli_arch: Option<&str>) -> bool {
+    cli_arch.is_some()
+        || std::env::var("CUDA_OXIDE_TARGET").is_ok()
+        || ctx.config.default_arch.is_some()
+        || project_config_env(ctx, "CUDA_OXIDE_TARGET").is_some()
+}
+
+pub(super) fn apply_config_env(cmd: &mut Command, ctx: &Context) {
+    for (key, value) in &ctx.config.env {
+        if matches!(key.as_str(), "RUSTFLAGS" | "CARGO_ENCODED_RUSTFLAGS") {
+            continue;
+        }
+        // Project values are defaults. An explicitly inherited environment is
+        // stronger, and command-specific CLI/internal settings are applied
+        // after this helper and are stronger still.
+        if std::env::var_os(key).is_none() {
+            cmd.env(key, value);
+        }
+    }
+}
+
+pub(super) fn apply_common_codegen_env(
+    cmd: &mut Command,
+    ctx: &Context,
+    verbose: bool,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+) {
+    apply_config_env(cmd, ctx);
+    if verbose {
+        cmd.env("CUDA_OXIDE_VERBOSE", "1");
+    }
+    if no_fmad {
+        cmd.env("CUDA_OXIDE_NO_FMA", "1");
+    }
+    if unchecked_indexing {
+        cmd.env("CUDA_OXIDE_UNCHECKED_INDEXING", "1");
+    }
+    // An explicit flag outranks an ambient `CUDA_OXIDE_DEBUG`, matching how
+    // `--no-fmad` outranks `CUDA_OXIDE_NO_FMA`. `DeviceDebug::Off` exports
+    // nothing rather than `off`, so omitting the flag cannot silently cancel a
+    // debug level the environment or project config already asked for.
+    if let Some(level) = device_debug.env_value() {
+        cmd.env("CUDA_OXIDE_DEBUG", level);
+    }
+    apply_ld_library_path(cmd, ctx);
+}
+
+/// Give Compute Sanitizer source line attribution without disabling normal
+/// device optimization. An explicit process or project setting remains
+/// authoritative, including an intentional `CUDA_OXIDE_DEBUG=off`. So does an
+/// explicit `--lineinfo` / `--device-debug` flag: `apply_common_codegen_env`
+/// has already exported its level onto `cmd`, and the default must not
+/// overwrite it.
+pub(super) fn apply_default_sanitizer_line_tables(
+    cmd: &mut Command,
+    ctx: &Context,
+    device_debug: DeviceDebug,
+) {
+    apply_default_sanitizer_line_tables_with_env(
+        cmd,
+        ctx,
+        std::env::var_os("CUDA_OXIDE_DEBUG").is_some(),
+        device_debug,
+    );
+}
+
+/// `apply_default_sanitizer_line_tables` with the `CUDA_OXIDE_DEBUG` probe
+/// injected.
+///
+/// `env_debug_set` is presence-only, matching the `var_os` check it replaces.
+/// Injected so a unit test can assert the defaulting without an exported
+/// `CUDA_OXIDE_DEBUG` suppressing it. `device_debug` carries the CLI flag:
+/// any level other than [`DeviceDebug::Off`] is an explicit request that
+/// outranks the line-tables default.
+pub(super) fn apply_default_sanitizer_line_tables_with_env(
+    cmd: &mut Command,
+    ctx: &Context,
+    env_debug_set: bool,
+    device_debug: DeviceDebug,
+) {
+    if device_debug == DeviceDebug::Off
+        && !env_debug_set
+        && project_config_env(ctx, "CUDA_OXIDE_DEBUG").is_none()
+    {
+        cmd.env("CUDA_OXIDE_DEBUG", "line-tables");
+    }
+}
+
+pub(super) fn apply_interop_device_codegen_options(
+    cmd: &mut Command,
+    ctx: &Context,
+    verbose: bool,
+    options: InteropDeviceBuildOptions,
+) {
+    apply_interop_device_codegen_options_with_env(
+        cmd,
+        ctx,
+        verbose,
+        options,
+        std::env::var_os("CUDA_OXIDE_DEBUG").is_some(),
+    );
+}
+
+/// `apply_interop_device_codegen_options` with the `CUDA_OXIDE_DEBUG` probe
+/// injected, forwarded to `apply_default_sanitizer_line_tables_with_env`.
+pub(super) fn apply_interop_device_codegen_options_with_env(
+    cmd: &mut Command,
+    ctx: &Context,
+    verbose: bool,
+    options: InteropDeviceBuildOptions,
+    env_debug_set: bool,
+) {
+    apply_common_codegen_env(
+        cmd,
+        ctx,
+        verbose,
+        options.no_fmad,
+        options.unchecked_indexing,
+        DeviceDebug::Off,
+    );
+    if options.sanitizer_line_tables {
+        apply_default_sanitizer_line_tables_with_env(cmd, ctx, env_debug_set, DeviceDebug::Off);
+    }
+}
+
+/// Forward the auto-detected GPU arch as a *hint* via `CUDA_OXIDE_DEVICE_ARCH`.
+///
+/// Unlike `CUDA_OXIDE_TARGET` (a hard override), this is advisory: the backend
+/// builds for the detected GPU only when that GPU can actually run the kernel.
+/// If the kernel needs a newer arch (e.g. tcgen05 / cta_group TMA multicast
+/// need sm_100a, which a consumer sm_120 GPU lacks), the backend builds for the
+/// required arch instead. Skipped when the user pinned `--arch` (that explicit
+/// choice already went to `CUDA_OXIDE_TARGET`).
+pub(super) fn apply_device_arch_hint(
+    cmd: &mut Command,
+    explicit_arch: Option<&str>,
+    detected_device_arch: Option<&str>,
+) {
+    if let (None, Some(dev)) = (explicit_arch, detected_device_arch) {
+        cmd.env("CUDA_OXIDE_DEVICE_ARCH", dev);
+    }
+}
+
+/// Pick a runnable target for `cargo oxide run` when the user has not pinned
+/// one explicitly.
+///
+/// # Precedence
+///
+/// `cargo oxide run` resolves the target architecture in this order, highest
+/// priority first:
+///
+/// 1. `--arch <sm_XX>`            (explicit user override)
+/// 2. `CUDA_OXIDE_TARGET=<sm_XX>` (explicit env override, set in the parent
+///    process before invoking `cargo oxide run`)
+/// 3. **This function**: the compute capability of the first GPU reported by
+///    `nvidia-smi`, forwarded as the `CUDA_OXIDE_DEVICE_ARCH` *hint*. Emits
+///    the arch-specific `sm_XYa` form for cc >= 9.0 (so the backend can lower
+///    WGMMA / tcgen05 / TMA-multicast when the GPU supports them) and the
+///    plain `sm_XY` form for cc < 9.0.
+/// 4. Backend feature-based default (`select_target` in
+///    `mir-importer::pipeline`), which picks the minimum `sm_XX` required by
+///    the IR shape (e.g. `Basic -> sm_80`, `Cluster -> sm_90`, `Tma -> sm_100`).
+///
+/// Slot 3 is advisory: the backend builds for the detected GPU only when that
+/// GPU can run the kernel, otherwise it falls back to slot 4 (the arch the
+/// kernel requires). This function returns `Some(sm_XY[a])` to fill slot 3, or
+/// `None` (falling through to slot 4) when the machine has no usable GPU.
+///
+/// # Why only `run`
+///
+/// `run` immediately loads the generated module on the local GPU and launches
+/// the kernel, so a target older than the local GPU's compute capability is
+/// the only safe default. `build` and `pipeline` may legitimately
+/// cross-compile to a different machine, so they keep the backend's
+/// feature-based default untouched.
+///
+/// # Why this is needed even with the backend default
+///
+/// The backend's `select_target` picks the minimum `sm_XX` the IR requires.
+/// `Basic → sm_80` is a fine *compilation* baseline, but PTX for `sm_80` will
+/// not load on a Turing (`sm_75`) GPU because the JIT refuses
+/// forward-incompatible PTX. Detecting the device CC in `run` keeps the
+/// generated module loadable on the actual hardware that will execute it.
+///
+/// # When this returns `None`
+///
+/// - The user passed `--arch` (slot 1 wins).
+/// - `CUDA_OXIDE_TARGET` is set in the environment (slot 2 wins).
+/// - `--emit-nvvm-ir` is in effect (NVVM IR mode requires explicit `--arch`,
+///   enforced by the CLI parser).
+/// - No CUDA driver / GPU is available on the machine (CI runners without
+///   GPUs, headless build boxes), or `nvidia-smi` is missing or broken. The
+///   caller falls through to slot 4 and the backend's feature-based default
+///   applies.
+pub(super) fn detect_run_target_arch(arch: Option<&str>, emit_nvvm_ir: bool) -> Option<String> {
+    detect_run_target_arch_with_env(
+        arch,
+        emit_nvvm_ir,
+        std::env::var_os("CUDA_OXIDE_TARGET").is_some(),
+    )
+}
+
+/// `detect_run_target_arch` with the `CUDA_OXIDE_TARGET` probe injected.
+///
+/// `env_target_set` is presence-only, matching the `var_os` check it replaces.
+/// Injected so a unit test can exercise the slot-2 skip without exporting the
+/// variable: `set_var` would be a data race against the `vars_os` reads the
+/// fingerprint helpers perform on other test threads.
+pub(super) fn detect_run_target_arch_with_env(
+    arch: Option<&str>,
+    emit_nvvm_ir: bool,
+    env_target_set: bool,
+) -> Option<String> {
+    if arch.is_some() || emit_nvvm_ir || env_target_set {
+        return None;
+    }
+
+    query_device_compute_cap().map(format_sm_arch)
+}
+
+/// Query the compute capability of the first GPU via `nvidia-smi`.
+///
+/// Runs `nvidia-smi --query-gpu=compute_cap --format=csv,noheader` and parses
+/// the first output line. A subprocess probe (rather than the CUDA driver
+/// API) keeps cargo-oxide free of any link-time or dlopen dependency on
+/// `libcuda`, so the subcommand builds and runs on machines with no CUDA
+/// toolkit and no driver; `scripts/smoketest.sh` derives `sm_XX` from
+/// `nvidia-smi` the same way.
+///
+/// Caveat: `nvidia-smi` enumerates GPUs in PCI bus order, while CUDA's
+/// default device order is fastest-first, so on heterogeneous multi-GPU
+/// machines this may describe a different GPU than CUDA device 0. That is
+/// safe because `CUDA_OXIDE_DEVICE_ARCH` is advisory (the backend only
+/// honors a compatible hint) and `--arch` / `CUDA_OXIDE_TARGET` remain hard
+/// overrides.
+fn query_device_compute_cap() -> Option<(u32, u32)> {
+    let output = Command::new("nvidia-smi")
+        .args(["--query-gpu=compute_cap", "--format=csv,noheader"])
+        .output()
+        .ok()
+        .filter(|o| o.status.success())?;
+    parse_compute_cap(&String::from_utf8_lossy(&output.stdout))
+}
+
+/// Parse the first line of `nvidia-smi --query-gpu=compute_cap` output as a
+/// `(major, minor)` compute-capability pair. Returns `None` for anything
+/// that is not shaped `<digits>.<digits>`.
+pub(super) fn parse_compute_cap(stdout: &str) -> Option<(u32, u32)> {
+    parse_compute_cap_field(stdout.lines().next()?)
+}
+
+/// Parse a single `compute_cap` CSV field (e.g. `"12.0"`).
+///
+/// Only the `<digits>.<digits>` shape is accepted: `nvidia-smi` prints its
+/// failure banners ("NVIDIA-SMI has failed ...") to *stdout*, sometimes with
+/// exit status 0, so this shape check is the real gate, not the exit status.
+fn parse_compute_cap_field(field: &str) -> Option<(u32, u32)> {
+    let (major, minor) = field.trim().split_once('.')?;
+    let all_digits = |s: &str| !s.is_empty() && s.bytes().all(|b| b.is_ascii_digit());
+    if !all_digits(major) || !all_digits(minor) {
+        return None;
+    }
+    Some((major.parse().ok()?, minor.parse().ok()?))
+}
+
+/// Query the name, compute capability, and driver version of the first GPU
+/// via `nvidia-smi`, for doctor's driver / GPU report. Same trust rules as
+/// [`query_device_compute_cap`]. The driver version matters for triage:
+/// PTX-JIT and driver-API compatibility bugs are driver-version-specific,
+/// and the bug-report template points reporters at this line.
+pub(super) fn query_gpu_name_cap_and_driver() -> Option<(String, (u32, u32), String)> {
+    let output = Command::new("nvidia-smi")
+        .args([
+            "--query-gpu=name,compute_cap,driver_version",
+            "--format=csv,noheader",
+        ])
+        .output()
+        .ok()
+        .filter(|o| o.status.success())?;
+    parse_gpu_name_cap_and_driver(&String::from_utf8_lossy(&output.stdout))
+}
+
+/// Parse the first line of `nvidia-smi
+/// --query-gpu=name,compute_cap,driver_version` output into the GPU name,
+/// `(major, minor)` pair, and driver version. Splits on the LAST two commas:
+/// GPU names may contain commas in principle, `compute_cap` and
+/// `driver_version` never do.
+pub(super) fn parse_gpu_name_cap_and_driver(stdout: &str) -> Option<(String, (u32, u32), String)> {
+    let line = stdout.lines().next()?;
+    let (rest, driver) = line.rsplit_once(',')?;
+    let (name, cap) = rest.rsplit_once(',')?;
+    Some((
+        name.trim().to_string(),
+        parse_compute_cap_field(cap)?,
+        driver.trim().to_string(),
+    ))
+}
+
+/// Format a `(major, minor)` compute-capability tuple as the `sm_XX` /
+/// `sm_XXX[a]` string the codegen backend expects on `CUDA_OXIDE_TARGET`.
+///
+/// Concatenates without a separator, matching CUDA conventions:
+/// `(7, 5)` → `"sm_75"`, `(12, 0)` → `"sm_120a"`.
+///
+/// # Arch-specific (`a`) suffix
+///
+/// Compute capability ≥ 9.0 always has an arch-specific PTX target (`sm_90a`,
+/// `sm_100a`, `sm_103a`, `sm_120a`, …) that is a strict superset of the plain
+/// target on that chip. The `a` form is what unlocks WGMMA on Hopper and
+/// `tcgen05` / TMA multicast / `cta_group::*` on Blackwell datacenter — and
+/// every chip that reports cc ≥ 9.0 *is* the `a`-variant chip in NVIDIA's
+/// lineup (there is no consumer Hopper, no non-`a` sm_100, and so on).
+///
+/// This helper is only used by [`detect_run_target_arch`] in `cargo oxide
+/// run`, where the local GPU is known exactly and no cross-compile is in
+/// flight. Emitting the `a` form there:
+///
+/// - **No false negatives:** kernels that need `tcgen05` / WGMMA compile and
+///   load on that GPU (was: silent fallback to `sm_100` / `sm_90` and a
+///   `ptxas: 'tcgen05.alloc' not supported on .target 'sm_100'` failure).
+/// - **No false positives:** cc < 9.0 keeps the plain `sm_XY` form, since
+///   there is no `sm_80a` / `sm_86a` / `sm_89a` target in the PTX ISA.
+/// - **Strict superset:** PTX targeting `sm_XYa` accepts every kernel that
+///   would have compiled for plain `sm_XY`; the `a` form only permits
+///   *additional* arch-specific intrinsics.
+pub(super) fn format_sm_arch((major, minor): (u32, u32)) -> String {
+    if major >= 9 {
+        format!("sm_{}{}a", major, minor)
+    } else {
+        format!("sm_{}{}", major, minor)
+    }
+}
+
+fn inherited_or_configured_env(ctx: &Context, key: &str) -> Option<String> {
+    std::env::var(key).ok().or_else(|| {
+        ctx.config
+            .env
+            .iter()
+            .find(|(configured_key, _)| configured_key == key)
+            .map(|(_, value)| value.clone())
+    })
+}
+
+/// Build `LD_LIBRARY_PATH` for the child cargo process.
+///
+/// Includes the rustc sysroot lib (for `librustc_driver.so` etc.), the
+/// libmathdx lib (when `LIBMATHDX_PATH` is set), and any existing
+/// `LD_LIBRARY_PATH` from the parent environment.
+pub(super) fn apply_ld_library_path(cmd: &mut Command, ctx: &Context) {
+    let mut ld_paths: Vec<String> = Vec::new();
+    if let Some(sysroot) = backend::get_rustc_sysroot() {
+        ld_paths.push(format!("{}/lib", sysroot));
+    }
+    if let Some(libmathdx_path) = inherited_or_configured_env(ctx, "LIBMATHDX_PATH") {
+        ld_paths.push(format!("{}/lib", libmathdx_path));
+    }
+    if let Some(existing) = inherited_or_configured_env(ctx, "LD_LIBRARY_PATH") {
+        ld_paths.push(existing);
+    }
+    if !ld_paths.is_empty() {
+        cmd.env("LD_LIBRARY_PATH", ld_paths.join(":"));
+    }
+}
diff --git a/crates/cargo-oxide/src/commands/context.rs b/crates/cargo-oxide/src/commands/context.rs
new file mode 100644
index 0000000000..7ec0f9a85b
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/context.rs
@@ -0,0 +1,511 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::backend;
+use std::path::{Path, PathBuf};
+
+use super::*;
+
+/// Project-local cuda-oxide defaults loaded from `.cargo/cuda-oxide.toml`.
+#[derive(Debug, Clone, Default, PartialEq, Eq)]
+pub struct OxideConfig {
+    /// Explicit backend shared object path.
+    pub backend: Option<PathBuf>,
+    /// Default CUDA architecture for codegen commands.
+    pub default_arch: Option<String>,
+    /// Additional rustflags appended after cuda-oxide's required flags.
+    pub extra_rustflags: Vec<String>,
+    /// Environment variables applied to child Cargo invocations.
+    pub env: Vec<(String, String)>,
+}
+
+/// Pre-resolved context shared across all commands.
+///
+/// Built once at startup by [`resolve_context`] and passed by reference to
+/// every command handler. Avoids repeated filesystem walks and backend builds.
+pub struct Context {
+    /// Absolute path to the workspace root (contains top-level `Cargo.toml`).
+    pub workspace_root: PathBuf,
+    /// Path to `crates/rustc-codegen-cuda` (backend source tree).
+    pub codegen_crate: PathBuf,
+    /// Path to `crates/rustc-codegen-cuda/examples/`.
+    pub examples_dir: PathBuf,
+    /// Path to the built `librustc_codegen_cuda.so` shared object.
+    pub backend_so: PathBuf,
+    /// True when running from inside the cuda-oxide workspace; false for
+    /// standalone projects scaffolded by `cargo oxide new`.
+    pub is_workspace: bool,
+    /// Project-local cuda-oxide defaults.
+    pub config: OxideConfig,
+}
+
+/// Resolve the workspace root and backend, or exit with a helpful error.
+///
+/// Supports two modes:
+/// - **Workspace mode**: CWD is inside the cuda-oxide repo (detected by
+///   `crates/rustc-codegen-cuda` directory). Examples are resolved from the
+///   workspace examples directory.
+/// - **Standalone mode**: CWD has a `Cargo.toml` but is not inside the
+///   workspace. The backend is located via cache or auto-fetch. Commands
+///   like `run` operate on the current directory directly.
+pub fn resolve_context() -> Context {
+    if let Some(workspace_root) = backend::find_workspace_root() {
+        let codegen_crate = workspace_root.join("crates/rustc-codegen-cuda");
+        let examples_dir = codegen_crate.join("examples");
+        let config = load_oxide_config(&workspace_root);
+        let backend_so = backend::find_or_build_backend(&workspace_root, config.backend.as_deref());
+        return Context {
+            workspace_root,
+            codegen_crate,
+            examples_dir,
+            backend_so,
+            is_workspace: true,
+            config,
+        };
+    }
+
+    let cwd = std::env::current_dir().unwrap_or_else(|e| {
+        eprintln!("Error: cannot determine current directory: {}", e);
+        std::process::exit(1);
+    });
+
+    if cwd.join("Cargo.toml").is_file() {
+        let config = load_oxide_config(&cwd);
+        let backend_so = backend::find_or_build_backend(&cwd, config.backend.as_deref());
+        return Context {
+            workspace_root: cwd.clone(),
+            codegen_crate: cwd.clone(),
+            examples_dir: cwd.clone(),
+            backend_so,
+            is_workspace: false,
+            config,
+        };
+    }
+
+    eprintln!("Error: Could not find cuda-oxide workspace or a standalone Cargo.toml.");
+    eprintln!();
+    eprintln!("Run from inside the cuda-oxide repository, or from a project created");
+    eprintln!("with `cargo oxide new <name>`.");
+    std::process::exit(1);
+}
+
+/// Resolve a context for commands that must not build or fetch the backend.
+///
+/// Identical discovery to [`resolve_context`], except the backend `.so` is
+/// only located via [`backend::backend_so_candidate`], never built and never
+/// cloned, and an invalid `.cargo/cuda-oxide.toml` degrades to defaults with
+/// a warning instead of exiting (so `doctor` can report it as a failed
+/// check). Passive commands such as `doctor` and `clean` must remain usable
+/// without triggering backend setup or network access.
+/// `run`/`build`/`pipeline`/`setup` still build the backend on demand.
+pub fn resolve_passive_context() -> Context {
+    if let Some(workspace_root) = backend::find_workspace_root() {
+        let codegen_crate = workspace_root.join("crates/rustc-codegen-cuda");
+        let examples_dir = codegen_crate.join("examples");
+        let config = load_oxide_config_lenient(&workspace_root);
+        let backend_so = backend::backend_so_candidate(&workspace_root, config.backend.as_deref());
+        return Context {
+            workspace_root,
+            codegen_crate,
+            examples_dir,
+            backend_so,
+            is_workspace: true,
+            config,
+        };
+    }
+
+    let cwd = std::env::current_dir().unwrap_or_else(|e| {
+        eprintln!("Error: cannot determine current directory: {}", e);
+        std::process::exit(1);
+    });
+
+    if cwd.join("Cargo.toml").is_file() {
+        let config = load_oxide_config_lenient(&cwd);
+        let backend_so = backend::backend_so_candidate(&cwd, config.backend.as_deref());
+        return Context {
+            workspace_root: cwd.clone(),
+            codegen_crate: cwd.clone(),
+            examples_dir: cwd.clone(),
+            backend_so,
+            is_workspace: false,
+            config,
+        };
+    }
+
+    eprintln!("Error: Could not find cuda-oxide workspace or a standalone Cargo.toml.");
+    eprintln!();
+    eprintln!("Run from inside the cuda-oxide repository, or from a project created");
+    eprintln!("with `cargo oxide new <name>`.");
+    std::process::exit(1);
+}
+
+// =============================================================================
+// Helpers
+// =============================================================================
+
+/// Load `.cargo/cuda-oxide.toml`, exiting on an invalid config.
+///
+/// Build commands ([`resolve_context`]) stay strict: they must not run with
+/// a config the user wrote but cargo-oxide cannot honor.
+pub(super) fn load_oxide_config(workspace_root: &Path) -> OxideConfig {
+    match inspect_oxide_config(workspace_root) {
+        OxideConfigInspection::Missing => OxideConfig::default(),
+        OxideConfigInspection::Valid { config, warnings } => {
+            for warning in warnings {
+                eprintln!("Warning: {warning}");
+            }
+            config
+        }
+        OxideConfigInspection::Invalid { errors, warnings } => {
+            for warning in warnings {
+                eprintln!("Warning: {warning}");
+            }
+            for error in errors {
+                eprintln!("Error: {error}");
+            }
+            std::process::exit(1);
+        }
+    }
+}
+
+/// Load `.cargo/cuda-oxide.toml`, falling back to defaults on an invalid
+/// config instead of exiting.
+///
+/// Passive commands ([`resolve_passive_context`]: `doctor`, `clean`, ...)
+/// must stay usable with a broken config. `doctor` in particular re-inspects
+/// the file and reports the failure as a regular failed check, which it can
+/// only do if context resolution survives long enough for the scan to start.
+pub(super) fn load_oxide_config_lenient(workspace_root: &Path) -> OxideConfig {
+    match inspect_oxide_config(workspace_root) {
+        OxideConfigInspection::Missing => OxideConfig::default(),
+        OxideConfigInspection::Valid { config, warnings } => {
+            for warning in warnings {
+                eprintln!("Warning: {warning}");
+            }
+            config
+        }
+        OxideConfigInspection::Invalid { errors, warnings } => {
+            for warning in warnings {
+                eprintln!("Warning: {warning}");
+            }
+            for error in errors {
+                eprintln!("Warning: {error}");
+            }
+            eprintln!("Warning: ignoring invalid cuda-oxide config and continuing with defaults");
+            OxideConfig::default()
+        }
+    }
+}
+
+/// Result of reading `.cargo/cuda-oxide.toml` without exiting the process.
+///
+/// `doctor` uses this so a bad config is reported alongside other checks
+/// instead of aborting before the rest of the environment scan runs.
+#[derive(Debug)]
+pub(super) enum OxideConfigInspection {
+    Missing,
+    Valid {
+        config: OxideConfig,
+        warnings: Vec<String>,
+    },
+    Invalid {
+        errors: Vec<String>,
+        warnings: Vec<String>,
+    },
+}
+
+pub(super) fn inspect_oxide_config(workspace_root: &Path) -> OxideConfigInspection {
+    let config_path = workspace_root.join(".cargo/cuda-oxide.toml");
+    if !config_path.exists() {
+        return OxideConfigInspection::Missing;
+    }
+
+    let source = match std::fs::read_to_string(&config_path) {
+        Ok(source) => source,
+        Err(error) => {
+            return OxideConfigInspection::Invalid {
+                errors: vec![format!(
+                    "could not read cuda-oxide config {}: {error}",
+                    config_path.display()
+                )],
+                warnings: Vec::new(),
+            };
+        }
+    };
+
+    let document: toml::Value = match toml::from_str(&source) {
+        Ok(document) => document,
+        Err(error) => {
+            return OxideConfigInspection::Invalid {
+                errors: vec![format!(
+                    "could not parse cuda-oxide config {}: {error}",
+                    config_path.display()
+                )],
+                warnings: Vec::new(),
+            };
+        }
+    };
+
+    let Some(table) = document.as_table() else {
+        return OxideConfigInspection::Invalid {
+            errors: vec![format!(
+                "cuda-oxide config {} must be a TOML table",
+                config_path.display()
+            )],
+            warnings: Vec::new(),
+        };
+    };
+
+    let mut errors = Vec::new();
+    let mut warnings = Vec::new();
+
+    let backend = match optional_config_string(table, "backend", &config_path) {
+        Ok(value) => value
+            .map(PathBuf::from)
+            .map(|path| absolutize_config_path(path, &config_path)),
+        Err(error) => {
+            errors.push(error);
+            None
+        }
+    };
+    let default_arch = match optional_config_string(table, "default-arch", &config_path) {
+        Ok(value) => {
+            if let Some(ref arch) = value {
+                // Validate with the same parser the consumers use
+                // (`parse_nvvm_arch` normalizes `sm_XX` / `compute_XX` / bare
+                // `XX` into a `CudaArch`), so load-time validation is exactly
+                // as permissive as what a build would accept. Non-`sm_XX`
+                // spellings work but are advisory-warned: `sm_XX` is the form
+                // `--arch` and the rest of cargo-oxide document.
+                match parse_nvvm_arch(arch) {
+                    Ok(parsed) => {
+                        if !arch.starts_with("sm_") {
+                            warnings.push(format!(
+                                "cuda-oxide config {} spells `default-arch` as `{arch}`; \
+                                 prefer the `{}` form used by `--arch`",
+                                config_path.display(),
+                                parsed.sm()
+                            ));
+                        }
+                    }
+                    Err(error) => {
+                        errors.push(format!(
+                            "cuda-oxide config {} field `default-arch`: {error}",
+                            config_path.display()
+                        ));
+                    }
+                }
+            }
+            value
+        }
+        Err(error) => {
+            errors.push(error);
+            None
+        }
+    };
+    let extra_rustflags = match optional_config_string_array(table, "extra-rustflags", &config_path)
+    {
+        Ok(value) => value,
+        Err(error) => {
+            errors.push(error);
+            Vec::new()
+        }
+    };
+    let env = match table.get("env") {
+        None => Vec::new(),
+        Some(value) => match parse_config_env(value, &config_path) {
+            Ok(env) => {
+                for (key, _) in &env {
+                    if matches!(key.as_str(), "RUSTFLAGS" | "CARGO_ENCODED_RUSTFLAGS") {
+                        warnings.push(format!(
+                            "cuda-oxide config {} `[env]` key `{key}` is ignored; \
+                             use `extra-rustflags` for project rustc defaults",
+                            config_path.display()
+                        ));
+                    }
+                }
+                env
+            }
+            Err(error) => {
+                errors.push(error);
+                Vec::new()
+            }
+        },
+    };
+
+    if !errors.is_empty() {
+        return OxideConfigInspection::Invalid { errors, warnings };
+    }
+
+    OxideConfigInspection::Valid {
+        config: OxideConfig {
+            backend,
+            default_arch,
+            extra_rustflags,
+            env,
+        },
+        warnings,
+    }
+}
+
+/// Outcome of doctor's project-config check, separated from printing so
+/// tests can assert the doctor-level behavior (headline, detail lines,
+/// pass/fail) directly.
+pub(super) struct OxideConfigCheck {
+    /// Line printed after the check label.
+    pub(super) headline: String,
+    /// Indented detail lines (warnings, then errors).
+    pub(super) details: Vec<String>,
+    /// Whether the check failed (flips doctor to a nonzero exit).
+    pub(super) failed: bool,
+}
+
+pub(super) fn check_oxide_config(workspace_root: &Path) -> OxideConfigCheck {
+    let config_path = workspace_root.join(".cargo/cuda-oxide.toml");
+    match inspect_oxide_config(workspace_root) {
+        OxideConfigInspection::Missing => OxideConfigCheck {
+            headline: "- not present (using defaults)".to_string(),
+            details: Vec::new(),
+            failed: false,
+        },
+        OxideConfigInspection::Valid { config, warnings } => OxideConfigCheck {
+            headline: match &config.default_arch {
+                Some(arch) => format!("✓ {} (default-arch = {arch})", config_path.display()),
+                None => format!("✓ {}", config_path.display()),
+            },
+            details: warnings
+                .into_iter()
+                .map(|warning| format!("⚠ {warning}"))
+                .collect(),
+            failed: false,
+        },
+        OxideConfigInspection::Invalid { errors, warnings } => OxideConfigCheck {
+            headline: format!("✗ {}", config_path.display()),
+            details: warnings
+                .into_iter()
+                .map(|warning| format!("⚠ {warning}"))
+                .chain(errors.into_iter().map(|error| format!("✗ {error}")))
+                .collect(),
+            failed: true,
+        },
+    }
+}
+
+pub(super) fn doctor_report_oxide_config(ctx: &Context, ok: &mut bool) {
+    print!("Project config (.cargo/cuda-oxide.toml)... ");
+    let check = check_oxide_config(&ctx.workspace_root);
+    println!("{}", check.headline);
+    for line in check.details {
+        println!("  {line}");
+    }
+    if check.failed {
+        *ok = false;
+    }
+}
+
+fn absolutize_config_path(path: PathBuf, config_path: &Path) -> PathBuf {
+    if path.is_absolute() {
+        return path;
+    }
+    config_path
+        .parent()
+        .unwrap_or_else(|| Path::new("."))
+        .join(path)
+}
+
+fn optional_config_string(
+    table: &toml::Table,
+    key: &str,
+    config_path: &Path,
+) -> Result<Option<String>, String> {
+    match table.get(key) {
+        None => Ok(None),
+        Some(value) => value.as_str().map(|s| Some(s.to_string())).ok_or_else(|| {
+            format!(
+                "cuda-oxide config {} field `{key}` must be a string",
+                config_path.display()
+            )
+        }),
+    }
+}
+
+fn optional_config_string_array(
+    table: &toml::Table,
+    key: &str,
+    config_path: &Path,
+) -> Result<Vec<String>, String> {
+    match table.get(key) {
+        None => Ok(Vec::new()),
+        Some(value) => {
+            let array = value.as_array().ok_or_else(|| {
+                format!(
+                    "cuda-oxide config {} field `{key}` must be an array of strings",
+                    config_path.display()
+                )
+            })?;
+            array
+                .iter()
+                .map(|item| {
+                    item.as_str().map(str::to_string).ok_or_else(|| {
+                        format!(
+                            "cuda-oxide config {} field `{key}` must be an array of strings",
+                            config_path.display()
+                        )
+                    })
+                })
+                .collect()
+        }
+    }
+}
+
+fn parse_config_env(
+    value: &toml::Value,
+    config_path: &Path,
+) -> Result<Vec<(String, String)>, String> {
+    let table = value.as_table().ok_or_else(|| {
+        format!(
+            "cuda-oxide config {} field `env` must be a table of strings",
+            config_path.display()
+        )
+    })?;
+    let mut env: Vec<_> = table
+        .iter()
+        .map(|(key, value)| {
+            let value = value.as_str().ok_or_else(|| {
+                format!(
+                    "cuda-oxide config {} env value `{key}` must be a string",
+                    config_path.display()
+                )
+            })?;
+            Ok((key.clone(), value.to_string()))
+        })
+        .collect::<Result<Vec<_>, String>>()?;
+    env.sort_by(|left, right| left.0.cmp(&right.0));
+    Ok(env)
+}
+
+/// Resolve an example name to its directory path, or exit with a list of
+/// available examples if not found.
+pub(super) fn resolve_example_dir(ctx: &Context, example: &str) -> PathBuf {
+    let example_dir = ctx.examples_dir.join(example);
+    if !example_dir.exists() {
+        eprintln!("Error: Example not found: {}", example_dir.display());
+        eprintln!();
+        eprintln!("Available examples:");
+        if let Ok(entries) = std::fs::read_dir(&ctx.examples_dir) {
+            let mut names: Vec<_> = entries
+                .flatten()
+                .filter(|e| e.path().is_dir())
+                .map(|e| e.file_name().to_string_lossy().to_string())
+                .collect();
+            names.sort();
+            for name in names {
+                eprintln!("  - {}", name);
+            }
+        }
+        std::process::exit(1);
+    }
+    example_dir
+}
diff --git a/crates/cargo-oxide/src/commands/doctor.rs b/crates/cargo-oxide/src/commands/doctor.rs
new file mode 100644
index 0000000000..40c55ffb78
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/doctor.rs
@@ -0,0 +1,702 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::backend;
+use std::path::{Path, PathBuf};
+use std::process::Command;
+
+use super::*;
+
+// =============================================================================
+// Doctor command
+// =============================================================================
+
+/// Parsed contents of a `rust-toolchain.toml` pin.
+#[derive(Clone, Debug, Eq, PartialEq)]
+pub(super) struct RustToolchainPin {
+    pub(super) channel: String,
+    pub(super) components: Vec<String>,
+}
+
+/// Components that doctor treats as hard requirements for the cuda-oxide
+/// pipeline even if `rust-toolchain.toml` stops listing them: `rust-src`
+/// (device-side core sources), `rustc-dev` (rustc_private, required to build
+/// the codegen backend), and `llvm-tools`.
+const DOCTOR_REQUIRED_COMPONENTS: &[&str] = &["rust-src", "rustc-dev", "llvm-tools"];
+
+/// The components doctor verifies for a pin: everything the pin itself lists,
+/// plus the [`DOCTOR_REQUIRED_COMPONENTS`] floor.
+///
+/// rustup auto-installs every component named in `rust-toolchain.toml` when it
+/// installs the pinned toolchain, so a pinned component that is absent from
+/// `rustup component list --installed` means a broken or manually trimmed
+/// install and is worth failing doctor over. The floor guards against a future
+/// edit of the pin file dropping a component the pipeline genuinely needs.
+pub(super) fn doctor_verified_components(pin: &RustToolchainPin) -> Vec<String> {
+    let mut required: Vec<String> = pin.components.clone();
+    for component in DOCTOR_REQUIRED_COMPONENTS {
+        if !required.iter().any(|existing| existing == component) {
+            required.push((*component).to_string());
+        }
+    }
+    required
+}
+
+/// Parse a `rust-toolchain.toml` document for channel and components.
+pub(super) fn parse_rust_toolchain_toml(contents: &str) -> Result<RustToolchainPin, String> {
+    let value: toml::Value =
+        toml::from_str(contents).map_err(|error| format!("invalid TOML: {error}"))?;
+    let toolchain = value
+        .get("toolchain")
+        .ok_or_else(|| "missing [toolchain] table".to_string())?;
+    let channel = toolchain
+        .get("channel")
+        .and_then(toml::Value::as_str)
+        .map(str::trim)
+        .filter(|channel| !channel.is_empty())
+        .ok_or_else(|| "missing toolchain.channel".to_string())?
+        .to_string();
+    let components = match toolchain.get("components") {
+        None => Vec::new(),
+        Some(toml::Value::Array(items)) => items
+            .iter()
+            .map(|item| {
+                item.as_str()
+                    .map(|name| name.trim().to_string())
+                    .filter(|name| !name.is_empty())
+                    .ok_or_else(|| {
+                        "toolchain.components entries must be non-empty strings".to_string()
+                    })
+            })
+            .collect::<Result<Vec<_>, _>>()?,
+        Some(_) => {
+            return Err("toolchain.components must be an array of strings".to_string());
+        }
+    };
+    Ok(RustToolchainPin {
+        channel,
+        components,
+    })
+}
+
+/// True when `rustup show active-toolchain` output matches the pinned channel.
+///
+/// The toolchain name is the first whitespace-delimited token of the first
+/// line in every rustup output format seen so far:
+///
+/// - pre-1.28 and 1.29+: `nightly-2026-04-03-<triple> (default)` or
+///   `nightly-2026-04-03-<triple> (overridden by '<path>')` on one line
+///   (verified against rustup 1.29.0);
+/// - 1.28.x: the bare name on the first line with the reason on a second
+///   `active because: ...` line.
+pub(super) fn active_toolchain_matches_channel(active_toolchain: &str, channel: &str) -> bool {
+    let active = active_toolchain
+        .lines()
+        .next()
+        .unwrap_or("")
+        .split_whitespace()
+        .next()
+        .unwrap_or("");
+    if active.is_empty() || channel.is_empty() {
+        return false;
+    }
+    active == channel || active.starts_with(&format!("{channel}-"))
+}
+
+/// Return required components that are absent from `rustup component list --installed`.
+pub(super) fn missing_rustup_components<S: AsRef<str>>(
+    installed_list: &str,
+    required: &[S],
+) -> Vec<String> {
+    required
+        .iter()
+        .map(AsRef::as_ref)
+        .filter(|component| !rustup_component_installed(installed_list, component))
+        .map(str::to_string)
+        .collect()
+}
+
+fn rustup_component_installed(installed_list: &str, component: &str) -> bool {
+    installed_list.lines().any(|line| {
+        let name = line.split_whitespace().next().unwrap_or("");
+        name == component || name.starts_with(&format!("{component}-"))
+    })
+}
+
+fn doctor_report_toolchain_pin(ctx: &Context, ok: &mut bool) {
+    let toolchain_file = ctx.workspace_root.join("rust-toolchain.toml");
+    print!("rust-toolchain.toml... ");
+    if !toolchain_file.exists() {
+        println!("✗ not found at {}", toolchain_file.display());
+        *ok = false;
+        return;
+    }
+
+    let contents = match std::fs::read_to_string(&toolchain_file) {
+        Ok(contents) => contents,
+        Err(error) => {
+            println!("✗ present but unreadable ({error})");
+            *ok = false;
+            return;
+        }
+    };
+
+    let pin = match parse_rust_toolchain_toml(&contents) {
+        Ok(pin) => pin,
+        Err(error) => {
+            println!("✗ present but invalid ({error})");
+            *ok = false;
+            return;
+        }
+    };
+    println!("✓ channel {}", pin.channel);
+
+    print!("Pinned toolchain active... ");
+    match Command::new("rustup")
+        .args(["show", "active-toolchain"])
+        .output()
+    {
+        Ok(output) if output.status.success() => {
+            let active = String::from_utf8_lossy(&output.stdout);
+            let active = active.trim();
+            if active_toolchain_matches_channel(active, &pin.channel) {
+                println!("✓ {active}");
+            } else {
+                println!(
+                    "✗ active `{active}`, expected `{pin_channel}`",
+                    pin_channel = pin.channel
+                );
+                eprintln!(
+                    "  Install/select the pin with `rustup toolchain install {}` and reopen the shell",
+                    pin.channel
+                );
+                eprintln!("  in this workspace so rust-toolchain.toml can select it.");
+                *ok = false;
+            }
+        }
+        Ok(output) => {
+            let stderr = String::from_utf8_lossy(&output.stderr);
+            println!("✗ rustup show active-toolchain failed");
+            if !stderr.trim().is_empty() {
+                eprintln!("  {}", stderr.trim());
+            }
+            *ok = false;
+        }
+        Err(_) => {
+            println!("✗ rustup not found");
+            eprintln!("  Install rustup from https://rustup.rs/ so doctor can verify the pin.");
+            *ok = false;
+        }
+    }
+
+    let required = doctor_verified_components(&pin);
+
+    print!("Required rustup components... ");
+    match Command::new("rustup")
+        .args([
+            "component",
+            "list",
+            "--installed",
+            "--toolchain",
+            &pin.channel,
+        ])
+        .output()
+    {
+        Ok(output) if output.status.success() => {
+            let installed = String::from_utf8_lossy(&output.stdout);
+            let missing = missing_rustup_components(&installed, &required);
+            if missing.is_empty() {
+                println!("✓ {}", required.join(", "));
+            } else {
+                println!("✗ missing {}", missing.join(", "));
+                eprintln!(
+                    "  Install with `rustup component add --toolchain {} {}`",
+                    pin.channel,
+                    missing.join(" ")
+                );
+                *ok = false;
+            }
+        }
+        Ok(output) => {
+            let stderr = String::from_utf8_lossy(&output.stderr);
+            println!("✗ could not list components for {}", pin.channel);
+            if !stderr.trim().is_empty() {
+                eprintln!("  {}", stderr.trim());
+            }
+            eprintln!(
+                "  Try `rustup toolchain install {channel} -c {components}`",
+                channel = pin.channel,
+                components = required.join(" -c ")
+            );
+            *ok = false;
+        }
+        Err(_) => {
+            println!("✗ rustup not found");
+            *ok = false;
+        }
+    }
+}
+
+/// Validate the development environment.
+///
+/// Checks for: Rust nightly toolchain, `rust-toolchain.toml`, the codegen
+/// backend `.so` (informational), CUDA headers (`cuda.h`), CUDA toolkit
+/// (`nvcc`, libNVVM, nvJitLink, libdevice), LLVM (`llc`), clang/libclang,
+/// the NVIDIA driver / GPU (informational), and optionally `cuda-gdb` /
+/// `compute-sanitizer`.
+/// Exits non-zero if any required check fails.
+///
+/// Doctor itself needs neither the CUDA toolkit nor a driver: every check
+/// is a subprocess, a filesystem probe, or a runtime `dlopen`, and the
+/// caller resolves the context via [`resolve_passive_context`] so nothing is
+/// built first. This is what lets it diagnose a bare machine (issue #87).
+pub fn doctor(ctx: &Context) {
+    println!("cargo-oxide environment check");
+    println!("==============================");
+    println!();
+
+    let mut ok = true;
+
+    // 1. Rust toolchain
+    print!("Rust nightly toolchain... ");
+    match Command::new("rustc").args(["--version"]).output() {
+        Ok(output) if output.status.success() => {
+            let version = String::from_utf8_lossy(&output.stdout);
+            let version = version.trim();
+            if version.contains("nightly") {
+                println!("✓ {}", version);
+            } else {
+                println!("✗ expected nightly, got: {}", version);
+                ok = false;
+            }
+        }
+        _ => {
+            println!("✗ rustc not found");
+            ok = false;
+        }
+    }
+
+    // 2. rust-toolchain.toml pin + active channel + required components
+    doctor_report_toolchain_pin(ctx, &mut ok);
+
+    // 3. Backend .so. Informational, not fatal: `run`/`build`/`pipeline`
+    // build the backend on demand, so "not built yet" is a healthy state
+    // for a fresh clone.
+    print!("Codegen backend... ");
+    if ctx.backend_so.exists() {
+        println!("✓ {}", ctx.backend_so.display());
+    } else {
+        println!("- not built yet (run `cargo oxide setup`)");
+    }
+
+    // 3a. Project config (`.cargo/cuda-oxide.toml`)
+    doctor_report_oxide_config(ctx, &mut ok);
+
+    // 3b. Shared cache. The check above reports the backend this context
+    // resolves to, which inside the repository is the local build. A project
+    // outside the repository resolves to the cache instead, so the two can
+    // disagree while every other check passes.
+    print!("Shared cache (external projects)... ");
+    match backend::cached_backend_path() {
+        Some(cached) => match backend::compare_cache_to_local(&cached, &ctx.backend_so) {
+            backend::CacheReport::Absent => {
+                println!("- empty; external projects build on first use");
+            }
+            backend::CacheReport::UpToDate => {
+                println!("✓ {}", cached.display());
+            }
+            backend::CacheReport::OlderThanLocal => {
+                println!("⚠ {}", cached.display());
+                println!("  Older than the backend built here, so projects outside this");
+                println!("  repository would load a different one. Run `cargo oxide setup`");
+                println!("  to publish, or set CUDA_OXIDE_BACKEND to pin an explicit path.");
+            }
+        },
+        None => println!("- cache directory unknown (set CARGO_HOME or HOME)"),
+    }
+
+    // 4. CUDA headers (cuda.h). The host `cuda-bindings` crate cannot build
+    // without them; cargo-oxide itself deliberately can, which is what makes
+    // this check reachable on a toolkit-less machine instead of dying inside
+    // cuda-bindings' build script (issue #87).
+    print!("CUDA headers (cuda.h)... ");
+    let toolkit = cuda_toolkit_root(|var| std::env::var(var).ok());
+    let target_dir_override = std::env::var("CUDA_TOOLKIT_TARGET_DIR").ok();
+    let header_candidates = cuda_header_candidates(
+        &toolkit,
+        target_dir_override.as_deref(),
+        std::env::consts::ARCH,
+        std::env::consts::OS,
+    );
+    match header_candidates.iter().find(|path| path.is_file()) {
+        Some(found) => println!("✓ {}", found.display()),
+        None => {
+            println!("✗ not found in the CUDA toolkit at `{}`", toolkit);
+            eprintln!("  Probed:");
+            for candidate in &header_candidates {
+                eprintln!("    {}", candidate.display());
+            }
+            eprintln!("  Host crates (cuda-bindings) cannot build without cuda.h. Set");
+            eprintln!("  CUDA_TOOLKIT_PATH or CUDA_HOME to a CUDA Toolkit install root;");
+            eprintln!("  when neither is set, /usr/local/cuda is used.");
+            ok = false;
+        }
+    }
+
+    // 5. CUDA toolkit -- same discovery order as `cuda.h`, libNVVM, libdevice
+    // and `compute-sanitizer` below. `nvcc` lives in the toolkit's `bin/`, so
+    // probing PATH alone reported the toolkit missing on exactly the install
+    // this project documents: CUDA_HOME set, toolkit not on PATH.
+    print!("CUDA toolkit (nvcc)... ");
+    match doctor_toolkit_tool(ctx, "nvcc") {
+        Some(path) => match Command::new(&path).arg("--version").output() {
+            Ok(output) if output.status.success() => {
+                let version = String::from_utf8_lossy(&output.stdout);
+                if let Some(line) = version.lines().find(|l| l.contains("release")) {
+                    println!("✓ {} ({})", line.trim(), path.display());
+                } else {
+                    println!("✓ {}", path.display());
+                }
+            }
+            _ => println!("✓ {}", path.display()),
+        },
+        None => {
+            let toolkit = cuda_toolkit_root(|key| {
+                std::env::var(key)
+                    .ok()
+                    .filter(|value| !value.trim().is_empty())
+                    .or_else(|| project_config_env(ctx, key).map(str::to_owned))
+            });
+            println!("✗ nvcc not found");
+            eprintln!("  Probed PATH, {toolkit}/bin/nvcc, and the standard install roots.");
+            eprintln!("  Set CUDA_TOOLKIT_PATH or CUDA_HOME to a CUDA Toolkit install root;");
+            eprintln!("  when neither is set, /usr/local/cuda is used.");
+            ok = false;
+        }
+    }
+
+    // 5b. libNVVM + nvJitLink + libdevice (only required when a kernel uses
+    // CUDA libdevice math, e.g. sin/cos/exp/pow). All three ship with the
+    // CUDA Toolkit; checking them here surfaces missing or split packagings
+    // before a runtime failure inside `cuda_host::ltoir::load_kernel_module`.
+    print!("libNVVM (libnvvm.so)... ");
+    match libnvvm_sys::LibNvvm::load() {
+        Ok(nvvm) => match nvvm.version() {
+            Ok((major, minor)) => println!("✓ libNVVM {}.{}", major, minor),
+            Err(_) => println!("✓ (version query failed but library loaded)"),
+        },
+        Err(e) => {
+            println!("✗ {}", e);
+            eprintln!("  Required only when kernels call CUDA libdevice math");
+            eprintln!("  (sin/cos/exp/pow/...). Ships with the CUDA Toolkit at");
+            eprintln!("  <CUDA>/nvvm/lib64/libnvvm.so. No separate download.");
+            ok = false;
+        }
+    }
+
+    print!("nvJitLink (libnvJitLink.so)... ");
+    match nvjitlink_sys::LibNvJitLink::load() {
+        Ok(nvj) => match nvj.version() {
+            Some((major, minor)) => println!("✓ nvJitLink {}.{}", major, minor),
+            None => println!("✓ (version symbol not exported on this CTK)"),
+        },
+        Err(e) => {
+            println!("✗ {}", e);
+            eprintln!("  Required only when kernels call CUDA libdevice math.");
+            eprintln!("  Ships with the CUDA Toolkit at <CUDA>/lib64/libnvJitLink.so.");
+            ok = false;
+        }
+    }
+
+    print!("libdevice (libdevice.10.bc)... ");
+    match libnvvm_sys::find_libdevice() {
+        Ok(path) => println!("✓ {}", path.display()),
+        Err(e) => {
+            println!("✗ {}", e);
+            eprintln!("  Required only when kernels call CUDA libdevice math.");
+            eprintln!("  Ships with the CUDA Toolkit at");
+            eprintln!("  <CUDA>/nvvm/libdevice/libdevice.10.bc. Override the search");
+            eprintln!("  with `CUDA_OXIDE_LIBDEVICE=<path>` if you have it elsewhere.");
+            ok = false;
+        }
+    }
+
+    // 6. llc (LLVM static compiler for PTX)
+    //
+    // cuda-oxide requires LLVM 21+: earlier releases reject modern TMA /
+    // tcgen05 / WGMMA intrinsic signatures. Probe in the same order as the
+    // pipeline:
+    //   1. `CUDA_OXIDE_LLC` (caller-supplied override)
+    //   2. Rust toolchain's `llvm-tools` component (auto-installed via rustup)
+    //   3. `llc-22`, `llc-21`, `llc` on `PATH`
+    // Whatever we pick, reject if the major version is < 21.
+    print!("llc (LLVM)... ");
+
+    // The pipeline's primary entry: the `llc` bundled with the pinned Rust
+    // toolchain's `llvm-tools` component. Built with the NVPTX backend
+    // enabled, so the typical novice path is `rustup component add llvm-tools`
+    // and that's it. Surface the absolute path so doctor's output matches
+    // what the pipeline actually invokes.
+    let rustup_llc_path: Option<String> = Command::new("rustc")
+        .args(["--print", "sysroot", "--print", "host-tuple"])
+        .output()
+        .ok()
+        .filter(|o| o.status.success())
+        .and_then(|output| {
+            let stdout = String::from_utf8(output.stdout).ok()?;
+            let mut lines = stdout.lines();
+            let sysroot = lines.next()?;
+            let host = lines.next()?;
+            let path: std::path::PathBuf = [sysroot, "lib", "rustlib", host, "bin", "llc"]
+                .iter()
+                .collect();
+            path.is_file()
+                .then(|| path.to_str().map(str::to_string))
+                .flatten()
+        });
+
+    let mut candidates: Vec<String> = Vec::new();
+    if let Ok(env_llc) = std::env::var("CUDA_OXIDE_LLC") {
+        candidates.push(env_llc);
+    }
+    if let Some(rustup) = rustup_llc_path.clone() {
+        candidates.push(rustup);
+    }
+    for name in ["llc-22", "llc-21", "llc"] {
+        candidates.push(name.to_string());
+    }
+
+    let llc_pick = candidates.iter().find_map(|candidate| {
+        Command::new(candidate)
+            .arg("--version")
+            .output()
+            .ok()
+            .filter(|o| o.status.success())
+            .map(|o| {
+                (
+                    candidate.clone(),
+                    String::from_utf8_lossy(&o.stdout).into_owned(),
+                )
+            })
+    });
+    match llc_pick {
+        Some((binary, stdout)) => {
+            let banner = stdout
+                .lines()
+                .find(|l| l.contains("LLVM version"))
+                .unwrap_or("(version unknown)")
+                .trim()
+                .to_string();
+            let major = banner
+                .split("LLVM version")
+                .nth(1)
+                .and_then(|rest| rest.trim().split('.').next())
+                .and_then(|s| s.parse::<u32>().ok());
+            match major {
+                Some(v) if v >= 21 => println!("✓ {} ({})", banner, binary),
+                Some(v) => {
+                    println!("✗ {} ({}) — need LLVM 21+", banner, binary);
+                    eprintln!(
+                        "  Your `{}` reports LLVM {}, which rejects the TMA / tcgen05 /",
+                        binary, v
+                    );
+                    eprintln!("  WGMMA intrinsic signatures cuda-oxide emits. Install a newer");
+                    eprintln!("  toolchain (`rustup component add llvm-tools` is usually enough,");
+                    eprintln!("  or `sudo apt install llvm-21`) and either add it to PATH or set");
+                    eprintln!("  `CUDA_OXIDE_LLC=/path/to/llc`.");
+                    ok = false;
+                }
+                None => println!("✓ {} ({}, version could not be parsed)", banner, binary),
+            }
+        }
+        None => {
+            println!("✗ llc not found");
+            eprintln!("  cuda-oxide probes (in order): $CUDA_OXIDE_LLC, the Rust toolchain's");
+            eprintln!("  llvm-tools llc, then llc-22/llc-21/llc on PATH. Easiest fix:");
+            eprintln!("    rustup component add llvm-tools");
+            eprintln!("  Alternative: `sudo apt install llvm-21` (older versions reject");
+            eprintln!("  modern TMA / tcgen05 / WGMMA intrinsics).");
+            ok = false;
+        }
+    }
+
+    // 7. clang / libclang resource dir (host `cuda-bindings` / bindgen)
+    //
+    // The host `cuda-bindings` crate's build.rs runs bindgen, which loads
+    // libclang at runtime to parse `wrapper.h`. That parse pulls in
+    // `<stddef.h>`, which must be served from clang's own resource
+    // directory — the system/GCC copy is not compatible. Fresh installs of
+    // bare `libclang1-*` (without the matching `libclang-common-*-dev`)
+    // leave `/usr/lib/clang/*/include` empty and bindgen explodes with a
+    // mysterious "'stddef.h' file not found". Catch that up front.
+    print!("clang / libclang resource dir... ");
+    let clang_resource_dir = Command::new("clang")
+        .arg("-print-resource-dir")
+        .output()
+        .ok()
+        .filter(|o| o.status.success())
+        .map(|o| String::from_utf8_lossy(&o.stdout).trim().to_string());
+    match clang_resource_dir {
+        Some(ref dir) if std::path::Path::new(&format!("{}/include/stddef.h", dir)).exists() => {
+            println!("✓ {}", dir);
+        }
+        Some(ref dir) => {
+            println!(
+                "✗ resource dir present but `include/stddef.h` missing: {}",
+                dir
+            );
+            eprintln!("  Host `cuda-bindings` uses bindgen, which needs clang's own stddef.h.");
+            eprintln!("  Install the matching dev headers: sudo apt install clang-21");
+            eprintln!("  (or libclang-common-21-dev)");
+            ok = false;
+        }
+        None => {
+            println!("✗ clang not found");
+            eprintln!(
+                "  Host `cuda-bindings` uses bindgen, which needs clang + its resource headers."
+            );
+            eprintln!("  Install with: sudo apt install clang-21");
+            eprintln!("  (or at minimum `libclang-common-21-dev` alongside your libclang)");
+            ok = false;
+        }
+    }
+
+    // 8. NVIDIA driver / GPU. Informational, not fatal: only `cargo oxide
+    // run` (kernel execution) needs a driver. Cross-compiling and GPU-less
+    // CI boxes are supported workflows (`build`/`pipeline` work fine), and
+    // the examples-compile CI job is exactly that.
+    print!("NVIDIA driver / GPU... ");
+    match query_gpu_name_cap_and_driver() {
+        Some((name, (major, minor), driver)) => {
+            println!(
+                "✓ {} (compute capability {}.{}, driver {})",
+                name, major, minor, driver
+            );
+        }
+        None => {
+            // Some containers mount the kernel driver without shipping
+            // nvidia-smi; /proc distinguishes "driver loaded, tool broken"
+            // from "no driver at all".
+            if Path::new("/proc/driver/nvidia/version").exists() {
+                println!("- driver loaded, but nvidia-smi is missing or not reporting a GPU");
+                eprintln!("  A kernel-mode NVIDIA driver is present (/proc/driver/nvidia/");
+                eprintln!("  version), but `nvidia-smi` did not report a usable GPU.");
+                eprintln!("  `cargo oxide run` may still work; arch auto-detection will fall");
+                eprintln!("  back to the backend default (override with --arch=<sm_XX>).");
+            } else {
+                println!("- no NVIDIA driver detected");
+                eprintln!("  Only `cargo oxide run` (kernel execution) needs the driver;");
+                eprintln!("  `cargo oxide build` and `pipeline` work without one.");
+            }
+        }
+    }
+
+    // 9. cuda-gdb (optional) -- same discovery order as `debug`, which is the
+    // command this line is predicting. Probing PATH alone made doctor report a
+    // cuda-gdb missing that `cargo oxide debug` would have found.
+    print!("cuda-gdb (optional)... ");
+    match doctor_toolkit_tool(ctx, "cuda-gdb") {
+        Some(path) => match Command::new(&path).arg("--version").output() {
+            Ok(output) if output.status.success() => {
+                let version = String::from_utf8_lossy(&output.stdout);
+                if let Some(line) = version.lines().next() {
+                    println!("✓ {} ({})", line.trim(), path.display());
+                } else {
+                    println!("✓ {}", path.display());
+                }
+            }
+            _ => println!("✓ {}", path.display()),
+        },
+        None => println!("- not found (only needed for `cargo oxide debug`)"),
+    }
+
+    // 10. compute-sanitizer (optional) — same discovery order as `sanitize`
+    print!("compute-sanitizer (optional)... ");
+    match doctor_toolkit_tool(ctx, "compute-sanitizer") {
+        Some(path) => match Command::new(&path).arg("--version").output() {
+            Ok(output) if output.status.success() => {
+                let version = String::from_utf8_lossy(&output.stdout);
+                // `compute-sanitizer --version` prints a banner and a
+                // copyright line before the actual "Version ..." line.
+                let line = version
+                    .lines()
+                    .map(str::trim)
+                    .find(|line| line.starts_with("Version"))
+                    .or_else(|| version.lines().next().map(str::trim));
+                if let Some(line) = line {
+                    println!("✓ {} ({})", line, path.display());
+                } else {
+                    println!("✓ {}", path.display());
+                }
+            }
+            _ => println!("✓ {}", path.display()),
+        },
+        None => {
+            println!("- not found (only needed for `cargo oxide sanitize`)");
+        }
+    }
+
+    println!();
+    if ok {
+        println!("✅ Environment looks good!");
+    } else {
+        println!("❌ Some checks failed. Fix the issues above and re-run `cargo oxide doctor`.");
+        std::process::exit(1);
+    }
+}
+
+/// CUDA toolkit install root for doctor's `cuda.h` probe: the first set
+/// variable among `CUDA_TOOLKIT_PATH`, `CUDA_HOME`, else `/usr/local/cuda`.
+///
+/// Kept in lockstep BY HAND with `crates/cuda-bindings/build.rs`
+/// (`cuda_toolkit_dir` / `find_cuda_include_dir`): doctor cannot import that
+/// probe because build.rs logic is not a library. If the build.rs discovery
+/// changes, mirror it here.
+pub(super) fn cuda_toolkit_root(mut get_env: impl FnMut(&str) -> Option<String>) -> String {
+    ["CUDA_TOOLKIT_PATH", "CUDA_HOME"]
+        .iter()
+        .find_map(|var| get_env(var).filter(|value| !value.trim().is_empty()))
+        .unwrap_or_else(|| "/usr/local/cuda".to_string())
+}
+
+/// Candidate `cuda.h` paths under `toolkit`, in probe order: the standard
+/// `include/` layout first, then the redistributable `targets/<dir>/include`
+/// layouts. CUDA names the target dirs after the GPU platform, not the Rust
+/// triple: x86_64 Linux hosts use `x86_64-linux`; aarch64 Linux is ambiguous
+/// between servers (`sbsa-linux`) and Tegra (`aarch64-linux`), so both are
+/// probed in that order. A non-blank `target_dir_override` (the
+/// `CUDA_TOOLKIT_TARGET_DIR` variable, like nvcc's `-target-dir`) replaces
+/// the table with that single directory.
+///
+/// Kept in lockstep BY HAND with the selection table in
+/// `crates/cuda-bindings/toolkit_target.rs` (`resolve_toolkit_target_dirs`):
+/// doctor cannot import it because build-script sources are not a library.
+/// If the selection there changes, mirror it here.
+///
+/// `arch` and `os` are the host CPU architecture and OS; the caller passes
+/// `std::env::consts::ARCH` / `std::env::consts::OS` (doctor runs at
+/// runtime, so there are no cargo target cfgs to consult). Injected as
+/// parameters for unit tests.
+pub(super) fn cuda_header_candidates(
+    toolkit: &str,
+    target_dir_override: Option<&str>,
+    arch: &str,
+    os: &str,
+) -> Vec<PathBuf> {
+    let base = Path::new(toolkit);
+    let mut candidates = vec![base.join("include/cuda.h")];
+    let target_dirs: Vec<&str> = match target_dir_override.filter(|dir| !dir.trim().is_empty()) {
+        Some(dir) => vec![dir],
+        None => match (arch, os) {
+            ("x86_64", "linux") => vec!["x86_64-linux"],
+            ("aarch64", "linux") => vec!["sbsa-linux", "aarch64-linux"],
+            _ => vec![],
+        },
+    };
+    for dir in target_dirs {
+        candidates.push(base.join("targets").join(dir).join("include/cuda.h"));
+    }
+    candidates
+}
diff --git a/crates/cargo-oxide/src/commands/examples_list.rs b/crates/cargo-oxide/src/commands/examples_list.rs
new file mode 100644
index 0000000000..7eff89cb16
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/examples_list.rs
@@ -0,0 +1,620 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::fs;
+use std::path::Path;
+
+use super::*;
+
+#[derive(Debug, Clone, Eq, PartialEq)]
+pub(super) struct ExampleInfo {
+    pub(super) name: String,
+    pub(super) title: String,
+    pub(super) description: String,
+    pub(super) requirements: Vec<String>,
+}
+
+#[derive(Debug, Default, Eq, PartialEq)]
+pub(super) struct ParsedReadme {
+    pub(super) title: Option<String>,
+    pub(super) description: Option<String>,
+    pub(super) requirements: Vec<String>,
+}
+
+#[derive(Debug, Default, Eq, PartialEq)]
+struct ManifestInfo {
+    description: Option<String>,
+}
+
+pub fn list_examples(ctx: &Context, json: bool) {
+    if !ctx.is_workspace {
+        eprintln!("Error: `cargo oxide list` must be run from inside a cuda-oxide checkout.");
+        eprintln!();
+        eprintln!("The command lists examples under crates/rustc-codegen-cuda/examples/.");
+        std::process::exit(1);
+    }
+
+    let examples = discover_examples(&ctx.examples_dir).unwrap_or_else(|error| {
+        eprintln!("Error: {error}");
+        std::process::exit(1);
+    });
+
+    let output = if json {
+        format_examples_json(&examples).unwrap_or_else(|error| {
+            eprintln!("Error: could not serialize example list: {error}");
+            std::process::exit(1);
+        })
+    } else {
+        format_examples_human(&examples)
+    };
+
+    print!("{output}");
+}
+
+pub(super) fn discover_examples(examples_dir: &Path) -> Result<Vec<ExampleInfo>, String> {
+    let entries = fs::read_dir(examples_dir).map_err(|error| {
+        format!(
+            "could not read examples directory {}: {error}",
+            examples_dir.display()
+        )
+    })?;
+
+    let mut examples = Vec::new();
+
+    for entry in entries {
+        let entry = entry.map_err(|error| {
+            format!(
+                "could not read an entry under {}: {error}",
+                examples_dir.display()
+            )
+        })?;
+
+        let file_type = entry
+            .file_type()
+            .map_err(|error| format!("could not inspect {}: {error}", entry.path().display()))?;
+
+        if !file_type.is_dir() {
+            continue;
+        }
+
+        let example_dir = entry.path();
+        let name = entry.file_name().into_string().map_err(|name| {
+            format!(
+                "example directory name is not valid UTF-8: {}",
+                name.to_string_lossy()
+            )
+        })?;
+
+        // A directory without a manifest is not an example (scratch dirs,
+        // checked-out tooling, ...). Skip it instead of failing the listing.
+        let manifest_path = example_dir.join("Cargo.toml");
+        if !manifest_path.is_file() {
+            eprintln!(
+                "Warning: skipping {}: no top-level Cargo.toml",
+                example_dir.display()
+            );
+            continue;
+        }
+
+        let manifest = parse_example_manifest(&manifest_path)?;
+
+        let readme_path = example_dir.join("README.md");
+        let parsed_readme = if readme_path.is_file() {
+            let contents = fs::read_to_string(&readme_path)
+                .map_err(|error| format!("could not read {}: {error}", readme_path.display()))?;
+            parse_example_readme(&name, &contents)
+        } else {
+            ParsedReadme::default()
+        };
+
+        let ParsedReadme {
+            title,
+            description,
+            requirements,
+        } = parsed_readme;
+
+        let title = title.unwrap_or_else(|| name.clone());
+
+        let description = description.or(manifest.description).unwrap_or_else(|| {
+            if title != name {
+                title.clone()
+            } else {
+                "No description documented.".to_string()
+            }
+        });
+
+        examples.push(ExampleInfo {
+            name,
+            title,
+            description,
+            requirements,
+        });
+    }
+
+    examples.sort_by(|left, right| left.name.cmp(&right.name));
+
+    if examples.is_empty() {
+        return Err(format!(
+            "no examples found under {}",
+            examples_dir.display()
+        ));
+    }
+
+    Ok(examples)
+}
+
+fn parse_example_manifest(path: &Path) -> Result<ManifestInfo, String> {
+    let contents = fs::read_to_string(path)
+        .map_err(|error| format!("could not read {}: {error}", path.display()))?;
+
+    let manifest: toml::Value = toml::from_str(&contents)
+        .map_err(|error| format!("could not parse {}: {error}", path.display()))?;
+
+    let package = manifest
+        .get("package")
+        .and_then(toml::Value::as_table)
+        .ok_or_else(|| format!("{} has no [package] table", path.display()))?;
+
+    let description = package
+        .get("description")
+        .and_then(toml::Value::as_str)
+        .map(str::trim)
+        .filter(|description| !description.is_empty())
+        .map(str::to_owned);
+
+    Ok(ManifestInfo { description })
+}
+
+pub(super) fn parse_example_readme(crate_name: &str, contents: &str) -> ParsedReadme {
+    let lines: Vec<&str> = contents.lines().collect();
+    let mut headings = Vec::new();
+    let mut in_code_fence = false;
+
+    for (index, line) in lines.iter().enumerate() {
+        if is_code_fence(line) {
+            in_code_fence = !in_code_fence;
+            continue;
+        }
+
+        if in_code_fence {
+            continue;
+        }
+
+        if let Some((level, title)) = parse_markdown_heading(line) {
+            headings.push((index, level, title));
+        }
+    }
+
+    let crate_heading = normalize_heading(crate_name);
+
+    let selected_heading = match headings.first() {
+        Some(first) if normalize_heading(&first.2) == crate_heading => headings
+            .get(1)
+            .filter(|heading| {
+                heading.1 == 2
+                    && first_prose_paragraph_in_range(&lines, first.0 + 1, heading.0).is_none()
+                    && !is_generic_section_heading(&normalize_heading(&heading.2))
+            })
+            .or(Some(first)),
+        Some(first) => Some(first),
+        None => None,
+    };
+
+    let title = selected_heading
+        .map(|(_, _, title)| strip_inline_markdown(title))
+        .filter(|title| !title.is_empty());
+
+    let description_start = selected_heading.map(|(index, _, _)| index + 1).unwrap_or(0);
+
+    let description_end = headings
+        .iter()
+        .find(|(index, _, _)| *index >= description_start)
+        .map(|(index, _, _)| *index)
+        .unwrap_or(lines.len());
+
+    let description = first_prose_paragraph_in_range(&lines, description_start, description_end);
+    let requirements = extract_requirements(&lines);
+
+    ParsedReadme {
+        title,
+        description,
+        requirements,
+    }
+}
+
+fn parse_markdown_heading(line: &str) -> Option<(usize, String)> {
+    let trimmed = line.trim_start();
+    let level = trimmed.bytes().take_while(|byte| *byte == b'#').count();
+
+    if !(1..=6).contains(&level) {
+        return None;
+    }
+
+    let remainder = &trimmed[level..];
+    if !remainder.chars().next().is_some_and(char::is_whitespace) {
+        return None;
+    }
+
+    let title = remainder.trim().trim_end_matches('#').trim();
+
+    if title.is_empty() {
+        None
+    } else {
+        Some((level, title.to_string()))
+    }
+}
+
+fn is_code_fence(line: &str) -> bool {
+    let trimmed = line.trim_start();
+    trimmed.starts_with("```") || trimmed.starts_with("~~~")
+}
+
+fn strip_inline_markdown(value: &str) -> String {
+    value
+        .replace("**", "")
+        .replace("__", "")
+        .replace('`', "")
+        .trim()
+        .to_string()
+}
+
+fn normalize_heading(value: &str) -> String {
+    strip_inline_markdown(value)
+        .trim_matches(|character: char| {
+            character == ':' || character == '-' || character.is_whitespace()
+        })
+        .to_ascii_lowercase()
+}
+
+fn is_generic_section_heading(heading: &str) -> bool {
+    matches!(
+        heading,
+        "overview"
+            | "what this example does"
+            | "key concepts"
+            | "key concepts demonstrated"
+            | "build"
+            | "build and run"
+            | "usage"
+            | "expected output"
+            | "requirements"
+            | "hardware requirements"
+            | "prerequisites"
+            | "potential errors"
+            | "how it works"
+            | "how it works under the hood"
+            | "generated ptx"
+            | "run"
+            | "test"
+            | "tests"
+            | "correctness"
+            | "trigger"
+            | "kernels"
+            | "features tested"
+            | "what this tests"
+            | "what it tests"
+            | "what this demonstrates"
+            | "why this exists"
+            | "the bug"
+            | "final design"
+    )
+}
+
+fn first_prose_paragraph_in_range(lines: &[&str], start: usize, end: usize) -> Option<String> {
+    let end = end.min(lines.len());
+    let start = start.min(end);
+    let mut paragraph = Vec::new();
+    let mut in_code_fence = false;
+
+    for line in &lines[start..end] {
+        if is_code_fence(line) {
+            if !paragraph.is_empty() {
+                break;
+            }
+            in_code_fence = !in_code_fence;
+            continue;
+        }
+
+        if in_code_fence {
+            continue;
+        }
+
+        let trimmed = line.trim();
+
+        if parse_markdown_heading(trimmed).is_some() {
+            break;
+        }
+
+        if trimmed.is_empty() {
+            if !paragraph.is_empty() {
+                break;
+            }
+            continue;
+        }
+
+        if is_non_prose_markdown(trimmed) {
+            if !paragraph.is_empty() {
+                break;
+            }
+            continue;
+        }
+
+        paragraph.push(trimmed);
+    }
+
+    if paragraph.is_empty() {
+        None
+    } else {
+        Some(paragraph.join(" "))
+    }
+}
+
+fn is_non_prose_markdown(line: &str) -> bool {
+    line.starts_with("- ")
+        || line.starts_with("* ")
+        || line.starts_with("+ ")
+        || line.starts_with('>')
+        || line.starts_with('|')
+        || line.starts_with("![")
+        || line.starts_with("<!--")
+        || is_ordered_list_item(line)
+}
+
+fn is_ordered_list_item(line: &str) -> bool {
+    strip_ordered_list_marker(line).is_some()
+}
+
+/// Strip a `1. ` / `42. ` ordered-list marker, returning the item text.
+fn strip_ordered_list_marker(line: &str) -> Option<&str> {
+    let (marker, item) = line.split_once(". ")?;
+    if !marker.is_empty() && marker.bytes().all(|byte| byte.is_ascii_digit()) {
+        Some(item.trim_start())
+    } else {
+        None
+    }
+}
+
+/// Collect the requirement entries documented under a requirements-style
+/// heading ([`is_requirements_heading`]).
+///
+/// Recognized forms:
+/// - unordered list items (`- ` / `* ` / `+ `), with indented
+///   wrap-continuation lines joined onto the item;
+/// - ordered list items (`1. `), same continuation rule;
+/// - two-column markdown tables, emitted as `name: value` per data row.
+///
+/// Tables with any other column count are skipped whole: without knowing
+/// which columns carry the requirement, half-parsing them would produce
+/// garbage entries.
+fn extract_requirements(lines: &[&str]) -> Vec<String> {
+    let mut requirements = Vec::new();
+    let mut current_requirement: Option<String> = None;
+    let mut table_rows: Vec<Vec<String>> = Vec::new();
+    let mut requirement_level = None;
+    let mut in_code_fence = false;
+
+    for line in lines {
+        if is_code_fence(line) {
+            if let Some(requirement) = current_requirement.take() {
+                requirements.push(requirement);
+            }
+            flush_requirement_table(&mut table_rows, &mut requirements);
+            in_code_fence = !in_code_fence;
+            continue;
+        }
+
+        if in_code_fence {
+            continue;
+        }
+
+        if let Some((level, heading)) = parse_markdown_heading(line) {
+            if let Some(requirement) = current_requirement.take() {
+                requirements.push(requirement);
+            }
+            flush_requirement_table(&mut table_rows, &mut requirements);
+
+            let normalized = normalize_heading(&heading);
+
+            if is_requirements_heading(&normalized) {
+                requirement_level = Some(level);
+            } else if requirement_level.is_some_and(|active| level <= active) {
+                requirement_level = None;
+            }
+
+            continue;
+        }
+
+        if requirement_level.is_none() {
+            continue;
+        }
+
+        let trimmed = line.trim();
+
+        // A blank line terminates the current list item or table. Whatever
+        // follows is a new paragraph (prose, a code fence, ...), not a
+        // wrapped continuation of the bullet above it.
+        if trimmed.is_empty() {
+            if let Some(requirement) = current_requirement.take() {
+                requirements.push(requirement);
+            }
+            flush_requirement_table(&mut table_rows, &mut requirements);
+            continue;
+        }
+
+        if trimmed.starts_with('|') {
+            if let Some(requirement) = current_requirement.take() {
+                requirements.push(requirement);
+            }
+            table_rows.push(split_table_row(trimmed));
+            continue;
+        }
+        flush_requirement_table(&mut table_rows, &mut requirements);
+
+        let item = trimmed
+            .strip_prefix("- ")
+            .or_else(|| trimmed.strip_prefix("* "))
+            .or_else(|| trimmed.strip_prefix("+ "))
+            .or_else(|| strip_ordered_list_marker(trimmed));
+
+        if let Some(item) = item {
+            if let Some(requirement) = current_requirement.take() {
+                requirements.push(requirement);
+            }
+
+            let item = strip_inline_markdown(item);
+            if !item.is_empty() {
+                current_requirement = Some(item);
+            }
+        } else if let Some(requirement) = &mut current_requirement {
+            requirement.push(' ');
+            requirement.push_str(&strip_inline_markdown(trimmed));
+        }
+    }
+
+    if let Some(requirement) = current_requirement {
+        requirements.push(requirement);
+    }
+    flush_requirement_table(&mut table_rows, &mut requirements);
+
+    requirements.dedup();
+    requirements
+}
+
+/// Split a markdown table row into trimmed cells, honoring `\|` escapes and
+/// dropping the empty leading/trailing cells produced by the outer pipes.
+fn split_table_row(row: &str) -> Vec<String> {
+    let mut cells = Vec::new();
+    let mut cell = String::new();
+    let mut characters = row.chars().peekable();
+
+    while let Some(character) = characters.next() {
+        match character {
+            '\\' if characters.peek() == Some(&'|') => {
+                cell.push('|');
+                characters.next();
+            }
+            '|' => {
+                cells.push(cell.trim().to_string());
+                cell.clear();
+            }
+            _ => cell.push(character),
+        }
+    }
+    cells.push(cell.trim().to_string());
+
+    if cells.first().is_some_and(|first| first.is_empty()) {
+        cells.remove(0);
+    }
+    if cells.last().is_some_and(|last| last.is_empty()) {
+        cells.pop();
+    }
+
+    cells
+}
+
+/// The `|---|:---:|` row separating a table header from its data rows.
+fn is_table_separator_row(cells: &[String]) -> bool {
+    !cells.is_empty()
+        && cells.iter().all(|cell| {
+            !cell.is_empty()
+                && cell
+                    .chars()
+                    .all(|character| character == '-' || character == ':')
+        })
+}
+
+/// Convert a buffered `| name | value |` requirements table into one
+/// `name: value` entry per data row. Tables whose header or data rows are
+/// not exactly two columns are dropped whole rather than half-parsed.
+fn flush_requirement_table(table_rows: &mut Vec<Vec<String>>, requirements: &mut Vec<String>) {
+    let rows = std::mem::take(table_rows);
+
+    // Header, separator, and at least one data row.
+    if rows.len() < 3 || !is_table_separator_row(&rows[1]) {
+        return;
+    }
+
+    if !rows.iter().all(|row| row.len() == 2) {
+        return;
+    }
+
+    for row in &rows[2..] {
+        let name = strip_inline_markdown(&row[0]);
+        let value = strip_inline_markdown(&row[1]);
+        if !name.is_empty() && !value.is_empty() {
+            requirements.push(format!("{name}: {value}"));
+        }
+    }
+}
+
+fn is_requirements_heading(heading: &str) -> bool {
+    matches!(
+        heading,
+        "requirements"
+            | "hardware requirements"
+            | "software requirements"
+            | "system requirements"
+            | "toolkit requirements"
+            | "build requirements"
+            | "prerequisites"
+    )
+}
+
+fn format_examples_human(examples: &[ExampleInfo]) -> String {
+    let mut output = String::new();
+
+    for (index, example) in examples.iter().enumerate() {
+        if index != 0 {
+            output.push('\n');
+        }
+
+        output.push_str(&example.name);
+        output.push('\n');
+
+        if example.title != example.name {
+            output.push_str("  ");
+            output.push_str(&example.title);
+            output.push('\n');
+        }
+
+        output.push_str("  ");
+        output.push_str(&example.description);
+        output.push('\n');
+
+        if !example.requirements.is_empty() {
+            output.push_str("  Requirements:\n");
+            for requirement in &example.requirements {
+                output.push_str("    - ");
+                output.push_str(requirement);
+                output.push('\n');
+            }
+        }
+    }
+
+    output
+}
+
+pub(super) fn format_examples_json(examples: &[ExampleInfo]) -> Result<String, serde_json::Error> {
+    let examples = examples
+        .iter()
+        .map(|example| {
+            serde_json::json!({
+                "name": example.name,
+                "title": example.title,
+                "description": example.description,
+                "requirements": example.requirements,
+            })
+        })
+        .collect::<Vec<_>>();
+
+    let document = serde_json::json!({
+        "schema_version": 1,
+        "examples": examples,
+    });
+
+    let mut output = serde_json::to_string_pretty(&document)?;
+    output.push('\n');
+    Ok(output)
+}
diff --git a/crates/cargo-oxide/src/commands/fingerprint.rs b/crates/cargo-oxide/src/commands/fingerprint.rs
new file mode 100644
index 0000000000..b5b981b48e
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/fingerprint.rs
@@ -0,0 +1,368 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use sha2::Digest as _;
+use std::collections::BTreeMap;
+use std::path::Path;
+
+use super::*;
+
+pub(super) fn digest_hex(digest: &[u8; 32]) -> String {
+    use std::fmt::Write;
+    let mut hex = String::with_capacity(64);
+    for byte in digest {
+        write!(&mut hex, "{byte:02x}").expect("writing to String cannot fail");
+    }
+    hex
+}
+
+pub(super) fn passthrough_codegen_fingerprint(
+    ctx: &Context,
+    opts: &CargoPassthroughOptions<'_>,
+    owner_filter: Option<&str>,
+    target_arch: Option<&str>,
+    materialization: &MaterializationMode,
+) -> String {
+    passthrough_codegen_fingerprint_with_env(
+        ctx,
+        opts,
+        owner_filter,
+        target_arch,
+        materialization,
+        &inherited_process_env(),
+    )
+}
+
+pub(super) fn passthrough_codegen_fingerprint_with_env(
+    ctx: &Context,
+    opts: &CargoPassthroughOptions<'_>,
+    owner_filter: Option<&str>,
+    target_arch: Option<&str>,
+    materialization: &MaterializationMode,
+    inherited_env: &BTreeMap<String, Vec<u8>>,
+) -> String {
+    let mut effective_env = BTreeMap::new();
+
+    // Project-configured CUDA_OXIDE_* variables are defaults. Mirror the same
+    // parent override rule as `apply_config_env` so changes that can affect
+    // codegen also change Cargo's rustflags fingerprint.
+    for (key, configured_value) in &ctx.config.env {
+        if !key.starts_with("CUDA_OXIDE_") {
+            continue;
+        }
+        if let Some(value) = inherited_env.get(key) {
+            // Keep the platform encoding. Presence-only backend switches such
+            // as CUDA_OXIDE_NO_FMA remain effective even when their value is
+            // not Unicode, so dropping those bytes could reuse stale code.
+            effective_env.insert(key.clone(), value.clone());
+        } else {
+            effective_env.insert(key.clone(), configured_value.as_bytes().to_vec());
+        }
+    }
+    // Capture backend settings inherited outside project config, including
+    // current and future CUDA_OXIDE_* switches.
+    for (key, value) in inherited_env.iter().filter(|(key, _)| {
+        key.starts_with("CUDA_OXIDE_") && key.as_str() != CODEGEN_FINGERPRINT_ENV
+    }) {
+        effective_env.insert(key.clone(), value.clone());
+    }
+
+    // These are wrapper-owned semantic values. Normalize away inherited
+    // false/stale handshakes before inserting the effective materialization
+    // state below, so no-op values do not create distinct Cargo identities.
+    effective_env.remove(CODEGEN_FINGERPRINT_ENV);
+    effective_env.remove(MATERIALIZE_ENV);
+    effective_env.remove(EXPECTED_PROVENANCE_ENV);
+    // Descriptor identity only accelerates verification; artifact identity is
+    // already represented by the content-derived provenance above.
+    effective_env.remove(MATERIALIZER_HANDSHAKE_ENV);
+
+    if opts.verbose {
+        effective_env.insert("CUDA_OXIDE_VERBOSE".to_string(), b"1".to_vec());
+    }
+    if opts.no_fmad {
+        effective_env.insert("CUDA_OXIDE_NO_FMA".to_string(), b"1".to_vec());
+    }
+    if opts.unchecked_indexing {
+        effective_env.insert("CUDA_OXIDE_UNCHECKED_INDEXING".to_string(), b"1".to_vec());
+    }
+    if let Some(level) = opts.device_debug.env_value() {
+        effective_env.insert("CUDA_OXIDE_DEBUG".to_string(), level.as_bytes().to_vec());
+    }
+    if opts.emit_nvvm_ir || materialization.enabled() {
+        effective_env.insert("CUDA_OXIDE_EMIT_NVVM_IR".to_string(), b"1".to_vec());
+    }
+    if let Some(prepared) = &materialization.prepared {
+        effective_env.insert(MATERIALIZE_ENV.to_string(), b"1".to_vec());
+        effective_env.insert(
+            EXPECTED_PROVENANCE_ENV.to_string(),
+            prepared.provenance_sha256_hex.as_bytes().to_vec(),
+        );
+    }
+    if let Some(target_arch) = target_arch {
+        effective_env.insert(
+            "CUDA_OXIDE_TARGET".to_string(),
+            target_arch.as_bytes().to_vec(),
+        );
+    }
+    if let Some(owner_filter) = owner_filter {
+        effective_env.insert(
+            DEVICE_CODEGEN_CRATE_ENV.to_string(),
+            owner_filter.as_bytes().to_vec(),
+        );
+    }
+
+    // SHA-256 over length-delimited key/value pairs. The complete digest is
+    // tracked by device-owning procedural macros, so settings are neither
+    // exposed verbatim in diagnostics nor reduced to a small collision space.
+    let mut hash = sha2::Sha256::new();
+    for (key, value) in effective_env {
+        update_codegen_fingerprint_hash(&mut hash, key.as_bytes());
+        update_codegen_fingerprint_hash(&mut hash, &value);
+    }
+    finish_codegen_fingerprint(hash)
+}
+
+fn update_codegen_fingerprint_hash(hash: &mut sha2::Sha256, bytes: &[u8]) {
+    use sha2::Digest as _;
+
+    hash.update((bytes.len() as u64).to_le_bytes());
+    hash.update(bytes);
+}
+
+fn finish_codegen_fingerprint(hash: sha2::Sha256) -> String {
+    use sha2::Digest as _;
+
+    let digest: [u8; 32] = hash.finalize().into();
+    digest_hex(&digest)
+}
+
+/// Track sanitizer-only device output settings in crates that declare device
+/// code, without invalidating their host-only dependency graph.
+#[allow(clippy::too_many_arguments)]
+pub(super) fn sanitize_codegen_fingerprint(
+    ctx: &Context,
+    verbose: bool,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+    target_arch: Option<&str>,
+    detected_device_arch: Option<&str>,
+    ptx_dir: Option<&Path>,
+    materialization: &MaterializationMode,
+) -> String {
+    sanitize_codegen_fingerprint_with_env(
+        ctx,
+        verbose,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+        target_arch,
+        detected_device_arch,
+        ptx_dir,
+        materialization,
+        &inherited_process_env(),
+    )
+}
+
+/// `sanitize_codegen_fingerprint` with the inherited environment injected, the
+/// counterpart to `passthrough_codegen_fingerprint_with_env`.
+#[allow(clippy::too_many_arguments)]
+pub(super) fn sanitize_codegen_fingerprint_with_env(
+    ctx: &Context,
+    verbose: bool,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+    target_arch: Option<&str>,
+    detected_device_arch: Option<&str>,
+    ptx_dir: Option<&Path>,
+    materialization: &MaterializationMode,
+    inherited_env: &BTreeMap<String, Vec<u8>>,
+) -> String {
+    let opts = CargoPassthroughOptions {
+        verbose,
+        emit_nvvm_ir: false,
+        arch: target_arch,
+        features: None,
+        cargo_target_dir: None,
+        device_codegen_crate: None,
+        device_cfgs: &[],
+        no_fmad,
+        unchecked_indexing,
+        materialize_cubin: materialization.enabled(),
+        device_debug,
+    };
+    let base = passthrough_codegen_fingerprint_with_env(
+        ctx,
+        &opts,
+        None,
+        target_arch,
+        materialization,
+        inherited_env,
+    );
+    let mut hash = sha2::Sha256::new();
+    for bytes in [
+        "sanitize-line-tables-v1".as_bytes(),
+        base.as_bytes(),
+        detected_device_arch.unwrap_or("").as_bytes(),
+    ] {
+        update_codegen_fingerprint_hash(&mut hash, bytes);
+    }
+    if let Some(ptx_dir) = ptx_dir {
+        update_codegen_fingerprint_hash(&mut hash, ptx_dir.as_os_str().as_encoded_bytes());
+    }
+    finish_codegen_fingerprint(hash)
+}
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn standard_codegen_fingerprint(
+    ctx: &Context,
+    verbose: bool,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+    emit_nvvm_ir: bool,
+    target_arch: Option<&str>,
+    detected_device_arch: Option<&str>,
+    materialization: &MaterializationMode,
+) -> String {
+    let opts = CargoPassthroughOptions {
+        verbose,
+        emit_nvvm_ir,
+        arch: target_arch,
+        features: None,
+        cargo_target_dir: None,
+        device_codegen_crate: None,
+        device_cfgs: &[],
+        no_fmad,
+        unchecked_indexing,
+        materialize_cubin: materialization.enabled(),
+        device_debug,
+    };
+    let base = passthrough_codegen_fingerprint(ctx, &opts, None, target_arch, materialization);
+    let mut hash = sha2::Sha256::new();
+    for bytes in [
+        "standard-codegen-v1".as_bytes(),
+        base.as_bytes(),
+        detected_device_arch.unwrap_or("").as_bytes(),
+    ] {
+        update_codegen_fingerprint_hash(&mut hash, bytes);
+    }
+    finish_codegen_fingerprint(hash)
+}
+
+pub(super) fn pipeline_codegen_fingerprint(
+    ctx: &Context,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+    emit_nvvm_ir: bool,
+    target_arch: Option<&str>,
+    materialization: &MaterializationMode,
+) -> String {
+    let base = standard_codegen_fingerprint(
+        ctx,
+        true,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+        emit_nvvm_ir,
+        target_arch,
+        None,
+        materialization,
+    );
+    let mut hash = sha2::Sha256::new();
+    for value in [
+        base.as_str(),
+        "CUDA_OXIDE_SHOW_RUSTC_MIR=1",
+        "CUDA_OXIDE_DUMP_MIR=1",
+        "CUDA_OXIDE_DUMP_LLVM=1",
+    ] {
+        update_codegen_fingerprint_hash(&mut hash, value.as_bytes());
+    }
+    finish_codegen_fingerprint(hash)
+}
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn interop_codegen_fingerprint(
+    ctx: &Context,
+    verbose: bool,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+    target_arch: Option<&str>,
+    detected_device_arch: Option<&str>,
+    artifact_dir: &Path,
+    emit_nvvm_ir: bool,
+    device_features: Option<&str>,
+    sanitizer_line_tables: bool,
+    materialization: &MaterializationMode,
+) -> String {
+    let base = standard_codegen_fingerprint(
+        ctx,
+        verbose,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+        emit_nvvm_ir,
+        target_arch,
+        detected_device_arch,
+        materialization,
+    );
+    let mut hash = sha2::Sha256::new();
+    for bytes in [
+        "interop-codegen-v1".as_bytes(),
+        base.as_bytes(),
+        if sanitizer_line_tables {
+            b"line-tables"
+        } else {
+            b"default-debug"
+        },
+        artifact_dir.as_os_str().as_encoded_bytes(),
+        device_features.unwrap_or("").as_bytes(),
+    ] {
+        update_codegen_fingerprint_hash(&mut hash, bytes);
+    }
+    finish_codegen_fingerprint(hash)
+}
+
+pub(super) fn backend_artifact_digest(path: &Path) -> Result<String, String> {
+    use sha2::{Digest, Sha256};
+    use std::io::Read;
+
+    let mut hasher = Sha256::new();
+    if path == Path::new("llvm") {
+        hasher.update(b"rustc built-in LLVM backend");
+        let digest: [u8; 32] = hasher.finalize().into();
+        return Ok(digest_hex(&digest));
+    }
+
+    let canonical = path
+        .canonicalize()
+        .map_err(|error| format!("could not resolve backend {}: {error}", path.display()))?;
+    let mut file = std::fs::File::open(&canonical).map_err(|error| {
+        format!(
+            "could not open backend {} for fingerprinting: {error}",
+            canonical.display()
+        )
+    })?;
+    let mut hasher = Sha256::new();
+    let mut chunk = [0_u8; 64 * 1024];
+    loop {
+        let read = file.read(&mut chunk).map_err(|error| {
+            format!(
+                "could not read backend {} for fingerprinting: {error}",
+                canonical.display()
+            )
+        })?;
+        if read == 0 {
+            break;
+        }
+        hasher.update(&chunk[..read]);
+    }
+    let digest: [u8; 32] = hasher.finalize().into();
+    Ok(digest_hex(&digest))
+}
diff --git a/crates/cargo-oxide/src/commands/fmt.rs b/crates/cargo-oxide/src/commands/fmt.rs
new file mode 100644
index 0000000000..a503412d96
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/fmt.rs
@@ -0,0 +1,164 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::path::{Path, PathBuf};
+use std::process::Command;
+
+use super::*;
+
+// =============================================================================
+// Fmt command
+// =============================================================================
+
+/// Format (or check formatting of) every scope the `fmt` CI gate checks.
+///
+/// `.github/workflows/fmt.yml` checks four: the root workspace, the codegen
+/// backend crate, the cuda-macros device-only fixture, and every `Cargo.toml`
+/// under `examples/`, nested ones included. This mirrors that set on purpose --
+/// the reason CONTRIBUTING tells contributors to prefer this command over a
+/// bare `cargo fmt` is so the gate cannot fail on code they had no way to
+/// format, which only holds while the two cover the same ground.
+///
+/// In `check` mode, reports which files need formatting without modifying them.
+pub fn format_all(ctx: &Context, check: bool) {
+    let mode = if check { "Checking" } else { "Formatting" };
+    let mut failed = false;
+
+    println!("📦 {} root workspace...", mode);
+    if !run_cargo_fmt(&ctx.workspace_root, check) {
+        failed = true;
+    }
+
+    println!("📦 {} rustc-codegen-cuda...", mode);
+    if !run_cargo_fmt(&ctx.codegen_crate, check) {
+        failed = true;
+    }
+
+    // Its own `[workspace]`, so neither run above reaches it and the examples
+    // walk below never sees it either. The gate carries a dedicated step for
+    // exactly this reason.
+    let fixture = ctx
+        .workspace_root
+        .join("crates")
+        .join("cuda-macros")
+        .join("tests")
+        .join("device-only");
+    if fixture.join("Cargo.toml").is_file() {
+        println!("📦 {} cuda-macros device-only fixture...", mode);
+        if !run_cargo_fmt(&fixture, check) {
+            failed = true;
+        }
+    }
+
+    // One `--manifest-path` run per manifest found, rather than `cargo fmt
+    // --all` once per top-level example directory. Both reasons match the gate:
+    //
+    //   * `--all` stops at a nested `[workspace]` boundary, and two examples
+    //     declare one (`cutile_inter_kernel/simt`,
+    //     `interop_cubin_identity/device`), so neither was ever formatted here.
+    //   * `--all` also formats an example's path dependencies, which means
+    //     re-formatting the large shared workspaces once per example.
+    let mut manifests = Vec::new();
+    collect_example_manifests(&ctx.examples_dir, &mut manifests);
+    manifests.sort();
+
+    for manifest in &manifests {
+        let label = manifest
+            .parent()
+            .and_then(|dir| dir.strip_prefix(&ctx.examples_dir).ok())
+            .unwrap_or(Path::new("."))
+            .display()
+            .to_string();
+        println!("📦 {} example: {}...", mode, label);
+        if !run_cargo_fmt_manifest(manifest, check) {
+            failed = true;
+        }
+    }
+
+    if failed {
+        if check {
+            eprintln!();
+            eprintln!("❌ Some files need formatting. Run: cargo oxide fmt");
+        } else {
+            eprintln!();
+            eprintln!("⚠️  Some formatting commands failed (see above)");
+        }
+        std::process::exit(1);
+    } else {
+        println!();
+        if check {
+            println!("✅ All files are properly formatted");
+        } else {
+            println!("✅ All crates formatted");
+        }
+    }
+}
+
+/// Run `cargo fmt --all` in a single directory. Returns `true` on success.
+fn run_cargo_fmt(dir: &Path, check: bool) -> bool {
+    let mut cmd = Command::new("cargo");
+    cmd.arg("fmt").arg("--all").current_dir(dir);
+
+    if check {
+        cmd.arg("--check");
+    }
+
+    run_fmt_command(cmd)
+}
+
+/// Run `cargo fmt` for one manifest. Returns `true` on success.
+///
+/// No `--all`: the caller walks every manifest, so a workspace member is
+/// visited through its own manifest rather than through its parent's.
+fn run_cargo_fmt_manifest(manifest: &Path, check: bool) -> bool {
+    let mut cmd = Command::new("cargo");
+    cmd.arg("fmt").arg("--manifest-path").arg(manifest);
+
+    if check {
+        cmd.arg("--check");
+    }
+
+    run_fmt_command(cmd)
+}
+
+fn run_fmt_command(mut cmd: Command) -> bool {
+    match cmd.status() {
+        Ok(status) => status.success(),
+        Err(e) => {
+            eprintln!("  Failed to run cargo fmt: {}", e);
+            false
+        }
+    }
+}
+
+/// Collect every `Cargo.toml` under `dir`, recursively.
+///
+/// Mirrors the gate's `examples/**/Cargo.toml` glob, with one difference that
+/// only matters off CI: `target` directories are skipped. A fresh checkout has
+/// none, but a working tree does, and a packaged or vendored manifest under one
+/// is not a crate this repository formats.
+pub(super) fn collect_example_manifests(dir: &Path, out: &mut Vec<PathBuf>) {
+    let manifest = dir.join("Cargo.toml");
+    if manifest.is_file() {
+        out.push(manifest);
+    }
+
+    let Ok(entries) = std::fs::read_dir(dir) else {
+        return;
+    };
+
+    for entry in entries.flatten() {
+        let path = entry.path();
+        if !path.is_dir() {
+            continue;
+        }
+        let name = entry.file_name();
+        let name = name.to_string_lossy();
+        if name == "target" || name.starts_with('.') {
+            continue;
+        }
+        collect_example_manifests(&path, out);
+    }
+}
diff --git a/crates/cargo-oxide/src/commands/host_cargo.rs b/crates/cargo-oxide/src/commands/host_cargo.rs
new file mode 100644
index 0000000000..36b1f36724
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/host_cargo.rs
@@ -0,0 +1,528 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::path::{Path, PathBuf};
+use std::process::Command;
+
+use super::*;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn run_host_cargo(
+    ctx: &Context,
+    example: &str,
+    example_dir: &Path,
+    cargo_subcommand: &str,
+    features: Option<&str>,
+    bin: Option<&str>,
+    verbose: bool,
+    app_args: &[String],
+) {
+    let mut cmd = Command::new("cargo");
+    cmd.arg(cargo_subcommand)
+        .arg("--release")
+        .current_dir(example_dir);
+
+    if cargo_subcommand == "run"
+        && let Some(bin) = bin
+    {
+        cmd.args(["--bin", bin]);
+    }
+    if let Some(features) = features {
+        cmd.args(["--features", features]);
+    }
+    if cargo_subcommand == "run" && !app_args.is_empty() {
+        cmd.arg("--").args(app_args);
+    }
+
+    apply_config_env(&mut cmd, ctx);
+    apply_ld_library_path(&mut cmd, ctx);
+
+    if cargo_subcommand == "run" {
+        if let Some(bin) = bin {
+            println!("Building and running {} (bin: {})...", example, bin);
+        } else {
+            println!("Building and running {}...", example);
+        }
+    } else {
+        println!("Building host crate {}...", example);
+    }
+    println!();
+
+    if verbose {
+        cmd.env("CUDA_OXIDE_VERBOSE", "1");
+    }
+
+    let status = cmd.status().expect("Failed to run host cargo command");
+    if !status.success() {
+        eprintln!(
+            "\nHost cargo command failed with exit code: {:?}",
+            status.code()
+        );
+        std::process::exit(status.code().unwrap_or(1));
+    }
+}
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn codegen_build_host_binary(
+    ctx: &Context,
+    example: &str,
+    example_dir: &Path,
+    verbose: bool,
+    arch: Option<&str>,
+    detected_device_arch: Option<&str>,
+    features: Option<&str>,
+    bin: Option<&str>,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+    materialization: &MaterializationMode,
+) -> PathBuf {
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release"]).current_dir(example_dir);
+
+    if let Some(bin) = bin {
+        cmd.args(["--bin", bin]);
+    }
+    if let Some(features) = features {
+        cmd.args(["--features", features]);
+    }
+
+    apply_common_codegen_env(
+        &mut cmd,
+        ctx,
+        verbose,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+    );
+    apply_default_sanitizer_line_tables(&mut cmd, ctx, device_debug);
+    let fingerprint = sanitize_codegen_fingerprint(
+        ctx,
+        verbose,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+        arch,
+        detected_device_arch,
+        None,
+        materialization,
+    );
+    apply_codegen_configuration_or_exit(
+        &mut cmd,
+        ctx,
+        CodegenProfilePolicy::ReleaseLike,
+        &[],
+        &fingerprint,
+    );
+    apply_output_mode(&mut cmd, false, arch, materialization);
+    apply_device_arch_hint(&mut cmd, arch, detected_device_arch);
+
+    if let Some(bin) = bin {
+        println!("Building {} (bin: {})...", example, bin);
+    } else {
+        println!("Building {}...", example);
+    }
+    println!();
+
+    run_cargo_build_for_executable(&mut cmd, example_dir, bin).unwrap_or_else(|message| {
+        eprintln!("\nBuild failed: {message}");
+        std::process::exit(1);
+    })
+}
+
+pub(super) fn build_host_cargo(
+    ctx: &Context,
+    example: &str,
+    example_dir: &Path,
+    features: Option<&str>,
+    bin: Option<&str>,
+    verbose: bool,
+) -> PathBuf {
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release"]).current_dir(example_dir);
+
+    if let Some(bin) = bin {
+        cmd.args(["--bin", bin]);
+    }
+    if let Some(features) = features {
+        cmd.args(["--features", features]);
+    }
+
+    apply_config_env(&mut cmd, ctx);
+    apply_ld_library_path(&mut cmd, ctx);
+
+    if let Some(bin) = bin {
+        println!("Building host crate {} (bin: {})...", example, bin);
+    } else {
+        println!("Building host crate {}...", example);
+    }
+    println!();
+
+    if verbose {
+        cmd.env("CUDA_OXIDE_VERBOSE", "1");
+    }
+
+    run_cargo_build_for_executable(&mut cmd, example_dir, bin).unwrap_or_else(|message| {
+        eprintln!("\nHost cargo build failed: {message}");
+        std::process::exit(1);
+    })
+}
+
+pub(super) fn run_cargo_build_for_executable(
+    cmd: &mut Command,
+    manifest_dir: &Path,
+    explicit_bin: Option<&str>,
+) -> Result<PathBuf, String> {
+    let selection = cargo_executable_selection(manifest_dir, explicit_bin)?;
+
+    cmd.arg("--message-format=json-render-diagnostics");
+    let output = cmd
+        .output()
+        .map_err(|error| format!("could not start Cargo: {error}"))?;
+
+    let stderr = String::from_utf8_lossy(&output.stderr);
+    if !stderr.is_empty() {
+        eprint!("{stderr}");
+    }
+
+    let mut executables = Vec::<CargoExecutableArtifact>::new();
+    for line in String::from_utf8_lossy(&output.stdout).lines() {
+        let message: serde_json::Value = match serde_json::from_str(line) {
+            Ok(message) => message,
+            Err(_) => {
+                if !line.is_empty() {
+                    println!("{line}");
+                }
+                continue;
+            }
+        };
+
+        if let Some(rendered) = message
+            .get("message")
+            .and_then(|message| message.get("rendered"))
+            .and_then(|rendered| rendered.as_str())
+        {
+            eprint!("{rendered}");
+        }
+
+        if message.get("reason").and_then(|reason| reason.as_str()) != Some("compiler-artifact") {
+            continue;
+        }
+        let is_binary = message
+            .get("target")
+            .and_then(|target| target.get("kind"))
+            .and_then(|kind| kind.as_array())
+            .is_some_and(|kinds| kinds.iter().any(|kind| kind.as_str() == Some("bin")));
+        if !is_binary {
+            continue;
+        }
+        let Some(path) = message.get("executable").and_then(|path| path.as_str()) else {
+            continue;
+        };
+        let Some(package_id) = message
+            .get("package_id")
+            .and_then(|package_id| package_id.as_str())
+        else {
+            continue;
+        };
+        let Some(name) = message
+            .get("target")
+            .and_then(|target| target.get("name"))
+            .and_then(|name| name.as_str())
+        else {
+            continue;
+        };
+        executables.push(CargoExecutableArtifact {
+            package_id: package_id.to_string(),
+            target_name: name.to_string(),
+            path: PathBuf::from(path),
+        });
+    }
+
+    if !output.status.success() {
+        return Err(format!("Cargo exited with status {}", output.status));
+    }
+
+    select_cargo_executable_artifact(&selection, &executables)
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub(super) struct CargoExecutableSelection {
+    pub(super) packages: Vec<CargoSelectedPackage>,
+    pub(super) explicit_bin: Option<String>,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub(super) struct CargoSelectedPackage {
+    pub(super) package_id: String,
+    pub(super) package_name: String,
+    pub(super) default_run: Option<String>,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub(super) struct CargoExecutableArtifact {
+    pub(super) package_id: String,
+    pub(super) target_name: String,
+    pub(super) path: PathBuf,
+}
+
+pub(super) fn cargo_executable_selection(
+    manifest_dir: &Path,
+    explicit_bin: Option<&str>,
+) -> Result<CargoExecutableSelection, String> {
+    let metadata = cargo_metadata(manifest_dir)?;
+    let manifest_path = manifest_dir.join("Cargo.toml");
+    let manifest_path = manifest_path
+        .canonicalize()
+        .map_err(|error| format!("could not resolve {}: {error}", manifest_path.display()))?;
+
+    let packages = metadata
+        .get("packages")
+        .and_then(|packages| packages.as_array())
+        .ok_or_else(|| "Cargo metadata did not include packages".to_string())?;
+
+    let selected_packages = cargo_selected_packages(&metadata, packages, &manifest_path)?;
+    let packages = selected_packages
+        .into_iter()
+        .map(cargo_selected_package)
+        .collect::<Result<Vec<_>, _>>()?;
+    Ok(CargoExecutableSelection {
+        packages,
+        explicit_bin: explicit_bin.map(str::to_owned),
+    })
+}
+
+/// Return the packages Cargo selects for a command launched from
+/// `manifest_path`.
+///
+/// At a workspace root, Cargo uses `workspace.default-members` even when the
+/// root manifest also contains a `[package]`. Inside a member directory, Cargo
+/// instead selects that member. `cargo metadata` has already resolved the
+/// workspace defaults for us, so mirror that distinction here.
+fn cargo_selected_packages<'a>(
+    metadata: &serde_json::Value,
+    packages: &'a [serde_json::Value],
+    manifest_path: &Path,
+) -> Result<Vec<&'a serde_json::Value>, String> {
+    let workspace_root = metadata
+        .get("workspace_root")
+        .and_then(|path| path.as_str())
+        .ok_or_else(|| "Cargo metadata did not include workspace_root".to_string())?;
+    let workspace_manifest = PathBuf::from(workspace_root).join("Cargo.toml");
+    let workspace_manifest = workspace_manifest.canonicalize().map_err(|error| {
+        format!(
+            "could not resolve workspace manifest {}: {error}",
+            workspace_manifest.display()
+        )
+    })?;
+
+    if manifest_path != workspace_manifest {
+        let package = packages
+            .iter()
+            .find(|package| cargo_package_manifest_matches(package, manifest_path))
+            .ok_or_else(|| {
+                format!(
+                    "could not determine the Cargo package for {}",
+                    manifest_path.display()
+                )
+            })?;
+        return Ok(vec![package]);
+    }
+
+    let default_members = metadata
+        .get("workspace_default_members")
+        .and_then(|members| members.as_array())
+        .ok_or_else(|| "Cargo metadata did not include workspace_default_members".to_string())?;
+    if default_members.is_empty() {
+        return Err("Cargo selected no workspace default members".to_string());
+    }
+
+    default_members
+        .iter()
+        .map(|member| {
+            let package_id = member.as_str().ok_or_else(|| {
+                "Cargo metadata contained a non-string workspace default member".to_string()
+            })?;
+            packages
+                .iter()
+                .find(|package| cargo_package_id(package).ok() == Some(package_id))
+                .ok_or_else(|| {
+                    format!(
+                        "Cargo workspace default member `{package_id}` was missing from metadata packages"
+                    )
+                })
+        })
+        .collect()
+}
+
+fn cargo_package_manifest_matches(package: &serde_json::Value, manifest_path: &Path) -> bool {
+    package
+        .get("manifest_path")
+        .and_then(|path| path.as_str())
+        .and_then(|path| PathBuf::from(path).canonicalize().ok())
+        .is_some_and(|path| path == manifest_path)
+}
+
+fn cargo_metadata(manifest_dir: &Path) -> Result<serde_json::Value, String> {
+    let output = Command::new("cargo")
+        .args(["metadata", "--format-version=1", "--no-deps"])
+        .current_dir(manifest_dir)
+        .output()
+        .map_err(|error| format!("could not start cargo metadata: {error}"))?;
+
+    if !output.status.success() {
+        let stderr = String::from_utf8_lossy(&output.stderr);
+        return Err(format!(
+            "cargo metadata failed with status {}{}{}",
+            output.status,
+            if stderr.is_empty() { "" } else { ": " },
+            stderr.trim()
+        ));
+    }
+
+    serde_json::from_slice(&output.stdout)
+        .map_err(|error| format!("could not parse cargo metadata JSON: {error}"))
+}
+
+fn cargo_package_id(package: &serde_json::Value) -> Result<&str, String> {
+    package
+        .get("id")
+        .and_then(|id| id.as_str())
+        .ok_or_else(|| "Cargo metadata package is missing id".to_string())
+}
+
+fn cargo_package_name(package: &serde_json::Value) -> Result<&str, String> {
+    package
+        .get("name")
+        .and_then(|name| name.as_str())
+        .ok_or_else(|| "Cargo metadata package is missing name".to_string())
+}
+
+fn cargo_selected_package(package: &serde_json::Value) -> Result<CargoSelectedPackage, String> {
+    Ok(CargoSelectedPackage {
+        package_id: cargo_package_id(package)?.to_string(),
+        package_name: cargo_package_name(package)?.to_string(),
+        default_run: package
+            .get("default_run")
+            .and_then(|name| name.as_str())
+            .map(str::to_owned),
+    })
+}
+
+pub(super) fn select_cargo_executable_artifact(
+    selection: &CargoExecutableSelection,
+    executables: &[CargoExecutableArtifact],
+) -> Result<PathBuf, String> {
+    if let Some(explicit_bin) = selection.explicit_bin.as_deref() {
+        let matches = selection
+            .packages
+            .iter()
+            .flat_map(|package| {
+                executables
+                    .iter()
+                    .filter(move |artifact| {
+                        artifact.package_id == package.package_id
+                            && artifact.target_name == explicit_bin
+                    })
+                    .map(move |artifact| (package, artifact))
+            })
+            .collect::<Vec<_>>();
+        return match matches.as_slice() {
+            [(_, artifact)] => Ok(artifact.path.clone()),
+            [] => Err(format!(
+                "Cargo produced no executable artifact for target `{explicit_bin}` in selected packages {}",
+                selected_package_names(selection)
+            )),
+            matches => Err(format!(
+                "Cargo produced executable target `{explicit_bin}` for multiple selected packages: {}; run from a package directory",
+                matches
+                    .iter()
+                    .map(|(package, _)| package.package_name.as_str())
+                    .collect::<Vec<_>>()
+                    .join(", ")
+            )),
+        };
+    }
+
+    let mut candidates = Vec::new();
+    for package in &selection.packages {
+        let artifacts = executables
+            .iter()
+            .filter(|artifact| artifact.package_id == package.package_id)
+            .collect::<Vec<_>>();
+
+        if let Some(default_run) = package.default_run.as_deref() {
+            let matches = artifacts
+                .iter()
+                .copied()
+                .filter(|artifact| artifact.target_name == default_run)
+                .collect::<Vec<_>>();
+            match matches.as_slice() {
+                [artifact] => candidates.push((package, *artifact)),
+                [] => {
+                    return Err(format!(
+                        "Cargo produced no executable artifact for package `{}` default-run target `{default_run}`",
+                        package.package_name
+                    ));
+                }
+                _ => {
+                    return Err(format!(
+                        "Cargo produced multiple executable artifacts for package `{}` default-run `{default_run}`",
+                        package.package_name
+                    ));
+                }
+            }
+            continue;
+        }
+
+        // A selected package without an emitted binary may simply be a
+        // library-only workspace member. A package with `default-run` is
+        // handled above: silently skipping its missing target could launch a
+        // different default member's program instead.
+        if artifacts.is_empty() {
+            continue;
+        }
+
+        match artifacts.as_slice() {
+            [artifact] => candidates.push((package, *artifact)),
+            artifacts => {
+                let choices = artifacts
+                    .iter()
+                    .map(|artifact| artifact.target_name.as_str())
+                    .collect::<Vec<_>>()
+                    .join(", ");
+                return Err(format!(
+                    "Cargo produced multiple executable targets for package `{}`: {choices}; pass --bin <name>",
+                    package.package_name
+                ));
+            }
+        }
+    }
+
+    match candidates.as_slice() {
+        [(_, artifact)] => Ok(artifact.path.clone()),
+        [] => Err(format!(
+            "Cargo produced no executable artifact for selected packages {}",
+            selected_package_names(selection)
+        )),
+        candidates => Err(format!(
+            "Cargo produced executables for multiple selected packages: {}; pass --bin <name> that is unique among them",
+            candidates
+                .iter()
+                .map(|(package, _)| package.package_name.as_str())
+                .collect::<Vec<_>>()
+                .join(", ")
+        )),
+    }
+}
+
+fn selected_package_names(selection: &CargoExecutableSelection) -> String {
+    selection
+        .packages
+        .iter()
+        .map(|package| package.package_name.as_str())
+        .collect::<Vec<_>>()
+        .join(", ")
+}
diff --git a/crates/cargo-oxide/src/commands/interop.rs b/crates/cargo-oxide/src/commands/interop.rs
new file mode 100644
index 0000000000..41718a3358
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/interop.rs
@@ -0,0 +1,938 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::path::{Path, PathBuf};
+use std::process::Command;
+
+use super::*;
+
+// =============================================================================
+// Interop host/device workflow
+// =============================================================================
+
+#[derive(Debug, Clone)]
+pub(super) struct InteropConfig {
+    pub(super) kind: Option<String>,
+    pub(super) device_crates: Vec<DeviceCrateConfig>,
+}
+
+#[derive(Debug, Clone)]
+pub(super) struct DeviceCrateConfig {
+    pub(super) manifest_path: PathBuf,
+    pub(super) artifact_dir: PathBuf,
+    pub(super) artifact_name: Option<String>,
+    pub(super) artifact_kind: InteropArtifactKind,
+    pub(super) source_identity: bool,
+    pub(super) bin: Option<String>,
+}
+
+#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
+pub(super) enum InteropArtifactKind {
+    #[default]
+    Ptx,
+    Cubin,
+}
+
+impl InteropArtifactKind {
+    fn extension(self) -> &'static str {
+        match self {
+            Self::Ptx => "ptx",
+            Self::Cubin => "cubin",
+        }
+    }
+
+    fn emits_nvvm_ir(self) -> bool {
+        self == Self::Cubin
+    }
+}
+
+#[derive(Debug, Clone, Eq, PartialEq)]
+pub(super) struct InteropBinaryTarget {
+    pub(super) source_path: PathBuf,
+}
+
+#[derive(Clone, Copy, Debug, Default)]
+pub(super) struct InteropDeviceBuildOptions {
+    pub(super) no_fmad: bool,
+    pub(super) unchecked_indexing: bool,
+    pub(super) sanitizer_line_tables: bool,
+}
+
+impl InteropDeviceBuildOptions {
+    pub(super) fn standard(no_fmad: bool, unchecked_indexing: bool) -> Self {
+        Self {
+            no_fmad,
+            unchecked_indexing,
+            sanitizer_line_tables: false,
+        }
+    }
+}
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn codegen_run_interop(
+    ctx: &Context,
+    example: &str,
+    example_dir: &Path,
+    interop: &InteropConfig,
+    verbose: bool,
+    emit_nvvm_ir: bool,
+    arch: Option<&str>,
+    detected_device_arch: Option<&str>,
+    features: Option<&str>,
+    device_features: Option<&str>,
+    bin: Option<&str>,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    materialization: &MaterializationMode,
+    app_args: &[String],
+) {
+    reject_interop_output_mode(emit_nvvm_ir, materialization);
+
+    println!("=========================================");
+    println!("RUSTC-CODEGEN-CUDA INTEROP: {}", example);
+    println!("=========================================");
+    if let Some(kind) = &interop.kind {
+        println!("Interop kind: {}", kind);
+    }
+    if let Some(dev) = detected_device_arch {
+        println!("Detected GPU arch: {dev} (via nvidia-smi)");
+    }
+    println!();
+
+    build_interop_device_crates(
+        ctx,
+        example_dir,
+        interop,
+        verbose,
+        arch,
+        detected_device_arch,
+        device_features,
+        InteropDeviceBuildOptions::standard(no_fmad, unchecked_indexing),
+        materialization,
+    );
+    run_host_cargo(
+        ctx,
+        example,
+        example_dir,
+        "run",
+        features,
+        bin,
+        verbose,
+        app_args,
+    );
+}
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn codegen_build_interop(
+    ctx: &Context,
+    example: &str,
+    example_dir: &Path,
+    interop: &InteropConfig,
+    verbose: bool,
+    emit_nvvm_ir: bool,
+    arch: Option<&str>,
+    features: Option<&str>,
+    device_features: Option<&str>,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    materialization: &MaterializationMode,
+) {
+    reject_interop_output_mode(emit_nvvm_ir, materialization);
+
+    println!("=========================================");
+    println!("RUSTC-CODEGEN-CUDA INTEROP BUILD: {}", example);
+    println!("=========================================");
+    if let Some(kind) = &interop.kind {
+        println!("Interop kind: {}", kind);
+    }
+    println!();
+
+    // `build` may cross-compile for another machine, so no device-arch hint:
+    // only an explicit `--arch` pins the target here.
+    build_interop_device_crates(
+        ctx,
+        example_dir,
+        interop,
+        verbose,
+        arch,
+        None,
+        device_features,
+        InteropDeviceBuildOptions::standard(no_fmad, unchecked_indexing),
+        materialization,
+    );
+    run_host_cargo(
+        ctx,
+        example,
+        example_dir,
+        "build",
+        features,
+        None,
+        verbose,
+        &[],
+    );
+}
+
+pub(super) fn reject_interop_output_mode(
+    emit_nvvm_ir: bool,
+    materialization: &MaterializationMode,
+) {
+    if materialization.enabled() {
+        eprintln!("Error: --materialize-cubin is not supported for metadata interop examples yet.");
+        eprintln!(
+            "Declare `artifact-kind = \"cubin\"` on each device crate that requires native output."
+        );
+        std::process::exit(2);
+    }
+    if emit_nvvm_ir {
+        eprintln!("Error: --emit-nvvm-ir is not supported for metadata interop examples yet.");
+        eprintln!("Interop device output is selected by each metadata `artifact-kind`.");
+        std::process::exit(2);
+    }
+}
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn build_interop_device_crates(
+    ctx: &Context,
+    example_dir: &Path,
+    interop: &InteropConfig,
+    verbose: bool,
+    arch: Option<&str>,
+    detected_device_arch: Option<&str>,
+    device_features: Option<&str>,
+    options: InteropDeviceBuildOptions,
+    materialization: &MaterializationMode,
+) {
+    for device_crate in &interop.device_crates {
+        build_interop_device_crate(
+            ctx,
+            example_dir,
+            device_crate,
+            verbose,
+            arch,
+            detected_device_arch,
+            device_features,
+            options,
+            materialization,
+        );
+    }
+}
+
+pub(super) fn interop_device_artifact_name(
+    manifest_path: &Path,
+    device_crate: &DeviceCrateConfig,
+) -> String {
+    device_crate.artifact_name.clone().unwrap_or_else(|| {
+        normalize_crate_name(&interop_device_cargo_target_name(
+            manifest_path,
+            device_crate,
+        ))
+    })
+}
+
+pub(super) fn interop_device_cargo_target_name(
+    manifest_path: &Path,
+    device_crate: &DeviceCrateConfig,
+) -> String {
+    device_crate
+        .bin
+        .clone()
+        .unwrap_or_else(|| package_name_from_manifest(manifest_path))
+}
+
+pub(super) fn interop_device_artifact_path(
+    example_dir: &Path,
+    device_crate: &DeviceCrateConfig,
+    artifact_name: &str,
+) -> PathBuf {
+    example_dir.join(&device_crate.artifact_dir).join(format!(
+        "{}.{}",
+        artifact_stem(artifact_name),
+        device_crate.artifact_kind.extension()
+    ))
+}
+
+/// Pre-build requirement check for `artifact-kind = "cubin"` device crates.
+///
+/// A native cubin needs a deliberate target, so require one from `--arch`,
+/// `CUDA_OXIDE_TARGET`, project configuration, or the device detected by
+/// `run` before spending a device build. This is a requirement check only:
+/// the arch the finalizer actually compiles for comes from the
+/// backend-recorded `.target` sidecar (see
+/// [`read_interop_recorded_target`]), because the backend may resolve a
+/// different arch than the hint (e.g. escalate a detected `sm_120a` to the
+/// `sm_90a` WGMMA floor).
+pub(super) fn interop_cubin_target(
+    arch: Option<&str>,
+    detected_device_arch: Option<&str>,
+) -> Result<cuda_artifact_finalizer::CudaArch, String> {
+    let target = arch
+        .map(str::to_owned)
+        .or_else(|| std::env::var("CUDA_OXIDE_TARGET").ok())
+        .or_else(|| detected_device_arch.map(str::to_owned))
+        .ok_or_else(|| {
+            "cubin interop artifacts require --arch, CUDA_OXIDE_TARGET, a configured target, or a detected run device"
+                .to_string()
+        })?;
+    parse_nvvm_arch(&target)
+        .map_err(|error| format!("invalid cubin interop target {target:?}: {error}"))
+}
+
+/// Path of the NVVM IR a cubin-kind device crate emits into its artifact dir.
+fn interop_device_ir_path(
+    example_dir: &Path,
+    device_crate: &DeviceCrateConfig,
+    artifact_name: &str,
+) -> PathBuf {
+    example_dir
+        .join(&device_crate.artifact_dir)
+        .join(format!("{}.ll", artifact_stem(artifact_name)))
+}
+
+/// Read the CUDA target the backend recorded next to an emitted NVVM IR.
+///
+/// The backend publishes `<name>.target` last, after the `.ll` and
+/// `.options`: it is both the authoritative arch record (NVVM IR does not
+/// encode its target) and the completion marker saying the sibling
+/// `.options` file is present and required (see
+/// `write_nvvm_target_sidecar` in mir-importer). A missing or malformed
+/// sidecar therefore means the device build did not complete its artifact
+/// contract, never that some other arch should be guessed.
+pub(super) fn read_interop_recorded_target(ir_path: &Path) -> Result<String, String> {
+    let path = ir_path.with_extension("target");
+    let text = std::fs::read_to_string(&path).map_err(|error| {
+        format!(
+            "device build did not record its CUDA target at {} ({error}); \
+             the .target sidecar is the backend's completion marker, so the \
+             emitted NVVM IR cannot be trusted without it",
+            path.display()
+        )
+    })?;
+    let mut lines = text.lines();
+    let target = lines.next().unwrap_or_default().trim();
+    if target.is_empty() {
+        return Err(format!("recorded CUDA target {} is empty", path.display()));
+    }
+    match (lines.next(), lines.next()) {
+        (None, None) => Ok(target.to_string()),
+        (Some(marker), None) if marker == oxide_artifacts::COMPILE_OPTIONS_TARGET_MARKER => {
+            let options_path = ir_path.with_extension("options");
+            if !options_path.is_file() {
+                return Err(format!(
+                    "recorded CUDA target {} requires the sibling compile options {}, which is missing",
+                    path.display(),
+                    options_path.display()
+                ));
+            }
+            Ok(target.to_string())
+        }
+        _ => Err(format!(
+            "recorded CUDA target {} has an unrecognized format: {:?}",
+            path.display(),
+            text.trim()
+        )),
+    }
+}
+
+/// Read the `.target sm_XX` directive from an emitted PTX artifact.
+///
+/// PTX carries its own target record, so the identity sidecar can state the
+/// arch the artifact was actually compiled for instead of echoing a request
+/// hint (which the backend is allowed to override).
+pub(super) fn ptx_recorded_target(ptx_path: &Path) -> Result<String, String> {
+    let text = std::fs::read_to_string(ptx_path).map_err(|error| {
+        format!(
+            "could not read emitted PTX at {}: {error}",
+            ptx_path.display()
+        )
+    })?;
+    let document = ptx_parse::Document::parse(&text).map_err(|error| {
+        format!(
+            "could not parse emitted PTX {} to read its target: {error}",
+            ptx_path.display()
+        )
+    })?;
+    document
+        .directives()
+        .iter()
+        .find(|directive| directive.name() == ".target")
+        .and_then(|directive| ptx_parse::split_top_level(directive.arguments()))
+        .and_then(|arguments| arguments.first().copied())
+        .map(str::to_string)
+        .filter(|target| !target.is_empty())
+        .ok_or_else(|| {
+            format!(
+                "emitted PTX {} does not declare a .target directive",
+                ptx_path.display()
+            )
+        })
+}
+
+/// The CUDA target an interop device artifact was actually built for, read
+/// from the emitted artifact itself: the backend `.target` sidecar for
+/// cubin (the same record the finalizer compiled with) and the `.target`
+/// directive for PTX.
+pub(super) fn interop_artifact_recorded_target(
+    example_dir: &Path,
+    device_crate: &DeviceCrateConfig,
+    artifact_name: &str,
+) -> Result<String, String> {
+    match device_crate.artifact_kind {
+        InteropArtifactKind::Ptx => ptx_recorded_target(&interop_device_artifact_path(
+            example_dir,
+            device_crate,
+            artifact_name,
+        )),
+        InteropArtifactKind::Cubin => read_interop_recorded_target(&interop_device_ir_path(
+            example_dir,
+            device_crate,
+            artifact_name,
+        )),
+    }
+}
+
+fn finalize_interop_device_artifact(
+    example_dir: &Path,
+    device_crate: &DeviceCrateConfig,
+    artifact_name: &str,
+) -> PathBuf {
+    let artifact_path = interop_device_artifact_path(example_dir, device_crate, artifact_name);
+    match device_crate.artifact_kind {
+        InteropArtifactKind::Ptx => artifact_path,
+        InteropArtifactKind::Cubin => {
+            let ir_path = interop_device_ir_path(example_dir, device_crate, artifact_name);
+            // The backend-recorded target, not the CLI/env/detected hint:
+            // the backend may have resolved a different arch, and this
+            // sidecar doubles as the completion marker for the .ll/.options
+            // pair consumed below.
+            let recorded_target = read_interop_recorded_target(&ir_path).unwrap_or_else(|error| {
+                eprintln!("Error: {error}");
+                std::process::exit(1);
+            });
+            let target = parse_nvvm_arch(&recorded_target).unwrap_or_else(|error| {
+                eprintln!(
+                    "Error: invalid recorded CUDA target {recorded_target:?} next to {}: {error}",
+                    ir_path.display()
+                );
+                std::process::exit(1);
+            });
+            let ir = std::fs::read(&ir_path).unwrap_or_else(|error| {
+                eprintln!(
+                    "Error: could not read emitted NVVM IR at {}: {error}",
+                    ir_path.display()
+                );
+                std::process::exit(1);
+            });
+            let options_path = ir_path.with_extension("options");
+            let options_text = std::fs::read_to_string(&options_path).unwrap_or_else(|error| {
+                eprintln!(
+                    "Error: could not read emitted compile options at {}: {error}",
+                    options_path.display()
+                );
+                std::process::exit(1);
+            });
+            let compile_options =
+                oxide_artifacts::ArtifactCompileOptions::from_sidecar_text(&options_text)
+                    .unwrap_or_else(|error| {
+                        eprintln!(
+                            "Error: invalid emitted compile options at {}: {error}",
+                            options_path.display()
+                        );
+                        std::process::exit(1);
+                    });
+            let finalizer = cuda_artifact_finalizer::Finalizer::discover().unwrap_or_else(|error| {
+                eprintln!("Error: could not initialize the CUDA artifact finalizer: {error}");
+                eprintln!(
+                    "libNVVM and nvJitLink ship with the CUDA Toolkit; run `cargo oxide doctor` to check discovery."
+                );
+                std::process::exit(1);
+            });
+            let options = finalization_options_from_artifact(&target, compile_options);
+            let cubin = finalizer
+                .materialize_nvvm_ir(artifact_name, &ir, &options)
+                .unwrap_or_else(|error| {
+                    eprintln!(
+                        "Error: could not finalize {} for {}: {error}",
+                        ir_path.display(),
+                        target.sm()
+                    );
+                    std::process::exit(1);
+                });
+            let temporary_path = artifact_path.with_extension("cubin.tmp");
+            std::fs::write(&temporary_path, cubin).unwrap_or_else(|error| {
+                eprintln!(
+                    "Error: could not write temporary cubin {}: {error}",
+                    temporary_path.display()
+                );
+                std::process::exit(1);
+            });
+            std::fs::rename(&temporary_path, &artifact_path).unwrap_or_else(|error| {
+                eprintln!(
+                    "Error: could not install cubin {}: {error}",
+                    artifact_path.display()
+                );
+                std::process::exit(1);
+            });
+            artifact_path
+        }
+    }
+}
+
+#[allow(clippy::too_many_arguments)]
+fn build_interop_device_crate(
+    ctx: &Context,
+    example_dir: &Path,
+    device_crate: &DeviceCrateConfig,
+    verbose: bool,
+    arch: Option<&str>,
+    detected_device_arch: Option<&str>,
+    device_features: Option<&str>,
+    options: InteropDeviceBuildOptions,
+    materialization: &MaterializationMode,
+) {
+    let manifest_path = example_dir.join(&device_crate.manifest_path);
+    let manifest_path = manifest_path.canonicalize().unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not resolve device crate manifest {}: {}",
+            manifest_path.display(),
+            e
+        );
+        std::process::exit(1);
+    });
+    let device_dir = manifest_path.parent().unwrap_or(example_dir);
+    // One `cargo metadata` invocation answers both consumers: bin-target
+    // resolution before the build and the uplifted depfile location after
+    // it. Skip it entirely when neither feature is requested.
+    let cargo_metadata = (device_crate.bin.is_some() || device_crate.source_identity).then(|| {
+        interop_cargo_metadata(ctx, device_dir, &manifest_path).unwrap_or_else(|error| {
+            eprintln!("Error: could not query cargo metadata for the device crate: {error}");
+            std::process::exit(1);
+        })
+    });
+    let binary_target = device_crate.bin.as_deref().map(|bin| {
+        let metadata = cargo_metadata
+            .as_ref()
+            .expect("cargo metadata is fetched whenever a bin target is configured");
+        interop_binary_target_from_metadata(metadata, &manifest_path, bin).unwrap_or_else(|error| {
+            eprintln!("Error: could not resolve device binary target: {error}");
+            std::process::exit(1);
+        })
+    });
+    let artifact_dir = example_dir.join(&device_crate.artifact_dir);
+    std::fs::create_dir_all(&artifact_dir).unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not create device artifact directory {}: {}",
+            artifact_dir.display(),
+            e
+        );
+        std::process::exit(1);
+    });
+
+    if device_crate.artifact_kind == InteropArtifactKind::Cubin
+        && let Err(error) = interop_cubin_target(arch, detected_device_arch)
+    {
+        eprintln!("Error: {error}");
+        std::process::exit(2);
+    }
+
+    let artifact_name = interop_device_artifact_name(&manifest_path, device_crate);
+    clean_generated_files(&artifact_dir, &artifact_name);
+    if let Some(target) = &binary_target {
+        touch_source_file(&target.source_path);
+    } else {
+        touch_main_rs(device_dir);
+    }
+
+    println!("Building device crate {}...", manifest_path.display());
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release", "--manifest-path"])
+        .arg(&manifest_path)
+        .current_dir(device_dir);
+    if let Some(device_features) = device_features {
+        cmd.args(["--features", device_features]);
+    }
+    if let Some(bin) = &device_crate.bin {
+        cmd.args(["--bin", bin]);
+    }
+
+    apply_interop_device_codegen_options(&mut cmd, ctx, verbose, options);
+    let fingerprint = interop_codegen_fingerprint(
+        ctx,
+        verbose,
+        options.no_fmad,
+        options.unchecked_indexing,
+        DeviceDebug::Off,
+        arch,
+        detected_device_arch,
+        &artifact_dir,
+        device_crate.artifact_kind.emits_nvvm_ir(),
+        device_features,
+        options.sanitizer_line_tables,
+        materialization,
+    );
+    apply_codegen_configuration_or_exit(
+        &mut cmd,
+        ctx,
+        CodegenProfilePolicy::ReleaseLike,
+        &[],
+        &fingerprint,
+    );
+    // This is an internal artifact contract, so it must override a project
+    // `[env]` default for the same variable.
+    cmd.env("CUDA_OXIDE_PTX_DIR", &artifact_dir);
+    apply_output_mode(
+        &mut cmd,
+        device_crate.artifact_kind.emits_nvvm_ir(),
+        arch,
+        materialization,
+    );
+    apply_device_arch_hint(&mut cmd, arch, detected_device_arch);
+
+    let status = cmd.status().expect("Failed to build interop device crate");
+    if !status.success() {
+        eprintln!(
+            "\nDevice crate build failed with exit code: {:?}",
+            status.code()
+        );
+        std::process::exit(status.code().unwrap_or(1));
+    }
+
+    let artifact_path = finalize_interop_device_artifact(example_dir, device_crate, &artifact_name);
+    if !artifact_path.exists() {
+        eprintln!(
+            "Error: device crate build succeeded but did not produce {}",
+            artifact_path.display()
+        );
+        std::process::exit(1);
+    }
+    println!(
+        "{} written: {}",
+        device_crate.artifact_kind.extension().to_ascii_uppercase(),
+        artifact_path.display()
+    );
+    if device_crate.source_identity {
+        // The identity records the arch the artifact was actually built
+        // for, read back from the emitted artifact, never the request hint.
+        let artifact_target =
+            interop_artifact_recorded_target(example_dir, device_crate, &artifact_name)
+                .unwrap_or_else(|error| {
+                    eprintln!(
+                        "Error: could not determine the built CUDA target for {}: {error}",
+                        artifact_path.display()
+                    );
+                    std::process::exit(1);
+                });
+        let cargo_target_name = interop_device_cargo_target_name(&manifest_path, device_crate);
+        let metadata = cargo_metadata
+            .as_ref()
+            .expect("cargo metadata is fetched whenever source-identity is configured");
+        let cargo_target_dir = cargo_target_directory(metadata).unwrap_or_else(|error| {
+            eprintln!("Error: could not locate the device cargo target directory: {error}");
+            std::process::exit(1);
+        });
+        let depfile_path = release_depfile_path(&cargo_target_dir, &cargo_target_name);
+        if !depfile_path.is_file() {
+            eprintln!(
+                "Error: device crate build succeeded but did not produce dependency file {}",
+                depfile_path.display()
+            );
+            std::process::exit(1);
+        }
+        let identity_base = artifact_path.parent().unwrap_or(example_dir);
+        let identity_path = crate::artifact_identity::write(
+            &artifact_path,
+            &depfile_path,
+            &manifest_path,
+            identity_base,
+            &cargo_target_dir,
+            &artifact_target,
+            device_features,
+        )
+        .unwrap_or_else(|error| {
+            eprintln!(
+                "Error: could not write source identity for {}: {error}",
+                artifact_path.display()
+            );
+            std::process::exit(1);
+        });
+        println!("Artifact identity written: {}", identity_path.display());
+    }
+}
+
+pub(super) fn load_interop_config(example_dir: &Path) -> Option<InteropConfig> {
+    let manifest_path = example_dir.join("Cargo.toml");
+    let source = std::fs::read_to_string(&manifest_path).unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not read manifest {}: {}",
+            manifest_path.display(),
+            e
+        );
+        std::process::exit(1);
+    });
+    let document: toml::Value = toml::from_str(&source).unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not parse manifest {}: {}",
+            manifest_path.display(),
+            e
+        );
+        std::process::exit(1);
+    });
+
+    let oxide = document
+        .get("package")
+        .and_then(|value| value.get("metadata"))
+        .and_then(|value| value.get("cuda-oxide"))?;
+
+    let kind = oxide.get("interop").and_then(|value| {
+        value.as_str().map(str::to_string).or_else(|| {
+            value
+                .get("kind")
+                .and_then(|kind| kind.as_str())
+                .map(str::to_string)
+        })
+    });
+
+    let device_crates = oxide
+        .get("device-crates")
+        .and_then(|value| value.as_array())
+        .map(|items| {
+            items
+                .iter()
+                .map(|item| parse_device_crate_config(item, &manifest_path))
+                .collect()
+        })
+        .unwrap_or_default();
+
+    Some(InteropConfig {
+        kind,
+        device_crates,
+    })
+}
+
+fn parse_device_crate_config(value: &toml::Value, manifest_path: &Path) -> DeviceCrateConfig {
+    let table = value.as_table().unwrap_or_else(|| {
+        eprintln!(
+            "Error: each package.metadata.cuda-oxide.device-crates entry in {} must be a table",
+            manifest_path.display()
+        );
+        std::process::exit(1);
+    });
+
+    let device_manifest = required_metadata_string(table, "manifest-path", manifest_path);
+    let artifact_dir = optional_metadata_string(table, "artifact-dir")
+        .or_else(|| optional_metadata_string(table, "ptx-dir"))
+        .map(PathBuf::from)
+        .unwrap_or_else(|| {
+            Path::new(&device_manifest)
+                .parent()
+                .unwrap_or_else(|| Path::new("."))
+                .to_path_buf()
+        });
+    let artifact_name = optional_metadata_string(table, "artifact-name");
+    let artifact_kind = match optional_metadata_string(table, "artifact-kind").as_deref() {
+        None | Some("ptx") => InteropArtifactKind::Ptx,
+        Some("cubin") => InteropArtifactKind::Cubin,
+        Some(value) => {
+            eprintln!(
+                "Error: package.metadata.cuda-oxide.device-crates `artifact-kind` in {} must be `ptx` or `cubin`, got {value:?}",
+                manifest_path.display()
+            );
+            std::process::exit(2);
+        }
+    };
+    let source_identity = match table.get("source-identity") {
+        None => false,
+        Some(value) => value.as_bool().unwrap_or_else(|| {
+            eprintln!(
+                "Error: package.metadata.cuda-oxide.device-crates `source-identity` in {} must be a boolean",
+                manifest_path.display()
+            );
+            std::process::exit(2);
+        }),
+    };
+    let bin = optional_metadata_string(table, "bin");
+
+    DeviceCrateConfig {
+        manifest_path: PathBuf::from(device_manifest),
+        artifact_dir,
+        artifact_name,
+        artifact_kind,
+        source_identity,
+        bin,
+    }
+}
+
+fn required_metadata_string(table: &toml::Table, key: &str, manifest_path: &Path) -> String {
+    optional_metadata_string(table, key).unwrap_or_else(|| {
+        eprintln!(
+            "Error: package.metadata.cuda-oxide.device-crates entry in {} is missing string field `{}`",
+            manifest_path.display(),
+            key
+        );
+        std::process::exit(1);
+    })
+}
+
+fn optional_metadata_string(table: &toml::Table, key: &str) -> Option<String> {
+    table
+        .get(key)
+        .and_then(|value| value.as_str())
+        .map(str::to_string)
+}
+
+fn package_name_from_manifest(manifest_path: &Path) -> String {
+    let source = std::fs::read_to_string(manifest_path).unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not read device manifest {}: {}",
+            manifest_path.display(),
+            e
+        );
+        std::process::exit(1);
+    });
+    let document: toml::Value = toml::from_str(&source).unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not parse device manifest {}: {}",
+            manifest_path.display(),
+            e
+        );
+        std::process::exit(1);
+    });
+
+    document
+        .get("package")
+        .and_then(|value| value.get("name"))
+        .and_then(|value| value.as_str())
+        .map(str::to_string)
+        .unwrap_or_else(|| {
+            eprintln!(
+                "Error: device manifest {} is missing package.name",
+                manifest_path.display()
+            );
+            std::process::exit(1);
+        })
+}
+
+fn normalize_crate_name(package_name: &str) -> String {
+    package_name.replace('-', "_")
+}
+
+/// The target directory cargo reports for a device crate, which locates both
+/// its uplifted build products and the build outputs the identity sidecar
+/// must exclude.
+pub(super) fn cargo_target_directory(metadata: &serde_json::Value) -> Result<PathBuf, String> {
+    metadata
+        .get("target_directory")
+        .and_then(|value| value.as_str())
+        .map(PathBuf::from)
+        .ok_or_else(|| "cargo metadata omitted target_directory".to_string())
+}
+
+/// Where cargo uplifts the dep-info file for a release binary target.
+///
+/// Cargo names the uplifted copy after the bin target verbatim, hyphens
+/// preserved: building the `simt-device` target writes
+/// `target/release/simt-device` and `target/release/simt-device.d` (this
+/// repo's own build writes `target/debug/cargo-oxide.d`). Only the internal
+/// per-unit copies under `target/release/deps/` use the underscore-normalized
+/// crate name, so the stem here must NOT be `normalize_crate_name`d.
+pub(super) fn release_depfile_path(cargo_target_dir: &Path, cargo_target_name: &str) -> PathBuf {
+    cargo_target_dir
+        .join("release")
+        .join(format!("{cargo_target_name}.d"))
+}
+
+fn interop_cargo_metadata(
+    ctx: &Context,
+    device_dir: &Path,
+    manifest_path: &Path,
+) -> Result<serde_json::Value, String> {
+    let mut command = Command::new("cargo");
+    command
+        .args([
+            "metadata",
+            "--format-version=1",
+            "--no-deps",
+            "--manifest-path",
+        ])
+        .arg(manifest_path)
+        .current_dir(device_dir);
+    apply_config_env(&mut command, ctx);
+    let output = command
+        .output()
+        .map_err(|error| format!("could not start cargo metadata: {error}"))?;
+    if !output.status.success() {
+        let stderr = String::from_utf8_lossy(&output.stderr);
+        return Err(format!(
+            "cargo metadata failed with status {}{}{}",
+            output.status,
+            if stderr.is_empty() { "" } else { ": " },
+            stderr.trim()
+        ));
+    }
+    serde_json::from_slice(&output.stdout)
+        .map_err(|error| format!("could not parse cargo metadata JSON: {error}"))
+}
+
+pub(super) fn interop_binary_target_from_metadata(
+    metadata: &serde_json::Value,
+    manifest_path: &Path,
+    bin: &str,
+) -> Result<InteropBinaryTarget, String> {
+    let packages = metadata
+        .get("packages")
+        .and_then(serde_json::Value::as_array)
+        .ok_or_else(|| "cargo metadata omitted packages".to_string())?;
+    let package = packages
+        .iter()
+        .find(|package| {
+            package
+                .get("manifest_path")
+                .and_then(serde_json::Value::as_str)
+                .is_some_and(|path| Path::new(path) == manifest_path)
+        })
+        .ok_or_else(|| {
+            format!(
+                "cargo metadata omitted package for manifest {}",
+                manifest_path.display()
+            )
+        })?;
+    let targets = package
+        .get("targets")
+        .and_then(serde_json::Value::as_array)
+        .ok_or_else(|| "cargo metadata omitted package targets".to_string())?;
+    let is_binary = |target: &&serde_json::Value| {
+        target
+            .get("kind")
+            .and_then(serde_json::Value::as_array)
+            .is_some_and(|kinds| kinds.iter().any(|kind| kind.as_str() == Some("bin")))
+    };
+    let target = targets
+        .iter()
+        .filter(is_binary)
+        .find(|target| target.get("name").and_then(serde_json::Value::as_str) == Some(bin))
+        .ok_or_else(|| {
+            let mut available = targets
+                .iter()
+                .filter(is_binary)
+                .filter_map(|target| target.get("name").and_then(serde_json::Value::as_str))
+                .collect::<Vec<_>>();
+            available.sort_unstable();
+            format!(
+                "manifest {} has no binary target {bin:?}; available binary targets: {}",
+                manifest_path.display(),
+                if available.is_empty() {
+                    "<none>".to_string()
+                } else {
+                    available.join(", ")
+                }
+            )
+        })?;
+    let source_path = target
+        .get("src_path")
+        .and_then(serde_json::Value::as_str)
+        .map(PathBuf::from)
+        .ok_or_else(|| format!("cargo metadata omitted source path for binary target {bin:?}"))?;
+    Ok(InteropBinaryTarget { source_path })
+}
diff --git a/crates/cargo-oxide/src/commands/ltoir.rs b/crates/cargo-oxide/src/commands/ltoir.rs
new file mode 100644
index 0000000000..fa8a151932
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/ltoir.rs
@@ -0,0 +1,220 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::path::Path;
+
+use super::*;
+
+// =============================================================================
+// emit-ltoir command
+// =============================================================================
+
+/// Compile a crate's device code to a binary LTOIR artifact in one step.
+///
+/// `cargo oxide build --emit-nvvm-ir` produces NVVM IR, which a consumer then
+/// has to run through libNVVM separately to get linkable LTOIR. This folds both
+/// halves into one command for the Tile-to-SIMT interop workflow (#96): it
+/// builds the crate in NVVM IR mode, then compiles the emitted `<crate>.ll`
+/// with libNVVM `-gen-lto` and writes `<crate>.ltoir` (or `output`) plus the
+/// matching `.target` and `.options` files used for runtime loading and final
+/// nvJitLink policy.
+///
+/// `arch` is required because LTOIR is architecture-specific. It accepts
+/// `sm_XX`, `compute_XX`, or a bare `XX`, all mapped to libNVVM's
+/// `-arch=compute_XX`.
+#[allow(clippy::too_many_arguments)]
+pub fn emit_ltoir(
+    ctx: &Context,
+    example: &str,
+    arch: &str,
+    features: Option<&str>,
+    output: Option<&Path>,
+    verbose: bool,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+) {
+    let example_dir = if ctx.is_workspace {
+        resolve_example_dir(ctx, example)
+    } else {
+        ctx.workspace_root.clone()
+    };
+
+    if load_interop_config(&example_dir).is_some_and(|config| !config.device_crates.is_empty()) {
+        eprintln!("Error: emit-ltoir does not support metadata interop examples.");
+        eprintln!("Point it at a single SIMT device crate instead.");
+        std::process::exit(1);
+    }
+
+    // Normalize once: libNVVM consumes compute_XX, while the compiler records
+    // and nvJitLink consumes the equivalent sm_XX spelling.
+    let parsed_arch = parse_nvvm_arch(arch).unwrap_or_else(|error| {
+        eprintln!("Error: {error}");
+        std::process::exit(1);
+    });
+    let sm_arch = parsed_arch.sm();
+
+    // Step 1: build in NVVM IR mode so the backend writes `<crate>.ll` as
+    // libNVVM-ready NVVM IR. codegen_build exits on build failure. Pass
+    // quiet=true so the intermediate "✓ Build succeeded" line is suppressed;
+    // emit_ltoir prints its own unified summary at the end.
+    codegen_build(
+        ctx,
+        example,
+        verbose,
+        true,
+        Some(&sm_arch),
+        features,
+        None,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+        false,
+    );
+
+    // Step 2: compile that NVVM IR to LTOIR via libNVVM -gen-lto.
+    let ll_path = emitted_ll_path(&example_dir, example);
+    let ir = std::fs::read(&ll_path).unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not read emitted NVVM IR at {}: {e}",
+            ll_path.display()
+        );
+        std::process::exit(1);
+    });
+    let source_options_path = ll_path.with_extension("options");
+    let source_options = std::fs::read_to_string(&source_options_path).unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not read emitted compile options at {}: {e}",
+            source_options_path.display()
+        );
+        std::process::exit(1);
+    });
+    let compile_options = oxide_artifacts::ArtifactCompileOptions::from_sidecar_text(
+        &source_options,
+    )
+    .unwrap_or_else(|e| {
+        eprintln!(
+            "Error: invalid emitted compile options at {}: {e}",
+            source_options_path.display()
+        );
+        std::process::exit(1);
+    });
+
+    let compute_arch = parsed_arch.compute();
+    let ltoir = compile_nvvm_to_ltoir(&ir, example, &parsed_arch, compile_options);
+
+    // Step 3: write the artifact.
+    let out_path = output
+        .map(Path::to_path_buf)
+        .unwrap_or_else(|| default_ltoir_path(&example_dir, example));
+    for metadata_path in [
+        out_path.with_extension("target"),
+        out_path.with_extension("options"),
+    ] {
+        match std::fs::remove_file(&metadata_path) {
+            Ok(()) => {}
+            Err(error) if error.kind() == std::io::ErrorKind::NotFound => {}
+            Err(error) => {
+                eprintln!(
+                    "Error: could not clear stale LTOIR metadata {}: {error}",
+                    metadata_path.display()
+                );
+                std::process::exit(1);
+            }
+        }
+    }
+    std::fs::write(&out_path, &ltoir).unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not write LTOIR to {}: {e}",
+            out_path.display()
+        );
+        std::process::exit(1);
+    });
+    let options_path = out_path.with_extension("options");
+    std::fs::write(&options_path, compile_options.sidecar_text()).unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not write LTOIR compile options to {}: {e}",
+            options_path.display()
+        );
+        std::process::exit(1);
+    });
+    let target_path = out_path.with_extension("target");
+    std::fs::write(
+        &target_path,
+        format!(
+            "{sm_arch}\n{}\n",
+            oxide_artifacts::COMPILE_OPTIONS_TARGET_MARKER
+        ),
+    )
+    .unwrap_or_else(|e| {
+        eprintln!(
+            "Error: could not write LTOIR target metadata to {}: {e}",
+            target_path.display()
+        );
+        std::process::exit(1);
+    });
+
+    println!();
+    println!(
+        "✓ LTOIR written to {} ({} bytes, {compute_arch})",
+        out_path.display(),
+        ltoir.len()
+    );
+}
+
+/// Normalize a target architecture to libNVVM's `compute_XX` form.
+///
+/// Accepts `sm_XX` (the form `--arch` and the rest of cargo-oxide use),
+/// `compute_XX` (passed through), or a bare `XX`.
+pub(super) fn parse_nvvm_arch(
+    arch: &str,
+) -> Result<cuda_artifact_finalizer::CudaArch, cuda_artifact_finalizer::CudaArchParseError> {
+    let normalized = if arch.starts_with("sm_") || arch.starts_with("compute_") {
+        arch.to_string()
+    } else {
+        format!("compute_{arch}")
+    };
+    normalized.parse()
+}
+
+/// Compile NVVM IR text to binary LTOIR with libNVVM `-gen-lto`. Exits with a
+/// diagnostic on any libNVVM failure (the program log is attached to the error).
+///
+fn compile_nvvm_to_ltoir(
+    ir: &[u8],
+    name: &str,
+    arch: &cuda_artifact_finalizer::CudaArch,
+    compile_options: oxide_artifacts::ArtifactCompileOptions,
+) -> Vec<u8> {
+    let compiler = cuda_artifact_finalizer::NvvmCompiler::discover().unwrap_or_else(|e| {
+        eprintln!("Error: could not initialize the CUDA artifact compiler: {e}");
+        eprintln!("libNVVM ships with the CUDA Toolkit at <CUDA>/nvvm/lib64/libnvvm.so.");
+        eprintln!("Run `cargo oxide doctor` to check your toolkit setup.");
+        std::process::exit(1);
+    });
+    let options = finalization_options_from_artifact(arch, compile_options);
+    compiler
+        .compile_nvvm_ir_to_ltoir(name, ir, &options)
+        .unwrap_or_else(|e| {
+            eprintln!("Error: libNVVM -gen-lto compilation failed: {e}");
+            std::process::exit(1);
+        })
+}
+
+pub(super) fn finalization_options_from_artifact(
+    arch: &cuda_artifact_finalizer::CudaArch,
+    compile_options: oxide_artifacts::ArtifactCompileOptions,
+) -> cuda_artifact_finalizer::FinalizationOptions {
+    let debug = match compile_options.debug_policy() {
+        oxide_artifacts::ArtifactDebugPolicy::None => cuda_artifact_finalizer::DebugPolicy::None,
+        oxide_artifacts::ArtifactDebugPolicy::LineTables => {
+            cuda_artifact_finalizer::DebugPolicy::LineTables
+        }
+        oxide_artifacts::ArtifactDebugPolicy::Full => cuda_artifact_finalizer::DebugPolicy::Full,
+    };
+    cuda_artifact_finalizer::FinalizationOptions::new(arch.clone())
+        .with_fma_contraction(compile_options.fma_contraction_enabled())
+        .with_debug_policy(debug)
+}
diff --git a/crates/cargo-oxide/src/commands/materialize.rs b/crates/cargo-oxide/src/commands/materialize.rs
new file mode 100644
index 0000000000..fb49d68aa6
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/materialize.rs
@@ -0,0 +1,334 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::fs;
+use std::path::{Path, PathBuf};
+use std::process::Command;
+
+use super::*;
+
+pub(super) const MATERIALIZE_ENV: &str = reserved_oxide_symbols::MATERIALIZE_CUBIN_ENV;
+pub(super) const EXPECTED_PROVENANCE_ENV: &str =
+    reserved_oxide_symbols::MATERIALIZER_PROVENANCE_ENV;
+pub(super) const MATERIALIZER_HANDSHAKE_ENV: &str =
+    reserved_oxide_symbols::MATERIALIZER_HANDSHAKE_ENV;
+pub(super) const CODEGEN_FINGERPRINT_ENV: &str = reserved_oxide_symbols::CODEGEN_FINGERPRINT_ENV;
+pub(super) const DEVICE_CODEGEN_CRATE_ENV: &str = reserved_oxide_symbols::DEVICE_CODEGEN_CRATE_ENV;
+pub(super) const BACKEND_IDENTITY_CFG: &str = "cuda_oxide_internal_backend_identity";
+pub(super) const LEGACY_CODEGEN_FINGERPRINT_CFG: &str = "cuda_oxide_internal_codegen_env";
+pub(super) const LEGACY_MATERIALIZER_PROVENANCE_CFG: &str =
+    "cuda_oxide_internal_materializer_provenance";
+const MATERIALIZER_HANDSHAKE_CACHE: &str = ".oxide-artifacts/materializer-handshake/v1.json";
+
+#[derive(Clone, Debug, Default, Eq, PartialEq)]
+pub(super) struct MaterializationMode {
+    pub(super) prepared: Option<PreparedMaterialization>,
+}
+
+#[derive(Clone, Debug, Eq, PartialEq)]
+pub(super) struct PreparedMaterialization {
+    pub(super) provenance_sha256_hex: String,
+    pub(super) tool_identity_handshake_json: String,
+}
+
+impl MaterializationMode {
+    pub(super) fn enabled(&self) -> bool {
+        self.prepared.is_some()
+    }
+
+    pub(super) fn apply(&self, cmd: &mut Command) {
+        if let Some(prepared) = &self.prepared {
+            // These override inherited/project values: they are a single
+            // wrapper-generated handshake tied to this Cargo invocation.
+            cmd.env(MATERIALIZE_ENV, "1")
+                .env(EXPECTED_PROVENANCE_ENV, &prepared.provenance_sha256_hex)
+                .env(
+                    MATERIALIZER_HANDSHAKE_ENV,
+                    &prepared.tool_identity_handshake_json,
+                )
+                .env("CUDA_OXIDE_EMIT_NVVM_IR", "1");
+        }
+    }
+}
+
+pub(super) fn prepare_materialization(
+    ctx: &Context,
+    cli_requested: bool,
+    cli_arch: Option<&str>,
+    emit_nvvm_ir: bool,
+) -> MaterializationMode {
+    prepare_materialization_result(ctx, cli_requested, cli_arch, emit_nvvm_ir).unwrap_or_else(
+        |error| {
+            eprintln!("Error: {error}");
+            std::process::exit(2);
+        },
+    )
+}
+
+/// `prepare_materialization` with the ambient `CUDA_OXIDE_MATERIALIZE_CUBIN`
+/// injected, so `cargo_passthrough_command_with_env` can reach
+/// `materialization_requested_with_env`.
+///
+/// Note this still exits the process on error, which inside a unit test aborts
+/// the whole test binary rather than failing one case -- a further reason tests
+/// must not reach the ambient read.
+pub(super) fn prepare_materialization_with_env(
+    ctx: &Context,
+    cli_requested: bool,
+    cli_arch: Option<&str>,
+    emit_nvvm_ir: bool,
+    materialize_env: Option<std::ffi::OsString>,
+) -> MaterializationMode {
+    prepare_materialization_result_with_env(
+        ctx,
+        cli_requested,
+        cli_arch,
+        emit_nvvm_ir,
+        materialize_env,
+    )
+    .unwrap_or_else(|error| {
+        eprintln!("Error: {error}");
+        std::process::exit(2);
+    })
+}
+
+const EMIT_NVVM_IR_ENV: &str = "CUDA_OXIDE_EMIT_NVVM_IR";
+
+pub(super) fn nvvm_ir_requested(ctx: &Context) -> Result<bool, String> {
+    nvvm_ir_requested_with_env(ctx, std::env::var_os(EMIT_NVVM_IR_ENV))
+}
+
+/// `nvvm_ir_requested` with the ambient `CUDA_OXIDE_EMIT_NVVM_IR` injected.
+///
+/// The process value outranks project config, so resolution has to be
+/// injectable for unit tests: an exported `CUDA_OXIDE_EMIT_NVVM_IR` would
+/// otherwise decide the answer before the configured value is consulted.
+pub(super) fn nvvm_ir_requested_with_env(
+    ctx: &Context,
+    env_value: Option<std::ffi::OsString>,
+) -> Result<bool, String> {
+    if let Some(value) = env_value {
+        let value = value
+            .into_string()
+            .map_err(|_| format!("{EMIT_NVVM_IR_ENV} is not valid Unicode"))?;
+        return parse_strict_bool(EMIT_NVVM_IR_ENV, &value);
+    }
+
+    if let Some(value) = project_config_env(ctx, EMIT_NVVM_IR_ENV) {
+        return parse_strict_bool(EMIT_NVVM_IR_ENV, value);
+    }
+
+    Ok(false)
+}
+
+pub(super) fn materialization_requested(
+    ctx: &Context,
+    cli_requested: bool,
+) -> Result<bool, String> {
+    materialization_requested_with_env(ctx, cli_requested, std::env::var_os(MATERIALIZE_ENV))
+}
+
+/// `materialization_requested` with the ambient `CUDA_OXIDE_MATERIALIZE_CUBIN`
+/// injected.
+///
+/// The process value outranks project config, so resolution has to be
+/// injectable for unit tests: an exported value would otherwise turn
+/// materialization on for tests that pass `materialize_cubin: false`, sending
+/// them into `discover_materializer_provenance`. Same rationale as
+/// `nvvm_ir_requested_with_env`.
+fn materialization_requested_with_env(
+    ctx: &Context,
+    cli_requested: bool,
+    env_value: Option<std::ffi::OsString>,
+) -> Result<bool, String> {
+    if cli_requested {
+        return Ok(true);
+    }
+
+    if let Some(value) = env_value {
+        let value = value
+            .into_string()
+            .map_err(|_| format!("{MATERIALIZE_ENV} is not valid Unicode"))?;
+        return parse_strict_bool(MATERIALIZE_ENV, &value);
+    }
+
+    if let Some(value) = project_config_env(ctx, MATERIALIZE_ENV) {
+        return parse_strict_bool(MATERIALIZE_ENV, value);
+    }
+
+    Ok(false)
+}
+
+pub(super) fn prepare_materialization_result(
+    ctx: &Context,
+    cli_requested: bool,
+    cli_arch: Option<&str>,
+    emit_nvvm_ir: bool,
+) -> Result<MaterializationMode, String> {
+    prepare_materialization_result_with_env(
+        ctx,
+        cli_requested,
+        cli_arch,
+        emit_nvvm_ir,
+        std::env::var_os(MATERIALIZE_ENV),
+    )
+}
+
+/// `prepare_materialization_result` with the ambient
+/// `CUDA_OXIDE_MATERIALIZE_CUBIN` injected, forwarded to
+/// `materialization_requested_with_env`.
+fn prepare_materialization_result_with_env(
+    ctx: &Context,
+    cli_requested: bool,
+    cli_arch: Option<&str>,
+    emit_nvvm_ir: bool,
+    materialize_env: Option<std::ffi::OsString>,
+) -> Result<MaterializationMode, String> {
+    let enabled = materialization_requested_with_env(ctx, cli_requested, materialize_env)?;
+    if !enabled {
+        return Ok(MaterializationMode::default());
+    }
+    if emit_nvvm_ir {
+        return Err(
+            "--materialize-cubin cannot be combined with --emit-nvvm-ir; one requests a final cubin and the other requests NVVM IR"
+                .to_string(),
+        );
+    }
+
+    let arch = configured_arch_label(ctx, cli_arch).ok_or_else(|| {
+        "--materialize-cubin requires --arch, CUDA_OXIDE_TARGET, or a configured default-arch"
+            .to_string()
+    })?;
+    let _: cuda_artifact_finalizer::CudaArch = arch
+        .parse()
+        .map_err(|error| format!("invalid materialization target {arch:?}: {error}"))?;
+
+    let handshake = discover_materializer_handshake(ctx)?;
+    let handshake_json = serde_json::to_string(&handshake)
+        .map_err(|error| format!("could not encode materializer handshake: {error}"))?;
+    Ok(MaterializationMode {
+        prepared: Some(PreparedMaterialization {
+            provenance_sha256_hex: digest_hex(&handshake.provenance_sha256),
+            tool_identity_handshake_json: handshake_json,
+        }),
+    })
+}
+
+fn discover_materializer_handshake(
+    ctx: &Context,
+) -> Result<cuda_artifact_finalizer::MaterializerHandshakeV1, String> {
+    let executable = std::env::current_exe()
+        .map_err(|error| format!("could not locate cargo-oxide executable: {error}"))?;
+    let mut command = materializer_discovery_command(ctx, &executable);
+    if let Some(cached) = read_materializer_handshake_cache(ctx) {
+        command.env(MATERIALIZER_HANDSHAKE_ENV, cached);
+    }
+    let output = command
+        .output()
+        .map_err(|error| format!("could not start CUDA materializer discovery: {error}"))?;
+    if !output.status.success() {
+        let stderr = String::from_utf8_lossy(&output.stderr);
+        return Err(format!(
+            "CUDA materializer discovery failed: {}",
+            stderr.trim()
+        ));
+    }
+    let handshake = String::from_utf8(output.stdout)
+        .map_err(|_| "CUDA materializer discovery returned non-UTF-8 output".to_string())?;
+    let handshake: cuda_artifact_finalizer::MaterializerHandshakeV1 =
+        serde_json::from_str(handshake.trim()).map_err(|error| {
+            format!("CUDA materializer discovery returned an invalid v1 handshake: {error}")
+        })?;
+    if !handshake.has_consistent_provenance() {
+        return Err(format!(
+            "CUDA materializer discovery returned an inconsistent handshake version {}",
+            handshake.version
+        ));
+    }
+    write_materializer_handshake_cache(ctx, &handshake);
+    Ok(handshake)
+}
+
+pub(super) fn materializer_discovery_command(ctx: &Context, executable: &Path) -> Command {
+    let mut command = Command::new(executable);
+    command.arg("__materializer-handshake");
+    apply_config_env(&mut command, ctx);
+    apply_ld_library_path(&mut command, ctx);
+    // Only the local cache explicitly installed by the caller may seed the
+    // helper; never consume an inherited or project-provided internal value.
+    command.env_remove(MATERIALIZER_HANDSHAKE_ENV);
+    command
+}
+
+pub(super) fn materializer_handshake_cache_path(ctx: &Context) -> PathBuf {
+    ctx.workspace_root.join(MATERIALIZER_HANDSHAKE_CACHE)
+}
+
+pub(super) fn read_materializer_handshake_cache(ctx: &Context) -> Option<String> {
+    let json = fs::read_to_string(materializer_handshake_cache_path(ctx)).ok()?;
+    let handshake: cuda_artifact_finalizer::MaterializerHandshakeV1 =
+        serde_json::from_str(json.trim()).ok()?;
+    handshake.has_consistent_provenance().then_some(json)
+}
+
+pub(super) fn write_materializer_handshake_cache(
+    ctx: &Context,
+    handshake: &cuda_artifact_finalizer::MaterializerHandshakeV1,
+) {
+    let path = materializer_handshake_cache_path(ctx);
+    let Some(parent) = path.parent() else {
+        return;
+    };
+    if fs::create_dir_all(parent).is_err() {
+        return;
+    }
+    let Ok(json) = serde_json::to_string(handshake) else {
+        return;
+    };
+    let temporary = parent.join(format!("v1.{}.tmp", std::process::id()));
+    if fs::write(&temporary, json).is_ok() {
+        let _ = fs::rename(&temporary, &path);
+    }
+}
+
+pub fn print_materializer_handshake() {
+    let cached = std::env::var(MATERIALIZER_HANDSHAKE_ENV)
+        .ok()
+        .and_then(|json| serde_json::from_str(&json).ok())
+        .filter(cuda_artifact_finalizer::MaterializerHandshakeV1::has_consistent_provenance);
+    let finalizer = cached
+        .as_ref()
+        .map_or_else(
+            cuda_artifact_finalizer::Finalizer::discover,
+            cuda_artifact_finalizer::Finalizer::discover_with_handshake,
+        )
+        .unwrap_or_else(|error| {
+            eprintln!("could not discover CUDA artifact finalizer: {error}");
+            std::process::exit(1);
+        });
+    let handshake = finalizer.materializer_handshake().unwrap_or_else(|| {
+        eprintln!(
+            "the loaded libNVVM or nvJitLink library cannot be tied to an exact file; refusing materialization because Cargo could not fingerprint the compiler inputs"
+        );
+        std::process::exit(1);
+    });
+    println!(
+        "{}",
+        serde_json::to_string(&handshake).unwrap_or_else(|error| {
+            eprintln!("could not encode CUDA materializer handshake: {error}");
+            std::process::exit(1);
+        })
+    );
+}
+
+pub(super) fn parse_strict_bool(name: &str, value: &str) -> Result<bool, String> {
+    match value.trim().to_ascii_lowercase().as_str() {
+        "1" | "true" | "yes" | "on" => Ok(true),
+        "0" | "false" | "no" | "off" => Ok(false),
+        _ => Err(format!(
+            "{name} must be a boolean (accepted true values: 1, true, yes, on; false values: 0, false, no, off), got {value:?}"
+        )),
+    }
+}
diff --git a/crates/cargo-oxide/src/commands/mod.rs b/crates/cargo-oxide/src/commands/mod.rs
new file mode 100644
index 0000000000..f0a94b187d
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/mod.rs
@@ -0,0 +1,50 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Command implementations for cargo-oxide.
+//!
+//! These port the xtask commands with improvements:
+//! - Backend path resolved via discovery chain instead of hardcoded relative path
+//! - Workspace root resolved by walking up from CWD instead of assuming CWD
+
+mod artifacts;
+mod build_run;
+mod clean;
+mod codegen_env;
+mod context;
+mod doctor;
+mod examples_list;
+mod fingerprint;
+mod fmt;
+mod host_cargo;
+mod interop;
+mod ltoir;
+mod materialize;
+mod passthrough;
+mod pipeline_debug;
+mod scaffold;
+mod setup_update;
+#[cfg(test)]
+mod tests;
+mod toolkit;
+
+use artifacts::*;
+pub use build_run::*;
+pub use clean::*;
+pub use codegen_env::*;
+pub use context::*;
+pub use doctor::*;
+pub use examples_list::*;
+use fingerprint::*;
+pub use fmt::*;
+use host_cargo::*;
+use interop::*;
+pub use ltoir::*;
+pub use materialize::*;
+pub use passthrough::*;
+pub use pipeline_debug::*;
+pub use scaffold::*;
+pub use setup_update::*;
+use toolkit::*;
diff --git a/crates/cargo-oxide/src/commands/passthrough.rs b/crates/cargo-oxide/src/commands/passthrough.rs
new file mode 100644
index 0000000000..9f250c942e
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/passthrough.rs
@@ -0,0 +1,311 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::collections::BTreeMap;
+use std::path::Path;
+use std::process::Command;
+
+use super::*;
+
+/// Device debug-information policy requested on the command line.
+///
+/// Mirrors nvcc: `--lineinfo` is `-lineinfo` (line tables, optimization intact)
+/// and `--device-debug` is `-G` (full debug, libNVVM optimization disabled).
+/// The two are ordered, not exclusive: asking for both yields [`Self::Full`],
+/// because full debug already carries line tables.
+///
+/// This is the CLI surface for a policy that already exists end to end --
+/// `CUDA_OXIDE_DEBUG`, `ArtifactCompileOptions`'s debug bits, and
+/// `FinalizationOptions::with_debug_policy` all predate it.
+#[derive(Clone, Copy, Debug, Default, PartialEq, Eq)]
+pub enum DeviceDebug {
+    /// Request no device debug information (the default).
+    #[default]
+    Off,
+    /// Preserve source line mappings without disabling optimization.
+    LineTables,
+    /// Emit full debug information; MIR optimization is disabled and libNVVM finalization runs unoptimized.
+    Full,
+}
+
+impl DeviceDebug {
+    /// Resolve the two independent CLI booleans into one ordered policy.
+    #[must_use]
+    pub fn from_flags(lineinfo: bool, device_debug: bool) -> Self {
+        match (device_debug, lineinfo) {
+            (true, _) => Self::Full,
+            (false, true) => Self::LineTables,
+            (false, false) => Self::Off,
+        }
+    }
+
+    /// Value for `CUDA_OXIDE_DEBUG`, or `None` when nothing must be exported.
+    ///
+    /// `Off` deliberately returns `None` rather than `"off"`: exporting `off`
+    /// would override a debug level the surrounding environment had already
+    /// asked for, turning an absent flag into an active opt-out.
+    #[must_use]
+    pub fn env_value(self) -> Option<&'static str> {
+        match self {
+            Self::Off => None,
+            Self::LineTables => Some("line"),
+            Self::Full => Some("full"),
+        }
+    }
+}
+
+/// Options for `cargo oxide build -- ...` / `cargo oxide test -- ...`.
+#[derive(Clone, Copy)]
+pub struct CargoPassthroughOptions<'a> {
+    pub verbose: bool,
+    pub emit_nvvm_ir: bool,
+    pub arch: Option<&'a str>,
+    pub features: Option<&'a str>,
+    pub cargo_target_dir: Option<&'a Path>,
+    pub device_codegen_crate: Option<&'a str>,
+    pub device_cfgs: &'a [String],
+    pub no_fmad: bool,
+    pub unchecked_indexing: bool,
+    pub materialize_cubin: bool,
+    pub device_debug: DeviceDebug,
+}
+
+/// Cargo operations supported by the passthrough path.
+///
+/// The subcommand determines who owns profile-related rustc flags: regular
+/// builds retain cuda-oxide's release-like defaults, while tests leave the
+/// selected Cargo profile intact (including `--release` and `--profile`).
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum CargoPassthroughSubcommand {
+    Build,
+    Test,
+}
+
+impl CargoPassthroughSubcommand {
+    fn as_str(self) -> &'static str {
+        match self {
+            Self::Build => "build",
+            Self::Test => "test",
+        }
+    }
+
+    pub(super) fn codegen_profile(self) -> CodegenProfilePolicy {
+        match self {
+            Self::Build => CodegenProfilePolicy::ReleaseLike,
+            Self::Test => CodegenProfilePolicy::CargoSelected,
+        }
+    }
+}
+
+pub(super) fn normalize_device_codegen_crates(raw: &str) -> Result<String, String> {
+    let mut normalized = Vec::new();
+    for item in raw.split(',') {
+        let name = item.trim().replace('-', "_");
+        if name.is_empty() {
+            return Err(
+                "--device-codegen-crate requires a comma-separated list without empty entries"
+                    .to_string(),
+            );
+        }
+        if !name
+            .chars()
+            .all(|character| character.is_ascii_alphanumeric() || character == '_')
+        {
+            return Err(format!(
+                "invalid device-codegen crate name `{item}`; use Cargo crate names separated by commas"
+            ));
+        }
+        if !normalized.contains(&name) {
+            normalized.push(name);
+        }
+    }
+    Ok(normalized.join(","))
+}
+
+pub(super) fn project_config_env<'a>(ctx: &'a Context, key: &str) -> Option<&'a str> {
+    ctx.config
+        .env
+        .iter()
+        .find(|(configured_key, _)| configured_key == key)
+        .map(|(_, value)| value.as_str())
+}
+
+fn configured_device_codegen_crates(
+    ctx: &Context,
+    explicit: Option<&str>,
+) -> Result<Option<String>, String> {
+    let inherited = std::env::var(DEVICE_CODEGEN_CRATE_ENV).ok();
+    resolve_device_codegen_crates(
+        explicit,
+        inherited.as_deref(),
+        project_config_env(ctx, DEVICE_CODEGEN_CRATE_ENV),
+    )
+}
+
+pub(super) fn resolve_device_codegen_crates(
+    explicit: Option<&str>,
+    inherited: Option<&str>,
+    configured: Option<&str>,
+) -> Result<Option<String>, String> {
+    if let Some(explicit) = explicit {
+        return normalize_device_codegen_crates(explicit).map(Some);
+    }
+
+    inherited
+        .or(configured)
+        .filter(|value| !value.trim().is_empty())
+        .map(normalize_device_codegen_crates)
+        .transpose()
+}
+
+/// The ambient environment, in the shape the fingerprint helpers consume.
+///
+/// Split out so both fingerprint wrappers share one collection, and so their
+/// `_with_env` counterparts stay the only entry points a unit test needs.
+pub(super) fn inherited_process_env() -> BTreeMap<String, Vec<u8>> {
+    std::env::vars_os()
+        .filter_map(|(key, value)| {
+            key.into_string()
+                .ok()
+                .map(|key| (key, value.as_encoded_bytes().to_vec()))
+        })
+        .collect()
+}
+
+fn cargo_passthrough_command(
+    ctx: &Context,
+    cargo_subcommand: CargoPassthroughSubcommand,
+    opts: &CargoPassthroughOptions<'_>,
+    cargo_args: &[String],
+) -> Result<Command, String> {
+    cargo_passthrough_command_with_env(
+        ctx,
+        cargo_subcommand,
+        opts,
+        cargo_args,
+        std::env::var_os(MATERIALIZE_ENV),
+    )
+}
+
+/// `cargo_passthrough_command` with the ambient
+/// `CUDA_OXIDE_MATERIALIZE_CUBIN` injected.
+///
+/// Unit tests must call this with `None`: the ambient value outranks
+/// `opts.materialize_cubin`, so an exported one turns materialization on and
+/// sends the test into `discover_materializer_provenance`, which re-executes
+/// `current_exe` -- the libtest binary under `cargo test` -- and then exits the
+/// process over the unusable digest, taking the whole suite with it.
+pub(super) fn cargo_passthrough_command_with_env(
+    ctx: &Context,
+    cargo_subcommand: CargoPassthroughSubcommand,
+    opts: &CargoPassthroughOptions<'_>,
+    cargo_args: &[String],
+    materialize_env: Option<std::ffi::OsString>,
+) -> Result<Command, String> {
+    let target_arch = configured_arch(ctx, opts.arch);
+    let materialization = prepare_materialization_with_env(
+        ctx,
+        opts.materialize_cubin,
+        opts.arch,
+        opts.emit_nvvm_ir,
+        materialize_env,
+    );
+    let owner_filter = configured_device_codegen_crates(ctx, opts.device_codegen_crate)?;
+    // Device-owning macros track this identity in their crate dep-info. Keep it
+    // out of global rustflags so host-only dependencies retain one cache key.
+    let fingerprint = passthrough_codegen_fingerprint(
+        ctx,
+        opts,
+        owner_filter.as_deref(),
+        target_arch,
+        &materialization,
+    );
+    let mut cmd = Command::new("cargo");
+    cmd.arg(cargo_subcommand.as_str());
+    if let Some(features) = opts.features {
+        cmd.args(["--features", features]);
+    }
+    cmd.args(cargo_args).current_dir(&ctx.workspace_root);
+
+    // Project configuration provides defaults. Explicit wrapper flags and
+    // internal compiler requirements are applied afterward and therefore win.
+    apply_common_codegen_env(
+        &mut cmd,
+        ctx,
+        opts.verbose,
+        opts.no_fmad,
+        opts.unchecked_indexing,
+        opts.device_debug,
+    );
+    apply_codegen_configuration(
+        &mut cmd,
+        ctx,
+        cargo_subcommand.codegen_profile(),
+        opts.device_cfgs,
+        &fingerprint,
+    )?;
+
+    if let Some(cargo_target_dir) = opts.cargo_target_dir {
+        cmd.env("CARGO_TARGET_DIR", cargo_target_dir);
+    }
+    if let Some(owner_filter) = owner_filter {
+        cmd.env(DEVICE_CODEGEN_CRATE_ENV, owner_filter);
+    }
+    apply_output_mode(&mut cmd, opts.emit_nvvm_ir, target_arch, &materialization);
+    Ok(cmd)
+}
+
+/// Run an arbitrary Cargo build-like subcommand through the cuda-oxide backend.
+///
+/// Unlike example mode, this does not touch source files or clean generated
+/// artifacts. It is intended for final-target workspace builds where Cargo's
+/// incremental behavior should remain intact.
+pub fn codegen_cargo_passthrough(
+    ctx: &Context,
+    cargo_subcommand: CargoPassthroughSubcommand,
+    opts: CargoPassthroughOptions<'_>,
+    cargo_args: &[String],
+) {
+    let cargo_subcommand_name = cargo_subcommand.as_str();
+    println!("=========================================");
+    println!("RUSTC-CODEGEN-CUDA CARGO {}", cargo_subcommand_name);
+    println!("=========================================");
+    println!();
+
+    let mut cmd = cargo_passthrough_command(ctx, cargo_subcommand, &opts, cargo_args)
+        .unwrap_or_else(|error| {
+            eprintln!("Error: {error}");
+            std::process::exit(2);
+        });
+
+    let displayed_args: Vec<_> = cmd
+        .get_args()
+        .skip(1)
+        .map(|arg| arg.to_string_lossy().into_owned())
+        .collect();
+    if displayed_args.is_empty() {
+        println!("Running cargo {}...", cargo_subcommand_name);
+    } else {
+        println!(
+            "Running cargo {} {}...",
+            cargo_subcommand_name,
+            displayed_args.join(" ")
+        );
+    }
+    println!();
+
+    let status = cmd.status().expect("Failed to run cargo");
+    if !status.success() {
+        eprintln!(
+            "\nCargo {} failed with exit code: {:?}",
+            cargo_subcommand_name,
+            status.code()
+        );
+        std::process::exit(status.code().unwrap_or(1));
+    }
+
+    println!();
+    println!("✓ Cargo {} succeeded", cargo_subcommand_name);
+}
diff --git a/crates/cargo-oxide/src/commands/pipeline_debug.rs b/crates/cargo-oxide/src/commands/pipeline_debug.rs
new file mode 100644
index 0000000000..8ef5ab9fe8
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/pipeline_debug.rs
@@ -0,0 +1,306 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::process::Command;
+
+use super::*;
+
+// =============================================================================
+// Pipeline command
+// =============================================================================
+
+/// Show verbose pipeline progress and the available intermediate artifacts.
+///
+/// Enables all diagnostic env vars (`CUDA_OXIDE_VERBOSE`, `SHOW_RUSTC_MIR`,
+/// `DUMP_MIR`, `DUMP_LLVM`) so the user can see MIR collection, the
+/// `dialect-mir` module (pre- and post-`mem2reg`), the LLVM dialect
+/// module, textual LLVM IR, and the final PTX or NVVM IR. After the build,
+/// generated artifacts are printed to stdout.
+#[allow(clippy::too_many_arguments)]
+pub fn codegen_show_pipeline(
+    ctx: &Context,
+    example: &str,
+    emit_nvvm_ir: bool,
+    arch: Option<&str>,
+    no_fmad: bool,
+    unchecked_indexing: bool,
+    device_debug: DeviceDebug,
+    materialize_cubin: bool,
+) {
+    let target_arch = configured_arch(ctx, arch);
+    let materialization = prepare_materialization(ctx, materialize_cubin, arch, emit_nvvm_ir);
+    let example_dir = if ctx.is_workspace {
+        resolve_example_dir(ctx, example)
+    } else {
+        ctx.workspace_root.clone()
+    };
+
+    if load_interop_config(&example_dir).is_some_and(|config| !config.device_crates.is_empty()) {
+        reject_interop_output_mode(emit_nvvm_ir, &materialization);
+    }
+
+    clean_generated_files(&example_dir, example);
+
+    println!("=========================================");
+    println!("RUSTC-CODEGEN-CUDA PIPELINE: {}", example);
+    println!("=========================================");
+    println!();
+    let target_arch_label = configured_arch_label(ctx, arch);
+    match (
+        materialization.enabled(),
+        emit_nvvm_ir,
+        target_arch_label.as_deref(),
+    ) {
+        (true, _, Some(target_arch)) => {
+            println!("Output format: materialized cubin (arch: {target_arch})")
+        }
+        (false, true, Some(target_arch)) => {
+            println!("Output format: NVVM IR (arch: {})", target_arch)
+        }
+        (false, false, Some(target_arch)) => {
+            println!("Output format: PTX (arch override: {})", target_arch)
+        }
+        (false, false, None) => println!("Output format: PTX (auto-detected arch)"),
+        (true, _, None) | (false, true, None) => {
+            unreachable!("IR/final materialization requires a configured architecture")
+        }
+    }
+    println!();
+    println!("Required flags (applied via CARGO_ENCODED_RUSTFLAGS):");
+    println!("  -C opt-level=3              MIR optimization");
+    println!("  -C debug-assertions=off     Remove debug checks");
+    println!("  -Z mir-enable-passes=-JumpThreading");
+    println!("                              Prevent barrier duplication");
+    println!("  -Z always-encode-mir        Emit MIR for all reachable device deps");
+    println!();
+    println!("Note: panic=abort is NOT required - the codegen backend treats");
+    println!("      unwind paths as unreachable (CUDA toolchain limitation, not HW).");
+    println!();
+
+    touch_main_rs(&example_dir);
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release"]).current_dir(&example_dir);
+
+    // The shared codegen env (including the CLI debug level) must be on the
+    // command before the rustflags decision below: a full-debug request adds
+    // `-Zmir-opt-level=0`, and `apply_codegen_rustflags` reads the command's
+    // `CUDA_OXIDE_DEBUG` to see it. This is the same ordering build/run use.
+    apply_common_codegen_env(
+        &mut cmd,
+        ctx,
+        true,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+    );
+    cmd.env("CUDA_OXIDE_SHOW_RUSTC_MIR", "1");
+    cmd.env("CUDA_OXIDE_DUMP_MIR", "1");
+    cmd.env("CUDA_OXIDE_DUMP_LLVM", "1");
+    let fingerprint = pipeline_codegen_fingerprint(
+        ctx,
+        no_fmad,
+        unchecked_indexing,
+        device_debug,
+        emit_nvvm_ir,
+        target_arch,
+        &materialization,
+    );
+    apply_codegen_configuration_or_exit(
+        &mut cmd,
+        ctx,
+        CodegenProfilePolicy::ReleaseLike,
+        &[],
+        &fingerprint,
+    );
+
+    apply_output_mode(&mut cmd, emit_nvvm_ir, target_arch, &materialization);
+
+    println!("Building {}...", example);
+    println!();
+
+    let status = cmd.status().expect("Failed to run cargo");
+
+    if !status.success() {
+        eprintln!("\nBuild failed with exit code: {:?}", status.code());
+        std::process::exit(status.code().unwrap_or(1));
+    }
+
+    show_generated_artifacts(&example_dir, example);
+}
+
+// =============================================================================
+// Debug command
+// =============================================================================
+
+/// Build with debug info and launch cuda-gdb (or cgdb).
+///
+/// Compiles the example with `-C debuginfo=2` on top of the normal release
+/// flags, then launches the debugger on the resulting binary. Prints a
+/// quick-reference cheat sheet for common cuda-gdb commands before handing
+/// control to the debugger.
+#[allow(clippy::too_many_arguments)]
+pub fn codegen_debug(
+    ctx: &Context,
+    example: &str,
+    arch: Option<&str>,
+    features: Option<&str>,
+    bin: Option<&str>,
+    use_cgdb: bool,
+    use_tui: bool,
+    materialize_cubin: bool,
+) {
+    let example_dir = if ctx.is_workspace {
+        resolve_example_dir(ctx, example)
+    } else {
+        ctx.workspace_root.clone()
+    };
+    let target_arch = configured_arch(ctx, arch);
+    let materialization = prepare_materialization(ctx, materialize_cubin, arch, false);
+    if load_interop_config(&example_dir).is_some_and(|config| !config.device_crates.is_empty()) {
+        reject_interop_output_mode(false, &materialization);
+    }
+
+    let cuda_gdb = find_cuda_toolkit_executable(ctx, "cuda-gdb", CUDA_GDB_FALLBACK_PATHS)
+        .unwrap_or_else(|| {
+            eprintln!("Error: cuda-gdb not found!");
+            eprintln!();
+            eprintln!("Make sure CUDA toolkit is installed and cuda-gdb is in your PATH");
+            eprintln!("or configured CUDA toolkit root:");
+            eprintln!("  export PATH=\"/usr/local/cuda/bin:$PATH\"");
+            eprintln!("  export CUDA_TOOLKIT_PATH=/usr/local/cuda");
+            std::process::exit(1);
+        });
+
+    let cgdb_path = if use_cgdb {
+        Some(find_executable("cgdb", &[]).unwrap_or_else(|| {
+            eprintln!("Error: cgdb not found!");
+            eprintln!("Install with: sudo apt install cgdb");
+            std::process::exit(1);
+        }))
+    } else {
+        None
+    };
+
+    let detected_device_arch = detect_run_target_arch(target_arch, materialization.enabled());
+
+    if let Some(bin) = bin {
+        println!("Building {} (bin: {}) with debug info...", example, bin);
+    } else {
+        println!("Building {} with debug info...", example);
+    }
+    if let Some(dev) = detected_device_arch.as_deref() {
+        println!("Detected GPU arch: {dev} (via nvidia-smi)");
+    }
+
+    clean_generated_files(&example_dir, example);
+
+    touch_main_rs(&example_dir);
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release"]).current_dir(&example_dir);
+
+    if let Some(bin) = bin {
+        cmd.args(["--bin", bin]);
+    }
+    if let Some(features) = features {
+        cmd.args(["--features", features]);
+    }
+
+    apply_config_env(&mut cmd, ctx);
+    let fingerprint = standard_codegen_fingerprint(
+        ctx,
+        false,
+        false,
+        false,
+        DeviceDebug::Off,
+        false,
+        target_arch,
+        detected_device_arch.as_deref(),
+        &materialization,
+    );
+    apply_codegen_configuration_or_exit(
+        &mut cmd,
+        ctx,
+        CodegenProfilePolicy::ReleaseLikeWithDebugInfo,
+        &[],
+        &fingerprint,
+    );
+    cmd.env("CARGO_PROFILE_RELEASE_DEBUG", "2");
+    apply_output_mode(&mut cmd, false, target_arch, &materialization);
+    apply_device_arch_hint(&mut cmd, target_arch, detected_device_arch.as_deref());
+    apply_ld_library_path(&mut cmd, ctx);
+
+    let binary =
+        run_cargo_build_for_executable(&mut cmd, &example_dir, bin).unwrap_or_else(|message| {
+            eprintln!("Failed to build {example}: {message}");
+            std::process::exit(1);
+        });
+    if !binary.exists() {
+        eprintln!(
+            "Error: Cargo reported executable artifact {}, but it does not exist",
+            binary.display()
+        );
+        std::process::exit(1);
+    }
+
+    if cgdb_path.is_some() {
+        println!("Launching cgdb (cuda-gdb frontend)...");
+    } else {
+        println!(
+            "Launching cuda-gdb{}...",
+            if use_tui { " (TUI mode)" } else { "" }
+        );
+    }
+    println!();
+    println!("Quick reference:");
+    println!("  set cuda break_on_launch application");
+    println!("                           - Break at start of any kernel");
+    println!("  run                      - Start the program");
+    println!("  info cuda kernels        - List active kernels");
+    println!("  info cuda threads        - List GPU threads");
+    println!("  cuda thread (0,0,0)      - Switch to thread");
+    println!("  cuda block (0,0,0)       - Switch to block");
+    println!("  print <var>              - Print variable");
+    println!("  next / step / continue   - Execution control");
+    println!("  quit                     - Exit debugger");
+    if cgdb_path.is_some() {
+        println!();
+        println!("cgdb shortcuts:");
+        println!("  Esc                      - Focus source window (vim keys work)");
+        println!("  i                        - Focus command window");
+        println!("  space                    - Set breakpoint on current line");
+        println!("  o                        - Open file dialog");
+    } else if use_tui {
+        println!();
+        println!("TUI shortcuts:");
+        println!("  Ctrl+x a                 - Toggle TUI mode");
+        println!("  Ctrl+x 2                 - Split view (source + asm)");
+        println!("  Ctrl+l                   - Refresh screen");
+    }
+    println!();
+
+    let status = if let Some(cgdb) = cgdb_path {
+        Command::new(cgdb)
+            .arg("-d")
+            .arg(&cuda_gdb)
+            .arg(&binary)
+            .current_dir(&example_dir)
+            .status()
+            .expect("Failed to launch cgdb")
+    } else {
+        let mut gdb_cmd = Command::new(&cuda_gdb);
+        if use_tui {
+            gdb_cmd.arg("--tui");
+        }
+        gdb_cmd.arg(&binary);
+        gdb_cmd.current_dir(&example_dir);
+        gdb_cmd.status().expect("Failed to launch cuda-gdb")
+    };
+
+    if !status.success() {
+        std::process::exit(status.code().unwrap_or(1));
+    }
+}
diff --git a/crates/cargo-oxide/src/commands/scaffold.rs b/crates/cargo-oxide/src/commands/scaffold.rs
new file mode 100644
index 0000000000..e02dc36d15
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/scaffold.rs
@@ -0,0 +1,333 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::path::PathBuf;
+
+use super::*;
+
+// =========================================================================
+// cargo oxide new -- standalone project scaffolding
+// =========================================================================
+
+const GIT_REPO: &str = "https://github.com/NVlabs/cuda-oxide.git";
+
+const RUST_TOOLCHAIN_TOML: &str = r#"[toolchain]
+channel = "nightly-2026-04-03"
+components = ["rust-src", "rustc-dev", "rust-analyzer", "clippy", "rustfmt", "llvm-tools"]
+"#;
+
+const SCAFFOLD_GITIGNORE_EXTRA: &[&str] = &[
+    "/target/",
+    "**/*.bc", // bitcode leftovers not in the clean suffix list
+    ".DS_Store",
+];
+
+pub(super) fn scaffold_gitignore() -> String {
+    let mut lines: Vec<String> = SCAFFOLD_GITIGNORE_EXTRA
+        .iter()
+        .map(|line| (*line).to_string())
+        .collect();
+    // Keep in lockstep with `GENERATED_ARTIFACT_SUFFIXES` so `cargo oxide new`
+    // ignores every artifact `cargo oxide clean` knows how to delete.
+    for suffix in GENERATED_ARTIFACT_SUFFIXES {
+        let pattern = format!("**/*.{suffix}");
+        if !lines.iter().any(|line| line == &pattern) {
+            lines.push(pattern);
+        }
+    }
+    // Stable order for readable diffs: keep the three fixed entries first,
+    // then sort generated patterns.
+    let (fixed, rest) = lines.split_at(SCAFFOLD_GITIGNORE_EXTRA.len());
+    let mut rest = rest.to_vec();
+    rest.sort();
+    let mut out = fixed.to_vec();
+    out.append(&mut rest);
+    out.push(String::new());
+    out.join("\n")
+}
+
+/// File contents produced by `cargo oxide new`.
+#[derive(Clone, Debug, Eq, PartialEq)]
+pub(super) struct ScaffoldFiles {
+    pub(super) cargo_toml: String,
+    rust_toolchain_toml: String,
+    pub(super) gitignore: String,
+    pub(super) readme: String,
+    pub(super) main_rs: String,
+}
+
+fn scaffold_readme(name: &str, async_mode: bool) -> String {
+    let mode = if async_mode {
+        "async cuda-oxide"
+    } else {
+        "cuda-oxide"
+    };
+    let template_notes = if async_mode {
+        "The template is a vector-add kernel launched through `cuda-async`:\n\
+         `vecadd_async` returns a lazy `DeviceOperation` scheduled on the\n\
+         stream pool. See the cuda-oxide book getting-started chapter for the\n\
+         next steps."
+    } else {
+        "The template is a vector-add kernel. It uses `#[launch_contract]` and\n\
+         `PreparedLaunch` so geometry is checked before launch. See the\n\
+         cuda-oxide book getting-started chapter for the next steps."
+    };
+    format!(
+        r#"# {name}
+
+Scaffolded {mode} project.
+
+## Setup
+
+```bash
+cargo oxide doctor
+```
+
+Fix anything doctor reports before building.
+
+## Run
+
+```bash
+cargo oxide run
+```
+
+{template_notes}
+"#
+    )
+}
+
+fn scaffold_cargo_toml(name: &str, async_mode: bool) -> String {
+    if async_mode {
+        format!(
+            r#"[package]
+name = "{name}"
+version = "0.1.0"
+edition = "2024"
+
+[workspace]
+
+[dependencies]
+cuda-device = {{ git = "{GIT_REPO}" }}
+cuda-host = {{ git = "{GIT_REPO}", features = ["async"] }}
+cuda-core = {{ git = "{GIT_REPO}" }}
+cuda-async = {{ git = "{GIT_REPO}" }}
+cuda-bindings = {{ git = "{GIT_REPO}" }}
+tokio = {{ version = "1", features = ["rt", "rt-multi-thread", "macros"] }}
+"#
+        )
+    } else {
+        format!(
+            r#"[package]
+name = "{name}"
+version = "0.1.0"
+edition = "2024"
+
+[workspace]
+
+[dependencies]
+cuda-device = {{ git = "{GIT_REPO}" }}
+cuda-host = {{ git = "{GIT_REPO}" }}
+cuda-core = {{ git = "{GIT_REPO}" }}
+"#
+        )
+    }
+}
+
+fn scaffold_main_rs(async_mode: bool) -> String {
+    if async_mode {
+        r#"use cuda_device::{kernel, thread, DisjointSlice};
+use cuda_host::cuda_module;
+use cuda_async::device_context::init_device_contexts;
+use cuda_async::device_operation::DeviceOperation;
+use cuda_core::LaunchConfig;
+
+#[cuda_module]
+mod kernels {
+    use super::*;
+
+    #[kernel]
+    pub fn vecadd(a: &[f32], b: &[f32], mut c: DisjointSlice<f32>) {
+        let idx = thread::index_1d();
+        let idx_raw = idx.get();
+        if let Some(c_elem) = c.get_mut(idx) {
+            *c_elem = a[idx_raw] + b[idx_raw];
+        }
+    }
+}
+
+#[tokio::main]
+async fn main() -> Result<(), Box<dyn std::error::Error>> {
+    use cuda_async::device_box::DeviceBox;
+    use cuda_core::memory::{malloc_async, memcpy_dtoh_async, memcpy_htod_async};
+    use std::mem;
+
+    init_device_contexts(0, 1)?;
+    let module = kernels::load_async(0)?;
+
+    const N: usize = 1024;
+    let a_host: Vec<f32> = (0..N).map(|i| i as f32).collect();
+    let b_host: Vec<f32> = (0..N).map(|i| (i * 2) as f32).collect();
+
+    let (a_dev, b_dev, mut c_dev) = cuda_async::device_context::with_cuda_context(0, |ctx| {
+        let stream = ctx.default_stream();
+        let num_bytes = N * mem::size_of::<f32>();
+        unsafe {
+            let a = malloc_async(stream.cu_stream(), num_bytes).unwrap();
+            let b = malloc_async(stream.cu_stream(), num_bytes).unwrap();
+            let c = malloc_async(stream.cu_stream(), num_bytes).unwrap();
+            memcpy_htod_async(a, a_host.as_ptr(), num_bytes, stream.cu_stream()).unwrap();
+            memcpy_htod_async(b, b_host.as_ptr(), num_bytes, stream.cu_stream()).unwrap();
+            stream.synchronize().unwrap();
+            (
+                DeviceBox::<[f32]>::from_raw_parts(a, N, 0),
+                DeviceBox::<[f32]>::from_raw_parts(b, N, 0),
+                DeviceBox::<[f32]>::from_raw_parts(c, N, 0),
+            )
+        }
+    })?;
+
+    // SAFETY: this is a 1D launch and `vecadd` guards its index against the
+    // output length before writing.
+    unsafe {
+        module.vecadd_async(
+            LaunchConfig::for_num_elems(N as u32),
+            &a_dev,
+            &b_dev,
+            &mut c_dev,
+        )
+    }?
+    .sync()?;
+
+    let mut c_host = vec![0.0f32; N];
+    cuda_async::device_context::with_cuda_context(0, |ctx| {
+        let stream = ctx.default_stream();
+        unsafe {
+            memcpy_dtoh_async(
+                c_host.as_mut_ptr(),
+                c_dev.cu_deviceptr(),
+                N * mem::size_of::<f32>(),
+                stream.cu_stream(),
+            )
+            .unwrap();
+            stream.synchronize().unwrap();
+        }
+    })?;
+
+    let errors = (0..N)
+        .filter(|&i| (c_host[i] - (a_host[i] + b_host[i])).abs() > 1e-5)
+        .count();
+
+    if errors == 0 {
+        println!("PASSED: all {} elements correct", N);
+    } else {
+        eprintln!("FAILED: {} errors", errors);
+        std::process::exit(1);
+    }
+
+    Ok(())
+}
+"#
+        .to_string()
+    } else {
+        r#"use cuda_device::{kernel, launch_bounds, launch_contract, thread, DisjointSlice};
+use cuda_host::cuda_module;
+use cuda_core::{CudaContext, DeviceBuffer, LaunchConfig1D};
+
+#[cuda_module]
+mod kernels {
+    use super::*;
+
+    #[kernel]
+    #[launch_bounds(256)]
+    #[launch_contract(domain = 1, block = (256, 1, 1))]
+    pub fn vecadd(a: &[f32], b: &[f32], mut c: DisjointSlice<f32>) {
+        let idx = thread::index_1d();
+        let idx_raw = idx.get();
+        if let Some(c_elem) = c.get_mut(idx) {
+            *c_elem = a[idx_raw] + b[idx_raw];
+        }
+    }
+}
+
+fn main() -> Result<(), Box<dyn std::error::Error>> {
+    let ctx = CudaContext::new(0)?;
+    let stream = ctx.default_stream();
+
+    const N: usize = 1024;
+    let a_host: Vec<f32> = (0..N).map(|i| i as f32).collect();
+    let b_host: Vec<f32> = (0..N).map(|i| (i * 2) as f32).collect();
+
+    let a_dev = DeviceBuffer::from_host(&stream, &a_host)?;
+    let b_dev = DeviceBuffer::from_host(&stream, &b_host)?;
+    let mut c_dev = DeviceBuffer::<f32>::zeroed(&stream, N)?;
+
+    // SAFETY: this package owns the embedded device bundle produced for the
+    // kernels module above.
+    let module = unsafe { kernels::load(&ctx)? };
+    let prepared = module.prepare_vecadd(LaunchConfig1D::new((N as u32).div_ceil(256), 256, 0))?;
+    module.vecadd(&stream, &prepared, &a_dev, &b_dev, &mut c_dev)?;
+
+    let c_host = c_dev.to_host_vec(&stream)?;
+    let errors = (0..N)
+        .filter(|&i| (c_host[i] - (a_host[i] + b_host[i])).abs() > 1e-5)
+        .count();
+
+    if errors == 0 {
+        println!("PASSED: all {} elements correct", N);
+    } else {
+        eprintln!("FAILED: {} errors", errors);
+        std::process::exit(1);
+    }
+    Ok(())
+}
+"#
+        .to_string()
+    }
+}
+
+pub(super) fn scaffold_files(name: &str, async_mode: bool) -> ScaffoldFiles {
+    ScaffoldFiles {
+        cargo_toml: scaffold_cargo_toml(name, async_mode),
+        rust_toolchain_toml: RUST_TOOLCHAIN_TOML.to_string(),
+        gitignore: scaffold_gitignore(),
+        readme: scaffold_readme(name, async_mode),
+        main_rs: scaffold_main_rs(async_mode),
+    }
+}
+
+/// Scaffold a new standalone cuda-oxide project.
+pub fn scaffold_new(name: &str, async_mode: bool) {
+    let project_dir = PathBuf::from(name);
+    if project_dir.exists() {
+        eprintln!("Error: directory '{}' already exists.", name);
+        std::process::exit(1);
+    }
+
+    let src_dir = project_dir.join("src");
+    std::fs::create_dir_all(&src_dir).unwrap_or_else(|e| {
+        eprintln!("Error creating directory: {}", e);
+        std::process::exit(1);
+    });
+
+    let files = scaffold_files(name, async_mode);
+    std::fs::write(project_dir.join("Cargo.toml"), files.cargo_toml)
+        .expect("Failed to write Cargo.toml");
+    std::fs::write(
+        project_dir.join("rust-toolchain.toml"),
+        files.rust_toolchain_toml,
+    )
+    .expect("Failed to write rust-toolchain.toml");
+    std::fs::write(project_dir.join(".gitignore"), files.gitignore)
+        .expect("Failed to write .gitignore");
+    std::fs::write(project_dir.join("README.md"), files.readme).expect("Failed to write README.md");
+    std::fs::write(src_dir.join("main.rs"), files.main_rs).expect("Failed to write src/main.rs");
+
+    let mode = if async_mode { " (async)" } else { "" };
+    println!("✓ Created cuda-oxide project '{}'{}", name, mode);
+    println!();
+    println!("  cd {}", name);
+    println!("  cargo oxide doctor");
+    println!("  cargo oxide run");
+}
diff --git a/crates/cargo-oxide/src/commands/setup_update.rs b/crates/cargo-oxide/src/commands/setup_update.rs
new file mode 100644
index 0000000000..9b94686164
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/setup_update.rs
@@ -0,0 +1,141 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::backend;
+
+use super::*;
+
+// =============================================================================
+// Setup command
+// =============================================================================
+
+/// Explicitly build (or rebuild) the codegen backend.
+///
+/// Normally the backend is built automatically on every `run`/`build`/`pipeline`
+/// invocation. `setup` exists for first-time setup, CI, or after pulling new
+/// changes when you want to rebuild without running an example.
+pub fn setup(ctx: &Context) {
+    println!("Building cuda-oxide codegen backend...");
+    println!();
+
+    let built_so = backend::build_backend_from_source(&ctx.codegen_crate);
+
+    println!();
+    println!("✓ Backend is ready. You can now use:");
+    println!("  cargo oxide run <example>");
+    println!("  cargo oxide build <example>");
+
+    // A project outside this repository resolves the backend through the
+    // shared cache, since `find_workspace_root` finds no
+    // `crates/rustc-codegen-cuda` above it. Publishing the build there keeps
+    // those projects on the backend that was just built instead of on whatever
+    // the cache last held.
+    match backend::publish_to_cache(&built_so) {
+        Some(path) => {
+            println!();
+            println!("✓ Published to {}", path.display());
+            println!("  Projects outside this repo will now use this build.");
+        }
+        None => {
+            eprintln!();
+            eprintln!("Warning: could not publish the backend to the shared cache.");
+            eprintln!("Projects outside this repo may keep using an older build.");
+            eprintln!("Set CUDA_OXIDE_BACKEND to this build to override.");
+        }
+    }
+}
+
+/// How `cargo oxide update` should behave for the current project mode.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum UpdatePlan {
+    /// Inside the monorepo: tell the user to run `setup` (non-destructive).
+    AdviseSetup,
+    /// Inside the monorepo with `--force`: rebuild via `setup`.
+    RunSetup,
+    /// Outside the monorepo: clear and rebuild the shared cache.
+    RefreshCache,
+}
+
+pub fn plan_update(is_workspace: bool, force: bool) -> UpdatePlan {
+    match (is_workspace, force) {
+        (true, false) => UpdatePlan::AdviseSetup,
+        (true, true) => UpdatePlan::RunSetup,
+        (false, _) => UpdatePlan::RefreshCache,
+    }
+}
+
+/// Refresh the codegen backend used by this project.
+///
+/// Inside the cuda-oxide workspace the authoritative backend is the local
+/// source tree, so the default path points at `cargo oxide setup`. Outside
+/// the workspace, the shared `~/.cargo/cuda-oxide/` cache is cleared and
+/// rebuilt via the auto-fetch path.
+/// The backend pin that outranks the shared cache `update` refreshes, if any.
+///
+/// Both the `CUDA_OXIDE_BACKEND` env var and a `.cargo/cuda-oxide.toml`
+/// `backend` entry sit above the cache in backend discovery, so a refreshed
+/// cache would never be consulted while either is set. `update` refuses
+/// rather than mislead.
+fn update_pin_refusal(ctx: &Context) -> Option<String> {
+    update_pin_refusal_with_env(ctx, std::env::var_os("CUDA_OXIDE_BACKEND"))
+}
+
+/// `update_pin_refusal` with the ambient `CUDA_OXIDE_BACKEND` injected.
+///
+/// The env var is checked before the project pin, so resolution has to be
+/// injectable for unit tests: a developer with `CUDA_OXIDE_BACKEND` exported
+/// would otherwise get the env refusal for every input, including the
+/// unpinned case that must return `None`. Same rationale as
+/// `nvvm_ir_requested_with_env`.
+pub(super) fn update_pin_refusal_with_env(
+    ctx: &Context,
+    backend_env: Option<std::ffi::OsString>,
+) -> Option<String> {
+    if backend_env.is_some() {
+        return Some(
+            "CUDA_OXIDE_BACKEND is set, so `cargo oxide update` will not\n\
+             modify the shared cache. Unset CUDA_OXIDE_BACKEND and re-run, or\n\
+             rebuild the pinned backend path yourself."
+                .to_string(),
+        );
+    }
+    ctx.config.backend.as_deref().map(|pinned| {
+        format!(
+            "`.cargo/cuda-oxide.toml` pins the backend to {}, so\n\
+             `cargo oxide update` will not modify the shared cache. Remove the\n\
+             `backend` entry and re-run, or rebuild the pinned path yourself.",
+            pinned.display()
+        )
+    })
+}
+
+pub fn update(ctx: &Context, force: bool) {
+    if let Some(refusal) = update_pin_refusal(ctx) {
+        eprintln!("Error: {refusal}");
+        std::process::exit(1);
+    }
+
+    match plan_update(ctx.is_workspace, force) {
+        UpdatePlan::AdviseSetup => {
+            println!("Inside the cuda-oxide workspace the codegen backend is built from");
+            println!("local source (`crates/rustc-codegen-cuda`).");
+            println!();
+            println!("Run `cargo oxide setup` to rebuild and publish to the shared cache,");
+            println!("or pass `--force` to run setup from this command.");
+        }
+        UpdatePlan::RunSetup => {
+            println!("`--force` requested inside the workspace; running setup...");
+            println!();
+            setup(ctx);
+        }
+        UpdatePlan::RefreshCache => {
+            println!("Refreshing the shared codegen backend cache for external projects...");
+            println!();
+            let so = backend::refresh_cached_backend();
+            println!();
+            println!("✓ Cached backend ready at {}", so.display());
+        }
+    }
+}
diff --git a/crates/cargo-oxide/src/commands/tests.rs b/crates/cargo-oxide/src/commands/tests.rs
new file mode 100644
index 0000000000..4b0958e311
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/tests.rs
@@ -0,0 +1,4227 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::collections::BTreeMap;
+use std::fs;
+use std::path::{Path, PathBuf};
+use std::process::Command;
+
+use super::*;
+use std::ffi::OsStr;
+
+/// The concatenated sources of every module under `commands/`, standing in
+/// for the old single-file `commands.rs` that the source-scanning tests
+/// below used to read with `include_str!`.
+const COMMANDS_SOURCE: &str = concat!(
+    include_str!("mod.rs"),
+    include_str!("artifacts.rs"),
+    include_str!("build_run.rs"),
+    include_str!("clean.rs"),
+    include_str!("codegen_env.rs"),
+    include_str!("context.rs"),
+    include_str!("doctor.rs"),
+    include_str!("examples_list.rs"),
+    include_str!("fingerprint.rs"),
+    include_str!("fmt.rs"),
+    include_str!("host_cargo.rs"),
+    include_str!("interop.rs"),
+    include_str!("ltoir.rs"),
+    include_str!("materialize.rs"),
+    include_str!("passthrough.rs"),
+    include_str!("pipeline_debug.rs"),
+    include_str!("scaffold.rs"),
+    include_str!("setup_update.rs"),
+    include_str!("tests.rs"),
+    include_str!("toolkit.rs"),
+);
+
+fn command_env(cmd: &Command, key: &str) -> Option<String> {
+    cmd.get_envs()
+        .find(|(name, _)| *name == OsStr::new(key))
+        .and_then(|(_, value)| value.map(|v| v.to_string_lossy().into_owned()))
+}
+
+fn decoded_rustflags(encoded: &str) -> Vec<&str> {
+    encoded.split(ENCODED_RUSTFLAGS_SEPARATOR).collect()
+}
+
+fn has_backend_identity_cfg(flags: &[&str]) -> bool {
+    flags.windows(2).any(|pair| {
+        pair[0] == "--cfg"
+            && pair[1].starts_with("cuda_oxide_internal_backend_identity=\"")
+            && pair[1].ends_with('"')
+    })
+}
+
+fn is_sha256(value: &str) -> bool {
+    value.len() == 64
+        && value
+            .bytes()
+            .all(|byte| byte.is_ascii_digit() || matches!(byte, b'a'..=b'f'))
+}
+
+/// `cargo_passthrough_command` with an empty ambient
+/// `CUDA_OXIDE_MATERIALIZE_CUBIN`.
+///
+/// Every test builds the command through this. Reading the real variable
+/// would let an exported value override `opts.materialize_cubin` and drive
+/// the test into materializer discovery, which re-executes the libtest
+/// binary and then exits the process -- aborting the whole suite instead of
+/// failing one case.
+fn passthrough_command_for_test(
+    ctx: &Context,
+    cargo_subcommand: CargoPassthroughSubcommand,
+    opts: &CargoPassthroughOptions<'_>,
+    cargo_args: &[String],
+) -> Result<Command, String> {
+    cargo_passthrough_command_with_env(ctx, cargo_subcommand, opts, cargo_args, None)
+}
+
+fn cargo_artifact_freshness(
+    ctx: &Context,
+    opts: &CargoPassthroughOptions<'_>,
+    materializer_provenance: Option<&str>,
+) -> BTreeMap<String, bool> {
+    let mut cmd = passthrough_command_for_test(
+        ctx,
+        CargoPassthroughSubcommand::Build,
+        opts,
+        &["--message-format=json-render-diagnostics".to_string()],
+    )
+    .unwrap();
+    if let Some(provenance) = materializer_provenance {
+        // Exercise a non-canonical spelling accepted by the backend. The
+        // macro must still track exact provenance rather than keying that
+        // dependency on the wrapper's canonical `1` spelling.
+        cmd.env(MATERIALIZE_ENV, "true");
+        cmd.env(EXPECTED_PROVENANCE_ENV, provenance);
+    }
+    let output = cmd.output().expect("failed to run Cargo cache probe");
+    assert!(
+        output.status.success(),
+        "Cargo cache probe failed:\n{}",
+        String::from_utf8_lossy(&output.stderr)
+    );
+
+    String::from_utf8(output.stdout)
+        .expect("Cargo JSON must be UTF-8")
+        .lines()
+        .filter_map(|line| serde_json::from_str::<serde_json::Value>(line).ok())
+        .filter(|message| message["reason"] == "compiler-artifact")
+        .filter_map(|message| {
+            Some((
+                message["target"]["name"].as_str()?.to_string(),
+                message["fresh"].as_bool()?,
+            ))
+        })
+        .collect()
+}
+
+fn test_context(config: OxideConfig) -> Context {
+    Context {
+        workspace_root: PathBuf::from("/tmp/cargo-oxide-test-workspace"),
+        codegen_crate: PathBuf::from("/tmp/cargo-oxide-test-codegen"),
+        examples_dir: PathBuf::from("/tmp/cargo-oxide-test-examples"),
+        backend_so: PathBuf::from("llvm"),
+        is_workspace: false,
+        config,
+    }
+}
+
+fn unique_temp_dir(prefix: &str) -> PathBuf {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    std::env::temp_dir().join(format!("{}_{}_{}", prefix, std::process::id(), unique))
+}
+
+/// The examples walk backing `cargo oxide fmt` must reach nested manifests
+/// and skip build directories.
+///
+/// The gate's glob is `examples/**/Cargo.toml`, so a nested manifest is a
+/// scope of its own; the loop this replaced read only the first level, which
+/// is how `cutile_inter_kernel/simt` and `interop_cubin_identity/device`
+/// went unformatted. `target` is skipped because a working tree has one and
+/// a packaged manifest under it is not a crate this repository formats.
+#[test]
+fn collect_example_manifests_reaches_nested_and_skips_target() {
+    let root = unique_temp_dir("cargo_oxide_fmt_walk");
+    let write = |rel: &str| {
+        let path = root.join(rel);
+        std::fs::create_dir_all(path.parent().unwrap()).unwrap();
+        std::fs::write(&path, "[package]\nname = \"x\"\n").unwrap();
+    };
+
+    write("plain/Cargo.toml");
+    write("with_member/Cargo.toml");
+    write("with_member/kernel-lib/Cargo.toml");
+    write("own_workspace/Cargo.toml");
+    write("own_workspace/simt/Cargo.toml");
+    write("built/Cargo.toml");
+    write("built/target/package/vendored/Cargo.toml");
+    write(".hidden/Cargo.toml");
+    std::fs::create_dir_all(root.join("no_manifest_here")).unwrap();
+
+    let mut found = Vec::new();
+    collect_example_manifests(&root, &mut found);
+    let mut got: Vec<String> = found
+        .iter()
+        .map(|p| {
+            p.strip_prefix(&root)
+                .unwrap()
+                .to_string_lossy()
+                .replace(std::path::MAIN_SEPARATOR, "/")
+        })
+        .collect();
+    got.sort();
+
+    assert_eq!(
+        got,
+        vec![
+            // `built` itself is a real example; only the manifest inside
+            // its `target/` is skipped.
+            "built/Cargo.toml",
+            "own_workspace/Cargo.toml",
+            "own_workspace/simt/Cargo.toml",
+            "plain/Cargo.toml",
+            "with_member/Cargo.toml",
+            "with_member/kernel-lib/Cargo.toml",
+        ],
+        "expected both nested manifests, and neither the one under target/ \
+             nor the one in a dot directory"
+    );
+
+    let _ = std::fs::remove_dir_all(&root);
+}
+
+fn test_materializer_handshake() -> cuda_artifact_finalizer::MaterializerHandshakeV1 {
+    let file = cuda_artifact_finalizer::ToolFileIdentity {
+        length: 123,
+        modified_seconds: 456,
+        modified_nanoseconds: 789,
+        device: Some(10),
+        inode: Some(11),
+        change_time_seconds: Some(12),
+        change_time_nanoseconds: Some(13),
+    };
+    cuda_artifact_finalizer::MaterializerHandshakeV1::new(
+        cuda_artifact_finalizer::PinnedToolProvenance {
+            sha256: [1; 32],
+            file,
+        },
+        cuda_artifact_finalizer::PinnedToolProvenance {
+            sha256: [2; 32],
+            file,
+        },
+        [3; 32],
+    )
+}
+
+#[test]
+fn strict_materialization_boolean_rejects_presence_only_values() {
+    for value in ["1", "true", " YES ", "on"] {
+        assert!(parse_strict_bool(MATERIALIZE_ENV, value).unwrap());
+    }
+    for value in ["0", "false", " NO ", "off"] {
+        assert!(!parse_strict_bool(MATERIALIZE_ENV, value).unwrap());
+    }
+    for value in ["", "enabled", "2"] {
+        let error = parse_strict_bool(MATERIALIZE_ENV, value).unwrap_err();
+        assert!(error.contains("must be a boolean"), "{error}");
+    }
+}
+
+#[test]
+fn materialization_rejects_nvvm_ir_as_a_competing_final_output() {
+    let error = prepare_materialization_result(
+        &test_context(OxideConfig::default()),
+        true,
+        Some("sm_90"),
+        true,
+    )
+    .expect_err("the two user-facing final output modes must conflict");
+
+    assert!(error.contains("cannot be combined with --emit-nvvm-ir"));
+}
+
+#[test]
+fn materializer_discovery_uses_the_same_project_tool_environment_as_rustc() {
+    let configured_libdevice = "/configured/cuda/nvvm/libdevice/libdevice.10.bc";
+    let ctx = test_context(OxideConfig {
+        env: vec![
+            (
+                "CUDA_OXIDE_LIBDEVICE".to_string(),
+                configured_libdevice.to_string(),
+            ),
+            (
+                "CUDA_TOOLKIT_PATH".to_string(),
+                "/configured/cuda".to_string(),
+            ),
+            (
+                "LD_LIBRARY_PATH".to_string(),
+                "/configured/cuda/lib64".to_string(),
+            ),
+            (
+                MATERIALIZER_HANDSHAKE_ENV.to_string(),
+                "ambient-handshake-must-not-be-used".to_string(),
+            ),
+        ],
+        ..OxideConfig::default()
+    });
+    let discovery = materializer_discovery_command(&ctx, Path::new("/fake/cargo-oxide"));
+    let mut rustc_child = Command::new("cargo");
+    apply_common_codegen_env(
+        &mut rustc_child,
+        &ctx,
+        false,
+        false,
+        false,
+        DeviceDebug::Off,
+    );
+
+    for key in [
+        "CUDA_OXIDE_LIBDEVICE",
+        "CUDA_TOOLKIT_PATH",
+        "LD_LIBRARY_PATH",
+    ] {
+        assert_eq!(
+            command_env(&discovery, key),
+            command_env(&rustc_child, key),
+            "discovery and rustc must see the same {key}"
+        );
+    }
+    if std::env::var_os("CUDA_OXIDE_LIBDEVICE").is_none() {
+        assert_eq!(
+            command_env(&discovery, "CUDA_OXIDE_LIBDEVICE").as_deref(),
+            Some(configured_libdevice)
+        );
+    }
+    assert_eq!(command_env(&discovery, MATERIALIZER_HANDSHAKE_ENV), None);
+}
+
+#[test]
+fn materializer_handshake_cache_accepts_only_consistent_v1_records() {
+    let root = unique_temp_dir("cargo_oxide_materializer_handshake");
+    fs::create_dir(&root).unwrap();
+    let mut ctx = test_context(OxideConfig::default());
+    ctx.workspace_root = root.clone();
+    let handshake = test_materializer_handshake();
+
+    write_materializer_handshake_cache(&ctx, &handshake);
+    let cached = read_materializer_handshake_cache(&ctx).unwrap();
+    assert_eq!(
+        serde_json::from_str::<cuda_artifact_finalizer::MaterializerHandshakeV1>(&cached).unwrap(),
+        handshake,
+    );
+
+    let mut inconsistent = handshake;
+    inconsistent.libnvvm.sha256[0] ^= 1;
+    fs::write(
+        materializer_handshake_cache_path(&ctx),
+        serde_json::to_string(&inconsistent).unwrap(),
+    )
+    .unwrap();
+    assert!(read_materializer_handshake_cache(&ctx).is_none());
+
+    fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn artifact_stem_normalizes_hyphens_like_cargo() {
+    assert_eq!(artifact_stem("rustlantis-smoke"), "rustlantis_smoke");
+    assert_eq!(artifact_stem("vecadd"), "vecadd");
+}
+
+#[test]
+fn emit_ltoir_paths_use_normalized_crate_stem() {
+    // Regression for the emit-ltoir read/write mismatch on hyphenated
+    // crates: the backend writes `rustlantis_smoke.{ll,ltoir}`, so both the
+    // NVVM IR read and the default LTOIR write must resolve to the
+    // underscore stem rather than the raw example name.
+    let dir = Path::new("/tmp/cargo-oxide-emit-ltoir");
+    assert_eq!(
+        emitted_ll_path(dir, "rustlantis-smoke"),
+        dir.join("rustlantis_smoke.ll")
+    );
+    assert_eq!(
+        default_ltoir_path(dir, "rustlantis-smoke"),
+        dir.join("rustlantis_smoke.ltoir")
+    );
+    // A non-hyphenated example is unaffected.
+    assert_eq!(emitted_ll_path(dir, "vecadd"), dir.join("vecadd.ll"));
+    assert_eq!(default_ltoir_path(dir, "vecadd"), dir.join("vecadd.ltoir"));
+}
+
+#[test]
+fn generated_file_cleanup_preserves_ltoir_cubin_cache() {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    let root = std::env::temp_dir().join(format!(
+        "cuda_oxide_clean_cache_{}_{}",
+        std::process::id(),
+        unique
+    ));
+    std::fs::create_dir_all(&root).unwrap();
+    for extension in ["ptx", "ll", "ltoir", "cubin", "target"] {
+        std::fs::write(root.join(format!("my_kernel.{extension}")), b"stale").unwrap();
+    }
+    let cached_cubin = root.join(".oxide-artifacts/ltoir-cubin-cache/v1/entries/key/image.cubin");
+    std::fs::create_dir_all(cached_cubin.parent().unwrap()).unwrap();
+    std::fs::write(&cached_cubin, b"persistent cache entry").unwrap();
+
+    clean_generated_files(&root, "my-kernel");
+
+    for extension in ["ptx", "ll", "ltoir", "cubin", "target"] {
+        assert!(!root.join(format!("my_kernel.{extension}")).exists());
+    }
+    assert_eq!(
+        std::fs::read(&cached_cubin).unwrap(),
+        b"persistent cache entry"
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn clean_removes_only_local_target_and_matching_artifacts() {
+    let root = unique_temp_dir("cargo_oxide_clean_standalone");
+    std::fs::create_dir_all(root.join("target/debug")).unwrap();
+
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"
+[package]
+name = "my-kernel"
+version = "0.1.0"
+edition = "2024"
+"#,
+    )
+    .unwrap();
+
+    for suffix in GENERATED_ARTIFACT_SUFFIXES {
+        std::fs::write(root.join(format!("my_kernel.{suffix}")), b"generated").unwrap();
+    }
+
+    let unrelated_artifact = root.join("other_kernel.ptx");
+    std::fs::write(&unrelated_artifact, b"preserve").unwrap();
+
+    let cached_cubin = root.join(".oxide-artifacts/ltoir-cubin-cache/v1/entries/key/image.cubin");
+    std::fs::create_dir_all(cached_cubin.parent().unwrap()).unwrap();
+    std::fs::write(&cached_cubin, b"persistent cache").unwrap();
+
+    let ctx = Context {
+        workspace_root: root.clone(),
+        codegen_crate: root.clone(),
+        examples_dir: root.clone(),
+        backend_so: root.join("unused-backend.so"),
+        is_workspace: false,
+        config: OxideConfig::default(),
+    };
+
+    let summary = clean_context(&ctx).unwrap();
+
+    assert_eq!(summary.removed_directories, 1);
+    assert_eq!(summary.removed_files, GENERATED_ARTIFACT_SUFFIXES.len());
+    assert!(!root.join("target").exists());
+
+    for suffix in GENERATED_ARTIFACT_SUFFIXES {
+        assert!(!root.join(format!("my_kernel.{suffix}")).exists());
+    }
+
+    assert_eq!(std::fs::read(&unrelated_artifact).unwrap(), b"preserve");
+    assert_eq!(std::fs::read(&cached_cubin).unwrap(), b"persistent cache");
+
+    let second_summary = clean_context(&ctx).unwrap();
+
+    assert_eq!(second_summary, CleanSummary::default());
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn workspace_clean_removes_root_backend_and_example_targets() {
+    let root = unique_temp_dir("cargo_oxide_clean_workspace");
+    let codegen_crate = root.join("crates/rustc-codegen-cuda");
+    let examples_dir = codegen_crate.join("examples");
+    let example_dir = examples_dir.join("demo");
+
+    std::fs::create_dir_all(root.join("target/debug")).unwrap();
+    std::fs::create_dir_all(codegen_crate.join("target/debug")).unwrap();
+    std::fs::create_dir_all(example_dir.join("target/debug")).unwrap();
+
+    std::fs::write(
+        example_dir.join("Cargo.toml"),
+        r#"
+[package]
+name = "demo"
+version = "0.1.0"
+edition = "2024"
+"#,
+    )
+    .unwrap();
+
+    std::fs::write(example_dir.join("demo.ptx"), b"generated").unwrap();
+
+    let ctx = Context {
+        workspace_root: root.clone(),
+        codegen_crate: codegen_crate.clone(),
+        examples_dir,
+        backend_so: root.join("unused-backend.so"),
+        is_workspace: true,
+        config: OxideConfig::default(),
+    };
+
+    let summary = clean_context(&ctx).unwrap();
+
+    assert_eq!(summary.removed_directories, 3);
+    assert_eq!(summary.removed_files, 1);
+    assert!(!root.join("target").exists());
+    assert!(!codegen_crate.join("target").exists());
+    assert!(!example_dir.join("target").exists());
+    assert!(!example_dir.join("demo.ptx").exists());
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[cfg(unix)]
+#[test]
+fn clean_refuses_symlinked_target_directory() {
+    use std::os::unix::fs::symlink;
+
+    let root = unique_temp_dir("cargo_oxide_clean_symlink");
+    let external = unique_temp_dir("cargo_oxide_clean_external");
+
+    std::fs::create_dir_all(&root).unwrap();
+    std::fs::create_dir_all(&external).unwrap();
+    std::fs::write(external.join("sentinel"), b"preserve").unwrap();
+
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"
+[package]
+name = "symlink-test"
+version = "0.1.0"
+edition = "2024"
+"#,
+    )
+    .unwrap();
+
+    symlink(&external, root.join("target")).unwrap();
+
+    let ctx = Context {
+        workspace_root: root.clone(),
+        codegen_crate: root.clone(),
+        examples_dir: root.clone(),
+        backend_so: root.join("unused-backend.so"),
+        is_workspace: false,
+        config: OxideConfig::default(),
+    };
+
+    let error = clean_context(&ctx).unwrap_err();
+
+    assert!(error.contains("symlinked target directory"), "{error}");
+    assert_eq!(
+        std::fs::read(external.join("sentinel")).unwrap(),
+        b"preserve"
+    );
+
+    std::fs::remove_dir_all(root).unwrap();
+    std::fs::remove_dir_all(external).unwrap();
+}
+
+#[test]
+fn cargo_metadata_selection_prefers_default_run() {
+    let root = unique_temp_dir("cargo_oxide_default_run");
+    std::fs::create_dir_all(&root).unwrap();
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"
+[package]
+name = "multi-bin-package"
+default-run = "main_bin"
+version = "0.1.0"
+edition = "2024"
+
+[[bin]]
+name = "main_bin"
+path = "src/main.rs"
+
+[[bin]]
+name = "other_bin"
+path = "src/other.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::create_dir_all(root.join("src")).unwrap();
+    std::fs::write(root.join("src/main.rs"), "fn main() {}\n").unwrap();
+    std::fs::write(root.join("src/other.rs"), "fn main() {}\n").unwrap();
+
+    let selection = cargo_executable_selection(&root, None).unwrap();
+    assert_eq!(selection.packages.len(), 1);
+    let package = &selection.packages[0];
+    assert!(package.package_id.starts_with("path+file://"));
+    assert!(package.package_id.contains("multi-bin-package@0.1.0"));
+    assert_eq!(package.package_name, "multi-bin-package");
+    assert_eq!(package.default_run.as_deref(), Some("main_bin"));
+    assert_eq!(selection.explicit_bin, None);
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn cargo_json_ignores_bins_disabled_by_required_features() {
+    let root = unique_temp_dir("cargo_oxide_artifact_required_features");
+    std::fs::create_dir_all(root.join("src")).unwrap();
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"
+[package]
+name = "feature-gated-bins"
+version = "0.1.0"
+edition = "2024"
+
+[features]
+extra = []
+
+[[bin]]
+name = "always"
+path = "src/always.rs"
+
+[[bin]]
+name = "gated"
+path = "src/gated.rs"
+required-features = ["extra"]
+"#,
+    )
+    .unwrap();
+    std::fs::write(root.join("src/always.rs"), "fn main() {}\n").unwrap();
+    std::fs::write(root.join("src/gated.rs"), "fn main() {}\n").unwrap();
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release"]).current_dir(&root);
+    let binary = run_cargo_build_for_executable(&mut cmd, &root, None).unwrap();
+
+    let expected_name = format!("always{}", std::env::consts::EXE_SUFFIX);
+    assert_eq!(
+        binary.file_name().and_then(OsStr::to_str),
+        Some(expected_name.as_str())
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn cargo_json_selects_custom_bin_in_configured_target_dir() {
+    let root = unique_temp_dir("cargo_oxide_artifact_binary");
+    std::fs::create_dir_all(&root).unwrap();
+    std::fs::create_dir_all(root.join(".cargo")).unwrap();
+    std::fs::create_dir_all(root.join("src")).unwrap();
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"
+[package]
+name = "package-bin"
+version = "0.1.0"
+edition = "2024"
+
+[[bin]]
+name = "actual-bin"
+path = "src/main.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::write(root.join("src/main.rs"), "fn main() {}\n").unwrap();
+    std::fs::write(
+        root.join(".cargo/config.toml"),
+        "[build]\ntarget-dir = \"configured-target\"\n",
+    )
+    .unwrap();
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release"]).current_dir(&root);
+    let binary = run_cargo_build_for_executable(&mut cmd, &root, None).unwrap();
+
+    assert!(binary.exists());
+    let expected_name = format!("actual-bin{}", std::env::consts::EXE_SUFFIX);
+    assert_eq!(
+        binary.file_name().and_then(OsStr::to_str),
+        Some(expected_name.as_str())
+    );
+    assert!(
+        binary
+            .components()
+            .any(|part| part.as_os_str() == "configured-target")
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn cargo_json_selects_single_binary_from_virtual_workspace() {
+    let root = unique_temp_dir("cargo_oxide_artifact_workspace");
+    let member = root.join("member");
+    std::fs::create_dir_all(member.join("src")).unwrap();
+    std::fs::write(
+        root.join("Cargo.toml"),
+        "[workspace]\nmembers = [\"member\"]\nresolver = \"2\"\n",
+    )
+    .unwrap();
+    std::fs::write(
+        member.join("Cargo.toml"),
+        r#"
+[package]
+name = "workspace-package"
+version = "0.1.0"
+edition = "2024"
+
+[[bin]]
+name = "workspace-bin"
+path = "src/main.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::write(member.join("src/main.rs"), "fn main() {}\n").unwrap();
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release"]).current_dir(&root);
+    let binary = run_cargo_build_for_executable(&mut cmd, &root, None).unwrap();
+
+    let expected_name = format!("workspace-bin{}", std::env::consts::EXE_SUFFIX);
+    assert_eq!(
+        binary.file_name().and_then(OsStr::to_str),
+        Some(expected_name.as_str())
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn cargo_json_honors_virtual_workspace_default_member_default_run() {
+    let root = unique_temp_dir("cargo_oxide_artifact_default_member");
+    let app = root.join("app");
+    let ignored = root.join("ignored");
+    std::fs::create_dir_all(app.join("src")).unwrap();
+    std::fs::create_dir_all(ignored.join("src")).unwrap();
+    std::fs::write(
+            root.join("Cargo.toml"),
+            "[workspace]\nmembers = [\"app\", \"ignored\"]\ndefault-members = [\"app\"]\nresolver = \"2\"\n",
+        )
+        .unwrap();
+    std::fs::write(
+        app.join("Cargo.toml"),
+        r#"
+[package]
+name = "selected-package"
+default-run = "chosen-bin"
+version = "0.1.0"
+edition = "2024"
+
+[[bin]]
+name = "chosen-bin"
+path = "src/chosen.rs"
+
+[[bin]]
+name = "other-bin"
+path = "src/other.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::write(app.join("src/chosen.rs"), "fn main() {}\n").unwrap();
+    std::fs::write(app.join("src/other.rs"), "fn main() {}\n").unwrap();
+    std::fs::write(
+        ignored.join("Cargo.toml"),
+        r#"
+[package]
+name = "ignored-package"
+version = "0.1.0"
+edition = "2024"
+"#,
+    )
+    .unwrap();
+    std::fs::write(ignored.join("src/main.rs"), "fn main() {}\n").unwrap();
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release"]).current_dir(&root);
+    let binary = run_cargo_build_for_executable(&mut cmd, &root, None).unwrap();
+
+    let expected_name = format!("chosen-bin{}", std::env::consts::EXE_SUFFIX);
+    assert_eq!(
+        binary.file_name().and_then(OsStr::to_str),
+        Some(expected_name.as_str())
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn cargo_json_honors_nonvirtual_workspace_default_member() {
+    let root = unique_temp_dir("cargo_oxide_artifact_nonvirtual_default_member");
+    let member = root.join("member");
+    std::fs::create_dir_all(root.join("src")).unwrap();
+    std::fs::create_dir_all(member.join("src")).unwrap();
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"
+[package]
+name = "workspace-root-package"
+version = "0.1.0"
+edition = "2024"
+
+[workspace]
+members = ["member"]
+default-members = ["member"]
+resolver = "2"
+
+[[bin]]
+name = "root-bin"
+path = "src/main.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::write(root.join("src/main.rs"), "fn main() {}\n").unwrap();
+    std::fs::write(
+        member.join("Cargo.toml"),
+        r#"
+[package]
+name = "selected-member"
+version = "0.1.0"
+edition = "2024"
+
+[[bin]]
+name = "member-bin"
+path = "src/main.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::write(member.join("src/main.rs"), "fn main() {}\n").unwrap();
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release"]).current_dir(&root);
+    let binary = run_cargo_build_for_executable(&mut cmd, &root, None).unwrap();
+
+    let expected_name = format!("member-bin{}", std::env::consts::EXE_SUFFIX);
+    assert_eq!(
+        binary.file_name().and_then(OsStr::to_str),
+        Some(expected_name.as_str())
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn cargo_json_explicit_bin_selects_one_of_multiple_default_members() {
+    let root = unique_temp_dir("cargo_oxide_artifact_multiple_default_members");
+    let first = root.join("first");
+    let second = root.join("second");
+    std::fs::create_dir_all(first.join("src")).unwrap();
+    std::fs::create_dir_all(second.join("src")).unwrap();
+    std::fs::write(
+            root.join("Cargo.toml"),
+            "[workspace]\nmembers = [\"first\", \"second\"]\ndefault-members = [\"first\", \"second\"]\nresolver = \"2\"\n",
+        )
+        .unwrap();
+    std::fs::write(
+        first.join("Cargo.toml"),
+        r#"
+[package]
+name = "first-package"
+version = "0.1.0"
+edition = "2024"
+
+[[bin]]
+name = "first-bin"
+path = "src/main.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::write(first.join("src/main.rs"), "fn main() {}\n").unwrap();
+    std::fs::write(
+        second.join("Cargo.toml"),
+        r#"
+[package]
+name = "second-package"
+version = "0.1.0"
+edition = "2024"
+
+[[bin]]
+name = "chosen-bin"
+path = "src/main.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::write(second.join("src/main.rs"), "fn main() {}\n").unwrap();
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release", "--bin", "chosen-bin"])
+        .current_dir(&root);
+    let binary = run_cargo_build_for_executable(&mut cmd, &root, Some("chosen-bin")).unwrap();
+
+    let expected_name = format!("chosen-bin{}", std::env::consts::EXE_SUFFIX);
+    assert_eq!(
+        binary.file_name().and_then(OsStr::to_str),
+        Some(expected_name.as_str())
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn explicit_bin_must_be_unique_across_selected_packages() {
+    let selection = CargoExecutableSelection {
+        packages: vec![
+            CargoSelectedPackage {
+                package_id: "first-package 0.1.0".to_string(),
+                package_name: "first-package".to_string(),
+                default_run: None,
+            },
+            CargoSelectedPackage {
+                package_id: "second-package 0.1.0".to_string(),
+                package_name: "second-package".to_string(),
+                default_run: None,
+            },
+        ],
+        explicit_bin: Some("shared-bin".to_string()),
+    };
+    let artifacts = vec![
+        CargoExecutableArtifact {
+            package_id: "first-package 0.1.0".to_string(),
+            target_name: "shared-bin".to_string(),
+            path: PathBuf::from("/tmp/first/shared-bin"),
+        },
+        CargoExecutableArtifact {
+            package_id: "second-package 0.1.0".to_string(),
+            target_name: "shared-bin".to_string(),
+            path: PathBuf::from("/tmp/second/shared-bin"),
+        },
+    ];
+
+    let error = select_cargo_executable_artifact(&selection, &artifacts)
+        .expect_err("the binary name does not uniquely identify an artifact");
+
+    assert!(error.contains("multiple selected packages"), "{error}");
+    assert!(error.contains("first-package"), "{error}");
+    assert!(error.contains("second-package"), "{error}");
+}
+
+#[test]
+fn one_executable_package_is_selected_alongside_library_only_defaults() {
+    let selection = CargoExecutableSelection {
+        packages: vec![
+            CargoSelectedPackage {
+                package_id: "library-package 0.1.0".to_string(),
+                package_name: "library-package".to_string(),
+                default_run: None,
+            },
+            CargoSelectedPackage {
+                package_id: "application-package 0.1.0".to_string(),
+                package_name: "application-package".to_string(),
+                default_run: None,
+            },
+        ],
+        explicit_bin: None,
+    };
+    let artifact = CargoExecutableArtifact {
+        package_id: "application-package 0.1.0".to_string(),
+        target_name: "application-bin".to_string(),
+        path: PathBuf::from("/tmp/application/application-bin"),
+    };
+
+    assert_eq!(
+        select_cargo_executable_artifact(&selection, &[artifact]).unwrap(),
+        PathBuf::from("/tmp/application/application-bin")
+    );
+}
+
+#[test]
+fn unbuilt_default_run_is_not_skipped_for_another_selected_package() {
+    let selection = CargoExecutableSelection {
+        packages: vec![
+            CargoSelectedPackage {
+                package_id: "first-package 0.1.0".to_string(),
+                package_name: "first-package".to_string(),
+                default_run: Some("gated-bin".to_string()),
+            },
+            CargoSelectedPackage {
+                package_id: "second-package 0.1.0".to_string(),
+                package_name: "second-package".to_string(),
+                default_run: None,
+            },
+        ],
+        explicit_bin: None,
+    };
+    let artifacts = [CargoExecutableArtifact {
+        package_id: "second-package 0.1.0".to_string(),
+        target_name: "other-bin".to_string(),
+        path: PathBuf::from("/tmp/second/other-bin"),
+    }];
+
+    let error = select_cargo_executable_artifact(&selection, &artifacts)
+        .expect_err("a missing default-run must not fall back to another package");
+
+    assert!(error.contains("first-package"), "{error}");
+    assert!(error.contains("target `gated-bin`"), "{error}");
+}
+
+#[test]
+fn cargo_json_errors_when_requested_bin_was_not_built() {
+    let root = unique_temp_dir("cargo_oxide_artifact_missing_bin");
+    std::fs::create_dir_all(root.join("src")).unwrap();
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"
+[package]
+name = "package-bin"
+version = "0.1.0"
+edition = "2024"
+
+[[bin]]
+name = "actual-bin"
+path = "src/actual.rs"
+
+[[bin]]
+name = "other-bin"
+path = "src/other.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::write(root.join("src/actual.rs"), "fn main() {}\n").unwrap();
+    std::fs::write(root.join("src/other.rs"), "fn main() {}\n").unwrap();
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release", "--bin", "actual-bin"])
+        .current_dir(&root);
+    let error = run_cargo_build_for_executable(&mut cmd, &root, Some("other-bin"))
+        .expect_err("requested but unbuilt binary should be rejected");
+
+    assert!(error.contains("target `other-bin`"), "{error}");
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn cargo_json_errors_when_default_run_was_not_built() {
+    let root = unique_temp_dir("cargo_oxide_artifact_missing_default_run");
+    std::fs::create_dir_all(root.join("src")).unwrap();
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"
+[package]
+name = "package-bin"
+default-run = "default-bin"
+version = "0.1.0"
+edition = "2024"
+
+[[bin]]
+name = "default-bin"
+path = "src/default.rs"
+
+[[bin]]
+name = "other-bin"
+path = "src/other.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::write(root.join("src/default.rs"), "fn main() {}\n").unwrap();
+    std::fs::write(root.join("src/other.rs"), "fn main() {}\n").unwrap();
+
+    let mut cmd = Command::new("cargo");
+    cmd.args(["build", "--release", "--bin", "other-bin"])
+        .current_dir(&root);
+    let error = run_cargo_build_for_executable(&mut cmd, &root, None)
+        .expect_err("unbuilt default-run binary should be rejected");
+
+    assert!(error.contains("target `default-bin`"), "{error}");
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn artifact_selection_ignores_executable_artifacts_from_other_packages() {
+    let selection = CargoExecutableSelection {
+        packages: vec![CargoSelectedPackage {
+            package_id: "app 0.1.0".to_string(),
+            package_name: "app".to_string(),
+            default_run: None,
+        }],
+        explicit_bin: Some("app-bin".to_string()),
+    };
+    let artifacts = vec![
+        CargoExecutableArtifact {
+            package_id: "build-tool 0.1.0".to_string(),
+            target_name: "app-bin".to_string(),
+            path: PathBuf::from("/tmp/build-tool/app-bin"),
+        },
+        CargoExecutableArtifact {
+            package_id: "app 0.1.0".to_string(),
+            target_name: "helper-bin".to_string(),
+            path: PathBuf::from("/tmp/app/helper-bin"),
+        },
+    ];
+
+    let error = select_cargo_executable_artifact(&selection, &artifacts)
+        .expect_err("foreign package artifacts must not be selected");
+    assert!(error.contains("target `app-bin`"), "{error}");
+    assert!(error.contains("selected packages app"), "{error}");
+}
+
+#[test]
+fn sanitizer_adds_nonzero_error_exitcode_by_default() {
+    let invocation = sanitizer_invocation_args(&["--leak-check".to_string(), "full".to_string()]);
+
+    assert_eq!(
+        invocation.args,
+        ["--error-exitcode", "86", "--leak-check", "full"]
+    );
+    assert!(invocation.uses_default_error_exitcode);
+    assert!(!invocation.status_checks_weakened);
+}
+
+#[test]
+fn sanitizer_preserves_explicit_zero_error_exitcode_without_claiming_detection() {
+    let separated = sanitizer_invocation_args(&[
+        "--error-exitcode".to_string(),
+        "0".to_string(),
+        "--leak-check".to_string(),
+    ]);
+    let equals = sanitizer_invocation_args(&["--error-exitcode=0".to_string()]);
+    let repeated = sanitizer_invocation_args(&[
+        "--error-exitcode=86".to_string(),
+        "--error-exitcode=0".to_string(),
+    ]);
+
+    assert_eq!(separated.args, ["--error-exitcode", "0", "--leak-check"]);
+    assert!(!separated.uses_default_error_exitcode);
+    assert!(!separated.status_checks_weakened);
+    assert_eq!(equals.args, ["--error-exitcode=0"]);
+    assert!(!equals.uses_default_error_exitcode);
+    assert_eq!(repeated.args, ["--error-exitcode=86", "--error-exitcode=0"]);
+    assert!(!repeated.uses_default_error_exitcode);
+}
+
+#[test]
+fn sanitizer_detects_options_that_weaken_success_status() {
+    for args in [
+        vec!["--check-exit-code=no".to_string()],
+        vec!["--check-exit-code".to_string(), "no".to_string()],
+        vec!["--require-cuda-init=no".to_string()],
+        vec!["--require-cuda-init".to_string(), "NO".to_string()],
+    ] {
+        let invocation = sanitizer_invocation_args(&args);
+        assert!(invocation.status_checks_weakened, "{args:?}");
+    }
+}
+
+#[test]
+fn sanitize_interop_codegen_defaults_to_line_tables_and_forwards_no_fmad() {
+    let ctx = test_context(OxideConfig::default());
+    let mut cmd = Command::new("cargo");
+
+    apply_interop_device_codegen_options_with_env(
+        &mut cmd,
+        &ctx,
+        false,
+        InteropDeviceBuildOptions {
+            no_fmad: true,
+            unchecked_indexing: false,
+            sanitizer_line_tables: true,
+        },
+        false,
+    );
+
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_NO_FMA").as_deref(), Some("1"));
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_DEBUG").as_deref(),
+        Some("line-tables")
+    );
+
+    let fingerprint = sanitize_codegen_fingerprint(
+        &ctx,
+        false,
+        true,
+        false,
+        DeviceDebug::Off,
+        Some("sm_80"),
+        None,
+        Some(Path::new("/tmp/generated-ptx")),
+        &MaterializationMode::default(),
+    );
+    apply_codegen_configuration(
+        &mut cmd,
+        &ctx,
+        CodegenProfilePolicy::ReleaseLike,
+        &[],
+        &fingerprint,
+    )
+    .unwrap();
+    let encoded = command_env(&cmd, "CARGO_ENCODED_RUSTFLAGS").unwrap();
+    assert!(has_backend_identity_cfg(&decoded_rustflags(&encoded)));
+    assert_eq!(
+        command_env(&cmd, CODEGEN_FINGERPRINT_ENV).as_deref(),
+        Some(fingerprint.as_str())
+    );
+}
+
+#[test]
+fn sanitize_device_debug_flag_overrides_the_line_tables_default() {
+    let ctx = test_context(OxideConfig::default());
+    let mut cmd = Command::new("cargo");
+
+    // Mirror codegen_build_host_binary's ordering: the flag's level lands
+    // on `cmd` first, then the sanitizer default runs. `env_debug_set` is
+    // injected as false, so with no ambient CUDA_OXIDE_DEBUG the explicit
+    // flag alone must suppress the line-tables default.
+    apply_common_codegen_env(&mut cmd, &ctx, false, false, false, DeviceDebug::Full);
+    apply_default_sanitizer_line_tables_with_env(&mut cmd, &ctx, false, DeviceDebug::Full);
+
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_DEBUG").as_deref(),
+        Some("full")
+    );
+}
+
+#[test]
+fn standard_interop_codegen_forwards_no_fmad_without_debug_override() {
+    let ctx = test_context(OxideConfig::default());
+    let mut cmd = Command::new("cargo");
+
+    apply_interop_device_codegen_options_with_env(
+        &mut cmd,
+        &ctx,
+        false,
+        InteropDeviceBuildOptions::standard(true, false),
+        false,
+    );
+
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_NO_FMA").as_deref(), Some("1"));
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_DEBUG"), None);
+}
+
+#[test]
+fn interop_fingerprint_tracks_artifact_mode_and_device_features() {
+    let ctx = test_context(OxideConfig::default());
+    let fingerprint = |emit_nvvm_ir: bool, device_features: Option<&str>| {
+        interop_codegen_fingerprint(
+            &ctx,
+            false,
+            false,
+            false,
+            DeviceDebug::Off,
+            Some("sm_120a"),
+            None,
+            Path::new("/tmp/cuda-oxide-artifacts"),
+            emit_nvvm_ir,
+            device_features,
+            false,
+            &MaterializationMode::default(),
+        )
+    };
+
+    assert_ne!(fingerprint(false, None), fingerprint(true, None));
+    assert_ne!(
+        fingerprint(true, None),
+        fingerprint(true, Some("tensor-cores"))
+    );
+}
+
+#[test]
+fn interop_codegen_forwards_unchecked_indexing() {
+    let ctx = test_context(OxideConfig::default());
+    let mut cmd = Command::new("cargo");
+
+    apply_interop_device_codegen_options_with_env(
+        &mut cmd,
+        &ctx,
+        false,
+        InteropDeviceBuildOptions::standard(false, true),
+        false,
+    );
+
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_UNCHECKED_INDEXING").as_deref(),
+        Some("1")
+    );
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_NO_FMA"), None);
+}
+
+#[test]
+fn sanitize_fingerprint_tracks_output_affecting_settings() {
+    let ctx = test_context(OxideConfig::default());
+    // Empty inherited environment, matching
+    // `passthrough_fingerprint_tracks_output_affecting_settings`. An
+    // ambient CUDA_OXIDE_NO_FMA / CUDA_OXIDE_UNCHECKED_INDEXING is folded
+    // into the digest on its own, so reading the real environment would
+    // make toggling the corresponding argument a no-op and collapse these
+    // fingerprints onto the base.
+    let inherited_env = BTreeMap::new();
+    let fingerprint = |no_fmad: bool,
+                       unchecked_indexing: bool,
+                       target_arch: Option<&str>,
+                       detected_device_arch: Option<&str>,
+                       ptx_dir: Option<&Path>| {
+        sanitize_codegen_fingerprint_with_env(
+            &ctx,
+            false,
+            no_fmad,
+            unchecked_indexing,
+            DeviceDebug::Off,
+            target_arch,
+            detected_device_arch,
+            ptx_dir,
+            &MaterializationMode::default(),
+            &inherited_env,
+        )
+    };
+
+    let base = fingerprint(false, false, None, Some("sm_80"), None);
+
+    for changed in [
+        fingerprint(true, false, None, Some("sm_80"), None),
+        fingerprint(false, true, None, Some("sm_80"), None),
+        fingerprint(false, false, None, Some("sm_90"), None),
+        fingerprint(false, false, Some("sm_80"), None, None),
+        fingerprint(
+            false,
+            false,
+            None,
+            Some("sm_80"),
+            Some(Path::new("/tmp/generated-ptx")),
+        ),
+    ] {
+        assert_ne!(base, changed);
+    }
+}
+
+#[test]
+fn pipeline_diagnostics_have_a_distinct_device_fingerprint() {
+    let ctx = test_context(OxideConfig::default());
+    let materialization = MaterializationMode::default();
+    let standard = standard_codegen_fingerprint(
+        &ctx,
+        true,
+        false,
+        false,
+        DeviceDebug::Off,
+        false,
+        Some("sm_86"),
+        None,
+        &materialization,
+    );
+    let pipeline = pipeline_codegen_fingerprint(
+        &ctx,
+        false,
+        false,
+        DeviceDebug::Off,
+        false,
+        Some("sm_86"),
+        &materialization,
+    );
+
+    assert_ne!(standard, pipeline);
+}
+
+/// A `Context` whose `cuda-oxide.toml` points `CUDA_TOOLKIT_PATH` at
+/// `root`, alongside a fake executable named `name` under `root/bin`.
+fn toolkit_context_with_tool(root: &Path, name: &str) -> (Context, PathBuf) {
+    let tool = root.join("bin").join(name);
+    std::fs::create_dir_all(tool.parent().unwrap()).unwrap();
+    std::fs::write(&tool, b"fake tool").unwrap();
+    let ctx = test_context(OxideConfig {
+        env: vec![(
+            "CUDA_TOOLKIT_PATH".to_string(),
+            root.to_string_lossy().into_owned(),
+        )],
+        ..OxideConfig::default()
+    });
+    (ctx, tool)
+}
+
+/// Every table entry pairs a tool with its own fallback list. Pure, so it
+/// covers all three tools on every host: pairing `nvcc` with
+/// `CUDA_GDB_FALLBACK_PATHS` is a one-token slip that no filesystem test
+/// using a fabricated name could see.
+#[test]
+fn each_toolkit_tool_is_paired_with_its_own_fallback_paths() {
+    assert_eq!(DOCTOR_TOOLKIT_TOOLS.len(), 3);
+    for (name, fallbacks) in DOCTOR_TOOLKIT_TOOLS {
+        assert!(!fallbacks.is_empty(), "{name} has no fallback paths");
+        for path in fallbacks {
+            assert_eq!(
+                Path::new(path).file_name().and_then(|n| n.to_str()),
+                Some(name),
+                "{name} lists a fallback for a different tool: {path}"
+            );
+        }
+    }
+}
+
+/// The lookup itself: each tool gets its own list, and an unknown name gets
+/// none rather than another tool's. Pure, so it holds on every host.
+#[test]
+fn the_fallback_lookup_returns_each_tools_own_list() {
+    assert_eq!(toolkit_tool_fallbacks("nvcc"), NVCC_FALLBACK_PATHS);
+    assert_eq!(toolkit_tool_fallbacks("cuda-gdb"), CUDA_GDB_FALLBACK_PATHS);
+    assert_eq!(
+        toolkit_tool_fallbacks("compute-sanitizer"),
+        COMPUTE_SANITIZER_FALLBACK_PATHS
+    );
+    assert!(toolkit_tool_fallbacks("ptxas").is_empty());
+}
+
+/// Every call site names a tool the table knows. `doctor_toolkit_tool`
+/// falls back to an empty list for an unknown name, so a typo would
+/// silently drop the standard install roots rather than fail.
+#[test]
+fn every_doctor_toolkit_tool_call_names_a_tool_in_the_table() {
+    let source = COMMANDS_SOURCE;
+    let mut calls = 0;
+    for (index, _) in source.match_indices("doctor_toolkit_tool(ctx, \"") {
+        let rest = &source[index + "doctor_toolkit_tool(ctx, \"".len()..];
+        let name = &rest[..rest.find('"').expect("a closing quote")];
+        assert!(
+            DOCTOR_TOOLKIT_TOOLS.iter().any(|(tool, _)| *tool == name),
+            "{name} is probed but absent from DOCTOR_TOOLKIT_TOOLS, so it \
+                 would silently lose its fallback paths"
+        );
+        calls += 1;
+    }
+    assert_eq!(
+        calls,
+        DOCTOR_TOOLKIT_TOOLS.len(),
+        "every table entry is probed once"
+    );
+}
+
+/// Unaffected control: the configured toolkit root is preferred over the
+/// standard install roots, so pointing `CUDA_TOOLKIT_PATH` at a toolkit does
+/// not start picking up `/usr/local/cuda`. Discovery order is unchanged by
+/// this fix; only which function `doctor` calls changed.
+///
+/// PATH precedence is deliberately *not* asserted here. `find_executable`
+/// shells out to `which`, so testing it would mean mutating the process
+/// `PATH` -- `unsafe` in edition 2024 and racy across the test threads. The
+/// end-to-end evidence in the pull request covers that case against the real
+/// binary instead, which is the stronger check anyway.
+#[test]
+fn the_configured_root_is_preferred_over_the_standard_install_roots() {
+    let root = unique_temp_dir("cargo_oxide_doctor_order");
+    let name = "cuda-oxide-test-doctor-order";
+    let under_toolkit = root.join("bin").join(name);
+    std::fs::create_dir_all(under_toolkit.parent().unwrap()).unwrap();
+    std::fs::write(&under_toolkit, b"fake tool").unwrap();
+    let fallback = root.join("fallback").join(name);
+    std::fs::create_dir_all(fallback.parent().unwrap()).unwrap();
+    std::fs::write(&fallback, b"fake tool").unwrap();
+    let ctx = test_context(OxideConfig {
+        env: vec![(
+            "CUDA_TOOLKIT_PATH".to_string(),
+            root.to_string_lossy().into_owned(),
+        )],
+        ..OxideConfig::default()
+    });
+
+    let fallback_arg = fallback.to_string_lossy().into_owned();
+    assert_eq!(
+        find_cuda_toolkit_executable_with_env(&ctx, name, &[&fallback_arg], |_| None),
+        Some(under_toolkit),
+        "the configured toolkit root must win over a fallback path"
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+/// Negative: absent from PATH, from the configured root, and from the
+/// fallbacks is still `None` -- the fix must not invent a path.
+#[test]
+fn a_missing_tool_is_still_missing() {
+    let root = unique_temp_dir("cargo_oxide_doctor_absent");
+    std::fs::create_dir_all(&root).unwrap();
+    let ctx = test_context(OxideConfig {
+        env: vec![(
+            "CUDA_TOOLKIT_PATH".to_string(),
+            root.to_string_lossy().into_owned(),
+        )],
+        ..OxideConfig::default()
+    });
+    assert_eq!(
+        find_cuda_toolkit_executable_with_env(
+            &ctx,
+            "cuda-oxide-test-absent-tool",
+            &["/nonexistent/bin/cuda-oxide-test-absent-tool"],
+            |_| None,
+        ),
+        None
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+/// The invariant a table alone cannot hold: no CUDA toolkit executable may
+/// be probed with a bare `Command::new`, which is how `nvcc` and `cuda-gdb`
+/// came to disagree with the commands they predict. Read out of the source
+/// rather than from `DOCTOR_TOOLKIT_TOOLS`, so a tool left out of the table
+/// is still caught.
+#[test]
+fn no_toolkit_executable_is_probed_by_bare_path() {
+    let source = COMMANDS_SOURCE;
+    for tool in [
+        "nvcc",
+        "cuda-gdb",
+        "compute-sanitizer",
+        "ptxas",
+        "nvlink",
+        "fatbinary",
+        "nvdisasm",
+        "cuobjdump",
+    ] {
+        let bare = format!("Command::new(\"{tool}\")");
+        assert!(
+            !source.contains(&bare),
+            "{tool} is probed with {bare}, bypassing the toolkit root; \
+                 route it through doctor_toolkit_tool / find_cuda_toolkit_executable"
+        );
+    }
+}
+
+/// `doctor` predicts whether `debug` will work, so both must consult one
+/// list. A second inline copy is how they drifted apart.
+#[test]
+fn doctor_and_debug_share_one_cuda_gdb_fallback_list() {
+    let source = COMMANDS_SOURCE;
+    assert!(
+        source.matches("CUDA_GDB_FALLBACK_PATHS").count() >= 3,
+        "the shared list is not referenced by both call sites"
+    );
+    assert_eq!(
+        source.matches("\"/usr/local/cuda/bin/cuda-gdb\"").count(),
+        1,
+        "a second inline cuda-gdb path list has appeared"
+    );
+}
+
+#[test]
+fn sanitizer_tool_lookup_uses_project_cuda_toolkit_root() {
+    let root = unique_temp_dir("cargo_oxide_sanitizer_tool");
+    let (ctx, tool) = toolkit_context_with_tool(&root, "cuda-oxide-test-sanitizer");
+
+    // `|_| None` stands in for an empty ambient environment. Reading the
+    // real one would let an exported CUDA_TOOLKIT_PATH/CUDA_HOME shadow the
+    // configured root this test asserts on.
+    assert_eq!(
+        find_cuda_toolkit_executable_with_env(&ctx, "cuda-oxide-test-sanitizer", &[], |_| None),
+        Some(tool)
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn doctor_compute_sanitizer_lookup_matches_sanitize_discovery() {
+    // Hermetic: a fake tool name keeps the user's real PATH (and any
+    // installed compute-sanitizer) out of the lookup, the injected empty
+    // environment keeps an exported toolkit root out of it, and the shared
+    // fallback const exercises the exact argument both `doctor` and
+    // `sanitize` pass. The configured toolkit root wins before any
+    // fallback path is consulted.
+    let root = unique_temp_dir("cargo_oxide_doctor_sanitizer");
+    let (ctx, tool) = toolkit_context_with_tool(&root, "cuda-oxide-test-doctor-sanitizer");
+
+    assert_eq!(
+        find_cuda_toolkit_executable_with_env(
+            &ctx,
+            "cuda-oxide-test-doctor-sanitizer",
+            COMPUTE_SANITIZER_FALLBACK_PATHS,
+            |_| None,
+        ),
+        Some(tool)
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn ambient_cuda_toolkit_path_shadows_the_project_configured_root() {
+    // The precedence the two lookups above have to be insulated from: an
+    // exported CUDA_TOOLKIT_PATH outranks `cuda-oxide.toml`, so a tool
+    // present only under the configured root is not found.
+    let root = unique_temp_dir("cargo_oxide_ambient_shadow");
+    let (ctx, _tool) = toolkit_context_with_tool(&root, "cuda-oxide-test-shadowed-sanitizer");
+    let ambient = unique_temp_dir("cargo_oxide_ambient_root");
+
+    assert_eq!(
+        find_cuda_toolkit_executable_with_env(
+            &ctx,
+            "cuda-oxide-test-shadowed-sanitizer",
+            &[],
+            |key| (key == "CUDA_TOOLKIT_PATH").then(|| ambient.to_string_lossy().into_owned()),
+        ),
+        None
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn test_passthrough_defers_profile_flags_to_cargo_and_keeps_invariants() {
+    let rustflags = build_encoded_rustflags_with_existing(
+        Path::new("/tmp/librustc_codegen_cuda.so"),
+        CargoPassthroughSubcommand::Test.codegen_profile(),
+        &[],
+        &["--cfg".to_string(), "device_test".to_string()],
+        None,
+        None,
+    );
+    let flags = decoded_rustflags(&rustflags);
+
+    assert_eq!(
+        flags,
+        [
+            "--cfg",
+            "device_test",
+            "-Zcodegen-backend=/tmp/librustc_codegen_cuda.so",
+            "-Zmir-enable-passes=-JumpThreading",
+            "-Zalways-encode-mir",
+            "-Csymbol-mangling-version=v0",
+        ]
+    );
+    assert!(!flags.iter().any(|flag| flag.starts_with("-Copt-level")));
+    assert!(
+        !flags
+            .iter()
+            .any(|flag| flag.starts_with("-Cdebug-assertions"))
+    );
+    assert!(!flags.iter().any(|flag| flag.starts_with("-Cdebuginfo")));
+
+    let ctx = test_context(OxideConfig::default());
+    let opts = CargoPassthroughOptions {
+        verbose: false,
+        emit_nvvm_ir: false,
+        arch: None,
+        features: None,
+        cargo_target_dir: None,
+        device_codegen_crate: None,
+        device_cfgs: &[],
+        no_fmad: false,
+        unchecked_indexing: false,
+        materialize_cubin: false,
+        device_debug: DeviceDebug::Off,
+    };
+    for cargo_args in [
+        vec!["--release".to_string()],
+        vec!["--profile".to_string(), "ci".to_string()],
+    ] {
+        let cmd = passthrough_command_for_test(
+            &ctx,
+            CargoPassthroughSubcommand::Test,
+            &opts,
+            &cargo_args,
+        )
+        .unwrap();
+        let mut expected = vec!["test".to_string()];
+        expected.extend(cargo_args);
+        assert_eq!(
+            cmd.get_args()
+                .map(|arg| arg.to_string_lossy().into_owned())
+                .collect::<Vec<_>>(),
+            expected
+        );
+    }
+}
+
+#[test]
+fn build_passthrough_retains_release_profile_and_required_flags() {
+    let rustflags = build_encoded_rustflags_with_existing(
+        Path::new("/tmp/librustc_codegen_cuda.so"),
+        CargoPassthroughSubcommand::Build.codegen_profile(),
+        &[],
+        &[],
+        Some("-Lnative=/nix/store/cuda-cudart/lib\u{1f}-Copt-level=0\u{1f}-Zcodegen-backend=llvm"),
+        Some("-L native=/nix/store/cuda-cudart/lib"),
+    );
+    let flags = decoded_rustflags(&rustflags);
+
+    assert_eq!(flags[0], "-Lnative=/nix/store/cuda-cudart/lib");
+    assert!(flags.contains(&"-Copt-level=0"));
+    assert!(flags.contains(&"-Zcodegen-backend=llvm"));
+    assert_eq!(
+        &flags[flags.len() - 6..],
+        [
+            "-Zcodegen-backend=/tmp/librustc_codegen_cuda.so",
+            "-Copt-level=3",
+            "-Cdebug-assertions=off",
+            "-Zmir-enable-passes=-JumpThreading",
+            "-Zalways-encode-mir",
+            "-Csymbol-mangling-version=v0",
+        ]
+    );
+    assert!(!flags.contains(&"native=/nix/store/cuda-cudart/lib"));
+}
+
+#[test]
+fn encoded_rustflags_preserve_configured_flag_boundaries_and_spaces() {
+    let rustflags = build_encoded_rustflags_with_existing(
+        Path::new("/tmp/backend path/librustc_codegen_cuda.so"),
+        CodegenProfilePolicy::ReleaseLike,
+        &["--cfg".to_string(), "model=\"alpha beta\"".to_string()],
+        &[],
+        None,
+        Some("-L native=/nix/store/cuda-cudart/lib"),
+    );
+    let flags = decoded_rustflags(&rustflags);
+
+    assert!(
+        flags
+            .windows(2)
+            .any(|pair| pair == ["--cfg", "model=\"alpha beta\""])
+    );
+    assert_eq!(&flags[2..4], ["-L", "native=/nix/store/cuda-cudart/lib"]);
+    assert_eq!(
+        flags[flags.len() - 6],
+        "-Zcodegen-backend=/tmp/backend path/librustc_codegen_cuda.so"
+    );
+}
+
+#[test]
+fn encoded_rustflags_remove_legacy_global_codegen_fingerprints() {
+    let encoded = [
+        "--cfg",
+        "cuda_oxide_internal_codegen_env=\"inherited\"",
+        "--cfg=cuda_oxide_internal_materializer_provenance=\"inherited\"",
+        "--cfg",
+        "keep_inherited",
+    ]
+    .join(&ENCODED_RUSTFLAGS_SEPARATOR.to_string());
+    let rustflags = build_encoded_rustflags_with_existing(
+        Path::new("/tmp/librustc_codegen_cuda.so"),
+        CodegenProfilePolicy::ReleaseLike,
+        &[
+            "--cfg".to_string(),
+            "cuda_oxide_internal_codegen_env=\"configured\"".to_string(),
+            "--cfg".to_string(),
+            "keep_configured".to_string(),
+        ],
+        &[
+            "--cfg".to_string(),
+            "cuda_oxide_internal_materializer_provenance=\"explicit\"".to_string(),
+            "--cfg".to_string(),
+            "keep_explicit".to_string(),
+        ],
+        Some(&encoded),
+        None,
+    );
+    let flags = decoded_rustflags(&rustflags);
+
+    assert!(!flags.iter().any(|flag| {
+        flag.contains(LEGACY_CODEGEN_FINGERPRINT_CFG)
+            || flag.contains(LEGACY_MATERIALIZER_PROVENANCE_CFG)
+    }));
+    for retained in ["keep_configured", "keep_inherited", "keep_explicit"] {
+        assert!(flags.contains(&retained));
+    }
+}
+
+#[test]
+fn debug_profile_retains_release_defaults_and_adds_debuginfo() {
+    let rustflags = build_encoded_rustflags_with_existing(
+        Path::new("/tmp/librustc_codegen_cuda.so"),
+        CodegenProfilePolicy::ReleaseLikeWithDebugInfo,
+        &[],
+        &[],
+        None,
+        Some(""),
+    );
+    let flags = decoded_rustflags(&rustflags);
+
+    assert!(flags.contains(&"-Copt-level=3"));
+    assert!(flags.contains(&"-Cdebug-assertions=off"));
+    assert!(flags.contains(&"-Cdebuginfo=2"));
+    assert!(flags.contains(&"-Zmir-enable-passes=-JumpThreading"));
+    assert!(flags.contains(&"-Zalways-encode-mir"));
+    assert!(flags.contains(&"-Csymbol-mangling-version=v0"));
+    assert!(!flags.contains(&""));
+}
+
+#[test]
+fn project_config_parser_loads_backend_arch_flags_and_env() {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    let root = std::env::temp_dir().join(format!(
+        "cargo_oxide_config_test_{}_{}",
+        std::process::id(),
+        unique
+    ));
+    let cargo_dir = root.join(".cargo");
+    std::fs::create_dir_all(&cargo_dir).unwrap();
+    std::fs::write(
+        cargo_dir.join("cuda-oxide.toml"),
+        r#"
+backend = "../backend/librustc_codegen_cuda.so"
+default-arch = "sm_90"
+extra-rustflags = ["--cfg", "model=\"alpha beta\""]
+
+[env]
+MY_BUILD_FLAG = "configured"
+"#,
+    )
+    .unwrap();
+
+    let config = load_oxide_config(&root);
+    assert_eq!(
+        config.backend,
+        Some(cargo_dir.join("../backend/librustc_codegen_cuda.so"))
+    );
+    assert_eq!(config.default_arch.as_deref(), Some("sm_90"));
+    assert_eq!(config.extra_rustflags, ["--cfg", "model=\"alpha beta\""]);
+    assert_eq!(
+        config.env,
+        vec![("MY_BUILD_FLAG".to_string(), "configured".to_string())]
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn inspect_oxide_config_missing_is_informational() {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    let root = std::env::temp_dir().join(format!(
+        "cargo_oxide_config_missing_{}_{}",
+        std::process::id(),
+        unique
+    ));
+    std::fs::create_dir_all(&root).unwrap();
+    assert!(matches!(
+        inspect_oxide_config(&root),
+        OxideConfigInspection::Missing
+    ));
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn inspect_oxide_config_rejects_bad_toml_and_arch() {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    let root = std::env::temp_dir().join(format!(
+        "cargo_oxide_config_bad_{}_{}",
+        std::process::id(),
+        unique
+    ));
+    let cargo_dir = root.join(".cargo");
+    std::fs::create_dir_all(&cargo_dir).unwrap();
+    std::fs::write(cargo_dir.join("cuda-oxide.toml"), "default-arch = [\n").unwrap();
+    match inspect_oxide_config(&root) {
+        OxideConfigInspection::Invalid { errors, .. } => {
+            assert!(errors.iter().any(|e| e.contains("could not parse")));
+        }
+        other => panic!("expected Invalid, got {other:?}"),
+    }
+
+    std::fs::write(
+        cargo_dir.join("cuda-oxide.toml"),
+        "default-arch = \"sm_9x\"\n",
+    )
+    .unwrap();
+    match inspect_oxide_config(&root) {
+        OxideConfigInspection::Invalid { errors, .. } => {
+            assert!(errors.iter().any(|e| e.contains("default-arch")));
+        }
+        other => panic!("expected Invalid, got {other:?}"),
+    }
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+/// `default-arch` load-time validation must be exactly as permissive as
+/// the consumers: `parse_nvvm_arch` (NVVM path) accepts `sm_XX`,
+/// `compute_XX`, and bare `XX`, so none of those may fail the load.
+/// Non-`sm_XX` spellings only earn an advisory warning.
+#[test]
+fn default_arch_validation_matches_the_real_arch_parser() {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    let root = std::env::temp_dir().join(format!(
+        "cargo_oxide_config_arch_{}_{}",
+        std::process::id(),
+        unique
+    ));
+    let cargo_dir = root.join(".cargo");
+    std::fs::create_dir_all(&cargo_dir).unwrap();
+    let config_path = cargo_dir.join("cuda-oxide.toml");
+
+    for accepted in ["sm_80", "sm_90a", "sm_100f", "sm_120"] {
+        std::fs::write(&config_path, format!("default-arch = \"{accepted}\"\n")).unwrap();
+        match inspect_oxide_config(&root) {
+            OxideConfigInspection::Valid { warnings, .. } => {
+                assert!(warnings.is_empty(), "unexpected warnings for {accepted}");
+            }
+            other => panic!("expected {accepted} to be Valid, got {other:?}"),
+        }
+    }
+
+    // Spellings that genuinely work today (the NVVM path normalizes
+    // them) load fine but get the preferred-spelling advice.
+    for (works_with_warning, preferred) in [("compute_90", "sm_90"), ("90", "sm_90")] {
+        std::fs::write(
+            &config_path,
+            format!("default-arch = \"{works_with_warning}\"\n"),
+        )
+        .unwrap();
+        match inspect_oxide_config(&root) {
+            OxideConfigInspection::Valid { config, warnings } => {
+                assert_eq!(config.default_arch.as_deref(), Some(works_with_warning));
+                assert!(
+                    warnings.iter().any(|w| w.contains(preferred)),
+                    "expected a `{preferred}` spelling advisory for \
+                         {works_with_warning}, got {warnings:?}"
+                );
+            }
+            other => panic!("expected {works_with_warning} to be Valid, got {other:?}"),
+        }
+    }
+
+    for rejected in ["sm_9", "sm_90x", "hopper"] {
+        std::fs::write(&config_path, format!("default-arch = \"{rejected}\"\n")).unwrap();
+        match inspect_oxide_config(&root) {
+            OxideConfigInspection::Invalid { errors, .. } => {
+                assert!(
+                    errors.iter().any(|e| e.contains("default-arch")),
+                    "expected a default-arch error for {rejected}, got {errors:?}"
+                );
+            }
+            other => panic!("expected {rejected} to be Invalid, got {other:?}"),
+        }
+    }
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn inspect_oxide_config_warns_on_forbidden_env_keys() {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    let root = std::env::temp_dir().join(format!(
+        "cargo_oxide_config_warn_{}_{}",
+        std::process::id(),
+        unique
+    ));
+    let cargo_dir = root.join(".cargo");
+    std::fs::create_dir_all(&cargo_dir).unwrap();
+    std::fs::write(
+        cargo_dir.join("cuda-oxide.toml"),
+        r#"
+default-arch = "sm_90a"
+
+[env]
+RUSTFLAGS = "-C opt-level=3"
+CARGO_ENCODED_RUSTFLAGS = "legacy"
+MY_OK = "1"
+"#,
+    )
+    .unwrap();
+
+    match inspect_oxide_config(&root) {
+        OxideConfigInspection::Valid { config, warnings } => {
+            assert_eq!(config.default_arch.as_deref(), Some("sm_90a"));
+            assert!(
+                warnings
+                    .iter()
+                    .any(|w| w.contains("RUSTFLAGS") && w.contains("ignored"))
+            );
+            assert!(
+                warnings
+                    .iter()
+                    .any(|w| w.contains("CARGO_ENCODED_RUSTFLAGS") && w.contains("ignored"))
+            );
+        }
+        other => panic!("expected Valid with warnings, got {other:?}"),
+    }
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn doctor_survives_malformed_config_and_reports_the_failed_check() {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    let root = std::env::temp_dir().join(format!(
+        "cargo_oxide_doctor_config_bad_{}_{}",
+        std::process::id(),
+        unique
+    ));
+    let cargo_dir = root.join(".cargo");
+    std::fs::create_dir_all(&cargo_dir).unwrap();
+    std::fs::write(cargo_dir.join("cuda-oxide.toml"), "default-arch = [\n").unwrap();
+
+    // Passive context resolution must not exit: it degrades to defaults
+    // so the doctor scan can start at all.
+    assert_eq!(load_oxide_config_lenient(&root), OxideConfig::default());
+
+    // Doctor's own check re-inspects the file and fails.
+    let check = check_oxide_config(&root);
+    assert!(check.failed);
+    assert!(check.headline.starts_with('✗'), "{}", check.headline);
+    assert!(
+        check
+            .details
+            .iter()
+            .any(|line| line.contains("could not parse")),
+        "{:?}",
+        check.details
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn doctor_reports_env_rustflags_warning_without_failing_the_check() {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    let root = std::env::temp_dir().join(format!(
+        "cargo_oxide_doctor_config_warn_{}_{}",
+        std::process::id(),
+        unique
+    ));
+    let cargo_dir = root.join(".cargo");
+    std::fs::create_dir_all(&cargo_dir).unwrap();
+    std::fs::write(
+        cargo_dir.join("cuda-oxide.toml"),
+        "default-arch = \"sm_90a\"\n\n[env]\nRUSTFLAGS = \"-C opt-level=3\"\n",
+    )
+    .unwrap();
+
+    let check = check_oxide_config(&root);
+    assert!(!check.failed);
+    assert!(check.headline.contains("default-arch = sm_90a"));
+    assert!(
+        check
+            .details
+            .iter()
+            .any(|line| line.contains("RUSTFLAGS") && line.contains("ignored")),
+        "{:?}",
+        check.details
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn doctor_reports_missing_config_as_informational() {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    let root = std::env::temp_dir().join(format!(
+        "cargo_oxide_doctor_config_missing_{}_{}",
+        std::process::id(),
+        unique
+    ));
+    std::fs::create_dir_all(&root).unwrap();
+
+    let check = check_oxide_config(&root);
+    assert!(!check.failed);
+    assert_eq!(check.headline, "- not present (using defaults)");
+    assert!(check.details.is_empty());
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn passthrough_command_preserves_argv_and_cli_overrides_config_defaults() {
+    let config = OxideConfig {
+        extra_rustflags: vec!["--cfg".to_string(), "from_config".to_string()],
+        env: vec![
+            ("CARGO_TARGET_DIR".to_string(), "config-target".to_string()),
+            (
+                "CUDA_OXIDE_DEVICE_CODEGEN_CRATE".to_string(),
+                "config_owner".to_string(),
+            ),
+            ("CUDA_OXIDE_VERBOSE".to_string(), "configured".to_string()),
+        ],
+        ..OxideConfig::default()
+    };
+    let ctx = test_context(config);
+    let device_cfgs = vec!["model=\"alpha beta\"".to_string()];
+    let opts = CargoPassthroughOptions {
+        verbose: true,
+        emit_nvvm_ir: false,
+        arch: Some("sm_90"),
+        features: Some("wrapper_feature"),
+        cargo_target_dir: Some(Path::new("cli-target")),
+        device_codegen_crate: Some("gpu-kernels, math_gpu"),
+        device_cfgs: &device_cfgs,
+        no_fmad: false,
+        unchecked_indexing: false,
+        materialize_cubin: false,
+        device_debug: DeviceDebug::Off,
+    };
+    let cargo_args = vec![
+        "-p".to_string(),
+        "gpu-app".to_string(),
+        "--".to_string(),
+        "--nocapture".to_string(),
+    ];
+
+    let cmd =
+        passthrough_command_for_test(&ctx, CargoPassthroughSubcommand::Test, &opts, &cargo_args)
+            .unwrap();
+    assert_eq!(
+        cmd.get_args()
+            .map(|arg| arg.to_string_lossy().into_owned())
+            .collect::<Vec<_>>(),
+        [
+            "test",
+            "--features",
+            "wrapper_feature",
+            "-p",
+            "gpu-app",
+            "--",
+            "--nocapture",
+        ]
+    );
+    assert_eq!(
+        command_env(&cmd, "CARGO_TARGET_DIR").as_deref(),
+        Some("cli-target")
+    );
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_DEVICE_CODEGEN_CRATE").as_deref(),
+        Some("gpu_kernels,math_gpu")
+    );
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_TARGET").as_deref(),
+        Some("sm_90")
+    );
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_VERBOSE").as_deref(),
+        Some("1")
+    );
+
+    let encoded = command_env(&cmd, "CARGO_ENCODED_RUSTFLAGS").unwrap();
+    let flags = decoded_rustflags(&encoded);
+    assert!(
+        flags
+            .windows(2)
+            .any(|pair| pair == ["--cfg", "from_config"])
+    );
+    assert!(
+        flags
+            .windows(2)
+            .any(|pair| pair == ["--cfg", "model=\"alpha beta\""])
+    );
+    assert!(has_backend_identity_cfg(&flags));
+    assert!(!flags.iter().any(|flag| {
+        flag.contains("cuda_oxide_internal_codegen_env")
+            || flag.contains("cuda_oxide_internal_materializer_provenance")
+    }));
+    assert!(is_sha256(
+        &command_env(&cmd, CODEGEN_FINGERPRINT_ENV).unwrap()
+    ));
+    assert!(
+        cmd.get_envs()
+            .any(|(key, value)| key == OsStr::new("RUSTFLAGS") && value.is_none())
+    );
+}
+
+#[test]
+fn passthrough_command_accepts_empty_cargo_args() {
+    let ctx = test_context(OxideConfig::default());
+    let opts = CargoPassthroughOptions {
+        verbose: false,
+        emit_nvvm_ir: false,
+        arch: None,
+        features: None,
+        cargo_target_dir: None,
+        device_codegen_crate: None,
+        device_cfgs: &[],
+        no_fmad: false,
+        unchecked_indexing: false,
+        materialize_cubin: false,
+        device_debug: DeviceDebug::Off,
+    };
+
+    let cmd =
+        passthrough_command_for_test(&ctx, CargoPassthroughSubcommand::Test, &opts, &[]).unwrap();
+    assert_eq!(
+        cmd.get_args()
+            .map(|arg| arg.to_string_lossy().into_owned())
+            .collect::<Vec<_>>(),
+        ["test"]
+    );
+}
+
+#[test]
+fn architecture_and_output_mode_do_not_change_global_rustflags() {
+    let ctx = test_context(OxideConfig::default());
+    let base = CargoPassthroughOptions {
+        verbose: false,
+        emit_nvvm_ir: false,
+        arch: Some("sm_80"),
+        features: None,
+        cargo_target_dir: None,
+        device_codegen_crate: None,
+        device_cfgs: &[],
+        no_fmad: false,
+        unchecked_indexing: false,
+        materialize_cubin: false,
+        device_debug: DeviceDebug::Off,
+    };
+    let base_cmd =
+        passthrough_command_for_test(&ctx, CargoPassthroughSubcommand::Build, &base, &[]).unwrap();
+    let different_mode = CargoPassthroughOptions {
+        emit_nvvm_ir: true,
+        arch: Some("sm_90"),
+        ..base
+    };
+    let different_cmd = passthrough_command_for_test(
+        &ctx,
+        CargoPassthroughSubcommand::Build,
+        &different_mode,
+        &[],
+    )
+    .unwrap();
+
+    assert_eq!(
+        command_env(&base_cmd, "CARGO_ENCODED_RUSTFLAGS"),
+        command_env(&different_cmd, "CARGO_ENCODED_RUSTFLAGS"),
+        "architecture/output switches must not invalidate every dependency"
+    );
+    assert_ne!(
+        command_env(&base_cmd, CODEGEN_FINGERPRINT_ENV),
+        command_env(&different_cmd, CODEGEN_FINGERPRINT_ENV),
+        "device owners still need a distinct Cargo identity"
+    );
+}
+
+#[test]
+fn codegen_mode_changes_rebuild_only_the_tracked_device_owner() {
+    let root = unique_temp_dir("cargo_oxide_scoped_codegen_fingerprint");
+    let target = root.join("target");
+    for path in [
+        root.join("shared-dep/src"),
+        root.join("tracked-macro/src"),
+        root.join("device-owner/src"),
+        root.join("device-consumer/src"),
+    ] {
+        std::fs::create_dir_all(path).unwrap();
+    }
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"[workspace]
+resolver = "3"
+members = ["shared-dep", "tracked-macro", "device-owner", "device-consumer"]
+"#,
+    )
+    .unwrap();
+    std::fs::write(
+        root.join("shared-dep/Cargo.toml"),
+        r#"[package]
+name = "shared-dep"
+version = "0.0.0"
+edition = "2024"
+"#,
+    )
+    .unwrap();
+    std::fs::write(
+        root.join("shared-dep/src/lib.rs"),
+        "pub fn shared_value() -> u32 { 42 }\n",
+    )
+    .unwrap();
+    std::fs::write(
+        root.join("tracked-macro/Cargo.toml"),
+        r#"[package]
+name = "tracked-macro"
+version = "0.0.0"
+edition = "2024"
+
+[lib]
+proc-macro = true
+"#,
+    )
+    .unwrap();
+    std::fs::write(
+        root.join("tracked-macro/src/lib.rs"),
+        format!(
+            r#"#![feature(proc_macro_tracked_env)]
+extern crate proc_macro;
+
+#[proc_macro]
+pub fn track_codegen(_input: proc_macro::TokenStream) -> proc_macro::TokenStream {{
+    let _ = proc_macro::tracked::env_var({CODEGEN_FINGERPRINT_ENV:?});
+    let _ = proc_macro::tracked::env_var({MATERIALIZE_ENV:?});
+    let _ = proc_macro::tracked::env_var({EXPECTED_PROVENANCE_ENV:?});
+    "()".parse().unwrap()
+}}
+"#
+        ),
+    )
+    .unwrap();
+    std::fs::write(
+        root.join("device-owner/Cargo.toml"),
+        r#"[package]
+name = "device-owner"
+version = "0.0.0"
+edition = "2024"
+
+[dependencies]
+shared-dep = { path = "../shared-dep" }
+tracked-macro = { path = "../tracked-macro" }
+"#,
+    )
+    .unwrap();
+    std::fs::write(
+            root.join("device-owner/src/lib.rs"),
+            "const _: () = tracked_macro::track_codegen!();\npub fn device_value() -> u32 { shared_dep::shared_value() }\n",
+        )
+        .unwrap();
+    std::fs::write(
+        root.join("device-consumer/Cargo.toml"),
+        r#"[package]
+name = "device-consumer"
+version = "0.0.0"
+edition = "2024"
+
+[dependencies]
+device-owner = { path = "../device-owner" }
+"#,
+    )
+    .unwrap();
+    std::fs::write(
+        root.join("device-consumer/src/main.rs"),
+        "fn main() { assert_eq!(device_owner::device_value(), 42); }\n",
+    )
+    .unwrap();
+
+    let ctx = Context {
+        workspace_root: root.clone(),
+        codegen_crate: root.join("unused-codegen-source"),
+        examples_dir: root.join("unused-examples"),
+        backend_so: PathBuf::from("llvm"),
+        is_workspace: false,
+        config: OxideConfig::default(),
+    };
+    let base = CargoPassthroughOptions {
+        verbose: false,
+        emit_nvvm_ir: false,
+        arch: Some("sm_80"),
+        features: None,
+        cargo_target_dir: Some(&target),
+        device_codegen_crate: None,
+        device_cfgs: &[],
+        no_fmad: false,
+        unchecked_indexing: false,
+        materialize_cubin: false,
+        device_debug: DeviceDebug::Off,
+    };
+
+    let cold = cargo_artifact_freshness(&ctx, &base, None);
+    assert_eq!(cold.get("shared_dep"), Some(&false));
+    assert_eq!(cold.get("tracked_macro"), Some(&false));
+    assert_eq!(cold.get("device_owner"), Some(&false));
+    assert_eq!(cold.get("device-consumer"), Some(&false));
+
+    let warm = cargo_artifact_freshness(&ctx, &base, None);
+    assert_eq!(warm.get("shared_dep"), Some(&true));
+    assert_eq!(warm.get("tracked_macro"), Some(&true));
+    assert_eq!(warm.get("device_owner"), Some(&true));
+    assert_eq!(warm.get("device-consumer"), Some(&true));
+
+    let different_arch = CargoPassthroughOptions {
+        arch: Some("sm_90"),
+        ..base
+    };
+    let arch_switch = cargo_artifact_freshness(&ctx, &different_arch, None);
+    assert_eq!(arch_switch.get("shared_dep"), Some(&true));
+    assert_eq!(arch_switch.get("tracked_macro"), Some(&true));
+    assert_eq!(arch_switch.get("device_owner"), Some(&false));
+    assert_eq!(arch_switch.get("device-consumer"), Some(&false));
+
+    let different_output = CargoPassthroughOptions {
+        emit_nvvm_ir: true,
+        ..different_arch
+    };
+    let output_switch = cargo_artifact_freshness(&ctx, &different_output, None);
+    assert_eq!(output_switch.get("shared_dep"), Some(&true));
+    assert_eq!(output_switch.get("tracked_macro"), Some(&true));
+    assert_eq!(output_switch.get("device_owner"), Some(&false));
+    assert_eq!(output_switch.get("device-consumer"), Some(&false));
+
+    let repeated_output = cargo_artifact_freshness(&ctx, &different_output, None);
+    assert_eq!(repeated_output.get("shared_dep"), Some(&true));
+    assert_eq!(repeated_output.get("tracked_macro"), Some(&true));
+    assert_eq!(repeated_output.get("device_owner"), Some(&true));
+    assert_eq!(repeated_output.get("device-consumer"), Some(&true));
+
+    let provenance_switch = cargo_artifact_freshness(
+        &ctx,
+        &different_output,
+        Some("11d91fbe164094f6242d44103d0fb01968b96c6d8f48f124eac8fa73a307a657"),
+    );
+    assert_eq!(provenance_switch.get("shared_dep"), Some(&true));
+    assert_eq!(provenance_switch.get("tracked_macro"), Some(&true));
+    assert_eq!(provenance_switch.get("device_owner"), Some(&false));
+    assert_eq!(provenance_switch.get("device-consumer"), Some(&false));
+
+    let changed_provenance = cargo_artifact_freshness(
+        &ctx,
+        &different_output,
+        Some("5b11618c2e44027877d0cd4d0cfd10afed5ef262876791e483ec58f4c5569139"),
+    );
+    assert_eq!(changed_provenance.get("shared_dep"), Some(&true));
+    assert_eq!(changed_provenance.get("tracked_macro"), Some(&true));
+    assert_eq!(changed_provenance.get("device_owner"), Some(&false));
+    assert_eq!(changed_provenance.get("device-consumer"), Some(&false));
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn owner_filter_resolution_is_normalized_and_has_explicit_precedence() {
+    assert_eq!(
+        resolve_device_codegen_crates(None, None, Some("gpu-kernels, math_gpu"))
+            .unwrap()
+            .as_deref(),
+        Some("gpu_kernels,math_gpu"),
+    );
+    assert_eq!(
+        resolve_device_codegen_crates(None, Some("parent-owner"), Some("config-owner"))
+            .unwrap()
+            .as_deref(),
+        Some("parent_owner"),
+    );
+    assert!(
+        resolve_device_codegen_crates(Some(""), Some("parent-owner"), Some("config-owner"))
+            .is_err()
+    );
+}
+
+#[test]
+fn passthrough_fingerprint_tracks_output_affecting_settings() {
+    let ctx = test_context(OxideConfig::default());
+    let base = CargoPassthroughOptions {
+        verbose: false,
+        emit_nvvm_ir: false,
+        arch: Some("sm_80"),
+        features: None,
+        cargo_target_dir: None,
+        device_codegen_crate: None,
+        device_cfgs: &[],
+        no_fmad: false,
+        unchecked_indexing: false,
+        materialize_cubin: false,
+        device_debug: DeviceDebug::Off,
+    };
+    let inherited_env = BTreeMap::new();
+    let base_hash = passthrough_codegen_fingerprint_with_env(
+        &ctx,
+        &base,
+        None,
+        Some("sm_80"),
+        &MaterializationMode::default(),
+        &inherited_env,
+    );
+
+    let arch = CargoPassthroughOptions {
+        arch: Some("sm_90"),
+        ..base
+    };
+    let emit = CargoPassthroughOptions {
+        emit_nvvm_ir: true,
+        ..base
+    };
+    let no_fmad = CargoPassthroughOptions {
+        no_fmad: true,
+        ..base
+    };
+    let unchecked_indexing = CargoPassthroughOptions {
+        unchecked_indexing: true,
+        ..base
+    };
+    let configured_ptx = test_context(OxideConfig {
+        env: vec![(
+            "CUDA_OXIDE_PTX_DIR".to_string(),
+            "configured-ptx".to_string(),
+        )],
+        ..OxideConfig::default()
+    });
+
+    assert_ne!(
+        base_hash,
+        passthrough_codegen_fingerprint_with_env(
+            &ctx,
+            &arch,
+            None,
+            Some("sm_90"),
+            &MaterializationMode::default(),
+            &inherited_env,
+        )
+    );
+    assert_ne!(
+        base_hash,
+        passthrough_codegen_fingerprint_with_env(
+            &ctx,
+            &emit,
+            None,
+            Some("sm_80"),
+            &MaterializationMode::default(),
+            &inherited_env,
+        )
+    );
+    assert_ne!(
+        base_hash,
+        passthrough_codegen_fingerprint_with_env(
+            &ctx,
+            &no_fmad,
+            None,
+            Some("sm_80"),
+            &MaterializationMode::default(),
+            &inherited_env,
+        )
+    );
+    assert_ne!(
+        base_hash,
+        passthrough_codegen_fingerprint_with_env(
+            &ctx,
+            &unchecked_indexing,
+            None,
+            Some("sm_80"),
+            &MaterializationMode::default(),
+            &inherited_env,
+        )
+    );
+    assert_ne!(
+        base_hash,
+        passthrough_codegen_fingerprint_with_env(
+            &ctx,
+            &base,
+            Some("gpu_kernel"),
+            Some("sm_80"),
+            &MaterializationMode::default(),
+            &inherited_env,
+        )
+    );
+    assert_ne!(
+        base_hash,
+        passthrough_codegen_fingerprint_with_env(
+            &configured_ptx,
+            &base,
+            None,
+            Some("sm_80"),
+            &MaterializationMode::default(),
+            &inherited_env,
+        )
+    );
+    let materialized = MaterializationMode {
+        prepared: Some(PreparedMaterialization {
+            provenance_sha256_hex: "ab".repeat(32),
+            tool_identity_handshake_json: "{\"version\":1}".to_string(),
+        }),
+    };
+    assert_ne!(
+        base_hash,
+        passthrough_codegen_fingerprint_with_env(
+            &ctx,
+            &base,
+            None,
+            Some("sm_80"),
+            &materialized,
+            &inherited_env,
+        ),
+        "exact CUDA-tool provenance must change Cargo's rustc fingerprint"
+    );
+}
+
+#[test]
+fn passthrough_fingerprint_tracks_non_unicode_presence_switch_bytes() {
+    let ctx = test_context(OxideConfig::default());
+    let opts = CargoPassthroughOptions {
+        verbose: false,
+        emit_nvvm_ir: false,
+        arch: Some("sm_80"),
+        features: None,
+        cargo_target_dir: None,
+        device_codegen_crate: None,
+        device_cfgs: &[],
+        no_fmad: false,
+        unchecked_indexing: false,
+        materialize_cubin: false,
+        device_debug: DeviceDebug::Off,
+    };
+    let fingerprint = |inherited_env: &BTreeMap<String, Vec<u8>>| {
+        passthrough_codegen_fingerprint_with_env(
+            &ctx,
+            &opts,
+            None,
+            Some("sm_80"),
+            &MaterializationMode::default(),
+            inherited_env,
+        )
+    };
+    let absent = BTreeMap::new();
+    let first = BTreeMap::from([("CUDA_OXIDE_NO_FMA".to_string(), vec![0xff])]);
+    let second = BTreeMap::from([("CUDA_OXIDE_NO_FMA".to_string(), vec![0xfe])]);
+
+    assert_ne!(fingerprint(&absent), fingerprint(&first));
+    assert_ne!(fingerprint(&first), fingerprint(&second));
+}
+
+#[test]
+fn global_backend_identity_tracks_rebuild_at_same_path() {
+    let unique = std::time::SystemTime::now()
+        .duration_since(std::time::UNIX_EPOCH)
+        .expect("system time before unix epoch")
+        .as_nanos();
+    let root = std::env::temp_dir().join(format!(
+        "cargo_oxide_backend_fingerprint_{}_{}",
+        std::process::id(),
+        unique
+    ));
+    std::fs::create_dir_all(&root).unwrap();
+    let backend = root.join("librustc_codegen_cuda.so");
+    std::fs::write(&backend, b"first").unwrap();
+    let original = std::fs::metadata(&backend).unwrap();
+    let original_modified = original.modified().unwrap();
+
+    let mut ctx = test_context(OxideConfig::default());
+    ctx.backend_so = backend.clone();
+    let fingerprint = "42".repeat(32);
+    let mut before_cmd = Command::new("cargo");
+    apply_codegen_configuration(
+        &mut before_cmd,
+        &ctx,
+        CodegenProfilePolicy::ReleaseLike,
+        &[],
+        &fingerprint,
+    )
+    .unwrap();
+    let before = command_env(&before_cmd, "CARGO_ENCODED_RUSTFLAGS").unwrap();
+    // Preserve the weak metadata identity that used to be fingerprinted:
+    // only the bytes differ.
+    std::fs::write(&backend, b"other").unwrap();
+    std::fs::File::options()
+        .write(true)
+        .open(&backend)
+        .unwrap()
+        .set_times(std::fs::FileTimes::new().set_modified(original_modified))
+        .unwrap();
+    let replacement = std::fs::metadata(&backend).unwrap();
+    assert_eq!(replacement.len(), original.len());
+    assert_eq!(replacement.modified().unwrap(), original_modified);
+    let mut after_cmd = Command::new("cargo");
+    apply_codegen_configuration(
+        &mut after_cmd,
+        &ctx,
+        CodegenProfilePolicy::ReleaseLike,
+        &[],
+        &fingerprint,
+    )
+    .unwrap();
+    let after = command_env(&after_cmd, "CARGO_ENCODED_RUSTFLAGS").unwrap();
+
+    assert_ne!(before, after);
+    assert_eq!(
+        command_env(&before_cmd, CODEGEN_FINGERPRINT_ENV),
+        command_env(&after_cmd, CODEGEN_FINGERPRINT_ENV)
+    );
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn owner_filter_rejects_empty_or_invalid_entries() {
+    assert_eq!(
+        normalize_device_codegen_crates("gpu-kernels, math_gpu").unwrap(),
+        "gpu_kernels,math_gpu"
+    );
+    assert!(normalize_device_codegen_crates("").is_err());
+    assert!(normalize_device_codegen_crates("   ").is_err());
+    assert!(normalize_device_codegen_crates("gpu,").is_err());
+    assert!(normalize_device_codegen_crates("gpu,not a crate").is_err());
+}
+
+#[test]
+fn internal_ptx_directory_overrides_project_env_default() {
+    let ctx = test_context(OxideConfig {
+        env: vec![(
+            "CUDA_OXIDE_PTX_DIR".to_string(),
+            "configured-ptx".to_string(),
+        )],
+        ..OxideConfig::default()
+    });
+    let mut cmd = Command::new("cargo");
+    apply_common_codegen_env(&mut cmd, &ctx, false, false, false, DeviceDebug::Off);
+    cmd.env("CUDA_OXIDE_PTX_DIR", "internal-ptx");
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_PTX_DIR").as_deref(),
+        Some("internal-ptx")
+    );
+}
+
+#[test]
+fn nvvm_arch_normalizes_all_accepted_forms() {
+    // `sm_XX` is the form `--arch` and the rest of cargo-oxide use.
+    assert_eq!(parse_nvvm_arch("sm_120").unwrap().compute(), "compute_120");
+    assert_eq!(parse_nvvm_arch("sm_90").unwrap().compute(), "compute_90");
+    // `compute_XX` passes through unchanged.
+    assert_eq!(
+        parse_nvvm_arch("compute_100").unwrap().compute(),
+        "compute_100"
+    );
+    // A bare capability is accepted too.
+    assert_eq!(parse_nvvm_arch("120").unwrap().compute(), "compute_120");
+    assert!(parse_nvvm_arch("sm_90x").is_err());
+}
+
+#[test]
+fn emit_ltoir_preserves_fma_and_debug_policy_for_libnvvm() {
+    let arch = parse_nvvm_arch("sm_90").unwrap();
+    for (artifact_debug, finalizer_debug) in [
+        (
+            oxide_artifacts::ArtifactDebugPolicy::None,
+            cuda_artifact_finalizer::DebugPolicy::None,
+        ),
+        (
+            oxide_artifacts::ArtifactDebugPolicy::LineTables,
+            cuda_artifact_finalizer::DebugPolicy::LineTables,
+        ),
+        (
+            oxide_artifacts::ArtifactDebugPolicy::Full,
+            cuda_artifact_finalizer::DebugPolicy::Full,
+        ),
+    ] {
+        let artifact_options = oxide_artifacts::ArtifactCompileOptions::new()
+            .with_fma_contraction(false)
+            .with_debug_policy(artifact_debug);
+        let finalizer_options = finalization_options_from_artifact(&arch, artifact_options);
+
+        assert_eq!(finalizer_options.target(), &arch);
+        assert!(!finalizer_options.allow_fma_contraction());
+        assert_eq!(finalizer_options.debug_policy(), finalizer_debug);
+    }
+}
+
+#[test]
+fn apply_output_mode_sets_target_for_arch_override() {
+    let mut cmd = Command::new("cargo");
+
+    apply_output_mode(
+        &mut cmd,
+        false,
+        Some("sm_120"),
+        &MaterializationMode::default(),
+    );
+
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_TARGET").as_deref(),
+        Some("sm_120")
+    );
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR"), None);
+}
+
+#[test]
+fn apply_output_mode_sets_nvvm_ir_flag_and_target() {
+    let mut cmd = Command::new("cargo");
+
+    apply_output_mode(
+        &mut cmd,
+        true,
+        Some("sm_100a"),
+        &MaterializationMode::default(),
+    );
+
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_TARGET").as_deref(),
+        Some("sm_100a")
+    );
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR").as_deref(),
+        Some("1")
+    );
+}
+
+#[test]
+fn materialization_forces_nvvm_ir_and_exact_provenance_handshake() {
+    let mut cmd = Command::new("cargo");
+    let materialization = MaterializationMode {
+        prepared: Some(PreparedMaterialization {
+            provenance_sha256_hex: "42".repeat(32),
+            tool_identity_handshake_json: "{\"version\":1}".to_string(),
+        }),
+    };
+
+    apply_output_mode(&mut cmd, false, Some("sm_90"), &materialization);
+
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR").as_deref(),
+        Some("1")
+    );
+    assert_eq!(command_env(&cmd, MATERIALIZE_ENV).as_deref(), Some("1"));
+    assert_eq!(
+        command_env(&cmd, MATERIALIZER_HANDSHAKE_ENV).as_deref(),
+        Some("{\"version\":1}")
+    );
+    assert_eq!(
+        command_env(&cmd, EXPECTED_PROVENANCE_ENV).as_deref(),
+        Some("4242424242424242424242424242424242424242424242424242424242424242")
+    );
+}
+
+#[test]
+fn apply_output_mode_leaves_auto_detect_ptx_unset() {
+    let mut cmd = Command::new("cargo");
+
+    apply_output_mode(&mut cmd, false, None, &MaterializationMode::default());
+
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_TARGET"), None);
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR"), None);
+}
+
+#[test]
+fn apply_device_arch_hint_sets_hint_when_no_explicit_arch() {
+    let mut cmd = Command::new("cargo");
+
+    apply_device_arch_hint(&mut cmd, None, Some("sm_120a"));
+
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_DEVICE_ARCH").as_deref(),
+        Some("sm_120a")
+    );
+    // The hint must never masquerade as the hard override.
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_TARGET"), None);
+}
+
+#[test]
+fn apply_device_arch_hint_skipped_when_arch_explicit() {
+    // An explicit --arch already went to CUDA_OXIDE_TARGET; don't also
+    // emit a competing device hint.
+    let mut cmd = Command::new("cargo");
+
+    apply_device_arch_hint(&mut cmd, Some("sm_90"), Some("sm_120a"));
+
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_DEVICE_ARCH"), None);
+}
+
+#[test]
+fn apply_device_arch_hint_noop_without_detection() {
+    let mut cmd = Command::new("cargo");
+
+    apply_device_arch_hint(&mut cmd, None, None);
+
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_DEVICE_ARCH"), None);
+}
+
+#[test]
+fn debug_output_mode_forwards_detected_gpu_hint() {
+    let mut cmd = Command::new("cargo");
+
+    apply_output_mode(&mut cmd, false, None, &MaterializationMode::default());
+    apply_device_arch_hint(&mut cmd, None, Some("sm_120a"));
+
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_DEVICE_ARCH").as_deref(),
+        Some("sm_120a")
+    );
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_TARGET"), None);
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR"), None);
+}
+
+#[test]
+fn debug_output_mode_honors_explicit_arch_override() {
+    let mut cmd = Command::new("cargo");
+
+    apply_output_mode(
+        &mut cmd,
+        false,
+        Some("sm_90"),
+        &MaterializationMode::default(),
+    );
+    apply_device_arch_hint(&mut cmd, Some("sm_90"), Some("sm_120a"));
+
+    assert_eq!(
+        command_env(&cmd, "CUDA_OXIDE_TARGET").as_deref(),
+        Some("sm_90")
+    );
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_DEVICE_ARCH"), None);
+    assert_eq!(command_env(&cmd, "CUDA_OXIDE_EMIT_NVVM_IR"), None);
+}
+
+#[test]
+fn format_sm_arch_uses_cuda_target_spelling() {
+    // cc < 9.0 — no arch-specific target exists in the PTX ISA, so we
+    // emit the plain `sm_XY` form. Confirms we do not produce false
+    // positives like `sm_75a` / `sm_80a` / `sm_89a`.
+    assert_eq!(format_sm_arch((7, 0)), "sm_70");
+    assert_eq!(format_sm_arch((7, 5)), "sm_75");
+    assert_eq!(format_sm_arch((8, 0)), "sm_80");
+    assert_eq!(format_sm_arch((8, 6)), "sm_86");
+    assert_eq!(format_sm_arch((8, 9)), "sm_89");
+
+    // cc ≥ 9.0 — every chip that reports this CC is an arch-specific
+    // (`a`) variant. Auto-detect emits the `a` form so the codegen
+    // backend can lower WGMMA / tcgen05 / TMA-multicast / cta_group
+    // intrinsics without falling through to a plain target that ptxas
+    // would reject. Confirms we do not produce false negatives.
+    assert_eq!(format_sm_arch((9, 0)), "sm_90a"); // Hopper (H100/H200)
+    assert_eq!(format_sm_arch((10, 0)), "sm_100a"); // Blackwell DC
+    assert_eq!(format_sm_arch((10, 1)), "sm_101a");
+    assert_eq!(format_sm_arch((10, 3)), "sm_103a");
+    assert_eq!(format_sm_arch((12, 0)), "sm_120a"); // consumer Blackwell
+}
+
+#[test]
+fn parse_compute_cap_accepts_real_nvidia_smi_output() {
+    assert_eq!(parse_compute_cap("12.0\n"), Some((12, 0)));
+    assert_eq!(parse_compute_cap("7.5\n"), Some((7, 5)));
+    assert_eq!(parse_compute_cap("10.3"), Some((10, 3)));
+    // End-to-end with format_sm_arch: the values the backend sees.
+    assert_eq!(
+        format_sm_arch(parse_compute_cap("12.0\n").unwrap()),
+        "sm_120a"
+    );
+    assert_eq!(format_sm_arch(parse_compute_cap("7.5\n").unwrap()), "sm_75");
+}
+
+#[test]
+fn parse_compute_cap_takes_first_gpu_on_multi_gpu_machines() {
+    assert_eq!(parse_compute_cap("9.0\n12.0\n"), Some((9, 0)));
+}
+
+#[test]
+fn parse_gpu_name_cap_and_driver_splits_on_last_two_commas() {
+    assert_eq!(
+        parse_gpu_name_cap_and_driver("NVIDIA GeForce RTX 5090, 12.0, 580.65.06\n"),
+        Some((
+            "NVIDIA GeForce RTX 5090".to_string(),
+            (12, 0),
+            "580.65.06".to_string()
+        ))
+    );
+    // Failure banner: no comma-separated cc/driver fields.
+    assert_eq!(
+        parse_gpu_name_cap_and_driver("NVIDIA-SMI has failed.\n"),
+        None
+    );
+    assert_eq!(parse_gpu_name_cap_and_driver(""), None);
+}
+
+#[test]
+fn cuda_toolkit_root_prefers_toolkit_path_then_home_then_default() {
+    let toolkit_and_home = cuda_toolkit_root(|var| match var {
+        "CUDA_TOOLKIT_PATH" => Some("/cuda/toolkit".to_string()),
+        "CUDA_HOME" => Some("/cuda/home".to_string()),
+        _ => None,
+    });
+    assert_eq!(toolkit_and_home, "/cuda/toolkit");
+
+    let home_only = cuda_toolkit_root(|var| (var == "CUDA_HOME").then(|| "/cuda/home".to_string()));
+    assert_eq!(home_only, "/cuda/home");
+
+    let empty_toolkit_path = cuda_toolkit_root(|var| match var {
+        "CUDA_TOOLKIT_PATH" => Some("  ".to_string()),
+        "CUDA_HOME" => Some("/cuda/home".to_string()),
+        _ => None,
+    });
+    assert_eq!(empty_toolkit_path, "/cuda/home");
+
+    assert_eq!(cuda_toolkit_root(|_| None), "/usr/local/cuda");
+}
+
+#[test]
+fn cuda_header_candidates_cover_standard_and_redistributable_layouts() {
+    // Standard install layout first, then the matching targets/ layout.
+    assert_eq!(
+        cuda_header_candidates("/usr/local/cuda", None, "x86_64", "linux"),
+        vec![
+            PathBuf::from("/usr/local/cuda/include/cuda.h"),
+            PathBuf::from("/usr/local/cuda/targets/x86_64-linux/include/cuda.h"),
+        ]
+    );
+    // aarch64 Linux is ambiguous between servers (sbsa-linux) and Tegra
+    // (aarch64-linux), so both are probed, servers first.
+    assert_eq!(
+        cuda_header_candidates("/opt/ctk", None, "aarch64", "linux"),
+        vec![
+            PathBuf::from("/opt/ctk/include/cuda.h"),
+            PathBuf::from("/opt/ctk/targets/sbsa-linux/include/cuda.h"),
+            PathBuf::from("/opt/ctk/targets/aarch64-linux/include/cuda.h"),
+        ]
+    );
+    // Unknown host arch or non-Linux OS: only the standard layout.
+    assert_eq!(
+        cuda_header_candidates("/opt/ctk", None, "riscv64", "linux"),
+        vec![PathBuf::from("/opt/ctk/include/cuda.h")]
+    );
+    assert_eq!(
+        cuda_header_candidates("/opt/ctk", None, "aarch64", "macos"),
+        vec![PathBuf::from("/opt/ctk/include/cuda.h")]
+    );
+    // CUDA_TOOLKIT_TARGET_DIR replaces the table with one directory;
+    // a blank value means "unset".
+    assert_eq!(
+        cuda_header_candidates("/opt/ctk", Some("aarch64-linux"), "aarch64", "linux"),
+        vec![
+            PathBuf::from("/opt/ctk/include/cuda.h"),
+            PathBuf::from("/opt/ctk/targets/aarch64-linux/include/cuda.h"),
+        ]
+    );
+    assert_eq!(
+        cuda_header_candidates("/opt/ctk", Some("  "), "x86_64", "linux"),
+        vec![
+            PathBuf::from("/opt/ctk/include/cuda.h"),
+            PathBuf::from("/opt/ctk/targets/x86_64-linux/include/cuda.h"),
+        ]
+    );
+}
+
+#[test]
+fn parse_rust_toolchain_toml_reads_channel_and_components() {
+    let pin = parse_rust_toolchain_toml(
+        r#"[toolchain]
+channel = "nightly-2026-04-03"
+components = ["rust-src", "rustc-dev", "llvm-tools"]
+"#,
+    )
+    .expect("pin should parse");
+    assert_eq!(pin.channel, "nightly-2026-04-03");
+    assert_eq!(
+        pin.components,
+        vec![
+            "rust-src".to_string(),
+            "rustc-dev".to_string(),
+            "llvm-tools".to_string()
+        ]
+    );
+}
+
+#[test]
+fn parse_rust_toolchain_toml_rejects_missing_channel() {
+    let error = parse_rust_toolchain_toml("[toolchain]\ncomponents = [\"rust-src\"]\n")
+        .expect_err("channel is required");
+    assert!(error.contains("channel"), "{error}");
+}
+
+#[test]
+fn active_toolchain_matches_channel_accepts_target_triple_suffix() {
+    assert!(active_toolchain_matches_channel(
+        "nightly-2026-04-03-aarch64-apple-darwin (default)",
+        "nightly-2026-04-03"
+    ));
+    assert!(active_toolchain_matches_channel(
+        "nightly-2026-04-03",
+        "nightly-2026-04-03"
+    ));
+    assert!(!active_toolchain_matches_channel(
+        "nightly-2026-01-01-x86_64-unknown-linux-gnu (default)",
+        "nightly-2026-04-03"
+    ));
+}
+
+#[test]
+fn active_toolchain_matches_channel_accepts_rustup_128_and_129_formats() {
+    // rustup 1.29 single-line form with an override annotation, as
+    // observed verbatim on a workspace with rust-toolchain.toml.
+    assert!(active_toolchain_matches_channel(
+        "nightly-2026-04-03-x86_64-unknown-linux-gnu (overridden by \
+             '/home/user/cuda-oxide/rust-toolchain.toml')",
+        "nightly-2026-04-03"
+    ));
+    // rustup 1.28 two-line form: bare name, then the reason line.
+    assert!(active_toolchain_matches_channel(
+        "nightly-2026-04-03-x86_64-unknown-linux-gnu\nactive because: \
+             overridden by '/home/user/cuda-oxide/rust-toolchain.toml'",
+        "nightly-2026-04-03"
+    ));
+    // A mismatched pin must not be rescued by later lines.
+    assert!(!active_toolchain_matches_channel(
+        "stable-x86_64-unknown-linux-gnu\nactive because: default",
+        "nightly-2026-04-03"
+    ));
+}
+
+#[test]
+fn plan_update_selects_advise_setup_or_cache_refresh() {
+    assert_eq!(plan_update(true, false), UpdatePlan::AdviseSetup);
+    assert_eq!(plan_update(true, true), UpdatePlan::RunSetup);
+    assert_eq!(plan_update(false, false), UpdatePlan::RefreshCache);
+    assert_eq!(plan_update(false, true), UpdatePlan::RefreshCache);
+}
+
+/// A `.cargo/cuda-oxide.toml` backend pin outranks the shared cache, so
+/// `update` must refuse just like it does for `CUDA_OXIDE_BACKEND`.
+#[test]
+fn update_refuses_when_the_config_pins_a_backend() {
+    let pinned = test_context(OxideConfig {
+        backend: Some(PathBuf::from("/tmp/pinned-backend.so")),
+        ..OxideConfig::default()
+    });
+    // `None` stands in for an unset ambient `CUDA_OXIDE_BACKEND`. Reading
+    // the real one would let an exported value produce the env refusal for
+    // both inputs, including the unpinned case asserted to be `None`.
+    let refusal =
+        update_pin_refusal_with_env(&pinned, None).expect("config pin must refuse update");
+    assert!(refusal.contains("pins the backend"), "{refusal}");
+    assert!(refusal.contains("/tmp/pinned-backend.so"), "{refusal}");
+
+    let unpinned = test_context(OxideConfig::default());
+    assert_eq!(update_pin_refusal_with_env(&unpinned, None), None);
+
+    // The env var outranks the project pin: set, it refuses even unpinned.
+    let from_env = update_pin_refusal_with_env(&unpinned, Some("/tmp/env-backend.so".into()))
+        .expect("exported CUDA_OXIDE_BACKEND must refuse update");
+    assert!(from_env.contains("CUDA_OXIDE_BACKEND is set"), "{from_env}");
+}
+
+#[test]
+fn doctor_verified_components_unions_pin_list_with_required_floor() {
+    // Pin lists everything: order preserved, no duplicates appended.
+    let pin = RustToolchainPin {
+        channel: "nightly-2026-04-03".to_string(),
+        components: vec![
+            "rust-src".to_string(),
+            "rustc-dev".to_string(),
+            "rust-analyzer".to_string(),
+            "clippy".to_string(),
+            "llvm-tools".to_string(),
+        ],
+    };
+    assert_eq!(
+        doctor_verified_components(&pin),
+        vec![
+            "rust-src",
+            "rustc-dev",
+            "rust-analyzer",
+            "clippy",
+            "llvm-tools"
+        ]
+    );
+
+    // A trimmed pin still gets the hard floor appended.
+    let trimmed = RustToolchainPin {
+        channel: "nightly-2026-04-03".to_string(),
+        components: vec!["clippy".to_string()],
+    };
+    assert_eq!(
+        doctor_verified_components(&trimmed),
+        vec!["clippy", "rust-src", "rustc-dev", "llvm-tools"]
+    );
+}
+
+#[test]
+fn missing_rustup_components_detects_host_triple_suffixes() {
+    let installed = "\
+rust-src-aarch64-apple-darwin
+clippy-aarch64-apple-darwin
+";
+    assert_eq!(
+        missing_rustup_components(installed, &["rust-src", "llvm-tools"]),
+        vec!["llvm-tools".to_string()]
+    );
+    assert!(missing_rustup_components(installed, &["rust-src"]).is_empty());
+}
+
+#[test]
+fn parse_compute_cap_rejects_failure_banners_and_garbage() {
+    // nvidia-smi prints failure text to STDOUT, not stderr.
+    assert_eq!(
+        parse_compute_cap(
+            "NVIDIA-SMI has failed because it couldn't communicate \
+                 with the NVIDIA driver.\n"
+        ),
+        None
+    );
+    assert_eq!(parse_compute_cap(""), None);
+    assert_eq!(parse_compute_cap("\n"), None);
+    assert_eq!(parse_compute_cap("N/A\n"), None);
+    assert_eq!(parse_compute_cap("12\n"), None);
+    assert_eq!(parse_compute_cap("12.\n"), None);
+    assert_eq!(parse_compute_cap(".5\n"), None);
+    assert_eq!(parse_compute_cap("12.0.1\n"), None);
+}
+
+// All three skip cases inject the `CUDA_OXIDE_TARGET` probe rather than
+// reading the ambient one, so each asserts the slot it names instead of
+// passing because the developer happens to have the variable exported.
+
+#[test]
+fn detect_run_target_arch_skips_when_arch_explicit() {
+    // --arch wins; never query the GPU.
+    assert_eq!(
+        detect_run_target_arch_with_env(Some("sm_120"), false, false),
+        None
+    );
+}
+
+#[test]
+fn detect_run_target_arch_skips_when_emit_nvvm_ir() {
+    // NVVM IR mode requires explicit --arch; auto-detect must not run.
+    assert_eq!(detect_run_target_arch_with_env(None, true, false), None);
+}
+
+#[test]
+fn detect_run_target_arch_skips_when_env_target_set() {
+    // Slot 2 wins; never query the GPU. Injected rather than exported:
+    // `set_var` is a data race against the `vars_os` reads the fingerprint
+    // helpers perform on other test threads, which the cargo test harness
+    // runs concurrently by default.
+    assert_eq!(detect_run_target_arch_with_env(None, false, true), None);
+}
+
+fn write_list_example(
+    examples_dir: &Path,
+    name: &str,
+    manifest_description: Option<&str>,
+    readme: Option<&str>,
+) {
+    let example_dir = examples_dir.join(name);
+    std::fs::create_dir_all(&example_dir).unwrap();
+
+    let description = manifest_description
+        .map(|value| format!("description = {value:?}\n"))
+        .unwrap_or_default();
+
+    std::fs::write(
+        example_dir.join("Cargo.toml"),
+        format!(
+            "[package]\nname = {name:?}\nversion = \"0.1.0\"\nedition = \"2024\"\n{description}"
+        ),
+    )
+    .unwrap();
+
+    if let Some(readme) = readme {
+        std::fs::write(example_dir.join("README.md"), readme).unwrap();
+    }
+}
+
+#[test]
+fn readme_parser_extracts_title_description_and_requirements() {
+    let parsed = parse_example_readme(
+        "vecadd",
+        r#"
+# vecadd
+
+## Vector Addition
+
+Adds two vectors using one CUDA thread per element.
+
+## Hardware Requirements
+
+- **Minimum GPU**: sm_70+
+- **CUDA Toolkit**: 12.x+
+"#,
+    );
+
+    assert_eq!(parsed.title.as_deref(), Some("Vector Addition"));
+    assert_eq!(
+        parsed.description.as_deref(),
+        Some("Adds two vectors using one CUDA thread per element.")
+    );
+    assert_eq!(
+        parsed.requirements,
+        ["Minimum GPU: sm_70+", "CUDA Toolkit: 12.x+"]
+    );
+}
+
+#[test]
+fn readme_parser_does_not_use_run_as_title() {
+    let parsed = parse_example_readme(
+        "cuda_module_nested",
+        r#"
+# cuda_module_nested
+
+## Run
+
+Expected output:
+
+```text
+PASS
+```
+
+"#,
+    );
+
+    assert_eq!(parsed.title.as_deref(), Some("cuda_module_nested"));
+    assert_eq!(parsed.description, None);
+}
+
+#[test]
+fn readme_parser_does_not_scan_later_headings_for_title() {
+    let parsed = parse_example_readme(
+        "example",
+        r#"
+
+# example
+
+Introductory description.
+
+## Build
+
+Build instructions.
+
+## Advanced Implementation Details
+
+Internal details.
+"#,
+    );
+
+    assert_eq!(parsed.title.as_deref(), Some("example"));
+    assert_eq!(
+        parsed.description.as_deref(),
+        Some("Introductory description.")
+    );
+}
+
+#[test]
+fn readme_parser_stops_description_at_next_heading() {
+    let parsed = parse_example_readme(
+        "vecadd",
+        r#"
+
+# vecadd
+
+## Vector Addition
+
+Adds two vectors on the GPU.
+
+## Run
+
+Run the example with cargo oxide.
+"#,
+    );
+
+    assert_eq!(parsed.title.as_deref(), Some("Vector Addition"));
+    assert_eq!(
+        parsed.description.as_deref(),
+        Some("Adds two vectors on the GPU.")
+    );
+}
+
+#[test]
+fn requirement_parser_joins_wrapped_list_items() {
+    let parsed = parse_example_readme(
+        "example",
+        r#"
+
+# example
+
+## Requirements
+
+* CUDA Toolkit 13.1+ with nvcc and tileiras available. This example
+  also requires the CUDA development libraries.
+* Blackwell GPU with sm_100+ support.
+  "#,
+    );
+
+    assert_eq!(
+        parsed.requirements,
+        [
+            "CUDA Toolkit 13.1+ with nvcc and tileiras available. This example also requires the CUDA development libraries.",
+            "Blackwell GPU with sm_100+ support.",
+        ]
+    );
+}
+
+#[test]
+fn requirement_parser_does_not_absorb_paragraph_after_blank_line() {
+    // Modeled on the cpp_consumes_rust_device README: a bullet list under
+    // the requirements heading, then a blank line, then a follow-up
+    // paragraph and a code fence. The paragraph is a new paragraph, not a
+    // wrapped continuation of the last bullet.
+    let parsed = parse_example_readme(
+        "cpp_consumes_rust_device",
+        r#"
+# cpp_consumes_rust_device
+
+## Prerequisites
+
+- CUDA Toolkit (nvcc, libNVVM, nvJitLink)
+- Blackwell+ GPU (sm_100+) — LTOIR requires NVVM 20 dialect
+
+If your default host compiler is newer than the CUDA Toolkit supports, set
+`NVCC_CCBIN` or `CUDAHOSTCXX` before running the example:
+
+```bash
+NVCC_CCBIN=/usr/bin/g++-15 cargo oxide run cpp_consumes_rust_device
+```
+"#,
+    );
+
+    assert_eq!(
+        parsed.requirements,
+        [
+            "CUDA Toolkit (nvcc, libNVVM, nvJitLink)",
+            "Blackwell+ GPU (sm_100+) — LTOIR requires NVVM 20 dialect",
+        ]
+    );
+}
+
+#[test]
+fn requirement_parser_joins_wrapped_items_but_not_following_paragraphs() {
+    // Modeled on the cutile_inter_kernel README: the last bullet wraps
+    // across indented lines (joined), and the paragraph after the blank
+    // line must not be glued onto it.
+    let parsed = parse_example_readme(
+        "cutile_inter_kernel",
+        r#"
+# cutile_inter_kernel
+
+## Requirements
+
+- cuda-oxide from this repository.
+- CUDA Toolkit 13.1+ with `nvcc` and `tileiras` available. This example
+  defaults `CUDA_TOOLKIT_PATH` to `/usr/local/cuda` through its local Cargo
+  config; set `CUDA_TOOLKIT_PATH` yourself if your toolkit lives elsewhere.
+
+`cargo oxide run` targets explicit `--arch` first, then `CUDA_OXIDE_TARGET`,
+then auto-detects the local GPU.
+
+## Run
+
+Run instructions.
+"#,
+    );
+
+    assert_eq!(
+        parsed.requirements,
+        [
+            "cuda-oxide from this repository.",
+            "CUDA Toolkit 13.1+ with nvcc and tileiras available. This example \
+                 defaults CUDA_TOOLKIT_PATH to /usr/local/cuda through its local Cargo \
+                 config; set CUDA_TOOLKIT_PATH yourself if your toolkit lives elsewhere.",
+        ]
+    );
+}
+
+#[test]
+fn requirement_parser_captures_ordered_list_items() {
+    // Modeled on the mathdx_ffi_test README: prerequisites written as an
+    // ordered list, followed by a paragraph that is not part of the list.
+    let parsed = parse_example_readme(
+        "mathdx_ffi_test",
+        r#"
+# mathdx_ffi_test
+
+## Prerequisites
+
+1. **CUDA Toolkit 12.x+** with nvcc
+2. **MathDx Library** - Download from: https://developer.nvidia.com/cublasdx-downloads
+3. **cuda-oxide compiler** toolchain
+
+If your default host compiler is newer than the CUDA Toolkit supports, set
+`NVCC_CCBIN` or `CUDAHOSTCXX` before running the example.
+"#,
+    );
+
+    assert_eq!(
+        parsed.requirements,
+        [
+            "CUDA Toolkit 12.x+ with nvcc",
+            "MathDx Library - Download from: https://developer.nvidia.com/cublasdx-downloads",
+            "cuda-oxide compiler toolchain",
+        ]
+    );
+}
+
+#[test]
+fn requirement_parser_recognizes_build_requirements_heading() {
+    let parsed = parse_example_readme(
+        "example",
+        r#"
+# example
+
+## Build Requirements
+
+- nvcc with `--expt-relaxed-constexpr`
+"#,
+    );
+
+    assert_eq!(parsed.requirements, ["nvcc with --expt-relaxed-constexpr"]);
+}
+
+#[test]
+fn requirement_parser_parses_two_column_requirement_tables() {
+    // Modeled on the abi_hmm README: requirements in a two-column table,
+    // including an escaped pipe inside a cell.
+    let parsed = parse_example_readme(
+        "abi_hmm",
+        r#"
+# abi_hmm
+
+## Requirements
+
+| Requirement   | Minimum                                           |
+|---------------|---------------------------------------------------|
+| GPU           | Turing or newer (RTX 20xx+)                       |
+| Linux Kernel  | 6.1.24+                                           |
+| HMM Support   | `nvidia-smi -q \| grep Addressing` shows "HMM"    |
+
+## Build and Run
+
+Instructions.
+"#,
+    );
+
+    assert_eq!(
+        parsed.requirements,
+        [
+            "GPU: Turing or newer (RTX 20xx+)",
+            "Linux Kernel: 6.1.24+",
+            "HMM Support: nvidia-smi -q | grep Addressing shows \"HMM\"",
+        ]
+    );
+}
+
+#[test]
+fn requirement_parser_skips_tables_that_are_not_two_columns() {
+    // A three-column table has no unambiguous name/value mapping, so it
+    // must be skipped whole instead of half-parsed.
+    let parsed = parse_example_readme(
+        "example",
+        r#"
+# example
+
+## Requirements
+
+| Test  | Status | Description |
+|-------|--------|-------------|
+| alpha | Pass   | First test  |
+| beta  | Pass   | Second test |
+"#,
+    );
+
+    assert_eq!(parsed.requirements, Vec::<String>::new());
+}
+
+#[test]
+fn example_discovery_is_sorted_and_uses_manifest_fallback() {
+    let root = unique_temp_dir("cargo_oxide_list_examples");
+    std::fs::create_dir_all(&root).unwrap();
+
+    write_list_example(&root, "zeta", Some("Manifest fallback description"), None);
+
+    write_list_example(
+        &root,
+        "alpha",
+        None,
+        Some("# alpha\n\n## Alpha Example\n\nREADME description.\n"),
+    );
+
+    let examples = discover_examples(&root).unwrap();
+
+    assert_eq!(
+        examples
+            .iter()
+            .map(|example| example.name.as_str())
+            .collect::<Vec<_>>(),
+        ["alpha", "zeta"]
+    );
+    assert_eq!(examples[0].description, "README description.");
+    assert_eq!(examples[1].description, "Manifest fallback description");
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn example_discovery_keeps_examples_without_readmes() {
+    let root = unique_temp_dir("cargo_oxide_list_missing_readme");
+    std::fs::create_dir_all(&root).unwrap();
+
+    write_list_example(&root, "minimal", None, None);
+
+    let examples = discover_examples(&root).unwrap();
+
+    assert_eq!(examples.len(), 1);
+    assert_eq!(examples[0].name, "minimal");
+    assert_eq!(examples[0].description, "No description documented.");
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn example_discovery_skips_directory_without_manifest() {
+    let root = unique_temp_dir("cargo_oxide_list_missing_manifest");
+    std::fs::create_dir_all(root.join("scratch")).unwrap();
+
+    write_list_example(&root, "real", Some("A real example"), None);
+
+    let examples =
+        discover_examples(&root).expect("manifest-less directories must not abort listing");
+
+    assert_eq!(
+        examples
+            .iter()
+            .map(|example| example.name.as_str())
+            .collect::<Vec<_>>(),
+        ["real"]
+    );
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn interop_metadata_selects_named_binary_artifact() {
+    let root = unique_temp_dir("cargo_oxide_named_bin_interop");
+    let device_dir = root.join("device");
+    std::fs::create_dir_all(&device_dir).unwrap();
+
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"[package]
+name = "host-app"
+version = "0.1.0"
+edition = "2024"
+
+[[package.metadata.cuda-oxide.device-crates]]
+manifest-path = "device/Cargo.toml"
+bin = "secondary-device"
+"#,
+    )
+    .unwrap();
+    std::fs::write(
+        device_dir.join("Cargo.toml"),
+        r#"[package]
+name = "kernel-package"
+version = "0.1.0"
+edition = "2024"
+"#,
+    )
+    .unwrap();
+
+    let config = load_interop_config(&root).expect("interop metadata should load");
+    let device = &config.device_crates[0];
+    assert_eq!(device.bin.as_deref(), Some("secondary-device"));
+    assert_eq!(
+        interop_device_cargo_target_name(&device_dir.join("Cargo.toml"), device),
+        "secondary-device"
+    );
+    assert_eq!(
+        interop_device_artifact_name(&device_dir.join("Cargo.toml"), device),
+        "secondary_device"
+    );
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn interop_binary_target_uses_cargo_source_path() {
+    let manifest = Path::new("/workspace/kernels/Cargo.toml");
+    let metadata = serde_json::json!({
+        "packages": [{
+            "manifest_path": "/workspace/kernels/Cargo.toml",
+            "targets": [
+                {
+                    "name": "kernel-package",
+                    "kind": ["lib"],
+                    "src_path": "/workspace/kernels/src/lib.rs"
+                },
+                {
+                    "name": "secondary-device",
+                    "kind": ["bin"],
+                    "src_path": "/workspace/kernels/src/device_secondary.rs"
+                }
+            ]
+        }]
+    });
+
+    assert_eq!(
+        interop_binary_target_from_metadata(&metadata, manifest, "secondary-device").unwrap(),
+        InteropBinaryTarget {
+            source_path: PathBuf::from("/workspace/kernels/src/device_secondary.rs"),
+        }
+    );
+}
+
+#[test]
+fn interop_binary_target_rejects_unknown_name_with_available_targets() {
+    let manifest = Path::new("/workspace/kernels/Cargo.toml");
+    let metadata = serde_json::json!({
+        "packages": [{
+            "manifest_path": "/workspace/kernels/Cargo.toml",
+            "targets": [{
+                "name": "main-device",
+                "kind": ["bin"],
+                "src_path": "/workspace/kernels/src/device_main.rs"
+            }]
+        }]
+    });
+
+    let error =
+        interop_binary_target_from_metadata(&metadata, manifest, "missing-device").unwrap_err();
+    assert!(error.contains("no binary target \"missing-device\""));
+    assert!(error.contains("available binary targets: main-device"));
+}
+
+#[test]
+fn release_depfile_stem_preserves_hyphens_like_cargo_uplift() {
+    let target_dir = Path::new("/workspace/device/target");
+    // Regression: the stem was normalize_crate_name'd (hyphen -> underscore),
+    // but cargo uplifts dep-info named after the bin target verbatim, so
+    // every hyphenated bin/package with source-identity aborted with
+    // "did not produce dependency file".
+    assert_eq!(
+        release_depfile_path(target_dir, "simt-device"),
+        PathBuf::from("/workspace/device/target/release/simt-device.d")
+    );
+    assert_eq!(
+        release_depfile_path(target_dir, "kernels"),
+        PathBuf::from("/workspace/device/target/release/kernels.d")
+    );
+}
+
+/// The load-bearing claim behind `release_depfile_path` is cargo's own
+/// uplift naming, so assert it against a real `cargo build` of a
+/// hyphenated package with a hyphenated bin target rather than against
+/// our expectations of it.
+#[test]
+fn release_depfile_path_matches_real_cargo_uplift_for_hyphenated_bin() {
+    let root = unique_temp_dir("cargo_oxide_hyphen_depfile");
+    std::fs::create_dir_all(root.join("src/bin")).unwrap();
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"[package]
+name = "probe-device"
+version = "0.1.0"
+edition = "2021"
+
+[[bin]]
+name = "hyphen-device"
+path = "src/bin/hyphen_device.rs"
+"#,
+    )
+    .unwrap();
+    std::fs::write(root.join("src/bin/hyphen_device.rs"), "fn main() {}\n").unwrap();
+    // Pin the probe's target dir inside the temp root so an ambient
+    // CARGO_TARGET_DIR (shared CI caches) cannot collide across tests.
+    let target_dir = root.join("target");
+
+    let build = Command::new("cargo")
+        .args(["build", "--release", "--bin", "hyphen-device"])
+        .env("CARGO_TARGET_DIR", &target_dir)
+        .current_dir(&root)
+        .output()
+        .expect("failed to run cargo build for the depfile probe");
+    assert!(
+        build.status.success(),
+        "depfile probe build failed:\n{}",
+        String::from_utf8_lossy(&build.stderr)
+    );
+
+    let metadata = Command::new("cargo")
+        .args(["metadata", "--format-version=1", "--no-deps"])
+        .env("CARGO_TARGET_DIR", &target_dir)
+        .current_dir(&root)
+        .output()
+        .expect("failed to run cargo metadata for the depfile probe");
+    assert!(
+        metadata.status.success(),
+        "depfile probe metadata failed:\n{}",
+        String::from_utf8_lossy(&metadata.stderr)
+    );
+    let metadata: serde_json::Value = serde_json::from_slice(&metadata.stdout).unwrap();
+
+    let depfile =
+        release_depfile_path(&cargo_target_directory(&metadata).unwrap(), "hyphen-device");
+    assert!(
+        depfile.is_file(),
+        "cargo did not uplift the dep-info where we derive it: {}",
+        depfile.display()
+    );
+    // The underscore-normalized twin must NOT be where we look.
+    assert!(
+        !depfile.with_file_name("hyphen_device.d").exists(),
+        "cargo unexpectedly uplifted an underscore-normalized dep-info file"
+    );
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn ptx_artifact_paths_normalize_hyphenated_example_names() {
+    let root = unique_temp_dir("cargo_oxide_inspect_regular");
+    std::fs::create_dir_all(&root).unwrap();
+
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"[package]
+name = "demo-app"
+version = "0.1.0"
+edition = "2024"
+"#,
+    )
+    .unwrap();
+
+    assert_eq!(
+        ptx_artifact_paths(&root, "demo-app"),
+        vec![root.join("demo_app.ptx")]
+    );
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn ptx_artifact_paths_resolve_interop_device_artifacts() {
+    let root = unique_temp_dir("cargo_oxide_inspect_interop");
+    let device_dir = root.join("device");
+    std::fs::create_dir_all(&device_dir).unwrap();
+
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"[package]
+name = "host-app"
+version = "0.1.0"
+edition = "2024"
+
+[package.metadata.cuda-oxide]
+interop = "device"
+
+[[package.metadata.cuda-oxide.device-crates]]
+manifest-path = "device/Cargo.toml"
+ptx-dir = "generated"
+artifact-name = "custom-device"
+"#,
+    )
+    .unwrap();
+
+    std::fs::write(
+        device_dir.join("Cargo.toml"),
+        r#"[package]
+name = "device-app"
+version = "0.1.0"
+edition = "2024"
+"#,
+    )
+    .unwrap();
+
+    assert_eq!(
+        ptx_artifact_paths(&root, "host-app"),
+        vec![root.join("generated/custom_device.ptx")]
+    );
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn interop_metadata_declares_cubin_and_source_identity() {
+    let root = unique_temp_dir("cargo_oxide_cubin_interop");
+    let device_dir = root.join("device");
+    std::fs::create_dir_all(&device_dir).unwrap();
+
+    std::fs::write(
+        root.join("Cargo.toml"),
+        r#"[package]
+name = "host-app"
+version = "0.1.0"
+edition = "2024"
+
+[package.metadata.cuda-oxide]
+interop = "device"
+
+[[package.metadata.cuda-oxide.device-crates]]
+manifest-path = "device/Cargo.toml"
+artifact-dir = "device"
+artifact-name = "custom-device"
+artifact-kind = "cubin"
+source-identity = true
+"#,
+    )
+    .unwrap();
+    std::fs::write(
+        device_dir.join("Cargo.toml"),
+        r#"[package]
+name = "device-app"
+version = "0.1.0"
+edition = "2024"
+"#,
+    )
+    .unwrap();
+
+    let config = load_interop_config(&root).expect("interop metadata should load");
+    assert_eq!(config.device_crates.len(), 1);
+    let device = &config.device_crates[0];
+    assert_eq!(device.artifact_kind, InteropArtifactKind::Cubin);
+    assert!(device.source_identity);
+    assert_eq!(
+        interop_device_artifact_path(&root, device, "custom-device"),
+        root.join("device/custom_device.cubin")
+    );
+    assert_eq!(
+        interop_cubin_target(Some("sm_120a"), None).unwrap().sm(),
+        "sm_120a"
+    );
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn recorded_target_sidecar_is_the_completion_marker() {
+    let root = unique_temp_dir("cargo_oxide_recorded_target");
+    std::fs::create_dir_all(&root).unwrap();
+    let ir_path = root.join("device_kernels.ll");
+
+    // No sidecar: the backend never completed its artifact contract.
+    let error = read_interop_recorded_target(&ir_path).unwrap_err();
+    assert!(error.contains("completion marker"), "{error}");
+
+    // Bare target line (pre-versioned contract) is accepted.
+    std::fs::write(root.join("device_kernels.target"), "sm_90a\n").unwrap();
+    assert_eq!(read_interop_recorded_target(&ir_path).unwrap(), "sm_90a");
+
+    // The versioned marker says the sibling .options file is required...
+    std::fs::write(
+        root.join("device_kernels.target"),
+        format!(
+            "sm_120a\n{}\n",
+            oxide_artifacts::COMPILE_OPTIONS_TARGET_MARKER
+        ),
+    )
+    .unwrap();
+    let error = read_interop_recorded_target(&ir_path).unwrap_err();
+    assert!(error.contains("compile options"), "{error}");
+
+    // ...and the record is trusted once it exists.
+    std::fs::write(root.join("device_kernels.options"), "fma=on\ndebug=none\n").unwrap();
+    assert_eq!(read_interop_recorded_target(&ir_path).unwrap(), "sm_120a");
+
+    // Unknown trailing content is rejected, not half-trusted.
+    std::fs::write(
+        root.join("device_kernels.target"),
+        "sm_120a\nmystery-marker\nrest\n",
+    )
+    .unwrap();
+    assert!(read_interop_recorded_target(&ir_path).is_err());
+    std::fs::write(root.join("device_kernels.target"), "\n").unwrap();
+    assert!(read_interop_recorded_target(&ir_path).is_err());
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn ptx_recorded_target_reads_the_target_directive() {
+    let root = unique_temp_dir("cargo_oxide_ptx_target");
+    std::fs::create_dir_all(&root).unwrap();
+    let ptx_path = root.join("kernels.ptx");
+
+    std::fs::write(
+        &ptx_path,
+        "// comment\n.version 8.7\n.target sm_120a\n.address_size 64\n",
+    )
+    .unwrap();
+    assert_eq!(ptx_recorded_target(&ptx_path).unwrap(), "sm_120a");
+
+    // Device-debug builds record `.target sm_90, debug`.
+    std::fs::write(&ptx_path, ".version 8.3\n.target sm_90, debug\n").unwrap();
+    assert_eq!(ptx_recorded_target(&ptx_path).unwrap(), "sm_90");
+
+    std::fs::write(&ptx_path, ".version 8.3\n").unwrap();
+    assert!(ptx_recorded_target(&ptx_path).is_err());
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn interop_identity_target_is_read_from_the_emitted_artifact() {
+    let root = unique_temp_dir("cargo_oxide_identity_target");
+    std::fs::create_dir_all(root.join("device")).unwrap();
+
+    let ptx_crate = DeviceCrateConfig {
+        manifest_path: PathBuf::from("device/Cargo.toml"),
+        artifact_dir: PathBuf::from("device"),
+        artifact_name: Some("kernels".to_string()),
+        artifact_kind: InteropArtifactKind::Ptx,
+        source_identity: true,
+        bin: None,
+    };
+    // Whatever the request hint said, the emitted PTX is the record.
+    std::fs::write(
+        root.join("device/kernels.ptx"),
+        ".version 8.7\n.target sm_90a\n",
+    )
+    .unwrap();
+    assert_eq!(
+        interop_artifact_recorded_target(&root, &ptx_crate, "kernels").unwrap(),
+        "sm_90a"
+    );
+
+    // Cubin identity reads the backend sidecar the finalizer compiled
+    // with, not the PTX and not any hint.
+    let cubin_crate = DeviceCrateConfig {
+        artifact_kind: InteropArtifactKind::Cubin,
+        ..ptx_crate
+    };
+    std::fs::write(root.join("device/kernels.target"), "sm_100a\n").unwrap();
+    assert_eq!(
+        interop_artifact_recorded_target(&root, &cubin_crate, "kernels").unwrap(),
+        "sm_100a"
+    );
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn read_ptx_artifact_returns_exact_contents() {
+    let root = unique_temp_dir("cargo_oxide_read_ptx");
+    std::fs::create_dir_all(&root).unwrap();
+
+    let path = root.join("demo.ptx");
+    std::fs::write(&path, ".version 8.0\n.target sm_90\n").unwrap();
+
+    assert_eq!(
+        read_ptx_artifact(&path).unwrap(),
+        ".version 8.0\n.target sm_90\n"
+    );
+
+    std::fs::remove_dir_all(root).unwrap();
+}
+
+#[test]
+fn list_json_has_versioned_stable_shape() {
+    let examples = vec![ExampleInfo {
+        name: "vecadd".to_string(),
+        title: "Vector Addition".to_string(),
+        description: "Adds two vectors.".to_string(),
+        requirements: vec!["Minimum GPU: sm_70+".to_string()],
+    }];
+
+    let output = format_examples_json(&examples).unwrap();
+    let value: serde_json::Value = serde_json::from_str(&output).unwrap();
+
+    assert_eq!(value["schema_version"], 1);
+    assert_eq!(value["examples"][0]["name"], "vecadd");
+    assert_eq!(
+        value["examples"][0]["requirements"][0],
+        "Minimum GPU: sm_70+"
+    );
+    assert!(output.ends_with('\n'));
+}
+
+#[test]
+fn read_ptx_artifact_reports_missing_file() {
+    let root = unique_temp_dir("cargo_oxide_missing_ptx");
+    let path = root.join("missing.ptx");
+
+    let error = read_ptx_artifact(&path).unwrap_err();
+
+    assert!(error.contains("could not read generated PTX"));
+    assert!(error.contains("missing.ptx"));
+}
+
+#[test]
+fn nvvm_ir_requested_reads_project_configuration() {
+    let ctx = Context {
+        workspace_root: PathBuf::from("/tmp/project"),
+        codegen_crate: PathBuf::from("/tmp/project"),
+        examples_dir: PathBuf::from("/tmp/project"),
+        backend_so: PathBuf::from("/tmp/backend.so"),
+        is_workspace: false,
+        config: OxideConfig {
+            env: vec![("CUDA_OXIDE_EMIT_NVVM_IR".to_string(), "true".to_string())],
+            ..OxideConfig::default()
+        },
+    };
+
+    assert_eq!(nvvm_ir_requested_with_env(&ctx, None), Ok(true));
+}
+
+#[test]
+fn nvvm_ir_requested_accepts_disabled_project_configuration() {
+    let ctx = Context {
+        workspace_root: PathBuf::from("/tmp/project"),
+        codegen_crate: PathBuf::from("/tmp/project"),
+        examples_dir: PathBuf::from("/tmp/project"),
+        backend_so: PathBuf::from("/tmp/backend.so"),
+        is_workspace: false,
+        config: OxideConfig {
+            env: vec![("CUDA_OXIDE_EMIT_NVVM_IR".to_string(), "false".to_string())],
+            ..OxideConfig::default()
+        },
+    };
+
+    assert_eq!(nvvm_ir_requested_with_env(&ctx, None), Ok(false));
+}
+
+#[test]
+fn nvvm_ir_requested_env_disable_overrides_enabled_project_configuration() {
+    let ctx = Context {
+        workspace_root: PathBuf::from("/tmp/project"),
+        codegen_crate: PathBuf::from("/tmp/project"),
+        examples_dir: PathBuf::from("/tmp/project"),
+        backend_so: PathBuf::from("/tmp/backend.so"),
+        is_workspace: false,
+        config: OxideConfig {
+            env: vec![("CUDA_OXIDE_EMIT_NVVM_IR".to_string(), "true".to_string())],
+            ..OxideConfig::default()
+        },
+    };
+
+    // The process environment outranks `cuda-oxide.toml`: an explicit
+    // false in the environment wins over the project's `true`, in either
+    // accepted spelling.
+    for disabled in ["false", "0"] {
+        assert_eq!(
+            nvvm_ir_requested_with_env(&ctx, Some(disabled.into())),
+            Ok(false)
+        );
+    }
+}
+
+#[test]
+fn scaffold_sync_template_uses_launch_contract_and_docs() {
+    let files = scaffold_files("demo_kernel", false);
+    assert!(files.cargo_toml.contains("name = \"demo_kernel\""));
+    assert!(files.readme.contains("cargo oxide doctor"));
+    assert!(files.readme.contains("cargo oxide run"));
+    assert!(files.gitignore.contains("/target/"));
+    // The template uses the launch_bounds / launch_contract attribute
+    // macros, so the cuda_device import must bring them in; a scaffolded
+    // project fails to compile without this exact line.
+    assert!(files.main_rs.starts_with(
+        "use cuda_device::{kernel, launch_bounds, launch_contract, thread, DisjointSlice};"
+    ));
+    assert!(
+        files
+            .main_rs
+            .contains("#[launch_contract(domain = 1, block = (256, 1, 1))]")
+    );
+    assert!(files.main_rs.contains("prepare_vecadd"));
+    assert!(files.main_rs.contains("LaunchConfig1D"));
+    assert!(!files.main_rs.contains("LaunchConfig::for_num_elems"));
+}
+
+#[test]
+fn scaffold_async_template_keeps_async_deps_and_docs() {
+    let files = scaffold_files("async_demo", true);
+    assert!(files.cargo_toml.contains("cuda-async"));
+    assert!(files.cargo_toml.contains("tokio"));
+    assert!(files.readme.contains("async cuda-oxide"));
+    assert!(files.readme.contains("cargo oxide doctor"));
+    // The async README must stand alone: it describes the async launch
+    // path and never talks about "the sync template".
+    assert!(files.readme.contains("DeviceOperation"));
+    assert!(!files.readme.contains("sync template"));
+    assert!(files.gitignore.contains("**/*.ptx"));
+    assert!(files.main_rs.contains("vecadd_async"));
+    assert!(files.main_rs.contains("use cuda_host::cuda_module;"));
+    assert!(!files.main_rs.contains("use cuda_device::{cuda_module"));
+}
+
+#[test]
+fn scaffold_gitignore_covers_every_clean_artifact_suffix() {
+    let gitignore = scaffold_gitignore();
+    assert!(gitignore.contains("/target/"));
+    assert!(gitignore.contains("**/*.bc"));
+    for suffix in GENERATED_ARTIFACT_SUFFIXES {
+        // Match whole lines, not substrings: `**/*.cubin.target` contains
+        // `**/*.cubin` as a substring, so `contains()` would keep passing
+        // even if the `cubin` pattern itself were dropped.
+        let pattern = format!("**/*.{suffix}");
+        assert!(
+            gitignore.lines().any(|line| line == pattern),
+            "scaffold .gitignore must ignore clean suffix `{suffix}`"
+        );
+    }
+}
+
+#[test]
+fn device_debug_env_value_matches_the_backend_parser() {
+    // The exported strings must round-trip through the shared
+    // `CUDA_OXIDE_DEBUG` parser (the same one the codegen backend uses);
+    // a typo would silently fall through to the profile-derived default
+    // instead of failing, so check the actual parse.
+    assert_eq!(DeviceDebug::Off.env_value(), None);
+    assert_eq!(DeviceDebug::LineTables.env_value(), Some("line"));
+    assert_eq!(DeviceDebug::Full.env_value(), Some("full"));
+    assert_eq!(
+        cuda_artifact_finalizer::DebugPolicy::parse_env_override("line"),
+        Some(cuda_artifact_finalizer::DebugPolicy::LineTables)
+    );
+    assert_eq!(
+        cuda_artifact_finalizer::DebugPolicy::parse_env_override("full"),
+        Some(cuda_artifact_finalizer::DebugPolicy::Full)
+    );
+}
+
+#[test]
+fn passthrough_fingerprint_separates_the_device_debug_policies() {
+    let ctx = test_context(OxideConfig::default());
+    let base = CargoPassthroughOptions {
+        verbose: false,
+        emit_nvvm_ir: false,
+        arch: None,
+        features: None,
+        cargo_target_dir: None,
+        device_codegen_crate: None,
+        device_cfgs: &[],
+        no_fmad: false,
+        unchecked_indexing: false,
+        materialize_cubin: false,
+        device_debug: DeviceDebug::Off,
+    };
+    let line_tables = CargoPassthroughOptions {
+        device_debug: DeviceDebug::LineTables,
+        ..base
+    };
+    let full = CargoPassthroughOptions {
+        device_debug: DeviceDebug::Full,
+        ..base
+    };
+    let materialization = MaterializationMode::default();
+    // Empty inherited env, for the same reason as the sibling fingerprint
+    // tests: an ambient CUDA_OXIDE_DEBUG is folded in on its own, which would
+    // collapse these onto the base.
+    let inherited_env = BTreeMap::new();
+    let fp = |opts: &CargoPassthroughOptions<'_>| {
+        passthrough_codegen_fingerprint_with_env(
+            &ctx,
+            opts,
+            None,
+            None,
+            &materialization,
+            &inherited_env,
+        )
+    };
+    // The policy changes what libNVVM and nvJitLink are asked to do (`-g`,
+    // `-opt=0`, `-lineinfo`), so it must not share a fingerprint with the
+    // default -- otherwise Cargo reuses artifacts built without it.
+    let off = fp(&base);
+    assert_ne!(off, fp(&line_tables));
+    assert_ne!(off, fp(&full));
+    assert_ne!(fp(&line_tables), fp(&full));
+}
+
+#[test]
+fn full_device_debug_disables_mir_optimization() {
+    let cmd = Command::new("cargo");
+    let mut encoded = "base".to_string();
+
+    append_full_debug_mir_rustflag(&mut encoded, &cmd, Some("full"));
+
+    assert_eq!(decoded_rustflags(&encoded), ["base", "-Zmir-opt-level=0"]);
+}
+
+#[test]
+fn numeric_full_debug_alias_disables_mir_optimization() {
+    // The backend accepts `CUDA_OXIDE_DEBUG=2` as full debug; the shared
+    // parser guarantees the build policy agrees, so `2` must disable MIR
+    // optimization exactly like `full`.
+    let mut cmd = Command::new("cargo");
+    cmd.env("CUDA_OXIDE_DEBUG", "2");
+    let mut encoded = "base".to_string();
+
+    append_full_debug_mir_rustflag(&mut encoded, &cmd, None);
+
+    assert_eq!(decoded_rustflags(&encoded), ["base", "-Zmir-opt-level=0"]);
+}
+
+#[test]
+fn line_tables_keep_normal_mir_optimization() {
+    let mut cmd = Command::new("cargo");
+    cmd.env("CUDA_OXIDE_DEBUG", "line");
+    let mut encoded = "base".to_string();
+
+    append_full_debug_mir_rustflag(&mut encoded, &cmd, None);
+
+    assert_eq!(decoded_rustflags(&encoded), ["base"]);
+}
+
+#[test]
+fn explicit_line_tables_override_inherited_full_debug_for_mir_optimization() {
+    let mut cmd = Command::new("cargo");
+    cmd.env("CUDA_OXIDE_DEBUG", "line");
+    let mut encoded = "base".to_string();
+
+    append_full_debug_mir_rustflag(&mut encoded, &cmd, Some("full"));
+
+    assert_eq!(decoded_rustflags(&encoded), ["base"]);
+}
diff --git a/crates/cargo-oxide/src/commands/toolkit.rs b/crates/cargo-oxide/src/commands/toolkit.rs
new file mode 100644
index 0000000000..e9f169e8ee
--- /dev/null
+++ b/crates/cargo-oxide/src/commands/toolkit.rs
@@ -0,0 +1,259 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use std::path::{Path, PathBuf};
+use std::process::Command;
+
+use super::*;
+
+const DEFAULT_SANITIZER_ERROR_EXITCODE: &str = "86";
+
+#[derive(Debug, PartialEq, Eq)]
+pub(super) struct SanitizerInvocationArgs {
+    pub(super) args: Vec<String>,
+    pub(super) uses_default_error_exitcode: bool,
+    pub(super) status_checks_weakened: bool,
+}
+
+pub(super) fn sanitizer_invocation_args(sanitizer_args: &[String]) -> SanitizerInvocationArgs {
+    let has_explicit_error_exitcode = sanitizer_args
+        .iter()
+        .any(|arg| arg == "--error-exitcode" || arg.starts_with("--error-exitcode="));
+    if has_explicit_error_exitcode {
+        return SanitizerInvocationArgs {
+            args: sanitizer_args.to_vec(),
+            uses_default_error_exitcode: false,
+            status_checks_weakened: sanitizer_option_is_no(sanitizer_args, "check-exit-code")
+                || sanitizer_option_is_no(sanitizer_args, "require-cuda-init"),
+        };
+    }
+
+    let mut args = Vec::with_capacity(sanitizer_args.len() + 2);
+    args.extend([
+        "--error-exitcode".to_string(),
+        DEFAULT_SANITIZER_ERROR_EXITCODE.to_string(),
+    ]);
+    args.extend_from_slice(sanitizer_args);
+    SanitizerInvocationArgs {
+        args,
+        uses_default_error_exitcode: true,
+        status_checks_weakened: sanitizer_option_is_no(sanitizer_args, "check-exit-code")
+            || sanitizer_option_is_no(sanitizer_args, "require-cuda-init"),
+    }
+}
+
+fn sanitizer_option_is_no(args: &[String], name: &str) -> bool {
+    let option = format!("--{name}");
+    let equals_prefix = format!("{option}=");
+    args.iter().enumerate().any(|(index, arg)| {
+        arg.strip_prefix(&equals_prefix)
+            .is_some_and(|value| value.eq_ignore_ascii_case("no"))
+            || (arg == &option
+                && args
+                    .get(index + 1)
+                    .is_some_and(|value| value.eq_ignore_ascii_case("no")))
+    })
+}
+
+/// Fallback locations probed for `compute-sanitizer` when it is neither on
+/// PATH nor under the configured CUDA toolkit root. Shared by `sanitize`
+/// (`run_compute_sanitizer`) and `doctor` so both use the same discovery
+/// order by construction.
+pub(super) const COMPUTE_SANITIZER_FALLBACK_PATHS: &[&str] = &[
+    "/usr/local/cuda/bin/compute-sanitizer",
+    "/opt/cuda/bin/compute-sanitizer",
+    "/usr/bin/compute-sanitizer",
+];
+
+/// Fallback locations probed for `nvcc`, in the same idiom and for the same
+/// reason as the list above. `nvcc` ships in the toolkit's `bin/` beside
+/// `compute-sanitizer` and `cuda-gdb`, so it has to be found the same way.
+pub(super) const NVCC_FALLBACK_PATHS: &[&str] = &[
+    "/usr/local/cuda/bin/nvcc",
+    "/opt/cuda/bin/nvcc",
+    "/usr/bin/nvcc",
+];
+
+/// Fallback locations probed for `cuda-gdb`. Shared by `debug`
+/// (`codegen_debug`) and `doctor` so both use the same discovery order by
+/// construction -- doctor exists to predict whether `debug` will work, so the
+/// two answering differently is the bug this list prevents.
+pub(super) const CUDA_GDB_FALLBACK_PATHS: &[&str] = &[
+    "/usr/local/cuda/bin/cuda-gdb",
+    "/opt/cuda/bin/cuda-gdb",
+    "/usr/bin/cuda-gdb",
+];
+
+/// Every CUDA toolkit executable `doctor` probes, with its fallbacks.
+///
+/// One table so a fourth tool cannot be added with a different discovery rule.
+/// Before this existed, `compute-sanitizer` resolved through the toolkit root
+/// while `nvcc` and `cuda-gdb` used a bare PATH lookup, so doctor reported the
+/// toolkit missing on an install where it had already found `cuda.h`, libNVVM,
+/// nvJitLink and libdevice under that same root.
+pub(super) const DOCTOR_TOOLKIT_TOOLS: [(&str, &[&str]); 3] = [
+    ("nvcc", NVCC_FALLBACK_PATHS),
+    ("cuda-gdb", CUDA_GDB_FALLBACK_PATHS),
+    ("compute-sanitizer", COMPUTE_SANITIZER_FALLBACK_PATHS),
+];
+
+/// Resolve one of [`DOCTOR_TOOLKIT_TOOLS`] the way the command that uses it
+/// does: PATH first, then the configured toolkit root, then the standard
+/// install roots.
+/// The standard install roots to try for `name`, or none if the table does not
+/// know it. Split out so the pairing can be checked without a filesystem or an
+/// ambient environment, neither of which a test can control here: the PATH
+/// probe inside `find_cuda_toolkit_executable` shells out to `which` and has no
+/// injection point.
+pub(super) fn toolkit_tool_fallbacks(name: &str) -> &'static [&'static str] {
+    DOCTOR_TOOLKIT_TOOLS
+        .iter()
+        .find(|(tool, _)| *tool == name)
+        .map(|(_, paths)| *paths)
+        .unwrap_or(&[])
+}
+
+pub(super) fn doctor_toolkit_tool(ctx: &Context, name: &str) -> Option<PathBuf> {
+    find_cuda_toolkit_executable(ctx, name, toolkit_tool_fallbacks(name))
+}
+
+pub(super) fn run_compute_sanitizer(
+    ctx: &Context,
+    example_dir: &Path,
+    tool: &str,
+    sanitizer_args: &[String],
+    application_args: &[String],
+    binary: &Path,
+) {
+    let compute_sanitizer = find_cuda_toolkit_executable(
+        ctx,
+        "compute-sanitizer",
+        COMPUTE_SANITIZER_FALLBACK_PATHS,
+    )
+    .unwrap_or_else(|| {
+        eprintln!("Error: compute-sanitizer not found.");
+        eprintln!(
+            "It is installed with the CUDA Toolkit; run `cargo oxide doctor` to check CUDA setup."
+        );
+        std::process::exit(1);
+    });
+
+    let invocation_args = sanitizer_invocation_args(sanitizer_args);
+    let mut cmd = Command::new(compute_sanitizer);
+    cmd.args(["--tool", tool])
+        .args(&invocation_args.args)
+        .arg(binary)
+        .args(application_args)
+        .current_dir(example_dir);
+    apply_config_env(&mut cmd, ctx);
+    apply_ld_library_path(&mut cmd, ctx);
+
+    let forwarded_args = if invocation_args.args.is_empty() {
+        String::new()
+    } else {
+        format!(" {}", invocation_args.args.join(" "))
+    };
+    let displayed_application_args = if application_args.is_empty() {
+        String::new()
+    } else {
+        format!(" {}", application_args.join(" "))
+    };
+    println!(
+        "Running compute-sanitizer --tool {tool}{forwarded_args} {}{displayed_application_args}...",
+        binary.display()
+    );
+    println!();
+
+    let status = cmd.status().expect("Failed to run compute-sanitizer");
+    if !status.success() {
+        eprintln!(
+            "\nCompute Sanitizer failed with exit code: {:?}",
+            status.code()
+        );
+        std::process::exit(status.code().unwrap_or(1));
+    }
+
+    println!();
+    println!("Compute Sanitizer completed with exit code 0.");
+    if !invocation_args.uses_default_error_exitcode {
+        println!(
+            "An explicit --error-exitcode was supplied, so it controls whether findings fail the command."
+        );
+    }
+    if invocation_args.status_checks_weakened {
+        println!(
+            "The supplied sanitizer options can allow target or CUDA-initialization failures to exit 0."
+        );
+    }
+    println!(
+        "Inspect the sanitizer report above; exit status alone is not a clean-report assertion."
+    );
+}
+
+/// Locate an executable by name, first via `which` (PATH lookup), then by
+/// checking a list of common fallback absolute paths.
+pub(super) fn find_executable(name: &str, fallback_paths: &[&str]) -> Option<PathBuf> {
+    if let Ok(output) = Command::new("which").arg(name).output()
+        && output.status.success()
+    {
+        let path = String::from_utf8_lossy(&output.stdout).trim().to_string();
+        if !path.is_empty() {
+            return Some(PathBuf::from(path));
+        }
+    }
+    for path in fallback_paths {
+        let p = PathBuf::from(path);
+        if p.exists() {
+            return Some(p);
+        }
+    }
+    None
+}
+
+/// Locate a CUDA Toolkit executable using the same configured toolkit roots as
+/// `doctor`, after the user's PATH and before generic system fallbacks.
+pub(super) fn find_cuda_toolkit_executable(
+    ctx: &Context,
+    name: &str,
+    fallback_paths: &[&str],
+) -> Option<PathBuf> {
+    find_cuda_toolkit_executable_with_env(ctx, name, fallback_paths, |key| std::env::var(key).ok())
+}
+
+/// `find_cuda_toolkit_executable` with the ambient environment injected.
+///
+/// The process environment takes precedence over `cuda-oxide.toml`'s `env`, so
+/// resolution has to be injectable for unit tests: a developer with a real
+/// `CUDA_TOOLKIT_PATH` (or `CUDA_HOME`) exported would otherwise shadow the
+/// configured root a test is trying to assert on. Same rationale as
+/// `cuda_toolkit_root` and `cuda_header_candidates`.
+pub(super) fn find_cuda_toolkit_executable_with_env(
+    ctx: &Context,
+    name: &str,
+    fallback_paths: &[&str],
+    mut get_env: impl FnMut(&str) -> Option<String>,
+) -> Option<PathBuf> {
+    if let Some(path) = find_executable(name, &[]) {
+        return Some(path);
+    }
+
+    let toolkit = cuda_toolkit_root(|key| {
+        get_env(key)
+            .filter(|value| !value.trim().is_empty())
+            .or_else(|| project_config_env(ctx, key).map(str::to_owned))
+    });
+    let configured = PathBuf::from(toolkit).join("bin").join(name);
+    if configured.exists() {
+        return Some(configured);
+    }
+
+    for path in fallback_paths {
+        let path = PathBuf::from(path);
+        if path.exists() {
+            return Some(path);
+        }
+    }
+    None
+}
diff --git a/crates/cuda-intrinsics-gen/src/model.rs b/crates/cuda-intrinsics-gen/src/model.rs
deleted file mode 100644
index 2a3392ae2e..0000000000
--- a/crates/cuda-intrinsics-gen/src/model.rs
+++ /dev/null
@@ -1,4730 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-use crate::ptx::InstructionPattern;
-use serde::{Deserialize, Serialize};
-use std::{fmt, str::FromStr};
-
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct UpstreamLock {
-    pub schema: u32,
-    pub llvm: LockedLlvm,
-    pub llvm_tblgen: LockedTool,
-    #[serde(default)]
-    pub comparison_tools: Vec<LockedTool>,
-    pub dumps: LockedDumps,
-}
-
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct LockedLlvm {
-    pub repository: String,
-    pub revision: String,
-    pub provenance: String,
-    pub public_output_allowed: bool,
-}
-
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct LockedTool {
-    pub name: String,
-    pub version_line: String,
-    pub sha256: String,
-    #[serde(default)]
-    pub enforce_sha256: bool,
-    pub provenance: String,
-    pub built_from_llvm_revision: Option<String>,
-}
-
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct LockedDumps {
-    pub intrinsics_sha256: String,
-    pub nvptx_sha256: String,
-    pub normalized_imported_sha256: String,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ImportedFile {
-    pub schema: u32,
-    pub source: ImportedSource,
-    pub intrinsics: Vec<ImportedIntrinsic>,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ImportedSource {
-    pub llvm_repository: String,
-    pub llvm_revision: String,
-    pub llvm_tblgen_version: String,
-    pub llvm_tblgen_source_revision: String,
-    pub intrinsics_json_sha256: String,
-    pub nvptx_json_sha256: String,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ImportedIntrinsic {
-    pub source_record: String,
-    pub llvm_name: String,
-    pub arguments: Vec<String>,
-    pub results: Vec<String>,
-    pub classes: Vec<String>,
-    pub properties: Vec<String>,
-    pub selections: Vec<ImportedSelection>,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ImportedSelection {
-    pub source_record: String,
-    pub asm: String,
-    pub predicates: Vec<String>,
-    #[serde(
-        default,
-        skip_serializing_if = "ImportedSelectionConstraints::is_empty"
-    )]
-    pub constraints: ImportedSelectionConstraints,
-}
-
-/// Normalized constraints attached to an NVPTX instruction-selection record.
-///
-/// TableGen represents address-space-specific patterns through anonymous
-/// `PatFrag` records and can bind intrinsic arguments to integer literals.
-/// Keeping those facts separate from the assembly spelling lets policy select
-/// an exact lowering without parsing PTX text.
-#[derive(Debug, Clone, Default, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ImportedSelectionConstraints {
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub address_space: Option<ImportedAddressSpace>,
-    #[serde(default, skip_serializing_if = "Vec::is_empty")]
-    pub immediate_bindings: Vec<ImportedImmediateBinding>,
-}
-
-/// One integer literal fixed by an NVPTX instruction-selection pattern.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ImportedImmediateBinding {
-    pub argument_index: usize,
-    pub value: i64,
-}
-
-impl ImportedSelectionConstraints {
-    pub fn is_empty(&self) -> bool {
-        self.address_space.is_none() && self.immediate_bindings.is_empty()
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ImportedAddressSpace {
-    Generic,
-    Shared,
-}
-
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct OverlayFile {
-    pub schema: u32,
-    pub catalog_version: String,
-    pub intrinsic_abi: u32,
-    pub backend_profile: String,
-    #[serde(default)]
-    pub shards: Vec<String>,
-    #[serde(rename = "intrinsic")]
-    #[serde(default)]
-    pub intrinsics: Vec<OverlayIntrinsic>,
-}
-
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct OverlayShardFile {
-    pub schema: u32,
-    pub family: String,
-    #[serde(rename = "intrinsic")]
-    #[serde(default)]
-    pub intrinsics: Vec<OverlayIntrinsic>,
-    #[serde(default)]
-    pub register_mma_int4: Option<RegisterMmaIntegerAdmission>,
-    #[serde(default)]
-    pub register_mma_int8: Option<RegisterMmaIntegerAdmission>,
-    #[serde(default)]
-    pub register_mma_b1: Option<RegisterMmaBinaryAdmission>,
-    #[serde(default)]
-    pub register_mma_f8f6f4_f32: Option<RegisterMmaF8F6F4Admission>,
-    #[serde(default)]
-    pub register_mma_f8f6f4_f16: Option<RegisterMmaF8F6F4Admission>,
-    #[serde(default)]
-    pub register_mma_mxf8f6f4_f32: Option<RegisterMmaF8F6F4Admission>,
-    #[serde(default)]
-    pub register_mma_fp8: Option<RegisterMmaFp8Admission>,
-    #[serde(default)]
-    pub register_mma_ampere_float: Option<RegisterMmaAmpereFloatAdmission>,
-    #[serde(default, alias = "sparse_mma_int8")]
-    pub sparse_mma_integer: Option<SparseMmaIntegerAdmission>,
-    #[serde(default)]
-    pub sparse_mma_f8f6f4_f32: Option<SparseMmaF8F6F4Admission>,
-    #[serde(default)]
-    pub sparse_mma_f8f6f4_f16: Option<SparseMmaF8F6F4F16Admission>,
-    #[serde(default)]
-    pub prmt: Option<PrmtAdmission>,
-    #[serde(default)]
-    pub packed_conversion_fp8: Option<PackedConversionFp8Admission>,
-    #[serde(default)]
-    pub packed_conversion_fp8_f16x2: Option<PackedConversionFp8F16x2Admission>,
-    #[serde(default)]
-    pub scalar_conversion: Option<ScalarConversionAdmission>,
-    #[serde(default)]
-    pub scalar_arithmetic: Option<ScalarArithmeticAdmission>,
-    #[serde(default)]
-    pub extended_minmax: Option<ExtendedMinMaxAdmission>,
-    #[serde(default)]
-    pub cluster_sreg: Option<ClusterSregAdmission>,
-    #[serde(default)]
-    pub cluster_barrier: Option<ClusterBarrierAdmission>,
-    #[serde(default)]
-    pub mbarrier_extended: Option<MbarrierExtendedAdmission>,
-    #[serde(default)]
-    pub special_registers: Option<SpecialRegisterAdmission>,
-    #[serde(default)]
-    pub debug_control: Option<DebugControlAdmission>,
-    #[serde(default)]
-    pub threadfence: Option<ThreadfenceAdmission>,
-    #[serde(default)]
-    pub cluster_memory: Option<ClusterMemoryAdmission>,
-    #[serde(default)]
-    pub stmatrix: Option<StmatrixAdmission>,
-    #[serde(default)]
-    pub clc: Option<ClcAdmission>,
-    #[serde(default)]
-    pub wgmma_controls: Option<WgmmaControlAdmission>,
-    #[serde(default)]
-    pub tma: Option<TmaAdmission>,
-    #[serde(default)]
-    pub tcgen05: Option<Tcgen05Admission>,
-    #[serde(default)]
-    pub scalar_math: Option<ScalarMathAdmission>,
-}
-
-/// Compact admission for unary scalar floating-point math operations.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ScalarMathAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<ScalarMathAdmissionVariant>,
-}
-
-/// One reviewed scalar math variant.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ScalarMathAdmissionVariant {
-    pub abi_id: String,
-    #[serde(default)]
-    pub libnvvm_evidence_profile: Option<String>,
-    pub format: ScalarMathFormat,
-    pub operation: ScalarMathOperation,
-    pub precision: ScalarMathPrecision,
-    pub subnormal: ScalarMathSubnormal,
-}
-
-/// Compact admission for the four existing `stmatrix` stores.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct StmatrixAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<StmatrixAdmissionVariant>,
-}
-
-/// One reviewed `stmatrix` multiplicity and layout.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct StmatrixAdmissionVariant {
-    pub abi_id: String,
-    pub multiplicity: StmatrixMultiplicity,
-    pub layout: StmatrixLayout,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum StmatrixMultiplicity {
-    X2,
-    X4,
-}
-
-impl StmatrixMultiplicity {
-    pub const fn register_count(self) -> usize {
-        match self {
-            Self::X2 => 2,
-            Self::X4 => 4,
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum StmatrixLayout {
-    Normal,
-    Transposed,
-}
-
-/// Compact admission for the remaining handwritten mbarrier operations.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct MbarrierExtendedAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<MbarrierExtendedAdmissionVariant>,
-}
-
-/// One reviewed extended-mbarrier operation and its reserved ABI ID.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct MbarrierExtendedAdmissionVariant {
-    pub abi_id: String,
-    pub operation: MbarrierExtendedOperation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum MbarrierExtendedOperation {
-    ArriveExpectTxCta,
-    ArriveExpectTxCluster,
-    ArriveRemoteCluster,
-    TryWaitTokenCta,
-    TryWaitParityCta,
-    TryWaitParityCluster,
-    FenceProxyAsyncSharedCta,
-    FenceMbarrierInitReleaseCluster,
-    FenceProxyAsyncGenericReleaseSharedCtaCluster,
-    FenceProxyAsyncGenericAcquireSharedClusterCluster,
-    Nanosleep,
-}
-
-/// Compact admission for Hopper cluster special registers.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ClusterSregAdmission {
-    pub axes: Vec<String>,
-    pub xyz_product_count: usize,
-    pub record_count: usize,
-}
-
-/// Compact admission for the six cluster-barrier instructions.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ClusterBarrierAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<ClusterBarrierAdmissionVariant>,
-}
-
-/// One reviewed cluster-barrier spelling.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ClusterBarrierAdmissionVariant {
-    pub abi_id: String,
-    pub mode: ClusterBarrierMode,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ClusterBarrierMode {
-    Arrive,
-    ArriveAligned,
-    ArriveRelaxed,
-    ArriveRelaxedAligned,
-    Wait,
-    WaitAligned,
-}
-
-/// Closed semantics for one cluster-barrier spelling.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ClusterBarrier {
-    pub mode: ClusterBarrierMode,
-    pub ordering: ClusterBarrierOrdering,
-    pub aligned: bool,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ClusterBarrierOrdering {
-    Release,
-    Relaxed,
-    Acquire,
-}
-
-/// Compact admission for cluster address mapping and remote shared reads.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ClusterMemoryAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<ClusterMemoryAdmissionVariant>,
-}
-
-/// One reviewed cluster-memory operation and its reserved ABI ID.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ClusterMemoryAdmissionVariant {
-    pub abi_id: String,
-    pub operation: ClusterMemoryOperation,
-}
-
-/// Compact admission for the three WGMMA control instructions.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct WgmmaControlAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<WgmmaControlAdmissionVariant>,
-}
-
-/// One reviewed WGMMA control operation.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct WgmmaControlAdmissionVariant {
-    pub abi_id: String,
-    pub mode: WgmmaControlMode,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ClusterMemoryOperation {
-    MapSharedRank,
-    ReadU32,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WgmmaControlMode {
-    Fence,
-    CommitGroup,
-    WaitGroup,
-}
-
-/// Closed semantics for one WGMMA control operation.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct WgmmaControl {
-    pub mode: WgmmaControlMode,
-    pub adapter: WgmmaControlAdapter,
-    pub participation: WgmmaControlParticipation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WgmmaControlAdapter {
-    NoArguments,
-    ConstGenericU32ToI64Immediate,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WgmmaControlParticipation {
-    WarpgroupAllThreadsSameInstruction,
-}
-
-/// Compact admission for the reviewed non-launch special-register reads.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct SpecialRegisterAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    pub registers: Vec<SpecialRegisterKind>,
-    pub product_count: usize,
-}
-
-/// Compact admission for PTX debug controls.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct DebugControlAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    pub operations: Vec<DebugControlOperation>,
-    /// Filled only when this pending shard is aggregated.
-    #[serde(default)]
-    pub abi_ids: Vec<String>,
-}
-
-/// Compact admission for the three CUDA thread fences.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ThreadfenceAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<ThreadfenceAdmissionVariant>,
-}
-
-/// One reviewed thread-fence scope.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ThreadfenceAdmissionVariant {
-    pub abi_id: String,
-    pub scope: ThreadfenceScope,
-}
-
-/// Scope encoded by a PTX `membar` instruction.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ThreadfenceScope {
-    Cta,
-    Device,
-    System,
-}
-
-/// Compact admission for Cluster Launch Control.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ClcAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<ClcAdmissionVariant>,
-}
-
-/// One reviewed Cluster Launch Control operation.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ClcAdmissionVariant {
-    pub abi_id: String,
-    pub operation: ClcOperation,
-}
-
-/// Compact admission for the existing TMA copy and group operations.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct TmaAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    #[serde(default)]
-    pub reduce_llvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub reduce_libnvvm_evidence_profile: Option<String>,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<TmaAdmissionVariant>,
-    #[serde(rename = "reduce_variant", default)]
-    pub reduce_variants: Vec<TmaReductionAdmissionVariant>,
-}
-
-/// One reviewed TMA operation and its reserved ABI ID.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct TmaAdmissionVariant {
-    pub abi_id: String,
-    pub operation: TmaOperation,
-}
-
-/// One reviewed tensor-reduction operation and its reserved ABI ID.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct TmaReductionAdmissionVariant {
-    pub abi_id: String,
-    pub operation: TmaReductionOperation,
-    pub load_mode: TmaReductionLoadMode,
-    pub dimensions: u8,
-}
-
-/// Compact admission for the existing Tensor Core Generation 5 operations.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05Admission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    #[serde(default)]
-    pub cp_llvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub cp_libnvvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub ld_llvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub ld_libnvvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub st_llvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub st_libnvvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub offset_llvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub offset_libnvvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub control_llvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub control_libnvvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub mma_llvm_evidence_profile: Option<String>,
-    #[serde(default)]
-    pub mma_libnvvm_evidence_profile: Option<String>,
-    #[serde(rename = "mma_llvm_target_contract", default)]
-    pub mma_llvm_target_contracts: Vec<TargetContract>,
-    #[serde(rename = "mma_libnvvm_target_contract", default)]
-    pub mma_libnvvm_target_contracts: Vec<TargetContract>,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<Tcgen05AdmissionVariant>,
-    #[serde(rename = "cp_variant", default)]
-    pub cp_variants: Vec<Tcgen05CpAdmissionVariant>,
-    #[serde(rename = "ld_variant", default)]
-    pub ld_variants: Vec<Tcgen05LdAdmissionVariant>,
-    #[serde(rename = "st_variant", default)]
-    pub st_variants: Vec<Tcgen05StAdmissionVariant>,
-    #[serde(rename = "ld_offset_variant", default)]
-    pub ld_offset_variants: Vec<Tcgen05LdAdmissionVariant>,
-    #[serde(rename = "st_offset_variant", default)]
-    pub st_offset_variants: Vec<Tcgen05StAdmissionVariant>,
-    #[serde(rename = "mma_variant", default)]
-    pub mma_variants: Vec<Tcgen05MmaAdmissionVariant>,
-}
-
-/// One reviewed tcgen05 operation and its reserved ABI ID.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05AdmissionVariant {
-    pub abi_id: String,
-    pub operation: Tcgen05Operation,
-}
-
-/// One reviewed tcgen05 copy member and CTA group.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05CpAdmissionVariant {
-    pub abi_id: String,
-    pub member: Tcgen05CpMember,
-    pub group: Tcgen05CpGroup,
-}
-
-/// One reviewed tcgen05 load shape, repetition, and packing mode.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05LdAdmissionVariant {
-    pub abi_id: String,
-    pub shape: Tcgen05LdShape,
-    pub multiplicity: Tcgen05LdMultiplicity,
-    pub pack16: bool,
-}
-
-/// One reviewed tcgen05 store shape, repetition, and unpacking mode.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05StAdmissionVariant {
-    pub abi_id: String,
-    pub shape: Tcgen05LdShape,
-    pub multiplicity: Tcgen05LdMultiplicity,
-    pub unpack16: bool,
-}
-
-/// One reviewed tcgen05 MMA source form or compatibility alias.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05MmaAdmissionVariant {
-    pub abi_id: String,
-    pub form: Tcgen05MmaForm,
-    #[serde(default)]
-    pub alias: Option<Tcgen05MmaAlias>,
-}
-
-/// Compact admission for the closed `prmt` family.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct PrmtAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<PrmtAdmissionVariant>,
-}
-
-/// One reviewed member of the `prmt` family.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct PrmtAdmissionVariant {
-    pub abi_id: String,
-    pub mode: PrmtMode,
-}
-
-/// Compact admission for the closed scalar-f32 to packed-FP8 family.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct PackedConversionFp8Admission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    pub destination_formats: Vec<PackedConversionDestinationFormat>,
-    pub saturations: Vec<PackedConversionSaturation>,
-    pub product_count: usize,
-}
-
-/// Compact admission for packed FP8 conversions whose other side is `f16x2`.
-///
-/// Covers both directions: packing `f16x2` down to `e4m3x2`/`e5m2x2`, and
-/// unpacking those back to `f16x2`. Both are single-operand conversions, unlike
-/// the scalar-`f32` pair admitted by [`PackedConversionFp8Admission`].
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct PackedConversionFp8F16x2Admission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    pub fp8_formats: Vec<PackedConversionFp8Format>,
-    pub directions: Vec<PackedConversionFp8Direction>,
-    pub relu_variants: bool,
-    pub product_count: usize,
-}
-
-/// The FP8 side of an `f16x2` conversion pair.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedConversionFp8Format {
-    E4m3x2,
-    E5m2x2,
-}
-
-/// Which way an FP8/`f16x2` conversion runs.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedConversionFp8Direction {
-    /// `f16x2` narrowed to packed FP8, always saturating to finite.
-    Pack,
-    /// Packed FP8 widened back to `f16x2`, which is always exact.
-    Unpack,
-}
-
-/// Compact admission for scalar F32-to-TF32 conversions.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ScalarConversionAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<ScalarConversionAdmissionVariant>,
-}
-
-/// One reviewed scalar conversion variant.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ScalarConversionAdmissionVariant {
-    pub abi_id: String,
-    pub rounding: ScalarConversionRounding,
-    pub saturation: ScalarConversionSaturation,
-}
-
-/// Compact admission for scalar floating-point arithmetic.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ScalarArithmeticAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<ScalarArithmeticAdmissionVariant>,
-}
-
-/// One reviewed scalar arithmetic variant.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ScalarArithmeticAdmissionVariant {
-    pub abi_id: String,
-    pub format: ScalarArithmeticFormat,
-    pub operation: ScalarArithmeticOperation,
-    pub rounding: ScalarArithmeticRounding,
-    pub subnormal: ScalarArithmeticSubnormal,
-    pub saturation: ScalarArithmeticSaturation,
-}
-
-/// Compact admission for the exact extended floating-point min/max family.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ExtendedMinMaxAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<ExtendedMinMaxAdmissionVariant>,
-}
-
-/// One reviewed extended min/max variant.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ExtendedMinMaxAdmissionVariant {
-    pub abi_id: String,
-    pub format: ExtendedMinMaxFormat,
-    pub operation: ExtendedMinMaxOperation,
-    pub subnormal: ExtendedMinMaxSubnormal,
-    pub nan: ExtendedMinMaxNan,
-    pub xorsign_abs: bool,
-}
-
-/// Compact admission for a closed dense integer register-MMA family.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct RegisterMmaIntegerAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<RegisterMmaIntegerVariant>,
-}
-
-/// One reviewed member of a dense integer register-MMA family.
-#[derive(Debug, Clone, Copy, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct RegisterMmaIntegerVariant {
-    pub shape: RegisterMmaShape,
-    pub a_element: RegisterMmaElement,
-    pub b_element: RegisterMmaElement,
-    pub overflow: RegisterMmaOverflow,
-}
-
-/// Compact admission for the closed dense binary register-MMA family.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct RegisterMmaBinaryAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    #[serde(rename = "variant")]
-    pub variants: Vec<RegisterMmaBinaryVariant>,
-}
-
-/// One reviewed member of the dense binary register-MMA family.
-#[derive(Debug, Clone, Copy, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct RegisterMmaBinaryVariant {
-    pub shape: RegisterMmaShape,
-    pub operation: RegisterMmaOperation,
-}
-
-/// Compact admission for one dense Blackwell `kind::f8f6f4` matrix.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct RegisterMmaF8F6F4Admission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    /// Legacy shard metadata retained only so older overlays continue to parse.
-    /// ABI identity is bound from the append-only ledger by catalog ID.
-    #[serde(default, rename = "first_abi_id")]
-    pub _legacy_first_abi_id: Option<String>,
-    pub a_elements: Vec<RegisterMmaElement>,
-    pub b_elements: Vec<RegisterMmaElement>,
-    pub product_count: usize,
-    pub targets: Vec<String>,
-}
-
-/// Compact admission for the standard FP8 register-MMA family.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct RegisterMmaFp8Admission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    /// Legacy shard metadata retained only so older overlays continue to parse.
-    /// ABI identity is bound from the append-only ledger by catalog ID.
-    #[serde(default, rename = "first_abi_id")]
-    pub _legacy_first_abi_id: Option<String>,
-    pub shapes: Vec<RegisterMmaShape>,
-    pub accumulators: Vec<RegisterMmaAccumulator>,
-    pub a_elements: Vec<RegisterMmaElement>,
-    pub b_elements: Vec<RegisterMmaElement>,
-    pub product_count: usize,
-}
-
-/// Compact admission for the reviewed Ampere floating-point MMA forms.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct RegisterMmaAmpereFloatAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    /// Legacy shard metadata retained only so older overlays continue to parse.
-    /// ABI identity is bound from the append-only ledger by catalog ID.
-    #[serde(default, rename = "first_abi_id")]
-    pub _legacy_first_abi_id: Option<String>,
-    pub product_count: usize,
-    #[serde(rename = "variant")]
-    pub variants: Vec<RegisterMmaAmpereFloatVariant>,
-}
-
-/// One reviewed Ampere floating-point MMA form.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct RegisterMmaAmpereFloatVariant {
-    pub shape: RegisterMmaShape,
-    pub accumulator: RegisterMmaAccumulator,
-    pub element: RegisterMmaElement,
-}
-
-/// Compact admission for a sparse integer register-MMA family.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct SparseMmaIntegerAdmission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    pub metadata: SparseMmaMetadata,
-    #[serde(rename = "variant")]
-    pub variants: Vec<SparseMmaIntegerVariant>,
-}
-
-/// One reviewed member of a sparse integer register-MMA family.
-#[derive(Debug, Clone, Copy, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct SparseMmaIntegerVariant {
-    pub shape: SparseMmaShape,
-    pub a_element: SparseMmaElement,
-    pub b_element: SparseMmaElement,
-    pub overflow: SparseMmaOverflow,
-}
-
-/// Compact admission for ordered sparse `kind::f8f6f4` F32 MMA.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct SparseMmaF8F6F4Admission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    pub a_elements: Vec<SparseMmaElement>,
-    pub b_elements: Vec<SparseMmaElement>,
-    pub product_count: usize,
-}
-
-/// Compact admission for ordered sparse `kind::f8f6f4` packed-F16 MMA.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct SparseMmaF8F6F4F16Admission {
-    pub llvm_evidence_profile: String,
-    pub libnvvm_evidence_profile: String,
-    pub runtime_validation: RuntimeValidation,
-    /// Legacy shard metadata retained only so older overlays continue to parse.
-    /// ABI identity is bound from the append-only ledger by catalog ID.
-    #[serde(default, rename = "first_abi_id")]
-    pub _legacy_first_abi_id: Option<String>,
-    pub a_elements: Vec<SparseMmaElement>,
-    pub b_elements: Vec<SparseMmaElement>,
-    pub product_count: usize,
-}
-
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct OverlayIntrinsic {
-    pub id: String,
-    pub abi_id: String,
-    pub operation_key: String,
-    pub family: String,
-    /// Imported LLVM records use the legacy `source_record` field below.
-    /// PTX-native records must instead carry an explicit tagged source.
-    #[serde(default)]
-    pub source: Option<IntrinsicSource>,
-    #[serde(default)]
-    pub source_record: Option<String>,
-    pub rust_module: String,
-    pub rust_name: String,
-    #[serde(default)]
-    pub rust_arguments: Vec<String>,
-    pub rust_result: String,
-    pub safe: bool,
-    #[serde(default)]
-    pub must_use: bool,
-    pub safe_allowlist_reason: Option<String>,
-    pub public_rust_path: String,
-    #[serde(default)]
-    pub compatibility_rust_paths: Vec<String>,
-    pub dialect_op_type: String,
-    pub dialect_op_name: String,
-    #[serde(default)]
-    pub dialect_operands: Vec<String>,
-    #[serde(default)]
-    pub dialect_results: Vec<String>,
-    #[serde(default)]
-    pub llvm_symbol: Option<String>,
-    #[serde(default)]
-    pub resolved_llvm_symbol: Option<String>,
-    #[serde(default)]
-    pub llvm_arguments: Vec<String>,
-    #[serde(default)]
-    pub llvm_results: Vec<String>,
-    pub pure: bool,
-    pub memory: String,
-    pub convergent: bool,
-    pub execution_scope: String,
-    pub minimum_ptx: String,
-    #[serde(default)]
-    pub minimum_sm: Option<String>,
-    pub ptx_result: String,
-    pub targets: String,
-    pub ptx_isa_version: String,
-    pub ptx_isa_section: String,
-    pub ptx_isa_url: String,
-    pub lowering: String,
-    #[serde(default)]
-    pub backend_lowerings: Vec<OverlayBackendLowering>,
-    #[serde(default)]
-    pub packed_atomic: Option<PackedAtomic>,
-    #[serde(default)]
-    pub redux: Option<Redux>,
-    #[serde(default)]
-    pub vote: Option<Vote>,
-    #[serde(default)]
-    pub active_mask: Option<ActiveMask>,
-    #[serde(default)]
-    pub warp_match: Option<WarpMatch>,
-    #[serde(default)]
-    pub warp_barrier: Option<WarpBarrier>,
-    #[serde(default)]
-    pub warp_shuffle: Option<WarpShuffle>,
-    #[serde(default)]
-    pub dot_product: Option<DotProduct>,
-    #[serde(default)]
-    pub packed_alu: Option<PackedAlu>,
-    #[serde(default)]
-    pub integer_minmax: Option<IntegerMinMax>,
-    #[serde(default)]
-    pub packed_conversion: Option<PackedConversion>,
-    #[serde(default)]
-    pub scalar_conversion: Option<ScalarConversion>,
-    #[serde(default)]
-    pub scalar_arithmetic: Option<ScalarArithmetic>,
-    #[serde(default)]
-    pub scalar_math: Option<ScalarMath>,
-    #[serde(default)]
-    pub extended_minmax: Option<ExtendedMinMax>,
-    #[serde(default)]
-    pub cp_async_copy: Option<CpAsyncCopy>,
-    #[serde(default)]
-    pub cp_async_control: Option<CpAsyncControl>,
-    #[serde(default)]
-    pub cp_async_mbarrier: Option<CpAsyncMbarrier>,
-    #[serde(default)]
-    pub mbarrier_basic: Option<MbarrierBasic>,
-    #[serde(default)]
-    pub movmatrix: Option<Movmatrix>,
-    #[serde(default)]
-    pub mbarrier_extended: Option<MbarrierExtended>,
-    #[serde(default)]
-    pub register_mma: Option<RegisterMma>,
-    #[serde(default)]
-    pub sparse_mma: Option<SparseMma>,
-    #[serde(default)]
-    pub prmt: Option<Prmt>,
-    #[serde(default)]
-    pub cluster_barrier: Option<ClusterBarrier>,
-    #[serde(default)]
-    pub wgmma_control: Option<WgmmaControl>,
-    #[serde(default)]
-    pub special_register: Option<SpecialRegister>,
-    #[serde(default)]
-    pub debug_control: Option<DebugControl>,
-    #[serde(default)]
-    pub cluster_memory: Option<ClusterMemory>,
-    #[serde(default)]
-    pub clc: Option<Clc>,
-    #[serde(default)]
-    pub tma: Option<Tma>,
-    #[serde(default)]
-    pub tcgen05: Option<Tcgen05>,
-    #[serde(default)]
-    pub ldmatrix_variant: Option<LdmatrixVariant>,
-    #[serde(default)]
-    pub ldmatrix_safety: Option<LdmatrixSafety>,
-    #[serde(default)]
-    pub ldmatrix_adapter: Option<LdmatrixAdapter>,
-    #[serde(default)]
-    pub selected_address_space: Option<ImportedAddressSpace>,
-    pub expected_ptx: InstructionPattern,
-    pub summary: String,
-}
-
-/// Closed semantic contract for byte permutation.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Prmt {
-    pub mode: PrmtMode,
-    pub adapter: PrmtAdapter,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PrmtMode {
-    Generic,
-    F4e,
-    B4e,
-    Rc8,
-    Ecl,
-    Ecr,
-    Rc16,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PrmtAdapter {
-    DirectThreeOperands,
-    InsertZeroSecondSource,
-}
-
-/// Closed semantic and lowering contract for one special-register read.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct SpecialRegister {
-    pub register: SpecialRegisterKind,
-    pub observation: SpecialRegisterObservation,
-    pub result_width: SpecialRegisterWidth,
-    pub ptx_type: SpecialRegisterPtxType,
-    pub output_constraint: SpecialRegisterOutputConstraint,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub llvm_exclusion: Option<SpecialRegisterLlvmExclusion>,
-}
-
-/// Closed semantic contract for PTX debug controls.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct DebugControl {
-    pub operation: DebugControlOperation,
-    pub adapter: DebugControlAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-/// Closed contract for cluster address mapping and remote shared reads.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ClusterMemory {
-    pub operation: ClusterMemoryOperation,
-    pub adapter: ClusterMemoryAdapter,
-    pub source_contract: ClusterMemorySourceContract,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ClusterMemoryAdapter {
-    GenericConstAndMutPointerRankToSamePointer,
-    ConstU32PointerRankToU32,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ClusterMemorySourceContract {
-    LlvmMapaSharedClusterAs7IdentityInlinePtx,
-    PtxNativeMapaThenWeakClusterLoad,
-}
-
-/// Closed semantic contract for Cluster Launch Control.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Clc {
-    pub operation: ClcOperation,
-    pub adapter: ClcAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ClcOperation {
-    TryCancel,
-    TryCancelMulticast,
-    QueryIsCanceled,
-    QueryGetFirstCtaidX,
-    QueryGetFirstCtaidY,
-    QueryGetFirstCtaidZ,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ClcAdapter {
-    GenericPointersToShared,
-    PairU64ToI128BoolToU32,
-    PairU64ToI128U32,
-}
-
-/// Closed semantic contract for a TMA operation.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tma {
-    pub operation: TmaOperation,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub reduction: Option<TmaReduction>,
-    pub adapter: TmaAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-impl Tma {
-    pub const fn dimensions(&self) -> Option<usize> {
-        match &self.reduction {
-            Some(reduction) => Some(reduction.dimensions as usize),
-            None => self.operation.dimensions(),
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum TmaOperation {
-    G2sTile1d,
-    G2sTile2d,
-    G2sTile2dMulticast,
-    G2sTile2dMulticastCg2,
-    G2sTile3d,
-    G2sTile4d,
-    G2sTile5d,
-    S2gTile1d,
-    S2gTile2d,
-    S2gTile3d,
-    S2gTile4d,
-    S2gTile5d,
-    Reduce,
-    CommitGroup,
-    WaitGroup,
-    WaitGroupRead,
-    PrefetchTensorMap,
-    PrefetchTile1d,
-    PrefetchTile2d,
-    PrefetchTile3d,
-    PrefetchTile4d,
-    PrefetchTile5d,
-    #[serde(rename = "prefetch_tile_gather4_2d")]
-    PrefetchTileGather4TwoDimensional,
-    PrefetchTile1dCacheHint,
-    PrefetchTile2dCacheHint,
-    PrefetchTile3dCacheHint,
-    PrefetchTile4dCacheHint,
-    PrefetchTile5dCacheHint,
-    #[serde(rename = "prefetch_tile_gather4_2d_cache_hint")]
-    PrefetchTileGather4TwoDimensionalCacheHint,
-    ReplaceBoxDim,
-    ReplaceElementStride,
-    ReplaceElementType,
-    ReplaceFillMode,
-    ReplaceGlobalAddress,
-    ReplaceGlobalDim,
-    ReplaceGlobalStride,
-    ReplaceInterleaveLayout,
-    ReplaceRank,
-    ReplaceSwizzleAtomicity,
-    ReplaceSwizzleMode,
-    FenceProxyTensorMapAcquireCluster,
-    FenceProxyTensorMapAcquireCta,
-    FenceProxyTensorMapAcquireGpu,
-    FenceProxyTensorMapAcquireSystem,
-    FenceProxyTensorMapReleaseCluster,
-    FenceProxyTensorMapReleaseCta,
-    FenceProxyTensorMapReleaseGpu,
-    FenceProxyTensorMapReleaseSystem,
-}
-
-impl TmaOperation {
-    pub const fn dimensions(self) -> Option<usize> {
-        match self {
-            Self::G2sTile1d | Self::S2gTile1d => Some(1),
-            Self::G2sTile2d
-            | Self::G2sTile2dMulticast
-            | Self::G2sTile2dMulticastCg2
-            | Self::S2gTile2d => Some(2),
-            Self::G2sTile3d | Self::S2gTile3d => Some(3),
-            Self::G2sTile4d | Self::S2gTile4d => Some(4),
-            Self::G2sTile5d | Self::S2gTile5d => Some(5),
-            Self::Reduce
-            | Self::CommitGroup
-            | Self::WaitGroup
-            | Self::WaitGroupRead
-            | Self::PrefetchTensorMap
-            | Self::PrefetchTile1d
-            | Self::PrefetchTile2d
-            | Self::PrefetchTile3d
-            | Self::PrefetchTile4d
-            | Self::PrefetchTile5d
-            | Self::PrefetchTileGather4TwoDimensional
-            | Self::PrefetchTile1dCacheHint
-            | Self::PrefetchTile2dCacheHint
-            | Self::PrefetchTile3dCacheHint
-            | Self::PrefetchTile4dCacheHint
-            | Self::PrefetchTile5dCacheHint
-            | Self::PrefetchTileGather4TwoDimensionalCacheHint
-            | Self::ReplaceBoxDim
-            | Self::ReplaceElementStride
-            | Self::ReplaceElementType
-            | Self::ReplaceFillMode
-            | Self::ReplaceGlobalAddress
-            | Self::ReplaceGlobalDim
-            | Self::ReplaceGlobalStride
-            | Self::ReplaceInterleaveLayout
-            | Self::ReplaceRank
-            | Self::ReplaceSwizzleAtomicity
-            | Self::ReplaceSwizzleMode
-            | Self::FenceProxyTensorMapAcquireCluster
-            | Self::FenceProxyTensorMapAcquireCta
-            | Self::FenceProxyTensorMapAcquireGpu
-            | Self::FenceProxyTensorMapAcquireSystem
-            | Self::FenceProxyTensorMapReleaseCluster
-            | Self::FenceProxyTensorMapReleaseCta
-            | Self::FenceProxyTensorMapReleaseGpu
-            | Self::FenceProxyTensorMapReleaseSystem => None,
-        }
-    }
-
-    pub const fn prefetch_coordinate_count(self) -> Option<usize> {
-        match self {
-            Self::PrefetchTile1d | Self::PrefetchTile1dCacheHint => Some(1),
-            Self::PrefetchTile2d | Self::PrefetchTile2dCacheHint => Some(2),
-            Self::PrefetchTile3d | Self::PrefetchTile3dCacheHint => Some(3),
-            Self::PrefetchTile4d | Self::PrefetchTile4dCacheHint => Some(4),
-            Self::PrefetchTile5d
-            | Self::PrefetchTile5dCacheHint
-            | Self::PrefetchTileGather4TwoDimensional
-            | Self::PrefetchTileGather4TwoDimensionalCacheHint => Some(5),
-            _ => None,
-        }
-    }
-
-    pub const fn uses_prefetch_cache_hint(self) -> bool {
-        matches!(
-            self,
-            Self::PrefetchTile1dCacheHint
-                | Self::PrefetchTile2dCacheHint
-                | Self::PrefetchTile3dCacheHint
-                | Self::PrefetchTile4dCacheHint
-                | Self::PrefetchTile5dCacheHint
-                | Self::PrefetchTileGather4TwoDimensionalCacheHint
-        )
-    }
-}
-
-/// Closed identity for one TMA tensor-reduction operation.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct TmaReduction {
-    pub operation: TmaReductionOperation,
-    pub load_mode: TmaReductionLoadMode,
-    pub dimensions: u8,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum TmaReductionOperation {
-    Add,
-    And,
-    Dec,
-    Inc,
-    Max,
-    Min,
-    Or,
-    Xor,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum TmaReductionLoadMode {
-    Tile,
-    Im2col,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum TmaAdapter {
-    G2sPointersCoordinatesBarrierInjectDefaults,
-    G2sPointersCoordinatesBarrierMaskInjectDefaults,
-    S2gPointersCoordinatesInjectDefaults,
-    ReductionPointersCoordinatesInjectDefaults,
-    NoOperands,
-    CompileTimeConstantMaxPending,
-    DescriptorPointer,
-    DescriptorCoordinatesInjectDefaults,
-    DescriptorCoordinatesCacheHintInjectFlag,
-    DescriptorAndAddressPointers,
-    DescriptorOrdinalAndU32,
-    DescriptorOrdinalAndU64,
-    DescriptorAndImmediateU32,
-    DescriptorAndRuntimeU32,
-    DescriptorPointerInjectBytes,
-}
-
-/// Closed semantic contract for one tcgen05 operation.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05 {
-    pub operation: Tcgen05Operation,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub cp: Option<Tcgen05Cp>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub ld: Option<Tcgen05Ld>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub st: Option<Tcgen05St>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub mma: Option<Tcgen05Mma>,
-    pub adapter: Tcgen05Adapter,
-    pub source_contract: Tcgen05SourceContract,
-    pub runtime_validation: RuntimeValidation,
-}
-
-/// Closed identity and selector contract for one tcgen05 MMA API.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05Mma {
-    pub form: Tcgen05MmaForm,
-    pub selector_layout: Tcgen05MmaSelectorLayout,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub fixed_selectors: Option<Tcgen05MmaFixedSelectors>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub alias: Option<Tcgen05MmaAlias>,
-    pub llvm_target: CatalogTargetRequirement,
-    pub libnvvm_target: CatalogTargetRequirement,
-}
-
-/// The 14 LLVM source forms covered by the first tcgen05 MMA batch.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum Tcgen05MmaForm {
-    Shared,
-    Tensor,
-    TensorAshift,
-    SpShared,
-    SpTensor,
-    SpTensorAshift,
-    WsShared,
-    WsSharedZeroColMask,
-    WsSpShared,
-    WsSpSharedZeroColMask,
-    WsSpTensor,
-    WsSpTensorZeroColMask,
-    WsTensor,
-    WsTensorZeroColMask,
-}
-
-/// Immediate arguments that select one imported tcgen05 MMA spelling.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(tag = "kind", rename_all = "snake_case")]
-pub enum Tcgen05MmaSelectorLayout {
-    Base {
-        kind_argument: u8,
-        cta_group_argument: u8,
-        collector_a_argument: u8,
-        collector_a_upper_exclusive: u8,
-    },
-    WarpSpecialized {
-        kind_argument: u8,
-        b_buffer_argument: u8,
-        b_usage_argument: u8,
-    },
-}
-
-/// A fixed warp-specialized selector tuple used by compatibility aliases.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05MmaFixedSelectors {
-    pub kind: Tcgen05MmaKind,
-    pub b_buffer: u8,
-    pub b_usage: Tcgen05MmaBUsage,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum Tcgen05MmaKind {
-    F16,
-    Tf32,
-    F8f6f4,
-    I8,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum Tcgen05MmaBUsage {
-    Discard,
-    LastUse,
-    Fill,
-    Use,
-}
-
-impl Tcgen05MmaBUsage {
-    pub const fn selector_value(self) -> u8 {
-        match self {
-            Self::Discard => 0,
-            Self::LastUse => 1,
-            Self::Fill => 2,
-            Self::Use => 3,
-        }
-    }
-}
-
-/// Public names proposed by PR #346 for the generic f8f6f4 carrier.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum Tcgen05MmaAlias {
-    E4m3,
-    E5m2,
-    E2m3,
-    E3m2,
-    E2m1,
-}
-
-/// Closed identity for one tcgen05 shared-to-tensor-memory copy.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05Cp {
-    pub member: Tcgen05CpMember,
-    pub group: Tcgen05CpGroup,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-pub enum Tcgen05CpMember {
-    #[serde(rename = "128x128b_b4x16_p64")]
-    M128x128bB4x16P64,
-    #[serde(rename = "128x128b_b6x16_p32")]
-    M128x128bB6x16P32,
-    #[serde(rename = "128x128b")]
-    M128x128b,
-    #[serde(rename = "128x256b_b4x16_p64")]
-    M128x256bB4x16P64,
-    #[serde(rename = "128x256b_b6x16_p32")]
-    M128x256bB6x16P32,
-    #[serde(rename = "32x128b_warpx4_b4x16_p64")]
-    M32x128bWarpx4B4x16P64,
-    #[serde(rename = "32x128b_warpx4_b6x16_p32")]
-    M32x128bWarpx4B6x16P32,
-    #[serde(rename = "32x128b_warpx4")]
-    M32x128bWarpx4,
-    #[serde(rename = "4x256b_b4x16_p64")]
-    M4x256bB4x16P64,
-    #[serde(rename = "4x256b_b6x16_p32")]
-    M4x256bB6x16P32,
-    #[serde(rename = "4x256b")]
-    M4x256b,
-    #[serde(rename = "64x128b_warpx2_01_23_b4x16_p64")]
-    M64x128bWarpx2Pair0123B4x16P64,
-    #[serde(rename = "64x128b_warpx2_01_23_b6x16_p32")]
-    M64x128bWarpx2Pair0123B6x16P32,
-    #[serde(rename = "64x128b_warpx2_01_23")]
-    M64x128bWarpx2Pair0123,
-    #[serde(rename = "64x128b_warpx2_02_13_b4x16_p64")]
-    M64x128bWarpx2Pair0213B4x16P64,
-    #[serde(rename = "64x128b_warpx2_02_13_b6x16_p32")]
-    M64x128bWarpx2Pair0213B6x16P32,
-    #[serde(rename = "64x128b_warpx2_02_13")]
-    M64x128bWarpx2Pair0213,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum Tcgen05CpGroup {
-    Cg1,
-    Cg2,
-}
-
-/// Closed identity for one tcgen05 tensor-memory load.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05Ld {
-    pub shape: Tcgen05LdShape,
-    pub multiplicity: Tcgen05LdMultiplicity,
-    pub pack16: bool,
-}
-
-/// Closed identity for one tcgen05 tensor-memory store.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Tcgen05St {
-    pub shape: Tcgen05LdShape,
-    pub multiplicity: Tcgen05LdMultiplicity,
-    pub unpack16: bool,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-pub enum Tcgen05LdShape {
-    #[serde(rename = "16x32bx2")]
-    M16x32bx2,
-    #[serde(rename = "16x64b")]
-    M16x64b,
-    #[serde(rename = "16x128b")]
-    M16x128b,
-    #[serde(rename = "16x256b")]
-    M16x256b,
-    #[serde(rename = "32x32b")]
-    M32x32b,
-}
-
-impl Tcgen05LdShape {
-    pub const fn register_multiplier(self) -> usize {
-        match self {
-            Self::M16x32bx2 | Self::M16x64b | Self::M32x32b => 1,
-            Self::M16x128b => 2,
-            Self::M16x256b => 4,
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum Tcgen05LdMultiplicity {
-    X1,
-    X2,
-    X4,
-    X8,
-    X16,
-    X32,
-    X64,
-    X128,
-}
-
-impl Tcgen05LdMultiplicity {
-    pub const fn count(self) -> usize {
-        match self {
-            Self::X1 => 1,
-            Self::X2 => 2,
-            Self::X4 => 4,
-            Self::X8 => 8,
-            Self::X16 => 16,
-            Self::X32 => 32,
-            Self::X64 => 64,
-            Self::X128 => 128,
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum Tcgen05Operation {
-    Alloc,
-    Dealloc,
-    RelinquishAllocPermit,
-    FenceBeforeThreadSync,
-    FenceAfterThreadSync,
-    Commit,
-    CommitSharedCluster,
-    MmaWsF16,
-    MmaF16,
-    MmaWsBf16,
-    MmaWsTf32,
-    CpSmemToTmem,
-    Ld16x256bX8Pure,
-    Ld16x256bPure,
-    LoadWait,
-    StoreWait,
-    AllocCg2,
-    DeallocCg2,
-    RelinquishAllocPermitCg2,
-    MmaF16Cg2,
-    CommitCg2,
-    CommitSharedClusterCg2,
-    CommitMulticastCg2,
-    CpSmemToTmemCg2,
-    Ld,
-    St,
-    CommitMulticast,
-    ShiftDown,
-    ShiftDownCg2,
-    Mma,
-}
-
-impl Tcgen05Operation {
-    pub const fn execution_scope(self) -> &'static str {
-        match self {
-            Self::Alloc
-            | Self::Dealloc
-            | Self::RelinquishAllocPermit
-            | Self::Ld16x256bX8Pure
-            | Self::Ld16x256bPure
-            | Self::LoadWait
-            | Self::StoreWait
-            | Self::AllocCg2
-            | Self::DeallocCg2
-            | Self::RelinquishAllocPermitCg2
-            | Self::Ld
-            | Self::St => "warp",
-            Self::FenceBeforeThreadSync
-            | Self::FenceAfterThreadSync
-            | Self::Commit
-            | Self::CommitSharedCluster
-            | Self::MmaWsF16
-            | Self::MmaF16
-            | Self::MmaWsBf16
-            | Self::MmaWsTf32
-            | Self::CpSmemToTmem
-            | Self::MmaF16Cg2
-            | Self::CommitCg2
-            | Self::CommitSharedClusterCg2
-            | Self::CommitMulticastCg2
-            | Self::CpSmemToTmemCg2
-            | Self::CommitMulticast
-            | Self::ShiftDown
-            | Self::ShiftDownCg2
-            | Self::Mma => "thread",
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum Tcgen05Adapter {
-    SharedPointerColumnsToVoid,
-    TmemAddressColumnsToVoid,
-    NoOperands,
-    BarrierPointerToVoid,
-    MmaWsDropLegacyADescriptor,
-    MmaInjectZeroDisableLanes,
-    TmemDescriptorToVoid,
-    TmemToF32x32,
-    TmemToF32x4,
-    BarrierPointerMaskToVoid,
-    TmemInjectPack16ToU32Registers,
-    TmemU32RegistersInjectUnpack16ToVoid,
-    TmemHalfSplitOffsetInjectPack16ToU32Registers,
-    TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid,
-    TmemAddressToVoid,
-    MmaDirectSelectors,
-    MmaWsFixedSelectorsDropLegacyADescriptor,
-}
-
-/// Relationship between the public operation and LLVM's NVPTX selection.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum Tcgen05SourceContract {
-    ExactTablegenSelection,
-    TablegenSelectionChangesPtx,
-    LlvmCustomLoweringWithoutSelection,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SpecialRegisterKind {
-    Clock,
-    Clock64,
-    Globaltimer,
-    Envreg1,
-    Envreg2,
-    Smid,
-    Nsmid,
-    Gridid,
-    Warpid,
-    Nwarpid,
-    DynamicSmemSize,
-    TotalSmemSize,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum DebugControlOperation {
-    Trap,
-    Breakpoint,
-    Pmevent,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SpecialRegisterObservation {
-    StablePure,
-    VolatileObservation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SpecialRegisterWidth {
-    B32,
-    B64,
-}
-
-impl SpecialRegisterWidth {
-    pub const fn bits(self) -> u32 {
-        match self {
-            Self::B32 => 32,
-            Self::B64 => 64,
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SpecialRegisterPtxType {
-    B32,
-    U32,
-    U64,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SpecialRegisterOutputConstraint {
-    Register32,
-    Register64,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct SpecialRegisterLlvmExclusion {
-    pub source_record: String,
-    pub llvm_symbol: String,
-    pub imported_result_width: SpecialRegisterWidth,
-    pub reason: SpecialRegisterLlvmExclusionReason,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SpecialRegisterLlvmExclusionReason {
-    ResultWidthMismatch,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum DebugControlAdapter {
-    Direct,
-    ConstGenericToImmediateU32,
-}
-
-/// Backend-specific lowering selected by reviewed evidence.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct OverlayBackendLowering {
-    pub backend: IntrinsicBackend,
-    pub mechanism: BackendLoweringMechanism,
-    pub evidence_profile: String,
-    /// Optional exact target alternatives for this backend route.
-    #[serde(default)]
-    pub targets: Option<String>,
-    /// Optional backend-profile floor. When absent, the intrinsic's native
-    /// target requirement is used.
-    #[serde(default)]
-    pub minimum_ptx: Option<String>,
-    #[serde(default)]
-    pub minimum_sm: Option<String>,
-}
-
-/// Provenance for a generated intrinsic. PTX-native operations deliberately
-/// have no invented LLVM TableGen record or LLVM intrinsic symbol.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(tag = "kind", rename_all = "snake_case", deny_unknown_fields)]
-pub enum IntrinsicSource {
-    LlvmImported { source_record: String },
-    PtxNative { instruction: String },
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum IntrinsicBackend {
-    LlvmNvptx,
-    LibNvvm,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum BackendLoweringMechanism {
-    TypedNvvm,
-    InlinePtx,
-}
-
-/// Closed identity for the small execution-control families that share a
-/// result-less MIR/dialect representation.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
-pub enum ExecutionControlOperation {
-    BarrierCtaSync,
-    BarrierCtaSyncAligned,
-    BarrierCtaArrive,
-    BarrierCtaArriveAligned,
-    GridDependencyLaunchDependents,
-    GridDependencyWait,
-    SetMaxNRegInc,
-    SetMaxNRegDec,
-}
-
-impl ExecutionControlOperation {
-    pub fn from_catalog_id(id: &str) -> Option<Self> {
-        Some(match id {
-            "barrier_cta_sync" => Self::BarrierCtaSync,
-            "barrier_cta_sync_aligned" => Self::BarrierCtaSyncAligned,
-            "barrier_cta_arrive" => Self::BarrierCtaArrive,
-            "barrier_cta_arrive_aligned" => Self::BarrierCtaArriveAligned,
-            "grid_dependency_launch_dependents" => Self::GridDependencyLaunchDependents,
-            "grid_dependency_wait" => Self::GridDependencyWait,
-            "setmaxnreg_inc" => Self::SetMaxNRegInc,
-            "setmaxnreg_dec" => Self::SetMaxNRegDec,
-            _ => return None,
-        })
-    }
-
-    pub const fn family(self) -> &'static str {
-        match self {
-            Self::BarrierCtaSync
-            | Self::BarrierCtaSyncAligned
-            | Self::BarrierCtaArrive
-            | Self::BarrierCtaArriveAligned => "counted_barrier",
-            Self::GridDependencyLaunchDependents | Self::GridDependencyWait => "grid_dependency",
-            Self::SetMaxNRegInc | Self::SetMaxNRegDec => "register_control",
-        }
-    }
-
-    pub const fn operand_count(self) -> usize {
-        match self {
-            Self::BarrierCtaSync
-            | Self::BarrierCtaSyncAligned
-            | Self::BarrierCtaArrive
-            | Self::BarrierCtaArriveAligned => 2,
-            Self::GridDependencyLaunchDependents | Self::GridDependencyWait => 0,
-            Self::SetMaxNRegInc | Self::SetMaxNRegDec => 1,
-        }
-    }
-
-    pub const fn requires_immediate_operands(self) -> bool {
-        matches!(self, Self::SetMaxNRegInc | Self::SetMaxNRegDec)
-    }
-}
-
-/// Closed semantic identity for the generated `ldmatrix` family.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct LdmatrixVariant {
-    pub shape: LdmatrixShape,
-    pub multiplicity: LdmatrixMultiplicity,
-    pub layout: LdmatrixLayout,
-    pub element: LdmatrixElement,
-    pub state_space: LdmatrixStateSpace,
-}
-
-impl LdmatrixVariant {
-    pub const fn register_count(&self) -> usize {
-        let matrices = self.multiplicity.register_count();
-        match self.shape {
-            LdmatrixShape::M8n8 | LdmatrixShape::M8n16 => matrices,
-            LdmatrixShape::M16n16 => matrices * 2,
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum LdmatrixShape {
-    M8n8,
-    M8n16,
-    M16n16,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum LdmatrixMultiplicity {
-    X1,
-    X2,
-    X4,
-}
-
-impl LdmatrixMultiplicity {
-    pub const fn register_count(self) -> usize {
-        match self {
-            Self::X1 => 1,
-            Self::X2 => 2,
-            Self::X4 => 4,
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum LdmatrixLayout {
-    Normal,
-    Transposed,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum LdmatrixElement {
-    B16,
-    B8,
-    B8x16B4x16P64,
-    B8x16B6x16P32,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum LdmatrixStateSpace {
-    Shared,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct LdmatrixSafety {
-    pub participation: LdmatrixParticipation,
-    pub address_contract: LdmatrixAddressContract,
-    pub memory_order: LdmatrixMemoryOrder,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum LdmatrixParticipation {
-    AllWarpLanesSameInstruction,
-    AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum LdmatrixAddressContract {
-    WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadableWithSm75Replication,
-    WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadable,
-    WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedThirtyTwoBytesReadable,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum LdmatrixMemoryOrder {
-    Weak,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RuntimeValidation {
-    Unexecuted,
-    Executed,
-}
-
-/// Closed contract for the in-register warp matrix transpose.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Movmatrix {
-    pub participation: MovmatrixParticipation,
-    pub adapter: MovmatrixAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum MovmatrixParticipation {
-    AllWarpLanesSameInstructionNoExitedLanes,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum MovmatrixAdapter {
-    PackedB16x2U32ToPackedB16x2U32,
-}
-
-/// Closed contract for register-only warp-level `mma.sync` operations.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct RegisterMma {
-    pub shape: RegisterMmaShape,
-    pub operation: RegisterMmaOperation,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub kind: Option<RegisterMmaKind>,
-    pub accumulator: RegisterMmaAccumulator,
-    pub a_element: RegisterMmaElement,
-    pub b_element: RegisterMmaElement,
-    pub a_layout: RegisterMmaLayout,
-    pub b_layout: RegisterMmaLayout,
-    pub overflow: RegisterMmaOverflow,
-    pub participation: RegisterMmaParticipation,
-    pub adapter: RegisterMmaAdapter,
-    pub compatibility_source: RegisterMmaCompatibilitySource,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RegisterMmaKind {
-    Standard,
-    F8f6f4,
-    Mxf8f6f4,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RegisterMmaShape {
-    M8n8k4,
-    M8n8k16,
-    M8n8k32,
-    M16n8k4,
-    M16n8k8,
-    M16n8k16,
-    M16n8k32,
-    M16n8k64,
-    M8n8k128,
-    M16n8k128,
-    M16n8k256,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RegisterMmaOperation {
-    Multiply,
-    AndPopc,
-    XorPopc,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RegisterMmaAccumulator {
-    F16,
-    F32,
-    F64,
-    S32,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RegisterMmaElement {
-    B1,
-    Bf16,
-    E2m1,
-    E2m3,
-    E3m2,
-    E4m3,
-    E5m2,
-    F16,
-    Tf32,
-    F64,
-    S4,
-    U4,
-    S8,
-    U8,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RegisterMmaLayout {
-    Row,
-    Col,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RegisterMmaOverflow {
-    NotApplicable,
-    Wrapping,
-    Satfinite,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RegisterMmaParticipation {
-    AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-}
-
-/// Rust `C, A, B` fragment shape used by the importer.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RegisterMmaAdapter {
-    C2U32A2U32B1U32ToD2U32,
-    C2U32A4U32B2U32ToD2U32,
-    C4F32A2U32B1U32ToD4F32,
-    C4F32A4U32B2U32ToD4F32,
-    C2F64A1F64B1F64ToD2F64,
-    C2I32A1U32B1U32ToD2I32,
-    C4I32A4U32B2U32ToD4I32,
-    C4I32A2U32B1U32ToD4I32,
-    C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-}
-
-/// Where the stable `cuda_device::wmma` callable is defined.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum RegisterMmaCompatibilitySource {
-    ExistingStub,
-    GeneratedStub,
-}
-
-/// Closed semantic contract for register-only sparse `mma.sp` operations.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct SparseMma {
-    pub shape: SparseMmaShape,
-    pub accumulator: SparseMmaAccumulator,
-    pub a_element: SparseMmaElement,
-    pub b_element: SparseMmaElement,
-    pub a_layout: SparseMmaLayout,
-    pub b_layout: SparseMmaLayout,
-    pub overflow: SparseMmaOverflow,
-    pub metadata: SparseMmaMetadata,
-    pub selector: SparseMmaSelector,
-    pub participation: SparseMmaParticipation,
-    pub adapter: SparseMmaAdapter,
-    pub llvm_adapter: SparseMmaLlvmAdapter,
-    pub compatibility_source: SparseMmaCompatibilitySource,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaShape {
-    M16n8k32,
-    M16n8k64,
-    M16n8k128,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaAccumulator {
-    F16,
-    F32,
-    S32,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaElement {
-    E2m1,
-    E2m3,
-    E3m2,
-    E4m3,
-    E5m2,
-    S4,
-    U4,
-    S8,
-    U8,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaLayout {
-    Row,
-    Col,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaOverflow {
-    NotApplicable,
-    Wrapping,
-    Satfinite,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaMetadata {
-    Standard,
-    Ordered,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaSelector {
-    ImmediateZeroOrOne,
-    ImmediateZero,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaParticipation {
-    AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-}
-
-/// Rust `C, A, B, metadata, selector` shape used by the importer.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaAdapter {
-    C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32,
-    C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32,
-    C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32,
-    C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32,
-}
-
-/// LLVM `A, B, C, metadata, selector` shape.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaLlvmAdapter {
-    A4I32B4I32C2V2F16MetadataI32SelectorI32ToD2V2F16,
-    A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32,
-    A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32,
-    A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32,
-}
-
-/// Where the stable `cuda_device::wmma` callable is defined.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum SparseMmaCompatibilitySource {
-    GeneratedStub,
-}
-
-/// Closed semantic contract for the generated packed global atomic-add
-/// family. These fields are intentionally enums rather than free-form strings:
-/// accepting an unreviewed state space, scope, or floating-point mode must
-/// require a generator change.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct PackedAtomic {
-    pub format: PackedAtomicFormat,
-    /// PTX ISA hardware floor, kept separate from cuda-oxide's admitted floor
-    /// and from backend-profile floors.
-    pub native_minimum_sm: u16,
-    pub operation: PackedAtomicOperation,
-    pub state_space: PackedAtomicStateSpace,
-    pub ordering: PackedAtomicOrdering,
-    pub scope: PackedAtomicScope,
-    pub rounding: PackedAtomicRounding,
-    pub subnormal: PackedAtomicSubnormal,
-    pub atomicity: PackedAtomicAtomicity,
-    pub pointer_contract: PackedAtomicPointerContract,
-    pub access_contract: PackedAtomicAccessContract,
-    pub scope_contract: PackedAtomicScopeContract,
-    pub codegen_contract: PackedAtomicCodegenContract,
-    pub return_contract: PackedAtomicReturnContract,
-    pub adapter: PackedAtomicAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicFormat {
-    F16x2,
-    Bf16x2,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicOperation {
-    Add,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicStateSpace {
-    Global,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicOrdering {
-    Relaxed,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicScope {
-    Gpu,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicRounding {
-    NearestEven,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicSubnormal {
-    Preserve,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicAtomicity {
-    PerElement,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicPointerContract {
-    MutableGlobalU32Aligned4,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicAccessContract {
-    NoMixedWholeWordOrNonAtomicAccess,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicScopeContract {
-    RacingAtomicsMutuallyInclusive,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicCodegenContract {
-    ExactNativeInstruction,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicReturnContract {
-    OldValuesPerElementMayBeNoncoherent,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAtomicAdapter {
-    OldPackedU32,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum LdmatrixAdapter {
-    SingleResultDirect,
-    MultipleResultsToArray,
-}
-
-/// Closed semantic and lowering contract for the generated `redux.sync`
-/// family.
-///
-/// The Rust and NVVM dialect APIs intentionally put the participation mask
-/// first, while LLVM's NVVM intrinsic puts the lane value first. Keeping that
-/// adapter typed prevents a generic direct-call renderer from silently
-/// swapping the collective's source and member mask.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Redux {
-    pub operation: ReduxOperation,
-    pub participation: ReduxParticipation,
-    pub adapter: ReduxAdapter,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ReduxOperation {
-    Add,
-    Umin,
-    Min,
-    Umax,
-    Max,
-    And,
-    Or,
-    Xor,
-    Fmin,
-    FminNan,
-    FminAbs,
-    FminAbsNan,
-    Fmax,
-    FmaxNan,
-    FmaxAbs,
-    FmaxAbsNan,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ReduxParticipation {
-    ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ReduxAdapter {
-    MaskValueToSourceMemberMask,
-}
-
-/// Closed semantic and lowering contract for the generated `vote.sync`
-/// family.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct Vote {
-    pub mode: VoteMode,
-    pub participation: VoteParticipation,
-    pub legacy_pre_sm70: PreSm70MemberMaskRule,
-    pub adapter: VoteAdapter,
-    pub mask_encoding: MaskEncoding,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum VoteMode {
-    All,
-    Any,
-    Ballot,
-    Uni,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum VoteParticipation {
-    ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum VoteAdapter {
-    DirectMaskPredicate,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum MaskEncoding {
-    RegisterOrImmediate,
-}
-
-/// Closed semantic and lowering contract for `activemask`.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ActiveMask {
-    pub observation: ActiveMaskObservation,
-    pub adapter: ActiveMaskAdapter,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ActiveMaskObservation {
-    ExecutingLanesAtInstruction,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ActiveMaskAdapter {
-    DirectZeroOperandMask,
-}
-
-/// Closed semantic and lowering contract for `match.sync`.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct WarpMatch {
-    pub mode: WarpMatchMode,
-    pub value_width: WarpMatchValueWidth,
-    pub participation: WarpMatchParticipation,
-    pub adapter: WarpMatchAdapter,
-    pub value_encoding: MatchOperandEncoding,
-    pub mask_encoding: MatchOperandEncoding,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpMatchMode {
-    Any,
-    All,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpMatchValueWidth {
-    B32,
-    B64,
-}
-
-impl WarpMatchValueWidth {
-    pub const fn bits(self) -> u32 {
-        match self {
-            Self::B32 => 32,
-            Self::B64 => 64,
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpMatchParticipation {
-    ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpMatchAdapter {
-    DirectMask,
-    ProjectMaskDiscardPredicate,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum MatchOperandEncoding {
-    RegisterOrImmediate,
-}
-
-/// Closed semantic and lowering contract for `bar.warp.sync`.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct WarpBarrier {
-    pub participation: WarpBarrierParticipation,
-    pub legacy_pre_sm70: PreSm70MemberMaskRule,
-    pub adapter: WarpBarrierAdapter,
-    pub mask_encoding: WarpBarrierMaskEncoding,
-    pub memory_ordering: WarpBarrierMemoryOrdering,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpBarrierParticipation {
-    ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PreSm70MemberMaskRule {
-    AllNamedLanesConvergedAndOnlyNamedLanesActive,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpBarrierAdapter {
-    DirectMemberMask,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpBarrierMaskEncoding {
-    RegisterOrImmediate,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpBarrierMemoryOrdering {
-    ParticipatingLanes,
-}
-
-/// Closed semantic and lowering contract for `shfl.sync`.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct WarpShuffle {
-    pub mode: WarpShuffleMode,
-    pub value_kind: WarpShuffleValueKind,
-    pub participation: WarpShuffleParticipation,
-    pub legacy_pre_sm70: PreSm70MemberMaskRule,
-    pub source_lane: WarpShuffleSourceLane,
-    pub adapter: WarpShuffleAdapter,
-    pub clamp: u32,
-    pub lane_encoding: WarpShuffleOperandEncoding,
-    pub mask_encoding: WarpShuffleOperandEncoding,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpShuffleMode {
-    Idx,
-    Bfly,
-    Down,
-    Up,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpShuffleValueKind {
-    I32,
-    F32,
-    I64,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpShuffleParticipation {
-    ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpShuffleSourceLane {
-    InRangeSourceActiveAndNamedOutOfRangeCopiesSelf,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpShuffleAdapter {
-    MaskValueLaneOrDeltaInsertClamp,
-    /// Split i64 into low/high b32 halves, shuffle both in one convergent
-    /// side-effecting block, then reassemble the original bit layout.
-    MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum WarpShuffleOperandEncoding {
-    RegisterOrImmediate,
-    RegisterOnly,
-}
-
-/// Closed identity and source adapter for generated packed integer dot products.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct DotProduct {
-    pub operation: DotProductOperation,
-    pub signedness: DotProductSignedness,
-    pub adapter: DotProductAdapter,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum DotProductOperation {
-    Dp2a,
-    Dp4a,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum DotProductSignedness {
-    Signed,
-    Unsigned,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum DotProductAdapter {
-    DirectThreeOperands,
-    InsertLowHalfFalse,
-}
-
-/// Closed identity and carrier contract for packed floating-point ALU ops.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct PackedAlu {
-    pub format: PackedAluFormat,
-    /// Hardware floor of the native PTX instruction, independent of the
-    /// target floor admitted by cuda-oxide.
-    pub native_minimum_sm: u16,
-    pub operation: PackedAluOperation,
-    pub adapter: PackedAluAdapter,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAluFormat {
-    Bf16x2,
-    F16x2,
-    F32x2,
-}
-
-/// Closed identity and carrier contract for extended integer min/max ops.
-///
-/// Covers the PTX ISA 8.0 integer min/max extensions: the `.relu` saturation
-/// qualifier on `s32` and `s16x2`, plus the packed `s16x2`/`u16x2` forms.
-/// These are the DPX-adjacent shapes ptxas fuses into `VIMNMX`-family SASS.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct IntegerMinMax {
-    pub format: IntegerMinMaxFormat,
-    /// Hardware floor of the native PTX instruction, independent of the
-    /// target floor admitted by cuda-oxide.
-    pub native_minimum_sm: u16,
-    pub operation: IntegerMinMaxOperation,
-    pub relu: bool,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum IntegerMinMaxFormat {
-    S32,
-    S16x2,
-    U16x2,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum IntegerMinMaxOperation {
-    Min,
-    Max,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAluOperation {
-    Add,
-    AddFtz,
-    Sub,
-    SubFtz,
-    Mul,
-    MulFtz,
-    Fma,
-    FmaFtz,
-    FmaSat,
-    FmaFtzSat,
-    FmaRelu,
-    FmaFtzRelu,
-    Min,
-    Max,
-    Neg,
-    Abs,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedAluAdapter {
-    DirectPackedU32,
-    DirectPackedU64,
-}
-
-/// Closed contract for scalar floating-point arithmetic.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ScalarArithmetic {
-    pub format: ScalarArithmeticFormat,
-    pub operation: ScalarArithmeticOperation,
-    pub rounding: ScalarArithmeticRounding,
-    pub subnormal: ScalarArithmeticSubnormal,
-    pub saturation: ScalarArithmeticSaturation,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarArithmeticFormat {
-    F32,
-    F64,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarArithmeticOperation {
-    Mul,
-    Div,
-    Fma,
-    Add,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarArithmeticRounding {
-    Rn,
-    Rz,
-    Rm,
-    Rp,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarArithmeticSubnormal {
-    Preserve,
-    Ftz,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarArithmeticSaturation {
-    None,
-    Sat,
-}
-
-/// Closed contract for unary scalar floating-point math operations.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ScalarMath {
-    pub format: ScalarMathFormat,
-    pub operation: ScalarMathOperation,
-    pub precision: ScalarMathPrecision,
-    pub subnormal: ScalarMathSubnormal,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarMathFormat {
-    F16,
-    F32,
-    F64,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarMathOperation {
-    Sin,
-    Cos,
-    /// Routes through inline PTX: LLVM 22's tblgen models ex2 as the
-    /// overloaded `int_nvvm_ex2_approx{,_ftz}` records (anyfloat, no DAG
-    /// selection pattern), so the evidence contract cannot admit a typed
-    /// call. The legacy `llvm.nvvm.ex2.approx.f`/`.ftz.f` names still select
-    /// directly on both llc 21 and 22, so this is promotable to a typed
-    /// route once the import resolves the overloaded family.
-    Ex2,
-    Lg2,
-    Rcp,
-    Rsqrt,
-    Sqrt,
-    /// Routes through inline PTX: LLVM 22.1.2's tblgen export carries no
-    /// record for tanh at all (llc 22 selects `llvm.nvvm.tanh.approx.f32`
-    /// via NVVMIntrinsic-class matching, and llc 21 miscompiles it into an
-    /// extern funcall), so this is the family's only PTX-native source.
-    /// Hardware floor is sm_75 (PTX ISA 7.0); the family contract gates it
-    /// at the attested sm_80 evidence floor like every other variant.
-    Tanh,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarMathPrecision {
-    Approx,
-    Rn,
-    Rz,
-    Rm,
-    Rp,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarMathSubnormal {
-    Preserve,
-    Ftz,
-}
-
-/// Closed identity and carrier contract for extended floating-point min/max.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ExtendedMinMax {
-    pub format: ExtendedMinMaxFormat,
-    pub operation: ExtendedMinMaxOperation,
-    pub subnormal: ExtendedMinMaxSubnormal,
-    pub nan: ExtendedMinMaxNan,
-    pub xorsign_abs: bool,
-    pub adapter: ExtendedMinMaxAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ExtendedMinMaxFormat {
-    F32,
-    F16,
-    Bf16,
-    F16x2,
-    Bf16x2,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ExtendedMinMaxOperation {
-    Min,
-    Max,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ExtendedMinMaxSubnormal {
-    Preserve,
-    Ftz,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ExtendedMinMaxNan {
-    Number,
-    Nan,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ExtendedMinMaxAdapter {
-    DirectF32,
-    /// A single 16-bit float carried as its `u16` bit pattern, matching how
-    /// `packed_conversion` already carries `e4m3x2` and `e5m2x2` operands.
-    DirectHalfU16,
-    DirectPackedU32,
-}
-
-/// Closed contract for converting between scalar and packed values.
-///
-/// The source may be a scalar pair (`f32x2`, two operands) or an already-packed
-/// 16-bit or 32-bit register (`f16x2`, `e4m3x2`, `e5m2x2`, one operand), so the
-/// operand arity follows [`PackedConversionSourceFormat`] rather than being
-/// fixed at two.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct PackedConversion {
-    pub source_format: PackedConversionSourceFormat,
-    pub destination_format: PackedConversionDestinationFormat,
-    pub rounding: PackedConversionRounding,
-    pub saturation: PackedConversionSaturation,
-    pub adapter: PackedConversionAdapter,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedConversionSourceFormat {
-    E4m3x2,
-    E5m2x2,
-    F16x2,
-    F32x2,
-}
-
-impl PackedConversionSourceFormat {
-    /// Number of source operands the conversion takes.
-    ///
-    /// `f32x2` names two scalar `f32` operands; every packed source arrives in a
-    /// single register.
-    pub fn operand_count(self) -> usize {
-        match self {
-            Self::F32x2 => 2,
-            Self::E4m3x2 | Self::E5m2x2 | Self::F16x2 => 1,
-        }
-    }
-
-    /// PTX source-type token, used as the trailing `cvt` modifier.
-    pub fn ptx_token(self) -> &'static str {
-        match self {
-            Self::E4m3x2 => "e4m3x2",
-            Self::E5m2x2 => "e5m2x2",
-            Self::F16x2 => "f16x2",
-            Self::F32x2 => "f32",
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedConversionDestinationFormat {
-    Bf16x2,
-    E4m3x2,
-    E5m2x2,
-    F16x2,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedConversionRounding {
-    NearestEven,
-    TowardZero,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedConversionSaturation {
-    None,
-    Relu,
-    Satfinite,
-    SatfiniteRelu,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum PackedConversionAdapter {
-    /// Forward the single packed source operand unchanged.
-    ///
-    /// PTX orders `cvt` operands as `d, a`, so a one-operand conversion needs no
-    /// reordering to keep the Rust argument order.
-    Identity,
-    /// Swap the two scalar operands.
-    ///
-    /// PTX writes the second source operand into the low half, so the operands
-    /// are reversed to keep the first Rust argument in the low half.
-    ReverseHighLowOperands,
-}
-
-/// Closed contract for one scalar floating-point conversion.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct ScalarConversion {
-    pub source_format: ScalarConversionSourceFormat,
-    pub destination_format: ScalarConversionDestinationFormat,
-    pub rounding: ScalarConversionRounding,
-    pub saturation: ScalarConversionSaturation,
-    pub result_representation: ScalarConversionResultRepresentation,
-    pub adapter: ScalarConversionAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarConversionSourceFormat {
-    F32,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarConversionDestinationFormat {
-    Tf32,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarConversionRounding {
-    NearestAway,
-    NearestEven,
-    TowardZero,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarConversionSaturation {
-    None,
-    Relu,
-    Satfinite,
-    ReluSatfinite,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarConversionResultRepresentation {
-    RawU32Bits,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum ScalarConversionAdapter {
-    DirectF32ToRawU32Bits,
-}
-
-/// Closed contract for classic global-to-shared `cp.async` copies.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct CpAsyncCopy {
-    pub cache_policy: CpAsyncCachePolicy,
-    pub copy_size: CpAsyncCopySize,
-    pub source_size: CpAsyncSourceSize,
-    pub adapter: CpAsyncAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum CpAsyncCachePolicy {
-    Ca,
-    Cg,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum CpAsyncCopySize {
-    B4,
-    B8,
-    B16,
-}
-
-impl CpAsyncCopySize {
-    pub const fn bytes(self) -> u32 {
-        match self {
-            Self::B4 => 4,
-            Self::B8 => 8,
-            Self::B16 => 16,
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum CpAsyncSourceSize {
-    Full,
-    Runtime,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum CpAsyncAdapter {
-    DirectPointers,
-    DirectPointersAndSourceSize,
-}
-
-/// Closed contract for classic `cp.async` group controls.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct CpAsyncControl {
-    pub operation: CpAsyncControlOperation,
-    pub adapter: CpAsyncControlAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum CpAsyncControlOperation {
-    CommitGroup,
-    WaitAll,
-    WaitGroup,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum CpAsyncControlAdapter {
-    NoOperands,
-    CompileTimeConstantMaxPending,
-}
-
-/// Closed contract for associating classic `cp.async` completion with an mbarrier.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct CpAsyncMbarrier {
-    pub operation: CpAsyncMbarrierOperation,
-    pub state_space: CpAsyncMbarrierStateSpace,
-    pub adapter: CpAsyncMbarrierAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum CpAsyncMbarrierOperation {
-    Arrive,
-    ArriveNoInc,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum CpAsyncMbarrierStateSpace {
-    Generic,
-    Shared,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum CpAsyncMbarrierAdapter {
-    PointerToVoid,
-}
-
-/// Closed contract for the basic shared-memory mbarrier lifecycle.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct MbarrierBasic {
-    pub operation: MbarrierBasicOperation,
-    pub state_space: MbarrierStateSpace,
-    pub adapter: MbarrierBasicAdapter,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum MbarrierBasicOperation {
-    Init,
-    Arrive,
-    TestWait,
-    Inval,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum MbarrierStateSpace {
-    Shared,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum MbarrierBasicAdapter {
-    #[serde(rename = "pointer_count_to_void")]
-    InitPointerCountToVoid,
-    #[serde(rename = "pointer_to_token")]
-    ArrivePointerToToken,
-    #[serde(rename = "pointer_token_to_predicate")]
-    TestWaitPointerTokenToPredicate,
-    #[serde(rename = "pointer_to_void")]
-    InvalPointerToVoid,
-}
-
-/// Closed contract for the remaining handwritten mbarrier operations.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct MbarrierExtended {
-    pub operation: MbarrierExtendedOperation,
-    pub adapter: MbarrierExtendedAdapter,
-    pub source_contract: MbarrierExtendedSourceContract,
-    pub runtime_validation: RuntimeValidation,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum MbarrierExtendedAdapter {
-    PointerTxCountBytesToTokenDroppingTxCount,
-    RawClusterAddressToVoid,
-    PointerTokenToPredicate,
-    PointerParityToPredicate,
-    ZeroOperandsToVoid,
-    NanosecondsToVoid,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum MbarrierExtendedSourceContract {
-    LlvmImported,
-    PtxNativeRawClusterAddress,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct AbiLedgerFile {
-    pub schema: u32,
-    pub intrinsic_abi: u32,
-    #[serde(rename = "entry")]
-    pub entries: Vec<AbiLedgerEntry>,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct AbiLedgerEntry {
-    pub abi_id: String,
-    pub status: String,
-    pub catalog_id: String,
-    pub operation_key: String,
-    pub raw_rust_signature: AbiRawRustSignature,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct AbiRawRustSignature {
-    pub safe: bool,
-    pub arguments: Vec<String>,
-    pub result: String,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct EvidenceFile {
-    pub schema: u32,
-    pub backend_profile: String,
-    #[serde(default)]
-    pub backend_kind: Option<IntrinsicBackend>,
-    pub llvm_revision: String,
-    pub backend_version: String,
-    pub backend_sha256: String,
-    #[serde(default)]
-    pub artifact_path: Option<String>,
-    #[serde(default)]
-    pub build_id_prefix: Option<String>,
-    #[serde(default)]
-    pub nvvm_ir_version: Option<String>,
-    #[serde(default)]
-    pub debug_ir_version: Option<String>,
-    pub records: Vec<EvidenceRecord>,
-}
-
-/// Schema-6 evidence before matrix expansion.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct EvidenceFileV6 {
-    pub schema: u32,
-    pub backend_profile: String,
-    #[serde(default)]
-    pub backend_kind: Option<IntrinsicBackend>,
-    pub llvm_revision: String,
-    pub backend_version: String,
-    pub backend_sha256: String,
-    #[serde(default)]
-    pub artifact_path: Option<String>,
-    #[serde(default)]
-    pub build_id_prefix: Option<String>,
-    #[serde(default)]
-    pub nvvm_ir_version: Option<String>,
-    #[serde(default)]
-    pub debug_ir_version: Option<String>,
-    #[serde(default)]
-    pub defaults: EvidenceRecordDefaults,
-    #[serde(default)]
-    pub fixtures: Vec<EvidenceFixture>,
-    #[serde(default)]
-    pub matrices: Vec<EvidenceMatrix>,
-    #[serde(default)]
-    pub records: Vec<EvidenceRecord>,
-}
-
-/// Facts shared by every record in one evidence matrix.
-#[derive(Debug, Clone, Default, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct EvidenceRecordDefaults {
-    #[serde(default)]
-    pub resolved_llvm_symbol: Option<String>,
-    #[serde(default)]
-    pub llvm_arguments: Option<Vec<String>>,
-    #[serde(default)]
-    pub llvm_results: Option<Vec<String>>,
-    #[serde(default)]
-    pub concrete_llvm_arguments: Option<Vec<String>>,
-    #[serde(default)]
-    pub concrete_llvm_results: Option<Vec<String>>,
-    #[serde(default)]
-    pub target_triple: Option<String>,
-    #[serde(default)]
-    pub gpu_target: Option<String>,
-    #[serde(default)]
-    pub ptx_feature: Option<String>,
-    #[serde(default)]
-    pub status: Option<String>,
-    #[serde(default)]
-    pub stages: Vec<EvidenceStage>,
-    #[serde(default)]
-    pub declaration_attributes_canonicalized: Option<bool>,
-    #[serde(default)]
-    pub runtime_validation: Option<RuntimeValidation>,
-}
-
-/// One shared fixture and the number of records it covers.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct EvidenceFixture {
-    pub id: String,
-    pub coverage_count: usize,
-    pub stages: Vec<EvidenceStage>,
-}
-
-/// One Cartesian evidence matrix.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct EvidenceMatrix {
-    pub axes: Vec<EvidenceMatrixAxis>,
-    pub product_count: usize,
-    #[serde(default)]
-    pub fixtures: Vec<String>,
-    pub template: EvidenceMatrixTemplate,
-}
-
-/// One named matrix axis.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct EvidenceMatrixAxis {
-    pub name: String,
-    pub values: Vec<String>,
-}
-
-/// Identity and matrix-specific facts for one record template.
-#[derive(Debug, Clone, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct EvidenceMatrixTemplate {
-    pub id: String,
-    #[serde(default)]
-    pub source: Option<IntrinsicSource>,
-    #[serde(default)]
-    pub source_record: Option<String>,
-    #[serde(deserialize_with = "deserialize_required_optional_string")]
-    pub llvm_symbol: Option<String>,
-    pub expected_ptx: InstructionPattern,
-    #[serde(default)]
-    pub facts: EvidenceRecordDefaults,
-}
-
-fn deserialize_required_optional_string<'de, D>(deserializer: D) -> Result<Option<String>, D::Error>
-where
-    D: serde::Deserializer<'de>,
-{
-    Option::<String>::deserialize(deserializer)
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct EvidenceRecord {
-    pub id: String,
-    #[serde(default)]
-    pub source: Option<IntrinsicSource>,
-    #[serde(default)]
-    pub source_record: Option<String>,
-    #[serde(default)]
-    pub llvm_symbol: Option<String>,
-    #[serde(default)]
-    pub resolved_llvm_symbol: Option<String>,
-    #[serde(default)]
-    pub llvm_arguments: Vec<String>,
-    #[serde(default)]
-    pub llvm_results: Vec<String>,
-    #[serde(default)]
-    pub concrete_llvm_arguments: Vec<String>,
-    #[serde(default)]
-    pub concrete_llvm_results: Vec<String>,
-    pub target_triple: String,
-    pub gpu_target: String,
-    pub ptx_feature: String,
-    pub status: String,
-    #[serde(default)]
-    pub stages: Vec<EvidenceStage>,
-    #[serde(default)]
-    pub declaration_attributes_canonicalized: Option<bool>,
-    #[serde(default)]
-    pub runtime_validation: Option<RuntimeValidation>,
-    pub expected_ptx: InstructionPattern,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct EvidenceStage {
-    pub targets: Vec<String>,
-    pub representation: String,
-    pub stage: EvidenceStageKind,
-    #[serde(default)]
-    pub mechanism: Option<BackendLoweringMechanism>,
-    pub outcome: String,
-    pub detail: String,
-    #[serde(default)]
-    pub artifact_kind: Option<EvidenceArtifactKind>,
-    #[serde(default)]
-    pub tool_path: Option<String>,
-    #[serde(default)]
-    pub tool_version: Option<String>,
-    #[serde(default)]
-    pub tool_sha256: Option<String>,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum EvidenceArtifactKind {
-    Cubin,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(rename_all = "snake_case")]
-pub enum EvidenceStageKind {
-    DeclarationCanonicalization,
-    BackendCodegen,
-    DeviceLink,
-    PtxAssembly,
-    Runtime,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogFile {
-    pub schema: u32,
-    pub catalog_version: String,
-    pub intrinsic_abi: u32,
-    pub generator_version: String,
-    pub source: CatalogSource,
-    pub inputs: CatalogInputs,
-    pub intrinsics: Vec<CatalogIntrinsic>,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogSource {
-    pub llvm_repository: String,
-    pub llvm_revision: String,
-    pub llvm_tblgen_version: String,
-    pub llvm_tblgen_source_revision: String,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogInputs {
-    pub imported_sha256: String,
-    pub overlay_sha256: String,
-    pub abi_ledger_sha256: String,
-    pub evidence_sha256: Vec<String>,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogIntrinsic {
-    pub id: String,
-    pub operation_key: String,
-    pub family: String,
-    pub source: IntrinsicSource,
-    pub selections: Vec<CatalogSelection>,
-    pub rust: CatalogRust,
-    pub dialect: CatalogDialect,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub llvm: Option<CatalogLlvm>,
-    pub semantics: CatalogSemantics,
-    pub target: CatalogTarget,
-    pub backend: CatalogBackend,
-    #[serde(default, skip_serializing_if = "Vec::is_empty")]
-    pub backend_lowerings: Vec<CatalogBackendLowering>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub packed_atomic: Option<PackedAtomic>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub redux: Option<Redux>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub vote: Option<Vote>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub active_mask: Option<ActiveMask>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub warp_match: Option<WarpMatch>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub warp_barrier: Option<WarpBarrier>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub warp_shuffle: Option<WarpShuffle>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub dot_product: Option<DotProduct>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub packed_alu: Option<PackedAlu>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub integer_minmax: Option<IntegerMinMax>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub packed_conversion: Option<PackedConversion>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub scalar_conversion: Option<ScalarConversion>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub scalar_arithmetic: Option<ScalarArithmetic>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub scalar_math: Option<ScalarMath>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub extended_minmax: Option<ExtendedMinMax>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub cp_async_copy: Option<CpAsyncCopy>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub cp_async_control: Option<CpAsyncControl>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub cp_async_mbarrier: Option<CpAsyncMbarrier>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub mbarrier_basic: Option<MbarrierBasic>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub movmatrix: Option<Movmatrix>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub mbarrier_extended: Option<MbarrierExtended>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub register_mma: Option<RegisterMma>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub sparse_mma: Option<SparseMma>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub prmt: Option<Prmt>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub cluster_barrier: Option<ClusterBarrier>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub wgmma_control: Option<WgmmaControl>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub special_register: Option<SpecialRegister>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub debug_control: Option<DebugControl>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub cluster_memory: Option<ClusterMemory>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub clc: Option<Clc>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub tma: Option<Tma>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub tcgen05: Option<Tcgen05>,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub ldmatrix: Option<CatalogLdmatrix>,
-    pub lowering: String,
-    pub expected_ptx: InstructionPattern,
-    pub summary: String,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogSelection {
-    pub source_record: String,
-    pub asm: String,
-    pub predicates: Vec<String>,
-    #[serde(
-        default,
-        skip_serializing_if = "ImportedSelectionConstraints::is_empty"
-    )]
-    pub constraints: ImportedSelectionConstraints,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogRust {
-    pub abi_id: String,
-    pub module: String,
-    pub name: String,
-    pub arguments: Vec<String>,
-    pub result: String,
-    pub safe: bool,
-    pub must_use: bool,
-    pub safe_allowlist_reason: Option<String>,
-    pub canonical_path: String,
-    pub public_path: String,
-    pub compatibility_paths: Vec<String>,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogDialect {
-    pub op_type: String,
-    pub op_name: String,
-    pub operands: Vec<String>,
-    pub results: Vec<String>,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogLlvm {
-    pub symbol: String,
-    #[serde(default, skip_serializing_if = "Option::is_none")]
-    pub resolved_symbol: Option<String>,
-    pub arguments: Vec<String>,
-    pub results: Vec<String>,
-    pub properties: Vec<String>,
-    pub result_facts: CatalogLlvmResultFacts,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogLlvmResultFacts {
-    pub no_undef: bool,
-    pub range: Option<CatalogHalfOpenRange>,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogHalfOpenRange {
-    pub lower: String,
-    pub upper_exclusive: String,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogSemantics {
-    pub pure: bool,
-    pub memory: String,
-    pub convergent: bool,
-    pub execution_scope: String,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogTarget {
-    pub minimum_ptx: PtxVersion,
-    pub hardware: CatalogHardwareTarget,
-    pub ptx_result: String,
-    pub targets: String,
-    pub ptx_isa_version: String,
-    pub ptx_isa_section: String,
-    pub ptx_isa_url: String,
-}
-
-/// A PTX ISA version encoded as `major * 10 + minor`.
-///
-/// PTX currently uses one decimal minor digit. The resolver validates that
-/// shape before constructing this value, so generated consumers compare a
-/// number rather than reparsing policy text.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
-pub struct PtxVersion(u16);
-
-impl PtxVersion {
-    pub const fn encoded(self) -> u16 {
-        self.0
-    }
-
-    pub const fn major(self) -> u16 {
-        self.0 / 10
-    }
-
-    pub const fn minor(self) -> u16 {
-        self.0 % 10
-    }
-}
-
-impl FromStr for PtxVersion {
-    type Err = String;
-
-    fn from_str(value: &str) -> Result<Self, Self::Err> {
-        let (major, minor) = value
-            .split_once('.')
-            .ok_or_else(|| "expected major.minor".to_owned())?;
-        if major.is_empty()
-            || !major.bytes().all(|byte| byte.is_ascii_digit())
-            || minor.len() != 1
-            || !minor.bytes().all(|byte| byte.is_ascii_digit())
-        {
-            return Err("expected numeric major.minor with one minor digit".to_owned());
-        }
-        let major: u16 = major.parse().map_err(|_| "major version is too large")?;
-        let minor: u16 = minor.parse().unwrap();
-        if format!("{major}.{minor}") != value {
-            return Err("version is not in canonical major.minor form".to_owned());
-        }
-        let encoded = major
-            .checked_mul(10)
-            .and_then(|value| value.checked_add(minor))
-            .ok_or_else(|| "version is too large".to_owned())?;
-        Ok(Self(encoded))
-    }
-}
-
-impl Serialize for PtxVersion {
-    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
-    where
-        S: serde::Serializer,
-    {
-        serializer.serialize_str(&self.to_string())
-    }
-}
-
-impl<'de> Deserialize<'de> for PtxVersion {
-    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
-    where
-        D: serde::Deserializer<'de>,
-    {
-        let value = String::deserialize(deserializer)?;
-        value.parse().map_err(serde::de::Error::custom)
-    }
-}
-
-impl fmt::Display for PtxVersion {
-    fn fmt(&self, formatter: &mut fmt::Formatter<'_>) -> fmt::Result {
-        write!(formatter, "{}.{}", self.major(), self.minor())
-    }
-}
-
-/// Reviewed hardware availability for an intrinsic.
-///
-/// Exact `a` and `f` targets stay distinct from monotonic minimums. A target
-/// matrix also keeps each hardware target paired with its PTX floor.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(tag = "kind", rename_all = "snake_case")]
-pub enum CatalogHardwareTarget {
-    All,
-    AnyOf {
-        alternatives: Vec<CatalogHardwareAlternative>,
-    },
-    /// Closed selector contracts with their exact PTX and hardware pairs.
-    TargetMatrix {
-        contracts: Vec<CatalogTargetContract>,
-    },
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(tag = "kind", rename_all = "snake_case")]
-pub enum CatalogHardwareAlternative {
-    MinimumSm { sm: u16 },
-    ExactArchitecture { sm: u16 },
-    FamilyTarget { sm: u16 },
-}
-
-/// One PTX floor paired with one hardware alternative.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct CatalogTargetAlternative {
-    pub minimum_ptx: PtxVersion,
-    pub hardware: CatalogHardwareAlternative,
-}
-
-/// One selector tuple and its exact PTX and hardware pairs.
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct CatalogTargetContract {
-    pub selectors: Vec<TargetSelectorBinding>,
-    pub alternatives: Vec<CatalogTargetAlternative>,
-}
-
-/// One field/value pair that selects a target contract.
-#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct TargetSelectorBinding {
-    pub name: String,
-    pub value: String,
-}
-
-/// One selector-specific target contract from admission policy.
-#[allow(dead_code)]
-#[derive(Debug, Clone, PartialEq, Eq, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct TargetContract {
-    #[serde(default)]
-    pub selectors: Vec<TargetSelectorBinding>,
-    pub alternatives: Vec<TargetContractAlternative>,
-}
-
-/// One target spelling and PTX floor.
-#[derive(Debug, Clone, PartialEq, Eq, Deserialize)]
-#[serde(deny_unknown_fields)]
-pub struct TargetContractAlternative {
-    pub target: String,
-    pub minimum_ptx: String,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogBackend {
-    pub profile: String,
-    pub version: String,
-    pub sha256: String,
-    pub status: String,
-    pub target_triple: String,
-    pub gpu_target: String,
-    pub ptx_feature: String,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogBackendLowering {
-    pub backend: IntrinsicBackend,
-    pub mechanism: BackendLoweringMechanism,
-    pub evidence_profile: String,
-    pub target: CatalogTargetRequirement,
-    pub version: String,
-    pub sha256: String,
-    pub artifact_path: Option<String>,
-    pub build_id_prefix: Option<String>,
-    pub status: String,
-    pub stages: Vec<EvidenceStage>,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogTargetRequirement {
-    pub minimum_ptx: PtxVersion,
-    pub hardware: CatalogHardwareTarget,
-}
-
-#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
-pub struct CatalogLdmatrix {
-    pub variant: LdmatrixVariant,
-    pub safety: LdmatrixSafety,
-    pub adapter: LdmatrixAdapter,
-    pub selected_address_space: ImportedAddressSpace,
-}
-
-impl CatalogIntrinsic {
-    pub fn scalar_width(&self) -> Option<u32> {
-        match self.rust.result.as_str() {
-            "u32" => Some(32),
-            "u64" => Some(64),
-            _ => None,
-        }
-    }
-
-    pub fn llvm_identifier(&self) -> String {
-        llvm_symbol_to_identifier(&self.llvm.as_ref().expect("LLVM-backed intrinsic").symbol)
-    }
-
-    pub fn resolved_llvm_identifier(&self) -> String {
-        let llvm = self.llvm.as_ref().expect("LLVM-backed intrinsic");
-        llvm_symbol_to_identifier(llvm.resolved_symbol.as_deref().unwrap_or(&llvm.symbol))
-    }
-}
-
-fn llvm_symbol_to_identifier(symbol: &str) -> String {
-    if !symbol.contains('_') {
-        return symbol.replace('.', "_");
-    }
-
-    let suffix = symbol
-        .strip_prefix("llvm.")
-        .expect("LLVM intrinsic symbol must start with llvm.");
-    let mut output = String::from("llvm__");
-    for ch in suffix.chars() {
-        match ch {
-            '.' => output.push_str("_d"),
-            '_' => output.push_str("_u"),
-            ch if ch.is_ascii_alphanumeric() => output.push(ch),
-            _ => panic!("LLVM intrinsic symbol contains an unsupported character"),
-        }
-    }
-    output
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-
-    #[test]
-    fn llvm_identifier_encoding_preserves_literal_underscores() {
-        assert_eq!(
-            llvm_symbol_to_identifier("llvm.nvvm.read.ptx.sreg.tid.x"),
-            "llvm_nvvm_read_ptx_sreg_tid_x"
-        );
-        assert_eq!(
-            llvm_symbol_to_identifier("llvm.nvvm.wgmma.wait_group.sync.aligned"),
-            "llvm__nvvm_dwgmma_dwait_ugroup_dsync_daligned"
-        );
-        assert_eq!(
-            llvm_symbol_to_identifier(
-                "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8x16.b4x16_p64.p3"
-            ),
-            "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db4x16_up64_dp3"
-        );
-        assert_eq!(
-            llvm_symbol_to_identifier(
-                "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x4.b8x16.b6x16_p32.p3"
-            ),
-            "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx4_db8x16_db6x16_up32_dp3"
-        );
-    }
-
-    #[test]
-    fn ldmatrix_register_count_includes_the_shape_width() {
-        let variant = |shape, multiplicity| LdmatrixVariant {
-            shape,
-            multiplicity,
-            layout: LdmatrixLayout::Normal,
-            element: LdmatrixElement::B8,
-            state_space: LdmatrixStateSpace::Shared,
-        };
-
-        assert_eq!(
-            variant(LdmatrixShape::M8n16, LdmatrixMultiplicity::X4).register_count(),
-            4
-        );
-        assert_eq!(
-            variant(LdmatrixShape::M16n16, LdmatrixMultiplicity::X1).register_count(),
-            2
-        );
-        assert_eq!(
-            variant(LdmatrixShape::M16n16, LdmatrixMultiplicity::X2).register_count(),
-            4
-        );
-    }
-
-    #[test]
-    fn blackwell_ldmatrix_address_contracts_keep_readable_widths_distinct() {
-        assert_eq!(
-            serde_json::from_str::<LdmatrixAddressContract>(
-                r#""warp_lane_addresses_mapped_by_multiplicity_sixteen_byte_aligned_sixteen_bytes_readable""#
-            )
-            .unwrap(),
-            LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadable
-        );
-        assert_eq!(
-            serde_json::from_str::<LdmatrixAddressContract>(
-                r#""warp_lane_addresses_mapped_by_multiplicity_sixteen_byte_aligned_thirty_two_bytes_readable""#
-            )
-            .unwrap(),
-            LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedThirtyTwoBytesReadable
-        );
-    }
-
-    #[test]
-    fn wgmma_control_contract_is_closed() {
-        let parsed: WgmmaControl = serde_json::from_str(
-            r#"{
-                "mode": "wait_group",
-                "adapter": "const_generic_u32_to_i64_immediate",
-                "participation": "warpgroup_all_threads_same_instruction"
-            }"#,
-        )
-        .unwrap();
-        assert_eq!(parsed.mode, WgmmaControlMode::WaitGroup);
-        assert_eq!(
-            parsed.adapter,
-            WgmmaControlAdapter::ConstGenericU32ToI64Immediate
-        );
-        assert_eq!(
-            parsed.participation,
-            WgmmaControlParticipation::WarpgroupAllThreadsSameInstruction
-        );
-
-        let open_ended = r#"{
-            "mode": "wait_group",
-            "adapter": "const_generic_u32_to_i64_immediate",
-            "participation": "warpgroup_all_threads_same_instruction",
-            "custom_ptx": "wgmma.wait_group.sync.aligned 0;"
-        }"#;
-        assert!(serde_json::from_str::<WgmmaControl>(open_ended).is_err());
-    }
-
-    #[test]
-    fn locked_tool_rejects_misspelled_security_field() {
-        let input = r#"
-name = "llvm-tblgen"
-version_line = "LLVM version test"
-sha256 = "abc"
-enforce_sha25 = true
-provenance = "test"
-"#;
-        let error = toml::from_str::<LockedTool>(input).unwrap_err();
-        assert!(error.to_string().contains("enforce_sha25"));
-    }
-
-    #[test]
-    fn imported_selection_rejects_misspelled_constraint() {
-        let input = r#"{
-            "source_record": "selection",
-            "asm": "op;",
-            "predicates": [],
-            "constraints": { "adress_space": "shared" }
-        }"#;
-        let error = serde_json::from_str::<ImportedSelection>(input).unwrap_err();
-        assert!(error.to_string().contains("adress_space"));
-    }
-
-    #[test]
-    fn imported_selection_preserves_immediate_binding() {
-        let input = r#"{
-            "source_record": "DOT2_lo_ss",
-            "asm": "dp2a.lo.s32.s32 $dst, $a, $b, $c;",
-            "predicates": ["hasDotInstructions"],
-            "constraints": {
-                "immediate_bindings": [
-                    { "argument_index": 2, "value": 0 }
-                ]
-            }
-        }"#;
-        let selection = serde_json::from_str::<ImportedSelection>(input).unwrap();
-        assert_eq!(
-            selection.constraints.immediate_bindings,
-            [ImportedImmediateBinding {
-                argument_index: 2,
-                value: 0,
-            }]
-        );
-        assert!(!selection.constraints.is_empty());
-    }
-
-    #[test]
-    fn imported_immediate_binding_rejects_misspelled_index() {
-        let input = r#"{
-            "source_record": "DOT2_lo_ss",
-            "asm": "dp2a.lo.s32.s32 $dst, $a, $b, $c;",
-            "predicates": [],
-            "constraints": {
-                "immediate_bindings": [
-                    { "argument_indx": 2, "value": 0 }
-                ]
-            }
-        }"#;
-        let error = serde_json::from_str::<ImportedSelection>(input).unwrap_err();
-        assert!(error.to_string().contains("argument_indx"));
-    }
-
-    #[test]
-    fn redux_contract_rejects_unknown_operand_adapter() {
-        let input = r#"
-operation = "add"
-participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
-adapter = "mask_value_direct"
-"#;
-        let error = toml::from_str::<Redux>(input).unwrap_err();
-        assert!(error.to_string().contains("mask_value_direct"));
-    }
-
-    #[test]
-    fn packed_alu_contract_rejects_unknown_format_operation_and_adapter() {
-        let valid = r#"
-format = "bf16x2"
-native_minimum_sm = 80
-operation = "fma"
-adapter = "direct_packed_u32"
-"#;
-        toml::from_str::<PackedAlu>(valid).unwrap();
-        for invalid in [
-            valid.replace("format = \"bf16x2\"", "format = \"bf16\""),
-            valid.replace("native_minimum_sm = 80\n", ""),
-            valid.replace("native_minimum_sm = 80", "native_minimum_sm = \"80\""),
-            valid.replace("operation = \"fma\"", "operation = \"mad\""),
-            valid.replace(
-                "adapter = \"direct_packed_u32\"",
-                "adapter = \"bitcast_any\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(toml::from_str::<PackedAlu>(&invalid).is_err(), "{invalid}");
-        }
-    }
-
-    #[test]
-    fn packed_conversion_contract_rejects_open_ended_policy() {
-        let valid = r#"
-source_format = "f32x2"
-destination_format = "bf16x2"
-rounding = "nearest_even"
-saturation = "none"
-adapter = "reverse_high_low_operands"
-"#;
-        toml::from_str::<PackedConversion>(valid).unwrap();
-        for invalid in [
-            valid.replace("source_format = \"f32x2\"", "source_format = \"f64x2\""),
-            valid.replace(
-                "destination_format = \"bf16x2\"",
-                "destination_format = \"f8x2\"",
-            ),
-            valid.replace("rounding = \"nearest_even\"", "rounding = \"zero\""),
-            valid.replace("saturation = \"none\"", "saturation = \"finite\""),
-            valid.replace(
-                "adapter = \"reverse_high_low_operands\"",
-                "adapter = \"direct\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(
-                toml::from_str::<PackedConversion>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-    }
-
-    #[test]
-    fn vote_contract_rejects_unknown_modes_and_mask_encodings() {
-        let valid = r#"
-mode = "all"
-participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
-legacy_pre_sm70 = "all_named_lanes_converged_and_only_named_lanes_active"
-adapter = "direct_mask_predicate"
-mask_encoding = "register_or_immediate"
-"#;
-        toml::from_str::<Vote>(valid).unwrap();
-
-        for invalid in [
-            valid.replace("mode = \"all\"", "mode = \"match\""),
-            valid.replace(
-                "mask_encoding = \"register_or_immediate\"",
-                "mask_encoding = \"any_operand\"",
-            ),
-            valid.replace(
-                "legacy_pre_sm70 = \"all_named_lanes_converged_and_only_named_lanes_active\"",
-                "legacy_pre_sm70 = \"independent_threads\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(toml::from_str::<Vote>(&invalid).is_err(), "{invalid}");
-        }
-    }
-
-    #[test]
-    fn warp_shuffle_contract_rejects_open_ended_policy() {
-        let valid = r#"
-mode = "idx"
-value_kind = "i32"
-participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
-legacy_pre_sm70 = "all_named_lanes_converged_and_only_named_lanes_active"
-source_lane = "in_range_source_active_and_named_out_of_range_copies_self"
-adapter = "mask_value_lane_or_delta_insert_clamp"
-clamp = 31
-lane_encoding = "register_or_immediate"
-mask_encoding = "register_or_immediate"
-"#;
-        toml::from_str::<WarpShuffle>(valid).unwrap();
-
-        for invalid in [
-            valid.replace("mode = \"idx\"", "mode = \"rotate\""),
-            valid.replace("value_kind = \"i32\"", "value_kind = \"b32\""),
-            valid.replace(
-                "source_lane = \"in_range_source_active_and_named_out_of_range_copies_self\"",
-                "source_lane = \"unchecked\"",
-            ),
-            valid.replace(
-                "lane_encoding = \"register_or_immediate\"",
-                "lane_encoding = \"anything\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(
-                toml::from_str::<WarpShuffle>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-
-        let i64 = r#"
-mode = "down"
-value_kind = "i64"
-participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
-legacy_pre_sm70 = "all_named_lanes_converged_and_only_named_lanes_active"
-source_lane = "in_range_source_active_and_named_out_of_range_copies_self"
-adapter = "mask_value_lane_or_delta_split_i64_low_high_b32_insert_clamp_reassemble"
-clamp = 31
-lane_encoding = "register_only"
-mask_encoding = "register_only"
-"#;
-        let parsed = toml::from_str::<WarpShuffle>(i64).unwrap();
-        assert_eq!(parsed.value_kind, WarpShuffleValueKind::I64);
-        assert_eq!(
-            parsed.adapter,
-            WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
-        );
-        assert_eq!(
-            parsed.lane_encoding,
-            WarpShuffleOperandEncoding::RegisterOnly
-        );
-
-        for invalid in [
-            i64.replace("value_kind = \"i64\"", "value_kind = \"u64\""),
-            i64.replace(
-                "adapter = \"mask_value_lane_or_delta_split_i64_low_high_b32_insert_clamp_reassemble\"",
-                "adapter = \"split_any_width\"",
-            ),
-            i64.replace(
-                "mask_encoding = \"register_only\"",
-                "mask_encoding = \"any_operand\"",
-            ),
-        ] {
-            assert!(
-                toml::from_str::<WarpShuffle>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-    }
-
-    #[test]
-    fn warp_match_contract_rejects_open_ended_adapters_and_encodings() {
-        let valid = r#"
-mode = "all"
-value_width = "b64"
-participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
-adapter = "project_mask_discard_predicate"
-value_encoding = "register_or_immediate"
-mask_encoding = "register_or_immediate"
-"#;
-        toml::from_str::<WarpMatch>(valid).unwrap();
-
-        for invalid in [
-            valid.replace("mode = \"all\"", "mode = \"equal\""),
-            valid.replace(
-                "adapter = \"project_mask_discard_predicate\"",
-                "adapter = \"first_result\"",
-            ),
-            valid.replace(
-                "value_encoding = \"register_or_immediate\"",
-                "value_encoding = \"anything\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(toml::from_str::<WarpMatch>(&invalid).is_err(), "{invalid}");
-        }
-    }
-
-    #[test]
-    fn warp_barrier_contract_rejects_open_ended_policy() {
-        let valid = r#"
-participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
-legacy_pre_sm70 = "all_named_lanes_converged_and_only_named_lanes_active"
-adapter = "direct_member_mask"
-mask_encoding = "register_or_immediate"
-memory_ordering = "participating_lanes"
-"#;
-        toml::from_str::<WarpBarrier>(valid).unwrap();
-
-        for invalid in [
-            valid.replace("adapter = \"direct_member_mask\"", "adapter = \"direct\""),
-            valid.replace(
-                "legacy_pre_sm70 = \"all_named_lanes_converged_and_only_named_lanes_active\"",
-                "legacy_pre_sm70 = \"independent_threads\"",
-            ),
-            valid.replace(
-                "mask_encoding = \"register_or_immediate\"",
-                "mask_encoding = \"any_operand\"",
-            ),
-            valid.replace(
-                "memory_ordering = \"participating_lanes\"",
-                "memory_ordering = \"none\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(
-                toml::from_str::<WarpBarrier>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-    }
-
-    #[test]
-    fn mbarrier_basic_contract_rejects_open_ended_policy() {
-        let valid = r#"
-operation = "test_wait"
-state_space = "shared"
-adapter = "pointer_token_to_predicate"
-runtime_validation = "unexecuted"
-"#;
-        let parsed = toml::from_str::<MbarrierBasic>(valid).unwrap();
-        assert_eq!(parsed.operation, MbarrierBasicOperation::TestWait);
-        assert_eq!(
-            parsed.adapter,
-            MbarrierBasicAdapter::TestWaitPointerTokenToPredicate
-        );
-
-        for invalid in [
-            valid.replace("operation = \"test_wait\"", "operation = \"wait\""),
-            valid.replace("state_space = \"shared\"", "state_space = \"global\""),
-            valid.replace(
-                "adapter = \"pointer_token_to_predicate\"",
-                "adapter = \"direct\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(
-                toml::from_str::<MbarrierBasic>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-    }
-
-    #[test]
-    fn movmatrix_contract_rejects_open_ended_policy() {
-        let valid = r#"
-participation = "all_warp_lanes_same_instruction_no_exited_lanes"
-adapter = "packed_b16x2_u32_to_packed_b16x2_u32"
-runtime_validation = "unexecuted"
-"#;
-        let parsed = toml::from_str::<Movmatrix>(valid).unwrap();
-        assert_eq!(
-            parsed.participation,
-            MovmatrixParticipation::AllWarpLanesSameInstructionNoExitedLanes
-        );
-
-        for invalid in [
-            valid.replace(
-                "all_warp_lanes_same_instruction_no_exited_lanes",
-                "participating_lanes",
-            ),
-            valid.replace("packed_b16x2_u32_to_packed_b16x2_u32", "direct_u32"),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(toml::from_str::<Movmatrix>(&invalid).is_err(), "{invalid}");
-        }
-    }
-
-    #[test]
-    fn mbarrier_extended_contract_rejects_open_ended_policy() {
-        let valid = r#"
-operation = "arrive_expect_tx_cta"
-adapter = "pointer_tx_count_bytes_to_token_dropping_tx_count"
-source_contract = "llvm_imported"
-runtime_validation = "unexecuted"
-"#;
-        let parsed = toml::from_str::<MbarrierExtended>(valid).unwrap();
-        assert_eq!(
-            parsed.adapter,
-            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount
-        );
-        assert_eq!(
-            parsed.source_contract,
-            MbarrierExtendedSourceContract::LlvmImported
-        );
-
-        for invalid in [
-            valid.replace("llvm_imported", "auto"),
-            valid.replace(
-                "pointer_tx_count_bytes_to_token_dropping_tx_count",
-                "direct",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(
-                toml::from_str::<MbarrierExtended>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-    }
-
-    #[test]
-    fn register_mma_contract_parses_unsigned_k16_generated_stub() {
-        let valid = r#"
-shape = "m16n8k16"
-operation = "multiply"
-accumulator = "s32"
-a_element = "s8"
-b_element = "u8"
-a_layout = "row"
-b_layout = "col"
-overflow = "satfinite"
-participation = "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes"
-adapter = "c4_i32_a2_u32_b1_u32_to_d4_i32"
-compatibility_source = "generated_stub"
-runtime_validation = "unexecuted"
-"#;
-        let parsed = toml::from_str::<RegisterMma>(valid).unwrap();
-        assert_eq!(parsed.b_element, RegisterMmaElement::U8);
-        assert_eq!(parsed.adapter, RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32);
-        assert_eq!(
-            parsed.compatibility_source,
-            RegisterMmaCompatibilitySource::GeneratedStub
-        );
-
-        for invalid in [
-            valid.replace("b_element = \"u8\"", "b_element = \"i8\""),
-            valid.replace(
-                "adapter = \"c4_i32_a2_u32_b1_u32_to_d4_i32\"",
-                "adapter = \"direct\"",
-            ),
-            valid.replace(
-                "compatibility_source = \"generated_stub\"",
-                "compatibility_source = \"automatic\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(
-                toml::from_str::<RegisterMma>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-    }
-
-    #[test]
-    fn sparse_mma_contract_closes_the_selector_and_metadata_modes() {
-        let valid = r#"
-shape = "m16n8k32"
-accumulator = "s32"
-a_element = "s8"
-b_element = "u8"
-a_layout = "row"
-b_layout = "col"
-overflow = "satfinite"
-metadata = "standard"
-selector = "immediate_zero_or_one"
-participation = "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes"
-adapter = "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32"
-llvm_adapter = "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32"
-compatibility_source = "generated_stub"
-runtime_validation = "unexecuted"
-"#;
-        let parsed = toml::from_str::<SparseMma>(valid).unwrap();
-        assert_eq!(parsed.metadata, SparseMmaMetadata::Standard);
-        assert_eq!(parsed.selector, SparseMmaSelector::ImmediateZeroOrOne);
-
-        let ordered = valid.replace("metadata = \"standard\"", "metadata = \"ordered\"");
-        assert_eq!(
-            toml::from_str::<SparseMma>(&ordered).unwrap().metadata,
-            SparseMmaMetadata::Ordered
-        );
-
-        let k64 = ordered
-            .replace("shape = \"m16n8k32\"", "shape = \"m16n8k64\"")
-            .replace(
-                "selector = \"immediate_zero_or_one\"",
-                "selector = \"immediate_zero\"",
-            )
-            .replace(
-                "adapter = \"c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32\"",
-                "adapter = \"c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32\"",
-            )
-            .replace(
-                "llvm_adapter = \"a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32\"",
-                "llvm_adapter = \"a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32\"",
-            );
-        let parsed_k64 = toml::from_str::<SparseMma>(&k64).unwrap();
-        assert_eq!(parsed_k64.shape, SparseMmaShape::M16n8k64);
-        assert_eq!(parsed_k64.selector, SparseMmaSelector::ImmediateZero);
-        assert_eq!(
-            parsed_k64.adapter,
-            SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32
-        );
-        assert_eq!(
-            parsed_k64.llvm_adapter,
-            SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32
-        );
-
-        let int4 = ordered
-            .replace("shape = \"m16n8k32\"", "shape = \"m16n8k64\"")
-            .replace("a_element = \"s8\"", "a_element = \"s4\"")
-            .replace("b_element = \"u8\"", "b_element = \"u4\"");
-        let parsed_int4 = toml::from_str::<SparseMma>(&int4).unwrap();
-        assert_eq!(parsed_int4.a_element, SparseMmaElement::S4);
-        assert_eq!(parsed_int4.b_element, SparseMmaElement::U4);
-
-        let k128_int4 = int4
-            .replace("shape = \"m16n8k64\"", "shape = \"m16n8k128\"")
-            .replace(
-                "selector = \"immediate_zero_or_one\"",
-                "selector = \"immediate_zero\"",
-            )
-            .replace(
-                "adapter = \"c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32\"",
-                "adapter = \"c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32\"",
-            )
-            .replace(
-                "llvm_adapter = \"a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32\"",
-                "llvm_adapter = \"a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32\"",
-            );
-        let parsed_k128_int4 = toml::from_str::<SparseMma>(&k128_int4).unwrap();
-        assert_eq!(parsed_k128_int4.shape, SparseMmaShape::M16n8k128);
-        assert_eq!(parsed_k128_int4.selector, SparseMmaSelector::ImmediateZero);
-
-        for invalid in [
-            valid.replace(
-                "selector = \"immediate_zero_or_one\"",
-                "selector = \"runtime\"",
-            ),
-            valid.replace("metadata = \"standard\"", "metadata = \"unreviewed\""),
-            valid.replace(
-                "llvm_adapter = \"a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32\"",
-                "llvm_adapter = \"c_then_a_then_b\"",
-            ),
-            valid.replace("shape = \"m16n8k32\"", "shape = \"m16n8k256\""),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(toml::from_str::<SparseMma>(&invalid).is_err(), "{invalid}");
-        }
-    }
-
-    #[test]
-    fn sparse_mma_admission_accepts_the_canonical_name_and_legacy_alias() {
-        let canonical = r#"
-schema = 25
-family = "sparse_mma"
-
-[sparse_mma_integer]
-llvm_evidence_profile = "llvm"
-libnvvm_evidence_profile = "libnvvm"
-runtime_validation = "unexecuted"
-metadata = "ordered"
-
-[[sparse_mma_integer.variant]]
-shape = "m16n8k64"
-a_element = "s4"
-b_element = "u4"
-overflow = "wrapping"
-"#;
-        let parsed = toml::from_str::<OverlayShardFile>(canonical).unwrap();
-        assert_eq!(
-            parsed.sparse_mma_integer.unwrap().variants[0].b_element,
-            SparseMmaElement::U4
-        );
-
-        let legacy = canonical.replace("sparse_mma_integer", "sparse_mma_int8");
-        assert!(
-            toml::from_str::<OverlayShardFile>(&legacy)
-                .unwrap()
-                .sparse_mma_integer
-                .is_some()
-        );
-    }
-
-    #[test]
-    fn cp_async_mbarrier_contract_rejects_open_ended_policy() {
-        let valid = r#"
-operation = "arrive_no_inc"
-state_space = "shared"
-adapter = "pointer_to_void"
-runtime_validation = "unexecuted"
-"#;
-        let parsed = toml::from_str::<CpAsyncMbarrier>(valid).unwrap();
-        assert_eq!(parsed.operation, CpAsyncMbarrierOperation::ArriveNoInc);
-        assert_eq!(parsed.state_space, CpAsyncMbarrierStateSpace::Shared);
-
-        for invalid in [
-            valid.replace("operation = \"arrive_no_inc\"", "operation = \"wait\""),
-            valid.replace("state_space = \"shared\"", "state_space = \"global\""),
-            valid.replace("adapter = \"pointer_to_void\"", "adapter = \"direct\""),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(
-                toml::from_str::<CpAsyncMbarrier>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-    }
-
-    #[test]
-    fn cluster_barrier_contract_rejects_open_ended_semantics() {
-        let valid = r#"
-mode = "arrive_relaxed_aligned"
-ordering = "relaxed"
-aligned = true
-"#;
-        let parsed = toml::from_str::<ClusterBarrier>(valid).unwrap();
-        assert_eq!(parsed.mode, ClusterBarrierMode::ArriveRelaxedAligned);
-        assert_eq!(parsed.ordering, ClusterBarrierOrdering::Relaxed);
-        assert!(parsed.aligned);
-
-        for invalid in [
-            valid.replace("ordering = \"relaxed\"", "ordering = \"unordered\""),
-            valid.replace("aligned = true", "aligned = \"sometimes\""),
-            valid.replace(
-                "mode = \"arrive_relaxed_aligned\"",
-                "mode = \"arrive_release_aligned\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(
-                toml::from_str::<ClusterBarrier>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-    }
-
-    #[test]
-    fn debug_control_contract_rejects_open_ended_policy() {
-        let valid = r#"
-operation = "pmevent"
-adapter = "const_generic_to_immediate_u32"
-runtime_validation = "unexecuted"
-"#;
-        let parsed = toml::from_str::<DebugControl>(valid).unwrap();
-        assert_eq!(parsed.operation, DebugControlOperation::Pmevent);
-        assert_eq!(
-            parsed.adapter,
-            DebugControlAdapter::ConstGenericToImmediateU32
-        );
-
-        for invalid in [
-            valid.replace("operation = \"pmevent\"", "operation = \"profiler\""),
-            valid.replace(
-                "adapter = \"const_generic_to_immediate_u32\"",
-                "adapter = \"runtime_u32\"",
-            ),
-            valid.replace(
-                "runtime_validation = \"unexecuted\"",
-                "runtime_validation = \"assumed\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(
-                toml::from_str::<DebugControl>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-    }
-
-    #[test]
-    fn cluster_memory_contract_rejects_open_ended_policy() {
-        let valid = r#"
-operation = "map_shared_rank"
-adapter = "generic_const_and_mut_pointer_rank_to_same_pointer"
-source_contract = "llvm_mapa_shared_cluster_as7_identity_inline_ptx"
-runtime_validation = "unexecuted"
-"#;
-        let parsed = toml::from_str::<ClusterMemory>(valid).unwrap();
-        assert_eq!(parsed.operation, ClusterMemoryOperation::MapSharedRank);
-        assert_eq!(
-            parsed.source_contract,
-            ClusterMemorySourceContract::LlvmMapaSharedClusterAs7IdentityInlinePtx
-        );
-
-        for invalid in [
-            valid.replace("map_shared_rank", "map_generic_rank"),
-            valid.replace(
-                "generic_const_and_mut_pointer_rank_to_same_pointer",
-                "direct",
-            ),
-            valid.replace(
-                "llvm_mapa_shared_cluster_as7_identity_inline_ptx",
-                "llvm_typed_as3",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(
-                toml::from_str::<ClusterMemory>(&invalid).is_err(),
-                "{invalid}"
-            );
-        }
-    }
-
-    #[test]
-    fn clc_contract_rejects_open_ended_policy() {
-        let valid = r#"
-operation = "query_is_canceled"
-adapter = "pair_u64_to_i128_bool_to_u32"
-runtime_validation = "unexecuted"
-"#;
-        let parsed = toml::from_str::<Clc>(valid).unwrap();
-        assert_eq!(parsed.operation, ClcOperation::QueryIsCanceled);
-        assert_eq!(parsed.adapter, ClcAdapter::PairU64ToI128BoolToU32);
-
-        for invalid in [
-            valid.replace("operation = \"query_is_canceled\"", "operation = \"query\""),
-            valid.replace(
-                "adapter = \"pair_u64_to_i128_bool_to_u32\"",
-                "adapter = \"pair_u64_to_i128\"",
-            ),
-            valid.replace(
-                "runtime_validation = \"unexecuted\"",
-                "runtime_validation = \"assumed\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(toml::from_str::<Clc>(&invalid).is_err(), "{invalid}");
-        }
-    }
-
-    #[test]
-    fn tma_contract_rejects_open_ended_policy() {
-        let valid = r#"
-operation = "g2s_tile2d_multicast"
-adapter = "g2s_pointers_coordinates_barrier_mask_inject_defaults"
-runtime_validation = "unexecuted"
-"#;
-        let parsed = toml::from_str::<Tma>(valid).unwrap();
-        assert_eq!(parsed.operation, TmaOperation::G2sTile2dMulticast);
-        assert_eq!(
-            parsed.adapter,
-            TmaAdapter::G2sPointersCoordinatesBarrierMaskInjectDefaults
-        );
-
-        for invalid in [
-            valid.replace("g2s_tile2d_multicast", "g2s_multicast"),
-            valid.replace(
-                "g2s_pointers_coordinates_barrier_mask_inject_defaults",
-                "direct",
-            ),
-            valid.replace(
-                "runtime_validation = \"unexecuted\"",
-                "runtime_validation = \"assumed\"",
-            ),
-            format!("{valid}unreviewed = true\n"),
-        ] {
-            assert!(toml::from_str::<Tma>(&invalid).is_err(), "{invalid}");
-        }
-    }
-
-    #[test]
-    fn tcgen05_execution_scope_is_closed() {
-        for operation in [
-            Tcgen05Operation::Alloc,
-            Tcgen05Operation::Dealloc,
-            Tcgen05Operation::RelinquishAllocPermit,
-            Tcgen05Operation::AllocCg2,
-            Tcgen05Operation::DeallocCg2,
-            Tcgen05Operation::RelinquishAllocPermitCg2,
-            Tcgen05Operation::Ld16x256bX8Pure,
-            Tcgen05Operation::Ld16x256bPure,
-            Tcgen05Operation::LoadWait,
-            Tcgen05Operation::StoreWait,
-            Tcgen05Operation::Ld,
-            Tcgen05Operation::St,
-        ] {
-            assert_eq!(operation.execution_scope(), "warp");
-        }
-        for operation in [
-            Tcgen05Operation::FenceBeforeThreadSync,
-            Tcgen05Operation::FenceAfterThreadSync,
-            Tcgen05Operation::Commit,
-            Tcgen05Operation::CommitSharedCluster,
-            Tcgen05Operation::MmaWsF16,
-            Tcgen05Operation::MmaWsBf16,
-            Tcgen05Operation::MmaWsTf32,
-            Tcgen05Operation::MmaF16,
-            Tcgen05Operation::CpSmemToTmem,
-            Tcgen05Operation::MmaF16Cg2,
-            Tcgen05Operation::CommitCg2,
-            Tcgen05Operation::CommitSharedClusterCg2,
-            Tcgen05Operation::CommitMulticastCg2,
-            Tcgen05Operation::CpSmemToTmemCg2,
-            Tcgen05Operation::CommitMulticast,
-            Tcgen05Operation::ShiftDown,
-            Tcgen05Operation::ShiftDownCg2,
-        ] {
-            assert_eq!(operation.execution_scope(), "thread");
-        }
-    }
-}
diff --git a/crates/cuda-intrinsics-gen/src/model/abi_ledger.rs b/crates/cuda-intrinsics-gen/src/model/abi_ledger.rs
new file mode 100644
index 0000000000..9e9e496ad7
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/abi_ledger.rs
@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use serde::Deserialize;
+
+#[derive(Debug, Clone, PartialEq, Eq, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct AbiLedgerFile {
+    pub schema: u32,
+    pub intrinsic_abi: u32,
+    #[serde(rename = "entry")]
+    pub entries: Vec<AbiLedgerEntry>,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct AbiLedgerEntry {
+    pub abi_id: String,
+    pub status: String,
+    pub catalog_id: String,
+    pub operation_key: String,
+    pub raw_rust_signature: AbiRawRustSignature,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct AbiRawRustSignature {
+    pub safe: bool,
+    pub arguments: Vec<String>,
+    pub result: String,
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/catalog.rs b/crates/cuda-intrinsics-gen/src/model/catalog.rs
new file mode 100644
index 0000000000..064d40446c
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/catalog.rs
@@ -0,0 +1,458 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::contracts::{
+    ActiveMask, Clc, ClusterBarrier, ClusterMemory, CpAsyncControl, CpAsyncCopy, CpAsyncMbarrier,
+    DebugControl, DotProduct, ExtendedMinMax, IntegerMinMax, LdmatrixAdapter, LdmatrixSafety,
+    LdmatrixVariant, MbarrierBasic, MbarrierExtended, Movmatrix, PackedAlu, PackedAtomic,
+    PackedConversion, Prmt, Redux, RegisterMma, ScalarArithmetic, ScalarConversion, ScalarMath,
+    SparseMma, SpecialRegister, Tcgen05, Tma, Vote, WarpBarrier, WarpMatch, WarpShuffle,
+    WgmmaControl,
+};
+use super::core::{BackendLoweringMechanism, IntrinsicBackend, IntrinsicSource};
+use super::evidence::EvidenceStage;
+use super::imported::{ImportedAddressSpace, ImportedSelectionConstraints};
+use crate::ptx::InstructionPattern;
+use serde::{Deserialize, Serialize};
+use std::{fmt, str::FromStr};
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogFile {
+    pub schema: u32,
+    pub catalog_version: String,
+    pub intrinsic_abi: u32,
+    pub generator_version: String,
+    pub source: CatalogSource,
+    pub inputs: CatalogInputs,
+    pub intrinsics: Vec<CatalogIntrinsic>,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogSource {
+    pub llvm_repository: String,
+    pub llvm_revision: String,
+    pub llvm_tblgen_version: String,
+    pub llvm_tblgen_source_revision: String,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogInputs {
+    pub imported_sha256: String,
+    pub overlay_sha256: String,
+    pub abi_ledger_sha256: String,
+    pub evidence_sha256: Vec<String>,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogIntrinsic {
+    pub id: String,
+    pub operation_key: String,
+    pub family: String,
+    pub source: IntrinsicSource,
+    pub selections: Vec<CatalogSelection>,
+    pub rust: CatalogRust,
+    pub dialect: CatalogDialect,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub llvm: Option<CatalogLlvm>,
+    pub semantics: CatalogSemantics,
+    pub target: CatalogTarget,
+    pub backend: CatalogBackend,
+    #[serde(default, skip_serializing_if = "Vec::is_empty")]
+    pub backend_lowerings: Vec<CatalogBackendLowering>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub packed_atomic: Option<PackedAtomic>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub redux: Option<Redux>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub vote: Option<Vote>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub active_mask: Option<ActiveMask>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub warp_match: Option<WarpMatch>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub warp_barrier: Option<WarpBarrier>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub warp_shuffle: Option<WarpShuffle>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub dot_product: Option<DotProduct>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub packed_alu: Option<PackedAlu>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub integer_minmax: Option<IntegerMinMax>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub packed_conversion: Option<PackedConversion>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub scalar_conversion: Option<ScalarConversion>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub scalar_arithmetic: Option<ScalarArithmetic>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub scalar_math: Option<ScalarMath>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub extended_minmax: Option<ExtendedMinMax>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub cp_async_copy: Option<CpAsyncCopy>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub cp_async_control: Option<CpAsyncControl>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub cp_async_mbarrier: Option<CpAsyncMbarrier>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub mbarrier_basic: Option<MbarrierBasic>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub movmatrix: Option<Movmatrix>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub mbarrier_extended: Option<MbarrierExtended>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub register_mma: Option<RegisterMma>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub sparse_mma: Option<SparseMma>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub prmt: Option<Prmt>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub cluster_barrier: Option<ClusterBarrier>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub wgmma_control: Option<WgmmaControl>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub special_register: Option<SpecialRegister>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub debug_control: Option<DebugControl>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub cluster_memory: Option<ClusterMemory>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub clc: Option<Clc>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub tma: Option<Tma>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub tcgen05: Option<Tcgen05>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub ldmatrix: Option<CatalogLdmatrix>,
+    pub lowering: String,
+    pub expected_ptx: InstructionPattern,
+    pub summary: String,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogSelection {
+    pub source_record: String,
+    pub asm: String,
+    pub predicates: Vec<String>,
+    #[serde(
+        default,
+        skip_serializing_if = "ImportedSelectionConstraints::is_empty"
+    )]
+    pub constraints: ImportedSelectionConstraints,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogRust {
+    pub abi_id: String,
+    pub module: String,
+    pub name: String,
+    pub arguments: Vec<String>,
+    pub result: String,
+    pub safe: bool,
+    pub must_use: bool,
+    pub safe_allowlist_reason: Option<String>,
+    pub canonical_path: String,
+    pub public_path: String,
+    pub compatibility_paths: Vec<String>,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogDialect {
+    pub op_type: String,
+    pub op_name: String,
+    pub operands: Vec<String>,
+    pub results: Vec<String>,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogLlvm {
+    pub symbol: String,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub resolved_symbol: Option<String>,
+    pub arguments: Vec<String>,
+    pub results: Vec<String>,
+    pub properties: Vec<String>,
+    pub result_facts: CatalogLlvmResultFacts,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogLlvmResultFacts {
+    pub no_undef: bool,
+    pub range: Option<CatalogHalfOpenRange>,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogHalfOpenRange {
+    pub lower: String,
+    pub upper_exclusive: String,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogSemantics {
+    pub pure: bool,
+    pub memory: String,
+    pub convergent: bool,
+    pub execution_scope: String,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogTarget {
+    pub minimum_ptx: PtxVersion,
+    pub hardware: CatalogHardwareTarget,
+    pub ptx_result: String,
+    pub targets: String,
+    pub ptx_isa_version: String,
+    pub ptx_isa_section: String,
+    pub ptx_isa_url: String,
+}
+
+/// A PTX ISA version encoded as `major * 10 + minor`.
+///
+/// PTX currently uses one decimal minor digit. The resolver validates that
+/// shape before constructing this value, so generated consumers compare a
+/// number rather than reparsing policy text.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+pub struct PtxVersion(u16);
+
+impl PtxVersion {
+    pub const fn encoded(self) -> u16 {
+        self.0
+    }
+
+    pub const fn major(self) -> u16 {
+        self.0 / 10
+    }
+
+    pub const fn minor(self) -> u16 {
+        self.0 % 10
+    }
+}
+
+impl FromStr for PtxVersion {
+    type Err = String;
+
+    fn from_str(value: &str) -> Result<Self, Self::Err> {
+        let (major, minor) = value
+            .split_once('.')
+            .ok_or_else(|| "expected major.minor".to_owned())?;
+        if major.is_empty()
+            || !major.bytes().all(|byte| byte.is_ascii_digit())
+            || minor.len() != 1
+            || !minor.bytes().all(|byte| byte.is_ascii_digit())
+        {
+            return Err("expected numeric major.minor with one minor digit".to_owned());
+        }
+        let major: u16 = major.parse().map_err(|_| "major version is too large")?;
+        let minor: u16 = minor.parse().unwrap();
+        if format!("{major}.{minor}") != value {
+            return Err("version is not in canonical major.minor form".to_owned());
+        }
+        let encoded = major
+            .checked_mul(10)
+            .and_then(|value| value.checked_add(minor))
+            .ok_or_else(|| "version is too large".to_owned())?;
+        Ok(Self(encoded))
+    }
+}
+
+impl Serialize for PtxVersion {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: serde::Serializer,
+    {
+        serializer.serialize_str(&self.to_string())
+    }
+}
+
+impl<'de> Deserialize<'de> for PtxVersion {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: serde::Deserializer<'de>,
+    {
+        let value = String::deserialize(deserializer)?;
+        value.parse().map_err(serde::de::Error::custom)
+    }
+}
+
+impl fmt::Display for PtxVersion {
+    fn fmt(&self, formatter: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(formatter, "{}.{}", self.major(), self.minor())
+    }
+}
+
+/// Reviewed hardware availability for an intrinsic.
+///
+/// Exact `a` and `f` targets stay distinct from monotonic minimums. A target
+/// matrix also keeps each hardware target paired with its PTX floor.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(tag = "kind", rename_all = "snake_case")]
+pub enum CatalogHardwareTarget {
+    All,
+    AnyOf {
+        alternatives: Vec<CatalogHardwareAlternative>,
+    },
+    /// Closed selector contracts with their exact PTX and hardware pairs.
+    TargetMatrix {
+        contracts: Vec<CatalogTargetContract>,
+    },
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(tag = "kind", rename_all = "snake_case")]
+pub enum CatalogHardwareAlternative {
+    MinimumSm { sm: u16 },
+    ExactArchitecture { sm: u16 },
+    FamilyTarget { sm: u16 },
+}
+
+/// One PTX floor paired with one hardware alternative.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct CatalogTargetAlternative {
+    pub minimum_ptx: PtxVersion,
+    pub hardware: CatalogHardwareAlternative,
+}
+
+/// One selector tuple and its exact PTX and hardware pairs.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct CatalogTargetContract {
+    pub selectors: Vec<TargetSelectorBinding>,
+    pub alternatives: Vec<CatalogTargetAlternative>,
+}
+
+/// One field/value pair that selects a target contract.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct TargetSelectorBinding {
+    pub name: String,
+    pub value: String,
+}
+
+/// One selector-specific target contract from admission policy.
+#[allow(dead_code)]
+#[derive(Debug, Clone, PartialEq, Eq, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct TargetContract {
+    #[serde(default)]
+    pub selectors: Vec<TargetSelectorBinding>,
+    pub alternatives: Vec<TargetContractAlternative>,
+}
+
+/// One target spelling and PTX floor.
+#[derive(Debug, Clone, PartialEq, Eq, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct TargetContractAlternative {
+    pub target: String,
+    pub minimum_ptx: String,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogBackend {
+    pub profile: String,
+    pub version: String,
+    pub sha256: String,
+    pub status: String,
+    pub target_triple: String,
+    pub gpu_target: String,
+    pub ptx_feature: String,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogBackendLowering {
+    pub backend: IntrinsicBackend,
+    pub mechanism: BackendLoweringMechanism,
+    pub evidence_profile: String,
+    pub target: CatalogTargetRequirement,
+    pub version: String,
+    pub sha256: String,
+    pub artifact_path: Option<String>,
+    pub build_id_prefix: Option<String>,
+    pub status: String,
+    pub stages: Vec<EvidenceStage>,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogTargetRequirement {
+    pub minimum_ptx: PtxVersion,
+    pub hardware: CatalogHardwareTarget,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+pub struct CatalogLdmatrix {
+    pub variant: LdmatrixVariant,
+    pub safety: LdmatrixSafety,
+    pub adapter: LdmatrixAdapter,
+    pub selected_address_space: ImportedAddressSpace,
+}
+
+impl CatalogIntrinsic {
+    pub fn scalar_width(&self) -> Option<u32> {
+        match self.rust.result.as_str() {
+            "u32" => Some(32),
+            "u64" => Some(64),
+            _ => None,
+        }
+    }
+
+    pub fn llvm_identifier(&self) -> String {
+        llvm_symbol_to_identifier(&self.llvm.as_ref().expect("LLVM-backed intrinsic").symbol)
+    }
+
+    pub fn resolved_llvm_identifier(&self) -> String {
+        let llvm = self.llvm.as_ref().expect("LLVM-backed intrinsic");
+        llvm_symbol_to_identifier(llvm.resolved_symbol.as_deref().unwrap_or(&llvm.symbol))
+    }
+}
+
+fn llvm_symbol_to_identifier(symbol: &str) -> String {
+    if !symbol.contains('_') {
+        return symbol.replace('.', "_");
+    }
+
+    let suffix = symbol
+        .strip_prefix("llvm.")
+        .expect("LLVM intrinsic symbol must start with llvm.");
+    let mut output = String::from("llvm__");
+    for ch in suffix.chars() {
+        match ch {
+            '.' => output.push_str("_d"),
+            '_' => output.push_str("_u"),
+            ch if ch.is_ascii_alphanumeric() => output.push(ch),
+            _ => panic!("LLVM intrinsic symbol contains an unsupported character"),
+        }
+    }
+    output
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn llvm_identifier_encoding_preserves_literal_underscores() {
+        assert_eq!(
+            llvm_symbol_to_identifier("llvm.nvvm.read.ptx.sreg.tid.x"),
+            "llvm_nvvm_read_ptx_sreg_tid_x"
+        );
+        assert_eq!(
+            llvm_symbol_to_identifier("llvm.nvvm.wgmma.wait_group.sync.aligned"),
+            "llvm__nvvm_dwgmma_dwait_ugroup_dsync_daligned"
+        );
+        assert_eq!(
+            llvm_symbol_to_identifier(
+                "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8x16.b4x16_p64.p3"
+            ),
+            "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db4x16_up64_dp3"
+        );
+        assert_eq!(
+            llvm_symbol_to_identifier(
+                "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x4.b8x16.b6x16_p32.p3"
+            ),
+            "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx4_db8x16_db6x16_up32_dp3"
+        );
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/contracts/control.rs b/crates/cuda-intrinsics-gen/src/model/contracts/control.rs
new file mode 100644
index 0000000000..10225ce0ba
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/contracts/control.rs
@@ -0,0 +1,266 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::super::core::RuntimeValidation;
+use serde::{Deserialize, Serialize};
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WgmmaControlMode {
+    Fence,
+    CommitGroup,
+    WaitGroup,
+}
+
+/// Closed semantics for one WGMMA control operation.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct WgmmaControl {
+    pub mode: WgmmaControlMode,
+    pub adapter: WgmmaControlAdapter,
+    pub participation: WgmmaControlParticipation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WgmmaControlAdapter {
+    NoArguments,
+    ConstGenericU32ToI64Immediate,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WgmmaControlParticipation {
+    WarpgroupAllThreadsSameInstruction,
+}
+
+/// Closed semantic and lowering contract for one special-register read.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct SpecialRegister {
+    pub register: SpecialRegisterKind,
+    pub observation: SpecialRegisterObservation,
+    pub result_width: SpecialRegisterWidth,
+    pub ptx_type: SpecialRegisterPtxType,
+    pub output_constraint: SpecialRegisterOutputConstraint,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub llvm_exclusion: Option<SpecialRegisterLlvmExclusion>,
+}
+
+/// Closed semantic contract for PTX debug controls.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct DebugControl {
+    pub operation: DebugControlOperation,
+    pub adapter: DebugControlAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+/// Closed semantic contract for Cluster Launch Control.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Clc {
+    pub operation: ClcOperation,
+    pub adapter: ClcAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ClcOperation {
+    TryCancel,
+    TryCancelMulticast,
+    QueryIsCanceled,
+    QueryGetFirstCtaidX,
+    QueryGetFirstCtaidY,
+    QueryGetFirstCtaidZ,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ClcAdapter {
+    GenericPointersToShared,
+    PairU64ToI128BoolToU32,
+    PairU64ToI128U32,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SpecialRegisterKind {
+    Clock,
+    Clock64,
+    Globaltimer,
+    Envreg1,
+    Envreg2,
+    Smid,
+    Nsmid,
+    Gridid,
+    Warpid,
+    Nwarpid,
+    DynamicSmemSize,
+    TotalSmemSize,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum DebugControlOperation {
+    Trap,
+    Breakpoint,
+    Pmevent,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SpecialRegisterObservation {
+    StablePure,
+    VolatileObservation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SpecialRegisterWidth {
+    B32,
+    B64,
+}
+
+impl SpecialRegisterWidth {
+    pub const fn bits(self) -> u32 {
+        match self {
+            Self::B32 => 32,
+            Self::B64 => 64,
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SpecialRegisterPtxType {
+    B32,
+    U32,
+    U64,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SpecialRegisterOutputConstraint {
+    Register32,
+    Register64,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct SpecialRegisterLlvmExclusion {
+    pub source_record: String,
+    pub llvm_symbol: String,
+    pub imported_result_width: SpecialRegisterWidth,
+    pub reason: SpecialRegisterLlvmExclusionReason,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SpecialRegisterLlvmExclusionReason {
+    ResultWidthMismatch,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum DebugControlAdapter {
+    Direct,
+    ConstGenericToImmediateU32,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn wgmma_control_contract_is_closed() {
+        let parsed: WgmmaControl = serde_json::from_str(
+            r#"{
+                "mode": "wait_group",
+                "adapter": "const_generic_u32_to_i64_immediate",
+                "participation": "warpgroup_all_threads_same_instruction"
+            }"#,
+        )
+        .unwrap();
+        assert_eq!(parsed.mode, WgmmaControlMode::WaitGroup);
+        assert_eq!(
+            parsed.adapter,
+            WgmmaControlAdapter::ConstGenericU32ToI64Immediate
+        );
+        assert_eq!(
+            parsed.participation,
+            WgmmaControlParticipation::WarpgroupAllThreadsSameInstruction
+        );
+
+        let open_ended = r#"{
+            "mode": "wait_group",
+            "adapter": "const_generic_u32_to_i64_immediate",
+            "participation": "warpgroup_all_threads_same_instruction",
+            "custom_ptx": "wgmma.wait_group.sync.aligned 0;"
+        }"#;
+        assert!(serde_json::from_str::<WgmmaControl>(open_ended).is_err());
+    }
+
+    #[test]
+    fn debug_control_contract_rejects_open_ended_policy() {
+        let valid = r#"
+operation = "pmevent"
+adapter = "const_generic_to_immediate_u32"
+runtime_validation = "unexecuted"
+"#;
+        let parsed = toml::from_str::<DebugControl>(valid).unwrap();
+        assert_eq!(parsed.operation, DebugControlOperation::Pmevent);
+        assert_eq!(
+            parsed.adapter,
+            DebugControlAdapter::ConstGenericToImmediateU32
+        );
+
+        for invalid in [
+            valid.replace("operation = \"pmevent\"", "operation = \"profiler\""),
+            valid.replace(
+                "adapter = \"const_generic_to_immediate_u32\"",
+                "adapter = \"runtime_u32\"",
+            ),
+            valid.replace(
+                "runtime_validation = \"unexecuted\"",
+                "runtime_validation = \"assumed\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(
+                toml::from_str::<DebugControl>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+    }
+
+    #[test]
+    fn clc_contract_rejects_open_ended_policy() {
+        let valid = r#"
+operation = "query_is_canceled"
+adapter = "pair_u64_to_i128_bool_to_u32"
+runtime_validation = "unexecuted"
+"#;
+        let parsed = toml::from_str::<Clc>(valid).unwrap();
+        assert_eq!(parsed.operation, ClcOperation::QueryIsCanceled);
+        assert_eq!(parsed.adapter, ClcAdapter::PairU64ToI128BoolToU32);
+
+        for invalid in [
+            valid.replace("operation = \"query_is_canceled\"", "operation = \"query\""),
+            valid.replace(
+                "adapter = \"pair_u64_to_i128_bool_to_u32\"",
+                "adapter = \"pair_u64_to_i128\"",
+            ),
+            valid.replace(
+                "runtime_validation = \"unexecuted\"",
+                "runtime_validation = \"assumed\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(toml::from_str::<Clc>(&invalid).is_err(), "{invalid}");
+        }
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs b/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs
new file mode 100644
index 0000000000..d62f5562d1
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs
@@ -0,0 +1,605 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::super::core::RuntimeValidation;
+use serde::{Deserialize, Serialize};
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum StmatrixMultiplicity {
+    X2,
+    X4,
+}
+
+impl StmatrixMultiplicity {
+    pub const fn register_count(self) -> usize {
+        match self {
+            Self::X2 => 2,
+            Self::X4 => 4,
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum StmatrixLayout {
+    Normal,
+    Transposed,
+}
+
+/// Closed semantic identity for the generated `ldmatrix` family.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct LdmatrixVariant {
+    pub shape: LdmatrixShape,
+    pub multiplicity: LdmatrixMultiplicity,
+    pub layout: LdmatrixLayout,
+    pub element: LdmatrixElement,
+    pub state_space: LdmatrixStateSpace,
+}
+
+impl LdmatrixVariant {
+    pub const fn register_count(&self) -> usize {
+        let matrices = self.multiplicity.register_count();
+        match self.shape {
+            LdmatrixShape::M8n8 | LdmatrixShape::M8n16 => matrices,
+            LdmatrixShape::M16n16 => matrices * 2,
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum LdmatrixShape {
+    M8n8,
+    M8n16,
+    M16n16,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum LdmatrixMultiplicity {
+    X1,
+    X2,
+    X4,
+}
+
+impl LdmatrixMultiplicity {
+    pub const fn register_count(self) -> usize {
+        match self {
+            Self::X1 => 1,
+            Self::X2 => 2,
+            Self::X4 => 4,
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum LdmatrixLayout {
+    Normal,
+    Transposed,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum LdmatrixElement {
+    B16,
+    B8,
+    B8x16B4x16P64,
+    B8x16B6x16P32,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum LdmatrixStateSpace {
+    Shared,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct LdmatrixSafety {
+    pub participation: LdmatrixParticipation,
+    pub address_contract: LdmatrixAddressContract,
+    pub memory_order: LdmatrixMemoryOrder,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum LdmatrixParticipation {
+    AllWarpLanesSameInstruction,
+    AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum LdmatrixAddressContract {
+    WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadableWithSm75Replication,
+    WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadable,
+    WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedThirtyTwoBytesReadable,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum LdmatrixMemoryOrder {
+    Weak,
+}
+
+/// Closed contract for the in-register warp matrix transpose.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Movmatrix {
+    pub participation: MovmatrixParticipation,
+    pub adapter: MovmatrixAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum MovmatrixParticipation {
+    AllWarpLanesSameInstructionNoExitedLanes,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum MovmatrixAdapter {
+    PackedB16x2U32ToPackedB16x2U32,
+}
+
+/// Closed contract for register-only warp-level `mma.sync` operations.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct RegisterMma {
+    pub shape: RegisterMmaShape,
+    pub operation: RegisterMmaOperation,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub kind: Option<RegisterMmaKind>,
+    pub accumulator: RegisterMmaAccumulator,
+    pub a_element: RegisterMmaElement,
+    pub b_element: RegisterMmaElement,
+    pub a_layout: RegisterMmaLayout,
+    pub b_layout: RegisterMmaLayout,
+    pub overflow: RegisterMmaOverflow,
+    pub participation: RegisterMmaParticipation,
+    pub adapter: RegisterMmaAdapter,
+    pub compatibility_source: RegisterMmaCompatibilitySource,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RegisterMmaKind {
+    Standard,
+    F8f6f4,
+    Mxf8f6f4,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RegisterMmaShape {
+    M8n8k4,
+    M8n8k16,
+    M8n8k32,
+    M16n8k4,
+    M16n8k8,
+    M16n8k16,
+    M16n8k32,
+    M16n8k64,
+    M8n8k128,
+    M16n8k128,
+    M16n8k256,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RegisterMmaOperation {
+    Multiply,
+    AndPopc,
+    XorPopc,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RegisterMmaAccumulator {
+    F16,
+    F32,
+    F64,
+    S32,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RegisterMmaElement {
+    B1,
+    Bf16,
+    E2m1,
+    E2m3,
+    E3m2,
+    E4m3,
+    E5m2,
+    F16,
+    Tf32,
+    F64,
+    S4,
+    U4,
+    S8,
+    U8,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RegisterMmaLayout {
+    Row,
+    Col,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RegisterMmaOverflow {
+    NotApplicable,
+    Wrapping,
+    Satfinite,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RegisterMmaParticipation {
+    AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+}
+
+/// Rust `C, A, B` fragment shape used by the importer.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RegisterMmaAdapter {
+    C2U32A2U32B1U32ToD2U32,
+    C2U32A4U32B2U32ToD2U32,
+    C4F32A2U32B1U32ToD4F32,
+    C4F32A4U32B2U32ToD4F32,
+    C2F64A1F64B1F64ToD2F64,
+    C2I32A1U32B1U32ToD2I32,
+    C4I32A4U32B2U32ToD4I32,
+    C4I32A2U32B1U32ToD4I32,
+    C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+}
+
+/// Where the stable `cuda_device::wmma` callable is defined.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RegisterMmaCompatibilitySource {
+    ExistingStub,
+    GeneratedStub,
+}
+
+/// Closed semantic contract for register-only sparse `mma.sp` operations.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct SparseMma {
+    pub shape: SparseMmaShape,
+    pub accumulator: SparseMmaAccumulator,
+    pub a_element: SparseMmaElement,
+    pub b_element: SparseMmaElement,
+    pub a_layout: SparseMmaLayout,
+    pub b_layout: SparseMmaLayout,
+    pub overflow: SparseMmaOverflow,
+    pub metadata: SparseMmaMetadata,
+    pub selector: SparseMmaSelector,
+    pub participation: SparseMmaParticipation,
+    pub adapter: SparseMmaAdapter,
+    pub llvm_adapter: SparseMmaLlvmAdapter,
+    pub compatibility_source: SparseMmaCompatibilitySource,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaShape {
+    M16n8k32,
+    M16n8k64,
+    M16n8k128,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaAccumulator {
+    F16,
+    F32,
+    S32,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaElement {
+    E2m1,
+    E2m3,
+    E3m2,
+    E4m3,
+    E5m2,
+    S4,
+    U4,
+    S8,
+    U8,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaLayout {
+    Row,
+    Col,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaOverflow {
+    NotApplicable,
+    Wrapping,
+    Satfinite,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaMetadata {
+    Standard,
+    Ordered,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaSelector {
+    ImmediateZeroOrOne,
+    ImmediateZero,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaParticipation {
+    AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+}
+
+/// Rust `C, A, B, metadata, selector` shape used by the importer.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaAdapter {
+    C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32,
+    C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32,
+    C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32,
+    C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32,
+}
+
+/// LLVM `A, B, C, metadata, selector` shape.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaLlvmAdapter {
+    A4I32B4I32C2V2F16MetadataI32SelectorI32ToD2V2F16,
+    A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32,
+    A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32,
+    A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32,
+}
+
+/// Where the stable `cuda_device::wmma` callable is defined.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum SparseMmaCompatibilitySource {
+    GeneratedStub,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum LdmatrixAdapter {
+    SingleResultDirect,
+    MultipleResultsToArray,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn ldmatrix_register_count_includes_the_shape_width() {
+        let variant = |shape, multiplicity| LdmatrixVariant {
+            shape,
+            multiplicity,
+            layout: LdmatrixLayout::Normal,
+            element: LdmatrixElement::B8,
+            state_space: LdmatrixStateSpace::Shared,
+        };
+
+        assert_eq!(
+            variant(LdmatrixShape::M8n16, LdmatrixMultiplicity::X4).register_count(),
+            4
+        );
+        assert_eq!(
+            variant(LdmatrixShape::M16n16, LdmatrixMultiplicity::X1).register_count(),
+            2
+        );
+        assert_eq!(
+            variant(LdmatrixShape::M16n16, LdmatrixMultiplicity::X2).register_count(),
+            4
+        );
+    }
+
+    #[test]
+    fn blackwell_ldmatrix_address_contracts_keep_readable_widths_distinct() {
+        assert_eq!(
+            serde_json::from_str::<LdmatrixAddressContract>(
+                r#""warp_lane_addresses_mapped_by_multiplicity_sixteen_byte_aligned_sixteen_bytes_readable""#
+            )
+            .unwrap(),
+            LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadable
+        );
+        assert_eq!(
+            serde_json::from_str::<LdmatrixAddressContract>(
+                r#""warp_lane_addresses_mapped_by_multiplicity_sixteen_byte_aligned_thirty_two_bytes_readable""#
+            )
+            .unwrap(),
+            LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedThirtyTwoBytesReadable
+        );
+    }
+
+    #[test]
+    fn movmatrix_contract_rejects_open_ended_policy() {
+        let valid = r#"
+participation = "all_warp_lanes_same_instruction_no_exited_lanes"
+adapter = "packed_b16x2_u32_to_packed_b16x2_u32"
+runtime_validation = "unexecuted"
+"#;
+        let parsed = toml::from_str::<Movmatrix>(valid).unwrap();
+        assert_eq!(
+            parsed.participation,
+            MovmatrixParticipation::AllWarpLanesSameInstructionNoExitedLanes
+        );
+
+        for invalid in [
+            valid.replace(
+                "all_warp_lanes_same_instruction_no_exited_lanes",
+                "participating_lanes",
+            ),
+            valid.replace("packed_b16x2_u32_to_packed_b16x2_u32", "direct_u32"),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(toml::from_str::<Movmatrix>(&invalid).is_err(), "{invalid}");
+        }
+    }
+
+    #[test]
+    fn register_mma_contract_parses_unsigned_k16_generated_stub() {
+        let valid = r#"
+shape = "m16n8k16"
+operation = "multiply"
+accumulator = "s32"
+a_element = "s8"
+b_element = "u8"
+a_layout = "row"
+b_layout = "col"
+overflow = "satfinite"
+participation = "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes"
+adapter = "c4_i32_a2_u32_b1_u32_to_d4_i32"
+compatibility_source = "generated_stub"
+runtime_validation = "unexecuted"
+"#;
+        let parsed = toml::from_str::<RegisterMma>(valid).unwrap();
+        assert_eq!(parsed.b_element, RegisterMmaElement::U8);
+        assert_eq!(parsed.adapter, RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32);
+        assert_eq!(
+            parsed.compatibility_source,
+            RegisterMmaCompatibilitySource::GeneratedStub
+        );
+
+        for invalid in [
+            valid.replace("b_element = \"u8\"", "b_element = \"i8\""),
+            valid.replace(
+                "adapter = \"c4_i32_a2_u32_b1_u32_to_d4_i32\"",
+                "adapter = \"direct\"",
+            ),
+            valid.replace(
+                "compatibility_source = \"generated_stub\"",
+                "compatibility_source = \"automatic\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(
+                toml::from_str::<RegisterMma>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+    }
+
+    #[test]
+    fn sparse_mma_contract_closes_the_selector_and_metadata_modes() {
+        let valid = r#"
+shape = "m16n8k32"
+accumulator = "s32"
+a_element = "s8"
+b_element = "u8"
+a_layout = "row"
+b_layout = "col"
+overflow = "satfinite"
+metadata = "standard"
+selector = "immediate_zero_or_one"
+participation = "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes"
+adapter = "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32"
+llvm_adapter = "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32"
+compatibility_source = "generated_stub"
+runtime_validation = "unexecuted"
+"#;
+        let parsed = toml::from_str::<SparseMma>(valid).unwrap();
+        assert_eq!(parsed.metadata, SparseMmaMetadata::Standard);
+        assert_eq!(parsed.selector, SparseMmaSelector::ImmediateZeroOrOne);
+
+        let ordered = valid.replace("metadata = \"standard\"", "metadata = \"ordered\"");
+        assert_eq!(
+            toml::from_str::<SparseMma>(&ordered).unwrap().metadata,
+            SparseMmaMetadata::Ordered
+        );
+
+        let k64 = ordered
+            .replace("shape = \"m16n8k32\"", "shape = \"m16n8k64\"")
+            .replace(
+                "selector = \"immediate_zero_or_one\"",
+                "selector = \"immediate_zero\"",
+            )
+            .replace(
+                "adapter = \"c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32\"",
+                "adapter = \"c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32\"",
+            )
+            .replace(
+                "llvm_adapter = \"a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32\"",
+                "llvm_adapter = \"a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32\"",
+            );
+        let parsed_k64 = toml::from_str::<SparseMma>(&k64).unwrap();
+        assert_eq!(parsed_k64.shape, SparseMmaShape::M16n8k64);
+        assert_eq!(parsed_k64.selector, SparseMmaSelector::ImmediateZero);
+        assert_eq!(
+            parsed_k64.adapter,
+            SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32
+        );
+        assert_eq!(
+            parsed_k64.llvm_adapter,
+            SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32
+        );
+
+        let int4 = ordered
+            .replace("shape = \"m16n8k32\"", "shape = \"m16n8k64\"")
+            .replace("a_element = \"s8\"", "a_element = \"s4\"")
+            .replace("b_element = \"u8\"", "b_element = \"u4\"");
+        let parsed_int4 = toml::from_str::<SparseMma>(&int4).unwrap();
+        assert_eq!(parsed_int4.a_element, SparseMmaElement::S4);
+        assert_eq!(parsed_int4.b_element, SparseMmaElement::U4);
+
+        let k128_int4 = int4
+            .replace("shape = \"m16n8k64\"", "shape = \"m16n8k128\"")
+            .replace(
+                "selector = \"immediate_zero_or_one\"",
+                "selector = \"immediate_zero\"",
+            )
+            .replace(
+                "adapter = \"c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32\"",
+                "adapter = \"c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32\"",
+            )
+            .replace(
+                "llvm_adapter = \"a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32\"",
+                "llvm_adapter = \"a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32\"",
+            );
+        let parsed_k128_int4 = toml::from_str::<SparseMma>(&k128_int4).unwrap();
+        assert_eq!(parsed_k128_int4.shape, SparseMmaShape::M16n8k128);
+        assert_eq!(parsed_k128_int4.selector, SparseMmaSelector::ImmediateZero);
+
+        for invalid in [
+            valid.replace(
+                "selector = \"immediate_zero_or_one\"",
+                "selector = \"runtime\"",
+            ),
+            valid.replace("metadata = \"standard\"", "metadata = \"unreviewed\""),
+            valid.replace(
+                "llvm_adapter = \"a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32\"",
+                "llvm_adapter = \"c_then_a_then_b\"",
+            ),
+            valid.replace("shape = \"m16n8k32\"", "shape = \"m16n8k256\""),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(toml::from_str::<SparseMma>(&invalid).is_err(), "{invalid}");
+        }
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/contracts/memory.rs b/crates/cuda-intrinsics-gen/src/model/contracts/memory.rs
new file mode 100644
index 0000000000..be03a8862d
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/contracts/memory.rs
@@ -0,0 +1,464 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::super::core::RuntimeValidation;
+use serde::{Deserialize, Serialize};
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum MbarrierExtendedOperation {
+    ArriveExpectTxCta,
+    ArriveExpectTxCluster,
+    ArriveRemoteCluster,
+    TryWaitTokenCta,
+    TryWaitParityCta,
+    TryWaitParityCluster,
+    FenceProxyAsyncSharedCta,
+    FenceMbarrierInitReleaseCluster,
+    FenceProxyAsyncGenericReleaseSharedCtaCluster,
+    FenceProxyAsyncGenericAcquireSharedClusterCluster,
+    Nanosleep,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ClusterMemoryOperation {
+    MapSharedRank,
+    ReadU32,
+}
+
+/// Closed contract for cluster address mapping and remote shared reads.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ClusterMemory {
+    pub operation: ClusterMemoryOperation,
+    pub adapter: ClusterMemoryAdapter,
+    pub source_contract: ClusterMemorySourceContract,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ClusterMemoryAdapter {
+    GenericConstAndMutPointerRankToSamePointer,
+    ConstU32PointerRankToU32,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ClusterMemorySourceContract {
+    LlvmMapaSharedClusterAs7IdentityInlinePtx,
+    PtxNativeMapaThenWeakClusterLoad,
+}
+
+/// Closed semantic contract for the generated packed global atomic-add
+/// family. These fields are intentionally enums rather than free-form strings:
+/// accepting an unreviewed state space, scope, or floating-point mode must
+/// require a generator change.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct PackedAtomic {
+    pub format: PackedAtomicFormat,
+    /// PTX ISA hardware floor, kept separate from cuda-oxide's admitted floor
+    /// and from backend-profile floors.
+    pub native_minimum_sm: u16,
+    pub operation: PackedAtomicOperation,
+    pub state_space: PackedAtomicStateSpace,
+    pub ordering: PackedAtomicOrdering,
+    pub scope: PackedAtomicScope,
+    pub rounding: PackedAtomicRounding,
+    pub subnormal: PackedAtomicSubnormal,
+    pub atomicity: PackedAtomicAtomicity,
+    pub pointer_contract: PackedAtomicPointerContract,
+    pub access_contract: PackedAtomicAccessContract,
+    pub scope_contract: PackedAtomicScopeContract,
+    pub codegen_contract: PackedAtomicCodegenContract,
+    pub return_contract: PackedAtomicReturnContract,
+    pub adapter: PackedAtomicAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicFormat {
+    F16x2,
+    Bf16x2,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicOperation {
+    Add,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicStateSpace {
+    Global,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicOrdering {
+    Relaxed,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicScope {
+    Gpu,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicRounding {
+    NearestEven,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicSubnormal {
+    Preserve,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicAtomicity {
+    PerElement,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicPointerContract {
+    MutableGlobalU32Aligned4,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicAccessContract {
+    NoMixedWholeWordOrNonAtomicAccess,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicScopeContract {
+    RacingAtomicsMutuallyInclusive,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicCodegenContract {
+    ExactNativeInstruction,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicReturnContract {
+    OldValuesPerElementMayBeNoncoherent,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAtomicAdapter {
+    OldPackedU32,
+}
+
+/// Closed contract for classic global-to-shared `cp.async` copies.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct CpAsyncCopy {
+    pub cache_policy: CpAsyncCachePolicy,
+    pub copy_size: CpAsyncCopySize,
+    pub source_size: CpAsyncSourceSize,
+    pub adapter: CpAsyncAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum CpAsyncCachePolicy {
+    Ca,
+    Cg,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum CpAsyncCopySize {
+    B4,
+    B8,
+    B16,
+}
+
+impl CpAsyncCopySize {
+    pub const fn bytes(self) -> u32 {
+        match self {
+            Self::B4 => 4,
+            Self::B8 => 8,
+            Self::B16 => 16,
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum CpAsyncSourceSize {
+    Full,
+    Runtime,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum CpAsyncAdapter {
+    DirectPointers,
+    DirectPointersAndSourceSize,
+}
+
+/// Closed contract for classic `cp.async` group controls.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct CpAsyncControl {
+    pub operation: CpAsyncControlOperation,
+    pub adapter: CpAsyncControlAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum CpAsyncControlOperation {
+    CommitGroup,
+    WaitAll,
+    WaitGroup,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum CpAsyncControlAdapter {
+    NoOperands,
+    CompileTimeConstantMaxPending,
+}
+
+/// Closed contract for associating classic `cp.async` completion with an mbarrier.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct CpAsyncMbarrier {
+    pub operation: CpAsyncMbarrierOperation,
+    pub state_space: CpAsyncMbarrierStateSpace,
+    pub adapter: CpAsyncMbarrierAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum CpAsyncMbarrierOperation {
+    Arrive,
+    ArriveNoInc,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum CpAsyncMbarrierStateSpace {
+    Generic,
+    Shared,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum CpAsyncMbarrierAdapter {
+    PointerToVoid,
+}
+
+/// Closed contract for the basic shared-memory mbarrier lifecycle.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct MbarrierBasic {
+    pub operation: MbarrierBasicOperation,
+    pub state_space: MbarrierStateSpace,
+    pub adapter: MbarrierBasicAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum MbarrierBasicOperation {
+    Init,
+    Arrive,
+    TestWait,
+    Inval,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum MbarrierStateSpace {
+    Shared,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum MbarrierBasicAdapter {
+    #[serde(rename = "pointer_count_to_void")]
+    InitPointerCountToVoid,
+    #[serde(rename = "pointer_to_token")]
+    ArrivePointerToToken,
+    #[serde(rename = "pointer_token_to_predicate")]
+    TestWaitPointerTokenToPredicate,
+    #[serde(rename = "pointer_to_void")]
+    InvalPointerToVoid,
+}
+
+/// Closed contract for the remaining handwritten mbarrier operations.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct MbarrierExtended {
+    pub operation: MbarrierExtendedOperation,
+    pub adapter: MbarrierExtendedAdapter,
+    pub source_contract: MbarrierExtendedSourceContract,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum MbarrierExtendedAdapter {
+    PointerTxCountBytesToTokenDroppingTxCount,
+    RawClusterAddressToVoid,
+    PointerTokenToPredicate,
+    PointerParityToPredicate,
+    ZeroOperandsToVoid,
+    NanosecondsToVoid,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum MbarrierExtendedSourceContract {
+    LlvmImported,
+    PtxNativeRawClusterAddress,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn mbarrier_basic_contract_rejects_open_ended_policy() {
+        let valid = r#"
+operation = "test_wait"
+state_space = "shared"
+adapter = "pointer_token_to_predicate"
+runtime_validation = "unexecuted"
+"#;
+        let parsed = toml::from_str::<MbarrierBasic>(valid).unwrap();
+        assert_eq!(parsed.operation, MbarrierBasicOperation::TestWait);
+        assert_eq!(
+            parsed.adapter,
+            MbarrierBasicAdapter::TestWaitPointerTokenToPredicate
+        );
+
+        for invalid in [
+            valid.replace("operation = \"test_wait\"", "operation = \"wait\""),
+            valid.replace("state_space = \"shared\"", "state_space = \"global\""),
+            valid.replace(
+                "adapter = \"pointer_token_to_predicate\"",
+                "adapter = \"direct\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(
+                toml::from_str::<MbarrierBasic>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+    }
+
+    #[test]
+    fn mbarrier_extended_contract_rejects_open_ended_policy() {
+        let valid = r#"
+operation = "arrive_expect_tx_cta"
+adapter = "pointer_tx_count_bytes_to_token_dropping_tx_count"
+source_contract = "llvm_imported"
+runtime_validation = "unexecuted"
+"#;
+        let parsed = toml::from_str::<MbarrierExtended>(valid).unwrap();
+        assert_eq!(
+            parsed.adapter,
+            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount
+        );
+        assert_eq!(
+            parsed.source_contract,
+            MbarrierExtendedSourceContract::LlvmImported
+        );
+
+        for invalid in [
+            valid.replace("llvm_imported", "auto"),
+            valid.replace(
+                "pointer_tx_count_bytes_to_token_dropping_tx_count",
+                "direct",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(
+                toml::from_str::<MbarrierExtended>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+    }
+
+    #[test]
+    fn cp_async_mbarrier_contract_rejects_open_ended_policy() {
+        let valid = r#"
+operation = "arrive_no_inc"
+state_space = "shared"
+adapter = "pointer_to_void"
+runtime_validation = "unexecuted"
+"#;
+        let parsed = toml::from_str::<CpAsyncMbarrier>(valid).unwrap();
+        assert_eq!(parsed.operation, CpAsyncMbarrierOperation::ArriveNoInc);
+        assert_eq!(parsed.state_space, CpAsyncMbarrierStateSpace::Shared);
+
+        for invalid in [
+            valid.replace("operation = \"arrive_no_inc\"", "operation = \"wait\""),
+            valid.replace("state_space = \"shared\"", "state_space = \"global\""),
+            valid.replace("adapter = \"pointer_to_void\"", "adapter = \"direct\""),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(
+                toml::from_str::<CpAsyncMbarrier>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+    }
+
+    #[test]
+    fn cluster_memory_contract_rejects_open_ended_policy() {
+        let valid = r#"
+operation = "map_shared_rank"
+adapter = "generic_const_and_mut_pointer_rank_to_same_pointer"
+source_contract = "llvm_mapa_shared_cluster_as7_identity_inline_ptx"
+runtime_validation = "unexecuted"
+"#;
+        let parsed = toml::from_str::<ClusterMemory>(valid).unwrap();
+        assert_eq!(parsed.operation, ClusterMemoryOperation::MapSharedRank);
+        assert_eq!(
+            parsed.source_contract,
+            ClusterMemorySourceContract::LlvmMapaSharedClusterAs7IdentityInlinePtx
+        );
+
+        for invalid in [
+            valid.replace("map_shared_rank", "map_generic_rank"),
+            valid.replace(
+                "generic_const_and_mut_pointer_rank_to_same_pointer",
+                "direct",
+            ),
+            valid.replace(
+                "llvm_mapa_shared_cluster_as7_identity_inline_ptx",
+                "llvm_typed_as3",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(
+                toml::from_str::<ClusterMemory>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/contracts/mod.rs b/crates/cuda-intrinsics-gen/src/model/contracts/mod.rs
new file mode 100644
index 0000000000..b92f736bda
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/contracts/mod.rs
@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+mod control;
+mod matrix;
+mod memory;
+mod scalar;
+mod tcgen05;
+mod tma;
+mod warp;
+
+pub use self::control::*;
+pub use self::matrix::*;
+pub use self::memory::*;
+pub use self::scalar::*;
+pub use self::tcgen05::*;
+pub use self::tma::*;
+pub use self::warp::*;
diff --git a/crates/cuda-intrinsics-gen/src/model/contracts/scalar.rs b/crates/cuda-intrinsics-gen/src/model/contracts/scalar.rs
new file mode 100644
index 0000000000..257a1a85e5
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/contracts/scalar.rs
@@ -0,0 +1,511 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::super::core::RuntimeValidation;
+use serde::{Deserialize, Serialize};
+
+/// Closed semantic contract for byte permutation.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Prmt {
+    pub mode: PrmtMode,
+    pub adapter: PrmtAdapter,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PrmtMode {
+    Generic,
+    F4e,
+    B4e,
+    Rc8,
+    Ecl,
+    Ecr,
+    Rc16,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PrmtAdapter {
+    DirectThreeOperands,
+    InsertZeroSecondSource,
+}
+
+/// Closed identity and source adapter for generated packed integer dot products.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct DotProduct {
+    pub operation: DotProductOperation,
+    pub signedness: DotProductSignedness,
+    pub adapter: DotProductAdapter,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum DotProductOperation {
+    Dp2a,
+    Dp4a,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum DotProductSignedness {
+    Signed,
+    Unsigned,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum DotProductAdapter {
+    DirectThreeOperands,
+    InsertLowHalfFalse,
+}
+
+/// Closed identity and carrier contract for packed floating-point ALU ops.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct PackedAlu {
+    pub format: PackedAluFormat,
+    /// Hardware floor of the native PTX instruction, independent of the
+    /// target floor admitted by cuda-oxide.
+    pub native_minimum_sm: u16,
+    pub operation: PackedAluOperation,
+    pub adapter: PackedAluAdapter,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAluFormat {
+    Bf16x2,
+    F16x2,
+    F32x2,
+}
+
+/// Closed identity and carrier contract for extended integer min/max ops.
+///
+/// Covers the PTX ISA 8.0 integer min/max extensions: the `.relu` saturation
+/// qualifier on `s32` and `s16x2`, plus the packed `s16x2`/`u16x2` forms.
+/// These are the DPX-adjacent shapes ptxas fuses into `VIMNMX`-family SASS.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct IntegerMinMax {
+    pub format: IntegerMinMaxFormat,
+    /// Hardware floor of the native PTX instruction, independent of the
+    /// target floor admitted by cuda-oxide.
+    pub native_minimum_sm: u16,
+    pub operation: IntegerMinMaxOperation,
+    pub relu: bool,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum IntegerMinMaxFormat {
+    S32,
+    S16x2,
+    U16x2,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum IntegerMinMaxOperation {
+    Min,
+    Max,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAluOperation {
+    Add,
+    AddFtz,
+    Sub,
+    SubFtz,
+    Mul,
+    MulFtz,
+    Fma,
+    FmaFtz,
+    FmaSat,
+    FmaFtzSat,
+    FmaRelu,
+    FmaFtzRelu,
+    Min,
+    Max,
+    Neg,
+    Abs,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedAluAdapter {
+    DirectPackedU32,
+    DirectPackedU64,
+}
+
+/// Closed contract for scalar floating-point arithmetic.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ScalarArithmetic {
+    pub format: ScalarArithmeticFormat,
+    pub operation: ScalarArithmeticOperation,
+    pub rounding: ScalarArithmeticRounding,
+    pub subnormal: ScalarArithmeticSubnormal,
+    pub saturation: ScalarArithmeticSaturation,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarArithmeticFormat {
+    F32,
+    F64,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarArithmeticOperation {
+    Mul,
+    Div,
+    Fma,
+    Add,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarArithmeticRounding {
+    Rn,
+    Rz,
+    Rm,
+    Rp,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarArithmeticSubnormal {
+    Preserve,
+    Ftz,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarArithmeticSaturation {
+    None,
+    Sat,
+}
+
+/// Closed contract for unary scalar floating-point math operations.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ScalarMath {
+    pub format: ScalarMathFormat,
+    pub operation: ScalarMathOperation,
+    pub precision: ScalarMathPrecision,
+    pub subnormal: ScalarMathSubnormal,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarMathFormat {
+    F16,
+    F32,
+    F64,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarMathOperation {
+    Sin,
+    Cos,
+    /// Routes through inline PTX: LLVM 22's tblgen models ex2 as the
+    /// overloaded `int_nvvm_ex2_approx{,_ftz}` records (anyfloat, no DAG
+    /// selection pattern), so the evidence contract cannot admit a typed
+    /// call. The legacy `llvm.nvvm.ex2.approx.f`/`.ftz.f` names still select
+    /// directly on both llc 21 and 22, so this is promotable to a typed
+    /// route once the import resolves the overloaded family.
+    Ex2,
+    Lg2,
+    Rcp,
+    Rsqrt,
+    Sqrt,
+    /// Routes through inline PTX: LLVM 22.1.2's tblgen export carries no
+    /// record for tanh at all (llc 22 selects `llvm.nvvm.tanh.approx.f32`
+    /// via NVVMIntrinsic-class matching, and llc 21 miscompiles it into an
+    /// extern funcall), so this is the family's only PTX-native source.
+    /// Hardware floor is sm_75 (PTX ISA 7.0); the family contract gates it
+    /// at the attested sm_80 evidence floor like every other variant.
+    Tanh,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarMathPrecision {
+    Approx,
+    Rn,
+    Rz,
+    Rm,
+    Rp,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarMathSubnormal {
+    Preserve,
+    Ftz,
+}
+
+/// Closed identity and carrier contract for extended floating-point min/max.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ExtendedMinMax {
+    pub format: ExtendedMinMaxFormat,
+    pub operation: ExtendedMinMaxOperation,
+    pub subnormal: ExtendedMinMaxSubnormal,
+    pub nan: ExtendedMinMaxNan,
+    pub xorsign_abs: bool,
+    pub adapter: ExtendedMinMaxAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ExtendedMinMaxFormat {
+    F32,
+    F16,
+    Bf16,
+    F16x2,
+    Bf16x2,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ExtendedMinMaxOperation {
+    Min,
+    Max,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ExtendedMinMaxSubnormal {
+    Preserve,
+    Ftz,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ExtendedMinMaxNan {
+    Number,
+    Nan,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ExtendedMinMaxAdapter {
+    DirectF32,
+    /// A single 16-bit float carried as its `u16` bit pattern, matching how
+    /// `packed_conversion` already carries `e4m3x2` and `e5m2x2` operands.
+    DirectHalfU16,
+    DirectPackedU32,
+}
+
+/// Closed contract for converting between scalar and packed values.
+///
+/// The source may be a scalar pair (`f32x2`, two operands) or an already-packed
+/// 16-bit or 32-bit register (`f16x2`, `e4m3x2`, `e5m2x2`, one operand), so the
+/// operand arity follows [`PackedConversionSourceFormat`] rather than being
+/// fixed at two.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct PackedConversion {
+    pub source_format: PackedConversionSourceFormat,
+    pub destination_format: PackedConversionDestinationFormat,
+    pub rounding: PackedConversionRounding,
+    pub saturation: PackedConversionSaturation,
+    pub adapter: PackedConversionAdapter,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedConversionSourceFormat {
+    E4m3x2,
+    E5m2x2,
+    F16x2,
+    F32x2,
+}
+
+impl PackedConversionSourceFormat {
+    /// Number of source operands the conversion takes.
+    ///
+    /// `f32x2` names two scalar `f32` operands; every packed source arrives in a
+    /// single register.
+    pub fn operand_count(self) -> usize {
+        match self {
+            Self::F32x2 => 2,
+            Self::E4m3x2 | Self::E5m2x2 | Self::F16x2 => 1,
+        }
+    }
+
+    /// PTX source-type token, used as the trailing `cvt` modifier.
+    pub fn ptx_token(self) -> &'static str {
+        match self {
+            Self::E4m3x2 => "e4m3x2",
+            Self::E5m2x2 => "e5m2x2",
+            Self::F16x2 => "f16x2",
+            Self::F32x2 => "f32",
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedConversionDestinationFormat {
+    Bf16x2,
+    E4m3x2,
+    E5m2x2,
+    F16x2,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedConversionRounding {
+    NearestEven,
+    TowardZero,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedConversionSaturation {
+    None,
+    Relu,
+    Satfinite,
+    SatfiniteRelu,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedConversionAdapter {
+    /// Forward the single packed source operand unchanged.
+    ///
+    /// PTX orders `cvt` operands as `d, a`, so a one-operand conversion needs no
+    /// reordering to keep the Rust argument order.
+    Identity,
+    /// Swap the two scalar operands.
+    ///
+    /// PTX writes the second source operand into the low half, so the operands
+    /// are reversed to keep the first Rust argument in the low half.
+    ReverseHighLowOperands,
+}
+
+/// Closed contract for one scalar floating-point conversion.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ScalarConversion {
+    pub source_format: ScalarConversionSourceFormat,
+    pub destination_format: ScalarConversionDestinationFormat,
+    pub rounding: ScalarConversionRounding,
+    pub saturation: ScalarConversionSaturation,
+    pub result_representation: ScalarConversionResultRepresentation,
+    pub adapter: ScalarConversionAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarConversionSourceFormat {
+    F32,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarConversionDestinationFormat {
+    Tf32,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarConversionRounding {
+    NearestAway,
+    NearestEven,
+    TowardZero,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarConversionSaturation {
+    None,
+    Relu,
+    Satfinite,
+    ReluSatfinite,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarConversionResultRepresentation {
+    RawU32Bits,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ScalarConversionAdapter {
+    DirectF32ToRawU32Bits,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn packed_alu_contract_rejects_unknown_format_operation_and_adapter() {
+        let valid = r#"
+format = "bf16x2"
+native_minimum_sm = 80
+operation = "fma"
+adapter = "direct_packed_u32"
+"#;
+        toml::from_str::<PackedAlu>(valid).unwrap();
+        for invalid in [
+            valid.replace("format = \"bf16x2\"", "format = \"bf16\""),
+            valid.replace("native_minimum_sm = 80\n", ""),
+            valid.replace("native_minimum_sm = 80", "native_minimum_sm = \"80\""),
+            valid.replace("operation = \"fma\"", "operation = \"mad\""),
+            valid.replace(
+                "adapter = \"direct_packed_u32\"",
+                "adapter = \"bitcast_any\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(toml::from_str::<PackedAlu>(&invalid).is_err(), "{invalid}");
+        }
+    }
+
+    #[test]
+    fn packed_conversion_contract_rejects_open_ended_policy() {
+        let valid = r#"
+source_format = "f32x2"
+destination_format = "bf16x2"
+rounding = "nearest_even"
+saturation = "none"
+adapter = "reverse_high_low_operands"
+"#;
+        toml::from_str::<PackedConversion>(valid).unwrap();
+        for invalid in [
+            valid.replace("source_format = \"f32x2\"", "source_format = \"f64x2\""),
+            valid.replace(
+                "destination_format = \"bf16x2\"",
+                "destination_format = \"f8x2\"",
+            ),
+            valid.replace("rounding = \"nearest_even\"", "rounding = \"zero\""),
+            valid.replace("saturation = \"none\"", "saturation = \"finite\""),
+            valid.replace(
+                "adapter = \"reverse_high_low_operands\"",
+                "adapter = \"direct\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(
+                toml::from_str::<PackedConversion>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/contracts/tcgen05.rs b/crates/cuda-intrinsics-gen/src/model/contracts/tcgen05.rs
new file mode 100644
index 0000000000..cbbba12ed2
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/contracts/tcgen05.rs
@@ -0,0 +1,398 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::super::catalog::CatalogTargetRequirement;
+use super::super::core::RuntimeValidation;
+use serde::{Deserialize, Serialize};
+
+/// Closed semantic contract for one tcgen05 operation.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05 {
+    pub operation: Tcgen05Operation,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub cp: Option<Tcgen05Cp>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub ld: Option<Tcgen05Ld>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub st: Option<Tcgen05St>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub mma: Option<Tcgen05Mma>,
+    pub adapter: Tcgen05Adapter,
+    pub source_contract: Tcgen05SourceContract,
+    pub runtime_validation: RuntimeValidation,
+}
+
+/// Closed identity and selector contract for one tcgen05 MMA API.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05Mma {
+    pub form: Tcgen05MmaForm,
+    pub selector_layout: Tcgen05MmaSelectorLayout,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub fixed_selectors: Option<Tcgen05MmaFixedSelectors>,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub alias: Option<Tcgen05MmaAlias>,
+    pub llvm_target: CatalogTargetRequirement,
+    pub libnvvm_target: CatalogTargetRequirement,
+}
+
+/// The 14 LLVM source forms covered by the first tcgen05 MMA batch.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum Tcgen05MmaForm {
+    Shared,
+    Tensor,
+    TensorAshift,
+    SpShared,
+    SpTensor,
+    SpTensorAshift,
+    WsShared,
+    WsSharedZeroColMask,
+    WsSpShared,
+    WsSpSharedZeroColMask,
+    WsSpTensor,
+    WsSpTensorZeroColMask,
+    WsTensor,
+    WsTensorZeroColMask,
+}
+
+/// Immediate arguments that select one imported tcgen05 MMA spelling.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(tag = "kind", rename_all = "snake_case")]
+pub enum Tcgen05MmaSelectorLayout {
+    Base {
+        kind_argument: u8,
+        cta_group_argument: u8,
+        collector_a_argument: u8,
+        collector_a_upper_exclusive: u8,
+    },
+    WarpSpecialized {
+        kind_argument: u8,
+        b_buffer_argument: u8,
+        b_usage_argument: u8,
+    },
+}
+
+/// A fixed warp-specialized selector tuple used by compatibility aliases.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05MmaFixedSelectors {
+    pub kind: Tcgen05MmaKind,
+    pub b_buffer: u8,
+    pub b_usage: Tcgen05MmaBUsage,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum Tcgen05MmaKind {
+    F16,
+    Tf32,
+    F8f6f4,
+    I8,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum Tcgen05MmaBUsage {
+    Discard,
+    LastUse,
+    Fill,
+    Use,
+}
+
+impl Tcgen05MmaBUsage {
+    pub const fn selector_value(self) -> u8 {
+        match self {
+            Self::Discard => 0,
+            Self::LastUse => 1,
+            Self::Fill => 2,
+            Self::Use => 3,
+        }
+    }
+}
+
+/// Public names proposed by PR #346 for the generic f8f6f4 carrier.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum Tcgen05MmaAlias {
+    E4m3,
+    E5m2,
+    E2m3,
+    E3m2,
+    E2m1,
+}
+
+/// Closed identity for one tcgen05 shared-to-tensor-memory copy.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05Cp {
+    pub member: Tcgen05CpMember,
+    pub group: Tcgen05CpGroup,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+pub enum Tcgen05CpMember {
+    #[serde(rename = "128x128b_b4x16_p64")]
+    M128x128bB4x16P64,
+    #[serde(rename = "128x128b_b6x16_p32")]
+    M128x128bB6x16P32,
+    #[serde(rename = "128x128b")]
+    M128x128b,
+    #[serde(rename = "128x256b_b4x16_p64")]
+    M128x256bB4x16P64,
+    #[serde(rename = "128x256b_b6x16_p32")]
+    M128x256bB6x16P32,
+    #[serde(rename = "32x128b_warpx4_b4x16_p64")]
+    M32x128bWarpx4B4x16P64,
+    #[serde(rename = "32x128b_warpx4_b6x16_p32")]
+    M32x128bWarpx4B6x16P32,
+    #[serde(rename = "32x128b_warpx4")]
+    M32x128bWarpx4,
+    #[serde(rename = "4x256b_b4x16_p64")]
+    M4x256bB4x16P64,
+    #[serde(rename = "4x256b_b6x16_p32")]
+    M4x256bB6x16P32,
+    #[serde(rename = "4x256b")]
+    M4x256b,
+    #[serde(rename = "64x128b_warpx2_01_23_b4x16_p64")]
+    M64x128bWarpx2Pair0123B4x16P64,
+    #[serde(rename = "64x128b_warpx2_01_23_b6x16_p32")]
+    M64x128bWarpx2Pair0123B6x16P32,
+    #[serde(rename = "64x128b_warpx2_01_23")]
+    M64x128bWarpx2Pair0123,
+    #[serde(rename = "64x128b_warpx2_02_13_b4x16_p64")]
+    M64x128bWarpx2Pair0213B4x16P64,
+    #[serde(rename = "64x128b_warpx2_02_13_b6x16_p32")]
+    M64x128bWarpx2Pair0213B6x16P32,
+    #[serde(rename = "64x128b_warpx2_02_13")]
+    M64x128bWarpx2Pair0213,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum Tcgen05CpGroup {
+    Cg1,
+    Cg2,
+}
+
+/// Closed identity for one tcgen05 tensor-memory load.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05Ld {
+    pub shape: Tcgen05LdShape,
+    pub multiplicity: Tcgen05LdMultiplicity,
+    pub pack16: bool,
+}
+
+/// Closed identity for one tcgen05 tensor-memory store.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05St {
+    pub shape: Tcgen05LdShape,
+    pub multiplicity: Tcgen05LdMultiplicity,
+    pub unpack16: bool,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+pub enum Tcgen05LdShape {
+    #[serde(rename = "16x32bx2")]
+    M16x32bx2,
+    #[serde(rename = "16x64b")]
+    M16x64b,
+    #[serde(rename = "16x128b")]
+    M16x128b,
+    #[serde(rename = "16x256b")]
+    M16x256b,
+    #[serde(rename = "32x32b")]
+    M32x32b,
+}
+
+impl Tcgen05LdShape {
+    pub const fn register_multiplier(self) -> usize {
+        match self {
+            Self::M16x32bx2 | Self::M16x64b | Self::M32x32b => 1,
+            Self::M16x128b => 2,
+            Self::M16x256b => 4,
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum Tcgen05LdMultiplicity {
+    X1,
+    X2,
+    X4,
+    X8,
+    X16,
+    X32,
+    X64,
+    X128,
+}
+
+impl Tcgen05LdMultiplicity {
+    pub const fn count(self) -> usize {
+        match self {
+            Self::X1 => 1,
+            Self::X2 => 2,
+            Self::X4 => 4,
+            Self::X8 => 8,
+            Self::X16 => 16,
+            Self::X32 => 32,
+            Self::X64 => 64,
+            Self::X128 => 128,
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum Tcgen05Operation {
+    Alloc,
+    Dealloc,
+    RelinquishAllocPermit,
+    FenceBeforeThreadSync,
+    FenceAfterThreadSync,
+    Commit,
+    CommitSharedCluster,
+    MmaWsF16,
+    MmaF16,
+    MmaWsBf16,
+    MmaWsTf32,
+    CpSmemToTmem,
+    Ld16x256bX8Pure,
+    Ld16x256bPure,
+    LoadWait,
+    StoreWait,
+    AllocCg2,
+    DeallocCg2,
+    RelinquishAllocPermitCg2,
+    MmaF16Cg2,
+    CommitCg2,
+    CommitSharedClusterCg2,
+    CommitMulticastCg2,
+    CpSmemToTmemCg2,
+    Ld,
+    St,
+    CommitMulticast,
+    ShiftDown,
+    ShiftDownCg2,
+    Mma,
+}
+
+impl Tcgen05Operation {
+    pub const fn execution_scope(self) -> &'static str {
+        match self {
+            Self::Alloc
+            | Self::Dealloc
+            | Self::RelinquishAllocPermit
+            | Self::Ld16x256bX8Pure
+            | Self::Ld16x256bPure
+            | Self::LoadWait
+            | Self::StoreWait
+            | Self::AllocCg2
+            | Self::DeallocCg2
+            | Self::RelinquishAllocPermitCg2
+            | Self::Ld
+            | Self::St => "warp",
+            Self::FenceBeforeThreadSync
+            | Self::FenceAfterThreadSync
+            | Self::Commit
+            | Self::CommitSharedCluster
+            | Self::MmaWsF16
+            | Self::MmaF16
+            | Self::MmaWsBf16
+            | Self::MmaWsTf32
+            | Self::CpSmemToTmem
+            | Self::MmaF16Cg2
+            | Self::CommitCg2
+            | Self::CommitSharedClusterCg2
+            | Self::CommitMulticastCg2
+            | Self::CpSmemToTmemCg2
+            | Self::CommitMulticast
+            | Self::ShiftDown
+            | Self::ShiftDownCg2
+            | Self::Mma => "thread",
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum Tcgen05Adapter {
+    SharedPointerColumnsToVoid,
+    TmemAddressColumnsToVoid,
+    NoOperands,
+    BarrierPointerToVoid,
+    MmaWsDropLegacyADescriptor,
+    MmaInjectZeroDisableLanes,
+    TmemDescriptorToVoid,
+    TmemToF32x32,
+    TmemToF32x4,
+    BarrierPointerMaskToVoid,
+    TmemInjectPack16ToU32Registers,
+    TmemU32RegistersInjectUnpack16ToVoid,
+    TmemHalfSplitOffsetInjectPack16ToU32Registers,
+    TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid,
+    TmemAddressToVoid,
+    MmaDirectSelectors,
+    MmaWsFixedSelectorsDropLegacyADescriptor,
+}
+
+/// Relationship between the public operation and LLVM's NVPTX selection.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum Tcgen05SourceContract {
+    ExactTablegenSelection,
+    TablegenSelectionChangesPtx,
+    LlvmCustomLoweringWithoutSelection,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn tcgen05_execution_scope_is_closed() {
+        for operation in [
+            Tcgen05Operation::Alloc,
+            Tcgen05Operation::Dealloc,
+            Tcgen05Operation::RelinquishAllocPermit,
+            Tcgen05Operation::AllocCg2,
+            Tcgen05Operation::DeallocCg2,
+            Tcgen05Operation::RelinquishAllocPermitCg2,
+            Tcgen05Operation::Ld16x256bX8Pure,
+            Tcgen05Operation::Ld16x256bPure,
+            Tcgen05Operation::LoadWait,
+            Tcgen05Operation::StoreWait,
+            Tcgen05Operation::Ld,
+            Tcgen05Operation::St,
+        ] {
+            assert_eq!(operation.execution_scope(), "warp");
+        }
+        for operation in [
+            Tcgen05Operation::FenceBeforeThreadSync,
+            Tcgen05Operation::FenceAfterThreadSync,
+            Tcgen05Operation::Commit,
+            Tcgen05Operation::CommitSharedCluster,
+            Tcgen05Operation::MmaWsF16,
+            Tcgen05Operation::MmaWsBf16,
+            Tcgen05Operation::MmaWsTf32,
+            Tcgen05Operation::MmaF16,
+            Tcgen05Operation::CpSmemToTmem,
+            Tcgen05Operation::MmaF16Cg2,
+            Tcgen05Operation::CommitCg2,
+            Tcgen05Operation::CommitSharedClusterCg2,
+            Tcgen05Operation::CommitMulticastCg2,
+            Tcgen05Operation::CpSmemToTmemCg2,
+            Tcgen05Operation::CommitMulticast,
+            Tcgen05Operation::ShiftDown,
+            Tcgen05Operation::ShiftDownCg2,
+        ] {
+            assert_eq!(operation.execution_scope(), "thread");
+        }
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/contracts/tma.rs b/crates/cuda-intrinsics-gen/src/model/contracts/tma.rs
new file mode 100644
index 0000000000..d4690333ec
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/contracts/tma.rs
@@ -0,0 +1,243 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::super::core::RuntimeValidation;
+use serde::{Deserialize, Serialize};
+
+/// Closed semantic contract for a TMA operation.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tma {
+    pub operation: TmaOperation,
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub reduction: Option<TmaReduction>,
+    pub adapter: TmaAdapter,
+    pub runtime_validation: RuntimeValidation,
+}
+
+impl Tma {
+    pub const fn dimensions(&self) -> Option<usize> {
+        match &self.reduction {
+            Some(reduction) => Some(reduction.dimensions as usize),
+            None => self.operation.dimensions(),
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum TmaOperation {
+    G2sTile1d,
+    G2sTile2d,
+    G2sTile2dMulticast,
+    G2sTile2dMulticastCg2,
+    G2sTile3d,
+    G2sTile4d,
+    G2sTile5d,
+    S2gTile1d,
+    S2gTile2d,
+    S2gTile3d,
+    S2gTile4d,
+    S2gTile5d,
+    Reduce,
+    CommitGroup,
+    WaitGroup,
+    WaitGroupRead,
+    PrefetchTensorMap,
+    PrefetchTile1d,
+    PrefetchTile2d,
+    PrefetchTile3d,
+    PrefetchTile4d,
+    PrefetchTile5d,
+    #[serde(rename = "prefetch_tile_gather4_2d")]
+    PrefetchTileGather4TwoDimensional,
+    PrefetchTile1dCacheHint,
+    PrefetchTile2dCacheHint,
+    PrefetchTile3dCacheHint,
+    PrefetchTile4dCacheHint,
+    PrefetchTile5dCacheHint,
+    #[serde(rename = "prefetch_tile_gather4_2d_cache_hint")]
+    PrefetchTileGather4TwoDimensionalCacheHint,
+    ReplaceBoxDim,
+    ReplaceElementStride,
+    ReplaceElementType,
+    ReplaceFillMode,
+    ReplaceGlobalAddress,
+    ReplaceGlobalDim,
+    ReplaceGlobalStride,
+    ReplaceInterleaveLayout,
+    ReplaceRank,
+    ReplaceSwizzleAtomicity,
+    ReplaceSwizzleMode,
+    FenceProxyTensorMapAcquireCluster,
+    FenceProxyTensorMapAcquireCta,
+    FenceProxyTensorMapAcquireGpu,
+    FenceProxyTensorMapAcquireSystem,
+    FenceProxyTensorMapReleaseCluster,
+    FenceProxyTensorMapReleaseCta,
+    FenceProxyTensorMapReleaseGpu,
+    FenceProxyTensorMapReleaseSystem,
+}
+
+impl TmaOperation {
+    pub const fn dimensions(self) -> Option<usize> {
+        match self {
+            Self::G2sTile1d | Self::S2gTile1d => Some(1),
+            Self::G2sTile2d
+            | Self::G2sTile2dMulticast
+            | Self::G2sTile2dMulticastCg2
+            | Self::S2gTile2d => Some(2),
+            Self::G2sTile3d | Self::S2gTile3d => Some(3),
+            Self::G2sTile4d | Self::S2gTile4d => Some(4),
+            Self::G2sTile5d | Self::S2gTile5d => Some(5),
+            Self::Reduce
+            | Self::CommitGroup
+            | Self::WaitGroup
+            | Self::WaitGroupRead
+            | Self::PrefetchTensorMap
+            | Self::PrefetchTile1d
+            | Self::PrefetchTile2d
+            | Self::PrefetchTile3d
+            | Self::PrefetchTile4d
+            | Self::PrefetchTile5d
+            | Self::PrefetchTileGather4TwoDimensional
+            | Self::PrefetchTile1dCacheHint
+            | Self::PrefetchTile2dCacheHint
+            | Self::PrefetchTile3dCacheHint
+            | Self::PrefetchTile4dCacheHint
+            | Self::PrefetchTile5dCacheHint
+            | Self::PrefetchTileGather4TwoDimensionalCacheHint
+            | Self::ReplaceBoxDim
+            | Self::ReplaceElementStride
+            | Self::ReplaceElementType
+            | Self::ReplaceFillMode
+            | Self::ReplaceGlobalAddress
+            | Self::ReplaceGlobalDim
+            | Self::ReplaceGlobalStride
+            | Self::ReplaceInterleaveLayout
+            | Self::ReplaceRank
+            | Self::ReplaceSwizzleAtomicity
+            | Self::ReplaceSwizzleMode
+            | Self::FenceProxyTensorMapAcquireCluster
+            | Self::FenceProxyTensorMapAcquireCta
+            | Self::FenceProxyTensorMapAcquireGpu
+            | Self::FenceProxyTensorMapAcquireSystem
+            | Self::FenceProxyTensorMapReleaseCluster
+            | Self::FenceProxyTensorMapReleaseCta
+            | Self::FenceProxyTensorMapReleaseGpu
+            | Self::FenceProxyTensorMapReleaseSystem => None,
+        }
+    }
+
+    pub const fn prefetch_coordinate_count(self) -> Option<usize> {
+        match self {
+            Self::PrefetchTile1d | Self::PrefetchTile1dCacheHint => Some(1),
+            Self::PrefetchTile2d | Self::PrefetchTile2dCacheHint => Some(2),
+            Self::PrefetchTile3d | Self::PrefetchTile3dCacheHint => Some(3),
+            Self::PrefetchTile4d | Self::PrefetchTile4dCacheHint => Some(4),
+            Self::PrefetchTile5d
+            | Self::PrefetchTile5dCacheHint
+            | Self::PrefetchTileGather4TwoDimensional
+            | Self::PrefetchTileGather4TwoDimensionalCacheHint => Some(5),
+            _ => None,
+        }
+    }
+
+    pub const fn uses_prefetch_cache_hint(self) -> bool {
+        matches!(
+            self,
+            Self::PrefetchTile1dCacheHint
+                | Self::PrefetchTile2dCacheHint
+                | Self::PrefetchTile3dCacheHint
+                | Self::PrefetchTile4dCacheHint
+                | Self::PrefetchTile5dCacheHint
+                | Self::PrefetchTileGather4TwoDimensionalCacheHint
+        )
+    }
+}
+
+/// Closed identity for one TMA tensor-reduction operation.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct TmaReduction {
+    pub operation: TmaReductionOperation,
+    pub load_mode: TmaReductionLoadMode,
+    pub dimensions: u8,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum TmaReductionOperation {
+    Add,
+    And,
+    Dec,
+    Inc,
+    Max,
+    Min,
+    Or,
+    Xor,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum TmaReductionLoadMode {
+    Tile,
+    Im2col,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum TmaAdapter {
+    G2sPointersCoordinatesBarrierInjectDefaults,
+    G2sPointersCoordinatesBarrierMaskInjectDefaults,
+    S2gPointersCoordinatesInjectDefaults,
+    ReductionPointersCoordinatesInjectDefaults,
+    NoOperands,
+    CompileTimeConstantMaxPending,
+    DescriptorPointer,
+    DescriptorCoordinatesInjectDefaults,
+    DescriptorCoordinatesCacheHintInjectFlag,
+    DescriptorAndAddressPointers,
+    DescriptorOrdinalAndU32,
+    DescriptorOrdinalAndU64,
+    DescriptorAndImmediateU32,
+    DescriptorAndRuntimeU32,
+    DescriptorPointerInjectBytes,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn tma_contract_rejects_open_ended_policy() {
+        let valid = r#"
+operation = "g2s_tile2d_multicast"
+adapter = "g2s_pointers_coordinates_barrier_mask_inject_defaults"
+runtime_validation = "unexecuted"
+"#;
+        let parsed = toml::from_str::<Tma>(valid).unwrap();
+        assert_eq!(parsed.operation, TmaOperation::G2sTile2dMulticast);
+        assert_eq!(
+            parsed.adapter,
+            TmaAdapter::G2sPointersCoordinatesBarrierMaskInjectDefaults
+        );
+
+        for invalid in [
+            valid.replace("g2s_tile2d_multicast", "g2s_multicast"),
+            valid.replace(
+                "g2s_pointers_coordinates_barrier_mask_inject_defaults",
+                "direct",
+            ),
+            valid.replace(
+                "runtime_validation = \"unexecuted\"",
+                "runtime_validation = \"assumed\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(toml::from_str::<Tma>(&invalid).is_err(), "{invalid}");
+        }
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/contracts/warp.rs b/crates/cuda-intrinsics-gen/src/model/contracts/warp.rs
new file mode 100644
index 0000000000..c94c87e1d8
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/contracts/warp.rs
@@ -0,0 +1,503 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use serde::{Deserialize, Serialize};
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ClusterBarrierMode {
+    Arrive,
+    ArriveAligned,
+    ArriveRelaxed,
+    ArriveRelaxedAligned,
+    Wait,
+    WaitAligned,
+}
+
+/// Closed semantics for one cluster-barrier spelling.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ClusterBarrier {
+    pub mode: ClusterBarrierMode,
+    pub ordering: ClusterBarrierOrdering,
+    pub aligned: bool,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ClusterBarrierOrdering {
+    Release,
+    Relaxed,
+    Acquire,
+}
+
+/// Closed semantic and lowering contract for the generated `redux.sync`
+/// family.
+///
+/// The Rust and NVVM dialect APIs intentionally put the participation mask
+/// first, while LLVM's NVVM intrinsic puts the lane value first. Keeping that
+/// adapter typed prevents a generic direct-call renderer from silently
+/// swapping the collective's source and member mask.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Redux {
+    pub operation: ReduxOperation,
+    pub participation: ReduxParticipation,
+    pub adapter: ReduxAdapter,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ReduxOperation {
+    Add,
+    Umin,
+    Min,
+    Umax,
+    Max,
+    And,
+    Or,
+    Xor,
+    Fmin,
+    FminNan,
+    FminAbs,
+    FminAbsNan,
+    Fmax,
+    FmaxNan,
+    FmaxAbs,
+    FmaxAbsNan,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ReduxParticipation {
+    ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ReduxAdapter {
+    MaskValueToSourceMemberMask,
+}
+
+/// Closed semantic and lowering contract for the generated `vote.sync`
+/// family.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Vote {
+    pub mode: VoteMode,
+    pub participation: VoteParticipation,
+    pub legacy_pre_sm70: PreSm70MemberMaskRule,
+    pub adapter: VoteAdapter,
+    pub mask_encoding: MaskEncoding,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum VoteMode {
+    All,
+    Any,
+    Ballot,
+    Uni,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum VoteParticipation {
+    ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum VoteAdapter {
+    DirectMaskPredicate,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum MaskEncoding {
+    RegisterOrImmediate,
+}
+
+/// Closed semantic and lowering contract for `activemask`.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ActiveMask {
+    pub observation: ActiveMaskObservation,
+    pub adapter: ActiveMaskAdapter,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ActiveMaskObservation {
+    ExecutingLanesAtInstruction,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ActiveMaskAdapter {
+    DirectZeroOperandMask,
+}
+
+/// Closed semantic and lowering contract for `match.sync`.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct WarpMatch {
+    pub mode: WarpMatchMode,
+    pub value_width: WarpMatchValueWidth,
+    pub participation: WarpMatchParticipation,
+    pub adapter: WarpMatchAdapter,
+    pub value_encoding: MatchOperandEncoding,
+    pub mask_encoding: MatchOperandEncoding,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpMatchMode {
+    Any,
+    All,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpMatchValueWidth {
+    B32,
+    B64,
+}
+
+impl WarpMatchValueWidth {
+    pub const fn bits(self) -> u32 {
+        match self {
+            Self::B32 => 32,
+            Self::B64 => 64,
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpMatchParticipation {
+    ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpMatchAdapter {
+    DirectMask,
+    ProjectMaskDiscardPredicate,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum MatchOperandEncoding {
+    RegisterOrImmediate,
+}
+
+/// Closed semantic and lowering contract for `bar.warp.sync`.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct WarpBarrier {
+    pub participation: WarpBarrierParticipation,
+    pub legacy_pre_sm70: PreSm70MemberMaskRule,
+    pub adapter: WarpBarrierAdapter,
+    pub mask_encoding: WarpBarrierMaskEncoding,
+    pub memory_ordering: WarpBarrierMemoryOrdering,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpBarrierParticipation {
+    ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PreSm70MemberMaskRule {
+    AllNamedLanesConvergedAndOnlyNamedLanesActive,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpBarrierAdapter {
+    DirectMemberMask,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpBarrierMaskEncoding {
+    RegisterOrImmediate,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpBarrierMemoryOrdering {
+    ParticipatingLanes,
+}
+
+/// Closed semantic and lowering contract for `shfl.sync`.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct WarpShuffle {
+    pub mode: WarpShuffleMode,
+    pub value_kind: WarpShuffleValueKind,
+    pub participation: WarpShuffleParticipation,
+    pub legacy_pre_sm70: PreSm70MemberMaskRule,
+    pub source_lane: WarpShuffleSourceLane,
+    pub adapter: WarpShuffleAdapter,
+    pub clamp: u32,
+    pub lane_encoding: WarpShuffleOperandEncoding,
+    pub mask_encoding: WarpShuffleOperandEncoding,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpShuffleMode {
+    Idx,
+    Bfly,
+    Down,
+    Up,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpShuffleValueKind {
+    I32,
+    F32,
+    I64,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpShuffleParticipation {
+    ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpShuffleSourceLane {
+    InRangeSourceActiveAndNamedOutOfRangeCopiesSelf,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpShuffleAdapter {
+    MaskValueLaneOrDeltaInsertClamp,
+    /// Split i64 into low/high b32 halves, shuffle both in one convergent
+    /// side-effecting block, then reassemble the original bit layout.
+    MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum WarpShuffleOperandEncoding {
+    RegisterOrImmediate,
+    RegisterOnly,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn redux_contract_rejects_unknown_operand_adapter() {
+        let input = r#"
+operation = "add"
+participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
+adapter = "mask_value_direct"
+"#;
+        let error = toml::from_str::<Redux>(input).unwrap_err();
+        assert!(error.to_string().contains("mask_value_direct"));
+    }
+
+    #[test]
+    fn vote_contract_rejects_unknown_modes_and_mask_encodings() {
+        let valid = r#"
+mode = "all"
+participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
+legacy_pre_sm70 = "all_named_lanes_converged_and_only_named_lanes_active"
+adapter = "direct_mask_predicate"
+mask_encoding = "register_or_immediate"
+"#;
+        toml::from_str::<Vote>(valid).unwrap();
+
+        for invalid in [
+            valid.replace("mode = \"all\"", "mode = \"match\""),
+            valid.replace(
+                "mask_encoding = \"register_or_immediate\"",
+                "mask_encoding = \"any_operand\"",
+            ),
+            valid.replace(
+                "legacy_pre_sm70 = \"all_named_lanes_converged_and_only_named_lanes_active\"",
+                "legacy_pre_sm70 = \"independent_threads\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(toml::from_str::<Vote>(&invalid).is_err(), "{invalid}");
+        }
+    }
+
+    #[test]
+    fn warp_shuffle_contract_rejects_open_ended_policy() {
+        let valid = r#"
+mode = "idx"
+value_kind = "i32"
+participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
+legacy_pre_sm70 = "all_named_lanes_converged_and_only_named_lanes_active"
+source_lane = "in_range_source_active_and_named_out_of_range_copies_self"
+adapter = "mask_value_lane_or_delta_insert_clamp"
+clamp = 31
+lane_encoding = "register_or_immediate"
+mask_encoding = "register_or_immediate"
+"#;
+        toml::from_str::<WarpShuffle>(valid).unwrap();
+
+        for invalid in [
+            valid.replace("mode = \"idx\"", "mode = \"rotate\""),
+            valid.replace("value_kind = \"i32\"", "value_kind = \"b32\""),
+            valid.replace(
+                "source_lane = \"in_range_source_active_and_named_out_of_range_copies_self\"",
+                "source_lane = \"unchecked\"",
+            ),
+            valid.replace(
+                "lane_encoding = \"register_or_immediate\"",
+                "lane_encoding = \"anything\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(
+                toml::from_str::<WarpShuffle>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+
+        let i64 = r#"
+mode = "down"
+value_kind = "i64"
+participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
+legacy_pre_sm70 = "all_named_lanes_converged_and_only_named_lanes_active"
+source_lane = "in_range_source_active_and_named_out_of_range_copies_self"
+adapter = "mask_value_lane_or_delta_split_i64_low_high_b32_insert_clamp_reassemble"
+clamp = 31
+lane_encoding = "register_only"
+mask_encoding = "register_only"
+"#;
+        let parsed = toml::from_str::<WarpShuffle>(i64).unwrap();
+        assert_eq!(parsed.value_kind, WarpShuffleValueKind::I64);
+        assert_eq!(
+            parsed.adapter,
+            WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
+        );
+        assert_eq!(
+            parsed.lane_encoding,
+            WarpShuffleOperandEncoding::RegisterOnly
+        );
+
+        for invalid in [
+            i64.replace("value_kind = \"i64\"", "value_kind = \"u64\""),
+            i64.replace(
+                "adapter = \"mask_value_lane_or_delta_split_i64_low_high_b32_insert_clamp_reassemble\"",
+                "adapter = \"split_any_width\"",
+            ),
+            i64.replace(
+                "mask_encoding = \"register_only\"",
+                "mask_encoding = \"any_operand\"",
+            ),
+        ] {
+            assert!(
+                toml::from_str::<WarpShuffle>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+    }
+
+    #[test]
+    fn warp_match_contract_rejects_open_ended_adapters_and_encodings() {
+        let valid = r#"
+mode = "all"
+value_width = "b64"
+participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
+adapter = "project_mask_discard_predicate"
+value_encoding = "register_or_immediate"
+mask_encoding = "register_or_immediate"
+"#;
+        toml::from_str::<WarpMatch>(valid).unwrap();
+
+        for invalid in [
+            valid.replace("mode = \"all\"", "mode = \"equal\""),
+            valid.replace(
+                "adapter = \"project_mask_discard_predicate\"",
+                "adapter = \"first_result\"",
+            ),
+            valid.replace(
+                "value_encoding = \"register_or_immediate\"",
+                "value_encoding = \"anything\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(toml::from_str::<WarpMatch>(&invalid).is_err(), "{invalid}");
+        }
+    }
+
+    #[test]
+    fn warp_barrier_contract_rejects_open_ended_policy() {
+        let valid = r#"
+participation = "executing_lane_named_all_named_lanes_same_instruction_and_mask"
+legacy_pre_sm70 = "all_named_lanes_converged_and_only_named_lanes_active"
+adapter = "direct_member_mask"
+mask_encoding = "register_or_immediate"
+memory_ordering = "participating_lanes"
+"#;
+        toml::from_str::<WarpBarrier>(valid).unwrap();
+
+        for invalid in [
+            valid.replace("adapter = \"direct_member_mask\"", "adapter = \"direct\""),
+            valid.replace(
+                "legacy_pre_sm70 = \"all_named_lanes_converged_and_only_named_lanes_active\"",
+                "legacy_pre_sm70 = \"independent_threads\"",
+            ),
+            valid.replace(
+                "mask_encoding = \"register_or_immediate\"",
+                "mask_encoding = \"any_operand\"",
+            ),
+            valid.replace(
+                "memory_ordering = \"participating_lanes\"",
+                "memory_ordering = \"none\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(
+                toml::from_str::<WarpBarrier>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+    }
+
+    #[test]
+    fn cluster_barrier_contract_rejects_open_ended_semantics() {
+        let valid = r#"
+mode = "arrive_relaxed_aligned"
+ordering = "relaxed"
+aligned = true
+"#;
+        let parsed = toml::from_str::<ClusterBarrier>(valid).unwrap();
+        assert_eq!(parsed.mode, ClusterBarrierMode::ArriveRelaxedAligned);
+        assert_eq!(parsed.ordering, ClusterBarrierOrdering::Relaxed);
+        assert!(parsed.aligned);
+
+        for invalid in [
+            valid.replace("ordering = \"relaxed\"", "ordering = \"unordered\""),
+            valid.replace("aligned = true", "aligned = \"sometimes\""),
+            valid.replace(
+                "mode = \"arrive_relaxed_aligned\"",
+                "mode = \"arrive_release_aligned\"",
+            ),
+            format!("{valid}unreviewed = true\n"),
+        ] {
+            assert!(
+                toml::from_str::<ClusterBarrier>(&invalid).is_err(),
+                "{invalid}"
+            );
+        }
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/core.rs b/crates/cuda-intrinsics-gen/src/model/core.rs
new file mode 100644
index 0000000000..f594dc884c
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/core.rs
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use serde::{Deserialize, Serialize};
+
+/// Provenance for a generated intrinsic. PTX-native operations deliberately
+/// have no invented LLVM TableGen record or LLVM intrinsic symbol.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(tag = "kind", rename_all = "snake_case", deny_unknown_fields)]
+pub enum IntrinsicSource {
+    LlvmImported { source_record: String },
+    PtxNative { instruction: String },
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum IntrinsicBackend {
+    LlvmNvptx,
+    LibNvvm,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum BackendLoweringMechanism {
+    TypedNvvm,
+    InlinePtx,
+}
+
+/// Closed identity for the small execution-control families that share a
+/// result-less MIR/dialect representation.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+pub enum ExecutionControlOperation {
+    BarrierCtaSync,
+    BarrierCtaSyncAligned,
+    BarrierCtaArrive,
+    BarrierCtaArriveAligned,
+    GridDependencyLaunchDependents,
+    GridDependencyWait,
+    SetMaxNRegInc,
+    SetMaxNRegDec,
+}
+
+impl ExecutionControlOperation {
+    pub fn from_catalog_id(id: &str) -> Option<Self> {
+        Some(match id {
+            "barrier_cta_sync" => Self::BarrierCtaSync,
+            "barrier_cta_sync_aligned" => Self::BarrierCtaSyncAligned,
+            "barrier_cta_arrive" => Self::BarrierCtaArrive,
+            "barrier_cta_arrive_aligned" => Self::BarrierCtaArriveAligned,
+            "grid_dependency_launch_dependents" => Self::GridDependencyLaunchDependents,
+            "grid_dependency_wait" => Self::GridDependencyWait,
+            "setmaxnreg_inc" => Self::SetMaxNRegInc,
+            "setmaxnreg_dec" => Self::SetMaxNRegDec,
+            _ => return None,
+        })
+    }
+
+    pub const fn family(self) -> &'static str {
+        match self {
+            Self::BarrierCtaSync
+            | Self::BarrierCtaSyncAligned
+            | Self::BarrierCtaArrive
+            | Self::BarrierCtaArriveAligned => "counted_barrier",
+            Self::GridDependencyLaunchDependents | Self::GridDependencyWait => "grid_dependency",
+            Self::SetMaxNRegInc | Self::SetMaxNRegDec => "register_control",
+        }
+    }
+
+    pub const fn operand_count(self) -> usize {
+        match self {
+            Self::BarrierCtaSync
+            | Self::BarrierCtaSyncAligned
+            | Self::BarrierCtaArrive
+            | Self::BarrierCtaArriveAligned => 2,
+            Self::GridDependencyLaunchDependents | Self::GridDependencyWait => 0,
+            Self::SetMaxNRegInc | Self::SetMaxNRegDec => 1,
+        }
+    }
+
+    pub const fn requires_immediate_operands(self) -> bool {
+        matches!(self, Self::SetMaxNRegInc | Self::SetMaxNRegDec)
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum RuntimeValidation {
+    Unexecuted,
+    Executed,
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/evidence.rs b/crates/cuda-intrinsics-gen/src/model/evidence.rs
new file mode 100644
index 0000000000..2800f68c28
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/evidence.rs
@@ -0,0 +1,208 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::core::{BackendLoweringMechanism, IntrinsicBackend, IntrinsicSource, RuntimeValidation};
+use crate::ptx::InstructionPattern;
+use serde::{Deserialize, Serialize};
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct EvidenceFile {
+    pub schema: u32,
+    pub backend_profile: String,
+    #[serde(default)]
+    pub backend_kind: Option<IntrinsicBackend>,
+    pub llvm_revision: String,
+    pub backend_version: String,
+    pub backend_sha256: String,
+    #[serde(default)]
+    pub artifact_path: Option<String>,
+    #[serde(default)]
+    pub build_id_prefix: Option<String>,
+    #[serde(default)]
+    pub nvvm_ir_version: Option<String>,
+    #[serde(default)]
+    pub debug_ir_version: Option<String>,
+    pub records: Vec<EvidenceRecord>,
+}
+
+/// Schema-6 evidence before matrix expansion.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct EvidenceFileV6 {
+    pub schema: u32,
+    pub backend_profile: String,
+    #[serde(default)]
+    pub backend_kind: Option<IntrinsicBackend>,
+    pub llvm_revision: String,
+    pub backend_version: String,
+    pub backend_sha256: String,
+    #[serde(default)]
+    pub artifact_path: Option<String>,
+    #[serde(default)]
+    pub build_id_prefix: Option<String>,
+    #[serde(default)]
+    pub nvvm_ir_version: Option<String>,
+    #[serde(default)]
+    pub debug_ir_version: Option<String>,
+    #[serde(default)]
+    pub defaults: EvidenceRecordDefaults,
+    #[serde(default)]
+    pub fixtures: Vec<EvidenceFixture>,
+    #[serde(default)]
+    pub matrices: Vec<EvidenceMatrix>,
+    #[serde(default)]
+    pub records: Vec<EvidenceRecord>,
+}
+
+/// Facts shared by every record in one evidence matrix.
+#[derive(Debug, Clone, Default, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct EvidenceRecordDefaults {
+    #[serde(default)]
+    pub resolved_llvm_symbol: Option<String>,
+    #[serde(default)]
+    pub llvm_arguments: Option<Vec<String>>,
+    #[serde(default)]
+    pub llvm_results: Option<Vec<String>>,
+    #[serde(default)]
+    pub concrete_llvm_arguments: Option<Vec<String>>,
+    #[serde(default)]
+    pub concrete_llvm_results: Option<Vec<String>>,
+    #[serde(default)]
+    pub target_triple: Option<String>,
+    #[serde(default)]
+    pub gpu_target: Option<String>,
+    #[serde(default)]
+    pub ptx_feature: Option<String>,
+    #[serde(default)]
+    pub status: Option<String>,
+    #[serde(default)]
+    pub stages: Vec<EvidenceStage>,
+    #[serde(default)]
+    pub declaration_attributes_canonicalized: Option<bool>,
+    #[serde(default)]
+    pub runtime_validation: Option<RuntimeValidation>,
+}
+
+/// One shared fixture and the number of records it covers.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct EvidenceFixture {
+    pub id: String,
+    pub coverage_count: usize,
+    pub stages: Vec<EvidenceStage>,
+}
+
+/// One Cartesian evidence matrix.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct EvidenceMatrix {
+    pub axes: Vec<EvidenceMatrixAxis>,
+    pub product_count: usize,
+    #[serde(default)]
+    pub fixtures: Vec<String>,
+    pub template: EvidenceMatrixTemplate,
+}
+
+/// One named matrix axis.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct EvidenceMatrixAxis {
+    pub name: String,
+    pub values: Vec<String>,
+}
+
+/// Identity and matrix-specific facts for one record template.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct EvidenceMatrixTemplate {
+    pub id: String,
+    #[serde(default)]
+    pub source: Option<IntrinsicSource>,
+    #[serde(default)]
+    pub source_record: Option<String>,
+    #[serde(deserialize_with = "deserialize_required_optional_string")]
+    pub llvm_symbol: Option<String>,
+    pub expected_ptx: InstructionPattern,
+    #[serde(default)]
+    pub facts: EvidenceRecordDefaults,
+}
+
+fn deserialize_required_optional_string<'de, D>(deserializer: D) -> Result<Option<String>, D::Error>
+where
+    D: serde::Deserializer<'de>,
+{
+    Option::<String>::deserialize(deserializer)
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct EvidenceRecord {
+    pub id: String,
+    #[serde(default)]
+    pub source: Option<IntrinsicSource>,
+    #[serde(default)]
+    pub source_record: Option<String>,
+    #[serde(default)]
+    pub llvm_symbol: Option<String>,
+    #[serde(default)]
+    pub resolved_llvm_symbol: Option<String>,
+    #[serde(default)]
+    pub llvm_arguments: Vec<String>,
+    #[serde(default)]
+    pub llvm_results: Vec<String>,
+    #[serde(default)]
+    pub concrete_llvm_arguments: Vec<String>,
+    #[serde(default)]
+    pub concrete_llvm_results: Vec<String>,
+    pub target_triple: String,
+    pub gpu_target: String,
+    pub ptx_feature: String,
+    pub status: String,
+    #[serde(default)]
+    pub stages: Vec<EvidenceStage>,
+    #[serde(default)]
+    pub declaration_attributes_canonicalized: Option<bool>,
+    #[serde(default)]
+    pub runtime_validation: Option<RuntimeValidation>,
+    pub expected_ptx: InstructionPattern,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct EvidenceStage {
+    pub targets: Vec<String>,
+    pub representation: String,
+    pub stage: EvidenceStageKind,
+    #[serde(default)]
+    pub mechanism: Option<BackendLoweringMechanism>,
+    pub outcome: String,
+    pub detail: String,
+    #[serde(default)]
+    pub artifact_kind: Option<EvidenceArtifactKind>,
+    #[serde(default)]
+    pub tool_path: Option<String>,
+    #[serde(default)]
+    pub tool_version: Option<String>,
+    #[serde(default)]
+    pub tool_sha256: Option<String>,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum EvidenceArtifactKind {
+    Cubin,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum EvidenceStageKind {
+    DeclarationCanonicalization,
+    BackendCodegen,
+    DeviceLink,
+    PtxAssembly,
+    Runtime,
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/imported.rs b/crates/cuda-intrinsics-gen/src/model/imported.rs
new file mode 100644
index 0000000000..7b5f796120
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/imported.rs
@@ -0,0 +1,195 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use serde::{Deserialize, Serialize};
+
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct UpstreamLock {
+    pub schema: u32,
+    pub llvm: LockedLlvm,
+    pub llvm_tblgen: LockedTool,
+    #[serde(default)]
+    pub comparison_tools: Vec<LockedTool>,
+    pub dumps: LockedDumps,
+}
+
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct LockedLlvm {
+    pub repository: String,
+    pub revision: String,
+    pub provenance: String,
+    pub public_output_allowed: bool,
+}
+
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct LockedTool {
+    pub name: String,
+    pub version_line: String,
+    pub sha256: String,
+    #[serde(default)]
+    pub enforce_sha256: bool,
+    pub provenance: String,
+    pub built_from_llvm_revision: Option<String>,
+}
+
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct LockedDumps {
+    pub intrinsics_sha256: String,
+    pub nvptx_sha256: String,
+    pub normalized_imported_sha256: String,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ImportedFile {
+    pub schema: u32,
+    pub source: ImportedSource,
+    pub intrinsics: Vec<ImportedIntrinsic>,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ImportedSource {
+    pub llvm_repository: String,
+    pub llvm_revision: String,
+    pub llvm_tblgen_version: String,
+    pub llvm_tblgen_source_revision: String,
+    pub intrinsics_json_sha256: String,
+    pub nvptx_json_sha256: String,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ImportedIntrinsic {
+    pub source_record: String,
+    pub llvm_name: String,
+    pub arguments: Vec<String>,
+    pub results: Vec<String>,
+    pub classes: Vec<String>,
+    pub properties: Vec<String>,
+    pub selections: Vec<ImportedSelection>,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ImportedSelection {
+    pub source_record: String,
+    pub asm: String,
+    pub predicates: Vec<String>,
+    #[serde(
+        default,
+        skip_serializing_if = "ImportedSelectionConstraints::is_empty"
+    )]
+    pub constraints: ImportedSelectionConstraints,
+}
+
+/// Normalized constraints attached to an NVPTX instruction-selection record.
+///
+/// TableGen represents address-space-specific patterns through anonymous
+/// `PatFrag` records and can bind intrinsic arguments to integer literals.
+/// Keeping those facts separate from the assembly spelling lets policy select
+/// an exact lowering without parsing PTX text.
+#[derive(Debug, Clone, Default, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ImportedSelectionConstraints {
+    #[serde(default, skip_serializing_if = "Option::is_none")]
+    pub address_space: Option<ImportedAddressSpace>,
+    #[serde(default, skip_serializing_if = "Vec::is_empty")]
+    pub immediate_bindings: Vec<ImportedImmediateBinding>,
+}
+
+/// One integer literal fixed by an NVPTX instruction-selection pattern.
+#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ImportedImmediateBinding {
+    pub argument_index: usize,
+    pub value: i64,
+}
+
+impl ImportedSelectionConstraints {
+    pub fn is_empty(&self) -> bool {
+        self.address_space.is_none() && self.immediate_bindings.is_empty()
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ImportedAddressSpace {
+    Generic,
+    Shared,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn locked_tool_rejects_misspelled_security_field() {
+        let input = r#"
+name = "llvm-tblgen"
+version_line = "LLVM version test"
+sha256 = "abc"
+enforce_sha25 = true
+provenance = "test"
+"#;
+        let error = toml::from_str::<LockedTool>(input).unwrap_err();
+        assert!(error.to_string().contains("enforce_sha25"));
+    }
+
+    #[test]
+    fn imported_selection_rejects_misspelled_constraint() {
+        let input = r#"{
+            "source_record": "selection",
+            "asm": "op;",
+            "predicates": [],
+            "constraints": { "adress_space": "shared" }
+        }"#;
+        let error = serde_json::from_str::<ImportedSelection>(input).unwrap_err();
+        assert!(error.to_string().contains("adress_space"));
+    }
+
+    #[test]
+    fn imported_selection_preserves_immediate_binding() {
+        let input = r#"{
+            "source_record": "DOT2_lo_ss",
+            "asm": "dp2a.lo.s32.s32 $dst, $a, $b, $c;",
+            "predicates": ["hasDotInstructions"],
+            "constraints": {
+                "immediate_bindings": [
+                    { "argument_index": 2, "value": 0 }
+                ]
+            }
+        }"#;
+        let selection = serde_json::from_str::<ImportedSelection>(input).unwrap();
+        assert_eq!(
+            selection.constraints.immediate_bindings,
+            [ImportedImmediateBinding {
+                argument_index: 2,
+                value: 0,
+            }]
+        );
+        assert!(!selection.constraints.is_empty());
+    }
+
+    #[test]
+    fn imported_immediate_binding_rejects_misspelled_index() {
+        let input = r#"{
+            "source_record": "DOT2_lo_ss",
+            "asm": "dp2a.lo.s32.s32 $dst, $a, $b, $c;",
+            "predicates": [],
+            "constraints": {
+                "immediate_bindings": [
+                    { "argument_indx": 2, "value": 0 }
+                ]
+            }
+        }"#;
+        let error = serde_json::from_str::<ImportedSelection>(input).unwrap_err();
+        assert!(error.to_string().contains("argument_indx"));
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/model/mod.rs b/crates/cuda-intrinsics-gen/src/model/mod.rs
new file mode 100644
index 0000000000..10713b4d27
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/mod.rs
@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+mod abi_ledger;
+mod catalog;
+mod contracts;
+mod core;
+mod evidence;
+mod imported;
+mod overlay;
+
+pub use self::abi_ledger::*;
+pub use self::catalog::*;
+pub use self::contracts::*;
+pub use self::core::*;
+pub use self::evidence::*;
+pub use self::imported::*;
+pub use self::overlay::*;
diff --git a/crates/cuda-intrinsics-gen/src/model/overlay.rs b/crates/cuda-intrinsics-gen/src/model/overlay.rs
new file mode 100644
index 0000000000..60b1b6e351
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/model/overlay.rs
@@ -0,0 +1,915 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::catalog::TargetContract;
+use super::contracts::{
+    ActiveMask, Clc, ClcOperation, ClusterBarrier, ClusterBarrierMode, ClusterMemory,
+    ClusterMemoryOperation, CpAsyncControl, CpAsyncCopy, CpAsyncMbarrier, DebugControl,
+    DebugControlOperation, DotProduct, ExtendedMinMax, ExtendedMinMaxFormat, ExtendedMinMaxNan,
+    ExtendedMinMaxOperation, ExtendedMinMaxSubnormal, IntegerMinMax, LdmatrixAdapter,
+    LdmatrixSafety, LdmatrixVariant, MbarrierBasic, MbarrierExtended, MbarrierExtendedOperation,
+    Movmatrix, PackedAlu, PackedAtomic, PackedConversion, PackedConversionDestinationFormat,
+    PackedConversionSaturation, Prmt, PrmtMode, Redux, RegisterMma, RegisterMmaAccumulator,
+    RegisterMmaElement, RegisterMmaOperation, RegisterMmaOverflow, RegisterMmaShape,
+    ScalarArithmetic, ScalarArithmeticFormat, ScalarArithmeticOperation, ScalarArithmeticRounding,
+    ScalarArithmeticSaturation, ScalarArithmeticSubnormal, ScalarConversion,
+    ScalarConversionRounding, ScalarConversionSaturation, ScalarMath, ScalarMathFormat,
+    ScalarMathOperation, ScalarMathPrecision, ScalarMathSubnormal, SparseMma, SparseMmaElement,
+    SparseMmaMetadata, SparseMmaOverflow, SparseMmaShape, SpecialRegister, SpecialRegisterKind,
+    StmatrixLayout, StmatrixMultiplicity, Tcgen05, Tcgen05CpGroup, Tcgen05CpMember,
+    Tcgen05LdMultiplicity, Tcgen05LdShape, Tcgen05MmaAlias, Tcgen05MmaForm, Tcgen05Operation, Tma,
+    TmaOperation, TmaReductionLoadMode, TmaReductionOperation, Vote, WarpBarrier, WarpMatch,
+    WarpShuffle, WgmmaControl, WgmmaControlMode,
+};
+use super::core::{BackendLoweringMechanism, IntrinsicBackend, IntrinsicSource, RuntimeValidation};
+use super::imported::ImportedAddressSpace;
+use crate::ptx::InstructionPattern;
+use serde::{Deserialize, Serialize};
+
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct OverlayFile {
+    pub schema: u32,
+    pub catalog_version: String,
+    pub intrinsic_abi: u32,
+    pub backend_profile: String,
+    #[serde(default)]
+    pub shards: Vec<String>,
+    #[serde(rename = "intrinsic")]
+    #[serde(default)]
+    pub intrinsics: Vec<OverlayIntrinsic>,
+}
+
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct OverlayShardFile {
+    pub schema: u32,
+    pub family: String,
+    #[serde(rename = "intrinsic")]
+    #[serde(default)]
+    pub intrinsics: Vec<OverlayIntrinsic>,
+    #[serde(default)]
+    pub register_mma_int4: Option<RegisterMmaIntegerAdmission>,
+    #[serde(default)]
+    pub register_mma_int8: Option<RegisterMmaIntegerAdmission>,
+    #[serde(default)]
+    pub register_mma_b1: Option<RegisterMmaBinaryAdmission>,
+    #[serde(default)]
+    pub register_mma_f8f6f4_f32: Option<RegisterMmaF8F6F4Admission>,
+    #[serde(default)]
+    pub register_mma_f8f6f4_f16: Option<RegisterMmaF8F6F4Admission>,
+    #[serde(default)]
+    pub register_mma_mxf8f6f4_f32: Option<RegisterMmaF8F6F4Admission>,
+    #[serde(default)]
+    pub register_mma_fp8: Option<RegisterMmaFp8Admission>,
+    #[serde(default)]
+    pub register_mma_ampere_float: Option<RegisterMmaAmpereFloatAdmission>,
+    #[serde(default, alias = "sparse_mma_int8")]
+    pub sparse_mma_integer: Option<SparseMmaIntegerAdmission>,
+    #[serde(default)]
+    pub sparse_mma_f8f6f4_f32: Option<SparseMmaF8F6F4Admission>,
+    #[serde(default)]
+    pub sparse_mma_f8f6f4_f16: Option<SparseMmaF8F6F4F16Admission>,
+    #[serde(default)]
+    pub prmt: Option<PrmtAdmission>,
+    #[serde(default)]
+    pub packed_conversion_fp8: Option<PackedConversionFp8Admission>,
+    #[serde(default)]
+    pub packed_conversion_fp8_f16x2: Option<PackedConversionFp8F16x2Admission>,
+    #[serde(default)]
+    pub scalar_conversion: Option<ScalarConversionAdmission>,
+    #[serde(default)]
+    pub scalar_arithmetic: Option<ScalarArithmeticAdmission>,
+    #[serde(default)]
+    pub extended_minmax: Option<ExtendedMinMaxAdmission>,
+    #[serde(default)]
+    pub cluster_sreg: Option<ClusterSregAdmission>,
+    #[serde(default)]
+    pub cluster_barrier: Option<ClusterBarrierAdmission>,
+    #[serde(default)]
+    pub mbarrier_extended: Option<MbarrierExtendedAdmission>,
+    #[serde(default)]
+    pub special_registers: Option<SpecialRegisterAdmission>,
+    #[serde(default)]
+    pub debug_control: Option<DebugControlAdmission>,
+    #[serde(default)]
+    pub threadfence: Option<ThreadfenceAdmission>,
+    #[serde(default)]
+    pub cluster_memory: Option<ClusterMemoryAdmission>,
+    #[serde(default)]
+    pub stmatrix: Option<StmatrixAdmission>,
+    #[serde(default)]
+    pub clc: Option<ClcAdmission>,
+    #[serde(default)]
+    pub wgmma_controls: Option<WgmmaControlAdmission>,
+    #[serde(default)]
+    pub tma: Option<TmaAdmission>,
+    #[serde(default)]
+    pub tcgen05: Option<Tcgen05Admission>,
+    #[serde(default)]
+    pub scalar_math: Option<ScalarMathAdmission>,
+}
+
+/// Compact admission for unary scalar floating-point math operations.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ScalarMathAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<ScalarMathAdmissionVariant>,
+}
+
+/// One reviewed scalar math variant.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ScalarMathAdmissionVariant {
+    pub abi_id: String,
+    #[serde(default)]
+    pub libnvvm_evidence_profile: Option<String>,
+    pub format: ScalarMathFormat,
+    pub operation: ScalarMathOperation,
+    pub precision: ScalarMathPrecision,
+    pub subnormal: ScalarMathSubnormal,
+}
+
+/// Compact admission for the four existing `stmatrix` stores.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct StmatrixAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<StmatrixAdmissionVariant>,
+}
+
+/// One reviewed `stmatrix` multiplicity and layout.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct StmatrixAdmissionVariant {
+    pub abi_id: String,
+    pub multiplicity: StmatrixMultiplicity,
+    pub layout: StmatrixLayout,
+}
+
+/// Compact admission for the remaining handwritten mbarrier operations.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct MbarrierExtendedAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<MbarrierExtendedAdmissionVariant>,
+}
+
+/// One reviewed extended-mbarrier operation and its reserved ABI ID.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct MbarrierExtendedAdmissionVariant {
+    pub abi_id: String,
+    pub operation: MbarrierExtendedOperation,
+}
+
+/// Compact admission for Hopper cluster special registers.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ClusterSregAdmission {
+    pub axes: Vec<String>,
+    pub xyz_product_count: usize,
+    pub record_count: usize,
+}
+
+/// Compact admission for the six cluster-barrier instructions.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ClusterBarrierAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<ClusterBarrierAdmissionVariant>,
+}
+
+/// One reviewed cluster-barrier spelling.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ClusterBarrierAdmissionVariant {
+    pub abi_id: String,
+    pub mode: ClusterBarrierMode,
+}
+
+/// Compact admission for cluster address mapping and remote shared reads.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ClusterMemoryAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<ClusterMemoryAdmissionVariant>,
+}
+
+/// One reviewed cluster-memory operation and its reserved ABI ID.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ClusterMemoryAdmissionVariant {
+    pub abi_id: String,
+    pub operation: ClusterMemoryOperation,
+}
+
+/// Compact admission for the three WGMMA control instructions.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct WgmmaControlAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<WgmmaControlAdmissionVariant>,
+}
+
+/// One reviewed WGMMA control operation.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct WgmmaControlAdmissionVariant {
+    pub abi_id: String,
+    pub mode: WgmmaControlMode,
+}
+
+/// Compact admission for the reviewed non-launch special-register reads.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct SpecialRegisterAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    pub registers: Vec<SpecialRegisterKind>,
+    pub product_count: usize,
+}
+
+/// Compact admission for PTX debug controls.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct DebugControlAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    pub operations: Vec<DebugControlOperation>,
+    /// Filled only when this pending shard is aggregated.
+    #[serde(default)]
+    pub abi_ids: Vec<String>,
+}
+
+/// Compact admission for the three CUDA thread fences.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ThreadfenceAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<ThreadfenceAdmissionVariant>,
+}
+
+/// One reviewed thread-fence scope.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ThreadfenceAdmissionVariant {
+    pub abi_id: String,
+    pub scope: ThreadfenceScope,
+}
+
+/// Scope encoded by a PTX `membar` instruction.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum ThreadfenceScope {
+    Cta,
+    Device,
+    System,
+}
+
+/// Compact admission for Cluster Launch Control.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ClcAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<ClcAdmissionVariant>,
+}
+
+/// One reviewed Cluster Launch Control operation.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ClcAdmissionVariant {
+    pub abi_id: String,
+    pub operation: ClcOperation,
+}
+
+/// Compact admission for the existing TMA copy and group operations.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct TmaAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    #[serde(default)]
+    pub reduce_llvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub reduce_libnvvm_evidence_profile: Option<String>,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<TmaAdmissionVariant>,
+    #[serde(rename = "reduce_variant", default)]
+    pub reduce_variants: Vec<TmaReductionAdmissionVariant>,
+}
+
+/// One reviewed TMA operation and its reserved ABI ID.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct TmaAdmissionVariant {
+    pub abi_id: String,
+    pub operation: TmaOperation,
+}
+
+/// One reviewed tensor-reduction operation and its reserved ABI ID.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct TmaReductionAdmissionVariant {
+    pub abi_id: String,
+    pub operation: TmaReductionOperation,
+    pub load_mode: TmaReductionLoadMode,
+    pub dimensions: u8,
+}
+
+/// Compact admission for the existing Tensor Core Generation 5 operations.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05Admission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    #[serde(default)]
+    pub cp_llvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub cp_libnvvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub ld_llvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub ld_libnvvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub st_llvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub st_libnvvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub offset_llvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub offset_libnvvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub control_llvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub control_libnvvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub mma_llvm_evidence_profile: Option<String>,
+    #[serde(default)]
+    pub mma_libnvvm_evidence_profile: Option<String>,
+    #[serde(rename = "mma_llvm_target_contract", default)]
+    pub mma_llvm_target_contracts: Vec<TargetContract>,
+    #[serde(rename = "mma_libnvvm_target_contract", default)]
+    pub mma_libnvvm_target_contracts: Vec<TargetContract>,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<Tcgen05AdmissionVariant>,
+    #[serde(rename = "cp_variant", default)]
+    pub cp_variants: Vec<Tcgen05CpAdmissionVariant>,
+    #[serde(rename = "ld_variant", default)]
+    pub ld_variants: Vec<Tcgen05LdAdmissionVariant>,
+    #[serde(rename = "st_variant", default)]
+    pub st_variants: Vec<Tcgen05StAdmissionVariant>,
+    #[serde(rename = "ld_offset_variant", default)]
+    pub ld_offset_variants: Vec<Tcgen05LdAdmissionVariant>,
+    #[serde(rename = "st_offset_variant", default)]
+    pub st_offset_variants: Vec<Tcgen05StAdmissionVariant>,
+    #[serde(rename = "mma_variant", default)]
+    pub mma_variants: Vec<Tcgen05MmaAdmissionVariant>,
+}
+
+/// One reviewed tcgen05 operation and its reserved ABI ID.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05AdmissionVariant {
+    pub abi_id: String,
+    pub operation: Tcgen05Operation,
+}
+
+/// One reviewed tcgen05 copy member and CTA group.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05CpAdmissionVariant {
+    pub abi_id: String,
+    pub member: Tcgen05CpMember,
+    pub group: Tcgen05CpGroup,
+}
+
+/// One reviewed tcgen05 load shape, repetition, and packing mode.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05LdAdmissionVariant {
+    pub abi_id: String,
+    pub shape: Tcgen05LdShape,
+    pub multiplicity: Tcgen05LdMultiplicity,
+    pub pack16: bool,
+}
+
+/// One reviewed tcgen05 store shape, repetition, and unpacking mode.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05StAdmissionVariant {
+    pub abi_id: String,
+    pub shape: Tcgen05LdShape,
+    pub multiplicity: Tcgen05LdMultiplicity,
+    pub unpack16: bool,
+}
+
+/// One reviewed tcgen05 MMA source form or compatibility alias.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct Tcgen05MmaAdmissionVariant {
+    pub abi_id: String,
+    pub form: Tcgen05MmaForm,
+    #[serde(default)]
+    pub alias: Option<Tcgen05MmaAlias>,
+}
+
+/// Compact admission for the closed `prmt` family.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct PrmtAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<PrmtAdmissionVariant>,
+}
+
+/// One reviewed member of the `prmt` family.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct PrmtAdmissionVariant {
+    pub abi_id: String,
+    pub mode: PrmtMode,
+}
+
+/// Compact admission for the closed scalar-f32 to packed-FP8 family.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct PackedConversionFp8Admission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    pub destination_formats: Vec<PackedConversionDestinationFormat>,
+    pub saturations: Vec<PackedConversionSaturation>,
+    pub product_count: usize,
+}
+
+/// Compact admission for packed FP8 conversions whose other side is `f16x2`.
+///
+/// Covers both directions: packing `f16x2` down to `e4m3x2`/`e5m2x2`, and
+/// unpacking those back to `f16x2`. Both are single-operand conversions, unlike
+/// the scalar-`f32` pair admitted by [`PackedConversionFp8Admission`].
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct PackedConversionFp8F16x2Admission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    pub fp8_formats: Vec<PackedConversionFp8Format>,
+    pub directions: Vec<PackedConversionFp8Direction>,
+    pub relu_variants: bool,
+    pub product_count: usize,
+}
+
+/// The FP8 side of an `f16x2` conversion pair.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedConversionFp8Format {
+    E4m3x2,
+    E5m2x2,
+}
+
+/// Which way an FP8/`f16x2` conversion runs.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Deserialize)]
+#[serde(rename_all = "snake_case")]
+pub enum PackedConversionFp8Direction {
+    /// `f16x2` narrowed to packed FP8, always saturating to finite.
+    Pack,
+    /// Packed FP8 widened back to `f16x2`, which is always exact.
+    Unpack,
+}
+
+/// Compact admission for scalar F32-to-TF32 conversions.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ScalarConversionAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<ScalarConversionAdmissionVariant>,
+}
+
+/// One reviewed scalar conversion variant.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ScalarConversionAdmissionVariant {
+    pub abi_id: String,
+    pub rounding: ScalarConversionRounding,
+    pub saturation: ScalarConversionSaturation,
+}
+
+/// Compact admission for scalar floating-point arithmetic.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ScalarArithmeticAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<ScalarArithmeticAdmissionVariant>,
+}
+
+/// One reviewed scalar arithmetic variant.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ScalarArithmeticAdmissionVariant {
+    pub abi_id: String,
+    pub format: ScalarArithmeticFormat,
+    pub operation: ScalarArithmeticOperation,
+    pub rounding: ScalarArithmeticRounding,
+    pub subnormal: ScalarArithmeticSubnormal,
+    pub saturation: ScalarArithmeticSaturation,
+}
+
+/// Compact admission for the exact extended floating-point min/max family.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ExtendedMinMaxAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<ExtendedMinMaxAdmissionVariant>,
+}
+
+/// One reviewed extended min/max variant.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct ExtendedMinMaxAdmissionVariant {
+    pub abi_id: String,
+    pub format: ExtendedMinMaxFormat,
+    pub operation: ExtendedMinMaxOperation,
+    pub subnormal: ExtendedMinMaxSubnormal,
+    pub nan: ExtendedMinMaxNan,
+    pub xorsign_abs: bool,
+}
+
+/// Compact admission for a closed dense integer register-MMA family.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct RegisterMmaIntegerAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<RegisterMmaIntegerVariant>,
+}
+
+/// One reviewed member of a dense integer register-MMA family.
+#[derive(Debug, Clone, Copy, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct RegisterMmaIntegerVariant {
+    pub shape: RegisterMmaShape,
+    pub a_element: RegisterMmaElement,
+    pub b_element: RegisterMmaElement,
+    pub overflow: RegisterMmaOverflow,
+}
+
+/// Compact admission for the closed dense binary register-MMA family.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct RegisterMmaBinaryAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    #[serde(rename = "variant")]
+    pub variants: Vec<RegisterMmaBinaryVariant>,
+}
+
+/// One reviewed member of the dense binary register-MMA family.
+#[derive(Debug, Clone, Copy, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct RegisterMmaBinaryVariant {
+    pub shape: RegisterMmaShape,
+    pub operation: RegisterMmaOperation,
+}
+
+/// Compact admission for one dense Blackwell `kind::f8f6f4` matrix.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct RegisterMmaF8F6F4Admission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    /// Legacy shard metadata retained only so older overlays continue to parse.
+    /// ABI identity is bound from the append-only ledger by catalog ID.
+    #[serde(default, rename = "first_abi_id")]
+    pub _legacy_first_abi_id: Option<String>,
+    pub a_elements: Vec<RegisterMmaElement>,
+    pub b_elements: Vec<RegisterMmaElement>,
+    pub product_count: usize,
+    pub targets: Vec<String>,
+}
+
+/// Compact admission for the standard FP8 register-MMA family.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct RegisterMmaFp8Admission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    /// Legacy shard metadata retained only so older overlays continue to parse.
+    /// ABI identity is bound from the append-only ledger by catalog ID.
+    #[serde(default, rename = "first_abi_id")]
+    pub _legacy_first_abi_id: Option<String>,
+    pub shapes: Vec<RegisterMmaShape>,
+    pub accumulators: Vec<RegisterMmaAccumulator>,
+    pub a_elements: Vec<RegisterMmaElement>,
+    pub b_elements: Vec<RegisterMmaElement>,
+    pub product_count: usize,
+}
+
+/// Compact admission for the reviewed Ampere floating-point MMA forms.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct RegisterMmaAmpereFloatAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    /// Legacy shard metadata retained only so older overlays continue to parse.
+    /// ABI identity is bound from the append-only ledger by catalog ID.
+    #[serde(default, rename = "first_abi_id")]
+    pub _legacy_first_abi_id: Option<String>,
+    pub product_count: usize,
+    #[serde(rename = "variant")]
+    pub variants: Vec<RegisterMmaAmpereFloatVariant>,
+}
+
+/// One reviewed Ampere floating-point MMA form.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct RegisterMmaAmpereFloatVariant {
+    pub shape: RegisterMmaShape,
+    pub accumulator: RegisterMmaAccumulator,
+    pub element: RegisterMmaElement,
+}
+
+/// Compact admission for a sparse integer register-MMA family.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct SparseMmaIntegerAdmission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    pub metadata: SparseMmaMetadata,
+    #[serde(rename = "variant")]
+    pub variants: Vec<SparseMmaIntegerVariant>,
+}
+
+/// One reviewed member of a sparse integer register-MMA family.
+#[derive(Debug, Clone, Copy, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct SparseMmaIntegerVariant {
+    pub shape: SparseMmaShape,
+    pub a_element: SparseMmaElement,
+    pub b_element: SparseMmaElement,
+    pub overflow: SparseMmaOverflow,
+}
+
+/// Compact admission for ordered sparse `kind::f8f6f4` F32 MMA.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct SparseMmaF8F6F4Admission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    pub a_elements: Vec<SparseMmaElement>,
+    pub b_elements: Vec<SparseMmaElement>,
+    pub product_count: usize,
+}
+
+/// Compact admission for ordered sparse `kind::f8f6f4` packed-F16 MMA.
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct SparseMmaF8F6F4F16Admission {
+    pub llvm_evidence_profile: String,
+    pub libnvvm_evidence_profile: String,
+    pub runtime_validation: RuntimeValidation,
+    /// Legacy shard metadata retained only so older overlays continue to parse.
+    /// ABI identity is bound from the append-only ledger by catalog ID.
+    #[serde(default, rename = "first_abi_id")]
+    pub _legacy_first_abi_id: Option<String>,
+    pub a_elements: Vec<SparseMmaElement>,
+    pub b_elements: Vec<SparseMmaElement>,
+    pub product_count: usize,
+}
+
+#[derive(Debug, Clone, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct OverlayIntrinsic {
+    pub id: String,
+    pub abi_id: String,
+    pub operation_key: String,
+    pub family: String,
+    /// Imported LLVM records use the legacy `source_record` field below.
+    /// PTX-native records must instead carry an explicit tagged source.
+    #[serde(default)]
+    pub source: Option<IntrinsicSource>,
+    #[serde(default)]
+    pub source_record: Option<String>,
+    pub rust_module: String,
+    pub rust_name: String,
+    #[serde(default)]
+    pub rust_arguments: Vec<String>,
+    pub rust_result: String,
+    pub safe: bool,
+    #[serde(default)]
+    pub must_use: bool,
+    pub safe_allowlist_reason: Option<String>,
+    pub public_rust_path: String,
+    #[serde(default)]
+    pub compatibility_rust_paths: Vec<String>,
+    pub dialect_op_type: String,
+    pub dialect_op_name: String,
+    #[serde(default)]
+    pub dialect_operands: Vec<String>,
+    #[serde(default)]
+    pub dialect_results: Vec<String>,
+    #[serde(default)]
+    pub llvm_symbol: Option<String>,
+    #[serde(default)]
+    pub resolved_llvm_symbol: Option<String>,
+    #[serde(default)]
+    pub llvm_arguments: Vec<String>,
+    #[serde(default)]
+    pub llvm_results: Vec<String>,
+    pub pure: bool,
+    pub memory: String,
+    pub convergent: bool,
+    pub execution_scope: String,
+    pub minimum_ptx: String,
+    #[serde(default)]
+    pub minimum_sm: Option<String>,
+    pub ptx_result: String,
+    pub targets: String,
+    pub ptx_isa_version: String,
+    pub ptx_isa_section: String,
+    pub ptx_isa_url: String,
+    pub lowering: String,
+    #[serde(default)]
+    pub backend_lowerings: Vec<OverlayBackendLowering>,
+    #[serde(default)]
+    pub packed_atomic: Option<PackedAtomic>,
+    #[serde(default)]
+    pub redux: Option<Redux>,
+    #[serde(default)]
+    pub vote: Option<Vote>,
+    #[serde(default)]
+    pub active_mask: Option<ActiveMask>,
+    #[serde(default)]
+    pub warp_match: Option<WarpMatch>,
+    #[serde(default)]
+    pub warp_barrier: Option<WarpBarrier>,
+    #[serde(default)]
+    pub warp_shuffle: Option<WarpShuffle>,
+    #[serde(default)]
+    pub dot_product: Option<DotProduct>,
+    #[serde(default)]
+    pub packed_alu: Option<PackedAlu>,
+    #[serde(default)]
+    pub integer_minmax: Option<IntegerMinMax>,
+    #[serde(default)]
+    pub packed_conversion: Option<PackedConversion>,
+    #[serde(default)]
+    pub scalar_conversion: Option<ScalarConversion>,
+    #[serde(default)]
+    pub scalar_arithmetic: Option<ScalarArithmetic>,
+    #[serde(default)]
+    pub scalar_math: Option<ScalarMath>,
+    #[serde(default)]
+    pub extended_minmax: Option<ExtendedMinMax>,
+    #[serde(default)]
+    pub cp_async_copy: Option<CpAsyncCopy>,
+    #[serde(default)]
+    pub cp_async_control: Option<CpAsyncControl>,
+    #[serde(default)]
+    pub cp_async_mbarrier: Option<CpAsyncMbarrier>,
+    #[serde(default)]
+    pub mbarrier_basic: Option<MbarrierBasic>,
+    #[serde(default)]
+    pub movmatrix: Option<Movmatrix>,
+    #[serde(default)]
+    pub mbarrier_extended: Option<MbarrierExtended>,
+    #[serde(default)]
+    pub register_mma: Option<RegisterMma>,
+    #[serde(default)]
+    pub sparse_mma: Option<SparseMma>,
+    #[serde(default)]
+    pub prmt: Option<Prmt>,
+    #[serde(default)]
+    pub cluster_barrier: Option<ClusterBarrier>,
+    #[serde(default)]
+    pub wgmma_control: Option<WgmmaControl>,
+    #[serde(default)]
+    pub special_register: Option<SpecialRegister>,
+    #[serde(default)]
+    pub debug_control: Option<DebugControl>,
+    #[serde(default)]
+    pub cluster_memory: Option<ClusterMemory>,
+    #[serde(default)]
+    pub clc: Option<Clc>,
+    #[serde(default)]
+    pub tma: Option<Tma>,
+    #[serde(default)]
+    pub tcgen05: Option<Tcgen05>,
+    #[serde(default)]
+    pub ldmatrix_variant: Option<LdmatrixVariant>,
+    #[serde(default)]
+    pub ldmatrix_safety: Option<LdmatrixSafety>,
+    #[serde(default)]
+    pub ldmatrix_adapter: Option<LdmatrixAdapter>,
+    #[serde(default)]
+    pub selected_address_space: Option<ImportedAddressSpace>,
+    pub expected_ptx: InstructionPattern,
+    pub summary: String,
+}
+
+/// Backend-specific lowering selected by reviewed evidence.
+#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)]
+#[serde(deny_unknown_fields)]
+pub struct OverlayBackendLowering {
+    pub backend: IntrinsicBackend,
+    pub mechanism: BackendLoweringMechanism,
+    pub evidence_profile: String,
+    /// Optional exact target alternatives for this backend route.
+    #[serde(default)]
+    pub targets: Option<String>,
+    /// Optional backend-profile floor. When absent, the intrinsic's native
+    /// target requirement is used.
+    #[serde(default)]
+    pub minimum_ptx: Option<String>,
+    #[serde(default)]
+    pub minimum_sm: Option<String>,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use crate::model::SparseMmaElement;
+
+    #[test]
+    fn sparse_mma_admission_accepts_the_canonical_name_and_legacy_alias() {
+        let canonical = r#"
+schema = 25
+family = "sparse_mma"
+
+[sparse_mma_integer]
+llvm_evidence_profile = "llvm"
+libnvvm_evidence_profile = "libnvvm"
+runtime_validation = "unexecuted"
+metadata = "ordered"
+
+[[sparse_mma_integer.variant]]
+shape = "m16n8k64"
+a_element = "s4"
+b_element = "u4"
+overflow = "wrapping"
+"#;
+        let parsed = toml::from_str::<OverlayShardFile>(canonical).unwrap();
+        assert_eq!(
+            parsed.sparse_mma_integer.unwrap().variants[0].b_element,
+            SparseMmaElement::U4
+        );
+
+        let legacy = canonical.replace("sparse_mma_integer", "sparse_mma_int8");
+        assert!(
+            toml::from_str::<OverlayShardFile>(&legacy)
+                .unwrap()
+                .sparse_mma_integer
+                .is_some()
+        );
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/render.rs b/crates/cuda-intrinsics-gen/src/render.rs
deleted file mode 100644
index 7ea55ce743..0000000000
--- a/crates/cuda-intrinsics-gen/src/render.rs
+++ /dev/null
@@ -1,25281 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-use crate::model::{
-    ActiveMaskAdapter, BackendLoweringMechanism, CatalogFile, CatalogHardwareAlternative,
-    CatalogHardwareTarget, CatalogIntrinsic, CatalogLlvm, CatalogSelection, CatalogTargetContract,
-    ClcAdapter, ClcOperation, ClusterBarrierMode, ClusterBarrierOrdering, ClusterMemoryAdapter,
-    ClusterMemoryOperation, ClusterMemorySourceContract, CpAsyncCachePolicy,
-    CpAsyncControlOperation, CpAsyncMbarrierAdapter, CpAsyncMbarrierOperation,
-    CpAsyncMbarrierStateSpace, CpAsyncSourceSize, DebugControlAdapter, DebugControlOperation,
-    DotProductAdapter, DotProductOperation, DotProductSignedness, EvidenceArtifactKind,
-    EvidenceStageKind, ExecutionControlOperation, ExtendedMinMaxAdapter, ExtendedMinMaxFormat,
-    ExtendedMinMaxNan, ExtendedMinMaxOperation, ExtendedMinMaxSubnormal, ImportedAddressSpace,
-    IntegerMinMaxFormat, IntegerMinMaxOperation, IntrinsicBackend, IntrinsicSource,
-    LdmatrixElement, LdmatrixLayout, LdmatrixMultiplicity, LdmatrixParticipation, LdmatrixShape,
-    LdmatrixStateSpace, MbarrierBasicAdapter, MbarrierBasicOperation, MbarrierExtendedAdapter,
-    MbarrierExtendedOperation, MbarrierExtendedSourceContract, MbarrierStateSpace,
-    PackedAluAdapter, PackedAluFormat, PackedAluOperation, PackedAtomicFormat,
-    PackedConversionAdapter, PackedConversionDestinationFormat, PackedConversionRounding,
-    PackedConversionSaturation, PackedConversionSourceFormat, PrmtAdapter, PrmtMode, ReduxAdapter,
-    RegisterMmaAccumulator, RegisterMmaAdapter, RegisterMmaCompatibilitySource, RegisterMmaElement,
-    RegisterMmaKind, RegisterMmaLayout, RegisterMmaOperation, RegisterMmaOverflow,
-    RegisterMmaShape, RuntimeValidation, ScalarArithmeticFormat, ScalarArithmeticOperation,
-    ScalarArithmeticRounding, ScalarArithmeticSaturation, ScalarArithmeticSubnormal,
-    ScalarConversionRounding, ScalarConversionSaturation, ScalarMathFormat, ScalarMathOperation,
-    ScalarMathPrecision, ScalarMathSubnormal, SparseMma, SparseMmaAccumulator, SparseMmaAdapter,
-    SparseMmaCompatibilitySource, SparseMmaElement, SparseMmaLayout, SparseMmaMetadata,
-    SparseMmaOverflow, SparseMmaSelector, SparseMmaShape, SpecialRegisterObservation,
-    SpecialRegisterOutputConstraint, SpecialRegisterPtxType, StmatrixLayout, StmatrixMultiplicity,
-    Tcgen05Adapter, Tcgen05CpGroup, Tcgen05CpMember, Tcgen05LdMultiplicity, Tcgen05LdShape,
-    Tcgen05Mma, Tcgen05MmaAlias, Tcgen05MmaBUsage, Tcgen05MmaForm, Tcgen05MmaKind,
-    Tcgen05MmaSelectorLayout, Tcgen05Operation, Tcgen05SourceContract, TmaAdapter, TmaOperation,
-    TmaReductionLoadMode, TmaReductionOperation, VoteAdapter, VoteMode, WarpBarrierAdapter,
-    WarpMatchAdapter, WarpMatchMode, WarpShuffleAdapter, WarpShuffleMode,
-    WarpShuffleOperandEncoding, WarpShuffleValueKind, WgmmaControlAdapter, WgmmaControlMode,
-    WgmmaControlParticipation,
-};
-use anyhow::{Result, ensure};
-use std::collections::{BTreeMap, BTreeSet};
-use std::fmt::Write as _;
-use std::path::PathBuf;
-
-pub fn all_outputs(
-    catalog: &CatalogFile,
-    catalog_json: String,
-    catalog_sha256: &str,
-) -> Result<BTreeMap<PathBuf, String>> {
-    validate_renderable(catalog)?;
-    let mut outputs = BTreeMap::new();
-    outputs.insert("intrinsics/catalog.json".into(), catalog_json);
-    outputs.insert(
-        "crates/cuda-intrinsics/src/generated/mod.rs".into(),
-        render_raw_mod(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        format!(
-            "crates/cuda-intrinsics/src/generated/abi_v{}.rs",
-            catalog.intrinsic_abi
-        )
-        .into(),
-        render_raw_abi(catalog, catalog_sha256)?,
-    );
-    outputs.insert(
-        "crates/cuda-device/src/generated/register_mma.rs".into(),
-        render_compat_register_mma(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/cuda-device/src/generated/ldmatrix.rs".into(),
-        render_compat_ldmatrix(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/cuda-device/src/generated/sparse_mma.rs".into(),
-        render_compat_sparse_mma(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/cuda-device/src/generated/sreg.rs".into(),
-        render_compat_sreg(catalog, catalog_sha256),
-    );
-    for module in ["debug", "grid", "shared", "warp"] {
-        outputs.insert(
-            format!("crates/cuda-device/src/generated/{module}_sreg.rs").into(),
-            render_compat_special_register_module(catalog, catalog_sha256, module),
-        );
-    }
-    outputs.insert(
-        "crates/cuda-device/src/generated/cluster_sreg.rs".into(),
-        render_compat_cluster_sreg(catalog, catalog_sha256),
-    );
-    if sync_intrinsics(catalog).any(|record| threadfence_ptx_level(record).is_some()) {
-        outputs.insert(
-            "crates/cuda-device/src/generated/fence.rs".into(),
-            render_compat_fence(catalog, catalog_sha256),
-        );
-    }
-    outputs.insert(
-        "crates/cuda-device/src/generated/dotprod.rs".into(),
-        render_compat_dotprod(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/cuda-device/src/generated/prmt.rs".into(),
-        render_compat_prmt(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/cuda-device/src/generated/cluster_barrier.rs".into(),
-        render_compat_cluster_barrier(catalog, catalog_sha256),
-    );
-    if cluster_memory(catalog).next().is_some() {
-        outputs.insert(
-            "crates/cuda-device/src/generated/cluster_memory.rs".into(),
-            render_compat_cluster_memory(catalog, catalog_sha256),
-        );
-    }
-    if stmatrices(catalog).next().is_some() {
-        outputs.insert(
-            "crates/cuda-device/src/generated/stmatrix.rs".into(),
-            render_compat_stmatrix(catalog, catalog_sha256),
-        );
-    }
-    if movmatrix(catalog).next().is_some() {
-        outputs.insert(
-            "crates/cuda-device/src/generated/movmatrix.rs".into(),
-            render_compat_movmatrix(catalog, catalog_sha256),
-        );
-    }
-    if wgmma_controls(catalog).next().is_some() {
-        outputs.insert(
-            "crates/cuda-device/src/generated/wgmma_control.rs".into(),
-            render_compat_wgmma_control(catalog, catalog_sha256),
-        );
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/wgmma_control.rs".into(),
-            render_dialect_wgmma_control(catalog, catalog_sha256),
-        );
-    }
-    outputs.insert(
-        "crates/cuda-device/src/generated/atomic.rs".into(),
-        render_compat_packed_atomic(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/cuda-device/src/generated/async_copy.rs".into(),
-        render_compat_cp_async_copy(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/cuda-device/src/generated/mbarrier_basic.rs".into(),
-        render_compat_mbarrier_basic(catalog, catalog_sha256),
-    );
-    if mbarrier_extended(catalog).next().is_some() {
-        outputs.insert(
-            "crates/cuda-device/src/generated/mbarrier_extended.rs".into(),
-            render_compat_mbarrier_extended(catalog, catalog_sha256),
-        );
-    }
-    outputs.insert(
-        "crates/cuda-device/src/generated/bf16x2.rs".into(),
-        render_compat_packed_alu(catalog, catalog_sha256, PackedAluFormat::Bf16x2),
-    );
-    for (module, format) in [
-        ("f16", ExtendedMinMaxFormat::F16),
-        ("bf16", ExtendedMinMaxFormat::Bf16),
-    ] {
-        if extended_minmax(catalog).any(|record| extended_minmax_contract(record).format == format)
-        {
-            outputs.insert(
-                format!("crates/cuda-device/src/generated/{module}.rs").into(),
-                render_compat_scalar_minmax(catalog, catalog_sha256, module),
-            );
-        }
-    }
-    outputs.insert(
-        "crates/cuda-device/src/generated/f16x2.rs".into(),
-        render_compat_packed_alu(catalog, catalog_sha256, PackedAluFormat::F16x2),
-    );
-    for module in ["i16x2", "int"] {
-        if integer_minmaxes(catalog).any(|record| record.rust.module == module) {
-            outputs.insert(
-                format!("crates/cuda-device/src/generated/{module}.rs").into(),
-                render_compat_integer_minmax(catalog, catalog_sha256, module),
-            );
-        }
-    }
-    if integer_minmaxes(catalog).next().is_some() {
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/integer_minmax.rs".into(),
-            render_dialect_integer_minmax(catalog, catalog_sha256),
-        );
-    }
-    outputs.insert(
-        "crates/cuda-device/src/generated/f32x2.rs".into(),
-        render_compat_packed_alu(catalog, catalog_sha256, PackedAluFormat::F32x2),
-    );
-    outputs.insert(
-        "crates/cuda-device/src/generated/convert.rs".into(),
-        render_compat_packed_conversion(
-            catalog,
-            catalog_sha256,
-            "cuda_device::convert::",
-            "convert",
-            ("lo", "hi"),
-        ),
-    );
-    if let Some((path, source)) = render_compat_float_output(catalog, catalog_sha256) {
-        outputs.insert(path, source);
-    }
-    if extended_minmax(catalog).next().is_some() {
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/extended_minmax.rs".into(),
-            render_dialect_extended_minmax(catalog, catalog_sha256),
-        );
-    }
-    if debug_controls(catalog).next().is_some() {
-        outputs.insert(
-            "crates/cuda-device/src/generated/debug_control.rs".into(),
-            render_compat_debug_control(catalog, catalog_sha256),
-        );
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/debug_control.rs".into(),
-            render_dialect_debug_control(catalog, catalog_sha256),
-        );
-    }
-    if clc_intrinsics(catalog).next().is_some() {
-        outputs.insert(
-            "crates/cuda-device/src/generated/clc.rs".into(),
-            render_compat_clc(catalog, catalog_sha256),
-        );
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/clc.rs".into(),
-            render_dialect_clc(catalog, catalog_sha256),
-        );
-    }
-    if tma_intrinsics(catalog).next().is_some() {
-        outputs.insert(
-            "crates/cuda-device/src/generated/tma.rs".into(),
-            render_compat_tma(catalog, catalog_sha256),
-        );
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/tma.rs".into(),
-            render_dialect_tma(catalog, catalog_sha256),
-        );
-    }
-    if execution_controls(catalog).next().is_some() {
-        outputs.insert(
-            "crates/cuda-device/src/generated/counted_barrier.rs".into(),
-            render_compat_counted_barrier(catalog, catalog_sha256),
-        );
-        outputs.insert(
-            "crates/cuda-device/src/generated/grid_dependency.rs".into(),
-            render_compat_grid_dependency(catalog, catalog_sha256),
-        );
-        outputs.insert(
-            "crates/cuda-device/src/generated/register_control.rs".into(),
-            render_compat_register_control(catalog, catalog_sha256),
-        );
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/execution_control.rs".into(),
-            render_dialect_execution_control(catalog, catalog_sha256),
-        );
-    }
-    if tcgen05_intrinsics(catalog).next().is_some() {
-        outputs.insert(
-            "crates/cuda-device/src/generated/tcgen05.rs".into(),
-            render_compat_tcgen05(catalog, catalog_sha256),
-        );
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/tcgen05.rs".into(),
-            render_dialect_tcgen05(catalog, catalog_sha256),
-        );
-    }
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/mod.rs".into(),
-        render_dialect_mod(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/sreg.rs".into(),
-        render_dialect_sreg(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/dotprod.rs".into(),
-        render_dialect_dotprod(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/ldmatrix.rs".into(),
-        render_dialect_ldmatrix(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/register_mma.rs".into(),
-        render_dialect_register_mma(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/sparse_mma.rs".into(),
-        render_dialect_sparse_mma(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/packed_atomic.rs".into(),
-        render_dialect_packed_atomic(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/packed_alu.rs".into(),
-        render_dialect_packed_alu(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/packed_conversion.rs".into(),
-        render_dialect_packed_conversion(catalog, catalog_sha256),
-    );
-    if scalar_conversions(catalog).next().is_some() {
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs".into(),
-            render_dialect_scalar_conversion(catalog, catalog_sha256),
-        );
-    }
-    if scalar_arithmetics(catalog).next().is_some() {
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs".into(),
-            render_dialect_scalar_arithmetic(catalog, catalog_sha256),
-        );
-    }
-    if scalar_maths(catalog).next().is_some() {
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/scalar_math.rs".into(),
-            render_dialect_scalar_math(catalog, catalog_sha256),
-        );
-    }
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/prmt.rs".into(),
-        render_dialect_prmt(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs".into(),
-        render_dialect_cluster_barrier(catalog, catalog_sha256),
-    );
-    if cluster_memory(catalog).next().is_some() {
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/cluster_memory.rs".into(),
-            render_dialect_cluster_memory(catalog, catalog_sha256),
-        );
-    }
-    if stmatrices(catalog).next().is_some() {
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/stmatrix.rs".into(),
-            render_dialect_stmatrix(catalog, catalog_sha256),
-        );
-    }
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/redux.rs".into(),
-        render_dialect_redux(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/sync.rs".into(),
-        render_dialect_sync(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/vote.rs".into(),
-        render_dialect_vote(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/active_mask.rs".into(),
-        render_dialect_active_mask(catalog, catalog_sha256),
-    );
-    if elect_intrinsics(catalog).next().is_some() {
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/elect.rs".into(),
-            render_dialect_elect(catalog, catalog_sha256),
-        );
-    }
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/cp_async.rs".into(),
-        render_dialect_cp_async_copy(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs".into(),
-        render_dialect_mbarrier_basic(catalog, catalog_sha256),
-    );
-    if movmatrix(catalog).next().is_some() {
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/movmatrix.rs".into(),
-            render_dialect_movmatrix(catalog, catalog_sha256),
-        );
-    }
-    if mbarrier_extended(catalog).next().is_some() {
-        outputs.insert(
-            "crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs".into(),
-            render_dialect_mbarrier_extended(catalog, catalog_sha256),
-        );
-    }
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/warp_match.rs".into(),
-        render_dialect_warp_match(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/warp_barrier.rs".into(),
-        render_dialect_warp_barrier(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs".into(),
-        render_dialect_warp_shuffle(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/mir-importer/src/translator/terminator/intrinsics/generated.rs".into(),
-        render_importer(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/mir-lower/src/convert/generated_intrinsics.rs".into(),
-        render_lowering(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/rustc-codegen-cuda/src/generated_intrinsics.rs".into(),
-        render_collector(catalog, catalog_sha256),
-    );
-    outputs.insert(
-        "crates/cuda-oxide-codegen/src/generated_intrinsic_targets.rs".into(),
-        render_targets(catalog, catalog_sha256),
-    );
-    for record in &catalog.intrinsics {
-        if record.special_register.is_some() || record.family == "elect" {
-            for backend in [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm] {
-                outputs.insert(
-                    format!(
-                        "intrinsics/probes/{}.{}.ll",
-                        record.id,
-                        backend_label(backend)
-                    )
-                    .into(),
-                    if record.family == "elect" {
-                        render_elect_probe(catalog, record, catalog_sha256, backend)
-                    } else {
-                        render_special_register_probe(catalog, record, catalog_sha256, backend)
-                    },
-                );
-            }
-        } else {
-            outputs.insert(
-                format!("intrinsics/probes/{}.ll", record.id).into(),
-                render_probe(catalog, record, catalog_sha256),
-            );
-        }
-    }
-    outputs.insert(
-        "intrinsics/generated-reference.md".into(),
-        render_reference(catalog, catalog_sha256),
-    );
-    Ok(outputs)
-}
-
-fn validate_renderable(catalog: &CatalogFile) -> Result<()> {
-    ensure!(
-        !catalog.intrinsics.is_empty(),
-        "catalog contains no intrinsics"
-    );
-    for record in &catalog.intrinsics {
-        match record.family.as_str() {
-            "sreg" => {
-                if let Some(special) = &record.special_register {
-                    ensure!(
-                        matches!(record.rust.module.as_str(), "debug" | "grid" | "thread" | "warp" | "shared")
-                            && record.rust.arguments.is_empty()
-                            && record.dialect.operands.is_empty()
-                            && record.dialect.results
-                                == [format!("i{}", special.result_width.bits())]
-                            && record.scalar_width() == Some(special.result_width.bits())
-                            && record.lowering == "generated_special_register"
-                            && record.backend_lowerings.len() == 2
-                            && record.semantics.pure
-                                == (special.observation
-                                    == SpecialRegisterObservation::StablePure),
-                        "{} is outside the closed generated special-register recipe",
-                        record.id
-                    );
-                } else {
-                    ensure!(
-                        record.rust.module == "sreg"
-                            && record.rust.arguments.is_empty()
-                            && llvm(record).arguments.is_empty()
-                            && record.lowering == "direct_nvvm"
-                            && record.scalar_width().is_some(),
-                        "{} is outside the zero-operand scalar direct-NVVM sreg recipe",
-                        record.id
-                    );
-                }
-            }
-            "ldmatrix" => ensure!(
-                record.rust.module == "matrix"
-                    && record.lowering == "generated_ldmatrix"
-                    && record.ldmatrix.as_ref().is_some_and(|ldmatrix| {
-                        record.rust.arguments
-                            == [if ldmatrix.variant.element == LdmatrixElement::B16 {
-                                "*const u32"
-                            } else {
-                                "*const u8"
-                            }]
-                    }),
-                "{} is outside the generated ldmatrix recipe",
-                record.id
-            ),
-            "stmatrix" => ensure!(
-                stmatrix_variant(record).is_some()
-                    && record.rust.module == "matrix"
-                    && !record.rust.safe
-                    && !record.rust.must_use
-                    && record.rust.result == "()"
-                    && record.dialect.results.is_empty()
-                    && record.llvm.as_ref().is_some_and(|llvm| llvm.results.is_empty())
-                    && record.semantics.memory == "write"
-                    && record.semantics.convergent
-                    && record.lowering == "generated_stmatrix",
-                "{} is outside the closed generated stmatrix recipe",
-                record.id
-            ),
-            "register_mma" => ensure!(
-                record.rust.module == "matrix"
-                    && record.rust.arguments.len() == 3 + register_mma_extra_operand_count(record)
-                    && !record.rust.safe
-                    && record.rust.must_use
-                    && record.semantics.memory == "none"
-                    && record.semantics.convergent
-                    && record.dialect.op_type == "RegisterMmaOp"
-                    && record.dialect.op_name == "nvvm.register_mma"
-                    && record.lowering == "generated_register_mma"
-                    && record.register_mma.is_some(),
-                "{} is outside the closed generated register-MMA recipe",
-                record.id
-            ),
-            "movmatrix" => ensure!(
-                record.rust.module == "matrix"
-                    && record.rust.arguments == ["u32"]
-                    && record.rust.result == "u32"
-                    && !record.rust.safe
-                    && record.rust.must_use
-                    && record.dialect.op_type == "MovmatrixTransB16Op"
-                    && record.dialect.op_name == "nvvm.movmatrix_trans_b16"
-                    && record.dialect.operands == ["i32"]
-                    && record.dialect.results == ["i32"]
-                    && !record.semantics.pure
-                    && record.semantics.memory == "inaccessible_read_write"
-                    && record.semantics.convergent
-                    && record.lowering == "generated_movmatrix_inline_ptx"
-                    && record.movmatrix.is_some(),
-                "{} is outside the generated movmatrix recipe",
-                record.id
-            ),
-            "sparse_mma" => {
-                ensure!(
-                    record.sparse_mma.is_some(),
-                    "{} is outside the closed generated sparse-MMA recipe",
-                    record.id
-                );
-                let (c_count, a_count, b_count, d_count) =
-                    sparse_mma_fragment_counts(record);
-                let accumulator = match record.sparse_mma.as_ref().unwrap().accumulator {
-                    SparseMmaAccumulator::F16 => "u32",
-                    SparseMmaAccumulator::F32 => "f32",
-                    SparseMmaAccumulator::S32 => "i32",
-                };
-                let arguments = [
-                    format!("[{accumulator}; {c_count}]"),
-                    format!("[u32; {a_count}]"),
-                    format!("[u32; {b_count}]"),
-                    "u32".to_owned(),
-                    "u32".to_owned(),
-                ];
-                ensure!(
-                    record.rust.module == "matrix"
-                        && record.rust.arguments == arguments
-                        && record.rust.result == format!("[{accumulator}; {d_count}]")
-                        && !record.rust.safe
-                        && record.rust.must_use
-                        && record.semantics.memory == "none"
-                        && record.semantics.convergent
-                        && record.dialect.op_type == "SparseMmaOp"
-                        && record.dialect.op_name == "nvvm.sparse_mma"
-                        && record.lowering == "generated_sparse_mma"
-                        && record.sparse_mma.is_some(),
-                    "{} is outside the closed generated sparse-MMA recipe",
-                    record.id
-                )
-            }
-            "packed_atomic" => ensure!(
-                record.rust.module == "atomic"
-                    && record.rust.arguments == ["*mut u32", "u32"]
-                    && record.rust.result == "u32"
-                    && record.rust.must_use
-                    && record.llvm.is_none()
-                    && record.lowering == "generated_packed_atomic_inline_ptx"
-                    && record.packed_atomic.is_some(),
-                "{} is outside the closed generated packed-atomic recipe",
-                record.id
-            ),
-            "redux" => ensure!(
-                record.rust.module == "warp"
-                    && matches!(record.rust.arguments.as_slice(), [mask, value]
-                        if mask == "u32" && value == &record.rust.result)
-                    && matches!(record.rust.result.as_str(), "u32" | "i32" | "f32")
-                    && !record.rust.safe
-                    && matches!(record.dialect.results.as_slice(), [result]
-                        if matches!(result.as_str(), "i32" | "f32"))
-                    && matches!(record.dialect.results.as_slice(), [result]
-                        if record.llvm.as_ref().is_some_and(|llvm| {
-                            llvm.arguments == [result.as_str(), "i32"]
-                                && llvm.results == [result.as_str()]
-                        }) && record.dialect.operands == ["i32", result.as_str()])
-                    && record.lowering == "generated_redux"
-                    && record.redux.is_some(),
-                "{} is outside the closed generated redux recipe",
-                record.id
-            ),
-            "dotprod" => ensure!(
-                record.rust.module == "dotprod"
-                    && matches!(record.rust.arguments.as_slice(), [a, b, c]
-                        if a == "u32" && b == "u32" && matches!(c.as_str(), "u32" | "i32"))
-                    && record.rust.result == *record.rust.arguments.last().unwrap()
-                    && record.rust.safe
-                    && !record.rust.must_use
-                    && record.llvm.as_ref().is_some_and(|llvm| {
-                        llvm.results == ["i32"]
-                            && (matches!(llvm.arguments.as_slice(), [a, b, c]
-                                if a == "i32" && b == "i32" && c == "i32")
-                                || matches!(llvm.arguments.as_slice(), [a, b, selector, c]
-                                    if a == "i32" && b == "i32" && selector == "i1" && c == "i32"))
-                    })
-                    && record.dialect.operands == ["i32", "i32", "i32"]
-                    && record.dialect.results == ["i32"]
-                    && record.lowering == "generated_dotprod"
-                    && record.dot_product.is_some(),
-                "{} is outside the closed generated dot-product recipe",
-                record.id
-            ),
-            "packed_alu" => ensure!(
-                record.packed_alu.as_ref().is_some_and(|packed| {
-                    let (module, must_use, rust_type, dialect_type, adapter) =
-                        packed_alu_format_shape(packed.format);
-                    record.rust.module == module
-                        && record.rust.must_use == must_use
-                        && packed.adapter == adapter
-                        && record
-                            .rust
-                            .arguments
-                            .iter()
-                            .all(|argument| argument == rust_type)
-                        && record.rust.result == rust_type
-                        && record
-                            .dialect
-                            .operands
-                            .iter()
-                            .all(|operand| operand == dialect_type)
-                        && record.dialect.results == [dialect_type]
-                })
-                    && (1..=3).contains(&record.rust.arguments.len())
-                    && record.rust.safe
-                    && record.dialect.operands.len() == record.rust.arguments.len()
-                    && record.lowering == "generated_packed_alu_inline_ptx",
-                "{} is outside the closed generated packed-ALU recipe",
-                record.id
-            ),
-            "packed_conversion" => ensure!(
-                record.rust.module == "convert"
-                    && record.rust.arguments == packed_conversion_rust_arguments(record)
-                    && record.rust.result == packed_conversion_rust_type(record)
-                    && record.rust.safe
-                    && !record.rust.must_use
-                    && record.dialect.operands == packed_conversion_dialect_operands(record)
-                    && record.dialect.results == [packed_conversion_dialect_type(record)]
-                    && record.lowering == packed_conversion_lowering_name(record)
-                    && record
-                        .packed_conversion
-                        .as_ref()
-                        .is_some_and(packed_conversion_is_closed_recipe),
-                "{} is outside the closed generated packed-conversion recipe",
-                record.id
-            ),
-            "scalar_conversion" => ensure!(
-                record.rust.module == "convert"
-                    && record.rust.arguments == ["f32"]
-                    && record.rust.result == "u32"
-                    && record.rust.safe
-                    && record.rust.must_use
-                    && record.dialect.op_type == "ScalarConversionOp"
-                    && record.dialect.op_name == "nvvm.scalar_conversion"
-                    && record.dialect.operands == ["f32"]
-                    && record.dialect.results == ["i32"]
-                    && record.lowering == "generated_scalar_conversion"
-                    && record.scalar_conversion.is_some(),
-                "{} is outside the closed generated scalar-conversion recipe",
-                record.id
-            ),
-            "scalar_arithmetic" => ensure!(
-                record.scalar_arithmetic.as_ref().is_some_and(|arithmetic| {
-                    let ty = match arithmetic.format {
-                        ScalarArithmeticFormat::F32 => "f32",
-                        ScalarArithmeticFormat::F64 => "f64",
-                    };
-                    let arity = match arithmetic.operation {
-                        ScalarArithmeticOperation::Mul
-                        | ScalarArithmeticOperation::Div
-                        | ScalarArithmeticOperation::Add => 2,
-                        ScalarArithmeticOperation::Fma => 3,
-                    };
-                    record.rust.arguments == vec![ty; arity]
-                        && record.rust.result == ty
-                        && record.dialect.operands == vec![ty; arity]
-                        && record.dialect.results == [ty]
-                        && record.semantics.pure
-                            == (arithmetic.operation != ScalarArithmeticOperation::Div)
-                })
-                    && record.rust.module == "float"
-                    && record.rust.safe
-                    && record.rust.must_use
-                    && record.dialect.op_type == "ScalarArithmeticOp"
-                    && record.dialect.op_name == "nvvm.scalar_arithmetic"
-                    && record.semantics.memory == "none"
-                    && !record.semantics.convergent
-                    && record.lowering == "generated_scalar_arithmetic",
-                "{} is outside the closed generated scalar-arithmetic recipe",
-                record.id
-            ),
-            "scalar_math" => ensure!(
-                record.scalar_math.as_ref().is_some_and(|math| {
-                    let (rust_ty, dialect_ty) = match math.format {
-                        ScalarMathFormat::F16 => ("u16", "i16"),
-                        ScalarMathFormat::F32 => ("f32", "f32"),
-                        ScalarMathFormat::F64 => ("f64", "f64"),
-                    };
-                    record.rust.arguments == [rust_ty]
-                        && record.rust.result == rust_ty
-                        && record.dialect.operands == [dialect_ty]
-                        && record.dialect.results == [dialect_ty]
-                        && record.semantics.pure
-                })
-                    && record.rust.module == "float"
-                    && record.rust.safe
-                    && record.rust.must_use
-                    && record.dialect.op_type == "ScalarMathOp"
-                    && record.dialect.op_name == "nvvm.scalar_math"
-                    && record.semantics.memory == "none"
-                    && !record.semantics.convergent
-                    && record.lowering == "generated_scalar_math",
-                "{} is outside the closed generated scalar-math recipe",
-                record.id
-            ),
-            "extended_minmax" => ensure!(
-                record.extended_minmax.as_ref().is_some_and(|minmax| {
-                    let (module, rust_type, dialect_type, adapter) = match minmax.format {
-                        ExtendedMinMaxFormat::F32 => (
-                            "float",
-                            "f32",
-                            "f32",
-                            ExtendedMinMaxAdapter::DirectF32,
-                        ),
-                        ExtendedMinMaxFormat::F16 => (
-                            "f16",
-                            "u16",
-                            "i16",
-                            ExtendedMinMaxAdapter::DirectHalfU16,
-                        ),
-                        ExtendedMinMaxFormat::Bf16 => (
-                            "bf16",
-                            "u16",
-                            "i16",
-                            ExtendedMinMaxAdapter::DirectHalfU16,
-                        ),
-                        ExtendedMinMaxFormat::F16x2 => (
-                            "f16x2",
-                            "u32",
-                            "i32",
-                            ExtendedMinMaxAdapter::DirectPackedU32,
-                        ),
-                        ExtendedMinMaxFormat::Bf16x2 => (
-                            "bf16x2",
-                            "u32",
-                            "i32",
-                            ExtendedMinMaxAdapter::DirectPackedU32,
-                        ),
-                    };
-                    record.rust.module == module
-                        && record.rust.arguments == [rust_type, rust_type]
-                        && record.rust.result == rust_type
-                        && record.dialect.operands == [dialect_type, dialect_type]
-                        && record.dialect.results == [dialect_type]
-                        && minmax.adapter == adapter
-                })
-                    && record.rust.safe
-                    && record.rust.must_use
-                    && record.dialect.op_type == "ExtendedMinMaxOp"
-                    && record.dialect.op_name == "nvvm.extended_minmax"
-                    && record.semantics.pure
-                    && record.semantics.memory == "none"
-                    && !record.semantics.convergent
-                    && record.lowering == "generated_extended_minmax",
-                "{} is outside the closed generated extended-minmax recipe",
-                record.id
-            ),
-            "prmt" => ensure!(
-                record.rust.module == "prmt"
-                    && matches!(record.rust.arguments.len(), 2 | 3)
-                    && record.rust.arguments.iter().all(|argument| argument == "u32")
-                    && record.rust.result == "u32"
-                    && record.rust.safe
-                    && record.rust.must_use
-                    && record.dialect.op_type == "PrmtOp"
-                    && record.dialect.op_name == "nvvm.prmt"
-                    && record.dialect.operands.len() == record.rust.arguments.len()
-                    && record.dialect.operands.iter().all(|operand| operand == "i32")
-                    && record.dialect.results == ["i32"]
-                    && record.lowering == "generated_prmt"
-                    && record.prmt.is_some(),
-                "{} is outside the closed generated prmt recipe",
-                record.id
-            ),
-            "cluster_barrier" => ensure!(
-                matches!(
-                    record.id.as_str(),
-                    "barrier_cluster_arrive"
-                        | "barrier_cluster_arrive_aligned"
-                        | "barrier_cluster_arrive_relaxed"
-                        | "barrier_cluster_arrive_relaxed_aligned"
-                        | "barrier_cluster_wait"
-                        | "barrier_cluster_wait_aligned"
-                )
-                    && record.rust.module == "cluster"
-                    && record.rust.arguments.is_empty()
-                    && record.rust.result == "()"
-                    && !record.rust.safe
-                    && !record.rust.must_use
-                    && record.dialect.op_type == "ClusterBarrierOp"
-                    && record.dialect.op_name == "nvvm.cluster_barrier"
-                    && record.dialect.operands.is_empty()
-                    && record.dialect.results.is_empty()
-                    && record.llvm.as_ref().is_some_and(|llvm| {
-                        llvm.arguments.is_empty() && llvm.results.is_empty()
-                    })
-                    && record.cluster_barrier.as_ref().is_some_and(|barrier| {
-                        matches!(
-                            (barrier.mode, barrier.ordering, barrier.aligned),
-                            (
-                                ClusterBarrierMode::Arrive,
-                                ClusterBarrierOrdering::Release,
-                                false
-                            ) | (
-                                ClusterBarrierMode::ArriveAligned,
-                                ClusterBarrierOrdering::Release,
-                                true
-                            ) | (
-                                ClusterBarrierMode::ArriveRelaxed,
-                                ClusterBarrierOrdering::Relaxed,
-                                false
-                            ) | (
-                                ClusterBarrierMode::ArriveRelaxedAligned,
-                                ClusterBarrierOrdering::Relaxed,
-                                true
-                            ) | (
-                                ClusterBarrierMode::Wait,
-                                ClusterBarrierOrdering::Acquire,
-                                false
-                            ) | (
-                                ClusterBarrierMode::WaitAligned,
-                                ClusterBarrierOrdering::Acquire,
-                                true
-                            )
-                        )
-                    })
-                    && record.lowering == "generated_cluster_barrier",
-                "{} is outside the closed generated cluster-barrier recipe",
-                record.id
-            ),
-            "cluster_memory" => ensure!(
-                record.rust.module == "cluster"
-                    && !record.rust.safe
-                    && record.rust.must_use
-                    && record.semantics.convergent
-                    && record.semantics.execution_scope == "cluster"
-                    && record.target.minimum_ptx.to_string() == "7.8"
-                    && matches!(
-                        &record.target.hardware,
-                        CatalogHardwareTarget::AnyOf { alternatives }
-                            if alternatives.as_slice()
-                                == [CatalogHardwareAlternative::MinimumSm { sm: 90 }]
-                    )
-                    && record.lowering == "generated_cluster_memory_inline_ptx"
-                    && record.backend_lowerings.len() == 2
-                    && record.backend_lowerings.iter().all(|lowering| {
-                        lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                            && lowering.target.minimum_ptx.to_string() == "7.8"
-                            && matches!(
-                                &lowering.target.hardware,
-                                CatalogHardwareTarget::AnyOf { alternatives }
-                                    if alternatives.as_slice()
-                                        == [CatalogHardwareAlternative::MinimumSm { sm: 90 }]
-                            )
-                    })
-                    && record.cluster_memory.as_ref().is_some_and(|cluster| {
-                        cluster.runtime_validation == RuntimeValidation::Unexecuted
-                            && match (cluster.operation, cluster.adapter, cluster.source_contract) {
-                                (
-                                    ClusterMemoryOperation::MapSharedRank,
-                                    ClusterMemoryAdapter::GenericConstAndMutPointerRankToSamePointer,
-                                    ClusterMemorySourceContract::LlvmMapaSharedClusterAs7IdentityInlinePtx,
-                                ) => {
-                                    record.id == "map_shared_rank"
-                                        && record.rust.arguments == ["*const u8", "u32"]
-                                        && record.rust.result == "*const u8"
-                                        && record.rust.compatibility_paths
-                                            == [
-                                                "cuda_device::cluster::map_shared_rank",
-                                                "cuda_device::cluster::map_shared_rank_mut",
-                                            ]
-                                        && record.dialect.op_type == "MapaSharedClusterOp"
-                                        && record.dialect.op_name == "nvvm.mapa_shared_cluster"
-                                        && record.dialect.operands == ["ptr", "i32"]
-                                        && record.dialect.results == ["ptr"]
-                                        && record.semantics.memory == "none"
-                                        && matches!(
-                                            record.source,
-                                            IntrinsicSource::LlvmImported { ref source_record }
-                                                if source_record == "int_nvvm_mapa_shared_cluster"
-                                        )
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.symbol == "llvm.nvvm.mapa.shared.cluster"
-                                                && llvm.arguments == ["shared_ptr", "i32"]
-                                                && llvm.results == ["shared_cluster_ptr"]
-                                                && llvm.properties
-                                                    == [
-                                                        "IntrNoMem",
-                                                        "IntrSpeculatable",
-                                                        "NoCapture<arg0>",
-                                                    ]
-                                        })
-                                        && record
-                                            .selections
-                                            .iter()
-                                            .map(|selection| selection.source_record.as_str())
-                                            .collect::<BTreeSet<_>>()
-                                            == BTreeSet::from([
-                                                "mapa_shared_cluster_64",
-                                                "mapa_shared_cluster_64i",
-                                            ])
-                                }
-                                (
-                                    ClusterMemoryOperation::ReadU32,
-                                    ClusterMemoryAdapter::ConstU32PointerRankToU32,
-                                    ClusterMemorySourceContract::PtxNativeMapaThenWeakClusterLoad,
-                                ) => {
-                                    record.id == "dsmem_read_u32"
-                                        && record.rust.arguments == ["*const u32", "u32"]
-                                        && record.rust.result == "u32"
-                                        && record.rust.compatibility_paths
-                                            == ["cuda_device::cluster::dsmem_read_u32"]
-                                        && record.dialect.op_type == "DsmemReadU32Op"
-                                        && record.dialect.op_name == "nvvm.dsmem_read_u32"
-                                        && record.dialect.operands == ["ptr", "i32"]
-                                        && record.dialect.results == ["i32"]
-                                        && record.semantics.memory == "read"
-                                        && record.llvm.is_none()
-                                        && record.selections.is_empty()
-                                        && matches!(
-                                            record.source,
-                                            IntrinsicSource::PtxNative { ref instruction }
-                                                if instruction
-                                                    == "mapa.shared::cluster.u64 + ld.shared::cluster.u32"
-                                        )
-                                }
-                                _ => false,
-                            }
-                    }),
-                "{} is outside the closed generated cluster-memory recipe",
-                record.id
-            ),
-            "debug_control" => ensure!(
-                record.rust.module == "debug"
-                    && record.rust.safe
-                    && !record.rust.must_use
-                    && record.dialect.operands.is_empty()
-                    && record.dialect.results.is_empty()
-                    && record.llvm.is_none()
-                    && record.lowering == "generated_debug_control"
-                    && record.debug_control.as_ref().is_some_and(|debug| {
-                        debug.runtime_validation == RuntimeValidation::Unexecuted
-                            && match debug.operation {
-                                DebugControlOperation::Trap => {
-                                    debug.adapter == DebugControlAdapter::Direct
-                                        && record.rust.arguments.is_empty()
-                                        && record.rust.result == "!"
-                                        && record.dialect.op_type == "TrapOp"
-                                        && record.dialect.op_name == "nvvm.trap"
-                                }
-                                DebugControlOperation::Breakpoint => {
-                                    debug.adapter == DebugControlAdapter::Direct
-                                        && record.rust.arguments.is_empty()
-                                        && record.rust.result == "()"
-                                        && record.dialect.op_type == "BreakpointOp"
-                                        && record.dialect.op_name == "nvvm.brkpt"
-                                }
-                                DebugControlOperation::Pmevent => {
-                                    debug.adapter
-                                        == DebugControlAdapter::ConstGenericToImmediateU32
-                                        && record.rust.arguments == ["u32"]
-                                        && record.rust.result == "()"
-                                        && record.dialect.op_type == "PmEventOp"
-                                        && record.dialect.op_name == "nvvm.pmevent"
-                                }
-                            }
-                    }),
-                "{} is outside the closed generated debug-control recipe",
-                record.id
-            ),
-            "clc" => ensure!(
-                record.rust.module == "clc"
-                    && !record.rust.safe
-                    && !record.rust.must_use
-                    && record.lowering == "generated_clc"
-                    && record.llvm.is_some()
-                    && record.clc.as_ref().is_some_and(|clc| {
-                        clc.runtime_validation == RuntimeValidation::Unexecuted
-                            && match (clc.operation, clc.adapter) {
-                                (
-                                    ClcOperation::TryCancel
-                                    | ClcOperation::TryCancelMulticast,
-                                    ClcAdapter::GenericPointersToShared,
-                                ) => {
-                                    record.rust.arguments == ["*mut u8", "*mut u64"]
-                                        && record.rust.result == "()"
-                                        && record.dialect.operands == ["ptr", "ptr"]
-                                        && record.dialect.results.is_empty()
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.arguments == ["shared_ptr", "shared_ptr"]
-                                                && llvm.results.is_empty()
-                                        })
-                                }
-                                (
-                                    ClcOperation::QueryIsCanceled,
-                                    ClcAdapter::PairU64ToI128BoolToU32,
-                                ) => {
-                                    record.rust.arguments == ["u64", "u64"]
-                                        && record.rust.result == "u32"
-                                        && record.dialect.operands == ["i64", "i64"]
-                                        && record.dialect.results == ["i32"]
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.arguments == ["i128"]
-                                                && llvm.results == ["i1"]
-                                        })
-                                }
-                                (
-                                    ClcOperation::QueryGetFirstCtaidX
-                                    | ClcOperation::QueryGetFirstCtaidY
-                                    | ClcOperation::QueryGetFirstCtaidZ,
-                                    ClcAdapter::PairU64ToI128U32,
-                                ) => {
-                                    record.rust.arguments == ["u64", "u64"]
-                                        && record.rust.result == "u32"
-                                        && record.dialect.operands == ["i64", "i64"]
-                                        && record.dialect.results == ["i32"]
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.arguments == ["i128"]
-                                                && llvm.results == ["i32"]
-                                        })
-                                }
-                                _ => false,
-                            }
-                    }),
-                "{} is outside the closed generated CLC recipe",
-                record.id
-            ),
-            "wgmma_control" => ensure!(
-                record.rust.module == "wgmma"
-                    && record.rust.result == "()"
-                    && !record.rust.safe
-                    && !record.rust.must_use
-                    && record.dialect.results.is_empty()
-                    && record.llvm.as_ref().is_some_and(|llvm| llvm.results.is_empty())
-                    && !record.semantics.pure
-                    && record.semantics.memory == "read_write"
-                    && record.semantics.convergent
-                    && record.semantics.execution_scope == "warpgroup"
-                    && record.target.minimum_ptx.encoded() == 80
-                    && record.target.hardware
-                        == CatalogHardwareTarget::AnyOf {
-                            alternatives: vec![CatalogHardwareAlternative::ExactArchitecture {
-                                sm: 90,
-                            }],
-                        }
-                    && record.backend_lowerings.len() == 2
-                    && record.backend_lowerings.iter().any(|lowering| {
-                        lowering.backend == IntrinsicBackend::LlvmNvptx
-                            && lowering.mechanism == BackendLoweringMechanism::TypedNvvm
-                    })
-                    && record.backend_lowerings.iter().any(|lowering| {
-                        lowering.backend == IntrinsicBackend::LibNvvm
-                            && lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    })
-                    && record.lowering == "generated_wgmma_control"
-                    && record.wgmma_control.as_ref().is_some_and(|control| {
-                        control.participation
-                            == WgmmaControlParticipation::WarpgroupAllThreadsSameInstruction
-                            && match control.mode {
-                                WgmmaControlMode::Fence => {
-                                    control.adapter == WgmmaControlAdapter::NoArguments
-                                        && record.id == "wgmma_fence"
-                                        && record.rust.arguments.is_empty()
-                                        && record.dialect.op_type == "WgmmaFenceSyncAlignedOp"
-                                        && record.dialect.op_name
-                                            == "nvvm.wgmma_fence_sync_aligned"
-                                        && record.dialect.operands.is_empty()
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.arguments.is_empty()
-                                        })
-                                }
-                                WgmmaControlMode::CommitGroup => {
-                                    control.adapter == WgmmaControlAdapter::NoArguments
-                                        && record.id == "wgmma_commit_group"
-                                        && record.rust.arguments.is_empty()
-                                        && record.dialect.op_type
-                                            == "WgmmaCommitGroupSyncAlignedOp"
-                                        && record.dialect.op_name
-                                            == "nvvm.wgmma_commit_group_sync_aligned"
-                                        && record.dialect.operands.is_empty()
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.arguments.is_empty()
-                                        })
-                                }
-                                WgmmaControlMode::WaitGroup => {
-                                    control.adapter
-                                        == WgmmaControlAdapter::ConstGenericU32ToI64Immediate
-                                        && record.id == "wgmma_wait_group"
-                                        && record.rust.arguments == ["u64"]
-                                        && record.rust.compatibility_paths
-                                            == ["cuda_device::wgmma::__wgmma_wait_group"]
-                                        && record.dialect.op_type
-                                            == "WgmmaWaitGroupSyncAlignedOp"
-                                        && record.dialect.op_name
-                                            == "nvvm.wgmma_wait_group_sync_aligned"
-                                        && record.dialect.operands == ["i64"]
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.arguments == ["i64"]
-                                        })
-                                }
-                            }
-                    }),
-                "{} is outside the closed generated WGMMA-control recipe",
-                record.id
-            ),
-            "tma" => ensure!(
-                record.rust.module == "tma"
-                    && record.rust.result == "()"
-                    && !record.rust.must_use
-                    && record.dialect.results.is_empty()
-                    && record.llvm.as_ref().is_some_and(|llvm| llvm.results.is_empty())
-                    && record.lowering == "generated_tma"
-                    && record.tma.as_ref().is_some_and(|tma| {
-                        tma.runtime_validation == RuntimeValidation::Unexecuted
-                            && match (tma.operation, tma.adapter) {
-                                (
-                                    TmaOperation::G2sTile1d
-                                    | TmaOperation::G2sTile2d
-                                    | TmaOperation::G2sTile3d
-                                    | TmaOperation::G2sTile4d
-                                    | TmaOperation::G2sTile5d,
-                                    TmaAdapter::G2sPointersCoordinatesBarrierInjectDefaults,
-                                ) => {
-                                    !record.rust.safe
-                                        && record.semantics.convergent
-                                        && record.semantics.memory == "read_write"
-                                }
-                                (
-                                    TmaOperation::G2sTile2dMulticast
-                                    | TmaOperation::G2sTile2dMulticastCg2,
-                                    TmaAdapter::G2sPointersCoordinatesBarrierMaskInjectDefaults,
-                                ) => {
-                                    !record.rust.safe
-                                        && record.semantics.convergent
-                                        && record.semantics.memory == "read_write"
-                                }
-                                (
-                                    TmaOperation::S2gTile1d
-                                    | TmaOperation::S2gTile2d
-                                    | TmaOperation::S2gTile3d
-                                    | TmaOperation::S2gTile4d
-                                    | TmaOperation::S2gTile5d,
-                                    TmaAdapter::S2gPointersCoordinatesInjectDefaults,
-                                ) => {
-                                    !record.rust.safe
-                                        && record.semantics.convergent
-                                        && record.semantics.memory == "read_write"
-                                }
-                                (
-                                    TmaOperation::Reduce,
-                                    TmaAdapter::ReductionPointersCoordinatesInjectDefaults,
-                                ) => {
-                                    !record.rust.safe
-                                        && record.semantics.convergent
-                                        && record.semantics.memory == "read_write"
-                                        && tma.reduction.is_some()
-                                }
-                                (TmaOperation::CommitGroup, TmaAdapter::NoOperands) => {
-                                    record.rust.safe
-                                        && !record.semantics.convergent
-                                        && record.semantics.memory == "read_write"
-                                }
-                                (
-                                    TmaOperation::WaitGroup | TmaOperation::WaitGroupRead,
-                                    TmaAdapter::CompileTimeConstantMaxPending,
-                                ) => {
-                                    record.rust.safe
-                                        && !record.semantics.convergent
-                                        && record.semantics.memory == "read_write"
-                                }
-                                (
-                                    TmaOperation::PrefetchTensorMap,
-                                    TmaAdapter::DescriptorPointer,
-                                ) => {
-                                    !record.rust.safe
-                                        && !record.semantics.convergent
-                                        && record.semantics.memory == "read"
-                                }
-                                (
-                                    TmaOperation::PrefetchTile1d
-                                    | TmaOperation::PrefetchTile2d
-                                    | TmaOperation::PrefetchTile3d
-                                    | TmaOperation::PrefetchTile4d
-                                    | TmaOperation::PrefetchTile5d
-                                    | TmaOperation::PrefetchTileGather4TwoDimensional,
-                                    TmaAdapter::DescriptorCoordinatesInjectDefaults,
-                                ) => {
-                                    !record.rust.safe
-                                        && record.semantics.convergent
-                                        && record.semantics.memory == "read"
-                                }
-                                (
-                                    TmaOperation::PrefetchTile1dCacheHint
-                                    | TmaOperation::PrefetchTile2dCacheHint
-                                    | TmaOperation::PrefetchTile3dCacheHint
-                                    | TmaOperation::PrefetchTile4dCacheHint
-                                    | TmaOperation::PrefetchTile5dCacheHint
-                                    | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint,
-                                    TmaAdapter::DescriptorCoordinatesCacheHintInjectFlag,
-                                ) => {
-                                    !record.rust.safe
-                                        && record.semantics.convergent
-                                        && record.semantics.memory == "read"
-                                }
-                                (
-                                    TmaOperation::ReplaceGlobalAddress,
-                                    TmaAdapter::DescriptorAndAddressPointers,
-                                )
-                                | (
-                                    TmaOperation::ReplaceBoxDim
-                                    | TmaOperation::ReplaceElementStride
-                                    | TmaOperation::ReplaceGlobalDim,
-                                    TmaAdapter::DescriptorOrdinalAndU32,
-                                )
-                                | (
-                                    TmaOperation::ReplaceGlobalStride,
-                                    TmaAdapter::DescriptorOrdinalAndU64,
-                                )
-                                | (
-                                    TmaOperation::ReplaceElementType
-                                    | TmaOperation::ReplaceFillMode
-                                    | TmaOperation::ReplaceInterleaveLayout
-                                    | TmaOperation::ReplaceSwizzleAtomicity
-                                    | TmaOperation::ReplaceSwizzleMode,
-                                    TmaAdapter::DescriptorAndImmediateU32,
-                                )
-                                | (
-                                    TmaOperation::ReplaceRank,
-                                    TmaAdapter::DescriptorAndRuntimeU32,
-                                ) => {
-                                    !record.rust.safe
-                                        && !record.semantics.convergent
-                                        && record.semantics.memory == "write"
-                                }
-                                (
-                                    TmaOperation::FenceProxyTensorMapAcquireCluster
-                                    | TmaOperation::FenceProxyTensorMapAcquireCta
-                                    | TmaOperation::FenceProxyTensorMapAcquireGpu
-                                    | TmaOperation::FenceProxyTensorMapAcquireSystem,
-                                    TmaAdapter::DescriptorPointerInjectBytes,
-                                ) => {
-                                    !record.rust.safe
-                                        && !record.semantics.convergent
-                                        && record.semantics.memory == "read_write"
-                                }
-                                (
-                                    TmaOperation::FenceProxyTensorMapReleaseCluster
-                                    | TmaOperation::FenceProxyTensorMapReleaseCta
-                                    | TmaOperation::FenceProxyTensorMapReleaseGpu
-                                    | TmaOperation::FenceProxyTensorMapReleaseSystem,
-                                    TmaAdapter::NoOperands,
-                                ) => {
-                                    record.rust.safe
-                                        && !record.semantics.convergent
-                                        && record.semantics.memory == "read_write"
-                                }
-                                _ => false,
-                            }
-                    }),
-                "{} is outside the closed generated TMA recipe",
-                record.id
-            ),
-            "counted_barrier" | "grid_dependency" | "register_control" => ensure!(
-                ExecutionControlOperation::from_catalog_id(&record.id).is_some_and(|operation| {
-                    record.family == operation.family()
-                        && record.rust.result == "()"
-                        && !record.rust.safe
-                        && !record.rust.must_use
-                        && record.dialect.results.is_empty()
-                        && record
-                            .llvm
-                            .as_ref()
-                            .is_some_and(|llvm| llvm.results.is_empty())
-                        && record.lowering == "generated_execution_control"
-                        && match operation {
-                            ExecutionControlOperation::BarrierCtaSync
-                            | ExecutionControlOperation::BarrierCtaSyncAligned
-                            | ExecutionControlOperation::BarrierCtaArrive
-                            | ExecutionControlOperation::BarrierCtaArriveAligned => {
-                                record.rust.module == "barrier"
-                                    && record.rust.arguments == ["u32", "u32"]
-                                    && record.dialect.operands == ["i32", "i32"]
-                                    && record.llvm.as_ref().is_some_and(|llvm| {
-                                        llvm.arguments == ["i32", "i32"]
-                                    })
-                            }
-                            ExecutionControlOperation::GridDependencyLaunchDependents
-                            | ExecutionControlOperation::GridDependencyWait => {
-                                record.rust.module == "grid"
-                                    && record.rust.arguments.is_empty()
-                                    && record.dialect.operands.is_empty()
-                                    && record
-                                        .llvm
-                                        .as_ref()
-                                        .is_some_and(|llvm| llvm.arguments.is_empty())
-                            }
-                            ExecutionControlOperation::SetMaxNRegInc
-                            | ExecutionControlOperation::SetMaxNRegDec => {
-                                record.rust.module == "thread"
-                                    && record.rust.arguments == ["u32"]
-                                    && record.dialect.operands.is_empty()
-                                    && record
-                                        .llvm
-                                        .as_ref()
-                                        .is_some_and(|llvm| llvm.arguments == ["i32"])
-                            }
-                        }
-                }),
-                "{} is outside the closed generated execution-control recipe",
-                record.id
-            ),
-            "tcgen05" => ensure!(
-                tcgen05_render_contract(record),
-                "{} is outside the closed generated tcgen05 recipe",
-                record.id
-            ),
-            "cp_async_copy" => ensure!(
-                record.rust.module == "async_copy"
-                    && record.rust.result == "()"
-                    && !record.rust.safe
-                    && !record.rust.must_use
-                    && record.llvm.as_ref().is_some_and(|llvm| {
-                        matches!(llvm.arguments.as_slice(), [dst, src]
-                            if dst == "shared_ptr" && src == "global_ptr")
-                            || matches!(llvm.arguments.as_slice(), [dst, src, size]
-                                if dst == "shared_ptr" && src == "global_ptr" && size == "i32")
-                    })
-                    && record.llvm.as_ref().is_some_and(|llvm| llvm.results.is_empty())
-                    && record.dialect.results.is_empty()
-                    && record.lowering == "generated_cp_async_copy"
-                    && record.cp_async_copy.is_some(),
-                "{} is outside the closed generated cp.async copy recipe",
-                record.id
-            ),
-            "cp_async_control" => ensure!(
-                record.rust.module == "async_copy"
-                    && record.rust.result == "()"
-                    && !record.rust.safe
-                    && !record.rust.must_use
-                    && record.llvm.as_ref().is_some_and(|llvm| {
-                        llvm.results.is_empty()
-                            && (llvm.arguments.is_empty() || llvm.arguments == ["i32"])
-                    })
-                    && record.dialect.results.is_empty()
-                    && record.lowering == "generated_cp_async_control"
-                    && record.cp_async_control.is_some(),
-                "{} is outside the closed generated cp.async control recipe",
-                record.id
-            ),
-            "cp_async_mbarrier" => ensure!(
-                record.rust.module == "async_copy"
-                    && record.rust.arguments == ["*mut u64"]
-                    && record.rust.result == "()"
-                    && !record.rust.safe
-                    && !record.rust.must_use
-                    && record.dialect.operands == ["ptr"]
-                    && record.dialect.results.is_empty()
-                    && record.lowering == "generated_cp_async_mbarrier"
-                    && record.cp_async_mbarrier.as_ref().is_some_and(|bridge| {
-                        bridge.adapter == CpAsyncMbarrierAdapter::PointerToVoid
-                            && record.llvm.as_ref().is_some_and(|llvm| {
-                                llvm.results.is_empty()
-                                    && match bridge.state_space {
-                                        CpAsyncMbarrierStateSpace::Generic => {
-                                            llvm.arguments == ["ptr"]
-                                        }
-                                        CpAsyncMbarrierStateSpace::Shared => {
-                                            llvm.arguments == ["shared_ptr"]
-                                        }
-                                    }
-                            })
-                    }),
-                "{} is outside the closed generated cp.async mbarrier recipe",
-                record.id
-            ),
-            "mbarrier_basic" => ensure!(
-                record.rust.module == "barrier"
-                    && !record.rust.safe
-                    && record.lowering == "generated_mbarrier_basic"
-                    && record.mbarrier_basic.as_ref().is_some_and(|mbarrier| {
-                        mbarrier.state_space == MbarrierStateSpace::Shared
-                            && match (mbarrier.operation, mbarrier.adapter) {
-                                (
-                                    MbarrierBasicOperation::Init,
-                                    MbarrierBasicAdapter::InitPointerCountToVoid,
-                                ) => {
-                                    record.rust.arguments == ["*mut u64", "u32"]
-                                        && record.rust.result == "()"
-                                        && !record.rust.must_use
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.arguments == ["shared_ptr", "i32"]
-                                                && llvm.results.is_empty()
-                                        })
-                                        && record.dialect.operands == ["ptr", "i32"]
-                                        && record.dialect.results.is_empty()
-                                }
-                                (
-                                    MbarrierBasicOperation::Arrive,
-                                    MbarrierBasicAdapter::ArrivePointerToToken,
-                                ) => {
-                                    record.rust.arguments == ["*const u64"]
-                                        && record.rust.result == "u64"
-                                        && record.rust.must_use
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.arguments == ["shared_ptr"]
-                                                && llvm.results == ["i64"]
-                                        })
-                                        && record.dialect.operands == ["ptr"]
-                                        && record.dialect.results == ["i64"]
-                                }
-                                (
-                                    MbarrierBasicOperation::TestWait,
-                                    MbarrierBasicAdapter::TestWaitPointerTokenToPredicate,
-                                ) => {
-                                    record.rust.arguments == ["*const u64", "u64"]
-                                        && record.rust.result == "bool"
-                                        && record.rust.must_use
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.arguments == ["shared_ptr", "i64"]
-                                                && llvm.results == ["i1"]
-                                        })
-                                        && record.dialect.operands == ["ptr", "i64"]
-                                        && record.dialect.results == ["i1"]
-                                }
-                                (
-                                    MbarrierBasicOperation::Inval,
-                                    MbarrierBasicAdapter::InvalPointerToVoid,
-                                ) => {
-                                    record.rust.arguments == ["*mut u64"]
-                                        && record.rust.result == "()"
-                                        && !record.rust.must_use
-                                        && record.llvm.as_ref().is_some_and(|llvm| {
-                                            llvm.arguments == ["shared_ptr"]
-                                                && llvm.results.is_empty()
-                                        })
-                                        && record.dialect.operands == ["ptr"]
-                                        && record.dialect.results.is_empty()
-                                }
-                                _ => false,
-                            }
-                    }),
-                "{} is outside the closed generated basic mbarrier recipe",
-                record.id
-            ),
-            "mbarrier_extended" => ensure!(
-                record.rust.module == "barrier"
-                    && !record.rust.safe
-                    && record.semantics.memory == "read_write"
-                    && record.semantics.convergent
-                    && record.lowering == "generated_mbarrier_extended_inline_ptx"
-                    && record.backend_lowerings.iter().all(|lowering| {
-                        lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    })
-                    && record.mbarrier_extended.as_ref().is_some_and(|mbarrier| {
-                        let source_matches = match mbarrier.source_contract {
-                            MbarrierExtendedSourceContract::LlvmImported => record.llvm.is_some(),
-                            MbarrierExtendedSourceContract::PtxNativeRawClusterAddress => {
-                                record.llvm.is_none()
-                                    && matches!(record.source, IntrinsicSource::PtxNative { .. })
-                            }
-                        };
-                        source_matches
-                            && match (mbarrier.operation, mbarrier.adapter) {
-                                (
-                                    MbarrierExtendedOperation::ArriveExpectTxCta,
-                                    MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount,
-                                ) => record.id == "mbarrier_arrive_expect_tx",
-                                (
-                                    MbarrierExtendedOperation::ArriveExpectTxCluster,
-                                    MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount,
-                                ) => record.id == "mbarrier_arrive_expect_tx_cluster",
-                                (
-                                    MbarrierExtendedOperation::ArriveRemoteCluster,
-                                    MbarrierExtendedAdapter::RawClusterAddressToVoid,
-                                ) => record.id == "mbarrier_arrive_cluster",
-                                (
-                                    MbarrierExtendedOperation::TryWaitTokenCta,
-                                    MbarrierExtendedAdapter::PointerTokenToPredicate,
-                                ) => record.id == "mbarrier_try_wait",
-                                (
-                                    MbarrierExtendedOperation::TryWaitParityCta,
-                                    MbarrierExtendedAdapter::PointerParityToPredicate,
-                                ) => record.id == "mbarrier_try_wait_parity",
-                                (
-                                    MbarrierExtendedOperation::TryWaitParityCluster,
-                                    MbarrierExtendedAdapter::PointerParityToPredicate,
-                                ) => record.id == "mbarrier_try_wait_parity_cluster",
-                                (
-                                    MbarrierExtendedOperation::FenceProxyAsyncSharedCta,
-                                    MbarrierExtendedAdapter::ZeroOperandsToVoid,
-                                ) => record.id == "fence_proxy_async_shared_cta",
-                                (
-                                    MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster,
-                                    MbarrierExtendedAdapter::ZeroOperandsToVoid,
-                                ) => record.id == "fence_mbarrier_init_release_cluster",
-                                (
-                                    MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster,
-                                    MbarrierExtendedAdapter::ZeroOperandsToVoid,
-                                ) => record.id
-                                    == "fence_proxy_async_generic_release_shared_cta_cluster",
-                                (
-                                    MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster,
-                                    MbarrierExtendedAdapter::ZeroOperandsToVoid,
-                                ) => record.id
-                                    == "fence_proxy_async_generic_acquire_shared_cluster_cluster",
-                                (
-                                    MbarrierExtendedOperation::Nanosleep,
-                                    MbarrierExtendedAdapter::NanosecondsToVoid,
-                                ) => record.id == "nanosleep",
-                                _ => false,
-                            }
-                    }),
-                "{} is outside the closed generated extended-mbarrier recipe",
-                record.id
-            ),
-            "sync" => {
-                if record.id == "sync_threads" {
-                    ensure!(
-                        record.rust.module == "thread"
-                            && record.rust.name == "sync_threads"
-                            && record.rust.arguments.is_empty()
-                            && record.rust.result == "()"
-                            && !record.rust.safe
-                            && !record.rust.must_use
-                            && record.llvm.as_ref().is_some_and(|llvm| {
-                                llvm.symbol == "llvm.nvvm.barrier.cta.sync.aligned.all"
-                                    && llvm.arguments == ["i32"]
-                                    && llvm.results.is_empty()
-                            })
-                            && record.dialect.op_type == "Barrier0Op"
-                            && record.dialect.op_name == "nvvm.barrier0"
-                            && record.dialect.operands.is_empty()
-                            && record.dialect.results.is_empty()
-                            && record.lowering == "generated_sync_threads",
-                        "{} is outside the fixed-zero generated sync_threads recipe",
-                        record.id
-                    );
-                } else {
-                    ensure!(
-                        threadfence_ptx_level(record).is_some()
-                            && record.rust.module == "fence"
-                            && record.rust.name == record.id
-                            && record.rust.arguments.is_empty()
-                            && record.rust.result == "()"
-                            && record.rust.safe
-                            && !record.rust.must_use
-                            && record.llvm.as_ref().is_some_and(|llvm| {
-                                llvm.arguments.is_empty() && llvm.results.is_empty()
-                            })
-                            && record.dialect.operands.is_empty()
-                            && record.dialect.results.is_empty()
-                            && record.lowering == "direct_nvvm"
-                            && record.semantics.memory == "read_write"
-                            && !record.semantics.pure
-                            && !record.semantics.convergent,
-                        "{} is outside the closed generated thread-fence recipe",
-                        record.id
-                    );
-                }
-            }
-            "vote" => ensure!(
-                record.rust.module == "warp"
-                    && record.rust.arguments == ["u32", "bool"]
-                    && matches!(record.rust.result.as_str(), "bool" | "u32")
-                    && !record.rust.safe
-                    && record.rust.must_use
-                    && record.llvm.as_ref().is_some_and(|llvm| {
-                        llvm.arguments == ["i32", "i1"]
-                            && matches!(llvm.results.as_slice(), [result]
-                                if result == "i1" || result == "i32")
-                    })
-                    && record.dialect.operands == ["i32", "i1"]
-                    && matches!(record.dialect.results.as_slice(), [result]
-                        if result == "i1" || result == "i32")
-                    && record.lowering == "generated_vote"
-                    && record.vote.is_some(),
-                "{} is outside the closed generated vote.sync recipe",
-                record.id
-            ),
-            "active_mask" => ensure!(
-                record.id == "active_mask"
-                    && record.rust.module == "warp"
-                    && record.rust.arguments.is_empty()
-                    && record.rust.result == "u32"
-                    && record.rust.safe
-                    && record.rust.must_use
-                    && record.llvm.as_ref().is_some_and(|llvm| {
-                        llvm.arguments.is_empty() && llvm.results == ["i32"]
-                    })
-                    && record.dialect.operands.is_empty()
-                    && record.dialect.results == ["i32"]
-                    && record.lowering == "generated_active_mask"
-                    && record.active_mask.is_some(),
-                "{} is outside the closed generated active-mask recipe",
-                record.id
-            ),
-            "warp_match" => ensure!(
-                record.rust.module == "warp"
-                    && matches!(record.rust.arguments.as_slice(), [mask, value]
-                        if mask == "u32" && matches!(value.as_str(), "u32" | "u64"))
-                    && record.rust.result == "u32"
-                    && !record.rust.safe
-                    && record.rust.must_use
-                    && record.llvm.as_ref().is_some_and(|llvm| {
-                        matches!(llvm.arguments.as_slice(), [mask, value]
-                            if mask == "i32" && matches!(value.as_str(), "i32" | "i64"))
-                            && (matches!(llvm.results.as_slice(), [mask] if mask == "i32")
-                                || matches!(llvm.results.as_slice(), [mask, predicate]
-                                    if mask == "i32" && predicate == "i1"))
-                    })
-                    && matches!(record.dialect.operands.as_slice(), [mask, value]
-                        if mask == "i32" && matches!(value.as_str(), "i32" | "i64"))
-                    && record.dialect.results == ["i32"]
-                    && record.lowering == "generated_warp_match"
-                    && record.warp_match.is_some(),
-                "{} is outside the closed generated match.sync recipe",
-                record.id
-            ),
-            "elect" => ensure!(
-                record.id == "elect_sync"
-                    && record.rust.module == "warp"
-                    && record.rust.name == "elect_sync"
-                    && record.rust.arguments == ["u32"]
-                    && record.rust.result == "(u32, bool)"
-                    && !record.rust.safe
-                    && record.rust.must_use
-                    && record.llvm.as_ref().is_some_and(|llvm| {
-                        llvm.symbol == "llvm.nvvm.elect.sync"
-                            && llvm.arguments == ["i32"]
-                            && llvm.results == ["i32", "i1"]
-                    })
-                    && record.dialect.op_type == "ElectSyncOp"
-                    && record.dialect.op_name == "nvvm.elect_sync"
-                    && record.dialect.operands == ["i32"]
-                    && record.dialect.results == ["i32", "i1"]
-                    && record.lowering == "generated_elect",
-                "{} is outside the closed generated elect.sync recipe",
-                record.id
-            ),
-            "warp_barrier" => ensure!(
-                record.id == "sync_mask"
-                    && record.rust.module == "warp"
-                    && record.rust.name == "sync_mask"
-                    && record.rust.arguments == ["u32"]
-                    && record.rust.result == "()"
-                    && !record.rust.safe
-                    && !record.rust.must_use
-                    && record.llvm.as_ref().is_some_and(|llvm| {
-                        llvm.symbol == "llvm.nvvm.bar.warp.sync"
-                            && llvm.arguments == ["i32"]
-                            && llvm.results.is_empty()
-                    })
-                    && record.dialect.op_type == "BarWarpSyncOp"
-                    && record.dialect.op_name == "nvvm.bar_warp_sync"
-                    && record.dialect.operands == ["i32"]
-                    && record.dialect.results.is_empty()
-                    && record.lowering == "generated_warp_barrier"
-                    && record.warp_barrier.as_ref().is_some_and(|barrier| {
-                        barrier.adapter == WarpBarrierAdapter::DirectMemberMask
-                    }),
-                "{} is outside the closed generated bar.warp.sync recipe",
-                record.id
-            ),
-            "warp_shuffle" => ensure!(
-                record.rust.module == "warp"
-                    && matches!(record.rust.arguments.as_slice(), [mask, value, lane]
-                        if mask == "u32"
-                            && lane == "u32"
-                            && matches!(value.as_str(), "u32" | "f32" | "u64")
-                            && value == &record.rust.result)
-                    && !record.rust.safe
-                    && record.rust.must_use
-                    && matches!(record.dialect.operands.as_slice(), [mask, value, lane]
-                        if mask == "i32"
-                            && lane == "i32"
-                            && matches!(value.as_str(), "i32" | "f32" | "i64"))
-                    && matches!(record.dialect.results.as_slice(), [result]
-                        if result == &record.dialect.operands[1])
-                    && record.warp_shuffle.as_ref().is_some_and(|shuffle| {
-                        match shuffle.value_kind {
-                            WarpShuffleValueKind::I32 | WarpShuffleValueKind::F32 => {
-                                let (value_ty, rust_ty) = match shuffle.value_kind {
-                                    WarpShuffleValueKind::I32 => ("i32", "u32"),
-                                    WarpShuffleValueKind::F32 => ("f32", "f32"),
-                                    WarpShuffleValueKind::I64 => unreachable!(),
-                                };
-                                shuffle.adapter
-                                    == WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp
-                                    && shuffle.lane_encoding
-                                        == WarpShuffleOperandEncoding::RegisterOrImmediate
-                                    && shuffle.mask_encoding
-                                        == WarpShuffleOperandEncoding::RegisterOrImmediate
-                                    && record.lowering == "generated_warp_shuffle"
-                                    && record.rust.result == rust_ty
-                                    && record.dialect.operands[1] == value_ty
-                                    && record.llvm.as_ref().is_some_and(|llvm| {
-                                        matches!(llvm.arguments.as_slice(), [mask, value, lane, clamp]
-                                            if mask == "i32"
-                                                && value == value_ty
-                                                && lane == "i32"
-                                                && clamp == "i32")
-                                            && llvm.results == [value_ty]
-                                    })
-                            }
-                            WarpShuffleValueKind::I64 => {
-                                shuffle.adapter
-                                    == WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
-                                    && shuffle.lane_encoding
-                                        == WarpShuffleOperandEncoding::RegisterOnly
-                                    && shuffle.mask_encoding
-                                        == WarpShuffleOperandEncoding::RegisterOnly
-                                    && record.rust.result == "u64"
-                                    && record.dialect.operands[1] == "i64"
-                                    && record.lowering
-                                        == "generated_warp_shuffle_i64_inline_ptx"
-                                    && record.llvm.is_none()
-                                    && matches!(record.source, IntrinsicSource::PtxNative { .. })
-                            }
-                        }
-                    }),
-                "{} is outside the closed generated shfl.sync recipe",
-                record.id
-            ),
-            "integer_minmax" => ensure!(
-                record.integer_minmax.as_ref().is_some_and(|minmax| {
-                    let module = match minmax.format {
-                        IntegerMinMaxFormat::S32 => "int",
-                        IntegerMinMaxFormat::S16x2 | IntegerMinMaxFormat::U16x2 => "i16x2",
-                    };
-                    record.rust.module == module
-                })
-                    && record.rust.arguments.len() == 2
-                    && record
-                        .rust
-                        .arguments
-                        .iter()
-                        .all(|argument| argument == &record.rust.result)
-                    && matches!(record.rust.result.as_str(), "i32" | "u32")
-                    && record.rust.safe
-                    && record.rust.must_use
-                    && record.dialect.operands == ["i32", "i32"]
-                    && record.dialect.results == ["i32"]
-                    && record.lowering == "generated_integer_minmax_inline_ptx",
-                "{} is outside the closed generated integer-min/max recipe",
-                record.id
-            ),
-            family => ensure!(false, "{} has unrenderable family {family}", record.id),
-        };
-    }
-    Ok(())
-}
-
-fn rust_header(catalog: &CatalogFile, catalog_sha256: &str) -> String {
-    format!(
-        "/*\n * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n * SPDX-License-Identifier: Apache-2.0\n */\n\n// @generated by cuda-intrinsics-gen {}. DO NOT EDIT.\n// Catalog schema/version: {}/{}; intrinsic ABI: v{}; catalog SHA-256: {}.\n// LLVM source: {}.\n\n",
-        catalog.generator_version,
-        catalog.schema,
-        catalog.catalog_version,
-        catalog.intrinsic_abi,
-        catalog_sha256,
-        catalog.source.llvm_revision
-    )
-}
-
-fn llvm_header(catalog: &CatalogFile, catalog_sha256: &str) -> String {
-    format!(
-        "; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n; SPDX-License-Identifier: Apache-2.0\n; @generated by cuda-intrinsics-gen {}. DO NOT EDIT.\n; Catalog schema/version: {}/{}; intrinsic ABI: v{}; catalog SHA-256: {}.\n; LLVM source: {}.\n\n",
-        catalog.generator_version,
-        catalog.schema,
-        catalog.catalog_version,
-        catalog.intrinsic_abi,
-        catalog_sha256,
-        catalog.source.llvm_revision
-    )
-}
-
-fn markdown_header(catalog: &CatalogFile, catalog_sha256: &str) -> String {
-    format!(
-        "<!--\nSPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\nSPDX-License-Identifier: Apache-2.0\n@generated by cuda-intrinsics-gen {}. DO NOT EDIT.\nCatalog schema/version: {}/{}; intrinsic ABI: v{}; catalog SHA-256: {}.\nLLVM source: {}.\n-->\n\n",
-        catalog.generator_version,
-        catalog.schema,
-        catalog.catalog_version,
-        catalog.intrinsic_abi,
-        catalog_sha256,
-        catalog.source.llvm_revision
-    )
-}
-
-fn sregs(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "sreg")
-}
-
-fn ldmatrix(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "ldmatrix")
-}
-
-fn is_blackwell_ldmatrix(record: &CatalogIntrinsic) -> bool {
-    record
-        .ldmatrix
-        .as_ref()
-        .is_some_and(|ldmatrix| ldmatrix.variant.shape != LdmatrixShape::M8n8)
-}
-
-const BLACKWELL_LDMATRIX_EFFECTIVE_FLOORS: &str = "sm_100a PTX 8.6, sm_100f PTX 8.8, sm_103a PTX 8.8, sm_103f PTX 8.8, sm_110a PTX 9.0, sm_110f PTX 9.0, sm_120a PTX 8.7, sm_120f PTX 8.8, sm_121a PTX 8.8, sm_121f PTX 8.8";
-
-fn ldmatrix_compat_op(record: &CatalogIntrinsic) -> Option<(&'static str, &'static str)> {
-    match record.id.as_str() {
-        "ldmatrix_m8n8_x1_b16" => Some(("LdmatrixX1Op", "nvvm.ldmatrix_x1")),
-        "ldmatrix_m8n8_x1_trans_b16" => Some(("LdmatrixX1TransOp", "nvvm.ldmatrix_x1_trans")),
-        "ldmatrix_m8n8_x2_b16" => Some(("LdmatrixX2Op", "nvvm.ldmatrix_x2")),
-        "ldmatrix_m8n8_x2_trans_b16" => Some(("LdmatrixX2TransOp", "nvvm.ldmatrix_x2_trans")),
-        "ldmatrix_m8n8_x4_b16" => Some(("LdmatrixX4Op", "nvvm.ldmatrix_x4")),
-        "ldmatrix_m8n8_x4_trans_b16" => Some(("LdmatrixX4TransOp", "nvvm.ldmatrix_x4_trans")),
-        _ => None,
-    }
-}
-
-fn stmatrices(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "stmatrix")
-}
-
-fn stmatrix_variant(record: &CatalogIntrinsic) -> Option<(StmatrixMultiplicity, StmatrixLayout)> {
-    match record.id.as_str() {
-        "stmatrix_m8n8_x2_b16" => Some((StmatrixMultiplicity::X2, StmatrixLayout::Normal)),
-        "stmatrix_m8n8_x2_trans_b16" => {
-            Some((StmatrixMultiplicity::X2, StmatrixLayout::Transposed))
-        }
-        "stmatrix_m8n8_x4_b16" => Some((StmatrixMultiplicity::X4, StmatrixLayout::Normal)),
-        "stmatrix_m8n8_x4_trans_b16" => {
-            Some((StmatrixMultiplicity::X4, StmatrixLayout::Transposed))
-        }
-        _ => None,
-    }
-}
-
-fn stmatrix_compatibility_name(record: &CatalogIntrinsic) -> &'static str {
-    match record.id.as_str() {
-        "stmatrix_m8n8_x2_b16" => "stmatrix_m8n8_x2",
-        "stmatrix_m8n8_x2_trans_b16" => "stmatrix_m8n8_x2_trans",
-        "stmatrix_m8n8_x4_b16" => "stmatrix_m8n8_x4",
-        "stmatrix_m8n8_x4_trans_b16" => "stmatrix_m8n8_x4_trans",
-        _ => panic!("unknown stmatrix record {}", record.id),
-    }
-}
-
-fn register_mmas(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "register_mma")
-}
-
-fn sparse_mmas(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "sparse_mma")
-}
-
-fn packed_atomics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "packed_atomic")
-}
-
-fn redux(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "redux")
-}
-
-fn dot_products(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "dotprod")
-}
-
-fn packed_alus(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "packed_alu")
-}
-
-fn packed_alu_format_shape(
-    format: PackedAluFormat,
-) -> (
-    &'static str,
-    bool,
-    &'static str,
-    &'static str,
-    PackedAluAdapter,
-) {
-    match format {
-        PackedAluFormat::Bf16x2 => (
-            "bf16x2",
-            false,
-            "u32",
-            "i32",
-            PackedAluAdapter::DirectPackedU32,
-        ),
-        PackedAluFormat::F16x2 => (
-            "f16x2",
-            true,
-            "u32",
-            "i32",
-            PackedAluAdapter::DirectPackedU32,
-        ),
-        PackedAluFormat::F32x2 => (
-            "f32x2",
-            true,
-            "u64",
-            "i64",
-            PackedAluAdapter::DirectPackedU64,
-        ),
-    }
-}
-
-fn packed_alu_width(record: &CatalogIntrinsic) -> u32 {
-    match record
-        .packed_alu
-        .as_ref()
-        .expect("packed-ALU record")
-        .adapter
-    {
-        PackedAluAdapter::DirectPackedU32 => 32,
-        PackedAluAdapter::DirectPackedU64 => 64,
-    }
-}
-
-fn packed_alu_register_constraint(record: &CatalogIntrinsic) -> &'static str {
-    match packed_alu_width(record) {
-        32 => "r",
-        64 => "l",
-        _ => unreachable!("closed packed-ALU carrier width"),
-    }
-}
-
-fn packed_conversions(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "packed_conversion")
-}
-
-fn scalar_conversions(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "scalar_conversion")
-}
-
-fn scalar_conversion_rounding_attr(record: &CatalogIntrinsic) -> &'static str {
-    match record
-        .scalar_conversion
-        .as_ref()
-        .expect("scalar-conversion contract")
-        .rounding
-    {
-        ScalarConversionRounding::NearestAway => "ScalarConversionRoundingAttr::NearestAway",
-        ScalarConversionRounding::NearestEven => "ScalarConversionRoundingAttr::NearestEven",
-        ScalarConversionRounding::TowardZero => "ScalarConversionRoundingAttr::TowardZero",
-    }
-}
-
-fn scalar_conversion_saturation_attr(record: &CatalogIntrinsic) -> &'static str {
-    match record
-        .scalar_conversion
-        .as_ref()
-        .expect("scalar-conversion contract")
-        .saturation
-    {
-        ScalarConversionSaturation::None => "ScalarConversionSaturationAttr::None",
-        ScalarConversionSaturation::Relu => "ScalarConversionSaturationAttr::Relu",
-        ScalarConversionSaturation::Satfinite => "ScalarConversionSaturationAttr::Satfinite",
-        ScalarConversionSaturation::ReluSatfinite => {
-            "ScalarConversionSaturationAttr::ReluSatfinite"
-        }
-    }
-}
-
-fn scalar_conversion_ptx_mnemonic(record: &CatalogIntrinsic) -> String {
-    format!(
-        "{}.{}",
-        record.expected_ptx.mnemonic,
-        record.expected_ptx.modifiers.join(".")
-    )
-}
-
-fn scalar_arithmetics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "scalar_arithmetic")
-}
-
-fn extended_minmax(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "extended_minmax")
-}
-
-fn extended_minmax_contract(record: &CatalogIntrinsic) -> &crate::model::ExtendedMinMax {
-    record
-        .extended_minmax
-        .as_ref()
-        .expect("extended-minmax contract")
-}
-
-fn extended_minmax_format_attr(record: &CatalogIntrinsic) -> &'static str {
-    match extended_minmax_contract(record).format {
-        ExtendedMinMaxFormat::F32 => "ExtendedMinMaxFormatAttr::F32",
-        ExtendedMinMaxFormat::F16 => "ExtendedMinMaxFormatAttr::F16",
-        ExtendedMinMaxFormat::Bf16 => "ExtendedMinMaxFormatAttr::Bf16",
-        ExtendedMinMaxFormat::F16x2 => "ExtendedMinMaxFormatAttr::F16x2",
-        ExtendedMinMaxFormat::Bf16x2 => "ExtendedMinMaxFormatAttr::Bf16x2",
-    }
-}
-
-fn extended_minmax_operation_attr(record: &CatalogIntrinsic) -> &'static str {
-    match extended_minmax_contract(record).operation {
-        ExtendedMinMaxOperation::Min => "ExtendedMinMaxOperationAttr::Min",
-        ExtendedMinMaxOperation::Max => "ExtendedMinMaxOperationAttr::Max",
-    }
-}
-
-fn extended_minmax_subnormal_attr(record: &CatalogIntrinsic) -> &'static str {
-    match extended_minmax_contract(record).subnormal {
-        ExtendedMinMaxSubnormal::Preserve => "ExtendedMinMaxSubnormalAttr::Preserve",
-        ExtendedMinMaxSubnormal::Ftz => "ExtendedMinMaxSubnormalAttr::Ftz",
-    }
-}
-
-fn extended_minmax_nan_attr(record: &CatalogIntrinsic) -> &'static str {
-    match extended_minmax_contract(record).nan {
-        ExtendedMinMaxNan::Number => "ExtendedMinMaxNanAttr::Number",
-        ExtendedMinMaxNan::Nan => "ExtendedMinMaxNanAttr::Nan",
-    }
-}
-
-fn extended_minmax_xorsign_abs_attr(record: &CatalogIntrinsic) -> &'static str {
-    if extended_minmax_contract(record).xorsign_abs {
-        "ExtendedMinMaxXorSignAbsAttr::Enabled"
-    } else {
-        "ExtendedMinMaxXorSignAbsAttr::Disabled"
-    }
-}
-
-fn extended_minmax_carrier(record: &CatalogIntrinsic) -> &'static str {
-    match extended_minmax_contract(record).format {
-        ExtendedMinMaxFormat::F32 => "MinMaxCarrier::F32",
-        ExtendedMinMaxFormat::F16 | ExtendedMinMaxFormat::Bf16 => "MinMaxCarrier::Half16",
-        ExtendedMinMaxFormat::F16x2 | ExtendedMinMaxFormat::Bf16x2 => "MinMaxCarrier::PackedU32",
-    }
-}
-
-fn extended_minmax_rust_type(record: &CatalogIntrinsic) -> &'static str {
-    match extended_minmax_contract(record).format {
-        ExtendedMinMaxFormat::F32 => "f32",
-        ExtendedMinMaxFormat::F16 | ExtendedMinMaxFormat::Bf16 => "u16",
-        ExtendedMinMaxFormat::F16x2 | ExtendedMinMaxFormat::Bf16x2 => "u32",
-    }
-}
-
-fn extended_minmax_ptx_mnemonic(record: &CatalogIntrinsic) -> String {
-    format!(
-        "{}.{}",
-        record.expected_ptx.mnemonic,
-        record.expected_ptx.modifiers.join(".")
-    )
-}
-
-fn scalar_arithmetic_contract(record: &CatalogIntrinsic) -> &crate::model::ScalarArithmetic {
-    record
-        .scalar_arithmetic
-        .as_ref()
-        .expect("scalar-arithmetic contract")
-}
-
-fn scalar_arithmetic_format_attr(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_arithmetic_contract(record).format {
-        ScalarArithmeticFormat::F32 => "ScalarArithmeticFormatAttr::F32",
-        ScalarArithmeticFormat::F64 => "ScalarArithmeticFormatAttr::F64",
-    }
-}
-
-fn scalar_arithmetic_operation_attr(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_arithmetic_contract(record).operation {
-        ScalarArithmeticOperation::Mul => "ScalarArithmeticOperationAttr::Mul",
-        ScalarArithmeticOperation::Div => "ScalarArithmeticOperationAttr::Div",
-        ScalarArithmeticOperation::Fma => "ScalarArithmeticOperationAttr::Fma",
-        ScalarArithmeticOperation::Add => "ScalarArithmeticOperationAttr::Add",
-    }
-}
-
-fn scalar_arithmetic_rounding_attr(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_arithmetic_contract(record).rounding {
-        ScalarArithmeticRounding::Rn => "ScalarArithmeticRoundingAttr::Rn",
-        ScalarArithmeticRounding::Rz => "ScalarArithmeticRoundingAttr::Rz",
-        ScalarArithmeticRounding::Rm => "ScalarArithmeticRoundingAttr::Rm",
-        ScalarArithmeticRounding::Rp => "ScalarArithmeticRoundingAttr::Rp",
-    }
-}
-
-fn scalar_arithmetic_subnormal_attr(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_arithmetic_contract(record).subnormal {
-        ScalarArithmeticSubnormal::Preserve => "ScalarArithmeticSubnormalAttr::Preserve",
-        ScalarArithmeticSubnormal::Ftz => "ScalarArithmeticSubnormalAttr::Ftz",
-    }
-}
-
-fn scalar_arithmetic_saturation_attr(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_arithmetic_contract(record).saturation {
-        ScalarArithmeticSaturation::None => "ScalarArithmeticSaturationAttr::None",
-        ScalarArithmeticSaturation::Sat => "ScalarArithmeticSaturationAttr::Sat",
-    }
-}
-
-fn scalar_arithmetic_arity(record: &CatalogIntrinsic) -> usize {
-    match scalar_arithmetic_contract(record).operation {
-        ScalarArithmeticOperation::Mul
-        | ScalarArithmeticOperation::Div
-        | ScalarArithmeticOperation::Add => 2,
-        ScalarArithmeticOperation::Fma => 3,
-    }
-}
-
-fn scalar_arithmetic_rust_type(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_arithmetic_contract(record).format {
-        ScalarArithmeticFormat::F32 => "f32",
-        ScalarArithmeticFormat::F64 => "f64",
-    }
-}
-
-fn scalar_arithmetic_llvm_type(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_arithmetic_contract(record).format {
-        ScalarArithmeticFormat::F32 => "float",
-        ScalarArithmeticFormat::F64 => "double",
-    }
-}
-
-fn scalar_arithmetic_ptx_mnemonic(record: &CatalogIntrinsic) -> String {
-    format!(
-        "{}.{}",
-        record.expected_ptx.mnemonic,
-        record.expected_ptx.modifiers.join(".")
-    )
-}
-
-fn scalar_arithmetic_llvm_mechanism(record: &CatalogIntrinsic) -> BackendLoweringMechanism {
-    record
-        .backend_lowerings
-        .iter()
-        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-        .expect("scalar arithmetic has an LLVM-NVPTX route")
-        .mechanism
-}
-
-fn scalar_maths(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "scalar_math")
-}
-
-fn scalar_math_contract(record: &CatalogIntrinsic) -> &crate::model::ScalarMath {
-    record.scalar_math.as_ref().expect("scalar-math contract")
-}
-
-fn scalar_math_format_attr(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_math_contract(record).format {
-        ScalarMathFormat::F16 => "ScalarMathFormatAttr::F16",
-        ScalarMathFormat::F32 => "ScalarMathFormatAttr::F32",
-        ScalarMathFormat::F64 => "ScalarMathFormatAttr::F64",
-    }
-}
-
-fn scalar_math_operation_attr(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_math_contract(record).operation {
-        ScalarMathOperation::Sin => "ScalarMathOperationAttr::Sin",
-        ScalarMathOperation::Cos => "ScalarMathOperationAttr::Cos",
-        ScalarMathOperation::Ex2 => "ScalarMathOperationAttr::Ex2",
-        ScalarMathOperation::Lg2 => "ScalarMathOperationAttr::Lg2",
-        ScalarMathOperation::Rcp => "ScalarMathOperationAttr::Rcp",
-        ScalarMathOperation::Rsqrt => "ScalarMathOperationAttr::Rsqrt",
-        ScalarMathOperation::Sqrt => "ScalarMathOperationAttr::Sqrt",
-        ScalarMathOperation::Tanh => "ScalarMathOperationAttr::Tanh",
-    }
-}
-
-fn scalar_math_precision_attr(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_math_contract(record).precision {
-        ScalarMathPrecision::Approx => "ScalarMathPrecisionAttr::Approx",
-        ScalarMathPrecision::Rn => "ScalarMathPrecisionAttr::Rn",
-        ScalarMathPrecision::Rz => "ScalarMathPrecisionAttr::Rz",
-        ScalarMathPrecision::Rm => "ScalarMathPrecisionAttr::Rm",
-        ScalarMathPrecision::Rp => "ScalarMathPrecisionAttr::Rp",
-    }
-}
-
-fn scalar_math_subnormal_attr(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_math_contract(record).subnormal {
-        ScalarMathSubnormal::Preserve => "ScalarMathSubnormalAttr::Preserve",
-        ScalarMathSubnormal::Ftz => "ScalarMathSubnormalAttr::Ftz",
-    }
-}
-
-fn scalar_math_llvm_type(record: &CatalogIntrinsic) -> &'static str {
-    match scalar_math_contract(record).format {
-        ScalarMathFormat::F16 => "i16",
-        ScalarMathFormat::F32 => "float",
-        ScalarMathFormat::F64 => "double",
-    }
-}
-
-fn scalar_math_ptx_mnemonic(record: &CatalogIntrinsic) -> String {
-    format!(
-        "{}.{}",
-        record.expected_ptx.mnemonic,
-        record.expected_ptx.modifiers.join(".")
-    )
-}
-
-fn scalar_math_llvm_mechanism(record: &CatalogIntrinsic) -> BackendLoweringMechanism {
-    record
-        .backend_lowerings
-        .iter()
-        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-        .expect("scalar math has an LLVM-NVPTX route")
-        .mechanism
-}
-
-fn prmts(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "prmt")
-}
-
-fn cluster_barriers(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "cluster_barrier")
-}
-
-fn cluster_barrier_attr(record: &CatalogIntrinsic) -> &'static str {
-    match record
-        .cluster_barrier
-        .as_ref()
-        .expect("cluster-barrier contract")
-        .mode
-    {
-        ClusterBarrierMode::Arrive => "ClusterBarrierModeAttr::Arrive",
-        ClusterBarrierMode::ArriveAligned => "ClusterBarrierModeAttr::ArriveAligned",
-        ClusterBarrierMode::ArriveRelaxed => "ClusterBarrierModeAttr::ArriveRelaxed",
-        ClusterBarrierMode::ArriveRelaxedAligned => "ClusterBarrierModeAttr::ArriveRelaxedAligned",
-        ClusterBarrierMode::Wait => "ClusterBarrierModeAttr::Wait",
-        ClusterBarrierMode::WaitAligned => "ClusterBarrierModeAttr::WaitAligned",
-    }
-}
-
-fn cluster_barrier_template(record: &CatalogIntrinsic) -> String {
-    format!(
-        "{}.{};",
-        record.expected_ptx.mnemonic,
-        record.expected_ptx.modifiers.join(".")
-    )
-}
-
-fn debug_controls(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "debug_control")
-}
-
-fn cluster_memory(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "cluster_memory")
-}
-
-fn clc_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "clc")
-}
-
-#[derive(Clone, Copy)]
-enum ClcSafetyArgNames {
-    RawAbi,
-    Compatibility,
-}
-
-fn clc_safety_lines(operation: ClcOperation, names: ClcSafetyArgNames) -> Vec<String> {
-    let (response, mbar, resp_lo, resp_hi) = match names {
-        ClcSafetyArgNames::RawAbi => ("`_arg0`", "`_arg1`", "`_arg0`", "`_arg1`"),
-        ClcSafetyArgNames::Compatibility => ("`response`", "`mbar`", "`resp_lo`", "`resp_hi`"),
-    };
-    match operation {
-        ClcOperation::TryCancel => vec![
-            format!(
-                "{response} must designate a writable, 16-byte-aligned 16-byte region in `shared::cta` memory, and {mbar} must designate a valid, aligned shared-memory mbarrier."
-            ),
-            format!(
-                "The calling CTA must issue `arrive_expect_tx` for {mbar} with 16 bytes before this request."
-            ),
-            "This CTA must not have observed a prior CLC try-cancel request fail.".into(),
-        ],
-        ClcOperation::TryCancelMulticast => vec![
-            format!(
-                "{response} must designate a writable, 16-byte-aligned 16-byte region in `shared::cta` memory, and {mbar} must designate a valid, aligned shared-memory mbarrier."
-            ),
-            format!(
-                "Each CTA must issue `arrive_expect_tx` for its own corresponding mbarrier with 16 bytes before this request."
-            ),
-            "This CTA must not have observed a prior CLC try-cancel request fail.".into(),
-            "The response is written to every CTA's shared-memory window and signals every CTA's mbarrier.".into(),
-            "Every CTA in the cluster must still be active.".into(),
-        ],
-        ClcOperation::QueryIsCanceled => vec![format!(
-            "{resp_lo} and {resp_hi} must be the two halves of an opaque response observed complete from a prior CLC try-cancel request."
-        )],
-        ClcOperation::QueryGetFirstCtaidX
-        | ClcOperation::QueryGetFirstCtaidY
-        | ClcOperation::QueryGetFirstCtaidZ => vec![
-            format!(
-                "{resp_lo} and {resp_hi} must be the two halves of an opaque response observed complete from a prior CLC try-cancel request."
-            ),
-            "The result is meaningful only when `clc_query_is_canceled` returned one for this response.".into(),
-        ],
-    }
-}
-
-fn render_clc_safety_lines(output: &mut String, operation: ClcOperation, names: ClcSafetyArgNames) {
-    for line in clc_safety_lines(operation, names) {
-        writeln!(output, "/// {line}").unwrap();
-    }
-}
-
-fn tma_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "tma")
-}
-
-fn execution_controls(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog.intrinsics.iter().filter(|record| {
-        matches!(
-            record.family.as_str(),
-            "counted_barrier" | "grid_dependency" | "register_control"
-        )
-    })
-}
-
-fn execution_control_family<'a>(
-    catalog: &'a CatalogFile,
-    family: &'a str,
-) -> impl Iterator<Item = &'a CatalogIntrinsic> {
-    execution_controls(catalog).filter(move |record| record.family == family)
-}
-
-fn wgmma_controls(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "wgmma_control")
-}
-
-fn wgmma_control(catalog: &CatalogFile, mode: WgmmaControlMode) -> &CatalogIntrinsic {
-    wgmma_controls(catalog)
-        .find(|record| {
-            record
-                .wgmma_control
-                .as_ref()
-                .is_some_and(|control| control.mode == mode)
-        })
-        .expect("complete WGMMA-control family")
-}
-
-fn wgmma_control_template(record: &CatalogIntrinsic) -> String {
-    let operand = if record
-        .wgmma_control
-        .as_ref()
-        .is_some_and(|control| control.mode == WgmmaControlMode::WaitGroup)
-    {
-        " $0"
-    } else {
-        ""
-    };
-    format!(
-        "{}.{}{operand};",
-        record.expected_ptx.mnemonic,
-        record.expected_ptx.modifiers.join(".")
-    )
-}
-
-fn tcgen05_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "tcgen05")
-}
-
-fn tcgen05_mma_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    tcgen05_intrinsics(catalog).filter(|record| {
-        record
-            .tcgen05
-            .as_ref()
-            .is_some_and(|tcgen05| tcgen05.mma.is_some())
-    })
-}
-
-fn tcgen05_non_mma_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    tcgen05_intrinsics(catalog).filter(|record| {
-        record
-            .tcgen05
-            .as_ref()
-            .is_some_and(|tcgen05| tcgen05.mma.is_none())
-    })
-}
-
-fn tcgen05_mma_form_name(form: Tcgen05MmaForm) -> &'static str {
-    match form {
-        Tcgen05MmaForm::Shared => "Shared",
-        Tcgen05MmaForm::Tensor => "Tensor",
-        Tcgen05MmaForm::TensorAshift => "TensorAshift",
-        Tcgen05MmaForm::SpShared => "SpShared",
-        Tcgen05MmaForm::SpTensor => "SpTensor",
-        Tcgen05MmaForm::SpTensorAshift => "SpTensorAshift",
-        Tcgen05MmaForm::WsShared => "WsShared",
-        Tcgen05MmaForm::WsSharedZeroColMask => "WsSharedZeroColMask",
-        Tcgen05MmaForm::WsSpShared => "WsSpShared",
-        Tcgen05MmaForm::WsSpSharedZeroColMask => "WsSpSharedZeroColMask",
-        Tcgen05MmaForm::WsSpTensor => "WsSpTensor",
-        Tcgen05MmaForm::WsSpTensorZeroColMask => "WsSpTensorZeroColMask",
-        Tcgen05MmaForm::WsTensor => "WsTensor",
-        Tcgen05MmaForm::WsTensorZeroColMask => "WsTensorZeroColMask",
-    }
-}
-
-fn tcgen05_mma_form_attr(form: Tcgen05MmaForm) -> String {
-    format!("Tcgen05MmaFormAttr::{}", tcgen05_mma_form_name(form))
-}
-
-fn tcgen05_mma_kind_attr(kind: Tcgen05MmaKind) -> &'static str {
-    match kind {
-        Tcgen05MmaKind::F16 => "Tcgen05MmaKindAttr::F16",
-        Tcgen05MmaKind::Tf32 => "Tcgen05MmaKindAttr::Tf32",
-        Tcgen05MmaKind::F8f6f4 => "Tcgen05MmaKindAttr::F8f6f4",
-        Tcgen05MmaKind::I8 => "Tcgen05MmaKindAttr::I8",
-    }
-}
-
-fn tcgen05_mma_b_usage_attr(usage: Tcgen05MmaBUsage) -> &'static str {
-    match usage {
-        Tcgen05MmaBUsage::Discard => "Tcgen05MmaBUsageAttr::Discard",
-        Tcgen05MmaBUsage::Fill => "Tcgen05MmaBUsageAttr::Fill",
-        Tcgen05MmaBUsage::Use => "Tcgen05MmaBUsageAttr::Use",
-        Tcgen05MmaBUsage::LastUse => "Tcgen05MmaBUsageAttr::LastUse",
-    }
-}
-
-fn tcgen05_mma_runtime_parameters(mma: &Tcgen05Mma) -> Vec<(&'static str, &'static str)> {
-    if mma.alias.is_some() && mma.form == Tcgen05MmaForm::WsTensor {
-        return vec![
-            ("d_tmem", "u32"),
-            ("a_tmem", "u32"),
-            ("legacy_a_desc", "u64"),
-            ("b_desc", "u64"),
-            ("idesc", "u32"),
-            ("enable_d", "bool"),
-        ];
-    }
-    let mut parameters = match mma.form {
-        Tcgen05MmaForm::Shared
-        | Tcgen05MmaForm::SpShared
-        | Tcgen05MmaForm::WsShared
-        | Tcgen05MmaForm::WsSharedZeroColMask
-        | Tcgen05MmaForm::WsSpShared
-        | Tcgen05MmaForm::WsSpSharedZeroColMask => vec![
-            ("d_tmem", "u32"),
-            ("a_desc", "u64"),
-            ("b_desc", "u64"),
-            ("idesc", "u32"),
-            ("enable_d", "bool"),
-        ],
-        Tcgen05MmaForm::Tensor
-        | Tcgen05MmaForm::TensorAshift
-        | Tcgen05MmaForm::SpTensor
-        | Tcgen05MmaForm::SpTensorAshift
-        | Tcgen05MmaForm::WsSpTensor
-        | Tcgen05MmaForm::WsSpTensorZeroColMask
-        | Tcgen05MmaForm::WsTensor
-        | Tcgen05MmaForm::WsTensorZeroColMask => vec![
-            ("d_tmem", "u32"),
-            ("a_tmem", "u32"),
-            ("b_desc", "u64"),
-            ("idesc", "u32"),
-            ("enable_d", "bool"),
-        ],
-    };
-    if matches!(
-        mma.form,
-        Tcgen05MmaForm::SpShared
-            | Tcgen05MmaForm::SpTensor
-            | Tcgen05MmaForm::SpTensorAshift
-            | Tcgen05MmaForm::WsSpShared
-            | Tcgen05MmaForm::WsSpSharedZeroColMask
-            | Tcgen05MmaForm::WsSpTensor
-            | Tcgen05MmaForm::WsSpTensorZeroColMask
-    ) {
-        parameters.push(("metadata_tmem", "u32"));
-    }
-    if matches!(
-        mma.form,
-        Tcgen05MmaForm::WsSharedZeroColMask
-            | Tcgen05MmaForm::WsSpSharedZeroColMask
-            | Tcgen05MmaForm::WsSpTensorZeroColMask
-            | Tcgen05MmaForm::WsTensorZeroColMask
-    ) {
-        parameters.push(("zero_column_mask", "u64"));
-    }
-    parameters
-}
-
-fn tcgen05_mma_selector_parameters(
-    layout: Tcgen05MmaSelectorLayout,
-) -> [(&'static str, &'static str); 3] {
-    match layout {
-        Tcgen05MmaSelectorLayout::Base { .. } => [
-            ("KIND", "kind"),
-            ("CTA_GROUP", "cta_group"),
-            ("COLLECTOR_A", "collector_a"),
-        ],
-        Tcgen05MmaSelectorLayout::WarpSpecialized { .. } => [
-            ("KIND", "kind"),
-            ("B_BUFFER", "b_buffer"),
-            ("B_USAGE", "b_usage"),
-        ],
-    }
-}
-
-fn tcgen05_mma_is_ws(form: Tcgen05MmaForm) -> bool {
-    matches!(
-        form,
-        Tcgen05MmaForm::WsShared
-            | Tcgen05MmaForm::WsSharedZeroColMask
-            | Tcgen05MmaForm::WsSpShared
-            | Tcgen05MmaForm::WsSpSharedZeroColMask
-            | Tcgen05MmaForm::WsSpTensor
-            | Tcgen05MmaForm::WsSpTensorZeroColMask
-            | Tcgen05MmaForm::WsTensor
-            | Tcgen05MmaForm::WsTensorZeroColMask
-    )
-}
-
-fn tcgen05_mma_is_sparse(form: Tcgen05MmaForm) -> bool {
-    matches!(
-        form,
-        Tcgen05MmaForm::SpShared
-            | Tcgen05MmaForm::SpTensor
-            | Tcgen05MmaForm::SpTensorAshift
-            | Tcgen05MmaForm::WsSpShared
-            | Tcgen05MmaForm::WsSpSharedZeroColMask
-            | Tcgen05MmaForm::WsSpTensor
-            | Tcgen05MmaForm::WsSpTensorZeroColMask
-    )
-}
-
-fn tcgen05_mma_is_tensor_a(form: Tcgen05MmaForm) -> bool {
-    matches!(
-        form,
-        Tcgen05MmaForm::Tensor
-            | Tcgen05MmaForm::TensorAshift
-            | Tcgen05MmaForm::SpTensor
-            | Tcgen05MmaForm::SpTensorAshift
-            | Tcgen05MmaForm::WsSpTensor
-            | Tcgen05MmaForm::WsSpTensorZeroColMask
-            | Tcgen05MmaForm::WsTensor
-            | Tcgen05MmaForm::WsTensorZeroColMask
-    )
-}
-
-fn tcgen05_mma_is_ashift(form: Tcgen05MmaForm) -> bool {
-    matches!(
-        form,
-        Tcgen05MmaForm::TensorAshift | Tcgen05MmaForm::SpTensorAshift
-    )
-}
-
-fn tcgen05_mma_has_zero_col_mask(form: Tcgen05MmaForm) -> bool {
-    matches!(
-        form,
-        Tcgen05MmaForm::WsSharedZeroColMask
-            | Tcgen05MmaForm::WsSpSharedZeroColMask
-            | Tcgen05MmaForm::WsSpTensorZeroColMask
-            | Tcgen05MmaForm::WsTensorZeroColMask
-    )
-}
-
-fn tcgen05_mma_kind_name(kind: Tcgen05MmaKind) -> &'static str {
-    match kind {
-        Tcgen05MmaKind::F16 => "f16",
-        Tcgen05MmaKind::Tf32 => "tf32",
-        Tcgen05MmaKind::F8f6f4 => "f8f6f4",
-        Tcgen05MmaKind::I8 => "i8",
-    }
-}
-
-fn tcgen05_mma_b_usage_name(usage: Tcgen05MmaBUsage) -> &'static str {
-    match usage {
-        Tcgen05MmaBUsage::Discard => "discard",
-        Tcgen05MmaBUsage::LastUse => "lastuse",
-        Tcgen05MmaBUsage::Fill => "fill",
-        Tcgen05MmaBUsage::Use => "use",
-    }
-}
-
-fn tcgen05_mma_inline_asm(
-    form: Tcgen05MmaForm,
-    kind: Tcgen05MmaKind,
-    cta_group: u8,
-    collector_a: Option<&str>,
-    b_buffer: Option<u8>,
-    b_usage: Option<Tcgen05MmaBUsage>,
-) -> (String, String) {
-    let mut instruction = "tcgen05.mma".to_owned();
-    if tcgen05_mma_is_ws(form) {
-        instruction.push_str(".ws");
-    }
-    if tcgen05_mma_is_sparse(form) {
-        instruction.push_str(".sp");
-    }
-    write!(
-        instruction,
-        ".cta_group::{cta_group}.kind::{}",
-        tcgen05_mma_kind_name(kind)
-    )
-    .unwrap();
-    if tcgen05_mma_is_ws(form) {
-        write!(
-            instruction,
-            ".collector::b{}::{}",
-            b_buffer.expect("warp-specialized B buffer"),
-            tcgen05_mma_b_usage_name(b_usage.expect("warp-specialized B usage"))
-        )
-        .unwrap();
-    } else {
-        write!(
-            instruction,
-            ".collector::a::{}",
-            collector_a.expect("base collector A usage")
-        )
-        .unwrap();
-        if tcgen05_mma_is_ashift(form) {
-            instruction.push_str(".ashift");
-        }
-    }
-
-    let a = if tcgen05_mma_is_tensor_a(form) {
-        "[$1]"
-    } else {
-        "$1"
-    };
-    write!(instruction, " [$0], {a}, $2").unwrap();
-    if tcgen05_mma_is_sparse(form) {
-        instruction.push_str(", [$5]");
-    }
-    instruction.push_str(", $3, %enable_pred");
-    if tcgen05_mma_has_zero_col_mask(form) {
-        instruction.push_str(if tcgen05_mma_is_sparse(form) {
-            ", $6"
-        } else {
-            ", $5"
-        });
-    }
-    instruction.push(';');
-
-    let template =
-        format!("{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; {instruction} }}");
-    let mut constraints = vec![
-        "r",
-        if tcgen05_mma_is_tensor_a(form) {
-            "r"
-        } else {
-            "l"
-        },
-        "l",
-        "r",
-        "r",
-    ];
-    if tcgen05_mma_is_sparse(form) {
-        constraints.push("r");
-    }
-    if tcgen05_mma_has_zero_col_mask(form) {
-        constraints.push("l");
-    }
-    constraints.push("~{memory}");
-    (template, constraints.join(","))
-}
-
-fn tcgen05_participation_doc(operation: Tcgen05Operation) -> Option<&'static str> {
-    match operation {
-        Tcgen05Operation::AllocCg2
-        | Tcgen05Operation::DeallocCg2
-        | Tcgen05Operation::RelinquishAllocPermitCg2 => Some(
-            "One full warp in each peer CTA must execute this instruction; lanes within each warp must execute uniformly with the same operands.",
-        ),
-        Tcgen05Operation::Alloc
-        | Tcgen05Operation::Dealloc
-        | Tcgen05Operation::RelinquishAllocPermit
-        | Tcgen05Operation::Ld16x256bX8Pure
-        | Tcgen05Operation::Ld16x256bPure
-        | Tcgen05Operation::LoadWait
-        | Tcgen05Operation::StoreWait => {
-            Some("One full warp must execute this instruction uniformly with the same operands.")
-        }
-        Tcgen05Operation::Commit
-        | Tcgen05Operation::CommitSharedCluster
-        | Tcgen05Operation::CommitMulticast
-        | Tcgen05Operation::ShiftDown => Some("One thread in the CTA issues this instruction."),
-        Tcgen05Operation::CommitCg2
-        | Tcgen05Operation::CommitSharedClusterCg2
-        | Tcgen05Operation::CommitMulticastCg2
-        | Tcgen05Operation::ShiftDownCg2 => Some(
-            "One thread in the CTA pair issues this instruction; the peer CTA must be active and must not have exited.",
-        ),
-        _ => None,
-    }
-}
-
-fn tcgen05_is_commit(operation: Tcgen05Operation) -> bool {
-    matches!(
-        operation,
-        Tcgen05Operation::Commit
-            | Tcgen05Operation::CommitSharedCluster
-            | Tcgen05Operation::CommitMulticast
-            | Tcgen05Operation::CommitCg2
-            | Tcgen05Operation::CommitSharedClusterCg2
-            | Tcgen05Operation::CommitMulticastCg2
-    )
-}
-
-fn tcgen05_is_multicast_commit(operation: Tcgen05Operation) -> bool {
-    matches!(
-        operation,
-        Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2
-    )
-}
-
-fn tcgen05_is_shift(operation: Tcgen05Operation) -> bool {
-    matches!(
-        operation,
-        Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2
-    )
-}
-
-fn tcgen05_cp_ptx_suffix(member: Tcgen05CpMember) -> &'static str {
-    use Tcgen05CpMember::*;
-    match member {
-        M128x128bB4x16P64 => "128x128b.b8x16.b4x16_p64",
-        M128x128bB6x16P32 => "128x128b.b8x16.b6x16_p32",
-        M128x128b => "128x128b",
-        M128x256bB4x16P64 => "128x256b.b8x16.b4x16_p64",
-        M128x256bB6x16P32 => "128x256b.b8x16.b6x16_p32",
-        M32x128bWarpx4B4x16P64 => "32x128b.warpx4.b8x16.b4x16_p64",
-        M32x128bWarpx4B6x16P32 => "32x128b.warpx4.b8x16.b6x16_p32",
-        M32x128bWarpx4 => "32x128b.warpx4",
-        M4x256bB4x16P64 => "4x256b.b8x16.b4x16_p64",
-        M4x256bB6x16P32 => "4x256b.b8x16.b6x16_p32",
-        M4x256b => "4x256b",
-        M64x128bWarpx2Pair0123B4x16P64 => "64x128b.warpx2::01_23.b8x16.b4x16_p64",
-        M64x128bWarpx2Pair0123B6x16P32 => "64x128b.warpx2::01_23.b8x16.b6x16_p32",
-        M64x128bWarpx2Pair0123 => "64x128b.warpx2::01_23",
-        M64x128bWarpx2Pair0213B4x16P64 => "64x128b.warpx2::02_13.b8x16.b4x16_p64",
-        M64x128bWarpx2Pair0213B6x16P32 => "64x128b.warpx2::02_13.b8x16.b6x16_p32",
-        M64x128bWarpx2Pair0213 => "64x128b.warpx2::02_13",
-    }
-}
-
-fn tcgen05_ld_shape_label(shape: Tcgen05LdShape) -> &'static str {
-    match shape {
-        Tcgen05LdShape::M16x32bx2 => "16x32bx2",
-        Tcgen05LdShape::M16x64b => "16x64b",
-        Tcgen05LdShape::M16x128b => "16x128b",
-        Tcgen05LdShape::M16x256b => "16x256b",
-        Tcgen05LdShape::M32x32b => "32x32b",
-    }
-}
-
-fn tcgen05_ld_multiplicity_label(multiplicity: Tcgen05LdMultiplicity) -> &'static str {
-    match multiplicity {
-        Tcgen05LdMultiplicity::X1 => "x1",
-        Tcgen05LdMultiplicity::X2 => "x2",
-        Tcgen05LdMultiplicity::X4 => "x4",
-        Tcgen05LdMultiplicity::X8 => "x8",
-        Tcgen05LdMultiplicity::X16 => "x16",
-        Tcgen05LdMultiplicity::X32 => "x32",
-        Tcgen05LdMultiplicity::X64 => "x64",
-        Tcgen05LdMultiplicity::X128 => "x128",
-    }
-}
-
-fn tcgen05_ld_register_count(record: &CatalogIntrinsic) -> usize {
-    let ld = record
-        .tcgen05
-        .as_ref()
-        .and_then(|tcgen05| tcgen05.ld)
-        .expect("generated tcgen05 load identity");
-    ld.shape.register_multiplier() * ld.multiplicity.count()
-}
-
-fn tcgen05_st_register_count(record: &CatalogIntrinsic) -> usize {
-    let st = record
-        .tcgen05
-        .as_ref()
-        .and_then(|tcgen05| tcgen05.st)
-        .expect("generated tcgen05 store identity");
-    st.shape.register_multiplier() * st.multiplicity.count()
-}
-
-fn tcgen05_mma_target_matrix_is_closed(
-    target: &crate::model::CatalogTargetRequirement,
-    backend: IntrinsicBackend,
-    fixed_kind: Option<Tcgen05MmaKind>,
-) -> bool {
-    let CatalogHardwareTarget::TargetMatrix { contracts } = &target.hardware else {
-        return false;
-    };
-    let expected_kinds: Vec<&str> = fixed_kind.map_or_else(
-        || vec!["f16", "tf32", "f8f6f4", "i8"],
-        |kind| vec![tcgen05_mma_kind_name(kind)],
-    );
-    if target.minimum_ptx.to_string() != "8.6" || contracts.len() != expected_kinds.len() {
-        return false;
-    }
-    let common = match backend {
-        IntrinsicBackend::LlvmNvptx => vec![
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                "8.6",
-            ),
-            (CatalogHardwareAlternative::FamilyTarget { sm: 100 }, "8.8"),
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                "8.6",
-            ),
-            (CatalogHardwareAlternative::FamilyTarget { sm: 101 }, "8.8"),
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                "8.8",
-            ),
-            (CatalogHardwareAlternative::FamilyTarget { sm: 103 }, "8.8"),
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                "9.0",
-            ),
-            (CatalogHardwareAlternative::FamilyTarget { sm: 110 }, "9.0"),
-        ],
-        IntrinsicBackend::LibNvvm => vec![
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                "8.6",
-            ),
-            (CatalogHardwareAlternative::FamilyTarget { sm: 100 }, "8.8"),
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                "8.8",
-            ),
-            (CatalogHardwareAlternative::FamilyTarget { sm: 103 }, "8.8"),
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                "9.0",
-            ),
-            (CatalogHardwareAlternative::FamilyTarget { sm: 110 }, "9.0"),
-        ],
-    };
-    let i8 = match backend {
-        IntrinsicBackend::LlvmNvptx => vec![
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                "8.6",
-            ),
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                "8.6",
-            ),
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                "9.0",
-            ),
-        ],
-        IntrinsicBackend::LibNvvm => vec![
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                "8.6",
-            ),
-            (
-                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                "9.0",
-            ),
-        ],
-    };
-    expected_kinds.into_iter().all(|kind| {
-        let Some(contract) = contracts.iter().find(|contract| {
-            contract.selectors.len() == 1
-                && contract.selectors[0].name == "kind"
-                && contract.selectors[0].value == kind
-        }) else {
-            return false;
-        };
-        let expected = if kind == "i8" { &i8 } else { &common };
-        contract.alternatives.len() == expected.len()
-            && contract.alternatives.iter().zip(expected).all(
-                |(actual, (hardware, minimum_ptx))| {
-                    actual.hardware == *hardware && actual.minimum_ptx.to_string() == *minimum_ptx
-                },
-            )
-    })
-}
-
-fn tcgen05_mma_render_contract(
-    record: &CatalogIntrinsic,
-    tcgen05: &crate::model::Tcgen05,
-    mma: &Tcgen05Mma,
-    llvm_route: &crate::model::CatalogBackendLowering,
-    libnvvm_route: &crate::model::CatalogBackendLowering,
-) -> bool {
-    if tcgen05.operation != Tcgen05Operation::Mma
-        || tcgen05.cp.is_some()
-        || tcgen05.ld.is_some()
-        || tcgen05.st.is_some()
-        || tcgen05.source_contract != Tcgen05SourceContract::TablegenSelectionChangesPtx
-        || tcgen05.runtime_validation != RuntimeValidation::Unexecuted
-        || record.rust.module != "tcgen05"
-        || record.rust.safe
-        || record.rust.must_use
-        || record.rust.result != "()"
-        || record.dialect.op_type != "Tcgen05MmaOp"
-        || record.dialect.op_name != "nvvm.tcgen05_mma"
-        || !record.dialect.results.is_empty()
-        || record.lowering != "generated_tcgen05_mma"
-        || record.semantics.pure
-        || record.semantics.memory != "read_write"
-        || !record.semantics.convergent
-        || record.semantics.execution_scope != "thread"
-        || record.target.minimum_ptx.to_string() != "8.6"
-        || record.target.hardware != mma.llvm_target.hardware
-        || record.target.targets != "sm_100a|sm_101a|sm_103a|sm_110a"
-        || llvm_route.backend != IntrinsicBackend::LlvmNvptx
-        || llvm_route.mechanism != BackendLoweringMechanism::InlinePtx
-        || llvm_route.target != mma.llvm_target
-        || !tcgen05_mma_target_matrix_is_closed(
-            &llvm_route.target,
-            IntrinsicBackend::LlvmNvptx,
-            mma.fixed_selectors.map(|fixed| fixed.kind),
-        )
-        || libnvvm_route.backend != IntrinsicBackend::LibNvvm
-        || libnvvm_route.mechanism != BackendLoweringMechanism::InlinePtx
-        || libnvvm_route.target != mma.libnvvm_target
-        || !tcgen05_mma_target_matrix_is_closed(
-            &libnvvm_route.target,
-            IntrinsicBackend::LibNvvm,
-            mma.fixed_selectors.map(|fixed| fixed.kind),
-        )
-    {
-        return false;
-    }
-
-    let mut expected_operands = vec![
-        "i32".to_owned(),
-        if tcgen05_mma_is_tensor_a(mma.form) {
-            "i32".to_owned()
-        } else {
-            "i64".to_owned()
-        },
-        "i64".to_owned(),
-        "i32".to_owned(),
-        "i1".to_owned(),
-    ];
-    if tcgen05_mma_is_sparse(mma.form) {
-        expected_operands.push("i32".into());
-    }
-    if tcgen05_mma_has_zero_col_mask(mma.form) {
-        expected_operands.push("i64".into());
-    }
-
-    let llvm = llvm(record);
-    let representative_kind = mma
-        .fixed_selectors
-        .map_or(Tcgen05MmaKind::F16, |fixed| fixed.kind);
-    let representative_buffer = mma.fixed_selectors.map_or(0, |fixed| fixed.b_buffer);
-    let representative_usage = mma
-        .fixed_selectors
-        .map_or(Tcgen05MmaBUsage::Discard, |fixed| fixed.b_usage);
-    let representative = if tcgen05_mma_is_ws(mma.form) {
-        tcgen05_mma_inline_asm(
-            mma.form,
-            representative_kind,
-            1,
-            None,
-            Some(representative_buffer),
-            Some(representative_usage),
-        )
-    } else {
-        tcgen05_mma_inline_asm(
-            mma.form,
-            representative_kind,
-            1,
-            Some("discard"),
-            None,
-            None,
-        )
-    };
-    let instruction = representative
-        .0
-        .find("tcgen05.mma")
-        .map_or("", |start| &representative.0[start..]);
-    let head = instruction.split_whitespace().next().unwrap_or_default();
-    let mut components = head.split('.');
-    let expected_mnemonic = components.next().unwrap_or_default();
-    let expected_modifiers = components.map(str::to_owned).collect::<Vec<_>>();
-    let mut expected_ptx_operands = vec![crate::ptx::OperandPattern::Address];
-    expected_ptx_operands.push(if tcgen05_mma_is_tensor_a(mma.form) {
-        crate::ptx::OperandPattern::Address
-    } else {
-        crate::ptx::OperandPattern::Register
-    });
-    expected_ptx_operands.push(crate::ptx::OperandPattern::Register);
-    if tcgen05_mma_is_sparse(mma.form) {
-        expected_ptx_operands.push(crate::ptx::OperandPattern::Address);
-    }
-    expected_ptx_operands.extend([
-        crate::ptx::OperandPattern::Register,
-        crate::ptx::OperandPattern::Exact {
-            value: "%enable_pred".into(),
-        },
-    ]);
-    if tcgen05_mma_has_zero_col_mask(mma.form) {
-        expected_ptx_operands.push(crate::ptx::OperandPattern::Register);
-    }
-    if record.dialect.operands != expected_operands
-        || !llvm.results.is_empty()
-        || record.expected_ptx.mnemonic != expected_mnemonic
-        || record.expected_ptx.modifiers != expected_modifiers
-        || record.expected_ptx.operands != expected_ptx_operands
-    {
-        return false;
-    }
-
-    match (tcgen05.adapter, mma.alias, mma.fixed_selectors) {
-        (Tcgen05Adapter::MmaDirectSelectors, None, None) => {
-            let selector_indices = match mma.selector_layout {
-                Tcgen05MmaSelectorLayout::Base {
-                    kind_argument,
-                    cta_group_argument,
-                    collector_a_argument,
-                    collector_a_upper_exclusive,
-                } => {
-                    if collector_a_upper_exclusive
-                        != if tcgen05_mma_is_ashift(mma.form) {
-                            2
-                        } else {
-                            4
-                        }
-                    {
-                        return false;
-                    }
-                    [kind_argument, cta_group_argument, collector_a_argument]
-                }
-                Tcgen05MmaSelectorLayout::WarpSpecialized {
-                    kind_argument,
-                    b_buffer_argument,
-                    b_usage_argument,
-                } => [kind_argument, b_buffer_argument, b_usage_argument],
-            };
-            let first_selector = expected_operands.len() as u8;
-            record.rust.arguments.len() == expected_operands.len() + 3
-                && record
-                    .rust
-                    .arguments
-                    .ends_with(&["u32".into(), "u32".into(), "u32".into()])
-                && llvm.arguments.len() == expected_operands.len() + 3
-                && selector_indices == [first_selector, first_selector + 1, first_selector + 2]
-                && tcgen05_mma_is_ws(mma.form)
-                    == matches!(
-                        mma.selector_layout,
-                        Tcgen05MmaSelectorLayout::WarpSpecialized { .. }
-                    )
-        }
-        (
-            Tcgen05Adapter::MmaDirectSelectors,
-            Some(
-                Tcgen05MmaAlias::E4m3
-                | Tcgen05MmaAlias::E5m2
-                | Tcgen05MmaAlias::E2m3
-                | Tcgen05MmaAlias::E3m2
-                | Tcgen05MmaAlias::E2m1,
-            ),
-            Some(fixed),
-        ) => {
-            mma.form == Tcgen05MmaForm::Shared
-                && fixed.kind == Tcgen05MmaKind::F8f6f4
-                && fixed.b_buffer == 0
-                && fixed.b_usage == Tcgen05MmaBUsage::Discard
-                && matches!(
-                    mma.selector_layout,
-                    Tcgen05MmaSelectorLayout::Base {
-                        kind_argument: 5,
-                        cta_group_argument: 6,
-                        collector_a_argument: 7,
-                        collector_a_upper_exclusive: 4,
-                    }
-                )
-                && record.rust.arguments == ["u32", "u64", "u64", "u32", "bool"]
-                && record.dialect.operands == ["i32", "i64", "i64", "i32", "i1"]
-                && llvm.arguments.len() == 8
-        }
-        (
-            Tcgen05Adapter::MmaWsFixedSelectorsDropLegacyADescriptor,
-            Some(
-                Tcgen05MmaAlias::E4m3
-                | Tcgen05MmaAlias::E5m2
-                | Tcgen05MmaAlias::E2m3
-                | Tcgen05MmaAlias::E3m2
-                | Tcgen05MmaAlias::E2m1,
-            ),
-            Some(fixed),
-        ) => {
-            mma.form == Tcgen05MmaForm::WsTensor
-                && fixed.kind == Tcgen05MmaKind::F8f6f4
-                && fixed.b_buffer == 0
-                && fixed.b_usage == Tcgen05MmaBUsage::Discard
-                && record.rust.arguments == ["u32", "u32", "u64", "u64", "u32", "bool"]
-                && record.dialect.operands == ["i32", "i32", "i64", "i32", "i1"]
-                && llvm.arguments.len() == 8
-        }
-        _ => false,
-    }
-}
-
-fn tcgen05_render_contract(record: &CatalogIntrinsic) -> bool {
-    let Some(tcgen05) = &record.tcgen05 else {
-        return false;
-    };
-    let [llvm_route, libnvvm_route] = record.backend_lowerings.as_slice() else {
-        return false;
-    };
-    if let Some(mma) = &tcgen05.mma {
-        return tcgen05_mma_render_contract(record, tcgen05, mma, llvm_route, libnvvm_route);
-    }
-    let llvm_hardware = CatalogHardwareTarget::AnyOf {
-        alternatives: vec![
-            CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-            CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-            CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-            CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-        ],
-    };
-    let libnvvm_hardware = CatalogHardwareTarget::AnyOf {
-        alternatives: vec![
-            CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-            CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-            CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-        ],
-    };
-    if record.rust.module != "tcgen05"
-        || record.rust.must_use != (tcgen05.operation == Tcgen05Operation::Ld)
-        || record.lowering != "generated_tcgen05"
-        || !record.semantics.convergent
-        || record.semantics.execution_scope != tcgen05.operation.execution_scope()
-        || record.target.minimum_ptx.to_string() != "8.6"
-        || record.target.targets != "sm_100a|sm_101a|sm_103a|sm_110a"
-        || llvm_route.backend != IntrinsicBackend::LlvmNvptx
-        || llvm_route.mechanism != BackendLoweringMechanism::InlinePtx
-        || llvm_route.target.minimum_ptx.to_string() != "8.6"
-        || llvm_route.target.hardware != llvm_hardware
-        || libnvvm_route.backend != IntrinsicBackend::LibNvvm
-        || libnvvm_route.mechanism != BackendLoweringMechanism::InlinePtx
-        || libnvvm_route.target.minimum_ptx.to_string() != "8.6"
-        || libnvvm_route.target.hardware != libnvvm_hardware
-        || tcgen05.runtime_validation != RuntimeValidation::Unexecuted
-    {
-        return false;
-    }
-    match tcgen05.cp {
-        Some(cp) => {
-            let expected_operation = match cp.group {
-                Tcgen05CpGroup::Cg1 => Tcgen05Operation::CpSmemToTmem,
-                Tcgen05CpGroup::Cg2 => Tcgen05Operation::CpSmemToTmemCg2,
-            };
-            let group = match cp.group {
-                Tcgen05CpGroup::Cg1 => "cta_group::1",
-                Tcgen05CpGroup::Cg2 => "cta_group::2",
-            };
-            let modifiers = std::iter::once("cp")
-                .chain(std::iter::once(group))
-                .chain(tcgen05_cp_ptx_suffix(cp.member).split('.'))
-                .collect::<Vec<_>>();
-            if tcgen05.operation != expected_operation
-                || tcgen05.ld.is_some()
-                || tcgen05.st.is_some()
-                || record.semantics.pure
-                || record.semantics.memory != "read_write"
-                || record.expected_ptx.mnemonic != "tcgen05"
-                || record.expected_ptx.modifiers != modifiers
-                || record.expected_ptx.operands
-                    != [
-                        crate::ptx::OperandPattern::Address,
-                        crate::ptx::OperandPattern::Register,
-                    ]
-            {
-                return false;
-            }
-        }
-        None if !matches!(
-            tcgen05.operation,
-            Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2
-        ) => {}
-        None if matches!(
-            record.id.as_str(),
-            "tcgen05_cp_smem_to_tmem" | "tcgen05_cp_smem_to_tmem_cg2"
-        ) => {}
-        None => return false,
-    }
-    match tcgen05.ld {
-        Some(ld) => {
-            let count = tcgen05_ld_register_count(record);
-            let mut modifiers: Vec<String> = vec![
-                "ld".into(),
-                "sync".into(),
-                "aligned".into(),
-                tcgen05_ld_shape_label(ld.shape).into(),
-                tcgen05_ld_multiplicity_label(ld.multiplicity).into(),
-            ];
-            if ld.pack16 {
-                modifiers.push("pack::16b".into());
-            }
-            modifiers.push("b32".into());
-            let destination = crate::ptx::OperandPattern::RegisterList { length: count };
-            let mut operands = vec![destination, crate::ptx::OperandPattern::Address];
-            if ld.shape == Tcgen05LdShape::M16x32bx2 {
-                operands.push(crate::ptx::OperandPattern::Immediate);
-            }
-            if tcgen05.operation != Tcgen05Operation::Ld
-                || tcgen05.cp.is_some()
-                || tcgen05.st.is_some()
-                || record.expected_ptx.mnemonic != "tcgen05"
-                || record.expected_ptx.modifiers != modifiers
-                || record.expected_ptx.operands != operands
-            {
-                return false;
-            }
-        }
-        None if tcgen05.operation != Tcgen05Operation::Ld => {}
-        None => return false,
-    }
-    match tcgen05.st {
-        Some(st) => {
-            let count = tcgen05_st_register_count(record);
-            let mut modifiers: Vec<String> = vec![
-                "st".into(),
-                "sync".into(),
-                "aligned".into(),
-                tcgen05_ld_shape_label(st.shape).into(),
-                tcgen05_ld_multiplicity_label(st.multiplicity).into(),
-            ];
-            if st.unpack16 {
-                modifiers.push("unpack::16b".into());
-            }
-            modifiers.push("b32".into());
-            let data = crate::ptx::OperandPattern::RegisterList { length: count };
-            let mut operands = vec![crate::ptx::OperandPattern::Address];
-            if st.shape == Tcgen05LdShape::M16x32bx2 {
-                operands.push(crate::ptx::OperandPattern::Immediate);
-            }
-            operands.push(data);
-            if tcgen05.operation != Tcgen05Operation::St
-                || tcgen05.cp.is_some()
-                || tcgen05.ld.is_some()
-                || record.expected_ptx.mnemonic != "tcgen05"
-                || record.expected_ptx.modifiers != modifiers
-                || record.expected_ptx.operands != operands
-            {
-                return false;
-            }
-        }
-        None if tcgen05.operation != Tcgen05Operation::St => {}
-        None => return false,
-    }
-    let llvm = llvm(record);
-    match (tcgen05.operation, tcgen05.adapter) {
-        (
-            Tcgen05Operation::Alloc | Tcgen05Operation::AllocCg2,
-            Tcgen05Adapter::SharedPointerColumnsToVoid,
-        ) => {
-            !record.rust.safe
-                && record.rust.arguments == ["*mut u32", "u32"]
-                && record.rust.result == "()"
-                && record.dialect.operands == ["ptr", "i32"]
-                && record.dialect.results.is_empty()
-                && llvm.arguments == ["shared_ptr", "i32"]
-                && llvm.results.is_empty()
-                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
-        }
-        (
-            Tcgen05Operation::Dealloc | Tcgen05Operation::DeallocCg2,
-            Tcgen05Adapter::TmemAddressColumnsToVoid,
-        ) => {
-            !record.rust.safe
-                && record.rust.arguments == ["u32", "u32"]
-                && record.rust.result == "()"
-                && record.dialect.operands == ["i32", "i32"]
-                && llvm.arguments == ["tmem_ptr", "i32"]
-                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
-        }
-        (
-            Tcgen05Operation::RelinquishAllocPermit
-            | Tcgen05Operation::RelinquishAllocPermitCg2
-            | Tcgen05Operation::FenceBeforeThreadSync
-            | Tcgen05Operation::FenceAfterThreadSync
-            | Tcgen05Operation::LoadWait
-            | Tcgen05Operation::StoreWait,
-            Tcgen05Adapter::NoOperands,
-        ) => {
-            record.rust.safe
-                && record.rust.arguments.is_empty()
-                && record.rust.result == "()"
-                && record.dialect.operands.is_empty()
-                && llvm.arguments.is_empty()
-                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
-        }
-        (
-            Tcgen05Operation::Commit
-            | Tcgen05Operation::CommitCg2
-            | Tcgen05Operation::CommitSharedCluster
-            | Tcgen05Operation::CommitSharedClusterCg2,
-            Tcgen05Adapter::BarrierPointerToVoid,
-        ) => {
-            !record.rust.safe
-                && record.rust.arguments == ["*mut u64"]
-                && record.rust.result == "()"
-                && record.dialect.operands == ["ptr"]
-                && llvm.arguments.len() == 1
-                && if matches!(
-                    tcgen05.operation,
-                    Tcgen05Operation::Commit | Tcgen05Operation::CommitCg2
-                ) {
-                    tcgen05.source_contract == Tcgen05SourceContract::TablegenSelectionChangesPtx
-                        && llvm.arguments == ["ptr"]
-                } else {
-                    tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
-                        && llvm.arguments == ["shared_ptr"]
-                }
-        }
-        (
-            Tcgen05Operation::MmaWsF16 | Tcgen05Operation::MmaWsBf16 | Tcgen05Operation::MmaWsTf32,
-            Tcgen05Adapter::MmaWsDropLegacyADescriptor,
-        ) => {
-            !record.rust.safe
-                && record.rust.arguments == ["u32", "u32", "u64", "u64", "u32", "bool"]
-                && record.rust.result == "()"
-                && record.dialect.operands == ["i32", "i32", "i64", "i64", "i32", "i1"]
-                && llvm.arguments
-                    == [
-                        "tmem_ptr", "tmem_ptr", "i64", "i32", "i1", "i32", "i32", "i32",
-                    ]
-                && tcgen05.source_contract == Tcgen05SourceContract::TablegenSelectionChangesPtx
-                && (tcgen05.operation != Tcgen05Operation::MmaWsBf16
-                    || (record.expected_ptx.modifiers.contains(&"kind::f16".into())
-                        && !record.expected_ptx.modifiers.contains(&"kind::bf16".into())))
-        }
-        (
-            Tcgen05Operation::MmaF16 | Tcgen05Operation::MmaF16Cg2,
-            Tcgen05Adapter::MmaInjectZeroDisableLanes,
-        ) => {
-            !record.rust.safe
-                && record.rust.arguments == ["u32", "u64", "u64", "u32", "bool"]
-                && record.rust.result == "()"
-                && record.dialect.operands == ["i32", "i64", "i64", "i32", "i1"]
-                && llvm.arguments.len() == 8
-                && tcgen05.source_contract
-                    == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
-        }
-        (
-            Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2,
-            Tcgen05Adapter::TmemDescriptorToVoid,
-        ) => {
-            !record.rust.safe
-                && record.rust.arguments == ["u32", "u64"]
-                && record.rust.result == "()"
-                && record.dialect.operands == ["i32", "i64"]
-                && llvm.arguments == ["tmem_ptr", "i64"]
-                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
-        }
-        (Tcgen05Operation::Ld16x256bX8Pure, Tcgen05Adapter::TmemToF32x32) => {
-            !record.rust.safe
-                && record.rust.arguments == ["u32"]
-                && record.rust.result == "[f32; 32]"
-                && record.dialect.operands == ["i32"]
-                && record.dialect.results == vec!["f32"; 32]
-                && llvm.arguments == ["tmem_ptr", "i1"]
-                && llvm.results == ["v32i32"]
-                && tcgen05.source_contract
-                    == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
-        }
-        (Tcgen05Operation::Ld16x256bPure, Tcgen05Adapter::TmemToF32x4) => {
-            !record.rust.safe
-                && record.rust.arguments == ["u32"]
-                && record.rust.result == "[f32; 4]"
-                && record.dialect.operands == ["i32"]
-                && record.dialect.results == ["f32", "f32", "f32", "f32"]
-                && llvm.arguments == ["tmem_ptr", "i1"]
-                && llvm.results == ["v4i32"]
-                && tcgen05.source_contract
-                    == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
-        }
-        (
-            Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2,
-            Tcgen05Adapter::BarrierPointerMaskToVoid,
-        ) => {
-            !record.rust.safe
-                && record.rust.arguments == ["*mut u64", "u16"]
-                && record.rust.result == "()"
-                && record.dialect.operands == ["ptr", "i16"]
-                && llvm.arguments == ["shared_ptr", "i16"]
-                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
-        }
-        (
-            Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2,
-            Tcgen05Adapter::TmemAddressToVoid,
-        ) => {
-            !record.rust.safe
-                && record.rust.arguments == ["u32"]
-                && record.rust.result == "()"
-                && record.dialect.operands == ["i32"]
-                && record.dialect.results.is_empty()
-                && llvm.arguments == ["tmem_ptr"]
-                && llvm.results.is_empty()
-                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
-        }
-        (
-            Tcgen05Operation::Ld,
-            Tcgen05Adapter::TmemInjectPack16ToU32Registers
-            | Tcgen05Adapter::TmemHalfSplitOffsetInjectPack16ToU32Registers,
-        ) => {
-            let count = tcgen05_ld_register_count(record);
-            let has_half_split_offset =
-                tcgen05.adapter == Tcgen05Adapter::TmemHalfSplitOffsetInjectPack16ToU32Registers;
-            let rust_result = if count == 1 {
-                "u32".into()
-            } else {
-                format!("[u32; {count}]")
-            };
-            let llvm_result = if count == 1 {
-                "i32".into()
-            } else {
-                format!("v{count}i32")
-            };
-            !record.rust.safe
-                && record.rust.arguments
-                    == if has_half_split_offset {
-                        vec!["u32", "i64"]
-                    } else {
-                        vec!["u32"]
-                    }
-                && record.rust.result == rust_result
-                && record.dialect.operands
-                    == if has_half_split_offset {
-                        vec!["i32", "i64"]
-                    } else {
-                        vec!["i32"]
-                    }
-                && record.dialect.results == vec!["i32"; count]
-                && llvm.arguments
-                    == if has_half_split_offset {
-                        vec!["tmem_ptr", "i64", "i1"]
-                    } else {
-                        vec!["tmem_ptr", "i1"]
-                    }
-                && llvm.results == [llvm_result]
-                && !record.semantics.pure
-                && record.semantics.memory == "read"
-                && tcgen05.source_contract
-                    == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
-        }
-        (
-            Tcgen05Operation::St,
-            Tcgen05Adapter::TmemU32RegistersInjectUnpack16ToVoid
-            | Tcgen05Adapter::TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid,
-        ) => {
-            let count = tcgen05_st_register_count(record);
-            let has_half_split_offset = tcgen05.adapter
-                == Tcgen05Adapter::TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid;
-            let rust_data = if count == 1 {
-                "u32".into()
-            } else {
-                format!("[u32; {count}]")
-            };
-            let llvm_data = if count == 1 {
-                "i32".into()
-            } else {
-                format!("v{count}i32")
-            };
-            !record.rust.safe
-                && record.rust.arguments
-                    == if has_half_split_offset {
-                        vec!["u32", "i64", rust_data.as_str()]
-                    } else {
-                        vec!["u32", rust_data.as_str()]
-                    }
-                && record.rust.result == "()"
-                && record.dialect.operands
-                    == std::iter::once("i32")
-                        .chain(has_half_split_offset.then_some("i64"))
-                        .chain(std::iter::repeat_n("i32", count))
-                        .collect::<Vec<_>>()
-                && record.dialect.results.is_empty()
-                && llvm.arguments
-                    == if has_half_split_offset {
-                        vec!["tmem_ptr", "i64", llvm_data.as_str(), "i1"]
-                    } else {
-                        vec!["tmem_ptr", llvm_data.as_str(), "i1"]
-                    }
-                && llvm.results.is_empty()
-                && !record.semantics.pure
-                && record.semantics.memory == "write"
-                && tcgen05.source_contract
-                    == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
-        }
-        _ => false,
-    }
-}
-
-fn cp_async_copies(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "cp_async_copy")
-}
-
-fn cp_async_controls(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "cp_async_control")
-}
-
-fn cp_async_mbarriers(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "cp_async_mbarrier")
-}
-
-fn mbarrier_basics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "mbarrier_basic")
-}
-
-fn movmatrix(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "movmatrix")
-}
-
-fn movmatrix_template(record: &CatalogIntrinsic) -> String {
-    format!(
-        "{}.{} $0, $1;",
-        record.expected_ptx.mnemonic,
-        record.expected_ptx.modifiers.join(".")
-    )
-}
-
-fn mbarrier_extended(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "mbarrier_extended")
-}
-
-fn sync_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "sync")
-}
-
-fn threadfence_ptx_level(record: &CatalogIntrinsic) -> Option<&'static str> {
-    match record.id.as_str() {
-        "threadfence_block" => Some("cta"),
-        "threadfence" => Some("gl"),
-        "threadfence_system" => Some("sys"),
-        _ => None,
-    }
-}
-
-fn vote_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "vote")
-}
-
-fn active_masks(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "active_mask")
-}
-
-fn elect_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "elect")
-}
-
-fn warp_matches(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "warp_match")
-}
-
-fn warp_barriers(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "warp_barrier")
-}
-
-fn warp_shuffles(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "warp_shuffle")
-}
-
-fn dot_product_ptx(record: &CatalogIntrinsic) -> &'static str {
-    let dot = record.dot_product.as_ref().expect("dot-product record");
-    match (dot.operation, dot.signedness, dot.adapter) {
-        (
-            DotProductOperation::Dp4a,
-            DotProductSignedness::Signed,
-            DotProductAdapter::DirectThreeOperands,
-        ) => "dp4a.s32.s32 $0, $1, $2, $3;",
-        (
-            DotProductOperation::Dp4a,
-            DotProductSignedness::Unsigned,
-            DotProductAdapter::DirectThreeOperands,
-        ) => "dp4a.u32.u32 $0, $1, $2, $3;",
-        (
-            DotProductOperation::Dp2a,
-            DotProductSignedness::Signed,
-            DotProductAdapter::InsertLowHalfFalse,
-        ) => "dp2a.lo.s32.s32 $0, $1, $2, $3;",
-        (
-            DotProductOperation::Dp2a,
-            DotProductSignedness::Unsigned,
-            DotProductAdapter::InsertLowHalfFalse,
-        ) => "dp2a.lo.u32.u32 $0, $1, $2, $3;",
-        combination => panic!("unsupported generated dot-product recipe {combination:?}"),
-    }
-}
-
-fn integer_minmaxes(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
-    catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "integer_minmax")
-}
-
-fn integer_minmax_ptx_mnemonic(record: &CatalogIntrinsic) -> &'static str {
-    let minmax = record
-        .integer_minmax
-        .as_ref()
-        .expect("integer-min/max record");
-    match (minmax.format, minmax.operation, minmax.relu) {
-        (IntegerMinMaxFormat::S32, IntegerMinMaxOperation::Min, true) => "min.relu.s32",
-        (IntegerMinMaxFormat::S32, IntegerMinMaxOperation::Max, true) => "max.relu.s32",
-        (IntegerMinMaxFormat::S16x2, IntegerMinMaxOperation::Min, false) => "min.s16x2",
-        (IntegerMinMaxFormat::S16x2, IntegerMinMaxOperation::Max, false) => "max.s16x2",
-        (IntegerMinMaxFormat::U16x2, IntegerMinMaxOperation::Min, false) => "min.u16x2",
-        (IntegerMinMaxFormat::U16x2, IntegerMinMaxOperation::Max, false) => "max.u16x2",
-        (IntegerMinMaxFormat::S16x2, IntegerMinMaxOperation::Min, true) => "min.relu.s16x2",
-        (IntegerMinMaxFormat::S16x2, IntegerMinMaxOperation::Max, true) => "max.relu.s16x2",
-        // `integer_minmax_recipe` rejects those combinations before a record
-        // can exist.
-        (IntegerMinMaxFormat::S32, _, false) | (IntegerMinMaxFormat::U16x2, _, true) => {
-            panic!("{} is outside the closed integer-min/max recipe", record.id)
-        }
-    }
-}
-
-fn packed_alu_ptx_mnemonic(record: &CatalogIntrinsic) -> &'static str {
-    let packed = record.packed_alu.as_ref().expect("packed-ALU record");
-    match (packed.format, packed.operation, packed.adapter) {
-        (PackedAluFormat::Bf16x2, PackedAluOperation::Add, PackedAluAdapter::DirectPackedU32) => {
-            "add.rn.bf16x2"
-        }
-        (PackedAluFormat::Bf16x2, PackedAluOperation::Sub, PackedAluAdapter::DirectPackedU32) => {
-            "sub.rn.bf16x2"
-        }
-        (PackedAluFormat::Bf16x2, PackedAluOperation::Mul, PackedAluAdapter::DirectPackedU32) => {
-            "mul.rn.bf16x2"
-        }
-        (PackedAluFormat::Bf16x2, PackedAluOperation::Fma, PackedAluAdapter::DirectPackedU32) => {
-            "fma.rn.bf16x2"
-        }
-        (
-            PackedAluFormat::Bf16x2,
-            PackedAluOperation::FmaRelu,
-            PackedAluAdapter::DirectPackedU32,
-        ) => "fma.rn.relu.bf16x2",
-        (PackedAluFormat::Bf16x2, PackedAluOperation::Min, PackedAluAdapter::DirectPackedU32) => {
-            "min.bf16x2"
-        }
-        (PackedAluFormat::Bf16x2, PackedAluOperation::Max, PackedAluAdapter::DirectPackedU32) => {
-            "max.bf16x2"
-        }
-        (PackedAluFormat::Bf16x2, PackedAluOperation::Neg, PackedAluAdapter::DirectPackedU32) => {
-            "neg.bf16x2"
-        }
-        (PackedAluFormat::Bf16x2, PackedAluOperation::Abs, PackedAluAdapter::DirectPackedU32) => {
-            "abs.bf16x2"
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::Add, PackedAluAdapter::DirectPackedU32) => {
-            "add.rn.f16x2"
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::Sub, PackedAluAdapter::DirectPackedU32) => {
-            "sub.rn.f16x2"
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::Mul, PackedAluAdapter::DirectPackedU32) => {
-            "mul.rn.f16x2"
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::Fma, PackedAluAdapter::DirectPackedU32) => {
-            "fma.rn.f16x2"
-        }
-        (
-            PackedAluFormat::F16x2,
-            PackedAluOperation::FmaRelu,
-            PackedAluAdapter::DirectPackedU32,
-        ) => "fma.rn.relu.f16x2",
-        (PackedAluFormat::F16x2, PackedAluOperation::FmaFtz, PackedAluAdapter::DirectPackedU32) => {
-            "fma.rn.ftz.f16x2"
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::FmaSat, PackedAluAdapter::DirectPackedU32) => {
-            "fma.rn.sat.f16x2"
-        }
-        (
-            PackedAluFormat::F16x2,
-            PackedAluOperation::FmaFtzSat,
-            PackedAluAdapter::DirectPackedU32,
-        ) => "fma.rn.ftz.sat.f16x2",
-        (
-            PackedAluFormat::F16x2,
-            PackedAluOperation::FmaFtzRelu,
-            PackedAluAdapter::DirectPackedU32,
-        ) => "fma.rn.ftz.relu.f16x2",
-        (PackedAluFormat::F16x2, PackedAluOperation::Min, PackedAluAdapter::DirectPackedU32) => {
-            "min.f16x2"
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::Max, PackedAluAdapter::DirectPackedU32) => {
-            "max.f16x2"
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::Neg, PackedAluAdapter::DirectPackedU32) => {
-            "neg.f16x2"
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::Abs, PackedAluAdapter::DirectPackedU32) => {
-            "abs.f16x2"
-        }
-        (PackedAluFormat::F32x2, PackedAluOperation::Add, PackedAluAdapter::DirectPackedU64) => {
-            "add.rn.f32x2"
-        }
-        (PackedAluFormat::F32x2, PackedAluOperation::AddFtz, PackedAluAdapter::DirectPackedU64) => {
-            "add.rn.ftz.f32x2"
-        }
-        (PackedAluFormat::F32x2, PackedAluOperation::Sub, PackedAluAdapter::DirectPackedU64) => {
-            "sub.rn.f32x2"
-        }
-        (PackedAluFormat::F32x2, PackedAluOperation::SubFtz, PackedAluAdapter::DirectPackedU64) => {
-            "sub.rn.ftz.f32x2"
-        }
-        (PackedAluFormat::F32x2, PackedAluOperation::Mul, PackedAluAdapter::DirectPackedU64) => {
-            "mul.rn.f32x2"
-        }
-        (PackedAluFormat::F32x2, PackedAluOperation::MulFtz, PackedAluAdapter::DirectPackedU64) => {
-            "mul.rn.ftz.f32x2"
-        }
-        (PackedAluFormat::F32x2, PackedAluOperation::Fma, PackedAluAdapter::DirectPackedU64) => {
-            "fma.rn.f32x2"
-        }
-        (PackedAluFormat::F32x2, PackedAluOperation::FmaFtz, PackedAluAdapter::DirectPackedU64) => {
-            "fma.rn.ftz.f32x2"
-        }
-        // bf16x2 has no NVPTX selection pattern for the ftz and sat fma forms;
-        // `packed_alu_recipe` rejects those pairs before a record can exist.
-        combination => panic!("unsupported generated packed-ALU recipe {combination:?}"),
-    }
-}
-
-fn packed_conversion_destination(record: &CatalogIntrinsic) -> &'static str {
-    match record
-        .packed_conversion
-        .as_ref()
-        .expect("packed-conversion record")
-        .destination_format
-    {
-        PackedConversionDestinationFormat::Bf16x2 => "bf16x2",
-        PackedConversionDestinationFormat::E4m3x2 => "e4m3x2",
-        PackedConversionDestinationFormat::E5m2x2 => "e5m2x2",
-        PackedConversionDestinationFormat::F16x2 => "f16x2",
-    }
-}
-
-fn packed_conversion_element(record: &CatalogIntrinsic) -> &'static str {
-    match record
-        .packed_conversion
-        .as_ref()
-        .expect("packed-conversion record")
-        .destination_format
-    {
-        PackedConversionDestinationFormat::Bf16x2 => "bf16",
-        PackedConversionDestinationFormat::E4m3x2 => "e4m3",
-        PackedConversionDestinationFormat::E5m2x2 => "e5m2",
-        PackedConversionDestinationFormat::F16x2 => "f16",
-    }
-}
-
-/// Whether the conversion is one of the closed, reviewed packed-conversion
-/// recipes: scalar `f32` pairs narrowed to a packed format, `f16x2` narrowed to
-/// packed FP8, or packed FP8 widened back to `f16x2`.
-fn packed_conversion_is_closed_recipe(conversion: &crate::model::PackedConversion) -> bool {
-    use PackedConversionDestinationFormat as Dst;
-    use PackedConversionRounding as Round;
-    use PackedConversionSaturation as Sat;
-    use PackedConversionSourceFormat as Src;
-
-    let adapter_matches = conversion.adapter
-        == match conversion.source_format {
-            Src::F32x2 => PackedConversionAdapter::ReverseHighLowOperands,
-            Src::E4m3x2 | Src::E5m2x2 | Src::F16x2 => PackedConversionAdapter::Identity,
-        };
-
-    adapter_matches
-        && matches!(
-            (
-                conversion.source_format,
-                conversion.destination_format,
-                conversion.rounding,
-                conversion.saturation,
-            ),
-            (Src::F32x2, Dst::Bf16x2, Round::NearestEven, Sat::None)
-                | (Src::F32x2, Dst::Bf16x2, Round::NearestEven, Sat::Relu)
-                | (Src::F32x2, Dst::Bf16x2, Round::TowardZero, Sat::None)
-                | (Src::F32x2, Dst::F16x2, Round::NearestEven, Sat::None)
-                | (Src::F32x2, Dst::F16x2, Round::NearestEven, Sat::Relu)
-                | (Src::F32x2, Dst::F16x2, Round::TowardZero, Sat::None)
-                | (Src::F32x2, Dst::E4m3x2, Round::NearestEven, Sat::Satfinite)
-                | (
-                    Src::F32x2,
-                    Dst::E4m3x2,
-                    Round::NearestEven,
-                    Sat::SatfiniteRelu
-                )
-                | (Src::F32x2, Dst::E5m2x2, Round::NearestEven, Sat::Satfinite)
-                | (
-                    Src::F32x2,
-                    Dst::E5m2x2,
-                    Round::NearestEven,
-                    Sat::SatfiniteRelu
-                )
-                | (Src::F16x2, Dst::E4m3x2, Round::NearestEven, Sat::Satfinite)
-                | (
-                    Src::F16x2,
-                    Dst::E4m3x2,
-                    Round::NearestEven,
-                    Sat::SatfiniteRelu
-                )
-                | (Src::F16x2, Dst::E5m2x2, Round::NearestEven, Sat::Satfinite)
-                | (
-                    Src::F16x2,
-                    Dst::E5m2x2,
-                    Round::NearestEven,
-                    Sat::SatfiniteRelu
-                )
-                | (Src::E4m3x2, Dst::F16x2, Round::NearestEven, Sat::None)
-                | (Src::E4m3x2, Dst::F16x2, Round::NearestEven, Sat::Relu)
-                | (Src::E5m2x2, Dst::F16x2, Round::NearestEven, Sat::None)
-                | (Src::E5m2x2, Dst::F16x2, Round::NearestEven, Sat::Relu)
-        )
-}
-
-fn packed_conversion_source(record: &CatalogIntrinsic) -> PackedConversionSourceFormat {
-    record
-        .packed_conversion
-        .as_ref()
-        .expect("packed-conversion record")
-        .source_format
-}
-
-/// Register width of a single packed source operand.
-fn packed_conversion_source_width(record: &CatalogIntrinsic) -> u32 {
-    match packed_conversion_source(record) {
-        PackedConversionSourceFormat::F16x2 => 32,
-        PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2 => 16,
-        PackedConversionSourceFormat::F32x2 => {
-            unreachable!("f32x2 conversions do not have a single packed source")
-        }
-    }
-}
-
-/// Rust argument types, one per source operand.
-fn packed_conversion_rust_arguments(record: &CatalogIntrinsic) -> Vec<&'static str> {
-    match packed_conversion_source(record) {
-        PackedConversionSourceFormat::F32x2 => vec!["f32", "f32"],
-        PackedConversionSourceFormat::F16x2 => vec!["u32"],
-        PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2 => vec!["u16"],
-    }
-}
-
-/// Dialect operand types, one per source operand.
-fn packed_conversion_dialect_operands(record: &CatalogIntrinsic) -> Vec<&'static str> {
-    match packed_conversion_source(record) {
-        PackedConversionSourceFormat::F32x2 => vec!["f32", "f32"],
-        PackedConversionSourceFormat::F16x2 => vec!["i32"],
-        PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2 => vec!["i16"],
-    }
-}
-
-fn packed_conversion_result_width(record: &CatalogIntrinsic) -> u32 {
-    match record
-        .packed_conversion
-        .as_ref()
-        .expect("packed-conversion record")
-        .destination_format
-    {
-        PackedConversionDestinationFormat::Bf16x2 | PackedConversionDestinationFormat::F16x2 => 32,
-        PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2 => 16,
-    }
-}
-
-fn packed_conversion_rust_type(record: &CatalogIntrinsic) -> &'static str {
-    match packed_conversion_result_width(record) {
-        16 => "u16",
-        32 => "u32",
-        _ => unreachable!("closed packed-conversion result width"),
-    }
-}
-
-fn packed_conversion_dialect_type(record: &CatalogIntrinsic) -> &'static str {
-    match packed_conversion_result_width(record) {
-        16 => "i16",
-        32 => "i32",
-        _ => unreachable!("closed packed-conversion result width"),
-    }
-}
-
-/// Inline-asm constraint string: one result register, then one per source
-/// operand. `h` is a 16-bit register, `r` a 32-bit one, and `f` an f32.
-fn packed_conversion_constraint(record: &CatalogIntrinsic) -> &'static str {
-    match (
-        packed_conversion_result_width(record),
-        packed_conversion_source(record),
-    ) {
-        (16, PackedConversionSourceFormat::F32x2) => "=h,f,f",
-        (32, PackedConversionSourceFormat::F32x2) => "=r,f,f",
-        (16, PackedConversionSourceFormat::F16x2) => "=h,r",
-        (32, PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2) => "=r,h",
-        _ => unreachable!("closed packed-conversion result width and source format"),
-    }
-}
-
-/// Whether the conversion lowers through a typed NVVM intrinsic call rather
-/// than inline PTX. Only the scalar-`f32` pair narrowed to FP8 does; see the
-/// matching predicate in `resolve.rs` for why.
-fn packed_conversion_uses_typed_nvvm(record: &CatalogIntrinsic) -> bool {
-    let conversion = record
-        .packed_conversion
-        .as_ref()
-        .expect("packed-conversion record");
-    conversion.source_format == PackedConversionSourceFormat::F32x2
-        && matches!(
-            conversion.destination_format,
-            PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2
-        )
-}
-
-fn packed_conversion_lowering_name(record: &CatalogIntrinsic) -> &'static str {
-    if packed_conversion_uses_typed_nvvm(record) {
-        "generated_packed_conversion_backend"
-    } else {
-        "generated_packed_conversion_inline_ptx"
-    }
-}
-
-fn packed_conversion_typed_llvm_name(record: &CatalogIntrinsic) -> Option<String> {
-    let route = record
-        .backend_lowerings
-        .iter()
-        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-        .expect("packed conversion has an LLVM-NVPTX route");
-    match route.mechanism {
-        BackendLoweringMechanism::TypedNvvm => Some(record.llvm_identifier()),
-        BackendLoweringMechanism::InlinePtx => None,
-    }
-}
-
-fn packed_conversion_ptx_mnemonic(record: &CatalogIntrinsic) -> String {
-    let conversion = record
-        .packed_conversion
-        .as_ref()
-        .expect("packed-conversion record");
-    debug_assert_eq!(
-        conversion.adapter,
-        match conversion.source_format {
-            PackedConversionSourceFormat::F32x2 => PackedConversionAdapter::ReverseHighLowOperands,
-            PackedConversionSourceFormat::E4m3x2
-            | PackedConversionSourceFormat::E5m2x2
-            | PackedConversionSourceFormat::F16x2 => PackedConversionAdapter::Identity,
-        }
-    );
-    let rounding = match conversion.rounding {
-        PackedConversionRounding::NearestEven => "rn",
-        PackedConversionRounding::TowardZero => "rz",
-    };
-    let saturation = match conversion.saturation {
-        PackedConversionSaturation::None => "",
-        PackedConversionSaturation::Relu => ".relu",
-        PackedConversionSaturation::Satfinite => ".satfinite",
-        PackedConversionSaturation::SatfiniteRelu => ".satfinite.relu",
-    };
-    format!(
-        "cvt.{rounding}{saturation}.{}.{}",
-        packed_conversion_destination(record),
-        conversion.source_format.ptx_token()
-    )
-}
-
-fn llvm(record: &CatalogIntrinsic) -> &CatalogLlvm {
-    record.llvm.as_ref().expect("LLVM-imported intrinsic")
-}
-
-fn source_label(record: &CatalogIntrinsic) -> String {
-    match &record.source {
-        IntrinsicSource::LlvmImported { source_record } => {
-            format!("LLVM `{}` from `{source_record}`", llvm(record).symbol)
-        }
-        IntrinsicSource::PtxNative { instruction } => {
-            format!("PTX-native `{instruction}`")
-        }
-    }
-}
-
-fn ldmatrix_attr_variants(
-    record: &CatalogIntrinsic,
-) -> (
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-) {
-    let variant = &record.ldmatrix.as_ref().expect("ldmatrix record").variant;
-    let shape = match variant.shape {
-        LdmatrixShape::M8n8 => "LdmatrixShapeAttr::M8n8",
-        LdmatrixShape::M8n16 => "LdmatrixShapeAttr::M8n16",
-        LdmatrixShape::M16n16 => "LdmatrixShapeAttr::M16n16",
-    };
-    let multiplicity = match variant.multiplicity {
-        LdmatrixMultiplicity::X1 => "LdmatrixMultiplicityAttr::X1",
-        LdmatrixMultiplicity::X2 => "LdmatrixMultiplicityAttr::X2",
-        LdmatrixMultiplicity::X4 => "LdmatrixMultiplicityAttr::X4",
-    };
-    let layout = match variant.layout {
-        LdmatrixLayout::Normal => "LdmatrixLayoutAttr::Normal",
-        LdmatrixLayout::Transposed => "LdmatrixLayoutAttr::Transposed",
-    };
-    let element = match variant.element {
-        LdmatrixElement::B16 => "LdmatrixElementAttr::B16",
-        LdmatrixElement::B8 => "LdmatrixElementAttr::B8",
-        LdmatrixElement::B8x16B4x16P64 => "LdmatrixElementAttr::B8x16B4x16P64",
-        LdmatrixElement::B8x16B6x16P32 => "LdmatrixElementAttr::B8x16B6x16P32",
-    };
-    let state_space = match variant.state_space {
-        LdmatrixStateSpace::Shared => "LdmatrixStateSpaceAttr::Shared",
-    };
-    (shape, multiplicity, layout, element, state_space)
-}
-
-fn register_mma_effective_kind(record: &CatalogIntrinsic) -> RegisterMmaKind {
-    let mma = record.register_mma.as_ref().expect("register-MMA record");
-    mma.kind.unwrap_or_else(|| {
-        if record
-            .llvm
-            .as_ref()
-            .is_some_and(|llvm| llvm.symbol.contains(".kind.f8f6f4."))
-        {
-            RegisterMmaKind::F8f6f4
-        } else {
-            RegisterMmaKind::Standard
-        }
-    })
-}
-
-fn register_mma_attr_variants(
-    record: &CatalogIntrinsic,
-) -> (
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-) {
-    let mma = record.register_mma.as_ref().expect("register-MMA record");
-    let shape = match mma.shape {
-        RegisterMmaShape::M8n8k4 => "RegisterMmaShapeAttr::M8n8k4",
-        RegisterMmaShape::M8n8k16 => "RegisterMmaShapeAttr::M8n8k16",
-        RegisterMmaShape::M8n8k32 => "RegisterMmaShapeAttr::M8n8k32",
-        RegisterMmaShape::M8n8k128 => "RegisterMmaShapeAttr::M8n8k128",
-        RegisterMmaShape::M16n8k4 => "RegisterMmaShapeAttr::M16n8k4",
-        RegisterMmaShape::M16n8k8 => "RegisterMmaShapeAttr::M16n8k8",
-        RegisterMmaShape::M16n8k16 => "RegisterMmaShapeAttr::M16n8k16",
-        RegisterMmaShape::M16n8k32 => "RegisterMmaShapeAttr::M16n8k32",
-        RegisterMmaShape::M16n8k64 => "RegisterMmaShapeAttr::M16n8k64",
-        RegisterMmaShape::M16n8k128 => "RegisterMmaShapeAttr::M16n8k128",
-        RegisterMmaShape::M16n8k256 => "RegisterMmaShapeAttr::M16n8k256",
-    };
-    let operation = match mma.operation {
-        RegisterMmaOperation::Multiply => "RegisterMmaOperationAttr::Multiply",
-        RegisterMmaOperation::AndPopc => "RegisterMmaOperationAttr::AndPopc",
-        RegisterMmaOperation::XorPopc => "RegisterMmaOperationAttr::XorPopc",
-    };
-    let kind = match register_mma_effective_kind(record) {
-        RegisterMmaKind::Standard => "RegisterMmaKindAttr::Standard",
-        RegisterMmaKind::F8f6f4 => "RegisterMmaKindAttr::F8f6f4",
-        RegisterMmaKind::Mxf8f6f4 => "RegisterMmaKindAttr::Mxf8f6f4",
-    };
-    let accumulator = match mma.accumulator {
-        RegisterMmaAccumulator::F16 => "RegisterMmaAccumulatorAttr::F16",
-        RegisterMmaAccumulator::F32 => "RegisterMmaAccumulatorAttr::F32",
-        RegisterMmaAccumulator::F64 => "RegisterMmaAccumulatorAttr::F64",
-        RegisterMmaAccumulator::S32 => "RegisterMmaAccumulatorAttr::S32",
-    };
-    let element = |element| match element {
-        RegisterMmaElement::Bf16 => "RegisterMmaElementAttr::Bf16",
-        RegisterMmaElement::E2m1 => "RegisterMmaElementAttr::E2m1",
-        RegisterMmaElement::E2m3 => "RegisterMmaElementAttr::E2m3",
-        RegisterMmaElement::E3m2 => "RegisterMmaElementAttr::E3m2",
-        RegisterMmaElement::E4m3 => "RegisterMmaElementAttr::E4m3",
-        RegisterMmaElement::E5m2 => "RegisterMmaElementAttr::E5m2",
-        RegisterMmaElement::F16 => "RegisterMmaElementAttr::F16",
-        RegisterMmaElement::Tf32 => "RegisterMmaElementAttr::Tf32",
-        RegisterMmaElement::F64 => "RegisterMmaElementAttr::F64",
-        RegisterMmaElement::B1 => "RegisterMmaElementAttr::B1",
-        RegisterMmaElement::S4 => "RegisterMmaElementAttr::S4",
-        RegisterMmaElement::U4 => "RegisterMmaElementAttr::U4",
-        RegisterMmaElement::S8 => "RegisterMmaElementAttr::S8",
-        RegisterMmaElement::U8 => "RegisterMmaElementAttr::U8",
-    };
-    let layout = |layout| match layout {
-        RegisterMmaLayout::Row => "RegisterMmaLayoutAttr::Row",
-        RegisterMmaLayout::Col => "RegisterMmaLayoutAttr::Col",
-    };
-    let overflow = match mma.overflow {
-        RegisterMmaOverflow::NotApplicable => "RegisterMmaOverflowAttr::NotApplicable",
-        RegisterMmaOverflow::Wrapping => "RegisterMmaOverflowAttr::Wrapping",
-        RegisterMmaOverflow::Satfinite => "RegisterMmaOverflowAttr::Satfinite",
-    };
-    (
-        shape,
-        operation,
-        kind,
-        accumulator,
-        element(mma.a_element),
-        element(mma.b_element),
-        layout(mma.a_layout),
-        layout(mma.b_layout),
-        overflow,
-    )
-}
-
-fn register_mma_fragment_counts(record: &CatalogIntrinsic) -> (usize, usize, usize, usize) {
-    match record.register_mma.as_ref().unwrap().adapter {
-        RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32 => (2, 2, 1, 2),
-        RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => (2, 4, 2, 2),
-        RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32 => (4, 2, 1, 4),
-        RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32 | RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32 => {
-            (4, 4, 2, 4)
-        }
-        RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => (4, 4, 2, 4),
-        RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 | RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32 => {
-            (2, 1, 1, 2)
-        }
-        RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => (4, 2, 1, 4),
-    }
-}
-
-fn register_mma_extra_operand_count(record: &CatalogIntrinsic) -> usize {
-    usize::from(
-        record.register_mma.as_ref().unwrap().adapter
-            == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-    ) * 6
-}
-
-fn expected_ptx_head(record: &CatalogIntrinsic) -> String {
-    let mut head = record.expected_ptx.mnemonic.clone();
-    for modifier in &record.expected_ptx.modifiers {
-        write!(head, ".{modifier}").unwrap();
-    }
-    head
-}
-
-fn register_list(first: usize, count: usize) -> String {
-    format!(
-        "{{{}}}",
-        (first..first + count)
-            .map(|index| format!("${index}"))
-            .collect::<Vec<_>>()
-            .join(", ")
-    )
-}
-
-fn register_mma_template(record: &CatalogIntrinsic) -> String {
-    let (c_count, a_count, b_count, d_count) = register_mma_fragment_counts(record);
-    let d = register_list(0, d_count);
-    let c = register_list(d_count, c_count);
-    let a = register_list(d_count + c_count, a_count);
-    let b = register_list(d_count + c_count + a_count, b_count);
-    if record.register_mma.as_ref().unwrap().adapter
-        == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
-    {
-        let scale_a = d_count + c_count + a_count + b_count;
-        let byte_id_a = scale_a + 1;
-        let thread_id_a = scale_a + 2;
-        let scale_b = scale_a + 3;
-        let byte_id_b = scale_a + 4;
-        let thread_id_b = scale_a + 5;
-        format!(
-            "{} {d}, {a}, {b}, {c}, ${scale_a}, {{${byte_id_a}, ${thread_id_a}}}, ${scale_b}, {{${byte_id_b}, ${thread_id_b}}};",
-            expected_ptx_head(record)
-        )
-    } else {
-        format!("{} {d}, {a}, {b}, {c};", expected_ptx_head(record))
-    }
-}
-
-fn register_mma_constraints(record: &CatalogIntrinsic) -> String {
-    let mma = record.register_mma.as_ref().unwrap();
-    let (c_count, a_count, b_count, d_count) = register_mma_fragment_counts(record);
-    let (output, c, packed) = match mma.adapter {
-        RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32 | RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => {
-            ("=r", "r", "r")
-        }
-        RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
-        | RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32
-        | RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => ("=f", "f", "r"),
-        RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 => ("=d", "d", "d"),
-        RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32
-        | RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32
-        | RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => ("=r", "r", "r"),
-    };
-    let mut constraints = std::iter::repeat_n(output, d_count)
-        .chain(std::iter::repeat_n(c, c_count))
-        .chain(std::iter::repeat_n(packed, a_count + b_count))
-        .collect::<Vec<_>>();
-    if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 {
-        constraints.extend(["r", "h", "h", "r", "h", "h"]);
-    }
-    constraints.join(",")
-}
-
-fn register_mma_result_variant(record: &CatalogIntrinsic) -> &'static str {
-    match record.register_mma.as_ref().unwrap().adapter {
-        RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32 | RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => {
-            "GeneratedMmaResultType::I32"
-        }
-        RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32 | RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32 => {
-            "GeneratedMmaResultType::F32"
-        }
-        RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => {
-            "GeneratedMmaResultType::F32"
-        }
-        RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 => "GeneratedMmaResultType::F64",
-        RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32
-        | RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32
-        | RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => "GeneratedMmaResultType::I32",
-    }
-}
-
-fn sparse_mma_fragment_counts(record: &CatalogIntrinsic) -> (usize, usize, usize, usize) {
-    match record.sparse_mma.as_ref().unwrap().adapter {
-        SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 => (2, 4, 4, 2),
-        SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32
-        | SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32 => (4, 4, 4, 4),
-        SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32 => (4, 2, 2, 4),
-    }
-}
-
-fn sparse_mma_selector_values(record: &CatalogIntrinsic) -> &'static [u32] {
-    match record.sparse_mma.as_ref().unwrap().selector {
-        SparseMmaSelector::ImmediateZeroOrOne => &[0, 1],
-        SparseMmaSelector::ImmediateZero => &[0],
-    }
-}
-
-fn sparse_mma_selector_description(record: &CatalogIntrinsic) -> &'static str {
-    match record.sparse_mma.as_ref().unwrap().selector {
-        SparseMmaSelector::ImmediateZeroOrOne => "the compile-time constant `0` or `1`",
-        SparseMmaSelector::ImmediateZero => "the compile-time constant `0`",
-    }
-}
-
-fn sparse_mma_selector_error(record: &CatalogIntrinsic) -> &'static str {
-    match record.sparse_mma.as_ref().unwrap().selector {
-        SparseMmaSelector::ImmediateZeroOrOne => {
-            "sparse MMA selector must be the compile-time constant 0 or 1"
-        }
-        SparseMmaSelector::ImmediateZero => {
-            "sparse MMA selector must be the compile-time constant 0"
-        }
-    }
-}
-
-const SPARSE_MMA_STANDARD_METADATA_RULE: &str = "Every 4-bit metadata group must encode two distinct 2-bit indices; `0x0`, `0x5`, `0xa`, and `0xf` are undefined behavior.";
-const SPARSE_MMA_ORDERED_METADATA_RULE: &str = "Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior.";
-
-fn sparse_mma_metadata_rule(mma: &SparseMma) -> &'static str {
-    match mma.metadata {
-        SparseMmaMetadata::Standard => SPARSE_MMA_STANDARD_METADATA_RULE,
-        SparseMmaMetadata::Ordered => SPARSE_MMA_ORDERED_METADATA_RULE,
-    }
-}
-
-fn sparse_mma_import_adapter(record: &CatalogIntrinsic) -> &'static str {
-    match record.sparse_mma.as_ref().unwrap().adapter {
-        SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 => {
-            "GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32"
-        }
-        SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32 => {
-            "GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32"
-        }
-        SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32 => {
-            "GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32"
-        }
-        SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32 => {
-            "GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32"
-        }
-    }
-}
-
-fn sparse_mma_attr_variants(
-    record: &CatalogIntrinsic,
-) -> (
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-    &'static str,
-) {
-    let mma = record.sparse_mma.as_ref().expect("sparse-MMA record");
-    let shape = match mma.shape {
-        SparseMmaShape::M16n8k32 => "SparseMmaShapeAttr::M16n8k32",
-        SparseMmaShape::M16n8k64 => "SparseMmaShapeAttr::M16n8k64",
-        SparseMmaShape::M16n8k128 => "SparseMmaShapeAttr::M16n8k128",
-    };
-    let accumulator = match mma.accumulator {
-        SparseMmaAccumulator::F16 => "SparseMmaAccumulatorAttr::F16",
-        SparseMmaAccumulator::F32 => "SparseMmaAccumulatorAttr::F32",
-        SparseMmaAccumulator::S32 => "SparseMmaAccumulatorAttr::S32",
-    };
-    let element = |element| match element {
-        SparseMmaElement::E2m1 => "SparseMmaElementAttr::E2m1",
-        SparseMmaElement::E2m3 => "SparseMmaElementAttr::E2m3",
-        SparseMmaElement::E3m2 => "SparseMmaElementAttr::E3m2",
-        SparseMmaElement::E4m3 => "SparseMmaElementAttr::E4m3",
-        SparseMmaElement::E5m2 => "SparseMmaElementAttr::E5m2",
-        SparseMmaElement::S4 => "SparseMmaElementAttr::S4",
-        SparseMmaElement::U4 => "SparseMmaElementAttr::U4",
-        SparseMmaElement::S8 => "SparseMmaElementAttr::S8",
-        SparseMmaElement::U8 => "SparseMmaElementAttr::U8",
-    };
-    let layout = |layout| match layout {
-        SparseMmaLayout::Row => "SparseMmaLayoutAttr::Row",
-        SparseMmaLayout::Col => "SparseMmaLayoutAttr::Col",
-    };
-    let overflow = match mma.overflow {
-        SparseMmaOverflow::NotApplicable => "SparseMmaOverflowAttr::NotApplicable",
-        SparseMmaOverflow::Wrapping => "SparseMmaOverflowAttr::Wrapping",
-        SparseMmaOverflow::Satfinite => "SparseMmaOverflowAttr::Satfinite",
-    };
-    let metadata = match mma.metadata {
-        SparseMmaMetadata::Standard => "SparseMmaMetadataAttr::Standard",
-        SparseMmaMetadata::Ordered => "SparseMmaMetadataAttr::Ordered",
-    };
-    let selector = match mma.selector {
-        SparseMmaSelector::ImmediateZeroOrOne => "SparseMmaSelectorAttr::ImmediateZeroOrOne",
-        SparseMmaSelector::ImmediateZero => "SparseMmaSelectorAttr::ImmediateZero",
-    };
-    (
-        shape,
-        accumulator,
-        element(mma.a_element),
-        element(mma.b_element),
-        layout(mma.a_layout),
-        layout(mma.b_layout),
-        overflow,
-        metadata,
-        selector,
-    )
-}
-
-fn sparse_mma_ptx_head(record: &CatalogIntrinsic) -> String {
-    let mut head = record.expected_ptx.mnemonic.clone();
-    for modifier in &record.expected_ptx.modifiers {
-        write!(head, ".{modifier}").unwrap();
-    }
-    head
-}
-
-fn sparse_mma_template(record: &CatalogIntrinsic) -> String {
-    let (c_count, a_count, b_count, d_count) = sparse_mma_fragment_counts(record);
-    let d = register_list(0, d_count);
-    let c = register_list(d_count, c_count);
-    let a = register_list(d_count + c_count, a_count);
-    let b = register_list(d_count + c_count + a_count, b_count);
-    let metadata = d_count + c_count + a_count + b_count;
-    let selector = metadata + 1;
-    format!(
-        "{} {d}, {a}, {b}, {c}, ${metadata}, ${selector};",
-        sparse_mma_ptx_head(record)
-    )
-}
-
-fn sparse_mma_constraints(record: &CatalogIntrinsic) -> String {
-    let mma = record.sparse_mma.as_ref().unwrap();
-    let (c_count, a_count, b_count, d_count) = sparse_mma_fragment_counts(record);
-    let (output, accumulator) = match mma.accumulator {
-        SparseMmaAccumulator::F16 => ("=r", "r"),
-        SparseMmaAccumulator::F32 => ("=f", "f"),
-        SparseMmaAccumulator::S32 => ("=r", "r"),
-    };
-    std::iter::repeat_n(output, d_count)
-        .chain(std::iter::repeat_n(accumulator, c_count))
-        .chain(std::iter::repeat_n("r", a_count + b_count + 1))
-        .chain(std::iter::once("n"))
-        .collect::<Vec<_>>()
-        .join(",")
-}
-
-fn sparse_mma_result_variant(record: &CatalogIntrinsic) -> &'static str {
-    match record.sparse_mma.as_ref().unwrap().accumulator {
-        SparseMmaAccumulator::F16 => "GeneratedMmaResultType::I32",
-        SparseMmaAccumulator::F32 => "GeneratedMmaResultType::F32",
-        SparseMmaAccumulator::S32 => "GeneratedMmaResultType::I32",
-    }
-}
-
-fn sparse_mma_carriers(record: &CatalogIntrinsic) -> (String, String) {
-    let mma = record.sparse_mma.as_ref().unwrap();
-    let (c_count, a_count, b_count, d_count) = sparse_mma_fragment_counts(record);
-    let accumulator = match mma.accumulator {
-        SparseMmaAccumulator::F16 => "MmaCarrier::U32",
-        SparseMmaAccumulator::F32 => "MmaCarrier::F32",
-        SparseMmaAccumulator::S32 => "MmaCarrier::I32",
-    };
-    let carrier_slice = |carriers: Vec<&str>| format!("&[{}]", carriers.join(", "));
-    let operands = carrier_slice(
-        std::iter::repeat_n(accumulator, c_count)
-            .chain(std::iter::repeat_n(
-                "MmaCarrier::U32",
-                a_count + b_count + 2,
-            ))
-            .collect(),
-    );
-    let results = carrier_slice(std::iter::repeat_n(accumulator, d_count).collect());
-    (operands, results)
-}
-
-fn intrinsic_marker(catalog: &CatalogFile, record: &CatalogIntrinsic) -> String {
-    format!("v{}:{}", catalog.intrinsic_abi, record.rust.abi_id)
-}
-
-fn hardware_target_label(target: &CatalogHardwareTarget) -> String {
-    match target {
-        CatalogHardwareTarget::All => "all".to_owned(),
-        CatalogHardwareTarget::AnyOf { alternatives } => alternatives
-            .iter()
-            .map(hardware_alternative_label)
-            .collect::<Vec<_>>()
-            .join(" or "),
-        CatalogHardwareTarget::TargetMatrix { contracts } => contracts
-            .iter()
-            .map(|contract| {
-                let selectors = contract
-                    .selectors
-                    .iter()
-                    .map(|selector| format!("{}={}", selector.name, selector.value))
-                    .collect::<Vec<_>>()
-                    .join(", ");
-                let alternatives = contract
-                    .alternatives
-                    .iter()
-                    .map(|alternative| {
-                        format!(
-                            "{} at PTX {}",
-                            hardware_alternative_label(&alternative.hardware),
-                            alternative.minimum_ptx
-                        )
-                    })
-                    .collect::<Vec<_>>()
-                    .join(" or ");
-                if selectors.is_empty() {
-                    alternatives
-                } else {
-                    format!("{alternatives} for {selectors}")
-                }
-            })
-            .collect::<Vec<_>>()
-            .join("; "),
-    }
-}
-
-fn hardware_alternative_label(alternative: &CatalogHardwareAlternative) -> String {
-    match alternative {
-        CatalogHardwareAlternative::MinimumSm { sm } => format!("sm_{sm}+"),
-        CatalogHardwareAlternative::ExactArchitecture { sm } => format!("sm_{sm}a"),
-        CatalogHardwareAlternative::FamilyTarget { sm } => format!("sm_{sm}f"),
-    }
-}
-
-fn generated_hardware_target(target: &CatalogHardwareTarget) -> String {
-    match target {
-        CatalogHardwareTarget::All => "GeneratedHardwareTarget::All".to_owned(),
-        CatalogHardwareTarget::AnyOf { alternatives } => {
-            let alternatives = alternatives
-                .iter()
-                .map(generated_hardware_alternative)
-                .collect::<Vec<_>>()
-                .join(", ");
-            format!("GeneratedHardwareTarget::AnyOf(&[{alternatives}])")
-        }
-        CatalogHardwareTarget::TargetMatrix { contracts } => {
-            let contracts = contracts
-                .iter()
-                .map(generated_target_contract)
-                .collect::<Vec<_>>()
-                .join(", ");
-            format!("GeneratedHardwareTarget::TargetMatrix {{ contracts: &[{contracts}] }}")
-        }
-    }
-}
-
-fn generated_target_contract(contract: &CatalogTargetContract) -> String {
-    let selectors = contract
-        .selectors
-        .iter()
-        .map(|selector| {
-            format!(
-                "GeneratedTargetSelectorBinding {{ name: {:?}, value: {:?} }}",
-                selector.name, selector.value
-            )
-        })
-        .collect::<Vec<_>>()
-        .join(", ");
-    let alternatives = contract
-        .alternatives
-        .iter()
-        .map(|alternative| {
-            format!(
-                "GeneratedTargetAlternative {{ minimum_ptx: GeneratedPtxVersion::from_encoded({}), hardware: {} }}",
-                alternative.minimum_ptx.encoded(),
-                generated_hardware_alternative(&alternative.hardware)
-            )
-        })
-        .collect::<Vec<_>>()
-        .join(", ");
-    format!(
-        "GeneratedTargetContract {{ selectors: &[{selectors}], alternatives: &[{alternatives}] }}"
-    )
-}
-
-fn generated_hardware_alternative(alternative: &CatalogHardwareAlternative) -> String {
-    match alternative {
-        CatalogHardwareAlternative::MinimumSm { sm } => {
-            format!("GeneratedHardwareAlternative::MinimumSm({sm})")
-        }
-        CatalogHardwareAlternative::ExactArchitecture { sm } => {
-            format!("GeneratedHardwareAlternative::ExactArchitecture({sm})")
-        }
-        CatalogHardwareAlternative::FamilyTarget { sm } => {
-            format!("GeneratedHardwareAlternative::FamilyTarget({sm})")
-        }
-    }
-}
-
-fn backend_label(backend: IntrinsicBackend) -> &'static str {
-    match backend {
-        IntrinsicBackend::LlvmNvptx => "llvm_nvptx",
-        IntrinsicBackend::LibNvvm => "lib_nvvm",
-    }
-}
-
-fn lowering_mechanism_label(mechanism: BackendLoweringMechanism) -> &'static str {
-    match mechanism {
-        BackendLoweringMechanism::TypedNvvm => "typed_nvvm",
-        BackendLoweringMechanism::InlinePtx => "inline_ptx",
-    }
-}
-
-fn evidence_stage_label(stage: EvidenceStageKind) -> &'static str {
-    match stage {
-        EvidenceStageKind::DeclarationCanonicalization => "declaration canonicalization",
-        EvidenceStageKind::BackendCodegen => "backend codegen",
-        EvidenceStageKind::DeviceLink => "device link",
-        EvidenceStageKind::PtxAssembly => "PTX assembly",
-        EvidenceStageKind::Runtime => "runtime",
-    }
-}
-
-fn render_raw_mod(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    let abi_module = format!("__cuda_oxide_intrinsic_abi_v{}", catalog.intrinsic_abi);
-    writeln!(
-        output,
-        "#[doc(hidden)]\n#[path = \"abi_v{}.rs\"]\npub mod {abi_module};\n",
-        catalog.intrinsic_abi
-    )
-    .unwrap();
-    for module in modules(catalog) {
-        writeln!(
-            output,
-            "/// Generated `{module}` intrinsic source API.\npub mod {module} {{"
-        )
-        .unwrap();
-        for record in catalog
-            .intrinsics
-            .iter()
-            .filter(|record| record.rust.module == module)
-        {
-            writeln!(
-                output,
-                "    pub use crate::{abi_module}::{} as {};",
-                record.rust.abi_id, record.rust.name
-            )
-            .unwrap();
-        }
-        output.push_str("}\n\n");
-    }
-    output.push_str("#[cfg(test)]\n#[allow(clippy::type_complexity)]\nmod tests {\n");
-    for record in &catalog.intrinsics {
-        let arguments = record.rust.arguments.join(", ");
-        writeln!(
-            output,
-            "    #[test]\n    fn public_{}_reexports_abi_{}() {{",
-            record.rust.name, record.rust.abi_id
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "        let public: {}fn({}) -> {} = super::{}::{};",
-            if record.rust.safe { "" } else { "unsafe " },
-            arguments,
-            record.rust.result,
-            record.rust.module,
-            record.rust.name
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "        let canonical: {}fn({}) -> {} = super::{abi_module}::{};",
-            if record.rust.safe { "" } else { "unsafe " },
-            arguments,
-            record.rust.result,
-            record.rust.abi_id
-        )
-        .unwrap();
-        output.push_str("        assert_eq!(public as usize, canonical as usize);\n    }\n");
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_raw_abi(catalog: &CatalogFile, hash: &str) -> Result<String> {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("//! Raw ABI functions recognized by cuda-oxide.\n\n");
-    for record in &catalog.intrinsics {
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "///").unwrap();
-        writeln!(
-            output,
-            "/// Catalog ID: `{}`. Source: {}; expects PTX `{}`.",
-            record.id,
-            source_label(record),
-            record.expected_ptx
-        )
-        .unwrap();
-        if is_blackwell_ldmatrix(record) {
-            writeln!(
-                output,
-                "/// Available on `{}` targets. Instruction floor PTX {}; the selected target may require a newer PTX version.",
-                hardware_target_label(&record.target.hardware),
-                record.target.minimum_ptx
-            )
-            .unwrap();
-        } else {
-            writeln!(
-                output,
-                "/// Available on `{}` targets from PTX {}.",
-                hardware_target_label(&record.target.hardware),
-                record.target.minimum_ptx
-            )
-            .unwrap();
-        }
-        if let Some(operation) = record.tcgen05.as_ref().map(|tcgen05| tcgen05.operation)
-            && let Some(participation) = tcgen05_participation_doc(operation)
-        {
-            writeln!(output, "/// {participation}").unwrap();
-        }
-        if record.tcgen05.is_some() {
-            output.push_str(
-                "/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n",
-            );
-        }
-        if let Some(reason) = &record.rust.safe_allowlist_reason {
-            writeln!(output, "/// Safe because {reason}").unwrap();
-        }
-        if !record.rust.safe {
-            output.push_str("///\n/// # Safety\n");
-            if let Some(ldmatrix) = &record.ldmatrix {
-                let variant = &ldmatrix.variant;
-                let contributing_lanes = variant.multiplicity.register_count() * 8;
-                let readable_bytes = if variant.shape == LdmatrixShape::M16n16 {
-                    32
-                } else {
-                    16
-                };
-                let participation = match ldmatrix.safety.participation {
-                    LdmatrixParticipation::AllWarpLanesSameInstruction => {
-                        "All 32 warp lanes must execute the same instruction."
-                    }
-                    LdmatrixParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes => {
-                        "All 32 warp lanes must execute the same instruction and qualifiers; no lane may have exited."
-                    }
-                };
-                writeln!(
-                    output,
-                    "/// {participation} PTX maps {contributing_lanes} lane-provided row addresses for this {:?} variant; addresses may alias, but each used address must be 16-byte aligned and have {readable_bytes} readable shared-memory bytes.",
-                    variant.multiplicity
-                )
-                .unwrap();
-                if matches!(
-                    ldmatrix.safety.address_contract,
-                    crate::model::LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadableWithSm75Replication
-                ) && contributing_lanes < 32
-                {
-                    output.push_str("/// For portable sm_75 behavior, otherwise-unused lanes must also carry valid addresses replicated from the contributing lanes.\n");
-                }
-                output.push_str(
-                    "/// This weak memory operation does not replace a required barrier or fence.\n",
-                );
-            } else if let Some((multiplicity, _)) = stmatrix_variant(record) {
-                let address_lanes = multiplicity.register_count() * 8;
-                writeln!(
-                    output,
-                    "/// All 32 warp lanes must execute the same instruction. The first {address_lanes} lanes must provide valid, 16-byte-aligned shared-memory row addresses."
-                )
-                .unwrap();
-                output.push_str(
-                    "/// Register operands must contain the packed b16 fragments required by the selected layout.\n/// This weak memory operation does not replace a required barrier or fence.\n",
-                );
-            } else if let Some(mma) = &record.sparse_mma {
-                let (c_count, a_count, b_count, _) = sparse_mma_fragment_counts(record);
-                output.push_str(
-                    "/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited.\n",
-                );
-                writeln!(
-                    output,
-                    "/// `_arg0`, `_arg1`, and `_arg2` hold this lane's {c_count}-register C, {a_count}-register A, and {b_count}-register B fragments; `_arg3` holds its sparse metadata."
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "/// `_arg4` must be {}.",
-                    sparse_mma_selector_description(record)
-                )
-                .unwrap();
-                output.push_str("/// The operation is register-only and is not a memory fence.\n");
-                writeln!(output, "/// {}", sparse_mma_metadata_rule(mma)).unwrap();
-                writeln!(
-                    output,
-                    "/// See the [PTX sparse MMA fragment layouts]({}).",
-                    record.target.ptx_isa_url
-                )
-                .unwrap();
-                match mma.overflow {
-                    SparseMmaOverflow::NotApplicable => {}
-                    SparseMmaOverflow::Wrapping => {
-                        output.push_str(
-                            "/// Signed accumulator overflow wraps because this form omits `.satfinite`.\n",
-                        );
-                    }
-                    SparseMmaOverflow::Satfinite => output.push_str(
-                        "/// Signed accumulator overflow clamps to the finite `i32` range.\n",
-                    ),
-                }
-            } else if let Some(mma) = &record.register_mma {
-                output.push_str(
-                    "/// All 32 warp lanes must execute the same `mma.sync.aligned` instruction with the same qualifiers, and no lane may have exited.\n\
-                     /// `_arg0`, `_arg1`, and `_arg2` must contain this lane's C, A, and B fragments in the documented PTX layout.\n\
-                     /// The operation is register-only and is not a memory fence.\n",
-                );
-                if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
-                {
-                    output.push_str(
-                        "/// `_arg3` and `_arg6` contain this lane's packed A and B scale data. `_arg4`/`_arg5` and `_arg7`/`_arg8` are the corresponding byte/thread selectors.\n\
-                         /// For `scale_vec::1X`, A and B byte selectors must be in `0..=3`, the A thread selector in `0..=1`, and the B thread selector in `0..=3`; other values make the PTX operation undefined.\n",
-                    );
-                }
-                writeln!(
-                    output,
-                    "/// See the [PTX MMA fragment layouts]({}).",
-                    record.target.ptx_isa_url
-                )
-                .unwrap();
-                if mma.overflow == RegisterMmaOverflow::Wrapping {
-                    output.push_str("/// Signed accumulator overflow wraps because this form omits `.satfinite`.\n");
-                } else if mma.overflow == RegisterMmaOverflow::Satfinite {
-                    output.push_str(
-                        "/// Signed accumulator overflow clamps to the finite `i32` range.\n",
-                    );
-                }
-            } else if record.movmatrix.is_some() {
-                output.push_str(
-                    "/// All 32 warp lanes must execute the same instruction, and no lane may have exited.\n\
-                     /// `_arg0` must contain this lane's two packed b16 input elements.\n\
-                     /// The operation is register-only and is not a memory fence.\n",
-                );
-            } else if record.redux.is_some() {
-                output.push_str(
-                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `redux.sync` operation with the same qualifiers and mask.\n\
-                     /// The instruction waits for those lanes; violating this participation contract makes the PTX operation undefined.\n",
-                );
-            } else if record.warp_barrier.is_some() {
-                output.push_str(
-                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `bar.warp.sync` operation with the same mask.\n\
-                     /// On `sm_6x` and earlier, all lanes named in `mask` must execute the barrier in convergence, and no lane outside `mask` may be active when it executes.\n\
-                     /// The barrier orders memory accesses among participating lanes; violating the participation contract makes the PTX operation undefined.\n",
-                );
-            } else if record.warp_shuffle.is_some() {
-                output.push_str(
-                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `shfl.sync` operation with the same qualifiers and mask.\n\
-                     /// On `sm_6x` and earlier, all lanes named in `mask` must execute in convergence, and no lane outside `mask` may be active.\n\
-                     /// If the computed source lane is in range, it must be active and named in `mask`; otherwise the result is undefined. If PTX marks the computed source out of range, the calling lane's input is copied.\n",
-                );
-                if record
-                    .warp_shuffle
-                    .as_ref()
-                    .is_some_and(|shuffle| shuffle.value_kind == WarpShuffleValueKind::I64)
-                {
-                    output.push_str(
-                        "/// The 64-bit value is moved by two `b32` shuffles in one convergent block.\n",
-                    );
-                }
-            } else if record.warp_match.is_some() {
-                output.push_str(
-                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `match.sync` operation with the same qualifiers and mask.\n\
-                     /// Violating this participation contract makes the PTX operation undefined.\n",
-                );
-            } else if record.family == "elect" {
-                output.push_str(
-                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `elect.sync` operation with the same mask.\n\
-                     /// Violating this participation contract makes the PTX operation undefined.\n",
-                );
-            } else if record.vote.is_some() {
-                output.push_str(
-                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `vote.sync` operation with the same qualifiers and mask.\n\
-                     /// On `sm_6x` and earlier, all lanes named in `mask` must execute in convergence, and no lane outside `mask` may be active.\n\
-                     /// Violating this participation contract makes the PTX operation undefined.\n",
-                );
-            } else if record.family == "sync" {
-                output.push_str(
-                    "/// Every active thread in the CTA must reach the same barrier. Calling it from divergent control flow can deadlock the CTA.\n",
-                );
-            } else if record.family == "cluster_barrier" {
-                let barrier = record
-                    .cluster_barrier
-                    .as_ref()
-                    .expect("cluster-barrier contract");
-                output.push_str(
-                    "/// Each non-exited cluster thread must arrive exactly once before the barrier completes, then execute the matching wait.\n",
-                );
-                if barrier.aligned {
-                    output.push_str(
-                        "/// Every non-exited thread in the warp must execute this aligned instruction with identical control flow.\n",
-                    );
-                }
-                if barrier.ordering == ClusterBarrierOrdering::Relaxed {
-                    output.push_str(
-                        "/// This relaxed arrival does not publish earlier memory accesses; add the required cluster-scope fence before it.\n",
-                    );
-                }
-            } else if let Some(cluster) = &record.cluster_memory {
-                match cluster.operation {
-                    ClusterMemoryOperation::MapSharedRank => output.push_str(
-                        "/// `_arg0` must point into CTA shared memory, and `_arg1` must name a rank in the same live cluster.\n\
-                         /// The result is a cluster-shared pointer in address space 7. Dereferencing it performs a remote DSMEM access; ordinary loads and stores compile to `ld.shared::cluster` and `st.shared::cluster`. The target CTA must remain live and synchronization must make the access race-free.\n",
-                    ),
-                    ClusterMemoryOperation::ReadU32 => output.push_str(
-                        "/// `_arg0` must point to an aligned readable `u32` in CTA shared memory, and `_arg1` must name a rank in the same live cluster.\n\
-                         /// The target CTA must publish the value with the required cluster synchronization before this weak load.\n",
-                    ),
-                }
-            } else if let Some(control) = &record.wgmma_control {
-                output.push_str(
-                    "/// All four warps in the warpgroup must execute this instruction in convergence with the same control flow.\n",
-                );
-                match control.mode {
-                    WgmmaControlMode::Fence => output.push_str(
-                        "/// Issue it after register writes and before the WGMMA operations that consume those registers.\n",
-                    ),
-                    WgmmaControlMode::CommitGroup => output.push_str(
-                        "/// Issue it only after the warpgroup has submitted the WGMMA operations to commit.\n",
-                    ),
-                    WgmmaControlMode::WaitGroup => output.push_str(
-                        "/// `_arg0` must be a compile-time constant shared by the whole warpgroup.\n",
-                    ),
-                }
-            } else if let Some(tma) = &record.tma {
-                match tma.adapter {
-                    TmaAdapter::G2sPointersCoordinatesBarrierInjectDefaults
-                    | TmaAdapter::G2sPointersCoordinatesBarrierMaskInjectDefaults => output
-                        .push_str(
-                            "/// The destination and barrier must be valid shared-memory objects, and the tensor map must be a live descriptor for this dimensionality.\n\
-                             /// Keep every object alive until the asynchronous copy completes. Only the designated issuing thread may start this transfer.\n",
-                        ),
-                    TmaAdapter::S2gPointersCoordinatesInjectDefaults => output.push_str(
-                        "/// The source must name a live shared-memory tile, and the tensor map must be a live descriptor for this dimensionality.\n\
-                         /// Keep both objects alive until the committed bulk-copy group completes.\n",
-                    ),
-                    TmaAdapter::ReductionPointersCoordinatesInjectDefaults => output.push_str(
-                        "/// The source must name a live shared-memory tile, and the tensor map must describe a compatible global tensor destination for this dimensionality.\n\
-                         /// Keep both objects alive until the committed asynchronous reduction completes.\n",
-                    ),
-                    TmaAdapter::DescriptorPointer
-                    | TmaAdapter::DescriptorCoordinatesInjectDefaults
-                    | TmaAdapter::DescriptorCoordinatesCacheHintInjectFlag => output.push_str(
-                        "/// The tensor-map pointer must name a live, correctly encoded descriptor for this operation.\n",
-                    ),
-                    TmaAdapter::DescriptorAndAddressPointers
-                    | TmaAdapter::DescriptorOrdinalAndU32
-                    | TmaAdapter::DescriptorOrdinalAndU64
-                    | TmaAdapter::DescriptorAndImmediateU32
-                    | TmaAdapter::DescriptorAndRuntimeU32 => output.push_str(
-                        "/// The tensor-map pointer must name a writable, 128-byte descriptor in global memory, and every replacement value must satisfy the PTX field contract.\n",
-                    ),
-                    TmaAdapter::DescriptorPointerInjectBytes => output.push_str(
-                        "/// The tensor-map pointer must name a live 128-byte descriptor covered by the matching generic-proxy release fence.\n",
-                    ),
-                    TmaAdapter::NoOperands | TmaAdapter::CompileTimeConstantMaxPending => {}
-                }
-            } else if let Some(operation) = ExecutionControlOperation::from_catalog_id(&record.id) {
-                match operation {
-                    ExecutionControlOperation::BarrierCtaSync
-                    | ExecutionControlOperation::BarrierCtaSyncAligned
-                    | ExecutionControlOperation::BarrierCtaArrive
-                    | ExecutionControlOperation::BarrierCtaArriveAligned => output.push_str(
-                        "/// `_arg0` must identify a CTA barrier and `_arg1` must be the compatible expected thread count used by every participant.\n",
-                    ),
-                    ExecutionControlOperation::GridDependencyLaunchDependents
-                    | ExecutionControlOperation::GridDependencyWait => output.push_str(
-                        "/// The kernel launch must participate in a valid programmatic dependent-launch protocol.\n",
-                    ),
-                    ExecutionControlOperation::SetMaxNRegInc
-                    | ExecutionControlOperation::SetMaxNRegDec => output.push_str(
-                        "/// `_arg0` must be a compile-time multiple of eight in `24..=256`, and every thread in the warpgroup must execute the same operation and count.\n",
-                    ),
-                }
-            } else if let Some(bridge) = &record.cp_async_mbarrier {
-                output.push_str(
-                    "/// `_arg0` must point to a live, initialized, eight-byte-aligned mbarrier object in shared memory.\n\
-                     /// The issuing thread must have prior `cp.async` operations, and the object must remain valid until they complete.\n",
-                );
-                match bridge.operation {
-                    CpAsyncMbarrierOperation::Arrive => output.push_str(
-                        "/// This instruction increments the pending count before scheduling the asynchronous arrival; that increment must not exceed the barrier's pending-count limit.\n",
-                    ),
-                    CpAsyncMbarrierOperation::ArriveNoInc => output.push_str(
-                        "/// The barrier's initial pending count must already include the asynchronous arrival because this form does not increment it.\n",
-                    ),
-                }
-            } else if let Some(mbarrier) = &record.mbarrier_basic {
-                output.push_str(
-                    "/// `_arg0` must point to a live, eight-byte-aligned mbarrier object in shared memory.\n",
-                );
-                match mbarrier.operation {
-                    MbarrierBasicOperation::Init => output.push_str(
-                        "/// Exactly one thread may initialize the object. `_arg1` must be in `1..=0xFFFFF` and include every arrival in the phase.\n\
-                         /// The object must be uninitialized or invalidated, with no concurrent barrier operation.\n",
-                    ),
-                    MbarrierBasicOperation::Arrive => output.push_str(
-                        "/// The object must be initialized, and this arrival must be included in the current phase's expected count.\n\
-                         /// Use the returned token only with the same object and phase.\n",
-                    ),
-                    MbarrierBasicOperation::TestWait => output.push_str(
-                        "/// The object must be initialized. `_arg1` must be a token returned for the same object and phase.\n",
-                    ),
-                    MbarrierBasicOperation::Inval => output.push_str(
-                        "/// The object must be initialized and no thread or asynchronous operation may still use it.\n\
-                         /// Exactly one thread may invalidate the object.\n",
-                    ),
-                }
-            } else if let Some(mbarrier) = &record.mbarrier_extended {
-                output.push_str(
-                    "/// This is a convergent, side-effecting operation with a compiler memory clobber.\n",
-                );
-                match mbarrier.adapter {
-                    MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount => {
-                        output.push_str(
-                            "/// `_arg0` must point to a live, initialized, eight-byte-aligned mbarrier in shared memory. `_arg2` must match the asynchronous transaction bytes.\n\
-                             /// `_arg1` is retained for compatibility and is not a PTX operand.\n",
-                        );
-                    }
-                    MbarrierExtendedAdapter::RawClusterAddressToVoid => output.push_str(
-                        "/// `_arg0` must be a live remote shared-memory barrier address obtained through cluster address mapping.\n",
-                    ),
-                    MbarrierExtendedAdapter::PointerTokenToPredicate => output.push_str(
-                        "/// `_arg0` must point to a live initialized barrier. `_arg1` must be a token for that barrier and phase.\n",
-                    ),
-                    MbarrierExtendedAdapter::PointerParityToPredicate => output.push_str(
-                        "/// `_arg0` must point to a live initialized barrier. `_arg1` must be the expected phase parity.\n",
-                    ),
-                    MbarrierExtendedAdapter::ZeroOperandsToVoid => output.push_str(
-                        "/// The call site must satisfy the scope and proxy-ordering contract named by the operation.\n",
-                    ),
-                    MbarrierExtendedAdapter::NanosecondsToVoid => output.push_str(
-                        "/// `_arg0` is an approximate suspension duration; hardware may resume the thread earlier.\n",
-                    ),
-                }
-            } else if let Some(copy) = &record.cp_async_copy {
-                let bytes = copy.copy_size.bytes();
-                writeln!(
-                    output,
-                    "/// `_arg0` must point to {bytes} writable bytes in shared memory and be aligned to {bytes} bytes."
-                )
-                .unwrap();
-                if copy.source_size == CpAsyncSourceSize::Runtime {
-                    writeln!(
-                        output,
-                        "/// `_arg2` must be at most {bytes}; `_arg1` must point to that many readable bytes in global memory and be aligned to {bytes} bytes."
-                    )
-                    .unwrap();
-                } else {
-                    writeln!(
-                        output,
-                        "/// `_arg1` must point to {bytes} readable bytes in global memory and be aligned to {bytes} bytes."
-                    )
-                    .unwrap();
-                }
-                output.push_str(
-                    "/// Both ranges must remain valid, the source must remain unchanged, and the destination must not be accessed until this copy completes.\n\
-                     /// The issuing thread must use a matching `cp.async` completion operation. Synchronize threads after completion before another thread accesses the destination.\n\
-                     /// User-authored completion assembly must include a compiler memory clobber.\n",
-                );
-            } else if let Some(control) = &record.cp_async_control {
-                if control.operation == CpAsyncControlOperation::WaitGroup {
-                    output.push_str(
-                        "/// `_arg0` must be a compile-time constant. Access only destinations whose copy groups this wait completes.\n",
-                    );
-                } else if control.operation == CpAsyncControlOperation::WaitAll {
-                    output.push_str(
-                        "/// This waits only for copies issued by the executing thread. Synchronize threads before another thread accesses a completed destination.\n",
-                    );
-                } else {
-                    output.push_str(
-                        "/// This commits only copies issued by the executing thread and does not wait for completion.\n",
-                    );
-                }
-            } else if let Some(tcgen05) = &record.tcgen05 {
-                if tcgen05_is_commit(tcgen05.operation) {
-                    if tcgen05_is_multicast_commit(tcgen05.operation) {
-                        output.push_str(
-                            "/// `_arg0` must point to a live initialized cluster-shared mbarrier. `_arg1` must select valid CTA ranks in its cluster.\n",
-                        );
-                    } else {
-                        output.push_str(
-                            "/// `_arg0` must point to a live initialized mbarrier valid for this CTA-group mode.\n",
-                        );
-                    }
-                    output.push_str(
-                        "/// The same thread that issued the tracked asynchronous tcgen05 operations must issue this commit.\n",
-                    );
-                } else if tcgen05_is_shift(tcgen05.operation) {
-                    output.push_str(
-                        "/// `_arg0` must name a live tensor-memory allocation, and its lane component must be a multiple of 32.\n\
-                         /// Completion must be tracked by a matching commit from that same thread and observed through the selected mbarrier before relying on shifted data.\n",
-                    );
-                } else if tcgen05.operation == Tcgen05Operation::Ld {
-                    output.push_str(
-                        "/// `_arg0` must name a live tensor-memory allocation covering the selected tile.\n\
-                         /// All active warp lanes must execute convergently with the same address.\n\
-                         /// Complete the matching tensor-memory load wait before consuming the returned registers.\n",
-                    );
-                    if tcgen05
-                        .ld
-                        .is_some_and(|ld| ld.shape == Tcgen05LdShape::M16x32bx2)
-                    {
-                        output.push_str(
-                            "/// `_arg1` must be a compile-time constant; inline PTX encodes its low 32 bits.\n",
-                        );
-                    }
-                } else if tcgen05.operation == Tcgen05Operation::St {
-                    output.push_str(
-                        "/// `_arg0` must name a live tensor-memory allocation covering the selected tile.\n\
-                         /// All active warp lanes must execute convergently with the same address.\n\
-                         /// Complete the matching tensor-memory store wait before relying on completion or reusing the affected storage.\n",
-                    );
-                    if tcgen05
-                        .st
-                        .is_some_and(|st| st.shape == Tcgen05LdShape::M16x32bx2)
-                    {
-                        output.push_str(
-                            "/// `_arg1` must be a compile-time constant; inline PTX encodes its low 32 bits.\n",
-                        );
-                    }
-                } else {
-                    output.push_str(
-                        "/// The caller must satisfy the tcgen05 address, lifetime, and participation rules.\n",
-                    );
-                }
-            } else if record.packed_atomic.is_some() {
-                output.push_str(
-                    "/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes.\n\
-                     /// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane.\n\
-                     /// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access.\n",
-                );
-            } else if let Some(clc) = &record.clc {
-                render_clc_safety_lines(&mut output, clc.operation, ClcSafetyArgNames::RawAbi);
-            } else {
-                anyhow::bail!(
-                    "{} ({}) is unsafe but has no dedicated family safety renderer",
-                    record.id,
-                    record.family
-                );
-            }
-        }
-        if record.rust.arguments.len() > 7 {
-            output.push_str("#[allow(clippy::too_many_arguments)]\n");
-        }
-        if record.rust.must_use {
-            output.push_str("#[must_use]\n");
-        }
-        output.push_str("#[inline(never)]\n");
-        let safety = if record.rust.safe { "" } else { "unsafe " };
-        let arguments = record
-            .rust
-            .arguments
-            .iter()
-            .enumerate()
-            .map(|(index, ty)| format!("_arg{index}: {ty}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(
-            output,
-            "pub {safety}fn {}({arguments}) -> {} {{",
-            record.rust.abi_id, record.rust.result,
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{}` executed outside device compilation\")",
-            record.rust.canonical_path
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    Ok(output)
-}
-
-fn render_compat_register_mma(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::wmma` to keep public paths stable.\n\n");
-    for record in register_mmas(catalog).filter(|record| {
-        record.register_mma.as_ref().is_some_and(|mma| {
-            mma.compatibility_source == RegisterMmaCompatibilitySource::GeneratedStub
-        })
-    }) {
-        let mma = record
-            .register_mma
-            .as_ref()
-            .expect("register-MMA semantics");
-        let [path] = record.rust.compatibility_paths.as_slice() else {
-            panic!("generated register-MMA API requires one compatibility path");
-        };
-        assert_eq!(path, &format!("cuda_device::wmma::{}", record.rust.name));
-        assert!(!record.rust.safe);
-        assert!(record.rust.must_use);
-        let argument_names: &[&str] =
-            if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 {
-                &[
-                    "c",
-                    "a",
-                    "b",
-                    "scale_a",
-                    "byte_id_a",
-                    "thread_id_a",
-                    "scale_b",
-                    "byte_id_b",
-                    "thread_id_b",
-                ]
-            } else {
-                &["c", "a", "b"]
-            };
-        assert_eq!(record.rust.arguments.len(), argument_names.len());
-
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "/// Lowers to `{}`. C, A, and B are this lane's fragments in PTX register order.",
-            expected_ptx_head(record)
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "/// Requires PTX {} and `{}`.",
-            record.target.minimum_ptx,
-            hardware_target_label(&record.target.hardware)
-        )
-        .unwrap();
-        match mma.overflow {
-            RegisterMmaOverflow::Wrapping => {
-                output.push_str("/// Signed accumulator overflow wraps.\n");
-            }
-            RegisterMmaOverflow::Satfinite => {
-                output.push_str(
-                    "/// Signed accumulator overflow clamps to the finite `i32` range.\n",
-                );
-            }
-            RegisterMmaOverflow::NotApplicable => {}
-        }
-        output.push_str("///\n/// # Safety\n");
-        output.push_str(
-            "/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited.\n",
-        );
-        output.push_str(
-            "/// `c`, `a`, and `b` must contain this lane's fragments in the documented PTX layout.\n",
-        );
-        if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 {
-            output.push_str(
-                "/// `scale_a` and `scale_b` contain this lane's packed scale data.\n\
-                 /// For `scale_vec::1X`, `byte_id_a` and `byte_id_b` must be in `0..=3`, `thread_id_a` in `0..=1`, and `thread_id_b` in `0..=3`; other values make the PTX operation undefined.\n",
-            );
-        }
-        writeln!(
-            output,
-            "/// See the [PTX MMA fragment layouts]({}).",
-            record.target.ptx_isa_url
-        )
-        .unwrap();
-        output.push_str("/// This register-only operation is not a memory fence.\n");
-        if record.rust.arguments.len() > 7 {
-            output.push_str("#[allow(clippy::too_many_arguments)]\n");
-        }
-        output.push_str("#[must_use]\n#[inline(never)]\n");
-        let arguments = argument_names
-            .iter()
-            .copied()
-            .zip(&record.rust.arguments)
-            .map(|(name, ty)| format!("{name}: {ty}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(
-            output,
-            "pub unsafe fn {}({arguments}) -> {} {{",
-            record.rust.name, record.rust.result
-        )
-        .unwrap();
-        writeln!(output, "    let _ = ({});", argument_names.join(", ")).unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_ldmatrix(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::wmma` to keep public paths stable.\n\n");
-    for record in ldmatrix(catalog).filter(|record| {
-        is_blackwell_ldmatrix(record) && !record.rust.compatibility_paths.is_empty()
-    }) {
-        let [path] = record.rust.compatibility_paths.as_slice() else {
-            panic!("generated Blackwell ldmatrix API requires one compatibility path");
-        };
-        assert_eq!(path, &format!("cuda_device::wmma::{}", record.rust.name));
-        assert_eq!(record.rust.arguments, ["*const u8"]);
-        assert!(!record.rust.safe);
-        assert!(record.rust.must_use);
-
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", expected_ptx_head(record)).unwrap();
-        writeln!(
-            output,
-            "/// Requires PTX {} and `{}`.",
-            record.target.minimum_ptx,
-            hardware_target_label(&record.target.hardware)
-        )
-        .unwrap();
-        output.push_str(
-            "///\n/// # Safety\n\
-             /// All 32 lanes must execute the same instruction and qualifiers, with no exited lanes.\n\
-             /// `smem_ptr` must satisfy the lane-address mapping, alignment, and readable-byte contract documented by PTX.\n\
-             #[must_use]\n#[inline(never)]\n",
-        );
-        writeln!(
-            output,
-            "pub unsafe fn {}(smem_ptr: *const u8) -> {} {{",
-            record.rust.name, record.rust.result
-        )
-        .unwrap();
-        output.push_str("    let _ = smem_ptr;\n");
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_sparse_mma(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::wmma` to keep public paths stable.\n\n");
-    for record in sparse_mmas(catalog).filter(|record| {
-        record.sparse_mma.as_ref().is_some_and(|mma| {
-            mma.compatibility_source == SparseMmaCompatibilitySource::GeneratedStub
-        })
-    }) {
-        let mma = record.sparse_mma.as_ref().expect("sparse-MMA semantics");
-        let [path] = record.rust.compatibility_paths.as_slice() else {
-            panic!("generated sparse-MMA API requires one compatibility path");
-        };
-        assert_eq!(path, &format!("cuda_device::wmma::{}", record.rust.name));
-        assert!(matches!(
-            mma.adapter,
-            SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32
-                | SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32
-                | SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32
-                | SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32
-        ));
-
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "/// Lowers to `{}`. C, A, B, and metadata are this lane's PTX fragments.",
-            sparse_mma_ptx_head(record)
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "/// Requires PTX {} and `{}`.",
-            record.target.minimum_ptx,
-            hardware_target_label(&record.target.hardware)
-        )
-        .unwrap();
-        match mma.overflow {
-            SparseMmaOverflow::NotApplicable => {}
-            SparseMmaOverflow::Wrapping => {
-                output.push_str("/// Signed accumulator overflow wraps.\n");
-            }
-            SparseMmaOverflow::Satfinite => output
-                .push_str("/// Signed accumulator overflow clamps to the finite `i32` range.\n"),
-        }
-        output.push_str("///\n/// # Safety\n");
-        output.push_str(
-            "/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited.\n",
-        );
-        let (c_count, a_count, b_count, _) = sparse_mma_fragment_counts(record);
-        writeln!(
-            output,
-            "/// `c`, `a`, and `b` must contain this lane's {c_count}-, {a_count}-, and {b_count}-register fragments; `metadata` must contain its sparse metadata."
-        )
-        .unwrap();
-        writeln!(output, "/// {}", sparse_mma_metadata_rule(mma)).unwrap();
-        writeln!(
-            output,
-            "/// `selector` must be {}.",
-            sparse_mma_selector_description(record)
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "/// See the [PTX sparse MMA fragment layouts]({}).",
-            record.target.ptx_isa_url
-        )
-        .unwrap();
-        output.push_str("/// This register-only operation is not a memory fence.\n");
-        output.push_str("#[must_use]\n#[inline(never)]\n");
-        let arguments = ["c", "a", "b", "metadata", "selector"]
-            .into_iter()
-            .zip(&record.rust.arguments)
-            .map(|(name, ty)| format!("{name}: {ty}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(
-            output,
-            "pub unsafe fn {}({arguments}) -> {} {{",
-            record.rust.name, record.rust.result
-        )
-        .unwrap();
-        output.push_str("    let _ = (c, a, b, metadata, selector);\n");
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_sreg(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "// This file is included lexically inside `cuda_device::thread` so existing\n// DefPaths remain stable during the generated-intrinsics migration.\n\n",
-    );
-    for record in sregs(catalog) {
-        let Some(path) = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::thread::"))
-        else {
-            continue;
-        };
-        let name = path.rsplit("::").next().unwrap();
-        writeln!(
-            output,
-            "/// Compatibility spelling for `{}`.",
-            record.rust.public_path
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "/// The compiler replaces this call with {}.",
-            source_label(record)
-        )
-        .unwrap();
-        output.push_str("#[allow(non_snake_case)]\n#[inline(never)]\n");
-        let safety = if record.rust.safe { "" } else { "unsafe " };
-        writeln!(
-            output,
-            "pub {safety}fn {name}() -> {} {{",
-            record.rust.result
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_cluster_sreg(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "// This file is included inside `cuda_device::cluster`.\n// Its private leaves let public helpers compose generated reads.\n\n",
-    );
-    for record in sregs(catalog) {
-        let Some(path) = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::cluster::__"))
-        else {
-            continue;
-        };
-        let name = path.rsplit("::").next().unwrap();
-        writeln!(
-            output,
-            "/// Private compatibility spelling for `{}`.",
-            record.rust.public_path
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "/// The compiler replaces this call with `{}`.",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push_str("#[allow(non_snake_case)]\n#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub(crate) fn {name}() -> {} {{",
-            record.rust.result
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_special_register_module(
-    catalog: &CatalogFile,
-    hash: &str,
-    module: &str,
-) -> String {
-    let mut output = rust_header(catalog, hash);
-    writeln!(
-        output,
-        "// Included inside `cuda_device::{module}` to keep existing paths stable.\n"
-    )
-    .unwrap();
-    let prefix = format!("cuda_device::{module}::");
-    for record in sregs(catalog).filter(|record| record.special_register.is_some()) {
-        let Some(path) = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with(&prefix))
-        else {
-            continue;
-        };
-        let name = path.rsplit("::").next().unwrap();
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Generated from {}.", source_label(record)).unwrap();
-        output.push_str("#[inline(never)]\n");
-        let safety = if record.rust.safe { "" } else { "unsafe " };
-        writeln!(
-            output,
-            "pub {safety}fn {name}() -> {} {{",
-            record.rust.result
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_fence(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "// This file is included inside `cuda_device::fence` so existing paths stay stable.\n\n",
-    );
-    for record in sync_intrinsics(catalog).filter(|record| threadfence_ptx_level(record).is_some())
-    {
-        let Some(path) = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::fence::"))
-        else {
-            continue;
-        };
-        let name = path.rsplit("::").next().unwrap();
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "/// The compiler replaces this call with `{}`.",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push_str("#[inline(never)]\n");
-        writeln!(output, "pub fn {name}() {{").unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_dotprod(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::dotprod` to keep existing paths stable.\n\n");
-    for record in dot_products(catalog) {
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::dotprod::"))
-            .expect("dot-product compatibility path");
-        let arguments = record
-            .rust
-            .arguments
-            .iter()
-            .enumerate()
-            .map(|(index, ty)| format!("arg{index}: {ty}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let values = (0..record.rust.arguments.len())
-            .map(|index| format!("arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub fn {}({arguments}) -> {} {{",
-            record.rust.name, record.rust.result
-        )
-        .unwrap();
-        if record.rust.arguments.len() == 1 {
-            writeln!(output, "    let _ = {values};").unwrap();
-        } else {
-            writeln!(output, "    let _ = ({values});").unwrap();
-        }
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_prmt(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::prmt` to keep the public paths stable.\n\n");
-    for record in prmts(catalog) {
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::prmt::"))
-            .expect("prmt compatibility path");
-        let arguments = record
-            .rust
-            .arguments
-            .iter()
-            .enumerate()
-            .map(|(index, ty)| format!("arg{index}: {ty}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let values = (0..record.rust.arguments.len())
-            .map(|index| format!("arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("#[must_use]\n#[inline(never)]\n");
-        writeln!(output, "pub fn {}({arguments}) -> u32 {{", record.rust.name).unwrap();
-        writeln!(output, "    let _ = ({values});").unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_cluster_barrier(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::cluster` to keep public paths stable.\n\n");
-    for record in cluster_barriers(catalog) {
-        let barrier = record
-            .cluster_barrier
-            .as_ref()
-            .expect("cluster-barrier contract");
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::cluster::"))
-            .expect("cluster-barrier compatibility path");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
-        output.push_str("///\n/// # Safety\n");
-        output.push_str(
-            "/// Each non-exited cluster thread must arrive exactly once before completion, then execute the matching wait.\n",
-        );
-        if barrier.aligned {
-            output.push_str(
-                "/// Every non-exited thread in the warp must execute this aligned instruction with identical control flow.\n",
-            );
-        }
-        if barrier.ordering == ClusterBarrierOrdering::Relaxed {
-            output.push_str(
-                "/// This relaxed arrival does not publish earlier memory accesses; use the required cluster-scope fence first.\n",
-            );
-        }
-        output.push_str("#[inline(never)]\n");
-        writeln!(output, "pub unsafe fn {}() {{", record.rust.name).unwrap();
-        writeln!(output, "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")").unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_cluster_memory(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::cluster` to keep its public API stable.\n\n");
-    for record in cluster_memory(catalog) {
-        let cluster = record
-            .cluster_memory
-            .as_ref()
-            .expect("cluster-memory contract");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
-        output.push_str("///\n/// # Safety\n");
-        match cluster.operation {
-            ClusterMemoryOperation::MapSharedRank => {
-                output.push_str(
-                    "/// `local_ptr` must point into CTA shared memory, and `target_rank` must name a rank in the same live cluster.\n\
-                     /// The result is a cluster-shared pointer in address space 7. Dereferencing it performs a remote DSMEM access; the target CTA must remain live and synchronization must make the access race-free.\n",
-                );
-                output.push_str("#[must_use]\n#[inline(never)]\n");
-                output.push_str(
-                    "pub unsafe fn map_shared_rank<T>(local_ptr: *const T, target_rank: u32) -> *const T {\n\
-                             let _ = (local_ptr, target_rank);\n\
-                             unreachable!(\"map_shared_rank called outside CUDA kernel context\")\n\
-                         }\n\n",
-                );
-                output.push_str(
-                    "/// Maps a mutable CTA-shared address to another cluster rank.\n\
-                     ///\n\
-                     /// # Safety\n\
-                     /// The mapping requirements above apply. The target CTA must remain live, and remote writes must be synchronized and race-free.\n\
-                     #[must_use]\n#[inline(never)]\n\
-                     pub unsafe fn map_shared_rank_mut<T>(local_ptr: *mut T, target_rank: u32) -> *mut T {\n\
-                             let _ = (local_ptr, target_rank);\n\
-                             unreachable!(\"map_shared_rank_mut called outside CUDA kernel context\")\n\
-                     }\n\n",
-                );
-            }
-            ClusterMemoryOperation::ReadU32 => {
-                output.push_str(
-                    "/// `local_ptr` must identify an aligned readable `u32` in CTA shared memory. `target_rank` must name a rank in the same live cluster.\n\
-                     /// The target CTA must publish the value before this weak cluster load.\n",
-                );
-                output.push_str("#[must_use]\n#[inline(never)]\n");
-                output.push_str(
-                    "pub unsafe fn dsmem_read_u32(local_ptr: *const u32, target_rank: u32) -> u32 {\n\
-                             let _ = (local_ptr, target_rank);\n\
-                             unreachable!(\"dsmem_read_u32 called outside CUDA kernel context\")\n\
-                         }\n\n",
-                );
-            }
-        }
-    }
-    output
-}
-
-fn render_compat_movmatrix(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::wmma` to keep its public API stable.\n\n");
-    for record in movmatrix(catalog) {
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::wmma::"))
-            .expect("movmatrix compatibility path");
-        assert_eq!(path, &format!("cuda_device::wmma::{}", record.rust.name));
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str(
-            "///\n\
-             /// Each lane supplies two packed b16 values. The warp collectively transposes the 8x8 tile.\n\
-             /// No addressable memory is touched, but the result depends on every lane's\n\
-             /// input, so the call is modelled as reading and writing inaccessible state:\n\
-             /// two calls with equal operands are not interchangeable.\n\
-             ///\n\
-             /// # Safety\n\
-             /// All 32 warp lanes must execute the same call, and no lane may have exited.\n",
-        );
-        writeln!(
-            output,
-            "/// Requires PTX {} and `sm_75+`.",
-            record.target.minimum_ptx
-        )
-        .unwrap();
-        output.push_str("#[must_use]\n#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub unsafe fn {}(value: u32) -> u32 {{",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("    let _ = value;\n");
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_debug_control(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::debug` to keep its public API stable.\n\n");
-    for operation in [
-        DebugControlOperation::Trap,
-        DebugControlOperation::Breakpoint,
-        DebugControlOperation::Pmevent,
-    ] {
-        let record = debug_controls(catalog)
-            .find(|record| {
-                record
-                    .debug_control
-                    .as_ref()
-                    .is_some_and(|debug| debug.operation == operation)
-            })
-            .expect("complete debug-control family");
-        match operation {
-            DebugControlOperation::Trap => {
-                writeln!(output, "/// {}", record.summary).unwrap();
-                output.push_str("#[inline(never)]\npub fn trap() -> ! {\n");
-                output.push_str(
-                    "    unreachable!(\"trap called outside CUDA kernel context\")\n}\n\n",
-                );
-            }
-            DebugControlOperation::Breakpoint => {
-                writeln!(output, "/// {}", record.summary).unwrap();
-                output.push_str("#[inline(never)]\npub fn breakpoint() {\n");
-                output.push_str(
-                    "    unreachable!(\"breakpoint called outside CUDA kernel context\")\n}\n\n",
-                );
-            }
-            DebugControlOperation::Pmevent => {
-                output.push_str(
-                    r#"/// Triggers performance monitor event `N`, which must be in `0..=15`.
-#[inline(always)]
-pub fn prof_trigger<const N: u32>() {
-    __prof_trigger(N);
-}
-
-#[doc(hidden)]
-#[inline(never)]
-pub(crate) fn __prof_trigger(_event_id: u32) {
-    unreachable!("prof_trigger called outside CUDA kernel context")
-}
-
-"#,
-                );
-            }
-        }
-    }
-    output
-}
-
-fn render_compat_stmatrix(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::tcgen05` to keep public paths stable.\n\n");
-    for record in stmatrices(catalog) {
-        let (multiplicity, _) = stmatrix_variant(record).expect("stmatrix variant");
-        let count = multiplicity.register_count();
-        let name = stmatrix_compatibility_name(record);
-        let path = record
-            .rust
-            .compatibility_paths
-            .first()
-            .expect("stmatrix compatibility path");
-        let arguments = std::iter::once("smem_ptr: *mut u8".to_owned())
-            .chain((0..count).map(|index| format!("r{index}: u32")))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let values = std::iter::once("smem_ptr".to_owned())
-            .chain((0..count).map(|index| format!("r{index}")))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("///\n/// # Safety\n");
-        output.push_str(
-            "/// All warp lanes must participate. The used row addresses must be valid, shared, and 16-byte aligned.\n",
-        );
-        output.push_str("#[inline(never)]\n");
-        writeln!(output, "pub unsafe fn {name}({arguments}) {{").unwrap();
-        writeln!(output, "    let _ = ({values});").unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_clc(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::clc` to keep its public API stable.\n\n");
-    for record in clc_intrinsics(catalog) {
-        let operation = record.clc.as_ref().expect("CLC contract").operation;
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("///\n/// # Safety\n");
-        render_clc_safety_lines(&mut output, operation, ClcSafetyArgNames::Compatibility);
-        match operation {
-            ClcOperation::TryCancel | ClcOperation::TryCancelMulticast => {
-                output.push_str("#[inline(never)]\n");
-                writeln!(
-                    output,
-                    "pub unsafe fn {}(response: *mut u8, mbar: *mut Barrier) {{",
-                    record.rust.name
-                )
-                .unwrap();
-                output.push_str("    let _ = (response, mbar);\n");
-            }
-            ClcOperation::QueryIsCanceled
-            | ClcOperation::QueryGetFirstCtaidX
-            | ClcOperation::QueryGetFirstCtaidY
-            | ClcOperation::QueryGetFirstCtaidZ => {
-                output.push_str("#[inline(never)]\n");
-                writeln!(
-                    output,
-                    "pub unsafe fn {}(resp_lo: u64, resp_hi: u64) -> u32 {{",
-                    record.rust.name
-                )
-                .unwrap();
-                output.push_str("    let _ = (resp_lo, resp_hi);\n");
-            }
-        }
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_counted_barrier(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(
-        execution_control_family(catalog, "counted_barrier").count(),
-        4
-    );
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::barrier` to keep its public API stable.\n\n");
-    for record in execution_control_family(catalog, "counted_barrier") {
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str(
-            "///\n/// # Safety\n/// Every participating thread must use a compatible barrier ID and expected thread count.\n#[inline(never)]\n",
-        );
-        writeln!(
-            output,
-            "pub unsafe fn {}(barrier_id: u32, thread_count: u32) {{",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("    let _ = (barrier_id, thread_count);\n");
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_grid_dependency(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(
-        execution_control_family(catalog, "grid_dependency").count(),
-        2
-    );
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "// Included inside `cuda_device::grid` to keep its public API stable.\n\npub mod dependency {\n",
-    );
-    for (id, name) in [
-        ("grid_dependency_launch_dependents", "trigger_dependents"),
-        ("grid_dependency_wait", "wait"),
-    ] {
-        let record = execution_control_family(catalog, "grid_dependency")
-            .find(|record| record.id == id)
-            .expect("complete grid-dependency family");
-        writeln!(output, "    /// {}", record.summary).unwrap();
-        output.push_str(
-            "    ///\n    /// # Safety\n    /// The kernel launch must participate in a valid programmatic dependent-launch protocol.\n    #[inline(never)]\n",
-        );
-        writeln!(output, "    pub unsafe fn {name}() {{").unwrap();
-        writeln!(
-            output,
-            "        unreachable!(\"{name} called outside CUDA kernel context\")"
-        )
-        .unwrap();
-        output.push_str("    }\n\n");
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_compat_register_control(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(
-        execution_control_family(catalog, "register_control").count(),
-        2
-    );
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::thread` to keep its public API stable.\n\n");
-    for (id, public_name, hidden_name) in [
-        ("setmaxnreg_inc", "setmaxnreg_inc", "__setmaxnreg_inc"),
-        ("setmaxnreg_dec", "setmaxnreg_dec", "__setmaxnreg_dec"),
-    ] {
-        let record = execution_control_family(catalog, "register_control")
-            .find(|record| record.id == id)
-            .expect("complete register-control family");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str(
-            "///\n/// # Safety\n/// Every thread in the warpgroup must execute the same operation with the same count.\n#[inline(always)]\n",
-        );
-        writeln!(output, "pub unsafe fn {public_name}<const N: u32>() {{").unwrap();
-        writeln!(output, "    unsafe {{ {hidden_name}(N) }}").unwrap();
-        output.push_str("}\n\n#[doc(hidden)]\n#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub(crate) unsafe fn {hidden_name}(_register_count: u32) {{"
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"{public_name} called outside CUDA kernel context\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_tma(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::tma` to keep its public API stable.\n\n");
-    for record in tma_intrinsics(catalog) {
-        let tma = record.tma.as_ref().expect("TMA contract");
-        let operation = tma.operation;
-        writeln!(output, "/// {}", record.summary).unwrap();
-        let dimensions = tma.dimensions();
-        let is_g2s = matches!(
-            operation,
-            TmaOperation::G2sTile1d
-                | TmaOperation::G2sTile2d
-                | TmaOperation::G2sTile2dMulticast
-                | TmaOperation::G2sTile2dMulticastCg2
-                | TmaOperation::G2sTile3d
-                | TmaOperation::G2sTile4d
-                | TmaOperation::G2sTile5d
-        );
-        let is_s2g = matches!(
-            operation,
-            TmaOperation::S2gTile1d
-                | TmaOperation::S2gTile2d
-                | TmaOperation::S2gTile3d
-                | TmaOperation::S2gTile4d
-                | TmaOperation::S2gTile5d
-        );
-        let is_reduction = operation == TmaOperation::Reduce;
-        if !record.rust.safe {
-            output.push_str("///\n/// # Safety\n");
-            if is_g2s {
-                output.push_str(
-                    "/// `dst`, `tensor_map`, and `barrier` must remain valid until the copy completes.\n",
-                );
-            } else if is_s2g {
-                output.push_str(
-                    "/// `src` and `tensor_map` must remain valid until the committed copy group completes.\n",
-                );
-            } else if is_reduction {
-                output.push_str(
-                    "/// `src` must name a live shared-memory tile and `tensor_map` must describe a compatible global destination until the committed reduction completes.\n",
-                );
-            } else if matches!(
-                tma.adapter,
-                TmaAdapter::DescriptorAndAddressPointers
-                    | TmaAdapter::DescriptorOrdinalAndU32
-                    | TmaAdapter::DescriptorOrdinalAndU64
-                    | TmaAdapter::DescriptorAndImmediateU32
-                    | TmaAdapter::DescriptorAndRuntimeU32
-            ) {
-                output.push_str(
-                    "/// `tensor_map` must point to a writable, 128-byte tensor-map descriptor in global memory.\n",
-                );
-            } else {
-                output.push_str("/// `tensor_map` must point to a live tensor-map descriptor.\n");
-            }
-        }
-        output.push_str("#[inline(never)]\n");
-        if is_g2s {
-            let dimensions = dimensions.unwrap();
-            let mut arguments = vec![
-                "dst: *mut u8".to_owned(),
-                "tensor_map: *const TmaDescriptor".to_owned(),
-            ];
-            let mut values = vec!["dst".to_owned(), "tensor_map".to_owned()];
-            for index in 0..dimensions {
-                arguments.push(format!("coord{index}: i32"));
-                values.push(format!("coord{index}"));
-            }
-            arguments.push("barrier: *mut Barrier".into());
-            values.push("barrier".into());
-            if matches!(
-                operation,
-                TmaOperation::G2sTile2dMulticast | TmaOperation::G2sTile2dMulticastCg2
-            ) {
-                arguments.push("cta_mask: u16".into());
-                values.push("cta_mask".into());
-            }
-            if arguments.len() > 7 {
-                output.push_str("#[allow(clippy::too_many_arguments)]\n");
-            }
-            writeln!(
-                output,
-                "pub unsafe fn {}({}) {{",
-                record.rust.name,
-                arguments.join(", ")
-            )
-            .unwrap();
-            writeln!(output, "    let _ = ({});", values.join(", ")).unwrap();
-        } else if is_s2g || is_reduction {
-            let dimensions = dimensions.unwrap();
-            let mut arguments = vec![
-                "src: *const u8".to_owned(),
-                "tensor_map: *const TmaDescriptor".to_owned(),
-            ];
-            let mut values = vec!["src".to_owned(), "tensor_map".to_owned()];
-            for index in 0..dimensions {
-                arguments.push(format!("coord{index}: i32"));
-                values.push(format!("coord{index}"));
-            }
-            writeln!(
-                output,
-                "pub unsafe fn {}({}) {{",
-                record.rust.name,
-                arguments.join(", ")
-            )
-            .unwrap();
-            writeln!(output, "    let _ = ({});", values.join(", ")).unwrap();
-        } else if operation == TmaOperation::CommitGroup {
-            writeln!(output, "pub fn {}() {{", record.rust.name).unwrap();
-        } else if matches!(
-            operation,
-            TmaOperation::WaitGroup | TmaOperation::WaitGroupRead
-        ) {
-            writeln!(output, "pub fn {}(n: u32) {{", record.rust.name).unwrap();
-            output.push_str("    let _ = n;\n");
-        } else if operation == TmaOperation::PrefetchTensorMap {
-            writeln!(
-                output,
-                "pub unsafe fn {}(tensor_map: *const TmaDescriptor) {{",
-                record.rust.name
-            )
-            .unwrap();
-            output.push_str("    let _ = tensor_map;\n");
-        } else if let Some(coordinate_count) = operation.prefetch_coordinate_count() {
-            let mut arguments = vec!["tensor_map: *const TmaDescriptor".to_owned()];
-            let mut values = vec!["tensor_map".to_owned()];
-            for index in 0..coordinate_count {
-                arguments.push(format!("coord{index}: i32"));
-                values.push(format!("coord{index}"));
-            }
-            if operation.uses_prefetch_cache_hint() {
-                arguments.push("cache_hint: u64".into());
-                values.push("cache_hint".into());
-            }
-            writeln!(
-                output,
-                "pub unsafe fn {}({}) {{",
-                record.rust.name,
-                arguments.join(", ")
-            )
-            .unwrap();
-            writeln!(output, "    let _ = ({});", values.join(", ")).unwrap();
-        } else {
-            match tma.adapter {
-                TmaAdapter::DescriptorAndAddressPointers => {
-                    writeln!(
-                        output,
-                        "pub unsafe fn {}(tensor_map: *mut TmaDescriptor, new_address: *const u8) {{",
-                        record.rust.name
-                    )
-                    .unwrap();
-                    output.push_str("    let _ = (tensor_map, new_address);\n");
-                }
-                TmaAdapter::DescriptorOrdinalAndU32 => {
-                    writeln!(
-                        output,
-                        "pub unsafe fn {}(tensor_map: *mut TmaDescriptor, ordinal: u32, new_value: u32) {{",
-                        record.rust.name
-                    )
-                    .unwrap();
-                    output.push_str("    let _ = (tensor_map, ordinal, new_value);\n");
-                }
-                TmaAdapter::DescriptorOrdinalAndU64 => {
-                    writeln!(
-                        output,
-                        "pub unsafe fn {}(tensor_map: *mut TmaDescriptor, ordinal: u32, new_value: u64) {{",
-                        record.rust.name
-                    )
-                    .unwrap();
-                    output.push_str("    let _ = (tensor_map, ordinal, new_value);\n");
-                }
-                TmaAdapter::DescriptorAndImmediateU32 | TmaAdapter::DescriptorAndRuntimeU32 => {
-                    writeln!(
-                        output,
-                        "pub unsafe fn {}(tensor_map: *mut TmaDescriptor, new_value: u32) {{",
-                        record.rust.name
-                    )
-                    .unwrap();
-                    output.push_str("    let _ = (tensor_map, new_value);\n");
-                }
-                TmaAdapter::DescriptorPointerInjectBytes => {
-                    writeln!(
-                        output,
-                        "pub unsafe fn {}(tensor_map: *const TmaDescriptor) {{",
-                        record.rust.name
-                    )
-                    .unwrap();
-                    output.push_str("    let _ = tensor_map;\n");
-                }
-                TmaAdapter::NoOperands => {
-                    writeln!(output, "pub fn {}() {{", record.rust.name).unwrap();
-                }
-                _ => unreachable!("TMA compatibility operation category was matched"),
-            }
-        }
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output.push_str(
-        r#"/// Replace a global tensor-map address and publish it to the tensor-map proxy.
-///
-/// # Safety
-/// `tensor_map` must point to a writable, 128-byte tensor-map descriptor in
-/// global memory, and `new_address` must remain valid for every later TMA use.
-#[inline(always)]
-pub unsafe fn replace_tma_global_address(
-    tensor_map: *mut TmaDescriptor,
-    new_address: *const u8,
-) {
-    unsafe { tensormap_replace_global_address(tensor_map, new_address) };
-    fence_proxy_tensormap_generic_release_gpu();
-    unsafe { fence_proxy_tensormap_generic_acquire_gpu(tensor_map) };
-}
-"#,
-    );
-    output
-}
-
-fn render_compat_wgmma_control(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(wgmma_controls(catalog).count(), 3);
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::wgmma` to keep its public API stable.\n\n");
-
-    for mode in [WgmmaControlMode::Fence, WgmmaControlMode::CommitGroup] {
-        let record = wgmma_control(catalog, mode);
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("#[inline(never)]\n");
-        writeln!(output, "pub fn {}() {{", record.rust.name).unwrap();
-        writeln!(
-            output,
-            "    unreachable!({:?})",
-            format!("{} called outside CUDA kernel context", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-
-    let wait = wgmma_control(catalog, WgmmaControlMode::WaitGroup);
-    writeln!(output, "/// {}", wait.summary).unwrap();
-    output.push_str(
-        r#"#[inline(always)]
-pub fn wgmma_wait_group<const N: u32>() {
-    __wgmma_wait_group(N as u64);
-}
-
-#[doc(hidden)]
-#[inline(never)]
-pub(crate) fn __wgmma_wait_group(_max_pending: u64) {
-    unreachable!("wgmma_wait_group called outside CUDA kernel context")
-}
-"#,
-    );
-    output
-}
-
-fn render_compat_tcgen05_mma_record(output: &mut String, record: &CatalogIntrinsic) {
-    let mma = record
-        .tcgen05
-        .as_ref()
-        .and_then(|tcgen05| tcgen05.mma.as_ref())
-        .expect("tcgen05 MMA record");
-    let parameters = tcgen05_mma_runtime_parameters(mma);
-    let signature = parameters
-        .iter()
-        .map(|(name, ty)| format!("{name}: {ty}"))
-        .collect::<Vec<_>>()
-        .join(", ");
-    let values = parameters
-        .iter()
-        .map(|(name, _)| *name)
-        .collect::<Vec<_>>()
-        .join(", ");
-
-    writeln!(output, "/// {}", record.summary).unwrap();
-    output.push_str("/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n");
-    if mma.alias.is_some() && mma.form == Tcgen05MmaForm::WsTensor {
-        output.push_str("/// This uses kind f8f6f4 and collector b0::discard.\n");
-        output.push_str("/// `legacy_a_desc` is kept for compatibility; tensor A uses `a_tmem`.\n");
-    } else if mma.alias.is_some() {
-        output.push_str("/// This uses kind f8f6f4, CTA group 1, and collector a::discard.\n");
-    } else {
-        match mma.selector_layout {
-            Tcgen05MmaSelectorLayout::Base { .. } => {
-                output.push_str("/// `KIND` is 0=f16, 1=tf32, 2=f8f6f4, or 3=i8.\n");
-                output.push_str(
-                    "/// `CTA_GROUP` is 1 or 2. `COLLECTOR_A` is 0=discard, 1=lastuse, 2=fill, or 3=use.\n",
-                );
-            }
-            Tcgen05MmaSelectorLayout::WarpSpecialized { .. } => {
-                output.push_str("/// `KIND` is 0=f16, 1=tf32, 2=f8f6f4, or 3=i8.\n");
-                output.push_str(
-                    "/// `B_BUFFER` is 0 through 3. `B_USAGE` is 0=discard, 1=lastuse, 2=fill, or 3=use.\n",
-                );
-            }
-        }
-    }
-    output.push_str("///\n/// # Safety\n");
-    output
-        .push_str("/// Tensor-memory addresses and descriptors must be valid for this MMA form.\n");
-    if mma.alias.is_some() {
-        output.push_str("#[inline(never)]\n");
-        output.push_str("#[allow(clippy::too_many_arguments)]\n");
-        writeln!(output, "pub unsafe fn {}({signature}) {{", record.rust.name).unwrap();
-        writeln!(output, "    let _ = ({values});").unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-        return;
-    }
-
-    let selectors = tcgen05_mma_selector_parameters(mma.selector_layout);
-    let const_parameters = selectors
-        .iter()
-        .map(|(name, _)| format!("const {name}: u32"))
-        .collect::<Vec<_>>()
-        .join(", ");
-    let selector_values = selectors
-        .iter()
-        .map(|(name, _)| *name)
-        .collect::<Vec<_>>()
-        .join(", ");
-    output.push_str("#[inline(always)]\n");
-    if parameters.len() > 5 {
-        output.push_str("#[allow(clippy::too_many_arguments)]\n");
-    }
-    writeln!(
-        output,
-        "pub unsafe fn {}<{const_parameters}>({signature}) {{",
-        record.rust.name
-    )
-    .unwrap();
-    writeln!(
-        output,
-        "    unsafe {{ __{}({values}, {selector_values}) }}",
-        record.rust.name
-    )
-    .unwrap();
-    output.push_str("}\n\n#[doc(hidden)]\n#[inline(never)]\n");
-    output.push_str("#[allow(clippy::too_many_arguments)]\n");
-    let hidden_parameters = parameters
-        .iter()
-        .map(|(name, ty)| format!("_{name}: {ty}"))
-        .chain(selectors.iter().map(|(_, name)| format!("_{name}: u32")))
-        .collect::<Vec<_>>()
-        .join(", ");
-    writeln!(
-        output,
-        "pub(crate) unsafe fn __{}({hidden_parameters}) {{",
-        record.rust.name
-    )
-    .unwrap();
-    writeln!(
-        output,
-        "    unreachable!(\"{} called outside CUDA kernel context\")",
-        record.rust.name
-    )
-    .unwrap();
-    output.push_str("}\n\n");
-}
-
-fn render_compat_tcgen05(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(tcgen05_intrinsics(catalog).count(), 233);
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::tcgen05` to keep its public API stable.\n\n");
-    for record in tcgen05_intrinsics(catalog) {
-        let tcgen05 = record.tcgen05.as_ref().unwrap();
-        if tcgen05.mma.is_some() {
-            render_compat_tcgen05_mma_record(&mut output, record);
-            continue;
-        }
-        let operation = tcgen05.operation;
-        let has_half_split_offset = tcgen05
-            .ld
-            .is_some_and(|ld| ld.shape == Tcgen05LdShape::M16x32bx2)
-            || tcgen05
-                .st
-                .is_some_and(|st| st.shape == Tcgen05LdShape::M16x32bx2);
-        if has_half_split_offset {
-            let (result, data) = if operation == Tcgen05Operation::Ld {
-                let count = tcgen05_ld_register_count(record);
-                (
-                    if count == 1 {
-                        "u32".into()
-                    } else {
-                        format!("CuSimd<u32, {count}>")
-                    },
-                    None,
-                )
-            } else {
-                let count = tcgen05_st_register_count(record);
-                (
-                    "()".into(),
-                    Some(if count == 1 {
-                        "u32".into()
-                    } else {
-                        format!("CuSimd<u32, {count}>")
-                    }),
-                )
-            };
-            writeln!(output, "/// {}", record.summary).unwrap();
-            output.push_str(
-                "/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n",
-            );
-            output.push_str("///\n/// # Safety\n");
-            output.push_str(
-                "/// The tensor-memory address must be live, and the warp must execute this call uniformly.\n",
-            );
-            output.push_str("#[inline(always)]\n");
-            if let Some(data) = &data {
-                writeln!(
-                    output,
-                    "pub unsafe fn {}<const HALF_SPLIT_OFFSET: i32>(tmem_addr: u32, data: {data}) {{",
-                    record.rust.name
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "    unsafe {{ __{}(tmem_addr, HALF_SPLIT_OFFSET as i64, data) }}",
-                    record.rust.name
-                )
-                .unwrap();
-            } else {
-                writeln!(
-                    output,
-                    "pub unsafe fn {}<const HALF_SPLIT_OFFSET: i32>(tmem_addr: u32) -> {result} {{",
-                    record.rust.name
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "    unsafe {{ __{}(tmem_addr, HALF_SPLIT_OFFSET as i64) }}",
-                    record.rust.name
-                )
-                .unwrap();
-            }
-            output.push_str("}\n\n#[doc(hidden)]\n#[inline(never)]\n");
-            if let Some(data) = data {
-                writeln!(
-                    output,
-                    "pub(crate) unsafe fn __{}(_tmem_addr: u32, _half_split_offset: i64, _data: {data}) {{",
-                    record.rust.name
-                )
-                .unwrap();
-            } else {
-                writeln!(
-                    output,
-                    "pub(crate) unsafe fn __{}(_tmem_addr: u32, _half_split_offset: i64) -> {result} {{",
-                    record.rust.name
-                )
-                .unwrap();
-            }
-            writeln!(
-                output,
-                "    unreachable!(\"{} called outside CUDA kernel context\")",
-                record.rust.name
-            )
-            .unwrap();
-            output.push_str("}\n\n");
-            continue;
-        }
-        let (arguments, values): (String, String) = if operation == Tcgen05Operation::St {
-            let count = tcgen05_st_register_count(record);
-            let data = if count == 1 {
-                "u32".into()
-            } else {
-                format!("CuSimd<u32, {count}>")
-            };
-            (
-                format!("tmem_addr: u32, data: {data}"),
-                "tmem_addr, data".into(),
-            )
-        } else {
-            let (arguments, values) = match operation {
-                Tcgen05Operation::Alloc | Tcgen05Operation::AllocCg2 => {
-                    ("dst_smem: *mut u32, n_cols: u32", "dst_smem, n_cols")
-                }
-                Tcgen05Operation::Dealloc | Tcgen05Operation::DeallocCg2 => {
-                    ("tmem_addr: u32, n_cols: u32", "tmem_addr, n_cols")
-                }
-                Tcgen05Operation::RelinquishAllocPermit
-                | Tcgen05Operation::FenceBeforeThreadSync
-                | Tcgen05Operation::FenceAfterThreadSync
-                | Tcgen05Operation::LoadWait
-                | Tcgen05Operation::StoreWait
-                | Tcgen05Operation::RelinquishAllocPermitCg2 => ("", ""),
-                Tcgen05Operation::Commit
-                | Tcgen05Operation::CommitSharedCluster
-                | Tcgen05Operation::CommitCg2
-                | Tcgen05Operation::CommitSharedClusterCg2 => ("mbar: *mut u64", "mbar"),
-                Tcgen05Operation::MmaWsF16
-                | Tcgen05Operation::MmaWsBf16
-                | Tcgen05Operation::MmaWsTf32 => (
-                    "d_tmem: u32, a_tmem: u32, a_desc: u64, b_desc: u64, idesc: u32, enable_d: bool",
-                    "d_tmem, a_tmem, a_desc, b_desc, idesc, enable_d",
-                ),
-                Tcgen05Operation::MmaF16 | Tcgen05Operation::MmaF16Cg2 => (
-                    "d_tmem: u32, a_desc: u64, b_desc: u64, idesc: u32, enable_d: bool",
-                    "d_tmem, a_desc, b_desc, idesc, enable_d",
-                ),
-                Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2 => {
-                    ("tmem_addr: u32, smem_desc: u64", "tmem_addr, smem_desc")
-                }
-                Tcgen05Operation::Ld16x256bX8Pure
-                | Tcgen05Operation::Ld16x256bPure
-                | Tcgen05Operation::Ld => ("tmem_addr: u32", "tmem_addr"),
-                Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2 => {
-                    ("mbar: *mut u64, cta_mask: u16", "mbar, cta_mask")
-                }
-                Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2 => {
-                    ("tmem_addr: u32", "tmem_addr")
-                }
-                Tcgen05Operation::St => unreachable!("store handled above"),
-                Tcgen05Operation::Mma => unreachable!("generic MMA handled above"),
-            };
-            (arguments.into(), values.into())
-        };
-        let result: String = match operation {
-            Tcgen05Operation::Ld16x256bX8Pure => "TmemF32x32".into(),
-            Tcgen05Operation::Ld16x256bPure => "TmemF32x4".into(),
-            Tcgen05Operation::Ld => {
-                let count = tcgen05_ld_register_count(record);
-                if count == 1 {
-                    "u32".into()
-                } else {
-                    format!("CuSimd<u32, {count}>")
-                }
-            }
-            Tcgen05Operation::St => "()".into(),
-            _ => "()".into(),
-        };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        if let Some(participation) = tcgen05_participation_doc(operation) {
-            writeln!(output, "/// {participation}").unwrap();
-        }
-        output.push_str(
-            "/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n",
-        );
-        if !record.rust.safe {
-            output.push_str("///\n/// # Safety\n");
-            if operation == Tcgen05Operation::St {
-                output.push_str(
-                    "/// The tensor-memory address must remain live and cover the selected tile.\n\
-                     /// All active warp lanes must execute convergently with the same address. Complete the store wait before relying on completion.\n",
-                );
-            } else if operation == Tcgen05Operation::Ld {
-                output.push_str(
-                    "/// The tensor-memory address must remain live and cover the selected tile.\n\
-                     /// All active warp lanes must execute convergently with the same address. Complete the load wait before using the result.\n",
-                );
-            } else if tcgen05_is_commit(operation) {
-                if tcgen05_is_multicast_commit(operation) {
-                    output.push_str(
-                        "/// `mbar` must point to a live initialized cluster-shared mbarrier. `cta_mask` must select valid CTA ranks in its cluster.\n",
-                    );
-                } else {
-                    output.push_str(
-                        "/// `mbar` must point to a live initialized mbarrier valid for this CTA-group mode.\n",
-                    );
-                }
-                output.push_str(
-                    "/// The same thread that issued the tracked asynchronous tcgen05 operations must issue this commit.\n",
-                );
-            } else if tcgen05_is_shift(operation) {
-                output.push_str(
-                    "/// `tmem_addr` must name a live tensor-memory allocation, and its lane component must be a multiple of 32.\n\
-                     /// Completion must be tracked by a matching commit from that same thread and observed through the selected mbarrier before relying on shifted data.\n",
-                );
-            } else {
-                output.push_str("/// The caller must satisfy the tcgen05 address, lifetime, and participation rules.\n");
-            }
-        }
-        output.push_str("#[inline(never)]\n");
-        if record.rust.arguments.len() > 5 {
-            output.push_str("#[allow(clippy::too_many_arguments)]\n");
-        }
-        let safety = if record.rust.safe { "" } else { "unsafe " };
-        writeln!(
-            output,
-            "pub {safety}fn {}({arguments}) -> {result} {{",
-            record.rust.name
-        )
-        .unwrap();
-        if !values.is_empty() {
-            if values.contains(',') {
-                writeln!(output, "    let _ = ({values});").unwrap();
-            } else {
-                writeln!(output, "    let _ = {values};").unwrap();
-            }
-        }
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_packed_atomic(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::atomic` to keep existing paths stable.\n\n");
-    for record in packed_atomics(catalog) {
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::atomic::"))
-            .expect("packed-atomic compatibility path");
-        assert_eq!(path, &format!("cuda_device::atomic::{}", record.rust.name));
-        let packed = record
-            .packed_atomic
-            .as_ref()
-            .expect("packed-atomic semantics");
-        let lane_type = match packed.format {
-            PackedAtomicFormat::F16x2 => "f16",
-            PackedAtomicFormat::Bf16x2 => "bf16",
-        };
-        let minimum_sm = match &record.target.hardware {
-            CatalogHardwareTarget::AnyOf { alternatives } => match alternatives.as_slice() {
-                [CatalogHardwareAlternative::MinimumSm { sm }] => *sm,
-                _ => panic!("packed-atomic compatibility API requires one minimum SM"),
-            },
-            _ => panic!("packed-atomic compatibility API requires one minimum SM"),
-        };
-        assert!(!record.rust.safe);
-        assert!(record.rust.must_use);
-        assert_eq!(record.rust.arguments, ["*mut u32", "u32"]);
-        assert_eq!(record.rust.result, "u32");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "/// `val` and the result pack two {lane_type} lanes into `u32`, low lane first."
-        )
-        .unwrap();
-        output.push_str(
-            "/// The lanes are atomic independently and may not form one old 32-bit snapshot.\n",
-        );
-        output.push_str("/// This is a relaxed GPU-scope operation. Each lane rounds to nearest-even and preserves subnormals.\n");
-        writeln!(
-            output,
-            "/// Requires PTX {} and `sm_{minimum_sm}+`.",
-            record.target.minimum_ptx
-        )
-        .unwrap();
-        output.push_str("///\n/// # Safety\n");
-        output.push_str(
-            "/// `addr` must point to four writable, four-byte-aligned bytes in global memory.\n",
-        );
-        output.push_str("/// Do not overlap this operation with a whole-word atomic or non-atomic lane access.\n");
-        output.push_str("/// Racing atomics must use mutually inclusive scopes; host/system access is not included.\n");
-        output.push_str("#[must_use]\n#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub unsafe fn {}(addr: *mut u32, val: u32) -> u32 {{",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("    let _ = (addr, val);\n");
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_cp_async_copy(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "// Included inside `cuda_device::async_copy` to keep existing paths stable.\n\n",
-    );
-    for record in cp_async_copies(catalog) {
-        let copy = record.cp_async_copy.as_ref().expect("cp.async semantics");
-        let bytes = copy.copy_size.bytes();
-        let cache = match copy.cache_policy {
-            CpAsyncCachePolicy::Ca => "cache-all",
-            CpAsyncCachePolicy::Cg => "cache-global",
-        };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "/// Uses the {cache} policy and copies {bytes} bytes."
-        )
-        .unwrap();
-        if copy.source_size == CpAsyncSourceSize::Runtime {
-            writeln!(
-                output,
-                "/// Bytes after `src_size` are filled with zero; `src_size` must be at most {bytes}."
-            )
-            .unwrap();
-        }
-        output.push_str("///\n/// # Safety\n");
-        writeln!(
-            output,
-            "/// `shared_dst` must point to {bytes} writable bytes in shared memory and be aligned to {bytes} bytes."
-        )
-        .unwrap();
-        if copy.source_size == CpAsyncSourceSize::Runtime {
-            writeln!(
-                output,
-                "/// `global_src` must point to `src_size` readable bytes in global memory and be aligned to {bytes} bytes."
-            )
-            .unwrap();
-        } else {
-            writeln!(
-                output,
-                "/// `global_src` must point to {bytes} readable bytes in global memory and be aligned to {bytes} bytes."
-            )
-            .unwrap();
-        }
-        output.push_str(
-            "/// Both ranges must remain valid, the source must remain unchanged, and the destination must not be accessed until this copy completes.\n\
-             /// The issuing thread must complete the copy. Synchronize threads afterward before another thread accesses the destination.\n\
-             /// User-authored completion assembly must include a compiler memory clobber.\n",
-        );
-        output.push_str("#[inline(never)]\n");
-        if copy.source_size == CpAsyncSourceSize::Runtime {
-            writeln!(
-                output,
-                "pub unsafe fn {}(_shared_dst: *mut u32, _global_src: *const u8, _src_size: u32) {{",
-                record.rust.name
-            )
-            .unwrap();
-        } else {
-            writeln!(
-                output,
-                "pub unsafe fn {}(_shared_dst: *mut u32, _global_src: *const u32) {{",
-                record.rust.name
-            )
-            .unwrap();
-        }
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    for record in cp_async_controls(catalog) {
-        let control = record
-            .cp_async_control
-            .as_ref()
-            .expect("cp.async control semantics");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("///\n/// # Safety\n");
-        match control.operation {
-            CpAsyncControlOperation::CommitGroup => output.push_str(
-                "/// This commits only copies issued by the executing thread and does not wait for completion.\n",
-            ),
-            CpAsyncControlOperation::WaitAll => output.push_str(
-                "/// This waits only for copies issued by this thread. Synchronize threads before another thread accesses a completed destination.\n",
-            ),
-            CpAsyncControlOperation::WaitGroup => output.push_str(
-                "/// `max_pending` must be a compile-time constant. Access only destinations whose copy groups this wait completes.\n",
-            ),
-        }
-        output.push_str("#[inline(never)]\n");
-        if control.operation == CpAsyncControlOperation::WaitGroup {
-            writeln!(
-                output,
-                "pub unsafe fn {}(_max_pending: u32) {{",
-                record.rust.name
-            )
-            .unwrap();
-        } else {
-            writeln!(output, "pub unsafe fn {}() {{", record.rust.name).unwrap();
-        }
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    for record in cp_async_mbarriers(catalog) {
-        let bridge = record
-            .cp_async_mbarrier
-            .as_ref()
-            .expect("cp.async mbarrier semantics");
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::async_copy::"))
-            .expect("cp.async mbarrier compatibility path");
-        assert_eq!(
-            path,
-            &format!("cuda_device::async_copy::{}", record.rust.name)
-        );
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
-        output.push_str("///\n/// # Safety\n");
-        output.push_str(
-            "/// `barrier` must point to a live, initialized, eight-byte-aligned mbarrier object in shared memory.\n\
-             /// This thread must have issued the `cp.async` operations being associated with it.\n\
-             /// The object must remain valid until those operations complete.\n",
-        );
-        match bridge.operation {
-            CpAsyncMbarrierOperation::Arrive => output.push_str(
-                "/// This form increments the pending count before scheduling the asynchronous arrival.\n\
-                 /// That increment must not exceed the barrier's pending-count limit.\n",
-            ),
-            CpAsyncMbarrierOperation::ArriveNoInc => output.push_str(
-                "/// The initial pending count must already include the asynchronous arrival.\n",
-            ),
-        }
-        output.push_str("#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub unsafe fn {}(_barrier: *mut crate::barrier::Barrier) {{",
-            record.rust.name
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_mbarrier_basic(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::barrier` to keep existing paths stable.\n\n");
-    for record in mbarrier_basics(catalog) {
-        let mbarrier = record
-            .mbarrier_basic
-            .as_ref()
-            .expect("basic mbarrier semantics");
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::barrier::"))
-            .expect("basic mbarrier compatibility path");
-        assert_eq!(path, &format!("cuda_device::barrier::{}", record.rust.name));
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
-        output.push_str("///\n/// # Safety\n");
-        output.push_str(
-            "/// `bar` must point to a live, eight-byte-aligned `Barrier` in shared memory.\n",
-        );
-        match mbarrier.operation {
-            MbarrierBasicOperation::Init => output.push_str(
-                "/// Exactly one thread may initialize it. `expected_count` must be in `1..=0xFFFFF` and include every arrival in the phase.\n\
-                 /// The barrier must be uninitialized or invalidated, with no concurrent barrier operation.\n",
-            ),
-            MbarrierBasicOperation::Arrive => output.push_str(
-                "/// The barrier must be initialized, and this arrival must be included in the current phase's expected count.\n\
-                 /// Use the returned token only with this barrier and phase.\n",
-            ),
-            MbarrierBasicOperation::TestWait => output.push_str(
-                "/// The barrier must be initialized. `token` must come from this barrier and phase.\n",
-            ),
-            MbarrierBasicOperation::Inval => output.push_str(
-                "/// The barrier must be initialized and unused by all threads and asynchronous operations.\n\
-                 /// Exactly one thread may invalidate it.\n",
-            ),
-        }
-        output.push_str("#[inline(never)]\n");
-        match mbarrier.operation {
-            MbarrierBasicOperation::Init => {
-                writeln!(
-                    output,
-                    "pub unsafe fn {}(bar: *mut Barrier, expected_count: u32) {{",
-                    record.rust.name
-                )
-                .unwrap();
-                output.push_str("    let _ = (bar, expected_count);\n");
-            }
-            MbarrierBasicOperation::Arrive => {
-                writeln!(
-                    output,
-                    "pub unsafe fn {}(bar: *const Barrier) -> u64 {{",
-                    record.rust.name
-                )
-                .unwrap();
-                output.push_str("    let _ = bar;\n");
-            }
-            MbarrierBasicOperation::TestWait => {
-                writeln!(
-                    output,
-                    "pub unsafe fn {}(bar: *const Barrier, token: u64) -> bool {{",
-                    record.rust.name
-                )
-                .unwrap();
-                output.push_str("    let _ = (bar, token);\n");
-            }
-            MbarrierBasicOperation::Inval => {
-                writeln!(
-                    output,
-                    "pub unsafe fn {}(bar: *mut Barrier) {{",
-                    record.rust.name
-                )
-                .unwrap();
-                output.push_str("    let _ = bar;\n");
-            }
-        }
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_mbarrier_extended(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::barrier` to keep existing paths stable.\n\n");
-    for record in mbarrier_extended(catalog) {
-        let contract = record
-            .mbarrier_extended
-            .as_ref()
-            .expect("extended-mbarrier contract");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
-        output.push_str("///\n/// # Safety\n");
-        output.push_str(
-            "/// The caller must satisfy the barrier, scope, and memory-ordering contract.\n",
-        );
-        output.push_str("#[inline(never)]\n");
-        match contract.operation {
-            MbarrierExtendedOperation::ArriveExpectTxCta
-            | MbarrierExtendedOperation::ArriveExpectTxCluster => {
-                writeln!(
-                    output,
-                    "pub unsafe fn {}(bar: *const Barrier, _tx_count: u32, bytes: u32) -> u64 {{",
-                    record.rust.name
-                )
-                .unwrap();
-                output.push_str("    let _ = (bar, bytes);\n");
-            }
-            MbarrierExtendedOperation::ArriveRemoteCluster => {
-                writeln!(
-                    output,
-                    "pub unsafe fn {}(remote_bar_addr: u64) {{",
-                    record.rust.name
-                )
-                .unwrap();
-                output.push_str("    let _ = remote_bar_addr;\n");
-            }
-            MbarrierExtendedOperation::TryWaitTokenCta => {
-                writeln!(
-                    output,
-                    "pub unsafe fn {}(bar: *const Barrier, token: u64) -> bool {{",
-                    record.rust.name
-                )
-                .unwrap();
-                output.push_str("    let _ = (bar, token);\n");
-            }
-            MbarrierExtendedOperation::TryWaitParityCta
-            | MbarrierExtendedOperation::TryWaitParityCluster => {
-                writeln!(
-                    output,
-                    "pub unsafe fn {}(bar: *const Barrier, parity: u32) -> bool {{",
-                    record.rust.name
-                )
-                .unwrap();
-                output.push_str("    let _ = (bar, parity);\n");
-            }
-            MbarrierExtendedOperation::FenceProxyAsyncSharedCta
-            | MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster
-            | MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster
-            | MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster => {
-                writeln!(output, "pub unsafe fn {}() {{", record.rust.name).unwrap();
-            }
-            MbarrierExtendedOperation::Nanosleep => {
-                writeln!(output, "pub unsafe fn {}(ns: u32) {{", record.rust.name).unwrap();
-                output.push_str("    let _ = ns;\n");
-            }
-        }
-        writeln!(
-            output,
-            "    unreachable!(\"{} called outside CUDA kernel context\")",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_compat_integer_minmax(catalog: &CatalogFile, hash: &str, module: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    writeln!(
-        output,
-        "// Included inside `cuda_device::{module}` to keep existing paths stable.\n"
-    )
-    .unwrap();
-    for record in integer_minmaxes(catalog).filter(|record| record.rust.module == module) {
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with(&format!("cuda_device::{module}::")))
-            .expect("integer-min/max compatibility path");
-        let scalar = &record.rust.result;
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("#[must_use]\n#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub fn {}(arg0: {scalar}, arg1: {scalar}) -> {scalar} {{",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("    let _ = (arg0, arg1);\n");
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    output
-}
-
-fn render_dialect_integer_minmax(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operations for generated extended integer min/max.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\n",
-    );
-    for record in integer_minmaxes(catalog) {
-        let signedness = if record.rust.result == "i32" {
-            "Signed"
-        } else {
-            "Unsigned"
-        };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "///\n/// Lowers to `{}`.",
-            integer_minmax_ptx_mnemonic(record)
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, arg0: Value, arg1: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, 32, Signedness::{signedness});\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![arg0, arg1],\n            vec![],\n            0,\n        )\n    }}\n}}"
-        )
-        .unwrap();
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 2 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !(0..2).all(|index| is_i32(ctx, op.get_operand(index).get_type(ctx)))\n            || !is_i32(ctx, op.get_result(0).get_type(ctx))\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-            format!(
-                "{} requires exactly 2 operands and one result",
-                record.dialect.op_name
-            ),
-            format!(
-                "{} operands and result must be 32-bit integers",
-                record.dialect.op_name
-            ),
-        )
-        .unwrap();
-    }
-    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
-    for record in integer_minmaxes(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_compat_packed_alu(catalog: &CatalogFile, hash: &str, format: PackedAluFormat) -> String {
-    let mut output = rust_header(catalog, hash);
-    let (module, _, _, _, _) = packed_alu_format_shape(format);
-    writeln!(
-        output,
-        "// Included inside `cuda_device::{module}` to keep existing paths stable.\n"
-    )
-    .unwrap();
-    for record in packed_alus(catalog).filter(|record| {
-        record
-            .packed_alu
-            .as_ref()
-            .is_some_and(|packed| packed.format == format)
-    }) {
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with(&format!("cuda_device::{module}::")))
-            .expect("packed-ALU compatibility path");
-        let arguments = record
-            .rust
-            .arguments
-            .iter()
-            .enumerate()
-            .map(|(index, ty)| format!("arg{index}: {ty}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let values = (0..record.rust.arguments.len())
-            .map(|index| format!("arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        if record.rust.must_use {
-            output.push_str("#[must_use]\n");
-        }
-        output.push_str("#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub fn {}({arguments}) -> {} {{",
-            record.rust.name, record.rust.result
-        )
-        .unwrap();
-        if record.rust.arguments.len() == 1 {
-            writeln!(output, "    let _ = {values};").unwrap();
-        } else {
-            writeln!(output, "    let _ = ({values});").unwrap();
-        }
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    render_compat_extended_minmax_into(&mut output, catalog, module);
-    output
-}
-
-fn render_compat_scalar_minmax(catalog: &CatalogFile, hash: &str, module: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    writeln!(
-        output,
-        "// Included inside `cuda_device::{module}` to keep existing paths stable.\n"
-    )
-    .unwrap();
-    render_compat_extended_minmax_into(&mut output, catalog, module);
-    output
-}
-
-fn render_compat_extended_minmax_into(output: &mut String, catalog: &CatalogFile, module: &str) {
-    for record in extended_minmax(catalog).filter(|record| record.rust.module == module) {
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with(&format!("cuda_device::{module}::")))
-            .expect("extended-minmax compatibility path");
-        let ty = extended_minmax_rust_type(record);
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("#[must_use]\n#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub fn {}(a: {ty}, b: {ty}) -> {ty} {{",
-            record.rust.name
-        )
-        .unwrap();
-        output.push_str("    let _ = (a, b);\n");
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-}
-
-fn render_compat_packed_conversion(
-    catalog: &CatalogFile,
-    hash: &str,
-    path_prefix: &str,
-    containing_module: &str,
-    argument_names: (&str, &str),
-) -> String {
-    let mut output = rust_header(catalog, hash);
-    writeln!(
-        output,
-        "// Included inside `cuda_device::{containing_module}`.\n"
-    )
-    .unwrap();
-    for record in packed_conversions(catalog).filter(|record| {
-        record
-            .rust
-            .compatibility_paths
-            .iter()
-            .any(|path| path.starts_with(path_prefix))
-    }) {
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with(path_prefix))
-            .expect("packed-conversion compatibility path");
-        // A packed source arrives in one register, so the parameter list
-        // follows the record's own argument types rather than a fixed f32 pair.
-        let parameter_names: Vec<&str> = match packed_conversion_source(record) {
-            PackedConversionSourceFormat::F32x2 => vec![argument_names.0, argument_names.1],
-            PackedConversionSourceFormat::E4m3x2
-            | PackedConversionSourceFormat::E5m2x2
-            | PackedConversionSourceFormat::F16x2 => vec!["packed"],
-        };
-        let parameter_types = packed_conversion_rust_arguments(record);
-        let parameters = parameter_names
-            .iter()
-            .zip(&parameter_types)
-            .map(|(name, ty)| format!("{name}: {ty}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let discards = parameter_names.join(", ");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub fn {}({parameters}) -> {} {{",
-            path.rsplit("::")
-                .next()
-                .expect("packed-conversion compatibility function name"),
-            record.rust.result,
-        )
-        .unwrap();
-        if parameter_names.len() == 1 {
-            writeln!(output, "    let _ = {discards};").unwrap();
-        } else {
-            writeln!(output, "    let _ = ({discards});").unwrap();
-        }
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    if containing_module == "convert" {
-        for record in scalar_conversions(catalog) {
-            let path = record
-                .rust
-                .compatibility_paths
-                .iter()
-                .find(|path| path.starts_with("cuda_device::convert::"))
-                .expect("scalar-conversion compatibility path");
-            writeln!(output, "/// {}", record.summary).unwrap();
-            output.push_str("#[must_use]\n#[inline(never)]\n");
-            writeln!(output, "pub fn {}(value: f32) -> u32 {{", record.rust.name).unwrap();
-            output.push_str("    let _ = value;\n");
-            writeln!(
-                output,
-                "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-            )
-            .unwrap();
-            output.push_str("}\n\n");
-        }
-    }
-    output
-}
-
-fn render_compat_float(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str("// Included inside `cuda_device::float`.\n\n");
-    for record in scalar_arithmetics(catalog) {
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::float::"))
-            .expect("scalar-arithmetic compatibility path");
-        let ty = scalar_arithmetic_rust_type(record);
-        let arity = scalar_arithmetic_arity(record);
-        let parameters = (0..arity)
-            .map(|index| format!("arg{index}: {ty}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let arguments = (0..arity)
-            .map(|index| format!("arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("#[must_use]\n#[inline(never)]\n");
-        writeln!(
-            output,
-            "pub fn {}({parameters}) -> {ty} {{",
-            record.rust.name
-        )
-        .unwrap();
-        writeln!(output, "    let _ = ({arguments});").unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    for record in scalar_maths(catalog) {
-        let path = record
-            .rust
-            .compatibility_paths
-            .iter()
-            .find(|path| path.starts_with("cuda_device::float::"))
-            .expect("scalar-math compatibility path");
-        let ty = match scalar_math_contract(record).format {
-            ScalarMathFormat::F16 => "u16",
-            ScalarMathFormat::F32 => "f32",
-            ScalarMathFormat::F64 => "f64",
-        };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("#[must_use]\n#[inline(never)]\n");
-        writeln!(output, "pub fn {}(arg0: {ty}) -> {ty} {{", record.rust.name).unwrap();
-        writeln!(output, "    let _ = arg0;").unwrap();
-        writeln!(
-            output,
-            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
-        )
-        .unwrap();
-        output.push_str("}\n\n");
-    }
-    render_compat_extended_minmax_into(&mut output, catalog, "float");
-    output
-}
-
-fn render_compat_float_output(catalog: &CatalogFile, hash: &str) -> Option<(PathBuf, String)> {
-    (scalar_arithmetics(catalog).next().is_some()
-        || extended_minmax(catalog).next().is_some()
-        || scalar_maths(catalog).next().is_some())
-    .then(|| {
-        (
-            "crates/cuda-device/src/generated/float.rs".into(),
-            render_compat_float(catalog, hash),
-        )
-    })
-}
-
-fn render_dialect_mod(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "mod active_mask;\nmod cluster_barrier;\nmod cp_async;\nmod dotprod;\nmod ldmatrix;\nmod mbarrier_basic;\nmod movmatrix;\nmod packed_alu;\nmod packed_atomic;\nmod packed_conversion;\nmod prmt;\nmod redux;\nmod register_mma;\nmod sparse_mma;\nmod sreg;\nmod sync;\nmod vote;\nmod warp_barrier;\nmod warp_match;\nmod warp_shuffle;\n\npub use active_mask::*;\npub use cluster_barrier::*;\npub use cp_async::*;\npub use dotprod::*;\npub use ldmatrix::*;\npub use mbarrier_basic::*;\npub use movmatrix::*;\npub use packed_alu::*;\npub use packed_atomic::*;\npub use packed_conversion::*;\npub use prmt::*;\npub use redux::*;\npub use register_mma::*;\npub use sparse_mma::*;\npub use sreg::*;\npub use sync::*;\npub use vote::*;\npub use warp_barrier::*;\npub use warp_match::*;\npub use warp_shuffle::*;\n\nuse pliron::context::Context;\n\npub(super) fn register(ctx: &mut Context) {\n    active_mask::register(ctx);\n    cluster_barrier::register(ctx);\n    cp_async::register(ctx);\n    dotprod::register(ctx);\n    ldmatrix::register(ctx);\n    mbarrier_basic::register(ctx);\n    movmatrix::register(ctx);\n    packed_alu::register(ctx);\n    packed_atomic::register(ctx);\n    packed_conversion::register(ctx);\n    prmt::register(ctx);\n    redux::register(ctx);\n    register_mma::register(ctx);\n    sparse_mma::register(ctx);\n    sreg::register(ctx);\n    sync::register(ctx);\n    vote::register(ctx);\n    warp_barrier::register(ctx);\n    warp_match::register(ctx);\n    warp_shuffle::register(ctx);\n}\n",
-    );
-    if scalar_conversions(catalog).next().is_some() {
-        output = output
-            .replace("mod redux;", "mod redux;\nmod scalar_conversion;")
-            .replace(
-                "pub use redux::*;",
-                "pub use redux::*;\npub use scalar_conversion::*;",
-            )
-            .replace(
-                "    redux::register(ctx);",
-                "    redux::register(ctx);\n    scalar_conversion::register(ctx);",
-            );
-    }
-    if scalar_arithmetics(catalog).next().is_some() {
-        output = output
-            .replace("mod redux;", "mod redux;\nmod scalar_arithmetic;")
-            .replace(
-                "pub use redux::*;",
-                "pub use redux::*;\npub use scalar_arithmetic::*;",
-            )
-            .replace(
-                "    redux::register(ctx);",
-                "    redux::register(ctx);\n    scalar_arithmetic::register(ctx);",
-            );
-    }
-    if scalar_maths(catalog).next().is_some() {
-        output = output
-            .replace("mod redux;", "mod redux;\nmod scalar_math;")
-            .replace(
-                "pub use redux::*;",
-                "pub use redux::*;\npub use scalar_math::*;",
-            )
-            .replace(
-                "    redux::register(ctx);",
-                "    redux::register(ctx);\n    scalar_math::register(ctx);",
-            );
-    }
-    if integer_minmaxes(catalog).next().is_some() {
-        output = output
-            .replace("mod ldmatrix;", "mod integer_minmax;\nmod ldmatrix;")
-            .replace(
-                "pub use ldmatrix::*;",
-                "pub use integer_minmax::*;\npub use ldmatrix::*;",
-            )
-            .replace(
-                "    ldmatrix::register(ctx);",
-                "    integer_minmax::register(ctx);\n    ldmatrix::register(ctx);",
-            );
-    }
-    if extended_minmax(catalog).next().is_some() {
-        output = output
-            .replace("mod dotprod;", "mod dotprod;\nmod extended_minmax;")
-            .replace(
-                "pub use dotprod::*;",
-                "pub use dotprod::*;\npub use extended_minmax::*;",
-            )
-            .replace(
-                "    dotprod::register(ctx);",
-                "    dotprod::register(ctx);\n    extended_minmax::register(ctx);",
-            );
-    }
-    if debug_controls(catalog).next().is_some() {
-        output = output
-            .replace("mod dotprod;", "mod debug_control;\nmod dotprod;")
-            .replace(
-                "pub use dotprod::*;",
-                "pub use debug_control::*;\npub use dotprod::*;",
-            )
-            .replace(
-                "    dotprod::register(ctx);",
-                "    debug_control::register(ctx);\n    dotprod::register(ctx);",
-            );
-    }
-    if cluster_memory(catalog).next().is_some() {
-        output = output
-            .replace(
-                "mod cluster_barrier;",
-                "mod cluster_barrier;\nmod cluster_memory;",
-            )
-            .replace(
-                "pub use cluster_barrier::*;",
-                "pub use cluster_barrier::*;\npub use cluster_memory::*;",
-            )
-            .replace(
-                "    cluster_barrier::register(ctx);",
-                "    cluster_barrier::register(ctx);\n    cluster_memory::register(ctx);",
-            );
-    }
-    if stmatrices(catalog).next().is_some() {
-        output = output
-            .replace("mod sync;", "mod stmatrix;\nmod sync;")
-            .replace("pub use sync::*;", "pub use stmatrix::*;\npub use sync::*;")
-            .replace(
-                "    sync::register(ctx);",
-                "    stmatrix::register(ctx);\n    sync::register(ctx);",
-            );
-    }
-    if movmatrix(catalog).next().is_none() {
-        output = output.replace("mod movmatrix;\n", "");
-        output = output.replace("pub use movmatrix::*;\n", "");
-        output = output.replace("    movmatrix::register(ctx);\n", "");
-    }
-    if clc_intrinsics(catalog).next().is_some() {
-        output = output
-            .replace("mod cluster_barrier;", "mod clc;\nmod cluster_barrier;")
-            .replace(
-                "pub use cluster_barrier::*;",
-                "pub use clc::*;\npub use cluster_barrier::*;",
-            )
-            .replace(
-                "    cluster_barrier::register(ctx);",
-                "    clc::register(ctx);\n    cluster_barrier::register(ctx);",
-            );
-    }
-    if elect_intrinsics(catalog).next().is_some() {
-        output = output
-            .replace("mod dotprod;", "mod dotprod;\nmod elect;")
-            .replace(
-                "pub use dotprod::*;",
-                "pub use dotprod::*;\npub use elect::*;",
-            )
-            .replace(
-                "    dotprod::register(ctx);",
-                "    dotprod::register(ctx);\n    elect::register(ctx);",
-            );
-    }
-    if mbarrier_extended(catalog).next().is_some() {
-        output = output.replace(
-            "mod mbarrier_basic;\n",
-            "mod mbarrier_basic;\nmod mbarrier_extended;\n",
-        );
-        output = output.replace(
-            "pub use mbarrier_basic::*;\n",
-            "pub use mbarrier_basic::*;\npub use mbarrier_extended::*;\n",
-        );
-        output = output.replace(
-            "    mbarrier_basic::register(ctx);\n",
-            "    mbarrier_basic::register(ctx);\n    mbarrier_extended::register(ctx);\n",
-        );
-    }
-    if wgmma_controls(catalog).next().is_some() {
-        output = output
-            .replace("mod warp_shuffle;", "mod warp_shuffle;\nmod wgmma_control;")
-            .replace(
-                "pub use warp_shuffle::*;",
-                "pub use warp_shuffle::*;\npub use wgmma_control::*;",
-            )
-            .replace(
-                "    warp_shuffle::register(ctx);",
-                "    warp_shuffle::register(ctx);\n    wgmma_control::register(ctx);",
-            );
-    }
-    if execution_controls(catalog).next().is_some() {
-        output = output
-            .replace("mod dotprod;", "mod dotprod;\nmod execution_control;")
-            .replace(
-                "pub use dotprod::*;",
-                "pub use dotprod::*;\npub use execution_control::*;",
-            )
-            .replace(
-                "    dotprod::register(ctx);",
-                "    dotprod::register(ctx);\n    execution_control::register(ctx);",
-            );
-    }
-    if tma_intrinsics(catalog).next().is_some() {
-        output = output
-            .replace("mod sync;", "mod sync;\nmod tma;")
-            .replace("pub use sync::*;", "pub use sync::*;\npub use tma::*;")
-            .replace(
-                "    sync::register(ctx);",
-                "    sync::register(ctx);\n    tma::register(ctx);",
-            );
-    }
-    if tcgen05_intrinsics(catalog).next().is_some() {
-        output = output
-            .replace("mod sync;", "mod sync;\nmod tcgen05;")
-            .replace("pub use sync::*;", "pub use sync::*;\npub use tcgen05::*;")
-            .replace(
-                "    sync::register(ctx);",
-                "    sync::register(ctx);\n    tcgen05::register(ctx);",
-            );
-    }
-    output
-}
-
-fn render_dialect_elect(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Generated warp leader-election operation.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::IntegerType,\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::{TypeHandle, Typed},\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\n",
-    );
-    for record in elect_intrinsics(catalog) {
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<2>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n}\n\n");
-        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
-        output.push_str(
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 1 || op.get_num_results() != 2 {\n            return verify_err!(op.loc(), \"nvvm.elect_sync requires one i32 operand and results [i32, i1]\");\n        }\n        if !is_integer_width(ctx, op.get_operand(0).get_type(ctx), 32)\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), 32)\n            || !is_integer_width(ctx, op.get_result(1).get_type(ctx), 1)\n        {\n            return verify_err!(op.loc(), \"nvvm.elect_sync requires one i32 operand and results [i32, i1]\");\n        }\n        Ok(())\n    }\n}\n\n",
-        );
-    }
-    output.push_str(
-        "fn is_integer_width(ctx: &Context, ty: TypeHandle, width: u32) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\npub(super) fn register(ctx: &mut Context) {\n",
-    );
-    for record in elect_intrinsics(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_sreg(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural NVVM operations for generated special-register reads.\n\nuse pliron::{\n    builtin::op_interfaces::{NOpdsInterface, NResultsInterface},\n    builtin::types::IntegerType,\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\n",
-    );
-    for record in sregs(catalog) {
-        let width = record.scalar_width().unwrap();
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "/// Catalog ID `{}`; {} returns one `i{width}` result.",
-            record.id,
-            source_label(record)
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<0>, NResultsInterface<1>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self {\n");
-        writeln!(output, "        Self {{ op }}").unwrap();
-        output.push_str("    }\n}\n");
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    fn verify(&self, ctx: &Context) -> Result<(), Error> {\n");
-        writeln!(
-            output,
-            "        verify_scalar_result(ctx, self.get_operation(), {:?}, {width})",
-            record.dialect.op_name
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    output.push_str(
-        "fn verify_scalar_result(\n    ctx: &Context,\n    op: Ptr<Operation>,\n    name: &str,\n    width: u32,\n) -> Result<(), Error> {\n    let op = op.deref(ctx);\n    let ty = op.get_result(0).get_type(ctx);\n    let ty_object = ty.deref(ctx);\n    let Some(integer) = ty_object.downcast_ref::<IntegerType>() else {\n        return verify_err!(op.loc(), \"{} result must be an integer\", name);\n    };\n    if integer.width() != width {\n        return verify_err!(\n            op.loc(),\n            \"{} result must be a {}-bit integer\",\n            name,\n            width\n        );\n    }\n    Ok(())\n}\n\npub(super) fn register(ctx: &mut Context) {\n",
-    );
-    for record in sregs(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_sync(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operation for generated CTA synchronization.\n\nuse pliron::{\n    builtin::op_interfaces::{NOpdsInterface, NResultsInterface},\n    context::{Context, Ptr},\n    op::Op,\n    operation::Operation,\n};\nuse pliron_derive::pliron_op;\n\n",
-    );
-    for record in sync_intrinsics(catalog) {
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    verifier = \"succ\",\n    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str(
-            "    pub fn new(op: Ptr<Operation>) -> Self {\n        Self { op }\n    }\n}\n\n",
-        );
-    }
-    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
-    for record in sync_intrinsics(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_vote(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operations for the generated `vote.sync` family.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_integer_width(ctx: &Context, ty: pliron::r#type::TypeHandle, width: u32) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\n",
-    );
-    for record in vote_intrinsics(catalog) {
-        let result_width = match record.vote.as_ref().unwrap().mode {
-            VoteMode::All | VoteMode::Any | VoteMode::Uni => 1,
-            VoteMode::Ballot => 32,
-        };
-        let result_signedness = if result_width == 32 {
-            "Unsigned"
-        } else {
-            "Signless"
-        };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str(
-            "///\n/// Operands are `[member_mask, predicate]`. The generated verifier keeps\n/// the mask, predicate, and result types exact.\n",
-        );
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, member_mask: Value, predicate: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, {result_width}, Signedness::{result_signedness});\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![member_mask, predicate],\n            vec![],\n            0,\n        )\n    }}\n}}"
-        )
-        .unwrap();
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 2 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_integer_width(ctx, op.get_operand(0).get_type(ctx), 32)\n            || !is_integer_width(ctx, op.get_operand(1).get_type(ctx), 1)\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), {result_width})\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-            format!(
-                "{} requires exactly two operands [member_mask, predicate] and one result",
-                record.dialect.op_name
-            ),
-            format!(
-                "{} requires i32 member mask, i1 predicate, and i{result_width} result",
-                record.dialect.op_name
-            ),
-        )
-        .unwrap();
-    }
-    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
-    for record in vote_intrinsics(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_active_mask(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operation for the generated active warp mask.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\n",
-    );
-    for record in active_masks(catalog) {
-        debug_assert_eq!(
-            record.active_mask.as_ref().unwrap().adapter,
-            ActiveMaskAdapter::DirectZeroOperandMask
-        );
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<0>, NResultsInterface<1>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str(
-            "    pub fn new(op: Ptr<Operation>) -> Self {\n        Self { op }\n    }\n\n    pub fn build(ctx: &mut Context) -> Ptr<Operation> {\n        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![],\n            vec![],\n            0,\n        )\n    }\n}\n",
-        );
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        let valid = op.get_num_operands() == 0\n            && op.get_num_results() == 1\n            && op.get_result(0).get_type(ctx).deref(ctx)\n                .downcast_ref::<IntegerType>()\n                .is_some_and(|integer| integer.width() == 32);\n        if !valid {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-            format!("{} requires no operands and one i32 result", record.dialect.op_name)
-        )
-        .unwrap();
-    }
-    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
-    for record in active_masks(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_cp_async_copy(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r#"//! Structural operations for classic `cp.async` instructions.
-
-use dialect_mir::{ops::MirConstantOp, types::{MirPtrType, address_space}};
-use pliron::{
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        ops::ConstantOp,
-        types::{IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::pliron_op;
-
-fn verify_pointer(
-    ctx: &Context,
-    op: &Operation,
-    value: Value,
-    role: &str,
-    allowed_address_spaces: &[u32],
-) -> Result<(), Error> {
-    let ty = value.get_type(ctx);
-    let ty = ty.deref(ctx);
-    let Some(pointer) = ty.downcast_ref::<MirPtrType>() else {
-        return verify_err!(op.loc(), "{role} must be a MIR pointer");
-    };
-    if !allowed_address_spaces.contains(&pointer.address_space) {
-        return verify_err!(op.loc(), "{role} has the wrong address space");
-    }
-    Ok(())
-}
-
-fn verify_cp_async_copy(
-    ctx: &Context,
-    operation: Ptr<Operation>,
-    name: &str,
-    has_source_size: bool,
-) -> Result<(), Error> {
-    let op = operation.deref(ctx);
-    let expected_operands = if has_source_size { 3 } else { 2 };
-    if op.get_num_operands() != expected_operands || op.get_num_results() != 0 {
-        return verify_err!(op.loc(), "{name} has the wrong operand or result count");
-    }
-    verify_pointer(
-        ctx,
-        &op,
-        op.get_operand(0),
-        "shared destination",
-        &[address_space::GENERIC, address_space::SHARED],
-    )?;
-    verify_pointer(
-        ctx,
-        &op,
-        op.get_operand(1),
-        "global source",
-        &[address_space::GENERIC, address_space::GLOBAL],
-    )?;
-    if has_source_size {
-        let ty = op.get_operand(2).get_type(ctx);
-        let ty = ty.deref(ctx);
-        let Some(integer) = ty.downcast_ref::<IntegerType>() else {
-            return verify_err!(op.loc(), "source size must be u32");
-        };
-        if integer.width() != 32 || integer.signedness() != Signedness::Unsigned {
-            return verify_err!(op.loc(), "source size must be u32");
-        }
-    }
-    Ok(())
-}
-
-fn verify_cp_async_control(
-    ctx: &Context,
-    operation: Ptr<Operation>,
-    name: &str,
-    has_immediate: bool,
-) -> Result<(), Error> {
-    let op = operation.deref(ctx);
-    let expected_operands = usize::from(has_immediate);
-    if op.get_num_operands() != expected_operands || op.get_num_results() != 0 {
-        return verify_err!(op.loc(), "{name} has the wrong operand or result count");
-    }
-    if has_immediate {
-        let value = op.get_operand(0);
-        let ty = value.get_type(ctx);
-        let ty = ty.deref(ctx);
-        let Some(integer) = ty.downcast_ref::<IntegerType>() else {
-            return verify_err!(op.loc(), "maximum pending group count must be u32");
-        };
-        if integer.width() != 32 || integer.signedness() != Signedness::Unsigned {
-            return verify_err!(op.loc(), "maximum pending group count must be u32");
-        }
-        let Some(defining_op) = value.defining_op() else {
-            return verify_err!(op.loc(), "maximum pending group count must be a compile-time constant");
-        };
-        if Operation::get_op::<MirConstantOp>(defining_op, ctx).is_none()
-            && Operation::get_op::<ConstantOp>(defining_op, ctx).is_none()
-        {
-            return verify_err!(op.loc(), "maximum pending group count must be a compile-time constant");
-        }
-    }
-    Ok(())
-}
-
-fn verify_cp_async_mbarrier(
-    ctx: &Context,
-    operation: Ptr<Operation>,
-    name: &str,
-) -> Result<(), Error> {
-    let op = operation.deref(ctx);
-    if op.get_num_operands() != 1 || op.get_num_results() != 0 {
-        return verify_err!(op.loc(), "{name} has the wrong operand or result count");
-    }
-    let ty = op.get_operand(0).get_type(ctx);
-    let ty = ty.deref(ctx);
-    let Some(pointer) = ty.downcast_ref::<MirPtrType>() else {
-        return verify_err!(op.loc(), "mbarrier address must be a MIR pointer");
-    };
-    let pointee = pointer.pointee.deref(ctx);
-    let valid_pointee = pointee
-        .downcast_ref::<IntegerType>()
-        .is_some_and(|integer| {
-            integer.width() == 64 && integer.signedness() == Signedness::Unsigned
-        });
-    if !pointer.is_mutable
-        || !valid_pointee
-        || !matches!(
-            pointer.address_space,
-            address_space::GENERIC | address_space::SHARED
-        )
-    {
-        return verify_err!(
-            op.loc(),
-            "mbarrier address must be a mutable generic/shared pointer to u64"
-        );
-    }
-    Ok(())
-}
-
-"#,
-    );
-    for record in cp_async_copies(catalog) {
-        let copy = record.cp_async_copy.as_ref().unwrap();
-        let dynamic = copy.source_size == CpAsyncSourceSize::Runtime;
-        let operand_count = if dynamic { 3 } else { 2 };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<0>],\n)]\npub struct {};",
-            record.dialect.op_name, record.dialect.op_type
-        )
-        .unwrap();
-        writeln!(output, "impl {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n");
-        if dynamic {
-            output.push_str(
-                "    pub fn build(ctx: &mut Context, shared_dst: Value, global_src: Value, source_size: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![shared_dst, global_src, source_size], vec![], 0)\n    }\n",
-            );
-        } else {
-            output.push_str(
-                "    pub fn build(ctx: &mut Context, shared_dst: Value, global_src: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![shared_dst, global_src], vec![], 0)\n    }\n",
-            );
-        }
-        output.push_str("}\n\n");
-        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_cp_async_copy(ctx, self.get_operation(), {:?}, {dynamic})\n    }}\n}}\n",
-            record.dialect.op_name
-        )
-        .unwrap();
-    }
-    for record in cp_async_controls(catalog) {
-        let control = record.cp_async_control.as_ref().unwrap();
-        let has_immediate = control.operation == CpAsyncControlOperation::WaitGroup;
-        let operand_count = usize::from(has_immediate);
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<0>],\n)]\npub struct {};",
-            record.dialect.op_name, record.dialect.op_type
-        )
-        .unwrap();
-        writeln!(output, "impl {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n");
-        if has_immediate {
-            output.push_str(
-                "    pub fn build(ctx: &mut Context, max_pending: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![max_pending], vec![], 0)\n    }\n",
-            );
-        } else {
-            output.push_str(
-                "    pub fn build(ctx: &mut Context) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)\n    }\n",
-            );
-        }
-        output.push_str("}\n\n");
-        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_cp_async_control(ctx, self.get_operation(), {:?}, {has_immediate})\n    }}\n}}\n",
-            record.dialect.op_name
-        )
-        .unwrap();
-    }
-    for record in cp_async_mbarriers(catalog) {
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<0>],\n)]\npub struct {};",
-            record.dialect.op_name, record.dialect.op_type
-        )
-        .unwrap();
-        writeln!(output, "impl {} {{", record.dialect.op_type).unwrap();
-        output.push_str(
-            "    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n    pub fn build(ctx: &mut Context, barrier: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![barrier], vec![], 0)\n    }\n}\n\n",
-        );
-        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_cp_async_mbarrier(ctx, self.get_operation(), {:?})\n    }}\n}}\n",
-            record.dialect.op_name
-        )
-        .unwrap();
-    }
-    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
-    for record in cp_async_copies(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    for record in cp_async_controls(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    for record in cp_async_mbarriers(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_mbarrier_basic(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r#"//! Structural operations for the basic shared-memory mbarrier lifecycle.
-
-use dialect_mir::types::{MirPtrType, address_space};
-use pliron::{
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        types::{IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::pliron_op;
-
-#[derive(Clone, Copy)]
-enum MbarrierBasicShape {
-    Init,
-    Arrive,
-    TestWait,
-    Inval,
-}
-
-fn is_integer(
-    ctx: &Context,
-    value: Value,
-    width: u32,
-    signedness: Signedness,
-) -> bool {
-    value
-        .get_type(ctx)
-        .deref(ctx)
-        .downcast_ref::<IntegerType>()
-        .is_some_and(|integer| {
-            integer.width() == width && integer.signedness() == signedness
-        })
-}
-
-fn verify_barrier_pointer(ctx: &Context, op: &Operation, value: Value) -> Result<(), Error> {
-    let ty = value.get_type(ctx);
-    let ty = ty.deref(ctx);
-    let Some(pointer) = ty.downcast_ref::<MirPtrType>() else {
-        return verify_err!(op.loc(), "mbarrier address must be a MIR pointer");
-    };
-    if !matches!(pointer.address_space, address_space::GENERIC | address_space::SHARED) {
-        return verify_err!(op.loc(), "mbarrier address must be generic or shared");
-    }
-    Ok(())
-}
-
-fn verify_mbarrier_basic(
-    ctx: &Context,
-    operation: Ptr<Operation>,
-    name: &str,
-    shape: MbarrierBasicShape,
-) -> Result<(), Error> {
-    let op = operation.deref(ctx);
-    let (operands, results) = match shape {
-        MbarrierBasicShape::Init | MbarrierBasicShape::TestWait => (2, usize::from(matches!(shape, MbarrierBasicShape::TestWait))),
-        MbarrierBasicShape::Arrive => (1, 1),
-        MbarrierBasicShape::Inval => (1, 0),
-    };
-    if op.get_num_operands() != operands || op.get_num_results() != results {
-        return verify_err!(op.loc(), "{name} has the wrong operand or result count");
-    }
-    verify_barrier_pointer(ctx, &op, op.get_operand(0))?;
-    match shape {
-        MbarrierBasicShape::Init => {
-            if !is_integer(ctx, op.get_operand(1), 32, Signedness::Unsigned) {
-                return verify_err!(op.loc(), "mbarrier expected count must be u32");
-            }
-        }
-        MbarrierBasicShape::Arrive => {
-            if !is_integer(ctx, op.get_result(0), 64, Signedness::Unsigned) {
-                return verify_err!(op.loc(), "mbarrier arrival token must be u64");
-            }
-        }
-        MbarrierBasicShape::TestWait => {
-            if !is_integer(ctx, op.get_operand(1), 64, Signedness::Unsigned)
-                || !is_integer(ctx, op.get_result(0), 1, Signedness::Signless)
-            {
-                return verify_err!(op.loc(), "mbarrier test-wait requires a u64 token and i1 result");
-            }
-        }
-        MbarrierBasicShape::Inval => {}
-    }
-    Ok(())
-}
-
-"#,
-    );
-    for record in mbarrier_basics(catalog) {
-        let mbarrier = record.mbarrier_basic.as_ref().unwrap();
-        debug_assert_eq!(mbarrier.state_space, MbarrierStateSpace::Shared);
-        let (operand_count, result_count, shape, build) = match mbarrier.operation {
-            MbarrierBasicOperation::Init => {
-                debug_assert_eq!(
-                    mbarrier.adapter,
-                    MbarrierBasicAdapter::InitPointerCountToVoid
-                );
-                (
-                    2,
-                    0,
-                    "Init",
-                    "    pub fn build(ctx: &mut Context, barrier: Value, expected_count: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![barrier, expected_count], vec![], 0)\n    }\n",
-                )
-            }
-            MbarrierBasicOperation::Arrive => {
-                debug_assert_eq!(mbarrier.adapter, MbarrierBasicAdapter::ArrivePointerToToken);
-                (
-                    1,
-                    1,
-                    "Arrive",
-                    "    pub fn build(ctx: &mut Context, barrier: Value) -> Ptr<Operation> {\n        let token_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![token_ty.into()], vec![barrier], vec![], 0)\n    }\n",
-                )
-            }
-            MbarrierBasicOperation::TestWait => {
-                debug_assert_eq!(
-                    mbarrier.adapter,
-                    MbarrierBasicAdapter::TestWaitPointerTokenToPredicate
-                );
-                (
-                    2,
-                    1,
-                    "TestWait",
-                    "    pub fn build(ctx: &mut Context, barrier: Value, token: Value) -> Ptr<Operation> {\n        let predicate_ty = IntegerType::get(ctx, 1, Signedness::Signless);\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![predicate_ty.into()], vec![barrier, token], vec![], 0)\n    }\n",
-                )
-            }
-            MbarrierBasicOperation::Inval => {
-                debug_assert_eq!(mbarrier.adapter, MbarrierBasicAdapter::InvalPointerToVoid);
-                (
-                    1,
-                    0,
-                    "Inval",
-                    "    pub fn build(ctx: &mut Context, barrier: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![barrier], vec![], 0)\n    }\n",
-                )
-            }
-        };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<{result_count}>],\n)]\npub struct {};",
-            record.dialect.op_name, record.dialect.op_type
-        )
-        .unwrap();
-        writeln!(output, "impl {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n");
-        output.push_str(build);
-        output.push_str("}\n\n");
-        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_mbarrier_basic(ctx, self.get_operation(), {:?}, MbarrierBasicShape::{shape})\n    }}\n}}\n",
-            record.dialect.op_name
-        )
-        .unwrap();
-    }
-    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
-    for record in mbarrier_basics(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_movmatrix(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    if movmatrix(catalog).next().is_none() {
-        output.push_str(
-            "//! Structural operation for generated in-register matrix transpose.\n\nuse pliron::context::Context;\n\npub(super) fn register(_ctx: &mut Context) {}\n",
-        );
-        return output;
-    }
-    let record = movmatrix(catalog).next().unwrap();
-    output.push_str(
-        "//! Structural operation for generated in-register matrix transpose.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\n",
-    );
-    writeln!(output, "/// {}", record.summary).unwrap();
-    writeln!(
-        output,
-        "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<1>],\n)]\npub struct {};\n",
-        record.dialect.op_name, record.dialect.op_type
-    )
-    .unwrap();
-    writeln!(
-        output,
-        "impl {} {{\n    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, value: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![value],\n            vec![],\n            0,\n        )\n    }}\n}}\n",
-        record.dialect.op_type
-    )
-    .unwrap();
-    writeln!(
-        output,
-        "impl Verify for {} {{\n    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 1 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_i32(ctx, op.get_operand(0).get_type(ctx))\n            || !is_i32(ctx, op.get_result(0).get_type(ctx))\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n\npub(super) fn register(ctx: &mut Context) {{\n    {}::register(ctx);\n}}\n",
-        record.dialect.op_type,
-        format!("{} requires one operand and one result", record.dialect.op_name),
-        format!(
-            "{} operand and result must be 32-bit integers",
-            record.dialect.op_name
-        ),
-        record.dialect.op_type,
-    )
-    .unwrap();
-    output
-}
-
-fn render_dialect_mbarrier_extended(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r#"//! Structural operations for extended mbarrier and async-proxy instructions.
-
-use dialect_mir::types::{MirPtrType, address_space};
-use pliron::{
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        types::{IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::pliron_op;
-
-#[derive(Clone, Copy)]
-enum MbarrierExtendedShape {
-    PointerU32ToU64,
-    RawU64ToVoid,
-    PointerU64ToI1,
-    PointerU32ToI1,
-    ZeroToVoid,
-    U32ToVoid,
-}
-
-fn is_integer(ctx: &Context, value: Value, width: u32, signedness: Signedness) -> bool {
-    value
-        .get_type(ctx)
-        .deref(ctx)
-        .downcast_ref::<IntegerType>()
-        .is_some_and(|integer| {
-            integer.width() == width && integer.signedness() == signedness
-        })
-}
-
-fn verify_barrier_pointer(ctx: &Context, op: &Operation, value: Value) -> Result<(), Error> {
-    let ty = value.get_type(ctx);
-    let ty = ty.deref(ctx);
-    let Some(pointer) = ty.downcast_ref::<MirPtrType>() else {
-        return verify_err!(op.loc(), "mbarrier address must be a MIR pointer");
-    };
-    if !matches!(pointer.address_space, address_space::GENERIC | address_space::SHARED) {
-        return verify_err!(op.loc(), "mbarrier address must be generic or shared");
-    }
-    Ok(())
-}
-
-fn verify_mbarrier_extended(
-    ctx: &Context,
-    operation: Ptr<Operation>,
-    name: &str,
-    shape: MbarrierExtendedShape,
-) -> Result<(), Error> {
-    let op = operation.deref(ctx);
-    let (operands, results) = match shape {
-        MbarrierExtendedShape::PointerU32ToU64
-        | MbarrierExtendedShape::PointerU64ToI1
-        | MbarrierExtendedShape::PointerU32ToI1 => (2, 1),
-        MbarrierExtendedShape::RawU64ToVoid | MbarrierExtendedShape::U32ToVoid => (1, 0),
-        MbarrierExtendedShape::ZeroToVoid => (0, 0),
-    };
-    if op.get_num_operands() != operands || op.get_num_results() != results {
-        return verify_err!(op.loc(), "{name} has the wrong operand or result count");
-    }
-    match shape {
-        MbarrierExtendedShape::PointerU32ToU64 => {
-            verify_barrier_pointer(ctx, &op, op.get_operand(0))?;
-            if !is_integer(ctx, op.get_operand(1), 32, Signedness::Unsigned)
-                || !is_integer(ctx, op.get_result(0), 64, Signedness::Unsigned)
-            {
-                return verify_err!(op.loc(), "mbarrier arrival requires u32 bytes and a u64 token");
-            }
-        }
-        MbarrierExtendedShape::PointerU64ToI1 => {
-            verify_barrier_pointer(ctx, &op, op.get_operand(0))?;
-            if !is_integer(ctx, op.get_operand(1), 64, Signedness::Unsigned)
-                || !is_integer(ctx, op.get_result(0), 1, Signedness::Signless)
-            {
-                return verify_err!(op.loc(), "mbarrier wait requires a u64 token and i1 result");
-            }
-        }
-        MbarrierExtendedShape::PointerU32ToI1 => {
-            verify_barrier_pointer(ctx, &op, op.get_operand(0))?;
-            if !is_integer(ctx, op.get_operand(1), 32, Signedness::Unsigned)
-                || !is_integer(ctx, op.get_result(0), 1, Signedness::Signless)
-            {
-                return verify_err!(op.loc(), "mbarrier wait requires u32 parity and i1 result");
-            }
-        }
-        MbarrierExtendedShape::RawU64ToVoid => {
-            if !is_integer(ctx, op.get_operand(0), 64, Signedness::Unsigned) {
-                return verify_err!(op.loc(), "remote mbarrier address must be u64");
-            }
-        }
-        MbarrierExtendedShape::U32ToVoid => {
-            if !is_integer(ctx, op.get_operand(0), 32, Signedness::Unsigned) {
-                return verify_err!(op.loc(), "nanosleep duration must be u32");
-            }
-        }
-        MbarrierExtendedShape::ZeroToVoid => {}
-    }
-    Ok(())
-}
-
-"#,
-    );
-    for record in mbarrier_extended(catalog) {
-        let contract = record.mbarrier_extended.as_ref().unwrap();
-        let (operand_count, result_count, shape, build) = match contract.operation {
-            MbarrierExtendedOperation::ArriveExpectTxCta
-            | MbarrierExtendedOperation::ArriveExpectTxCluster => (
-                2,
-                1,
-                "PointerU32ToU64",
-                "    pub fn build(ctx: &mut Context, barrier: Value, bytes: Value) -> Ptr<Operation> {\n        let token_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![token_ty.into()], vec![barrier, bytes], vec![], 0)\n    }\n",
-            ),
-            MbarrierExtendedOperation::ArriveRemoteCluster => (
-                1,
-                0,
-                "RawU64ToVoid",
-                "    pub fn build(ctx: &mut Context, address: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![address], vec![], 0)\n    }\n",
-            ),
-            MbarrierExtendedOperation::TryWaitTokenCta => (
-                2,
-                1,
-                "PointerU64ToI1",
-                "    pub fn build(ctx: &mut Context, barrier: Value, token: Value) -> Ptr<Operation> {\n        let result_ty = IntegerType::get(ctx, 1, Signedness::Signless);\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![result_ty.into()], vec![barrier, token], vec![], 0)\n    }\n",
-            ),
-            MbarrierExtendedOperation::TryWaitParityCta
-            | MbarrierExtendedOperation::TryWaitParityCluster => (
-                2,
-                1,
-                "PointerU32ToI1",
-                "    pub fn build(ctx: &mut Context, barrier: Value, parity: Value) -> Ptr<Operation> {\n        let result_ty = IntegerType::get(ctx, 1, Signedness::Signless);\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![result_ty.into()], vec![barrier, parity], vec![], 0)\n    }\n",
-            ),
-            MbarrierExtendedOperation::FenceProxyAsyncSharedCta
-            | MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster
-            | MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster
-            | MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster => (
-                0,
-                0,
-                "ZeroToVoid",
-                "    pub fn build(ctx: &mut Context) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)\n    }\n",
-            ),
-            MbarrierExtendedOperation::Nanosleep => (
-                1,
-                0,
-                "U32ToVoid",
-                "    pub fn build(ctx: &mut Context, ns: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![ns], vec![], 0)\n    }\n",
-            ),
-        };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<{result_count}>],\n)]\npub struct {};",
-            record.dialect.op_name, record.dialect.op_type
-        )
-        .unwrap();
-        writeln!(output, "impl {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n");
-        output.push_str(build);
-        output.push_str("}\n\n");
-        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_mbarrier_extended(ctx, self.get_operation(), {:?}, MbarrierExtendedShape::{shape})\n    }}\n}}\n",
-            record.dialect.op_name
-        )
-        .unwrap();
-    }
-    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
-    for record in mbarrier_extended(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_warp_match(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operations for the generated `match.sync` family.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_integer_width(ctx: &Context, ty: pliron::r#type::TypeHandle, width: u32) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\n",
-    );
-    for record in warp_matches(catalog) {
-        let warp_match = record.warp_match.as_ref().unwrap();
-        let value_width = warp_match.value_width.bits();
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str(
-            "///\n/// Operands are `[member_mask, value]`; the result is a 32-bit lane mask.\n",
-        );
-        if warp_match.mode == WarpMatchMode::All {
-            output.push_str(
-                "/// LLVM also returns a predicate, which the established API discards.\n",
-            );
-        }
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str(
-            "    pub fn new(op: Ptr<Operation>) -> Self {\n        Self { op }\n    }\n\n    pub fn build(ctx: &mut Context, member_mask: Value, value: Value) -> Ptr<Operation> {\n        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![member_mask, value],\n            vec![],\n            0,\n        )\n    }\n}\n",
-        );
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 2 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_integer_width(ctx, op.get_operand(0).get_type(ctx), 32)\n            || !is_integer_width(ctx, op.get_operand(1).get_type(ctx), {value_width})\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), 32)\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-            format!(
-                "{} requires exactly [member_mask, value] and one mask result",
-                record.dialect.op_name
-            ),
-            format!(
-                "{} requires i32 member mask, i{value_width} value, and i32 result",
-                record.dialect.op_name
-            ),
-        )
-        .unwrap();
-    }
-    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
-    for record in warp_matches(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_warp_barrier(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operation for generated warp synchronization.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::IntegerType,\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\n",
-    );
-    for record in warp_barriers(catalog) {
-        debug_assert_eq!(
-            record.warp_barrier.as_ref().unwrap().adapter,
-            WarpBarrierAdapter::DirectMemberMask
-        );
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("///\n/// The operand is the 32-bit warp participation mask.\n");
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<0>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str(
-            "    pub fn new(op: Ptr<Operation>) -> Self {\n        Self { op }\n    }\n\n    pub fn build(ctx: &mut Context, member_mask: Value) -> Ptr<Operation> {\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![],\n            vec![member_mask],\n            vec![],\n            0,\n        )\n    }\n}\n",
-        );
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 1 || op.get_num_results() != 0 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_i32(ctx, op.get_operand(0).get_type(ctx)) {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-            format!(
-                "{} requires exactly one member-mask operand and no results",
-                record.dialect.op_name
-            ),
-            format!("{} member mask must be i32", record.dialect.op_name),
-        )
-        .unwrap();
-    }
-    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
-    for record in warp_barriers(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_warp_shuffle(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operations for the generated `shfl.sync` family.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{FP32Type, IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\nfn is_i64(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 64)\n}\n\nfn is_f32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx).downcast_ref::<FP32Type>().is_some()\n}\n\n",
-    );
-    for record in warp_shuffles(catalog) {
-        let shuffle = record.warp_shuffle.as_ref().unwrap();
-        debug_assert!(matches!(
-            (shuffle.value_kind, shuffle.adapter),
-            (
-                WarpShuffleValueKind::I32 | WarpShuffleValueKind::F32,
-                WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp
-            ) | (
-                WarpShuffleValueKind::I64,
-                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
-            )
-        ));
-        let (result_builder, value_check, value_label) = match shuffle.value_kind {
-            WarpShuffleValueKind::I32 => (
-                "IntegerType::get(ctx, 32, Signedness::Unsigned).into()",
-                "is_i32",
-                "i32",
-            ),
-            WarpShuffleValueKind::F32 => ("FP32Type::get(ctx).into()", "is_f32", "f32"),
-            WarpShuffleValueKind::I64 => (
-                "IntegerType::get(ctx, 64, Signedness::Unsigned).into()",
-                "is_i64",
-                "i64",
-            ),
-        };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str("///\n/// Operands are `[member_mask, value, lane_or_delta]`.\n");
-        if shuffle.value_kind == WarpShuffleValueKind::I64 {
-            output.push_str(
-                "/// Lowering splits the value into two `b32` halves, shuffles both, and reassembles it.\n",
-            );
-        } else {
-            output.push_str(
-                "/// Generated lowering inserts the fixed clamp required by the selected shuffle mode.\n",
-            );
-        }
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<3>, NResultsInterface<1>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(\n        ctx: &mut Context,\n        member_mask: Value,\n        value: Value,\n        lane_or_delta: Value,\n    ) -> Ptr<Operation> {{\n        let result_ty: pliron::r#type::TypeHandle = {result_builder};\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty],\n            vec![member_mask, value, lane_or_delta],\n            vec![],\n            0,\n        )\n    }}\n}}"
-        )
-        .unwrap();
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 3 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_i32(ctx, op.get_operand(0).get_type(ctx))\n            || !{value_check}(ctx, op.get_operand(1).get_type(ctx))\n            || !is_i32(ctx, op.get_operand(2).get_type(ctx))\n            || !{value_check}(ctx, op.get_result(0).get_type(ctx))\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-            format!(
-                "{} requires exactly [member_mask, value, lane_or_delta] and one result",
-                record.dialect.op_name
-            ),
-            format!(
-                "{} requires i32 mask/lane and {value_label} value/result",
-                record.dialect.op_name
-            ),
-        )
-        .unwrap();
-    }
-    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
-    for record in warp_shuffles(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_dotprod(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operations for generated packed integer dot products.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\n",
-    );
-    for record in dot_products(catalog) {
-        let signedness = match record.rust.result.as_str() {
-            "i32" => "Signed",
-            "u32" => "Unsigned",
-            result => panic!("unsupported dot-product result {result}"),
-        };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "/// Lowers to `{}`.",
-            dot_product_ptx(record).replace("$0, $1, $2, $3", "%d, %a, %b, %c")
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<3>, NResultsInterface<1>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, a: Value, b: Value, c: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, 32, Signedness::{signedness});\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![a, b, c],\n            vec![],\n            0,\n        )\n    }}\n}}"
-        )
-        .unwrap();
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 3 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !(0..3).all(|index| is_i32(ctx, op.get_operand(index).get_type(ctx)))\n            || !is_i32(ctx, op.get_result(0).get_type(ctx))\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-            format!(
-                "{} requires exactly three operands and one result",
-                record.dialect.op_name
-            ),
-            format!(
-                "{} operands and result must be 32-bit integers",
-                record.dialect.op_name
-            ),
-        )
-        .unwrap();
-    }
-    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
-    for record in dot_products(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_redux(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    let has_f32 = redux(catalog).any(|record| record.dialect.results == ["f32"]);
-    if has_f32 {
-        output.push_str(
-            "//! Structural NVVM operations for the closed generated `redux.sync` family.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{FP32Type, IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\nfn is_f32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx).downcast_ref::<FP32Type>().is_some()\n}\n\n",
-        );
-    } else {
-        output.push_str(
-            "//! Structural NVVM operations for the closed generated `redux.sync` family.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\n",
-        );
-    }
-    for record in redux(catalog) {
-        writeln!(output, "/// {}", record.summary).unwrap();
-        output.push_str(
-            "///\n/// Dialect operands are `[member_mask, value]`; generated lowering adapts\n/// them to LLVM's `(value, member_mask)` signature.\n",
-        );
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        let (result_type, value_predicate, type_error) = match record.rust.result.as_str() {
-            "u32" => (
-                "IntegerType::get(ctx, 32, Signedness::Unsigned)",
-                "is_i32",
-                format!(
-                    "{} member mask, value, and result must be 32-bit integers",
-                    record.dialect.op_name
-                ),
-            ),
-            "i32" => (
-                "IntegerType::get(ctx, 32, Signedness::Signed)",
-                "is_i32",
-                format!(
-                    "{} member mask, value, and result must be 32-bit integers",
-                    record.dialect.op_name
-                ),
-            ),
-            "f32" => (
-                "FP32Type::get(ctx)",
-                "is_f32",
-                format!(
-                    "{} member mask must be a 32-bit integer and value and result must be f32",
-                    record.dialect.op_name
-                ),
-            ),
-            result => panic!("unsupported redux result {result}"),
-        };
-        writeln!(
-            output,
-            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, member_mask: Value, value: Value) -> Ptr<Operation> {{\n        let result_ty = {result_type};\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![member_mask, value],\n            vec![],\n            0,\n        )\n    }}\n}}"
-        )
-        .unwrap();
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 2 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_i32(ctx, op.get_operand(0).get_type(ctx))\n            || !{value_predicate}(ctx, op.get_operand(1).get_type(ctx))\n            || !{value_predicate}(ctx, op.get_result(0).get_type(ctx))\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-            format!(
-                "{} requires exactly two operands [member_mask, value] and one result",
-                record.dialect.op_name
-            ),
-            type_error,
-        )
-        .unwrap();
-    }
-    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
-    for record in redux(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_ldmatrix(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r##"//! Structural operation and compatibility carriers for generated `ldmatrix`.
-
-use dialect_mir::types::{address_space, MirPtrType};
-use pliron::{
-    attribute::Attribute,
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        types::{IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[pliron_attr(name = "nvvm.ldmatrix_shape", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum LdmatrixShapeAttr {
-    M8n8,
-    M8n16,
-    M16n16,
-}
-
-impl LdmatrixShapeAttr {
-    pub const fn register_count(&self, multiplicity: &LdmatrixMultiplicityAttr) -> usize {
-        let matrices = multiplicity.register_count();
-        match self {
-            Self::M8n8 | Self::M8n16 => matrices,
-            Self::M16n16 => matrices * 2,
-        }
-    }
-}
-
-#[pliron_attr(name = "nvvm.ldmatrix_multiplicity", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum LdmatrixMultiplicityAttr {
-    X1,
-    X2,
-    X4,
-}
-
-impl LdmatrixMultiplicityAttr {
-    pub const fn register_count(&self) -> usize {
-        match self {
-            Self::X1 => 1,
-            Self::X2 => 2,
-            Self::X4 => 4,
-        }
-    }
-}
-
-#[pliron_attr(name = "nvvm.ldmatrix_layout", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum LdmatrixLayoutAttr {
-    Normal,
-    Transposed,
-}
-
-#[pliron_attr(name = "nvvm.ldmatrix_element", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum LdmatrixElementAttr {
-    B16,
-    B8,
-    B8x16B4x16P64,
-    B8x16B6x16P32,
-}
-
-#[pliron_attr(name = "nvvm.ldmatrix_state_space", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum LdmatrixStateSpaceAttr {
-    Shared,
-}
-
-/// A warp-cooperative matrix load whose exact variant is carried by attributes.
-#[pliron_op(
-    name = "nvvm.ldmatrix",
-    format,
-    interfaces = [NOpdsInterface<1>],
-    attributes = (
-        nvvm_ldmatrix_shape: LdmatrixShapeAttr,
-        nvvm_ldmatrix_multiplicity: LdmatrixMultiplicityAttr,
-        nvvm_ldmatrix_layout: LdmatrixLayoutAttr,
-        nvvm_ldmatrix_element: LdmatrixElementAttr,
-        nvvm_ldmatrix_state_space: LdmatrixStateSpaceAttr
-    )
-)]
-pub struct LdmatrixOp;
-
-impl LdmatrixOp {
-    pub fn new(op: Ptr<Operation>) -> Self {
-        Self { op }
-    }
-
-    pub fn build(
-        ctx: &mut Context,
-        address: Value,
-        shape: LdmatrixShapeAttr,
-        multiplicity: LdmatrixMultiplicityAttr,
-        layout: LdmatrixLayoutAttr,
-        element: LdmatrixElementAttr,
-        state_space: LdmatrixStateSpaceAttr,
-    ) -> Ptr<Operation> {
-        let register_count = shape.register_count(&multiplicity);
-        let u32_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
-        let op = Operation::new(
-            ctx,
-            Self::get_concrete_op_info(),
-            vec![u32_ty.into(); register_count],
-            vec![address],
-            vec![],
-            0,
-        );
-        let this = Self { op };
-        this.set_attr_nvvm_ldmatrix_shape(ctx, shape);
-        this.set_attr_nvvm_ldmatrix_multiplicity(ctx, multiplicity);
-        this.set_attr_nvvm_ldmatrix_layout(ctx, layout);
-        this.set_attr_nvvm_ldmatrix_element(ctx, element);
-        this.set_attr_nvvm_ldmatrix_state_space(ctx, state_space);
-        this.get_operation()
-    }
-}
-
-impl Verify for LdmatrixOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let op = self.get_operation().deref(ctx);
-        let operands: Vec<_> = op.operands().collect();
-        if operands.len() != 1 {
-            return verify_err!(op.loc(), "nvvm.ldmatrix requires exactly one pointer operand");
-        }
-        let pointer = operands[0].get_type(ctx);
-        let pointer_object = pointer.deref(ctx);
-        let Some(pointer) = pointer_object.downcast_ref::<MirPtrType>() else {
-            return verify_err!(op.loc(), "nvvm.ldmatrix operand must be a MIR pointer");
-        };
-        if !matches!(pointer.address_space, address_space::GENERIC | address_space::SHARED) {
-            return verify_err!(
-                op.loc(),
-                "nvvm.ldmatrix pointer must be generic (p0) or shared (p3), not address space {}",
-                pointer.address_space
-            );
-        }
-        let pointee = pointer.pointee.deref(ctx);
-        let Some(pointee) = pointee.downcast_ref::<IntegerType>() else {
-            return verify_err!(op.loc(), "nvvm.ldmatrix pointer must point to an unsigned integer");
-        };
-
-        let Some(shape) = self.get_attr_nvvm_ldmatrix_shape(ctx) else {
-            return verify_err!(op.loc(), "nvvm.ldmatrix requires a shape attribute");
-        };
-        let Some(multiplicity) = self.get_attr_nvvm_ldmatrix_multiplicity(ctx) else {
-            return verify_err!(op.loc(), "nvvm.ldmatrix requires a multiplicity attribute");
-        };
-        let layout = self.get_attr_nvvm_ldmatrix_layout(ctx);
-        let element = self.get_attr_nvvm_ldmatrix_element(ctx);
-        let expected_pointee_width = if element.as_deref() == Some(&LdmatrixElementAttr::B16) {
-            32
-        } else {
-            8
-        };
-        if pointee.width() != expected_pointee_width
-            || pointee.signedness() != Signedness::Unsigned
-        {
-            return verify_err!(
-                op.loc(),
-                "nvvm.ldmatrix pointer element width does not match its matrix element format"
-            );
-        }
-        let supported = matches!(
-            (&*shape, layout.as_deref(), element.as_deref()),
-            (LdmatrixShapeAttr::M8n8, Some(_), Some(LdmatrixElementAttr::B16))
-            |
-            (
-                LdmatrixShapeAttr::M8n16,
-                Some(LdmatrixLayoutAttr::Normal),
-                Some(
-                    LdmatrixElementAttr::B8x16B4x16P64
-                        | LdmatrixElementAttr::B8x16B6x16P32,
-                ),
-            )
-            |
-            (
-                LdmatrixShapeAttr::M16n16,
-                Some(LdmatrixLayoutAttr::Transposed),
-                Some(
-                    LdmatrixElementAttr::B8
-                        | LdmatrixElementAttr::B8x16B4x16P64
-                        | LdmatrixElementAttr::B8x16B6x16P32,
-                ),
-            )
-        );
-        if !supported
-            || (*shape == LdmatrixShapeAttr::M16n16
-                && *multiplicity == LdmatrixMultiplicityAttr::X4)
-            || self.get_attr_nvvm_ldmatrix_state_space(ctx).as_deref()
-                != Some(&LdmatrixStateSpaceAttr::Shared)
-        {
-            return verify_err!(op.loc(), "nvvm.ldmatrix has a missing or unsupported variant attribute");
-        }
-
-        let register_count = shape.register_count(&multiplicity);
-        if op.get_num_results() != register_count {
-            return verify_err!(
-                op.loc(),
-                "nvvm.ldmatrix {:?} requires {} u32 results",
-                multiplicity,
-                register_count
-            );
-        }
-        for index in 0..register_count {
-            let ty = op.get_result(index).get_type(ctx);
-            let ty_object = ty.deref(ctx);
-            let Some(integer) = ty_object.downcast_ref::<IntegerType>() else {
-                return verify_err!(op.loc(), "nvvm.ldmatrix result {} must be u32", index);
-            };
-            if integer.width() != 32 || integer.signedness() != Signedness::Unsigned {
-                return verify_err!(op.loc(), "nvvm.ldmatrix result {} must be u32", index);
-            }
-        }
-        Ok(())
-    }
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    LdmatrixShapeAttr::register(ctx);
-    LdmatrixMultiplicityAttr::register(ctx);
-    LdmatrixLayoutAttr::register(ctx);
-    LdmatrixElementAttr::register(ctx);
-    LdmatrixStateSpaceAttr::register(ctx);
-    LdmatrixOp::register(ctx);
-}
-"##,
-    );
-
-    let compatibility = ldmatrix(catalog)
-        .filter_map(|record| ldmatrix_compat_op(record).map(|compat| (record, compat)))
-        .collect::<Vec<_>>();
-    assert_eq!(compatibility.len(), 6);
-
-    let mut definitions = String::from(
-        r#"
-fn verify_compat_ldmatrix(
-    ctx: &Context,
-    op: Ptr<Operation>,
-    op_name: &str,
-    result_count: usize,
-) -> Result<(), Error> {
-    let op = op.deref(ctx);
-    let operands: Vec<_> = op.operands().collect();
-    if operands.len() != 1 {
-        return verify_err!(op.loc(), "{} requires one shared-memory pointer", op_name);
-    }
-    if operands[0]
-        .get_type(ctx)
-        .deref(ctx)
-        .downcast_ref::<MirPtrType>()
-        .is_none()
-    {
-        return verify_err!(op.loc(), "{} operand 0 must be a MIR pointer", op_name);
-    }
-    if op.get_num_results() != result_count {
-        return verify_err!(
-            op.loc(),
-            "{} requires {} register results",
-            op_name,
-            result_count
-        );
-    }
-    for index in 0..result_count {
-        let ty = op.get_result(index).get_type(ctx);
-        let ty = ty.deref(ctx);
-        let Some(integer) = ty.downcast_ref::<IntegerType>() else {
-            return verify_err!(op.loc(), "{} result {} must be an integer", op_name, index);
-        };
-        if integer.width() != 32 {
-            return verify_err!(op.loc(), "{} result {} must be 32 bits", op_name, index);
-        }
-    }
-    Ok(())
-}
-
-"#,
-    );
-    for (record, (op_type, op_name)) in &compatibility {
-        let result_count = record
-            .ldmatrix
-            .as_ref()
-            .expect("ldmatrix compatibility record")
-            .variant
-            .multiplicity
-            .register_count();
-        writeln!(
-            definitions,
-            "/// Compatibility carrier for `{op_name}`.\n#[pliron_op(\n    name = {op_name:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<{result_count}>],\n)]\npub struct {op_type};\n\nimpl {op_type} {{\n    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n}}\n\nimpl Verify for {op_type} {{\n    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_compat_ldmatrix(ctx, self.get_operation(), {op_name:?}, {result_count})\n    }}\n}}\n"
-        )
-        .unwrap();
-    }
-    let register_start = output
-        .find("pub(super) fn register(ctx: &mut Context) {")
-        .expect("ldmatrix register function");
-    output.insert_str(register_start, &definitions);
-    let register_anchor = "    LdmatrixOp::register(ctx);\n";
-    let mut registrations = String::from(register_anchor);
-    for (_, (op_type, _)) in compatibility {
-        writeln!(registrations, "    {op_type}::register(ctx);").unwrap();
-    }
-    output = output.replacen(register_anchor, &registrations, 1);
-    output
-}
-
-fn render_dialect_stmatrix(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(stmatrices(catalog).count(), 4);
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r#"//! Structural operations for the four generated `stmatrix` stores.
-
-use dialect_mir::types::MirPtrType;
-use pliron::{
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        types::IntegerType,
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    verify_err,
-};
-use pliron_derive::pliron_op;
-
-fn verify_stmatrix_operands(
-    ctx: &Context,
-    op: Ptr<Operation>,
-    op_name: &str,
-    register_count: usize,
-) -> Result<(), Error> {
-    let op = op.deref(ctx);
-    let operands: Vec<_> = op.operands().collect();
-    if operands.len() != register_count + 1 {
-        return verify_err!(
-            op.loc(),
-            "{} requires one pointer and {} register operands",
-            op_name,
-            register_count
-        );
-    }
-    if operands[0]
-        .get_type(ctx)
-        .deref(ctx)
-        .downcast_ref::<MirPtrType>()
-        .is_none()
-    {
-        return verify_err!(op.loc(), "{} operand 0 must be a MIR pointer", op_name);
-    }
-    for (index, register) in operands.iter().enumerate().skip(1) {
-        let ty = register.get_type(ctx);
-        let ty = ty.deref(ctx);
-        let Some(integer) = ty.downcast_ref::<IntegerType>() else {
-            return verify_err!(
-                op.loc(),
-                "{} register operand {} must be an integer",
-                op_name,
-                index - 1
-            );
-        };
-        if integer.width() != 32 {
-            return verify_err!(
-                op.loc(),
-                "{} register operand {} must be 32 bits",
-                op_name,
-                index - 1
-            );
-        }
-    }
-    Ok(())
-}
-
-"#,
-    );
-    for record in stmatrices(catalog) {
-        let (multiplicity, _) = stmatrix_variant(record).expect("stmatrix variant");
-        let count = multiplicity.register_count();
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{}>, NResultsInterface<0>],\n)]",
-            record.dialect.op_name,
-            count + 1
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str(
-            "    pub fn new(op: Ptr<Operation>) -> Self {\n        Self { op }\n    }\n}\n",
-        );
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_stmatrix_operands(ctx, self.get_operation(), {:?}, {count})\n    }}\n}}\n",
-            record.dialect.op_name
-        )
-        .unwrap();
-    }
-    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
-    for record in stmatrices(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn register_mma_carriers(record: &CatalogIntrinsic) -> (&'static str, &'static str) {
-    match record.register_mma.as_ref().unwrap().adapter {
-        RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32 => (
-            "&[MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
-            "&[MmaCarrier::U32, MmaCarrier::U32]",
-        ),
-        RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => (
-            "&[MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
-            "&[MmaCarrier::U32, MmaCarrier::U32]",
-        ),
-        RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32 => (
-            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
-            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32]",
-        ),
-        RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32 => (
-            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
-            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32]",
-        ),
-        RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => (
-            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U16, MmaCarrier::U16, MmaCarrier::U32, MmaCarrier::U16, MmaCarrier::U16]",
-            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32]",
-        ),
-        RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 => (
-            "&[MmaCarrier::F64, MmaCarrier::F64, MmaCarrier::F64, MmaCarrier::F64]",
-            "&[MmaCarrier::F64, MmaCarrier::F64]",
-        ),
-        RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32 => (
-            "&[MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::U32, MmaCarrier::U32]",
-            "&[MmaCarrier::I32, MmaCarrier::I32]",
-        ),
-        RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32 => (
-            "&[MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
-            "&[MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32]",
-        ),
-        RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => (
-            "&[MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
-            "&[MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32]",
-        ),
-    }
-}
-
-fn register_mma_compat_op_type(record: &CatalogIntrinsic) -> Option<&'static str> {
-    match record.id.as_str() {
-        "mma_m16n8k16_f32_bf16" => Some("MmaM16N8K16F32Bf16Op"),
-        "mma_m16n8k16_f32_f16" => Some("MmaM16N8K16F32F16Op"),
-        "mma_m16n8k8_f32_tf32" => Some("MmaM16N8K8F32Tf32Op"),
-        "mma_m16n8k32_s32_s8" => Some("MmaM16N8K32S32S8Op"),
-        "mma_m8n8k4_f64" => Some("MmaM8N8K4F64Op"),
-        _ => None,
-    }
-}
-
-fn render_dialect_register_mma(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r#"//! One structural operation for generated register-only `mma.sync` variants.
-
-use pliron::{
-    attribute::Attribute,
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        types::{FP32Type, FP64Type, IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::{TypeHandle, Typed},
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[pliron_attr(name = "nvvm.register_mma_shape", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum RegisterMmaShapeAttr { M8n8k4, M8n8k16, M8n8k32, M8n8k128, M16n8k4, M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128, M16n8k256 }
-
-#[pliron_attr(name = "nvvm.register_mma_operation", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum RegisterMmaOperationAttr { Multiply, AndPopc, XorPopc }
-
-#[pliron_attr(name = "nvvm.register_mma_kind", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum RegisterMmaKindAttr { Standard, F8f6f4, Mxf8f6f4 }
-
-#[pliron_attr(name = "nvvm.register_mma_accumulator", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum RegisterMmaAccumulatorAttr { F16, F32, F64, S32 }
-
-#[pliron_attr(name = "nvvm.register_mma_element", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum RegisterMmaElementAttr { Bf16, E2m1, E2m3, E3m2, E4m3, E5m2, F16, Tf32, F64, B1, S4, U4, S8, U8 }
-
-#[pliron_attr(name = "nvvm.register_mma_layout", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum RegisterMmaLayoutAttr { Row, Col }
-
-#[pliron_attr(name = "nvvm.register_mma_overflow", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum RegisterMmaOverflowAttr { NotApplicable, Wrapping, Satfinite }
-
-#[pliron_op(
-    name = "nvvm.register_mma",
-    format,
-    attributes = (
-        nvvm_register_mma_shape: RegisterMmaShapeAttr,
-        nvvm_register_mma_operation: RegisterMmaOperationAttr,
-        nvvm_register_mma_kind: RegisterMmaKindAttr,
-        nvvm_register_mma_accumulator: RegisterMmaAccumulatorAttr,
-        nvvm_register_mma_a_element: RegisterMmaElementAttr,
-        nvvm_register_mma_b_element: RegisterMmaElementAttr,
-        nvvm_register_mma_a_layout: RegisterMmaLayoutAttr,
-        nvvm_register_mma_b_layout: RegisterMmaLayoutAttr,
-        nvvm_register_mma_overflow: RegisterMmaOverflowAttr
-    )
-)]
-pub struct RegisterMmaOp;
-
-impl RegisterMmaOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-
-    /// Defaults older multiply-only IR to multiply.
-    pub fn operation_or_multiply(&self, ctx: &Context) -> RegisterMmaOperationAttr {
-        self.get_attr_nvvm_register_mma_operation(ctx)
-            .as_deref()
-            .cloned()
-            .unwrap_or(RegisterMmaOperationAttr::Multiply)
-    }
-
-    /// Infers the kind used by older generated IR.
-    pub fn kind_or_inferred(&self, ctx: &Context) -> RegisterMmaKindAttr {
-        if let Some(kind) = self.get_attr_nvvm_register_mma_kind(ctx).as_deref() {
-            return kind.clone();
-        }
-        let low_format = |element: Option<&RegisterMmaElementAttr>| {
-            matches!(
-                element,
-                Some(
-                    RegisterMmaElementAttr::E2m1
-                        | RegisterMmaElementAttr::E2m3
-                        | RegisterMmaElementAttr::E3m2
-                        | RegisterMmaElementAttr::E4m3
-                        | RegisterMmaElementAttr::E5m2
-                )
-            )
-        };
-        let old_f8f6f4 = self.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-            == Some(&RegisterMmaShapeAttr::M16n8k32)
-            && low_format(self.get_attr_nvvm_register_mma_a_element(ctx).as_deref())
-            && low_format(self.get_attr_nvvm_register_mma_b_element(ctx).as_deref());
-        if old_f8f6f4 {
-            RegisterMmaKindAttr::F8f6f4
-        } else {
-            RegisterMmaKindAttr::Standard
-        }
-    }
-}
-
-#[derive(Clone, Copy)]
-enum MmaCarrier { F32, F64, I32, U16, U32 }
-
-fn is_carrier(ctx: &Context, ty: TypeHandle, carrier: MmaCarrier) -> bool {
-    match carrier {
-        MmaCarrier::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
-        MmaCarrier::F64 => ty.deref(ctx).downcast_ref::<FP64Type>().is_some(),
-        MmaCarrier::I32 | MmaCarrier::U16 | MmaCarrier::U32 => {
-            let expected = if matches!(carrier, MmaCarrier::I32) {
-                Signedness::Signed
-            } else {
-                Signedness::Unsigned
-            };
-            ty.deref(ctx)
-                .downcast_ref::<IntegerType>()
-                .is_some_and(|integer| {
-                    integer.width()
-                        == if matches!(carrier, MmaCarrier::U16) { 16 } else { 32 }
-                        && integer.signedness() == expected
-                })
-        }
-    }
-}
-
-impl Verify for RegisterMmaOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let op = self.get_operation().deref(ctx);
-        let operation = self.operation_or_multiply(ctx);
-        let kind = self.kind_or_inferred(ctx);
-        let recipe: (&[MmaCarrier], &[MmaCarrier]) = match (
-            self.get_attr_nvvm_register_mma_shape(ctx).as_deref(),
-            operation,
-            kind,
-            self.get_attr_nvvm_register_mma_accumulator(ctx).as_deref(),
-            self.get_attr_nvvm_register_mma_a_element(ctx).as_deref(),
-            self.get_attr_nvvm_register_mma_b_element(ctx).as_deref(),
-            self.get_attr_nvvm_register_mma_a_layout(ctx).as_deref(),
-            self.get_attr_nvvm_register_mma_b_layout(ctx).as_deref(),
-            self.get_attr_nvvm_register_mma_overflow(ctx).as_deref(),
-        ) {
-"#,
-    );
-    for record in register_mmas(catalog) {
-        let (
-            shape,
-            operation,
-            kind,
-            accumulator,
-            a_element,
-            b_element,
-            a_layout,
-            b_layout,
-            overflow,
-        ) = register_mma_attr_variants(record);
-        let (operands, results) = register_mma_carriers(record);
-        writeln!(
-            output,
-            "            (Some(&{shape}), {operation}, {kind}, Some(&{accumulator}), Some(&{a_element}), Some(&{b_element}), Some(&{a_layout}), Some(&{b_layout}), Some(&{overflow})) => ({operands}, {results}),"
-        )
-        .unwrap();
-    }
-    output.push_str(
-        r#"            _ => return verify_err!(op.loc(), "nvvm.register_mma has a missing or unsupported variant"),
-        };
-        let operands: Vec<_> = op.operands().collect();
-        if operands.len() != recipe.0.len() || op.get_num_results() != recipe.1.len() {
-            return verify_err!(op.loc(), "nvvm.register_mma has the wrong register count");
-        }
-        for (index, (operand, carrier)) in operands.iter().zip(recipe.0).enumerate() {
-            if !is_carrier(ctx, operand.get_type(ctx), *carrier) {
-                return verify_err!(op.loc(), "nvvm.register_mma operand {} has the wrong carrier type", index);
-            }
-        }
-        for (index, carrier) in recipe.1.iter().enumerate() {
-            if !is_carrier(ctx, op.get_result(index).get_type(ctx), *carrier) {
-                return verify_err!(op.loc(), "nvvm.register_mma result {} has the wrong carrier type", index);
-            }
-        }
-        Ok(())
-    }
-}
-
-"#,
-    );
-    output.push_str(
-        r#"
-fn is_compat_carrier(ctx: &Context, ty: TypeHandle, carrier: MmaCarrier) -> bool {
-    match carrier {
-        MmaCarrier::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
-        MmaCarrier::F64 => ty.deref(ctx).downcast_ref::<FP64Type>().is_some(),
-        MmaCarrier::I32 | MmaCarrier::U16 | MmaCarrier::U32 => {
-            let expected_width = if matches!(carrier, MmaCarrier::U16) {
-                16
-            } else {
-                32
-            };
-            ty.deref(ctx)
-                .downcast_ref::<IntegerType>()
-                .is_some_and(|integer| integer.width() == expected_width)
-        }
-    }
-}
-
-fn verify_compat_register_mma(
-    ctx: &Context,
-    op_ptr: Ptr<Operation>,
-    op_name: &str,
-    operand_carriers: &[MmaCarrier],
-    result_carriers: &[MmaCarrier],
-) -> Result<(), Error> {
-    let op = op_ptr.deref(ctx);
-    let operands: Vec<_> = op.operands().collect();
-    if operands.len() != operand_carriers.len() || op.get_num_results() != result_carriers.len() {
-        return verify_err!(op.loc(), "{} has the wrong register count", op_name);
-    }
-    for (index, (operand, carrier)) in operands.iter().zip(operand_carriers).enumerate() {
-        if !is_compat_carrier(ctx, operand.get_type(ctx), *carrier) {
-            return verify_err!(op.loc(), "{} operand {} has the wrong carrier type", op_name, index);
-        }
-    }
-    for (index, carrier) in result_carriers.iter().enumerate() {
-        if !is_compat_carrier(ctx, op.get_result(index).get_type(ctx), *carrier) {
-            return verify_err!(op.loc(), "{} result {} has the wrong carrier type", op_name, index);
-        }
-    }
-    Ok(())
-}
-
-"#,
-    );
-    for record in
-        register_mmas(catalog).filter(|record| register_mma_compat_op_type(record).is_some())
-    {
-        let op_type = register_mma_compat_op_type(record).unwrap();
-        let op_name = format!("nvvm.{}", record.id);
-        let operand_count = record.dialect.operands.len();
-        let result_count = record.dialect.results.len();
-        let (operands, results) = register_mma_carriers(record);
-        writeln!(output, "/// Compatibility carrier for `{}`.", record.id).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {op_name:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<{result_count}>],\n)]\npub struct {op_type};\n"
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "impl {op_type} {{\n    pub fn new(op: Ptr<Operation>) -> Self {{ Self {{ op }} }}\n}}\n"
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "impl Verify for {op_type} {{\n    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_compat_register_mma(ctx, self.get_operation(), {op_name:?}, {operands}, {results})\n    }}\n}}\n"
-        )
-        .unwrap();
-    }
-    output.push_str(
-        "pub(super) fn register(ctx: &mut Context) {\n    RegisterMmaShapeAttr::register(ctx);\n    RegisterMmaOperationAttr::register(ctx);\n    RegisterMmaKindAttr::register(ctx);\n    RegisterMmaAccumulatorAttr::register(ctx);\n    RegisterMmaElementAttr::register(ctx);\n    RegisterMmaLayoutAttr::register(ctx);\n    RegisterMmaOverflowAttr::register(ctx);\n    RegisterMmaOp::register(ctx);\n",
-    );
-    for record in
-        register_mmas(catalog).filter(|record| register_mma_compat_op_type(record).is_some())
-    {
-        writeln!(
-            output,
-            "    {}::register(ctx);",
-            register_mma_compat_op_type(record).unwrap()
-        )
-        .unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_sparse_mma(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r#"//! One structural operation for generated sparse MMA variants.
-
-use dialect_mir::ops::MirConstantOp;
-use pliron::{
-    attribute::Attribute,
-    builtin::{attributes::IntegerAttr, ops::ConstantOp, types::{FP32Type, IntegerType, Signedness}},
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::{TypeHandle, Typed},
-    value::Value,
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[pliron_attr(name = "nvvm.sparse_mma_shape", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum SparseMmaShapeAttr { M16n8k32, M16n8k64, M16n8k128 }
-
-#[pliron_attr(name = "nvvm.sparse_mma_accumulator", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum SparseMmaAccumulatorAttr { F16, F32, S32 }
-
-#[pliron_attr(name = "nvvm.sparse_mma_element", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum SparseMmaElementAttr { E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 }
-
-#[pliron_attr(name = "nvvm.sparse_mma_layout", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum SparseMmaLayoutAttr { Row, Col }
-
-#[pliron_attr(name = "nvvm.sparse_mma_overflow", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum SparseMmaOverflowAttr { NotApplicable, Wrapping, Satfinite }
-
-#[pliron_attr(name = "nvvm.sparse_mma_metadata", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum SparseMmaMetadataAttr { Standard, Ordered }
-
-#[pliron_attr(name = "nvvm.sparse_mma_selector", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum SparseMmaSelectorAttr { ImmediateZeroOrOne, ImmediateZero }
-
-#[pliron_op(
-    name = "nvvm.sparse_mma",
-    format,
-    attributes = (
-        nvvm_sparse_mma_shape: SparseMmaShapeAttr,
-        nvvm_sparse_mma_accumulator: SparseMmaAccumulatorAttr,
-        nvvm_sparse_mma_a_element: SparseMmaElementAttr,
-        nvvm_sparse_mma_b_element: SparseMmaElementAttr,
-        nvvm_sparse_mma_a_layout: SparseMmaLayoutAttr,
-        nvvm_sparse_mma_b_layout: SparseMmaLayoutAttr,
-        nvvm_sparse_mma_overflow: SparseMmaOverflowAttr,
-        nvvm_sparse_mma_metadata: SparseMmaMetadataAttr,
-        nvvm_sparse_mma_selector: SparseMmaSelectorAttr
-    )
-)]
-pub struct SparseMmaOp;
-
-impl SparseMmaOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-}
-
-#[derive(Clone, Copy)]
-enum MmaCarrier { F32, I32, U32 }
-
-fn is_carrier(ctx: &Context, ty: TypeHandle, carrier: MmaCarrier) -> bool {
-    match carrier {
-        MmaCarrier::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
-        MmaCarrier::I32 | MmaCarrier::U32 => {
-            let expected = if matches!(carrier, MmaCarrier::I32) {
-                Signedness::Signed
-            } else {
-                Signedness::Unsigned
-            };
-            ty.deref(ctx)
-                .downcast_ref::<IntegerType>()
-                .is_some_and(|integer| integer.width() == 32 && integer.signedness() == expected)
-        }
-    }
-}
-
-fn constant_u32(ctx: &Context, value: Value) -> Option<u64> {
-    let defining_op = value.defining_op()?;
-    if let Some(constant) = Operation::get_op::<MirConstantOp>(defining_op, ctx) {
-        return constant.get_attr_value(ctx).map(|value| value.value().to_u64());
-    }
-    let constant = Operation::get_op::<ConstantOp>(defining_op, ctx)?;
-    constant
-        .get_value(ctx)
-        .downcast_ref::<IntegerAttr>()
-        .map(|value| value.value().to_u64())
-}
-
-impl Verify for SparseMmaOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let op = self.get_operation().deref(ctx);
-        let (expected_operands, expected_results, selector_upper_exclusive): (&[MmaCarrier], &[MmaCarrier], usize) = match (
-            self.get_attr_nvvm_sparse_mma_shape(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_selector(ctx).as_deref(),
-        ) {
-"#,
-    );
-    for record in sparse_mmas(catalog) {
-        let (
-            shape,
-            accumulator,
-            a_element,
-            b_element,
-            a_layout,
-            b_layout,
-            overflow,
-            metadata,
-            selector,
-        ) = sparse_mma_attr_variants(record);
-        let (expected_operands, expected_results) = sparse_mma_carriers(record);
-        let selector_upper_exclusive = sparse_mma_selector_values(record).len();
-        writeln!(
-            output,
-            "            (Some(&{shape}), Some(&{accumulator}), Some(&{a_element}), Some(&{b_element}), Some(&{a_layout}), Some(&{b_layout}), Some(&{overflow}), Some(&{metadata}), Some(&{selector})) => ({expected_operands}, {expected_results}, {selector_upper_exclusive}),"
-        )
-        .unwrap();
-    }
-    output.push_str(
-        r#"            _ => return verify_err!(op.loc(), "nvvm.sparse_mma has a missing or unsupported variant"),
-        };
-        let operands: Vec<_> = op.operands().collect();
-        if operands.len() != expected_operands.len() || op.get_num_results() != expected_results.len() {
-            return verify_err!(op.loc(), "nvvm.sparse_mma has the wrong register count");
-        }
-        for (index, (operand, carrier)) in operands.iter().zip(expected_operands).enumerate() {
-            if !is_carrier(ctx, operand.get_type(ctx), *carrier) {
-                return verify_err!(op.loc(), "nvvm.sparse_mma operand {} has the wrong carrier type", index);
-            }
-        }
-        for (index, carrier) in expected_results.iter().enumerate() {
-            if !is_carrier(ctx, op.get_result(index).get_type(ctx), *carrier) {
-                return verify_err!(op.loc(), "nvvm.sparse_mma result {} has the wrong carrier type", index);
-            }
-        }
-        if constant_u32(ctx, operands[expected_operands.len() - 1])
-            .is_none_or(|selector| selector >= selector_upper_exclusive as u64)
-        {
-            return verify_err!(op.loc(), "nvvm.sparse_mma selector must be a compile-time constant in 0..{}", selector_upper_exclusive);
-        }
-        Ok(())
-    }
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    SparseMmaShapeAttr::register(ctx);
-    SparseMmaAccumulatorAttr::register(ctx);
-    SparseMmaElementAttr::register(ctx);
-    SparseMmaLayoutAttr::register(ctx);
-    SparseMmaOverflowAttr::register(ctx);
-    SparseMmaMetadataAttr::register(ctx);
-    SparseMmaSelectorAttr::register(ctx);
-    SparseMmaOp::register(ctx);
-}
-"#,
-    );
-    output
-}
-
-fn render_dialect_packed_atomic(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r##"//! One structural operation for the closed generated packed-atomic family.
-
-use dialect_mir::types::{address_space, MirPtrType};
-use pliron::{
-    attribute::Attribute,
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        types::{IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[pliron_attr(name = "nvvm.packed_atomic_format", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum PackedAtomicFormatAttr { F16x2, Bf16x2 }
-
-#[pliron_attr(name = "nvvm.packed_atomic_state_space", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum PackedAtomicStateSpaceAttr { Global }
-
-#[pliron_attr(name = "nvvm.packed_atomic_ordering", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum PackedAtomicOrderingAttr { Relaxed }
-
-#[pliron_attr(name = "nvvm.packed_atomic_scope", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum PackedAtomicScopeAttr { Gpu }
-
-#[pliron_attr(name = "nvvm.packed_atomic_rounding", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum PackedAtomicRoundingAttr { Rn }
-
-#[pliron_attr(name = "nvvm.packed_atomic_subnormal", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum PackedAtomicSubnormalAttr { NoFtz }
-
-#[pliron_attr(name = "nvvm.packed_atomic_atomicity", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum PackedAtomicAtomicityAttr { PerElement }
-
-/// Packed global atomic add with exact format and semantic attributes.
-#[pliron_op(
-    name = "nvvm.packed_atomic_add",
-    format,
-    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
-    attributes = (
-        nvvm_packed_atomic_format: PackedAtomicFormatAttr,
-        nvvm_packed_atomic_state_space: PackedAtomicStateSpaceAttr,
-        nvvm_packed_atomic_ordering: PackedAtomicOrderingAttr,
-        nvvm_packed_atomic_scope: PackedAtomicScopeAttr,
-        nvvm_packed_atomic_rounding: PackedAtomicRoundingAttr,
-        nvvm_packed_atomic_subnormal: PackedAtomicSubnormalAttr,
-        nvvm_packed_atomic_atomicity: PackedAtomicAtomicityAttr
-    )
-)]
-pub struct PackedAtomicAddOp;
-
-impl PackedAtomicAddOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-
-    pub fn build(
-        ctx: &mut Context,
-        address: Value,
-        addend: Value,
-        format: PackedAtomicFormatAttr,
-    ) -> Ptr<Operation> {
-        let u32_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
-        let op = Operation::new(
-            ctx,
-            Self::get_concrete_op_info(),
-            vec![u32_ty.into()],
-            vec![address, addend],
-            vec![],
-            0,
-        );
-        let this = Self { op };
-        this.set_attr_nvvm_packed_atomic_format(ctx, format);
-        this.set_attr_nvvm_packed_atomic_state_space(ctx, PackedAtomicStateSpaceAttr::Global);
-        this.set_attr_nvvm_packed_atomic_ordering(ctx, PackedAtomicOrderingAttr::Relaxed);
-        this.set_attr_nvvm_packed_atomic_scope(ctx, PackedAtomicScopeAttr::Gpu);
-        this.set_attr_nvvm_packed_atomic_rounding(ctx, PackedAtomicRoundingAttr::Rn);
-        this.set_attr_nvvm_packed_atomic_subnormal(ctx, PackedAtomicSubnormalAttr::NoFtz);
-        this.set_attr_nvvm_packed_atomic_atomicity(ctx, PackedAtomicAtomicityAttr::PerElement);
-        this.get_operation()
-    }
-}
-
-fn is_u32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {
-    ty.deref(ctx).downcast_ref::<IntegerType>().is_some_and(|integer| {
-        integer.width() == 32 && integer.signedness() == Signedness::Unsigned
-    })
-}
-
-fn verify_packed_atomic_signature(
-    ctx: &Context,
-    op_ptr: Ptr<Operation>,
-    op_name: &str,
-) -> Result<(), Error> {
-    let op = op_ptr.deref(ctx);
-    if op.get_num_operands() != 2 || op.get_num_results() != 1 {
-        return verify_err!(op.loc(), "{} requires exactly two operands and one result", op_name);
-    }
-    let pointer_ty = op.get_operand(0).get_type(ctx);
-    let pointer_object = pointer_ty.deref(ctx);
-    let Some(pointer) = pointer_object.downcast_ref::<MirPtrType>() else {
-        return verify_err!(op.loc(), "{} address must be a MIR pointer", op_name);
-    };
-    if !pointer.is_mutable()
-        || !matches!(pointer.address_space(), address_space::GENERIC | address_space::GLOBAL)
-        || !is_u32(ctx, pointer.pointee)
-    {
-        return verify_err!(op.loc(), "{} address must be a mutable generic/global pointer to u32", op_name);
-    }
-    if !is_u32(ctx, op.get_operand(1).get_type(ctx)) || !is_u32(ctx, op.get_result(0).get_type(ctx)) {
-        return verify_err!(op.loc(), "{} addend and result must be u32", op_name);
-    }
-    Ok(())
-}
-
-impl Verify for PackedAtomicAddOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        verify_packed_atomic_signature(ctx, self.get_operation(), "nvvm.packed_atomic_add")?;
-        let op = self.get_operation().deref(ctx);
-        if self.get_attr_nvvm_packed_atomic_format(ctx).is_none()
-            || self.get_attr_nvvm_packed_atomic_state_space(ctx).as_deref() != Some(&PackedAtomicStateSpaceAttr::Global)
-            || self.get_attr_nvvm_packed_atomic_ordering(ctx).as_deref() != Some(&PackedAtomicOrderingAttr::Relaxed)
-            || self.get_attr_nvvm_packed_atomic_scope(ctx).as_deref() != Some(&PackedAtomicScopeAttr::Gpu)
-            || self.get_attr_nvvm_packed_atomic_rounding(ctx).as_deref() != Some(&PackedAtomicRoundingAttr::Rn)
-            || self.get_attr_nvvm_packed_atomic_subnormal(ctx).as_deref() != Some(&PackedAtomicSubnormalAttr::NoFtz)
-            || self.get_attr_nvvm_packed_atomic_atomicity(ctx).as_deref() != Some(&PackedAtomicAtomicityAttr::PerElement)
-        {
-            return verify_err!(op.loc(), "nvvm.packed_atomic_add has a missing or unsupported semantic attribute");
-        }
-        Ok(())
-    }
-}
-
-/// Compatibility operation for the existing `nvvm.atom_add_f16x2` carrier.
-#[pliron_op(
-    name = "nvvm.atom_add_f16x2",
-    format,
-    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
-)]
-pub struct NvvmAtomAddF16x2Op;
-
-impl NvvmAtomAddF16x2Op {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-}
-
-impl Verify for NvvmAtomAddF16x2Op {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        verify_packed_atomic_signature(ctx, self.get_operation(), "nvvm.atom_add_f16x2")
-    }
-}
-
-/// Compatibility operation for the existing `nvvm.atom_add_bf16x2` carrier.
-#[pliron_op(
-    name = "nvvm.atom_add_bf16x2",
-    format,
-    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
-)]
-pub struct NvvmAtomAddBf16x2Op;
-
-impl NvvmAtomAddBf16x2Op {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-}
-
-impl Verify for NvvmAtomAddBf16x2Op {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        verify_packed_atomic_signature(ctx, self.get_operation(), "nvvm.atom_add_bf16x2")
-    }
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    PackedAtomicFormatAttr::register(ctx);
-    PackedAtomicStateSpaceAttr::register(ctx);
-    PackedAtomicOrderingAttr::register(ctx);
-    PackedAtomicScopeAttr::register(ctx);
-    PackedAtomicRoundingAttr::register(ctx);
-    PackedAtomicSubnormalAttr::register(ctx);
-    PackedAtomicAtomicityAttr::register(ctx);
-    PackedAtomicAddOp::register(ctx);
-    NvvmAtomAddF16x2Op::register(ctx);
-    NvvmAtomAddBf16x2Op::register(ctx);
-}
-"##,
-    );
-    output
-}
-
-fn render_dialect_packed_alu(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operations for generated packed floating-point arithmetic.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_integer_width(\n    ctx: &Context,\n    ty: pliron::r#type::TypeHandle,\n    width: u32,\n) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\n",
-    );
-    for record in packed_alus(catalog) {
-        let arity = record.rust.arguments.len();
-        let width = packed_alu_width(record);
-        let parameters = (0..arity)
-            .map(|index| format!("arg{index}: Value"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let operands = (0..arity)
-            .map(|index| format!("arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "///\n/// Lowers to `{}`.",
-            packed_alu_ptx_mnemonic(record)
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{arity}>, NResultsInterface<1>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, {parameters}) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, {width}, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![{operands}],\n            vec![],\n            0,\n        )\n    }}\n}}"
-        )
-        .unwrap();
-        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-        writeln!(
-            output,
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != {arity} || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !(0..{arity}).all(|index| is_integer_width(ctx, op.get_operand(index).get_type(ctx), {width}))\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), {width})\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-            format!(
-                "{} requires exactly {arity} operands and one result",
-                record.dialect.op_name
-            ),
-            format!(
-                "{} operands and result must be {width}-bit integers",
-                record.dialect.op_name,
-            ),
-        )
-        .unwrap();
-    }
-    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
-    for record in packed_alus(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_packed_conversion(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operation for generated packed conversion.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{FP32Type, IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_f32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx).downcast_ref::<FP32Type>().is_some()\n}\n\nfn is_integer_width(\n    ctx: &Context,\n    ty: pliron::r#type::TypeHandle,\n    width: u32,\n) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\n",
-    );
-    for record in packed_conversions(catalog) {
-        let result_width = packed_conversion_result_width(record);
-        writeln!(output, "/// {}", record.summary).unwrap();
-        match packed_conversion_source(record) {
-            PackedConversionSourceFormat::F32x2 => {
-                writeln!(
-                    output,
-                    "///\n/// The first input becomes the low {} lane; the second becomes the high lane.",
-                    packed_conversion_element(record)
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],\n)]",
-                    record.dialect.op_name
-                )
-                .unwrap();
-                writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-                writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-                writeln!(
-                    output,
-                    "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, low: Value, high: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, {result_width}, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![low, high],\n            vec![],\n            0,\n        )\n    }}\n}}",
-                )
-                .unwrap();
-                writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-                writeln!(
-                    output,
-                    "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 2 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_f32(ctx, op.get_operand(0).get_type(ctx))\n            || !is_f32(ctx, op.get_operand(1).get_type(ctx))\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), {})\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-                    format!("{} requires two operands and one result", record.dialect.op_name),
-                    result_width,
-                    format!(
-                        "{} requires f32 operands and one {result_width}-bit integer result",
-                        record.dialect.op_name,
-                    ),
-                )
-                .unwrap();
-            }
-            PackedConversionSourceFormat::E4m3x2
-            | PackedConversionSourceFormat::E5m2x2
-            | PackedConversionSourceFormat::F16x2 => {
-                let source_width = packed_conversion_source_width(record);
-                writeln!(
-                    output,
-                    "///\n/// The single input carries both packed lanes, and lane order is preserved."
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<1>],\n)]",
-                    record.dialect.op_name
-                )
-                .unwrap();
-                writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-                writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-                writeln!(
-                    output,
-                    "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, packed: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, {result_width}, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![packed],\n            vec![],\n            0,\n        )\n    }}\n}}",
-                )
-                .unwrap();
-                writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
-                writeln!(
-                    output,
-                    "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 1 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_integer_width(ctx, op.get_operand(0).get_type(ctx), {source_width})\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), {result_width})\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
-                    format!("{} requires one operand and one result", record.dialect.op_name),
-                    format!(
-                        "{} requires one {source_width}-bit integer operand and one {result_width}-bit integer result",
-                        record.dialect.op_name,
-                    ),
-                )
-                .unwrap();
-            }
-        }
-    }
-    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
-    for record in packed_conversions(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_scalar_conversion(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r##"//! One structural operation for generated `f32` to TF32 conversions.
-
-use pliron::{
-    attribute::Attribute,
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        types::{FP32Type, IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[pliron_attr(name = "nvvm.scalar_conversion_rounding", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarConversionRoundingAttr {
-    NearestAway,
-    NearestEven,
-    TowardZero,
-}
-
-#[pliron_attr(name = "nvvm.scalar_conversion_saturation", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarConversionSaturationAttr {
-    None,
-    Relu,
-    Satfinite,
-    ReluSatfinite,
-}
-
-/// Converts one `f32` value and returns the raw TF32 bits.
-#[pliron_op(
-    name = "nvvm.scalar_conversion",
-    format,
-    interfaces = [NOpdsInterface<1>, NResultsInterface<1>],
-    attributes = (
-        nvvm_scalar_conversion_rounding: ScalarConversionRoundingAttr,
-        nvvm_scalar_conversion_saturation: ScalarConversionSaturationAttr
-    )
-)]
-pub struct ScalarConversionOp;
-
-impl ScalarConversionOp {
-    pub fn new(op: Ptr<Operation>) -> Self {
-        Self { op }
-    }
-
-    pub fn build(
-        ctx: &mut Context,
-        value: Value,
-        rounding: ScalarConversionRoundingAttr,
-        saturation: ScalarConversionSaturationAttr,
-    ) -> Ptr<Operation> {
-        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
-        let op = Operation::new(
-            ctx,
-            Self::get_concrete_op_info(),
-            vec![result_ty.into()],
-            vec![value],
-            vec![],
-            0,
-        );
-        let this = Self { op };
-        this.set_attr_nvvm_scalar_conversion_rounding(ctx, rounding);
-        this.set_attr_nvvm_scalar_conversion_saturation(ctx, saturation);
-        this.get_operation()
-    }
-}
-
-impl Verify for ScalarConversionOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let op = self.get_operation().deref(ctx);
-        let Some(rounding) = self.get_attr_nvvm_scalar_conversion_rounding(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_conversion requires rounding");
-        };
-        let Some(saturation) = self.get_attr_nvvm_scalar_conversion_saturation(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_conversion requires saturation");
-        };
-        let admitted = matches!(
-            (&*rounding, &*saturation),
-"##,
-    );
-    for (index, record) in scalar_conversions(catalog).enumerate() {
-        if index != 0 {
-            output.push_str(" |\n");
-        }
-        writeln!(
-            output,
-            "            ({}, {})",
-            scalar_conversion_rounding_attr(record),
-            scalar_conversion_saturation_attr(record),
-        )
-        .unwrap();
-    }
-    output.push_str(
-        r##"        );
-        if !admitted {
-            return verify_err!(op.loc(), "nvvm.scalar_conversion variant is not admitted");
-        }
-        if op
-            .get_operand(0)
-            .get_type(ctx)
-            .deref(ctx)
-            .downcast_ref::<FP32Type>()
-            .is_none()
-        {
-            return verify_err!(op.loc(), "nvvm.scalar_conversion operand must be f32");
-        }
-        if op
-            .get_result(0)
-            .get_type(ctx)
-            .deref(ctx)
-            .downcast_ref::<IntegerType>()
-            .is_none_or(|integer| integer.width() != 32)
-        {
-            return verify_err!(op.loc(), "nvvm.scalar_conversion result must be a 32-bit integer");
-        }
-        Ok(())
-    }
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    ScalarConversionRoundingAttr::register(ctx);
-    ScalarConversionSaturationAttr::register(ctx);
-    ScalarConversionOp::register(ctx);
-}
-"##,
-    );
-    output
-}
-
-fn render_dialect_scalar_arithmetic(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r##"//! One structural operation for generated scalar arithmetic.
-
-use pliron::{
-    attribute::Attribute,
-    builtin::{op_interfaces::NResultsInterface, types::{FP32Type, FP64Type}},
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[pliron_attr(name = "nvvm.scalar_arithmetic_format", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarArithmeticFormatAttr { F32, F64 }
-
-#[pliron_attr(name = "nvvm.scalar_arithmetic_operation", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarArithmeticOperationAttr { Mul, Div, Fma, Add }
-
-#[pliron_attr(name = "nvvm.scalar_arithmetic_rounding", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarArithmeticRoundingAttr { Rn, Rz, Rm, Rp }
-
-#[pliron_attr(name = "nvvm.scalar_arithmetic_subnormal", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarArithmeticSubnormalAttr { Preserve, Ftz }
-
-#[pliron_attr(name = "nvvm.scalar_arithmetic_saturation", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarArithmeticSaturationAttr { None, Sat }
-
-/// Scalar arithmetic with explicit PTX modifiers.
-#[pliron_op(
-    name = "nvvm.scalar_arithmetic",
-    format,
-    interfaces = [NResultsInterface<1>],
-    attributes = (
-        nvvm_scalar_arithmetic_format: ScalarArithmeticFormatAttr,
-        nvvm_scalar_arithmetic_operation: ScalarArithmeticOperationAttr,
-        nvvm_scalar_arithmetic_rounding: ScalarArithmeticRoundingAttr,
-        nvvm_scalar_arithmetic_subnormal: ScalarArithmeticSubnormalAttr,
-        nvvm_scalar_arithmetic_saturation: ScalarArithmeticSaturationAttr
-    )
-)]
-pub struct ScalarArithmeticOp;
-
-impl ScalarArithmeticOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-
-    pub fn build(
-        ctx: &mut Context,
-        operands: Vec<Value>,
-        format: ScalarArithmeticFormatAttr,
-        operation: ScalarArithmeticOperationAttr,
-        rounding: ScalarArithmeticRoundingAttr,
-        subnormal: ScalarArithmeticSubnormalAttr,
-        saturation: ScalarArithmeticSaturationAttr,
-    ) -> Ptr<Operation> {
-        let result_ty = match &format {
-            ScalarArithmeticFormatAttr::F32 => FP32Type::get(ctx).into(),
-            ScalarArithmeticFormatAttr::F64 => FP64Type::get(ctx).into(),
-        };
-        let op = Operation::new(
-            ctx,
-            Self::get_concrete_op_info(),
-            vec![result_ty],
-            operands,
-            vec![],
-            0,
-        );
-        let this = Self { op };
-        this.set_attr_nvvm_scalar_arithmetic_format(ctx, format);
-        this.set_attr_nvvm_scalar_arithmetic_operation(ctx, operation);
-        this.set_attr_nvvm_scalar_arithmetic_rounding(ctx, rounding);
-        this.set_attr_nvvm_scalar_arithmetic_subnormal(ctx, subnormal);
-        this.set_attr_nvvm_scalar_arithmetic_saturation(ctx, saturation);
-        this.get_operation()
-    }
-}
-
-impl Verify for ScalarArithmeticOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let op = self.get_operation().deref(ctx);
-        let Some(format) = self.get_attr_nvvm_scalar_arithmetic_format(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_arithmetic requires a format");
-        };
-        let Some(operation) = self.get_attr_nvvm_scalar_arithmetic_operation(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_arithmetic requires an operation");
-        };
-        let Some(rounding) = self.get_attr_nvvm_scalar_arithmetic_rounding(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_arithmetic requires rounding");
-        };
-        let Some(subnormal) = self.get_attr_nvvm_scalar_arithmetic_subnormal(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_arithmetic requires a subnormal mode");
-        };
-        let Some(saturation) = self.get_attr_nvvm_scalar_arithmetic_saturation(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_arithmetic requires saturation");
-        };
-        let admitted = matches!(
-            (&*format, &*operation, &*rounding, &*subnormal, &*saturation),
-"##,
-    );
-    for (index, record) in scalar_arithmetics(catalog).enumerate() {
-        if index != 0 {
-            output.push_str(" |\n");
-        }
-        writeln!(
-            output,
-            "            ({}, {}, {}, {}, {})",
-            scalar_arithmetic_format_attr(record),
-            scalar_arithmetic_operation_attr(record),
-            scalar_arithmetic_rounding_attr(record),
-            scalar_arithmetic_subnormal_attr(record),
-            scalar_arithmetic_saturation_attr(record),
-        )
-        .unwrap();
-    }
-    output.push_str(
-        r##"        );
-        if !admitted {
-            return verify_err!(op.loc(), "nvvm.scalar_arithmetic variant is not admitted");
-        }
-        let expected_operands = match &*operation {
-            ScalarArithmeticOperationAttr::Mul
-            | ScalarArithmeticOperationAttr::Div
-            | ScalarArithmeticOperationAttr::Add => 2,
-            ScalarArithmeticOperationAttr::Fma => 3,
-        };
-        if op.get_num_operands() != expected_operands || op.get_num_results() != 1 {
-            return verify_err!(
-                op.loc(),
-                "nvvm.scalar_arithmetic requires {} operands and one result",
-                expected_operands,
-            );
-        }
-        let type_matches = |ty: pliron::r#type::TypeHandle| match &*format {
-            ScalarArithmeticFormatAttr::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
-            ScalarArithmeticFormatAttr::F64 => ty.deref(ctx).downcast_ref::<FP64Type>().is_some(),
-        };
-        if !(0..expected_operands).all(|index| type_matches(op.get_operand(index).get_type(ctx)))
-            || !type_matches(op.get_result(0).get_type(ctx))
-        {
-            return verify_err!(op.loc(), "nvvm.scalar_arithmetic types do not match its format");
-        }
-        Ok(())
-    }
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    ScalarArithmeticFormatAttr::register(ctx);
-    ScalarArithmeticOperationAttr::register(ctx);
-    ScalarArithmeticRoundingAttr::register(ctx);
-    ScalarArithmeticSubnormalAttr::register(ctx);
-    ScalarArithmeticSaturationAttr::register(ctx);
-    ScalarArithmeticOp::register(ctx);
-}
-"##,
-    );
-    output
-}
-
-fn render_dialect_scalar_math(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r##"//! One structural operation for generated scalar math.
-
-use pliron::{
-    attribute::Attribute,
-    builtin::{op_interfaces::{NOpdsInterface, NResultsInterface}, types::{FP32Type, FP64Type, IntegerType, Signedness}},
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[pliron_attr(name = "nvvm.scalar_math_format", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarMathFormatAttr { F16, F32, F64 }
-
-#[pliron_attr(name = "nvvm.scalar_math_operation", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarMathOperationAttr { Sin, Cos, Ex2, Lg2, Rcp, Rsqrt, Sqrt, Tanh }
-
-#[pliron_attr(name = "nvvm.scalar_math_precision", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarMathPrecisionAttr { Approx, Rn, Rz, Rm, Rp }
-
-#[pliron_attr(name = "nvvm.scalar_math_subnormal", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ScalarMathSubnormalAttr { Preserve, Ftz }
-
-/// Scalar math with exact PTX modifiers.
-#[pliron_op(
-    name = "nvvm.scalar_math",
-    format,
-    interfaces = [NOpdsInterface<1>, NResultsInterface<1>],
-    attributes = (
-        nvvm_scalar_math_format: ScalarMathFormatAttr,
-        nvvm_scalar_math_operation: ScalarMathOperationAttr,
-        nvvm_scalar_math_precision: ScalarMathPrecisionAttr,
-        nvvm_scalar_math_subnormal: ScalarMathSubnormalAttr
-    )
-)]
-pub struct ScalarMathOp;
-
-impl ScalarMathOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-
-    pub fn build(
-        ctx: &mut Context,
-        operand: Value,
-        format: ScalarMathFormatAttr,
-        operation: ScalarMathOperationAttr,
-        precision: ScalarMathPrecisionAttr,
-        subnormal: ScalarMathSubnormalAttr,
-    ) -> Ptr<Operation> {
-        let result_ty = match &format {
-            ScalarMathFormatAttr::F16 => IntegerType::get(ctx, 16, Signedness::Unsigned).into(),
-            ScalarMathFormatAttr::F32 => FP32Type::get(ctx).into(),
-            ScalarMathFormatAttr::F64 => FP64Type::get(ctx).into(),
-        };
-        let op = Operation::new(
-            ctx,
-            Self::get_concrete_op_info(),
-            vec![result_ty],
-            vec![operand],
-            vec![],
-            0,
-        );
-        let this = Self { op };
-        this.set_attr_nvvm_scalar_math_format(ctx, format);
-        this.set_attr_nvvm_scalar_math_operation(ctx, operation);
-        this.set_attr_nvvm_scalar_math_precision(ctx, precision);
-        this.set_attr_nvvm_scalar_math_subnormal(ctx, subnormal);
-        this.get_operation()
-    }
-}
-
-impl Verify for ScalarMathOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let op = self.get_operation().deref(ctx);
-        let Some(format) = self.get_attr_nvvm_scalar_math_format(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_math requires a format");
-        };
-        let Some(operation) = self.get_attr_nvvm_scalar_math_operation(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_math requires an operation");
-        };
-        let Some(precision) = self.get_attr_nvvm_scalar_math_precision(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_math requires a precision");
-        };
-        let Some(subnormal) = self.get_attr_nvvm_scalar_math_subnormal(ctx) else {
-            return verify_err!(op.loc(), "nvvm.scalar_math requires a subnormal mode");
-        };
-        let admitted = matches!(
-            (&*format, &*operation, &*precision, &*subnormal),
-"##,
-    );
-    for (index, record) in scalar_maths(catalog).enumerate() {
-        if index != 0 {
-            output.push_str(" |\n");
-        }
-        writeln!(
-            output,
-            "            ({}, {}, {}, {})",
-            scalar_math_format_attr(record),
-            scalar_math_operation_attr(record),
-            scalar_math_precision_attr(record),
-            scalar_math_subnormal_attr(record),
-        )
-        .unwrap();
-    }
-    output.push_str(
-        r##"        );
-        if !admitted {
-            return verify_err!(op.loc(), "nvvm.scalar_math variant is not admitted");
-        }
-        if op.get_num_operands() != 1 || op.get_num_results() != 1 {
-            return verify_err!(
-                op.loc(),
-                "nvvm.scalar_math requires one operand and one result",
-            );
-        }
-        let type_matches = |ty: pliron::r#type::TypeHandle| match &*format {
-            ScalarMathFormatAttr::F16 => ty.deref(ctx).downcast_ref::<IntegerType>().is_some_and(|integer| integer.width() == 16),
-            ScalarMathFormatAttr::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
-            ScalarMathFormatAttr::F64 => ty.deref(ctx).downcast_ref::<FP64Type>().is_some(),
-        };
-        if !type_matches(op.get_operand(0).get_type(ctx))
-            || !type_matches(op.get_result(0).get_type(ctx))
-        {
-            return verify_err!(op.loc(), "nvvm.scalar_math types do not match its format");
-        }
-        Ok(())
-    }
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    ScalarMathFormatAttr::register(ctx);
-    ScalarMathOperationAttr::register(ctx);
-    ScalarMathPrecisionAttr::register(ctx);
-    ScalarMathSubnormalAttr::register(ctx);
-    ScalarMathOp::register(ctx);
-}
-"##,
-    );
-    output
-}
-
-fn render_dialect_extended_minmax(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r##"//! One structural operation for extended floating-point min/max.
-
-use pliron::{
-    attribute::Attribute,
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        types::{FP32Type, IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[pliron_attr(name = "nvvm.extended_minmax_format", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ExtendedMinMaxFormatAttr { F32, F16, Bf16, F16x2, Bf16x2 }
-
-#[pliron_attr(name = "nvvm.extended_minmax_operation", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ExtendedMinMaxOperationAttr { Min, Max }
-
-#[pliron_attr(name = "nvvm.extended_minmax_subnormal", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ExtendedMinMaxSubnormalAttr { Preserve, Ftz }
-
-#[pliron_attr(name = "nvvm.extended_minmax_nan", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ExtendedMinMaxNanAttr { Number, Nan }
-
-#[pliron_attr(name = "nvvm.extended_minmax_xorsign_abs", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ExtendedMinMaxXorSignAbsAttr { Disabled, Enabled }
-
-/// Extended min/max with exact PTX modifiers.
-#[pliron_op(
-    name = "nvvm.extended_minmax",
-    format,
-    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
-    attributes = (
-        nvvm_extended_minmax_format: ExtendedMinMaxFormatAttr,
-        nvvm_extended_minmax_operation: ExtendedMinMaxOperationAttr,
-        nvvm_extended_minmax_subnormal: ExtendedMinMaxSubnormalAttr,
-        nvvm_extended_minmax_nan: ExtendedMinMaxNanAttr,
-        nvvm_extended_minmax_xorsign_abs: ExtendedMinMaxXorSignAbsAttr
-    )
-)]
-pub struct ExtendedMinMaxOp;
-
-impl ExtendedMinMaxOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-
-    #[allow(clippy::too_many_arguments)]
-    pub fn build(
-        ctx: &mut Context,
-        a: Value,
-        b: Value,
-        format: ExtendedMinMaxFormatAttr,
-        operation: ExtendedMinMaxOperationAttr,
-        subnormal: ExtendedMinMaxSubnormalAttr,
-        nan: ExtendedMinMaxNanAttr,
-        xorsign_abs: ExtendedMinMaxXorSignAbsAttr,
-    ) -> Ptr<Operation> {
-        let result_ty = match &format {
-            ExtendedMinMaxFormatAttr::F32 => FP32Type::get(ctx).into(),
-            ExtendedMinMaxFormatAttr::F16 | ExtendedMinMaxFormatAttr::Bf16 => {
-                IntegerType::get(ctx, 16, Signedness::Unsigned).into()
-            }
-            ExtendedMinMaxFormatAttr::F16x2 | ExtendedMinMaxFormatAttr::Bf16x2 => {
-                IntegerType::get(ctx, 32, Signedness::Unsigned).into()
-            }
-        };
-        let op = Operation::new(
-            ctx,
-            Self::get_concrete_op_info(),
-            vec![result_ty],
-            vec![a, b],
-            vec![],
-            0,
-        );
-        let this = Self { op };
-        this.set_attr_nvvm_extended_minmax_format(ctx, format);
-        this.set_attr_nvvm_extended_minmax_operation(ctx, operation);
-        this.set_attr_nvvm_extended_minmax_subnormal(ctx, subnormal);
-        this.set_attr_nvvm_extended_minmax_nan(ctx, nan);
-        this.set_attr_nvvm_extended_minmax_xorsign_abs(ctx, xorsign_abs);
-        this.get_operation()
-    }
-}
-
-impl Verify for ExtendedMinMaxOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let op = self.get_operation().deref(ctx);
-        let Some(format) = self.get_attr_nvvm_extended_minmax_format(ctx) else {
-            return verify_err!(op.loc(), "nvvm.extended_minmax requires a format");
-        };
-        let Some(operation) = self.get_attr_nvvm_extended_minmax_operation(ctx) else {
-            return verify_err!(op.loc(), "nvvm.extended_minmax requires an operation");
-        };
-        let Some(subnormal) = self.get_attr_nvvm_extended_minmax_subnormal(ctx) else {
-            return verify_err!(op.loc(), "nvvm.extended_minmax requires a subnormal mode");
-        };
-        let Some(nan) = self.get_attr_nvvm_extended_minmax_nan(ctx) else {
-            return verify_err!(op.loc(), "nvvm.extended_minmax requires a NaN mode");
-        };
-        let Some(xorsign_abs) = self.get_attr_nvvm_extended_minmax_xorsign_abs(ctx) else {
-            return verify_err!(op.loc(), "nvvm.extended_minmax requires an xorsign.abs mode");
-        };
-        let admitted = matches!(
-            (&*format, &*operation, &*subnormal, &*nan, &*xorsign_abs),
-"##,
-    );
-    for (index, record) in extended_minmax(catalog).enumerate() {
-        if index != 0 {
-            output.push_str(" |\n");
-        }
-        writeln!(
-            output,
-            "            ({}, {}, {}, {}, {})",
-            extended_minmax_format_attr(record),
-            extended_minmax_operation_attr(record),
-            extended_minmax_subnormal_attr(record),
-            extended_minmax_nan_attr(record),
-            extended_minmax_xorsign_abs_attr(record),
-        )
-        .unwrap();
-    }
-    output.push_str(
-        r##"        );
-        if !admitted {
-            return verify_err!(op.loc(), "nvvm.extended_minmax variant is not admitted");
-        }
-        let type_matches = |ty: pliron::r#type::TypeHandle| match &*format {
-            ExtendedMinMaxFormatAttr::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
-            ExtendedMinMaxFormatAttr::F16 | ExtendedMinMaxFormatAttr::Bf16 => ty
-                .deref(ctx)
-                .downcast_ref::<IntegerType>()
-                .is_some_and(|integer| integer.width() == 16),
-            ExtendedMinMaxFormatAttr::F16x2 | ExtendedMinMaxFormatAttr::Bf16x2 => ty
-                .deref(ctx)
-                .downcast_ref::<IntegerType>()
-                .is_some_and(|integer| integer.width() == 32),
-        };
-        if !type_matches(op.get_operand(0).get_type(ctx))
-            || !type_matches(op.get_operand(1).get_type(ctx))
-            || !type_matches(op.get_result(0).get_type(ctx))
-        {
-            return verify_err!(op.loc(), "nvvm.extended_minmax types do not match its format");
-        }
-        Ok(())
-    }
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    ExtendedMinMaxFormatAttr::register(ctx);
-    ExtendedMinMaxOperationAttr::register(ctx);
-    ExtendedMinMaxSubnormalAttr::register(ctx);
-    ExtendedMinMaxNanAttr::register(ctx);
-    ExtendedMinMaxXorSignAbsAttr::register(ctx);
-    ExtendedMinMaxOp::register(ctx);
-}
-"##,
-    );
-    output
-}
-
-fn render_dialect_prmt(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r##"//! One structural operation for the closed generated `prmt` family.
-
-use pliron::{
-    attribute::Attribute,
-    builtin::{
-        op_interfaces::NResultsInterface,
-        types::{IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[pliron_attr(name = "nvvm.prmt_mode", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum PrmtModeAttr {
-    Generic,
-    F4e,
-    B4e,
-    Rc8,
-    Ecl,
-    Ecr,
-    Rc16,
-}
-
-/// Byte permutation whose exact mode is carried by an attribute.
-#[pliron_op(
-    name = "nvvm.prmt",
-    format,
-    interfaces = [NResultsInterface<1>],
-    attributes = (nvvm_prmt_mode: PrmtModeAttr)
-)]
-pub struct PrmtOp;
-
-impl PrmtOp {
-    pub fn new(op: Ptr<Operation>) -> Self {
-        Self { op }
-    }
-
-    pub fn build(ctx: &mut Context, operands: Vec<Value>, mode: PrmtModeAttr) -> Ptr<Operation> {
-        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
-        let op = Operation::new(
-            ctx,
-            Self::get_concrete_op_info(),
-            vec![result_ty.into()],
-            operands,
-            vec![],
-            0,
-        );
-        let this = Self { op };
-        this.set_attr_nvvm_prmt_mode(ctx, mode);
-        this.get_operation()
-    }
-}
-
-impl Verify for PrmtOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let op = self.get_operation().deref(ctx);
-        let Some(mode) = self.get_attr_nvvm_prmt_mode(ctx) else {
-            return verify_err!(op.loc(), "nvvm.prmt requires a mode attribute");
-        };
-        let expected_operands = match &*mode {
-            PrmtModeAttr::Generic | PrmtModeAttr::F4e | PrmtModeAttr::B4e => 3,
-            PrmtModeAttr::Rc8 | PrmtModeAttr::Ecl | PrmtModeAttr::Ecr | PrmtModeAttr::Rc16 => 2,
-        };
-        if op.get_num_operands() != expected_operands || op.get_num_results() != 1 {
-            return verify_err!(
-                op.loc(),
-                "nvvm.prmt {:?} requires {} operands and one result",
-                mode,
-                expected_operands
-            );
-        }
-        for index in 0..expected_operands {
-            let ty = op.get_operand(index).get_type(ctx);
-            if ty
-                .deref(ctx)
-                .downcast_ref::<IntegerType>()
-                .is_none_or(|integer| integer.width() != 32)
-            {
-                return verify_err!(op.loc(), "nvvm.prmt operand {} must be a 32-bit integer", index);
-            }
-        }
-        let result_ty = op.get_result(0).get_type(ctx);
-        if result_ty
-            .deref(ctx)
-            .downcast_ref::<IntegerType>()
-            .is_none_or(|integer| integer.width() != 32)
-        {
-            return verify_err!(op.loc(), "nvvm.prmt result must be a 32-bit integer");
-        }
-        Ok(())
-    }
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    PrmtModeAttr::register(ctx);
-    PrmtOp::register(ctx);
-}
-"##,
-    );
-    output
-}
-
-fn render_dialect_cluster_barrier(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    if cluster_barriers(catalog).next().is_none() {
-        return output;
-    }
-    output.push_str(
-        r##"//! Generated operations for the closed cluster-barrier family.
-
-use pliron::{
-    attribute::Attribute,
-    builtin::op_interfaces::{NOpdsInterface, NResultsInterface},
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[pliron_attr(name = "nvvm.cluster_barrier_mode", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum ClusterBarrierModeAttr {
-    Arrive,
-    ArriveAligned,
-    ArriveRelaxed,
-    ArriveRelaxedAligned,
-    Wait,
-    WaitAligned,
-}
-
-/// Cluster synchronization whose exact spelling is carried by an attribute.
-#[pliron_op(
-    name = "nvvm.cluster_barrier",
-    format,
-    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],
-    attributes = (nvvm_cluster_barrier_mode: ClusterBarrierModeAttr)
-)]
-pub struct ClusterBarrierOp;
-
-impl ClusterBarrierOp {
-    pub fn new(op: Ptr<Operation>) -> Self {
-        Self { op }
-    }
-
-    pub fn build(ctx: &mut Context, mode: ClusterBarrierModeAttr) -> Ptr<Operation> {
-        let op = Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0);
-        let this = Self { op };
-        this.set_attr_nvvm_cluster_barrier_mode(ctx, mode);
-        this.get_operation()
-    }
-}
-
-impl Verify for ClusterBarrierOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let op = self.get_operation().deref(ctx);
-        if self.get_attr_nvvm_cluster_barrier_mode(ctx).is_none() {
-            return verify_err!(op.loc(), "nvvm.cluster_barrier requires a mode attribute");
-        }
-        if op.get_num_operands() != 0 || op.get_num_results() != 0 {
-            return verify_err!(op.loc(), "nvvm.cluster_barrier takes no operands or results");
-        }
-        Ok(())
-    }
-}
-
-/// Compatibility operation for a complete aligned cluster synchronization.
-#[pliron_op(
-    name = "nvvm.cluster_sync",
-    format,
-    verifier = "succ",
-    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],
-)]
-pub struct ClusterSyncOp;
-
-impl ClusterSyncOp {
-    pub fn new(op: Ptr<Operation>) -> Self {
-        Self { op }
-    }
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    ClusterBarrierModeAttr::register(ctx);
-    ClusterBarrierOp::register(ctx);
-    ClusterSyncOp::register(ctx);
-}
-"##,
-    );
-    output
-}
-
-fn render_dialect_cluster_memory(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(cluster_memory(catalog).count(), 2);
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r#"//! Structural operations for cluster address mapping and remote shared reads.
-
-use dialect_mir::types::{MirPointerKind, MirPtrType, address_space};
-use pliron::{
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        types::{IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::Typed,
-    value::Value,
-    verify_err,
-};
-use pliron_derive::pliron_op;
-
-fn verify_pointer_rank(
-    ctx: &Context,
-    operation: Ptr<Operation>,
-    name: &str,
-) -> Result<(), Error> {
-    let op = operation.deref(ctx);
-    if op.get_num_operands() != 2 || op.get_num_results() != 1 {
-        return verify_err!(op.loc(), "{name} requires two operands and one result");
-    }
-    if op
-        .get_operand(0)
-        .get_type(ctx)
-        .deref(ctx)
-        .downcast_ref::<MirPtrType>()
-        .is_none()
-    {
-        return verify_err!(op.loc(), "{name} source must be a MIR pointer");
-    }
-    let rank_ty = op.get_operand(1).get_type(ctx);
-    let rank_ty = rank_ty.deref(ctx);
-    if !rank_ty
-        .downcast_ref::<IntegerType>()
-        .is_some_and(|ty| ty.width() == 32 && ty.signedness() == Signedness::Unsigned)
-    {
-        return verify_err!(op.loc(), "{name} rank must be u32");
-    }
-    Ok(())
-}
-
-#[pliron_op(
-    name = "nvvm.mapa_shared_cluster",
-    format,
-    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
-)]
-pub struct MapaSharedClusterOp;
-
-impl MapaSharedClusterOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-
-    // Kind-preserving addrspace retype: copies the source pointer's kind
-    // verbatim; concrete kinds are minted only in mir-importer's facts.rs.
-    #[allow(clippy::disallowed_methods)]
-    pub fn build(ctx: &mut Context, source: Value, rank: Value) -> Ptr<Operation> {
-        let source_ty = source.get_type(ctx);
-        let (pointee, is_mutable, pointer_kind) = {
-            let source_ty_obj = source_ty.deref(ctx);
-            let source_ptr = source_ty_obj
-                .downcast_ref::<MirPtrType>()
-                .expect("nvvm.mapa_shared_cluster source must be a MIR pointer");
-            (
-                source_ptr.pointee,
-                source_ptr.is_mutable(),
-                source_ptr.pointer_kind(),
-            )
-        };
-        let result_ty = MirPtrType::get_with_kind(
-            ctx,
-            pointee,
-            is_mutable,
-            address_space::CLUSTER_SHARED,
-            pointer_kind,
-        );
-        Operation::new(
-            ctx,
-            Self::get_concrete_op_info(),
-            vec![result_ty.into()],
-            vec![source, rank],
-            vec![],
-            0,
-        )
-    }
-}
-
-impl Verify for MapaSharedClusterOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let operation = self.get_operation();
-        verify_pointer_rank(ctx, operation, "nvvm.mapa_shared_cluster")?;
-        let op = operation.deref(ctx);
-        let source_ty = op.get_operand(0).get_type(ctx);
-        let result_ty = op.get_result(0).get_type(ctx);
-        let source_ty_obj = source_ty.deref(ctx);
-        let result_ty_obj = result_ty.deref(ctx);
-        let source_ptr = source_ty_obj.downcast_ref::<MirPtrType>().unwrap();
-        let Some(result_ptr) = result_ty_obj.downcast_ref::<MirPtrType>() else {
-            return verify_err!(
-                op.loc(),
-                "nvvm.mapa_shared_cluster result must be a MIR pointer"
-            );
-        };
-        if !matches!(
-            source_ptr.pointer_kind(),
-            MirPointerKind::RawConst | MirPointerKind::RawMut
-        )
-            || result_ptr.pointee != source_ptr.pointee
-            || result_ptr.is_mutable() != source_ptr.is_mutable()
-            || !result_ptr.is_cluster_shared()
-            || result_ptr.pointer_kind() != source_ptr.pointer_kind()
-        {
-            return verify_err!(
-                op.loc(),
-                "nvvm.mapa_shared_cluster requires a raw source pointer and must preserve its pointee, mutability, and raw kind while returning addrspace(7)"
-            );
-        }
-        Ok(())
-    }
-}
-
-#[pliron_op(
-    name = "nvvm.dsmem_read_u32",
-    format,
-    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
-)]
-pub struct DsmemReadU32Op;
-
-impl DsmemReadU32Op {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-
-    pub fn build(ctx: &mut Context, source: Value, rank: Value) -> Ptr<Operation> {
-        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
-        Operation::new(
-            ctx,
-            Self::get_concrete_op_info(),
-            vec![result_ty.to_handle()],
-            vec![source, rank],
-            vec![],
-            0,
-        )
-    }
-}
-
-impl Verify for DsmemReadU32Op {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let operation = self.get_operation();
-        verify_pointer_rank(ctx, operation, "nvvm.dsmem_read_u32")?;
-        let op = operation.deref(ctx);
-        let result_ty = op.get_result(0).get_type(ctx);
-        let result_ty = result_ty.deref(ctx);
-        if !result_ty
-            .downcast_ref::<IntegerType>()
-            .is_some_and(|ty| ty.width() == 32 && ty.signedness() == Signedness::Unsigned)
-        {
-            return verify_err!(op.loc(), "nvvm.dsmem_read_u32 result must be u32");
-        }
-        Ok(())
-    }
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    MapaSharedClusterOp::register(ctx);
-    DsmemReadU32Op::register(ctx);
-}
-"#,
-    );
-    output
-}
-
-fn render_dialect_wgmma_control(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(wgmma_controls(catalog).count(), 3);
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r##"//! Structural operations for generated WGMMA controls.
-
-use pliron::{
-    builtin::{op_interfaces::{NOpdsInterface, NResultsInterface}, types::IntegerType},
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::{TypeHandle, Typed},
-    value::Value,
-    verify_err,
-};
-use pliron_derive::pliron_op;
-
-#[pliron_op(
-    name = "nvvm.wgmma_fence_sync_aligned",
-    format,
-    verifier = "succ",
-    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],
-)]
-pub struct WgmmaFenceSyncAlignedOp;
-
-impl WgmmaFenceSyncAlignedOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-
-    pub fn build(ctx: &mut Context) -> Ptr<Operation> {
-        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)
-    }
-}
-
-#[pliron_op(
-    name = "nvvm.wgmma_commit_group_sync_aligned",
-    format,
-    verifier = "succ",
-    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],
-)]
-pub struct WgmmaCommitGroupSyncAlignedOp;
-
-impl WgmmaCommitGroupSyncAlignedOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-
-    pub fn build(ctx: &mut Context) -> Ptr<Operation> {
-        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)
-    }
-}
-
-#[pliron_op(
-    name = "nvvm.wgmma_wait_group_sync_aligned",
-    format,
-    interfaces = [NOpdsInterface<1>, NResultsInterface<0>],
-)]
-pub struct WgmmaWaitGroupSyncAlignedOp;
-
-impl WgmmaWaitGroupSyncAlignedOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-
-    pub fn build(ctx: &mut Context, max_pending: Value) -> Ptr<Operation> {
-        Operation::new(
-            ctx,
-            Self::get_concrete_op_info(),
-            vec![],
-            vec![max_pending],
-            vec![],
-            0,
-        )
-    }
-}
-
-impl Verify for WgmmaWaitGroupSyncAlignedOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        let op = self.get_operation().deref(ctx);
-        if op.get_num_operands() != 1 || op.get_num_results() != 0 {
-            return verify_err!(op.loc(), "nvvm.wgmma_wait_group_sync_aligned takes one operand and no results");
-        }
-        if !is_i64(ctx, op.get_operand(0).get_type(ctx)) {
-            return verify_err!(op.loc(), "nvvm.wgmma_wait_group_sync_aligned operand must be i64");
-        }
-        Ok(())
-    }
-}
-
-fn is_i64(ctx: &Context, ty: TypeHandle) -> bool {
-    ty.deref(ctx)
-        .downcast_ref::<IntegerType>()
-        .is_some_and(|integer| integer.width() == 64)
-}
-
-pub(super) fn register(ctx: &mut Context) {
-    WgmmaFenceSyncAlignedOp::register(ctx);
-    WgmmaCommitGroupSyncAlignedOp::register(ctx);
-    WgmmaWaitGroupSyncAlignedOp::register(ctx);
-}
-"##,
-    );
-    output
-}
-
-fn render_dialect_debug_control(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(debug_controls(catalog).count(), 3);
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Structural operations for generated PTX debug controls.\n\n\
-         use pliron::{\n\
-             builtin::{\n\
-                 attributes::IntegerAttr,\n\
-                 op_interfaces::{NOpdsInterface, NResultsInterface},\n\
-                 types::{IntegerType, Signedness},\n\
-             },\n\
-             common_traits::Verify,\n\
-             context::{Context, Ptr},\n\
-             identifier::Identifier,\n\
-             location::Located,\n\
-             op::Op,\n\
-             operation::Operation,\n\
-             result::Error,\n\
-             verify_err,\n\
-         };\n\
-         use pliron::utils::apint::APInt;\n\
-         use pliron_derive::pliron_op;\n\
-         use std::num::NonZeroUsize;\n\n\
-         #[pliron_op(\n\
-             name = \"nvvm.trap\",\n\
-             format,\n\
-             verifier = \"succ\",\n\
-             interfaces = [NOpdsInterface<0>, NResultsInterface<0>],\n\
-         )]\n\
-         pub struct TrapOp;\n\n\
-         impl TrapOp {\n\
-             pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\
-             pub fn build(ctx: &mut Context) -> Ptr<Operation> {\n\
-                 Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)\n\
-             }\n\
-         }\n\n\
-         #[pliron_op(\n\
-             name = \"nvvm.brkpt\",\n\
-             format,\n\
-             verifier = \"succ\",\n\
-             interfaces = [NOpdsInterface<0>, NResultsInterface<0>],\n\
-         )]\n\
-         pub struct BreakpointOp;\n\n\
-         impl BreakpointOp {\n\
-             pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\
-             pub fn build(ctx: &mut Context) -> Ptr<Operation> {\n\
-                 Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)\n\
-             }\n\
-         }\n\n\
-         #[pliron_op(\n\
-             name = \"nvvm.pmevent\",\n\
-             format,\n\
-             interfaces = [NOpdsInterface<0>, NResultsInterface<0>],\n\
-         )]\n\
-         pub struct PmEventOp;\n\n\
-         impl PmEventOp {\n\
-             pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n\
-             pub fn build(ctx: &mut Context, event_id: u32) -> Ptr<Operation> {\n\
-                 let op = Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0);\n\
-                 let ty = IntegerType::get(ctx, 32, Signedness::Unsigned);\n\
-                 let value = APInt::from_u64(event_id.into(), NonZeroUsize::new(32).unwrap());\n\
-                 op.deref_mut(ctx).attributes.set(\n\
-                     Identifier::try_from(\"event_id\").unwrap(),\n\
-                     IntegerAttr::new(ty, value),\n\
-                 );\n\
-                 op\n\
-             }\n\n\
-             pub fn new_with_event_id(ctx: &mut Context, event_id: u32) -> Ptr<Operation> {\n\
-                 Self::build(ctx, event_id)\n\
-             }\n\n\
-             pub fn event_id(&self, ctx: &Context) -> Option<u32> {\n\
-                 let key = Identifier::try_from(\"event_id\").unwrap();\n\
-                 let operation = self.get_operation().deref(ctx);\n\
-                 let attribute: &IntegerAttr = operation.attributes.get(&key)?;\n\
-                 let ty_handle = attribute.get_type();\n\
-                 let ty = ty_handle.deref(ctx);\n\
-                 if ty.width() != 32 || ty.signedness() != Signedness::Unsigned {\n\
-                     return None;\n\
-                 }\n\
-                 u32::try_from(attribute.value().to_u64()).ok().filter(|value| *value <= 15)\n\
-             }\n\
-\n\
-             pub fn get_event_id(&self, ctx: &Context) -> Option<u32> {\n\
-                 self.event_id(ctx)\n\
-             }\n\
-         }\n\n\
-         impl Verify for PmEventOp {\n\
-             fn verify(&self, ctx: &Context) -> Result<(), Error> {\n\
-                 let op = self.get_operation().deref(ctx);\n\
-                 if self.event_id(ctx).is_none() {\n\
-                     return verify_err!(op.loc(), \"nvvm.pmevent requires a u32 event ID in 0..=15\");\n\
-                 }\n\
-                 Ok(())\n\
-             }\n\
-         }\n\n\
-         pub(super) fn register(ctx: &mut Context) {\n\
-             TrapOp::register(ctx);\n\
-             BreakpointOp::register(ctx);\n\
-             PmEventOp::register(ctx);\n\
-         }\n",
-    );
-    output
-}
-
-fn render_dialect_clc(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(clc_intrinsics(catalog).count(), 6);
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Generated Cluster Launch Control operations.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::IntegerType,\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::{TypeHandle, Typed},\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\n",
-    );
-    for record in clc_intrinsics(catalog) {
-        let result_count = record.dialect.results.len();
-        let verifier = if result_count == 0 {
-            "    verifier = \"succ\",\n"
-        } else {
-            ""
-        };
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n{verifier}    interfaces = [NOpdsInterface<2>, NResultsInterface<{result_count}>],\n)]",
-            record.dialect.op_name,
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n}\n\n");
-        if result_count == 1 {
-            writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
-            writeln!(
-                output,
-                "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_query_shape(ctx, self.get_operation(), {:?})\n    }}\n}}\n",
-                record.dialect.op_name,
-            )
-            .unwrap();
-        }
-    }
-    output.push_str(
-        "fn verify_query_shape(\n    ctx: &Context,\n    operation: Ptr<Operation>,\n    name: &str,\n) -> Result<(), Error> {\n    let op = operation.deref(ctx);\n    let valid = op.get_num_operands() == 2\n        && op.get_num_results() == 1\n        && is_integer_width(ctx, op.get_operand(0).get_type(ctx), 64)\n        && is_integer_width(ctx, op.get_operand(1).get_type(ctx), 64)\n        && is_integer_width(ctx, op.get_result(0).get_type(ctx), 32);\n    if !valid {\n        return verify_err!(\n            op.loc(),\n            \"{} requires two i64 operands and one i32 result\",\n            name\n        );\n    }\n    Ok(())\n}\n\nfn is_integer_width(ctx: &Context, ty: TypeHandle, width: u32) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\npub(super) fn register(ctx: &mut Context) {\n",
-    );
-    for record in clc_intrinsics(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_execution_control(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(execution_controls(catalog).count(), 8);
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Generated counted-barrier, grid-dependency, and register-control operations.\n\nuse pliron::{\n    builtin::{attributes::IntegerAttr, op_interfaces::{NOpdsInterface, NResultsInterface}, types::{IntegerType, Signedness}},\n    common_traits::Verify,\n    context::{Context, Ptr},\n    identifier::Identifier,\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    verify_err,\n};\nuse pliron::utils::apint::APInt;\nuse pliron_derive::pliron_op;\nuse std::num::NonZeroUsize;\n\n",
-    );
-    for record in execution_controls(catalog).filter(|record| record.family != "register_control") {
-        let operand_count = record.dialect.operands.len();
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    verifier = \"succ\",\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<0>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n}\n\n");
-    }
-    for record in execution_control_family(catalog, "register_control") {
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str(
-            "    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n    pub fn build(ctx: &mut Context, register_count: u32) -> Ptr<Operation> {\n        let op = Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0);\n        let ty = IntegerType::get(ctx, 32, Signedness::Unsigned);\n        let value = APInt::from_u64(register_count.into(), NonZeroUsize::new(32).unwrap());\n        op.deref_mut(ctx).attributes.set(\n            Identifier::try_from(\"register_count\").unwrap(),\n            IntegerAttr::new(ty, value),\n        );\n        op\n    }\n\n    pub fn register_count(&self, ctx: &Context) -> Option<u32> {\n        let key = Identifier::try_from(\"register_count\").unwrap();\n        let operation = self.get_operation().deref(ctx);\n        let attribute: &IntegerAttr = operation.attributes.get(&key)?;\n        let ty_handle = attribute.get_type();\n        let ty = ty_handle.deref(ctx);\n        if ty.width() != 32 || ty.signedness() != Signedness::Unsigned {\n            return None;\n        }\n        u32::try_from(attribute.value().to_u64()).ok().filter(|value| (24..=256).contains(value) && value % 8 == 0)\n    }\n}\n\n",
-        );
-        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
-        output.push_str(
-            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {\n        let op = self.get_operation().deref(ctx);\n        if self.register_count(ctx).is_none() {\n            return verify_err!(op.loc(), \"setmaxnreg requires an immediate register count in 24..=256 divisible by 8\");\n        }\n        Ok(())\n    }\n}\n\n",
-        );
-    }
-    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
-    for record in execution_controls(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_dialect_tma(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Generated Tensor Memory Accelerator operations.\n\nuse pliron::{\n    builtin::op_interfaces::{NOpdsInterface, NResultsInterface},\n    context::{Context, Ptr},\n    op::Op,\n    operation::Operation,\n};\nuse pliron_derive::pliron_op;\n\n",
-    );
-    for record in tma_intrinsics(catalog) {
-        let operand_count = record.dialect.operands.len();
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    verifier = \"succ\",\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<0>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n}\n\n");
-    }
-    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
-    for record in tma_intrinsics(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn tcgen05_carrier_name(ty: &str) -> &'static str {
-    match ty {
-        "ptr" => "Ptr",
-        "i1" => "I1",
-        "i16" => "I16",
-        "i32" => "I32",
-        "i64" => "I64",
-        "f32" => "F32",
-        _ => panic!("unsupported tcgen05 dialect carrier {ty}"),
-    }
-}
-
-fn render_tcgen05_carrier_runs(types: &[String]) -> String {
-    let mut runs = Vec::<(&str, usize)>::new();
-    for ty in types {
-        let carrier = tcgen05_carrier_name(ty);
-        if let Some((previous, count)) = runs.last_mut()
-            && *previous == carrier
-        {
-            *count += 1;
-        } else {
-            runs.push((carrier, 1));
-        }
-    }
-
-    let mut output = String::from("&[");
-    for (index, (carrier, count)) in runs.into_iter().enumerate() {
-        if index != 0 {
-            output.push_str(", ");
-        }
-        write!(output, "(Tcgen05Carrier::{carrier}, {count})").unwrap();
-    }
-    output.push(']');
-    output
-}
-
-fn render_dialect_tcgen05(catalog: &CatalogFile, hash: &str) -> String {
-    assert_eq!(tcgen05_intrinsics(catalog).count(), 233);
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        r#"//! Generated Tensor Core Generation 5 operations.
-
-use dialect_mir::{ops::MirConstantOp, types::MirPtrType};
-use pliron::{
-    attribute::Attribute,
-    builtin::{
-        op_interfaces::{NOpdsInterface, NResultsInterface},
-        ops::ConstantOp,
-        types::{FP32Type, IntegerType},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    location::Located,
-    op::Op,
-    operation::Operation,
-    result::Error,
-    r#type::{TypeHandle, Typed},
-    verify_err,
-};
-use pliron_derive::{pliron_attr, pliron_op};
-
-#[derive(Clone, Copy)]
-enum Tcgen05Carrier {
-    Ptr,
-    I1,
-    I16,
-    I32,
-    I64,
-    F32,
-}
-
-impl Tcgen05Carrier {
-    fn matches(self, ctx: &Context, ty: TypeHandle) -> bool {
-        match self {
-            Self::Ptr => ty.deref(ctx).downcast_ref::<MirPtrType>().is_some(),
-            Self::I1 => is_integer_width(ctx, ty, 1),
-            Self::I16 => is_integer_width(ctx, ty, 16),
-            Self::I32 => is_integer_width(ctx, ty, 32),
-            Self::I64 => is_integer_width(ctx, ty, 64),
-            Self::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
-        }
-    }
-
-    fn name(self) -> &'static str {
-        match self {
-            Self::Ptr => "MIR pointer",
-            Self::I1 => "i1",
-            Self::I16 => "i16",
-            Self::I32 => "i32",
-            Self::I64 => "i64",
-            Self::F32 => "f32",
-        }
-    }
-}
-
-fn is_integer_width(ctx: &Context, ty: TypeHandle, width: u32) -> bool {
-    ty.deref(ctx)
-        .downcast_ref::<IntegerType>()
-        .is_some_and(|integer| integer.width() == width)
-}
-
-fn expected_carrier_count(runs: &[(Tcgen05Carrier, usize)]) -> usize {
-    runs.iter().map(|(_, count)| *count).sum()
-}
-
-fn verify_tcgen05_signature(
-    ctx: &Context,
-    operation: Ptr<Operation>,
-    name: &str,
-    operand_runs: &[(Tcgen05Carrier, usize)],
-    result_runs: &[(Tcgen05Carrier, usize)],
-    constant_operand: Option<usize>,
-) -> Result<(), Error> {
-    let op = operation.deref(ctx);
-    let expected_operands = expected_carrier_count(operand_runs);
-    let expected_results = expected_carrier_count(result_runs);
-    if op.get_num_operands() != expected_operands || op.get_num_results() != expected_results {
-        return verify_err!(
-            op.loc(),
-            "{name} requires {expected_operands} operands and {expected_results} results"
-        );
-    }
-
-    let mut index = 0;
-    for (carrier, count) in operand_runs {
-        for _ in 0..*count {
-            if !carrier.matches(ctx, op.get_operand(index).get_type(ctx)) {
-                return verify_err!(
-                    op.loc(),
-                    "{name} operand {index} must be {}",
-                    carrier.name()
-                );
-            }
-            index += 1;
-        }
-    }
-
-    index = 0;
-    for (carrier, count) in result_runs {
-        for _ in 0..*count {
-            if !carrier.matches(ctx, op.get_result(index).get_type(ctx)) {
-                return verify_err!(
-                    op.loc(),
-                    "{name} result {index} must be {}",
-                    carrier.name()
-                );
-            }
-            index += 1;
-        }
-    }
-
-    if let Some(index) = constant_operand {
-        let value = op.get_operand(index);
-        let is_constant = value.defining_op().is_some_and(|defining_op| {
-            Operation::get_op::<MirConstantOp>(defining_op, ctx).is_some()
-                || Operation::get_op::<ConstantOp>(defining_op, ctx).is_some()
-        });
-        if !is_constant {
-            return verify_err!(
-                op.loc(),
-                "{name} operand {index} must be a compile-time constant"
-            );
-        }
-    }
-
-    Ok(())
-}
-
-"#,
-    );
-    if tcgen05_mma_intrinsics(catalog).next().is_some() {
-        output.push_str(
-            r#"#[pliron_attr(name = "nvvm.tcgen05_mma_form", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum Tcgen05MmaFormAttr {
-    Shared, Tensor, TensorAshift, SpShared, SpTensor, SpTensorAshift,
-    WsShared, WsSharedZeroColMask, WsSpShared, WsSpSharedZeroColMask,
-    WsSpTensor, WsSpTensorZeroColMask, WsTensor, WsTensorZeroColMask,
-}
-
-#[pliron_attr(name = "nvvm.tcgen05_mma_kind", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum Tcgen05MmaKindAttr { F16, Tf32, F8f6f4, I8 }
-
-#[pliron_attr(name = "nvvm.tcgen05_mma_cta_group", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum Tcgen05MmaCtaGroupAttr { Cg1, Cg2 }
-
-#[pliron_attr(name = "nvvm.tcgen05_mma_collector_a", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum Tcgen05MmaCollectorAAttr { Discard, LastUse, Fill, Use }
-
-#[pliron_attr(name = "nvvm.tcgen05_mma_b_buffer", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum Tcgen05MmaBBufferAttr { B0, B1, B2, B3 }
-
-#[pliron_attr(name = "nvvm.tcgen05_mma_b_usage", format, verifier = "succ")]
-#[derive(PartialEq, Eq, Clone, Debug, Hash)]
-pub enum Tcgen05MmaBUsageAttr { Discard, LastUse, Fill, Use }
-
-#[pliron_op(
-    name = "nvvm.tcgen05_mma",
-    format,
-    attributes = (
-        nvvm_tcgen05_mma_form: Tcgen05MmaFormAttr,
-        nvvm_tcgen05_mma_kind: Tcgen05MmaKindAttr,
-        nvvm_tcgen05_mma_cta_group: Tcgen05MmaCtaGroupAttr,
-        nvvm_tcgen05_mma_collector_a: Tcgen05MmaCollectorAAttr,
-        nvvm_tcgen05_mma_b_buffer: Tcgen05MmaBBufferAttr,
-        nvvm_tcgen05_mma_b_usage: Tcgen05MmaBUsageAttr
-    )
-)]
-pub struct Tcgen05MmaOp;
-
-impl Tcgen05MmaOp {
-    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
-}
-
-impl Verify for Tcgen05MmaOp {
-    fn verify(&self, ctx: &Context) -> Result<(), Error> {
-        use Tcgen05Carrier::{I1, I32, I64};
-        let op = self.get_operation();
-        let form = self.get_attr_nvvm_tcgen05_mma_form(ctx);
-        let Some(form) = form.as_deref() else {
-            return verify_err!(op.deref(ctx).loc(), "nvvm.tcgen05_mma requires a form");
-        };
-        if self.get_attr_nvvm_tcgen05_mma_kind(ctx).is_none() {
-            return verify_err!(op.deref(ctx).loc(), "nvvm.tcgen05_mma requires a kind");
-        }
-        let (operands, base): (&[(Tcgen05Carrier, usize)], bool) = match form {
-            Tcgen05MmaFormAttr::Shared | Tcgen05MmaFormAttr::WsShared =>
-                (&[(I32, 1), (I64, 2), (I32, 1), (I1, 1)], matches!(form, Tcgen05MmaFormAttr::Shared)),
-            Tcgen05MmaFormAttr::Tensor | Tcgen05MmaFormAttr::TensorAshift | Tcgen05MmaFormAttr::WsTensor =>
-                (&[(I32, 2), (I64, 1), (I32, 1), (I1, 1)], !matches!(form, Tcgen05MmaFormAttr::WsTensor)),
-            Tcgen05MmaFormAttr::SpShared | Tcgen05MmaFormAttr::WsSpShared =>
-                (&[(I32, 1), (I64, 2), (I32, 1), (I1, 1), (I32, 1)], matches!(form, Tcgen05MmaFormAttr::SpShared)),
-            Tcgen05MmaFormAttr::SpTensor | Tcgen05MmaFormAttr::SpTensorAshift | Tcgen05MmaFormAttr::WsSpTensor =>
-                (&[(I32, 2), (I64, 1), (I32, 1), (I1, 1), (I32, 1)], !matches!(form, Tcgen05MmaFormAttr::WsSpTensor)),
-            Tcgen05MmaFormAttr::WsSharedZeroColMask =>
-                (&[(I32, 1), (I64, 2), (I32, 1), (I1, 1), (I64, 1)], false),
-            Tcgen05MmaFormAttr::WsSpSharedZeroColMask =>
-                (&[(I32, 1), (I64, 2), (I32, 1), (I1, 1), (I32, 1), (I64, 1)], false),
-            Tcgen05MmaFormAttr::WsSpTensorZeroColMask =>
-                (&[(I32, 2), (I64, 1), (I32, 1), (I1, 1), (I32, 1), (I64, 1)], false),
-            Tcgen05MmaFormAttr::WsTensorZeroColMask =>
-                (&[(I32, 2), (I64, 1), (I32, 1), (I1, 1), (I64, 1)], false),
-        };
-        verify_tcgen05_signature(ctx, op, "nvvm.tcgen05_mma", operands, &[], None)?;
-
-        let cta_group = self.get_attr_nvvm_tcgen05_mma_cta_group(ctx);
-        let collector_a = self.get_attr_nvvm_tcgen05_mma_collector_a(ctx);
-        let b_buffer = self.get_attr_nvvm_tcgen05_mma_b_buffer(ctx);
-        let b_usage = self.get_attr_nvvm_tcgen05_mma_b_usage(ctx);
-        if base {
-            if cta_group.is_none() || collector_a.is_none() || b_buffer.is_some() || b_usage.is_some() {
-                return verify_err!(op.deref(ctx).loc(), "base tcgen05 MMA requires CTA-group and collector-A selectors");
-            }
-            if matches!(form, Tcgen05MmaFormAttr::TensorAshift | Tcgen05MmaFormAttr::SpTensorAshift)
-                && !matches!(collector_a.as_deref(), Some(Tcgen05MmaCollectorAAttr::Discard | Tcgen05MmaCollectorAAttr::LastUse))
-            {
-                return verify_err!(op.deref(ctx).loc(), "ashift tcgen05 MMA only supports discard or last-use collector-A");
-            }
-        } else if cta_group.is_some() || collector_a.is_some() || b_buffer.is_none() || b_usage.is_none() {
-            return verify_err!(op.deref(ctx).loc(), "warp-specialized tcgen05 MMA requires B-buffer and B-usage selectors");
-        }
-        Ok(())
-    }
-}
-
-"#,
-        );
-    }
-    for record in tcgen05_non_mma_intrinsics(catalog) {
-        let operand_count = record.dialect.operands.len();
-        let result_count = record.dialect.results.len();
-        let operand_runs = render_tcgen05_carrier_runs(&record.dialect.operands);
-        let result_runs = render_tcgen05_carrier_runs(&record.dialect.results);
-        let constant_operand = record
-            .tcgen05
-            .as_ref()
-            .is_some_and(|tcgen05| {
-                matches!(
-                    tcgen05.adapter,
-                    Tcgen05Adapter::TmemHalfSplitOffsetInjectPack16ToU32Registers
-                        | Tcgen05Adapter::TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid
-                )
-            })
-            .then_some(1);
-        writeln!(output, "/// {}", record.summary).unwrap();
-        writeln!(
-            output,
-            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<{result_count}>],\n)]",
-            record.dialect.op_name
-        )
-        .unwrap();
-        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
-        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n}\n\n");
-        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
-        output.push_str("    fn verify(&self, ctx: &Context) -> Result<(), Error> {\n");
-        output.push_str("        verify_tcgen05_signature(\n");
-        output.push_str("            ctx,\n");
-        output.push_str("            self.get_operation(),\n");
-        writeln!(output, "            {:?},", record.dialect.op_name).unwrap();
-        writeln!(output, "            {operand_runs},").unwrap();
-        writeln!(output, "            {result_runs},").unwrap();
-        writeln!(output, "            {constant_operand:?},").unwrap();
-        output.push_str("        )\n");
-        output.push_str("    }\n");
-        output.push_str("}\n\n");
-    }
-    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
-    if tcgen05_mma_intrinsics(catalog).next().is_some() {
-        output.push_str(
-            "    Tcgen05MmaFormAttr::register(ctx);\n    Tcgen05MmaKindAttr::register(ctx);\n    Tcgen05MmaCtaGroupAttr::register(ctx);\n    Tcgen05MmaCollectorAAttr::register(ctx);\n    Tcgen05MmaBBufferAttr::register(ctx);\n    Tcgen05MmaBUsageAttr::register(ctx);\n    Tcgen05MmaOp::register(ctx);\n",
-        );
-    }
-    for record in tcgen05_non_mma_intrinsics(catalog) {
-        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
-    }
-    output.push_str("}\n");
-    output
-}
-
-fn render_importer_pure_value_dispatch(
-    output: &mut String,
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-) {
-    let mut path_refs = vec![record.rust.canonical_path.as_str()];
-    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-    output.push_str("        ");
-    render_inline_patterns(output, &path_refs);
-    output.push_str(" => {\n");
-    writeln!(
-        output,
-        "            require_arity(name, args.len(), {}, &loc)?;",
-        record.rust.arguments.len()
-    )
-    .unwrap();
-    for index in 0..record.rust.arguments.len() {
-        let previous = if index == 0 { "prev_op" } else { "last_op" };
-        writeln!(
-            output,
-            "            let (arg{index}, last_op) = rvalue::translate_operand(\n                ctx, body, &args[{index}], value_map, block_ptr, {previous}, loc.clone(),\n            )?;"
-        )
-        .unwrap();
-    }
-    let arguments = (0..record.rust.arguments.len())
-        .map(|index| format!("arg{index}"))
-        .collect::<Vec<_>>()
-        .join(", ");
-    writeln!(
-        output,
-        "            let intrinsic = {}::build(ctx, {arguments});",
-        record.dialect.op_type
-    )
-    .unwrap();
-    output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
-    writeln!(
-        output,
-        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
-        intrinsic_marker(catalog, record)
-    )
-    .unwrap();
-    output.push_str(
-        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n            let result = intrinsic.deref(ctx).get_result(0);\n",
-    );
-    writeln!(
-        output,
-        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
-        format!("{} call without target block", record.rust.name)
-    )
-    .unwrap();
-    output.push_str("        }\n");
-}
-
-fn render_importer_scalar_conversion_dispatch(
-    output: &mut String,
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-) {
-    let mut path_refs = vec![record.rust.canonical_path.as_str()];
-    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-    output.push_str("        ");
-    render_inline_patterns(output, &path_refs);
-    output.push_str(" => {\n");
-    output.push_str(
-        "            require_arity(name, args.len(), 1, &loc)?;\n\
-                     let (value, last_op) = rvalue::translate_operand(\n\
-                         ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
-                     )?;\n",
-    );
-    writeln!(
-        output,
-        "            let intrinsic = ScalarConversionOp::build(ctx, value, {}, {});",
-        scalar_conversion_rounding_attr(record),
-        scalar_conversion_saturation_attr(record),
-    )
-    .unwrap();
-    output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
-    writeln!(
-        output,
-        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
-        intrinsic_marker(catalog, record)
-    )
-    .unwrap();
-    output.push_str(
-        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n\
-                     let result = intrinsic.deref(ctx).get_result(0);\n",
-    );
-    writeln!(
-        output,
-        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
-        format!("{} call without target block", record.rust.name)
-    )
-    .unwrap();
-    output.push_str("        }\n");
-}
-
-fn render_importer_scalar_arithmetic_dispatch(
-    output: &mut String,
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-) {
-    let mut path_refs = vec![record.rust.canonical_path.as_str()];
-    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-    output.push_str("        ");
-    render_inline_patterns(output, &path_refs);
-    output.push_str(" => {\n");
-    let arity = scalar_arithmetic_arity(record);
-    writeln!(
-        output,
-        "            require_arity(name, args.len(), {arity}, &loc)?;"
-    )
-    .unwrap();
-    for index in 0..arity {
-        let previous = if index == 0 { "prev_op" } else { "last_op" };
-        writeln!(
-            output,
-            "            let (arg{index}, last_op) = rvalue::translate_operand(\n                ctx, body, &args[{index}], value_map, block_ptr, {previous}, loc.clone(),\n            )?;"
-        )
-        .unwrap();
-    }
-    let arguments = (0..arity)
-        .map(|index| format!("arg{index}"))
-        .collect::<Vec<_>>()
-        .join(", ");
-    writeln!(
-        output,
-        "            let intrinsic = ScalarArithmeticOp::build(ctx, vec![{arguments}], {}, {}, {}, {}, {});",
-        scalar_arithmetic_format_attr(record),
-        scalar_arithmetic_operation_attr(record),
-        scalar_arithmetic_rounding_attr(record),
-        scalar_arithmetic_subnormal_attr(record),
-        scalar_arithmetic_saturation_attr(record),
-    )
-    .unwrap();
-    output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
-    writeln!(
-        output,
-        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
-        intrinsic_marker(catalog, record)
-    )
-    .unwrap();
-    output.push_str(
-        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n\
-                     let result = intrinsic.deref(ctx).get_result(0);\n",
-    );
-    writeln!(
-        output,
-        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
-        format!("{} call without target block", record.rust.name)
-    )
-    .unwrap();
-    output.push_str("        }\n");
-}
-
-fn render_importer_scalar_math_dispatch(
-    output: &mut String,
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-) {
-    let mut path_refs = vec![record.rust.canonical_path.as_str()];
-    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-    output.push_str("        ");
-    render_inline_patterns(output, &path_refs);
-    output.push_str(" => {\n");
-    writeln!(
-        output,
-        "            require_arity(name, args.len(), 1, &loc)?;"
-    )
-    .unwrap();
-    writeln!(
-        output,
-        "            let (arg0, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;"
-    )
-    .unwrap();
-    writeln!(
-        output,
-        "            let intrinsic = ScalarMathOp::build(ctx, arg0, {}, {}, {}, {});",
-        scalar_math_format_attr(record),
-        scalar_math_operation_attr(record),
-        scalar_math_precision_attr(record),
-        scalar_math_subnormal_attr(record),
-    )
-    .unwrap();
-    output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
-    writeln!(
-        output,
-        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
-        intrinsic_marker(catalog, record)
-    )
-    .unwrap();
-    output.push_str(
-        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n\
-                     let result = intrinsic.deref(ctx).get_result(0);\n",
-    );
-    writeln!(
-        output,
-        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
-        format!("{} call without target block", record.rust.name)
-    )
-    .unwrap();
-    output.push_str("        }\n");
-}
-
-fn render_importer_extended_minmax_dispatch(
-    output: &mut String,
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-) {
-    let mut path_refs = vec![record.rust.canonical_path.as_str()];
-    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-    output.push_str("        ");
-    render_inline_patterns(output, &path_refs);
-    output.push_str(" => {\n");
-    output.push_str(
-        "            require_arity(name, args.len(), 2, &loc)?;\n\
-                     let (a, last_op) = rvalue::translate_operand(\n\
-                         ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
-                     )?;\n\
-                     let (b, last_op) = rvalue::translate_operand(\n\
-                         ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n\
-                     )?;\n",
-    );
-    writeln!(
-        output,
-        "            let intrinsic = ExtendedMinMaxOp::build(ctx, a, b, {}, {}, {}, {}, {});",
-        extended_minmax_format_attr(record),
-        extended_minmax_operation_attr(record),
-        extended_minmax_subnormal_attr(record),
-        extended_minmax_nan_attr(record),
-        extended_minmax_xorsign_abs_attr(record),
-    )
-    .unwrap();
-    output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
-    writeln!(
-        output,
-        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
-        intrinsic_marker(catalog, record)
-    )
-    .unwrap();
-    output.push_str(
-        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n\
-                     let result = intrinsic.deref(ctx).get_result(0);\n",
-    );
-    writeln!(
-        output,
-        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
-        format!("{} call without target block", record.rust.name)
-    )
-    .unwrap();
-    output.push_str("        }\n");
-}
-
-fn render_importer_elect_dispatch(
-    output: &mut String,
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-) {
-    let mut path_refs = vec![record.rust.canonical_path.as_str()];
-    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-    output.push_str("        ");
-    render_inline_patterns(output, &path_refs);
-    output.push_str(" => {\n");
-    output.push_str(
-        "            require_arity(name, args.len(), 1, &loc)?;\n\
-         \n\
-                     let tuple_ty = crate::translator::types::translate_destination_type(\n\
-                         ctx, body, destination, &loc,\n\
-                     )?;\n\
-                     let (leader_ty, elected_ty) = {\n\
-                         let ty = tuple_ty.deref(ctx);\n\
-                         match ty.downcast_ref::<MirTupleType>() {\n\
-                             Some(tuple) if tuple.get_types().len() == 2 => {\n\
-                                 (tuple.get_types()[0], tuple.get_types()[1])\n\
-                             }\n\
-                             _ => {\n\
-                                 return input_err!(\n\
-                                     loc.clone(),\n\
-                                     TranslationErr::unsupported(\n\
-                                         \"warp::elect_sync destination must be a (u32, bool) tuple\"\n\
-                                             .to_owned()\n\
-                                     )\n\
-                                 );\n\
-                             }\n\
-                         }\n\
-                     };\n\
-                     let (mask, last_op) = rvalue::translate_operand(\n\
-                         ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
-                     )?;\n",
-    );
-    writeln!(
-        output,
-        "            let elect = Operation::new(\n                ctx, {}::get_concrete_op_info(), vec![leader_ty, elected_ty],\n                vec![mask], vec![], 0,\n            );",
-        record.dialect.op_type
-    )
-    .unwrap();
-    output.push_str("            elect.deref_mut(ctx).set_loc(loc.clone());\n");
-    writeln!(
-        output,
-        "            helpers::set_generated_intrinsic_marker(ctx, elect, {:?});",
-        intrinsic_marker(catalog, record)
-    )
-    .unwrap();
-    output.push_str(
-        "            helpers::insert_op(ctx, elect, block_ptr, last_op);\n\
-                     let leader = elect.deref(ctx).get_result(0);\n\
-                     let elected = elect.deref(ctx).get_result(1);\n\
-                     let tuple = Operation::new(\n\
-                         ctx, MirConstructTupleOp::get_concrete_op_info(), vec![tuple_ty],\n\
-                         vec![leader, elected],\n\
-                         vec![], 0,\n\
-                     );\n\
-                     tuple.deref_mut(ctx).set_loc(loc.clone());\n\
-                     tuple.insert_after(ctx, elect);\n\
-                     let result = tuple.deref(ctx).get_result(0);\n",
-    );
-    writeln!(
-        output,
-        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, tuple, value_map, block_map, loc,\n                {:?},\n            )?))",
-        format!("{} call without target block", record.rust.name)
-    )
-    .unwrap();
-    output.push_str("        }\n");
-}
-
-fn render_importer_tcgen05_mma_dispatch(
-    output: &mut String,
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-) {
-    let mma = record
-        .tcgen05
-        .as_ref()
-        .and_then(|tcgen05| tcgen05.mma.as_ref())
-        .expect("tcgen05 MMA record");
-    let mut path_refs = vec![record.rust.canonical_path.as_str()];
-    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-    output.push_str("        ");
-    render_inline_patterns(output, &path_refs);
-    output.push_str(" => {\n");
-    writeln!(
-        output,
-        "            require_arity(name, args.len(), {}, &loc)?;",
-        record.rust.arguments.len()
-    )
-    .unwrap();
-
-    let runtime_indices = if mma.alias.is_some() && mma.form == Tcgen05MmaForm::WsTensor {
-        vec![0, 1, 3, 4, 5]
-    } else if mma.alias.is_some() {
-        (0..record.rust.arguments.len()).collect()
-    } else {
-        let selector_indices = match mma.selector_layout {
-            Tcgen05MmaSelectorLayout::Base {
-                kind_argument,
-                cta_group_argument,
-                collector_a_argument,
-                ..
-            } => [
-                kind_argument as usize,
-                cta_group_argument as usize,
-                collector_a_argument as usize,
-            ],
-            Tcgen05MmaSelectorLayout::WarpSpecialized {
-                kind_argument,
-                b_buffer_argument,
-                b_usage_argument,
-            } => [
-                kind_argument as usize,
-                b_buffer_argument as usize,
-                b_usage_argument as usize,
-            ],
-        };
-        (0..record.rust.arguments.len())
-            .filter(|index| !selector_indices.contains(index))
-            .collect()
-    };
-    writeln!(
-        output,
-        "            let runtime_indices: &[usize] = &{runtime_indices:?};"
-    )
-    .unwrap();
-    output.push_str(
-        "            let mut last_op = prev_op;\n            let mut operands = Vec::with_capacity(runtime_indices.len());\n            for &index in runtime_indices {\n                let (value, translated) = rvalue::translate_operand(\n                    ctx, body, &args[index], value_map, block_ptr, last_op, loc.clone(),\n                )?;\n                last_op = translated;\n                operands.push(value);\n            }\n",
-    );
-
-    if let Some(fixed) = mma.fixed_selectors {
-        writeln!(
-            output,
-            "            let kind = {};",
-            tcgen05_mma_kind_attr(fixed.kind)
-        )
-        .unwrap();
-        match mma.selector_layout {
-            Tcgen05MmaSelectorLayout::Base { .. } => {
-                output.push_str(
-                    "            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;\n            let collector_a = Tcgen05MmaCollectorAAttr::Discard;\n",
-                );
-            }
-            Tcgen05MmaSelectorLayout::WarpSpecialized { .. } => {
-                let b_buffer = match fixed.b_buffer {
-                    0 => "Tcgen05MmaBBufferAttr::B0",
-                    1 => "Tcgen05MmaBBufferAttr::B1",
-                    2 => "Tcgen05MmaBBufferAttr::B2",
-                    3 => "Tcgen05MmaBBufferAttr::B3",
-                    _ => panic!("admitted tcgen05 MMA B buffer"),
-                };
-                writeln!(output, "            let b_buffer = {b_buffer};").unwrap();
-                writeln!(
-                    output,
-                    "            let b_usage = {};",
-                    tcgen05_mma_b_usage_attr(fixed.b_usage)
-                )
-                .unwrap();
-            }
-        }
-    } else {
-        let (kind_argument, second_argument, third_argument) = match mma.selector_layout {
-            Tcgen05MmaSelectorLayout::Base {
-                kind_argument,
-                cta_group_argument,
-                collector_a_argument,
-                ..
-            } => (kind_argument, cta_group_argument, collector_a_argument),
-            Tcgen05MmaSelectorLayout::WarpSpecialized {
-                kind_argument,
-                b_buffer_argument,
-                b_usage_argument,
-            } => (kind_argument, b_buffer_argument, b_usage_argument),
-        };
-        writeln!(
-            output,
-            "            let kind = match generated_tcgen05_mma_selector(args.get({kind_argument}usize)) {{\n                Some(0) => Tcgen05MmaKindAttr::F16,\n                Some(1) => Tcgen05MmaKindAttr::Tf32,\n                Some(2) => Tcgen05MmaKindAttr::F8f6f4,\n                Some(3) => Tcgen05MmaKindAttr::I8,\n                _ => return input_err!(loc.clone(), TranslationErr::unsupported(\"tcgen05 MMA kind must be a compile-time u32 constant in 0..=3\".to_owned())),\n            }};"
-        )
-        .unwrap();
-        match mma.selector_layout {
-            Tcgen05MmaSelectorLayout::Base {
-                collector_a_upper_exclusive,
-                ..
-            } => {
-                writeln!(
-                    output,
-                    "            let cta_group = match generated_tcgen05_mma_selector(args.get({second_argument}usize)) {{\n                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,\n                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,\n                _ => {{\n                    return input_err!(\n                        loc.clone(),\n                        TranslationErr::unsupported(\n                            \"tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2\"\n                                .to_owned()\n                        )\n                    );\n                }}\n            }};"
-                )
-                .unwrap();
-                let collector_arms = if collector_a_upper_exclusive == 2 {
-                    "                Some(0) => Tcgen05MmaCollectorAAttr::Discard,\n                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,\n"
-                } else {
-                    "                Some(0) => Tcgen05MmaCollectorAAttr::Discard,\n                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,\n                Some(2) => Tcgen05MmaCollectorAAttr::Fill,\n                Some(3) => Tcgen05MmaCollectorAAttr::Use,\n"
-                };
-                writeln!(
-                    output,
-                    "            let collector_a = match generated_tcgen05_mma_selector(args.get({third_argument}usize)) {{\n{collector_arms}                _ => return input_err!(loc.clone(), TranslationErr::unsupported(\"tcgen05 MMA collector-A selector is outside its closed range\".to_owned())),\n            }};"
-                )
-                .unwrap();
-            }
-            Tcgen05MmaSelectorLayout::WarpSpecialized { .. } => {
-                writeln!(
-                    output,
-                    "            let b_buffer = match generated_tcgen05_mma_selector(args.get({second_argument}usize)) {{\n                Some(0) => Tcgen05MmaBBufferAttr::B0,\n                Some(1) => Tcgen05MmaBBufferAttr::B1,\n                Some(2) => Tcgen05MmaBBufferAttr::B2,\n                Some(3) => Tcgen05MmaBBufferAttr::B3,\n                _ => return input_err!(loc.clone(), TranslationErr::unsupported(\"tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3\".to_owned())),\n            }};"
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "            let b_usage = match generated_tcgen05_mma_selector(args.get({third_argument}usize)) {{\n                Some(0) => Tcgen05MmaBUsageAttr::Discard,\n                Some(1) => Tcgen05MmaBUsageAttr::LastUse,\n                Some(2) => Tcgen05MmaBUsageAttr::Fill,\n                Some(3) => Tcgen05MmaBUsageAttr::Use,\n                _ => return input_err!(loc.clone(), TranslationErr::unsupported(\"tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3\".to_owned())),\n            }};"
-                )
-                .unwrap();
-            }
-        }
-    }
-
-    output.push_str(
-        "            let intrinsic = Operation::new(ctx, Tcgen05MmaOp::get_concrete_op_info(), vec![], operands, vec![], 0);\n            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n            let mma_op = Tcgen05MmaOp::new(intrinsic);\n",
-    );
-    writeln!(
-        output,
-        "            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, {});",
-        tcgen05_mma_form_attr(mma.form)
-    )
-    .unwrap();
-    output.push_str("            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);\n");
-    match mma.selector_layout {
-        Tcgen05MmaSelectorLayout::Base { .. } => output.push_str(
-            "            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);\n            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);\n",
-        ),
-        Tcgen05MmaSelectorLayout::WarpSpecialized { .. } => output.push_str(
-            "            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);\n            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);\n",
-        ),
-    }
-    writeln!(
-        output,
-        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
-        intrinsic_marker(catalog, record)
-    )
-    .unwrap();
-    output.push_str(
-        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, intrinsic, block_map, loc)))\n            } else {\n",
-    );
-    writeln!(
-        output,
-        "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-        format!("{} call without target block", record.rust.name)
-    )
-    .unwrap();
-    output.push_str("            }\n        }\n");
-}
-
-fn render_importer(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Generated raw/compatibility path dispatch for CUDA intrinsics.\n\nuse crate::error::{TranslationErr, TranslationResult};\nuse crate::translator::{rvalue, terminator::helpers};\nuse crate::translator::values::ValueMap;\nuse dialect_nvvm::ops::{",
-    );
-    for (index, record) in sregs(catalog).enumerate() {
-        if index != 0 {
-            output.push_str(", ");
-        }
-        output.push_str(&record.dialect.op_type);
-    }
-    if ldmatrix(catalog).next().is_some() {
-        if sregs(catalog).next().is_some() {
-            output.push_str(", ");
-        }
-        output.push_str("LdmatrixElementAttr, LdmatrixLayoutAttr, LdmatrixMultiplicityAttr, LdmatrixOp, LdmatrixShapeAttr, LdmatrixStateSpaceAttr");
-    }
-    if let Some(record) = movmatrix(catalog).next() {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    if register_mmas(catalog).next().is_some() {
-        output.push_str(", RegisterMmaAccumulatorAttr, RegisterMmaElementAttr, RegisterMmaKindAttr, RegisterMmaLayoutAttr, RegisterMmaOp, RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr");
-    }
-    if sparse_mmas(catalog).next().is_some() {
-        output.push_str(", SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr, SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr");
-    }
-    if prmts(catalog).next().is_some() {
-        output.push_str(", PrmtModeAttr, PrmtOp");
-    }
-    if scalar_conversions(catalog).next().is_some() {
-        output.push_str(
-            ", ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr",
-        );
-    }
-    if scalar_arithmetics(catalog).next().is_some() {
-        output.push_str(
-            ", ScalarArithmeticFormatAttr, ScalarArithmeticOp, ScalarArithmeticOperationAttr, ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr",
-        );
-    }
-    if scalar_maths(catalog).next().is_some() {
-        output.push_str(
-            ", ScalarMathFormatAttr, ScalarMathOp, ScalarMathOperationAttr, ScalarMathPrecisionAttr, ScalarMathSubnormalAttr",
-        );
-    }
-    if extended_minmax(catalog).next().is_some() {
-        output.push_str(
-            ", ExtendedMinMaxFormatAttr, ExtendedMinMaxNanAttr, ExtendedMinMaxOp, ExtendedMinMaxOperationAttr, ExtendedMinMaxSubnormalAttr, ExtendedMinMaxXorSignAbsAttr",
-        );
-    }
-    if cluster_barriers(catalog).next().is_some() {
-        output.push_str(", ClusterBarrierModeAttr, ClusterBarrierOp");
-    }
-    if debug_controls(catalog).next().is_some() {
-        output.push_str(", BreakpointOp, PmEventOp, TrapOp");
-    }
-    for record in cluster_memory(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    for record in clc_intrinsics(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    for record in execution_controls(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    if wgmma_controls(catalog).next().is_some() {
-        output.push_str(
-            ", WgmmaCommitGroupSyncAlignedOp, WgmmaFenceSyncAlignedOp, WgmmaWaitGroupSyncAlignedOp",
-        );
-    }
-    if packed_atomics(catalog).next().is_some() {
-        if sregs(catalog).next().is_some() || ldmatrix(catalog).next().is_some() {
-            output.push_str(", ");
-        }
-        output.push_str("PackedAtomicAddOp, PackedAtomicFormatAttr");
-    }
-    if redux(catalog).next().is_some() {
-        if sregs(catalog).next().is_some()
-            || ldmatrix(catalog).next().is_some()
-            || packed_atomics(catalog).next().is_some()
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in redux(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if vote_intrinsics(catalog).next().is_some() {
-        if sregs(catalog).next().is_some()
-            || ldmatrix(catalog).next().is_some()
-            || packed_atomics(catalog).next().is_some()
-            || redux(catalog).next().is_some()
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in vote_intrinsics(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if active_masks(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in active_masks(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if warp_matches(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in warp_matches(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    for record in elect_intrinsics(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    if warp_barriers(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in warp_barriers(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if warp_shuffles(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in warp_shuffles(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if packed_alus(catalog).next().is_some() {
-        if sregs(catalog).next().is_some()
-            || ldmatrix(catalog).next().is_some()
-            || packed_atomics(catalog).next().is_some()
-            || redux(catalog).next().is_some()
-            || vote_intrinsics(catalog).next().is_some()
-            || active_masks(catalog).next().is_some()
-            || warp_matches(catalog).next().is_some()
-            || warp_barriers(catalog).next().is_some()
-            || warp_shuffles(catalog).next().is_some()
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in packed_alus(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if integer_minmaxes(catalog).next().is_some() {
-        // packed_alu records always exist, so a separator is always needed.
-        output.push_str(", ");
-        for (index, record) in integer_minmaxes(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if packed_conversions(catalog).next().is_some() {
-        if sregs(catalog).next().is_some()
-            || ldmatrix(catalog).next().is_some()
-            || packed_atomics(catalog).next().is_some()
-            || redux(catalog).next().is_some()
-            || vote_intrinsics(catalog).next().is_some()
-            || active_masks(catalog).next().is_some()
-            || warp_matches(catalog).next().is_some()
-            || warp_barriers(catalog).next().is_some()
-            || warp_shuffles(catalog).next().is_some()
-            || packed_alus(catalog).next().is_some()
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in packed_conversions(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if cp_async_copies(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in cp_async_copies(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if cp_async_controls(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in cp_async_controls(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if cp_async_mbarriers(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in cp_async_mbarriers(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    for record in mbarrier_basics(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    for record in mbarrier_extended(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    if dot_products(catalog).next().is_some() {
-        if sregs(catalog).next().is_some()
-            || ldmatrix(catalog).next().is_some()
-            || packed_atomics(catalog).next().is_some()
-            || redux(catalog).next().is_some()
-            || vote_intrinsics(catalog).next().is_some()
-            || packed_alus(catalog).next().is_some()
-            || packed_conversions(catalog).next().is_some()
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in dot_products(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if sync_intrinsics(catalog).next().is_some() {
-        if sregs(catalog).next().is_some()
-            || ldmatrix(catalog).next().is_some()
-            || packed_atomics(catalog).next().is_some()
-            || redux(catalog).next().is_some()
-            || vote_intrinsics(catalog).next().is_some()
-            || dot_products(catalog).next().is_some()
-            || packed_alus(catalog).next().is_some()
-            || packed_conversions(catalog).next().is_some()
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in sync_intrinsics(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    for record in stmatrices(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    for record in tcgen05_non_mma_intrinsics(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    if tcgen05_mma_intrinsics(catalog).next().is_some() {
-        output.push_str(", Tcgen05MmaBBufferAttr, Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr, Tcgen05MmaFormAttr, Tcgen05MmaKindAttr, Tcgen05MmaOp");
-    }
-    output.push_str(
-        "};\nuse pliron::basic_block::BasicBlock;\nuse pliron::context::{Context, Ptr};\nuse pliron::input_err;\nuse pliron::location::{Located, Location};\nuse pliron::op::Op;\nuse pliron::operation::Operation;\nuse rustc_public::{CrateDef, mir, ty::FnDef};\n\n",
-    );
-    if debug_controls(catalog).next().is_some()
-        || execution_control_family(catalog, "register_control")
-            .next()
-            .is_some()
-    {
-        output.push_str("use dialect_mir::ops::{MirConstantOp, MirUnreachableOp};\n\n");
-    } else if wgmma_controls(catalog).next().is_some() {
-        output.push_str("use dialect_mir::ops::MirConstantOp;\n\n");
-    }
-    if register_mmas(catalog).next().is_some()
-        || sparse_mmas(catalog).next().is_some()
-        || tcgen05_intrinsics(catalog).next().is_some()
-    {
-        output.push_str(
-            "use dialect_mir::{attributes::FieldIndexAttr, ops::{MirConstructArrayOp, MirConstructStructOp, MirExtractFieldOp}, types::{MirArrayType, MirStructType}};\nuse pliron::{builtin::types::{FP32Type, FP64Type, IntegerType, Signedness}, r#type::{TypeHandle, Typed}, value::Value};\n\n",
-        );
-    }
-    if tcgen05_intrinsics(catalog).next().is_some() {
-        output = output.replace(
-            "use crate::translator::{rvalue, terminator::helpers};",
-            "use crate::translator::{rvalue, terminator::helpers, types};",
-        );
-    }
-    if elect_intrinsics(catalog).next().is_some() {
-        output.push_str("use dialect_mir::{ops::MirConstructTupleOp, types::MirTupleType};\n\n");
-    }
-    writeln!(
-        output,
-        "pub const GENERATED_INTRINSIC_ABI: u32 = {};",
-        catalog.intrinsic_abi
-    )
-    .unwrap();
-    writeln!(
-        output,
-        "pub const GENERATED_INTRINSIC_ABI_NAMESPACE: &str = {:?};\n",
-        format!("__cuda_oxide_intrinsic_abi_v{}", catalog.intrinsic_abi)
-    )
-    .unwrap();
-    output.push_str(
-        "#[derive(Debug, Clone, PartialEq, Eq)]\npub enum RawIntrinsicIdentity {\n    NotRawCrate,\n    Known(String),\n    UnsupportedAbi(String),\n    UnknownId(String),\n}\n\n/// Classify the unrewritten raw intrinsic DefPath. rustc's ordinary name\n/// printer may prefer a public re-export path, which is source API rather than ABI.\npub fn classify_raw_intrinsic(fn_def: FnDef) -> RawIntrinsicIdentity {\n    let crate_name = fn_def.krate().name.to_string();\n    if !matches!(crate_name.as_str(), \"cuda_intrinsics\" | \"cuda-intrinsics\") {\n        return RawIntrinsicIdentity::NotRawCrate;\n    }\n\n    let mut segments = Vec::new();\n    let mut current = Some(fn_def.def_id());\n    while let Some(def_id) = current {\n        let printed = def_id.name();\n        let segment = printed.as_str().rsplit(\"::\").next().unwrap_or_default();\n        if segment != crate_name {\n            segments.push(segment.to_owned());\n        }\n        current = def_id.parent();\n    }\n    segments.reverse();\n    classify_raw_intrinsic_path(&crate_name, format!(\"{crate_name}::{}\", segments.join(\"::\")))\n}\n\nfn classify_raw_intrinsic_path(crate_name: &str, path: String) -> RawIntrinsicIdentity {\n    if !matches!(crate_name, \"cuda_intrinsics\" | \"cuda-intrinsics\") {\n        return RawIntrinsicIdentity::NotRawCrate;\n    }\n    if is_raw_generated_intrinsic_path(&path) {\n        return RawIntrinsicIdentity::Known(path);\n    }\n    let namespace = path.split(\"::\").nth(1).unwrap_or_default();\n    if namespace.starts_with(\"__cuda_oxide_intrinsic_abi_v\")\n        && namespace != GENERATED_INTRINSIC_ABI_NAMESPACE\n    {\n        RawIntrinsicIdentity::UnsupportedAbi(path)\n    } else {\n        RawIntrinsicIdentity::UnknownId(path)\n    }\n}\n\npub fn require_supported_raw_intrinsic(\n    fn_def: FnDef,\n    loc: &Location,\n) -> TranslationResult<Option<String>> {\n    match classify_raw_intrinsic(fn_def) {\n        RawIntrinsicIdentity::NotRawCrate => Ok(None),\n        RawIntrinsicIdentity::Known(path) => Ok(Some(path)),\n        RawIntrinsicIdentity::UnsupportedAbi(path) => input_err!(\n            loc.clone(),\n            TranslationErr::unsupported(format!(\n                \"cuda-intrinsics ABI mismatch: `{path}` uses an unsupported intrinsic ABI; this compiler supports ABI v{GENERATED_INTRINSIC_ABI}\"\n            ))\n        ),\n        RawIntrinsicIdentity::UnknownId(path) => input_err!(\n            loc.clone(),\n            TranslationErr::unsupported(format!(\n                \"cuda-intrinsics ABI mismatch: `{path}` is not a known intrinsic ID in ABI v{GENERATED_INTRINSIC_ABI}\"\n            ))\n        ),\n    }\n}\n\n",
-    );
-    output
-        .push_str("pub fn is_generated_intrinsic_path(name: &str) -> bool {\n    matches!(name,\n");
-    render_compiler_path_patterns(&mut output, catalog, "        ");
-    output.push_str("    )\n}\n\npub fn is_raw_generated_intrinsic_path(name: &str) -> bool {\n    matches!(name,\n");
-    let raw_paths: Vec<_> = catalog
-        .intrinsics
-        .iter()
-        .map(|record| record.rust.canonical_path.as_str())
-        .collect();
-    render_string_patterns(&mut output, &raw_paths, "        ");
-    // Test-only. The dispatch arms rendered below carry each marker as a
-    // literal, and the op-name-keyed lookup the compiler actually calls lives
-    // in `cuda-oxide-codegen`; nothing outside this file's own generated tests
-    // reads this path-keyed table. Gate it rather than leave a 2000-line match
-    // sitting unreferenced in the compiler.
-    output.push_str("    )\n}\n\n#[cfg(test)]\npub fn generated_intrinsic_marker(name: &str) -> Option<&'static str> {\n    match name {\n");
-    for record in &catalog.intrinsics {
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        writeln!(output, " => Some({:?}),", intrinsic_marker(catalog, record)).unwrap();
-    }
-    output.push_str("        _ => None,\n    }\n}\n\n");
-    output.push_str(
-        "#[allow(clippy::too_many_arguments)]\npub fn try_dispatch_generated_intrinsic(\n    ctx: &mut Context,\n    body: &mir::Body,\n    name: &str,\n    args: &[mir::Operand],\n    destination: &mir::Place,\n    target: &Option<usize>,\n    block_ptr: Ptr<BasicBlock>,\n    prev_op: Option<Ptr<Operation>>,\n    value_map: &mut ValueMap,\n    block_map: &[Ptr<BasicBlock>],\n    loc: Location,\n) -> TranslationResult<Option<Ptr<Operation>>> {\n    match name {\n",
-    );
-    for record in sregs(catalog) {
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        writeln!(
-            output,
-            "            require_arity(name, args.len(), 0, &loc)?;"
-        )
-        .unwrap();
-        let helper = if record.scalar_width() == Some(64) {
-            "emit_generated_nvvm_intrinsic_u64"
-        } else {
-            "emit_generated_nvvm_intrinsic"
-        };
-        writeln!(output, "            Ok(Some(helpers::{helper}(").unwrap();
-        writeln!(
-            output,
-            "                ctx, {}::get_concrete_op_info(), {:?}, destination, target, block_ptr,",
-            record.dialect.op_type,
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "                prev_op, value_map, block_map, loc,\n            )?))\n        }\n",
-        );
-    }
-    for record in active_masks(catalog) {
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 0, &loc)?;\n");
-        writeln!(
-            output,
-            "            let active_mask = {}::build(ctx);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            active_mask.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, active_mask, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, active_mask, block_ptr, prev_op);\n            let result = active_mask.deref(ctx).get_result(0);\n",
-        );
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, active_mask, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in ldmatrix(catalog) {
-        let (shape, multiplicity, layout, element, state_space) = ldmatrix_attr_variants(record);
-        let register_count = record.ldmatrix.as_ref().unwrap().variant.register_count();
-        output.push_str("        ");
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 1, &loc)?;\n");
-        output.push_str(
-            "            let (address, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-        );
-        writeln!(
-            output,
-            "            let load = LdmatrixOp::build(ctx, address, {shape}, {multiplicity}, {layout}, {element}, {state_space});"
-        )
-        .unwrap();
-        output.push_str("            load.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, load, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str("            helpers::insert_op(ctx, load, block_ptr, last_op);\n");
-        if register_count == 1 {
-            output.push_str("            let value = load.deref(ctx).get_result(0);\n");
-            output.push_str("            let last_op = load;\n");
-        } else {
-            writeln!(
-                output,
-                "            let (value, last_op) = helpers::bundle_generated_u32_results_as_array(ctx, load, {register_count}, loc.clone());"
-            )
-            .unwrap();
-        }
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, value, target, block_ptr, last_op, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in stmatrices(catalog) {
-        let (multiplicity, _) = stmatrix_variant(record).expect("stmatrix variant");
-        let arity = multiplicity.register_count() + 1;
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        writeln!(
-            output,
-            "            require_arity(name, args.len(), {arity}, &loc)?;"
-        )
-        .unwrap();
-        output.push_str(
-            "            let mut last_op = prev_op;\n            let mut operands = Vec::with_capacity(args.len());\n            for arg in args {\n                let (value, translated) = rvalue::translate_operand(\n                    ctx, body, arg, value_map, block_ptr, last_op, loc.clone(),\n                )?;\n                last_op = translated;\n                operands.push(value);\n            }\n",
-        );
-        writeln!(
-            output,
-            "            let store = Operation::new(ctx, {}::get_concrete_op_info(), vec![], operands, vec![], 0);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            store.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, store, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, store, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, store, block_map, loc)))\n            } else {\n",
-        );
-        writeln!(
-            output,
-            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-            format!(
-                "{} call without target block",
-                stmatrix_compatibility_name(record)
-            )
-        )
-        .unwrap();
-        output.push_str("            }\n        }\n");
-    }
-    for record in register_mmas(catalog) {
-        let adapter = match record.register_mma.as_ref().unwrap().adapter {
-            RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32 => {
-                "GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32"
-            }
-            RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => {
-                "GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32"
-            }
-            RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32 => {
-                "GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32"
-            }
-            RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32 => {
-                "GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32"
-            }
-            RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 => {
-                "GeneratedMmaImportAdapter::C2F64A1F64B1F64ToD2F64"
-            }
-            RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32 => {
-                "GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32"
-            }
-            RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32 => {
-                "GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32"
-            }
-            RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => {
-                "GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32"
-            }
-            RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => {
-                "GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32"
-            }
-        };
-        let (
-            shape,
-            operation,
-            kind,
-            accumulator,
-            a_element,
-            b_element,
-            a_layout,
-            b_layout,
-            overflow,
-        ) = register_mma_attr_variants(record);
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        let arity = record.rust.arguments.len();
-        writeln!(
-            output,
-            "            require_arity(name, args.len(), {arity}, &loc)?;"
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(ctx, body, args, block_ptr, prev_op, value_map, loc.clone(), {adapter})?;"
-        )
-        .unwrap();
-        output.push_str(
-            "            let mma = Operation::new(ctx, RegisterMmaOp::get_concrete_op_info(), vec![result_ty; result_count], operands, vec![], 0);\n            mma.deref_mut(ctx).set_loc(loc.clone());\n            let mma = RegisterMmaOp::new(mma);\n",
-        );
-        writeln!(
-            output,
-            "            mma.set_attr_nvvm_register_mma_shape(ctx, {shape});\n            mma.set_attr_nvvm_register_mma_operation(ctx, {operation});\n            mma.set_attr_nvvm_register_mma_kind(ctx, {kind});\n            mma.set_attr_nvvm_register_mma_accumulator(ctx, {accumulator});\n            mma.set_attr_nvvm_register_mma_a_element(ctx, {a_element});\n            mma.set_attr_nvvm_register_mma_b_element(ctx, {b_element});\n            mma.set_attr_nvvm_register_mma_a_layout(ctx, {a_layout});\n            mma.set_attr_nvvm_register_mma_b_layout(ctx, {b_layout});\n            mma.set_attr_nvvm_register_mma_overflow(ctx, {overflow});"
-        )
-        .unwrap();
-        output.push_str("            let mma = mma.get_operation();\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, mma, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));\n            let (result, last_op) = bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());\n",
-        );
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, last_op, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in sparse_mmas(catalog) {
-        let (
-            shape,
-            accumulator,
-            a_element,
-            b_element,
-            a_layout,
-            b_layout,
-            overflow,
-            metadata,
-            selector,
-        ) = sparse_mma_attr_variants(record);
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 5, &loc)?;\n");
-        writeln!(
-            output,
-            "            if !matches!(&args[4], mir::Operand::Constant(_)) {{\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        {:?}.to_owned()\n                    )\n                );\n            }}",
-            sparse_mma_selector_error(record)
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(ctx, body, args, block_ptr, prev_op, value_map, loc.clone(), {})?;",
-            sparse_mma_import_adapter(record)
-        )
-        .unwrap();
-        output.push_str(
-            "            let (metadata, last_op) = rvalue::translate_operand(\n                ctx, body, &args[3], value_map, block_ptr, Some(last_op), loc.clone(),\n            )?;\n            operands.push(metadata);\n            let (selector_value, last_op) = rvalue::translate_operand(\n                ctx, body, &args[4], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n            operands.push(selector_value);\n",
-        );
-        output.push_str(
-            "            let mma = Operation::new(ctx, SparseMmaOp::get_concrete_op_info(), vec![result_ty; result_count], operands, vec![], 0);\n            mma.deref_mut(ctx).set_loc(loc.clone());\n            let mma = SparseMmaOp::new(mma);\n",
-        );
-        writeln!(
-            output,
-            "            mma.set_attr_nvvm_sparse_mma_shape(ctx, {shape});\n            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, {accumulator});\n            mma.set_attr_nvvm_sparse_mma_a_element(ctx, {a_element});\n            mma.set_attr_nvvm_sparse_mma_b_element(ctx, {b_element});\n            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, {a_layout});\n            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, {b_layout});\n            mma.set_attr_nvvm_sparse_mma_overflow(ctx, {overflow});\n            mma.set_attr_nvvm_sparse_mma_metadata(ctx, {metadata});\n            mma.set_attr_nvvm_sparse_mma_selector(ctx, {selector});"
-        )
-        .unwrap();
-        output.push_str("            let mma = mma.get_operation();\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, mma, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, mma, block_ptr, last_op);\n            let (result, last_op) = bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());\n",
-        );
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, last_op, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in packed_atomics(catalog) {
-        let format = match record.packed_atomic.as_ref().unwrap().format {
-            PackedAtomicFormat::F16x2 => "PackedAtomicFormatAttr::F16x2",
-            PackedAtomicFormat::Bf16x2 => "PackedAtomicFormatAttr::Bf16x2",
-        };
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 2, &loc)?;\n");
-        output.push_str(
-            "            let (address, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-        );
-        output.push_str(
-            "            let (addend, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-        );
-        writeln!(
-            output,
-            "            let atom = PackedAtomicAddOp::build(ctx, address, addend, {format});"
-        )
-        .unwrap();
-        output.push_str("            atom.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, atom, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str("            helpers::insert_op(ctx, atom, block_ptr, last_op);\n");
-        output.push_str("            let value = atom.deref(ctx).get_result(0);\n");
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, value, target, block_ptr, atom, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in redux(catalog) {
-        debug_assert_eq!(
-            record.redux.as_ref().unwrap().adapter,
-            ReduxAdapter::MaskValueToSourceMemberMask
-        );
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 2, &loc)?;\n");
-        output.push_str(
-            "            let (member_mask, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-        );
-        output.push_str(
-            "            let (value, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-        );
-        writeln!(
-            output,
-            "            let reduction = {}::build(ctx, member_mask, value);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            reduction.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, reduction, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, reduction, block_ptr, last_op);\n            let result = reduction.deref(ctx).get_result(0);\n",
-        );
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, reduction, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in vote_intrinsics(catalog) {
-        debug_assert_eq!(
-            record.vote.as_ref().unwrap().adapter,
-            VoteAdapter::DirectMaskPredicate
-        );
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 2, &loc)?;\n");
-        output.push_str(
-            "            let (member_mask, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-        );
-        output.push_str(
-            "            let (predicate, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-        );
-        writeln!(
-            output,
-            "            let vote = {}::build(ctx, member_mask, predicate);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            vote.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, vote, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, vote, block_ptr, last_op);\n            let result = vote.deref(ctx).get_result(0);\n",
-        );
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, vote, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in warp_matches(catalog) {
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 2, &loc)?;\n");
-        output.push_str(
-            "            let (member_mask, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-        );
-        output.push_str(
-            "            let (value, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-        );
-        writeln!(
-            output,
-            "            let warp_match = {}::build(ctx, member_mask, value);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            warp_match.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, warp_match, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, warp_match, block_ptr, last_op);\n            let result = warp_match.deref(ctx).get_result(0);\n",
-        );
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, warp_match, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in elect_intrinsics(catalog) {
-        render_importer_elect_dispatch(&mut output, catalog, record);
-    }
-    for record in warp_barriers(catalog) {
-        debug_assert_eq!(
-            record.warp_barrier.as_ref().unwrap().adapter,
-            WarpBarrierAdapter::DirectMemberMask
-        );
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 1, &loc)?;\n");
-        output.push_str(
-            "            let (member_mask, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-        );
-        writeln!(
-            output,
-            "            let barrier = {}::build(ctx, member_mask);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            barrier.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, barrier, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, barrier, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, barrier, block_map, loc)))\n            } else {\n",
-        );
-        writeln!(
-            output,
-            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("            }\n        }\n");
-    }
-    for record in warp_shuffles(catalog) {
-        debug_assert!(matches!(
-            record.warp_shuffle.as_ref().unwrap().adapter,
-            WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp
-                | WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
-        ));
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 3, &loc)?;\n");
-        output.push_str(
-            "            let (member_mask, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-        );
-        output.push_str(
-            "            let (value, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-        );
-        output.push_str(
-            "            let (lane_or_delta, last_op) = rvalue::translate_operand(\n                ctx, body, &args[2], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-        );
-        writeln!(
-            output,
-            "            let shuffle = {}::build(ctx, member_mask, value, lane_or_delta);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            shuffle.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, shuffle, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, shuffle, block_ptr, last_op);\n            let result = shuffle.deref(ctx).get_result(0);\n",
-        );
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, shuffle, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in dot_products(catalog) {
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 3, &loc)?;\n");
-        output.push_str(
-            "            let (a, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-        );
-        output.push_str(
-            "            let (b, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-        );
-        output.push_str(
-            "            let (c, last_op) = rvalue::translate_operand(\n                ctx, body, &args[2], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-        );
-        writeln!(
-            output,
-            "            let dot = {}::build(ctx, a, b, c);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            dot.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, dot, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, dot, block_ptr, last_op);\n            let result = dot.deref(ctx).get_result(0);\n",
-        );
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, dot, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in packed_alus(catalog) {
-        render_importer_pure_value_dispatch(&mut output, catalog, record);
-    }
-    for record in integer_minmaxes(catalog) {
-        render_importer_pure_value_dispatch(&mut output, catalog, record);
-    }
-    for record in packed_conversions(catalog) {
-        render_importer_pure_value_dispatch(&mut output, catalog, record);
-    }
-    for record in scalar_conversions(catalog) {
-        render_importer_scalar_conversion_dispatch(&mut output, catalog, record);
-    }
-    for record in scalar_arithmetics(catalog) {
-        render_importer_scalar_arithmetic_dispatch(&mut output, catalog, record);
-    }
-    for record in scalar_maths(catalog) {
-        render_importer_scalar_math_dispatch(&mut output, catalog, record);
-    }
-    for record in extended_minmax(catalog) {
-        render_importer_extended_minmax_dispatch(&mut output, catalog, record);
-    }
-    for record in movmatrix(catalog) {
-        render_importer_pure_value_dispatch(&mut output, catalog, record);
-    }
-    for record in prmts(catalog) {
-        let mode = match record.prmt.as_ref().unwrap().mode {
-            PrmtMode::Generic => "PrmtModeAttr::Generic",
-            PrmtMode::F4e => "PrmtModeAttr::F4e",
-            PrmtMode::B4e => "PrmtModeAttr::B4e",
-            PrmtMode::Rc8 => "PrmtModeAttr::Rc8",
-            PrmtMode::Ecl => "PrmtModeAttr::Ecl",
-            PrmtMode::Ecr => "PrmtModeAttr::Ecr",
-            PrmtMode::Rc16 => "PrmtModeAttr::Rc16",
-        };
-        let arity = record.rust.arguments.len();
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        writeln!(
-            output,
-            "            require_arity(name, args.len(), {arity}, &loc)?;"
-        )
-        .unwrap();
-        for index in 0..arity {
-            let previous = if index == 0 { "prev_op" } else { "last_op" };
-            writeln!(
-                output,
-                "            let (arg{index}, last_op) = rvalue::translate_operand(\n                ctx, body, &args[{index}], value_map, block_ptr, {previous}, loc.clone(),\n            )?;"
-            )
-            .unwrap();
-        }
-        let arguments = (0..arity)
-            .map(|index| format!("arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(
-            output,
-            "            let prmt = PrmtOp::build(ctx, vec![{arguments}], {mode});"
-        )
-        .unwrap();
-        output.push_str("            prmt.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, prmt, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, prmt, block_ptr, last_op);\n            let result = prmt.deref(ctx).get_result(0);\n",
-        );
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, prmt, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    if cluster_barriers(catalog).next().is_some() {
-        let arrive = cluster_barriers(catalog)
-            .find(|record| {
-                record
-                    .cluster_barrier
-                    .as_ref()
-                    .is_some_and(|barrier| barrier.mode == ClusterBarrierMode::ArriveAligned)
-            })
-            .expect("aligned cluster arrival");
-        let wait = cluster_barriers(catalog)
-            .find(|record| {
-                record
-                    .cluster_barrier
-                    .as_ref()
-                    .is_some_and(|barrier| barrier.mode == ClusterBarrierMode::WaitAligned)
-            })
-            .expect("aligned cluster wait");
-        output.push_str(
-            "        \"cuda_device::cluster::cluster_sync\" => {\n            require_arity(name, args.len(), 0, &loc)?;\n            let arrive = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::ArriveAligned);\n            arrive.deref_mut(ctx).set_loc(loc.clone());\n",
-        );
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, arrive, {:?});",
-            intrinsic_marker(catalog, arrive)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, arrive, block_ptr, prev_op);\n            let wait = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::WaitAligned);\n            wait.deref_mut(ctx).set_loc(loc.clone());\n",
-        );
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, wait, {:?});",
-            intrinsic_marker(catalog, wait)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, wait, block_ptr, Some(arrive));\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, wait, block_map, loc)))\n            } else {\n                input_err!(loc, TranslationErr::unsupported(\"cluster_sync call without target block\".to_owned()))\n            }\n        }\n",
-        );
-    }
-    for record in cluster_barriers(catalog) {
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n            require_arity(name, args.len(), 0, &loc)?;\n");
-        writeln!(
-            output,
-            "            let barrier = ClusterBarrierOp::build(ctx, {});",
-            cluster_barrier_attr(record)
-        )
-        .unwrap();
-        output.push_str("            barrier.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, barrier, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, barrier, block_ptr, prev_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, barrier, block_map, loc)))\n            } else {\n",
-        );
-        writeln!(
-            output,
-            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("            }\n        }\n");
-    }
-    for record in cluster_memory(catalog) {
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str(
-            "            require_arity(name, args.len(), 2, &loc)?;\n\
-             let (source, last_op) = rvalue::translate_operand(\n\
-                 ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
-             )?;\n\
-             let (rank, last_op) = rvalue::translate_operand(\n\
-                 ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n\
-             )?;\n",
-        );
-        writeln!(
-            output,
-            "            let cluster = {}::build(ctx, source, rank);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            cluster.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, cluster, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, cluster, block_ptr, last_op);\n\
-             let result = cluster.deref(ctx).get_result(0);\n",
-        );
-        writeln!(
-            output,
-            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, cluster, value_map, block_map, loc,\n                {:?},\n            )?))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("        }\n");
-    }
-    for record in debug_controls(catalog) {
-        let operation = record.debug_control.as_ref().unwrap().operation;
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        match operation {
-            DebugControlOperation::Trap => {
-                output.push_str("            require_arity(name, args.len(), 0, &loc)?;\n");
-                output.push_str("            let debug = TrapOp::build(ctx);\n");
-                output.push_str("            debug.deref_mut(ctx).set_loc(loc.clone());\n");
-                writeln!(
-                    output,
-                    "            helpers::set_generated_intrinsic_marker(ctx, debug, {:?});",
-                    intrinsic_marker(catalog, record)
-                )
-                .unwrap();
-                output.push_str(
-                    "            helpers::insert_op(ctx, debug, block_ptr, prev_op);\n\
-                     let unreachable = Operation::new(\n\
-                         ctx, MirUnreachableOp::get_concrete_op_info(), vec![], vec![], vec![], 0,\n\
-                     );\n\
-                     unreachable.deref_mut(ctx).set_loc(loc);\n\
-                     helpers::insert_op(ctx, unreachable, block_ptr, Some(debug));\n\
-                     Ok(Some(unreachable))\n",
-                );
-            }
-            DebugControlOperation::Breakpoint => {
-                output.push_str("            require_arity(name, args.len(), 0, &loc)?;\n");
-                output.push_str("            let debug = BreakpointOp::build(ctx);\n");
-                output.push_str("            debug.deref_mut(ctx).set_loc(loc.clone());\n");
-                writeln!(
-                    output,
-                    "            helpers::set_generated_intrinsic_marker(ctx, debug, {:?});",
-                    intrinsic_marker(catalog, record)
-                )
-                .unwrap();
-                output.push_str(
-                    "            helpers::insert_op(ctx, debug, block_ptr, prev_op);\n\
-                     if let Some(target_idx) = target {\n\
-                         Ok(Some(helpers::emit_goto(ctx, *target_idx, debug, block_map, loc)))\n\
-                     } else {\n",
-                );
-                writeln!(
-                    output,
-                    "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-                    format!("{} call without target block", record.rust.name)
-                )
-                .unwrap();
-                output.push_str("            }\n");
-            }
-            DebugControlOperation::Pmevent => {
-                output.push_str(
-                    "            require_arity(name, args.len(), 1, &loc)?;\n\
-                     if !matches!(&args[0], mir::Operand::Constant(_)) {\n\
-                         return input_err!(\n\
-                             loc,\n\
-                             TranslationErr::unsupported(\n\
-                                 \"prof_trigger requires a compile-time constant event ID in 0..=15\".to_owned()\n\
-                             )\n\
-                         );\n\
-                     }\n\
-                     let (event_id_value, last_op) = rvalue::translate_operand(\n\
-                         ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
-                     )?;\n\
-                     let event_id = event_id_value\n\
-                         .defining_op()\n\
-                         .and_then(|defining_op| Operation::get_op::<MirConstantOp>(defining_op, ctx))\n\
-                         .and_then(|constant| constant.get_attr_value(ctx))\n\
-                         .map(|value| value.value().to_u64())\n\
-                         .and_then(|value| u32::try_from(value).ok())\n\
-                         .filter(|value| *value <= 15);\n\
-                     let Some(event_id) = event_id else {\n\
-                         return input_err!(\n\
-                             loc,\n\
-                             TranslationErr::unsupported(\n\
-                                 \"prof_trigger requires a compile-time constant event ID in 0..=15\".to_owned()\n\
-                             )\n\
-                         );\n\
-                     };\n\
-                     let debug = PmEventOp::build(ctx, event_id);\n\
-                     debug.deref_mut(ctx).set_loc(loc.clone());\n",
-                );
-                writeln!(
-                    output,
-                    "            helpers::set_generated_intrinsic_marker(ctx, debug, {:?});",
-                    intrinsic_marker(catalog, record)
-                )
-                .unwrap();
-                output.push_str(
-                    "            helpers::insert_op(ctx, debug, block_ptr, last_op);\n\
-                     if let Some(target_idx) = target {\n\
-                         Ok(Some(helpers::emit_goto(ctx, *target_idx, debug, block_map, loc)))\n\
-                     } else {\n",
-                );
-                writeln!(
-                    output,
-                    "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-                    format!("{} call without target block", record.rust.name)
-                )
-                .unwrap();
-                output.push_str("            }\n");
-            }
-        }
-        output.push_str("        }\n");
-    }
-    for record in clc_intrinsics(catalog) {
-        let query = !matches!(
-            record.clc.as_ref().unwrap().operation,
-            ClcOperation::TryCancel | ClcOperation::TryCancelMulticast
-        );
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n            require_arity(name, args.len(), 2, &loc)?;\n");
-        output.push_str(
-            "            let (arg0, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n            let (arg1, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-        );
-        let result_types = if query {
-            "vec![pliron::builtin::types::IntegerType::get(ctx, 32, pliron::builtin::types::Signedness::Unsigned).into()]"
-        } else {
-            "vec![]"
-        };
-        writeln!(
-            output,
-            "            let intrinsic = Operation::new(ctx, {}::get_concrete_op_info(), {result_types}, vec![arg0, arg1], vec![], 0);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str("            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n");
-        if query {
-            output.push_str("            let result = intrinsic.deref(ctx).get_result(0);\n");
-            writeln!(
-                output,
-                "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
-                format!("{} call without target block", record.rust.name)
-            )
-            .unwrap();
-        } else {
-            output.push_str("            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, intrinsic, block_map, loc)))\n            } else {\n");
-            writeln!(
-                output,
-                "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-                format!("{} call without target block", record.rust.name)
-            )
-            .unwrap();
-            output.push_str("            }\n");
-        }
-        output.push_str("        }\n");
-    }
-    for record in wgmma_controls(catalog) {
-        let control = record.wgmma_control.as_ref().unwrap();
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        match control.mode {
-            WgmmaControlMode::Fence | WgmmaControlMode::CommitGroup => {
-                output.push_str("            require_arity(name, args.len(), 0, &loc)?;\n");
-                writeln!(
-                    output,
-                    "            let control = {}::build(ctx);",
-                    record.dialect.op_type
-                )
-                .unwrap();
-                output.push_str("            control.deref_mut(ctx).set_loc(loc.clone());\n");
-                writeln!(
-                    output,
-                    "            helpers::set_generated_intrinsic_marker(ctx, control, {:?});",
-                    intrinsic_marker(catalog, record)
-                )
-                .unwrap();
-                output.push_str(
-                    "            helpers::insert_op(ctx, control, block_ptr, prev_op);\n",
-                );
-            }
-            WgmmaControlMode::WaitGroup => {
-                output.push_str(
-                    "            require_arity(name, args.len(), 1, &loc)?;\n\
-                     if !matches!(&args[0], mir::Operand::Constant(_)) {\n\
-                         return input_err!(\n\
-                             loc,\n\
-                             TranslationErr::unsupported(\n\
-                                 \"wgmma_wait_group requires a compile-time constant\".to_owned()\n\
-                             )\n\
-                         );\n\
-                     }\n\
-                     let (max_pending, last_op) = rvalue::translate_operand(\n\
-                         ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
-                     )?;\n\
-                     if max_pending\n\
-                         .defining_op()\n\
-                         .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))\n\
-                         .is_none()\n\
-                     {\n\
-                         return input_err!(\n\
-                             loc,\n\
-                             TranslationErr::unsupported(\n\
-                                 \"wgmma_wait_group requires a compile-time constant\".to_owned()\n\
-                             )\n\
-                         );\n\
-                     }\n\
-                     let control = WgmmaWaitGroupSyncAlignedOp::build(ctx, max_pending);\n\
-                     control.deref_mut(ctx).set_loc(loc.clone());\n",
-                );
-                writeln!(
-                    output,
-                    "            helpers::set_generated_intrinsic_marker(ctx, control, {:?});",
-                    intrinsic_marker(catalog, record)
-                )
-                .unwrap();
-                output.push_str(
-                    "            helpers::insert_op(ctx, control, block_ptr, last_op);\n",
-                );
-            }
-        }
-        output.push_str(
-            "            if let Some(target_idx) = target {\n\
-                 Ok(Some(helpers::emit_goto(ctx, *target_idx, control, block_map, loc)))\n\
-             } else {\n",
-        );
-        writeln!(
-            output,
-            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("            }\n        }\n");
-    }
-    for record in cp_async_copies(catalog) {
-        let copy = record.cp_async_copy.as_ref().unwrap();
-        let dynamic = copy.source_size == CpAsyncSourceSize::Runtime;
-        let arity = if dynamic { 3 } else { 2 };
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        writeln!(
-            output,
-            "            require_arity(name, args.len(), {arity}, &loc)?;"
-        )
-        .unwrap();
-        output.push_str(
-            "            let (shared_dst, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-        );
-        output.push_str(
-            "            let (global_src, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-        );
-        if dynamic {
-            output.push_str(
-                "            let (source_size, last_op) = rvalue::translate_operand(\n                ctx, body, &args[2], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
-            );
-            writeln!(
-                output,
-                "            let copy = {}::build(ctx, shared_dst, global_src, source_size);",
-                record.dialect.op_type
-            )
-            .unwrap();
-        } else {
-            writeln!(
-                output,
-                "            let copy = {}::build(ctx, shared_dst, global_src);",
-                record.dialect.op_type
-            )
-            .unwrap();
-        }
-        output.push_str("            copy.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, copy, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, copy, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, copy, block_map, loc)))\n            } else {\n",
-        );
-        writeln!(
-            output,
-            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("            }\n        }\n");
-    }
-    for record in cp_async_controls(catalog) {
-        let control = record.cp_async_control.as_ref().unwrap();
-        let has_immediate = control.operation == CpAsyncControlOperation::WaitGroup;
-        let arity = usize::from(has_immediate);
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        writeln!(
-            output,
-            "            require_arity(name, args.len(), {arity}, &loc)?;"
-        )
-        .unwrap();
-        if has_immediate {
-            output.push_str(
-                "            if !matches!(&args[0], mir::Operand::Constant(_)) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"cp_async_wait_group requires a compile-time constant max_pending value\".to_owned()\n                    )\n                );\n            }\n",
-            );
-            output.push_str(
-                "            let (max_pending, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-            );
-            writeln!(
-                output,
-                "            let control = {}::build(ctx, max_pending);",
-                record.dialect.op_type
-            )
-            .unwrap();
-        } else {
-            output.push_str("            let last_op = prev_op;\n");
-            writeln!(
-                output,
-                "            let control = {}::build(ctx);",
-                record.dialect.op_type
-            )
-            .unwrap();
-        }
-        output.push_str("            control.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, control, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, control, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, control, block_map, loc)))\n            } else {\n",
-        );
-        writeln!(
-            output,
-            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("            }\n        }\n");
-    }
-    for record in cp_async_mbarriers(catalog) {
-        debug_assert_eq!(
-            record.cp_async_mbarrier.as_ref().unwrap().adapter,
-            CpAsyncMbarrierAdapter::PointerToVoid
-        );
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 1, &loc)?;\n");
-        output.push_str(
-            "            let (barrier, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
-        );
-        writeln!(
-            output,
-            "            let bridge = {}::build(ctx, barrier);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            bridge.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, bridge, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, bridge, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, bridge, block_map, loc)))\n            } else {\n",
-        );
-        writeln!(
-            output,
-            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("            }\n        }\n");
-    }
-    for record in mbarrier_basics(catalog) {
-        let mbarrier = record.mbarrier_basic.as_ref().unwrap();
-        let (argument_names, returns_value) = match mbarrier.operation {
-            MbarrierBasicOperation::Init => {
-                debug_assert_eq!(
-                    mbarrier.adapter,
-                    MbarrierBasicAdapter::InitPointerCountToVoid
-                );
-                (&["barrier", "expected_count"][..], false)
-            }
-            MbarrierBasicOperation::Arrive => {
-                debug_assert_eq!(mbarrier.adapter, MbarrierBasicAdapter::ArrivePointerToToken);
-                (&["barrier"][..], true)
-            }
-            MbarrierBasicOperation::TestWait => {
-                debug_assert_eq!(
-                    mbarrier.adapter,
-                    MbarrierBasicAdapter::TestWaitPointerTokenToPredicate
-                );
-                (&["barrier", "token"][..], true)
-            }
-            MbarrierBasicOperation::Inval => {
-                debug_assert_eq!(mbarrier.adapter, MbarrierBasicAdapter::InvalPointerToVoid);
-                (&["barrier"][..], false)
-            }
-        };
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        writeln!(
-            output,
-            "            require_arity(name, args.len(), {}, &loc)?;",
-            argument_names.len()
-        )
-        .unwrap();
-        for (index, argument_name) in argument_names.iter().enumerate() {
-            let previous = if index == 0 { "prev_op" } else { "last_op" };
-            writeln!(
-                output,
-                "            let ({argument_name}, last_op) = rvalue::translate_operand(\n                ctx, body, &args[{index}], value_map, block_ptr, {previous}, loc.clone(),\n            )?;"
-            )
-            .unwrap();
-        }
-        writeln!(
-            output,
-            "            let mbarrier = {}::build(ctx, {});",
-            record.dialect.op_type,
-            argument_names.join(", ")
-        )
-        .unwrap();
-        output.push_str("            mbarrier.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, mbarrier, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str("            helpers::insert_op(ctx, mbarrier, block_ptr, last_op);\n");
-        if returns_value {
-            output.push_str("            let result = mbarrier.deref(ctx).get_result(0);\n");
-            writeln!(
-                output,
-                "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, mbarrier, value_map, block_map, loc,\n                {:?},\n            )?))",
-                format!("{} call without target block", record.rust.name)
-            )
-            .unwrap();
-        } else {
-            output.push_str(
-                "            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, mbarrier, block_map, loc)))\n            } else {\n",
-            );
-            writeln!(
-                output,
-                "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-                format!("{} call without target block", record.rust.name)
-            )
-            .unwrap();
-            output.push_str("            }\n");
-        }
-        output.push_str("        }\n");
-    }
-    for record in mbarrier_extended(catalog) {
-        let contract = record.mbarrier_extended.as_ref().unwrap();
-        let (arguments, returns_value): (Vec<(usize, &str)>, bool) = match contract.adapter {
-            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount => {
-                (vec![(0, "barrier"), (2, "bytes")], true)
-            }
-            MbarrierExtendedAdapter::RawClusterAddressToVoid => (vec![(0, "address")], false),
-            MbarrierExtendedAdapter::PointerTokenToPredicate => {
-                (vec![(0, "barrier"), (1, "token")], true)
-            }
-            MbarrierExtendedAdapter::PointerParityToPredicate => {
-                (vec![(0, "barrier"), (1, "parity")], true)
-            }
-            MbarrierExtendedAdapter::ZeroOperandsToVoid => (vec![], false),
-            MbarrierExtendedAdapter::NanosecondsToVoid => (vec![(0, "ns")], false),
-        };
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        writeln!(
-            output,
-            "            require_arity(name, args.len(), {}, &loc)?;",
-            record.rust.arguments.len()
-        )
-        .unwrap();
-        if arguments.is_empty() {
-            output.push_str("            let last_op = prev_op;\n");
-        }
-        for (position, (argument_index, argument_name)) in arguments.iter().enumerate() {
-            let previous = if position == 0 { "prev_op" } else { "last_op" };
-            writeln!(
-                output,
-                "            let ({argument_name}, last_op) = rvalue::translate_operand(\n                ctx, body, &args[{argument_index}], value_map, block_ptr, {previous}, loc.clone(),\n            )?;"
-            )
-            .unwrap();
-        }
-        let build_arguments = arguments
-            .iter()
-            .map(|(_, name)| *name)
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(
-            output,
-            "            let extended = {}::build(ctx{}{});",
-            record.dialect.op_type,
-            if build_arguments.is_empty() { "" } else { ", " },
-            build_arguments,
-        )
-        .unwrap();
-        output.push_str("            extended.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, extended, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str("            helpers::insert_op(ctx, extended, block_ptr, last_op);\n");
-        if returns_value {
-            output.push_str("            let result = extended.deref(ctx).get_result(0);\n");
-            writeln!(
-                output,
-                "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, extended, value_map, block_map, loc,\n                {:?},\n            )?))",
-                format!("{} call without target block", record.rust.name)
-            )
-            .unwrap();
-        } else {
-            output.push_str(
-                "            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, extended, block_map, loc)))\n            } else {\n",
-            );
-            writeln!(
-                output,
-                "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-                format!("{} call without target block", record.rust.name)
-            )
-            .unwrap();
-            output.push_str("            }\n");
-        }
-        output.push_str("        }\n");
-    }
-    for record in sync_intrinsics(catalog) {
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        output.push_str("            require_arity(name, args.len(), 0, &loc)?;\n");
-        writeln!(
-            output,
-            "            let barrier = Operation::new(ctx, {}::get_concrete_op_info(), vec![], vec![], vec![], 0);",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str("            barrier.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, barrier, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, barrier, block_ptr, prev_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, barrier, block_map, loc)))\n            } else {\n",
-        );
-        writeln!(
-            output,
-            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("            }\n        }\n");
-    }
-    for record in execution_controls(catalog) {
-        let operation = ExecutionControlOperation::from_catalog_id(&record.id)
-            .expect("closed execution-control record");
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        writeln!(
-            output,
-            "            require_arity(name, args.len(), {}, &loc)?;",
-            operation.operand_count()
-        )
-        .unwrap();
-        if operation.requires_immediate_operands() {
-            output.push_str(
-                "            if !matches!(&args[0], mir::Operand::Constant(_)) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"setmaxnreg requires a compile-time register count in 24..=256 divisible by 8\".to_owned()\n                    )\n                );\n            }\n            let (register_count_value, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n            let register_count = register_count_value\n                .defining_op()\n                .and_then(|defining_op| Operation::get_op::<MirConstantOp>(defining_op, ctx))\n                .and_then(|constant| constant.get_attr_value(ctx))\n                .map(|value| value.value().to_u64())\n                .and_then(|value| u32::try_from(value).ok())\n                .filter(|value| (24..=256).contains(value) && value % 8 == 0);\n            let Some(register_count) = register_count else {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"setmaxnreg requires a compile-time register count in 24..=256 divisible by 8\".to_owned()\n                    )\n                );\n            };\n",
-            );
-            writeln!(
-                output,
-                "            let control = {}::build(ctx, register_count);",
-                record.dialect.op_type
-            )
-            .unwrap();
-        } else if operation.operand_count() == 0 {
-            output.push_str("            let last_op = prev_op;\n");
-            writeln!(
-                output,
-                "            let control = Operation::new(ctx, {}::get_concrete_op_info(), vec![], vec![], vec![], 0);",
-                record.dialect.op_type
-            )
-            .unwrap();
-        } else {
-            output.push_str(
-                "            let mut last_op = prev_op;\n            let mut operands = Vec::with_capacity(args.len());\n            for arg in args {\n                let (value, translated) = rvalue::translate_operand(\n                    ctx, body, arg, value_map, block_ptr, last_op, loc.clone(),\n                )?;\n                last_op = translated;\n                operands.push(value);\n            }\n",
-            );
-            writeln!(
-                output,
-                "            let control = Operation::new(ctx, {}::get_concrete_op_info(), vec![], operands, vec![], 0);",
-                record.dialect.op_type
-            )
-            .unwrap();
-        }
-        output.push_str("            control.deref_mut(ctx).set_loc(loc.clone());\n");
-        writeln!(
-            output,
-            "            helpers::set_generated_intrinsic_marker(ctx, control, {:?});",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        output.push_str(
-            "            helpers::insert_op(ctx, control, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, control, block_map, loc)))\n            } else {\n",
-        );
-        writeln!(
-            output,
-            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-            format!("{} call without target block", record.rust.name)
-        )
-        .unwrap();
-        output.push_str("            }\n        }\n");
-    }
-    for record in tma_intrinsics(catalog) {
-        let operation = record.tma.as_ref().unwrap().operation;
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        if matches!(
-            operation,
-            TmaOperation::WaitGroup | TmaOperation::WaitGroupRead
-        ) {
-            output.push_str(
-                "            require_arity(name, args.len(), 1, &loc)?;\n            if !matches!(args.first(), Some(mir::Operand::Constant(_))) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"TMA wait-group count must be a compile-time constant\".to_owned()\n                    )\n                );\n            }\n",
-            );
-        }
-        let marker = intrinsic_marker(catalog, record);
-        match operation {
-            TmaOperation::G2sTile1d
-            | TmaOperation::G2sTile2d
-            | TmaOperation::G2sTile3d
-            | TmaOperation::G2sTile4d
-            | TmaOperation::G2sTile5d => {
-                writeln!(
-                    output,
-                    "            Ok(Some(super::tma::emit_tma_g2s(\n                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, {}, {marker:?},\n            )?))",
-                    operation.dimensions().unwrap()
-                )
-                .unwrap();
-            }
-            TmaOperation::G2sTile2dMulticast => {
-                writeln!(
-                    output,
-                    "            Ok(Some(super::tma::emit_tma_g2s_multicast(\n                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, {marker:?},\n            )?))"
-                )
-                .unwrap();
-            }
-            TmaOperation::G2sTile2dMulticastCg2 => {
-                writeln!(
-                    output,
-                    "            Ok(Some(super::tma::emit_tma_g2s_multicast_cg2(\n                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, {marker:?},\n            )?))"
-                )
-                .unwrap();
-            }
-            TmaOperation::S2gTile1d
-            | TmaOperation::S2gTile2d
-            | TmaOperation::S2gTile3d
-            | TmaOperation::S2gTile4d
-            | TmaOperation::S2gTile5d => {
-                writeln!(
-                    output,
-                    "            Ok(Some(super::tma::emit_tma_s2g(\n                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, {}, {marker:?},\n            )?))",
-                    operation.dimensions().unwrap()
-                )
-                .unwrap();
-            }
-            TmaOperation::CommitGroup => {
-                writeln!(
-                    output,
-                    "            Ok(Some(super::tma::emit_tma_commit_group(\n                ctx, args, target, block_ptr, prev_op, block_map, loc, {marker:?},\n            )?))"
-                )
-                .unwrap();
-            }
-            TmaOperation::WaitGroup | TmaOperation::WaitGroupRead => {
-                writeln!(
-                    output,
-                    "            Ok(Some(super::tma::emit_tma_wait_group(\n                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, {}, {marker:?},\n            )?))",
-                    operation == TmaOperation::WaitGroupRead
-                )
-                .unwrap();
-            }
-            _ => {
-                let arity = record.dialect.operands.len();
-                writeln!(
-                    output,
-                    "            require_arity(name, args.len(), {arity}, &loc)?;"
-                )
-                .unwrap();
-                if matches!(
-                    record.tma.as_ref().unwrap().adapter,
-                    TmaAdapter::DescriptorOrdinalAndU32
-                        | TmaAdapter::DescriptorOrdinalAndU64
-                        | TmaAdapter::DescriptorAndImmediateU32
-                ) {
-                    output.push_str(
-                        "            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"tensor-map replacement selector must be a compile-time constant\".to_owned()\n                    )\n                );\n            }\n",
-                    );
-                }
-                output.push_str(
-                    "            let mut last_op = prev_op;\n            let mut operands = Vec::with_capacity(args.len());\n            for arg in args {\n                let (value, translated) = rvalue::translate_operand(\n                    ctx, body, arg, value_map, block_ptr, last_op, loc.clone(),\n                )?;\n                last_op = translated;\n                operands.push(value);\n            }\n",
-                );
-                writeln!(
-                    output,
-                    "            let intrinsic = Operation::new(ctx, dialect_nvvm::ops::{}::get_concrete_op_info(), vec![], operands, vec![], 0);",
-                    record.dialect.op_type
-                )
-                .unwrap();
-                output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
-                writeln!(
-                    output,
-                    "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {marker:?});"
-                )
-                .unwrap();
-                output.push_str(
-                    "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, intrinsic, block_map, loc)))\n            } else {\n",
-                );
-                writeln!(
-                    output,
-                    "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-                    format!("{} call without target block", record.rust.name)
-                )
-                .unwrap();
-                output.push_str("            }\n");
-            }
-        }
-        output.push_str("        }\n");
-    }
-    for record in tcgen05_intrinsics(catalog) {
-        let tcgen05 = record.tcgen05.as_ref().unwrap();
-        if tcgen05.mma.is_some() {
-            render_importer_tcgen05_mma_dispatch(&mut output, catalog, record);
-            continue;
-        }
-        let operation = tcgen05.operation;
-        let has_half_split_offset = tcgen05
-            .ld
-            .is_some_and(|ld| ld.shape == Tcgen05LdShape::M16x32bx2)
-            || tcgen05
-                .st
-                .is_some_and(|st| st.shape == Tcgen05LdShape::M16x32bx2);
-        let mut path_refs = vec![record.rust.canonical_path.as_str()];
-        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
-        output.push_str("        ");
-        render_inline_patterns(&mut output, &path_refs);
-        output.push_str(" => {\n");
-        if operation == Tcgen05Operation::St {
-            let count = tcgen05_st_register_count(record);
-            writeln!(
-                output,
-                "            require_arity(name, args.len(), {}, &loc)?;",
-                if has_half_split_offset { 3 } else { 2 }
-            )
-            .unwrap();
-            if has_half_split_offset {
-                output.push_str(
-                    "            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"tcgen05 16x32bx2 half-split offset must be a compile-time constant\".to_owned()\n                    )\n                );\n            }\n",
-                );
-            }
-            writeln!(
-                output,
-                "            let (operands, last_op) = import_generated_tcgen05_store_operands(\n                ctx, body, args, {count}, {has_half_split_offset}, block_ptr, prev_op, value_map, loc.clone(),\n            )?;"
-            )
-            .unwrap();
-            writeln!(
-                output,
-                "            let intrinsic = Operation::new(ctx, {}::get_concrete_op_info(), vec![], operands, vec![], 0);",
-                record.dialect.op_type
-            )
-            .unwrap();
-            output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
-            writeln!(
-                output,
-                "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
-                intrinsic_marker(catalog, record)
-            )
-            .unwrap();
-            output.push_str(
-                "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, intrinsic, block_map, loc)))\n            } else {\n",
-            );
-            writeln!(
-                output,
-                "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-                format!("{} call without target block", record.rust.name)
-            )
-            .unwrap();
-            output.push_str("            }\n        }\n");
-            continue;
-        }
-        let arity = record.dialect.operands.len();
-        writeln!(
-            output,
-            "            require_arity(name, args.len(), {arity}, &loc)?;"
-        )
-        .unwrap();
-        if has_half_split_offset {
-            output.push_str(
-                "            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"tcgen05 16x32bx2 half-split offset must be a compile-time constant\".to_owned()\n                    )\n                );\n            }\n",
-            );
-        }
-        output.push_str(
-            "            let mut last_op = prev_op;\n            let mut operands = Vec::with_capacity(args.len());\n            for arg in args {\n                let (value, translated) = rvalue::translate_operand(\n                    ctx, body, arg, value_map, block_ptr, last_op, loc.clone(),\n                )?;\n                last_op = translated;\n                operands.push(value);\n            }\n",
-        );
-        if has_half_split_offset {
-            output.push_str(
-                "            if operands.get(1).and_then(|value| value.defining_op()).and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx)).is_none() {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"tcgen05 16x32bx2 half-split offset must lower to a constant\".to_owned()\n                    )\n                );\n            }\n",
-            );
-        }
-        let load = match operation {
-            Tcgen05Operation::Ld16x256bX8Pure => Some((32, "FP32Type::get(ctx).into()")),
-            Tcgen05Operation::Ld16x256bPure => Some((4, "FP32Type::get(ctx).into()")),
-            Tcgen05Operation::Ld => Some((
-                tcgen05_ld_register_count(record),
-                "IntegerType::get(ctx, 32, Signedness::Unsigned).into()",
-            )),
-            _ => None,
-        };
-        if let Some((count, result_ty)) = load {
-            writeln!(
-                output,
-                "            let result_ty: TypeHandle = {result_ty};"
-            )
-            .unwrap();
-            writeln!(
-                output,
-                "            let result_types = (0..{count}).map(|_| result_ty).collect();"
-            )
-            .unwrap();
-            writeln!(
-                    output,
-                    "            let intrinsic = Operation::new(ctx, {}::get_concrete_op_info(), result_types, operands, vec![], 0);",
-                    record.dialect.op_type
-                )
-                .unwrap();
-            output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
-            writeln!(
-                output,
-                "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
-                intrinsic_marker(catalog, record)
-            )
-            .unwrap();
-            output
-                .push_str("            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n");
-            if count == 1 {
-                output.push_str(
-                        "            let result = intrinsic.deref(ctx).get_result(0);\n            let value = intrinsic;\n",
-                    );
-            } else {
-                writeln!(
-                        output,
-                        "            let results: Vec<Value> = (0..{count}).map(|index| intrinsic.deref(ctx).get_result(index)).collect();"
-                    )
-                    .unwrap();
-                writeln!(
-                    output,
-                    "            let array_ty = MirArrayType::get(ctx, result_ty, {count});"
-                )
-                .unwrap();
-                output.push_str(
-                        "            let array = Operation::new(ctx, MirConstructArrayOp::get_concrete_op_info(), vec![array_ty.into()], results, vec![], 0);\n            array.deref_mut(ctx).set_loc(loc.clone());\n            array.insert_after(ctx, intrinsic);\n            let destination_rust_ty = match destination.ty(body.locals()) {\n                Ok(ty) => ty,\n                Err(error) => {\n                    return input_err!(\n                        loc,\n                        TranslationErr::unsupported(format!(\n                            \"failed to resolve destination type for intrinsic result: {error:?}\"\n                        ))\n                    );\n                }\n            };\n            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;\n            let array_result = array.deref(ctx).get_result(0);\n            let (result, value) = if destination_ty == array_result.get_type(ctx) {\n                (array_result, array)\n            } else {\n                let value = Operation::new(ctx, MirConstructStructOp::get_concrete_op_info(), vec![destination_ty], vec![array_result], vec![], 0);\n                value.deref_mut(ctx).set_loc(loc.clone());\n                value.insert_after(ctx, array);\n                (value.deref(ctx).get_result(0), value)\n            };\n            helpers::set_compiler_result_bundle_marker(ctx, value);\n",
-                    );
-            }
-            writeln!(
-                    output,
-                    "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, value, value_map, block_map, loc,\n                {:?},\n            )?))",
-                    format!("{} call without target block", record.rust.name)
-                )
-                .unwrap();
-        } else {
-            writeln!(
-                    output,
-                    "            let intrinsic = Operation::new(ctx, {}::get_concrete_op_info(), vec![], operands, vec![], 0);",
-                    record.dialect.op_type
-                )
-                .unwrap();
-            output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
-            writeln!(
-                output,
-                "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
-                intrinsic_marker(catalog, record)
-            )
-            .unwrap();
-            output.push_str(
-                    "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, intrinsic, block_map, loc)))\n            } else {\n",
-                );
-            writeln!(
-                output,
-                "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
-                format!("{} call without target block", record.rust.name)
-            )
-            .unwrap();
-            output.push_str("            }\n");
-        }
-        output.push_str("        }\n");
-    }
-    output.push_str("        _ => Ok(None),\n    }\n}\n\n");
-    output.push_str(
-        "fn require_arity(\n    name: &str,\n    actual: usize,\n    expected: usize,\n    loc: &Location,\n) -> TranslationResult<()> {\n    if actual != expected {\n        return input_err!(\n            loc.clone(),\n            TranslationErr::unsupported(format!(\n                \"generated intrinsic `{name}` expects {expected} arguments, got {actual}\"\n            ))\n        );\n    }\n    Ok(())\n}\n",
-    );
-    if tcgen05_mma_intrinsics(catalog).next().is_some() {
-        output.push_str(
-            r#"
-
-fn generated_tcgen05_mma_selector(operand: Option<&mir::Operand>) -> Option<u32> {
-    use rustc_public::ty::{ConstantKind, TyConstKind};
-    let mir::Operand::Constant(constant) = operand? else { return None; };
-    let value: u128 = match constant.const_.kind() {
-        ConstantKind::Allocated(alloc) => alloc.read_uint().ok()?,
-        ConstantKind::Ty(value) => match value.kind() {
-            TyConstKind::Value(_, alloc) => alloc.read_uint().ok()?,
-            _ => value.eval_target_usize().ok()? as u128,
-        },
-        ConstantKind::Unevaluated(_) | ConstantKind::Param(_) => return None,
-        ConstantKind::ZeroSized => return None,
-    };
-    u32::try_from(value).ok()
-}
-"#,
-        );
-    }
-    if tcgen05_intrinsics(catalog)
-        .any(|record| record.tcgen05.as_ref().unwrap().operation == Tcgen05Operation::St)
-    {
-        output.push_str(
-            r#"
-
-#[allow(clippy::too_many_arguments)]
-fn import_generated_tcgen05_store_operands(
-    ctx: &mut Context,
-    body: &mir::Body,
-    args: &[mir::Operand],
-    expected_len: usize,
-    has_half_split_offset: bool,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    value_map: &mut ValueMap,
-    loc: Location,
-) -> TranslationResult<(Vec<Value>, Option<Ptr<Operation>>)> {
-    let expected_arity = if has_half_split_offset { 3 } else { 2 };
-    if args.len() != expected_arity || !(1..=128).contains(&expected_len) {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(
-                "generated tcgen05 store has an invalid address, offset, or register count".to_owned()
-            )
-        );
-    }
-    let u32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-    let (address, last_op) = rvalue::translate_operand(
-        ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),
-    )?;
-    let (half_split_offset, last_op) = if has_half_split_offset {
-        let (offset, translated) = rvalue::translate_operand(
-            ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),
-        )?;
-        if offset
-            .defining_op()
-            .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-            .is_none()
-        {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(
-                    "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                )
-            );
-        }
-        (Some(offset), translated)
-    } else {
-        (None, last_op)
-    };
-    let data_index = if has_half_split_offset { 2 } else { 1 };
-    let (data, mut last_op) = rvalue::translate_operand(
-        ctx, body, &args[data_index], value_map, block_ptr, last_op, loc.clone(),
-    )?;
-    if expected_len == 1 {
-        if data.get_type(ctx) != u32_ty {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(
-                    "generated tcgen05 store data must be a u32 register".to_owned()
-                )
-            );
-        }
-        let mut operands = vec![address];
-        operands.extend(half_split_offset);
-        operands.push(data);
-        return Ok((operands, last_op));
-    }
-
-    let data_ty = data.get_type(ctx);
-    let direct_array = data_ty
-        .deref(ctx)
-        .downcast_ref::<MirArrayType>()
-        .is_some_and(|array| {
-            array.size() == expected_len as u64 && array.element_type() == u32_ty
-        });
-    let array = if direct_array {
-        data
-    } else {
-        let wrapped_array_ty = data_ty
-            .deref(ctx)
-            .downcast_ref::<MirStructType>()
-            .filter(|structure| structure.field_count() == 1)
-            .and_then(|structure| structure.get_field_type(0));
-        let valid_wrapper = wrapped_array_ty.is_some_and(|field_ty| {
-            field_ty
-                .deref(ctx)
-                .downcast_ref::<MirArrayType>()
-                .is_some_and(|array| {
-                    array.size() == expected_len as u64 && array.element_type() == u32_ty
-                })
-        });
-        if !valid_wrapper {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "generated tcgen05 store data must contain {expected_len} u32 registers"
-                ))
-            );
-        }
-        let array_ty = wrapped_array_ty.expect("validated tcgen05 store wrapper");
-        let extract = Operation::new(
-            ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![array_ty],
-            vec![data],
-            vec![],
-            0,
-        );
-        extract.deref_mut(ctx).set_loc(loc.clone());
-        let extract = MirExtractFieldOp::new(extract);
-        extract.set_attr_index(ctx, FieldIndexAttr(0));
-        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
-        last_op = Some(extract.get_operation());
-        extract.get_operation().deref(ctx).get_result(0)
-    };
-
-    let mut operands = Vec::with_capacity(expected_len + 1 + usize::from(has_half_split_offset));
-    operands.push(address);
-    operands.extend(half_split_offset);
-    for index in 0..expected_len {
-        let extract = Operation::new(
-            ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![u32_ty],
-            vec![array],
-            vec![],
-            0,
-        );
-        extract.deref_mut(ctx).set_loc(loc.clone());
-        let extract = MirExtractFieldOp::new(extract);
-        extract.set_attr_index(ctx, FieldIndexAttr(index as u32));
-        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
-        last_op = Some(extract.get_operation());
-        operands.push(extract.get_operation().deref(ctx).get_result(0));
-    }
-    Ok((operands, last_op))
-}
-"#,
-        );
-    }
-    if register_mmas(catalog).next().is_some() || sparse_mmas(catalog).next().is_some() {
-        output.push_str(
-            r#"
-
-#[derive(Clone, Copy)]
-enum GeneratedMmaImportAdapter {
-    C2U32A2U32B1U32ToD2U32,
-    C2U32A4U32B2U32ToD2U32,
-    C2U32A4U32B4U32ToD2U32,
-    C4F32A2U32B1U32ToD4F32,
-    C4F32A4U32B2U32ToD4F32,
-    C4F32A4U32B4U32ToD4F32,
-    C2F64A1F64B1F64ToD2F64,
-    C2I32A1U32B1U32ToD2I32,
-    C4I32A4U32B2U32ToD4I32,
-    C4I32A4U32B4U32ToD4I32,
-    C4I32A2U32B1U32ToD4I32,
-    C4I32A2U32B2U32ToD4I32,
-    C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-}
-
-#[allow(clippy::too_many_arguments)]
-fn extract_generated_mma_array(
-    ctx: &mut Context,
-    array: Value,
-    expected_element_ty: TypeHandle,
-    expected_len: usize,
-    block_ptr: Ptr<BasicBlock>,
-    mut last_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Vec<Value>, Ptr<Operation>)> {
-    let valid = array
-        .get_type(ctx)
-        .deref(ctx)
-        .downcast_ref::<MirArrayType>()
-        .is_some_and(|array_ty| {
-            array_ty.size() == expected_len as u64
-                && array_ty.element_type() == expected_element_ty
-        });
-    if !valid {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "generated MMA fragment must be an array of {expected_len} scalar registers"
-            ))
-        );
-    }
-    let mut registers = Vec::with_capacity(expected_len);
-    for index in 0..expected_len {
-        let extract = Operation::new(
-            ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![expected_element_ty],
-            vec![array],
-            vec![],
-            0,
-        );
-        extract.deref_mut(ctx).set_loc(loc.clone());
-        let extract = MirExtractFieldOp::new(extract);
-        extract.set_attr_index(ctx, FieldIndexAttr(index as u32));
-        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
-        last_op = Some(extract.get_operation());
-        registers.push(extract.get_operation().deref(ctx).get_result(0));
-    }
-    Ok((registers, last_op.expect("non-empty generated MMA fragment")))
-}
-
-#[allow(clippy::too_many_arguments)]
-fn import_generated_mma_operands(
-    ctx: &mut Context,
-    body: &mir::Body,
-    args: &[mir::Operand],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    value_map: &mut ValueMap,
-    loc: Location,
-    adapter: GeneratedMmaImportAdapter,
-) -> TranslationResult<(Vec<Value>, Ptr<Operation>, TypeHandle, usize)> {
-    let f32_ty: TypeHandle = FP32Type::get(ctx).into();
-    let f64_ty: TypeHandle = FP64Type::get(ctx).into();
-    let i32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Signed).into();
-    let u32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-    let (c_ty, c_count, a_ty, a_count, a_array, b_ty, b_count, b_array, result_ty, result_count) =
-        match adapter {
-            GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32 =>
-                (u32_ty, 2, u32_ty, 2, true, u32_ty, 1, false, u32_ty, 2),
-            GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32 =>
-                (u32_ty, 2, u32_ty, 4, true, u32_ty, 2, true, u32_ty, 2),
-            GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32 =>
-                (u32_ty, 2, u32_ty, 4, true, u32_ty, 4, true, u32_ty, 2),
-            GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32 =>
-                (f32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, f32_ty, 4),
-            GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32 =>
-                (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4),
-            GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32 =>
-                (f32_ty, 4, u32_ty, 4, true, u32_ty, 4, true, f32_ty, 4),
-            GeneratedMmaImportAdapter::C2F64A1F64B1F64ToD2F64 =>
-                (f64_ty, 2, f64_ty, 1, false, f64_ty, 1, false, f64_ty, 2),
-            GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32 =>
-                (i32_ty, 2, u32_ty, 1, false, u32_ty, 1, false, i32_ty, 2),
-            GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32 =>
-                (i32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, i32_ty, 4),
-            GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32 =>
-                (i32_ty, 4, u32_ty, 4, true, u32_ty, 4, true, i32_ty, 4),
-            GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32 =>
-                (i32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, i32_ty, 4),
-            GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32 =>
-                (i32_ty, 4, u32_ty, 2, true, u32_ty, 2, true, i32_ty, 4),
-            GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 =>
-                (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4),
-        };
-    let (c_array, last_op) = rvalue::translate_operand(
-        ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),
-    )?;
-    let (mut operands, last_op) = extract_generated_mma_array(
-        ctx, c_array, c_ty, c_count, block_ptr, last_op, loc.clone(),
-    )?;
-    let (a_value, last_after_a) = rvalue::translate_operand(
-        ctx, body, &args[1], value_map, block_ptr, Some(last_op), loc.clone(),
-    )?;
-    let (a_registers, last_op) = if a_array {
-        extract_generated_mma_array(
-            ctx, a_value, a_ty, a_count, block_ptr, last_after_a, loc.clone(),
-        )?
-    } else {
-        (vec![a_value], last_after_a.expect("generated MMA A translation keeps predecessor"))
-    };
-    operands.extend(a_registers);
-    let (b_value, last_after_b) = rvalue::translate_operand(
-        ctx, body, &args[2], value_map, block_ptr, Some(last_op), loc.clone(),
-    )?;
-    let (b_registers, last_op) = if b_array {
-        extract_generated_mma_array(
-            ctx, b_value, b_ty, b_count, block_ptr, last_after_b, loc.clone(),
-        )?
-    } else {
-        (vec![b_value], last_after_b.expect("generated MMA B translation keeps predecessor"))
-    };
-    operands.extend(b_registers);
-    let mut last_op = last_op;
-    if matches!(
-        adapter,
-        GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
-    ) {
-        for arg in &args[3..] {
-            let (value, translated) = rvalue::translate_operand(
-                ctx,
-                body,
-                arg,
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            last_op = translated.expect("generated block-scale MMA operand translation keeps predecessor");
-            operands.push(value);
-        }
-    }
-    Ok((operands, last_op, result_ty, result_count))
-}
-
-fn bundle_generated_mma_results(
-    ctx: &mut Context,
-    mma: Ptr<Operation>,
-    result_ty: TypeHandle,
-    result_count: usize,
-    loc: Location,
-) -> (Value, Ptr<Operation>) {
-    let results = (0..result_count)
-        .map(|index| mma.deref(ctx).get_result(index))
-        .collect();
-    let array_ty = MirArrayType::get(ctx, result_ty, result_count as u64);
-    let array = Operation::new(
-        ctx,
-        MirConstructArrayOp::get_concrete_op_info(),
-        vec![array_ty.into()],
-        results,
-        vec![],
-        0,
-    );
-    array.deref_mut(ctx).set_loc(loc);
-    array.insert_after(ctx, mma);
-    (array.deref(ctx).get_result(0), array)
-}
-"#,
-        );
-    }
-    output.push_str("\n#[cfg(test)]\nmod tests {\n    use super::*;\n\n");
-    for record in &catalog.intrinsics {
-        writeln!(
-            output,
-            "    #[test]\n    fn {}_uses_only_canonical_or_compatibility_defpaths() {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "        assert!(is_generated_intrinsic_path({:?}));",
-            record.rust.canonical_path
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "        assert!(is_raw_generated_intrinsic_path({:?}));",
-            record.rust.canonical_path
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "        assert_eq!(generated_intrinsic_marker({:?}), Some({:?}));",
-            record.rust.canonical_path,
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "        assert!(matches!(classify_raw_intrinsic_path(\"cuda_intrinsics\", {:?}.into()), RawIntrinsicIdentity::Known(_)));",
-            record.rust.canonical_path
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "        assert!(!is_generated_intrinsic_path({:?}));",
-            record.rust.public_path
-        )
-        .unwrap();
-        for compatibility_path in &record.rust.compatibility_paths {
-            writeln!(
-                output,
-                "        assert!(is_generated_intrinsic_path({compatibility_path:?}));\n        assert!(!is_raw_generated_intrinsic_path({compatibility_path:?}));\n        assert_eq!(generated_intrinsic_marker({compatibility_path:?}), Some({:?}));",
-                intrinsic_marker(catalog, record)
-            )
-            .unwrap();
-        }
-        writeln!(
-            output,
-            "        assert!(!is_generated_intrinsic_path(\"cuda_intrinsics::__cuda_oxide_intrinsic_abi_v{}::{}\"));",
-            catalog.intrinsic_abi + 1,
-            record.rust.abi_id
-        )
-        .unwrap();
-        output.push_str("    }\n");
-    }
-    output.push_str(
-        "\n    #[test]\n    fn raw_intrinsic_identity_classification_fails_closed() {\n        assert_eq!(\n            classify_raw_intrinsic_path(\"serde\", \"serde::helper\".into()),\n            RawIntrinsicIdentity::NotRawCrate\n        );\n        assert!(matches!(\n            classify_raw_intrinsic_path(\"cuda_intrinsics\", \"cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0001\".into()),\n            RawIntrinsicIdentity::UnsupportedAbi(_)\n        ));\n        assert!(matches!(\n            classify_raw_intrinsic_path(\"cuda_intrinsics\", \"cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i9999\".into()),\n            RawIntrinsicIdentity::UnknownId(_)\n        ));\n        assert!(matches!(\n            classify_raw_intrinsic_path(\"cuda_intrinsics\", \"cuda_intrinsics::helper\".into()),\n            RawIntrinsicIdentity::UnknownId(_)\n        ));\n    }\n",
-    );
-    output.push_str("}\n");
-    output
-}
-
-fn special_register_ptx_type(record: &CatalogIntrinsic) -> &'static str {
-    match record
-        .special_register
-        .as_ref()
-        .expect("special-register record")
-        .ptx_type
-    {
-        SpecialRegisterPtxType::B32 => "b32",
-        SpecialRegisterPtxType::U32 => "u32",
-        SpecialRegisterPtxType::U64 => "u64",
-    }
-}
-
-fn special_register_output_constraint(record: &CatalogIntrinsic) -> &'static str {
-    match record
-        .special_register
-        .as_ref()
-        .expect("special-register record")
-        .output_constraint
-    {
-        SpecialRegisterOutputConstraint::Register32 => "=r",
-        SpecialRegisterOutputConstraint::Register64 => "=l",
-    }
-}
-
-fn special_register_inline_template(record: &CatalogIntrinsic) -> String {
-    let register = match record.expected_ptx.operands.as_slice() {
-        [_, crate::ptx::OperandPattern::Exact { value }] => value,
-        _ => unreachable!("closed special-register PTX operands"),
-    };
-    format!("mov.{} $0, {register};", special_register_ptx_type(record))
-}
-
-fn special_register_asm_kind(record: &CatalogIntrinsic) -> &'static str {
-    match record
-        .special_register
-        .as_ref()
-        .expect("special-register record")
-        .observation
-    {
-        SpecialRegisterObservation::StablePure => "AsmKind::Pure",
-        SpecialRegisterObservation::VolatileObservation => "AsmKind::SideEffect",
-    }
-}
-
-fn special_register_backend_mechanism(
-    record: &CatalogIntrinsic,
-    backend: IntrinsicBackend,
-) -> BackendLoweringMechanism {
-    record
-        .backend_lowerings
-        .iter()
-        .find(|route| route.backend == backend)
-        .expect("special-register backend route")
-        .mechanism
-}
-
-fn tcgen05_inline_asm(record: &CatalogIntrinsic) -> (String, String, Option<usize>) {
-    let operation = record.tcgen05.as_ref().expect("tcgen05 contract").operation;
-    match operation {
-        Tcgen05Operation::Alloc | Tcgen05Operation::AllocCg2 => {
-            let group = if operation == Tcgen05Operation::AllocCg2 { 2 } else { 1 };
-            (
-                format!("{{ .reg .u64 %shared64; .reg .u32 %shared32; cvta.to.shared.u64 %shared64, $0; cvt.u32.u64 %shared32, %shared64; tcgen05.alloc.cta_group::{group}.sync.aligned.shared::cta.b32 [%shared32], $1; }}"),
-                "l,r,~{memory}".into(),
-                None,
-            )
-        }
-        Tcgen05Operation::Dealloc | Tcgen05Operation::DeallocCg2 => {
-            let group = if operation == Tcgen05Operation::DeallocCg2 { 2 } else { 1 };
-            (
-                format!("tcgen05.dealloc.cta_group::{group}.sync.aligned.b32 $0, $1;"),
-                "r,r,~{memory}".into(),
-                None,
-            )
-        }
-        Tcgen05Operation::RelinquishAllocPermit
-        | Tcgen05Operation::RelinquishAllocPermitCg2 => {
-            let group = if operation == Tcgen05Operation::RelinquishAllocPermitCg2 {
-                2
-            } else {
-                1
-            };
-            (
-                format!("tcgen05.relinquish_alloc_permit.cta_group::{group}.sync.aligned;"),
-                "~{memory}".into(),
-                None,
-            )
-        }
-        Tcgen05Operation::FenceBeforeThreadSync => (
-            "tcgen05.fence::before_thread_sync;".into(),
-            "~{memory}".into(),
-            None,
-        ),
-        Tcgen05Operation::FenceAfterThreadSync => (
-            "tcgen05.fence::after_thread_sync;".into(),
-            "~{memory}".into(),
-            None,
-        ),
-        Tcgen05Operation::Commit
-        | Tcgen05Operation::CommitSharedCluster
-        | Tcgen05Operation::CommitCg2
-        | Tcgen05Operation::CommitSharedClusterCg2 => {
-            let group = if matches!(
-                operation,
-                Tcgen05Operation::CommitCg2 | Tcgen05Operation::CommitSharedClusterCg2
-            ) {
-                2
-            } else {
-                1
-            };
-            let shared = if matches!(
-                operation,
-                Tcgen05Operation::CommitSharedCluster
-                    | Tcgen05Operation::CommitSharedClusterCg2
-            ) {
-                ".shared::cluster"
-            } else {
-                ""
-            };
-            (
-                format!("tcgen05.commit.cta_group::{group}.mbarrier::arrive::one{shared}.b64 [$0];"),
-                "r,~{memory}".into(),
-                None,
-            )
-        }
-        Tcgen05Operation::MmaWsF16 | Tcgen05Operation::MmaWsBf16 => (
-            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::f16 [$0], [$1], $3, $4, %enable_pred; }".into(),
-            "r,r,l,l,r,r,~{memory}".into(),
-            None,
-        ),
-        Tcgen05Operation::MmaWsTf32 => (
-            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::tf32 [$0], [$1], $3, $4, %enable_pred; }".into(),
-            "r,r,l,l,r,r,~{memory}".into(),
-            None,
-        ),
-        Tcgen05Operation::MmaF16 | Tcgen05Operation::MmaF16Cg2 => {
-            let group = if operation == Tcgen05Operation::MmaF16Cg2 { 2 } else { 1 };
-            let zeros = std::iter::repeat_n("%z", if group == 2 { 8 } else { 4 })
-                .collect::<Vec<_>>()
-                .join(", ");
-            (
-                format!("{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; .reg .u32 %z; mov.u32 %z, 0; tcgen05.mma.cta_group::{group}.kind::f16 [$0], $1, $2, $3, {{{zeros}}}, %enable_pred; }}"),
-                "r,l,l,r,r,~{memory}".into(),
-                None,
-            )
-        }
-        Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2 => {
-            (
-                format!(
-                    "{}.{} [$0], $1;",
-                    record.expected_ptx.mnemonic,
-                    record.expected_ptx.modifiers.join(".")
-                ),
-                "r,l,~{memory}".into(),
-                None,
-            )
-        }
-        Tcgen05Operation::Ld16x256bX8Pure | Tcgen05Operation::Ld16x256bPure => {
-            let count = if operation == Tcgen05Operation::Ld16x256bX8Pure {
-                32
-            } else {
-                4
-            };
-            let registers = (0..count)
-                .map(|index| format!("${index}"))
-                .collect::<Vec<_>>()
-                .join(",");
-            let constraints = std::iter::repeat_n("=f", count)
-                .chain(std::iter::once("r"))
-                .collect::<Vec<_>>()
-                .join(",");
-            (
-                format!(
-                    "tcgen05.ld.sync.aligned.16x256b.{}.b32 {{{registers}}}, [${count}];",
-                    if count == 32 { "x8" } else { "x1" }
-                ),
-                constraints,
-                Some(count),
-            )
-        }
-        Tcgen05Operation::Ld => {
-            let count = tcgen05_ld_register_count(record);
-            let has_half_split_offset = record
-                .tcgen05
-                .as_ref()
-                .and_then(|tcgen05| tcgen05.ld)
-                .is_some_and(|ld| ld.shape == Tcgen05LdShape::M16x32bx2);
-            let registers = (0..count)
-                .map(|index| format!("${index}"))
-                .collect::<Vec<_>>()
-                .join(",");
-            let constraints = std::iter::repeat_n("=r", count)
-                .chain(if has_half_split_offset {
-                    vec!["r", "n", "~{memory}"]
-                } else {
-                    vec!["r", "~{memory}"]
-                })
-                .collect::<Vec<_>>()
-                .join(",");
-            (
-                format!(
-                    "{}.{} {{{registers}}}, [${count}]{};",
-                    record.expected_ptx.mnemonic,
-                    record.expected_ptx.modifiers.join("."),
-                    if has_half_split_offset {
-                        format!(", ${}", count + 1)
-                    } else {
-                        String::new()
-                    }
-                ),
-                constraints,
-                Some(count),
-            )
-        }
-        Tcgen05Operation::St => {
-            let count = tcgen05_st_register_count(record);
-            let has_half_split_offset = record
-                .tcgen05
-                .as_ref()
-                .and_then(|tcgen05| tcgen05.st)
-                .is_some_and(|st| st.shape == Tcgen05LdShape::M16x32bx2);
-            let first_data = if has_half_split_offset { 2 } else { 1 };
-            let registers = (first_data..first_data + count)
-                .map(|index| format!("${index}"))
-                .collect::<Vec<_>>()
-                .join(",");
-            let constraints = std::iter::once("r")
-                .chain(has_half_split_offset.then_some("n"))
-                .chain(std::iter::repeat_n("r", count))
-                .chain(std::iter::once("~{memory}"))
-                .collect::<Vec<_>>()
-                .join(",");
-            (
-                format!(
-                    "{}.{} [$0], {}{{{registers}}};",
-                    record.expected_ptx.mnemonic,
-                    record.expected_ptx.modifiers.join("."),
-                    if has_half_split_offset {
-                        "$1, "
-                    } else {
-                        ""
-                    }
-                ),
-                constraints,
-                None,
-            )
-        }
-        Tcgen05Operation::LoadWait => (
-            "tcgen05.wait::ld.sync.aligned;".into(),
-            "~{memory}".into(),
-            None,
-        ),
-        Tcgen05Operation::StoreWait => (
-            "tcgen05.wait::st.sync.aligned;".into(),
-            "~{memory}".into(),
-            None,
-        ),
-        Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2 => {
-            let group = if operation == Tcgen05Operation::CommitMulticastCg2 {
-                2
-            } else {
-                1
-            };
-            (
-                format!("tcgen05.commit.cta_group::{group}.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;"),
-                "r,h,~{memory}".into(),
-                None,
-            )
-        }
-        Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2 => {
-            let group = if operation == Tcgen05Operation::ShiftDownCg2 {
-                2
-            } else {
-                1
-            };
-            (
-                format!("tcgen05.shift.cta_group::{group}.down [$0];"),
-                "r,~{memory}".into(),
-                None,
-            )
-        }
-        Tcgen05Operation::Mma => unreachable!("generic MMA uses attribute-driven lowering"),
-    }
-}
-
-fn render_lowering(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Generated conversion interfaces for admitted CUDA intrinsic families.\n\nuse crate::conversion_interface::MirToLlvmConversion;\nuse crate::convert::intrinsics::{atomic::convert_packed_atom_add, basic::convert_sreg_read_inline, common::{call_intrinsic, create_i32_const, inline_asm_convergent}, cp_async::{convert_generated_cp_async_control, convert_generated_cp_async_copy, convert_generated_cp_async_mbarrier}, dotprod::convert_generated_dot_product, ldmatrix::convert_generated_ldmatrix, mbarrier::{convert_arrive, convert_init, convert_inval, convert_test_wait}, packed::{convert_generated_packed_alu, convert_generated_packed_f32x2, convert_generated_packed_unary}, prmt::convert_generated_prmt, warp::{convert_active_mask, convert_bar_warp_sync, convert_match_all, convert_match_any, convert_redux, convert_shuffle_f32, convert_shuffle_i32, convert_shuffle_i64, convert_vote}, wmma::{convert_generated_register_mma, convert_generated_sparse_mma, GeneratedMmaResultType}};\nuse crate::{context, IntrinsicBackend};\nuse dialect_nvvm::ops::{",
-    );
-    if debug_controls(catalog).next().is_some() {
-        output = output.replace(
-            "inline_asm_convergent}",
-            "inline_asm_convergent, inline_asm_sideeffect}",
-        );
-    }
-    if integer_minmaxes(catalog).next().is_some() {
-        output = output.replace(
-            "ldmatrix::convert_generated_ldmatrix, ",
-            "integer_minmax::convert_generated_integer_minmax, ldmatrix::convert_generated_ldmatrix, ",
-        );
-    }
-    if stmatrices(catalog).next().is_some() {
-        output = output.replace(
-            "common::{call_intrinsic,",
-            "common::{call_intrinsic, cast_to_shared_addrspace,",
-        );
-    }
-    if clc_intrinsics(catalog).next().is_some() {
-        output = output.replace(
-            "cp_async::{",
-            "clc::{convert_generated_clc_query, convert_generated_clc_try_cancel}, cp_async::{",
-        );
-    }
-    if tma_intrinsics(catalog).next().is_some() {
-        output = output.replace(
-            "prmt::convert_generated_prmt, warp::{",
-            "prmt::convert_generated_prmt, tma::{convert_control, convert_g2s, convert_g2s_multicast_cg2, convert_prefetch_tensormap, convert_prefetch_tile, convert_reduce_s2g, convert_s2g, convert_tensormap_fence, convert_tensormap_replace, PrefetchTileConfig, ReduceConfig}, warp::{",
-        );
-    }
-    if execution_controls(catalog).next().is_some() {
-        output = output.replace(
-            "dotprod::convert_generated_dot_product, ",
-            "dotprod::convert_generated_dot_product, execution_control::{convert_counted_barrier, convert_grid_dependency, convert_setmaxnreg}, ",
-        );
-    }
-    if scalar_conversions(catalog).next().is_some() {
-        output = output.replace(
-            "prmt::convert_generated_prmt, ",
-            "prmt::convert_generated_prmt, scalar_conversion::convert_generated_scalar_conversion, ",
-        );
-    }
-    if scalar_arithmetics(catalog).next().is_some() {
-        output = output.replace(
-            "prmt::convert_generated_prmt, ",
-            "prmt::convert_generated_prmt, scalar_arithmetic::convert_generated_scalar_arithmetic, ",
-        );
-    }
-    if scalar_maths(catalog).next().is_some() {
-        output = output.replace(
-            "prmt::convert_generated_prmt, ",
-            "prmt::convert_generated_prmt, scalar_math::convert_generated_scalar_math, ",
-        );
-    }
-    if extended_minmax(catalog).next().is_some() {
-        output = output.replace(
-            "dotprod::convert_generated_dot_product, ",
-            "dotprod::convert_generated_dot_product, extended_minmax::{MinMaxCarrier, convert_generated_extended_minmax}, ",
-        );
-    }
-    if elect_intrinsics(catalog).next().is_some() {
-        output = output.replace(
-            "warp::{convert_active_mask,",
-            "warp::{convert_active_mask, convert_elect_sync_inline, convert_elect_sync_typed,",
-        );
-    }
-    for (index, record) in sregs(catalog).enumerate() {
-        if index != 0 {
-            output.push_str(", ");
-        }
-        output.push_str(&record.dialect.op_type);
-    }
-    if ldmatrix(catalog).next().is_some() {
-        if sregs(catalog).next().is_some() {
-            output.push_str(", ");
-        }
-        output.push_str("LdmatrixElementAttr, LdmatrixLayoutAttr, LdmatrixMultiplicityAttr, LdmatrixOp, LdmatrixShapeAttr, LdmatrixStateSpaceAttr");
-        for record in ldmatrix(catalog) {
-            if let Some((op_type, _)) = ldmatrix_compat_op(record) {
-                output.push_str(", ");
-                output.push_str(op_type);
-            }
-        }
-    }
-    if let Some(record) = movmatrix(catalog).next() {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    if register_mmas(catalog).next().is_some() {
-        for record in
-            register_mmas(catalog).filter(|record| register_mma_compat_op_type(record).is_some())
-        {
-            output.push_str(", ");
-            output.push_str(register_mma_compat_op_type(record).unwrap());
-        }
-        output.push_str(", RegisterMmaAccumulatorAttr, RegisterMmaElementAttr, RegisterMmaKindAttr, RegisterMmaLayoutAttr, RegisterMmaOp, RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr");
-    }
-    if sparse_mmas(catalog).next().is_some() {
-        output.push_str(", SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr, SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr");
-    }
-    if prmts(catalog).next().is_some() {
-        output.push_str(", PrmtModeAttr, PrmtOp");
-    }
-    if scalar_conversions(catalog).next().is_some() {
-        output.push_str(
-            ", ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr",
-        );
-    }
-    if scalar_arithmetics(catalog).next().is_some() {
-        output.push_str(
-            ", ScalarArithmeticFormatAttr, ScalarArithmeticOp, ScalarArithmeticOperationAttr, ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr",
-        );
-    }
-    if scalar_maths(catalog).next().is_some() {
-        output.push_str(
-            ", ScalarMathFormatAttr, ScalarMathOp, ScalarMathOperationAttr, ScalarMathPrecisionAttr, ScalarMathSubnormalAttr",
-        );
-    }
-    if extended_minmax(catalog).next().is_some() {
-        output.push_str(
-            ", ExtendedMinMaxFormatAttr, ExtendedMinMaxNanAttr, ExtendedMinMaxOp, ExtendedMinMaxOperationAttr, ExtendedMinMaxSubnormalAttr, ExtendedMinMaxXorSignAbsAttr",
-        );
-    }
-    if cluster_barriers(catalog).next().is_some() {
-        output.push_str(", ClusterBarrierModeAttr, ClusterBarrierOp, ClusterSyncOp");
-    }
-    if debug_controls(catalog).next().is_some() {
-        output.push_str(", BreakpointOp, PmEventOp, TrapOp");
-    }
-    for record in clc_intrinsics(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    if wgmma_controls(catalog).next().is_some() {
-        output.push_str(
-            ", WgmmaCommitGroupSyncAlignedOp, WgmmaFenceSyncAlignedOp, WgmmaWaitGroupSyncAlignedOp",
-        );
-    }
-    for record in tcgen05_non_mma_intrinsics(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    if tcgen05_mma_intrinsics(catalog).next().is_some() {
-        output.push_str(", Tcgen05MmaBBufferAttr, Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr, Tcgen05MmaFormAttr, Tcgen05MmaKindAttr, Tcgen05MmaOp");
-    }
-    if packed_atomics(catalog).next().is_some() {
-        if sregs(catalog).next().is_some() || ldmatrix(catalog).next().is_some() {
-            output.push_str(", ");
-        }
-        output.push_str("NvvmAtomAddBf16x2Op, NvvmAtomAddF16x2Op, PackedAtomicAddOp, PackedAtomicAtomicityAttr, PackedAtomicFormatAttr, PackedAtomicOrderingAttr, PackedAtomicRoundingAttr, PackedAtomicScopeAttr, PackedAtomicStateSpaceAttr, PackedAtomicSubnormalAttr");
-    }
-    if redux(catalog).next().is_some() {
-        if sregs(catalog).next().is_some()
-            || ldmatrix(catalog).next().is_some()
-            || packed_atomics(catalog).next().is_some()
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in redux(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if vote_intrinsics(catalog).next().is_some() {
-        if sregs(catalog).next().is_some()
-            || ldmatrix(catalog).next().is_some()
-            || packed_atomics(catalog).next().is_some()
-            || redux(catalog).next().is_some()
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in vote_intrinsics(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if active_masks(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in active_masks(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if warp_matches(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in warp_matches(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    for record in elect_intrinsics(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    if warp_barriers(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in warp_barriers(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if dot_products(catalog).next().is_some() {
-        if sregs(catalog).next().is_some()
-            || ldmatrix(catalog).next().is_some()
-            || packed_atomics(catalog).next().is_some()
-            || redux(catalog).next().is_some()
-            || vote_intrinsics(catalog).next().is_some()
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in dot_products(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if sync_intrinsics(catalog).next().is_some() {
-        if sregs(catalog).next().is_some()
-            || ldmatrix(catalog).next().is_some()
-            || packed_atomics(catalog).next().is_some()
-            || redux(catalog).next().is_some()
-            || vote_intrinsics(catalog).next().is_some()
-            || dot_products(catalog).next().is_some()
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in sync_intrinsics(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if warp_shuffles(catalog).next().is_some() {
-        output.push_str(", ");
-        for (index, record) in warp_shuffles(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if packed_alus(catalog).next().is_some() {
-        if catalog
-            .intrinsics
-            .iter()
-            .any(|record| record.family != "packed_alu")
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in packed_alus(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if integer_minmaxes(catalog).next().is_some() {
-        // packed_alu records always exist, so a separator is always needed.
-        output.push_str(", ");
-        for (index, record) in integer_minmaxes(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    if packed_conversions(catalog).next().is_some() {
-        if catalog
-            .intrinsics
-            .iter()
-            .any(|record| record.family != "packed_conversion")
-        {
-            output.push_str(", ");
-        }
-        for (index, record) in packed_conversions(catalog).enumerate() {
-            if index != 0 {
-                output.push_str(", ");
-            }
-            output.push_str(&record.dialect.op_type);
-        }
-    }
-    for record in cp_async_copies(catalog)
-        .chain(cp_async_controls(catalog))
-        .chain(cp_async_mbarriers(catalog))
-    {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    for record in mbarrier_basics(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    for record in cluster_memory(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    for record in stmatrices(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    for record in mbarrier_extended(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    for record in tma_intrinsics(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    for record in execution_controls(catalog) {
-        output.push_str(", ");
-        output.push_str(&record.dialect.op_type);
-    }
-    output.push_str(
-        "};\nuse llvm_export::{ops::AsmKind, types as llvm_types};\nuse pliron::{\n    builtin::types::{IntegerType, Signedness},\n    context::{Context, Ptr},\n    derive::op_interface_impl,\n    irbuild::{\n        dialect_conversion::{DialectConversionRewriter, OperandsInfo},\n        rewriter::Rewriter,\n    },\n    op::Op,\n    operation::Operation,\n    result::Result,\n};\n\n",
-    );
-    if cluster_memory(catalog).next().is_some() {
-        if !output.contains("cast_to_shared_addrspace") {
-            output = output.replace(
-                "common::{call_intrinsic, ",
-                "common::{call_intrinsic, cast_to_shared_addrspace, ",
-            );
-        }
-        output = output
-            .replace(
-                "use llvm_export::{ops::AsmKind, types as llvm_types};",
-                "use llvm_export::{op_interfaces::CastOpInterface, ops as llvm_ops, ops::AsmKind, types as llvm_types};",
-            )
-            .replace(
-                "dialect_conversion::{DialectConversionRewriter, OperandsInfo},\n        rewriter::Rewriter,",
-                "dialect_conversion::{DialectConversionRewriter, OperandsInfo},\n        inserter::Inserter,\n        rewriter::Rewriter,",
-            );
-    }
-    if tcgen05_intrinsics(catalog).next().is_some() {
-        output = output.replace(
-            "use llvm_export::{ops::AsmKind, types as llvm_types};",
-            "use llvm_export::{ops as llvm_ops, ops::AsmKind, types as llvm_types};",
-        );
-        output = output.replace(
-            "builtin::types::{IntegerType, Signedness}",
-            "builtin::types::{FP32Type, IntegerType, Signedness}",
-        );
-        output = output.replace(
-            "dialect_conversion::{DialectConversionRewriter, OperandsInfo},\n        rewriter::Rewriter,",
-            "dialect_conversion::{DialectConversionRewriter, OperandsInfo},\n        inserter::Inserter,\n        rewriter::Rewriter,",
-        );
-    }
-    output.push_str("use pliron::location::Located;\n\n");
-    if mbarrier_extended(catalog).next().is_some() {
-        if !output.contains("cast_to_shared_addrspace") {
-            output = output.replace(
-                "common::{call_intrinsic,",
-                "common::{call_intrinsic, cast_to_shared_addrspace,",
-            );
-        }
-        output = if output.contains("inline_asm_sideeffect}") {
-            output.replace(
-                "inline_asm_sideeffect}",
-                "inline_asm_sideeffect, trunc_to_i1}",
-            )
-        } else {
-            output.replace(
-                "inline_asm_convergent}",
-                "inline_asm_convergent, trunc_to_i1}",
-            )
-        };
-        output.push_str("use pliron::value::DefiningEntity;\n\n");
-    }
-    output.push_str(
-        "fn convert_zero_operand_scalar_direct(\n    ctx: &mut Context,\n    rewriter: &mut DialectConversionRewriter,\n    op: Ptr<Operation>,\n    width: u32,\n    intrinsic_name: &str,\n) -> Result<()> {\n    let result_ty = IntegerType::get(ctx, width, Signedness::Signless);\n    let function_ty = llvm_types::FuncType::get(ctx, result_ty.into(), vec![], false);\n    let call = call_intrinsic(ctx, rewriter, op, intrinsic_name, function_ty, vec![])?;\n    rewriter.replace_operation(ctx, op, call);\n    Ok(())\n}\n\n",
-    );
-    if tcgen05_intrinsics(catalog).next().is_some() {
-        output.push_str(
-            r#"fn convert_generated_tcgen05_void(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    arity: usize,
-    template: &str,
-    constraints: &str,
-) -> Result<()> {
-    let operands: Vec<_> = op.deref(ctx).operands().collect();
-    if operands.len() != arity {
-        return pliron::input_err_noloc!(
-            "generated tcgen05 operation expects {arity} operands, got {}",
-            operands.len()
-        );
-    }
-    let void_ty = llvm_types::VoidType::get(ctx);
-    inline_asm_convergent(
-        ctx,
-        rewriter,
-        op,
-        void_ty.into(),
-        operands,
-        template,
-        constraints,
-    );
-    rewriter.erase_operation(ctx, op);
-    Ok(())
-}
-
-#[allow(clippy::too_many_arguments)]
-fn convert_generated_tcgen05_load(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    arity: usize,
-    count: usize,
-    integer_results: bool,
-    template: &str,
-    constraints: &str,
-) -> Result<()> {
-    let operands: Vec<_> = op.deref(ctx).operands().collect();
-    if operands.len() != arity || !(1..=2).contains(&arity) || !(1..=128).contains(&count) || op.deref(ctx).get_num_results() != count {
-        return pliron::input_err_noloc!(
-            "generated tcgen05 load requires 1..=2 operands and 1..=128 results"
-        );
-    }
-    let scalar_ty: pliron::r#type::TypeHandle = if integer_results {
-        IntegerType::get(ctx, 32, Signedness::Signless).into()
-    } else {
-        FP32Type::get(ctx).into()
-    };
-    if count == 1 {
-        let inline_asm = inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            scalar_ty,
-            operands,
-            template,
-            constraints,
-        );
-        let result = inline_asm.deref(ctx).get_result(0);
-        rewriter.replace_operation_with_values(ctx, op, vec![result]);
-        return Ok(());
-    }
-    let result_ty = llvm_types::StructType::get_unnamed(
-        ctx,
-        (
-            (0..count).map(|_| scalar_ty).collect(),
-            llvm_types::StructLayout::Unpacked,
-        ),
-    );
-    let inline_asm = inline_asm_convergent(
-        ctx,
-        rewriter,
-        op,
-        result_ty.into(),
-        operands,
-        template,
-        constraints,
-    );
-    let result = inline_asm.deref(ctx).get_result(0);
-    let mut values = Vec::with_capacity(count);
-    for index in 0..count as u32 {
-        let extract = llvm_ops::ExtractValueOp::new(ctx, result, vec![index])
-            .map_err(|error| pliron::input_error_noloc!("{}", error))?;
-        rewriter.insert_operation(ctx, extract.get_operation());
-        values.push(extract.get_operation().deref(ctx).get_result(0));
-    }
-    rewriter.replace_operation_with_values(ctx, op, values);
-    Ok(())
-}
-
-"#,
-        );
-    }
-    if stmatrices(catalog).next().is_some() {
-        output.push_str(
-            r#"fn convert_generated_stmatrix(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    register_count: usize,
-    transposed: bool,
-    typed_intrinsic_name: &str,
-) -> Result<()> {
-    let operands: Vec<_> = op.deref(ctx).operands().collect();
-    if operands.len() != register_count + 1 || !matches!(register_count, 2 | 4) {
-        return pliron::input_err_noloc!(
-            "stmatrix requires one pointer and two or four registers"
-        );
-    }
-    let void_ty = llvm_types::VoidType::get(ctx);
-    match context::lowering_options(ctx).intrinsic_backend {
-        IntrinsicBackend::LlvmNvptx => {
-            let shared = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
-            let shared_ty = llvm_types::PointerType::get(
-                ctx,
-                llvm_types::address_space::SHARED,
-            );
-            let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-            let argument_types = std::iter::once(shared_ty.into())
-                .chain(std::iter::repeat_n(i32_ty.into(), register_count))
-                .collect();
-            let function_ty = llvm_types::FuncType::get(
-                ctx,
-                void_ty.into(),
-                argument_types,
-                false,
-            );
-            let arguments = std::iter::once(shared)
-                .chain(operands.iter().skip(1).copied())
-                .collect();
-            call_intrinsic(
-                ctx,
-                rewriter,
-                op,
-                typed_intrinsic_name,
-                function_ty,
-                arguments,
-            )?;
-        }
-        IntrinsicBackend::LibNvvm => {
-            let registers = (1..=register_count)
-                .map(|index| format!("${index}"))
-                .collect::<Vec<_>>()
-                .join(", ");
-            let trans = if transposed { ".trans" } else { "" };
-            let template = format!(
-                "{{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x{register_count}{trans}.shared.b16 [%ptr32], {{{registers}}}; }}"
-            );
-            let constraints = std::iter::once("l")
-                .chain(std::iter::repeat_n("r", register_count))
-                .chain(std::iter::once("~{memory}"))
-                .collect::<Vec<_>>()
-                .join(",");
-            inline_asm_convergent(
-                ctx,
-                rewriter,
-                op,
-                void_ty.into(),
-                operands,
-                &template,
-                &constraints,
-            );
-        }
-    }
-    rewriter.erase_operation(ctx, op);
-    Ok(())
-}
-
-"#,
-        );
-    }
-    for record in sregs(catalog) {
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        if record.special_register.is_none() {
-            writeln!(
-                output,
-                "        convert_zero_operand_scalar_direct(ctx, rewriter, self.get_operation(), {}, {:?})",
-                record.scalar_width().unwrap(),
-                record.llvm_identifier()
-            )
-            .unwrap();
-        } else {
-            output.push_str("        match context::lowering_options(ctx).intrinsic_backend {\n");
-            for (backend, backend_variant) in [
-                (IntrinsicBackend::LlvmNvptx, "LlvmNvptx"),
-                (IntrinsicBackend::LibNvvm, "LibNvvm"),
-            ] {
-                writeln!(
-                    output,
-                    "            IntrinsicBackend::{backend_variant} => {{"
-                )
-                .unwrap();
-                match special_register_backend_mechanism(record, backend) {
-                    BackendLoweringMechanism::TypedNvvm => writeln!(
-                        output,
-                        "                convert_zero_operand_scalar_direct(ctx, rewriter, self.get_operation(), {}, {:?})",
-                        record.scalar_width().unwrap(),
-                        record.llvm_identifier()
-                    )
-                    .unwrap(),
-                    BackendLoweringMechanism::InlinePtx => writeln!(
-                        output,
-                        "                convert_sreg_read_inline(ctx, rewriter, self.get_operation(), {}, {:?}, {:?}, {})",
-                        record.scalar_width().unwrap(),
-                        special_register_inline_template(record),
-                        special_register_output_constraint(record),
-                        special_register_asm_kind(record),
-                    )
-                    .unwrap(),
-                }
-                output.push_str("            }\n");
-            }
-            output.push_str("        }\n");
-        }
-        output.push_str("    }\n}\n\n");
-    }
-    for record in active_masks(catalog) {
-        debug_assert_eq!(
-            record.active_mask.as_ref().unwrap().adapter,
-            ActiveMaskAdapter::DirectZeroOperandMask
-        );
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        match context::lowering_options(ctx).intrinsic_backend {\n            IntrinsicBackend::LlvmNvptx => {\n                convert_active_mask(ctx, rewriter, op, operands_info)\n            }\n            IntrinsicBackend::LibNvvm => {\n                let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);\n                let inline_asm = inline_asm_convergent(\n                    ctx,\n                    rewriter,\n                    op,\n                    i32_ty.into(),\n                    vec![],\n                    \"activemask.b32 $0;\",\n                    \"=r,~{memory}\",\n                );\n                rewriter.replace_operation(ctx, op, inline_asm);\n                Ok(())\n            }\n        }\n    }\n}\n\n",
-        );
-    }
-    if ldmatrix(catalog).next().is_some() {
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for LdmatrixOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = {\n            let shape = self.get_attr_nvvm_ldmatrix_shape(ctx);\n            let multiplicity = self.get_attr_nvvm_ldmatrix_multiplicity(ctx);\n            let layout = self.get_attr_nvvm_ldmatrix_layout(ctx);\n            let element = self.get_attr_nvvm_ldmatrix_element(ctx);\n            let state_space = self.get_attr_nvvm_ldmatrix_state_space(ctx);\n            match (shape.as_deref(), multiplicity.as_deref(), layout.as_deref(), element.as_deref(), state_space.as_deref()) {\n",
-        );
-        for record in ldmatrix(catalog) {
-            let (shape, multiplicity, layout, element, state_space) =
-                ldmatrix_attr_variants(record);
-            let variant = &record.ldmatrix.as_ref().unwrap().variant;
-            let register_count = variant.register_count();
-            let instruction_head = expected_ptx_head(record);
-            let intrinsic_name = record.resolved_llvm_identifier();
-            writeln!(
-                output,
-                "                (Some(&{shape}), Some(&{multiplicity}), Some(&{layout}), Some(&{element}), Some(&{state_space})) => ({register_count}, {instruction_head:?}, {intrinsic_name:?}),"
-            )
-            .unwrap();
-        }
-        output.push_str(
-            "                _ => return pliron::input_err!(\n                    self.get_operation().deref(ctx).loc(),\n                    \"nvvm.ldmatrix variant has no generated lowering recipe\",\n                ),\n            }\n        };\n        convert_generated_ldmatrix(ctx, rewriter, self.get_operation(), recipe.0, recipe.1, recipe.2)\n    }\n}\n\n",
-        );
-        for record in ldmatrix(catalog) {
-            let Some((op_type, _)) = ldmatrix_compat_op(record) else {
-                continue;
-            };
-            let variant = &record
-                .ldmatrix
-                .as_ref()
-                .expect("ldmatrix compatibility record")
-                .variant;
-            let register_count = variant.register_count();
-            let instruction_head = expected_ptx_head(record);
-            let intrinsic_name = record.resolved_llvm_identifier();
-            writeln!(
-                output,
-                "#[op_interface_impl]\nimpl MirToLlvmConversion for {op_type} {{\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {{\n        convert_generated_ldmatrix(\n            ctx, rewriter, self.get_operation(), {register_count}, {instruction_head:?}, {intrinsic_name:?},\n        )\n    }}\n}}\n"
-            )
-            .unwrap();
-        }
-    }
-    for record in stmatrices(catalog) {
-        let (multiplicity, layout) = stmatrix_variant(record).expect("stmatrix variant");
-        let count = multiplicity.register_count();
-        let transposed = layout == StmatrixLayout::Transposed;
-        let intrinsic_name = record.resolved_llvm_identifier();
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {{\n        convert_generated_stmatrix(\n            ctx, rewriter, self.get_operation(), {count}, {transposed}, {intrinsic_name:?},\n        )\n    }}\n}}\n"
-        )
-        .unwrap();
-    }
-    if let Some(record) = movmatrix(catalog).next() {
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {{\n        let op = self.get_operation();\n        let operands: Vec<_> = op.deref(ctx).operands().collect();\n        if operands.len() != 1 {{\n            return pliron::input_err_noloc!(\n                \"movmatrix_trans_b16 requires 1 operand, got {{}}\",\n                operands.len()\n            );\n        }}\n        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);\n        let asm = inline_asm_convergent(\n            ctx, rewriter, op, result_ty.into(), operands, {:?}, \"=r,r\",\n        );\n        rewriter.replace_operation(ctx, op, asm);\n        Ok(())\n    }}\n}}\n",
-            record.dialect.op_type,
-            movmatrix_template(record),
-        )
-        .unwrap();
-    }
-    if register_mmas(catalog).next().is_some() {
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for RegisterMmaOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let operation = self.operation_or_multiply(ctx);\n        let kind = self.kind_or_inferred(ctx);\n        let recipe = match (\n            self.get_attr_nvvm_register_mma_shape(ctx).as_deref(),\n            operation,\n            kind,\n            self.get_attr_nvvm_register_mma_accumulator(ctx).as_deref(),\n            self.get_attr_nvvm_register_mma_a_element(ctx).as_deref(),\n            self.get_attr_nvvm_register_mma_b_element(ctx).as_deref(),\n            self.get_attr_nvvm_register_mma_a_layout(ctx).as_deref(),\n            self.get_attr_nvvm_register_mma_b_layout(ctx).as_deref(),\n            self.get_attr_nvvm_register_mma_overflow(ctx).as_deref(),\n        ) {\n",
-        );
-        for record in register_mmas(catalog) {
-            let (
-                shape,
-                operation,
-                kind,
-                accumulator,
-                a_element,
-                b_element,
-                a_layout,
-                b_layout,
-                overflow,
-            ) = register_mma_attr_variants(record);
-            let (c_count, a_count, b_count, result_count) = register_mma_fragment_counts(record);
-            let expected_operands =
-                c_count + a_count + b_count + register_mma_extra_operand_count(record);
-            writeln!(
-                output,
-                "            (Some(&{shape}), {operation}, {kind}, Some(&{accumulator}), Some(&{a_element}), Some(&{b_element}), Some(&{a_layout}), Some(&{b_layout}), Some(&{overflow})) => ({}, {result_count}, {expected_operands}, {:?}, {:?}),",
-                register_mma_result_variant(record),
-                register_mma_template(record),
-                register_mma_constraints(record),
-            )
-            .unwrap();
-        }
-        output.push_str(
-            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.register_mma variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_register_mma(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1, recipe.2, recipe.3, recipe.4,\n        )\n    }\n}\n\n",
-        );
-        for record in
-            register_mmas(catalog).filter(|record| register_mma_compat_op_type(record).is_some())
-        {
-            let op_type = register_mma_compat_op_type(record).unwrap();
-            let (c_count, a_count, b_count, result_count) = register_mma_fragment_counts(record);
-            let expected_operands = c_count + a_count + b_count;
-            writeln!(
-                output,
-                "#[op_interface_impl]\nimpl MirToLlvmConversion for {op_type} {{\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {{\n        convert_generated_register_mma(\n            ctx, rewriter, self.get_operation(), {}, {result_count}, {expected_operands}, {:?}, {:?},\n        )\n    }}\n}}\n",
-                register_mma_result_variant(record),
-                register_mma_template(record),
-                register_mma_constraints(record),
-            )
-            .unwrap();
-        }
-    }
-    if sparse_mmas(catalog).next().is_some() {
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for SparseMmaOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match (\n            self.get_attr_nvvm_sparse_mma_shape(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_selector(ctx).as_deref(),\n        ) {\n",
-        );
-        for record in sparse_mmas(catalog) {
-            let (
-                shape,
-                accumulator,
-                a_element,
-                b_element,
-                a_layout,
-                b_layout,
-                overflow,
-                metadata,
-                selector,
-            ) = sparse_mma_attr_variants(record);
-            let (c_count, a_count, b_count, result_count) = sparse_mma_fragment_counts(record);
-            let expected_operands = c_count + a_count + b_count + 2;
-            writeln!(
-                output,
-                "            (Some(&{shape}), Some(&{accumulator}), Some(&{a_element}), Some(&{b_element}), Some(&{a_layout}), Some(&{b_layout}), Some(&{overflow}), Some(&{metadata}), Some(&{selector})) => ({}, {result_count}, {expected_operands}, {:?}, {:?}),",
-                sparse_mma_result_variant(record),
-                sparse_mma_template(record),
-                sparse_mma_constraints(record),
-            )
-            .unwrap();
-        }
-        output.push_str(
-            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.sparse_mma variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_sparse_mma(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1, recipe.2, recipe.3, recipe.4,\n        )\n    }\n}\n\n",
-        );
-    }
-    if prmts(catalog).next().is_some() {
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for PrmtOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match self.get_attr_nvvm_prmt_mode(ctx).as_deref() {\n",
-        );
-        for record in prmts(catalog) {
-            let prmt = record.prmt.as_ref().unwrap();
-            let mode = match prmt.mode {
-                PrmtMode::Generic => "PrmtModeAttr::Generic",
-                PrmtMode::F4e => "PrmtModeAttr::F4e",
-                PrmtMode::B4e => "PrmtModeAttr::B4e",
-                PrmtMode::Rc8 => "PrmtModeAttr::Rc8",
-                PrmtMode::Ecl => "PrmtModeAttr::Ecl",
-                PrmtMode::Ecr => "PrmtModeAttr::Ecr",
-                PrmtMode::Rc16 => "PrmtModeAttr::Rc16",
-            };
-            let modifier = match prmt.mode {
-                PrmtMode::Generic => "",
-                PrmtMode::F4e => ".f4e",
-                PrmtMode::B4e => ".b4e",
-                PrmtMode::Rc8 => ".rc8",
-                PrmtMode::Ecl => ".ecl",
-                PrmtMode::Ecr => ".ecr",
-                PrmtMode::Rc16 => ".rc16",
-            };
-            let template = match prmt.adapter {
-                PrmtAdapter::DirectThreeOperands => {
-                    format!("prmt.b32{modifier} $0, $1, $2, $3;")
-                }
-                PrmtAdapter::InsertZeroSecondSource => {
-                    format!("prmt.b32{modifier} $0, $1, 0, $2;")
-                }
-            };
-            writeln!(
-                output,
-                "            Some(&{mode}) => ({:?}, {:?}),",
-                record.llvm_identifier(),
-                template
-            )
-            .unwrap();
-        }
-        output.push_str(
-            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.prmt mode has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_prmt(ctx, rewriter, self.get_operation(), recipe.0, recipe.1)\n    }\n}\n\n",
-        );
-    }
-    if scalar_conversions(catalog).next().is_some() {
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for ScalarConversionOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match (\n            self.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_conversion_saturation(ctx).as_deref(),\n        ) {\n",
-        );
-        for record in scalar_conversions(catalog) {
-            writeln!(
-                output,
-                "            (Some(&{}), Some(&{})) => ({:?}, {:?}),",
-                scalar_conversion_rounding_attr(record),
-                scalar_conversion_saturation_attr(record),
-                record.llvm_identifier(),
-                scalar_conversion_ptx_mnemonic(record),
-            )
-            .unwrap();
-        }
-        output.push_str(
-            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.scalar_conversion variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_scalar_conversion(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1,\n        )\n    }\n}\n\n",
-        );
-    }
-    if scalar_arithmetics(catalog).next().is_some() {
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for ScalarArithmeticOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match (\n            self.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_arithmetic_subnormal(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_arithmetic_saturation(ctx).as_deref(),\n        ) {\n",
-        );
-        for record in scalar_arithmetics(catalog) {
-            writeln!(
-                output,
-                "            (Some(&{}), Some(&{}), Some(&{}), Some(&{}), Some(&{})) => ({:?}, {:?}, {}, {}),",
-                scalar_arithmetic_format_attr(record),
-                scalar_arithmetic_operation_attr(record),
-                scalar_arithmetic_rounding_attr(record),
-                scalar_arithmetic_subnormal_attr(record),
-                scalar_arithmetic_saturation_attr(record),
-                record.llvm_identifier(),
-                scalar_arithmetic_ptx_mnemonic(record),
-                scalar_arithmetic_contract(record).format == ScalarArithmeticFormat::F64,
-                scalar_arithmetic_llvm_mechanism(record)
-                    == BackendLoweringMechanism::InlinePtx,
-            )
-            .unwrap();
-        }
-        output.push_str(
-            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.scalar_arithmetic variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_scalar_arithmetic(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1, recipe.2, recipe.3,\n        )\n    }\n}\n\n",
-        );
-    }
-    if scalar_maths(catalog).next().is_some() {
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for ScalarMathOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match (\n            self.get_attr_nvvm_scalar_math_format(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_math_operation(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_math_precision(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_math_subnormal(ctx).as_deref(),\n        ) {\n",
-        );
-        for record in scalar_maths(catalog) {
-            // PTX-native records carry no LLVM symbol. The identifier is
-            // only consumed by the typed route, which such records never
-            // take (their mechanism is always inline PTX), so render an
-            // empty name; the lowering helper rejects it defensively.
-            let intrinsic_name = if record.llvm.is_some() {
-                record.llvm_identifier()
-            } else {
-                String::new()
-            };
-            writeln!(
-                output,
-                "            (Some(&{}), Some(&{}), Some(&{}), Some(&{})) => ({:?}, {:?}, {}, {}, {}),",
-                scalar_math_format_attr(record),
-                scalar_math_operation_attr(record),
-                scalar_math_precision_attr(record),
-                scalar_math_subnormal_attr(record),
-                intrinsic_name,
-                scalar_math_ptx_mnemonic(record),
-                scalar_math_contract(record).format == ScalarMathFormat::F16,
-                scalar_math_contract(record).format == ScalarMathFormat::F64,
-                scalar_math_llvm_mechanism(record) == BackendLoweringMechanism::InlinePtx,
-            )
-            .unwrap();
-        }
-        output.push_str(
-            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.scalar_math variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_scalar_math(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1, recipe.2, recipe.3, recipe.4,\n        )\n    }\n}\n\n",
-        );
-    }
-    if extended_minmax(catalog).next().is_some() {
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for ExtendedMinMaxOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match (\n            self.get_attr_nvvm_extended_minmax_format(ctx).as_deref(),\n            self.get_attr_nvvm_extended_minmax_operation(ctx).as_deref(),\n            self.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref(),\n            self.get_attr_nvvm_extended_minmax_nan(ctx).as_deref(),\n            self.get_attr_nvvm_extended_minmax_xorsign_abs(ctx).as_deref(),\n        ) {\n",
-        );
-        for record in extended_minmax(catalog) {
-            writeln!(
-                output,
-                "            (Some(&{}), Some(&{}), Some(&{}), Some(&{}), Some(&{})) => ({:?}, {}),",
-                extended_minmax_format_attr(record),
-                extended_minmax_operation_attr(record),
-                extended_minmax_subnormal_attr(record),
-                extended_minmax_nan_attr(record),
-                extended_minmax_xorsign_abs_attr(record),
-                extended_minmax_ptx_mnemonic(record),
-                extended_minmax_carrier(record),
-            )
-            .unwrap();
-        }
-        output.push_str(
-            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.extended_minmax variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_extended_minmax(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1,\n        )\n    }\n}\n\n",
-        );
-    }
-    if cluster_barriers(catalog).next().is_some() {
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for ClusterBarrierOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match self.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() {\n",
-        );
-        for record in cluster_barriers(catalog) {
-            writeln!(
-                output,
-                "            Some(&{}) => ({:?}, {:?}),",
-                cluster_barrier_attr(record),
-                record.llvm_identifier(),
-                cluster_barrier_template(record)
-            )
-            .unwrap();
-        }
-        output.push_str(
-            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.cluster_barrier mode has no generated lowering recipe\",\n            ),\n        };\n        let op = self.get_operation();\n        let void_ty = llvm_types::VoidType::get(ctx);\n        match context::lowering_options(ctx).intrinsic_backend {\n            IntrinsicBackend::LlvmNvptx => {\n                let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);\n                call_intrinsic(ctx, rewriter, op, recipe.0, function_ty, vec![])?;\n            }\n            IntrinsicBackend::LibNvvm => {\n                inline_asm_convergent(ctx, rewriter, op, void_ty.into(), vec![], recipe.1, \"~{memory}\");\n            }\n        }\n        rewriter.erase_operation(ctx, op);\n        Ok(())\n    }\n}\n\n",
-        );
-
-        let arrive = cluster_barriers(catalog)
-            .find(|record| {
-                record
-                    .cluster_barrier
-                    .as_ref()
-                    .is_some_and(|barrier| barrier.mode == ClusterBarrierMode::ArriveAligned)
-            })
-            .expect("aligned cluster arrival");
-        let wait = cluster_barriers(catalog)
-            .find(|record| {
-                record
-                    .cluster_barrier
-                    .as_ref()
-                    .is_some_and(|barrier| barrier.mode == ClusterBarrierMode::WaitAligned)
-            })
-            .expect("aligned cluster wait");
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for ClusterSyncOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        let void_ty = llvm_types::VoidType::get(ctx);\n        match context::lowering_options(ctx).intrinsic_backend {\n            IntrinsicBackend::LlvmNvptx => {\n                let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);\n",
-        );
-        writeln!(
-            output,
-            "                call_intrinsic(ctx, rewriter, op, {:?}, function_ty, vec![])?;",
-            arrive.llvm_identifier()
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "                call_intrinsic(ctx, rewriter, op, {:?}, function_ty, vec![])?;",
-            wait.llvm_identifier()
-        )
-        .unwrap();
-        output.push_str("            }\n            IntrinsicBackend::LibNvvm => {\n");
-        writeln!(
-            output,
-            "                inline_asm_convergent(ctx, rewriter, op, void_ty.into(), vec![], {:?}, \"~{{memory}}\");",
-            format!(
-                "{} {}",
-                cluster_barrier_template(arrive),
-                cluster_barrier_template(wait)
-            )
-        )
-        .unwrap();
-        output.push_str(
-            "            }\n        }\n        rewriter.erase_operation(ctx, op);\n        Ok(())\n    }\n}\n\n",
-        );
-    }
-    if wgmma_controls(catalog).next().is_some() {
-        output.push_str(
-            "fn convert_generated_wgmma_control(\n\
-                 ctx: &mut Context,\n\
-                 rewriter: &mut DialectConversionRewriter,\n\
-                 op: Ptr<Operation>,\n\
-                 intrinsic_name: &str,\n\
-                 ptx: &str,\n\
-                 has_immediate: bool,\n\
-             ) -> Result<()> {\n\
-                 let operands: Vec<_> = op.deref(ctx).operands().collect();\n\
-                 if operands.len() != usize::from(has_immediate) {\n\
-                     return pliron::input_err!(\n\
-                         op.deref(ctx).loc(),\n\
-                         \"generated WGMMA control has the wrong operand count\",\n\
-                     );\n\
-                 }\n\
-                 let void_ty = llvm_types::VoidType::get(ctx);\n\
-                 match context::lowering_options(ctx).intrinsic_backend {\n\
-                     IntrinsicBackend::LlvmNvptx => {\n\
-                         let arguments = if has_immediate {\n\
-                             vec![IntegerType::get(ctx, 64, Signedness::Signless).into()]\n\
-                         } else {\n\
-                             vec![]\n\
-                         };\n\
-                         let function_ty = llvm_types::FuncType::get(\n\
-                             ctx, void_ty.into(), arguments, false,\n\
-                         );\n\
-                         call_intrinsic(\n\
-                             ctx, rewriter, op, intrinsic_name, function_ty, operands,\n\
-                         )?;\n\
-                     }\n\
-                     IntrinsicBackend::LibNvvm => {\n\
-                         let constraints = if has_immediate {\n\
-                             \"n,~{memory}\"\n\
-                         } else {\n\
-                             \"~{memory}\"\n\
-                         };\n\
-                         inline_asm_convergent(\n\
-                             ctx, rewriter, op, void_ty.into(), operands, ptx, constraints,\n\
-                         );\n\
-                     }\n\
-                 }\n\
-                 rewriter.erase_operation(ctx, op);\n\
-                 Ok(())\n\
-             }\n\n",
-        );
-        for record in wgmma_controls(catalog) {
-            let has_immediate = record
-                .wgmma_control
-                .as_ref()
-                .is_some_and(|control| control.mode == WgmmaControlMode::WaitGroup);
-            writeln!(
-                output,
-                "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {{\n        convert_generated_wgmma_control(\n            ctx, rewriter, self.get_operation(), {:?}, {:?}, {has_immediate},\n        )\n    }}\n}}\n",
-                record.dialect.op_type,
-                record.llvm_identifier(),
-                wgmma_control_template(record),
-            )
-            .unwrap();
-        }
-    }
-    if packed_atomics(catalog).next().is_some() {
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for PackedAtomicAddOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let format = self.get_attr_nvvm_packed_atomic_format(ctx);\n        let state_space = self.get_attr_nvvm_packed_atomic_state_space(ctx);\n        let ordering = self.get_attr_nvvm_packed_atomic_ordering(ctx);\n        let scope = self.get_attr_nvvm_packed_atomic_scope(ctx);\n        let rounding = self.get_attr_nvvm_packed_atomic_rounding(ctx);\n        let subnormal = self.get_attr_nvvm_packed_atomic_subnormal(ctx);\n        let atomicity = self.get_attr_nvvm_packed_atomic_atomicity(ctx);\n        let ptx_type = match (format.as_deref(), state_space.as_deref(), ordering.as_deref(), scope.as_deref(), rounding.as_deref(), subnormal.as_deref(), atomicity.as_deref()) {\n            (Some(&PackedAtomicFormatAttr::F16x2), Some(&PackedAtomicStateSpaceAttr::Global), Some(&PackedAtomicOrderingAttr::Relaxed), Some(&PackedAtomicScopeAttr::Gpu), Some(&PackedAtomicRoundingAttr::Rn), Some(&PackedAtomicSubnormalAttr::NoFtz), Some(&PackedAtomicAtomicityAttr::PerElement)) => \"f16x2\",\n            (Some(&PackedAtomicFormatAttr::Bf16x2), Some(&PackedAtomicStateSpaceAttr::Global), Some(&PackedAtomicOrderingAttr::Relaxed), Some(&PackedAtomicScopeAttr::Gpu), Some(&PackedAtomicRoundingAttr::Rn), Some(&PackedAtomicSubnormalAttr::NoFtz), Some(&PackedAtomicAtomicityAttr::PerElement)) => \"bf16x2\",\n            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.packed_atomic_add attributes have no generated lowering recipe\",\n            ),\n        };\n        convert_packed_atom_add(ctx, rewriter, self.get_operation(), ptx_type)\n    }\n}\n\n",
-        );
-        output = output.replace(
-            "        convert_packed_atom_add(ctx, rewriter, self.get_operation(), ptx_type)",
-            "        drop((format, state_space, ordering, scope, rounding, subnormal, atomicity));\n        convert_packed_atom_add(ctx, rewriter, self.get_operation(), ptx_type)",
-        );
-        output.push_str(
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for NvvmAtomAddF16x2Op {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        convert_packed_atom_add(ctx, rewriter, self.get_operation(), \"f16x2\")\n    }\n}\n\n#[op_interface_impl]\nimpl MirToLlvmConversion for NvvmAtomAddBf16x2Op {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        convert_packed_atom_add(ctx, rewriter, self.get_operation(), \"bf16x2\")\n    }\n}\n\n",
-        );
-    }
-    for record in redux(catalog) {
-        debug_assert_eq!(
-            record.redux.as_ref().unwrap().adapter,
-            ReduxAdapter::MaskValueToSourceMemberMask
-        );
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        writeln!(
-            output,
-            "        convert_redux(ctx, rewriter, self.get_operation(), operands_info, {:?})",
-            record.llvm_identifier()
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    for record in vote_intrinsics(catalog) {
-        debug_assert_eq!(
-            record.vote.as_ref().unwrap().adapter,
-            VoteAdapter::DirectMaskPredicate
-        );
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        writeln!(
-            output,
-            "        convert_vote(ctx, rewriter, self.get_operation(), operands_info, {:?})",
-            record.llvm_identifier()
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    for record in warp_matches(catalog) {
-        let warp_match = record.warp_match.as_ref().unwrap();
-        let helper = match warp_match.adapter {
-            WarpMatchAdapter::DirectMask => "convert_match_any",
-            WarpMatchAdapter::ProjectMaskDiscardPredicate => "convert_match_all",
-        };
-        let value_width = warp_match.value_width.bits();
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        writeln!(
-            output,
-            "        let value_ty = IntegerType::get(ctx, {value_width}, Signedness::Signless);"
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "        {helper}(ctx, rewriter, self.get_operation(), operands_info, {:?}, value_ty.into())",
-            record.llvm_identifier()
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    for record in elect_intrinsics(catalog) {
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        match context::lowering_options(ctx).intrinsic_backend {\n",
-        );
-        for (backend, variant) in [
-            (IntrinsicBackend::LlvmNvptx, "LlvmNvptx"),
-            (IntrinsicBackend::LibNvvm, "LibNvvm"),
-        ] {
-            let mechanism = record
-                .backend_lowerings
-                .iter()
-                .find(|route| route.backend == backend)
-                .expect("elect backend route")
-                .mechanism;
-            writeln!(output, "            IntrinsicBackend::{variant} => {{").unwrap();
-            match mechanism {
-                BackendLoweringMechanism::TypedNvvm => writeln!(
-                    output,
-                    "                convert_elect_sync_typed(ctx, rewriter, self.get_operation(), operands_info, {:?})",
-                    record.llvm_identifier()
-                )
-                .unwrap(),
-                BackendLoweringMechanism::InlinePtx => output.push_str(
-                    "                convert_elect_sync_inline(ctx, rewriter, self.get_operation(), operands_info)\n",
-                ),
-            }
-            output.push_str("            }\n");
-        }
-        output.push_str("        }\n    }\n}\n\n");
-    }
-    for record in warp_barriers(catalog) {
-        debug_assert_eq!(
-            record.warp_barrier.as_ref().unwrap().adapter,
-            WarpBarrierAdapter::DirectMemberMask
-        );
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        convert_bar_warp_sync(ctx, rewriter, self.get_operation(), operands_info)\n    }\n}\n\n",
-        );
-    }
-    for record in warp_shuffles(catalog) {
-        let shuffle = record.warp_shuffle.as_ref().unwrap();
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        match shuffle.value_kind {
-            WarpShuffleValueKind::I32 | WarpShuffleValueKind::F32 => {
-                debug_assert_eq!(
-                    shuffle.adapter,
-                    WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp
-                );
-                let helper = match shuffle.value_kind {
-                    WarpShuffleValueKind::I32 => "convert_shuffle_i32",
-                    WarpShuffleValueKind::F32 => "convert_shuffle_f32",
-                    WarpShuffleValueKind::I64 => unreachable!(),
-                };
-                writeln!(
-                    output,
-                    "        {helper}(ctx, rewriter, self.get_operation(), operands_info, {:?}, {})",
-                    record.llvm_identifier(),
-                    shuffle.clamp,
-                )
-                .unwrap();
-            }
-            WarpShuffleValueKind::I64 => {
-                debug_assert_eq!(
-                    shuffle.adapter,
-                    WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
-                );
-                let mode = match shuffle.mode {
-                    WarpShuffleMode::Idx => "idx",
-                    WarpShuffleMode::Bfly => "bfly",
-                    WarpShuffleMode::Down => "down",
-                    WarpShuffleMode::Up => "up",
-                };
-                writeln!(
-                    output,
-                    "        convert_shuffle_i64(ctx, rewriter, self.get_operation(), operands_info, {mode:?}, {})",
-                    shuffle.clamp,
-                )
-                .unwrap();
-            }
-        }
-        output.push_str("    }\n}\n\n");
-    }
-    for record in packed_alus(catalog) {
-        let width = packed_alu_width(record);
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        writeln!(
-            output,
-            "        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), {:?}, {width})",
-            packed_alu_ptx_mnemonic(record),
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    for record in integer_minmaxes(catalog) {
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        writeln!(
-            output,
-            "        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), {:?})",
-            integer_minmax_ptx_mnemonic(record)
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    for record in packed_conversions(catalog) {
-        let conversion = record
-            .packed_conversion
-            .as_ref()
-            .expect("packed-conversion record");
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        match conversion.source_format {
-            PackedConversionSourceFormat::F32x2 => {
-                debug_assert_eq!(
-                    conversion.adapter,
-                    PackedConversionAdapter::ReverseHighLowOperands
-                );
-                let typed_intrinsic = packed_conversion_typed_llvm_name(record)
-                    .map(|name| format!("Some({name:?})"))
-                    .unwrap_or_else(|| "None".into());
-                writeln!(
-                    output,
-                    "        convert_generated_packed_f32x2(ctx, rewriter, self.get_operation(), {typed_intrinsic}, {:?}, {})",
-                    packed_conversion_ptx_mnemonic(record),
-                    packed_conversion_result_width(record),
-                )
-                .unwrap();
-            }
-            PackedConversionSourceFormat::E4m3x2
-            | PackedConversionSourceFormat::E5m2x2
-            | PackedConversionSourceFormat::F16x2 => {
-                debug_assert_eq!(conversion.adapter, PackedConversionAdapter::Identity);
-                writeln!(
-                    output,
-                    "        convert_generated_packed_unary(ctx, rewriter, self.get_operation(), {:?}, {}, {})",
-                    packed_conversion_ptx_mnemonic(record),
-                    packed_conversion_result_width(record),
-                    packed_conversion_source_width(record),
-                )
-                .unwrap();
-            }
-        }
-        output.push_str("    }\n}\n\n");
-    }
-    for record in cp_async_copies(catalog) {
-        let copy = record.cp_async_copy.as_ref().unwrap();
-        let cache_policy = match copy.cache_policy {
-            CpAsyncCachePolicy::Ca => "ca",
-            CpAsyncCachePolicy::Cg => "cg",
-        };
-        let has_source_size = copy.source_size == CpAsyncSourceSize::Runtime;
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        writeln!(
-            output,
-            "        convert_generated_cp_async_copy(ctx, rewriter, self.get_operation(), {cache_policy:?}, {}, {has_source_size}, {:?})",
-            copy.copy_size.bytes(),
-            record.llvm_identifier(),
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    for record in cp_async_controls(catalog) {
-        let operation = match record.cp_async_control.as_ref().unwrap().operation {
-            CpAsyncControlOperation::CommitGroup => "commit_group",
-            CpAsyncControlOperation::WaitAll => "wait_all",
-            CpAsyncControlOperation::WaitGroup => "wait_group",
-        };
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        writeln!(
-            output,
-            "        convert_generated_cp_async_control(ctx, rewriter, self.get_operation(), {operation:?}, {:?})",
-            record.llvm_identifier(),
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    for record in cp_async_mbarriers(catalog) {
-        let bridge = record.cp_async_mbarrier.as_ref().unwrap();
-        let operation = match bridge.operation {
-            CpAsyncMbarrierOperation::Arrive => "arrive",
-            CpAsyncMbarrierOperation::ArriveNoInc => "arrive_no_inc",
-        };
-        let state_space = match bridge.state_space {
-            CpAsyncMbarrierStateSpace::Generic => "generic",
-            CpAsyncMbarrierStateSpace::Shared => "shared",
-        };
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        writeln!(
-            output,
-            "        convert_generated_cp_async_mbarrier(ctx, rewriter, self.get_operation(), {operation:?}, {state_space:?}, {:?})",
-            record.llvm_identifier(),
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    for record in mbarrier_basics(catalog) {
-        let mbarrier = record.mbarrier_basic.as_ref().unwrap();
-        let helper = match (mbarrier.operation, mbarrier.adapter) {
-            (MbarrierBasicOperation::Init, MbarrierBasicAdapter::InitPointerCountToVoid) => {
-                "convert_init"
-            }
-            (MbarrierBasicOperation::Arrive, MbarrierBasicAdapter::ArrivePointerToToken) => {
-                "convert_arrive"
-            }
-            (
-                MbarrierBasicOperation::TestWait,
-                MbarrierBasicAdapter::TestWaitPointerTokenToPredicate,
-            ) => "convert_test_wait",
-            (MbarrierBasicOperation::Inval, MbarrierBasicAdapter::InvalPointerToVoid) => {
-                "convert_inval"
-            }
-            _ => unreachable!("resolver admitted an invalid basic mbarrier adapter"),
-        };
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        writeln!(
-            output,
-            "        {helper}(ctx, rewriter, self.get_operation(), operands_info)"
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    for record in cluster_memory(catalog) {
-        let cluster = record.cluster_memory.as_ref().unwrap();
-        let (template, constraints) =
-            crate::resolve::cluster_memory_inline_recipe(cluster.operation);
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        let operands: Vec<_> = op.deref(ctx).operands().collect();\n",
-        );
-        writeln!(
-            output,
-            "        if operands.len() != 2 {{\n            return pliron::input_err_noloc!({:?}, operands.len());\n        }}",
-            format!("{} requires 2 operands, got {{}}", record.rust.name)
-        )
-        .unwrap();
-        output.push_str(
-            "        let shared_pointer = cast_to_shared_addrspace(ctx, rewriter, operands[0]);\n        let rank = operands[1];\n",
-        );
-        match cluster.operation {
-            ClusterMemoryOperation::MapSharedRank => {
-                writeln!(
-                    output,
-                    "        let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);\n        let asm = inline_asm_convergent(\n            ctx, rewriter, op, i64_ty.into(), vec![shared_pointer, rank], {template:?}, {constraints:?},\n        );\n        let mapped = asm.deref(ctx).get_result(0);\n        let cluster_shared_pointer_ty = llvm_types::PointerType::get(ctx, 7);\n        let int_to_ptr = llvm_ops::IntToPtrOp::new(ctx, mapped, cluster_shared_pointer_ty.into());\n        rewriter.insert_operation(ctx, int_to_ptr.get_operation());\n        rewriter.replace_operation(ctx, op, int_to_ptr.get_operation());\n        Ok(())"
-                )
-                .unwrap();
-            }
-            ClusterMemoryOperation::ReadU32 => {
-                writeln!(
-                    output,
-                    "        let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);\n        let asm = inline_asm_convergent(\n            ctx, rewriter, op, i32_ty.into(), vec![shared_pointer, rank], {template:?}, {constraints:?},\n        );\n        rewriter.replace_operation(ctx, op, asm);\n        Ok(())"
-                )
-                .unwrap();
-            }
-        }
-        output.push_str("    }\n}\n\n");
-    }
-    for record in mbarrier_extended(catalog) {
-        let contract = record.mbarrier_extended.as_ref().unwrap();
-        let (template, constraints) =
-            crate::resolve::mbarrier_extended_inline_recipe(contract.operation);
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        let mutability = if matches!(
-            contract.adapter,
-            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount
-                | MbarrierExtendedAdapter::PointerTokenToPredicate
-                | MbarrierExtendedAdapter::PointerParityToPredicate
-        ) {
-            "mut "
-        } else {
-            ""
-        };
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n",
-        );
-        writeln!(
-            output,
-            "        let {mutability}operands: Vec<_> = op.deref(ctx).operands().collect();"
-        )
-        .unwrap();
-        let operand_count = record.dialect.operands.len();
-        let operand_count_check = if operand_count == 0 {
-            "!operands.is_empty()".to_owned()
-        } else {
-            format!("operands.len() != {operand_count}")
-        };
-        writeln!(
-            output,
-            "        if {operand_count_check} {{\n            return pliron::input_err_noloc!({:?}, operands.len());\n        }}",
-            format!(
-                "{} requires {} operands, got {{}}",
-                record.rust.name,
-                operand_count
-            )
-        )
-        .unwrap();
-        if matches!(
-            contract.adapter,
-            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount
-                | MbarrierExtendedAdapter::PointerTokenToPredicate
-                | MbarrierExtendedAdapter::PointerParityToPredicate
-        ) {
-            output.push_str(
-                "        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);\n",
-            );
-        }
-        match contract.adapter {
-            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount => {
-                writeln!(
-                    output,
-                    "        let result_ty = IntegerType::get(ctx, 64, Signedness::Signless);\n        let asm = inline_asm_convergent(ctx, rewriter, op, result_ty.into(), operands, {template:?}, {constraints:?});\n        rewriter.replace_operation(ctx, op, asm);\n        Ok(())"
-                )
-                .unwrap();
-            }
-            MbarrierExtendedAdapter::PointerTokenToPredicate
-            | MbarrierExtendedAdapter::PointerParityToPredicate => {
-                writeln!(
-                    output,
-                    "        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);\n        let asm = inline_asm_convergent(ctx, rewriter, op, result_ty.into(), operands, {template:?}, {constraints:?});\n        let asm_result = asm.deref(ctx).get_result(0);\n        let result = trunc_to_i1(ctx, rewriter, asm_result);\n        let DefiningEntity::Op(result_op) = result.defining_entity() else {{ unreachable!() }};\n        rewriter.replace_operation(ctx, op, result_op);\n        Ok(())"
-                )
-                .unwrap();
-            }
-            MbarrierExtendedAdapter::RawClusterAddressToVoid
-            | MbarrierExtendedAdapter::ZeroOperandsToVoid
-            | MbarrierExtendedAdapter::NanosecondsToVoid => {
-                writeln!(
-                    output,
-                    "        let void_ty = llvm_types::VoidType::get(ctx);\n        inline_asm_convergent(ctx, rewriter, op, void_ty.into(), operands, {template:?}, {constraints:?});\n        rewriter.erase_operation(ctx, op);\n        Ok(())"
-                )
-                .unwrap();
-            }
-        }
-        output.push_str("    }\n}\n\n");
-    }
-    for record in dot_products(catalog) {
-        let insert_low_half_selector = matches!(
-            record.dot_product.as_ref().unwrap().adapter,
-            DotProductAdapter::InsertLowHalfFalse
-        );
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        writeln!(
-            output,
-            "        convert_generated_dot_product(ctx, rewriter, self.get_operation(), {:?}, {:?}, {insert_low_half_selector})",
-            record.llvm_identifier(),
-            dot_product_ptx(record),
-        )
-        .unwrap();
-        output.push_str("    }\n}\n\n");
-    }
-    for record in clc_intrinsics(catalog) {
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        match record.clc.as_ref().unwrap().operation {
-            ClcOperation::TryCancel | ClcOperation::TryCancelMulticast => {
-                writeln!(
-                    output,
-                    "        convert_generated_clc_try_cancel(ctx, rewriter, self.get_operation(), operands_info, {:?})",
-                    record.llvm_identifier()
-                )
-                .unwrap();
-            }
-            ClcOperation::QueryIsCanceled
-            | ClcOperation::QueryGetFirstCtaidX
-            | ClcOperation::QueryGetFirstCtaidY
-            | ClcOperation::QueryGetFirstCtaidZ => {
-                writeln!(
-                    output,
-                    "        convert_generated_clc_query(ctx, rewriter, self.get_operation(), operands_info, {:?}, {})",
-                    record.llvm_identifier(),
-                    record.clc.as_ref().unwrap().operation == ClcOperation::QueryIsCanceled
-                )
-                .unwrap();
-            }
-        }
-        output.push_str("    }\n}\n\n");
-    }
-    for record in execution_controls(catalog) {
-        let operation = ExecutionControlOperation::from_catalog_id(&record.id)
-            .expect("closed execution-control record");
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        match operation {
-            ExecutionControlOperation::BarrierCtaSync
-            | ExecutionControlOperation::BarrierCtaSyncAligned
-            | ExecutionControlOperation::BarrierCtaArrive
-            | ExecutionControlOperation::BarrierCtaArriveAligned => {
-                let template = format!(
-                    "{}.{} $0, $1;",
-                    record.expected_ptx.mnemonic,
-                    record.expected_ptx.modifiers.join(".")
-                );
-                writeln!(
-                    output,
-                    "        convert_counted_barrier(ctx, rewriter, self.get_operation(), operands_info, {:?}, {template:?})",
-                    record.llvm_identifier()
-                )
-                .unwrap();
-            }
-            ExecutionControlOperation::GridDependencyLaunchDependents
-            | ExecutionControlOperation::GridDependencyWait => {
-                let template = format!(
-                    "{}.{};",
-                    record.expected_ptx.mnemonic,
-                    record.expected_ptx.modifiers.join(".")
-                );
-                writeln!(
-                    output,
-                    "        convert_grid_dependency(ctx, rewriter, self.get_operation(), operands_info, {:?}, {template:?})",
-                    record.llvm_identifier()
-                )
-                .unwrap();
-            }
-            ExecutionControlOperation::SetMaxNRegInc | ExecutionControlOperation::SetMaxNRegDec => {
-                let direction = match operation {
-                    ExecutionControlOperation::SetMaxNRegInc => "inc",
-                    ExecutionControlOperation::SetMaxNRegDec => "dec",
-                    _ => unreachable!("setmaxnreg operation was matched"),
-                };
-                output.push_str(
-                    "        let register_count = self.register_count(ctx).ok_or_else(|| pliron::input_error_noloc!(\"setmaxnreg register-count attribute is invalid\"))?;\n",
-                );
-                writeln!(
-                    output,
-                    "        convert_setmaxnreg(ctx, rewriter, self.get_operation(), operands_info, register_count, {:?}, {direction:?})",
-                    record.llvm_identifier()
-                )
-                .unwrap();
-            }
-        }
-        output.push_str("    }\n}\n\n");
-    }
-    for record in tma_intrinsics(catalog) {
-        let operation = record.tma.as_ref().unwrap().operation;
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        match operation {
-            TmaOperation::G2sTile1d
-            | TmaOperation::G2sTile2d
-            | TmaOperation::G2sTile3d
-            | TmaOperation::G2sTile4d
-            | TmaOperation::G2sTile5d => {
-                writeln!(
-                    output,
-                    "        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, {}, false)",
-                    operation.dimensions().unwrap()
-                )
-                .unwrap();
-            }
-            TmaOperation::G2sTile2dMulticast => output.push_str(
-                "        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 2, true)\n",
-            ),
-            TmaOperation::G2sTile2dMulticastCg2 => output.push_str(
-                "        convert_g2s_multicast_cg2(ctx, rewriter, self.get_operation(), operands_info)\n",
-            ),
-            TmaOperation::S2gTile1d
-            | TmaOperation::S2gTile2d
-            | TmaOperation::S2gTile3d
-            | TmaOperation::S2gTile4d
-            | TmaOperation::S2gTile5d => {
-                writeln!(
-                    output,
-                    "        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, {})",
-                    operation.dimensions().unwrap()
-                )
-                .unwrap();
-            }
-            TmaOperation::Reduce => {
-                let reduction = record
-                    .tma
-                    .as_ref()
-                    .and_then(|tma| tma.reduction.as_ref())
-                    .expect("TMA reduction contract");
-                let reduction_name = match reduction.operation {
-                    TmaReductionOperation::Add => "add",
-                    TmaReductionOperation::And => "and",
-                    TmaReductionOperation::Dec => "dec",
-                    TmaReductionOperation::Inc => "inc",
-                    TmaReductionOperation::Max => "max",
-                    TmaReductionOperation::Min => "min",
-                    TmaReductionOperation::Or => "or",
-                    TmaReductionOperation::Xor => "xor",
-                };
-                let load_mode = match reduction.load_mode {
-                    TmaReductionLoadMode::Tile => "tile",
-                    TmaReductionLoadMode::Im2col => "im2col",
-                };
-                writeln!(
-                    output,
-                    "        convert_reduce_s2g(ctx, rewriter, self.get_operation(), operands_info, ReduceConfig::new({}, {reduction_name:?}, {load_mode:?}, {:?}))",
-                    reduction.dimensions,
-                    record.resolved_llvm_identifier()
-                )
-                    .unwrap();
-            }
-            TmaOperation::CommitGroup | TmaOperation::WaitGroup | TmaOperation::WaitGroupRead => {
-                let operation_name = match operation {
-                    TmaOperation::CommitGroup => "commit_group",
-                    TmaOperation::WaitGroup => "wait_group",
-                    TmaOperation::WaitGroupRead => "wait_group_read",
-                    _ => unreachable!("TMA control operation was matched"),
-                };
-                writeln!(
-                    output,
-                    "        convert_control(ctx, rewriter, self.get_operation(), operands_info, {operation_name:?}, {:?})",
-                    record.resolved_llvm_identifier()
-                )
-                .unwrap();
-            }
-            TmaOperation::PrefetchTensorMap => {
-                writeln!(
-                    output,
-                    "        convert_prefetch_tensormap(ctx, rewriter, self.get_operation(), operands_info, {:?})",
-                    record.resolved_llvm_identifier()
-                )
-                .unwrap();
-            }
-            TmaOperation::PrefetchTile1d
-            | TmaOperation::PrefetchTile2d
-            | TmaOperation::PrefetchTile3d
-            | TmaOperation::PrefetchTile4d
-            | TmaOperation::PrefetchTile5d
-            | TmaOperation::PrefetchTileGather4TwoDimensional
-            | TmaOperation::PrefetchTile1dCacheHint
-            | TmaOperation::PrefetchTile2dCacheHint
-            | TmaOperation::PrefetchTile3dCacheHint
-            | TmaOperation::PrefetchTile4dCacheHint
-            | TmaOperation::PrefetchTile5dCacheHint
-            | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint => {
-                writeln!(
-                    output,
-                    "        convert_prefetch_tile(ctx, rewriter, self.get_operation(), operands_info, PrefetchTileConfig::new({}, {}, {}, {:?}))",
-                    operation.prefetch_coordinate_count().unwrap(),
-                    matches!(
-                        operation,
-                        TmaOperation::PrefetchTileGather4TwoDimensional
-                            | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint
-                    ),
-                    operation.uses_prefetch_cache_hint(),
-                    record.resolved_llvm_identifier()
-                )
-                .unwrap();
-            }
-            TmaOperation::ReplaceBoxDim
-            | TmaOperation::ReplaceElementStride
-            | TmaOperation::ReplaceElementType
-            | TmaOperation::ReplaceFillMode
-            | TmaOperation::ReplaceGlobalAddress
-            | TmaOperation::ReplaceGlobalDim
-            | TmaOperation::ReplaceGlobalStride
-            | TmaOperation::ReplaceInterleaveLayout
-            | TmaOperation::ReplaceRank
-            | TmaOperation::ReplaceSwizzleAtomicity
-            | TmaOperation::ReplaceSwizzleMode => {
-                let (field, value_kind, ordinal, immediate) = match operation {
-                    TmaOperation::ReplaceBoxDim => ("box_dim", "u32", true, false),
-                    TmaOperation::ReplaceElementStride => {
-                        ("element_stride", "u32", true, false)
-                    }
-                    TmaOperation::ReplaceElementType => ("elemtype", "u32", false, true),
-                    TmaOperation::ReplaceFillMode => ("fill_mode", "u32", false, true),
-                    TmaOperation::ReplaceGlobalAddress => {
-                        ("global_address", "address", false, false)
-                    }
-                    TmaOperation::ReplaceGlobalDim => ("global_dim", "u32", true, false),
-                    TmaOperation::ReplaceGlobalStride => {
-                        ("global_stride", "u64", true, false)
-                    }
-                    TmaOperation::ReplaceInterleaveLayout => {
-                        ("interleave_layout", "u32", false, true)
-                    }
-                    TmaOperation::ReplaceRank => ("rank", "u32", false, false),
-                    TmaOperation::ReplaceSwizzleAtomicity => {
-                        ("swizzle_atomicity", "u32", false, true)
-                    }
-                    TmaOperation::ReplaceSwizzleMode => {
-                        ("swizzle_mode", "u32", false, true)
-                    }
-                    _ => unreachable!("TMA tensor-map replace operation was matched"),
-                };
-                writeln!(
-                    output,
-                    "        convert_tensormap_replace(ctx, rewriter, self.get_operation(), operands_info, {:?}, {field:?}, {value_kind:?}, {ordinal}, {immediate})",
-                    record.resolved_llvm_identifier()
-                )
-                .unwrap();
-            }
-            TmaOperation::FenceProxyTensorMapAcquireCluster
-            | TmaOperation::FenceProxyTensorMapAcquireCta
-            | TmaOperation::FenceProxyTensorMapAcquireGpu
-            | TmaOperation::FenceProxyTensorMapAcquireSystem
-            | TmaOperation::FenceProxyTensorMapReleaseCluster
-            | TmaOperation::FenceProxyTensorMapReleaseCta
-            | TmaOperation::FenceProxyTensorMapReleaseGpu
-            | TmaOperation::FenceProxyTensorMapReleaseSystem => {
-                let (acquire, scope) = match operation {
-                    TmaOperation::FenceProxyTensorMapAcquireCluster => (true, "cluster"),
-                    TmaOperation::FenceProxyTensorMapAcquireCta => (true, "cta"),
-                    TmaOperation::FenceProxyTensorMapAcquireGpu => (true, "gpu"),
-                    TmaOperation::FenceProxyTensorMapAcquireSystem => (true, "sys"),
-                    TmaOperation::FenceProxyTensorMapReleaseCluster => (false, "cluster"),
-                    TmaOperation::FenceProxyTensorMapReleaseCta => (false, "cta"),
-                    TmaOperation::FenceProxyTensorMapReleaseGpu => (false, "gpu"),
-                    TmaOperation::FenceProxyTensorMapReleaseSystem => (false, "sys"),
-                    _ => unreachable!("TMA tensor-map fence operation was matched"),
-                };
-                writeln!(
-                    output,
-                    "        convert_tensormap_fence(ctx, rewriter, self.get_operation(), operands_info, {:?}, {acquire}, {scope:?})",
-                    record.resolved_llvm_identifier()
-                )
-                .unwrap();
-            }
-        }
-        output.push_str("    }\n}\n\n");
-    }
-    for record in tcgen05_non_mma_intrinsics(catalog) {
-        let operation = record.tcgen05.as_ref().unwrap().operation;
-        let (template, constraints, result_count) = tcgen05_inline_asm(record);
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
-        );
-        if let Some(count) = result_count {
-            let integer_results = operation == Tcgen05Operation::Ld;
-            writeln!(
-                output,
-                "        convert_generated_tcgen05_load(ctx, rewriter, self.get_operation(), {}, {count}, {integer_results}, {template:?}, {constraints:?})",
-                record.dialect.operands.len()
-            )
-            .unwrap();
-        } else {
-            writeln!(
-                output,
-                "        convert_generated_tcgen05_void(ctx, rewriter, self.get_operation(), {}, {template:?}, {constraints:?})",
-                record.dialect.operands.len()
-            )
-            .unwrap();
-        }
-        output.push_str("    }\n}\n\n");
-    }
-    if tcgen05_mma_intrinsics(catalog).next().is_some() {
-        output.push_str(
-            r#"#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05MmaOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let form = self
-            .get_attr_nvvm_tcgen05_mma_form(ctx)
-            .as_deref()
-            .cloned();
-        let kind = self
-            .get_attr_nvvm_tcgen05_mma_kind(ctx)
-            .as_deref()
-            .cloned();
-        let cta_group = self
-            .get_attr_nvvm_tcgen05_mma_cta_group(ctx)
-            .as_deref()
-            .cloned();
-        let collector_a = self
-            .get_attr_nvvm_tcgen05_mma_collector_a(ctx)
-            .as_deref()
-            .cloned();
-        let b_buffer = self
-            .get_attr_nvvm_tcgen05_mma_b_buffer(ctx)
-            .as_deref()
-            .cloned();
-        let b_usage = self
-            .get_attr_nvvm_tcgen05_mma_b_usage(ctx)
-            .as_deref()
-            .cloned();
-        let kind = match kind {
-            Some(Tcgen05MmaKindAttr::F16) => "f16",
-            Some(Tcgen05MmaKindAttr::Tf32) => "tf32",
-            Some(Tcgen05MmaKindAttr::F8f6f4) => "f8f6f4",
-            Some(Tcgen05MmaKindAttr::I8) => "i8",
-            None => return pliron::input_err!(
-                op.deref(ctx).loc(),
-                "nvvm.tcgen05_mma requires a kind",
-            ),
-        };
-        let (prefix, a, metadata, zero_mask, constraints, arity, base, ashift) =
-            match form {
-                Some(Tcgen05MmaFormAttr::Shared) =>
-                    ("tcgen05.mma", "$1", None, None, "r,l,l,r,r,~{memory}", 5, true, false),
-                Some(Tcgen05MmaFormAttr::Tensor) =>
-                    ("tcgen05.mma", "[$1]", None, None, "r,r,l,r,r,~{memory}", 5, true, false),
-                Some(Tcgen05MmaFormAttr::TensorAshift) =>
-                    ("tcgen05.mma", "[$1]", None, None, "r,r,l,r,r,~{memory}", 5, true, true),
-                Some(Tcgen05MmaFormAttr::SpShared) =>
-                    ("tcgen05.mma.sp", "$1", Some("$5"), None, "r,l,l,r,r,r,~{memory}", 6, true, false),
-                Some(Tcgen05MmaFormAttr::SpTensor) =>
-                    ("tcgen05.mma.sp", "[$1]", Some("$5"), None, "r,r,l,r,r,r,~{memory}", 6, true, false),
-                Some(Tcgen05MmaFormAttr::SpTensorAshift) =>
-                    ("tcgen05.mma.sp", "[$1]", Some("$5"), None, "r,r,l,r,r,r,~{memory}", 6, true, true),
-                Some(Tcgen05MmaFormAttr::WsShared) =>
-                    ("tcgen05.mma.ws", "$1", None, None, "r,l,l,r,r,~{memory}", 5, false, false),
-                Some(Tcgen05MmaFormAttr::WsSharedZeroColMask) =>
-                    ("tcgen05.mma.ws", "$1", None, Some("$5"), "r,l,l,r,r,l,~{memory}", 6, false, false),
-                Some(Tcgen05MmaFormAttr::WsSpShared) =>
-                    ("tcgen05.mma.ws.sp", "$1", Some("$5"), None, "r,l,l,r,r,r,~{memory}", 6, false, false),
-                Some(Tcgen05MmaFormAttr::WsSpSharedZeroColMask) =>
-                    ("tcgen05.mma.ws.sp", "$1", Some("$5"), Some("$6"), "r,l,l,r,r,r,l,~{memory}", 7, false, false),
-                Some(Tcgen05MmaFormAttr::WsSpTensor) =>
-                    ("tcgen05.mma.ws.sp", "[$1]", Some("$5"), None, "r,r,l,r,r,r,~{memory}", 6, false, false),
-                Some(Tcgen05MmaFormAttr::WsSpTensorZeroColMask) =>
-                    ("tcgen05.mma.ws.sp", "[$1]", Some("$5"), Some("$6"), "r,r,l,r,r,r,l,~{memory}", 7, false, false),
-                Some(Tcgen05MmaFormAttr::WsTensor) =>
-                    ("tcgen05.mma.ws", "[$1]", None, None, "r,r,l,r,r,~{memory}", 5, false, false),
-                Some(Tcgen05MmaFormAttr::WsTensorZeroColMask) =>
-                    ("tcgen05.mma.ws", "[$1]", None, Some("$5"), "r,r,l,r,r,l,~{memory}", 6, false, false),
-                None => return pliron::input_err!(
-                    op.deref(ctx).loc(),
-                    "nvvm.tcgen05_mma requires a form",
-                ),
-            };
-
-        let selector = if base {
-            let group = match cta_group {
-                Some(Tcgen05MmaCtaGroupAttr::Cg1) => 1,
-                Some(Tcgen05MmaCtaGroupAttr::Cg2) => 2,
-                None => return pliron::input_err!(
-                    op.deref(ctx).loc(),
-                    "base tcgen05 MMA requires a CTA-group selector",
-                ),
-            };
-            let usage = match collector_a {
-                Some(Tcgen05MmaCollectorAAttr::Discard) => "discard",
-                Some(Tcgen05MmaCollectorAAttr::LastUse) => "lastuse",
-                Some(Tcgen05MmaCollectorAAttr::Fill) if !ashift => "fill",
-                Some(Tcgen05MmaCollectorAAttr::Use) if !ashift => "use",
-                _ => return pliron::input_err!(
-                    op.deref(ctx).loc(),
-                    "tcgen05 MMA collector-A selector has no generated recipe",
-                ),
-            };
-            format!(
-                ".cta_group::{group}.kind::{kind}.collector::a::{usage}{}",
-                if ashift { ".ashift" } else { "" },
-            )
-        } else {
-            let buffer = match b_buffer {
-                Some(Tcgen05MmaBBufferAttr::B0) => 0,
-                Some(Tcgen05MmaBBufferAttr::B1) => 1,
-                Some(Tcgen05MmaBBufferAttr::B2) => 2,
-                Some(Tcgen05MmaBBufferAttr::B3) => 3,
-                None => return pliron::input_err!(
-                    op.deref(ctx).loc(),
-                    "warp-specialized tcgen05 MMA requires a B-buffer selector",
-                ),
-            };
-            let usage = match b_usage {
-                Some(Tcgen05MmaBUsageAttr::Discard) => "discard",
-                Some(Tcgen05MmaBUsageAttr::LastUse) => "lastuse",
-                Some(Tcgen05MmaBUsageAttr::Fill) => "fill",
-                Some(Tcgen05MmaBUsageAttr::Use) => "use",
-                None => return pliron::input_err!(
-                    op.deref(ctx).loc(),
-                    "warp-specialized tcgen05 MMA requires a B-usage selector",
-                ),
-            };
-            format!(
-                ".cta_group::1.kind::{kind}.collector::b{buffer}::{usage}"
-            )
-        };
-
-        let mut operands = format!("[$0], {a}, $2");
-        if let Some(metadata) = metadata {
-            operands.push_str(&format!(", [{metadata}]"));
-        }
-        operands.push_str(", $3, %enable_pred");
-        if let Some(zero_mask) = zero_mask {
-            operands.push_str(&format!(", {zero_mask}"));
-        }
-        let template = format!(
-            "{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; {prefix}{selector} {operands}; }}"
-        );
-        convert_generated_tcgen05_void(
-            ctx, rewriter, op, arity, &template, constraints,
-        )
-    }
-}
-
-"#,
-        );
-    }
-    for record in debug_controls(catalog) {
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        output.push_str(
-            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        let void_ty = llvm_types::VoidType::get(ctx);\n",
-        );
-        match record.debug_control.as_ref().unwrap().operation {
-            DebugControlOperation::Trap => output.push_str(
-                "        inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], \"trap;\", \"\");\n",
-            ),
-            DebugControlOperation::Breakpoint => output.push_str(
-                "        inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], \"brkpt;\", \"\");\n",
-            ),
-            DebugControlOperation::Pmevent => output.push_str(
-                "        let Some(event_id) = self.event_id(ctx) else {\n\
-                     return pliron::input_err!(\n\
-                         op.deref(ctx).loc(),\n\
-                         \"nvvm.pmevent requires a u32 event ID in 0..=15\",\n\
-                     );\n\
-                 };\n\
-                 let template = format!(\"pmevent {event_id};\");\n\
-                 inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], &template, \"\");\n",
-            ),
-        }
-        output.push_str("        rewriter.erase_operation(ctx, op);\n        Ok(())\n    }\n}\n\n");
-    }
-    for record in sync_intrinsics(catalog) {
-        writeln!(
-            output,
-            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
-            record.dialect.op_type
-        )
-        .unwrap();
-        if record.id == "sync_threads" {
-            output.push_str(
-                "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        let void_ty = llvm_types::VoidType::get(ctx);\n        match context::lowering_options(ctx).intrinsic_backend {\n            IntrinsicBackend::LlvmNvptx => {\n                let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);\n                let barrier_id = create_i32_const(ctx, rewriter, 0);\n                let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![i32_ty.into()], false);\n",
-            );
-            writeln!(
-                output,
-                "                call_intrinsic(ctx, rewriter, op, {:?}, function_ty, vec![barrier_id])?;",
-                record.llvm_identifier()
-            )
-            .unwrap();
-            output.push_str(
-                "            }\n            IntrinsicBackend::LibNvvm => {\n                inline_asm_convergent(ctx, rewriter, op, void_ty.into(), vec![], \"bar.sync 0;\", \"~{memory}\");\n            }\n        }\n        rewriter.erase_operation(ctx, op);\n        Ok(())\n    }\n}\n\n",
-            );
-        } else {
-            debug_assert!(threadfence_ptx_level(record).is_some());
-            output.push_str(
-                "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        let void_ty = llvm_types::VoidType::get(ctx);\n        let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);\n",
-            );
-            writeln!(
-                output,
-                "        call_intrinsic(ctx, rewriter, op, {:?}, function_ty, vec![])?;",
-                record.llvm_identifier()
-            )
-            .unwrap();
-            output.push_str(
-                "        rewriter.erase_operation(ctx, op);\n        Ok(())\n    }\n}\n\n",
-            );
-        }
-    }
-    output
-}
-
-fn render_collector(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = rust_header(catalog, hash);
-    let abi_namespace = format!("__cuda_oxide_intrinsic_abi_v{}", catalog.intrinsic_abi);
-    output.push_str("//! Generated collector predicates for intrinsic placeholder functions.\n\n");
-    writeln!(
-        output,
-        "pub(crate) const GENERATED_INTRINSIC_ABI: u32 = {};",
-        catalog.intrinsic_abi
-    )
-    .unwrap();
-    writeln!(
-        output,
-        "pub(crate) const GENERATED_INTRINSIC_ABI_NAMESPACE: &str = {abi_namespace:?};"
-    )
-    .unwrap();
-    output.push_str(
-        "pub(crate) const GENERATED_INTRINSIC_CRATES: &[&str] = &[\n    \"cuda_intrinsics\",\n    \"cuda-intrinsics\",\n];\n\npub(crate) const GENERATED_INTRINSIC_CANONICAL_PATHS: &[&str] = &[\n",
-    );
-    for record in &catalog.intrinsics {
-        writeln!(output, "    {:?},", record.rust.canonical_path).unwrap();
-    }
-    output.push_str("];\n\npub(crate) const GENERATED_INTRINSIC_PUBLIC_PATHS: &[&str] = &[\n");
-    for record in &catalog.intrinsics {
-        writeln!(output, "    {:?},", record.rust.public_path).unwrap();
-    }
-    output.push_str("];\n\npub(crate) fn is_generated_intrinsic_crate(crate_name: &str) -> bool {\n    GENERATED_INTRINSIC_CRATES.contains(&crate_name)\n}\n\npub(crate) fn is_generated_intrinsic_canonical_path(path: &str) -> bool {\n    matches!(path,\n");
-    let canonical_paths: Vec<_> = catalog
-        .intrinsics
-        .iter()
-        .map(|record| record.rust.canonical_path.as_str())
-        .collect();
-    render_string_patterns(&mut output, &canonical_paths, "        ");
-    output.push_str("    )\n}\n\npub(crate) fn is_generated_intrinsic_compatibility_path(path: &str) -> bool {\n");
-    let compatibility_paths: Vec<_> = catalog
-        .intrinsics
-        .iter()
-        .flat_map(|record| record.rust.compatibility_paths.iter().map(String::as_str))
-        .collect();
-    if compatibility_paths.is_empty() {
-        output.push_str("    let _ = path;\n    false\n");
-    } else {
-        output.push_str("    matches!(path,\n");
-        render_string_patterns(&mut output, &compatibility_paths, "        ");
-        output.push_str("    )\n");
-    }
-    output.push_str(
-        "}\n\npub(crate) fn is_generated_intrinsic_placeholder(crate_name: &str, path: &str) -> bool {\n    if is_generated_intrinsic_crate(crate_name) {\n        is_generated_intrinsic_canonical_path(path)\n    } else if matches!(crate_name, \"cuda_device\" | \"cuda-device\") {\n        is_generated_intrinsic_compatibility_path(path)\n    } else {\n        false\n    }\n}\n",
-    );
-    output
-}
-
-fn generated_selection_constraints(selection: &CatalogSelection) -> String {
-    let address_space = match selection.constraints.address_space {
-        None => "None",
-        Some(ImportedAddressSpace::Generic) => "Some(GeneratedSelectionAddressSpace::Generic)",
-        Some(ImportedAddressSpace::Shared) => "Some(GeneratedSelectionAddressSpace::Shared)",
-    };
-    let immediate_bindings = selection
-        .constraints
-        .immediate_bindings
-        .iter()
-        .map(|binding| {
-            format!(
-                "GeneratedImmediateBinding {{ argument_index: {}, value: {} }}",
-                binding.argument_index, binding.value
-            )
-        })
-        .collect::<Vec<_>>()
-        .join(", ");
-    format!(
-        "GeneratedSelectionConstraints {{ address_space: {address_space}, immediate_bindings: &[{immediate_bindings}] }}"
-    )
-}
-
-fn generated_selection_alternatives(selections: &[CatalogSelection]) -> String {
-    let mut output = String::from("&[");
-    for selection in selections {
-        write!(
-            output,
-            "GeneratedSelectionAlternative {{ source_record: {:?}, asm: {:?}, predicates: &{:?}, constraints: {} }},",
-            selection.source_record,
-            selection.asm,
-            selection.predicates,
-            generated_selection_constraints(selection),
-        )
-        .unwrap();
-    }
-    output.push(']');
-    output
-}
-
-fn generated_intrinsic_variant(record: &CatalogIntrinsic) -> String {
-    if let Some(mma) = record
-        .tcgen05
-        .as_ref()
-        .and_then(|tcgen05| tcgen05.mma.as_ref())
-    {
-        return format!(
-            "GeneratedIntrinsicVariant::Tcgen05Mma {{ form: GeneratedTcgen05MmaForm::{}, target_selector: GeneratedTcgen05MmaTargetSelector::Kind, compatibility_alias: {} }}",
-            tcgen05_mma_form_name(mma.form),
-            mma.alias.is_some(),
-        );
-    }
-    if let Some(control) = &record.wgmma_control {
-        let mode = match control.mode {
-            WgmmaControlMode::Fence => "GeneratedWgmmaControlMode::Fence",
-            WgmmaControlMode::CommitGroup => "GeneratedWgmmaControlMode::CommitGroup",
-            WgmmaControlMode::WaitGroup => "GeneratedWgmmaControlMode::WaitGroup",
-        };
-        return format!("GeneratedIntrinsicVariant::WgmmaControl {{ mode: {mode} }}");
-    }
-    if let Some(barrier) = &record.cluster_barrier {
-        let mode = match barrier.mode {
-            ClusterBarrierMode::Arrive => "GeneratedClusterBarrierMode::Arrive",
-            ClusterBarrierMode::ArriveAligned => "GeneratedClusterBarrierMode::ArriveAligned",
-            ClusterBarrierMode::ArriveRelaxed => "GeneratedClusterBarrierMode::ArriveRelaxed",
-            ClusterBarrierMode::ArriveRelaxedAligned => {
-                "GeneratedClusterBarrierMode::ArriveRelaxedAligned"
-            }
-            ClusterBarrierMode::Wait => "GeneratedClusterBarrierMode::Wait",
-            ClusterBarrierMode::WaitAligned => "GeneratedClusterBarrierMode::WaitAligned",
-        };
-        return format!("GeneratedIntrinsicVariant::ClusterBarrier {{ mode: {mode} }}");
-    }
-    if let Some(prmt) = &record.prmt {
-        let mode = match prmt.mode {
-            PrmtMode::Generic => "GeneratedPrmtMode::Generic",
-            PrmtMode::F4e => "GeneratedPrmtMode::F4e",
-            PrmtMode::B4e => "GeneratedPrmtMode::B4e",
-            PrmtMode::Rc8 => "GeneratedPrmtMode::Rc8",
-            PrmtMode::Ecl => "GeneratedPrmtMode::Ecl",
-            PrmtMode::Ecr => "GeneratedPrmtMode::Ecr",
-            PrmtMode::Rc16 => "GeneratedPrmtMode::Rc16",
-        };
-        return format!("GeneratedIntrinsicVariant::Prmt {{ mode: {mode} }}");
-    }
-    if let Some(packed) = &record.packed_atomic {
-        let format = match packed.format {
-            PackedAtomicFormat::F16x2 => "GeneratedPackedAtomicFormat::F16x2",
-            PackedAtomicFormat::Bf16x2 => "GeneratedPackedAtomicFormat::Bf16x2",
-        };
-        return format!("GeneratedIntrinsicVariant::PackedAtomic {{ format: {format} }}");
-    }
-    if let Some(mma) = &record.register_mma {
-        let shape = match mma.shape {
-            RegisterMmaShape::M8n8k4 => "GeneratedRegisterMmaShape::M8n8k4",
-            RegisterMmaShape::M8n8k16 => "GeneratedRegisterMmaShape::M8n8k16",
-            RegisterMmaShape::M8n8k32 => "GeneratedRegisterMmaShape::M8n8k32",
-            RegisterMmaShape::M8n8k128 => "GeneratedRegisterMmaShape::M8n8k128",
-            RegisterMmaShape::M16n8k4 => "GeneratedRegisterMmaShape::M16n8k4",
-            RegisterMmaShape::M16n8k8 => "GeneratedRegisterMmaShape::M16n8k8",
-            RegisterMmaShape::M16n8k16 => "GeneratedRegisterMmaShape::M16n8k16",
-            RegisterMmaShape::M16n8k32 => "GeneratedRegisterMmaShape::M16n8k32",
-            RegisterMmaShape::M16n8k64 => "GeneratedRegisterMmaShape::M16n8k64",
-            RegisterMmaShape::M16n8k128 => "GeneratedRegisterMmaShape::M16n8k128",
-            RegisterMmaShape::M16n8k256 => "GeneratedRegisterMmaShape::M16n8k256",
-        };
-        let operation = match mma.operation {
-            RegisterMmaOperation::Multiply => "GeneratedRegisterMmaOperation::Multiply",
-            RegisterMmaOperation::AndPopc => "GeneratedRegisterMmaOperation::AndPopc",
-            RegisterMmaOperation::XorPopc => "GeneratedRegisterMmaOperation::XorPopc",
-        };
-        let kind = match register_mma_effective_kind(record) {
-            RegisterMmaKind::Standard => "GeneratedRegisterMmaKind::Standard",
-            RegisterMmaKind::F8f6f4 => "GeneratedRegisterMmaKind::F8f6f4",
-            RegisterMmaKind::Mxf8f6f4 => "GeneratedRegisterMmaKind::Mxf8f6f4",
-        };
-        let accumulator = match mma.accumulator {
-            RegisterMmaAccumulator::F16 => "GeneratedRegisterMmaAccumulator::F16",
-            RegisterMmaAccumulator::F32 => "GeneratedRegisterMmaAccumulator::F32",
-            RegisterMmaAccumulator::F64 => "GeneratedRegisterMmaAccumulator::F64",
-            RegisterMmaAccumulator::S32 => "GeneratedRegisterMmaAccumulator::S32",
-        };
-        let element = |element| match element {
-            RegisterMmaElement::Bf16 => "GeneratedRegisterMmaElement::Bf16",
-            RegisterMmaElement::E2m1 => "GeneratedRegisterMmaElement::E2m1",
-            RegisterMmaElement::E2m3 => "GeneratedRegisterMmaElement::E2m3",
-            RegisterMmaElement::E3m2 => "GeneratedRegisterMmaElement::E3m2",
-            RegisterMmaElement::E4m3 => "GeneratedRegisterMmaElement::E4m3",
-            RegisterMmaElement::E5m2 => "GeneratedRegisterMmaElement::E5m2",
-            RegisterMmaElement::F16 => "GeneratedRegisterMmaElement::F16",
-            RegisterMmaElement::Tf32 => "GeneratedRegisterMmaElement::Tf32",
-            RegisterMmaElement::F64 => "GeneratedRegisterMmaElement::F64",
-            RegisterMmaElement::B1 => "GeneratedRegisterMmaElement::B1",
-            RegisterMmaElement::S4 => "GeneratedRegisterMmaElement::S4",
-            RegisterMmaElement::U4 => "GeneratedRegisterMmaElement::U4",
-            RegisterMmaElement::S8 => "GeneratedRegisterMmaElement::S8",
-            RegisterMmaElement::U8 => "GeneratedRegisterMmaElement::U8",
-        };
-        let layout = |layout| match layout {
-            RegisterMmaLayout::Row => "GeneratedRegisterMmaLayout::Row",
-            RegisterMmaLayout::Col => "GeneratedRegisterMmaLayout::Col",
-        };
-        let overflow = match mma.overflow {
-            RegisterMmaOverflow::NotApplicable => "GeneratedRegisterMmaOverflow::NotApplicable",
-            RegisterMmaOverflow::Wrapping => "GeneratedRegisterMmaOverflow::Wrapping",
-            RegisterMmaOverflow::Satfinite => "GeneratedRegisterMmaOverflow::Satfinite",
-        };
-        return format!(
-            "GeneratedIntrinsicVariant::RegisterMma {{ shape: {shape}, operation: {operation}, kind: {kind}, accumulator: {accumulator}, a_element: {}, b_element: {}, a_layout: {}, b_layout: {}, overflow: {overflow} }}",
-            element(mma.a_element),
-            element(mma.b_element),
-            layout(mma.a_layout),
-            layout(mma.b_layout),
-        );
-    }
-    if let Some(mma) = &record.sparse_mma {
-        let shape = match mma.shape {
-            SparseMmaShape::M16n8k32 => "GeneratedSparseMmaShape::M16n8k32",
-            SparseMmaShape::M16n8k64 => "GeneratedSparseMmaShape::M16n8k64",
-            SparseMmaShape::M16n8k128 => "GeneratedSparseMmaShape::M16n8k128",
-        };
-        let accumulator = match mma.accumulator {
-            SparseMmaAccumulator::F16 => "GeneratedSparseMmaAccumulator::F16",
-            SparseMmaAccumulator::F32 => "GeneratedSparseMmaAccumulator::F32",
-            SparseMmaAccumulator::S32 => "GeneratedSparseMmaAccumulator::S32",
-        };
-        let element = |element| match element {
-            SparseMmaElement::E2m1 => "GeneratedSparseMmaElement::E2m1",
-            SparseMmaElement::E2m3 => "GeneratedSparseMmaElement::E2m3",
-            SparseMmaElement::E3m2 => "GeneratedSparseMmaElement::E3m2",
-            SparseMmaElement::E4m3 => "GeneratedSparseMmaElement::E4m3",
-            SparseMmaElement::E5m2 => "GeneratedSparseMmaElement::E5m2",
-            SparseMmaElement::S4 => "GeneratedSparseMmaElement::S4",
-            SparseMmaElement::U4 => "GeneratedSparseMmaElement::U4",
-            SparseMmaElement::S8 => "GeneratedSparseMmaElement::S8",
-            SparseMmaElement::U8 => "GeneratedSparseMmaElement::U8",
-        };
-        let layout = |layout| match layout {
-            SparseMmaLayout::Row => "GeneratedSparseMmaLayout::Row",
-            SparseMmaLayout::Col => "GeneratedSparseMmaLayout::Col",
-        };
-        let overflow = match mma.overflow {
-            SparseMmaOverflow::NotApplicable => "GeneratedSparseMmaOverflow::NotApplicable",
-            SparseMmaOverflow::Wrapping => "GeneratedSparseMmaOverflow::Wrapping",
-            SparseMmaOverflow::Satfinite => "GeneratedSparseMmaOverflow::Satfinite",
-        };
-        let metadata = match mma.metadata {
-            SparseMmaMetadata::Standard => "GeneratedSparseMmaMetadata::Standard",
-            SparseMmaMetadata::Ordered => "GeneratedSparseMmaMetadata::Ordered",
-        };
-        let selector = match mma.selector {
-            SparseMmaSelector::ImmediateZeroOrOne => {
-                "GeneratedSparseMmaSelector::ImmediateZeroOrOne"
-            }
-            SparseMmaSelector::ImmediateZero => "GeneratedSparseMmaSelector::ImmediateZero",
-        };
-        return format!(
-            "GeneratedIntrinsicVariant::SparseMma {{ shape: {shape}, accumulator: {accumulator}, a_element: {}, b_element: {}, a_layout: {}, b_layout: {}, overflow: {overflow}, metadata: {metadata}, selector: {selector} }}",
-            element(mma.a_element),
-            element(mma.b_element),
-            layout(mma.a_layout),
-            layout(mma.b_layout),
-        );
-    }
-    if let Some(arithmetic) = &record.scalar_arithmetic {
-        let format = match arithmetic.format {
-            ScalarArithmeticFormat::F32 => "GeneratedScalarArithmeticFormat::F32",
-            ScalarArithmeticFormat::F64 => "GeneratedScalarArithmeticFormat::F64",
-        };
-        let operation = match arithmetic.operation {
-            ScalarArithmeticOperation::Mul => "GeneratedScalarArithmeticOperation::Mul",
-            ScalarArithmeticOperation::Div => "GeneratedScalarArithmeticOperation::Div",
-            ScalarArithmeticOperation::Fma => "GeneratedScalarArithmeticOperation::Fma",
-            ScalarArithmeticOperation::Add => "GeneratedScalarArithmeticOperation::Add",
-        };
-        let rounding = match arithmetic.rounding {
-            ScalarArithmeticRounding::Rn => "GeneratedScalarArithmeticRounding::Rn",
-            ScalarArithmeticRounding::Rz => "GeneratedScalarArithmeticRounding::Rz",
-            ScalarArithmeticRounding::Rm => "GeneratedScalarArithmeticRounding::Rm",
-            ScalarArithmeticRounding::Rp => "GeneratedScalarArithmeticRounding::Rp",
-        };
-        let subnormal = match arithmetic.subnormal {
-            ScalarArithmeticSubnormal::Preserve => "GeneratedScalarArithmeticSubnormal::Preserve",
-            ScalarArithmeticSubnormal::Ftz => "GeneratedScalarArithmeticSubnormal::Ftz",
-        };
-        let saturation = match arithmetic.saturation {
-            ScalarArithmeticSaturation::None => "GeneratedScalarArithmeticSaturation::None",
-            ScalarArithmeticSaturation::Sat => "GeneratedScalarArithmeticSaturation::Sat",
-        };
-        return format!(
-            "GeneratedIntrinsicVariant::ScalarArithmetic {{ format: {format}, operation: {operation}, rounding: {rounding}, subnormal: {subnormal}, saturation: {saturation} }}"
-        );
-    }
-    if let Some(minmax) = &record.extended_minmax {
-        let format = match minmax.format {
-            ExtendedMinMaxFormat::F32 => "GeneratedExtendedMinMaxFormat::F32",
-            ExtendedMinMaxFormat::F16 => "GeneratedExtendedMinMaxFormat::F16",
-            ExtendedMinMaxFormat::Bf16 => "GeneratedExtendedMinMaxFormat::Bf16",
-            ExtendedMinMaxFormat::F16x2 => "GeneratedExtendedMinMaxFormat::F16x2",
-            ExtendedMinMaxFormat::Bf16x2 => "GeneratedExtendedMinMaxFormat::Bf16x2",
-        };
-        let operation = match minmax.operation {
-            ExtendedMinMaxOperation::Min => "GeneratedExtendedMinMaxOperation::Min",
-            ExtendedMinMaxOperation::Max => "GeneratedExtendedMinMaxOperation::Max",
-        };
-        let subnormal = match minmax.subnormal {
-            ExtendedMinMaxSubnormal::Preserve => "GeneratedExtendedMinMaxSubnormal::Preserve",
-            ExtendedMinMaxSubnormal::Ftz => "GeneratedExtendedMinMaxSubnormal::Ftz",
-        };
-        let nan = match minmax.nan {
-            ExtendedMinMaxNan::Number => "GeneratedExtendedMinMaxNan::Number",
-            ExtendedMinMaxNan::Nan => "GeneratedExtendedMinMaxNan::Nan",
-        };
-        return format!(
-            "GeneratedIntrinsicVariant::ExtendedMinMax {{ format: {format}, operation: {operation}, subnormal: {subnormal}, nan: {nan}, xorsign_abs: {} }}",
-            minmax.xorsign_abs
-        );
-    }
-    if let Some(conversion) = &record.scalar_conversion {
-        let rounding = match conversion.rounding {
-            ScalarConversionRounding::NearestAway => {
-                "GeneratedScalarConversionRounding::NearestAway"
-            }
-            ScalarConversionRounding::NearestEven => {
-                "GeneratedScalarConversionRounding::NearestEven"
-            }
-            ScalarConversionRounding::TowardZero => "GeneratedScalarConversionRounding::TowardZero",
-        };
-        let saturation = match conversion.saturation {
-            ScalarConversionSaturation::None => "GeneratedScalarConversionSaturation::None",
-            ScalarConversionSaturation::Relu => "GeneratedScalarConversionSaturation::Relu",
-            ScalarConversionSaturation::Satfinite => {
-                "GeneratedScalarConversionSaturation::Satfinite"
-            }
-            ScalarConversionSaturation::ReluSatfinite => {
-                "GeneratedScalarConversionSaturation::ReluSatfinite"
-            }
-        };
-        return format!(
-            "GeneratedIntrinsicVariant::ScalarConversion {{ rounding: {rounding}, saturation: {saturation} }}"
-        );
-    }
-    let Some(ldmatrix) = &record.ldmatrix else {
-        return "GeneratedIntrinsicVariant::Scalar".to_owned();
-    };
-    let variant = &ldmatrix.variant;
-    let shape = match variant.shape {
-        LdmatrixShape::M8n8 => "GeneratedLdmatrixShape::M8n8",
-        LdmatrixShape::M8n16 => "GeneratedLdmatrixShape::M8n16",
-        LdmatrixShape::M16n16 => "GeneratedLdmatrixShape::M16n16",
-    };
-    let multiplicity = match variant.multiplicity {
-        LdmatrixMultiplicity::X1 => "GeneratedLdmatrixMultiplicity::X1",
-        LdmatrixMultiplicity::X2 => "GeneratedLdmatrixMultiplicity::X2",
-        LdmatrixMultiplicity::X4 => "GeneratedLdmatrixMultiplicity::X4",
-    };
-    let layout = match variant.layout {
-        LdmatrixLayout::Normal => "GeneratedLdmatrixLayout::Normal",
-        LdmatrixLayout::Transposed => "GeneratedLdmatrixLayout::Transposed",
-    };
-    let element = match variant.element {
-        LdmatrixElement::B16 => "GeneratedLdmatrixElement::B16",
-        LdmatrixElement::B8 => "GeneratedLdmatrixElement::B8",
-        LdmatrixElement::B8x16B4x16P64 => "GeneratedLdmatrixElement::B8x16B4x16P64",
-        LdmatrixElement::B8x16B6x16P32 => "GeneratedLdmatrixElement::B8x16B6x16P32",
-    };
-    format!(
-        "GeneratedIntrinsicVariant::Ldmatrix {{ shape: {shape}, multiplicity: {multiplicity}, layout: {layout}, element: {element} }}"
-    )
-}
-
-fn generated_backend_requirements(record: &CatalogIntrinsic) -> String {
-    let requirements = record
-        .backend_lowerings
-        .iter()
-        .map(|lowering| {
-            let backend = match lowering.backend {
-                IntrinsicBackend::LlvmNvptx => "GeneratedIntrinsicBackend::LlvmNvptx",
-                IntrinsicBackend::LibNvvm => "GeneratedIntrinsicBackend::LibNvvm",
-            };
-            format!(
-                "GeneratedBackendRequirement {{ backend: {backend}, requirement: GeneratedTargetRequirement {{ minimum_ptx: GeneratedPtxVersion::from_encoded({}), hardware: {} }} }}",
-                lowering.target.minimum_ptx.encoded(),
-                generated_hardware_target(&lowering.target.hardware),
-            )
-        })
-        .collect::<Vec<_>>()
-        .join(", ");
-    format!("&[{requirements}]")
-}
-
-fn replace_exact_render_fragment(output: &mut String, fragment: &str, replacement: &str) {
-    assert_eq!(
-        output.matches(fragment).count(),
-        1,
-        "render fragment must occur exactly once"
-    );
-    let start = output.find(fragment).expect("checked render fragment");
-    output.replace_range(start..start + fragment.len(), replacement);
-}
-
-fn render_targets(catalog: &CatalogFile, hash: &str) -> String {
-    let mut records = catalog.intrinsics.iter().collect::<Vec<_>>();
-    records.sort_by(|left, right| left.rust.abi_id.cmp(&right.rust.abi_id));
-    let mut output = rust_header(catalog, hash);
-    output.push_str(
-        "//! Generated target requirements and separately imported LLVM/selection facts.\n\npub const GENERATED_INTRINSIC_MARKER_ATTR: &str = \"cuda_oxide_intrinsic_marker\";\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]\npub struct GeneratedPtxVersion(u16);\nimpl GeneratedPtxVersion {\n    pub const fn from_encoded(encoded: u16) -> Self { Self(encoded) }\n    pub const fn encoded(self) -> u16 { self.0 }\n    pub const fn major(self) -> u16 { self.0 / 10 }\n    pub const fn minor(self) -> u16 { self.0 % 10 }\n}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedHardwareAlternative { MinimumSm(u16), ExactArchitecture(u16), FamilyTarget(u16) }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetSelectorBinding { pub name: &'static str, pub value: &'static str }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetAlternative { pub minimum_ptx: GeneratedPtxVersion, pub hardware: GeneratedHardwareAlternative }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedHardwareTarget { All, AnyOf(&'static [GeneratedHardwareAlternative]), TargetMatrix { selectors: &'static [GeneratedTargetSelectorBinding], alternatives: &'static [GeneratedTargetAlternative] } }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetRequirement { pub minimum_ptx: GeneratedPtxVersion, pub hardware: GeneratedHardwareTarget }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicBackend { LlvmNvptx, LibNvvm }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedBackendRequirement { pub backend: GeneratedIntrinsicBackend, pub requirement: GeneratedTargetRequirement }\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSelectionAddressSpace { Generic, Shared }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedImmediateBinding { pub argument_index: usize, pub value: i64 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedSelectionConstraints { pub address_space: Option<GeneratedSelectionAddressSpace>, pub immediate_bindings: &'static [GeneratedImmediateBinding] }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedSelectionAlternative { pub source_record: &'static str, pub asm: &'static str, pub predicates: &'static [&'static str], pub constraints: GeneratedSelectionConstraints }\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicRange { pub lower: &'static str, pub upper_exclusive: &'static str }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedLlvmFacts { pub properties: &'static [&'static str], pub result_no_undef: bool, pub result_range: Option<GeneratedIntrinsicRange> }\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedLdmatrixShape { M8n8 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedLdmatrixMultiplicity { X1, X2, X4 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedLdmatrixLayout { Normal, Transposed }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedPackedAtomicFormat { F16x2, Bf16x2 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaShape { M8n8k4, M16n8k8, M16n8k16, M16n8k32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaAccumulator { F32, F64, S32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaElement { Bf16, F16, Tf32, F64, S8, U8 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaLayout { Row, Col }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaOverflow { NotApplicable, Wrapping, Satfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {\n    Scalar,\n    Ldmatrix { shape: GeneratedLdmatrixShape, multiplicity: GeneratedLdmatrixMultiplicity, layout: GeneratedLdmatrixLayout },\n    PackedAtomic { format: GeneratedPackedAtomicFormat },\n    RegisterMma { shape: GeneratedRegisterMmaShape, accumulator: GeneratedRegisterMmaAccumulator, a_element: GeneratedRegisterMmaElement, b_element: GeneratedRegisterMmaElement, a_layout: GeneratedRegisterMmaLayout, b_layout: GeneratedRegisterMmaLayout, overflow: GeneratedRegisterMmaOverflow },\n}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicTarget {\n    pub marker: &'static str,\n    pub id: &'static str,\n    pub abi_id: &'static str,\n    pub dialect_op: &'static str,\n    pub variant: GeneratedIntrinsicVariant,\n    pub requirement: GeneratedTargetRequirement,\n    pub backend_requirements: &'static [GeneratedBackendRequirement],\n    pub selections: &'static [GeneratedSelectionAlternative],\n    pub llvm: Option<GeneratedLlvmFacts>,\n}\n\nimpl GeneratedIntrinsicTarget {\n    pub fn requirement_for_backend(&self, backend: GeneratedIntrinsicBackend) -> GeneratedTargetRequirement {\n        self.backend_requirements.iter().find(|entry| entry.backend == backend).map(|entry| entry.requirement).unwrap_or(self.requirement)\n    }\n}\n\npub const GENERATED_INTRINSIC_TARGETS: &[GeneratedIntrinsicTarget] = &[\n",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetAlternative { pub minimum_ptx: GeneratedPtxVersion, pub hardware: GeneratedHardwareAlternative }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedHardwareTarget { All, AnyOf(&'static [GeneratedHardwareAlternative]), TargetMatrix { selectors: &'static [GeneratedTargetSelectorBinding], alternatives: &'static [GeneratedTargetAlternative] } }",
-        "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetAlternative { pub minimum_ptx: GeneratedPtxVersion, pub hardware: GeneratedHardwareAlternative }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetContract { pub selectors: &'static [GeneratedTargetSelectorBinding], pub alternatives: &'static [GeneratedTargetAlternative] }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedHardwareTarget { All, AnyOf(&'static [GeneratedHardwareAlternative]), TargetMatrix { contracts: &'static [GeneratedTargetContract] } }",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "impl GeneratedIntrinsicTarget {\n    pub fn requirement_for_backend(&self, backend: GeneratedIntrinsicBackend) -> GeneratedTargetRequirement {\n        self.backend_requirements.iter().find(|entry| entry.backend == backend).map(|entry| entry.requirement).unwrap_or(self.requirement)\n    }\n}",
-        r#"impl GeneratedHardwareTarget {
-    pub fn contract_for_selector(
-        self,
-        name: &str,
-        value: &str,
-    ) -> Option<&'static GeneratedTargetContract> {
-        let Self::TargetMatrix { contracts } = self else { return None; };
-        let mut matching = contracts.iter().filter(|contract| {
-            matches!(contract.selectors, [binding] if binding.name == name && binding.value == value)
-        });
-        let contract = matching.next()?;
-        if matching.next().is_some() { None } else { Some(contract) }
-    }
-}
-
-impl GeneratedIntrinsicTarget {
-    pub fn requirement_for_backend(&self, backend: GeneratedIntrinsicBackend) -> GeneratedTargetRequirement {
-        self.backend_requirements.iter().find(|entry| entry.backend == backend).map(|entry| entry.requirement).unwrap_or(self.requirement)
-    }
-
-    pub fn target_contract_for_backend_selector(
-        &self,
-        backend: GeneratedIntrinsicBackend,
-        name: &str,
-        value: &str,
-    ) -> Option<&'static GeneratedTargetContract> {
-        self.requirement_for_backend(backend).hardware.contract_for_selector(name, value)
-    }
-}"#,
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "GeneratedLdmatrixShape { M8n8 }",
-        "GeneratedLdmatrixShape { M8n8, M8n16, M16n16 }",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "pub enum GeneratedPackedAtomicFormat { F16x2, Bf16x2 }",
-        "pub enum GeneratedLdmatrixElement { B16, B8, B8x16B4x16P64, B8x16B6x16P32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedPackedAtomicFormat { F16x2, Bf16x2 }",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "Ldmatrix { shape: GeneratedLdmatrixShape, multiplicity: GeneratedLdmatrixMultiplicity, layout: GeneratedLdmatrixLayout }",
-        "Ldmatrix { shape: GeneratedLdmatrixShape, multiplicity: GeneratedLdmatrixMultiplicity, layout: GeneratedLdmatrixLayout, element: GeneratedLdmatrixElement }",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "GeneratedRegisterMmaShape { M8n8k4, M16n8k8, M16n8k16, M16n8k32 }",
-        "GeneratedRegisterMmaShape { M8n8k4, M8n8k16, M8n8k32, M8n8k128, M16n8k4, M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128, M16n8k256 }",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "GeneratedRegisterMmaElement { Bf16, F16, Tf32, F64, S8, U8 }",
-        "GeneratedRegisterMmaElement { Bf16, E2m1, E2m3, E3m2, E4m3, E5m2, F16, Tf32, F64, B1, S4, U4, S8, U8 }",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "pub enum GeneratedRegisterMmaAccumulator { F32, F64, S32 }",
-        "pub enum GeneratedRegisterMmaOperation { Multiply, AndPopc, XorPopc }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaKind { Standard, F8f6f4, Mxf8f6f4 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaAccumulator { F16, F32, F64, S32 }",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "RegisterMma { shape: GeneratedRegisterMmaShape, accumulator: GeneratedRegisterMmaAccumulator,",
-        "RegisterMma { shape: GeneratedRegisterMmaShape, operation: GeneratedRegisterMmaOperation, kind: GeneratedRegisterMmaKind, accumulator: GeneratedRegisterMmaAccumulator,",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
-        "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaShape { M16n8k32, M16n8k64, M16n8k128 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaAccumulator { F16, F32, S32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaElement { E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaLayout { Row, Col }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaOverflow { NotApplicable, Wrapping, Satfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaMetadata { Standard, Ordered }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaSelector { ImmediateZeroOrOne, ImmediateZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedPrmtMode { Generic, F4e, B4e, Rc8, Ecl, Ecr, Rc16 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedClusterBarrierMode { Arrive, ArriveAligned, ArriveRelaxed, ArriveRelaxedAligned, Wait, WaitAligned }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionRounding { NearestAway, NearestEven, TowardZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionSaturation { None, Relu, Satfinite, ReluSatfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "    RegisterMma { shape: GeneratedRegisterMmaShape, operation: GeneratedRegisterMmaOperation, kind: GeneratedRegisterMmaKind, accumulator: GeneratedRegisterMmaAccumulator, a_element: GeneratedRegisterMmaElement, b_element: GeneratedRegisterMmaElement, a_layout: GeneratedRegisterMmaLayout, b_layout: GeneratedRegisterMmaLayout, overflow: GeneratedRegisterMmaOverflow },\n}",
-        "    RegisterMma { shape: GeneratedRegisterMmaShape, operation: GeneratedRegisterMmaOperation, kind: GeneratedRegisterMmaKind, accumulator: GeneratedRegisterMmaAccumulator, a_element: GeneratedRegisterMmaElement, b_element: GeneratedRegisterMmaElement, a_layout: GeneratedRegisterMmaLayout, b_layout: GeneratedRegisterMmaLayout, overflow: GeneratedRegisterMmaOverflow },\n    SparseMma { shape: GeneratedSparseMmaShape, accumulator: GeneratedSparseMmaAccumulator, a_element: GeneratedSparseMmaElement, b_element: GeneratedSparseMmaElement, a_layout: GeneratedSparseMmaLayout, b_layout: GeneratedSparseMmaLayout, overflow: GeneratedSparseMmaOverflow, metadata: GeneratedSparseMmaMetadata, selector: GeneratedSparseMmaSelector },\n    Prmt { mode: GeneratedPrmtMode },\n    ClusterBarrier { mode: GeneratedClusterBarrierMode },\n    ScalarConversion { rounding: GeneratedScalarConversionRounding, saturation: GeneratedScalarConversionSaturation },\n}",
-    );
-    if wgmma_controls(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
-            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedWgmmaControlMode { Fence, CommitGroup, WaitGroup }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
-        );
-        replace_exact_render_fragment(
-            &mut output,
-            "    ClusterBarrier { mode: GeneratedClusterBarrierMode },\n    ScalarConversion { rounding: GeneratedScalarConversionRounding, saturation: GeneratedScalarConversionSaturation },\n}",
-            "    ClusterBarrier { mode: GeneratedClusterBarrierMode },\n    ScalarConversion { rounding: GeneratedScalarConversionRounding, saturation: GeneratedScalarConversionSaturation },\n    WgmmaControl { mode: GeneratedWgmmaControlMode },\n}",
-        );
-    }
-    if scalar_arithmetics(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
-            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarArithmeticFormat { F32, F64 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarArithmeticOperation { Mul, Div, Fma, Add }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarArithmeticRounding { Rn, Rz, Rm, Rp }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarArithmeticSubnormal { Preserve, Ftz }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarArithmeticSaturation { None, Sat }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
-        );
-        if wgmma_controls(catalog).next().is_some() {
-            replace_exact_render_fragment(
-                &mut output,
-                "    WgmmaControl { mode: GeneratedWgmmaControlMode },\n}",
-                "    WgmmaControl { mode: GeneratedWgmmaControlMode },\n    ScalarArithmetic { format: GeneratedScalarArithmeticFormat, operation: GeneratedScalarArithmeticOperation, rounding: GeneratedScalarArithmeticRounding, subnormal: GeneratedScalarArithmeticSubnormal, saturation: GeneratedScalarArithmeticSaturation },\n}",
-            );
-        } else {
-            replace_exact_render_fragment(
-                &mut output,
-                "    ScalarConversion { rounding: GeneratedScalarConversionRounding, saturation: GeneratedScalarConversionSaturation },\n}",
-                "    ScalarConversion { rounding: GeneratedScalarConversionRounding, saturation: GeneratedScalarConversionSaturation },\n    ScalarArithmetic { format: GeneratedScalarArithmeticFormat, operation: GeneratedScalarArithmeticOperation, rounding: GeneratedScalarArithmeticRounding, subnormal: GeneratedScalarArithmeticSubnormal, saturation: GeneratedScalarArithmeticSaturation },\n}",
-            );
-        }
-    }
-    if extended_minmax(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
-            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedExtendedMinMaxFormat { F32, F16, Bf16, F16x2, Bf16x2 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedExtendedMinMaxOperation { Min, Max }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedExtendedMinMaxSubnormal { Preserve, Ftz }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedExtendedMinMaxNan { Number, Nan }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
-        );
-        replace_exact_render_fragment(
-            &mut output,
-            "}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicTarget",
-            "    ExtendedMinMax { format: GeneratedExtendedMinMaxFormat, operation: GeneratedExtendedMinMaxOperation, subnormal: GeneratedExtendedMinMaxSubnormal, nan: GeneratedExtendedMinMaxNan, xorsign_abs: bool },\n}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicTarget",
-        );
-    }
-    if tcgen05_mma_intrinsics(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
-            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedTcgen05MmaForm { Shared, Tensor, TensorAshift, SpShared, SpTensor, SpTensorAshift, WsShared, WsSharedZeroColMask, WsSpShared, WsSpSharedZeroColMask, WsSpTensor, WsSpTensorZeroColMask, WsTensor, WsTensorZeroColMask }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedTcgen05MmaTargetSelector { Kind }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
-        );
-        replace_exact_render_fragment(
-            &mut output,
-            "}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicTarget",
-            "    Tcgen05Mma { form: GeneratedTcgen05MmaForm, target_selector: GeneratedTcgen05MmaTargetSelector, compatibility_alias: bool },\n}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicTarget",
-        );
-    }
-    for record in records.iter().copied() {
-        let llvm_facts = match &record.llvm {
-            Some(llvm) => {
-                let result_range = match &llvm.result_facts.range {
-                    Some(range) => format!(
-                        "Some(GeneratedIntrinsicRange {{ lower: {:?}, upper_exclusive: {:?} }})",
-                        range.lower, range.upper_exclusive
-                    ),
-                    None => "None".to_owned(),
-                };
-                format!(
-                    "Some(GeneratedLlvmFacts {{ properties: &{:?}, result_no_undef: {}, result_range: {} }})",
-                    llvm.properties, llvm.result_facts.no_undef, result_range
-                )
-            }
-            None => "None".to_owned(),
-        };
-        writeln!(
-            output,
-            "    GeneratedIntrinsicTarget {{ marker: {:?}, id: {:?}, abi_id: {:?}, dialect_op: {:?}, variant: {}, requirement: GeneratedTargetRequirement {{ minimum_ptx: GeneratedPtxVersion::from_encoded({}), hardware: {} }}, backend_requirements: {}, selections: {}, llvm: {} }},",
-            intrinsic_marker(catalog, record),
-            record.id,
-            record.rust.abi_id,
-            record.dialect.op_name,
-            generated_intrinsic_variant(record),
-            record.target.minimum_ptx.encoded(),
-            generated_hardware_target(&record.target.hardware),
-            generated_backend_requirements(record),
-            generated_selection_alternatives(&record.selections),
-            llvm_facts,
-        )
-        .unwrap();
-    }
-    output.push_str(
-        "];\n\npub fn generated_intrinsic_target_by_marker(marker: &str) -> Option<&'static GeneratedIntrinsicTarget> {\n    GENERATED_INTRINSIC_TARGETS.iter().find(|target| target.marker == marker)\n}\n\npub fn generated_intrinsic_targets_by_op_name(op_name: &str) -> impl Iterator<Item = &'static GeneratedIntrinsicTarget> + '_ {\n    GENERATED_INTRINSIC_TARGETS.iter().filter(move |target| target.dialect_op == op_name)\n}\n\npub fn generated_intrinsic_target_by_op_name(op_name: &str) -> Option<&'static GeneratedIntrinsicTarget> {\n    generated_intrinsic_targets_by_op_name(op_name).next()\n}\n\npub fn generated_intrinsic_target(op_name: &str) -> Option<&'static GeneratedIntrinsicTarget> {\n    generated_intrinsic_target_by_op_name(op_name)\n}\n\npub fn generated_intrinsic_operation_matches(ctx: &Context, target: &GeneratedIntrinsicTarget, operation: Ptr<Operation>) -> bool {\n    match target.variant {\n        GeneratedIntrinsicVariant::Scalar => true,\n        GeneratedIntrinsicVariant::Ldmatrix { shape, multiplicity, layout } => {\n            let Some(op) = Operation::get_op::<LdmatrixOp>(operation, ctx) else { return false; };\n            let shape_matches = matches!(shape, GeneratedLdmatrixShape::M8n8) && op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref() == Some(&LdmatrixShapeAttr::M8n8);\n            let multiplicity_matches = match multiplicity {\n                GeneratedLdmatrixMultiplicity::X1 => op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref() == Some(&LdmatrixMultiplicityAttr::X1),\n                GeneratedLdmatrixMultiplicity::X2 => op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref() == Some(&LdmatrixMultiplicityAttr::X2),\n                GeneratedLdmatrixMultiplicity::X4 => op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref() == Some(&LdmatrixMultiplicityAttr::X4),\n            };\n            let layout_matches = match layout {\n                GeneratedLdmatrixLayout::Normal => op.get_attr_nvvm_ldmatrix_layout(ctx).as_deref() == Some(&LdmatrixLayoutAttr::Normal),\n                GeneratedLdmatrixLayout::Transposed => op.get_attr_nvvm_ldmatrix_layout(ctx).as_deref() == Some(&LdmatrixLayoutAttr::Transposed),\n            };\n            shape_matches && multiplicity_matches && layout_matches\n                && op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B16)\n                && op.get_attr_nvvm_ldmatrix_state_space(ctx).as_deref() == Some(&LdmatrixStateSpaceAttr::Shared)\n        }\n        GeneratedIntrinsicVariant::PackedAtomic { format } => {\n            let Some(op) = Operation::get_op::<PackedAtomicAddOp>(operation, ctx) else { return false; };\n            let format_matches = match format {\n                GeneratedPackedAtomicFormat::F16x2 => op.get_attr_nvvm_packed_atomic_format(ctx).as_deref() == Some(&PackedAtomicFormatAttr::F16x2),\n                GeneratedPackedAtomicFormat::Bf16x2 => op.get_attr_nvvm_packed_atomic_format(ctx).as_deref() == Some(&PackedAtomicFormatAttr::Bf16x2),\n            };\n            format_matches\n                && op.get_attr_nvvm_packed_atomic_state_space(ctx).as_deref() == Some(&PackedAtomicStateSpaceAttr::Global)\n                && op.get_attr_nvvm_packed_atomic_ordering(ctx).as_deref() == Some(&PackedAtomicOrderingAttr::Relaxed)\n                && op.get_attr_nvvm_packed_atomic_scope(ctx).as_deref() == Some(&PackedAtomicScopeAttr::Gpu)\n                && op.get_attr_nvvm_packed_atomic_rounding(ctx).as_deref() == Some(&PackedAtomicRoundingAttr::Rn)\n                && op.get_attr_nvvm_packed_atomic_subnormal(ctx).as_deref() == Some(&PackedAtomicSubnormalAttr::NoFtz)\n                && op.get_attr_nvvm_packed_atomic_atomicity(ctx).as_deref() == Some(&PackedAtomicAtomicityAttr::PerElement)\n        }\n        GeneratedIntrinsicVariant::RegisterMma { shape, accumulator, a_element, b_element, a_layout, b_layout, overflow } => {\n            let Some(op) = Operation::get_op::<RegisterMmaOp>(operation, ctx) else { return false; };\n            let shape_matches = match shape {\n                GeneratedRegisterMmaShape::M8n8k4 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k4),\n                GeneratedRegisterMmaShape::M16n8k8 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k8),\n                GeneratedRegisterMmaShape::M16n8k16 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k16),\n                GeneratedRegisterMmaShape::M16n8k32 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k32),\n            };\n            let accumulator_matches = match accumulator {\n                GeneratedRegisterMmaAccumulator::F32 => op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref() == Some(&RegisterMmaAccumulatorAttr::F32),\n                GeneratedRegisterMmaAccumulator::F64 => op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref() == Some(&RegisterMmaAccumulatorAttr::F64),\n                GeneratedRegisterMmaAccumulator::S32 => op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref() == Some(&RegisterMmaAccumulatorAttr::S32),\n            };\n            let element_matches = |expected, actual: Option<&RegisterMmaElementAttr>| match expected {\n                GeneratedRegisterMmaElement::Bf16 => actual == Some(&RegisterMmaElementAttr::Bf16),\n                GeneratedRegisterMmaElement::F16 => actual == Some(&RegisterMmaElementAttr::F16),\n                GeneratedRegisterMmaElement::Tf32 => actual == Some(&RegisterMmaElementAttr::Tf32),\n                GeneratedRegisterMmaElement::F64 => actual == Some(&RegisterMmaElementAttr::F64),\n                GeneratedRegisterMmaElement::S8 => actual == Some(&RegisterMmaElementAttr::S8),\n                GeneratedRegisterMmaElement::U8 => actual == Some(&RegisterMmaElementAttr::U8),\n            };\n            let layout_matches = |expected, actual: Option<&RegisterMmaLayoutAttr>| match expected {\n                GeneratedRegisterMmaLayout::Row => actual == Some(&RegisterMmaLayoutAttr::Row),\n                GeneratedRegisterMmaLayout::Col => actual == Some(&RegisterMmaLayoutAttr::Col),\n            };\n            let overflow_matches = match overflow {\n                GeneratedRegisterMmaOverflow::NotApplicable => op.get_attr_nvvm_register_mma_overflow(ctx).as_deref() == Some(&RegisterMmaOverflowAttr::NotApplicable),\n                GeneratedRegisterMmaOverflow::Wrapping => op.get_attr_nvvm_register_mma_overflow(ctx).as_deref() == Some(&RegisterMmaOverflowAttr::Wrapping),\n                GeneratedRegisterMmaOverflow::Satfinite => op.get_attr_nvvm_register_mma_overflow(ctx).as_deref() == Some(&RegisterMmaOverflowAttr::Satfinite),\n            };\n            shape_matches && accumulator_matches\n                && element_matches(a_element, op.get_attr_nvvm_register_mma_a_element(ctx).as_deref())\n                && element_matches(b_element, op.get_attr_nvvm_register_mma_b_element(ctx).as_deref())\n                && layout_matches(a_layout, op.get_attr_nvvm_register_mma_a_layout(ctx).as_deref())\n                && layout_matches(b_layout, op.get_attr_nvvm_register_mma_b_layout(ctx).as_deref())\n                && overflow_matches\n        }\n    }\n}\n",
-    );
-    if tcgen05_mma_intrinsics(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "pub fn generated_intrinsic_target(op_name: &str) -> Option<&'static GeneratedIntrinsicTarget> {\n    generated_intrinsic_target_by_op_name(op_name)\n}\n\npub fn generated_intrinsic_operation_matches",
-            "pub fn generated_intrinsic_target(op_name: &str) -> Option<&'static GeneratedIntrinsicTarget> {\n    generated_intrinsic_target_by_op_name(op_name)\n}\n\npub fn generated_intrinsic_target_is_direct_dialect_candidate(target: &GeneratedIntrinsicTarget) -> bool {\n    !matches!(target.variant, GeneratedIntrinsicVariant::Tcgen05Mma { compatibility_alias: true, .. })\n}\n\npub fn generated_intrinsic_operation_matches",
-        );
-        replace_exact_render_fragment(
-            &mut output,
-            "        GeneratedIntrinsicVariant::Scalar => true,",
-            r#"        GeneratedIntrinsicVariant::Scalar => true,
-        GeneratedIntrinsicVariant::Tcgen05Mma { form, target_selector, compatibility_alias } => {
-            let Some(op) = Operation::get_op::<Tcgen05MmaOp>(operation, ctx) else { return false; };
-            let form_matches = match form {
-                GeneratedTcgen05MmaForm::Shared => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::Shared),
-                GeneratedTcgen05MmaForm::Tensor => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::Tensor),
-                GeneratedTcgen05MmaForm::TensorAshift => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::TensorAshift),
-                GeneratedTcgen05MmaForm::SpShared => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::SpShared),
-                GeneratedTcgen05MmaForm::SpTensor => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::SpTensor),
-                GeneratedTcgen05MmaForm::SpTensorAshift => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::SpTensorAshift),
-                GeneratedTcgen05MmaForm::WsShared => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsShared),
-                GeneratedTcgen05MmaForm::WsSharedZeroColMask => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsSharedZeroColMask),
-                GeneratedTcgen05MmaForm::WsSpShared => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsSpShared),
-                GeneratedTcgen05MmaForm::WsSpSharedZeroColMask => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsSpSharedZeroColMask),
-                GeneratedTcgen05MmaForm::WsSpTensor => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsSpTensor),
-                GeneratedTcgen05MmaForm::WsSpTensorZeroColMask => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsSpTensorZeroColMask),
-                GeneratedTcgen05MmaForm::WsTensor => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsTensor),
-                GeneratedTcgen05MmaForm::WsTensorZeroColMask => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsTensorZeroColMask),
-            };
-            let selector_matches = matches!(target_selector, GeneratedTcgen05MmaTargetSelector::Kind)
-                && op.get_attr_nvvm_tcgen05_mma_kind(ctx).is_some();
-            let alias_matches = !compatibility_alias || (
-                op.get_attr_nvvm_tcgen05_mma_kind(ctx).as_deref() == Some(&Tcgen05MmaKindAttr::F8f6f4)
-                    && match form {
-                        GeneratedTcgen05MmaForm::Shared => {
-                            op.get_attr_nvvm_tcgen05_mma_cta_group(ctx).as_deref() == Some(&Tcgen05MmaCtaGroupAttr::Cg1)
-                                && op.get_attr_nvvm_tcgen05_mma_collector_a(ctx).as_deref() == Some(&Tcgen05MmaCollectorAAttr::Discard)
-                        }
-                        GeneratedTcgen05MmaForm::WsTensor => {
-                            op.get_attr_nvvm_tcgen05_mma_b_buffer(ctx).as_deref() == Some(&Tcgen05MmaBBufferAttr::B0)
-                                && op.get_attr_nvvm_tcgen05_mma_b_usage(ctx).as_deref() == Some(&Tcgen05MmaBUsageAttr::Discard)
-                        }
-                        _ => false,
-                    }
-            );
-            form_matches && selector_matches && alias_matches
-        }"#,
-        );
-    }
-    replace_exact_render_fragment(
-        &mut output,
-        "GeneratedIntrinsicVariant::Ldmatrix { shape, multiplicity, layout } => {",
-        "GeneratedIntrinsicVariant::Ldmatrix { shape, multiplicity, layout, element } => {",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "            let shape_matches = matches!(shape, GeneratedLdmatrixShape::M8n8) && op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref() == Some(&LdmatrixShapeAttr::M8n8);",
-        "            let shape_matches = match shape {\n                GeneratedLdmatrixShape::M8n8 => op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref() == Some(&LdmatrixShapeAttr::M8n8),\n                GeneratedLdmatrixShape::M8n16 => op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref() == Some(&LdmatrixShapeAttr::M8n16),\n                GeneratedLdmatrixShape::M16n16 => op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref() == Some(&LdmatrixShapeAttr::M16n16),\n            };",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "            shape_matches && multiplicity_matches && layout_matches\n                && op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B16)",
-        "            let element_matches = match element {\n                GeneratedLdmatrixElement::B16 => op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B16),\n                GeneratedLdmatrixElement::B8 => op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B8),\n                GeneratedLdmatrixElement::B8x16B4x16P64 => op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B8x16B4x16P64),\n                GeneratedLdmatrixElement::B8x16B6x16P32 => op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B8x16B6x16P32),\n            };\n            shape_matches && multiplicity_matches && layout_matches && element_matches",
-    );
-    let mut compatibility_aliases = String::from(
-        "fn generated_intrinsic_compatibility_marker_by_op_name(op_name: &str) -> Option<&'static str> {\n    match op_name {\n",
-    );
-    let mut compatibility_count = 0;
-    for record in ldmatrix(catalog) {
-        let Some((_, op_name)) = ldmatrix_compat_op(record) else {
-            continue;
-        };
-        compatibility_count += 1;
-        writeln!(
-            compatibility_aliases,
-            "        {op_name:?} => Some({:?}),",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-    }
-    assert_eq!(compatibility_count, 6);
-    compatibility_aliases.push_str("        _ => None,\n    }\n}\n\n");
-    replace_exact_render_fragment(
-        &mut output,
-        "pub fn generated_intrinsic_target_by_marker(marker: &str)",
-        &format!(
-            "{compatibility_aliases}pub fn generated_intrinsic_target_by_marker(marker: &str)"
-        ),
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "    GENERATED_INTRINSIC_TARGETS.iter().filter(move |target| target.dialect_op == op_name)\n",
-        "    let compatibility_marker = generated_intrinsic_compatibility_marker_by_op_name(op_name);\n    GENERATED_INTRINSIC_TARGETS.iter().filter(move |target| {\n        target.dialect_op == op_name || compatibility_marker == Some(target.marker)\n    })\n",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "        GeneratedIntrinsicVariant::Ldmatrix { shape, multiplicity, layout, element } => {\n            let Some(op) = Operation::get_op::<LdmatrixOp>(operation, ctx) else { return false; };",
-        "        GeneratedIntrinsicVariant::Ldmatrix { shape, multiplicity, layout, element } => {\n            let operation_name = Operation::get_opid(operation, ctx).to_string();\n            if let Some(marker) = generated_intrinsic_compatibility_marker_by_op_name(&operation_name) {\n                return marker == target.marker;\n            }\n            let Some(op) = Operation::get_op::<LdmatrixOp>(operation, ctx) else { return false; };",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "GeneratedIntrinsicVariant::RegisterMma { shape, accumulator,",
-        "GeneratedIntrinsicVariant::RegisterMma { shape, operation: mma_operation, kind, accumulator,",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "            };\n            let accumulator_matches = match accumulator {",
-        "            };\n            let operation_matches = match mma_operation {\n                GeneratedRegisterMmaOperation::Multiply => op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::Multiply,\n                GeneratedRegisterMmaOperation::AndPopc => op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::AndPopc,\n                GeneratedRegisterMmaOperation::XorPopc => op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::XorPopc,\n            };\n            let kind_matches = match kind {\n                GeneratedRegisterMmaKind::Standard => op.kind_or_inferred(ctx) == RegisterMmaKindAttr::Standard,\n                GeneratedRegisterMmaKind::F8f6f4 => op.kind_or_inferred(ctx) == RegisterMmaKindAttr::F8f6f4,\n                GeneratedRegisterMmaKind::Mxf8f6f4 => op.kind_or_inferred(ctx) == RegisterMmaKindAttr::Mxf8f6f4,\n            };\n            let accumulator_matches = match accumulator {",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "            let accumulator_matches = match accumulator {\n                GeneratedRegisterMmaAccumulator::F32",
-        "            let accumulator_matches = match accumulator {\n                GeneratedRegisterMmaAccumulator::F16 => op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref() == Some(&RegisterMmaAccumulatorAttr::F16),\n                GeneratedRegisterMmaAccumulator::F32",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "            shape_matches && accumulator_matches",
-        "            shape_matches && operation_matches && kind_matches && accumulator_matches",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "GeneratedRegisterMmaShape::M8n8k4 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k4),\n                GeneratedRegisterMmaShape::M16n8k8",
-        "GeneratedRegisterMmaShape::M8n8k4 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k4),\n                GeneratedRegisterMmaShape::M8n8k16 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k16),\n                GeneratedRegisterMmaShape::M8n8k32 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k32),\n                GeneratedRegisterMmaShape::M8n8k128 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k128),\n                GeneratedRegisterMmaShape::M16n8k4 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k4),\n                GeneratedRegisterMmaShape::M16n8k8",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "GeneratedRegisterMmaShape::M16n8k32 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k32),\n            };",
-        "GeneratedRegisterMmaShape::M16n8k32 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k32),\n                GeneratedRegisterMmaShape::M16n8k64 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k64),\n                GeneratedRegisterMmaShape::M16n8k128 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k128),\n                GeneratedRegisterMmaShape::M16n8k256 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k256),\n            };",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "GeneratedRegisterMmaElement::F64 => actual == Some(&RegisterMmaElementAttr::F64),\n                GeneratedRegisterMmaElement::S8",
-        "GeneratedRegisterMmaElement::F64 => actual == Some(&RegisterMmaElementAttr::F64),\n                GeneratedRegisterMmaElement::E2m1 => actual == Some(&RegisterMmaElementAttr::E2m1),\n                GeneratedRegisterMmaElement::E2m3 => actual == Some(&RegisterMmaElementAttr::E2m3),\n                GeneratedRegisterMmaElement::E3m2 => actual == Some(&RegisterMmaElementAttr::E3m2),\n                GeneratedRegisterMmaElement::E4m3 => actual == Some(&RegisterMmaElementAttr::E4m3),\n                GeneratedRegisterMmaElement::E5m2 => actual == Some(&RegisterMmaElementAttr::E5m2),\n                GeneratedRegisterMmaElement::B1 => actual == Some(&RegisterMmaElementAttr::B1),\n                GeneratedRegisterMmaElement::S4 => actual == Some(&RegisterMmaElementAttr::S4),\n                GeneratedRegisterMmaElement::U4 => actual == Some(&RegisterMmaElementAttr::U4),\n                GeneratedRegisterMmaElement::S8",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "                && overflow_matches\n        }\n    }\n}\n",
-        "                && overflow_matches\n        }\n        GeneratedIntrinsicVariant::SparseMma { shape, accumulator, a_element, b_element, a_layout, b_layout, overflow, metadata, selector } => {\n            let Some(op) = Operation::get_op::<SparseMmaOp>(operation, ctx) else { return false; };\n            let element_matches = |expected, actual: Option<&SparseMmaElementAttr>| match expected {\n                GeneratedSparseMmaElement::E2m1 => actual == Some(&SparseMmaElementAttr::E2m1),\n                GeneratedSparseMmaElement::E2m3 => actual == Some(&SparseMmaElementAttr::E2m3),\n                GeneratedSparseMmaElement::E3m2 => actual == Some(&SparseMmaElementAttr::E3m2),\n                GeneratedSparseMmaElement::E4m3 => actual == Some(&SparseMmaElementAttr::E4m3),\n                GeneratedSparseMmaElement::E5m2 => actual == Some(&SparseMmaElementAttr::E5m2),\n                GeneratedSparseMmaElement::S4 => actual == Some(&SparseMmaElementAttr::S4),\n                GeneratedSparseMmaElement::U4 => actual == Some(&SparseMmaElementAttr::U4),\n                GeneratedSparseMmaElement::S8 => actual == Some(&SparseMmaElementAttr::S8),\n                GeneratedSparseMmaElement::U8 => actual == Some(&SparseMmaElementAttr::U8),\n            };\n            let layout_matches = |expected, actual: Option<&SparseMmaLayoutAttr>| match expected {\n                GeneratedSparseMmaLayout::Row => actual == Some(&SparseMmaLayoutAttr::Row),\n                GeneratedSparseMmaLayout::Col => actual == Some(&SparseMmaLayoutAttr::Col),\n            };\n            let overflow_matches = match overflow {\n                GeneratedSparseMmaOverflow::NotApplicable => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::NotApplicable),\n                GeneratedSparseMmaOverflow::Wrapping => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Wrapping),\n                GeneratedSparseMmaOverflow::Satfinite => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Satfinite),\n            };\n            let metadata_matches = match metadata {\n                GeneratedSparseMmaMetadata::Standard => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Standard),\n                GeneratedSparseMmaMetadata::Ordered => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Ordered),\n            };\n            matches!(shape, GeneratedSparseMmaShape::M16n8k32)\n                && op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32)\n                && matches!(accumulator, GeneratedSparseMmaAccumulator::S32)\n                && op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32)\n                && element_matches(a_element, op.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref())\n                && element_matches(b_element, op.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref())\n                && layout_matches(a_layout, op.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref())\n                && layout_matches(b_layout, op.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref())\n                && overflow_matches\n                && metadata_matches\n                && matches!(selector, GeneratedSparseMmaSelector::ImmediateZeroOrOne)\n                && op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne)\n        }\n    }\n}\n",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "            matches!(shape, GeneratedSparseMmaShape::M16n8k32)\n                && op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32)\n                && matches!(accumulator, GeneratedSparseMmaAccumulator::S32)\n                && op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32)",
-        "            let shape_matches = match shape {\n                GeneratedSparseMmaShape::M16n8k32 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32),\n                GeneratedSparseMmaShape::M16n8k64 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k64),\n                GeneratedSparseMmaShape::M16n8k128 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k128),\n            };\n            let accumulator_matches = match accumulator {\n                GeneratedSparseMmaAccumulator::F16 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F16),\n                GeneratedSparseMmaAccumulator::F32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F32),\n                GeneratedSparseMmaAccumulator::S32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32),\n            };\n            let selector_matches = match selector {\n                GeneratedSparseMmaSelector::ImmediateZeroOrOne => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),\n                GeneratedSparseMmaSelector::ImmediateZero => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZero),\n            };\n            shape_matches\n                && accumulator_matches",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "                && metadata_matches\n                && matches!(selector, GeneratedSparseMmaSelector::ImmediateZeroOrOne)\n                && op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne)",
-        "                && metadata_matches\n                && selector_matches",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "        }\n    }\n}\n",
-        "        }\n        GeneratedIntrinsicVariant::Prmt { mode } => {\n            let Some(op) = Operation::get_op::<PrmtOp>(operation, ctx) else { return false; };\n            match mode {\n                GeneratedPrmtMode::Generic => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Generic),\n                GeneratedPrmtMode::F4e => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::F4e),\n                GeneratedPrmtMode::B4e => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::B4e),\n                GeneratedPrmtMode::Rc8 => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Rc8),\n                GeneratedPrmtMode::Ecl => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Ecl),\n                GeneratedPrmtMode::Ecr => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Ecr),\n                GeneratedPrmtMode::Rc16 => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Rc16),\n            }\n        }\n    }\n}\n",
-    );
-    replace_exact_render_fragment(
-        &mut output,
-        "        }\n    }\n}\n",
-        "        }\n        GeneratedIntrinsicVariant::ClusterBarrier { mode } => {\n            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else { return false; };\n            match mode {\n                GeneratedClusterBarrierMode::Arrive => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Arrive),\n                GeneratedClusterBarrierMode::ArriveAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveAligned),\n                GeneratedClusterBarrierMode::ArriveRelaxed => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxed),\n                GeneratedClusterBarrierMode::ArriveRelaxedAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned),\n                GeneratedClusterBarrierMode::Wait => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Wait),\n                GeneratedClusterBarrierMode::WaitAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::WaitAligned),\n            }\n        }\n    }\n}\n",
-    );
-    if wgmma_controls(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "        GeneratedIntrinsicVariant::ClusterBarrier { mode } => {\n            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else { return false; };\n            match mode {\n                GeneratedClusterBarrierMode::Arrive => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Arrive),\n                GeneratedClusterBarrierMode::ArriveAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveAligned),\n                GeneratedClusterBarrierMode::ArriveRelaxed => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxed),\n                GeneratedClusterBarrierMode::ArriveRelaxedAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned),\n                GeneratedClusterBarrierMode::Wait => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Wait),\n                GeneratedClusterBarrierMode::WaitAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::WaitAligned),\n            }\n        }\n    }\n}\n",
-            "        GeneratedIntrinsicVariant::ClusterBarrier { mode } => {\n            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else { return false; };\n            match mode {\n                GeneratedClusterBarrierMode::Arrive => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Arrive),\n                GeneratedClusterBarrierMode::ArriveAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveAligned),\n                GeneratedClusterBarrierMode::ArriveRelaxed => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxed),\n                GeneratedClusterBarrierMode::ArriveRelaxedAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned),\n                GeneratedClusterBarrierMode::Wait => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Wait),\n                GeneratedClusterBarrierMode::WaitAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::WaitAligned),\n            }\n        }\n        GeneratedIntrinsicVariant::WgmmaControl { mode } => match mode {\n            GeneratedWgmmaControlMode::Fence => Operation::get_op::<WgmmaFenceSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::CommitGroup => Operation::get_op::<WgmmaCommitGroupSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::WaitGroup => Operation::get_op::<WgmmaWaitGroupSyncAlignedOp>(operation, ctx).is_some(),\n        },\n    }\n}\n",
-        );
-    }
-    if scalar_conversions(catalog).next().is_some() {
-        let scalar_match = "        GeneratedIntrinsicVariant::ScalarConversion { rounding, saturation } => {\n            let Some(op) = Operation::get_op::<ScalarConversionOp>(operation, ctx) else { return false; };\n            let rounding_matches = match rounding {\n                GeneratedScalarConversionRounding::NearestAway => op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref() == Some(&ScalarConversionRoundingAttr::NearestAway),\n                GeneratedScalarConversionRounding::NearestEven => op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref() == Some(&ScalarConversionRoundingAttr::NearestEven),\n                GeneratedScalarConversionRounding::TowardZero => op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref() == Some(&ScalarConversionRoundingAttr::TowardZero),\n            };\n            let saturation_matches = match saturation {\n                GeneratedScalarConversionSaturation::None => op.get_attr_nvvm_scalar_conversion_saturation(ctx).as_deref() == Some(&ScalarConversionSaturationAttr::None),\n                GeneratedScalarConversionSaturation::Relu => op.get_attr_nvvm_scalar_conversion_saturation(ctx).as_deref() == Some(&ScalarConversionSaturationAttr::Relu),\n                GeneratedScalarConversionSaturation::Satfinite => op.get_attr_nvvm_scalar_conversion_saturation(ctx).as_deref() == Some(&ScalarConversionSaturationAttr::Satfinite),\n                GeneratedScalarConversionSaturation::ReluSatfinite => op.get_attr_nvvm_scalar_conversion_saturation(ctx).as_deref() == Some(&ScalarConversionSaturationAttr::ReluSatfinite),\n            };\n            rounding_matches && saturation_matches\n        }\n";
-        if wgmma_controls(catalog).next().is_some() {
-            replace_exact_render_fragment(
-                &mut output,
-                "        GeneratedIntrinsicVariant::WgmmaControl { mode } => match mode {\n            GeneratedWgmmaControlMode::Fence => Operation::get_op::<WgmmaFenceSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::CommitGroup => Operation::get_op::<WgmmaCommitGroupSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::WaitGroup => Operation::get_op::<WgmmaWaitGroupSyncAlignedOp>(operation, ctx).is_some(),\n        },\n    }\n}\n",
-                &format!(
-                    "        GeneratedIntrinsicVariant::WgmmaControl {{ mode }} => match mode {{\n            GeneratedWgmmaControlMode::Fence => Operation::get_op::<WgmmaFenceSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::CommitGroup => Operation::get_op::<WgmmaCommitGroupSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::WaitGroup => Operation::get_op::<WgmmaWaitGroupSyncAlignedOp>(operation, ctx).is_some(),\n        }},\n{scalar_match}    }}\n}}\n"
-                ),
-            );
-        } else {
-            replace_exact_render_fragment(
-                &mut output,
-                "        GeneratedIntrinsicVariant::ClusterBarrier { mode } => {\n            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else { return false; };\n            match mode {\n                GeneratedClusterBarrierMode::Arrive => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Arrive),\n                GeneratedClusterBarrierMode::ArriveAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveAligned),\n                GeneratedClusterBarrierMode::ArriveRelaxed => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxed),\n                GeneratedClusterBarrierMode::ArriveRelaxedAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned),\n                GeneratedClusterBarrierMode::Wait => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Wait),\n                GeneratedClusterBarrierMode::WaitAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::WaitAligned),\n            }\n        }\n    }\n}\n",
-                &format!(
-                    "        GeneratedIntrinsicVariant::ClusterBarrier {{ mode }} => {{\n            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else {{ return false; }};\n            match mode {{\n                GeneratedClusterBarrierMode::Arrive => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Arrive),\n                GeneratedClusterBarrierMode::ArriveAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveAligned),\n                GeneratedClusterBarrierMode::ArriveRelaxed => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxed),\n                GeneratedClusterBarrierMode::ArriveRelaxedAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned),\n                GeneratedClusterBarrierMode::Wait => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Wait),\n                GeneratedClusterBarrierMode::WaitAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::WaitAligned),\n            }}\n        }}\n{scalar_match}    }}\n}}\n"
-                ),
-            );
-        }
-    }
-    if scalar_arithmetics(catalog).next().is_some() {
-        let arithmetic_match = r#"        GeneratedIntrinsicVariant::ScalarArithmetic { format, operation: arithmetic_operation, rounding, subnormal, saturation } => {
-            let Some(op) = Operation::get_op::<ScalarArithmeticOp>(operation, ctx) else { return false; };
-            let format_matches = match format {
-                GeneratedScalarArithmeticFormat::F32 => op.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref() == Some(&ScalarArithmeticFormatAttr::F32),
-                GeneratedScalarArithmeticFormat::F64 => op.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref() == Some(&ScalarArithmeticFormatAttr::F64),
-            };
-            let operation_matches = match arithmetic_operation {
-                GeneratedScalarArithmeticOperation::Mul => op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref() == Some(&ScalarArithmeticOperationAttr::Mul),
-                GeneratedScalarArithmeticOperation::Div => op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref() == Some(&ScalarArithmeticOperationAttr::Div),
-                GeneratedScalarArithmeticOperation::Fma => op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref() == Some(&ScalarArithmeticOperationAttr::Fma),
-                GeneratedScalarArithmeticOperation::Add => op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref() == Some(&ScalarArithmeticOperationAttr::Add),
-            };
-            let rounding_matches = match rounding {
-                GeneratedScalarArithmeticRounding::Rn => op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref() == Some(&ScalarArithmeticRoundingAttr::Rn),
-                GeneratedScalarArithmeticRounding::Rz => op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref() == Some(&ScalarArithmeticRoundingAttr::Rz),
-                GeneratedScalarArithmeticRounding::Rm => op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref() == Some(&ScalarArithmeticRoundingAttr::Rm),
-                GeneratedScalarArithmeticRounding::Rp => op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref() == Some(&ScalarArithmeticRoundingAttr::Rp),
-            };
-            let subnormal_matches = match subnormal {
-                GeneratedScalarArithmeticSubnormal::Preserve => op.get_attr_nvvm_scalar_arithmetic_subnormal(ctx).as_deref() == Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                GeneratedScalarArithmeticSubnormal::Ftz => op.get_attr_nvvm_scalar_arithmetic_subnormal(ctx).as_deref() == Some(&ScalarArithmeticSubnormalAttr::Ftz),
-            };
-            let saturation_matches = match saturation {
-                GeneratedScalarArithmeticSaturation::None => op.get_attr_nvvm_scalar_arithmetic_saturation(ctx).as_deref() == Some(&ScalarArithmeticSaturationAttr::None),
-                GeneratedScalarArithmeticSaturation::Sat => op.get_attr_nvvm_scalar_arithmetic_saturation(ctx).as_deref() == Some(&ScalarArithmeticSaturationAttr::Sat),
-            };
-            format_matches && operation_matches && rounding_matches && subnormal_matches && saturation_matches
-        }
-"#;
-        replace_exact_render_fragment(
-            &mut output,
-            "            rounding_matches && saturation_matches\n        }\n    }\n}\n",
-            &format!(
-                "            rounding_matches && saturation_matches\n        }}\n{arithmetic_match}    }}\n}}\n"
-            ),
-        );
-    }
-    if extended_minmax(catalog).next().is_some() {
-        let minmax_match = r#"        GeneratedIntrinsicVariant::ExtendedMinMax { format, operation: minmax_operation, subnormal, nan, xorsign_abs } => {
-            let Some(op) = Operation::get_op::<ExtendedMinMaxOp>(operation, ctx) else { return false; };
-            let format_matches = match format {
-                GeneratedExtendedMinMaxFormat::F32 => op.get_attr_nvvm_extended_minmax_format(ctx).as_deref() == Some(&ExtendedMinMaxFormatAttr::F32),
-                GeneratedExtendedMinMaxFormat::F16 => op.get_attr_nvvm_extended_minmax_format(ctx).as_deref() == Some(&ExtendedMinMaxFormatAttr::F16),
-                GeneratedExtendedMinMaxFormat::Bf16 => op.get_attr_nvvm_extended_minmax_format(ctx).as_deref() == Some(&ExtendedMinMaxFormatAttr::Bf16),
-                GeneratedExtendedMinMaxFormat::F16x2 => op.get_attr_nvvm_extended_minmax_format(ctx).as_deref() == Some(&ExtendedMinMaxFormatAttr::F16x2),
-                GeneratedExtendedMinMaxFormat::Bf16x2 => op.get_attr_nvvm_extended_minmax_format(ctx).as_deref() == Some(&ExtendedMinMaxFormatAttr::Bf16x2),
-            };
-            let operation_matches = match minmax_operation {
-                GeneratedExtendedMinMaxOperation::Min => op.get_attr_nvvm_extended_minmax_operation(ctx).as_deref() == Some(&ExtendedMinMaxOperationAttr::Min),
-                GeneratedExtendedMinMaxOperation::Max => op.get_attr_nvvm_extended_minmax_operation(ctx).as_deref() == Some(&ExtendedMinMaxOperationAttr::Max),
-            };
-            let subnormal_matches = match subnormal {
-                GeneratedExtendedMinMaxSubnormal::Preserve => op.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref() == Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                GeneratedExtendedMinMaxSubnormal::Ftz => op.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref() == Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-            };
-            let nan_matches = match nan {
-                GeneratedExtendedMinMaxNan::Number => op.get_attr_nvvm_extended_minmax_nan(ctx).as_deref() == Some(&ExtendedMinMaxNanAttr::Number),
-                GeneratedExtendedMinMaxNan::Nan => op.get_attr_nvvm_extended_minmax_nan(ctx).as_deref() == Some(&ExtendedMinMaxNanAttr::Nan),
-            };
-            let xorsign_abs_matches = match xorsign_abs {
-                false => op.get_attr_nvvm_extended_minmax_xorsign_abs(ctx).as_deref() == Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-                true => op.get_attr_nvvm_extended_minmax_xorsign_abs(ctx).as_deref() == Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            };
-            format_matches && operation_matches && subnormal_matches && nan_matches && xorsign_abs_matches
-        }
-"#;
-        let match_end = output
-            .rfind("    }\n}\n")
-            .expect("generated target matcher terminator");
-        output.insert_str(match_end, minmax_match);
-    }
-    output.push_str(
-        "\nuse dialect_nvvm::ops::{ClusterBarrierModeAttr, ClusterBarrierOp, LdmatrixElementAttr, LdmatrixLayoutAttr, LdmatrixMultiplicityAttr, LdmatrixOp, LdmatrixShapeAttr, LdmatrixStateSpaceAttr, PackedAtomicAddOp, PackedAtomicAtomicityAttr, PackedAtomicFormatAttr, PackedAtomicOrderingAttr, PackedAtomicRoundingAttr, PackedAtomicScopeAttr, PackedAtomicStateSpaceAttr, PackedAtomicSubnormalAttr, PrmtModeAttr, PrmtOp, RegisterMmaAccumulatorAttr, RegisterMmaElementAttr, RegisterMmaKindAttr, RegisterMmaLayoutAttr, RegisterMmaOp, RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr, SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr, SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr};\nuse pliron::{context::{Context, Ptr}, operation::Operation};\n",
-    );
-    if wgmma_controls(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "SparseMmaSelectorAttr, SparseMmaShapeAttr};",
-            "SparseMmaSelectorAttr, SparseMmaShapeAttr, WgmmaCommitGroupSyncAlignedOp, WgmmaFenceSyncAlignedOp, WgmmaWaitGroupSyncAlignedOp};",
-        );
-    }
-    if scalar_conversions(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "SparseMmaSelectorAttr, SparseMmaShapeAttr",
-            "ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr",
-        );
-    }
-    if scalar_arithmetics(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "SparseMmaSelectorAttr, SparseMmaShapeAttr",
-            "ScalarArithmeticFormatAttr, ScalarArithmeticOp, ScalarArithmeticOperationAttr, ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr",
-        );
-    }
-    if extended_minmax(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "SparseMmaSelectorAttr, SparseMmaShapeAttr",
-            "ExtendedMinMaxFormatAttr, ExtendedMinMaxNanAttr, ExtendedMinMaxOp, ExtendedMinMaxOperationAttr, ExtendedMinMaxSubnormalAttr, ExtendedMinMaxXorSignAbsAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr",
-        );
-    }
-    if tcgen05_mma_intrinsics(catalog).next().is_some() {
-        replace_exact_render_fragment(
-            &mut output,
-            "SparseMmaSelectorAttr, SparseMmaShapeAttr",
-            "SparseMmaSelectorAttr, SparseMmaShapeAttr, Tcgen05MmaBBufferAttr, Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr, Tcgen05MmaFormAttr, Tcgen05MmaKindAttr, Tcgen05MmaOp",
-        );
-    }
-    output.push_str(
-        "\n#[cfg(test)]\nmod tests {\n    use super::*;\n    use std::collections::BTreeSet;\n\n    #[test]\n    fn generated_target_table_is_unique_and_lookup_is_complete() {\n        let mut ids = BTreeSet::new();\n        let mut markers = BTreeSet::new();\n        let mut previous_abi_id = None;\n        for target in GENERATED_INTRINSIC_TARGETS {\n            if let Some(previous) = previous_abi_id {\n                assert!(previous < target.abi_id, \"generated ABI IDs are not strictly increasing: {previous} then {}\", target.abi_id);\n            }\n            previous_abi_id = Some(target.abi_id);\n            assert!(ids.insert(target.id), \"duplicate generated intrinsic ID {}\", target.id);\n            assert!(markers.insert(target.marker), \"duplicate generated marker {}\", target.marker);\n            assert_eq!(generated_intrinsic_target_by_marker(target.marker), Some(target));\n            assert!(generated_intrinsic_targets_by_op_name(target.dialect_op).any(|candidate| candidate == target));\n        }\n",
-    );
-    for record in records {
-        writeln!(
-            output,
-            "        let target = generated_intrinsic_target_by_marker({:?}).unwrap();",
-            intrinsic_marker(catalog, record)
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "        assert_eq!(target.id, {:?});\n        assert_eq!(target.abi_id, {:?});\n        assert_eq!(target.dialect_op, {:?});\n        assert_eq!(target.variant, {});\n        assert_eq!(target.requirement.minimum_ptx.encoded(), {});\n        assert_eq!(target.requirement.hardware, const {{ {} }});\n        assert_eq!(target.backend_requirements, const {{ {} }});\n        assert_eq!(target.selections, {});",
-            record.id,
-            record.rust.abi_id,
-            record.dialect.op_name,
-            generated_intrinsic_variant(record),
-            record.target.minimum_ptx.encoded(),
-            generated_hardware_target(&record.target.hardware),
-            generated_backend_requirements(record),
-            generated_selection_alternatives(&record.selections),
-        )
-        .unwrap();
-        match &record.llvm {
-            Some(llvm) => {
-                writeln!(
-                    output,
-                    "        assert_eq!(target.llvm.unwrap().properties, &{:?} as &[&str]);",
-                    llvm.properties
-                )
-                .unwrap();
-            }
-            None => output.push_str("        assert!(target.llvm.is_none());\n"),
-        }
-    }
-    output.push_str("        assert!(generated_intrinsic_target_by_marker(\"v1:i9999\").is_none());\n    }\n}\n");
-    output
-}
-
-fn render_special_register_probe(
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-    hash: &str,
-    backend: IntrinsicBackend,
-) -> String {
-    let mut output = llvm_header(catalog, hash);
-    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
-    let width = record.scalar_width().expect("special-register width");
-    let function_name = format!("probe_{}_{}", record.id, backend_label(backend));
-    match special_register_backend_mechanism(record, backend) {
-        BackendLoweringMechanism::TypedNvvm => {
-            let symbol = &record
-                .llvm
-                .as_ref()
-                .expect("typed special-register route")
-                .symbol;
-            writeln!(output, "declare i{width} @{symbol}()\n").unwrap();
-            writeln!(output, "define i{width} @{function_name}() {{").unwrap();
-            writeln!(output, "  %result = call i{width} @{symbol}()").unwrap();
-        }
-        BackendLoweringMechanism::InlinePtx => {
-            writeln!(output, "define i{width} @{function_name}() {{").unwrap();
-            let sideeffect = if record.special_register.as_ref().is_some_and(|special| {
-                special.observation == SpecialRegisterObservation::VolatileObservation
-            }) {
-                " sideeffect"
-            } else {
-                ""
-            };
-            writeln!(
-                output,
-                "  %result = call i{width} asm{sideeffect} {:?}, {:?}()",
-                special_register_inline_template(record),
-                special_register_output_constraint(record)
-            )
-            .unwrap();
-        }
-    }
-    writeln!(output, "  ret i{width} %result\n}}").unwrap();
-    output
-}
-
-fn render_tma_probe(catalog: &CatalogFile, record: &CatalogIntrinsic, hash: &str) -> String {
-    let tma = record.tma.as_ref().expect("TMA contract");
-    let operation = tma.operation;
-    let llvm = llvm(record);
-    let symbol = llvm.resolved_symbol.as_ref().unwrap_or(&llvm.symbol);
-    let mut output = llvm_header(catalog, hash);
-    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
-    if let Some(dimensions) = tma.dimensions() {
-        let is_g2s = matches!(
-            operation,
-            TmaOperation::G2sTile1d
-                | TmaOperation::G2sTile2d
-                | TmaOperation::G2sTile2dMulticast
-                | TmaOperation::G2sTile2dMulticastCg2
-                | TmaOperation::G2sTile3d
-                | TmaOperation::G2sTile4d
-                | TmaOperation::G2sTile5d
-        );
-        let coordinates = std::iter::repeat_n("i32", dimensions)
-            .collect::<Vec<_>>()
-            .join(", ");
-        let coordinate_parameters = (0..dimensions)
-            .map(|index| format!("i32 %coord{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let coordinate_arguments = (0..dimensions)
-            .map(|index| format!("i32 %coord{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        if is_g2s {
-            let multicast = matches!(
-                operation,
-                TmaOperation::G2sTile2dMulticast | TmaOperation::G2sTile2dMulticastCg2
-            );
-            let declaration_coordinates = if coordinates.is_empty() {
-                String::new()
-            } else {
-                format!(", {coordinates}")
-            };
-            writeln!(
-                output,
-                "declare void @{symbol}(ptr addrspace(7), ptr addrspace(3), ptr{declaration_coordinates}, i16, i64, i1, i1, i32) #0\n"
-            )
-            .unwrap();
-            let parameters = if coordinate_parameters.is_empty() {
-                String::new()
-            } else {
-                format!(", {coordinate_parameters}")
-            };
-            let mask_parameter = if multicast { ", i16 %cta_mask" } else { "" };
-            writeln!(
-                output,
-                "define void @probe_{}(ptr %dst_generic, ptr %barrier_generic, ptr %tensor_map{parameters}{mask_parameter}) #0 {{",
-                record.id
-            )
-            .unwrap();
-            output.push_str(
-                "  %dst = addrspacecast ptr %dst_generic to ptr addrspace(7)\n  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
-            );
-            let arguments = if coordinate_arguments.is_empty() {
-                String::new()
-            } else {
-                format!(", {coordinate_arguments}")
-            };
-            let mask = if multicast { "%cta_mask" } else { "0" };
-            let group = if operation == TmaOperation::G2sTile2dMulticastCg2 {
-                2
-            } else {
-                0
-            };
-            writeln!(
-                output,
-                "  call void @{symbol}(ptr addrspace(7) %dst, ptr addrspace(3) %barrier, ptr %tensor_map{arguments}, i16 {mask}, i64 0, i1 {multicast}, i1 false, i32 {group}) #0"
-            )
-            .unwrap();
-        } else {
-            let declaration_coordinates = if coordinates.is_empty() {
-                String::new()
-            } else {
-                format!(", {coordinates}")
-            };
-            writeln!(
-                output,
-                "declare void @{symbol}(ptr addrspace(3), ptr{declaration_coordinates}, i64, i1) #0\n"
-            )
-            .unwrap();
-            let parameters = if coordinate_parameters.is_empty() {
-                String::new()
-            } else {
-                format!(", {coordinate_parameters}")
-            };
-            writeln!(
-                output,
-                "define void @probe_{}(ptr %src_generic, ptr %tensor_map{parameters}) #0 {{",
-                record.id
-            )
-            .unwrap();
-            output.push_str("  %src = addrspacecast ptr %src_generic to ptr addrspace(3)\n");
-            let arguments = if coordinate_arguments.is_empty() {
-                String::new()
-            } else {
-                format!(", {coordinate_arguments}")
-            };
-            writeln!(
-                output,
-                "  call void @{symbol}(ptr addrspace(3) %src, ptr %tensor_map{arguments}, i64 0, i1 false) #0"
-            )
-            .unwrap();
-        }
-        output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
-    } else if operation == TmaOperation::PrefetchTensorMap {
-        writeln!(output, "declare void @{symbol}(ptr)\n").unwrap();
-        writeln!(
-            output,
-            "define void @probe_{}(ptr %tensor_map) {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(output, "  call void @{symbol}(ptr %tensor_map)").unwrap();
-        output.push_str("  ret void\n}\n");
-    } else if let Some(coordinate_count) = operation.prefetch_coordinate_count() {
-        let coordinates = std::iter::repeat_n("i32", coordinate_count)
-            .collect::<Vec<_>>()
-            .join(", ");
-        let declaration_coordinates = if coordinates.is_empty() {
-            String::new()
-        } else {
-            format!(", {coordinates}")
-        };
-        let coordinate_parameters = (0..coordinate_count)
-            .map(|index| format!("i32 %coord{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let parameters = if coordinate_parameters.is_empty() {
-            String::new()
-        } else {
-            format!(", {coordinate_parameters}")
-        };
-        let cache_hint_parameter = if operation.uses_prefetch_cache_hint() {
-            ", i64 %cache_hint"
-        } else {
-            ""
-        };
-        let coordinate_arguments = (0..coordinate_count)
-            .map(|index| format!("i32 %coord{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let arguments = if coordinate_arguments.is_empty() {
-            String::new()
-        } else {
-            format!(", {coordinate_arguments}")
-        };
-        writeln!(
-            output,
-            "declare void @{symbol}(ptr{declaration_coordinates}, i64, i1) #0\n"
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "define void @probe_{}(ptr %tensor_map{parameters}{cache_hint_parameter}) #0 {{",
-            record.id,
-        )
-        .unwrap();
-        let cache_hint = if operation.uses_prefetch_cache_hint() {
-            "%cache_hint"
-        } else {
-            "0"
-        };
-        let use_cache_hint = operation.uses_prefetch_cache_hint();
-        writeln!(
-            output,
-            "  call void @{symbol}(ptr %tensor_map{arguments}, i64 {cache_hint}, i1 {use_cache_hint}) #0"
-        )
-        .unwrap();
-        output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
-    } else if matches!(
-        operation,
-        TmaOperation::ReplaceBoxDim
-            | TmaOperation::ReplaceElementStride
-            | TmaOperation::ReplaceElementType
-            | TmaOperation::ReplaceFillMode
-            | TmaOperation::ReplaceGlobalAddress
-            | TmaOperation::ReplaceGlobalDim
-            | TmaOperation::ReplaceGlobalStride
-            | TmaOperation::ReplaceInterleaveLayout
-            | TmaOperation::ReplaceRank
-            | TmaOperation::ReplaceSwizzleAtomicity
-            | TmaOperation::ReplaceSwizzleMode
-    ) {
-        let (field, width, ordinal, value_ty, immediate, address) = match operation {
-            TmaOperation::ReplaceBoxDim => ("box_dim", "b32", true, "i32", false, false),
-            TmaOperation::ReplaceElementStride => {
-                ("element_stride", "b32", true, "i32", false, false)
-            }
-            TmaOperation::ReplaceElementType => ("elemtype", "b32", false, "i32", true, false),
-            TmaOperation::ReplaceFillMode => ("fill_mode", "b32", false, "i32", true, false),
-            TmaOperation::ReplaceGlobalAddress => {
-                ("global_address", "b64", false, "i64", false, true)
-            }
-            TmaOperation::ReplaceGlobalDim => ("global_dim", "b32", true, "i32", false, false),
-            TmaOperation::ReplaceGlobalStride => {
-                ("global_stride", "b64", true, "i64", false, false)
-            }
-            TmaOperation::ReplaceInterleaveLayout => {
-                ("interleave_layout", "b32", false, "i32", true, false)
-            }
-            TmaOperation::ReplaceRank => ("rank", "b32", false, "i32", false, false),
-            TmaOperation::ReplaceSwizzleAtomicity => {
-                ("swizzle_atomicity", "b32", false, "i32", true, false)
-            }
-            TmaOperation::ReplaceSwizzleMode => ("swizzle_mode", "b32", false, "i32", true, false),
-            _ => unreachable!("TMA tensor-map replace operation was matched"),
-        };
-        let value_parameter = if immediate {
-            String::new()
-        } else if address {
-            ", ptr %new_address".into()
-        } else {
-            format!(", {value_ty} %new_value")
-        };
-        writeln!(
-            output,
-            "define void @probe_{}(ptr %tensor_map{value_parameter}) {{",
-            record.id
-        )
-        .unwrap();
-        let mut arguments = vec!["ptr %tensor_map".to_owned()];
-        let mut constraints = vec!["l"];
-        if ordinal {
-            arguments.push("i32 0".into());
-            constraints.push("n");
-        }
-        if immediate {
-            arguments.push(format!("{value_ty} 0"));
-            constraints.push("n");
-        } else if address {
-            arguments.push("ptr %new_address".into());
-            constraints.push("l");
-        } else {
-            arguments.push(format!("{value_ty} %new_value"));
-            constraints.push(if value_ty == "i64" { "l" } else { "r" });
-        }
-        constraints.push("~{memory}");
-        let template = if ordinal {
-            format!("tensormap.replace.tile.{field}.global.b1024.{width} [$0], $1, $2;")
-        } else {
-            format!("tensormap.replace.tile.{field}.global.b1024.{width} [$0], $1;")
-        };
-        writeln!(
-            output,
-            "  call void asm sideeffect {template:?}, {:?}({})",
-            constraints.join(","),
-            arguments.join(", ")
-        )
-        .unwrap();
-        output.push_str("  ret void\n}\n");
-    } else if matches!(
-        operation,
-        TmaOperation::FenceProxyTensorMapAcquireCluster
-            | TmaOperation::FenceProxyTensorMapAcquireCta
-            | TmaOperation::FenceProxyTensorMapAcquireGpu
-            | TmaOperation::FenceProxyTensorMapAcquireSystem
-    ) {
-        writeln!(output, "declare void @{symbol}(ptr, i32)\n").unwrap();
-        writeln!(
-            output,
-            "define void @probe_{}(ptr %tensor_map) {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(output, "  call void @{symbol}(ptr %tensor_map, i32 128)").unwrap();
-        output.push_str("  ret void\n}\n");
-    } else if operation == TmaOperation::CommitGroup
-        || matches!(
-            operation,
-            TmaOperation::FenceProxyTensorMapReleaseCluster
-                | TmaOperation::FenceProxyTensorMapReleaseCta
-                | TmaOperation::FenceProxyTensorMapReleaseGpu
-                | TmaOperation::FenceProxyTensorMapReleaseSystem
-        )
-    {
-        writeln!(output, "declare void @{symbol}()\n").unwrap();
-        writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
-        writeln!(output, "  call void @{symbol}()").unwrap();
-        output.push_str("  ret void\n}\n");
-    } else {
-        writeln!(output, "declare void @{symbol}(i32)\n").unwrap();
-        writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
-        writeln!(output, "  call void @{symbol}(i32 0)").unwrap();
-        output.push_str("  ret void\n}\n");
-    }
-    output
-}
-
-fn render_execution_control_probe(
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-    hash: &str,
-) -> String {
-    let operation = ExecutionControlOperation::from_catalog_id(&record.id)
-        .expect("closed execution-control operation");
-    let symbol = &llvm(record).symbol;
-    let mut output = llvm_header(catalog, hash);
-    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
-    match operation {
-        ExecutionControlOperation::BarrierCtaSync
-        | ExecutionControlOperation::BarrierCtaSyncAligned
-        | ExecutionControlOperation::BarrierCtaArrive
-        | ExecutionControlOperation::BarrierCtaArriveAligned => {
-            writeln!(output, "declare void @{symbol}(i32, i32)\n").unwrap();
-            for (suffix, parameters, barrier_id, thread_count) in [
-                (
-                    "rr",
-                    "i32 %barrier_id, i32 %thread_count",
-                    "%barrier_id",
-                    "%thread_count",
-                ),
-                ("ri", "i32 %barrier_id", "%barrier_id", "32"),
-                ("ir", "i32 %thread_count", "1", "%thread_count"),
-                ("ii", "", "1", "32"),
-            ] {
-                writeln!(
-                    output,
-                    "define void @probe_{}_{suffix}({parameters}) #0 {{",
-                    record.id
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "  call void @{symbol}(i32 {barrier_id}, i32 {thread_count})"
-                )
-                .unwrap();
-                output.push_str("  ret void\n}\n\n");
-            }
-            output.push_str("attributes #0 = { convergent }\n");
-        }
-        ExecutionControlOperation::GridDependencyLaunchDependents
-        | ExecutionControlOperation::GridDependencyWait => {
-            writeln!(output, "declare void @{symbol}()\n").unwrap();
-            writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
-            writeln!(output, "  call void @{symbol}()").unwrap();
-            output.push_str("  ret void\n}\n");
-        }
-        ExecutionControlOperation::SetMaxNRegInc | ExecutionControlOperation::SetMaxNRegDec => {
-            writeln!(output, "declare void @{symbol}(i32)\n").unwrap();
-            writeln!(output, "define void @probe_{}() #0 {{", record.id).unwrap();
-            writeln!(output, "  call void @{symbol}(i32 64)").unwrap();
-            output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
-        }
-    }
-    output
-}
-
-fn render_tcgen05_mma_probe(
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-    hash: &str,
-    mma: &Tcgen05Mma,
-) -> String {
-    let (kind, b_buffer, b_usage) = mma.fixed_selectors.map_or(
-        (Tcgen05MmaKind::F16, 0, Tcgen05MmaBUsage::Discard),
-        |fixed| (fixed.kind, fixed.b_buffer, fixed.b_usage),
-    );
-    let (template, constraints) = if tcgen05_mma_is_ws(mma.form) {
-        tcgen05_mma_inline_asm(mma.form, kind, 1, None, Some(b_buffer), Some(b_usage))
-    } else {
-        tcgen05_mma_inline_asm(mma.form, kind, 1, Some("discard"), None, None)
-    };
-    let parameters = tcgen05_mma_runtime_parameters(mma);
-    let llvm_parameter = |(name, ty): &(&str, &str)| {
-        let ty = match *ty {
-            "u32" => "i32",
-            "u64" => "i64",
-            "bool" => "i1",
-            _ => unreachable!("closed tcgen05 MMA probe type"),
-        };
-        format!("{ty} %{name}")
-    };
-    let signature = parameters
-        .iter()
-        .map(llvm_parameter)
-        .collect::<Vec<_>>()
-        .join(", ");
-    let argument_indices: Vec<usize> =
-        if mma.alias.is_some() && mma.form == Tcgen05MmaForm::WsTensor {
-            vec![0, 1, 3, 4, 5]
-        } else {
-            (0..parameters.len()).collect()
-        };
-    let arguments = argument_indices
-        .iter()
-        .map(|&index| llvm_parameter(&parameters[index]))
-        .collect::<Vec<_>>()
-        .join(", ");
-
-    let mut output = llvm_header(catalog, hash);
-    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
-    writeln!(
-        output,
-        "; LLVM source: {}; route: inline PTX; source contract: {:?}",
-        llvm(record).symbol,
-        record.tcgen05.as_ref().unwrap().source_contract
-    )
-    .unwrap();
-    writeln!(
-        output,
-        "define void @probe_{}({signature}) #0 {{",
-        record.id
-    )
-    .unwrap();
-    writeln!(
-        output,
-        "  call void asm sideeffect {template:?}, {constraints:?}({arguments}) #0"
-    )
-    .unwrap();
-    output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
-    output
-}
-
-fn render_tcgen05_probe(catalog: &CatalogFile, record: &CatalogIntrinsic, hash: &str) -> String {
-    let tcgen05 = record.tcgen05.as_ref().expect("tcgen05 contract");
-    if let Some(mma) = &tcgen05.mma {
-        return render_tcgen05_mma_probe(catalog, record, hash, mma);
-    }
-    let operation = tcgen05.operation;
-    let mut output = llvm_header(catalog, hash);
-    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
-    writeln!(
-        output,
-        "; LLVM source: {}; route: inline PTX; source contract: {:?}",
-        llvm(record).symbol,
-        record.tcgen05.as_ref().unwrap().source_contract
-    )
-    .unwrap();
-    let (parameters, result_ty, template, constraints, arguments) = match operation {
-        Tcgen05Operation::Alloc | Tcgen05Operation::AllocCg2 => {
-            let group = if operation == Tcgen05Operation::AllocCg2 {
-                "2"
-            } else {
-                "1"
-            };
-            (
-                "ptr %dst, i32 %ncols".into(),
-                "void".into(),
-                format!(
-                    "{{ .reg .u64 %shared64; .reg .u32 %shared32; cvta.to.shared.u64 %shared64, $0; cvt.u32.u64 %shared32, %shared64; tcgen05.alloc.cta_group::{group}.sync.aligned.shared::cta.b32 [%shared32], $1; }}"
-                ),
-                "l,r,~{memory}".into(),
-                "ptr %dst, i32 %ncols".into(),
-            )
-        }
-        Tcgen05Operation::Dealloc | Tcgen05Operation::DeallocCg2 => {
-            let group = if operation == Tcgen05Operation::DeallocCg2 {
-                "2"
-            } else {
-                "1"
-            };
-            (
-                "i32 %tmem, i32 %ncols".into(),
-                "void".into(),
-                format!("tcgen05.dealloc.cta_group::{group}.sync.aligned.b32 $0, $1;"),
-                "r,r,~{memory}".into(),
-                "i32 %tmem, i32 %ncols".into(),
-            )
-        }
-        Tcgen05Operation::RelinquishAllocPermit | Tcgen05Operation::RelinquishAllocPermitCg2 => {
-            let group = if operation == Tcgen05Operation::RelinquishAllocPermitCg2 {
-                "2"
-            } else {
-                "1"
-            };
-            (
-                String::new(),
-                "void".into(),
-                format!("tcgen05.relinquish_alloc_permit.cta_group::{group}.sync.aligned;"),
-                "~{memory}".into(),
-                String::new(),
-            )
-        }
-        Tcgen05Operation::FenceBeforeThreadSync | Tcgen05Operation::FenceAfterThreadSync => {
-            let modifier = if operation == Tcgen05Operation::FenceBeforeThreadSync {
-                "before_thread_sync"
-            } else {
-                "after_thread_sync"
-            };
-            (
-                String::new(),
-                "void".into(),
-                format!("tcgen05.fence::{modifier};"),
-                "~{memory}".into(),
-                String::new(),
-            )
-        }
-        Tcgen05Operation::Commit
-        | Tcgen05Operation::CommitSharedCluster
-        | Tcgen05Operation::CommitCg2
-        | Tcgen05Operation::CommitSharedClusterCg2 => {
-            let group = if matches!(
-                operation,
-                Tcgen05Operation::CommitCg2 | Tcgen05Operation::CommitSharedClusterCg2
-            ) {
-                "2"
-            } else {
-                "1"
-            };
-            let shared = matches!(
-                operation,
-                Tcgen05Operation::CommitSharedCluster | Tcgen05Operation::CommitSharedClusterCg2
-            );
-            (
-                "i32 %mbar".into(),
-                "void".into(),
-                format!(
-                    "tcgen05.commit.cta_group::{group}.mbarrier::arrive::one{}.b64 [$0];",
-                    if shared { ".shared::cluster" } else { "" }
-                ),
-                "r,~{memory}".into(),
-                "i32 %mbar".into(),
-            )
-        }
-        Tcgen05Operation::MmaWsF16 | Tcgen05Operation::MmaWsBf16 | Tcgen05Operation::MmaWsTf32 => {
-            let kind = if operation == Tcgen05Operation::MmaWsTf32 {
-                "tf32"
-            } else {
-                "f16"
-            };
-            (
-                "i32 %d, i32 %a, i64 %legacy_a_desc, i64 %b, i32 %idesc, i1 %enable".into(),
-                "void".into(),
-                format!(
-                    "{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::{kind} [$0], [$1], $3, $4, %enable_pred; }}"
-                ),
-                "r,r,l,l,r,r,~{memory}".into(),
-                "i32 %d, i32 %a, i64 %legacy_a_desc, i64 %b, i32 %idesc, i1 %enable".into(),
-            )
-        }
-        Tcgen05Operation::MmaF16 | Tcgen05Operation::MmaF16Cg2 => {
-            let group = if operation == Tcgen05Operation::MmaF16Cg2 {
-                "2"
-            } else {
-                "1"
-            };
-            let zeros = if operation == Tcgen05Operation::MmaF16Cg2 {
-                "%z, %z, %z, %z, %z, %z, %z, %z"
-            } else {
-                "%z, %z, %z, %z"
-            };
-            (
-                "i32 %d, i64 %a, i64 %b, i32 %idesc, i1 %enable".into(),
-                "void".into(),
-                format!(
-                    "{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; .reg .u32 %z; mov.u32 %z, 0; tcgen05.mma.cta_group::{group}.kind::f16 [$0], $1, $2, $3, {{{zeros}}}, %enable_pred; }}"
-                ),
-                "r,l,l,r,r,~{memory}".into(),
-                "i32 %d, i64 %a, i64 %b, i32 %idesc, i1 %enable".into(),
-            )
-        }
-        Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2 => (
-            "i32 %tmem, i64 %desc".into(),
-            "void".into(),
-            format!(
-                "{}.{} [$0], $1;",
-                record.expected_ptx.mnemonic,
-                record.expected_ptx.modifiers.join(".")
-            ),
-            "r,l,~{memory}".into(),
-            "i32 %tmem, i64 %desc".into(),
-        ),
-        Tcgen05Operation::Ld16x256bX8Pure | Tcgen05Operation::Ld16x256bPure => {
-            let count = if operation == Tcgen05Operation::Ld16x256bX8Pure {
-                32
-            } else {
-                4
-            };
-            let registers = (0..count)
-                .map(|index| format!("${index}"))
-                .collect::<Vec<_>>()
-                .join(",");
-            let constraints = std::iter::repeat_n("=f", count)
-                .chain(std::iter::once("r"))
-                .collect::<Vec<_>>()
-                .join(",");
-            let fields = std::iter::repeat_n("float", count)
-                .collect::<Vec<_>>()
-                .join(", ");
-            (
-                "i32 %tmem".into(),
-                format!("{{ {fields} }}"),
-                format!(
-                    "tcgen05.ld.sync.aligned.16x256b.{}.b32 {{{registers}}}, [${count}];",
-                    if count == 32 { "x8" } else { "x1" }
-                ),
-                constraints,
-                "i32 %tmem".into(),
-            )
-        }
-        Tcgen05Operation::St => {
-            let count = tcgen05_st_register_count(record);
-            let has_half_split_offset = record
-                .tcgen05
-                .as_ref()
-                .and_then(|tcgen05| tcgen05.st)
-                .is_some_and(|st| st.shape == Tcgen05LdShape::M16x32bx2);
-            let parameters = std::iter::once("i32 %tmem".into())
-                .chain((0..count).map(|index| format!("i32 %d{index}")))
-                .collect::<Vec<_>>()
-                .join(", ");
-            let arguments = std::iter::once("i32 %tmem".into())
-                .chain(has_half_split_offset.then(|| "i64 16".into()))
-                .chain((0..count).map(|index| format!("i32 %d{index}")))
-                .collect::<Vec<_>>()
-                .join(", ");
-            let (template, constraints, _) = tcgen05_inline_asm(record);
-            (parameters, "void".into(), template, constraints, arguments)
-        }
-        Tcgen05Operation::Ld => {
-            let count = tcgen05_ld_register_count(record);
-            let has_half_split_offset = record
-                .tcgen05
-                .as_ref()
-                .and_then(|tcgen05| tcgen05.ld)
-                .is_some_and(|ld| ld.shape == Tcgen05LdShape::M16x32bx2);
-            let fields = std::iter::repeat_n("i32", count)
-                .collect::<Vec<_>>()
-                .join(", ");
-            let (template, constraints, _) = tcgen05_inline_asm(record);
-            (
-                "i32 %tmem".into(),
-                if count == 1 {
-                    "i32".into()
-                } else {
-                    format!("{{ {fields} }}")
-                },
-                template,
-                constraints,
-                if has_half_split_offset {
-                    "i32 %tmem, i64 16".into()
-                } else {
-                    "i32 %tmem".into()
-                },
-            )
-        }
-        Tcgen05Operation::LoadWait | Tcgen05Operation::StoreWait => {
-            let kind = if operation == Tcgen05Operation::LoadWait {
-                "ld"
-            } else {
-                "st"
-            };
-            (
-                String::new(),
-                "void".into(),
-                format!("tcgen05.wait::{kind}.sync.aligned;"),
-                "~{memory}".into(),
-                String::new(),
-            )
-        }
-        Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2 => {
-            let group = if operation == Tcgen05Operation::CommitMulticastCg2 {
-                2
-            } else {
-                1
-            };
-            (
-                "i32 %mbar, i16 %mask".into(),
-                "void".into(),
-                format!(
-                    "tcgen05.commit.cta_group::{group}.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;"
-                ),
-                "r,h,~{memory}".into(),
-                "i32 %mbar, i16 %mask".into(),
-            )
-        }
-        Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2 => {
-            let group = if operation == Tcgen05Operation::ShiftDownCg2 {
-                2
-            } else {
-                1
-            };
-            (
-                "i32 %tmem".into(),
-                "void".into(),
-                format!("tcgen05.shift.cta_group::{group}.down [$0];"),
-                "r,~{memory}".into(),
-                "i32 %tmem".into(),
-            )
-        }
-        Tcgen05Operation::Mma => unreachable!("generic MMA probe handled above"),
-    };
-    let (lowering_template, lowering_constraints, lowering_results) = tcgen05_inline_asm(record);
-    assert_eq!(template, lowering_template);
-    assert_eq!(constraints, lowering_constraints);
-    assert_eq!(result_ty != "void", lowering_results.is_some());
-    writeln!(
-        output,
-        "define void @probe_{}({parameters}) #0 {{",
-        record.id
-    )
-    .unwrap();
-    if result_ty == "void" {
-        writeln!(
-            output,
-            "  call void asm sideeffect {template:?}, {constraints:?}({arguments}) #0"
-        )
-        .unwrap();
-    } else {
-        writeln!(
-            output,
-            "  %result = call {result_ty} asm sideeffect {template:?}, {constraints:?}({arguments}) #0"
-        )
-        .unwrap();
-    }
-    output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
-    output
-}
-
-fn render_elect_probe(
-    catalog: &CatalogFile,
-    record: &CatalogIntrinsic,
-    hash: &str,
-    backend: IntrinsicBackend,
-) -> String {
-    let mut output = llvm_header(catalog, hash);
-    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
-    let mechanism = record
-        .backend_lowerings
-        .iter()
-        .find(|route| route.backend == backend)
-        .expect("elect backend route")
-        .mechanism;
-    match mechanism {
-        BackendLoweringMechanism::TypedNvvm => {
-            writeln!(
-                output,
-                "declare {{ i32, i1 }} @{}(i32) #0\n",
-                llvm(record).symbol
-            )
-            .unwrap();
-            for (suffix, parameters, mask) in
-                [("register", "i32 %mask", "%mask"), ("immediate", "", "-1")]
-            {
-                writeln!(
-                    output,
-                    "define {{ i32, i1 }} @probe_{}_{}_{suffix}({parameters}) #0 {{",
-                    record.id,
-                    backend_label(backend)
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "  %result = call {{ i32, i1 }} @{}(i32 {mask}) #0",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                output.push_str("  ret { i32, i1 } %result\n}\n");
-            }
-        }
-        BackendLoweringMechanism::InlinePtx => {
-            for (suffix, parameters, mask) in [
-                ("register", "i32 %mask", "%mask"),
-                ("constant_mask", "", "-1"),
-            ] {
-                writeln!(
-                    output,
-                    "define {{ i32, i1 }} @probe_{}_{}_{suffix}({parameters}) #0 {{",
-                    record.id,
-                    backend_label(backend)
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "  %raw = call {{ i32, i32 }} asm sideeffect \"{{ .reg .pred p; elect.sync $0|p, $2; selp.b32 $1, 1, 0, p; }}\", \"=r,=r,r\"(i32 {mask}) #0"
-                )
-                .unwrap();
-                output.push_str(
-                    "  %leader = extractvalue { i32, i32 } %raw, 0\n\
-                     \x20 %predicate.i32 = extractvalue { i32, i32 } %raw, 1\n\
-                     \x20 %predicate = trunc i32 %predicate.i32 to i1\n\
-                     \x20 %result.0 = insertvalue { i32, i1 } poison, i32 %leader, 0\n\
-                     \x20 %result.1 = insertvalue { i32, i1 } %result.0, i1 %predicate, 1\n\
-                     \x20 ret { i32, i1 } %result.1\n}\n",
-                );
-            }
-        }
-    }
-    output.push_str("\nattributes #0 = { convergent }\n");
-    output
-}
-
-pub(crate) fn render_probe(catalog: &CatalogFile, record: &CatalogIntrinsic, hash: &str) -> String {
-    if record.special_register.is_some() {
-        return render_special_register_probe(catalog, record, hash, IntrinsicBackend::LlvmNvptx);
-    }
-    if record.tma.is_some() {
-        return render_tma_probe(catalog, record, hash);
-    }
-    if ExecutionControlOperation::from_catalog_id(&record.id).is_some() {
-        return render_execution_control_probe(catalog, record, hash);
-    }
-    if record.tcgen05.is_some() {
-        return render_tcgen05_probe(catalog, record, hash);
-    }
-    if record.family == "elect" {
-        return render_elect_probe(catalog, record, hash, IntrinsicBackend::LlvmNvptx);
-    }
-    let mut output = llvm_header(catalog, hash);
-    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
-    if let Some(cluster) = &record.cluster_memory {
-        let (template, constraints) =
-            crate::resolve::cluster_memory_inline_recipe(cluster.operation);
-        match cluster.operation {
-            ClusterMemoryOperation::MapSharedRank => {
-                writeln!(
-                    output,
-                    "define ptr addrspace(7) @probe_{}(ptr %source_generic, i32 %rank) #0 {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %source = addrspacecast ptr %source_generic to ptr addrspace(3)\n",
-                );
-                writeln!(
-                    output,
-                    "  %mapped_integer = call i64 asm sideeffect {template:?}, {constraints:?}(ptr addrspace(3) %source, i32 %rank) #0"
-                )
-                .unwrap();
-                output.push_str(
-                    "  %mapped = inttoptr i64 %mapped_integer to ptr addrspace(7)\n  ret ptr addrspace(7) %mapped\n}\n\nattributes #0 = { convergent }\n",
-                );
-            }
-            ClusterMemoryOperation::ReadU32 => {
-                writeln!(
-                    output,
-                    "define i32 @probe_{}(ptr %source_generic, i32 %rank) #0 {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %source = addrspacecast ptr %source_generic to ptr addrspace(3)\n",
-                );
-                writeln!(
-                    output,
-                    "  %value = call i32 asm sideeffect {template:?}, {constraints:?}(ptr addrspace(3) %source, i32 %rank) #0"
-                )
-                .unwrap();
-                output.push_str("  ret i32 %value\n}\n\nattributes #0 = { convergent }\n");
-            }
-        }
-    } else if let Some(clc) = &record.clc {
-        match clc.adapter {
-            ClcAdapter::GenericPointersToShared => {
-                writeln!(
-                    output,
-                    "declare void @{}(ptr addrspace(3), ptr addrspace(3))\n",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "define void @probe_{}(ptr %response_generic, ptr %mbarrier_generic) {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %response = addrspacecast ptr %response_generic to ptr addrspace(3)\n\
-                     \x20 %mbarrier = addrspacecast ptr %mbarrier_generic to ptr addrspace(3)\n",
-                );
-                writeln!(
-                    output,
-                    "  call void @{}(ptr addrspace(3) %response, ptr addrspace(3) %mbarrier)",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                output.push_str("  ret void\n}\n");
-            }
-            ClcAdapter::PairU64ToI128BoolToU32 | ClcAdapter::PairU64ToI128U32 => {
-                let llvm_result = if clc.adapter == ClcAdapter::PairU64ToI128BoolToU32 {
-                    "i1"
-                } else {
-                    "i32"
-                };
-                writeln!(
-                    output,
-                    "declare {llvm_result} @{}(i128)\n",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "define i32 @probe_{}(i64 %response_low, i64 %response_high) {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %response_low_i128 = zext i64 %response_low to i128\n\
-                     \x20 %response_high_i128 = zext i64 %response_high to i128\n\
-                     \x20 %response_high_shifted = shl i128 %response_high_i128, 64\n\
-                     \x20 %response = or i128 %response_low_i128, %response_high_shifted\n",
-                );
-                writeln!(
-                    output,
-                    "  %raw_result = call {llvm_result} @{}(i128 %response)",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                if clc.adapter == ClcAdapter::PairU64ToI128BoolToU32 {
-                    output.push_str(
-                        "  %result = zext i1 %raw_result to i32\n\
-                         \x20 ret i32 %result\n}\n",
-                    );
-                } else {
-                    output.push_str("  ret i32 %raw_result\n}\n");
-                }
-            }
-        }
-    } else if let Some(bridge) = &record.cp_async_mbarrier {
-        let shared = bridge.state_space == CpAsyncMbarrierStateSpace::Shared;
-        let pointer_type = if shared { "ptr addrspace(3)" } else { "ptr" };
-        writeln!(
-            output,
-            "declare void @{}({pointer_type})\n",
-            llvm(record).symbol
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "define void @probe_{}(ptr %barrier_generic) {{",
-            record.id
-        )
-        .unwrap();
-        if shared {
-            output
-                .push_str("  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n");
-            writeln!(
-                output,
-                "  call void @{}(ptr addrspace(3) %barrier)",
-                llvm(record).symbol
-            )
-            .unwrap();
-        } else {
-            writeln!(
-                output,
-                "  call void @{}(ptr %barrier_generic)",
-                llvm(record).symbol
-            )
-            .unwrap();
-        }
-        output.push_str("  ret void\n}\n");
-    } else if let Some(mbarrier) = &record.mbarrier_basic {
-        match mbarrier.operation {
-            MbarrierBasicOperation::Init => {
-                writeln!(
-                    output,
-                    "declare void @{}(ptr addrspace(3), i32)\n",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "define void @probe_{}(ptr %barrier_generic, i32 %expected_count) {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
-                );
-                writeln!(
-                    output,
-                    "  call void @{}(ptr addrspace(3) %barrier, i32 %expected_count)",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                output.push_str("  ret void\n}\n");
-            }
-            MbarrierBasicOperation::Arrive => {
-                writeln!(
-                    output,
-                    "declare i64 @{}(ptr addrspace(3))\n",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "define i64 @probe_{}(ptr %barrier_generic) {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
-                );
-                writeln!(
-                    output,
-                    "  %token = call i64 @{}(ptr addrspace(3) %barrier)",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                output.push_str("  ret i64 %token\n}\n");
-            }
-            MbarrierBasicOperation::TestWait => {
-                writeln!(
-                    output,
-                    "define i1 @probe_{}(ptr %barrier_generic, i64 %token) #0 {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n\
-                     \x20 %result_i32 = call i32 asm sideeffect \"{ .reg .pred %p0; mbarrier.test_wait.shared.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }\", \"=r,l,l,~{memory}\"(ptr addrspace(3) %barrier, i64 %token) #0\n\
-                     \x20 %result = trunc i32 %result_i32 to i1\n\
-                     \x20 ret i1 %result\n\
-                     }\n\n\
-                     attributes #0 = { convergent }\n",
-                );
-            }
-            MbarrierBasicOperation::Inval => {
-                writeln!(
-                    output,
-                    "declare void @{}(ptr addrspace(3))\n",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "define void @probe_{}(ptr %barrier_generic) {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
-                );
-                writeln!(
-                    output,
-                    "  call void @{}(ptr addrspace(3) %barrier)",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                output.push_str("  ret void\n}\n");
-            }
-        }
-    } else if record.movmatrix.is_some() {
-        writeln!(output, "define i32 @probe_{}(i32 %value) #0 {{", record.id).unwrap();
-        writeln!(
-            output,
-            "  %result = call i32 asm {:?}, \"=r,r\"(i32 %value) #0",
-            movmatrix_template(record),
-        )
-        .unwrap();
-        output.push_str("  ret i32 %result\n}\n\nattributes #0 = { convergent }\n");
-    } else if let Some(mbarrier) = &record.mbarrier_extended {
-        let (template, constraints) =
-            crate::resolve::mbarrier_extended_inline_recipe(mbarrier.operation);
-        match mbarrier.adapter {
-            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount => {
-                writeln!(
-                    output,
-                    "define i64 @probe_{}(ptr %barrier_generic, i32 %bytes) #0 {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
-                );
-                writeln!(
-                    output,
-                    "  %token = call i64 asm sideeffect {template:?}, {constraints:?}(ptr addrspace(3) %barrier, i32 %bytes) #0"
-                )
-                .unwrap();
-                output.push_str("  ret i64 %token\n}\n\nattributes #0 = { convergent }\n");
-            }
-            MbarrierExtendedAdapter::PointerTokenToPredicate => {
-                writeln!(
-                    output,
-                    "define i1 @probe_{}(ptr %barrier_generic, i64 %token) #0 {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
-                );
-                writeln!(
-                    output,
-                    "  %result_i32 = call i32 asm sideeffect {template:?}, {constraints:?}(ptr addrspace(3) %barrier, i64 %token) #0"
-                )
-                .unwrap();
-                output.push_str(
-                    "  %result = trunc i32 %result_i32 to i1\n  ret i1 %result\n}\n\nattributes #0 = { convergent }\n",
-                );
-            }
-            MbarrierExtendedAdapter::PointerParityToPredicate => {
-                writeln!(
-                    output,
-                    "define i1 @probe_{}(ptr %barrier_generic, i32 %parity) #0 {{",
-                    record.id
-                )
-                .unwrap();
-                output.push_str(
-                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
-                );
-                writeln!(
-                    output,
-                    "  %result_i32 = call i32 asm sideeffect {template:?}, {constraints:?}(ptr addrspace(3) %barrier, i32 %parity) #0"
-                )
-                .unwrap();
-                output.push_str(
-                    "  %result = trunc i32 %result_i32 to i1\n  ret i1 %result\n}\n\nattributes #0 = { convergent }\n",
-                );
-            }
-            MbarrierExtendedAdapter::RawClusterAddressToVoid => {
-                writeln!(
-                    output,
-                    "define void @probe_{}(i64 %address) #0 {{",
-                    record.id
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "  call void asm sideeffect {template:?}, {constraints:?}(i64 %address) #0"
-                )
-                .unwrap();
-                output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
-            }
-            MbarrierExtendedAdapter::ZeroOperandsToVoid => {
-                writeln!(output, "define void @probe_{}() #0 {{", record.id).unwrap();
-                writeln!(
-                    output,
-                    "  call void asm sideeffect {template:?}, {constraints:?}() #0"
-                )
-                .unwrap();
-                output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
-            }
-            MbarrierExtendedAdapter::NanosecondsToVoid => {
-                writeln!(output, "define void @probe_{}(i32 %ns) #0 {{", record.id).unwrap();
-                writeln!(
-                    output,
-                    "  call void asm sideeffect {template:?}, {constraints:?}(i32 %ns) #0"
-                )
-                .unwrap();
-                output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
-            }
-        }
-    } else if record.integer_minmax.is_some() {
-        let parameters = "i32 %arg0, i32 %arg1";
-        writeln!(output, "define i32 @probe_{}({parameters}) {{", record.id).unwrap();
-        writeln!(
-            output,
-            "  %result = call i32 asm \"{} $0, $1, $2;\", \"=r,r,r\"(i32 %arg0, i32 %arg1)",
-            integer_minmax_ptx_mnemonic(record)
-        )
-        .unwrap();
-        output.push_str("  ret i32 %result\n}\n");
-    } else if record.packed_alu.is_some() {
-        let arity = record.rust.arguments.len();
-        let width = packed_alu_width(record);
-        let llvm_type = format!("i{width}");
-        let register_constraint = packed_alu_register_constraint(record);
-        let parameters = (0..arity)
-            .map(|index| format!("{llvm_type} %arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let arguments = (0..arity)
-            .map(|index| format!("{llvm_type} %arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let operands = (0..=arity)
-            .map(|index| format!("${index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let constraints = std::iter::once(format!("={register_constraint}"))
-            .chain(std::iter::repeat_n(register_constraint.to_owned(), arity))
-            .collect::<Vec<_>>()
-            .join(",");
-        writeln!(
-            output,
-            "define {llvm_type} @probe_{}({parameters}) {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "  %result = call {llvm_type} asm \"{} {operands};\", \"{constraints}\"({arguments})",
-            packed_alu_ptx_mnemonic(record)
-        )
-        .unwrap();
-        writeln!(output, "  ret {llvm_type} %result\n}}").unwrap();
-    } else if record.packed_conversion.is_some() {
-        let result_ty = packed_conversion_dialect_type(record);
-        if packed_conversion_typed_llvm_name(record).is_some() {
-            let llvm = llvm(record);
-            let symbol = llvm.resolved_symbol.as_deref().unwrap_or(&llvm.symbol);
-            writeln!(output, "declare {result_ty} @{symbol}(float, float)\n").unwrap();
-            writeln!(
-                output,
-                "define {result_ty} @probe_{}(float %low, float %high) {{",
-                record.id,
-            )
-            .unwrap();
-            writeln!(
-                output,
-                "  %result = call {result_ty} @{symbol}(float %high, float %low)"
-            )
-            .unwrap();
-        } else if packed_conversion_source(record) == PackedConversionSourceFormat::F32x2 {
-            writeln!(
-                output,
-                "define {result_ty} @probe_{}(float %low, float %high) {{",
-                record.id,
-            )
-            .unwrap();
-            writeln!(
-                output,
-                "  %result = call {result_ty} asm \"{} $0, $2, $1;\", \"{}\"(float %low, float %high)",
-                packed_conversion_ptx_mnemonic(record),
-                packed_conversion_constraint(record),
-            )
-            .unwrap();
-        } else {
-            // A packed source arrives in one integer register, so the probe
-            // takes a single operand and needs no reordering.
-            let source_ty = format!("i{}", packed_conversion_source_width(record));
-            writeln!(
-                output,
-                "define {result_ty} @probe_{}({source_ty} %packed) {{",
-                record.id,
-            )
-            .unwrap();
-            writeln!(
-                output,
-                "  %result = call {result_ty} asm \"{} $0, $1;\", \"{}\"({source_ty} %packed)",
-                packed_conversion_ptx_mnemonic(record),
-                packed_conversion_constraint(record),
-            )
-            .unwrap();
-        }
-        writeln!(output, "  ret {result_ty} %result\n}}").unwrap();
-    } else if let Some(packed) = &record.packed_atomic {
-        let format = match packed.format {
-            PackedAtomicFormat::F16x2 => "f16x2",
-            PackedAtomicFormat::Bf16x2 => "bf16x2",
-        };
-        writeln!(
-            output,
-            "define i32 @probe_{}(ptr %address, i32 %addend) {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "  %old = call i32 asm sideeffect \"atom.global.add.noftz.{format} $0, [$1], $2;\", \"=r,l,r,~{{memory}}\"(ptr %address, i32 %addend)"
-        )
-        .unwrap();
-        output.push_str("  ret i32 %old\n}\n");
-    } else if let Some(copy) = &record.cp_async_copy {
-        let dynamic_source_size = copy.source_size == CpAsyncSourceSize::Runtime;
-        let declaration_arguments = if dynamic_source_size {
-            "ptr addrspace(3), ptr addrspace(1), i32"
-        } else {
-            "ptr addrspace(3), ptr addrspace(1)"
-        };
-        writeln!(
-            output,
-            "declare void @{}({declaration_arguments})",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push('\n');
-        if dynamic_source_size {
-            writeln!(
-                output,
-                "define void @probe_{}_register(ptr %shared_generic, ptr %global_generic, i32 %source_size) {{",
-                record.id
-            )
-            .unwrap();
-            output.push_str(
-                "  %shared = addrspacecast ptr %shared_generic to ptr addrspace(3)\n  %global = addrspacecast ptr %global_generic to ptr addrspace(1)\n",
-            );
-            writeln!(
-                output,
-                "  call void @{}(ptr addrspace(3) %shared, ptr addrspace(1) %global, i32 %source_size)",
-                llvm(record).symbol
-            )
-            .unwrap();
-            output.push_str("  ret void\n}\n");
-            writeln!(
-                output,
-                "define void @probe_{}_immediate(ptr %shared_generic, ptr %global_generic) {{",
-                record.id
-            )
-            .unwrap();
-            output.push_str(
-                "  %shared = addrspacecast ptr %shared_generic to ptr addrspace(3)\n  %global = addrspacecast ptr %global_generic to ptr addrspace(1)\n",
-            );
-            writeln!(
-                output,
-                "  call void @{}(ptr addrspace(3) %shared, ptr addrspace(1) %global, i32 3)",
-                llvm(record).symbol
-            )
-            .unwrap();
-            output.push_str("  ret void\n}\n");
-        } else {
-            writeln!(
-                output,
-                "define void @probe_{}(ptr %shared_generic, ptr %global_generic) {{",
-                record.id
-            )
-            .unwrap();
-            output.push_str(
-                "  %shared = addrspacecast ptr %shared_generic to ptr addrspace(3)\n  %global = addrspacecast ptr %global_generic to ptr addrspace(1)\n",
-            );
-            writeln!(
-                output,
-                "  call void @{}(ptr addrspace(3) %shared, ptr addrspace(1) %global)",
-                llvm(record).symbol
-            )
-            .unwrap();
-            output.push_str("  ret void\n}\n");
-        }
-    } else if let Some(control) = &record.cp_async_control {
-        let has_immediate = control.operation == CpAsyncControlOperation::WaitGroup;
-        let declaration_arguments = if has_immediate { "i32" } else { "" };
-        writeln!(
-            output,
-            "declare void @{}({declaration_arguments})",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push('\n');
-        writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
-        if has_immediate {
-            writeln!(output, "  call void @{}(i32 3)", llvm(record).symbol).unwrap();
-        } else {
-            writeln!(output, "  call void @{}()", llvm(record).symbol).unwrap();
-        }
-        output.push_str("  ret void\n}\n");
-    } else if let Some(control) = &record.wgmma_control {
-        if control.mode == WgmmaControlMode::WaitGroup {
-            writeln!(
-                output,
-                "declare void @{}(i64 immarg) #0\n",
-                llvm(record).symbol
-            )
-            .unwrap();
-        } else {
-            writeln!(output, "declare void @{}() #0\n", llvm(record).symbol).unwrap();
-        }
-        writeln!(output, "define void @probe_{}() #0 {{", record.id).unwrap();
-        if control.mode == WgmmaControlMode::WaitGroup {
-            writeln!(output, "  call void @{}(i64 0) #0", llvm(record).symbol,).unwrap();
-        } else {
-            writeln!(output, "  call void @{}() #0", llvm(record).symbol,).unwrap();
-        }
-        output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
-    } else if record.cluster_barrier.is_some() {
-        writeln!(output, "declare void @{}() #0", llvm(record).symbol).unwrap();
-        output.push('\n');
-        writeln!(output, "define void @probe_{}() #0 {{", record.id).unwrap();
-        writeln!(output, "  call void @{}() #0", llvm(record).symbol).unwrap();
-        output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
-    } else if record.family == "sync" {
-        let arguments = if record.id == "sync_threads" {
-            "i32"
-        } else {
-            debug_assert!(threadfence_ptx_level(record).is_some());
-            ""
-        };
-        writeln!(output, "declare void @{}({arguments})", llvm(record).symbol).unwrap();
-        output.push('\n');
-        writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
-        let call_arguments = if record.id == "sync_threads" {
-            "i32 0"
-        } else {
-            ""
-        };
-        writeln!(
-            output,
-            "  call void @{}({call_arguments})",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push_str("  ret void\n}\n");
-    } else if let Some(warp_barrier) = &record.warp_barrier {
-        debug_assert_eq!(warp_barrier.adapter, WarpBarrierAdapter::DirectMemberMask);
-        writeln!(output, "declare void @{}(i32)", llvm(record).symbol).unwrap();
-        output.push('\n');
-        writeln!(
-            output,
-            "define void @probe_{}(i32 %member_mask) {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "  call void @{}(i32 %member_mask)",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push_str("  ret void\n}\n");
-        writeln!(output, "define void @probe_{}_immediate() {{", record.id).unwrap();
-        writeln!(output, "  call void @{}(i32 -1)", llvm(record).symbol).unwrap();
-        output.push_str("  ret void\n}\n");
-    } else if let Some(dot) = &record.dot_product {
-        match dot.adapter {
-            DotProductAdapter::DirectThreeOperands => {
-                writeln!(
-                    output,
-                    "declare i32 @{}(i32, i32, i32)",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                output.push('\n');
-                writeln!(
-                    output,
-                    "define i32 @probe_{}(i32 %a, i32 %b, i32 %c) {{",
-                    record.id
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "  %result = call i32 @{}(i32 %a, i32 %b, i32 %c)",
-                    llvm(record).symbol
-                )
-                .unwrap();
-            }
-            DotProductAdapter::InsertLowHalfFalse => {
-                writeln!(
-                    output,
-                    "declare i32 @{}(i32, i32, i1, i32)",
-                    llvm(record).symbol
-                )
-                .unwrap();
-                output.push('\n');
-                writeln!(
-                    output,
-                    "define i32 @probe_{}(i32 %a, i32 %b, i32 %c) {{",
-                    record.id
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "  %result = call i32 @{}(i32 %a, i32 %b, i1 false, i32 %c)",
-                    llvm(record).symbol
-                )
-                .unwrap();
-            }
-        }
-        output.push_str("  ret i32 %result\n}\n");
-    } else if let Some(vote) = &record.vote {
-        debug_assert_eq!(vote.adapter, VoteAdapter::DirectMaskPredicate);
-        let result_ty = match vote.mode {
-            VoteMode::All | VoteMode::Any | VoteMode::Uni => "i1",
-            VoteMode::Ballot => "i32",
-        };
-        writeln!(
-            output,
-            "declare {result_ty} @{}(i32, i1)",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push('\n');
-        writeln!(
-            output,
-            "define {result_ty} @probe_{}(i32 %member_mask, i1 %predicate) {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "  %result = call {result_ty} @{}(i32 %member_mask, i1 %predicate)",
-            llvm(record).symbol
-        )
-        .unwrap();
-        writeln!(output, "  ret {result_ty} %result\n}}").unwrap();
-        writeln!(
-            output,
-            "define {result_ty} @probe_{}_immediate(i1 %predicate) {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "  %result = call {result_ty} @{}(i32 -1, i1 %predicate)",
-            llvm(record).symbol
-        )
-        .unwrap();
-        writeln!(output, "  ret {result_ty} %result\n}}").unwrap();
-    } else if let Some(warp_match) = &record.warp_match {
-        let value_ty = format!("i{}", warp_match.value_width.bits());
-        let result_ty = match warp_match.mode {
-            WarpMatchMode::Any => "i32".to_owned(),
-            WarpMatchMode::All => "{ i32, i1 }".to_owned(),
-        };
-        writeln!(
-            output,
-            "declare {result_ty} @{}(i32, {value_ty})",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push('\n');
-        let forms = [
-            (
-                "rr",
-                "i32 %member_mask, ",
-                "i32 %member_mask",
-                format!("{value_ty} %value"),
-            ),
-            ("ri", "", "i32 -1", format!("{value_ty} %value")),
-            (
-                "ir",
-                "i32 %member_mask",
-                "i32 %member_mask",
-                format!("{value_ty} 7"),
-            ),
-            ("ii", "", "i32 -1", format!("{value_ty} 7")),
-        ];
-        for (suffix, first_parameter, mask, value) in forms {
-            let parameters = match suffix {
-                "rr" => format!("{first_parameter}{value_ty} %value"),
-                "ri" => format!("{value_ty} %value"),
-                "ir" => first_parameter.to_owned(),
-                "ii" => String::new(),
-                _ => unreachable!(),
-            };
-            writeln!(
-                output,
-                "define {result_ty} @probe_{}_{suffix}({parameters}) {{",
-                record.id
-            )
-            .unwrap();
-            writeln!(
-                output,
-                "  %result = call {result_ty} @{}({mask}, {value})",
-                llvm(record).symbol
-            )
-            .unwrap();
-            writeln!(output, "  ret {result_ty} %result\n}}").unwrap();
-        }
-    } else if let Some(warp_shuffle) = &record.warp_shuffle {
-        if warp_shuffle.value_kind == WarpShuffleValueKind::I64 {
-            debug_assert_eq!(
-                warp_shuffle.adapter,
-                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
-            );
-            let mode = match warp_shuffle.mode {
-                WarpShuffleMode::Idx => "idx",
-                WarpShuffleMode::Bfly => "bfly",
-                WarpShuffleMode::Down => "down",
-                WarpShuffleMode::Up => "up",
-            };
-            let asm = format!(
-                "{{ .reg .b32 lo; .reg .b32 hi; mov.b64 {{lo, hi}}, $1; shfl.sync.{mode}.b32 lo, lo, $2, {}, $3; shfl.sync.{mode}.b32 hi, hi, $2, {}, $3; mov.b64 $0, {{lo, hi}}; }}",
-                warp_shuffle.clamp, warp_shuffle.clamp
-            );
-            writeln!(
-                output,
-                "define i64 @probe_{}(i32 %member_mask, i64 %value, i32 %lane) #0 {{",
-                record.id
-            )
-            .unwrap();
-            writeln!(
-                output,
-                "  %result = call i64 asm sideeffect {asm:?}, \"=l,l,r,r\"(i64 %value, i32 %lane, i32 %member_mask) #0"
-            )
-            .unwrap();
-            output.push_str("  ret i64 %result\n}\n\nattributes #0 = { convergent }\n");
-        } else {
-            debug_assert_eq!(
-                warp_shuffle.adapter,
-                WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp
-            );
-            let value_ty = match warp_shuffle.value_kind {
-                WarpShuffleValueKind::I32 => "i32",
-                WarpShuffleValueKind::F32 => "float",
-                WarpShuffleValueKind::I64 => unreachable!(),
-            };
-            writeln!(
-                output,
-                "declare {value_ty} @{}(i32, {value_ty}, i32, i32)",
-                llvm(record).symbol
-            )
-            .unwrap();
-            output.push('\n');
-            let forms = [
-                (
-                    "rr",
-                    format!("i32 %member_mask, {value_ty} %value, i32 %lane"),
-                    "i32 %member_mask",
-                    "i32 %lane",
-                ),
-                (
-                    "ri",
-                    format!("{value_ty} %value, i32 %lane"),
-                    "i32 -1",
-                    "i32 %lane",
-                ),
-                (
-                    "ir",
-                    format!("i32 %member_mask, {value_ty} %value"),
-                    "i32 %member_mask",
-                    "i32 1",
-                ),
-                ("ii", format!("{value_ty} %value"), "i32 -1", "i32 1"),
-            ];
-            for (suffix, parameters, member_mask, lane) in forms {
-                writeln!(
-                    output,
-                    "define {value_ty} @probe_{}_{suffix}({parameters}) {{",
-                    record.id
-                )
-                .unwrap();
-                writeln!(
-                    output,
-                    "  %result = call {value_ty} @{}({member_mask}, {value_ty} %value, {lane}, i32 {})",
-                    llvm(record).symbol,
-                    warp_shuffle.clamp,
-                )
-                .unwrap();
-                writeln!(output, "  ret {value_ty} %result\n}}").unwrap();
-            }
-        }
-    } else if let Some(redux) = &record.redux {
-        debug_assert_eq!(redux.adapter, ReduxAdapter::MaskValueToSourceMemberMask);
-        let value_type = match llvm(record).results[0].as_str() {
-            "i32" => "i32",
-            "f32" => "float",
-            other => panic!("unsupported redux value type {other}"),
-        };
-        writeln!(
-            output,
-            "declare {value_type} @{}({value_type}, i32)",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push('\n');
-        writeln!(
-            output,
-            "define {value_type} @probe_{}(i32 %member_mask, {value_type} %value) {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "  %result = call {value_type} @{}({value_type} %value, i32 %member_mask)",
-            llvm(record).symbol
-        )
-        .unwrap();
-        writeln!(output, "  ret {value_type} %result\n}}").unwrap();
-    } else if let Some(sparse_mma) = &record.sparse_mma {
-        let accumulator = match sparse_mma.accumulator {
-            SparseMmaAccumulator::F16 => "i32",
-            SparseMmaAccumulator::F32 => "float",
-            SparseMmaAccumulator::S32 => "i32",
-        };
-        let (c_count, a_count, b_count, d_count) = sparse_mma_fragment_counts(record);
-        let result = format!(
-            "{{ {} }}",
-            std::iter::repeat_n(accumulator, d_count)
-                .collect::<Vec<_>>()
-                .join(", ")
-        );
-        let parameters = (0..c_count)
-            .map(|index| format!("{accumulator} %c{index}"))
-            .chain((0..a_count).map(|index| format!("i32 %a{index}")))
-            .chain((0..b_count).map(|index| format!("i32 %b{index}")))
-            .chain(std::iter::once("i32 %metadata".to_owned()))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let arguments = (0..c_count)
-            .map(|index| format!("{accumulator} %c{index}"))
-            .chain((0..a_count).map(|index| format!("i32 %a{index}")))
-            .chain((0..b_count).map(|index| format!("i32 %b{index}")))
-            .chain(std::iter::once("i32 %metadata".to_owned()))
-            .collect::<Vec<_>>()
-            .join(", ");
-        for selector in sparse_mma_selector_values(record) {
-            writeln!(
-                output,
-                "define {result} @probe_{}_selector_{selector}({parameters}) #0 {{",
-                record.id
-            )
-            .unwrap();
-            writeln!(
-                output,
-                "  %result = call {result} asm sideeffect {:?}, {:?}({arguments}, i32 {selector}) #0",
-                sparse_mma_template(record),
-                sparse_mma_constraints(record),
-            )
-            .unwrap();
-            writeln!(output, "  ret {result} %result\n}}").unwrap();
-        }
-        output.push_str("\nattributes #0 = { convergent }\n");
-    } else if let Some(mma) = &record.register_mma {
-        let (c_count, a_count, b_count, d_count) = register_mma_fragment_counts(record);
-        let (c_type, packed_type, result_type) = match mma.adapter {
-            RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32
-            | RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => ("i32", "i32", "i32"),
-            RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
-            | RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32
-            | RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => {
-                ("float", "i32", "float")
-            }
-            RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 => ("double", "double", "double"),
-            RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32
-            | RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32
-            | RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => ("i32", "i32", "i32"),
-        };
-        let mut parameter_values = (0..c_count)
-            .map(|index| format!("{c_type} %c{index}"))
-            .chain((0..a_count).map(|index| format!("{packed_type} %a{index}")))
-            .chain((0..b_count).map(|index| format!("{packed_type} %b{index}")))
-            .collect::<Vec<_>>();
-        let mut argument_values = (0..c_count)
-            .map(|index| format!("{c_type} %c{index}"))
-            .chain((0..a_count).map(|index| format!("{packed_type} %a{index}")))
-            .chain((0..b_count).map(|index| format!("{packed_type} %b{index}")))
-            .collect::<Vec<_>>();
-        if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 {
-            let block_scale_parameters = [
-                "i32 %scale_a",
-                "i16 %byte_id_a",
-                "i16 %thread_id_a",
-                "i32 %scale_b",
-                "i16 %byte_id_b",
-                "i16 %thread_id_b",
-            ];
-            parameter_values.extend(block_scale_parameters.map(str::to_owned));
-            argument_values.extend(block_scale_parameters.map(str::to_owned));
-        }
-        let parameters = parameter_values.join(", ");
-        let arguments = argument_values.join(", ");
-        let result = format!(
-            "{{ {} }}",
-            std::iter::repeat_n(result_type, d_count)
-                .collect::<Vec<_>>()
-                .join(", ")
-        );
-        writeln!(
-            output,
-            "define {result} @probe_{}({parameters}) #0 {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "  %result = call {result} asm sideeffect {:?}, {:?}({arguments}) #0",
-            register_mma_template(record),
-            register_mma_constraints(record),
-        )
-        .unwrap();
-        output.push_str("  ret ");
-        output.push_str(&result);
-        output.push_str(" %result\n}\n\nattributes #0 = { convergent }\n");
-    } else if let Some(debug) = &record.debug_control {
-        let template = match debug.operation {
-            DebugControlOperation::Trap => "trap;",
-            DebugControlOperation::Breakpoint => "brkpt;",
-            DebugControlOperation::Pmevent => "pmevent 15;",
-        };
-        writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
-        writeln!(output, "  call void asm sideeffect {:?}, \"\"()", template).unwrap();
-        output.push_str("  ret void\n}\n");
-    } else if record.family == "stmatrix" {
-        let (multiplicity, _) = stmatrix_variant(record).expect("stmatrix variant");
-        let count = multiplicity.register_count();
-        let symbol = llvm(record)
-            .resolved_symbol
-            .as_ref()
-            .expect("stmatrix resolved symbol");
-        let declaration = std::iter::once("ptr addrspace(3)".to_owned())
-            .chain(std::iter::repeat_n("i32".to_owned(), count))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let parameters = std::iter::once("ptr %generic".to_owned())
-            .chain((0..count).map(|index| format!("i32 %r{index}")))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let arguments = std::iter::once("ptr addrspace(3) %shared".to_owned())
-            .chain((0..count).map(|index| format!("i32 %r{index}")))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(output, "declare void @{symbol}({declaration})\n").unwrap();
-        writeln!(output, "define void @probe_{}({parameters}) {{", record.id).unwrap();
-        output.push_str("  %shared = addrspacecast ptr %generic to ptr addrspace(3)\n");
-        writeln!(output, "  call void @{symbol}({arguments})").unwrap();
-        output.push_str("  ret void\n}\n");
-    } else if record.prmt.is_some() {
-        let arity = record.rust.arguments.len();
-        let declaration = std::iter::repeat_n("i32", arity)
-            .collect::<Vec<_>>()
-            .join(", ");
-        let parameters = (0..arity)
-            .map(|index| format!("i32 %arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let arguments = (0..arity)
-            .map(|index| format!("i32 %arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(
-            output,
-            "declare i32 @{}({declaration})\n",
-            llvm(record).symbol
-        )
-        .unwrap();
-        writeln!(output, "define i32 @probe_{}({parameters}) {{", record.id).unwrap();
-        writeln!(
-            output,
-            "  %result = call i32 @{}({arguments})",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push_str("  ret i32 %result\n}\n");
-    } else if let Some(ldmatrix) = &record.ldmatrix {
-        let register_count = ldmatrix.variant.register_count();
-        let result_ty = if register_count == 1 {
-            "i32".to_owned()
-        } else {
-            format!(
-                "{{ {} }}",
-                std::iter::repeat_n("i32", register_count)
-                    .collect::<Vec<_>>()
-                    .join(", ")
-            )
-        };
-        let symbol = record
-            .llvm
-            .as_ref()
-            .expect("ldmatrix LLVM facts")
-            .resolved_symbol
-            .as_ref()
-            .expect("ldmatrix resolved symbol");
-        writeln!(output, "declare {result_ty} @{symbol}(ptr addrspace(3))").unwrap();
-        output.push('\n');
-        writeln!(
-            output,
-            "define {result_ty} @probe_{}(ptr %generic) {{",
-            record.id
-        )
-        .unwrap();
-        output.push_str("  %shared = addrspacecast ptr %generic to ptr addrspace(3)\n");
-        writeln!(
-            output,
-            "  %result = call {result_ty} @{symbol}(ptr addrspace(3) %shared)"
-        )
-        .unwrap();
-        writeln!(output, "  ret {result_ty} %result\n}}\n").unwrap();
-    } else if record.scalar_arithmetic.is_some() {
-        let ty = scalar_arithmetic_llvm_type(record);
-        let arity = scalar_arithmetic_arity(record);
-        let parameters = (0..arity)
-            .map(|index| format!("{ty} %arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let arguments = (0..arity)
-            .map(|index| format!("{ty} %arg{index}"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        if scalar_arithmetic_llvm_mechanism(record) == BackendLoweringMechanism::TypedNvvm {
-            let declaration = std::iter::repeat_n(ty, arity)
-                .collect::<Vec<_>>()
-                .join(", ");
-            writeln!(
-                output,
-                "declare {ty} @{}({declaration})\n",
-                llvm(record).symbol
-            )
-            .unwrap();
-        }
-        writeln!(output, "define {ty} @probe_{}({parameters}) {{", record.id).unwrap();
-        match scalar_arithmetic_llvm_mechanism(record) {
-            BackendLoweringMechanism::TypedNvvm => {
-                writeln!(
-                    output,
-                    "  %result = call {ty} @{}({arguments})",
-                    llvm(record).symbol
-                )
-                .unwrap();
-            }
-            BackendLoweringMechanism::InlinePtx => {
-                let register = if ty == "double" { "d" } else { "f" };
-                let constraints = std::iter::once(format!("={register}"))
-                    .chain(std::iter::repeat_n(register.to_owned(), arity))
-                    .collect::<Vec<_>>()
-                    .join(",");
-                let operands = (0..=arity)
-                    .map(|index| format!("${index}"))
-                    .collect::<Vec<_>>()
-                    .join(", ");
-                writeln!(
-                    output,
-                    "  %result = call {ty} asm {:?}, {:?}({arguments})",
-                    format!("{} {operands};", scalar_arithmetic_ptx_mnemonic(record)),
-                    constraints,
-                )
-                .unwrap();
-            }
-        }
-        writeln!(output, "  ret {ty} %result\n}}").unwrap();
-    } else if record.scalar_math.is_some() {
-        let ty = scalar_math_llvm_type(record);
-        let parameters = format!("{ty} %arg0");
-        let arguments = format!("{ty} %arg0");
-        if scalar_math_llvm_mechanism(record) == BackendLoweringMechanism::TypedNvvm {
-            writeln!(output, "declare {ty} @{}({ty})\n", llvm(record).symbol).unwrap();
-        }
-        writeln!(output, "define {ty} @probe_{}({parameters}) {{", record.id).unwrap();
-        match scalar_math_llvm_mechanism(record) {
-            BackendLoweringMechanism::TypedNvvm => {
-                writeln!(
-                    output,
-                    "  %result = call {ty} @{}({arguments})",
-                    llvm(record).symbol
-                )
-                .unwrap();
-            }
-            BackendLoweringMechanism::InlinePtx => {
-                let register = match ty {
-                    "double" => "d",
-                    "i16" => "h",
-                    _ => "f",
-                };
-                writeln!(
-                    output,
-                    "  %result = call {ty} asm {:?}, {:?}({arguments})",
-                    format!("{} $0, $1;", scalar_math_ptx_mnemonic(record)),
-                    format!("={register},{register}"),
-                )
-                .unwrap();
-            }
-        }
-        writeln!(output, "  ret {ty} %result\n}}").unwrap();
-    } else if record.extended_minmax.is_some() {
-        let (ty, register) = match extended_minmax_contract(record).format {
-            ExtendedMinMaxFormat::F32 => ("float", "f"),
-            ExtendedMinMaxFormat::F16 | ExtendedMinMaxFormat::Bf16 => ("i16", "h"),
-            ExtendedMinMaxFormat::F16x2 | ExtendedMinMaxFormat::Bf16x2 => ("i32", "r"),
-        };
-        writeln!(
-            output,
-            "define {ty} @probe_{}({ty} %a, {ty} %b) {{",
-            record.id
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "  %result = call {ty} asm {:?}, {:?}({ty} %a, {ty} %b)",
-            format!("{} $0, $1, $2;", extended_minmax_ptx_mnemonic(record)),
-            format!("={register},{register},{register}"),
-        )
-        .unwrap();
-        writeln!(output, "  ret {ty} %result\n}}").unwrap();
-    } else if record.scalar_conversion.is_some() {
-        writeln!(output, "declare i32 @{}(float)", llvm(record).symbol).unwrap();
-        output.push('\n');
-        writeln!(output, "define i32 @probe_{}(float %value) {{", record.id).unwrap();
-        writeln!(
-            output,
-            "  %result = call i32 @{}(float %value)",
-            llvm(record).symbol
-        )
-        .unwrap();
-        output.push_str("  ret i32 %result\n}\n");
-    } else if let Some(width) = record.scalar_width() {
-        writeln!(output, "declare i{width} @{}()", llvm(record).symbol).unwrap();
-        output.push('\n');
-        writeln!(output, "define i{width} @probe_{}() {{", record.id).unwrap();
-        writeln!(
-            output,
-            "  %result = call i{width} @{}()",
-            llvm(record).symbol
-        )
-        .unwrap();
-        writeln!(output, "  ret i{width} %result\n}}\n").unwrap();
-    } else {
-        unreachable!("generated intrinsic has no probe renderer: {}", record.id);
-    }
-    output
-}
-
-/// Escape a value for a GFM table cell.
-///
-/// A `|` splits the row before inline parsing runs, so it splits the cell even
-/// inside a code span. GFM's own rule is that a literal pipe must be written
-/// `\|` wherever it appears. Three catalog entries carry a literal pipe today:
-/// the `elect.sync` and `match.all.sync` PTX patterns write their two
-/// destinations as `<register|predicate>`. Their rows rendered with a seventh
-/// cell, which dropped the backend-evidence column.
-fn escape_table_cell(value: impl std::fmt::Display) -> String {
-    value.to_string().replace('|', "\\|")
-}
-
-fn render_reference(catalog: &CatalogFile, hash: &str) -> String {
-    let mut output = markdown_header(catalog, hash);
-    output.push_str(
-        "# Generated Intrinsic Reference\n\nThis table is generated from the resolved catalog. Evidence stages below distinguish backend code generation, terminal validation, and GPU runtime execution; no runtime claim is made unless an executed stage is recorded.\n\n| Rust function | CUDA operation | Source | Effects | Availability | Backend evidence |\n|:--|:--|:--|:--|:--|:--|\n",
-    );
-    for record in &catalog.intrinsics {
-        let safety = if record.rust.safe { "safe" } else { "unsafe" };
-        let availability = if is_blackwell_ldmatrix(record) {
-            format!(
-                "Instruction floor PTX {} on {}; effective LLVM target floors: {BLACKWELL_LDMATRIX_EFFECTIVE_FLOORS}",
-                record.target.minimum_ptx,
-                hardware_target_label(&record.target.hardware)
-            )
-        } else {
-            format!(
-                "PTX {} on {}",
-                record.target.minimum_ptx,
-                hardware_target_label(&record.target.hardware)
-            )
-        };
-        writeln!(
-            output,
-            "| `{}` | `{}` | {} | {safety}; scope {}; {}; memory {}; convergent {} | {availability} ([PTX ISA {}, {}]({})) | {} on `{}`; expects `{}` (`{}`, SHA-256 `{}`) |",
-            escape_table_cell(&record.rust.public_path),
-            escape_table_cell(&record.dialect.op_name),
-            escape_table_cell(source_label(record)),
-            escape_table_cell(&record.semantics.execution_scope),
-            if record.semantics.pure { "pure" } else { "impure" },
-            escape_table_cell(&record.semantics.memory),
-            record.semantics.convergent,
-            escape_table_cell(&record.target.ptx_isa_version),
-            escape_table_cell(&record.target.ptx_isa_section),
-            escape_table_cell(&record.target.ptx_isa_url),
-            escape_table_cell(&record.backend.status),
-            escape_table_cell(&record.backend.profile),
-            escape_table_cell(&record.expected_ptx),
-            escape_table_cell(&record.backend.version),
-            escape_table_cell(&record.backend.sha256),
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Compiler identity and compatibility paths\n\n");
-    for record in &catalog.intrinsics {
-        writeln!(output, "- `{}` (`{}`)", record.id, record.rust.abi_id).unwrap();
-        writeln!(
-            output,
-            "  - canonical compiler path: `{}`",
-            record.rust.canonical_path
-        )
-        .unwrap();
-        writeln!(
-            output,
-            "  - public source path: `{}`",
-            record.rust.public_path
-        )
-        .unwrap();
-        for path in &record.rust.compatibility_paths {
-            writeln!(output, "  - compatibility compiler path: `{path}`").unwrap();
-        }
-    }
-    output.push_str("\n## Register-MMA contracts\n\n");
-    for record in register_mmas(catalog) {
-        let mma = record.register_mma.as_ref().unwrap();
-        let operation = match mma.operation {
-            RegisterMmaOperation::Multiply => "multiply-accumulate",
-            RegisterMmaOperation::AndPopc => "AND, population count, and accumulate",
-            RegisterMmaOperation::XorPopc => "XOR, population count, and accumulate",
-        };
-        let overflow = match mma.overflow {
-            RegisterMmaOverflow::NotApplicable => "not applicable",
-            RegisterMmaOverflow::Wrapping => "wrapping",
-            RegisterMmaOverflow::Satfinite => "finite saturation",
-        };
-        let runtime = match mma.runtime_validation {
-            RuntimeValidation::Unexecuted => "not executed on a GPU",
-            RuntimeValidation::Executed => "executed on a GPU",
-        };
-        if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 {
-            writeln!(
-                output,
-                "- `{}` takes C, A, B, scale-A data/selectors, and scale-B data/selectors in PTX operand order, performs {operation}, and lowers to one convergent, register-only `{}` instruction. For `scale_vec::1X`, byte selectors must be in `0..=3`, the A thread selector in `0..=1`, and the B thread selector in `0..=3`. Every non-exited warp lane must execute the same instruction and qualifiers. Integer overflow is {overflow}; runtime validation is {runtime}.",
-                record.id,
-                expected_ptx_head(record),
-            )
-            .unwrap();
-        } else {
-            writeln!(
-                output,
-                "- `{}` takes fragments in C, A, B order, performs {operation}, and lowers to one convergent, register-only `{}` instruction. Every non-exited warp lane must execute the same instruction and qualifiers. Integer overflow is {overflow}; runtime validation is {runtime}.",
-                record.id,
-                expected_ptx_head(record),
-            )
-            .unwrap();
-        }
-    }
-    output.push_str("\n## Sparse-MMA contracts\n\n");
-    for record in sparse_mmas(catalog) {
-        let mma = record.sparse_mma.as_ref().unwrap();
-        let overflow = match mma.overflow {
-            SparseMmaOverflow::NotApplicable => "Overflow mode is not applicable.",
-            SparseMmaOverflow::Wrapping => "Integer overflow wraps.",
-            SparseMmaOverflow::Satfinite => "Integer overflow uses finite saturation.",
-        };
-        let runtime = match mma.runtime_validation {
-            RuntimeValidation::Unexecuted => "not executed on a GPU",
-            RuntimeValidation::Executed => "executed on a GPU",
-        };
-        let metadata = sparse_mma_metadata_rule(mma);
-        writeln!(
-            output,
-            "- `{}` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `{}` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be {}. Every non-exited warp lane must execute the same instruction and qualifiers. {metadata} {overflow} Runtime validation is {runtime}.",
-            record.id,
-            sparse_mma_ptx_head(record),
-            sparse_mma_selector_description(record),
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Packed-atomic contracts\n\n");
-    for record in packed_atomics(catalog) {
-        let packed = record.packed_atomic.as_ref().unwrap();
-        let format = match packed.format {
-            PackedAtomicFormat::F16x2 => "f16x2",
-            PackedAtomicFormat::Bf16x2 => "bf16x2",
-        };
-        writeln!(
-            output,
-            "- `{}` (`{format}`): the native PTX instruction starts at `sm_{}`; cuda-oxide admits it from {}. Omitted `.sem` / `.scope` mean relaxed GPU scope. Each 16-bit element rounds to nearest-even and `.noftz` preserves subnormal inputs and results. The elements are atomic independently, so the returned `u32` contains old per-element values that may not form one coherent pair. The pointer must address four writable, four-byte-aligned global bytes; do not mix whole-word or non-atomic overlapping access, and every racing atomic must use a mutually inclusive scope.",
-            record.id,
-            packed.native_minimum_sm,
-            hardware_target_label(&record.target.hardware),
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Redux contracts\n\n");
-    for record in redux(catalog) {
-        writeln!(
-            output,
-            "- `{}`: raw and dialect operands are `[member_mask, value]`, adapted to LLVM `(value, membermask)`. The executing lane must be named in the mask, and every non-exited named lane must execute the same instruction with the same qualifiers and mask.",
-            record.id,
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Packed-ALU contracts\n\n");
-    for record in packed_alus(catalog) {
-        let packed = record.packed_alu.as_ref().unwrap();
-        let (format, _, carrier, _, _) = packed_alu_format_shape(packed.format);
-        let backend_floors = record
-            .backend_lowerings
-            .iter()
-            .map(|lowering| {
-                let backend = match lowering.backend {
-                    IntrinsicBackend::LlvmNvptx => "LLVM-NVPTX",
-                    IntrinsicBackend::LibNvvm => "libNVVM",
-                };
-                format!(
-                    "{backend} PTX {} on {}",
-                    lowering.target.minimum_ptx,
-                    hardware_target_label(&lowering.target.hardware),
-                )
-            })
-            .collect::<Vec<_>>()
-            .join("; ");
-        writeln!(
-            output,
-            "- `{}` carries one packed `{format}` value in a `{carrier}` and lowers to one pure `{}` instruction. The native instruction starts at PTX {} / `sm_{}`; cuda-oxide admits it from {}. Backend profile floors: {backend_floors}.",
-            record.id,
-            packed_alu_ptx_mnemonic(record),
-            record.target.minimum_ptx,
-            packed.native_minimum_sm,
-            hardware_target_label(&record.target.hardware),
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Packed-conversion contract\n\n");
-    for record in packed_conversions(catalog) {
-        let conversion = record.packed_conversion.as_ref().unwrap();
-        let rounding = match conversion.rounding {
-            PackedConversionRounding::NearestEven => "nearest-even",
-            PackedConversionRounding::TowardZero => "toward-zero",
-        };
-        let saturation = match conversion.saturation {
-            PackedConversionSaturation::None => "without saturation",
-            PackedConversionSaturation::Relu => "with ReLU",
-            PackedConversionSaturation::Satfinite => "with finite saturation",
-            PackedConversionSaturation::SatfiniteRelu => "with finite saturation and ReLU",
-        };
-        if packed_conversion_typed_llvm_name(record).is_some() {
-            writeln!(
-                output,
-                "- `{}` converts two `f32` inputs to packed `{}` using {rounding} rounding {saturation}. LLVM-NVPTX uses typed `{}` with `[high, low]` inputs; libNVVM uses pure `{}` inline PTX. The public first input becomes the low lane and the second becomes the high lane.",
-                record.id,
-                packed_conversion_destination(record),
-                llvm(record).symbol,
-                packed_conversion_ptx_mnemonic(record),
-            )
-            .unwrap();
-        } else {
-            writeln!(
-                output,
-                "- `{}` converts two `f32` inputs to packed `{}` using {rounding} rounding {saturation}. It lowers to pure `{}` inline PTX. The first input becomes the low lane and the second becomes the high lane, so PTX prints the inputs in reverse order.",
-                record.id,
-                packed_conversion_destination(record),
-                packed_conversion_ptx_mnemonic(record),
-            )
-            .unwrap();
-        }
-    }
-    output.push_str("\n## Scalar TF32-conversion contract\n\n");
-    for record in scalar_conversions(catalog) {
-        writeln!(
-            output,
-            "- `{}` converts one `f32` value to raw TF32 bits with `{}`. LLVM-NVPTX uses the typed intrinsic; libNVVM uses pure inline PTX so the native target floor is preserved.",
-            record.id,
-            scalar_conversion_ptx_mnemonic(record),
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Explicit-rounding scalar-arithmetic contracts\n\n");
-    for record in scalar_arithmetics(catalog) {
-        let llvm_route = match scalar_arithmetic_llvm_mechanism(record) {
-            BackendLoweringMechanism::TypedNvvm => "the typed intrinsic",
-            BackendLoweringMechanism::InlinePtx => "pure inline PTX",
-        };
-        writeln!(
-            output,
-            "- `{}` performs `{}`. LLVM-NVPTX uses {llvm_route}; libNVVM uses pure inline PTX.",
-            record.id,
-            scalar_arithmetic_ptx_mnemonic(record),
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Warp vote contracts\n\n");
-    for record in vote_intrinsics(catalog) {
-        writeln!(
-            output,
-            "- `{}` keeps raw and dialect operands in `[member_mask, predicate]` order. The executing lane must be named in the mask, and every non-exited named lane must execute the same `vote.sync` instruction with the same qualifiers and mask. On `sm_6x` and earlier, all named lanes must execute in convergence and no unnamed lane may be active. Both immediate and register member masks are admitted.",
-            record.id,
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Active-mask contract\n\n");
-    for record in active_masks(catalog) {
-        writeln!(
-            output,
-            "- `{}` observes the lanes active at the instruction. LLVM uses the typed intrinsic; libNVVM uses reviewed convergent, side-effecting inline PTX because that backend does not select the intrinsic.",
-            record.id,
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Warp-match contracts\n\n");
-    for record in warp_matches(catalog) {
-        let adapter = match record.warp_match.as_ref().unwrap().adapter {
-            WarpMatchAdapter::DirectMask => "returns LLVM's mask directly",
-            WarpMatchAdapter::ProjectMaskDiscardPredicate => {
-                "projects field 0 from LLVM's `{i32, i1}` result"
-            }
-        };
-        writeln!(
-            output,
-            "- `{}` keeps operands in `[member_mask, value]` order and {adapter}. The executing lane must be named in the mask, and every non-exited named lane must execute the same `match.sync` operation with the same qualifiers and mask. All register/immediate value and mask forms are admitted.",
-            record.id,
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Warp-barrier contract\n\n");
-    for record in warp_barriers(catalog) {
-        writeln!(
-            output,
-            "- `{}` passes the 32-bit member mask directly to the typed LLVM intrinsic on both backends. The executing lane must be named in the mask, and every non-exited named lane must execute the same `bar.warp.sync` operation with the same mask. On `sm_6x` and earlier, all named lanes must execute the barrier in convergence, and no unnamed lane may be active when it executes. The barrier orders memory accesses among participating lanes. Both immediate and register masks are admitted.",
-            record.id,
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Warp-shuffle contracts\n\n");
-    for record in warp_shuffles(catalog) {
-        let shuffle = record.warp_shuffle.as_ref().unwrap();
-        let lowering = match shuffle.value_kind {
-            WarpShuffleValueKind::I32 | WarpShuffleValueKind::F32 => {
-                "Register and immediate lane/mask forms are admitted."
-            }
-            WarpShuffleValueKind::I64 => {
-                "One convergent, side-effecting inline-PTX block splits `i64`, performs low then high `b32` shuffles with the same register lane/mask, and reassembles it."
-            }
-        };
-        writeln!(
-            output,
-            "- `{}` keeps raw and dialect operands in `[member_mask, value, lane_or_delta]` order and inserts clamp `{}` during lowering. The executing lane must be named in the mask, and every non-exited named lane must execute the same `shfl.sync` operation with the same qualifiers and mask. On `sm_6x` and earlier, all named lanes must execute in convergence and no unnamed lane may be active. A computed in-range source must be active and named; if PTX marks it out of range, the calling lane's input is copied. {lowering}",
-            record.id,
-            shuffle.clamp,
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Cluster-barrier contracts\n\n");
-    for record in cluster_barriers(catalog) {
-        let barrier = record.cluster_barrier.as_ref().unwrap();
-        let ordering = match barrier.ordering {
-            ClusterBarrierOrdering::Release => "release",
-            ClusterBarrierOrdering::Relaxed => "relaxed",
-            ClusterBarrierOrdering::Acquire => "acquire",
-        };
-        let alignment = if barrier.aligned {
-            "Every non-exited warp thread must execute the same aligned instruction in identical control flow."
-        } else {
-            "The instruction is not aligned."
-        };
-        writeln!(
-            output,
-            "- `{}` has {ordering} ordering. Each non-exited cluster thread must arrive exactly once before completion, then execute the matching wait. {alignment}",
-            record.id,
-        )
-        .unwrap();
-    }
-    if cluster_barriers(catalog).next().is_some() {
-        output.push_str(
-            "- `cuda_device::cluster::cluster_sync` is the generated compatibility operation: aligned arrive followed by aligned wait.\n",
-        );
-    }
-    if cluster_memory(catalog).next().is_some() {
-        output.push_str("\n## Cluster-memory contracts\n\n");
-        for record in cluster_memory(catalog) {
-            match record.cluster_memory.as_ref().unwrap().source_contract {
-                ClusterMemorySourceContract::LlvmMapaSharedClusterAs7IdentityInlinePtx => {
-                    writeln!(
-                        output,
-                        "- `{}` preserves LLVM 22's address-space-7 result. Both backends use exact convergent `mapa.shared::cluster.u64` inline PTX, and ordinary Rust dereference of the mapped pointer lowers through cluster shared memory.",
-                        record.id
-                    )
-                    .unwrap();
-                }
-                ClusterMemorySourceContract::PtxNativeMapaThenWeakClusterLoad => {
-                    writeln!(
-                        output,
-                        "- `{}` has no one-to-one LLVM intrinsic. Both backends use one convergent `mapa.shared::cluster.u64` plus `ld.shared::cluster.u32` block with a compiler memory clobber.",
-                        record.id
-                    )
-                    .unwrap();
-                }
-            }
-        }
-    }
-    if movmatrix(catalog).next().is_some() {
-        output.push_str("\n## movmatrix contracts\n\n");
-        for record in movmatrix(catalog) {
-            writeln!(
-                output,
-                "- `{}` transposes one packed b16 fragment in registers. All warp lanes must execute the same instruction, and no lane may have exited.",
-                record.id,
-            )
-            .unwrap();
-        }
-    }
-    if mbarrier_extended(catalog).next().is_some() {
-        output.push_str("\n## Extended mbarrier contracts\n\n");
-        for record in mbarrier_extended(catalog) {
-            let contract = record.mbarrier_extended.as_ref().unwrap();
-            let source = match contract.source_contract {
-                MbarrierExtendedSourceContract::LlvmImported => "LLVM 22 TableGen",
-                MbarrierExtendedSourceContract::PtxNativeRawClusterAddress => {
-                    "PTX-native raw-address contract"
-                }
-            };
-            writeln!(
-                output,
-                "- `{}` keeps its established CUDA-device signature and exact convergent inline-PTX memory clobber. Its source identity is {source}.",
-                record.id,
-            )
-            .unwrap();
-        }
-    }
-    if wgmma_controls(catalog).next().is_some() {
-        output.push_str("\n## WGMMA-control contracts\n\n");
-        for record in wgmma_controls(catalog) {
-            let detail = match record.wgmma_control.as_ref().unwrap().mode {
-                WgmmaControlMode::Fence => {
-                    "It orders register writes before later WGMMA operations."
-                }
-                WgmmaControlMode::CommitGroup => {
-                    "It commits the warpgroup's prior uncommitted WGMMA operations."
-                }
-                WgmmaControlMode::WaitGroup => {
-                    "Its `u64` argument must be a compile-time constant."
-                }
-            };
-            writeln!(
-                output,
-                "- `{}` must be executed by all four warps in the warpgroup with the same control flow. {detail}",
-                record.id,
-            )
-            .unwrap();
-        }
-    }
-    if sync_intrinsics(catalog).any(|record| threadfence_ptx_level(record).is_some()) {
-        output.push_str("\n## Synchronization contracts\n\n");
-    } else {
-        output.push_str("\n## CTA synchronization contracts\n\n");
-    }
-    for record in sync_intrinsics(catalog) {
-        if record.id == "sync_threads" {
-            writeln!(
-                output,
-                "- `{}` inserts the fixed barrier ID `0`. Every active CTA thread must reach the same barrier; divergent use can deadlock the CTA.",
-                record.id,
-            )
-            .unwrap();
-        } else {
-            let level = threadfence_ptx_level(record)
-                .expect("resolver admitted an unknown generated synchronization record");
-            writeln!(
-                output,
-                "- `{}` emits `membar.{level}` through the reviewed typed NVVM route on both backends.",
-                record.id,
-            )
-            .unwrap();
-        }
-    }
-    output.push_str("\n## cp.async mbarrier contracts\n\n");
-    for record in cp_async_mbarriers(catalog) {
-        let bridge = record.cp_async_mbarrier.as_ref().unwrap();
-        let address = match bridge.state_space {
-            CpAsyncMbarrierStateSpace::Generic => "generic",
-            CpAsyncMbarrierStateSpace::Shared => "explicit shared",
-        };
-        let counting = match bridge.operation {
-            CpAsyncMbarrierOperation::Arrive => {
-                "increments the pending count before the later asynchronous decrement"
-            }
-            CpAsyncMbarrierOperation::ArriveNoInc => {
-                "does not increment the pending count, so initialization must already include the later asynchronous decrement"
-            }
-        };
-        writeln!(
-            output,
-            "- `{}` uses {address} addressing and {counting}. It associates only the executing thread's prior `cp.async` operations with a live, eight-byte-aligned shared-memory barrier. LLVM-NVPTX uses the typed intrinsic; libNVVM uses reviewed convergent, side-effecting inline PTX with a memory clobber.",
-            record.id,
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Basic mbarrier contracts\n\n");
-    for record in mbarrier_basics(catalog) {
-        let mbarrier = record.mbarrier_basic.as_ref().unwrap();
-        let contract = match mbarrier.operation {
-            MbarrierBasicOperation::Init => {
-                "initializes one eight-byte-aligned shared-memory object exactly once with an expected count in `1..=0xFFFFF`"
-            }
-            MbarrierBasicOperation::Arrive => {
-                "records one expected arrival and returns a token for the same barrier phase"
-            }
-            MbarrierBasicOperation::TestWait => {
-                "tests one token from the same barrier phase with convergent, side-effecting inline PTX"
-            }
-            MbarrierBasicOperation::Inval => {
-                "invalidates an initialized barrier only after all users are finished"
-            }
-        };
-        let mechanism = if mbarrier.operation == MbarrierBasicOperation::TestWait {
-            "inline PTX on both backends"
-        } else {
-            "the typed NVVM intrinsic with LLVM-NVPTX and inline PTX with libNVVM"
-        };
-        writeln!(
-            output,
-            "- `{}` {contract}. It lowers through {mechanism}; generic MIR pointers are normalized to shared address space during lowering.",
-            record.id,
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Imported LLVM properties and result facts\n\n");
-    for record in &catalog.intrinsics {
-        let Some(llvm) = &record.llvm else {
-            writeln!(
-                output,
-                "- `{}`: PTX-native source; no LLVM record, symbol, properties, or selection facts.",
-                record.id
-            )
-            .unwrap();
-            continue;
-        };
-        let properties = record
-            .llvm
-            .as_ref()
-            .unwrap()
-            .properties
-            .iter()
-            .map(|property| format!("`{property}`"))
-            .collect::<Vec<_>>()
-            .join(", ");
-        let range = record
-            .llvm
-            .as_ref()
-            .unwrap()
-            .result_facts
-            .range
-            .as_ref()
-            .map(|range| format!("[{}, {})", range.lower, range.upper_exclusive))
-            .unwrap_or_else(|| "none".to_owned());
-        let selection_records = record
-            .selections
-            .iter()
-            .map(|selection| format!("`{}`", selection.source_record))
-            .collect::<BTreeSet<_>>()
-            .into_iter()
-            .collect::<Vec<_>>()
-            .join(", ");
-        let selection_predicates = record
-            .selections
-            .iter()
-            .flat_map(|selection| selection.predicates.iter())
-            .map(|predicate| format!("`{predicate}`"))
-            .collect::<BTreeSet<_>>()
-            .into_iter()
-            .collect::<Vec<_>>()
-            .join(", ");
-        writeln!(
-            output,
-            "- `{}`: properties {}; result `NoUndef` {}; half-open result range `{}`; selection records {}; selection predicates {}",
-            record.id,
-            properties,
-            llvm.result_facts.no_undef,
-            range,
-            selection_records,
-            if selection_predicates.is_empty() {
-                "none"
-            } else {
-                &selection_predicates
-            }
-        )
-        .unwrap();
-    }
-    output.push_str("\n## Backend-specific lowering evidence\n\n");
-    for record in &catalog.intrinsics {
-        if record.backend_lowerings.is_empty() {
-            continue;
-        }
-        let runtime = record
-            .ldmatrix
-            .as_ref()
-            .map(|record| format!("{:?}", record.safety.runtime_validation).to_lowercase())
-            .or_else(|| {
-                record
-                    .packed_atomic
-                    .as_ref()
-                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
-            })
-            .or_else(|| {
-                record
-                    .mbarrier_basic
-                    .as_ref()
-                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
-            })
-            .or_else(|| {
-                record
-                    .movmatrix
-                    .as_ref()
-                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
-            })
-            .or_else(|| {
-                record
-                    .mbarrier_extended
-                    .as_ref()
-                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
-            })
-            .or_else(|| {
-                record
-                    .cp_async_mbarrier
-                    .as_ref()
-                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
-            })
-            .or_else(|| {
-                record
-                    .register_mma
-                    .as_ref()
-                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
-            })
-            .or_else(|| {
-                record
-                    .sparse_mma
-                    .as_ref()
-                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
-            })
-            .or_else(|| {
-                record
-                    .debug_control
-                    .as_ref()
-                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
-            })
-            .or_else(|| {
-                record
-                    .cluster_memory
-                    .as_ref()
-                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
-            })
-            .or_else(|| {
-                record
-                    .tcgen05
-                    .as_ref()
-                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
-            })
-            .or_else(|| (record.family == "stmatrix").then(|| "unexecuted".to_owned()))
-            .unwrap_or_else(|| "not recorded".to_owned());
-        writeln!(output, "- `{}`: runtime `{runtime}`", record.id).unwrap();
-        for lowering in &record.backend_lowerings {
-            writeln!(
-                output,
-                "  - `{}` uses `{}` from profile `{}` at PTX {} / {}: status `{}` (`{}`, SHA-256 `{}`)",
-                backend_label(lowering.backend),
-                lowering_mechanism_label(lowering.mechanism),
-                lowering.evidence_profile,
-                lowering.target.minimum_ptx,
-                hardware_target_label(&lowering.target.hardware),
-                lowering.status,
-                lowering.version,
-                lowering.sha256,
-            )
-            .unwrap();
-            for stage in &lowering.stages {
-                let tool = match (
-                    stage.tool_path.as_deref(),
-                    stage.tool_version.as_deref(),
-                    stage.tool_sha256.as_deref(),
-                ) {
-                    (Some(path), Some(version), Some(sha256)) => {
-                        format!(" Tool `{path}` reports `{version}` (SHA-256 `{sha256}`).")
-                    }
-                    _ => String::new(),
-                };
-                let artifact = match stage.artifact_kind {
-                    Some(EvidenceArtifactKind::Cubin) => " Artifact `cubin`.",
-                    None => "",
-                };
-                writeln!(
-                    output,
-                    "    - {} on `{}`: `{}` — {}{}{}",
-                    evidence_stage_label(stage.stage),
-                    stage.targets.join(", "),
-                    stage.outcome,
-                    stage.detail,
-                    tool,
-                    artifact,
-                )
-                .unwrap();
-            }
-        }
-    }
-    output
-}
-
-fn render_compiler_path_patterns(output: &mut String, catalog: &CatalogFile, indent: &str) {
-    let paths: Vec<_> = catalog
-        .intrinsics
-        .iter()
-        .flat_map(|record| {
-            std::iter::once(record.rust.canonical_path.as_str())
-                .chain(record.rust.compatibility_paths.iter().map(String::as_str))
-        })
-        .collect();
-    render_string_patterns(output, &paths, indent);
-}
-
-fn render_string_patterns(output: &mut String, values: &[&str], indent: &str) {
-    for (index, value) in values.iter().enumerate() {
-        if index == 0 {
-            writeln!(output, "{indent}{value:?}").unwrap();
-        } else {
-            writeln!(output, "{indent}| {value:?}").unwrap();
-        }
-    }
-}
-
-fn render_inline_patterns(output: &mut String, values: &[&str]) {
-    for (index, value) in values.iter().enumerate() {
-        if index != 0 {
-            output.push_str(" | ");
-        }
-        write!(output, "{value:?}").unwrap();
-    }
-}
-
-#[allow(dead_code)]
-fn modules(catalog: &CatalogFile) -> BTreeSet<&str> {
-    catalog
-        .intrinsics
-        .iter()
-        .map(|record| record.rust.module.as_str())
-        .collect()
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use crate::model::{
-        CatalogTargetAlternative, ImportedSelectionConstraints, TargetSelectorBinding,
-    };
-    use crate::ptx::{InstructionPattern, OperandPattern};
-    use crate::util::read_json;
-    use std::path::Path;
-
-    #[test]
-    fn paired_target_matrix_renders_selectors_and_ptx_floors() {
-        let target = CatalogHardwareTarget::TargetMatrix {
-            contracts: vec![CatalogTargetContract {
-                selectors: vec![TargetSelectorBinding {
-                    name: "kind".into(),
-                    value: "i8".into(),
-                }],
-                alternatives: vec![
-                    CatalogTargetAlternative {
-                        minimum_ptx: "8.8".parse().unwrap(),
-                        hardware: CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                    },
-                    CatalogTargetAlternative {
-                        minimum_ptx: "9.0".parse().unwrap(),
-                        hardware: CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                    },
-                ],
-            }],
-        };
-
-        assert_eq!(
-            hardware_target_label(&target),
-            "sm_100a at PTX 8.8 or sm_110a at PTX 9.0 for kind=i8"
-        );
-        assert_eq!(
-            generated_hardware_target(&target),
-            "GeneratedHardwareTarget::TargetMatrix { contracts: &[GeneratedTargetContract { selectors: &[GeneratedTargetSelectorBinding { name: \"kind\", value: \"i8\" }], alternatives: &[GeneratedTargetAlternative { minimum_ptx: GeneratedPtxVersion::from_encoded(88), hardware: GeneratedHardwareAlternative::ExactArchitecture(100) }, GeneratedTargetAlternative { minimum_ptx: GeneratedPtxVersion::from_encoded(90), hardware: GeneratedHardwareAlternative::ExactArchitecture(110) }] }] }"
-        );
-    }
-
-    #[test]
-    fn tcgen05_mma_inline_asm_closes_selectors_and_operand_order() {
-        for (kind, spelling) in [
-            (Tcgen05MmaKind::F16, "kind::f16"),
-            (Tcgen05MmaKind::Tf32, "kind::tf32"),
-            (Tcgen05MmaKind::F8f6f4, "kind::f8f6f4"),
-            (Tcgen05MmaKind::I8, "kind::i8"),
-        ] {
-            let (template, _) = tcgen05_mma_inline_asm(
-                Tcgen05MmaForm::WsTensor,
-                kind,
-                1,
-                None,
-                Some(0),
-                Some(Tcgen05MmaBUsage::Discard),
-            );
-            assert!(template.contains(spelling));
-        }
-        for (usage, spelling) in [
-            (Tcgen05MmaBUsage::Discard, "collector::b0::discard"),
-            (Tcgen05MmaBUsage::LastUse, "collector::b0::lastuse"),
-            (Tcgen05MmaBUsage::Fill, "collector::b0::fill"),
-            (Tcgen05MmaBUsage::Use, "collector::b0::use"),
-        ] {
-            let (template, _) = tcgen05_mma_inline_asm(
-                Tcgen05MmaForm::WsTensor,
-                Tcgen05MmaKind::F16,
-                1,
-                None,
-                Some(0),
-                Some(usage),
-            );
-            assert!(template.contains(spelling));
-        }
-
-        for (form, operands, constraints) in [
-            (
-                Tcgen05MmaForm::WsTensor,
-                "[$0], [$1], $2, $3, %enable_pred;",
-                "r,r,l,r,r,~{memory}",
-            ),
-            (
-                Tcgen05MmaForm::WsSpTensor,
-                "[$0], [$1], $2, [$5], $3, %enable_pred;",
-                "r,r,l,r,r,r,~{memory}",
-            ),
-            (
-                Tcgen05MmaForm::WsTensorZeroColMask,
-                "[$0], [$1], $2, $3, %enable_pred, $5;",
-                "r,r,l,r,r,l,~{memory}",
-            ),
-            (
-                Tcgen05MmaForm::WsSpTensorZeroColMask,
-                "[$0], [$1], $2, [$5], $3, %enable_pred, $6;",
-                "r,r,l,r,r,r,l,~{memory}",
-            ),
-        ] {
-            let (template, actual_constraints) = tcgen05_mma_inline_asm(
-                form,
-                Tcgen05MmaKind::F16,
-                1,
-                None,
-                Some(3),
-                Some(Tcgen05MmaBUsage::LastUse),
-            );
-            assert!(template.contains(operands));
-            assert_eq!(actual_constraints, constraints);
-        }
-    }
-
-    fn catalog_with_debug_controls() -> CatalogFile {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        assert_eq!(debug_controls(&catalog).count(), 3);
-        catalog
-    }
-
-    fn catalog_with_stmatrix() -> CatalogFile {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        assert_eq!(stmatrices(&catalog).count(), 4);
-        catalog
-    }
-
-    fn catalog_with_clc() -> CatalogFile {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::test_catalog_with_clc(&repo_root).unwrap();
-        assert_eq!(clc_intrinsics(&catalog).count(), 6);
-        catalog
-    }
-
-    fn catalog_with_tma() -> CatalogFile {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::test_catalog_with_tma(&repo_root).unwrap();
-        assert_eq!(tma_intrinsics(&catalog).count(), 111);
-        catalog
-    }
-
-    fn catalog_with_wgmma_controls() -> CatalogFile {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let mut catalog = crate::resolve::resolve(&repo_root).unwrap();
-        if wgmma_controls(&catalog).count() == 3 {
-            return catalog;
-        }
-        let template = catalog
-            .intrinsics
-            .iter()
-            .find(|record| record.cluster_barrier.is_some())
-            .expect("cluster-barrier template")
-            .clone();
-
-        let recipes = [
-            (
-                WgmmaControlMode::Fence,
-                "i0317",
-                "wgmma_fence",
-                "WgmmaFenceSyncAlignedOp",
-                "nvvm.wgmma_fence_sync_aligned",
-                "llvm.nvvm.wgmma.fence.sync.aligned",
-                "WGMMA_FENCE_SYNC_ALIGNED",
-                "fence.sync.aligned",
-                WgmmaControlAdapter::NoArguments,
-                "cuda_device::wgmma::wgmma_fence",
-            ),
-            (
-                WgmmaControlMode::CommitGroup,
-                "i0318",
-                "wgmma_commit_group",
-                "WgmmaCommitGroupSyncAlignedOp",
-                "nvvm.wgmma_commit_group_sync_aligned",
-                "llvm.nvvm.wgmma.commit_group.sync.aligned",
-                "WGMMA_COMMIT_GROUP_SYNC_ALIGNED",
-                "commit_group.sync.aligned",
-                WgmmaControlAdapter::NoArguments,
-                "cuda_device::wgmma::wgmma_commit_group",
-            ),
-            (
-                WgmmaControlMode::WaitGroup,
-                "i0319",
-                "wgmma_wait_group",
-                "WgmmaWaitGroupSyncAlignedOp",
-                "nvvm.wgmma_wait_group_sync_aligned",
-                "llvm.nvvm.wgmma.wait_group.sync.aligned",
-                "WGMMA_WAIT_GROUP_SYNC_ALIGNED",
-                "wait_group.sync.aligned",
-                WgmmaControlAdapter::ConstGenericU32ToI64Immediate,
-                "cuda_device::wgmma::__wgmma_wait_group",
-            ),
-        ];
-
-        for (
-            mode,
-            abi_id,
-            id,
-            op_type,
-            op_name,
-            llvm_symbol,
-            selection_record,
-            suffix,
-            adapter,
-            compatibility_path,
-        ) in recipes
-        {
-            let wait = mode == WgmmaControlMode::WaitGroup;
-            let mut record = template.clone();
-            record.id = id.into();
-            record.operation_key = format!("wgmma.control.{suffix}");
-            record.family = "wgmma_control".into();
-            record.source = crate::model::IntrinsicSource::LlvmImported {
-                source_record: format!("int_nvvm_wgmma_{}", suffix.replace('.', "_")),
-            };
-            record.selections = vec![CatalogSelection {
-                source_record: selection_record.into(),
-                asm: format!("wgmma.{suffix};"),
-                predicates: vec!["Subtarget->getPTXVersion() >= 80".into(), "hasSM90a".into()],
-                constraints: ImportedSelectionConstraints::default(),
-            }];
-            record.rust.abi_id = abi_id.into();
-            record.rust.module = "wgmma".into();
-            record.rust.name = id.into();
-            record.rust.arguments = if wait { vec!["u64".into()] } else { vec![] };
-            record.rust.result = "()".into();
-            record.rust.safe = false;
-            record.rust.must_use = false;
-            record.rust.safe_allowlist_reason = None;
-            record.rust.canonical_path =
-                format!("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::{abi_id}");
-            record.rust.public_path = format!("cuda_intrinsics::wgmma::{id}");
-            record.rust.compatibility_paths = vec![compatibility_path.into()];
-            record.dialect.op_type = op_type.into();
-            record.dialect.op_name = op_name.into();
-            record.dialect.operands = if wait { vec!["i64".into()] } else { vec![] };
-            record.dialect.results.clear();
-            let llvm = record.llvm.as_mut().unwrap();
-            llvm.symbol = llvm_symbol.into();
-            llvm.resolved_symbol = None;
-            llvm.arguments = if wait { vec!["i64".into()] } else { vec![] };
-            llvm.results.clear();
-            llvm.properties = if wait {
-                vec!["ImmArg<arg0>".into(), "IntrConvergent".into()]
-            } else {
-                vec!["IntrConvergent".into()]
-            };
-            record.semantics.pure = false;
-            record.semantics.memory = "read_write".into();
-            record.semantics.convergent = true;
-            record.semantics.execution_scope = "warpgroup".into();
-            record.target.minimum_ptx = "8.0".parse().unwrap();
-            record.target.hardware = CatalogHardwareTarget::AnyOf {
-                alternatives: vec![CatalogHardwareAlternative::ExactArchitecture { sm: 90 }],
-            };
-            record.target.ptx_result = "()".into();
-            record.target.targets = "sm_90a".into();
-            record.target.ptx_isa_version = "9.3".into();
-            record.target.ptx_isa_section = "WGMMA control".into();
-            record.target.ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#asynchronous-warpgroup-level-matrix-instructions".into();
-            for lowering in &mut record.backend_lowerings {
-                lowering.target.minimum_ptx = "8.0".parse().unwrap();
-                lowering.target.hardware = record.target.hardware.clone();
-                lowering.mechanism = match lowering.backend {
-                    IntrinsicBackend::LlvmNvptx => BackendLoweringMechanism::TypedNvvm,
-                    IntrinsicBackend::LibNvvm => BackendLoweringMechanism::InlinePtx,
-                };
-            }
-            record.packed_atomic = None;
-            record.redux = None;
-            record.vote = None;
-            record.active_mask = None;
-            record.warp_match = None;
-            record.warp_barrier = None;
-            record.warp_shuffle = None;
-            record.dot_product = None;
-            record.packed_alu = None;
-            record.packed_conversion = None;
-            record.cp_async_copy = None;
-            record.cp_async_control = None;
-            record.cp_async_mbarrier = None;
-            record.mbarrier_basic = None;
-            record.register_mma = None;
-            record.sparse_mma = None;
-            record.prmt = None;
-            record.cluster_barrier = None;
-            record.wgmma_control = Some(crate::model::WgmmaControl {
-                mode,
-                adapter,
-                participation: WgmmaControlParticipation::WarpgroupAllThreadsSameInstruction,
-            });
-            record.special_register = None;
-            record.ldmatrix = None;
-            record.lowering = "generated_wgmma_control".into();
-            record.expected_ptx = InstructionPattern {
-                mnemonic: "wgmma".into(),
-                modifiers: suffix.split('.').map(str::to_owned).collect(),
-                operands: if wait {
-                    vec![OperandPattern::Immediate]
-                } else {
-                    vec![]
-                },
-            };
-            record.summary = format!("Generated {id} test record.");
-            catalog.intrinsics.push(record);
-        }
-        catalog
-    }
-
-    fn raw_abi_item<'a>(raw: &'a str, id: &str) -> &'a str {
-        let marker = format!("Catalog ID: `{id}`");
-        let marker_offset = raw.find(&marker).unwrap();
-        let start = raw[..marker_offset]
-            .rfind("\n\n")
-            .map_or(0, |offset| offset + 2);
-        let end = raw[marker_offset..]
-            .find("\n}\n")
-            .map_or(raw.len(), |offset| marker_offset + offset + 3);
-        &raw[start..end]
-    }
-
-    fn raw_abi_safety_block<'a>(raw: &'a str, id: &str) -> &'a str {
-        let item = raw_abi_item(raw, id);
-        let marker = "/// # Safety\n";
-        let start = item.find(marker).unwrap() + marker.len();
-        let end = item[start..].find("#[").unwrap() + start;
-        &item[start..end]
-    }
-
-    #[test]
-    fn unsafe_safety_docs_never_reference_missing_addr() {
-        let catalog = catalog_with_clc();
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        let offenders = catalog
-            .intrinsics
-            .iter()
-            .filter(|record| !record.rust.safe)
-            .filter(|record| raw_abi_item(&raw, &record.id).contains("/// `addr`"))
-            .filter(|record| {
-                !record
-                    .rust
-                    .arguments
-                    .iter()
-                    .any(|argument| argument.starts_with('*'))
-            })
-            .map(|record| record.id.as_str())
-            .collect::<Vec<_>>();
-        assert!(
-            offenders.is_empty(),
-            "unsafe safety docs reference `addr` without a pointer argument: {}",
-            offenders.join(", ")
-        );
-    }
-
-    #[test]
-    fn unsafe_safety_blocks_are_exclusive_to_one_family() {
-        let catalog = catalog_with_clc();
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        let mut families_by_block = BTreeMap::<&str, BTreeSet<&str>>::new();
-        for record in catalog.intrinsics.iter().filter(|record| !record.rust.safe) {
-            families_by_block
-                .entry(raw_abi_safety_block(&raw, &record.id))
-                .or_default()
-                .insert(&record.family);
-        }
-        let collisions = families_by_block
-            .values()
-            .filter(|families| families.len() != 1)
-            .collect::<Vec<_>>();
-        assert!(
-            collisions.is_empty(),
-            "unsafe safety blocks shared across families: {collisions:?}; render a legitimate shared contract through a shared arm"
-        );
-    }
-
-    #[test]
-    fn wgmma_controls_render_closed_compatibility_and_backend_routes() {
-        let catalog = catalog_with_wgmma_controls();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(wgmma_controls(&catalog).count(), 3);
-
-        let compatibility = render_compat_wgmma_control(&catalog, "test-hash");
-        assert!(compatibility.contains("pub fn wgmma_fence()"));
-        assert!(compatibility.contains("pub fn wgmma_commit_group()"));
-        assert!(compatibility.contains("pub fn wgmma_wait_group<const N: u32>()"));
-        assert!(compatibility.contains("__wgmma_wait_group(N as u64);"));
-        assert!(compatibility.contains("pub(crate) fn __wgmma_wait_group(_max_pending: u64)"));
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("pub unsafe fn i0317()"));
-        assert!(raw.contains("pub unsafe fn i0318()"));
-        assert!(raw.contains("pub unsafe fn i0319(_arg0: u64)"));
-        let raw_mod = render_raw_mod(&catalog, "test-hash");
-        assert!(
-            raw_mod.contains("pub use crate::__cuda_oxide_intrinsic_abi_v1::i0317 as wgmma_fence;")
-        );
-        assert!(
-            raw_mod.contains(
-                "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0319 as wgmma_wait_group;"
-            )
-        );
-
-        let dialect = render_dialect_wgmma_control(&catalog, "test-hash");
-        for op in [
-            "WgmmaFenceSyncAlignedOp",
-            "WgmmaCommitGroupSyncAlignedOp",
-            "WgmmaWaitGroupSyncAlignedOp",
-        ] {
-            assert!(dialect.contains(&format!("pub struct {op};")));
-            assert!(dialect.contains(&format!("{op}::register(ctx);")));
-        }
-        assert!(dialect.contains("operand must be i64"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::wgmma::wgmma_fence"));
-        assert!(importer.contains("cuda_device::wgmma::wgmma_commit_group"));
-        assert!(importer.contains("cuda_device::wgmma::__wgmma_wait_group"));
-        assert!(importer.contains("wgmma_wait_group requires a compile-time constant"));
-        assert!(importer.contains("WgmmaWaitGroupSyncAlignedOp::build(ctx, max_pending)"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("llvm_nvvm_wgmma_fence_sync_aligned"));
-        assert!(lowering.contains("llvm__nvvm_dwgmma_dcommit_ugroup_dsync_daligned"));
-        assert!(lowering.contains("llvm__nvvm_dwgmma_dwait_ugroup_dsync_daligned"));
-        assert!(lowering.contains("IntrinsicBackend::LlvmNvptx"));
-        assert!(lowering.contains("IntrinsicBackend::LibNvvm"));
-        assert!(lowering.contains("wgmma.fence.sync.aligned;"));
-        assert!(lowering.contains("wgmma.commit_group.sync.aligned;"));
-        assert!(lowering.contains("wgmma.wait_group.sync.aligned $0;"));
-        assert!(lowering.contains("\"n,~{memory}\""));
-
-        let targets = render_targets(&catalog, "test-hash");
-        assert!(
-            targets
-                .contains("pub enum GeneratedWgmmaControlMode { Fence, CommitGroup, WaitGroup }")
-        );
-        assert!(targets.contains("GeneratedIntrinsicVariant::WgmmaControl"));
-        assert!(targets.contains("WgmmaFenceSyncAlignedOp>(operation, ctx).is_some()"));
-
-        for record in wgmma_controls(&catalog) {
-            let probe = render_probe(&catalog, record, "test-hash");
-            assert!(probe.contains(&format!("@{}", llvm(record).symbol)));
-            assert!(!probe.contains("asm sideeffect"));
-            assert!(probe.contains("attributes #0 = { convergent }"));
-        }
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/wgmma_control.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/wgmma_control.rs"
-        )));
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("## WGMMA-control contracts"));
-    }
-
-    fn catalog_with_tcgen05() -> CatalogFile {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::test_catalog_with_tcgen05(&repo_root).unwrap();
-        assert_eq!(tcgen05_intrinsics(&catalog).count(), 233);
-        catalog
-    }
-
-    #[test]
-    fn selection_alternatives_keep_predicates_and_constraints_grouped() {
-        let selections = vec![
-            CatalogSelection {
-                source_record: "SELECT_A".into(),
-                asm: "op.a $dst;".into(),
-                predicates: vec!["HasA".into(), "HasCommon".into()],
-                constraints: ImportedSelectionConstraints {
-                    address_space: Some(ImportedAddressSpace::Generic),
-                    immediate_bindings: vec![],
-                },
-            },
-            CatalogSelection {
-                source_record: "SELECT_B".into(),
-                asm: "op.b $dst;".into(),
-                predicates: vec!["HasB".into()],
-                constraints: ImportedSelectionConstraints {
-                    address_space: Some(ImportedAddressSpace::Shared),
-                    immediate_bindings: vec![],
-                },
-            },
-        ];
-
-        let rendered = generated_selection_alternatives(&selections);
-        assert_eq!(rendered.matches("GeneratedSelectionAlternative").count(), 2);
-        assert!(rendered.contains(
-            "source_record: \"SELECT_A\", asm: \"op.a $dst;\", predicates: &[\"HasA\", \"HasCommon\"], constraints: GeneratedSelectionConstraints { address_space: Some(GeneratedSelectionAddressSpace::Generic), immediate_bindings: &[] }"
-        ));
-        assert!(rendered.contains(
-            "source_record: \"SELECT_B\", asm: \"op.b $dst;\", predicates: &[\"HasB\"], constraints: GeneratedSelectionConstraints { address_space: Some(GeneratedSelectionAddressSpace::Shared), immediate_bindings: &[] }"
-        ));
-    }
-
-    #[test]
-    fn stmatrix_rendering_preserves_all_four_public_and_backend_contracts() {
-        let catalog = catalog_with_stmatrix();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(stmatrices(&catalog).count(), 4);
-
-        let compatibility = render_compat_stmatrix(&catalog, "test-hash");
-        for signature in [
-            "pub unsafe fn stmatrix_m8n8_x2(smem_ptr: *mut u8, r0: u32, r1: u32)",
-            "pub unsafe fn stmatrix_m8n8_x2_trans(smem_ptr: *mut u8, r0: u32, r1: u32)",
-            "pub unsafe fn stmatrix_m8n8_x4(smem_ptr: *mut u8, r0: u32, r1: u32, r2: u32, r3: u32)",
-            "pub unsafe fn stmatrix_m8n8_x4_trans(smem_ptr: *mut u8, r0: u32, r1: u32, r2: u32, r3: u32)",
-        ] {
-            assert!(compatibility.contains(signature));
-        }
-        assert!(compatibility.contains("All warp lanes must participate"));
-
-        let dialect_mod = render_dialect_mod(&catalog, "test-hash");
-        assert!(dialect_mod.contains("mod stmatrix;"));
-        assert!(dialect_mod.contains("stmatrix::register(ctx)"));
-        let dialect = render_dialect_stmatrix(&catalog, "test-hash");
-        for (op_type, op_name, operands) in [
-            ("StmatrixM8n8X2Op", "nvvm.stmatrix_m8n8_x2", 3),
-            ("StmatrixM8n8X2TransOp", "nvvm.stmatrix_m8n8_x2_trans", 3),
-            ("StmatrixM8n8X4Op", "nvvm.stmatrix_m8n8_x4", 5),
-            ("StmatrixM8n8X4TransOp", "nvvm.stmatrix_m8n8_x4_trans", 5),
-        ] {
-            assert!(dialect.contains(&format!("pub struct {op_type};")));
-            assert!(dialect.contains(&format!("name = \"{op_name}\"")));
-            assert!(dialect.contains(&format!("NOpdsInterface<{operands}>")));
-            assert!(dialect.contains(&format!("{op_type}::register(ctx)")));
-        }
-
-        let importer = render_importer(&catalog, "test-hash");
-        for (path, op_type, marker) in [
-            (
-                "cuda_device::tcgen05::stmatrix_m8n8_x2",
-                "StmatrixM8n8X2Op",
-                "v1:i0301",
-            ),
-            (
-                "cuda_device::tcgen05::stmatrix_m8n8_x2_trans",
-                "StmatrixM8n8X2TransOp",
-                "v1:i0302",
-            ),
-            (
-                "cuda_device::tcgen05::stmatrix_m8n8_x4",
-                "StmatrixM8n8X4Op",
-                "v1:i0303",
-            ),
-            (
-                "cuda_device::tcgen05::stmatrix_m8n8_x4_trans",
-                "StmatrixM8n8X4TransOp",
-                "v1:i0304",
-            ),
-        ] {
-            assert!(importer.contains(path));
-            assert!(importer.contains(&format!("{op_type}::get_concrete_op_info()")));
-            assert!(importer.contains(&format!(
-                "set_generated_intrinsic_marker(ctx, store, \"{marker}\")"
-            )));
-        }
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert_eq!(
-            lowering
-                .matches("impl MirToLlvmConversion for StmatrixM8n8")
-                .count(),
-            4
-        );
-        assert!(lowering.contains("IntrinsicBackend::LlvmNvptx"));
-        assert!(lowering.contains("IntrinsicBackend::LibNvvm"));
-        assert!(lowering.contains("cast_to_shared_addrspace"));
-        assert!(lowering.contains("llvm_nvvm_stmatrix_sync_aligned_m8n8_x2_b16_p3"));
-        assert!(lowering.contains("llvm_nvvm_stmatrix_sync_aligned_m8n8_x4_trans_b16_p3"));
-        assert!(
-            lowering.contains("stmatrix.sync.aligned.m8n8.x{register_count}{trans}.shared.b16")
-        );
-        assert!(lowering.contains("std::iter::once(\"~{memory}\")"));
-
-        let x2 = stmatrices(&catalog)
-            .find(|record| record.id == "stmatrix_m8n8_x2_b16")
-            .unwrap();
-        let probe = render_probe(&catalog, x2, "test-hash");
-        assert!(probe.contains(
-            "declare void @llvm.nvvm.stmatrix.sync.aligned.m8n8.x2.b16.p3(ptr addrspace(3), i32, i32)"
-        ));
-        assert!(probe.contains("%shared = addrspacecast ptr %generic to ptr addrspace(3)"));
-        assert!(probe.contains(
-            "call void @llvm.nvvm.stmatrix.sync.aligned.m8n8.x2.b16.p3(ptr addrspace(3) %shared, i32 %r0, i32 %r1)"
-        ));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/stmatrix.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/stmatrix.rs"
-        )));
-    }
-
-    #[test]
-    fn cluster_composites_use_generated_private_sreg_leaves() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-
-        let leaves = render_compat_cluster_sreg(&catalog, "test-hash");
-        assert_eq!(leaves.matches("pub(crate) fn __cluster_").count(), 6);
-        for name in [
-            "__cluster_idxX",
-            "__cluster_idxY",
-            "__cluster_idxZ",
-            "__cluster_grid_dimX",
-            "__cluster_grid_dimY",
-            "__cluster_grid_dimZ",
-        ] {
-            assert!(leaves.contains(&format!("pub(crate) fn {name}() -> u32")));
-        }
-        assert!(!leaves.contains("pub fn cluster_ctaidX"));
-        assert!(!leaves.contains("pub fn cluster_nctaidX"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::cluster::__cluster_idxX"));
-        assert!(importer.contains("cuda_device::cluster::__cluster_grid_dimZ"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/cluster_sreg.rs"
-        )));
-    }
-
-    #[test]
-    fn packed_alu_and_conversion_render_exact_pure_inline_ptx_adapters() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(packed_alus(&catalog).count(), 30);
-        assert_eq!(packed_conversions(&catalog).count(), 18);
-
-        let dialect = render_dialect_packed_alu(&catalog, "test-hash");
-        for op in [
-            "FmaBf16x2Op",
-            "FmaReluBf16x2Op",
-            "AddBf16x2Op",
-            "SubBf16x2Op",
-            "MulBf16x2Op",
-            "MinBf16x2Op",
-            "MaxBf16x2Op",
-            "NegBf16x2Op",
-            "AbsBf16x2Op",
-            "FmaF16x2Op",
-            "FmaReluF16x2Op",
-            "AddF16x2Op",
-            "SubF16x2Op",
-            "MulF16x2Op",
-            "MinF16x2Op",
-            "MaxF16x2Op",
-            "NegF16x2Op",
-            "AbsF16x2Op",
-            "AddF32x2Op",
-            "AddFtzF32x2Op",
-            "SubF32x2Op",
-            "SubFtzF32x2Op",
-            "MulF32x2Op",
-            "MulFtzF32x2Op",
-            "FmaF32x2Op",
-            "FmaFtzF32x2Op",
-        ] {
-            assert!(dialect.contains(&format!("pub struct {op}")));
-            assert!(dialect.contains(&format!("{op}::register(ctx)")));
-        }
-        let conversion_dialect = render_dialect_packed_conversion(&catalog, "test-hash");
-        for op in [
-            "CvtF32x2Bf16x2Op",
-            "CvtF16x2F32Op",
-            "CvtRzF16x2F32Op",
-            "CvtRnReluF16x2F32Op",
-            "CvtRnReluBf16x2F32Op",
-            "CvtRzBf16x2F32Op",
-            "CvtRnSatfiniteE4m3x2F32Op",
-            "CvtRnSatfiniteReluE4m3x2F32Op",
-            "CvtRnSatfiniteE5m2x2F32Op",
-            "CvtRnSatfiniteReluE5m2x2F32Op",
-        ] {
-            assert!(conversion_dialect.contains(&format!("pub struct {op}")));
-            assert!(conversion_dialect.contains(&format!("{op}::register(ctx)")));
-        }
-        assert!(conversion_dialect.contains("low f16 lane"));
-        assert!(conversion_dialect.contains("low bf16 lane"));
-        assert!(conversion_dialect.contains("low e4m3 lane"));
-        assert!(conversion_dialect.contains("low e5m2 lane"));
-        assert!(conversion_dialect.contains("vec![low, high]"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::bf16x2::fma_bf16x2"));
-        assert!(importer.contains("cuda_device::f16x2::fma_f16x2"));
-        assert!(importer.contains("cuda_device::convert::cvt_bf16x2_f32"));
-        assert!(importer.contains("cuda_device::convert::cvt_f16x2_f32"));
-        assert!(importer.contains("cuda_device::convert::cvt_rz_bf16x2_f32"));
-        assert!(importer.contains("cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32"));
-        assert!(importer.contains("cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32"));
-        assert!(importer.contains("FmaBf16x2Op::build(ctx, arg0, arg1, arg2)"));
-        assert!(importer.contains("CvtF32x2Bf16x2Op::build(ctx, arg0, arg1)"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        for mnemonic in [
-            "fma.rn.bf16x2",
-            "fma.rn.relu.bf16x2",
-            "add.rn.bf16x2",
-            "sub.rn.bf16x2",
-            "mul.rn.bf16x2",
-            "min.bf16x2",
-            "max.bf16x2",
-            "neg.bf16x2",
-            "abs.bf16x2",
-            "fma.rn.f16x2",
-            "fma.rn.relu.f16x2",
-            "add.rn.f16x2",
-            "sub.rn.f16x2",
-            "mul.rn.f16x2",
-            "min.f16x2",
-            "max.f16x2",
-            "neg.f16x2",
-            "abs.f16x2",
-        ] {
-            assert!(lowering.contains(&format!(
-                "convert_generated_packed_alu(ctx, rewriter, self.get_operation(), \"{mnemonic}\", 32)"
-            )));
-        }
-        for mnemonic in [
-            "add.rn.f32x2",
-            "add.rn.ftz.f32x2",
-            "sub.rn.f32x2",
-            "sub.rn.ftz.f32x2",
-            "mul.rn.f32x2",
-            "mul.rn.ftz.f32x2",
-            "fma.rn.f32x2",
-            "fma.rn.ftz.f32x2",
-        ] {
-            assert!(lowering.contains(&format!(
-                "convert_generated_packed_alu(ctx, rewriter, self.get_operation(), \"{mnemonic}\", 64)"
-            )));
-        }
-        for mnemonic in [
-            "cvt.rn.bf16x2.f32",
-            "cvt.rn.f16x2.f32",
-            "cvt.rz.f16x2.f32",
-            "cvt.rn.relu.f16x2.f32",
-            "cvt.rn.relu.bf16x2.f32",
-            "cvt.rz.bf16x2.f32",
-        ] {
-            assert!(lowering.contains(&format!(
-                "convert_generated_packed_f32x2(ctx, rewriter, self.get_operation(), None, \"{mnemonic}\", 32)"
-            )));
-        }
-        for (intrinsic, mnemonic) in [
-            ("llvm_nvvm_ff_to_e4m3x2_rn", "cvt.rn.satfinite.e4m3x2.f32"),
-            (
-                "llvm_nvvm_ff_to_e4m3x2_rn_relu",
-                "cvt.rn.satfinite.relu.e4m3x2.f32",
-            ),
-            ("llvm_nvvm_ff_to_e5m2x2_rn", "cvt.rn.satfinite.e5m2x2.f32"),
-            (
-                "llvm_nvvm_ff_to_e5m2x2_rn_relu",
-                "cvt.rn.satfinite.relu.e5m2x2.f32",
-            ),
-        ] {
-            assert!(lowering.contains(&format!(
-                "convert_generated_packed_f32x2(ctx, rewriter, self.get_operation(), Some(\"{intrinsic}\"), \"{mnemonic}\", 16)"
-            )));
-        }
-
-        for record in packed_alus(&catalog) {
-            let probe = render_probe(&catalog, record, "test-hash");
-            let register = packed_alu_register_constraint(record);
-            let constraints = std::iter::once(format!("={register}"))
-                .chain(std::iter::repeat_n(
-                    register.to_owned(),
-                    record.rust.arguments.len(),
-                ))
-                .collect::<Vec<_>>()
-                .join(",");
-            assert!(probe.contains(&format!("\", \"{constraints}\"")));
-            assert!(!probe.contains("asm sideeffect"));
-            assert!(!probe.contains("~{memory}"));
-        }
-        let mut typed_probe_count = 0;
-        for conversion in packed_conversions(&catalog) {
-            let probe = render_probe(&catalog, conversion, "test-hash");
-            if packed_conversion_typed_llvm_name(conversion).is_some() {
-                typed_probe_count += 1;
-                let llvm = llvm(conversion);
-                let symbol = llvm.resolved_symbol.as_deref().unwrap_or(&llvm.symbol);
-                assert!(probe.contains(&format!("declare i16 @{symbol}(float, float)")));
-                assert!(probe.contains(&format!("call i16 @{symbol}(float %high, float %low)")));
-                assert!(!probe.contains(" asm "));
-            } else if packed_conversion_source(conversion) == PackedConversionSourceFormat::F32x2 {
-                assert!(probe.contains(&format!(
-                    "asm \"{} $0, $2, $1;\", \"{}\"(float %low, float %high)",
-                    packed_conversion_ptx_mnemonic(conversion),
-                    packed_conversion_constraint(conversion),
-                )));
-                assert!(!probe.contains("declare "));
-            } else {
-                // One packed source operand, so no high/low reordering.
-                let source_ty = format!("i{}", packed_conversion_source_width(conversion));
-                assert!(probe.contains(&format!(
-                    "asm \"{} $0, $1;\", \"{}\"({source_ty} %packed)",
-                    packed_conversion_ptx_mnemonic(conversion),
-                    packed_conversion_constraint(conversion),
-                )));
-                assert!(!probe.contains("declare "));
-            }
-            assert!(!probe.contains("asm sideeffect"));
-        }
-        assert_eq!(typed_probe_count, 4);
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("pub fn i0062(_arg0: u32, _arg1: u32, _arg2: u32) -> u32"));
-        assert!(raw.contains("pub fn i0071(_arg0: f32, _arg1: f32) -> u32"));
-        assert!(raw.contains("pub fn i0072(_arg0: u32, _arg1: u32, _arg2: u32) -> u32"));
-        assert!(raw.contains("pub fn i0085(_arg0: f32, _arg1: f32) -> u32"));
-        assert!(raw.contains("pub fn i0259(_arg0: f32, _arg1: f32) -> u16"));
-        assert!(raw.contains("pub fn i0262(_arg0: f32, _arg1: f32) -> u16"));
-        assert!(raw.contains("pub fn i0995(_arg0: u64, _arg1: u64) -> u64"));
-        assert!(raw.contains("pub fn i1002(_arg0: u64, _arg1: u64, _arg2: u64) -> u64"));
-        assert!(!raw.contains("#[must_use]\n#[inline(never)]\npub fn i0062"));
-        let f16_raw = raw.find("pub fn i0072").unwrap();
-        assert!(raw[..f16_raw].ends_with("#[must_use]\n#[inline(never)]\n"));
-
-        let compatibility =
-            render_compat_packed_alu(&catalog, "test-hash", PackedAluFormat::Bf16x2);
-        assert!(compatibility.contains("pub fn fma_bf16x2(arg0: u32, arg1: u32, arg2: u32)"));
-        assert!(!compatibility.contains("fma_f16x2"));
-        assert!(compatibility.contains("let _ = arg0;"));
-        assert!(!compatibility.contains("let _ = (arg0);"));
-        let compatibility = render_compat_packed_alu(&catalog, "test-hash", PackedAluFormat::F16x2);
-        let f16_compat = compatibility.find("pub fn fma_f16x2").unwrap();
-        assert!(compatibility[..f16_compat].ends_with("#[must_use]\n#[inline(never)]\n"));
-        assert!(!compatibility.contains("fma_bf16x2"));
-        let compatibility = render_compat_packed_alu(&catalog, "test-hash", PackedAluFormat::F32x2);
-        assert!(compatibility.contains("pub fn add_f32x2(arg0: u64, arg1: u64) -> u64"));
-        assert!(
-            compatibility.contains("pub fn fma_ftz_f32x2(arg0: u64, arg1: u64, arg2: u64) -> u64")
-        );
-        assert!(!compatibility.contains("fma_f16x2"));
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("`fma_f16x2` carries one packed `f16x2` value in a `u32`"));
-        assert!(reference.contains(
-            "native instruction starts at PTX 4.2 / `sm_53`; cuda-oxide admits it from sm_70+"
-        ));
-        assert!(reference.contains("LLVM-NVPTX PTX 6.0 on sm_70+"));
-        assert!(reference.contains("libNVVM PTX 4.2 on sm_75+"));
-        assert!(reference.contains(
-            "`cvt_rn_relu_f16x2_f32` converts two `f32` inputs to packed `f16x2` using nearest-even rounding with ReLU"
-        ));
-        assert!(reference.contains("pure `cvt.rz.bf16x2.f32` inline PTX"));
-        assert!(reference.contains(
-            "LLVM-NVPTX uses typed `llvm.nvvm.ff.to.e4m3x2.rn` with `[high, low]` inputs; libNVVM uses pure `cvt.rn.satfinite.e4m3x2.f32` inline PTX"
-        ));
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/bf16x2.rs")));
-        assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/f16x2.rs")));
-        assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/f32x2.rs")));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/convert.rs"
-        )));
-        let compatibility = render_compat_packed_conversion(
-            &catalog,
-            "test-hash",
-            "cuda_device::convert::",
-            "convert",
-            ("lo", "hi"),
-        );
-        assert!(compatibility.contains("pub fn cvt_bf16x2_f32(lo: f32, hi: f32) -> u32"));
-        assert!(compatibility.contains("pub fn cvt_f16x2_f32(lo: f32, hi: f32) -> u32"));
-        assert!(compatibility.contains("pub fn cvt_rz_bf16x2_f32(lo: f32, hi: f32) -> u32"));
-        assert!(
-            compatibility.contains("pub fn cvt_rn_satfinite_e4m3x2_f32(lo: f32, hi: f32) -> u16")
-        );
-        assert!(
-            compatibility
-                .contains("pub fn cvt_rn_satfinite_relu_e5m2x2_f32(lo: f32, hi: f32) -> u16")
-        );
-        assert!(!compatibility.contains("pub fn cvt_f32x2_bf16x2("));
-        assert!(!outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/tcgen05_conversion.rs"
-        )));
-    }
-
-    #[test]
-    fn scalar_tf32_conversions_render_one_exact_attribute_carrier() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        let records = scalar_conversions(&catalog).collect::<Vec<_>>();
-        assert_eq!(records.len(), 10);
-
-        for record in &records {
-            assert_eq!(record.rust.arguments, ["f32"]);
-            assert_eq!(record.rust.result, "u32");
-            assert!(record.backend_lowerings.iter().any(|lowering| {
-                lowering.backend == IntrinsicBackend::LlvmNvptx
-                    && lowering.mechanism == BackendLoweringMechanism::TypedNvvm
-            }));
-            assert!(record.backend_lowerings.iter().any(|lowering| {
-                lowering.backend == IntrinsicBackend::LibNvvm
-                    && lowering.mechanism == BackendLoweringMechanism::InlinePtx
-            }));
-        }
-
-        let dialect = render_dialect_scalar_conversion(&catalog, "test-hash");
-        assert_eq!(dialect.matches("pub struct ScalarConversionOp;").count(), 1);
-        assert!(dialect.contains("pub enum ScalarConversionRoundingAttr"));
-        assert!(dialect.contains("pub enum ScalarConversionSaturationAttr"));
-        assert_eq!(
-            dialect
-                .matches("ScalarConversionOp::register(ctx);")
-                .count(),
-            1
-        );
-        for record in &records {
-            assert!(dialect.contains(scalar_conversion_rounding_attr(record)));
-            assert!(dialect.contains(scalar_conversion_saturation_attr(record)));
-        }
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert_eq!(
-            importer
-                .matches("let intrinsic = ScalarConversionOp::build")
-                .count(),
-            10
-        );
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert_eq!(
-            lowering
-                .matches("impl MirToLlvmConversion for ScalarConversionOp")
-                .count(),
-            1
-        );
-        for record in &records {
-            assert!(lowering.contains(&record.llvm_identifier()));
-            assert!(lowering.contains(&scalar_conversion_ptx_mnemonic(record)));
-            let probe = render_probe(&catalog, record, "test-hash");
-            assert!(probe.contains(&format!("declare i32 @{}(float)", llvm(record).symbol)));
-        }
-
-        let targets = render_targets(&catalog, "test-hash");
-        let production_targets = targets.split("\n#[cfg(test)]").next().unwrap();
-        assert_eq!(
-            production_targets
-                .matches("GeneratedIntrinsicVariant::ScalarConversion {")
-                .count(),
-            11
-        );
-        assert!(targets.contains("Operation::get_op::<ScalarConversionOp>"));
-        assert!(targets.contains("GeneratedScalarConversionRounding::NearestAway"));
-        assert!(targets.contains("GeneratedScalarConversionSaturation::ReluSatfinite"));
-
-        let compatibility = render_compat_packed_conversion(
-            &catalog,
-            "test-hash",
-            "cuda_device::convert::",
-            "convert",
-            ("lo", "hi"),
-        );
-        assert!(compatibility.contains("pub fn cvt_rna_tf32_f32(value: f32) -> u32"));
-        assert!(compatibility.contains("pub fn cvt_rz_relu_satfinite_tf32_f32(value: f32) -> u32"));
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("pub fn i0368(_arg0: f32) -> u32"));
-        assert!(raw.contains("pub fn i0377(_arg0: f32) -> u32"));
-    }
-
-    #[test]
-    fn ldmatrix_family_lowering_uses_one_attribute_dispatch_impl() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-
-        let dialect = render_dialect_ldmatrix(&catalog, "test-hash");
-        let rendered = render_lowering(&catalog, "test-hash");
-        assert_eq!(
-            rendered
-                .matches("impl MirToLlvmConversion for LdmatrixOp")
-                .count(),
-            1
-        );
-        assert!(rendered.contains("LdmatrixMultiplicityAttr::X4"));
-        assert!(rendered.contains("LdmatrixMultiplicityAttr::X2"));
-        assert!(rendered.contains("LdmatrixMultiplicityAttr::X1"));
-        assert!(rendered.contains("LdmatrixLayoutAttr::Transposed"));
-        assert!(rendered.contains("llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16_p3"));
-        for (op_type, op_name, count, instruction_head, intrinsic) in [
-            (
-                "LdmatrixX1Op",
-                "nvvm.ldmatrix_x1",
-                1,
-                "ldmatrix.sync.aligned.m8n8.x1.shared.b16",
-                "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_b16_p3",
-            ),
-            (
-                "LdmatrixX1TransOp",
-                "nvvm.ldmatrix_x1_trans",
-                1,
-                "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16",
-                "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_trans_b16_p3",
-            ),
-            (
-                "LdmatrixX2Op",
-                "nvvm.ldmatrix_x2",
-                2,
-                "ldmatrix.sync.aligned.m8n8.x2.shared.b16",
-                "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_b16_p3",
-            ),
-            (
-                "LdmatrixX2TransOp",
-                "nvvm.ldmatrix_x2_trans",
-                2,
-                "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16",
-                "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
-            ),
-            (
-                "LdmatrixX4Op",
-                "nvvm.ldmatrix_x4",
-                4,
-                "ldmatrix.sync.aligned.m8n8.x4.shared.b16",
-                "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_b16_p3",
-            ),
-            (
-                "LdmatrixX4TransOp",
-                "nvvm.ldmatrix_x4_trans",
-                4,
-                "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16",
-                "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
-            ),
-        ] {
-            assert!(dialect.contains(&format!("pub struct {op_type};")));
-            assert!(dialect.contains(&format!("name = {op_name:?}")));
-            assert!(dialect.contains(&format!("NResultsInterface<{count}>")));
-            assert!(dialect.contains(&format!("{op_type}::register(ctx);")));
-            assert_eq!(
-                rendered
-                    .matches(&format!("impl MirToLlvmConversion for {op_type}"))
-                    .count(),
-                1
-            );
-            assert!(rendered.contains(&format!(
-                "self.get_operation(), {count}, {instruction_head:?}, {intrinsic:?}"
-            )));
-        }
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(!importer.contains("LdmatrixX1Op"));
-        assert!(!importer.contains("LdmatrixX4TransOp"));
-        let targets = render_targets(&catalog, "test-hash");
-        for op_name in [
-            "nvvm.ldmatrix_x1",
-            "nvvm.ldmatrix_x1_trans",
-            "nvvm.ldmatrix_x2",
-            "nvvm.ldmatrix_x2_trans",
-            "nvvm.ldmatrix_x4",
-            "nvvm.ldmatrix_x4_trans",
-        ] {
-            assert!(targets.contains(&format!("{op_name:?} => Some(")));
-        }
-        assert_eq!(ldmatrix(&catalog).count(), 18);
-        assert!(dialect.contains("LdmatrixShapeAttr::M16n16"));
-        assert!(dialect.contains("LdmatrixShapeAttr::M8n16"));
-        assert!(dialect.contains("LdmatrixElementAttr::B8x16B4x16P64"));
-        assert!(rendered.contains(
-            "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db4x16_up64_dp3"
-        ));
-        assert!(rendered.contains("ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b6x16_p32"));
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains(
-            "Instruction floor PTX 8.6; the selected target may require a newer PTX version."
-        ));
-        assert!(raw.contains("no lane may have exited"));
-        assert!(raw.contains("have 32 readable shared-memory bytes"));
-        assert!(raw.contains("have 16 readable shared-memory bytes"));
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains(BLACKWELL_LDMATRIX_EFFECTIVE_FLOORS));
-    }
-
-    #[test]
-    fn ldmatrix_x1_probe_keeps_its_pointer_operand() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        let record = catalog
-            .intrinsics
-            .iter()
-            .find(|record| record.id == "ldmatrix_m8n8_x1_b16")
-            .unwrap();
-
-        let rendered = render_probe(&catalog, record, "test-hash");
-        assert!(rendered.contains(
-            "declare i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.b16.p3(ptr addrspace(3))"
-        ));
-        assert!(rendered.contains("define i32 @probe_ldmatrix_m8n8_x1_b16(ptr %generic)"));
-        assert!(!rendered.contains("@llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.b16.p3()"));
-    }
-
-    #[test]
-    fn packed_atomic_family_uses_one_attribute_dispatch_impl() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        let rendered = render_lowering(&catalog, "test-hash");
-        assert_eq!(
-            rendered
-                .matches("impl MirToLlvmConversion for PackedAtomicAddOp")
-                .count(),
-            1
-        );
-        assert_eq!(
-            rendered.matches("PackedAtomicFormatAttr::F16x2)").count(),
-            1
-        );
-        assert_eq!(
-            rendered.matches("PackedAtomicFormatAttr::Bf16x2)").count(),
-            1
-        );
-        for (op_type, ptx_type) in [
-            ("NvvmAtomAddF16x2Op", "f16x2"),
-            ("NvvmAtomAddBf16x2Op", "bf16x2"),
-        ] {
-            assert_eq!(
-                rendered
-                    .matches(&format!("impl MirToLlvmConversion for {op_type}"))
-                    .count(),
-                1
-            );
-            assert!(rendered.contains(&format!(
-                "convert_packed_atom_add(ctx, rewriter, self.get_operation(), \"{ptx_type}\")"
-            )));
-        }
-
-        let dialect = render_dialect_packed_atomic(&catalog, "test-hash");
-        for (op_type, op_name) in [
-            ("NvvmAtomAddF16x2Op", "nvvm.atom_add_f16x2"),
-            ("NvvmAtomAddBf16x2Op", "nvvm.atom_add_bf16x2"),
-        ] {
-            assert!(dialect.contains(&format!("pub struct {op_type};")));
-            assert!(dialect.contains(&format!("name = \"{op_name}\"")));
-            assert!(dialect.contains(&format!("{op_type}::register(ctx);")));
-        }
-    }
-
-    #[test]
-    fn packed_atomic_raw_abi_is_unsafe_and_must_use() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        let rendered = render_raw_abi(&catalog, "test-hash").unwrap();
-        for abi_id in ["i0014", "i0015"] {
-            let signature = format!("pub unsafe fn {abi_id}(_arg0: *mut u32, _arg1: u32) -> u32");
-            let index = rendered.find(&signature).unwrap();
-            assert!(rendered[..index].ends_with("#[must_use]\n#[inline(never)]\n"));
-        }
-    }
-
-    #[test]
-    fn packed_atomic_compatibility_preserves_paths_signature_and_safety() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        let rendered = render_compat_packed_atomic(&catalog, "test-hash");
-
-        for name in ["atom_add_f16x2", "atom_add_bf16x2"] {
-            let signature = format!("pub unsafe fn {name}(addr: *mut u32, val: u32) -> u32");
-            let index = rendered.find(&signature).unwrap();
-            assert!(rendered[..index].ends_with("#[must_use]\n#[inline(never)]\n"));
-            assert!(rendered.contains(&format!(
-                "unreachable!(\"{name} called outside CUDA kernel context\")"
-            )));
-        }
-        assert!(rendered.contains("relaxed GPU-scope operation"));
-        assert!(rendered.contains("low lane first"));
-        assert!(rendered.contains("may not form one old 32-bit snapshot"));
-        assert!(rendered.contains("Requires PTX 6.2 and `sm_70+`"));
-        assert!(rendered.contains("Requires PTX 7.8 and `sm_90+`"));
-        assert!(rendered.contains("four writable, four-byte-aligned bytes in global memory"));
-        assert!(rendered.contains("whole-word atomic or non-atomic lane access"));
-        assert!(rendered.contains("Racing atomics must use mutually inclusive scopes"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert_eq!(
-            outputs.get(&PathBuf::from("crates/cuda-device/src/generated/atomic.rs")),
-            Some(&rendered)
-        );
-    }
-
-    #[test]
-    fn cp_async_rendering_preserves_compatibility_dispatch_and_backend_routes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(cp_async_copies(&catalog).count(), 8);
-        assert_eq!(cp_async_controls(&catalog).count(), 3);
-        assert_eq!(cp_async_mbarriers(&catalog).count(), 4);
-
-        let compatibility = render_compat_cp_async_copy(&catalog, "test-hash");
-        for signature in [
-            "pub unsafe fn cp_async_ca_4(_shared_dst: *mut u32, _global_src: *const u32)",
-            "pub unsafe fn cp_async_ca_8(_shared_dst: *mut u32, _global_src: *const u32)",
-            "pub unsafe fn cp_async_ca_16(_shared_dst: *mut u32, _global_src: *const u32)",
-            "pub unsafe fn cp_async_ca_zfill_4(_shared_dst: *mut u32, _global_src: *const u8, _src_size: u32)",
-            "pub unsafe fn cp_async_ca_zfill_8(_shared_dst: *mut u32, _global_src: *const u8, _src_size: u32)",
-            "pub unsafe fn cp_async_ca_zfill_16(_shared_dst: *mut u32, _global_src: *const u8, _src_size: u32)",
-            "pub unsafe fn cp_async_cg_16(_shared_dst: *mut u32, _global_src: *const u32)",
-            "pub unsafe fn cp_async_cg_zfill_16(_shared_dst: *mut u32, _global_src: *const u8, _src_size: u32)",
-            "pub unsafe fn cp_async_commit_group()",
-            "pub unsafe fn cp_async_wait_all()",
-            "pub unsafe fn cp_async_wait_group(_max_pending: u32)",
-            "pub unsafe fn cp_async_mbarrier_arrive(_barrier: *mut crate::barrier::Barrier)",
-            "pub unsafe fn cp_async_mbarrier_arrive_shared(_barrier: *mut crate::barrier::Barrier)",
-            "pub unsafe fn cp_async_mbarrier_arrive_noinc(_barrier: *mut crate::barrier::Barrier)",
-            "pub unsafe fn cp_async_mbarrier_arrive_noinc_shared(_barrier: *mut crate::barrier::Barrier)",
-        ] {
-            assert!(compatibility.contains(signature));
-        }
-
-        let dialect = render_dialect_cp_async_copy(&catalog, "test-hash");
-        let importer = render_importer(&catalog, "test-hash");
-        let lowering = render_lowering(&catalog, "test-hash");
-        let targets = render_targets(&catalog, "test-hash");
-        for record in cp_async_copies(&catalog)
-            .chain(cp_async_controls(&catalog))
-            .chain(cp_async_mbarriers(&catalog))
-        {
-            assert!(dialect.contains(&format!("pub struct {}", record.dialect.op_type)));
-            assert!(dialect.contains(&format!("{}::register(ctx)", record.dialect.op_type)));
-            assert!(importer.contains(&record.rust.canonical_path));
-            for path in &record.rust.compatibility_paths {
-                assert!(importer.contains(path));
-            }
-            assert!(importer.contains(&intrinsic_marker(&catalog, record)));
-            assert!(lowering.contains(&format!(
-                "impl MirToLlvmConversion for {}",
-                record.dialect.op_type
-            )));
-            assert!(lowering.contains(&record.llvm_identifier()));
-            assert!(
-                record
-                    .backend_lowerings
-                    .iter()
-                    .any(|entry| entry.backend == IntrinsicBackend::LlvmNvptx)
-            );
-            assert!(
-                record
-                    .backend_lowerings
-                    .iter()
-                    .any(|entry| entry.backend == IntrinsicBackend::LibNvvm)
-            );
-            assert!(targets.contains(&format!("id: {:?}", record.id)));
-        }
-        assert_eq!(dialect.matches("::register(ctx);").count(), 15);
-        assert!(lowering.contains("convert_generated_cp_async_copy"));
-        assert!(lowering.contains("convert_generated_cp_async_control"));
-        assert!(lowering.contains("convert_generated_cp_async_mbarrier"));
-    }
-
-    #[test]
-    fn cp_async_mbarrier_rendering_preserves_counting_and_state_space_routes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        let records: Vec<_> = cp_async_mbarriers(&catalog).collect();
-        assert_eq!(records.len(), 4);
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("pub unsafe fn i0101(_arg0: *mut u64)"));
-        assert!(raw.contains("live, initialized, eight-byte-aligned mbarrier"));
-        assert!(raw.contains("initial pending count must already include"));
-
-        let compatibility = render_compat_cp_async_copy(&catalog, "test-hash");
-        assert_eq!(
-            compatibility
-                .matches("That increment must not exceed the barrier's pending-count limit.")
-                .count(),
-            2
-        );
-
-        let dialect = render_dialect_cp_async_copy(&catalog, "test-hash");
-        assert!(dialect.contains("mutable generic/shared pointer to u64"));
-        let importer = render_importer(&catalog, "test-hash");
-        let lowering = render_lowering(&catalog, "test-hash");
-        for record in &records {
-            assert!(importer.contains(&format!(
-                "let bridge = {}::build(ctx, barrier)",
-                record.dialect.op_type
-            )));
-            assert!(lowering.contains(&record.llvm_identifier()));
-            let routes: BTreeSet<_> = record
-                .backend_lowerings
-                .iter()
-                .map(|route| (route.backend, route.mechanism))
-                .collect();
-            assert_eq!(
-                routes,
-                BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ])
-            );
-        }
-        assert!(lowering.contains("\"arrive\", \"generic\""));
-        assert!(lowering.contains("\"arrive\", \"shared\""));
-        assert!(lowering.contains("\"arrive_no_inc\", \"generic\""));
-        assert!(lowering.contains("\"arrive_no_inc\", \"shared\""));
-
-        let generic = records
-            .iter()
-            .find(|record| record.id == "cp_async_mbarrier_arrive")
-            .unwrap();
-        let generic_probe = render_probe(&catalog, generic, "test-hash");
-        assert!(generic_probe.contains("declare void @llvm.nvvm.cp.async.mbarrier.arrive(ptr)"));
-        assert!(!generic_probe.contains("addrspacecast"));
-        let shared = records
-            .iter()
-            .find(|record| record.id == "cp_async_mbarrier_arrive_shared")
-            .unwrap();
-        let shared_probe = render_probe(&catalog, shared, "test-hash");
-        assert!(shared_probe.contains("ptr addrspace(3)"));
-        assert!(shared_probe.contains("addrspacecast ptr %barrier_generic"));
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("## cp.async mbarrier contracts"));
-        assert!(reference.contains("cp_async_mbarrier_arrive_noinc`: runtime `unexecuted`"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/async_copy.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/cp_async.rs"
-        )));
-        assert!(!outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/cp_async_mbarrier.rs"
-        )));
-    }
-
-    #[test]
-    fn redux_rendering_preserves_mask_first_api_and_source_first_llvm_order() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        assert_eq!(catalog.schema, crate::resolve::CATALOG_SCHEMA);
-        validate_renderable(&catalog).unwrap();
-
-        assert_eq!(redux(&catalog).count(), 16);
-        let record = redux(&catalog).next().unwrap();
-        assert_eq!(
-            record.redux.as_ref().unwrap().adapter,
-            ReduxAdapter::MaskValueToSourceMemberMask
-        );
-
-        let dialect = render_dialect_redux(&catalog, "test-hash");
-        assert!(dialect.contains("name = \"nvvm.redux_sync_add\""));
-        assert!(dialect.contains("name = \"nvvm.redux_sync_min\""));
-        assert!(dialect.contains("vec![member_mask, value]"));
-        assert!(dialect.contains("ReduxSyncAddOp::register(ctx)"));
-        assert!(dialect.contains("Signedness::Signed"));
-
-        assert!(dialect.contains("name = \"nvvm.redux_sync_fmin\""));
-        assert!(dialect.contains("types::{FP32Type, IntegerType, Signedness}"));
-        assert!(dialect.contains("let result_ty = FP32Type::get(ctx);"));
-        assert!(dialect.contains("is_f32(ctx, op.get_operand(1).get_type(ctx))"));
-        assert!(dialect.contains("is_f32(ctx, op.get_result(0).get_type(ctx))"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::warp::redux_sync_add"));
-        assert!(importer.contains("let (member_mask, last_op)"));
-        assert!(
-            importer.contains("let reduction = ReduxSyncAddOp::build(ctx, member_mask, value)")
-        );
-        assert!(importer.contains("set_generated_intrinsic_marker(ctx, reduction, \"v1:i0017\")"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("impl MirToLlvmConversion for ReduxSyncAddOp"));
-        assert!(
-            lowering.contains("convert_redux(ctx, rewriter, self.get_operation(), operands_info")
-        );
-        assert!(lowering.contains("\"llvm_nvvm_redux_sync_add\""));
-
-        let probe = render_probe(&catalog, record, "test-hash");
-        assert!(probe.contains("define i32 @probe_redux_sync_add(i32 %member_mask, i32 %value)"));
-        assert!(probe.contains("call i32 @llvm.nvvm.redux.sync.add(i32 %value, i32 %member_mask)"));
-
-        let f32_record = redux(&catalog)
-            .find(|record| record.id == "redux_sync_min_f32")
-            .unwrap();
-        let f32_probe = render_probe(&catalog, f32_record, "test-hash");
-        assert!(
-            f32_probe
-                .contains("define float @probe_redux_sync_min_f32(i32 %member_mask, float %value)")
-        );
-        assert!(
-            f32_probe
-                .contains("call float @llvm.nvvm.redux.sync.fmin(float %value, i32 %member_mask)")
-        );
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        let signature = "pub unsafe fn i0017(_arg0: u32, _arg1: u32) -> u32";
-        let index = raw.find(signature).unwrap();
-        assert!(raw[..index].ends_with("#[must_use]\n#[inline(never)]\n"));
-        assert!(raw.contains("pub unsafe fn i0019(_arg0: u32, _arg1: i32) -> i32"));
-        assert!(raw.contains("pub unsafe fn i0024(_arg0: u32, _arg1: u32) -> u32"));
-        assert!(raw.contains("pub unsafe fn i1003(_arg0: u32, _arg1: f32) -> f32"));
-        assert!(raw.contains("The executing lane must be named in `mask`"));
-    }
-
-    #[test]
-    fn vote_rendering_keeps_types_selection_pairs_and_raw_only_uni() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(vote_intrinsics(&catalog).count(), 4);
-
-        let dialect = render_dialect_vote(&catalog, "test-hash");
-        for op in [
-            "VoteSyncAllOp",
-            "VoteSyncAnyOp",
-            "VoteSyncBallotOp",
-            "VoteSyncUniOp",
-        ] {
-            assert!(dialect.contains(&format!("pub struct {op}")));
-            assert!(dialect.contains(&format!("{op}::register(ctx)")));
-        }
-        assert!(dialect.contains("requires i32 member mask, i1 predicate, and i1 result"));
-        assert!(dialect.contains("requires i32 member mask, i1 predicate, and i32 result"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::warp::all_sync"));
-        assert!(!importer.contains("cuda_device::warp::uni_sync"));
-        assert!(importer.contains("let vote = VoteSyncUniOp::build(ctx, member_mask, predicate)"));
-        assert!(importer.contains("set_generated_intrinsic_marker(ctx, vote, \"v1:i0043\")"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("impl MirToLlvmConversion for VoteSyncUniOp"));
-        assert!(lowering.contains("\"llvm_nvvm_vote_uni_sync\""));
-        assert!(
-            lowering.contains("convert_vote(ctx, rewriter, self.get_operation(), operands_info")
-        );
-
-        let record = vote_intrinsics(&catalog)
-            .find(|record| record.id == "ballot_sync")
-            .unwrap();
-        assert_eq!(record.selections.len(), 2);
-        let probe = render_probe(&catalog, record, "test-hash");
-        assert!(probe.contains("define i32 @probe_ballot_sync(i32 %member_mask, i1 %predicate)"));
-        assert!(probe.contains("define i32 @probe_ballot_sync_immediate(i1 %predicate)"));
-        assert!(probe.contains("i32 -1, i1 %predicate"));
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        for abi_id in ["i0040", "i0041", "i0042", "i0043"] {
-            assert!(raw.contains(&format!("pub unsafe fn {abi_id}")));
-        }
-        assert!(raw.contains("Every non-exited lane named in `mask`"));
-    }
-
-    #[test]
-    fn active_mask_and_warp_match_rendering_preserves_backend_and_abi_contracts() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(active_masks(&catalog).count(), 1);
-        assert_eq!(warp_matches(&catalog).count(), 4);
-
-        let dialect = render_dialect_active_mask(&catalog, "test-hash");
-        assert!(dialect.contains("pub struct ActiveMaskOp"));
-        assert!(dialect.contains("NOpdsInterface<0>, NResultsInterface<1>"));
-
-        let match_dialect = render_dialect_warp_match(&catalog, "test-hash");
-        for op in [
-            "MatchAnySyncI32Op",
-            "MatchAnySyncI64Op",
-            "MatchAllSyncI32Op",
-            "MatchAllSyncI64Op",
-        ] {
-            assert!(match_dialect.contains(&format!("pub struct {op}")));
-            assert!(match_dialect.contains(&format!("{op}::register(ctx)")));
-        }
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("IntrinsicBackend::LlvmNvptx => {"));
-        assert!(lowering.contains("convert_active_mask(ctx, rewriter, op, operands_info)"));
-        assert!(lowering.contains("IntrinsicBackend::LibNvvm =>"));
-        assert!(lowering.contains("\"activemask.b32 $0;\""));
-        assert!(lowering.contains("\"=r,~{memory}\""));
-        assert!(lowering.contains("convert_match_any("));
-        assert!(lowering.contains("convert_match_all("));
-        assert!(lowering.contains("\"llvm_nvvm_match_all_sync_i64p\""));
-
-        let match_all = warp_matches(&catalog)
-            .find(|record| record.id == "match_all_sync")
-            .unwrap();
-        let probe = render_probe(&catalog, match_all, "test-hash");
-        for suffix in ["rr", "ri", "ir", "ii"] {
-            assert!(probe.contains(&format!("@probe_match_all_sync_{suffix}")));
-        }
-        assert!(probe.contains("declare { i32, i1 } @llvm.nvvm.match.all.sync.i32p"));
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("pub fn i0044() -> u32"));
-        assert!(!raw.contains("pub unsafe fn i0044() -> u32"));
-        assert!(raw.contains("pub unsafe fn i0045(_arg0: u32, _arg1: u32) -> u32"));
-        assert!(raw.contains("pub unsafe fn i0046(_arg0: u32, _arg1: u64) -> u32"));
-        assert!(raw.contains("pub unsafe fn i0047(_arg0: u32, _arg1: u32) -> u32"));
-        assert!(raw.contains("pub unsafe fn i0048(_arg0: u32, _arg1: u64) -> u32"));
-    }
-
-    #[test]
-    fn warp_barrier_rendering_preserves_mask_and_void_contracts() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(warp_barriers(&catalog).count(), 1);
-
-        let record = warp_barriers(&catalog).next().unwrap();
-        assert_eq!(record.id, "sync_mask");
-        assert_eq!(
-            record.warp_barrier.as_ref().unwrap().adapter,
-            WarpBarrierAdapter::DirectMemberMask
-        );
-
-        let dialect_mod = render_dialect_mod(&catalog, "test-hash");
-        assert!(dialect_mod.contains("mod warp_barrier;"));
-        assert!(dialect_mod.contains("warp_barrier::register(ctx)"));
-
-        let dialect = render_dialect_warp_barrier(&catalog, "test-hash");
-        assert!(dialect.contains("pub struct BarWarpSyncOp"));
-        assert!(dialect.contains("NOpdsInterface<1>, NResultsInterface<0>"));
-        assert!(dialect.contains("vec![member_mask]"));
-        assert!(dialect.contains("op.get_num_operands() != 1 || op.get_num_results() != 0"));
-        assert!(dialect.contains("if !is_i32(ctx, op.get_operand(0).get_type(ctx))"));
-        assert!(dialect.contains("requires exactly one member-mask operand and no results"));
-        assert!(dialect.contains("member mask must be i32"));
-        assert!(dialect.contains("BarWarpSyncOp::register(ctx)"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::warp::sync_mask"));
-        assert!(importer.contains("let barrier = BarWarpSyncOp::build(ctx, member_mask)"));
-        assert!(importer.contains("set_generated_intrinsic_marker(ctx, barrier, \"v1:i0049\")"));
-        assert!(importer.contains("helpers::emit_goto(ctx, *target_idx, barrier"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("impl MirToLlvmConversion for BarWarpSyncOp"));
-        assert!(
-            lowering.contains(
-                "convert_bar_warp_sync(ctx, rewriter, self.get_operation(), operands_info)"
-            )
-        );
-
-        let probe = render_probe(&catalog, record, "test-hash");
-        assert!(probe.contains("declare void @llvm.nvvm.bar.warp.sync(i32)"));
-        assert!(probe.contains("define void @probe_sync_mask(i32 %member_mask)"));
-        assert!(probe.contains("call void @llvm.nvvm.bar.warp.sync(i32 %member_mask)"));
-        assert!(probe.contains("define void @probe_sync_mask_immediate()"));
-        assert!(probe.contains("call void @llvm.nvvm.bar.warp.sync(i32 -1)"));
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("pub unsafe fn i0049(_arg0: u32) -> ()"));
-        assert!(raw.contains("On `sm_6x` and earlier"));
-        assert!(raw.contains("no lane outside `mask` may be active"));
-        assert!(raw.contains("The barrier orders memory accesses among participating lanes"));
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("## Warp-barrier contract"));
-        assert!(reference.contains("no unnamed lane may be active"));
-        assert!(reference.contains("Both immediate and register masks are admitted"));
-    }
-
-    #[test]
-    fn warp_shuffle_rendering_owns_all_i32_f32_and_i64_modes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(warp_shuffles(&catalog).count(), 12);
-
-        let dialect_mod = render_dialect_mod(&catalog, "test-hash");
-        assert!(dialect_mod.contains("mod warp_shuffle;"));
-        assert!(dialect_mod.contains("warp_shuffle::register(ctx)"));
-
-        let dialect = render_dialect_warp_shuffle(&catalog, "test-hash");
-        for op in [
-            "ShflSyncIdxI32Op",
-            "ShflSyncBflyI32Op",
-            "ShflSyncDownI32Op",
-            "ShflSyncUpI32Op",
-            "ShflSyncIdxF32Op",
-            "ShflSyncBflyF32Op",
-            "ShflSyncDownF32Op",
-            "ShflSyncUpF32Op",
-            "ShflSyncIdxI64Op",
-            "ShflSyncBflyI64Op",
-            "ShflSyncDownI64Op",
-            "ShflSyncUpI64Op",
-        ] {
-            assert!(dialect.contains(&format!("pub struct {op}")));
-            assert!(dialect.contains(&format!("{op}::register(ctx)")));
-        }
-        assert!(dialect.contains("vec![member_mask, value, lane_or_delta]"));
-        assert!(dialect.contains("requires i32 mask/lane and i32 value/result"));
-        assert!(dialect.contains("requires i32 mask/lane and f32 value/result"));
-        assert!(dialect.contains("requires i32 mask/lane and i64 value/result"));
-        assert!(dialect.contains("fn is_i64"));
-        assert!(dialect.contains("integer.width() == 64"));
-        assert!(dialect.contains("IntegerType::get(ctx, 64, Signedness::Unsigned)"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::warp::shuffle_sync"));
-        assert!(importer.contains("cuda_device::warp::shuffle_up_f32_sync"));
-        assert!(importer.contains(
-            "let shuffle = ShflSyncIdxI32Op::build(ctx, member_mask, value, lane_or_delta)"
-        ));
-        assert!(importer.contains("set_generated_intrinsic_marker(ctx, shuffle, \"v1:i0050\")"));
-        for (name, op, marker) in [
-            ("shuffle_u64_sync", "ShflSyncIdxI64Op", "v1:i0058"),
-            ("shuffle_xor_u64_sync", "ShflSyncBflyI64Op", "v1:i0059"),
-            ("shuffle_down_u64_sync", "ShflSyncDownI64Op", "v1:i0060"),
-            ("shuffle_up_u64_sync", "ShflSyncUpI64Op", "v1:i0061"),
-        ] {
-            assert!(importer.contains(&format!(
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::{}",
-                marker.strip_prefix("v1:").unwrap()
-            )));
-            assert!(importer.contains(&format!("cuda_device::warp::{name}")));
-            assert!(importer.contains(&format!(
-                "let shuffle = {op}::build(ctx, member_mask, value, lane_or_delta)"
-            )));
-            assert!(importer.contains(&format!(
-                "set_generated_intrinsic_marker(ctx, shuffle, {marker:?})"
-            )));
-        }
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("impl MirToLlvmConversion for ShflSyncIdxI32Op"));
-        assert!(lowering.contains("convert_shuffle_i32(ctx, rewriter"));
-        assert!(lowering.contains("\"llvm_nvvm_shfl_sync_idx_i32\", 31)"));
-        assert!(lowering.contains("impl MirToLlvmConversion for ShflSyncUpF32Op"));
-        assert!(lowering.contains("convert_shuffle_f32(ctx, rewriter"));
-        assert!(lowering.contains("\"llvm_nvvm_shfl_sync_up_f32\", 0)"));
-
-        for (op, mode, clamp) in [
-            ("ShflSyncIdxI64Op", "idx", 31),
-            ("ShflSyncBflyI64Op", "bfly", 31),
-            ("ShflSyncDownI64Op", "down", 31),
-            ("ShflSyncUpI64Op", "up", 0),
-        ] {
-            assert!(lowering.contains(&format!("impl MirToLlvmConversion for {op}")));
-            assert!(lowering.contains(&format!(
-                "convert_shuffle_i64(ctx, rewriter, self.get_operation(), operands_info, {mode:?}, {clamp})"
-            )));
-        }
-        assert!(!lowering.contains("llvm_nvvm_shfl_sync_idx_i64"));
-        assert!(!lowering.contains("llvm_nvvm_shfl_sync_bfly_i64"));
-        assert!(!lowering.contains("llvm_nvvm_shfl_sync_down_i64"));
-        assert!(!lowering.contains("llvm_nvvm_shfl_sync_up_i64"));
-
-        for record in warp_shuffles(&catalog) {
-            let probe = render_probe(&catalog, record, "test-hash");
-            let shuffle = record.warp_shuffle.as_ref().unwrap();
-            if shuffle.value_kind == WarpShuffleValueKind::I64 {
-                let mode = match shuffle.mode {
-                    WarpShuffleMode::Idx => "idx",
-                    WarpShuffleMode::Bfly => "bfly",
-                    WarpShuffleMode::Down => "down",
-                    WarpShuffleMode::Up => "up",
-                };
-                let asm = format!(
-                    "{{ .reg .b32 lo; .reg .b32 hi; mov.b64 {{lo, hi}}, $1; shfl.sync.{mode}.b32 lo, lo, $2, {}, $3; shfl.sync.{mode}.b32 hi, hi, $2, {}, $3; mov.b64 $0, {{lo, hi}}; }}",
-                    shuffle.clamp, shuffle.clamp
-                );
-                assert!(probe.contains(&format!(
-                    "define i64 @probe_{}(i32 %member_mask, i64 %value, i32 %lane) #0",
-                    record.id
-                )));
-                assert!(probe.contains(&format!(
-                    "call i64 asm sideeffect {asm:?}, \"=l,l,r,r\"(i64 %value, i32 %lane, i32 %member_mask) #0"
-                )));
-                assert_eq!(probe.matches("asm sideeffect").count(), 1);
-                assert_eq!(probe.matches("attributes #0 = { convergent }").count(), 1);
-                assert!(!probe.contains("declare i64 @llvm.nvvm.shfl"));
-                for suffix in ["rr", "ri", "ir", "ii"] {
-                    assert!(!probe.contains(&format!("@probe_{}_{suffix}", record.id)));
-                }
-            } else {
-                for suffix in ["rr", "ri", "ir", "ii"] {
-                    assert!(probe.contains(&format!("@probe_{}_{suffix}", record.id)));
-                }
-                assert!(probe.contains(&format!(", i32 {})", shuffle.clamp)));
-            }
-        }
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("pub unsafe fn i0050(_arg0: u32, _arg1: u32, _arg2: u32) -> u32"));
-        assert!(raw.contains("pub unsafe fn i0057(_arg0: u32, _arg1: f32, _arg2: u32) -> f32"));
-        for abi_id in ["i0058", "i0059", "i0060", "i0061"] {
-            assert!(raw.contains(&format!(
-                "pub unsafe fn {abi_id}(_arg0: u32, _arg1: u64, _arg2: u32) -> u64"
-            )));
-        }
-        assert!(raw.contains("If the computed source lane is in range"));
-        assert!(raw.contains(
-            "If PTX marks the computed source out of range, the calling lane's input is copied"
-        ));
-        assert!(raw.contains("two `b32` shuffles in one convergent block"));
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("## Warp-shuffle contracts"));
-        assert!(reference.contains("inserts clamp `31` during lowering"));
-        assert!(reference.contains("inserts clamp `0` during lowering"));
-        assert!(reference.contains("One convergent, side-effecting inline-PTX block splits `i64`"));
-        assert!(reference.contains("PTX-native source; no LLVM record"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs"
-        )));
-    }
-
-    #[test]
-    fn dot_product_rendering_preserves_stable_paths_and_low_selector() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(dot_products(&catalog).count(), 4);
-
-        let compatibility = render_compat_dotprod(&catalog, "test-hash");
-        for name in ["dp4a_s32", "dp4a_u32", "dp2a_s32", "dp2a_u32"] {
-            assert!(compatibility.contains(&format!("pub fn {name}(")));
-        }
-
-        let dialect = render_dialect_dotprod(&catalog, "test-hash");
-        assert!(dialect.contains("pub struct Dp4aS32Op"));
-        assert!(dialect.contains("pub struct Dp2aU32Op"));
-        assert!(dialect.contains("NOpdsInterface<3>"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::dotprod::dp2a_s32"));
-        assert!(importer.contains("let dot = Dp2aS32Op::build(ctx, a, b, c)"));
-        assert!(importer.contains("set_generated_intrinsic_marker(ctx, dot, \"v1:i0032\")"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("impl MirToLlvmConversion for Dp4aS32Op"));
-        assert!(lowering.contains("\"llvm_nvvm_idp2a_s_s\""));
-        assert!(lowering.contains("\"dp2a.lo.s32.s32 $0, $1, $2, $3;\""));
-        assert!(lowering.contains("\"dp2a.lo.s32.s32 $0, $1, $2, $3;\", true)"));
-
-        let low = dot_products(&catalog)
-            .find(|record| record.id == "dp2a_s32")
-            .unwrap();
-        let probe = render_probe(&catalog, low, "test-hash");
-        assert!(probe.contains("call i32 @llvm.nvvm.idp2a.s.s(i32 %a, i32 %b, i1 false, i32 %c)"));
-        assert!(!probe.contains("i1 true"));
-
-        let target = render_targets(&catalog, "test-hash");
-        assert!(target.contains("GeneratedImmediateBinding { argument_index: 2, value: 0 }"));
-        assert!(!target.contains("GeneratedImmediateBinding { argument_index: 2, value: -1 }"));
-    }
-
-    #[test]
-    fn sync_rendering_keeps_barrier_and_threadfence_contracts_explicit() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        let record = sync_intrinsics(&catalog).next().unwrap();
-        assert_eq!(sync_intrinsics(&catalog).count(), 4);
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("pub unsafe fn i0034() -> ()"));
-        assert!(raw.contains("Every active thread in the CTA must reach the same barrier"));
-
-        let dialect = render_dialect_sync(&catalog, "test-hash");
-        assert!(dialect.contains("pub struct Barrier0Op"));
-        assert!(dialect.contains("NOpdsInterface<0>, NResultsInterface<0>"));
-        assert!(dialect.contains("Barrier0Op::register(ctx)"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::thread::sync_threads"));
-        assert!(importer.contains("cuda_device::sync_threads"));
-        assert!(importer.contains("Barrier0Op::get_concrete_op_info()"));
-        assert!(importer.contains("set_generated_intrinsic_marker(ctx, barrier, \"v1:i0034\")"));
-        assert!(importer.contains("helpers::emit_goto(ctx, *target_idx, barrier"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("impl MirToLlvmConversion for Barrier0Op"));
-        assert!(lowering.contains("create_i32_const(ctx, rewriter, 0)"));
-        assert!(lowering.contains("\"llvm_nvvm_barrier_cta_sync_aligned_all\""));
-        assert!(lowering.contains("IntrinsicBackend::LlvmNvptx"));
-        assert!(lowering.contains("IntrinsicBackend::LibNvvm"));
-        assert!(lowering.contains("\"bar.sync 0;\", \"~{memory}\""));
-
-        let probe = render_probe(&catalog, record, "test-hash");
-        assert!(probe.contains("declare void @llvm.nvvm.barrier.cta.sync.aligned.all(i32)"));
-        assert!(probe.contains("call void @llvm.nvvm.barrier.cta.sync.aligned.all(i32 0)"));
-
-        let targets = render_targets(&catalog, "test-hash");
-        assert!(targets.contains("id: \"sync_threads\", abi_id: \"i0034\""));
-        assert!(targets.contains("source_record: \"BARRIER_CTA_SYNC_ALIGNED_ALL_i\""));
-        assert!(targets.contains(
-            "backend: GeneratedIntrinsicBackend::LlvmNvptx, requirement: GeneratedTargetRequirement { minimum_ptx: GeneratedPtxVersion::from_encoded(32), hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }"
-        ));
-        assert!(targets.contains(
-            "backend: GeneratedIntrinsicBackend::LibNvvm, requirement: GeneratedTargetRequirement { minimum_ptx: GeneratedPtxVersion::from_encoded(10), hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }"
-        ));
-        assert!(
-            !record
-                .selections
-                .iter()
-                .any(|selection| selection.source_record.ends_with("_r"))
-        );
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/sync.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/fence.rs")));
-
-        let compatibility = render_compat_fence(&catalog, "test-hash");
-        for (id, abi_id, op_type, op_name, llvm_identifier, ptx) in [
-            (
-                "threadfence_block",
-                "i0298",
-                "ThreadfenceBlockOp",
-                "nvvm.threadfence_block",
-                "llvm_nvvm_membar_cta",
-                "membar.cta;",
-            ),
-            (
-                "threadfence",
-                "i0299",
-                "ThreadfenceOp",
-                "nvvm.threadfence",
-                "llvm_nvvm_membar_gl",
-                "membar.gl;",
-            ),
-            (
-                "threadfence_system",
-                "i0300",
-                "ThreadfenceSystemOp",
-                "nvvm.threadfence_system",
-                "llvm_nvvm_membar_sys",
-                "membar.sys;",
-            ),
-        ] {
-            let record = sync_intrinsics(&catalog)
-                .find(|record| record.id == id)
-                .unwrap();
-            assert_eq!(record.rust.abi_id, abi_id);
-            assert!(compatibility.contains(&format!("pub fn {id}()")));
-            assert!(dialect.contains(&format!("pub struct {op_type}")));
-            assert!(dialect.contains(&format!("name = \"{op_name}\"")));
-            assert!(dialect.contains(&format!("{op_type}::register(ctx)")));
-            assert!(importer.contains(&format!("cuda_device::fence::{id}")));
-            assert!(importer.contains(&format!("cuda_device::{id}")));
-            assert!(importer.contains(&format!(
-                "set_generated_intrinsic_marker(ctx, barrier, \"v1:{abi_id}\")"
-            )));
-            assert!(lowering.contains(&format!("impl MirToLlvmConversion for {op_type}")));
-            assert!(lowering.contains(&format!("\"{llvm_identifier}\"")));
-
-            let probe = render_probe(&catalog, record, "test-hash");
-            assert!(probe.contains(&format!("declare void @{}()", llvm(record).symbol)));
-            assert!(probe.contains(&format!("call void @{}()", llvm(record).symbol)));
-            assert!(targets.contains(&format!("id: \"{id}\", abi_id: \"{abi_id}\"")));
-            assert!(targets.contains(&format!("asm: \"{ptx}\"")));
-        }
-        for ptx in ["membar.cta;", "membar.gl;", "membar.sys;"] {
-            assert!(!lowering.contains(&format!("\"{ptx}\"")));
-        }
-    }
-
-    #[test]
-    fn basic_mbarrier_rendering_preserves_existing_paths_shapes_and_routes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(mbarrier_basics(&catalog).count(), 4);
-
-        let compatibility = render_compat_mbarrier_basic(&catalog, "test-hash");
-        for signature in [
-            "pub unsafe fn mbarrier_init(bar: *mut Barrier, expected_count: u32)",
-            "pub unsafe fn mbarrier_arrive(bar: *const Barrier) -> u64",
-            "pub unsafe fn mbarrier_test_wait(bar: *const Barrier, token: u64) -> bool",
-            "pub unsafe fn mbarrier_inval(bar: *mut Barrier)",
-        ] {
-            assert!(compatibility.contains(signature));
-        }
-        assert!(compatibility.contains("eight-byte-aligned `Barrier` in shared memory"));
-        assert!(compatibility.contains("expected_count` must be in `1..=0xFFFFF`"));
-        let arrive = compatibility.find("pub unsafe fn mbarrier_arrive").unwrap();
-        assert!(compatibility[..arrive].ends_with("#[inline(never)]\n"));
-        assert!(!compatibility.contains("#[must_use]"));
-
-        let dialect_mod = render_dialect_mod(&catalog, "test-hash");
-        assert!(dialect_mod.contains("mod mbarrier_basic;"));
-        assert!(dialect_mod.contains("mbarrier_basic::register(ctx)"));
-        let dialect = render_dialect_mbarrier_basic(&catalog, "test-hash");
-        assert!(dialect.contains("address_space::GENERIC | address_space::SHARED"));
-        assert!(dialect.contains("mbarrier expected count must be u32"));
-        assert!(dialect.contains("mbarrier arrival token must be u64"));
-        assert!(dialect.contains("mbarrier test-wait requires a u64 token and i1 result"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        let lowering = render_lowering(&catalog, "test-hash");
-        let targets = render_targets(&catalog, "test-hash");
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        for record in mbarrier_basics(&catalog) {
-            assert!(dialect.contains(&format!("pub struct {}", record.dialect.op_type)));
-            assert!(dialect.contains(&format!("{}::register(ctx)", record.dialect.op_type)));
-            assert!(importer.contains(&record.rust.canonical_path));
-            assert!(importer.contains(&format!(
-                "set_generated_intrinsic_marker(ctx, mbarrier, {:?})",
-                intrinsic_marker(&catalog, record)
-            )));
-            assert!(lowering.contains(&format!(
-                "impl MirToLlvmConversion for {}",
-                record.dialect.op_type
-            )));
-            assert!(targets.contains(&format!("id: {:?}", record.id)));
-            assert!(raw.contains(&format!("pub unsafe fn {}", record.rust.abi_id)));
-
-            let probe = render_probe(&catalog, record, "test-hash");
-            assert!(
-                probe.contains("%barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)")
-            );
-            let mbarrier = record.mbarrier_basic.as_ref().unwrap();
-            let llvm_route = record
-                .backend_lowerings
-                .iter()
-                .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-                .unwrap();
-            let libnvvm_route = record
-                .backend_lowerings
-                .iter()
-                .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
-                .unwrap();
-            let expected_llvm_mechanism = match mbarrier.operation {
-                MbarrierBasicOperation::TestWait => BackendLoweringMechanism::InlinePtx,
-                _ => BackendLoweringMechanism::TypedNvvm,
-            };
-            assert_eq!(llvm_route.mechanism, expected_llvm_mechanism);
-            assert_eq!(libnvvm_route.mechanism, BackendLoweringMechanism::InlinePtx);
-            match mbarrier.operation {
-                MbarrierBasicOperation::Init => {
-                    assert!(
-                        dialect
-                            .contains("MbarrierInitSharedOp::build(ctx, barrier, expected_count)")
-                            || importer.contains(
-                                "MbarrierInitSharedOp::build(ctx, barrier, expected_count)"
-                            )
-                    );
-                    assert!(lowering.contains(
-                        "convert_init(ctx, rewriter, self.get_operation(), operands_info)"
-                    ));
-                    assert!(probe.contains(&format!(
-                        "declare void @{}(ptr addrspace(3), i32)",
-                        llvm(record).symbol
-                    )));
-                }
-                MbarrierBasicOperation::Arrive => {
-                    assert!(importer.contains("MbarrierArriveSharedOp::build(ctx, barrier)"));
-                    assert!(lowering.contains(
-                        "convert_arrive(ctx, rewriter, self.get_operation(), operands_info)"
-                    ));
-                    assert!(probe.contains(&format!(
-                        "declare i64 @{}(ptr addrspace(3))",
-                        llvm(record).symbol
-                    )));
-                }
-                MbarrierBasicOperation::TestWait => {
-                    assert!(
-                        importer.contains("MbarrierTestWaitSharedOp::build(ctx, barrier, token)")
-                    );
-                    assert!(lowering.contains(
-                        "convert_test_wait(ctx, rewriter, self.get_operation(), operands_info)"
-                    ));
-                    assert!(probe.contains("mbarrier.test_wait.shared.b64"));
-                    assert!(probe.contains("asm sideeffect"));
-                    assert!(probe.contains("attributes #0 = { convergent }"));
-                    assert!(!probe.contains(&format!("declare i1 @{}", llvm(record).symbol)));
-                }
-                MbarrierBasicOperation::Inval => {
-                    assert!(importer.contains("MbarrierInvalSharedOp::build(ctx, barrier)"));
-                    assert!(lowering.contains(
-                        "convert_inval(ctx, rewriter, self.get_operation(), operands_info)"
-                    ));
-                    assert!(probe.contains(&format!(
-                        "declare void @{}(ptr addrspace(3))",
-                        llvm(record).symbol
-                    )));
-                }
-            }
-        }
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("## Basic mbarrier contracts"));
-        assert!(reference.contains("inline PTX on both backends"));
-        assert!(reference.contains("typed NVVM intrinsic with LLVM-NVPTX"));
-        assert!(reference.contains("inline PTX with libNVVM"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/mbarrier_basic.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs"
-        )));
-    }
-
-    #[test]
-    fn movmatrix_rendering_owns_dialect_import_and_lowering() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let mut catalog = crate::resolve::resolve(&repo_root).unwrap();
-        let mut record = catalog
-            .intrinsics
-            .iter()
-            .find(|record| record.id == "packed_atomic_add_f16x2")
-            .unwrap()
-            .clone();
-        record.id = "movmatrix_trans_b16".into();
-        record.operation_key = "movmatrix.m8n8.trans.b16".into();
-        record.family = "movmatrix".into();
-        record.rust.abi_id = "i0305".into();
-        record.rust.module = "matrix".into();
-        record.rust.name = "movmatrix_trans_b16".into();
-        record.rust.arguments = vec!["u32".into()];
-        record.rust.result = "u32".into();
-        record.rust.safe = false;
-        record.rust.must_use = true;
-        record.rust.canonical_path = "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305".into();
-        record.rust.public_path = "cuda_intrinsics::matrix::movmatrix_trans_b16".into();
-        record.rust.compatibility_paths = vec!["cuda_device::wmma::movmatrix_trans_b16".into()];
-        record.dialect.op_type = "MovmatrixTransB16Op".into();
-        record.dialect.op_name = "nvvm.movmatrix_trans_b16".into();
-        record.dialect.operands = vec!["i32".into()];
-        record.dialect.results = vec!["i32".into()];
-        record.semantics.pure = false;
-        record.semantics.memory = "inaccessible_read_write".into();
-        record.semantics.convergent = true;
-        record.semantics.execution_scope = "warp".into();
-        record.packed_atomic = None;
-        record.movmatrix = Some(crate::model::Movmatrix {
-            participation:
-                crate::model::MovmatrixParticipation::AllWarpLanesSameInstructionNoExitedLanes,
-            adapter: crate::model::MovmatrixAdapter::PackedB16x2U32ToPackedB16x2U32,
-            runtime_validation: RuntimeValidation::Unexecuted,
-        });
-        record.lowering = "generated_movmatrix_inline_ptx".into();
-        record.expected_ptx = crate::ptx::InstructionPattern::new(
-            "movmatrix",
-            &["sync", "aligned", "m8n8", "trans", "b16"],
-            vec![
-                crate::ptx::OperandPattern::Register,
-                crate::ptx::OperandPattern::Register,
-            ],
-        );
-        record.summary = "Transposes one packed b16 matrix fragment across a warp.".into();
-        catalog.intrinsics.push(record);
-
-        validate_renderable(&catalog).unwrap();
-        let dialect_mod = render_dialect_mod(&catalog, "test-hash");
-        assert!(dialect_mod.contains("mod movmatrix;"));
-        assert!(dialect_mod.contains("movmatrix::register(ctx);"));
-
-        let dialect = render_dialect_movmatrix(&catalog, "test-hash");
-        assert!(dialect.contains("pub struct MovmatrixTransB16Op;"));
-        assert!(dialect.contains("name = \"nvvm.movmatrix_trans_b16\""));
-        assert!(dialect.contains("MovmatrixTransB16Op::register(ctx);"));
-
-        let compatibility = render_compat_movmatrix(&catalog, "test-hash");
-        assert!(compatibility.contains("pub unsafe fn movmatrix_trans_b16(value: u32) -> u32"));
-        assert!(compatibility.contains("All 32 warp lanes must execute the same call"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::wmma::movmatrix_trans_b16"));
-        assert!(importer.contains("MovmatrixTransB16Op::build(ctx, arg0)"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("impl MirToLlvmConversion for MovmatrixTransB16Op"));
-        assert!(lowering.contains("movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;"));
-        assert!(lowering.contains("\"=r,r\""));
-        assert!(lowering.contains("inline_asm_convergent"));
-
-        let probe_record = movmatrix(&catalog).next().unwrap();
-        let probe = render_probe(&catalog, probe_record, "test-hash");
-        assert!(probe.contains("call i32 asm \"movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;\""));
-        assert!(probe.contains("attributes #0 = { convergent }"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/movmatrix.rs"
-        )));
-    }
-
-    #[test]
-    fn extended_mbarrier_rendering_preserves_all_manual_contracts() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        let records = mbarrier_extended(&catalog).collect::<Vec<_>>();
-        assert_eq!(records.len(), 11);
-
-        let compatibility = render_compat_mbarrier_extended(&catalog, "test-hash");
-        for signature in [
-            "pub unsafe fn mbarrier_arrive_expect_tx(bar: *const Barrier, _tx_count: u32, bytes: u32) -> u64",
-            "pub unsafe fn mbarrier_arrive_expect_tx_cluster(bar: *const Barrier, _tx_count: u32, bytes: u32) -> u64",
-            "pub unsafe fn mbarrier_arrive_cluster(remote_bar_addr: u64)",
-            "pub unsafe fn mbarrier_try_wait(bar: *const Barrier, token: u64) -> bool",
-            "pub unsafe fn mbarrier_try_wait_parity(bar: *const Barrier, parity: u32) -> bool",
-            "pub unsafe fn mbarrier_try_wait_parity_cluster(bar: *const Barrier, parity: u32) -> bool",
-            "pub unsafe fn fence_proxy_async_shared_cta()",
-            "pub unsafe fn fence_mbarrier_init_release_cluster()",
-            "pub unsafe fn fence_proxy_async_generic_release_shared_cta_cluster()",
-            "pub unsafe fn fence_proxy_async_generic_acquire_shared_cluster_cluster()",
-            "pub unsafe fn nanosleep(ns: u32)",
-        ] {
-            assert!(compatibility.contains(signature), "missing {signature}");
-        }
-        assert!(!compatibility.contains("#[must_use]"));
-
-        let dialect_mod = render_dialect_mod(&catalog, "test-hash");
-        assert!(dialect_mod.contains("mod mbarrier_extended;"));
-        assert!(dialect_mod.contains("pub use mbarrier_extended::*;"));
-        assert!(dialect_mod.contains("mbarrier_extended::register(ctx);"));
-
-        let dialect = render_dialect_mbarrier_extended(&catalog, "test-hash");
-        let importer = render_importer(&catalog, "test-hash");
-        let lowering = render_lowering(&catalog, "test-hash");
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        for record in &records {
-            assert!(dialect.contains(&format!("pub struct {}", record.dialect.op_type)));
-            assert!(dialect.contains(&format!("{}::register(ctx);", record.dialect.op_type)));
-            assert!(importer.contains(&record.rust.canonical_path));
-            assert!(importer.contains(&record.rust.compatibility_paths[0]));
-            assert!(lowering.contains(&format!(
-                "impl MirToLlvmConversion for {}",
-                record.dialect.op_type
-            )));
-            assert!(raw.contains(&format!("pub unsafe fn {}", record.rust.abi_id)));
-            for route in &record.backend_lowerings {
-                assert_eq!(route.mechanism, BackendLoweringMechanism::InlinePtx);
-            }
-            let (template, constraints) = crate::resolve::mbarrier_extended_inline_recipe(
-                record.mbarrier_extended.as_ref().unwrap().operation,
-            );
-            assert!(lowering.contains(&format!("{template:?}, {constraints:?}")));
-            let probe = render_probe(&catalog, record, "test-hash");
-            assert!(probe.contains("asm sideeffect"));
-            assert!(probe.contains(template));
-            assert!(probe.contains("~{memory}"));
-            assert!(probe.contains("attributes #0 = { convergent }"));
-        }
-
-        assert!(dialect.contains("address_space::GENERIC | address_space::SHARED"));
-        assert!(dialect.contains("mbarrier arrival requires u32 bytes and a u64 token"));
-        assert!(dialect.contains("mbarrier wait requires a u64 token and i1 result"));
-        assert!(dialect.contains("mbarrier wait requires u32 parity and i1 result"));
-        assert!(dialect.contains("remote mbarrier address must be u64"));
-        assert!(dialect.contains("nanosleep duration must be u32"));
-
-        assert!(importer.contains("MbarrierArriveExpectTxSharedOp::build(ctx, barrier, bytes)"));
-        assert!(importer.contains("MbarrierArriveExpectTxClusterOp::build(ctx, barrier, bytes)"));
-        assert!(
-            !importer
-                .contains("MbarrierArriveExpectTxSharedOp::build(ctx, barrier, tx_count, bytes)")
-        );
-        assert!(importer.contains("MbarrierArriveClusterOp::build(ctx, address)"));
-        assert!(importer.contains("MbarrierTryWaitSharedOp::build(ctx, barrier, token)"));
-        assert!(importer.contains("MbarrierTryWaitParitySharedOp::build(ctx, barrier, parity)"));
-        assert!(importer.contains("MbarrierTryWaitParityClusterOp::build(ctx, barrier, parity)"));
-        assert!(importer.contains("FenceProxyAsyncSharedCtaOp::build(ctx)"));
-        assert!(importer.contains("FenceMbarrierInitReleaseClusterOp::build(ctx)"));
-        assert!(importer.contains("NanosleepOp::build(ctx, ns)"));
-
-        assert!(lowering.contains("cast_to_shared_addrspace"));
-        assert!(lowering.contains("trunc_to_i1"));
-        assert!(lowering.contains("DefiningEntity::Op(result_op)"));
-        assert!(lowering.contains("rewriter.erase_operation(ctx, op)"));
-        assert!(lowering.contains("mbarrier.arrive.release.cluster.shared::cluster.b64 _, [$0];"));
-        let remote = records
-            .iter()
-            .find(|record| record.id == "mbarrier_arrive_cluster")
-            .unwrap();
-        assert!(remote.llvm.is_none());
-        assert!(matches!(remote.source, IntrinsicSource::PtxNative { .. }));
-        assert!(!render_probe(&catalog, remote, "test-hash").contains("declare"));
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("## Extended mbarrier contracts"));
-        assert!(reference.contains("LLVM 22 TableGen"));
-        assert!(reference.contains("PTX-native raw-address contract"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/mbarrier_extended.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs"
-        )));
-    }
-
-    #[test]
-    fn register_mma_rendering_preserves_apis_order_convergence_and_variants() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(catalog.intrinsics.len(), 1016);
-        let records: Vec<_> = register_mmas(&catalog).collect();
-        assert_eq!(records.len(), 154);
-        let generated_records = records
-            .iter()
-            .copied()
-            .filter(|record| {
-                record.register_mma.as_ref().unwrap().compatibility_source
-                    == RegisterMmaCompatibilitySource::GeneratedStub
-            })
-            .collect::<Vec<_>>();
-        let existing_records = records
-            .iter()
-            .copied()
-            .filter(|record| {
-                record.register_mma.as_ref().unwrap().compatibility_source
-                    == RegisterMmaCompatibilitySource::ExistingStub
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(generated_records.len(), 149);
-        assert_eq!(existing_records.len(), 5);
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        for record in &records {
-            assert!(raw.contains(&format!("pub unsafe fn {}(", record.rust.abi_id)));
-        }
-        assert!(raw.contains("no lane may have exited"));
-        assert!(raw.contains("Signed accumulator overflow wraps"));
-        assert!(raw.contains("Signed accumulator overflow clamps"));
-
-        let compatibility = render_compat_register_mma(&catalog, "test-hash");
-        assert_eq!(compatibility.matches("pub unsafe fn ").count(), 149);
-        for record in generated_records {
-            let argument_names: &[&str] = if record.register_mma.as_ref().unwrap().adapter
-                == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
-            {
-                &[
-                    "c",
-                    "a",
-                    "b",
-                    "scale_a",
-                    "byte_id_a",
-                    "thread_id_a",
-                    "scale_b",
-                    "byte_id_b",
-                    "thread_id_b",
-                ]
-            } else {
-                &["c", "a", "b"]
-            };
-            let arguments = argument_names
-                .iter()
-                .zip(&record.rust.arguments)
-                .map(|(name, ty)| format!("{name}: {ty}"))
-                .collect::<Vec<_>>()
-                .join(", ");
-            assert!(compatibility.contains(&format!(
-                "pub unsafe fn {}({arguments}) -> {} {{",
-                record.rust.name, record.rust.result
-            )));
-        }
-        for record in existing_records {
-            assert!(!compatibility.contains(&format!("pub unsafe fn {}(", record.rust.name)));
-        }
-
-        let dialect = render_dialect_register_mma(&catalog, "test-hash");
-        assert_eq!(dialect.matches("pub struct RegisterMmaOp").count(), 1);
-        assert!(dialect.contains("let recipe: (&[MmaCarrier], &[MmaCarrier])"));
-        assert!(dialect.contains("RegisterMmaShapeAttr::M8n8k4"));
-        assert!(dialect.contains("RegisterMmaShapeAttr::M8n8k16"));
-        assert!(dialect.contains("RegisterMmaShapeAttr::M8n8k32"));
-        assert!(dialect.contains("RegisterMmaShapeAttr::M8n8k128"));
-        assert!(dialect.contains("RegisterMmaShapeAttr::M16n8k4"));
-        assert!(dialect.contains("RegisterMmaShapeAttr::M16n8k32"));
-        assert!(dialect.contains("RegisterMmaShapeAttr::M16n8k64"));
-        assert!(dialect.contains("RegisterMmaShapeAttr::M16n8k128"));
-        assert!(dialect.contains("RegisterMmaShapeAttr::M16n8k256"));
-        assert!(dialect.contains("RegisterMmaOperationAttr::Multiply"));
-        assert!(dialect.contains("RegisterMmaOperationAttr::AndPopc"));
-        assert!(dialect.contains("RegisterMmaOperationAttr::XorPopc"));
-        assert!(dialect.contains("pub enum RegisterMmaKindAttr { Standard, F8f6f4, Mxf8f6f4 }"));
-        assert!(dialect.contains("kind_or_inferred"));
-        assert!(dialect.contains("RegisterMmaAccumulatorAttr::F16"));
-        assert!(dialect.contains("operation_or_multiply"));
-        assert!(dialect.contains("MmaCarrier::I32 | MmaCarrier::U16 | MmaCarrier::U32"));
-        assert!(dialect.contains("if matches!(carrier, MmaCarrier::U16)"));
-        assert!(dialect.contains("RegisterMmaElementAttr::B1"));
-        assert!(dialect.contains("RegisterMmaElementAttr::E2m1"));
-        assert!(dialect.contains("RegisterMmaElementAttr::E5m2"));
-        assert!(dialect.contains("RegisterMmaElementAttr::S4"));
-        assert!(dialect.contains("RegisterMmaElementAttr::U4"));
-        assert!(dialect.contains("RegisterMmaElementAttr::U8"));
-        assert!(dialect.contains("RegisterMmaOverflowAttr::Wrapping"));
-        assert!(dialect.contains("RegisterMmaOverflowAttr::Satfinite"));
-        assert!(dialect.contains(
-            "&[MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]"
-        ));
-        for (op_type, op_name) in [
-            ("MmaM16N8K16F32Bf16Op", "nvvm.mma_m16n8k16_f32_bf16"),
-            ("MmaM16N8K16F32F16Op", "nvvm.mma_m16n8k16_f32_f16"),
-            ("MmaM16N8K8F32Tf32Op", "nvvm.mma_m16n8k8_f32_tf32"),
-            ("MmaM16N8K32S32S8Op", "nvvm.mma_m16n8k32_s32_s8"),
-            ("MmaM8N8K4F64Op", "nvvm.mma_m8n8k4_f64"),
-        ] {
-            assert!(dialect.contains(&format!("pub struct {op_type};")));
-            assert!(dialect.contains(&format!("name = {op_name:?}")));
-            assert!(dialect.contains(&format!("{op_type}::register(ctx);")));
-        }
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("enum GeneratedMmaImportAdapter"));
-        assert!(importer.contains("C2U32A4U32B2U32ToD2U32"));
-        assert!(importer.contains("C2U32A2U32B1U32ToD2U32"));
-        assert!(importer.contains("C4F32A2U32B1U32ToD4F32"));
-        assert!(importer.contains("C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32"));
-        assert!(
-            importer.contains("ctx, b_value, b_ty, b_count, block_ptr, last_after_b, loc.clone()")
-        );
-        assert!(importer.contains("C4I32A2U32B1U32ToD4I32"));
-        assert!(importer.contains("C2I32A1U32B1U32ToD2I32"));
-        assert!(importer.contains("(i32_ty, 2, u32_ty, 1, false, u32_ty, 1, false, i32_ty, 2)"));
-        assert!(importer.contains("(i32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, i32_ty, 4)"));
-        assert!(importer.contains("(u32_ty, 2, u32_ty, 4, true, u32_ty, 2, true, u32_ty, 2)"));
-        assert!(importer.contains("import_generated_mma_operands"));
-        assert!(importer.contains("bundle_generated_mma_results"));
-        assert!(importer.contains("set_attr_nvvm_register_mma_operation"));
-        assert!(importer.contains("set_attr_nvvm_register_mma_kind"));
-        for record in &records {
-            assert!(importer.contains(&record.rust.canonical_path));
-            assert!(importer.contains(&record.rust.compatibility_paths[0]));
-            assert!(importer.contains(&format!(
-                "set_generated_intrinsic_marker(ctx, mma, {:?})",
-                intrinsic_marker(&catalog, record)
-            )));
-        }
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert_eq!(
-            lowering
-                .matches("impl MirToLlvmConversion for RegisterMmaOp")
-                .count(),
-            1
-        );
-        assert!(lowering.contains("convert_generated_register_mma"));
-        assert!(lowering.contains("operation_or_multiply"));
-        assert!(lowering.contains("kind_or_inferred"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e4m3.f16"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k4.row.col.f32.tf32.tf32.f32"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e5m2.f32"));
-        assert!(lowering.contains("=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r"));
-        assert!(lowering.contains("=d,=d,d,d,d,d"));
-        assert!(lowering.contains("=r,=r,=r,=r,r,r,r,r,r,r,r"));
-        assert!(lowering.contains("=r,=r,r,r,r,r"));
-        assert!(lowering.contains("=r,=r,r,r,r,r,r,r,r,r"));
-        assert!(lowering.contains("mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32"));
-        assert!(lowering.contains("mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc"));
-        assert!(lowering.contains("mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc"));
-        assert!(lowering.contains("mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc"));
-        for op_type in [
-            "MmaM16N8K16F32Bf16Op",
-            "MmaM16N8K16F32F16Op",
-            "MmaM16N8K8F32Tf32Op",
-            "MmaM16N8K32S32S8Op",
-            "MmaM8N8K4F64Op",
-        ] {
-            assert_eq!(
-                lowering
-                    .matches(&format!("impl MirToLlvmConversion for {op_type}"))
-                    .count(),
-                1
-            );
-        }
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::I32, 4, 7, "mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};", "=r,=r,=r,=r,r,r,r,r,r,r,r")"#
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::I32, 4, 10, "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};", "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r")"#
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::I32, 2, 4, "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc {$0, $1}, {$4}, {$5}, {$2, $3};", "=r,=r,r,r,r,r")"#
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::I32, 4, 7, "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};", "=r,=r,=r,=r,r,r,r,r,r,r,r")"#
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::I32, 4, 10, "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};", "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r")"#
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::F32, 4, 10, "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r")"#
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::F32, 4, 10, "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r")"#
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::I32, 2, 8, "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};", "=r,=r,r,r,r,r,r,r,r,r")"#
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::I32, 2, 8, "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};", "=r,=r,r,r,r,r,r,r,r,r")"#
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::F32, 4, 16, "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h")"#
-        ));
-
-        let targets = render_targets(&catalog, "test-hash");
-        assert!(targets.contains("GeneratedIntrinsicVariant::RegisterMma"));
-        assert!(targets.contains("GeneratedRegisterMmaShape::M8n8k4"));
-        assert!(targets.contains("GeneratedRegisterMmaShape::M16n8k4"));
-        assert!(targets.contains(
-            "pub enum GeneratedRegisterMmaShape { M8n8k4, M8n8k16, M8n8k32, M8n8k128, M16n8k4, M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128, M16n8k256 }"
-        ));
-        assert!(targets.contains(
-            "GeneratedRegisterMmaShape::M8n8k16 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k16)"
-        ));
-        assert!(targets.contains(
-            "GeneratedRegisterMmaShape::M8n8k32 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k32)"
-        ));
-        assert!(targets.contains(
-            "GeneratedRegisterMmaShape::M8n8k128 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k128)"
-        ));
-        assert!(targets.contains("GeneratedRegisterMmaShape::M16n8k32"));
-        assert!(targets.contains(
-            "GeneratedRegisterMmaShape::M16n8k64 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k64)"
-        ));
-        assert!(targets.contains(
-            "GeneratedRegisterMmaShape::M16n8k128 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k128)"
-        ));
-        assert!(targets.contains(
-            "GeneratedRegisterMmaShape::M16n8k256 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k256)"
-        ));
-        assert!(targets.contains("GeneratedRegisterMmaOperation::Multiply"));
-        assert!(targets.contains("GeneratedRegisterMmaOperation::AndPopc"));
-        assert!(targets.contains("GeneratedRegisterMmaOperation::XorPopc"));
-        assert!(
-            targets.contains("pub enum GeneratedRegisterMmaKind { Standard, F8f6f4, Mxf8f6f4 }")
-        );
-        assert!(targets.contains("kind: GeneratedRegisterMmaKind::Standard"));
-        assert!(targets.contains("kind: GeneratedRegisterMmaKind::F8f6f4"));
-        assert!(targets.contains("kind: GeneratedRegisterMmaKind::Mxf8f6f4"));
-        assert!(targets.contains("kind_or_inferred"));
-        assert!(targets.contains("RegisterMmaKindAttr::Standard"));
-        assert!(targets.contains("RegisterMmaKindAttr::F8f6f4"));
-        assert!(targets.contains("RegisterMmaKindAttr::Mxf8f6f4"));
-        assert!(targets.contains("GeneratedRegisterMmaAccumulator::F16"));
-        assert!(targets.contains("operation: GeneratedRegisterMmaOperation::AndPopc"));
-        assert!(targets.contains("operation: GeneratedRegisterMmaOperation::XorPopc"));
-        assert!(targets.contains("operation: mma_operation"));
-        assert!(targets.contains("operation_or_multiply"));
-        assert!(targets.contains("GeneratedRegisterMmaElement::B1"));
-        assert!(targets.contains("GeneratedRegisterMmaElement::E2m1"));
-        assert!(targets.contains("GeneratedRegisterMmaElement::E5m2"));
-        assert!(targets.contains("GeneratedRegisterMmaElement::S4"));
-        assert!(targets.contains("GeneratedRegisterMmaElement::U4"));
-        assert!(targets.contains("GeneratedRegisterMmaElement::U8"));
-        assert!(targets.contains(
-            "a_element: GeneratedRegisterMmaElement::S4, b_element: GeneratedRegisterMmaElement::U4"
-        ));
-        assert!(targets.contains(
-            "a_element: GeneratedRegisterMmaElement::U4, b_element: GeneratedRegisterMmaElement::S4"
-        ));
-        assert!(targets.contains(
-            "a_element: GeneratedRegisterMmaElement::S8, b_element: GeneratedRegisterMmaElement::U8"
-        ));
-        assert!(targets.contains(
-            "a_element: GeneratedRegisterMmaElement::U8, b_element: GeneratedRegisterMmaElement::S8"
-        ));
-        assert!(targets.contains("overflow: GeneratedRegisterMmaOverflow::Satfinite"));
-        assert!(targets.contains("get_attr_nvvm_register_mma_overflow"));
-        assert!(targets.contains("minimum_ptx: GeneratedPtxVersion::from_encoded(87)"));
-        assert!(targets.contains("minimum_ptx: GeneratedPtxVersion::from_encoded(84)"));
-        assert!(targets.contains("GeneratedHardwareAlternative::ExactArchitecture(120)"));
-        assert!(targets.contains("GeneratedHardwareAlternative::FamilyTarget(121)"));
-
-        let first_dense = records
-            .iter()
-            .find(|record| record.id == "mma_m16n8k32_f32_e2m1_e2m1")
-            .unwrap();
-        let last_dense = records
-            .iter()
-            .find(|record| record.id == "mma_m16n8k32_f32_e5m2_e5m2")
-            .unwrap();
-        assert_eq!(first_dense.rust.abi_id, "i0454");
-        assert_eq!(last_dense.rust.abi_id, "i0478");
-        assert_eq!(
-            register_mma_constraints(first_dense),
-            "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r"
-        );
-        let first_dense_f16 = records
-            .iter()
-            .find(|record| record.id == "mma_m16n8k32_f16_e2m1_e2m1")
-            .unwrap();
-        let last_dense_f16 = records
-            .iter()
-            .find(|record| record.id == "mma_m16n8k32_f16_e5m2_e5m2")
-            .unwrap();
-        assert_eq!(first_dense_f16.rust.abi_id, "i0479");
-        assert_eq!(last_dense_f16.rust.abi_id, "i0503");
-        assert_eq!(
-            register_mma_constraints(first_dense_f16),
-            "=r,=r,r,r,r,r,r,r,r,r"
-        );
-        assert!(
-            render_probe(&catalog, first_dense_f16, "test-hash").contains("define { i32, i32 }")
-        );
-
-        let first_mxf8f6f4 = records
-            .iter()
-            .find(|record| record.id == "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1")
-            .unwrap();
-        let last_mxf8f6f4 = records
-            .iter()
-            .find(|record| record.id == "mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2")
-            .unwrap();
-        assert_eq!(first_mxf8f6f4.rust.abi_id, "i0858");
-        assert_eq!(last_mxf8f6f4.rust.abi_id, "i0882");
-        assert_eq!(
-            register_mma_constraints(first_mxf8f6f4),
-            "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h"
-        );
-        assert!(
-            render_probe(&catalog, first_mxf8f6f4, "test-hash")
-                .contains("kind::mxf8f6f4.block_scale")
-        );
-        let first_mxf8f6f4_compatibility = format!("pub unsafe fn {}(", first_mxf8f6f4.rust.name);
-        let first_mxf8f6f4_compatibility = compatibility
-            .find(&first_mxf8f6f4_compatibility)
-            .expect("generated MXF8F6F4 compatibility wrapper");
-        assert!(
-            compatibility[..first_mxf8f6f4_compatibility]
-                .ends_with("#[allow(clippy::too_many_arguments)]\n#[must_use]\n#[inline(never)]\n")
-        );
-
-        for record in &records {
-            let probe = render_probe(&catalog, record, "test-hash");
-            assert!(probe.contains("asm sideeffect"));
-            assert!(probe.contains("attributes #0 = { convergent }"));
-            assert!(probe.contains(&register_mma_template(record)));
-            assert!(probe.contains(&register_mma_constraints(record)));
-        }
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("## Register-MMA contracts"));
-        assert!(reference.contains("performs XOR, population count, and accumulate"));
-        assert!(reference.contains("performs AND, population count, and accumulate"));
-        assert!(reference.contains("runtime validation is not executed on a GPU"));
-        for record in &records {
-            assert!(reference.contains(&format!("- `{}`: runtime `unexecuted`", record.id)));
-        }
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/register_mma.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/register_mma.rs"
-        )));
-    }
-
-    #[test]
-    fn register_mma_kind_is_explicit_and_legacy_ir_stays_compatible() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let mut catalog: CatalogFile =
-            read_json(&repo_root.join("intrinsics/catalog.json")).unwrap();
-        let old = catalog
-            .intrinsics
-            .iter()
-            .find(|record| record.id == "mma_m16n8k32_f16_e4m3_e4m3")
-            .unwrap()
-            .clone();
-        assert_eq!(old.register_mma.as_ref().unwrap().kind, None);
-        assert_eq!(
-            register_mma_attr_variants(&old).2,
-            "RegisterMmaKindAttr::F8f6f4"
-        );
-        assert!(
-            generated_intrinsic_variant(&old).contains("kind: GeneratedRegisterMmaKind::F8f6f4")
-        );
-
-        let mut standard = old.clone();
-        standard.id = "mma_m16n8k32_fp8_f16_e4m3_e4m3".into();
-        standard.operation_key =
-            "matrix.mma.m16n8k32.row.col.standard_fp8.f16.e4m3.e4m3.f16".into();
-        standard.rust.abi_id = "i9999".into();
-        standard.rust.name = standard.id.clone();
-        standard.rust.canonical_path = format!("cuda_intrinsics::matrix::{}", standard.id);
-        standard.rust.public_path = standard.rust.canonical_path.clone();
-        standard.rust.compatibility_paths = vec![format!("cuda_device::wmma::{}", standard.id)];
-        standard.llvm.as_mut().unwrap().symbol =
-            "llvm.nvvm.mma.m16n8k32.row.col.f16.e4m3.e4m3.f16".into();
-        standard.register_mma.as_mut().unwrap().kind = Some(RegisterMmaKind::Standard);
-        standard
-            .expected_ptx
-            .modifiers
-            .retain(|modifier| modifier != "kind::f8f6f4");
-        assert_eq!(
-            register_mma_attr_variants(&standard).2,
-            "RegisterMmaKindAttr::Standard"
-        );
-        assert!(
-            generated_intrinsic_variant(&standard)
-                .contains("kind: GeneratedRegisterMmaKind::Standard")
-        );
-        catalog.intrinsics.push(standard);
-
-        let dialect = render_dialect_register_mma(&catalog, "test-hash");
-        assert!(dialect.contains("pub fn kind_or_inferred"));
-        assert!(
-            dialect
-                .contains("let old_f8f6f4 = self.get_attr_nvvm_register_mma_shape(ctx).as_deref()")
-        );
-        assert!(dialect.contains("== Some(&RegisterMmaShapeAttr::M16n8k32)"));
-        assert!(
-            dialect.contains(
-                "&& low_format(self.get_attr_nvvm_register_mma_a_element(ctx).as_deref())"
-            )
-        );
-        assert!(
-            dialect.contains(
-                "&& low_format(self.get_attr_nvvm_register_mma_b_element(ctx).as_deref())"
-            )
-        );
-        assert!(dialect.contains("RegisterMmaKindAttr::F8f6f4"));
-        assert!(dialect.contains("RegisterMmaKindAttr::Standard"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(
-            importer.contains("set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4)")
-        );
-        assert!(
-            importer
-                .contains("set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard)")
-        );
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("let kind = self.kind_or_inferred(ctx)"));
-        assert!(lowering.contains("kind::f8f6f4.f16.e4m3.e4m3.f16"));
-        assert!(lowering.contains("row.col.f16.e4m3.e4m3.f16"));
-
-        let targets = render_targets(&catalog, "test-hash");
-        assert!(targets.contains("kind: GeneratedRegisterMmaKind::F8f6f4"));
-        assert!(targets.contains("kind: GeneratedRegisterMmaKind::Standard"));
-        assert!(targets.contains(
-            "GeneratedRegisterMmaKind::Standard => op.kind_or_inferred(ctx) == RegisterMmaKindAttr::Standard"
-        ));
-        assert!(targets.contains(
-            "GeneratedRegisterMmaKind::F8f6f4 => op.kind_or_inferred(ctx) == RegisterMmaKindAttr::F8f6f4"
-        ));
-        assert!(targets.contains("kind_matches && accumulator_matches"));
-    }
-
-    #[test]
-    fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        let records = sparse_mmas(&catalog).collect::<Vec<_>>();
-        let k32 = records
-            .iter()
-            .filter(|record| record.sparse_mma.as_ref().unwrap().shape == SparseMmaShape::M16n8k32)
-            .count();
-        let k64 = records
-            .iter()
-            .filter(|record| record.sparse_mma.as_ref().unwrap().shape == SparseMmaShape::M16n8k64)
-            .count();
-        let k128 = records
-            .iter()
-            .filter(|record| record.sparse_mma.as_ref().unwrap().shape == SparseMmaShape::M16n8k128)
-            .count();
-        assert_eq!((records.len(), k32, k64, k128), (114, 16, 82, 16));
-        let standard_k64 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_m16n8k64_s32_s8")
-            .unwrap();
-        assert_eq!(
-            standard_k64.sparse_mma.as_ref().unwrap().adapter,
-            SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32
-        );
-        assert_eq!(
-            standard_k64.sparse_mma.as_ref().unwrap().llvm_adapter,
-            crate::model::SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32
-        );
-        assert_eq!(
-            sparse_mma_template(standard_k64),
-            "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;"
-        );
-        assert_eq!(
-            sparse_mma_constraints(standard_k64),
-            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n"
-        );
-        let standard_int4_k64 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_m16n8k64_s32_s4")
-            .unwrap();
-        assert_eq!(
-            sparse_mma_template(standard_int4_k64),
-            "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;"
-        );
-        assert_eq!(
-            sparse_mma_constraints(standard_int4_k64),
-            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n"
-        );
-        let ordered_int4_k64 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k64_s32_s4")
-            .unwrap();
-        assert_eq!(
-            ordered_int4_k64.sparse_mma.as_ref().unwrap().adapter,
-            SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32
-        );
-        assert_eq!(
-            ordered_int4_k64.sparse_mma.as_ref().unwrap().llvm_adapter,
-            crate::model::SparseMmaLlvmAdapter::A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32
-        );
-        assert_eq!(
-            sparse_mma_template(ordered_int4_k64),
-            "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;"
-        );
-        assert_eq!(
-            sparse_mma_constraints(ordered_int4_k64),
-            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n"
-        );
-        let ordered_int4_k128 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k128_s32_s4")
-            .unwrap();
-        assert_eq!(
-            ordered_int4_k128.sparse_mma.as_ref().unwrap().adapter,
-            SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32
-        );
-        assert_eq!(
-            ordered_int4_k128.sparse_mma.as_ref().unwrap().llvm_adapter,
-            crate::model::SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32
-        );
-        assert_eq!(
-            sparse_mma_template(ordered_int4_k128),
-            "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;"
-        );
-        assert_eq!(
-            sparse_mma_constraints(ordered_int4_k128),
-            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n"
-        );
-        let standard_int4_k128 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_m16n8k128_s32_s4")
-            .unwrap();
-        assert_eq!(
-            sparse_mma_template(standard_int4_k128),
-            "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;"
-        );
-        assert_eq!(
-            sparse_mma_constraints(standard_int4_k128),
-            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n"
-        );
-        let ordered_f8f6f4 = records
-            .iter()
-            .copied()
-            .find(|record| {
-                record.id == "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
-            })
-            .unwrap();
-        assert_eq!(
-            ordered_f8f6f4.sparse_mma.as_ref().unwrap().adapter,
-            SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32
-        );
-        assert_eq!(
-            sparse_mma_template(ordered_f8f6f4),
-            "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;"
-        );
-        assert_eq!(
-            sparse_mma_constraints(ordered_f8f6f4),
-            "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"
-        );
-        assert_eq!(
-            sparse_mma_carriers(ordered_f8f6f4),
-            (
-                "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]".into(),
-                "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32]".into(),
-            )
-        );
-        let ordered_f8f6f4_f16 = records
-            .iter()
-            .copied()
-            .find(|record| {
-                record.id == "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
-            })
-            .unwrap();
-        assert_eq!(
-            ordered_f8f6f4_f16.sparse_mma.as_ref().unwrap().adapter,
-            SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32
-        );
-        assert_eq!(sparse_mma_fragment_counts(ordered_f8f6f4_f16), (2, 4, 4, 2));
-        assert_eq!(
-            sparse_mma_template(ordered_f8f6f4_f16),
-            "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;"
-        );
-        assert_eq!(
-            sparse_mma_constraints(ordered_f8f6f4_f16),
-            "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n"
-        );
-        assert_eq!(
-            sparse_mma_carriers(ordered_f8f6f4_f16),
-            (
-                "&[MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]".into(),
-                "&[MmaCarrier::U32, MmaCarrier::U32]".into(),
-            )
-        );
-        assert_eq!(sparse_mma_selector_values(ordered_f8f6f4_f16), &[0]);
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("must be the compile-time constant `0` or `1`"));
-        assert!(raw.contains("must be the compile-time constant `0`"));
-        for record in &records {
-            let (c_count, a_count, b_count, d_count) = sparse_mma_fragment_counts(record);
-            let scalar = match record.sparse_mma.as_ref().unwrap().accumulator {
-                SparseMmaAccumulator::F16 => "u32",
-                SparseMmaAccumulator::F32 => "f32",
-                SparseMmaAccumulator::S32 => "i32",
-            };
-            assert!(raw.contains(&format!(
-                "pub unsafe fn {}(_arg0: [{scalar}; {c_count}], _arg1: [u32; {a_count}], _arg2: [u32; {b_count}], _arg3: u32, _arg4: u32) -> [{scalar}; {d_count}]",
-                record.rust.abi_id,
-            )));
-        }
-
-        let compatibility = render_compat_sparse_mma(&catalog, "test-hash");
-        assert_eq!(compatibility.matches("pub unsafe fn ").count(), 114);
-        assert!(
-            compatibility
-                .contains("c: [i32; 4], a: [u32; 2], b: [u32; 2], metadata: u32, selector: u32")
-        );
-        assert!(
-            compatibility
-                .contains("c: [i32; 4], a: [u32; 4], b: [u32; 4], metadata: u32, selector: u32")
-        );
-        assert!(
-            compatibility
-                .contains("c: [f32; 4], a: [u32; 4], b: [u32; 4], metadata: u32, selector: u32")
-        );
-        assert!(
-            compatibility
-                .contains("c: [u32; 2], a: [u32; 4], b: [u32; 4], metadata: u32, selector: u32")
-        );
-
-        let dialect = render_dialect_sparse_mma(&catalog, "test-hash");
-        assert_eq!(dialect.matches("pub struct SparseMmaOp").count(), 1);
-        assert!(dialect.contains("MmaCarrier::F32"));
-        assert!(dialect.contains("MmaCarrier::I32"));
-        assert!(dialect.contains("MmaCarrier::U32"));
-        assert!(dialect.contains("operands.len() != expected_operands"));
-        assert!(dialect.contains("SparseMmaShapeAttr { M16n8k32, M16n8k64, M16n8k128 }"));
-        assert!(dialect.contains("SparseMmaAccumulatorAttr { F16, F32, S32 }"));
-        assert!(dialect.contains("SparseMmaSelectorAttr { ImmediateZeroOrOne, ImmediateZero }"));
-        assert!(dialect.contains("SparseMmaElementAttr::E2m1"));
-        assert!(dialect.contains("SparseMmaElementAttr::E2m3"));
-        assert!(dialect.contains("SparseMmaElementAttr::E3m2"));
-        assert!(dialect.contains("SparseMmaElementAttr::E4m3"));
-        assert!(dialect.contains("SparseMmaElementAttr::E5m2"));
-        assert!(dialect.contains("SparseMmaElementAttr::S4"));
-        assert!(dialect.contains("SparseMmaElementAttr::U4"));
-        assert!(dialect.contains("SparseMmaElementAttr::S8"));
-        assert!(dialect.contains("SparseMmaElementAttr::U8"));
-        assert!(dialect.contains("SparseMmaOverflowAttr::Wrapping"));
-        assert!(dialect.contains("SparseMmaOverflowAttr::Satfinite"));
-        assert!(dialect.contains("SparseMmaOverflowAttr::NotApplicable"));
-        assert!(dialect.contains("SparseMmaMetadataAttr { Standard, Ordered }"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("sparse MMA selector must be the compile-time constant 0 or 1"));
-        assert!(importer.contains("sparse MMA selector must be the compile-time constant 0"));
-        assert!(importer.contains("GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32"));
-        assert!(importer.contains("GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32"));
-        assert!(importer.contains("GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32"));
-        assert!(importer.contains("GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32"));
-        assert!(importer.contains("(u32_ty, 2, u32_ty, 4, true, u32_ty, 4, true, u32_ty, 2)"));
-        assert!(importer.contains("let (c_array, last_op) = rvalue::translate_operand("));
-        assert!(importer.contains("ctx, body, &args[0], value_map"));
-        assert!(importer.contains("let (a_value, last_after_a) = rvalue::translate_operand("));
-        assert!(importer.contains("ctx, body, &args[1], value_map"));
-        assert!(importer.contains("let (b_value, last_after_b) = rvalue::translate_operand("));
-        assert!(importer.contains("ctx, body, &args[2], value_map"));
-        assert!(importer.contains("operands.push(metadata)"));
-        assert!(importer.contains("operands.push(selector_value)"));
-        assert!(importer.contains("SparseMmaOp::get_concrete_op_info"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert_eq!(
-            lowering
-                .matches("impl MirToLlvmConversion for SparseMmaOp")
-                .count(),
-            1
-        );
-        assert!(lowering.contains("convert_generated_sparse_mma"));
-        for record in &records {
-            assert!(lowering.contains(&sparse_mma_template(record)));
-            assert!(lowering.contains(&sparse_mma_constraints(record)));
-        }
-
-        let targets = render_targets(&catalog, "test-hash");
-        assert!(targets.contains("GeneratedIntrinsicVariant::SparseMma"));
-        assert!(targets.contains("Operation::get_op::<SparseMmaOp>"));
-        assert!(targets.contains("get_attr_nvvm_sparse_mma_selector"));
-        assert!(targets.contains("GeneratedSparseMmaSelector::ImmediateZeroOrOne"));
-        assert!(targets.contains("GeneratedSparseMmaSelector::ImmediateZero"));
-        assert!(targets.contains("GeneratedSparseMmaShape::M16n8k64"));
-        assert!(targets.contains("SparseMmaShapeAttr::M16n8k64"));
-        assert!(targets.contains("GeneratedSparseMmaShape::M16n8k128"));
-        assert!(targets.contains("SparseMmaShapeAttr::M16n8k128"));
-        assert!(targets.contains("GeneratedSparseMmaElement::S4"));
-        assert!(targets.contains("GeneratedSparseMmaElement::U4"));
-        assert!(targets.contains("GeneratedSparseMmaElement::E2m1"));
-        assert!(targets.contains("GeneratedSparseMmaElement::E5m2"));
-        assert!(targets.contains("SparseMmaElementAttr::S4"));
-        assert!(targets.contains("SparseMmaElementAttr::U4"));
-        assert!(targets.contains("GeneratedSparseMmaMetadata::Standard"));
-        assert!(targets.contains("SparseMmaMetadataAttr::Standard"));
-        assert!(targets.contains("GeneratedSparseMmaMetadata::Ordered"));
-        assert!(targets.contains("SparseMmaMetadataAttr::Ordered"));
-        assert!(targets.contains("GeneratedSparseMmaAccumulator::F16"));
-        assert!(targets.contains("GeneratedSparseMmaAccumulator::F32"));
-        assert!(targets.contains("GeneratedSparseMmaOverflow::NotApplicable"));
-        assert!(targets.contains("GeneratedHardwareAlternative::ExactArchitecture(120)"));
-
-        assert_eq!(raw.matches(SPARSE_MMA_STANDARD_METADATA_RULE).count(), 32);
-        assert_eq!(raw.matches(SPARSE_MMA_ORDERED_METADATA_RULE).count(), 82);
-        assert_eq!(
-            compatibility
-                .matches(SPARSE_MMA_STANDARD_METADATA_RULE)
-                .count(),
-            32
-        );
-        assert_eq!(
-            compatibility
-                .matches(SPARSE_MMA_ORDERED_METADATA_RULE)
-                .count(),
-            82
-        );
-        assert!(
-            lowering
-                .contains("mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32")
-        );
-        assert!(
-            lowering
-                .contains("mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32")
-        );
-        assert!(
-            lowering
-                .contains("mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32")
-        );
-        assert!(
-            lowering
-                .contains("mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32")
-        );
-        assert!(lowering.contains("mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32"));
-        assert!(lowering.contains("mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32"));
-        assert!(lowering.contains("mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32"));
-        assert!(lowering.contains(
-            "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32"
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::F32, 4, 14, "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n")"#
-        ));
-        assert!(lowering.contains(
-            r#"(GeneratedMmaResultType::I32, 2, 12, "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;", "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n")"#
-        ));
-        let f16_probe = render_probe(&catalog, ordered_f8f6f4_f16, "test-hash");
-        assert!(f16_probe.contains(
-            "define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16_selector_0"
-        ));
-        assert!(!f16_probe.contains("_selector_1"));
-
-        for record in &records {
-            let probe = render_probe(&catalog, record, "test-hash");
-            assert!(probe.contains(&format!("probe_{}_selector_0", record.id)));
-            let selectors = sparse_mma_selector_values(record);
-            assert_eq!(
-                probe.contains(&format!("probe_{}_selector_1", record.id)),
-                selectors.contains(&1)
-            );
-            assert_eq!(probe.matches("asm sideeffect").count(), selectors.len());
-            assert!(probe.contains(&sparse_mma_template(record)));
-            assert!(probe.contains(&sparse_mma_constraints(record)));
-            assert!(probe.contains("attributes #0 = { convergent }"));
-        }
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("## Sparse-MMA contracts"));
-        assert!(reference.contains("C, A, B, metadata, selector order"));
-        assert!(reference.contains("LLVM source record uses A, B, C, metadata, selector order"));
-        assert_eq!(
-            reference.matches(SPARSE_MMA_STANDARD_METADATA_RULE).count(),
-            32
-        );
-        assert_eq!(
-            reference.matches(SPARSE_MMA_ORDERED_METADATA_RULE).count(),
-            82
-        );
-        let sparse_reference = reference
-            .split("## Sparse-MMA contracts")
-            .nth(1)
-            .unwrap()
-            .split("## Packed-atomic contracts")
-            .next()
-            .unwrap();
-        assert!(sparse_reference.contains("Overflow mode is not applicable."));
-        assert!(!sparse_reference.contains("Integer overflow is not applicable"));
-        for record in &records {
-            assert!(reference.contains(&format!("- `{}`: runtime `unexecuted`", record.id)));
-        }
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/sparse_mma.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/sparse_mma.rs"
-        )));
-    }
-
-    #[test]
-    fn prmt_rendering_keeps_modes_and_zero_source_exact() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(prmts(&catalog).count(), 7);
-
-        let dialect = render_dialect_prmt(&catalog, "test-hash");
-        assert_eq!(dialect.matches("pub struct PrmtOp").count(), 1);
-        for mode in ["Generic", "F4e", "B4e", "Rc8", "Ecl", "Ecr", "Rc16"] {
-            assert!(dialect.contains(mode));
-        }
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        for mode in ["rc8", "ecl", "ecr", "rc16"] {
-            assert!(lowering.contains(&format!("prmt.b32.{mode} $0, $1, 0, $2;")));
-        }
-        assert!(lowering.contains("prmt.b32 $0, $1, $2, $3;"));
-        assert!(lowering.contains("prmt.b32.f4e $0, $1, $2, $3;"));
-        assert!(lowering.contains("prmt.b32.b4e $0, $1, $2, $3;"));
-        assert!(lowering.contains("convert_generated_prmt"));
-
-        let targets = render_targets(&catalog, "test-hash");
-        assert!(targets.contains("GeneratedIntrinsicVariant::Prmt"));
-        assert!(targets.contains("Operation::get_op::<PrmtOp>"));
-        assert!(targets.contains("GeneratedPrmtMode::Rc16"));
-
-        let compatibility = render_compat_prmt(&catalog, "test-hash");
-        assert_eq!(compatibility.matches("pub fn prmt").count(), 7);
-    }
-
-    #[test]
-    fn selected_special_register_probes_use_the_llvm_route() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-
-        let clock = catalog
-            .intrinsics
-            .iter()
-            .find(|record| record.id == "clock")
-            .unwrap();
-        let typed = render_probe(&catalog, clock, "test-hash");
-        assert!(typed.contains("declare i32 @llvm.nvvm.read.ptx.sreg.clock()"));
-        assert!(typed.contains("call i32 @llvm.nvvm.read.ptx.sreg.clock()"));
-
-        let gridid = catalog
-            .intrinsics
-            .iter()
-            .find(|record| record.id == "gridid")
-            .unwrap();
-        let inline = render_probe(&catalog, gridid, "test-hash");
-        assert!(inline.contains("define i64 @probe_gridid_llvm_nvptx()"));
-        assert!(inline.contains("call i64 asm \"mov.u64 $0, %gridid;\", \"=l\"()"));
-    }
-
-    #[test]
-    fn cluster_barrier_rendering_owns_compatibility_sync_and_both_backends() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        assert_eq!(cluster_barriers(&catalog).count(), 6);
-
-        let dialect = render_dialect_cluster_barrier(&catalog, "test-hash");
-        assert_eq!(dialect.matches("pub struct ClusterBarrierOp").count(), 1);
-        assert_eq!(dialect.matches("pub struct ClusterSyncOp").count(), 1);
-        assert!(dialect.contains("name = \"nvvm.cluster_sync\""));
-        assert!(dialect.contains("ClusterSyncOp::register(ctx);"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("\"cuda_device::cluster::cluster_sync\" =>"));
-        assert!(importer.contains("ClusterBarrierModeAttr::ArriveAligned"));
-        assert!(importer.contains("ClusterBarrierModeAttr::WaitAligned"));
-        assert!(!importer.contains("ClusterSyncOp"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert_eq!(
-            lowering
-                .matches("impl MirToLlvmConversion for ClusterSyncOp")
-                .count(),
-            1
-        );
-        assert!(lowering.contains("llvm_nvvm_barrier_cluster_arrive_aligned"));
-        assert!(lowering.contains("llvm_nvvm_barrier_cluster_wait_aligned"));
-        assert!(lowering.contains("barrier.cluster.arrive.aligned; barrier.cluster.wait.aligned;"));
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("## Cluster-barrier contracts"));
-        assert!(reference.contains(
-            "`cuda_device::cluster::cluster_sync` is the generated compatibility operation"
-        ));
-
-        let targets = render_targets(&catalog, "test-hash");
-        assert!(targets.contains(
-            "GeneratedIntrinsicVariant::ClusterBarrier { mode: GeneratedClusterBarrierMode::ArriveRelaxedAligned }"
-        ));
-        assert!(targets.contains("Operation::get_op::<ClusterBarrierOp>"));
-        assert!(targets.contains("ClusterBarrierModeAttr::WaitAligned"));
-    }
-
-    #[test]
-    fn cluster_memory_rendering_preserves_cluster_shared_addrspace_and_composite_load() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        let records = cluster_memory(&catalog).collect::<Vec<_>>();
-        assert_eq!(records.len(), 2);
-
-        let compatibility = render_compat_cluster_memory(&catalog, "test-hash");
-        for signature in [
-            "pub unsafe fn map_shared_rank<T>(local_ptr: *const T, target_rank: u32) -> *const T",
-            "pub unsafe fn map_shared_rank_mut<T>(local_ptr: *mut T, target_rank: u32) -> *mut T",
-            "pub unsafe fn dsmem_read_u32(local_ptr: *const u32, target_rank: u32) -> u32",
-        ] {
-            assert!(compatibility.contains(signature), "missing {signature}");
-        }
-        assert!(compatibility.contains("cluster-shared pointer in address space 7"));
-
-        let dialect_mod = render_dialect_mod(&catalog, "test-hash");
-        assert!(dialect_mod.contains("mod cluster_memory;"));
-        assert!(dialect_mod.contains("pub use cluster_memory::*;"));
-        assert!(dialect_mod.contains("cluster_memory::register(ctx);"));
-
-        let dialect = render_dialect_cluster_memory(&catalog, "test-hash");
-        assert!(dialect.contains("pub struct MapaSharedClusterOp"));
-        assert!(dialect.contains("pub struct DsmemReadU32Op"));
-        assert!(dialect.contains("source_ptr.pointer_kind()"));
-        assert!(dialect.contains("address_space::CLUSTER_SHARED"));
-        assert!(dialect.contains("MirPointerKind::RawConst | MirPointerKind::RawMut"));
-        assert!(dialect.contains("result_ptr.pointer_kind() != source_ptr.pointer_kind()"));
-        assert!(dialect.contains(
-            "nvvm.mapa_shared_cluster requires a raw source pointer and must preserve its pointee, mutability, and raw kind while returning addrspace(7)"
-        ));
-        assert!(dialect.contains("nvvm.dsmem_read_u32 result must be u32"));
-        assert!(dialect.contains("MapaSharedClusterOp::register(ctx);"));
-        assert!(dialect.contains("DsmemReadU32Op::register(ctx);"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        for path in [
-            "cuda_device::cluster::map_shared_rank",
-            "cuda_device::cluster::map_shared_rank_mut",
-            "cuda_device::cluster::dsmem_read_u32",
-        ] {
-            assert!(importer.contains(path));
-        }
-        assert!(importer.contains("MapaSharedClusterOp::build(ctx, source, rank)"));
-        assert!(importer.contains("DsmemReadU32Op::build(ctx, source, rank)"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("cast_to_shared_addrspace"));
-        assert!(lowering.contains("llvm_ops::IntToPtrOp::new"));
-        assert!(lowering.contains("llvm_types::PointerType::get(ctx, 7)"));
-        assert!(lowering.contains("mapa.shared::cluster.u64 $0, $1, $2;"));
-        assert!(lowering.contains(
-            "{ .reg .u64 %mapped; mapa.shared::cluster.u64 %mapped, $1, $2; ld.shared::cluster.u32 $0, [%mapped]; }"
-        ));
-        assert!(lowering.contains("\"=l,l,r\""));
-        assert!(lowering.contains("\"=r,l,r,~{memory}\""));
-
-        let map = records
-            .iter()
-            .find(|record| record.id == "map_shared_rank")
-            .unwrap();
-        assert_eq!(map.llvm.as_ref().unwrap().results, ["shared_cluster_ptr"]);
-        let map_probe = render_probe(&catalog, map, "test-hash");
-        assert!(map_probe.contains("define ptr addrspace(7)"));
-        assert!(map_probe.contains("inttoptr i64"));
-        assert!(map_probe.contains("asm sideeffect"));
-        assert!(!map_probe.contains("~{memory}"));
-        assert!(map_probe.contains("attributes #0 = { convergent }"));
-
-        let read = records
-            .iter()
-            .find(|record| record.id == "dsmem_read_u32")
-            .unwrap();
-        assert!(read.llvm.is_none());
-        let read_probe = render_probe(&catalog, read, "test-hash");
-        assert!(read_probe.contains("ld.shared::cluster.u32"));
-        assert!(read_probe.contains("~{memory}"));
-        assert!(read_probe.contains("attributes #0 = { convergent }"));
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("pub unsafe fn i0320(_arg0: *const u8, _arg1: u32) -> *const u8"));
-        assert!(raw.contains("pub unsafe fn i0321(_arg0: *const u32, _arg1: u32) -> u32"));
-        assert!(raw.contains(
-            "ordinary loads and stores compile to `ld.shared::cluster` and `st.shared::cluster`"
-        ));
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("## Cluster-memory contracts"));
-        assert!(reference.contains("preserves LLVM 22's address-space-7 result"));
-        assert!(reference.contains("has no one-to-one LLVM intrinsic"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/cluster_memory.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/cluster_memory.rs"
-        )));
-
-        let mut wrong_as = catalog.clone();
-        wrong_as
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "map_shared_rank")
-            .unwrap()
-            .llvm
-            .as_mut()
-            .unwrap()
-            .results = vec!["shared_ptr".into()];
-        assert!(validate_renderable(&wrong_as).is_err());
-
-        let mut wrong_source = catalog;
-        wrong_source
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "dsmem_read_u32")
-            .unwrap()
-            .source = IntrinsicSource::LlvmImported {
-            source_record: "invented".into(),
-        };
-        assert!(validate_renderable(&wrong_source).is_err());
-    }
-
-    #[test]
-    fn lowering_imports_cast_to_shared_addrspace_exactly_once_across_families() {
-        // The stmatrix, cluster_memory, and mbarrier_extended families all
-        // insert the `cast_to_shared_addrspace` helper into the same
-        // `common::{call_intrinsic, ...}` use group. An unguarded second
-        // insert duplicates the name inside one use group, which is a hard
-        // rustc error (E0252) in the raw generator output. The rustfmt pass
-        // run over generated files silently dedupes the duplicate, so assert
-        // on the raw (pre-rustfmt) output to catch a regressed guard loudly.
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        assert!(stmatrices(&catalog).next().is_some());
-        assert!(cluster_memory(&catalog).next().is_some());
-        assert!(mbarrier_extended(&catalog).next().is_some());
-
-        let import_count = |lowering: &str| {
-            // Everything before the first rendered helper function is the
-            // module header plus the use block; helper call sites in the
-            // function bodies below must not count.
-            let bodies_start = lowering
-                .find("fn convert_zero_operand_scalar_direct")
-                .expect("lowering output must contain the first helper function");
-            lowering[..bodies_start]
-                .matches("cast_to_shared_addrspace")
-                .count()
-        };
-
-        assert_eq!(
-            import_count(&render_lowering(&catalog, "test-hash")),
-            1,
-            "cast_to_shared_addrspace must be imported exactly once in the \
-             raw lowering output when multiple families need it"
-        );
-
-        // The guard must not suppress the import either: with stmatrix
-        // absent, cluster_memory still needs the helper and must insert it.
-        let mut without_stmatrix = catalog;
-        without_stmatrix
-            .intrinsics
-            .retain(|record| record.family != "stmatrix");
-        assert!(stmatrices(&without_stmatrix).next().is_none());
-        assert_eq!(
-            import_count(&render_lowering(&without_stmatrix, "test-hash")),
-            1,
-            "cast_to_shared_addrspace must still be imported when only \
-             cluster_memory and mbarrier_extended need it"
-        );
-    }
-
-    #[test]
-    fn clc_rendering_preserves_api_and_uses_typed_llvm_routes() {
-        let catalog = catalog_with_clc();
-        validate_renderable(&catalog).unwrap();
-
-        let compatibility = render_compat_clc(&catalog, "test-hash");
-        assert!(
-            compatibility
-                .contains("pub unsafe fn clc_try_cancel(response: *mut u8, mbar: *mut Barrier)")
-        );
-        assert!(compatibility.contains(
-            "pub unsafe fn clc_try_cancel_multicast(response: *mut u8, mbar: *mut Barrier)"
-        ));
-        assert!(
-            compatibility
-                .contains("pub unsafe fn clc_query_is_canceled(resp_lo: u64, resp_hi: u64) -> u32")
-        );
-
-        let dialect = render_dialect_clc(&catalog, "test-hash");
-        for op in [
-            "ClcTryCancelOp",
-            "ClcTryCancelMulticastOp",
-            "ClcQueryIsCanceledOp",
-            "ClcQueryGetFirstCtaidXOp",
-            "ClcQueryGetFirstCtaidYOp",
-            "ClcQueryGetFirstCtaidZOp",
-        ] {
-            assert_eq!(dialect.matches(&format!("pub struct {op}")).count(), 1);
-            assert!(dialect.contains(&format!("{op}::register(ctx)")));
-        }
-        assert_eq!(dialect.matches("NResultsInterface<0>").count(), 2);
-        assert_eq!(dialect.matches("NResultsInterface<1>").count(), 4);
-        assert_eq!(dialect.matches("impl Verify for ClcQuery").count(), 4);
-        assert!(dialect.contains("is_integer_width(ctx, op.get_operand(0).get_type(ctx), 64)"));
-        assert!(dialect.contains("is_integer_width(ctx, op.get_result(0).get_type(ctx), 32)"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::clc::clc_try_cancel"));
-        assert!(importer.contains("ClcTryCancelOp::get_concrete_op_info()"));
-        assert!(importer.contains("ClcQueryIsCanceledOp::get_concrete_op_info()"));
-        assert!(importer.contains("helpers::emit_store_result_and_goto"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(
-            lowering
-                .contains("clc::{convert_generated_clc_query, convert_generated_clc_try_cancel}")
-        );
-        assert!(lowering.contains(
-            "convert_generated_clc_try_cancel(ctx, rewriter, self.get_operation(), operands_info, \"llvm__nvvm_dclusterlaunchcontrol_dtry_ucancel_dasync_dshared\")"
-        ));
-        assert!(lowering.contains(
-            "convert_generated_clc_query(ctx, rewriter, self.get_operation(), operands_info, \"llvm__nvvm_dclusterlaunchcontrol_dquery_ucancel_dis_ucanceled\", true)"
-        ));
-
-        let request = clc_intrinsics(&catalog)
-            .find(|record| record.id == "clc_try_cancel")
-            .unwrap();
-        let request_probe = render_probe(&catalog, request, "test-hash");
-        assert_eq!(request_probe.matches("addrspacecast ptr").count(), 2);
-        assert!(request_probe.contains(
-            "call void @llvm.nvvm.clusterlaunchcontrol.try_cancel.async.shared(ptr addrspace(3) %response, ptr addrspace(3) %mbarrier)"
-        ));
-
-        let query = clc_intrinsics(&catalog)
-            .find(|record| record.id == "clc_query_is_canceled")
-            .unwrap();
-        let query_probe = render_probe(&catalog, query, "test-hash");
-        assert!(query_probe.contains("%response_high_shifted = shl i128 %response_high_i128, 64"));
-        assert!(
-            query_probe.contains("%response = or i128 %response_low_i128, %response_high_shifted")
-        );
-        assert!(query_probe.contains("%result = zext i1 %raw_result to i32"));
-
-        let targets = render_targets(&catalog, "test-hash");
-        assert!(targets.contains(
-            "GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(100), GeneratedHardwareAlternative::ExactArchitecture(101), GeneratedHardwareAlternative::ExactArchitecture(103), GeneratedHardwareAlternative::ExactArchitecture(110), GeneratedHardwareAlternative::ExactArchitecture(120), GeneratedHardwareAlternative::ExactArchitecture(121)])"
-        ));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/clc.rs")));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/clc.rs"
-        )));
-
-        let mut wrong_adapter = catalog;
-        wrong_adapter
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "clc_query_is_canceled")
-            .unwrap()
-            .clc
-            .as_mut()
-            .unwrap()
-            .adapter = ClcAdapter::PairU64ToI128U32;
-        assert!(validate_renderable(&wrong_adapter).is_err());
-    }
-
-    #[test]
-    fn elect_dialect_verifies_its_scalar_shape() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        let dialect = render_dialect_elect(&catalog, "test-hash");
-
-        assert!(dialect.contains("impl Verify for ElectSyncOp"));
-        assert!(dialect.contains("is_integer_width(ctx, op.get_operand(0).get_type(ctx), 32)"));
-        assert!(dialect.contains("is_integer_width(ctx, op.get_result(0).get_type(ctx), 32)"));
-        assert!(dialect.contains("is_integer_width(ctx, op.get_result(1).get_type(ctx), 1)"));
-        assert!(!dialect.contains("verifier = \"succ\""));
-    }
-
-    #[test]
-    fn tma_rendering_preserves_api_and_injects_backend_defaults() {
-        let catalog = catalog_with_tma();
-        validate_renderable(&catalog).unwrap();
-
-        let compatibility = render_compat_tma(&catalog, "test-hash");
-        assert!(compatibility.contains(
-            "pub unsafe fn cp_async_bulk_tensor_1d_g2s(dst: *mut u8, tensor_map: *const TmaDescriptor, coord0: i32, barrier: *mut Barrier)"
-        ));
-        assert!(compatibility.contains(
-            "pub unsafe fn cp_async_bulk_tensor_2d_g2s_multicast(dst: *mut u8, tensor_map: *const TmaDescriptor, coord0: i32, coord1: i32, barrier: *mut Barrier, cta_mask: u16)"
-        ));
-        assert!(compatibility.contains(
-            "pub unsafe fn cp_async_bulk_tensor_5d_s2g(src: *const u8, tensor_map: *const TmaDescriptor, coord0: i32, coord1: i32, coord2: i32, coord3: i32, coord4: i32)"
-        ));
-        assert!(compatibility.contains("pub fn cp_async_bulk_commit_group()"));
-        assert!(compatibility.contains("pub fn cp_async_bulk_wait_group(n: u32)"));
-        assert!(compatibility.contains(
-            "pub unsafe fn cp_async_bulk_tensor_reduce_add_tile_2d(src: *const u8, tensor_map: *const TmaDescriptor, coord0: i32, coord1: i32)"
-        ));
-        assert!(compatibility.contains(
-            "pub unsafe fn cp_async_bulk_tensor_reduce_xor_im2col_5d(src: *const u8, tensor_map: *const TmaDescriptor, coord0: i32, coord1: i32, coord2: i32, coord3: i32, coord4: i32)"
-        ));
-        for dimensions in 1..=5 {
-            assert!(compatibility.contains(&format!(
-                "pub unsafe fn cp_async_bulk_prefetch_tensor_{dimensions}d_l2("
-            )));
-            assert!(compatibility.contains(&format!(
-                "pub unsafe fn cp_async_bulk_prefetch_tensor_{dimensions}d_l2_cache_hint("
-            )));
-        }
-        assert!(
-            compatibility.contains("pub unsafe fn cp_async_bulk_prefetch_tensor_gather4_2d_l2(")
-        );
-        assert!(
-            compatibility
-                .contains("pub unsafe fn cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint(")
-        );
-        assert!(compatibility.contains("pub unsafe fn tensormap_replace_swizzle_atomicity("));
-        assert!(
-            compatibility.contains("pub unsafe fn fence_proxy_tensormap_generic_acquire_system(")
-        );
-        assert!(compatibility.contains("pub fn fence_proxy_tensormap_generic_release_system()"));
-
-        let dialect = render_dialect_tma(&catalog, "test-hash");
-        assert_eq!(dialect.matches("pub struct ").count(), 111);
-        assert_eq!(dialect.matches("NResultsInterface<0>").count(), 111);
-        assert!(dialect.contains("NOpdsInterface<10>"));
-        assert!(dialect.contains("CpAsyncBulkWaitGroupReadOp::register(ctx)"));
-        assert!(
-            dialect.contains("CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op::register(ctx)")
-        );
-        assert!(dialect.contains(
-            "CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp::register(ctx)"
-        ));
-        assert!(dialect.contains("ReplaceTensorMapSwizzleAtomicityOp::register(ctx)"));
-        assert!(dialect.contains("FenceProxyTensorMapGenericReleaseSystemOp::register(ctx)"));
-
-        let dialect_mod = render_dialect_mod(&catalog, "test-hash");
-        assert!(dialect_mod.contains("mod tma;"));
-        assert!(dialect_mod.contains("pub use tma::*;"));
-        assert!(dialect_mod.contains("tma::register(ctx);"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::tma::cp_async_bulk_tensor_1d_g2s"));
-        assert!(importer.contains("super::tma::emit_tma_g2s("));
-        assert!(importer.contains("super::tma::emit_tma_g2s_multicast_cg2("));
-        assert!(importer.contains("super::tma::emit_tma_s2g("));
-        assert!(importer.contains("TMA wait-group count must be a compile-time constant"));
-        assert!(importer.contains("require_arity(name, args.len(), 1, &loc)?;"));
-        assert!(importer.contains("args.first(), Some(mir::Operand::Constant(_))"));
-        assert!(importer.contains("\"v1:i0328\""));
-        assert!(importer.contains("cp_async_bulk_tensor_reduce_add_tile_2d"));
-        assert!(importer.contains(
-            "dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile2dOp::get_concrete_op_info()"
-        ));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(lowering.contains("CpAsyncBulkTensorG2sTile1dOp"));
-        assert!(lowering.contains(
-            "tma::{convert_control, convert_g2s, convert_g2s_multicast_cg2, convert_prefetch_tensormap, convert_prefetch_tile, convert_reduce_s2g, convert_s2g, convert_tensormap_fence, convert_tensormap_replace, PrefetchTileConfig, ReduceConfig}"
-        ));
-        assert!(
-            lowering.contains(
-                "convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 5, false)"
-            )
-        );
-        assert!(
-            lowering.contains("convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 5)")
-        );
-        assert!(lowering.contains(
-            "convert_control(ctx, rewriter, self.get_operation(), operands_info, \"commit_group\", \"llvm_nvvm_cp_async_bulk_commit_group\")"
-        ));
-        assert!(lowering.contains(
-            "convert_reduce_s2g(ctx, rewriter, self.get_operation(), operands_info, ReduceConfig::new(2, \"add\", \"tile\", \"llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_2d\"))"
-        ));
-        assert!(lowering.contains(
-            "convert_prefetch_tile(ctx, rewriter, self.get_operation(), operands_info, PrefetchTileConfig::new(5, false, false, \"llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_5d\"))"
-        ));
-        assert!(lowering.contains(
-            "convert_tensormap_replace(ctx, rewriter, self.get_operation(), operands_info, \"llvm_nvvm_tensormap_replace_global_address\", \"global_address\", \"address\", false, false)"
-        ));
-        let release_system = tma_intrinsics(&catalog)
-            .find(|record| record.id == "fence_proxy_tensormap_generic_release_system")
-            .unwrap();
-        assert!(lowering.contains(&format!(
-            "convert_tensormap_fence(ctx, rewriter, self.get_operation(), operands_info, {:?}, false, \"sys\")",
-            release_system.resolved_llvm_identifier()
-        )));
-
-        let g2s = tma_intrinsics(&catalog)
-            .find(|record| record.id == "cp_async_bulk_tensor_2d_g2s_multicast_cg2")
-            .unwrap();
-        let g2s_probe = render_probe(&catalog, g2s, "test-hash");
-        assert!(g2s_probe.contains("i16 %cta_mask, i64 0, i1 true, i1 false, i32 2"));
-        assert!(g2s_probe.contains("addrspacecast ptr %dst_generic to ptr addrspace(7)"));
-
-        let s2g = tma_intrinsics(&catalog)
-            .find(|record| record.id == "cp_async_bulk_tensor_2d_s2g")
-            .unwrap();
-        let s2g_probe = render_probe(&catalog, s2g, "test-hash");
-        assert!(s2g_probe.contains("ptr %tensor_map, i32 %coord0, i32 %coord1, i64 0, i1 false"));
-
-        let reduce = tma_intrinsics(&catalog)
-            .find(|record| record.id == "cp_async_bulk_tensor_reduce_add_tile_2d")
-            .unwrap();
-        let reduce_probe = render_probe(&catalog, reduce, "test-hash");
-        assert!(reduce_probe.contains(
-            "declare void @llvm.nvvm.cp.async.bulk.tensor.reduce.add.tile.2d(ptr addrspace(3), ptr, i32, i32, i64, i1)"
-        ));
-        assert!(reduce_probe.contains(
-            "call void @llvm.nvvm.cp.async.bulk.tensor.reduce.add.tile.2d(ptr addrspace(3) %src, ptr %tensor_map, i32 %coord0, i32 %coord1, i64 0, i1 false)"
-        ));
-
-        for stem in [
-            "cp_async_bulk_prefetch_tensor_1d_l2",
-            "cp_async_bulk_prefetch_tensor_2d_l2",
-            "cp_async_bulk_prefetch_tensor_3d_l2",
-            "cp_async_bulk_prefetch_tensor_4d_l2",
-            "cp_async_bulk_prefetch_tensor_5d_l2",
-            "cp_async_bulk_prefetch_tensor_gather4_2d_l2",
-        ] {
-            let prefetch_plain = tma_intrinsics(&catalog)
-                .find(|record| record.id == stem)
-                .unwrap();
-            let prefetch_plain_probe = render_probe(&catalog, prefetch_plain, "test-hash");
-            assert!(prefetch_plain_probe.contains("i64 0, i1 false"));
-            assert!(!prefetch_plain_probe.contains("%cache_hint"));
-
-            let cache_hint_id = format!("{stem}_cache_hint");
-            let prefetch_cache_hint = tma_intrinsics(&catalog)
-                .find(|record| record.id == cache_hint_id)
-                .unwrap();
-            let prefetch_cache_hint_probe =
-                render_probe(&catalog, prefetch_cache_hint, "test-hash");
-            assert!(prefetch_cache_hint_probe.contains("i64 %cache_hint"));
-            assert!(prefetch_cache_hint_probe.contains("i64 %cache_hint, i1 true"));
-        }
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/tma.rs")));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/tma.rs"
-        )));
-
-        let mut wrong_adapter = catalog;
-        wrong_adapter
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "cp_async_bulk_tensor_1d_g2s")
-            .unwrap()
-            .tma
-            .as_mut()
-            .unwrap()
-            .adapter = TmaAdapter::NoOperands;
-        assert!(validate_renderable(&wrong_adapter).is_err());
-    }
-
-    #[test]
-    fn tcgen05_rendering_preserves_api_and_inline_ptx_routes() {
-        let catalog = catalog_with_tcgen05();
-        validate_renderable(&catalog).unwrap();
-
-        let compatibility = render_compat_tcgen05(&catalog, "test-hash");
-        assert!(
-            compatibility
-                .contains("pub unsafe fn tcgen05_alloc(dst_smem: *mut u32, n_cols: u32) -> ()")
-        );
-        assert!(compatibility.contains(
-            "pub unsafe fn tcgen05_mma_ws_f16(d_tmem: u32, a_tmem: u32, a_desc: u64, b_desc: u64, idesc: u32, enable_d: bool) -> ()"
-        ));
-        for alias in ["e4m3", "e5m2", "e2m3", "e3m2", "e2m1"] {
-            assert!(compatibility.contains(&format!(
-                "pub unsafe fn tcgen05_mma_{alias}(d_tmem: u32, a_desc: u64, b_desc: u64, idesc: u32, enable_d: bool)"
-            )));
-        }
-        assert!(
-            compatibility
-                .contains("pub unsafe fn tcgen05_ld_16x256b_x8_pure(tmem_addr: u32) -> TmemF32x32")
-        );
-        assert!(compatibility.contains("pub fn tcgen05_load_wait() -> ()"));
-        assert!(compatibility.contains("pub fn tcgen05_relinquish_alloc_permit() -> ()"));
-        assert!(compatibility.contains("pub fn tcgen05_relinquish_alloc_permit_cg2() -> ()"));
-        assert!(compatibility.contains(
-            "One full warp must execute this instruction uniformly with the same operands."
-        ));
-        assert!(compatibility.contains(
-            "One full warp in each peer CTA must execute this instruction; lanes within each warp must execute uniformly with the same operands."
-        ));
-        assert!(compatibility.contains(
-            "pub unsafe fn tcgen05_commit_multicast_cg2(mbar: *mut u64, cta_mask: u16) -> ()"
-        ));
-        assert!(compatibility.contains(
-            "pub unsafe fn tcgen05_cp_128x128b_b4x16_p64(tmem_addr: u32, smem_desc: u64) -> ()"
-        ));
-        assert!(compatibility.contains(
-            "pub unsafe fn tcgen05_cp_64x128b_warpx2_02_13_cg2(tmem_addr: u32, smem_desc: u64) -> ()"
-        ));
-        assert!(
-            compatibility.contains("pub unsafe fn tcgen05_ld_16x64b_x1_raw(tmem_addr: u32) -> u32")
-        );
-        assert!(
-            compatibility.contains(
-                "pub unsafe fn tcgen05_ld_16x64b_x2_raw(tmem_addr: u32) -> CuSimd<u32, 2>"
-            )
-        );
-        assert!(compatibility.contains(
-            "pub unsafe fn tcgen05_ld_32x32b_x128_pack16(tmem_addr: u32) -> CuSimd<u32, 128>"
-        ));
-        assert!(
-            compatibility.contains(
-                "pub unsafe fn tcgen05_st_16x64b_x1_raw(tmem_addr: u32, data: u32) -> ()"
-            )
-        );
-        assert!(compatibility.contains(
-            "pub unsafe fn tcgen05_st_16x64b_x2_raw(tmem_addr: u32, data: CuSimd<u32, 2>) -> ()"
-        ));
-        assert!(compatibility.contains(
-            "pub unsafe fn tcgen05_st_32x32b_x128_unpack16(tmem_addr: u32, data: CuSimd<u32, 128>) -> ()"
-        ));
-        assert!(compatibility.contains(
-            "pub unsafe fn tcgen05_ld_16x32bx2_x1_raw<const HALF_SPLIT_OFFSET: i32>(tmem_addr: u32) -> u32"
-        ));
-        assert!(compatibility.contains(
-            "pub(crate) unsafe fn __tcgen05_ld_16x32bx2_x1_raw(_tmem_addr: u32, _half_split_offset: i64) -> u32"
-        ));
-        assert!(compatibility.contains(
-            "unsafe { __tcgen05_ld_16x32bx2_x1_raw(tmem_addr, HALF_SPLIT_OFFSET as i64) }"
-        ));
-        assert!(compatibility.contains(
-            "pub unsafe fn tcgen05_st_16x32bx2_x128_unpack16<const HALF_SPLIT_OFFSET: i32>(tmem_addr: u32, data: CuSimd<u32, 128>)"
-        ));
-        assert!(compatibility.contains(
-            "pub(crate) unsafe fn __tcgen05_st_16x32bx2_x128_unpack16(_tmem_addr: u32, _half_split_offset: i64, _data: CuSimd<u32, 128>)"
-        ));
-        assert!(compatibility.contains(
-            "pub unsafe fn tcgen05_commit_multicast(mbar: *mut u64, cta_mask: u16) -> ()"
-        ));
-        assert!(compatibility.contains("pub unsafe fn tcgen05_shift_down(tmem_addr: u32) -> ()"));
-        assert!(
-            compatibility.contains("pub unsafe fn tcgen05_shift_down_cg2(tmem_addr: u32) -> ()")
-        );
-        assert_eq!(
-            compatibility
-                .matches("/// One thread in the CTA issues this instruction.\n")
-                .count(),
-            4
-        );
-        assert_eq!(
-            compatibility
-                .matches(
-                    "/// One thread in the CTA pair issues this instruction; the peer CTA must be active and must not have exited.\n",
-                )
-                .count(),
-            4
-        );
-        assert_eq!(
-            compatibility
-                .matches(
-                    "/// The same thread that issued the tracked asynchronous tcgen05 operations must issue this commit.\n",
-                )
-                .count(),
-            6
-        );
-        assert_eq!(
-            compatibility
-                .matches(
-                    "/// Completion must be tracked by a matching commit from that same thread and observed through the selected mbarrier before relying on shifted data.\n",
-                )
-                .count(),
-            2
-        );
-        assert_eq!(
-            compatibility
-                .matches(
-                    "/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n",
-                )
-                .count(),
-            233
-        );
-        assert!(compatibility.contains("/// `KIND` is 0=f16, 1=tf32, 2=f8f6f4, or 3=i8."));
-        assert!(compatibility.contains(
-            "/// `CTA_GROUP` is 1 or 2. `COLLECTOR_A` is 0=discard, 1=lastuse, 2=fill, or 3=use."
-        ));
-        assert!(compatibility.contains(
-            "/// `B_BUFFER` is 0 through 3. `B_USAGE` is 0=discard, 1=lastuse, 2=fill, or 3=use."
-        ));
-        assert_eq!(
-            compatibility
-                .matches(
-                    "/// `legacy_a_desc` is kept for compatibility; tensor A uses `a_tmem`.\n",
-                )
-                .count(),
-            5
-        );
-        assert_eq!(
-            compatibility
-                .matches("/// This uses kind f8f6f4, CTA group 1, and collector a::discard.\n",)
-                .count(),
-            5
-        );
-        assert!(!compatibility.contains("tcgen05_mma_ws_f16_with_collector"));
-
-        let raw = render_raw_abi(&catalog, "test-hash").unwrap();
-        assert!(raw.contains("pub unsafe fn i0578(_arg0: u32, _arg1: u64) -> ()"));
-        assert!(raw.contains("pub unsafe fn i0611(_arg0: u32, _arg1: u64) -> ()"));
-        assert!(raw.contains("pub unsafe fn i0612(_arg0: u32) -> u32"));
-        assert!(raw.contains("pub unsafe fn i0614(_arg0: u32) -> [u32; 2]"));
-        assert!(raw.contains("pub unsafe fn i0669(_arg0: u32) -> [u32; 128]"));
-        assert!(raw.contains("pub unsafe fn i0670(_arg0: u32, _arg1: u32) -> ()"));
-        assert!(raw.contains("pub unsafe fn i0672(_arg0: u32, _arg1: [u32; 2]) -> ()"));
-        assert!(raw.contains("pub unsafe fn i0727(_arg0: u32, _arg1: [u32; 128]) -> ()"));
-        assert!(raw.contains("pub unsafe fn i0728(_arg0: u32, _arg1: i64) -> u32"));
-        assert!(raw.contains("pub unsafe fn i0743(_arg0: u32, _arg1: i64) -> [u32; 128]"));
-        assert!(
-            raw.contains("pub unsafe fn i0759(_arg0: u32, _arg1: i64, _arg2: [u32; 128]) -> ()")
-        );
-        assert!(raw.contains("pub unsafe fn i0760(_arg0: *mut u64, _arg1: u16) -> ()"));
-        assert!(raw.contains("pub unsafe fn i0761(_arg0: u32) -> ()"));
-        assert!(raw.contains("pub unsafe fn i0762(_arg0: u32) -> ()"));
-        let mma = raw.find("pub unsafe fn i0763").unwrap();
-        assert!(raw[..mma].ends_with("#[allow(clippy::too_many_arguments)]\n#[inline(never)]\n"));
-        assert!(raw.contains("lane component must be a multiple of 32"));
-        assert!(raw.contains("`_arg0` must name a live tensor-memory allocation"));
-        assert_eq!(
-            raw.matches("/// One thread in the CTA issues this instruction.\n")
-                .count(),
-            4
-        );
-        assert_eq!(
-            raw.matches(
-                "/// One thread in the CTA pair issues this instruction; the peer CTA must be active and must not have exited.\n",
-            )
-            .count(),
-            4
-        );
-        assert_eq!(
-            raw.matches(
-                "/// The same thread that issued the tracked asynchronous tcgen05 operations must issue this commit.\n",
-            )
-            .count(),
-            6
-        );
-        assert_eq!(
-            raw.matches(
-                "/// Completion must be tracked by a matching commit from that same thread and observed through the selected mbarrier before relying on shifted data.\n",
-            )
-            .count(),
-            2
-        );
-        assert_eq!(
-            raw.matches(
-                "/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n",
-            )
-            .count(),
-            233
-        );
-        assert!(raw.contains("pub fn i0345() -> ()"));
-        assert!(raw.contains("pub fn i0357() -> ()"));
-        assert!(raw.contains("pub fn i0358() -> ()"));
-        assert!(raw.contains("pub fn i0361() -> ()"));
-        assert!(raw.contains("Complete the matching tensor-memory load wait"));
-        assert!(raw.contains("Complete the matching tensor-memory store wait"));
-        let raw_mod = render_raw_mod(&catalog, "test-hash");
-        assert!(raw_mod.contains(
-            "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0578 as tcgen05_cp_128x128b_b4x16_p64;"
-        ));
-        assert!(raw_mod.contains(
-            "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0611 as tcgen05_cp_64x128b_warpx2_02_13_cg2;"
-        ));
-        assert!(raw_mod.contains(
-            "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0727 as tcgen05_st_32x32b_x128_unpack16;"
-        ));
-        assert!(raw_mod.contains(
-            "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0728 as tcgen05_ld_16x32bx2_x1_raw;"
-        ));
-        assert!(raw_mod.contains(
-            "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0759 as tcgen05_st_16x32bx2_x128_unpack16;"
-        ));
-        assert!(raw_mod.contains(
-            "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0760 as tcgen05_commit_multicast;"
-        ));
-        assert!(raw_mod.contains(
-            "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0761 as tcgen05_shift_down;"
-        ));
-        assert!(raw_mod.contains(
-            "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0762 as tcgen05_shift_down_cg2;"
-        ));
-
-        let dialect = render_dialect_tcgen05(&catalog, "test-hash");
-        assert_eq!(dialect.matches("pub struct Tcgen05").count(), 210);
-        assert_eq!(dialect.matches("impl Verify for Tcgen05").count(), 210);
-        assert_eq!(dialect.matches("::register(ctx)").count(), 216);
-        assert_eq!(dialect.matches("            Some(1),").count(), 32);
-        assert_eq!(dialect.matches("verifier = \"succ\"").count(), 6);
-        assert!(dialect.contains("Operation::get_op::<MirConstantOp>"));
-        assert!(dialect.contains("Operation::get_op::<ConstantOp>"));
-        assert!(dialect.contains("&[(Tcgen05Carrier::I32, 1), (Tcgen05Carrier::I64, 1)],"));
-        assert!(dialect.contains(
-            "&[(Tcgen05Carrier::I32, 1), (Tcgen05Carrier::I64, 1), (Tcgen05Carrier::I32, 128)],"
-        ));
-        assert!(dialect.contains("pub struct Tcgen05Ld16x64bX1RawOp"));
-        assert!(dialect.contains("pub struct Tcgen05Ld32x32bX128Pack16Op"));
-        assert!(dialect.contains("pub struct Tcgen05St16x64bX1RawOp"));
-        assert!(dialect.contains("pub struct Tcgen05St32x32bX128Unpack16Op"));
-        assert!(dialect.contains("pub struct Tcgen05Ld16x32bx2X1RawOp"));
-        assert!(dialect.contains("pub struct Tcgen05St16x32bx2X128Unpack16Op"));
-        assert!(dialect.contains("pub struct Tcgen05CommitMulticastOp"));
-        assert!(dialect.contains("pub struct Tcgen05ShiftDownOp"));
-        assert!(dialect.contains("pub struct Tcgen05ShiftDownCg2Op"));
-        assert!(dialect.contains("NResultsInterface<128>"));
-        assert!(dialect.contains("NResultsInterface<32>"));
-        assert!(dialect.contains("NResultsInterface<4>"));
-        assert!(dialect.contains("NOpdsInterface<6>"));
-
-        let dialect_mod = render_dialect_mod(&catalog, "test-hash");
-        assert!(dialect_mod.contains("mod tcgen05;"));
-        assert!(dialect_mod.contains("pub use tcgen05::*;"));
-        assert!(dialect_mod.contains("tcgen05::register(ctx);"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::tcgen05::tcgen05_alloc"));
-        assert!(importer.contains("Tcgen05AllocOp::get_concrete_op_info()"));
-        assert!(importer.contains("Tcgen05Ld16x256bX8PureOp::get_concrete_op_info()"));
-        assert!(importer.contains("MirConstructStructOp::get_concrete_op_info()"));
-        assert!(importer.contains("Tcgen05Ld16x64bX1RawOp::get_concrete_op_info()"));
-        assert!(importer.contains("Tcgen05Ld32x32bX128Pack16Op::get_concrete_op_info()"));
-        assert!(importer.contains("Tcgen05St16x64bX1RawOp::get_concrete_op_info()"));
-        assert!(importer.contains("Tcgen05St32x32bX128Unpack16Op::get_concrete_op_info()"));
-        assert!(importer.contains("import_generated_tcgen05_store_operands("));
-        assert!(importer.contains("downcast_ref::<MirStructType>()"));
-        assert!(
-            importer
-                .contains("generated tcgen05 store data must contain {expected_len} u32 registers")
-        );
-        assert!(importer.contains("destination_ty == array_result.get_type(ctx)"));
-        assert!(!importer.contains("super::tcgen05::emit_"));
-        assert!(importer.contains("\"v1:i0343\""));
-        assert!(importer.contains("\"v1:i0366\""));
-        assert!(importer.contains("cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64"));
-        assert!(importer.contains("Tcgen05Cp128x128bB4x16P64Op::get_concrete_op_info()"));
-        assert!(importer.contains("\"v1:i0578\""));
-        assert!(importer.contains("\"v1:i0611\""));
-        assert!(importer.contains("\"v1:i0670\""));
-        assert!(importer.contains("\"v1:i0727\""));
-        assert!(importer.contains("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw"));
-        assert!(importer.contains("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16"));
-        assert!(
-            importer.contains("tcgen05 16x32bx2 half-split offset must be a compile-time constant")
-        );
-        assert!(importer.contains("half-split offset must lower to a constant"));
-        assert!(importer.contains("args, 128, true, block_ptr"));
-        assert!(importer.contains("\"v1:i0728\""));
-        assert!(importer.contains("\"v1:i0759\""));
-        assert!(importer.contains("\"v1:i0760\""));
-        assert!(importer.contains("\"v1:i0761\""));
-        assert!(importer.contains("\"v1:i0762\""));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert!(!lowering.contains("use crate::convert::intrinsics::tcgen05;"));
-        assert!(lowering.contains("impl MirToLlvmConversion for Tcgen05AllocOp"));
-        assert!(
-            lowering.contains(
-                "tcgen05.mma.ws.cta_group::1.kind::f16 [$0], [$1], $3, $4, %enable_pred;"
-            )
-        );
-        assert!(!lowering.contains(".kind::bf16"));
-        assert!(lowering.contains("convert_generated_tcgen05_load("));
-        assert!(lowering.contains("tcgen05.ld.sync.aligned.16x64b.x1.b32 {$0}, [$1];"));
-        assert!(lowering.contains("tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 {$0}, [$1];"));
-        assert!(lowering.contains("\"=r,r,~{memory}\""));
-        assert!(lowering.contains(
-            "convert_generated_tcgen05_load(ctx, rewriter, self.get_operation(), 1, 1, true"
-        ));
-        assert!(lowering.contains("convert_generated_tcgen05_void("));
-        assert!(lowering.contains("tcgen05.st.sync.aligned.16x64b.x1.b32 [$0], {$1};"));
-        assert!(
-            lowering.contains("tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [$0], {$1,$2")
-        );
-        assert!(lowering.contains("\"r,r,~{memory}\""));
-        assert!(lowering.contains("tcgen05.ld.sync.aligned.16x32bx2.x1.b32 {$0}, [$1], $2;"));
-        assert!(lowering.contains("tcgen05.st.sync.aligned.16x32bx2.x1.b32 [$0], $1, {$2};"));
-        assert!(lowering.contains("\"=r,r,n,~{memory}\""));
-        assert!(lowering.contains("\"r,n,r,~{memory}\""));
-        assert!(lowering.contains(
-            "convert_generated_tcgen05_load(ctx, rewriter, self.get_operation(), 2, 1, true"
-        ));
-        assert!(lowering.contains("builtin::types::{FP32Type, IntegerType, Signedness}"));
-        assert!(lowering.contains("ops as llvm_ops"));
-        assert!(lowering.contains("inserter::Inserter"));
-        assert!(lowering.contains("tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 [$0], $1;"));
-        assert!(lowering.contains("tcgen05.cp.cta_group::1.32x128b.warpx4 [$0], $1;"));
-        assert!(
-            lowering.contains(
-                "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 [$0], $1;"
-            )
-        );
-        assert!(lowering.contains("tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [$0], $1;"));
-        assert!(lowering.contains("\"r,l,~{memory}\""));
-        assert!(lowering.contains(
-            "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;"
-        ));
-        assert!(lowering.contains("tcgen05.shift.cta_group::1.down [$0];"));
-        assert!(lowering.contains("tcgen05.shift.cta_group::2.down [$0];"));
-        assert!(lowering.contains("\"r,h,~{memory}\""));
-
-        let bf16 = tcgen05_intrinsics(&catalog)
-            .find(|record| record.id == "tcgen05_mma_ws_bf16")
-            .unwrap();
-        let bf16_probe = render_probe(&catalog, bf16, "test-hash");
-        assert!(bf16_probe.contains("route: inline PTX"));
-        assert!(bf16_probe.contains(".kind::f16 [$0]"));
-        assert!(!bf16_probe.contains(".kind::bf16"));
-
-        let base_commit = tcgen05_intrinsics(&catalog)
-            .find(|record| record.id == "tcgen05_commit")
-            .unwrap();
-        let base_commit_probe = render_probe(&catalog, base_commit, "test-hash");
-        assert!(base_commit_probe.contains("mbarrier::arrive::one.b64"));
-        assert!(!base_commit_probe.contains("one.shared::cluster.b64"));
-
-        let shared_commit = tcgen05_intrinsics(&catalog)
-            .find(|record| record.id == "tcgen05_commit_shared_cluster")
-            .unwrap();
-        let shared_commit_probe = render_probe(&catalog, shared_commit, "test-hash");
-        assert!(shared_commit_probe.contains("one.shared::cluster.b64"));
-
-        for (id, spelling) in [
-            (
-                "tcgen05_commit_multicast",
-                "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;",
-            ),
-            (
-                "tcgen05_shift_down",
-                "tcgen05.shift.cta_group::1.down [$0];",
-            ),
-            (
-                "tcgen05_shift_down_cg2",
-                "tcgen05.shift.cta_group::2.down [$0];",
-            ),
-        ] {
-            let record = tcgen05_intrinsics(&catalog)
-                .find(|record| record.id == id)
-                .unwrap();
-            let probe = render_probe(&catalog, record, "test-hash");
-            assert!(probe.contains(spelling));
-            assert!(probe.contains("asm sideeffect"));
-            assert!(probe.contains("attributes #0 = { convergent }"));
-        }
-
-        for (id, spelling) in [
-            (
-                "tcgen05_cp_128x128b_b4x16_p64",
-                "tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64",
-            ),
-            (
-                "tcgen05_cp_32x128b_warpx4",
-                "tcgen05.cp.cta_group::1.32x128b.warpx4",
-            ),
-            (
-                "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2",
-                "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32",
-            ),
-            (
-                "tcgen05_cp_64x128b_warpx2_02_13",
-                "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13",
-            ),
-        ] {
-            let record = tcgen05_intrinsics(&catalog)
-                .find(|record| record.id == id)
-                .unwrap();
-            let probe = render_probe(&catalog, record, "test-hash");
-            assert!(probe.contains(spelling));
-            assert!(probe.contains("asm sideeffect"));
-            assert!(probe.contains("\"r,l,~{memory}\""));
-            assert!(probe.contains("attributes #0 = { convergent }"));
-        }
-
-        let scalar_load = tcgen05_intrinsics(&catalog)
-            .find(|record| record.id == "tcgen05_ld_16x64b_x1_raw")
-            .unwrap();
-        let scalar_load_probe = render_probe(&catalog, scalar_load, "test-hash");
-        assert!(scalar_load_probe.contains("%result = call i32 asm sideeffect"));
-        assert!(scalar_load_probe.contains("tcgen05.ld.sync.aligned.16x64b.x1.b32"));
-        assert!(scalar_load_probe.contains("\"=r,r,~{memory}\""));
-
-        let packed_load = tcgen05_intrinsics(&catalog)
-            .find(|record| record.id == "tcgen05_ld_32x32b_x128_pack16")
-            .unwrap();
-        let packed_load_probe = render_probe(&catalog, packed_load, "test-hash");
-        assert!(packed_load_probe.contains("tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32"));
-        assert!(packed_load_probe.contains("{ i32, i32"));
-
-        let scalar_store = tcgen05_intrinsics(&catalog)
-            .find(|record| record.id == "tcgen05_st_16x64b_x1_raw")
-            .unwrap();
-        let scalar_store_probe = render_probe(&catalog, scalar_store, "test-hash");
-        assert!(scalar_store_probe.contains("call void asm sideeffect"));
-        assert!(scalar_store_probe.contains("tcgen05.st.sync.aligned.16x64b.x1.b32"));
-        assert!(scalar_store_probe.contains("\"r,r,~{memory}\""));
-
-        let unpacked_store = tcgen05_intrinsics(&catalog)
-            .find(|record| record.id == "tcgen05_st_32x32b_x128_unpack16")
-            .unwrap();
-        let unpacked_store_probe = render_probe(&catalog, unpacked_store, "test-hash");
-        assert!(
-            unpacked_store_probe.contains("tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32")
-        );
-        assert!(unpacked_store_probe.contains("i32 %d127"));
-
-        let offset_load = tcgen05_intrinsics(&catalog)
-            .find(|record| record.id == "tcgen05_ld_16x32bx2_x1_pack16")
-            .unwrap();
-        let offset_load_probe = render_probe(&catalog, offset_load, "test-hash");
-        assert!(offset_load_probe.contains("i64 16"));
-        assert!(offset_load_probe.contains("[$1], $2;"));
-        assert!(offset_load_probe.contains("\"=r,r,n,~{memory}\""));
-
-        let offset_store = tcgen05_intrinsics(&catalog)
-            .find(|record| record.id == "tcgen05_st_16x32bx2_x1_unpack16")
-            .unwrap();
-        let offset_store_probe = render_probe(&catalog, offset_store, "test-hash");
-        assert!(offset_store_probe.contains("i64 16"));
-        assert!(offset_store_probe.contains("[$0], $1, {$2};"));
-        assert!(offset_store_probe.contains("\"r,n,r,~{memory}\""));
-
-        let target = render_targets(&catalog, "test-hash");
-        assert!(target.contains("\"v1:i0343\""));
-        assert!(target.contains("\"v1:i0578\""));
-        assert!(target.contains("\"v1:i0611\""));
-        assert!(target.contains("\"v1:i0727\""));
-        assert!(target.contains("\"v1:i0728\""));
-        assert!(target.contains("\"v1:i0759\""));
-        assert!(target.contains(
-            "Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr, Tcgen05MmaFormAttr"
-        ));
-        assert!(target.contains(
-            "GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(100), GeneratedHardwareAlternative::ExactArchitecture(101), GeneratedHardwareAlternative::ExactArchitecture(103), GeneratedHardwareAlternative::ExactArchitecture(110)])"
-        ));
-        assert!(target.contains(
-            "GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(100), GeneratedHardwareAlternative::ExactArchitecture(103), GeneratedHardwareAlternative::ExactArchitecture(110)])"
-        ));
-
-        let reference = render_reference(&catalog, "test-hash");
-        assert!(reference.contains("- `tcgen05_st_16x64b_x1_raw`: runtime `unexecuted`"));
-        assert!(!reference.contains("- `tcgen05_st_16x64b_x1_raw`: runtime `not recorded`"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/tcgen05.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/tcgen05.rs"
-        )));
-
-        let mut wrong_adapter = catalog.clone();
-        wrong_adapter
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "tcgen05_alloc")
-            .unwrap()
-            .tcgen05
-            .as_mut()
-            .unwrap()
-            .adapter = Tcgen05Adapter::NoOperands;
-        assert!(validate_renderable(&wrong_adapter).is_err());
-
-        let mut wrong_libnvvm_target = catalog.clone();
-        wrong_libnvvm_target
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "tcgen05_cp_128x128b_b4x16_p64")
-            .unwrap()
-            .backend_lowerings[1]
-            .target
-            .hardware = CatalogHardwareTarget::AnyOf {
-            alternatives: vec![
-                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-            ],
-        };
-        assert!(validate_renderable(&wrong_libnvvm_target).is_err());
-
-        let mut wrong_load_selector = catalog.clone();
-        wrong_load_selector
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "tcgen05_ld_16x64b_x1_pack16")
-            .unwrap()
-            .expected_ptx
-            .modifiers
-            .remove(5);
-        assert!(validate_renderable(&wrong_load_selector).is_err());
-
-        let mut wrong_store_selector = catalog.clone();
-        wrong_store_selector
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "tcgen05_st_16x64b_x1_unpack16")
-            .unwrap()
-            .expected_ptx
-            .modifiers
-            .remove(5);
-        assert!(validate_renderable(&wrong_store_selector).is_err());
-
-        let mut wrong_offset_scope = catalog.clone();
-        wrong_offset_scope
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "tcgen05_ld_16x32bx2_x1_raw")
-            .unwrap()
-            .semantics
-            .execution_scope = "thread".into();
-        assert!(validate_renderable(&wrong_offset_scope).is_err());
-
-        let mut wrong_copy_spelling = catalog;
-        wrong_copy_spelling
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "tcgen05_cp_128x128b_b4x16_p64")
-            .unwrap()
-            .expected_ptx
-            .modifiers
-            .remove(3);
-        assert!(validate_renderable(&wrong_copy_spelling).is_err());
-    }
-
-    #[test]
-    fn debug_control_rendering_preserves_api_immediates_and_side_effects() {
-        let catalog = catalog_with_debug_controls();
-        validate_renderable(&catalog).unwrap();
-        assert_eq!(debug_controls(&catalog).count(), 3);
-
-        let compatibility = render_compat_debug_control(&catalog, "test-hash");
-        assert!(compatibility.contains("pub fn trap() -> !"));
-        assert!(compatibility.contains("pub fn breakpoint()"));
-        assert!(compatibility.contains("pub fn prof_trigger<const N: u32>()"));
-        assert!(compatibility.contains("pub(crate) fn __prof_trigger(_event_id: u32)"));
-        assert!(compatibility.contains("__prof_trigger(N);"));
-
-        let dialect = render_dialect_debug_control(&catalog, "test-hash");
-        for op in ["TrapOp", "BreakpointOp", "PmEventOp"] {
-            assert_eq!(dialect.matches(&format!("pub struct {op}")).count(), 1);
-            assert!(dialect.contains(&format!("{op}::register(ctx)")));
-        }
-        assert!(dialect.contains("event_id: u32"));
-        assert!(dialect.contains("pub fn new_with_event_id"));
-        assert!(dialect.contains("pub fn get_event_id"));
-        assert!(dialect.contains("filter(|value| *value <= 15)"));
-        assert!(dialect.contains("requires a u32 event ID in 0..=15"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert!(importer.contains("cuda_device::debug::__prof_trigger"));
-        assert!(importer.contains("mir::Operand::Constant"));
-        assert!(importer.contains("u32::try_from(value)"));
-        assert!(importer.contains("filter(|value| *value <= 15)"));
-        assert!(importer.contains("PmEventOp::build(ctx, event_id)"));
-        assert!(importer.contains("MirUnreachableOp::get_concrete_op_info()"));
-        assert!(
-            importer.contains("prof_trigger requires a compile-time constant event ID in 0..=15")
-        );
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        for op in ["TrapOp", "BreakpointOp", "PmEventOp"] {
-            assert!(lowering.contains(&format!("impl MirToLlvmConversion for {op}")));
-        }
-        assert!(lowering.contains(
-            "inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], \"trap;\", \"\")"
-        ));
-        assert!(lowering.contains(
-            "inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], \"brkpt;\", \"\")"
-        ));
-        assert!(lowering.contains("let template = format!(\"pmevent {event_id};\")"));
-
-        for record in debug_controls(&catalog) {
-            let probe = render_probe(&catalog, record, "test-hash");
-            assert!(probe.contains("call void asm sideeffect"));
-            assert!(!probe.contains("attributes #0 = { convergent }"));
-        }
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/cuda-device/src/generated/debug_control.rs"
-        )));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/debug_control.rs"
-        )));
-
-        let mut wrong_adapter = catalog.clone();
-        wrong_adapter
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "pmevent")
-            .unwrap()
-            .debug_control
-            .as_mut()
-            .unwrap()
-            .adapter = DebugControlAdapter::Direct;
-        assert!(validate_renderable(&wrong_adapter).is_err());
-
-        let mut wrong_runtime = catalog;
-        wrong_runtime
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "trap")
-            .unwrap()
-            .debug_control
-            .as_mut()
-            .unwrap()
-            .runtime_validation = RuntimeValidation::Executed;
-        assert!(validate_renderable(&wrong_runtime).is_err());
-    }
-
-    #[test]
-    fn scalar_arithmetic_rendering_uses_one_closed_carrier() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        let records = scalar_arithmetics(&catalog).collect::<Vec<_>>();
-        assert_eq!(records.len(), 64);
-        assert!(records.iter().all(|record| {
-            record.semantics.pure
-                == (record.scalar_arithmetic.as_ref().unwrap().operation
-                    != ScalarArithmeticOperation::Div)
-        }));
-
-        let compatibility = render_compat_float(&catalog, "test-hash");
-        assert!(compatibility.contains("pub fn mul_rn_f64(arg0: f64, arg1: f64) -> f64"));
-        assert!(
-            compatibility
-                .contains("pub fn fma_rp_ftz_sat_f32(arg0: f32, arg1: f32, arg2: f32) -> f32")
-        );
-        assert!(compatibility.contains("pub fn add_rp_ftz_sat_f32(arg0: f32, arg1: f32) -> f32"));
-        assert_eq!(compatibility.matches("#[must_use]").count(), 113);
-
-        let dialect = render_dialect_scalar_arithmetic(&catalog, "test-hash");
-        assert_eq!(dialect.matches("pub struct ScalarArithmeticOp").count(), 1);
-        for attr in [
-            "ScalarArithmeticFormatAttr",
-            "ScalarArithmeticOperationAttr",
-            "ScalarArithmeticRoundingAttr",
-            "ScalarArithmeticSubnormalAttr",
-            "ScalarArithmeticSaturationAttr",
-        ] {
-            assert!(dialect.contains(attr));
-            assert!(dialect.contains(&format!("{attr}::register(ctx)")));
-        }
-        assert!(dialect.contains("variant is not admitted"));
-        assert!(dialect.contains("ScalarArithmeticOperationAttr::Fma => 3"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert_eq!(
-            importer.matches("ScalarArithmeticOp::build(ctx").count(),
-            64
-        );
-        assert!(importer.contains("cuda_device::float::fma_rp_ftz_sat_f32"));
-        assert!(importer.contains("cuda_device::float::add_rp_ftz_sat_f32"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert_eq!(
-            lowering
-                .matches("impl MirToLlvmConversion for ScalarArithmeticOp")
-                .count(),
-            1
-        );
-        assert!(lowering.contains("llvm_nvvm_mul_rn_d"));
-        assert!(lowering.contains("fma.rp.ftz.sat.f32"));
-        assert!(lowering.contains("llvm_nvvm_add_rn_d"));
-        assert!(lowering.contains("add.rp.sat.ftz.f32"));
-        assert!(lowering.contains("recipe.0, recipe.1, recipe.2, recipe.3"));
-
-        let targets = render_targets(&catalog, "test-hash");
-        assert!(targets.contains("GeneratedIntrinsicVariant::ScalarArithmetic"));
-        assert!(targets.contains("GeneratedScalarArithmeticFormat::F64"));
-        assert!(targets.contains("GeneratedScalarArithmeticSaturation::Sat"));
-        assert!(targets.contains("Operation::get_op::<ScalarArithmeticOp>"));
-
-        let f64_mul = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mul_rn_f64")
-            .unwrap();
-        let f64_probe = render_probe(&catalog, f64_mul, "test-hash");
-        assert!(f64_probe.contains("declare double @llvm.nvvm.mul.rn.d(double, double)"));
-        let f32_sat = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "fma_rp_ftz_sat_f32")
-            .unwrap();
-        let f32_probe = render_probe(&catalog, f32_sat, "test-hash");
-        assert!(
-            f32_probe
-                .contains("call float asm \"fma.rp.ftz.sat.f32 $0, $1, $2, $3;\", \"=f,f,f,f\"")
-        );
-        assert!(!f32_probe.contains("@llvm.nvvm.fma.rp.ftz.sat.f"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/float.rs")));
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs"
-        )));
-    }
-
-    #[test]
-    fn extended_minmax_rendering_is_closed_pure_and_exact() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        validate_renderable(&catalog).unwrap();
-        let records = extended_minmax(&catalog).collect::<Vec<_>>();
-        assert_eq!(records.len(), 52);
-        assert_eq!(
-            records
-                .iter()
-                .filter(|record| record.target.minimum_ptx.encoded() == 70)
-                .count(),
-            20
-        );
-        assert_eq!(
-            records
-                .iter()
-                .filter(|record| record.target.minimum_ptx.encoded() == 72)
-                .count(),
-            32
-        );
-        for id in ["min_f16x2", "max_f16x2", "min_bf16x2", "max_bf16x2"] {
-            assert_eq!(
-                catalog
-                    .intrinsics
-                    .iter()
-                    .find(|record| record.id == id)
-                    .unwrap()
-                    .family,
-                "packed_alu"
-            );
-            assert!(records.iter().all(|record| record.id != id));
-        }
-
-        let f16 = render_compat_packed_alu(&catalog, "test-hash", PackedAluFormat::F16x2);
-        assert!(f16.contains("pub fn min_ftz_nan_xorsign_abs_f16x2(a: u32, b: u32) -> u32"));
-        let bf16 = render_compat_packed_alu(&catalog, "test-hash", PackedAluFormat::Bf16x2);
-        assert!(bf16.contains("pub fn max_nan_xorsign_abs_bf16x2(a: u32, b: u32) -> u32"));
-        let float = render_compat_float(&catalog, "test-hash");
-        assert!(float.contains("pub fn min_ftz_nan_xorsign_abs_f32(a: f32, b: f32) -> f32"));
-
-        let dialect = render_dialect_extended_minmax(&catalog, "test-hash");
-        assert_eq!(dialect.matches("pub struct ExtendedMinMaxOp").count(), 1);
-        assert_eq!(
-            dialect
-                .matches("            (ExtendedMinMaxFormatAttr::")
-                .count(),
-            52
-        );
-        for attr in [
-            "ExtendedMinMaxFormatAttr",
-            "ExtendedMinMaxOperationAttr",
-            "ExtendedMinMaxSubnormalAttr",
-            "ExtendedMinMaxNanAttr",
-            "ExtendedMinMaxXorSignAbsAttr",
-        ] {
-            assert!(dialect.contains(attr));
-            assert!(dialect.contains(&format!("{attr}::register(ctx)")));
-        }
-        assert!(dialect.contains("variant is not admitted"));
-
-        let importer = render_importer(&catalog, "test-hash");
-        assert_eq!(importer.matches("ExtendedMinMaxOp::build(ctx").count(), 52);
-        assert!(importer.contains("cuda_device::float::min_xorsign_abs_f32"));
-        assert!(importer.contains("cuda_device::bf16x2::max_nan_bf16x2"));
-
-        let lowering = render_lowering(&catalog, "test-hash");
-        assert_eq!(
-            lowering
-                .matches("impl MirToLlvmConversion for ExtendedMinMaxOp")
-                .count(),
-            1
-        );
-        assert!(lowering.contains("convert_generated_extended_minmax"));
-        assert!(lowering.contains("min.ftz.NaN.xorsign.abs.f32"));
-        assert!(lowering.contains("max.NaN.xorsign.abs.bf16x2"));
-
-        let targets = render_targets(&catalog, "test-hash");
-        assert!(targets.contains("GeneratedIntrinsicVariant::ExtendedMinMax"));
-        assert!(targets.contains("GeneratedPtxVersion::from_encoded(72)"));
-        assert!(targets.contains("Operation::get_op::<ExtendedMinMaxOp>"));
-        assert!(targets.contains("ExtendedMinMaxXorSignAbsAttr::Enabled"));
-
-        let packed_record = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "min_ftz_nan_f16x2")
-            .unwrap();
-        let packed_probe = render_probe(&catalog, packed_record, "test-hash");
-        assert!(
-            packed_probe.contains("call i32 asm \"min.ftz.NaN.f16x2 $0, $1, $2;\", \"=r,r,r\"")
-        );
-        assert!(!packed_probe.contains("sideeffect"));
-        assert!(!packed_probe.contains("convergent"));
-        let f32_record = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "max_ftz_nan_xorsign_abs_f32")
-            .unwrap();
-        let f32_probe = render_probe(&catalog, f32_record, "test-hash");
-        assert!(
-            f32_probe
-                .contains("call float asm \"max.ftz.NaN.xorsign.abs.f32 $0, $1, $2;\", \"=f,f,f\"")
-        );
-        // Scalar 16-bit forms ride in `h` registers, not the packed `r` pair.
-        let half_record = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "min_ftz_nan_f16")
-            .unwrap();
-        let half_probe = render_probe(&catalog, half_record, "test-hash");
-        assert!(half_probe.contains("call i16 asm \"min.ftz.NaN.f16 $0, $1, $2;\", \"=h,h,h\""));
-        let bf16_record = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "max_nan_xorsign_abs_bf16")
-            .unwrap();
-        let bf16_probe = render_probe(&catalog, bf16_record, "test-hash");
-        assert!(
-            bf16_probe
-                .contains("call i16 asm \"max.NaN.xorsign.abs.bf16 $0, $1, $2;\", \"=h,h,h\"")
-        );
-        assert!(lowering.contains("MinMaxCarrier::Half16"));
-
-        let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
-        assert!(outputs.contains_key(&PathBuf::from(
-            "crates/dialect-nvvm/src/ops/generated/extended_minmax.rs"
-        )));
-        for module in ["float", "f16", "bf16", "f16x2", "bf16x2"] {
-            assert!(outputs.contains_key(&PathBuf::from(format!(
-                "crates/cuda-device/src/generated/{module}.rs"
-            ))));
-        }
-
-        let mut wrong_adapter = catalog;
-        wrong_adapter
-            .intrinsics
-            .iter_mut()
-            .find(|record| record.id == "min_xorsign_abs_f32")
-            .unwrap()
-            .extended_minmax
-            .as_mut()
-            .unwrap()
-            .adapter = ExtendedMinMaxAdapter::DirectPackedU32;
-        assert!(validate_renderable(&wrong_adapter).is_err());
-    }
-
-    #[test]
-    fn extended_minmax_alone_renders_float_wrappers() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let mut catalog = crate::resolve::resolve(&repo_root).unwrap();
-        catalog
-            .intrinsics
-            .retain(|record| record.family == "extended_minmax");
-
-        let (path, float) = render_compat_float_output(&catalog, "test-hash")
-            .expect("extended min/max alone must render float wrappers");
-        assert_eq!(
-            path,
-            PathBuf::from("crates/cuda-device/src/generated/float.rs")
-        );
-        assert!(float.contains("pub fn min_xorsign_abs_f32(a: f32, b: f32) -> f32"));
-        assert!(!float.contains("pub fn add_rn_f32"));
-    }
-
-    /// Every reference row must carry exactly the six cells of its header.
-    ///
-    /// A `|` in cell data splits the row before inline parsing, so it splits
-    /// the cell even inside a code span. Three catalog entries write a PTX
-    /// destination pair as `<register|predicate>`, and their rows rendered with
-    /// a seventh cell, which drops the backend-evidence column. Counting
-    /// unescaped pipes per row is the direct check.
-    #[test]
-    fn reference_rows_have_one_cell_per_header_column() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = crate::resolve::resolve(&repo_root).unwrap();
-        let reference = render_reference(&catalog, "test-hash");
-
-        let mut rows = 0usize;
-        let mut carried_a_pipe = 0usize;
-        for line in reference
-            .lines()
-            .filter(|line| line.starts_with("| `cuda_intrinsics::"))
-        {
-            rows += 1;
-            if line.contains("\\|") {
-                carried_a_pipe += 1;
-            }
-            // Delimiters only: drop every escaped pipe first, then a six-column
-            // row leaves seven.
-            let delimiters = line.replace("\\|", "").matches('|').count();
-            assert_eq!(
-                delimiters, 7,
-                "row has {delimiters} cell delimiters, expected 7: {line}"
-            );
-        }
-
-        assert!(
-            rows > 900,
-            "expected the full reference, rendered {rows} rows"
-        );
-        assert!(
-            carried_a_pipe >= 3,
-            "expected the elect.sync and match.all.sync patterns to need escaping, \
-             found {carried_a_pipe} rows with an escaped pipe"
-        );
-    }
-}
diff --git a/crates/cuda-intrinsics-gen/src/render/collector_targets.rs b/crates/cuda-intrinsics-gen/src/render/collector_targets.rs
new file mode 100644
index 0000000000..de065ddffb
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/collector_targets.rs
@@ -0,0 +1,1238 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    CatalogFile, CatalogIntrinsic, CatalogSelection, ClusterBarrierMode, ExtendedMinMaxFormat,
+    ExtendedMinMaxNan, ExtendedMinMaxOperation, ExtendedMinMaxSubnormal, ImportedAddressSpace,
+    IntrinsicBackend, LdmatrixElement, LdmatrixLayout, LdmatrixMultiplicity, LdmatrixShape,
+    PackedAtomicFormat, PrmtMode, RegisterMmaAccumulator, RegisterMmaElement, RegisterMmaKind,
+    RegisterMmaLayout, RegisterMmaOperation, RegisterMmaOverflow, RegisterMmaShape,
+    ScalarArithmeticFormat, ScalarArithmeticOperation, ScalarArithmeticRounding,
+    ScalarArithmeticSaturation, ScalarArithmeticSubnormal, ScalarConversionRounding,
+    ScalarConversionSaturation, SparseMmaAccumulator, SparseMmaElement, SparseMmaLayout,
+    SparseMmaMetadata, SparseMmaOverflow, SparseMmaSelector, SparseMmaShape, WgmmaControlMode,
+};
+use crate::render::common::{
+    generated_hardware_target, intrinsic_marker, rust_header, uses_identifier,
+};
+use crate::render::families::{
+    extended_minmax, ldmatrix, ldmatrix_compat_op, register_mma_effective_kind, scalar_arithmetics,
+    scalar_conversions, tcgen05_mma_form_name, tcgen05_mma_intrinsics, wgmma_controls,
+};
+use crate::render::reference::render_string_patterns;
+use std::fmt::Write as _;
+use std::path::PathBuf;
+
+pub(super) fn render_collector(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    let abi_namespace = format!("__cuda_oxide_intrinsic_abi_v{}", catalog.intrinsic_abi);
+    output.push_str("//! Generated collector predicates for intrinsic placeholder functions.\n\n");
+    writeln!(
+        output,
+        "pub(crate) const GENERATED_INTRINSIC_ABI: u32 = {};",
+        catalog.intrinsic_abi
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "pub(crate) const GENERATED_INTRINSIC_ABI_NAMESPACE: &str = {abi_namespace:?};"
+    )
+    .unwrap();
+    output.push_str(
+        "pub(crate) const GENERATED_INTRINSIC_CRATES: &[&str] = &[\n    \"cuda_intrinsics\",\n    \"cuda-intrinsics\",\n];\n\npub(crate) const GENERATED_INTRINSIC_CANONICAL_PATHS: &[&str] = &[\n",
+    );
+    for record in &catalog.intrinsics {
+        writeln!(output, "    {:?},", record.rust.canonical_path).unwrap();
+    }
+    output.push_str("];\n\npub(crate) const GENERATED_INTRINSIC_PUBLIC_PATHS: &[&str] = &[\n");
+    for record in &catalog.intrinsics {
+        writeln!(output, "    {:?},", record.rust.public_path).unwrap();
+    }
+    output.push_str("];\n\npub(crate) fn is_generated_intrinsic_crate(crate_name: &str) -> bool {\n    GENERATED_INTRINSIC_CRATES.contains(&crate_name)\n}\n\npub(crate) fn is_generated_intrinsic_canonical_path(path: &str) -> bool {\n    matches!(path,\n");
+    let canonical_paths: Vec<_> = catalog
+        .intrinsics
+        .iter()
+        .map(|record| record.rust.canonical_path.as_str())
+        .collect();
+    render_string_patterns(&mut output, &canonical_paths, "        ");
+    output.push_str("    )\n}\n\npub(crate) fn is_generated_intrinsic_compatibility_path(path: &str) -> bool {\n");
+    let compatibility_paths: Vec<_> = catalog
+        .intrinsics
+        .iter()
+        .flat_map(|record| record.rust.compatibility_paths.iter().map(String::as_str))
+        .collect();
+    if compatibility_paths.is_empty() {
+        output.push_str("    let _ = path;\n    false\n");
+    } else {
+        output.push_str("    matches!(path,\n");
+        render_string_patterns(&mut output, &compatibility_paths, "        ");
+        output.push_str("    )\n");
+    }
+    output.push_str(
+        "}\n\npub(crate) fn is_generated_intrinsic_placeholder(crate_name: &str, path: &str) -> bool {\n    if is_generated_intrinsic_crate(crate_name) {\n        is_generated_intrinsic_canonical_path(path)\n    } else if matches!(crate_name, \"cuda_device\" | \"cuda-device\") {\n        is_generated_intrinsic_compatibility_path(path)\n    } else {\n        false\n    }\n}\n",
+    );
+    output
+}
+
+fn generated_selection_constraints(selection: &CatalogSelection) -> String {
+    let address_space = match selection.constraints.address_space {
+        None => "None",
+        Some(ImportedAddressSpace::Generic) => "Some(GeneratedSelectionAddressSpace::Generic)",
+        Some(ImportedAddressSpace::Shared) => "Some(GeneratedSelectionAddressSpace::Shared)",
+    };
+    let immediate_bindings = selection
+        .constraints
+        .immediate_bindings
+        .iter()
+        .map(|binding| {
+            format!(
+                "GeneratedImmediateBinding {{ argument_index: {}, value: {} }}",
+                binding.argument_index, binding.value
+            )
+        })
+        .collect::<Vec<_>>()
+        .join(", ");
+    format!(
+        "GeneratedSelectionConstraints {{ address_space: {address_space}, immediate_bindings: &[{immediate_bindings}] }}"
+    )
+}
+
+pub(super) fn generated_selection_alternatives(selections: &[CatalogSelection]) -> String {
+    let mut output = String::from("&[");
+    for selection in selections {
+        write!(
+            output,
+            "GeneratedSelectionAlternative {{ source_record: {:?}, asm: {:?}, predicates: &{:?}, constraints: {} }},",
+            selection.source_record,
+            selection.asm,
+            selection.predicates,
+            generated_selection_constraints(selection),
+        )
+        .unwrap();
+    }
+    output.push(']');
+    output
+}
+
+pub(super) fn generated_intrinsic_variant(record: &CatalogIntrinsic) -> String {
+    if let Some(mma) = record
+        .tcgen05
+        .as_ref()
+        .and_then(|tcgen05| tcgen05.mma.as_ref())
+    {
+        return format!(
+            "GeneratedIntrinsicVariant::Tcgen05Mma {{ form: GeneratedTcgen05MmaForm::{}, target_selector: GeneratedTcgen05MmaTargetSelector::Kind, compatibility_alias: {} }}",
+            tcgen05_mma_form_name(mma.form),
+            mma.alias.is_some(),
+        );
+    }
+    if let Some(control) = &record.wgmma_control {
+        let mode = match control.mode {
+            WgmmaControlMode::Fence => "GeneratedWgmmaControlMode::Fence",
+            WgmmaControlMode::CommitGroup => "GeneratedWgmmaControlMode::CommitGroup",
+            WgmmaControlMode::WaitGroup => "GeneratedWgmmaControlMode::WaitGroup",
+        };
+        return format!("GeneratedIntrinsicVariant::WgmmaControl {{ mode: {mode} }}");
+    }
+    if let Some(barrier) = &record.cluster_barrier {
+        let mode = match barrier.mode {
+            ClusterBarrierMode::Arrive => "GeneratedClusterBarrierMode::Arrive",
+            ClusterBarrierMode::ArriveAligned => "GeneratedClusterBarrierMode::ArriveAligned",
+            ClusterBarrierMode::ArriveRelaxed => "GeneratedClusterBarrierMode::ArriveRelaxed",
+            ClusterBarrierMode::ArriveRelaxedAligned => {
+                "GeneratedClusterBarrierMode::ArriveRelaxedAligned"
+            }
+            ClusterBarrierMode::Wait => "GeneratedClusterBarrierMode::Wait",
+            ClusterBarrierMode::WaitAligned => "GeneratedClusterBarrierMode::WaitAligned",
+        };
+        return format!("GeneratedIntrinsicVariant::ClusterBarrier {{ mode: {mode} }}");
+    }
+    if let Some(prmt) = &record.prmt {
+        let mode = match prmt.mode {
+            PrmtMode::Generic => "GeneratedPrmtMode::Generic",
+            PrmtMode::F4e => "GeneratedPrmtMode::F4e",
+            PrmtMode::B4e => "GeneratedPrmtMode::B4e",
+            PrmtMode::Rc8 => "GeneratedPrmtMode::Rc8",
+            PrmtMode::Ecl => "GeneratedPrmtMode::Ecl",
+            PrmtMode::Ecr => "GeneratedPrmtMode::Ecr",
+            PrmtMode::Rc16 => "GeneratedPrmtMode::Rc16",
+        };
+        return format!("GeneratedIntrinsicVariant::Prmt {{ mode: {mode} }}");
+    }
+    if let Some(packed) = &record.packed_atomic {
+        let format = match packed.format {
+            PackedAtomicFormat::F16x2 => "GeneratedPackedAtomicFormat::F16x2",
+            PackedAtomicFormat::Bf16x2 => "GeneratedPackedAtomicFormat::Bf16x2",
+        };
+        return format!("GeneratedIntrinsicVariant::PackedAtomic {{ format: {format} }}");
+    }
+    if let Some(mma) = &record.register_mma {
+        let shape = match mma.shape {
+            RegisterMmaShape::M8n8k4 => "GeneratedRegisterMmaShape::M8n8k4",
+            RegisterMmaShape::M8n8k16 => "GeneratedRegisterMmaShape::M8n8k16",
+            RegisterMmaShape::M8n8k32 => "GeneratedRegisterMmaShape::M8n8k32",
+            RegisterMmaShape::M8n8k128 => "GeneratedRegisterMmaShape::M8n8k128",
+            RegisterMmaShape::M16n8k4 => "GeneratedRegisterMmaShape::M16n8k4",
+            RegisterMmaShape::M16n8k8 => "GeneratedRegisterMmaShape::M16n8k8",
+            RegisterMmaShape::M16n8k16 => "GeneratedRegisterMmaShape::M16n8k16",
+            RegisterMmaShape::M16n8k32 => "GeneratedRegisterMmaShape::M16n8k32",
+            RegisterMmaShape::M16n8k64 => "GeneratedRegisterMmaShape::M16n8k64",
+            RegisterMmaShape::M16n8k128 => "GeneratedRegisterMmaShape::M16n8k128",
+            RegisterMmaShape::M16n8k256 => "GeneratedRegisterMmaShape::M16n8k256",
+        };
+        let operation = match mma.operation {
+            RegisterMmaOperation::Multiply => "GeneratedRegisterMmaOperation::Multiply",
+            RegisterMmaOperation::AndPopc => "GeneratedRegisterMmaOperation::AndPopc",
+            RegisterMmaOperation::XorPopc => "GeneratedRegisterMmaOperation::XorPopc",
+        };
+        let kind = match register_mma_effective_kind(record) {
+            RegisterMmaKind::Standard => "GeneratedRegisterMmaKind::Standard",
+            RegisterMmaKind::F8f6f4 => "GeneratedRegisterMmaKind::F8f6f4",
+            RegisterMmaKind::Mxf8f6f4 => "GeneratedRegisterMmaKind::Mxf8f6f4",
+        };
+        let accumulator = match mma.accumulator {
+            RegisterMmaAccumulator::F16 => "GeneratedRegisterMmaAccumulator::F16",
+            RegisterMmaAccumulator::F32 => "GeneratedRegisterMmaAccumulator::F32",
+            RegisterMmaAccumulator::F64 => "GeneratedRegisterMmaAccumulator::F64",
+            RegisterMmaAccumulator::S32 => "GeneratedRegisterMmaAccumulator::S32",
+        };
+        let element = |element| match element {
+            RegisterMmaElement::Bf16 => "GeneratedRegisterMmaElement::Bf16",
+            RegisterMmaElement::E2m1 => "GeneratedRegisterMmaElement::E2m1",
+            RegisterMmaElement::E2m3 => "GeneratedRegisterMmaElement::E2m3",
+            RegisterMmaElement::E3m2 => "GeneratedRegisterMmaElement::E3m2",
+            RegisterMmaElement::E4m3 => "GeneratedRegisterMmaElement::E4m3",
+            RegisterMmaElement::E5m2 => "GeneratedRegisterMmaElement::E5m2",
+            RegisterMmaElement::F16 => "GeneratedRegisterMmaElement::F16",
+            RegisterMmaElement::Tf32 => "GeneratedRegisterMmaElement::Tf32",
+            RegisterMmaElement::F64 => "GeneratedRegisterMmaElement::F64",
+            RegisterMmaElement::B1 => "GeneratedRegisterMmaElement::B1",
+            RegisterMmaElement::S4 => "GeneratedRegisterMmaElement::S4",
+            RegisterMmaElement::U4 => "GeneratedRegisterMmaElement::U4",
+            RegisterMmaElement::S8 => "GeneratedRegisterMmaElement::S8",
+            RegisterMmaElement::U8 => "GeneratedRegisterMmaElement::U8",
+        };
+        let layout = |layout| match layout {
+            RegisterMmaLayout::Row => "GeneratedRegisterMmaLayout::Row",
+            RegisterMmaLayout::Col => "GeneratedRegisterMmaLayout::Col",
+        };
+        let overflow = match mma.overflow {
+            RegisterMmaOverflow::NotApplicable => "GeneratedRegisterMmaOverflow::NotApplicable",
+            RegisterMmaOverflow::Wrapping => "GeneratedRegisterMmaOverflow::Wrapping",
+            RegisterMmaOverflow::Satfinite => "GeneratedRegisterMmaOverflow::Satfinite",
+        };
+        return format!(
+            "GeneratedIntrinsicVariant::RegisterMma {{ shape: {shape}, operation: {operation}, kind: {kind}, accumulator: {accumulator}, a_element: {}, b_element: {}, a_layout: {}, b_layout: {}, overflow: {overflow} }}",
+            element(mma.a_element),
+            element(mma.b_element),
+            layout(mma.a_layout),
+            layout(mma.b_layout),
+        );
+    }
+    if let Some(mma) = &record.sparse_mma {
+        let shape = match mma.shape {
+            SparseMmaShape::M16n8k32 => "GeneratedSparseMmaShape::M16n8k32",
+            SparseMmaShape::M16n8k64 => "GeneratedSparseMmaShape::M16n8k64",
+            SparseMmaShape::M16n8k128 => "GeneratedSparseMmaShape::M16n8k128",
+        };
+        let accumulator = match mma.accumulator {
+            SparseMmaAccumulator::F16 => "GeneratedSparseMmaAccumulator::F16",
+            SparseMmaAccumulator::F32 => "GeneratedSparseMmaAccumulator::F32",
+            SparseMmaAccumulator::S32 => "GeneratedSparseMmaAccumulator::S32",
+        };
+        let element = |element| match element {
+            SparseMmaElement::E2m1 => "GeneratedSparseMmaElement::E2m1",
+            SparseMmaElement::E2m3 => "GeneratedSparseMmaElement::E2m3",
+            SparseMmaElement::E3m2 => "GeneratedSparseMmaElement::E3m2",
+            SparseMmaElement::E4m3 => "GeneratedSparseMmaElement::E4m3",
+            SparseMmaElement::E5m2 => "GeneratedSparseMmaElement::E5m2",
+            SparseMmaElement::S4 => "GeneratedSparseMmaElement::S4",
+            SparseMmaElement::U4 => "GeneratedSparseMmaElement::U4",
+            SparseMmaElement::S8 => "GeneratedSparseMmaElement::S8",
+            SparseMmaElement::U8 => "GeneratedSparseMmaElement::U8",
+        };
+        let layout = |layout| match layout {
+            SparseMmaLayout::Row => "GeneratedSparseMmaLayout::Row",
+            SparseMmaLayout::Col => "GeneratedSparseMmaLayout::Col",
+        };
+        let overflow = match mma.overflow {
+            SparseMmaOverflow::NotApplicable => "GeneratedSparseMmaOverflow::NotApplicable",
+            SparseMmaOverflow::Wrapping => "GeneratedSparseMmaOverflow::Wrapping",
+            SparseMmaOverflow::Satfinite => "GeneratedSparseMmaOverflow::Satfinite",
+        };
+        let metadata = match mma.metadata {
+            SparseMmaMetadata::Standard => "GeneratedSparseMmaMetadata::Standard",
+            SparseMmaMetadata::Ordered => "GeneratedSparseMmaMetadata::Ordered",
+        };
+        let selector = match mma.selector {
+            SparseMmaSelector::ImmediateZeroOrOne => {
+                "GeneratedSparseMmaSelector::ImmediateZeroOrOne"
+            }
+            SparseMmaSelector::ImmediateZero => "GeneratedSparseMmaSelector::ImmediateZero",
+        };
+        return format!(
+            "GeneratedIntrinsicVariant::SparseMma {{ shape: {shape}, accumulator: {accumulator}, a_element: {}, b_element: {}, a_layout: {}, b_layout: {}, overflow: {overflow}, metadata: {metadata}, selector: {selector} }}",
+            element(mma.a_element),
+            element(mma.b_element),
+            layout(mma.a_layout),
+            layout(mma.b_layout),
+        );
+    }
+    if let Some(arithmetic) = &record.scalar_arithmetic {
+        let format = match arithmetic.format {
+            ScalarArithmeticFormat::F32 => "GeneratedScalarArithmeticFormat::F32",
+            ScalarArithmeticFormat::F64 => "GeneratedScalarArithmeticFormat::F64",
+        };
+        let operation = match arithmetic.operation {
+            ScalarArithmeticOperation::Mul => "GeneratedScalarArithmeticOperation::Mul",
+            ScalarArithmeticOperation::Div => "GeneratedScalarArithmeticOperation::Div",
+            ScalarArithmeticOperation::Fma => "GeneratedScalarArithmeticOperation::Fma",
+            ScalarArithmeticOperation::Add => "GeneratedScalarArithmeticOperation::Add",
+        };
+        let rounding = match arithmetic.rounding {
+            ScalarArithmeticRounding::Rn => "GeneratedScalarArithmeticRounding::Rn",
+            ScalarArithmeticRounding::Rz => "GeneratedScalarArithmeticRounding::Rz",
+            ScalarArithmeticRounding::Rm => "GeneratedScalarArithmeticRounding::Rm",
+            ScalarArithmeticRounding::Rp => "GeneratedScalarArithmeticRounding::Rp",
+        };
+        let subnormal = match arithmetic.subnormal {
+            ScalarArithmeticSubnormal::Preserve => "GeneratedScalarArithmeticSubnormal::Preserve",
+            ScalarArithmeticSubnormal::Ftz => "GeneratedScalarArithmeticSubnormal::Ftz",
+        };
+        let saturation = match arithmetic.saturation {
+            ScalarArithmeticSaturation::None => "GeneratedScalarArithmeticSaturation::None",
+            ScalarArithmeticSaturation::Sat => "GeneratedScalarArithmeticSaturation::Sat",
+        };
+        return format!(
+            "GeneratedIntrinsicVariant::ScalarArithmetic {{ format: {format}, operation: {operation}, rounding: {rounding}, subnormal: {subnormal}, saturation: {saturation} }}"
+        );
+    }
+    if let Some(minmax) = &record.extended_minmax {
+        let format = match minmax.format {
+            ExtendedMinMaxFormat::F32 => "GeneratedExtendedMinMaxFormat::F32",
+            ExtendedMinMaxFormat::F16 => "GeneratedExtendedMinMaxFormat::F16",
+            ExtendedMinMaxFormat::Bf16 => "GeneratedExtendedMinMaxFormat::Bf16",
+            ExtendedMinMaxFormat::F16x2 => "GeneratedExtendedMinMaxFormat::F16x2",
+            ExtendedMinMaxFormat::Bf16x2 => "GeneratedExtendedMinMaxFormat::Bf16x2",
+        };
+        let operation = match minmax.operation {
+            ExtendedMinMaxOperation::Min => "GeneratedExtendedMinMaxOperation::Min",
+            ExtendedMinMaxOperation::Max => "GeneratedExtendedMinMaxOperation::Max",
+        };
+        let subnormal = match minmax.subnormal {
+            ExtendedMinMaxSubnormal::Preserve => "GeneratedExtendedMinMaxSubnormal::Preserve",
+            ExtendedMinMaxSubnormal::Ftz => "GeneratedExtendedMinMaxSubnormal::Ftz",
+        };
+        let nan = match minmax.nan {
+            ExtendedMinMaxNan::Number => "GeneratedExtendedMinMaxNan::Number",
+            ExtendedMinMaxNan::Nan => "GeneratedExtendedMinMaxNan::Nan",
+        };
+        return format!(
+            "GeneratedIntrinsicVariant::ExtendedMinMax {{ format: {format}, operation: {operation}, subnormal: {subnormal}, nan: {nan}, xorsign_abs: {} }}",
+            minmax.xorsign_abs
+        );
+    }
+    if let Some(conversion) = &record.scalar_conversion {
+        let rounding = match conversion.rounding {
+            ScalarConversionRounding::NearestAway => {
+                "GeneratedScalarConversionRounding::NearestAway"
+            }
+            ScalarConversionRounding::NearestEven => {
+                "GeneratedScalarConversionRounding::NearestEven"
+            }
+            ScalarConversionRounding::TowardZero => "GeneratedScalarConversionRounding::TowardZero",
+        };
+        let saturation = match conversion.saturation {
+            ScalarConversionSaturation::None => "GeneratedScalarConversionSaturation::None",
+            ScalarConversionSaturation::Relu => "GeneratedScalarConversionSaturation::Relu",
+            ScalarConversionSaturation::Satfinite => {
+                "GeneratedScalarConversionSaturation::Satfinite"
+            }
+            ScalarConversionSaturation::ReluSatfinite => {
+                "GeneratedScalarConversionSaturation::ReluSatfinite"
+            }
+        };
+        return format!(
+            "GeneratedIntrinsicVariant::ScalarConversion {{ rounding: {rounding}, saturation: {saturation} }}"
+        );
+    }
+    let Some(ldmatrix) = &record.ldmatrix else {
+        return "GeneratedIntrinsicVariant::Scalar".to_owned();
+    };
+    let variant = &ldmatrix.variant;
+    let shape = match variant.shape {
+        LdmatrixShape::M8n8 => "GeneratedLdmatrixShape::M8n8",
+        LdmatrixShape::M8n16 => "GeneratedLdmatrixShape::M8n16",
+        LdmatrixShape::M16n16 => "GeneratedLdmatrixShape::M16n16",
+    };
+    let multiplicity = match variant.multiplicity {
+        LdmatrixMultiplicity::X1 => "GeneratedLdmatrixMultiplicity::X1",
+        LdmatrixMultiplicity::X2 => "GeneratedLdmatrixMultiplicity::X2",
+        LdmatrixMultiplicity::X4 => "GeneratedLdmatrixMultiplicity::X4",
+    };
+    let layout = match variant.layout {
+        LdmatrixLayout::Normal => "GeneratedLdmatrixLayout::Normal",
+        LdmatrixLayout::Transposed => "GeneratedLdmatrixLayout::Transposed",
+    };
+    let element = match variant.element {
+        LdmatrixElement::B16 => "GeneratedLdmatrixElement::B16",
+        LdmatrixElement::B8 => "GeneratedLdmatrixElement::B8",
+        LdmatrixElement::B8x16B4x16P64 => "GeneratedLdmatrixElement::B8x16B4x16P64",
+        LdmatrixElement::B8x16B6x16P32 => "GeneratedLdmatrixElement::B8x16B6x16P32",
+    };
+    format!(
+        "GeneratedIntrinsicVariant::Ldmatrix {{ shape: {shape}, multiplicity: {multiplicity}, layout: {layout}, element: {element} }}"
+    )
+}
+
+fn generated_backend_requirements(record: &CatalogIntrinsic) -> String {
+    let requirements = record
+        .backend_lowerings
+        .iter()
+        .map(|lowering| {
+            let backend = match lowering.backend {
+                IntrinsicBackend::LlvmNvptx => "GeneratedIntrinsicBackend::LlvmNvptx",
+                IntrinsicBackend::LibNvvm => "GeneratedIntrinsicBackend::LibNvvm",
+            };
+            format!(
+                "GeneratedBackendRequirement {{ backend: {backend}, requirement: GeneratedTargetRequirement {{ minimum_ptx: GeneratedPtxVersion::from_encoded({}), hardware: {} }} }}",
+                lowering.target.minimum_ptx.encoded(),
+                generated_hardware_target(&lowering.target.hardware),
+            )
+        })
+        .collect::<Vec<_>>()
+        .join(", ");
+    format!("&[{requirements}]")
+}
+
+fn replace_exact_render_fragment(output: &mut String, fragment: &str, replacement: &str) {
+    assert_eq!(
+        output.matches(fragment).count(),
+        1,
+        "render fragment must occur exactly once"
+    );
+    let start = output.find(fragment).expect("checked render fragment");
+    output.replace_range(start..start + fragment.len(), replacement);
+}
+
+fn render_target_record(output: &mut String, catalog: &CatalogFile, record: &CatalogIntrinsic) {
+    let llvm_facts = match &record.llvm {
+        Some(llvm) => {
+            let result_range = match &llvm.result_facts.range {
+                Some(range) => format!(
+                    "Some(GeneratedIntrinsicRange {{ lower: {:?}, upper_exclusive: {:?} }})",
+                    range.lower, range.upper_exclusive
+                ),
+                None => "None".to_owned(),
+            };
+            format!(
+                "Some(GeneratedLlvmFacts {{ properties: &{:?}, result_no_undef: {}, result_range: {} }})",
+                llvm.properties, llvm.result_facts.no_undef, result_range
+            )
+        }
+        None => "None".to_owned(),
+    };
+    writeln!(
+            output,
+            "    GeneratedIntrinsicTarget {{ marker: {:?}, id: {:?}, abi_id: {:?}, dialect_op: {:?}, variant: {}, requirement: GeneratedTargetRequirement {{ minimum_ptx: GeneratedPtxVersion::from_encoded({}), hardware: {} }}, backend_requirements: {}, selections: {}, llvm: {} }},",
+            intrinsic_marker(catalog, record),
+            record.id,
+            record.rust.abi_id,
+            record.dialect.op_name,
+            generated_intrinsic_variant(record),
+            record.target.minimum_ptx.encoded(),
+            generated_hardware_target(&record.target.hardware),
+            generated_backend_requirements(record),
+            generated_selection_alternatives(&record.selections),
+            llvm_facts,
+        )
+        .unwrap();
+}
+
+fn render_target_record_assertions(
+    output: &mut String,
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+) {
+    writeln!(
+        output,
+        "        let target = generated_intrinsic_target_by_marker({:?}).unwrap();",
+        intrinsic_marker(catalog, record)
+    )
+    .unwrap();
+    writeln!(
+            output,
+            "        assert_eq!(target.id, {:?});\n        assert_eq!(target.abi_id, {:?});\n        assert_eq!(target.dialect_op, {:?});\n        assert_eq!(target.variant, {});\n        assert_eq!(target.requirement.minimum_ptx.encoded(), {});\n        assert_eq!(target.requirement.hardware, const {{ {} }});\n        assert_eq!(target.backend_requirements, const {{ {} }});\n        assert_eq!(target.selections, {});",
+            record.id,
+            record.rust.abi_id,
+            record.dialect.op_name,
+            generated_intrinsic_variant(record),
+            record.target.minimum_ptx.encoded(),
+            generated_hardware_target(&record.target.hardware),
+            generated_backend_requirements(record),
+            generated_selection_alternatives(&record.selections),
+        )
+        .unwrap();
+    match &record.llvm {
+        Some(llvm) => {
+            writeln!(
+                output,
+                "        assert_eq!(target.llvm.unwrap().properties, &{:?} as &[&str]);",
+                llvm.properties
+            )
+            .unwrap();
+        }
+        None => output.push_str("        assert!(target.llvm.is_none());\n"),
+    }
+}
+
+fn targets_mod_file(
+    catalog: &CatalogFile,
+    hash: &str,
+    groups: &[(&'static str, Vec<&CatalogIntrinsic>)],
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Generated target requirements and separately imported LLVM/selection facts.\n\npub const GENERATED_INTRINSIC_MARKER_ATTR: &str = \"cuda_oxide_intrinsic_marker\";\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]\npub struct GeneratedPtxVersion(u16);\nimpl GeneratedPtxVersion {\n    pub const fn from_encoded(encoded: u16) -> Self { Self(encoded) }\n    pub const fn encoded(self) -> u16 { self.0 }\n    pub const fn major(self) -> u16 { self.0 / 10 }\n    pub const fn minor(self) -> u16 { self.0 % 10 }\n}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedHardwareAlternative { MinimumSm(u16), ExactArchitecture(u16), FamilyTarget(u16) }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetSelectorBinding { pub name: &'static str, pub value: &'static str }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetAlternative { pub minimum_ptx: GeneratedPtxVersion, pub hardware: GeneratedHardwareAlternative }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedHardwareTarget { All, AnyOf(&'static [GeneratedHardwareAlternative]), TargetMatrix { selectors: &'static [GeneratedTargetSelectorBinding], alternatives: &'static [GeneratedTargetAlternative] } }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetRequirement { pub minimum_ptx: GeneratedPtxVersion, pub hardware: GeneratedHardwareTarget }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicBackend { LlvmNvptx, LibNvvm }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedBackendRequirement { pub backend: GeneratedIntrinsicBackend, pub requirement: GeneratedTargetRequirement }\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSelectionAddressSpace { Generic, Shared }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedImmediateBinding { pub argument_index: usize, pub value: i64 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedSelectionConstraints { pub address_space: Option<GeneratedSelectionAddressSpace>, pub immediate_bindings: &'static [GeneratedImmediateBinding] }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedSelectionAlternative { pub source_record: &'static str, pub asm: &'static str, pub predicates: &'static [&'static str], pub constraints: GeneratedSelectionConstraints }\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicRange { pub lower: &'static str, pub upper_exclusive: &'static str }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedLlvmFacts { pub properties: &'static [&'static str], pub result_no_undef: bool, pub result_range: Option<GeneratedIntrinsicRange> }\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedLdmatrixShape { M8n8 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedLdmatrixMultiplicity { X1, X2, X4 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedLdmatrixLayout { Normal, Transposed }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedPackedAtomicFormat { F16x2, Bf16x2 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaShape { M8n8k4, M16n8k8, M16n8k16, M16n8k32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaAccumulator { F32, F64, S32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaElement { Bf16, F16, Tf32, F64, S8, U8 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaLayout { Row, Col }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaOverflow { NotApplicable, Wrapping, Satfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {\n    Scalar,\n    Ldmatrix { shape: GeneratedLdmatrixShape, multiplicity: GeneratedLdmatrixMultiplicity, layout: GeneratedLdmatrixLayout },\n    PackedAtomic { format: GeneratedPackedAtomicFormat },\n    RegisterMma { shape: GeneratedRegisterMmaShape, accumulator: GeneratedRegisterMmaAccumulator, a_element: GeneratedRegisterMmaElement, b_element: GeneratedRegisterMmaElement, a_layout: GeneratedRegisterMmaLayout, b_layout: GeneratedRegisterMmaLayout, overflow: GeneratedRegisterMmaOverflow },\n}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicTarget {\n    pub marker: &'static str,\n    pub id: &'static str,\n    pub abi_id: &'static str,\n    pub dialect_op: &'static str,\n    pub variant: GeneratedIntrinsicVariant,\n    pub requirement: GeneratedTargetRequirement,\n    pub backend_requirements: &'static [GeneratedBackendRequirement],\n    pub selections: &'static [GeneratedSelectionAlternative],\n    pub llvm: Option<GeneratedLlvmFacts>,\n}\n\nimpl GeneratedIntrinsicTarget {\n    pub fn requirement_for_backend(&self, backend: GeneratedIntrinsicBackend) -> GeneratedTargetRequirement {\n        self.backend_requirements.iter().find(|entry| entry.backend == backend).map(|entry| entry.requirement).unwrap_or(self.requirement)\n    }\n}\n",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetAlternative { pub minimum_ptx: GeneratedPtxVersion, pub hardware: GeneratedHardwareAlternative }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedHardwareTarget { All, AnyOf(&'static [GeneratedHardwareAlternative]), TargetMatrix { selectors: &'static [GeneratedTargetSelectorBinding], alternatives: &'static [GeneratedTargetAlternative] } }",
+        "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetAlternative { pub minimum_ptx: GeneratedPtxVersion, pub hardware: GeneratedHardwareAlternative }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedTargetContract { pub selectors: &'static [GeneratedTargetSelectorBinding], pub alternatives: &'static [GeneratedTargetAlternative] }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedHardwareTarget { All, AnyOf(&'static [GeneratedHardwareAlternative]), TargetMatrix { contracts: &'static [GeneratedTargetContract] } }",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "impl GeneratedIntrinsicTarget {\n    pub fn requirement_for_backend(&self, backend: GeneratedIntrinsicBackend) -> GeneratedTargetRequirement {\n        self.backend_requirements.iter().find(|entry| entry.backend == backend).map(|entry| entry.requirement).unwrap_or(self.requirement)\n    }\n}",
+        r#"impl GeneratedHardwareTarget {
+    pub fn contract_for_selector(
+        self,
+        name: &str,
+        value: &str,
+    ) -> Option<&'static GeneratedTargetContract> {
+        let Self::TargetMatrix { contracts } = self else { return None; };
+        let mut matching = contracts.iter().filter(|contract| {
+            matches!(contract.selectors, [binding] if binding.name == name && binding.value == value)
+        });
+        let contract = matching.next()?;
+        if matching.next().is_some() { None } else { Some(contract) }
+    }
+}
+
+impl GeneratedIntrinsicTarget {
+    pub fn requirement_for_backend(&self, backend: GeneratedIntrinsicBackend) -> GeneratedTargetRequirement {
+        self.backend_requirements.iter().find(|entry| entry.backend == backend).map(|entry| entry.requirement).unwrap_or(self.requirement)
+    }
+
+    pub fn target_contract_for_backend_selector(
+        &self,
+        backend: GeneratedIntrinsicBackend,
+        name: &str,
+        value: &str,
+    ) -> Option<&'static GeneratedTargetContract> {
+        self.requirement_for_backend(backend).hardware.contract_for_selector(name, value)
+    }
+}"#,
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "GeneratedLdmatrixShape { M8n8 }",
+        "GeneratedLdmatrixShape { M8n8, M8n16, M16n16 }",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "pub enum GeneratedPackedAtomicFormat { F16x2, Bf16x2 }",
+        "pub enum GeneratedLdmatrixElement { B16, B8, B8x16B4x16P64, B8x16B6x16P32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedPackedAtomicFormat { F16x2, Bf16x2 }",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "Ldmatrix { shape: GeneratedLdmatrixShape, multiplicity: GeneratedLdmatrixMultiplicity, layout: GeneratedLdmatrixLayout }",
+        "Ldmatrix { shape: GeneratedLdmatrixShape, multiplicity: GeneratedLdmatrixMultiplicity, layout: GeneratedLdmatrixLayout, element: GeneratedLdmatrixElement }",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "GeneratedRegisterMmaShape { M8n8k4, M16n8k8, M16n8k16, M16n8k32 }",
+        "GeneratedRegisterMmaShape { M8n8k4, M8n8k16, M8n8k32, M8n8k128, M16n8k4, M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128, M16n8k256 }",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "GeneratedRegisterMmaElement { Bf16, F16, Tf32, F64, S8, U8 }",
+        "GeneratedRegisterMmaElement { Bf16, E2m1, E2m3, E3m2, E4m3, E5m2, F16, Tf32, F64, B1, S4, U4, S8, U8 }",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "pub enum GeneratedRegisterMmaAccumulator { F32, F64, S32 }",
+        "pub enum GeneratedRegisterMmaOperation { Multiply, AndPopc, XorPopc }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaKind { Standard, F8f6f4, Mxf8f6f4 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedRegisterMmaAccumulator { F16, F32, F64, S32 }",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "RegisterMma { shape: GeneratedRegisterMmaShape, accumulator: GeneratedRegisterMmaAccumulator,",
+        "RegisterMma { shape: GeneratedRegisterMmaShape, operation: GeneratedRegisterMmaOperation, kind: GeneratedRegisterMmaKind, accumulator: GeneratedRegisterMmaAccumulator,",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
+        "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaShape { M16n8k32, M16n8k64, M16n8k128 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaAccumulator { F16, F32, S32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaElement { E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaLayout { Row, Col }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaOverflow { NotApplicable, Wrapping, Satfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaMetadata { Standard, Ordered }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaSelector { ImmediateZeroOrOne, ImmediateZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedPrmtMode { Generic, F4e, B4e, Rc8, Ecl, Ecr, Rc16 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedClusterBarrierMode { Arrive, ArriveAligned, ArriveRelaxed, ArriveRelaxedAligned, Wait, WaitAligned }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionRounding { NearestAway, NearestEven, TowardZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionSaturation { None, Relu, Satfinite, ReluSatfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "    RegisterMma { shape: GeneratedRegisterMmaShape, operation: GeneratedRegisterMmaOperation, kind: GeneratedRegisterMmaKind, accumulator: GeneratedRegisterMmaAccumulator, a_element: GeneratedRegisterMmaElement, b_element: GeneratedRegisterMmaElement, a_layout: GeneratedRegisterMmaLayout, b_layout: GeneratedRegisterMmaLayout, overflow: GeneratedRegisterMmaOverflow },\n}",
+        "    RegisterMma { shape: GeneratedRegisterMmaShape, operation: GeneratedRegisterMmaOperation, kind: GeneratedRegisterMmaKind, accumulator: GeneratedRegisterMmaAccumulator, a_element: GeneratedRegisterMmaElement, b_element: GeneratedRegisterMmaElement, a_layout: GeneratedRegisterMmaLayout, b_layout: GeneratedRegisterMmaLayout, overflow: GeneratedRegisterMmaOverflow },\n    SparseMma { shape: GeneratedSparseMmaShape, accumulator: GeneratedSparseMmaAccumulator, a_element: GeneratedSparseMmaElement, b_element: GeneratedSparseMmaElement, a_layout: GeneratedSparseMmaLayout, b_layout: GeneratedSparseMmaLayout, overflow: GeneratedSparseMmaOverflow, metadata: GeneratedSparseMmaMetadata, selector: GeneratedSparseMmaSelector },\n    Prmt { mode: GeneratedPrmtMode },\n    ClusterBarrier { mode: GeneratedClusterBarrierMode },\n    ScalarConversion { rounding: GeneratedScalarConversionRounding, saturation: GeneratedScalarConversionSaturation },\n}",
+    );
+    if wgmma_controls(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
+            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedWgmmaControlMode { Fence, CommitGroup, WaitGroup }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
+        );
+        replace_exact_render_fragment(
+            &mut output,
+            "    ClusterBarrier { mode: GeneratedClusterBarrierMode },\n    ScalarConversion { rounding: GeneratedScalarConversionRounding, saturation: GeneratedScalarConversionSaturation },\n}",
+            "    ClusterBarrier { mode: GeneratedClusterBarrierMode },\n    ScalarConversion { rounding: GeneratedScalarConversionRounding, saturation: GeneratedScalarConversionSaturation },\n    WgmmaControl { mode: GeneratedWgmmaControlMode },\n}",
+        );
+    }
+    if scalar_arithmetics(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
+            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarArithmeticFormat { F32, F64 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarArithmeticOperation { Mul, Div, Fma, Add }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarArithmeticRounding { Rn, Rz, Rm, Rp }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarArithmeticSubnormal { Preserve, Ftz }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarArithmeticSaturation { None, Sat }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
+        );
+        if wgmma_controls(catalog).next().is_some() {
+            replace_exact_render_fragment(
+                &mut output,
+                "    WgmmaControl { mode: GeneratedWgmmaControlMode },\n}",
+                "    WgmmaControl { mode: GeneratedWgmmaControlMode },\n    ScalarArithmetic { format: GeneratedScalarArithmeticFormat, operation: GeneratedScalarArithmeticOperation, rounding: GeneratedScalarArithmeticRounding, subnormal: GeneratedScalarArithmeticSubnormal, saturation: GeneratedScalarArithmeticSaturation },\n}",
+            );
+        } else {
+            replace_exact_render_fragment(
+                &mut output,
+                "    ScalarConversion { rounding: GeneratedScalarConversionRounding, saturation: GeneratedScalarConversionSaturation },\n}",
+                "    ScalarConversion { rounding: GeneratedScalarConversionRounding, saturation: GeneratedScalarConversionSaturation },\n    ScalarArithmetic { format: GeneratedScalarArithmeticFormat, operation: GeneratedScalarArithmeticOperation, rounding: GeneratedScalarArithmeticRounding, subnormal: GeneratedScalarArithmeticSubnormal, saturation: GeneratedScalarArithmeticSaturation },\n}",
+            );
+        }
+    }
+    if extended_minmax(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
+            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedExtendedMinMaxFormat { F32, F16, Bf16, F16x2, Bf16x2 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedExtendedMinMaxOperation { Min, Max }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedExtendedMinMaxSubnormal { Preserve, Ftz }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedExtendedMinMaxNan { Number, Nan }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
+        );
+        replace_exact_render_fragment(
+            &mut output,
+            "}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicTarget",
+            "    ExtendedMinMax { format: GeneratedExtendedMinMaxFormat, operation: GeneratedExtendedMinMaxOperation, subnormal: GeneratedExtendedMinMaxSubnormal, nan: GeneratedExtendedMinMaxNan, xorsign_abs: bool },\n}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicTarget",
+        );
+    }
+    if tcgen05_mma_intrinsics(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
+            "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedTcgen05MmaForm { Shared, Tensor, TensorAshift, SpShared, SpTensor, SpTensorAshift, WsShared, WsSharedZeroColMask, WsSpShared, WsSpSharedZeroColMask, WsSpTensor, WsSpTensorZeroColMask, WsTensor, WsTensorZeroColMask }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedTcgen05MmaTargetSelector { Kind }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {",
+        );
+        replace_exact_render_fragment(
+            &mut output,
+            "}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicTarget",
+            "    Tcgen05Mma { form: GeneratedTcgen05MmaForm, target_selector: GeneratedTcgen05MmaTargetSelector, compatibility_alias: bool },\n}\n\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub struct GeneratedIntrinsicTarget",
+        );
+    }
+    output.push_str(
+        "pub const GENERATED_INTRINSIC_TARGET_GROUPS: &[&[GeneratedIntrinsicTarget]] = &[\n",
+    );
+    for (shard, _) in groups {
+        writeln!(output, "    {shard}::TARGETS,").unwrap();
+    }
+    output.push_str(
+        "];\n\npub fn generated_intrinsic_targets() -> impl Iterator<Item = &'static GeneratedIntrinsicTarget> {\n    GENERATED_INTRINSIC_TARGET_GROUPS.iter().flat_map(|group| group.iter())\n}\n\n",
+    );
+    output.push_str(
+        "pub fn generated_intrinsic_target_by_marker(marker: &str) -> Option<&'static GeneratedIntrinsicTarget> {\n    generated_intrinsic_targets().find(|target| target.marker == marker)\n}\n\npub fn generated_intrinsic_targets_by_op_name(op_name: &str) -> impl Iterator<Item = &'static GeneratedIntrinsicTarget> + '_ {\n    generated_intrinsic_targets().filter(move |target| target.dialect_op == op_name)\n}\n\npub fn generated_intrinsic_target_by_op_name(op_name: &str) -> Option<&'static GeneratedIntrinsicTarget> {\n    generated_intrinsic_targets_by_op_name(op_name).next()\n}\n\npub fn generated_intrinsic_target(op_name: &str) -> Option<&'static GeneratedIntrinsicTarget> {\n    generated_intrinsic_target_by_op_name(op_name)\n}\n\npub fn generated_intrinsic_operation_matches(ctx: &Context, target: &GeneratedIntrinsicTarget, operation: Ptr<Operation>) -> bool {\n    match target.variant {\n        GeneratedIntrinsicVariant::Scalar => true,\n        GeneratedIntrinsicVariant::Ldmatrix { shape, multiplicity, layout } => {\n            let Some(op) = Operation::get_op::<LdmatrixOp>(operation, ctx) else { return false; };\n            let shape_matches = matches!(shape, GeneratedLdmatrixShape::M8n8) && op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref() == Some(&LdmatrixShapeAttr::M8n8);\n            let multiplicity_matches = match multiplicity {\n                GeneratedLdmatrixMultiplicity::X1 => op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref() == Some(&LdmatrixMultiplicityAttr::X1),\n                GeneratedLdmatrixMultiplicity::X2 => op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref() == Some(&LdmatrixMultiplicityAttr::X2),\n                GeneratedLdmatrixMultiplicity::X4 => op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref() == Some(&LdmatrixMultiplicityAttr::X4),\n            };\n            let layout_matches = match layout {\n                GeneratedLdmatrixLayout::Normal => op.get_attr_nvvm_ldmatrix_layout(ctx).as_deref() == Some(&LdmatrixLayoutAttr::Normal),\n                GeneratedLdmatrixLayout::Transposed => op.get_attr_nvvm_ldmatrix_layout(ctx).as_deref() == Some(&LdmatrixLayoutAttr::Transposed),\n            };\n            shape_matches && multiplicity_matches && layout_matches\n                && op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B16)\n                && op.get_attr_nvvm_ldmatrix_state_space(ctx).as_deref() == Some(&LdmatrixStateSpaceAttr::Shared)\n        }\n        GeneratedIntrinsicVariant::PackedAtomic { format } => {\n            let Some(op) = Operation::get_op::<PackedAtomicAddOp>(operation, ctx) else { return false; };\n            let format_matches = match format {\n                GeneratedPackedAtomicFormat::F16x2 => op.get_attr_nvvm_packed_atomic_format(ctx).as_deref() == Some(&PackedAtomicFormatAttr::F16x2),\n                GeneratedPackedAtomicFormat::Bf16x2 => op.get_attr_nvvm_packed_atomic_format(ctx).as_deref() == Some(&PackedAtomicFormatAttr::Bf16x2),\n            };\n            format_matches\n                && op.get_attr_nvvm_packed_atomic_state_space(ctx).as_deref() == Some(&PackedAtomicStateSpaceAttr::Global)\n                && op.get_attr_nvvm_packed_atomic_ordering(ctx).as_deref() == Some(&PackedAtomicOrderingAttr::Relaxed)\n                && op.get_attr_nvvm_packed_atomic_scope(ctx).as_deref() == Some(&PackedAtomicScopeAttr::Gpu)\n                && op.get_attr_nvvm_packed_atomic_rounding(ctx).as_deref() == Some(&PackedAtomicRoundingAttr::Rn)\n                && op.get_attr_nvvm_packed_atomic_subnormal(ctx).as_deref() == Some(&PackedAtomicSubnormalAttr::NoFtz)\n                && op.get_attr_nvvm_packed_atomic_atomicity(ctx).as_deref() == Some(&PackedAtomicAtomicityAttr::PerElement)\n        }\n        GeneratedIntrinsicVariant::RegisterMma { shape, accumulator, a_element, b_element, a_layout, b_layout, overflow } => {\n            let Some(op) = Operation::get_op::<RegisterMmaOp>(operation, ctx) else { return false; };\n            let shape_matches = match shape {\n                GeneratedRegisterMmaShape::M8n8k4 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k4),\n                GeneratedRegisterMmaShape::M16n8k8 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k8),\n                GeneratedRegisterMmaShape::M16n8k16 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k16),\n                GeneratedRegisterMmaShape::M16n8k32 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k32),\n            };\n            let accumulator_matches = match accumulator {\n                GeneratedRegisterMmaAccumulator::F32 => op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref() == Some(&RegisterMmaAccumulatorAttr::F32),\n                GeneratedRegisterMmaAccumulator::F64 => op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref() == Some(&RegisterMmaAccumulatorAttr::F64),\n                GeneratedRegisterMmaAccumulator::S32 => op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref() == Some(&RegisterMmaAccumulatorAttr::S32),\n            };\n            let element_matches = |expected, actual: Option<&RegisterMmaElementAttr>| match expected {\n                GeneratedRegisterMmaElement::Bf16 => actual == Some(&RegisterMmaElementAttr::Bf16),\n                GeneratedRegisterMmaElement::F16 => actual == Some(&RegisterMmaElementAttr::F16),\n                GeneratedRegisterMmaElement::Tf32 => actual == Some(&RegisterMmaElementAttr::Tf32),\n                GeneratedRegisterMmaElement::F64 => actual == Some(&RegisterMmaElementAttr::F64),\n                GeneratedRegisterMmaElement::S8 => actual == Some(&RegisterMmaElementAttr::S8),\n                GeneratedRegisterMmaElement::U8 => actual == Some(&RegisterMmaElementAttr::U8),\n            };\n            let layout_matches = |expected, actual: Option<&RegisterMmaLayoutAttr>| match expected {\n                GeneratedRegisterMmaLayout::Row => actual == Some(&RegisterMmaLayoutAttr::Row),\n                GeneratedRegisterMmaLayout::Col => actual == Some(&RegisterMmaLayoutAttr::Col),\n            };\n            let overflow_matches = match overflow {\n                GeneratedRegisterMmaOverflow::NotApplicable => op.get_attr_nvvm_register_mma_overflow(ctx).as_deref() == Some(&RegisterMmaOverflowAttr::NotApplicable),\n                GeneratedRegisterMmaOverflow::Wrapping => op.get_attr_nvvm_register_mma_overflow(ctx).as_deref() == Some(&RegisterMmaOverflowAttr::Wrapping),\n                GeneratedRegisterMmaOverflow::Satfinite => op.get_attr_nvvm_register_mma_overflow(ctx).as_deref() == Some(&RegisterMmaOverflowAttr::Satfinite),\n            };\n            shape_matches && accumulator_matches\n                && element_matches(a_element, op.get_attr_nvvm_register_mma_a_element(ctx).as_deref())\n                && element_matches(b_element, op.get_attr_nvvm_register_mma_b_element(ctx).as_deref())\n                && layout_matches(a_layout, op.get_attr_nvvm_register_mma_a_layout(ctx).as_deref())\n                && layout_matches(b_layout, op.get_attr_nvvm_register_mma_b_layout(ctx).as_deref())\n                && overflow_matches\n        }\n    }\n}\n",
+    );
+    if tcgen05_mma_intrinsics(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "pub fn generated_intrinsic_target(op_name: &str) -> Option<&'static GeneratedIntrinsicTarget> {\n    generated_intrinsic_target_by_op_name(op_name)\n}\n\npub fn generated_intrinsic_operation_matches",
+            "pub fn generated_intrinsic_target(op_name: &str) -> Option<&'static GeneratedIntrinsicTarget> {\n    generated_intrinsic_target_by_op_name(op_name)\n}\n\npub fn generated_intrinsic_target_is_direct_dialect_candidate(target: &GeneratedIntrinsicTarget) -> bool {\n    !matches!(target.variant, GeneratedIntrinsicVariant::Tcgen05Mma { compatibility_alias: true, .. })\n}\n\npub fn generated_intrinsic_operation_matches",
+        );
+        replace_exact_render_fragment(
+            &mut output,
+            "        GeneratedIntrinsicVariant::Scalar => true,",
+            r#"        GeneratedIntrinsicVariant::Scalar => true,
+        GeneratedIntrinsicVariant::Tcgen05Mma { form, target_selector, compatibility_alias } => {
+            let Some(op) = Operation::get_op::<Tcgen05MmaOp>(operation, ctx) else { return false; };
+            let form_matches = match form {
+                GeneratedTcgen05MmaForm::Shared => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::Shared),
+                GeneratedTcgen05MmaForm::Tensor => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::Tensor),
+                GeneratedTcgen05MmaForm::TensorAshift => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::TensorAshift),
+                GeneratedTcgen05MmaForm::SpShared => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::SpShared),
+                GeneratedTcgen05MmaForm::SpTensor => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::SpTensor),
+                GeneratedTcgen05MmaForm::SpTensorAshift => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::SpTensorAshift),
+                GeneratedTcgen05MmaForm::WsShared => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsShared),
+                GeneratedTcgen05MmaForm::WsSharedZeroColMask => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsSharedZeroColMask),
+                GeneratedTcgen05MmaForm::WsSpShared => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsSpShared),
+                GeneratedTcgen05MmaForm::WsSpSharedZeroColMask => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsSpSharedZeroColMask),
+                GeneratedTcgen05MmaForm::WsSpTensor => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsSpTensor),
+                GeneratedTcgen05MmaForm::WsSpTensorZeroColMask => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsSpTensorZeroColMask),
+                GeneratedTcgen05MmaForm::WsTensor => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsTensor),
+                GeneratedTcgen05MmaForm::WsTensorZeroColMask => op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref() == Some(&Tcgen05MmaFormAttr::WsTensorZeroColMask),
+            };
+            let selector_matches = matches!(target_selector, GeneratedTcgen05MmaTargetSelector::Kind)
+                && op.get_attr_nvvm_tcgen05_mma_kind(ctx).is_some();
+            let alias_matches = !compatibility_alias || (
+                op.get_attr_nvvm_tcgen05_mma_kind(ctx).as_deref() == Some(&Tcgen05MmaKindAttr::F8f6f4)
+                    && match form {
+                        GeneratedTcgen05MmaForm::Shared => {
+                            op.get_attr_nvvm_tcgen05_mma_cta_group(ctx).as_deref() == Some(&Tcgen05MmaCtaGroupAttr::Cg1)
+                                && op.get_attr_nvvm_tcgen05_mma_collector_a(ctx).as_deref() == Some(&Tcgen05MmaCollectorAAttr::Discard)
+                        }
+                        GeneratedTcgen05MmaForm::WsTensor => {
+                            op.get_attr_nvvm_tcgen05_mma_b_buffer(ctx).as_deref() == Some(&Tcgen05MmaBBufferAttr::B0)
+                                && op.get_attr_nvvm_tcgen05_mma_b_usage(ctx).as_deref() == Some(&Tcgen05MmaBUsageAttr::Discard)
+                        }
+                        _ => false,
+                    }
+            );
+            form_matches && selector_matches && alias_matches
+        }"#,
+        );
+    }
+    replace_exact_render_fragment(
+        &mut output,
+        "GeneratedIntrinsicVariant::Ldmatrix { shape, multiplicity, layout } => {",
+        "GeneratedIntrinsicVariant::Ldmatrix { shape, multiplicity, layout, element } => {",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "            let shape_matches = matches!(shape, GeneratedLdmatrixShape::M8n8) && op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref() == Some(&LdmatrixShapeAttr::M8n8);",
+        "            let shape_matches = match shape {\n                GeneratedLdmatrixShape::M8n8 => op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref() == Some(&LdmatrixShapeAttr::M8n8),\n                GeneratedLdmatrixShape::M8n16 => op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref() == Some(&LdmatrixShapeAttr::M8n16),\n                GeneratedLdmatrixShape::M16n16 => op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref() == Some(&LdmatrixShapeAttr::M16n16),\n            };",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "            shape_matches && multiplicity_matches && layout_matches\n                && op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B16)",
+        "            let element_matches = match element {\n                GeneratedLdmatrixElement::B16 => op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B16),\n                GeneratedLdmatrixElement::B8 => op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B8),\n                GeneratedLdmatrixElement::B8x16B4x16P64 => op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B8x16B4x16P64),\n                GeneratedLdmatrixElement::B8x16B6x16P32 => op.get_attr_nvvm_ldmatrix_element(ctx).as_deref() == Some(&LdmatrixElementAttr::B8x16B6x16P32),\n            };\n            shape_matches && multiplicity_matches && layout_matches && element_matches",
+    );
+    let mut compatibility_aliases = String::from(
+        "fn generated_intrinsic_compatibility_marker_by_op_name(op_name: &str) -> Option<&'static str> {\n    match op_name {\n",
+    );
+    let mut compatibility_count = 0;
+    for record in ldmatrix(catalog) {
+        let Some((_, op_name)) = ldmatrix_compat_op(record) else {
+            continue;
+        };
+        compatibility_count += 1;
+        writeln!(
+            compatibility_aliases,
+            "        {op_name:?} => Some({:?}),",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+    }
+    assert_eq!(compatibility_count, 6);
+    compatibility_aliases.push_str("        _ => None,\n    }\n}\n\n");
+    replace_exact_render_fragment(
+        &mut output,
+        "pub fn generated_intrinsic_target_by_marker(marker: &str)",
+        &format!(
+            "{compatibility_aliases}pub fn generated_intrinsic_target_by_marker(marker: &str)"
+        ),
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "    generated_intrinsic_targets().filter(move |target| target.dialect_op == op_name)\n",
+        "    let compatibility_marker = generated_intrinsic_compatibility_marker_by_op_name(op_name);\n    generated_intrinsic_targets().filter(move |target| {\n        target.dialect_op == op_name || compatibility_marker == Some(target.marker)\n    })\n",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "        GeneratedIntrinsicVariant::Ldmatrix { shape, multiplicity, layout, element } => {\n            let Some(op) = Operation::get_op::<LdmatrixOp>(operation, ctx) else { return false; };",
+        "        GeneratedIntrinsicVariant::Ldmatrix { shape, multiplicity, layout, element } => {\n            let operation_name = Operation::get_opid(operation, ctx).to_string();\n            if let Some(marker) = generated_intrinsic_compatibility_marker_by_op_name(&operation_name) {\n                return marker == target.marker;\n            }\n            let Some(op) = Operation::get_op::<LdmatrixOp>(operation, ctx) else { return false; };",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "GeneratedIntrinsicVariant::RegisterMma { shape, accumulator,",
+        "GeneratedIntrinsicVariant::RegisterMma { shape, operation: mma_operation, kind, accumulator,",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "            };\n            let accumulator_matches = match accumulator {",
+        "            };\n            let operation_matches = match mma_operation {\n                GeneratedRegisterMmaOperation::Multiply => op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::Multiply,\n                GeneratedRegisterMmaOperation::AndPopc => op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::AndPopc,\n                GeneratedRegisterMmaOperation::XorPopc => op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::XorPopc,\n            };\n            let kind_matches = match kind {\n                GeneratedRegisterMmaKind::Standard => op.kind_or_inferred(ctx) == RegisterMmaKindAttr::Standard,\n                GeneratedRegisterMmaKind::F8f6f4 => op.kind_or_inferred(ctx) == RegisterMmaKindAttr::F8f6f4,\n                GeneratedRegisterMmaKind::Mxf8f6f4 => op.kind_or_inferred(ctx) == RegisterMmaKindAttr::Mxf8f6f4,\n            };\n            let accumulator_matches = match accumulator {",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "            let accumulator_matches = match accumulator {\n                GeneratedRegisterMmaAccumulator::F32",
+        "            let accumulator_matches = match accumulator {\n                GeneratedRegisterMmaAccumulator::F16 => op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref() == Some(&RegisterMmaAccumulatorAttr::F16),\n                GeneratedRegisterMmaAccumulator::F32",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "            shape_matches && accumulator_matches",
+        "            shape_matches && operation_matches && kind_matches && accumulator_matches",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "GeneratedRegisterMmaShape::M8n8k4 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k4),\n                GeneratedRegisterMmaShape::M16n8k8",
+        "GeneratedRegisterMmaShape::M8n8k4 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k4),\n                GeneratedRegisterMmaShape::M8n8k16 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k16),\n                GeneratedRegisterMmaShape::M8n8k32 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k32),\n                GeneratedRegisterMmaShape::M8n8k128 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k128),\n                GeneratedRegisterMmaShape::M16n8k4 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k4),\n                GeneratedRegisterMmaShape::M16n8k8",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "GeneratedRegisterMmaShape::M16n8k32 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k32),\n            };",
+        "GeneratedRegisterMmaShape::M16n8k32 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k32),\n                GeneratedRegisterMmaShape::M16n8k64 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k64),\n                GeneratedRegisterMmaShape::M16n8k128 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k128),\n                GeneratedRegisterMmaShape::M16n8k256 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k256),\n            };",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "GeneratedRegisterMmaElement::F64 => actual == Some(&RegisterMmaElementAttr::F64),\n                GeneratedRegisterMmaElement::S8",
+        "GeneratedRegisterMmaElement::F64 => actual == Some(&RegisterMmaElementAttr::F64),\n                GeneratedRegisterMmaElement::E2m1 => actual == Some(&RegisterMmaElementAttr::E2m1),\n                GeneratedRegisterMmaElement::E2m3 => actual == Some(&RegisterMmaElementAttr::E2m3),\n                GeneratedRegisterMmaElement::E3m2 => actual == Some(&RegisterMmaElementAttr::E3m2),\n                GeneratedRegisterMmaElement::E4m3 => actual == Some(&RegisterMmaElementAttr::E4m3),\n                GeneratedRegisterMmaElement::E5m2 => actual == Some(&RegisterMmaElementAttr::E5m2),\n                GeneratedRegisterMmaElement::B1 => actual == Some(&RegisterMmaElementAttr::B1),\n                GeneratedRegisterMmaElement::S4 => actual == Some(&RegisterMmaElementAttr::S4),\n                GeneratedRegisterMmaElement::U4 => actual == Some(&RegisterMmaElementAttr::U4),\n                GeneratedRegisterMmaElement::S8",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "                && overflow_matches\n        }\n    }\n}\n",
+        "                && overflow_matches\n        }\n        GeneratedIntrinsicVariant::SparseMma { shape, accumulator, a_element, b_element, a_layout, b_layout, overflow, metadata, selector } => {\n            let Some(op) = Operation::get_op::<SparseMmaOp>(operation, ctx) else { return false; };\n            let element_matches = |expected, actual: Option<&SparseMmaElementAttr>| match expected {\n                GeneratedSparseMmaElement::E2m1 => actual == Some(&SparseMmaElementAttr::E2m1),\n                GeneratedSparseMmaElement::E2m3 => actual == Some(&SparseMmaElementAttr::E2m3),\n                GeneratedSparseMmaElement::E3m2 => actual == Some(&SparseMmaElementAttr::E3m2),\n                GeneratedSparseMmaElement::E4m3 => actual == Some(&SparseMmaElementAttr::E4m3),\n                GeneratedSparseMmaElement::E5m2 => actual == Some(&SparseMmaElementAttr::E5m2),\n                GeneratedSparseMmaElement::S4 => actual == Some(&SparseMmaElementAttr::S4),\n                GeneratedSparseMmaElement::U4 => actual == Some(&SparseMmaElementAttr::U4),\n                GeneratedSparseMmaElement::S8 => actual == Some(&SparseMmaElementAttr::S8),\n                GeneratedSparseMmaElement::U8 => actual == Some(&SparseMmaElementAttr::U8),\n            };\n            let layout_matches = |expected, actual: Option<&SparseMmaLayoutAttr>| match expected {\n                GeneratedSparseMmaLayout::Row => actual == Some(&SparseMmaLayoutAttr::Row),\n                GeneratedSparseMmaLayout::Col => actual == Some(&SparseMmaLayoutAttr::Col),\n            };\n            let overflow_matches = match overflow {\n                GeneratedSparseMmaOverflow::NotApplicable => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::NotApplicable),\n                GeneratedSparseMmaOverflow::Wrapping => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Wrapping),\n                GeneratedSparseMmaOverflow::Satfinite => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Satfinite),\n            };\n            let metadata_matches = match metadata {\n                GeneratedSparseMmaMetadata::Standard => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Standard),\n                GeneratedSparseMmaMetadata::Ordered => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Ordered),\n            };\n            matches!(shape, GeneratedSparseMmaShape::M16n8k32)\n                && op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32)\n                && matches!(accumulator, GeneratedSparseMmaAccumulator::S32)\n                && op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32)\n                && element_matches(a_element, op.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref())\n                && element_matches(b_element, op.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref())\n                && layout_matches(a_layout, op.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref())\n                && layout_matches(b_layout, op.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref())\n                && overflow_matches\n                && metadata_matches\n                && matches!(selector, GeneratedSparseMmaSelector::ImmediateZeroOrOne)\n                && op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne)\n        }\n    }\n}\n",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "            matches!(shape, GeneratedSparseMmaShape::M16n8k32)\n                && op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32)\n                && matches!(accumulator, GeneratedSparseMmaAccumulator::S32)\n                && op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32)",
+        "            let shape_matches = match shape {\n                GeneratedSparseMmaShape::M16n8k32 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32),\n                GeneratedSparseMmaShape::M16n8k64 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k64),\n                GeneratedSparseMmaShape::M16n8k128 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k128),\n            };\n            let accumulator_matches = match accumulator {\n                GeneratedSparseMmaAccumulator::F16 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F16),\n                GeneratedSparseMmaAccumulator::F32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F32),\n                GeneratedSparseMmaAccumulator::S32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32),\n            };\n            let selector_matches = match selector {\n                GeneratedSparseMmaSelector::ImmediateZeroOrOne => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),\n                GeneratedSparseMmaSelector::ImmediateZero => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZero),\n            };\n            shape_matches\n                && accumulator_matches",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "                && metadata_matches\n                && matches!(selector, GeneratedSparseMmaSelector::ImmediateZeroOrOne)\n                && op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne)",
+        "                && metadata_matches\n                && selector_matches",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "        }\n    }\n}\n",
+        "        }\n        GeneratedIntrinsicVariant::Prmt { mode } => {\n            let Some(op) = Operation::get_op::<PrmtOp>(operation, ctx) else { return false; };\n            match mode {\n                GeneratedPrmtMode::Generic => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Generic),\n                GeneratedPrmtMode::F4e => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::F4e),\n                GeneratedPrmtMode::B4e => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::B4e),\n                GeneratedPrmtMode::Rc8 => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Rc8),\n                GeneratedPrmtMode::Ecl => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Ecl),\n                GeneratedPrmtMode::Ecr => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Ecr),\n                GeneratedPrmtMode::Rc16 => op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Rc16),\n            }\n        }\n    }\n}\n",
+    );
+    replace_exact_render_fragment(
+        &mut output,
+        "        }\n    }\n}\n",
+        "        }\n        GeneratedIntrinsicVariant::ClusterBarrier { mode } => {\n            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else { return false; };\n            match mode {\n                GeneratedClusterBarrierMode::Arrive => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Arrive),\n                GeneratedClusterBarrierMode::ArriveAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveAligned),\n                GeneratedClusterBarrierMode::ArriveRelaxed => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxed),\n                GeneratedClusterBarrierMode::ArriveRelaxedAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned),\n                GeneratedClusterBarrierMode::Wait => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Wait),\n                GeneratedClusterBarrierMode::WaitAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::WaitAligned),\n            }\n        }\n    }\n}\n",
+    );
+    if wgmma_controls(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "        GeneratedIntrinsicVariant::ClusterBarrier { mode } => {\n            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else { return false; };\n            match mode {\n                GeneratedClusterBarrierMode::Arrive => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Arrive),\n                GeneratedClusterBarrierMode::ArriveAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveAligned),\n                GeneratedClusterBarrierMode::ArriveRelaxed => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxed),\n                GeneratedClusterBarrierMode::ArriveRelaxedAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned),\n                GeneratedClusterBarrierMode::Wait => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Wait),\n                GeneratedClusterBarrierMode::WaitAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::WaitAligned),\n            }\n        }\n    }\n}\n",
+            "        GeneratedIntrinsicVariant::ClusterBarrier { mode } => {\n            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else { return false; };\n            match mode {\n                GeneratedClusterBarrierMode::Arrive => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Arrive),\n                GeneratedClusterBarrierMode::ArriveAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveAligned),\n                GeneratedClusterBarrierMode::ArriveRelaxed => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxed),\n                GeneratedClusterBarrierMode::ArriveRelaxedAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned),\n                GeneratedClusterBarrierMode::Wait => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Wait),\n                GeneratedClusterBarrierMode::WaitAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::WaitAligned),\n            }\n        }\n        GeneratedIntrinsicVariant::WgmmaControl { mode } => match mode {\n            GeneratedWgmmaControlMode::Fence => Operation::get_op::<WgmmaFenceSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::CommitGroup => Operation::get_op::<WgmmaCommitGroupSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::WaitGroup => Operation::get_op::<WgmmaWaitGroupSyncAlignedOp>(operation, ctx).is_some(),\n        },\n    }\n}\n",
+        );
+    }
+    if scalar_conversions(catalog).next().is_some() {
+        let scalar_match = "        GeneratedIntrinsicVariant::ScalarConversion { rounding, saturation } => {\n            let Some(op) = Operation::get_op::<ScalarConversionOp>(operation, ctx) else { return false; };\n            let rounding_matches = match rounding {\n                GeneratedScalarConversionRounding::NearestAway => op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref() == Some(&ScalarConversionRoundingAttr::NearestAway),\n                GeneratedScalarConversionRounding::NearestEven => op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref() == Some(&ScalarConversionRoundingAttr::NearestEven),\n                GeneratedScalarConversionRounding::TowardZero => op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref() == Some(&ScalarConversionRoundingAttr::TowardZero),\n            };\n            let saturation_matches = match saturation {\n                GeneratedScalarConversionSaturation::None => op.get_attr_nvvm_scalar_conversion_saturation(ctx).as_deref() == Some(&ScalarConversionSaturationAttr::None),\n                GeneratedScalarConversionSaturation::Relu => op.get_attr_nvvm_scalar_conversion_saturation(ctx).as_deref() == Some(&ScalarConversionSaturationAttr::Relu),\n                GeneratedScalarConversionSaturation::Satfinite => op.get_attr_nvvm_scalar_conversion_saturation(ctx).as_deref() == Some(&ScalarConversionSaturationAttr::Satfinite),\n                GeneratedScalarConversionSaturation::ReluSatfinite => op.get_attr_nvvm_scalar_conversion_saturation(ctx).as_deref() == Some(&ScalarConversionSaturationAttr::ReluSatfinite),\n            };\n            rounding_matches && saturation_matches\n        }\n";
+        if wgmma_controls(catalog).next().is_some() {
+            replace_exact_render_fragment(
+                &mut output,
+                "        GeneratedIntrinsicVariant::WgmmaControl { mode } => match mode {\n            GeneratedWgmmaControlMode::Fence => Operation::get_op::<WgmmaFenceSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::CommitGroup => Operation::get_op::<WgmmaCommitGroupSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::WaitGroup => Operation::get_op::<WgmmaWaitGroupSyncAlignedOp>(operation, ctx).is_some(),\n        },\n    }\n}\n",
+                &format!(
+                    "        GeneratedIntrinsicVariant::WgmmaControl {{ mode }} => match mode {{\n            GeneratedWgmmaControlMode::Fence => Operation::get_op::<WgmmaFenceSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::CommitGroup => Operation::get_op::<WgmmaCommitGroupSyncAlignedOp>(operation, ctx).is_some(),\n            GeneratedWgmmaControlMode::WaitGroup => Operation::get_op::<WgmmaWaitGroupSyncAlignedOp>(operation, ctx).is_some(),\n        }},\n{scalar_match}    }}\n}}\n"
+                ),
+            );
+        } else {
+            replace_exact_render_fragment(
+                &mut output,
+                "        GeneratedIntrinsicVariant::ClusterBarrier { mode } => {\n            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else { return false; };\n            match mode {\n                GeneratedClusterBarrierMode::Arrive => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Arrive),\n                GeneratedClusterBarrierMode::ArriveAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveAligned),\n                GeneratedClusterBarrierMode::ArriveRelaxed => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxed),\n                GeneratedClusterBarrierMode::ArriveRelaxedAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned),\n                GeneratedClusterBarrierMode::Wait => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Wait),\n                GeneratedClusterBarrierMode::WaitAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::WaitAligned),\n            }\n        }\n    }\n}\n",
+                &format!(
+                    "        GeneratedIntrinsicVariant::ClusterBarrier {{ mode }} => {{\n            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else {{ return false; }};\n            match mode {{\n                GeneratedClusterBarrierMode::Arrive => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Arrive),\n                GeneratedClusterBarrierMode::ArriveAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveAligned),\n                GeneratedClusterBarrierMode::ArriveRelaxed => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxed),\n                GeneratedClusterBarrierMode::ArriveRelaxedAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned),\n                GeneratedClusterBarrierMode::Wait => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::Wait),\n                GeneratedClusterBarrierMode::WaitAligned => op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() == Some(&ClusterBarrierModeAttr::WaitAligned),\n            }}\n        }}\n{scalar_match}    }}\n}}\n"
+                ),
+            );
+        }
+    }
+    if scalar_arithmetics(catalog).next().is_some() {
+        let arithmetic_match = r#"        GeneratedIntrinsicVariant::ScalarArithmetic { format, operation: arithmetic_operation, rounding, subnormal, saturation } => {
+            let Some(op) = Operation::get_op::<ScalarArithmeticOp>(operation, ctx) else { return false; };
+            let format_matches = match format {
+                GeneratedScalarArithmeticFormat::F32 => op.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref() == Some(&ScalarArithmeticFormatAttr::F32),
+                GeneratedScalarArithmeticFormat::F64 => op.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref() == Some(&ScalarArithmeticFormatAttr::F64),
+            };
+            let operation_matches = match arithmetic_operation {
+                GeneratedScalarArithmeticOperation::Mul => op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref() == Some(&ScalarArithmeticOperationAttr::Mul),
+                GeneratedScalarArithmeticOperation::Div => op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref() == Some(&ScalarArithmeticOperationAttr::Div),
+                GeneratedScalarArithmeticOperation::Fma => op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref() == Some(&ScalarArithmeticOperationAttr::Fma),
+                GeneratedScalarArithmeticOperation::Add => op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref() == Some(&ScalarArithmeticOperationAttr::Add),
+            };
+            let rounding_matches = match rounding {
+                GeneratedScalarArithmeticRounding::Rn => op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref() == Some(&ScalarArithmeticRoundingAttr::Rn),
+                GeneratedScalarArithmeticRounding::Rz => op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref() == Some(&ScalarArithmeticRoundingAttr::Rz),
+                GeneratedScalarArithmeticRounding::Rm => op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref() == Some(&ScalarArithmeticRoundingAttr::Rm),
+                GeneratedScalarArithmeticRounding::Rp => op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref() == Some(&ScalarArithmeticRoundingAttr::Rp),
+            };
+            let subnormal_matches = match subnormal {
+                GeneratedScalarArithmeticSubnormal::Preserve => op.get_attr_nvvm_scalar_arithmetic_subnormal(ctx).as_deref() == Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                GeneratedScalarArithmeticSubnormal::Ftz => op.get_attr_nvvm_scalar_arithmetic_subnormal(ctx).as_deref() == Some(&ScalarArithmeticSubnormalAttr::Ftz),
+            };
+            let saturation_matches = match saturation {
+                GeneratedScalarArithmeticSaturation::None => op.get_attr_nvvm_scalar_arithmetic_saturation(ctx).as_deref() == Some(&ScalarArithmeticSaturationAttr::None),
+                GeneratedScalarArithmeticSaturation::Sat => op.get_attr_nvvm_scalar_arithmetic_saturation(ctx).as_deref() == Some(&ScalarArithmeticSaturationAttr::Sat),
+            };
+            format_matches && operation_matches && rounding_matches && subnormal_matches && saturation_matches
+        }
+"#;
+        replace_exact_render_fragment(
+            &mut output,
+            "            rounding_matches && saturation_matches\n        }\n    }\n}\n",
+            &format!(
+                "            rounding_matches && saturation_matches\n        }}\n{arithmetic_match}    }}\n}}\n"
+            ),
+        );
+    }
+    if extended_minmax(catalog).next().is_some() {
+        let minmax_match = r#"        GeneratedIntrinsicVariant::ExtendedMinMax { format, operation: minmax_operation, subnormal, nan, xorsign_abs } => {
+            let Some(op) = Operation::get_op::<ExtendedMinMaxOp>(operation, ctx) else { return false; };
+            let format_matches = match format {
+                GeneratedExtendedMinMaxFormat::F32 => op.get_attr_nvvm_extended_minmax_format(ctx).as_deref() == Some(&ExtendedMinMaxFormatAttr::F32),
+                GeneratedExtendedMinMaxFormat::F16 => op.get_attr_nvvm_extended_minmax_format(ctx).as_deref() == Some(&ExtendedMinMaxFormatAttr::F16),
+                GeneratedExtendedMinMaxFormat::Bf16 => op.get_attr_nvvm_extended_minmax_format(ctx).as_deref() == Some(&ExtendedMinMaxFormatAttr::Bf16),
+                GeneratedExtendedMinMaxFormat::F16x2 => op.get_attr_nvvm_extended_minmax_format(ctx).as_deref() == Some(&ExtendedMinMaxFormatAttr::F16x2),
+                GeneratedExtendedMinMaxFormat::Bf16x2 => op.get_attr_nvvm_extended_minmax_format(ctx).as_deref() == Some(&ExtendedMinMaxFormatAttr::Bf16x2),
+            };
+            let operation_matches = match minmax_operation {
+                GeneratedExtendedMinMaxOperation::Min => op.get_attr_nvvm_extended_minmax_operation(ctx).as_deref() == Some(&ExtendedMinMaxOperationAttr::Min),
+                GeneratedExtendedMinMaxOperation::Max => op.get_attr_nvvm_extended_minmax_operation(ctx).as_deref() == Some(&ExtendedMinMaxOperationAttr::Max),
+            };
+            let subnormal_matches = match subnormal {
+                GeneratedExtendedMinMaxSubnormal::Preserve => op.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref() == Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                GeneratedExtendedMinMaxSubnormal::Ftz => op.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref() == Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+            };
+            let nan_matches = match nan {
+                GeneratedExtendedMinMaxNan::Number => op.get_attr_nvvm_extended_minmax_nan(ctx).as_deref() == Some(&ExtendedMinMaxNanAttr::Number),
+                GeneratedExtendedMinMaxNan::Nan => op.get_attr_nvvm_extended_minmax_nan(ctx).as_deref() == Some(&ExtendedMinMaxNanAttr::Nan),
+            };
+            let xorsign_abs_matches = match xorsign_abs {
+                false => op.get_attr_nvvm_extended_minmax_xorsign_abs(ctx).as_deref() == Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+                true => op.get_attr_nvvm_extended_minmax_xorsign_abs(ctx).as_deref() == Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            };
+            format_matches && operation_matches && subnormal_matches && nan_matches && xorsign_abs_matches
+        }
+"#;
+        let match_end = output
+            .rfind("    }\n}\n")
+            .expect("generated target matcher terminator");
+        output.insert_str(match_end, minmax_match);
+    }
+    output.push_str(
+        "\nuse dialect_nvvm::ops::{ClusterBarrierModeAttr, ClusterBarrierOp, LdmatrixElementAttr, LdmatrixLayoutAttr, LdmatrixMultiplicityAttr, LdmatrixOp, LdmatrixShapeAttr, LdmatrixStateSpaceAttr, PackedAtomicAddOp, PackedAtomicAtomicityAttr, PackedAtomicFormatAttr, PackedAtomicOrderingAttr, PackedAtomicRoundingAttr, PackedAtomicScopeAttr, PackedAtomicStateSpaceAttr, PackedAtomicSubnormalAttr, PrmtModeAttr, PrmtOp, RegisterMmaAccumulatorAttr, RegisterMmaElementAttr, RegisterMmaKindAttr, RegisterMmaLayoutAttr, RegisterMmaOp, RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr, SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr, SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr};\nuse pliron::{context::{Context, Ptr}, operation::Operation};\n",
+    );
+    if wgmma_controls(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "SparseMmaSelectorAttr, SparseMmaShapeAttr};",
+            "SparseMmaSelectorAttr, SparseMmaShapeAttr, WgmmaCommitGroupSyncAlignedOp, WgmmaFenceSyncAlignedOp, WgmmaWaitGroupSyncAlignedOp};",
+        );
+    }
+    if scalar_conversions(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "SparseMmaSelectorAttr, SparseMmaShapeAttr",
+            "ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr",
+        );
+    }
+    if scalar_arithmetics(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "SparseMmaSelectorAttr, SparseMmaShapeAttr",
+            "ScalarArithmeticFormatAttr, ScalarArithmeticOp, ScalarArithmeticOperationAttr, ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr",
+        );
+    }
+    if extended_minmax(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "SparseMmaSelectorAttr, SparseMmaShapeAttr",
+            "ExtendedMinMaxFormatAttr, ExtendedMinMaxNanAttr, ExtendedMinMaxOp, ExtendedMinMaxOperationAttr, ExtendedMinMaxSubnormalAttr, ExtendedMinMaxXorSignAbsAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr",
+        );
+    }
+    if tcgen05_mma_intrinsics(catalog).next().is_some() {
+        replace_exact_render_fragment(
+            &mut output,
+            "SparseMmaSelectorAttr, SparseMmaShapeAttr",
+            "SparseMmaSelectorAttr, SparseMmaShapeAttr, Tcgen05MmaBBufferAttr, Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr, Tcgen05MmaFormAttr, Tcgen05MmaKindAttr, Tcgen05MmaOp",
+        );
+    }
+    output.push('\n');
+    for (shard, _) in groups {
+        writeln!(output, "mod {shard};").unwrap();
+    }
+    output.push_str("\n#[cfg(test)]\nmod tests;\n");
+    output
+}
+
+const TARGETS_GENERATED_DIR: &str = "crates/cuda-oxide-codegen/src/generated_intrinsic_targets";
+
+/// Family shard for one target record. Mirrors the dialect-nvvm family
+/// coalescings; tcgen05 sub-splits on the same contract members the
+/// importer shards use, with the MMA half further cut on the
+/// warp-specialized form bit so every table file stays reviewable.
+fn targets_record_shard(record: &CatalogIntrinsic) -> &'static str {
+    if record.family == "tcgen05" {
+        let tcgen05 = record.tcgen05.as_ref().expect("tcgen05 record");
+        if let Some(mma) = &tcgen05.mma {
+            return if tcgen05_mma_form_name(mma.form).starts_with("Ws") {
+                "tcgen05_mma_ws"
+            } else {
+                "tcgen05_mma"
+            };
+        }
+        if tcgen05.ld.is_some() {
+            return "tcgen05_ld";
+        }
+        if tcgen05.st.is_some() {
+            return "tcgen05_st";
+        }
+        if tcgen05.cp.is_some() {
+            return "tcgen05_cp";
+        }
+        return "tcgen05_other";
+    }
+    match record.family.as_str() {
+        "cp_async_copy" | "cp_async_control" | "cp_async_mbarrier" => "cp_async",
+        "counted_barrier" | "grid_dependency" | "register_control" => "execution_control",
+        family => TARGETS_FAMILY_SHARDS
+            .iter()
+            .copied()
+            .find(|shard| *shard == family)
+            .unwrap_or_else(|| panic!("unmapped generated intrinsic family `{family}`")),
+    }
+}
+
+const TARGETS_FAMILY_SHARDS: &[&str] = &[
+    "sreg",
+    "active_mask",
+    "ldmatrix",
+    "stmatrix",
+    "register_mma",
+    "sparse_mma",
+    "packed_atomic",
+    "redux",
+    "vote",
+    "warp_match",
+    "elect",
+    "warp_barrier",
+    "warp_shuffle",
+    "dotprod",
+    "packed_alu",
+    "integer_minmax",
+    "packed_conversion",
+    "scalar_conversion",
+    "scalar_arithmetic",
+    "scalar_math",
+    "extended_minmax",
+    "movmatrix",
+    "prmt",
+    "cluster_barrier",
+    "cluster_memory",
+    "debug_control",
+    "clc",
+    "wgmma_control",
+    "mbarrier_basic",
+    "mbarrier_extended",
+    "sync",
+    "tma",
+];
+
+/// Group the abi-sorted records per shard; group order is each shard's first
+/// appearance in abi order, so iteration stays as close to the old global
+/// table order as a per-family split permits.
+fn targets_groups(catalog: &CatalogFile) -> Vec<(&'static str, Vec<&CatalogIntrinsic>)> {
+    let mut records = catalog.intrinsics.iter().collect::<Vec<_>>();
+    records.sort_by(|left, right| left.rust.abi_id.cmp(&right.rust.abi_id));
+    let mut groups: Vec<(&'static str, Vec<&CatalogIntrinsic>)> = Vec::new();
+    for record in records {
+        let shard = targets_record_shard(record);
+        match groups.iter_mut().find(|(name, _)| *name == shard) {
+            Some((_, members)) => members.push(record),
+            None => groups.push((shard, vec![record])),
+        }
+    }
+    groups
+}
+
+/// Every type name a target shard may need from the module root.
+const TARGETS_TYPE_CANDIDATES: &[&str] = &[
+    "GeneratedBackendRequirement",
+    "GeneratedClusterBarrierMode",
+    "GeneratedExtendedMinMaxFormat",
+    "GeneratedExtendedMinMaxNan",
+    "GeneratedExtendedMinMaxOperation",
+    "GeneratedExtendedMinMaxSubnormal",
+    "GeneratedHardwareAlternative",
+    "GeneratedHardwareTarget",
+    "GeneratedImmediateBinding",
+    "GeneratedIntrinsicBackend",
+    "GeneratedIntrinsicRange",
+    "GeneratedIntrinsicTarget",
+    "GeneratedIntrinsicVariant",
+    "GeneratedLdmatrixElement",
+    "GeneratedLdmatrixLayout",
+    "GeneratedLdmatrixMultiplicity",
+    "GeneratedLdmatrixShape",
+    "GeneratedLlvmFacts",
+    "GeneratedPackedAtomicFormat",
+    "GeneratedPrmtMode",
+    "GeneratedPtxVersion",
+    "GeneratedRegisterMmaAccumulator",
+    "GeneratedRegisterMmaElement",
+    "GeneratedRegisterMmaKind",
+    "GeneratedRegisterMmaLayout",
+    "GeneratedRegisterMmaOperation",
+    "GeneratedRegisterMmaOverflow",
+    "GeneratedRegisterMmaShape",
+    "GeneratedScalarArithmeticFormat",
+    "GeneratedScalarArithmeticOperation",
+    "GeneratedScalarArithmeticRounding",
+    "GeneratedScalarArithmeticSaturation",
+    "GeneratedScalarArithmeticSubnormal",
+    "GeneratedScalarConversionRounding",
+    "GeneratedScalarConversionSaturation",
+    "GeneratedSelectionAddressSpace",
+    "GeneratedSelectionAlternative",
+    "GeneratedSelectionConstraints",
+    "GeneratedSparseMmaAccumulator",
+    "GeneratedSparseMmaElement",
+    "GeneratedSparseMmaLayout",
+    "GeneratedSparseMmaMetadata",
+    "GeneratedSparseMmaOverflow",
+    "GeneratedSparseMmaSelector",
+    "GeneratedSparseMmaShape",
+    "GeneratedTargetAlternative",
+    "GeneratedTargetContract",
+    "GeneratedTargetRequirement",
+    "GeneratedTargetSelectorBinding",
+    "GeneratedTcgen05MmaForm",
+    "GeneratedTcgen05MmaTargetSelector",
+    "GeneratedWgmmaControlMode",
+];
+
+fn targets_shard_imports(entries: &str) -> String {
+    let items: Vec<&str> = TARGETS_TYPE_CANDIDATES
+        .iter()
+        .copied()
+        .filter(|item| uses_identifier(entries, item))
+        .collect();
+    format!("use super::{{{}}};\n", items.join(", "))
+}
+
+fn targets_shard_file(
+    catalog: &CatalogFile,
+    hash: &str,
+    shard: &str,
+    records: &[&CatalogIntrinsic],
+) -> String {
+    let mut entries = String::new();
+    for record in records {
+        render_target_record(&mut entries, catalog, record);
+    }
+    let mut output = rust_header(catalog, hash);
+    writeln!(
+        output,
+        "//! Generated intrinsic target records: `{shard}` intrinsics.\n"
+    )
+    .unwrap();
+    output.push_str(&targets_shard_imports(&entries));
+    output.push_str("\npub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[\n");
+    output.push_str(&entries);
+    output.push_str("];\n");
+    output
+}
+
+/// Test files per table shard. `register_mma` alone splits its assertion
+/// blocks on the accumulator contract so no generated test file passes the
+/// 10k-line review bound; every other shard keeps a single test file.
+fn targets_test_shards<'catalog>(
+    groups: &[(&'static str, Vec<&'catalog CatalogIntrinsic>)],
+) -> Vec<(String, Vec<&'catalog CatalogIntrinsic>)> {
+    let mut test_shards = Vec::new();
+    for (shard, records) in groups {
+        if *shard == "register_mma" {
+            let (integer, float): (Vec<_>, Vec<_>) = records.iter().copied().partition(|record| {
+                matches!(
+                    record
+                        .register_mma
+                        .as_ref()
+                        .expect("register_mma record")
+                        .accumulator,
+                    RegisterMmaAccumulator::S32
+                )
+            });
+            test_shards.push(("register_mma_float".to_owned(), float));
+            test_shards.push(("register_mma_s32".to_owned(), integer));
+        } else {
+            test_shards.push(((*shard).to_owned(), records.clone()));
+        }
+    }
+    test_shards
+}
+
+fn targets_tests_mod_file(
+    catalog: &CatalogFile,
+    hash: &str,
+    test_shards: &[(String, Vec<&CatalogIntrinsic>)],
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Generated intrinsic target tests, grouped per family shard.\n\nuse super::*;\nuse std::collections::BTreeSet;\n\n",
+    );
+    for (shard, _) in test_shards {
+        writeln!(output, "mod {shard};").unwrap();
+    }
+    output.push_str(
+        "\n#[test]\nfn generated_target_table_is_unique_and_lookup_is_complete() {\n    let mut ids = BTreeSet::new();\n    let mut markers = BTreeSet::new();\n    let mut abi_ids = BTreeSet::new();\n    for group in GENERATED_INTRINSIC_TARGET_GROUPS {\n        let mut previous_abi_id = None;\n        for target in *group {\n            if let Some(previous) = previous_abi_id {\n                assert!(previous < target.abi_id, \"generated ABI IDs are not strictly increasing: {previous} then {}\", target.abi_id);\n            }\n            previous_abi_id = Some(target.abi_id);\n            assert!(abi_ids.insert(target.abi_id), \"duplicate generated ABI ID {}\", target.abi_id);\n            assert!(ids.insert(target.id), \"duplicate generated intrinsic ID {}\", target.id);\n            assert!(markers.insert(target.marker), \"duplicate generated marker {}\", target.marker);\n            assert_eq!(generated_intrinsic_target_by_marker(target.marker), Some(target));\n            assert!(generated_intrinsic_targets_by_op_name(target.dialect_op).any(|candidate| candidate == target));\n        }\n    }\n    assert!(generated_intrinsic_target_by_marker(\"v1:i9999\").is_none());\n}\n",
+    );
+    output
+}
+
+fn targets_tests_shard_file(
+    catalog: &CatalogFile,
+    hash: &str,
+    shard: &str,
+    records: &[&CatalogIntrinsic],
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    writeln!(
+        output,
+        "//! Generated intrinsic target tests: `{shard}` intrinsics.\n\nuse super::super::*;\n"
+    )
+    .unwrap();
+    for record in records {
+        writeln!(
+            output,
+            "#[test]\nfn {}_target_matches_the_catalog() {{",
+            record.id
+        )
+        .unwrap();
+        render_target_record_assertions(&mut output, catalog, record);
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_targets_files(catalog: &CatalogFile, hash: &str) -> Vec<(PathBuf, String)> {
+    let groups = targets_groups(catalog);
+    let test_shards = targets_test_shards(&groups);
+    let mut files = vec![
+        (
+            PathBuf::from(format!("{TARGETS_GENERATED_DIR}/mod.rs")),
+            targets_mod_file(catalog, hash, &groups),
+        ),
+        (
+            PathBuf::from(format!("{TARGETS_GENERATED_DIR}/tests/mod.rs")),
+            targets_tests_mod_file(catalog, hash, &test_shards),
+        ),
+    ];
+    for (shard, records) in &groups {
+        files.push((
+            PathBuf::from(format!("{TARGETS_GENERATED_DIR}/{shard}.rs")),
+            targets_shard_file(catalog, hash, shard, records),
+        ));
+    }
+    for (shard, records) in &test_shards {
+        files.push((
+            PathBuf::from(format!("{TARGETS_GENERATED_DIR}/tests/{shard}.rs")),
+            targets_tests_shard_file(catalog, hash, shard, records),
+        ));
+    }
+    files
+}
+
+#[cfg(test)]
+pub(super) fn render_targets(catalog: &CatalogFile, hash: &str) -> String {
+    render_targets_files(catalog, hash)
+        .into_iter()
+        .map(|(_, contents)| contents)
+        .collect::<Vec<_>>()
+        .join("\n")
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/common.rs b/crates/cuda-intrinsics-gen/src/render/common.rs
new file mode 100644
index 0000000000..e4d603c537
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/common.rs
@@ -0,0 +1,225 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogFile, CatalogHardwareAlternative, CatalogHardwareTarget,
+    CatalogIntrinsic, CatalogLlvm, CatalogTargetContract, EvidenceStageKind, IntrinsicBackend,
+    IntrinsicSource,
+};
+
+pub(super) fn rust_header(catalog: &CatalogFile, catalog_sha256: &str) -> String {
+    format!(
+        "/*\n * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n * SPDX-License-Identifier: Apache-2.0\n */\n\n// @generated by cuda-intrinsics-gen {}. DO NOT EDIT.\n// Catalog schema/version: {}/{}; intrinsic ABI: v{}; catalog SHA-256: {}.\n// LLVM source: {}.\n\n",
+        catalog.generator_version,
+        catalog.schema,
+        catalog.catalog_version,
+        catalog.intrinsic_abi,
+        catalog_sha256,
+        catalog.source.llvm_revision
+    )
+}
+
+pub(super) fn llvm_header(catalog: &CatalogFile, catalog_sha256: &str) -> String {
+    format!(
+        "; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n; SPDX-License-Identifier: Apache-2.0\n; @generated by cuda-intrinsics-gen {}. DO NOT EDIT.\n; Catalog schema/version: {}/{}; intrinsic ABI: v{}; catalog SHA-256: {}.\n; LLVM source: {}.\n\n",
+        catalog.generator_version,
+        catalog.schema,
+        catalog.catalog_version,
+        catalog.intrinsic_abi,
+        catalog_sha256,
+        catalog.source.llvm_revision
+    )
+}
+
+pub(super) fn markdown_header(catalog: &CatalogFile, catalog_sha256: &str) -> String {
+    format!(
+        "<!--\nSPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\nSPDX-License-Identifier: Apache-2.0\n@generated by cuda-intrinsics-gen {}. DO NOT EDIT.\nCatalog schema/version: {}/{}; intrinsic ABI: v{}; catalog SHA-256: {}.\nLLVM source: {}.\n-->\n\n",
+        catalog.generator_version,
+        catalog.schema,
+        catalog.catalog_version,
+        catalog.intrinsic_abi,
+        catalog_sha256,
+        catalog.source.llvm_revision
+    )
+}
+
+pub(super) fn llvm(record: &CatalogIntrinsic) -> &CatalogLlvm {
+    record.llvm.as_ref().expect("LLVM-imported intrinsic")
+}
+
+pub(super) fn source_label(record: &CatalogIntrinsic) -> String {
+    match &record.source {
+        IntrinsicSource::LlvmImported { source_record } => {
+            format!("LLVM `{}` from `{source_record}`", llvm(record).symbol)
+        }
+        IntrinsicSource::PtxNative { instruction } => {
+            format!("PTX-native `{instruction}`")
+        }
+    }
+}
+
+pub(super) fn intrinsic_marker(catalog: &CatalogFile, record: &CatalogIntrinsic) -> String {
+    format!("v{}:{}", catalog.intrinsic_abi, record.rust.abi_id)
+}
+
+/// True when `identifier` occurs in `body` as a standalone token that is not
+/// path-qualified (not immediately preceded by `::`). Drives the per-shard
+/// import lists of the sharded generated outputs: an identifier that only
+/// appears fully qualified (e.g. `dialect_nvvm::ops::TmaOp`) must not be
+/// imported, while `TmaOp::build` or `PrmtModeAttr::Generic` must be.
+pub(super) fn uses_identifier(body: &str, identifier: &str) -> bool {
+    let bytes = body.as_bytes();
+    let is_word = |byte: u8| byte.is_ascii_alphanumeric() || byte == b'_';
+    let mut search_from = 0;
+    while let Some(found) = body[search_from..].find(identifier) {
+        let begin = search_from + found;
+        let end = begin + identifier.len();
+        let before_ok = begin == 0 || !is_word(bytes[begin - 1]);
+        let after_ok = end == bytes.len() || !is_word(bytes[end]);
+        let unqualified = begin < 2 || &body[begin - 2..begin] != "::";
+        if before_ok && after_ok && unqualified {
+            return true;
+        }
+        search_from = begin + 1;
+    }
+    false
+}
+
+pub(super) fn hardware_target_label(target: &CatalogHardwareTarget) -> String {
+    match target {
+        CatalogHardwareTarget::All => "all".to_owned(),
+        CatalogHardwareTarget::AnyOf { alternatives } => alternatives
+            .iter()
+            .map(hardware_alternative_label)
+            .collect::<Vec<_>>()
+            .join(" or "),
+        CatalogHardwareTarget::TargetMatrix { contracts } => contracts
+            .iter()
+            .map(|contract| {
+                let selectors = contract
+                    .selectors
+                    .iter()
+                    .map(|selector| format!("{}={}", selector.name, selector.value))
+                    .collect::<Vec<_>>()
+                    .join(", ");
+                let alternatives = contract
+                    .alternatives
+                    .iter()
+                    .map(|alternative| {
+                        format!(
+                            "{} at PTX {}",
+                            hardware_alternative_label(&alternative.hardware),
+                            alternative.minimum_ptx
+                        )
+                    })
+                    .collect::<Vec<_>>()
+                    .join(" or ");
+                if selectors.is_empty() {
+                    alternatives
+                } else {
+                    format!("{alternatives} for {selectors}")
+                }
+            })
+            .collect::<Vec<_>>()
+            .join("; "),
+    }
+}
+
+fn hardware_alternative_label(alternative: &CatalogHardwareAlternative) -> String {
+    match alternative {
+        CatalogHardwareAlternative::MinimumSm { sm } => format!("sm_{sm}+"),
+        CatalogHardwareAlternative::ExactArchitecture { sm } => format!("sm_{sm}a"),
+        CatalogHardwareAlternative::FamilyTarget { sm } => format!("sm_{sm}f"),
+    }
+}
+
+pub(super) fn generated_hardware_target(target: &CatalogHardwareTarget) -> String {
+    match target {
+        CatalogHardwareTarget::All => "GeneratedHardwareTarget::All".to_owned(),
+        CatalogHardwareTarget::AnyOf { alternatives } => {
+            let alternatives = alternatives
+                .iter()
+                .map(generated_hardware_alternative)
+                .collect::<Vec<_>>()
+                .join(", ");
+            format!("GeneratedHardwareTarget::AnyOf(&[{alternatives}])")
+        }
+        CatalogHardwareTarget::TargetMatrix { contracts } => {
+            let contracts = contracts
+                .iter()
+                .map(generated_target_contract)
+                .collect::<Vec<_>>()
+                .join(", ");
+            format!("GeneratedHardwareTarget::TargetMatrix {{ contracts: &[{contracts}] }}")
+        }
+    }
+}
+
+fn generated_target_contract(contract: &CatalogTargetContract) -> String {
+    let selectors = contract
+        .selectors
+        .iter()
+        .map(|selector| {
+            format!(
+                "GeneratedTargetSelectorBinding {{ name: {:?}, value: {:?} }}",
+                selector.name, selector.value
+            )
+        })
+        .collect::<Vec<_>>()
+        .join(", ");
+    let alternatives = contract
+        .alternatives
+        .iter()
+        .map(|alternative| {
+            format!(
+                "GeneratedTargetAlternative {{ minimum_ptx: GeneratedPtxVersion::from_encoded({}), hardware: {} }}",
+                alternative.minimum_ptx.encoded(),
+                generated_hardware_alternative(&alternative.hardware)
+            )
+        })
+        .collect::<Vec<_>>()
+        .join(", ");
+    format!(
+        "GeneratedTargetContract {{ selectors: &[{selectors}], alternatives: &[{alternatives}] }}"
+    )
+}
+
+fn generated_hardware_alternative(alternative: &CatalogHardwareAlternative) -> String {
+    match alternative {
+        CatalogHardwareAlternative::MinimumSm { sm } => {
+            format!("GeneratedHardwareAlternative::MinimumSm({sm})")
+        }
+        CatalogHardwareAlternative::ExactArchitecture { sm } => {
+            format!("GeneratedHardwareAlternative::ExactArchitecture({sm})")
+        }
+        CatalogHardwareAlternative::FamilyTarget { sm } => {
+            format!("GeneratedHardwareAlternative::FamilyTarget({sm})")
+        }
+    }
+}
+
+pub(super) fn backend_label(backend: IntrinsicBackend) -> &'static str {
+    match backend {
+        IntrinsicBackend::LlvmNvptx => "llvm_nvptx",
+        IntrinsicBackend::LibNvvm => "lib_nvvm",
+    }
+}
+
+pub(super) fn lowering_mechanism_label(mechanism: BackendLoweringMechanism) -> &'static str {
+    match mechanism {
+        BackendLoweringMechanism::TypedNvvm => "typed_nvvm",
+        BackendLoweringMechanism::InlinePtx => "inline_ptx",
+    }
+}
+
+pub(super) fn evidence_stage_label(stage: EvidenceStageKind) -> &'static str {
+    match stage {
+        EvidenceStageKind::DeclarationCanonicalization => "declaration canonicalization",
+        EvidenceStageKind::BackendCodegen => "backend codegen",
+        EvidenceStageKind::DeviceLink => "device link",
+        EvidenceStageKind::PtxAssembly => "PTX assembly",
+        EvidenceStageKind::Runtime => "runtime",
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/compat.rs b/crates/cuda-intrinsics-gen/src/render/compat.rs
new file mode 100644
index 0000000000..979f9445fa
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/compat.rs
@@ -0,0 +1,2214 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    CatalogFile, CatalogHardwareAlternative, CatalogHardwareTarget, CatalogIntrinsic, ClcOperation,
+    ClusterBarrierOrdering, ClusterMemoryOperation, CpAsyncCachePolicy, CpAsyncControlOperation,
+    CpAsyncMbarrierOperation, CpAsyncSourceSize, DebugControlOperation, MbarrierBasicOperation,
+    MbarrierExtendedOperation, PackedAluFormat, PackedAtomicFormat, PackedConversionSourceFormat,
+    RegisterMmaAdapter, RegisterMmaCompatibilitySource, RegisterMmaOverflow, ScalarMathFormat,
+    SparseMmaAdapter, SparseMmaCompatibilitySource, SparseMmaOverflow, Tcgen05LdShape,
+    Tcgen05MmaForm, Tcgen05MmaSelectorLayout, Tcgen05Operation, TmaAdapter, TmaOperation,
+    WgmmaControlMode,
+};
+use crate::render::common::{hardware_target_label, llvm, rust_header, source_label};
+use crate::render::families::{
+    ClcSafetyArgNames, clc_intrinsics, cluster_barriers, cluster_memory, cp_async_controls,
+    cp_async_copies, cp_async_mbarriers, debug_controls, dot_products, execution_control_family,
+    expected_ptx_head, extended_minmax, extended_minmax_rust_type, integer_minmaxes,
+    is_blackwell_ldmatrix, ldmatrix, mbarrier_basics, mbarrier_extended, movmatrix,
+    packed_alu_format_shape, packed_alus, packed_atomics, packed_conversion_rust_arguments,
+    packed_conversion_source, packed_conversions, prmts, register_mmas, render_clc_safety_lines,
+    scalar_arithmetic_arity, scalar_arithmetic_rust_type, scalar_arithmetics, scalar_conversions,
+    scalar_math_contract, scalar_maths, sparse_mma_fragment_counts, sparse_mma_metadata_rule,
+    sparse_mma_ptx_head, sparse_mma_selector_description, sparse_mmas, sregs, stmatrices,
+    stmatrix_compatibility_name, stmatrix_variant, sync_intrinsics, tcgen05_intrinsics,
+    tcgen05_is_commit, tcgen05_is_multicast_commit, tcgen05_is_shift, tcgen05_ld_register_count,
+    tcgen05_mma_runtime_parameters, tcgen05_mma_selector_parameters, tcgen05_participation_doc,
+    tcgen05_st_register_count, threadfence_ptx_level, tma_intrinsics, wgmma_control,
+    wgmma_controls,
+};
+use std::fmt::Write as _;
+use std::path::PathBuf;
+
+pub(super) fn render_compat_register_mma(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::wmma` to keep public paths stable.\n\n");
+    for record in register_mmas(catalog).filter(|record| {
+        record.register_mma.as_ref().is_some_and(|mma| {
+            mma.compatibility_source == RegisterMmaCompatibilitySource::GeneratedStub
+        })
+    }) {
+        let mma = record
+            .register_mma
+            .as_ref()
+            .expect("register-MMA semantics");
+        let [path] = record.rust.compatibility_paths.as_slice() else {
+            panic!("generated register-MMA API requires one compatibility path");
+        };
+        assert_eq!(path, &format!("cuda_device::wmma::{}", record.rust.name));
+        assert!(!record.rust.safe);
+        assert!(record.rust.must_use);
+        let argument_names: &[&str] =
+            if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 {
+                &[
+                    "c",
+                    "a",
+                    "b",
+                    "scale_a",
+                    "byte_id_a",
+                    "thread_id_a",
+                    "scale_b",
+                    "byte_id_b",
+                    "thread_id_b",
+                ]
+            } else {
+                &["c", "a", "b"]
+            };
+        assert_eq!(record.rust.arguments.len(), argument_names.len());
+
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "/// Lowers to `{}`. C, A, and B are this lane's fragments in PTX register order.",
+            expected_ptx_head(record)
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "/// Requires PTX {} and `{}`.",
+            record.target.minimum_ptx,
+            hardware_target_label(&record.target.hardware)
+        )
+        .unwrap();
+        match mma.overflow {
+            RegisterMmaOverflow::Wrapping => {
+                output.push_str("/// Signed accumulator overflow wraps.\n");
+            }
+            RegisterMmaOverflow::Satfinite => {
+                output.push_str(
+                    "/// Signed accumulator overflow clamps to the finite `i32` range.\n",
+                );
+            }
+            RegisterMmaOverflow::NotApplicable => {}
+        }
+        output.push_str("///\n/// # Safety\n");
+        output.push_str(
+            "/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited.\n",
+        );
+        output.push_str(
+            "/// `c`, `a`, and `b` must contain this lane's fragments in the documented PTX layout.\n",
+        );
+        if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 {
+            output.push_str(
+                "/// `scale_a` and `scale_b` contain this lane's packed scale data.\n\
+                 /// For `scale_vec::1X`, `byte_id_a` and `byte_id_b` must be in `0..=3`, `thread_id_a` in `0..=1`, and `thread_id_b` in `0..=3`; other values make the PTX operation undefined.\n",
+            );
+        }
+        writeln!(
+            output,
+            "/// See the [PTX MMA fragment layouts]({}).",
+            record.target.ptx_isa_url
+        )
+        .unwrap();
+        output.push_str("/// This register-only operation is not a memory fence.\n");
+        if record.rust.arguments.len() > 7 {
+            output.push_str("#[allow(clippy::too_many_arguments)]\n");
+        }
+        output.push_str("#[must_use]\n#[inline(never)]\n");
+        let arguments = argument_names
+            .iter()
+            .copied()
+            .zip(&record.rust.arguments)
+            .map(|(name, ty)| format!("{name}: {ty}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(
+            output,
+            "pub unsafe fn {}({arguments}) -> {} {{",
+            record.rust.name, record.rust.result
+        )
+        .unwrap();
+        writeln!(output, "    let _ = ({});", argument_names.join(", ")).unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_ldmatrix(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::wmma` to keep public paths stable.\n\n");
+    for record in ldmatrix(catalog).filter(|record| {
+        is_blackwell_ldmatrix(record) && !record.rust.compatibility_paths.is_empty()
+    }) {
+        let [path] = record.rust.compatibility_paths.as_slice() else {
+            panic!("generated Blackwell ldmatrix API requires one compatibility path");
+        };
+        assert_eq!(path, &format!("cuda_device::wmma::{}", record.rust.name));
+        assert_eq!(record.rust.arguments, ["*const u8"]);
+        assert!(!record.rust.safe);
+        assert!(record.rust.must_use);
+
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", expected_ptx_head(record)).unwrap();
+        writeln!(
+            output,
+            "/// Requires PTX {} and `{}`.",
+            record.target.minimum_ptx,
+            hardware_target_label(&record.target.hardware)
+        )
+        .unwrap();
+        output.push_str(
+            "///\n/// # Safety\n\
+             /// All 32 lanes must execute the same instruction and qualifiers, with no exited lanes.\n\
+             /// `smem_ptr` must satisfy the lane-address mapping, alignment, and readable-byte contract documented by PTX.\n\
+             #[must_use]\n#[inline(never)]\n",
+        );
+        writeln!(
+            output,
+            "pub unsafe fn {}(smem_ptr: *const u8) -> {} {{",
+            record.rust.name, record.rust.result
+        )
+        .unwrap();
+        output.push_str("    let _ = smem_ptr;\n");
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_sparse_mma(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::wmma` to keep public paths stable.\n\n");
+    for record in sparse_mmas(catalog).filter(|record| {
+        record.sparse_mma.as_ref().is_some_and(|mma| {
+            mma.compatibility_source == SparseMmaCompatibilitySource::GeneratedStub
+        })
+    }) {
+        let mma = record.sparse_mma.as_ref().expect("sparse-MMA semantics");
+        let [path] = record.rust.compatibility_paths.as_slice() else {
+            panic!("generated sparse-MMA API requires one compatibility path");
+        };
+        assert_eq!(path, &format!("cuda_device::wmma::{}", record.rust.name));
+        assert!(matches!(
+            mma.adapter,
+            SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32
+                | SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32
+                | SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32
+                | SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32
+        ));
+
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "/// Lowers to `{}`. C, A, B, and metadata are this lane's PTX fragments.",
+            sparse_mma_ptx_head(record)
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "/// Requires PTX {} and `{}`.",
+            record.target.minimum_ptx,
+            hardware_target_label(&record.target.hardware)
+        )
+        .unwrap();
+        match mma.overflow {
+            SparseMmaOverflow::NotApplicable => {}
+            SparseMmaOverflow::Wrapping => {
+                output.push_str("/// Signed accumulator overflow wraps.\n");
+            }
+            SparseMmaOverflow::Satfinite => output
+                .push_str("/// Signed accumulator overflow clamps to the finite `i32` range.\n"),
+        }
+        output.push_str("///\n/// # Safety\n");
+        output.push_str(
+            "/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited.\n",
+        );
+        let (c_count, a_count, b_count, _) = sparse_mma_fragment_counts(record);
+        writeln!(
+            output,
+            "/// `c`, `a`, and `b` must contain this lane's {c_count}-, {a_count}-, and {b_count}-register fragments; `metadata` must contain its sparse metadata."
+        )
+        .unwrap();
+        writeln!(output, "/// {}", sparse_mma_metadata_rule(mma)).unwrap();
+        writeln!(
+            output,
+            "/// `selector` must be {}.",
+            sparse_mma_selector_description(record)
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "/// See the [PTX sparse MMA fragment layouts]({}).",
+            record.target.ptx_isa_url
+        )
+        .unwrap();
+        output.push_str("/// This register-only operation is not a memory fence.\n");
+        output.push_str("#[must_use]\n#[inline(never)]\n");
+        let arguments = ["c", "a", "b", "metadata", "selector"]
+            .into_iter()
+            .zip(&record.rust.arguments)
+            .map(|(name, ty)| format!("{name}: {ty}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(
+            output,
+            "pub unsafe fn {}({arguments}) -> {} {{",
+            record.rust.name, record.rust.result
+        )
+        .unwrap();
+        output.push_str("    let _ = (c, a, b, metadata, selector);\n");
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_sreg(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "// This file is included lexically inside `cuda_device::thread` so existing\n// DefPaths remain stable during the generated-intrinsics migration.\n\n",
+    );
+    for record in sregs(catalog) {
+        let Some(path) = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::thread::"))
+        else {
+            continue;
+        };
+        let name = path.rsplit("::").next().unwrap();
+        writeln!(
+            output,
+            "/// Compatibility spelling for `{}`.",
+            record.rust.public_path
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "/// The compiler replaces this call with {}.",
+            source_label(record)
+        )
+        .unwrap();
+        output.push_str("#[allow(non_snake_case)]\n#[inline(never)]\n");
+        let safety = if record.rust.safe { "" } else { "unsafe " };
+        writeln!(
+            output,
+            "pub {safety}fn {name}() -> {} {{",
+            record.rust.result
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_cluster_sreg(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "// This file is included inside `cuda_device::cluster`.\n// Its private leaves let public helpers compose generated reads.\n\n",
+    );
+    for record in sregs(catalog) {
+        let Some(path) = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::cluster::__"))
+        else {
+            continue;
+        };
+        let name = path.rsplit("::").next().unwrap();
+        writeln!(
+            output,
+            "/// Private compatibility spelling for `{}`.",
+            record.rust.public_path
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "/// The compiler replaces this call with `{}`.",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push_str("#[allow(non_snake_case)]\n#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub(crate) fn {name}() -> {} {{",
+            record.rust.result
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_special_register_module(
+    catalog: &CatalogFile,
+    hash: &str,
+    module: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    writeln!(
+        output,
+        "// Included inside `cuda_device::{module}` to keep existing paths stable.\n"
+    )
+    .unwrap();
+    let prefix = format!("cuda_device::{module}::");
+    for record in sregs(catalog).filter(|record| record.special_register.is_some()) {
+        let Some(path) = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with(&prefix))
+        else {
+            continue;
+        };
+        let name = path.rsplit("::").next().unwrap();
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Generated from {}.", source_label(record)).unwrap();
+        output.push_str("#[inline(never)]\n");
+        let safety = if record.rust.safe { "" } else { "unsafe " };
+        writeln!(
+            output,
+            "pub {safety}fn {name}() -> {} {{",
+            record.rust.result
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_fence(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "// This file is included inside `cuda_device::fence` so existing paths stay stable.\n\n",
+    );
+    for record in sync_intrinsics(catalog).filter(|record| threadfence_ptx_level(record).is_some())
+    {
+        let Some(path) = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::fence::"))
+        else {
+            continue;
+        };
+        let name = path.rsplit("::").next().unwrap();
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "/// The compiler replaces this call with `{}`.",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push_str("#[inline(never)]\n");
+        writeln!(output, "pub fn {name}() {{").unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_dotprod(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::dotprod` to keep existing paths stable.\n\n");
+    for record in dot_products(catalog) {
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::dotprod::"))
+            .expect("dot-product compatibility path");
+        let arguments = record
+            .rust
+            .arguments
+            .iter()
+            .enumerate()
+            .map(|(index, ty)| format!("arg{index}: {ty}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let values = (0..record.rust.arguments.len())
+            .map(|index| format!("arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub fn {}({arguments}) -> {} {{",
+            record.rust.name, record.rust.result
+        )
+        .unwrap();
+        if record.rust.arguments.len() == 1 {
+            writeln!(output, "    let _ = {values};").unwrap();
+        } else {
+            writeln!(output, "    let _ = ({values});").unwrap();
+        }
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_prmt(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::prmt` to keep the public paths stable.\n\n");
+    for record in prmts(catalog) {
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::prmt::"))
+            .expect("prmt compatibility path");
+        let arguments = record
+            .rust
+            .arguments
+            .iter()
+            .enumerate()
+            .map(|(index, ty)| format!("arg{index}: {ty}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let values = (0..record.rust.arguments.len())
+            .map(|index| format!("arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("#[must_use]\n#[inline(never)]\n");
+        writeln!(output, "pub fn {}({arguments}) -> u32 {{", record.rust.name).unwrap();
+        writeln!(output, "    let _ = ({values});").unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_cluster_barrier(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::cluster` to keep public paths stable.\n\n");
+    for record in cluster_barriers(catalog) {
+        let barrier = record
+            .cluster_barrier
+            .as_ref()
+            .expect("cluster-barrier contract");
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::cluster::"))
+            .expect("cluster-barrier compatibility path");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
+        output.push_str("///\n/// # Safety\n");
+        output.push_str(
+            "/// Each non-exited cluster thread must arrive exactly once before completion, then execute the matching wait.\n",
+        );
+        if barrier.aligned {
+            output.push_str(
+                "/// Every non-exited thread in the warp must execute this aligned instruction with identical control flow.\n",
+            );
+        }
+        if barrier.ordering == ClusterBarrierOrdering::Relaxed {
+            output.push_str(
+                "/// This relaxed arrival does not publish earlier memory accesses; use the required cluster-scope fence first.\n",
+            );
+        }
+        output.push_str("#[inline(never)]\n");
+        writeln!(output, "pub unsafe fn {}() {{", record.rust.name).unwrap();
+        writeln!(output, "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")").unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_cluster_memory(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::cluster` to keep its public API stable.\n\n");
+    for record in cluster_memory(catalog) {
+        let cluster = record
+            .cluster_memory
+            .as_ref()
+            .expect("cluster-memory contract");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
+        output.push_str("///\n/// # Safety\n");
+        match cluster.operation {
+            ClusterMemoryOperation::MapSharedRank => {
+                output.push_str(
+                    "/// `local_ptr` must point into CTA shared memory, and `target_rank` must name a rank in the same live cluster.\n\
+                     /// The result is a cluster-shared pointer in address space 7. Dereferencing it performs a remote DSMEM access; the target CTA must remain live and synchronization must make the access race-free.\n",
+                );
+                output.push_str("#[must_use]\n#[inline(never)]\n");
+                output.push_str(
+                    "pub unsafe fn map_shared_rank<T>(local_ptr: *const T, target_rank: u32) -> *const T {\n\
+                             let _ = (local_ptr, target_rank);\n\
+                             unreachable!(\"map_shared_rank called outside CUDA kernel context\")\n\
+                         }\n\n",
+                );
+                output.push_str(
+                    "/// Maps a mutable CTA-shared address to another cluster rank.\n\
+                     ///\n\
+                     /// # Safety\n\
+                     /// The mapping requirements above apply. The target CTA must remain live, and remote writes must be synchronized and race-free.\n\
+                     #[must_use]\n#[inline(never)]\n\
+                     pub unsafe fn map_shared_rank_mut<T>(local_ptr: *mut T, target_rank: u32) -> *mut T {\n\
+                             let _ = (local_ptr, target_rank);\n\
+                             unreachable!(\"map_shared_rank_mut called outside CUDA kernel context\")\n\
+                     }\n\n",
+                );
+            }
+            ClusterMemoryOperation::ReadU32 => {
+                output.push_str(
+                    "/// `local_ptr` must identify an aligned readable `u32` in CTA shared memory. `target_rank` must name a rank in the same live cluster.\n\
+                     /// The target CTA must publish the value before this weak cluster load.\n",
+                );
+                output.push_str("#[must_use]\n#[inline(never)]\n");
+                output.push_str(
+                    "pub unsafe fn dsmem_read_u32(local_ptr: *const u32, target_rank: u32) -> u32 {\n\
+                             let _ = (local_ptr, target_rank);\n\
+                             unreachable!(\"dsmem_read_u32 called outside CUDA kernel context\")\n\
+                         }\n\n",
+                );
+            }
+        }
+    }
+    output
+}
+
+pub(super) fn render_compat_movmatrix(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::wmma` to keep its public API stable.\n\n");
+    for record in movmatrix(catalog) {
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::wmma::"))
+            .expect("movmatrix compatibility path");
+        assert_eq!(path, &format!("cuda_device::wmma::{}", record.rust.name));
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str(
+            "///\n\
+             /// Each lane supplies two packed b16 values. The warp collectively transposes the 8x8 tile.\n\
+             /// No addressable memory is touched, but the result depends on every lane's\n\
+             /// input, so the call is modelled as reading and writing inaccessible state:\n\
+             /// two calls with equal operands are not interchangeable.\n\
+             ///\n\
+             /// # Safety\n\
+             /// All 32 warp lanes must execute the same call, and no lane may have exited.\n",
+        );
+        writeln!(
+            output,
+            "/// Requires PTX {} and `sm_75+`.",
+            record.target.minimum_ptx
+        )
+        .unwrap();
+        output.push_str("#[must_use]\n#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub unsafe fn {}(value: u32) -> u32 {{",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("    let _ = value;\n");
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_debug_control(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::debug` to keep its public API stable.\n\n");
+    for operation in [
+        DebugControlOperation::Trap,
+        DebugControlOperation::Breakpoint,
+        DebugControlOperation::Pmevent,
+    ] {
+        let record = debug_controls(catalog)
+            .find(|record| {
+                record
+                    .debug_control
+                    .as_ref()
+                    .is_some_and(|debug| debug.operation == operation)
+            })
+            .expect("complete debug-control family");
+        match operation {
+            DebugControlOperation::Trap => {
+                writeln!(output, "/// {}", record.summary).unwrap();
+                output.push_str("#[inline(never)]\npub fn trap() -> ! {\n");
+                output.push_str(
+                    "    unreachable!(\"trap called outside CUDA kernel context\")\n}\n\n",
+                );
+            }
+            DebugControlOperation::Breakpoint => {
+                writeln!(output, "/// {}", record.summary).unwrap();
+                output.push_str("#[inline(never)]\npub fn breakpoint() {\n");
+                output.push_str(
+                    "    unreachable!(\"breakpoint called outside CUDA kernel context\")\n}\n\n",
+                );
+            }
+            DebugControlOperation::Pmevent => {
+                output.push_str(
+                    r#"/// Triggers performance monitor event `N`, which must be in `0..=15`.
+#[inline(always)]
+pub fn prof_trigger<const N: u32>() {
+    __prof_trigger(N);
+}
+
+#[doc(hidden)]
+#[inline(never)]
+pub(crate) fn __prof_trigger(_event_id: u32) {
+    unreachable!("prof_trigger called outside CUDA kernel context")
+}
+
+"#,
+                );
+            }
+        }
+    }
+    output
+}
+
+pub(super) fn render_compat_stmatrix(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::tcgen05` to keep public paths stable.\n\n");
+    for record in stmatrices(catalog) {
+        let (multiplicity, _) = stmatrix_variant(record).expect("stmatrix variant");
+        let count = multiplicity.register_count();
+        let name = stmatrix_compatibility_name(record);
+        let path = record
+            .rust
+            .compatibility_paths
+            .first()
+            .expect("stmatrix compatibility path");
+        let arguments = std::iter::once("smem_ptr: *mut u8".to_owned())
+            .chain((0..count).map(|index| format!("r{index}: u32")))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let values = std::iter::once("smem_ptr".to_owned())
+            .chain((0..count).map(|index| format!("r{index}")))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("///\n/// # Safety\n");
+        output.push_str(
+            "/// All warp lanes must participate. The used row addresses must be valid, shared, and 16-byte aligned.\n",
+        );
+        output.push_str("#[inline(never)]\n");
+        writeln!(output, "pub unsafe fn {name}({arguments}) {{").unwrap();
+        writeln!(output, "    let _ = ({values});").unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_clc(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::clc` to keep its public API stable.\n\n");
+    for record in clc_intrinsics(catalog) {
+        let operation = record.clc.as_ref().expect("CLC contract").operation;
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("///\n/// # Safety\n");
+        render_clc_safety_lines(&mut output, operation, ClcSafetyArgNames::Compatibility);
+        match operation {
+            ClcOperation::TryCancel | ClcOperation::TryCancelMulticast => {
+                output.push_str("#[inline(never)]\n");
+                writeln!(
+                    output,
+                    "pub unsafe fn {}(response: *mut u8, mbar: *mut Barrier) {{",
+                    record.rust.name
+                )
+                .unwrap();
+                output.push_str("    let _ = (response, mbar);\n");
+            }
+            ClcOperation::QueryIsCanceled
+            | ClcOperation::QueryGetFirstCtaidX
+            | ClcOperation::QueryGetFirstCtaidY
+            | ClcOperation::QueryGetFirstCtaidZ => {
+                output.push_str("#[inline(never)]\n");
+                writeln!(
+                    output,
+                    "pub unsafe fn {}(resp_lo: u64, resp_hi: u64) -> u32 {{",
+                    record.rust.name
+                )
+                .unwrap();
+                output.push_str("    let _ = (resp_lo, resp_hi);\n");
+            }
+        }
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_counted_barrier(catalog: &CatalogFile, hash: &str) -> String {
+    assert_eq!(
+        execution_control_family(catalog, "counted_barrier").count(),
+        4
+    );
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::barrier` to keep its public API stable.\n\n");
+    for record in execution_control_family(catalog, "counted_barrier") {
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str(
+            "///\n/// # Safety\n/// Every participating thread must use a compatible barrier ID and expected thread count.\n#[inline(never)]\n",
+        );
+        writeln!(
+            output,
+            "pub unsafe fn {}(barrier_id: u32, thread_count: u32) {{",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("    let _ = (barrier_id, thread_count);\n");
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_grid_dependency(catalog: &CatalogFile, hash: &str) -> String {
+    assert_eq!(
+        execution_control_family(catalog, "grid_dependency").count(),
+        2
+    );
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "// Included inside `cuda_device::grid` to keep its public API stable.\n\npub mod dependency {\n",
+    );
+    for (id, name) in [
+        ("grid_dependency_launch_dependents", "trigger_dependents"),
+        ("grid_dependency_wait", "wait"),
+    ] {
+        let record = execution_control_family(catalog, "grid_dependency")
+            .find(|record| record.id == id)
+            .expect("complete grid-dependency family");
+        writeln!(output, "    /// {}", record.summary).unwrap();
+        output.push_str(
+            "    ///\n    /// # Safety\n    /// The kernel launch must participate in a valid programmatic dependent-launch protocol.\n    #[inline(never)]\n",
+        );
+        writeln!(output, "    pub unsafe fn {name}() {{").unwrap();
+        writeln!(
+            output,
+            "        unreachable!(\"{name} called outside CUDA kernel context\")"
+        )
+        .unwrap();
+        output.push_str("    }\n\n");
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(super) fn render_compat_register_control(catalog: &CatalogFile, hash: &str) -> String {
+    assert_eq!(
+        execution_control_family(catalog, "register_control").count(),
+        2
+    );
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::thread` to keep its public API stable.\n\n");
+    for (id, public_name, hidden_name) in [
+        ("setmaxnreg_inc", "setmaxnreg_inc", "__setmaxnreg_inc"),
+        ("setmaxnreg_dec", "setmaxnreg_dec", "__setmaxnreg_dec"),
+    ] {
+        let record = execution_control_family(catalog, "register_control")
+            .find(|record| record.id == id)
+            .expect("complete register-control family");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str(
+            "///\n/// # Safety\n/// Every thread in the warpgroup must execute the same operation with the same count.\n#[inline(always)]\n",
+        );
+        writeln!(output, "pub unsafe fn {public_name}<const N: u32>() {{").unwrap();
+        writeln!(output, "    unsafe {{ {hidden_name}(N) }}").unwrap();
+        output.push_str("}\n\n#[doc(hidden)]\n#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub(crate) unsafe fn {hidden_name}(_register_count: u32) {{"
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"{public_name} called outside CUDA kernel context\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_tma(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::tma` to keep its public API stable.\n\n");
+    for record in tma_intrinsics(catalog) {
+        let tma = record.tma.as_ref().expect("TMA contract");
+        let operation = tma.operation;
+        writeln!(output, "/// {}", record.summary).unwrap();
+        let dimensions = tma.dimensions();
+        let is_g2s = matches!(
+            operation,
+            TmaOperation::G2sTile1d
+                | TmaOperation::G2sTile2d
+                | TmaOperation::G2sTile2dMulticast
+                | TmaOperation::G2sTile2dMulticastCg2
+                | TmaOperation::G2sTile3d
+                | TmaOperation::G2sTile4d
+                | TmaOperation::G2sTile5d
+        );
+        let is_s2g = matches!(
+            operation,
+            TmaOperation::S2gTile1d
+                | TmaOperation::S2gTile2d
+                | TmaOperation::S2gTile3d
+                | TmaOperation::S2gTile4d
+                | TmaOperation::S2gTile5d
+        );
+        let is_reduction = operation == TmaOperation::Reduce;
+        if !record.rust.safe {
+            output.push_str("///\n/// # Safety\n");
+            if is_g2s {
+                output.push_str(
+                    "/// `dst`, `tensor_map`, and `barrier` must remain valid until the copy completes.\n",
+                );
+            } else if is_s2g {
+                output.push_str(
+                    "/// `src` and `tensor_map` must remain valid until the committed copy group completes.\n",
+                );
+            } else if is_reduction {
+                output.push_str(
+                    "/// `src` must name a live shared-memory tile and `tensor_map` must describe a compatible global destination until the committed reduction completes.\n",
+                );
+            } else if matches!(
+                tma.adapter,
+                TmaAdapter::DescriptorAndAddressPointers
+                    | TmaAdapter::DescriptorOrdinalAndU32
+                    | TmaAdapter::DescriptorOrdinalAndU64
+                    | TmaAdapter::DescriptorAndImmediateU32
+                    | TmaAdapter::DescriptorAndRuntimeU32
+            ) {
+                output.push_str(
+                    "/// `tensor_map` must point to a writable, 128-byte tensor-map descriptor in global memory.\n",
+                );
+            } else {
+                output.push_str("/// `tensor_map` must point to a live tensor-map descriptor.\n");
+            }
+        }
+        output.push_str("#[inline(never)]\n");
+        if is_g2s {
+            let dimensions = dimensions.unwrap();
+            let mut arguments = vec![
+                "dst: *mut u8".to_owned(),
+                "tensor_map: *const TmaDescriptor".to_owned(),
+            ];
+            let mut values = vec!["dst".to_owned(), "tensor_map".to_owned()];
+            for index in 0..dimensions {
+                arguments.push(format!("coord{index}: i32"));
+                values.push(format!("coord{index}"));
+            }
+            arguments.push("barrier: *mut Barrier".into());
+            values.push("barrier".into());
+            if matches!(
+                operation,
+                TmaOperation::G2sTile2dMulticast | TmaOperation::G2sTile2dMulticastCg2
+            ) {
+                arguments.push("cta_mask: u16".into());
+                values.push("cta_mask".into());
+            }
+            if arguments.len() > 7 {
+                output.push_str("#[allow(clippy::too_many_arguments)]\n");
+            }
+            writeln!(
+                output,
+                "pub unsafe fn {}({}) {{",
+                record.rust.name,
+                arguments.join(", ")
+            )
+            .unwrap();
+            writeln!(output, "    let _ = ({});", values.join(", ")).unwrap();
+        } else if is_s2g || is_reduction {
+            let dimensions = dimensions.unwrap();
+            let mut arguments = vec![
+                "src: *const u8".to_owned(),
+                "tensor_map: *const TmaDescriptor".to_owned(),
+            ];
+            let mut values = vec!["src".to_owned(), "tensor_map".to_owned()];
+            for index in 0..dimensions {
+                arguments.push(format!("coord{index}: i32"));
+                values.push(format!("coord{index}"));
+            }
+            writeln!(
+                output,
+                "pub unsafe fn {}({}) {{",
+                record.rust.name,
+                arguments.join(", ")
+            )
+            .unwrap();
+            writeln!(output, "    let _ = ({});", values.join(", ")).unwrap();
+        } else if operation == TmaOperation::CommitGroup {
+            writeln!(output, "pub fn {}() {{", record.rust.name).unwrap();
+        } else if matches!(
+            operation,
+            TmaOperation::WaitGroup | TmaOperation::WaitGroupRead
+        ) {
+            writeln!(output, "pub fn {}(n: u32) {{", record.rust.name).unwrap();
+            output.push_str("    let _ = n;\n");
+        } else if operation == TmaOperation::PrefetchTensorMap {
+            writeln!(
+                output,
+                "pub unsafe fn {}(tensor_map: *const TmaDescriptor) {{",
+                record.rust.name
+            )
+            .unwrap();
+            output.push_str("    let _ = tensor_map;\n");
+        } else if let Some(coordinate_count) = operation.prefetch_coordinate_count() {
+            let mut arguments = vec!["tensor_map: *const TmaDescriptor".to_owned()];
+            let mut values = vec!["tensor_map".to_owned()];
+            for index in 0..coordinate_count {
+                arguments.push(format!("coord{index}: i32"));
+                values.push(format!("coord{index}"));
+            }
+            if operation.uses_prefetch_cache_hint() {
+                arguments.push("cache_hint: u64".into());
+                values.push("cache_hint".into());
+            }
+            writeln!(
+                output,
+                "pub unsafe fn {}({}) {{",
+                record.rust.name,
+                arguments.join(", ")
+            )
+            .unwrap();
+            writeln!(output, "    let _ = ({});", values.join(", ")).unwrap();
+        } else {
+            match tma.adapter {
+                TmaAdapter::DescriptorAndAddressPointers => {
+                    writeln!(
+                        output,
+                        "pub unsafe fn {}(tensor_map: *mut TmaDescriptor, new_address: *const u8) {{",
+                        record.rust.name
+                    )
+                    .unwrap();
+                    output.push_str("    let _ = (tensor_map, new_address);\n");
+                }
+                TmaAdapter::DescriptorOrdinalAndU32 => {
+                    writeln!(
+                        output,
+                        "pub unsafe fn {}(tensor_map: *mut TmaDescriptor, ordinal: u32, new_value: u32) {{",
+                        record.rust.name
+                    )
+                    .unwrap();
+                    output.push_str("    let _ = (tensor_map, ordinal, new_value);\n");
+                }
+                TmaAdapter::DescriptorOrdinalAndU64 => {
+                    writeln!(
+                        output,
+                        "pub unsafe fn {}(tensor_map: *mut TmaDescriptor, ordinal: u32, new_value: u64) {{",
+                        record.rust.name
+                    )
+                    .unwrap();
+                    output.push_str("    let _ = (tensor_map, ordinal, new_value);\n");
+                }
+                TmaAdapter::DescriptorAndImmediateU32 | TmaAdapter::DescriptorAndRuntimeU32 => {
+                    writeln!(
+                        output,
+                        "pub unsafe fn {}(tensor_map: *mut TmaDescriptor, new_value: u32) {{",
+                        record.rust.name
+                    )
+                    .unwrap();
+                    output.push_str("    let _ = (tensor_map, new_value);\n");
+                }
+                TmaAdapter::DescriptorPointerInjectBytes => {
+                    writeln!(
+                        output,
+                        "pub unsafe fn {}(tensor_map: *const TmaDescriptor) {{",
+                        record.rust.name
+                    )
+                    .unwrap();
+                    output.push_str("    let _ = tensor_map;\n");
+                }
+                TmaAdapter::NoOperands => {
+                    writeln!(output, "pub fn {}() {{", record.rust.name).unwrap();
+                }
+                _ => unreachable!("TMA compatibility operation category was matched"),
+            }
+        }
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output.push_str(
+        r#"/// Replace a global tensor-map address and publish it to the tensor-map proxy.
+///
+/// # Safety
+/// `tensor_map` must point to a writable, 128-byte tensor-map descriptor in
+/// global memory, and `new_address` must remain valid for every later TMA use.
+#[inline(always)]
+pub unsafe fn replace_tma_global_address(
+    tensor_map: *mut TmaDescriptor,
+    new_address: *const u8,
+) {
+    unsafe { tensormap_replace_global_address(tensor_map, new_address) };
+    fence_proxy_tensormap_generic_release_gpu();
+    unsafe { fence_proxy_tensormap_generic_acquire_gpu(tensor_map) };
+}
+"#,
+    );
+    output
+}
+
+pub(super) fn render_compat_wgmma_control(catalog: &CatalogFile, hash: &str) -> String {
+    assert_eq!(wgmma_controls(catalog).count(), 3);
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::wgmma` to keep its public API stable.\n\n");
+
+    for mode in [WgmmaControlMode::Fence, WgmmaControlMode::CommitGroup] {
+        let record = wgmma_control(catalog, mode);
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("#[inline(never)]\n");
+        writeln!(output, "pub fn {}() {{", record.rust.name).unwrap();
+        writeln!(
+            output,
+            "    unreachable!({:?})",
+            format!("{} called outside CUDA kernel context", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+
+    let wait = wgmma_control(catalog, WgmmaControlMode::WaitGroup);
+    writeln!(output, "/// {}", wait.summary).unwrap();
+    output.push_str(
+        r#"#[inline(always)]
+pub fn wgmma_wait_group<const N: u32>() {
+    __wgmma_wait_group(N as u64);
+}
+
+#[doc(hidden)]
+#[inline(never)]
+pub(crate) fn __wgmma_wait_group(_max_pending: u64) {
+    unreachable!("wgmma_wait_group called outside CUDA kernel context")
+}
+"#,
+    );
+    output
+}
+
+fn render_compat_tcgen05_mma_record(output: &mut String, record: &CatalogIntrinsic) {
+    let mma = record
+        .tcgen05
+        .as_ref()
+        .and_then(|tcgen05| tcgen05.mma.as_ref())
+        .expect("tcgen05 MMA record");
+    let parameters = tcgen05_mma_runtime_parameters(mma);
+    let signature = parameters
+        .iter()
+        .map(|(name, ty)| format!("{name}: {ty}"))
+        .collect::<Vec<_>>()
+        .join(", ");
+    let values = parameters
+        .iter()
+        .map(|(name, _)| *name)
+        .collect::<Vec<_>>()
+        .join(", ");
+
+    writeln!(output, "/// {}", record.summary).unwrap();
+    output.push_str("/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n");
+    if mma.alias.is_some() && mma.form == Tcgen05MmaForm::WsTensor {
+        output.push_str("/// This uses kind f8f6f4 and collector b0::discard.\n");
+        output.push_str("/// `legacy_a_desc` is kept for compatibility; tensor A uses `a_tmem`.\n");
+    } else if mma.alias.is_some() {
+        output.push_str("/// This uses kind f8f6f4, CTA group 1, and collector a::discard.\n");
+    } else {
+        match mma.selector_layout {
+            Tcgen05MmaSelectorLayout::Base { .. } => {
+                output.push_str("/// `KIND` is 0=f16, 1=tf32, 2=f8f6f4, or 3=i8.\n");
+                output.push_str(
+                    "/// `CTA_GROUP` is 1 or 2. `COLLECTOR_A` is 0=discard, 1=lastuse, 2=fill, or 3=use.\n",
+                );
+            }
+            Tcgen05MmaSelectorLayout::WarpSpecialized { .. } => {
+                output.push_str("/// `KIND` is 0=f16, 1=tf32, 2=f8f6f4, or 3=i8.\n");
+                output.push_str(
+                    "/// `B_BUFFER` is 0 through 3. `B_USAGE` is 0=discard, 1=lastuse, 2=fill, or 3=use.\n",
+                );
+            }
+        }
+    }
+    output.push_str("///\n/// # Safety\n");
+    output
+        .push_str("/// Tensor-memory addresses and descriptors must be valid for this MMA form.\n");
+    if mma.alias.is_some() {
+        output.push_str("#[inline(never)]\n");
+        output.push_str("#[allow(clippy::too_many_arguments)]\n");
+        writeln!(output, "pub unsafe fn {}({signature}) {{", record.rust.name).unwrap();
+        writeln!(output, "    let _ = ({values});").unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+        return;
+    }
+
+    let selectors = tcgen05_mma_selector_parameters(mma.selector_layout);
+    let const_parameters = selectors
+        .iter()
+        .map(|(name, _)| format!("const {name}: u32"))
+        .collect::<Vec<_>>()
+        .join(", ");
+    let selector_values = selectors
+        .iter()
+        .map(|(name, _)| *name)
+        .collect::<Vec<_>>()
+        .join(", ");
+    output.push_str("#[inline(always)]\n");
+    if parameters.len() > 5 {
+        output.push_str("#[allow(clippy::too_many_arguments)]\n");
+    }
+    writeln!(
+        output,
+        "pub unsafe fn {}<{const_parameters}>({signature}) {{",
+        record.rust.name
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "    unsafe {{ __{}({values}, {selector_values}) }}",
+        record.rust.name
+    )
+    .unwrap();
+    output.push_str("}\n\n#[doc(hidden)]\n#[inline(never)]\n");
+    output.push_str("#[allow(clippy::too_many_arguments)]\n");
+    let hidden_parameters = parameters
+        .iter()
+        .map(|(name, ty)| format!("_{name}: {ty}"))
+        .chain(selectors.iter().map(|(_, name)| format!("_{name}: u32")))
+        .collect::<Vec<_>>()
+        .join(", ");
+    writeln!(
+        output,
+        "pub(crate) unsafe fn __{}({hidden_parameters}) {{",
+        record.rust.name
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "    unreachable!(\"{} called outside CUDA kernel context\")",
+        record.rust.name
+    )
+    .unwrap();
+    output.push_str("}\n\n");
+}
+
+pub(super) fn render_compat_tcgen05(catalog: &CatalogFile, hash: &str) -> String {
+    assert_eq!(tcgen05_intrinsics(catalog).count(), 233);
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::tcgen05` to keep its public API stable.\n\n");
+    for record in tcgen05_intrinsics(catalog) {
+        let tcgen05 = record.tcgen05.as_ref().unwrap();
+        if tcgen05.mma.is_some() {
+            render_compat_tcgen05_mma_record(&mut output, record);
+            continue;
+        }
+        let operation = tcgen05.operation;
+        let has_half_split_offset = tcgen05
+            .ld
+            .is_some_and(|ld| ld.shape == Tcgen05LdShape::M16x32bx2)
+            || tcgen05
+                .st
+                .is_some_and(|st| st.shape == Tcgen05LdShape::M16x32bx2);
+        if has_half_split_offset {
+            let (result, data) = if operation == Tcgen05Operation::Ld {
+                let count = tcgen05_ld_register_count(record);
+                (
+                    if count == 1 {
+                        "u32".into()
+                    } else {
+                        format!("CuSimd<u32, {count}>")
+                    },
+                    None,
+                )
+            } else {
+                let count = tcgen05_st_register_count(record);
+                (
+                    "()".into(),
+                    Some(if count == 1 {
+                        "u32".into()
+                    } else {
+                        format!("CuSimd<u32, {count}>")
+                    }),
+                )
+            };
+            writeln!(output, "/// {}", record.summary).unwrap();
+            output.push_str(
+                "/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n",
+            );
+            output.push_str("///\n/// # Safety\n");
+            output.push_str(
+                "/// The tensor-memory address must be live, and the warp must execute this call uniformly.\n",
+            );
+            output.push_str("#[inline(always)]\n");
+            if let Some(data) = &data {
+                writeln!(
+                    output,
+                    "pub unsafe fn {}<const HALF_SPLIT_OFFSET: i32>(tmem_addr: u32, data: {data}) {{",
+                    record.rust.name
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "    unsafe {{ __{}(tmem_addr, HALF_SPLIT_OFFSET as i64, data) }}",
+                    record.rust.name
+                )
+                .unwrap();
+            } else {
+                writeln!(
+                    output,
+                    "pub unsafe fn {}<const HALF_SPLIT_OFFSET: i32>(tmem_addr: u32) -> {result} {{",
+                    record.rust.name
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "    unsafe {{ __{}(tmem_addr, HALF_SPLIT_OFFSET as i64) }}",
+                    record.rust.name
+                )
+                .unwrap();
+            }
+            output.push_str("}\n\n#[doc(hidden)]\n#[inline(never)]\n");
+            if let Some(data) = data {
+                writeln!(
+                    output,
+                    "pub(crate) unsafe fn __{}(_tmem_addr: u32, _half_split_offset: i64, _data: {data}) {{",
+                    record.rust.name
+                )
+                .unwrap();
+            } else {
+                writeln!(
+                    output,
+                    "pub(crate) unsafe fn __{}(_tmem_addr: u32, _half_split_offset: i64) -> {result} {{",
+                    record.rust.name
+                )
+                .unwrap();
+            }
+            writeln!(
+                output,
+                "    unreachable!(\"{} called outside CUDA kernel context\")",
+                record.rust.name
+            )
+            .unwrap();
+            output.push_str("}\n\n");
+            continue;
+        }
+        let (arguments, values): (String, String) = if operation == Tcgen05Operation::St {
+            let count = tcgen05_st_register_count(record);
+            let data = if count == 1 {
+                "u32".into()
+            } else {
+                format!("CuSimd<u32, {count}>")
+            };
+            (
+                format!("tmem_addr: u32, data: {data}"),
+                "tmem_addr, data".into(),
+            )
+        } else {
+            let (arguments, values) = match operation {
+                Tcgen05Operation::Alloc | Tcgen05Operation::AllocCg2 => {
+                    ("dst_smem: *mut u32, n_cols: u32", "dst_smem, n_cols")
+                }
+                Tcgen05Operation::Dealloc | Tcgen05Operation::DeallocCg2 => {
+                    ("tmem_addr: u32, n_cols: u32", "tmem_addr, n_cols")
+                }
+                Tcgen05Operation::RelinquishAllocPermit
+                | Tcgen05Operation::FenceBeforeThreadSync
+                | Tcgen05Operation::FenceAfterThreadSync
+                | Tcgen05Operation::LoadWait
+                | Tcgen05Operation::StoreWait
+                | Tcgen05Operation::RelinquishAllocPermitCg2 => ("", ""),
+                Tcgen05Operation::Commit
+                | Tcgen05Operation::CommitSharedCluster
+                | Tcgen05Operation::CommitCg2
+                | Tcgen05Operation::CommitSharedClusterCg2 => ("mbar: *mut u64", "mbar"),
+                Tcgen05Operation::MmaWsF16
+                | Tcgen05Operation::MmaWsBf16
+                | Tcgen05Operation::MmaWsTf32 => (
+                    "d_tmem: u32, a_tmem: u32, a_desc: u64, b_desc: u64, idesc: u32, enable_d: bool",
+                    "d_tmem, a_tmem, a_desc, b_desc, idesc, enable_d",
+                ),
+                Tcgen05Operation::MmaF16 | Tcgen05Operation::MmaF16Cg2 => (
+                    "d_tmem: u32, a_desc: u64, b_desc: u64, idesc: u32, enable_d: bool",
+                    "d_tmem, a_desc, b_desc, idesc, enable_d",
+                ),
+                Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2 => {
+                    ("tmem_addr: u32, smem_desc: u64", "tmem_addr, smem_desc")
+                }
+                Tcgen05Operation::Ld16x256bX8Pure
+                | Tcgen05Operation::Ld16x256bPure
+                | Tcgen05Operation::Ld => ("tmem_addr: u32", "tmem_addr"),
+                Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2 => {
+                    ("mbar: *mut u64, cta_mask: u16", "mbar, cta_mask")
+                }
+                Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2 => {
+                    ("tmem_addr: u32", "tmem_addr")
+                }
+                Tcgen05Operation::St => unreachable!("store handled above"),
+                Tcgen05Operation::Mma => unreachable!("generic MMA handled above"),
+            };
+            (arguments.into(), values.into())
+        };
+        let result: String = match operation {
+            Tcgen05Operation::Ld16x256bX8Pure => "TmemF32x32".into(),
+            Tcgen05Operation::Ld16x256bPure => "TmemF32x4".into(),
+            Tcgen05Operation::Ld => {
+                let count = tcgen05_ld_register_count(record);
+                if count == 1 {
+                    "u32".into()
+                } else {
+                    format!("CuSimd<u32, {count}>")
+                }
+            }
+            Tcgen05Operation::St => "()".into(),
+            _ => "()".into(),
+        };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        if let Some(participation) = tcgen05_participation_doc(operation) {
+            writeln!(output, "/// {participation}").unwrap();
+        }
+        output.push_str(
+            "/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n",
+        );
+        if !record.rust.safe {
+            output.push_str("///\n/// # Safety\n");
+            if operation == Tcgen05Operation::St {
+                output.push_str(
+                    "/// The tensor-memory address must remain live and cover the selected tile.\n\
+                     /// All active warp lanes must execute convergently with the same address. Complete the store wait before relying on completion.\n",
+                );
+            } else if operation == Tcgen05Operation::Ld {
+                output.push_str(
+                    "/// The tensor-memory address must remain live and cover the selected tile.\n\
+                     /// All active warp lanes must execute convergently with the same address. Complete the load wait before using the result.\n",
+                );
+            } else if tcgen05_is_commit(operation) {
+                if tcgen05_is_multicast_commit(operation) {
+                    output.push_str(
+                        "/// `mbar` must point to a live initialized cluster-shared mbarrier. `cta_mask` must select valid CTA ranks in its cluster.\n",
+                    );
+                } else {
+                    output.push_str(
+                        "/// `mbar` must point to a live initialized mbarrier valid for this CTA-group mode.\n",
+                    );
+                }
+                output.push_str(
+                    "/// The same thread that issued the tracked asynchronous tcgen05 operations must issue this commit.\n",
+                );
+            } else if tcgen05_is_shift(operation) {
+                output.push_str(
+                    "/// `tmem_addr` must name a live tensor-memory allocation, and its lane component must be a multiple of 32.\n\
+                     /// Completion must be tracked by a matching commit from that same thread and observed through the selected mbarrier before relying on shifted data.\n",
+                );
+            } else {
+                output.push_str("/// The caller must satisfy the tcgen05 address, lifetime, and participation rules.\n");
+            }
+        }
+        output.push_str("#[inline(never)]\n");
+        if record.rust.arguments.len() > 5 {
+            output.push_str("#[allow(clippy::too_many_arguments)]\n");
+        }
+        let safety = if record.rust.safe { "" } else { "unsafe " };
+        writeln!(
+            output,
+            "pub {safety}fn {}({arguments}) -> {result} {{",
+            record.rust.name
+        )
+        .unwrap();
+        if !values.is_empty() {
+            if values.contains(',') {
+                writeln!(output, "    let _ = ({values});").unwrap();
+            } else {
+                writeln!(output, "    let _ = {values};").unwrap();
+            }
+        }
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_packed_atomic(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::atomic` to keep existing paths stable.\n\n");
+    for record in packed_atomics(catalog) {
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::atomic::"))
+            .expect("packed-atomic compatibility path");
+        assert_eq!(path, &format!("cuda_device::atomic::{}", record.rust.name));
+        let packed = record
+            .packed_atomic
+            .as_ref()
+            .expect("packed-atomic semantics");
+        let lane_type = match packed.format {
+            PackedAtomicFormat::F16x2 => "f16",
+            PackedAtomicFormat::Bf16x2 => "bf16",
+        };
+        let minimum_sm = match &record.target.hardware {
+            CatalogHardwareTarget::AnyOf { alternatives } => match alternatives.as_slice() {
+                [CatalogHardwareAlternative::MinimumSm { sm }] => *sm,
+                _ => panic!("packed-atomic compatibility API requires one minimum SM"),
+            },
+            _ => panic!("packed-atomic compatibility API requires one minimum SM"),
+        };
+        assert!(!record.rust.safe);
+        assert!(record.rust.must_use);
+        assert_eq!(record.rust.arguments, ["*mut u32", "u32"]);
+        assert_eq!(record.rust.result, "u32");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "/// `val` and the result pack two {lane_type} lanes into `u32`, low lane first."
+        )
+        .unwrap();
+        output.push_str(
+            "/// The lanes are atomic independently and may not form one old 32-bit snapshot.\n",
+        );
+        output.push_str("/// This is a relaxed GPU-scope operation. Each lane rounds to nearest-even and preserves subnormals.\n");
+        writeln!(
+            output,
+            "/// Requires PTX {} and `sm_{minimum_sm}+`.",
+            record.target.minimum_ptx
+        )
+        .unwrap();
+        output.push_str("///\n/// # Safety\n");
+        output.push_str(
+            "/// `addr` must point to four writable, four-byte-aligned bytes in global memory.\n",
+        );
+        output.push_str("/// Do not overlap this operation with a whole-word atomic or non-atomic lane access.\n");
+        output.push_str("/// Racing atomics must use mutually inclusive scopes; host/system access is not included.\n");
+        output.push_str("#[must_use]\n#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub unsafe fn {}(addr: *mut u32, val: u32) -> u32 {{",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("    let _ = (addr, val);\n");
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_cp_async_copy(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "// Included inside `cuda_device::async_copy` to keep existing paths stable.\n\n",
+    );
+    for record in cp_async_copies(catalog) {
+        let copy = record.cp_async_copy.as_ref().expect("cp.async semantics");
+        let bytes = copy.copy_size.bytes();
+        let cache = match copy.cache_policy {
+            CpAsyncCachePolicy::Ca => "cache-all",
+            CpAsyncCachePolicy::Cg => "cache-global",
+        };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "/// Uses the {cache} policy and copies {bytes} bytes."
+        )
+        .unwrap();
+        if copy.source_size == CpAsyncSourceSize::Runtime {
+            writeln!(
+                output,
+                "/// Bytes after `src_size` are filled with zero; `src_size` must be at most {bytes}."
+            )
+            .unwrap();
+        }
+        output.push_str("///\n/// # Safety\n");
+        writeln!(
+            output,
+            "/// `shared_dst` must point to {bytes} writable bytes in shared memory and be aligned to {bytes} bytes."
+        )
+        .unwrap();
+        if copy.source_size == CpAsyncSourceSize::Runtime {
+            writeln!(
+                output,
+                "/// `global_src` must point to `src_size` readable bytes in global memory and be aligned to {bytes} bytes."
+            )
+            .unwrap();
+        } else {
+            writeln!(
+                output,
+                "/// `global_src` must point to {bytes} readable bytes in global memory and be aligned to {bytes} bytes."
+            )
+            .unwrap();
+        }
+        output.push_str(
+            "/// Both ranges must remain valid, the source must remain unchanged, and the destination must not be accessed until this copy completes.\n\
+             /// The issuing thread must complete the copy. Synchronize threads afterward before another thread accesses the destination.\n\
+             /// User-authored completion assembly must include a compiler memory clobber.\n",
+        );
+        output.push_str("#[inline(never)]\n");
+        if copy.source_size == CpAsyncSourceSize::Runtime {
+            writeln!(
+                output,
+                "pub unsafe fn {}(_shared_dst: *mut u32, _global_src: *const u8, _src_size: u32) {{",
+                record.rust.name
+            )
+            .unwrap();
+        } else {
+            writeln!(
+                output,
+                "pub unsafe fn {}(_shared_dst: *mut u32, _global_src: *const u32) {{",
+                record.rust.name
+            )
+            .unwrap();
+        }
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    for record in cp_async_controls(catalog) {
+        let control = record
+            .cp_async_control
+            .as_ref()
+            .expect("cp.async control semantics");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("///\n/// # Safety\n");
+        match control.operation {
+            CpAsyncControlOperation::CommitGroup => output.push_str(
+                "/// This commits only copies issued by the executing thread and does not wait for completion.\n",
+            ),
+            CpAsyncControlOperation::WaitAll => output.push_str(
+                "/// This waits only for copies issued by this thread. Synchronize threads before another thread accesses a completed destination.\n",
+            ),
+            CpAsyncControlOperation::WaitGroup => output.push_str(
+                "/// `max_pending` must be a compile-time constant. Access only destinations whose copy groups this wait completes.\n",
+            ),
+        }
+        output.push_str("#[inline(never)]\n");
+        if control.operation == CpAsyncControlOperation::WaitGroup {
+            writeln!(
+                output,
+                "pub unsafe fn {}(_max_pending: u32) {{",
+                record.rust.name
+            )
+            .unwrap();
+        } else {
+            writeln!(output, "pub unsafe fn {}() {{", record.rust.name).unwrap();
+        }
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    for record in cp_async_mbarriers(catalog) {
+        let bridge = record
+            .cp_async_mbarrier
+            .as_ref()
+            .expect("cp.async mbarrier semantics");
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::async_copy::"))
+            .expect("cp.async mbarrier compatibility path");
+        assert_eq!(
+            path,
+            &format!("cuda_device::async_copy::{}", record.rust.name)
+        );
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
+        output.push_str("///\n/// # Safety\n");
+        output.push_str(
+            "/// `barrier` must point to a live, initialized, eight-byte-aligned mbarrier object in shared memory.\n\
+             /// This thread must have issued the `cp.async` operations being associated with it.\n\
+             /// The object must remain valid until those operations complete.\n",
+        );
+        match bridge.operation {
+            CpAsyncMbarrierOperation::Arrive => output.push_str(
+                "/// This form increments the pending count before scheduling the asynchronous arrival.\n\
+                 /// That increment must not exceed the barrier's pending-count limit.\n",
+            ),
+            CpAsyncMbarrierOperation::ArriveNoInc => output.push_str(
+                "/// The initial pending count must already include the asynchronous arrival.\n",
+            ),
+        }
+        output.push_str("#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub unsafe fn {}(_barrier: *mut crate::barrier::Barrier) {{",
+            record.rust.name
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_mbarrier_basic(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::barrier` to keep existing paths stable.\n\n");
+    for record in mbarrier_basics(catalog) {
+        let mbarrier = record
+            .mbarrier_basic
+            .as_ref()
+            .expect("basic mbarrier semantics");
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::barrier::"))
+            .expect("basic mbarrier compatibility path");
+        assert_eq!(path, &format!("cuda_device::barrier::{}", record.rust.name));
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
+        output.push_str("///\n/// # Safety\n");
+        output.push_str(
+            "/// `bar` must point to a live, eight-byte-aligned `Barrier` in shared memory.\n",
+        );
+        match mbarrier.operation {
+            MbarrierBasicOperation::Init => output.push_str(
+                "/// Exactly one thread may initialize it. `expected_count` must be in `1..=0xFFFFF` and include every arrival in the phase.\n\
+                 /// The barrier must be uninitialized or invalidated, with no concurrent barrier operation.\n",
+            ),
+            MbarrierBasicOperation::Arrive => output.push_str(
+                "/// The barrier must be initialized, and this arrival must be included in the current phase's expected count.\n\
+                 /// Use the returned token only with this barrier and phase.\n",
+            ),
+            MbarrierBasicOperation::TestWait => output.push_str(
+                "/// The barrier must be initialized. `token` must come from this barrier and phase.\n",
+            ),
+            MbarrierBasicOperation::Inval => output.push_str(
+                "/// The barrier must be initialized and unused by all threads and asynchronous operations.\n\
+                 /// Exactly one thread may invalidate it.\n",
+            ),
+        }
+        output.push_str("#[inline(never)]\n");
+        match mbarrier.operation {
+            MbarrierBasicOperation::Init => {
+                writeln!(
+                    output,
+                    "pub unsafe fn {}(bar: *mut Barrier, expected_count: u32) {{",
+                    record.rust.name
+                )
+                .unwrap();
+                output.push_str("    let _ = (bar, expected_count);\n");
+            }
+            MbarrierBasicOperation::Arrive => {
+                writeln!(
+                    output,
+                    "pub unsafe fn {}(bar: *const Barrier) -> u64 {{",
+                    record.rust.name
+                )
+                .unwrap();
+                output.push_str("    let _ = bar;\n");
+            }
+            MbarrierBasicOperation::TestWait => {
+                writeln!(
+                    output,
+                    "pub unsafe fn {}(bar: *const Barrier, token: u64) -> bool {{",
+                    record.rust.name
+                )
+                .unwrap();
+                output.push_str("    let _ = (bar, token);\n");
+            }
+            MbarrierBasicOperation::Inval => {
+                writeln!(
+                    output,
+                    "pub unsafe fn {}(bar: *mut Barrier) {{",
+                    record.rust.name
+                )
+                .unwrap();
+                output.push_str("    let _ = bar;\n");
+            }
+        }
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_mbarrier_extended(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::barrier` to keep existing paths stable.\n\n");
+    for record in mbarrier_extended(catalog) {
+        let contract = record
+            .mbarrier_extended
+            .as_ref()
+            .expect("extended-mbarrier contract");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
+        output.push_str("///\n/// # Safety\n");
+        output.push_str(
+            "/// The caller must satisfy the barrier, scope, and memory-ordering contract.\n",
+        );
+        output.push_str("#[inline(never)]\n");
+        match contract.operation {
+            MbarrierExtendedOperation::ArriveExpectTxCta
+            | MbarrierExtendedOperation::ArriveExpectTxCluster => {
+                writeln!(
+                    output,
+                    "pub unsafe fn {}(bar: *const Barrier, _tx_count: u32, bytes: u32) -> u64 {{",
+                    record.rust.name
+                )
+                .unwrap();
+                output.push_str("    let _ = (bar, bytes);\n");
+            }
+            MbarrierExtendedOperation::ArriveRemoteCluster => {
+                writeln!(
+                    output,
+                    "pub unsafe fn {}(remote_bar_addr: u64) {{",
+                    record.rust.name
+                )
+                .unwrap();
+                output.push_str("    let _ = remote_bar_addr;\n");
+            }
+            MbarrierExtendedOperation::TryWaitTokenCta => {
+                writeln!(
+                    output,
+                    "pub unsafe fn {}(bar: *const Barrier, token: u64) -> bool {{",
+                    record.rust.name
+                )
+                .unwrap();
+                output.push_str("    let _ = (bar, token);\n");
+            }
+            MbarrierExtendedOperation::TryWaitParityCta
+            | MbarrierExtendedOperation::TryWaitParityCluster => {
+                writeln!(
+                    output,
+                    "pub unsafe fn {}(bar: *const Barrier, parity: u32) -> bool {{",
+                    record.rust.name
+                )
+                .unwrap();
+                output.push_str("    let _ = (bar, parity);\n");
+            }
+            MbarrierExtendedOperation::FenceProxyAsyncSharedCta
+            | MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster
+            | MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster
+            | MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster => {
+                writeln!(output, "pub unsafe fn {}() {{", record.rust.name).unwrap();
+            }
+            MbarrierExtendedOperation::Nanosleep => {
+                writeln!(output, "pub unsafe fn {}(ns: u32) {{", record.rust.name).unwrap();
+                output.push_str("    let _ = ns;\n");
+            }
+        }
+        writeln!(
+            output,
+            "    unreachable!(\"{} called outside CUDA kernel context\")",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_integer_minmax(
+    catalog: &CatalogFile,
+    hash: &str,
+    module: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    writeln!(
+        output,
+        "// Included inside `cuda_device::{module}` to keep existing paths stable.\n"
+    )
+    .unwrap();
+    for record in integer_minmaxes(catalog).filter(|record| record.rust.module == module) {
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with(&format!("cuda_device::{module}::")))
+            .expect("integer-min/max compatibility path");
+        let scalar = &record.rust.result;
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("#[must_use]\n#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub fn {}(arg0: {scalar}, arg1: {scalar}) -> {scalar} {{",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("    let _ = (arg0, arg1);\n");
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    output
+}
+
+pub(super) fn render_compat_packed_alu(
+    catalog: &CatalogFile,
+    hash: &str,
+    format: PackedAluFormat,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    let (module, _, _, _, _) = packed_alu_format_shape(format);
+    writeln!(
+        output,
+        "// Included inside `cuda_device::{module}` to keep existing paths stable.\n"
+    )
+    .unwrap();
+    for record in packed_alus(catalog).filter(|record| {
+        record
+            .packed_alu
+            .as_ref()
+            .is_some_and(|packed| packed.format == format)
+    }) {
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with(&format!("cuda_device::{module}::")))
+            .expect("packed-ALU compatibility path");
+        let arguments = record
+            .rust
+            .arguments
+            .iter()
+            .enumerate()
+            .map(|(index, ty)| format!("arg{index}: {ty}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let values = (0..record.rust.arguments.len())
+            .map(|index| format!("arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        if record.rust.must_use {
+            output.push_str("#[must_use]\n");
+        }
+        output.push_str("#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub fn {}({arguments}) -> {} {{",
+            record.rust.name, record.rust.result
+        )
+        .unwrap();
+        if record.rust.arguments.len() == 1 {
+            writeln!(output, "    let _ = {values};").unwrap();
+        } else {
+            writeln!(output, "    let _ = ({values});").unwrap();
+        }
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    render_compat_extended_minmax_into(&mut output, catalog, module);
+    output
+}
+
+pub(super) fn render_compat_scalar_minmax(
+    catalog: &CatalogFile,
+    hash: &str,
+    module: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    writeln!(
+        output,
+        "// Included inside `cuda_device::{module}` to keep existing paths stable.\n"
+    )
+    .unwrap();
+    render_compat_extended_minmax_into(&mut output, catalog, module);
+    output
+}
+
+fn render_compat_extended_minmax_into(output: &mut String, catalog: &CatalogFile, module: &str) {
+    for record in extended_minmax(catalog).filter(|record| record.rust.module == module) {
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with(&format!("cuda_device::{module}::")))
+            .expect("extended-minmax compatibility path");
+        let ty = extended_minmax_rust_type(record);
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("#[must_use]\n#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub fn {}(a: {ty}, b: {ty}) -> {ty} {{",
+            record.rust.name
+        )
+        .unwrap();
+        output.push_str("    let _ = (a, b);\n");
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+}
+
+pub(super) fn render_compat_packed_conversion(
+    catalog: &CatalogFile,
+    hash: &str,
+    path_prefix: &str,
+    containing_module: &str,
+    argument_names: (&str, &str),
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    writeln!(
+        output,
+        "// Included inside `cuda_device::{containing_module}`.\n"
+    )
+    .unwrap();
+    for record in packed_conversions(catalog).filter(|record| {
+        record
+            .rust
+            .compatibility_paths
+            .iter()
+            .any(|path| path.starts_with(path_prefix))
+    }) {
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with(path_prefix))
+            .expect("packed-conversion compatibility path");
+        // A packed source arrives in one register, so the parameter list
+        // follows the record's own argument types rather than a fixed f32 pair.
+        let parameter_names: Vec<&str> = match packed_conversion_source(record) {
+            PackedConversionSourceFormat::F32x2 => vec![argument_names.0, argument_names.1],
+            PackedConversionSourceFormat::E4m3x2
+            | PackedConversionSourceFormat::E5m2x2
+            | PackedConversionSourceFormat::F16x2 => vec!["packed"],
+        };
+        let parameter_types = packed_conversion_rust_arguments(record);
+        let parameters = parameter_names
+            .iter()
+            .zip(&parameter_types)
+            .map(|(name, ty)| format!("{name}: {ty}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let discards = parameter_names.join(", ");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub fn {}({parameters}) -> {} {{",
+            path.rsplit("::")
+                .next()
+                .expect("packed-conversion compatibility function name"),
+            record.rust.result,
+        )
+        .unwrap();
+        if parameter_names.len() == 1 {
+            writeln!(output, "    let _ = {discards};").unwrap();
+        } else {
+            writeln!(output, "    let _ = ({discards});").unwrap();
+        }
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    if containing_module == "convert" {
+        for record in scalar_conversions(catalog) {
+            let path = record
+                .rust
+                .compatibility_paths
+                .iter()
+                .find(|path| path.starts_with("cuda_device::convert::"))
+                .expect("scalar-conversion compatibility path");
+            writeln!(output, "/// {}", record.summary).unwrap();
+            output.push_str("#[must_use]\n#[inline(never)]\n");
+            writeln!(output, "pub fn {}(value: f32) -> u32 {{", record.rust.name).unwrap();
+            output.push_str("    let _ = value;\n");
+            writeln!(
+                output,
+                "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+            )
+            .unwrap();
+            output.push_str("}\n\n");
+        }
+    }
+    output
+}
+
+pub(super) fn render_compat_float(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("// Included inside `cuda_device::float`.\n\n");
+    for record in scalar_arithmetics(catalog) {
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::float::"))
+            .expect("scalar-arithmetic compatibility path");
+        let ty = scalar_arithmetic_rust_type(record);
+        let arity = scalar_arithmetic_arity(record);
+        let parameters = (0..arity)
+            .map(|index| format!("arg{index}: {ty}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let arguments = (0..arity)
+            .map(|index| format!("arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("#[must_use]\n#[inline(never)]\n");
+        writeln!(
+            output,
+            "pub fn {}({parameters}) -> {ty} {{",
+            record.rust.name
+        )
+        .unwrap();
+        writeln!(output, "    let _ = ({arguments});").unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    for record in scalar_maths(catalog) {
+        let path = record
+            .rust
+            .compatibility_paths
+            .iter()
+            .find(|path| path.starts_with("cuda_device::float::"))
+            .expect("scalar-math compatibility path");
+        let ty = match scalar_math_contract(record).format {
+            ScalarMathFormat::F16 => "u16",
+            ScalarMathFormat::F32 => "f32",
+            ScalarMathFormat::F64 => "f64",
+        };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("#[must_use]\n#[inline(never)]\n");
+        writeln!(output, "pub fn {}(arg0: {ty}) -> {ty} {{", record.rust.name).unwrap();
+        writeln!(output, "    let _ = arg0;").unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{path}` executed outside device compilation\")"
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    render_compat_extended_minmax_into(&mut output, catalog, "float");
+    output
+}
+
+pub(super) fn render_compat_float_output(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> Option<(PathBuf, String)> {
+    (scalar_arithmetics(catalog).next().is_some()
+        || extended_minmax(catalog).next().is_some()
+        || scalar_maths(catalog).next().is_some())
+    .then(|| {
+        (
+            "crates/cuda-device/src/generated/float.rs".into(),
+            render_compat_float(catalog, hash),
+        )
+    })
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/dialect/cluster_tensor.rs b/crates/cuda-intrinsics-gen/src/render/dialect/cluster_tensor.rs
new file mode 100644
index 0000000000..0a66d7d299
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/dialect/cluster_tensor.rs
@@ -0,0 +1,903 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{CatalogFile, Tcgen05Adapter};
+use crate::render::common::rust_header;
+use crate::render::families::{
+    clc_intrinsics, cluster_barriers, cluster_memory, debug_controls, execution_control_family,
+    execution_controls, render_tcgen05_carrier_runs, tcgen05_intrinsics, tcgen05_mma_intrinsics,
+    tcgen05_non_mma_intrinsics, tma_intrinsics, wgmma_controls,
+};
+use std::fmt::Write as _;
+
+pub(in crate::render) fn render_dialect_cluster_barrier(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    if cluster_barriers(catalog).next().is_none() {
+        return output;
+    }
+    output.push_str(
+        r##"//! Generated operations for the closed cluster-barrier family.
+
+use pliron::{
+    attribute::Attribute,
+    builtin::op_interfaces::{NOpdsInterface, NResultsInterface},
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[pliron_attr(name = "nvvm.cluster_barrier_mode", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ClusterBarrierModeAttr {
+    Arrive,
+    ArriveAligned,
+    ArriveRelaxed,
+    ArriveRelaxedAligned,
+    Wait,
+    WaitAligned,
+}
+
+/// Cluster synchronization whose exact spelling is carried by an attribute.
+#[pliron_op(
+    name = "nvvm.cluster_barrier",
+    format,
+    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],
+    attributes = (nvvm_cluster_barrier_mode: ClusterBarrierModeAttr)
+)]
+pub struct ClusterBarrierOp;
+
+impl ClusterBarrierOp {
+    pub fn new(op: Ptr<Operation>) -> Self {
+        Self { op }
+    }
+
+    pub fn build(ctx: &mut Context, mode: ClusterBarrierModeAttr) -> Ptr<Operation> {
+        let op = Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0);
+        let this = Self { op };
+        this.set_attr_nvvm_cluster_barrier_mode(ctx, mode);
+        this.get_operation()
+    }
+}
+
+impl Verify for ClusterBarrierOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let op = self.get_operation().deref(ctx);
+        if self.get_attr_nvvm_cluster_barrier_mode(ctx).is_none() {
+            return verify_err!(op.loc(), "nvvm.cluster_barrier requires a mode attribute");
+        }
+        if op.get_num_operands() != 0 || op.get_num_results() != 0 {
+            return verify_err!(op.loc(), "nvvm.cluster_barrier takes no operands or results");
+        }
+        Ok(())
+    }
+}
+
+/// Compatibility operation for a complete aligned cluster synchronization.
+#[pliron_op(
+    name = "nvvm.cluster_sync",
+    format,
+    verifier = "succ",
+    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],
+)]
+pub struct ClusterSyncOp;
+
+impl ClusterSyncOp {
+    pub fn new(op: Ptr<Operation>) -> Self {
+        Self { op }
+    }
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    ClusterBarrierModeAttr::register(ctx);
+    ClusterBarrierOp::register(ctx);
+    ClusterSyncOp::register(ctx);
+}
+"##,
+    );
+    output
+}
+
+pub(in crate::render) fn render_dialect_cluster_memory(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> String {
+    assert_eq!(cluster_memory(catalog).count(), 2);
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r#"//! Structural operations for cluster address mapping and remote shared reads.
+
+use dialect_mir::types::{MirPointerKind, MirPtrType, address_space};
+use pliron::{
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        types::{IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::pliron_op;
+
+fn verify_pointer_rank(
+    ctx: &Context,
+    operation: Ptr<Operation>,
+    name: &str,
+) -> Result<(), Error> {
+    let op = operation.deref(ctx);
+    if op.get_num_operands() != 2 || op.get_num_results() != 1 {
+        return verify_err!(op.loc(), "{name} requires two operands and one result");
+    }
+    if op
+        .get_operand(0)
+        .get_type(ctx)
+        .deref(ctx)
+        .downcast_ref::<MirPtrType>()
+        .is_none()
+    {
+        return verify_err!(op.loc(), "{name} source must be a MIR pointer");
+    }
+    let rank_ty = op.get_operand(1).get_type(ctx);
+    let rank_ty = rank_ty.deref(ctx);
+    if !rank_ty
+        .downcast_ref::<IntegerType>()
+        .is_some_and(|ty| ty.width() == 32 && ty.signedness() == Signedness::Unsigned)
+    {
+        return verify_err!(op.loc(), "{name} rank must be u32");
+    }
+    Ok(())
+}
+
+#[pliron_op(
+    name = "nvvm.mapa_shared_cluster",
+    format,
+    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
+)]
+pub struct MapaSharedClusterOp;
+
+impl MapaSharedClusterOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+
+    // Kind-preserving addrspace retype: copies the source pointer's kind
+    // verbatim; concrete kinds are minted only in mir-importer's facts.rs.
+    #[allow(clippy::disallowed_methods)]
+    pub fn build(ctx: &mut Context, source: Value, rank: Value) -> Ptr<Operation> {
+        let source_ty = source.get_type(ctx);
+        let (pointee, is_mutable, pointer_kind) = {
+            let source_ty_obj = source_ty.deref(ctx);
+            let source_ptr = source_ty_obj
+                .downcast_ref::<MirPtrType>()
+                .expect("nvvm.mapa_shared_cluster source must be a MIR pointer");
+            (
+                source_ptr.pointee,
+                source_ptr.is_mutable(),
+                source_ptr.pointer_kind(),
+            )
+        };
+        let result_ty = MirPtrType::get_with_kind(
+            ctx,
+            pointee,
+            is_mutable,
+            address_space::CLUSTER_SHARED,
+            pointer_kind,
+        );
+        Operation::new(
+            ctx,
+            Self::get_concrete_op_info(),
+            vec![result_ty.into()],
+            vec![source, rank],
+            vec![],
+            0,
+        )
+    }
+}
+
+impl Verify for MapaSharedClusterOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let operation = self.get_operation();
+        verify_pointer_rank(ctx, operation, "nvvm.mapa_shared_cluster")?;
+        let op = operation.deref(ctx);
+        let source_ty = op.get_operand(0).get_type(ctx);
+        let result_ty = op.get_result(0).get_type(ctx);
+        let source_ty_obj = source_ty.deref(ctx);
+        let result_ty_obj = result_ty.deref(ctx);
+        let source_ptr = source_ty_obj.downcast_ref::<MirPtrType>().unwrap();
+        let Some(result_ptr) = result_ty_obj.downcast_ref::<MirPtrType>() else {
+            return verify_err!(
+                op.loc(),
+                "nvvm.mapa_shared_cluster result must be a MIR pointer"
+            );
+        };
+        if !matches!(
+            source_ptr.pointer_kind(),
+            MirPointerKind::RawConst | MirPointerKind::RawMut
+        )
+            || result_ptr.pointee != source_ptr.pointee
+            || result_ptr.is_mutable() != source_ptr.is_mutable()
+            || !result_ptr.is_cluster_shared()
+            || result_ptr.pointer_kind() != source_ptr.pointer_kind()
+        {
+            return verify_err!(
+                op.loc(),
+                "nvvm.mapa_shared_cluster requires a raw source pointer and must preserve its pointee, mutability, and raw kind while returning addrspace(7)"
+            );
+        }
+        Ok(())
+    }
+}
+
+#[pliron_op(
+    name = "nvvm.dsmem_read_u32",
+    format,
+    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
+)]
+pub struct DsmemReadU32Op;
+
+impl DsmemReadU32Op {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+
+    pub fn build(ctx: &mut Context, source: Value, rank: Value) -> Ptr<Operation> {
+        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
+        Operation::new(
+            ctx,
+            Self::get_concrete_op_info(),
+            vec![result_ty.to_handle()],
+            vec![source, rank],
+            vec![],
+            0,
+        )
+    }
+}
+
+impl Verify for DsmemReadU32Op {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let operation = self.get_operation();
+        verify_pointer_rank(ctx, operation, "nvvm.dsmem_read_u32")?;
+        let op = operation.deref(ctx);
+        let result_ty = op.get_result(0).get_type(ctx);
+        let result_ty = result_ty.deref(ctx);
+        if !result_ty
+            .downcast_ref::<IntegerType>()
+            .is_some_and(|ty| ty.width() == 32 && ty.signedness() == Signedness::Unsigned)
+        {
+            return verify_err!(op.loc(), "nvvm.dsmem_read_u32 result must be u32");
+        }
+        Ok(())
+    }
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    MapaSharedClusterOp::register(ctx);
+    DsmemReadU32Op::register(ctx);
+}
+"#,
+    );
+    output
+}
+
+pub(in crate::render) fn render_dialect_wgmma_control(catalog: &CatalogFile, hash: &str) -> String {
+    assert_eq!(wgmma_controls(catalog).count(), 3);
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r##"//! Structural operations for generated WGMMA controls.
+
+use pliron::{
+    builtin::{op_interfaces::{NOpdsInterface, NResultsInterface}, types::IntegerType},
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::{TypeHandle, Typed},
+    value::Value,
+    verify_err,
+};
+use pliron_derive::pliron_op;
+
+#[pliron_op(
+    name = "nvvm.wgmma_fence_sync_aligned",
+    format,
+    verifier = "succ",
+    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],
+)]
+pub struct WgmmaFenceSyncAlignedOp;
+
+impl WgmmaFenceSyncAlignedOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+
+    pub fn build(ctx: &mut Context) -> Ptr<Operation> {
+        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)
+    }
+}
+
+#[pliron_op(
+    name = "nvvm.wgmma_commit_group_sync_aligned",
+    format,
+    verifier = "succ",
+    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],
+)]
+pub struct WgmmaCommitGroupSyncAlignedOp;
+
+impl WgmmaCommitGroupSyncAlignedOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+
+    pub fn build(ctx: &mut Context) -> Ptr<Operation> {
+        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)
+    }
+}
+
+#[pliron_op(
+    name = "nvvm.wgmma_wait_group_sync_aligned",
+    format,
+    interfaces = [NOpdsInterface<1>, NResultsInterface<0>],
+)]
+pub struct WgmmaWaitGroupSyncAlignedOp;
+
+impl WgmmaWaitGroupSyncAlignedOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+
+    pub fn build(ctx: &mut Context, max_pending: Value) -> Ptr<Operation> {
+        Operation::new(
+            ctx,
+            Self::get_concrete_op_info(),
+            vec![],
+            vec![max_pending],
+            vec![],
+            0,
+        )
+    }
+}
+
+impl Verify for WgmmaWaitGroupSyncAlignedOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let op = self.get_operation().deref(ctx);
+        if op.get_num_operands() != 1 || op.get_num_results() != 0 {
+            return verify_err!(op.loc(), "nvvm.wgmma_wait_group_sync_aligned takes one operand and no results");
+        }
+        if !is_i64(ctx, op.get_operand(0).get_type(ctx)) {
+            return verify_err!(op.loc(), "nvvm.wgmma_wait_group_sync_aligned operand must be i64");
+        }
+        Ok(())
+    }
+}
+
+fn is_i64(ctx: &Context, ty: TypeHandle) -> bool {
+    ty.deref(ctx)
+        .downcast_ref::<IntegerType>()
+        .is_some_and(|integer| integer.width() == 64)
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    WgmmaFenceSyncAlignedOp::register(ctx);
+    WgmmaCommitGroupSyncAlignedOp::register(ctx);
+    WgmmaWaitGroupSyncAlignedOp::register(ctx);
+}
+"##,
+    );
+    output
+}
+
+pub(in crate::render) fn render_dialect_debug_control(catalog: &CatalogFile, hash: &str) -> String {
+    assert_eq!(debug_controls(catalog).count(), 3);
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operations for generated PTX debug controls.\n\n\
+         use pliron::{\n\
+             builtin::{\n\
+                 attributes::IntegerAttr,\n\
+                 op_interfaces::{NOpdsInterface, NResultsInterface},\n\
+                 types::{IntegerType, Signedness},\n\
+             },\n\
+             common_traits::Verify,\n\
+             context::{Context, Ptr},\n\
+             identifier::Identifier,\n\
+             location::Located,\n\
+             op::Op,\n\
+             operation::Operation,\n\
+             result::Error,\n\
+             verify_err,\n\
+         };\n\
+         use pliron::utils::apint::APInt;\n\
+         use pliron_derive::pliron_op;\n\
+         use std::num::NonZeroUsize;\n\n\
+         #[pliron_op(\n\
+             name = \"nvvm.trap\",\n\
+             format,\n\
+             verifier = \"succ\",\n\
+             interfaces = [NOpdsInterface<0>, NResultsInterface<0>],\n\
+         )]\n\
+         pub struct TrapOp;\n\n\
+         impl TrapOp {\n\
+             pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\
+             pub fn build(ctx: &mut Context) -> Ptr<Operation> {\n\
+                 Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)\n\
+             }\n\
+         }\n\n\
+         #[pliron_op(\n\
+             name = \"nvvm.brkpt\",\n\
+             format,\n\
+             verifier = \"succ\",\n\
+             interfaces = [NOpdsInterface<0>, NResultsInterface<0>],\n\
+         )]\n\
+         pub struct BreakpointOp;\n\n\
+         impl BreakpointOp {\n\
+             pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\
+             pub fn build(ctx: &mut Context) -> Ptr<Operation> {\n\
+                 Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)\n\
+             }\n\
+         }\n\n\
+         #[pliron_op(\n\
+             name = \"nvvm.pmevent\",\n\
+             format,\n\
+             interfaces = [NOpdsInterface<0>, NResultsInterface<0>],\n\
+         )]\n\
+         pub struct PmEventOp;\n\n\
+         impl PmEventOp {\n\
+             pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n\
+             pub fn build(ctx: &mut Context, event_id: u32) -> Ptr<Operation> {\n\
+                 let op = Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0);\n\
+                 let ty = IntegerType::get(ctx, 32, Signedness::Unsigned);\n\
+                 let value = APInt::from_u64(event_id.into(), NonZeroUsize::new(32).unwrap());\n\
+                 op.deref_mut(ctx).attributes.set(\n\
+                     Identifier::try_from(\"event_id\").unwrap(),\n\
+                     IntegerAttr::new(ty, value),\n\
+                 );\n\
+                 op\n\
+             }\n\n\
+             pub fn new_with_event_id(ctx: &mut Context, event_id: u32) -> Ptr<Operation> {\n\
+                 Self::build(ctx, event_id)\n\
+             }\n\n\
+             pub fn event_id(&self, ctx: &Context) -> Option<u32> {\n\
+                 let key = Identifier::try_from(\"event_id\").unwrap();\n\
+                 let operation = self.get_operation().deref(ctx);\n\
+                 let attribute: &IntegerAttr = operation.attributes.get(&key)?;\n\
+                 let ty_handle = attribute.get_type();\n\
+                 let ty = ty_handle.deref(ctx);\n\
+                 if ty.width() != 32 || ty.signedness() != Signedness::Unsigned {\n\
+                     return None;\n\
+                 }\n\
+                 u32::try_from(attribute.value().to_u64()).ok().filter(|value| *value <= 15)\n\
+             }\n\
+\n\
+             pub fn get_event_id(&self, ctx: &Context) -> Option<u32> {\n\
+                 self.event_id(ctx)\n\
+             }\n\
+         }\n\n\
+         impl Verify for PmEventOp {\n\
+             fn verify(&self, ctx: &Context) -> Result<(), Error> {\n\
+                 let op = self.get_operation().deref(ctx);\n\
+                 if self.event_id(ctx).is_none() {\n\
+                     return verify_err!(op.loc(), \"nvvm.pmevent requires a u32 event ID in 0..=15\");\n\
+                 }\n\
+                 Ok(())\n\
+             }\n\
+         }\n\n\
+         pub(super) fn register(ctx: &mut Context) {\n\
+             TrapOp::register(ctx);\n\
+             BreakpointOp::register(ctx);\n\
+             PmEventOp::register(ctx);\n\
+         }\n",
+    );
+    output
+}
+
+pub(in crate::render) fn render_dialect_clc(catalog: &CatalogFile, hash: &str) -> String {
+    assert_eq!(clc_intrinsics(catalog).count(), 6);
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Generated Cluster Launch Control operations.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::IntegerType,\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::{TypeHandle, Typed},\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\n",
+    );
+    for record in clc_intrinsics(catalog) {
+        let result_count = record.dialect.results.len();
+        let verifier = if result_count == 0 {
+            "    verifier = \"succ\",\n"
+        } else {
+            ""
+        };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n{verifier}    interfaces = [NOpdsInterface<2>, NResultsInterface<{result_count}>],\n)]",
+            record.dialect.op_name,
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n}\n\n");
+        if result_count == 1 {
+            writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
+            writeln!(
+                output,
+                "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_query_shape(ctx, self.get_operation(), {:?})\n    }}\n}}\n",
+                record.dialect.op_name,
+            )
+            .unwrap();
+        }
+    }
+    output.push_str(
+        "fn verify_query_shape(\n    ctx: &Context,\n    operation: Ptr<Operation>,\n    name: &str,\n) -> Result<(), Error> {\n    let op = operation.deref(ctx);\n    let valid = op.get_num_operands() == 2\n        && op.get_num_results() == 1\n        && is_integer_width(ctx, op.get_operand(0).get_type(ctx), 64)\n        && is_integer_width(ctx, op.get_operand(1).get_type(ctx), 64)\n        && is_integer_width(ctx, op.get_result(0).get_type(ctx), 32);\n    if !valid {\n        return verify_err!(\n            op.loc(),\n            \"{} requires two i64 operands and one i32 result\",\n            name\n        );\n    }\n    Ok(())\n}\n\nfn is_integer_width(ctx: &Context, ty: TypeHandle, width: u32) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\npub(super) fn register(ctx: &mut Context) {\n",
+    );
+    for record in clc_intrinsics(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_execution_control(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> String {
+    assert_eq!(execution_controls(catalog).count(), 8);
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Generated counted-barrier, grid-dependency, and register-control operations.\n\nuse pliron::{\n    builtin::{attributes::IntegerAttr, op_interfaces::{NOpdsInterface, NResultsInterface}, types::{IntegerType, Signedness}},\n    common_traits::Verify,\n    context::{Context, Ptr},\n    identifier::Identifier,\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    verify_err,\n};\nuse pliron::utils::apint::APInt;\nuse pliron_derive::pliron_op;\nuse std::num::NonZeroUsize;\n\n",
+    );
+    for record in execution_controls(catalog).filter(|record| record.family != "register_control") {
+        let operand_count = record.dialect.operands.len();
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    verifier = \"succ\",\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<0>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n}\n\n");
+    }
+    for record in execution_control_family(catalog, "register_control") {
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str(
+            "    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n    pub fn build(ctx: &mut Context, register_count: u32) -> Ptr<Operation> {\n        let op = Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0);\n        let ty = IntegerType::get(ctx, 32, Signedness::Unsigned);\n        let value = APInt::from_u64(register_count.into(), NonZeroUsize::new(32).unwrap());\n        op.deref_mut(ctx).attributes.set(\n            Identifier::try_from(\"register_count\").unwrap(),\n            IntegerAttr::new(ty, value),\n        );\n        op\n    }\n\n    pub fn register_count(&self, ctx: &Context) -> Option<u32> {\n        let key = Identifier::try_from(\"register_count\").unwrap();\n        let operation = self.get_operation().deref(ctx);\n        let attribute: &IntegerAttr = operation.attributes.get(&key)?;\n        let ty_handle = attribute.get_type();\n        let ty = ty_handle.deref(ctx);\n        if ty.width() != 32 || ty.signedness() != Signedness::Unsigned {\n            return None;\n        }\n        u32::try_from(attribute.value().to_u64()).ok().filter(|value| (24..=256).contains(value) && value % 8 == 0)\n    }\n}\n\n",
+        );
+        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
+        output.push_str(
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {\n        let op = self.get_operation().deref(ctx);\n        if self.register_count(ctx).is_none() {\n            return verify_err!(op.loc(), \"setmaxnreg requires an immediate register count in 24..=256 divisible by 8\");\n        }\n        Ok(())\n    }\n}\n\n",
+        );
+    }
+    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
+    for record in execution_controls(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_tma(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Generated Tensor Memory Accelerator operations.\n\nuse pliron::{\n    builtin::op_interfaces::{NOpdsInterface, NResultsInterface},\n    context::{Context, Ptr},\n    op::Op,\n    operation::Operation,\n};\nuse pliron_derive::pliron_op;\n\n",
+    );
+    for record in tma_intrinsics(catalog) {
+        let operand_count = record.dialect.operands.len();
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    verifier = \"succ\",\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<0>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n}\n\n");
+    }
+    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
+    for record in tma_intrinsics(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_tcgen05(catalog: &CatalogFile, hash: &str) -> String {
+    assert_eq!(tcgen05_intrinsics(catalog).count(), 233);
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r#"//! Generated Tensor Core Generation 5 operations.
+
+use dialect_mir::{ops::MirConstantOp, types::MirPtrType};
+use pliron::{
+    attribute::Attribute,
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        ops::ConstantOp,
+        types::{FP32Type, IntegerType},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::{TypeHandle, Typed},
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[derive(Clone, Copy)]
+enum Tcgen05Carrier {
+    Ptr,
+    I1,
+    I16,
+    I32,
+    I64,
+    F32,
+}
+
+impl Tcgen05Carrier {
+    fn matches(self, ctx: &Context, ty: TypeHandle) -> bool {
+        match self {
+            Self::Ptr => ty.deref(ctx).downcast_ref::<MirPtrType>().is_some(),
+            Self::I1 => is_integer_width(ctx, ty, 1),
+            Self::I16 => is_integer_width(ctx, ty, 16),
+            Self::I32 => is_integer_width(ctx, ty, 32),
+            Self::I64 => is_integer_width(ctx, ty, 64),
+            Self::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
+        }
+    }
+
+    fn name(self) -> &'static str {
+        match self {
+            Self::Ptr => "MIR pointer",
+            Self::I1 => "i1",
+            Self::I16 => "i16",
+            Self::I32 => "i32",
+            Self::I64 => "i64",
+            Self::F32 => "f32",
+        }
+    }
+}
+
+fn is_integer_width(ctx: &Context, ty: TypeHandle, width: u32) -> bool {
+    ty.deref(ctx)
+        .downcast_ref::<IntegerType>()
+        .is_some_and(|integer| integer.width() == width)
+}
+
+fn expected_carrier_count(runs: &[(Tcgen05Carrier, usize)]) -> usize {
+    runs.iter().map(|(_, count)| *count).sum()
+}
+
+fn verify_tcgen05_signature(
+    ctx: &Context,
+    operation: Ptr<Operation>,
+    name: &str,
+    operand_runs: &[(Tcgen05Carrier, usize)],
+    result_runs: &[(Tcgen05Carrier, usize)],
+    constant_operand: Option<usize>,
+) -> Result<(), Error> {
+    let op = operation.deref(ctx);
+    let expected_operands = expected_carrier_count(operand_runs);
+    let expected_results = expected_carrier_count(result_runs);
+    if op.get_num_operands() != expected_operands || op.get_num_results() != expected_results {
+        return verify_err!(
+            op.loc(),
+            "{name} requires {expected_operands} operands and {expected_results} results"
+        );
+    }
+
+    let mut index = 0;
+    for (carrier, count) in operand_runs {
+        for _ in 0..*count {
+            if !carrier.matches(ctx, op.get_operand(index).get_type(ctx)) {
+                return verify_err!(
+                    op.loc(),
+                    "{name} operand {index} must be {}",
+                    carrier.name()
+                );
+            }
+            index += 1;
+        }
+    }
+
+    index = 0;
+    for (carrier, count) in result_runs {
+        for _ in 0..*count {
+            if !carrier.matches(ctx, op.get_result(index).get_type(ctx)) {
+                return verify_err!(
+                    op.loc(),
+                    "{name} result {index} must be {}",
+                    carrier.name()
+                );
+            }
+            index += 1;
+        }
+    }
+
+    if let Some(index) = constant_operand {
+        let value = op.get_operand(index);
+        let is_constant = value.defining_op().is_some_and(|defining_op| {
+            Operation::get_op::<MirConstantOp>(defining_op, ctx).is_some()
+                || Operation::get_op::<ConstantOp>(defining_op, ctx).is_some()
+        });
+        if !is_constant {
+            return verify_err!(
+                op.loc(),
+                "{name} operand {index} must be a compile-time constant"
+            );
+        }
+    }
+
+    Ok(())
+}
+
+"#,
+    );
+    if tcgen05_mma_intrinsics(catalog).next().is_some() {
+        output.push_str(
+            r#"#[pliron_attr(name = "nvvm.tcgen05_mma_form", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum Tcgen05MmaFormAttr {
+    Shared, Tensor, TensorAshift, SpShared, SpTensor, SpTensorAshift,
+    WsShared, WsSharedZeroColMask, WsSpShared, WsSpSharedZeroColMask,
+    WsSpTensor, WsSpTensorZeroColMask, WsTensor, WsTensorZeroColMask,
+}
+
+#[pliron_attr(name = "nvvm.tcgen05_mma_kind", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum Tcgen05MmaKindAttr { F16, Tf32, F8f6f4, I8 }
+
+#[pliron_attr(name = "nvvm.tcgen05_mma_cta_group", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum Tcgen05MmaCtaGroupAttr { Cg1, Cg2 }
+
+#[pliron_attr(name = "nvvm.tcgen05_mma_collector_a", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum Tcgen05MmaCollectorAAttr { Discard, LastUse, Fill, Use }
+
+#[pliron_attr(name = "nvvm.tcgen05_mma_b_buffer", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum Tcgen05MmaBBufferAttr { B0, B1, B2, B3 }
+
+#[pliron_attr(name = "nvvm.tcgen05_mma_b_usage", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum Tcgen05MmaBUsageAttr { Discard, LastUse, Fill, Use }
+
+#[pliron_op(
+    name = "nvvm.tcgen05_mma",
+    format,
+    attributes = (
+        nvvm_tcgen05_mma_form: Tcgen05MmaFormAttr,
+        nvvm_tcgen05_mma_kind: Tcgen05MmaKindAttr,
+        nvvm_tcgen05_mma_cta_group: Tcgen05MmaCtaGroupAttr,
+        nvvm_tcgen05_mma_collector_a: Tcgen05MmaCollectorAAttr,
+        nvvm_tcgen05_mma_b_buffer: Tcgen05MmaBBufferAttr,
+        nvvm_tcgen05_mma_b_usage: Tcgen05MmaBUsageAttr
+    )
+)]
+pub struct Tcgen05MmaOp;
+
+impl Tcgen05MmaOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+}
+
+impl Verify for Tcgen05MmaOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        use Tcgen05Carrier::{I1, I32, I64};
+        let op = self.get_operation();
+        let form = self.get_attr_nvvm_tcgen05_mma_form(ctx);
+        let Some(form) = form.as_deref() else {
+            return verify_err!(op.deref(ctx).loc(), "nvvm.tcgen05_mma requires a form");
+        };
+        if self.get_attr_nvvm_tcgen05_mma_kind(ctx).is_none() {
+            return verify_err!(op.deref(ctx).loc(), "nvvm.tcgen05_mma requires a kind");
+        }
+        let (operands, base): (&[(Tcgen05Carrier, usize)], bool) = match form {
+            Tcgen05MmaFormAttr::Shared | Tcgen05MmaFormAttr::WsShared =>
+                (&[(I32, 1), (I64, 2), (I32, 1), (I1, 1)], matches!(form, Tcgen05MmaFormAttr::Shared)),
+            Tcgen05MmaFormAttr::Tensor | Tcgen05MmaFormAttr::TensorAshift | Tcgen05MmaFormAttr::WsTensor =>
+                (&[(I32, 2), (I64, 1), (I32, 1), (I1, 1)], !matches!(form, Tcgen05MmaFormAttr::WsTensor)),
+            Tcgen05MmaFormAttr::SpShared | Tcgen05MmaFormAttr::WsSpShared =>
+                (&[(I32, 1), (I64, 2), (I32, 1), (I1, 1), (I32, 1)], matches!(form, Tcgen05MmaFormAttr::SpShared)),
+            Tcgen05MmaFormAttr::SpTensor | Tcgen05MmaFormAttr::SpTensorAshift | Tcgen05MmaFormAttr::WsSpTensor =>
+                (&[(I32, 2), (I64, 1), (I32, 1), (I1, 1), (I32, 1)], !matches!(form, Tcgen05MmaFormAttr::WsSpTensor)),
+            Tcgen05MmaFormAttr::WsSharedZeroColMask =>
+                (&[(I32, 1), (I64, 2), (I32, 1), (I1, 1), (I64, 1)], false),
+            Tcgen05MmaFormAttr::WsSpSharedZeroColMask =>
+                (&[(I32, 1), (I64, 2), (I32, 1), (I1, 1), (I32, 1), (I64, 1)], false),
+            Tcgen05MmaFormAttr::WsSpTensorZeroColMask =>
+                (&[(I32, 2), (I64, 1), (I32, 1), (I1, 1), (I32, 1), (I64, 1)], false),
+            Tcgen05MmaFormAttr::WsTensorZeroColMask =>
+                (&[(I32, 2), (I64, 1), (I32, 1), (I1, 1), (I64, 1)], false),
+        };
+        verify_tcgen05_signature(ctx, op, "nvvm.tcgen05_mma", operands, &[], None)?;
+
+        let cta_group = self.get_attr_nvvm_tcgen05_mma_cta_group(ctx);
+        let collector_a = self.get_attr_nvvm_tcgen05_mma_collector_a(ctx);
+        let b_buffer = self.get_attr_nvvm_tcgen05_mma_b_buffer(ctx);
+        let b_usage = self.get_attr_nvvm_tcgen05_mma_b_usage(ctx);
+        if base {
+            if cta_group.is_none() || collector_a.is_none() || b_buffer.is_some() || b_usage.is_some() {
+                return verify_err!(op.deref(ctx).loc(), "base tcgen05 MMA requires CTA-group and collector-A selectors");
+            }
+            if matches!(form, Tcgen05MmaFormAttr::TensorAshift | Tcgen05MmaFormAttr::SpTensorAshift)
+                && !matches!(collector_a.as_deref(), Some(Tcgen05MmaCollectorAAttr::Discard | Tcgen05MmaCollectorAAttr::LastUse))
+            {
+                return verify_err!(op.deref(ctx).loc(), "ashift tcgen05 MMA only supports discard or last-use collector-A");
+            }
+        } else if cta_group.is_some() || collector_a.is_some() || b_buffer.is_none() || b_usage.is_none() {
+            return verify_err!(op.deref(ctx).loc(), "warp-specialized tcgen05 MMA requires B-buffer and B-usage selectors");
+        }
+        Ok(())
+    }
+}
+
+"#,
+        );
+    }
+    for record in tcgen05_non_mma_intrinsics(catalog) {
+        let operand_count = record.dialect.operands.len();
+        let result_count = record.dialect.results.len();
+        let operand_runs = render_tcgen05_carrier_runs(&record.dialect.operands);
+        let result_runs = render_tcgen05_carrier_runs(&record.dialect.results);
+        let constant_operand = record
+            .tcgen05
+            .as_ref()
+            .is_some_and(|tcgen05| {
+                matches!(
+                    tcgen05.adapter,
+                    Tcgen05Adapter::TmemHalfSplitOffsetInjectPack16ToU32Registers
+                        | Tcgen05Adapter::TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid
+                )
+            })
+            .then_some(1);
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<{result_count}>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n}\n\n");
+        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    fn verify(&self, ctx: &Context) -> Result<(), Error> {\n");
+        output.push_str("        verify_tcgen05_signature(\n");
+        output.push_str("            ctx,\n");
+        output.push_str("            self.get_operation(),\n");
+        writeln!(output, "            {:?},", record.dialect.op_name).unwrap();
+        writeln!(output, "            {operand_runs},").unwrap();
+        writeln!(output, "            {result_runs},").unwrap();
+        writeln!(output, "            {constant_operand:?},").unwrap();
+        output.push_str("        )\n");
+        output.push_str("    }\n");
+        output.push_str("}\n\n");
+    }
+    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
+    if tcgen05_mma_intrinsics(catalog).next().is_some() {
+        output.push_str(
+            "    Tcgen05MmaFormAttr::register(ctx);\n    Tcgen05MmaKindAttr::register(ctx);\n    Tcgen05MmaCtaGroupAttr::register(ctx);\n    Tcgen05MmaCollectorAAttr::register(ctx);\n    Tcgen05MmaBBufferAttr::register(ctx);\n    Tcgen05MmaBUsageAttr::register(ctx);\n    Tcgen05MmaOp::register(ctx);\n",
+        );
+    }
+    for record in tcgen05_non_mma_intrinsics(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs b/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs
new file mode 100644
index 0000000000..bd793ae84d
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs
@@ -0,0 +1,932 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::CatalogFile;
+use crate::render::common::rust_header;
+use crate::render::families::{
+    ldmatrix, ldmatrix_compat_op, movmatrix, register_mma_attr_variants, register_mma_carriers,
+    register_mma_compat_op_type, register_mmas, sparse_mma_attr_variants, sparse_mma_carriers,
+    sparse_mma_selector_values, sparse_mmas, stmatrices, stmatrix_variant,
+};
+use std::fmt::Write as _;
+
+pub(in crate::render) fn render_dialect_movmatrix(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    if movmatrix(catalog).next().is_none() {
+        output.push_str(
+            "//! Structural operation for generated in-register matrix transpose.\n\nuse pliron::context::Context;\n\npub(super) fn register(_ctx: &mut Context) {}\n",
+        );
+        return output;
+    }
+    let record = movmatrix(catalog).next().unwrap();
+    output.push_str(
+        "//! Structural operation for generated in-register matrix transpose.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\n",
+    );
+    writeln!(output, "/// {}", record.summary).unwrap();
+    writeln!(
+        output,
+        "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<1>],\n)]\npub struct {};\n",
+        record.dialect.op_name, record.dialect.op_type
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "impl {} {{\n    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, value: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![value],\n            vec![],\n            0,\n        )\n    }}\n}}\n",
+        record.dialect.op_type
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "impl Verify for {} {{\n    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 1 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_i32(ctx, op.get_operand(0).get_type(ctx))\n            || !is_i32(ctx, op.get_result(0).get_type(ctx))\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n\npub(super) fn register(ctx: &mut Context) {{\n    {}::register(ctx);\n}}\n",
+        record.dialect.op_type,
+        format!("{} requires one operand and one result", record.dialect.op_name),
+        format!(
+            "{} operand and result must be 32-bit integers",
+            record.dialect.op_name
+        ),
+        record.dialect.op_type,
+    )
+    .unwrap();
+    output
+}
+
+pub(in crate::render) fn render_dialect_ldmatrix(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r##"//! Structural operation and compatibility carriers for generated `ldmatrix`.
+
+use dialect_mir::types::{address_space, MirPtrType};
+use pliron::{
+    attribute::Attribute,
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        types::{IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[pliron_attr(name = "nvvm.ldmatrix_shape", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum LdmatrixShapeAttr {
+    M8n8,
+    M8n16,
+    M16n16,
+}
+
+impl LdmatrixShapeAttr {
+    pub const fn register_count(&self, multiplicity: &LdmatrixMultiplicityAttr) -> usize {
+        let matrices = multiplicity.register_count();
+        match self {
+            Self::M8n8 | Self::M8n16 => matrices,
+            Self::M16n16 => matrices * 2,
+        }
+    }
+}
+
+#[pliron_attr(name = "nvvm.ldmatrix_multiplicity", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum LdmatrixMultiplicityAttr {
+    X1,
+    X2,
+    X4,
+}
+
+impl LdmatrixMultiplicityAttr {
+    pub const fn register_count(&self) -> usize {
+        match self {
+            Self::X1 => 1,
+            Self::X2 => 2,
+            Self::X4 => 4,
+        }
+    }
+}
+
+#[pliron_attr(name = "nvvm.ldmatrix_layout", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum LdmatrixLayoutAttr {
+    Normal,
+    Transposed,
+}
+
+#[pliron_attr(name = "nvvm.ldmatrix_element", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum LdmatrixElementAttr {
+    B16,
+    B8,
+    B8x16B4x16P64,
+    B8x16B6x16P32,
+}
+
+#[pliron_attr(name = "nvvm.ldmatrix_state_space", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum LdmatrixStateSpaceAttr {
+    Shared,
+}
+
+/// A warp-cooperative matrix load whose exact variant is carried by attributes.
+#[pliron_op(
+    name = "nvvm.ldmatrix",
+    format,
+    interfaces = [NOpdsInterface<1>],
+    attributes = (
+        nvvm_ldmatrix_shape: LdmatrixShapeAttr,
+        nvvm_ldmatrix_multiplicity: LdmatrixMultiplicityAttr,
+        nvvm_ldmatrix_layout: LdmatrixLayoutAttr,
+        nvvm_ldmatrix_element: LdmatrixElementAttr,
+        nvvm_ldmatrix_state_space: LdmatrixStateSpaceAttr
+    )
+)]
+pub struct LdmatrixOp;
+
+impl LdmatrixOp {
+    pub fn new(op: Ptr<Operation>) -> Self {
+        Self { op }
+    }
+
+    pub fn build(
+        ctx: &mut Context,
+        address: Value,
+        shape: LdmatrixShapeAttr,
+        multiplicity: LdmatrixMultiplicityAttr,
+        layout: LdmatrixLayoutAttr,
+        element: LdmatrixElementAttr,
+        state_space: LdmatrixStateSpaceAttr,
+    ) -> Ptr<Operation> {
+        let register_count = shape.register_count(&multiplicity);
+        let u32_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
+        let op = Operation::new(
+            ctx,
+            Self::get_concrete_op_info(),
+            vec![u32_ty.into(); register_count],
+            vec![address],
+            vec![],
+            0,
+        );
+        let this = Self { op };
+        this.set_attr_nvvm_ldmatrix_shape(ctx, shape);
+        this.set_attr_nvvm_ldmatrix_multiplicity(ctx, multiplicity);
+        this.set_attr_nvvm_ldmatrix_layout(ctx, layout);
+        this.set_attr_nvvm_ldmatrix_element(ctx, element);
+        this.set_attr_nvvm_ldmatrix_state_space(ctx, state_space);
+        this.get_operation()
+    }
+}
+
+impl Verify for LdmatrixOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let op = self.get_operation().deref(ctx);
+        let operands: Vec<_> = op.operands().collect();
+        if operands.len() != 1 {
+            return verify_err!(op.loc(), "nvvm.ldmatrix requires exactly one pointer operand");
+        }
+        let pointer = operands[0].get_type(ctx);
+        let pointer_object = pointer.deref(ctx);
+        let Some(pointer) = pointer_object.downcast_ref::<MirPtrType>() else {
+            return verify_err!(op.loc(), "nvvm.ldmatrix operand must be a MIR pointer");
+        };
+        if !matches!(pointer.address_space, address_space::GENERIC | address_space::SHARED) {
+            return verify_err!(
+                op.loc(),
+                "nvvm.ldmatrix pointer must be generic (p0) or shared (p3), not address space {}",
+                pointer.address_space
+            );
+        }
+        let pointee = pointer.pointee.deref(ctx);
+        let Some(pointee) = pointee.downcast_ref::<IntegerType>() else {
+            return verify_err!(op.loc(), "nvvm.ldmatrix pointer must point to an unsigned integer");
+        };
+
+        let Some(shape) = self.get_attr_nvvm_ldmatrix_shape(ctx) else {
+            return verify_err!(op.loc(), "nvvm.ldmatrix requires a shape attribute");
+        };
+        let Some(multiplicity) = self.get_attr_nvvm_ldmatrix_multiplicity(ctx) else {
+            return verify_err!(op.loc(), "nvvm.ldmatrix requires a multiplicity attribute");
+        };
+        let layout = self.get_attr_nvvm_ldmatrix_layout(ctx);
+        let element = self.get_attr_nvvm_ldmatrix_element(ctx);
+        let expected_pointee_width = if element.as_deref() == Some(&LdmatrixElementAttr::B16) {
+            32
+        } else {
+            8
+        };
+        if pointee.width() != expected_pointee_width
+            || pointee.signedness() != Signedness::Unsigned
+        {
+            return verify_err!(
+                op.loc(),
+                "nvvm.ldmatrix pointer element width does not match its matrix element format"
+            );
+        }
+        let supported = matches!(
+            (&*shape, layout.as_deref(), element.as_deref()),
+            (LdmatrixShapeAttr::M8n8, Some(_), Some(LdmatrixElementAttr::B16))
+            |
+            (
+                LdmatrixShapeAttr::M8n16,
+                Some(LdmatrixLayoutAttr::Normal),
+                Some(
+                    LdmatrixElementAttr::B8x16B4x16P64
+                        | LdmatrixElementAttr::B8x16B6x16P32,
+                ),
+            )
+            |
+            (
+                LdmatrixShapeAttr::M16n16,
+                Some(LdmatrixLayoutAttr::Transposed),
+                Some(
+                    LdmatrixElementAttr::B8
+                        | LdmatrixElementAttr::B8x16B4x16P64
+                        | LdmatrixElementAttr::B8x16B6x16P32,
+                ),
+            )
+        );
+        if !supported
+            || (*shape == LdmatrixShapeAttr::M16n16
+                && *multiplicity == LdmatrixMultiplicityAttr::X4)
+            || self.get_attr_nvvm_ldmatrix_state_space(ctx).as_deref()
+                != Some(&LdmatrixStateSpaceAttr::Shared)
+        {
+            return verify_err!(op.loc(), "nvvm.ldmatrix has a missing or unsupported variant attribute");
+        }
+
+        let register_count = shape.register_count(&multiplicity);
+        if op.get_num_results() != register_count {
+            return verify_err!(
+                op.loc(),
+                "nvvm.ldmatrix {:?} requires {} u32 results",
+                multiplicity,
+                register_count
+            );
+        }
+        for index in 0..register_count {
+            let ty = op.get_result(index).get_type(ctx);
+            let ty_object = ty.deref(ctx);
+            let Some(integer) = ty_object.downcast_ref::<IntegerType>() else {
+                return verify_err!(op.loc(), "nvvm.ldmatrix result {} must be u32", index);
+            };
+            if integer.width() != 32 || integer.signedness() != Signedness::Unsigned {
+                return verify_err!(op.loc(), "nvvm.ldmatrix result {} must be u32", index);
+            }
+        }
+        Ok(())
+    }
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    LdmatrixShapeAttr::register(ctx);
+    LdmatrixMultiplicityAttr::register(ctx);
+    LdmatrixLayoutAttr::register(ctx);
+    LdmatrixElementAttr::register(ctx);
+    LdmatrixStateSpaceAttr::register(ctx);
+    LdmatrixOp::register(ctx);
+}
+"##,
+    );
+
+    let compatibility = ldmatrix(catalog)
+        .filter_map(|record| ldmatrix_compat_op(record).map(|compat| (record, compat)))
+        .collect::<Vec<_>>();
+    assert_eq!(compatibility.len(), 6);
+
+    let mut definitions = String::from(
+        r#"
+fn verify_compat_ldmatrix(
+    ctx: &Context,
+    op: Ptr<Operation>,
+    op_name: &str,
+    result_count: usize,
+) -> Result<(), Error> {
+    let op = op.deref(ctx);
+    let operands: Vec<_> = op.operands().collect();
+    if operands.len() != 1 {
+        return verify_err!(op.loc(), "{} requires one shared-memory pointer", op_name);
+    }
+    if operands[0]
+        .get_type(ctx)
+        .deref(ctx)
+        .downcast_ref::<MirPtrType>()
+        .is_none()
+    {
+        return verify_err!(op.loc(), "{} operand 0 must be a MIR pointer", op_name);
+    }
+    if op.get_num_results() != result_count {
+        return verify_err!(
+            op.loc(),
+            "{} requires {} register results",
+            op_name,
+            result_count
+        );
+    }
+    for index in 0..result_count {
+        let ty = op.get_result(index).get_type(ctx);
+        let ty = ty.deref(ctx);
+        let Some(integer) = ty.downcast_ref::<IntegerType>() else {
+            return verify_err!(op.loc(), "{} result {} must be an integer", op_name, index);
+        };
+        if integer.width() != 32 {
+            return verify_err!(op.loc(), "{} result {} must be 32 bits", op_name, index);
+        }
+    }
+    Ok(())
+}
+
+"#,
+    );
+    for (record, (op_type, op_name)) in &compatibility {
+        let result_count = record
+            .ldmatrix
+            .as_ref()
+            .expect("ldmatrix compatibility record")
+            .variant
+            .multiplicity
+            .register_count();
+        writeln!(
+            definitions,
+            "/// Compatibility carrier for `{op_name}`.\n#[pliron_op(\n    name = {op_name:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<{result_count}>],\n)]\npub struct {op_type};\n\nimpl {op_type} {{\n    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n}}\n\nimpl Verify for {op_type} {{\n    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_compat_ldmatrix(ctx, self.get_operation(), {op_name:?}, {result_count})\n    }}\n}}\n"
+        )
+        .unwrap();
+    }
+    let register_start = output
+        .find("pub(super) fn register(ctx: &mut Context) {")
+        .expect("ldmatrix register function");
+    output.insert_str(register_start, &definitions);
+    let register_anchor = "    LdmatrixOp::register(ctx);\n";
+    let mut registrations = String::from(register_anchor);
+    for (_, (op_type, _)) in compatibility {
+        writeln!(registrations, "    {op_type}::register(ctx);").unwrap();
+    }
+    output = output.replacen(register_anchor, &registrations, 1);
+    output
+}
+
+pub(in crate::render) fn render_dialect_stmatrix(catalog: &CatalogFile, hash: &str) -> String {
+    assert_eq!(stmatrices(catalog).count(), 4);
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r#"//! Structural operations for the four generated `stmatrix` stores.
+
+use dialect_mir::types::MirPtrType;
+use pliron::{
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        types::IntegerType,
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    verify_err,
+};
+use pliron_derive::pliron_op;
+
+fn verify_stmatrix_operands(
+    ctx: &Context,
+    op: Ptr<Operation>,
+    op_name: &str,
+    register_count: usize,
+) -> Result<(), Error> {
+    let op = op.deref(ctx);
+    let operands: Vec<_> = op.operands().collect();
+    if operands.len() != register_count + 1 {
+        return verify_err!(
+            op.loc(),
+            "{} requires one pointer and {} register operands",
+            op_name,
+            register_count
+        );
+    }
+    if operands[0]
+        .get_type(ctx)
+        .deref(ctx)
+        .downcast_ref::<MirPtrType>()
+        .is_none()
+    {
+        return verify_err!(op.loc(), "{} operand 0 must be a MIR pointer", op_name);
+    }
+    for (index, register) in operands.iter().enumerate().skip(1) {
+        let ty = register.get_type(ctx);
+        let ty = ty.deref(ctx);
+        let Some(integer) = ty.downcast_ref::<IntegerType>() else {
+            return verify_err!(
+                op.loc(),
+                "{} register operand {} must be an integer",
+                op_name,
+                index - 1
+            );
+        };
+        if integer.width() != 32 {
+            return verify_err!(
+                op.loc(),
+                "{} register operand {} must be 32 bits",
+                op_name,
+                index - 1
+            );
+        }
+    }
+    Ok(())
+}
+
+"#,
+    );
+    for record in stmatrices(catalog) {
+        let (multiplicity, _) = stmatrix_variant(record).expect("stmatrix variant");
+        let count = multiplicity.register_count();
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{}>, NResultsInterface<0>],\n)]",
+            record.dialect.op_name,
+            count + 1
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str(
+            "    pub fn new(op: Ptr<Operation>) -> Self {\n        Self { op }\n    }\n}\n",
+        );
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_stmatrix_operands(ctx, self.get_operation(), {:?}, {count})\n    }}\n}}\n",
+            record.dialect.op_name
+        )
+        .unwrap();
+    }
+    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
+    for record in stmatrices(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_register_mma(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r#"//! One structural operation for generated register-only `mma.sync` variants.
+
+use pliron::{
+    attribute::Attribute,
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        types::{FP32Type, FP64Type, IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::{TypeHandle, Typed},
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[pliron_attr(name = "nvvm.register_mma_shape", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum RegisterMmaShapeAttr { M8n8k4, M8n8k16, M8n8k32, M8n8k128, M16n8k4, M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128, M16n8k256 }
+
+#[pliron_attr(name = "nvvm.register_mma_operation", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum RegisterMmaOperationAttr { Multiply, AndPopc, XorPopc }
+
+#[pliron_attr(name = "nvvm.register_mma_kind", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum RegisterMmaKindAttr { Standard, F8f6f4, Mxf8f6f4 }
+
+#[pliron_attr(name = "nvvm.register_mma_accumulator", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum RegisterMmaAccumulatorAttr { F16, F32, F64, S32 }
+
+#[pliron_attr(name = "nvvm.register_mma_element", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum RegisterMmaElementAttr { Bf16, E2m1, E2m3, E3m2, E4m3, E5m2, F16, Tf32, F64, B1, S4, U4, S8, U8 }
+
+#[pliron_attr(name = "nvvm.register_mma_layout", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum RegisterMmaLayoutAttr { Row, Col }
+
+#[pliron_attr(name = "nvvm.register_mma_overflow", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum RegisterMmaOverflowAttr { NotApplicable, Wrapping, Satfinite }
+
+#[pliron_op(
+    name = "nvvm.register_mma",
+    format,
+    attributes = (
+        nvvm_register_mma_shape: RegisterMmaShapeAttr,
+        nvvm_register_mma_operation: RegisterMmaOperationAttr,
+        nvvm_register_mma_kind: RegisterMmaKindAttr,
+        nvvm_register_mma_accumulator: RegisterMmaAccumulatorAttr,
+        nvvm_register_mma_a_element: RegisterMmaElementAttr,
+        nvvm_register_mma_b_element: RegisterMmaElementAttr,
+        nvvm_register_mma_a_layout: RegisterMmaLayoutAttr,
+        nvvm_register_mma_b_layout: RegisterMmaLayoutAttr,
+        nvvm_register_mma_overflow: RegisterMmaOverflowAttr
+    )
+)]
+pub struct RegisterMmaOp;
+
+impl RegisterMmaOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+
+    /// Defaults older multiply-only IR to multiply.
+    pub fn operation_or_multiply(&self, ctx: &Context) -> RegisterMmaOperationAttr {
+        self.get_attr_nvvm_register_mma_operation(ctx)
+            .as_deref()
+            .cloned()
+            .unwrap_or(RegisterMmaOperationAttr::Multiply)
+    }
+
+    /// Infers the kind used by older generated IR.
+    pub fn kind_or_inferred(&self, ctx: &Context) -> RegisterMmaKindAttr {
+        if let Some(kind) = self.get_attr_nvvm_register_mma_kind(ctx).as_deref() {
+            return kind.clone();
+        }
+        let low_format = |element: Option<&RegisterMmaElementAttr>| {
+            matches!(
+                element,
+                Some(
+                    RegisterMmaElementAttr::E2m1
+                        | RegisterMmaElementAttr::E2m3
+                        | RegisterMmaElementAttr::E3m2
+                        | RegisterMmaElementAttr::E4m3
+                        | RegisterMmaElementAttr::E5m2
+                )
+            )
+        };
+        let old_f8f6f4 = self.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+            == Some(&RegisterMmaShapeAttr::M16n8k32)
+            && low_format(self.get_attr_nvvm_register_mma_a_element(ctx).as_deref())
+            && low_format(self.get_attr_nvvm_register_mma_b_element(ctx).as_deref());
+        if old_f8f6f4 {
+            RegisterMmaKindAttr::F8f6f4
+        } else {
+            RegisterMmaKindAttr::Standard
+        }
+    }
+}
+
+#[derive(Clone, Copy)]
+enum MmaCarrier { F32, F64, I32, U16, U32 }
+
+fn is_carrier(ctx: &Context, ty: TypeHandle, carrier: MmaCarrier) -> bool {
+    match carrier {
+        MmaCarrier::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
+        MmaCarrier::F64 => ty.deref(ctx).downcast_ref::<FP64Type>().is_some(),
+        MmaCarrier::I32 | MmaCarrier::U16 | MmaCarrier::U32 => {
+            let expected = if matches!(carrier, MmaCarrier::I32) {
+                Signedness::Signed
+            } else {
+                Signedness::Unsigned
+            };
+            ty.deref(ctx)
+                .downcast_ref::<IntegerType>()
+                .is_some_and(|integer| {
+                    integer.width()
+                        == if matches!(carrier, MmaCarrier::U16) { 16 } else { 32 }
+                        && integer.signedness() == expected
+                })
+        }
+    }
+}
+
+impl Verify for RegisterMmaOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let op = self.get_operation().deref(ctx);
+        let operation = self.operation_or_multiply(ctx);
+        let kind = self.kind_or_inferred(ctx);
+        let recipe: (&[MmaCarrier], &[MmaCarrier]) = match (
+            self.get_attr_nvvm_register_mma_shape(ctx).as_deref(),
+            operation,
+            kind,
+            self.get_attr_nvvm_register_mma_accumulator(ctx).as_deref(),
+            self.get_attr_nvvm_register_mma_a_element(ctx).as_deref(),
+            self.get_attr_nvvm_register_mma_b_element(ctx).as_deref(),
+            self.get_attr_nvvm_register_mma_a_layout(ctx).as_deref(),
+            self.get_attr_nvvm_register_mma_b_layout(ctx).as_deref(),
+            self.get_attr_nvvm_register_mma_overflow(ctx).as_deref(),
+        ) {
+"#,
+    );
+    for record in register_mmas(catalog) {
+        let (
+            shape,
+            operation,
+            kind,
+            accumulator,
+            a_element,
+            b_element,
+            a_layout,
+            b_layout,
+            overflow,
+        ) = register_mma_attr_variants(record);
+        let (operands, results) = register_mma_carriers(record);
+        writeln!(
+            output,
+            "            (Some(&{shape}), {operation}, {kind}, Some(&{accumulator}), Some(&{a_element}), Some(&{b_element}), Some(&{a_layout}), Some(&{b_layout}), Some(&{overflow})) => ({operands}, {results}),"
+        )
+        .unwrap();
+    }
+    output.push_str(
+        r#"            _ => return verify_err!(op.loc(), "nvvm.register_mma has a missing or unsupported variant"),
+        };
+        let operands: Vec<_> = op.operands().collect();
+        if operands.len() != recipe.0.len() || op.get_num_results() != recipe.1.len() {
+            return verify_err!(op.loc(), "nvvm.register_mma has the wrong register count");
+        }
+        for (index, (operand, carrier)) in operands.iter().zip(recipe.0).enumerate() {
+            if !is_carrier(ctx, operand.get_type(ctx), *carrier) {
+                return verify_err!(op.loc(), "nvvm.register_mma operand {} has the wrong carrier type", index);
+            }
+        }
+        for (index, carrier) in recipe.1.iter().enumerate() {
+            if !is_carrier(ctx, op.get_result(index).get_type(ctx), *carrier) {
+                return verify_err!(op.loc(), "nvvm.register_mma result {} has the wrong carrier type", index);
+            }
+        }
+        Ok(())
+    }
+}
+
+"#,
+    );
+    output.push_str(
+        r#"
+fn is_compat_carrier(ctx: &Context, ty: TypeHandle, carrier: MmaCarrier) -> bool {
+    match carrier {
+        MmaCarrier::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
+        MmaCarrier::F64 => ty.deref(ctx).downcast_ref::<FP64Type>().is_some(),
+        MmaCarrier::I32 | MmaCarrier::U16 | MmaCarrier::U32 => {
+            let expected_width = if matches!(carrier, MmaCarrier::U16) {
+                16
+            } else {
+                32
+            };
+            ty.deref(ctx)
+                .downcast_ref::<IntegerType>()
+                .is_some_and(|integer| integer.width() == expected_width)
+        }
+    }
+}
+
+fn verify_compat_register_mma(
+    ctx: &Context,
+    op_ptr: Ptr<Operation>,
+    op_name: &str,
+    operand_carriers: &[MmaCarrier],
+    result_carriers: &[MmaCarrier],
+) -> Result<(), Error> {
+    let op = op_ptr.deref(ctx);
+    let operands: Vec<_> = op.operands().collect();
+    if operands.len() != operand_carriers.len() || op.get_num_results() != result_carriers.len() {
+        return verify_err!(op.loc(), "{} has the wrong register count", op_name);
+    }
+    for (index, (operand, carrier)) in operands.iter().zip(operand_carriers).enumerate() {
+        if !is_compat_carrier(ctx, operand.get_type(ctx), *carrier) {
+            return verify_err!(op.loc(), "{} operand {} has the wrong carrier type", op_name, index);
+        }
+    }
+    for (index, carrier) in result_carriers.iter().enumerate() {
+        if !is_compat_carrier(ctx, op.get_result(index).get_type(ctx), *carrier) {
+            return verify_err!(op.loc(), "{} result {} has the wrong carrier type", op_name, index);
+        }
+    }
+    Ok(())
+}
+
+"#,
+    );
+    for record in
+        register_mmas(catalog).filter(|record| register_mma_compat_op_type(record).is_some())
+    {
+        let op_type = register_mma_compat_op_type(record).unwrap();
+        let op_name = format!("nvvm.{}", record.id);
+        let operand_count = record.dialect.operands.len();
+        let result_count = record.dialect.results.len();
+        let (operands, results) = register_mma_carriers(record);
+        writeln!(output, "/// Compatibility carrier for `{}`.", record.id).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {op_name:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<{result_count}>],\n)]\npub struct {op_type};\n"
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "impl {op_type} {{\n    pub fn new(op: Ptr<Operation>) -> Self {{ Self {{ op }} }}\n}}\n"
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "impl Verify for {op_type} {{\n    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_compat_register_mma(ctx, self.get_operation(), {op_name:?}, {operands}, {results})\n    }}\n}}\n"
+        )
+        .unwrap();
+    }
+    output.push_str(
+        "pub(super) fn register(ctx: &mut Context) {\n    RegisterMmaShapeAttr::register(ctx);\n    RegisterMmaOperationAttr::register(ctx);\n    RegisterMmaKindAttr::register(ctx);\n    RegisterMmaAccumulatorAttr::register(ctx);\n    RegisterMmaElementAttr::register(ctx);\n    RegisterMmaLayoutAttr::register(ctx);\n    RegisterMmaOverflowAttr::register(ctx);\n    RegisterMmaOp::register(ctx);\n",
+    );
+    for record in
+        register_mmas(catalog).filter(|record| register_mma_compat_op_type(record).is_some())
+    {
+        writeln!(
+            output,
+            "    {}::register(ctx);",
+            register_mma_compat_op_type(record).unwrap()
+        )
+        .unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_sparse_mma(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r#"//! One structural operation for generated sparse MMA variants.
+
+use dialect_mir::ops::MirConstantOp;
+use pliron::{
+    attribute::Attribute,
+    builtin::{attributes::IntegerAttr, ops::ConstantOp, types::{FP32Type, IntegerType, Signedness}},
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::{TypeHandle, Typed},
+    value::Value,
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[pliron_attr(name = "nvvm.sparse_mma_shape", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum SparseMmaShapeAttr { M16n8k32, M16n8k64, M16n8k128 }
+
+#[pliron_attr(name = "nvvm.sparse_mma_accumulator", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum SparseMmaAccumulatorAttr { F16, F32, S32 }
+
+#[pliron_attr(name = "nvvm.sparse_mma_element", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum SparseMmaElementAttr { E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 }
+
+#[pliron_attr(name = "nvvm.sparse_mma_layout", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum SparseMmaLayoutAttr { Row, Col }
+
+#[pliron_attr(name = "nvvm.sparse_mma_overflow", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum SparseMmaOverflowAttr { NotApplicable, Wrapping, Satfinite }
+
+#[pliron_attr(name = "nvvm.sparse_mma_metadata", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum SparseMmaMetadataAttr { Standard, Ordered }
+
+#[pliron_attr(name = "nvvm.sparse_mma_selector", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum SparseMmaSelectorAttr { ImmediateZeroOrOne, ImmediateZero }
+
+#[pliron_op(
+    name = "nvvm.sparse_mma",
+    format,
+    attributes = (
+        nvvm_sparse_mma_shape: SparseMmaShapeAttr,
+        nvvm_sparse_mma_accumulator: SparseMmaAccumulatorAttr,
+        nvvm_sparse_mma_a_element: SparseMmaElementAttr,
+        nvvm_sparse_mma_b_element: SparseMmaElementAttr,
+        nvvm_sparse_mma_a_layout: SparseMmaLayoutAttr,
+        nvvm_sparse_mma_b_layout: SparseMmaLayoutAttr,
+        nvvm_sparse_mma_overflow: SparseMmaOverflowAttr,
+        nvvm_sparse_mma_metadata: SparseMmaMetadataAttr,
+        nvvm_sparse_mma_selector: SparseMmaSelectorAttr
+    )
+)]
+pub struct SparseMmaOp;
+
+impl SparseMmaOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+}
+
+#[derive(Clone, Copy)]
+enum MmaCarrier { F32, I32, U32 }
+
+fn is_carrier(ctx: &Context, ty: TypeHandle, carrier: MmaCarrier) -> bool {
+    match carrier {
+        MmaCarrier::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
+        MmaCarrier::I32 | MmaCarrier::U32 => {
+            let expected = if matches!(carrier, MmaCarrier::I32) {
+                Signedness::Signed
+            } else {
+                Signedness::Unsigned
+            };
+            ty.deref(ctx)
+                .downcast_ref::<IntegerType>()
+                .is_some_and(|integer| integer.width() == 32 && integer.signedness() == expected)
+        }
+    }
+}
+
+fn constant_u32(ctx: &Context, value: Value) -> Option<u64> {
+    let defining_op = value.defining_op()?;
+    if let Some(constant) = Operation::get_op::<MirConstantOp>(defining_op, ctx) {
+        return constant.get_attr_value(ctx).map(|value| value.value().to_u64());
+    }
+    let constant = Operation::get_op::<ConstantOp>(defining_op, ctx)?;
+    constant
+        .get_value(ctx)
+        .downcast_ref::<IntegerAttr>()
+        .map(|value| value.value().to_u64())
+}
+
+impl Verify for SparseMmaOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let op = self.get_operation().deref(ctx);
+        let (expected_operands, expected_results, selector_upper_exclusive): (&[MmaCarrier], &[MmaCarrier], usize) = match (
+            self.get_attr_nvvm_sparse_mma_shape(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_selector(ctx).as_deref(),
+        ) {
+"#,
+    );
+    for record in sparse_mmas(catalog) {
+        let (
+            shape,
+            accumulator,
+            a_element,
+            b_element,
+            a_layout,
+            b_layout,
+            overflow,
+            metadata,
+            selector,
+        ) = sparse_mma_attr_variants(record);
+        let (expected_operands, expected_results) = sparse_mma_carriers(record);
+        let selector_upper_exclusive = sparse_mma_selector_values(record).len();
+        writeln!(
+            output,
+            "            (Some(&{shape}), Some(&{accumulator}), Some(&{a_element}), Some(&{b_element}), Some(&{a_layout}), Some(&{b_layout}), Some(&{overflow}), Some(&{metadata}), Some(&{selector})) => ({expected_operands}, {expected_results}, {selector_upper_exclusive}),"
+        )
+        .unwrap();
+    }
+    output.push_str(
+        r#"            _ => return verify_err!(op.loc(), "nvvm.sparse_mma has a missing or unsupported variant"),
+        };
+        let operands: Vec<_> = op.operands().collect();
+        if operands.len() != expected_operands.len() || op.get_num_results() != expected_results.len() {
+            return verify_err!(op.loc(), "nvvm.sparse_mma has the wrong register count");
+        }
+        for (index, (operand, carrier)) in operands.iter().zip(expected_operands).enumerate() {
+            if !is_carrier(ctx, operand.get_type(ctx), *carrier) {
+                return verify_err!(op.loc(), "nvvm.sparse_mma operand {} has the wrong carrier type", index);
+            }
+        }
+        for (index, carrier) in expected_results.iter().enumerate() {
+            if !is_carrier(ctx, op.get_result(index).get_type(ctx), *carrier) {
+                return verify_err!(op.loc(), "nvvm.sparse_mma result {} has the wrong carrier type", index);
+            }
+        }
+        if constant_u32(ctx, operands[expected_operands.len() - 1])
+            .is_none_or(|selector| selector >= selector_upper_exclusive as u64)
+        {
+            return verify_err!(op.loc(), "nvvm.sparse_mma selector must be a compile-time constant in 0..{}", selector_upper_exclusive);
+        }
+        Ok(())
+    }
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    SparseMmaShapeAttr::register(ctx);
+    SparseMmaAccumulatorAttr::register(ctx);
+    SparseMmaElementAttr::register(ctx);
+    SparseMmaLayoutAttr::register(ctx);
+    SparseMmaOverflowAttr::register(ctx);
+    SparseMmaMetadataAttr::register(ctx);
+    SparseMmaSelectorAttr::register(ctx);
+    SparseMmaOp::register(ctx);
+}
+"#,
+    );
+    output
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/dialect/mod.rs b/crates/cuda-intrinsics-gen/src/render/dialect/mod.rs
new file mode 100644
index 0000000000..95f0b41e50
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/dialect/mod.rs
@@ -0,0 +1,212 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::CatalogFile;
+use crate::render::common::rust_header;
+use crate::render::families::{
+    clc_intrinsics, cluster_memory, debug_controls, elect_intrinsics, execution_controls,
+    extended_minmax, integer_minmaxes, mbarrier_extended, movmatrix, scalar_arithmetics,
+    scalar_conversions, scalar_maths, stmatrices, tcgen05_intrinsics, tma_intrinsics,
+    wgmma_controls,
+};
+
+mod cluster_tensor;
+mod mma;
+mod scalar_packed;
+mod warp_sync;
+
+pub(super) use cluster_tensor::*;
+pub(super) use mma::*;
+pub(super) use scalar_packed::*;
+pub(super) use warp_sync::*;
+
+pub(super) fn render_dialect_mod(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "mod active_mask;\nmod cluster_barrier;\nmod cp_async;\nmod dotprod;\nmod ldmatrix;\nmod mbarrier_basic;\nmod movmatrix;\nmod packed_alu;\nmod packed_atomic;\nmod packed_conversion;\nmod prmt;\nmod redux;\nmod register_mma;\nmod sparse_mma;\nmod sreg;\nmod sync;\nmod vote;\nmod warp_barrier;\nmod warp_match;\nmod warp_shuffle;\n\npub use active_mask::*;\npub use cluster_barrier::*;\npub use cp_async::*;\npub use dotprod::*;\npub use ldmatrix::*;\npub use mbarrier_basic::*;\npub use movmatrix::*;\npub use packed_alu::*;\npub use packed_atomic::*;\npub use packed_conversion::*;\npub use prmt::*;\npub use redux::*;\npub use register_mma::*;\npub use sparse_mma::*;\npub use sreg::*;\npub use sync::*;\npub use vote::*;\npub use warp_barrier::*;\npub use warp_match::*;\npub use warp_shuffle::*;\n\nuse pliron::context::Context;\n\npub(super) fn register(ctx: &mut Context) {\n    active_mask::register(ctx);\n    cluster_barrier::register(ctx);\n    cp_async::register(ctx);\n    dotprod::register(ctx);\n    ldmatrix::register(ctx);\n    mbarrier_basic::register(ctx);\n    movmatrix::register(ctx);\n    packed_alu::register(ctx);\n    packed_atomic::register(ctx);\n    packed_conversion::register(ctx);\n    prmt::register(ctx);\n    redux::register(ctx);\n    register_mma::register(ctx);\n    sparse_mma::register(ctx);\n    sreg::register(ctx);\n    sync::register(ctx);\n    vote::register(ctx);\n    warp_barrier::register(ctx);\n    warp_match::register(ctx);\n    warp_shuffle::register(ctx);\n}\n",
+    );
+    if scalar_conversions(catalog).next().is_some() {
+        output = output
+            .replace("mod redux;", "mod redux;\nmod scalar_conversion;")
+            .replace(
+                "pub use redux::*;",
+                "pub use redux::*;\npub use scalar_conversion::*;",
+            )
+            .replace(
+                "    redux::register(ctx);",
+                "    redux::register(ctx);\n    scalar_conversion::register(ctx);",
+            );
+    }
+    if scalar_arithmetics(catalog).next().is_some() {
+        output = output
+            .replace("mod redux;", "mod redux;\nmod scalar_arithmetic;")
+            .replace(
+                "pub use redux::*;",
+                "pub use redux::*;\npub use scalar_arithmetic::*;",
+            )
+            .replace(
+                "    redux::register(ctx);",
+                "    redux::register(ctx);\n    scalar_arithmetic::register(ctx);",
+            );
+    }
+    if scalar_maths(catalog).next().is_some() {
+        output = output
+            .replace("mod redux;", "mod redux;\nmod scalar_math;")
+            .replace(
+                "pub use redux::*;",
+                "pub use redux::*;\npub use scalar_math::*;",
+            )
+            .replace(
+                "    redux::register(ctx);",
+                "    redux::register(ctx);\n    scalar_math::register(ctx);",
+            );
+    }
+    if integer_minmaxes(catalog).next().is_some() {
+        output = output
+            .replace("mod ldmatrix;", "mod integer_minmax;\nmod ldmatrix;")
+            .replace(
+                "pub use ldmatrix::*;",
+                "pub use integer_minmax::*;\npub use ldmatrix::*;",
+            )
+            .replace(
+                "    ldmatrix::register(ctx);",
+                "    integer_minmax::register(ctx);\n    ldmatrix::register(ctx);",
+            );
+    }
+    if extended_minmax(catalog).next().is_some() {
+        output = output
+            .replace("mod dotprod;", "mod dotprod;\nmod extended_minmax;")
+            .replace(
+                "pub use dotprod::*;",
+                "pub use dotprod::*;\npub use extended_minmax::*;",
+            )
+            .replace(
+                "    dotprod::register(ctx);",
+                "    dotprod::register(ctx);\n    extended_minmax::register(ctx);",
+            );
+    }
+    if debug_controls(catalog).next().is_some() {
+        output = output
+            .replace("mod dotprod;", "mod debug_control;\nmod dotprod;")
+            .replace(
+                "pub use dotprod::*;",
+                "pub use debug_control::*;\npub use dotprod::*;",
+            )
+            .replace(
+                "    dotprod::register(ctx);",
+                "    debug_control::register(ctx);\n    dotprod::register(ctx);",
+            );
+    }
+    if cluster_memory(catalog).next().is_some() {
+        output = output
+            .replace(
+                "mod cluster_barrier;",
+                "mod cluster_barrier;\nmod cluster_memory;",
+            )
+            .replace(
+                "pub use cluster_barrier::*;",
+                "pub use cluster_barrier::*;\npub use cluster_memory::*;",
+            )
+            .replace(
+                "    cluster_barrier::register(ctx);",
+                "    cluster_barrier::register(ctx);\n    cluster_memory::register(ctx);",
+            );
+    }
+    if stmatrices(catalog).next().is_some() {
+        output = output
+            .replace("mod sync;", "mod stmatrix;\nmod sync;")
+            .replace("pub use sync::*;", "pub use stmatrix::*;\npub use sync::*;")
+            .replace(
+                "    sync::register(ctx);",
+                "    stmatrix::register(ctx);\n    sync::register(ctx);",
+            );
+    }
+    if movmatrix(catalog).next().is_none() {
+        output = output.replace("mod movmatrix;\n", "");
+        output = output.replace("pub use movmatrix::*;\n", "");
+        output = output.replace("    movmatrix::register(ctx);\n", "");
+    }
+    if clc_intrinsics(catalog).next().is_some() {
+        output = output
+            .replace("mod cluster_barrier;", "mod clc;\nmod cluster_barrier;")
+            .replace(
+                "pub use cluster_barrier::*;",
+                "pub use clc::*;\npub use cluster_barrier::*;",
+            )
+            .replace(
+                "    cluster_barrier::register(ctx);",
+                "    clc::register(ctx);\n    cluster_barrier::register(ctx);",
+            );
+    }
+    if elect_intrinsics(catalog).next().is_some() {
+        output = output
+            .replace("mod dotprod;", "mod dotprod;\nmod elect;")
+            .replace(
+                "pub use dotprod::*;",
+                "pub use dotprod::*;\npub use elect::*;",
+            )
+            .replace(
+                "    dotprod::register(ctx);",
+                "    dotprod::register(ctx);\n    elect::register(ctx);",
+            );
+    }
+    if mbarrier_extended(catalog).next().is_some() {
+        output = output.replace(
+            "mod mbarrier_basic;\n",
+            "mod mbarrier_basic;\nmod mbarrier_extended;\n",
+        );
+        output = output.replace(
+            "pub use mbarrier_basic::*;\n",
+            "pub use mbarrier_basic::*;\npub use mbarrier_extended::*;\n",
+        );
+        output = output.replace(
+            "    mbarrier_basic::register(ctx);\n",
+            "    mbarrier_basic::register(ctx);\n    mbarrier_extended::register(ctx);\n",
+        );
+    }
+    if wgmma_controls(catalog).next().is_some() {
+        output = output
+            .replace("mod warp_shuffle;", "mod warp_shuffle;\nmod wgmma_control;")
+            .replace(
+                "pub use warp_shuffle::*;",
+                "pub use warp_shuffle::*;\npub use wgmma_control::*;",
+            )
+            .replace(
+                "    warp_shuffle::register(ctx);",
+                "    warp_shuffle::register(ctx);\n    wgmma_control::register(ctx);",
+            );
+    }
+    if execution_controls(catalog).next().is_some() {
+        output = output
+            .replace("mod dotprod;", "mod dotprod;\nmod execution_control;")
+            .replace(
+                "pub use dotprod::*;",
+                "pub use dotprod::*;\npub use execution_control::*;",
+            )
+            .replace(
+                "    dotprod::register(ctx);",
+                "    dotprod::register(ctx);\n    execution_control::register(ctx);",
+            );
+    }
+    if tma_intrinsics(catalog).next().is_some() {
+        output = output
+            .replace("mod sync;", "mod sync;\nmod tma;")
+            .replace("pub use sync::*;", "pub use sync::*;\npub use tma::*;")
+            .replace(
+                "    sync::register(ctx);",
+                "    sync::register(ctx);\n    tma::register(ctx);",
+            );
+    }
+    if tcgen05_intrinsics(catalog).next().is_some() {
+        output = output
+            .replace("mod sync;", "mod sync;\nmod tcgen05;")
+            .replace("pub use sync::*;", "pub use sync::*;\npub use tcgen05::*;")
+            .replace(
+                "    sync::register(ctx);",
+                "    sync::register(ctx);\n    tcgen05::register(ctx);",
+            );
+    }
+    output
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/dialect/scalar_packed.rs b/crates/cuda-intrinsics-gen/src/render/dialect/scalar_packed.rs
new file mode 100644
index 0000000000..045f7c5c83
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/dialect/scalar_packed.rs
@@ -0,0 +1,1190 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{CatalogFile, PackedConversionSourceFormat};
+use crate::render::common::rust_header;
+use crate::render::families::{
+    extended_minmax, extended_minmax_format_attr, extended_minmax_nan_attr,
+    extended_minmax_operation_attr, extended_minmax_subnormal_attr,
+    extended_minmax_xorsign_abs_attr, integer_minmax_ptx_mnemonic, integer_minmaxes,
+    packed_alu_ptx_mnemonic, packed_alu_width, packed_alus, packed_conversion_element,
+    packed_conversion_result_width, packed_conversion_source, packed_conversion_source_width,
+    packed_conversions, scalar_arithmetic_format_attr, scalar_arithmetic_operation_attr,
+    scalar_arithmetic_rounding_attr, scalar_arithmetic_saturation_attr,
+    scalar_arithmetic_subnormal_attr, scalar_arithmetics, scalar_conversion_rounding_attr,
+    scalar_conversion_saturation_attr, scalar_conversions, scalar_math_format_attr,
+    scalar_math_operation_attr, scalar_math_precision_attr, scalar_math_subnormal_attr,
+    scalar_maths,
+};
+use std::fmt::Write as _;
+
+pub(in crate::render) fn render_dialect_integer_minmax(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operations for generated extended integer min/max.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\n",
+    );
+    for record in integer_minmaxes(catalog) {
+        let signedness = if record.rust.result == "i32" {
+            "Signed"
+        } else {
+            "Unsigned"
+        };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "///\n/// Lowers to `{}`.",
+            integer_minmax_ptx_mnemonic(record)
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, arg0: Value, arg1: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, 32, Signedness::{signedness});\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![arg0, arg1],\n            vec![],\n            0,\n        )\n    }}\n}}"
+        )
+        .unwrap();
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 2 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !(0..2).all(|index| is_i32(ctx, op.get_operand(index).get_type(ctx)))\n            || !is_i32(ctx, op.get_result(0).get_type(ctx))\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+            format!(
+                "{} requires exactly 2 operands and one result",
+                record.dialect.op_name
+            ),
+            format!(
+                "{} operands and result must be 32-bit integers",
+                record.dialect.op_name
+            ),
+        )
+        .unwrap();
+    }
+    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
+    for record in integer_minmaxes(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_packed_atomic(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r##"//! One structural operation for the closed generated packed-atomic family.
+
+use dialect_mir::types::{address_space, MirPtrType};
+use pliron::{
+    attribute::Attribute,
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        types::{IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[pliron_attr(name = "nvvm.packed_atomic_format", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum PackedAtomicFormatAttr { F16x2, Bf16x2 }
+
+#[pliron_attr(name = "nvvm.packed_atomic_state_space", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum PackedAtomicStateSpaceAttr { Global }
+
+#[pliron_attr(name = "nvvm.packed_atomic_ordering", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum PackedAtomicOrderingAttr { Relaxed }
+
+#[pliron_attr(name = "nvvm.packed_atomic_scope", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum PackedAtomicScopeAttr { Gpu }
+
+#[pliron_attr(name = "nvvm.packed_atomic_rounding", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum PackedAtomicRoundingAttr { Rn }
+
+#[pliron_attr(name = "nvvm.packed_atomic_subnormal", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum PackedAtomicSubnormalAttr { NoFtz }
+
+#[pliron_attr(name = "nvvm.packed_atomic_atomicity", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum PackedAtomicAtomicityAttr { PerElement }
+
+/// Packed global atomic add with exact format and semantic attributes.
+#[pliron_op(
+    name = "nvvm.packed_atomic_add",
+    format,
+    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
+    attributes = (
+        nvvm_packed_atomic_format: PackedAtomicFormatAttr,
+        nvvm_packed_atomic_state_space: PackedAtomicStateSpaceAttr,
+        nvvm_packed_atomic_ordering: PackedAtomicOrderingAttr,
+        nvvm_packed_atomic_scope: PackedAtomicScopeAttr,
+        nvvm_packed_atomic_rounding: PackedAtomicRoundingAttr,
+        nvvm_packed_atomic_subnormal: PackedAtomicSubnormalAttr,
+        nvvm_packed_atomic_atomicity: PackedAtomicAtomicityAttr
+    )
+)]
+pub struct PackedAtomicAddOp;
+
+impl PackedAtomicAddOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+
+    pub fn build(
+        ctx: &mut Context,
+        address: Value,
+        addend: Value,
+        format: PackedAtomicFormatAttr,
+    ) -> Ptr<Operation> {
+        let u32_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
+        let op = Operation::new(
+            ctx,
+            Self::get_concrete_op_info(),
+            vec![u32_ty.into()],
+            vec![address, addend],
+            vec![],
+            0,
+        );
+        let this = Self { op };
+        this.set_attr_nvvm_packed_atomic_format(ctx, format);
+        this.set_attr_nvvm_packed_atomic_state_space(ctx, PackedAtomicStateSpaceAttr::Global);
+        this.set_attr_nvvm_packed_atomic_ordering(ctx, PackedAtomicOrderingAttr::Relaxed);
+        this.set_attr_nvvm_packed_atomic_scope(ctx, PackedAtomicScopeAttr::Gpu);
+        this.set_attr_nvvm_packed_atomic_rounding(ctx, PackedAtomicRoundingAttr::Rn);
+        this.set_attr_nvvm_packed_atomic_subnormal(ctx, PackedAtomicSubnormalAttr::NoFtz);
+        this.set_attr_nvvm_packed_atomic_atomicity(ctx, PackedAtomicAtomicityAttr::PerElement);
+        this.get_operation()
+    }
+}
+
+fn is_u32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {
+    ty.deref(ctx).downcast_ref::<IntegerType>().is_some_and(|integer| {
+        integer.width() == 32 && integer.signedness() == Signedness::Unsigned
+    })
+}
+
+fn verify_packed_atomic_signature(
+    ctx: &Context,
+    op_ptr: Ptr<Operation>,
+    op_name: &str,
+) -> Result<(), Error> {
+    let op = op_ptr.deref(ctx);
+    if op.get_num_operands() != 2 || op.get_num_results() != 1 {
+        return verify_err!(op.loc(), "{} requires exactly two operands and one result", op_name);
+    }
+    let pointer_ty = op.get_operand(0).get_type(ctx);
+    let pointer_object = pointer_ty.deref(ctx);
+    let Some(pointer) = pointer_object.downcast_ref::<MirPtrType>() else {
+        return verify_err!(op.loc(), "{} address must be a MIR pointer", op_name);
+    };
+    if !pointer.is_mutable()
+        || !matches!(pointer.address_space(), address_space::GENERIC | address_space::GLOBAL)
+        || !is_u32(ctx, pointer.pointee)
+    {
+        return verify_err!(op.loc(), "{} address must be a mutable generic/global pointer to u32", op_name);
+    }
+    if !is_u32(ctx, op.get_operand(1).get_type(ctx)) || !is_u32(ctx, op.get_result(0).get_type(ctx)) {
+        return verify_err!(op.loc(), "{} addend and result must be u32", op_name);
+    }
+    Ok(())
+}
+
+impl Verify for PackedAtomicAddOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        verify_packed_atomic_signature(ctx, self.get_operation(), "nvvm.packed_atomic_add")?;
+        let op = self.get_operation().deref(ctx);
+        if self.get_attr_nvvm_packed_atomic_format(ctx).is_none()
+            || self.get_attr_nvvm_packed_atomic_state_space(ctx).as_deref() != Some(&PackedAtomicStateSpaceAttr::Global)
+            || self.get_attr_nvvm_packed_atomic_ordering(ctx).as_deref() != Some(&PackedAtomicOrderingAttr::Relaxed)
+            || self.get_attr_nvvm_packed_atomic_scope(ctx).as_deref() != Some(&PackedAtomicScopeAttr::Gpu)
+            || self.get_attr_nvvm_packed_atomic_rounding(ctx).as_deref() != Some(&PackedAtomicRoundingAttr::Rn)
+            || self.get_attr_nvvm_packed_atomic_subnormal(ctx).as_deref() != Some(&PackedAtomicSubnormalAttr::NoFtz)
+            || self.get_attr_nvvm_packed_atomic_atomicity(ctx).as_deref() != Some(&PackedAtomicAtomicityAttr::PerElement)
+        {
+            return verify_err!(op.loc(), "nvvm.packed_atomic_add has a missing or unsupported semantic attribute");
+        }
+        Ok(())
+    }
+}
+
+/// Compatibility operation for the existing `nvvm.atom_add_f16x2` carrier.
+#[pliron_op(
+    name = "nvvm.atom_add_f16x2",
+    format,
+    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
+)]
+pub struct NvvmAtomAddF16x2Op;
+
+impl NvvmAtomAddF16x2Op {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+}
+
+impl Verify for NvvmAtomAddF16x2Op {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        verify_packed_atomic_signature(ctx, self.get_operation(), "nvvm.atom_add_f16x2")
+    }
+}
+
+/// Compatibility operation for the existing `nvvm.atom_add_bf16x2` carrier.
+#[pliron_op(
+    name = "nvvm.atom_add_bf16x2",
+    format,
+    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
+)]
+pub struct NvvmAtomAddBf16x2Op;
+
+impl NvvmAtomAddBf16x2Op {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+}
+
+impl Verify for NvvmAtomAddBf16x2Op {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        verify_packed_atomic_signature(ctx, self.get_operation(), "nvvm.atom_add_bf16x2")
+    }
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    PackedAtomicFormatAttr::register(ctx);
+    PackedAtomicStateSpaceAttr::register(ctx);
+    PackedAtomicOrderingAttr::register(ctx);
+    PackedAtomicScopeAttr::register(ctx);
+    PackedAtomicRoundingAttr::register(ctx);
+    PackedAtomicSubnormalAttr::register(ctx);
+    PackedAtomicAtomicityAttr::register(ctx);
+    PackedAtomicAddOp::register(ctx);
+    NvvmAtomAddF16x2Op::register(ctx);
+    NvvmAtomAddBf16x2Op::register(ctx);
+}
+"##,
+    );
+    output
+}
+
+pub(in crate::render) fn render_dialect_packed_alu(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operations for generated packed floating-point arithmetic.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_integer_width(\n    ctx: &Context,\n    ty: pliron::r#type::TypeHandle,\n    width: u32,\n) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\n",
+    );
+    for record in packed_alus(catalog) {
+        let arity = record.rust.arguments.len();
+        let width = packed_alu_width(record);
+        let parameters = (0..arity)
+            .map(|index| format!("arg{index}: Value"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let operands = (0..arity)
+            .map(|index| format!("arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "///\n/// Lowers to `{}`.",
+            packed_alu_ptx_mnemonic(record)
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{arity}>, NResultsInterface<1>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, {parameters}) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, {width}, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![{operands}],\n            vec![],\n            0,\n        )\n    }}\n}}"
+        )
+        .unwrap();
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != {arity} || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !(0..{arity}).all(|index| is_integer_width(ctx, op.get_operand(index).get_type(ctx), {width}))\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), {width})\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+            format!(
+                "{} requires exactly {arity} operands and one result",
+                record.dialect.op_name
+            ),
+            format!(
+                "{} operands and result must be {width}-bit integers",
+                record.dialect.op_name,
+            ),
+        )
+        .unwrap();
+    }
+    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
+    for record in packed_alus(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_packed_conversion(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operation for generated packed conversion.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{FP32Type, IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_f32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx).downcast_ref::<FP32Type>().is_some()\n}\n\nfn is_integer_width(\n    ctx: &Context,\n    ty: pliron::r#type::TypeHandle,\n    width: u32,\n) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\n",
+    );
+    for record in packed_conversions(catalog) {
+        let result_width = packed_conversion_result_width(record);
+        writeln!(output, "/// {}", record.summary).unwrap();
+        match packed_conversion_source(record) {
+            PackedConversionSourceFormat::F32x2 => {
+                writeln!(
+                    output,
+                    "///\n/// The first input becomes the low {} lane; the second becomes the high lane.",
+                    packed_conversion_element(record)
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],\n)]",
+                    record.dialect.op_name
+                )
+                .unwrap();
+                writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+                writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+                writeln!(
+                    output,
+                    "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, low: Value, high: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, {result_width}, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![low, high],\n            vec![],\n            0,\n        )\n    }}\n}}",
+                )
+                .unwrap();
+                writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+                writeln!(
+                    output,
+                    "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 2 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_f32(ctx, op.get_operand(0).get_type(ctx))\n            || !is_f32(ctx, op.get_operand(1).get_type(ctx))\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), {})\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+                    format!("{} requires two operands and one result", record.dialect.op_name),
+                    result_width,
+                    format!(
+                        "{} requires f32 operands and one {result_width}-bit integer result",
+                        record.dialect.op_name,
+                    ),
+                )
+                .unwrap();
+            }
+            PackedConversionSourceFormat::E4m3x2
+            | PackedConversionSourceFormat::E5m2x2
+            | PackedConversionSourceFormat::F16x2 => {
+                let source_width = packed_conversion_source_width(record);
+                writeln!(
+                    output,
+                    "///\n/// The single input carries both packed lanes, and lane order is preserved."
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<1>],\n)]",
+                    record.dialect.op_name
+                )
+                .unwrap();
+                writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+                writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+                writeln!(
+                    output,
+                    "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, packed: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, {result_width}, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![packed],\n            vec![],\n            0,\n        )\n    }}\n}}",
+                )
+                .unwrap();
+                writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+                writeln!(
+                    output,
+                    "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 1 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_integer_width(ctx, op.get_operand(0).get_type(ctx), {source_width})\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), {result_width})\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+                    format!("{} requires one operand and one result", record.dialect.op_name),
+                    format!(
+                        "{} requires one {source_width}-bit integer operand and one {result_width}-bit integer result",
+                        record.dialect.op_name,
+                    ),
+                )
+                .unwrap();
+            }
+        }
+    }
+    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
+    for record in packed_conversions(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_scalar_conversion(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r##"//! One structural operation for generated `f32` to TF32 conversions.
+
+use pliron::{
+    attribute::Attribute,
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        types::{FP32Type, IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[pliron_attr(name = "nvvm.scalar_conversion_rounding", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarConversionRoundingAttr {
+    NearestAway,
+    NearestEven,
+    TowardZero,
+}
+
+#[pliron_attr(name = "nvvm.scalar_conversion_saturation", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarConversionSaturationAttr {
+    None,
+    Relu,
+    Satfinite,
+    ReluSatfinite,
+}
+
+/// Converts one `f32` value and returns the raw TF32 bits.
+#[pliron_op(
+    name = "nvvm.scalar_conversion",
+    format,
+    interfaces = [NOpdsInterface<1>, NResultsInterface<1>],
+    attributes = (
+        nvvm_scalar_conversion_rounding: ScalarConversionRoundingAttr,
+        nvvm_scalar_conversion_saturation: ScalarConversionSaturationAttr
+    )
+)]
+pub struct ScalarConversionOp;
+
+impl ScalarConversionOp {
+    pub fn new(op: Ptr<Operation>) -> Self {
+        Self { op }
+    }
+
+    pub fn build(
+        ctx: &mut Context,
+        value: Value,
+        rounding: ScalarConversionRoundingAttr,
+        saturation: ScalarConversionSaturationAttr,
+    ) -> Ptr<Operation> {
+        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
+        let op = Operation::new(
+            ctx,
+            Self::get_concrete_op_info(),
+            vec![result_ty.into()],
+            vec![value],
+            vec![],
+            0,
+        );
+        let this = Self { op };
+        this.set_attr_nvvm_scalar_conversion_rounding(ctx, rounding);
+        this.set_attr_nvvm_scalar_conversion_saturation(ctx, saturation);
+        this.get_operation()
+    }
+}
+
+impl Verify for ScalarConversionOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let op = self.get_operation().deref(ctx);
+        let Some(rounding) = self.get_attr_nvvm_scalar_conversion_rounding(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_conversion requires rounding");
+        };
+        let Some(saturation) = self.get_attr_nvvm_scalar_conversion_saturation(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_conversion requires saturation");
+        };
+        let admitted = matches!(
+            (&*rounding, &*saturation),
+"##,
+    );
+    for (index, record) in scalar_conversions(catalog).enumerate() {
+        if index != 0 {
+            output.push_str(" |\n");
+        }
+        writeln!(
+            output,
+            "            ({}, {})",
+            scalar_conversion_rounding_attr(record),
+            scalar_conversion_saturation_attr(record),
+        )
+        .unwrap();
+    }
+    output.push_str(
+        r##"        );
+        if !admitted {
+            return verify_err!(op.loc(), "nvvm.scalar_conversion variant is not admitted");
+        }
+        if op
+            .get_operand(0)
+            .get_type(ctx)
+            .deref(ctx)
+            .downcast_ref::<FP32Type>()
+            .is_none()
+        {
+            return verify_err!(op.loc(), "nvvm.scalar_conversion operand must be f32");
+        }
+        if op
+            .get_result(0)
+            .get_type(ctx)
+            .deref(ctx)
+            .downcast_ref::<IntegerType>()
+            .is_none_or(|integer| integer.width() != 32)
+        {
+            return verify_err!(op.loc(), "nvvm.scalar_conversion result must be a 32-bit integer");
+        }
+        Ok(())
+    }
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    ScalarConversionRoundingAttr::register(ctx);
+    ScalarConversionSaturationAttr::register(ctx);
+    ScalarConversionOp::register(ctx);
+}
+"##,
+    );
+    output
+}
+
+pub(in crate::render) fn render_dialect_scalar_arithmetic(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r##"//! One structural operation for generated scalar arithmetic.
+
+use pliron::{
+    attribute::Attribute,
+    builtin::{op_interfaces::NResultsInterface, types::{FP32Type, FP64Type}},
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[pliron_attr(name = "nvvm.scalar_arithmetic_format", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarArithmeticFormatAttr { F32, F64 }
+
+#[pliron_attr(name = "nvvm.scalar_arithmetic_operation", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarArithmeticOperationAttr { Mul, Div, Fma, Add }
+
+#[pliron_attr(name = "nvvm.scalar_arithmetic_rounding", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarArithmeticRoundingAttr { Rn, Rz, Rm, Rp }
+
+#[pliron_attr(name = "nvvm.scalar_arithmetic_subnormal", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarArithmeticSubnormalAttr { Preserve, Ftz }
+
+#[pliron_attr(name = "nvvm.scalar_arithmetic_saturation", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarArithmeticSaturationAttr { None, Sat }
+
+/// Scalar arithmetic with explicit PTX modifiers.
+#[pliron_op(
+    name = "nvvm.scalar_arithmetic",
+    format,
+    interfaces = [NResultsInterface<1>],
+    attributes = (
+        nvvm_scalar_arithmetic_format: ScalarArithmeticFormatAttr,
+        nvvm_scalar_arithmetic_operation: ScalarArithmeticOperationAttr,
+        nvvm_scalar_arithmetic_rounding: ScalarArithmeticRoundingAttr,
+        nvvm_scalar_arithmetic_subnormal: ScalarArithmeticSubnormalAttr,
+        nvvm_scalar_arithmetic_saturation: ScalarArithmeticSaturationAttr
+    )
+)]
+pub struct ScalarArithmeticOp;
+
+impl ScalarArithmeticOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+
+    pub fn build(
+        ctx: &mut Context,
+        operands: Vec<Value>,
+        format: ScalarArithmeticFormatAttr,
+        operation: ScalarArithmeticOperationAttr,
+        rounding: ScalarArithmeticRoundingAttr,
+        subnormal: ScalarArithmeticSubnormalAttr,
+        saturation: ScalarArithmeticSaturationAttr,
+    ) -> Ptr<Operation> {
+        let result_ty = match &format {
+            ScalarArithmeticFormatAttr::F32 => FP32Type::get(ctx).into(),
+            ScalarArithmeticFormatAttr::F64 => FP64Type::get(ctx).into(),
+        };
+        let op = Operation::new(
+            ctx,
+            Self::get_concrete_op_info(),
+            vec![result_ty],
+            operands,
+            vec![],
+            0,
+        );
+        let this = Self { op };
+        this.set_attr_nvvm_scalar_arithmetic_format(ctx, format);
+        this.set_attr_nvvm_scalar_arithmetic_operation(ctx, operation);
+        this.set_attr_nvvm_scalar_arithmetic_rounding(ctx, rounding);
+        this.set_attr_nvvm_scalar_arithmetic_subnormal(ctx, subnormal);
+        this.set_attr_nvvm_scalar_arithmetic_saturation(ctx, saturation);
+        this.get_operation()
+    }
+}
+
+impl Verify for ScalarArithmeticOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let op = self.get_operation().deref(ctx);
+        let Some(format) = self.get_attr_nvvm_scalar_arithmetic_format(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_arithmetic requires a format");
+        };
+        let Some(operation) = self.get_attr_nvvm_scalar_arithmetic_operation(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_arithmetic requires an operation");
+        };
+        let Some(rounding) = self.get_attr_nvvm_scalar_arithmetic_rounding(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_arithmetic requires rounding");
+        };
+        let Some(subnormal) = self.get_attr_nvvm_scalar_arithmetic_subnormal(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_arithmetic requires a subnormal mode");
+        };
+        let Some(saturation) = self.get_attr_nvvm_scalar_arithmetic_saturation(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_arithmetic requires saturation");
+        };
+        let admitted = matches!(
+            (&*format, &*operation, &*rounding, &*subnormal, &*saturation),
+"##,
+    );
+    for (index, record) in scalar_arithmetics(catalog).enumerate() {
+        if index != 0 {
+            output.push_str(" |\n");
+        }
+        writeln!(
+            output,
+            "            ({}, {}, {}, {}, {})",
+            scalar_arithmetic_format_attr(record),
+            scalar_arithmetic_operation_attr(record),
+            scalar_arithmetic_rounding_attr(record),
+            scalar_arithmetic_subnormal_attr(record),
+            scalar_arithmetic_saturation_attr(record),
+        )
+        .unwrap();
+    }
+    output.push_str(
+        r##"        );
+        if !admitted {
+            return verify_err!(op.loc(), "nvvm.scalar_arithmetic variant is not admitted");
+        }
+        let expected_operands = match &*operation {
+            ScalarArithmeticOperationAttr::Mul
+            | ScalarArithmeticOperationAttr::Div
+            | ScalarArithmeticOperationAttr::Add => 2,
+            ScalarArithmeticOperationAttr::Fma => 3,
+        };
+        if op.get_num_operands() != expected_operands || op.get_num_results() != 1 {
+            return verify_err!(
+                op.loc(),
+                "nvvm.scalar_arithmetic requires {} operands and one result",
+                expected_operands,
+            );
+        }
+        let type_matches = |ty: pliron::r#type::TypeHandle| match &*format {
+            ScalarArithmeticFormatAttr::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
+            ScalarArithmeticFormatAttr::F64 => ty.deref(ctx).downcast_ref::<FP64Type>().is_some(),
+        };
+        if !(0..expected_operands).all(|index| type_matches(op.get_operand(index).get_type(ctx)))
+            || !type_matches(op.get_result(0).get_type(ctx))
+        {
+            return verify_err!(op.loc(), "nvvm.scalar_arithmetic types do not match its format");
+        }
+        Ok(())
+    }
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    ScalarArithmeticFormatAttr::register(ctx);
+    ScalarArithmeticOperationAttr::register(ctx);
+    ScalarArithmeticRoundingAttr::register(ctx);
+    ScalarArithmeticSubnormalAttr::register(ctx);
+    ScalarArithmeticSaturationAttr::register(ctx);
+    ScalarArithmeticOp::register(ctx);
+}
+"##,
+    );
+    output
+}
+
+pub(in crate::render) fn render_dialect_scalar_math(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r##"//! One structural operation for generated scalar math.
+
+use pliron::{
+    attribute::Attribute,
+    builtin::{op_interfaces::{NOpdsInterface, NResultsInterface}, types::{FP32Type, FP64Type, IntegerType, Signedness}},
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[pliron_attr(name = "nvvm.scalar_math_format", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarMathFormatAttr { F16, F32, F64 }
+
+#[pliron_attr(name = "nvvm.scalar_math_operation", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarMathOperationAttr { Sin, Cos, Ex2, Lg2, Rcp, Rsqrt, Sqrt, Tanh }
+
+#[pliron_attr(name = "nvvm.scalar_math_precision", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarMathPrecisionAttr { Approx, Rn, Rz, Rm, Rp }
+
+#[pliron_attr(name = "nvvm.scalar_math_subnormal", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ScalarMathSubnormalAttr { Preserve, Ftz }
+
+/// Scalar math with exact PTX modifiers.
+#[pliron_op(
+    name = "nvvm.scalar_math",
+    format,
+    interfaces = [NOpdsInterface<1>, NResultsInterface<1>],
+    attributes = (
+        nvvm_scalar_math_format: ScalarMathFormatAttr,
+        nvvm_scalar_math_operation: ScalarMathOperationAttr,
+        nvvm_scalar_math_precision: ScalarMathPrecisionAttr,
+        nvvm_scalar_math_subnormal: ScalarMathSubnormalAttr
+    )
+)]
+pub struct ScalarMathOp;
+
+impl ScalarMathOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+
+    pub fn build(
+        ctx: &mut Context,
+        operand: Value,
+        format: ScalarMathFormatAttr,
+        operation: ScalarMathOperationAttr,
+        precision: ScalarMathPrecisionAttr,
+        subnormal: ScalarMathSubnormalAttr,
+    ) -> Ptr<Operation> {
+        let result_ty = match &format {
+            ScalarMathFormatAttr::F16 => IntegerType::get(ctx, 16, Signedness::Unsigned).into(),
+            ScalarMathFormatAttr::F32 => FP32Type::get(ctx).into(),
+            ScalarMathFormatAttr::F64 => FP64Type::get(ctx).into(),
+        };
+        let op = Operation::new(
+            ctx,
+            Self::get_concrete_op_info(),
+            vec![result_ty],
+            vec![operand],
+            vec![],
+            0,
+        );
+        let this = Self { op };
+        this.set_attr_nvvm_scalar_math_format(ctx, format);
+        this.set_attr_nvvm_scalar_math_operation(ctx, operation);
+        this.set_attr_nvvm_scalar_math_precision(ctx, precision);
+        this.set_attr_nvvm_scalar_math_subnormal(ctx, subnormal);
+        this.get_operation()
+    }
+}
+
+impl Verify for ScalarMathOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let op = self.get_operation().deref(ctx);
+        let Some(format) = self.get_attr_nvvm_scalar_math_format(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_math requires a format");
+        };
+        let Some(operation) = self.get_attr_nvvm_scalar_math_operation(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_math requires an operation");
+        };
+        let Some(precision) = self.get_attr_nvvm_scalar_math_precision(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_math requires a precision");
+        };
+        let Some(subnormal) = self.get_attr_nvvm_scalar_math_subnormal(ctx) else {
+            return verify_err!(op.loc(), "nvvm.scalar_math requires a subnormal mode");
+        };
+        let admitted = matches!(
+            (&*format, &*operation, &*precision, &*subnormal),
+"##,
+    );
+    for (index, record) in scalar_maths(catalog).enumerate() {
+        if index != 0 {
+            output.push_str(" |\n");
+        }
+        writeln!(
+            output,
+            "            ({}, {}, {}, {})",
+            scalar_math_format_attr(record),
+            scalar_math_operation_attr(record),
+            scalar_math_precision_attr(record),
+            scalar_math_subnormal_attr(record),
+        )
+        .unwrap();
+    }
+    output.push_str(
+        r##"        );
+        if !admitted {
+            return verify_err!(op.loc(), "nvvm.scalar_math variant is not admitted");
+        }
+        if op.get_num_operands() != 1 || op.get_num_results() != 1 {
+            return verify_err!(
+                op.loc(),
+                "nvvm.scalar_math requires one operand and one result",
+            );
+        }
+        let type_matches = |ty: pliron::r#type::TypeHandle| match &*format {
+            ScalarMathFormatAttr::F16 => ty.deref(ctx).downcast_ref::<IntegerType>().is_some_and(|integer| integer.width() == 16),
+            ScalarMathFormatAttr::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
+            ScalarMathFormatAttr::F64 => ty.deref(ctx).downcast_ref::<FP64Type>().is_some(),
+        };
+        if !type_matches(op.get_operand(0).get_type(ctx))
+            || !type_matches(op.get_result(0).get_type(ctx))
+        {
+            return verify_err!(op.loc(), "nvvm.scalar_math types do not match its format");
+        }
+        Ok(())
+    }
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    ScalarMathFormatAttr::register(ctx);
+    ScalarMathOperationAttr::register(ctx);
+    ScalarMathPrecisionAttr::register(ctx);
+    ScalarMathSubnormalAttr::register(ctx);
+    ScalarMathOp::register(ctx);
+}
+"##,
+    );
+    output
+}
+
+pub(in crate::render) fn render_dialect_extended_minmax(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r##"//! One structural operation for extended floating-point min/max.
+
+use pliron::{
+    attribute::Attribute,
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        types::{FP32Type, IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[pliron_attr(name = "nvvm.extended_minmax_format", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ExtendedMinMaxFormatAttr { F32, F16, Bf16, F16x2, Bf16x2 }
+
+#[pliron_attr(name = "nvvm.extended_minmax_operation", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ExtendedMinMaxOperationAttr { Min, Max }
+
+#[pliron_attr(name = "nvvm.extended_minmax_subnormal", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ExtendedMinMaxSubnormalAttr { Preserve, Ftz }
+
+#[pliron_attr(name = "nvvm.extended_minmax_nan", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ExtendedMinMaxNanAttr { Number, Nan }
+
+#[pliron_attr(name = "nvvm.extended_minmax_xorsign_abs", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum ExtendedMinMaxXorSignAbsAttr { Disabled, Enabled }
+
+/// Extended min/max with exact PTX modifiers.
+#[pliron_op(
+    name = "nvvm.extended_minmax",
+    format,
+    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],
+    attributes = (
+        nvvm_extended_minmax_format: ExtendedMinMaxFormatAttr,
+        nvvm_extended_minmax_operation: ExtendedMinMaxOperationAttr,
+        nvvm_extended_minmax_subnormal: ExtendedMinMaxSubnormalAttr,
+        nvvm_extended_minmax_nan: ExtendedMinMaxNanAttr,
+        nvvm_extended_minmax_xorsign_abs: ExtendedMinMaxXorSignAbsAttr
+    )
+)]
+pub struct ExtendedMinMaxOp;
+
+impl ExtendedMinMaxOp {
+    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }
+
+    #[allow(clippy::too_many_arguments)]
+    pub fn build(
+        ctx: &mut Context,
+        a: Value,
+        b: Value,
+        format: ExtendedMinMaxFormatAttr,
+        operation: ExtendedMinMaxOperationAttr,
+        subnormal: ExtendedMinMaxSubnormalAttr,
+        nan: ExtendedMinMaxNanAttr,
+        xorsign_abs: ExtendedMinMaxXorSignAbsAttr,
+    ) -> Ptr<Operation> {
+        let result_ty = match &format {
+            ExtendedMinMaxFormatAttr::F32 => FP32Type::get(ctx).into(),
+            ExtendedMinMaxFormatAttr::F16 | ExtendedMinMaxFormatAttr::Bf16 => {
+                IntegerType::get(ctx, 16, Signedness::Unsigned).into()
+            }
+            ExtendedMinMaxFormatAttr::F16x2 | ExtendedMinMaxFormatAttr::Bf16x2 => {
+                IntegerType::get(ctx, 32, Signedness::Unsigned).into()
+            }
+        };
+        let op = Operation::new(
+            ctx,
+            Self::get_concrete_op_info(),
+            vec![result_ty],
+            vec![a, b],
+            vec![],
+            0,
+        );
+        let this = Self { op };
+        this.set_attr_nvvm_extended_minmax_format(ctx, format);
+        this.set_attr_nvvm_extended_minmax_operation(ctx, operation);
+        this.set_attr_nvvm_extended_minmax_subnormal(ctx, subnormal);
+        this.set_attr_nvvm_extended_minmax_nan(ctx, nan);
+        this.set_attr_nvvm_extended_minmax_xorsign_abs(ctx, xorsign_abs);
+        this.get_operation()
+    }
+}
+
+impl Verify for ExtendedMinMaxOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let op = self.get_operation().deref(ctx);
+        let Some(format) = self.get_attr_nvvm_extended_minmax_format(ctx) else {
+            return verify_err!(op.loc(), "nvvm.extended_minmax requires a format");
+        };
+        let Some(operation) = self.get_attr_nvvm_extended_minmax_operation(ctx) else {
+            return verify_err!(op.loc(), "nvvm.extended_minmax requires an operation");
+        };
+        let Some(subnormal) = self.get_attr_nvvm_extended_minmax_subnormal(ctx) else {
+            return verify_err!(op.loc(), "nvvm.extended_minmax requires a subnormal mode");
+        };
+        let Some(nan) = self.get_attr_nvvm_extended_minmax_nan(ctx) else {
+            return verify_err!(op.loc(), "nvvm.extended_minmax requires a NaN mode");
+        };
+        let Some(xorsign_abs) = self.get_attr_nvvm_extended_minmax_xorsign_abs(ctx) else {
+            return verify_err!(op.loc(), "nvvm.extended_minmax requires an xorsign.abs mode");
+        };
+        let admitted = matches!(
+            (&*format, &*operation, &*subnormal, &*nan, &*xorsign_abs),
+"##,
+    );
+    for (index, record) in extended_minmax(catalog).enumerate() {
+        if index != 0 {
+            output.push_str(" |\n");
+        }
+        writeln!(
+            output,
+            "            ({}, {}, {}, {}, {})",
+            extended_minmax_format_attr(record),
+            extended_minmax_operation_attr(record),
+            extended_minmax_subnormal_attr(record),
+            extended_minmax_nan_attr(record),
+            extended_minmax_xorsign_abs_attr(record),
+        )
+        .unwrap();
+    }
+    output.push_str(
+        r##"        );
+        if !admitted {
+            return verify_err!(op.loc(), "nvvm.extended_minmax variant is not admitted");
+        }
+        let type_matches = |ty: pliron::r#type::TypeHandle| match &*format {
+            ExtendedMinMaxFormatAttr::F32 => ty.deref(ctx).downcast_ref::<FP32Type>().is_some(),
+            ExtendedMinMaxFormatAttr::F16 | ExtendedMinMaxFormatAttr::Bf16 => ty
+                .deref(ctx)
+                .downcast_ref::<IntegerType>()
+                .is_some_and(|integer| integer.width() == 16),
+            ExtendedMinMaxFormatAttr::F16x2 | ExtendedMinMaxFormatAttr::Bf16x2 => ty
+                .deref(ctx)
+                .downcast_ref::<IntegerType>()
+                .is_some_and(|integer| integer.width() == 32),
+        };
+        if !type_matches(op.get_operand(0).get_type(ctx))
+            || !type_matches(op.get_operand(1).get_type(ctx))
+            || !type_matches(op.get_result(0).get_type(ctx))
+        {
+            return verify_err!(op.loc(), "nvvm.extended_minmax types do not match its format");
+        }
+        Ok(())
+    }
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    ExtendedMinMaxFormatAttr::register(ctx);
+    ExtendedMinMaxOperationAttr::register(ctx);
+    ExtendedMinMaxSubnormalAttr::register(ctx);
+    ExtendedMinMaxNanAttr::register(ctx);
+    ExtendedMinMaxXorSignAbsAttr::register(ctx);
+    ExtendedMinMaxOp::register(ctx);
+}
+"##,
+    );
+    output
+}
+
+pub(in crate::render) fn render_dialect_prmt(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r##"//! One structural operation for the closed generated `prmt` family.
+
+use pliron::{
+    attribute::Attribute,
+    builtin::{
+        op_interfaces::NResultsInterface,
+        types::{IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::{pliron_attr, pliron_op};
+
+#[pliron_attr(name = "nvvm.prmt_mode", format, verifier = "succ")]
+#[derive(PartialEq, Eq, Clone, Debug, Hash)]
+pub enum PrmtModeAttr {
+    Generic,
+    F4e,
+    B4e,
+    Rc8,
+    Ecl,
+    Ecr,
+    Rc16,
+}
+
+/// Byte permutation whose exact mode is carried by an attribute.
+#[pliron_op(
+    name = "nvvm.prmt",
+    format,
+    interfaces = [NResultsInterface<1>],
+    attributes = (nvvm_prmt_mode: PrmtModeAttr)
+)]
+pub struct PrmtOp;
+
+impl PrmtOp {
+    pub fn new(op: Ptr<Operation>) -> Self {
+        Self { op }
+    }
+
+    pub fn build(ctx: &mut Context, operands: Vec<Value>, mode: PrmtModeAttr) -> Ptr<Operation> {
+        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
+        let op = Operation::new(
+            ctx,
+            Self::get_concrete_op_info(),
+            vec![result_ty.into()],
+            operands,
+            vec![],
+            0,
+        );
+        let this = Self { op };
+        this.set_attr_nvvm_prmt_mode(ctx, mode);
+        this.get_operation()
+    }
+}
+
+impl Verify for PrmtOp {
+    fn verify(&self, ctx: &Context) -> Result<(), Error> {
+        let op = self.get_operation().deref(ctx);
+        let Some(mode) = self.get_attr_nvvm_prmt_mode(ctx) else {
+            return verify_err!(op.loc(), "nvvm.prmt requires a mode attribute");
+        };
+        let expected_operands = match &*mode {
+            PrmtModeAttr::Generic | PrmtModeAttr::F4e | PrmtModeAttr::B4e => 3,
+            PrmtModeAttr::Rc8 | PrmtModeAttr::Ecl | PrmtModeAttr::Ecr | PrmtModeAttr::Rc16 => 2,
+        };
+        if op.get_num_operands() != expected_operands || op.get_num_results() != 1 {
+            return verify_err!(
+                op.loc(),
+                "nvvm.prmt {:?} requires {} operands and one result",
+                mode,
+                expected_operands
+            );
+        }
+        for index in 0..expected_operands {
+            let ty = op.get_operand(index).get_type(ctx);
+            if ty
+                .deref(ctx)
+                .downcast_ref::<IntegerType>()
+                .is_none_or(|integer| integer.width() != 32)
+            {
+                return verify_err!(op.loc(), "nvvm.prmt operand {} must be a 32-bit integer", index);
+            }
+        }
+        let result_ty = op.get_result(0).get_type(ctx);
+        if result_ty
+            .deref(ctx)
+            .downcast_ref::<IntegerType>()
+            .is_none_or(|integer| integer.width() != 32)
+        {
+            return verify_err!(op.loc(), "nvvm.prmt result must be a 32-bit integer");
+        }
+        Ok(())
+    }
+}
+
+pub(super) fn register(ctx: &mut Context) {
+    PrmtModeAttr::register(ctx);
+    PrmtOp::register(ctx);
+}
+"##,
+    );
+    output
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/dialect/warp_sync.rs b/crates/cuda-intrinsics-gen/src/render/dialect/warp_sync.rs
new file mode 100644
index 0000000000..0c2be7cc00
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/dialect/warp_sync.rs
@@ -0,0 +1,1132 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    ActiveMaskAdapter, CatalogFile, CpAsyncControlOperation, CpAsyncSourceSize,
+    MbarrierBasicAdapter, MbarrierBasicOperation, MbarrierExtendedOperation, MbarrierStateSpace,
+    VoteMode, WarpBarrierAdapter, WarpMatchMode, WarpShuffleAdapter, WarpShuffleValueKind,
+};
+use crate::render::common::{rust_header, source_label};
+use crate::render::families::{
+    active_masks, cp_async_controls, cp_async_copies, cp_async_mbarriers, dot_product_ptx,
+    dot_products, elect_intrinsics, mbarrier_basics, mbarrier_extended, redux, sregs,
+    sync_intrinsics, vote_intrinsics, warp_barriers, warp_matches, warp_shuffles,
+};
+use std::fmt::Write as _;
+
+pub(in crate::render) fn render_dialect_elect(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Generated warp leader-election operation.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::IntegerType,\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::{TypeHandle, Typed},\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\n",
+    );
+    for record in elect_intrinsics(catalog) {
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<2>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n}\n\n");
+        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
+        output.push_str(
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 1 || op.get_num_results() != 2 {\n            return verify_err!(op.loc(), \"nvvm.elect_sync requires one i32 operand and results [i32, i1]\");\n        }\n        if !is_integer_width(ctx, op.get_operand(0).get_type(ctx), 32)\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), 32)\n            || !is_integer_width(ctx, op.get_result(1).get_type(ctx), 1)\n        {\n            return verify_err!(op.loc(), \"nvvm.elect_sync requires one i32 operand and results [i32, i1]\");\n        }\n        Ok(())\n    }\n}\n\n",
+        );
+    }
+    output.push_str(
+        "fn is_integer_width(ctx: &Context, ty: TypeHandle, width: u32) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\npub(super) fn register(ctx: &mut Context) {\n",
+    );
+    for record in elect_intrinsics(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_sreg(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural NVVM operations for generated special-register reads.\n\nuse pliron::{\n    builtin::op_interfaces::{NOpdsInterface, NResultsInterface},\n    builtin::types::IntegerType,\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\n",
+    );
+    for record in sregs(catalog) {
+        let width = record.scalar_width().unwrap();
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "/// Catalog ID `{}`; {} returns one `i{width}` result.",
+            record.id,
+            source_label(record)
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<0>, NResultsInterface<1>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self {\n");
+        writeln!(output, "        Self {{ op }}").unwrap();
+        output.push_str("    }\n}\n");
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    fn verify(&self, ctx: &Context) -> Result<(), Error> {\n");
+        writeln!(
+            output,
+            "        verify_scalar_result(ctx, self.get_operation(), {:?}, {width})",
+            record.dialect.op_name
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    output.push_str(
+        "fn verify_scalar_result(\n    ctx: &Context,\n    op: Ptr<Operation>,\n    name: &str,\n    width: u32,\n) -> Result<(), Error> {\n    let op = op.deref(ctx);\n    let ty = op.get_result(0).get_type(ctx);\n    let ty_object = ty.deref(ctx);\n    let Some(integer) = ty_object.downcast_ref::<IntegerType>() else {\n        return verify_err!(op.loc(), \"{} result must be an integer\", name);\n    };\n    if integer.width() != width {\n        return verify_err!(\n            op.loc(),\n            \"{} result must be a {}-bit integer\",\n            name,\n            width\n        );\n    }\n    Ok(())\n}\n\npub(super) fn register(ctx: &mut Context) {\n",
+    );
+    for record in sregs(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_sync(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operation for generated CTA synchronization.\n\nuse pliron::{\n    builtin::op_interfaces::{NOpdsInterface, NResultsInterface},\n    context::{Context, Ptr},\n    op::Op,\n    operation::Operation,\n};\nuse pliron_derive::pliron_op;\n\n",
+    );
+    for record in sync_intrinsics(catalog) {
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    verifier = \"succ\",\n    interfaces = [NOpdsInterface<0>, NResultsInterface<0>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str(
+            "    pub fn new(op: Ptr<Operation>) -> Self {\n        Self { op }\n    }\n}\n\n",
+        );
+    }
+    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
+    for record in sync_intrinsics(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_vote(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operations for the generated `vote.sync` family.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_integer_width(ctx: &Context, ty: pliron::r#type::TypeHandle, width: u32) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\n",
+    );
+    for record in vote_intrinsics(catalog) {
+        let result_width = match record.vote.as_ref().unwrap().mode {
+            VoteMode::All | VoteMode::Any | VoteMode::Uni => 1,
+            VoteMode::Ballot => 32,
+        };
+        let result_signedness = if result_width == 32 {
+            "Unsigned"
+        } else {
+            "Signless"
+        };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str(
+            "///\n/// Operands are `[member_mask, predicate]`. The generated verifier keeps\n/// the mask, predicate, and result types exact.\n",
+        );
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, member_mask: Value, predicate: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, {result_width}, Signedness::{result_signedness});\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![member_mask, predicate],\n            vec![],\n            0,\n        )\n    }}\n}}"
+        )
+        .unwrap();
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 2 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_integer_width(ctx, op.get_operand(0).get_type(ctx), 32)\n            || !is_integer_width(ctx, op.get_operand(1).get_type(ctx), 1)\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), {result_width})\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+            format!(
+                "{} requires exactly two operands [member_mask, predicate] and one result",
+                record.dialect.op_name
+            ),
+            format!(
+                "{} requires i32 member mask, i1 predicate, and i{result_width} result",
+                record.dialect.op_name
+            ),
+        )
+        .unwrap();
+    }
+    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
+    for record in vote_intrinsics(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_active_mask(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operation for the generated active warp mask.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\n",
+    );
+    for record in active_masks(catalog) {
+        debug_assert_eq!(
+            record.active_mask.as_ref().unwrap().adapter,
+            ActiveMaskAdapter::DirectZeroOperandMask
+        );
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<0>, NResultsInterface<1>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str(
+            "    pub fn new(op: Ptr<Operation>) -> Self {\n        Self { op }\n    }\n\n    pub fn build(ctx: &mut Context) -> Ptr<Operation> {\n        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![],\n            vec![],\n            0,\n        )\n    }\n}\n",
+        );
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        let valid = op.get_num_operands() == 0\n            && op.get_num_results() == 1\n            && op.get_result(0).get_type(ctx).deref(ctx)\n                .downcast_ref::<IntegerType>()\n                .is_some_and(|integer| integer.width() == 32);\n        if !valid {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+            format!("{} requires no operands and one i32 result", record.dialect.op_name)
+        )
+        .unwrap();
+    }
+    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
+    for record in active_masks(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_cp_async_copy(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r#"//! Structural operations for classic `cp.async` instructions.
+
+use dialect_mir::{ops::MirConstantOp, types::{MirPtrType, address_space}};
+use pliron::{
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        ops::ConstantOp,
+        types::{IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::pliron_op;
+
+fn verify_pointer(
+    ctx: &Context,
+    op: &Operation,
+    value: Value,
+    role: &str,
+    allowed_address_spaces: &[u32],
+) -> Result<(), Error> {
+    let ty = value.get_type(ctx);
+    let ty = ty.deref(ctx);
+    let Some(pointer) = ty.downcast_ref::<MirPtrType>() else {
+        return verify_err!(op.loc(), "{role} must be a MIR pointer");
+    };
+    if !allowed_address_spaces.contains(&pointer.address_space) {
+        return verify_err!(op.loc(), "{role} has the wrong address space");
+    }
+    Ok(())
+}
+
+fn verify_cp_async_copy(
+    ctx: &Context,
+    operation: Ptr<Operation>,
+    name: &str,
+    has_source_size: bool,
+) -> Result<(), Error> {
+    let op = operation.deref(ctx);
+    let expected_operands = if has_source_size { 3 } else { 2 };
+    if op.get_num_operands() != expected_operands || op.get_num_results() != 0 {
+        return verify_err!(op.loc(), "{name} has the wrong operand or result count");
+    }
+    verify_pointer(
+        ctx,
+        &op,
+        op.get_operand(0),
+        "shared destination",
+        &[address_space::GENERIC, address_space::SHARED],
+    )?;
+    verify_pointer(
+        ctx,
+        &op,
+        op.get_operand(1),
+        "global source",
+        &[address_space::GENERIC, address_space::GLOBAL],
+    )?;
+    if has_source_size {
+        let ty = op.get_operand(2).get_type(ctx);
+        let ty = ty.deref(ctx);
+        let Some(integer) = ty.downcast_ref::<IntegerType>() else {
+            return verify_err!(op.loc(), "source size must be u32");
+        };
+        if integer.width() != 32 || integer.signedness() != Signedness::Unsigned {
+            return verify_err!(op.loc(), "source size must be u32");
+        }
+    }
+    Ok(())
+}
+
+fn verify_cp_async_control(
+    ctx: &Context,
+    operation: Ptr<Operation>,
+    name: &str,
+    has_immediate: bool,
+) -> Result<(), Error> {
+    let op = operation.deref(ctx);
+    let expected_operands = usize::from(has_immediate);
+    if op.get_num_operands() != expected_operands || op.get_num_results() != 0 {
+        return verify_err!(op.loc(), "{name} has the wrong operand or result count");
+    }
+    if has_immediate {
+        let value = op.get_operand(0);
+        let ty = value.get_type(ctx);
+        let ty = ty.deref(ctx);
+        let Some(integer) = ty.downcast_ref::<IntegerType>() else {
+            return verify_err!(op.loc(), "maximum pending group count must be u32");
+        };
+        if integer.width() != 32 || integer.signedness() != Signedness::Unsigned {
+            return verify_err!(op.loc(), "maximum pending group count must be u32");
+        }
+        let Some(defining_op) = value.defining_op() else {
+            return verify_err!(op.loc(), "maximum pending group count must be a compile-time constant");
+        };
+        if Operation::get_op::<MirConstantOp>(defining_op, ctx).is_none()
+            && Operation::get_op::<ConstantOp>(defining_op, ctx).is_none()
+        {
+            return verify_err!(op.loc(), "maximum pending group count must be a compile-time constant");
+        }
+    }
+    Ok(())
+}
+
+fn verify_cp_async_mbarrier(
+    ctx: &Context,
+    operation: Ptr<Operation>,
+    name: &str,
+) -> Result<(), Error> {
+    let op = operation.deref(ctx);
+    if op.get_num_operands() != 1 || op.get_num_results() != 0 {
+        return verify_err!(op.loc(), "{name} has the wrong operand or result count");
+    }
+    let ty = op.get_operand(0).get_type(ctx);
+    let ty = ty.deref(ctx);
+    let Some(pointer) = ty.downcast_ref::<MirPtrType>() else {
+        return verify_err!(op.loc(), "mbarrier address must be a MIR pointer");
+    };
+    let pointee = pointer.pointee.deref(ctx);
+    let valid_pointee = pointee
+        .downcast_ref::<IntegerType>()
+        .is_some_and(|integer| {
+            integer.width() == 64 && integer.signedness() == Signedness::Unsigned
+        });
+    if !pointer.is_mutable
+        || !valid_pointee
+        || !matches!(
+            pointer.address_space,
+            address_space::GENERIC | address_space::SHARED
+        )
+    {
+        return verify_err!(
+            op.loc(),
+            "mbarrier address must be a mutable generic/shared pointer to u64"
+        );
+    }
+    Ok(())
+}
+
+"#,
+    );
+    for record in cp_async_copies(catalog) {
+        let copy = record.cp_async_copy.as_ref().unwrap();
+        let dynamic = copy.source_size == CpAsyncSourceSize::Runtime;
+        let operand_count = if dynamic { 3 } else { 2 };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<0>],\n)]\npub struct {};",
+            record.dialect.op_name, record.dialect.op_type
+        )
+        .unwrap();
+        writeln!(output, "impl {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n");
+        if dynamic {
+            output.push_str(
+                "    pub fn build(ctx: &mut Context, shared_dst: Value, global_src: Value, source_size: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![shared_dst, global_src, source_size], vec![], 0)\n    }\n",
+            );
+        } else {
+            output.push_str(
+                "    pub fn build(ctx: &mut Context, shared_dst: Value, global_src: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![shared_dst, global_src], vec![], 0)\n    }\n",
+            );
+        }
+        output.push_str("}\n\n");
+        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_cp_async_copy(ctx, self.get_operation(), {:?}, {dynamic})\n    }}\n}}\n",
+            record.dialect.op_name
+        )
+        .unwrap();
+    }
+    for record in cp_async_controls(catalog) {
+        let control = record.cp_async_control.as_ref().unwrap();
+        let has_immediate = control.operation == CpAsyncControlOperation::WaitGroup;
+        let operand_count = usize::from(has_immediate);
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<0>],\n)]\npub struct {};",
+            record.dialect.op_name, record.dialect.op_type
+        )
+        .unwrap();
+        writeln!(output, "impl {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n");
+        if has_immediate {
+            output.push_str(
+                "    pub fn build(ctx: &mut Context, max_pending: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![max_pending], vec![], 0)\n    }\n",
+            );
+        } else {
+            output.push_str(
+                "    pub fn build(ctx: &mut Context) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)\n    }\n",
+            );
+        }
+        output.push_str("}\n\n");
+        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_cp_async_control(ctx, self.get_operation(), {:?}, {has_immediate})\n    }}\n}}\n",
+            record.dialect.op_name
+        )
+        .unwrap();
+    }
+    for record in cp_async_mbarriers(catalog) {
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<0>],\n)]\npub struct {};",
+            record.dialect.op_name, record.dialect.op_type
+        )
+        .unwrap();
+        writeln!(output, "impl {} {{", record.dialect.op_type).unwrap();
+        output.push_str(
+            "    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n    pub fn build(ctx: &mut Context, barrier: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![barrier], vec![], 0)\n    }\n}\n\n",
+        );
+        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_cp_async_mbarrier(ctx, self.get_operation(), {:?})\n    }}\n}}\n",
+            record.dialect.op_name
+        )
+        .unwrap();
+    }
+    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
+    for record in cp_async_copies(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    for record in cp_async_controls(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    for record in cp_async_mbarriers(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_mbarrier_basic(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r#"//! Structural operations for the basic shared-memory mbarrier lifecycle.
+
+use dialect_mir::types::{MirPtrType, address_space};
+use pliron::{
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        types::{IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::pliron_op;
+
+#[derive(Clone, Copy)]
+enum MbarrierBasicShape {
+    Init,
+    Arrive,
+    TestWait,
+    Inval,
+}
+
+fn is_integer(
+    ctx: &Context,
+    value: Value,
+    width: u32,
+    signedness: Signedness,
+) -> bool {
+    value
+        .get_type(ctx)
+        .deref(ctx)
+        .downcast_ref::<IntegerType>()
+        .is_some_and(|integer| {
+            integer.width() == width && integer.signedness() == signedness
+        })
+}
+
+fn verify_barrier_pointer(ctx: &Context, op: &Operation, value: Value) -> Result<(), Error> {
+    let ty = value.get_type(ctx);
+    let ty = ty.deref(ctx);
+    let Some(pointer) = ty.downcast_ref::<MirPtrType>() else {
+        return verify_err!(op.loc(), "mbarrier address must be a MIR pointer");
+    };
+    if !matches!(pointer.address_space, address_space::GENERIC | address_space::SHARED) {
+        return verify_err!(op.loc(), "mbarrier address must be generic or shared");
+    }
+    Ok(())
+}
+
+fn verify_mbarrier_basic(
+    ctx: &Context,
+    operation: Ptr<Operation>,
+    name: &str,
+    shape: MbarrierBasicShape,
+) -> Result<(), Error> {
+    let op = operation.deref(ctx);
+    let (operands, results) = match shape {
+        MbarrierBasicShape::Init | MbarrierBasicShape::TestWait => (2, usize::from(matches!(shape, MbarrierBasicShape::TestWait))),
+        MbarrierBasicShape::Arrive => (1, 1),
+        MbarrierBasicShape::Inval => (1, 0),
+    };
+    if op.get_num_operands() != operands || op.get_num_results() != results {
+        return verify_err!(op.loc(), "{name} has the wrong operand or result count");
+    }
+    verify_barrier_pointer(ctx, &op, op.get_operand(0))?;
+    match shape {
+        MbarrierBasicShape::Init => {
+            if !is_integer(ctx, op.get_operand(1), 32, Signedness::Unsigned) {
+                return verify_err!(op.loc(), "mbarrier expected count must be u32");
+            }
+        }
+        MbarrierBasicShape::Arrive => {
+            if !is_integer(ctx, op.get_result(0), 64, Signedness::Unsigned) {
+                return verify_err!(op.loc(), "mbarrier arrival token must be u64");
+            }
+        }
+        MbarrierBasicShape::TestWait => {
+            if !is_integer(ctx, op.get_operand(1), 64, Signedness::Unsigned)
+                || !is_integer(ctx, op.get_result(0), 1, Signedness::Signless)
+            {
+                return verify_err!(op.loc(), "mbarrier test-wait requires a u64 token and i1 result");
+            }
+        }
+        MbarrierBasicShape::Inval => {}
+    }
+    Ok(())
+}
+
+"#,
+    );
+    for record in mbarrier_basics(catalog) {
+        let mbarrier = record.mbarrier_basic.as_ref().unwrap();
+        debug_assert_eq!(mbarrier.state_space, MbarrierStateSpace::Shared);
+        let (operand_count, result_count, shape, build) = match mbarrier.operation {
+            MbarrierBasicOperation::Init => {
+                debug_assert_eq!(
+                    mbarrier.adapter,
+                    MbarrierBasicAdapter::InitPointerCountToVoid
+                );
+                (
+                    2,
+                    0,
+                    "Init",
+                    "    pub fn build(ctx: &mut Context, barrier: Value, expected_count: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![barrier, expected_count], vec![], 0)\n    }\n",
+                )
+            }
+            MbarrierBasicOperation::Arrive => {
+                debug_assert_eq!(mbarrier.adapter, MbarrierBasicAdapter::ArrivePointerToToken);
+                (
+                    1,
+                    1,
+                    "Arrive",
+                    "    pub fn build(ctx: &mut Context, barrier: Value) -> Ptr<Operation> {\n        let token_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![token_ty.into()], vec![barrier], vec![], 0)\n    }\n",
+                )
+            }
+            MbarrierBasicOperation::TestWait => {
+                debug_assert_eq!(
+                    mbarrier.adapter,
+                    MbarrierBasicAdapter::TestWaitPointerTokenToPredicate
+                );
+                (
+                    2,
+                    1,
+                    "TestWait",
+                    "    pub fn build(ctx: &mut Context, barrier: Value, token: Value) -> Ptr<Operation> {\n        let predicate_ty = IntegerType::get(ctx, 1, Signedness::Signless);\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![predicate_ty.into()], vec![barrier, token], vec![], 0)\n    }\n",
+                )
+            }
+            MbarrierBasicOperation::Inval => {
+                debug_assert_eq!(mbarrier.adapter, MbarrierBasicAdapter::InvalPointerToVoid);
+                (
+                    1,
+                    0,
+                    "Inval",
+                    "    pub fn build(ctx: &mut Context, barrier: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![barrier], vec![], 0)\n    }\n",
+                )
+            }
+        };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<{result_count}>],\n)]\npub struct {};",
+            record.dialect.op_name, record.dialect.op_type
+        )
+        .unwrap();
+        writeln!(output, "impl {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n");
+        output.push_str(build);
+        output.push_str("}\n\n");
+        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_mbarrier_basic(ctx, self.get_operation(), {:?}, MbarrierBasicShape::{shape})\n    }}\n}}\n",
+            record.dialect.op_name
+        )
+        .unwrap();
+    }
+    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
+    for record in mbarrier_basics(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_mbarrier_extended(
+    catalog: &CatalogFile,
+    hash: &str,
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        r#"//! Structural operations for extended mbarrier and async-proxy instructions.
+
+use dialect_mir::types::{MirPtrType, address_space};
+use pliron::{
+    builtin::{
+        op_interfaces::{NOpdsInterface, NResultsInterface},
+        types::{IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::{Context, Ptr},
+    location::Located,
+    op::Op,
+    operation::Operation,
+    result::Error,
+    r#type::Typed,
+    value::Value,
+    verify_err,
+};
+use pliron_derive::pliron_op;
+
+#[derive(Clone, Copy)]
+enum MbarrierExtendedShape {
+    PointerU32ToU64,
+    RawU64ToVoid,
+    PointerU64ToI1,
+    PointerU32ToI1,
+    ZeroToVoid,
+    U32ToVoid,
+}
+
+fn is_integer(ctx: &Context, value: Value, width: u32, signedness: Signedness) -> bool {
+    value
+        .get_type(ctx)
+        .deref(ctx)
+        .downcast_ref::<IntegerType>()
+        .is_some_and(|integer| {
+            integer.width() == width && integer.signedness() == signedness
+        })
+}
+
+fn verify_barrier_pointer(ctx: &Context, op: &Operation, value: Value) -> Result<(), Error> {
+    let ty = value.get_type(ctx);
+    let ty = ty.deref(ctx);
+    let Some(pointer) = ty.downcast_ref::<MirPtrType>() else {
+        return verify_err!(op.loc(), "mbarrier address must be a MIR pointer");
+    };
+    if !matches!(pointer.address_space, address_space::GENERIC | address_space::SHARED) {
+        return verify_err!(op.loc(), "mbarrier address must be generic or shared");
+    }
+    Ok(())
+}
+
+fn verify_mbarrier_extended(
+    ctx: &Context,
+    operation: Ptr<Operation>,
+    name: &str,
+    shape: MbarrierExtendedShape,
+) -> Result<(), Error> {
+    let op = operation.deref(ctx);
+    let (operands, results) = match shape {
+        MbarrierExtendedShape::PointerU32ToU64
+        | MbarrierExtendedShape::PointerU64ToI1
+        | MbarrierExtendedShape::PointerU32ToI1 => (2, 1),
+        MbarrierExtendedShape::RawU64ToVoid | MbarrierExtendedShape::U32ToVoid => (1, 0),
+        MbarrierExtendedShape::ZeroToVoid => (0, 0),
+    };
+    if op.get_num_operands() != operands || op.get_num_results() != results {
+        return verify_err!(op.loc(), "{name} has the wrong operand or result count");
+    }
+    match shape {
+        MbarrierExtendedShape::PointerU32ToU64 => {
+            verify_barrier_pointer(ctx, &op, op.get_operand(0))?;
+            if !is_integer(ctx, op.get_operand(1), 32, Signedness::Unsigned)
+                || !is_integer(ctx, op.get_result(0), 64, Signedness::Unsigned)
+            {
+                return verify_err!(op.loc(), "mbarrier arrival requires u32 bytes and a u64 token");
+            }
+        }
+        MbarrierExtendedShape::PointerU64ToI1 => {
+            verify_barrier_pointer(ctx, &op, op.get_operand(0))?;
+            if !is_integer(ctx, op.get_operand(1), 64, Signedness::Unsigned)
+                || !is_integer(ctx, op.get_result(0), 1, Signedness::Signless)
+            {
+                return verify_err!(op.loc(), "mbarrier wait requires a u64 token and i1 result");
+            }
+        }
+        MbarrierExtendedShape::PointerU32ToI1 => {
+            verify_barrier_pointer(ctx, &op, op.get_operand(0))?;
+            if !is_integer(ctx, op.get_operand(1), 32, Signedness::Unsigned)
+                || !is_integer(ctx, op.get_result(0), 1, Signedness::Signless)
+            {
+                return verify_err!(op.loc(), "mbarrier wait requires u32 parity and i1 result");
+            }
+        }
+        MbarrierExtendedShape::RawU64ToVoid => {
+            if !is_integer(ctx, op.get_operand(0), 64, Signedness::Unsigned) {
+                return verify_err!(op.loc(), "remote mbarrier address must be u64");
+            }
+        }
+        MbarrierExtendedShape::U32ToVoid => {
+            if !is_integer(ctx, op.get_operand(0), 32, Signedness::Unsigned) {
+                return verify_err!(op.loc(), "nanosleep duration must be u32");
+            }
+        }
+        MbarrierExtendedShape::ZeroToVoid => {}
+    }
+    Ok(())
+}
+
+"#,
+    );
+    for record in mbarrier_extended(catalog) {
+        let contract = record.mbarrier_extended.as_ref().unwrap();
+        let (operand_count, result_count, shape, build) = match contract.operation {
+            MbarrierExtendedOperation::ArriveExpectTxCta
+            | MbarrierExtendedOperation::ArriveExpectTxCluster => (
+                2,
+                1,
+                "PointerU32ToU64",
+                "    pub fn build(ctx: &mut Context, barrier: Value, bytes: Value) -> Ptr<Operation> {\n        let token_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![token_ty.into()], vec![barrier, bytes], vec![], 0)\n    }\n",
+            ),
+            MbarrierExtendedOperation::ArriveRemoteCluster => (
+                1,
+                0,
+                "RawU64ToVoid",
+                "    pub fn build(ctx: &mut Context, address: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![address], vec![], 0)\n    }\n",
+            ),
+            MbarrierExtendedOperation::TryWaitTokenCta => (
+                2,
+                1,
+                "PointerU64ToI1",
+                "    pub fn build(ctx: &mut Context, barrier: Value, token: Value) -> Ptr<Operation> {\n        let result_ty = IntegerType::get(ctx, 1, Signedness::Signless);\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![result_ty.into()], vec![barrier, token], vec![], 0)\n    }\n",
+            ),
+            MbarrierExtendedOperation::TryWaitParityCta
+            | MbarrierExtendedOperation::TryWaitParityCluster => (
+                2,
+                1,
+                "PointerU32ToI1",
+                "    pub fn build(ctx: &mut Context, barrier: Value, parity: Value) -> Ptr<Operation> {\n        let result_ty = IntegerType::get(ctx, 1, Signedness::Signless);\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![result_ty.into()], vec![barrier, parity], vec![], 0)\n    }\n",
+            ),
+            MbarrierExtendedOperation::FenceProxyAsyncSharedCta
+            | MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster
+            | MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster
+            | MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster => (
+                0,
+                0,
+                "ZeroToVoid",
+                "    pub fn build(ctx: &mut Context) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![], vec![], 0)\n    }\n",
+            ),
+            MbarrierExtendedOperation::Nanosleep => (
+                1,
+                0,
+                "U32ToVoid",
+                "    pub fn build(ctx: &mut Context, ns: Value) -> Ptr<Operation> {\n        Operation::new(ctx, Self::get_concrete_op_info(), vec![], vec![ns], vec![], 0)\n    }\n",
+            ),
+        };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "/// Lowers to `{}`.", record.expected_ptx).unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<{result_count}>],\n)]\npub struct {};",
+            record.dialect.op_name, record.dialect.op_type
+        )
+        .unwrap();
+        writeln!(output, "impl {} {{", record.dialect.op_type).unwrap();
+        output.push_str("    pub fn new(op: Ptr<Operation>) -> Self { Self { op } }\n\n");
+        output.push_str(build);
+        output.push_str("}\n\n");
+        writeln!(output, "impl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        verify_mbarrier_extended(ctx, self.get_operation(), {:?}, MbarrierExtendedShape::{shape})\n    }}\n}}\n",
+            record.dialect.op_name
+        )
+        .unwrap();
+    }
+    output.push_str("pub(super) fn register(ctx: &mut Context) {\n");
+    for record in mbarrier_extended(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_warp_match(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operations for the generated `match.sync` family.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_integer_width(ctx: &Context, ty: pliron::r#type::TypeHandle, width: u32) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == width)\n}\n\n",
+    );
+    for record in warp_matches(catalog) {
+        let warp_match = record.warp_match.as_ref().unwrap();
+        let value_width = warp_match.value_width.bits();
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str(
+            "///\n/// Operands are `[member_mask, value]`; the result is a 32-bit lane mask.\n",
+        );
+        if warp_match.mode == WarpMatchMode::All {
+            output.push_str(
+                "/// LLVM also returns a predicate, which the established API discards.\n",
+            );
+        }
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str(
+            "    pub fn new(op: Ptr<Operation>) -> Self {\n        Self { op }\n    }\n\n    pub fn build(ctx: &mut Context, member_mask: Value, value: Value) -> Ptr<Operation> {\n        let result_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![member_mask, value],\n            vec![],\n            0,\n        )\n    }\n}\n",
+        );
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 2 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_integer_width(ctx, op.get_operand(0).get_type(ctx), 32)\n            || !is_integer_width(ctx, op.get_operand(1).get_type(ctx), {value_width})\n            || !is_integer_width(ctx, op.get_result(0).get_type(ctx), 32)\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+            format!(
+                "{} requires exactly [member_mask, value] and one mask result",
+                record.dialect.op_name
+            ),
+            format!(
+                "{} requires i32 member mask, i{value_width} value, and i32 result",
+                record.dialect.op_name
+            ),
+        )
+        .unwrap();
+    }
+    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
+    for record in warp_matches(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_warp_barrier(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operation for generated warp synchronization.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::IntegerType,\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\n",
+    );
+    for record in warp_barriers(catalog) {
+        debug_assert_eq!(
+            record.warp_barrier.as_ref().unwrap().adapter,
+            WarpBarrierAdapter::DirectMemberMask
+        );
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("///\n/// The operand is the 32-bit warp participation mask.\n");
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<1>, NResultsInterface<0>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        output.push_str(
+            "    pub fn new(op: Ptr<Operation>) -> Self {\n        Self { op }\n    }\n\n    pub fn build(ctx: &mut Context, member_mask: Value) -> Ptr<Operation> {\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![],\n            vec![member_mask],\n            vec![],\n            0,\n        )\n    }\n}\n",
+        );
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 1 || op.get_num_results() != 0 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_i32(ctx, op.get_operand(0).get_type(ctx)) {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+            format!(
+                "{} requires exactly one member-mask operand and no results",
+                record.dialect.op_name
+            ),
+            format!("{} member mask must be i32", record.dialect.op_name),
+        )
+        .unwrap();
+    }
+    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
+    for record in warp_barriers(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_warp_shuffle(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operations for the generated `shfl.sync` family.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{FP32Type, IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\nfn is_i64(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 64)\n}\n\nfn is_f32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx).downcast_ref::<FP32Type>().is_some()\n}\n\n",
+    );
+    for record in warp_shuffles(catalog) {
+        let shuffle = record.warp_shuffle.as_ref().unwrap();
+        debug_assert!(matches!(
+            (shuffle.value_kind, shuffle.adapter),
+            (
+                WarpShuffleValueKind::I32 | WarpShuffleValueKind::F32,
+                WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp
+            ) | (
+                WarpShuffleValueKind::I64,
+                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
+            )
+        ));
+        let (result_builder, value_check, value_label) = match shuffle.value_kind {
+            WarpShuffleValueKind::I32 => (
+                "IntegerType::get(ctx, 32, Signedness::Unsigned).into()",
+                "is_i32",
+                "i32",
+            ),
+            WarpShuffleValueKind::F32 => ("FP32Type::get(ctx).into()", "is_f32", "f32"),
+            WarpShuffleValueKind::I64 => (
+                "IntegerType::get(ctx, 64, Signedness::Unsigned).into()",
+                "is_i64",
+                "i64",
+            ),
+        };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str("///\n/// Operands are `[member_mask, value, lane_or_delta]`.\n");
+        if shuffle.value_kind == WarpShuffleValueKind::I64 {
+            output.push_str(
+                "/// Lowering splits the value into two `b32` halves, shuffles both, and reassembles it.\n",
+            );
+        } else {
+            output.push_str(
+                "/// Generated lowering inserts the fixed clamp required by the selected shuffle mode.\n",
+            );
+        }
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<3>, NResultsInterface<1>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(\n        ctx: &mut Context,\n        member_mask: Value,\n        value: Value,\n        lane_or_delta: Value,\n    ) -> Ptr<Operation> {{\n        let result_ty: pliron::r#type::TypeHandle = {result_builder};\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty],\n            vec![member_mask, value, lane_or_delta],\n            vec![],\n            0,\n        )\n    }}\n}}"
+        )
+        .unwrap();
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 3 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_i32(ctx, op.get_operand(0).get_type(ctx))\n            || !{value_check}(ctx, op.get_operand(1).get_type(ctx))\n            || !is_i32(ctx, op.get_operand(2).get_type(ctx))\n            || !{value_check}(ctx, op.get_result(0).get_type(ctx))\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+            format!(
+                "{} requires exactly [member_mask, value, lane_or_delta] and one result",
+                record.dialect.op_name
+            ),
+            format!(
+                "{} requires i32 mask/lane and {value_label} value/result",
+                record.dialect.op_name
+            ),
+        )
+        .unwrap();
+    }
+    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
+    for record in warp_shuffles(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_dotprod(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Structural operations for generated packed integer dot products.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\n",
+    );
+    for record in dot_products(catalog) {
+        let signedness = match record.rust.result.as_str() {
+            "i32" => "Signed",
+            "u32" => "Unsigned",
+            result => panic!("unsupported dot-product result {result}"),
+        };
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(
+            output,
+            "/// Lowers to `{}`.",
+            dot_product_ptx(record).replace("$0, $1, $2, $3", "%d, %a, %b, %c")
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<3>, NResultsInterface<1>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, a: Value, b: Value, c: Value) -> Ptr<Operation> {{\n        let result_ty = IntegerType::get(ctx, 32, Signedness::{signedness});\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![a, b, c],\n            vec![],\n            0,\n        )\n    }}\n}}"
+        )
+        .unwrap();
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 3 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !(0..3).all(|index| is_i32(ctx, op.get_operand(index).get_type(ctx)))\n            || !is_i32(ctx, op.get_result(0).get_type(ctx))\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+            format!(
+                "{} requires exactly three operands and one result",
+                record.dialect.op_name
+            ),
+            format!(
+                "{} operands and result must be 32-bit integers",
+                record.dialect.op_name
+            ),
+        )
+        .unwrap();
+    }
+    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
+    for record in dot_products(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(in crate::render) fn render_dialect_redux(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    let has_f32 = redux(catalog).any(|record| record.dialect.results == ["f32"]);
+    if has_f32 {
+        output.push_str(
+            "//! Structural NVVM operations for the closed generated `redux.sync` family.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{FP32Type, IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\nfn is_f32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx).downcast_ref::<FP32Type>().is_some()\n}\n\n",
+        );
+    } else {
+        output.push_str(
+            "//! Structural NVVM operations for the closed generated `redux.sync` family.\n\nuse pliron::{\n    builtin::{\n        op_interfaces::{NOpdsInterface, NResultsInterface},\n        types::{IntegerType, Signedness},\n    },\n    common_traits::Verify,\n    context::{Context, Ptr},\n    location::Located,\n    op::Op,\n    operation::Operation,\n    result::Error,\n    r#type::Typed,\n    value::Value,\n    verify_err,\n};\nuse pliron_derive::pliron_op;\n\nfn is_i32(ctx: &Context, ty: pliron::r#type::TypeHandle) -> bool {\n    ty.deref(ctx)\n        .downcast_ref::<IntegerType>()\n        .is_some_and(|integer| integer.width() == 32)\n}\n\n",
+        );
+    }
+    for record in redux(catalog) {
+        writeln!(output, "/// {}", record.summary).unwrap();
+        output.push_str(
+            "///\n/// Dialect operands are `[member_mask, value]`; generated lowering adapts\n/// them to LLVM's `(value, member_mask)` signature.\n",
+        );
+        writeln!(
+            output,
+            "#[pliron_op(\n    name = {:?},\n    format,\n    interfaces = [NOpdsInterface<2>, NResultsInterface<1>],\n)]",
+            record.dialect.op_name
+        )
+        .unwrap();
+        writeln!(output, "pub struct {};", record.dialect.op_type).unwrap();
+        writeln!(output, "\nimpl {} {{", record.dialect.op_type).unwrap();
+        let (result_type, value_predicate, type_error) = match record.rust.result.as_str() {
+            "u32" => (
+                "IntegerType::get(ctx, 32, Signedness::Unsigned)",
+                "is_i32",
+                format!(
+                    "{} member mask, value, and result must be 32-bit integers",
+                    record.dialect.op_name
+                ),
+            ),
+            "i32" => (
+                "IntegerType::get(ctx, 32, Signedness::Signed)",
+                "is_i32",
+                format!(
+                    "{} member mask, value, and result must be 32-bit integers",
+                    record.dialect.op_name
+                ),
+            ),
+            "f32" => (
+                "FP32Type::get(ctx)",
+                "is_f32",
+                format!(
+                    "{} member mask must be a 32-bit integer and value and result must be f32",
+                    record.dialect.op_name
+                ),
+            ),
+            result => panic!("unsupported redux result {result}"),
+        };
+        writeln!(
+            output,
+            "    pub fn new(op: Ptr<Operation>) -> Self {{\n        Self {{ op }}\n    }}\n\n    pub fn build(ctx: &mut Context, member_mask: Value, value: Value) -> Ptr<Operation> {{\n        let result_ty = {result_type};\n        Operation::new(\n            ctx,\n            Self::get_concrete_op_info(),\n            vec![result_ty.into()],\n            vec![member_mask, value],\n            vec![],\n            0,\n        )\n    }}\n}}"
+        )
+        .unwrap();
+        writeln!(output, "\nimpl Verify for {} {{", record.dialect.op_type).unwrap();
+        writeln!(
+            output,
+            "    fn verify(&self, ctx: &Context) -> Result<(), Error> {{\n        let op = self.get_operation().deref(ctx);\n        if op.get_num_operands() != 2 || op.get_num_results() != 1 {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        if !is_i32(ctx, op.get_operand(0).get_type(ctx))\n            || !{value_predicate}(ctx, op.get_operand(1).get_type(ctx))\n            || !{value_predicate}(ctx, op.get_result(0).get_type(ctx))\n        {{\n            return verify_err!(op.loc(), {:?});\n        }}\n        Ok(())\n    }}\n}}\n",
+            format!(
+                "{} requires exactly two operands [member_mask, value] and one result",
+                record.dialect.op_name
+            ),
+            type_error,
+        )
+        .unwrap();
+    }
+    output.push_str("\npub(super) fn register(ctx: &mut Context) {\n");
+    for record in redux(catalog) {
+        writeln!(output, "    {}::register(ctx);", record.dialect.op_type).unwrap();
+    }
+    output.push_str("}\n");
+    output
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/families/misc.rs b/crates/cuda-intrinsics-gen/src/render/families/misc.rs
new file mode 100644
index 0000000000..c6abdaf74e
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/families/misc.rs
@@ -0,0 +1,198 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogFile, CatalogIntrinsic, ClcOperation, ClusterBarrierMode,
+    IntrinsicBackend, SpecialRegisterObservation, SpecialRegisterOutputConstraint,
+    SpecialRegisterPtxType, WgmmaControlMode,
+};
+use crate::render::families::{execution_controls, wgmma_controls};
+use std::fmt::Write as _;
+
+pub(in crate::render) fn cluster_barrier_attr(record: &CatalogIntrinsic) -> &'static str {
+    match record
+        .cluster_barrier
+        .as_ref()
+        .expect("cluster-barrier contract")
+        .mode
+    {
+        ClusterBarrierMode::Arrive => "ClusterBarrierModeAttr::Arrive",
+        ClusterBarrierMode::ArriveAligned => "ClusterBarrierModeAttr::ArriveAligned",
+        ClusterBarrierMode::ArriveRelaxed => "ClusterBarrierModeAttr::ArriveRelaxed",
+        ClusterBarrierMode::ArriveRelaxedAligned => "ClusterBarrierModeAttr::ArriveRelaxedAligned",
+        ClusterBarrierMode::Wait => "ClusterBarrierModeAttr::Wait",
+        ClusterBarrierMode::WaitAligned => "ClusterBarrierModeAttr::WaitAligned",
+    }
+}
+
+pub(in crate::render) fn cluster_barrier_template(record: &CatalogIntrinsic) -> String {
+    format!(
+        "{}.{};",
+        record.expected_ptx.mnemonic,
+        record.expected_ptx.modifiers.join(".")
+    )
+}
+
+#[derive(Clone, Copy)]
+pub(in crate::render) enum ClcSafetyArgNames {
+    RawAbi,
+    Compatibility,
+}
+
+fn clc_safety_lines(operation: ClcOperation, names: ClcSafetyArgNames) -> Vec<String> {
+    let (response, mbar, resp_lo, resp_hi) = match names {
+        ClcSafetyArgNames::RawAbi => ("`_arg0`", "`_arg1`", "`_arg0`", "`_arg1`"),
+        ClcSafetyArgNames::Compatibility => ("`response`", "`mbar`", "`resp_lo`", "`resp_hi`"),
+    };
+    match operation {
+        ClcOperation::TryCancel => vec![
+            format!(
+                "{response} must designate a writable, 16-byte-aligned 16-byte region in `shared::cta` memory, and {mbar} must designate a valid, aligned shared-memory mbarrier."
+            ),
+            format!(
+                "The calling CTA must issue `arrive_expect_tx` for {mbar} with 16 bytes before this request."
+            ),
+            "This CTA must not have observed a prior CLC try-cancel request fail.".into(),
+        ],
+        ClcOperation::TryCancelMulticast => vec![
+            format!(
+                "{response} must designate a writable, 16-byte-aligned 16-byte region in `shared::cta` memory, and {mbar} must designate a valid, aligned shared-memory mbarrier."
+            ),
+            format!(
+                "Each CTA must issue `arrive_expect_tx` for its own corresponding mbarrier with 16 bytes before this request."
+            ),
+            "This CTA must not have observed a prior CLC try-cancel request fail.".into(),
+            "The response is written to every CTA's shared-memory window and signals every CTA's mbarrier.".into(),
+            "Every CTA in the cluster must still be active.".into(),
+        ],
+        ClcOperation::QueryIsCanceled => vec![format!(
+            "{resp_lo} and {resp_hi} must be the two halves of an opaque response observed complete from a prior CLC try-cancel request."
+        )],
+        ClcOperation::QueryGetFirstCtaidX
+        | ClcOperation::QueryGetFirstCtaidY
+        | ClcOperation::QueryGetFirstCtaidZ => vec![
+            format!(
+                "{resp_lo} and {resp_hi} must be the two halves of an opaque response observed complete from a prior CLC try-cancel request."
+            ),
+            "The result is meaningful only when `clc_query_is_canceled` returned one for this response.".into(),
+        ],
+    }
+}
+
+pub(in crate::render) fn render_clc_safety_lines(
+    output: &mut String,
+    operation: ClcOperation,
+    names: ClcSafetyArgNames,
+) {
+    for line in clc_safety_lines(operation, names) {
+        writeln!(output, "/// {line}").unwrap();
+    }
+}
+
+pub(in crate::render) fn execution_control_family<'a>(
+    catalog: &'a CatalogFile,
+    family: &'a str,
+) -> impl Iterator<Item = &'a CatalogIntrinsic> {
+    execution_controls(catalog).filter(move |record| record.family == family)
+}
+
+pub(in crate::render) fn wgmma_control(
+    catalog: &CatalogFile,
+    mode: WgmmaControlMode,
+) -> &CatalogIntrinsic {
+    wgmma_controls(catalog)
+        .find(|record| {
+            record
+                .wgmma_control
+                .as_ref()
+                .is_some_and(|control| control.mode == mode)
+        })
+        .expect("complete WGMMA-control family")
+}
+
+pub(in crate::render) fn wgmma_control_template(record: &CatalogIntrinsic) -> String {
+    let operand = if record
+        .wgmma_control
+        .as_ref()
+        .is_some_and(|control| control.mode == WgmmaControlMode::WaitGroup)
+    {
+        " $0"
+    } else {
+        ""
+    };
+    format!(
+        "{}.{}{operand};",
+        record.expected_ptx.mnemonic,
+        record.expected_ptx.modifiers.join(".")
+    )
+}
+
+pub(in crate::render) fn threadfence_ptx_level(record: &CatalogIntrinsic) -> Option<&'static str> {
+    match record.id.as_str() {
+        "threadfence_block" => Some("cta"),
+        "threadfence" => Some("gl"),
+        "threadfence_system" => Some("sys"),
+        _ => None,
+    }
+}
+
+fn special_register_ptx_type(record: &CatalogIntrinsic) -> &'static str {
+    match record
+        .special_register
+        .as_ref()
+        .expect("special-register record")
+        .ptx_type
+    {
+        SpecialRegisterPtxType::B32 => "b32",
+        SpecialRegisterPtxType::U32 => "u32",
+        SpecialRegisterPtxType::U64 => "u64",
+    }
+}
+
+pub(in crate::render) fn special_register_output_constraint(
+    record: &CatalogIntrinsic,
+) -> &'static str {
+    match record
+        .special_register
+        .as_ref()
+        .expect("special-register record")
+        .output_constraint
+    {
+        SpecialRegisterOutputConstraint::Register32 => "=r",
+        SpecialRegisterOutputConstraint::Register64 => "=l",
+    }
+}
+
+pub(in crate::render) fn special_register_inline_template(record: &CatalogIntrinsic) -> String {
+    let register = match record.expected_ptx.operands.as_slice() {
+        [_, crate::ptx::OperandPattern::Exact { value }] => value,
+        _ => unreachable!("closed special-register PTX operands"),
+    };
+    format!("mov.{} $0, {register};", special_register_ptx_type(record))
+}
+
+pub(in crate::render) fn special_register_asm_kind(record: &CatalogIntrinsic) -> &'static str {
+    match record
+        .special_register
+        .as_ref()
+        .expect("special-register record")
+        .observation
+    {
+        SpecialRegisterObservation::StablePure => "AsmKind::Pure",
+        SpecialRegisterObservation::VolatileObservation => "AsmKind::SideEffect",
+    }
+}
+
+pub(in crate::render) fn special_register_backend_mechanism(
+    record: &CatalogIntrinsic,
+    backend: IntrinsicBackend,
+) -> BackendLoweringMechanism {
+    record
+        .backend_lowerings
+        .iter()
+        .find(|route| route.backend == backend)
+        .expect("special-register backend route")
+        .mechanism
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/families/mma.rs b/crates/cuda-intrinsics-gen/src/render/families/mma.rs
new file mode 100644
index 0000000000..42aebc76c0
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/families/mma.rs
@@ -0,0 +1,566 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    CatalogIntrinsic, LdmatrixElement, LdmatrixLayout, LdmatrixMultiplicity, LdmatrixShape,
+    LdmatrixStateSpace, RegisterMmaAccumulator, RegisterMmaAdapter, RegisterMmaElement,
+    RegisterMmaKind, RegisterMmaLayout, RegisterMmaOperation, RegisterMmaOverflow,
+    RegisterMmaShape, SparseMma, SparseMmaAccumulator, SparseMmaAdapter, SparseMmaElement,
+    SparseMmaLayout, SparseMmaMetadata, SparseMmaOverflow, SparseMmaSelector, SparseMmaShape,
+    StmatrixLayout, StmatrixMultiplicity,
+};
+use std::fmt::Write as _;
+
+pub(in crate::render) fn is_blackwell_ldmatrix(record: &CatalogIntrinsic) -> bool {
+    record
+        .ldmatrix
+        .as_ref()
+        .is_some_and(|ldmatrix| ldmatrix.variant.shape != LdmatrixShape::M8n8)
+}
+
+pub(in crate::render) const BLACKWELL_LDMATRIX_EFFECTIVE_FLOORS: &str = "sm_100a PTX 8.6, sm_100f PTX 8.8, sm_103a PTX 8.8, sm_103f PTX 8.8, sm_110a PTX 9.0, sm_110f PTX 9.0, sm_120a PTX 8.7, sm_120f PTX 8.8, sm_121a PTX 8.8, sm_121f PTX 8.8";
+
+pub(in crate::render) fn ldmatrix_compat_op(
+    record: &CatalogIntrinsic,
+) -> Option<(&'static str, &'static str)> {
+    match record.id.as_str() {
+        "ldmatrix_m8n8_x1_b16" => Some(("LdmatrixX1Op", "nvvm.ldmatrix_x1")),
+        "ldmatrix_m8n8_x1_trans_b16" => Some(("LdmatrixX1TransOp", "nvvm.ldmatrix_x1_trans")),
+        "ldmatrix_m8n8_x2_b16" => Some(("LdmatrixX2Op", "nvvm.ldmatrix_x2")),
+        "ldmatrix_m8n8_x2_trans_b16" => Some(("LdmatrixX2TransOp", "nvvm.ldmatrix_x2_trans")),
+        "ldmatrix_m8n8_x4_b16" => Some(("LdmatrixX4Op", "nvvm.ldmatrix_x4")),
+        "ldmatrix_m8n8_x4_trans_b16" => Some(("LdmatrixX4TransOp", "nvvm.ldmatrix_x4_trans")),
+        _ => None,
+    }
+}
+
+pub(in crate::render) fn stmatrix_variant(
+    record: &CatalogIntrinsic,
+) -> Option<(StmatrixMultiplicity, StmatrixLayout)> {
+    match record.id.as_str() {
+        "stmatrix_m8n8_x2_b16" => Some((StmatrixMultiplicity::X2, StmatrixLayout::Normal)),
+        "stmatrix_m8n8_x2_trans_b16" => {
+            Some((StmatrixMultiplicity::X2, StmatrixLayout::Transposed))
+        }
+        "stmatrix_m8n8_x4_b16" => Some((StmatrixMultiplicity::X4, StmatrixLayout::Normal)),
+        "stmatrix_m8n8_x4_trans_b16" => {
+            Some((StmatrixMultiplicity::X4, StmatrixLayout::Transposed))
+        }
+        _ => None,
+    }
+}
+
+pub(in crate::render) fn stmatrix_compatibility_name(record: &CatalogIntrinsic) -> &'static str {
+    match record.id.as_str() {
+        "stmatrix_m8n8_x2_b16" => "stmatrix_m8n8_x2",
+        "stmatrix_m8n8_x2_trans_b16" => "stmatrix_m8n8_x2_trans",
+        "stmatrix_m8n8_x4_b16" => "stmatrix_m8n8_x4",
+        "stmatrix_m8n8_x4_trans_b16" => "stmatrix_m8n8_x4_trans",
+        _ => panic!("unknown stmatrix record {}", record.id),
+    }
+}
+
+pub(in crate::render) fn movmatrix_template(record: &CatalogIntrinsic) -> String {
+    format!(
+        "{}.{} $0, $1;",
+        record.expected_ptx.mnemonic,
+        record.expected_ptx.modifiers.join(".")
+    )
+}
+
+pub(in crate::render) fn ldmatrix_attr_variants(
+    record: &CatalogIntrinsic,
+) -> (
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+) {
+    let variant = &record.ldmatrix.as_ref().expect("ldmatrix record").variant;
+    let shape = match variant.shape {
+        LdmatrixShape::M8n8 => "LdmatrixShapeAttr::M8n8",
+        LdmatrixShape::M8n16 => "LdmatrixShapeAttr::M8n16",
+        LdmatrixShape::M16n16 => "LdmatrixShapeAttr::M16n16",
+    };
+    let multiplicity = match variant.multiplicity {
+        LdmatrixMultiplicity::X1 => "LdmatrixMultiplicityAttr::X1",
+        LdmatrixMultiplicity::X2 => "LdmatrixMultiplicityAttr::X2",
+        LdmatrixMultiplicity::X4 => "LdmatrixMultiplicityAttr::X4",
+    };
+    let layout = match variant.layout {
+        LdmatrixLayout::Normal => "LdmatrixLayoutAttr::Normal",
+        LdmatrixLayout::Transposed => "LdmatrixLayoutAttr::Transposed",
+    };
+    let element = match variant.element {
+        LdmatrixElement::B16 => "LdmatrixElementAttr::B16",
+        LdmatrixElement::B8 => "LdmatrixElementAttr::B8",
+        LdmatrixElement::B8x16B4x16P64 => "LdmatrixElementAttr::B8x16B4x16P64",
+        LdmatrixElement::B8x16B6x16P32 => "LdmatrixElementAttr::B8x16B6x16P32",
+    };
+    let state_space = match variant.state_space {
+        LdmatrixStateSpace::Shared => "LdmatrixStateSpaceAttr::Shared",
+    };
+    (shape, multiplicity, layout, element, state_space)
+}
+
+pub(in crate::render) fn register_mma_effective_kind(record: &CatalogIntrinsic) -> RegisterMmaKind {
+    let mma = record.register_mma.as_ref().expect("register-MMA record");
+    mma.kind.unwrap_or_else(|| {
+        if record
+            .llvm
+            .as_ref()
+            .is_some_and(|llvm| llvm.symbol.contains(".kind.f8f6f4."))
+        {
+            RegisterMmaKind::F8f6f4
+        } else {
+            RegisterMmaKind::Standard
+        }
+    })
+}
+
+pub(in crate::render) fn register_mma_attr_variants(
+    record: &CatalogIntrinsic,
+) -> (
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+) {
+    let mma = record.register_mma.as_ref().expect("register-MMA record");
+    let shape = match mma.shape {
+        RegisterMmaShape::M8n8k4 => "RegisterMmaShapeAttr::M8n8k4",
+        RegisterMmaShape::M8n8k16 => "RegisterMmaShapeAttr::M8n8k16",
+        RegisterMmaShape::M8n8k32 => "RegisterMmaShapeAttr::M8n8k32",
+        RegisterMmaShape::M8n8k128 => "RegisterMmaShapeAttr::M8n8k128",
+        RegisterMmaShape::M16n8k4 => "RegisterMmaShapeAttr::M16n8k4",
+        RegisterMmaShape::M16n8k8 => "RegisterMmaShapeAttr::M16n8k8",
+        RegisterMmaShape::M16n8k16 => "RegisterMmaShapeAttr::M16n8k16",
+        RegisterMmaShape::M16n8k32 => "RegisterMmaShapeAttr::M16n8k32",
+        RegisterMmaShape::M16n8k64 => "RegisterMmaShapeAttr::M16n8k64",
+        RegisterMmaShape::M16n8k128 => "RegisterMmaShapeAttr::M16n8k128",
+        RegisterMmaShape::M16n8k256 => "RegisterMmaShapeAttr::M16n8k256",
+    };
+    let operation = match mma.operation {
+        RegisterMmaOperation::Multiply => "RegisterMmaOperationAttr::Multiply",
+        RegisterMmaOperation::AndPopc => "RegisterMmaOperationAttr::AndPopc",
+        RegisterMmaOperation::XorPopc => "RegisterMmaOperationAttr::XorPopc",
+    };
+    let kind = match register_mma_effective_kind(record) {
+        RegisterMmaKind::Standard => "RegisterMmaKindAttr::Standard",
+        RegisterMmaKind::F8f6f4 => "RegisterMmaKindAttr::F8f6f4",
+        RegisterMmaKind::Mxf8f6f4 => "RegisterMmaKindAttr::Mxf8f6f4",
+    };
+    let accumulator = match mma.accumulator {
+        RegisterMmaAccumulator::F16 => "RegisterMmaAccumulatorAttr::F16",
+        RegisterMmaAccumulator::F32 => "RegisterMmaAccumulatorAttr::F32",
+        RegisterMmaAccumulator::F64 => "RegisterMmaAccumulatorAttr::F64",
+        RegisterMmaAccumulator::S32 => "RegisterMmaAccumulatorAttr::S32",
+    };
+    let element = |element| match element {
+        RegisterMmaElement::Bf16 => "RegisterMmaElementAttr::Bf16",
+        RegisterMmaElement::E2m1 => "RegisterMmaElementAttr::E2m1",
+        RegisterMmaElement::E2m3 => "RegisterMmaElementAttr::E2m3",
+        RegisterMmaElement::E3m2 => "RegisterMmaElementAttr::E3m2",
+        RegisterMmaElement::E4m3 => "RegisterMmaElementAttr::E4m3",
+        RegisterMmaElement::E5m2 => "RegisterMmaElementAttr::E5m2",
+        RegisterMmaElement::F16 => "RegisterMmaElementAttr::F16",
+        RegisterMmaElement::Tf32 => "RegisterMmaElementAttr::Tf32",
+        RegisterMmaElement::F64 => "RegisterMmaElementAttr::F64",
+        RegisterMmaElement::B1 => "RegisterMmaElementAttr::B1",
+        RegisterMmaElement::S4 => "RegisterMmaElementAttr::S4",
+        RegisterMmaElement::U4 => "RegisterMmaElementAttr::U4",
+        RegisterMmaElement::S8 => "RegisterMmaElementAttr::S8",
+        RegisterMmaElement::U8 => "RegisterMmaElementAttr::U8",
+    };
+    let layout = |layout| match layout {
+        RegisterMmaLayout::Row => "RegisterMmaLayoutAttr::Row",
+        RegisterMmaLayout::Col => "RegisterMmaLayoutAttr::Col",
+    };
+    let overflow = match mma.overflow {
+        RegisterMmaOverflow::NotApplicable => "RegisterMmaOverflowAttr::NotApplicable",
+        RegisterMmaOverflow::Wrapping => "RegisterMmaOverflowAttr::Wrapping",
+        RegisterMmaOverflow::Satfinite => "RegisterMmaOverflowAttr::Satfinite",
+    };
+    (
+        shape,
+        operation,
+        kind,
+        accumulator,
+        element(mma.a_element),
+        element(mma.b_element),
+        layout(mma.a_layout),
+        layout(mma.b_layout),
+        overflow,
+    )
+}
+
+pub(in crate::render) fn register_mma_fragment_counts(
+    record: &CatalogIntrinsic,
+) -> (usize, usize, usize, usize) {
+    match record.register_mma.as_ref().unwrap().adapter {
+        RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32 => (2, 2, 1, 2),
+        RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => (2, 4, 2, 2),
+        RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32 => (4, 2, 1, 4),
+        RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32 | RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32 => {
+            (4, 4, 2, 4)
+        }
+        RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => (4, 4, 2, 4),
+        RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 | RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32 => {
+            (2, 1, 1, 2)
+        }
+        RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => (4, 2, 1, 4),
+    }
+}
+
+pub(in crate::render) fn register_mma_extra_operand_count(record: &CatalogIntrinsic) -> usize {
+    usize::from(
+        record.register_mma.as_ref().unwrap().adapter
+            == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+    ) * 6
+}
+
+pub(in crate::render) fn expected_ptx_head(record: &CatalogIntrinsic) -> String {
+    let mut head = record.expected_ptx.mnemonic.clone();
+    for modifier in &record.expected_ptx.modifiers {
+        write!(head, ".{modifier}").unwrap();
+    }
+    head
+}
+
+fn register_list(first: usize, count: usize) -> String {
+    format!(
+        "{{{}}}",
+        (first..first + count)
+            .map(|index| format!("${index}"))
+            .collect::<Vec<_>>()
+            .join(", ")
+    )
+}
+
+pub(in crate::render) fn register_mma_template(record: &CatalogIntrinsic) -> String {
+    let (c_count, a_count, b_count, d_count) = register_mma_fragment_counts(record);
+    let d = register_list(0, d_count);
+    let c = register_list(d_count, c_count);
+    let a = register_list(d_count + c_count, a_count);
+    let b = register_list(d_count + c_count + a_count, b_count);
+    if record.register_mma.as_ref().unwrap().adapter
+        == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
+    {
+        let scale_a = d_count + c_count + a_count + b_count;
+        let byte_id_a = scale_a + 1;
+        let thread_id_a = scale_a + 2;
+        let scale_b = scale_a + 3;
+        let byte_id_b = scale_a + 4;
+        let thread_id_b = scale_a + 5;
+        format!(
+            "{} {d}, {a}, {b}, {c}, ${scale_a}, {{${byte_id_a}, ${thread_id_a}}}, ${scale_b}, {{${byte_id_b}, ${thread_id_b}}};",
+            expected_ptx_head(record)
+        )
+    } else {
+        format!("{} {d}, {a}, {b}, {c};", expected_ptx_head(record))
+    }
+}
+
+pub(in crate::render) fn register_mma_constraints(record: &CatalogIntrinsic) -> String {
+    let mma = record.register_mma.as_ref().unwrap();
+    let (c_count, a_count, b_count, d_count) = register_mma_fragment_counts(record);
+    let (output, c, packed) = match mma.adapter {
+        RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32 | RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => {
+            ("=r", "r", "r")
+        }
+        RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
+        | RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32
+        | RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => ("=f", "f", "r"),
+        RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 => ("=d", "d", "d"),
+        RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32
+        | RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32
+        | RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => ("=r", "r", "r"),
+    };
+    let mut constraints = std::iter::repeat_n(output, d_count)
+        .chain(std::iter::repeat_n(c, c_count))
+        .chain(std::iter::repeat_n(packed, a_count + b_count))
+        .collect::<Vec<_>>();
+    if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 {
+        constraints.extend(["r", "h", "h", "r", "h", "h"]);
+    }
+    constraints.join(",")
+}
+
+pub(in crate::render) fn register_mma_result_variant(record: &CatalogIntrinsic) -> &'static str {
+    match record.register_mma.as_ref().unwrap().adapter {
+        RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32 | RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => {
+            "GeneratedMmaResultType::I32"
+        }
+        RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32 | RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32 => {
+            "GeneratedMmaResultType::F32"
+        }
+        RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => {
+            "GeneratedMmaResultType::F32"
+        }
+        RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 => "GeneratedMmaResultType::F64",
+        RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32
+        | RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32
+        | RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => "GeneratedMmaResultType::I32",
+    }
+}
+
+pub(in crate::render) fn sparse_mma_fragment_counts(
+    record: &CatalogIntrinsic,
+) -> (usize, usize, usize, usize) {
+    match record.sparse_mma.as_ref().unwrap().adapter {
+        SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 => (2, 4, 4, 2),
+        SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32
+        | SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32 => (4, 4, 4, 4),
+        SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32 => (4, 2, 2, 4),
+    }
+}
+
+pub(in crate::render) fn sparse_mma_selector_values(record: &CatalogIntrinsic) -> &'static [u32] {
+    match record.sparse_mma.as_ref().unwrap().selector {
+        SparseMmaSelector::ImmediateZeroOrOne => &[0, 1],
+        SparseMmaSelector::ImmediateZero => &[0],
+    }
+}
+
+pub(in crate::render) fn sparse_mma_selector_description(
+    record: &CatalogIntrinsic,
+) -> &'static str {
+    match record.sparse_mma.as_ref().unwrap().selector {
+        SparseMmaSelector::ImmediateZeroOrOne => "the compile-time constant `0` or `1`",
+        SparseMmaSelector::ImmediateZero => "the compile-time constant `0`",
+    }
+}
+
+pub(in crate::render) fn sparse_mma_selector_error(record: &CatalogIntrinsic) -> &'static str {
+    match record.sparse_mma.as_ref().unwrap().selector {
+        SparseMmaSelector::ImmediateZeroOrOne => {
+            "sparse MMA selector must be the compile-time constant 0 or 1"
+        }
+        SparseMmaSelector::ImmediateZero => {
+            "sparse MMA selector must be the compile-time constant 0"
+        }
+    }
+}
+
+pub(in crate::render) const SPARSE_MMA_STANDARD_METADATA_RULE: &str = "Every 4-bit metadata group must encode two distinct 2-bit indices; `0x0`, `0x5`, `0xa`, and `0xf` are undefined behavior.";
+pub(in crate::render) const SPARSE_MMA_ORDERED_METADATA_RULE: &str = "Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior.";
+
+pub(in crate::render) fn sparse_mma_metadata_rule(mma: &SparseMma) -> &'static str {
+    match mma.metadata {
+        SparseMmaMetadata::Standard => SPARSE_MMA_STANDARD_METADATA_RULE,
+        SparseMmaMetadata::Ordered => SPARSE_MMA_ORDERED_METADATA_RULE,
+    }
+}
+
+pub(in crate::render) fn sparse_mma_import_adapter(record: &CatalogIntrinsic) -> &'static str {
+    match record.sparse_mma.as_ref().unwrap().adapter {
+        SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 => {
+            "GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32"
+        }
+        SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32 => {
+            "GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32"
+        }
+        SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32 => {
+            "GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32"
+        }
+        SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32 => {
+            "GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32"
+        }
+    }
+}
+
+pub(in crate::render) fn sparse_mma_attr_variants(
+    record: &CatalogIntrinsic,
+) -> (
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+    &'static str,
+) {
+    let mma = record.sparse_mma.as_ref().expect("sparse-MMA record");
+    let shape = match mma.shape {
+        SparseMmaShape::M16n8k32 => "SparseMmaShapeAttr::M16n8k32",
+        SparseMmaShape::M16n8k64 => "SparseMmaShapeAttr::M16n8k64",
+        SparseMmaShape::M16n8k128 => "SparseMmaShapeAttr::M16n8k128",
+    };
+    let accumulator = match mma.accumulator {
+        SparseMmaAccumulator::F16 => "SparseMmaAccumulatorAttr::F16",
+        SparseMmaAccumulator::F32 => "SparseMmaAccumulatorAttr::F32",
+        SparseMmaAccumulator::S32 => "SparseMmaAccumulatorAttr::S32",
+    };
+    let element = |element| match element {
+        SparseMmaElement::E2m1 => "SparseMmaElementAttr::E2m1",
+        SparseMmaElement::E2m3 => "SparseMmaElementAttr::E2m3",
+        SparseMmaElement::E3m2 => "SparseMmaElementAttr::E3m2",
+        SparseMmaElement::E4m3 => "SparseMmaElementAttr::E4m3",
+        SparseMmaElement::E5m2 => "SparseMmaElementAttr::E5m2",
+        SparseMmaElement::S4 => "SparseMmaElementAttr::S4",
+        SparseMmaElement::U4 => "SparseMmaElementAttr::U4",
+        SparseMmaElement::S8 => "SparseMmaElementAttr::S8",
+        SparseMmaElement::U8 => "SparseMmaElementAttr::U8",
+    };
+    let layout = |layout| match layout {
+        SparseMmaLayout::Row => "SparseMmaLayoutAttr::Row",
+        SparseMmaLayout::Col => "SparseMmaLayoutAttr::Col",
+    };
+    let overflow = match mma.overflow {
+        SparseMmaOverflow::NotApplicable => "SparseMmaOverflowAttr::NotApplicable",
+        SparseMmaOverflow::Wrapping => "SparseMmaOverflowAttr::Wrapping",
+        SparseMmaOverflow::Satfinite => "SparseMmaOverflowAttr::Satfinite",
+    };
+    let metadata = match mma.metadata {
+        SparseMmaMetadata::Standard => "SparseMmaMetadataAttr::Standard",
+        SparseMmaMetadata::Ordered => "SparseMmaMetadataAttr::Ordered",
+    };
+    let selector = match mma.selector {
+        SparseMmaSelector::ImmediateZeroOrOne => "SparseMmaSelectorAttr::ImmediateZeroOrOne",
+        SparseMmaSelector::ImmediateZero => "SparseMmaSelectorAttr::ImmediateZero",
+    };
+    (
+        shape,
+        accumulator,
+        element(mma.a_element),
+        element(mma.b_element),
+        layout(mma.a_layout),
+        layout(mma.b_layout),
+        overflow,
+        metadata,
+        selector,
+    )
+}
+
+pub(in crate::render) fn sparse_mma_ptx_head(record: &CatalogIntrinsic) -> String {
+    let mut head = record.expected_ptx.mnemonic.clone();
+    for modifier in &record.expected_ptx.modifiers {
+        write!(head, ".{modifier}").unwrap();
+    }
+    head
+}
+
+pub(in crate::render) fn sparse_mma_template(record: &CatalogIntrinsic) -> String {
+    let (c_count, a_count, b_count, d_count) = sparse_mma_fragment_counts(record);
+    let d = register_list(0, d_count);
+    let c = register_list(d_count, c_count);
+    let a = register_list(d_count + c_count, a_count);
+    let b = register_list(d_count + c_count + a_count, b_count);
+    let metadata = d_count + c_count + a_count + b_count;
+    let selector = metadata + 1;
+    format!(
+        "{} {d}, {a}, {b}, {c}, ${metadata}, ${selector};",
+        sparse_mma_ptx_head(record)
+    )
+}
+
+pub(in crate::render) fn sparse_mma_constraints(record: &CatalogIntrinsic) -> String {
+    let mma = record.sparse_mma.as_ref().unwrap();
+    let (c_count, a_count, b_count, d_count) = sparse_mma_fragment_counts(record);
+    let (output, accumulator) = match mma.accumulator {
+        SparseMmaAccumulator::F16 => ("=r", "r"),
+        SparseMmaAccumulator::F32 => ("=f", "f"),
+        SparseMmaAccumulator::S32 => ("=r", "r"),
+    };
+    std::iter::repeat_n(output, d_count)
+        .chain(std::iter::repeat_n(accumulator, c_count))
+        .chain(std::iter::repeat_n("r", a_count + b_count + 1))
+        .chain(std::iter::once("n"))
+        .collect::<Vec<_>>()
+        .join(",")
+}
+
+pub(in crate::render) fn sparse_mma_result_variant(record: &CatalogIntrinsic) -> &'static str {
+    match record.sparse_mma.as_ref().unwrap().accumulator {
+        SparseMmaAccumulator::F16 => "GeneratedMmaResultType::I32",
+        SparseMmaAccumulator::F32 => "GeneratedMmaResultType::F32",
+        SparseMmaAccumulator::S32 => "GeneratedMmaResultType::I32",
+    }
+}
+
+pub(in crate::render) fn sparse_mma_carriers(record: &CatalogIntrinsic) -> (String, String) {
+    let mma = record.sparse_mma.as_ref().unwrap();
+    let (c_count, a_count, b_count, d_count) = sparse_mma_fragment_counts(record);
+    let accumulator = match mma.accumulator {
+        SparseMmaAccumulator::F16 => "MmaCarrier::U32",
+        SparseMmaAccumulator::F32 => "MmaCarrier::F32",
+        SparseMmaAccumulator::S32 => "MmaCarrier::I32",
+    };
+    let carrier_slice = |carriers: Vec<&str>| format!("&[{}]", carriers.join(", "));
+    let operands = carrier_slice(
+        std::iter::repeat_n(accumulator, c_count)
+            .chain(std::iter::repeat_n(
+                "MmaCarrier::U32",
+                a_count + b_count + 2,
+            ))
+            .collect(),
+    );
+    let results = carrier_slice(std::iter::repeat_n(accumulator, d_count).collect());
+    (operands, results)
+}
+
+pub(in crate::render) fn register_mma_carriers(
+    record: &CatalogIntrinsic,
+) -> (&'static str, &'static str) {
+    match record.register_mma.as_ref().unwrap().adapter {
+        RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32 => (
+            "&[MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
+            "&[MmaCarrier::U32, MmaCarrier::U32]",
+        ),
+        RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => (
+            "&[MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
+            "&[MmaCarrier::U32, MmaCarrier::U32]",
+        ),
+        RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32 => (
+            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
+            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32]",
+        ),
+        RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32 => (
+            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
+            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32]",
+        ),
+        RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => (
+            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U16, MmaCarrier::U16, MmaCarrier::U32, MmaCarrier::U16, MmaCarrier::U16]",
+            "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32]",
+        ),
+        RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 => (
+            "&[MmaCarrier::F64, MmaCarrier::F64, MmaCarrier::F64, MmaCarrier::F64]",
+            "&[MmaCarrier::F64, MmaCarrier::F64]",
+        ),
+        RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32 => (
+            "&[MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::U32, MmaCarrier::U32]",
+            "&[MmaCarrier::I32, MmaCarrier::I32]",
+        ),
+        RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32 => (
+            "&[MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
+            "&[MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32]",
+        ),
+        RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => (
+            "&[MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]",
+            "&[MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32, MmaCarrier::I32]",
+        ),
+    }
+}
+
+pub(in crate::render) fn register_mma_compat_op_type(
+    record: &CatalogIntrinsic,
+) -> Option<&'static str> {
+    match record.id.as_str() {
+        "mma_m16n8k16_f32_bf16" => Some("MmaM16N8K16F32Bf16Op"),
+        "mma_m16n8k16_f32_f16" => Some("MmaM16N8K16F32F16Op"),
+        "mma_m16n8k8_f32_tf32" => Some("MmaM16N8K8F32Tf32Op"),
+        "mma_m16n8k32_s32_s8" => Some("MmaM16N8K32S32S8Op"),
+        "mma_m8n8k4_f64" => Some("MmaM8N8K4F64Op"),
+        _ => None,
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/families/mod.rs b/crates/cuda-intrinsics-gen/src/render/families/mod.rs
new file mode 100644
index 0000000000..590e601e7c
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/families/mod.rs
@@ -0,0 +1,398 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{CatalogFile, CatalogIntrinsic};
+use std::collections::BTreeSet;
+
+mod misc;
+mod mma;
+mod packed;
+mod scalar;
+mod tcgen05;
+
+pub(super) use misc::*;
+pub(super) use mma::*;
+pub(super) use packed::*;
+pub(super) use scalar::*;
+pub(super) use tcgen05::*;
+
+pub(super) fn sregs(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "sreg")
+}
+
+pub(super) fn ldmatrix(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "ldmatrix")
+}
+
+pub(super) fn stmatrices(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "stmatrix")
+}
+
+pub(super) fn register_mmas(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "register_mma")
+}
+
+pub(super) fn sparse_mmas(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "sparse_mma")
+}
+
+pub(super) fn packed_atomics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "packed_atomic")
+}
+
+pub(super) fn redux(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "redux")
+}
+
+pub(super) fn dot_products(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "dotprod")
+}
+
+pub(super) fn packed_alus(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "packed_alu")
+}
+
+pub(super) fn packed_conversions(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "packed_conversion")
+}
+
+pub(super) fn scalar_conversions(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "scalar_conversion")
+}
+
+pub(super) fn scalar_arithmetics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "scalar_arithmetic")
+}
+
+pub(super) fn extended_minmax(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "extended_minmax")
+}
+
+pub(super) fn scalar_maths(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "scalar_math")
+}
+
+pub(super) fn prmts(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "prmt")
+}
+
+pub(super) fn cluster_barriers(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "cluster_barrier")
+}
+
+pub(super) fn debug_controls(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "debug_control")
+}
+
+pub(super) fn cluster_memory(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "cluster_memory")
+}
+
+pub(super) fn clc_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "clc")
+}
+
+pub(super) fn tma_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "tma")
+}
+
+pub(super) fn execution_controls(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog.intrinsics.iter().filter(|record| {
+        matches!(
+            record.family.as_str(),
+            "counted_barrier" | "grid_dependency" | "register_control"
+        )
+    })
+}
+
+pub(super) fn wgmma_controls(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "wgmma_control")
+}
+
+pub(super) fn tcgen05_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "tcgen05")
+}
+
+pub(super) fn tcgen05_mma_intrinsics(
+    catalog: &CatalogFile,
+) -> impl Iterator<Item = &CatalogIntrinsic> {
+    tcgen05_intrinsics(catalog).filter(|record| {
+        record
+            .tcgen05
+            .as_ref()
+            .is_some_and(|tcgen05| tcgen05.mma.is_some())
+    })
+}
+
+pub(super) fn tcgen05_non_mma_intrinsics(
+    catalog: &CatalogFile,
+) -> impl Iterator<Item = &CatalogIntrinsic> {
+    tcgen05_intrinsics(catalog).filter(|record| {
+        record
+            .tcgen05
+            .as_ref()
+            .is_some_and(|tcgen05| tcgen05.mma.is_none())
+    })
+}
+
+pub(super) fn cp_async_copies(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "cp_async_copy")
+}
+
+pub(super) fn cp_async_controls(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "cp_async_control")
+}
+
+pub(super) fn cp_async_mbarriers(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "cp_async_mbarrier")
+}
+
+pub(super) fn mbarrier_basics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "mbarrier_basic")
+}
+
+pub(super) fn movmatrix(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "movmatrix")
+}
+
+pub(super) fn mbarrier_extended(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "mbarrier_extended")
+}
+
+pub(super) fn sync_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "sync")
+}
+
+pub(super) fn vote_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "vote")
+}
+
+pub(super) fn active_masks(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "active_mask")
+}
+
+pub(super) fn elect_intrinsics(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "elect")
+}
+
+pub(super) fn warp_matches(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "warp_match")
+}
+
+pub(super) fn warp_barriers(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "warp_barrier")
+}
+
+pub(super) fn warp_shuffles(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "warp_shuffle")
+}
+
+pub(super) fn integer_minmaxes(catalog: &CatalogFile) -> impl Iterator<Item = &CatalogIntrinsic> {
+    catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "integer_minmax")
+}
+
+/// Everything a sharded generated output may import from `dialect_nvvm::ops`:
+/// each record's op type, the compatibility op types, and the attribute types
+/// the renderers spell out inline. Shard emitters filter this list against the
+/// shard body so each generated file imports exactly what it uses.
+pub(super) fn dialect_nvvm_ops_import_candidates(catalog: &CatalogFile) -> Vec<String> {
+    let mut candidates: BTreeSet<String> = [
+        "BreakpointOp",
+        "ClusterBarrierModeAttr",
+        "ClusterBarrierOp",
+        "ClusterSyncOp",
+        "ExtendedMinMaxFormatAttr",
+        "ExtendedMinMaxNanAttr",
+        "ExtendedMinMaxOp",
+        "ExtendedMinMaxOperationAttr",
+        "ExtendedMinMaxSubnormalAttr",
+        "ExtendedMinMaxXorSignAbsAttr",
+        "LdmatrixElementAttr",
+        "LdmatrixLayoutAttr",
+        "LdmatrixMultiplicityAttr",
+        "LdmatrixOp",
+        "LdmatrixShapeAttr",
+        "LdmatrixStateSpaceAttr",
+        "NvvmAtomAddBf16x2Op",
+        "NvvmAtomAddF16x2Op",
+        "PackedAtomicAddOp",
+        "PackedAtomicAtomicityAttr",
+        "PackedAtomicFormatAttr",
+        "PackedAtomicOrderingAttr",
+        "PackedAtomicRoundingAttr",
+        "PackedAtomicScopeAttr",
+        "PackedAtomicStateSpaceAttr",
+        "PackedAtomicSubnormalAttr",
+        "PmEventOp",
+        "PrmtModeAttr",
+        "PrmtOp",
+        "RegisterMmaAccumulatorAttr",
+        "RegisterMmaElementAttr",
+        "RegisterMmaKindAttr",
+        "RegisterMmaLayoutAttr",
+        "RegisterMmaOp",
+        "RegisterMmaOperationAttr",
+        "RegisterMmaOverflowAttr",
+        "RegisterMmaShapeAttr",
+        "ScalarArithmeticFormatAttr",
+        "ScalarArithmeticOp",
+        "ScalarArithmeticOperationAttr",
+        "ScalarArithmeticRoundingAttr",
+        "ScalarArithmeticSaturationAttr",
+        "ScalarArithmeticSubnormalAttr",
+        "ScalarConversionOp",
+        "ScalarConversionRoundingAttr",
+        "ScalarConversionSaturationAttr",
+        "ScalarMathFormatAttr",
+        "ScalarMathOp",
+        "ScalarMathOperationAttr",
+        "ScalarMathPrecisionAttr",
+        "ScalarMathSubnormalAttr",
+        "SparseMmaAccumulatorAttr",
+        "SparseMmaElementAttr",
+        "SparseMmaLayoutAttr",
+        "SparseMmaMetadataAttr",
+        "SparseMmaOp",
+        "SparseMmaOverflowAttr",
+        "SparseMmaSelectorAttr",
+        "SparseMmaShapeAttr",
+        "Tcgen05MmaBBufferAttr",
+        "Tcgen05MmaBUsageAttr",
+        "Tcgen05MmaCollectorAAttr",
+        "Tcgen05MmaCtaGroupAttr",
+        "Tcgen05MmaFormAttr",
+        "Tcgen05MmaKindAttr",
+        "Tcgen05MmaOp",
+        "TrapOp",
+        "WgmmaCommitGroupSyncAlignedOp",
+        "WgmmaFenceSyncAlignedOp",
+        "WgmmaWaitGroupSyncAlignedOp",
+    ]
+    .into_iter()
+    .map(str::to_owned)
+    .collect();
+    for record in &catalog.intrinsics {
+        candidates.insert(record.dialect.op_type.clone());
+    }
+    for record in ldmatrix(catalog) {
+        if let Some((op_type, _)) = ldmatrix_compat_op(record) {
+            candidates.insert(op_type.to_owned());
+        }
+    }
+    for record in register_mmas(catalog) {
+        if let Some(op_type) = register_mma_compat_op_type(record) {
+            candidates.insert(op_type.to_owned());
+        }
+    }
+    candidates.into_iter().collect()
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/families/packed.rs b/crates/cuda-intrinsics-gen/src/render/families/packed.rs
new file mode 100644
index 0000000000..6815833d5a
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/families/packed.rs
@@ -0,0 +1,449 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogIntrinsic, DotProductAdapter, DotProductOperation,
+    DotProductSignedness, IntrinsicBackend, PackedAluAdapter, PackedAluFormat, PackedAluOperation,
+    PackedConversionAdapter, PackedConversionDestinationFormat, PackedConversionRounding,
+    PackedConversionSaturation, PackedConversionSourceFormat,
+};
+
+pub(in crate::render) fn packed_alu_format_shape(
+    format: PackedAluFormat,
+) -> (
+    &'static str,
+    bool,
+    &'static str,
+    &'static str,
+    PackedAluAdapter,
+) {
+    match format {
+        PackedAluFormat::Bf16x2 => (
+            "bf16x2",
+            false,
+            "u32",
+            "i32",
+            PackedAluAdapter::DirectPackedU32,
+        ),
+        PackedAluFormat::F16x2 => (
+            "f16x2",
+            true,
+            "u32",
+            "i32",
+            PackedAluAdapter::DirectPackedU32,
+        ),
+        PackedAluFormat::F32x2 => (
+            "f32x2",
+            true,
+            "u64",
+            "i64",
+            PackedAluAdapter::DirectPackedU64,
+        ),
+    }
+}
+
+pub(in crate::render) fn packed_alu_width(record: &CatalogIntrinsic) -> u32 {
+    match record
+        .packed_alu
+        .as_ref()
+        .expect("packed-ALU record")
+        .adapter
+    {
+        PackedAluAdapter::DirectPackedU32 => 32,
+        PackedAluAdapter::DirectPackedU64 => 64,
+    }
+}
+
+pub(in crate::render) fn packed_alu_register_constraint(record: &CatalogIntrinsic) -> &'static str {
+    match packed_alu_width(record) {
+        32 => "r",
+        64 => "l",
+        _ => unreachable!("closed packed-ALU carrier width"),
+    }
+}
+
+pub(in crate::render) fn dot_product_ptx(record: &CatalogIntrinsic) -> &'static str {
+    let dot = record.dot_product.as_ref().expect("dot-product record");
+    match (dot.operation, dot.signedness, dot.adapter) {
+        (
+            DotProductOperation::Dp4a,
+            DotProductSignedness::Signed,
+            DotProductAdapter::DirectThreeOperands,
+        ) => "dp4a.s32.s32 $0, $1, $2, $3;",
+        (
+            DotProductOperation::Dp4a,
+            DotProductSignedness::Unsigned,
+            DotProductAdapter::DirectThreeOperands,
+        ) => "dp4a.u32.u32 $0, $1, $2, $3;",
+        (
+            DotProductOperation::Dp2a,
+            DotProductSignedness::Signed,
+            DotProductAdapter::InsertLowHalfFalse,
+        ) => "dp2a.lo.s32.s32 $0, $1, $2, $3;",
+        (
+            DotProductOperation::Dp2a,
+            DotProductSignedness::Unsigned,
+            DotProductAdapter::InsertLowHalfFalse,
+        ) => "dp2a.lo.u32.u32 $0, $1, $2, $3;",
+        combination => panic!("unsupported generated dot-product recipe {combination:?}"),
+    }
+}
+
+pub(in crate::render) fn packed_alu_ptx_mnemonic(record: &CatalogIntrinsic) -> &'static str {
+    let packed = record.packed_alu.as_ref().expect("packed-ALU record");
+    match (packed.format, packed.operation, packed.adapter) {
+        (PackedAluFormat::Bf16x2, PackedAluOperation::Add, PackedAluAdapter::DirectPackedU32) => {
+            "add.rn.bf16x2"
+        }
+        (PackedAluFormat::Bf16x2, PackedAluOperation::Sub, PackedAluAdapter::DirectPackedU32) => {
+            "sub.rn.bf16x2"
+        }
+        (PackedAluFormat::Bf16x2, PackedAluOperation::Mul, PackedAluAdapter::DirectPackedU32) => {
+            "mul.rn.bf16x2"
+        }
+        (PackedAluFormat::Bf16x2, PackedAluOperation::Fma, PackedAluAdapter::DirectPackedU32) => {
+            "fma.rn.bf16x2"
+        }
+        (
+            PackedAluFormat::Bf16x2,
+            PackedAluOperation::FmaRelu,
+            PackedAluAdapter::DirectPackedU32,
+        ) => "fma.rn.relu.bf16x2",
+        (PackedAluFormat::Bf16x2, PackedAluOperation::Min, PackedAluAdapter::DirectPackedU32) => {
+            "min.bf16x2"
+        }
+        (PackedAluFormat::Bf16x2, PackedAluOperation::Max, PackedAluAdapter::DirectPackedU32) => {
+            "max.bf16x2"
+        }
+        (PackedAluFormat::Bf16x2, PackedAluOperation::Neg, PackedAluAdapter::DirectPackedU32) => {
+            "neg.bf16x2"
+        }
+        (PackedAluFormat::Bf16x2, PackedAluOperation::Abs, PackedAluAdapter::DirectPackedU32) => {
+            "abs.bf16x2"
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::Add, PackedAluAdapter::DirectPackedU32) => {
+            "add.rn.f16x2"
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::Sub, PackedAluAdapter::DirectPackedU32) => {
+            "sub.rn.f16x2"
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::Mul, PackedAluAdapter::DirectPackedU32) => {
+            "mul.rn.f16x2"
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::Fma, PackedAluAdapter::DirectPackedU32) => {
+            "fma.rn.f16x2"
+        }
+        (
+            PackedAluFormat::F16x2,
+            PackedAluOperation::FmaRelu,
+            PackedAluAdapter::DirectPackedU32,
+        ) => "fma.rn.relu.f16x2",
+        (PackedAluFormat::F16x2, PackedAluOperation::FmaFtz, PackedAluAdapter::DirectPackedU32) => {
+            "fma.rn.ftz.f16x2"
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::FmaSat, PackedAluAdapter::DirectPackedU32) => {
+            "fma.rn.sat.f16x2"
+        }
+        (
+            PackedAluFormat::F16x2,
+            PackedAluOperation::FmaFtzSat,
+            PackedAluAdapter::DirectPackedU32,
+        ) => "fma.rn.ftz.sat.f16x2",
+        (
+            PackedAluFormat::F16x2,
+            PackedAluOperation::FmaFtzRelu,
+            PackedAluAdapter::DirectPackedU32,
+        ) => "fma.rn.ftz.relu.f16x2",
+        (PackedAluFormat::F16x2, PackedAluOperation::Min, PackedAluAdapter::DirectPackedU32) => {
+            "min.f16x2"
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::Max, PackedAluAdapter::DirectPackedU32) => {
+            "max.f16x2"
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::Neg, PackedAluAdapter::DirectPackedU32) => {
+            "neg.f16x2"
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::Abs, PackedAluAdapter::DirectPackedU32) => {
+            "abs.f16x2"
+        }
+        (PackedAluFormat::F32x2, PackedAluOperation::Add, PackedAluAdapter::DirectPackedU64) => {
+            "add.rn.f32x2"
+        }
+        (PackedAluFormat::F32x2, PackedAluOperation::AddFtz, PackedAluAdapter::DirectPackedU64) => {
+            "add.rn.ftz.f32x2"
+        }
+        (PackedAluFormat::F32x2, PackedAluOperation::Sub, PackedAluAdapter::DirectPackedU64) => {
+            "sub.rn.f32x2"
+        }
+        (PackedAluFormat::F32x2, PackedAluOperation::SubFtz, PackedAluAdapter::DirectPackedU64) => {
+            "sub.rn.ftz.f32x2"
+        }
+        (PackedAluFormat::F32x2, PackedAluOperation::Mul, PackedAluAdapter::DirectPackedU64) => {
+            "mul.rn.f32x2"
+        }
+        (PackedAluFormat::F32x2, PackedAluOperation::MulFtz, PackedAluAdapter::DirectPackedU64) => {
+            "mul.rn.ftz.f32x2"
+        }
+        (PackedAluFormat::F32x2, PackedAluOperation::Fma, PackedAluAdapter::DirectPackedU64) => {
+            "fma.rn.f32x2"
+        }
+        (PackedAluFormat::F32x2, PackedAluOperation::FmaFtz, PackedAluAdapter::DirectPackedU64) => {
+            "fma.rn.ftz.f32x2"
+        }
+        // bf16x2 has no NVPTX selection pattern for the ftz and sat fma forms;
+        // `packed_alu_recipe` rejects those pairs before a record can exist.
+        combination => panic!("unsupported generated packed-ALU recipe {combination:?}"),
+    }
+}
+
+pub(in crate::render) fn packed_conversion_destination(record: &CatalogIntrinsic) -> &'static str {
+    match record
+        .packed_conversion
+        .as_ref()
+        .expect("packed-conversion record")
+        .destination_format
+    {
+        PackedConversionDestinationFormat::Bf16x2 => "bf16x2",
+        PackedConversionDestinationFormat::E4m3x2 => "e4m3x2",
+        PackedConversionDestinationFormat::E5m2x2 => "e5m2x2",
+        PackedConversionDestinationFormat::F16x2 => "f16x2",
+    }
+}
+
+pub(in crate::render) fn packed_conversion_element(record: &CatalogIntrinsic) -> &'static str {
+    match record
+        .packed_conversion
+        .as_ref()
+        .expect("packed-conversion record")
+        .destination_format
+    {
+        PackedConversionDestinationFormat::Bf16x2 => "bf16",
+        PackedConversionDestinationFormat::E4m3x2 => "e4m3",
+        PackedConversionDestinationFormat::E5m2x2 => "e5m2",
+        PackedConversionDestinationFormat::F16x2 => "f16",
+    }
+}
+
+/// Whether the conversion is one of the closed, reviewed packed-conversion
+/// recipes: scalar `f32` pairs narrowed to a packed format, `f16x2` narrowed to
+/// packed FP8, or packed FP8 widened back to `f16x2`.
+pub(in crate::render) fn packed_conversion_is_closed_recipe(
+    conversion: &crate::model::PackedConversion,
+) -> bool {
+    use PackedConversionDestinationFormat as Dst;
+    use PackedConversionRounding as Round;
+    use PackedConversionSaturation as Sat;
+    use PackedConversionSourceFormat as Src;
+
+    let adapter_matches = conversion.adapter
+        == match conversion.source_format {
+            Src::F32x2 => PackedConversionAdapter::ReverseHighLowOperands,
+            Src::E4m3x2 | Src::E5m2x2 | Src::F16x2 => PackedConversionAdapter::Identity,
+        };
+
+    adapter_matches
+        && matches!(
+            (
+                conversion.source_format,
+                conversion.destination_format,
+                conversion.rounding,
+                conversion.saturation,
+            ),
+            (Src::F32x2, Dst::Bf16x2, Round::NearestEven, Sat::None)
+                | (Src::F32x2, Dst::Bf16x2, Round::NearestEven, Sat::Relu)
+                | (Src::F32x2, Dst::Bf16x2, Round::TowardZero, Sat::None)
+                | (Src::F32x2, Dst::F16x2, Round::NearestEven, Sat::None)
+                | (Src::F32x2, Dst::F16x2, Round::NearestEven, Sat::Relu)
+                | (Src::F32x2, Dst::F16x2, Round::TowardZero, Sat::None)
+                | (Src::F32x2, Dst::E4m3x2, Round::NearestEven, Sat::Satfinite)
+                | (
+                    Src::F32x2,
+                    Dst::E4m3x2,
+                    Round::NearestEven,
+                    Sat::SatfiniteRelu
+                )
+                | (Src::F32x2, Dst::E5m2x2, Round::NearestEven, Sat::Satfinite)
+                | (
+                    Src::F32x2,
+                    Dst::E5m2x2,
+                    Round::NearestEven,
+                    Sat::SatfiniteRelu
+                )
+                | (Src::F16x2, Dst::E4m3x2, Round::NearestEven, Sat::Satfinite)
+                | (
+                    Src::F16x2,
+                    Dst::E4m3x2,
+                    Round::NearestEven,
+                    Sat::SatfiniteRelu
+                )
+                | (Src::F16x2, Dst::E5m2x2, Round::NearestEven, Sat::Satfinite)
+                | (
+                    Src::F16x2,
+                    Dst::E5m2x2,
+                    Round::NearestEven,
+                    Sat::SatfiniteRelu
+                )
+                | (Src::E4m3x2, Dst::F16x2, Round::NearestEven, Sat::None)
+                | (Src::E4m3x2, Dst::F16x2, Round::NearestEven, Sat::Relu)
+                | (Src::E5m2x2, Dst::F16x2, Round::NearestEven, Sat::None)
+                | (Src::E5m2x2, Dst::F16x2, Round::NearestEven, Sat::Relu)
+        )
+}
+
+pub(in crate::render) fn packed_conversion_source(
+    record: &CatalogIntrinsic,
+) -> PackedConversionSourceFormat {
+    record
+        .packed_conversion
+        .as_ref()
+        .expect("packed-conversion record")
+        .source_format
+}
+
+/// Register width of a single packed source operand.
+pub(in crate::render) fn packed_conversion_source_width(record: &CatalogIntrinsic) -> u32 {
+    match packed_conversion_source(record) {
+        PackedConversionSourceFormat::F16x2 => 32,
+        PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2 => 16,
+        PackedConversionSourceFormat::F32x2 => {
+            unreachable!("f32x2 conversions do not have a single packed source")
+        }
+    }
+}
+
+/// Rust argument types, one per source operand.
+pub(in crate::render) fn packed_conversion_rust_arguments(
+    record: &CatalogIntrinsic,
+) -> Vec<&'static str> {
+    match packed_conversion_source(record) {
+        PackedConversionSourceFormat::F32x2 => vec!["f32", "f32"],
+        PackedConversionSourceFormat::F16x2 => vec!["u32"],
+        PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2 => vec!["u16"],
+    }
+}
+
+/// Dialect operand types, one per source operand.
+pub(in crate::render) fn packed_conversion_dialect_operands(
+    record: &CatalogIntrinsic,
+) -> Vec<&'static str> {
+    match packed_conversion_source(record) {
+        PackedConversionSourceFormat::F32x2 => vec!["f32", "f32"],
+        PackedConversionSourceFormat::F16x2 => vec!["i32"],
+        PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2 => vec!["i16"],
+    }
+}
+
+pub(in crate::render) fn packed_conversion_result_width(record: &CatalogIntrinsic) -> u32 {
+    match record
+        .packed_conversion
+        .as_ref()
+        .expect("packed-conversion record")
+        .destination_format
+    {
+        PackedConversionDestinationFormat::Bf16x2 | PackedConversionDestinationFormat::F16x2 => 32,
+        PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2 => 16,
+    }
+}
+
+pub(in crate::render) fn packed_conversion_rust_type(record: &CatalogIntrinsic) -> &'static str {
+    match packed_conversion_result_width(record) {
+        16 => "u16",
+        32 => "u32",
+        _ => unreachable!("closed packed-conversion result width"),
+    }
+}
+
+pub(in crate::render) fn packed_conversion_dialect_type(record: &CatalogIntrinsic) -> &'static str {
+    match packed_conversion_result_width(record) {
+        16 => "i16",
+        32 => "i32",
+        _ => unreachable!("closed packed-conversion result width"),
+    }
+}
+
+/// Inline-asm constraint string: one result register, then one per source
+/// operand. `h` is a 16-bit register, `r` a 32-bit one, and `f` an f32.
+pub(in crate::render) fn packed_conversion_constraint(record: &CatalogIntrinsic) -> &'static str {
+    match (
+        packed_conversion_result_width(record),
+        packed_conversion_source(record),
+    ) {
+        (16, PackedConversionSourceFormat::F32x2) => "=h,f,f",
+        (32, PackedConversionSourceFormat::F32x2) => "=r,f,f",
+        (16, PackedConversionSourceFormat::F16x2) => "=h,r",
+        (32, PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2) => "=r,h",
+        _ => unreachable!("closed packed-conversion result width and source format"),
+    }
+}
+
+/// Whether the conversion lowers through a typed NVVM intrinsic call rather
+/// than inline PTX. Only the scalar-`f32` pair narrowed to FP8 does; see the
+/// matching predicate in `resolve.rs` for why.
+fn packed_conversion_uses_typed_nvvm(record: &CatalogIntrinsic) -> bool {
+    let conversion = record
+        .packed_conversion
+        .as_ref()
+        .expect("packed-conversion record");
+    conversion.source_format == PackedConversionSourceFormat::F32x2
+        && matches!(
+            conversion.destination_format,
+            PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2
+        )
+}
+
+pub(in crate::render) fn packed_conversion_lowering_name(
+    record: &CatalogIntrinsic,
+) -> &'static str {
+    if packed_conversion_uses_typed_nvvm(record) {
+        "generated_packed_conversion_backend"
+    } else {
+        "generated_packed_conversion_inline_ptx"
+    }
+}
+
+pub(in crate::render) fn packed_conversion_typed_llvm_name(
+    record: &CatalogIntrinsic,
+) -> Option<String> {
+    let route = record
+        .backend_lowerings
+        .iter()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+        .expect("packed conversion has an LLVM-NVPTX route");
+    match route.mechanism {
+        BackendLoweringMechanism::TypedNvvm => Some(record.llvm_identifier()),
+        BackendLoweringMechanism::InlinePtx => None,
+    }
+}
+
+pub(in crate::render) fn packed_conversion_ptx_mnemonic(record: &CatalogIntrinsic) -> String {
+    let conversion = record
+        .packed_conversion
+        .as_ref()
+        .expect("packed-conversion record");
+    debug_assert_eq!(
+        conversion.adapter,
+        match conversion.source_format {
+            PackedConversionSourceFormat::F32x2 => PackedConversionAdapter::ReverseHighLowOperands,
+            PackedConversionSourceFormat::E4m3x2
+            | PackedConversionSourceFormat::E5m2x2
+            | PackedConversionSourceFormat::F16x2 => PackedConversionAdapter::Identity,
+        }
+    );
+    let rounding = match conversion.rounding {
+        PackedConversionRounding::NearestEven => "rn",
+        PackedConversionRounding::TowardZero => "rz",
+    };
+    let saturation = match conversion.saturation {
+        PackedConversionSaturation::None => "",
+        PackedConversionSaturation::Relu => ".relu",
+        PackedConversionSaturation::Satfinite => ".satfinite",
+        PackedConversionSaturation::SatfiniteRelu => ".satfinite.relu",
+    };
+    format!(
+        "cvt.{rounding}{saturation}.{}.{}",
+        packed_conversion_destination(record),
+        conversion.source_format.ptx_token()
+    )
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/families/scalar.rs b/crates/cuda-intrinsics-gen/src/render/families/scalar.rs
new file mode 100644
index 0000000000..4f55eb7fc1
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/families/scalar.rs
@@ -0,0 +1,319 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogIntrinsic, ExtendedMinMaxFormat, ExtendedMinMaxNan,
+    ExtendedMinMaxOperation, ExtendedMinMaxSubnormal, IntegerMinMaxFormat, IntegerMinMaxOperation,
+    IntrinsicBackend, ScalarArithmeticFormat, ScalarArithmeticOperation, ScalarArithmeticRounding,
+    ScalarArithmeticSaturation, ScalarArithmeticSubnormal, ScalarConversionRounding,
+    ScalarConversionSaturation, ScalarMathFormat, ScalarMathOperation, ScalarMathPrecision,
+    ScalarMathSubnormal,
+};
+
+pub(in crate::render) fn scalar_conversion_rounding_attr(
+    record: &CatalogIntrinsic,
+) -> &'static str {
+    match record
+        .scalar_conversion
+        .as_ref()
+        .expect("scalar-conversion contract")
+        .rounding
+    {
+        ScalarConversionRounding::NearestAway => "ScalarConversionRoundingAttr::NearestAway",
+        ScalarConversionRounding::NearestEven => "ScalarConversionRoundingAttr::NearestEven",
+        ScalarConversionRounding::TowardZero => "ScalarConversionRoundingAttr::TowardZero",
+    }
+}
+
+pub(in crate::render) fn scalar_conversion_saturation_attr(
+    record: &CatalogIntrinsic,
+) -> &'static str {
+    match record
+        .scalar_conversion
+        .as_ref()
+        .expect("scalar-conversion contract")
+        .saturation
+    {
+        ScalarConversionSaturation::None => "ScalarConversionSaturationAttr::None",
+        ScalarConversionSaturation::Relu => "ScalarConversionSaturationAttr::Relu",
+        ScalarConversionSaturation::Satfinite => "ScalarConversionSaturationAttr::Satfinite",
+        ScalarConversionSaturation::ReluSatfinite => {
+            "ScalarConversionSaturationAttr::ReluSatfinite"
+        }
+    }
+}
+
+pub(in crate::render) fn scalar_conversion_ptx_mnemonic(record: &CatalogIntrinsic) -> String {
+    format!(
+        "{}.{}",
+        record.expected_ptx.mnemonic,
+        record.expected_ptx.modifiers.join(".")
+    )
+}
+
+pub(in crate::render) fn extended_minmax_contract(
+    record: &CatalogIntrinsic,
+) -> &crate::model::ExtendedMinMax {
+    record
+        .extended_minmax
+        .as_ref()
+        .expect("extended-minmax contract")
+}
+
+pub(in crate::render) fn extended_minmax_format_attr(record: &CatalogIntrinsic) -> &'static str {
+    match extended_minmax_contract(record).format {
+        ExtendedMinMaxFormat::F32 => "ExtendedMinMaxFormatAttr::F32",
+        ExtendedMinMaxFormat::F16 => "ExtendedMinMaxFormatAttr::F16",
+        ExtendedMinMaxFormat::Bf16 => "ExtendedMinMaxFormatAttr::Bf16",
+        ExtendedMinMaxFormat::F16x2 => "ExtendedMinMaxFormatAttr::F16x2",
+        ExtendedMinMaxFormat::Bf16x2 => "ExtendedMinMaxFormatAttr::Bf16x2",
+    }
+}
+
+pub(in crate::render) fn extended_minmax_operation_attr(record: &CatalogIntrinsic) -> &'static str {
+    match extended_minmax_contract(record).operation {
+        ExtendedMinMaxOperation::Min => "ExtendedMinMaxOperationAttr::Min",
+        ExtendedMinMaxOperation::Max => "ExtendedMinMaxOperationAttr::Max",
+    }
+}
+
+pub(in crate::render) fn extended_minmax_subnormal_attr(record: &CatalogIntrinsic) -> &'static str {
+    match extended_minmax_contract(record).subnormal {
+        ExtendedMinMaxSubnormal::Preserve => "ExtendedMinMaxSubnormalAttr::Preserve",
+        ExtendedMinMaxSubnormal::Ftz => "ExtendedMinMaxSubnormalAttr::Ftz",
+    }
+}
+
+pub(in crate::render) fn extended_minmax_nan_attr(record: &CatalogIntrinsic) -> &'static str {
+    match extended_minmax_contract(record).nan {
+        ExtendedMinMaxNan::Number => "ExtendedMinMaxNanAttr::Number",
+        ExtendedMinMaxNan::Nan => "ExtendedMinMaxNanAttr::Nan",
+    }
+}
+
+pub(in crate::render) fn extended_minmax_xorsign_abs_attr(
+    record: &CatalogIntrinsic,
+) -> &'static str {
+    if extended_minmax_contract(record).xorsign_abs {
+        "ExtendedMinMaxXorSignAbsAttr::Enabled"
+    } else {
+        "ExtendedMinMaxXorSignAbsAttr::Disabled"
+    }
+}
+
+pub(in crate::render) fn extended_minmax_carrier(record: &CatalogIntrinsic) -> &'static str {
+    match extended_minmax_contract(record).format {
+        ExtendedMinMaxFormat::F32 => "MinMaxCarrier::F32",
+        ExtendedMinMaxFormat::F16 | ExtendedMinMaxFormat::Bf16 => "MinMaxCarrier::Half16",
+        ExtendedMinMaxFormat::F16x2 | ExtendedMinMaxFormat::Bf16x2 => "MinMaxCarrier::PackedU32",
+    }
+}
+
+pub(in crate::render) fn extended_minmax_rust_type(record: &CatalogIntrinsic) -> &'static str {
+    match extended_minmax_contract(record).format {
+        ExtendedMinMaxFormat::F32 => "f32",
+        ExtendedMinMaxFormat::F16 | ExtendedMinMaxFormat::Bf16 => "u16",
+        ExtendedMinMaxFormat::F16x2 | ExtendedMinMaxFormat::Bf16x2 => "u32",
+    }
+}
+
+pub(in crate::render) fn extended_minmax_ptx_mnemonic(record: &CatalogIntrinsic) -> String {
+    format!(
+        "{}.{}",
+        record.expected_ptx.mnemonic,
+        record.expected_ptx.modifiers.join(".")
+    )
+}
+
+pub(in crate::render) fn scalar_arithmetic_contract(
+    record: &CatalogIntrinsic,
+) -> &crate::model::ScalarArithmetic {
+    record
+        .scalar_arithmetic
+        .as_ref()
+        .expect("scalar-arithmetic contract")
+}
+
+pub(in crate::render) fn scalar_arithmetic_format_attr(record: &CatalogIntrinsic) -> &'static str {
+    match scalar_arithmetic_contract(record).format {
+        ScalarArithmeticFormat::F32 => "ScalarArithmeticFormatAttr::F32",
+        ScalarArithmeticFormat::F64 => "ScalarArithmeticFormatAttr::F64",
+    }
+}
+
+pub(in crate::render) fn scalar_arithmetic_operation_attr(
+    record: &CatalogIntrinsic,
+) -> &'static str {
+    match scalar_arithmetic_contract(record).operation {
+        ScalarArithmeticOperation::Mul => "ScalarArithmeticOperationAttr::Mul",
+        ScalarArithmeticOperation::Div => "ScalarArithmeticOperationAttr::Div",
+        ScalarArithmeticOperation::Fma => "ScalarArithmeticOperationAttr::Fma",
+        ScalarArithmeticOperation::Add => "ScalarArithmeticOperationAttr::Add",
+    }
+}
+
+pub(in crate::render) fn scalar_arithmetic_rounding_attr(
+    record: &CatalogIntrinsic,
+) -> &'static str {
+    match scalar_arithmetic_contract(record).rounding {
+        ScalarArithmeticRounding::Rn => "ScalarArithmeticRoundingAttr::Rn",
+        ScalarArithmeticRounding::Rz => "ScalarArithmeticRoundingAttr::Rz",
+        ScalarArithmeticRounding::Rm => "ScalarArithmeticRoundingAttr::Rm",
+        ScalarArithmeticRounding::Rp => "ScalarArithmeticRoundingAttr::Rp",
+    }
+}
+
+pub(in crate::render) fn scalar_arithmetic_subnormal_attr(
+    record: &CatalogIntrinsic,
+) -> &'static str {
+    match scalar_arithmetic_contract(record).subnormal {
+        ScalarArithmeticSubnormal::Preserve => "ScalarArithmeticSubnormalAttr::Preserve",
+        ScalarArithmeticSubnormal::Ftz => "ScalarArithmeticSubnormalAttr::Ftz",
+    }
+}
+
+pub(in crate::render) fn scalar_arithmetic_saturation_attr(
+    record: &CatalogIntrinsic,
+) -> &'static str {
+    match scalar_arithmetic_contract(record).saturation {
+        ScalarArithmeticSaturation::None => "ScalarArithmeticSaturationAttr::None",
+        ScalarArithmeticSaturation::Sat => "ScalarArithmeticSaturationAttr::Sat",
+    }
+}
+
+pub(in crate::render) fn scalar_arithmetic_arity(record: &CatalogIntrinsic) -> usize {
+    match scalar_arithmetic_contract(record).operation {
+        ScalarArithmeticOperation::Mul
+        | ScalarArithmeticOperation::Div
+        | ScalarArithmeticOperation::Add => 2,
+        ScalarArithmeticOperation::Fma => 3,
+    }
+}
+
+pub(in crate::render) fn scalar_arithmetic_rust_type(record: &CatalogIntrinsic) -> &'static str {
+    match scalar_arithmetic_contract(record).format {
+        ScalarArithmeticFormat::F32 => "f32",
+        ScalarArithmeticFormat::F64 => "f64",
+    }
+}
+
+pub(in crate::render) fn scalar_arithmetic_llvm_type(record: &CatalogIntrinsic) -> &'static str {
+    match scalar_arithmetic_contract(record).format {
+        ScalarArithmeticFormat::F32 => "float",
+        ScalarArithmeticFormat::F64 => "double",
+    }
+}
+
+pub(in crate::render) fn scalar_arithmetic_ptx_mnemonic(record: &CatalogIntrinsic) -> String {
+    format!(
+        "{}.{}",
+        record.expected_ptx.mnemonic,
+        record.expected_ptx.modifiers.join(".")
+    )
+}
+
+pub(in crate::render) fn scalar_arithmetic_llvm_mechanism(
+    record: &CatalogIntrinsic,
+) -> BackendLoweringMechanism {
+    record
+        .backend_lowerings
+        .iter()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+        .expect("scalar arithmetic has an LLVM-NVPTX route")
+        .mechanism
+}
+
+pub(in crate::render) fn scalar_math_contract(
+    record: &CatalogIntrinsic,
+) -> &crate::model::ScalarMath {
+    record.scalar_math.as_ref().expect("scalar-math contract")
+}
+
+pub(in crate::render) fn scalar_math_format_attr(record: &CatalogIntrinsic) -> &'static str {
+    match scalar_math_contract(record).format {
+        ScalarMathFormat::F16 => "ScalarMathFormatAttr::F16",
+        ScalarMathFormat::F32 => "ScalarMathFormatAttr::F32",
+        ScalarMathFormat::F64 => "ScalarMathFormatAttr::F64",
+    }
+}
+
+pub(in crate::render) fn scalar_math_operation_attr(record: &CatalogIntrinsic) -> &'static str {
+    match scalar_math_contract(record).operation {
+        ScalarMathOperation::Sin => "ScalarMathOperationAttr::Sin",
+        ScalarMathOperation::Cos => "ScalarMathOperationAttr::Cos",
+        ScalarMathOperation::Ex2 => "ScalarMathOperationAttr::Ex2",
+        ScalarMathOperation::Lg2 => "ScalarMathOperationAttr::Lg2",
+        ScalarMathOperation::Rcp => "ScalarMathOperationAttr::Rcp",
+        ScalarMathOperation::Rsqrt => "ScalarMathOperationAttr::Rsqrt",
+        ScalarMathOperation::Sqrt => "ScalarMathOperationAttr::Sqrt",
+        ScalarMathOperation::Tanh => "ScalarMathOperationAttr::Tanh",
+    }
+}
+
+pub(in crate::render) fn scalar_math_precision_attr(record: &CatalogIntrinsic) -> &'static str {
+    match scalar_math_contract(record).precision {
+        ScalarMathPrecision::Approx => "ScalarMathPrecisionAttr::Approx",
+        ScalarMathPrecision::Rn => "ScalarMathPrecisionAttr::Rn",
+        ScalarMathPrecision::Rz => "ScalarMathPrecisionAttr::Rz",
+        ScalarMathPrecision::Rm => "ScalarMathPrecisionAttr::Rm",
+        ScalarMathPrecision::Rp => "ScalarMathPrecisionAttr::Rp",
+    }
+}
+
+pub(in crate::render) fn scalar_math_subnormal_attr(record: &CatalogIntrinsic) -> &'static str {
+    match scalar_math_contract(record).subnormal {
+        ScalarMathSubnormal::Preserve => "ScalarMathSubnormalAttr::Preserve",
+        ScalarMathSubnormal::Ftz => "ScalarMathSubnormalAttr::Ftz",
+    }
+}
+
+pub(in crate::render) fn scalar_math_llvm_type(record: &CatalogIntrinsic) -> &'static str {
+    match scalar_math_contract(record).format {
+        ScalarMathFormat::F16 => "i16",
+        ScalarMathFormat::F32 => "float",
+        ScalarMathFormat::F64 => "double",
+    }
+}
+
+pub(in crate::render) fn scalar_math_ptx_mnemonic(record: &CatalogIntrinsic) -> String {
+    format!(
+        "{}.{}",
+        record.expected_ptx.mnemonic,
+        record.expected_ptx.modifiers.join(".")
+    )
+}
+
+pub(in crate::render) fn scalar_math_llvm_mechanism(
+    record: &CatalogIntrinsic,
+) -> BackendLoweringMechanism {
+    record
+        .backend_lowerings
+        .iter()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+        .expect("scalar math has an LLVM-NVPTX route")
+        .mechanism
+}
+
+pub(in crate::render) fn integer_minmax_ptx_mnemonic(record: &CatalogIntrinsic) -> &'static str {
+    let minmax = record
+        .integer_minmax
+        .as_ref()
+        .expect("integer-min/max record");
+    match (minmax.format, minmax.operation, minmax.relu) {
+        (IntegerMinMaxFormat::S32, IntegerMinMaxOperation::Min, true) => "min.relu.s32",
+        (IntegerMinMaxFormat::S32, IntegerMinMaxOperation::Max, true) => "max.relu.s32",
+        (IntegerMinMaxFormat::S16x2, IntegerMinMaxOperation::Min, false) => "min.s16x2",
+        (IntegerMinMaxFormat::S16x2, IntegerMinMaxOperation::Max, false) => "max.s16x2",
+        (IntegerMinMaxFormat::U16x2, IntegerMinMaxOperation::Min, false) => "min.u16x2",
+        (IntegerMinMaxFormat::U16x2, IntegerMinMaxOperation::Max, false) => "max.u16x2",
+        (IntegerMinMaxFormat::S16x2, IntegerMinMaxOperation::Min, true) => "min.relu.s16x2",
+        (IntegerMinMaxFormat::S16x2, IntegerMinMaxOperation::Max, true) => "max.relu.s16x2",
+        // `integer_minmax_recipe` rejects those combinations before a record
+        // can exist.
+        (IntegerMinMaxFormat::S32, _, false) | (IntegerMinMaxFormat::U16x2, _, true) => {
+            panic!("{} is outside the closed integer-min/max recipe", record.id)
+        }
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/families/tcgen05.rs b/crates/cuda-intrinsics-gen/src/render/families/tcgen05.rs
new file mode 100644
index 0000000000..21b8a88e81
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/families/tcgen05.rs
@@ -0,0 +1,1398 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogHardwareAlternative, CatalogHardwareTarget, CatalogIntrinsic,
+    IntrinsicBackend, RuntimeValidation, Tcgen05Adapter, Tcgen05CpGroup, Tcgen05CpMember,
+    Tcgen05LdMultiplicity, Tcgen05LdShape, Tcgen05Mma, Tcgen05MmaAlias, Tcgen05MmaBUsage,
+    Tcgen05MmaForm, Tcgen05MmaKind, Tcgen05MmaSelectorLayout, Tcgen05Operation,
+    Tcgen05SourceContract,
+};
+use crate::render::common::llvm;
+use std::fmt::Write as _;
+
+pub(in crate::render) fn tcgen05_mma_form_name(form: Tcgen05MmaForm) -> &'static str {
+    match form {
+        Tcgen05MmaForm::Shared => "Shared",
+        Tcgen05MmaForm::Tensor => "Tensor",
+        Tcgen05MmaForm::TensorAshift => "TensorAshift",
+        Tcgen05MmaForm::SpShared => "SpShared",
+        Tcgen05MmaForm::SpTensor => "SpTensor",
+        Tcgen05MmaForm::SpTensorAshift => "SpTensorAshift",
+        Tcgen05MmaForm::WsShared => "WsShared",
+        Tcgen05MmaForm::WsSharedZeroColMask => "WsSharedZeroColMask",
+        Tcgen05MmaForm::WsSpShared => "WsSpShared",
+        Tcgen05MmaForm::WsSpSharedZeroColMask => "WsSpSharedZeroColMask",
+        Tcgen05MmaForm::WsSpTensor => "WsSpTensor",
+        Tcgen05MmaForm::WsSpTensorZeroColMask => "WsSpTensorZeroColMask",
+        Tcgen05MmaForm::WsTensor => "WsTensor",
+        Tcgen05MmaForm::WsTensorZeroColMask => "WsTensorZeroColMask",
+    }
+}
+
+pub(in crate::render) fn tcgen05_mma_form_attr(form: Tcgen05MmaForm) -> String {
+    format!("Tcgen05MmaFormAttr::{}", tcgen05_mma_form_name(form))
+}
+
+pub(in crate::render) fn tcgen05_mma_kind_attr(kind: Tcgen05MmaKind) -> &'static str {
+    match kind {
+        Tcgen05MmaKind::F16 => "Tcgen05MmaKindAttr::F16",
+        Tcgen05MmaKind::Tf32 => "Tcgen05MmaKindAttr::Tf32",
+        Tcgen05MmaKind::F8f6f4 => "Tcgen05MmaKindAttr::F8f6f4",
+        Tcgen05MmaKind::I8 => "Tcgen05MmaKindAttr::I8",
+    }
+}
+
+pub(in crate::render) fn tcgen05_mma_b_usage_attr(usage: Tcgen05MmaBUsage) -> &'static str {
+    match usage {
+        Tcgen05MmaBUsage::Discard => "Tcgen05MmaBUsageAttr::Discard",
+        Tcgen05MmaBUsage::Fill => "Tcgen05MmaBUsageAttr::Fill",
+        Tcgen05MmaBUsage::Use => "Tcgen05MmaBUsageAttr::Use",
+        Tcgen05MmaBUsage::LastUse => "Tcgen05MmaBUsageAttr::LastUse",
+    }
+}
+
+pub(in crate::render) fn tcgen05_mma_runtime_parameters(
+    mma: &Tcgen05Mma,
+) -> Vec<(&'static str, &'static str)> {
+    if mma.alias.is_some() && mma.form == Tcgen05MmaForm::WsTensor {
+        return vec![
+            ("d_tmem", "u32"),
+            ("a_tmem", "u32"),
+            ("legacy_a_desc", "u64"),
+            ("b_desc", "u64"),
+            ("idesc", "u32"),
+            ("enable_d", "bool"),
+        ];
+    }
+    let mut parameters = match mma.form {
+        Tcgen05MmaForm::Shared
+        | Tcgen05MmaForm::SpShared
+        | Tcgen05MmaForm::WsShared
+        | Tcgen05MmaForm::WsSharedZeroColMask
+        | Tcgen05MmaForm::WsSpShared
+        | Tcgen05MmaForm::WsSpSharedZeroColMask => vec![
+            ("d_tmem", "u32"),
+            ("a_desc", "u64"),
+            ("b_desc", "u64"),
+            ("idesc", "u32"),
+            ("enable_d", "bool"),
+        ],
+        Tcgen05MmaForm::Tensor
+        | Tcgen05MmaForm::TensorAshift
+        | Tcgen05MmaForm::SpTensor
+        | Tcgen05MmaForm::SpTensorAshift
+        | Tcgen05MmaForm::WsSpTensor
+        | Tcgen05MmaForm::WsSpTensorZeroColMask
+        | Tcgen05MmaForm::WsTensor
+        | Tcgen05MmaForm::WsTensorZeroColMask => vec![
+            ("d_tmem", "u32"),
+            ("a_tmem", "u32"),
+            ("b_desc", "u64"),
+            ("idesc", "u32"),
+            ("enable_d", "bool"),
+        ],
+    };
+    if matches!(
+        mma.form,
+        Tcgen05MmaForm::SpShared
+            | Tcgen05MmaForm::SpTensor
+            | Tcgen05MmaForm::SpTensorAshift
+            | Tcgen05MmaForm::WsSpShared
+            | Tcgen05MmaForm::WsSpSharedZeroColMask
+            | Tcgen05MmaForm::WsSpTensor
+            | Tcgen05MmaForm::WsSpTensorZeroColMask
+    ) {
+        parameters.push(("metadata_tmem", "u32"));
+    }
+    if matches!(
+        mma.form,
+        Tcgen05MmaForm::WsSharedZeroColMask
+            | Tcgen05MmaForm::WsSpSharedZeroColMask
+            | Tcgen05MmaForm::WsSpTensorZeroColMask
+            | Tcgen05MmaForm::WsTensorZeroColMask
+    ) {
+        parameters.push(("zero_column_mask", "u64"));
+    }
+    parameters
+}
+
+pub(in crate::render) fn tcgen05_mma_selector_parameters(
+    layout: Tcgen05MmaSelectorLayout,
+) -> [(&'static str, &'static str); 3] {
+    match layout {
+        Tcgen05MmaSelectorLayout::Base { .. } => [
+            ("KIND", "kind"),
+            ("CTA_GROUP", "cta_group"),
+            ("COLLECTOR_A", "collector_a"),
+        ],
+        Tcgen05MmaSelectorLayout::WarpSpecialized { .. } => [
+            ("KIND", "kind"),
+            ("B_BUFFER", "b_buffer"),
+            ("B_USAGE", "b_usage"),
+        ],
+    }
+}
+
+pub(in crate::render) fn tcgen05_mma_is_ws(form: Tcgen05MmaForm) -> bool {
+    matches!(
+        form,
+        Tcgen05MmaForm::WsShared
+            | Tcgen05MmaForm::WsSharedZeroColMask
+            | Tcgen05MmaForm::WsSpShared
+            | Tcgen05MmaForm::WsSpSharedZeroColMask
+            | Tcgen05MmaForm::WsSpTensor
+            | Tcgen05MmaForm::WsSpTensorZeroColMask
+            | Tcgen05MmaForm::WsTensor
+            | Tcgen05MmaForm::WsTensorZeroColMask
+    )
+}
+
+fn tcgen05_mma_is_sparse(form: Tcgen05MmaForm) -> bool {
+    matches!(
+        form,
+        Tcgen05MmaForm::SpShared
+            | Tcgen05MmaForm::SpTensor
+            | Tcgen05MmaForm::SpTensorAshift
+            | Tcgen05MmaForm::WsSpShared
+            | Tcgen05MmaForm::WsSpSharedZeroColMask
+            | Tcgen05MmaForm::WsSpTensor
+            | Tcgen05MmaForm::WsSpTensorZeroColMask
+    )
+}
+
+fn tcgen05_mma_is_tensor_a(form: Tcgen05MmaForm) -> bool {
+    matches!(
+        form,
+        Tcgen05MmaForm::Tensor
+            | Tcgen05MmaForm::TensorAshift
+            | Tcgen05MmaForm::SpTensor
+            | Tcgen05MmaForm::SpTensorAshift
+            | Tcgen05MmaForm::WsSpTensor
+            | Tcgen05MmaForm::WsSpTensorZeroColMask
+            | Tcgen05MmaForm::WsTensor
+            | Tcgen05MmaForm::WsTensorZeroColMask
+    )
+}
+
+fn tcgen05_mma_is_ashift(form: Tcgen05MmaForm) -> bool {
+    matches!(
+        form,
+        Tcgen05MmaForm::TensorAshift | Tcgen05MmaForm::SpTensorAshift
+    )
+}
+
+fn tcgen05_mma_has_zero_col_mask(form: Tcgen05MmaForm) -> bool {
+    matches!(
+        form,
+        Tcgen05MmaForm::WsSharedZeroColMask
+            | Tcgen05MmaForm::WsSpSharedZeroColMask
+            | Tcgen05MmaForm::WsSpTensorZeroColMask
+            | Tcgen05MmaForm::WsTensorZeroColMask
+    )
+}
+
+fn tcgen05_mma_kind_name(kind: Tcgen05MmaKind) -> &'static str {
+    match kind {
+        Tcgen05MmaKind::F16 => "f16",
+        Tcgen05MmaKind::Tf32 => "tf32",
+        Tcgen05MmaKind::F8f6f4 => "f8f6f4",
+        Tcgen05MmaKind::I8 => "i8",
+    }
+}
+
+fn tcgen05_mma_b_usage_name(usage: Tcgen05MmaBUsage) -> &'static str {
+    match usage {
+        Tcgen05MmaBUsage::Discard => "discard",
+        Tcgen05MmaBUsage::LastUse => "lastuse",
+        Tcgen05MmaBUsage::Fill => "fill",
+        Tcgen05MmaBUsage::Use => "use",
+    }
+}
+
+pub(in crate::render) fn tcgen05_mma_inline_asm(
+    form: Tcgen05MmaForm,
+    kind: Tcgen05MmaKind,
+    cta_group: u8,
+    collector_a: Option<&str>,
+    b_buffer: Option<u8>,
+    b_usage: Option<Tcgen05MmaBUsage>,
+) -> (String, String) {
+    let mut instruction = "tcgen05.mma".to_owned();
+    if tcgen05_mma_is_ws(form) {
+        instruction.push_str(".ws");
+    }
+    if tcgen05_mma_is_sparse(form) {
+        instruction.push_str(".sp");
+    }
+    write!(
+        instruction,
+        ".cta_group::{cta_group}.kind::{}",
+        tcgen05_mma_kind_name(kind)
+    )
+    .unwrap();
+    if tcgen05_mma_is_ws(form) {
+        write!(
+            instruction,
+            ".collector::b{}::{}",
+            b_buffer.expect("warp-specialized B buffer"),
+            tcgen05_mma_b_usage_name(b_usage.expect("warp-specialized B usage"))
+        )
+        .unwrap();
+    } else {
+        write!(
+            instruction,
+            ".collector::a::{}",
+            collector_a.expect("base collector A usage")
+        )
+        .unwrap();
+        if tcgen05_mma_is_ashift(form) {
+            instruction.push_str(".ashift");
+        }
+    }
+
+    let a = if tcgen05_mma_is_tensor_a(form) {
+        "[$1]"
+    } else {
+        "$1"
+    };
+    write!(instruction, " [$0], {a}, $2").unwrap();
+    if tcgen05_mma_is_sparse(form) {
+        instruction.push_str(", [$5]");
+    }
+    instruction.push_str(", $3, %enable_pred");
+    if tcgen05_mma_has_zero_col_mask(form) {
+        instruction.push_str(if tcgen05_mma_is_sparse(form) {
+            ", $6"
+        } else {
+            ", $5"
+        });
+    }
+    instruction.push(';');
+
+    let template =
+        format!("{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; {instruction} }}");
+    let mut constraints = vec![
+        "r",
+        if tcgen05_mma_is_tensor_a(form) {
+            "r"
+        } else {
+            "l"
+        },
+        "l",
+        "r",
+        "r",
+    ];
+    if tcgen05_mma_is_sparse(form) {
+        constraints.push("r");
+    }
+    if tcgen05_mma_has_zero_col_mask(form) {
+        constraints.push("l");
+    }
+    constraints.push("~{memory}");
+    (template, constraints.join(","))
+}
+
+pub(in crate::render) fn tcgen05_participation_doc(
+    operation: Tcgen05Operation,
+) -> Option<&'static str> {
+    match operation {
+        Tcgen05Operation::AllocCg2
+        | Tcgen05Operation::DeallocCg2
+        | Tcgen05Operation::RelinquishAllocPermitCg2 => Some(
+            "One full warp in each peer CTA must execute this instruction; lanes within each warp must execute uniformly with the same operands.",
+        ),
+        Tcgen05Operation::Alloc
+        | Tcgen05Operation::Dealloc
+        | Tcgen05Operation::RelinquishAllocPermit
+        | Tcgen05Operation::Ld16x256bX8Pure
+        | Tcgen05Operation::Ld16x256bPure
+        | Tcgen05Operation::LoadWait
+        | Tcgen05Operation::StoreWait => {
+            Some("One full warp must execute this instruction uniformly with the same operands.")
+        }
+        Tcgen05Operation::Commit
+        | Tcgen05Operation::CommitSharedCluster
+        | Tcgen05Operation::CommitMulticast
+        | Tcgen05Operation::ShiftDown => Some("One thread in the CTA issues this instruction."),
+        Tcgen05Operation::CommitCg2
+        | Tcgen05Operation::CommitSharedClusterCg2
+        | Tcgen05Operation::CommitMulticastCg2
+        | Tcgen05Operation::ShiftDownCg2 => Some(
+            "One thread in the CTA pair issues this instruction; the peer CTA must be active and must not have exited.",
+        ),
+        _ => None,
+    }
+}
+
+pub(in crate::render) fn tcgen05_is_commit(operation: Tcgen05Operation) -> bool {
+    matches!(
+        operation,
+        Tcgen05Operation::Commit
+            | Tcgen05Operation::CommitSharedCluster
+            | Tcgen05Operation::CommitMulticast
+            | Tcgen05Operation::CommitCg2
+            | Tcgen05Operation::CommitSharedClusterCg2
+            | Tcgen05Operation::CommitMulticastCg2
+    )
+}
+
+pub(in crate::render) fn tcgen05_is_multicast_commit(operation: Tcgen05Operation) -> bool {
+    matches!(
+        operation,
+        Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2
+    )
+}
+
+pub(in crate::render) fn tcgen05_is_shift(operation: Tcgen05Operation) -> bool {
+    matches!(
+        operation,
+        Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2
+    )
+}
+
+fn tcgen05_cp_ptx_suffix(member: Tcgen05CpMember) -> &'static str {
+    use Tcgen05CpMember::*;
+    match member {
+        M128x128bB4x16P64 => "128x128b.b8x16.b4x16_p64",
+        M128x128bB6x16P32 => "128x128b.b8x16.b6x16_p32",
+        M128x128b => "128x128b",
+        M128x256bB4x16P64 => "128x256b.b8x16.b4x16_p64",
+        M128x256bB6x16P32 => "128x256b.b8x16.b6x16_p32",
+        M32x128bWarpx4B4x16P64 => "32x128b.warpx4.b8x16.b4x16_p64",
+        M32x128bWarpx4B6x16P32 => "32x128b.warpx4.b8x16.b6x16_p32",
+        M32x128bWarpx4 => "32x128b.warpx4",
+        M4x256bB4x16P64 => "4x256b.b8x16.b4x16_p64",
+        M4x256bB6x16P32 => "4x256b.b8x16.b6x16_p32",
+        M4x256b => "4x256b",
+        M64x128bWarpx2Pair0123B4x16P64 => "64x128b.warpx2::01_23.b8x16.b4x16_p64",
+        M64x128bWarpx2Pair0123B6x16P32 => "64x128b.warpx2::01_23.b8x16.b6x16_p32",
+        M64x128bWarpx2Pair0123 => "64x128b.warpx2::01_23",
+        M64x128bWarpx2Pair0213B4x16P64 => "64x128b.warpx2::02_13.b8x16.b4x16_p64",
+        M64x128bWarpx2Pair0213B6x16P32 => "64x128b.warpx2::02_13.b8x16.b6x16_p32",
+        M64x128bWarpx2Pair0213 => "64x128b.warpx2::02_13",
+    }
+}
+
+fn tcgen05_ld_shape_label(shape: Tcgen05LdShape) -> &'static str {
+    match shape {
+        Tcgen05LdShape::M16x32bx2 => "16x32bx2",
+        Tcgen05LdShape::M16x64b => "16x64b",
+        Tcgen05LdShape::M16x128b => "16x128b",
+        Tcgen05LdShape::M16x256b => "16x256b",
+        Tcgen05LdShape::M32x32b => "32x32b",
+    }
+}
+
+fn tcgen05_ld_multiplicity_label(multiplicity: Tcgen05LdMultiplicity) -> &'static str {
+    match multiplicity {
+        Tcgen05LdMultiplicity::X1 => "x1",
+        Tcgen05LdMultiplicity::X2 => "x2",
+        Tcgen05LdMultiplicity::X4 => "x4",
+        Tcgen05LdMultiplicity::X8 => "x8",
+        Tcgen05LdMultiplicity::X16 => "x16",
+        Tcgen05LdMultiplicity::X32 => "x32",
+        Tcgen05LdMultiplicity::X64 => "x64",
+        Tcgen05LdMultiplicity::X128 => "x128",
+    }
+}
+
+pub(in crate::render) fn tcgen05_ld_register_count(record: &CatalogIntrinsic) -> usize {
+    let ld = record
+        .tcgen05
+        .as_ref()
+        .and_then(|tcgen05| tcgen05.ld)
+        .expect("generated tcgen05 load identity");
+    ld.shape.register_multiplier() * ld.multiplicity.count()
+}
+
+pub(in crate::render) fn tcgen05_st_register_count(record: &CatalogIntrinsic) -> usize {
+    let st = record
+        .tcgen05
+        .as_ref()
+        .and_then(|tcgen05| tcgen05.st)
+        .expect("generated tcgen05 store identity");
+    st.shape.register_multiplier() * st.multiplicity.count()
+}
+
+fn tcgen05_mma_target_matrix_is_closed(
+    target: &crate::model::CatalogTargetRequirement,
+    backend: IntrinsicBackend,
+    fixed_kind: Option<Tcgen05MmaKind>,
+) -> bool {
+    let CatalogHardwareTarget::TargetMatrix { contracts } = &target.hardware else {
+        return false;
+    };
+    let expected_kinds: Vec<&str> = fixed_kind.map_or_else(
+        || vec!["f16", "tf32", "f8f6f4", "i8"],
+        |kind| vec![tcgen05_mma_kind_name(kind)],
+    );
+    if target.minimum_ptx.to_string() != "8.6" || contracts.len() != expected_kinds.len() {
+        return false;
+    }
+    let common = match backend {
+        IntrinsicBackend::LlvmNvptx => vec![
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                "8.6",
+            ),
+            (CatalogHardwareAlternative::FamilyTarget { sm: 100 }, "8.8"),
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+                "8.6",
+            ),
+            (CatalogHardwareAlternative::FamilyTarget { sm: 101 }, "8.8"),
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+                "8.8",
+            ),
+            (CatalogHardwareAlternative::FamilyTarget { sm: 103 }, "8.8"),
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+                "9.0",
+            ),
+            (CatalogHardwareAlternative::FamilyTarget { sm: 110 }, "9.0"),
+        ],
+        IntrinsicBackend::LibNvvm => vec![
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                "8.6",
+            ),
+            (CatalogHardwareAlternative::FamilyTarget { sm: 100 }, "8.8"),
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+                "8.8",
+            ),
+            (CatalogHardwareAlternative::FamilyTarget { sm: 103 }, "8.8"),
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+                "9.0",
+            ),
+            (CatalogHardwareAlternative::FamilyTarget { sm: 110 }, "9.0"),
+        ],
+    };
+    let i8 = match backend {
+        IntrinsicBackend::LlvmNvptx => vec![
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                "8.6",
+            ),
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+                "8.6",
+            ),
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+                "9.0",
+            ),
+        ],
+        IntrinsicBackend::LibNvvm => vec![
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                "8.6",
+            ),
+            (
+                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+                "9.0",
+            ),
+        ],
+    };
+    expected_kinds.into_iter().all(|kind| {
+        let Some(contract) = contracts.iter().find(|contract| {
+            contract.selectors.len() == 1
+                && contract.selectors[0].name == "kind"
+                && contract.selectors[0].value == kind
+        }) else {
+            return false;
+        };
+        let expected = if kind == "i8" { &i8 } else { &common };
+        contract.alternatives.len() == expected.len()
+            && contract.alternatives.iter().zip(expected).all(
+                |(actual, (hardware, minimum_ptx))| {
+                    actual.hardware == *hardware && actual.minimum_ptx.to_string() == *minimum_ptx
+                },
+            )
+    })
+}
+
+fn tcgen05_mma_render_contract(
+    record: &CatalogIntrinsic,
+    tcgen05: &crate::model::Tcgen05,
+    mma: &Tcgen05Mma,
+    llvm_route: &crate::model::CatalogBackendLowering,
+    libnvvm_route: &crate::model::CatalogBackendLowering,
+) -> bool {
+    if tcgen05.operation != Tcgen05Operation::Mma
+        || tcgen05.cp.is_some()
+        || tcgen05.ld.is_some()
+        || tcgen05.st.is_some()
+        || tcgen05.source_contract != Tcgen05SourceContract::TablegenSelectionChangesPtx
+        || tcgen05.runtime_validation != RuntimeValidation::Unexecuted
+        || record.rust.module != "tcgen05"
+        || record.rust.safe
+        || record.rust.must_use
+        || record.rust.result != "()"
+        || record.dialect.op_type != "Tcgen05MmaOp"
+        || record.dialect.op_name != "nvvm.tcgen05_mma"
+        || !record.dialect.results.is_empty()
+        || record.lowering != "generated_tcgen05_mma"
+        || record.semantics.pure
+        || record.semantics.memory != "read_write"
+        || !record.semantics.convergent
+        || record.semantics.execution_scope != "thread"
+        || record.target.minimum_ptx.to_string() != "8.6"
+        || record.target.hardware != mma.llvm_target.hardware
+        || record.target.targets != "sm_100a|sm_101a|sm_103a|sm_110a"
+        || llvm_route.backend != IntrinsicBackend::LlvmNvptx
+        || llvm_route.mechanism != BackendLoweringMechanism::InlinePtx
+        || llvm_route.target != mma.llvm_target
+        || !tcgen05_mma_target_matrix_is_closed(
+            &llvm_route.target,
+            IntrinsicBackend::LlvmNvptx,
+            mma.fixed_selectors.map(|fixed| fixed.kind),
+        )
+        || libnvvm_route.backend != IntrinsicBackend::LibNvvm
+        || libnvvm_route.mechanism != BackendLoweringMechanism::InlinePtx
+        || libnvvm_route.target != mma.libnvvm_target
+        || !tcgen05_mma_target_matrix_is_closed(
+            &libnvvm_route.target,
+            IntrinsicBackend::LibNvvm,
+            mma.fixed_selectors.map(|fixed| fixed.kind),
+        )
+    {
+        return false;
+    }
+
+    let mut expected_operands = vec![
+        "i32".to_owned(),
+        if tcgen05_mma_is_tensor_a(mma.form) {
+            "i32".to_owned()
+        } else {
+            "i64".to_owned()
+        },
+        "i64".to_owned(),
+        "i32".to_owned(),
+        "i1".to_owned(),
+    ];
+    if tcgen05_mma_is_sparse(mma.form) {
+        expected_operands.push("i32".into());
+    }
+    if tcgen05_mma_has_zero_col_mask(mma.form) {
+        expected_operands.push("i64".into());
+    }
+
+    let llvm = llvm(record);
+    let representative_kind = mma
+        .fixed_selectors
+        .map_or(Tcgen05MmaKind::F16, |fixed| fixed.kind);
+    let representative_buffer = mma.fixed_selectors.map_or(0, |fixed| fixed.b_buffer);
+    let representative_usage = mma
+        .fixed_selectors
+        .map_or(Tcgen05MmaBUsage::Discard, |fixed| fixed.b_usage);
+    let representative = if tcgen05_mma_is_ws(mma.form) {
+        tcgen05_mma_inline_asm(
+            mma.form,
+            representative_kind,
+            1,
+            None,
+            Some(representative_buffer),
+            Some(representative_usage),
+        )
+    } else {
+        tcgen05_mma_inline_asm(
+            mma.form,
+            representative_kind,
+            1,
+            Some("discard"),
+            None,
+            None,
+        )
+    };
+    let instruction = representative
+        .0
+        .find("tcgen05.mma")
+        .map_or("", |start| &representative.0[start..]);
+    let head = instruction.split_whitespace().next().unwrap_or_default();
+    let mut components = head.split('.');
+    let expected_mnemonic = components.next().unwrap_or_default();
+    let expected_modifiers = components.map(str::to_owned).collect::<Vec<_>>();
+    let mut expected_ptx_operands = vec![crate::ptx::OperandPattern::Address];
+    expected_ptx_operands.push(if tcgen05_mma_is_tensor_a(mma.form) {
+        crate::ptx::OperandPattern::Address
+    } else {
+        crate::ptx::OperandPattern::Register
+    });
+    expected_ptx_operands.push(crate::ptx::OperandPattern::Register);
+    if tcgen05_mma_is_sparse(mma.form) {
+        expected_ptx_operands.push(crate::ptx::OperandPattern::Address);
+    }
+    expected_ptx_operands.extend([
+        crate::ptx::OperandPattern::Register,
+        crate::ptx::OperandPattern::Exact {
+            value: "%enable_pred".into(),
+        },
+    ]);
+    if tcgen05_mma_has_zero_col_mask(mma.form) {
+        expected_ptx_operands.push(crate::ptx::OperandPattern::Register);
+    }
+    if record.dialect.operands != expected_operands
+        || !llvm.results.is_empty()
+        || record.expected_ptx.mnemonic != expected_mnemonic
+        || record.expected_ptx.modifiers != expected_modifiers
+        || record.expected_ptx.operands != expected_ptx_operands
+    {
+        return false;
+    }
+
+    match (tcgen05.adapter, mma.alias, mma.fixed_selectors) {
+        (Tcgen05Adapter::MmaDirectSelectors, None, None) => {
+            let selector_indices = match mma.selector_layout {
+                Tcgen05MmaSelectorLayout::Base {
+                    kind_argument,
+                    cta_group_argument,
+                    collector_a_argument,
+                    collector_a_upper_exclusive,
+                } => {
+                    if collector_a_upper_exclusive
+                        != if tcgen05_mma_is_ashift(mma.form) {
+                            2
+                        } else {
+                            4
+                        }
+                    {
+                        return false;
+                    }
+                    [kind_argument, cta_group_argument, collector_a_argument]
+                }
+                Tcgen05MmaSelectorLayout::WarpSpecialized {
+                    kind_argument,
+                    b_buffer_argument,
+                    b_usage_argument,
+                } => [kind_argument, b_buffer_argument, b_usage_argument],
+            };
+            let first_selector = expected_operands.len() as u8;
+            record.rust.arguments.len() == expected_operands.len() + 3
+                && record
+                    .rust
+                    .arguments
+                    .ends_with(&["u32".into(), "u32".into(), "u32".into()])
+                && llvm.arguments.len() == expected_operands.len() + 3
+                && selector_indices == [first_selector, first_selector + 1, first_selector + 2]
+                && tcgen05_mma_is_ws(mma.form)
+                    == matches!(
+                        mma.selector_layout,
+                        Tcgen05MmaSelectorLayout::WarpSpecialized { .. }
+                    )
+        }
+        (
+            Tcgen05Adapter::MmaDirectSelectors,
+            Some(
+                Tcgen05MmaAlias::E4m3
+                | Tcgen05MmaAlias::E5m2
+                | Tcgen05MmaAlias::E2m3
+                | Tcgen05MmaAlias::E3m2
+                | Tcgen05MmaAlias::E2m1,
+            ),
+            Some(fixed),
+        ) => {
+            mma.form == Tcgen05MmaForm::Shared
+                && fixed.kind == Tcgen05MmaKind::F8f6f4
+                && fixed.b_buffer == 0
+                && fixed.b_usage == Tcgen05MmaBUsage::Discard
+                && matches!(
+                    mma.selector_layout,
+                    Tcgen05MmaSelectorLayout::Base {
+                        kind_argument: 5,
+                        cta_group_argument: 6,
+                        collector_a_argument: 7,
+                        collector_a_upper_exclusive: 4,
+                    }
+                )
+                && record.rust.arguments == ["u32", "u64", "u64", "u32", "bool"]
+                && record.dialect.operands == ["i32", "i64", "i64", "i32", "i1"]
+                && llvm.arguments.len() == 8
+        }
+        (
+            Tcgen05Adapter::MmaWsFixedSelectorsDropLegacyADescriptor,
+            Some(
+                Tcgen05MmaAlias::E4m3
+                | Tcgen05MmaAlias::E5m2
+                | Tcgen05MmaAlias::E2m3
+                | Tcgen05MmaAlias::E3m2
+                | Tcgen05MmaAlias::E2m1,
+            ),
+            Some(fixed),
+        ) => {
+            mma.form == Tcgen05MmaForm::WsTensor
+                && fixed.kind == Tcgen05MmaKind::F8f6f4
+                && fixed.b_buffer == 0
+                && fixed.b_usage == Tcgen05MmaBUsage::Discard
+                && record.rust.arguments == ["u32", "u32", "u64", "u64", "u32", "bool"]
+                && record.dialect.operands == ["i32", "i32", "i64", "i32", "i1"]
+                && llvm.arguments.len() == 8
+        }
+        _ => false,
+    }
+}
+
+pub(in crate::render) fn tcgen05_render_contract(record: &CatalogIntrinsic) -> bool {
+    let Some(tcgen05) = &record.tcgen05 else {
+        return false;
+    };
+    let [llvm_route, libnvvm_route] = record.backend_lowerings.as_slice() else {
+        return false;
+    };
+    if let Some(mma) = &tcgen05.mma {
+        return tcgen05_mma_render_contract(record, tcgen05, mma, llvm_route, libnvvm_route);
+    }
+    let llvm_hardware = CatalogHardwareTarget::AnyOf {
+        alternatives: vec![
+            CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+            CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+            CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+            CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+        ],
+    };
+    let libnvvm_hardware = CatalogHardwareTarget::AnyOf {
+        alternatives: vec![
+            CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+            CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+            CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+        ],
+    };
+    if record.rust.module != "tcgen05"
+        || record.rust.must_use != (tcgen05.operation == Tcgen05Operation::Ld)
+        || record.lowering != "generated_tcgen05"
+        || !record.semantics.convergent
+        || record.semantics.execution_scope != tcgen05.operation.execution_scope()
+        || record.target.minimum_ptx.to_string() != "8.6"
+        || record.target.targets != "sm_100a|sm_101a|sm_103a|sm_110a"
+        || llvm_route.backend != IntrinsicBackend::LlvmNvptx
+        || llvm_route.mechanism != BackendLoweringMechanism::InlinePtx
+        || llvm_route.target.minimum_ptx.to_string() != "8.6"
+        || llvm_route.target.hardware != llvm_hardware
+        || libnvvm_route.backend != IntrinsicBackend::LibNvvm
+        || libnvvm_route.mechanism != BackendLoweringMechanism::InlinePtx
+        || libnvvm_route.target.minimum_ptx.to_string() != "8.6"
+        || libnvvm_route.target.hardware != libnvvm_hardware
+        || tcgen05.runtime_validation != RuntimeValidation::Unexecuted
+    {
+        return false;
+    }
+    match tcgen05.cp {
+        Some(cp) => {
+            let expected_operation = match cp.group {
+                Tcgen05CpGroup::Cg1 => Tcgen05Operation::CpSmemToTmem,
+                Tcgen05CpGroup::Cg2 => Tcgen05Operation::CpSmemToTmemCg2,
+            };
+            let group = match cp.group {
+                Tcgen05CpGroup::Cg1 => "cta_group::1",
+                Tcgen05CpGroup::Cg2 => "cta_group::2",
+            };
+            let modifiers = std::iter::once("cp")
+                .chain(std::iter::once(group))
+                .chain(tcgen05_cp_ptx_suffix(cp.member).split('.'))
+                .collect::<Vec<_>>();
+            if tcgen05.operation != expected_operation
+                || tcgen05.ld.is_some()
+                || tcgen05.st.is_some()
+                || record.semantics.pure
+                || record.semantics.memory != "read_write"
+                || record.expected_ptx.mnemonic != "tcgen05"
+                || record.expected_ptx.modifiers != modifiers
+                || record.expected_ptx.operands
+                    != [
+                        crate::ptx::OperandPattern::Address,
+                        crate::ptx::OperandPattern::Register,
+                    ]
+            {
+                return false;
+            }
+        }
+        None if !matches!(
+            tcgen05.operation,
+            Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2
+        ) => {}
+        None if matches!(
+            record.id.as_str(),
+            "tcgen05_cp_smem_to_tmem" | "tcgen05_cp_smem_to_tmem_cg2"
+        ) => {}
+        None => return false,
+    }
+    match tcgen05.ld {
+        Some(ld) => {
+            let count = tcgen05_ld_register_count(record);
+            let mut modifiers: Vec<String> = vec![
+                "ld".into(),
+                "sync".into(),
+                "aligned".into(),
+                tcgen05_ld_shape_label(ld.shape).into(),
+                tcgen05_ld_multiplicity_label(ld.multiplicity).into(),
+            ];
+            if ld.pack16 {
+                modifiers.push("pack::16b".into());
+            }
+            modifiers.push("b32".into());
+            let destination = crate::ptx::OperandPattern::RegisterList { length: count };
+            let mut operands = vec![destination, crate::ptx::OperandPattern::Address];
+            if ld.shape == Tcgen05LdShape::M16x32bx2 {
+                operands.push(crate::ptx::OperandPattern::Immediate);
+            }
+            if tcgen05.operation != Tcgen05Operation::Ld
+                || tcgen05.cp.is_some()
+                || tcgen05.st.is_some()
+                || record.expected_ptx.mnemonic != "tcgen05"
+                || record.expected_ptx.modifiers != modifiers
+                || record.expected_ptx.operands != operands
+            {
+                return false;
+            }
+        }
+        None if tcgen05.operation != Tcgen05Operation::Ld => {}
+        None => return false,
+    }
+    match tcgen05.st {
+        Some(st) => {
+            let count = tcgen05_st_register_count(record);
+            let mut modifiers: Vec<String> = vec![
+                "st".into(),
+                "sync".into(),
+                "aligned".into(),
+                tcgen05_ld_shape_label(st.shape).into(),
+                tcgen05_ld_multiplicity_label(st.multiplicity).into(),
+            ];
+            if st.unpack16 {
+                modifiers.push("unpack::16b".into());
+            }
+            modifiers.push("b32".into());
+            let data = crate::ptx::OperandPattern::RegisterList { length: count };
+            let mut operands = vec![crate::ptx::OperandPattern::Address];
+            if st.shape == Tcgen05LdShape::M16x32bx2 {
+                operands.push(crate::ptx::OperandPattern::Immediate);
+            }
+            operands.push(data);
+            if tcgen05.operation != Tcgen05Operation::St
+                || tcgen05.cp.is_some()
+                || tcgen05.ld.is_some()
+                || record.expected_ptx.mnemonic != "tcgen05"
+                || record.expected_ptx.modifiers != modifiers
+                || record.expected_ptx.operands != operands
+            {
+                return false;
+            }
+        }
+        None if tcgen05.operation != Tcgen05Operation::St => {}
+        None => return false,
+    }
+    let llvm = llvm(record);
+    match (tcgen05.operation, tcgen05.adapter) {
+        (
+            Tcgen05Operation::Alloc | Tcgen05Operation::AllocCg2,
+            Tcgen05Adapter::SharedPointerColumnsToVoid,
+        ) => {
+            !record.rust.safe
+                && record.rust.arguments == ["*mut u32", "u32"]
+                && record.rust.result == "()"
+                && record.dialect.operands == ["ptr", "i32"]
+                && record.dialect.results.is_empty()
+                && llvm.arguments == ["shared_ptr", "i32"]
+                && llvm.results.is_empty()
+                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
+        }
+        (
+            Tcgen05Operation::Dealloc | Tcgen05Operation::DeallocCg2,
+            Tcgen05Adapter::TmemAddressColumnsToVoid,
+        ) => {
+            !record.rust.safe
+                && record.rust.arguments == ["u32", "u32"]
+                && record.rust.result == "()"
+                && record.dialect.operands == ["i32", "i32"]
+                && llvm.arguments == ["tmem_ptr", "i32"]
+                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
+        }
+        (
+            Tcgen05Operation::RelinquishAllocPermit
+            | Tcgen05Operation::RelinquishAllocPermitCg2
+            | Tcgen05Operation::FenceBeforeThreadSync
+            | Tcgen05Operation::FenceAfterThreadSync
+            | Tcgen05Operation::LoadWait
+            | Tcgen05Operation::StoreWait,
+            Tcgen05Adapter::NoOperands,
+        ) => {
+            record.rust.safe
+                && record.rust.arguments.is_empty()
+                && record.rust.result == "()"
+                && record.dialect.operands.is_empty()
+                && llvm.arguments.is_empty()
+                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
+        }
+        (
+            Tcgen05Operation::Commit
+            | Tcgen05Operation::CommitCg2
+            | Tcgen05Operation::CommitSharedCluster
+            | Tcgen05Operation::CommitSharedClusterCg2,
+            Tcgen05Adapter::BarrierPointerToVoid,
+        ) => {
+            !record.rust.safe
+                && record.rust.arguments == ["*mut u64"]
+                && record.rust.result == "()"
+                && record.dialect.operands == ["ptr"]
+                && llvm.arguments.len() == 1
+                && if matches!(
+                    tcgen05.operation,
+                    Tcgen05Operation::Commit | Tcgen05Operation::CommitCg2
+                ) {
+                    tcgen05.source_contract == Tcgen05SourceContract::TablegenSelectionChangesPtx
+                        && llvm.arguments == ["ptr"]
+                } else {
+                    tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
+                        && llvm.arguments == ["shared_ptr"]
+                }
+        }
+        (
+            Tcgen05Operation::MmaWsF16 | Tcgen05Operation::MmaWsBf16 | Tcgen05Operation::MmaWsTf32,
+            Tcgen05Adapter::MmaWsDropLegacyADescriptor,
+        ) => {
+            !record.rust.safe
+                && record.rust.arguments == ["u32", "u32", "u64", "u64", "u32", "bool"]
+                && record.rust.result == "()"
+                && record.dialect.operands == ["i32", "i32", "i64", "i64", "i32", "i1"]
+                && llvm.arguments
+                    == [
+                        "tmem_ptr", "tmem_ptr", "i64", "i32", "i1", "i32", "i32", "i32",
+                    ]
+                && tcgen05.source_contract == Tcgen05SourceContract::TablegenSelectionChangesPtx
+                && (tcgen05.operation != Tcgen05Operation::MmaWsBf16
+                    || (record.expected_ptx.modifiers.contains(&"kind::f16".into())
+                        && !record.expected_ptx.modifiers.contains(&"kind::bf16".into())))
+        }
+        (
+            Tcgen05Operation::MmaF16 | Tcgen05Operation::MmaF16Cg2,
+            Tcgen05Adapter::MmaInjectZeroDisableLanes,
+        ) => {
+            !record.rust.safe
+                && record.rust.arguments == ["u32", "u64", "u64", "u32", "bool"]
+                && record.rust.result == "()"
+                && record.dialect.operands == ["i32", "i64", "i64", "i32", "i1"]
+                && llvm.arguments.len() == 8
+                && tcgen05.source_contract
+                    == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
+        }
+        (
+            Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2,
+            Tcgen05Adapter::TmemDescriptorToVoid,
+        ) => {
+            !record.rust.safe
+                && record.rust.arguments == ["u32", "u64"]
+                && record.rust.result == "()"
+                && record.dialect.operands == ["i32", "i64"]
+                && llvm.arguments == ["tmem_ptr", "i64"]
+                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
+        }
+        (Tcgen05Operation::Ld16x256bX8Pure, Tcgen05Adapter::TmemToF32x32) => {
+            !record.rust.safe
+                && record.rust.arguments == ["u32"]
+                && record.rust.result == "[f32; 32]"
+                && record.dialect.operands == ["i32"]
+                && record.dialect.results == vec!["f32"; 32]
+                && llvm.arguments == ["tmem_ptr", "i1"]
+                && llvm.results == ["v32i32"]
+                && tcgen05.source_contract
+                    == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
+        }
+        (Tcgen05Operation::Ld16x256bPure, Tcgen05Adapter::TmemToF32x4) => {
+            !record.rust.safe
+                && record.rust.arguments == ["u32"]
+                && record.rust.result == "[f32; 4]"
+                && record.dialect.operands == ["i32"]
+                && record.dialect.results == ["f32", "f32", "f32", "f32"]
+                && llvm.arguments == ["tmem_ptr", "i1"]
+                && llvm.results == ["v4i32"]
+                && tcgen05.source_contract
+                    == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
+        }
+        (
+            Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2,
+            Tcgen05Adapter::BarrierPointerMaskToVoid,
+        ) => {
+            !record.rust.safe
+                && record.rust.arguments == ["*mut u64", "u16"]
+                && record.rust.result == "()"
+                && record.dialect.operands == ["ptr", "i16"]
+                && llvm.arguments == ["shared_ptr", "i16"]
+                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
+        }
+        (
+            Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2,
+            Tcgen05Adapter::TmemAddressToVoid,
+        ) => {
+            !record.rust.safe
+                && record.rust.arguments == ["u32"]
+                && record.rust.result == "()"
+                && record.dialect.operands == ["i32"]
+                && record.dialect.results.is_empty()
+                && llvm.arguments == ["tmem_ptr"]
+                && llvm.results.is_empty()
+                && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
+        }
+        (
+            Tcgen05Operation::Ld,
+            Tcgen05Adapter::TmemInjectPack16ToU32Registers
+            | Tcgen05Adapter::TmemHalfSplitOffsetInjectPack16ToU32Registers,
+        ) => {
+            let count = tcgen05_ld_register_count(record);
+            let has_half_split_offset =
+                tcgen05.adapter == Tcgen05Adapter::TmemHalfSplitOffsetInjectPack16ToU32Registers;
+            let rust_result = if count == 1 {
+                "u32".into()
+            } else {
+                format!("[u32; {count}]")
+            };
+            let llvm_result = if count == 1 {
+                "i32".into()
+            } else {
+                format!("v{count}i32")
+            };
+            !record.rust.safe
+                && record.rust.arguments
+                    == if has_half_split_offset {
+                        vec!["u32", "i64"]
+                    } else {
+                        vec!["u32"]
+                    }
+                && record.rust.result == rust_result
+                && record.dialect.operands
+                    == if has_half_split_offset {
+                        vec!["i32", "i64"]
+                    } else {
+                        vec!["i32"]
+                    }
+                && record.dialect.results == vec!["i32"; count]
+                && llvm.arguments
+                    == if has_half_split_offset {
+                        vec!["tmem_ptr", "i64", "i1"]
+                    } else {
+                        vec!["tmem_ptr", "i1"]
+                    }
+                && llvm.results == [llvm_result]
+                && !record.semantics.pure
+                && record.semantics.memory == "read"
+                && tcgen05.source_contract
+                    == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
+        }
+        (
+            Tcgen05Operation::St,
+            Tcgen05Adapter::TmemU32RegistersInjectUnpack16ToVoid
+            | Tcgen05Adapter::TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid,
+        ) => {
+            let count = tcgen05_st_register_count(record);
+            let has_half_split_offset = tcgen05.adapter
+                == Tcgen05Adapter::TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid;
+            let rust_data = if count == 1 {
+                "u32".into()
+            } else {
+                format!("[u32; {count}]")
+            };
+            let llvm_data = if count == 1 {
+                "i32".into()
+            } else {
+                format!("v{count}i32")
+            };
+            !record.rust.safe
+                && record.rust.arguments
+                    == if has_half_split_offset {
+                        vec!["u32", "i64", rust_data.as_str()]
+                    } else {
+                        vec!["u32", rust_data.as_str()]
+                    }
+                && record.rust.result == "()"
+                && record.dialect.operands
+                    == std::iter::once("i32")
+                        .chain(has_half_split_offset.then_some("i64"))
+                        .chain(std::iter::repeat_n("i32", count))
+                        .collect::<Vec<_>>()
+                && record.dialect.results.is_empty()
+                && llvm.arguments
+                    == if has_half_split_offset {
+                        vec!["tmem_ptr", "i64", llvm_data.as_str(), "i1"]
+                    } else {
+                        vec!["tmem_ptr", llvm_data.as_str(), "i1"]
+                    }
+                && llvm.results.is_empty()
+                && !record.semantics.pure
+                && record.semantics.memory == "write"
+                && tcgen05.source_contract
+                    == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
+        }
+        _ => false,
+    }
+}
+
+fn tcgen05_carrier_name(ty: &str) -> &'static str {
+    match ty {
+        "ptr" => "Ptr",
+        "i1" => "I1",
+        "i16" => "I16",
+        "i32" => "I32",
+        "i64" => "I64",
+        "f32" => "F32",
+        _ => panic!("unsupported tcgen05 dialect carrier {ty}"),
+    }
+}
+
+pub(in crate::render) fn render_tcgen05_carrier_runs(types: &[String]) -> String {
+    let mut runs = Vec::<(&str, usize)>::new();
+    for ty in types {
+        let carrier = tcgen05_carrier_name(ty);
+        if let Some((previous, count)) = runs.last_mut()
+            && *previous == carrier
+        {
+            *count += 1;
+        } else {
+            runs.push((carrier, 1));
+        }
+    }
+
+    let mut output = String::from("&[");
+    for (index, (carrier, count)) in runs.into_iter().enumerate() {
+        if index != 0 {
+            output.push_str(", ");
+        }
+        write!(output, "(Tcgen05Carrier::{carrier}, {count})").unwrap();
+    }
+    output.push(']');
+    output
+}
+
+pub(in crate::render) fn tcgen05_inline_asm(
+    record: &CatalogIntrinsic,
+) -> (String, String, Option<usize>) {
+    let operation = record.tcgen05.as_ref().expect("tcgen05 contract").operation;
+    match operation {
+        Tcgen05Operation::Alloc | Tcgen05Operation::AllocCg2 => {
+            let group = if operation == Tcgen05Operation::AllocCg2 { 2 } else { 1 };
+            (
+                format!("{{ .reg .u64 %shared64; .reg .u32 %shared32; cvta.to.shared.u64 %shared64, $0; cvt.u32.u64 %shared32, %shared64; tcgen05.alloc.cta_group::{group}.sync.aligned.shared::cta.b32 [%shared32], $1; }}"),
+                "l,r,~{memory}".into(),
+                None,
+            )
+        }
+        Tcgen05Operation::Dealloc | Tcgen05Operation::DeallocCg2 => {
+            let group = if operation == Tcgen05Operation::DeallocCg2 { 2 } else { 1 };
+            (
+                format!("tcgen05.dealloc.cta_group::{group}.sync.aligned.b32 $0, $1;"),
+                "r,r,~{memory}".into(),
+                None,
+            )
+        }
+        Tcgen05Operation::RelinquishAllocPermit
+        | Tcgen05Operation::RelinquishAllocPermitCg2 => {
+            let group = if operation == Tcgen05Operation::RelinquishAllocPermitCg2 {
+                2
+            } else {
+                1
+            };
+            (
+                format!("tcgen05.relinquish_alloc_permit.cta_group::{group}.sync.aligned;"),
+                "~{memory}".into(),
+                None,
+            )
+        }
+        Tcgen05Operation::FenceBeforeThreadSync => (
+            "tcgen05.fence::before_thread_sync;".into(),
+            "~{memory}".into(),
+            None,
+        ),
+        Tcgen05Operation::FenceAfterThreadSync => (
+            "tcgen05.fence::after_thread_sync;".into(),
+            "~{memory}".into(),
+            None,
+        ),
+        Tcgen05Operation::Commit
+        | Tcgen05Operation::CommitSharedCluster
+        | Tcgen05Operation::CommitCg2
+        | Tcgen05Operation::CommitSharedClusterCg2 => {
+            let group = if matches!(
+                operation,
+                Tcgen05Operation::CommitCg2 | Tcgen05Operation::CommitSharedClusterCg2
+            ) {
+                2
+            } else {
+                1
+            };
+            let shared = if matches!(
+                operation,
+                Tcgen05Operation::CommitSharedCluster
+                    | Tcgen05Operation::CommitSharedClusterCg2
+            ) {
+                ".shared::cluster"
+            } else {
+                ""
+            };
+            (
+                format!("tcgen05.commit.cta_group::{group}.mbarrier::arrive::one{shared}.b64 [$0];"),
+                "r,~{memory}".into(),
+                None,
+            )
+        }
+        Tcgen05Operation::MmaWsF16 | Tcgen05Operation::MmaWsBf16 => (
+            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::f16 [$0], [$1], $3, $4, %enable_pred; }".into(),
+            "r,r,l,l,r,r,~{memory}".into(),
+            None,
+        ),
+        Tcgen05Operation::MmaWsTf32 => (
+            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::tf32 [$0], [$1], $3, $4, %enable_pred; }".into(),
+            "r,r,l,l,r,r,~{memory}".into(),
+            None,
+        ),
+        Tcgen05Operation::MmaF16 | Tcgen05Operation::MmaF16Cg2 => {
+            let group = if operation == Tcgen05Operation::MmaF16Cg2 { 2 } else { 1 };
+            let zeros = std::iter::repeat_n("%z", if group == 2 { 8 } else { 4 })
+                .collect::<Vec<_>>()
+                .join(", ");
+            (
+                format!("{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; .reg .u32 %z; mov.u32 %z, 0; tcgen05.mma.cta_group::{group}.kind::f16 [$0], $1, $2, $3, {{{zeros}}}, %enable_pred; }}"),
+                "r,l,l,r,r,~{memory}".into(),
+                None,
+            )
+        }
+        Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2 => {
+            (
+                format!(
+                    "{}.{} [$0], $1;",
+                    record.expected_ptx.mnemonic,
+                    record.expected_ptx.modifiers.join(".")
+                ),
+                "r,l,~{memory}".into(),
+                None,
+            )
+        }
+        Tcgen05Operation::Ld16x256bX8Pure | Tcgen05Operation::Ld16x256bPure => {
+            let count = if operation == Tcgen05Operation::Ld16x256bX8Pure {
+                32
+            } else {
+                4
+            };
+            let registers = (0..count)
+                .map(|index| format!("${index}"))
+                .collect::<Vec<_>>()
+                .join(",");
+            let constraints = std::iter::repeat_n("=f", count)
+                .chain(std::iter::once("r"))
+                .collect::<Vec<_>>()
+                .join(",");
+            (
+                format!(
+                    "tcgen05.ld.sync.aligned.16x256b.{}.b32 {{{registers}}}, [${count}];",
+                    if count == 32 { "x8" } else { "x1" }
+                ),
+                constraints,
+                Some(count),
+            )
+        }
+        Tcgen05Operation::Ld => {
+            let count = tcgen05_ld_register_count(record);
+            let has_half_split_offset = record
+                .tcgen05
+                .as_ref()
+                .and_then(|tcgen05| tcgen05.ld)
+                .is_some_and(|ld| ld.shape == Tcgen05LdShape::M16x32bx2);
+            let registers = (0..count)
+                .map(|index| format!("${index}"))
+                .collect::<Vec<_>>()
+                .join(",");
+            let constraints = std::iter::repeat_n("=r", count)
+                .chain(if has_half_split_offset {
+                    vec!["r", "n", "~{memory}"]
+                } else {
+                    vec!["r", "~{memory}"]
+                })
+                .collect::<Vec<_>>()
+                .join(",");
+            (
+                format!(
+                    "{}.{} {{{registers}}}, [${count}]{};",
+                    record.expected_ptx.mnemonic,
+                    record.expected_ptx.modifiers.join("."),
+                    if has_half_split_offset {
+                        format!(", ${}", count + 1)
+                    } else {
+                        String::new()
+                    }
+                ),
+                constraints,
+                Some(count),
+            )
+        }
+        Tcgen05Operation::St => {
+            let count = tcgen05_st_register_count(record);
+            let has_half_split_offset = record
+                .tcgen05
+                .as_ref()
+                .and_then(|tcgen05| tcgen05.st)
+                .is_some_and(|st| st.shape == Tcgen05LdShape::M16x32bx2);
+            let first_data = if has_half_split_offset { 2 } else { 1 };
+            let registers = (first_data..first_data + count)
+                .map(|index| format!("${index}"))
+                .collect::<Vec<_>>()
+                .join(",");
+            let constraints = std::iter::once("r")
+                .chain(has_half_split_offset.then_some("n"))
+                .chain(std::iter::repeat_n("r", count))
+                .chain(std::iter::once("~{memory}"))
+                .collect::<Vec<_>>()
+                .join(",");
+            (
+                format!(
+                    "{}.{} [$0], {}{{{registers}}};",
+                    record.expected_ptx.mnemonic,
+                    record.expected_ptx.modifiers.join("."),
+                    if has_half_split_offset {
+                        "$1, "
+                    } else {
+                        ""
+                    }
+                ),
+                constraints,
+                None,
+            )
+        }
+        Tcgen05Operation::LoadWait => (
+            "tcgen05.wait::ld.sync.aligned;".into(),
+            "~{memory}".into(),
+            None,
+        ),
+        Tcgen05Operation::StoreWait => (
+            "tcgen05.wait::st.sync.aligned;".into(),
+            "~{memory}".into(),
+            None,
+        ),
+        Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2 => {
+            let group = if operation == Tcgen05Operation::CommitMulticastCg2 {
+                2
+            } else {
+                1
+            };
+            (
+                format!("tcgen05.commit.cta_group::{group}.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;"),
+                "r,h,~{memory}".into(),
+                None,
+            )
+        }
+        Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2 => {
+            let group = if operation == Tcgen05Operation::ShiftDownCg2 {
+                2
+            } else {
+                1
+            };
+            (
+                format!("tcgen05.shift.cta_group::{group}.down [$0];"),
+                "r,~{memory}".into(),
+                None,
+            )
+        }
+        Tcgen05Operation::Mma => unreachable!("generic MMA uses attribute-driven lowering"),
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/importer.rs b/crates/cuda-intrinsics-gen/src/render/importer.rs
new file mode 100644
index 0000000000..d6f860d1f6
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/importer.rs
@@ -0,0 +1,3326 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    CatalogFile, CatalogIntrinsic, ClcOperation, ClusterBarrierMode, CpAsyncControlOperation,
+    CpAsyncMbarrierAdapter, CpAsyncSourceSize, DebugControlOperation, ExecutionControlOperation,
+    MbarrierBasicAdapter, MbarrierBasicOperation, MbarrierExtendedAdapter, PackedAtomicFormat,
+    PrmtMode, ReduxAdapter, RegisterMmaAdapter, Tcgen05LdShape, Tcgen05MmaForm,
+    Tcgen05MmaSelectorLayout, Tcgen05Operation, TmaAdapter, TmaOperation, VoteAdapter,
+    WarpBarrierAdapter, WarpShuffleAdapter, WgmmaControlMode,
+};
+use crate::render::common::{intrinsic_marker, rust_header, uses_identifier};
+use crate::render::families::dialect_nvvm_ops_import_candidates;
+use crate::render::families::{
+    active_masks, clc_intrinsics, cluster_barrier_attr, cluster_barriers, cluster_memory,
+    cp_async_controls, cp_async_copies, cp_async_mbarriers, debug_controls, dot_products,
+    elect_intrinsics, execution_controls, extended_minmax, extended_minmax_format_attr,
+    extended_minmax_nan_attr, extended_minmax_operation_attr, extended_minmax_subnormal_attr,
+    extended_minmax_xorsign_abs_attr, integer_minmaxes, ldmatrix, ldmatrix_attr_variants,
+    mbarrier_basics, mbarrier_extended, movmatrix, packed_alus, packed_atomics, packed_conversions,
+    prmts, redux, register_mma_attr_variants, register_mmas, scalar_arithmetic_arity,
+    scalar_arithmetic_format_attr, scalar_arithmetic_operation_attr,
+    scalar_arithmetic_rounding_attr, scalar_arithmetic_saturation_attr,
+    scalar_arithmetic_subnormal_attr, scalar_arithmetics, scalar_conversion_rounding_attr,
+    scalar_conversion_saturation_attr, scalar_conversions, scalar_math_format_attr,
+    scalar_math_operation_attr, scalar_math_precision_attr, scalar_math_subnormal_attr,
+    scalar_maths, sparse_mma_attr_variants, sparse_mma_import_adapter, sparse_mma_selector_error,
+    sparse_mmas, sregs, stmatrices, stmatrix_compatibility_name, stmatrix_variant, sync_intrinsics,
+    tcgen05_intrinsics, tcgen05_ld_register_count, tcgen05_mma_b_usage_attr, tcgen05_mma_form_attr,
+    tcgen05_mma_intrinsics, tcgen05_mma_kind_attr, tcgen05_st_register_count, tma_intrinsics,
+    vote_intrinsics, warp_barriers, warp_matches, warp_shuffles, wgmma_controls,
+};
+use crate::render::reference::{
+    render_compiler_path_patterns, render_inline_patterns, render_string_patterns,
+};
+use std::fmt::Write as _;
+use std::path::PathBuf;
+
+fn render_importer_pure_value_dispatch(
+    output: &mut String,
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+) {
+    let mut path_refs = vec![record.rust.canonical_path.as_str()];
+    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+    output.push_str("        ");
+    render_inline_patterns(output, &path_refs);
+    output.push_str(" => {\n");
+    writeln!(
+        output,
+        "            require_arity(name, args.len(), {}, &loc)?;",
+        record.rust.arguments.len()
+    )
+    .unwrap();
+    for index in 0..record.rust.arguments.len() {
+        let previous = if index == 0 { "prev_op" } else { "last_op" };
+        writeln!(
+            output,
+            "            let (arg{index}, last_op) = rvalue::translate_operand(\n                ctx, body, &args[{index}], value_map, block_ptr, {previous}, loc.clone(),\n            )?;"
+        )
+        .unwrap();
+    }
+    let arguments = (0..record.rust.arguments.len())
+        .map(|index| format!("arg{index}"))
+        .collect::<Vec<_>>()
+        .join(", ");
+    writeln!(
+        output,
+        "            let intrinsic = {}::build(ctx, {arguments});",
+        record.dialect.op_type
+    )
+    .unwrap();
+    output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
+    writeln!(
+        output,
+        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
+        intrinsic_marker(catalog, record)
+    )
+    .unwrap();
+    output.push_str(
+        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n            let result = intrinsic.deref(ctx).get_result(0);\n",
+    );
+    writeln!(
+        output,
+        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
+        format!("{} call without target block", record.rust.name)
+    )
+    .unwrap();
+    output.push_str("        }\n");
+}
+
+fn render_importer_scalar_conversion_dispatch(
+    output: &mut String,
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+) {
+    let mut path_refs = vec![record.rust.canonical_path.as_str()];
+    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+    output.push_str("        ");
+    render_inline_patterns(output, &path_refs);
+    output.push_str(" => {\n");
+    output.push_str(
+        "            require_arity(name, args.len(), 1, &loc)?;\n\
+                     let (value, last_op) = rvalue::translate_operand(\n\
+                         ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
+                     )?;\n",
+    );
+    writeln!(
+        output,
+        "            let intrinsic = ScalarConversionOp::build(ctx, value, {}, {});",
+        scalar_conversion_rounding_attr(record),
+        scalar_conversion_saturation_attr(record),
+    )
+    .unwrap();
+    output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
+    writeln!(
+        output,
+        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
+        intrinsic_marker(catalog, record)
+    )
+    .unwrap();
+    output.push_str(
+        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n\
+                     let result = intrinsic.deref(ctx).get_result(0);\n",
+    );
+    writeln!(
+        output,
+        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
+        format!("{} call without target block", record.rust.name)
+    )
+    .unwrap();
+    output.push_str("        }\n");
+}
+
+fn render_importer_scalar_arithmetic_dispatch(
+    output: &mut String,
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+) {
+    let mut path_refs = vec![record.rust.canonical_path.as_str()];
+    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+    output.push_str("        ");
+    render_inline_patterns(output, &path_refs);
+    output.push_str(" => {\n");
+    let arity = scalar_arithmetic_arity(record);
+    writeln!(
+        output,
+        "            require_arity(name, args.len(), {arity}, &loc)?;"
+    )
+    .unwrap();
+    for index in 0..arity {
+        let previous = if index == 0 { "prev_op" } else { "last_op" };
+        writeln!(
+            output,
+            "            let (arg{index}, last_op) = rvalue::translate_operand(\n                ctx, body, &args[{index}], value_map, block_ptr, {previous}, loc.clone(),\n            )?;"
+        )
+        .unwrap();
+    }
+    let arguments = (0..arity)
+        .map(|index| format!("arg{index}"))
+        .collect::<Vec<_>>()
+        .join(", ");
+    writeln!(
+        output,
+        "            let intrinsic = ScalarArithmeticOp::build(ctx, vec![{arguments}], {}, {}, {}, {}, {});",
+        scalar_arithmetic_format_attr(record),
+        scalar_arithmetic_operation_attr(record),
+        scalar_arithmetic_rounding_attr(record),
+        scalar_arithmetic_subnormal_attr(record),
+        scalar_arithmetic_saturation_attr(record),
+    )
+    .unwrap();
+    output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
+    writeln!(
+        output,
+        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
+        intrinsic_marker(catalog, record)
+    )
+    .unwrap();
+    output.push_str(
+        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n\
+                     let result = intrinsic.deref(ctx).get_result(0);\n",
+    );
+    writeln!(
+        output,
+        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
+        format!("{} call without target block", record.rust.name)
+    )
+    .unwrap();
+    output.push_str("        }\n");
+}
+
+fn render_importer_scalar_math_dispatch(
+    output: &mut String,
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+) {
+    let mut path_refs = vec![record.rust.canonical_path.as_str()];
+    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+    output.push_str("        ");
+    render_inline_patterns(output, &path_refs);
+    output.push_str(" => {\n");
+    writeln!(
+        output,
+        "            require_arity(name, args.len(), 1, &loc)?;"
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "            let (arg0, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;"
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "            let intrinsic = ScalarMathOp::build(ctx, arg0, {}, {}, {}, {});",
+        scalar_math_format_attr(record),
+        scalar_math_operation_attr(record),
+        scalar_math_precision_attr(record),
+        scalar_math_subnormal_attr(record),
+    )
+    .unwrap();
+    output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
+    writeln!(
+        output,
+        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
+        intrinsic_marker(catalog, record)
+    )
+    .unwrap();
+    output.push_str(
+        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n\
+                     let result = intrinsic.deref(ctx).get_result(0);\n",
+    );
+    writeln!(
+        output,
+        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
+        format!("{} call without target block", record.rust.name)
+    )
+    .unwrap();
+    output.push_str("        }\n");
+}
+
+fn render_importer_extended_minmax_dispatch(
+    output: &mut String,
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+) {
+    let mut path_refs = vec![record.rust.canonical_path.as_str()];
+    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+    output.push_str("        ");
+    render_inline_patterns(output, &path_refs);
+    output.push_str(" => {\n");
+    output.push_str(
+        "            require_arity(name, args.len(), 2, &loc)?;\n\
+                     let (a, last_op) = rvalue::translate_operand(\n\
+                         ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
+                     )?;\n\
+                     let (b, last_op) = rvalue::translate_operand(\n\
+                         ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n\
+                     )?;\n",
+    );
+    writeln!(
+        output,
+        "            let intrinsic = ExtendedMinMaxOp::build(ctx, a, b, {}, {}, {}, {}, {});",
+        extended_minmax_format_attr(record),
+        extended_minmax_operation_attr(record),
+        extended_minmax_subnormal_attr(record),
+        extended_minmax_nan_attr(record),
+        extended_minmax_xorsign_abs_attr(record),
+    )
+    .unwrap();
+    output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
+    writeln!(
+        output,
+        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
+        intrinsic_marker(catalog, record)
+    )
+    .unwrap();
+    output.push_str(
+        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n\
+                     let result = intrinsic.deref(ctx).get_result(0);\n",
+    );
+    writeln!(
+        output,
+        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
+        format!("{} call without target block", record.rust.name)
+    )
+    .unwrap();
+    output.push_str("        }\n");
+}
+
+fn render_importer_elect_dispatch(
+    output: &mut String,
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+) {
+    let mut path_refs = vec![record.rust.canonical_path.as_str()];
+    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+    output.push_str("        ");
+    render_inline_patterns(output, &path_refs);
+    output.push_str(" => {\n");
+    output.push_str(
+        "            require_arity(name, args.len(), 1, &loc)?;\n\
+         \n\
+                     let tuple_ty = crate::translator::types::translate_destination_type(\n\
+                         ctx, body, destination, &loc,\n\
+                     )?;\n\
+                     let (leader_ty, elected_ty) = {\n\
+                         let ty = tuple_ty.deref(ctx);\n\
+                         match ty.downcast_ref::<MirTupleType>() {\n\
+                             Some(tuple) if tuple.get_types().len() == 2 => {\n\
+                                 (tuple.get_types()[0], tuple.get_types()[1])\n\
+                             }\n\
+                             _ => {\n\
+                                 return input_err!(\n\
+                                     loc.clone(),\n\
+                                     TranslationErr::unsupported(\n\
+                                         \"warp::elect_sync destination must be a (u32, bool) tuple\"\n\
+                                             .to_owned()\n\
+                                     )\n\
+                                 );\n\
+                             }\n\
+                         }\n\
+                     };\n\
+                     let (mask, last_op) = rvalue::translate_operand(\n\
+                         ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
+                     )?;\n",
+    );
+    writeln!(
+        output,
+        "            let elect = Operation::new(\n                ctx, {}::get_concrete_op_info(), vec![leader_ty, elected_ty],\n                vec![mask], vec![], 0,\n            );",
+        record.dialect.op_type
+    )
+    .unwrap();
+    output.push_str("            elect.deref_mut(ctx).set_loc(loc.clone());\n");
+    writeln!(
+        output,
+        "            helpers::set_generated_intrinsic_marker(ctx, elect, {:?});",
+        intrinsic_marker(catalog, record)
+    )
+    .unwrap();
+    output.push_str(
+        "            helpers::insert_op(ctx, elect, block_ptr, last_op);\n\
+                     let leader = elect.deref(ctx).get_result(0);\n\
+                     let elected = elect.deref(ctx).get_result(1);\n\
+                     let tuple = Operation::new(\n\
+                         ctx, MirConstructTupleOp::get_concrete_op_info(), vec![tuple_ty],\n\
+                         vec![leader, elected],\n\
+                         vec![], 0,\n\
+                     );\n\
+                     tuple.deref_mut(ctx).set_loc(loc.clone());\n\
+                     tuple.insert_after(ctx, elect);\n\
+                     let result = tuple.deref(ctx).get_result(0);\n",
+    );
+    writeln!(
+        output,
+        "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, tuple, value_map, block_map, loc,\n                {:?},\n            )?))",
+        format!("{} call without target block", record.rust.name)
+    )
+    .unwrap();
+    output.push_str("        }\n");
+}
+
+fn render_importer_tcgen05_mma_dispatch(
+    output: &mut String,
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+) {
+    let mma = record
+        .tcgen05
+        .as_ref()
+        .and_then(|tcgen05| tcgen05.mma.as_ref())
+        .expect("tcgen05 MMA record");
+    let mut path_refs = vec![record.rust.canonical_path.as_str()];
+    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+    output.push_str("        ");
+    render_inline_patterns(output, &path_refs);
+    output.push_str(" => {\n");
+    writeln!(
+        output,
+        "            require_arity(name, args.len(), {}, &loc)?;",
+        record.rust.arguments.len()
+    )
+    .unwrap();
+
+    let runtime_indices = if mma.alias.is_some() && mma.form == Tcgen05MmaForm::WsTensor {
+        vec![0, 1, 3, 4, 5]
+    } else if mma.alias.is_some() {
+        (0..record.rust.arguments.len()).collect()
+    } else {
+        let selector_indices = match mma.selector_layout {
+            Tcgen05MmaSelectorLayout::Base {
+                kind_argument,
+                cta_group_argument,
+                collector_a_argument,
+                ..
+            } => [
+                kind_argument as usize,
+                cta_group_argument as usize,
+                collector_a_argument as usize,
+            ],
+            Tcgen05MmaSelectorLayout::WarpSpecialized {
+                kind_argument,
+                b_buffer_argument,
+                b_usage_argument,
+            } => [
+                kind_argument as usize,
+                b_buffer_argument as usize,
+                b_usage_argument as usize,
+            ],
+        };
+        (0..record.rust.arguments.len())
+            .filter(|index| !selector_indices.contains(index))
+            .collect()
+    };
+    writeln!(
+        output,
+        "            let runtime_indices: &[usize] = &{runtime_indices:?};"
+    )
+    .unwrap();
+    output.push_str(
+        "            let mut last_op = prev_op;\n            let mut operands = Vec::with_capacity(runtime_indices.len());\n            for &index in runtime_indices {\n                let (value, translated) = rvalue::translate_operand(\n                    ctx, body, &args[index], value_map, block_ptr, last_op, loc.clone(),\n                )?;\n                last_op = translated;\n                operands.push(value);\n            }\n",
+    );
+
+    if let Some(fixed) = mma.fixed_selectors {
+        writeln!(
+            output,
+            "            let kind = {};",
+            tcgen05_mma_kind_attr(fixed.kind)
+        )
+        .unwrap();
+        match mma.selector_layout {
+            Tcgen05MmaSelectorLayout::Base { .. } => {
+                output.push_str(
+                    "            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;\n            let collector_a = Tcgen05MmaCollectorAAttr::Discard;\n",
+                );
+            }
+            Tcgen05MmaSelectorLayout::WarpSpecialized { .. } => {
+                let b_buffer = match fixed.b_buffer {
+                    0 => "Tcgen05MmaBBufferAttr::B0",
+                    1 => "Tcgen05MmaBBufferAttr::B1",
+                    2 => "Tcgen05MmaBBufferAttr::B2",
+                    3 => "Tcgen05MmaBBufferAttr::B3",
+                    _ => panic!("admitted tcgen05 MMA B buffer"),
+                };
+                writeln!(output, "            let b_buffer = {b_buffer};").unwrap();
+                writeln!(
+                    output,
+                    "            let b_usage = {};",
+                    tcgen05_mma_b_usage_attr(fixed.b_usage)
+                )
+                .unwrap();
+            }
+        }
+    } else {
+        let (kind_argument, second_argument, third_argument) = match mma.selector_layout {
+            Tcgen05MmaSelectorLayout::Base {
+                kind_argument,
+                cta_group_argument,
+                collector_a_argument,
+                ..
+            } => (kind_argument, cta_group_argument, collector_a_argument),
+            Tcgen05MmaSelectorLayout::WarpSpecialized {
+                kind_argument,
+                b_buffer_argument,
+                b_usage_argument,
+            } => (kind_argument, b_buffer_argument, b_usage_argument),
+        };
+        writeln!(
+            output,
+            "            let kind = match generated_tcgen05_mma_selector(args.get({kind_argument}usize)) {{\n                Some(0) => Tcgen05MmaKindAttr::F16,\n                Some(1) => Tcgen05MmaKindAttr::Tf32,\n                Some(2) => Tcgen05MmaKindAttr::F8f6f4,\n                Some(3) => Tcgen05MmaKindAttr::I8,\n                _ => return input_err!(loc.clone(), TranslationErr::unsupported(\"tcgen05 MMA kind must be a compile-time u32 constant in 0..=3\".to_owned())),\n            }};"
+        )
+        .unwrap();
+        match mma.selector_layout {
+            Tcgen05MmaSelectorLayout::Base {
+                collector_a_upper_exclusive,
+                ..
+            } => {
+                writeln!(
+                    output,
+                    "            let cta_group = match generated_tcgen05_mma_selector(args.get({second_argument}usize)) {{\n                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,\n                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,\n                _ => {{\n                    return input_err!(\n                        loc.clone(),\n                        TranslationErr::unsupported(\n                            \"tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2\"\n                                .to_owned()\n                        )\n                    );\n                }}\n            }};"
+                )
+                .unwrap();
+                let collector_arms = if collector_a_upper_exclusive == 2 {
+                    "                Some(0) => Tcgen05MmaCollectorAAttr::Discard,\n                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,\n"
+                } else {
+                    "                Some(0) => Tcgen05MmaCollectorAAttr::Discard,\n                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,\n                Some(2) => Tcgen05MmaCollectorAAttr::Fill,\n                Some(3) => Tcgen05MmaCollectorAAttr::Use,\n"
+                };
+                writeln!(
+                    output,
+                    "            let collector_a = match generated_tcgen05_mma_selector(args.get({third_argument}usize)) {{\n{collector_arms}                _ => return input_err!(loc.clone(), TranslationErr::unsupported(\"tcgen05 MMA collector-A selector is outside its closed range\".to_owned())),\n            }};"
+                )
+                .unwrap();
+            }
+            Tcgen05MmaSelectorLayout::WarpSpecialized { .. } => {
+                writeln!(
+                    output,
+                    "            let b_buffer = match generated_tcgen05_mma_selector(args.get({second_argument}usize)) {{\n                Some(0) => Tcgen05MmaBBufferAttr::B0,\n                Some(1) => Tcgen05MmaBBufferAttr::B1,\n                Some(2) => Tcgen05MmaBBufferAttr::B2,\n                Some(3) => Tcgen05MmaBBufferAttr::B3,\n                _ => return input_err!(loc.clone(), TranslationErr::unsupported(\"tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3\".to_owned())),\n            }};"
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "            let b_usage = match generated_tcgen05_mma_selector(args.get({third_argument}usize)) {{\n                Some(0) => Tcgen05MmaBUsageAttr::Discard,\n                Some(1) => Tcgen05MmaBUsageAttr::LastUse,\n                Some(2) => Tcgen05MmaBUsageAttr::Fill,\n                Some(3) => Tcgen05MmaBUsageAttr::Use,\n                _ => return input_err!(loc.clone(), TranslationErr::unsupported(\"tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3\".to_owned())),\n            }};"
+                )
+                .unwrap();
+            }
+        }
+    }
+
+    output.push_str(
+        "            let intrinsic = Operation::new(ctx, Tcgen05MmaOp::get_concrete_op_info(), vec![], operands, vec![], 0);\n            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n            let mma_op = Tcgen05MmaOp::new(intrinsic);\n",
+    );
+    writeln!(
+        output,
+        "            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, {});",
+        tcgen05_mma_form_attr(mma.form)
+    )
+    .unwrap();
+    output.push_str("            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);\n");
+    match mma.selector_layout {
+        Tcgen05MmaSelectorLayout::Base { .. } => output.push_str(
+            "            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);\n            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);\n",
+        ),
+        Tcgen05MmaSelectorLayout::WarpSpecialized { .. } => output.push_str(
+            "            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);\n            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);\n",
+        ),
+    }
+    writeln!(
+        output,
+        "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
+        intrinsic_marker(catalog, record)
+    )
+    .unwrap();
+    output.push_str(
+        "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, intrinsic, block_map, loc)))\n            } else {\n",
+    );
+    writeln!(
+        output,
+        "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+        format!("{} call without target block", record.rust.name)
+    )
+    .unwrap();
+    output.push_str("            }\n        }\n");
+}
+
+fn render_importer_tcgen05_non_mma_dispatch(
+    output: &mut String,
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+) {
+    let tcgen05 = record.tcgen05.as_ref().unwrap();
+    let operation = tcgen05.operation;
+    let has_half_split_offset = tcgen05
+        .ld
+        .is_some_and(|ld| ld.shape == Tcgen05LdShape::M16x32bx2)
+        || tcgen05
+            .st
+            .is_some_and(|st| st.shape == Tcgen05LdShape::M16x32bx2);
+    let mut path_refs = vec![record.rust.canonical_path.as_str()];
+    path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+    output.push_str("        ");
+    render_inline_patterns(output, &path_refs);
+    output.push_str(" => {\n");
+    if operation == Tcgen05Operation::St {
+        let count = tcgen05_st_register_count(record);
+        writeln!(
+            output,
+            "            require_arity(name, args.len(), {}, &loc)?;",
+            if has_half_split_offset { 3 } else { 2 }
+        )
+        .unwrap();
+        if has_half_split_offset {
+            output.push_str(
+                    "            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"tcgen05 16x32bx2 half-split offset must be a compile-time constant\".to_owned()\n                    )\n                );\n            }\n",
+                );
+        }
+        writeln!(
+                output,
+                "            let (operands, last_op) = import_generated_tcgen05_store_operands(\n                ctx, body, args, {count}, {has_half_split_offset}, block_ptr, prev_op, value_map, loc.clone(),\n            )?;"
+            )
+            .unwrap();
+        writeln!(
+                output,
+                "            let intrinsic = Operation::new(ctx, {}::get_concrete_op_info(), vec![], operands, vec![], 0);",
+                record.dialect.op_type
+            )
+            .unwrap();
+        output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+                "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, intrinsic, block_map, loc)))\n            } else {\n",
+            );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("            }\n        }\n");
+        return;
+    }
+    let arity = record.dialect.operands.len();
+    writeln!(
+        output,
+        "            require_arity(name, args.len(), {arity}, &loc)?;"
+    )
+    .unwrap();
+    if has_half_split_offset {
+        output.push_str(
+                "            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"tcgen05 16x32bx2 half-split offset must be a compile-time constant\".to_owned()\n                    )\n                );\n            }\n",
+            );
+    }
+    output.push_str(
+            "            let mut last_op = prev_op;\n            let mut operands = Vec::with_capacity(args.len());\n            for arg in args {\n                let (value, translated) = rvalue::translate_operand(\n                    ctx, body, arg, value_map, block_ptr, last_op, loc.clone(),\n                )?;\n                last_op = translated;\n                operands.push(value);\n            }\n",
+        );
+    if has_half_split_offset {
+        output.push_str(
+                "            if operands.get(1).and_then(|value| value.defining_op()).and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx)).is_none() {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"tcgen05 16x32bx2 half-split offset must lower to a constant\".to_owned()\n                    )\n                );\n            }\n",
+            );
+    }
+    let load = match operation {
+        Tcgen05Operation::Ld16x256bX8Pure => Some((32, "FP32Type::get(ctx).into()")),
+        Tcgen05Operation::Ld16x256bPure => Some((4, "FP32Type::get(ctx).into()")),
+        Tcgen05Operation::Ld => Some((
+            tcgen05_ld_register_count(record),
+            "IntegerType::get(ctx, 32, Signedness::Unsigned).into()",
+        )),
+        _ => None,
+    };
+    if let Some((count, result_ty)) = load {
+        writeln!(
+            output,
+            "            let result_ty: TypeHandle = {result_ty};"
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "            let result_types = (0..{count}).map(|_| result_ty).collect();"
+        )
+        .unwrap();
+        writeln!(
+                    output,
+                    "            let intrinsic = Operation::new(ctx, {}::get_concrete_op_info(), result_types, operands, vec![], 0);",
+                    record.dialect.op_type
+                )
+                .unwrap();
+        output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str("            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n");
+        if count == 1 {
+            output.push_str(
+                        "            let result = intrinsic.deref(ctx).get_result(0);\n            let value = intrinsic;\n",
+                    );
+        } else {
+            writeln!(
+                        output,
+                        "            let results: Vec<Value> = (0..{count}).map(|index| intrinsic.deref(ctx).get_result(index)).collect();"
+                    )
+                    .unwrap();
+            writeln!(
+                output,
+                "            let array_ty = MirArrayType::get(ctx, result_ty, {count});"
+            )
+            .unwrap();
+            output.push_str(
+                        "            let array = Operation::new(ctx, MirConstructArrayOp::get_concrete_op_info(), vec![array_ty.into()], results, vec![], 0);\n            array.deref_mut(ctx).set_loc(loc.clone());\n            array.insert_after(ctx, intrinsic);\n            let destination_rust_ty = match destination.ty(body.locals()) {\n                Ok(ty) => ty,\n                Err(error) => {\n                    return input_err!(\n                        loc,\n                        TranslationErr::unsupported(format!(\n                            \"failed to resolve destination type for intrinsic result: {error:?}\"\n                        ))\n                    );\n                }\n            };\n            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;\n            let array_result = array.deref(ctx).get_result(0);\n            let (result, value) = if destination_ty == array_result.get_type(ctx) {\n                (array_result, array)\n            } else {\n                let value = Operation::new(ctx, MirConstructStructOp::get_concrete_op_info(), vec![destination_ty], vec![array_result], vec![], 0);\n                value.deref_mut(ctx).set_loc(loc.clone());\n                value.insert_after(ctx, array);\n                (value.deref(ctx).get_result(0), value)\n            };\n            helpers::set_compiler_result_bundle_marker(ctx, value);\n",
+                    );
+        }
+        writeln!(
+                    output,
+                    "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, value, value_map, block_map, loc,\n                {:?},\n            )?))",
+                    format!("{} call without target block", record.rust.name)
+                )
+                .unwrap();
+    } else {
+        writeln!(
+                    output,
+                    "            let intrinsic = Operation::new(ctx, {}::get_concrete_op_info(), vec![], operands, vec![], 0);",
+                    record.dialect.op_type
+                )
+                .unwrap();
+        output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+                    "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, intrinsic, block_map, loc)))\n            } else {\n",
+                );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("            }\n");
+    }
+    output.push_str("        }\n");
+}
+
+fn append_importer_classification(output: &mut String, catalog: &CatalogFile) {
+    writeln!(
+        output,
+        "pub const GENERATED_INTRINSIC_ABI: u32 = {};",
+        catalog.intrinsic_abi
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "pub const GENERATED_INTRINSIC_ABI_NAMESPACE: &str = {:?};\n",
+        format!("__cuda_oxide_intrinsic_abi_v{}", catalog.intrinsic_abi)
+    )
+    .unwrap();
+    output.push_str(
+        "#[derive(Debug, Clone, PartialEq, Eq)]\npub enum RawIntrinsicIdentity {\n    NotRawCrate,\n    Known(String),\n    UnsupportedAbi(String),\n    UnknownId(String),\n}\n\n/// Classify the unrewritten raw intrinsic DefPath. rustc's ordinary name\n/// printer may prefer a public re-export path, which is source API rather than ABI.\npub fn classify_raw_intrinsic(fn_def: FnDef) -> RawIntrinsicIdentity {\n    let crate_name = fn_def.krate().name.to_string();\n    if !matches!(crate_name.as_str(), \"cuda_intrinsics\" | \"cuda-intrinsics\") {\n        return RawIntrinsicIdentity::NotRawCrate;\n    }\n\n    let mut segments = Vec::new();\n    let mut current = Some(fn_def.def_id());\n    while let Some(def_id) = current {\n        let printed = def_id.name();\n        let segment = printed.as_str().rsplit(\"::\").next().unwrap_or_default();\n        if segment != crate_name {\n            segments.push(segment.to_owned());\n        }\n        current = def_id.parent();\n    }\n    segments.reverse();\n    classify_raw_intrinsic_path(&crate_name, format!(\"{crate_name}::{}\", segments.join(\"::\")))\n}\n\nfn classify_raw_intrinsic_path(crate_name: &str, path: String) -> RawIntrinsicIdentity {\n    if !matches!(crate_name, \"cuda_intrinsics\" | \"cuda-intrinsics\") {\n        return RawIntrinsicIdentity::NotRawCrate;\n    }\n    if is_raw_generated_intrinsic_path(&path) {\n        return RawIntrinsicIdentity::Known(path);\n    }\n    let namespace = path.split(\"::\").nth(1).unwrap_or_default();\n    if namespace.starts_with(\"__cuda_oxide_intrinsic_abi_v\")\n        && namespace != GENERATED_INTRINSIC_ABI_NAMESPACE\n    {\n        RawIntrinsicIdentity::UnsupportedAbi(path)\n    } else {\n        RawIntrinsicIdentity::UnknownId(path)\n    }\n}\n\npub fn require_supported_raw_intrinsic(\n    fn_def: FnDef,\n    loc: &Location,\n) -> TranslationResult<Option<String>> {\n    match classify_raw_intrinsic(fn_def) {\n        RawIntrinsicIdentity::NotRawCrate => Ok(None),\n        RawIntrinsicIdentity::Known(path) => Ok(Some(path)),\n        RawIntrinsicIdentity::UnsupportedAbi(path) => input_err!(\n            loc.clone(),\n            TranslationErr::unsupported(format!(\n                \"cuda-intrinsics ABI mismatch: `{path}` uses an unsupported intrinsic ABI; this compiler supports ABI v{GENERATED_INTRINSIC_ABI}\"\n            ))\n        ),\n        RawIntrinsicIdentity::UnknownId(path) => input_err!(\n            loc.clone(),\n            TranslationErr::unsupported(format!(\n                \"cuda-intrinsics ABI mismatch: `{path}` is not a known intrinsic ID in ABI v{GENERATED_INTRINSIC_ABI}\"\n            ))\n        ),\n    }\n}\n\n",
+    );
+    output
+        .push_str("pub fn is_generated_intrinsic_path(name: &str) -> bool {\n    matches!(name,\n");
+    render_compiler_path_patterns(output, catalog, "        ");
+    output.push_str("    )\n}\n\npub fn is_raw_generated_intrinsic_path(name: &str) -> bool {\n    matches!(name,\n");
+    let raw_paths: Vec<_> = catalog
+        .intrinsics
+        .iter()
+        .map(|record| record.rust.canonical_path.as_str())
+        .collect();
+    render_string_patterns(output, &raw_paths, "        ");
+    // Test-only. The dispatch arms rendered below carry each marker as a
+    // literal, and the op-name-keyed lookup the compiler actually calls lives
+    // in `cuda-oxide-codegen`; nothing outside this file's own generated tests
+    // reads this path-keyed table. Gate it rather than leave a 2000-line match
+    // sitting unreferenced in the compiler.
+    output.push_str("    )\n}\n\n#[cfg(test)]\npub fn generated_intrinsic_marker(name: &str) -> Option<&'static str> {\n    match name {\n");
+    for record in &catalog.intrinsics {
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(output, &path_refs);
+        writeln!(output, " => Some({:?}),", intrinsic_marker(catalog, record)).unwrap();
+    }
+    output.push_str("        _ => None,\n    }\n}\n\n");
+}
+
+fn sreg_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in sregs(catalog) {
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        writeln!(
+            output,
+            "            require_arity(name, args.len(), 0, &loc)?;"
+        )
+        .unwrap();
+        let helper = if record.scalar_width() == Some(64) {
+            "emit_generated_nvvm_intrinsic_u64"
+        } else {
+            "emit_generated_nvvm_intrinsic"
+        };
+        writeln!(output, "            Ok(Some(helpers::{helper}(").unwrap();
+        writeln!(
+            output,
+            "                ctx, {}::get_concrete_op_info(), {:?}, destination, target, block_ptr,",
+            record.dialect.op_type,
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "                prev_op, value_map, block_map, loc,\n            )?))\n        }\n",
+        );
+    }
+    output
+}
+
+fn active_mask_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in active_masks(catalog) {
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 0, &loc)?;\n");
+        writeln!(
+            output,
+            "            let active_mask = {}::build(ctx);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            active_mask.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, active_mask, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, active_mask, block_ptr, prev_op);\n            let result = active_mask.deref(ctx).get_result(0);\n",
+        );
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, active_mask, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn ldmatrix_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in ldmatrix(catalog) {
+        let (shape, multiplicity, layout, element, state_space) = ldmatrix_attr_variants(record);
+        let register_count = record.ldmatrix.as_ref().unwrap().variant.register_count();
+        output.push_str("        ");
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 1, &loc)?;\n");
+        output.push_str(
+            "            let (address, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+        );
+        writeln!(
+            output,
+            "            let load = LdmatrixOp::build(ctx, address, {shape}, {multiplicity}, {layout}, {element}, {state_space});"
+        )
+        .unwrap();
+        output.push_str("            load.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, load, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str("            helpers::insert_op(ctx, load, block_ptr, last_op);\n");
+        if register_count == 1 {
+            output.push_str("            let value = load.deref(ctx).get_result(0);\n");
+            output.push_str("            let last_op = load;\n");
+        } else {
+            writeln!(
+                output,
+                "            let (value, last_op) = helpers::bundle_generated_u32_results_as_array(ctx, load, {register_count}, loc.clone());"
+            )
+            .unwrap();
+        }
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, value, target, block_ptr, last_op, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn stmatrix_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in stmatrices(catalog) {
+        let (multiplicity, _) = stmatrix_variant(record).expect("stmatrix variant");
+        let arity = multiplicity.register_count() + 1;
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        writeln!(
+            output,
+            "            require_arity(name, args.len(), {arity}, &loc)?;"
+        )
+        .unwrap();
+        output.push_str(
+            "            let mut last_op = prev_op;\n            let mut operands = Vec::with_capacity(args.len());\n            for arg in args {\n                let (value, translated) = rvalue::translate_operand(\n                    ctx, body, arg, value_map, block_ptr, last_op, loc.clone(),\n                )?;\n                last_op = translated;\n                operands.push(value);\n            }\n",
+        );
+        writeln!(
+            output,
+            "            let store = Operation::new(ctx, {}::get_concrete_op_info(), vec![], operands, vec![], 0);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            store.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, store, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, store, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, store, block_map, loc)))\n            } else {\n",
+        );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!(
+                "{} call without target block",
+                stmatrix_compatibility_name(record)
+            )
+        )
+        .unwrap();
+        output.push_str("            }\n        }\n");
+    }
+    output
+}
+
+fn register_mma_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in register_mmas(catalog) {
+        let adapter = match record.register_mma.as_ref().unwrap().adapter {
+            RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32 => {
+                "GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32"
+            }
+            RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => {
+                "GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32"
+            }
+            RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32 => {
+                "GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32"
+            }
+            RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32 => {
+                "GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32"
+            }
+            RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 => {
+                "GeneratedMmaImportAdapter::C2F64A1F64B1F64ToD2F64"
+            }
+            RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32 => {
+                "GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32"
+            }
+            RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32 => {
+                "GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32"
+            }
+            RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => {
+                "GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32"
+            }
+            RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => {
+                "GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32"
+            }
+        };
+        let (
+            shape,
+            operation,
+            kind,
+            accumulator,
+            a_element,
+            b_element,
+            a_layout,
+            b_layout,
+            overflow,
+        ) = register_mma_attr_variants(record);
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        let arity = record.rust.arguments.len();
+        writeln!(
+            output,
+            "            require_arity(name, args.len(), {arity}, &loc)?;"
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(ctx, body, args, block_ptr, prev_op, value_map, loc.clone(), {adapter})?;"
+        )
+        .unwrap();
+        output.push_str(
+            "            let mma = Operation::new(ctx, RegisterMmaOp::get_concrete_op_info(), vec![result_ty; result_count], operands, vec![], 0);\n            mma.deref_mut(ctx).set_loc(loc.clone());\n            let mma = RegisterMmaOp::new(mma);\n",
+        );
+        writeln!(
+            output,
+            "            mma.set_attr_nvvm_register_mma_shape(ctx, {shape});\n            mma.set_attr_nvvm_register_mma_operation(ctx, {operation});\n            mma.set_attr_nvvm_register_mma_kind(ctx, {kind});\n            mma.set_attr_nvvm_register_mma_accumulator(ctx, {accumulator});\n            mma.set_attr_nvvm_register_mma_a_element(ctx, {a_element});\n            mma.set_attr_nvvm_register_mma_b_element(ctx, {b_element});\n            mma.set_attr_nvvm_register_mma_a_layout(ctx, {a_layout});\n            mma.set_attr_nvvm_register_mma_b_layout(ctx, {b_layout});\n            mma.set_attr_nvvm_register_mma_overflow(ctx, {overflow});"
+        )
+        .unwrap();
+        output.push_str("            let mma = mma.get_operation();\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, mma, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));\n            let (result, last_op) = bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());\n",
+        );
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, last_op, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn sparse_mma_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in sparse_mmas(catalog) {
+        let (
+            shape,
+            accumulator,
+            a_element,
+            b_element,
+            a_layout,
+            b_layout,
+            overflow,
+            metadata,
+            selector,
+        ) = sparse_mma_attr_variants(record);
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 5, &loc)?;\n");
+        writeln!(
+            output,
+            "            if !matches!(&args[4], mir::Operand::Constant(_)) {{\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        {:?}.to_owned()\n                    )\n                );\n            }}",
+            sparse_mma_selector_error(record)
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(ctx, body, args, block_ptr, prev_op, value_map, loc.clone(), {})?;",
+            sparse_mma_import_adapter(record)
+        )
+        .unwrap();
+        output.push_str(
+            "            let (metadata, last_op) = rvalue::translate_operand(\n                ctx, body, &args[3], value_map, block_ptr, Some(last_op), loc.clone(),\n            )?;\n            operands.push(metadata);\n            let (selector_value, last_op) = rvalue::translate_operand(\n                ctx, body, &args[4], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n            operands.push(selector_value);\n",
+        );
+        output.push_str(
+            "            let mma = Operation::new(ctx, SparseMmaOp::get_concrete_op_info(), vec![result_ty; result_count], operands, vec![], 0);\n            mma.deref_mut(ctx).set_loc(loc.clone());\n            let mma = SparseMmaOp::new(mma);\n",
+        );
+        writeln!(
+            output,
+            "            mma.set_attr_nvvm_sparse_mma_shape(ctx, {shape});\n            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, {accumulator});\n            mma.set_attr_nvvm_sparse_mma_a_element(ctx, {a_element});\n            mma.set_attr_nvvm_sparse_mma_b_element(ctx, {b_element});\n            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, {a_layout});\n            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, {b_layout});\n            mma.set_attr_nvvm_sparse_mma_overflow(ctx, {overflow});\n            mma.set_attr_nvvm_sparse_mma_metadata(ctx, {metadata});\n            mma.set_attr_nvvm_sparse_mma_selector(ctx, {selector});"
+        )
+        .unwrap();
+        output.push_str("            let mma = mma.get_operation();\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, mma, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, mma, block_ptr, last_op);\n            let (result, last_op) = bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());\n",
+        );
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, last_op, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn packed_atomic_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in packed_atomics(catalog) {
+        let format = match record.packed_atomic.as_ref().unwrap().format {
+            PackedAtomicFormat::F16x2 => "PackedAtomicFormatAttr::F16x2",
+            PackedAtomicFormat::Bf16x2 => "PackedAtomicFormatAttr::Bf16x2",
+        };
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 2, &loc)?;\n");
+        output.push_str(
+            "            let (address, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+        );
+        output.push_str(
+            "            let (addend, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+        );
+        writeln!(
+            output,
+            "            let atom = PackedAtomicAddOp::build(ctx, address, addend, {format});"
+        )
+        .unwrap();
+        output.push_str("            atom.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, atom, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str("            helpers::insert_op(ctx, atom, block_ptr, last_op);\n");
+        output.push_str("            let value = atom.deref(ctx).get_result(0);\n");
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, value, target, block_ptr, atom, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn redux_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in redux(catalog) {
+        debug_assert_eq!(
+            record.redux.as_ref().unwrap().adapter,
+            ReduxAdapter::MaskValueToSourceMemberMask
+        );
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 2, &loc)?;\n");
+        output.push_str(
+            "            let (member_mask, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+        );
+        output.push_str(
+            "            let (value, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+        );
+        writeln!(
+            output,
+            "            let reduction = {}::build(ctx, member_mask, value);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            reduction.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, reduction, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, reduction, block_ptr, last_op);\n            let result = reduction.deref(ctx).get_result(0);\n",
+        );
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, reduction, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn vote_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in vote_intrinsics(catalog) {
+        debug_assert_eq!(
+            record.vote.as_ref().unwrap().adapter,
+            VoteAdapter::DirectMaskPredicate
+        );
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 2, &loc)?;\n");
+        output.push_str(
+            "            let (member_mask, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+        );
+        output.push_str(
+            "            let (predicate, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+        );
+        writeln!(
+            output,
+            "            let vote = {}::build(ctx, member_mask, predicate);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            vote.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, vote, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, vote, block_ptr, last_op);\n            let result = vote.deref(ctx).get_result(0);\n",
+        );
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, vote, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn warp_match_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in warp_matches(catalog) {
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 2, &loc)?;\n");
+        output.push_str(
+            "            let (member_mask, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+        );
+        output.push_str(
+            "            let (value, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+        );
+        writeln!(
+            output,
+            "            let warp_match = {}::build(ctx, member_mask, value);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            warp_match.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, warp_match, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, warp_match, block_ptr, last_op);\n            let result = warp_match.deref(ctx).get_result(0);\n",
+        );
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, warp_match, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn elect_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in elect_intrinsics(catalog) {
+        render_importer_elect_dispatch(&mut output, catalog, record);
+    }
+    output
+}
+
+fn warp_barrier_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in warp_barriers(catalog) {
+        debug_assert_eq!(
+            record.warp_barrier.as_ref().unwrap().adapter,
+            WarpBarrierAdapter::DirectMemberMask
+        );
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 1, &loc)?;\n");
+        output.push_str(
+            "            let (member_mask, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+        );
+        writeln!(
+            output,
+            "            let barrier = {}::build(ctx, member_mask);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            barrier.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, barrier, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, barrier, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, barrier, block_map, loc)))\n            } else {\n",
+        );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("            }\n        }\n");
+    }
+    output
+}
+
+fn warp_shuffle_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in warp_shuffles(catalog) {
+        debug_assert!(matches!(
+            record.warp_shuffle.as_ref().unwrap().adapter,
+            WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp
+                | WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
+        ));
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 3, &loc)?;\n");
+        output.push_str(
+            "            let (member_mask, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+        );
+        output.push_str(
+            "            let (value, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+        );
+        output.push_str(
+            "            let (lane_or_delta, last_op) = rvalue::translate_operand(\n                ctx, body, &args[2], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+        );
+        writeln!(
+            output,
+            "            let shuffle = {}::build(ctx, member_mask, value, lane_or_delta);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            shuffle.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, shuffle, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, shuffle, block_ptr, last_op);\n            let result = shuffle.deref(ctx).get_result(0);\n",
+        );
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, shuffle, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn dotprod_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in dot_products(catalog) {
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 3, &loc)?;\n");
+        output.push_str(
+            "            let (a, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+        );
+        output.push_str(
+            "            let (b, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+        );
+        output.push_str(
+            "            let (c, last_op) = rvalue::translate_operand(\n                ctx, body, &args[2], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+        );
+        writeln!(
+            output,
+            "            let dot = {}::build(ctx, a, b, c);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            dot.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, dot, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, dot, block_ptr, last_op);\n            let result = dot.deref(ctx).get_result(0);\n",
+        );
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, dot, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn packed_alu_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in packed_alus(catalog) {
+        render_importer_pure_value_dispatch(&mut output, catalog, record);
+    }
+    output
+}
+
+fn integer_minmax_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in integer_minmaxes(catalog) {
+        render_importer_pure_value_dispatch(&mut output, catalog, record);
+    }
+    output
+}
+
+fn packed_conversion_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in packed_conversions(catalog) {
+        render_importer_pure_value_dispatch(&mut output, catalog, record);
+    }
+    output
+}
+
+fn scalar_conversion_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in scalar_conversions(catalog) {
+        render_importer_scalar_conversion_dispatch(&mut output, catalog, record);
+    }
+    output
+}
+
+fn scalar_arithmetic_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in scalar_arithmetics(catalog) {
+        render_importer_scalar_arithmetic_dispatch(&mut output, catalog, record);
+    }
+    output
+}
+
+fn scalar_math_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in scalar_maths(catalog) {
+        render_importer_scalar_math_dispatch(&mut output, catalog, record);
+    }
+    output
+}
+
+fn extended_minmax_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in extended_minmax(catalog) {
+        render_importer_extended_minmax_dispatch(&mut output, catalog, record);
+    }
+    output
+}
+
+fn movmatrix_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in movmatrix(catalog) {
+        render_importer_pure_value_dispatch(&mut output, catalog, record);
+    }
+    output
+}
+
+fn prmt_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in prmts(catalog) {
+        let mode = match record.prmt.as_ref().unwrap().mode {
+            PrmtMode::Generic => "PrmtModeAttr::Generic",
+            PrmtMode::F4e => "PrmtModeAttr::F4e",
+            PrmtMode::B4e => "PrmtModeAttr::B4e",
+            PrmtMode::Rc8 => "PrmtModeAttr::Rc8",
+            PrmtMode::Ecl => "PrmtModeAttr::Ecl",
+            PrmtMode::Ecr => "PrmtModeAttr::Ecr",
+            PrmtMode::Rc16 => "PrmtModeAttr::Rc16",
+        };
+        let arity = record.rust.arguments.len();
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        writeln!(
+            output,
+            "            require_arity(name, args.len(), {arity}, &loc)?;"
+        )
+        .unwrap();
+        for index in 0..arity {
+            let previous = if index == 0 { "prev_op" } else { "last_op" };
+            writeln!(
+                output,
+                "            let (arg{index}, last_op) = rvalue::translate_operand(\n                ctx, body, &args[{index}], value_map, block_ptr, {previous}, loc.clone(),\n            )?;"
+            )
+            .unwrap();
+        }
+        let arguments = (0..arity)
+            .map(|index| format!("arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(
+            output,
+            "            let prmt = PrmtOp::build(ctx, vec![{arguments}], {mode});"
+        )
+        .unwrap();
+        output.push_str("            prmt.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, prmt, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, prmt, block_ptr, last_op);\n            let result = prmt.deref(ctx).get_result(0);\n",
+        );
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, prmt, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn cluster_barrier_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if cluster_barriers(catalog).next().is_some() {
+        let arrive = cluster_barriers(catalog)
+            .find(|record| {
+                record
+                    .cluster_barrier
+                    .as_ref()
+                    .is_some_and(|barrier| barrier.mode == ClusterBarrierMode::ArriveAligned)
+            })
+            .expect("aligned cluster arrival");
+        let wait = cluster_barriers(catalog)
+            .find(|record| {
+                record
+                    .cluster_barrier
+                    .as_ref()
+                    .is_some_and(|barrier| barrier.mode == ClusterBarrierMode::WaitAligned)
+            })
+            .expect("aligned cluster wait");
+        output.push_str(
+            "        \"cuda_device::cluster::cluster_sync\" => {\n            require_arity(name, args.len(), 0, &loc)?;\n            let arrive = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::ArriveAligned);\n            arrive.deref_mut(ctx).set_loc(loc.clone());\n",
+        );
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, arrive, {:?});",
+            intrinsic_marker(catalog, arrive)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, arrive, block_ptr, prev_op);\n            let wait = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::WaitAligned);\n            wait.deref_mut(ctx).set_loc(loc.clone());\n",
+        );
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, wait, {:?});",
+            intrinsic_marker(catalog, wait)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, wait, block_ptr, Some(arrive));\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, wait, block_map, loc)))\n            } else {\n                input_err!(loc, TranslationErr::unsupported(\"cluster_sync call without target block\".to_owned()))\n            }\n        }\n",
+        );
+    }
+    for record in cluster_barriers(catalog) {
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n            require_arity(name, args.len(), 0, &loc)?;\n");
+        writeln!(
+            output,
+            "            let barrier = ClusterBarrierOp::build(ctx, {});",
+            cluster_barrier_attr(record)
+        )
+        .unwrap();
+        output.push_str("            barrier.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, barrier, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, barrier, block_ptr, prev_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, barrier, block_map, loc)))\n            } else {\n",
+        );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("            }\n        }\n");
+    }
+    output
+}
+
+fn cluster_memory_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in cluster_memory(catalog) {
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str(
+            "            require_arity(name, args.len(), 2, &loc)?;\n\
+             let (source, last_op) = rvalue::translate_operand(\n\
+                 ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
+             )?;\n\
+             let (rank, last_op) = rvalue::translate_operand(\n\
+                 ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n\
+             )?;\n",
+        );
+        writeln!(
+            output,
+            "            let cluster = {}::build(ctx, source, rank);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            cluster.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, cluster, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, cluster, block_ptr, last_op);\n\
+             let result = cluster.deref(ctx).get_result(0);\n",
+        );
+        writeln!(
+            output,
+            "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, cluster, value_map, block_map, loc,\n                {:?},\n            )?))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn debug_control_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in debug_controls(catalog) {
+        let operation = record.debug_control.as_ref().unwrap().operation;
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        match operation {
+            DebugControlOperation::Trap => {
+                output.push_str("            require_arity(name, args.len(), 0, &loc)?;\n");
+                output.push_str("            let debug = TrapOp::build(ctx);\n");
+                output.push_str("            debug.deref_mut(ctx).set_loc(loc.clone());\n");
+                writeln!(
+                    output,
+                    "            helpers::set_generated_intrinsic_marker(ctx, debug, {:?});",
+                    intrinsic_marker(catalog, record)
+                )
+                .unwrap();
+                output.push_str(
+                    "            helpers::insert_op(ctx, debug, block_ptr, prev_op);\n\
+                     let unreachable = Operation::new(\n\
+                         ctx, MirUnreachableOp::get_concrete_op_info(), vec![], vec![], vec![], 0,\n\
+                     );\n\
+                     unreachable.deref_mut(ctx).set_loc(loc);\n\
+                     helpers::insert_op(ctx, unreachable, block_ptr, Some(debug));\n\
+                     Ok(Some(unreachable))\n",
+                );
+            }
+            DebugControlOperation::Breakpoint => {
+                output.push_str("            require_arity(name, args.len(), 0, &loc)?;\n");
+                output.push_str("            let debug = BreakpointOp::build(ctx);\n");
+                output.push_str("            debug.deref_mut(ctx).set_loc(loc.clone());\n");
+                writeln!(
+                    output,
+                    "            helpers::set_generated_intrinsic_marker(ctx, debug, {:?});",
+                    intrinsic_marker(catalog, record)
+                )
+                .unwrap();
+                output.push_str(
+                    "            helpers::insert_op(ctx, debug, block_ptr, prev_op);\n\
+                     if let Some(target_idx) = target {\n\
+                         Ok(Some(helpers::emit_goto(ctx, *target_idx, debug, block_map, loc)))\n\
+                     } else {\n",
+                );
+                writeln!(
+                    output,
+                    "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+                    format!("{} call without target block", record.rust.name)
+                )
+                .unwrap();
+                output.push_str("            }\n");
+            }
+            DebugControlOperation::Pmevent => {
+                output.push_str(
+                    "            require_arity(name, args.len(), 1, &loc)?;\n\
+                     if !matches!(&args[0], mir::Operand::Constant(_)) {\n\
+                         return input_err!(\n\
+                             loc,\n\
+                             TranslationErr::unsupported(\n\
+                                 \"prof_trigger requires a compile-time constant event ID in 0..=15\".to_owned()\n\
+                             )\n\
+                         );\n\
+                     }\n\
+                     let (event_id_value, last_op) = rvalue::translate_operand(\n\
+                         ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
+                     )?;\n\
+                     let event_id = event_id_value\n\
+                         .defining_op()\n\
+                         .and_then(|defining_op| Operation::get_op::<MirConstantOp>(defining_op, ctx))\n\
+                         .and_then(|constant| constant.get_attr_value(ctx))\n\
+                         .map(|value| value.value().to_u64())\n\
+                         .and_then(|value| u32::try_from(value).ok())\n\
+                         .filter(|value| *value <= 15);\n\
+                     let Some(event_id) = event_id else {\n\
+                         return input_err!(\n\
+                             loc,\n\
+                             TranslationErr::unsupported(\n\
+                                 \"prof_trigger requires a compile-time constant event ID in 0..=15\".to_owned()\n\
+                             )\n\
+                         );\n\
+                     };\n\
+                     let debug = PmEventOp::build(ctx, event_id);\n\
+                     debug.deref_mut(ctx).set_loc(loc.clone());\n",
+                );
+                writeln!(
+                    output,
+                    "            helpers::set_generated_intrinsic_marker(ctx, debug, {:?});",
+                    intrinsic_marker(catalog, record)
+                )
+                .unwrap();
+                output.push_str(
+                    "            helpers::insert_op(ctx, debug, block_ptr, last_op);\n\
+                     if let Some(target_idx) = target {\n\
+                         Ok(Some(helpers::emit_goto(ctx, *target_idx, debug, block_map, loc)))\n\
+                     } else {\n",
+                );
+                writeln!(
+                    output,
+                    "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+                    format!("{} call without target block", record.rust.name)
+                )
+                .unwrap();
+                output.push_str("            }\n");
+            }
+        }
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn clc_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in clc_intrinsics(catalog) {
+        let query = !matches!(
+            record.clc.as_ref().unwrap().operation,
+            ClcOperation::TryCancel | ClcOperation::TryCancelMulticast
+        );
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n            require_arity(name, args.len(), 2, &loc)?;\n");
+        output.push_str(
+            "            let (arg0, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n            let (arg1, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+        );
+        let result_types = if query {
+            "vec![pliron::builtin::types::IntegerType::get(ctx, 32, pliron::builtin::types::Signedness::Unsigned).into()]"
+        } else {
+            "vec![]"
+        };
+        writeln!(
+            output,
+            "            let intrinsic = Operation::new(ctx, {}::get_concrete_op_info(), {result_types}, vec![arg0, arg1], vec![], 0);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str("            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n");
+        if query {
+            output.push_str("            let result = intrinsic.deref(ctx).get_result(0);\n");
+            writeln!(
+                output,
+                "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, intrinsic, value_map, block_map, loc,\n                {:?},\n            )?))",
+                format!("{} call without target block", record.rust.name)
+            )
+            .unwrap();
+        } else {
+            output.push_str("            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, intrinsic, block_map, loc)))\n            } else {\n");
+            writeln!(
+                output,
+                "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+                format!("{} call without target block", record.rust.name)
+            )
+            .unwrap();
+            output.push_str("            }\n");
+        }
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn wgmma_control_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in wgmma_controls(catalog) {
+        let control = record.wgmma_control.as_ref().unwrap();
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        match control.mode {
+            WgmmaControlMode::Fence | WgmmaControlMode::CommitGroup => {
+                output.push_str("            require_arity(name, args.len(), 0, &loc)?;\n");
+                writeln!(
+                    output,
+                    "            let control = {}::build(ctx);",
+                    record.dialect.op_type
+                )
+                .unwrap();
+                output.push_str("            control.deref_mut(ctx).set_loc(loc.clone());\n");
+                writeln!(
+                    output,
+                    "            helpers::set_generated_intrinsic_marker(ctx, control, {:?});",
+                    intrinsic_marker(catalog, record)
+                )
+                .unwrap();
+                output.push_str(
+                    "            helpers::insert_op(ctx, control, block_ptr, prev_op);\n",
+                );
+            }
+            WgmmaControlMode::WaitGroup => {
+                output.push_str(
+                    "            require_arity(name, args.len(), 1, &loc)?;\n\
+                     if !matches!(&args[0], mir::Operand::Constant(_)) {\n\
+                         return input_err!(\n\
+                             loc,\n\
+                             TranslationErr::unsupported(\n\
+                                 \"wgmma_wait_group requires a compile-time constant\".to_owned()\n\
+                             )\n\
+                         );\n\
+                     }\n\
+                     let (max_pending, last_op) = rvalue::translate_operand(\n\
+                         ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n\
+                     )?;\n\
+                     if max_pending\n\
+                         .defining_op()\n\
+                         .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))\n\
+                         .is_none()\n\
+                     {\n\
+                         return input_err!(\n\
+                             loc,\n\
+                             TranslationErr::unsupported(\n\
+                                 \"wgmma_wait_group requires a compile-time constant\".to_owned()\n\
+                             )\n\
+                         );\n\
+                     }\n\
+                     let control = WgmmaWaitGroupSyncAlignedOp::build(ctx, max_pending);\n\
+                     control.deref_mut(ctx).set_loc(loc.clone());\n",
+                );
+                writeln!(
+                    output,
+                    "            helpers::set_generated_intrinsic_marker(ctx, control, {:?});",
+                    intrinsic_marker(catalog, record)
+                )
+                .unwrap();
+                output.push_str(
+                    "            helpers::insert_op(ctx, control, block_ptr, last_op);\n",
+                );
+            }
+        }
+        output.push_str(
+            "            if let Some(target_idx) = target {\n\
+                 Ok(Some(helpers::emit_goto(ctx, *target_idx, control, block_map, loc)))\n\
+             } else {\n",
+        );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("            }\n        }\n");
+    }
+    output
+}
+
+fn cp_async_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in cp_async_copies(catalog) {
+        let copy = record.cp_async_copy.as_ref().unwrap();
+        let dynamic = copy.source_size == CpAsyncSourceSize::Runtime;
+        let arity = if dynamic { 3 } else { 2 };
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        writeln!(
+            output,
+            "            require_arity(name, args.len(), {arity}, &loc)?;"
+        )
+        .unwrap();
+        output.push_str(
+            "            let (shared_dst, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+        );
+        output.push_str(
+            "            let (global_src, last_op) = rvalue::translate_operand(\n                ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+        );
+        if dynamic {
+            output.push_str(
+                "            let (source_size, last_op) = rvalue::translate_operand(\n                ctx, body, &args[2], value_map, block_ptr, last_op, loc.clone(),\n            )?;\n",
+            );
+            writeln!(
+                output,
+                "            let copy = {}::build(ctx, shared_dst, global_src, source_size);",
+                record.dialect.op_type
+            )
+            .unwrap();
+        } else {
+            writeln!(
+                output,
+                "            let copy = {}::build(ctx, shared_dst, global_src);",
+                record.dialect.op_type
+            )
+            .unwrap();
+        }
+        output.push_str("            copy.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, copy, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, copy, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, copy, block_map, loc)))\n            } else {\n",
+        );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("            }\n        }\n");
+    }
+    for record in cp_async_controls(catalog) {
+        let control = record.cp_async_control.as_ref().unwrap();
+        let has_immediate = control.operation == CpAsyncControlOperation::WaitGroup;
+        let arity = usize::from(has_immediate);
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        writeln!(
+            output,
+            "            require_arity(name, args.len(), {arity}, &loc)?;"
+        )
+        .unwrap();
+        if has_immediate {
+            output.push_str(
+                "            if !matches!(&args[0], mir::Operand::Constant(_)) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"cp_async_wait_group requires a compile-time constant max_pending value\".to_owned()\n                    )\n                );\n            }\n",
+            );
+            output.push_str(
+                "            let (max_pending, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+            );
+            writeln!(
+                output,
+                "            let control = {}::build(ctx, max_pending);",
+                record.dialect.op_type
+            )
+            .unwrap();
+        } else {
+            output.push_str("            let last_op = prev_op;\n");
+            writeln!(
+                output,
+                "            let control = {}::build(ctx);",
+                record.dialect.op_type
+            )
+            .unwrap();
+        }
+        output.push_str("            control.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, control, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, control, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, control, block_map, loc)))\n            } else {\n",
+        );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("            }\n        }\n");
+    }
+    for record in cp_async_mbarriers(catalog) {
+        debug_assert_eq!(
+            record.cp_async_mbarrier.as_ref().unwrap().adapter,
+            CpAsyncMbarrierAdapter::PointerToVoid
+        );
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 1, &loc)?;\n");
+        output.push_str(
+            "            let (barrier, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n",
+        );
+        writeln!(
+            output,
+            "            let bridge = {}::build(ctx, barrier);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            bridge.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, bridge, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, bridge, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, bridge, block_map, loc)))\n            } else {\n",
+        );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("            }\n        }\n");
+    }
+    output
+}
+
+fn mbarrier_basic_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in mbarrier_basics(catalog) {
+        let mbarrier = record.mbarrier_basic.as_ref().unwrap();
+        let (argument_names, returns_value) = match mbarrier.operation {
+            MbarrierBasicOperation::Init => {
+                debug_assert_eq!(
+                    mbarrier.adapter,
+                    MbarrierBasicAdapter::InitPointerCountToVoid
+                );
+                (&["barrier", "expected_count"][..], false)
+            }
+            MbarrierBasicOperation::Arrive => {
+                debug_assert_eq!(mbarrier.adapter, MbarrierBasicAdapter::ArrivePointerToToken);
+                (&["barrier"][..], true)
+            }
+            MbarrierBasicOperation::TestWait => {
+                debug_assert_eq!(
+                    mbarrier.adapter,
+                    MbarrierBasicAdapter::TestWaitPointerTokenToPredicate
+                );
+                (&["barrier", "token"][..], true)
+            }
+            MbarrierBasicOperation::Inval => {
+                debug_assert_eq!(mbarrier.adapter, MbarrierBasicAdapter::InvalPointerToVoid);
+                (&["barrier"][..], false)
+            }
+        };
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        writeln!(
+            output,
+            "            require_arity(name, args.len(), {}, &loc)?;",
+            argument_names.len()
+        )
+        .unwrap();
+        for (index, argument_name) in argument_names.iter().enumerate() {
+            let previous = if index == 0 { "prev_op" } else { "last_op" };
+            writeln!(
+                output,
+                "            let ({argument_name}, last_op) = rvalue::translate_operand(\n                ctx, body, &args[{index}], value_map, block_ptr, {previous}, loc.clone(),\n            )?;"
+            )
+            .unwrap();
+        }
+        writeln!(
+            output,
+            "            let mbarrier = {}::build(ctx, {});",
+            record.dialect.op_type,
+            argument_names.join(", ")
+        )
+        .unwrap();
+        output.push_str("            mbarrier.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, mbarrier, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str("            helpers::insert_op(ctx, mbarrier, block_ptr, last_op);\n");
+        if returns_value {
+            output.push_str("            let result = mbarrier.deref(ctx).get_result(0);\n");
+            writeln!(
+                output,
+                "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, mbarrier, value_map, block_map, loc,\n                {:?},\n            )?))",
+                format!("{} call without target block", record.rust.name)
+            )
+            .unwrap();
+        } else {
+            output.push_str(
+                "            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, mbarrier, block_map, loc)))\n            } else {\n",
+            );
+            writeln!(
+                output,
+                "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+                format!("{} call without target block", record.rust.name)
+            )
+            .unwrap();
+            output.push_str("            }\n");
+        }
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn mbarrier_extended_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in mbarrier_extended(catalog) {
+        let contract = record.mbarrier_extended.as_ref().unwrap();
+        let (arguments, returns_value): (Vec<(usize, &str)>, bool) = match contract.adapter {
+            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount => {
+                (vec![(0, "barrier"), (2, "bytes")], true)
+            }
+            MbarrierExtendedAdapter::RawClusterAddressToVoid => (vec![(0, "address")], false),
+            MbarrierExtendedAdapter::PointerTokenToPredicate => {
+                (vec![(0, "barrier"), (1, "token")], true)
+            }
+            MbarrierExtendedAdapter::PointerParityToPredicate => {
+                (vec![(0, "barrier"), (1, "parity")], true)
+            }
+            MbarrierExtendedAdapter::ZeroOperandsToVoid => (vec![], false),
+            MbarrierExtendedAdapter::NanosecondsToVoid => (vec![(0, "ns")], false),
+        };
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        writeln!(
+            output,
+            "            require_arity(name, args.len(), {}, &loc)?;",
+            record.rust.arguments.len()
+        )
+        .unwrap();
+        if arguments.is_empty() {
+            output.push_str("            let last_op = prev_op;\n");
+        }
+        for (position, (argument_index, argument_name)) in arguments.iter().enumerate() {
+            let previous = if position == 0 { "prev_op" } else { "last_op" };
+            writeln!(
+                output,
+                "            let ({argument_name}, last_op) = rvalue::translate_operand(\n                ctx, body, &args[{argument_index}], value_map, block_ptr, {previous}, loc.clone(),\n            )?;"
+            )
+            .unwrap();
+        }
+        let build_arguments = arguments
+            .iter()
+            .map(|(_, name)| *name)
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(
+            output,
+            "            let extended = {}::build(ctx{}{});",
+            record.dialect.op_type,
+            if build_arguments.is_empty() { "" } else { ", " },
+            build_arguments,
+        )
+        .unwrap();
+        output.push_str("            extended.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, extended, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str("            helpers::insert_op(ctx, extended, block_ptr, last_op);\n");
+        if returns_value {
+            output.push_str("            let result = extended.deref(ctx).get_result(0);\n");
+            writeln!(
+                output,
+                "            Ok(Some(helpers::emit_store_result_and_goto(\n                ctx, destination, result, target, block_ptr, extended, value_map, block_map, loc,\n                {:?},\n            )?))",
+                format!("{} call without target block", record.rust.name)
+            )
+            .unwrap();
+        } else {
+            output.push_str(
+                "            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, extended, block_map, loc)))\n            } else {\n",
+            );
+            writeln!(
+                output,
+                "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+                format!("{} call without target block", record.rust.name)
+            )
+            .unwrap();
+            output.push_str("            }\n");
+        }
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn sync_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in sync_intrinsics(catalog) {
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        output.push_str("            require_arity(name, args.len(), 0, &loc)?;\n");
+        writeln!(
+            output,
+            "            let barrier = Operation::new(ctx, {}::get_concrete_op_info(), vec![], vec![], vec![], 0);",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str("            barrier.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, barrier, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, barrier, block_ptr, prev_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, barrier, block_map, loc)))\n            } else {\n",
+        );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("            }\n        }\n");
+    }
+    output
+}
+
+fn execution_control_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in execution_controls(catalog) {
+        let operation = ExecutionControlOperation::from_catalog_id(&record.id)
+            .expect("closed execution-control record");
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        writeln!(
+            output,
+            "            require_arity(name, args.len(), {}, &loc)?;",
+            operation.operand_count()
+        )
+        .unwrap();
+        if operation.requires_immediate_operands() {
+            output.push_str(
+                "            if !matches!(&args[0], mir::Operand::Constant(_)) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"setmaxnreg requires a compile-time register count in 24..=256 divisible by 8\".to_owned()\n                    )\n                );\n            }\n            let (register_count_value, last_op) = rvalue::translate_operand(\n                ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),\n            )?;\n            let register_count = register_count_value\n                .defining_op()\n                .and_then(|defining_op| Operation::get_op::<MirConstantOp>(defining_op, ctx))\n                .and_then(|constant| constant.get_attr_value(ctx))\n                .map(|value| value.value().to_u64())\n                .and_then(|value| u32::try_from(value).ok())\n                .filter(|value| (24..=256).contains(value) && value % 8 == 0);\n            let Some(register_count) = register_count else {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"setmaxnreg requires a compile-time register count in 24..=256 divisible by 8\".to_owned()\n                    )\n                );\n            };\n",
+            );
+            writeln!(
+                output,
+                "            let control = {}::build(ctx, register_count);",
+                record.dialect.op_type
+            )
+            .unwrap();
+        } else if operation.operand_count() == 0 {
+            output.push_str("            let last_op = prev_op;\n");
+            writeln!(
+                output,
+                "            let control = Operation::new(ctx, {}::get_concrete_op_info(), vec![], vec![], vec![], 0);",
+                record.dialect.op_type
+            )
+            .unwrap();
+        } else {
+            output.push_str(
+                "            let mut last_op = prev_op;\n            let mut operands = Vec::with_capacity(args.len());\n            for arg in args {\n                let (value, translated) = rvalue::translate_operand(\n                    ctx, body, arg, value_map, block_ptr, last_op, loc.clone(),\n                )?;\n                last_op = translated;\n                operands.push(value);\n            }\n",
+            );
+            writeln!(
+                output,
+                "            let control = Operation::new(ctx, {}::get_concrete_op_info(), vec![], operands, vec![], 0);",
+                record.dialect.op_type
+            )
+            .unwrap();
+        }
+        output.push_str("            control.deref_mut(ctx).set_loc(loc.clone());\n");
+        writeln!(
+            output,
+            "            helpers::set_generated_intrinsic_marker(ctx, control, {:?});",
+            intrinsic_marker(catalog, record)
+        )
+        .unwrap();
+        output.push_str(
+            "            helpers::insert_op(ctx, control, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, control, block_map, loc)))\n            } else {\n",
+        );
+        writeln!(
+            output,
+            "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+            format!("{} call without target block", record.rust.name)
+        )
+        .unwrap();
+        output.push_str("            }\n        }\n");
+    }
+    output
+}
+
+fn tma_arms(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in tma_intrinsics(catalog) {
+        let operation = record.tma.as_ref().unwrap().operation;
+        let mut path_refs = vec![record.rust.canonical_path.as_str()];
+        path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str));
+        output.push_str("        ");
+        render_inline_patterns(&mut output, &path_refs);
+        output.push_str(" => {\n");
+        if matches!(
+            operation,
+            TmaOperation::WaitGroup | TmaOperation::WaitGroupRead
+        ) {
+            output.push_str(
+                "            require_arity(name, args.len(), 1, &loc)?;\n            if !matches!(args.first(), Some(mir::Operand::Constant(_))) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"TMA wait-group count must be a compile-time constant\".to_owned()\n                    )\n                );\n            }\n",
+            );
+        }
+        let marker = intrinsic_marker(catalog, record);
+        match operation {
+            TmaOperation::G2sTile1d
+            | TmaOperation::G2sTile2d
+            | TmaOperation::G2sTile3d
+            | TmaOperation::G2sTile4d
+            | TmaOperation::G2sTile5d => {
+                writeln!(
+                    output,
+                    "            Ok(Some(super::super::tma::emit_tma_g2s(\n                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, {}, {marker:?},\n            )?))",
+                    operation.dimensions().unwrap()
+                )
+                .unwrap();
+            }
+            TmaOperation::G2sTile2dMulticast => {
+                writeln!(
+                    output,
+                    "            Ok(Some(super::super::tma::emit_tma_g2s_multicast(\n                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, {marker:?},\n            )?))"
+                )
+                .unwrap();
+            }
+            TmaOperation::G2sTile2dMulticastCg2 => {
+                writeln!(
+                    output,
+                    "            Ok(Some(super::super::tma::emit_tma_g2s_multicast_cg2(\n                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, {marker:?},\n            )?))"
+                )
+                .unwrap();
+            }
+            TmaOperation::S2gTile1d
+            | TmaOperation::S2gTile2d
+            | TmaOperation::S2gTile3d
+            | TmaOperation::S2gTile4d
+            | TmaOperation::S2gTile5d => {
+                writeln!(
+                    output,
+                    "            Ok(Some(super::super::tma::emit_tma_s2g(\n                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, {}, {marker:?},\n            )?))",
+                    operation.dimensions().unwrap()
+                )
+                .unwrap();
+            }
+            TmaOperation::CommitGroup => {
+                writeln!(
+                    output,
+                    "            Ok(Some(super::super::tma::emit_tma_commit_group(\n                ctx, args, target, block_ptr, prev_op, block_map, loc, {marker:?},\n            )?))"
+                )
+                .unwrap();
+            }
+            TmaOperation::WaitGroup | TmaOperation::WaitGroupRead => {
+                writeln!(
+                    output,
+                    "            Ok(Some(super::super::tma::emit_tma_wait_group(\n                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, {}, {marker:?},\n            )?))",
+                    operation == TmaOperation::WaitGroupRead
+                )
+                .unwrap();
+            }
+            _ => {
+                let arity = record.dialect.operands.len();
+                writeln!(
+                    output,
+                    "            require_arity(name, args.len(), {arity}, &loc)?;"
+                )
+                .unwrap();
+                if matches!(
+                    record.tma.as_ref().unwrap().adapter,
+                    TmaAdapter::DescriptorOrdinalAndU32
+                        | TmaAdapter::DescriptorOrdinalAndU64
+                        | TmaAdapter::DescriptorAndImmediateU32
+                ) {
+                    output.push_str(
+                        "            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {\n                return input_err!(\n                    loc,\n                    TranslationErr::unsupported(\n                        \"tensor-map replacement selector must be a compile-time constant\".to_owned()\n                    )\n                );\n            }\n",
+                    );
+                }
+                output.push_str(
+                    "            let mut last_op = prev_op;\n            let mut operands = Vec::with_capacity(args.len());\n            for arg in args {\n                let (value, translated) = rvalue::translate_operand(\n                    ctx, body, arg, value_map, block_ptr, last_op, loc.clone(),\n                )?;\n                last_op = translated;\n                operands.push(value);\n            }\n",
+                );
+                writeln!(
+                    output,
+                    "            let intrinsic = Operation::new(ctx, dialect_nvvm::ops::{}::get_concrete_op_info(), vec![], operands, vec![], 0);",
+                    record.dialect.op_type
+                )
+                .unwrap();
+                output.push_str("            intrinsic.deref_mut(ctx).set_loc(loc.clone());\n");
+                writeln!(
+                    output,
+                    "            helpers::set_generated_intrinsic_marker(ctx, intrinsic, {marker:?});"
+                )
+                .unwrap();
+                output.push_str(
+                    "            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);\n            if let Some(target_idx) = target {\n                Ok(Some(helpers::emit_goto(ctx, *target_idx, intrinsic, block_map, loc)))\n            } else {\n",
+                );
+                writeln!(
+                    output,
+                    "                input_err!(loc, TranslationErr::unsupported({:?}.to_owned()))",
+                    format!("{} call without target block", record.rust.name)
+                )
+                .unwrap();
+                output.push_str("            }\n");
+            }
+        }
+        output.push_str("        }\n");
+    }
+    output
+}
+
+fn importer_helpers_body(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    output.push_str(
+        "pub(super) fn require_arity(\n    name: &str,\n    actual: usize,\n    expected: usize,\n    loc: &Location,\n) -> TranslationResult<()> {\n    if actual != expected {\n        return input_err!(\n            loc.clone(),\n            TranslationErr::unsupported(format!(\n                \"generated intrinsic `{name}` expects {expected} arguments, got {actual}\"\n            ))\n        );\n    }\n    Ok(())\n}\n",
+    );
+    if tcgen05_mma_intrinsics(catalog).next().is_some() {
+        output.push_str(
+            r#"
+
+pub(super) fn generated_tcgen05_mma_selector(operand: Option<&mir::Operand>) -> Option<u32> {
+    use rustc_public::ty::{ConstantKind, TyConstKind};
+    let mir::Operand::Constant(constant) = operand? else { return None; };
+    let value: u128 = match constant.const_.kind() {
+        ConstantKind::Allocated(alloc) => alloc.read_uint().ok()?,
+        ConstantKind::Ty(value) => match value.kind() {
+            TyConstKind::Value(_, alloc) => alloc.read_uint().ok()?,
+            _ => value.eval_target_usize().ok()? as u128,
+        },
+        ConstantKind::Unevaluated(_) | ConstantKind::Param(_) => return None,
+        ConstantKind::ZeroSized => return None,
+    };
+    u32::try_from(value).ok()
+}
+"#,
+        );
+    }
+    if tcgen05_intrinsics(catalog)
+        .any(|record| record.tcgen05.as_ref().unwrap().operation == Tcgen05Operation::St)
+    {
+        output.push_str(
+            r#"
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn import_generated_tcgen05_store_operands(
+    ctx: &mut Context,
+    body: &mir::Body,
+    args: &[mir::Operand],
+    expected_len: usize,
+    has_half_split_offset: bool,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    loc: Location,
+) -> TranslationResult<(Vec<Value>, Option<Ptr<Operation>>)> {
+    let expected_arity = if has_half_split_offset { 3 } else { 2 };
+    if args.len() != expected_arity || !(1..=128).contains(&expected_len) {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(
+                "generated tcgen05 store has an invalid address, offset, or register count".to_owned()
+            )
+        );
+    }
+    let u32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+    let (address, last_op) = rvalue::translate_operand(
+        ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),
+    )?;
+    let (half_split_offset, last_op) = if has_half_split_offset {
+        let (offset, translated) = rvalue::translate_operand(
+            ctx, body, &args[1], value_map, block_ptr, last_op, loc.clone(),
+        )?;
+        if offset
+            .defining_op()
+            .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+            .is_none()
+        {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(
+                    "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                )
+            );
+        }
+        (Some(offset), translated)
+    } else {
+        (None, last_op)
+    };
+    let data_index = if has_half_split_offset { 2 } else { 1 };
+    let (data, mut last_op) = rvalue::translate_operand(
+        ctx, body, &args[data_index], value_map, block_ptr, last_op, loc.clone(),
+    )?;
+    if expected_len == 1 {
+        if data.get_type(ctx) != u32_ty {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(
+                    "generated tcgen05 store data must be a u32 register".to_owned()
+                )
+            );
+        }
+        let mut operands = vec![address];
+        operands.extend(half_split_offset);
+        operands.push(data);
+        return Ok((operands, last_op));
+    }
+
+    let data_ty = data.get_type(ctx);
+    let direct_array = data_ty
+        .deref(ctx)
+        .downcast_ref::<MirArrayType>()
+        .is_some_and(|array| {
+            array.size() == expected_len as u64 && array.element_type() == u32_ty
+        });
+    let array = if direct_array {
+        data
+    } else {
+        let wrapped_array_ty = data_ty
+            .deref(ctx)
+            .downcast_ref::<MirStructType>()
+            .filter(|structure| structure.field_count() == 1)
+            .and_then(|structure| structure.get_field_type(0));
+        let valid_wrapper = wrapped_array_ty.is_some_and(|field_ty| {
+            field_ty
+                .deref(ctx)
+                .downcast_ref::<MirArrayType>()
+                .is_some_and(|array| {
+                    array.size() == expected_len as u64 && array.element_type() == u32_ty
+                })
+        });
+        if !valid_wrapper {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "generated tcgen05 store data must contain {expected_len} u32 registers"
+                ))
+            );
+        }
+        let array_ty = wrapped_array_ty.expect("validated tcgen05 store wrapper");
+        let extract = Operation::new(
+            ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![array_ty],
+            vec![data],
+            vec![],
+            0,
+        );
+        extract.deref_mut(ctx).set_loc(loc.clone());
+        let extract = MirExtractFieldOp::new(extract);
+        extract.set_attr_index(ctx, FieldIndexAttr(0));
+        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
+        last_op = Some(extract.get_operation());
+        extract.get_operation().deref(ctx).get_result(0)
+    };
+
+    let mut operands = Vec::with_capacity(expected_len + 1 + usize::from(has_half_split_offset));
+    operands.push(address);
+    operands.extend(half_split_offset);
+    for index in 0..expected_len {
+        let extract = Operation::new(
+            ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![u32_ty],
+            vec![array],
+            vec![],
+            0,
+        );
+        extract.deref_mut(ctx).set_loc(loc.clone());
+        let extract = MirExtractFieldOp::new(extract);
+        extract.set_attr_index(ctx, FieldIndexAttr(index as u32));
+        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
+        last_op = Some(extract.get_operation());
+        operands.push(extract.get_operation().deref(ctx).get_result(0));
+    }
+    Ok((operands, last_op))
+}
+"#,
+        );
+    }
+    if register_mmas(catalog).next().is_some() || sparse_mmas(catalog).next().is_some() {
+        output.push_str(
+            r#"
+
+#[derive(Clone, Copy)]
+pub(super) enum GeneratedMmaImportAdapter {
+    C2U32A2U32B1U32ToD2U32,
+    C2U32A4U32B2U32ToD2U32,
+    C2U32A4U32B4U32ToD2U32,
+    C4F32A2U32B1U32ToD4F32,
+    C4F32A4U32B2U32ToD4F32,
+    C4F32A4U32B4U32ToD4F32,
+    C2F64A1F64B1F64ToD2F64,
+    C2I32A1U32B1U32ToD2I32,
+    C4I32A4U32B2U32ToD4I32,
+    C4I32A4U32B4U32ToD4I32,
+    C4I32A2U32B1U32ToD4I32,
+    C4I32A2U32B2U32ToD4I32,
+    C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+}
+
+#[allow(clippy::too_many_arguments)]
+fn extract_generated_mma_array(
+    ctx: &mut Context,
+    array: Value,
+    expected_element_ty: TypeHandle,
+    expected_len: usize,
+    block_ptr: Ptr<BasicBlock>,
+    mut last_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Vec<Value>, Ptr<Operation>)> {
+    let valid = array
+        .get_type(ctx)
+        .deref(ctx)
+        .downcast_ref::<MirArrayType>()
+        .is_some_and(|array_ty| {
+            array_ty.size() == expected_len as u64
+                && array_ty.element_type() == expected_element_ty
+        });
+    if !valid {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "generated MMA fragment must be an array of {expected_len} scalar registers"
+            ))
+        );
+    }
+    let mut registers = Vec::with_capacity(expected_len);
+    for index in 0..expected_len {
+        let extract = Operation::new(
+            ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![expected_element_ty],
+            vec![array],
+            vec![],
+            0,
+        );
+        extract.deref_mut(ctx).set_loc(loc.clone());
+        let extract = MirExtractFieldOp::new(extract);
+        extract.set_attr_index(ctx, FieldIndexAttr(index as u32));
+        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
+        last_op = Some(extract.get_operation());
+        registers.push(extract.get_operation().deref(ctx).get_result(0));
+    }
+    Ok((registers, last_op.expect("non-empty generated MMA fragment")))
+}
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn import_generated_mma_operands(
+    ctx: &mut Context,
+    body: &mir::Body,
+    args: &[mir::Operand],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    loc: Location,
+    adapter: GeneratedMmaImportAdapter,
+) -> TranslationResult<(Vec<Value>, Ptr<Operation>, TypeHandle, usize)> {
+    let f32_ty: TypeHandle = FP32Type::get(ctx).into();
+    let f64_ty: TypeHandle = FP64Type::get(ctx).into();
+    let i32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Signed).into();
+    let u32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+    let (c_ty, c_count, a_ty, a_count, a_array, b_ty, b_count, b_array, result_ty, result_count) =
+        match adapter {
+            GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32 =>
+                (u32_ty, 2, u32_ty, 2, true, u32_ty, 1, false, u32_ty, 2),
+            GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32 =>
+                (u32_ty, 2, u32_ty, 4, true, u32_ty, 2, true, u32_ty, 2),
+            GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32 =>
+                (u32_ty, 2, u32_ty, 4, true, u32_ty, 4, true, u32_ty, 2),
+            GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32 =>
+                (f32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, f32_ty, 4),
+            GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32 =>
+                (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4),
+            GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32 =>
+                (f32_ty, 4, u32_ty, 4, true, u32_ty, 4, true, f32_ty, 4),
+            GeneratedMmaImportAdapter::C2F64A1F64B1F64ToD2F64 =>
+                (f64_ty, 2, f64_ty, 1, false, f64_ty, 1, false, f64_ty, 2),
+            GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32 =>
+                (i32_ty, 2, u32_ty, 1, false, u32_ty, 1, false, i32_ty, 2),
+            GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32 =>
+                (i32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, i32_ty, 4),
+            GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32 =>
+                (i32_ty, 4, u32_ty, 4, true, u32_ty, 4, true, i32_ty, 4),
+            GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32 =>
+                (i32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, i32_ty, 4),
+            GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32 =>
+                (i32_ty, 4, u32_ty, 2, true, u32_ty, 2, true, i32_ty, 4),
+            GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 =>
+                (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4),
+        };
+    let (c_array, last_op) = rvalue::translate_operand(
+        ctx, body, &args[0], value_map, block_ptr, prev_op, loc.clone(),
+    )?;
+    let (mut operands, last_op) = extract_generated_mma_array(
+        ctx, c_array, c_ty, c_count, block_ptr, last_op, loc.clone(),
+    )?;
+    let (a_value, last_after_a) = rvalue::translate_operand(
+        ctx, body, &args[1], value_map, block_ptr, Some(last_op), loc.clone(),
+    )?;
+    let (a_registers, last_op) = if a_array {
+        extract_generated_mma_array(
+            ctx, a_value, a_ty, a_count, block_ptr, last_after_a, loc.clone(),
+        )?
+    } else {
+        (vec![a_value], last_after_a.expect("generated MMA A translation keeps predecessor"))
+    };
+    operands.extend(a_registers);
+    let (b_value, last_after_b) = rvalue::translate_operand(
+        ctx, body, &args[2], value_map, block_ptr, Some(last_op), loc.clone(),
+    )?;
+    let (b_registers, last_op) = if b_array {
+        extract_generated_mma_array(
+            ctx, b_value, b_ty, b_count, block_ptr, last_after_b, loc.clone(),
+        )?
+    } else {
+        (vec![b_value], last_after_b.expect("generated MMA B translation keeps predecessor"))
+    };
+    operands.extend(b_registers);
+    let mut last_op = last_op;
+    if matches!(
+        adapter,
+        GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
+    ) {
+        for arg in &args[3..] {
+            let (value, translated) = rvalue::translate_operand(
+                ctx,
+                body,
+                arg,
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            last_op = translated.expect("generated block-scale MMA operand translation keeps predecessor");
+            operands.push(value);
+        }
+    }
+    Ok((operands, last_op, result_ty, result_count))
+}
+
+pub(super) fn bundle_generated_mma_results(
+    ctx: &mut Context,
+    mma: Ptr<Operation>,
+    result_ty: TypeHandle,
+    result_count: usize,
+    loc: Location,
+) -> (Value, Ptr<Operation>) {
+    let results = (0..result_count)
+        .map(|index| mma.deref(ctx).get_result(index))
+        .collect();
+    let array_ty = MirArrayType::get(ctx, result_ty, result_count as u64);
+    let array = Operation::new(
+        ctx,
+        MirConstructArrayOp::get_concrete_op_info(),
+        vec![array_ty.into()],
+        results,
+        vec![],
+        0,
+    );
+    array.deref_mut(ctx).set_loc(loc);
+    array.insert_after(ctx, mma);
+    (array.deref(ctx).get_result(0), array)
+}
+"#,
+        );
+    }
+    output
+}
+
+fn render_importer_record_test(
+    output: &mut String,
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+) {
+    writeln!(
+        output,
+        "    #[test]\n    fn {}_uses_only_canonical_or_compatibility_defpaths() {{",
+        record.id
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "        assert!(is_generated_intrinsic_path({:?}));",
+        record.rust.canonical_path
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "        assert!(is_raw_generated_intrinsic_path({:?}));",
+        record.rust.canonical_path
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "        assert_eq!(generated_intrinsic_marker({:?}), Some({:?}));",
+        record.rust.canonical_path,
+        intrinsic_marker(catalog, record)
+    )
+    .unwrap();
+    writeln!(
+            output,
+            "        assert!(matches!(classify_raw_intrinsic_path(\"cuda_intrinsics\", {:?}.into()), RawIntrinsicIdentity::Known(_)));",
+            record.rust.canonical_path
+        )
+        .unwrap();
+    writeln!(
+        output,
+        "        assert!(!is_generated_intrinsic_path({:?}));",
+        record.rust.public_path
+    )
+    .unwrap();
+    for compatibility_path in &record.rust.compatibility_paths {
+        writeln!(
+                output,
+                "        assert!(is_generated_intrinsic_path({compatibility_path:?}));\n        assert!(!is_raw_generated_intrinsic_path({compatibility_path:?}));\n        assert_eq!(generated_intrinsic_marker({compatibility_path:?}), Some({:?}));",
+                intrinsic_marker(catalog, record)
+            )
+            .unwrap();
+    }
+    writeln!(
+            output,
+            "        assert!(!is_generated_intrinsic_path(\"cuda_intrinsics::__cuda_oxide_intrinsic_abi_v{}::{}\"));",
+            catalog.intrinsic_abi + 1,
+            record.rust.abi_id
+        )
+        .unwrap();
+    output.push_str("    }\n");
+}
+
+const IMPORTER_GENERATED_DIR: &str =
+    "crates/mir-importer/src/translator/terminator/intrinsics/generated";
+
+/// tcgen05 dispatch sub-shards, keyed off the catalog contract member each
+/// record carries (the same fields `tcgen05_mma_intrinsics` /
+/// `tcgen05_non_mma_intrinsics` inspect, extended to ld/st/cp).
+const TCGEN05_BUCKETS: &[&str] = &[
+    "tcgen05_mma",
+    "tcgen05_ld",
+    "tcgen05_st",
+    "tcgen05_cp",
+    "tcgen05_other",
+];
+
+fn tcgen05_member_bucket(record: &CatalogIntrinsic) -> &'static str {
+    let tcgen05 = record.tcgen05.as_ref().expect("tcgen05 record");
+    if tcgen05.mma.is_some() {
+        "tcgen05_mma"
+    } else if tcgen05.ld.is_some() {
+        "tcgen05_ld"
+    } else if tcgen05.st.is_some() {
+        "tcgen05_st"
+    } else if tcgen05.cp.is_some() {
+        "tcgen05_cp"
+    } else {
+        "tcgen05_other"
+    }
+}
+
+fn tcgen05_bucket_arms(catalog: &CatalogFile, bucket: &str) -> String {
+    let mut output = String::new();
+    for record in
+        tcgen05_intrinsics(catalog).filter(|record| tcgen05_member_bucket(record) == bucket)
+    {
+        if record.tcgen05.as_ref().unwrap().mma.is_some() {
+            render_importer_tcgen05_mma_dispatch(&mut output, catalog, record);
+        } else {
+            render_importer_tcgen05_non_mma_dispatch(&mut output, catalog, record);
+        }
+    }
+    output
+}
+
+/// Dispatch shards in the old single-file family emission order. `cp_async`
+/// and `execution_control` coalesce the same catalog families as
+/// `dialect-nvvm/src/ops/generated/`.
+fn importer_dispatch_shards(catalog: &CatalogFile) -> Vec<(&'static str, String)> {
+    let mut shards: Vec<(&'static str, String)> = vec![
+        ("sreg", sreg_arms(catalog)),
+        ("active_mask", active_mask_arms(catalog)),
+        ("ldmatrix", ldmatrix_arms(catalog)),
+        ("stmatrix", stmatrix_arms(catalog)),
+        ("register_mma", register_mma_arms(catalog)),
+        ("sparse_mma", sparse_mma_arms(catalog)),
+        ("packed_atomic", packed_atomic_arms(catalog)),
+        ("redux", redux_arms(catalog)),
+        ("vote", vote_arms(catalog)),
+        ("warp_match", warp_match_arms(catalog)),
+        ("elect", elect_arms(catalog)),
+        ("warp_barrier", warp_barrier_arms(catalog)),
+        ("warp_shuffle", warp_shuffle_arms(catalog)),
+        ("dotprod", dotprod_arms(catalog)),
+        ("packed_alu", packed_alu_arms(catalog)),
+        ("integer_minmax", integer_minmax_arms(catalog)),
+        ("packed_conversion", packed_conversion_arms(catalog)),
+        ("scalar_conversion", scalar_conversion_arms(catalog)),
+        ("scalar_arithmetic", scalar_arithmetic_arms(catalog)),
+        ("scalar_math", scalar_math_arms(catalog)),
+        ("extended_minmax", extended_minmax_arms(catalog)),
+        ("movmatrix", movmatrix_arms(catalog)),
+        ("prmt", prmt_arms(catalog)),
+        ("cluster_barrier", cluster_barrier_arms(catalog)),
+        ("cluster_memory", cluster_memory_arms(catalog)),
+        ("debug_control", debug_control_arms(catalog)),
+        ("clc", clc_arms(catalog)),
+        ("wgmma_control", wgmma_control_arms(catalog)),
+        ("cp_async", cp_async_arms(catalog)),
+        ("mbarrier_basic", mbarrier_basic_arms(catalog)),
+        ("mbarrier_extended", mbarrier_extended_arms(catalog)),
+        ("sync", sync_arms(catalog)),
+        ("execution_control", execution_control_arms(catalog)),
+        ("tma", tma_arms(catalog)),
+    ];
+    for bucket in TCGEN05_BUCKETS {
+        shards.push((bucket, tcgen05_bucket_arms(catalog, bucket)));
+    }
+    shards.retain(|(_, arms)| !arms.is_empty());
+    shards
+}
+
+/// Test shards keep whole families together (tcgen05 fits one test file).
+const IMPORTER_TEST_SHARD_ORDER: &[&str] = &[
+    "sreg",
+    "active_mask",
+    "ldmatrix",
+    "stmatrix",
+    "register_mma",
+    "sparse_mma",
+    "packed_atomic",
+    "redux",
+    "vote",
+    "warp_match",
+    "elect",
+    "warp_barrier",
+    "warp_shuffle",
+    "dotprod",
+    "packed_alu",
+    "integer_minmax",
+    "packed_conversion",
+    "scalar_conversion",
+    "scalar_arithmetic",
+    "scalar_math",
+    "extended_minmax",
+    "movmatrix",
+    "prmt",
+    "cluster_barrier",
+    "cluster_memory",
+    "debug_control",
+    "clc",
+    "wgmma_control",
+    "cp_async",
+    "mbarrier_basic",
+    "mbarrier_extended",
+    "sync",
+    "execution_control",
+    "tma",
+    "tcgen05",
+];
+
+fn importer_shard_for_family(family: &str) -> &'static str {
+    match family {
+        "cp_async_copy" | "cp_async_control" | "cp_async_mbarrier" => "cp_async",
+        "counted_barrier" | "grid_dependency" | "register_control" => "execution_control",
+        _ => IMPORTER_TEST_SHARD_ORDER
+            .iter()
+            .copied()
+            .find(|shard| *shard == family)
+            .unwrap_or_else(|| panic!("unmapped generated intrinsic family `{family}`")),
+    }
+}
+
+fn importer_test_shards(catalog: &CatalogFile) -> Vec<(&'static str, Vec<&CatalogIntrinsic>)> {
+    let mut shards: Vec<(&'static str, Vec<&CatalogIntrinsic>)> = IMPORTER_TEST_SHARD_ORDER
+        .iter()
+        .map(|name| (*name, Vec::new()))
+        .collect();
+    for record in &catalog.intrinsics {
+        let shard = importer_shard_for_family(&record.family);
+        shards
+            .iter_mut()
+            .find(|(name, _)| *name == shard)
+            .expect("closed importer shard list")
+            .1
+            .push(record);
+    }
+    shards.retain(|(_, records)| !records.is_empty());
+    shards
+}
+
+fn push_use_group<S: AsRef<str>>(output: &mut String, root: &str, items: &[S]) {
+    match items {
+        [] => {}
+        [only] => writeln!(output, "use {root}::{};", only.as_ref()).unwrap(),
+        _ => writeln!(
+            output,
+            "use {root}::{{{}}};",
+            items
+                .iter()
+                .map(AsRef::as_ref)
+                .collect::<Vec<_>>()
+                .join(", ")
+        )
+        .unwrap(),
+    }
+}
+
+fn nested_use_items(prefix: &str, items: &[&str]) -> Option<String> {
+    match items {
+        [] => None,
+        [only] => Some(format!("{prefix}::{only}")),
+        _ => Some(format!("{prefix}::{{{}}}", items.join(", "))),
+    }
+}
+
+/// Build the exact `use` list one importer shard needs by scanning its body.
+/// `dispatch_signature` marks files whose `try_dispatch` signature always
+/// needs the dispatch parameter types; `helpers_module` suppresses the
+/// `super::helpers` group inside the helpers module itself.
+fn importer_shard_imports(
+    catalog: &CatalogFile,
+    body: &str,
+    dispatch_signature: bool,
+    helpers_module: bool,
+) -> String {
+    let mut output = String::new();
+    let mut error_items = Vec::new();
+    if uses_identifier(body, "TranslationErr") {
+        error_items.push("TranslationErr");
+    }
+    if dispatch_signature || uses_identifier(body, "TranslationResult") {
+        error_items.push("TranslationResult");
+    }
+    push_use_group(&mut output, "crate::error", &error_items);
+
+    let mut translator_items = Vec::new();
+    if body.contains("rvalue::") {
+        translator_items.push("rvalue");
+    }
+    if body.contains("helpers::") {
+        translator_items.push("terminator::helpers");
+    }
+    if uses_identifier(body, "types") {
+        translator_items.push("types");
+    }
+    if dispatch_signature || uses_identifier(body, "ValueMap") {
+        translator_items.push("values::ValueMap");
+    }
+    push_use_group(&mut output, "crate::translator", &translator_items);
+
+    let mut mir_dialect = Vec::new();
+    if uses_identifier(body, "FieldIndexAttr") {
+        mir_dialect.push("attributes::FieldIndexAttr".to_owned());
+    }
+    let mir_ops: Vec<&str> = [
+        "MirConstantOp",
+        "MirConstructArrayOp",
+        "MirConstructStructOp",
+        "MirConstructTupleOp",
+        "MirExtractFieldOp",
+        "MirUnreachableOp",
+    ]
+    .into_iter()
+    .filter(|item| uses_identifier(body, item))
+    .collect();
+    if let Some(nested) = nested_use_items("ops", &mir_ops) {
+        mir_dialect.push(nested);
+    }
+    let mir_types: Vec<&str> = ["MirArrayType", "MirStructType", "MirTupleType"]
+        .into_iter()
+        .filter(|item| uses_identifier(body, item))
+        .collect();
+    if let Some(nested) = nested_use_items("types", &mir_types) {
+        mir_dialect.push(nested);
+    }
+    push_use_group(&mut output, "dialect_mir", &mir_dialect);
+
+    let nvvm: Vec<String> = dialect_nvvm_ops_import_candidates(catalog)
+        .into_iter()
+        .filter(|item| uses_identifier(body, item))
+        .collect();
+    push_use_group(&mut output, "dialect_nvvm::ops", &nvvm);
+
+    if dispatch_signature || uses_identifier(body, "BasicBlock") {
+        output.push_str("use pliron::basic_block::BasicBlock;\n");
+    }
+    let builtin: Vec<&str> = ["FP32Type", "FP64Type", "IntegerType", "Signedness"]
+        .into_iter()
+        .filter(|item| uses_identifier(body, item))
+        .collect();
+    push_use_group(&mut output, "pliron::builtin::types", &builtin);
+    if dispatch_signature || uses_identifier(body, "Context") || uses_identifier(body, "Ptr") {
+        output.push_str("use pliron::context::{Context, Ptr};\n");
+    }
+    if body.contains("input_err!") {
+        output.push_str("use pliron::input_err;\n");
+    }
+    let mut location_items = Vec::new();
+    if body.contains(".set_loc(") {
+        location_items.push("Located");
+    }
+    if dispatch_signature || uses_identifier(body, "Location") {
+        location_items.push("Location");
+    }
+    push_use_group(&mut output, "pliron::location", &location_items);
+    if body.contains("::get_concrete_op_info(") || body.contains(".get_operation()") {
+        output.push_str("use pliron::op::Op;\n");
+    }
+    if dispatch_signature || uses_identifier(body, "Operation") {
+        output.push_str("use pliron::operation::Operation;\n");
+    }
+    let mut type_items = Vec::new();
+    if uses_identifier(body, "TypeHandle") {
+        type_items.push("TypeHandle");
+    }
+    if body.contains(".get_type(") {
+        type_items.push("Typed");
+    }
+    push_use_group(&mut output, "pliron::r#type", &type_items);
+    if uses_identifier(body, "Value") {
+        output.push_str("use pliron::value::Value;\n");
+    }
+    if dispatch_signature || uses_identifier(body, "mir") {
+        output.push_str("use rustc_public::mir;\n");
+    }
+
+    if !helpers_module {
+        let glue: Vec<&str> = [
+            "GeneratedMmaImportAdapter",
+            "bundle_generated_mma_results",
+            "generated_tcgen05_mma_selector",
+            "import_generated_mma_operands",
+            "import_generated_tcgen05_store_operands",
+            "require_arity",
+        ]
+        .into_iter()
+        .filter(|item| uses_identifier(body, item))
+        .collect();
+        push_use_group(&mut output, "super::helpers", &glue);
+    }
+    output
+}
+
+const IMPORTER_DISPATCH_PARAMS: &[(&str, &str)] = &[
+    ("ctx", "&mut Context"),
+    ("body", "&mir::Body"),
+    ("name", "&str"),
+    ("args", "&[mir::Operand]"),
+    ("destination", "&mir::Place"),
+    ("target", "&Option<usize>"),
+    ("block_ptr", "Ptr<BasicBlock>"),
+    ("prev_op", "Option<Ptr<Operation>>"),
+    ("value_map", "&mut ValueMap"),
+    ("block_map", "&[Ptr<BasicBlock>]"),
+    ("loc", "Location"),
+];
+
+fn importer_dispatch_file(catalog: &CatalogFile, hash: &str, shard: &str, arms: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    writeln!(
+        output,
+        "//! Generated raw/compatibility dispatch arms: `{shard}` intrinsics.\n"
+    )
+    .unwrap();
+    output.push_str(&importer_shard_imports(catalog, arms, true, false));
+    output.push_str("\n#[allow(clippy::too_many_arguments)]\npub(super) fn try_dispatch(\n");
+    for (parameter, ty) in IMPORTER_DISPATCH_PARAMS {
+        let silent = *parameter != "name" && !uses_identifier(arms, parameter);
+        writeln!(
+            output,
+            "    {}{parameter}: {ty},",
+            if silent { "_" } else { "" }
+        )
+        .unwrap();
+    }
+    output.push_str(") -> TranslationResult<Option<Ptr<Operation>>> {\n    match name {\n");
+    output.push_str(arms);
+    output.push_str("        _ => Ok(None),\n    }\n}\n");
+    output
+}
+
+fn importer_helpers_file(catalog: &CatalogFile, hash: &str) -> String {
+    let body = importer_helpers_body(catalog);
+    let mut output = rust_header(catalog, hash);
+    output.push_str("//! Shared glue for the generated intrinsic dispatch shards.\n\n");
+    output.push_str(&importer_shard_imports(catalog, &body, false, true));
+    output.push('\n');
+    output.push_str(&body);
+    output.push('\n');
+    output
+}
+
+fn importer_mod_file(
+    catalog: &CatalogFile,
+    hash: &str,
+    shards: &[(&'static str, String)],
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Generated raw/compatibility path dispatch for CUDA intrinsics.\n\nuse crate::error::{TranslationErr, TranslationResult};\nuse crate::translator::values::ValueMap;\nuse pliron::basic_block::BasicBlock;\nuse pliron::context::{Context, Ptr};\nuse pliron::input_err;\nuse pliron::location::Location;\nuse pliron::operation::Operation;\nuse rustc_public::{CrateDef, mir, ty::FnDef};\n\nmod helpers;\n",
+    );
+    for (shard, _) in shards {
+        writeln!(output, "mod {shard};").unwrap();
+    }
+    output.push_str("#[cfg(test)]\nmod tests;\n\n");
+    append_importer_classification(&mut output, catalog);
+    output.push_str(
+        "#[allow(clippy::too_many_arguments)]\npub fn try_dispatch_generated_intrinsic(\n    ctx: &mut Context,\n    body: &mir::Body,\n    name: &str,\n    args: &[mir::Operand],\n    destination: &mir::Place,\n    target: &Option<usize>,\n    block_ptr: Ptr<BasicBlock>,\n    prev_op: Option<Ptr<Operation>>,\n    value_map: &mut ValueMap,\n    block_map: &[Ptr<BasicBlock>],\n    loc: Location,\n) -> TranslationResult<Option<Ptr<Operation>>> {\n",
+    );
+    for (shard, _) in shards {
+        writeln!(
+            output,
+            "    if let Some(operation) = {shard}::try_dispatch(\n        ctx, body, name, args, destination, target, block_ptr, prev_op, value_map, block_map,\n        loc.clone(),\n    )? {{\n        return Ok(Some(operation));\n    }}"
+        )
+        .unwrap();
+    }
+    output.push_str("    Ok(None)\n}\n");
+    output
+}
+
+fn importer_tests_mod_file(
+    catalog: &CatalogFile,
+    hash: &str,
+    shards: &[(&'static str, Vec<&CatalogIntrinsic>)],
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    output.push_str(
+        "//! Generated dispatch-path tests, grouped per intrinsic family.\n\nuse super::*;\n\n",
+    );
+    for (shard, _) in shards {
+        writeln!(output, "mod {shard};").unwrap();
+    }
+    output.push_str(
+        "\n    #[test]\n    fn raw_intrinsic_identity_classification_fails_closed() {\n        assert_eq!(\n            classify_raw_intrinsic_path(\"serde\", \"serde::helper\".into()),\n            RawIntrinsicIdentity::NotRawCrate\n        );\n        assert!(matches!(\n            classify_raw_intrinsic_path(\"cuda_intrinsics\", \"cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0001\".into()),\n            RawIntrinsicIdentity::UnsupportedAbi(_)\n        ));\n        assert!(matches!(\n            classify_raw_intrinsic_path(\"cuda_intrinsics\", \"cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i9999\".into()),\n            RawIntrinsicIdentity::UnknownId(_)\n        ));\n        assert!(matches!(\n            classify_raw_intrinsic_path(\"cuda_intrinsics\", \"cuda_intrinsics::helper\".into()),\n            RawIntrinsicIdentity::UnknownId(_)\n        ));\n    }\n",
+    );
+    output
+}
+
+fn importer_tests_shard_file(
+    catalog: &CatalogFile,
+    hash: &str,
+    shard: &str,
+    records: &[&CatalogIntrinsic],
+) -> String {
+    let mut output = rust_header(catalog, hash);
+    writeln!(
+        output,
+        "//! Generated dispatch-path tests: `{shard}` intrinsics.\n\nuse super::super::*;\n"
+    )
+    .unwrap();
+    for record in records {
+        render_importer_record_test(&mut output, catalog, record);
+    }
+    output
+}
+
+pub(super) fn render_importer_files(catalog: &CatalogFile, hash: &str) -> Vec<(PathBuf, String)> {
+    let shards = importer_dispatch_shards(catalog);
+    let test_shards = importer_test_shards(catalog);
+    let mut files = vec![
+        (
+            PathBuf::from(format!("{IMPORTER_GENERATED_DIR}/mod.rs")),
+            importer_mod_file(catalog, hash, &shards),
+        ),
+        (
+            PathBuf::from(format!("{IMPORTER_GENERATED_DIR}/helpers.rs")),
+            importer_helpers_file(catalog, hash),
+        ),
+        (
+            PathBuf::from(format!("{IMPORTER_GENERATED_DIR}/tests/mod.rs")),
+            importer_tests_mod_file(catalog, hash, &test_shards),
+        ),
+    ];
+    for (shard, arms) in &shards {
+        files.push((
+            PathBuf::from(format!("{IMPORTER_GENERATED_DIR}/{shard}.rs")),
+            importer_dispatch_file(catalog, hash, shard, arms),
+        ));
+    }
+    for (shard, records) in &test_shards {
+        files.push((
+            PathBuf::from(format!("{IMPORTER_GENERATED_DIR}/tests/{shard}.rs")),
+            importer_tests_shard_file(catalog, hash, shard, records),
+        ));
+    }
+    files
+}
+
+#[cfg(test)]
+pub(super) fn render_importer(catalog: &CatalogFile, hash: &str) -> String {
+    render_importer_files(catalog, hash)
+        .into_iter()
+        .map(|(_, contents)| contents)
+        .collect::<Vec<_>>()
+        .join("\n")
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/lowering.rs b/crates/cuda-intrinsics-gen/src/render/lowering.rs
new file mode 100644
index 0000000000..299ffacd2c
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/lowering.rs
@@ -0,0 +1,2317 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    ActiveMaskAdapter, BackendLoweringMechanism, CatalogFile, ClcOperation, ClusterBarrierMode,
+    ClusterMemoryOperation, CpAsyncCachePolicy, CpAsyncControlOperation, CpAsyncMbarrierOperation,
+    CpAsyncMbarrierStateSpace, CpAsyncSourceSize, DebugControlOperation, DotProductAdapter,
+    ExecutionControlOperation, IntrinsicBackend, MbarrierBasicAdapter, MbarrierBasicOperation,
+    MbarrierExtendedAdapter, PackedConversionAdapter, PackedConversionSourceFormat, PrmtAdapter,
+    PrmtMode, ReduxAdapter, ScalarArithmeticFormat, ScalarMathFormat, StmatrixLayout,
+    Tcgen05Operation, TmaOperation, TmaReductionLoadMode, TmaReductionOperation, VoteAdapter,
+    WarpBarrierAdapter, WarpMatchAdapter, WarpShuffleAdapter, WarpShuffleMode,
+    WarpShuffleValueKind, WgmmaControlMode,
+};
+use crate::render::common::{rust_header, uses_identifier};
+use crate::render::families::{
+    active_masks, clc_intrinsics, cluster_barrier_attr, cluster_barrier_template, cluster_barriers,
+    cluster_memory, cp_async_controls, cp_async_copies, cp_async_mbarriers, debug_controls,
+    dialect_nvvm_ops_import_candidates, dot_product_ptx, dot_products, elect_intrinsics,
+    execution_controls, expected_ptx_head, extended_minmax, extended_minmax_carrier,
+    extended_minmax_format_attr, extended_minmax_nan_attr, extended_minmax_operation_attr,
+    extended_minmax_ptx_mnemonic, extended_minmax_subnormal_attr, extended_minmax_xorsign_abs_attr,
+    integer_minmax_ptx_mnemonic, integer_minmaxes, ldmatrix, ldmatrix_attr_variants,
+    ldmatrix_compat_op, mbarrier_basics, mbarrier_extended, movmatrix, movmatrix_template,
+    packed_alu_ptx_mnemonic, packed_alu_width, packed_alus, packed_atomics,
+    packed_conversion_ptx_mnemonic, packed_conversion_result_width, packed_conversion_source_width,
+    packed_conversion_typed_llvm_name, packed_conversions, prmts, redux,
+    register_mma_attr_variants, register_mma_compat_op_type, register_mma_constraints,
+    register_mma_extra_operand_count, register_mma_fragment_counts, register_mma_result_variant,
+    register_mma_template, register_mmas, scalar_arithmetic_contract,
+    scalar_arithmetic_format_attr, scalar_arithmetic_llvm_mechanism,
+    scalar_arithmetic_operation_attr, scalar_arithmetic_ptx_mnemonic,
+    scalar_arithmetic_rounding_attr, scalar_arithmetic_saturation_attr,
+    scalar_arithmetic_subnormal_attr, scalar_arithmetics, scalar_conversion_ptx_mnemonic,
+    scalar_conversion_rounding_attr, scalar_conversion_saturation_attr, scalar_conversions,
+    scalar_math_contract, scalar_math_format_attr, scalar_math_llvm_mechanism,
+    scalar_math_operation_attr, scalar_math_precision_attr, scalar_math_ptx_mnemonic,
+    scalar_math_subnormal_attr, scalar_maths, sparse_mma_attr_variants, sparse_mma_constraints,
+    sparse_mma_fragment_counts, sparse_mma_result_variant, sparse_mma_template, sparse_mmas,
+    special_register_asm_kind, special_register_backend_mechanism,
+    special_register_inline_template, special_register_output_constraint, sregs, stmatrices,
+    stmatrix_variant, sync_intrinsics, tcgen05_inline_asm, tcgen05_intrinsics,
+    tcgen05_mma_intrinsics, tcgen05_non_mma_intrinsics, threadfence_ptx_level, tma_intrinsics,
+    vote_intrinsics, warp_barriers, warp_matches, warp_shuffles, wgmma_control_template,
+    wgmma_controls,
+};
+use std::fmt::Write as _;
+use std::path::PathBuf;
+
+fn lowering_shared_converters(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    output.push_str(
+        "fn convert_zero_operand_scalar_direct(\n    ctx: &mut Context,\n    rewriter: &mut DialectConversionRewriter,\n    op: Ptr<Operation>,\n    width: u32,\n    intrinsic_name: &str,\n) -> Result<()> {\n    let result_ty = IntegerType::get(ctx, width, Signedness::Signless);\n    let function_ty = llvm_types::FuncType::get(ctx, result_ty.into(), vec![], false);\n    let call = call_intrinsic(ctx, rewriter, op, intrinsic_name, function_ty, vec![])?;\n    rewriter.replace_operation(ctx, op, call);\n    Ok(())\n}\n\n",
+    );
+    if tcgen05_intrinsics(catalog).next().is_some() {
+        output.push_str(
+            r#"fn convert_generated_tcgen05_void(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    arity: usize,
+    template: &str,
+    constraints: &str,
+) -> Result<()> {
+    let operands: Vec<_> = op.deref(ctx).operands().collect();
+    if operands.len() != arity {
+        return pliron::input_err_noloc!(
+            "generated tcgen05 operation expects {arity} operands, got {}",
+            operands.len()
+        );
+    }
+    let void_ty = llvm_types::VoidType::get(ctx);
+    inline_asm_convergent(
+        ctx,
+        rewriter,
+        op,
+        void_ty.into(),
+        operands,
+        template,
+        constraints,
+    );
+    rewriter.erase_operation(ctx, op);
+    Ok(())
+}
+
+#[allow(clippy::too_many_arguments)]
+fn convert_generated_tcgen05_load(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    arity: usize,
+    count: usize,
+    integer_results: bool,
+    template: &str,
+    constraints: &str,
+) -> Result<()> {
+    let operands: Vec<_> = op.deref(ctx).operands().collect();
+    if operands.len() != arity || !(1..=2).contains(&arity) || !(1..=128).contains(&count) || op.deref(ctx).get_num_results() != count {
+        return pliron::input_err_noloc!(
+            "generated tcgen05 load requires 1..=2 operands and 1..=128 results"
+        );
+    }
+    let scalar_ty: pliron::r#type::TypeHandle = if integer_results {
+        IntegerType::get(ctx, 32, Signedness::Signless).into()
+    } else {
+        FP32Type::get(ctx).into()
+    };
+    if count == 1 {
+        let inline_asm = inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            scalar_ty,
+            operands,
+            template,
+            constraints,
+        );
+        let result = inline_asm.deref(ctx).get_result(0);
+        rewriter.replace_operation_with_values(ctx, op, vec![result]);
+        return Ok(());
+    }
+    let result_ty = llvm_types::StructType::get_unnamed(
+        ctx,
+        (
+            (0..count).map(|_| scalar_ty).collect(),
+            llvm_types::StructLayout::Unpacked,
+        ),
+    );
+    let inline_asm = inline_asm_convergent(
+        ctx,
+        rewriter,
+        op,
+        result_ty.into(),
+        operands,
+        template,
+        constraints,
+    );
+    let result = inline_asm.deref(ctx).get_result(0);
+    let mut values = Vec::with_capacity(count);
+    for index in 0..count as u32 {
+        let extract = llvm_ops::ExtractValueOp::new(ctx, result, vec![index])
+            .map_err(|error| pliron::input_error_noloc!("{}", error))?;
+        rewriter.insert_operation(ctx, extract.get_operation());
+        values.push(extract.get_operation().deref(ctx).get_result(0));
+    }
+    rewriter.replace_operation_with_values(ctx, op, values);
+    Ok(())
+}
+
+"#,
+        );
+    }
+    if stmatrices(catalog).next().is_some() {
+        output.push_str(
+            r#"fn convert_generated_stmatrix(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    register_count: usize,
+    transposed: bool,
+    typed_intrinsic_name: &str,
+) -> Result<()> {
+    let operands: Vec<_> = op.deref(ctx).operands().collect();
+    if operands.len() != register_count + 1 || !matches!(register_count, 2 | 4) {
+        return pliron::input_err_noloc!(
+            "stmatrix requires one pointer and two or four registers"
+        );
+    }
+    let void_ty = llvm_types::VoidType::get(ctx);
+    match context::lowering_options(ctx).intrinsic_backend {
+        IntrinsicBackend::LlvmNvptx => {
+            let shared = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
+            let shared_ty = llvm_types::PointerType::get(
+                ctx,
+                llvm_types::address_space::SHARED,
+            );
+            let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+            let argument_types = std::iter::once(shared_ty.into())
+                .chain(std::iter::repeat_n(i32_ty.into(), register_count))
+                .collect();
+            let function_ty = llvm_types::FuncType::get(
+                ctx,
+                void_ty.into(),
+                argument_types,
+                false,
+            );
+            let arguments = std::iter::once(shared)
+                .chain(operands.iter().skip(1).copied())
+                .collect();
+            call_intrinsic(
+                ctx,
+                rewriter,
+                op,
+                typed_intrinsic_name,
+                function_ty,
+                arguments,
+            )?;
+        }
+        IntrinsicBackend::LibNvvm => {
+            let registers = (1..=register_count)
+                .map(|index| format!("${index}"))
+                .collect::<Vec<_>>()
+                .join(", ");
+            let trans = if transposed { ".trans" } else { "" };
+            let template = format!(
+                "{{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x{register_count}{trans}.shared.b16 [%ptr32], {{{registers}}}; }}"
+            );
+            let constraints = std::iter::once("l")
+                .chain(std::iter::repeat_n("r", register_count))
+                .chain(std::iter::once("~{memory}"))
+                .collect::<Vec<_>>()
+                .join(",");
+            inline_asm_convergent(
+                ctx,
+                rewriter,
+                op,
+                void_ty.into(),
+                operands,
+                &template,
+                &constraints,
+            );
+        }
+    }
+    rewriter.erase_operation(ctx, op);
+    Ok(())
+}
+
+"#,
+        );
+    }
+    output
+}
+
+fn sreg_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in sregs(catalog) {
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        if record.special_register.is_none() {
+            writeln!(
+                output,
+                "        convert_zero_operand_scalar_direct(ctx, rewriter, self.get_operation(), {}, {:?})",
+                record.scalar_width().unwrap(),
+                record.llvm_identifier()
+            )
+            .unwrap();
+        } else {
+            output.push_str("        match context::lowering_options(ctx).intrinsic_backend {\n");
+            for (backend, backend_variant) in [
+                (IntrinsicBackend::LlvmNvptx, "LlvmNvptx"),
+                (IntrinsicBackend::LibNvvm, "LibNvvm"),
+            ] {
+                writeln!(
+                    output,
+                    "            IntrinsicBackend::{backend_variant} => {{"
+                )
+                .unwrap();
+                match special_register_backend_mechanism(record, backend) {
+                    BackendLoweringMechanism::TypedNvvm => writeln!(
+                        output,
+                        "                convert_zero_operand_scalar_direct(ctx, rewriter, self.get_operation(), {}, {:?})",
+                        record.scalar_width().unwrap(),
+                        record.llvm_identifier()
+                    )
+                    .unwrap(),
+                    BackendLoweringMechanism::InlinePtx => writeln!(
+                        output,
+                        "                convert_sreg_read_inline(ctx, rewriter, self.get_operation(), {}, {:?}, {:?}, {})",
+                        record.scalar_width().unwrap(),
+                        special_register_inline_template(record),
+                        special_register_output_constraint(record),
+                        special_register_asm_kind(record),
+                    )
+                    .unwrap(),
+                }
+                output.push_str("            }\n");
+            }
+            output.push_str("        }\n");
+        }
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn active_mask_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in active_masks(catalog) {
+        debug_assert_eq!(
+            record.active_mask.as_ref().unwrap().adapter,
+            ActiveMaskAdapter::DirectZeroOperandMask
+        );
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        match context::lowering_options(ctx).intrinsic_backend {\n            IntrinsicBackend::LlvmNvptx => {\n                convert_active_mask(ctx, rewriter, op, operands_info)\n            }\n            IntrinsicBackend::LibNvvm => {\n                let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);\n                let inline_asm = inline_asm_convergent(\n                    ctx,\n                    rewriter,\n                    op,\n                    i32_ty.into(),\n                    vec![],\n                    \"activemask.b32 $0;\",\n                    \"=r,~{memory}\",\n                );\n                rewriter.replace_operation(ctx, op, inline_asm);\n                Ok(())\n            }\n        }\n    }\n}\n\n",
+        );
+    }
+    output
+}
+
+fn ldmatrix_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if ldmatrix(catalog).next().is_some() {
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for LdmatrixOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = {\n            let shape = self.get_attr_nvvm_ldmatrix_shape(ctx);\n            let multiplicity = self.get_attr_nvvm_ldmatrix_multiplicity(ctx);\n            let layout = self.get_attr_nvvm_ldmatrix_layout(ctx);\n            let element = self.get_attr_nvvm_ldmatrix_element(ctx);\n            let state_space = self.get_attr_nvvm_ldmatrix_state_space(ctx);\n            match (shape.as_deref(), multiplicity.as_deref(), layout.as_deref(), element.as_deref(), state_space.as_deref()) {\n",
+        );
+        for record in ldmatrix(catalog) {
+            let (shape, multiplicity, layout, element, state_space) =
+                ldmatrix_attr_variants(record);
+            let variant = &record.ldmatrix.as_ref().unwrap().variant;
+            let register_count = variant.register_count();
+            let instruction_head = expected_ptx_head(record);
+            let intrinsic_name = record.resolved_llvm_identifier();
+            writeln!(
+                output,
+                "                (Some(&{shape}), Some(&{multiplicity}), Some(&{layout}), Some(&{element}), Some(&{state_space})) => ({register_count}, {instruction_head:?}, {intrinsic_name:?}),"
+            )
+            .unwrap();
+        }
+        output.push_str(
+            "                _ => return pliron::input_err!(\n                    self.get_operation().deref(ctx).loc(),\n                    \"nvvm.ldmatrix variant has no generated lowering recipe\",\n                ),\n            }\n        };\n        convert_generated_ldmatrix(ctx, rewriter, self.get_operation(), recipe.0, recipe.1, recipe.2)\n    }\n}\n\n",
+        );
+        for record in ldmatrix(catalog) {
+            let Some((op_type, _)) = ldmatrix_compat_op(record) else {
+                continue;
+            };
+            let variant = &record
+                .ldmatrix
+                .as_ref()
+                .expect("ldmatrix compatibility record")
+                .variant;
+            let register_count = variant.register_count();
+            let instruction_head = expected_ptx_head(record);
+            let intrinsic_name = record.resolved_llvm_identifier();
+            writeln!(
+                output,
+                "#[op_interface_impl]\nimpl MirToLlvmConversion for {op_type} {{\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {{\n        convert_generated_ldmatrix(\n            ctx, rewriter, self.get_operation(), {register_count}, {instruction_head:?}, {intrinsic_name:?},\n        )\n    }}\n}}\n"
+            )
+            .unwrap();
+        }
+    }
+    output
+}
+
+fn stmatrix_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in stmatrices(catalog) {
+        let (multiplicity, layout) = stmatrix_variant(record).expect("stmatrix variant");
+        let count = multiplicity.register_count();
+        let transposed = layout == StmatrixLayout::Transposed;
+        let intrinsic_name = record.resolved_llvm_identifier();
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {{\n        convert_generated_stmatrix(\n            ctx, rewriter, self.get_operation(), {count}, {transposed}, {intrinsic_name:?},\n        )\n    }}\n}}\n"
+        )
+        .unwrap();
+    }
+    output
+}
+
+fn movmatrix_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if let Some(record) = movmatrix(catalog).next() {
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {{\n        let op = self.get_operation();\n        let operands: Vec<_> = op.deref(ctx).operands().collect();\n        if operands.len() != 1 {{\n            return pliron::input_err_noloc!(\n                \"movmatrix_trans_b16 requires 1 operand, got {{}}\",\n                operands.len()\n            );\n        }}\n        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);\n        let asm = inline_asm_convergent(\n            ctx, rewriter, op, result_ty.into(), operands, {:?}, \"=r,r\",\n        );\n        rewriter.replace_operation(ctx, op, asm);\n        Ok(())\n    }}\n}}\n",
+            record.dialect.op_type,
+            movmatrix_template(record),
+        )
+        .unwrap();
+    }
+    output
+}
+
+fn register_mma_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if register_mmas(catalog).next().is_some() {
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for RegisterMmaOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let operation = self.operation_or_multiply(ctx);\n        let kind = self.kind_or_inferred(ctx);\n        let recipe = match (\n            self.get_attr_nvvm_register_mma_shape(ctx).as_deref(),\n            operation,\n            kind,\n            self.get_attr_nvvm_register_mma_accumulator(ctx).as_deref(),\n            self.get_attr_nvvm_register_mma_a_element(ctx).as_deref(),\n            self.get_attr_nvvm_register_mma_b_element(ctx).as_deref(),\n            self.get_attr_nvvm_register_mma_a_layout(ctx).as_deref(),\n            self.get_attr_nvvm_register_mma_b_layout(ctx).as_deref(),\n            self.get_attr_nvvm_register_mma_overflow(ctx).as_deref(),\n        ) {\n",
+        );
+        for record in register_mmas(catalog) {
+            let (
+                shape,
+                operation,
+                kind,
+                accumulator,
+                a_element,
+                b_element,
+                a_layout,
+                b_layout,
+                overflow,
+            ) = register_mma_attr_variants(record);
+            let (c_count, a_count, b_count, result_count) = register_mma_fragment_counts(record);
+            let expected_operands =
+                c_count + a_count + b_count + register_mma_extra_operand_count(record);
+            writeln!(
+                output,
+                "            (Some(&{shape}), {operation}, {kind}, Some(&{accumulator}), Some(&{a_element}), Some(&{b_element}), Some(&{a_layout}), Some(&{b_layout}), Some(&{overflow})) => ({}, {result_count}, {expected_operands}, {:?}, {:?}),",
+                register_mma_result_variant(record),
+                register_mma_template(record),
+                register_mma_constraints(record),
+            )
+            .unwrap();
+        }
+        output.push_str(
+            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.register_mma variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_register_mma(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1, recipe.2, recipe.3, recipe.4,\n        )\n    }\n}\n\n",
+        );
+        for record in
+            register_mmas(catalog).filter(|record| register_mma_compat_op_type(record).is_some())
+        {
+            let op_type = register_mma_compat_op_type(record).unwrap();
+            let (c_count, a_count, b_count, result_count) = register_mma_fragment_counts(record);
+            let expected_operands = c_count + a_count + b_count;
+            writeln!(
+                output,
+                "#[op_interface_impl]\nimpl MirToLlvmConversion for {op_type} {{\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {{\n        convert_generated_register_mma(\n            ctx, rewriter, self.get_operation(), {}, {result_count}, {expected_operands}, {:?}, {:?},\n        )\n    }}\n}}\n",
+                register_mma_result_variant(record),
+                register_mma_template(record),
+                register_mma_constraints(record),
+            )
+            .unwrap();
+        }
+    }
+    output
+}
+
+fn sparse_mma_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if sparse_mmas(catalog).next().is_some() {
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for SparseMmaOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match (\n            self.get_attr_nvvm_sparse_mma_shape(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref(),\n            self.get_attr_nvvm_sparse_mma_selector(ctx).as_deref(),\n        ) {\n",
+        );
+        for record in sparse_mmas(catalog) {
+            let (
+                shape,
+                accumulator,
+                a_element,
+                b_element,
+                a_layout,
+                b_layout,
+                overflow,
+                metadata,
+                selector,
+            ) = sparse_mma_attr_variants(record);
+            let (c_count, a_count, b_count, result_count) = sparse_mma_fragment_counts(record);
+            let expected_operands = c_count + a_count + b_count + 2;
+            writeln!(
+                output,
+                "            (Some(&{shape}), Some(&{accumulator}), Some(&{a_element}), Some(&{b_element}), Some(&{a_layout}), Some(&{b_layout}), Some(&{overflow}), Some(&{metadata}), Some(&{selector})) => ({}, {result_count}, {expected_operands}, {:?}, {:?}),",
+                sparse_mma_result_variant(record),
+                sparse_mma_template(record),
+                sparse_mma_constraints(record),
+            )
+            .unwrap();
+        }
+        output.push_str(
+            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.sparse_mma variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_sparse_mma(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1, recipe.2, recipe.3, recipe.4,\n        )\n    }\n}\n\n",
+        );
+    }
+    output
+}
+
+fn prmt_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if prmts(catalog).next().is_some() {
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for PrmtOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match self.get_attr_nvvm_prmt_mode(ctx).as_deref() {\n",
+        );
+        for record in prmts(catalog) {
+            let prmt = record.prmt.as_ref().unwrap();
+            let mode = match prmt.mode {
+                PrmtMode::Generic => "PrmtModeAttr::Generic",
+                PrmtMode::F4e => "PrmtModeAttr::F4e",
+                PrmtMode::B4e => "PrmtModeAttr::B4e",
+                PrmtMode::Rc8 => "PrmtModeAttr::Rc8",
+                PrmtMode::Ecl => "PrmtModeAttr::Ecl",
+                PrmtMode::Ecr => "PrmtModeAttr::Ecr",
+                PrmtMode::Rc16 => "PrmtModeAttr::Rc16",
+            };
+            let modifier = match prmt.mode {
+                PrmtMode::Generic => "",
+                PrmtMode::F4e => ".f4e",
+                PrmtMode::B4e => ".b4e",
+                PrmtMode::Rc8 => ".rc8",
+                PrmtMode::Ecl => ".ecl",
+                PrmtMode::Ecr => ".ecr",
+                PrmtMode::Rc16 => ".rc16",
+            };
+            let template = match prmt.adapter {
+                PrmtAdapter::DirectThreeOperands => {
+                    format!("prmt.b32{modifier} $0, $1, $2, $3;")
+                }
+                PrmtAdapter::InsertZeroSecondSource => {
+                    format!("prmt.b32{modifier} $0, $1, 0, $2;")
+                }
+            };
+            writeln!(
+                output,
+                "            Some(&{mode}) => ({:?}, {:?}),",
+                record.llvm_identifier(),
+                template
+            )
+            .unwrap();
+        }
+        output.push_str(
+            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.prmt mode has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_prmt(ctx, rewriter, self.get_operation(), recipe.0, recipe.1)\n    }\n}\n\n",
+        );
+    }
+    output
+}
+
+fn scalar_conversion_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if scalar_conversions(catalog).next().is_some() {
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for ScalarConversionOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match (\n            self.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_conversion_saturation(ctx).as_deref(),\n        ) {\n",
+        );
+        for record in scalar_conversions(catalog) {
+            writeln!(
+                output,
+                "            (Some(&{}), Some(&{})) => ({:?}, {:?}),",
+                scalar_conversion_rounding_attr(record),
+                scalar_conversion_saturation_attr(record),
+                record.llvm_identifier(),
+                scalar_conversion_ptx_mnemonic(record),
+            )
+            .unwrap();
+        }
+        output.push_str(
+            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.scalar_conversion variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_scalar_conversion(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1,\n        )\n    }\n}\n\n",
+        );
+    }
+    output
+}
+
+fn scalar_arithmetic_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if scalar_arithmetics(catalog).next().is_some() {
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for ScalarArithmeticOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match (\n            self.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_arithmetic_subnormal(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_arithmetic_saturation(ctx).as_deref(),\n        ) {\n",
+        );
+        for record in scalar_arithmetics(catalog) {
+            writeln!(
+                output,
+                "            (Some(&{}), Some(&{}), Some(&{}), Some(&{}), Some(&{})) => ({:?}, {:?}, {}, {}),",
+                scalar_arithmetic_format_attr(record),
+                scalar_arithmetic_operation_attr(record),
+                scalar_arithmetic_rounding_attr(record),
+                scalar_arithmetic_subnormal_attr(record),
+                scalar_arithmetic_saturation_attr(record),
+                record.llvm_identifier(),
+                scalar_arithmetic_ptx_mnemonic(record),
+                scalar_arithmetic_contract(record).format == ScalarArithmeticFormat::F64,
+                scalar_arithmetic_llvm_mechanism(record)
+                    == BackendLoweringMechanism::InlinePtx,
+            )
+            .unwrap();
+        }
+        output.push_str(
+            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.scalar_arithmetic variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_scalar_arithmetic(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1, recipe.2, recipe.3,\n        )\n    }\n}\n\n",
+        );
+    }
+    output
+}
+
+fn scalar_math_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if scalar_maths(catalog).next().is_some() {
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for ScalarMathOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match (\n            self.get_attr_nvvm_scalar_math_format(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_math_operation(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_math_precision(ctx).as_deref(),\n            self.get_attr_nvvm_scalar_math_subnormal(ctx).as_deref(),\n        ) {\n",
+        );
+        for record in scalar_maths(catalog) {
+            // PTX-native records carry no LLVM symbol. The identifier is
+            // only consumed by the typed route, which such records never
+            // take (their mechanism is always inline PTX), so render an
+            // empty name; the lowering helper rejects it defensively.
+            let intrinsic_name = if record.llvm.is_some() {
+                record.llvm_identifier()
+            } else {
+                String::new()
+            };
+            writeln!(
+                output,
+                "            (Some(&{}), Some(&{}), Some(&{}), Some(&{})) => ({:?}, {:?}, {}, {}, {}),",
+                scalar_math_format_attr(record),
+                scalar_math_operation_attr(record),
+                scalar_math_precision_attr(record),
+                scalar_math_subnormal_attr(record),
+                intrinsic_name,
+                scalar_math_ptx_mnemonic(record),
+                scalar_math_contract(record).format == ScalarMathFormat::F16,
+                scalar_math_contract(record).format == ScalarMathFormat::F64,
+                scalar_math_llvm_mechanism(record) == BackendLoweringMechanism::InlinePtx,
+            )
+            .unwrap();
+        }
+        output.push_str(
+            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.scalar_math variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_scalar_math(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1, recipe.2, recipe.3, recipe.4,\n        )\n    }\n}\n\n",
+        );
+    }
+    output
+}
+
+fn extended_minmax_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if extended_minmax(catalog).next().is_some() {
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for ExtendedMinMaxOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match (\n            self.get_attr_nvvm_extended_minmax_format(ctx).as_deref(),\n            self.get_attr_nvvm_extended_minmax_operation(ctx).as_deref(),\n            self.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref(),\n            self.get_attr_nvvm_extended_minmax_nan(ctx).as_deref(),\n            self.get_attr_nvvm_extended_minmax_xorsign_abs(ctx).as_deref(),\n        ) {\n",
+        );
+        for record in extended_minmax(catalog) {
+            writeln!(
+                output,
+                "            (Some(&{}), Some(&{}), Some(&{}), Some(&{}), Some(&{})) => ({:?}, {}),",
+                extended_minmax_format_attr(record),
+                extended_minmax_operation_attr(record),
+                extended_minmax_subnormal_attr(record),
+                extended_minmax_nan_attr(record),
+                extended_minmax_xorsign_abs_attr(record),
+                extended_minmax_ptx_mnemonic(record),
+                extended_minmax_carrier(record),
+            )
+            .unwrap();
+        }
+        output.push_str(
+            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.extended_minmax variant has no generated lowering recipe\",\n            ),\n        };\n        convert_generated_extended_minmax(\n            ctx, rewriter, self.get_operation(), recipe.0, recipe.1,\n        )\n    }\n}\n\n",
+        );
+    }
+    output
+}
+
+fn cluster_barrier_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if cluster_barriers(catalog).next().is_some() {
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for ClusterBarrierOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let recipe = match self.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() {\n",
+        );
+        for record in cluster_barriers(catalog) {
+            writeln!(
+                output,
+                "            Some(&{}) => ({:?}, {:?}),",
+                cluster_barrier_attr(record),
+                record.llvm_identifier(),
+                cluster_barrier_template(record)
+            )
+            .unwrap();
+        }
+        output.push_str(
+            "            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.cluster_barrier mode has no generated lowering recipe\",\n            ),\n        };\n        let op = self.get_operation();\n        let void_ty = llvm_types::VoidType::get(ctx);\n        match context::lowering_options(ctx).intrinsic_backend {\n            IntrinsicBackend::LlvmNvptx => {\n                let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);\n                call_intrinsic(ctx, rewriter, op, recipe.0, function_ty, vec![])?;\n            }\n            IntrinsicBackend::LibNvvm => {\n                inline_asm_convergent(ctx, rewriter, op, void_ty.into(), vec![], recipe.1, \"~{memory}\");\n            }\n        }\n        rewriter.erase_operation(ctx, op);\n        Ok(())\n    }\n}\n\n",
+        );
+
+        let arrive = cluster_barriers(catalog)
+            .find(|record| {
+                record
+                    .cluster_barrier
+                    .as_ref()
+                    .is_some_and(|barrier| barrier.mode == ClusterBarrierMode::ArriveAligned)
+            })
+            .expect("aligned cluster arrival");
+        let wait = cluster_barriers(catalog)
+            .find(|record| {
+                record
+                    .cluster_barrier
+                    .as_ref()
+                    .is_some_and(|barrier| barrier.mode == ClusterBarrierMode::WaitAligned)
+            })
+            .expect("aligned cluster wait");
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for ClusterSyncOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        let void_ty = llvm_types::VoidType::get(ctx);\n        match context::lowering_options(ctx).intrinsic_backend {\n            IntrinsicBackend::LlvmNvptx => {\n                let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);\n",
+        );
+        writeln!(
+            output,
+            "                call_intrinsic(ctx, rewriter, op, {:?}, function_ty, vec![])?;",
+            arrive.llvm_identifier()
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "                call_intrinsic(ctx, rewriter, op, {:?}, function_ty, vec![])?;",
+            wait.llvm_identifier()
+        )
+        .unwrap();
+        output.push_str("            }\n            IntrinsicBackend::LibNvvm => {\n");
+        writeln!(
+            output,
+            "                inline_asm_convergent(ctx, rewriter, op, void_ty.into(), vec![], {:?}, \"~{{memory}}\");",
+            format!(
+                "{} {}",
+                cluster_barrier_template(arrive),
+                cluster_barrier_template(wait)
+            )
+        )
+        .unwrap();
+        output.push_str(
+            "            }\n        }\n        rewriter.erase_operation(ctx, op);\n        Ok(())\n    }\n}\n\n",
+        );
+    }
+    output
+}
+
+fn wgmma_control_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if wgmma_controls(catalog).next().is_some() {
+        output.push_str(
+            "fn convert_generated_wgmma_control(\n\
+                 ctx: &mut Context,\n\
+                 rewriter: &mut DialectConversionRewriter,\n\
+                 op: Ptr<Operation>,\n\
+                 intrinsic_name: &str,\n\
+                 ptx: &str,\n\
+                 has_immediate: bool,\n\
+             ) -> Result<()> {\n\
+                 let operands: Vec<_> = op.deref(ctx).operands().collect();\n\
+                 if operands.len() != usize::from(has_immediate) {\n\
+                     return pliron::input_err!(\n\
+                         op.deref(ctx).loc(),\n\
+                         \"generated WGMMA control has the wrong operand count\",\n\
+                     );\n\
+                 }\n\
+                 let void_ty = llvm_types::VoidType::get(ctx);\n\
+                 match context::lowering_options(ctx).intrinsic_backend {\n\
+                     IntrinsicBackend::LlvmNvptx => {\n\
+                         let arguments = if has_immediate {\n\
+                             vec![IntegerType::get(ctx, 64, Signedness::Signless).into()]\n\
+                         } else {\n\
+                             vec![]\n\
+                         };\n\
+                         let function_ty = llvm_types::FuncType::get(\n\
+                             ctx, void_ty.into(), arguments, false,\n\
+                         );\n\
+                         call_intrinsic(\n\
+                             ctx, rewriter, op, intrinsic_name, function_ty, operands,\n\
+                         )?;\n\
+                     }\n\
+                     IntrinsicBackend::LibNvvm => {\n\
+                         let constraints = if has_immediate {\n\
+                             \"n,~{memory}\"\n\
+                         } else {\n\
+                             \"~{memory}\"\n\
+                         };\n\
+                         inline_asm_convergent(\n\
+                             ctx, rewriter, op, void_ty.into(), operands, ptx, constraints,\n\
+                         );\n\
+                     }\n\
+                 }\n\
+                 rewriter.erase_operation(ctx, op);\n\
+                 Ok(())\n\
+             }\n\n",
+        );
+        for record in wgmma_controls(catalog) {
+            let has_immediate = record
+                .wgmma_control
+                .as_ref()
+                .is_some_and(|control| control.mode == WgmmaControlMode::WaitGroup);
+            writeln!(
+                output,
+                "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {{\n        convert_generated_wgmma_control(\n            ctx, rewriter, self.get_operation(), {:?}, {:?}, {has_immediate},\n        )\n    }}\n}}\n",
+                record.dialect.op_type,
+                record.llvm_identifier(),
+                wgmma_control_template(record),
+            )
+            .unwrap();
+        }
+    }
+    output
+}
+
+fn packed_atomic_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    if packed_atomics(catalog).next().is_some() {
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for PackedAtomicAddOp {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let format = self.get_attr_nvvm_packed_atomic_format(ctx);\n        let state_space = self.get_attr_nvvm_packed_atomic_state_space(ctx);\n        let ordering = self.get_attr_nvvm_packed_atomic_ordering(ctx);\n        let scope = self.get_attr_nvvm_packed_atomic_scope(ctx);\n        let rounding = self.get_attr_nvvm_packed_atomic_rounding(ctx);\n        let subnormal = self.get_attr_nvvm_packed_atomic_subnormal(ctx);\n        let atomicity = self.get_attr_nvvm_packed_atomic_atomicity(ctx);\n        let ptx_type = match (format.as_deref(), state_space.as_deref(), ordering.as_deref(), scope.as_deref(), rounding.as_deref(), subnormal.as_deref(), atomicity.as_deref()) {\n            (Some(&PackedAtomicFormatAttr::F16x2), Some(&PackedAtomicStateSpaceAttr::Global), Some(&PackedAtomicOrderingAttr::Relaxed), Some(&PackedAtomicScopeAttr::Gpu), Some(&PackedAtomicRoundingAttr::Rn), Some(&PackedAtomicSubnormalAttr::NoFtz), Some(&PackedAtomicAtomicityAttr::PerElement)) => \"f16x2\",\n            (Some(&PackedAtomicFormatAttr::Bf16x2), Some(&PackedAtomicStateSpaceAttr::Global), Some(&PackedAtomicOrderingAttr::Relaxed), Some(&PackedAtomicScopeAttr::Gpu), Some(&PackedAtomicRoundingAttr::Rn), Some(&PackedAtomicSubnormalAttr::NoFtz), Some(&PackedAtomicAtomicityAttr::PerElement)) => \"bf16x2\",\n            _ => return pliron::input_err!(\n                self.get_operation().deref(ctx).loc(),\n                \"nvvm.packed_atomic_add attributes have no generated lowering recipe\",\n            ),\n        };\n        convert_packed_atom_add(ctx, rewriter, self.get_operation(), ptx_type)\n    }\n}\n\n",
+        );
+        output = output.replace(
+            "        convert_packed_atom_add(ctx, rewriter, self.get_operation(), ptx_type)",
+            "        drop((format, state_space, ordering, scope, rounding, subnormal, atomicity));\n        convert_packed_atom_add(ctx, rewriter, self.get_operation(), ptx_type)",
+        );
+        output.push_str(
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for NvvmAtomAddF16x2Op {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        convert_packed_atom_add(ctx, rewriter, self.get_operation(), \"f16x2\")\n    }\n}\n\n#[op_interface_impl]\nimpl MirToLlvmConversion for NvvmAtomAddBf16x2Op {\n    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        convert_packed_atom_add(ctx, rewriter, self.get_operation(), \"bf16x2\")\n    }\n}\n\n",
+        );
+    }
+    output
+}
+
+fn redux_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in redux(catalog) {
+        debug_assert_eq!(
+            record.redux.as_ref().unwrap().adapter,
+            ReduxAdapter::MaskValueToSourceMemberMask
+        );
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        writeln!(
+            output,
+            "        convert_redux(ctx, rewriter, self.get_operation(), operands_info, {:?})",
+            record.llvm_identifier()
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn vote_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in vote_intrinsics(catalog) {
+        debug_assert_eq!(
+            record.vote.as_ref().unwrap().adapter,
+            VoteAdapter::DirectMaskPredicate
+        );
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        writeln!(
+            output,
+            "        convert_vote(ctx, rewriter, self.get_operation(), operands_info, {:?})",
+            record.llvm_identifier()
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn warp_match_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in warp_matches(catalog) {
+        let warp_match = record.warp_match.as_ref().unwrap();
+        let helper = match warp_match.adapter {
+            WarpMatchAdapter::DirectMask => "convert_match_any",
+            WarpMatchAdapter::ProjectMaskDiscardPredicate => "convert_match_all",
+        };
+        let value_width = warp_match.value_width.bits();
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        writeln!(
+            output,
+            "        let value_ty = IntegerType::get(ctx, {value_width}, Signedness::Signless);"
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "        {helper}(ctx, rewriter, self.get_operation(), operands_info, {:?}, value_ty.into())",
+            record.llvm_identifier()
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn elect_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in elect_intrinsics(catalog) {
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        match context::lowering_options(ctx).intrinsic_backend {\n",
+        );
+        for (backend, variant) in [
+            (IntrinsicBackend::LlvmNvptx, "LlvmNvptx"),
+            (IntrinsicBackend::LibNvvm, "LibNvvm"),
+        ] {
+            let mechanism = record
+                .backend_lowerings
+                .iter()
+                .find(|route| route.backend == backend)
+                .expect("elect backend route")
+                .mechanism;
+            writeln!(output, "            IntrinsicBackend::{variant} => {{").unwrap();
+            match mechanism {
+                BackendLoweringMechanism::TypedNvvm => writeln!(
+                    output,
+                    "                convert_elect_sync_typed(ctx, rewriter, self.get_operation(), operands_info, {:?})",
+                    record.llvm_identifier()
+                )
+                .unwrap(),
+                BackendLoweringMechanism::InlinePtx => output.push_str(
+                    "                convert_elect_sync_inline(ctx, rewriter, self.get_operation(), operands_info)\n",
+                ),
+            }
+            output.push_str("            }\n");
+        }
+        output.push_str("        }\n    }\n}\n\n");
+    }
+    output
+}
+
+fn warp_barrier_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in warp_barriers(catalog) {
+        debug_assert_eq!(
+            record.warp_barrier.as_ref().unwrap().adapter,
+            WarpBarrierAdapter::DirectMemberMask
+        );
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        convert_bar_warp_sync(ctx, rewriter, self.get_operation(), operands_info)\n    }\n}\n\n",
+        );
+    }
+    output
+}
+
+fn warp_shuffle_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in warp_shuffles(catalog) {
+        let shuffle = record.warp_shuffle.as_ref().unwrap();
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        match shuffle.value_kind {
+            WarpShuffleValueKind::I32 | WarpShuffleValueKind::F32 => {
+                debug_assert_eq!(
+                    shuffle.adapter,
+                    WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp
+                );
+                let helper = match shuffle.value_kind {
+                    WarpShuffleValueKind::I32 => "convert_shuffle_i32",
+                    WarpShuffleValueKind::F32 => "convert_shuffle_f32",
+                    WarpShuffleValueKind::I64 => unreachable!(),
+                };
+                writeln!(
+                    output,
+                    "        {helper}(ctx, rewriter, self.get_operation(), operands_info, {:?}, {})",
+                    record.llvm_identifier(),
+                    shuffle.clamp,
+                )
+                .unwrap();
+            }
+            WarpShuffleValueKind::I64 => {
+                debug_assert_eq!(
+                    shuffle.adapter,
+                    WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
+                );
+                let mode = match shuffle.mode {
+                    WarpShuffleMode::Idx => "idx",
+                    WarpShuffleMode::Bfly => "bfly",
+                    WarpShuffleMode::Down => "down",
+                    WarpShuffleMode::Up => "up",
+                };
+                writeln!(
+                    output,
+                    "        convert_shuffle_i64(ctx, rewriter, self.get_operation(), operands_info, {mode:?}, {})",
+                    shuffle.clamp,
+                )
+                .unwrap();
+            }
+        }
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn packed_alu_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in packed_alus(catalog) {
+        let width = packed_alu_width(record);
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        writeln!(
+            output,
+            "        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), {:?}, {width})",
+            packed_alu_ptx_mnemonic(record),
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn integer_minmax_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in integer_minmaxes(catalog) {
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        writeln!(
+            output,
+            "        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), {:?})",
+            integer_minmax_ptx_mnemonic(record)
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn packed_conversion_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in packed_conversions(catalog) {
+        let conversion = record
+            .packed_conversion
+            .as_ref()
+            .expect("packed-conversion record");
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        match conversion.source_format {
+            PackedConversionSourceFormat::F32x2 => {
+                debug_assert_eq!(
+                    conversion.adapter,
+                    PackedConversionAdapter::ReverseHighLowOperands
+                );
+                let typed_intrinsic = packed_conversion_typed_llvm_name(record)
+                    .map(|name| format!("Some({name:?})"))
+                    .unwrap_or_else(|| "None".into());
+                writeln!(
+                    output,
+                    "        convert_generated_packed_f32x2(ctx, rewriter, self.get_operation(), {typed_intrinsic}, {:?}, {})",
+                    packed_conversion_ptx_mnemonic(record),
+                    packed_conversion_result_width(record),
+                )
+                .unwrap();
+            }
+            PackedConversionSourceFormat::E4m3x2
+            | PackedConversionSourceFormat::E5m2x2
+            | PackedConversionSourceFormat::F16x2 => {
+                debug_assert_eq!(conversion.adapter, PackedConversionAdapter::Identity);
+                writeln!(
+                    output,
+                    "        convert_generated_packed_unary(ctx, rewriter, self.get_operation(), {:?}, {}, {})",
+                    packed_conversion_ptx_mnemonic(record),
+                    packed_conversion_result_width(record),
+                    packed_conversion_source_width(record),
+                )
+                .unwrap();
+            }
+        }
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn cp_async_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in cp_async_copies(catalog) {
+        let copy = record.cp_async_copy.as_ref().unwrap();
+        let cache_policy = match copy.cache_policy {
+            CpAsyncCachePolicy::Ca => "ca",
+            CpAsyncCachePolicy::Cg => "cg",
+        };
+        let has_source_size = copy.source_size == CpAsyncSourceSize::Runtime;
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        writeln!(
+            output,
+            "        convert_generated_cp_async_copy(ctx, rewriter, self.get_operation(), {cache_policy:?}, {}, {has_source_size}, {:?})",
+            copy.copy_size.bytes(),
+            record.llvm_identifier(),
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    for record in cp_async_controls(catalog) {
+        let operation = match record.cp_async_control.as_ref().unwrap().operation {
+            CpAsyncControlOperation::CommitGroup => "commit_group",
+            CpAsyncControlOperation::WaitAll => "wait_all",
+            CpAsyncControlOperation::WaitGroup => "wait_group",
+        };
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        writeln!(
+            output,
+            "        convert_generated_cp_async_control(ctx, rewriter, self.get_operation(), {operation:?}, {:?})",
+            record.llvm_identifier(),
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    for record in cp_async_mbarriers(catalog) {
+        let bridge = record.cp_async_mbarrier.as_ref().unwrap();
+        let operation = match bridge.operation {
+            CpAsyncMbarrierOperation::Arrive => "arrive",
+            CpAsyncMbarrierOperation::ArriveNoInc => "arrive_no_inc",
+        };
+        let state_space = match bridge.state_space {
+            CpAsyncMbarrierStateSpace::Generic => "generic",
+            CpAsyncMbarrierStateSpace::Shared => "shared",
+        };
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        writeln!(
+            output,
+            "        convert_generated_cp_async_mbarrier(ctx, rewriter, self.get_operation(), {operation:?}, {state_space:?}, {:?})",
+            record.llvm_identifier(),
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn mbarrier_basic_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in mbarrier_basics(catalog) {
+        let mbarrier = record.mbarrier_basic.as_ref().unwrap();
+        let helper = match (mbarrier.operation, mbarrier.adapter) {
+            (MbarrierBasicOperation::Init, MbarrierBasicAdapter::InitPointerCountToVoid) => {
+                "convert_init"
+            }
+            (MbarrierBasicOperation::Arrive, MbarrierBasicAdapter::ArrivePointerToToken) => {
+                "convert_arrive"
+            }
+            (
+                MbarrierBasicOperation::TestWait,
+                MbarrierBasicAdapter::TestWaitPointerTokenToPredicate,
+            ) => "convert_test_wait",
+            (MbarrierBasicOperation::Inval, MbarrierBasicAdapter::InvalPointerToVoid) => {
+                "convert_inval"
+            }
+            _ => unreachable!("resolver admitted an invalid basic mbarrier adapter"),
+        };
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        writeln!(
+            output,
+            "        {helper}(ctx, rewriter, self.get_operation(), operands_info)"
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn cluster_memory_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in cluster_memory(catalog) {
+        let cluster = record.cluster_memory.as_ref().unwrap();
+        let (template, constraints) =
+            crate::resolve::cluster_memory_inline_recipe(cluster.operation);
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        let operands: Vec<_> = op.deref(ctx).operands().collect();\n",
+        );
+        writeln!(
+            output,
+            "        if operands.len() != 2 {{\n            return pliron::input_err_noloc!({:?}, operands.len());\n        }}",
+            format!("{} requires 2 operands, got {{}}", record.rust.name)
+        )
+        .unwrap();
+        output.push_str(
+            "        let shared_pointer = cast_to_shared_addrspace(ctx, rewriter, operands[0]);\n        let rank = operands[1];\n",
+        );
+        match cluster.operation {
+            ClusterMemoryOperation::MapSharedRank => {
+                writeln!(
+                    output,
+                    "        let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);\n        let asm = inline_asm_convergent(\n            ctx, rewriter, op, i64_ty.into(), vec![shared_pointer, rank], {template:?}, {constraints:?},\n        );\n        let mapped = asm.deref(ctx).get_result(0);\n        let cluster_shared_pointer_ty = llvm_types::PointerType::get(ctx, 7);\n        let int_to_ptr = llvm_ops::IntToPtrOp::new(ctx, mapped, cluster_shared_pointer_ty.into());\n        rewriter.insert_operation(ctx, int_to_ptr.get_operation());\n        rewriter.replace_operation(ctx, op, int_to_ptr.get_operation());\n        Ok(())"
+                )
+                .unwrap();
+            }
+            ClusterMemoryOperation::ReadU32 => {
+                writeln!(
+                    output,
+                    "        let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);\n        let asm = inline_asm_convergent(\n            ctx, rewriter, op, i32_ty.into(), vec![shared_pointer, rank], {template:?}, {constraints:?},\n        );\n        rewriter.replace_operation(ctx, op, asm);\n        Ok(())"
+                )
+                .unwrap();
+            }
+        }
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn mbarrier_extended_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in mbarrier_extended(catalog) {
+        let contract = record.mbarrier_extended.as_ref().unwrap();
+        let (template, constraints) =
+            crate::resolve::mbarrier_extended_inline_recipe(contract.operation);
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        let mutability = if matches!(
+            contract.adapter,
+            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount
+                | MbarrierExtendedAdapter::PointerTokenToPredicate
+                | MbarrierExtendedAdapter::PointerParityToPredicate
+        ) {
+            "mut "
+        } else {
+            ""
+        };
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n",
+        );
+        writeln!(
+            output,
+            "        let {mutability}operands: Vec<_> = op.deref(ctx).operands().collect();"
+        )
+        .unwrap();
+        let operand_count = record.dialect.operands.len();
+        let operand_count_check = if operand_count == 0 {
+            "!operands.is_empty()".to_owned()
+        } else {
+            format!("operands.len() != {operand_count}")
+        };
+        writeln!(
+            output,
+            "        if {operand_count_check} {{\n            return pliron::input_err_noloc!({:?}, operands.len());\n        }}",
+            format!(
+                "{} requires {} operands, got {{}}",
+                record.rust.name,
+                operand_count
+            )
+        )
+        .unwrap();
+        if matches!(
+            contract.adapter,
+            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount
+                | MbarrierExtendedAdapter::PointerTokenToPredicate
+                | MbarrierExtendedAdapter::PointerParityToPredicate
+        ) {
+            output.push_str(
+                "        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);\n",
+            );
+        }
+        match contract.adapter {
+            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount => {
+                writeln!(
+                    output,
+                    "        let result_ty = IntegerType::get(ctx, 64, Signedness::Signless);\n        let asm = inline_asm_convergent(ctx, rewriter, op, result_ty.into(), operands, {template:?}, {constraints:?});\n        rewriter.replace_operation(ctx, op, asm);\n        Ok(())"
+                )
+                .unwrap();
+            }
+            MbarrierExtendedAdapter::PointerTokenToPredicate
+            | MbarrierExtendedAdapter::PointerParityToPredicate => {
+                writeln!(
+                    output,
+                    "        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);\n        let asm = inline_asm_convergent(ctx, rewriter, op, result_ty.into(), operands, {template:?}, {constraints:?});\n        let asm_result = asm.deref(ctx).get_result(0);\n        let result = trunc_to_i1(ctx, rewriter, asm_result);\n        let DefiningEntity::Op(result_op) = result.defining_entity() else {{ unreachable!() }};\n        rewriter.replace_operation(ctx, op, result_op);\n        Ok(())"
+                )
+                .unwrap();
+            }
+            MbarrierExtendedAdapter::RawClusterAddressToVoid
+            | MbarrierExtendedAdapter::ZeroOperandsToVoid
+            | MbarrierExtendedAdapter::NanosecondsToVoid => {
+                writeln!(
+                    output,
+                    "        let void_ty = llvm_types::VoidType::get(ctx);\n        inline_asm_convergent(ctx, rewriter, op, void_ty.into(), operands, {template:?}, {constraints:?});\n        rewriter.erase_operation(ctx, op);\n        Ok(())"
+                )
+                .unwrap();
+            }
+        }
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn dotprod_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in dot_products(catalog) {
+        let insert_low_half_selector = matches!(
+            record.dot_product.as_ref().unwrap().adapter,
+            DotProductAdapter::InsertLowHalfFalse
+        );
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        writeln!(
+            output,
+            "        convert_generated_dot_product(ctx, rewriter, self.get_operation(), {:?}, {:?}, {insert_low_half_selector})",
+            record.llvm_identifier(),
+            dot_product_ptx(record),
+        )
+        .unwrap();
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn clc_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in clc_intrinsics(catalog) {
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        match record.clc.as_ref().unwrap().operation {
+            ClcOperation::TryCancel | ClcOperation::TryCancelMulticast => {
+                writeln!(
+                    output,
+                    "        convert_generated_clc_try_cancel(ctx, rewriter, self.get_operation(), operands_info, {:?})",
+                    record.llvm_identifier()
+                )
+                .unwrap();
+            }
+            ClcOperation::QueryIsCanceled
+            | ClcOperation::QueryGetFirstCtaidX
+            | ClcOperation::QueryGetFirstCtaidY
+            | ClcOperation::QueryGetFirstCtaidZ => {
+                writeln!(
+                    output,
+                    "        convert_generated_clc_query(ctx, rewriter, self.get_operation(), operands_info, {:?}, {})",
+                    record.llvm_identifier(),
+                    record.clc.as_ref().unwrap().operation == ClcOperation::QueryIsCanceled
+                )
+                .unwrap();
+            }
+        }
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn execution_control_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in execution_controls(catalog) {
+        let operation = ExecutionControlOperation::from_catalog_id(&record.id)
+            .expect("closed execution-control record");
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        match operation {
+            ExecutionControlOperation::BarrierCtaSync
+            | ExecutionControlOperation::BarrierCtaSyncAligned
+            | ExecutionControlOperation::BarrierCtaArrive
+            | ExecutionControlOperation::BarrierCtaArriveAligned => {
+                let template = format!(
+                    "{}.{} $0, $1;",
+                    record.expected_ptx.mnemonic,
+                    record.expected_ptx.modifiers.join(".")
+                );
+                writeln!(
+                    output,
+                    "        convert_counted_barrier(ctx, rewriter, self.get_operation(), operands_info, {:?}, {template:?})",
+                    record.llvm_identifier()
+                )
+                .unwrap();
+            }
+            ExecutionControlOperation::GridDependencyLaunchDependents
+            | ExecutionControlOperation::GridDependencyWait => {
+                let template = format!(
+                    "{}.{};",
+                    record.expected_ptx.mnemonic,
+                    record.expected_ptx.modifiers.join(".")
+                );
+                writeln!(
+                    output,
+                    "        convert_grid_dependency(ctx, rewriter, self.get_operation(), operands_info, {:?}, {template:?})",
+                    record.llvm_identifier()
+                )
+                .unwrap();
+            }
+            ExecutionControlOperation::SetMaxNRegInc | ExecutionControlOperation::SetMaxNRegDec => {
+                let direction = match operation {
+                    ExecutionControlOperation::SetMaxNRegInc => "inc",
+                    ExecutionControlOperation::SetMaxNRegDec => "dec",
+                    _ => unreachable!("setmaxnreg operation was matched"),
+                };
+                output.push_str(
+                    "        let register_count = self.register_count(ctx).ok_or_else(|| pliron::input_error_noloc!(\"setmaxnreg register-count attribute is invalid\"))?;\n",
+                );
+                writeln!(
+                    output,
+                    "        convert_setmaxnreg(ctx, rewriter, self.get_operation(), operands_info, register_count, {:?}, {direction:?})",
+                    record.llvm_identifier()
+                )
+                .unwrap();
+            }
+        }
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn tma_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in tma_intrinsics(catalog) {
+        let operation = record.tma.as_ref().unwrap().operation;
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        match operation {
+            TmaOperation::G2sTile1d
+            | TmaOperation::G2sTile2d
+            | TmaOperation::G2sTile3d
+            | TmaOperation::G2sTile4d
+            | TmaOperation::G2sTile5d => {
+                writeln!(
+                    output,
+                    "        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, {}, false)",
+                    operation.dimensions().unwrap()
+                )
+                .unwrap();
+            }
+            TmaOperation::G2sTile2dMulticast => output.push_str(
+                "        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 2, true)\n",
+            ),
+            TmaOperation::G2sTile2dMulticastCg2 => output.push_str(
+                "        convert_g2s_multicast_cg2(ctx, rewriter, self.get_operation(), operands_info)\n",
+            ),
+            TmaOperation::S2gTile1d
+            | TmaOperation::S2gTile2d
+            | TmaOperation::S2gTile3d
+            | TmaOperation::S2gTile4d
+            | TmaOperation::S2gTile5d => {
+                writeln!(
+                    output,
+                    "        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, {})",
+                    operation.dimensions().unwrap()
+                )
+                .unwrap();
+            }
+            TmaOperation::Reduce => {
+                let reduction = record
+                    .tma
+                    .as_ref()
+                    .and_then(|tma| tma.reduction.as_ref())
+                    .expect("TMA reduction contract");
+                let reduction_name = match reduction.operation {
+                    TmaReductionOperation::Add => "add",
+                    TmaReductionOperation::And => "and",
+                    TmaReductionOperation::Dec => "dec",
+                    TmaReductionOperation::Inc => "inc",
+                    TmaReductionOperation::Max => "max",
+                    TmaReductionOperation::Min => "min",
+                    TmaReductionOperation::Or => "or",
+                    TmaReductionOperation::Xor => "xor",
+                };
+                let load_mode = match reduction.load_mode {
+                    TmaReductionLoadMode::Tile => "tile",
+                    TmaReductionLoadMode::Im2col => "im2col",
+                };
+                writeln!(
+                    output,
+                    "        convert_reduce_s2g(ctx, rewriter, self.get_operation(), operands_info, ReduceConfig::new({}, {reduction_name:?}, {load_mode:?}, {:?}))",
+                    reduction.dimensions,
+                    record.resolved_llvm_identifier()
+                )
+                    .unwrap();
+            }
+            TmaOperation::CommitGroup | TmaOperation::WaitGroup | TmaOperation::WaitGroupRead => {
+                let operation_name = match operation {
+                    TmaOperation::CommitGroup => "commit_group",
+                    TmaOperation::WaitGroup => "wait_group",
+                    TmaOperation::WaitGroupRead => "wait_group_read",
+                    _ => unreachable!("TMA control operation was matched"),
+                };
+                writeln!(
+                    output,
+                    "        convert_control(ctx, rewriter, self.get_operation(), operands_info, {operation_name:?}, {:?})",
+                    record.resolved_llvm_identifier()
+                )
+                .unwrap();
+            }
+            TmaOperation::PrefetchTensorMap => {
+                writeln!(
+                    output,
+                    "        convert_prefetch_tensormap(ctx, rewriter, self.get_operation(), operands_info, {:?})",
+                    record.resolved_llvm_identifier()
+                )
+                .unwrap();
+            }
+            TmaOperation::PrefetchTile1d
+            | TmaOperation::PrefetchTile2d
+            | TmaOperation::PrefetchTile3d
+            | TmaOperation::PrefetchTile4d
+            | TmaOperation::PrefetchTile5d
+            | TmaOperation::PrefetchTileGather4TwoDimensional
+            | TmaOperation::PrefetchTile1dCacheHint
+            | TmaOperation::PrefetchTile2dCacheHint
+            | TmaOperation::PrefetchTile3dCacheHint
+            | TmaOperation::PrefetchTile4dCacheHint
+            | TmaOperation::PrefetchTile5dCacheHint
+            | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint => {
+                writeln!(
+                    output,
+                    "        convert_prefetch_tile(ctx, rewriter, self.get_operation(), operands_info, PrefetchTileConfig::new({}, {}, {}, {:?}))",
+                    operation.prefetch_coordinate_count().unwrap(),
+                    matches!(
+                        operation,
+                        TmaOperation::PrefetchTileGather4TwoDimensional
+                            | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint
+                    ),
+                    operation.uses_prefetch_cache_hint(),
+                    record.resolved_llvm_identifier()
+                )
+                .unwrap();
+            }
+            TmaOperation::ReplaceBoxDim
+            | TmaOperation::ReplaceElementStride
+            | TmaOperation::ReplaceElementType
+            | TmaOperation::ReplaceFillMode
+            | TmaOperation::ReplaceGlobalAddress
+            | TmaOperation::ReplaceGlobalDim
+            | TmaOperation::ReplaceGlobalStride
+            | TmaOperation::ReplaceInterleaveLayout
+            | TmaOperation::ReplaceRank
+            | TmaOperation::ReplaceSwizzleAtomicity
+            | TmaOperation::ReplaceSwizzleMode => {
+                let (field, value_kind, ordinal, immediate) = match operation {
+                    TmaOperation::ReplaceBoxDim => ("box_dim", "u32", true, false),
+                    TmaOperation::ReplaceElementStride => {
+                        ("element_stride", "u32", true, false)
+                    }
+                    TmaOperation::ReplaceElementType => ("elemtype", "u32", false, true),
+                    TmaOperation::ReplaceFillMode => ("fill_mode", "u32", false, true),
+                    TmaOperation::ReplaceGlobalAddress => {
+                        ("global_address", "address", false, false)
+                    }
+                    TmaOperation::ReplaceGlobalDim => ("global_dim", "u32", true, false),
+                    TmaOperation::ReplaceGlobalStride => {
+                        ("global_stride", "u64", true, false)
+                    }
+                    TmaOperation::ReplaceInterleaveLayout => {
+                        ("interleave_layout", "u32", false, true)
+                    }
+                    TmaOperation::ReplaceRank => ("rank", "u32", false, false),
+                    TmaOperation::ReplaceSwizzleAtomicity => {
+                        ("swizzle_atomicity", "u32", false, true)
+                    }
+                    TmaOperation::ReplaceSwizzleMode => {
+                        ("swizzle_mode", "u32", false, true)
+                    }
+                    _ => unreachable!("TMA tensor-map replace operation was matched"),
+                };
+                writeln!(
+                    output,
+                    "        convert_tensormap_replace(ctx, rewriter, self.get_operation(), operands_info, {:?}, {field:?}, {value_kind:?}, {ordinal}, {immediate})",
+                    record.resolved_llvm_identifier()
+                )
+                .unwrap();
+            }
+            TmaOperation::FenceProxyTensorMapAcquireCluster
+            | TmaOperation::FenceProxyTensorMapAcquireCta
+            | TmaOperation::FenceProxyTensorMapAcquireGpu
+            | TmaOperation::FenceProxyTensorMapAcquireSystem
+            | TmaOperation::FenceProxyTensorMapReleaseCluster
+            | TmaOperation::FenceProxyTensorMapReleaseCta
+            | TmaOperation::FenceProxyTensorMapReleaseGpu
+            | TmaOperation::FenceProxyTensorMapReleaseSystem => {
+                let (acquire, scope) = match operation {
+                    TmaOperation::FenceProxyTensorMapAcquireCluster => (true, "cluster"),
+                    TmaOperation::FenceProxyTensorMapAcquireCta => (true, "cta"),
+                    TmaOperation::FenceProxyTensorMapAcquireGpu => (true, "gpu"),
+                    TmaOperation::FenceProxyTensorMapAcquireSystem => (true, "sys"),
+                    TmaOperation::FenceProxyTensorMapReleaseCluster => (false, "cluster"),
+                    TmaOperation::FenceProxyTensorMapReleaseCta => (false, "cta"),
+                    TmaOperation::FenceProxyTensorMapReleaseGpu => (false, "gpu"),
+                    TmaOperation::FenceProxyTensorMapReleaseSystem => (false, "sys"),
+                    _ => unreachable!("TMA tensor-map fence operation was matched"),
+                };
+                writeln!(
+                    output,
+                    "        convert_tensormap_fence(ctx, rewriter, self.get_operation(), operands_info, {:?}, {acquire}, {scope:?})",
+                    record.resolved_llvm_identifier()
+                )
+                .unwrap();
+            }
+        }
+        output.push_str("    }\n}\n\n");
+    }
+    output
+}
+
+fn tcgen05_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in tcgen05_non_mma_intrinsics(catalog) {
+        let operation = record.tcgen05.as_ref().unwrap().operation;
+        let (template, constraints, result_count) = tcgen05_inline_asm(record);
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n",
+        );
+        if let Some(count) = result_count {
+            let integer_results = operation == Tcgen05Operation::Ld;
+            writeln!(
+                output,
+                "        convert_generated_tcgen05_load(ctx, rewriter, self.get_operation(), {}, {count}, {integer_results}, {template:?}, {constraints:?})",
+                record.dialect.operands.len()
+            )
+            .unwrap();
+        } else {
+            writeln!(
+                output,
+                "        convert_generated_tcgen05_void(ctx, rewriter, self.get_operation(), {}, {template:?}, {constraints:?})",
+                record.dialect.operands.len()
+            )
+            .unwrap();
+        }
+        output.push_str("    }\n}\n\n");
+    }
+    if tcgen05_mma_intrinsics(catalog).next().is_some() {
+        output.push_str(
+            r#"#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05MmaOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let form = self
+            .get_attr_nvvm_tcgen05_mma_form(ctx)
+            .as_deref()
+            .cloned();
+        let kind = self
+            .get_attr_nvvm_tcgen05_mma_kind(ctx)
+            .as_deref()
+            .cloned();
+        let cta_group = self
+            .get_attr_nvvm_tcgen05_mma_cta_group(ctx)
+            .as_deref()
+            .cloned();
+        let collector_a = self
+            .get_attr_nvvm_tcgen05_mma_collector_a(ctx)
+            .as_deref()
+            .cloned();
+        let b_buffer = self
+            .get_attr_nvvm_tcgen05_mma_b_buffer(ctx)
+            .as_deref()
+            .cloned();
+        let b_usage = self
+            .get_attr_nvvm_tcgen05_mma_b_usage(ctx)
+            .as_deref()
+            .cloned();
+        let kind = match kind {
+            Some(Tcgen05MmaKindAttr::F16) => "f16",
+            Some(Tcgen05MmaKindAttr::Tf32) => "tf32",
+            Some(Tcgen05MmaKindAttr::F8f6f4) => "f8f6f4",
+            Some(Tcgen05MmaKindAttr::I8) => "i8",
+            None => return pliron::input_err!(
+                op.deref(ctx).loc(),
+                "nvvm.tcgen05_mma requires a kind",
+            ),
+        };
+        let (prefix, a, metadata, zero_mask, constraints, arity, base, ashift) =
+            match form {
+                Some(Tcgen05MmaFormAttr::Shared) =>
+                    ("tcgen05.mma", "$1", None, None, "r,l,l,r,r,~{memory}", 5, true, false),
+                Some(Tcgen05MmaFormAttr::Tensor) =>
+                    ("tcgen05.mma", "[$1]", None, None, "r,r,l,r,r,~{memory}", 5, true, false),
+                Some(Tcgen05MmaFormAttr::TensorAshift) =>
+                    ("tcgen05.mma", "[$1]", None, None, "r,r,l,r,r,~{memory}", 5, true, true),
+                Some(Tcgen05MmaFormAttr::SpShared) =>
+                    ("tcgen05.mma.sp", "$1", Some("$5"), None, "r,l,l,r,r,r,~{memory}", 6, true, false),
+                Some(Tcgen05MmaFormAttr::SpTensor) =>
+                    ("tcgen05.mma.sp", "[$1]", Some("$5"), None, "r,r,l,r,r,r,~{memory}", 6, true, false),
+                Some(Tcgen05MmaFormAttr::SpTensorAshift) =>
+                    ("tcgen05.mma.sp", "[$1]", Some("$5"), None, "r,r,l,r,r,r,~{memory}", 6, true, true),
+                Some(Tcgen05MmaFormAttr::WsShared) =>
+                    ("tcgen05.mma.ws", "$1", None, None, "r,l,l,r,r,~{memory}", 5, false, false),
+                Some(Tcgen05MmaFormAttr::WsSharedZeroColMask) =>
+                    ("tcgen05.mma.ws", "$1", None, Some("$5"), "r,l,l,r,r,l,~{memory}", 6, false, false),
+                Some(Tcgen05MmaFormAttr::WsSpShared) =>
+                    ("tcgen05.mma.ws.sp", "$1", Some("$5"), None, "r,l,l,r,r,r,~{memory}", 6, false, false),
+                Some(Tcgen05MmaFormAttr::WsSpSharedZeroColMask) =>
+                    ("tcgen05.mma.ws.sp", "$1", Some("$5"), Some("$6"), "r,l,l,r,r,r,l,~{memory}", 7, false, false),
+                Some(Tcgen05MmaFormAttr::WsSpTensor) =>
+                    ("tcgen05.mma.ws.sp", "[$1]", Some("$5"), None, "r,r,l,r,r,r,~{memory}", 6, false, false),
+                Some(Tcgen05MmaFormAttr::WsSpTensorZeroColMask) =>
+                    ("tcgen05.mma.ws.sp", "[$1]", Some("$5"), Some("$6"), "r,r,l,r,r,r,l,~{memory}", 7, false, false),
+                Some(Tcgen05MmaFormAttr::WsTensor) =>
+                    ("tcgen05.mma.ws", "[$1]", None, None, "r,r,l,r,r,~{memory}", 5, false, false),
+                Some(Tcgen05MmaFormAttr::WsTensorZeroColMask) =>
+                    ("tcgen05.mma.ws", "[$1]", None, Some("$5"), "r,r,l,r,r,l,~{memory}", 6, false, false),
+                None => return pliron::input_err!(
+                    op.deref(ctx).loc(),
+                    "nvvm.tcgen05_mma requires a form",
+                ),
+            };
+
+        let selector = if base {
+            let group = match cta_group {
+                Some(Tcgen05MmaCtaGroupAttr::Cg1) => 1,
+                Some(Tcgen05MmaCtaGroupAttr::Cg2) => 2,
+                None => return pliron::input_err!(
+                    op.deref(ctx).loc(),
+                    "base tcgen05 MMA requires a CTA-group selector",
+                ),
+            };
+            let usage = match collector_a {
+                Some(Tcgen05MmaCollectorAAttr::Discard) => "discard",
+                Some(Tcgen05MmaCollectorAAttr::LastUse) => "lastuse",
+                Some(Tcgen05MmaCollectorAAttr::Fill) if !ashift => "fill",
+                Some(Tcgen05MmaCollectorAAttr::Use) if !ashift => "use",
+                _ => return pliron::input_err!(
+                    op.deref(ctx).loc(),
+                    "tcgen05 MMA collector-A selector has no generated recipe",
+                ),
+            };
+            format!(
+                ".cta_group::{group}.kind::{kind}.collector::a::{usage}{}",
+                if ashift { ".ashift" } else { "" },
+            )
+        } else {
+            let buffer = match b_buffer {
+                Some(Tcgen05MmaBBufferAttr::B0) => 0,
+                Some(Tcgen05MmaBBufferAttr::B1) => 1,
+                Some(Tcgen05MmaBBufferAttr::B2) => 2,
+                Some(Tcgen05MmaBBufferAttr::B3) => 3,
+                None => return pliron::input_err!(
+                    op.deref(ctx).loc(),
+                    "warp-specialized tcgen05 MMA requires a B-buffer selector",
+                ),
+            };
+            let usage = match b_usage {
+                Some(Tcgen05MmaBUsageAttr::Discard) => "discard",
+                Some(Tcgen05MmaBUsageAttr::LastUse) => "lastuse",
+                Some(Tcgen05MmaBUsageAttr::Fill) => "fill",
+                Some(Tcgen05MmaBUsageAttr::Use) => "use",
+                None => return pliron::input_err!(
+                    op.deref(ctx).loc(),
+                    "warp-specialized tcgen05 MMA requires a B-usage selector",
+                ),
+            };
+            format!(
+                ".cta_group::1.kind::{kind}.collector::b{buffer}::{usage}"
+            )
+        };
+
+        let mut operands = format!("[$0], {a}, $2");
+        if let Some(metadata) = metadata {
+            operands.push_str(&format!(", [{metadata}]"));
+        }
+        operands.push_str(", $3, %enable_pred");
+        if let Some(zero_mask) = zero_mask {
+            operands.push_str(&format!(", {zero_mask}"));
+        }
+        let template = format!(
+            "{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; {prefix}{selector} {operands}; }}"
+        );
+        convert_generated_tcgen05_void(
+            ctx, rewriter, op, arity, &template, constraints,
+        )
+    }
+}
+
+"#,
+        );
+    }
+    output
+}
+
+fn debug_control_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in debug_controls(catalog) {
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        output.push_str(
+            "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        let void_ty = llvm_types::VoidType::get(ctx);\n",
+        );
+        match record.debug_control.as_ref().unwrap().operation {
+            DebugControlOperation::Trap => output.push_str(
+                "        inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], \"trap;\", \"\");\n",
+            ),
+            DebugControlOperation::Breakpoint => output.push_str(
+                "        inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], \"brkpt;\", \"\");\n",
+            ),
+            DebugControlOperation::Pmevent => output.push_str(
+                "        let Some(event_id) = self.event_id(ctx) else {\n\
+                     return pliron::input_err!(\n\
+                         op.deref(ctx).loc(),\n\
+                         \"nvvm.pmevent requires a u32 event ID in 0..=15\",\n\
+                     );\n\
+                 };\n\
+                 let template = format!(\"pmevent {event_id};\");\n\
+                 inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], &template, \"\");\n",
+            ),
+        }
+        output.push_str("        rewriter.erase_operation(ctx, op);\n        Ok(())\n    }\n}\n\n");
+    }
+    output
+}
+
+fn sync_impls(catalog: &CatalogFile) -> String {
+    let mut output = String::new();
+    for record in sync_intrinsics(catalog) {
+        writeln!(
+            output,
+            "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{",
+            record.dialect.op_type
+        )
+        .unwrap();
+        if record.id == "sync_threads" {
+            output.push_str(
+                "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        let void_ty = llvm_types::VoidType::get(ctx);\n        match context::lowering_options(ctx).intrinsic_backend {\n            IntrinsicBackend::LlvmNvptx => {\n                let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);\n                let barrier_id = create_i32_const(ctx, rewriter, 0);\n                let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![i32_ty.into()], false);\n",
+            );
+            writeln!(
+                output,
+                "                call_intrinsic(ctx, rewriter, op, {:?}, function_ty, vec![barrier_id])?;",
+                record.llvm_identifier()
+            )
+            .unwrap();
+            output.push_str(
+                "            }\n            IntrinsicBackend::LibNvvm => {\n                inline_asm_convergent(ctx, rewriter, op, void_ty.into(), vec![], \"bar.sync 0;\", \"~{memory}\");\n            }\n        }\n        rewriter.erase_operation(ctx, op);\n        Ok(())\n    }\n}\n\n",
+            );
+        } else {
+            debug_assert!(threadfence_ptx_level(record).is_some());
+            output.push_str(
+                "    fn convert(\n        &self,\n        ctx: &mut Context,\n        rewriter: &mut DialectConversionRewriter,\n        _operands_info: &OperandsInfo,\n    ) -> Result<()> {\n        let op = self.get_operation();\n        let void_ty = llvm_types::VoidType::get(ctx);\n        let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);\n",
+            );
+            writeln!(
+                output,
+                "        call_intrinsic(ctx, rewriter, op, {:?}, function_ty, vec![])?;",
+                record.llvm_identifier()
+            )
+            .unwrap();
+            output.push_str(
+                "        rewriter.erase_operation(ctx, op);\n        Ok(())\n    }\n}\n\n",
+            );
+        }
+    }
+    output
+}
+
+const LOWERING_GENERATED_DIR: &str = "crates/mir-lower/src/convert/generated_intrinsics";
+
+/// Lowering shards in the old single-file impl emission order. `cp_async`
+/// and `execution_control` coalesce the same catalog families as
+/// `dialect-nvvm/src/ops/generated/`.
+fn lowering_shards(catalog: &CatalogFile) -> Vec<(&'static str, String)> {
+    let mut shards: Vec<(&'static str, String)> = vec![
+        ("sreg", sreg_impls(catalog)),
+        ("active_mask", active_mask_impls(catalog)),
+        ("ldmatrix", ldmatrix_impls(catalog)),
+        ("stmatrix", stmatrix_impls(catalog)),
+        ("movmatrix", movmatrix_impls(catalog)),
+        ("register_mma", register_mma_impls(catalog)),
+        ("sparse_mma", sparse_mma_impls(catalog)),
+        ("prmt", prmt_impls(catalog)),
+        ("scalar_conversion", scalar_conversion_impls(catalog)),
+        ("scalar_arithmetic", scalar_arithmetic_impls(catalog)),
+        ("scalar_math", scalar_math_impls(catalog)),
+        ("extended_minmax", extended_minmax_impls(catalog)),
+        ("cluster_barrier", cluster_barrier_impls(catalog)),
+        ("wgmma_control", wgmma_control_impls(catalog)),
+        ("packed_atomic", packed_atomic_impls(catalog)),
+        ("redux", redux_impls(catalog)),
+        ("vote", vote_impls(catalog)),
+        ("warp_match", warp_match_impls(catalog)),
+        ("elect", elect_impls(catalog)),
+        ("warp_barrier", warp_barrier_impls(catalog)),
+        ("warp_shuffle", warp_shuffle_impls(catalog)),
+        ("packed_alu", packed_alu_impls(catalog)),
+        ("integer_minmax", integer_minmax_impls(catalog)),
+        ("packed_conversion", packed_conversion_impls(catalog)),
+        ("cp_async", cp_async_impls(catalog)),
+        ("mbarrier_basic", mbarrier_basic_impls(catalog)),
+        ("cluster_memory", cluster_memory_impls(catalog)),
+        ("mbarrier_extended", mbarrier_extended_impls(catalog)),
+        ("dotprod", dotprod_impls(catalog)),
+        ("clc", clc_impls(catalog)),
+        ("execution_control", execution_control_impls(catalog)),
+        ("tma", tma_impls(catalog)),
+        ("tcgen05", tcgen05_impls(catalog)),
+        ("debug_control", debug_control_impls(catalog)),
+        ("sync", sync_impls(catalog)),
+    ];
+    shards.retain(|(_, impls)| !impls.is_empty());
+    shards
+}
+
+/// Map every helper a lowering shard may pull from `crate::convert::intrinsics`.
+const LOWERING_INTRINSIC_HELPERS: &[(&str, &str)] = &[
+    ("convert_packed_atom_add", "atomic::convert_packed_atom_add"),
+    (
+        "convert_sreg_read_inline",
+        "basic::convert_sreg_read_inline",
+    ),
+    (
+        "convert_generated_clc_query",
+        "clc::convert_generated_clc_query",
+    ),
+    (
+        "convert_generated_clc_try_cancel",
+        "clc::convert_generated_clc_try_cancel",
+    ),
+    ("call_intrinsic", "common::call_intrinsic"),
+    (
+        "cast_to_shared_addrspace",
+        "common::cast_to_shared_addrspace",
+    ),
+    ("create_i32_const", "common::create_i32_const"),
+    ("inline_asm_convergent", "common::inline_asm_convergent"),
+    ("inline_asm_sideeffect", "common::inline_asm_sideeffect"),
+    ("trunc_to_i1", "common::trunc_to_i1"),
+    (
+        "convert_generated_cp_async_control",
+        "cp_async::convert_generated_cp_async_control",
+    ),
+    (
+        "convert_generated_cp_async_copy",
+        "cp_async::convert_generated_cp_async_copy",
+    ),
+    (
+        "convert_generated_cp_async_mbarrier",
+        "cp_async::convert_generated_cp_async_mbarrier",
+    ),
+    (
+        "convert_generated_dot_product",
+        "dotprod::convert_generated_dot_product",
+    ),
+    (
+        "convert_counted_barrier",
+        "execution_control::convert_counted_barrier",
+    ),
+    (
+        "convert_grid_dependency",
+        "execution_control::convert_grid_dependency",
+    ),
+    (
+        "convert_setmaxnreg",
+        "execution_control::convert_setmaxnreg",
+    ),
+    ("MinMaxCarrier", "extended_minmax::MinMaxCarrier"),
+    (
+        "convert_generated_extended_minmax",
+        "extended_minmax::convert_generated_extended_minmax",
+    ),
+    (
+        "convert_generated_integer_minmax",
+        "integer_minmax::convert_generated_integer_minmax",
+    ),
+    (
+        "convert_generated_ldmatrix",
+        "ldmatrix::convert_generated_ldmatrix",
+    ),
+    ("convert_arrive", "mbarrier::convert_arrive"),
+    ("convert_init", "mbarrier::convert_init"),
+    ("convert_inval", "mbarrier::convert_inval"),
+    ("convert_test_wait", "mbarrier::convert_test_wait"),
+    (
+        "convert_generated_packed_alu",
+        "packed::convert_generated_packed_alu",
+    ),
+    (
+        "convert_generated_packed_f32x2",
+        "packed::convert_generated_packed_f32x2",
+    ),
+    (
+        "convert_generated_packed_unary",
+        "packed::convert_generated_packed_unary",
+    ),
+    ("convert_generated_prmt", "prmt::convert_generated_prmt"),
+    (
+        "convert_generated_scalar_arithmetic",
+        "scalar_arithmetic::convert_generated_scalar_arithmetic",
+    ),
+    (
+        "convert_generated_scalar_conversion",
+        "scalar_conversion::convert_generated_scalar_conversion",
+    ),
+    (
+        "convert_generated_scalar_math",
+        "scalar_math::convert_generated_scalar_math",
+    ),
+    ("PrefetchTileConfig", "tma::PrefetchTileConfig"),
+    ("ReduceConfig", "tma::ReduceConfig"),
+    ("convert_control", "tma::convert_control"),
+    ("convert_g2s", "tma::convert_g2s"),
+    (
+        "convert_g2s_multicast_cg2",
+        "tma::convert_g2s_multicast_cg2",
+    ),
+    (
+        "convert_prefetch_tensormap",
+        "tma::convert_prefetch_tensormap",
+    ),
+    ("convert_prefetch_tile", "tma::convert_prefetch_tile"),
+    ("convert_reduce_s2g", "tma::convert_reduce_s2g"),
+    ("convert_s2g", "tma::convert_s2g"),
+    ("convert_tensormap_fence", "tma::convert_tensormap_fence"),
+    (
+        "convert_tensormap_replace",
+        "tma::convert_tensormap_replace",
+    ),
+    ("convert_active_mask", "warp::convert_active_mask"),
+    ("convert_bar_warp_sync", "warp::convert_bar_warp_sync"),
+    (
+        "convert_elect_sync_inline",
+        "warp::convert_elect_sync_inline",
+    ),
+    ("convert_elect_sync_typed", "warp::convert_elect_sync_typed"),
+    ("convert_match_all", "warp::convert_match_all"),
+    ("convert_match_any", "warp::convert_match_any"),
+    ("convert_redux", "warp::convert_redux"),
+    ("convert_shuffle_f32", "warp::convert_shuffle_f32"),
+    ("convert_shuffle_i32", "warp::convert_shuffle_i32"),
+    ("convert_shuffle_i64", "warp::convert_shuffle_i64"),
+    ("convert_vote", "warp::convert_vote"),
+    ("GeneratedMmaResultType", "wmma::GeneratedMmaResultType"),
+    (
+        "convert_generated_register_mma",
+        "wmma::convert_generated_register_mma",
+    ),
+    (
+        "convert_generated_sparse_mma",
+        "wmma::convert_generated_sparse_mma",
+    ),
+];
+
+fn lowering_push_use_group<S: AsRef<str>>(output: &mut String, root: &str, items: &[S]) {
+    match items {
+        [] => {}
+        [only] => writeln!(output, "use {root}::{};", only.as_ref()).unwrap(),
+        _ => writeln!(
+            output,
+            "use {root}::{{{}}};",
+            items
+                .iter()
+                .map(AsRef::as_ref)
+                .collect::<Vec<_>>()
+                .join(", ")
+        )
+        .unwrap(),
+    }
+}
+
+/// Build the exact `use` list one lowering shard (or the shared-converter
+/// module, with `shard_file` false) needs by scanning its body.
+fn lowering_shard_imports(catalog: &CatalogFile, body: &str, shard_file: bool) -> String {
+    let mut output = String::new();
+    if uses_identifier(body, "MirToLlvmConversion") {
+        output.push_str("use crate::conversion_interface::MirToLlvmConversion;\n");
+    }
+    let helpers: Vec<&str> = LOWERING_INTRINSIC_HELPERS
+        .iter()
+        .filter(|(token, _)| uses_identifier(body, token))
+        .map(|(_, path)| *path)
+        .collect();
+    lowering_push_use_group(&mut output, "crate::convert::intrinsics", &helpers);
+    let mut crate_items = Vec::new();
+    if uses_identifier(body, "IntrinsicBackend") {
+        crate_items.push("IntrinsicBackend");
+    }
+    if body.contains("context::") {
+        crate_items.push("context");
+    }
+    lowering_push_use_group(&mut output, "crate", &crate_items);
+
+    let nvvm: Vec<String> = dialect_nvvm_ops_import_candidates(catalog)
+        .into_iter()
+        .filter(|item| uses_identifier(body, item))
+        .collect();
+    lowering_push_use_group(&mut output, "dialect_nvvm::ops", &nvvm);
+
+    let mut llvm_items = Vec::new();
+    if body.contains("IntToPtrOp::new(") {
+        llvm_items.push("op_interfaces::CastOpInterface");
+    }
+    if body.contains("llvm_ops::") {
+        llvm_items.push("ops as llvm_ops");
+    }
+    if uses_identifier(body, "AsmKind") {
+        llvm_items.push("ops::AsmKind");
+    }
+    if body.contains("llvm_types::") {
+        llvm_items.push("types as llvm_types");
+    }
+    lowering_push_use_group(&mut output, "llvm_export", &llvm_items);
+
+    let builtin: Vec<&str> = ["FP32Type", "IntegerType", "Signedness"]
+        .into_iter()
+        .filter(|item| uses_identifier(body, item))
+        .collect();
+    lowering_push_use_group(&mut output, "pliron::builtin::types", &builtin);
+    let mut context_items = Vec::new();
+    if uses_identifier(body, "Context") {
+        context_items.push("Context");
+    }
+    if uses_identifier(body, "Ptr") {
+        context_items.push("Ptr");
+    }
+    lowering_push_use_group(&mut output, "pliron::context", &context_items);
+    if body.contains("#[op_interface_impl]") {
+        output.push_str("use pliron::derive::op_interface_impl;\n");
+    }
+    let mut conversion_items = Vec::new();
+    if uses_identifier(body, "DialectConversionRewriter") {
+        conversion_items.push("DialectConversionRewriter");
+    }
+    if uses_identifier(body, "OperandsInfo") {
+        conversion_items.push("OperandsInfo");
+    }
+    lowering_push_use_group(
+        &mut output,
+        "pliron::irbuild::dialect_conversion",
+        &conversion_items,
+    );
+    if body.contains(".insert_operation(") {
+        output.push_str("use pliron::irbuild::inserter::Inserter;\n");
+    }
+    if body.contains(".replace_operation(")
+        || body.contains(".replace_operation_with_values(")
+        || body.contains(".erase_operation(")
+    {
+        output.push_str("use pliron::irbuild::rewriter::Rewriter;\n");
+    }
+    if body.contains(".loc()") || body.contains(".set_loc(") {
+        output.push_str("use pliron::location::Located;\n");
+    }
+    if body.contains("::get_concrete_op_info(") || body.contains(".get_operation()") {
+        output.push_str("use pliron::op::Op;\n");
+    }
+    if uses_identifier(body, "Operation") {
+        output.push_str("use pliron::operation::Operation;\n");
+    }
+    if uses_identifier(body, "Result") {
+        output.push_str("use pliron::result::Result;\n");
+    }
+    if uses_identifier(body, "DefiningEntity") {
+        output.push_str("use pliron::value::DefiningEntity;\n");
+    }
+
+    if shard_file {
+        let converters: Vec<&str> = [
+            "convert_generated_stmatrix",
+            "convert_generated_tcgen05_load",
+            "convert_generated_tcgen05_void",
+            "convert_zero_operand_scalar_direct",
+        ]
+        .into_iter()
+        .filter(|item| uses_identifier(body, item))
+        .collect();
+        lowering_push_use_group(&mut output, "super", &converters);
+    }
+    output
+}
+
+fn lowering_shard_file(catalog: &CatalogFile, hash: &str, shard: &str, impls: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    writeln!(
+        output,
+        "//! Generated conversion interfaces: `{shard}` intrinsics.\n"
+    )
+    .unwrap();
+    output.push_str(&lowering_shard_imports(catalog, impls, true));
+    output.push('\n');
+    output.push_str(impls);
+    output
+}
+
+fn lowering_mod_file(
+    catalog: &CatalogFile,
+    hash: &str,
+    shards: &[(&'static str, String)],
+) -> String {
+    let converters = lowering_shared_converters(catalog);
+    let mut output = rust_header(catalog, hash);
+    output
+        .push_str("//! Generated conversion interfaces for admitted CUDA intrinsic families.\n\n");
+    output.push_str(&lowering_shard_imports(catalog, &converters, false));
+    output.push('\n');
+    for (shard, _) in shards {
+        writeln!(output, "mod {shard};").unwrap();
+    }
+    output.push('\n');
+    output.push_str(&converters);
+    output
+}
+
+pub(super) fn render_lowering_files(catalog: &CatalogFile, hash: &str) -> Vec<(PathBuf, String)> {
+    let shards = lowering_shards(catalog);
+    let mut files = vec![(
+        PathBuf::from(format!("{LOWERING_GENERATED_DIR}/mod.rs")),
+        lowering_mod_file(catalog, hash, &shards),
+    )];
+    for (shard, impls) in &shards {
+        files.push((
+            PathBuf::from(format!("{LOWERING_GENERATED_DIR}/{shard}.rs")),
+            lowering_shard_file(catalog, hash, shard, impls),
+        ));
+    }
+    files
+}
+
+#[cfg(test)]
+pub(super) fn render_lowering(catalog: &CatalogFile, hash: &str) -> String {
+    render_lowering_files(catalog, hash)
+        .into_iter()
+        .map(|(_, contents)| contents)
+        .collect::<Vec<_>>()
+        .join("\n")
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/mod.rs b/crates/cuda-intrinsics-gen/src/render/mod.rs
new file mode 100644
index 0000000000..f425bba095
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/mod.rs
@@ -0,0 +1,468 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{CatalogFile, ExtendedMinMaxFormat, IntrinsicBackend, PackedAluFormat};
+#[cfg(test)]
+use crate::render::collector_targets::render_targets;
+use crate::render::collector_targets::{render_collector, render_targets_files};
+use crate::render::common::backend_label;
+use crate::render::compat::{
+    render_compat_clc, render_compat_cluster_barrier, render_compat_cluster_memory,
+    render_compat_cluster_sreg, render_compat_counted_barrier, render_compat_cp_async_copy,
+    render_compat_debug_control, render_compat_dotprod, render_compat_fence,
+    render_compat_float_output, render_compat_grid_dependency, render_compat_integer_minmax,
+    render_compat_ldmatrix, render_compat_mbarrier_basic, render_compat_mbarrier_extended,
+    render_compat_movmatrix, render_compat_packed_alu, render_compat_packed_atomic,
+    render_compat_packed_conversion, render_compat_prmt, render_compat_register_control,
+    render_compat_register_mma, render_compat_scalar_minmax, render_compat_sparse_mma,
+    render_compat_special_register_module, render_compat_sreg, render_compat_stmatrix,
+    render_compat_tcgen05, render_compat_tma, render_compat_wgmma_control,
+};
+use crate::render::dialect::{
+    render_dialect_active_mask, render_dialect_clc, render_dialect_cluster_barrier,
+    render_dialect_cluster_memory, render_dialect_cp_async_copy, render_dialect_debug_control,
+    render_dialect_dotprod, render_dialect_elect, render_dialect_execution_control,
+    render_dialect_extended_minmax, render_dialect_integer_minmax, render_dialect_ldmatrix,
+    render_dialect_mbarrier_basic, render_dialect_mbarrier_extended, render_dialect_mod,
+    render_dialect_movmatrix, render_dialect_packed_alu, render_dialect_packed_atomic,
+    render_dialect_packed_conversion, render_dialect_prmt, render_dialect_redux,
+    render_dialect_register_mma, render_dialect_scalar_arithmetic,
+    render_dialect_scalar_conversion, render_dialect_scalar_math, render_dialect_sparse_mma,
+    render_dialect_sreg, render_dialect_stmatrix, render_dialect_sync, render_dialect_tcgen05,
+    render_dialect_tma, render_dialect_vote, render_dialect_warp_barrier,
+    render_dialect_warp_match, render_dialect_warp_shuffle, render_dialect_wgmma_control,
+};
+use crate::render::families::{
+    clc_intrinsics, cluster_memory, debug_controls, elect_intrinsics, execution_controls,
+    extended_minmax, extended_minmax_contract, integer_minmaxes, mbarrier_extended, movmatrix,
+    scalar_arithmetics, scalar_conversions, scalar_maths, stmatrices, sync_intrinsics,
+    tcgen05_intrinsics, threadfence_ptx_level, tma_intrinsics, wgmma_controls,
+};
+#[cfg(test)]
+use crate::render::importer::render_importer;
+use crate::render::importer::render_importer_files;
+#[cfg(test)]
+use crate::render::lowering::render_lowering;
+use crate::render::lowering::render_lowering_files;
+use crate::render::probes::{render_elect_probe, render_special_register_probe};
+use crate::render::raw_abi::{render_raw_abi, render_raw_mod};
+use crate::render::reference::render_reference;
+use crate::render::validate::validate_renderable;
+use anyhow::Result;
+use std::collections::BTreeMap;
+use std::path::PathBuf;
+
+mod collector_targets;
+mod common;
+mod compat;
+mod dialect;
+mod families;
+mod importer;
+mod lowering;
+mod probes;
+mod raw_abi;
+mod reference;
+#[cfg(test)]
+mod tests;
+mod validate;
+
+pub(crate) use probes::render_probe;
+
+pub fn all_outputs(
+    catalog: &CatalogFile,
+    catalog_json: String,
+    catalog_sha256: &str,
+) -> Result<BTreeMap<PathBuf, String>> {
+    validate_renderable(catalog)?;
+    let mut outputs = BTreeMap::new();
+    outputs.insert("intrinsics/catalog.json".into(), catalog_json);
+    outputs.insert(
+        "crates/cuda-intrinsics/src/generated/mod.rs".into(),
+        render_raw_mod(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        format!(
+            "crates/cuda-intrinsics/src/generated/abi_v{}.rs",
+            catalog.intrinsic_abi
+        )
+        .into(),
+        render_raw_abi(catalog, catalog_sha256)?,
+    );
+    outputs.insert(
+        "crates/cuda-device/src/generated/register_mma.rs".into(),
+        render_compat_register_mma(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/cuda-device/src/generated/ldmatrix.rs".into(),
+        render_compat_ldmatrix(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/cuda-device/src/generated/sparse_mma.rs".into(),
+        render_compat_sparse_mma(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/cuda-device/src/generated/sreg.rs".into(),
+        render_compat_sreg(catalog, catalog_sha256),
+    );
+    for module in ["debug", "grid", "shared", "warp"] {
+        outputs.insert(
+            format!("crates/cuda-device/src/generated/{module}_sreg.rs").into(),
+            render_compat_special_register_module(catalog, catalog_sha256, module),
+        );
+    }
+    outputs.insert(
+        "crates/cuda-device/src/generated/cluster_sreg.rs".into(),
+        render_compat_cluster_sreg(catalog, catalog_sha256),
+    );
+    if sync_intrinsics(catalog).any(|record| threadfence_ptx_level(record).is_some()) {
+        outputs.insert(
+            "crates/cuda-device/src/generated/fence.rs".into(),
+            render_compat_fence(catalog, catalog_sha256),
+        );
+    }
+    outputs.insert(
+        "crates/cuda-device/src/generated/dotprod.rs".into(),
+        render_compat_dotprod(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/cuda-device/src/generated/prmt.rs".into(),
+        render_compat_prmt(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/cuda-device/src/generated/cluster_barrier.rs".into(),
+        render_compat_cluster_barrier(catalog, catalog_sha256),
+    );
+    if cluster_memory(catalog).next().is_some() {
+        outputs.insert(
+            "crates/cuda-device/src/generated/cluster_memory.rs".into(),
+            render_compat_cluster_memory(catalog, catalog_sha256),
+        );
+    }
+    if stmatrices(catalog).next().is_some() {
+        outputs.insert(
+            "crates/cuda-device/src/generated/stmatrix.rs".into(),
+            render_compat_stmatrix(catalog, catalog_sha256),
+        );
+    }
+    if movmatrix(catalog).next().is_some() {
+        outputs.insert(
+            "crates/cuda-device/src/generated/movmatrix.rs".into(),
+            render_compat_movmatrix(catalog, catalog_sha256),
+        );
+    }
+    if wgmma_controls(catalog).next().is_some() {
+        outputs.insert(
+            "crates/cuda-device/src/generated/wgmma_control.rs".into(),
+            render_compat_wgmma_control(catalog, catalog_sha256),
+        );
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/wgmma_control.rs".into(),
+            render_dialect_wgmma_control(catalog, catalog_sha256),
+        );
+    }
+    outputs.insert(
+        "crates/cuda-device/src/generated/atomic.rs".into(),
+        render_compat_packed_atomic(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/cuda-device/src/generated/async_copy.rs".into(),
+        render_compat_cp_async_copy(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/cuda-device/src/generated/mbarrier_basic.rs".into(),
+        render_compat_mbarrier_basic(catalog, catalog_sha256),
+    );
+    if mbarrier_extended(catalog).next().is_some() {
+        outputs.insert(
+            "crates/cuda-device/src/generated/mbarrier_extended.rs".into(),
+            render_compat_mbarrier_extended(catalog, catalog_sha256),
+        );
+    }
+    outputs.insert(
+        "crates/cuda-device/src/generated/bf16x2.rs".into(),
+        render_compat_packed_alu(catalog, catalog_sha256, PackedAluFormat::Bf16x2),
+    );
+    for (module, format) in [
+        ("f16", ExtendedMinMaxFormat::F16),
+        ("bf16", ExtendedMinMaxFormat::Bf16),
+    ] {
+        if extended_minmax(catalog).any(|record| extended_minmax_contract(record).format == format)
+        {
+            outputs.insert(
+                format!("crates/cuda-device/src/generated/{module}.rs").into(),
+                render_compat_scalar_minmax(catalog, catalog_sha256, module),
+            );
+        }
+    }
+    outputs.insert(
+        "crates/cuda-device/src/generated/f16x2.rs".into(),
+        render_compat_packed_alu(catalog, catalog_sha256, PackedAluFormat::F16x2),
+    );
+    for module in ["i16x2", "int"] {
+        if integer_minmaxes(catalog).any(|record| record.rust.module == module) {
+            outputs.insert(
+                format!("crates/cuda-device/src/generated/{module}.rs").into(),
+                render_compat_integer_minmax(catalog, catalog_sha256, module),
+            );
+        }
+    }
+    if integer_minmaxes(catalog).next().is_some() {
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/integer_minmax.rs".into(),
+            render_dialect_integer_minmax(catalog, catalog_sha256),
+        );
+    }
+    outputs.insert(
+        "crates/cuda-device/src/generated/f32x2.rs".into(),
+        render_compat_packed_alu(catalog, catalog_sha256, PackedAluFormat::F32x2),
+    );
+    outputs.insert(
+        "crates/cuda-device/src/generated/convert.rs".into(),
+        render_compat_packed_conversion(
+            catalog,
+            catalog_sha256,
+            "cuda_device::convert::",
+            "convert",
+            ("lo", "hi"),
+        ),
+    );
+    if let Some((path, source)) = render_compat_float_output(catalog, catalog_sha256) {
+        outputs.insert(path, source);
+    }
+    if extended_minmax(catalog).next().is_some() {
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/extended_minmax.rs".into(),
+            render_dialect_extended_minmax(catalog, catalog_sha256),
+        );
+    }
+    if debug_controls(catalog).next().is_some() {
+        outputs.insert(
+            "crates/cuda-device/src/generated/debug_control.rs".into(),
+            render_compat_debug_control(catalog, catalog_sha256),
+        );
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/debug_control.rs".into(),
+            render_dialect_debug_control(catalog, catalog_sha256),
+        );
+    }
+    if clc_intrinsics(catalog).next().is_some() {
+        outputs.insert(
+            "crates/cuda-device/src/generated/clc.rs".into(),
+            render_compat_clc(catalog, catalog_sha256),
+        );
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/clc.rs".into(),
+            render_dialect_clc(catalog, catalog_sha256),
+        );
+    }
+    if tma_intrinsics(catalog).next().is_some() {
+        outputs.insert(
+            "crates/cuda-device/src/generated/tma.rs".into(),
+            render_compat_tma(catalog, catalog_sha256),
+        );
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/tma.rs".into(),
+            render_dialect_tma(catalog, catalog_sha256),
+        );
+    }
+    if execution_controls(catalog).next().is_some() {
+        outputs.insert(
+            "crates/cuda-device/src/generated/counted_barrier.rs".into(),
+            render_compat_counted_barrier(catalog, catalog_sha256),
+        );
+        outputs.insert(
+            "crates/cuda-device/src/generated/grid_dependency.rs".into(),
+            render_compat_grid_dependency(catalog, catalog_sha256),
+        );
+        outputs.insert(
+            "crates/cuda-device/src/generated/register_control.rs".into(),
+            render_compat_register_control(catalog, catalog_sha256),
+        );
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/execution_control.rs".into(),
+            render_dialect_execution_control(catalog, catalog_sha256),
+        );
+    }
+    if tcgen05_intrinsics(catalog).next().is_some() {
+        outputs.insert(
+            "crates/cuda-device/src/generated/tcgen05.rs".into(),
+            render_compat_tcgen05(catalog, catalog_sha256),
+        );
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/tcgen05.rs".into(),
+            render_dialect_tcgen05(catalog, catalog_sha256),
+        );
+    }
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/mod.rs".into(),
+        render_dialect_mod(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/sreg.rs".into(),
+        render_dialect_sreg(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/dotprod.rs".into(),
+        render_dialect_dotprod(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/ldmatrix.rs".into(),
+        render_dialect_ldmatrix(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/register_mma.rs".into(),
+        render_dialect_register_mma(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/sparse_mma.rs".into(),
+        render_dialect_sparse_mma(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/packed_atomic.rs".into(),
+        render_dialect_packed_atomic(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/packed_alu.rs".into(),
+        render_dialect_packed_alu(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/packed_conversion.rs".into(),
+        render_dialect_packed_conversion(catalog, catalog_sha256),
+    );
+    if scalar_conversions(catalog).next().is_some() {
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs".into(),
+            render_dialect_scalar_conversion(catalog, catalog_sha256),
+        );
+    }
+    if scalar_arithmetics(catalog).next().is_some() {
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs".into(),
+            render_dialect_scalar_arithmetic(catalog, catalog_sha256),
+        );
+    }
+    if scalar_maths(catalog).next().is_some() {
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/scalar_math.rs".into(),
+            render_dialect_scalar_math(catalog, catalog_sha256),
+        );
+    }
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/prmt.rs".into(),
+        render_dialect_prmt(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs".into(),
+        render_dialect_cluster_barrier(catalog, catalog_sha256),
+    );
+    if cluster_memory(catalog).next().is_some() {
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/cluster_memory.rs".into(),
+            render_dialect_cluster_memory(catalog, catalog_sha256),
+        );
+    }
+    if stmatrices(catalog).next().is_some() {
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/stmatrix.rs".into(),
+            render_dialect_stmatrix(catalog, catalog_sha256),
+        );
+    }
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/redux.rs".into(),
+        render_dialect_redux(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/sync.rs".into(),
+        render_dialect_sync(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/vote.rs".into(),
+        render_dialect_vote(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/active_mask.rs".into(),
+        render_dialect_active_mask(catalog, catalog_sha256),
+    );
+    if elect_intrinsics(catalog).next().is_some() {
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/elect.rs".into(),
+            render_dialect_elect(catalog, catalog_sha256),
+        );
+    }
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/cp_async.rs".into(),
+        render_dialect_cp_async_copy(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs".into(),
+        render_dialect_mbarrier_basic(catalog, catalog_sha256),
+    );
+    if movmatrix(catalog).next().is_some() {
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/movmatrix.rs".into(),
+            render_dialect_movmatrix(catalog, catalog_sha256),
+        );
+    }
+    if mbarrier_extended(catalog).next().is_some() {
+        outputs.insert(
+            "crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs".into(),
+            render_dialect_mbarrier_extended(catalog, catalog_sha256),
+        );
+    }
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/warp_match.rs".into(),
+        render_dialect_warp_match(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/warp_barrier.rs".into(),
+        render_dialect_warp_barrier(catalog, catalog_sha256),
+    );
+    outputs.insert(
+        "crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs".into(),
+        render_dialect_warp_shuffle(catalog, catalog_sha256),
+    );
+    for (path, contents) in render_importer_files(catalog, catalog_sha256) {
+        outputs.insert(path, contents);
+    }
+    for (path, contents) in render_lowering_files(catalog, catalog_sha256) {
+        outputs.insert(path, contents);
+    }
+    outputs.insert(
+        "crates/rustc-codegen-cuda/src/generated_intrinsics.rs".into(),
+        render_collector(catalog, catalog_sha256),
+    );
+    for (path, contents) in render_targets_files(catalog, catalog_sha256) {
+        outputs.insert(path, contents);
+    }
+    for record in &catalog.intrinsics {
+        if record.special_register.is_some() || record.family == "elect" {
+            for backend in [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm] {
+                outputs.insert(
+                    format!(
+                        "intrinsics/probes/{}.{}.ll",
+                        record.id,
+                        backend_label(backend)
+                    )
+                    .into(),
+                    if record.family == "elect" {
+                        render_elect_probe(catalog, record, catalog_sha256, backend)
+                    } else {
+                        render_special_register_probe(catalog, record, catalog_sha256, backend)
+                    },
+                );
+            }
+        } else {
+            outputs.insert(
+                format!("intrinsics/probes/{}.ll", record.id).into(),
+                render_probe(catalog, record, catalog_sha256),
+            );
+        }
+    }
+    outputs.insert(
+        "intrinsics/generated-reference.md".into(),
+        render_reference(catalog, catalog_sha256),
+    );
+    Ok(outputs)
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/probes.rs b/crates/cuda-intrinsics-gen/src/render/probes.rs
new file mode 100644
index 0000000000..445a14262c
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/probes.rs
@@ -0,0 +1,2050 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogFile, CatalogIntrinsic, ClcAdapter, ClusterMemoryOperation,
+    CpAsyncControlOperation, CpAsyncMbarrierStateSpace, CpAsyncSourceSize, DebugControlOperation,
+    DotProductAdapter, ExecutionControlOperation, ExtendedMinMaxFormat, IntrinsicBackend,
+    MbarrierBasicOperation, MbarrierExtendedAdapter, PackedAtomicFormat,
+    PackedConversionSourceFormat, ReduxAdapter, RegisterMmaAdapter, SparseMmaAccumulator,
+    SpecialRegisterObservation, Tcgen05LdShape, Tcgen05Mma, Tcgen05MmaBUsage, Tcgen05MmaForm,
+    Tcgen05MmaKind, Tcgen05Operation, TmaOperation, VoteAdapter, VoteMode, WarpBarrierAdapter,
+    WarpMatchMode, WarpShuffleAdapter, WarpShuffleMode, WarpShuffleValueKind, WgmmaControlMode,
+};
+use crate::render::common::{backend_label, llvm, llvm_header};
+use crate::render::families::{
+    extended_minmax_contract, extended_minmax_ptx_mnemonic, integer_minmax_ptx_mnemonic,
+    movmatrix_template, packed_alu_ptx_mnemonic, packed_alu_register_constraint, packed_alu_width,
+    packed_conversion_constraint, packed_conversion_dialect_type, packed_conversion_ptx_mnemonic,
+    packed_conversion_source, packed_conversion_source_width, packed_conversion_typed_llvm_name,
+    register_mma_constraints, register_mma_fragment_counts, register_mma_template,
+    scalar_arithmetic_arity, scalar_arithmetic_llvm_mechanism, scalar_arithmetic_llvm_type,
+    scalar_arithmetic_ptx_mnemonic, scalar_math_llvm_mechanism, scalar_math_llvm_type,
+    scalar_math_ptx_mnemonic, sparse_mma_constraints, sparse_mma_fragment_counts,
+    sparse_mma_selector_values, sparse_mma_template, special_register_backend_mechanism,
+    special_register_inline_template, special_register_output_constraint, stmatrix_variant,
+    tcgen05_inline_asm, tcgen05_ld_register_count, tcgen05_mma_inline_asm, tcgen05_mma_is_ws,
+    tcgen05_mma_runtime_parameters, tcgen05_st_register_count, threadfence_ptx_level,
+};
+use std::fmt::Write as _;
+
+pub(super) fn render_special_register_probe(
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+    hash: &str,
+    backend: IntrinsicBackend,
+) -> String {
+    let mut output = llvm_header(catalog, hash);
+    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
+    let width = record.scalar_width().expect("special-register width");
+    let function_name = format!("probe_{}_{}", record.id, backend_label(backend));
+    match special_register_backend_mechanism(record, backend) {
+        BackendLoweringMechanism::TypedNvvm => {
+            let symbol = &record
+                .llvm
+                .as_ref()
+                .expect("typed special-register route")
+                .symbol;
+            writeln!(output, "declare i{width} @{symbol}()\n").unwrap();
+            writeln!(output, "define i{width} @{function_name}() {{").unwrap();
+            writeln!(output, "  %result = call i{width} @{symbol}()").unwrap();
+        }
+        BackendLoweringMechanism::InlinePtx => {
+            writeln!(output, "define i{width} @{function_name}() {{").unwrap();
+            let sideeffect = if record.special_register.as_ref().is_some_and(|special| {
+                special.observation == SpecialRegisterObservation::VolatileObservation
+            }) {
+                " sideeffect"
+            } else {
+                ""
+            };
+            writeln!(
+                output,
+                "  %result = call i{width} asm{sideeffect} {:?}, {:?}()",
+                special_register_inline_template(record),
+                special_register_output_constraint(record)
+            )
+            .unwrap();
+        }
+    }
+    writeln!(output, "  ret i{width} %result\n}}").unwrap();
+    output
+}
+
+fn render_tma_probe(catalog: &CatalogFile, record: &CatalogIntrinsic, hash: &str) -> String {
+    let tma = record.tma.as_ref().expect("TMA contract");
+    let operation = tma.operation;
+    let llvm = llvm(record);
+    let symbol = llvm.resolved_symbol.as_ref().unwrap_or(&llvm.symbol);
+    let mut output = llvm_header(catalog, hash);
+    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
+    if let Some(dimensions) = tma.dimensions() {
+        let is_g2s = matches!(
+            operation,
+            TmaOperation::G2sTile1d
+                | TmaOperation::G2sTile2d
+                | TmaOperation::G2sTile2dMulticast
+                | TmaOperation::G2sTile2dMulticastCg2
+                | TmaOperation::G2sTile3d
+                | TmaOperation::G2sTile4d
+                | TmaOperation::G2sTile5d
+        );
+        let coordinates = std::iter::repeat_n("i32", dimensions)
+            .collect::<Vec<_>>()
+            .join(", ");
+        let coordinate_parameters = (0..dimensions)
+            .map(|index| format!("i32 %coord{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let coordinate_arguments = (0..dimensions)
+            .map(|index| format!("i32 %coord{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        if is_g2s {
+            let multicast = matches!(
+                operation,
+                TmaOperation::G2sTile2dMulticast | TmaOperation::G2sTile2dMulticastCg2
+            );
+            let declaration_coordinates = if coordinates.is_empty() {
+                String::new()
+            } else {
+                format!(", {coordinates}")
+            };
+            writeln!(
+                output,
+                "declare void @{symbol}(ptr addrspace(7), ptr addrspace(3), ptr{declaration_coordinates}, i16, i64, i1, i1, i32) #0\n"
+            )
+            .unwrap();
+            let parameters = if coordinate_parameters.is_empty() {
+                String::new()
+            } else {
+                format!(", {coordinate_parameters}")
+            };
+            let mask_parameter = if multicast { ", i16 %cta_mask" } else { "" };
+            writeln!(
+                output,
+                "define void @probe_{}(ptr %dst_generic, ptr %barrier_generic, ptr %tensor_map{parameters}{mask_parameter}) #0 {{",
+                record.id
+            )
+            .unwrap();
+            output.push_str(
+                "  %dst = addrspacecast ptr %dst_generic to ptr addrspace(7)\n  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
+            );
+            let arguments = if coordinate_arguments.is_empty() {
+                String::new()
+            } else {
+                format!(", {coordinate_arguments}")
+            };
+            let mask = if multicast { "%cta_mask" } else { "0" };
+            let group = if operation == TmaOperation::G2sTile2dMulticastCg2 {
+                2
+            } else {
+                0
+            };
+            writeln!(
+                output,
+                "  call void @{symbol}(ptr addrspace(7) %dst, ptr addrspace(3) %barrier, ptr %tensor_map{arguments}, i16 {mask}, i64 0, i1 {multicast}, i1 false, i32 {group}) #0"
+            )
+            .unwrap();
+        } else {
+            let declaration_coordinates = if coordinates.is_empty() {
+                String::new()
+            } else {
+                format!(", {coordinates}")
+            };
+            writeln!(
+                output,
+                "declare void @{symbol}(ptr addrspace(3), ptr{declaration_coordinates}, i64, i1) #0\n"
+            )
+            .unwrap();
+            let parameters = if coordinate_parameters.is_empty() {
+                String::new()
+            } else {
+                format!(", {coordinate_parameters}")
+            };
+            writeln!(
+                output,
+                "define void @probe_{}(ptr %src_generic, ptr %tensor_map{parameters}) #0 {{",
+                record.id
+            )
+            .unwrap();
+            output.push_str("  %src = addrspacecast ptr %src_generic to ptr addrspace(3)\n");
+            let arguments = if coordinate_arguments.is_empty() {
+                String::new()
+            } else {
+                format!(", {coordinate_arguments}")
+            };
+            writeln!(
+                output,
+                "  call void @{symbol}(ptr addrspace(3) %src, ptr %tensor_map{arguments}, i64 0, i1 false) #0"
+            )
+            .unwrap();
+        }
+        output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
+    } else if operation == TmaOperation::PrefetchTensorMap {
+        writeln!(output, "declare void @{symbol}(ptr)\n").unwrap();
+        writeln!(
+            output,
+            "define void @probe_{}(ptr %tensor_map) {{",
+            record.id
+        )
+        .unwrap();
+        writeln!(output, "  call void @{symbol}(ptr %tensor_map)").unwrap();
+        output.push_str("  ret void\n}\n");
+    } else if let Some(coordinate_count) = operation.prefetch_coordinate_count() {
+        let coordinates = std::iter::repeat_n("i32", coordinate_count)
+            .collect::<Vec<_>>()
+            .join(", ");
+        let declaration_coordinates = if coordinates.is_empty() {
+            String::new()
+        } else {
+            format!(", {coordinates}")
+        };
+        let coordinate_parameters = (0..coordinate_count)
+            .map(|index| format!("i32 %coord{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let parameters = if coordinate_parameters.is_empty() {
+            String::new()
+        } else {
+            format!(", {coordinate_parameters}")
+        };
+        let cache_hint_parameter = if operation.uses_prefetch_cache_hint() {
+            ", i64 %cache_hint"
+        } else {
+            ""
+        };
+        let coordinate_arguments = (0..coordinate_count)
+            .map(|index| format!("i32 %coord{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let arguments = if coordinate_arguments.is_empty() {
+            String::new()
+        } else {
+            format!(", {coordinate_arguments}")
+        };
+        writeln!(
+            output,
+            "declare void @{symbol}(ptr{declaration_coordinates}, i64, i1) #0\n"
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "define void @probe_{}(ptr %tensor_map{parameters}{cache_hint_parameter}) #0 {{",
+            record.id,
+        )
+        .unwrap();
+        let cache_hint = if operation.uses_prefetch_cache_hint() {
+            "%cache_hint"
+        } else {
+            "0"
+        };
+        let use_cache_hint = operation.uses_prefetch_cache_hint();
+        writeln!(
+            output,
+            "  call void @{symbol}(ptr %tensor_map{arguments}, i64 {cache_hint}, i1 {use_cache_hint}) #0"
+        )
+        .unwrap();
+        output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
+    } else if matches!(
+        operation,
+        TmaOperation::ReplaceBoxDim
+            | TmaOperation::ReplaceElementStride
+            | TmaOperation::ReplaceElementType
+            | TmaOperation::ReplaceFillMode
+            | TmaOperation::ReplaceGlobalAddress
+            | TmaOperation::ReplaceGlobalDim
+            | TmaOperation::ReplaceGlobalStride
+            | TmaOperation::ReplaceInterleaveLayout
+            | TmaOperation::ReplaceRank
+            | TmaOperation::ReplaceSwizzleAtomicity
+            | TmaOperation::ReplaceSwizzleMode
+    ) {
+        let (field, width, ordinal, value_ty, immediate, address) = match operation {
+            TmaOperation::ReplaceBoxDim => ("box_dim", "b32", true, "i32", false, false),
+            TmaOperation::ReplaceElementStride => {
+                ("element_stride", "b32", true, "i32", false, false)
+            }
+            TmaOperation::ReplaceElementType => ("elemtype", "b32", false, "i32", true, false),
+            TmaOperation::ReplaceFillMode => ("fill_mode", "b32", false, "i32", true, false),
+            TmaOperation::ReplaceGlobalAddress => {
+                ("global_address", "b64", false, "i64", false, true)
+            }
+            TmaOperation::ReplaceGlobalDim => ("global_dim", "b32", true, "i32", false, false),
+            TmaOperation::ReplaceGlobalStride => {
+                ("global_stride", "b64", true, "i64", false, false)
+            }
+            TmaOperation::ReplaceInterleaveLayout => {
+                ("interleave_layout", "b32", false, "i32", true, false)
+            }
+            TmaOperation::ReplaceRank => ("rank", "b32", false, "i32", false, false),
+            TmaOperation::ReplaceSwizzleAtomicity => {
+                ("swizzle_atomicity", "b32", false, "i32", true, false)
+            }
+            TmaOperation::ReplaceSwizzleMode => ("swizzle_mode", "b32", false, "i32", true, false),
+            _ => unreachable!("TMA tensor-map replace operation was matched"),
+        };
+        let value_parameter = if immediate {
+            String::new()
+        } else if address {
+            ", ptr %new_address".into()
+        } else {
+            format!(", {value_ty} %new_value")
+        };
+        writeln!(
+            output,
+            "define void @probe_{}(ptr %tensor_map{value_parameter}) {{",
+            record.id
+        )
+        .unwrap();
+        let mut arguments = vec!["ptr %tensor_map".to_owned()];
+        let mut constraints = vec!["l"];
+        if ordinal {
+            arguments.push("i32 0".into());
+            constraints.push("n");
+        }
+        if immediate {
+            arguments.push(format!("{value_ty} 0"));
+            constraints.push("n");
+        } else if address {
+            arguments.push("ptr %new_address".into());
+            constraints.push("l");
+        } else {
+            arguments.push(format!("{value_ty} %new_value"));
+            constraints.push(if value_ty == "i64" { "l" } else { "r" });
+        }
+        constraints.push("~{memory}");
+        let template = if ordinal {
+            format!("tensormap.replace.tile.{field}.global.b1024.{width} [$0], $1, $2;")
+        } else {
+            format!("tensormap.replace.tile.{field}.global.b1024.{width} [$0], $1;")
+        };
+        writeln!(
+            output,
+            "  call void asm sideeffect {template:?}, {:?}({})",
+            constraints.join(","),
+            arguments.join(", ")
+        )
+        .unwrap();
+        output.push_str("  ret void\n}\n");
+    } else if matches!(
+        operation,
+        TmaOperation::FenceProxyTensorMapAcquireCluster
+            | TmaOperation::FenceProxyTensorMapAcquireCta
+            | TmaOperation::FenceProxyTensorMapAcquireGpu
+            | TmaOperation::FenceProxyTensorMapAcquireSystem
+    ) {
+        writeln!(output, "declare void @{symbol}(ptr, i32)\n").unwrap();
+        writeln!(
+            output,
+            "define void @probe_{}(ptr %tensor_map) {{",
+            record.id
+        )
+        .unwrap();
+        writeln!(output, "  call void @{symbol}(ptr %tensor_map, i32 128)").unwrap();
+        output.push_str("  ret void\n}\n");
+    } else if operation == TmaOperation::CommitGroup
+        || matches!(
+            operation,
+            TmaOperation::FenceProxyTensorMapReleaseCluster
+                | TmaOperation::FenceProxyTensorMapReleaseCta
+                | TmaOperation::FenceProxyTensorMapReleaseGpu
+                | TmaOperation::FenceProxyTensorMapReleaseSystem
+        )
+    {
+        writeln!(output, "declare void @{symbol}()\n").unwrap();
+        writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
+        writeln!(output, "  call void @{symbol}()").unwrap();
+        output.push_str("  ret void\n}\n");
+    } else {
+        writeln!(output, "declare void @{symbol}(i32)\n").unwrap();
+        writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
+        writeln!(output, "  call void @{symbol}(i32 0)").unwrap();
+        output.push_str("  ret void\n}\n");
+    }
+    output
+}
+
+fn render_execution_control_probe(
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+    hash: &str,
+) -> String {
+    let operation = ExecutionControlOperation::from_catalog_id(&record.id)
+        .expect("closed execution-control operation");
+    let symbol = &llvm(record).symbol;
+    let mut output = llvm_header(catalog, hash);
+    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
+    match operation {
+        ExecutionControlOperation::BarrierCtaSync
+        | ExecutionControlOperation::BarrierCtaSyncAligned
+        | ExecutionControlOperation::BarrierCtaArrive
+        | ExecutionControlOperation::BarrierCtaArriveAligned => {
+            writeln!(output, "declare void @{symbol}(i32, i32)\n").unwrap();
+            for (suffix, parameters, barrier_id, thread_count) in [
+                (
+                    "rr",
+                    "i32 %barrier_id, i32 %thread_count",
+                    "%barrier_id",
+                    "%thread_count",
+                ),
+                ("ri", "i32 %barrier_id", "%barrier_id", "32"),
+                ("ir", "i32 %thread_count", "1", "%thread_count"),
+                ("ii", "", "1", "32"),
+            ] {
+                writeln!(
+                    output,
+                    "define void @probe_{}_{suffix}({parameters}) #0 {{",
+                    record.id
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "  call void @{symbol}(i32 {barrier_id}, i32 {thread_count})"
+                )
+                .unwrap();
+                output.push_str("  ret void\n}\n\n");
+            }
+            output.push_str("attributes #0 = { convergent }\n");
+        }
+        ExecutionControlOperation::GridDependencyLaunchDependents
+        | ExecutionControlOperation::GridDependencyWait => {
+            writeln!(output, "declare void @{symbol}()\n").unwrap();
+            writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
+            writeln!(output, "  call void @{symbol}()").unwrap();
+            output.push_str("  ret void\n}\n");
+        }
+        ExecutionControlOperation::SetMaxNRegInc | ExecutionControlOperation::SetMaxNRegDec => {
+            writeln!(output, "declare void @{symbol}(i32)\n").unwrap();
+            writeln!(output, "define void @probe_{}() #0 {{", record.id).unwrap();
+            writeln!(output, "  call void @{symbol}(i32 64)").unwrap();
+            output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
+        }
+    }
+    output
+}
+
+fn render_tcgen05_mma_probe(
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+    hash: &str,
+    mma: &Tcgen05Mma,
+) -> String {
+    let (kind, b_buffer, b_usage) = mma.fixed_selectors.map_or(
+        (Tcgen05MmaKind::F16, 0, Tcgen05MmaBUsage::Discard),
+        |fixed| (fixed.kind, fixed.b_buffer, fixed.b_usage),
+    );
+    let (template, constraints) = if tcgen05_mma_is_ws(mma.form) {
+        tcgen05_mma_inline_asm(mma.form, kind, 1, None, Some(b_buffer), Some(b_usage))
+    } else {
+        tcgen05_mma_inline_asm(mma.form, kind, 1, Some("discard"), None, None)
+    };
+    let parameters = tcgen05_mma_runtime_parameters(mma);
+    let llvm_parameter = |(name, ty): &(&str, &str)| {
+        let ty = match *ty {
+            "u32" => "i32",
+            "u64" => "i64",
+            "bool" => "i1",
+            _ => unreachable!("closed tcgen05 MMA probe type"),
+        };
+        format!("{ty} %{name}")
+    };
+    let signature = parameters
+        .iter()
+        .map(llvm_parameter)
+        .collect::<Vec<_>>()
+        .join(", ");
+    let argument_indices: Vec<usize> =
+        if mma.alias.is_some() && mma.form == Tcgen05MmaForm::WsTensor {
+            vec![0, 1, 3, 4, 5]
+        } else {
+            (0..parameters.len()).collect()
+        };
+    let arguments = argument_indices
+        .iter()
+        .map(|&index| llvm_parameter(&parameters[index]))
+        .collect::<Vec<_>>()
+        .join(", ");
+
+    let mut output = llvm_header(catalog, hash);
+    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
+    writeln!(
+        output,
+        "; LLVM source: {}; route: inline PTX; source contract: {:?}",
+        llvm(record).symbol,
+        record.tcgen05.as_ref().unwrap().source_contract
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "define void @probe_{}({signature}) #0 {{",
+        record.id
+    )
+    .unwrap();
+    writeln!(
+        output,
+        "  call void asm sideeffect {template:?}, {constraints:?}({arguments}) #0"
+    )
+    .unwrap();
+    output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
+    output
+}
+
+fn render_tcgen05_probe(catalog: &CatalogFile, record: &CatalogIntrinsic, hash: &str) -> String {
+    let tcgen05 = record.tcgen05.as_ref().expect("tcgen05 contract");
+    if let Some(mma) = &tcgen05.mma {
+        return render_tcgen05_mma_probe(catalog, record, hash, mma);
+    }
+    let operation = tcgen05.operation;
+    let mut output = llvm_header(catalog, hash);
+    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
+    writeln!(
+        output,
+        "; LLVM source: {}; route: inline PTX; source contract: {:?}",
+        llvm(record).symbol,
+        record.tcgen05.as_ref().unwrap().source_contract
+    )
+    .unwrap();
+    let (parameters, result_ty, template, constraints, arguments) = match operation {
+        Tcgen05Operation::Alloc | Tcgen05Operation::AllocCg2 => {
+            let group = if operation == Tcgen05Operation::AllocCg2 {
+                "2"
+            } else {
+                "1"
+            };
+            (
+                "ptr %dst, i32 %ncols".into(),
+                "void".into(),
+                format!(
+                    "{{ .reg .u64 %shared64; .reg .u32 %shared32; cvta.to.shared.u64 %shared64, $0; cvt.u32.u64 %shared32, %shared64; tcgen05.alloc.cta_group::{group}.sync.aligned.shared::cta.b32 [%shared32], $1; }}"
+                ),
+                "l,r,~{memory}".into(),
+                "ptr %dst, i32 %ncols".into(),
+            )
+        }
+        Tcgen05Operation::Dealloc | Tcgen05Operation::DeallocCg2 => {
+            let group = if operation == Tcgen05Operation::DeallocCg2 {
+                "2"
+            } else {
+                "1"
+            };
+            (
+                "i32 %tmem, i32 %ncols".into(),
+                "void".into(),
+                format!("tcgen05.dealloc.cta_group::{group}.sync.aligned.b32 $0, $1;"),
+                "r,r,~{memory}".into(),
+                "i32 %tmem, i32 %ncols".into(),
+            )
+        }
+        Tcgen05Operation::RelinquishAllocPermit | Tcgen05Operation::RelinquishAllocPermitCg2 => {
+            let group = if operation == Tcgen05Operation::RelinquishAllocPermitCg2 {
+                "2"
+            } else {
+                "1"
+            };
+            (
+                String::new(),
+                "void".into(),
+                format!("tcgen05.relinquish_alloc_permit.cta_group::{group}.sync.aligned;"),
+                "~{memory}".into(),
+                String::new(),
+            )
+        }
+        Tcgen05Operation::FenceBeforeThreadSync | Tcgen05Operation::FenceAfterThreadSync => {
+            let modifier = if operation == Tcgen05Operation::FenceBeforeThreadSync {
+                "before_thread_sync"
+            } else {
+                "after_thread_sync"
+            };
+            (
+                String::new(),
+                "void".into(),
+                format!("tcgen05.fence::{modifier};"),
+                "~{memory}".into(),
+                String::new(),
+            )
+        }
+        Tcgen05Operation::Commit
+        | Tcgen05Operation::CommitSharedCluster
+        | Tcgen05Operation::CommitCg2
+        | Tcgen05Operation::CommitSharedClusterCg2 => {
+            let group = if matches!(
+                operation,
+                Tcgen05Operation::CommitCg2 | Tcgen05Operation::CommitSharedClusterCg2
+            ) {
+                "2"
+            } else {
+                "1"
+            };
+            let shared = matches!(
+                operation,
+                Tcgen05Operation::CommitSharedCluster | Tcgen05Operation::CommitSharedClusterCg2
+            );
+            (
+                "i32 %mbar".into(),
+                "void".into(),
+                format!(
+                    "tcgen05.commit.cta_group::{group}.mbarrier::arrive::one{}.b64 [$0];",
+                    if shared { ".shared::cluster" } else { "" }
+                ),
+                "r,~{memory}".into(),
+                "i32 %mbar".into(),
+            )
+        }
+        Tcgen05Operation::MmaWsF16 | Tcgen05Operation::MmaWsBf16 | Tcgen05Operation::MmaWsTf32 => {
+            let kind = if operation == Tcgen05Operation::MmaWsTf32 {
+                "tf32"
+            } else {
+                "f16"
+            };
+            (
+                "i32 %d, i32 %a, i64 %legacy_a_desc, i64 %b, i32 %idesc, i1 %enable".into(),
+                "void".into(),
+                format!(
+                    "{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::{kind} [$0], [$1], $3, $4, %enable_pred; }}"
+                ),
+                "r,r,l,l,r,r,~{memory}".into(),
+                "i32 %d, i32 %a, i64 %legacy_a_desc, i64 %b, i32 %idesc, i1 %enable".into(),
+            )
+        }
+        Tcgen05Operation::MmaF16 | Tcgen05Operation::MmaF16Cg2 => {
+            let group = if operation == Tcgen05Operation::MmaF16Cg2 {
+                "2"
+            } else {
+                "1"
+            };
+            let zeros = if operation == Tcgen05Operation::MmaF16Cg2 {
+                "%z, %z, %z, %z, %z, %z, %z, %z"
+            } else {
+                "%z, %z, %z, %z"
+            };
+            (
+                "i32 %d, i64 %a, i64 %b, i32 %idesc, i1 %enable".into(),
+                "void".into(),
+                format!(
+                    "{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; .reg .u32 %z; mov.u32 %z, 0; tcgen05.mma.cta_group::{group}.kind::f16 [$0], $1, $2, $3, {{{zeros}}}, %enable_pred; }}"
+                ),
+                "r,l,l,r,r,~{memory}".into(),
+                "i32 %d, i64 %a, i64 %b, i32 %idesc, i1 %enable".into(),
+            )
+        }
+        Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2 => (
+            "i32 %tmem, i64 %desc".into(),
+            "void".into(),
+            format!(
+                "{}.{} [$0], $1;",
+                record.expected_ptx.mnemonic,
+                record.expected_ptx.modifiers.join(".")
+            ),
+            "r,l,~{memory}".into(),
+            "i32 %tmem, i64 %desc".into(),
+        ),
+        Tcgen05Operation::Ld16x256bX8Pure | Tcgen05Operation::Ld16x256bPure => {
+            let count = if operation == Tcgen05Operation::Ld16x256bX8Pure {
+                32
+            } else {
+                4
+            };
+            let registers = (0..count)
+                .map(|index| format!("${index}"))
+                .collect::<Vec<_>>()
+                .join(",");
+            let constraints = std::iter::repeat_n("=f", count)
+                .chain(std::iter::once("r"))
+                .collect::<Vec<_>>()
+                .join(",");
+            let fields = std::iter::repeat_n("float", count)
+                .collect::<Vec<_>>()
+                .join(", ");
+            (
+                "i32 %tmem".into(),
+                format!("{{ {fields} }}"),
+                format!(
+                    "tcgen05.ld.sync.aligned.16x256b.{}.b32 {{{registers}}}, [${count}];",
+                    if count == 32 { "x8" } else { "x1" }
+                ),
+                constraints,
+                "i32 %tmem".into(),
+            )
+        }
+        Tcgen05Operation::St => {
+            let count = tcgen05_st_register_count(record);
+            let has_half_split_offset = record
+                .tcgen05
+                .as_ref()
+                .and_then(|tcgen05| tcgen05.st)
+                .is_some_and(|st| st.shape == Tcgen05LdShape::M16x32bx2);
+            let parameters = std::iter::once("i32 %tmem".into())
+                .chain((0..count).map(|index| format!("i32 %d{index}")))
+                .collect::<Vec<_>>()
+                .join(", ");
+            let arguments = std::iter::once("i32 %tmem".into())
+                .chain(has_half_split_offset.then(|| "i64 16".into()))
+                .chain((0..count).map(|index| format!("i32 %d{index}")))
+                .collect::<Vec<_>>()
+                .join(", ");
+            let (template, constraints, _) = tcgen05_inline_asm(record);
+            (parameters, "void".into(), template, constraints, arguments)
+        }
+        Tcgen05Operation::Ld => {
+            let count = tcgen05_ld_register_count(record);
+            let has_half_split_offset = record
+                .tcgen05
+                .as_ref()
+                .and_then(|tcgen05| tcgen05.ld)
+                .is_some_and(|ld| ld.shape == Tcgen05LdShape::M16x32bx2);
+            let fields = std::iter::repeat_n("i32", count)
+                .collect::<Vec<_>>()
+                .join(", ");
+            let (template, constraints, _) = tcgen05_inline_asm(record);
+            (
+                "i32 %tmem".into(),
+                if count == 1 {
+                    "i32".into()
+                } else {
+                    format!("{{ {fields} }}")
+                },
+                template,
+                constraints,
+                if has_half_split_offset {
+                    "i32 %tmem, i64 16".into()
+                } else {
+                    "i32 %tmem".into()
+                },
+            )
+        }
+        Tcgen05Operation::LoadWait | Tcgen05Operation::StoreWait => {
+            let kind = if operation == Tcgen05Operation::LoadWait {
+                "ld"
+            } else {
+                "st"
+            };
+            (
+                String::new(),
+                "void".into(),
+                format!("tcgen05.wait::{kind}.sync.aligned;"),
+                "~{memory}".into(),
+                String::new(),
+            )
+        }
+        Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2 => {
+            let group = if operation == Tcgen05Operation::CommitMulticastCg2 {
+                2
+            } else {
+                1
+            };
+            (
+                "i32 %mbar, i16 %mask".into(),
+                "void".into(),
+                format!(
+                    "tcgen05.commit.cta_group::{group}.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;"
+                ),
+                "r,h,~{memory}".into(),
+                "i32 %mbar, i16 %mask".into(),
+            )
+        }
+        Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2 => {
+            let group = if operation == Tcgen05Operation::ShiftDownCg2 {
+                2
+            } else {
+                1
+            };
+            (
+                "i32 %tmem".into(),
+                "void".into(),
+                format!("tcgen05.shift.cta_group::{group}.down [$0];"),
+                "r,~{memory}".into(),
+                "i32 %tmem".into(),
+            )
+        }
+        Tcgen05Operation::Mma => unreachable!("generic MMA probe handled above"),
+    };
+    let (lowering_template, lowering_constraints, lowering_results) = tcgen05_inline_asm(record);
+    assert_eq!(template, lowering_template);
+    assert_eq!(constraints, lowering_constraints);
+    assert_eq!(result_ty != "void", lowering_results.is_some());
+    writeln!(
+        output,
+        "define void @probe_{}({parameters}) #0 {{",
+        record.id
+    )
+    .unwrap();
+    if result_ty == "void" {
+        writeln!(
+            output,
+            "  call void asm sideeffect {template:?}, {constraints:?}({arguments}) #0"
+        )
+        .unwrap();
+    } else {
+        writeln!(
+            output,
+            "  %result = call {result_ty} asm sideeffect {template:?}, {constraints:?}({arguments}) #0"
+        )
+        .unwrap();
+    }
+    output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
+    output
+}
+
+pub(super) fn render_elect_probe(
+    catalog: &CatalogFile,
+    record: &CatalogIntrinsic,
+    hash: &str,
+    backend: IntrinsicBackend,
+) -> String {
+    let mut output = llvm_header(catalog, hash);
+    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
+    let mechanism = record
+        .backend_lowerings
+        .iter()
+        .find(|route| route.backend == backend)
+        .expect("elect backend route")
+        .mechanism;
+    match mechanism {
+        BackendLoweringMechanism::TypedNvvm => {
+            writeln!(
+                output,
+                "declare {{ i32, i1 }} @{}(i32) #0\n",
+                llvm(record).symbol
+            )
+            .unwrap();
+            for (suffix, parameters, mask) in
+                [("register", "i32 %mask", "%mask"), ("immediate", "", "-1")]
+            {
+                writeln!(
+                    output,
+                    "define {{ i32, i1 }} @probe_{}_{}_{suffix}({parameters}) #0 {{",
+                    record.id,
+                    backend_label(backend)
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "  %result = call {{ i32, i1 }} @{}(i32 {mask}) #0",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                output.push_str("  ret { i32, i1 } %result\n}\n");
+            }
+        }
+        BackendLoweringMechanism::InlinePtx => {
+            for (suffix, parameters, mask) in [
+                ("register", "i32 %mask", "%mask"),
+                ("constant_mask", "", "-1"),
+            ] {
+                writeln!(
+                    output,
+                    "define {{ i32, i1 }} @probe_{}_{}_{suffix}({parameters}) #0 {{",
+                    record.id,
+                    backend_label(backend)
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "  %raw = call {{ i32, i32 }} asm sideeffect \"{{ .reg .pred p; elect.sync $0|p, $2; selp.b32 $1, 1, 0, p; }}\", \"=r,=r,r\"(i32 {mask}) #0"
+                )
+                .unwrap();
+                output.push_str(
+                    "  %leader = extractvalue { i32, i32 } %raw, 0\n\
+                     \x20 %predicate.i32 = extractvalue { i32, i32 } %raw, 1\n\
+                     \x20 %predicate = trunc i32 %predicate.i32 to i1\n\
+                     \x20 %result.0 = insertvalue { i32, i1 } poison, i32 %leader, 0\n\
+                     \x20 %result.1 = insertvalue { i32, i1 } %result.0, i1 %predicate, 1\n\
+                     \x20 ret { i32, i1 } %result.1\n}\n",
+                );
+            }
+        }
+    }
+    output.push_str("\nattributes #0 = { convergent }\n");
+    output
+}
+
+pub(crate) fn render_probe(catalog: &CatalogFile, record: &CatalogIntrinsic, hash: &str) -> String {
+    if record.special_register.is_some() {
+        return render_special_register_probe(catalog, record, hash, IntrinsicBackend::LlvmNvptx);
+    }
+    if record.tma.is_some() {
+        return render_tma_probe(catalog, record, hash);
+    }
+    if ExecutionControlOperation::from_catalog_id(&record.id).is_some() {
+        return render_execution_control_probe(catalog, record, hash);
+    }
+    if record.tcgen05.is_some() {
+        return render_tcgen05_probe(catalog, record, hash);
+    }
+    if record.family == "elect" {
+        return render_elect_probe(catalog, record, hash, IntrinsicBackend::LlvmNvptx);
+    }
+    let mut output = llvm_header(catalog, hash);
+    output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n");
+    if let Some(cluster) = &record.cluster_memory {
+        let (template, constraints) =
+            crate::resolve::cluster_memory_inline_recipe(cluster.operation);
+        match cluster.operation {
+            ClusterMemoryOperation::MapSharedRank => {
+                writeln!(
+                    output,
+                    "define ptr addrspace(7) @probe_{}(ptr %source_generic, i32 %rank) #0 {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %source = addrspacecast ptr %source_generic to ptr addrspace(3)\n",
+                );
+                writeln!(
+                    output,
+                    "  %mapped_integer = call i64 asm sideeffect {template:?}, {constraints:?}(ptr addrspace(3) %source, i32 %rank) #0"
+                )
+                .unwrap();
+                output.push_str(
+                    "  %mapped = inttoptr i64 %mapped_integer to ptr addrspace(7)\n  ret ptr addrspace(7) %mapped\n}\n\nattributes #0 = { convergent }\n",
+                );
+            }
+            ClusterMemoryOperation::ReadU32 => {
+                writeln!(
+                    output,
+                    "define i32 @probe_{}(ptr %source_generic, i32 %rank) #0 {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %source = addrspacecast ptr %source_generic to ptr addrspace(3)\n",
+                );
+                writeln!(
+                    output,
+                    "  %value = call i32 asm sideeffect {template:?}, {constraints:?}(ptr addrspace(3) %source, i32 %rank) #0"
+                )
+                .unwrap();
+                output.push_str("  ret i32 %value\n}\n\nattributes #0 = { convergent }\n");
+            }
+        }
+    } else if let Some(clc) = &record.clc {
+        match clc.adapter {
+            ClcAdapter::GenericPointersToShared => {
+                writeln!(
+                    output,
+                    "declare void @{}(ptr addrspace(3), ptr addrspace(3))\n",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "define void @probe_{}(ptr %response_generic, ptr %mbarrier_generic) {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %response = addrspacecast ptr %response_generic to ptr addrspace(3)\n\
+                     \x20 %mbarrier = addrspacecast ptr %mbarrier_generic to ptr addrspace(3)\n",
+                );
+                writeln!(
+                    output,
+                    "  call void @{}(ptr addrspace(3) %response, ptr addrspace(3) %mbarrier)",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                output.push_str("  ret void\n}\n");
+            }
+            ClcAdapter::PairU64ToI128BoolToU32 | ClcAdapter::PairU64ToI128U32 => {
+                let llvm_result = if clc.adapter == ClcAdapter::PairU64ToI128BoolToU32 {
+                    "i1"
+                } else {
+                    "i32"
+                };
+                writeln!(
+                    output,
+                    "declare {llvm_result} @{}(i128)\n",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "define i32 @probe_{}(i64 %response_low, i64 %response_high) {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %response_low_i128 = zext i64 %response_low to i128\n\
+                     \x20 %response_high_i128 = zext i64 %response_high to i128\n\
+                     \x20 %response_high_shifted = shl i128 %response_high_i128, 64\n\
+                     \x20 %response = or i128 %response_low_i128, %response_high_shifted\n",
+                );
+                writeln!(
+                    output,
+                    "  %raw_result = call {llvm_result} @{}(i128 %response)",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                if clc.adapter == ClcAdapter::PairU64ToI128BoolToU32 {
+                    output.push_str(
+                        "  %result = zext i1 %raw_result to i32\n\
+                         \x20 ret i32 %result\n}\n",
+                    );
+                } else {
+                    output.push_str("  ret i32 %raw_result\n}\n");
+                }
+            }
+        }
+    } else if let Some(bridge) = &record.cp_async_mbarrier {
+        let shared = bridge.state_space == CpAsyncMbarrierStateSpace::Shared;
+        let pointer_type = if shared { "ptr addrspace(3)" } else { "ptr" };
+        writeln!(
+            output,
+            "declare void @{}({pointer_type})\n",
+            llvm(record).symbol
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "define void @probe_{}(ptr %barrier_generic) {{",
+            record.id
+        )
+        .unwrap();
+        if shared {
+            output
+                .push_str("  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n");
+            writeln!(
+                output,
+                "  call void @{}(ptr addrspace(3) %barrier)",
+                llvm(record).symbol
+            )
+            .unwrap();
+        } else {
+            writeln!(
+                output,
+                "  call void @{}(ptr %barrier_generic)",
+                llvm(record).symbol
+            )
+            .unwrap();
+        }
+        output.push_str("  ret void\n}\n");
+    } else if let Some(mbarrier) = &record.mbarrier_basic {
+        match mbarrier.operation {
+            MbarrierBasicOperation::Init => {
+                writeln!(
+                    output,
+                    "declare void @{}(ptr addrspace(3), i32)\n",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "define void @probe_{}(ptr %barrier_generic, i32 %expected_count) {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
+                );
+                writeln!(
+                    output,
+                    "  call void @{}(ptr addrspace(3) %barrier, i32 %expected_count)",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                output.push_str("  ret void\n}\n");
+            }
+            MbarrierBasicOperation::Arrive => {
+                writeln!(
+                    output,
+                    "declare i64 @{}(ptr addrspace(3))\n",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "define i64 @probe_{}(ptr %barrier_generic) {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
+                );
+                writeln!(
+                    output,
+                    "  %token = call i64 @{}(ptr addrspace(3) %barrier)",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                output.push_str("  ret i64 %token\n}\n");
+            }
+            MbarrierBasicOperation::TestWait => {
+                writeln!(
+                    output,
+                    "define i1 @probe_{}(ptr %barrier_generic, i64 %token) #0 {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n\
+                     \x20 %result_i32 = call i32 asm sideeffect \"{ .reg .pred %p0; mbarrier.test_wait.shared.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }\", \"=r,l,l,~{memory}\"(ptr addrspace(3) %barrier, i64 %token) #0\n\
+                     \x20 %result = trunc i32 %result_i32 to i1\n\
+                     \x20 ret i1 %result\n\
+                     }\n\n\
+                     attributes #0 = { convergent }\n",
+                );
+            }
+            MbarrierBasicOperation::Inval => {
+                writeln!(
+                    output,
+                    "declare void @{}(ptr addrspace(3))\n",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "define void @probe_{}(ptr %barrier_generic) {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
+                );
+                writeln!(
+                    output,
+                    "  call void @{}(ptr addrspace(3) %barrier)",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                output.push_str("  ret void\n}\n");
+            }
+        }
+    } else if record.movmatrix.is_some() {
+        writeln!(output, "define i32 @probe_{}(i32 %value) #0 {{", record.id).unwrap();
+        writeln!(
+            output,
+            "  %result = call i32 asm {:?}, \"=r,r\"(i32 %value) #0",
+            movmatrix_template(record),
+        )
+        .unwrap();
+        output.push_str("  ret i32 %result\n}\n\nattributes #0 = { convergent }\n");
+    } else if let Some(mbarrier) = &record.mbarrier_extended {
+        let (template, constraints) =
+            crate::resolve::mbarrier_extended_inline_recipe(mbarrier.operation);
+        match mbarrier.adapter {
+            MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount => {
+                writeln!(
+                    output,
+                    "define i64 @probe_{}(ptr %barrier_generic, i32 %bytes) #0 {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
+                );
+                writeln!(
+                    output,
+                    "  %token = call i64 asm sideeffect {template:?}, {constraints:?}(ptr addrspace(3) %barrier, i32 %bytes) #0"
+                )
+                .unwrap();
+                output.push_str("  ret i64 %token\n}\n\nattributes #0 = { convergent }\n");
+            }
+            MbarrierExtendedAdapter::PointerTokenToPredicate => {
+                writeln!(
+                    output,
+                    "define i1 @probe_{}(ptr %barrier_generic, i64 %token) #0 {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
+                );
+                writeln!(
+                    output,
+                    "  %result_i32 = call i32 asm sideeffect {template:?}, {constraints:?}(ptr addrspace(3) %barrier, i64 %token) #0"
+                )
+                .unwrap();
+                output.push_str(
+                    "  %result = trunc i32 %result_i32 to i1\n  ret i1 %result\n}\n\nattributes #0 = { convergent }\n",
+                );
+            }
+            MbarrierExtendedAdapter::PointerParityToPredicate => {
+                writeln!(
+                    output,
+                    "define i1 @probe_{}(ptr %barrier_generic, i32 %parity) #0 {{",
+                    record.id
+                )
+                .unwrap();
+                output.push_str(
+                    "  %barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)\n",
+                );
+                writeln!(
+                    output,
+                    "  %result_i32 = call i32 asm sideeffect {template:?}, {constraints:?}(ptr addrspace(3) %barrier, i32 %parity) #0"
+                )
+                .unwrap();
+                output.push_str(
+                    "  %result = trunc i32 %result_i32 to i1\n  ret i1 %result\n}\n\nattributes #0 = { convergent }\n",
+                );
+            }
+            MbarrierExtendedAdapter::RawClusterAddressToVoid => {
+                writeln!(
+                    output,
+                    "define void @probe_{}(i64 %address) #0 {{",
+                    record.id
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "  call void asm sideeffect {template:?}, {constraints:?}(i64 %address) #0"
+                )
+                .unwrap();
+                output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
+            }
+            MbarrierExtendedAdapter::ZeroOperandsToVoid => {
+                writeln!(output, "define void @probe_{}() #0 {{", record.id).unwrap();
+                writeln!(
+                    output,
+                    "  call void asm sideeffect {template:?}, {constraints:?}() #0"
+                )
+                .unwrap();
+                output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
+            }
+            MbarrierExtendedAdapter::NanosecondsToVoid => {
+                writeln!(output, "define void @probe_{}(i32 %ns) #0 {{", record.id).unwrap();
+                writeln!(
+                    output,
+                    "  call void asm sideeffect {template:?}, {constraints:?}(i32 %ns) #0"
+                )
+                .unwrap();
+                output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
+            }
+        }
+    } else if record.integer_minmax.is_some() {
+        let parameters = "i32 %arg0, i32 %arg1";
+        writeln!(output, "define i32 @probe_{}({parameters}) {{", record.id).unwrap();
+        writeln!(
+            output,
+            "  %result = call i32 asm \"{} $0, $1, $2;\", \"=r,r,r\"(i32 %arg0, i32 %arg1)",
+            integer_minmax_ptx_mnemonic(record)
+        )
+        .unwrap();
+        output.push_str("  ret i32 %result\n}\n");
+    } else if record.packed_alu.is_some() {
+        let arity = record.rust.arguments.len();
+        let width = packed_alu_width(record);
+        let llvm_type = format!("i{width}");
+        let register_constraint = packed_alu_register_constraint(record);
+        let parameters = (0..arity)
+            .map(|index| format!("{llvm_type} %arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let arguments = (0..arity)
+            .map(|index| format!("{llvm_type} %arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let operands = (0..=arity)
+            .map(|index| format!("${index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let constraints = std::iter::once(format!("={register_constraint}"))
+            .chain(std::iter::repeat_n(register_constraint.to_owned(), arity))
+            .collect::<Vec<_>>()
+            .join(",");
+        writeln!(
+            output,
+            "define {llvm_type} @probe_{}({parameters}) {{",
+            record.id
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "  %result = call {llvm_type} asm \"{} {operands};\", \"{constraints}\"({arguments})",
+            packed_alu_ptx_mnemonic(record)
+        )
+        .unwrap();
+        writeln!(output, "  ret {llvm_type} %result\n}}").unwrap();
+    } else if record.packed_conversion.is_some() {
+        let result_ty = packed_conversion_dialect_type(record);
+        if packed_conversion_typed_llvm_name(record).is_some() {
+            let llvm = llvm(record);
+            let symbol = llvm.resolved_symbol.as_deref().unwrap_or(&llvm.symbol);
+            writeln!(output, "declare {result_ty} @{symbol}(float, float)\n").unwrap();
+            writeln!(
+                output,
+                "define {result_ty} @probe_{}(float %low, float %high) {{",
+                record.id,
+            )
+            .unwrap();
+            writeln!(
+                output,
+                "  %result = call {result_ty} @{symbol}(float %high, float %low)"
+            )
+            .unwrap();
+        } else if packed_conversion_source(record) == PackedConversionSourceFormat::F32x2 {
+            writeln!(
+                output,
+                "define {result_ty} @probe_{}(float %low, float %high) {{",
+                record.id,
+            )
+            .unwrap();
+            writeln!(
+                output,
+                "  %result = call {result_ty} asm \"{} $0, $2, $1;\", \"{}\"(float %low, float %high)",
+                packed_conversion_ptx_mnemonic(record),
+                packed_conversion_constraint(record),
+            )
+            .unwrap();
+        } else {
+            // A packed source arrives in one integer register, so the probe
+            // takes a single operand and needs no reordering.
+            let source_ty = format!("i{}", packed_conversion_source_width(record));
+            writeln!(
+                output,
+                "define {result_ty} @probe_{}({source_ty} %packed) {{",
+                record.id,
+            )
+            .unwrap();
+            writeln!(
+                output,
+                "  %result = call {result_ty} asm \"{} $0, $1;\", \"{}\"({source_ty} %packed)",
+                packed_conversion_ptx_mnemonic(record),
+                packed_conversion_constraint(record),
+            )
+            .unwrap();
+        }
+        writeln!(output, "  ret {result_ty} %result\n}}").unwrap();
+    } else if let Some(packed) = &record.packed_atomic {
+        let format = match packed.format {
+            PackedAtomicFormat::F16x2 => "f16x2",
+            PackedAtomicFormat::Bf16x2 => "bf16x2",
+        };
+        writeln!(
+            output,
+            "define i32 @probe_{}(ptr %address, i32 %addend) {{",
+            record.id
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "  %old = call i32 asm sideeffect \"atom.global.add.noftz.{format} $0, [$1], $2;\", \"=r,l,r,~{{memory}}\"(ptr %address, i32 %addend)"
+        )
+        .unwrap();
+        output.push_str("  ret i32 %old\n}\n");
+    } else if let Some(copy) = &record.cp_async_copy {
+        let dynamic_source_size = copy.source_size == CpAsyncSourceSize::Runtime;
+        let declaration_arguments = if dynamic_source_size {
+            "ptr addrspace(3), ptr addrspace(1), i32"
+        } else {
+            "ptr addrspace(3), ptr addrspace(1)"
+        };
+        writeln!(
+            output,
+            "declare void @{}({declaration_arguments})",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push('\n');
+        if dynamic_source_size {
+            writeln!(
+                output,
+                "define void @probe_{}_register(ptr %shared_generic, ptr %global_generic, i32 %source_size) {{",
+                record.id
+            )
+            .unwrap();
+            output.push_str(
+                "  %shared = addrspacecast ptr %shared_generic to ptr addrspace(3)\n  %global = addrspacecast ptr %global_generic to ptr addrspace(1)\n",
+            );
+            writeln!(
+                output,
+                "  call void @{}(ptr addrspace(3) %shared, ptr addrspace(1) %global, i32 %source_size)",
+                llvm(record).symbol
+            )
+            .unwrap();
+            output.push_str("  ret void\n}\n");
+            writeln!(
+                output,
+                "define void @probe_{}_immediate(ptr %shared_generic, ptr %global_generic) {{",
+                record.id
+            )
+            .unwrap();
+            output.push_str(
+                "  %shared = addrspacecast ptr %shared_generic to ptr addrspace(3)\n  %global = addrspacecast ptr %global_generic to ptr addrspace(1)\n",
+            );
+            writeln!(
+                output,
+                "  call void @{}(ptr addrspace(3) %shared, ptr addrspace(1) %global, i32 3)",
+                llvm(record).symbol
+            )
+            .unwrap();
+            output.push_str("  ret void\n}\n");
+        } else {
+            writeln!(
+                output,
+                "define void @probe_{}(ptr %shared_generic, ptr %global_generic) {{",
+                record.id
+            )
+            .unwrap();
+            output.push_str(
+                "  %shared = addrspacecast ptr %shared_generic to ptr addrspace(3)\n  %global = addrspacecast ptr %global_generic to ptr addrspace(1)\n",
+            );
+            writeln!(
+                output,
+                "  call void @{}(ptr addrspace(3) %shared, ptr addrspace(1) %global)",
+                llvm(record).symbol
+            )
+            .unwrap();
+            output.push_str("  ret void\n}\n");
+        }
+    } else if let Some(control) = &record.cp_async_control {
+        let has_immediate = control.operation == CpAsyncControlOperation::WaitGroup;
+        let declaration_arguments = if has_immediate { "i32" } else { "" };
+        writeln!(
+            output,
+            "declare void @{}({declaration_arguments})",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push('\n');
+        writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
+        if has_immediate {
+            writeln!(output, "  call void @{}(i32 3)", llvm(record).symbol).unwrap();
+        } else {
+            writeln!(output, "  call void @{}()", llvm(record).symbol).unwrap();
+        }
+        output.push_str("  ret void\n}\n");
+    } else if let Some(control) = &record.wgmma_control {
+        if control.mode == WgmmaControlMode::WaitGroup {
+            writeln!(
+                output,
+                "declare void @{}(i64 immarg) #0\n",
+                llvm(record).symbol
+            )
+            .unwrap();
+        } else {
+            writeln!(output, "declare void @{}() #0\n", llvm(record).symbol).unwrap();
+        }
+        writeln!(output, "define void @probe_{}() #0 {{", record.id).unwrap();
+        if control.mode == WgmmaControlMode::WaitGroup {
+            writeln!(output, "  call void @{}(i64 0) #0", llvm(record).symbol,).unwrap();
+        } else {
+            writeln!(output, "  call void @{}() #0", llvm(record).symbol,).unwrap();
+        }
+        output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
+    } else if record.cluster_barrier.is_some() {
+        writeln!(output, "declare void @{}() #0", llvm(record).symbol).unwrap();
+        output.push('\n');
+        writeln!(output, "define void @probe_{}() #0 {{", record.id).unwrap();
+        writeln!(output, "  call void @{}() #0", llvm(record).symbol).unwrap();
+        output.push_str("  ret void\n}\n\nattributes #0 = { convergent }\n");
+    } else if record.family == "sync" {
+        let arguments = if record.id == "sync_threads" {
+            "i32"
+        } else {
+            debug_assert!(threadfence_ptx_level(record).is_some());
+            ""
+        };
+        writeln!(output, "declare void @{}({arguments})", llvm(record).symbol).unwrap();
+        output.push('\n');
+        writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
+        let call_arguments = if record.id == "sync_threads" {
+            "i32 0"
+        } else {
+            ""
+        };
+        writeln!(
+            output,
+            "  call void @{}({call_arguments})",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push_str("  ret void\n}\n");
+    } else if let Some(warp_barrier) = &record.warp_barrier {
+        debug_assert_eq!(warp_barrier.adapter, WarpBarrierAdapter::DirectMemberMask);
+        writeln!(output, "declare void @{}(i32)", llvm(record).symbol).unwrap();
+        output.push('\n');
+        writeln!(
+            output,
+            "define void @probe_{}(i32 %member_mask) {{",
+            record.id
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "  call void @{}(i32 %member_mask)",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push_str("  ret void\n}\n");
+        writeln!(output, "define void @probe_{}_immediate() {{", record.id).unwrap();
+        writeln!(output, "  call void @{}(i32 -1)", llvm(record).symbol).unwrap();
+        output.push_str("  ret void\n}\n");
+    } else if let Some(dot) = &record.dot_product {
+        match dot.adapter {
+            DotProductAdapter::DirectThreeOperands => {
+                writeln!(
+                    output,
+                    "declare i32 @{}(i32, i32, i32)",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                output.push('\n');
+                writeln!(
+                    output,
+                    "define i32 @probe_{}(i32 %a, i32 %b, i32 %c) {{",
+                    record.id
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "  %result = call i32 @{}(i32 %a, i32 %b, i32 %c)",
+                    llvm(record).symbol
+                )
+                .unwrap();
+            }
+            DotProductAdapter::InsertLowHalfFalse => {
+                writeln!(
+                    output,
+                    "declare i32 @{}(i32, i32, i1, i32)",
+                    llvm(record).symbol
+                )
+                .unwrap();
+                output.push('\n');
+                writeln!(
+                    output,
+                    "define i32 @probe_{}(i32 %a, i32 %b, i32 %c) {{",
+                    record.id
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "  %result = call i32 @{}(i32 %a, i32 %b, i1 false, i32 %c)",
+                    llvm(record).symbol
+                )
+                .unwrap();
+            }
+        }
+        output.push_str("  ret i32 %result\n}\n");
+    } else if let Some(vote) = &record.vote {
+        debug_assert_eq!(vote.adapter, VoteAdapter::DirectMaskPredicate);
+        let result_ty = match vote.mode {
+            VoteMode::All | VoteMode::Any | VoteMode::Uni => "i1",
+            VoteMode::Ballot => "i32",
+        };
+        writeln!(
+            output,
+            "declare {result_ty} @{}(i32, i1)",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push('\n');
+        writeln!(
+            output,
+            "define {result_ty} @probe_{}(i32 %member_mask, i1 %predicate) {{",
+            record.id
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "  %result = call {result_ty} @{}(i32 %member_mask, i1 %predicate)",
+            llvm(record).symbol
+        )
+        .unwrap();
+        writeln!(output, "  ret {result_ty} %result\n}}").unwrap();
+        writeln!(
+            output,
+            "define {result_ty} @probe_{}_immediate(i1 %predicate) {{",
+            record.id
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "  %result = call {result_ty} @{}(i32 -1, i1 %predicate)",
+            llvm(record).symbol
+        )
+        .unwrap();
+        writeln!(output, "  ret {result_ty} %result\n}}").unwrap();
+    } else if let Some(warp_match) = &record.warp_match {
+        let value_ty = format!("i{}", warp_match.value_width.bits());
+        let result_ty = match warp_match.mode {
+            WarpMatchMode::Any => "i32".to_owned(),
+            WarpMatchMode::All => "{ i32, i1 }".to_owned(),
+        };
+        writeln!(
+            output,
+            "declare {result_ty} @{}(i32, {value_ty})",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push('\n');
+        let forms = [
+            (
+                "rr",
+                "i32 %member_mask, ",
+                "i32 %member_mask",
+                format!("{value_ty} %value"),
+            ),
+            ("ri", "", "i32 -1", format!("{value_ty} %value")),
+            (
+                "ir",
+                "i32 %member_mask",
+                "i32 %member_mask",
+                format!("{value_ty} 7"),
+            ),
+            ("ii", "", "i32 -1", format!("{value_ty} 7")),
+        ];
+        for (suffix, first_parameter, mask, value) in forms {
+            let parameters = match suffix {
+                "rr" => format!("{first_parameter}{value_ty} %value"),
+                "ri" => format!("{value_ty} %value"),
+                "ir" => first_parameter.to_owned(),
+                "ii" => String::new(),
+                _ => unreachable!(),
+            };
+            writeln!(
+                output,
+                "define {result_ty} @probe_{}_{suffix}({parameters}) {{",
+                record.id
+            )
+            .unwrap();
+            writeln!(
+                output,
+                "  %result = call {result_ty} @{}({mask}, {value})",
+                llvm(record).symbol
+            )
+            .unwrap();
+            writeln!(output, "  ret {result_ty} %result\n}}").unwrap();
+        }
+    } else if let Some(warp_shuffle) = &record.warp_shuffle {
+        if warp_shuffle.value_kind == WarpShuffleValueKind::I64 {
+            debug_assert_eq!(
+                warp_shuffle.adapter,
+                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
+            );
+            let mode = match warp_shuffle.mode {
+                WarpShuffleMode::Idx => "idx",
+                WarpShuffleMode::Bfly => "bfly",
+                WarpShuffleMode::Down => "down",
+                WarpShuffleMode::Up => "up",
+            };
+            let asm = format!(
+                "{{ .reg .b32 lo; .reg .b32 hi; mov.b64 {{lo, hi}}, $1; shfl.sync.{mode}.b32 lo, lo, $2, {}, $3; shfl.sync.{mode}.b32 hi, hi, $2, {}, $3; mov.b64 $0, {{lo, hi}}; }}",
+                warp_shuffle.clamp, warp_shuffle.clamp
+            );
+            writeln!(
+                output,
+                "define i64 @probe_{}(i32 %member_mask, i64 %value, i32 %lane) #0 {{",
+                record.id
+            )
+            .unwrap();
+            writeln!(
+                output,
+                "  %result = call i64 asm sideeffect {asm:?}, \"=l,l,r,r\"(i64 %value, i32 %lane, i32 %member_mask) #0"
+            )
+            .unwrap();
+            output.push_str("  ret i64 %result\n}\n\nattributes #0 = { convergent }\n");
+        } else {
+            debug_assert_eq!(
+                warp_shuffle.adapter,
+                WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp
+            );
+            let value_ty = match warp_shuffle.value_kind {
+                WarpShuffleValueKind::I32 => "i32",
+                WarpShuffleValueKind::F32 => "float",
+                WarpShuffleValueKind::I64 => unreachable!(),
+            };
+            writeln!(
+                output,
+                "declare {value_ty} @{}(i32, {value_ty}, i32, i32)",
+                llvm(record).symbol
+            )
+            .unwrap();
+            output.push('\n');
+            let forms = [
+                (
+                    "rr",
+                    format!("i32 %member_mask, {value_ty} %value, i32 %lane"),
+                    "i32 %member_mask",
+                    "i32 %lane",
+                ),
+                (
+                    "ri",
+                    format!("{value_ty} %value, i32 %lane"),
+                    "i32 -1",
+                    "i32 %lane",
+                ),
+                (
+                    "ir",
+                    format!("i32 %member_mask, {value_ty} %value"),
+                    "i32 %member_mask",
+                    "i32 1",
+                ),
+                ("ii", format!("{value_ty} %value"), "i32 -1", "i32 1"),
+            ];
+            for (suffix, parameters, member_mask, lane) in forms {
+                writeln!(
+                    output,
+                    "define {value_ty} @probe_{}_{suffix}({parameters}) {{",
+                    record.id
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "  %result = call {value_ty} @{}({member_mask}, {value_ty} %value, {lane}, i32 {})",
+                    llvm(record).symbol,
+                    warp_shuffle.clamp,
+                )
+                .unwrap();
+                writeln!(output, "  ret {value_ty} %result\n}}").unwrap();
+            }
+        }
+    } else if let Some(redux) = &record.redux {
+        debug_assert_eq!(redux.adapter, ReduxAdapter::MaskValueToSourceMemberMask);
+        let value_type = match llvm(record).results[0].as_str() {
+            "i32" => "i32",
+            "f32" => "float",
+            other => panic!("unsupported redux value type {other}"),
+        };
+        writeln!(
+            output,
+            "declare {value_type} @{}({value_type}, i32)",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push('\n');
+        writeln!(
+            output,
+            "define {value_type} @probe_{}(i32 %member_mask, {value_type} %value) {{",
+            record.id
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "  %result = call {value_type} @{}({value_type} %value, i32 %member_mask)",
+            llvm(record).symbol
+        )
+        .unwrap();
+        writeln!(output, "  ret {value_type} %result\n}}").unwrap();
+    } else if let Some(sparse_mma) = &record.sparse_mma {
+        let accumulator = match sparse_mma.accumulator {
+            SparseMmaAccumulator::F16 => "i32",
+            SparseMmaAccumulator::F32 => "float",
+            SparseMmaAccumulator::S32 => "i32",
+        };
+        let (c_count, a_count, b_count, d_count) = sparse_mma_fragment_counts(record);
+        let result = format!(
+            "{{ {} }}",
+            std::iter::repeat_n(accumulator, d_count)
+                .collect::<Vec<_>>()
+                .join(", ")
+        );
+        let parameters = (0..c_count)
+            .map(|index| format!("{accumulator} %c{index}"))
+            .chain((0..a_count).map(|index| format!("i32 %a{index}")))
+            .chain((0..b_count).map(|index| format!("i32 %b{index}")))
+            .chain(std::iter::once("i32 %metadata".to_owned()))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let arguments = (0..c_count)
+            .map(|index| format!("{accumulator} %c{index}"))
+            .chain((0..a_count).map(|index| format!("i32 %a{index}")))
+            .chain((0..b_count).map(|index| format!("i32 %b{index}")))
+            .chain(std::iter::once("i32 %metadata".to_owned()))
+            .collect::<Vec<_>>()
+            .join(", ");
+        for selector in sparse_mma_selector_values(record) {
+            writeln!(
+                output,
+                "define {result} @probe_{}_selector_{selector}({parameters}) #0 {{",
+                record.id
+            )
+            .unwrap();
+            writeln!(
+                output,
+                "  %result = call {result} asm sideeffect {:?}, {:?}({arguments}, i32 {selector}) #0",
+                sparse_mma_template(record),
+                sparse_mma_constraints(record),
+            )
+            .unwrap();
+            writeln!(output, "  ret {result} %result\n}}").unwrap();
+        }
+        output.push_str("\nattributes #0 = { convergent }\n");
+    } else if let Some(mma) = &record.register_mma {
+        let (c_count, a_count, b_count, d_count) = register_mma_fragment_counts(record);
+        let (c_type, packed_type, result_type) = match mma.adapter {
+            RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32
+            | RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32 => ("i32", "i32", "i32"),
+            RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
+            | RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32
+            | RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => {
+                ("float", "i32", "float")
+            }
+            RegisterMmaAdapter::C2F64A1F64B1F64ToD2F64 => ("double", "double", "double"),
+            RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32
+            | RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32
+            | RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32 => ("i32", "i32", "i32"),
+        };
+        let mut parameter_values = (0..c_count)
+            .map(|index| format!("{c_type} %c{index}"))
+            .chain((0..a_count).map(|index| format!("{packed_type} %a{index}")))
+            .chain((0..b_count).map(|index| format!("{packed_type} %b{index}")))
+            .collect::<Vec<_>>();
+        let mut argument_values = (0..c_count)
+            .map(|index| format!("{c_type} %c{index}"))
+            .chain((0..a_count).map(|index| format!("{packed_type} %a{index}")))
+            .chain((0..b_count).map(|index| format!("{packed_type} %b{index}")))
+            .collect::<Vec<_>>();
+        if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 {
+            let block_scale_parameters = [
+                "i32 %scale_a",
+                "i16 %byte_id_a",
+                "i16 %thread_id_a",
+                "i32 %scale_b",
+                "i16 %byte_id_b",
+                "i16 %thread_id_b",
+            ];
+            parameter_values.extend(block_scale_parameters.map(str::to_owned));
+            argument_values.extend(block_scale_parameters.map(str::to_owned));
+        }
+        let parameters = parameter_values.join(", ");
+        let arguments = argument_values.join(", ");
+        let result = format!(
+            "{{ {} }}",
+            std::iter::repeat_n(result_type, d_count)
+                .collect::<Vec<_>>()
+                .join(", ")
+        );
+        writeln!(
+            output,
+            "define {result} @probe_{}({parameters}) #0 {{",
+            record.id
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "  %result = call {result} asm sideeffect {:?}, {:?}({arguments}) #0",
+            register_mma_template(record),
+            register_mma_constraints(record),
+        )
+        .unwrap();
+        output.push_str("  ret ");
+        output.push_str(&result);
+        output.push_str(" %result\n}\n\nattributes #0 = { convergent }\n");
+    } else if let Some(debug) = &record.debug_control {
+        let template = match debug.operation {
+            DebugControlOperation::Trap => "trap;",
+            DebugControlOperation::Breakpoint => "brkpt;",
+            DebugControlOperation::Pmevent => "pmevent 15;",
+        };
+        writeln!(output, "define void @probe_{}() {{", record.id).unwrap();
+        writeln!(output, "  call void asm sideeffect {:?}, \"\"()", template).unwrap();
+        output.push_str("  ret void\n}\n");
+    } else if record.family == "stmatrix" {
+        let (multiplicity, _) = stmatrix_variant(record).expect("stmatrix variant");
+        let count = multiplicity.register_count();
+        let symbol = llvm(record)
+            .resolved_symbol
+            .as_ref()
+            .expect("stmatrix resolved symbol");
+        let declaration = std::iter::once("ptr addrspace(3)".to_owned())
+            .chain(std::iter::repeat_n("i32".to_owned(), count))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let parameters = std::iter::once("ptr %generic".to_owned())
+            .chain((0..count).map(|index| format!("i32 %r{index}")))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let arguments = std::iter::once("ptr addrspace(3) %shared".to_owned())
+            .chain((0..count).map(|index| format!("i32 %r{index}")))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(output, "declare void @{symbol}({declaration})\n").unwrap();
+        writeln!(output, "define void @probe_{}({parameters}) {{", record.id).unwrap();
+        output.push_str("  %shared = addrspacecast ptr %generic to ptr addrspace(3)\n");
+        writeln!(output, "  call void @{symbol}({arguments})").unwrap();
+        output.push_str("  ret void\n}\n");
+    } else if record.prmt.is_some() {
+        let arity = record.rust.arguments.len();
+        let declaration = std::iter::repeat_n("i32", arity)
+            .collect::<Vec<_>>()
+            .join(", ");
+        let parameters = (0..arity)
+            .map(|index| format!("i32 %arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let arguments = (0..arity)
+            .map(|index| format!("i32 %arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(
+            output,
+            "declare i32 @{}({declaration})\n",
+            llvm(record).symbol
+        )
+        .unwrap();
+        writeln!(output, "define i32 @probe_{}({parameters}) {{", record.id).unwrap();
+        writeln!(
+            output,
+            "  %result = call i32 @{}({arguments})",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push_str("  ret i32 %result\n}\n");
+    } else if let Some(ldmatrix) = &record.ldmatrix {
+        let register_count = ldmatrix.variant.register_count();
+        let result_ty = if register_count == 1 {
+            "i32".to_owned()
+        } else {
+            format!(
+                "{{ {} }}",
+                std::iter::repeat_n("i32", register_count)
+                    .collect::<Vec<_>>()
+                    .join(", ")
+            )
+        };
+        let symbol = record
+            .llvm
+            .as_ref()
+            .expect("ldmatrix LLVM facts")
+            .resolved_symbol
+            .as_ref()
+            .expect("ldmatrix resolved symbol");
+        writeln!(output, "declare {result_ty} @{symbol}(ptr addrspace(3))").unwrap();
+        output.push('\n');
+        writeln!(
+            output,
+            "define {result_ty} @probe_{}(ptr %generic) {{",
+            record.id
+        )
+        .unwrap();
+        output.push_str("  %shared = addrspacecast ptr %generic to ptr addrspace(3)\n");
+        writeln!(
+            output,
+            "  %result = call {result_ty} @{symbol}(ptr addrspace(3) %shared)"
+        )
+        .unwrap();
+        writeln!(output, "  ret {result_ty} %result\n}}\n").unwrap();
+    } else if record.scalar_arithmetic.is_some() {
+        let ty = scalar_arithmetic_llvm_type(record);
+        let arity = scalar_arithmetic_arity(record);
+        let parameters = (0..arity)
+            .map(|index| format!("{ty} %arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let arguments = (0..arity)
+            .map(|index| format!("{ty} %arg{index}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        if scalar_arithmetic_llvm_mechanism(record) == BackendLoweringMechanism::TypedNvvm {
+            let declaration = std::iter::repeat_n(ty, arity)
+                .collect::<Vec<_>>()
+                .join(", ");
+            writeln!(
+                output,
+                "declare {ty} @{}({declaration})\n",
+                llvm(record).symbol
+            )
+            .unwrap();
+        }
+        writeln!(output, "define {ty} @probe_{}({parameters}) {{", record.id).unwrap();
+        match scalar_arithmetic_llvm_mechanism(record) {
+            BackendLoweringMechanism::TypedNvvm => {
+                writeln!(
+                    output,
+                    "  %result = call {ty} @{}({arguments})",
+                    llvm(record).symbol
+                )
+                .unwrap();
+            }
+            BackendLoweringMechanism::InlinePtx => {
+                let register = if ty == "double" { "d" } else { "f" };
+                let constraints = std::iter::once(format!("={register}"))
+                    .chain(std::iter::repeat_n(register.to_owned(), arity))
+                    .collect::<Vec<_>>()
+                    .join(",");
+                let operands = (0..=arity)
+                    .map(|index| format!("${index}"))
+                    .collect::<Vec<_>>()
+                    .join(", ");
+                writeln!(
+                    output,
+                    "  %result = call {ty} asm {:?}, {:?}({arguments})",
+                    format!("{} {operands};", scalar_arithmetic_ptx_mnemonic(record)),
+                    constraints,
+                )
+                .unwrap();
+            }
+        }
+        writeln!(output, "  ret {ty} %result\n}}").unwrap();
+    } else if record.scalar_math.is_some() {
+        let ty = scalar_math_llvm_type(record);
+        let parameters = format!("{ty} %arg0");
+        let arguments = format!("{ty} %arg0");
+        if scalar_math_llvm_mechanism(record) == BackendLoweringMechanism::TypedNvvm {
+            writeln!(output, "declare {ty} @{}({ty})\n", llvm(record).symbol).unwrap();
+        }
+        writeln!(output, "define {ty} @probe_{}({parameters}) {{", record.id).unwrap();
+        match scalar_math_llvm_mechanism(record) {
+            BackendLoweringMechanism::TypedNvvm => {
+                writeln!(
+                    output,
+                    "  %result = call {ty} @{}({arguments})",
+                    llvm(record).symbol
+                )
+                .unwrap();
+            }
+            BackendLoweringMechanism::InlinePtx => {
+                let register = match ty {
+                    "double" => "d",
+                    "i16" => "h",
+                    _ => "f",
+                };
+                writeln!(
+                    output,
+                    "  %result = call {ty} asm {:?}, {:?}({arguments})",
+                    format!("{} $0, $1;", scalar_math_ptx_mnemonic(record)),
+                    format!("={register},{register}"),
+                )
+                .unwrap();
+            }
+        }
+        writeln!(output, "  ret {ty} %result\n}}").unwrap();
+    } else if record.extended_minmax.is_some() {
+        let (ty, register) = match extended_minmax_contract(record).format {
+            ExtendedMinMaxFormat::F32 => ("float", "f"),
+            ExtendedMinMaxFormat::F16 | ExtendedMinMaxFormat::Bf16 => ("i16", "h"),
+            ExtendedMinMaxFormat::F16x2 | ExtendedMinMaxFormat::Bf16x2 => ("i32", "r"),
+        };
+        writeln!(
+            output,
+            "define {ty} @probe_{}({ty} %a, {ty} %b) {{",
+            record.id
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "  %result = call {ty} asm {:?}, {:?}({ty} %a, {ty} %b)",
+            format!("{} $0, $1, $2;", extended_minmax_ptx_mnemonic(record)),
+            format!("={register},{register},{register}"),
+        )
+        .unwrap();
+        writeln!(output, "  ret {ty} %result\n}}").unwrap();
+    } else if record.scalar_conversion.is_some() {
+        writeln!(output, "declare i32 @{}(float)", llvm(record).symbol).unwrap();
+        output.push('\n');
+        writeln!(output, "define i32 @probe_{}(float %value) {{", record.id).unwrap();
+        writeln!(
+            output,
+            "  %result = call i32 @{}(float %value)",
+            llvm(record).symbol
+        )
+        .unwrap();
+        output.push_str("  ret i32 %result\n}\n");
+    } else if let Some(width) = record.scalar_width() {
+        writeln!(output, "declare i{width} @{}()", llvm(record).symbol).unwrap();
+        output.push('\n');
+        writeln!(output, "define i{width} @probe_{}() {{", record.id).unwrap();
+        writeln!(
+            output,
+            "  %result = call i{width} @{}()",
+            llvm(record).symbol
+        )
+        .unwrap();
+        writeln!(output, "  ret i{width} %result\n}}\n").unwrap();
+    } else {
+        unreachable!("generated intrinsic has no probe renderer: {}", record.id);
+    }
+    output
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/raw_abi.rs b/crates/cuda-intrinsics-gen/src/render/raw_abi.rs
new file mode 100644
index 0000000000..460399d395
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/raw_abi.rs
@@ -0,0 +1,580 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    CatalogFile, ClusterBarrierOrdering, ClusterMemoryOperation, CpAsyncControlOperation,
+    CpAsyncMbarrierOperation, CpAsyncSourceSize, ExecutionControlOperation, LdmatrixParticipation,
+    LdmatrixShape, MbarrierBasicOperation, MbarrierExtendedAdapter, RegisterMmaAdapter,
+    RegisterMmaOverflow, SparseMmaOverflow, Tcgen05LdShape, Tcgen05Operation, TmaAdapter,
+    WarpShuffleValueKind, WgmmaControlMode,
+};
+use crate::render::common::{hardware_target_label, rust_header, source_label};
+use crate::render::families::{
+    ClcSafetyArgNames, is_blackwell_ldmatrix, render_clc_safety_lines, sparse_mma_fragment_counts,
+    sparse_mma_metadata_rule, sparse_mma_selector_description, stmatrix_variant, tcgen05_is_commit,
+    tcgen05_is_multicast_commit, tcgen05_is_shift, tcgen05_participation_doc,
+};
+use crate::render::reference::modules;
+use anyhow::Result;
+use std::fmt::Write as _;
+
+pub(super) fn render_raw_mod(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = rust_header(catalog, hash);
+    let abi_module = format!("__cuda_oxide_intrinsic_abi_v{}", catalog.intrinsic_abi);
+    writeln!(
+        output,
+        "#[doc(hidden)]\n#[path = \"abi_v{}.rs\"]\npub mod {abi_module};\n",
+        catalog.intrinsic_abi
+    )
+    .unwrap();
+    for module in modules(catalog) {
+        writeln!(
+            output,
+            "/// Generated `{module}` intrinsic source API.\npub mod {module} {{"
+        )
+        .unwrap();
+        for record in catalog
+            .intrinsics
+            .iter()
+            .filter(|record| record.rust.module == module)
+        {
+            writeln!(
+                output,
+                "    pub use crate::{abi_module}::{} as {};",
+                record.rust.abi_id, record.rust.name
+            )
+            .unwrap();
+        }
+        output.push_str("}\n\n");
+    }
+    output.push_str("#[cfg(test)]\n#[allow(clippy::type_complexity)]\nmod tests {\n");
+    for record in &catalog.intrinsics {
+        let arguments = record.rust.arguments.join(", ");
+        writeln!(
+            output,
+            "    #[test]\n    fn public_{}_reexports_abi_{}() {{",
+            record.rust.name, record.rust.abi_id
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "        let public: {}fn({}) -> {} = super::{}::{};",
+            if record.rust.safe { "" } else { "unsafe " },
+            arguments,
+            record.rust.result,
+            record.rust.module,
+            record.rust.name
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "        let canonical: {}fn({}) -> {} = super::{abi_module}::{};",
+            if record.rust.safe { "" } else { "unsafe " },
+            arguments,
+            record.rust.result,
+            record.rust.abi_id
+        )
+        .unwrap();
+        output.push_str("        assert_eq!(public as usize, canonical as usize);\n    }\n");
+    }
+    output.push_str("}\n");
+    output
+}
+
+pub(super) fn render_raw_abi(catalog: &CatalogFile, hash: &str) -> Result<String> {
+    let mut output = rust_header(catalog, hash);
+    output.push_str("//! Raw ABI functions recognized by cuda-oxide.\n\n");
+    for record in &catalog.intrinsics {
+        writeln!(output, "/// {}", record.summary).unwrap();
+        writeln!(output, "///").unwrap();
+        writeln!(
+            output,
+            "/// Catalog ID: `{}`. Source: {}; expects PTX `{}`.",
+            record.id,
+            source_label(record),
+            record.expected_ptx
+        )
+        .unwrap();
+        if is_blackwell_ldmatrix(record) {
+            writeln!(
+                output,
+                "/// Available on `{}` targets. Instruction floor PTX {}; the selected target may require a newer PTX version.",
+                hardware_target_label(&record.target.hardware),
+                record.target.minimum_ptx
+            )
+            .unwrap();
+        } else {
+            writeln!(
+                output,
+                "/// Available on `{}` targets from PTX {}.",
+                hardware_target_label(&record.target.hardware),
+                record.target.minimum_ptx
+            )
+            .unwrap();
+        }
+        if let Some(operation) = record.tcgen05.as_ref().map(|tcgen05| tcgen05.operation)
+            && let Some(participation) = tcgen05_participation_doc(operation)
+        {
+            writeln!(output, "/// {participation}").unwrap();
+        }
+        if record.tcgen05.is_some() {
+            output.push_str(
+                "/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n",
+            );
+        }
+        if let Some(reason) = &record.rust.safe_allowlist_reason {
+            writeln!(output, "/// Safe because {reason}").unwrap();
+        }
+        if !record.rust.safe {
+            output.push_str("///\n/// # Safety\n");
+            if let Some(ldmatrix) = &record.ldmatrix {
+                let variant = &ldmatrix.variant;
+                let contributing_lanes = variant.multiplicity.register_count() * 8;
+                let readable_bytes = if variant.shape == LdmatrixShape::M16n16 {
+                    32
+                } else {
+                    16
+                };
+                let participation = match ldmatrix.safety.participation {
+                    LdmatrixParticipation::AllWarpLanesSameInstruction => {
+                        "All 32 warp lanes must execute the same instruction."
+                    }
+                    LdmatrixParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes => {
+                        "All 32 warp lanes must execute the same instruction and qualifiers; no lane may have exited."
+                    }
+                };
+                writeln!(
+                    output,
+                    "/// {participation} PTX maps {contributing_lanes} lane-provided row addresses for this {:?} variant; addresses may alias, but each used address must be 16-byte aligned and have {readable_bytes} readable shared-memory bytes.",
+                    variant.multiplicity
+                )
+                .unwrap();
+                if matches!(
+                    ldmatrix.safety.address_contract,
+                    crate::model::LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadableWithSm75Replication
+                ) && contributing_lanes < 32
+                {
+                    output.push_str("/// For portable sm_75 behavior, otherwise-unused lanes must also carry valid addresses replicated from the contributing lanes.\n");
+                }
+                output.push_str(
+                    "/// This weak memory operation does not replace a required barrier or fence.\n",
+                );
+            } else if let Some((multiplicity, _)) = stmatrix_variant(record) {
+                let address_lanes = multiplicity.register_count() * 8;
+                writeln!(
+                    output,
+                    "/// All 32 warp lanes must execute the same instruction. The first {address_lanes} lanes must provide valid, 16-byte-aligned shared-memory row addresses."
+                )
+                .unwrap();
+                output.push_str(
+                    "/// Register operands must contain the packed b16 fragments required by the selected layout.\n/// This weak memory operation does not replace a required barrier or fence.\n",
+                );
+            } else if let Some(mma) = &record.sparse_mma {
+                let (c_count, a_count, b_count, _) = sparse_mma_fragment_counts(record);
+                output.push_str(
+                    "/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited.\n",
+                );
+                writeln!(
+                    output,
+                    "/// `_arg0`, `_arg1`, and `_arg2` hold this lane's {c_count}-register C, {a_count}-register A, and {b_count}-register B fragments; `_arg3` holds its sparse metadata."
+                )
+                .unwrap();
+                writeln!(
+                    output,
+                    "/// `_arg4` must be {}.",
+                    sparse_mma_selector_description(record)
+                )
+                .unwrap();
+                output.push_str("/// The operation is register-only and is not a memory fence.\n");
+                writeln!(output, "/// {}", sparse_mma_metadata_rule(mma)).unwrap();
+                writeln!(
+                    output,
+                    "/// See the [PTX sparse MMA fragment layouts]({}).",
+                    record.target.ptx_isa_url
+                )
+                .unwrap();
+                match mma.overflow {
+                    SparseMmaOverflow::NotApplicable => {}
+                    SparseMmaOverflow::Wrapping => {
+                        output.push_str(
+                            "/// Signed accumulator overflow wraps because this form omits `.satfinite`.\n",
+                        );
+                    }
+                    SparseMmaOverflow::Satfinite => output.push_str(
+                        "/// Signed accumulator overflow clamps to the finite `i32` range.\n",
+                    ),
+                }
+            } else if let Some(mma) = &record.register_mma {
+                output.push_str(
+                    "/// All 32 warp lanes must execute the same `mma.sync.aligned` instruction with the same qualifiers, and no lane may have exited.\n\
+                     /// `_arg0`, `_arg1`, and `_arg2` must contain this lane's C, A, and B fragments in the documented PTX layout.\n\
+                     /// The operation is register-only and is not a memory fence.\n",
+                );
+                if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
+                {
+                    output.push_str(
+                        "/// `_arg3` and `_arg6` contain this lane's packed A and B scale data. `_arg4`/`_arg5` and `_arg7`/`_arg8` are the corresponding byte/thread selectors.\n\
+                         /// For `scale_vec::1X`, A and B byte selectors must be in `0..=3`, the A thread selector in `0..=1`, and the B thread selector in `0..=3`; other values make the PTX operation undefined.\n",
+                    );
+                }
+                writeln!(
+                    output,
+                    "/// See the [PTX MMA fragment layouts]({}).",
+                    record.target.ptx_isa_url
+                )
+                .unwrap();
+                if mma.overflow == RegisterMmaOverflow::Wrapping {
+                    output.push_str("/// Signed accumulator overflow wraps because this form omits `.satfinite`.\n");
+                } else if mma.overflow == RegisterMmaOverflow::Satfinite {
+                    output.push_str(
+                        "/// Signed accumulator overflow clamps to the finite `i32` range.\n",
+                    );
+                }
+            } else if record.movmatrix.is_some() {
+                output.push_str(
+                    "/// All 32 warp lanes must execute the same instruction, and no lane may have exited.\n\
+                     /// `_arg0` must contain this lane's two packed b16 input elements.\n\
+                     /// The operation is register-only and is not a memory fence.\n",
+                );
+            } else if record.redux.is_some() {
+                output.push_str(
+                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `redux.sync` operation with the same qualifiers and mask.\n\
+                     /// The instruction waits for those lanes; violating this participation contract makes the PTX operation undefined.\n",
+                );
+            } else if record.warp_barrier.is_some() {
+                output.push_str(
+                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `bar.warp.sync` operation with the same mask.\n\
+                     /// On `sm_6x` and earlier, all lanes named in `mask` must execute the barrier in convergence, and no lane outside `mask` may be active when it executes.\n\
+                     /// The barrier orders memory accesses among participating lanes; violating the participation contract makes the PTX operation undefined.\n",
+                );
+            } else if record.warp_shuffle.is_some() {
+                output.push_str(
+                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `shfl.sync` operation with the same qualifiers and mask.\n\
+                     /// On `sm_6x` and earlier, all lanes named in `mask` must execute in convergence, and no lane outside `mask` may be active.\n\
+                     /// If the computed source lane is in range, it must be active and named in `mask`; otherwise the result is undefined. If PTX marks the computed source out of range, the calling lane's input is copied.\n",
+                );
+                if record
+                    .warp_shuffle
+                    .as_ref()
+                    .is_some_and(|shuffle| shuffle.value_kind == WarpShuffleValueKind::I64)
+                {
+                    output.push_str(
+                        "/// The 64-bit value is moved by two `b32` shuffles in one convergent block.\n",
+                    );
+                }
+            } else if record.warp_match.is_some() {
+                output.push_str(
+                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `match.sync` operation with the same qualifiers and mask.\n\
+                     /// Violating this participation contract makes the PTX operation undefined.\n",
+                );
+            } else if record.family == "elect" {
+                output.push_str(
+                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `elect.sync` operation with the same mask.\n\
+                     /// Violating this participation contract makes the PTX operation undefined.\n",
+                );
+            } else if record.vote.is_some() {
+                output.push_str(
+                    "/// The executing lane must be named in `mask`. Every non-exited lane named in `mask` must execute the same `vote.sync` operation with the same qualifiers and mask.\n\
+                     /// On `sm_6x` and earlier, all lanes named in `mask` must execute in convergence, and no lane outside `mask` may be active.\n\
+                     /// Violating this participation contract makes the PTX operation undefined.\n",
+                );
+            } else if record.family == "sync" {
+                output.push_str(
+                    "/// Every active thread in the CTA must reach the same barrier. Calling it from divergent control flow can deadlock the CTA.\n",
+                );
+            } else if record.family == "cluster_barrier" {
+                let barrier = record
+                    .cluster_barrier
+                    .as_ref()
+                    .expect("cluster-barrier contract");
+                output.push_str(
+                    "/// Each non-exited cluster thread must arrive exactly once before the barrier completes, then execute the matching wait.\n",
+                );
+                if barrier.aligned {
+                    output.push_str(
+                        "/// Every non-exited thread in the warp must execute this aligned instruction with identical control flow.\n",
+                    );
+                }
+                if barrier.ordering == ClusterBarrierOrdering::Relaxed {
+                    output.push_str(
+                        "/// This relaxed arrival does not publish earlier memory accesses; add the required cluster-scope fence before it.\n",
+                    );
+                }
+            } else if let Some(cluster) = &record.cluster_memory {
+                match cluster.operation {
+                    ClusterMemoryOperation::MapSharedRank => output.push_str(
+                        "/// `_arg0` must point into CTA shared memory, and `_arg1` must name a rank in the same live cluster.\n\
+                         /// The result is a cluster-shared pointer in address space 7. Dereferencing it performs a remote DSMEM access; ordinary loads and stores compile to `ld.shared::cluster` and `st.shared::cluster`. The target CTA must remain live and synchronization must make the access race-free.\n",
+                    ),
+                    ClusterMemoryOperation::ReadU32 => output.push_str(
+                        "/// `_arg0` must point to an aligned readable `u32` in CTA shared memory, and `_arg1` must name a rank in the same live cluster.\n\
+                         /// The target CTA must publish the value with the required cluster synchronization before this weak load.\n",
+                    ),
+                }
+            } else if let Some(control) = &record.wgmma_control {
+                output.push_str(
+                    "/// All four warps in the warpgroup must execute this instruction in convergence with the same control flow.\n",
+                );
+                match control.mode {
+                    WgmmaControlMode::Fence => output.push_str(
+                        "/// Issue it after register writes and before the WGMMA operations that consume those registers.\n",
+                    ),
+                    WgmmaControlMode::CommitGroup => output.push_str(
+                        "/// Issue it only after the warpgroup has submitted the WGMMA operations to commit.\n",
+                    ),
+                    WgmmaControlMode::WaitGroup => output.push_str(
+                        "/// `_arg0` must be a compile-time constant shared by the whole warpgroup.\n",
+                    ),
+                }
+            } else if let Some(tma) = &record.tma {
+                match tma.adapter {
+                    TmaAdapter::G2sPointersCoordinatesBarrierInjectDefaults
+                    | TmaAdapter::G2sPointersCoordinatesBarrierMaskInjectDefaults => output
+                        .push_str(
+                            "/// The destination and barrier must be valid shared-memory objects, and the tensor map must be a live descriptor for this dimensionality.\n\
+                             /// Keep every object alive until the asynchronous copy completes. Only the designated issuing thread may start this transfer.\n",
+                        ),
+                    TmaAdapter::S2gPointersCoordinatesInjectDefaults => output.push_str(
+                        "/// The source must name a live shared-memory tile, and the tensor map must be a live descriptor for this dimensionality.\n\
+                         /// Keep both objects alive until the committed bulk-copy group completes.\n",
+                    ),
+                    TmaAdapter::ReductionPointersCoordinatesInjectDefaults => output.push_str(
+                        "/// The source must name a live shared-memory tile, and the tensor map must describe a compatible global tensor destination for this dimensionality.\n\
+                         /// Keep both objects alive until the committed asynchronous reduction completes.\n",
+                    ),
+                    TmaAdapter::DescriptorPointer
+                    | TmaAdapter::DescriptorCoordinatesInjectDefaults
+                    | TmaAdapter::DescriptorCoordinatesCacheHintInjectFlag => output.push_str(
+                        "/// The tensor-map pointer must name a live, correctly encoded descriptor for this operation.\n",
+                    ),
+                    TmaAdapter::DescriptorAndAddressPointers
+                    | TmaAdapter::DescriptorOrdinalAndU32
+                    | TmaAdapter::DescriptorOrdinalAndU64
+                    | TmaAdapter::DescriptorAndImmediateU32
+                    | TmaAdapter::DescriptorAndRuntimeU32 => output.push_str(
+                        "/// The tensor-map pointer must name a writable, 128-byte descriptor in global memory, and every replacement value must satisfy the PTX field contract.\n",
+                    ),
+                    TmaAdapter::DescriptorPointerInjectBytes => output.push_str(
+                        "/// The tensor-map pointer must name a live 128-byte descriptor covered by the matching generic-proxy release fence.\n",
+                    ),
+                    TmaAdapter::NoOperands | TmaAdapter::CompileTimeConstantMaxPending => {}
+                }
+            } else if let Some(operation) = ExecutionControlOperation::from_catalog_id(&record.id) {
+                match operation {
+                    ExecutionControlOperation::BarrierCtaSync
+                    | ExecutionControlOperation::BarrierCtaSyncAligned
+                    | ExecutionControlOperation::BarrierCtaArrive
+                    | ExecutionControlOperation::BarrierCtaArriveAligned => output.push_str(
+                        "/// `_arg0` must identify a CTA barrier and `_arg1` must be the compatible expected thread count used by every participant.\n",
+                    ),
+                    ExecutionControlOperation::GridDependencyLaunchDependents
+                    | ExecutionControlOperation::GridDependencyWait => output.push_str(
+                        "/// The kernel launch must participate in a valid programmatic dependent-launch protocol.\n",
+                    ),
+                    ExecutionControlOperation::SetMaxNRegInc
+                    | ExecutionControlOperation::SetMaxNRegDec => output.push_str(
+                        "/// `_arg0` must be a compile-time multiple of eight in `24..=256`, and every thread in the warpgroup must execute the same operation and count.\n",
+                    ),
+                }
+            } else if let Some(bridge) = &record.cp_async_mbarrier {
+                output.push_str(
+                    "/// `_arg0` must point to a live, initialized, eight-byte-aligned mbarrier object in shared memory.\n\
+                     /// The issuing thread must have prior `cp.async` operations, and the object must remain valid until they complete.\n",
+                );
+                match bridge.operation {
+                    CpAsyncMbarrierOperation::Arrive => output.push_str(
+                        "/// This instruction increments the pending count before scheduling the asynchronous arrival; that increment must not exceed the barrier's pending-count limit.\n",
+                    ),
+                    CpAsyncMbarrierOperation::ArriveNoInc => output.push_str(
+                        "/// The barrier's initial pending count must already include the asynchronous arrival because this form does not increment it.\n",
+                    ),
+                }
+            } else if let Some(mbarrier) = &record.mbarrier_basic {
+                output.push_str(
+                    "/// `_arg0` must point to a live, eight-byte-aligned mbarrier object in shared memory.\n",
+                );
+                match mbarrier.operation {
+                    MbarrierBasicOperation::Init => output.push_str(
+                        "/// Exactly one thread may initialize the object. `_arg1` must be in `1..=0xFFFFF` and include every arrival in the phase.\n\
+                         /// The object must be uninitialized or invalidated, with no concurrent barrier operation.\n",
+                    ),
+                    MbarrierBasicOperation::Arrive => output.push_str(
+                        "/// The object must be initialized, and this arrival must be included in the current phase's expected count.\n\
+                         /// Use the returned token only with the same object and phase.\n",
+                    ),
+                    MbarrierBasicOperation::TestWait => output.push_str(
+                        "/// The object must be initialized. `_arg1` must be a token returned for the same object and phase.\n",
+                    ),
+                    MbarrierBasicOperation::Inval => output.push_str(
+                        "/// The object must be initialized and no thread or asynchronous operation may still use it.\n\
+                         /// Exactly one thread may invalidate the object.\n",
+                    ),
+                }
+            } else if let Some(mbarrier) = &record.mbarrier_extended {
+                output.push_str(
+                    "/// This is a convergent, side-effecting operation with a compiler memory clobber.\n",
+                );
+                match mbarrier.adapter {
+                    MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount => {
+                        output.push_str(
+                            "/// `_arg0` must point to a live, initialized, eight-byte-aligned mbarrier in shared memory. `_arg2` must match the asynchronous transaction bytes.\n\
+                             /// `_arg1` is retained for compatibility and is not a PTX operand.\n",
+                        );
+                    }
+                    MbarrierExtendedAdapter::RawClusterAddressToVoid => output.push_str(
+                        "/// `_arg0` must be a live remote shared-memory barrier address obtained through cluster address mapping.\n",
+                    ),
+                    MbarrierExtendedAdapter::PointerTokenToPredicate => output.push_str(
+                        "/// `_arg0` must point to a live initialized barrier. `_arg1` must be a token for that barrier and phase.\n",
+                    ),
+                    MbarrierExtendedAdapter::PointerParityToPredicate => output.push_str(
+                        "/// `_arg0` must point to a live initialized barrier. `_arg1` must be the expected phase parity.\n",
+                    ),
+                    MbarrierExtendedAdapter::ZeroOperandsToVoid => output.push_str(
+                        "/// The call site must satisfy the scope and proxy-ordering contract named by the operation.\n",
+                    ),
+                    MbarrierExtendedAdapter::NanosecondsToVoid => output.push_str(
+                        "/// `_arg0` is an approximate suspension duration; hardware may resume the thread earlier.\n",
+                    ),
+                }
+            } else if let Some(copy) = &record.cp_async_copy {
+                let bytes = copy.copy_size.bytes();
+                writeln!(
+                    output,
+                    "/// `_arg0` must point to {bytes} writable bytes in shared memory and be aligned to {bytes} bytes."
+                )
+                .unwrap();
+                if copy.source_size == CpAsyncSourceSize::Runtime {
+                    writeln!(
+                        output,
+                        "/// `_arg2` must be at most {bytes}; `_arg1` must point to that many readable bytes in global memory and be aligned to {bytes} bytes."
+                    )
+                    .unwrap();
+                } else {
+                    writeln!(
+                        output,
+                        "/// `_arg1` must point to {bytes} readable bytes in global memory and be aligned to {bytes} bytes."
+                    )
+                    .unwrap();
+                }
+                output.push_str(
+                    "/// Both ranges must remain valid, the source must remain unchanged, and the destination must not be accessed until this copy completes.\n\
+                     /// The issuing thread must use a matching `cp.async` completion operation. Synchronize threads after completion before another thread accesses the destination.\n\
+                     /// User-authored completion assembly must include a compiler memory clobber.\n",
+                );
+            } else if let Some(control) = &record.cp_async_control {
+                if control.operation == CpAsyncControlOperation::WaitGroup {
+                    output.push_str(
+                        "/// `_arg0` must be a compile-time constant. Access only destinations whose copy groups this wait completes.\n",
+                    );
+                } else if control.operation == CpAsyncControlOperation::WaitAll {
+                    output.push_str(
+                        "/// This waits only for copies issued by the executing thread. Synchronize threads before another thread accesses a completed destination.\n",
+                    );
+                } else {
+                    output.push_str(
+                        "/// This commits only copies issued by the executing thread and does not wait for completion.\n",
+                    );
+                }
+            } else if let Some(tcgen05) = &record.tcgen05 {
+                if tcgen05_is_commit(tcgen05.operation) {
+                    if tcgen05_is_multicast_commit(tcgen05.operation) {
+                        output.push_str(
+                            "/// `_arg0` must point to a live initialized cluster-shared mbarrier. `_arg1` must select valid CTA ranks in its cluster.\n",
+                        );
+                    } else {
+                        output.push_str(
+                            "/// `_arg0` must point to a live initialized mbarrier valid for this CTA-group mode.\n",
+                        );
+                    }
+                    output.push_str(
+                        "/// The same thread that issued the tracked asynchronous tcgen05 operations must issue this commit.\n",
+                    );
+                } else if tcgen05_is_shift(tcgen05.operation) {
+                    output.push_str(
+                        "/// `_arg0` must name a live tensor-memory allocation, and its lane component must be a multiple of 32.\n\
+                         /// Completion must be tracked by a matching commit from that same thread and observed through the selected mbarrier before relying on shifted data.\n",
+                    );
+                } else if tcgen05.operation == Tcgen05Operation::Ld {
+                    output.push_str(
+                        "/// `_arg0` must name a live tensor-memory allocation covering the selected tile.\n\
+                         /// All active warp lanes must execute convergently with the same address.\n\
+                         /// Complete the matching tensor-memory load wait before consuming the returned registers.\n",
+                    );
+                    if tcgen05
+                        .ld
+                        .is_some_and(|ld| ld.shape == Tcgen05LdShape::M16x32bx2)
+                    {
+                        output.push_str(
+                            "/// `_arg1` must be a compile-time constant; inline PTX encodes its low 32 bits.\n",
+                        );
+                    }
+                } else if tcgen05.operation == Tcgen05Operation::St {
+                    output.push_str(
+                        "/// `_arg0` must name a live tensor-memory allocation covering the selected tile.\n\
+                         /// All active warp lanes must execute convergently with the same address.\n\
+                         /// Complete the matching tensor-memory store wait before relying on completion or reusing the affected storage.\n",
+                    );
+                    if tcgen05
+                        .st
+                        .is_some_and(|st| st.shape == Tcgen05LdShape::M16x32bx2)
+                    {
+                        output.push_str(
+                            "/// `_arg1` must be a compile-time constant; inline PTX encodes its low 32 bits.\n",
+                        );
+                    }
+                } else {
+                    output.push_str(
+                        "/// The caller must satisfy the tcgen05 address, lifetime, and participation rules.\n",
+                    );
+                }
+            } else if record.packed_atomic.is_some() {
+                output.push_str(
+                    "/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes.\n\
+                     /// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane.\n\
+                     /// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access.\n",
+                );
+            } else if let Some(clc) = &record.clc {
+                render_clc_safety_lines(&mut output, clc.operation, ClcSafetyArgNames::RawAbi);
+            } else {
+                anyhow::bail!(
+                    "{} ({}) is unsafe but has no dedicated family safety renderer",
+                    record.id,
+                    record.family
+                );
+            }
+        }
+        if record.rust.arguments.len() > 7 {
+            output.push_str("#[allow(clippy::too_many_arguments)]\n");
+        }
+        if record.rust.must_use {
+            output.push_str("#[must_use]\n");
+        }
+        output.push_str("#[inline(never)]\n");
+        let safety = if record.rust.safe { "" } else { "unsafe " };
+        let arguments = record
+            .rust
+            .arguments
+            .iter()
+            .enumerate()
+            .map(|(index, ty)| format!("_arg{index}: {ty}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(
+            output,
+            "pub {safety}fn {}({arguments}) -> {} {{",
+            record.rust.abi_id, record.rust.result,
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "    unreachable!(\"generated CUDA intrinsic `{}` executed outside device compilation\")",
+            record.rust.canonical_path
+        )
+        .unwrap();
+        output.push_str("}\n\n");
+    }
+    Ok(output)
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/reference.rs b/crates/cuda-intrinsics-gen/src/render/reference.rs
new file mode 100644
index 0000000000..98f59a0cfa
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/reference.rs
@@ -0,0 +1,733 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogFile, ClusterBarrierOrdering, ClusterMemorySourceContract,
+    CpAsyncMbarrierOperation, CpAsyncMbarrierStateSpace, EvidenceArtifactKind, IntrinsicBackend,
+    MbarrierBasicOperation, MbarrierExtendedSourceContract, PackedAtomicFormat,
+    PackedConversionRounding, PackedConversionSaturation, RegisterMmaAdapter, RegisterMmaOperation,
+    RegisterMmaOverflow, RuntimeValidation, SparseMmaOverflow, WarpMatchAdapter,
+    WarpShuffleValueKind, WgmmaControlMode,
+};
+use crate::render::common::{
+    backend_label, evidence_stage_label, hardware_target_label, llvm, lowering_mechanism_label,
+    markdown_header, source_label,
+};
+use crate::render::families::{
+    BLACKWELL_LDMATRIX_EFFECTIVE_FLOORS, active_masks, cluster_barriers, cluster_memory,
+    cp_async_mbarriers, expected_ptx_head, is_blackwell_ldmatrix, mbarrier_basics,
+    mbarrier_extended, movmatrix, packed_alu_format_shape, packed_alu_ptx_mnemonic, packed_alus,
+    packed_atomics, packed_conversion_destination, packed_conversion_ptx_mnemonic,
+    packed_conversion_typed_llvm_name, packed_conversions, redux, register_mmas,
+    scalar_arithmetic_llvm_mechanism, scalar_arithmetic_ptx_mnemonic, scalar_arithmetics,
+    scalar_conversion_ptx_mnemonic, scalar_conversions, sparse_mma_metadata_rule,
+    sparse_mma_ptx_head, sparse_mma_selector_description, sparse_mmas, sync_intrinsics,
+    threadfence_ptx_level, vote_intrinsics, warp_barriers, warp_matches, warp_shuffles,
+    wgmma_controls,
+};
+use std::collections::BTreeSet;
+use std::fmt::Write as _;
+
+/// Escape a value for a GFM table cell.
+///
+/// A `|` splits the row before inline parsing runs, so it splits the cell even
+/// inside a code span. GFM's own rule is that a literal pipe must be written
+/// `\|` wherever it appears. Three catalog entries carry a literal pipe today:
+/// the `elect.sync` and `match.all.sync` PTX patterns write their two
+/// destinations as `<register|predicate>`. Their rows rendered with a seventh
+/// cell, which dropped the backend-evidence column.
+fn escape_table_cell(value: impl std::fmt::Display) -> String {
+    value.to_string().replace('|', "\\|")
+}
+
+pub(super) fn render_reference(catalog: &CatalogFile, hash: &str) -> String {
+    let mut output = markdown_header(catalog, hash);
+    output.push_str(
+        "# Generated Intrinsic Reference\n\nThis table is generated from the resolved catalog. Evidence stages below distinguish backend code generation, terminal validation, and GPU runtime execution; no runtime claim is made unless an executed stage is recorded.\n\n| Rust function | CUDA operation | Source | Effects | Availability | Backend evidence |\n|:--|:--|:--|:--|:--|:--|\n",
+    );
+    for record in &catalog.intrinsics {
+        let safety = if record.rust.safe { "safe" } else { "unsafe" };
+        let availability = if is_blackwell_ldmatrix(record) {
+            format!(
+                "Instruction floor PTX {} on {}; effective LLVM target floors: {BLACKWELL_LDMATRIX_EFFECTIVE_FLOORS}",
+                record.target.minimum_ptx,
+                hardware_target_label(&record.target.hardware)
+            )
+        } else {
+            format!(
+                "PTX {} on {}",
+                record.target.minimum_ptx,
+                hardware_target_label(&record.target.hardware)
+            )
+        };
+        writeln!(
+            output,
+            "| `{}` | `{}` | {} | {safety}; scope {}; {}; memory {}; convergent {} | {availability} ([PTX ISA {}, {}]({})) | {} on `{}`; expects `{}` (`{}`, SHA-256 `{}`) |",
+            escape_table_cell(&record.rust.public_path),
+            escape_table_cell(&record.dialect.op_name),
+            escape_table_cell(source_label(record)),
+            escape_table_cell(&record.semantics.execution_scope),
+            if record.semantics.pure { "pure" } else { "impure" },
+            escape_table_cell(&record.semantics.memory),
+            record.semantics.convergent,
+            escape_table_cell(&record.target.ptx_isa_version),
+            escape_table_cell(&record.target.ptx_isa_section),
+            escape_table_cell(&record.target.ptx_isa_url),
+            escape_table_cell(&record.backend.status),
+            escape_table_cell(&record.backend.profile),
+            escape_table_cell(&record.expected_ptx),
+            escape_table_cell(&record.backend.version),
+            escape_table_cell(&record.backend.sha256),
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Compiler identity and compatibility paths\n\n");
+    for record in &catalog.intrinsics {
+        writeln!(output, "- `{}` (`{}`)", record.id, record.rust.abi_id).unwrap();
+        writeln!(
+            output,
+            "  - canonical compiler path: `{}`",
+            record.rust.canonical_path
+        )
+        .unwrap();
+        writeln!(
+            output,
+            "  - public source path: `{}`",
+            record.rust.public_path
+        )
+        .unwrap();
+        for path in &record.rust.compatibility_paths {
+            writeln!(output, "  - compatibility compiler path: `{path}`").unwrap();
+        }
+    }
+    output.push_str("\n## Register-MMA contracts\n\n");
+    for record in register_mmas(catalog) {
+        let mma = record.register_mma.as_ref().unwrap();
+        let operation = match mma.operation {
+            RegisterMmaOperation::Multiply => "multiply-accumulate",
+            RegisterMmaOperation::AndPopc => "AND, population count, and accumulate",
+            RegisterMmaOperation::XorPopc => "XOR, population count, and accumulate",
+        };
+        let overflow = match mma.overflow {
+            RegisterMmaOverflow::NotApplicable => "not applicable",
+            RegisterMmaOverflow::Wrapping => "wrapping",
+            RegisterMmaOverflow::Satfinite => "finite saturation",
+        };
+        let runtime = match mma.runtime_validation {
+            RuntimeValidation::Unexecuted => "not executed on a GPU",
+            RuntimeValidation::Executed => "executed on a GPU",
+        };
+        if mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 {
+            writeln!(
+                output,
+                "- `{}` takes C, A, B, scale-A data/selectors, and scale-B data/selectors in PTX operand order, performs {operation}, and lowers to one convergent, register-only `{}` instruction. For `scale_vec::1X`, byte selectors must be in `0..=3`, the A thread selector in `0..=1`, and the B thread selector in `0..=3`. Every non-exited warp lane must execute the same instruction and qualifiers. Integer overflow is {overflow}; runtime validation is {runtime}.",
+                record.id,
+                expected_ptx_head(record),
+            )
+            .unwrap();
+        } else {
+            writeln!(
+                output,
+                "- `{}` takes fragments in C, A, B order, performs {operation}, and lowers to one convergent, register-only `{}` instruction. Every non-exited warp lane must execute the same instruction and qualifiers. Integer overflow is {overflow}; runtime validation is {runtime}.",
+                record.id,
+                expected_ptx_head(record),
+            )
+            .unwrap();
+        }
+    }
+    output.push_str("\n## Sparse-MMA contracts\n\n");
+    for record in sparse_mmas(catalog) {
+        let mma = record.sparse_mma.as_ref().unwrap();
+        let overflow = match mma.overflow {
+            SparseMmaOverflow::NotApplicable => "Overflow mode is not applicable.",
+            SparseMmaOverflow::Wrapping => "Integer overflow wraps.",
+            SparseMmaOverflow::Satfinite => "Integer overflow uses finite saturation.",
+        };
+        let runtime = match mma.runtime_validation {
+            RuntimeValidation::Unexecuted => "not executed on a GPU",
+            RuntimeValidation::Executed => "executed on a GPU",
+        };
+        let metadata = sparse_mma_metadata_rule(mma);
+        writeln!(
+            output,
+            "- `{}` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `{}` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be {}. Every non-exited warp lane must execute the same instruction and qualifiers. {metadata} {overflow} Runtime validation is {runtime}.",
+            record.id,
+            sparse_mma_ptx_head(record),
+            sparse_mma_selector_description(record),
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Packed-atomic contracts\n\n");
+    for record in packed_atomics(catalog) {
+        let packed = record.packed_atomic.as_ref().unwrap();
+        let format = match packed.format {
+            PackedAtomicFormat::F16x2 => "f16x2",
+            PackedAtomicFormat::Bf16x2 => "bf16x2",
+        };
+        writeln!(
+            output,
+            "- `{}` (`{format}`): the native PTX instruction starts at `sm_{}`; cuda-oxide admits it from {}. Omitted `.sem` / `.scope` mean relaxed GPU scope. Each 16-bit element rounds to nearest-even and `.noftz` preserves subnormal inputs and results. The elements are atomic independently, so the returned `u32` contains old per-element values that may not form one coherent pair. The pointer must address four writable, four-byte-aligned global bytes; do not mix whole-word or non-atomic overlapping access, and every racing atomic must use a mutually inclusive scope.",
+            record.id,
+            packed.native_minimum_sm,
+            hardware_target_label(&record.target.hardware),
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Redux contracts\n\n");
+    for record in redux(catalog) {
+        writeln!(
+            output,
+            "- `{}`: raw and dialect operands are `[member_mask, value]`, adapted to LLVM `(value, membermask)`. The executing lane must be named in the mask, and every non-exited named lane must execute the same instruction with the same qualifiers and mask.",
+            record.id,
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Packed-ALU contracts\n\n");
+    for record in packed_alus(catalog) {
+        let packed = record.packed_alu.as_ref().unwrap();
+        let (format, _, carrier, _, _) = packed_alu_format_shape(packed.format);
+        let backend_floors = record
+            .backend_lowerings
+            .iter()
+            .map(|lowering| {
+                let backend = match lowering.backend {
+                    IntrinsicBackend::LlvmNvptx => "LLVM-NVPTX",
+                    IntrinsicBackend::LibNvvm => "libNVVM",
+                };
+                format!(
+                    "{backend} PTX {} on {}",
+                    lowering.target.minimum_ptx,
+                    hardware_target_label(&lowering.target.hardware),
+                )
+            })
+            .collect::<Vec<_>>()
+            .join("; ");
+        writeln!(
+            output,
+            "- `{}` carries one packed `{format}` value in a `{carrier}` and lowers to one pure `{}` instruction. The native instruction starts at PTX {} / `sm_{}`; cuda-oxide admits it from {}. Backend profile floors: {backend_floors}.",
+            record.id,
+            packed_alu_ptx_mnemonic(record),
+            record.target.minimum_ptx,
+            packed.native_minimum_sm,
+            hardware_target_label(&record.target.hardware),
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Packed-conversion contract\n\n");
+    for record in packed_conversions(catalog) {
+        let conversion = record.packed_conversion.as_ref().unwrap();
+        let rounding = match conversion.rounding {
+            PackedConversionRounding::NearestEven => "nearest-even",
+            PackedConversionRounding::TowardZero => "toward-zero",
+        };
+        let saturation = match conversion.saturation {
+            PackedConversionSaturation::None => "without saturation",
+            PackedConversionSaturation::Relu => "with ReLU",
+            PackedConversionSaturation::Satfinite => "with finite saturation",
+            PackedConversionSaturation::SatfiniteRelu => "with finite saturation and ReLU",
+        };
+        if packed_conversion_typed_llvm_name(record).is_some() {
+            writeln!(
+                output,
+                "- `{}` converts two `f32` inputs to packed `{}` using {rounding} rounding {saturation}. LLVM-NVPTX uses typed `{}` with `[high, low]` inputs; libNVVM uses pure `{}` inline PTX. The public first input becomes the low lane and the second becomes the high lane.",
+                record.id,
+                packed_conversion_destination(record),
+                llvm(record).symbol,
+                packed_conversion_ptx_mnemonic(record),
+            )
+            .unwrap();
+        } else {
+            writeln!(
+                output,
+                "- `{}` converts two `f32` inputs to packed `{}` using {rounding} rounding {saturation}. It lowers to pure `{}` inline PTX. The first input becomes the low lane and the second becomes the high lane, so PTX prints the inputs in reverse order.",
+                record.id,
+                packed_conversion_destination(record),
+                packed_conversion_ptx_mnemonic(record),
+            )
+            .unwrap();
+        }
+    }
+    output.push_str("\n## Scalar TF32-conversion contract\n\n");
+    for record in scalar_conversions(catalog) {
+        writeln!(
+            output,
+            "- `{}` converts one `f32` value to raw TF32 bits with `{}`. LLVM-NVPTX uses the typed intrinsic; libNVVM uses pure inline PTX so the native target floor is preserved.",
+            record.id,
+            scalar_conversion_ptx_mnemonic(record),
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Explicit-rounding scalar-arithmetic contracts\n\n");
+    for record in scalar_arithmetics(catalog) {
+        let llvm_route = match scalar_arithmetic_llvm_mechanism(record) {
+            BackendLoweringMechanism::TypedNvvm => "the typed intrinsic",
+            BackendLoweringMechanism::InlinePtx => "pure inline PTX",
+        };
+        writeln!(
+            output,
+            "- `{}` performs `{}`. LLVM-NVPTX uses {llvm_route}; libNVVM uses pure inline PTX.",
+            record.id,
+            scalar_arithmetic_ptx_mnemonic(record),
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Warp vote contracts\n\n");
+    for record in vote_intrinsics(catalog) {
+        writeln!(
+            output,
+            "- `{}` keeps raw and dialect operands in `[member_mask, predicate]` order. The executing lane must be named in the mask, and every non-exited named lane must execute the same `vote.sync` instruction with the same qualifiers and mask. On `sm_6x` and earlier, all named lanes must execute in convergence and no unnamed lane may be active. Both immediate and register member masks are admitted.",
+            record.id,
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Active-mask contract\n\n");
+    for record in active_masks(catalog) {
+        writeln!(
+            output,
+            "- `{}` observes the lanes active at the instruction. LLVM uses the typed intrinsic; libNVVM uses reviewed convergent, side-effecting inline PTX because that backend does not select the intrinsic.",
+            record.id,
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Warp-match contracts\n\n");
+    for record in warp_matches(catalog) {
+        let adapter = match record.warp_match.as_ref().unwrap().adapter {
+            WarpMatchAdapter::DirectMask => "returns LLVM's mask directly",
+            WarpMatchAdapter::ProjectMaskDiscardPredicate => {
+                "projects field 0 from LLVM's `{i32, i1}` result"
+            }
+        };
+        writeln!(
+            output,
+            "- `{}` keeps operands in `[member_mask, value]` order and {adapter}. The executing lane must be named in the mask, and every non-exited named lane must execute the same `match.sync` operation with the same qualifiers and mask. All register/immediate value and mask forms are admitted.",
+            record.id,
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Warp-barrier contract\n\n");
+    for record in warp_barriers(catalog) {
+        writeln!(
+            output,
+            "- `{}` passes the 32-bit member mask directly to the typed LLVM intrinsic on both backends. The executing lane must be named in the mask, and every non-exited named lane must execute the same `bar.warp.sync` operation with the same mask. On `sm_6x` and earlier, all named lanes must execute the barrier in convergence, and no unnamed lane may be active when it executes. The barrier orders memory accesses among participating lanes. Both immediate and register masks are admitted.",
+            record.id,
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Warp-shuffle contracts\n\n");
+    for record in warp_shuffles(catalog) {
+        let shuffle = record.warp_shuffle.as_ref().unwrap();
+        let lowering = match shuffle.value_kind {
+            WarpShuffleValueKind::I32 | WarpShuffleValueKind::F32 => {
+                "Register and immediate lane/mask forms are admitted."
+            }
+            WarpShuffleValueKind::I64 => {
+                "One convergent, side-effecting inline-PTX block splits `i64`, performs low then high `b32` shuffles with the same register lane/mask, and reassembles it."
+            }
+        };
+        writeln!(
+            output,
+            "- `{}` keeps raw and dialect operands in `[member_mask, value, lane_or_delta]` order and inserts clamp `{}` during lowering. The executing lane must be named in the mask, and every non-exited named lane must execute the same `shfl.sync` operation with the same qualifiers and mask. On `sm_6x` and earlier, all named lanes must execute in convergence and no unnamed lane may be active. A computed in-range source must be active and named; if PTX marks it out of range, the calling lane's input is copied. {lowering}",
+            record.id,
+            shuffle.clamp,
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Cluster-barrier contracts\n\n");
+    for record in cluster_barriers(catalog) {
+        let barrier = record.cluster_barrier.as_ref().unwrap();
+        let ordering = match barrier.ordering {
+            ClusterBarrierOrdering::Release => "release",
+            ClusterBarrierOrdering::Relaxed => "relaxed",
+            ClusterBarrierOrdering::Acquire => "acquire",
+        };
+        let alignment = if barrier.aligned {
+            "Every non-exited warp thread must execute the same aligned instruction in identical control flow."
+        } else {
+            "The instruction is not aligned."
+        };
+        writeln!(
+            output,
+            "- `{}` has {ordering} ordering. Each non-exited cluster thread must arrive exactly once before completion, then execute the matching wait. {alignment}",
+            record.id,
+        )
+        .unwrap();
+    }
+    if cluster_barriers(catalog).next().is_some() {
+        output.push_str(
+            "- `cuda_device::cluster::cluster_sync` is the generated compatibility operation: aligned arrive followed by aligned wait.\n",
+        );
+    }
+    if cluster_memory(catalog).next().is_some() {
+        output.push_str("\n## Cluster-memory contracts\n\n");
+        for record in cluster_memory(catalog) {
+            match record.cluster_memory.as_ref().unwrap().source_contract {
+                ClusterMemorySourceContract::LlvmMapaSharedClusterAs7IdentityInlinePtx => {
+                    writeln!(
+                        output,
+                        "- `{}` preserves LLVM 22's address-space-7 result. Both backends use exact convergent `mapa.shared::cluster.u64` inline PTX, and ordinary Rust dereference of the mapped pointer lowers through cluster shared memory.",
+                        record.id
+                    )
+                    .unwrap();
+                }
+                ClusterMemorySourceContract::PtxNativeMapaThenWeakClusterLoad => {
+                    writeln!(
+                        output,
+                        "- `{}` has no one-to-one LLVM intrinsic. Both backends use one convergent `mapa.shared::cluster.u64` plus `ld.shared::cluster.u32` block with a compiler memory clobber.",
+                        record.id
+                    )
+                    .unwrap();
+                }
+            }
+        }
+    }
+    if movmatrix(catalog).next().is_some() {
+        output.push_str("\n## movmatrix contracts\n\n");
+        for record in movmatrix(catalog) {
+            writeln!(
+                output,
+                "- `{}` transposes one packed b16 fragment in registers. All warp lanes must execute the same instruction, and no lane may have exited.",
+                record.id,
+            )
+            .unwrap();
+        }
+    }
+    if mbarrier_extended(catalog).next().is_some() {
+        output.push_str("\n## Extended mbarrier contracts\n\n");
+        for record in mbarrier_extended(catalog) {
+            let contract = record.mbarrier_extended.as_ref().unwrap();
+            let source = match contract.source_contract {
+                MbarrierExtendedSourceContract::LlvmImported => "LLVM 22 TableGen",
+                MbarrierExtendedSourceContract::PtxNativeRawClusterAddress => {
+                    "PTX-native raw-address contract"
+                }
+            };
+            writeln!(
+                output,
+                "- `{}` keeps its established CUDA-device signature and exact convergent inline-PTX memory clobber. Its source identity is {source}.",
+                record.id,
+            )
+            .unwrap();
+        }
+    }
+    if wgmma_controls(catalog).next().is_some() {
+        output.push_str("\n## WGMMA-control contracts\n\n");
+        for record in wgmma_controls(catalog) {
+            let detail = match record.wgmma_control.as_ref().unwrap().mode {
+                WgmmaControlMode::Fence => {
+                    "It orders register writes before later WGMMA operations."
+                }
+                WgmmaControlMode::CommitGroup => {
+                    "It commits the warpgroup's prior uncommitted WGMMA operations."
+                }
+                WgmmaControlMode::WaitGroup => {
+                    "Its `u64` argument must be a compile-time constant."
+                }
+            };
+            writeln!(
+                output,
+                "- `{}` must be executed by all four warps in the warpgroup with the same control flow. {detail}",
+                record.id,
+            )
+            .unwrap();
+        }
+    }
+    if sync_intrinsics(catalog).any(|record| threadfence_ptx_level(record).is_some()) {
+        output.push_str("\n## Synchronization contracts\n\n");
+    } else {
+        output.push_str("\n## CTA synchronization contracts\n\n");
+    }
+    for record in sync_intrinsics(catalog) {
+        if record.id == "sync_threads" {
+            writeln!(
+                output,
+                "- `{}` inserts the fixed barrier ID `0`. Every active CTA thread must reach the same barrier; divergent use can deadlock the CTA.",
+                record.id,
+            )
+            .unwrap();
+        } else {
+            let level = threadfence_ptx_level(record)
+                .expect("resolver admitted an unknown generated synchronization record");
+            writeln!(
+                output,
+                "- `{}` emits `membar.{level}` through the reviewed typed NVVM route on both backends.",
+                record.id,
+            )
+            .unwrap();
+        }
+    }
+    output.push_str("\n## cp.async mbarrier contracts\n\n");
+    for record in cp_async_mbarriers(catalog) {
+        let bridge = record.cp_async_mbarrier.as_ref().unwrap();
+        let address = match bridge.state_space {
+            CpAsyncMbarrierStateSpace::Generic => "generic",
+            CpAsyncMbarrierStateSpace::Shared => "explicit shared",
+        };
+        let counting = match bridge.operation {
+            CpAsyncMbarrierOperation::Arrive => {
+                "increments the pending count before the later asynchronous decrement"
+            }
+            CpAsyncMbarrierOperation::ArriveNoInc => {
+                "does not increment the pending count, so initialization must already include the later asynchronous decrement"
+            }
+        };
+        writeln!(
+            output,
+            "- `{}` uses {address} addressing and {counting}. It associates only the executing thread's prior `cp.async` operations with a live, eight-byte-aligned shared-memory barrier. LLVM-NVPTX uses the typed intrinsic; libNVVM uses reviewed convergent, side-effecting inline PTX with a memory clobber.",
+            record.id,
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Basic mbarrier contracts\n\n");
+    for record in mbarrier_basics(catalog) {
+        let mbarrier = record.mbarrier_basic.as_ref().unwrap();
+        let contract = match mbarrier.operation {
+            MbarrierBasicOperation::Init => {
+                "initializes one eight-byte-aligned shared-memory object exactly once with an expected count in `1..=0xFFFFF`"
+            }
+            MbarrierBasicOperation::Arrive => {
+                "records one expected arrival and returns a token for the same barrier phase"
+            }
+            MbarrierBasicOperation::TestWait => {
+                "tests one token from the same barrier phase with convergent, side-effecting inline PTX"
+            }
+            MbarrierBasicOperation::Inval => {
+                "invalidates an initialized barrier only after all users are finished"
+            }
+        };
+        let mechanism = if mbarrier.operation == MbarrierBasicOperation::TestWait {
+            "inline PTX on both backends"
+        } else {
+            "the typed NVVM intrinsic with LLVM-NVPTX and inline PTX with libNVVM"
+        };
+        writeln!(
+            output,
+            "- `{}` {contract}. It lowers through {mechanism}; generic MIR pointers are normalized to shared address space during lowering.",
+            record.id,
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Imported LLVM properties and result facts\n\n");
+    for record in &catalog.intrinsics {
+        let Some(llvm) = &record.llvm else {
+            writeln!(
+                output,
+                "- `{}`: PTX-native source; no LLVM record, symbol, properties, or selection facts.",
+                record.id
+            )
+            .unwrap();
+            continue;
+        };
+        let properties = record
+            .llvm
+            .as_ref()
+            .unwrap()
+            .properties
+            .iter()
+            .map(|property| format!("`{property}`"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        let range = record
+            .llvm
+            .as_ref()
+            .unwrap()
+            .result_facts
+            .range
+            .as_ref()
+            .map(|range| format!("[{}, {})", range.lower, range.upper_exclusive))
+            .unwrap_or_else(|| "none".to_owned());
+        let selection_records = record
+            .selections
+            .iter()
+            .map(|selection| format!("`{}`", selection.source_record))
+            .collect::<BTreeSet<_>>()
+            .into_iter()
+            .collect::<Vec<_>>()
+            .join(", ");
+        let selection_predicates = record
+            .selections
+            .iter()
+            .flat_map(|selection| selection.predicates.iter())
+            .map(|predicate| format!("`{predicate}`"))
+            .collect::<BTreeSet<_>>()
+            .into_iter()
+            .collect::<Vec<_>>()
+            .join(", ");
+        writeln!(
+            output,
+            "- `{}`: properties {}; result `NoUndef` {}; half-open result range `{}`; selection records {}; selection predicates {}",
+            record.id,
+            properties,
+            llvm.result_facts.no_undef,
+            range,
+            selection_records,
+            if selection_predicates.is_empty() {
+                "none"
+            } else {
+                &selection_predicates
+            }
+        )
+        .unwrap();
+    }
+    output.push_str("\n## Backend-specific lowering evidence\n\n");
+    for record in &catalog.intrinsics {
+        if record.backend_lowerings.is_empty() {
+            continue;
+        }
+        let runtime = record
+            .ldmatrix
+            .as_ref()
+            .map(|record| format!("{:?}", record.safety.runtime_validation).to_lowercase())
+            .or_else(|| {
+                record
+                    .packed_atomic
+                    .as_ref()
+                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
+            })
+            .or_else(|| {
+                record
+                    .mbarrier_basic
+                    .as_ref()
+                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
+            })
+            .or_else(|| {
+                record
+                    .movmatrix
+                    .as_ref()
+                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
+            })
+            .or_else(|| {
+                record
+                    .mbarrier_extended
+                    .as_ref()
+                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
+            })
+            .or_else(|| {
+                record
+                    .cp_async_mbarrier
+                    .as_ref()
+                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
+            })
+            .or_else(|| {
+                record
+                    .register_mma
+                    .as_ref()
+                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
+            })
+            .or_else(|| {
+                record
+                    .sparse_mma
+                    .as_ref()
+                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
+            })
+            .or_else(|| {
+                record
+                    .debug_control
+                    .as_ref()
+                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
+            })
+            .or_else(|| {
+                record
+                    .cluster_memory
+                    .as_ref()
+                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
+            })
+            .or_else(|| {
+                record
+                    .tcgen05
+                    .as_ref()
+                    .map(|record| format!("{:?}", record.runtime_validation).to_lowercase())
+            })
+            .or_else(|| (record.family == "stmatrix").then(|| "unexecuted".to_owned()))
+            .unwrap_or_else(|| "not recorded".to_owned());
+        writeln!(output, "- `{}`: runtime `{runtime}`", record.id).unwrap();
+        for lowering in &record.backend_lowerings {
+            writeln!(
+                output,
+                "  - `{}` uses `{}` from profile `{}` at PTX {} / {}: status `{}` (`{}`, SHA-256 `{}`)",
+                backend_label(lowering.backend),
+                lowering_mechanism_label(lowering.mechanism),
+                lowering.evidence_profile,
+                lowering.target.minimum_ptx,
+                hardware_target_label(&lowering.target.hardware),
+                lowering.status,
+                lowering.version,
+                lowering.sha256,
+            )
+            .unwrap();
+            for stage in &lowering.stages {
+                let tool = match (
+                    stage.tool_path.as_deref(),
+                    stage.tool_version.as_deref(),
+                    stage.tool_sha256.as_deref(),
+                ) {
+                    (Some(path), Some(version), Some(sha256)) => {
+                        format!(" Tool `{path}` reports `{version}` (SHA-256 `{sha256}`).")
+                    }
+                    _ => String::new(),
+                };
+                let artifact = match stage.artifact_kind {
+                    Some(EvidenceArtifactKind::Cubin) => " Artifact `cubin`.",
+                    None => "",
+                };
+                writeln!(
+                    output,
+                    "    - {} on `{}`: `{}` — {}{}{}",
+                    evidence_stage_label(stage.stage),
+                    stage.targets.join(", "),
+                    stage.outcome,
+                    stage.detail,
+                    tool,
+                    artifact,
+                )
+                .unwrap();
+            }
+        }
+    }
+    output
+}
+
+pub(super) fn render_compiler_path_patterns(
+    output: &mut String,
+    catalog: &CatalogFile,
+    indent: &str,
+) {
+    let paths: Vec<_> = catalog
+        .intrinsics
+        .iter()
+        .flat_map(|record| {
+            std::iter::once(record.rust.canonical_path.as_str())
+                .chain(record.rust.compatibility_paths.iter().map(String::as_str))
+        })
+        .collect();
+    render_string_patterns(output, &paths, indent);
+}
+
+pub(super) fn render_string_patterns(output: &mut String, values: &[&str], indent: &str) {
+    for (index, value) in values.iter().enumerate() {
+        if index == 0 {
+            writeln!(output, "{indent}{value:?}").unwrap();
+        } else {
+            writeln!(output, "{indent}| {value:?}").unwrap();
+        }
+    }
+}
+
+pub(super) fn render_inline_patterns(output: &mut String, values: &[&str]) {
+    for (index, value) in values.iter().enumerate() {
+        if index != 0 {
+            output.push_str(" | ");
+        }
+        write!(output, "{value:?}").unwrap();
+    }
+}
+
+#[allow(dead_code)]
+pub(super) fn modules(catalog: &CatalogFile) -> BTreeSet<&str> {
+    catalog
+        .intrinsics
+        .iter()
+        .map(|record| record.rust.module.as_str())
+        .collect()
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/tests/mma.rs b/crates/cuda-intrinsics-gen/src/render/tests/mma.rs
new file mode 100644
index 0000000000..5b1d4c4570
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/tests/mma.rs
@@ -0,0 +1,1160 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::*;
+
+use crate::model::{
+    RegisterMmaAdapter, RegisterMmaCompatibilitySource, RegisterMmaKind, RuntimeValidation,
+    SparseMmaAccumulator, SparseMmaAdapter, SparseMmaShape,
+};
+use crate::render::collector_targets::generated_intrinsic_variant;
+use crate::render::common::intrinsic_marker;
+use crate::render::families::{
+    BLACKWELL_LDMATRIX_EFFECTIVE_FLOORS, SPARSE_MMA_ORDERED_METADATA_RULE,
+    SPARSE_MMA_STANDARD_METADATA_RULE, ldmatrix, register_mma_attr_variants,
+    register_mma_constraints, register_mma_template, register_mmas, sparse_mma_carriers,
+    sparse_mma_constraints, sparse_mma_fragment_counts, sparse_mma_selector_values,
+    sparse_mma_template, sparse_mmas,
+};
+use crate::util::read_json;
+use std::path::Path;
+
+#[test]
+fn stmatrix_rendering_preserves_all_four_public_and_backend_contracts() {
+    let catalog = catalog_with_stmatrix();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(stmatrices(&catalog).count(), 4);
+
+    let compatibility = render_compat_stmatrix(&catalog, "test-hash");
+    for signature in [
+        "pub unsafe fn stmatrix_m8n8_x2(smem_ptr: *mut u8, r0: u32, r1: u32)",
+        "pub unsafe fn stmatrix_m8n8_x2_trans(smem_ptr: *mut u8, r0: u32, r1: u32)",
+        "pub unsafe fn stmatrix_m8n8_x4(smem_ptr: *mut u8, r0: u32, r1: u32, r2: u32, r3: u32)",
+        "pub unsafe fn stmatrix_m8n8_x4_trans(smem_ptr: *mut u8, r0: u32, r1: u32, r2: u32, r3: u32)",
+    ] {
+        assert!(compatibility.contains(signature));
+    }
+    assert!(compatibility.contains("All warp lanes must participate"));
+
+    let dialect_mod = render_dialect_mod(&catalog, "test-hash");
+    assert!(dialect_mod.contains("mod stmatrix;"));
+    assert!(dialect_mod.contains("stmatrix::register(ctx)"));
+    let dialect = render_dialect_stmatrix(&catalog, "test-hash");
+    for (op_type, op_name, operands) in [
+        ("StmatrixM8n8X2Op", "nvvm.stmatrix_m8n8_x2", 3),
+        ("StmatrixM8n8X2TransOp", "nvvm.stmatrix_m8n8_x2_trans", 3),
+        ("StmatrixM8n8X4Op", "nvvm.stmatrix_m8n8_x4", 5),
+        ("StmatrixM8n8X4TransOp", "nvvm.stmatrix_m8n8_x4_trans", 5),
+    ] {
+        assert!(dialect.contains(&format!("pub struct {op_type};")));
+        assert!(dialect.contains(&format!("name = \"{op_name}\"")));
+        assert!(dialect.contains(&format!("NOpdsInterface<{operands}>")));
+        assert!(dialect.contains(&format!("{op_type}::register(ctx)")));
+    }
+
+    let importer = render_importer(&catalog, "test-hash");
+    for (path, op_type, marker) in [
+        (
+            "cuda_device::tcgen05::stmatrix_m8n8_x2",
+            "StmatrixM8n8X2Op",
+            "v1:i0301",
+        ),
+        (
+            "cuda_device::tcgen05::stmatrix_m8n8_x2_trans",
+            "StmatrixM8n8X2TransOp",
+            "v1:i0302",
+        ),
+        (
+            "cuda_device::tcgen05::stmatrix_m8n8_x4",
+            "StmatrixM8n8X4Op",
+            "v1:i0303",
+        ),
+        (
+            "cuda_device::tcgen05::stmatrix_m8n8_x4_trans",
+            "StmatrixM8n8X4TransOp",
+            "v1:i0304",
+        ),
+    ] {
+        assert!(importer.contains(path));
+        assert!(importer.contains(&format!("{op_type}::get_concrete_op_info()")));
+        assert!(importer.contains(&format!(
+            "set_generated_intrinsic_marker(ctx, store, \"{marker}\")"
+        )));
+    }
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert_eq!(
+        lowering
+            .matches("impl MirToLlvmConversion for StmatrixM8n8")
+            .count(),
+        4
+    );
+    assert!(lowering.contains("IntrinsicBackend::LlvmNvptx"));
+    assert!(lowering.contains("IntrinsicBackend::LibNvvm"));
+    assert!(lowering.contains("cast_to_shared_addrspace"));
+    assert!(lowering.contains("llvm_nvvm_stmatrix_sync_aligned_m8n8_x2_b16_p3"));
+    assert!(lowering.contains("llvm_nvvm_stmatrix_sync_aligned_m8n8_x4_trans_b16_p3"));
+    assert!(lowering.contains("stmatrix.sync.aligned.m8n8.x{register_count}{trans}.shared.b16"));
+    assert!(lowering.contains("std::iter::once(\"~{memory}\")"));
+
+    let x2 = stmatrices(&catalog)
+        .find(|record| record.id == "stmatrix_m8n8_x2_b16")
+        .unwrap();
+    let probe = render_probe(&catalog, x2, "test-hash");
+    assert!(probe.contains(
+        "declare void @llvm.nvvm.stmatrix.sync.aligned.m8n8.x2.b16.p3(ptr addrspace(3), i32, i32)"
+    ));
+    assert!(probe.contains("%shared = addrspacecast ptr %generic to ptr addrspace(3)"));
+    assert!(probe.contains(
+            "call void @llvm.nvvm.stmatrix.sync.aligned.m8n8.x2.b16.p3(ptr addrspace(3) %shared, i32 %r0, i32 %r1)"
+        ));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/stmatrix.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/stmatrix.rs"
+    )));
+}
+
+#[test]
+fn ldmatrix_family_lowering_uses_one_attribute_dispatch_impl() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+
+    let dialect = render_dialect_ldmatrix(&catalog, "test-hash");
+    let rendered = render_lowering(&catalog, "test-hash");
+    assert_eq!(
+        rendered
+            .matches("impl MirToLlvmConversion for LdmatrixOp")
+            .count(),
+        1
+    );
+    assert!(rendered.contains("LdmatrixMultiplicityAttr::X4"));
+    assert!(rendered.contains("LdmatrixMultiplicityAttr::X2"));
+    assert!(rendered.contains("LdmatrixMultiplicityAttr::X1"));
+    assert!(rendered.contains("LdmatrixLayoutAttr::Transposed"));
+    assert!(rendered.contains("llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16_p3"));
+    for (op_type, op_name, count, instruction_head, intrinsic) in [
+        (
+            "LdmatrixX1Op",
+            "nvvm.ldmatrix_x1",
+            1,
+            "ldmatrix.sync.aligned.m8n8.x1.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_b16_p3",
+        ),
+        (
+            "LdmatrixX1TransOp",
+            "nvvm.ldmatrix_x1_trans",
+            1,
+            "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_trans_b16_p3",
+        ),
+        (
+            "LdmatrixX2Op",
+            "nvvm.ldmatrix_x2",
+            2,
+            "ldmatrix.sync.aligned.m8n8.x2.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_b16_p3",
+        ),
+        (
+            "LdmatrixX2TransOp",
+            "nvvm.ldmatrix_x2_trans",
+            2,
+            "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
+        ),
+        (
+            "LdmatrixX4Op",
+            "nvvm.ldmatrix_x4",
+            4,
+            "ldmatrix.sync.aligned.m8n8.x4.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_b16_p3",
+        ),
+        (
+            "LdmatrixX4TransOp",
+            "nvvm.ldmatrix_x4_trans",
+            4,
+            "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
+        ),
+    ] {
+        assert!(dialect.contains(&format!("pub struct {op_type};")));
+        assert!(dialect.contains(&format!("name = {op_name:?}")));
+        assert!(dialect.contains(&format!("NResultsInterface<{count}>")));
+        assert!(dialect.contains(&format!("{op_type}::register(ctx);")));
+        assert_eq!(
+            rendered
+                .matches(&format!("impl MirToLlvmConversion for {op_type}"))
+                .count(),
+            1
+        );
+        assert!(rendered.contains(&format!(
+            "self.get_operation(), {count}, {instruction_head:?}, {intrinsic:?}"
+        )));
+    }
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(!importer.contains("LdmatrixX1Op"));
+    assert!(!importer.contains("LdmatrixX4TransOp"));
+    let targets = render_targets(&catalog, "test-hash");
+    for op_name in [
+        "nvvm.ldmatrix_x1",
+        "nvvm.ldmatrix_x1_trans",
+        "nvvm.ldmatrix_x2",
+        "nvvm.ldmatrix_x2_trans",
+        "nvvm.ldmatrix_x4",
+        "nvvm.ldmatrix_x4_trans",
+    ] {
+        assert!(targets.contains(&format!("{op_name:?} => Some(")));
+    }
+    assert_eq!(ldmatrix(&catalog).count(), 18);
+    assert!(dialect.contains("LdmatrixShapeAttr::M16n16"));
+    assert!(dialect.contains("LdmatrixShapeAttr::M8n16"));
+    assert!(dialect.contains("LdmatrixElementAttr::B8x16B4x16P64"));
+    assert!(
+        rendered.contains(
+            "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db4x16_up64_dp3"
+        )
+    );
+    assert!(rendered.contains("ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b6x16_p32"));
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains(
+        "Instruction floor PTX 8.6; the selected target may require a newer PTX version."
+    ));
+    assert!(raw.contains("no lane may have exited"));
+    assert!(raw.contains("have 32 readable shared-memory bytes"));
+    assert!(raw.contains("have 16 readable shared-memory bytes"));
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains(BLACKWELL_LDMATRIX_EFFECTIVE_FLOORS));
+}
+
+#[test]
+fn ldmatrix_x1_probe_keeps_its_pointer_operand() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    let record = catalog
+        .intrinsics
+        .iter()
+        .find(|record| record.id == "ldmatrix_m8n8_x1_b16")
+        .unwrap();
+
+    let rendered = render_probe(&catalog, record, "test-hash");
+    assert!(
+        rendered.contains(
+            "declare i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.b16.p3(ptr addrspace(3))"
+        )
+    );
+    assert!(rendered.contains("define i32 @probe_ldmatrix_m8n8_x1_b16(ptr %generic)"));
+    assert!(!rendered.contains("@llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.b16.p3()"));
+}
+
+#[test]
+fn movmatrix_rendering_owns_dialect_import_and_lowering() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let mut catalog = crate::resolve::resolve(&repo_root).unwrap();
+    let mut record = catalog
+        .intrinsics
+        .iter()
+        .find(|record| record.id == "packed_atomic_add_f16x2")
+        .unwrap()
+        .clone();
+    record.id = "movmatrix_trans_b16".into();
+    record.operation_key = "movmatrix.m8n8.trans.b16".into();
+    record.family = "movmatrix".into();
+    record.rust.abi_id = "i0305".into();
+    record.rust.module = "matrix".into();
+    record.rust.name = "movmatrix_trans_b16".into();
+    record.rust.arguments = vec!["u32".into()];
+    record.rust.result = "u32".into();
+    record.rust.safe = false;
+    record.rust.must_use = true;
+    record.rust.canonical_path = "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305".into();
+    record.rust.public_path = "cuda_intrinsics::matrix::movmatrix_trans_b16".into();
+    record.rust.compatibility_paths = vec!["cuda_device::wmma::movmatrix_trans_b16".into()];
+    record.dialect.op_type = "MovmatrixTransB16Op".into();
+    record.dialect.op_name = "nvvm.movmatrix_trans_b16".into();
+    record.dialect.operands = vec!["i32".into()];
+    record.dialect.results = vec!["i32".into()];
+    record.semantics.pure = false;
+    record.semantics.memory = "inaccessible_read_write".into();
+    record.semantics.convergent = true;
+    record.semantics.execution_scope = "warp".into();
+    record.packed_atomic = None;
+    record.movmatrix = Some(crate::model::Movmatrix {
+        participation:
+            crate::model::MovmatrixParticipation::AllWarpLanesSameInstructionNoExitedLanes,
+        adapter: crate::model::MovmatrixAdapter::PackedB16x2U32ToPackedB16x2U32,
+        runtime_validation: RuntimeValidation::Unexecuted,
+    });
+    record.lowering = "generated_movmatrix_inline_ptx".into();
+    record.expected_ptx = crate::ptx::InstructionPattern::new(
+        "movmatrix",
+        &["sync", "aligned", "m8n8", "trans", "b16"],
+        vec![
+            crate::ptx::OperandPattern::Register,
+            crate::ptx::OperandPattern::Register,
+        ],
+    );
+    record.summary = "Transposes one packed b16 matrix fragment across a warp.".into();
+    catalog.intrinsics.push(record);
+
+    validate_renderable(&catalog).unwrap();
+    let dialect_mod = render_dialect_mod(&catalog, "test-hash");
+    assert!(dialect_mod.contains("mod movmatrix;"));
+    assert!(dialect_mod.contains("movmatrix::register(ctx);"));
+
+    let dialect = render_dialect_movmatrix(&catalog, "test-hash");
+    assert!(dialect.contains("pub struct MovmatrixTransB16Op;"));
+    assert!(dialect.contains("name = \"nvvm.movmatrix_trans_b16\""));
+    assert!(dialect.contains("MovmatrixTransB16Op::register(ctx);"));
+
+    let compatibility = render_compat_movmatrix(&catalog, "test-hash");
+    assert!(compatibility.contains("pub unsafe fn movmatrix_trans_b16(value: u32) -> u32"));
+    assert!(compatibility.contains("All 32 warp lanes must execute the same call"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::wmma::movmatrix_trans_b16"));
+    assert!(importer.contains("MovmatrixTransB16Op::build(ctx, arg0)"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("impl MirToLlvmConversion for MovmatrixTransB16Op"));
+    assert!(lowering.contains("movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;"));
+    assert!(lowering.contains("\"=r,r\""));
+    assert!(lowering.contains("inline_asm_convergent"));
+
+    let probe_record = movmatrix(&catalog).next().unwrap();
+    let probe = render_probe(&catalog, probe_record, "test-hash");
+    assert!(probe.contains("call i32 asm \"movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;\""));
+    assert!(probe.contains("attributes #0 = { convergent }"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/movmatrix.rs"
+    )));
+}
+
+#[test]
+fn register_mma_rendering_preserves_apis_order_convergence_and_variants() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(catalog.intrinsics.len(), 1016);
+    let records: Vec<_> = register_mmas(&catalog).collect();
+    assert_eq!(records.len(), 154);
+    let generated_records = records
+        .iter()
+        .copied()
+        .filter(|record| {
+            record.register_mma.as_ref().unwrap().compatibility_source
+                == RegisterMmaCompatibilitySource::GeneratedStub
+        })
+        .collect::<Vec<_>>();
+    let existing_records = records
+        .iter()
+        .copied()
+        .filter(|record| {
+            record.register_mma.as_ref().unwrap().compatibility_source
+                == RegisterMmaCompatibilitySource::ExistingStub
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(generated_records.len(), 149);
+    assert_eq!(existing_records.len(), 5);
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    for record in &records {
+        assert!(raw.contains(&format!("pub unsafe fn {}(", record.rust.abi_id)));
+    }
+    assert!(raw.contains("no lane may have exited"));
+    assert!(raw.contains("Signed accumulator overflow wraps"));
+    assert!(raw.contains("Signed accumulator overflow clamps"));
+
+    let compatibility = render_compat_register_mma(&catalog, "test-hash");
+    assert_eq!(compatibility.matches("pub unsafe fn ").count(), 149);
+    for record in generated_records {
+        let argument_names: &[&str] = if record.register_mma.as_ref().unwrap().adapter
+            == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
+        {
+            &[
+                "c",
+                "a",
+                "b",
+                "scale_a",
+                "byte_id_a",
+                "thread_id_a",
+                "scale_b",
+                "byte_id_b",
+                "thread_id_b",
+            ]
+        } else {
+            &["c", "a", "b"]
+        };
+        let arguments = argument_names
+            .iter()
+            .zip(&record.rust.arguments)
+            .map(|(name, ty)| format!("{name}: {ty}"))
+            .collect::<Vec<_>>()
+            .join(", ");
+        assert!(compatibility.contains(&format!(
+            "pub unsafe fn {}({arguments}) -> {} {{",
+            record.rust.name, record.rust.result
+        )));
+    }
+    for record in existing_records {
+        assert!(!compatibility.contains(&format!("pub unsafe fn {}(", record.rust.name)));
+    }
+
+    let dialect = render_dialect_register_mma(&catalog, "test-hash");
+    assert_eq!(dialect.matches("pub struct RegisterMmaOp").count(), 1);
+    assert!(dialect.contains("let recipe: (&[MmaCarrier], &[MmaCarrier])"));
+    assert!(dialect.contains("RegisterMmaShapeAttr::M8n8k4"));
+    assert!(dialect.contains("RegisterMmaShapeAttr::M8n8k16"));
+    assert!(dialect.contains("RegisterMmaShapeAttr::M8n8k32"));
+    assert!(dialect.contains("RegisterMmaShapeAttr::M8n8k128"));
+    assert!(dialect.contains("RegisterMmaShapeAttr::M16n8k4"));
+    assert!(dialect.contains("RegisterMmaShapeAttr::M16n8k32"));
+    assert!(dialect.contains("RegisterMmaShapeAttr::M16n8k64"));
+    assert!(dialect.contains("RegisterMmaShapeAttr::M16n8k128"));
+    assert!(dialect.contains("RegisterMmaShapeAttr::M16n8k256"));
+    assert!(dialect.contains("RegisterMmaOperationAttr::Multiply"));
+    assert!(dialect.contains("RegisterMmaOperationAttr::AndPopc"));
+    assert!(dialect.contains("RegisterMmaOperationAttr::XorPopc"));
+    assert!(dialect.contains("pub enum RegisterMmaKindAttr { Standard, F8f6f4, Mxf8f6f4 }"));
+    assert!(dialect.contains("kind_or_inferred"));
+    assert!(dialect.contains("RegisterMmaAccumulatorAttr::F16"));
+    assert!(dialect.contains("operation_or_multiply"));
+    assert!(dialect.contains("MmaCarrier::I32 | MmaCarrier::U16 | MmaCarrier::U32"));
+    assert!(dialect.contains("if matches!(carrier, MmaCarrier::U16)"));
+    assert!(dialect.contains("RegisterMmaElementAttr::B1"));
+    assert!(dialect.contains("RegisterMmaElementAttr::E2m1"));
+    assert!(dialect.contains("RegisterMmaElementAttr::E5m2"));
+    assert!(dialect.contains("RegisterMmaElementAttr::S4"));
+    assert!(dialect.contains("RegisterMmaElementAttr::U4"));
+    assert!(dialect.contains("RegisterMmaElementAttr::U8"));
+    assert!(dialect.contains("RegisterMmaOverflowAttr::Wrapping"));
+    assert!(dialect.contains("RegisterMmaOverflowAttr::Satfinite"));
+    assert!(dialect.contains(
+            "&[MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]"
+        ));
+    for (op_type, op_name) in [
+        ("MmaM16N8K16F32Bf16Op", "nvvm.mma_m16n8k16_f32_bf16"),
+        ("MmaM16N8K16F32F16Op", "nvvm.mma_m16n8k16_f32_f16"),
+        ("MmaM16N8K8F32Tf32Op", "nvvm.mma_m16n8k8_f32_tf32"),
+        ("MmaM16N8K32S32S8Op", "nvvm.mma_m16n8k32_s32_s8"),
+        ("MmaM8N8K4F64Op", "nvvm.mma_m8n8k4_f64"),
+    ] {
+        assert!(dialect.contains(&format!("pub struct {op_type};")));
+        assert!(dialect.contains(&format!("name = {op_name:?}")));
+        assert!(dialect.contains(&format!("{op_type}::register(ctx);")));
+    }
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("enum GeneratedMmaImportAdapter"));
+    assert!(importer.contains("C2U32A4U32B2U32ToD2U32"));
+    assert!(importer.contains("C2U32A2U32B1U32ToD2U32"));
+    assert!(importer.contains("C4F32A2U32B1U32ToD4F32"));
+    assert!(importer.contains("C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32"));
+    assert!(importer.contains("ctx, b_value, b_ty, b_count, block_ptr, last_after_b, loc.clone()"));
+    assert!(importer.contains("C4I32A2U32B1U32ToD4I32"));
+    assert!(importer.contains("C2I32A1U32B1U32ToD2I32"));
+    assert!(importer.contains("(i32_ty, 2, u32_ty, 1, false, u32_ty, 1, false, i32_ty, 2)"));
+    assert!(importer.contains("(i32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, i32_ty, 4)"));
+    assert!(importer.contains("(u32_ty, 2, u32_ty, 4, true, u32_ty, 2, true, u32_ty, 2)"));
+    assert!(importer.contains("import_generated_mma_operands"));
+    assert!(importer.contains("bundle_generated_mma_results"));
+    assert!(importer.contains("set_attr_nvvm_register_mma_operation"));
+    assert!(importer.contains("set_attr_nvvm_register_mma_kind"));
+    for record in &records {
+        assert!(importer.contains(&record.rust.canonical_path));
+        assert!(importer.contains(&record.rust.compatibility_paths[0]));
+        assert!(importer.contains(&format!(
+            "set_generated_intrinsic_marker(ctx, mma, {:?})",
+            intrinsic_marker(&catalog, record)
+        )));
+    }
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert_eq!(
+        lowering
+            .matches("impl MirToLlvmConversion for RegisterMmaOp")
+            .count(),
+        1
+    );
+    assert!(lowering.contains("convert_generated_register_mma"));
+    assert!(lowering.contains("operation_or_multiply"));
+    assert!(lowering.contains("kind_or_inferred"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e4m3.f16"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k4.row.col.f32.tf32.tf32.f32"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e5m2.f32"));
+    assert!(lowering.contains("=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r"));
+    assert!(lowering.contains("=d,=d,d,d,d,d"));
+    assert!(lowering.contains("=r,=r,=r,=r,r,r,r,r,r,r,r"));
+    assert!(lowering.contains("=r,=r,r,r,r,r"));
+    assert!(lowering.contains("=r,=r,r,r,r,r,r,r,r,r"));
+    assert!(lowering.contains("mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32"));
+    assert!(lowering.contains("mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc"));
+    assert!(lowering.contains("mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc"));
+    assert!(lowering.contains("mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc"));
+    for op_type in [
+        "MmaM16N8K16F32Bf16Op",
+        "MmaM16N8K16F32F16Op",
+        "MmaM16N8K8F32Tf32Op",
+        "MmaM16N8K32S32S8Op",
+        "MmaM8N8K4F64Op",
+    ] {
+        assert_eq!(
+            lowering
+                .matches(&format!("impl MirToLlvmConversion for {op_type}"))
+                .count(),
+            1
+        );
+    }
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::I32, 4, 7, "mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};", "=r,=r,=r,=r,r,r,r,r,r,r,r")"#
+        ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::I32, 4, 10, "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};", "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r")"#
+        ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::I32, 2, 4, "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc {$0, $1}, {$4}, {$5}, {$2, $3};", "=r,=r,r,r,r,r")"#
+        ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::I32, 4, 7, "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};", "=r,=r,=r,=r,r,r,r,r,r,r,r")"#
+        ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::I32, 4, 10, "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};", "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r")"#
+        ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::F32, 4, 10, "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r")"#
+        ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::F32, 4, 10, "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r")"#
+        ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::I32, 2, 8, "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};", "=r,=r,r,r,r,r,r,r,r,r")"#
+        ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::I32, 2, 8, "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};", "=r,=r,r,r,r,r,r,r,r,r")"#
+        ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::F32, 4, 16, "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h")"#
+        ));
+
+    let targets = render_targets(&catalog, "test-hash");
+    assert!(targets.contains("GeneratedIntrinsicVariant::RegisterMma"));
+    assert!(targets.contains("GeneratedRegisterMmaShape::M8n8k4"));
+    assert!(targets.contains("GeneratedRegisterMmaShape::M16n8k4"));
+    assert!(targets.contains(
+            "pub enum GeneratedRegisterMmaShape { M8n8k4, M8n8k16, M8n8k32, M8n8k128, M16n8k4, M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128, M16n8k256 }"
+        ));
+    assert!(targets.contains(
+            "GeneratedRegisterMmaShape::M8n8k16 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k16)"
+        ));
+    assert!(targets.contains(
+            "GeneratedRegisterMmaShape::M8n8k32 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k32)"
+        ));
+    assert!(targets.contains(
+            "GeneratedRegisterMmaShape::M8n8k128 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M8n8k128)"
+        ));
+    assert!(targets.contains("GeneratedRegisterMmaShape::M16n8k32"));
+    assert!(targets.contains(
+            "GeneratedRegisterMmaShape::M16n8k64 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k64)"
+        ));
+    assert!(targets.contains(
+            "GeneratedRegisterMmaShape::M16n8k128 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k128)"
+        ));
+    assert!(targets.contains(
+            "GeneratedRegisterMmaShape::M16n8k256 => op.get_attr_nvvm_register_mma_shape(ctx).as_deref() == Some(&RegisterMmaShapeAttr::M16n8k256)"
+        ));
+    assert!(targets.contains("GeneratedRegisterMmaOperation::Multiply"));
+    assert!(targets.contains("GeneratedRegisterMmaOperation::AndPopc"));
+    assert!(targets.contains("GeneratedRegisterMmaOperation::XorPopc"));
+    assert!(targets.contains("pub enum GeneratedRegisterMmaKind { Standard, F8f6f4, Mxf8f6f4 }"));
+    assert!(targets.contains("kind: GeneratedRegisterMmaKind::Standard"));
+    assert!(targets.contains("kind: GeneratedRegisterMmaKind::F8f6f4"));
+    assert!(targets.contains("kind: GeneratedRegisterMmaKind::Mxf8f6f4"));
+    assert!(targets.contains("kind_or_inferred"));
+    assert!(targets.contains("RegisterMmaKindAttr::Standard"));
+    assert!(targets.contains("RegisterMmaKindAttr::F8f6f4"));
+    assert!(targets.contains("RegisterMmaKindAttr::Mxf8f6f4"));
+    assert!(targets.contains("GeneratedRegisterMmaAccumulator::F16"));
+    assert!(targets.contains("operation: GeneratedRegisterMmaOperation::AndPopc"));
+    assert!(targets.contains("operation: GeneratedRegisterMmaOperation::XorPopc"));
+    assert!(targets.contains("operation: mma_operation"));
+    assert!(targets.contains("operation_or_multiply"));
+    assert!(targets.contains("GeneratedRegisterMmaElement::B1"));
+    assert!(targets.contains("GeneratedRegisterMmaElement::E2m1"));
+    assert!(targets.contains("GeneratedRegisterMmaElement::E5m2"));
+    assert!(targets.contains("GeneratedRegisterMmaElement::S4"));
+    assert!(targets.contains("GeneratedRegisterMmaElement::U4"));
+    assert!(targets.contains("GeneratedRegisterMmaElement::U8"));
+    assert!(targets.contains(
+        "a_element: GeneratedRegisterMmaElement::S4, b_element: GeneratedRegisterMmaElement::U4"
+    ));
+    assert!(targets.contains(
+        "a_element: GeneratedRegisterMmaElement::U4, b_element: GeneratedRegisterMmaElement::S4"
+    ));
+    assert!(targets.contains(
+        "a_element: GeneratedRegisterMmaElement::S8, b_element: GeneratedRegisterMmaElement::U8"
+    ));
+    assert!(targets.contains(
+        "a_element: GeneratedRegisterMmaElement::U8, b_element: GeneratedRegisterMmaElement::S8"
+    ));
+    assert!(targets.contains("overflow: GeneratedRegisterMmaOverflow::Satfinite"));
+    assert!(targets.contains("get_attr_nvvm_register_mma_overflow"));
+    assert!(targets.contains("minimum_ptx: GeneratedPtxVersion::from_encoded(87)"));
+    assert!(targets.contains("minimum_ptx: GeneratedPtxVersion::from_encoded(84)"));
+    assert!(targets.contains("GeneratedHardwareAlternative::ExactArchitecture(120)"));
+    assert!(targets.contains("GeneratedHardwareAlternative::FamilyTarget(121)"));
+
+    let first_dense = records
+        .iter()
+        .find(|record| record.id == "mma_m16n8k32_f32_e2m1_e2m1")
+        .unwrap();
+    let last_dense = records
+        .iter()
+        .find(|record| record.id == "mma_m16n8k32_f32_e5m2_e5m2")
+        .unwrap();
+    assert_eq!(first_dense.rust.abi_id, "i0454");
+    assert_eq!(last_dense.rust.abi_id, "i0478");
+    assert_eq!(
+        register_mma_constraints(first_dense),
+        "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r"
+    );
+    let first_dense_f16 = records
+        .iter()
+        .find(|record| record.id == "mma_m16n8k32_f16_e2m1_e2m1")
+        .unwrap();
+    let last_dense_f16 = records
+        .iter()
+        .find(|record| record.id == "mma_m16n8k32_f16_e5m2_e5m2")
+        .unwrap();
+    assert_eq!(first_dense_f16.rust.abi_id, "i0479");
+    assert_eq!(last_dense_f16.rust.abi_id, "i0503");
+    assert_eq!(
+        register_mma_constraints(first_dense_f16),
+        "=r,=r,r,r,r,r,r,r,r,r"
+    );
+    assert!(render_probe(&catalog, first_dense_f16, "test-hash").contains("define { i32, i32 }"));
+
+    let first_mxf8f6f4 = records
+        .iter()
+        .find(|record| record.id == "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1")
+        .unwrap();
+    let last_mxf8f6f4 = records
+        .iter()
+        .find(|record| record.id == "mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2")
+        .unwrap();
+    assert_eq!(first_mxf8f6f4.rust.abi_id, "i0858");
+    assert_eq!(last_mxf8f6f4.rust.abi_id, "i0882");
+    assert_eq!(
+        register_mma_constraints(first_mxf8f6f4),
+        "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h"
+    );
+    assert!(
+        render_probe(&catalog, first_mxf8f6f4, "test-hash").contains("kind::mxf8f6f4.block_scale")
+    );
+    let first_mxf8f6f4_compatibility = format!("pub unsafe fn {}(", first_mxf8f6f4.rust.name);
+    let first_mxf8f6f4_compatibility = compatibility
+        .find(&first_mxf8f6f4_compatibility)
+        .expect("generated MXF8F6F4 compatibility wrapper");
+    assert!(
+        compatibility[..first_mxf8f6f4_compatibility]
+            .ends_with("#[allow(clippy::too_many_arguments)]\n#[must_use]\n#[inline(never)]\n")
+    );
+
+    for record in &records {
+        let probe = render_probe(&catalog, record, "test-hash");
+        assert!(probe.contains("asm sideeffect"));
+        assert!(probe.contains("attributes #0 = { convergent }"));
+        assert!(probe.contains(&register_mma_template(record)));
+        assert!(probe.contains(&register_mma_constraints(record)));
+    }
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("## Register-MMA contracts"));
+    assert!(reference.contains("performs XOR, population count, and accumulate"));
+    assert!(reference.contains("performs AND, population count, and accumulate"));
+    assert!(reference.contains("runtime validation is not executed on a GPU"));
+    for record in &records {
+        assert!(reference.contains(&format!("- `{}`: runtime `unexecuted`", record.id)));
+    }
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/register_mma.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/register_mma.rs"
+    )));
+}
+
+#[test]
+fn register_mma_kind_is_explicit_and_legacy_ir_stays_compatible() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let mut catalog: CatalogFile = read_json(&repo_root.join("intrinsics/catalog.json")).unwrap();
+    let old = catalog
+        .intrinsics
+        .iter()
+        .find(|record| record.id == "mma_m16n8k32_f16_e4m3_e4m3")
+        .unwrap()
+        .clone();
+    assert_eq!(old.register_mma.as_ref().unwrap().kind, None);
+    assert_eq!(
+        register_mma_attr_variants(&old).2,
+        "RegisterMmaKindAttr::F8f6f4"
+    );
+    assert!(generated_intrinsic_variant(&old).contains("kind: GeneratedRegisterMmaKind::F8f6f4"));
+
+    let mut standard = old.clone();
+    standard.id = "mma_m16n8k32_fp8_f16_e4m3_e4m3".into();
+    standard.operation_key = "matrix.mma.m16n8k32.row.col.standard_fp8.f16.e4m3.e4m3.f16".into();
+    standard.rust.abi_id = "i9999".into();
+    standard.rust.name = standard.id.clone();
+    standard.rust.canonical_path = format!("cuda_intrinsics::matrix::{}", standard.id);
+    standard.rust.public_path = standard.rust.canonical_path.clone();
+    standard.rust.compatibility_paths = vec![format!("cuda_device::wmma::{}", standard.id)];
+    standard.llvm.as_mut().unwrap().symbol =
+        "llvm.nvvm.mma.m16n8k32.row.col.f16.e4m3.e4m3.f16".into();
+    standard.register_mma.as_mut().unwrap().kind = Some(RegisterMmaKind::Standard);
+    standard
+        .expected_ptx
+        .modifiers
+        .retain(|modifier| modifier != "kind::f8f6f4");
+    assert_eq!(
+        register_mma_attr_variants(&standard).2,
+        "RegisterMmaKindAttr::Standard"
+    );
+    assert!(
+        generated_intrinsic_variant(&standard).contains("kind: GeneratedRegisterMmaKind::Standard")
+    );
+    catalog.intrinsics.push(standard);
+
+    let dialect = render_dialect_register_mma(&catalog, "test-hash");
+    assert!(dialect.contains("pub fn kind_or_inferred"));
+    assert!(
+        dialect.contains("let old_f8f6f4 = self.get_attr_nvvm_register_mma_shape(ctx).as_deref()")
+    );
+    assert!(dialect.contains("== Some(&RegisterMmaShapeAttr::M16n8k32)"));
+    assert!(
+        dialect
+            .contains("&& low_format(self.get_attr_nvvm_register_mma_a_element(ctx).as_deref())")
+    );
+    assert!(
+        dialect
+            .contains("&& low_format(self.get_attr_nvvm_register_mma_b_element(ctx).as_deref())")
+    );
+    assert!(dialect.contains("RegisterMmaKindAttr::F8f6f4"));
+    assert!(dialect.contains("RegisterMmaKindAttr::Standard"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4)"));
+    assert!(
+        importer.contains("set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard)")
+    );
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("let kind = self.kind_or_inferred(ctx)"));
+    assert!(lowering.contains("kind::f8f6f4.f16.e4m3.e4m3.f16"));
+    assert!(lowering.contains("row.col.f16.e4m3.e4m3.f16"));
+
+    let targets = render_targets(&catalog, "test-hash");
+    assert!(targets.contains("kind: GeneratedRegisterMmaKind::F8f6f4"));
+    assert!(targets.contains("kind: GeneratedRegisterMmaKind::Standard"));
+    assert!(targets.contains(
+            "GeneratedRegisterMmaKind::Standard => op.kind_or_inferred(ctx) == RegisterMmaKindAttr::Standard"
+        ));
+    assert!(targets.contains(
+            "GeneratedRegisterMmaKind::F8f6f4 => op.kind_or_inferred(ctx) == RegisterMmaKindAttr::F8f6f4"
+        ));
+    assert!(targets.contains("kind_matches && accumulator_matches"));
+}
+
+#[test]
+fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    let records = sparse_mmas(&catalog).collect::<Vec<_>>();
+    let k32 = records
+        .iter()
+        .filter(|record| record.sparse_mma.as_ref().unwrap().shape == SparseMmaShape::M16n8k32)
+        .count();
+    let k64 = records
+        .iter()
+        .filter(|record| record.sparse_mma.as_ref().unwrap().shape == SparseMmaShape::M16n8k64)
+        .count();
+    let k128 = records
+        .iter()
+        .filter(|record| record.sparse_mma.as_ref().unwrap().shape == SparseMmaShape::M16n8k128)
+        .count();
+    assert_eq!((records.len(), k32, k64, k128), (114, 16, 82, 16));
+    let standard_k64 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_m16n8k64_s32_s8")
+        .unwrap();
+    assert_eq!(
+        standard_k64.sparse_mma.as_ref().unwrap().adapter,
+        SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32
+    );
+    assert_eq!(
+        standard_k64.sparse_mma.as_ref().unwrap().llvm_adapter,
+        crate::model::SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32
+    );
+    assert_eq!(
+        sparse_mma_template(standard_k64),
+        "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;"
+    );
+    assert_eq!(
+        sparse_mma_constraints(standard_k64),
+        "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n"
+    );
+    let standard_int4_k64 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_m16n8k64_s32_s4")
+        .unwrap();
+    assert_eq!(
+        sparse_mma_template(standard_int4_k64),
+        "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;"
+    );
+    assert_eq!(
+        sparse_mma_constraints(standard_int4_k64),
+        "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n"
+    );
+    let ordered_int4_k64 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k64_s32_s4")
+        .unwrap();
+    assert_eq!(
+        ordered_int4_k64.sparse_mma.as_ref().unwrap().adapter,
+        SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32
+    );
+    assert_eq!(
+        ordered_int4_k64.sparse_mma.as_ref().unwrap().llvm_adapter,
+        crate::model::SparseMmaLlvmAdapter::A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32
+    );
+    assert_eq!(
+        sparse_mma_template(ordered_int4_k64),
+        "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;"
+    );
+    assert_eq!(
+        sparse_mma_constraints(ordered_int4_k64),
+        "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n"
+    );
+    let ordered_int4_k128 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k128_s32_s4")
+        .unwrap();
+    assert_eq!(
+        ordered_int4_k128.sparse_mma.as_ref().unwrap().adapter,
+        SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32
+    );
+    assert_eq!(
+        ordered_int4_k128.sparse_mma.as_ref().unwrap().llvm_adapter,
+        crate::model::SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32
+    );
+    assert_eq!(
+        sparse_mma_template(ordered_int4_k128),
+        "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;"
+    );
+    assert_eq!(
+        sparse_mma_constraints(ordered_int4_k128),
+        "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n"
+    );
+    let standard_int4_k128 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_m16n8k128_s32_s4")
+        .unwrap();
+    assert_eq!(
+        sparse_mma_template(standard_int4_k128),
+        "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;"
+    );
+    assert_eq!(
+        sparse_mma_constraints(standard_int4_k128),
+        "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n"
+    );
+    let ordered_f8f6f4 = records
+        .iter()
+        .copied()
+        .find(|record| {
+            record.id == "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
+        })
+        .unwrap();
+    assert_eq!(
+        ordered_f8f6f4.sparse_mma.as_ref().unwrap().adapter,
+        SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32
+    );
+    assert_eq!(
+        sparse_mma_template(ordered_f8f6f4),
+        "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;"
+    );
+    assert_eq!(
+        sparse_mma_constraints(ordered_f8f6f4),
+        "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"
+    );
+    assert_eq!(
+            sparse_mma_carriers(ordered_f8f6f4),
+            (
+                "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]".into(),
+                "&[MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32, MmaCarrier::F32]".into(),
+            )
+        );
+    let ordered_f8f6f4_f16 = records
+        .iter()
+        .copied()
+        .find(|record| {
+            record.id == "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
+        })
+        .unwrap();
+    assert_eq!(
+        ordered_f8f6f4_f16.sparse_mma.as_ref().unwrap().adapter,
+        SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32
+    );
+    assert_eq!(sparse_mma_fragment_counts(ordered_f8f6f4_f16), (2, 4, 4, 2));
+    assert_eq!(
+        sparse_mma_template(ordered_f8f6f4_f16),
+        "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;"
+    );
+    assert_eq!(
+        sparse_mma_constraints(ordered_f8f6f4_f16),
+        "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n"
+    );
+    assert_eq!(
+            sparse_mma_carriers(ordered_f8f6f4_f16),
+            (
+                "&[MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32, MmaCarrier::U32]".into(),
+                "&[MmaCarrier::U32, MmaCarrier::U32]".into(),
+            )
+        );
+    assert_eq!(sparse_mma_selector_values(ordered_f8f6f4_f16), &[0]);
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("must be the compile-time constant `0` or `1`"));
+    assert!(raw.contains("must be the compile-time constant `0`"));
+    for record in &records {
+        let (c_count, a_count, b_count, d_count) = sparse_mma_fragment_counts(record);
+        let scalar = match record.sparse_mma.as_ref().unwrap().accumulator {
+            SparseMmaAccumulator::F16 => "u32",
+            SparseMmaAccumulator::F32 => "f32",
+            SparseMmaAccumulator::S32 => "i32",
+        };
+        assert!(raw.contains(&format!(
+                "pub unsafe fn {}(_arg0: [{scalar}; {c_count}], _arg1: [u32; {a_count}], _arg2: [u32; {b_count}], _arg3: u32, _arg4: u32) -> [{scalar}; {d_count}]",
+                record.rust.abi_id,
+            )));
+    }
+
+    let compatibility = render_compat_sparse_mma(&catalog, "test-hash");
+    assert_eq!(compatibility.matches("pub unsafe fn ").count(), 114);
+    assert!(
+        compatibility
+            .contains("c: [i32; 4], a: [u32; 2], b: [u32; 2], metadata: u32, selector: u32")
+    );
+    assert!(
+        compatibility
+            .contains("c: [i32; 4], a: [u32; 4], b: [u32; 4], metadata: u32, selector: u32")
+    );
+    assert!(
+        compatibility
+            .contains("c: [f32; 4], a: [u32; 4], b: [u32; 4], metadata: u32, selector: u32")
+    );
+    assert!(
+        compatibility
+            .contains("c: [u32; 2], a: [u32; 4], b: [u32; 4], metadata: u32, selector: u32")
+    );
+
+    let dialect = render_dialect_sparse_mma(&catalog, "test-hash");
+    assert_eq!(dialect.matches("pub struct SparseMmaOp").count(), 1);
+    assert!(dialect.contains("MmaCarrier::F32"));
+    assert!(dialect.contains("MmaCarrier::I32"));
+    assert!(dialect.contains("MmaCarrier::U32"));
+    assert!(dialect.contains("operands.len() != expected_operands"));
+    assert!(dialect.contains("SparseMmaShapeAttr { M16n8k32, M16n8k64, M16n8k128 }"));
+    assert!(dialect.contains("SparseMmaAccumulatorAttr { F16, F32, S32 }"));
+    assert!(dialect.contains("SparseMmaSelectorAttr { ImmediateZeroOrOne, ImmediateZero }"));
+    assert!(dialect.contains("SparseMmaElementAttr::E2m1"));
+    assert!(dialect.contains("SparseMmaElementAttr::E2m3"));
+    assert!(dialect.contains("SparseMmaElementAttr::E3m2"));
+    assert!(dialect.contains("SparseMmaElementAttr::E4m3"));
+    assert!(dialect.contains("SparseMmaElementAttr::E5m2"));
+    assert!(dialect.contains("SparseMmaElementAttr::S4"));
+    assert!(dialect.contains("SparseMmaElementAttr::U4"));
+    assert!(dialect.contains("SparseMmaElementAttr::S8"));
+    assert!(dialect.contains("SparseMmaElementAttr::U8"));
+    assert!(dialect.contains("SparseMmaOverflowAttr::Wrapping"));
+    assert!(dialect.contains("SparseMmaOverflowAttr::Satfinite"));
+    assert!(dialect.contains("SparseMmaOverflowAttr::NotApplicable"));
+    assert!(dialect.contains("SparseMmaMetadataAttr { Standard, Ordered }"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("sparse MMA selector must be the compile-time constant 0 or 1"));
+    assert!(importer.contains("sparse MMA selector must be the compile-time constant 0"));
+    assert!(importer.contains("GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32"));
+    assert!(importer.contains("GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32"));
+    assert!(importer.contains("GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32"));
+    assert!(importer.contains("GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32"));
+    assert!(importer.contains("(u32_ty, 2, u32_ty, 4, true, u32_ty, 4, true, u32_ty, 2)"));
+    assert!(importer.contains("let (c_array, last_op) = rvalue::translate_operand("));
+    assert!(importer.contains("ctx, body, &args[0], value_map"));
+    assert!(importer.contains("let (a_value, last_after_a) = rvalue::translate_operand("));
+    assert!(importer.contains("ctx, body, &args[1], value_map"));
+    assert!(importer.contains("let (b_value, last_after_b) = rvalue::translate_operand("));
+    assert!(importer.contains("ctx, body, &args[2], value_map"));
+    assert!(importer.contains("operands.push(metadata)"));
+    assert!(importer.contains("operands.push(selector_value)"));
+    assert!(importer.contains("SparseMmaOp::get_concrete_op_info"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert_eq!(
+        lowering
+            .matches("impl MirToLlvmConversion for SparseMmaOp")
+            .count(),
+        1
+    );
+    assert!(lowering.contains("convert_generated_sparse_mma"));
+    for record in &records {
+        assert!(lowering.contains(&sparse_mma_template(record)));
+        assert!(lowering.contains(&sparse_mma_constraints(record)));
+    }
+
+    let targets = render_targets(&catalog, "test-hash");
+    assert!(targets.contains("GeneratedIntrinsicVariant::SparseMma"));
+    assert!(targets.contains("Operation::get_op::<SparseMmaOp>"));
+    assert!(targets.contains("get_attr_nvvm_sparse_mma_selector"));
+    assert!(targets.contains("GeneratedSparseMmaSelector::ImmediateZeroOrOne"));
+    assert!(targets.contains("GeneratedSparseMmaSelector::ImmediateZero"));
+    assert!(targets.contains("GeneratedSparseMmaShape::M16n8k64"));
+    assert!(targets.contains("SparseMmaShapeAttr::M16n8k64"));
+    assert!(targets.contains("GeneratedSparseMmaShape::M16n8k128"));
+    assert!(targets.contains("SparseMmaShapeAttr::M16n8k128"));
+    assert!(targets.contains("GeneratedSparseMmaElement::S4"));
+    assert!(targets.contains("GeneratedSparseMmaElement::U4"));
+    assert!(targets.contains("GeneratedSparseMmaElement::E2m1"));
+    assert!(targets.contains("GeneratedSparseMmaElement::E5m2"));
+    assert!(targets.contains("SparseMmaElementAttr::S4"));
+    assert!(targets.contains("SparseMmaElementAttr::U4"));
+    assert!(targets.contains("GeneratedSparseMmaMetadata::Standard"));
+    assert!(targets.contains("SparseMmaMetadataAttr::Standard"));
+    assert!(targets.contains("GeneratedSparseMmaMetadata::Ordered"));
+    assert!(targets.contains("SparseMmaMetadataAttr::Ordered"));
+    assert!(targets.contains("GeneratedSparseMmaAccumulator::F16"));
+    assert!(targets.contains("GeneratedSparseMmaAccumulator::F32"));
+    assert!(targets.contains("GeneratedSparseMmaOverflow::NotApplicable"));
+    assert!(targets.contains("GeneratedHardwareAlternative::ExactArchitecture(120)"));
+
+    assert_eq!(raw.matches(SPARSE_MMA_STANDARD_METADATA_RULE).count(), 32);
+    assert_eq!(raw.matches(SPARSE_MMA_ORDERED_METADATA_RULE).count(), 82);
+    assert_eq!(
+        compatibility
+            .matches(SPARSE_MMA_STANDARD_METADATA_RULE)
+            .count(),
+        32
+    );
+    assert_eq!(
+        compatibility
+            .matches(SPARSE_MMA_ORDERED_METADATA_RULE)
+            .count(),
+        82
+    );
+    assert!(
+        lowering.contains("mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32")
+    );
+    assert!(
+        lowering.contains("mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32")
+    );
+    assert!(
+        lowering.contains("mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32")
+    );
+    assert!(
+        lowering.contains("mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32")
+    );
+    assert!(lowering.contains("mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32"));
+    assert!(lowering.contains("mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32"));
+    assert!(lowering.contains("mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32"));
+    assert!(lowering.contains(
+        "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32"
+    ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::F32, 4, 14, "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n")"#
+        ));
+    assert!(lowering.contains(
+            r#"(GeneratedMmaResultType::I32, 2, 12, "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;", "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n")"#
+        ));
+    let f16_probe = render_probe(&catalog, ordered_f8f6f4_f16, "test-hash");
+    assert!(f16_probe.contains(
+            "define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16_selector_0"
+        ));
+    assert!(!f16_probe.contains("_selector_1"));
+
+    for record in &records {
+        let probe = render_probe(&catalog, record, "test-hash");
+        assert!(probe.contains(&format!("probe_{}_selector_0", record.id)));
+        let selectors = sparse_mma_selector_values(record);
+        assert_eq!(
+            probe.contains(&format!("probe_{}_selector_1", record.id)),
+            selectors.contains(&1)
+        );
+        assert_eq!(probe.matches("asm sideeffect").count(), selectors.len());
+        assert!(probe.contains(&sparse_mma_template(record)));
+        assert!(probe.contains(&sparse_mma_constraints(record)));
+        assert!(probe.contains("attributes #0 = { convergent }"));
+    }
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("## Sparse-MMA contracts"));
+    assert!(reference.contains("C, A, B, metadata, selector order"));
+    assert!(reference.contains("LLVM source record uses A, B, C, metadata, selector order"));
+    assert_eq!(
+        reference.matches(SPARSE_MMA_STANDARD_METADATA_RULE).count(),
+        32
+    );
+    assert_eq!(
+        reference.matches(SPARSE_MMA_ORDERED_METADATA_RULE).count(),
+        82
+    );
+    let sparse_reference = reference
+        .split("## Sparse-MMA contracts")
+        .nth(1)
+        .unwrap()
+        .split("## Packed-atomic contracts")
+        .next()
+        .unwrap();
+    assert!(sparse_reference.contains("Overflow mode is not applicable."));
+    assert!(!sparse_reference.contains("Integer overflow is not applicable"));
+    for record in &records {
+        assert!(reference.contains(&format!("- `{}`: runtime `unexecuted`", record.id)));
+    }
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/sparse_mma.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/sparse_mma.rs"
+    )));
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/tests/mod.rs b/crates/cuda-intrinsics-gen/src/render/tests/mod.rs
new file mode 100644
index 0000000000..729db95fa8
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/tests/mod.rs
@@ -0,0 +1,241 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::*;
+use crate::model::ImportedSelectionConstraints;
+use crate::ptx::{InstructionPattern, OperandPattern};
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogHardwareAlternative, CatalogHardwareTarget, CatalogSelection,
+    WgmmaControlAdapter, WgmmaControlMode, WgmmaControlParticipation,
+};
+use std::path::Path;
+
+mod mma;
+mod scalar_misc;
+mod tensor;
+mod warp_memory;
+
+fn catalog_with_debug_controls() -> CatalogFile {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    assert_eq!(debug_controls(&catalog).count(), 3);
+    catalog
+}
+
+fn catalog_with_stmatrix() -> CatalogFile {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    assert_eq!(stmatrices(&catalog).count(), 4);
+    catalog
+}
+
+fn catalog_with_clc() -> CatalogFile {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::test_catalog_with_clc(&repo_root).unwrap();
+    assert_eq!(clc_intrinsics(&catalog).count(), 6);
+    catalog
+}
+
+fn catalog_with_tma() -> CatalogFile {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::test_catalog_with_tma(&repo_root).unwrap();
+    assert_eq!(tma_intrinsics(&catalog).count(), 111);
+    catalog
+}
+
+fn catalog_with_wgmma_controls() -> CatalogFile {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let mut catalog = crate::resolve::resolve(&repo_root).unwrap();
+    if wgmma_controls(&catalog).count() == 3 {
+        return catalog;
+    }
+    let template = catalog
+        .intrinsics
+        .iter()
+        .find(|record| record.cluster_barrier.is_some())
+        .expect("cluster-barrier template")
+        .clone();
+
+    let recipes = [
+        (
+            WgmmaControlMode::Fence,
+            "i0317",
+            "wgmma_fence",
+            "WgmmaFenceSyncAlignedOp",
+            "nvvm.wgmma_fence_sync_aligned",
+            "llvm.nvvm.wgmma.fence.sync.aligned",
+            "WGMMA_FENCE_SYNC_ALIGNED",
+            "fence.sync.aligned",
+            WgmmaControlAdapter::NoArguments,
+            "cuda_device::wgmma::wgmma_fence",
+        ),
+        (
+            WgmmaControlMode::CommitGroup,
+            "i0318",
+            "wgmma_commit_group",
+            "WgmmaCommitGroupSyncAlignedOp",
+            "nvvm.wgmma_commit_group_sync_aligned",
+            "llvm.nvvm.wgmma.commit_group.sync.aligned",
+            "WGMMA_COMMIT_GROUP_SYNC_ALIGNED",
+            "commit_group.sync.aligned",
+            WgmmaControlAdapter::NoArguments,
+            "cuda_device::wgmma::wgmma_commit_group",
+        ),
+        (
+            WgmmaControlMode::WaitGroup,
+            "i0319",
+            "wgmma_wait_group",
+            "WgmmaWaitGroupSyncAlignedOp",
+            "nvvm.wgmma_wait_group_sync_aligned",
+            "llvm.nvvm.wgmma.wait_group.sync.aligned",
+            "WGMMA_WAIT_GROUP_SYNC_ALIGNED",
+            "wait_group.sync.aligned",
+            WgmmaControlAdapter::ConstGenericU32ToI64Immediate,
+            "cuda_device::wgmma::__wgmma_wait_group",
+        ),
+    ];
+
+    for (
+        mode,
+        abi_id,
+        id,
+        op_type,
+        op_name,
+        llvm_symbol,
+        selection_record,
+        suffix,
+        adapter,
+        compatibility_path,
+    ) in recipes
+    {
+        let wait = mode == WgmmaControlMode::WaitGroup;
+        let mut record = template.clone();
+        record.id = id.into();
+        record.operation_key = format!("wgmma.control.{suffix}");
+        record.family = "wgmma_control".into();
+        record.source = crate::model::IntrinsicSource::LlvmImported {
+            source_record: format!("int_nvvm_wgmma_{}", suffix.replace('.', "_")),
+        };
+        record.selections = vec![CatalogSelection {
+            source_record: selection_record.into(),
+            asm: format!("wgmma.{suffix};"),
+            predicates: vec!["Subtarget->getPTXVersion() >= 80".into(), "hasSM90a".into()],
+            constraints: ImportedSelectionConstraints::default(),
+        }];
+        record.rust.abi_id = abi_id.into();
+        record.rust.module = "wgmma".into();
+        record.rust.name = id.into();
+        record.rust.arguments = if wait { vec!["u64".into()] } else { vec![] };
+        record.rust.result = "()".into();
+        record.rust.safe = false;
+        record.rust.must_use = false;
+        record.rust.safe_allowlist_reason = None;
+        record.rust.canonical_path =
+            format!("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::{abi_id}");
+        record.rust.public_path = format!("cuda_intrinsics::wgmma::{id}");
+        record.rust.compatibility_paths = vec![compatibility_path.into()];
+        record.dialect.op_type = op_type.into();
+        record.dialect.op_name = op_name.into();
+        record.dialect.operands = if wait { vec!["i64".into()] } else { vec![] };
+        record.dialect.results.clear();
+        let llvm = record.llvm.as_mut().unwrap();
+        llvm.symbol = llvm_symbol.into();
+        llvm.resolved_symbol = None;
+        llvm.arguments = if wait { vec!["i64".into()] } else { vec![] };
+        llvm.results.clear();
+        llvm.properties = if wait {
+            vec!["ImmArg<arg0>".into(), "IntrConvergent".into()]
+        } else {
+            vec!["IntrConvergent".into()]
+        };
+        record.semantics.pure = false;
+        record.semantics.memory = "read_write".into();
+        record.semantics.convergent = true;
+        record.semantics.execution_scope = "warpgroup".into();
+        record.target.minimum_ptx = "8.0".parse().unwrap();
+        record.target.hardware = CatalogHardwareTarget::AnyOf {
+            alternatives: vec![CatalogHardwareAlternative::ExactArchitecture { sm: 90 }],
+        };
+        record.target.ptx_result = "()".into();
+        record.target.targets = "sm_90a".into();
+        record.target.ptx_isa_version = "9.3".into();
+        record.target.ptx_isa_section = "WGMMA control".into();
+        record.target.ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#asynchronous-warpgroup-level-matrix-instructions".into();
+        for lowering in &mut record.backend_lowerings {
+            lowering.target.minimum_ptx = "8.0".parse().unwrap();
+            lowering.target.hardware = record.target.hardware.clone();
+            lowering.mechanism = match lowering.backend {
+                IntrinsicBackend::LlvmNvptx => BackendLoweringMechanism::TypedNvvm,
+                IntrinsicBackend::LibNvvm => BackendLoweringMechanism::InlinePtx,
+            };
+        }
+        record.packed_atomic = None;
+        record.redux = None;
+        record.vote = None;
+        record.active_mask = None;
+        record.warp_match = None;
+        record.warp_barrier = None;
+        record.warp_shuffle = None;
+        record.dot_product = None;
+        record.packed_alu = None;
+        record.packed_conversion = None;
+        record.cp_async_copy = None;
+        record.cp_async_control = None;
+        record.cp_async_mbarrier = None;
+        record.mbarrier_basic = None;
+        record.register_mma = None;
+        record.sparse_mma = None;
+        record.prmt = None;
+        record.cluster_barrier = None;
+        record.wgmma_control = Some(crate::model::WgmmaControl {
+            mode,
+            adapter,
+            participation: WgmmaControlParticipation::WarpgroupAllThreadsSameInstruction,
+        });
+        record.special_register = None;
+        record.ldmatrix = None;
+        record.lowering = "generated_wgmma_control".into();
+        record.expected_ptx = InstructionPattern {
+            mnemonic: "wgmma".into(),
+            modifiers: suffix.split('.').map(str::to_owned).collect(),
+            operands: if wait {
+                vec![OperandPattern::Immediate]
+            } else {
+                vec![]
+            },
+        };
+        record.summary = format!("Generated {id} test record.");
+        catalog.intrinsics.push(record);
+    }
+    catalog
+}
+
+fn raw_abi_item<'a>(raw: &'a str, id: &str) -> &'a str {
+    let marker = format!("Catalog ID: `{id}`");
+    let marker_offset = raw.find(&marker).unwrap();
+    let start = raw[..marker_offset]
+        .rfind("\n\n")
+        .map_or(0, |offset| offset + 2);
+    let end = raw[marker_offset..]
+        .find("\n}\n")
+        .map_or(raw.len(), |offset| marker_offset + offset + 3);
+    &raw[start..end]
+}
+
+fn raw_abi_safety_block<'a>(raw: &'a str, id: &str) -> &'a str {
+    let item = raw_abi_item(raw, id);
+    let marker = "/// # Safety\n";
+    let start = item.find(marker).unwrap() + marker.len();
+    let end = item[start..].find("#[").unwrap() + start;
+    &item[start..end]
+}
+
+fn catalog_with_tcgen05() -> CatalogFile {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::test_catalog_with_tcgen05(&repo_root).unwrap();
+    assert_eq!(tcgen05_intrinsics(&catalog).count(), 233);
+    catalog
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/tests/scalar_misc.rs b/crates/cuda-intrinsics-gen/src/render/tests/scalar_misc.rs
new file mode 100644
index 0000000000..75e1e47783
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/tests/scalar_misc.rs
@@ -0,0 +1,1098 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::*;
+use crate::model::ImportedSelectionConstraints;
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogSelection, ClcAdapter, DebugControlAdapter,
+    ExtendedMinMaxAdapter, ImportedAddressSpace, PackedConversionSourceFormat, RuntimeValidation,
+    ScalarArithmeticOperation,
+};
+use crate::render::collector_targets::generated_selection_alternatives;
+use crate::render::common::llvm;
+use crate::render::compat::render_compat_float;
+use crate::render::families::{
+    dot_products, packed_alu_register_constraint, packed_alus, packed_conversion_constraint,
+    packed_conversion_ptx_mnemonic, packed_conversion_source, packed_conversion_source_width,
+    packed_conversion_typed_llvm_name, packed_conversions, prmts, scalar_conversion_ptx_mnemonic,
+    scalar_conversion_rounding_attr, scalar_conversion_saturation_attr,
+};
+use std::collections::BTreeSet;
+use std::path::Path;
+
+#[test]
+fn unsafe_safety_docs_never_reference_missing_addr() {
+    let catalog = catalog_with_clc();
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    let offenders = catalog
+        .intrinsics
+        .iter()
+        .filter(|record| !record.rust.safe)
+        .filter(|record| raw_abi_item(&raw, &record.id).contains("/// `addr`"))
+        .filter(|record| {
+            !record
+                .rust
+                .arguments
+                .iter()
+                .any(|argument| argument.starts_with('*'))
+        })
+        .map(|record| record.id.as_str())
+        .collect::<Vec<_>>();
+    assert!(
+        offenders.is_empty(),
+        "unsafe safety docs reference `addr` without a pointer argument: {}",
+        offenders.join(", ")
+    );
+}
+
+#[test]
+fn unsafe_safety_blocks_are_exclusive_to_one_family() {
+    let catalog = catalog_with_clc();
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    let mut families_by_block = BTreeMap::<&str, BTreeSet<&str>>::new();
+    for record in catalog.intrinsics.iter().filter(|record| !record.rust.safe) {
+        families_by_block
+            .entry(raw_abi_safety_block(&raw, &record.id))
+            .or_default()
+            .insert(&record.family);
+    }
+    let collisions = families_by_block
+        .values()
+        .filter(|families| families.len() != 1)
+        .collect::<Vec<_>>();
+    assert!(
+        collisions.is_empty(),
+        "unsafe safety blocks shared across families: {collisions:?}; render a legitimate shared contract through a shared arm"
+    );
+}
+
+#[test]
+fn selection_alternatives_keep_predicates_and_constraints_grouped() {
+    let selections = vec![
+        CatalogSelection {
+            source_record: "SELECT_A".into(),
+            asm: "op.a $dst;".into(),
+            predicates: vec!["HasA".into(), "HasCommon".into()],
+            constraints: ImportedSelectionConstraints {
+                address_space: Some(ImportedAddressSpace::Generic),
+                immediate_bindings: vec![],
+            },
+        },
+        CatalogSelection {
+            source_record: "SELECT_B".into(),
+            asm: "op.b $dst;".into(),
+            predicates: vec!["HasB".into()],
+            constraints: ImportedSelectionConstraints {
+                address_space: Some(ImportedAddressSpace::Shared),
+                immediate_bindings: vec![],
+            },
+        },
+    ];
+
+    let rendered = generated_selection_alternatives(&selections);
+    assert_eq!(rendered.matches("GeneratedSelectionAlternative").count(), 2);
+    assert!(rendered.contains(
+            "source_record: \"SELECT_A\", asm: \"op.a $dst;\", predicates: &[\"HasA\", \"HasCommon\"], constraints: GeneratedSelectionConstraints { address_space: Some(GeneratedSelectionAddressSpace::Generic), immediate_bindings: &[] }"
+        ));
+    assert!(rendered.contains(
+            "source_record: \"SELECT_B\", asm: \"op.b $dst;\", predicates: &[\"HasB\"], constraints: GeneratedSelectionConstraints { address_space: Some(GeneratedSelectionAddressSpace::Shared), immediate_bindings: &[] }"
+        ));
+}
+
+#[test]
+fn packed_alu_and_conversion_render_exact_pure_inline_ptx_adapters() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(packed_alus(&catalog).count(), 30);
+    assert_eq!(packed_conversions(&catalog).count(), 18);
+
+    let dialect = render_dialect_packed_alu(&catalog, "test-hash");
+    for op in [
+        "FmaBf16x2Op",
+        "FmaReluBf16x2Op",
+        "AddBf16x2Op",
+        "SubBf16x2Op",
+        "MulBf16x2Op",
+        "MinBf16x2Op",
+        "MaxBf16x2Op",
+        "NegBf16x2Op",
+        "AbsBf16x2Op",
+        "FmaF16x2Op",
+        "FmaReluF16x2Op",
+        "AddF16x2Op",
+        "SubF16x2Op",
+        "MulF16x2Op",
+        "MinF16x2Op",
+        "MaxF16x2Op",
+        "NegF16x2Op",
+        "AbsF16x2Op",
+        "AddF32x2Op",
+        "AddFtzF32x2Op",
+        "SubF32x2Op",
+        "SubFtzF32x2Op",
+        "MulF32x2Op",
+        "MulFtzF32x2Op",
+        "FmaF32x2Op",
+        "FmaFtzF32x2Op",
+    ] {
+        assert!(dialect.contains(&format!("pub struct {op}")));
+        assert!(dialect.contains(&format!("{op}::register(ctx)")));
+    }
+    let conversion_dialect = render_dialect_packed_conversion(&catalog, "test-hash");
+    for op in [
+        "CvtF32x2Bf16x2Op",
+        "CvtF16x2F32Op",
+        "CvtRzF16x2F32Op",
+        "CvtRnReluF16x2F32Op",
+        "CvtRnReluBf16x2F32Op",
+        "CvtRzBf16x2F32Op",
+        "CvtRnSatfiniteE4m3x2F32Op",
+        "CvtRnSatfiniteReluE4m3x2F32Op",
+        "CvtRnSatfiniteE5m2x2F32Op",
+        "CvtRnSatfiniteReluE5m2x2F32Op",
+    ] {
+        assert!(conversion_dialect.contains(&format!("pub struct {op}")));
+        assert!(conversion_dialect.contains(&format!("{op}::register(ctx)")));
+    }
+    assert!(conversion_dialect.contains("low f16 lane"));
+    assert!(conversion_dialect.contains("low bf16 lane"));
+    assert!(conversion_dialect.contains("low e4m3 lane"));
+    assert!(conversion_dialect.contains("low e5m2 lane"));
+    assert!(conversion_dialect.contains("vec![low, high]"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::bf16x2::fma_bf16x2"));
+    assert!(importer.contains("cuda_device::f16x2::fma_f16x2"));
+    assert!(importer.contains("cuda_device::convert::cvt_bf16x2_f32"));
+    assert!(importer.contains("cuda_device::convert::cvt_f16x2_f32"));
+    assert!(importer.contains("cuda_device::convert::cvt_rz_bf16x2_f32"));
+    assert!(importer.contains("cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32"));
+    assert!(importer.contains("cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32"));
+    assert!(importer.contains("FmaBf16x2Op::build(ctx, arg0, arg1, arg2)"));
+    assert!(importer.contains("CvtF32x2Bf16x2Op::build(ctx, arg0, arg1)"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    for mnemonic in [
+        "fma.rn.bf16x2",
+        "fma.rn.relu.bf16x2",
+        "add.rn.bf16x2",
+        "sub.rn.bf16x2",
+        "mul.rn.bf16x2",
+        "min.bf16x2",
+        "max.bf16x2",
+        "neg.bf16x2",
+        "abs.bf16x2",
+        "fma.rn.f16x2",
+        "fma.rn.relu.f16x2",
+        "add.rn.f16x2",
+        "sub.rn.f16x2",
+        "mul.rn.f16x2",
+        "min.f16x2",
+        "max.f16x2",
+        "neg.f16x2",
+        "abs.f16x2",
+    ] {
+        assert!(lowering.contains(&format!(
+            "convert_generated_packed_alu(ctx, rewriter, self.get_operation(), \"{mnemonic}\", 32)"
+        )));
+    }
+    for mnemonic in [
+        "add.rn.f32x2",
+        "add.rn.ftz.f32x2",
+        "sub.rn.f32x2",
+        "sub.rn.ftz.f32x2",
+        "mul.rn.f32x2",
+        "mul.rn.ftz.f32x2",
+        "fma.rn.f32x2",
+        "fma.rn.ftz.f32x2",
+    ] {
+        assert!(lowering.contains(&format!(
+            "convert_generated_packed_alu(ctx, rewriter, self.get_operation(), \"{mnemonic}\", 64)"
+        )));
+    }
+    for mnemonic in [
+        "cvt.rn.bf16x2.f32",
+        "cvt.rn.f16x2.f32",
+        "cvt.rz.f16x2.f32",
+        "cvt.rn.relu.f16x2.f32",
+        "cvt.rn.relu.bf16x2.f32",
+        "cvt.rz.bf16x2.f32",
+    ] {
+        assert!(lowering.contains(&format!(
+                "convert_generated_packed_f32x2(ctx, rewriter, self.get_operation(), None, \"{mnemonic}\", 32)"
+            )));
+    }
+    for (intrinsic, mnemonic) in [
+        ("llvm_nvvm_ff_to_e4m3x2_rn", "cvt.rn.satfinite.e4m3x2.f32"),
+        (
+            "llvm_nvvm_ff_to_e4m3x2_rn_relu",
+            "cvt.rn.satfinite.relu.e4m3x2.f32",
+        ),
+        ("llvm_nvvm_ff_to_e5m2x2_rn", "cvt.rn.satfinite.e5m2x2.f32"),
+        (
+            "llvm_nvvm_ff_to_e5m2x2_rn_relu",
+            "cvt.rn.satfinite.relu.e5m2x2.f32",
+        ),
+    ] {
+        assert!(lowering.contains(&format!(
+                "convert_generated_packed_f32x2(ctx, rewriter, self.get_operation(), Some(\"{intrinsic}\"), \"{mnemonic}\", 16)"
+            )));
+    }
+
+    for record in packed_alus(&catalog) {
+        let probe = render_probe(&catalog, record, "test-hash");
+        let register = packed_alu_register_constraint(record);
+        let constraints = std::iter::once(format!("={register}"))
+            .chain(std::iter::repeat_n(
+                register.to_owned(),
+                record.rust.arguments.len(),
+            ))
+            .collect::<Vec<_>>()
+            .join(",");
+        assert!(probe.contains(&format!("\", \"{constraints}\"")));
+        assert!(!probe.contains("asm sideeffect"));
+        assert!(!probe.contains("~{memory}"));
+    }
+    let mut typed_probe_count = 0;
+    for conversion in packed_conversions(&catalog) {
+        let probe = render_probe(&catalog, conversion, "test-hash");
+        if packed_conversion_typed_llvm_name(conversion).is_some() {
+            typed_probe_count += 1;
+            let llvm = llvm(conversion);
+            let symbol = llvm.resolved_symbol.as_deref().unwrap_or(&llvm.symbol);
+            assert!(probe.contains(&format!("declare i16 @{symbol}(float, float)")));
+            assert!(probe.contains(&format!("call i16 @{symbol}(float %high, float %low)")));
+            assert!(!probe.contains(" asm "));
+        } else if packed_conversion_source(conversion) == PackedConversionSourceFormat::F32x2 {
+            assert!(probe.contains(&format!(
+                "asm \"{} $0, $2, $1;\", \"{}\"(float %low, float %high)",
+                packed_conversion_ptx_mnemonic(conversion),
+                packed_conversion_constraint(conversion),
+            )));
+            assert!(!probe.contains("declare "));
+        } else {
+            // One packed source operand, so no high/low reordering.
+            let source_ty = format!("i{}", packed_conversion_source_width(conversion));
+            assert!(probe.contains(&format!(
+                "asm \"{} $0, $1;\", \"{}\"({source_ty} %packed)",
+                packed_conversion_ptx_mnemonic(conversion),
+                packed_conversion_constraint(conversion),
+            )));
+            assert!(!probe.contains("declare "));
+        }
+        assert!(!probe.contains("asm sideeffect"));
+    }
+    assert_eq!(typed_probe_count, 4);
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("pub fn i0062(_arg0: u32, _arg1: u32, _arg2: u32) -> u32"));
+    assert!(raw.contains("pub fn i0071(_arg0: f32, _arg1: f32) -> u32"));
+    assert!(raw.contains("pub fn i0072(_arg0: u32, _arg1: u32, _arg2: u32) -> u32"));
+    assert!(raw.contains("pub fn i0085(_arg0: f32, _arg1: f32) -> u32"));
+    assert!(raw.contains("pub fn i0259(_arg0: f32, _arg1: f32) -> u16"));
+    assert!(raw.contains("pub fn i0262(_arg0: f32, _arg1: f32) -> u16"));
+    assert!(raw.contains("pub fn i0995(_arg0: u64, _arg1: u64) -> u64"));
+    assert!(raw.contains("pub fn i1002(_arg0: u64, _arg1: u64, _arg2: u64) -> u64"));
+    assert!(!raw.contains("#[must_use]\n#[inline(never)]\npub fn i0062"));
+    let f16_raw = raw.find("pub fn i0072").unwrap();
+    assert!(raw[..f16_raw].ends_with("#[must_use]\n#[inline(never)]\n"));
+
+    let compatibility = render_compat_packed_alu(&catalog, "test-hash", PackedAluFormat::Bf16x2);
+    assert!(compatibility.contains("pub fn fma_bf16x2(arg0: u32, arg1: u32, arg2: u32)"));
+    assert!(!compatibility.contains("fma_f16x2"));
+    assert!(compatibility.contains("let _ = arg0;"));
+    assert!(!compatibility.contains("let _ = (arg0);"));
+    let compatibility = render_compat_packed_alu(&catalog, "test-hash", PackedAluFormat::F16x2);
+    let f16_compat = compatibility.find("pub fn fma_f16x2").unwrap();
+    assert!(compatibility[..f16_compat].ends_with("#[must_use]\n#[inline(never)]\n"));
+    assert!(!compatibility.contains("fma_bf16x2"));
+    let compatibility = render_compat_packed_alu(&catalog, "test-hash", PackedAluFormat::F32x2);
+    assert!(compatibility.contains("pub fn add_f32x2(arg0: u64, arg1: u64) -> u64"));
+    assert!(compatibility.contains("pub fn fma_ftz_f32x2(arg0: u64, arg1: u64, arg2: u64) -> u64"));
+    assert!(!compatibility.contains("fma_f16x2"));
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("`fma_f16x2` carries one packed `f16x2` value in a `u32`"));
+    assert!(reference.contains(
+        "native instruction starts at PTX 4.2 / `sm_53`; cuda-oxide admits it from sm_70+"
+    ));
+    assert!(reference.contains("LLVM-NVPTX PTX 6.0 on sm_70+"));
+    assert!(reference.contains("libNVVM PTX 4.2 on sm_75+"));
+    assert!(reference.contains(
+            "`cvt_rn_relu_f16x2_f32` converts two `f32` inputs to packed `f16x2` using nearest-even rounding with ReLU"
+        ));
+    assert!(reference.contains("pure `cvt.rz.bf16x2.f32` inline PTX"));
+    assert!(reference.contains(
+            "LLVM-NVPTX uses typed `llvm.nvvm.ff.to.e4m3x2.rn` with `[high, low]` inputs; libNVVM uses pure `cvt.rn.satfinite.e4m3x2.f32` inline PTX"
+        ));
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/bf16x2.rs")));
+    assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/f16x2.rs")));
+    assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/f32x2.rs")));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/convert.rs"
+    )));
+    let compatibility = render_compat_packed_conversion(
+        &catalog,
+        "test-hash",
+        "cuda_device::convert::",
+        "convert",
+        ("lo", "hi"),
+    );
+    assert!(compatibility.contains("pub fn cvt_bf16x2_f32(lo: f32, hi: f32) -> u32"));
+    assert!(compatibility.contains("pub fn cvt_f16x2_f32(lo: f32, hi: f32) -> u32"));
+    assert!(compatibility.contains("pub fn cvt_rz_bf16x2_f32(lo: f32, hi: f32) -> u32"));
+    assert!(compatibility.contains("pub fn cvt_rn_satfinite_e4m3x2_f32(lo: f32, hi: f32) -> u16"));
+    assert!(
+        compatibility.contains("pub fn cvt_rn_satfinite_relu_e5m2x2_f32(lo: f32, hi: f32) -> u16")
+    );
+    assert!(!compatibility.contains("pub fn cvt_f32x2_bf16x2("));
+    assert!(!outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/tcgen05_conversion.rs"
+    )));
+}
+
+#[test]
+fn scalar_tf32_conversions_render_one_exact_attribute_carrier() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    let records = scalar_conversions(&catalog).collect::<Vec<_>>();
+    assert_eq!(records.len(), 10);
+
+    for record in &records {
+        assert_eq!(record.rust.arguments, ["f32"]);
+        assert_eq!(record.rust.result, "u32");
+        assert!(record.backend_lowerings.iter().any(|lowering| {
+            lowering.backend == IntrinsicBackend::LlvmNvptx
+                && lowering.mechanism == BackendLoweringMechanism::TypedNvvm
+        }));
+        assert!(record.backend_lowerings.iter().any(|lowering| {
+            lowering.backend == IntrinsicBackend::LibNvvm
+                && lowering.mechanism == BackendLoweringMechanism::InlinePtx
+        }));
+    }
+
+    let dialect = render_dialect_scalar_conversion(&catalog, "test-hash");
+    assert_eq!(dialect.matches("pub struct ScalarConversionOp;").count(), 1);
+    assert!(dialect.contains("pub enum ScalarConversionRoundingAttr"));
+    assert!(dialect.contains("pub enum ScalarConversionSaturationAttr"));
+    assert_eq!(
+        dialect
+            .matches("ScalarConversionOp::register(ctx);")
+            .count(),
+        1
+    );
+    for record in &records {
+        assert!(dialect.contains(scalar_conversion_rounding_attr(record)));
+        assert!(dialect.contains(scalar_conversion_saturation_attr(record)));
+    }
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert_eq!(
+        importer
+            .matches("let intrinsic = ScalarConversionOp::build")
+            .count(),
+        10
+    );
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert_eq!(
+        lowering
+            .matches("impl MirToLlvmConversion for ScalarConversionOp")
+            .count(),
+        1
+    );
+    for record in &records {
+        assert!(lowering.contains(&record.llvm_identifier()));
+        assert!(lowering.contains(&scalar_conversion_ptx_mnemonic(record)));
+        let probe = render_probe(&catalog, record, "test-hash");
+        assert!(probe.contains(&format!("declare i32 @{}(float)", llvm(record).symbol)));
+    }
+
+    let targets = render_targets(&catalog, "test-hash");
+    let production_targets = render_targets_files(&catalog, "test-hash")
+        .into_iter()
+        .filter(|(path, _)| !path.to_string_lossy().contains("/tests/"))
+        .map(|(_, contents)| contents)
+        .collect::<Vec<_>>()
+        .join("\n");
+    assert_eq!(
+        production_targets
+            .matches("GeneratedIntrinsicVariant::ScalarConversion {")
+            .count(),
+        11
+    );
+    assert!(targets.contains("Operation::get_op::<ScalarConversionOp>"));
+    assert!(targets.contains("GeneratedScalarConversionRounding::NearestAway"));
+    assert!(targets.contains("GeneratedScalarConversionSaturation::ReluSatfinite"));
+
+    let compatibility = render_compat_packed_conversion(
+        &catalog,
+        "test-hash",
+        "cuda_device::convert::",
+        "convert",
+        ("lo", "hi"),
+    );
+    assert!(compatibility.contains("pub fn cvt_rna_tf32_f32(value: f32) -> u32"));
+    assert!(compatibility.contains("pub fn cvt_rz_relu_satfinite_tf32_f32(value: f32) -> u32"));
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("pub fn i0368(_arg0: f32) -> u32"));
+    assert!(raw.contains("pub fn i0377(_arg0: f32) -> u32"));
+}
+
+#[test]
+fn packed_atomic_family_uses_one_attribute_dispatch_impl() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    let rendered = render_lowering(&catalog, "test-hash");
+    assert_eq!(
+        rendered
+            .matches("impl MirToLlvmConversion for PackedAtomicAddOp")
+            .count(),
+        1
+    );
+    assert_eq!(
+        rendered.matches("PackedAtomicFormatAttr::F16x2)").count(),
+        1
+    );
+    assert_eq!(
+        rendered.matches("PackedAtomicFormatAttr::Bf16x2)").count(),
+        1
+    );
+    for (op_type, ptx_type) in [
+        ("NvvmAtomAddF16x2Op", "f16x2"),
+        ("NvvmAtomAddBf16x2Op", "bf16x2"),
+    ] {
+        assert_eq!(
+            rendered
+                .matches(&format!("impl MirToLlvmConversion for {op_type}"))
+                .count(),
+            1
+        );
+        assert!(rendered.contains(&format!(
+            "convert_packed_atom_add(ctx, rewriter, self.get_operation(), \"{ptx_type}\")"
+        )));
+    }
+
+    let dialect = render_dialect_packed_atomic(&catalog, "test-hash");
+    for (op_type, op_name) in [
+        ("NvvmAtomAddF16x2Op", "nvvm.atom_add_f16x2"),
+        ("NvvmAtomAddBf16x2Op", "nvvm.atom_add_bf16x2"),
+    ] {
+        assert!(dialect.contains(&format!("pub struct {op_type};")));
+        assert!(dialect.contains(&format!("name = \"{op_name}\"")));
+        assert!(dialect.contains(&format!("{op_type}::register(ctx);")));
+    }
+}
+
+#[test]
+fn packed_atomic_raw_abi_is_unsafe_and_must_use() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    let rendered = render_raw_abi(&catalog, "test-hash").unwrap();
+    for abi_id in ["i0014", "i0015"] {
+        let signature = format!("pub unsafe fn {abi_id}(_arg0: *mut u32, _arg1: u32) -> u32");
+        let index = rendered.find(&signature).unwrap();
+        assert!(rendered[..index].ends_with("#[must_use]\n#[inline(never)]\n"));
+    }
+}
+
+#[test]
+fn packed_atomic_compatibility_preserves_paths_signature_and_safety() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    let rendered = render_compat_packed_atomic(&catalog, "test-hash");
+
+    for name in ["atom_add_f16x2", "atom_add_bf16x2"] {
+        let signature = format!("pub unsafe fn {name}(addr: *mut u32, val: u32) -> u32");
+        let index = rendered.find(&signature).unwrap();
+        assert!(rendered[..index].ends_with("#[must_use]\n#[inline(never)]\n"));
+        assert!(rendered.contains(&format!(
+            "unreachable!(\"{name} called outside CUDA kernel context\")"
+        )));
+    }
+    assert!(rendered.contains("relaxed GPU-scope operation"));
+    assert!(rendered.contains("low lane first"));
+    assert!(rendered.contains("may not form one old 32-bit snapshot"));
+    assert!(rendered.contains("Requires PTX 6.2 and `sm_70+`"));
+    assert!(rendered.contains("Requires PTX 7.8 and `sm_90+`"));
+    assert!(rendered.contains("four writable, four-byte-aligned bytes in global memory"));
+    assert!(rendered.contains("whole-word atomic or non-atomic lane access"));
+    assert!(rendered.contains("Racing atomics must use mutually inclusive scopes"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert_eq!(
+        outputs.get(&PathBuf::from("crates/cuda-device/src/generated/atomic.rs")),
+        Some(&rendered)
+    );
+}
+
+#[test]
+fn dot_product_rendering_preserves_stable_paths_and_low_selector() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(dot_products(&catalog).count(), 4);
+
+    let compatibility = render_compat_dotprod(&catalog, "test-hash");
+    for name in ["dp4a_s32", "dp4a_u32", "dp2a_s32", "dp2a_u32"] {
+        assert!(compatibility.contains(&format!("pub fn {name}(")));
+    }
+
+    let dialect = render_dialect_dotprod(&catalog, "test-hash");
+    assert!(dialect.contains("pub struct Dp4aS32Op"));
+    assert!(dialect.contains("pub struct Dp2aU32Op"));
+    assert!(dialect.contains("NOpdsInterface<3>"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::dotprod::dp2a_s32"));
+    assert!(importer.contains("let dot = Dp2aS32Op::build(ctx, a, b, c)"));
+    assert!(importer.contains("set_generated_intrinsic_marker(ctx, dot, \"v1:i0032\")"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("impl MirToLlvmConversion for Dp4aS32Op"));
+    assert!(lowering.contains("\"llvm_nvvm_idp2a_s_s\""));
+    assert!(lowering.contains("\"dp2a.lo.s32.s32 $0, $1, $2, $3;\""));
+    assert!(lowering.contains("\"dp2a.lo.s32.s32 $0, $1, $2, $3;\", true)"));
+
+    let low = dot_products(&catalog)
+        .find(|record| record.id == "dp2a_s32")
+        .unwrap();
+    let probe = render_probe(&catalog, low, "test-hash");
+    assert!(probe.contains("call i32 @llvm.nvvm.idp2a.s.s(i32 %a, i32 %b, i1 false, i32 %c)"));
+    assert!(!probe.contains("i1 true"));
+
+    let target = render_targets(&catalog, "test-hash");
+    assert!(target.contains("GeneratedImmediateBinding { argument_index: 2, value: 0 }"));
+    assert!(!target.contains("GeneratedImmediateBinding { argument_index: 2, value: -1 }"));
+}
+
+#[test]
+fn prmt_rendering_keeps_modes_and_zero_source_exact() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(prmts(&catalog).count(), 7);
+
+    let dialect = render_dialect_prmt(&catalog, "test-hash");
+    assert_eq!(dialect.matches("pub struct PrmtOp").count(), 1);
+    for mode in ["Generic", "F4e", "B4e", "Rc8", "Ecl", "Ecr", "Rc16"] {
+        assert!(dialect.contains(mode));
+    }
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    for mode in ["rc8", "ecl", "ecr", "rc16"] {
+        assert!(lowering.contains(&format!("prmt.b32.{mode} $0, $1, 0, $2;")));
+    }
+    assert!(lowering.contains("prmt.b32 $0, $1, $2, $3;"));
+    assert!(lowering.contains("prmt.b32.f4e $0, $1, $2, $3;"));
+    assert!(lowering.contains("prmt.b32.b4e $0, $1, $2, $3;"));
+    assert!(lowering.contains("convert_generated_prmt"));
+
+    let targets = render_targets(&catalog, "test-hash");
+    assert!(targets.contains("GeneratedIntrinsicVariant::Prmt"));
+    assert!(targets.contains("Operation::get_op::<PrmtOp>"));
+    assert!(targets.contains("GeneratedPrmtMode::Rc16"));
+
+    let compatibility = render_compat_prmt(&catalog, "test-hash");
+    assert_eq!(compatibility.matches("pub fn prmt").count(), 7);
+}
+
+#[test]
+fn selected_special_register_probes_use_the_llvm_route() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+
+    let clock = catalog
+        .intrinsics
+        .iter()
+        .find(|record| record.id == "clock")
+        .unwrap();
+    let typed = render_probe(&catalog, clock, "test-hash");
+    assert!(typed.contains("declare i32 @llvm.nvvm.read.ptx.sreg.clock()"));
+    assert!(typed.contains("call i32 @llvm.nvvm.read.ptx.sreg.clock()"));
+
+    let gridid = catalog
+        .intrinsics
+        .iter()
+        .find(|record| record.id == "gridid")
+        .unwrap();
+    let inline = render_probe(&catalog, gridid, "test-hash");
+    assert!(inline.contains("define i64 @probe_gridid_llvm_nvptx()"));
+    assert!(inline.contains("call i64 asm \"mov.u64 $0, %gridid;\", \"=l\"()"));
+}
+
+#[test]
+fn clc_rendering_preserves_api_and_uses_typed_llvm_routes() {
+    let catalog = catalog_with_clc();
+    validate_renderable(&catalog).unwrap();
+
+    let compatibility = render_compat_clc(&catalog, "test-hash");
+    assert!(
+        compatibility
+            .contains("pub unsafe fn clc_try_cancel(response: *mut u8, mbar: *mut Barrier)")
+    );
+    assert!(
+        compatibility.contains(
+            "pub unsafe fn clc_try_cancel_multicast(response: *mut u8, mbar: *mut Barrier)"
+        )
+    );
+    assert!(
+        compatibility
+            .contains("pub unsafe fn clc_query_is_canceled(resp_lo: u64, resp_hi: u64) -> u32")
+    );
+
+    let dialect = render_dialect_clc(&catalog, "test-hash");
+    for op in [
+        "ClcTryCancelOp",
+        "ClcTryCancelMulticastOp",
+        "ClcQueryIsCanceledOp",
+        "ClcQueryGetFirstCtaidXOp",
+        "ClcQueryGetFirstCtaidYOp",
+        "ClcQueryGetFirstCtaidZOp",
+    ] {
+        assert_eq!(dialect.matches(&format!("pub struct {op}")).count(), 1);
+        assert!(dialect.contains(&format!("{op}::register(ctx)")));
+    }
+    assert_eq!(dialect.matches("NResultsInterface<0>").count(), 2);
+    assert_eq!(dialect.matches("NResultsInterface<1>").count(), 4);
+    assert_eq!(dialect.matches("impl Verify for ClcQuery").count(), 4);
+    assert!(dialect.contains("is_integer_width(ctx, op.get_operand(0).get_type(ctx), 64)"));
+    assert!(dialect.contains("is_integer_width(ctx, op.get_result(0).get_type(ctx), 32)"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::clc::clc_try_cancel"));
+    assert!(importer.contains("ClcTryCancelOp::get_concrete_op_info()"));
+    assert!(importer.contains("ClcQueryIsCanceledOp::get_concrete_op_info()"));
+    assert!(importer.contains("helpers::emit_store_result_and_goto"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("clc::convert_generated_clc_query"));
+    assert!(lowering.contains("clc::convert_generated_clc_try_cancel"));
+    assert!(lowering.contains(
+            "convert_generated_clc_try_cancel(ctx, rewriter, self.get_operation(), operands_info, \"llvm__nvvm_dclusterlaunchcontrol_dtry_ucancel_dasync_dshared\")"
+        ));
+    assert!(lowering.contains(
+            "convert_generated_clc_query(ctx, rewriter, self.get_operation(), operands_info, \"llvm__nvvm_dclusterlaunchcontrol_dquery_ucancel_dis_ucanceled\", true)"
+        ));
+
+    let request = clc_intrinsics(&catalog)
+        .find(|record| record.id == "clc_try_cancel")
+        .unwrap();
+    let request_probe = render_probe(&catalog, request, "test-hash");
+    assert_eq!(request_probe.matches("addrspacecast ptr").count(), 2);
+    assert!(request_probe.contains(
+            "call void @llvm.nvvm.clusterlaunchcontrol.try_cancel.async.shared(ptr addrspace(3) %response, ptr addrspace(3) %mbarrier)"
+        ));
+
+    let query = clc_intrinsics(&catalog)
+        .find(|record| record.id == "clc_query_is_canceled")
+        .unwrap();
+    let query_probe = render_probe(&catalog, query, "test-hash");
+    assert!(query_probe.contains("%response_high_shifted = shl i128 %response_high_i128, 64"));
+    assert!(query_probe.contains("%response = or i128 %response_low_i128, %response_high_shifted"));
+    assert!(query_probe.contains("%result = zext i1 %raw_result to i32"));
+
+    let targets = render_targets(&catalog, "test-hash");
+    assert!(targets.contains(
+            "GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(100), GeneratedHardwareAlternative::ExactArchitecture(101), GeneratedHardwareAlternative::ExactArchitecture(103), GeneratedHardwareAlternative::ExactArchitecture(110), GeneratedHardwareAlternative::ExactArchitecture(120), GeneratedHardwareAlternative::ExactArchitecture(121)])"
+        ));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/clc.rs")));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/clc.rs"
+    )));
+
+    let mut wrong_adapter = catalog;
+    wrong_adapter
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "clc_query_is_canceled")
+        .unwrap()
+        .clc
+        .as_mut()
+        .unwrap()
+        .adapter = ClcAdapter::PairU64ToI128U32;
+    assert!(validate_renderable(&wrong_adapter).is_err());
+}
+
+#[test]
+fn debug_control_rendering_preserves_api_immediates_and_side_effects() {
+    let catalog = catalog_with_debug_controls();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(debug_controls(&catalog).count(), 3);
+
+    let compatibility = render_compat_debug_control(&catalog, "test-hash");
+    assert!(compatibility.contains("pub fn trap() -> !"));
+    assert!(compatibility.contains("pub fn breakpoint()"));
+    assert!(compatibility.contains("pub fn prof_trigger<const N: u32>()"));
+    assert!(compatibility.contains("pub(crate) fn __prof_trigger(_event_id: u32)"));
+    assert!(compatibility.contains("__prof_trigger(N);"));
+
+    let dialect = render_dialect_debug_control(&catalog, "test-hash");
+    for op in ["TrapOp", "BreakpointOp", "PmEventOp"] {
+        assert_eq!(dialect.matches(&format!("pub struct {op}")).count(), 1);
+        assert!(dialect.contains(&format!("{op}::register(ctx)")));
+    }
+    assert!(dialect.contains("event_id: u32"));
+    assert!(dialect.contains("pub fn new_with_event_id"));
+    assert!(dialect.contains("pub fn get_event_id"));
+    assert!(dialect.contains("filter(|value| *value <= 15)"));
+    assert!(dialect.contains("requires a u32 event ID in 0..=15"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::debug::__prof_trigger"));
+    assert!(importer.contains("mir::Operand::Constant"));
+    assert!(importer.contains("u32::try_from(value)"));
+    assert!(importer.contains("filter(|value| *value <= 15)"));
+    assert!(importer.contains("PmEventOp::build(ctx, event_id)"));
+    assert!(importer.contains("MirUnreachableOp::get_concrete_op_info()"));
+    assert!(importer.contains("prof_trigger requires a compile-time constant event ID in 0..=15"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    for op in ["TrapOp", "BreakpointOp", "PmEventOp"] {
+        assert!(lowering.contains(&format!("impl MirToLlvmConversion for {op}")));
+    }
+    assert!(lowering.contains(
+        "inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], \"trap;\", \"\")"
+    ));
+    assert!(lowering.contains(
+        "inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], \"brkpt;\", \"\")"
+    ));
+    assert!(lowering.contains("let template = format!(\"pmevent {event_id};\")"));
+
+    for record in debug_controls(&catalog) {
+        let probe = render_probe(&catalog, record, "test-hash");
+        assert!(probe.contains("call void asm sideeffect"));
+        assert!(!probe.contains("attributes #0 = { convergent }"));
+    }
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/debug_control.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/debug_control.rs"
+    )));
+
+    let mut wrong_adapter = catalog.clone();
+    wrong_adapter
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "pmevent")
+        .unwrap()
+        .debug_control
+        .as_mut()
+        .unwrap()
+        .adapter = DebugControlAdapter::Direct;
+    assert!(validate_renderable(&wrong_adapter).is_err());
+
+    let mut wrong_runtime = catalog;
+    wrong_runtime
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "trap")
+        .unwrap()
+        .debug_control
+        .as_mut()
+        .unwrap()
+        .runtime_validation = RuntimeValidation::Executed;
+    assert!(validate_renderable(&wrong_runtime).is_err());
+}
+
+#[test]
+fn scalar_arithmetic_rendering_uses_one_closed_carrier() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    let records = scalar_arithmetics(&catalog).collect::<Vec<_>>();
+    assert_eq!(records.len(), 64);
+    assert!(records.iter().all(|record| {
+        record.semantics.pure
+            == (record.scalar_arithmetic.as_ref().unwrap().operation
+                != ScalarArithmeticOperation::Div)
+    }));
+
+    let compatibility = render_compat_float(&catalog, "test-hash");
+    assert!(compatibility.contains("pub fn mul_rn_f64(arg0: f64, arg1: f64) -> f64"));
+    assert!(
+        compatibility.contains("pub fn fma_rp_ftz_sat_f32(arg0: f32, arg1: f32, arg2: f32) -> f32")
+    );
+    assert!(compatibility.contains("pub fn add_rp_ftz_sat_f32(arg0: f32, arg1: f32) -> f32"));
+    assert_eq!(compatibility.matches("#[must_use]").count(), 113);
+
+    let dialect = render_dialect_scalar_arithmetic(&catalog, "test-hash");
+    assert_eq!(dialect.matches("pub struct ScalarArithmeticOp").count(), 1);
+    for attr in [
+        "ScalarArithmeticFormatAttr",
+        "ScalarArithmeticOperationAttr",
+        "ScalarArithmeticRoundingAttr",
+        "ScalarArithmeticSubnormalAttr",
+        "ScalarArithmeticSaturationAttr",
+    ] {
+        assert!(dialect.contains(attr));
+        assert!(dialect.contains(&format!("{attr}::register(ctx)")));
+    }
+    assert!(dialect.contains("variant is not admitted"));
+    assert!(dialect.contains("ScalarArithmeticOperationAttr::Fma => 3"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert_eq!(
+        importer.matches("ScalarArithmeticOp::build(ctx").count(),
+        64
+    );
+    assert!(importer.contains("cuda_device::float::fma_rp_ftz_sat_f32"));
+    assert!(importer.contains("cuda_device::float::add_rp_ftz_sat_f32"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert_eq!(
+        lowering
+            .matches("impl MirToLlvmConversion for ScalarArithmeticOp")
+            .count(),
+        1
+    );
+    assert!(lowering.contains("llvm_nvvm_mul_rn_d"));
+    assert!(lowering.contains("fma.rp.ftz.sat.f32"));
+    assert!(lowering.contains("llvm_nvvm_add_rn_d"));
+    assert!(lowering.contains("add.rp.sat.ftz.f32"));
+    assert!(lowering.contains("recipe.0, recipe.1, recipe.2, recipe.3"));
+
+    let targets = render_targets(&catalog, "test-hash");
+    assert!(targets.contains("GeneratedIntrinsicVariant::ScalarArithmetic"));
+    assert!(targets.contains("GeneratedScalarArithmeticFormat::F64"));
+    assert!(targets.contains("GeneratedScalarArithmeticSaturation::Sat"));
+    assert!(targets.contains("Operation::get_op::<ScalarArithmeticOp>"));
+
+    let f64_mul = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mul_rn_f64")
+        .unwrap();
+    let f64_probe = render_probe(&catalog, f64_mul, "test-hash");
+    assert!(f64_probe.contains("declare double @llvm.nvvm.mul.rn.d(double, double)"));
+    let f32_sat = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "fma_rp_ftz_sat_f32")
+        .unwrap();
+    let f32_probe = render_probe(&catalog, f32_sat, "test-hash");
+    assert!(
+        f32_probe.contains("call float asm \"fma.rp.ftz.sat.f32 $0, $1, $2, $3;\", \"=f,f,f,f\"")
+    );
+    assert!(!f32_probe.contains("@llvm.nvvm.fma.rp.ftz.sat.f"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/float.rs")));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs"
+    )));
+}
+
+#[test]
+fn extended_minmax_rendering_is_closed_pure_and_exact() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    let records = extended_minmax(&catalog).collect::<Vec<_>>();
+    assert_eq!(records.len(), 52);
+    assert_eq!(
+        records
+            .iter()
+            .filter(|record| record.target.minimum_ptx.encoded() == 70)
+            .count(),
+        20
+    );
+    assert_eq!(
+        records
+            .iter()
+            .filter(|record| record.target.minimum_ptx.encoded() == 72)
+            .count(),
+        32
+    );
+    for id in ["min_f16x2", "max_f16x2", "min_bf16x2", "max_bf16x2"] {
+        assert_eq!(
+            catalog
+                .intrinsics
+                .iter()
+                .find(|record| record.id == id)
+                .unwrap()
+                .family,
+            "packed_alu"
+        );
+        assert!(records.iter().all(|record| record.id != id));
+    }
+
+    let f16 = render_compat_packed_alu(&catalog, "test-hash", PackedAluFormat::F16x2);
+    assert!(f16.contains("pub fn min_ftz_nan_xorsign_abs_f16x2(a: u32, b: u32) -> u32"));
+    let bf16 = render_compat_packed_alu(&catalog, "test-hash", PackedAluFormat::Bf16x2);
+    assert!(bf16.contains("pub fn max_nan_xorsign_abs_bf16x2(a: u32, b: u32) -> u32"));
+    let float = render_compat_float(&catalog, "test-hash");
+    assert!(float.contains("pub fn min_ftz_nan_xorsign_abs_f32(a: f32, b: f32) -> f32"));
+
+    let dialect = render_dialect_extended_minmax(&catalog, "test-hash");
+    assert_eq!(dialect.matches("pub struct ExtendedMinMaxOp").count(), 1);
+    assert_eq!(
+        dialect
+            .matches("            (ExtendedMinMaxFormatAttr::")
+            .count(),
+        52
+    );
+    for attr in [
+        "ExtendedMinMaxFormatAttr",
+        "ExtendedMinMaxOperationAttr",
+        "ExtendedMinMaxSubnormalAttr",
+        "ExtendedMinMaxNanAttr",
+        "ExtendedMinMaxXorSignAbsAttr",
+    ] {
+        assert!(dialect.contains(attr));
+        assert!(dialect.contains(&format!("{attr}::register(ctx)")));
+    }
+    assert!(dialect.contains("variant is not admitted"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert_eq!(importer.matches("ExtendedMinMaxOp::build(ctx").count(), 52);
+    assert!(importer.contains("cuda_device::float::min_xorsign_abs_f32"));
+    assert!(importer.contains("cuda_device::bf16x2::max_nan_bf16x2"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert_eq!(
+        lowering
+            .matches("impl MirToLlvmConversion for ExtendedMinMaxOp")
+            .count(),
+        1
+    );
+    assert!(lowering.contains("convert_generated_extended_minmax"));
+    assert!(lowering.contains("min.ftz.NaN.xorsign.abs.f32"));
+    assert!(lowering.contains("max.NaN.xorsign.abs.bf16x2"));
+
+    let targets = render_targets(&catalog, "test-hash");
+    assert!(targets.contains("GeneratedIntrinsicVariant::ExtendedMinMax"));
+    assert!(targets.contains("GeneratedPtxVersion::from_encoded(72)"));
+    assert!(targets.contains("Operation::get_op::<ExtendedMinMaxOp>"));
+    assert!(targets.contains("ExtendedMinMaxXorSignAbsAttr::Enabled"));
+
+    let packed_record = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "min_ftz_nan_f16x2")
+        .unwrap();
+    let packed_probe = render_probe(&catalog, packed_record, "test-hash");
+    assert!(packed_probe.contains("call i32 asm \"min.ftz.NaN.f16x2 $0, $1, $2;\", \"=r,r,r\""));
+    assert!(!packed_probe.contains("sideeffect"));
+    assert!(!packed_probe.contains("convergent"));
+    let f32_record = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "max_ftz_nan_xorsign_abs_f32")
+        .unwrap();
+    let f32_probe = render_probe(&catalog, f32_record, "test-hash");
+    assert!(
+        f32_probe
+            .contains("call float asm \"max.ftz.NaN.xorsign.abs.f32 $0, $1, $2;\", \"=f,f,f\"")
+    );
+    // Scalar 16-bit forms ride in `h` registers, not the packed `r` pair.
+    let half_record = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "min_ftz_nan_f16")
+        .unwrap();
+    let half_probe = render_probe(&catalog, half_record, "test-hash");
+    assert!(half_probe.contains("call i16 asm \"min.ftz.NaN.f16 $0, $1, $2;\", \"=h,h,h\""));
+    let bf16_record = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "max_nan_xorsign_abs_bf16")
+        .unwrap();
+    let bf16_probe = render_probe(&catalog, bf16_record, "test-hash");
+    assert!(
+        bf16_probe.contains("call i16 asm \"max.NaN.xorsign.abs.bf16 $0, $1, $2;\", \"=h,h,h\"")
+    );
+    assert!(lowering.contains("MinMaxCarrier::Half16"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/extended_minmax.rs"
+    )));
+    for module in ["float", "f16", "bf16", "f16x2", "bf16x2"] {
+        assert!(outputs.contains_key(&PathBuf::from(format!(
+            "crates/cuda-device/src/generated/{module}.rs"
+        ))));
+    }
+
+    let mut wrong_adapter = catalog;
+    wrong_adapter
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "min_xorsign_abs_f32")
+        .unwrap()
+        .extended_minmax
+        .as_mut()
+        .unwrap()
+        .adapter = ExtendedMinMaxAdapter::DirectPackedU32;
+    assert!(validate_renderable(&wrong_adapter).is_err());
+}
+
+#[test]
+fn extended_minmax_alone_renders_float_wrappers() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let mut catalog = crate::resolve::resolve(&repo_root).unwrap();
+    catalog
+        .intrinsics
+        .retain(|record| record.family == "extended_minmax");
+
+    let (path, float) = render_compat_float_output(&catalog, "test-hash")
+        .expect("extended min/max alone must render float wrappers");
+    assert_eq!(
+        path,
+        PathBuf::from("crates/cuda-device/src/generated/float.rs")
+    );
+    assert!(float.contains("pub fn min_xorsign_abs_f32(a: f32, b: f32) -> f32"));
+    assert!(!float.contains("pub fn add_rn_f32"));
+}
+
+/// Every reference row must carry exactly the six cells of its header.
+///
+/// A `|` in cell data splits the row before inline parsing, so it splits
+/// the cell even inside a code span. Three catalog entries write a PTX
+/// destination pair as `<register|predicate>`, and their rows rendered with
+/// a seventh cell, which drops the backend-evidence column. Counting
+/// unescaped pipes per row is the direct check.
+#[test]
+fn reference_rows_have_one_cell_per_header_column() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    let reference = render_reference(&catalog, "test-hash");
+
+    let mut rows = 0usize;
+    let mut carried_a_pipe = 0usize;
+    for line in reference
+        .lines()
+        .filter(|line| line.starts_with("| `cuda_intrinsics::"))
+    {
+        rows += 1;
+        if line.contains("\\|") {
+            carried_a_pipe += 1;
+        }
+        // Delimiters only: drop every escaped pipe first, then a six-column
+        // row leaves seven.
+        let delimiters = line.replace("\\|", "").matches('|').count();
+        assert_eq!(
+            delimiters, 7,
+            "row has {delimiters} cell delimiters, expected 7: {line}"
+        );
+    }
+
+    assert!(
+        rows > 900,
+        "expected the full reference, rendered {rows} rows"
+    );
+    assert!(
+        carried_a_pipe >= 3,
+        "expected the elect.sync and match.all.sync patterns to need escaping, \
+             found {carried_a_pipe} rows with an escaped pipe"
+    );
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/tests/tensor.rs b/crates/cuda-intrinsics-gen/src/render/tests/tensor.rs
new file mode 100644
index 0000000000..d431282c51
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/tests/tensor.rs
@@ -0,0 +1,1145 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::*;
+use crate::model::{CatalogTargetAlternative, TargetSelectorBinding};
+
+use crate::model::{
+    CatalogHardwareAlternative, CatalogHardwareTarget, CatalogTargetContract, IntrinsicSource,
+    Tcgen05Adapter, Tcgen05MmaBUsage, Tcgen05MmaForm, Tcgen05MmaKind, TmaAdapter,
+};
+use crate::render::common::{generated_hardware_target, hardware_target_label, llvm};
+use crate::render::families::{cluster_barriers, tcgen05_mma_inline_asm};
+use std::path::Path;
+
+#[test]
+fn paired_target_matrix_renders_selectors_and_ptx_floors() {
+    let target = CatalogHardwareTarget::TargetMatrix {
+        contracts: vec![CatalogTargetContract {
+            selectors: vec![TargetSelectorBinding {
+                name: "kind".into(),
+                value: "i8".into(),
+            }],
+            alternatives: vec![
+                CatalogTargetAlternative {
+                    minimum_ptx: "8.8".parse().unwrap(),
+                    hardware: CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                },
+                CatalogTargetAlternative {
+                    minimum_ptx: "9.0".parse().unwrap(),
+                    hardware: CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+                },
+            ],
+        }],
+    };
+
+    assert_eq!(
+        hardware_target_label(&target),
+        "sm_100a at PTX 8.8 or sm_110a at PTX 9.0 for kind=i8"
+    );
+    assert_eq!(
+        generated_hardware_target(&target),
+        "GeneratedHardwareTarget::TargetMatrix { contracts: &[GeneratedTargetContract { selectors: &[GeneratedTargetSelectorBinding { name: \"kind\", value: \"i8\" }], alternatives: &[GeneratedTargetAlternative { minimum_ptx: GeneratedPtxVersion::from_encoded(88), hardware: GeneratedHardwareAlternative::ExactArchitecture(100) }, GeneratedTargetAlternative { minimum_ptx: GeneratedPtxVersion::from_encoded(90), hardware: GeneratedHardwareAlternative::ExactArchitecture(110) }] }] }"
+    );
+}
+
+#[test]
+fn tcgen05_mma_inline_asm_closes_selectors_and_operand_order() {
+    for (kind, spelling) in [
+        (Tcgen05MmaKind::F16, "kind::f16"),
+        (Tcgen05MmaKind::Tf32, "kind::tf32"),
+        (Tcgen05MmaKind::F8f6f4, "kind::f8f6f4"),
+        (Tcgen05MmaKind::I8, "kind::i8"),
+    ] {
+        let (template, _) = tcgen05_mma_inline_asm(
+            Tcgen05MmaForm::WsTensor,
+            kind,
+            1,
+            None,
+            Some(0),
+            Some(Tcgen05MmaBUsage::Discard),
+        );
+        assert!(template.contains(spelling));
+    }
+    for (usage, spelling) in [
+        (Tcgen05MmaBUsage::Discard, "collector::b0::discard"),
+        (Tcgen05MmaBUsage::LastUse, "collector::b0::lastuse"),
+        (Tcgen05MmaBUsage::Fill, "collector::b0::fill"),
+        (Tcgen05MmaBUsage::Use, "collector::b0::use"),
+    ] {
+        let (template, _) = tcgen05_mma_inline_asm(
+            Tcgen05MmaForm::WsTensor,
+            Tcgen05MmaKind::F16,
+            1,
+            None,
+            Some(0),
+            Some(usage),
+        );
+        assert!(template.contains(spelling));
+    }
+
+    for (form, operands, constraints) in [
+        (
+            Tcgen05MmaForm::WsTensor,
+            "[$0], [$1], $2, $3, %enable_pred;",
+            "r,r,l,r,r,~{memory}",
+        ),
+        (
+            Tcgen05MmaForm::WsSpTensor,
+            "[$0], [$1], $2, [$5], $3, %enable_pred;",
+            "r,r,l,r,r,r,~{memory}",
+        ),
+        (
+            Tcgen05MmaForm::WsTensorZeroColMask,
+            "[$0], [$1], $2, $3, %enable_pred, $5;",
+            "r,r,l,r,r,l,~{memory}",
+        ),
+        (
+            Tcgen05MmaForm::WsSpTensorZeroColMask,
+            "[$0], [$1], $2, [$5], $3, %enable_pred, $6;",
+            "r,r,l,r,r,r,l,~{memory}",
+        ),
+    ] {
+        let (template, actual_constraints) = tcgen05_mma_inline_asm(
+            form,
+            Tcgen05MmaKind::F16,
+            1,
+            None,
+            Some(3),
+            Some(Tcgen05MmaBUsage::LastUse),
+        );
+        assert!(template.contains(operands));
+        assert_eq!(actual_constraints, constraints);
+    }
+}
+
+#[test]
+fn wgmma_controls_render_closed_compatibility_and_backend_routes() {
+    let catalog = catalog_with_wgmma_controls();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(wgmma_controls(&catalog).count(), 3);
+
+    let compatibility = render_compat_wgmma_control(&catalog, "test-hash");
+    assert!(compatibility.contains("pub fn wgmma_fence()"));
+    assert!(compatibility.contains("pub fn wgmma_commit_group()"));
+    assert!(compatibility.contains("pub fn wgmma_wait_group<const N: u32>()"));
+    assert!(compatibility.contains("__wgmma_wait_group(N as u64);"));
+    assert!(compatibility.contains("pub(crate) fn __wgmma_wait_group(_max_pending: u64)"));
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("pub unsafe fn i0317()"));
+    assert!(raw.contains("pub unsafe fn i0318()"));
+    assert!(raw.contains("pub unsafe fn i0319(_arg0: u64)"));
+    let raw_mod = render_raw_mod(&catalog, "test-hash");
+    assert!(
+        raw_mod.contains("pub use crate::__cuda_oxide_intrinsic_abi_v1::i0317 as wgmma_fence;")
+    );
+    assert!(
+        raw_mod
+            .contains("pub use crate::__cuda_oxide_intrinsic_abi_v1::i0319 as wgmma_wait_group;")
+    );
+
+    let dialect = render_dialect_wgmma_control(&catalog, "test-hash");
+    for op in [
+        "WgmmaFenceSyncAlignedOp",
+        "WgmmaCommitGroupSyncAlignedOp",
+        "WgmmaWaitGroupSyncAlignedOp",
+    ] {
+        assert!(dialect.contains(&format!("pub struct {op};")));
+        assert!(dialect.contains(&format!("{op}::register(ctx);")));
+    }
+    assert!(dialect.contains("operand must be i64"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::wgmma::wgmma_fence"));
+    assert!(importer.contains("cuda_device::wgmma::wgmma_commit_group"));
+    assert!(importer.contains("cuda_device::wgmma::__wgmma_wait_group"));
+    assert!(importer.contains("wgmma_wait_group requires a compile-time constant"));
+    assert!(importer.contains("WgmmaWaitGroupSyncAlignedOp::build(ctx, max_pending)"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("llvm_nvvm_wgmma_fence_sync_aligned"));
+    assert!(lowering.contains("llvm__nvvm_dwgmma_dcommit_ugroup_dsync_daligned"));
+    assert!(lowering.contains("llvm__nvvm_dwgmma_dwait_ugroup_dsync_daligned"));
+    assert!(lowering.contains("IntrinsicBackend::LlvmNvptx"));
+    assert!(lowering.contains("IntrinsicBackend::LibNvvm"));
+    assert!(lowering.contains("wgmma.fence.sync.aligned;"));
+    assert!(lowering.contains("wgmma.commit_group.sync.aligned;"));
+    assert!(lowering.contains("wgmma.wait_group.sync.aligned $0;"));
+    assert!(lowering.contains("\"n,~{memory}\""));
+
+    let targets = render_targets(&catalog, "test-hash");
+    assert!(
+        targets.contains("pub enum GeneratedWgmmaControlMode { Fence, CommitGroup, WaitGroup }")
+    );
+    assert!(targets.contains("GeneratedIntrinsicVariant::WgmmaControl"));
+    assert!(targets.contains("WgmmaFenceSyncAlignedOp>(operation, ctx).is_some()"));
+
+    for record in wgmma_controls(&catalog) {
+        let probe = render_probe(&catalog, record, "test-hash");
+        assert!(probe.contains(&format!("@{}", llvm(record).symbol)));
+        assert!(!probe.contains("asm sideeffect"));
+        assert!(probe.contains("attributes #0 = { convergent }"));
+    }
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/wgmma_control.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/wgmma_control.rs"
+    )));
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("## WGMMA-control contracts"));
+}
+
+#[test]
+fn cluster_composites_use_generated_private_sreg_leaves() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+
+    let leaves = render_compat_cluster_sreg(&catalog, "test-hash");
+    assert_eq!(leaves.matches("pub(crate) fn __cluster_").count(), 6);
+    for name in [
+        "__cluster_idxX",
+        "__cluster_idxY",
+        "__cluster_idxZ",
+        "__cluster_grid_dimX",
+        "__cluster_grid_dimY",
+        "__cluster_grid_dimZ",
+    ] {
+        assert!(leaves.contains(&format!("pub(crate) fn {name}() -> u32")));
+    }
+    assert!(!leaves.contains("pub fn cluster_ctaidX"));
+    assert!(!leaves.contains("pub fn cluster_nctaidX"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::cluster::__cluster_idxX"));
+    assert!(importer.contains("cuda_device::cluster::__cluster_grid_dimZ"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/cluster_sreg.rs"
+    )));
+}
+
+#[test]
+fn cluster_barrier_rendering_owns_compatibility_sync_and_both_backends() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    assert_eq!(cluster_barriers(&catalog).count(), 6);
+
+    let dialect = render_dialect_cluster_barrier(&catalog, "test-hash");
+    assert_eq!(dialect.matches("pub struct ClusterBarrierOp").count(), 1);
+    assert_eq!(dialect.matches("pub struct ClusterSyncOp").count(), 1);
+    assert!(dialect.contains("name = \"nvvm.cluster_sync\""));
+    assert!(dialect.contains("ClusterSyncOp::register(ctx);"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("\"cuda_device::cluster::cluster_sync\" =>"));
+    assert!(importer.contains("ClusterBarrierModeAttr::ArriveAligned"));
+    assert!(importer.contains("ClusterBarrierModeAttr::WaitAligned"));
+    assert!(!importer.contains("ClusterSyncOp"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert_eq!(
+        lowering
+            .matches("impl MirToLlvmConversion for ClusterSyncOp")
+            .count(),
+        1
+    );
+    assert!(lowering.contains("llvm_nvvm_barrier_cluster_arrive_aligned"));
+    assert!(lowering.contains("llvm_nvvm_barrier_cluster_wait_aligned"));
+    assert!(lowering.contains("barrier.cluster.arrive.aligned; barrier.cluster.wait.aligned;"));
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("## Cluster-barrier contracts"));
+    assert!(
+        reference.contains(
+            "`cuda_device::cluster::cluster_sync` is the generated compatibility operation"
+        )
+    );
+
+    let targets = render_targets(&catalog, "test-hash");
+    assert!(targets.contains(
+            "GeneratedIntrinsicVariant::ClusterBarrier { mode: GeneratedClusterBarrierMode::ArriveRelaxedAligned }"
+        ));
+    assert!(targets.contains("Operation::get_op::<ClusterBarrierOp>"));
+    assert!(targets.contains("ClusterBarrierModeAttr::WaitAligned"));
+}
+
+#[test]
+fn cluster_memory_rendering_preserves_cluster_shared_addrspace_and_composite_load() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    let records = cluster_memory(&catalog).collect::<Vec<_>>();
+    assert_eq!(records.len(), 2);
+
+    let compatibility = render_compat_cluster_memory(&catalog, "test-hash");
+    for signature in [
+        "pub unsafe fn map_shared_rank<T>(local_ptr: *const T, target_rank: u32) -> *const T",
+        "pub unsafe fn map_shared_rank_mut<T>(local_ptr: *mut T, target_rank: u32) -> *mut T",
+        "pub unsafe fn dsmem_read_u32(local_ptr: *const u32, target_rank: u32) -> u32",
+    ] {
+        assert!(compatibility.contains(signature), "missing {signature}");
+    }
+    assert!(compatibility.contains("cluster-shared pointer in address space 7"));
+
+    let dialect_mod = render_dialect_mod(&catalog, "test-hash");
+    assert!(dialect_mod.contains("mod cluster_memory;"));
+    assert!(dialect_mod.contains("pub use cluster_memory::*;"));
+    assert!(dialect_mod.contains("cluster_memory::register(ctx);"));
+
+    let dialect = render_dialect_cluster_memory(&catalog, "test-hash");
+    assert!(dialect.contains("pub struct MapaSharedClusterOp"));
+    assert!(dialect.contains("pub struct DsmemReadU32Op"));
+    assert!(dialect.contains("source_ptr.pointer_kind()"));
+    assert!(dialect.contains("address_space::CLUSTER_SHARED"));
+    assert!(dialect.contains("MirPointerKind::RawConst | MirPointerKind::RawMut"));
+    assert!(dialect.contains("result_ptr.pointer_kind() != source_ptr.pointer_kind()"));
+    assert!(dialect.contains(
+            "nvvm.mapa_shared_cluster requires a raw source pointer and must preserve its pointee, mutability, and raw kind while returning addrspace(7)"
+        ));
+    assert!(dialect.contains("nvvm.dsmem_read_u32 result must be u32"));
+    assert!(dialect.contains("MapaSharedClusterOp::register(ctx);"));
+    assert!(dialect.contains("DsmemReadU32Op::register(ctx);"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    for path in [
+        "cuda_device::cluster::map_shared_rank",
+        "cuda_device::cluster::map_shared_rank_mut",
+        "cuda_device::cluster::dsmem_read_u32",
+    ] {
+        assert!(importer.contains(path));
+    }
+    assert!(importer.contains("MapaSharedClusterOp::build(ctx, source, rank)"));
+    assert!(importer.contains("DsmemReadU32Op::build(ctx, source, rank)"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("cast_to_shared_addrspace"));
+    assert!(lowering.contains("llvm_ops::IntToPtrOp::new"));
+    assert!(lowering.contains("llvm_types::PointerType::get(ctx, 7)"));
+    assert!(lowering.contains("mapa.shared::cluster.u64 $0, $1, $2;"));
+    assert!(lowering.contains(
+            "{ .reg .u64 %mapped; mapa.shared::cluster.u64 %mapped, $1, $2; ld.shared::cluster.u32 $0, [%mapped]; }"
+        ));
+    assert!(lowering.contains("\"=l,l,r\""));
+    assert!(lowering.contains("\"=r,l,r,~{memory}\""));
+
+    let map = records
+        .iter()
+        .find(|record| record.id == "map_shared_rank")
+        .unwrap();
+    assert_eq!(map.llvm.as_ref().unwrap().results, ["shared_cluster_ptr"]);
+    let map_probe = render_probe(&catalog, map, "test-hash");
+    assert!(map_probe.contains("define ptr addrspace(7)"));
+    assert!(map_probe.contains("inttoptr i64"));
+    assert!(map_probe.contains("asm sideeffect"));
+    assert!(!map_probe.contains("~{memory}"));
+    assert!(map_probe.contains("attributes #0 = { convergent }"));
+
+    let read = records
+        .iter()
+        .find(|record| record.id == "dsmem_read_u32")
+        .unwrap();
+    assert!(read.llvm.is_none());
+    let read_probe = render_probe(&catalog, read, "test-hash");
+    assert!(read_probe.contains("ld.shared::cluster.u32"));
+    assert!(read_probe.contains("~{memory}"));
+    assert!(read_probe.contains("attributes #0 = { convergent }"));
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("pub unsafe fn i0320(_arg0: *const u8, _arg1: u32) -> *const u8"));
+    assert!(raw.contains("pub unsafe fn i0321(_arg0: *const u32, _arg1: u32) -> u32"));
+    assert!(raw.contains(
+        "ordinary loads and stores compile to `ld.shared::cluster` and `st.shared::cluster`"
+    ));
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("## Cluster-memory contracts"));
+    assert!(reference.contains("preserves LLVM 22's address-space-7 result"));
+    assert!(reference.contains("has no one-to-one LLVM intrinsic"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/cluster_memory.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/cluster_memory.rs"
+    )));
+
+    let mut wrong_as = catalog.clone();
+    wrong_as
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "map_shared_rank")
+        .unwrap()
+        .llvm
+        .as_mut()
+        .unwrap()
+        .results = vec!["shared_ptr".into()];
+    assert!(validate_renderable(&wrong_as).is_err());
+
+    let mut wrong_source = catalog;
+    wrong_source
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "dsmem_read_u32")
+        .unwrap()
+        .source = IntrinsicSource::LlvmImported {
+        source_record: "invented".into(),
+    };
+    assert!(validate_renderable(&wrong_source).is_err());
+}
+
+#[test]
+fn tma_rendering_preserves_api_and_injects_backend_defaults() {
+    let catalog = catalog_with_tma();
+    validate_renderable(&catalog).unwrap();
+
+    let compatibility = render_compat_tma(&catalog, "test-hash");
+    assert!(compatibility.contains(
+            "pub unsafe fn cp_async_bulk_tensor_1d_g2s(dst: *mut u8, tensor_map: *const TmaDescriptor, coord0: i32, barrier: *mut Barrier)"
+        ));
+    assert!(compatibility.contains(
+            "pub unsafe fn cp_async_bulk_tensor_2d_g2s_multicast(dst: *mut u8, tensor_map: *const TmaDescriptor, coord0: i32, coord1: i32, barrier: *mut Barrier, cta_mask: u16)"
+        ));
+    assert!(compatibility.contains(
+            "pub unsafe fn cp_async_bulk_tensor_5d_s2g(src: *const u8, tensor_map: *const TmaDescriptor, coord0: i32, coord1: i32, coord2: i32, coord3: i32, coord4: i32)"
+        ));
+    assert!(compatibility.contains("pub fn cp_async_bulk_commit_group()"));
+    assert!(compatibility.contains("pub fn cp_async_bulk_wait_group(n: u32)"));
+    assert!(compatibility.contains(
+            "pub unsafe fn cp_async_bulk_tensor_reduce_add_tile_2d(src: *const u8, tensor_map: *const TmaDescriptor, coord0: i32, coord1: i32)"
+        ));
+    assert!(compatibility.contains(
+            "pub unsafe fn cp_async_bulk_tensor_reduce_xor_im2col_5d(src: *const u8, tensor_map: *const TmaDescriptor, coord0: i32, coord1: i32, coord2: i32, coord3: i32, coord4: i32)"
+        ));
+    for dimensions in 1..=5 {
+        assert!(compatibility.contains(&format!(
+            "pub unsafe fn cp_async_bulk_prefetch_tensor_{dimensions}d_l2("
+        )));
+        assert!(compatibility.contains(&format!(
+            "pub unsafe fn cp_async_bulk_prefetch_tensor_{dimensions}d_l2_cache_hint("
+        )));
+    }
+    assert!(compatibility.contains("pub unsafe fn cp_async_bulk_prefetch_tensor_gather4_2d_l2("));
+    assert!(
+        compatibility
+            .contains("pub unsafe fn cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint(")
+    );
+    assert!(compatibility.contains("pub unsafe fn tensormap_replace_swizzle_atomicity("));
+    assert!(compatibility.contains("pub unsafe fn fence_proxy_tensormap_generic_acquire_system("));
+    assert!(compatibility.contains("pub fn fence_proxy_tensormap_generic_release_system()"));
+
+    let dialect = render_dialect_tma(&catalog, "test-hash");
+    assert_eq!(dialect.matches("pub struct ").count(), 111);
+    assert_eq!(dialect.matches("NResultsInterface<0>").count(), 111);
+    assert!(dialect.contains("NOpdsInterface<10>"));
+    assert!(dialect.contains("CpAsyncBulkWaitGroupReadOp::register(ctx)"));
+    assert!(dialect.contains("CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op::register(ctx)"));
+    assert!(
+        dialect
+            .contains("CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp::register(ctx)")
+    );
+    assert!(dialect.contains("ReplaceTensorMapSwizzleAtomicityOp::register(ctx)"));
+    assert!(dialect.contains("FenceProxyTensorMapGenericReleaseSystemOp::register(ctx)"));
+
+    let dialect_mod = render_dialect_mod(&catalog, "test-hash");
+    assert!(dialect_mod.contains("mod tma;"));
+    assert!(dialect_mod.contains("pub use tma::*;"));
+    assert!(dialect_mod.contains("tma::register(ctx);"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::tma::cp_async_bulk_tensor_1d_g2s"));
+    assert!(importer.contains("super::tma::emit_tma_g2s("));
+    assert!(importer.contains("super::tma::emit_tma_g2s_multicast_cg2("));
+    assert!(importer.contains("super::tma::emit_tma_s2g("));
+    assert!(importer.contains("TMA wait-group count must be a compile-time constant"));
+    assert!(importer.contains("require_arity(name, args.len(), 1, &loc)?;"));
+    assert!(importer.contains("args.first(), Some(mir::Operand::Constant(_))"));
+    assert!(importer.contains("\"v1:i0328\""));
+    assert!(importer.contains("cp_async_bulk_tensor_reduce_add_tile_2d"));
+    assert!(
+        importer.contains(
+            "dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile2dOp::get_concrete_op_info()"
+        )
+    );
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("CpAsyncBulkTensorG2sTile1dOp"));
+    for tma_import in [
+        "tma::convert_control",
+        "tma::convert_g2s",
+        "tma::convert_g2s_multicast_cg2",
+        "tma::convert_prefetch_tensormap",
+        "tma::convert_prefetch_tile",
+        "tma::convert_reduce_s2g",
+        "tma::convert_s2g",
+        "tma::convert_tensormap_fence",
+        "tma::convert_tensormap_replace",
+        "tma::PrefetchTileConfig",
+        "tma::ReduceConfig",
+    ] {
+        assert!(lowering.contains(tma_import), "{tma_import}");
+    }
+    assert!(
+        lowering
+            .contains("convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 5, false)")
+    );
+    assert!(
+        lowering.contains("convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 5)")
+    );
+    assert!(lowering.contains(
+            "convert_control(ctx, rewriter, self.get_operation(), operands_info, \"commit_group\", \"llvm_nvvm_cp_async_bulk_commit_group\")"
+        ));
+    assert!(lowering.contains(
+            "convert_reduce_s2g(ctx, rewriter, self.get_operation(), operands_info, ReduceConfig::new(2, \"add\", \"tile\", \"llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_2d\"))"
+        ));
+    assert!(lowering.contains(
+            "convert_prefetch_tile(ctx, rewriter, self.get_operation(), operands_info, PrefetchTileConfig::new(5, false, false, \"llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_5d\"))"
+        ));
+    assert!(lowering.contains(
+            "convert_tensormap_replace(ctx, rewriter, self.get_operation(), operands_info, \"llvm_nvvm_tensormap_replace_global_address\", \"global_address\", \"address\", false, false)"
+        ));
+    let release_system = tma_intrinsics(&catalog)
+        .find(|record| record.id == "fence_proxy_tensormap_generic_release_system")
+        .unwrap();
+    assert!(lowering.contains(&format!(
+            "convert_tensormap_fence(ctx, rewriter, self.get_operation(), operands_info, {:?}, false, \"sys\")",
+            release_system.resolved_llvm_identifier()
+        )));
+
+    let g2s = tma_intrinsics(&catalog)
+        .find(|record| record.id == "cp_async_bulk_tensor_2d_g2s_multicast_cg2")
+        .unwrap();
+    let g2s_probe = render_probe(&catalog, g2s, "test-hash");
+    assert!(g2s_probe.contains("i16 %cta_mask, i64 0, i1 true, i1 false, i32 2"));
+    assert!(g2s_probe.contains("addrspacecast ptr %dst_generic to ptr addrspace(7)"));
+
+    let s2g = tma_intrinsics(&catalog)
+        .find(|record| record.id == "cp_async_bulk_tensor_2d_s2g")
+        .unwrap();
+    let s2g_probe = render_probe(&catalog, s2g, "test-hash");
+    assert!(s2g_probe.contains("ptr %tensor_map, i32 %coord0, i32 %coord1, i64 0, i1 false"));
+
+    let reduce = tma_intrinsics(&catalog)
+        .find(|record| record.id == "cp_async_bulk_tensor_reduce_add_tile_2d")
+        .unwrap();
+    let reduce_probe = render_probe(&catalog, reduce, "test-hash");
+    assert!(reduce_probe.contains(
+            "declare void @llvm.nvvm.cp.async.bulk.tensor.reduce.add.tile.2d(ptr addrspace(3), ptr, i32, i32, i64, i1)"
+        ));
+    assert!(reduce_probe.contains(
+            "call void @llvm.nvvm.cp.async.bulk.tensor.reduce.add.tile.2d(ptr addrspace(3) %src, ptr %tensor_map, i32 %coord0, i32 %coord1, i64 0, i1 false)"
+        ));
+
+    for stem in [
+        "cp_async_bulk_prefetch_tensor_1d_l2",
+        "cp_async_bulk_prefetch_tensor_2d_l2",
+        "cp_async_bulk_prefetch_tensor_3d_l2",
+        "cp_async_bulk_prefetch_tensor_4d_l2",
+        "cp_async_bulk_prefetch_tensor_5d_l2",
+        "cp_async_bulk_prefetch_tensor_gather4_2d_l2",
+    ] {
+        let prefetch_plain = tma_intrinsics(&catalog)
+            .find(|record| record.id == stem)
+            .unwrap();
+        let prefetch_plain_probe = render_probe(&catalog, prefetch_plain, "test-hash");
+        assert!(prefetch_plain_probe.contains("i64 0, i1 false"));
+        assert!(!prefetch_plain_probe.contains("%cache_hint"));
+
+        let cache_hint_id = format!("{stem}_cache_hint");
+        let prefetch_cache_hint = tma_intrinsics(&catalog)
+            .find(|record| record.id == cache_hint_id)
+            .unwrap();
+        let prefetch_cache_hint_probe = render_probe(&catalog, prefetch_cache_hint, "test-hash");
+        assert!(prefetch_cache_hint_probe.contains("i64 %cache_hint"));
+        assert!(prefetch_cache_hint_probe.contains("i64 %cache_hint, i1 true"));
+    }
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/tma.rs")));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/tma.rs"
+    )));
+
+    let mut wrong_adapter = catalog;
+    wrong_adapter
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "cp_async_bulk_tensor_1d_g2s")
+        .unwrap()
+        .tma
+        .as_mut()
+        .unwrap()
+        .adapter = TmaAdapter::NoOperands;
+    assert!(validate_renderable(&wrong_adapter).is_err());
+}
+
+#[test]
+fn tcgen05_rendering_preserves_api_and_inline_ptx_routes() {
+    let catalog = catalog_with_tcgen05();
+    validate_renderable(&catalog).unwrap();
+
+    let compatibility = render_compat_tcgen05(&catalog, "test-hash");
+    assert!(
+        compatibility
+            .contains("pub unsafe fn tcgen05_alloc(dst_smem: *mut u32, n_cols: u32) -> ()")
+    );
+    assert!(compatibility.contains(
+            "pub unsafe fn tcgen05_mma_ws_f16(d_tmem: u32, a_tmem: u32, a_desc: u64, b_desc: u64, idesc: u32, enable_d: bool) -> ()"
+        ));
+    for alias in ["e4m3", "e5m2", "e2m3", "e3m2", "e2m1"] {
+        assert!(compatibility.contains(&format!(
+                "pub unsafe fn tcgen05_mma_{alias}(d_tmem: u32, a_desc: u64, b_desc: u64, idesc: u32, enable_d: bool)"
+            )));
+    }
+    assert!(
+        compatibility
+            .contains("pub unsafe fn tcgen05_ld_16x256b_x8_pure(tmem_addr: u32) -> TmemF32x32")
+    );
+    assert!(compatibility.contains("pub fn tcgen05_load_wait() -> ()"));
+    assert!(compatibility.contains("pub fn tcgen05_relinquish_alloc_permit() -> ()"));
+    assert!(compatibility.contains("pub fn tcgen05_relinquish_alloc_permit_cg2() -> ()"));
+    assert!(
+        compatibility.contains(
+            "One full warp must execute this instruction uniformly with the same operands."
+        )
+    );
+    assert!(compatibility.contains(
+            "One full warp in each peer CTA must execute this instruction; lanes within each warp must execute uniformly with the same operands."
+        ));
+    assert!(compatibility.contains(
+        "pub unsafe fn tcgen05_commit_multicast_cg2(mbar: *mut u64, cta_mask: u16) -> ()"
+    ));
+    assert!(compatibility.contains(
+        "pub unsafe fn tcgen05_cp_128x128b_b4x16_p64(tmem_addr: u32, smem_desc: u64) -> ()"
+    ));
+    assert!(compatibility.contains(
+        "pub unsafe fn tcgen05_cp_64x128b_warpx2_02_13_cg2(tmem_addr: u32, smem_desc: u64) -> ()"
+    ));
+    assert!(
+        compatibility.contains("pub unsafe fn tcgen05_ld_16x64b_x1_raw(tmem_addr: u32) -> u32")
+    );
+    assert!(
+        compatibility
+            .contains("pub unsafe fn tcgen05_ld_16x64b_x2_raw(tmem_addr: u32) -> CuSimd<u32, 2>")
+    );
+    assert!(compatibility.contains(
+        "pub unsafe fn tcgen05_ld_32x32b_x128_pack16(tmem_addr: u32) -> CuSimd<u32, 128>"
+    ));
+    assert!(
+        compatibility
+            .contains("pub unsafe fn tcgen05_st_16x64b_x1_raw(tmem_addr: u32, data: u32) -> ()")
+    );
+    assert!(compatibility.contains(
+        "pub unsafe fn tcgen05_st_16x64b_x2_raw(tmem_addr: u32, data: CuSimd<u32, 2>) -> ()"
+    ));
+    assert!(compatibility.contains(
+            "pub unsafe fn tcgen05_st_32x32b_x128_unpack16(tmem_addr: u32, data: CuSimd<u32, 128>) -> ()"
+        ));
+    assert!(compatibility.contains(
+            "pub unsafe fn tcgen05_ld_16x32bx2_x1_raw<const HALF_SPLIT_OFFSET: i32>(tmem_addr: u32) -> u32"
+        ));
+    assert!(compatibility.contains(
+            "pub(crate) unsafe fn __tcgen05_ld_16x32bx2_x1_raw(_tmem_addr: u32, _half_split_offset: i64) -> u32"
+        ));
+    assert!(
+        compatibility.contains(
+            "unsafe { __tcgen05_ld_16x32bx2_x1_raw(tmem_addr, HALF_SPLIT_OFFSET as i64) }"
+        )
+    );
+    assert!(compatibility.contains(
+            "pub unsafe fn tcgen05_st_16x32bx2_x128_unpack16<const HALF_SPLIT_OFFSET: i32>(tmem_addr: u32, data: CuSimd<u32, 128>)"
+        ));
+    assert!(compatibility.contains(
+            "pub(crate) unsafe fn __tcgen05_st_16x32bx2_x128_unpack16(_tmem_addr: u32, _half_split_offset: i64, _data: CuSimd<u32, 128>)"
+        ));
+    assert!(
+        compatibility.contains(
+            "pub unsafe fn tcgen05_commit_multicast(mbar: *mut u64, cta_mask: u16) -> ()"
+        )
+    );
+    assert!(compatibility.contains("pub unsafe fn tcgen05_shift_down(tmem_addr: u32) -> ()"));
+    assert!(compatibility.contains("pub unsafe fn tcgen05_shift_down_cg2(tmem_addr: u32) -> ()"));
+    assert_eq!(
+        compatibility
+            .matches("/// One thread in the CTA issues this instruction.\n")
+            .count(),
+        4
+    );
+    assert_eq!(
+            compatibility
+                .matches(
+                    "/// One thread in the CTA pair issues this instruction; the peer CTA must be active and must not have exited.\n",
+                )
+                .count(),
+            4
+        );
+    assert_eq!(
+            compatibility
+                .matches(
+                    "/// The same thread that issued the tracked asynchronous tcgen05 operations must issue this commit.\n",
+                )
+                .count(),
+            6
+        );
+    assert_eq!(
+            compatibility
+                .matches(
+                    "/// Completion must be tracked by a matching commit from that same thread and observed through the selected mbarrier before relying on shifted data.\n",
+                )
+                .count(),
+            2
+        );
+    assert_eq!(
+            compatibility
+                .matches(
+                    "/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n",
+                )
+                .count(),
+            233
+        );
+    assert!(compatibility.contains("/// `KIND` is 0=f16, 1=tf32, 2=f8f6f4, or 3=i8."));
+    assert!(compatibility.contains(
+        "/// `CTA_GROUP` is 1 or 2. `COLLECTOR_A` is 0=discard, 1=lastuse, 2=fill, or 3=use."
+    ));
+    assert!(compatibility.contains(
+        "/// `B_BUFFER` is 0 through 3. `B_USAGE` is 0=discard, 1=lastuse, 2=fill, or 3=use."
+    ));
+    assert_eq!(
+        compatibility
+            .matches("/// `legacy_a_desc` is kept for compatibility; tensor A uses `a_tmem`.\n",)
+            .count(),
+        5
+    );
+    assert_eq!(
+        compatibility
+            .matches("/// This uses kind f8f6f4, CTA group 1, and collector a::discard.\n",)
+            .count(),
+        5
+    );
+    assert!(!compatibility.contains("tcgen05_mma_ws_f16_with_collector"));
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("pub unsafe fn i0578(_arg0: u32, _arg1: u64) -> ()"));
+    assert!(raw.contains("pub unsafe fn i0611(_arg0: u32, _arg1: u64) -> ()"));
+    assert!(raw.contains("pub unsafe fn i0612(_arg0: u32) -> u32"));
+    assert!(raw.contains("pub unsafe fn i0614(_arg0: u32) -> [u32; 2]"));
+    assert!(raw.contains("pub unsafe fn i0669(_arg0: u32) -> [u32; 128]"));
+    assert!(raw.contains("pub unsafe fn i0670(_arg0: u32, _arg1: u32) -> ()"));
+    assert!(raw.contains("pub unsafe fn i0672(_arg0: u32, _arg1: [u32; 2]) -> ()"));
+    assert!(raw.contains("pub unsafe fn i0727(_arg0: u32, _arg1: [u32; 128]) -> ()"));
+    assert!(raw.contains("pub unsafe fn i0728(_arg0: u32, _arg1: i64) -> u32"));
+    assert!(raw.contains("pub unsafe fn i0743(_arg0: u32, _arg1: i64) -> [u32; 128]"));
+    assert!(raw.contains("pub unsafe fn i0759(_arg0: u32, _arg1: i64, _arg2: [u32; 128]) -> ()"));
+    assert!(raw.contains("pub unsafe fn i0760(_arg0: *mut u64, _arg1: u16) -> ()"));
+    assert!(raw.contains("pub unsafe fn i0761(_arg0: u32) -> ()"));
+    assert!(raw.contains("pub unsafe fn i0762(_arg0: u32) -> ()"));
+    let mma = raw.find("pub unsafe fn i0763").unwrap();
+    assert!(raw[..mma].ends_with("#[allow(clippy::too_many_arguments)]\n#[inline(never)]\n"));
+    assert!(raw.contains("lane component must be a multiple of 32"));
+    assert!(raw.contains("`_arg0` must name a live tensor-memory allocation"));
+    assert_eq!(
+        raw.matches("/// One thread in the CTA issues this instruction.\n")
+            .count(),
+        4
+    );
+    assert_eq!(
+            raw.matches(
+                "/// One thread in the CTA pair issues this instruction; the peer CTA must be active and must not have exited.\n",
+            )
+            .count(),
+            4
+        );
+    assert_eq!(
+            raw.matches(
+                "/// The same thread that issued the tracked asynchronous tcgen05 operations must issue this commit.\n",
+            )
+            .count(),
+            6
+        );
+    assert_eq!(
+            raw.matches(
+                "/// Completion must be tracked by a matching commit from that same thread and observed through the selected mbarrier before relying on shifted data.\n",
+            )
+            .count(),
+            2
+        );
+    assert_eq!(
+            raw.matches(
+                "/// All tcgen05 operations in the kernel must use the same CTA-group mode.\n",
+            )
+            .count(),
+            233
+        );
+    assert!(raw.contains("pub fn i0345() -> ()"));
+    assert!(raw.contains("pub fn i0357() -> ()"));
+    assert!(raw.contains("pub fn i0358() -> ()"));
+    assert!(raw.contains("pub fn i0361() -> ()"));
+    assert!(raw.contains("Complete the matching tensor-memory load wait"));
+    assert!(raw.contains("Complete the matching tensor-memory store wait"));
+    let raw_mod = render_raw_mod(&catalog, "test-hash");
+    assert!(raw_mod.contains(
+        "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0578 as tcgen05_cp_128x128b_b4x16_p64;"
+    ));
+    assert!(raw_mod.contains(
+            "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0611 as tcgen05_cp_64x128b_warpx2_02_13_cg2;"
+        ));
+    assert!(raw_mod.contains(
+        "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0727 as tcgen05_st_32x32b_x128_unpack16;"
+    ));
+    assert!(raw_mod.contains(
+        "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0728 as tcgen05_ld_16x32bx2_x1_raw;"
+    ));
+    assert!(raw_mod.contains(
+        "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0759 as tcgen05_st_16x32bx2_x128_unpack16;"
+    ));
+    assert!(raw_mod.contains(
+        "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0760 as tcgen05_commit_multicast;"
+    ));
+    assert!(
+        raw_mod
+            .contains("pub use crate::__cuda_oxide_intrinsic_abi_v1::i0761 as tcgen05_shift_down;")
+    );
+    assert!(raw_mod.contains(
+        "pub use crate::__cuda_oxide_intrinsic_abi_v1::i0762 as tcgen05_shift_down_cg2;"
+    ));
+
+    let dialect = render_dialect_tcgen05(&catalog, "test-hash");
+    assert_eq!(dialect.matches("pub struct Tcgen05").count(), 210);
+    assert_eq!(dialect.matches("impl Verify for Tcgen05").count(), 210);
+    assert_eq!(dialect.matches("::register(ctx)").count(), 216);
+    assert_eq!(dialect.matches("            Some(1),").count(), 32);
+    assert_eq!(dialect.matches("verifier = \"succ\"").count(), 6);
+    assert!(dialect.contains("Operation::get_op::<MirConstantOp>"));
+    assert!(dialect.contains("Operation::get_op::<ConstantOp>"));
+    assert!(dialect.contains("&[(Tcgen05Carrier::I32, 1), (Tcgen05Carrier::I64, 1)],"));
+    assert!(dialect.contains(
+        "&[(Tcgen05Carrier::I32, 1), (Tcgen05Carrier::I64, 1), (Tcgen05Carrier::I32, 128)],"
+    ));
+    assert!(dialect.contains("pub struct Tcgen05Ld16x64bX1RawOp"));
+    assert!(dialect.contains("pub struct Tcgen05Ld32x32bX128Pack16Op"));
+    assert!(dialect.contains("pub struct Tcgen05St16x64bX1RawOp"));
+    assert!(dialect.contains("pub struct Tcgen05St32x32bX128Unpack16Op"));
+    assert!(dialect.contains("pub struct Tcgen05Ld16x32bx2X1RawOp"));
+    assert!(dialect.contains("pub struct Tcgen05St16x32bx2X128Unpack16Op"));
+    assert!(dialect.contains("pub struct Tcgen05CommitMulticastOp"));
+    assert!(dialect.contains("pub struct Tcgen05ShiftDownOp"));
+    assert!(dialect.contains("pub struct Tcgen05ShiftDownCg2Op"));
+    assert!(dialect.contains("NResultsInterface<128>"));
+    assert!(dialect.contains("NResultsInterface<32>"));
+    assert!(dialect.contains("NResultsInterface<4>"));
+    assert!(dialect.contains("NOpdsInterface<6>"));
+
+    let dialect_mod = render_dialect_mod(&catalog, "test-hash");
+    assert!(dialect_mod.contains("mod tcgen05;"));
+    assert!(dialect_mod.contains("pub use tcgen05::*;"));
+    assert!(dialect_mod.contains("tcgen05::register(ctx);"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::tcgen05::tcgen05_alloc"));
+    assert!(importer.contains("Tcgen05AllocOp::get_concrete_op_info()"));
+    assert!(importer.contains("Tcgen05Ld16x256bX8PureOp::get_concrete_op_info()"));
+    assert!(importer.contains("MirConstructStructOp::get_concrete_op_info()"));
+    assert!(importer.contains("Tcgen05Ld16x64bX1RawOp::get_concrete_op_info()"));
+    assert!(importer.contains("Tcgen05Ld32x32bX128Pack16Op::get_concrete_op_info()"));
+    assert!(importer.contains("Tcgen05St16x64bX1RawOp::get_concrete_op_info()"));
+    assert!(importer.contains("Tcgen05St32x32bX128Unpack16Op::get_concrete_op_info()"));
+    assert!(importer.contains("import_generated_tcgen05_store_operands("));
+    assert!(importer.contains("downcast_ref::<MirStructType>()"));
+    assert!(
+        importer.contains("generated tcgen05 store data must contain {expected_len} u32 registers")
+    );
+    assert!(importer.contains("destination_ty == array_result.get_type(ctx)"));
+    assert!(!importer.contains("super::tcgen05::emit_"));
+    assert!(importer.contains("\"v1:i0343\""));
+    assert!(importer.contains("\"v1:i0366\""));
+    assert!(importer.contains("cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64"));
+    assert!(importer.contains("Tcgen05Cp128x128bB4x16P64Op::get_concrete_op_info()"));
+    assert!(importer.contains("\"v1:i0578\""));
+    assert!(importer.contains("\"v1:i0611\""));
+    assert!(importer.contains("\"v1:i0670\""));
+    assert!(importer.contains("\"v1:i0727\""));
+    assert!(importer.contains("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw"));
+    assert!(importer.contains("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16"));
+    assert!(
+        importer.contains("tcgen05 16x32bx2 half-split offset must be a compile-time constant")
+    );
+    assert!(importer.contains("half-split offset must lower to a constant"));
+    assert!(importer.contains("args, 128, true, block_ptr"));
+    assert!(importer.contains("\"v1:i0728\""));
+    assert!(importer.contains("\"v1:i0759\""));
+    assert!(importer.contains("\"v1:i0760\""));
+    assert!(importer.contains("\"v1:i0761\""));
+    assert!(importer.contains("\"v1:i0762\""));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(!lowering.contains("use crate::convert::intrinsics::tcgen05;"));
+    assert!(lowering.contains("impl MirToLlvmConversion for Tcgen05AllocOp"));
+    assert!(
+        lowering
+            .contains("tcgen05.mma.ws.cta_group::1.kind::f16 [$0], [$1], $3, $4, %enable_pred;")
+    );
+    assert!(!lowering.contains(".kind::bf16"));
+    assert!(lowering.contains("convert_generated_tcgen05_load("));
+    assert!(lowering.contains("tcgen05.ld.sync.aligned.16x64b.x1.b32 {$0}, [$1];"));
+    assert!(lowering.contains("tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 {$0}, [$1];"));
+    assert!(lowering.contains("\"=r,r,~{memory}\""));
+    assert!(lowering.contains(
+        "convert_generated_tcgen05_load(ctx, rewriter, self.get_operation(), 1, 1, true"
+    ));
+    assert!(lowering.contains("convert_generated_tcgen05_void("));
+    assert!(lowering.contains("tcgen05.st.sync.aligned.16x64b.x1.b32 [$0], {$1};"));
+    assert!(lowering.contains("tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [$0], {$1,$2"));
+    assert!(lowering.contains("\"r,r,~{memory}\""));
+    assert!(lowering.contains("tcgen05.ld.sync.aligned.16x32bx2.x1.b32 {$0}, [$1], $2;"));
+    assert!(lowering.contains("tcgen05.st.sync.aligned.16x32bx2.x1.b32 [$0], $1, {$2};"));
+    assert!(lowering.contains("\"=r,r,n,~{memory}\""));
+    assert!(lowering.contains("\"r,n,r,~{memory}\""));
+    assert!(lowering.contains(
+        "convert_generated_tcgen05_load(ctx, rewriter, self.get_operation(), 2, 1, true"
+    ));
+    assert!(lowering.contains("builtin::types::{FP32Type, IntegerType, Signedness}"));
+    assert!(lowering.contains("ops as llvm_ops"));
+    assert!(lowering.contains("inserter::Inserter"));
+    assert!(lowering.contains("tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 [$0], $1;"));
+    assert!(lowering.contains("tcgen05.cp.cta_group::1.32x128b.warpx4 [$0], $1;"));
+    assert!(
+        lowering
+            .contains("tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 [$0], $1;")
+    );
+    assert!(lowering.contains("tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [$0], $1;"));
+    assert!(lowering.contains("\"r,l,~{memory}\""));
+    assert!(lowering.contains(
+            "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;"
+        ));
+    assert!(lowering.contains("tcgen05.shift.cta_group::1.down [$0];"));
+    assert!(lowering.contains("tcgen05.shift.cta_group::2.down [$0];"));
+    assert!(lowering.contains("\"r,h,~{memory}\""));
+
+    let bf16 = tcgen05_intrinsics(&catalog)
+        .find(|record| record.id == "tcgen05_mma_ws_bf16")
+        .unwrap();
+    let bf16_probe = render_probe(&catalog, bf16, "test-hash");
+    assert!(bf16_probe.contains("route: inline PTX"));
+    assert!(bf16_probe.contains(".kind::f16 [$0]"));
+    assert!(!bf16_probe.contains(".kind::bf16"));
+
+    let base_commit = tcgen05_intrinsics(&catalog)
+        .find(|record| record.id == "tcgen05_commit")
+        .unwrap();
+    let base_commit_probe = render_probe(&catalog, base_commit, "test-hash");
+    assert!(base_commit_probe.contains("mbarrier::arrive::one.b64"));
+    assert!(!base_commit_probe.contains("one.shared::cluster.b64"));
+
+    let shared_commit = tcgen05_intrinsics(&catalog)
+        .find(|record| record.id == "tcgen05_commit_shared_cluster")
+        .unwrap();
+    let shared_commit_probe = render_probe(&catalog, shared_commit, "test-hash");
+    assert!(shared_commit_probe.contains("one.shared::cluster.b64"));
+
+    for (id, spelling) in [
+        (
+            "tcgen05_commit_multicast",
+            "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;",
+        ),
+        (
+            "tcgen05_shift_down",
+            "tcgen05.shift.cta_group::1.down [$0];",
+        ),
+        (
+            "tcgen05_shift_down_cg2",
+            "tcgen05.shift.cta_group::2.down [$0];",
+        ),
+    ] {
+        let record = tcgen05_intrinsics(&catalog)
+            .find(|record| record.id == id)
+            .unwrap();
+        let probe = render_probe(&catalog, record, "test-hash");
+        assert!(probe.contains(spelling));
+        assert!(probe.contains("asm sideeffect"));
+        assert!(probe.contains("attributes #0 = { convergent }"));
+    }
+
+    for (id, spelling) in [
+        (
+            "tcgen05_cp_128x128b_b4x16_p64",
+            "tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64",
+        ),
+        (
+            "tcgen05_cp_32x128b_warpx4",
+            "tcgen05.cp.cta_group::1.32x128b.warpx4",
+        ),
+        (
+            "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2",
+            "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32",
+        ),
+        (
+            "tcgen05_cp_64x128b_warpx2_02_13",
+            "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13",
+        ),
+    ] {
+        let record = tcgen05_intrinsics(&catalog)
+            .find(|record| record.id == id)
+            .unwrap();
+        let probe = render_probe(&catalog, record, "test-hash");
+        assert!(probe.contains(spelling));
+        assert!(probe.contains("asm sideeffect"));
+        assert!(probe.contains("\"r,l,~{memory}\""));
+        assert!(probe.contains("attributes #0 = { convergent }"));
+    }
+
+    let scalar_load = tcgen05_intrinsics(&catalog)
+        .find(|record| record.id == "tcgen05_ld_16x64b_x1_raw")
+        .unwrap();
+    let scalar_load_probe = render_probe(&catalog, scalar_load, "test-hash");
+    assert!(scalar_load_probe.contains("%result = call i32 asm sideeffect"));
+    assert!(scalar_load_probe.contains("tcgen05.ld.sync.aligned.16x64b.x1.b32"));
+    assert!(scalar_load_probe.contains("\"=r,r,~{memory}\""));
+
+    let packed_load = tcgen05_intrinsics(&catalog)
+        .find(|record| record.id == "tcgen05_ld_32x32b_x128_pack16")
+        .unwrap();
+    let packed_load_probe = render_probe(&catalog, packed_load, "test-hash");
+    assert!(packed_load_probe.contains("tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32"));
+    assert!(packed_load_probe.contains("{ i32, i32"));
+
+    let scalar_store = tcgen05_intrinsics(&catalog)
+        .find(|record| record.id == "tcgen05_st_16x64b_x1_raw")
+        .unwrap();
+    let scalar_store_probe = render_probe(&catalog, scalar_store, "test-hash");
+    assert!(scalar_store_probe.contains("call void asm sideeffect"));
+    assert!(scalar_store_probe.contains("tcgen05.st.sync.aligned.16x64b.x1.b32"));
+    assert!(scalar_store_probe.contains("\"r,r,~{memory}\""));
+
+    let unpacked_store = tcgen05_intrinsics(&catalog)
+        .find(|record| record.id == "tcgen05_st_32x32b_x128_unpack16")
+        .unwrap();
+    let unpacked_store_probe = render_probe(&catalog, unpacked_store, "test-hash");
+    assert!(unpacked_store_probe.contains("tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32"));
+    assert!(unpacked_store_probe.contains("i32 %d127"));
+
+    let offset_load = tcgen05_intrinsics(&catalog)
+        .find(|record| record.id == "tcgen05_ld_16x32bx2_x1_pack16")
+        .unwrap();
+    let offset_load_probe = render_probe(&catalog, offset_load, "test-hash");
+    assert!(offset_load_probe.contains("i64 16"));
+    assert!(offset_load_probe.contains("[$1], $2;"));
+    assert!(offset_load_probe.contains("\"=r,r,n,~{memory}\""));
+
+    let offset_store = tcgen05_intrinsics(&catalog)
+        .find(|record| record.id == "tcgen05_st_16x32bx2_x1_unpack16")
+        .unwrap();
+    let offset_store_probe = render_probe(&catalog, offset_store, "test-hash");
+    assert!(offset_store_probe.contains("i64 16"));
+    assert!(offset_store_probe.contains("[$0], $1, {$2};"));
+    assert!(offset_store_probe.contains("\"r,n,r,~{memory}\""));
+
+    let target = render_targets(&catalog, "test-hash");
+    assert!(target.contains("\"v1:i0343\""));
+    assert!(target.contains("\"v1:i0578\""));
+    assert!(target.contains("\"v1:i0611\""));
+    assert!(target.contains("\"v1:i0727\""));
+    assert!(target.contains("\"v1:i0728\""));
+    assert!(target.contains("\"v1:i0759\""));
+    assert!(target.contains(
+        "Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr, Tcgen05MmaFormAttr"
+    ));
+    assert!(target.contains(
+            "GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(100), GeneratedHardwareAlternative::ExactArchitecture(101), GeneratedHardwareAlternative::ExactArchitecture(103), GeneratedHardwareAlternative::ExactArchitecture(110)])"
+        ));
+    assert!(target.contains(
+            "GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(100), GeneratedHardwareAlternative::ExactArchitecture(103), GeneratedHardwareAlternative::ExactArchitecture(110)])"
+        ));
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("- `tcgen05_st_16x64b_x1_raw`: runtime `unexecuted`"));
+    assert!(!reference.contains("- `tcgen05_st_16x64b_x1_raw`: runtime `not recorded`"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/tcgen05.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/tcgen05.rs"
+    )));
+
+    let mut wrong_adapter = catalog.clone();
+    wrong_adapter
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "tcgen05_alloc")
+        .unwrap()
+        .tcgen05
+        .as_mut()
+        .unwrap()
+        .adapter = Tcgen05Adapter::NoOperands;
+    assert!(validate_renderable(&wrong_adapter).is_err());
+
+    let mut wrong_libnvvm_target = catalog.clone();
+    wrong_libnvvm_target
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "tcgen05_cp_128x128b_b4x16_p64")
+        .unwrap()
+        .backend_lowerings[1]
+        .target
+        .hardware = CatalogHardwareTarget::AnyOf {
+        alternatives: vec![
+            CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+            CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+            CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+            CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+        ],
+    };
+    assert!(validate_renderable(&wrong_libnvvm_target).is_err());
+
+    let mut wrong_load_selector = catalog.clone();
+    wrong_load_selector
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "tcgen05_ld_16x64b_x1_pack16")
+        .unwrap()
+        .expected_ptx
+        .modifiers
+        .remove(5);
+    assert!(validate_renderable(&wrong_load_selector).is_err());
+
+    let mut wrong_store_selector = catalog.clone();
+    wrong_store_selector
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "tcgen05_st_16x64b_x1_unpack16")
+        .unwrap()
+        .expected_ptx
+        .modifiers
+        .remove(5);
+    assert!(validate_renderable(&wrong_store_selector).is_err());
+
+    let mut wrong_offset_scope = catalog.clone();
+    wrong_offset_scope
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "tcgen05_ld_16x32bx2_x1_raw")
+        .unwrap()
+        .semantics
+        .execution_scope = "thread".into();
+    assert!(validate_renderable(&wrong_offset_scope).is_err());
+
+    let mut wrong_copy_spelling = catalog;
+    wrong_copy_spelling
+        .intrinsics
+        .iter_mut()
+        .find(|record| record.id == "tcgen05_cp_128x128b_b4x16_p64")
+        .unwrap()
+        .expected_ptx
+        .modifiers
+        .remove(3);
+    assert!(validate_renderable(&wrong_copy_spelling).is_err());
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/tests/warp_memory.rs b/crates/cuda-intrinsics-gen/src/render/tests/warp_memory.rs
new file mode 100644
index 0000000000..a72a520f88
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/tests/warp_memory.rs
@@ -0,0 +1,979 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::*;
+
+use crate::model::{
+    BackendLoweringMechanism, IntrinsicSource, MbarrierBasicOperation, ReduxAdapter,
+    WarpBarrierAdapter, WarpShuffleMode, WarpShuffleValueKind,
+};
+use crate::render::common::{intrinsic_marker, llvm};
+use crate::render::families::{
+    active_masks, cp_async_controls, cp_async_copies, cp_async_mbarriers, mbarrier_basics, redux,
+    vote_intrinsics, warp_barriers, warp_matches, warp_shuffles,
+};
+use std::collections::BTreeSet;
+use std::path::Path;
+
+#[test]
+fn cp_async_rendering_preserves_compatibility_dispatch_and_backend_routes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(cp_async_copies(&catalog).count(), 8);
+    assert_eq!(cp_async_controls(&catalog).count(), 3);
+    assert_eq!(cp_async_mbarriers(&catalog).count(), 4);
+
+    let compatibility = render_compat_cp_async_copy(&catalog, "test-hash");
+    for signature in [
+        "pub unsafe fn cp_async_ca_4(_shared_dst: *mut u32, _global_src: *const u32)",
+        "pub unsafe fn cp_async_ca_8(_shared_dst: *mut u32, _global_src: *const u32)",
+        "pub unsafe fn cp_async_ca_16(_shared_dst: *mut u32, _global_src: *const u32)",
+        "pub unsafe fn cp_async_ca_zfill_4(_shared_dst: *mut u32, _global_src: *const u8, _src_size: u32)",
+        "pub unsafe fn cp_async_ca_zfill_8(_shared_dst: *mut u32, _global_src: *const u8, _src_size: u32)",
+        "pub unsafe fn cp_async_ca_zfill_16(_shared_dst: *mut u32, _global_src: *const u8, _src_size: u32)",
+        "pub unsafe fn cp_async_cg_16(_shared_dst: *mut u32, _global_src: *const u32)",
+        "pub unsafe fn cp_async_cg_zfill_16(_shared_dst: *mut u32, _global_src: *const u8, _src_size: u32)",
+        "pub unsafe fn cp_async_commit_group()",
+        "pub unsafe fn cp_async_wait_all()",
+        "pub unsafe fn cp_async_wait_group(_max_pending: u32)",
+        "pub unsafe fn cp_async_mbarrier_arrive(_barrier: *mut crate::barrier::Barrier)",
+        "pub unsafe fn cp_async_mbarrier_arrive_shared(_barrier: *mut crate::barrier::Barrier)",
+        "pub unsafe fn cp_async_mbarrier_arrive_noinc(_barrier: *mut crate::barrier::Barrier)",
+        "pub unsafe fn cp_async_mbarrier_arrive_noinc_shared(_barrier: *mut crate::barrier::Barrier)",
+    ] {
+        assert!(compatibility.contains(signature));
+    }
+
+    let dialect = render_dialect_cp_async_copy(&catalog, "test-hash");
+    let importer = render_importer(&catalog, "test-hash");
+    let lowering = render_lowering(&catalog, "test-hash");
+    let targets = render_targets(&catalog, "test-hash");
+    for record in cp_async_copies(&catalog)
+        .chain(cp_async_controls(&catalog))
+        .chain(cp_async_mbarriers(&catalog))
+    {
+        assert!(dialect.contains(&format!("pub struct {}", record.dialect.op_type)));
+        assert!(dialect.contains(&format!("{}::register(ctx)", record.dialect.op_type)));
+        assert!(importer.contains(&record.rust.canonical_path));
+        for path in &record.rust.compatibility_paths {
+            assert!(importer.contains(path));
+        }
+        assert!(importer.contains(&intrinsic_marker(&catalog, record)));
+        assert!(lowering.contains(&format!(
+            "impl MirToLlvmConversion for {}",
+            record.dialect.op_type
+        )));
+        assert!(lowering.contains(&record.llvm_identifier()));
+        assert!(
+            record
+                .backend_lowerings
+                .iter()
+                .any(|entry| entry.backend == IntrinsicBackend::LlvmNvptx)
+        );
+        assert!(
+            record
+                .backend_lowerings
+                .iter()
+                .any(|entry| entry.backend == IntrinsicBackend::LibNvvm)
+        );
+        assert!(targets.contains(&format!("id: {:?}", record.id)));
+    }
+    assert_eq!(dialect.matches("::register(ctx);").count(), 15);
+    assert!(lowering.contains("convert_generated_cp_async_copy"));
+    assert!(lowering.contains("convert_generated_cp_async_control"));
+    assert!(lowering.contains("convert_generated_cp_async_mbarrier"));
+}
+
+#[test]
+fn cp_async_mbarrier_rendering_preserves_counting_and_state_space_routes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    let records: Vec<_> = cp_async_mbarriers(&catalog).collect();
+    assert_eq!(records.len(), 4);
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("pub unsafe fn i0101(_arg0: *mut u64)"));
+    assert!(raw.contains("live, initialized, eight-byte-aligned mbarrier"));
+    assert!(raw.contains("initial pending count must already include"));
+
+    let compatibility = render_compat_cp_async_copy(&catalog, "test-hash");
+    assert_eq!(
+        compatibility
+            .matches("That increment must not exceed the barrier's pending-count limit.")
+            .count(),
+        2
+    );
+
+    let dialect = render_dialect_cp_async_copy(&catalog, "test-hash");
+    assert!(dialect.contains("mutable generic/shared pointer to u64"));
+    let importer = render_importer(&catalog, "test-hash");
+    let lowering = render_lowering(&catalog, "test-hash");
+    for record in &records {
+        assert!(importer.contains(&format!(
+            "let bridge = {}::build(ctx, barrier)",
+            record.dialect.op_type
+        )));
+        assert!(lowering.contains(&record.llvm_identifier()));
+        let routes: BTreeSet<_> = record
+            .backend_lowerings
+            .iter()
+            .map(|route| (route.backend, route.mechanism))
+            .collect();
+        assert_eq!(
+            routes,
+            BTreeSet::from([
+                (
+                    IntrinsicBackend::LlvmNvptx,
+                    BackendLoweringMechanism::TypedNvvm,
+                ),
+                (
+                    IntrinsicBackend::LibNvvm,
+                    BackendLoweringMechanism::InlinePtx,
+                ),
+            ])
+        );
+    }
+    assert!(lowering.contains("\"arrive\", \"generic\""));
+    assert!(lowering.contains("\"arrive\", \"shared\""));
+    assert!(lowering.contains("\"arrive_no_inc\", \"generic\""));
+    assert!(lowering.contains("\"arrive_no_inc\", \"shared\""));
+
+    let generic = records
+        .iter()
+        .find(|record| record.id == "cp_async_mbarrier_arrive")
+        .unwrap();
+    let generic_probe = render_probe(&catalog, generic, "test-hash");
+    assert!(generic_probe.contains("declare void @llvm.nvvm.cp.async.mbarrier.arrive(ptr)"));
+    assert!(!generic_probe.contains("addrspacecast"));
+    let shared = records
+        .iter()
+        .find(|record| record.id == "cp_async_mbarrier_arrive_shared")
+        .unwrap();
+    let shared_probe = render_probe(&catalog, shared, "test-hash");
+    assert!(shared_probe.contains("ptr addrspace(3)"));
+    assert!(shared_probe.contains("addrspacecast ptr %barrier_generic"));
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("## cp.async mbarrier contracts"));
+    assert!(reference.contains("cp_async_mbarrier_arrive_noinc`: runtime `unexecuted`"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/async_copy.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/cp_async.rs"
+    )));
+    assert!(!outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/cp_async_mbarrier.rs"
+    )));
+}
+
+#[test]
+fn redux_rendering_preserves_mask_first_api_and_source_first_llvm_order() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    assert_eq!(catalog.schema, crate::resolve::CATALOG_SCHEMA);
+    validate_renderable(&catalog).unwrap();
+
+    assert_eq!(redux(&catalog).count(), 16);
+    let record = redux(&catalog).next().unwrap();
+    assert_eq!(
+        record.redux.as_ref().unwrap().adapter,
+        ReduxAdapter::MaskValueToSourceMemberMask
+    );
+
+    let dialect = render_dialect_redux(&catalog, "test-hash");
+    assert!(dialect.contains("name = \"nvvm.redux_sync_add\""));
+    assert!(dialect.contains("name = \"nvvm.redux_sync_min\""));
+    assert!(dialect.contains("vec![member_mask, value]"));
+    assert!(dialect.contains("ReduxSyncAddOp::register(ctx)"));
+    assert!(dialect.contains("Signedness::Signed"));
+
+    assert!(dialect.contains("name = \"nvvm.redux_sync_fmin\""));
+    assert!(dialect.contains("types::{FP32Type, IntegerType, Signedness}"));
+    assert!(dialect.contains("let result_ty = FP32Type::get(ctx);"));
+    assert!(dialect.contains("is_f32(ctx, op.get_operand(1).get_type(ctx))"));
+    assert!(dialect.contains("is_f32(ctx, op.get_result(0).get_type(ctx))"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::warp::redux_sync_add"));
+    assert!(importer.contains("let (member_mask, last_op)"));
+    assert!(importer.contains("let reduction = ReduxSyncAddOp::build(ctx, member_mask, value)"));
+    assert!(importer.contains("set_generated_intrinsic_marker(ctx, reduction, \"v1:i0017\")"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("impl MirToLlvmConversion for ReduxSyncAddOp"));
+    assert!(lowering.contains("convert_redux(ctx, rewriter, self.get_operation(), operands_info"));
+    assert!(lowering.contains("\"llvm_nvvm_redux_sync_add\""));
+
+    let probe = render_probe(&catalog, record, "test-hash");
+    assert!(probe.contains("define i32 @probe_redux_sync_add(i32 %member_mask, i32 %value)"));
+    assert!(probe.contains("call i32 @llvm.nvvm.redux.sync.add(i32 %value, i32 %member_mask)"));
+
+    let f32_record = redux(&catalog)
+        .find(|record| record.id == "redux_sync_min_f32")
+        .unwrap();
+    let f32_probe = render_probe(&catalog, f32_record, "test-hash");
+    assert!(
+        f32_probe
+            .contains("define float @probe_redux_sync_min_f32(i32 %member_mask, float %value)")
+    );
+    assert!(
+        f32_probe.contains("call float @llvm.nvvm.redux.sync.fmin(float %value, i32 %member_mask)")
+    );
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    let signature = "pub unsafe fn i0017(_arg0: u32, _arg1: u32) -> u32";
+    let index = raw.find(signature).unwrap();
+    assert!(raw[..index].ends_with("#[must_use]\n#[inline(never)]\n"));
+    assert!(raw.contains("pub unsafe fn i0019(_arg0: u32, _arg1: i32) -> i32"));
+    assert!(raw.contains("pub unsafe fn i0024(_arg0: u32, _arg1: u32) -> u32"));
+    assert!(raw.contains("pub unsafe fn i1003(_arg0: u32, _arg1: f32) -> f32"));
+    assert!(raw.contains("The executing lane must be named in `mask`"));
+}
+
+#[test]
+fn vote_rendering_keeps_types_selection_pairs_and_raw_only_uni() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(vote_intrinsics(&catalog).count(), 4);
+
+    let dialect = render_dialect_vote(&catalog, "test-hash");
+    for op in [
+        "VoteSyncAllOp",
+        "VoteSyncAnyOp",
+        "VoteSyncBallotOp",
+        "VoteSyncUniOp",
+    ] {
+        assert!(dialect.contains(&format!("pub struct {op}")));
+        assert!(dialect.contains(&format!("{op}::register(ctx)")));
+    }
+    assert!(dialect.contains("requires i32 member mask, i1 predicate, and i1 result"));
+    assert!(dialect.contains("requires i32 member mask, i1 predicate, and i32 result"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::warp::all_sync"));
+    assert!(!importer.contains("cuda_device::warp::uni_sync"));
+    assert!(importer.contains("let vote = VoteSyncUniOp::build(ctx, member_mask, predicate)"));
+    assert!(importer.contains("set_generated_intrinsic_marker(ctx, vote, \"v1:i0043\")"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("impl MirToLlvmConversion for VoteSyncUniOp"));
+    assert!(lowering.contains("\"llvm_nvvm_vote_uni_sync\""));
+    assert!(lowering.contains("convert_vote(ctx, rewriter, self.get_operation(), operands_info"));
+
+    let record = vote_intrinsics(&catalog)
+        .find(|record| record.id == "ballot_sync")
+        .unwrap();
+    assert_eq!(record.selections.len(), 2);
+    let probe = render_probe(&catalog, record, "test-hash");
+    assert!(probe.contains("define i32 @probe_ballot_sync(i32 %member_mask, i1 %predicate)"));
+    assert!(probe.contains("define i32 @probe_ballot_sync_immediate(i1 %predicate)"));
+    assert!(probe.contains("i32 -1, i1 %predicate"));
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    for abi_id in ["i0040", "i0041", "i0042", "i0043"] {
+        assert!(raw.contains(&format!("pub unsafe fn {abi_id}")));
+    }
+    assert!(raw.contains("Every non-exited lane named in `mask`"));
+}
+
+#[test]
+fn active_mask_and_warp_match_rendering_preserves_backend_and_abi_contracts() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(active_masks(&catalog).count(), 1);
+    assert_eq!(warp_matches(&catalog).count(), 4);
+
+    let dialect = render_dialect_active_mask(&catalog, "test-hash");
+    assert!(dialect.contains("pub struct ActiveMaskOp"));
+    assert!(dialect.contains("NOpdsInterface<0>, NResultsInterface<1>"));
+
+    let match_dialect = render_dialect_warp_match(&catalog, "test-hash");
+    for op in [
+        "MatchAnySyncI32Op",
+        "MatchAnySyncI64Op",
+        "MatchAllSyncI32Op",
+        "MatchAllSyncI64Op",
+    ] {
+        assert!(match_dialect.contains(&format!("pub struct {op}")));
+        assert!(match_dialect.contains(&format!("{op}::register(ctx)")));
+    }
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("IntrinsicBackend::LlvmNvptx => {"));
+    assert!(lowering.contains("convert_active_mask(ctx, rewriter, op, operands_info)"));
+    assert!(lowering.contains("IntrinsicBackend::LibNvvm =>"));
+    assert!(lowering.contains("\"activemask.b32 $0;\""));
+    assert!(lowering.contains("\"=r,~{memory}\""));
+    assert!(lowering.contains("convert_match_any("));
+    assert!(lowering.contains("convert_match_all("));
+    assert!(lowering.contains("\"llvm_nvvm_match_all_sync_i64p\""));
+
+    let match_all = warp_matches(&catalog)
+        .find(|record| record.id == "match_all_sync")
+        .unwrap();
+    let probe = render_probe(&catalog, match_all, "test-hash");
+    for suffix in ["rr", "ri", "ir", "ii"] {
+        assert!(probe.contains(&format!("@probe_match_all_sync_{suffix}")));
+    }
+    assert!(probe.contains("declare { i32, i1 } @llvm.nvvm.match.all.sync.i32p"));
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("pub fn i0044() -> u32"));
+    assert!(!raw.contains("pub unsafe fn i0044() -> u32"));
+    assert!(raw.contains("pub unsafe fn i0045(_arg0: u32, _arg1: u32) -> u32"));
+    assert!(raw.contains("pub unsafe fn i0046(_arg0: u32, _arg1: u64) -> u32"));
+    assert!(raw.contains("pub unsafe fn i0047(_arg0: u32, _arg1: u32) -> u32"));
+    assert!(raw.contains("pub unsafe fn i0048(_arg0: u32, _arg1: u64) -> u32"));
+}
+
+#[test]
+fn warp_barrier_rendering_preserves_mask_and_void_contracts() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(warp_barriers(&catalog).count(), 1);
+
+    let record = warp_barriers(&catalog).next().unwrap();
+    assert_eq!(record.id, "sync_mask");
+    assert_eq!(
+        record.warp_barrier.as_ref().unwrap().adapter,
+        WarpBarrierAdapter::DirectMemberMask
+    );
+
+    let dialect_mod = render_dialect_mod(&catalog, "test-hash");
+    assert!(dialect_mod.contains("mod warp_barrier;"));
+    assert!(dialect_mod.contains("warp_barrier::register(ctx)"));
+
+    let dialect = render_dialect_warp_barrier(&catalog, "test-hash");
+    assert!(dialect.contains("pub struct BarWarpSyncOp"));
+    assert!(dialect.contains("NOpdsInterface<1>, NResultsInterface<0>"));
+    assert!(dialect.contains("vec![member_mask]"));
+    assert!(dialect.contains("op.get_num_operands() != 1 || op.get_num_results() != 0"));
+    assert!(dialect.contains("if !is_i32(ctx, op.get_operand(0).get_type(ctx))"));
+    assert!(dialect.contains("requires exactly one member-mask operand and no results"));
+    assert!(dialect.contains("member mask must be i32"));
+    assert!(dialect.contains("BarWarpSyncOp::register(ctx)"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::warp::sync_mask"));
+    assert!(importer.contains("let barrier = BarWarpSyncOp::build(ctx, member_mask)"));
+    assert!(importer.contains("set_generated_intrinsic_marker(ctx, barrier, \"v1:i0049\")"));
+    assert!(importer.contains("helpers::emit_goto(ctx, *target_idx, barrier"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("impl MirToLlvmConversion for BarWarpSyncOp"));
+    assert!(
+        lowering
+            .contains("convert_bar_warp_sync(ctx, rewriter, self.get_operation(), operands_info)")
+    );
+
+    let probe = render_probe(&catalog, record, "test-hash");
+    assert!(probe.contains("declare void @llvm.nvvm.bar.warp.sync(i32)"));
+    assert!(probe.contains("define void @probe_sync_mask(i32 %member_mask)"));
+    assert!(probe.contains("call void @llvm.nvvm.bar.warp.sync(i32 %member_mask)"));
+    assert!(probe.contains("define void @probe_sync_mask_immediate()"));
+    assert!(probe.contains("call void @llvm.nvvm.bar.warp.sync(i32 -1)"));
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("pub unsafe fn i0049(_arg0: u32) -> ()"));
+    assert!(raw.contains("On `sm_6x` and earlier"));
+    assert!(raw.contains("no lane outside `mask` may be active"));
+    assert!(raw.contains("The barrier orders memory accesses among participating lanes"));
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("## Warp-barrier contract"));
+    assert!(reference.contains("no unnamed lane may be active"));
+    assert!(reference.contains("Both immediate and register masks are admitted"));
+}
+
+#[test]
+fn warp_shuffle_rendering_owns_all_i32_f32_and_i64_modes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(warp_shuffles(&catalog).count(), 12);
+
+    let dialect_mod = render_dialect_mod(&catalog, "test-hash");
+    assert!(dialect_mod.contains("mod warp_shuffle;"));
+    assert!(dialect_mod.contains("warp_shuffle::register(ctx)"));
+
+    let dialect = render_dialect_warp_shuffle(&catalog, "test-hash");
+    for op in [
+        "ShflSyncIdxI32Op",
+        "ShflSyncBflyI32Op",
+        "ShflSyncDownI32Op",
+        "ShflSyncUpI32Op",
+        "ShflSyncIdxF32Op",
+        "ShflSyncBflyF32Op",
+        "ShflSyncDownF32Op",
+        "ShflSyncUpF32Op",
+        "ShflSyncIdxI64Op",
+        "ShflSyncBflyI64Op",
+        "ShflSyncDownI64Op",
+        "ShflSyncUpI64Op",
+    ] {
+        assert!(dialect.contains(&format!("pub struct {op}")));
+        assert!(dialect.contains(&format!("{op}::register(ctx)")));
+    }
+    assert!(dialect.contains("vec![member_mask, value, lane_or_delta]"));
+    assert!(dialect.contains("requires i32 mask/lane and i32 value/result"));
+    assert!(dialect.contains("requires i32 mask/lane and f32 value/result"));
+    assert!(dialect.contains("requires i32 mask/lane and i64 value/result"));
+    assert!(dialect.contains("fn is_i64"));
+    assert!(dialect.contains("integer.width() == 64"));
+    assert!(dialect.contains("IntegerType::get(ctx, 64, Signedness::Unsigned)"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::warp::shuffle_sync"));
+    assert!(importer.contains("cuda_device::warp::shuffle_up_f32_sync"));
+    assert!(
+        importer.contains(
+            "let shuffle = ShflSyncIdxI32Op::build(ctx, member_mask, value, lane_or_delta)"
+        )
+    );
+    assert!(importer.contains("set_generated_intrinsic_marker(ctx, shuffle, \"v1:i0050\")"));
+    for (name, op, marker) in [
+        ("shuffle_u64_sync", "ShflSyncIdxI64Op", "v1:i0058"),
+        ("shuffle_xor_u64_sync", "ShflSyncBflyI64Op", "v1:i0059"),
+        ("shuffle_down_u64_sync", "ShflSyncDownI64Op", "v1:i0060"),
+        ("shuffle_up_u64_sync", "ShflSyncUpI64Op", "v1:i0061"),
+    ] {
+        assert!(importer.contains(&format!(
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::{}",
+            marker.strip_prefix("v1:").unwrap()
+        )));
+        assert!(importer.contains(&format!("cuda_device::warp::{name}")));
+        assert!(importer.contains(&format!(
+            "let shuffle = {op}::build(ctx, member_mask, value, lane_or_delta)"
+        )));
+        assert!(importer.contains(&format!(
+            "set_generated_intrinsic_marker(ctx, shuffle, {marker:?})"
+        )));
+    }
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("impl MirToLlvmConversion for ShflSyncIdxI32Op"));
+    assert!(lowering.contains("convert_shuffle_i32(ctx, rewriter"));
+    assert!(lowering.contains("\"llvm_nvvm_shfl_sync_idx_i32\", 31)"));
+    assert!(lowering.contains("impl MirToLlvmConversion for ShflSyncUpF32Op"));
+    assert!(lowering.contains("convert_shuffle_f32(ctx, rewriter"));
+    assert!(lowering.contains("\"llvm_nvvm_shfl_sync_up_f32\", 0)"));
+
+    for (op, mode, clamp) in [
+        ("ShflSyncIdxI64Op", "idx", 31),
+        ("ShflSyncBflyI64Op", "bfly", 31),
+        ("ShflSyncDownI64Op", "down", 31),
+        ("ShflSyncUpI64Op", "up", 0),
+    ] {
+        assert!(lowering.contains(&format!("impl MirToLlvmConversion for {op}")));
+        assert!(lowering.contains(&format!(
+                "convert_shuffle_i64(ctx, rewriter, self.get_operation(), operands_info, {mode:?}, {clamp})"
+            )));
+    }
+    assert!(!lowering.contains("llvm_nvvm_shfl_sync_idx_i64"));
+    assert!(!lowering.contains("llvm_nvvm_shfl_sync_bfly_i64"));
+    assert!(!lowering.contains("llvm_nvvm_shfl_sync_down_i64"));
+    assert!(!lowering.contains("llvm_nvvm_shfl_sync_up_i64"));
+
+    for record in warp_shuffles(&catalog) {
+        let probe = render_probe(&catalog, record, "test-hash");
+        let shuffle = record.warp_shuffle.as_ref().unwrap();
+        if shuffle.value_kind == WarpShuffleValueKind::I64 {
+            let mode = match shuffle.mode {
+                WarpShuffleMode::Idx => "idx",
+                WarpShuffleMode::Bfly => "bfly",
+                WarpShuffleMode::Down => "down",
+                WarpShuffleMode::Up => "up",
+            };
+            let asm = format!(
+                "{{ .reg .b32 lo; .reg .b32 hi; mov.b64 {{lo, hi}}, $1; shfl.sync.{mode}.b32 lo, lo, $2, {}, $3; shfl.sync.{mode}.b32 hi, hi, $2, {}, $3; mov.b64 $0, {{lo, hi}}; }}",
+                shuffle.clamp, shuffle.clamp
+            );
+            assert!(probe.contains(&format!(
+                "define i64 @probe_{}(i32 %member_mask, i64 %value, i32 %lane) #0",
+                record.id
+            )));
+            assert!(probe.contains(&format!(
+                    "call i64 asm sideeffect {asm:?}, \"=l,l,r,r\"(i64 %value, i32 %lane, i32 %member_mask) #0"
+                )));
+            assert_eq!(probe.matches("asm sideeffect").count(), 1);
+            assert_eq!(probe.matches("attributes #0 = { convergent }").count(), 1);
+            assert!(!probe.contains("declare i64 @llvm.nvvm.shfl"));
+            for suffix in ["rr", "ri", "ir", "ii"] {
+                assert!(!probe.contains(&format!("@probe_{}_{suffix}", record.id)));
+            }
+        } else {
+            for suffix in ["rr", "ri", "ir", "ii"] {
+                assert!(probe.contains(&format!("@probe_{}_{suffix}", record.id)));
+            }
+            assert!(probe.contains(&format!(", i32 {})", shuffle.clamp)));
+        }
+    }
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("pub unsafe fn i0050(_arg0: u32, _arg1: u32, _arg2: u32) -> u32"));
+    assert!(raw.contains("pub unsafe fn i0057(_arg0: u32, _arg1: f32, _arg2: u32) -> f32"));
+    for abi_id in ["i0058", "i0059", "i0060", "i0061"] {
+        assert!(raw.contains(&format!(
+            "pub unsafe fn {abi_id}(_arg0: u32, _arg1: u64, _arg2: u32) -> u64"
+        )));
+    }
+    assert!(raw.contains("If the computed source lane is in range"));
+    assert!(raw.contains(
+        "If PTX marks the computed source out of range, the calling lane's input is copied"
+    ));
+    assert!(raw.contains("two `b32` shuffles in one convergent block"));
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("## Warp-shuffle contracts"));
+    assert!(reference.contains("inserts clamp `31` during lowering"));
+    assert!(reference.contains("inserts clamp `0` during lowering"));
+    assert!(reference.contains("One convergent, side-effecting inline-PTX block splits `i64`"));
+    assert!(reference.contains("PTX-native source; no LLVM record"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs"
+    )));
+}
+
+#[test]
+fn sync_rendering_keeps_barrier_and_threadfence_contracts_explicit() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    let record = sync_intrinsics(&catalog).next().unwrap();
+    assert_eq!(sync_intrinsics(&catalog).count(), 4);
+
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    assert!(raw.contains("pub unsafe fn i0034() -> ()"));
+    assert!(raw.contains("Every active thread in the CTA must reach the same barrier"));
+
+    let dialect = render_dialect_sync(&catalog, "test-hash");
+    assert!(dialect.contains("pub struct Barrier0Op"));
+    assert!(dialect.contains("NOpdsInterface<0>, NResultsInterface<0>"));
+    assert!(dialect.contains("Barrier0Op::register(ctx)"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    assert!(importer.contains("cuda_device::thread::sync_threads"));
+    assert!(importer.contains("cuda_device::sync_threads"));
+    assert!(importer.contains("Barrier0Op::get_concrete_op_info()"));
+    assert!(importer.contains("set_generated_intrinsic_marker(ctx, barrier, \"v1:i0034\")"));
+    assert!(importer.contains("helpers::emit_goto(ctx, *target_idx, barrier"));
+
+    let lowering = render_lowering(&catalog, "test-hash");
+    assert!(lowering.contains("impl MirToLlvmConversion for Barrier0Op"));
+    assert!(lowering.contains("create_i32_const(ctx, rewriter, 0)"));
+    assert!(lowering.contains("\"llvm_nvvm_barrier_cta_sync_aligned_all\""));
+    assert!(lowering.contains("IntrinsicBackend::LlvmNvptx"));
+    assert!(lowering.contains("IntrinsicBackend::LibNvvm"));
+    assert!(lowering.contains("\"bar.sync 0;\", \"~{memory}\""));
+
+    let probe = render_probe(&catalog, record, "test-hash");
+    assert!(probe.contains("declare void @llvm.nvvm.barrier.cta.sync.aligned.all(i32)"));
+    assert!(probe.contains("call void @llvm.nvvm.barrier.cta.sync.aligned.all(i32 0)"));
+
+    let targets = render_targets(&catalog, "test-hash");
+    assert!(targets.contains("id: \"sync_threads\", abi_id: \"i0034\""));
+    assert!(targets.contains("source_record: \"BARRIER_CTA_SYNC_ALIGNED_ALL_i\""));
+    assert!(targets.contains(
+            "backend: GeneratedIntrinsicBackend::LlvmNvptx, requirement: GeneratedTargetRequirement { minimum_ptx: GeneratedPtxVersion::from_encoded(32), hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }"
+        ));
+    assert!(targets.contains(
+            "backend: GeneratedIntrinsicBackend::LibNvvm, requirement: GeneratedTargetRequirement { minimum_ptx: GeneratedPtxVersion::from_encoded(10), hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }"
+        ));
+    assert!(
+        !record
+            .selections
+            .iter()
+            .any(|selection| selection.source_record.ends_with("_r"))
+    );
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/sync.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from("crates/cuda-device/src/generated/fence.rs")));
+
+    let compatibility = render_compat_fence(&catalog, "test-hash");
+    for (id, abi_id, op_type, op_name, llvm_identifier, ptx) in [
+        (
+            "threadfence_block",
+            "i0298",
+            "ThreadfenceBlockOp",
+            "nvvm.threadfence_block",
+            "llvm_nvvm_membar_cta",
+            "membar.cta;",
+        ),
+        (
+            "threadfence",
+            "i0299",
+            "ThreadfenceOp",
+            "nvvm.threadfence",
+            "llvm_nvvm_membar_gl",
+            "membar.gl;",
+        ),
+        (
+            "threadfence_system",
+            "i0300",
+            "ThreadfenceSystemOp",
+            "nvvm.threadfence_system",
+            "llvm_nvvm_membar_sys",
+            "membar.sys;",
+        ),
+    ] {
+        let record = sync_intrinsics(&catalog)
+            .find(|record| record.id == id)
+            .unwrap();
+        assert_eq!(record.rust.abi_id, abi_id);
+        assert!(compatibility.contains(&format!("pub fn {id}()")));
+        assert!(dialect.contains(&format!("pub struct {op_type}")));
+        assert!(dialect.contains(&format!("name = \"{op_name}\"")));
+        assert!(dialect.contains(&format!("{op_type}::register(ctx)")));
+        assert!(importer.contains(&format!("cuda_device::fence::{id}")));
+        assert!(importer.contains(&format!("cuda_device::{id}")));
+        assert!(importer.contains(&format!(
+            "set_generated_intrinsic_marker(ctx, barrier, \"v1:{abi_id}\")"
+        )));
+        assert!(lowering.contains(&format!("impl MirToLlvmConversion for {op_type}")));
+        assert!(lowering.contains(&format!("\"{llvm_identifier}\"")));
+
+        let probe = render_probe(&catalog, record, "test-hash");
+        assert!(probe.contains(&format!("declare void @{}()", llvm(record).symbol)));
+        assert!(probe.contains(&format!("call void @{}()", llvm(record).symbol)));
+        assert!(targets.contains(&format!("id: \"{id}\", abi_id: \"{abi_id}\"")));
+        assert!(targets.contains(&format!("asm: \"{ptx}\"")));
+    }
+    for ptx in ["membar.cta;", "membar.gl;", "membar.sys;"] {
+        assert!(!lowering.contains(&format!("\"{ptx}\"")));
+    }
+}
+
+#[test]
+fn basic_mbarrier_rendering_preserves_existing_paths_shapes_and_routes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    assert_eq!(mbarrier_basics(&catalog).count(), 4);
+
+    let compatibility = render_compat_mbarrier_basic(&catalog, "test-hash");
+    for signature in [
+        "pub unsafe fn mbarrier_init(bar: *mut Barrier, expected_count: u32)",
+        "pub unsafe fn mbarrier_arrive(bar: *const Barrier) -> u64",
+        "pub unsafe fn mbarrier_test_wait(bar: *const Barrier, token: u64) -> bool",
+        "pub unsafe fn mbarrier_inval(bar: *mut Barrier)",
+    ] {
+        assert!(compatibility.contains(signature));
+    }
+    assert!(compatibility.contains("eight-byte-aligned `Barrier` in shared memory"));
+    assert!(compatibility.contains("expected_count` must be in `1..=0xFFFFF`"));
+    let arrive = compatibility.find("pub unsafe fn mbarrier_arrive").unwrap();
+    assert!(compatibility[..arrive].ends_with("#[inline(never)]\n"));
+    assert!(!compatibility.contains("#[must_use]"));
+
+    let dialect_mod = render_dialect_mod(&catalog, "test-hash");
+    assert!(dialect_mod.contains("mod mbarrier_basic;"));
+    assert!(dialect_mod.contains("mbarrier_basic::register(ctx)"));
+    let dialect = render_dialect_mbarrier_basic(&catalog, "test-hash");
+    assert!(dialect.contains("address_space::GENERIC | address_space::SHARED"));
+    assert!(dialect.contains("mbarrier expected count must be u32"));
+    assert!(dialect.contains("mbarrier arrival token must be u64"));
+    assert!(dialect.contains("mbarrier test-wait requires a u64 token and i1 result"));
+
+    let importer = render_importer(&catalog, "test-hash");
+    let lowering = render_lowering(&catalog, "test-hash");
+    let targets = render_targets(&catalog, "test-hash");
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    for record in mbarrier_basics(&catalog) {
+        assert!(dialect.contains(&format!("pub struct {}", record.dialect.op_type)));
+        assert!(dialect.contains(&format!("{}::register(ctx)", record.dialect.op_type)));
+        assert!(importer.contains(&record.rust.canonical_path));
+        assert!(importer.contains(&format!(
+            "set_generated_intrinsic_marker(ctx, mbarrier, {:?})",
+            intrinsic_marker(&catalog, record)
+        )));
+        assert!(lowering.contains(&format!(
+            "impl MirToLlvmConversion for {}",
+            record.dialect.op_type
+        )));
+        assert!(targets.contains(&format!("id: {:?}", record.id)));
+        assert!(raw.contains(&format!("pub unsafe fn {}", record.rust.abi_id)));
+
+        let probe = render_probe(&catalog, record, "test-hash");
+        assert!(
+            probe.contains("%barrier = addrspacecast ptr %barrier_generic to ptr addrspace(3)")
+        );
+        let mbarrier = record.mbarrier_basic.as_ref().unwrap();
+        let llvm_route = record
+            .backend_lowerings
+            .iter()
+            .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+            .unwrap();
+        let libnvvm_route = record
+            .backend_lowerings
+            .iter()
+            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
+            .unwrap();
+        let expected_llvm_mechanism = match mbarrier.operation {
+            MbarrierBasicOperation::TestWait => BackendLoweringMechanism::InlinePtx,
+            _ => BackendLoweringMechanism::TypedNvvm,
+        };
+        assert_eq!(llvm_route.mechanism, expected_llvm_mechanism);
+        assert_eq!(libnvvm_route.mechanism, BackendLoweringMechanism::InlinePtx);
+        match mbarrier.operation {
+            MbarrierBasicOperation::Init => {
+                assert!(
+                    dialect.contains("MbarrierInitSharedOp::build(ctx, barrier, expected_count)")
+                        || importer
+                            .contains("MbarrierInitSharedOp::build(ctx, barrier, expected_count)")
+                );
+                assert!(
+                    lowering.contains(
+                        "convert_init(ctx, rewriter, self.get_operation(), operands_info)"
+                    )
+                );
+                assert!(probe.contains(&format!(
+                    "declare void @{}(ptr addrspace(3), i32)",
+                    llvm(record).symbol
+                )));
+            }
+            MbarrierBasicOperation::Arrive => {
+                assert!(importer.contains("MbarrierArriveSharedOp::build(ctx, barrier)"));
+                assert!(lowering.contains(
+                    "convert_arrive(ctx, rewriter, self.get_operation(), operands_info)"
+                ));
+                assert!(probe.contains(&format!(
+                    "declare i64 @{}(ptr addrspace(3))",
+                    llvm(record).symbol
+                )));
+            }
+            MbarrierBasicOperation::TestWait => {
+                assert!(importer.contains("MbarrierTestWaitSharedOp::build(ctx, barrier, token)"));
+                assert!(lowering.contains(
+                    "convert_test_wait(ctx, rewriter, self.get_operation(), operands_info)"
+                ));
+                assert!(probe.contains("mbarrier.test_wait.shared.b64"));
+                assert!(probe.contains("asm sideeffect"));
+                assert!(probe.contains("attributes #0 = { convergent }"));
+                assert!(!probe.contains(&format!("declare i1 @{}", llvm(record).symbol)));
+            }
+            MbarrierBasicOperation::Inval => {
+                assert!(importer.contains("MbarrierInvalSharedOp::build(ctx, barrier)"));
+                assert!(
+                    lowering.contains(
+                        "convert_inval(ctx, rewriter, self.get_operation(), operands_info)"
+                    )
+                );
+                assert!(probe.contains(&format!(
+                    "declare void @{}(ptr addrspace(3))",
+                    llvm(record).symbol
+                )));
+            }
+        }
+    }
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("## Basic mbarrier contracts"));
+    assert!(reference.contains("inline PTX on both backends"));
+    assert!(reference.contains("typed NVVM intrinsic with LLVM-NVPTX"));
+    assert!(reference.contains("inline PTX with libNVVM"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/mbarrier_basic.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs"
+    )));
+}
+
+#[test]
+fn extended_mbarrier_rendering_preserves_all_manual_contracts() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    validate_renderable(&catalog).unwrap();
+    let records = mbarrier_extended(&catalog).collect::<Vec<_>>();
+    assert_eq!(records.len(), 11);
+
+    let compatibility = render_compat_mbarrier_extended(&catalog, "test-hash");
+    for signature in [
+        "pub unsafe fn mbarrier_arrive_expect_tx(bar: *const Barrier, _tx_count: u32, bytes: u32) -> u64",
+        "pub unsafe fn mbarrier_arrive_expect_tx_cluster(bar: *const Barrier, _tx_count: u32, bytes: u32) -> u64",
+        "pub unsafe fn mbarrier_arrive_cluster(remote_bar_addr: u64)",
+        "pub unsafe fn mbarrier_try_wait(bar: *const Barrier, token: u64) -> bool",
+        "pub unsafe fn mbarrier_try_wait_parity(bar: *const Barrier, parity: u32) -> bool",
+        "pub unsafe fn mbarrier_try_wait_parity_cluster(bar: *const Barrier, parity: u32) -> bool",
+        "pub unsafe fn fence_proxy_async_shared_cta()",
+        "pub unsafe fn fence_mbarrier_init_release_cluster()",
+        "pub unsafe fn fence_proxy_async_generic_release_shared_cta_cluster()",
+        "pub unsafe fn fence_proxy_async_generic_acquire_shared_cluster_cluster()",
+        "pub unsafe fn nanosleep(ns: u32)",
+    ] {
+        assert!(compatibility.contains(signature), "missing {signature}");
+    }
+    assert!(!compatibility.contains("#[must_use]"));
+
+    let dialect_mod = render_dialect_mod(&catalog, "test-hash");
+    assert!(dialect_mod.contains("mod mbarrier_extended;"));
+    assert!(dialect_mod.contains("pub use mbarrier_extended::*;"));
+    assert!(dialect_mod.contains("mbarrier_extended::register(ctx);"));
+
+    let dialect = render_dialect_mbarrier_extended(&catalog, "test-hash");
+    let importer = render_importer(&catalog, "test-hash");
+    let lowering = render_lowering(&catalog, "test-hash");
+    let raw = render_raw_abi(&catalog, "test-hash").unwrap();
+    for record in &records {
+        assert!(dialect.contains(&format!("pub struct {}", record.dialect.op_type)));
+        assert!(dialect.contains(&format!("{}::register(ctx);", record.dialect.op_type)));
+        assert!(importer.contains(&record.rust.canonical_path));
+        assert!(importer.contains(&record.rust.compatibility_paths[0]));
+        assert!(lowering.contains(&format!(
+            "impl MirToLlvmConversion for {}",
+            record.dialect.op_type
+        )));
+        assert!(raw.contains(&format!("pub unsafe fn {}", record.rust.abi_id)));
+        for route in &record.backend_lowerings {
+            assert_eq!(route.mechanism, BackendLoweringMechanism::InlinePtx);
+        }
+        let (template, constraints) = crate::resolve::mbarrier_extended_inline_recipe(
+            record.mbarrier_extended.as_ref().unwrap().operation,
+        );
+        assert!(lowering.contains(&format!("{template:?}, {constraints:?}")));
+        let probe = render_probe(&catalog, record, "test-hash");
+        assert!(probe.contains("asm sideeffect"));
+        assert!(probe.contains(template));
+        assert!(probe.contains("~{memory}"));
+        assert!(probe.contains("attributes #0 = { convergent }"));
+    }
+
+    assert!(dialect.contains("address_space::GENERIC | address_space::SHARED"));
+    assert!(dialect.contains("mbarrier arrival requires u32 bytes and a u64 token"));
+    assert!(dialect.contains("mbarrier wait requires a u64 token and i1 result"));
+    assert!(dialect.contains("mbarrier wait requires u32 parity and i1 result"));
+    assert!(dialect.contains("remote mbarrier address must be u64"));
+    assert!(dialect.contains("nanosleep duration must be u32"));
+
+    assert!(importer.contains("MbarrierArriveExpectTxSharedOp::build(ctx, barrier, bytes)"));
+    assert!(importer.contains("MbarrierArriveExpectTxClusterOp::build(ctx, barrier, bytes)"));
+    assert!(
+        !importer.contains("MbarrierArriveExpectTxSharedOp::build(ctx, barrier, tx_count, bytes)")
+    );
+    assert!(importer.contains("MbarrierArriveClusterOp::build(ctx, address)"));
+    assert!(importer.contains("MbarrierTryWaitSharedOp::build(ctx, barrier, token)"));
+    assert!(importer.contains("MbarrierTryWaitParitySharedOp::build(ctx, barrier, parity)"));
+    assert!(importer.contains("MbarrierTryWaitParityClusterOp::build(ctx, barrier, parity)"));
+    assert!(importer.contains("FenceProxyAsyncSharedCtaOp::build(ctx)"));
+    assert!(importer.contains("FenceMbarrierInitReleaseClusterOp::build(ctx)"));
+    assert!(importer.contains("NanosleepOp::build(ctx, ns)"));
+
+    assert!(lowering.contains("cast_to_shared_addrspace"));
+    assert!(lowering.contains("trunc_to_i1"));
+    assert!(lowering.contains("DefiningEntity::Op(result_op)"));
+    assert!(lowering.contains("rewriter.erase_operation(ctx, op)"));
+    assert!(lowering.contains("mbarrier.arrive.release.cluster.shared::cluster.b64 _, [$0];"));
+    let remote = records
+        .iter()
+        .find(|record| record.id == "mbarrier_arrive_cluster")
+        .unwrap();
+    assert!(remote.llvm.is_none());
+    assert!(matches!(remote.source, IntrinsicSource::PtxNative { .. }));
+    assert!(!render_probe(&catalog, remote, "test-hash").contains("declare"));
+
+    let reference = render_reference(&catalog, "test-hash");
+    assert!(reference.contains("## Extended mbarrier contracts"));
+    assert!(reference.contains("LLVM 22 TableGen"));
+    assert!(reference.contains("PTX-native raw-address contract"));
+
+    let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap();
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/cuda-device/src/generated/mbarrier_extended.rs"
+    )));
+    assert!(outputs.contains_key(&PathBuf::from(
+        "crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs"
+    )));
+}
+
+#[test]
+fn lowering_imports_cast_to_shared_addrspace_exactly_once_across_families() {
+    // The stmatrix, cluster_memory, and mbarrier_extended families all pull
+    // the `cast_to_shared_addrspace` helper from `convert::intrinsics`. Each
+    // sharded lowering file must import the name at most once in the raw
+    // generator output (a duplicate inside one use group is a hard rustc
+    // error, E0252, that the rustfmt pass would silently dedupe), and every
+    // shard whose body calls the helper must import it exactly once.
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    assert!(stmatrices(&catalog).next().is_some());
+    assert!(cluster_memory(&catalog).next().is_some());
+    assert!(mbarrier_extended(&catalog).next().is_some());
+
+    let import_count = |contents: &str| {
+        // Everything before the first rendered item is the module header
+        // plus the use block; helper call sites in the item bodies below
+        // must not count.
+        let bodies_start = contents
+            .find("#[op_interface_impl]")
+            .or_else(|| contents.find("mod "))
+            .expect("lowering output must contain rendered items");
+        contents[..bodies_start]
+            .matches("cast_to_shared_addrspace")
+            .count()
+    };
+    let shard_import_count = |catalog: &CatalogFile, shard: &str| {
+        let files = render_lowering_files(catalog, "test-hash");
+        let (_, contents) = files
+            .iter()
+            .find(|(path, _)| path.ends_with(format!("{shard}.rs")))
+            .unwrap_or_else(|| panic!("missing lowering shard `{shard}`"));
+        import_count(contents)
+    };
+
+    for (path, contents) in render_lowering_files(&catalog, "test-hash") {
+        assert!(
+            import_count(&contents) <= 1,
+            "cast_to_shared_addrspace must be imported at most once in the \
+                 raw output of {}",
+            path.display()
+        );
+    }
+    // The shared stmatrix converter lives in mod.rs; the cluster_memory and
+    // mbarrier_extended impls call the helper directly in their own shards.
+    assert_eq!(shard_import_count(&catalog, "mod"), 1);
+    assert_eq!(shard_import_count(&catalog, "cluster_memory"), 1);
+    assert_eq!(shard_import_count(&catalog, "mbarrier_extended"), 1);
+
+    // Dropping stmatrix must not suppress the import where it is still
+    // needed: cluster_memory keeps using the helper.
+    let mut without_stmatrix = catalog;
+    without_stmatrix
+        .intrinsics
+        .retain(|record| record.family != "stmatrix");
+    assert!(stmatrices(&without_stmatrix).next().is_none());
+    assert_eq!(
+        shard_import_count(&without_stmatrix, "cluster_memory"),
+        1,
+        "cast_to_shared_addrspace must still be imported when only \
+             cluster_memory and mbarrier_extended need it"
+    );
+}
+
+#[test]
+fn elect_dialect_verifies_its_scalar_shape() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = crate::resolve::resolve(&repo_root).unwrap();
+    let dialect = render_dialect_elect(&catalog, "test-hash");
+
+    assert!(dialect.contains("impl Verify for ElectSyncOp"));
+    assert!(dialect.contains("is_integer_width(ctx, op.get_operand(0).get_type(ctx), 32)"));
+    assert!(dialect.contains("is_integer_width(ctx, op.get_result(0).get_type(ctx), 32)"));
+    assert!(dialect.contains("is_integer_width(ctx, op.get_result(1).get_type(ctx), 1)"));
+    assert!(!dialect.contains("verifier = \"succ\""));
+}
diff --git a/crates/cuda-intrinsics-gen/src/render/validate.rs b/crates/cuda-intrinsics-gen/src/render/validate.rs
new file mode 100644
index 0000000000..4b61703361
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/render/validate.rs
@@ -0,0 +1,1369 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogFile, CatalogHardwareAlternative, CatalogHardwareTarget,
+    ClcAdapter, ClcOperation, ClusterBarrierMode, ClusterBarrierOrdering, ClusterMemoryAdapter,
+    ClusterMemoryOperation, ClusterMemorySourceContract, CpAsyncMbarrierAdapter,
+    CpAsyncMbarrierStateSpace, DebugControlAdapter, DebugControlOperation,
+    ExecutionControlOperation, ExtendedMinMaxAdapter, ExtendedMinMaxFormat, IntegerMinMaxFormat,
+    IntrinsicBackend, IntrinsicSource, LdmatrixElement, MbarrierBasicAdapter,
+    MbarrierBasicOperation, MbarrierExtendedAdapter, MbarrierExtendedOperation,
+    MbarrierExtendedSourceContract, MbarrierStateSpace, RuntimeValidation, ScalarArithmeticFormat,
+    ScalarArithmeticOperation, ScalarMathFormat, SparseMmaAccumulator, SpecialRegisterObservation,
+    TmaAdapter, TmaOperation, WarpBarrierAdapter, WarpShuffleAdapter, WarpShuffleOperandEncoding,
+    WarpShuffleValueKind, WgmmaControlAdapter, WgmmaControlMode, WgmmaControlParticipation,
+};
+use crate::render::common::llvm;
+use crate::render::families::{
+    packed_alu_format_shape, packed_conversion_dialect_operands, packed_conversion_dialect_type,
+    packed_conversion_is_closed_recipe, packed_conversion_lowering_name,
+    packed_conversion_rust_arguments, packed_conversion_rust_type,
+    register_mma_extra_operand_count, sparse_mma_fragment_counts, stmatrix_variant,
+    tcgen05_render_contract, threadfence_ptx_level,
+};
+use anyhow::{Result, ensure};
+use std::collections::BTreeSet;
+
+pub(super) fn validate_renderable(catalog: &CatalogFile) -> Result<()> {
+    ensure!(
+        !catalog.intrinsics.is_empty(),
+        "catalog contains no intrinsics"
+    );
+    for record in &catalog.intrinsics {
+        match record.family.as_str() {
+            "sreg" => {
+                if let Some(special) = &record.special_register {
+                    ensure!(
+                        matches!(record.rust.module.as_str(), "debug" | "grid" | "thread" | "warp" | "shared")
+                            && record.rust.arguments.is_empty()
+                            && record.dialect.operands.is_empty()
+                            && record.dialect.results
+                                == [format!("i{}", special.result_width.bits())]
+                            && record.scalar_width() == Some(special.result_width.bits())
+                            && record.lowering == "generated_special_register"
+                            && record.backend_lowerings.len() == 2
+                            && record.semantics.pure
+                                == (special.observation
+                                    == SpecialRegisterObservation::StablePure),
+                        "{} is outside the closed generated special-register recipe",
+                        record.id
+                    );
+                } else {
+                    ensure!(
+                        record.rust.module == "sreg"
+                            && record.rust.arguments.is_empty()
+                            && llvm(record).arguments.is_empty()
+                            && record.lowering == "direct_nvvm"
+                            && record.scalar_width().is_some(),
+                        "{} is outside the zero-operand scalar direct-NVVM sreg recipe",
+                        record.id
+                    );
+                }
+            }
+            "ldmatrix" => ensure!(
+                record.rust.module == "matrix"
+                    && record.lowering == "generated_ldmatrix"
+                    && record.ldmatrix.as_ref().is_some_and(|ldmatrix| {
+                        record.rust.arguments
+                            == [if ldmatrix.variant.element == LdmatrixElement::B16 {
+                                "*const u32"
+                            } else {
+                                "*const u8"
+                            }]
+                    }),
+                "{} is outside the generated ldmatrix recipe",
+                record.id
+            ),
+            "stmatrix" => ensure!(
+                stmatrix_variant(record).is_some()
+                    && record.rust.module == "matrix"
+                    && !record.rust.safe
+                    && !record.rust.must_use
+                    && record.rust.result == "()"
+                    && record.dialect.results.is_empty()
+                    && record.llvm.as_ref().is_some_and(|llvm| llvm.results.is_empty())
+                    && record.semantics.memory == "write"
+                    && record.semantics.convergent
+                    && record.lowering == "generated_stmatrix",
+                "{} is outside the closed generated stmatrix recipe",
+                record.id
+            ),
+            "register_mma" => ensure!(
+                record.rust.module == "matrix"
+                    && record.rust.arguments.len() == 3 + register_mma_extra_operand_count(record)
+                    && !record.rust.safe
+                    && record.rust.must_use
+                    && record.semantics.memory == "none"
+                    && record.semantics.convergent
+                    && record.dialect.op_type == "RegisterMmaOp"
+                    && record.dialect.op_name == "nvvm.register_mma"
+                    && record.lowering == "generated_register_mma"
+                    && record.register_mma.is_some(),
+                "{} is outside the closed generated register-MMA recipe",
+                record.id
+            ),
+            "movmatrix" => ensure!(
+                record.rust.module == "matrix"
+                    && record.rust.arguments == ["u32"]
+                    && record.rust.result == "u32"
+                    && !record.rust.safe
+                    && record.rust.must_use
+                    && record.dialect.op_type == "MovmatrixTransB16Op"
+                    && record.dialect.op_name == "nvvm.movmatrix_trans_b16"
+                    && record.dialect.operands == ["i32"]
+                    && record.dialect.results == ["i32"]
+                    && !record.semantics.pure
+                    && record.semantics.memory == "inaccessible_read_write"
+                    && record.semantics.convergent
+                    && record.lowering == "generated_movmatrix_inline_ptx"
+                    && record.movmatrix.is_some(),
+                "{} is outside the generated movmatrix recipe",
+                record.id
+            ),
+            "sparse_mma" => {
+                ensure!(
+                    record.sparse_mma.is_some(),
+                    "{} is outside the closed generated sparse-MMA recipe",
+                    record.id
+                );
+                let (c_count, a_count, b_count, d_count) =
+                    sparse_mma_fragment_counts(record);
+                let accumulator = match record.sparse_mma.as_ref().unwrap().accumulator {
+                    SparseMmaAccumulator::F16 => "u32",
+                    SparseMmaAccumulator::F32 => "f32",
+                    SparseMmaAccumulator::S32 => "i32",
+                };
+                let arguments = [
+                    format!("[{accumulator}; {c_count}]"),
+                    format!("[u32; {a_count}]"),
+                    format!("[u32; {b_count}]"),
+                    "u32".to_owned(),
+                    "u32".to_owned(),
+                ];
+                ensure!(
+                    record.rust.module == "matrix"
+                        && record.rust.arguments == arguments
+                        && record.rust.result == format!("[{accumulator}; {d_count}]")
+                        && !record.rust.safe
+                        && record.rust.must_use
+                        && record.semantics.memory == "none"
+                        && record.semantics.convergent
+                        && record.dialect.op_type == "SparseMmaOp"
+                        && record.dialect.op_name == "nvvm.sparse_mma"
+                        && record.lowering == "generated_sparse_mma"
+                        && record.sparse_mma.is_some(),
+                    "{} is outside the closed generated sparse-MMA recipe",
+                    record.id
+                )
+            }
+            "packed_atomic" => ensure!(
+                record.rust.module == "atomic"
+                    && record.rust.arguments == ["*mut u32", "u32"]
+                    && record.rust.result == "u32"
+                    && record.rust.must_use
+                    && record.llvm.is_none()
+                    && record.lowering == "generated_packed_atomic_inline_ptx"
+                    && record.packed_atomic.is_some(),
+                "{} is outside the closed generated packed-atomic recipe",
+                record.id
+            ),
+            "redux" => ensure!(
+                record.rust.module == "warp"
+                    && matches!(record.rust.arguments.as_slice(), [mask, value]
+                        if mask == "u32" && value == &record.rust.result)
+                    && matches!(record.rust.result.as_str(), "u32" | "i32" | "f32")
+                    && !record.rust.safe
+                    && matches!(record.dialect.results.as_slice(), [result]
+                        if matches!(result.as_str(), "i32" | "f32"))
+                    && matches!(record.dialect.results.as_slice(), [result]
+                        if record.llvm.as_ref().is_some_and(|llvm| {
+                            llvm.arguments == [result.as_str(), "i32"]
+                                && llvm.results == [result.as_str()]
+                        }) && record.dialect.operands == ["i32", result.as_str()])
+                    && record.lowering == "generated_redux"
+                    && record.redux.is_some(),
+                "{} is outside the closed generated redux recipe",
+                record.id
+            ),
+            "dotprod" => ensure!(
+                record.rust.module == "dotprod"
+                    && matches!(record.rust.arguments.as_slice(), [a, b, c]
+                        if a == "u32" && b == "u32" && matches!(c.as_str(), "u32" | "i32"))
+                    && record.rust.result == *record.rust.arguments.last().unwrap()
+                    && record.rust.safe
+                    && !record.rust.must_use
+                    && record.llvm.as_ref().is_some_and(|llvm| {
+                        llvm.results == ["i32"]
+                            && (matches!(llvm.arguments.as_slice(), [a, b, c]
+                                if a == "i32" && b == "i32" && c == "i32")
+                                || matches!(llvm.arguments.as_slice(), [a, b, selector, c]
+                                    if a == "i32" && b == "i32" && selector == "i1" && c == "i32"))
+                    })
+                    && record.dialect.operands == ["i32", "i32", "i32"]
+                    && record.dialect.results == ["i32"]
+                    && record.lowering == "generated_dotprod"
+                    && record.dot_product.is_some(),
+                "{} is outside the closed generated dot-product recipe",
+                record.id
+            ),
+            "packed_alu" => ensure!(
+                record.packed_alu.as_ref().is_some_and(|packed| {
+                    let (module, must_use, rust_type, dialect_type, adapter) =
+                        packed_alu_format_shape(packed.format);
+                    record.rust.module == module
+                        && record.rust.must_use == must_use
+                        && packed.adapter == adapter
+                        && record
+                            .rust
+                            .arguments
+                            .iter()
+                            .all(|argument| argument == rust_type)
+                        && record.rust.result == rust_type
+                        && record
+                            .dialect
+                            .operands
+                            .iter()
+                            .all(|operand| operand == dialect_type)
+                        && record.dialect.results == [dialect_type]
+                })
+                    && (1..=3).contains(&record.rust.arguments.len())
+                    && record.rust.safe
+                    && record.dialect.operands.len() == record.rust.arguments.len()
+                    && record.lowering == "generated_packed_alu_inline_ptx",
+                "{} is outside the closed generated packed-ALU recipe",
+                record.id
+            ),
+            "packed_conversion" => ensure!(
+                record.rust.module == "convert"
+                    && record.rust.arguments == packed_conversion_rust_arguments(record)
+                    && record.rust.result == packed_conversion_rust_type(record)
+                    && record.rust.safe
+                    && !record.rust.must_use
+                    && record.dialect.operands == packed_conversion_dialect_operands(record)
+                    && record.dialect.results == [packed_conversion_dialect_type(record)]
+                    && record.lowering == packed_conversion_lowering_name(record)
+                    && record
+                        .packed_conversion
+                        .as_ref()
+                        .is_some_and(packed_conversion_is_closed_recipe),
+                "{} is outside the closed generated packed-conversion recipe",
+                record.id
+            ),
+            "scalar_conversion" => ensure!(
+                record.rust.module == "convert"
+                    && record.rust.arguments == ["f32"]
+                    && record.rust.result == "u32"
+                    && record.rust.safe
+                    && record.rust.must_use
+                    && record.dialect.op_type == "ScalarConversionOp"
+                    && record.dialect.op_name == "nvvm.scalar_conversion"
+                    && record.dialect.operands == ["f32"]
+                    && record.dialect.results == ["i32"]
+                    && record.lowering == "generated_scalar_conversion"
+                    && record.scalar_conversion.is_some(),
+                "{} is outside the closed generated scalar-conversion recipe",
+                record.id
+            ),
+            "scalar_arithmetic" => ensure!(
+                record.scalar_arithmetic.as_ref().is_some_and(|arithmetic| {
+                    let ty = match arithmetic.format {
+                        ScalarArithmeticFormat::F32 => "f32",
+                        ScalarArithmeticFormat::F64 => "f64",
+                    };
+                    let arity = match arithmetic.operation {
+                        ScalarArithmeticOperation::Mul
+                        | ScalarArithmeticOperation::Div
+                        | ScalarArithmeticOperation::Add => 2,
+                        ScalarArithmeticOperation::Fma => 3,
+                    };
+                    record.rust.arguments == vec![ty; arity]
+                        && record.rust.result == ty
+                        && record.dialect.operands == vec![ty; arity]
+                        && record.dialect.results == [ty]
+                        && record.semantics.pure
+                            == (arithmetic.operation != ScalarArithmeticOperation::Div)
+                })
+                    && record.rust.module == "float"
+                    && record.rust.safe
+                    && record.rust.must_use
+                    && record.dialect.op_type == "ScalarArithmeticOp"
+                    && record.dialect.op_name == "nvvm.scalar_arithmetic"
+                    && record.semantics.memory == "none"
+                    && !record.semantics.convergent
+                    && record.lowering == "generated_scalar_arithmetic",
+                "{} is outside the closed generated scalar-arithmetic recipe",
+                record.id
+            ),
+            "scalar_math" => ensure!(
+                record.scalar_math.as_ref().is_some_and(|math| {
+                    let (rust_ty, dialect_ty) = match math.format {
+                        ScalarMathFormat::F16 => ("u16", "i16"),
+                        ScalarMathFormat::F32 => ("f32", "f32"),
+                        ScalarMathFormat::F64 => ("f64", "f64"),
+                    };
+                    record.rust.arguments == [rust_ty]
+                        && record.rust.result == rust_ty
+                        && record.dialect.operands == [dialect_ty]
+                        && record.dialect.results == [dialect_ty]
+                        && record.semantics.pure
+                })
+                    && record.rust.module == "float"
+                    && record.rust.safe
+                    && record.rust.must_use
+                    && record.dialect.op_type == "ScalarMathOp"
+                    && record.dialect.op_name == "nvvm.scalar_math"
+                    && record.semantics.memory == "none"
+                    && !record.semantics.convergent
+                    && record.lowering == "generated_scalar_math",
+                "{} is outside the closed generated scalar-math recipe",
+                record.id
+            ),
+            "extended_minmax" => ensure!(
+                record.extended_minmax.as_ref().is_some_and(|minmax| {
+                    let (module, rust_type, dialect_type, adapter) = match minmax.format {
+                        ExtendedMinMaxFormat::F32 => (
+                            "float",
+                            "f32",
+                            "f32",
+                            ExtendedMinMaxAdapter::DirectF32,
+                        ),
+                        ExtendedMinMaxFormat::F16 => (
+                            "f16",
+                            "u16",
+                            "i16",
+                            ExtendedMinMaxAdapter::DirectHalfU16,
+                        ),
+                        ExtendedMinMaxFormat::Bf16 => (
+                            "bf16",
+                            "u16",
+                            "i16",
+                            ExtendedMinMaxAdapter::DirectHalfU16,
+                        ),
+                        ExtendedMinMaxFormat::F16x2 => (
+                            "f16x2",
+                            "u32",
+                            "i32",
+                            ExtendedMinMaxAdapter::DirectPackedU32,
+                        ),
+                        ExtendedMinMaxFormat::Bf16x2 => (
+                            "bf16x2",
+                            "u32",
+                            "i32",
+                            ExtendedMinMaxAdapter::DirectPackedU32,
+                        ),
+                    };
+                    record.rust.module == module
+                        && record.rust.arguments == [rust_type, rust_type]
+                        && record.rust.result == rust_type
+                        && record.dialect.operands == [dialect_type, dialect_type]
+                        && record.dialect.results == [dialect_type]
+                        && minmax.adapter == adapter
+                })
+                    && record.rust.safe
+                    && record.rust.must_use
+                    && record.dialect.op_type == "ExtendedMinMaxOp"
+                    && record.dialect.op_name == "nvvm.extended_minmax"
+                    && record.semantics.pure
+                    && record.semantics.memory == "none"
+                    && !record.semantics.convergent
+                    && record.lowering == "generated_extended_minmax",
+                "{} is outside the closed generated extended-minmax recipe",
+                record.id
+            ),
+            "prmt" => ensure!(
+                record.rust.module == "prmt"
+                    && matches!(record.rust.arguments.len(), 2 | 3)
+                    && record.rust.arguments.iter().all(|argument| argument == "u32")
+                    && record.rust.result == "u32"
+                    && record.rust.safe
+                    && record.rust.must_use
+                    && record.dialect.op_type == "PrmtOp"
+                    && record.dialect.op_name == "nvvm.prmt"
+                    && record.dialect.operands.len() == record.rust.arguments.len()
+                    && record.dialect.operands.iter().all(|operand| operand == "i32")
+                    && record.dialect.results == ["i32"]
+                    && record.lowering == "generated_prmt"
+                    && record.prmt.is_some(),
+                "{} is outside the closed generated prmt recipe",
+                record.id
+            ),
+            "cluster_barrier" => ensure!(
+                matches!(
+                    record.id.as_str(),
+                    "barrier_cluster_arrive"
+                        | "barrier_cluster_arrive_aligned"
+                        | "barrier_cluster_arrive_relaxed"
+                        | "barrier_cluster_arrive_relaxed_aligned"
+                        | "barrier_cluster_wait"
+                        | "barrier_cluster_wait_aligned"
+                )
+                    && record.rust.module == "cluster"
+                    && record.rust.arguments.is_empty()
+                    && record.rust.result == "()"
+                    && !record.rust.safe
+                    && !record.rust.must_use
+                    && record.dialect.op_type == "ClusterBarrierOp"
+                    && record.dialect.op_name == "nvvm.cluster_barrier"
+                    && record.dialect.operands.is_empty()
+                    && record.dialect.results.is_empty()
+                    && record.llvm.as_ref().is_some_and(|llvm| {
+                        llvm.arguments.is_empty() && llvm.results.is_empty()
+                    })
+                    && record.cluster_barrier.as_ref().is_some_and(|barrier| {
+                        matches!(
+                            (barrier.mode, barrier.ordering, barrier.aligned),
+                            (
+                                ClusterBarrierMode::Arrive,
+                                ClusterBarrierOrdering::Release,
+                                false
+                            ) | (
+                                ClusterBarrierMode::ArriveAligned,
+                                ClusterBarrierOrdering::Release,
+                                true
+                            ) | (
+                                ClusterBarrierMode::ArriveRelaxed,
+                                ClusterBarrierOrdering::Relaxed,
+                                false
+                            ) | (
+                                ClusterBarrierMode::ArriveRelaxedAligned,
+                                ClusterBarrierOrdering::Relaxed,
+                                true
+                            ) | (
+                                ClusterBarrierMode::Wait,
+                                ClusterBarrierOrdering::Acquire,
+                                false
+                            ) | (
+                                ClusterBarrierMode::WaitAligned,
+                                ClusterBarrierOrdering::Acquire,
+                                true
+                            )
+                        )
+                    })
+                    && record.lowering == "generated_cluster_barrier",
+                "{} is outside the closed generated cluster-barrier recipe",
+                record.id
+            ),
+            "cluster_memory" => ensure!(
+                record.rust.module == "cluster"
+                    && !record.rust.safe
+                    && record.rust.must_use
+                    && record.semantics.convergent
+                    && record.semantics.execution_scope == "cluster"
+                    && record.target.minimum_ptx.to_string() == "7.8"
+                    && matches!(
+                        &record.target.hardware,
+                        CatalogHardwareTarget::AnyOf { alternatives }
+                            if alternatives.as_slice()
+                                == [CatalogHardwareAlternative::MinimumSm { sm: 90 }]
+                    )
+                    && record.lowering == "generated_cluster_memory_inline_ptx"
+                    && record.backend_lowerings.len() == 2
+                    && record.backend_lowerings.iter().all(|lowering| {
+                        lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                            && lowering.target.minimum_ptx.to_string() == "7.8"
+                            && matches!(
+                                &lowering.target.hardware,
+                                CatalogHardwareTarget::AnyOf { alternatives }
+                                    if alternatives.as_slice()
+                                        == [CatalogHardwareAlternative::MinimumSm { sm: 90 }]
+                            )
+                    })
+                    && record.cluster_memory.as_ref().is_some_and(|cluster| {
+                        cluster.runtime_validation == RuntimeValidation::Unexecuted
+                            && match (cluster.operation, cluster.adapter, cluster.source_contract) {
+                                (
+                                    ClusterMemoryOperation::MapSharedRank,
+                                    ClusterMemoryAdapter::GenericConstAndMutPointerRankToSamePointer,
+                                    ClusterMemorySourceContract::LlvmMapaSharedClusterAs7IdentityInlinePtx,
+                                ) => {
+                                    record.id == "map_shared_rank"
+                                        && record.rust.arguments == ["*const u8", "u32"]
+                                        && record.rust.result == "*const u8"
+                                        && record.rust.compatibility_paths
+                                            == [
+                                                "cuda_device::cluster::map_shared_rank",
+                                                "cuda_device::cluster::map_shared_rank_mut",
+                                            ]
+                                        && record.dialect.op_type == "MapaSharedClusterOp"
+                                        && record.dialect.op_name == "nvvm.mapa_shared_cluster"
+                                        && record.dialect.operands == ["ptr", "i32"]
+                                        && record.dialect.results == ["ptr"]
+                                        && record.semantics.memory == "none"
+                                        && matches!(
+                                            record.source,
+                                            IntrinsicSource::LlvmImported { ref source_record }
+                                                if source_record == "int_nvvm_mapa_shared_cluster"
+                                        )
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.symbol == "llvm.nvvm.mapa.shared.cluster"
+                                                && llvm.arguments == ["shared_ptr", "i32"]
+                                                && llvm.results == ["shared_cluster_ptr"]
+                                                && llvm.properties
+                                                    == [
+                                                        "IntrNoMem",
+                                                        "IntrSpeculatable",
+                                                        "NoCapture<arg0>",
+                                                    ]
+                                        })
+                                        && record
+                                            .selections
+                                            .iter()
+                                            .map(|selection| selection.source_record.as_str())
+                                            .collect::<BTreeSet<_>>()
+                                            == BTreeSet::from([
+                                                "mapa_shared_cluster_64",
+                                                "mapa_shared_cluster_64i",
+                                            ])
+                                }
+                                (
+                                    ClusterMemoryOperation::ReadU32,
+                                    ClusterMemoryAdapter::ConstU32PointerRankToU32,
+                                    ClusterMemorySourceContract::PtxNativeMapaThenWeakClusterLoad,
+                                ) => {
+                                    record.id == "dsmem_read_u32"
+                                        && record.rust.arguments == ["*const u32", "u32"]
+                                        && record.rust.result == "u32"
+                                        && record.rust.compatibility_paths
+                                            == ["cuda_device::cluster::dsmem_read_u32"]
+                                        && record.dialect.op_type == "DsmemReadU32Op"
+                                        && record.dialect.op_name == "nvvm.dsmem_read_u32"
+                                        && record.dialect.operands == ["ptr", "i32"]
+                                        && record.dialect.results == ["i32"]
+                                        && record.semantics.memory == "read"
+                                        && record.llvm.is_none()
+                                        && record.selections.is_empty()
+                                        && matches!(
+                                            record.source,
+                                            IntrinsicSource::PtxNative { ref instruction }
+                                                if instruction
+                                                    == "mapa.shared::cluster.u64 + ld.shared::cluster.u32"
+                                        )
+                                }
+                                _ => false,
+                            }
+                    }),
+                "{} is outside the closed generated cluster-memory recipe",
+                record.id
+            ),
+            "debug_control" => ensure!(
+                record.rust.module == "debug"
+                    && record.rust.safe
+                    && !record.rust.must_use
+                    && record.dialect.operands.is_empty()
+                    && record.dialect.results.is_empty()
+                    && record.llvm.is_none()
+                    && record.lowering == "generated_debug_control"
+                    && record.debug_control.as_ref().is_some_and(|debug| {
+                        debug.runtime_validation == RuntimeValidation::Unexecuted
+                            && match debug.operation {
+                                DebugControlOperation::Trap => {
+                                    debug.adapter == DebugControlAdapter::Direct
+                                        && record.rust.arguments.is_empty()
+                                        && record.rust.result == "!"
+                                        && record.dialect.op_type == "TrapOp"
+                                        && record.dialect.op_name == "nvvm.trap"
+                                }
+                                DebugControlOperation::Breakpoint => {
+                                    debug.adapter == DebugControlAdapter::Direct
+                                        && record.rust.arguments.is_empty()
+                                        && record.rust.result == "()"
+                                        && record.dialect.op_type == "BreakpointOp"
+                                        && record.dialect.op_name == "nvvm.brkpt"
+                                }
+                                DebugControlOperation::Pmevent => {
+                                    debug.adapter
+                                        == DebugControlAdapter::ConstGenericToImmediateU32
+                                        && record.rust.arguments == ["u32"]
+                                        && record.rust.result == "()"
+                                        && record.dialect.op_type == "PmEventOp"
+                                        && record.dialect.op_name == "nvvm.pmevent"
+                                }
+                            }
+                    }),
+                "{} is outside the closed generated debug-control recipe",
+                record.id
+            ),
+            "clc" => ensure!(
+                record.rust.module == "clc"
+                    && !record.rust.safe
+                    && !record.rust.must_use
+                    && record.lowering == "generated_clc"
+                    && record.llvm.is_some()
+                    && record.clc.as_ref().is_some_and(|clc| {
+                        clc.runtime_validation == RuntimeValidation::Unexecuted
+                            && match (clc.operation, clc.adapter) {
+                                (
+                                    ClcOperation::TryCancel
+                                    | ClcOperation::TryCancelMulticast,
+                                    ClcAdapter::GenericPointersToShared,
+                                ) => {
+                                    record.rust.arguments == ["*mut u8", "*mut u64"]
+                                        && record.rust.result == "()"
+                                        && record.dialect.operands == ["ptr", "ptr"]
+                                        && record.dialect.results.is_empty()
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.arguments == ["shared_ptr", "shared_ptr"]
+                                                && llvm.results.is_empty()
+                                        })
+                                }
+                                (
+                                    ClcOperation::QueryIsCanceled,
+                                    ClcAdapter::PairU64ToI128BoolToU32,
+                                ) => {
+                                    record.rust.arguments == ["u64", "u64"]
+                                        && record.rust.result == "u32"
+                                        && record.dialect.operands == ["i64", "i64"]
+                                        && record.dialect.results == ["i32"]
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.arguments == ["i128"]
+                                                && llvm.results == ["i1"]
+                                        })
+                                }
+                                (
+                                    ClcOperation::QueryGetFirstCtaidX
+                                    | ClcOperation::QueryGetFirstCtaidY
+                                    | ClcOperation::QueryGetFirstCtaidZ,
+                                    ClcAdapter::PairU64ToI128U32,
+                                ) => {
+                                    record.rust.arguments == ["u64", "u64"]
+                                        && record.rust.result == "u32"
+                                        && record.dialect.operands == ["i64", "i64"]
+                                        && record.dialect.results == ["i32"]
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.arguments == ["i128"]
+                                                && llvm.results == ["i32"]
+                                        })
+                                }
+                                _ => false,
+                            }
+                    }),
+                "{} is outside the closed generated CLC recipe",
+                record.id
+            ),
+            "wgmma_control" => ensure!(
+                record.rust.module == "wgmma"
+                    && record.rust.result == "()"
+                    && !record.rust.safe
+                    && !record.rust.must_use
+                    && record.dialect.results.is_empty()
+                    && record.llvm.as_ref().is_some_and(|llvm| llvm.results.is_empty())
+                    && !record.semantics.pure
+                    && record.semantics.memory == "read_write"
+                    && record.semantics.convergent
+                    && record.semantics.execution_scope == "warpgroup"
+                    && record.target.minimum_ptx.encoded() == 80
+                    && record.target.hardware
+                        == CatalogHardwareTarget::AnyOf {
+                            alternatives: vec![CatalogHardwareAlternative::ExactArchitecture {
+                                sm: 90,
+                            }],
+                        }
+                    && record.backend_lowerings.len() == 2
+                    && record.backend_lowerings.iter().any(|lowering| {
+                        lowering.backend == IntrinsicBackend::LlvmNvptx
+                            && lowering.mechanism == BackendLoweringMechanism::TypedNvvm
+                    })
+                    && record.backend_lowerings.iter().any(|lowering| {
+                        lowering.backend == IntrinsicBackend::LibNvvm
+                            && lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                    })
+                    && record.lowering == "generated_wgmma_control"
+                    && record.wgmma_control.as_ref().is_some_and(|control| {
+                        control.participation
+                            == WgmmaControlParticipation::WarpgroupAllThreadsSameInstruction
+                            && match control.mode {
+                                WgmmaControlMode::Fence => {
+                                    control.adapter == WgmmaControlAdapter::NoArguments
+                                        && record.id == "wgmma_fence"
+                                        && record.rust.arguments.is_empty()
+                                        && record.dialect.op_type == "WgmmaFenceSyncAlignedOp"
+                                        && record.dialect.op_name
+                                            == "nvvm.wgmma_fence_sync_aligned"
+                                        && record.dialect.operands.is_empty()
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.arguments.is_empty()
+                                        })
+                                }
+                                WgmmaControlMode::CommitGroup => {
+                                    control.adapter == WgmmaControlAdapter::NoArguments
+                                        && record.id == "wgmma_commit_group"
+                                        && record.rust.arguments.is_empty()
+                                        && record.dialect.op_type
+                                            == "WgmmaCommitGroupSyncAlignedOp"
+                                        && record.dialect.op_name
+                                            == "nvvm.wgmma_commit_group_sync_aligned"
+                                        && record.dialect.operands.is_empty()
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.arguments.is_empty()
+                                        })
+                                }
+                                WgmmaControlMode::WaitGroup => {
+                                    control.adapter
+                                        == WgmmaControlAdapter::ConstGenericU32ToI64Immediate
+                                        && record.id == "wgmma_wait_group"
+                                        && record.rust.arguments == ["u64"]
+                                        && record.rust.compatibility_paths
+                                            == ["cuda_device::wgmma::__wgmma_wait_group"]
+                                        && record.dialect.op_type
+                                            == "WgmmaWaitGroupSyncAlignedOp"
+                                        && record.dialect.op_name
+                                            == "nvvm.wgmma_wait_group_sync_aligned"
+                                        && record.dialect.operands == ["i64"]
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.arguments == ["i64"]
+                                        })
+                                }
+                            }
+                    }),
+                "{} is outside the closed generated WGMMA-control recipe",
+                record.id
+            ),
+            "tma" => ensure!(
+                record.rust.module == "tma"
+                    && record.rust.result == "()"
+                    && !record.rust.must_use
+                    && record.dialect.results.is_empty()
+                    && record.llvm.as_ref().is_some_and(|llvm| llvm.results.is_empty())
+                    && record.lowering == "generated_tma"
+                    && record.tma.as_ref().is_some_and(|tma| {
+                        tma.runtime_validation == RuntimeValidation::Unexecuted
+                            && match (tma.operation, tma.adapter) {
+                                (
+                                    TmaOperation::G2sTile1d
+                                    | TmaOperation::G2sTile2d
+                                    | TmaOperation::G2sTile3d
+                                    | TmaOperation::G2sTile4d
+                                    | TmaOperation::G2sTile5d,
+                                    TmaAdapter::G2sPointersCoordinatesBarrierInjectDefaults,
+                                ) => {
+                                    !record.rust.safe
+                                        && record.semantics.convergent
+                                        && record.semantics.memory == "read_write"
+                                }
+                                (
+                                    TmaOperation::G2sTile2dMulticast
+                                    | TmaOperation::G2sTile2dMulticastCg2,
+                                    TmaAdapter::G2sPointersCoordinatesBarrierMaskInjectDefaults,
+                                ) => {
+                                    !record.rust.safe
+                                        && record.semantics.convergent
+                                        && record.semantics.memory == "read_write"
+                                }
+                                (
+                                    TmaOperation::S2gTile1d
+                                    | TmaOperation::S2gTile2d
+                                    | TmaOperation::S2gTile3d
+                                    | TmaOperation::S2gTile4d
+                                    | TmaOperation::S2gTile5d,
+                                    TmaAdapter::S2gPointersCoordinatesInjectDefaults,
+                                ) => {
+                                    !record.rust.safe
+                                        && record.semantics.convergent
+                                        && record.semantics.memory == "read_write"
+                                }
+                                (
+                                    TmaOperation::Reduce,
+                                    TmaAdapter::ReductionPointersCoordinatesInjectDefaults,
+                                ) => {
+                                    !record.rust.safe
+                                        && record.semantics.convergent
+                                        && record.semantics.memory == "read_write"
+                                        && tma.reduction.is_some()
+                                }
+                                (TmaOperation::CommitGroup, TmaAdapter::NoOperands) => {
+                                    record.rust.safe
+                                        && !record.semantics.convergent
+                                        && record.semantics.memory == "read_write"
+                                }
+                                (
+                                    TmaOperation::WaitGroup | TmaOperation::WaitGroupRead,
+                                    TmaAdapter::CompileTimeConstantMaxPending,
+                                ) => {
+                                    record.rust.safe
+                                        && !record.semantics.convergent
+                                        && record.semantics.memory == "read_write"
+                                }
+                                (
+                                    TmaOperation::PrefetchTensorMap,
+                                    TmaAdapter::DescriptorPointer,
+                                ) => {
+                                    !record.rust.safe
+                                        && !record.semantics.convergent
+                                        && record.semantics.memory == "read"
+                                }
+                                (
+                                    TmaOperation::PrefetchTile1d
+                                    | TmaOperation::PrefetchTile2d
+                                    | TmaOperation::PrefetchTile3d
+                                    | TmaOperation::PrefetchTile4d
+                                    | TmaOperation::PrefetchTile5d
+                                    | TmaOperation::PrefetchTileGather4TwoDimensional,
+                                    TmaAdapter::DescriptorCoordinatesInjectDefaults,
+                                ) => {
+                                    !record.rust.safe
+                                        && record.semantics.convergent
+                                        && record.semantics.memory == "read"
+                                }
+                                (
+                                    TmaOperation::PrefetchTile1dCacheHint
+                                    | TmaOperation::PrefetchTile2dCacheHint
+                                    | TmaOperation::PrefetchTile3dCacheHint
+                                    | TmaOperation::PrefetchTile4dCacheHint
+                                    | TmaOperation::PrefetchTile5dCacheHint
+                                    | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint,
+                                    TmaAdapter::DescriptorCoordinatesCacheHintInjectFlag,
+                                ) => {
+                                    !record.rust.safe
+                                        && record.semantics.convergent
+                                        && record.semantics.memory == "read"
+                                }
+                                (
+                                    TmaOperation::ReplaceGlobalAddress,
+                                    TmaAdapter::DescriptorAndAddressPointers,
+                                )
+                                | (
+                                    TmaOperation::ReplaceBoxDim
+                                    | TmaOperation::ReplaceElementStride
+                                    | TmaOperation::ReplaceGlobalDim,
+                                    TmaAdapter::DescriptorOrdinalAndU32,
+                                )
+                                | (
+                                    TmaOperation::ReplaceGlobalStride,
+                                    TmaAdapter::DescriptorOrdinalAndU64,
+                                )
+                                | (
+                                    TmaOperation::ReplaceElementType
+                                    | TmaOperation::ReplaceFillMode
+                                    | TmaOperation::ReplaceInterleaveLayout
+                                    | TmaOperation::ReplaceSwizzleAtomicity
+                                    | TmaOperation::ReplaceSwizzleMode,
+                                    TmaAdapter::DescriptorAndImmediateU32,
+                                )
+                                | (
+                                    TmaOperation::ReplaceRank,
+                                    TmaAdapter::DescriptorAndRuntimeU32,
+                                ) => {
+                                    !record.rust.safe
+                                        && !record.semantics.convergent
+                                        && record.semantics.memory == "write"
+                                }
+                                (
+                                    TmaOperation::FenceProxyTensorMapAcquireCluster
+                                    | TmaOperation::FenceProxyTensorMapAcquireCta
+                                    | TmaOperation::FenceProxyTensorMapAcquireGpu
+                                    | TmaOperation::FenceProxyTensorMapAcquireSystem,
+                                    TmaAdapter::DescriptorPointerInjectBytes,
+                                ) => {
+                                    !record.rust.safe
+                                        && !record.semantics.convergent
+                                        && record.semantics.memory == "read_write"
+                                }
+                                (
+                                    TmaOperation::FenceProxyTensorMapReleaseCluster
+                                    | TmaOperation::FenceProxyTensorMapReleaseCta
+                                    | TmaOperation::FenceProxyTensorMapReleaseGpu
+                                    | TmaOperation::FenceProxyTensorMapReleaseSystem,
+                                    TmaAdapter::NoOperands,
+                                ) => {
+                                    record.rust.safe
+                                        && !record.semantics.convergent
+                                        && record.semantics.memory == "read_write"
+                                }
+                                _ => false,
+                            }
+                    }),
+                "{} is outside the closed generated TMA recipe",
+                record.id
+            ),
+            "counted_barrier" | "grid_dependency" | "register_control" => ensure!(
+                ExecutionControlOperation::from_catalog_id(&record.id).is_some_and(|operation| {
+                    record.family == operation.family()
+                        && record.rust.result == "()"
+                        && !record.rust.safe
+                        && !record.rust.must_use
+                        && record.dialect.results.is_empty()
+                        && record
+                            .llvm
+                            .as_ref()
+                            .is_some_and(|llvm| llvm.results.is_empty())
+                        && record.lowering == "generated_execution_control"
+                        && match operation {
+                            ExecutionControlOperation::BarrierCtaSync
+                            | ExecutionControlOperation::BarrierCtaSyncAligned
+                            | ExecutionControlOperation::BarrierCtaArrive
+                            | ExecutionControlOperation::BarrierCtaArriveAligned => {
+                                record.rust.module == "barrier"
+                                    && record.rust.arguments == ["u32", "u32"]
+                                    && record.dialect.operands == ["i32", "i32"]
+                                    && record.llvm.as_ref().is_some_and(|llvm| {
+                                        llvm.arguments == ["i32", "i32"]
+                                    })
+                            }
+                            ExecutionControlOperation::GridDependencyLaunchDependents
+                            | ExecutionControlOperation::GridDependencyWait => {
+                                record.rust.module == "grid"
+                                    && record.rust.arguments.is_empty()
+                                    && record.dialect.operands.is_empty()
+                                    && record
+                                        .llvm
+                                        .as_ref()
+                                        .is_some_and(|llvm| llvm.arguments.is_empty())
+                            }
+                            ExecutionControlOperation::SetMaxNRegInc
+                            | ExecutionControlOperation::SetMaxNRegDec => {
+                                record.rust.module == "thread"
+                                    && record.rust.arguments == ["u32"]
+                                    && record.dialect.operands.is_empty()
+                                    && record
+                                        .llvm
+                                        .as_ref()
+                                        .is_some_and(|llvm| llvm.arguments == ["i32"])
+                            }
+                        }
+                }),
+                "{} is outside the closed generated execution-control recipe",
+                record.id
+            ),
+            "tcgen05" => ensure!(
+                tcgen05_render_contract(record),
+                "{} is outside the closed generated tcgen05 recipe",
+                record.id
+            ),
+            "cp_async_copy" => ensure!(
+                record.rust.module == "async_copy"
+                    && record.rust.result == "()"
+                    && !record.rust.safe
+                    && !record.rust.must_use
+                    && record.llvm.as_ref().is_some_and(|llvm| {
+                        matches!(llvm.arguments.as_slice(), [dst, src]
+                            if dst == "shared_ptr" && src == "global_ptr")
+                            || matches!(llvm.arguments.as_slice(), [dst, src, size]
+                                if dst == "shared_ptr" && src == "global_ptr" && size == "i32")
+                    })
+                    && record.llvm.as_ref().is_some_and(|llvm| llvm.results.is_empty())
+                    && record.dialect.results.is_empty()
+                    && record.lowering == "generated_cp_async_copy"
+                    && record.cp_async_copy.is_some(),
+                "{} is outside the closed generated cp.async copy recipe",
+                record.id
+            ),
+            "cp_async_control" => ensure!(
+                record.rust.module == "async_copy"
+                    && record.rust.result == "()"
+                    && !record.rust.safe
+                    && !record.rust.must_use
+                    && record.llvm.as_ref().is_some_and(|llvm| {
+                        llvm.results.is_empty()
+                            && (llvm.arguments.is_empty() || llvm.arguments == ["i32"])
+                    })
+                    && record.dialect.results.is_empty()
+                    && record.lowering == "generated_cp_async_control"
+                    && record.cp_async_control.is_some(),
+                "{} is outside the closed generated cp.async control recipe",
+                record.id
+            ),
+            "cp_async_mbarrier" => ensure!(
+                record.rust.module == "async_copy"
+                    && record.rust.arguments == ["*mut u64"]
+                    && record.rust.result == "()"
+                    && !record.rust.safe
+                    && !record.rust.must_use
+                    && record.dialect.operands == ["ptr"]
+                    && record.dialect.results.is_empty()
+                    && record.lowering == "generated_cp_async_mbarrier"
+                    && record.cp_async_mbarrier.as_ref().is_some_and(|bridge| {
+                        bridge.adapter == CpAsyncMbarrierAdapter::PointerToVoid
+                            && record.llvm.as_ref().is_some_and(|llvm| {
+                                llvm.results.is_empty()
+                                    && match bridge.state_space {
+                                        CpAsyncMbarrierStateSpace::Generic => {
+                                            llvm.arguments == ["ptr"]
+                                        }
+                                        CpAsyncMbarrierStateSpace::Shared => {
+                                            llvm.arguments == ["shared_ptr"]
+                                        }
+                                    }
+                            })
+                    }),
+                "{} is outside the closed generated cp.async mbarrier recipe",
+                record.id
+            ),
+            "mbarrier_basic" => ensure!(
+                record.rust.module == "barrier"
+                    && !record.rust.safe
+                    && record.lowering == "generated_mbarrier_basic"
+                    && record.mbarrier_basic.as_ref().is_some_and(|mbarrier| {
+                        mbarrier.state_space == MbarrierStateSpace::Shared
+                            && match (mbarrier.operation, mbarrier.adapter) {
+                                (
+                                    MbarrierBasicOperation::Init,
+                                    MbarrierBasicAdapter::InitPointerCountToVoid,
+                                ) => {
+                                    record.rust.arguments == ["*mut u64", "u32"]
+                                        && record.rust.result == "()"
+                                        && !record.rust.must_use
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.arguments == ["shared_ptr", "i32"]
+                                                && llvm.results.is_empty()
+                                        })
+                                        && record.dialect.operands == ["ptr", "i32"]
+                                        && record.dialect.results.is_empty()
+                                }
+                                (
+                                    MbarrierBasicOperation::Arrive,
+                                    MbarrierBasicAdapter::ArrivePointerToToken,
+                                ) => {
+                                    record.rust.arguments == ["*const u64"]
+                                        && record.rust.result == "u64"
+                                        && record.rust.must_use
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.arguments == ["shared_ptr"]
+                                                && llvm.results == ["i64"]
+                                        })
+                                        && record.dialect.operands == ["ptr"]
+                                        && record.dialect.results == ["i64"]
+                                }
+                                (
+                                    MbarrierBasicOperation::TestWait,
+                                    MbarrierBasicAdapter::TestWaitPointerTokenToPredicate,
+                                ) => {
+                                    record.rust.arguments == ["*const u64", "u64"]
+                                        && record.rust.result == "bool"
+                                        && record.rust.must_use
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.arguments == ["shared_ptr", "i64"]
+                                                && llvm.results == ["i1"]
+                                        })
+                                        && record.dialect.operands == ["ptr", "i64"]
+                                        && record.dialect.results == ["i1"]
+                                }
+                                (
+                                    MbarrierBasicOperation::Inval,
+                                    MbarrierBasicAdapter::InvalPointerToVoid,
+                                ) => {
+                                    record.rust.arguments == ["*mut u64"]
+                                        && record.rust.result == "()"
+                                        && !record.rust.must_use
+                                        && record.llvm.as_ref().is_some_and(|llvm| {
+                                            llvm.arguments == ["shared_ptr"]
+                                                && llvm.results.is_empty()
+                                        })
+                                        && record.dialect.operands == ["ptr"]
+                                        && record.dialect.results.is_empty()
+                                }
+                                _ => false,
+                            }
+                    }),
+                "{} is outside the closed generated basic mbarrier recipe",
+                record.id
+            ),
+            "mbarrier_extended" => ensure!(
+                record.rust.module == "barrier"
+                    && !record.rust.safe
+                    && record.semantics.memory == "read_write"
+                    && record.semantics.convergent
+                    && record.lowering == "generated_mbarrier_extended_inline_ptx"
+                    && record.backend_lowerings.iter().all(|lowering| {
+                        lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                    })
+                    && record.mbarrier_extended.as_ref().is_some_and(|mbarrier| {
+                        let source_matches = match mbarrier.source_contract {
+                            MbarrierExtendedSourceContract::LlvmImported => record.llvm.is_some(),
+                            MbarrierExtendedSourceContract::PtxNativeRawClusterAddress => {
+                                record.llvm.is_none()
+                                    && matches!(record.source, IntrinsicSource::PtxNative { .. })
+                            }
+                        };
+                        source_matches
+                            && match (mbarrier.operation, mbarrier.adapter) {
+                                (
+                                    MbarrierExtendedOperation::ArriveExpectTxCta,
+                                    MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount,
+                                ) => record.id == "mbarrier_arrive_expect_tx",
+                                (
+                                    MbarrierExtendedOperation::ArriveExpectTxCluster,
+                                    MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount,
+                                ) => record.id == "mbarrier_arrive_expect_tx_cluster",
+                                (
+                                    MbarrierExtendedOperation::ArriveRemoteCluster,
+                                    MbarrierExtendedAdapter::RawClusterAddressToVoid,
+                                ) => record.id == "mbarrier_arrive_cluster",
+                                (
+                                    MbarrierExtendedOperation::TryWaitTokenCta,
+                                    MbarrierExtendedAdapter::PointerTokenToPredicate,
+                                ) => record.id == "mbarrier_try_wait",
+                                (
+                                    MbarrierExtendedOperation::TryWaitParityCta,
+                                    MbarrierExtendedAdapter::PointerParityToPredicate,
+                                ) => record.id == "mbarrier_try_wait_parity",
+                                (
+                                    MbarrierExtendedOperation::TryWaitParityCluster,
+                                    MbarrierExtendedAdapter::PointerParityToPredicate,
+                                ) => record.id == "mbarrier_try_wait_parity_cluster",
+                                (
+                                    MbarrierExtendedOperation::FenceProxyAsyncSharedCta,
+                                    MbarrierExtendedAdapter::ZeroOperandsToVoid,
+                                ) => record.id == "fence_proxy_async_shared_cta",
+                                (
+                                    MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster,
+                                    MbarrierExtendedAdapter::ZeroOperandsToVoid,
+                                ) => record.id == "fence_mbarrier_init_release_cluster",
+                                (
+                                    MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster,
+                                    MbarrierExtendedAdapter::ZeroOperandsToVoid,
+                                ) => record.id
+                                    == "fence_proxy_async_generic_release_shared_cta_cluster",
+                                (
+                                    MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster,
+                                    MbarrierExtendedAdapter::ZeroOperandsToVoid,
+                                ) => record.id
+                                    == "fence_proxy_async_generic_acquire_shared_cluster_cluster",
+                                (
+                                    MbarrierExtendedOperation::Nanosleep,
+                                    MbarrierExtendedAdapter::NanosecondsToVoid,
+                                ) => record.id == "nanosleep",
+                                _ => false,
+                            }
+                    }),
+                "{} is outside the closed generated extended-mbarrier recipe",
+                record.id
+            ),
+            "sync" => {
+                if record.id == "sync_threads" {
+                    ensure!(
+                        record.rust.module == "thread"
+                            && record.rust.name == "sync_threads"
+                            && record.rust.arguments.is_empty()
+                            && record.rust.result == "()"
+                            && !record.rust.safe
+                            && !record.rust.must_use
+                            && record.llvm.as_ref().is_some_and(|llvm| {
+                                llvm.symbol == "llvm.nvvm.barrier.cta.sync.aligned.all"
+                                    && llvm.arguments == ["i32"]
+                                    && llvm.results.is_empty()
+                            })
+                            && record.dialect.op_type == "Barrier0Op"
+                            && record.dialect.op_name == "nvvm.barrier0"
+                            && record.dialect.operands.is_empty()
+                            && record.dialect.results.is_empty()
+                            && record.lowering == "generated_sync_threads",
+                        "{} is outside the fixed-zero generated sync_threads recipe",
+                        record.id
+                    );
+                } else {
+                    ensure!(
+                        threadfence_ptx_level(record).is_some()
+                            && record.rust.module == "fence"
+                            && record.rust.name == record.id
+                            && record.rust.arguments.is_empty()
+                            && record.rust.result == "()"
+                            && record.rust.safe
+                            && !record.rust.must_use
+                            && record.llvm.as_ref().is_some_and(|llvm| {
+                                llvm.arguments.is_empty() && llvm.results.is_empty()
+                            })
+                            && record.dialect.operands.is_empty()
+                            && record.dialect.results.is_empty()
+                            && record.lowering == "direct_nvvm"
+                            && record.semantics.memory == "read_write"
+                            && !record.semantics.pure
+                            && !record.semantics.convergent,
+                        "{} is outside the closed generated thread-fence recipe",
+                        record.id
+                    );
+                }
+            }
+            "vote" => ensure!(
+                record.rust.module == "warp"
+                    && record.rust.arguments == ["u32", "bool"]
+                    && matches!(record.rust.result.as_str(), "bool" | "u32")
+                    && !record.rust.safe
+                    && record.rust.must_use
+                    && record.llvm.as_ref().is_some_and(|llvm| {
+                        llvm.arguments == ["i32", "i1"]
+                            && matches!(llvm.results.as_slice(), [result]
+                                if result == "i1" || result == "i32")
+                    })
+                    && record.dialect.operands == ["i32", "i1"]
+                    && matches!(record.dialect.results.as_slice(), [result]
+                        if result == "i1" || result == "i32")
+                    && record.lowering == "generated_vote"
+                    && record.vote.is_some(),
+                "{} is outside the closed generated vote.sync recipe",
+                record.id
+            ),
+            "active_mask" => ensure!(
+                record.id == "active_mask"
+                    && record.rust.module == "warp"
+                    && record.rust.arguments.is_empty()
+                    && record.rust.result == "u32"
+                    && record.rust.safe
+                    && record.rust.must_use
+                    && record.llvm.as_ref().is_some_and(|llvm| {
+                        llvm.arguments.is_empty() && llvm.results == ["i32"]
+                    })
+                    && record.dialect.operands.is_empty()
+                    && record.dialect.results == ["i32"]
+                    && record.lowering == "generated_active_mask"
+                    && record.active_mask.is_some(),
+                "{} is outside the closed generated active-mask recipe",
+                record.id
+            ),
+            "warp_match" => ensure!(
+                record.rust.module == "warp"
+                    && matches!(record.rust.arguments.as_slice(), [mask, value]
+                        if mask == "u32" && matches!(value.as_str(), "u32" | "u64"))
+                    && record.rust.result == "u32"
+                    && !record.rust.safe
+                    && record.rust.must_use
+                    && record.llvm.as_ref().is_some_and(|llvm| {
+                        matches!(llvm.arguments.as_slice(), [mask, value]
+                            if mask == "i32" && matches!(value.as_str(), "i32" | "i64"))
+                            && (matches!(llvm.results.as_slice(), [mask] if mask == "i32")
+                                || matches!(llvm.results.as_slice(), [mask, predicate]
+                                    if mask == "i32" && predicate == "i1"))
+                    })
+                    && matches!(record.dialect.operands.as_slice(), [mask, value]
+                        if mask == "i32" && matches!(value.as_str(), "i32" | "i64"))
+                    && record.dialect.results == ["i32"]
+                    && record.lowering == "generated_warp_match"
+                    && record.warp_match.is_some(),
+                "{} is outside the closed generated match.sync recipe",
+                record.id
+            ),
+            "elect" => ensure!(
+                record.id == "elect_sync"
+                    && record.rust.module == "warp"
+                    && record.rust.name == "elect_sync"
+                    && record.rust.arguments == ["u32"]
+                    && record.rust.result == "(u32, bool)"
+                    && !record.rust.safe
+                    && record.rust.must_use
+                    && record.llvm.as_ref().is_some_and(|llvm| {
+                        llvm.symbol == "llvm.nvvm.elect.sync"
+                            && llvm.arguments == ["i32"]
+                            && llvm.results == ["i32", "i1"]
+                    })
+                    && record.dialect.op_type == "ElectSyncOp"
+                    && record.dialect.op_name == "nvvm.elect_sync"
+                    && record.dialect.operands == ["i32"]
+                    && record.dialect.results == ["i32", "i1"]
+                    && record.lowering == "generated_elect",
+                "{} is outside the closed generated elect.sync recipe",
+                record.id
+            ),
+            "warp_barrier" => ensure!(
+                record.id == "sync_mask"
+                    && record.rust.module == "warp"
+                    && record.rust.name == "sync_mask"
+                    && record.rust.arguments == ["u32"]
+                    && record.rust.result == "()"
+                    && !record.rust.safe
+                    && !record.rust.must_use
+                    && record.llvm.as_ref().is_some_and(|llvm| {
+                        llvm.symbol == "llvm.nvvm.bar.warp.sync"
+                            && llvm.arguments == ["i32"]
+                            && llvm.results.is_empty()
+                    })
+                    && record.dialect.op_type == "BarWarpSyncOp"
+                    && record.dialect.op_name == "nvvm.bar_warp_sync"
+                    && record.dialect.operands == ["i32"]
+                    && record.dialect.results.is_empty()
+                    && record.lowering == "generated_warp_barrier"
+                    && record.warp_barrier.as_ref().is_some_and(|barrier| {
+                        barrier.adapter == WarpBarrierAdapter::DirectMemberMask
+                    }),
+                "{} is outside the closed generated bar.warp.sync recipe",
+                record.id
+            ),
+            "warp_shuffle" => ensure!(
+                record.rust.module == "warp"
+                    && matches!(record.rust.arguments.as_slice(), [mask, value, lane]
+                        if mask == "u32"
+                            && lane == "u32"
+                            && matches!(value.as_str(), "u32" | "f32" | "u64")
+                            && value == &record.rust.result)
+                    && !record.rust.safe
+                    && record.rust.must_use
+                    && matches!(record.dialect.operands.as_slice(), [mask, value, lane]
+                        if mask == "i32"
+                            && lane == "i32"
+                            && matches!(value.as_str(), "i32" | "f32" | "i64"))
+                    && matches!(record.dialect.results.as_slice(), [result]
+                        if result == &record.dialect.operands[1])
+                    && record.warp_shuffle.as_ref().is_some_and(|shuffle| {
+                        match shuffle.value_kind {
+                            WarpShuffleValueKind::I32 | WarpShuffleValueKind::F32 => {
+                                let (value_ty, rust_ty) = match shuffle.value_kind {
+                                    WarpShuffleValueKind::I32 => ("i32", "u32"),
+                                    WarpShuffleValueKind::F32 => ("f32", "f32"),
+                                    WarpShuffleValueKind::I64 => unreachable!(),
+                                };
+                                shuffle.adapter
+                                    == WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp
+                                    && shuffle.lane_encoding
+                                        == WarpShuffleOperandEncoding::RegisterOrImmediate
+                                    && shuffle.mask_encoding
+                                        == WarpShuffleOperandEncoding::RegisterOrImmediate
+                                    && record.lowering == "generated_warp_shuffle"
+                                    && record.rust.result == rust_ty
+                                    && record.dialect.operands[1] == value_ty
+                                    && record.llvm.as_ref().is_some_and(|llvm| {
+                                        matches!(llvm.arguments.as_slice(), [mask, value, lane, clamp]
+                                            if mask == "i32"
+                                                && value == value_ty
+                                                && lane == "i32"
+                                                && clamp == "i32")
+                                            && llvm.results == [value_ty]
+                                    })
+                            }
+                            WarpShuffleValueKind::I64 => {
+                                shuffle.adapter
+                                    == WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
+                                    && shuffle.lane_encoding
+                                        == WarpShuffleOperandEncoding::RegisterOnly
+                                    && shuffle.mask_encoding
+                                        == WarpShuffleOperandEncoding::RegisterOnly
+                                    && record.rust.result == "u64"
+                                    && record.dialect.operands[1] == "i64"
+                                    && record.lowering
+                                        == "generated_warp_shuffle_i64_inline_ptx"
+                                    && record.llvm.is_none()
+                                    && matches!(record.source, IntrinsicSource::PtxNative { .. })
+                            }
+                        }
+                    }),
+                "{} is outside the closed generated shfl.sync recipe",
+                record.id
+            ),
+            "integer_minmax" => ensure!(
+                record.integer_minmax.as_ref().is_some_and(|minmax| {
+                    let module = match minmax.format {
+                        IntegerMinMaxFormat::S32 => "int",
+                        IntegerMinMaxFormat::S16x2 | IntegerMinMaxFormat::U16x2 => "i16x2",
+                    };
+                    record.rust.module == module
+                })
+                    && record.rust.arguments.len() == 2
+                    && record
+                        .rust
+                        .arguments
+                        .iter()
+                        .all(|argument| argument == &record.rust.result)
+                    && matches!(record.rust.result.as_str(), "i32" | "u32")
+                    && record.rust.safe
+                    && record.rust.must_use
+                    && record.dialect.operands == ["i32", "i32"]
+                    && record.dialect.results == ["i32"]
+                    && record.lowering == "generated_integer_minmax_inline_ptx",
+                "{} is outside the closed generated integer-min/max recipe",
+                record.id
+            ),
+            family => ensure!(false, "{} has unrenderable family {family}", record.id),
+        };
+    }
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve.rs b/crates/cuda-intrinsics-gen/src/resolve.rs
deleted file mode 100644
index 9ffeb4a5a2..0000000000
--- a/crates/cuda-intrinsics-gen/src/resolve.rs
+++ /dev/null
@@ -1,42000 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-use crate::extract::{IMPORTED_SCHEMA, read_upstream_lock};
-use crate::model::{
-    AbiLedgerEntry, AbiLedgerFile, AbiRawRustSignature, ActiveMaskAdapter, ActiveMaskObservation,
-    BackendLoweringMechanism, CatalogBackend, CatalogBackendLowering, CatalogDialect, CatalogFile,
-    CatalogHalfOpenRange, CatalogHardwareAlternative, CatalogHardwareTarget, CatalogInputs,
-    CatalogIntrinsic, CatalogLdmatrix, CatalogLlvm, CatalogLlvmResultFacts, CatalogRust,
-    CatalogSelection, CatalogSemantics, CatalogSource, CatalogTarget, CatalogTargetAlternative,
-    CatalogTargetContract, CatalogTargetRequirement, Clc, ClcAdapter, ClcAdmission, ClcOperation,
-    ClusterBarrier, ClusterBarrierAdmission, ClusterBarrierMode, ClusterBarrierOrdering,
-    ClusterMemory, ClusterMemoryAdapter, ClusterMemoryAdmission, ClusterMemoryOperation,
-    ClusterMemorySourceContract, ClusterSregAdmission, CpAsyncAdapter, CpAsyncCachePolicy,
-    CpAsyncControlAdapter, CpAsyncControlOperation, CpAsyncCopySize, CpAsyncMbarrierAdapter,
-    CpAsyncMbarrierOperation, CpAsyncMbarrierStateSpace, CpAsyncSourceSize, DebugControl,
-    DebugControlAdapter, DebugControlAdmission, DebugControlOperation, DotProductAdapter,
-    DotProductOperation, DotProductSignedness, EvidenceArtifactKind, EvidenceFile, EvidenceFileV6,
-    EvidenceMatrix, EvidenceMatrixTemplate, EvidenceRecord, EvidenceRecordDefaults, EvidenceStage,
-    EvidenceStageKind, ExecutionControlOperation, ExtendedMinMax, ExtendedMinMaxAdapter,
-    ExtendedMinMaxAdmission, ExtendedMinMaxFormat, ExtendedMinMaxNan, ExtendedMinMaxOperation,
-    ExtendedMinMaxSubnormal, ImportedAddressSpace, ImportedFile, ImportedIntrinsic,
-    IntegerMinMaxFormat, IntegerMinMaxOperation, IntrinsicBackend, IntrinsicSource,
-    LdmatrixAdapter, LdmatrixAddressContract, LdmatrixElement, LdmatrixLayout, LdmatrixMemoryOrder,
-    LdmatrixMultiplicity, LdmatrixParticipation, LdmatrixShape, LdmatrixStateSpace, MaskEncoding,
-    MatchOperandEncoding, MbarrierBasicAdapter, MbarrierBasicOperation, MbarrierExtended,
-    MbarrierExtendedAdapter, MbarrierExtendedAdmission, MbarrierExtendedOperation,
-    MbarrierExtendedSourceContract, MbarrierStateSpace, MovmatrixAdapter, MovmatrixParticipation,
-    OverlayBackendLowering, OverlayFile, OverlayIntrinsic, OverlayShardFile, PackedAluAdapter,
-    PackedAluFormat, PackedAluOperation, PackedAtomicAccessContract, PackedAtomicAdapter,
-    PackedAtomicAtomicity, PackedAtomicCodegenContract, PackedAtomicFormat, PackedAtomicOperation,
-    PackedAtomicOrdering, PackedAtomicPointerContract, PackedAtomicReturnContract,
-    PackedAtomicRounding, PackedAtomicScope, PackedAtomicScopeContract, PackedAtomicStateSpace,
-    PackedAtomicSubnormal, PackedConversionAdapter, PackedConversionDestinationFormat,
-    PackedConversionFp8Admission, PackedConversionFp8Direction, PackedConversionFp8F16x2Admission,
-    PackedConversionFp8Format, PackedConversionRounding, PackedConversionSaturation,
-    PackedConversionSourceFormat, PreSm70MemberMaskRule, Prmt, PrmtAdapter, PrmtAdmission,
-    PrmtMode, PtxVersion, ReduxAdapter, ReduxOperation, ReduxParticipation, RegisterMma,
-    RegisterMmaAccumulator, RegisterMmaAdapter, RegisterMmaAmpereFloatAdmission,
-    RegisterMmaAmpereFloatVariant, RegisterMmaBinaryAdmission, RegisterMmaCompatibilitySource,
-    RegisterMmaElement, RegisterMmaF8F6F4Admission, RegisterMmaFp8Admission,
-    RegisterMmaIntegerAdmission, RegisterMmaKind, RegisterMmaLayout, RegisterMmaOperation,
-    RegisterMmaOverflow, RegisterMmaParticipation, RegisterMmaShape, RuntimeValidation,
-    ScalarArithmetic, ScalarArithmeticAdmission, ScalarArithmeticFormat, ScalarArithmeticOperation,
-    ScalarArithmeticRounding, ScalarArithmeticSaturation, ScalarArithmeticSubnormal,
-    ScalarConversion, ScalarConversionAdapter, ScalarConversionAdmission,
-    ScalarConversionDestinationFormat, ScalarConversionResultRepresentation,
-    ScalarConversionRounding, ScalarConversionSaturation, ScalarConversionSourceFormat, ScalarMath,
-    ScalarMathAdmission, ScalarMathFormat, ScalarMathOperation, ScalarMathPrecision,
-    ScalarMathSubnormal, SparseMma, SparseMmaAccumulator, SparseMmaAdapter,
-    SparseMmaCompatibilitySource, SparseMmaElement, SparseMmaF8F6F4Admission,
-    SparseMmaF8F6F4F16Admission, SparseMmaIntegerAdmission, SparseMmaLayout, SparseMmaLlvmAdapter,
-    SparseMmaMetadata, SparseMmaOverflow, SparseMmaParticipation, SparseMmaSelector,
-    SparseMmaShape, SpecialRegister, SpecialRegisterAdmission, SpecialRegisterKind,
-    SpecialRegisterLlvmExclusion, SpecialRegisterLlvmExclusionReason, SpecialRegisterObservation,
-    SpecialRegisterOutputConstraint, SpecialRegisterPtxType, SpecialRegisterWidth,
-    StmatrixAdmission, StmatrixLayout, StmatrixMultiplicity, TargetContract, TargetSelectorBinding,
-    Tcgen05, Tcgen05Adapter, Tcgen05Admission, Tcgen05Cp, Tcgen05CpAdmissionVariant,
-    Tcgen05CpGroup, Tcgen05CpMember, Tcgen05Ld, Tcgen05LdAdmissionVariant, Tcgen05LdMultiplicity,
-    Tcgen05LdShape, Tcgen05Mma, Tcgen05MmaAdmissionVariant, Tcgen05MmaAlias, Tcgen05MmaBUsage,
-    Tcgen05MmaFixedSelectors, Tcgen05MmaForm, Tcgen05MmaKind, Tcgen05MmaSelectorLayout,
-    Tcgen05Operation, Tcgen05SourceContract, Tcgen05St, Tcgen05StAdmissionVariant,
-    ThreadfenceAdmission, ThreadfenceScope, Tma, TmaAdapter, TmaAdmission, TmaOperation,
-    TmaReduction, TmaReductionAdmissionVariant, TmaReductionLoadMode, TmaReductionOperation,
-    VoteAdapter, VoteMode, VoteParticipation, WarpBarrierAdapter, WarpBarrierMaskEncoding,
-    WarpBarrierMemoryOrdering, WarpBarrierParticipation, WarpMatchAdapter, WarpMatchMode,
-    WarpMatchParticipation, WarpMatchValueWidth, WarpShuffleAdapter, WarpShuffleMode,
-    WarpShuffleOperandEncoding, WarpShuffleParticipation, WarpShuffleSourceLane,
-    WarpShuffleValueKind, WgmmaControl, WgmmaControlAdapter, WgmmaControlAdmission,
-    WgmmaControlMode, WgmmaControlParticipation,
-};
-use crate::ptx::{InstructionPattern, OperandPattern};
-use crate::util::{read_json, sha256_bytes, sha256_file};
-use anyhow::{Context, Result, bail, ensure};
-use cuda_target_spec::{CudaArch, recorded_ptx_floor};
-use ptx_parse::ParseError;
-use std::collections::{BTreeMap, BTreeSet};
-use std::fs;
-use std::path::{Component, Path, PathBuf};
-
-const OVERLAY_SCHEMA: u32 = 44;
-const MINIMUM_OVERLAY_SHARD_SCHEMA: u32 = 26;
-const OVERLAY_SHARD_SCHEMA: u32 = 62;
-const REGISTER_MMA_F8F6F4_SHARD_SCHEMA: u32 = 46;
-const REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA: u32 = 47;
-const REGISTER_MMA_MXF8F6F4_SHARD_SCHEMA: u32 = 60;
-const REGISTER_MMA_FP8_SHARD_SCHEMA: u32 = 48;
-const REGISTER_MMA_AMPERE_FLOAT_SHARD_SCHEMA: u32 = 49;
-const SPARSE_MMA_F8F6F4_SHARD_SCHEMA: u32 = 27;
-const SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA: u32 = 50;
-const PRMT_SHARD_SCHEMA: u32 = 28;
-const PACKED_CONVERSION_FP8_SHARD_SCHEMA: u32 = 29;
-const PACKED_CONVERSION_FP8_F16X2_SHARD_SCHEMA: u32 = 59;
-const CLUSTER_SREG_SHARD_SCHEMA: u32 = 30;
-const CLUSTER_BARRIER_SHARD_SCHEMA: u32 = 31;
-const SPECIAL_REGISTER_SHARD_SCHEMA: u32 = 32;
-const DEBUG_CONTROL_SHARD_SCHEMA: u32 = 33;
-const THREADFENCE_SHARD_SCHEMA: u32 = 34;
-const STMATRIX_SHARD_SCHEMA: u32 = 35;
-const CLUSTER_MEMORY_SHARD_SCHEMA: u32 = 39;
-const CLC_SHARD_SCHEMA: u32 = 40;
-const TMA_SHARD_SCHEMA: u32 = 61;
-const TMA_REDUCTION_SHARD_SCHEMA: u32 = 62;
-const MBARRIER_EXTENDED_SHARD_SCHEMA: u32 = 40;
-const WGMMA_CONTROL_SHARD_SCHEMA: u32 = 38;
-const TCGEN05_SHARD_SCHEMA: u32 = 42;
-const SCALAR_CONVERSION_SHARD_SCHEMA: u32 = 43;
-const SCALAR_ARITHMETIC_SHARD_SCHEMA: u32 = 45;
-const EXTENDED_MINMAX_SHARD_SCHEMA: u32 = 60;
-const TCGEN05_CP_SHARD_SCHEMA: u32 = 52;
-const TCGEN05_LD_SHARD_SCHEMA: u32 = 53;
-const TCGEN05_ST_SHARD_SCHEMA: u32 = 54;
-const TCGEN05_OFFSET_LDST_SHARD_SCHEMA: u32 = 55;
-const TCGEN05_CONTROL_SHARD_SCHEMA: u32 = 56;
-const TCGEN05_MMA_SHARD_SCHEMA: u32 = 57;
-const SCALAR_MATH_SHARD_SCHEMA: u32 = 58;
-pub(crate) const CATALOG_SCHEMA: u32 = 46;
-const BLACKWELL_LDMATRIX_LLVM_TARGETS: &str =
-    "sm_100a|sm_100f|sm_103a|sm_103f|sm_110a|sm_110f|sm_120a|sm_120f|sm_121a|sm_121f";
-const BLACKWELL_LDMATRIX_LIBNVVM_TARGETS: &str = BLACKWELL_LDMATRIX_LLVM_TARGETS;
-const TMA_BLACKWELL_TARGETS: &str = "sm_100a|sm_101a|sm_103a|sm_110a";
-const TENSOR_MAP_REPLACE_TARGETS: &str =
-    "sm_100a|sm_100f|sm_103a|sm_103f|sm_110a|sm_110f|sm_120a|sm_120f|sm_121a|sm_121f|sm_90a";
-const TCGEN05_LLVM_TARGETS: &str = "sm_100a|sm_101a|sm_103a|sm_110a";
-const TCGEN05_LIBNVVM_TARGETS: &str = "sm_100a|sm_103a|sm_110a";
-const TCGEN05_MMA_FORMS: [Tcgen05MmaForm; 14] = [
-    Tcgen05MmaForm::Shared,
-    Tcgen05MmaForm::Tensor,
-    Tcgen05MmaForm::TensorAshift,
-    Tcgen05MmaForm::SpShared,
-    Tcgen05MmaForm::SpTensor,
-    Tcgen05MmaForm::SpTensorAshift,
-    Tcgen05MmaForm::WsShared,
-    Tcgen05MmaForm::WsSharedZeroColMask,
-    Tcgen05MmaForm::WsSpShared,
-    Tcgen05MmaForm::WsSpSharedZeroColMask,
-    Tcgen05MmaForm::WsSpTensor,
-    Tcgen05MmaForm::WsSpTensorZeroColMask,
-    Tcgen05MmaForm::WsTensor,
-    Tcgen05MmaForm::WsTensorZeroColMask,
-];
-const TCGEN05_MMA_ALIASES: [Tcgen05MmaAlias; 5] = [
-    Tcgen05MmaAlias::E4m3,
-    Tcgen05MmaAlias::E5m2,
-    Tcgen05MmaAlias::E2m3,
-    Tcgen05MmaAlias::E3m2,
-    Tcgen05MmaAlias::E2m1,
-];
-const TCGEN05_MMA_KINDS: [Tcgen05MmaKind; 4] = [
-    Tcgen05MmaKind::F16,
-    Tcgen05MmaKind::F8f6f4,
-    Tcgen05MmaKind::I8,
-    Tcgen05MmaKind::Tf32,
-];
-const TCGEN05_MMA_DIALECT_OP_TYPE: &str = "Tcgen05MmaOp";
-const TCGEN05_MMA_DIALECT_OP_NAME: &str = "nvvm.tcgen05_mma";
-const REGISTER_MMA_F8F6F4_TARGETS: &str = "sm_120a|sm_120f|sm_121a|sm_121f";
-const SPARSE_MMA_F8F6F4_TARGETS: &str = "sm_120a|sm_120f|sm_121a|sm_121f";
-
-struct ResolutionBase {
-    overlay: OverlayFile,
-    imported: ImportedFile,
-    source: CatalogSource,
-    imported_sha256: String,
-    overlay_sha256: String,
-    abi_ledger_sha256: String,
-}
-
-#[derive(Debug)]
-pub(crate) struct CandidateResolution {
-    pub catalog: CatalogFile,
-    pub mechanism: BackendLoweringMechanism,
-    pub requirement: CatalogTargetRequirement,
-}
-
-fn primary_evidence_profile<'a>(
-    policy: &'a OverlayIntrinsic,
-    default_profile: &'a str,
-) -> Result<&'a str> {
-    let needs_family_profile = policy.tma.is_some()
-        || ExecutionControlOperation::from_catalog_id(&policy.id).is_some()
-        || policy
-            .tcgen05
-            .as_ref()
-            .and_then(|tcgen05| tcgen05.mma.as_ref())
-            .is_some();
-    if !needs_family_profile {
-        return Ok(default_profile);
-    }
-    policy
-        .backend_lowerings
-        .iter()
-        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-        .map(|lowering| lowering.evidence_profile.as_str())
-        .with_context(|| format!("{} has no LLVM family evidence route", policy.id))
-}
-
-pub fn resolve(repo_root: &Path) -> Result<CatalogFile> {
-    let base = load_resolution_base(repo_root)?;
-    let ResolutionBase {
-        overlay,
-        imported,
-        source,
-        imported_sha256,
-        overlay_sha256,
-        abi_ledger_sha256,
-    } = base;
-    let imported_by_record = index_imported_intrinsics(&imported)?;
-    let llvm_revision = source.llvm_revision.clone();
-    let (evidence_files, evidence_hashes) = read_evidence(repo_root)?;
-    let evidence_by_profile_id = index_evidence(&evidence_files, &llvm_revision)?;
-
-    let mut intrinsics = Vec::with_capacity(overlay.intrinsics.len());
-    for policy in &overlay.intrinsics {
-        let source = resolve_policy_source(policy)?;
-        let declaration = resolve_imported_declaration(policy, &source, &imported_by_record)?;
-        validate_special_register_llvm_exclusion(policy, &imported_by_record)?;
-        validate_policy(policy, &source, declaration, overlay.intrinsic_abi)?;
-        let primary_profile = primary_evidence_profile(policy, &overlay.backend_profile)?;
-        let evidence = evidence_by_profile_id
-            .get(&(primary_profile, policy.id.as_str()))
-            .with_context(|| {
-                format!(
-                    "intrinsic {} has no evidence record in selected profile {}",
-                    policy.id, primary_profile
-                )
-            })?;
-        validate_evidence(policy, evidence, None)?;
-        let backend_lowerings = resolve_backend_lowerings(policy, &evidence_by_profile_id)?;
-        intrinsics.push(resolve_record(
-            policy,
-            source,
-            declaration,
-            evidence.record,
-            primary_profile,
-            evidence.backend_version,
-            evidence.backend_sha256,
-            backend_lowerings,
-            overlay.intrinsic_abi,
-        )?);
-    }
-    for (_, evidence_id) in evidence_by_profile_id.keys() {
-        ensure!(
-            overlay
-                .intrinsics
-                .iter()
-                .any(|record| record.id == *evidence_id),
-            "evidence exists for unknown catalog ID {evidence_id}"
-        );
-    }
-
-    Ok(CatalogFile {
-        schema: CATALOG_SCHEMA,
-        catalog_version: overlay.catalog_version,
-        intrinsic_abi: overlay.intrinsic_abi,
-        generator_version: env!("CARGO_PKG_VERSION").to_owned(),
-        source,
-        inputs: CatalogInputs {
-            imported_sha256,
-            overlay_sha256,
-            abi_ledger_sha256,
-            evidence_sha256: evidence_hashes,
-        },
-        intrinsics,
-    })
-}
-
-#[cfg(test)]
-pub(crate) fn test_catalog_with_clc(repo_root: &Path) -> Result<CatalogFile> {
-    let mut catalog = resolve(repo_root)?;
-    let active_count = catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "clc")
-        .count();
-    if active_count != 0 {
-        ensure!(
-            active_count == 6,
-            "active CLC family must contain six records"
-        );
-        return Ok(catalog);
-    }
-    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json"))?;
-    let imported_by_record = index_imported_intrinsics(&imported)?;
-    let operations = [
-        ClcOperation::TryCancel,
-        ClcOperation::TryCancelMulticast,
-        ClcOperation::QueryIsCanceled,
-        ClcOperation::QueryGetFirstCtaidX,
-        ClcOperation::QueryGetFirstCtaidY,
-        ClcOperation::QueryGetFirstCtaidZ,
-    ];
-    let admission = ClcAdmission {
-        llvm_evidence_profile: "llvm-clc-test".into(),
-        libnvvm_evidence_profile: "libnvvm-clc-test".into(),
-        runtime_validation: RuntimeValidation::Unexecuted,
-        variants: operations
-            .into_iter()
-            .map(|operation| crate::model::ClcAdmissionVariant {
-                abi_id: clc_recipe(operation).abi_id.into(),
-                operation,
-            })
-            .collect(),
-    };
-    for policy in expand_clc_admission(&admission)? {
-        let source = resolve_policy_source(&policy)?;
-        let declaration = resolve_imported_declaration(&policy, &source, &imported_by_record)?;
-        validate_policy(&policy, &source, declaration, catalog.intrinsic_abi)?;
-        let backend_lowerings = policy
-            .backend_lowerings
-            .iter()
-            .map(|lowering| {
-                Ok(CatalogBackendLowering {
-                    backend: lowering.backend,
-                    mechanism: lowering.mechanism,
-                    evidence_profile: lowering.evidence_profile.clone(),
-                    target: backend_target_requirement(&policy, lowering)?,
-                    version: "test".into(),
-                    sha256: "0".repeat(64),
-                    artifact_path: None,
-                    build_id_prefix: None,
-                    status: "validated".into(),
-                    stages: vec![],
-                })
-            })
-            .collect::<Result<Vec<_>>>()?;
-        catalog.intrinsics.push(materialize_record(
-            &policy,
-            source,
-            declaration,
-            CatalogBackend {
-                profile: "clc-test".into(),
-                version: "test".into(),
-                sha256: "0".repeat(64),
-                status: "validated".into(),
-                target_triple: "nvptx64-nvidia-cuda".into(),
-                gpu_target: "sm_100".into(),
-                ptx_feature: "+ptx86".into(),
-            },
-            backend_lowerings,
-            catalog.intrinsic_abi,
-        )?);
-    }
-    catalog
-        .intrinsics
-        .sort_by(|left, right| left.id.cmp(&right.id));
-    Ok(catalog)
-}
-
-#[cfg(test)]
-pub(crate) fn test_catalog_with_tma(repo_root: &Path) -> Result<CatalogFile> {
-    let mut catalog = resolve(repo_root)?;
-    let active_count = catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.tma.is_some())
-        .count();
-    let expected_count = TMA_OPERATIONS.len() + tma_reduction_matrix().len();
-    if active_count == expected_count {
-        return Ok(catalog);
-    }
-    ensure!(
-        active_count == 0 || active_count == TMA_OPERATIONS.len(),
-        "active TMA catalog has {active_count} records; expected 0, {} base records, or {expected_count} total records",
-        TMA_OPERATIONS.len()
-    );
-    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json"))?;
-    let imported_by_record = index_imported_intrinsics(&imported)?;
-    let admission = TmaAdmission {
-        llvm_evidence_profile: "llvm-tma-test".into(),
-        libnvvm_evidence_profile: "libnvvm-tma-test".into(),
-        reduce_llvm_evidence_profile: Some("llvm-tma-reduce-test".into()),
-        reduce_libnvvm_evidence_profile: Some("libnvvm-tma-reduce-test".into()),
-        runtime_validation: RuntimeValidation::Unexecuted,
-        variants: TMA_OPERATIONS
-            .into_iter()
-            .map(|operation| crate::model::TmaAdmissionVariant {
-                abi_id: tma_recipe(operation).abi_id.into(),
-                operation,
-            })
-            .collect(),
-        reduce_variants: tma_reduction_admission_variants(),
-    };
-    for policy in expand_tma_admission(&admission)? {
-        if catalog
-            .intrinsics
-            .iter()
-            .any(|record| record.id.as_str() == policy.id.as_str())
-        {
-            continue;
-        }
-        let source = resolve_policy_source(&policy)?;
-        let declaration = resolve_imported_declaration(&policy, &source, &imported_by_record)?;
-        validate_policy(&policy, &source, declaration, catalog.intrinsic_abi)?;
-        let backend_lowerings = policy
-            .backend_lowerings
-            .iter()
-            .map(|lowering| {
-                Ok(CatalogBackendLowering {
-                    backend: lowering.backend,
-                    mechanism: lowering.mechanism,
-                    evidence_profile: lowering.evidence_profile.clone(),
-                    target: backend_target_requirement(&policy, lowering)?,
-                    version: "test".into(),
-                    sha256: "0".repeat(64),
-                    artifact_path: None,
-                    build_id_prefix: None,
-                    status: "validated".into(),
-                    stages: vec![],
-                })
-            })
-            .collect::<Result<Vec<_>>>()?;
-        catalog.intrinsics.push(materialize_record(
-            &policy,
-            source,
-            declaration,
-            CatalogBackend {
-                profile: "tma-test".into(),
-                version: "test".into(),
-                sha256: "0".repeat(64),
-                status: "validated".into(),
-                target_triple: "nvptx64-nvidia-cuda".into(),
-                gpu_target: "sm_90".into(),
-                ptx_feature: "+ptx80".into(),
-            },
-            backend_lowerings,
-            catalog.intrinsic_abi,
-        )?);
-    }
-    catalog
-        .intrinsics
-        .sort_by(|left, right| left.id.cmp(&right.id));
-    Ok(catalog)
-}
-
-#[cfg(test)]
-pub(crate) fn test_catalog_with_tcgen05(repo_root: &Path) -> Result<CatalogFile> {
-    let mut catalog = resolve(repo_root)?;
-    let active_count = catalog
-        .intrinsics
-        .iter()
-        .filter(|record| record.family == "tcgen05")
-        .count();
-    match active_count {
-        233 => return Ok(catalog),
-        0 => {}
-        count => bail!("active tcgen05 catalog has {count} of 233 records"),
-    }
-    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json"))?;
-    let imported_by_record = index_imported_intrinsics(&imported)?;
-    let operations = [
-        Tcgen05Operation::Alloc,
-        Tcgen05Operation::Dealloc,
-        Tcgen05Operation::RelinquishAllocPermit,
-        Tcgen05Operation::FenceBeforeThreadSync,
-        Tcgen05Operation::FenceAfterThreadSync,
-        Tcgen05Operation::Commit,
-        Tcgen05Operation::CommitSharedCluster,
-        Tcgen05Operation::MmaWsF16,
-        Tcgen05Operation::MmaF16,
-        Tcgen05Operation::MmaWsBf16,
-        Tcgen05Operation::MmaWsTf32,
-        Tcgen05Operation::CpSmemToTmem,
-        Tcgen05Operation::Ld16x256bX8Pure,
-        Tcgen05Operation::Ld16x256bPure,
-        Tcgen05Operation::LoadWait,
-        Tcgen05Operation::StoreWait,
-        Tcgen05Operation::AllocCg2,
-        Tcgen05Operation::DeallocCg2,
-        Tcgen05Operation::RelinquishAllocPermitCg2,
-        Tcgen05Operation::MmaF16Cg2,
-        Tcgen05Operation::CommitCg2,
-        Tcgen05Operation::CommitSharedClusterCg2,
-        Tcgen05Operation::CommitMulticastCg2,
-        Tcgen05Operation::CpSmemToTmemCg2,
-        Tcgen05Operation::CommitMulticast,
-        Tcgen05Operation::ShiftDown,
-        Tcgen05Operation::ShiftDownCg2,
-    ];
-    let admission = Tcgen05Admission {
-        llvm_evidence_profile: "llvm-tcgen05-test".into(),
-        libnvvm_evidence_profile: "libnvvm-tcgen05-test".into(),
-        cp_llvm_evidence_profile: None,
-        cp_libnvvm_evidence_profile: None,
-        ld_llvm_evidence_profile: None,
-        ld_libnvvm_evidence_profile: None,
-        st_llvm_evidence_profile: None,
-        st_libnvvm_evidence_profile: None,
-        offset_llvm_evidence_profile: Some("llvm-tcgen05-offset-test".into()),
-        offset_libnvvm_evidence_profile: Some("libnvvm-tcgen05-offset-test".into()),
-        control_llvm_evidence_profile: Some("llvm-tcgen05-control-test".into()),
-        control_libnvvm_evidence_profile: Some("libnvvm-tcgen05-control-test".into()),
-        mma_llvm_evidence_profile: None,
-        mma_libnvvm_evidence_profile: None,
-        mma_llvm_target_contracts: vec![],
-        mma_libnvvm_target_contracts: vec![],
-        runtime_validation: RuntimeValidation::Unexecuted,
-        variants: operations
-            .into_iter()
-            .map(|operation| crate::model::Tcgen05AdmissionVariant {
-                abi_id: tcgen05_recipe(operation).abi_id.into(),
-                operation,
-            })
-            .collect(),
-        cp_variants: vec![],
-        ld_variants: vec![],
-        st_variants: vec![],
-        ld_offset_variants: TCGEN05_OFFSET_LDST_VARIANTS
-            .into_iter()
-            .flat_map(|(shape, multiplicity)| {
-                [false, true]
-                    .into_iter()
-                    .map(move |pack16| (shape, multiplicity, pack16))
-            })
-            .enumerate()
-            .map(
-                |(index, (shape, multiplicity, pack16))| Tcgen05LdAdmissionVariant {
-                    abi_id: format!("i{:04}", 728 + index),
-                    shape,
-                    multiplicity,
-                    pack16,
-                },
-            )
-            .collect(),
-        st_offset_variants: TCGEN05_OFFSET_LDST_VARIANTS
-            .into_iter()
-            .flat_map(|(shape, multiplicity)| {
-                [false, true]
-                    .into_iter()
-                    .map(move |unpack16| (shape, multiplicity, unpack16))
-            })
-            .enumerate()
-            .map(
-                |(index, (shape, multiplicity, unpack16))| Tcgen05StAdmissionVariant {
-                    abi_id: format!("i{:04}", 744 + index),
-                    shape,
-                    multiplicity,
-                    unpack16,
-                },
-            )
-            .collect(),
-        mma_variants: vec![],
-    };
-    for policy in expand_tcgen05_admission(&admission)? {
-        let source = resolve_policy_source(&policy)?;
-        let declaration = resolve_imported_declaration(&policy, &source, &imported_by_record)?;
-        validate_policy(&policy, &source, declaration, catalog.intrinsic_abi)?;
-        let backend_lowerings = policy
-            .backend_lowerings
-            .iter()
-            .map(|lowering| {
-                Ok(CatalogBackendLowering {
-                    backend: lowering.backend,
-                    mechanism: lowering.mechanism,
-                    evidence_profile: lowering.evidence_profile.clone(),
-                    target: backend_target_requirement(&policy, lowering)?,
-                    version: "test".into(),
-                    sha256: "0".repeat(64),
-                    artifact_path: None,
-                    build_id_prefix: None,
-                    status: "validated".into(),
-                    stages: vec![],
-                })
-            })
-            .collect::<Result<Vec<_>>>()?;
-        catalog.intrinsics.push(materialize_record(
-            &policy,
-            source,
-            declaration,
-            CatalogBackend {
-                profile: "tcgen05-test".into(),
-                version: "test".into(),
-                sha256: "0".repeat(64),
-                status: "validated".into(),
-                target_triple: "nvptx64-nvidia-cuda".into(),
-                gpu_target: "sm_100a".into(),
-                ptx_feature: "+ptx86".into(),
-            },
-            backend_lowerings,
-            catalog.intrinsic_abi,
-        )?);
-    }
-    catalog
-        .intrinsics
-        .sort_by(|left, right| left.id.cmp(&right.id));
-    Ok(catalog)
-}
-
-fn load_resolution_base(repo_root: &Path) -> Result<ResolutionBase> {
-    let lock = read_upstream_lock(repo_root)?;
-    let imported_path = repo_root.join("intrinsics/imported.json");
-    let overlay_path = repo_root.join("intrinsics/overlay.toml");
-    let imported: ImportedFile = read_json(&imported_path)?;
-    let (mut overlay, overlay_sha256) = read_overlay(repo_root, &overlay_path)?;
-    let ledger_path = repo_root.join(format!("intrinsics/abi-v{}.toml", overlay.intrinsic_abi));
-    let ledger_text = fs::read_to_string(&ledger_path)
-        .with_context(|| format!("read {}", ledger_path.display()))?;
-    let ledger: AbiLedgerFile =
-        toml::from_str(&ledger_text).with_context(|| format!("parse {}", ledger_path.display()))?;
-
-    ensure!(
-        imported.schema == IMPORTED_SCHEMA,
-        "unsupported imported.json schema {}",
-        imported.schema
-    );
-    ensure!(
-        overlay.schema == OVERLAY_SCHEMA,
-        "unsupported overlay.toml schema {}",
-        overlay.schema
-    );
-    ensure!(
-        overlay.intrinsic_abi > 0,
-        "intrinsic_abi must be a positive integer"
-    );
-    ensure!(
-        imported.source.llvm_revision == lock.llvm.revision,
-        "imported facts use LLVM {}, but upstream.lock pins {}",
-        imported.source.llvm_revision,
-        lock.llvm.revision
-    );
-    ensure!(
-        imported.source.llvm_tblgen_source_revision == lock.llvm.revision,
-        "imported facts were not produced by llvm-tblgen built from the pinned source"
-    );
-    ensure!(
-        imported.source.llvm_tblgen_version == lock.llvm_tblgen.version_line,
-        "imported facts use llvm-tblgen {:?}, but upstream.lock pins {:?}",
-        imported.source.llvm_tblgen_version,
-        lock.llvm_tblgen.version_line
-    );
-    ensure!(
-        imported.source.intrinsics_json_sha256 == lock.dumps.intrinsics_sha256,
-        "imported intrinsic dump hash does not match upstream.lock"
-    );
-    ensure!(
-        imported.source.nvptx_json_sha256 == lock.dumps.nvptx_sha256,
-        "imported NVPTX dump hash does not match upstream.lock"
-    );
-    let imported_sha256 = sha256_file(&imported_path)?;
-    ensure!(
-        imported_sha256 == lock.dumps.normalized_imported_sha256,
-        "normalized imported.json hash mismatch: upstream.lock records {}, found {}; regenerate from the pinned dumps, and refresh the lock explicitly only for an intentional normalizer change",
-        lock.dumps.normalized_imported_sha256,
-        imported_sha256
-    );
-
-    bind_generated_abi_ids(&mut overlay, &ledger)?;
-    overlay
-        .intrinsics
-        .sort_by(|left, right| left.id.cmp(&right.id));
-    validate_execution_control_family_completeness(&overlay.intrinsics)?;
-    validate_unique_overlay(&overlay.intrinsics, overlay.intrinsic_abi)?;
-    validate_abi_ledger(&overlay, &ledger)?;
-    Ok(ResolutionBase {
-        overlay,
-        imported,
-        source: CatalogSource {
-            llvm_repository: lock.llvm.repository,
-            llvm_revision: lock.llvm.revision,
-            llvm_tblgen_version: lock.llvm_tblgen.version_line,
-            llvm_tblgen_source_revision: lock
-                .llvm_tblgen
-                .built_from_llvm_revision
-                .context("pinned llvm-tblgen has no source revision")?,
-        },
-        imported_sha256,
-        overlay_sha256,
-        abi_ledger_sha256: sha256_file(&ledger_path)?,
-    })
-}
-
-fn index_imported_intrinsics(
-    imported: &ImportedFile,
-) -> Result<BTreeMap<&str, &ImportedIntrinsic>> {
-    let imported_by_record: BTreeMap<_, _> = imported
-        .intrinsics
-        .iter()
-        .map(|intrinsic| (intrinsic.source_record.as_str(), intrinsic))
-        .collect();
-    ensure!(
-        imported_by_record.len() == imported.intrinsics.len(),
-        "imported.json contains duplicate source records"
-    );
-    Ok(imported_by_record)
-}
-
-fn resolve_imported_declaration<'a>(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-    imported_by_record: &'a BTreeMap<&str, &'a ImportedIntrinsic>,
-) -> Result<Option<&'a ImportedIntrinsic>> {
-    match source {
-        IntrinsicSource::LlvmImported { source_record } => Ok(Some(
-            *imported_by_record
-                .get(source_record.as_str())
-                .with_context(|| {
-                    format!(
-                        "overlay intrinsic {} references missing imported record {}",
-                        policy.id, source_record
-                    )
-                })?,
-        )),
-        IntrinsicSource::PtxNative { .. } => Ok(None),
-    }
-}
-
-pub(crate) fn resolve_candidate(
-    repo_root: &Path,
-    intrinsic_id: &str,
-    backend_version: &str,
-    backend_sha256: &str,
-    gpu_target: &str,
-    ptx_feature: &str,
-) -> Result<CandidateResolution> {
-    let base = load_resolution_base(repo_root)?;
-    let imported_by_record = index_imported_intrinsics(&base.imported)?;
-    let policy = base
-        .overlay
-        .intrinsics
-        .iter()
-        .find(|policy| policy.id == intrinsic_id || policy.abi_id == intrinsic_id)
-        .with_context(|| format!("unknown overlay intrinsic {intrinsic_id}"))?;
-    let source = resolve_policy_source(policy)?;
-    let declaration = resolve_imported_declaration(policy, &source, &imported_by_record)?;
-    validate_special_register_llvm_exclusion(policy, &imported_by_record)?;
-    validate_policy(policy, &source, declaration, base.overlay.intrinsic_abi)?;
-    ensure!(
-        !backend_version.trim().is_empty()
-            && backend_sha256.len() == 64
-            && backend_sha256.bytes().all(|byte| byte.is_ascii_hexdigit()),
-        "candidate backend identity is incomplete"
-    );
-    let (mechanism, target) = candidate_llvm_route(policy)?;
-    validate_candidate_target(policy, &target, gpu_target, ptx_feature)?;
-
-    let record = materialize_record(
-        policy,
-        source,
-        declaration,
-        CatalogBackend {
-            profile: "candidate-comparison".into(),
-            version: backend_version.into(),
-            sha256: backend_sha256.into(),
-            status: "candidate".into(),
-            target_triple: "nvptx64-nvidia-cuda".into(),
-            gpu_target: gpu_target.into(),
-            ptx_feature: ptx_feature.into(),
-        },
-        Vec::new(),
-        base.overlay.intrinsic_abi,
-    )?;
-    Ok(CandidateResolution {
-        catalog: CatalogFile {
-            schema: CATALOG_SCHEMA,
-            catalog_version: base.overlay.catalog_version,
-            intrinsic_abi: base.overlay.intrinsic_abi,
-            generator_version: env!("CARGO_PKG_VERSION").to_owned(),
-            source: base.source,
-            inputs: CatalogInputs {
-                imported_sha256: base.imported_sha256,
-                overlay_sha256: base.overlay_sha256,
-                abi_ledger_sha256: base.abi_ledger_sha256,
-                evidence_sha256: Vec::new(),
-            },
-            intrinsics: vec![record],
-        },
-        mechanism,
-        requirement: target,
-    })
-}
-
-fn candidate_llvm_route(
-    policy: &OverlayIntrinsic,
-) -> Result<(BackendLoweringMechanism, CatalogTargetRequirement)> {
-    let routes = policy
-        .backend_lowerings
-        .iter()
-        .filter(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-        .collect::<Vec<_>>();
-    ensure!(
-        routes.len() <= 1,
-        "{} has more than one LLVM-NVPTX route",
-        policy.id
-    );
-    if let Some(route) = routes.first() {
-        return Ok((route.mechanism, backend_target_requirement(policy, route)?));
-    }
-    ensure!(
-        matches!(
-            resolve_policy_source(policy)?,
-            IntrinsicSource::LlvmImported { .. }
-        ),
-        "{} has no LLVM-NVPTX candidate route",
-        policy.id
-    );
-    Ok((
-        BackendLoweringMechanism::TypedNvvm,
-        CatalogTargetRequirement {
-            minimum_ptx: parse_ptx_version(&policy.minimum_ptx, &policy.id)?,
-            hardware: parse_hardware_target(policy)?,
-        },
-    ))
-}
-
-fn validate_candidate_target(
-    policy: &OverlayIntrinsic,
-    requirement: &CatalogTargetRequirement,
-    gpu_target: &str,
-    ptx_feature: &str,
-) -> Result<()> {
-    ensure!(
-        gpu_target.starts_with("sm_"),
-        "candidate GPU target {gpu_target:?} must use sm_NN, sm_NNa, or sm_NNf"
-    );
-    let hardware = parse_stage_hardware(gpu_target).with_context(|| {
-        format!("candidate GPU target {gpu_target:?} must use sm_NN, sm_NNa, or sm_NNf")
-    })?;
-    ensure!(
-        describe_stage_hardware(hardware) == gpu_target,
-        "candidate GPU target {gpu_target:?} is not canonical"
-    );
-    let ptx = parse_candidate_ptx_feature(ptx_feature)?;
-    let effective_minimum_ptx = if is_f8f6f4_mma_target_matrix_policy(policy) {
-        f8f6f4_llvm_ptx_floor(hardware)?
-    } else {
-        target_requirement_ptx_floor(requirement, hardware, true).with_context(|| {
-            format!(
-                "candidate GPU target {gpu_target} does not satisfy {} hardware requirement {:?}",
-                policy.id, requirement.hardware
-            )
-        })?
-    };
-    ensure!(
-        ptx.encoded() >= effective_minimum_ptx,
-        "candidate target {gpu_target} / {ptx_feature} is below {} PTX floor {}.{}",
-        policy.id,
-        effective_minimum_ptx / 10,
-        effective_minimum_ptx % 10
-    );
-    let hardware_matches = target_requirement_ptx_floor(requirement, hardware, true).is_some();
-    ensure!(
-        hardware_matches,
-        "candidate GPU target {gpu_target} does not satisfy {} hardware requirement {:?}",
-        policy.id,
-        requirement.hardware
-    );
-    Ok(())
-}
-
-fn target_requirement_ptx_floor(
-    requirement: &CatalogTargetRequirement,
-    hardware: CatalogHardwareAlternative,
-    allow_forward_minimum: bool,
-) -> Option<u16> {
-    match &requirement.hardware {
-        CatalogHardwareTarget::All => Some(requirement.minimum_ptx.encoded()),
-        CatalogHardwareTarget::AnyOf { alternatives } => alternatives
-            .iter()
-            .any(|expected| {
-                selected_stage_hardware_matches(hardware, *expected, allow_forward_minimum)
-            })
-            .then(|| requirement.minimum_ptx.encoded()),
-        CatalogHardwareTarget::TargetMatrix { contracts } => contracts
-            .iter()
-            .flat_map(|contract| contract.alternatives.iter())
-            .filter(|alternative| {
-                selected_stage_hardware_matches(
-                    hardware,
-                    alternative.hardware,
-                    allow_forward_minimum,
-                )
-            })
-            .map(|alternative| alternative.minimum_ptx.encoded())
-            .min(),
-    }
-}
-
-fn parse_candidate_ptx_feature(value: &str) -> Result<PtxVersion> {
-    let digits = value
-        .strip_prefix("+ptx")
-        .with_context(|| format!("candidate PTX feature {value:?} must use +ptxNN"))?;
-    ensure!(
-        matches!(digits.len(), 2 | 3) && digits.bytes().all(|byte| byte.is_ascii_digit()),
-        "candidate PTX feature {value:?} must use +ptxNN"
-    );
-    let split = digits.len() - 1;
-    let version = format!("{}.{}", &digits[..split], &digits[split..]);
-    version
-        .parse()
-        .map_err(|reason: String| anyhow::anyhow!("candidate PTX feature {value:?}: {reason}"))
-}
-
-fn read_overlay(repo_root: &Path, manifest_path: &Path) -> Result<(OverlayFile, String)> {
-    let manifest_bytes =
-        fs::read(manifest_path).with_context(|| format!("read {}", manifest_path.display()))?;
-    let mut overlay: OverlayFile = toml::from_slice(&manifest_bytes)
-        .with_context(|| format!("parse {}", manifest_path.display()))?;
-
-    ensure!(
-        overlay.intrinsics.is_empty(),
-        "overlay.toml must list family shards instead of inline intrinsic records"
-    );
-    ensure!(
-        !overlay.shards.is_empty(),
-        "overlay.toml must list at least one family shard"
-    );
-
-    let mut previous = None;
-    let mut seen = BTreeSet::new();
-    let mut hash_input = Vec::new();
-    append_overlay_hash_input(&mut hash_input, "intrinsics/overlay.toml", &manifest_bytes);
-
-    for shard_name in &overlay.shards {
-        validate_overlay_shard_path(shard_name)?;
-        ensure!(
-            seen.insert(shard_name.as_str()),
-            "overlay.toml lists duplicate shard {shard_name}"
-        );
-        if let Some(previous) = previous {
-            ensure!(
-                previous < shard_name.as_str(),
-                "overlay.toml shards must be sorted"
-            );
-        }
-        previous = Some(shard_name.as_str());
-
-        let relative = Path::new("intrinsics").join(shard_name);
-        let path = repo_root.join(&relative);
-        let bytes = fs::read(&path).with_context(|| format!("read {}", path.display()))?;
-        let mut shard: OverlayShardFile =
-            toml::from_slice(&bytes).with_context(|| format!("parse {}", path.display()))?;
-        validate_overlay_shard_schema(&shard, &path)?;
-        let int4_mma_admission = shard.register_mma_int4.take();
-        let int8_mma_admission = shard.register_mma_int8.take();
-        let binary_mma_admission = shard.register_mma_b1.take();
-        let f8f6f4_f32_mma_admission = shard.register_mma_f8f6f4_f32.take();
-        let f8f6f4_f16_mma_admission = shard.register_mma_f8f6f4_f16.take();
-        let mxf8f6f4_f32_mma_admission = shard.register_mma_mxf8f6f4_f32.take();
-        let fp8_mma_admission = shard.register_mma_fp8.take();
-        let ampere_float_mma_admission = shard.register_mma_ampere_float.take();
-        let sparse_mma_admission = shard.sparse_mma_integer.take();
-        let sparse_mma_f8f6f4_admission = shard.sparse_mma_f8f6f4_f32.take();
-        let sparse_mma_f8f6f4_f16_admission = shard.sparse_mma_f8f6f4_f16.take();
-        let prmt_admission = shard.prmt.take();
-        let packed_conversion_fp8_admission = shard.packed_conversion_fp8.take();
-        let packed_conversion_fp8_f16x2_admission = shard.packed_conversion_fp8_f16x2.take();
-        let scalar_conversion_admission = shard.scalar_conversion.take();
-        let scalar_arithmetic_admission = shard.scalar_arithmetic.take();
-        let scalar_math_admission = shard.scalar_math.take();
-        let extended_minmax_admission = shard.extended_minmax.take();
-        let cluster_sreg_admission = shard.cluster_sreg.take();
-        let cluster_barrier_admission = shard.cluster_barrier.take();
-        let mbarrier_extended_admission = shard.mbarrier_extended.take();
-        let special_register_admission = shard.special_registers.take();
-        let debug_control_admission = shard.debug_control.take();
-        let threadfence_admission = shard.threadfence.take();
-        let cluster_memory_admission = shard.cluster_memory.take();
-        let stmatrix_admission = shard.stmatrix.take();
-        let clc_admission = shard.clc.take();
-        let wgmma_control_admission = shard.wgmma_controls.take();
-        let tma_admission = shard.tma.take();
-        let tcgen05_admission = shard.tcgen05.take();
-        let compact_mma_count = usize::from(int4_mma_admission.is_some())
-            + usize::from(int8_mma_admission.is_some())
-            + usize::from(binary_mma_admission.is_some())
-            + usize::from(f8f6f4_f32_mma_admission.is_some())
-            + usize::from(f8f6f4_f16_mma_admission.is_some())
-            + usize::from(mxf8f6f4_f32_mma_admission.is_some())
-            + usize::from(fp8_mma_admission.is_some())
-            + usize::from(ampere_float_mma_admission.is_some())
-            + usize::from(sparse_mma_admission.is_some())
-            + usize::from(sparse_mma_f8f6f4_admission.is_some())
-            + usize::from(sparse_mma_f8f6f4_f16_admission.is_some());
-        ensure!(
-            compact_mma_count <= 1,
-            "overlay shard {} contains more than one compact MMA admission",
-            path.display()
-        );
-        let integer_mma_admission = int4_mma_admission
-            .map(|admission| (RegisterMmaIntegerKind::Int4, admission))
-            .or_else(|| {
-                int8_mma_admission.map(|admission| (RegisterMmaIntegerKind::Int8, admission))
-            });
-        if let Some((kind, admission)) = integer_mma_admission {
-            ensure!(
-                shard.family == "register_mma" && shard.intrinsics.is_empty(),
-                "compact integer MMA admission must be the only content of a register_mma shard"
-            );
-            shard.intrinsics = expand_register_mma_integer_admission(kind, &admission)?;
-        }
-        if let Some(admission) = binary_mma_admission {
-            ensure!(
-                shard.family == "register_mma" && shard.intrinsics.is_empty(),
-                "compact binary MMA admission must be the only content of a register_mma shard"
-            );
-            shard.intrinsics = expand_register_mma_binary_admission(&admission)?;
-        }
-        if let Some(admission) = f8f6f4_f32_mma_admission {
-            ensure!(
-                shard.family == "register_mma" && shard.intrinsics.is_empty(),
-                "compact dense f8f6f4 MMA admission must be the only content of a register_mma shard"
-            );
-            shard.intrinsics =
-                expand_register_mma_f8f6f4_admission(&admission, RegisterMmaAccumulator::F32)?;
-        }
-        if let Some(admission) = f8f6f4_f16_mma_admission {
-            ensure!(
-                shard.family == "register_mma" && shard.intrinsics.is_empty(),
-                "compact dense f8f6f4 MMA admission must be the only content of a register_mma shard"
-            );
-            shard.intrinsics =
-                expand_register_mma_f8f6f4_admission(&admission, RegisterMmaAccumulator::F16)?;
-        }
-        if let Some(admission) = mxf8f6f4_f32_mma_admission {
-            ensure!(
-                shard.family == "register_mma" && shard.intrinsics.is_empty(),
-                "compact dense mxf8f6f4 MMA admission must be the only content of a register_mma shard"
-            );
-            shard.intrinsics = expand_register_mma_mxf8f6f4_admission(&admission)?;
-        }
-        if let Some(admission) = fp8_mma_admission {
-            ensure!(
-                shard.family == "register_mma" && shard.intrinsics.is_empty(),
-                "compact standard FP8 MMA admission must be the only content of a register_mma shard"
-            );
-            shard.intrinsics = expand_register_mma_fp8_admission(&admission)?;
-        }
-        if let Some(admission) = ampere_float_mma_admission {
-            ensure!(
-                shard.family == "register_mma" && shard.intrinsics.is_empty(),
-                "compact Ampere floating-point MMA admission must be the only content of a register_mma shard"
-            );
-            shard.intrinsics = expand_register_mma_ampere_float_admission(&admission)?;
-        }
-        if let Some(admission) = sparse_mma_admission {
-            ensure!(
-                shard.family == "sparse_mma" && shard.intrinsics.is_empty(),
-                "compact sparse MMA admission must be the only content of a sparse_mma shard"
-            );
-            shard.intrinsics = expand_sparse_mma_integer_admission(&admission)?;
-        }
-        if let Some(admission) = sparse_mma_f8f6f4_admission {
-            ensure!(
-                shard.family == "sparse_mma" && shard.intrinsics.is_empty(),
-                "compact sparse f8f6f4 MMA admission must be the only content of a sparse_mma shard"
-            );
-            shard.intrinsics = expand_sparse_mma_f8f6f4_admission(&admission)?;
-        }
-        if let Some(admission) = sparse_mma_f8f6f4_f16_admission {
-            ensure!(
-                shard.family == "sparse_mma" && shard.intrinsics.is_empty(),
-                "compact sparse f8f6f4 F16 MMA admission must be the only content of a sparse_mma shard"
-            );
-            shard.intrinsics = expand_sparse_mma_f8f6f4_f16_admission(&admission)?;
-        }
-        if let Some(admission) = prmt_admission {
-            ensure!(
-                shard.family == "prmt" && shard.intrinsics.is_empty(),
-                "compact prmt admission must be the only content of a prmt shard"
-            );
-            shard.intrinsics = expand_prmt_admission(&admission)?;
-        }
-        if let Some(admission) = packed_conversion_fp8_admission {
-            ensure!(
-                shard.family == "packed_conversion" && shard.intrinsics.is_empty(),
-                "compact FP8 conversion admission must be the only content of a packed_conversion shard"
-            );
-            shard.intrinsics = expand_packed_conversion_fp8_admission(&admission)?;
-        }
-        if let Some(admission) = packed_conversion_fp8_f16x2_admission {
-            ensure!(
-                shard.family == "packed_conversion" && shard.intrinsics.is_empty(),
-                "compact FP8 f16x2 conversion admission must be the only content of a packed_conversion shard"
-            );
-            shard.intrinsics = expand_packed_conversion_fp8_f16x2_admission(&admission)?;
-        }
-        if let Some(admission) = scalar_conversion_admission {
-            ensure!(
-                shard.family == "scalar_conversion" && shard.intrinsics.is_empty(),
-                "compact scalar-conversion admission must be the only content of its shard"
-            );
-            shard.intrinsics = expand_scalar_conversion_admission(&admission)?;
-        }
-        if let Some(admission) = scalar_arithmetic_admission {
-            ensure!(
-                shard.family == "scalar_arithmetic" && shard.intrinsics.is_empty(),
-                "compact scalar-arithmetic admission must be the only content of its shard"
-            );
-            shard.intrinsics = expand_scalar_arithmetic_admission(&admission)?;
-        }
-        if let Some(admission) = scalar_math_admission {
-            ensure!(
-                shard.family == "scalar_math" && shard.intrinsics.is_empty(),
-                "compact scalar-math admission must be the only content of its shard"
-            );
-            shard.intrinsics = expand_scalar_math_admission(&admission)?;
-        }
-        if let Some(admission) = extended_minmax_admission {
-            ensure!(
-                shard.family == "extended_minmax" && shard.intrinsics.is_empty(),
-                "compact extended-minmax admission must be the only content of its shard"
-            );
-            shard.intrinsics = expand_extended_minmax_admission(&admission)?;
-        }
-        if let Some(admission) = cluster_sreg_admission {
-            ensure!(
-                shard.family == "sreg" && shard.intrinsics.is_empty() && compact_mma_count == 0,
-                "compact cluster-sreg admission must be the only content of an sreg shard"
-            );
-            shard.intrinsics = expand_cluster_sreg_admission(&admission)?;
-        }
-        if let Some(admission) = cluster_barrier_admission {
-            ensure!(
-                shard.family == "cluster_barrier" && shard.intrinsics.is_empty(),
-                "compact cluster-barrier admission must be the only content of its shard"
-            );
-            shard.intrinsics = expand_cluster_barrier_admission(&admission)?;
-        }
-        if let Some(admission) = mbarrier_extended_admission {
-            ensure!(
-                shard.family == "mbarrier_extended" && shard.intrinsics.is_empty(),
-                "compact extended-mbarrier admission must be the only content of its shard"
-            );
-            shard.intrinsics = expand_mbarrier_extended_admission(&admission)?;
-        }
-        if let Some(admission) = special_register_admission {
-            ensure!(
-                shard.family == "sreg" && shard.intrinsics.is_empty(),
-                "compact special-register admission must be the only content of an sreg shard"
-            );
-            shard.intrinsics = expand_special_register_admission(&admission)?;
-        }
-        if let Some(admission) = debug_control_admission {
-            ensure!(
-                shard.family == "debug_control" && shard.intrinsics.is_empty(),
-                "compact debug-control admission must be the only content of a debug_control shard"
-            );
-            shard.intrinsics = expand_debug_control_admission(&admission)?;
-        }
-        if let Some(admission) = threadfence_admission {
-            ensure!(
-                shard.family == "sync" && shard.intrinsics.is_empty(),
-                "compact threadfence admission must be the only content of a sync shard"
-            );
-            shard.intrinsics = expand_threadfence_admission(&admission)?;
-        }
-        if let Some(admission) = cluster_memory_admission {
-            ensure!(
-                shard.family == "cluster_memory" && shard.intrinsics.is_empty(),
-                "compact cluster-memory admission must be the only content of its shard"
-            );
-            shard.intrinsics = expand_cluster_memory_admission(&admission)?;
-        }
-        if let Some(admission) = stmatrix_admission {
-            ensure!(
-                shard.family == "stmatrix" && shard.intrinsics.is_empty(),
-                "compact stmatrix admission must be the only content of its shard"
-            );
-            shard.intrinsics = expand_stmatrix_admission(&admission)?;
-        }
-        if let Some(admission) = clc_admission {
-            ensure!(
-                shard.family == "clc" && shard.intrinsics.is_empty(),
-                "compact CLC admission must be the only content of a clc shard"
-            );
-            shard.intrinsics = expand_clc_admission(&admission)?;
-        }
-        if let Some(admission) = wgmma_control_admission {
-            ensure!(
-                shard.family == "wgmma_control" && shard.intrinsics.is_empty(),
-                "compact WGMMA-control admission must be the only content of its shard"
-            );
-            shard.intrinsics = expand_wgmma_control_admission(&admission)?;
-        }
-        if let Some(admission) = tma_admission {
-            ensure!(
-                shard.family == "tma" && shard.intrinsics.is_empty(),
-                "compact TMA admission must be the only content of a tma shard"
-            );
-            shard.intrinsics = expand_tma_admission(&admission)?;
-        }
-        if let Some(admission) = tcgen05_admission {
-            ensure!(
-                shard.family == "tcgen05" && shard.intrinsics.is_empty(),
-                "compact tcgen05 admission must be the only content of a tcgen05 shard"
-            );
-            shard.intrinsics = expand_tcgen05_admission(&admission)?;
-        }
-        ensure!(
-            !shard.intrinsics.is_empty(),
-            "overlay shard {} contains no intrinsic records",
-            path.display()
-        );
-        for record in &shard.intrinsics {
-            ensure!(
-                record.family == shard.family,
-                "overlay shard {} declares family {}, but intrinsic {} uses family {}",
-                path.display(),
-                shard.family,
-                record.id,
-                record.family
-            );
-        }
-
-        append_overlay_hash_input(
-            &mut hash_input,
-            relative
-                .to_str()
-                .context("overlay shard path is not valid UTF-8")?,
-            &bytes,
-        );
-        overlay.intrinsics.extend(shard.intrinsics);
-    }
-
-    Ok((overlay, sha256_bytes(&hash_input)))
-}
-
-fn validate_overlay_shard_schema(shard: &OverlayShardFile, path: &Path) -> Result<()> {
-    validate_overlay_shard_schema_with_max(shard, path, OVERLAY_SHARD_SCHEMA)
-}
-
-fn validate_overlay_shard_schema_with_max(
-    shard: &OverlayShardFile,
-    path: &Path,
-    maximum_schema: u32,
-) -> Result<()> {
-    ensure!(
-        (MINIMUM_OVERLAY_SHARD_SCHEMA..=maximum_schema).contains(&shard.schema),
-        "unsupported overlay shard schema {} in {}",
-        shard.schema,
-        path.display()
-    );
-    ensure!(
-        shard.sparse_mma_f8f6f4_f32.is_none() || shard.schema >= SPARSE_MMA_F8F6F4_SHARD_SCHEMA,
-        "compact sparse f8f6f4 MMA admission requires overlay shard schema {}",
-        SPARSE_MMA_F8F6F4_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.sparse_mma_f8f6f4_f16.is_none() || shard.schema >= SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA,
-        "compact sparse f8f6f4 F16 MMA admission requires overlay shard schema {}",
-        SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.register_mma_f8f6f4_f32.is_none() || shard.schema >= REGISTER_MMA_F8F6F4_SHARD_SCHEMA,
-        "compact dense f8f6f4 MMA admission requires overlay shard schema {}",
-        REGISTER_MMA_F8F6F4_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.register_mma_f8f6f4_f16.is_none()
-            || shard.schema >= REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA,
-        "compact dense f8f6f4 F16 MMA admission requires overlay shard schema {}",
-        REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.register_mma_mxf8f6f4_f32.is_none()
-            || shard.schema >= REGISTER_MMA_MXF8F6F4_SHARD_SCHEMA,
-        "compact dense mxf8f6f4 MMA admission requires overlay shard schema {}",
-        REGISTER_MMA_MXF8F6F4_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.register_mma_fp8.is_none() || shard.schema >= REGISTER_MMA_FP8_SHARD_SCHEMA,
-        "compact standard FP8 MMA admission requires overlay shard schema {}",
-        REGISTER_MMA_FP8_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.register_mma_ampere_float.is_none()
-            || shard.schema >= REGISTER_MMA_AMPERE_FLOAT_SHARD_SCHEMA,
-        "compact Ampere floating-point MMA admission requires overlay shard schema {}",
-        REGISTER_MMA_AMPERE_FLOAT_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.prmt.is_none() || shard.schema >= PRMT_SHARD_SCHEMA,
-        "compact prmt admission requires overlay shard schema {}",
-        PRMT_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.packed_conversion_fp8.is_none() || shard.schema >= PACKED_CONVERSION_FP8_SHARD_SCHEMA,
-        "compact FP8 conversion admission requires overlay shard schema {}",
-        PACKED_CONVERSION_FP8_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.packed_conversion_fp8_f16x2.is_none()
-            || shard.schema >= PACKED_CONVERSION_FP8_F16X2_SHARD_SCHEMA,
-        "compact FP8 f16x2 conversion admission requires overlay shard schema {}",
-        PACKED_CONVERSION_FP8_F16X2_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.scalar_conversion.is_none() || shard.schema >= SCALAR_CONVERSION_SHARD_SCHEMA,
-        "compact scalar-conversion admission requires overlay shard schema {}",
-        SCALAR_CONVERSION_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.scalar_arithmetic.is_none() || shard.schema >= SCALAR_ARITHMETIC_SHARD_SCHEMA,
-        "compact scalar-arithmetic admission requires overlay shard schema {}",
-        SCALAR_ARITHMETIC_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.scalar_math.is_none() || shard.schema >= SCALAR_MATH_SHARD_SCHEMA,
-        "compact scalar-math admission requires overlay shard schema {}",
-        SCALAR_MATH_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.extended_minmax.is_none() || shard.schema >= EXTENDED_MINMAX_SHARD_SCHEMA,
-        "compact extended-minmax admission requires overlay shard schema {}",
-        EXTENDED_MINMAX_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.cluster_sreg.is_none() || shard.schema >= CLUSTER_SREG_SHARD_SCHEMA,
-        "compact cluster-sreg admission requires overlay shard schema {}",
-        CLUSTER_SREG_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.cluster_barrier.is_none() || shard.schema >= CLUSTER_BARRIER_SHARD_SCHEMA,
-        "compact cluster-barrier admission requires overlay shard schema {}",
-        CLUSTER_BARRIER_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.special_registers.is_none() || shard.schema >= SPECIAL_REGISTER_SHARD_SCHEMA,
-        "compact special-register admission requires overlay shard schema {}",
-        SPECIAL_REGISTER_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.debug_control.is_none() || shard.schema >= DEBUG_CONTROL_SHARD_SCHEMA,
-        "compact debug-control admission requires overlay shard schema {}",
-        DEBUG_CONTROL_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.threadfence.is_none() || shard.schema >= THREADFENCE_SHARD_SCHEMA,
-        "compact threadfence admission requires overlay shard schema {}",
-        THREADFENCE_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.cluster_memory.is_none() || shard.schema >= CLUSTER_MEMORY_SHARD_SCHEMA,
-        "compact cluster-memory admission requires overlay shard schema {}",
-        CLUSTER_MEMORY_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.stmatrix.is_none() || shard.schema >= STMATRIX_SHARD_SCHEMA,
-        "compact stmatrix admission requires overlay shard schema {}",
-        STMATRIX_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.clc.is_none() || shard.schema >= CLC_SHARD_SCHEMA,
-        "compact CLC admission requires overlay shard schema {}",
-        CLC_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.tma.is_none() || shard.schema >= TMA_SHARD_SCHEMA,
-        "compact TMA admission requires overlay shard schema {}",
-        TMA_SHARD_SCHEMA
-    );
-    ensure!(
-        shard
-            .tma
-            .as_ref()
-            .is_none_or(|admission| admission.reduce_variants.is_empty())
-            || shard.schema >= TMA_REDUCTION_SHARD_SCHEMA,
-        "compact TMA reduction admission requires overlay shard schema {}",
-        TMA_REDUCTION_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.mbarrier_extended.is_none() || shard.schema >= MBARRIER_EXTENDED_SHARD_SCHEMA,
-        "compact extended-mbarrier admission requires overlay shard schema {}",
-        MBARRIER_EXTENDED_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.wgmma_controls.is_none() || shard.schema >= WGMMA_CONTROL_SHARD_SCHEMA,
-        "compact WGMMA-control admission requires overlay shard schema {}",
-        WGMMA_CONTROL_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.tcgen05.is_none() || shard.schema >= TCGEN05_SHARD_SCHEMA,
-        "compact tcgen05 admission requires overlay shard schema {}",
-        TCGEN05_SHARD_SCHEMA
-    );
-    ensure!(
-        shard
-            .tcgen05
-            .as_ref()
-            .is_none_or(|admission| admission.cp_variants.is_empty())
-            || shard.schema >= TCGEN05_CP_SHARD_SCHEMA,
-        "compact tcgen05 copy admission requires overlay shard schema {}",
-        TCGEN05_CP_SHARD_SCHEMA
-    );
-    ensure!(
-        shard
-            .tcgen05
-            .as_ref()
-            .is_none_or(|admission| admission.ld_variants.is_empty())
-            || shard.schema >= TCGEN05_LD_SHARD_SCHEMA,
-        "compact tcgen05 load admission requires overlay shard schema {}",
-        TCGEN05_LD_SHARD_SCHEMA
-    );
-    ensure!(
-        shard
-            .tcgen05
-            .as_ref()
-            .is_none_or(|admission| admission.st_variants.is_empty())
-            || shard.schema >= TCGEN05_ST_SHARD_SCHEMA,
-        "compact tcgen05 store admission requires overlay shard schema {}",
-        TCGEN05_ST_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.tcgen05.as_ref().is_none_or(|admission| {
-            admission.ld_offset_variants.is_empty() && admission.st_offset_variants.is_empty()
-        }) || shard.schema >= TCGEN05_OFFSET_LDST_SHARD_SCHEMA,
-        "compact tcgen05 offset load/store admission requires overlay shard schema {}",
-        TCGEN05_OFFSET_LDST_SHARD_SCHEMA
-    );
-    ensure!(
-        shard.tcgen05.as_ref().is_none_or(|admission| {
-            admission.control_llvm_evidence_profile.is_none()
-                && admission.control_libnvvm_evidence_profile.is_none()
-                && !admission.variants.iter().any(|variant| {
-                    matches!(
-                        variant.operation,
-                        Tcgen05Operation::CommitMulticast
-                            | Tcgen05Operation::ShiftDown
-                            | Tcgen05Operation::ShiftDownCg2
-                    )
-                })
-        }) || shard.schema >= TCGEN05_CONTROL_SHARD_SCHEMA,
-        "compact tcgen05 control admission requires overlay shard schema {}",
-        TCGEN05_CONTROL_SHARD_SCHEMA
-    );
-    if let Some(admission) = &shard.tcgen05
-        && shard.schema >= TCGEN05_CONTROL_SHARD_SCHEMA
-    {
-        ensure!(
-            admission
-                .control_llvm_evidence_profile
-                .as_deref()
-                .is_some_and(|profile| !profile.trim().is_empty())
-                && admission
-                    .control_libnvvm_evidence_profile
-                    .as_deref()
-                    .is_some_and(|profile| !profile.trim().is_empty())
-                && [
-                    Tcgen05Operation::CommitMulticast,
-                    Tcgen05Operation::ShiftDown,
-                    Tcgen05Operation::ShiftDownCg2,
-                ]
-                .into_iter()
-                .all(|operation| admission
-                    .variants
-                    .iter()
-                    .any(|variant| variant.operation == operation)),
-            "compact tcgen05 schema {} requires all three control variants and both backend evidence profiles",
-            TCGEN05_CONTROL_SHARD_SCHEMA
-        );
-    }
-    ensure!(
-        shard.tcgen05.as_ref().is_none_or(|admission| {
-            admission.mma_variants.is_empty()
-                && admission.mma_llvm_evidence_profile.is_none()
-                && admission.mma_libnvvm_evidence_profile.is_none()
-                && admission.mma_llvm_target_contracts.is_empty()
-                && admission.mma_libnvvm_target_contracts.is_empty()
-        }) || shard.schema >= TCGEN05_MMA_SHARD_SCHEMA,
-        "compact tcgen05 MMA admission requires overlay shard schema {}",
-        TCGEN05_MMA_SHARD_SCHEMA
-    );
-    Ok(())
-}
-
-fn validate_overlay_shard_path(path: &str) -> Result<()> {
-    let path = Path::new(path);
-    ensure!(
-        path.extension().and_then(|extension| extension.to_str()) == Some("toml"),
-        "overlay shard path must name a TOML file: {}",
-        path.display()
-    );
-    let components: Vec<_> = path.components().collect();
-    ensure!(
-        components.len() >= 2 && components[0] == Component::Normal("overlay".as_ref()),
-        "overlay shard path must stay under intrinsics/overlay: {}",
-        path.display()
-    );
-    ensure!(
-        components
-            .iter()
-            .all(|component| matches!(component, Component::Normal(_))),
-        "overlay shard path contains a non-normal component: {}",
-        path.display()
-    );
-    Ok(())
-}
-
-fn append_overlay_hash_input(output: &mut Vec<u8>, path: &str, contents: &[u8]) {
-    output.extend_from_slice(&(path.len() as u64).to_le_bytes());
-    output.extend_from_slice(path.as_bytes());
-    output.extend_from_slice(&(contents.len() as u64).to_le_bytes());
-    output.extend_from_slice(contents);
-}
-
-fn shares_tma_2d_g2s_symbol(record: &OverlayIntrinsic, symbol: &str) -> bool {
-    symbol == "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d"
-        && record.tma.as_ref().is_some_and(|tma| {
-            matches!(
-                tma.operation,
-                TmaOperation::G2sTile2d
-                    | TmaOperation::G2sTile2dMulticast
-                    | TmaOperation::G2sTile2dMulticastCg2
-            )
-        })
-}
-
-fn shares_tma_prefetch_tile_symbol(record: &OverlayIntrinsic, symbol: &str) -> bool {
-    let Some(tma) = record.tma.as_ref() else {
-        return false;
-    };
-    let expected_symbol = match tma.operation {
-        TmaOperation::PrefetchTile1d | TmaOperation::PrefetchTile1dCacheHint => {
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d"
-        }
-        TmaOperation::PrefetchTile2d | TmaOperation::PrefetchTile2dCacheHint => {
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d"
-        }
-        TmaOperation::PrefetchTile3d | TmaOperation::PrefetchTile3dCacheHint => {
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d"
-        }
-        TmaOperation::PrefetchTile4d | TmaOperation::PrefetchTile4dCacheHint => {
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d"
-        }
-        TmaOperation::PrefetchTile5d | TmaOperation::PrefetchTile5dCacheHint => {
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d"
-        }
-        TmaOperation::PrefetchTileGather4TwoDimensional
-        | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint => {
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.gather4.2d"
-        }
-        _ => return false,
-    };
-    symbol == expected_symbol
-}
-
-fn shares_tcgen05_mma_symbol(record: &OverlayIntrinsic, symbol: &str) -> bool {
-    record.tcgen05.as_ref().is_some_and(|tcgen05| {
-        (symbol == "llvm.nvvm.tcgen05.mma.ws.tensor"
-            && matches!(
-                tcgen05.operation,
-                Tcgen05Operation::MmaWsF16
-                    | Tcgen05Operation::MmaWsBf16
-                    | Tcgen05Operation::MmaWsTf32
-            ))
-            || tcgen05
-                .mma
-                .as_ref()
-                .is_some_and(|mma| symbol == tcgen05_mma_llvm_symbol(mma.form))
-    })
-}
-
-fn shares_tcgen05_ld_symbol(record: &OverlayIntrinsic, symbol: &str) -> bool {
-    let Some(tcgen05) = record.tcgen05.as_ref() else {
-        return false;
-    };
-    if let Some(ld) = tcgen05.ld {
-        return tcgen05.operation == Tcgen05Operation::Ld
-            && record.source_record.as_deref() == Some(tcgen05_ld_source_record(ld).as_str())
-            && symbol == tcgen05_ld_llvm_symbol(ld);
-    }
-    matches!(
-        (tcgen05.operation, record.source_record.as_deref(), symbol),
-        (
-            Tcgen05Operation::Ld16x256bPure,
-            Some("int_nvvm_tcgen05_ld_16x256b_x1"),
-            "llvm.nvvm.tcgen05.ld.16x256b.x1"
-        ) | (
-            Tcgen05Operation::Ld16x256bX8Pure,
-            Some("int_nvvm_tcgen05_ld_16x256b_x8"),
-            "llvm.nvvm.tcgen05.ld.16x256b.x8"
-        )
-    )
-}
-
-fn shares_tcgen05_st_symbol(record: &OverlayIntrinsic, symbol: &str) -> bool {
-    record.tcgen05.as_ref().is_some_and(|tcgen05| {
-        tcgen05.st.is_some_and(|st| {
-            tcgen05.operation == Tcgen05Operation::St
-                && record.source_record.as_deref() == Some(tcgen05_st_source_record(st).as_str())
-                && symbol == tcgen05_st_llvm_symbol(st)
-        })
-    })
-}
-
-fn validate_unique_overlay(records: &[OverlayIntrinsic], intrinsic_abi: u32) -> Result<()> {
-    let mut ids = BTreeSet::new();
-    let mut abi_ids = BTreeSet::new();
-    let mut operation_keys = BTreeSet::new();
-    let mut paths = BTreeSet::new();
-    let mut op_variants = BTreeSet::new();
-    let mut op_type_names = BTreeMap::new();
-    let mut symbol_bases = BTreeMap::new();
-    let mut symbols = BTreeSet::new();
-    let mut rust_items = BTreeSet::new();
-    for record in records {
-        insert_unique(&mut ids, &record.id, "catalog ID")?;
-        validate_abi_id(&record.abi_id)?;
-        insert_unique(&mut abi_ids, &record.abi_id, "intrinsic ABI ID")?;
-        validate_operation_key(&record.operation_key)?;
-        insert_unique(
-            &mut operation_keys,
-            &record.operation_key,
-            "intrinsic operation key",
-        )?;
-        if let Some(previous_name) = op_type_names.insert(
-            record.dialect_op_type.as_str(),
-            record.dialect_op_name.as_str(),
-        ) {
-            ensure!(
-                previous_name == record.dialect_op_name,
-                "dialect op type {} maps to both {} and {}",
-                record.dialect_op_type,
-                previous_name,
-                record.dialect_op_name
-            );
-        }
-        let op_variant = format!(
-            "{}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}",
-            record.dialect_op_name,
-            record.ldmatrix_variant,
-            record.packed_atomic,
-            record.redux,
-            record.vote,
-            record.active_mask,
-            record.warp_match,
-            record.warp_barrier,
-            record.warp_shuffle,
-            record.dot_product,
-            record.cp_async_copy,
-            record.cp_async_control,
-            record.cp_async_mbarrier,
-            record.mbarrier_basic,
-            record.movmatrix,
-            record.mbarrier_extended,
-            record.register_mma,
-            record.sparse_mma,
-            record.prmt,
-            record.cluster_barrier,
-            record.cluster_memory,
-            record.scalar_conversion,
-            record.scalar_arithmetic,
-            record.scalar_math,
-            record.extended_minmax,
-            record.tcgen05,
-        );
-        insert_unique(&mut op_variants, &op_variant, "dialect op variant")?;
-        if let Some(symbol) = &record.llvm_symbol {
-            let is_resolved = record.resolved_llvm_symbol.is_some();
-            let shares_reviewed_symbol = shares_tma_2d_g2s_symbol(record, symbol)
-                || shares_tma_prefetch_tile_symbol(record, symbol)
-                || shares_tcgen05_mma_symbol(record, symbol)
-                || shares_tcgen05_ld_symbol(record, symbol)
-                || shares_tcgen05_st_symbol(record, symbol);
-            if let Some((previous_was_resolved, previous_shared_symbol)) =
-                symbol_bases.insert(symbol, (is_resolved, shares_reviewed_symbol))
-            {
-                ensure!(
-                    (previous_was_resolved && is_resolved)
-                        || (previous_shared_symbol && shares_reviewed_symbol),
-                    "duplicate LLVM symbol {symbol} is reused without a resolved symbol"
-                );
-            }
-            if !shares_reviewed_symbol {
-                insert_unique(
-                    &mut symbols,
-                    record.resolved_llvm_symbol.as_ref().unwrap_or(symbol),
-                    "resolved LLVM symbol",
-                )?;
-            }
-        }
-        insert_unique(
-            &mut rust_items,
-            &format!("{}::{}", record.rust_module, record.rust_name),
-            "raw Rust item",
-        )?;
-        insert_unique(
-            &mut paths,
-            &canonical_rust_path(intrinsic_abi, &record.abi_id),
-            "canonical Rust path",
-        )?;
-        insert_unique(&mut paths, &record.public_rust_path, "public Rust path")?;
-        for path in &record.compatibility_rust_paths {
-            insert_unique(&mut paths, path, "compatibility Rust path")?;
-        }
-    }
-    Ok(())
-}
-
-struct AbiLedgerIndex<'a> {
-    by_catalog_id: BTreeMap<&'a str, &'a AbiLedgerEntry>,
-}
-
-impl<'a> AbiLedgerIndex<'a> {
-    fn new(ledger: &'a AbiLedgerFile) -> Result<Self> {
-        let mut by_catalog_id = BTreeMap::new();
-        for entry in &ledger.entries {
-            ensure!(
-                by_catalog_id
-                    .insert(entry.catalog_id.as_str(), entry)
-                    .is_none(),
-                "duplicate ABI ledger catalog ID: {}",
-                entry.catalog_id
-            );
-        }
-        Ok(Self { by_catalog_id })
-    }
-
-    fn active(&self, catalog_id: &str) -> Result<&'a AbiLedgerEntry> {
-        let entry = self
-            .by_catalog_id
-            .get(catalog_id)
-            .copied()
-            .with_context(|| format!("generated intrinsic {catalog_id} has no ABI ledger entry"))?;
-        ensure!(
-            entry.status == "active",
-            "generated intrinsic {catalog_id} maps to non-active ABI ledger entry {}",
-            entry.abi_id
-        );
-        Ok(entry)
-    }
-}
-
-fn bind_generated_abi_ids(overlay: &mut OverlayFile, ledger: &AbiLedgerFile) -> Result<()> {
-    let index = AbiLedgerIndex::new(ledger)?;
-    for record in overlay
-        .intrinsics
-        .iter_mut()
-        .filter(|record| record.abi_id.is_empty())
-    {
-        let entry = index.active(&record.id)?;
-        ensure!(
-            entry.operation_key == record.operation_key,
-            "generated intrinsic {} operation key mismatch: ledger {:?}, derived {:?}",
-            record.id,
-            entry.operation_key,
-            record.operation_key
-        );
-        let derived_signature = raw_rust_signature(record);
-        ensure!(
-            entry.raw_rust_signature == derived_signature,
-            "generated intrinsic {} raw Rust signature mismatch: ledger {:?}, derived {:?}",
-            record.id,
-            entry.raw_rust_signature,
-            derived_signature
-        );
-        record.abi_id.clone_from(&entry.abi_id);
-    }
-    Ok(())
-}
-
-fn validate_abi_ledger(overlay: &OverlayFile, ledger: &AbiLedgerFile) -> Result<()> {
-    ensure!(
-        ledger.schema == 1,
-        "unsupported ABI ledger schema {}",
-        ledger.schema
-    );
-    ensure!(
-        ledger.intrinsic_abi == overlay.intrinsic_abi,
-        "ABI ledger v{} does not match overlay ABI v{}",
-        ledger.intrinsic_abi,
-        overlay.intrinsic_abi
-    );
-    ensure!(!ledger.entries.is_empty(), "ABI ledger contains no entries");
-
-    let overlay_by_abi_id: BTreeMap<_, _> = overlay
-        .intrinsics
-        .iter()
-        .map(|record| (record.abi_id.as_str(), record))
-        .collect();
-    let mut abi_ids = BTreeSet::new();
-    let mut catalog_ids = BTreeSet::new();
-    let mut operation_keys = BTreeSet::new();
-    let mut previous_abi_id: Option<&str> = None;
-    for entry in &ledger.entries {
-        validate_abi_id(&entry.abi_id)?;
-        if let Some(previous) = previous_abi_id {
-            ensure!(
-                previous < entry.abi_id.as_str(),
-                "ABI ledger IDs must be unique and append-only in ascending order: {} follows {}",
-                entry.abi_id,
-                previous
-            );
-        }
-        previous_abi_id = Some(&entry.abi_id);
-        insert_unique(&mut abi_ids, &entry.abi_id, "ABI ledger ID")?;
-        insert_unique(&mut catalog_ids, &entry.catalog_id, "ABI ledger catalog ID")?;
-        validate_operation_key(&entry.operation_key)?;
-        insert_unique(
-            &mut operation_keys,
-            &entry.operation_key,
-            "ABI ledger operation key",
-        )?;
-        ensure!(
-            !entry.catalog_id.is_empty()
-                && !entry.raw_rust_signature.result.is_empty()
-                && entry
-                    .raw_rust_signature
-                    .arguments
-                    .iter()
-                    .all(|argument| !argument.is_empty()),
-            "ABI ledger entry {} has incomplete identity data",
-            entry.abi_id
-        );
-
-        let overlay_record = overlay_by_abi_id.get(entry.abi_id.as_str()).copied();
-        match entry.status.as_str() {
-            "active" => {
-                let record = overlay_record.with_context(|| {
-                    format!(
-                        "active ABI ledger entry {} ({}) has no overlay record",
-                        entry.abi_id, entry.catalog_id
-                    )
-                })?;
-                validate_active_ledger_entry(entry, record)?;
-            }
-            "tombstone" => ensure!(
-                overlay_record.is_none(),
-                "tombstoned ABI ID {} cannot reappear in the overlay",
-                entry.abi_id
-            ),
-            status => bail!(
-                "ABI ledger entry {} has unsupported status {status:?}; expected active or tombstone",
-                entry.abi_id
-            ),
-        }
-    }
-
-    for record in &overlay.intrinsics {
-        ensure!(
-            abi_ids.contains(&record.abi_id),
-            "overlay intrinsic {} uses ABI ID {} with no ledger entry",
-            record.id,
-            record.abi_id
-        );
-    }
-    Ok(())
-}
-
-fn validate_active_ledger_entry(entry: &AbiLedgerEntry, record: &OverlayIntrinsic) -> Result<()> {
-    let comparisons = [
-        ("catalog ID", entry.catalog_id.as_str(), record.id.as_str()),
-        (
-            "operation key",
-            entry.operation_key.as_str(),
-            record.operation_key.as_str(),
-        ),
-    ];
-    for (field, ledger_value, overlay_value) in comparisons {
-        ensure!(
-            ledger_value == overlay_value,
-            "ABI ledger {} {field} mismatch: ledger {ledger_value:?}, overlay {overlay_value:?}",
-            entry.abi_id
-        );
-    }
-    let expected_signature = raw_rust_signature(record);
-    ensure!(
-        entry.raw_rust_signature == expected_signature,
-        "ABI ledger {} raw Rust signature mismatch: ledger {:?}, overlay {:?}",
-        entry.abi_id,
-        entry.raw_rust_signature,
-        expected_signature
-    );
-    Ok(())
-}
-
-fn raw_rust_signature(record: &OverlayIntrinsic) -> AbiRawRustSignature {
-    AbiRawRustSignature {
-        safe: record.safe,
-        arguments: record.rust_arguments.clone(),
-        result: record.rust_result.clone(),
-    }
-}
-
-fn validate_abi_id(abi_id: &str) -> Result<()> {
-    ensure!(
-        abi_id.len() == 5
-            && abi_id.starts_with('i')
-            && abi_id[1..].bytes().all(|byte| byte.is_ascii_digit()),
-        "intrinsic ABI ID `{abi_id}` must use the stable `iNNNN` form"
-    );
-    Ok(())
-}
-
-pub(crate) fn validate_operation_key(operation_key: &str) -> Result<()> {
-    ensure!(
-        !operation_key.is_empty()
-            && operation_key.split('.').all(|segment| {
-                !segment.is_empty()
-                    && segment.bytes().all(|byte| {
-                        byte.is_ascii_lowercase() || byte.is_ascii_digit() || byte == b'_'
-                    })
-            }),
-        "intrinsic operation key `{operation_key}` must contain dot-separated lowercase semantic components"
-    );
-    Ok(())
-}
-
-fn canonical_rust_path(intrinsic_abi: u32, abi_id: &str) -> String {
-    format!("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v{intrinsic_abi}::{abi_id}")
-}
-
-fn insert_unique(set: &mut BTreeSet<String>, value: &str, kind: &str) -> Result<()> {
-    ensure!(set.insert(value.to_owned()), "duplicate {kind}: {value}");
-    Ok(())
-}
-
-fn resolve_policy_source(policy: &OverlayIntrinsic) -> Result<IntrinsicSource> {
-    match (&policy.source, &policy.source_record) {
-        (None, Some(source_record)) => Ok(IntrinsicSource::LlvmImported {
-            source_record: source_record.clone(),
-        }),
-        (Some(source @ IntrinsicSource::PtxNative { .. }), None) => Ok(source.clone()),
-        (Some(IntrinsicSource::LlvmImported { source_record }), None) => {
-            ensure!(
-                !source_record.trim().is_empty(),
-                "{} has an empty imported LLVM source record",
-                policy.id
-            );
-            Ok(IntrinsicSource::LlvmImported {
-                source_record: source_record.clone(),
-            })
-        }
-        (Some(_), Some(_)) => bail!(
-            "{} mixes tagged source provenance with the legacy source_record field",
-            policy.id
-        ),
-        (None, None) => bail!("{} has no intrinsic source provenance", policy.id),
-    }
-}
-
-fn validate_policy(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-    declaration: Option<&ImportedIntrinsic>,
-    intrinsic_abi: u32,
-) -> Result<()> {
-    validate_abi_id(&policy.abi_id)?;
-    parse_ptx_version(&policy.minimum_ptx, &policy.id)?;
-    parse_hardware_target(policy)?;
-    policy.expected_ptx.validate().map_err(|reason| {
-        anyhow::anyhow!(
-            "{} has an invalid expected PTX pattern: {reason}",
-            policy.id
-        )
-    })?;
-    let public_path = format!(
-        "cuda_intrinsics::{}::{}",
-        policy.rust_module, policy.rust_name
-    );
-    ensure!(
-        policy.public_rust_path == public_path,
-        "{} public Rust path must be {}",
-        policy.id,
-        public_path
-    );
-    let canonical_path = canonical_rust_path(intrinsic_abi, &policy.abi_id);
-    ensure!(
-        canonical_path != policy.public_rust_path
-            && !policy
-                .compatibility_rust_paths
-                .iter()
-                .any(|path| path == &canonical_path || path == &policy.public_rust_path),
-        "{} must keep canonical, public, and compatibility Rust paths distinct",
-        policy.id
-    );
-    match (source, declaration) {
-        (IntrinsicSource::LlvmImported { .. }, Some(declaration)) => {
-            ensure!(
-                policy.llvm_symbol.as_deref() == Some(declaration.llvm_name.as_str()),
-                "{} LLVM symbol mismatch: imported {}, overlay {:?}",
-                policy.id,
-                declaration.llvm_name,
-                policy.llvm_symbol
-            );
-            ensure!(
-                declaration.arguments == policy.llvm_arguments,
-                "{} LLVM argument signature mismatch: imported {:?}, overlay {:?}",
-                policy.id,
-                declaration.arguments,
-                policy.llvm_arguments
-            );
-            ensure!(
-                declaration.results == policy.llvm_results,
-                "{} LLVM result signature mismatch: imported {:?}, overlay {:?}",
-                policy.id,
-                declaration.results,
-                policy.llvm_results
-            );
-        }
-        (IntrinsicSource::PtxNative { instruction }, None) => ensure!(
-            !instruction.trim().is_empty()
-                && policy.llvm_symbol.is_none()
-                && policy.resolved_llvm_symbol.is_none()
-                && policy.llvm_arguments.is_empty()
-                && policy.llvm_results.is_empty(),
-            "{} PTX-native source must not invent LLVM source facts",
-            policy.id
-        ),
-        _ => bail!(
-            "{} source kind and imported declaration disagree",
-            policy.id
-        ),
-    }
-    match policy.family.as_str() {
-        "sreg" => validate_sreg_policy(policy, source, declaration)?,
-        "ldmatrix" => validate_ldmatrix_policy(
-            policy,
-            declaration.context("ldmatrix requires imported LLVM declaration")?,
-        )?,
-        "stmatrix" => validate_stmatrix_policy(
-            policy,
-            declaration.context("stmatrix requires imported LLVM declaration")?,
-        )?,
-        "packed_atomic" => validate_packed_atomic_policy(policy, source)?,
-        "redux" => validate_redux_policy(
-            policy,
-            declaration.context("redux requires imported LLVM declaration")?,
-        )?,
-        "dotprod" => validate_dot_product_policy(
-            policy,
-            declaration.context("dotprod requires imported LLVM declaration")?,
-        )?,
-        "sync" => validate_sync_policy(
-            policy,
-            declaration.context("sync requires imported LLVM declaration")?,
-        )?,
-        "vote" => validate_vote_policy(
-            policy,
-            declaration.context("vote requires imported LLVM declaration")?,
-        )?,
-        "active_mask" => validate_active_mask_policy(
-            policy,
-            declaration.context("active_mask requires imported LLVM declaration")?,
-        )?,
-        "warp_match" => validate_warp_match_policy(
-            policy,
-            declaration.context("warp_match requires imported LLVM declaration")?,
-        )?,
-        "elect" => validate_elect_policy(
-            policy,
-            declaration.context("elect requires imported LLVM declaration")?,
-        )?,
-        "warp_barrier" => validate_warp_barrier_policy(
-            policy,
-            declaration.context("warp_barrier requires imported LLVM declaration")?,
-        )?,
-        "warp_shuffle" => validate_warp_shuffle_policy(policy, declaration)?,
-        "packed_alu" => validate_packed_alu_policy(policy, source, declaration)?,
-        "integer_minmax" => validate_integer_minmax_policy(policy, source, declaration)?,
-        "packed_conversion" => validate_packed_conversion_policy(policy, source, declaration)?,
-        "scalar_conversion" => validate_scalar_conversion_policy(
-            policy,
-            declaration.context("scalar_conversion requires imported LLVM declaration")?,
-        )?,
-        "scalar_arithmetic" => validate_scalar_arithmetic_policy(
-            policy,
-            declaration.context("scalar_arithmetic requires imported LLVM declaration")?,
-        )?,
-        "scalar_math" => validate_scalar_math_policy(policy, declaration)?,
-        "extended_minmax" => validate_extended_minmax_policy(
-            policy,
-            declaration.context("extended_minmax requires imported LLVM declaration")?,
-        )?,
-        "cp_async_copy" => validate_cp_async_copy_policy(
-            policy,
-            declaration.context("cp_async_copy requires imported LLVM declaration")?,
-        )?,
-        "cp_async_control" => validate_cp_async_control_policy(
-            policy,
-            declaration.context("cp_async_control requires imported LLVM declaration")?,
-        )?,
-        "cp_async_mbarrier" => validate_cp_async_mbarrier_policy(
-            policy,
-            declaration.context("cp_async_mbarrier requires imported LLVM declaration")?,
-        )?,
-        "mbarrier_basic" => validate_mbarrier_basic_policy(
-            policy,
-            declaration.context("mbarrier_basic requires imported LLVM declaration")?,
-        )?,
-        "movmatrix" => validate_movmatrix_policy(policy, source)?,
-        "mbarrier_extended" => validate_mbarrier_extended_policy(policy, source, declaration)?,
-        "register_mma" => validate_register_mma_policy(
-            policy,
-            declaration.context("register_mma requires imported LLVM declaration")?,
-        )?,
-        "sparse_mma" => validate_sparse_mma_policy(
-            policy,
-            declaration.context("sparse_mma requires imported LLVM declaration")?,
-        )?,
-        "prmt" => validate_prmt_policy(
-            policy,
-            declaration.context("prmt requires imported LLVM declaration")?,
-        )?,
-        "cluster_barrier" => validate_cluster_barrier_policy(
-            policy,
-            declaration.context("cluster_barrier requires imported LLVM declaration")?,
-        )?,
-        "debug_control" => validate_debug_control_policy(policy, source)?,
-        "cluster_memory" => validate_cluster_memory_policy(policy, source, declaration)?,
-        "clc" => validate_clc_policy(
-            policy,
-            declaration.context("clc requires imported LLVM declaration")?,
-        )?,
-        "wgmma_control" => validate_wgmma_control_policy(
-            policy,
-            declaration.context("wgmma_control requires imported LLVM declaration")?,
-        )?,
-        "tma" => validate_tma_policy(
-            policy,
-            declaration.context("tma requires imported LLVM declaration")?,
-        )?,
-        "counted_barrier" | "grid_dependency" | "register_control" => {
-            validate_execution_control_policy(
-                policy,
-                declaration.context("execution-control requires imported LLVM declaration")?,
-            )?
-        }
-        "tcgen05" => validate_tcgen05_policy(
-            policy,
-            declaration.context("tcgen05 requires imported LLVM declaration")?,
-        )?,
-        family => bail!("{} uses unsupported generated family {family:?}", policy.id),
-    }
-    ensure!(
-        (policy.family == "movmatrix") == policy.movmatrix.is_some(),
-        "{} mixes the movmatrix contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "mbarrier_extended") == policy.mbarrier_extended.is_some(),
-        "{} mixes the extended-mbarrier contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "register_mma") == policy.register_mma.is_some(),
-        "{} mixes the register-MMA contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "sparse_mma") == policy.sparse_mma.is_some(),
-        "{} mixes the sparse-MMA contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "prmt") == policy.prmt.is_some(),
-        "{} mixes the prmt contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "cluster_barrier") == policy.cluster_barrier.is_some(),
-        "{} mixes the cluster-barrier contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "wgmma_control") == policy.wgmma_control.is_some(),
-        "{} mixes the WGMMA-control contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "tma") == policy.tma.is_some(),
-        "{} mixes the TMA contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        policy.special_register.is_none() || policy.family == "sreg",
-        "{} mixes the special-register contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "debug_control") == policy.debug_control.is_some(),
-        "{} mixes the debug-control contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "cluster_memory") == policy.cluster_memory.is_some(),
-        "{} mixes the cluster-memory contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "clc") == policy.clc.is_some(),
-        "{} mixes the CLC contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "tma") == policy.tma.is_some(),
-        "{} mixes the TMA contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "tcgen05") == policy.tcgen05.is_some(),
-        "{} mixes the tcgen05 contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "scalar_conversion") == policy.scalar_conversion.is_some(),
-        "{} mixes the scalar-conversion contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "scalar_arithmetic") == policy.scalar_arithmetic.is_some(),
-        "{} mixes the scalar-arithmetic contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "scalar_math") == policy.scalar_math.is_some(),
-        "{} mixes the scalar-math contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        (policy.family == "extended_minmax") == policy.extended_minmax.is_some(),
-        "{} mixes the extended-minmax contract with another generated family",
-        policy.id
-    );
-    ensure!(
-        !policy.execution_scope.trim().is_empty(),
-        "{} has no execution scope",
-        policy.id
-    );
-    ensure!(
-        !policy.ptx_isa_version.trim().is_empty()
-            && !policy.ptx_isa_section.trim().is_empty()
-            && policy.ptx_isa_url.starts_with("https://docs.nvidia.com/"),
-        "{} has incomplete or non-authoritative PTX ISA provenance",
-        policy.id
-    );
-    match (policy.safe, policy.safe_allowlist_reason.as_deref()) {
-        (true, Some(reason)) if !reason.trim().is_empty() => {}
-        (true, _) => bail!(
-            "{} is safe but has no nonempty safe_allowlist_reason",
-            policy.id
-        ),
-        (false, Some(reason)) if !reason.trim().is_empty() => bail!(
-            "{} is unsafe but has a safe_allowlist_reason; safe exceptions apply only to safe items",
-            policy.id
-        ),
-        (false, _) => {}
-    }
-    if let Some(declaration) = declaration {
-        if policy.pure {
-            ensure!(
-                declaration
-                    .classes
-                    .iter()
-                    .any(|class| class == "NVVMPureIntrinsic")
-                    || (matches!(
-                        policy.family.as_str(),
-                        "packed_alu" | "scalar_arithmetic" | "extended_minmax"
-                    ) && declaration
-                        .properties
-                        .iter()
-                        .any(|property| property == "IntrNoMem")
-                        && declaration
-                            .properties
-                            .iter()
-                            .any(|property| property == "IntrSpeculatable"))
-                    || (policy.family == "scalar_math"
-                        && declaration
-                            .properties
-                            .iter()
-                            .any(|property| property == "IntrNoMem")),
-                "{} is marked pure, but its imported declaration is not an NVVMPureIntrinsic",
-                policy.id
-            );
-        }
-        if policy.memory == "none" {
-            ensure!(
-                declaration
-                    .properties
-                    .iter()
-                    .any(|property| property == "IntrNoMem"),
-                "{} is marked no-memory, but its imported declaration lacks IntrNoMem",
-                policy.id
-            );
-        }
-        let imported_convergent = declaration
-            .properties
-            .iter()
-            .any(|property| property == "IntrConvergent");
-        let convergence_supplied_by_ptx =
-            (matches!(policy.family.as_str(), "register_mma" | "sparse_mma")
-                && (policy.register_mma.is_some() || policy.sparse_mma.is_some())
-                || (policy.family == "cluster_memory"
-                    && policy.cluster_memory.is_some()
-                    && policy.backend_lowerings.iter().all(|lowering| {
-                        lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    }))
-                || (policy.family == "mbarrier_extended"
-                    && policy.mbarrier_extended.is_some()
-                    && policy.backend_lowerings.iter().all(|lowering| {
-                        lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    }))
-                || (policy.family == "tcgen05"
-                    && policy.tcgen05.is_some()
-                    && policy.backend_lowerings.iter().all(|lowering| {
-                        lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    })))
-                && policy.convergent
-                && !imported_convergent;
-        ensure!(
-            imported_convergent == policy.convergent || convergence_supplied_by_ptx,
-            "{} convergence mismatch: imported {}, overlay {}",
-            policy.id,
-            imported_convergent,
-            policy.convergent
-        );
-        let selectionless_closed_family = (policy.family == "packed_conversion"
-            && policy.packed_conversion.is_some())
-            || (policy.family == "prmt" && policy.prmt.is_some())
-            || (policy.family == "clc"
-                && policy.clc.as_ref().is_some_and(|clc| {
-                    matches!(
-                        clc.operation,
-                        ClcOperation::QueryIsCanceled
-                            | ClcOperation::QueryGetFirstCtaidX
-                            | ClcOperation::QueryGetFirstCtaidY
-                            | ClcOperation::QueryGetFirstCtaidZ
-                    )
-                }))
-            || (policy.family == "sreg"
-                && policy.special_register.as_ref().is_some_and(|special| {
-                    matches!(
-                        special.register,
-                        SpecialRegisterKind::Envreg1 | SpecialRegisterKind::Envreg2
-                    )
-                }))
-            || policy.family == "stmatrix"
-            || (policy.family == "tma"
-                && policy.tma.as_ref().is_some_and(|tma| {
-                    matches!(
-                        tma.operation,
-                        TmaOperation::Reduce
-                            | TmaOperation::PrefetchTensorMap
-                            | TmaOperation::ReplaceBoxDim
-                            | TmaOperation::ReplaceElementStride
-                            | TmaOperation::ReplaceElementType
-                            | TmaOperation::ReplaceFillMode
-                            | TmaOperation::ReplaceGlobalAddress
-                            | TmaOperation::ReplaceGlobalDim
-                            | TmaOperation::ReplaceGlobalStride
-                            | TmaOperation::ReplaceInterleaveLayout
-                            | TmaOperation::ReplaceRank
-                            | TmaOperation::ReplaceSwizzleAtomicity
-                            | TmaOperation::ReplaceSwizzleMode
-                    )
-                }))
-            || (policy.family == "tcgen05"
-                && policy.tcgen05.as_ref().is_some_and(|tcgen05| {
-                    tcgen05.source_contract
-                        == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
-                }))
-            || (policy.family == "scalar_math"
-                && policy.scalar_math.as_ref().is_some_and(|sm| {
-                    // Tanh is absent here only because it is PTX-native (no
-                    // imported declaration), so this check never sees it.
-                    matches!(
-                        sm.operation,
-                        ScalarMathOperation::Sin
-                            | ScalarMathOperation::Cos
-                            | ScalarMathOperation::Ex2
-                            | ScalarMathOperation::Lg2
-                            | ScalarMathOperation::Rsqrt
-                    )
-                }));
-        ensure!(
-            !declaration.selections.is_empty() || selectionless_closed_family,
-            "{} has a declaration but no NVPTX TableGen selection record",
-            policy.id
-        );
-        let mut matching_selections = Vec::new();
-        for selection in &declaration.selections {
-            if selection_matches_policy(policy, selection)? {
-                matching_selections.push(selection);
-            }
-        }
-        let expected_selection_count = match policy.family.as_str() {
-            "vote" | "warp_barrier" | "elect" => 2,
-            "warp_match" => 4,
-            "warp_shuffle" => 8,
-            "counted_barrier" => 4,
-            "packed_conversion" | "prmt" | "stmatrix" => 0,
-            "tma"
-                if policy.tma.as_ref().is_some_and(|tma| {
-                    matches!(
-                        tma.operation,
-                        TmaOperation::Reduce
-                            | TmaOperation::PrefetchTensorMap
-                            | TmaOperation::ReplaceBoxDim
-                            | TmaOperation::ReplaceElementStride
-                            | TmaOperation::ReplaceElementType
-                            | TmaOperation::ReplaceFillMode
-                            | TmaOperation::ReplaceGlobalAddress
-                            | TmaOperation::ReplaceGlobalDim
-                            | TmaOperation::ReplaceGlobalStride
-                            | TmaOperation::ReplaceInterleaveLayout
-                            | TmaOperation::ReplaceRank
-                            | TmaOperation::ReplaceSwizzleAtomicity
-                            | TmaOperation::ReplaceSwizzleMode
-                    )
-                }) =>
-            {
-                0
-            }
-            "tcgen05"
-                if policy
-                    .tcgen05
-                    .as_ref()
-                    .and_then(|tcgen05| tcgen05.mma.as_ref())
-                    .is_some() =>
-            {
-                let mma = policy.tcgen05.as_ref().unwrap().mma.as_ref().unwrap();
-                if mma.alias.is_some() {
-                    1
-                } else if tcgen05_mma_is_ws(mma.form) {
-                    64
-                } else if tcgen05_mma_is_ashift(mma.form) {
-                    16
-                } else {
-                    32
-                }
-            }
-            "tcgen05"
-                if policy.tcgen05.as_ref().is_some_and(|tcgen05| {
-                    tcgen05.source_contract != Tcgen05SourceContract::ExactTablegenSelection
-                }) =>
-            {
-                0
-            }
-            "clc"
-                if policy.clc.as_ref().is_some_and(|clc| {
-                    matches!(
-                        clc.operation,
-                        ClcOperation::QueryIsCanceled
-                            | ClcOperation::QueryGetFirstCtaidX
-                            | ClcOperation::QueryGetFirstCtaidY
-                            | ClcOperation::QueryGetFirstCtaidZ
-                    )
-                }) =>
-            {
-                0
-            }
-            "sreg"
-                if policy.special_register.as_ref().is_some_and(|special| {
-                    matches!(
-                        special.register,
-                        SpecialRegisterKind::Envreg1 | SpecialRegisterKind::Envreg2
-                    )
-                }) =>
-            {
-                0
-            }
-            "mbarrier_extended"
-                if policy.mbarrier_extended.as_ref().is_some_and(|mbarrier| {
-                    matches!(
-                        mbarrier.operation,
-                        MbarrierExtendedOperation::ArriveExpectTxCta
-                            | MbarrierExtendedOperation::ArriveExpectTxCluster
-                            | MbarrierExtendedOperation::TryWaitParityCta
-                            | MbarrierExtendedOperation::TryWaitParityCluster
-                    )
-                }) =>
-            {
-                0
-            }
-            "mbarrier_extended" if policy.id == "nanosleep" => 2,
-            "cp_async_copy"
-                if policy
-                    .cp_async_copy
-                    .as_ref()
-                    .is_some_and(|copy| copy.source_size == CpAsyncSourceSize::Runtime) =>
-            {
-                2
-            }
-            "cluster_memory" if policy.id == "map_shared_rank" => 2,
-            "scalar_math"
-                if policy.scalar_math.as_ref().is_some_and(|sm| {
-                    matches!(
-                        sm.operation,
-                        ScalarMathOperation::Sin
-                            | ScalarMathOperation::Cos
-                            | ScalarMathOperation::Ex2
-                            | ScalarMathOperation::Lg2
-                            | ScalarMathOperation::Rsqrt
-                    )
-                }) =>
-            {
-                0
-            }
-            _ => 1,
-        };
-        ensure!(
-            matching_selections.len() == expected_selection_count,
-            "{} expected PTX {:?} does not agree with its closed imported selection set",
-            policy.id,
-            policy.expected_ptx
-        );
-        for selection in matching_selections {
-            validate_selected_target_predicates(policy, selection)?;
-        }
-    }
-    Ok(())
-}
-
-fn selection_matches_policy(
-    policy: &OverlayIntrinsic,
-    selection: &crate::model::ImportedSelection,
-) -> Result<bool, ParseError> {
-    if policy.family == "wgmma_control" {
-        let Some(control) = &policy.wgmma_control else {
-            return Ok(false);
-        };
-        let recipe = wgmma_control_recipe(control.mode);
-        let selection_shape_matches = if control.mode == WgmmaControlMode::WaitGroup {
-            selection.asm == "wgmma.wait_group.sync.aligned \t$n;"
-        } else {
-            policy.expected_ptx.matches(&selection.asm)?
-        };
-        return Ok(selection.source_record == recipe.selection_record
-            && selection_shape_matches
-            && selection.predicates == ["Subtarget->getPTXVersion() >= 80", "hasSM90a"]
-            && selection.constraints.is_empty());
-    }
-
-    if policy.family == "tma" {
-        return Ok(selection_matches_tma_policy(policy, selection));
-    }
-    if matches!(
-        policy.family.as_str(),
-        "counted_barrier" | "grid_dependency" | "register_control"
-    ) {
-        let Some(operation) = ExecutionControlOperation::from_catalog_id(&policy.id) else {
-            return Ok(false);
-        };
-        let recipe = execution_control_recipe(operation);
-        return Ok(recipe
-            .selection_records
-            .contains(&selection.source_record.as_str())
-            && selection.asm == recipe.selection_asm
-            && selection.predicates == recipe.selection_predicates
-            && selection.constraints.is_empty());
-    }
-    if policy.family == "tcgen05" {
-        let Some(tcgen05) = &policy.tcgen05 else {
-            return Ok(false);
-        };
-        if let Some(mma) = &tcgen05.mma {
-            let expected = if mma.alias.is_some() {
-                BTreeSet::from([if tcgen05_mma_is_ws(mma.form) {
-                    tcgen05_mma_selection_asm(
-                        mma.form,
-                        Tcgen05MmaKind::F8f6f4,
-                        1,
-                        None,
-                        Some(0),
-                        Some(Tcgen05MmaBUsage::Discard),
-                    )
-                } else {
-                    tcgen05_mma_selection_asm(
-                        mma.form,
-                        Tcgen05MmaKind::F8f6f4,
-                        1,
-                        Some("discard"),
-                        None,
-                        None,
-                    )
-                }])
-            } else {
-                tcgen05_mma_valid_selection_asms(mma.form)
-            };
-            return Ok(expected.contains(&selection.asm)
-                && selection.predicates
-                    == [if selection.asm.contains(".kind::i8.") {
-                        "Subtarget->hasTcgen05MMAI8Kind()"
-                    } else {
-                        "Subtarget->hasTcgen05InstSupport()"
-                    }]
-                && selection.constraints.is_empty());
-        }
-        if tcgen05.source_contract != Tcgen05SourceContract::ExactTablegenSelection {
-            return Ok(false);
-        }
-        if let Some(cp) = tcgen05.cp {
-            let recipe = tcgen05_cp_member_recipe(cp.member);
-            let group = match cp.group {
-                Tcgen05CpGroup::Cg1 => 1,
-                Tcgen05CpGroup::Cg2 => 2,
-            };
-            return Ok(selection.source_record
-                == format!("TCGEN05_CP_{}_cg{group}", recipe.selection_stem)
-                && selection.asm
-                    == format!(
-                        "tcgen05.cp.cta_group::{group}.{} \t[$tmem_addr], $sdesc;",
-                        recipe.ptx_suffix
-                    )
-                && selection.predicates == ["Subtarget->hasTcgen05InstSupport()"]
-                && selection.constraints.is_empty());
-        }
-        let recipe = tcgen05_recipe(tcgen05.operation);
-        return Ok(
-            recipe.selection_record == Some(selection.source_record.as_str())
-                && recipe.selection_asm == Some(selection.asm.as_str())
-                && selection.constraints.is_empty(),
-        );
-    }
-    if policy.family == "sparse_mma" {
-        let Some(last) = policy.expected_ptx.operands.last() else {
-            return Ok(false);
-        };
-        if *last != OperandPattern::Immediate {
-            return Ok(false);
-        }
-        let mut selection_shape = policy.expected_ptx.clone();
-        *selection_shape.operands.last_mut().unwrap() = OperandPattern::RegisterOrImmediate;
-        return Ok(selection_shape.matches(&selection.asm)? && selection.constraints.is_empty());
-    }
-    if policy.family == "sync" {
-        if policy.id == "sync_threads" {
-            return Ok(selection.source_record == "BARRIER_CTA_SYNC_ALIGNED_ALL_i"
-                && selection.asm == "bar.sync \t$i;"
-                && selection.predicates.is_empty()
-                && selection.constraints.is_empty());
-        }
-        let Some(scope) = threadfence_scope_for_id(&policy.id) else {
-            return Ok(false);
-        };
-        let recipe = threadfence_recipe(scope);
-        return Ok(selection.source_record == recipe.selection_record
-            && selection.asm == format!("membar.{};", recipe.ptx_level)
-            && selection.predicates.is_empty()
-            && selection.constraints.is_empty());
-    }
-
-    if policy.family == "vote" {
-        let Some(vote) = &policy.vote else {
-            return Ok(false);
-        };
-        let recipe = vote_recipe(vote.mode);
-        return Ok([recipe.immediate_selection, recipe.register_selection]
-            .contains(&selection.source_record.as_str())
-            && policy.expected_ptx.matches(&selection.asm)?
-            && selection.constraints.address_space.is_none()
-            && selection.constraints.immediate_bindings.is_empty());
-    }
-
-    if policy.family == "warp_match" {
-        let Some(warp_match) = &policy.warp_match else {
-            return Ok(false);
-        };
-        let recipe = warp_match_recipe(warp_match.mode, warp_match.value_width);
-        return Ok(recipe
-            .selections
-            .contains(&selection.source_record.as_str())
-            && policy.expected_ptx.matches(&selection.asm)?
-            && selection.constraints.is_empty());
-    }
-
-    if policy.family == "elect" {
-        return Ok(["INT_ELECT_SYNC_I", "INT_ELECT_SYNC_R"]
-            .contains(&selection.source_record.as_str())
-            && selection.asm == "elect.sync \t$dest|$pred, $mask;"
-            && selection.constraints.is_empty());
-    }
-
-    if policy.family == "warp_barrier" {
-        return Ok(policy.warp_barrier.is_some()
-            && ["INT_BAR_WARP_SYNC_I", "INT_BAR_WARP_SYNC_R"]
-                .contains(&selection.source_record.as_str())
-            && policy.expected_ptx.matches(&selection.asm)?
-            && selection.constraints.is_empty());
-    }
-
-    if policy.family == "warp_shuffle" {
-        let Some(shuffle) = &policy.warp_shuffle else {
-            return Ok(false);
-        };
-        let recipe = warp_shuffle_recipe(shuffle.mode, shuffle.value_kind);
-        return Ok(selection.asm
-            == format!(
-                "shfl.sync.{}.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                recipe.ptx_mode
-            )
-            && selection.constraints.is_empty());
-    }
-
-    if policy.family == "cp_async_copy" {
-        let Some(copy) = &policy.cp_async_copy else {
-            return Ok(false);
-        };
-        let Some(recipe) = cp_async_copy_recipe(copy) else {
-            return Ok(false);
-        };
-        return Ok(recipe
-            .selections
-            .contains(&selection.source_record.as_str())
-            && policy.expected_ptx.matches(&selection.asm)?
-            && selection.constraints.is_empty());
-    }
-
-    if policy.family == "cp_async_control" {
-        let Some(control) = &policy.cp_async_control else {
-            return Ok(false);
-        };
-        let recipe = cp_async_control_recipe(control.operation);
-        let instruction_matches = if control.operation == CpAsyncControlOperation::WaitGroup {
-            selection.asm == "cp.async.wait_group \t$n;"
-        } else {
-            policy.expected_ptx.matches(&selection.asm)?
-        };
-        return Ok(selection.source_record == recipe.selection
-            && instruction_matches
-            && selection.constraints.is_empty());
-    }
-
-    if policy.family == "cp_async_mbarrier" {
-        let Some(bridge) = &policy.cp_async_mbarrier else {
-            return Ok(false);
-        };
-        let recipe = cp_async_mbarrier_recipe(bridge.operation, bridge.state_space);
-        return Ok(selection.source_record == recipe.selection
-            && selection.asm == recipe.selection_asm
-            && selection.constraints.is_empty());
-    }
-
-    if policy.family == "mbarrier_basic" {
-        let Some(mbarrier) = &policy.mbarrier_basic else {
-            return Ok(false);
-        };
-        let recipe = mbarrier_basic_recipe(mbarrier.operation);
-        return Ok(selection.source_record == recipe.selection
-            && policy.expected_ptx.matches(&selection.asm)?
-            && selection.constraints.is_empty());
-    }
-
-    if !policy.expected_ptx.matches(&selection.asm)?
-        || policy
-            .selected_address_space
-            .is_some_and(|address_space| selection.constraints.address_space != Some(address_space))
-    {
-        return Ok(false);
-    }
-
-    let Some(dot_product) = &policy.dot_product else {
-        return Ok(true);
-    };
-    if selection.constraints.address_space.is_some() {
-        return Ok(false);
-    }
-    Ok(match dot_product.adapter {
-        DotProductAdapter::DirectThreeOperands => {
-            selection.constraints.immediate_bindings.is_empty()
-        }
-        DotProductAdapter::InsertLowHalfFalse => {
-            selection.constraints.immediate_bindings.len() == 1
-                && selection.constraints.immediate_bindings[0].argument_index == 2
-                && selection.constraints.immediate_bindings[0].value == 0
-        }
-    })
-}
-
-fn selection_matches_tma_policy(
-    policy: &OverlayIntrinsic,
-    selection: &crate::model::ImportedSelection,
-) -> bool {
-    let Some(tma) = &policy.tma else {
-        return false;
-    };
-    let operation = tma.operation;
-    if matches!(
-        operation,
-        TmaOperation::Reduce
-            | TmaOperation::PrefetchTensorMap
-            | TmaOperation::ReplaceBoxDim
-            | TmaOperation::ReplaceElementStride
-            | TmaOperation::ReplaceElementType
-            | TmaOperation::ReplaceFillMode
-            | TmaOperation::ReplaceGlobalAddress
-            | TmaOperation::ReplaceGlobalDim
-            | TmaOperation::ReplaceGlobalStride
-            | TmaOperation::ReplaceInterleaveLayout
-            | TmaOperation::ReplaceRank
-            | TmaOperation::ReplaceSwizzleAtomicity
-            | TmaOperation::ReplaceSwizzleMode
-    ) {
-        return false;
-    }
-    let (source_record, asm) = match operation {
-        TmaOperation::G2sTile1d => (
-            "TMA_G2S_TILE_CG0_1D",
-            "cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0}}], [$mbar];",
-        ),
-        TmaOperation::G2sTile2d => (
-            "TMA_G2S_TILE_CG0_2D",
-            "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar];",
-        ),
-        TmaOperation::G2sTile2dMulticast => (
-            "TMA_G2S_TILE_CG0_2D_MC",
-            "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
-        ),
-        TmaOperation::G2sTile2dMulticastCg2 => (
-            "TMA_G2S_TILE_2D_MC",
-            "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
-        ),
-        TmaOperation::G2sTile3d => (
-            "TMA_G2S_TILE_CG0_3D",
-            "cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2}}], [$mbar];",
-        ),
-        TmaOperation::G2sTile4d => (
-            "TMA_G2S_TILE_CG0_4D",
-            "cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3}}], [$mbar];",
-        ),
-        TmaOperation::G2sTile5d => (
-            "TMA_G2S_TILE_CG0_5D",
-            "cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$mbar];",
-        ),
-        TmaOperation::S2gTile1d => (
-            "TMA_TENSOR_S2G_TILE_1D",
-            "cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [$tmap, {{$d0}}], [$src];",
-        ),
-        TmaOperation::S2gTile2d => (
-            "TMA_TENSOR_S2G_TILE_2D",
-            "cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1}}], [$src];",
-        ),
-        TmaOperation::S2gTile3d => (
-            "TMA_TENSOR_S2G_TILE_3D",
-            "cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2}}], [$src];",
-        ),
-        TmaOperation::S2gTile4d => (
-            "TMA_TENSOR_S2G_TILE_4D",
-            "cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3}}], [$src];",
-        ),
-        TmaOperation::S2gTile5d => (
-            "TMA_TENSOR_S2G_TILE_5D",
-            "cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$src];",
-        ),
-        TmaOperation::CommitGroup => ("CP_ASYNC_BULK_COMMIT_GROUP", "cp.async.bulk.commit_group;"),
-        TmaOperation::WaitGroup => ("CP_ASYNC_BULK_WAIT_GROUP", "cp.async.bulk.wait_group \t$n;"),
-        TmaOperation::WaitGroupRead => (
-            "CP_ASYNC_BULK_WAIT_GROUP_READ",
-            "cp.async.bulk.wait_group.read \t$n;",
-        ),
-        TmaOperation::PrefetchTile1d => (
-            "TMA_TENSOR_PF_TILE_1D",
-            "cp.async.bulk.prefetch.tensor.1d.L2.global.tile [$tmap, {{$d0}}];",
-        ),
-        TmaOperation::PrefetchTile2d => (
-            "TMA_TENSOR_PF_TILE_2D",
-            "cp.async.bulk.prefetch.tensor.2d.L2.global.tile [$tmap, {{$d0, $d1}}];",
-        ),
-        TmaOperation::PrefetchTile3d => (
-            "TMA_TENSOR_PF_TILE_3D",
-            "cp.async.bulk.prefetch.tensor.3d.L2.global.tile [$tmap, {{$d0, $d1, $d2}}];",
-        ),
-        TmaOperation::PrefetchTile4d => (
-            "TMA_TENSOR_PF_TILE_4D",
-            "cp.async.bulk.prefetch.tensor.4d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3}}];",
-        ),
-        TmaOperation::PrefetchTile5d => (
-            "TMA_TENSOR_PF_TILE_5D",
-            "cp.async.bulk.prefetch.tensor.5d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
-        ),
-        TmaOperation::PrefetchTileGather4TwoDimensional => (
-            "TMA_TENSOR_PF_TILE_GATHER4_2D",
-            "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4 [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
-        ),
-        TmaOperation::PrefetchTile1dCacheHint => (
-            "TMA_TENSOR_PF_TILE_1D_CH",
-            "cp.async.bulk.prefetch.tensor.1d.L2.global.tile.L2::cache_hint [$tmap, {{$d0}}], $ch;",
-        ),
-        TmaOperation::PrefetchTile2dCacheHint => (
-            "TMA_TENSOR_PF_TILE_2D_CH",
-            "cp.async.bulk.prefetch.tensor.2d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1}}], $ch;",
-        ),
-        TmaOperation::PrefetchTile3dCacheHint => (
-            "TMA_TENSOR_PF_TILE_3D_CH",
-            "cp.async.bulk.prefetch.tensor.3d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2}}], $ch;",
-        ),
-        TmaOperation::PrefetchTile4dCacheHint => (
-            "TMA_TENSOR_PF_TILE_4D_CH",
-            "cp.async.bulk.prefetch.tensor.4d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3}}], $ch;",
-        ),
-        TmaOperation::PrefetchTile5dCacheHint => (
-            "TMA_TENSOR_PF_TILE_5D_CH",
-            "cp.async.bulk.prefetch.tensor.5d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
-        ),
-        TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint => (
-            "TMA_TENSOR_PF_TILE_GATHER4_2D_CH",
-            "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
-        ),
-        TmaOperation::FenceProxyTensorMapAcquireCluster => (
-            "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CLUSTER",
-            "fence.proxy.tensormap::generic.acquire.cluster [$addr], 128;",
-        ),
-        TmaOperation::FenceProxyTensorMapAcquireCta => (
-            "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CTA",
-            "fence.proxy.tensormap::generic.acquire.cta [$addr], 128;",
-        ),
-        TmaOperation::FenceProxyTensorMapAcquireGpu => (
-            "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_GPU",
-            "fence.proxy.tensormap::generic.acquire.gpu [$addr], 128;",
-        ),
-        TmaOperation::FenceProxyTensorMapAcquireSystem => (
-            "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_SYS",
-            "fence.proxy.tensormap::generic.acquire.sys [$addr], 128;",
-        ),
-        TmaOperation::FenceProxyTensorMapReleaseCluster => (
-            "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CLUSTER",
-            "fence.proxy.tensormap::generic.release.cluster;",
-        ),
-        TmaOperation::FenceProxyTensorMapReleaseCta => (
-            "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CTA",
-            "fence.proxy.tensormap::generic.release.cta;",
-        ),
-        TmaOperation::FenceProxyTensorMapReleaseGpu => (
-            "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_GPU",
-            "fence.proxy.tensormap::generic.release.gpu;",
-        ),
-        TmaOperation::FenceProxyTensorMapReleaseSystem => (
-            "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_SYS",
-            "fence.proxy.tensormap::generic.release.sys;",
-        ),
-        TmaOperation::Reduce
-        | TmaOperation::PrefetchTensorMap
-        | TmaOperation::ReplaceBoxDim
-        | TmaOperation::ReplaceElementStride
-        | TmaOperation::ReplaceElementType
-        | TmaOperation::ReplaceFillMode
-        | TmaOperation::ReplaceGlobalAddress
-        | TmaOperation::ReplaceGlobalDim
-        | TmaOperation::ReplaceGlobalStride
-        | TmaOperation::ReplaceInterleaveLayout
-        | TmaOperation::ReplaceRank
-        | TmaOperation::ReplaceSwizzleAtomicity
-        | TmaOperation::ReplaceSwizzleMode => unreachable!("selectionless TMA operation"),
-    };
-
-    let mut immediate_bindings = Vec::new();
-    if matches!(
-        operation,
-        TmaOperation::G2sTile1d
-            | TmaOperation::G2sTile2d
-            | TmaOperation::G2sTile2dMulticast
-            | TmaOperation::G2sTile2dMulticastCg2
-            | TmaOperation::G2sTile3d
-            | TmaOperation::G2sTile4d
-            | TmaOperation::G2sTile5d
-    ) {
-        let dimensions = operation.dimensions().unwrap();
-        immediate_bindings.push(crate::model::ImportedImmediateBinding {
-            argument_index: dimensions + 5,
-            value: if matches!(
-                operation,
-                TmaOperation::G2sTile2dMulticast | TmaOperation::G2sTile2dMulticastCg2
-            ) {
-                -1
-            } else {
-                0
-            },
-        });
-        immediate_bindings.push(crate::model::ImportedImmediateBinding {
-            argument_index: dimensions + 6,
-            value: 0,
-        });
-    } else if matches!(
-        operation,
-        TmaOperation::S2gTile1d
-            | TmaOperation::S2gTile2d
-            | TmaOperation::S2gTile3d
-            | TmaOperation::S2gTile4d
-            | TmaOperation::S2gTile5d
-    ) {
-        immediate_bindings.push(crate::model::ImportedImmediateBinding {
-            argument_index: operation.dimensions().unwrap() + 3,
-            value: 0,
-        });
-    } else if let Some(coordinate_count) = operation.prefetch_coordinate_count() {
-        immediate_bindings.push(crate::model::ImportedImmediateBinding {
-            argument_index: coordinate_count + 2,
-            value: if operation.uses_prefetch_cache_hint() {
-                -1
-            } else {
-                0
-            },
-        });
-    }
-
-    selection.source_record == source_record
-        && selection.asm == asm
-        && selection.constraints
-            == crate::model::ImportedSelectionConstraints {
-                address_space: None,
-                immediate_bindings,
-            }
-}
-
-#[derive(Clone, Copy)]
-struct ThreadfenceRecipe {
-    scope: ThreadfenceScope,
-    abi_id: &'static str,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    selection_record: &'static str,
-    llvm_symbol: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    ptx_level: &'static str,
-    execution_scope: &'static str,
-    minimum_ptx: &'static str,
-    minimum_sm: Option<&'static str>,
-    summary: &'static str,
-}
-
-fn threadfence_recipe(scope: ThreadfenceScope) -> ThreadfenceRecipe {
-    match scope {
-        ThreadfenceScope::Cta => ThreadfenceRecipe {
-            scope,
-            abi_id: "i0298",
-            id: "threadfence_block",
-            operation_key: "memory.fence.cta.sc",
-            source_record: "int_nvvm_membar_cta",
-            selection_record: "INT_MEMBAR_CTA",
-            llvm_symbol: "llvm.nvvm.membar.cta",
-            dialect_op_type: "ThreadfenceBlockOp",
-            dialect_op_name: "nvvm.threadfence_block",
-            ptx_level: "cta",
-            execution_scope: "cta",
-            minimum_ptx: "1.4",
-            minimum_sm: None,
-            summary: "Orders this thread's memory operations for observers in its CTA.",
-        },
-        ThreadfenceScope::Device => ThreadfenceRecipe {
-            scope,
-            abi_id: "i0299",
-            id: "threadfence",
-            operation_key: "memory.fence.device.sc",
-            source_record: "int_nvvm_membar_gl",
-            selection_record: "INT_MEMBAR_GL",
-            llvm_symbol: "llvm.nvvm.membar.gl",
-            dialect_op_type: "ThreadfenceOp",
-            dialect_op_name: "nvvm.threadfence",
-            ptx_level: "gl",
-            execution_scope: "device",
-            minimum_ptx: "1.4",
-            minimum_sm: None,
-            summary: "Orders this thread's memory operations for observers on its GPU.",
-        },
-        ThreadfenceScope::System => ThreadfenceRecipe {
-            scope,
-            abi_id: "i0300",
-            id: "threadfence_system",
-            operation_key: "memory.fence.system.sc",
-            source_record: "int_nvvm_membar_sys",
-            selection_record: "INT_MEMBAR_SYS",
-            llvm_symbol: "llvm.nvvm.membar.sys",
-            dialect_op_type: "ThreadfenceSystemOp",
-            dialect_op_name: "nvvm.threadfence_system",
-            ptx_level: "sys",
-            execution_scope: "system",
-            minimum_ptx: "2.0",
-            minimum_sm: Some("sm_20"),
-            summary: "Orders this thread's memory operations for system-wide observers.",
-        },
-    }
-}
-
-fn threadfence_scope_for_id(id: &str) -> Option<ThreadfenceScope> {
-    match id {
-        "threadfence_block" => Some(ThreadfenceScope::Cta),
-        "threadfence" => Some(ThreadfenceScope::Device),
-        "threadfence_system" => Some(ThreadfenceScope::System),
-        _ => None,
-    }
-}
-
-fn expand_threadfence_admission(admission: &ThreadfenceAdmission) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "threadfence runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact threadfence admission requires both backend evidence profiles"
-    );
-    let expected_scopes = [
-        ThreadfenceScope::Cta,
-        ThreadfenceScope::Device,
-        ThreadfenceScope::System,
-    ];
-    let actual_scopes = admission
-        .variants
-        .iter()
-        .map(|variant| variant.scope)
-        .collect::<Vec<_>>();
-    ensure!(
-        actual_scopes == expected_scopes,
-        "compact threadfence admission must contain each reviewed scope exactly once in canonical order"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = threadfence_recipe(variant.scope);
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must keep reserved ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: variant.abi_id.clone(),
-                operation_key: recipe.operation_key.into(),
-                family: "sync".into(),
-                source: None,
-                source_record: Some(recipe.source_record.into()),
-                rust_module: "fence".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments: vec![],
-                rust_result: "()".into(),
-                safe: true,
-                must_use: false,
-                safe_allowlist_reason: Some(
-                    "a fence only orders the calling thread's memory operations and has no caller preconditions"
-                        .into(),
-                ),
-                public_rust_path: format!("cuda_intrinsics::fence::{}", recipe.id),
-                compatibility_rust_paths: vec![
-                    format!("cuda_device::fence::{}", recipe.id),
-                    format!("cuda_device::{}", recipe.id),
-                ],
-                dialect_op_type: recipe.dialect_op_type.into(),
-                dialect_op_name: recipe.dialect_op_name.into(),
-                dialect_operands: vec![],
-                dialect_results: vec![],
-                llvm_symbol: Some(recipe.llvm_symbol.into()),
-                resolved_llvm_symbol: None,
-                llvm_arguments: vec![],
-                llvm_results: vec![],
-                pure: false,
-                memory: "read_write".into(),
-                convergent: false,
-                execution_scope: recipe.execution_scope.into(),
-                minimum_ptx: recipe.minimum_ptx.into(),
-                minimum_sm: recipe.minimum_sm.map(Into::into),
-                ptx_result: "()".into(),
-                targets: "all".into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section:
-                    "9.7.14.4 Parallel Synchronization and Communication Instructions: membar / fence"
-                        .into(),
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-membar-fence".into(),
-                lowering: "direct_nvvm".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: BackendLoweringMechanism::TypedNvvm,
-                        evidence_profile: admission.llvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some("3.2".into()),
-                        minimum_sm: Some("sm_20".into()),
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::TypedNvvm,
-                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some("7.0".into()),
-                        minimum_sm: Some("sm_80".into()),
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: "membar".into(),
-                    modifiers: vec![recipe.ptx_level.into()],
-                    operands: vec![],
-                },
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect()
-}
-
-fn validate_threadfence_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-    scope: ThreadfenceScope,
-) -> Result<()> {
-    let recipe = threadfence_recipe(scope);
-    ensure!(
-        recipe.scope == scope
-            && policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} threadfence identity does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "fence"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments.is_empty()
-            && policy.rust_result == "()"
-            && policy.safe
-            && !policy.must_use
-            && policy.public_rust_path == format!("cuda_intrinsics::fence::{}", recipe.id)
-            && policy.compatibility_rust_paths
-                == [
-                    format!("cuda_device::fence::{}", recipe.id),
-                    format!("cuda_device::{}", recipe.id),
-                ],
-        "{} threadfence Rust API does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands.is_empty()
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments.is_empty()
-            && policy.llvm_results.is_empty()
-            && policy.lowering == "direct_nvvm",
-        "{} threadfence carrier or lowering does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.properties == ["IntrNoCallback"]
-            && !policy.pure
-            && policy.memory == "read_write"
-            && !policy.convergent
-            && policy.execution_scope == recipe.execution_scope,
-        "{} threadfence effects disagree with the imported declaration",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == recipe.minimum_sm
-            && policy.ptx_result == "()"
-            && policy.targets == "all"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.14.4 Parallel Synchronization and Communication Instructions: membar / fence"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-membar-fence",
-        "{} threadfence target floor or PTX provenance changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx
-            == (InstructionPattern {
-                mnemonic: "membar".into(),
-                modifiers: vec![recipe.ptx_level.into()],
-                operands: vec![],
-            }),
-        "{} expected PTX does not match its closed threadfence scope",
-        policy.id
-    );
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && policy.backend_lowerings.iter().any(|route| {
-                route.backend == IntrinsicBackend::LlvmNvptx
-                    && route.mechanism == BackendLoweringMechanism::TypedNvvm
-                    && route.minimum_ptx.as_deref() == Some("3.2")
-                    && route.minimum_sm.as_deref() == Some("sm_20")
-            })
-            && policy.backend_lowerings.iter().any(|route| {
-                route.backend == IntrinsicBackend::LibNvvm
-                    && route.mechanism == BackendLoweringMechanism::TypedNvvm
-                    && route.minimum_ptx.as_deref() == Some("7.0")
-                    && route.minimum_sm.as_deref() == Some("sm_80")
-            }),
-        "{} must keep both reviewed typed threadfence routes",
-        policy.id
-    );
-    ensure!(
-        policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.cp_async_mbarrier.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.register_mma.is_none()
-            && policy.sparse_mma.is_none()
-            && policy.prmt.is_none()
-            && policy.cluster_barrier.is_none()
-            && policy.special_register.is_none()
-            && policy.debug_control.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with threadfence",
-        policy.id
-    );
-    Ok(())
-}
-
-#[derive(Clone, Copy)]
-struct ClcRecipe {
-    operation: ClcOperation,
-    abi_id: &'static str,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    rust_arguments: &'static [&'static str],
-    llvm_arguments: &'static [&'static str],
-    llvm_results: &'static [&'static str],
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    dialect_operands: &'static [&'static str],
-    dialect_results: &'static [&'static str],
-    adapter: ClcAdapter,
-    modifiers: &'static [&'static str],
-    operands: &'static [OperandPattern],
-    targets: &'static str,
-    minimum_sm: Option<&'static str>,
-    pure: bool,
-    memory: &'static str,
-    execution_scope: &'static str,
-    summary: &'static str,
-}
-
-fn clc_recipe(operation: ClcOperation) -> ClcRecipe {
-    const TRY_OPERANDS: &[OperandPattern] = &[OperandPattern::Address, OperandPattern::Address];
-    const QUERY_OPERANDS: &[OperandPattern] = &[OperandPattern::Register, OperandPattern::Register];
-    let (abi_id, id, operation_key, source_record, llvm_symbol, op_type, op_name) = match operation
-    {
-        ClcOperation::TryCancel => (
-            "i0322",
-            "clc_try_cancel",
-            "cluster.launch_control.try_cancel",
-            "int_nvvm_clusterlaunchcontrol_try_cancel_async_shared",
-            "llvm.nvvm.clusterlaunchcontrol.try_cancel.async.shared",
-            "ClcTryCancelOp",
-            "nvvm.clc_try_cancel",
-        ),
-        ClcOperation::TryCancelMulticast => (
-            "i0323",
-            "clc_try_cancel_multicast",
-            "cluster.launch_control.try_cancel.multicast",
-            "int_nvvm_clusterlaunchcontrol_try_cancel_async_multicast_shared",
-            "llvm.nvvm.clusterlaunchcontrol.try_cancel.async.multicast.shared",
-            "ClcTryCancelMulticastOp",
-            "nvvm.clc_try_cancel_multicast",
-        ),
-        ClcOperation::QueryIsCanceled => (
-            "i0324",
-            "clc_query_is_canceled",
-            "cluster.launch_control.query.is_canceled",
-            "int_nvvm_clusterlaunchcontrol_query_cancel_is_canceled",
-            "llvm.nvvm.clusterlaunchcontrol.query_cancel.is_canceled",
-            "ClcQueryIsCanceledOp",
-            "nvvm.clc_query_is_canceled",
-        ),
-        ClcOperation::QueryGetFirstCtaidX => (
-            "i0325",
-            "clc_query_get_first_ctaid_x",
-            "cluster.launch_control.query.first_ctaid.x",
-            "int_nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_x",
-            "llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.x",
-            "ClcQueryGetFirstCtaidXOp",
-            "nvvm.clc_query_get_first_ctaid_x",
-        ),
-        ClcOperation::QueryGetFirstCtaidY => (
-            "i0326",
-            "clc_query_get_first_ctaid_y",
-            "cluster.launch_control.query.first_ctaid.y",
-            "int_nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_y",
-            "llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.y",
-            "ClcQueryGetFirstCtaidYOp",
-            "nvvm.clc_query_get_first_ctaid_y",
-        ),
-        ClcOperation::QueryGetFirstCtaidZ => (
-            "i0327",
-            "clc_query_get_first_ctaid_z",
-            "cluster.launch_control.query.first_ctaid.z",
-            "int_nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_z",
-            "llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.z",
-            "ClcQueryGetFirstCtaidZOp",
-            "nvvm.clc_query_get_first_ctaid_z",
-        ),
-    };
-    match operation {
-        ClcOperation::TryCancel | ClcOperation::TryCancelMulticast => ClcRecipe {
-            operation,
-            abi_id,
-            id,
-            operation_key,
-            source_record,
-            llvm_symbol,
-            rust_arguments: &["*mut u8", "*mut u64"],
-            llvm_arguments: &["shared_ptr", "shared_ptr"],
-            llvm_results: &[],
-            dialect_op_type: op_type,
-            dialect_op_name: op_name,
-            dialect_operands: &["ptr", "ptr"],
-            dialect_results: &[],
-            adapter: ClcAdapter::GenericPointersToShared,
-            modifiers: if operation == ClcOperation::TryCancel {
-                &[
-                    "try_cancel",
-                    "async",
-                    "shared::cta",
-                    "mbarrier::complete_tx::bytes",
-                    "b128",
-                ]
-            } else {
-                &[
-                    "try_cancel",
-                    "async",
-                    "shared::cta",
-                    "mbarrier::complete_tx::bytes",
-                    "multicast::cluster::all",
-                    "b128",
-                ]
-            },
-            operands: TRY_OPERANDS,
-            targets: if operation == ClcOperation::TryCancel {
-                "all"
-            } else {
-                // LLVM 22 exposes 101a; CUDA 13.3 exposes the other toolkit names.
-                "sm_100a|sm_101a|sm_103a|sm_110a|sm_120a|sm_121a"
-            },
-            minimum_sm: if operation == ClcOperation::TryCancel {
-                Some("sm_100")
-            } else {
-                None
-            },
-            pure: false,
-            memory: "read_write",
-            execution_scope: "cta",
-            summary: if operation == ClcOperation::TryCancel {
-                "Requests one pending CTA and writes its response to shared memory."
-            } else {
-                "Requests one pending CTA and multicasts its response across the cluster."
-            },
-        },
-        ClcOperation::QueryIsCanceled
-        | ClcOperation::QueryGetFirstCtaidX
-        | ClcOperation::QueryGetFirstCtaidY
-        | ClcOperation::QueryGetFirstCtaidZ => {
-            let (adapter, modifiers, summary) = match operation {
-                ClcOperation::QueryIsCanceled => (
-                    ClcAdapter::PairU64ToI128BoolToU32,
-                    &["query_cancel", "is_canceled", "pred", "b128"] as &[_],
-                    "Returns whether the Cluster Launch Control request was canceled.",
-                ),
-                ClcOperation::QueryGetFirstCtaidX => (
-                    ClcAdapter::PairU64ToI128U32,
-                    &["query_cancel", "get_first_ctaid::x", "b32", "b128"] as &[_],
-                    "Returns the X coordinate from a successful cancellation response.",
-                ),
-                ClcOperation::QueryGetFirstCtaidY => (
-                    ClcAdapter::PairU64ToI128U32,
-                    &["query_cancel", "get_first_ctaid::y", "b32", "b128"] as &[_],
-                    "Returns the Y coordinate from a successful cancellation response.",
-                ),
-                ClcOperation::QueryGetFirstCtaidZ => (
-                    ClcAdapter::PairU64ToI128U32,
-                    &["query_cancel", "get_first_ctaid::z", "b32", "b128"] as &[_],
-                    "Returns the Z coordinate from a successful cancellation response.",
-                ),
-                _ => unreachable!(),
-            };
-            ClcRecipe {
-                operation,
-                abi_id,
-                id,
-                operation_key,
-                source_record,
-                llvm_symbol,
-                rust_arguments: &["u64", "u64"],
-                llvm_arguments: &["i128"],
-                llvm_results: if operation == ClcOperation::QueryIsCanceled {
-                    &["i1"]
-                } else {
-                    &["i32"]
-                },
-                dialect_op_type: op_type,
-                dialect_op_name: op_name,
-                dialect_operands: &["i64", "i64"],
-                dialect_results: &["i32"],
-                adapter,
-                modifiers,
-                operands: QUERY_OPERANDS,
-                targets: "all",
-                minimum_sm: Some("sm_100"),
-                pure: true,
-                memory: "none",
-                execution_scope: "thread",
-                summary,
-            }
-        }
-    }
-}
-
-fn expand_clc_admission(admission: &ClcAdmission) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "CLC runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact CLC admission requires both backend evidence profiles"
-    );
-    let expected = [
-        ClcOperation::TryCancel,
-        ClcOperation::TryCancelMulticast,
-        ClcOperation::QueryIsCanceled,
-        ClcOperation::QueryGetFirstCtaidX,
-        ClcOperation::QueryGetFirstCtaidY,
-        ClcOperation::QueryGetFirstCtaidZ,
-    ];
-    ensure!(
-        admission
-            .variants
-            .iter()
-            .map(|variant| variant.operation)
-            .eq(expected),
-        "compact CLC admission must list all six operations in canonical order"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = clc_recipe(variant.operation);
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must keep reserved ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            let query = recipe.pure;
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: variant.abi_id.clone(),
-                operation_key: recipe.operation_key.into(),
-                family: "clc".into(),
-                source: None,
-                source_record: Some(recipe.source_record.into()),
-                rust_module: "clc".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments: recipe.rust_arguments.iter().map(|value| (*value).into()).collect(),
-                rust_result: if query { "u32".into() } else { "()".into() },
-                safe: false,
-                must_use: false,
-                safe_allowlist_reason: None,
-                public_rust_path: format!("cuda_intrinsics::clc::{}", recipe.id),
-                compatibility_rust_paths: vec![format!("cuda_device::clc::{}", recipe.id)],
-                dialect_op_type: recipe.dialect_op_type.into(),
-                dialect_op_name: recipe.dialect_op_name.into(),
-                dialect_operands: recipe.dialect_operands.iter().map(|value| (*value).into()).collect(),
-                dialect_results: recipe.dialect_results.iter().map(|value| (*value).into()).collect(),
-                llvm_symbol: Some(recipe.llvm_symbol.into()),
-                resolved_llvm_symbol: None,
-                llvm_arguments: recipe.llvm_arguments.iter().map(|value| (*value).into()).collect(),
-                llvm_results: recipe.llvm_results.iter().map(|value| (*value).into()).collect(),
-                pure: recipe.pure,
-                memory: recipe.memory.into(),
-                convergent: false,
-                execution_scope: recipe.execution_scope.into(),
-                minimum_ptx: "8.6".into(),
-                minimum_sm: recipe.minimum_sm.map(Into::into),
-                ptx_result: if query { "u32".into() } else { "()".into() },
-                targets: recipe.targets.into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section: "9.7.14.18-19 Cluster Launch Control".into(),
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel".into(),
-                lowering: "generated_clc".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: BackendLoweringMechanism::TypedNvvm,
-                        evidence_profile: admission.llvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some("8.6".into()),
-                        minimum_sm: recipe.minimum_sm.map(Into::into),
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::TypedNvvm,
-                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some("8.6".into()),
-                        minimum_sm: recipe.minimum_sm.map(Into::into),
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: Some(Clc {
-                    operation: recipe.operation,
-                    adapter: recipe.adapter,
-                    runtime_validation: admission.runtime_validation,
-                }),
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: "clusterlaunchcontrol".into(),
-                    modifiers: recipe.modifiers.iter().map(|value| (*value).into()).collect(),
-                    operands: if query {
-                        vec![
-                            OperandPattern::Register,
-                            OperandPattern::Exact { value: "%clc_handle".into() },
-                        ]
-                    } else {
-                        recipe.operands.to_vec()
-                    },
-                },
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect()
-}
-
-fn validate_clc_policy(policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic) -> Result<()> {
-    let clc = policy
-        .clc
-        .as_ref()
-        .with_context(|| format!("{} has no closed CLC contract", policy.id))?;
-    let recipe = clc_recipe(clc.operation);
-    let query = recipe.pure;
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none()
-            && declaration.source_record == recipe.source_record
-            && declaration.llvm_name == recipe.llvm_symbol,
-        "{} CLC identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "clc"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == recipe.rust_arguments
-            && policy.rust_result == if query { "u32" } else { "()" }
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::clc::{}", recipe.id)
-            && policy.compatibility_rust_paths == [format!("cuda_device::clc::{}", recipe.id)],
-        "{} CLC Rust API changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == recipe.dialect_operands
-            && policy.dialect_results == recipe.dialect_results
-            && policy.llvm_arguments == recipe.llvm_arguments
-            && policy.llvm_results == recipe.llvm_results
-            && policy.lowering == "generated_clc",
-        "{} CLC carrier or LLVM adapter changed",
-        policy.id
-    );
-    ensure!(
-        declaration.arguments == recipe.llvm_arguments
-            && declaration.results == recipe.llvm_results
-            && declaration.properties
-                == if query {
-                    vec!["IntrNoMem", "IntrSpeculatable"]
-                } else {
-                    vec!["IntrArgMemOnly", "IntrHasSideEffects"]
-                },
-        "{} imported CLC declaration changed",
-        policy.id
-    );
-    ensure!(
-        policy.pure == recipe.pure
-            && policy.memory == recipe.memory
-            && !policy.convergent
-            && policy.execution_scope == recipe.execution_scope
-            && clc.adapter == recipe.adapter
-            && clc.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} CLC semantics changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == "8.6"
-            && policy.minimum_sm.as_deref() == recipe.minimum_sm
-            && policy.targets == recipe.targets
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_result == if query { "u32" } else { "()" },
-        "{} CLC target contract changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "clusterlaunchcontrol"
-            && policy.expected_ptx.modifiers == recipe.modifiers
-            && policy.expected_ptx.operands
-                == if query {
-                    vec![
-                        OperandPattern::Register,
-                        OperandPattern::Exact {
-                            value: "%clc_handle".into(),
-                        },
-                    ]
-                } else {
-                    recipe.operands.to_vec()
-                }
-            && policy.backend_lowerings.len() == 2
-            && policy.backend_lowerings.iter().all(|route| {
-                route.mechanism == BackendLoweringMechanism::TypedNvvm
-                    && route.minimum_ptx.as_deref() == Some("8.6")
-                    && route.minimum_sm.as_deref() == recipe.minimum_sm
-                    && !route.evidence_profile.trim().is_empty()
-            }),
-        "{} CLC PTX shape or backend route changed",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "CLC")?;
-    Ok(())
-}
-
-const EXECUTION_CONTROL_OPERATIONS: [ExecutionControlOperation; 8] = [
-    ExecutionControlOperation::BarrierCtaSync,
-    ExecutionControlOperation::BarrierCtaSyncAligned,
-    ExecutionControlOperation::BarrierCtaArrive,
-    ExecutionControlOperation::BarrierCtaArriveAligned,
-    ExecutionControlOperation::GridDependencyLaunchDependents,
-    ExecutionControlOperation::GridDependencyWait,
-    ExecutionControlOperation::SetMaxNRegInc,
-    ExecutionControlOperation::SetMaxNRegDec,
-];
-
-fn validate_execution_control_family_completeness(intrinsics: &[OverlayIntrinsic]) -> Result<()> {
-    let has_execution_control_family = intrinsics.iter().any(|policy| {
-        matches!(
-            policy.family.as_str(),
-            "counted_barrier" | "grid_dependency" | "register_control"
-        )
-    });
-    if !has_execution_control_family {
-        return Ok(());
-    }
-    let actual = intrinsics
-        .iter()
-        .filter_map(|policy| ExecutionControlOperation::from_catalog_id(&policy.id))
-        .collect::<BTreeSet<_>>();
-    let expected = EXECUTION_CONTROL_OPERATIONS
-        .into_iter()
-        .collect::<BTreeSet<_>>();
-    ensure!(
-        actual == expected,
-        "execution-control overlay must admit all four counted barriers, both grid-dependency controls, and both setmaxnreg operations"
-    );
-    for family in ["counted_barrier", "grid_dependency", "register_control"] {
-        ensure!(
-            intrinsics
-                .iter()
-                .filter(|policy| policy.family == family)
-                .all(|policy| {
-                    ExecutionControlOperation::from_catalog_id(&policy.id)
-                        .is_some_and(|operation| operation.family() == family)
-                }),
-            "{family} overlay contains an operation outside its closed instruction family"
-        );
-    }
-    Ok(())
-}
-
-#[derive(Clone)]
-struct ExecutionControlRecipe {
-    abi_id: &'static str,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    rust_module: &'static str,
-    rust_arguments: &'static [&'static str],
-    compatibility_path: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    dialect_operands: &'static [&'static str],
-    llvm_arguments: &'static [&'static str],
-    imported_classes: &'static [&'static str],
-    imported_properties: &'static [&'static str],
-    memory: &'static str,
-    convergent: bool,
-    execution_scope: &'static str,
-    minimum_ptx: &'static str,
-    minimum_sm: Option<&'static str>,
-    targets: &'static str,
-    ptx_isa_section: &'static str,
-    ptx_isa_url: &'static str,
-    mnemonic: &'static str,
-    modifiers: &'static [&'static str],
-    operands: &'static [OperandPattern],
-    selection_records: &'static [&'static str],
-    selection_asm: &'static str,
-    selection_predicates: &'static [&'static str],
-    summary: &'static str,
-}
-
-fn execution_control_recipe(operation: ExecutionControlOperation) -> ExecutionControlRecipe {
-    use ExecutionControlOperation::*;
-
-    const EMPTY: &[&str] = &[];
-    const I32: &[&str] = &["i32"];
-    const I32_I32: &[&str] = &["i32", "i32"];
-    const U32: &[&str] = &["u32"];
-    const U32_U32: &[&str] = &["u32", "u32"];
-    const BASE_CLASSES: &[&str] = &["SDPatternOperator", "Intrinsic"];
-    const DEFAULT_CLASSES: &[&str] = &["SDPatternOperator", "Intrinsic", "DefaultAttrsIntrinsic"];
-    const BARRIER_PROPERTIES: &[&str] = &["IntrConvergent", "IntrNoCallback"];
-    const GRID_PROPERTIES: &[&str] = &["IntrHasSideEffects", "IntrNoMem"];
-    const SETMAX_PROPERTIES: &[&str] = &[
-        "ImmArg<arg0>",
-        "IntrConvergent",
-        "IntrHasSideEffects",
-        "IntrNoMem",
-        "Range<arg0,24,257>",
-    ];
-    const TWO_REGISTER_OR_IMMEDIATE: &[OperandPattern] = &[
-        OperandPattern::RegisterOrImmediate,
-        OperandPattern::RegisterOrImmediate,
-    ];
-    const ONE_IMMEDIATE: &[OperandPattern] = &[OperandPattern::Immediate];
-    const NO_OPERANDS: &[OperandPattern] = &[];
-    const BARRIER_SYNC_SELECTIONS: &[&str] = &[
-        "BARRIER_CTA_SYNC_ii",
-        "BARRIER_CTA_SYNC_ir",
-        "BARRIER_CTA_SYNC_ri",
-        "BARRIER_CTA_SYNC_rr",
-    ];
-    const BAR_SYNC_SELECTIONS: &[&str] = &[
-        "BARRIER_CTA_SYNC_ALIGNED_ii",
-        "BARRIER_CTA_SYNC_ALIGNED_ir",
-        "BARRIER_CTA_SYNC_ALIGNED_ri",
-        "BARRIER_CTA_SYNC_ALIGNED_rr",
-    ];
-    const BARRIER_ARRIVE_SELECTIONS: &[&str] = &[
-        "BARRIER_CTA_ARRIVE_ii",
-        "BARRIER_CTA_ARRIVE_ir",
-        "BARRIER_CTA_ARRIVE_ri",
-        "BARRIER_CTA_ARRIVE_rr",
-    ];
-    const BAR_ARRIVE_SELECTIONS: &[&str] = &[
-        "BARRIER_CTA_ARRIVE_ALIGNED_ii",
-        "BARRIER_CTA_ARRIVE_ALIGNED_ir",
-        "BARRIER_CTA_ARRIVE_ALIGNED_ri",
-        "BARRIER_CTA_ARRIVE_ALIGNED_rr",
-    ];
-    const PTX_60: &[&str] = &["Subtarget->getPTXVersion() >= 60"];
-    const GRID_PREDICATES: &[&str] = &[
-        "Subtarget->getSmVersion() >= 90",
-        "Subtarget->getPTXVersion() >= 78",
-    ];
-    const SETMAX_PREDICATES: &[&str] = &["Subtarget->hasSetMaxNRegSupport()"];
-    const SYNC_MODIFIERS: &[&str] = &["sync"];
-    const ARRIVE_MODIFIERS: &[&str] = &["arrive"];
-    const LAUNCH_DEPENDENTS_MODIFIERS: &[&str] = &["launch_dependents"];
-    const WAIT_MODIFIERS: &[&str] = &["wait"];
-    const SETMAX_INC_MODIFIERS: &[&str] = &["inc", "sync", "aligned", "u32"];
-    const SETMAX_DEC_MODIFIERS: &[&str] = &["dec", "sync", "aligned", "u32"];
-    const GRID_LAUNCH_SELECTIONS: &[&str] = &["GRIDDEPCONTROL_LAUNCH_DEPENDENTS"];
-    const GRID_WAIT_SELECTIONS: &[&str] = &["GRIDDEPCONTROL_WAIT"];
-    const SETMAX_INC_SELECTIONS: &[&str] = &["anonymous_22212"];
-    const SETMAX_DEC_SELECTIONS: &[&str] = &["anonymous_22214"];
-    const BAR_SECTION: &str =
-        "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier";
-    const BAR_URL: &str = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier";
-    const GRID_SECTION: &str =
-        "9.7.15.1 Parallel Synchronization and Communication Instructions: griddepcontrol";
-    const GRID_URL: &str = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-griddepcontrol";
-    const SETMAX_SECTION: &str = "9.7.16.5 Miscellaneous Instructions: setmaxnreg";
-    const SETMAX_URL: &str = "https://docs.nvidia.com/cuda/parallel-thread-execution/#miscellaneous-instructions-setmaxnreg";
-
-    let (
-        abi_id,
-        id,
-        operation_key,
-        source_record,
-        llvm_symbol,
-        rust_module,
-        rust_arguments,
-        compatibility_path,
-        dialect_op_type,
-        dialect_op_name,
-        dialect_operands,
-        llvm_arguments,
-        imported_classes,
-        imported_properties,
-        memory,
-        convergent,
-        execution_scope,
-        minimum_ptx,
-        minimum_sm,
-        targets,
-        ptx_isa_section,
-        ptx_isa_url,
-        mnemonic,
-        modifiers,
-        operands,
-        selection_records,
-        selection_asm,
-        selection_predicates,
-        summary,
-    ) = match operation {
-        BarrierCtaSync => (
-            "i0883",
-            "barrier_cta_sync",
-            "synchronization.cta.barrier.count",
-            "int_nvvm_barrier_cta_sync_count",
-            "llvm.nvvm.barrier.cta.sync.count",
-            "barrier",
-            U32_U32,
-            "cuda_device::barrier::barrier_cta_sync",
-            "BarrierCtaSyncCountOp",
-            "nvvm.barrier_cta_sync_count",
-            I32_I32,
-            I32_I32,
-            BASE_CLASSES,
-            BARRIER_PROPERTIES,
-            "read_write",
-            true,
-            "cta",
-            "6.0",
-            Some("sm_30"),
-            "all",
-            BAR_SECTION,
-            BAR_URL,
-            "barrier",
-            SYNC_MODIFIERS,
-            TWO_REGISTER_OR_IMMEDIATE,
-            BARRIER_SYNC_SELECTIONS,
-            "barrier.sync \t$i, $j;",
-            PTX_60,
-            "Synchronizes the requested number of CTA threads at a numbered barrier.",
-        ),
-        BarrierCtaSyncAligned => (
-            "i0884",
-            "barrier_cta_sync_aligned",
-            "synchronization.cta.bar.aligned.count",
-            "int_nvvm_barrier_cta_sync_aligned_count",
-            "llvm.nvvm.barrier.cta.sync.aligned.count",
-            "barrier",
-            U32_U32,
-            "cuda_device::barrier::barrier_cta_sync_aligned",
-            "BarrierCtaSyncAlignedCountOp",
-            "nvvm.barrier_cta_sync_aligned_count",
-            I32_I32,
-            I32_I32,
-            BASE_CLASSES,
-            BARRIER_PROPERTIES,
-            "read_write",
-            true,
-            "cta",
-            "1.0",
-            None,
-            "all",
-            BAR_SECTION,
-            BAR_URL,
-            "bar",
-            SYNC_MODIFIERS,
-            TWO_REGISTER_OR_IMMEDIATE,
-            BAR_SYNC_SELECTIONS,
-            "bar.sync \t$i, $j;",
-            EMPTY,
-            "Synchronizes the requested number of CTA threads at an aligned numbered barrier.",
-        ),
-        BarrierCtaArrive => (
-            "i0885",
-            "barrier_cta_arrive",
-            "synchronization.cta.barrier.arrive.count",
-            "int_nvvm_barrier_cta_arrive_count",
-            "llvm.nvvm.barrier.cta.arrive.count",
-            "barrier",
-            U32_U32,
-            "cuda_device::barrier::barrier_cta_arrive",
-            "BarrierCtaArriveCountOp",
-            "nvvm.barrier_cta_arrive_count",
-            I32_I32,
-            I32_I32,
-            BASE_CLASSES,
-            BARRIER_PROPERTIES,
-            "read_write",
-            true,
-            "cta",
-            "6.0",
-            Some("sm_30"),
-            "all",
-            BAR_SECTION,
-            BAR_URL,
-            "barrier",
-            ARRIVE_MODIFIERS,
-            TWO_REGISTER_OR_IMMEDIATE,
-            BARRIER_ARRIVE_SELECTIONS,
-            "barrier.arrive \t$i, $j;",
-            PTX_60,
-            "Signals arrival of the requested number of CTA threads at a numbered barrier without waiting.",
-        ),
-        BarrierCtaArriveAligned => (
-            "i0886",
-            "barrier_cta_arrive_aligned",
-            "synchronization.cta.bar.arrive.aligned.count",
-            "int_nvvm_barrier_cta_arrive_aligned_count",
-            "llvm.nvvm.barrier.cta.arrive.aligned.count",
-            "barrier",
-            U32_U32,
-            "cuda_device::barrier::barrier_cta_arrive_aligned",
-            "BarrierCtaArriveAlignedCountOp",
-            "nvvm.barrier_cta_arrive_aligned_count",
-            I32_I32,
-            I32_I32,
-            BASE_CLASSES,
-            BARRIER_PROPERTIES,
-            "read_write",
-            true,
-            "cta",
-            "1.0",
-            None,
-            "all",
-            BAR_SECTION,
-            BAR_URL,
-            "bar",
-            ARRIVE_MODIFIERS,
-            TWO_REGISTER_OR_IMMEDIATE,
-            BAR_ARRIVE_SELECTIONS,
-            "bar.arrive \t$i, $j;",
-            EMPTY,
-            "Signals arrival of the requested number of CTA threads at an aligned numbered barrier without waiting.",
-        ),
-        GridDependencyLaunchDependents => (
-            "i0913",
-            "grid_dependency_launch_dependents",
-            "synchronization.grid.dependency.launch_dependents",
-            "int_nvvm_griddepcontrol_launch_dependents",
-            "llvm.nvvm.griddepcontrol.launch.dependents",
-            "grid",
-            EMPTY,
-            "cuda_device::grid::dependency::trigger_dependents",
-            "GridDependencyLaunchDependentsOp",
-            "nvvm.grid_dependency_launch_dependents",
-            EMPTY,
-            EMPTY,
-            BASE_CLASSES,
-            GRID_PROPERTIES,
-            "none",
-            false,
-            "grid",
-            "7.8",
-            Some("sm_90"),
-            "all",
-            GRID_SECTION,
-            GRID_URL,
-            "griddepcontrol",
-            LAUNCH_DEPENDENTS_MODIFIERS,
-            NO_OPERANDS,
-            GRID_LAUNCH_SELECTIONS,
-            "griddepcontrol.launch_dependents;",
-            GRID_PREDICATES,
-            "Makes dependent grids eligible to launch before the current grid completes.",
-        ),
-        GridDependencyWait => (
-            "i0914",
-            "grid_dependency_wait",
-            "synchronization.grid.dependency.wait",
-            "int_nvvm_griddepcontrol_wait",
-            "llvm.nvvm.griddepcontrol.wait",
-            "grid",
-            EMPTY,
-            "cuda_device::grid::dependency::wait",
-            "GridDependencyWaitOp",
-            "nvvm.grid_dependency_wait",
-            EMPTY,
-            EMPTY,
-            BASE_CLASSES,
-            GRID_PROPERTIES,
-            "none",
-            false,
-            "grid",
-            "7.8",
-            Some("sm_90"),
-            "all",
-            GRID_SECTION,
-            GRID_URL,
-            "griddepcontrol",
-            WAIT_MODIFIERS,
-            NO_OPERANDS,
-            GRID_WAIT_SELECTIONS,
-            "griddepcontrol.wait;",
-            GRID_PREDICATES,
-            "Waits until all prerequisite grids have completed.",
-        ),
-        SetMaxNRegInc => (
-            "i0915",
-            "setmaxnreg_inc",
-            "register_control.warpgroup.setmaxnreg.increment",
-            "int_nvvm_setmaxnreg_inc_sync_aligned_u32",
-            "llvm.nvvm.setmaxnreg.inc.sync.aligned.u32",
-            "thread",
-            U32,
-            "cuda_device::thread::__setmaxnreg_inc",
-            "SetMaxNRegIncOp",
-            "nvvm.setmaxnreg_inc",
-            EMPTY,
-            I32,
-            DEFAULT_CLASSES,
-            SETMAX_PROPERTIES,
-            "none",
-            true,
-            "warpgroup",
-            "8.0",
-            None,
-            TENSOR_MAP_REPLACE_TARGETS,
-            SETMAX_SECTION,
-            SETMAX_URL,
-            "setmaxnreg",
-            SETMAX_INC_MODIFIERS,
-            ONE_IMMEDIATE,
-            SETMAX_INC_SELECTIONS,
-            "setmaxnreg.inc.sync.aligned.u32 \t$reg_count;",
-            SETMAX_PREDICATES,
-            "Increases the executing warpgroup's maximum register allocation to the immediate count.",
-        ),
-        SetMaxNRegDec => (
-            "i0916",
-            "setmaxnreg_dec",
-            "register_control.warpgroup.setmaxnreg.decrement",
-            "int_nvvm_setmaxnreg_dec_sync_aligned_u32",
-            "llvm.nvvm.setmaxnreg.dec.sync.aligned.u32",
-            "thread",
-            U32,
-            "cuda_device::thread::__setmaxnreg_dec",
-            "SetMaxNRegDecOp",
-            "nvvm.setmaxnreg_dec",
-            EMPTY,
-            I32,
-            DEFAULT_CLASSES,
-            SETMAX_PROPERTIES,
-            "none",
-            true,
-            "warpgroup",
-            "8.0",
-            None,
-            TENSOR_MAP_REPLACE_TARGETS,
-            SETMAX_SECTION,
-            SETMAX_URL,
-            "setmaxnreg",
-            SETMAX_DEC_MODIFIERS,
-            ONE_IMMEDIATE,
-            SETMAX_DEC_SELECTIONS,
-            "setmaxnreg.dec.sync.aligned.u32 \t$reg_count;",
-            SETMAX_PREDICATES,
-            "Decreases the executing warpgroup's maximum register allocation to the immediate count.",
-        ),
-    };
-
-    ExecutionControlRecipe {
-        abi_id,
-        id,
-        operation_key,
-        source_record,
-        llvm_symbol,
-        rust_module,
-        rust_arguments,
-        compatibility_path,
-        dialect_op_type,
-        dialect_op_name,
-        dialect_operands,
-        llvm_arguments,
-        imported_classes,
-        imported_properties,
-        memory,
-        convergent,
-        execution_scope,
-        minimum_ptx,
-        minimum_sm,
-        targets,
-        ptx_isa_section,
-        ptx_isa_url,
-        mnemonic,
-        modifiers,
-        operands,
-        selection_records,
-        selection_asm,
-        selection_predicates,
-        summary,
-    }
-}
-
-fn execution_control_backend_floor(
-    operation: ExecutionControlOperation,
-    backend: IntrinsicBackend,
-) -> (&'static str, Option<&'static str>) {
-    use ExecutionControlOperation::*;
-
-    match (operation, backend) {
-        (BarrierCtaSync | BarrierCtaArrive, IntrinsicBackend::LlvmNvptx) => ("6.0", Some("sm_30")),
-        (BarrierCtaSync | BarrierCtaArrive, IntrinsicBackend::LibNvvm) => ("6.0", Some("sm_75")),
-        (BarrierCtaSyncAligned | BarrierCtaArriveAligned, IntrinsicBackend::LlvmNvptx) => {
-            ("3.2", Some("sm_20"))
-        }
-        (BarrierCtaSyncAligned | BarrierCtaArriveAligned, IntrinsicBackend::LibNvvm) => {
-            ("1.0", Some("sm_75"))
-        }
-        _ => {
-            let recipe = execution_control_recipe(operation);
-            (recipe.minimum_ptx, recipe.minimum_sm)
-        }
-    }
-}
-
-fn validate_execution_control_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let operation = ExecutionControlOperation::from_catalog_id(&policy.id)
-        .with_context(|| format!("{} is not a closed execution-control operation", policy.id))?;
-    let recipe = execution_control_recipe(operation);
-    ensure!(
-        policy.family == operation.family()
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.summary == recipe.summary
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none()
-            && declaration.source_record == recipe.source_record
-            && declaration.llvm_name == recipe.llvm_symbol,
-        "{} execution-control identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == recipe.rust_module
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == recipe.rust_arguments
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path
-                == format!("cuda_intrinsics::{}::{}", recipe.rust_module, recipe.id)
-            && policy.compatibility_rust_paths == [recipe.compatibility_path],
-        "{} execution-control Rust API changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == recipe.dialect_operands
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == recipe.llvm_arguments
-            && policy.llvm_results.is_empty()
-            && declaration.arguments == recipe.llvm_arguments
-            && declaration.results.is_empty()
-            && policy.lowering == "generated_execution_control",
-        "{} execution-control carrier or LLVM adapter changed",
-        policy.id
-    );
-    ensure!(
-        declaration.classes == recipe.imported_classes
-            && declaration.properties == recipe.imported_properties,
-        "{} imported execution-control declaration changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == recipe.memory
-            && policy.convergent == recipe.convergent
-            && policy.execution_scope == recipe.execution_scope,
-        "{} execution-control semantics changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == recipe.minimum_sm
-            && policy.targets == recipe.targets
-            && policy.ptx_result == "()"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.ptx_isa_section
-            && policy.ptx_isa_url == recipe.ptx_isa_url
-            && policy.expected_ptx.mnemonic == recipe.mnemonic
-            && policy.expected_ptx.modifiers == recipe.modifiers
-            && policy.expected_ptx.operands == recipe.operands,
-        "{} execution-control target or PTX contract changed",
-        policy.id
-    );
-    let valid_route = |backend, mechanism| {
-        let (minimum_ptx, minimum_sm) = execution_control_backend_floor(operation, backend);
-        policy.backend_lowerings.iter().any(|route| {
-            route.backend == backend
-                && route.mechanism == mechanism
-                && route.minimum_ptx.as_deref() == Some(minimum_ptx)
-                && route.minimum_sm.as_deref() == minimum_sm
-                && !route.evidence_profile.trim().is_empty()
-        })
-    };
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && valid_route(
-                IntrinsicBackend::LlvmNvptx,
-                BackendLoweringMechanism::TypedNvvm,
-            )
-            && valid_route(
-                IntrinsicBackend::LibNvvm,
-                BackendLoweringMechanism::InlinePtx,
-            ),
-        "{} execution-control backend route changed",
-        policy.id
-    );
-    let expected_selections = recipe
-        .selection_records
-        .iter()
-        .copied()
-        .collect::<BTreeSet<_>>();
-    let actual_selections = declaration
-        .selections
-        .iter()
-        .map(|selection| selection.source_record.as_str())
-        .collect::<BTreeSet<_>>();
-    ensure!(
-        declaration.selections.len() == recipe.selection_records.len()
-            && actual_selections == expected_selections
-            && declaration.selections.iter().all(|selection| {
-                selection.asm == recipe.selection_asm
-                    && selection.predicates == recipe.selection_predicates
-                    && selection.constraints.is_empty()
-            }),
-        "{} imported execution-control selection family changed",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "execution-control")?;
-    Ok(())
-}
-
-const TMA_OPERATIONS: [TmaOperation; 47] = [
-    TmaOperation::G2sTile1d,
-    TmaOperation::G2sTile2d,
-    TmaOperation::G2sTile2dMulticast,
-    TmaOperation::G2sTile2dMulticastCg2,
-    TmaOperation::G2sTile3d,
-    TmaOperation::G2sTile4d,
-    TmaOperation::G2sTile5d,
-    TmaOperation::S2gTile1d,
-    TmaOperation::S2gTile2d,
-    TmaOperation::S2gTile3d,
-    TmaOperation::S2gTile4d,
-    TmaOperation::S2gTile5d,
-    TmaOperation::CommitGroup,
-    TmaOperation::WaitGroup,
-    TmaOperation::WaitGroupRead,
-    TmaOperation::PrefetchTensorMap,
-    TmaOperation::PrefetchTile1d,
-    TmaOperation::PrefetchTile2d,
-    TmaOperation::PrefetchTile3d,
-    TmaOperation::PrefetchTile4d,
-    TmaOperation::PrefetchTile5d,
-    TmaOperation::PrefetchTileGather4TwoDimensional,
-    TmaOperation::ReplaceBoxDim,
-    TmaOperation::ReplaceElementStride,
-    TmaOperation::ReplaceElementType,
-    TmaOperation::ReplaceFillMode,
-    TmaOperation::ReplaceGlobalAddress,
-    TmaOperation::ReplaceGlobalDim,
-    TmaOperation::ReplaceGlobalStride,
-    TmaOperation::ReplaceInterleaveLayout,
-    TmaOperation::ReplaceRank,
-    TmaOperation::ReplaceSwizzleAtomicity,
-    TmaOperation::ReplaceSwizzleMode,
-    TmaOperation::FenceProxyTensorMapAcquireCluster,
-    TmaOperation::FenceProxyTensorMapAcquireCta,
-    TmaOperation::FenceProxyTensorMapAcquireGpu,
-    TmaOperation::FenceProxyTensorMapAcquireSystem,
-    TmaOperation::FenceProxyTensorMapReleaseCluster,
-    TmaOperation::FenceProxyTensorMapReleaseCta,
-    TmaOperation::FenceProxyTensorMapReleaseGpu,
-    TmaOperation::FenceProxyTensorMapReleaseSystem,
-    TmaOperation::PrefetchTile1dCacheHint,
-    TmaOperation::PrefetchTile2dCacheHint,
-    TmaOperation::PrefetchTile3dCacheHint,
-    TmaOperation::PrefetchTile4dCacheHint,
-    TmaOperation::PrefetchTile5dCacheHint,
-    TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint,
-];
-
-const TMA_REDUCTION_OPERATIONS: [TmaReductionOperation; 8] = [
-    TmaReductionOperation::Add,
-    TmaReductionOperation::And,
-    TmaReductionOperation::Dec,
-    TmaReductionOperation::Inc,
-    TmaReductionOperation::Max,
-    TmaReductionOperation::Min,
-    TmaReductionOperation::Or,
-    TmaReductionOperation::Xor,
-];
-
-fn tma_reduction_matrix() -> Vec<TmaReduction> {
-    let mut reductions = Vec::with_capacity(64);
-    for operation in TMA_REDUCTION_OPERATIONS {
-        for dimensions in 1..=5 {
-            reductions.push(TmaReduction {
-                operation,
-                load_mode: TmaReductionLoadMode::Tile,
-                dimensions,
-            });
-        }
-        for dimensions in 3..=5 {
-            reductions.push(TmaReduction {
-                operation,
-                load_mode: TmaReductionLoadMode::Im2col,
-                dimensions,
-            });
-        }
-    }
-    reductions
-}
-
-#[cfg(test)]
-fn tma_reduction_admission_variants() -> Vec<TmaReductionAdmissionVariant> {
-    tma_reduction_matrix()
-        .into_iter()
-        .enumerate()
-        .map(|(index, reduction)| TmaReductionAdmissionVariant {
-            // Preserve the repository's current ledger assignments in this test fixture.
-            abi_id: format!("i{:04}", 923 + index),
-            operation: reduction.operation,
-            load_mode: reduction.load_mode,
-            dimensions: reduction.dimensions,
-        })
-        .collect()
-}
-
-fn tma_reduction_operation_name(operation: TmaReductionOperation) -> (&'static str, &'static str) {
-    match operation {
-        TmaReductionOperation::Add => ("add", "Add"),
-        TmaReductionOperation::And => ("and", "And"),
-        TmaReductionOperation::Dec => ("dec", "Dec"),
-        TmaReductionOperation::Inc => ("inc", "Inc"),
-        TmaReductionOperation::Max => ("max", "Max"),
-        TmaReductionOperation::Min => ("min", "Min"),
-        TmaReductionOperation::Or => ("or", "Or"),
-        TmaReductionOperation::Xor => ("xor", "Xor"),
-    }
-}
-
-fn tma_reduction_load_mode_name(
-    load_mode: TmaReductionLoadMode,
-) -> (&'static str, &'static str, &'static str) {
-    match load_mode {
-        TmaReductionLoadMode::Tile => ("tile", "Tile", "tile"),
-        TmaReductionLoadMode::Im2col => ("im2col", "Im2col", "im2col_no_offs"),
-    }
-}
-
-struct TmaReductionRecipe {
-    id: String,
-    operation_key: String,
-    source_record: String,
-    llvm_symbol: String,
-    rust_arguments: Vec<&'static str>,
-    dialect_op_type: String,
-    dialect_op_name: String,
-    dialect_operands: Vec<&'static str>,
-    llvm_arguments: Vec<&'static str>,
-    modifiers: Vec<String>,
-    operands: Vec<OperandPattern>,
-    summary: String,
-}
-
-fn tma_reduction_recipe(reduction: TmaReduction) -> Result<TmaReductionRecipe> {
-    ensure!(
-        (1..=5).contains(&reduction.dimensions),
-        "TMA reduction dimensionality must be in 1..=5"
-    );
-    ensure!(
-        reduction.load_mode != TmaReductionLoadMode::Im2col || reduction.dimensions >= 3,
-        "TMA reduction im2col mode requires at least three dimensions"
-    );
-
-    let (operation, operation_camel) = tma_reduction_operation_name(reduction.operation);
-    let (load_mode, load_mode_camel, ptx_load_mode) =
-        tma_reduction_load_mode_name(reduction.load_mode);
-    let dimensions = reduction.dimensions as usize;
-    let id = format!(
-        "cp_async_bulk_tensor_reduce_{operation}_{load_mode}_{}d",
-        reduction.dimensions
-    );
-    let mut rust_arguments = vec!["*const u8", "*const u8"];
-    rust_arguments.extend(std::iter::repeat_n("i32", dimensions));
-    let mut dialect_operands = vec!["ptr", "ptr"];
-    dialect_operands.extend(std::iter::repeat_n("i32", dimensions));
-    let mut llvm_arguments = vec!["shared_ptr", "ptr"];
-    llvm_arguments.extend(std::iter::repeat_n("i32", dimensions));
-    llvm_arguments.extend(["i64", "i1"]);
-
-    Ok(TmaReductionRecipe {
-        operation_key: format!(
-            "memory.reduce.async.bulk.tensor.{operation}.{load_mode}.{}d",
-            reduction.dimensions
-        ),
-        source_record: format!(
-            "int_nvvm_cp_async_bulk_tensor_reduce_{operation}_{load_mode}_{}d",
-            reduction.dimensions
-        ),
-        llvm_symbol: format!(
-            "llvm.nvvm.cp.async.bulk.tensor.reduce.{operation}.{load_mode}.{}d",
-            reduction.dimensions
-        ),
-        dialect_op_type: format!(
-            "CpAsyncBulkTensorReduce{operation_camel}{load_mode_camel}{}dOp",
-            reduction.dimensions
-        ),
-        dialect_op_name: format!(
-            "nvvm.cp_async_bulk_tensor_reduce_{operation}_{load_mode}_{}d",
-            reduction.dimensions
-        ),
-        rust_arguments,
-        dialect_operands,
-        llvm_arguments,
-        modifiers: vec![
-            "reduce".into(),
-            "async".into(),
-            "bulk".into(),
-            "tensor".into(),
-            format!("{}d", reduction.dimensions),
-            "global".into(),
-            "shared::cta".into(),
-            operation.into(),
-            ptx_load_mode.into(),
-            "bulk_group".into(),
-        ],
-        operands: vec![OperandPattern::Address, OperandPattern::Address],
-        summary: format!(
-            "Starts a TMA tensor {operation} reduction from shared to global memory in {load_mode} mode."
-        ),
-        id,
-    })
-}
-
-fn expand_tma_reduction_variant(
-    admission: &TmaAdmission,
-    variant: &TmaReductionAdmissionVariant,
-) -> Result<OverlayIntrinsic> {
-    validate_abi_id(&variant.abi_id)?;
-    let reduction = TmaReduction {
-        operation: variant.operation,
-        load_mode: variant.load_mode,
-        dimensions: variant.dimensions,
-    };
-    let recipe = tma_reduction_recipe(reduction)?;
-
-    Ok(OverlayIntrinsic {
-        id: recipe.id.clone(),
-        abi_id: variant.abi_id.clone(),
-        operation_key: recipe.operation_key.clone(),
-        family: "tma".into(),
-        source: None,
-        source_record: Some(recipe.source_record.clone()),
-        rust_module: "tma".into(),
-        rust_name: recipe.id.clone(),
-        rust_arguments: recipe
-            .rust_arguments
-            .iter()
-            .map(|value| (*value).into())
-            .collect(),
-        rust_result: "()".into(),
-        safe: false,
-        must_use: false,
-        safe_allowlist_reason: None,
-        public_rust_path: format!("cuda_intrinsics::tma::{}", recipe.id),
-        compatibility_rust_paths: vec![format!("cuda_device::tma::{}", recipe.id)],
-        dialect_op_type: recipe.dialect_op_type.clone(),
-        dialect_op_name: recipe.dialect_op_name.clone(),
-        dialect_operands: recipe
-            .dialect_operands
-            .iter()
-            .map(|value| (*value).into())
-            .collect(),
-        dialect_results: vec![],
-        llvm_symbol: Some(recipe.llvm_symbol.clone()),
-        resolved_llvm_symbol: None,
-        llvm_arguments: recipe
-            .llvm_arguments
-            .iter()
-            .map(|value| (*value).into())
-            .collect(),
-        llvm_results: vec![],
-        pure: false,
-        memory: "read_write".into(),
-        convergent: true,
-        execution_scope: "thread".into(),
-        minimum_ptx: "8.0".into(),
-        minimum_sm: Some("sm_90".into()),
-        ptx_result: "()".into(),
-        targets: "all".into(),
-        ptx_isa_version: "9.3".into(),
-        ptx_isa_section:
-        "9.7.9.26.5.3 Data Movement and Conversion Instructions: cp.reduce.async.bulk.tensor"
-            .into(),
-        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor".into(),
-        lowering: "generated_tma".into(),
-        backend_lowerings: vec![
-            OverlayBackendLowering {
-                backend: IntrinsicBackend::LlvmNvptx,
-                mechanism: BackendLoweringMechanism::TypedNvvm,
-                evidence_profile: admission
-                    .reduce_llvm_evidence_profile
-                    .as_ref()
-                    .expect("validated TMA reduction LLVM evidence profile")
-                    .clone(),
-                targets: None,
-                minimum_ptx: Some("8.0".into()),
-                minimum_sm: Some("sm_90".into()),
-            },
-            OverlayBackendLowering {
-                backend: IntrinsicBackend::LibNvvm,
-                mechanism: BackendLoweringMechanism::InlinePtx,
-                evidence_profile: admission
-                    .reduce_libnvvm_evidence_profile
-                    .as_ref()
-                    .expect("validated TMA reduction libNVVM evidence profile")
-                    .clone(),
-                targets: None,
-                minimum_ptx: Some("8.0".into()),
-                minimum_sm: Some("sm_90".into()),
-            },
-        ],
-        packed_atomic: None,
-        redux: None,
-        vote: None,
-        active_mask: None,
-        warp_match: None,
-        warp_barrier: None,
-        warp_shuffle: None,
-        dot_product: None,
-        packed_alu: None,
-        integer_minmax: None,
-        packed_conversion: None,
-        scalar_conversion: None,
-        scalar_arithmetic: None,
-        scalar_math: None,
-        extended_minmax: None,
-        cp_async_copy: None,
-        cp_async_control: None,
-        cp_async_mbarrier: None,
-        mbarrier_basic: None,
-        movmatrix: None,
-        mbarrier_extended: None,
-        register_mma: None,
-        sparse_mma: None,
-        prmt: None,
-        cluster_barrier: None,
-        wgmma_control: None,
-        special_register: None,
-        debug_control: None,
-        cluster_memory: None,
-        clc: None,
-        tma: Some(Tma {
-            operation: TmaOperation::Reduce,
-            reduction: Some(reduction),
-            adapter: TmaAdapter::ReductionPointersCoordinatesInjectDefaults,
-            runtime_validation: admission.runtime_validation,
-        }),
-        tcgen05: None,
-        ldmatrix_variant: None,
-        ldmatrix_safety: None,
-        ldmatrix_adapter: None,
-        selected_address_space: None,
-        expected_ptx: InstructionPattern {
-            mnemonic: "cp".into(),
-            modifiers: recipe.modifiers,
-            operands: recipe.operands,
-        },
-        summary: recipe.summary,
-    })
-}
-
-struct TmaRecipe {
-    operation: TmaOperation,
-    abi_id: &'static str,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    resolved_llvm_symbol: Option<String>,
-    selected_address_space: Option<ImportedAddressSpace>,
-    llvm_mechanism: BackendLoweringMechanism,
-    rust_arguments: Vec<&'static str>,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    dialect_operands: Vec<&'static str>,
-    llvm_arguments: Vec<&'static str>,
-    adapter: TmaAdapter,
-    safe: bool,
-    safe_reason: Option<&'static str>,
-    convergent: bool,
-    minimum_ptx: &'static str,
-    minimum_sm: Option<&'static str>,
-    targets: &'static str,
-    memory: &'static str,
-    ptx_isa_section: &'static str,
-    ptx_isa_url: &'static str,
-    mnemonic: &'static str,
-    modifiers: Vec<String>,
-    operands: Vec<OperandPattern>,
-    summary: &'static str,
-}
-
-fn tma_recipe(operation: TmaOperation) -> TmaRecipe {
-    let (abi_id, id, operation_key, source_record, llvm_symbol, op_type, op_name) = match operation
-    {
-        TmaOperation::Reduce => unreachable!("TMA reductions use tma_reduction_recipe"),
-        TmaOperation::G2sTile1d => (
-            "i0328",
-            "cp_async_bulk_tensor_1d_g2s",
-            "memory.copy.async.bulk.tensor.g2s.tile.1d",
-            "int_nvvm_cp_async_bulk_tensor_g2s_tile_1d",
-            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.1d",
-            "CpAsyncBulkTensorG2sTile1dOp",
-            "nvvm.cp_async_bulk_tensor_g2s_tile_1d",
-        ),
-        TmaOperation::G2sTile2d => (
-            "i0329",
-            "cp_async_bulk_tensor_2d_g2s",
-            "memory.copy.async.bulk.tensor.g2s.tile.2d",
-            "int_nvvm_cp_async_bulk_tensor_g2s_tile_2d",
-            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d",
-            "CpAsyncBulkTensorG2sTile2dOp",
-            "nvvm.cp_async_bulk_tensor_g2s_tile_2d",
-        ),
-        TmaOperation::G2sTile2dMulticast => (
-            "i0330",
-            "cp_async_bulk_tensor_2d_g2s_multicast",
-            "memory.copy.async.bulk.tensor.g2s.tile.2d.multicast",
-            "int_nvvm_cp_async_bulk_tensor_g2s_tile_2d",
-            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d",
-            "CpAsyncBulkTensorG2sTile2dMulticastOp",
-            "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast",
-        ),
-        TmaOperation::G2sTile2dMulticastCg2 => (
-            "i0331",
-            "cp_async_bulk_tensor_2d_g2s_multicast_cg2",
-            "memory.copy.async.bulk.tensor.g2s.tile.2d.multicast.cta_group_2",
-            "int_nvvm_cp_async_bulk_tensor_g2s_tile_2d",
-            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d",
-            "CpAsyncBulkTensorG2sTile2dMulticastCg2Op",
-            "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast_cg2",
-        ),
-        TmaOperation::G2sTile3d => (
-            "i0332",
-            "cp_async_bulk_tensor_3d_g2s",
-            "memory.copy.async.bulk.tensor.g2s.tile.3d",
-            "int_nvvm_cp_async_bulk_tensor_g2s_tile_3d",
-            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.3d",
-            "CpAsyncBulkTensorG2sTile3dOp",
-            "nvvm.cp_async_bulk_tensor_g2s_tile_3d",
-        ),
-        TmaOperation::G2sTile4d => (
-            "i0333",
-            "cp_async_bulk_tensor_4d_g2s",
-            "memory.copy.async.bulk.tensor.g2s.tile.4d",
-            "int_nvvm_cp_async_bulk_tensor_g2s_tile_4d",
-            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.4d",
-            "CpAsyncBulkTensorG2sTile4dOp",
-            "nvvm.cp_async_bulk_tensor_g2s_tile_4d",
-        ),
-        TmaOperation::G2sTile5d => (
-            "i0334",
-            "cp_async_bulk_tensor_5d_g2s",
-            "memory.copy.async.bulk.tensor.g2s.tile.5d",
-            "int_nvvm_cp_async_bulk_tensor_g2s_tile_5d",
-            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.5d",
-            "CpAsyncBulkTensorG2sTile5dOp",
-            "nvvm.cp_async_bulk_tensor_g2s_tile_5d",
-        ),
-        TmaOperation::S2gTile1d => (
-            "i0335",
-            "cp_async_bulk_tensor_1d_s2g",
-            "memory.copy.async.bulk.tensor.s2g.tile.1d",
-            "int_nvvm_cp_async_bulk_tensor_s2g_tile_1d",
-            "llvm.nvvm.cp.async.bulk.tensor.s2g.tile.1d",
-            "CpAsyncBulkTensorS2gTile1dOp",
-            "nvvm.cp_async_bulk_tensor_s2g_tile_1d",
-        ),
-        TmaOperation::S2gTile2d => (
-            "i0336",
-            "cp_async_bulk_tensor_2d_s2g",
-            "memory.copy.async.bulk.tensor.s2g.tile.2d",
-            "int_nvvm_cp_async_bulk_tensor_s2g_tile_2d",
-            "llvm.nvvm.cp.async.bulk.tensor.s2g.tile.2d",
-            "CpAsyncBulkTensorS2gTile2dOp",
-            "nvvm.cp_async_bulk_tensor_s2g_tile_2d",
-        ),
-        TmaOperation::S2gTile3d => (
-            "i0337",
-            "cp_async_bulk_tensor_3d_s2g",
-            "memory.copy.async.bulk.tensor.s2g.tile.3d",
-            "int_nvvm_cp_async_bulk_tensor_s2g_tile_3d",
-            "llvm.nvvm.cp.async.bulk.tensor.s2g.tile.3d",
-            "CpAsyncBulkTensorS2gTile3dOp",
-            "nvvm.cp_async_bulk_tensor_s2g_tile_3d",
-        ),
-        TmaOperation::S2gTile4d => (
-            "i0338",
-            "cp_async_bulk_tensor_4d_s2g",
-            "memory.copy.async.bulk.tensor.s2g.tile.4d",
-            "int_nvvm_cp_async_bulk_tensor_s2g_tile_4d",
-            "llvm.nvvm.cp.async.bulk.tensor.s2g.tile.4d",
-            "CpAsyncBulkTensorS2gTile4dOp",
-            "nvvm.cp_async_bulk_tensor_s2g_tile_4d",
-        ),
-        TmaOperation::S2gTile5d => (
-            "i0339",
-            "cp_async_bulk_tensor_5d_s2g",
-            "memory.copy.async.bulk.tensor.s2g.tile.5d",
-            "int_nvvm_cp_async_bulk_tensor_s2g_tile_5d",
-            "llvm.nvvm.cp.async.bulk.tensor.s2g.tile.5d",
-            "CpAsyncBulkTensorS2gTile5dOp",
-            "nvvm.cp_async_bulk_tensor_s2g_tile_5d",
-        ),
-        TmaOperation::CommitGroup => (
-            "i0340",
-            "cp_async_bulk_commit_group",
-            "memory.copy.async.bulk.group.commit",
-            "int_nvvm_cp_async_bulk_commit_group",
-            "llvm.nvvm.cp.async.bulk.commit.group",
-            "CpAsyncBulkCommitGroupOp",
-            "nvvm.cp_async_bulk_commit_group",
-        ),
-        TmaOperation::WaitGroup => (
-            "i0341",
-            "cp_async_bulk_wait_group",
-            "memory.copy.async.bulk.group.wait_max_pending",
-            "int_nvvm_cp_async_bulk_wait_group",
-            "llvm.nvvm.cp.async.bulk.wait.group",
-            "CpAsyncBulkWaitGroupOp",
-            "nvvm.cp_async_bulk_wait_group",
-        ),
-        TmaOperation::WaitGroupRead => (
-            "i0342",
-            "cp_async_bulk_wait_group_read",
-            "memory.copy.async.bulk.group.wait_read_max_pending",
-            "int_nvvm_cp_async_bulk_wait_group_read",
-            "llvm.nvvm.cp.async.bulk.wait.group.read",
-            "CpAsyncBulkWaitGroupReadOp",
-            "nvvm.cp_async_bulk_wait_group_read",
-        ),
-        TmaOperation::PrefetchTensorMap => (
-            "i0887",
-            "prefetch_tma_descriptor",
-            "memory.prefetch.tensor_map",
-            "int_nvvm_prefetch_tensormap",
-            "llvm.nvvm.prefetch.tensormap",
-            "PrefetchTensorMapOp",
-            "nvvm.prefetch_tensormap",
-        ),
-        TmaOperation::PrefetchTile1d => (
-            "i0888",
-            "cp_async_bulk_prefetch_tensor_1d_l2",
-            "memory.prefetch.async.bulk.tensor.global.tile.1d.l2",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_1d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d",
-            "CpAsyncBulkPrefetchTensor1dL2Op",
-            "nvvm.cp_async_bulk_prefetch_tensor_1d_l2",
-        ),
-        TmaOperation::PrefetchTile2d => (
-            "i0889",
-            "cp_async_bulk_prefetch_tensor_2d_l2",
-            "memory.prefetch.async.bulk.tensor.global.tile.2d.l2",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_2d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d",
-            "CpAsyncBulkPrefetchTensor2dL2Op",
-            "nvvm.cp_async_bulk_prefetch_tensor_2d_l2",
-        ),
-        TmaOperation::PrefetchTile3d => (
-            "i0890",
-            "cp_async_bulk_prefetch_tensor_3d_l2",
-            "memory.prefetch.async.bulk.tensor.global.tile.3d.l2",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_3d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d",
-            "CpAsyncBulkPrefetchTensor3dL2Op",
-            "nvvm.cp_async_bulk_prefetch_tensor_3d_l2",
-        ),
-        TmaOperation::PrefetchTile4d => (
-            "i0891",
-            "cp_async_bulk_prefetch_tensor_4d_l2",
-            "memory.prefetch.async.bulk.tensor.global.tile.4d.l2",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_4d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d",
-            "CpAsyncBulkPrefetchTensor4dL2Op",
-            "nvvm.cp_async_bulk_prefetch_tensor_4d_l2",
-        ),
-        TmaOperation::PrefetchTile5d => (
-            "i0892",
-            "cp_async_bulk_prefetch_tensor_5d_l2",
-            "memory.prefetch.async.bulk.tensor.global.tile.5d.l2",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_5d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d",
-            "CpAsyncBulkPrefetchTensor5dL2Op",
-            "nvvm.cp_async_bulk_prefetch_tensor_5d_l2",
-        ),
-        TmaOperation::PrefetchTileGather4TwoDimensional => (
-            "i0893",
-            "cp_async_bulk_prefetch_tensor_gather4_2d_l2",
-            "memory.prefetch.async.bulk.tensor.global.tile.gather4.2d.l2",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_gather4_2d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.gather4.2d",
-            "CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op",
-            "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2",
-        ),
-        TmaOperation::PrefetchTile1dCacheHint => (
-            "i0917",
-            "cp_async_bulk_prefetch_tensor_1d_l2_cache_hint",
-            "memory.prefetch.async.bulk.tensor.global.tile.1d.l2.cache_hint",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_1d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d",
-            "CpAsyncBulkPrefetchTensor1dL2CacheHintOp",
-            "nvvm.cp_async_bulk_prefetch_tensor_1d_l2_cache_hint",
-        ),
-        TmaOperation::PrefetchTile2dCacheHint => (
-            "i0918",
-            "cp_async_bulk_prefetch_tensor_2d_l2_cache_hint",
-            "memory.prefetch.async.bulk.tensor.global.tile.2d.l2.cache_hint",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_2d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d",
-            "CpAsyncBulkPrefetchTensor2dL2CacheHintOp",
-            "nvvm.cp_async_bulk_prefetch_tensor_2d_l2_cache_hint",
-        ),
-        TmaOperation::PrefetchTile3dCacheHint => (
-            "i0919",
-            "cp_async_bulk_prefetch_tensor_3d_l2_cache_hint",
-            "memory.prefetch.async.bulk.tensor.global.tile.3d.l2.cache_hint",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_3d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d",
-            "CpAsyncBulkPrefetchTensor3dL2CacheHintOp",
-            "nvvm.cp_async_bulk_prefetch_tensor_3d_l2_cache_hint",
-        ),
-        TmaOperation::PrefetchTile4dCacheHint => (
-            "i0920",
-            "cp_async_bulk_prefetch_tensor_4d_l2_cache_hint",
-            "memory.prefetch.async.bulk.tensor.global.tile.4d.l2.cache_hint",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_4d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d",
-            "CpAsyncBulkPrefetchTensor4dL2CacheHintOp",
-            "nvvm.cp_async_bulk_prefetch_tensor_4d_l2_cache_hint",
-        ),
-        TmaOperation::PrefetchTile5dCacheHint => (
-            "i0921",
-            "cp_async_bulk_prefetch_tensor_5d_l2_cache_hint",
-            "memory.prefetch.async.bulk.tensor.global.tile.5d.l2.cache_hint",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_5d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d",
-            "CpAsyncBulkPrefetchTensor5dL2CacheHintOp",
-            "nvvm.cp_async_bulk_prefetch_tensor_5d_l2_cache_hint",
-        ),
-        TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint => (
-            "i0922",
-            "cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint",
-            "memory.prefetch.async.bulk.tensor.global.tile.gather4.2d.l2.cache_hint",
-            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_gather4_2d",
-            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.gather4.2d",
-            "CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp",
-            "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint",
-        ),
-        TmaOperation::ReplaceBoxDim => (
-            "i0894",
-            "tensormap_replace_box_dim",
-            "memory.tensor_map.replace.box_dim",
-            "int_nvvm_tensormap_replace_box_dim",
-            "llvm.nvvm.tensormap.replace.box.dim",
-            "ReplaceTensorMapBoxDimOp",
-            "nvvm.tensormap_replace_box_dim",
-        ),
-        TmaOperation::ReplaceElementStride => (
-            "i0895",
-            "tensormap_replace_element_stride",
-            "memory.tensor_map.replace.element_stride",
-            "int_nvvm_tensormap_replace_element_stride",
-            "llvm.nvvm.tensormap.replace.element.stride",
-            "ReplaceTensorMapElementStrideOp",
-            "nvvm.tensormap_replace_element_stride",
-        ),
-        TmaOperation::ReplaceElementType => (
-            "i0896",
-            "tensormap_replace_element_type",
-            "memory.tensor_map.replace.element_type",
-            "int_nvvm_tensormap_replace_elemtype",
-            "llvm.nvvm.tensormap.replace.elemtype",
-            "ReplaceTensorMapElementTypeOp",
-            "nvvm.tensormap_replace_element_type",
-        ),
-        TmaOperation::ReplaceFillMode => (
-            "i0897",
-            "tensormap_replace_fill_mode",
-            "memory.tensor_map.replace.fill_mode",
-            "int_nvvm_tensormap_replace_fill_mode",
-            "llvm.nvvm.tensormap.replace.fill.mode",
-            "ReplaceTensorMapFillModeOp",
-            "nvvm.tensormap_replace_fill_mode",
-        ),
-        TmaOperation::ReplaceGlobalAddress => (
-            "i0898",
-            "tensormap_replace_global_address",
-            "memory.tensor_map.replace.global_address",
-            "int_nvvm_tensormap_replace_global_address",
-            "llvm.nvvm.tensormap.replace.global.address",
-            "ReplaceTensorMapGlobalAddressOp",
-            "nvvm.tensormap_replace_global_address",
-        ),
-        TmaOperation::ReplaceGlobalDim => (
-            "i0899",
-            "tensormap_replace_global_dim",
-            "memory.tensor_map.replace.global_dim",
-            "int_nvvm_tensormap_replace_global_dim",
-            "llvm.nvvm.tensormap.replace.global.dim",
-            "ReplaceTensorMapGlobalDimOp",
-            "nvvm.tensormap_replace_global_dim",
-        ),
-        TmaOperation::ReplaceGlobalStride => (
-            "i0900",
-            "tensormap_replace_global_stride",
-            "memory.tensor_map.replace.global_stride",
-            "int_nvvm_tensormap_replace_global_stride",
-            "llvm.nvvm.tensormap.replace.global.stride",
-            "ReplaceTensorMapGlobalStrideOp",
-            "nvvm.tensormap_replace_global_stride",
-        ),
-        TmaOperation::ReplaceInterleaveLayout => (
-            "i0901",
-            "tensormap_replace_interleave_layout",
-            "memory.tensor_map.replace.interleave_layout",
-            "int_nvvm_tensormap_replace_interleave_layout",
-            "llvm.nvvm.tensormap.replace.interleave.layout",
-            "ReplaceTensorMapInterleaveLayoutOp",
-            "nvvm.tensormap_replace_interleave_layout",
-        ),
-        TmaOperation::ReplaceRank => (
-            "i0902",
-            "tensormap_replace_rank",
-            "memory.tensor_map.replace.rank",
-            "int_nvvm_tensormap_replace_rank",
-            "llvm.nvvm.tensormap.replace.rank",
-            "ReplaceTensorMapRankOp",
-            "nvvm.tensormap_replace_rank",
-        ),
-        TmaOperation::ReplaceSwizzleAtomicity => (
-            "i0903",
-            "tensormap_replace_swizzle_atomicity",
-            "memory.tensor_map.replace.swizzle_atomicity",
-            "int_nvvm_tensormap_replace_swizzle_atomicity",
-            "llvm.nvvm.tensormap.replace.swizzle.atomicity",
-            "ReplaceTensorMapSwizzleAtomicityOp",
-            "nvvm.tensormap_replace_swizzle_atomicity",
-        ),
-        TmaOperation::ReplaceSwizzleMode => (
-            "i0904",
-            "tensormap_replace_swizzle_mode",
-            "memory.tensor_map.replace.swizzle_mode",
-            "int_nvvm_tensormap_replace_swizzle_mode",
-            "llvm.nvvm.tensormap.replace.swizzle.mode",
-            "ReplaceTensorMapSwizzleModeOp",
-            "nvvm.tensormap_replace_swizzle_mode",
-        ),
-        TmaOperation::FenceProxyTensorMapAcquireCluster => (
-            "i0905",
-            "fence_proxy_tensormap_generic_acquire_cluster",
-            "memory.fence.proxy.tensor_map.generic.acquire.cluster",
-            "int_nvvm_fence_proxy_tensormap_generic_acquire_cluster",
-            "llvm.nvvm.fence.proxy.tensormap_generic.acquire.cluster",
-            "FenceProxyTensorMapGenericAcquireClusterOp",
-            "nvvm.fence_proxy_tensormap_generic_acquire_cluster",
-        ),
-        TmaOperation::FenceProxyTensorMapAcquireCta => (
-            "i0906",
-            "fence_proxy_tensormap_generic_acquire_cta",
-            "memory.fence.proxy.tensor_map.generic.acquire.cta",
-            "int_nvvm_fence_proxy_tensormap_generic_acquire_cta",
-            "llvm.nvvm.fence.proxy.tensormap_generic.acquire.cta",
-            "FenceProxyTensorMapGenericAcquireCtaOp",
-            "nvvm.fence_proxy_tensormap_generic_acquire_cta",
-        ),
-        TmaOperation::FenceProxyTensorMapAcquireGpu => (
-            "i0907",
-            "fence_proxy_tensormap_generic_acquire_gpu",
-            "memory.fence.proxy.tensor_map.generic.acquire.gpu",
-            "int_nvvm_fence_proxy_tensormap_generic_acquire_gpu",
-            "llvm.nvvm.fence.proxy.tensormap_generic.acquire.gpu",
-            "FenceProxyTensorMapGenericAcquireGpuOp",
-            "nvvm.fence_proxy_tensormap_generic_acquire_gpu",
-        ),
-        TmaOperation::FenceProxyTensorMapAcquireSystem => (
-            "i0908",
-            "fence_proxy_tensormap_generic_acquire_system",
-            "memory.fence.proxy.tensor_map.generic.acquire.system",
-            "int_nvvm_fence_proxy_tensormap_generic_acquire_sys",
-            "llvm.nvvm.fence.proxy.tensormap_generic.acquire.sys",
-            "FenceProxyTensorMapGenericAcquireSystemOp",
-            "nvvm.fence_proxy_tensormap_generic_acquire_system",
-        ),
-        TmaOperation::FenceProxyTensorMapReleaseCluster => (
-            "i0909",
-            "fence_proxy_tensormap_generic_release_cluster",
-            "memory.fence.proxy.tensor_map.generic.release.cluster",
-            "int_nvvm_fence_proxy_tensormap_generic_release_cluster",
-            "llvm.nvvm.fence.proxy.tensormap_generic.release.cluster",
-            "FenceProxyTensorMapGenericReleaseClusterOp",
-            "nvvm.fence_proxy_tensormap_generic_release_cluster",
-        ),
-        TmaOperation::FenceProxyTensorMapReleaseCta => (
-            "i0910",
-            "fence_proxy_tensormap_generic_release_cta",
-            "memory.fence.proxy.tensor_map.generic.release.cta",
-            "int_nvvm_fence_proxy_tensormap_generic_release_cta",
-            "llvm.nvvm.fence.proxy.tensormap_generic.release.cta",
-            "FenceProxyTensorMapGenericReleaseCtaOp",
-            "nvvm.fence_proxy_tensormap_generic_release_cta",
-        ),
-        TmaOperation::FenceProxyTensorMapReleaseGpu => (
-            "i0911",
-            "fence_proxy_tensormap_generic_release_gpu",
-            "memory.fence.proxy.tensor_map.generic.release.gpu",
-            "int_nvvm_fence_proxy_tensormap_generic_release_gpu",
-            "llvm.nvvm.fence.proxy.tensormap_generic.release.gpu",
-            "FenceProxyTensorMapGenericReleaseGpuOp",
-            "nvvm.fence_proxy_tensormap_generic_release_gpu",
-        ),
-        TmaOperation::FenceProxyTensorMapReleaseSystem => (
-            "i0912",
-            "fence_proxy_tensormap_generic_release_system",
-            "memory.fence.proxy.tensor_map.generic.release.system",
-            "int_nvvm_fence_proxy_tensormap_generic_release_sys",
-            "llvm.nvvm.fence.proxy.tensormap_generic.release.sys",
-            "FenceProxyTensorMapGenericReleaseSystemOp",
-            "nvvm.fence_proxy_tensormap_generic_release_system",
-        ),
-    };
-
-    let dimensions = operation.dimensions();
-    let is_g2s = matches!(
-        operation,
-        TmaOperation::G2sTile1d
-            | TmaOperation::G2sTile2d
-            | TmaOperation::G2sTile2dMulticast
-            | TmaOperation::G2sTile2dMulticastCg2
-            | TmaOperation::G2sTile3d
-            | TmaOperation::G2sTile4d
-            | TmaOperation::G2sTile5d
-    );
-    let is_s2g = matches!(
-        operation,
-        TmaOperation::S2gTile1d
-            | TmaOperation::S2gTile2d
-            | TmaOperation::S2gTile3d
-            | TmaOperation::S2gTile4d
-            | TmaOperation::S2gTile5d
-    );
-    let multicast = matches!(
-        operation,
-        TmaOperation::G2sTile2dMulticast | TmaOperation::G2sTile2dMulticastCg2
-    );
-    let cg2 = operation == TmaOperation::G2sTile2dMulticastCg2;
-    let prefetch_coordinates = operation.prefetch_coordinate_count();
-    let is_release_fence = matches!(
-        operation,
-        TmaOperation::FenceProxyTensorMapReleaseCluster
-            | TmaOperation::FenceProxyTensorMapReleaseCta
-            | TmaOperation::FenceProxyTensorMapReleaseGpu
-            | TmaOperation::FenceProxyTensorMapReleaseSystem
-    );
-    let is_acquire_fence = matches!(
-        operation,
-        TmaOperation::FenceProxyTensorMapAcquireCluster
-            | TmaOperation::FenceProxyTensorMapAcquireCta
-            | TmaOperation::FenceProxyTensorMapAcquireGpu
-            | TmaOperation::FenceProxyTensorMapAcquireSystem
-    );
-
-    let mut rust_arguments = Vec::new();
-    let mut dialect_operands = Vec::new();
-    let mut llvm_arguments = Vec::new();
-    let (adapter, safe, safe_reason, convergent, summary) = if is_g2s {
-        rust_arguments.extend(["*mut u8", "*const u8"]);
-        rust_arguments.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
-        rust_arguments.push("*mut u64");
-        if multicast {
-            rust_arguments.push("u16");
-        }
-        dialect_operands.extend(["ptr", "ptr", "ptr"]);
-        dialect_operands.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
-        dialect_operands.extend(["i16", "i64"]);
-        llvm_arguments.extend(["shared_cluster_ptr", "shared_ptr", "ptr"]);
-        llvm_arguments.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
-        llvm_arguments.extend(["i16", "i64", "i1", "i1", "i32"]);
-        (
-            if multicast {
-                TmaAdapter::G2sPointersCoordinatesBarrierMaskInjectDefaults
-            } else {
-                TmaAdapter::G2sPointersCoordinatesBarrierInjectDefaults
-            },
-            false,
-            None,
-            true,
-            if multicast {
-                "Starts a multicast TMA tile copy from global to cluster shared memory."
-            } else {
-                "Starts a TMA tile copy from global to cluster shared memory."
-            },
-        )
-    } else if is_s2g {
-        rust_arguments.extend(["*const u8", "*const u8"]);
-        rust_arguments.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
-        dialect_operands.extend(["ptr", "ptr"]);
-        dialect_operands.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
-        llvm_arguments.extend(["shared_ptr", "ptr"]);
-        llvm_arguments.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
-        llvm_arguments.extend(["i64", "i1"]);
-        (
-            TmaAdapter::S2gPointersCoordinatesInjectDefaults,
-            false,
-            None,
-            true,
-            "Starts a TMA tile copy from shared to global memory.",
-        )
-    } else if operation == TmaOperation::CommitGroup || is_release_fence {
-        (
-            TmaAdapter::NoOperands,
-            true,
-            Some(if operation == TmaOperation::CommitGroup {
-                "committing this thread's pending bulk-copy group has no Rust memory-safety precondition."
-            } else {
-                "publishing prior tensor-map writes has no Rust memory-safety precondition."
-            }),
-            false,
-            if operation == TmaOperation::CommitGroup {
-                "Commits this thread's pending asynchronous bulk copies as one group."
-            } else {
-                "Publishes prior generic-proxy tensor-map writes to the selected tensor-map proxy scope."
-            },
-        )
-    } else if operation == TmaOperation::PrefetchTensorMap {
-        rust_arguments.push("*const u8");
-        dialect_operands.push("ptr");
-        llvm_arguments.push("anyptr");
-        (
-            TmaAdapter::DescriptorPointer,
-            false,
-            None,
-            false,
-            "Prefetches a live tensor-map descriptor into the tensor-map cache.",
-        )
-    } else if let Some(coordinate_count) = prefetch_coordinates {
-        rust_arguments.push("*const u8");
-        rust_arguments.extend(std::iter::repeat_n("i32", coordinate_count));
-        dialect_operands.push("ptr");
-        dialect_operands.extend(std::iter::repeat_n("i32", coordinate_count));
-        if operation.uses_prefetch_cache_hint() {
-            rust_arguments.push("u64");
-            dialect_operands.push("i64");
-        }
-        llvm_arguments.push("ptr");
-        llvm_arguments.extend(std::iter::repeat_n("i32", coordinate_count));
-        llvm_arguments.extend(["i64", "i1"]);
-        (
-            if operation.uses_prefetch_cache_hint() {
-                TmaAdapter::DescriptorCoordinatesCacheHintInjectFlag
-            } else {
-                TmaAdapter::DescriptorCoordinatesInjectDefaults
-            },
-            false,
-            None,
-            true,
-            if operation.uses_prefetch_cache_hint() {
-                "Prefetches one tensor tile through a tensor map into L2 using an explicit cache hint."
-            } else {
-                "Prefetches one tensor tile through a tensor map into L2."
-            },
-        )
-    } else if operation == TmaOperation::ReplaceGlobalAddress {
-        rust_arguments.extend(["*mut u8", "*const u8"]);
-        dialect_operands.extend(["ptr", "ptr"]);
-        llvm_arguments.extend(["anyptr", "i64"]);
-        (
-            TmaAdapter::DescriptorAndAddressPointers,
-            false,
-            None,
-            false,
-            "Replaces the global base address stored in a writable tensor-map descriptor.",
-        )
-    } else if matches!(
-        operation,
-        TmaOperation::ReplaceBoxDim
-            | TmaOperation::ReplaceElementStride
-            | TmaOperation::ReplaceGlobalDim
-    ) {
-        rust_arguments.extend(["*mut u8", "u32", "u32"]);
-        dialect_operands.extend(["ptr", "i32", "i32"]);
-        llvm_arguments.extend(["anyptr", "i32", "i32"]);
-        (
-            TmaAdapter::DescriptorOrdinalAndU32,
-            false,
-            None,
-            false,
-            "Replaces one indexed 32-bit field in a writable tensor-map descriptor.",
-        )
-    } else if operation == TmaOperation::ReplaceGlobalStride {
-        rust_arguments.extend(["*mut u8", "u32", "u64"]);
-        dialect_operands.extend(["ptr", "i32", "i64"]);
-        llvm_arguments.extend(["anyptr", "i32", "i64"]);
-        (
-            TmaAdapter::DescriptorOrdinalAndU64,
-            false,
-            None,
-            false,
-            "Replaces one indexed 64-bit stride in a writable tensor-map descriptor.",
-        )
-    } else if matches!(
-        operation,
-        TmaOperation::ReplaceElementType
-            | TmaOperation::ReplaceFillMode
-            | TmaOperation::ReplaceInterleaveLayout
-            | TmaOperation::ReplaceSwizzleAtomicity
-            | TmaOperation::ReplaceSwizzleMode
-    ) {
-        rust_arguments.extend(["*mut u8", "u32"]);
-        dialect_operands.extend(["ptr", "i32"]);
-        llvm_arguments.extend(["anyptr", "i32"]);
-        (
-            TmaAdapter::DescriptorAndImmediateU32,
-            false,
-            None,
-            false,
-            "Replaces one immediate-valued field in a writable tensor-map descriptor.",
-        )
-    } else if operation == TmaOperation::ReplaceRank {
-        rust_arguments.extend(["*mut u8", "u32"]);
-        dialect_operands.extend(["ptr", "i32"]);
-        llvm_arguments.extend(["anyptr", "i32"]);
-        (
-            TmaAdapter::DescriptorAndRuntimeU32,
-            false,
-            None,
-            false,
-            "Replaces the rank stored in a writable tensor-map descriptor.",
-        )
-    } else if is_acquire_fence {
-        rust_arguments.push("*const u8");
-        dialect_operands.push("ptr");
-        llvm_arguments.extend(["ptr", "i32"]);
-        (
-            TmaAdapter::DescriptorPointerInjectBytes,
-            false,
-            None,
-            false,
-            "Acquires a published tensor-map descriptor into the selected tensor-map proxy scope.",
-        )
-    } else {
-        rust_arguments.push("u32");
-        dialect_operands.push("i32");
-        llvm_arguments.push("i32");
-        (
-            TmaAdapter::CompileTimeConstantMaxPending,
-            true,
-            Some(
-                "waiting on this thread's bulk-copy groups has no Rust memory-safety precondition.",
-            ),
-            false,
-            if operation == TmaOperation::WaitGroupRead {
-                "Waits for bulk-copy groups and completes their reads."
-            } else {
-                "Waits until at most the requested bulk-copy groups remain pending."
-            },
-        )
-    };
-
-    let is_replace = matches!(
-        operation,
-        TmaOperation::ReplaceBoxDim
-            | TmaOperation::ReplaceElementStride
-            | TmaOperation::ReplaceElementType
-            | TmaOperation::ReplaceFillMode
-            | TmaOperation::ReplaceGlobalAddress
-            | TmaOperation::ReplaceGlobalDim
-            | TmaOperation::ReplaceGlobalStride
-            | TmaOperation::ReplaceInterleaveLayout
-            | TmaOperation::ReplaceRank
-            | TmaOperation::ReplaceSwizzleAtomicity
-            | TmaOperation::ReplaceSwizzleMode
-    );
-    let is_fence = is_acquire_fence || is_release_fence;
-    let descriptor_control = operation == TmaOperation::PrefetchTensorMap
-        || prefetch_coordinates.is_some()
-        || is_replace
-        || is_fence;
-    let blackwell_tma = cg2
-        || matches!(
-            operation,
-            TmaOperation::PrefetchTileGather4TwoDimensional
-                | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint
-        );
-
-    let (mnemonic, modifiers, operands) = if is_g2s {
-        let mut modifiers = vec![
-            "async".into(),
-            "bulk".into(),
-            "tensor".into(),
-            format!("{}d", dimensions.unwrap()),
-            "shared::cluster".into(),
-            "global".into(),
-            "tile".into(),
-            "mbarrier::complete_tx::bytes".into(),
-        ];
-        if multicast {
-            modifiers.push("multicast::cluster".into());
-        }
-        if cg2 {
-            modifiers.push("cta_group::2".into());
-        }
-        let mut operands = vec![
-            OperandPattern::Address,
-            OperandPattern::Address,
-            OperandPattern::Address,
-        ];
-        if multicast {
-            operands.push(OperandPattern::Register);
-        }
-        ("cp", modifiers, operands)
-    } else if is_s2g {
-        (
-            "cp",
-            vec![
-                "async".into(),
-                "bulk".into(),
-                "tensor".into(),
-                format!("{}d", dimensions.unwrap()),
-                "global".into(),
-                "shared::cta".into(),
-                "tile".into(),
-                "bulk_group".into(),
-            ],
-            vec![OperandPattern::Address, OperandPattern::Address],
-        )
-    } else if operation == TmaOperation::CommitGroup {
-        (
-            "cp",
-            vec!["async".into(), "bulk".into(), "commit_group".into()],
-            vec![],
-        )
-    } else if matches!(
-        operation,
-        TmaOperation::WaitGroup | TmaOperation::WaitGroupRead
-    ) {
-        let mut modifiers = vec!["async".into(), "bulk".into(), "wait_group".into()];
-        if operation == TmaOperation::WaitGroupRead {
-            modifiers.push("read".into());
-        }
-        ("cp", modifiers, vec![OperandPattern::Immediate])
-    } else if operation == TmaOperation::PrefetchTensorMap {
-        (
-            "prefetch",
-            vec!["tensormap".into()],
-            vec![OperandPattern::Address],
-        )
-    } else if prefetch_coordinates.is_some() {
-        let (dimensionality, tile) = if matches!(
-            operation,
-            TmaOperation::PrefetchTileGather4TwoDimensional
-                | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint
-        ) {
-            ("2d", "tile::gather4")
-        } else {
-            (
-                match prefetch_coordinates.unwrap() {
-                    1 => "1d",
-                    2 => "2d",
-                    3 => "3d",
-                    4 => "4d",
-                    5 => "5d",
-                    _ => unreachable!("closed TMA prefetch dimensionality"),
-                },
-                "tile",
-            )
-        };
-        let mut modifiers = vec![
-            "async".into(),
-            "bulk".into(),
-            "prefetch".into(),
-            "tensor".into(),
-            dimensionality.into(),
-            "L2".into(),
-            "global".into(),
-            tile.into(),
-        ];
-        let mut operands = vec![OperandPattern::Address];
-        if operation.uses_prefetch_cache_hint() {
-            modifiers.push("L2::cache_hint".into());
-            operands.push(OperandPattern::Register);
-        }
-        ("cp", modifiers, operands)
-    } else if is_replace {
-        let (field, width, operands) = match operation {
-            TmaOperation::ReplaceGlobalAddress => (
-                "global_address",
-                "b64",
-                vec![OperandPattern::Address, OperandPattern::Register],
-            ),
-            TmaOperation::ReplaceRank => (
-                "rank",
-                "b32",
-                vec![OperandPattern::Address, OperandPattern::Register],
-            ),
-            TmaOperation::ReplaceBoxDim => (
-                "box_dim",
-                "b32",
-                vec![
-                    OperandPattern::Address,
-                    OperandPattern::Immediate,
-                    OperandPattern::Register,
-                ],
-            ),
-            TmaOperation::ReplaceElementStride => (
-                "element_stride",
-                "b32",
-                vec![
-                    OperandPattern::Address,
-                    OperandPattern::Immediate,
-                    OperandPattern::Register,
-                ],
-            ),
-            TmaOperation::ReplaceGlobalDim => (
-                "global_dim",
-                "b32",
-                vec![
-                    OperandPattern::Address,
-                    OperandPattern::Immediate,
-                    OperandPattern::Register,
-                ],
-            ),
-            TmaOperation::ReplaceGlobalStride => (
-                "global_stride",
-                "b64",
-                vec![
-                    OperandPattern::Address,
-                    OperandPattern::Immediate,
-                    OperandPattern::Register,
-                ],
-            ),
-            TmaOperation::ReplaceElementType => (
-                "elemtype",
-                "b32",
-                vec![OperandPattern::Address, OperandPattern::Immediate],
-            ),
-            TmaOperation::ReplaceFillMode => (
-                "fill_mode",
-                "b32",
-                vec![OperandPattern::Address, OperandPattern::Immediate],
-            ),
-            TmaOperation::ReplaceInterleaveLayout => (
-                "interleave_layout",
-                "b32",
-                vec![OperandPattern::Address, OperandPattern::Immediate],
-            ),
-            TmaOperation::ReplaceSwizzleAtomicity => (
-                "swizzle_atomicity",
-                "b32",
-                vec![OperandPattern::Address, OperandPattern::Immediate],
-            ),
-            TmaOperation::ReplaceSwizzleMode => (
-                "swizzle_mode",
-                "b32",
-                vec![OperandPattern::Address, OperandPattern::Immediate],
-            ),
-            _ => unreachable!("TMA tensor-map replace operation was matched"),
-        };
-        (
-            "tensormap",
-            vec![
-                "replace".into(),
-                "tile".into(),
-                field.into(),
-                "global".into(),
-                "b1024".into(),
-                width.into(),
-            ],
-            operands,
-        )
-    } else if is_fence {
-        let (semantics, scope) = match operation {
-            TmaOperation::FenceProxyTensorMapAcquireCluster => ("acquire", "cluster"),
-            TmaOperation::FenceProxyTensorMapAcquireCta => ("acquire", "cta"),
-            TmaOperation::FenceProxyTensorMapAcquireGpu => ("acquire", "gpu"),
-            TmaOperation::FenceProxyTensorMapAcquireSystem => ("acquire", "sys"),
-            TmaOperation::FenceProxyTensorMapReleaseCluster => ("release", "cluster"),
-            TmaOperation::FenceProxyTensorMapReleaseCta => ("release", "cta"),
-            TmaOperation::FenceProxyTensorMapReleaseGpu => ("release", "gpu"),
-            TmaOperation::FenceProxyTensorMapReleaseSystem => ("release", "sys"),
-            _ => unreachable!("TMA tensor-map fence operation was matched"),
-        };
-        (
-            "fence",
-            vec![
-                "proxy".into(),
-                "tensormap::generic".into(),
-                semantics.into(),
-                scope.into(),
-            ],
-            if is_acquire_fence {
-                vec![
-                    OperandPattern::Address,
-                    OperandPattern::Exact {
-                        value: "128".into(),
-                    },
-                ]
-            } else {
-                vec![]
-            },
-        )
-    } else {
-        unreachable!("TMA operation category was matched")
-    };
-
-    let minimum_ptx = if blackwell_tma || operation == TmaOperation::ReplaceSwizzleAtomicity {
-        "8.6"
-    } else if is_replace || is_fence {
-        "8.3"
-    } else {
-        "8.0"
-    };
-    let (minimum_sm, targets) = if blackwell_tma {
-        (None, TMA_BLACKWELL_TARGETS)
-    } else if operation == TmaOperation::ReplaceSwizzleAtomicity {
-        (None, BLACKWELL_LDMATRIX_LLVM_TARGETS)
-    } else if is_replace {
-        (None, TENSOR_MAP_REPLACE_TARGETS)
-    } else {
-        (Some("sm_90"), "all")
-    };
-    let memory = if operation == TmaOperation::PrefetchTensorMap || prefetch_coordinates.is_some() {
-        "read"
-    } else if is_replace {
-        "write"
-    } else {
-        "read_write"
-    };
-    let polymorphic_descriptor = operation == TmaOperation::PrefetchTensorMap;
-
-    TmaRecipe {
-        operation,
-        abi_id,
-        id,
-        operation_key,
-        source_record,
-        llvm_symbol,
-        resolved_llvm_symbol: polymorphic_descriptor.then(|| format!("{llvm_symbol}.p0")),
-        selected_address_space: polymorphic_descriptor.then_some(ImportedAddressSpace::Generic),
-        llvm_mechanism: if is_replace {
-            BackendLoweringMechanism::InlinePtx
-        } else {
-            BackendLoweringMechanism::TypedNvvm
-        },
-        rust_arguments,
-        dialect_op_type: op_type,
-        dialect_op_name: op_name,
-        dialect_operands,
-        llvm_arguments,
-        adapter,
-        safe,
-        safe_reason,
-        convergent,
-        minimum_ptx,
-        minimum_sm,
-        targets,
-        memory,
-        ptx_isa_section: if descriptor_control {
-            "Tensor-map descriptor and asynchronous bulk tensor operations"
-        } else {
-            "9.7.9.26.5 Asynchronous bulk tensor copy"
-        },
-        ptx_isa_url: if descriptor_control {
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-map"
-        } else {
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-tensor"
-        },
-        mnemonic,
-        modifiers,
-        operands,
-        summary,
-    }
-}
-
-fn expand_tma_admission(admission: &TmaAdmission) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "TMA runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact TMA admission requires both backend evidence profiles"
-    );
-    ensure!(
-        admission
-            .variants
-            .iter()
-            .map(|variant| variant.operation)
-            .eq(TMA_OPERATIONS),
-        "compact TMA admission must list all {} operations in canonical order",
-        TMA_OPERATIONS.len()
-    );
-
-    let mut records = admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = tma_recipe(variant.operation);
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must keep reserved ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: variant.abi_id.clone(),
-                operation_key: recipe.operation_key.into(),
-                family: "tma".into(),
-                source: None,
-                source_record: Some(recipe.source_record.into()),
-                rust_module: "tma".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments: recipe
-                    .rust_arguments
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                rust_result: "()".into(),
-                safe: recipe.safe,
-                must_use: false,
-                safe_allowlist_reason: recipe.safe_reason.map(Into::into),
-                public_rust_path: format!("cuda_intrinsics::tma::{}", recipe.id),
-                compatibility_rust_paths: vec![format!("cuda_device::tma::{}", recipe.id)],
-                dialect_op_type: recipe.dialect_op_type.into(),
-                dialect_op_name: recipe.dialect_op_name.into(),
-                dialect_operands: recipe
-                    .dialect_operands
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                dialect_results: vec![],
-                llvm_symbol: Some(recipe.llvm_symbol.into()),
-                resolved_llvm_symbol: recipe.resolved_llvm_symbol.clone(),
-                llvm_arguments: recipe
-                    .llvm_arguments
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                llvm_results: vec![],
-                pure: false,
-                memory: recipe.memory.into(),
-                convergent: recipe.convergent,
-                execution_scope: "thread".into(),
-                minimum_ptx: recipe.minimum_ptx.into(),
-                minimum_sm: recipe.minimum_sm.map(Into::into),
-                ptx_result: "()".into(),
-                targets: recipe.targets.into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section: recipe.ptx_isa_section.into(),
-                ptx_isa_url: recipe.ptx_isa_url.into(),
-                lowering: "generated_tma".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: recipe.llvm_mechanism,
-                        evidence_profile: admission.llvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some(recipe.minimum_ptx.into()),
-                        minimum_sm: recipe.minimum_sm.map(Into::into),
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some(recipe.minimum_ptx.into()),
-                        minimum_sm: recipe.minimum_sm.map(Into::into),
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: Some(Tma {
-                    operation: recipe.operation,
-                    reduction: None,
-                    adapter: recipe.adapter,
-                    runtime_validation: admission.runtime_validation,
-                }),
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: recipe.selected_address_space,
-                expected_ptx: InstructionPattern {
-                    mnemonic: recipe.mnemonic.into(),
-                    modifiers: recipe.modifiers,
-                    operands: recipe.operands,
-                },
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect::<Result<Vec<_>>>()?;
-
-    if !admission.reduce_variants.is_empty() {
-        ensure!(
-            admission.reduce_llvm_evidence_profile.is_some(),
-            "compact TMA reduction admission requires reduce_llvm_evidence_profile"
-        );
-        ensure!(
-            admission.reduce_libnvvm_evidence_profile.is_some(),
-            "compact TMA reduction admission requires reduce_libnvvm_evidence_profile"
-        );
-
-        let expected_reductions = tma_reduction_matrix();
-        ensure!(
-            admission.reduce_variants.len() == expected_reductions.len()
-                && admission
-                    .reduce_variants
-                    .iter()
-                    .zip(expected_reductions.iter())
-                    .all(|(variant, expected)| {
-                        variant.operation == expected.operation
-                            && variant.load_mode == expected.load_mode
-                            && variant.dimensions == expected.dimensions
-                    }),
-            "compact TMA reduction admission must list all 64 operations in canonical order"
-        );
-        for variant in &admission.reduce_variants {
-            records.push(expand_tma_reduction_variant(admission, variant)?);
-        }
-    }
-    Ok(records)
-}
-
-fn validate_tma_policy(policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic) -> Result<()> {
-    let tma = policy
-        .tma
-        .as_ref()
-        .with_context(|| format!("{} has no closed TMA contract", policy.id))?;
-    if tma.operation == TmaOperation::Reduce {
-        return validate_tma_reduction_policy(policy, declaration, tma);
-    }
-    ensure!(
-        tma.reduction.is_none(),
-        "{} non-reduction TMA operation carries a reduction contract",
-        policy.id
-    );
-    let recipe = tma_recipe(tma.operation);
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol == recipe.resolved_llvm_symbol
-            && declaration.source_record == recipe.source_record
-            && declaration.llvm_name == recipe.llvm_symbol,
-        "{} TMA identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "tma"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == recipe.rust_arguments
-            && policy.rust_result == "()"
-            && policy.safe == recipe.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.as_deref() == recipe.safe_reason
-            && policy.public_rust_path == format!("cuda_intrinsics::tma::{}", recipe.id)
-            && policy.compatibility_rust_paths == [format!("cuda_device::tma::{}", recipe.id)],
-        "{} TMA Rust API changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == recipe.dialect_operands
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == recipe.llvm_arguments
-            && policy.llvm_results.is_empty()
-            && declaration.arguments == recipe.llvm_arguments
-            && declaration.results.is_empty()
-            && policy.selected_address_space == recipe.selected_address_space
-            && policy.lowering == "generated_tma",
-        "{} TMA carrier or LLVM adapter changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == recipe.memory
-            && policy.convergent == recipe.convergent
-            && policy.execution_scope == "thread"
-            && tma.adapter == recipe.adapter
-            && tma.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} TMA semantics changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == recipe.minimum_sm
-            && policy.targets == recipe.targets
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.ptx_isa_section
-            && policy.ptx_isa_url == recipe.ptx_isa_url
-            && policy.ptx_result == "()"
-            && policy.expected_ptx.mnemonic == recipe.mnemonic
-            && policy.expected_ptx.modifiers == recipe.modifiers
-            && policy.expected_ptx.operands == recipe.operands,
-        "{} TMA target or PTX contract changed",
-        policy.id
-    );
-    let valid_route = |backend, mechanism| {
-        policy.backend_lowerings.iter().any(|route| {
-            route.backend == backend
-                && route.mechanism == mechanism
-                && route.minimum_ptx.as_deref() == Some(recipe.minimum_ptx)
-                && route.minimum_sm.as_deref() == recipe.minimum_sm
-                && !route.evidence_profile.trim().is_empty()
-        })
-    };
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && valid_route(IntrinsicBackend::LlvmNvptx, recipe.llvm_mechanism,)
-            && valid_route(
-                IntrinsicBackend::LibNvvm,
-                BackendLoweringMechanism::InlinePtx,
-            ),
-        "{} TMA backend route changed",
-        policy.id
-    );
-    let expected_properties = tma_imported_properties(tma.operation);
-    ensure!(
-        declaration.properties == expected_properties,
-        "{} imported TMA declaration changed",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "TMA")?;
-    Ok(())
-}
-
-fn validate_tma_reduction_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-    tma: &Tma,
-) -> Result<()> {
-    ensure!(
-        tma.operation == TmaOperation::Reduce,
-        "{} is not a TMA reduction",
-        policy.id
-    );
-    let reduction = tma
-        .reduction
-        .with_context(|| format!("{} has no TMA reduction contract", policy.id))?;
-    let recipe = tma_reduction_recipe(reduction)?;
-    ensure!(
-        policy.id == recipe.id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record.as_str())
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none()
-            && declaration.source_record == recipe.source_record
-            && declaration.llvm_name == recipe.llvm_symbol,
-        "{} TMA reduction identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "tma"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == recipe.rust_arguments
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::tma::{}", recipe.id)
-            && policy.compatibility_rust_paths == [format!("cuda_device::tma::{}", recipe.id)],
-        "{} TMA reduction Rust API changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == recipe.dialect_operands
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == recipe.llvm_arguments
-            && policy.llvm_results.is_empty()
-            && declaration.arguments == recipe.llvm_arguments
-            && declaration.results.is_empty()
-            && declaration.selections.is_empty()
-            && policy.lowering == "generated_tma",
-        "{} TMA reduction carrier or LLVM adapter changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read_write"
-            && policy.convergent
-            && policy.execution_scope == "thread"
-            && tma.adapter == TmaAdapter::ReductionPointersCoordinatesInjectDefaults
-            && tma.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} TMA reduction semantics changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == "8.0"
-            && policy.minimum_sm.as_deref() == Some("sm_90")
-            && policy.targets == "all"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.9.26.5.3 Data Movement and Conversion Instructions: cp.reduce.async.bulk.tensor"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor"
-            && policy.ptx_result == "()"
-            && policy.expected_ptx.mnemonic == "cp"
-            && policy.expected_ptx.modifiers == recipe.modifiers
-            && policy.expected_ptx.operands == recipe.operands,
-        "{} TMA reduction target or PTX contract changed",
-        policy.id
-    );
-    let valid_route = |backend, mechanism| {
-        policy.backend_lowerings.iter().any(|route| {
-            route.backend == backend
-                && route.mechanism == mechanism
-                && route.minimum_ptx.as_deref() == Some("8.0")
-                && route.minimum_sm.as_deref() == Some("sm_90")
-                && !route.evidence_profile.trim().is_empty()
-        })
-    };
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && valid_route(
-                IntrinsicBackend::LlvmNvptx,
-                BackendLoweringMechanism::TypedNvvm,
-            )
-            && valid_route(
-                IntrinsicBackend::LibNvvm,
-                BackendLoweringMechanism::InlinePtx,
-            ),
-        "{} TMA reduction backend route changed",
-        policy.id
-    );
-    ensure!(
-        declaration.properties == tma_reduction_imported_properties(reduction.dimensions as usize),
-        "{} imported TMA reduction declaration changed",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "TMA")?;
-    Ok(())
-}
-
-struct Tcgen05Recipe {
-    operation: Tcgen05Operation,
-    abi_id: &'static str,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    rust_arguments: &'static [&'static str],
-    rust_result: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    dialect_operands: &'static [&'static str],
-    dialect_results: &'static [&'static str],
-    llvm_arguments: &'static [&'static str],
-    llvm_results: &'static [&'static str],
-    imported_classes: &'static [&'static str],
-    imported_properties: &'static [&'static str],
-    adapter: Tcgen05Adapter,
-    source_contract: Tcgen05SourceContract,
-    safe: bool,
-    safe_reason: Option<&'static str>,
-    memory: &'static str,
-    modifiers: Vec<String>,
-    operands: Vec<OperandPattern>,
-    selection_record: Option<&'static str>,
-    selection_asm: Option<&'static str>,
-    summary: &'static str,
-}
-
-fn tcgen05_recipe(operation: Tcgen05Operation) -> Tcgen05Recipe {
-    const EMPTY: &[&str] = &[];
-    const F32_X4: &[&str] = &["f32", "f32", "f32", "f32"];
-    const F32_X32: &[&str] = &["f32"; 32];
-    const BASE_CLASSES: &[&str] = &["SDPatternOperator", "Intrinsic"];
-    const MMA_CLASSES: &[&str] = &[
-        "SDPatternOperator",
-        "Intrinsic",
-        "DefaultAttrsIntrinsic",
-        "DefaultAttrsIntrinsicFlags",
-    ];
-    const LOAD_CLASSES: &[&str] = &["SDPatternOperator", "Intrinsic", "NVVM_TCGEN05_LD"];
-    const CONVERGENT_ARG_MEMORY: &[&str] = &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"];
-    const CONVERGENT_INACCESSIBLE_ARG_MEMORY: &[&str] = &[
-        "IntrConvergent",
-        "IntrInaccessibleMemOrArgMemOnly",
-        "NoCapture<arg0>",
-    ];
-    const CONVERGENT_INACCESSIBLE_MEMORY: &[&str] = &["IntrConvergent", "IntrInaccessibleMemOnly"];
-    const ALLOC_PROPERTIES: &[&str] = &[
-        "IntrConvergent",
-        "IntrInaccessibleMemOrArgMemOnly",
-        "NoCapture<arg0>",
-        "WriteOnly<arg0>",
-    ];
-    const FENCE_PROPERTIES: &[&str] = &["IntrHasSideEffects", "IntrNoMem"];
-    const MMA_WS_PROPERTIES: &[&str] = &[
-        "ImmArg<arg5>",
-        "ImmArg<arg6>",
-        "ImmArg<arg7>",
-        "IntrArgMemOnly",
-        "Range<arg5,0,4>",
-        "Range<arg6,0,4>",
-        "Range<arg7,0,4>",
-        "ReadOnly<arg1>",
-        "WriteOnly<arg0>",
-    ];
-    const MMA_CG1_PROPERTIES: &[&str] = &[
-        "ImmArg<arg6>",
-        "ImmArg<arg7>",
-        "IntrArgMemOnly",
-        "Range<arg6,0,4>",
-        "Range<arg7,0,4>",
-        "WriteOnly<arg0>",
-    ];
-    const LOAD_PROPERTIES: &[&str] = &[
-        "ImmArg<arg1>",
-        "IntrArgMemOnly",
-        "IntrConvergent",
-        "NoCapture<arg0>",
-    ];
-
-    let (
-        abi_id,
-        id,
-        operation_key,
-        source_record,
-        llvm_symbol,
-        dialect_op_type,
-        dialect_op_name,
-        adapter,
-        source_contract,
-    ) = match operation {
-        Tcgen05Operation::Alloc => (
-            "i0343",
-            "tcgen05_alloc",
-            "tcgen05.alloc.cg1",
-            "int_nvvm_tcgen05_alloc_shared_cg1",
-            "llvm.nvvm.tcgen05.alloc.shared.cg1",
-            "Tcgen05AllocOp",
-            "nvvm.tcgen05_alloc",
-            Tcgen05Adapter::SharedPointerColumnsToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::Dealloc => (
-            "i0344",
-            "tcgen05_dealloc",
-            "tcgen05.dealloc.cg1",
-            "int_nvvm_tcgen05_dealloc_cg1",
-            "llvm.nvvm.tcgen05.dealloc.cg1",
-            "Tcgen05DeallocOp",
-            "nvvm.tcgen05_dealloc",
-            Tcgen05Adapter::TmemAddressColumnsToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::RelinquishAllocPermit => (
-            "i0345",
-            "tcgen05_relinquish_alloc_permit",
-            "tcgen05.relinquish_alloc_permit.cg1",
-            "int_nvvm_tcgen05_relinq_alloc_permit_cg1",
-            "llvm.nvvm.tcgen05.relinq.alloc.permit.cg1",
-            "Tcgen05RelinquishAllocPermitOp",
-            "nvvm.tcgen05_relinquish_alloc_permit",
-            Tcgen05Adapter::NoOperands,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::FenceBeforeThreadSync => (
-            "i0346",
-            "tcgen05_fence_before_thread_sync",
-            "tcgen05.fence.before_thread_sync",
-            "int_nvvm_tcgen05_fence_before_thread_sync",
-            "llvm.nvvm.tcgen05.fence.before.thread.sync",
-            "Tcgen05FenceBeforeThreadSyncOp",
-            "nvvm.tcgen05_fence_before_thread_sync",
-            Tcgen05Adapter::NoOperands,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::FenceAfterThreadSync => (
-            "i0347",
-            "tcgen05_fence_after_thread_sync",
-            "tcgen05.fence.after.thread.sync",
-            "int_nvvm_tcgen05_fence_after_thread_sync",
-            "llvm.nvvm.tcgen05.fence.after.thread.sync",
-            "Tcgen05FenceAfterThreadSyncOp",
-            "nvvm.tcgen05_fence_after_thread_sync",
-            Tcgen05Adapter::NoOperands,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::Commit => (
-            "i0348",
-            "tcgen05_commit",
-            "tcgen05.commit.cg1",
-            "int_nvvm_tcgen05_commit_cg1",
-            "llvm.nvvm.tcgen05.commit.cg1",
-            "Tcgen05CommitOp",
-            "nvvm.tcgen05_commit",
-            Tcgen05Adapter::BarrierPointerToVoid,
-            Tcgen05SourceContract::TablegenSelectionChangesPtx,
-        ),
-        Tcgen05Operation::CommitSharedCluster => (
-            "i0349",
-            "tcgen05_commit_shared_cluster",
-            "tcgen05.commit.shared_cluster.cg1",
-            "int_nvvm_tcgen05_commit_shared_cg1",
-            "llvm.nvvm.tcgen05.commit.shared.cg1",
-            "Tcgen05CommitSharedClusterOp",
-            "nvvm.tcgen05_commit_shared_cluster",
-            Tcgen05Adapter::BarrierPointerToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::MmaWsF16 => (
-            "i0350",
-            "tcgen05_mma_ws_f16",
-            "tcgen05.mma.ws.f16.cg1",
-            "int_nvvm_tcgen05_mma_ws_tensor",
-            "llvm.nvvm.tcgen05.mma.ws.tensor",
-            "Tcgen05MmaWsF16Op",
-            "nvvm.tcgen05_mma_ws_f16",
-            Tcgen05Adapter::MmaWsDropLegacyADescriptor,
-            Tcgen05SourceContract::TablegenSelectionChangesPtx,
-        ),
-        Tcgen05Operation::MmaF16 => (
-            "i0351",
-            "tcgen05_mma_f16",
-            "tcgen05.mma.f16.cg1",
-            "int_nvvm_tcgen05_mma_shared_disable_output_lane_cg1",
-            "llvm.nvvm.tcgen05.mma.shared.disable_output_lane.cg1",
-            "Tcgen05MmaF16Op",
-            "nvvm.tcgen05_mma_f16",
-            Tcgen05Adapter::MmaInjectZeroDisableLanes,
-            Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
-        ),
-        Tcgen05Operation::MmaWsBf16 => (
-            "i0352",
-            "tcgen05_mma_ws_bf16",
-            "tcgen05.mma.ws.bf16.cg1",
-            "int_nvvm_tcgen05_mma_ws_tensor",
-            "llvm.nvvm.tcgen05.mma.ws.tensor",
-            "Tcgen05MmaWsBf16Op",
-            "nvvm.tcgen05_mma_ws_bf16",
-            Tcgen05Adapter::MmaWsDropLegacyADescriptor,
-            Tcgen05SourceContract::TablegenSelectionChangesPtx,
-        ),
-        Tcgen05Operation::MmaWsTf32 => (
-            "i0353",
-            "tcgen05_mma_ws_tf32",
-            "tcgen05.mma.ws.tf32.cg1",
-            "int_nvvm_tcgen05_mma_ws_tensor",
-            "llvm.nvvm.tcgen05.mma.ws.tensor",
-            "Tcgen05MmaWsTf32Op",
-            "nvvm.tcgen05_mma_ws_tf32",
-            Tcgen05Adapter::MmaWsDropLegacyADescriptor,
-            Tcgen05SourceContract::TablegenSelectionChangesPtx,
-        ),
-        Tcgen05Operation::CpSmemToTmem => (
-            "i0354",
-            "tcgen05_cp_smem_to_tmem",
-            "tcgen05.cp.128x256b.cg1",
-            "int_nvvm_tcgen05_cp_128x256b_cg1",
-            "llvm.nvvm.tcgen05.cp.128x256b.cg1",
-            "Tcgen05CpSmemToTmemOp",
-            "nvvm.tcgen05_cp_smem_to_tmem",
-            Tcgen05Adapter::TmemDescriptorToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::Ld16x256bX8Pure => (
-            "i0355",
-            "tcgen05_ld_16x256b_x8_pure",
-            "tcgen05.ld.16x256b.x8",
-            "int_nvvm_tcgen05_ld_16x256b_x8",
-            "llvm.nvvm.tcgen05.ld.16x256b.x8",
-            "Tcgen05Ld16x256bX8PureOp",
-            "nvvm.tcgen05_ld_16x256b_x8_pure",
-            Tcgen05Adapter::TmemToF32x32,
-            Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
-        ),
-        Tcgen05Operation::Ld16x256bPure => (
-            "i0356",
-            "tcgen05_ld_16x256b_pure",
-            "tcgen05.ld.16x256b.x1",
-            "int_nvvm_tcgen05_ld_16x256b_x1",
-            "llvm.nvvm.tcgen05.ld.16x256b.x1",
-            "Tcgen05Ld16x256bPureOp",
-            "nvvm.tcgen05_ld_16x256b_pure",
-            Tcgen05Adapter::TmemToF32x4,
-            Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
-        ),
-        Tcgen05Operation::LoadWait => (
-            "i0357",
-            "tcgen05_load_wait",
-            "tcgen05.wait.ld",
-            "int_nvvm_tcgen05_wait_ld",
-            "llvm.nvvm.tcgen05.wait.ld",
-            "Tcgen05LoadWaitOp",
-            "nvvm.tcgen05_load_wait",
-            Tcgen05Adapter::NoOperands,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::StoreWait => (
-            "i0358",
-            "tcgen05_store_wait",
-            "tcgen05.wait.st",
-            "int_nvvm_tcgen05_wait_st",
-            "llvm.nvvm.tcgen05.wait.st",
-            "Tcgen05StoreWaitOp",
-            "nvvm.tcgen05_store_wait",
-            Tcgen05Adapter::NoOperands,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::AllocCg2 => (
-            "i0359",
-            "tcgen05_alloc_cg2",
-            "tcgen05.alloc.cg2",
-            "int_nvvm_tcgen05_alloc_shared_cg2",
-            "llvm.nvvm.tcgen05.alloc.shared.cg2",
-            "Tcgen05AllocCg2Op",
-            "nvvm.tcgen05_alloc_cg2",
-            Tcgen05Adapter::SharedPointerColumnsToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::DeallocCg2 => (
-            "i0360",
-            "tcgen05_dealloc_cg2",
-            "tcgen05.dealloc.cg2",
-            "int_nvvm_tcgen05_dealloc_cg2",
-            "llvm.nvvm.tcgen05.dealloc.cg2",
-            "Tcgen05DeallocCg2Op",
-            "nvvm.tcgen05_dealloc_cg2",
-            Tcgen05Adapter::TmemAddressColumnsToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::RelinquishAllocPermitCg2 => (
-            "i0361",
-            "tcgen05_relinquish_alloc_permit_cg2",
-            "tcgen05.relinquish_alloc_permit.cg2",
-            "int_nvvm_tcgen05_relinq_alloc_permit_cg2",
-            "llvm.nvvm.tcgen05.relinq.alloc.permit.cg2",
-            "Tcgen05RelinquishAllocPermitCg2Op",
-            "nvvm.tcgen05_relinquish_alloc_permit_cg2",
-            Tcgen05Adapter::NoOperands,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::MmaF16Cg2 => (
-            "i0362",
-            "tcgen05_mma_f16_cg2",
-            "tcgen05.mma.f16.cg2",
-            "int_nvvm_tcgen05_mma_shared_disable_output_lane_cg2",
-            "llvm.nvvm.tcgen05.mma.shared.disable_output_lane.cg2",
-            "Tcgen05MmaF16Cg2Op",
-            "nvvm.tcgen05_mma_f16_cg2",
-            Tcgen05Adapter::MmaInjectZeroDisableLanes,
-            Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
-        ),
-        Tcgen05Operation::CommitCg2 => (
-            "i0363",
-            "tcgen05_commit_cg2",
-            "tcgen05.commit.cg2",
-            "int_nvvm_tcgen05_commit_cg2",
-            "llvm.nvvm.tcgen05.commit.cg2",
-            "Tcgen05CommitCg2Op",
-            "nvvm.tcgen05_commit_cg2",
-            Tcgen05Adapter::BarrierPointerToVoid,
-            Tcgen05SourceContract::TablegenSelectionChangesPtx,
-        ),
-        Tcgen05Operation::CommitSharedClusterCg2 => (
-            "i0364",
-            "tcgen05_commit_shared_cluster_cg2",
-            "tcgen05.commit.shared_cluster.cg2",
-            "int_nvvm_tcgen05_commit_shared_cg2",
-            "llvm.nvvm.tcgen05.commit.shared.cg2",
-            "Tcgen05CommitSharedClusterCg2Op",
-            "nvvm.tcgen05_commit_shared_cluster_cg2",
-            Tcgen05Adapter::BarrierPointerToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::CommitMulticastCg2 => (
-            "i0365",
-            "tcgen05_commit_multicast_cg2",
-            "tcgen05.commit.multicast.cg2",
-            "int_nvvm_tcgen05_commit_mc_shared_cg2",
-            "llvm.nvvm.tcgen05.commit.mc.shared.cg2",
-            "Tcgen05CommitMulticastCg2Op",
-            "nvvm.tcgen05_commit_multicast_cg2",
-            Tcgen05Adapter::BarrierPointerMaskToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::CpSmemToTmemCg2 => (
-            "i0366",
-            "tcgen05_cp_smem_to_tmem_cg2",
-            "tcgen05.cp.128x256b.cg2",
-            "int_nvvm_tcgen05_cp_128x256b_cg2",
-            "llvm.nvvm.tcgen05.cp.128x256b.cg2",
-            "Tcgen05CpSmemToTmemCg2Op",
-            "nvvm.tcgen05_cp_smem_to_tmem_cg2",
-            Tcgen05Adapter::TmemDescriptorToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::CommitMulticast => (
-            "i0760",
-            "tcgen05_commit_multicast",
-            "tcgen05.commit.multicast.cg1",
-            "int_nvvm_tcgen05_commit_mc_shared_cg1",
-            "llvm.nvvm.tcgen05.commit.mc.shared.cg1",
-            "Tcgen05CommitMulticastOp",
-            "nvvm.tcgen05_commit_multicast",
-            Tcgen05Adapter::BarrierPointerMaskToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::ShiftDown => (
-            "i0761",
-            "tcgen05_shift_down",
-            "tcgen05.shift.down.cg1",
-            "int_nvvm_tcgen05_shift_down_cg1",
-            "llvm.nvvm.tcgen05.shift.down.cg1",
-            "Tcgen05ShiftDownOp",
-            "nvvm.tcgen05_shift_down",
-            Tcgen05Adapter::TmemAddressToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::ShiftDownCg2 => (
-            "i0762",
-            "tcgen05_shift_down_cg2",
-            "tcgen05.shift.down.cg2",
-            "int_nvvm_tcgen05_shift_down_cg2",
-            "llvm.nvvm.tcgen05.shift.down.cg2",
-            "Tcgen05ShiftDownCg2Op",
-            "nvvm.tcgen05_shift_down_cg2",
-            Tcgen05Adapter::TmemAddressToVoid,
-            Tcgen05SourceContract::ExactTablegenSelection,
-        ),
-        Tcgen05Operation::Ld | Tcgen05Operation::St | Tcgen05Operation::Mma => {
-            unreachable!("tcgen05 load/store variants use their compact recipes")
-        }
-    };
-
-    let cg2 = matches!(
-        operation,
-        Tcgen05Operation::AllocCg2
-            | Tcgen05Operation::DeallocCg2
-            | Tcgen05Operation::RelinquishAllocPermitCg2
-            | Tcgen05Operation::MmaF16Cg2
-            | Tcgen05Operation::CommitCg2
-            | Tcgen05Operation::CommitSharedClusterCg2
-            | Tcgen05Operation::CommitMulticastCg2
-            | Tcgen05Operation::CpSmemToTmemCg2
-            | Tcgen05Operation::ShiftDownCg2
-    );
-    let group = if cg2 { "cta_group::2" } else { "cta_group::1" };
-    let (
-        rust_arguments,
-        rust_result,
-        dialect_operands,
-        dialect_results,
-        llvm_arguments,
-        llvm_results,
-        imported_classes,
-        imported_properties,
-        safe,
-        safe_reason,
-        memory,
-        modifiers,
-        operands,
-        selection_record,
-        selection_asm,
-        summary,
-    ) = match operation {
-        Tcgen05Operation::Alloc | Tcgen05Operation::AllocCg2 => (
-            &["*mut u32", "u32"] as &[_],
-            "()",
-            &["ptr", "i32"] as &[_],
-            EMPTY,
-            &["shared_ptr", "i32"] as &[_],
-            EMPTY,
-            BASE_CLASSES,
-            ALLOC_PROPERTIES,
-            false,
-            None,
-            "write",
-            vec![
-                "alloc".into(),
-                group.into(),
-                "sync".into(),
-                "aligned".into(),
-                "shared::cta".into(),
-                "b32".into(),
-            ],
-            vec![OperandPattern::Address, OperandPattern::Register],
-            Some(if cg2 {
-                "TCGEN05_ALLOC_S64_CG2"
-            } else {
-                "TCGEN05_ALLOC_S64_CG1"
-            }),
-            Some(if cg2 {
-                "tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 \t[$dst], $ncols;"
-            } else {
-                "tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 \t[$dst], $ncols;"
-            }),
-            "Allocates tensor-memory columns and writes their address to shared memory.",
-        ),
-        Tcgen05Operation::Dealloc | Tcgen05Operation::DeallocCg2 => (
-            &["u32", "u32"] as &[_],
-            "()",
-            &["i32", "i32"] as &[_],
-            EMPTY,
-            &["tmem_ptr", "i32"] as &[_],
-            EMPTY,
-            BASE_CLASSES,
-            CONVERGENT_ARG_MEMORY,
-            false,
-            None,
-            "read_write",
-            vec![
-                "dealloc".into(),
-                group.into(),
-                "sync".into(),
-                "aligned".into(),
-                "b32".into(),
-            ],
-            vec![OperandPattern::Register, OperandPattern::Register],
-            Some(if cg2 {
-                "TCGEN05_DEALLOC_CG2"
-            } else {
-                "TCGEN05_DEALLOC_CG1"
-            }),
-            Some(if cg2 {
-                "tcgen05.dealloc.cta_group::2.sync.aligned.b32 \t$tmem_addr, $ncols;"
-            } else {
-                "tcgen05.dealloc.cta_group::1.sync.aligned.b32 \t$tmem_addr, $ncols;"
-            }),
-            "Releases tensor-memory columns allocated to the CTA group.",
-        ),
-        Tcgen05Operation::RelinquishAllocPermit | Tcgen05Operation::RelinquishAllocPermitCg2 => (
-            EMPTY,
-            "()",
-            EMPTY,
-            EMPTY,
-            EMPTY,
-            EMPTY,
-            BASE_CLASSES,
-            CONVERGENT_INACCESSIBLE_MEMORY,
-            true,
-            Some(
-                "The operation has no Rust memory operand and only releases this CTA group's allocation permit.",
-            ),
-            "read_write",
-            vec![
-                "relinquish_alloc_permit".into(),
-                group.into(),
-                "sync".into(),
-                "aligned".into(),
-            ],
-            vec![],
-            Some(if cg2 {
-                "TCGEN05_RELINQ_CG2"
-            } else {
-                "TCGEN05_RELINQ_CG1"
-            }),
-            Some(if cg2 {
-                "tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;"
-            } else {
-                "tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;"
-            }),
-            "Releases the CTA group's tensor-memory allocation permit.",
-        ),
-        Tcgen05Operation::FenceBeforeThreadSync | Tcgen05Operation::FenceAfterThreadSync => {
-            let before = operation == Tcgen05Operation::FenceBeforeThreadSync;
-            (
-                EMPTY,
-                "()",
-                EMPTY,
-                EMPTY,
-                EMPTY,
-                EMPTY,
-                BASE_CLASSES,
-                FENCE_PROPERTIES,
-                true,
-                Some("The operation only orders the calling thread's tcgen05 accesses."),
-                "none",
-                vec![if before {
-                    "fence::before_thread_sync".into()
-                } else {
-                    "fence::after_thread_sync".into()
-                }],
-                vec![],
-                Some(if before {
-                    "tcgen05_fence_before_thread_sync"
-                } else {
-                    "tcgen05_fence_after_thread_sync"
-                }),
-                Some(if before {
-                    "tcgen05.fence::before_thread_sync;"
-                } else {
-                    "tcgen05.fence::after_thread_sync;"
-                }),
-                if before {
-                    "Orders prior tcgen05 accesses before thread synchronization."
-                } else {
-                    "Orders later tcgen05 accesses after thread synchronization."
-                },
-            )
-        }
-        Tcgen05Operation::Commit
-        | Tcgen05Operation::CommitCg2
-        | Tcgen05Operation::CommitSharedCluster
-        | Tcgen05Operation::CommitSharedClusterCg2 => {
-            let shared = matches!(
-                operation,
-                Tcgen05Operation::CommitSharedCluster | Tcgen05Operation::CommitSharedClusterCg2
-            );
-            let llvm_args = if shared {
-                &["shared_ptr"] as &[_]
-            } else {
-                &["ptr"] as &[_]
-            };
-            let record = match (cg2, shared) {
-                (false, false) => "TCGEN05_COMMIT_CG1",
-                (true, false) => "TCGEN05_COMMIT_CG2",
-                (false, true) => "TCGEN05_COMMIT_S64_CG1",
-                (true, true) => "TCGEN05_COMMIT_S64_CG2",
-            };
-            let asm = match cg2 {
-                false => {
-                    "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];"
-                }
-                true => {
-                    "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];"
-                }
-            };
-            let mut modifiers = vec![
-                "commit".into(),
-                group.into(),
-                "mbarrier::arrive::one".into(),
-            ];
-            if shared {
-                modifiers.push("shared::cluster".into());
-            }
-            modifiers.push("b64".into());
-            (
-                &["*mut u64"] as &[_],
-                "()",
-                &["ptr"] as &[_],
-                EMPTY,
-                llvm_args,
-                EMPTY,
-                BASE_CLASSES,
-                CONVERGENT_INACCESSIBLE_ARG_MEMORY,
-                false,
-                None,
-                "read_write",
-                modifiers,
-                vec![OperandPattern::Address],
-                Some(record),
-                Some(asm),
-                if shared {
-                    "Commits tcgen05 completion to a cluster-shared mbarrier."
-                } else {
-                    "Commits tcgen05 completion to an mbarrier."
-                },
-            )
-        }
-        Tcgen05Operation::MmaWsF16 | Tcgen05Operation::MmaWsBf16 | Tcgen05Operation::MmaWsTf32 => {
-            let kind = if operation == Tcgen05Operation::MmaWsTf32 {
-                "kind::tf32"
-            } else {
-                "kind::f16"
-            };
-            (
-                &["u32", "u32", "u64", "u64", "u32", "bool"] as &[_],
-                "()",
-                &["i32", "i32", "i64", "i64", "i32", "i1"] as &[_],
-                EMPTY,
-                &[
-                    "tmem_ptr", "tmem_ptr", "i64", "i32", "i1", "i32", "i32", "i32",
-                ] as &[_],
-                EMPTY,
-                MMA_CLASSES,
-                MMA_WS_PROPERTIES,
-                false,
-                None,
-                "read_write",
-                vec![
-                    "mma".into(),
-                    "ws".into(),
-                    "cta_group::1".into(),
-                    kind.into(),
-                ],
-                vec![
-                    OperandPattern::Address,
-                    OperandPattern::Address,
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                    OperandPattern::Exact {
-                        value: "%enable_pred".into(),
-                    },
-                ],
-                None,
-                None,
-                match operation {
-                    Tcgen05Operation::MmaWsF16 => "Issues warp-specialized f16 tensor-memory MMA.",
-                    Tcgen05Operation::MmaWsBf16 => {
-                        "Issues warp-specialized bf16 tensor-memory MMA using the f16 instruction class."
-                    }
-                    _ => "Issues warp-specialized tf32 tensor-memory MMA.",
-                },
-            )
-        }
-        Tcgen05Operation::MmaF16 | Tcgen05Operation::MmaF16Cg2 => (
-            &["u32", "u64", "u64", "u32", "bool"] as &[_],
-            "()",
-            &["i32", "i64", "i64", "i32", "i1"] as &[_],
-            EMPTY,
-            if cg2 {
-                &["tmem_ptr", "i64", "i64", "i32", "i1", "v8i32", "i32", "i32"] as &[_]
-            } else {
-                &["tmem_ptr", "i64", "i64", "i32", "i1", "v4i32", "i32", "i32"] as &[_]
-            },
-            EMPTY,
-            MMA_CLASSES,
-            MMA_CG1_PROPERTIES,
-            false,
-            None,
-            "write",
-            vec!["mma".into(), group.into(), "kind::f16".into()],
-            vec![
-                OperandPattern::Address,
-                OperandPattern::Register,
-                OperandPattern::Register,
-                OperandPattern::Register,
-                OperandPattern::Exact {
-                    value: if cg2 {
-                        "{%z, %z, %z, %z, %z, %z, %z, %z}"
-                    } else {
-                        "{%z, %z, %z, %z}"
-                    }
-                    .into(),
-                },
-                OperandPattern::Exact {
-                    value: "%enable_pred".into(),
-                },
-            ],
-            None,
-            None,
-            "Issues f16 tensor-memory MMA with zeroed disable-output-lane controls.",
-        ),
-        Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2 => (
-            &["u32", "u64"] as &[_],
-            "()",
-            &["i32", "i64"] as &[_],
-            EMPTY,
-            &["tmem_ptr", "i64"] as &[_],
-            EMPTY,
-            BASE_CLASSES,
-            CONVERGENT_INACCESSIBLE_ARG_MEMORY,
-            false,
-            None,
-            "read_write",
-            vec!["cp".into(), group.into(), "128x256b".into()],
-            vec![OperandPattern::Address, OperandPattern::Register],
-            Some(if cg2 {
-                "TCGEN05_CP_128x256b_cg2"
-            } else {
-                "TCGEN05_CP_128x256b_cg1"
-            }),
-            Some(if cg2 {
-                "tcgen05.cp.cta_group::2.128x256b \t[$tmem_addr], $sdesc;"
-            } else {
-                "tcgen05.cp.cta_group::1.128x256b \t[$tmem_addr], $sdesc;"
-            }),
-            "Copies one 128x256-bit tile from shared memory to tensor memory.",
-        ),
-        Tcgen05Operation::Ld16x256bX8Pure | Tcgen05Operation::Ld16x256bPure => {
-            let x8 = operation == Tcgen05Operation::Ld16x256bX8Pure;
-            (
-                &["u32"] as &[_],
-                if x8 { "[f32; 32]" } else { "[f32; 4]" },
-                &["i32"] as &[_],
-                if x8 { F32_X32 } else { F32_X4 },
-                &["tmem_ptr", "i1"] as &[_],
-                if x8 {
-                    &["v32i32"] as &[_]
-                } else {
-                    &["v4i32"] as &[_]
-                },
-                LOAD_CLASSES,
-                LOAD_PROPERTIES,
-                false,
-                None,
-                "read",
-                vec![
-                    "ld".into(),
-                    "sync".into(),
-                    "aligned".into(),
-                    "16x256b".into(),
-                    if x8 { "x8".into() } else { "x1".into() },
-                    "b32".into(),
-                ],
-                vec![
-                    OperandPattern::RegisterList {
-                        length: if x8 { 32 } else { 4 },
-                    },
-                    OperandPattern::Address,
-                ],
-                None,
-                None,
-                if x8 {
-                    "Loads 32 f32 register values from tensor memory."
-                } else {
-                    "Loads four f32 register values from tensor memory."
-                },
-            )
-        }
-        Tcgen05Operation::LoadWait | Tcgen05Operation::StoreWait => {
-            let load = operation == Tcgen05Operation::LoadWait;
-            (
-                EMPTY,
-                "()",
-                EMPTY,
-                EMPTY,
-                EMPTY,
-                EMPTY,
-                BASE_CLASSES,
-                CONVERGENT_INACCESSIBLE_MEMORY,
-                true,
-                Some("The operation only waits for the calling thread's prior tcgen05 access."),
-                "read_write",
-                vec![
-                    if load {
-                        "wait::ld".into()
-                    } else {
-                        "wait::st".into()
-                    },
-                    "sync".into(),
-                    "aligned".into(),
-                ],
-                vec![],
-                Some(if load {
-                    "tcgen05_wait_ld"
-                } else {
-                    "tcgen05_wait_st"
-                }),
-                Some(if load {
-                    "tcgen05.wait::ld.sync.aligned;"
-                } else {
-                    "tcgen05.wait::st.sync.aligned;"
-                }),
-                if load {
-                    "Waits for prior tensor-memory loads to complete."
-                } else {
-                    "Waits for prior tensor-memory stores to complete."
-                },
-            )
-        }
-        Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2 => (
-            &["*mut u64", "u16"] as &[_],
-            "()",
-            &["ptr", "i16"] as &[_],
-            EMPTY,
-            &["shared_ptr", "i16"] as &[_],
-            EMPTY,
-            BASE_CLASSES,
-            CONVERGENT_INACCESSIBLE_ARG_MEMORY,
-            false,
-            None,
-            "read_write",
-            vec![
-                "commit".into(),
-                group.into(),
-                "mbarrier::arrive::one".into(),
-                "shared::cluster".into(),
-                "multicast::cluster".into(),
-                "b64".into(),
-            ],
-            vec![OperandPattern::Address, OperandPattern::Register],
-            Some(if cg2 {
-                "TCGEN05_COMMIT_S64_CG2_MC"
-            } else {
-                "TCGEN05_COMMIT_S64_CG1_MC"
-            }),
-            Some(if cg2 {
-                "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;"
-            } else {
-                "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;"
-            }),
-            "Commits tcgen05 completion to the selected cluster mbarriers.",
-        ),
-        Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2 => (
-            &["u32"] as &[_],
-            "()",
-            &["i32"] as &[_],
-            EMPTY,
-            &["tmem_ptr"] as &[_],
-            EMPTY,
-            BASE_CLASSES,
-            CONVERGENT_ARG_MEMORY,
-            false,
-            None,
-            "read_write",
-            vec!["shift".into(), group.into(), "down".into()],
-            vec![OperandPattern::Address],
-            Some(if cg2 {
-                "TCGEN05_SHIFT_CG2"
-            } else {
-                "TCGEN05_SHIFT_CG1"
-            }),
-            Some(if cg2 {
-                "tcgen05.shift.cta_group::2.down \t[$tmem_addr];"
-            } else {
-                "tcgen05.shift.cta_group::1.down \t[$tmem_addr];"
-            }),
-            "Shifts tensor-memory rows down by one row.",
-        ),
-        Tcgen05Operation::Ld | Tcgen05Operation::St | Tcgen05Operation::Mma => {
-            unreachable!("tcgen05 load/store variants use their compact recipes")
-        }
-    };
-
-    Tcgen05Recipe {
-        operation,
-        abi_id,
-        id,
-        operation_key,
-        source_record,
-        llvm_symbol,
-        rust_arguments,
-        rust_result,
-        dialect_op_type,
-        dialect_op_name,
-        dialect_operands,
-        dialect_results,
-        llvm_arguments,
-        llvm_results,
-        imported_classes,
-        imported_properties,
-        adapter,
-        source_contract,
-        safe,
-        safe_reason,
-        memory,
-        modifiers,
-        operands,
-        selection_record,
-        selection_asm,
-        summary,
-    }
-}
-
-fn tcgen05_mma_form_name(form: Tcgen05MmaForm) -> &'static str {
-    match form {
-        Tcgen05MmaForm::Shared => "shared",
-        Tcgen05MmaForm::Tensor => "tensor",
-        Tcgen05MmaForm::TensorAshift => "tensor_ashift",
-        Tcgen05MmaForm::SpShared => "sp_shared",
-        Tcgen05MmaForm::SpTensor => "sp_tensor",
-        Tcgen05MmaForm::SpTensorAshift => "sp_tensor_ashift",
-        Tcgen05MmaForm::WsShared => "ws_shared",
-        Tcgen05MmaForm::WsSharedZeroColMask => "ws_shared_zero_col_mask",
-        Tcgen05MmaForm::WsSpShared => "ws_sp_shared",
-        Tcgen05MmaForm::WsSpSharedZeroColMask => "ws_sp_shared_zero_col_mask",
-        Tcgen05MmaForm::WsSpTensor => "ws_sp_tensor",
-        Tcgen05MmaForm::WsSpTensorZeroColMask => "ws_sp_tensor_zero_col_mask",
-        Tcgen05MmaForm::WsTensor => "ws_tensor",
-        Tcgen05MmaForm::WsTensorZeroColMask => "ws_tensor_zero_col_mask",
-    }
-}
-
-fn tcgen05_mma_alias_name(alias: Tcgen05MmaAlias) -> &'static str {
-    match alias {
-        Tcgen05MmaAlias::E4m3 => "e4m3",
-        Tcgen05MmaAlias::E5m2 => "e5m2",
-        Tcgen05MmaAlias::E2m3 => "e2m3",
-        Tcgen05MmaAlias::E3m2 => "e3m2",
-        Tcgen05MmaAlias::E2m1 => "e2m1",
-    }
-}
-
-fn tcgen05_mma_kind_name(kind: Tcgen05MmaKind) -> &'static str {
-    match kind {
-        Tcgen05MmaKind::F16 => "f16",
-        Tcgen05MmaKind::Tf32 => "tf32",
-        Tcgen05MmaKind::F8f6f4 => "f8f6f4",
-        Tcgen05MmaKind::I8 => "i8",
-    }
-}
-
-fn tcgen05_mma_b_usage_name(usage: Tcgen05MmaBUsage) -> &'static str {
-    match usage {
-        Tcgen05MmaBUsage::Discard => "discard",
-        Tcgen05MmaBUsage::Fill => "fill",
-        Tcgen05MmaBUsage::Use => "use",
-        Tcgen05MmaBUsage::LastUse => "lastuse",
-    }
-}
-
-fn tcgen05_mma_is_ws(form: Tcgen05MmaForm) -> bool {
-    matches!(
-        form,
-        Tcgen05MmaForm::WsShared
-            | Tcgen05MmaForm::WsSharedZeroColMask
-            | Tcgen05MmaForm::WsSpShared
-            | Tcgen05MmaForm::WsSpSharedZeroColMask
-            | Tcgen05MmaForm::WsSpTensor
-            | Tcgen05MmaForm::WsSpTensorZeroColMask
-            | Tcgen05MmaForm::WsTensor
-            | Tcgen05MmaForm::WsTensorZeroColMask
-    )
-}
-
-fn tcgen05_mma_is_sparse(form: Tcgen05MmaForm) -> bool {
-    matches!(
-        form,
-        Tcgen05MmaForm::SpShared
-            | Tcgen05MmaForm::SpTensor
-            | Tcgen05MmaForm::SpTensorAshift
-            | Tcgen05MmaForm::WsSpShared
-            | Tcgen05MmaForm::WsSpSharedZeroColMask
-            | Tcgen05MmaForm::WsSpTensor
-            | Tcgen05MmaForm::WsSpTensorZeroColMask
-    )
-}
-
-fn tcgen05_mma_is_tensor_a(form: Tcgen05MmaForm) -> bool {
-    matches!(
-        form,
-        Tcgen05MmaForm::Tensor
-            | Tcgen05MmaForm::TensorAshift
-            | Tcgen05MmaForm::SpTensor
-            | Tcgen05MmaForm::SpTensorAshift
-            | Tcgen05MmaForm::WsSpTensor
-            | Tcgen05MmaForm::WsSpTensorZeroColMask
-            | Tcgen05MmaForm::WsTensor
-            | Tcgen05MmaForm::WsTensorZeroColMask
-    )
-}
-
-fn tcgen05_mma_is_ashift(form: Tcgen05MmaForm) -> bool {
-    matches!(
-        form,
-        Tcgen05MmaForm::TensorAshift | Tcgen05MmaForm::SpTensorAshift
-    )
-}
-
-fn tcgen05_mma_has_zero_col_mask(form: Tcgen05MmaForm) -> bool {
-    matches!(
-        form,
-        Tcgen05MmaForm::WsSharedZeroColMask
-            | Tcgen05MmaForm::WsSpSharedZeroColMask
-            | Tcgen05MmaForm::WsSpTensorZeroColMask
-            | Tcgen05MmaForm::WsTensorZeroColMask
-    )
-}
-
-fn tcgen05_mma_source_record(form: Tcgen05MmaForm) -> String {
-    format!("int_nvvm_tcgen05_mma_{}", tcgen05_mma_form_name(form))
-}
-
-fn tcgen05_mma_llvm_symbol(form: Tcgen05MmaForm) -> String {
-    let suffix = match form {
-        Tcgen05MmaForm::Shared => "shared",
-        Tcgen05MmaForm::Tensor => "tensor",
-        Tcgen05MmaForm::TensorAshift => "tensor.ashift",
-        Tcgen05MmaForm::SpShared => "sp.shared",
-        Tcgen05MmaForm::SpTensor => "sp.tensor",
-        Tcgen05MmaForm::SpTensorAshift => "sp.tensor.ashift",
-        Tcgen05MmaForm::WsShared => "ws.shared",
-        Tcgen05MmaForm::WsSharedZeroColMask => "ws.shared.zero_col_mask",
-        Tcgen05MmaForm::WsSpShared => "ws.sp.shared",
-        Tcgen05MmaForm::WsSpSharedZeroColMask => "ws.sp.shared.zero_col_mask",
-        Tcgen05MmaForm::WsSpTensor => "ws.sp.tensor",
-        Tcgen05MmaForm::WsSpTensorZeroColMask => "ws.sp.tensor.zero_col_mask",
-        Tcgen05MmaForm::WsTensor => "ws.tensor",
-        Tcgen05MmaForm::WsTensorZeroColMask => "ws.tensor.zero_col_mask",
-    };
-    format!("llvm.nvvm.tcgen05.mma.{suffix}")
-}
-
-fn tcgen05_mma_llvm_arguments(form: Tcgen05MmaForm) -> Vec<String> {
-    let mut arguments = vec![
-        "tmem_ptr".into(),
-        if tcgen05_mma_is_tensor_a(form) {
-            "tmem_ptr".into()
-        } else {
-            "i64".into()
-        },
-        "i64".into(),
-        "i32".into(),
-        "i1".into(),
-    ];
-    if tcgen05_mma_is_sparse(form) {
-        arguments.push("tmem_ptr".into());
-    }
-    if tcgen05_mma_has_zero_col_mask(form) {
-        arguments.push("i64".into());
-    }
-    arguments.extend(["i32".into(), "i32".into(), "i32".into()]);
-    arguments
-}
-
-fn tcgen05_mma_selector_layout(form: Tcgen05MmaForm) -> Tcgen05MmaSelectorLayout {
-    let first =
-        5 + u8::from(tcgen05_mma_is_sparse(form)) + u8::from(tcgen05_mma_has_zero_col_mask(form));
-    if tcgen05_mma_is_ws(form) {
-        Tcgen05MmaSelectorLayout::WarpSpecialized {
-            kind_argument: first,
-            b_buffer_argument: first + 1,
-            b_usage_argument: first + 2,
-        }
-    } else {
-        Tcgen05MmaSelectorLayout::Base {
-            kind_argument: first,
-            cta_group_argument: first + 1,
-            collector_a_argument: first + 2,
-            collector_a_upper_exclusive: if tcgen05_mma_is_ashift(form) { 2 } else { 4 },
-        }
-    }
-}
-
-fn tcgen05_mma_imported_properties(form: Tcgen05MmaForm) -> Vec<String> {
-    let layout = tcgen05_mma_selector_layout(form);
-    let (kind, second, third, second_lower, second_upper, third_upper) = match layout {
-        Tcgen05MmaSelectorLayout::Base {
-            kind_argument,
-            cta_group_argument,
-            collector_a_argument,
-            collector_a_upper_exclusive,
-        } => (
-            kind_argument,
-            cta_group_argument,
-            collector_a_argument,
-            1,
-            3,
-            collector_a_upper_exclusive,
-        ),
-        Tcgen05MmaSelectorLayout::WarpSpecialized {
-            kind_argument,
-            b_buffer_argument,
-            b_usage_argument,
-        } => (kind_argument, b_buffer_argument, b_usage_argument, 0, 4, 4),
-    };
-    let mut properties = vec![
-        format!("ImmArg<arg{kind}>"),
-        format!("ImmArg<arg{second}>"),
-        format!("ImmArg<arg{third}>"),
-        "IntrArgMemOnly".into(),
-        format!("Range<arg{kind},0,4>"),
-        format!("Range<arg{second},{second_lower},{second_upper}>"),
-        format!("Range<arg{third},0,{third_upper}>"),
-        "WriteOnly<arg0>".into(),
-    ];
-    if tcgen05_mma_is_tensor_a(form) {
-        properties.push("ReadOnly<arg1>".into());
-    }
-    if form == Tcgen05MmaForm::Tensor {
-        properties.extend([
-            "ArgInfo<arg5>".into(),
-            "ArgInfo<arg6>".into(),
-            "ArgInfo<arg7>".into(),
-        ]);
-    }
-    properties.sort();
-    properties
-}
-
-fn tcgen05_mma_selection_asm(
-    form: Tcgen05MmaForm,
-    kind: Tcgen05MmaKind,
-    cta_group: u8,
-    collector_a: Option<&str>,
-    b_buffer: Option<u8>,
-    b_usage: Option<Tcgen05MmaBUsage>,
-) -> String {
-    let mut head = "tcgen05.mma".to_owned();
-    if tcgen05_mma_is_ws(form) {
-        head.push_str(".ws");
-    }
-    if tcgen05_mma_is_sparse(form) {
-        head.push_str(".sp");
-    }
-    head.push_str(&format!(
-        ".cta_group::{cta_group}.kind::{}",
-        tcgen05_mma_kind_name(kind)
-    ));
-    if tcgen05_mma_is_ws(form) {
-        head.push_str(&format!(
-            ".collector::b{}::{}",
-            b_buffer.expect("warp-specialized B buffer"),
-            tcgen05_mma_b_usage_name(b_usage.expect("warp-specialized B usage"))
-        ));
-    } else {
-        head.push_str(&format!(
-            ".collector::a::{}",
-            collector_a.expect("base collector A usage")
-        ));
-        if tcgen05_mma_is_ashift(form) {
-            head.push_str(".ashift");
-        }
-    }
-
-    let a = if tcgen05_mma_is_tensor_a(form) {
-        "[$a]"
-    } else {
-        "$a"
-    };
-    let mut operands = format!("[$dtmem], {a}, $b");
-    if tcgen05_mma_is_sparse(form) {
-        operands.push_str(", [$spmetadata]");
-    }
-    operands.push_str(", $idesc, $enable_inp_d");
-    if tcgen05_mma_has_zero_col_mask(form) {
-        operands.push_str(", $zero_col_mask");
-    }
-    format!("{head} {operands};")
-}
-
-fn tcgen05_mma_all_selection_asms(form: Tcgen05MmaForm) -> BTreeSet<String> {
-    if tcgen05_mma_is_ws(form) {
-        return [
-            Tcgen05MmaBUsage::Discard,
-            Tcgen05MmaBUsage::LastUse,
-            Tcgen05MmaBUsage::Fill,
-            Tcgen05MmaBUsage::Use,
-        ]
-        .into_iter()
-        .flat_map(|usage| {
-            TCGEN05_MMA_KINDS.into_iter().flat_map(move |kind| {
-                (0..4).map(move |buffer| {
-                    tcgen05_mma_selection_asm(form, kind, 1, None, Some(buffer), Some(usage))
-                })
-            })
-        })
-        .collect();
-    }
-    TCGEN05_MMA_KINDS
-        .into_iter()
-        .flat_map(|kind| {
-            (1..=2).flat_map(move |group| {
-                ["discard", "lastuse", "fill", "use"].map(move |usage| {
-                    tcgen05_mma_selection_asm(form, kind, group, Some(usage), None, None)
-                })
-            })
-        })
-        .collect()
-}
-
-fn tcgen05_mma_valid_selection_asms(form: Tcgen05MmaForm) -> BTreeSet<String> {
-    if !tcgen05_mma_is_ashift(form) {
-        return tcgen05_mma_all_selection_asms(form);
-    }
-    TCGEN05_MMA_KINDS
-        .into_iter()
-        .flat_map(|kind| {
-            (1..=2).flat_map(move |group| {
-                ["discard", "lastuse"].map(move |usage| {
-                    tcgen05_mma_selection_asm(form, kind, group, Some(usage), None, None)
-                })
-            })
-        })
-        .collect()
-}
-
-fn tcgen05_mma_target_contract(
-    kind: Tcgen05MmaKind,
-    alternatives: &[(&str, &str)],
-) -> TargetContract {
-    TargetContract {
-        selectors: vec![TargetSelectorBinding {
-            name: "kind".into(),
-            value: tcgen05_mma_kind_name(kind).into(),
-        }],
-        alternatives: alternatives
-            .iter()
-            .map(
-                |(target, minimum_ptx)| crate::model::TargetContractAlternative {
-                    target: (*target).into(),
-                    minimum_ptx: (*minimum_ptx).into(),
-                },
-            )
-            .collect(),
-    }
-}
-
-fn expected_tcgen05_mma_target_contracts(backend: IntrinsicBackend) -> Vec<TargetContract> {
-    const LLVM_COMMON: &[(&str, &str)] = &[
-        ("sm_100a", "8.6"),
-        ("sm_100f", "8.8"),
-        ("sm_101a", "8.6"),
-        ("sm_101f", "8.8"),
-        ("sm_103a", "8.8"),
-        ("sm_103f", "8.8"),
-        ("sm_110a", "9.0"),
-        ("sm_110f", "9.0"),
-    ];
-    const LLVM_I8: &[(&str, &str)] = &[("sm_100a", "8.6"), ("sm_101a", "8.6"), ("sm_110a", "9.0")];
-    const LIBNVVM_COMMON: &[(&str, &str)] = &[
-        ("sm_100a", "8.6"),
-        ("sm_100f", "8.8"),
-        ("sm_103a", "8.8"),
-        ("sm_103f", "8.8"),
-        ("sm_110a", "9.0"),
-        ("sm_110f", "9.0"),
-    ];
-    const LIBNVVM_I8: &[(&str, &str)] = &[("sm_100a", "8.6"), ("sm_110a", "9.0")];
-    TCGEN05_MMA_KINDS
-        .into_iter()
-        .map(|kind| {
-            let alternatives = match (backend, kind) {
-                (IntrinsicBackend::LlvmNvptx, Tcgen05MmaKind::I8) => LLVM_I8,
-                (IntrinsicBackend::LlvmNvptx, _) => LLVM_COMMON,
-                (IntrinsicBackend::LibNvvm, Tcgen05MmaKind::I8) => LIBNVVM_I8,
-                (IntrinsicBackend::LibNvvm, _) => LIBNVVM_COMMON,
-            };
-            tcgen05_mma_target_contract(kind, alternatives)
-        })
-        .collect()
-}
-
-fn tcgen05_mma_expected_ptx(
-    form: Tcgen05MmaForm,
-    alias: Option<Tcgen05MmaAlias>,
-) -> InstructionPattern {
-    let kind = if alias.is_some() {
-        Tcgen05MmaKind::F8f6f4
-    } else {
-        Tcgen05MmaKind::F16
-    };
-    let asm = if tcgen05_mma_is_ws(form) {
-        tcgen05_mma_selection_asm(
-            form,
-            kind,
-            1,
-            None,
-            Some(0),
-            Some(Tcgen05MmaBUsage::Discard),
-        )
-    } else {
-        tcgen05_mma_selection_asm(form, kind, 1, Some("discard"), None, None)
-    };
-    let head = asm.split_whitespace().next().unwrap();
-    let mut components = head.split('.');
-    let mnemonic = components.next().unwrap().into();
-    let modifiers = components.map(str::to_owned).collect();
-    let mut operands = vec![OperandPattern::Address];
-    operands.push(if tcgen05_mma_is_tensor_a(form) {
-        OperandPattern::Address
-    } else {
-        OperandPattern::Register
-    });
-    operands.push(OperandPattern::Register);
-    if tcgen05_mma_is_sparse(form) {
-        operands.push(OperandPattern::Address);
-    }
-    operands.extend([
-        OperandPattern::Register,
-        OperandPattern::Exact {
-            value: "%enable_pred".into(),
-        },
-    ]);
-    if tcgen05_mma_has_zero_col_mask(form) {
-        operands.push(OperandPattern::Register);
-    }
-    InstructionPattern {
-        mnemonic,
-        modifiers,
-        operands,
-    }
-}
-
-fn tcgen05_mma_rust_arguments(form: Tcgen05MmaForm, alias: Option<Tcgen05MmaAlias>) -> Vec<String> {
-    if alias.is_some() && form == Tcgen05MmaForm::WsTensor {
-        return ["u32", "u32", "u64", "u64", "u32", "bool"]
-            .into_iter()
-            .map(str::to_owned)
-            .collect();
-    }
-    let mut arguments = tcgen05_mma_llvm_arguments(form);
-    if alias.is_some() {
-        arguments.truncate(arguments.len() - 3);
-    }
-    arguments
-        .iter()
-        .map(|argument| match argument.as_str() {
-            "tmem_ptr" | "i32" => "u32",
-            "i64" => "u64",
-            "i1" => "bool",
-            _ => unreachable!("closed tcgen05 MMA LLVM type"),
-        })
-        .map(str::to_owned)
-        .collect()
-}
-
-fn tcgen05_mma_dialect_operands(
-    form: Tcgen05MmaForm,
-    _alias: Option<Tcgen05MmaAlias>,
-) -> Vec<String> {
-    let mut arguments = tcgen05_mma_llvm_arguments(form);
-    arguments.truncate(arguments.len() - 3);
-    arguments
-        .iter()
-        .map(|argument| match argument.as_str() {
-            "tmem_ptr" | "i32" => "i32",
-            "i64" => "i64",
-            "i1" => "i1",
-            _ => unreachable!("closed tcgen05 MMA LLVM type"),
-        })
-        .map(str::to_owned)
-        .collect()
-}
-
-fn tcgen05_mma_public_id(form: Tcgen05MmaForm, alias: Option<Tcgen05MmaAlias>) -> String {
-    alias.map_or_else(
-        || format!("tcgen05_mma_{}", tcgen05_mma_form_name(form)),
-        |alias| {
-            let alias = tcgen05_mma_alias_name(alias);
-            if form == Tcgen05MmaForm::WsTensor {
-                format!("tcgen05_mma_ws_{alias}")
-            } else {
-                format!("tcgen05_mma_{alias}")
-            }
-        },
-    )
-}
-
-fn tcgen05_mma_operation_key(form: Tcgen05MmaForm, alias: Option<Tcgen05MmaAlias>) -> String {
-    let base = tcgen05_mma_form_name(form).replace('_', ".");
-    alias.map_or_else(
-        || format!("tcgen05.mma.{base}"),
-        |alias| format!("tcgen05.mma.{base}.{}", tcgen05_mma_alias_name(alias)),
-    )
-}
-
-fn tcgen05_mma_adapter(form: Tcgen05MmaForm, alias: Option<Tcgen05MmaAlias>) -> Tcgen05Adapter {
-    match alias {
-        Some(_) if form == Tcgen05MmaForm::WsTensor => {
-            Tcgen05Adapter::MmaWsFixedSelectorsDropLegacyADescriptor
-        }
-        _ => Tcgen05Adapter::MmaDirectSelectors,
-    }
-}
-
-fn materialize_tcgen05_mma_variant(
-    admission: &Tcgen05Admission,
-    variant: &Tcgen05MmaAdmissionVariant,
-    llvm_target: &CatalogTargetRequirement,
-    libnvvm_target: &CatalogTargetRequirement,
-) -> OverlayIntrinsic {
-    let form = variant.form;
-    let alias = variant.alias;
-    let id = tcgen05_mma_public_id(form, alias);
-    let operation_key = tcgen05_mma_operation_key(form, alias);
-    let llvm_arguments = tcgen05_mma_llvm_arguments(form);
-    let rust_arguments = tcgen05_mma_rust_arguments(form, alias);
-    let dialect_operands = tcgen05_mma_dialect_operands(form, alias);
-    let fixed_selectors = alias.map(|_| Tcgen05MmaFixedSelectors {
-        kind: Tcgen05MmaKind::F8f6f4,
-        b_buffer: 0,
-        b_usage: Tcgen05MmaBUsage::Discard,
-    });
-
-    OverlayIntrinsic {
-        id: id.clone(),
-        abi_id: variant.abi_id.clone(),
-        operation_key,
-        family: "tcgen05".into(),
-        source: None,
-        source_record: Some(tcgen05_mma_source_record(form)),
-        rust_module: "tcgen05".into(),
-        rust_name: id.clone(),
-        rust_arguments,
-        rust_result: "()".into(),
-        safe: false,
-        must_use: false,
-        safe_allowlist_reason: None,
-        public_rust_path: format!("cuda_intrinsics::tcgen05::{id}"),
-        compatibility_rust_paths: vec![if alias.is_some() {
-            format!("cuda_device::tcgen05::{id}")
-        } else {
-            format!("cuda_device::tcgen05::__{id}")
-        }],
-        dialect_op_type: TCGEN05_MMA_DIALECT_OP_TYPE.into(),
-        dialect_op_name: TCGEN05_MMA_DIALECT_OP_NAME.into(),
-        dialect_operands,
-        dialect_results: vec![],
-        llvm_symbol: Some(tcgen05_mma_llvm_symbol(form)),
-        resolved_llvm_symbol: None,
-        llvm_arguments,
-        llvm_results: vec![],
-        pure: false,
-        memory: "read_write".into(),
-        // TableGen omits IntrConvergent, but collective MMA must not move across control flow.
-        convergent: true,
-        execution_scope: "thread".into(),
-        minimum_ptx: "8.6".into(),
-        minimum_sm: None,
-        ptx_result: "()".into(),
-        targets: TCGEN05_LLVM_TARGETS.into(),
-        ptx_isa_version: "8.6".into(),
-        ptx_isa_section: "Tensor Memory tcgen05 instructions".into(),
-        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-memory".into(),
-        lowering: "generated_tcgen05_mma".into(),
-        backend_lowerings: vec![
-            OverlayBackendLowering {
-                backend: IntrinsicBackend::LlvmNvptx,
-                mechanism: BackendLoweringMechanism::InlinePtx,
-                evidence_profile: admission
-                    .mma_llvm_evidence_profile
-                    .as_ref()
-                    .expect("validated tcgen05 MMA LLVM evidence profile")
-                    .clone(),
-                targets: None,
-                minimum_ptx: None,
-                minimum_sm: None,
-            },
-            OverlayBackendLowering {
-                backend: IntrinsicBackend::LibNvvm,
-                mechanism: BackendLoweringMechanism::InlinePtx,
-                evidence_profile: admission
-                    .mma_libnvvm_evidence_profile
-                    .as_ref()
-                    .expect("validated tcgen05 MMA libNVVM evidence profile")
-                    .clone(),
-                targets: None,
-                minimum_ptx: None,
-                minimum_sm: None,
-            },
-        ],
-        packed_atomic: None,
-        redux: None,
-        vote: None,
-        active_mask: None,
-        warp_match: None,
-        warp_barrier: None,
-        warp_shuffle: None,
-        dot_product: None,
-        packed_alu: None,
-        integer_minmax: None,
-        packed_conversion: None,
-        scalar_conversion: None,
-        scalar_arithmetic: None,
-        scalar_math: None,
-        extended_minmax: None,
-        cp_async_copy: None,
-        cp_async_control: None,
-        cp_async_mbarrier: None,
-        mbarrier_basic: None,
-        movmatrix: None,
-        mbarrier_extended: None,
-        register_mma: None,
-        sparse_mma: None,
-        prmt: None,
-        cluster_barrier: None,
-        wgmma_control: None,
-        special_register: None,
-        debug_control: None,
-        cluster_memory: None,
-        clc: None,
-        tma: None,
-        tcgen05: Some(Tcgen05 {
-            operation: Tcgen05Operation::Mma,
-            cp: None,
-            ld: None,
-            st: None,
-            mma: Some(Tcgen05Mma {
-                form,
-                selector_layout: tcgen05_mma_selector_layout(form),
-                fixed_selectors,
-                alias,
-                llvm_target: llvm_target.clone(),
-                libnvvm_target: libnvvm_target.clone(),
-            }),
-            adapter: tcgen05_mma_adapter(form, alias),
-            source_contract: Tcgen05SourceContract::TablegenSelectionChangesPtx,
-            runtime_validation: admission.runtime_validation,
-        }),
-        ldmatrix_variant: None,
-        ldmatrix_safety: None,
-        ldmatrix_adapter: None,
-        selected_address_space: None,
-        expected_ptx: tcgen05_mma_expected_ptx(form, alias),
-        summary: match (form, alias) {
-            (Tcgen05MmaForm::WsTensor, Some(_)) => {
-                "Issues one f8f6f4 warp-specialized tensor-memory MMA.".into()
-            }
-            (Tcgen05MmaForm::Shared, Some(_)) => {
-                "Issues one f8f6f4 standard tensor-memory MMA.".into()
-            }
-            _ => "Issues one selector-controlled tensor-memory MMA.".into(),
-        },
-    }
-}
-
-struct Tcgen05CpMemberRecipe {
-    llvm_suffix: &'static str,
-    ptx_suffix: &'static str,
-    op_suffix: &'static str,
-    selection_stem: &'static str,
-}
-
-const TCGEN05_CP_MEMBERS: [Tcgen05CpMember; 17] = [
-    Tcgen05CpMember::M128x128bB4x16P64,
-    Tcgen05CpMember::M128x128bB6x16P32,
-    Tcgen05CpMember::M128x128b,
-    Tcgen05CpMember::M128x256bB4x16P64,
-    Tcgen05CpMember::M128x256bB6x16P32,
-    Tcgen05CpMember::M32x128bWarpx4B4x16P64,
-    Tcgen05CpMember::M32x128bWarpx4B6x16P32,
-    Tcgen05CpMember::M32x128bWarpx4,
-    Tcgen05CpMember::M4x256bB4x16P64,
-    Tcgen05CpMember::M4x256bB6x16P32,
-    Tcgen05CpMember::M4x256b,
-    Tcgen05CpMember::M64x128bWarpx2Pair0123B4x16P64,
-    Tcgen05CpMember::M64x128bWarpx2Pair0123B6x16P32,
-    Tcgen05CpMember::M64x128bWarpx2Pair0123,
-    Tcgen05CpMember::M64x128bWarpx2Pair0213B4x16P64,
-    Tcgen05CpMember::M64x128bWarpx2Pair0213B6x16P32,
-    Tcgen05CpMember::M64x128bWarpx2Pair0213,
-];
-
-fn tcgen05_cp_member_recipe(member: Tcgen05CpMember) -> Tcgen05CpMemberRecipe {
-    use Tcgen05CpMember::*;
-    let (llvm_suffix, ptx_suffix, op_suffix, selection_stem) = match member {
-        M128x128bB4x16P64 => (
-            "128x128b.b4x16_p64",
-            "128x128b.b8x16.b4x16_p64",
-            "128x128bB4x16P64",
-            "128x128bb4x16_p64",
-        ),
-        M128x128bB6x16P32 => (
-            "128x128b.b6x16_p32",
-            "128x128b.b8x16.b6x16_p32",
-            "128x128bB6x16P32",
-            "128x128bb6x16_p32",
-        ),
-        M128x128b => ("128x128b", "128x128b", "128x128b", "128x128b"),
-        M128x256bB4x16P64 => (
-            "128x256b.b4x16_p64",
-            "128x256b.b8x16.b4x16_p64",
-            "128x256bB4x16P64",
-            "128x256bb4x16_p64",
-        ),
-        M128x256bB6x16P32 => (
-            "128x256b.b6x16_p32",
-            "128x256b.b8x16.b6x16_p32",
-            "128x256bB6x16P32",
-            "128x256bb6x16_p32",
-        ),
-        M32x128bWarpx4B4x16P64 => (
-            "32x128b_warpx4.b4x16_p64",
-            "32x128b.warpx4.b8x16.b4x16_p64",
-            "32x128bWarpx4B4x16P64",
-            "32x128b4x16_p64",
-        ),
-        M32x128bWarpx4B6x16P32 => (
-            "32x128b_warpx4.b6x16_p32",
-            "32x128b.warpx4.b8x16.b6x16_p32",
-            "32x128bWarpx4B6x16P32",
-            "32x128b6x16_p32",
-        ),
-        M32x128bWarpx4 => (
-            "32x128b_warpx4",
-            "32x128b.warpx4",
-            "32x128bWarpx4",
-            "32x128",
-        ),
-        M4x256bB4x16P64 => (
-            "4x256b.b4x16_p64",
-            "4x256b.b8x16.b4x16_p64",
-            "4x256bB4x16P64",
-            "4x256bb4x16_p64",
-        ),
-        M4x256bB6x16P32 => (
-            "4x256b.b6x16_p32",
-            "4x256b.b8x16.b6x16_p32",
-            "4x256bB6x16P32",
-            "4x256bb6x16_p32",
-        ),
-        M4x256b => ("4x256b", "4x256b", "4x256b", "4x256b"),
-        M64x128bWarpx2Pair0123B4x16P64 => (
-            "64x128b_warpx2_01_23.b4x16_p64",
-            "64x128b.warpx2::01_23.b8x16.b4x16_p64",
-            "64x128bWarpx2Pair0123B4x16P64",
-            "64x128_2b4x16_p64",
-        ),
-        M64x128bWarpx2Pair0123B6x16P32 => (
-            "64x128b_warpx2_01_23.b6x16_p32",
-            "64x128b.warpx2::01_23.b8x16.b6x16_p32",
-            "64x128bWarpx2Pair0123B6x16P32",
-            "64x128_2b6x16_p32",
-        ),
-        M64x128bWarpx2Pair0123 => (
-            "64x128b_warpx2_01_23",
-            "64x128b.warpx2::01_23",
-            "64x128bWarpx2Pair0123",
-            "64x128_2",
-        ),
-        M64x128bWarpx2Pair0213B4x16P64 => (
-            "64x128b_warpx2_02_13.b4x16_p64",
-            "64x128b.warpx2::02_13.b8x16.b4x16_p64",
-            "64x128bWarpx2Pair0213B4x16P64",
-            "64x128_1b4x16_p64",
-        ),
-        M64x128bWarpx2Pair0213B6x16P32 => (
-            "64x128b_warpx2_02_13.b6x16_p32",
-            "64x128b.warpx2::02_13.b8x16.b6x16_p32",
-            "64x128bWarpx2Pair0213B6x16P32",
-            "64x128_1b6x16_p32",
-        ),
-        M64x128bWarpx2Pair0213 => (
-            "64x128b_warpx2_02_13",
-            "64x128b.warpx2::02_13",
-            "64x128bWarpx2Pair0213",
-            "64x128_1",
-        ),
-    };
-    Tcgen05CpMemberRecipe {
-        llvm_suffix,
-        ptx_suffix,
-        op_suffix,
-        selection_stem,
-    }
-}
-
-fn materialize_tcgen05_cp_variant(
-    base: &OverlayIntrinsic,
-    admission: &Tcgen05Admission,
-    variant: &Tcgen05CpAdmissionVariant,
-) -> OverlayIntrinsic {
-    let recipe = tcgen05_cp_member_recipe(variant.member);
-    let group = match variant.group {
-        Tcgen05CpGroup::Cg1 => 1,
-        Tcgen05CpGroup::Cg2 => 2,
-    };
-    let group_suffix = if group == 1 { "" } else { "_cg2" };
-    let id_suffix = recipe.llvm_suffix.replace('.', "_");
-    let id = format!("tcgen05_cp_{id_suffix}{group_suffix}");
-    let mut record = base.clone();
-    record.id = id.clone();
-    record.abi_id = variant.abi_id.clone();
-    record.operation_key = format!("tcgen05.cp.{}.cg{group}", recipe.llvm_suffix);
-    record.source_record = Some(format!("int_nvvm_tcgen05_cp_{}_cg{group}", id_suffix));
-    record.rust_name = id.clone();
-    record.public_rust_path = format!("cuda_intrinsics::tcgen05::{id}");
-    record.compatibility_rust_paths = vec![format!("cuda_device::tcgen05::{id}")];
-    record.dialect_op_type = format!(
-        "Tcgen05Cp{}{}Op",
-        recipe.op_suffix,
-        if group == 1 { "" } else { "Cg2" }
-    );
-    record.dialect_op_name = format!("nvvm.{id}");
-    record.llvm_symbol = Some(format!(
-        "llvm.nvvm.tcgen05.cp.{}.cg{group}",
-        recipe.llvm_suffix
-    ));
-    record.backend_lowerings[0].evidence_profile = admission
-        .cp_llvm_evidence_profile
-        .as_ref()
-        .expect("validated tcgen05 copy LLVM evidence profile")
-        .clone();
-    record.backend_lowerings[1].evidence_profile = admission
-        .cp_libnvvm_evidence_profile
-        .as_ref()
-        .expect("validated tcgen05 copy libNVVM evidence profile")
-        .clone();
-    record.tcgen05 = Some(Tcgen05 {
-        operation: if group == 1 {
-            Tcgen05Operation::CpSmemToTmem
-        } else {
-            Tcgen05Operation::CpSmemToTmemCg2
-        },
-        cp: Some(Tcgen05Cp {
-            member: variant.member,
-            group: variant.group,
-        }),
-        ld: None,
-        st: None,
-        mma: None,
-        adapter: Tcgen05Adapter::TmemDescriptorToVoid,
-        source_contract: Tcgen05SourceContract::ExactTablegenSelection,
-        runtime_validation: admission.runtime_validation,
-    });
-    record.expected_ptx.modifiers = std::iter::once("cp".into())
-        .chain(std::iter::once(format!("cta_group::{group}")))
-        .chain(recipe.ptx_suffix.split('.').map(Into::into))
-        .collect();
-    record.summary = format!(
-        "Copies one {} tile from shared memory to tensor memory.",
-        recipe.ptx_suffix
-    );
-    record
-}
-
-const TCGEN05_LD_VARIANTS: [(Tcgen05LdShape, Tcgen05LdMultiplicity); 29] = {
-    use Tcgen05LdMultiplicity::*;
-    use Tcgen05LdShape::*;
-    [
-        (M16x64b, X1),
-        (M16x64b, X2),
-        (M16x64b, X4),
-        (M16x64b, X8),
-        (M16x64b, X16),
-        (M16x64b, X32),
-        (M16x64b, X64),
-        (M16x64b, X128),
-        (M16x128b, X1),
-        (M16x128b, X2),
-        (M16x128b, X4),
-        (M16x128b, X8),
-        (M16x128b, X16),
-        (M16x128b, X32),
-        (M16x128b, X64),
-        (M16x256b, X1),
-        (M16x256b, X2),
-        (M16x256b, X4),
-        (M16x256b, X8),
-        (M16x256b, X16),
-        (M16x256b, X32),
-        (M32x32b, X1),
-        (M32x32b, X2),
-        (M32x32b, X4),
-        (M32x32b, X8),
-        (M32x32b, X16),
-        (M32x32b, X32),
-        (M32x32b, X64),
-        (M32x32b, X128),
-    ]
-};
-
-const TCGEN05_OFFSET_LDST_VARIANTS: [(Tcgen05LdShape, Tcgen05LdMultiplicity); 8] = {
-    use Tcgen05LdMultiplicity::*;
-    use Tcgen05LdShape::*;
-    [
-        (M16x32bx2, X1),
-        (M16x32bx2, X2),
-        (M16x32bx2, X4),
-        (M16x32bx2, X8),
-        (M16x32bx2, X16),
-        (M16x32bx2, X32),
-        (M16x32bx2, X64),
-        (M16x32bx2, X128),
-    ]
-};
-
-fn tcgen05_ld_shape_name(shape: Tcgen05LdShape) -> &'static str {
-    match shape {
-        Tcgen05LdShape::M16x32bx2 => "16x32bx2",
-        Tcgen05LdShape::M16x64b => "16x64b",
-        Tcgen05LdShape::M16x128b => "16x128b",
-        Tcgen05LdShape::M16x256b => "16x256b",
-        Tcgen05LdShape::M32x32b => "32x32b",
-    }
-}
-
-fn tcgen05_ld_multiplicity_name(multiplicity: Tcgen05LdMultiplicity) -> &'static str {
-    match multiplicity {
-        Tcgen05LdMultiplicity::X1 => "x1",
-        Tcgen05LdMultiplicity::X2 => "x2",
-        Tcgen05LdMultiplicity::X4 => "x4",
-        Tcgen05LdMultiplicity::X8 => "x8",
-        Tcgen05LdMultiplicity::X16 => "x16",
-        Tcgen05LdMultiplicity::X32 => "x32",
-        Tcgen05LdMultiplicity::X64 => "x64",
-        Tcgen05LdMultiplicity::X128 => "x128",
-    }
-}
-
-fn tcgen05_ld_register_count(ld: Tcgen05Ld) -> usize {
-    ld.shape.register_multiplier() * ld.multiplicity.count()
-}
-
-fn tcgen05_ld_id(ld: Tcgen05Ld) -> String {
-    format!(
-        "tcgen05_ld_{}_{}_{}",
-        tcgen05_ld_shape_name(ld.shape),
-        tcgen05_ld_multiplicity_name(ld.multiplicity),
-        if ld.pack16 { "pack16" } else { "raw" }
-    )
-}
-
-fn tcgen05_ld_source_record(ld: Tcgen05Ld) -> String {
-    format!(
-        "int_nvvm_tcgen05_ld_{}_{}",
-        tcgen05_ld_shape_name(ld.shape),
-        tcgen05_ld_multiplicity_name(ld.multiplicity)
-    )
-}
-
-fn tcgen05_ld_llvm_symbol(ld: Tcgen05Ld) -> String {
-    format!(
-        "llvm.nvvm.tcgen05.ld.{}.{}",
-        tcgen05_ld_shape_name(ld.shape),
-        tcgen05_ld_multiplicity_name(ld.multiplicity)
-    )
-}
-
-fn tcgen05_ld_rust_result(ld: Tcgen05Ld) -> String {
-    match tcgen05_ld_register_count(ld) {
-        1 => "u32".into(),
-        count => format!("[u32; {count}]"),
-    }
-}
-
-fn tcgen05_ld_llvm_result(ld: Tcgen05Ld) -> String {
-    match tcgen05_ld_register_count(ld) {
-        1 => "i32".into(),
-        count => format!("v{count}i32"),
-    }
-}
-
-fn tcgen05_ld_op_type(ld: Tcgen05Ld) -> String {
-    let shape = tcgen05_ld_shape_name(ld.shape);
-    let multiplicity = tcgen05_ld_multiplicity_name(ld.multiplicity)
-        .strip_prefix('x')
-        .unwrap();
-    format!(
-        "Tcgen05Ld{shape}X{multiplicity}{}Op",
-        if ld.pack16 { "Pack16" } else { "Raw" }
-    )
-}
-
-fn tcgen05_ld_modifiers(ld: Tcgen05Ld) -> Vec<String> {
-    let mut modifiers = vec![
-        "ld".into(),
-        "sync".into(),
-        "aligned".into(),
-        tcgen05_ld_shape_name(ld.shape).into(),
-        tcgen05_ld_multiplicity_name(ld.multiplicity).into(),
-    ];
-    if ld.pack16 {
-        modifiers.push("pack::16b".into());
-    }
-    modifiers.push("b32".into());
-    modifiers
-}
-
-fn tcgen05_ld_operands(ld: Tcgen05Ld) -> Vec<OperandPattern> {
-    let result = OperandPattern::RegisterList {
-        length: tcgen05_ld_register_count(ld),
-    };
-    let mut operands = vec![result, OperandPattern::Address];
-    if ld.shape == Tcgen05LdShape::M16x32bx2 {
-        operands.push(OperandPattern::Immediate);
-    }
-    operands
-}
-
-fn materialize_tcgen05_ld_variant(
-    base: &OverlayIntrinsic,
-    admission: &Tcgen05Admission,
-    variant: &Tcgen05LdAdmissionVariant,
-) -> OverlayIntrinsic {
-    let ld = Tcgen05Ld {
-        shape: variant.shape,
-        multiplicity: variant.multiplicity,
-        pack16: variant.pack16,
-    };
-    let id = tcgen05_ld_id(ld);
-    let register_count = tcgen05_ld_register_count(ld);
-    let rust_result = tcgen05_ld_rust_result(ld);
-    let llvm_result = tcgen05_ld_llvm_result(ld);
-    let mode = if ld.pack16 { "pack16" } else { "raw" };
-    let mut record = base.clone();
-    record.id = id.clone();
-    record.abi_id = variant.abi_id.clone();
-    record.operation_key = format!(
-        "tcgen05.ld.{}.{}.{}",
-        tcgen05_ld_shape_name(ld.shape),
-        tcgen05_ld_multiplicity_name(ld.multiplicity),
-        mode
-    );
-    record.source_record = Some(tcgen05_ld_source_record(ld));
-    record.rust_name = id.clone();
-    let has_half_split_offset = ld.shape == Tcgen05LdShape::M16x32bx2;
-    record.rust_arguments = if has_half_split_offset {
-        vec!["u32".into(), "i64".into()]
-    } else {
-        vec!["u32".into()]
-    };
-    record.rust_result = rust_result.clone();
-    record.must_use = true;
-    record.public_rust_path = format!("cuda_intrinsics::tcgen05::{id}");
-    record.compatibility_rust_paths = vec![format!(
-        "cuda_device::tcgen05::{}",
-        if has_half_split_offset {
-            format!("__{id}")
-        } else {
-            id.clone()
-        }
-    )];
-    record.dialect_op_type = tcgen05_ld_op_type(ld);
-    record.dialect_op_name = format!("nvvm.{id}");
-    record.dialect_operands = if has_half_split_offset {
-        vec!["i32".into(), "i64".into()]
-    } else {
-        vec!["i32".into()]
-    };
-    record.dialect_results = vec!["i32".into(); register_count];
-    record.llvm_symbol = Some(tcgen05_ld_llvm_symbol(ld));
-    record.resolved_llvm_symbol = None;
-    record.llvm_arguments = if has_half_split_offset {
-        vec!["tmem_ptr".into(), "i64".into(), "i1".into()]
-    } else {
-        vec!["tmem_ptr".into(), "i1".into()]
-    };
-    record.llvm_results = vec![llvm_result];
-    record.ptx_result = rust_result;
-    record.execution_scope = Tcgen05Operation::Ld.execution_scope().into();
-    record.backend_lowerings[0].evidence_profile = if has_half_split_offset {
-        &admission.offset_llvm_evidence_profile
-    } else {
-        &admission.ld_llvm_evidence_profile
-    }
-    .as_ref()
-    .expect("validated tcgen05 load LLVM evidence profile")
-    .clone();
-    record.backend_lowerings[1].evidence_profile = if has_half_split_offset {
-        &admission.offset_libnvvm_evidence_profile
-    } else {
-        &admission.ld_libnvvm_evidence_profile
-    }
-    .as_ref()
-    .expect("validated tcgen05 load libNVVM evidence profile")
-    .clone();
-    record.tcgen05 = Some(Tcgen05 {
-        operation: Tcgen05Operation::Ld,
-        cp: None,
-        ld: Some(ld),
-        st: None,
-        mma: None,
-        adapter: if has_half_split_offset {
-            Tcgen05Adapter::TmemHalfSplitOffsetInjectPack16ToU32Registers
-        } else {
-            Tcgen05Adapter::TmemInjectPack16ToU32Registers
-        },
-        source_contract: Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
-        runtime_validation: admission.runtime_validation,
-    });
-    record.expected_ptx.modifiers = tcgen05_ld_modifiers(ld);
-    record.expected_ptx.operands = tcgen05_ld_operands(ld);
-    record.summary = format!(
-        "Loads {register_count} {} 32-bit register value{} from tensor memory.",
-        if ld.pack16 { "packed" } else { "raw" },
-        if register_count == 1 { "" } else { "s" }
-    );
-    record
-}
-
-const TCGEN05_ST_VARIANTS: [(Tcgen05LdShape, Tcgen05LdMultiplicity); 29] = TCGEN05_LD_VARIANTS;
-
-fn tcgen05_st_register_count(st: Tcgen05St) -> usize {
-    st.shape.register_multiplier() * st.multiplicity.count()
-}
-
-fn tcgen05_st_id(st: Tcgen05St) -> String {
-    format!(
-        "tcgen05_st_{}_{}_{}",
-        tcgen05_ld_shape_name(st.shape),
-        tcgen05_ld_multiplicity_name(st.multiplicity),
-        if st.unpack16 { "unpack16" } else { "raw" }
-    )
-}
-
-fn tcgen05_st_source_record(st: Tcgen05St) -> String {
-    format!(
-        "int_nvvm_tcgen05_st_{}_{}",
-        tcgen05_ld_shape_name(st.shape),
-        tcgen05_ld_multiplicity_name(st.multiplicity)
-    )
-}
-
-fn tcgen05_st_llvm_symbol(st: Tcgen05St) -> String {
-    format!(
-        "llvm.nvvm.tcgen05.st.{}.{}",
-        tcgen05_ld_shape_name(st.shape),
-        tcgen05_ld_multiplicity_name(st.multiplicity)
-    )
-}
-
-fn tcgen05_st_rust_data(st: Tcgen05St) -> String {
-    match tcgen05_st_register_count(st) {
-        1 => "u32".into(),
-        count => format!("[u32; {count}]"),
-    }
-}
-
-fn tcgen05_st_llvm_data(st: Tcgen05St) -> String {
-    match tcgen05_st_register_count(st) {
-        1 => "i32".into(),
-        count => format!("v{count}i32"),
-    }
-}
-
-fn tcgen05_st_op_type(st: Tcgen05St) -> String {
-    let shape = tcgen05_ld_shape_name(st.shape);
-    let multiplicity = tcgen05_ld_multiplicity_name(st.multiplicity)
-        .strip_prefix('x')
-        .unwrap();
-    format!(
-        "Tcgen05St{shape}X{multiplicity}{}Op",
-        if st.unpack16 { "Unpack16" } else { "Raw" }
-    )
-}
-
-fn tcgen05_st_modifiers(st: Tcgen05St) -> Vec<String> {
-    let mut modifiers = vec![
-        "st".into(),
-        "sync".into(),
-        "aligned".into(),
-        tcgen05_ld_shape_name(st.shape).into(),
-        tcgen05_ld_multiplicity_name(st.multiplicity).into(),
-    ];
-    if st.unpack16 {
-        modifiers.push("unpack::16b".into());
-    }
-    modifiers.push("b32".into());
-    modifiers
-}
-
-fn tcgen05_st_operands(st: Tcgen05St) -> Vec<OperandPattern> {
-    let data = OperandPattern::RegisterList {
-        length: tcgen05_st_register_count(st),
-    };
-    let mut operands = vec![OperandPattern::Address];
-    if st.shape == Tcgen05LdShape::M16x32bx2 {
-        operands.push(OperandPattern::Immediate);
-    }
-    operands.push(data);
-    operands
-}
-
-fn materialize_tcgen05_st_variant(
-    base: &OverlayIntrinsic,
-    admission: &Tcgen05Admission,
-    variant: &Tcgen05StAdmissionVariant,
-) -> OverlayIntrinsic {
-    let st = Tcgen05St {
-        shape: variant.shape,
-        multiplicity: variant.multiplicity,
-        unpack16: variant.unpack16,
-    };
-    let id = tcgen05_st_id(st);
-    let register_count = tcgen05_st_register_count(st);
-    let rust_data = tcgen05_st_rust_data(st);
-    let llvm_data = tcgen05_st_llvm_data(st);
-    let mode = if st.unpack16 { "unpack16" } else { "raw" };
-    let mut record = base.clone();
-    record.id = id.clone();
-    record.abi_id = variant.abi_id.clone();
-    record.operation_key = format!(
-        "tcgen05.st.{}.{}.{}",
-        tcgen05_ld_shape_name(st.shape),
-        tcgen05_ld_multiplicity_name(st.multiplicity),
-        mode
-    );
-    record.source_record = Some(tcgen05_st_source_record(st));
-    record.rust_name = id.clone();
-    let has_half_split_offset = st.shape == Tcgen05LdShape::M16x32bx2;
-    record.rust_arguments = if has_half_split_offset {
-        vec!["u32".into(), "i64".into(), rust_data]
-    } else {
-        vec!["u32".into(), rust_data]
-    };
-    record.rust_result = "()".into();
-    record.must_use = false;
-    record.public_rust_path = format!("cuda_intrinsics::tcgen05::{id}");
-    record.compatibility_rust_paths = vec![format!(
-        "cuda_device::tcgen05::{}",
-        if has_half_split_offset {
-            format!("__{id}")
-        } else {
-            id.clone()
-        }
-    )];
-    record.dialect_op_type = tcgen05_st_op_type(st);
-    record.dialect_op_name = format!("nvvm.{id}");
-    record.dialect_operands = std::iter::once("i32".into())
-        .chain(has_half_split_offset.then(|| "i64".into()))
-        .chain(std::iter::repeat_n("i32".into(), register_count))
-        .collect();
-    record.dialect_results.clear();
-    record.llvm_symbol = Some(tcgen05_st_llvm_symbol(st));
-    record.resolved_llvm_symbol = None;
-    record.llvm_arguments = if has_half_split_offset {
-        vec!["tmem_ptr".into(), "i64".into(), llvm_data, "i1".into()]
-    } else {
-        vec!["tmem_ptr".into(), llvm_data, "i1".into()]
-    };
-    record.llvm_results.clear();
-    record.memory = "write".into();
-    record.ptx_result = "()".into();
-    record.execution_scope = Tcgen05Operation::St.execution_scope().into();
-    record.backend_lowerings[0].evidence_profile = if has_half_split_offset {
-        &admission.offset_llvm_evidence_profile
-    } else {
-        &admission.st_llvm_evidence_profile
-    }
-    .as_ref()
-    .expect("validated tcgen05 store LLVM evidence profile")
-    .clone();
-    record.backend_lowerings[1].evidence_profile = if has_half_split_offset {
-        &admission.offset_libnvvm_evidence_profile
-    } else {
-        &admission.st_libnvvm_evidence_profile
-    }
-    .as_ref()
-    .expect("validated tcgen05 store libNVVM evidence profile")
-    .clone();
-    record.tcgen05 = Some(Tcgen05 {
-        operation: Tcgen05Operation::St,
-        cp: None,
-        ld: None,
-        st: Some(st),
-        mma: None,
-        adapter: if has_half_split_offset {
-            Tcgen05Adapter::TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid
-        } else {
-            Tcgen05Adapter::TmemU32RegistersInjectUnpack16ToVoid
-        },
-        source_contract: Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
-        runtime_validation: admission.runtime_validation,
-    });
-    record.expected_ptx.modifiers = tcgen05_st_modifiers(st);
-    record.expected_ptx.operands = tcgen05_st_operands(st);
-    record.summary = format!(
-        "Stores {register_count} {} 32-bit register value{} to tensor memory.",
-        if st.unpack16 { "unpacked" } else { "raw" },
-        if register_count == 1 { "" } else { "s" }
-    );
-    record
-}
-
-fn expand_tcgen05_admission(admission: &Tcgen05Admission) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "tcgen05 runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact tcgen05 admission requires both backend evidence profiles"
-    );
-    let expected = [
-        Tcgen05Operation::Alloc,
-        Tcgen05Operation::Dealloc,
-        Tcgen05Operation::RelinquishAllocPermit,
-        Tcgen05Operation::FenceBeforeThreadSync,
-        Tcgen05Operation::FenceAfterThreadSync,
-        Tcgen05Operation::Commit,
-        Tcgen05Operation::CommitSharedCluster,
-        Tcgen05Operation::MmaWsF16,
-        Tcgen05Operation::MmaF16,
-        Tcgen05Operation::MmaWsBf16,
-        Tcgen05Operation::MmaWsTf32,
-        Tcgen05Operation::CpSmemToTmem,
-        Tcgen05Operation::Ld16x256bX8Pure,
-        Tcgen05Operation::Ld16x256bPure,
-        Tcgen05Operation::LoadWait,
-        Tcgen05Operation::StoreWait,
-        Tcgen05Operation::AllocCg2,
-        Tcgen05Operation::DeallocCg2,
-        Tcgen05Operation::RelinquishAllocPermitCg2,
-        Tcgen05Operation::MmaF16Cg2,
-        Tcgen05Operation::CommitCg2,
-        Tcgen05Operation::CommitSharedClusterCg2,
-        Tcgen05Operation::CommitMulticastCg2,
-        Tcgen05Operation::CpSmemToTmemCg2,
-        Tcgen05Operation::CommitMulticast,
-        Tcgen05Operation::ShiftDown,
-        Tcgen05Operation::ShiftDownCg2,
-    ];
-    let has_control_variants = admission.variants.iter().any(|variant| {
-        matches!(
-            variant.operation,
-            Tcgen05Operation::CommitMulticast
-                | Tcgen05Operation::ShiftDown
-                | Tcgen05Operation::ShiftDownCg2
-        )
-    });
-    if has_control_variants {
-        ensure!(
-            admission
-                .control_llvm_evidence_profile
-                .as_deref()
-                .is_some_and(|profile| !profile.trim().is_empty())
-                && admission
-                    .control_libnvvm_evidence_profile
-                    .as_deref()
-                    .is_some_and(|profile| !profile.trim().is_empty()),
-            "compact tcgen05 control admission requires both backend evidence profiles"
-        );
-    }
-    let expected = if has_control_variants {
-        &expected[..]
-    } else {
-        &expected[..24]
-    };
-    ensure!(
-        admission
-            .variants
-            .iter()
-            .map(|variant| variant.operation)
-            .eq(expected.iter().copied()),
-        "compact tcgen05 admission must list all 24 base operations or all 27 current operations in canonical order"
-    );
-
-    let mut records = admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = tcgen05_recipe(variant.operation);
-            let control = matches!(
-                variant.operation,
-                Tcgen05Operation::CommitMulticast
-                    | Tcgen05Operation::ShiftDown
-                    | Tcgen05Operation::ShiftDownCg2
-            );
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must keep reserved ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: variant.abi_id.clone(),
-                operation_key: recipe.operation_key.into(),
-                family: "tcgen05".into(),
-                source: None,
-                source_record: Some(recipe.source_record.into()),
-                rust_module: "tcgen05".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments: recipe
-                    .rust_arguments
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                rust_result: recipe.rust_result.into(),
-                safe: recipe.safe,
-                must_use: false,
-                safe_allowlist_reason: recipe.safe_reason.map(Into::into),
-                public_rust_path: format!("cuda_intrinsics::tcgen05::{}", recipe.id),
-                compatibility_rust_paths: vec![format!("cuda_device::tcgen05::{}", recipe.id)],
-                dialect_op_type: recipe.dialect_op_type.into(),
-                dialect_op_name: recipe.dialect_op_name.into(),
-                dialect_operands: recipe
-                    .dialect_operands
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                dialect_results: recipe
-                    .dialect_results
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                llvm_symbol: Some(recipe.llvm_symbol.into()),
-                resolved_llvm_symbol: None,
-                llvm_arguments: recipe
-                    .llvm_arguments
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                llvm_results: recipe
-                    .llvm_results
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                pure: false,
-                memory: recipe.memory.into(),
-                convergent: true,
-                execution_scope: recipe.operation.execution_scope().into(),
-                minimum_ptx: "8.6".into(),
-                minimum_sm: None,
-                ptx_result: recipe.rust_result.into(),
-                targets: TCGEN05_LLVM_TARGETS.into(),
-                ptx_isa_version: "8.6".into(),
-                ptx_isa_section: "Tensor Memory tcgen05 instructions".into(),
-                ptx_isa_url:
-                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-memory".into(),
-                lowering: "generated_tcgen05".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: if control {
-                            admission
-                                .control_llvm_evidence_profile
-                                .as_ref()
-                                .expect("validated tcgen05 control LLVM evidence profile")
-                                .clone()
-                        } else {
-                            admission.llvm_evidence_profile.clone()
-                        },
-                        targets: None,
-                        minimum_ptx: Some("8.6".into()),
-                        minimum_sm: None,
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: if control {
-                            admission
-                                .control_libnvvm_evidence_profile
-                                .as_ref()
-                                .expect("validated tcgen05 control libNVVM evidence profile")
-                                .clone()
-                        } else {
-                            admission.libnvvm_evidence_profile.clone()
-                        },
-                        targets: Some(TCGEN05_LIBNVVM_TARGETS.into()),
-                        minimum_ptx: Some("8.6".into()),
-                        minimum_sm: None,
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: Some(Tcgen05 {
-                    operation: recipe.operation,
-                    cp: None,
-                    ld: None,
-                    st: None,
-                    mma: None,
-                    adapter: recipe.adapter,
-                    source_contract: recipe.source_contract,
-                    runtime_validation: admission.runtime_validation,
-                }),
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: "tcgen05".into(),
-                    modifiers: recipe.modifiers,
-                    operands: recipe.operands,
-                },
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect::<Result<Vec<_>>>()?;
-
-    if admission.cp_variants.is_empty() {
-        ensure!(
-            admission.cp_llvm_evidence_profile.is_none()
-                && admission.cp_libnvvm_evidence_profile.is_none(),
-            "tcgen05 copy evidence profiles require admitted copy variants"
-        );
-    } else {
-        ensure!(
-            [
-                Tcgen05MmaBUsage::Discard,
-                Tcgen05MmaBUsage::LastUse,
-                Tcgen05MmaBUsage::Fill,
-                Tcgen05MmaBUsage::Use,
-            ]
-            .map(Tcgen05MmaBUsage::selector_value)
-                == [0, 1, 2, 3],
-            "tcgen05 MMA B-usage selector mapping changed"
-        );
-        ensure!(
-            admission
-                .cp_llvm_evidence_profile
-                .as_deref()
-                .is_some_and(|profile| !profile.trim().is_empty())
-                && admission
-                    .cp_libnvvm_evidence_profile
-                    .as_deref()
-                    .is_some_and(|profile| !profile.trim().is_empty()),
-            "compact tcgen05 copy admission requires both backend evidence profiles"
-        );
-
-        use Tcgen05CpGroup::{Cg1, Cg2};
-        let expected_cp = TCGEN05_CP_MEMBERS
-            .into_iter()
-            .flat_map(|member| [Cg1, Cg2].into_iter().map(move |group| (member, group)))
-            .collect::<Vec<_>>();
-        ensure!(
-            admission
-                .cp_variants
-                .iter()
-                .map(|variant| (variant.member, variant.group))
-                .eq(expected_cp),
-            "compact tcgen05 copy admission must list all 34 variants in canonical order"
-        );
-        for variant in &admission.cp_variants {
-            validate_abi_id(&variant.abi_id)?;
-            let base_id = if variant.group == Cg1 {
-                "tcgen05_cp_smem_to_tmem"
-            } else {
-                "tcgen05_cp_smem_to_tmem_cg2"
-            };
-            let base = records
-                .iter()
-                .find(|record| record.id == base_id)
-                .unwrap()
-                .clone();
-            records.push(materialize_tcgen05_cp_variant(&base, admission, variant));
-        }
-    }
-
-    if admission.ld_variants.is_empty() {
-        ensure!(
-            admission.ld_llvm_evidence_profile.is_none()
-                && admission.ld_libnvvm_evidence_profile.is_none(),
-            "tcgen05 load evidence profiles require admitted load variants"
-        );
-    } else {
-        ensure!(
-            admission
-                .ld_llvm_evidence_profile
-                .as_deref()
-                .is_some_and(|profile| !profile.trim().is_empty())
-                && admission
-                    .ld_libnvvm_evidence_profile
-                    .as_deref()
-                    .is_some_and(|profile| !profile.trim().is_empty()),
-            "compact tcgen05 load admission requires both backend evidence profiles"
-        );
-        let expected_ld = TCGEN05_LD_VARIANTS
-            .into_iter()
-            .flat_map(|(shape, multiplicity)| {
-                [false, true]
-                    .into_iter()
-                    .map(move |pack16| (shape, multiplicity, pack16))
-            })
-            .collect::<Vec<_>>();
-        ensure!(
-            admission
-                .ld_variants
-                .iter()
-                .map(|variant| (variant.shape, variant.multiplicity, variant.pack16))
-                .eq(expected_ld),
-            "compact tcgen05 load admission must list all 58 variants in canonical order"
-        );
-        let base = records
-            .iter()
-            .find(|record| record.id == "tcgen05_ld_16x256b_pure")
-            .expect("closed tcgen05 load base")
-            .clone();
-        let first_load = records.len();
-        for variant in &admission.ld_variants {
-            validate_abi_id(&variant.abi_id)?;
-            records.push(materialize_tcgen05_ld_variant(&base, admission, variant));
-        }
-        for pair in records[first_load..].chunks_exact(2) {
-            let raw = pair[0].tcgen05.as_ref().and_then(|tcgen05| tcgen05.ld);
-            let packed = pair[1].tcgen05.as_ref().and_then(|tcgen05| tcgen05.ld);
-            ensure!(
-                raw.is_some_and(|ld| !ld.pack16)
-                    && packed.is_some_and(|ld| ld.pack16)
-                    && raw.map(|mut ld| {
-                        ld.pack16 = true;
-                        ld
-                    }) == packed
-                    && pair[0].source_record == pair[1].source_record
-                    && pair[0].llvm_symbol == pair[1].llvm_symbol,
-                "tcgen05 load source sharing must pair raw and pack16 leaves"
-            );
-        }
-    }
-
-    if admission.st_variants.is_empty() {
-        ensure!(
-            admission.st_llvm_evidence_profile.is_none()
-                && admission.st_libnvvm_evidence_profile.is_none(),
-            "tcgen05 store evidence profiles require admitted store variants"
-        );
-    } else {
-        ensure!(
-            admission
-                .st_llvm_evidence_profile
-                .as_deref()
-                .is_some_and(|profile| !profile.trim().is_empty())
-                && admission
-                    .st_libnvvm_evidence_profile
-                    .as_deref()
-                    .is_some_and(|profile| !profile.trim().is_empty()),
-            "compact tcgen05 store admission requires both backend evidence profiles"
-        );
-        let expected_st = TCGEN05_ST_VARIANTS
-            .into_iter()
-            .flat_map(|(shape, multiplicity)| {
-                [false, true]
-                    .into_iter()
-                    .map(move |unpack16| (shape, multiplicity, unpack16))
-            })
-            .collect::<Vec<_>>();
-        ensure!(
-            admission
-                .st_variants
-                .iter()
-                .map(|variant| (variant.shape, variant.multiplicity, variant.unpack16))
-                .eq(expected_st),
-            "compact tcgen05 store admission must list all 58 variants in canonical order"
-        );
-        let base = records
-            .iter()
-            .find(|record| record.id == "tcgen05_ld_16x256b_pure")
-            .expect("closed tcgen05 store base")
-            .clone();
-        let first_store = records.len();
-        for variant in &admission.st_variants {
-            validate_abi_id(&variant.abi_id)?;
-            records.push(materialize_tcgen05_st_variant(&base, admission, variant));
-        }
-        for pair in records[first_store..].chunks_exact(2) {
-            let raw = pair[0].tcgen05.as_ref().and_then(|tcgen05| tcgen05.st);
-            let unpacked = pair[1].tcgen05.as_ref().and_then(|tcgen05| tcgen05.st);
-            ensure!(
-                raw.is_some_and(|st| !st.unpack16)
-                    && unpacked.is_some_and(|st| st.unpack16)
-                    && raw.map(|mut st| {
-                        st.unpack16 = true;
-                        st
-                    }) == unpacked
-                    && pair[0].source_record == pair[1].source_record
-                    && pair[0].llvm_symbol == pair[1].llvm_symbol,
-                "tcgen05 store source sharing must pair raw and unpack16 leaves"
-            );
-        }
-    }
-
-    if admission.ld_offset_variants.is_empty() && admission.st_offset_variants.is_empty() {
-        ensure!(
-            admission.offset_llvm_evidence_profile.is_none()
-                && admission.offset_libnvvm_evidence_profile.is_none(),
-            "tcgen05 offset evidence profiles require admitted offset load/store variants"
-        );
-    } else {
-        ensure!(
-            admission
-                .offset_llvm_evidence_profile
-                .as_deref()
-                .is_some_and(|profile| !profile.trim().is_empty())
-                && admission
-                    .offset_libnvvm_evidence_profile
-                    .as_deref()
-                    .is_some_and(|profile| !profile.trim().is_empty()),
-            "compact tcgen05 offset admission requires both backend evidence profiles"
-        );
-        let expected_ld = TCGEN05_OFFSET_LDST_VARIANTS
-            .into_iter()
-            .flat_map(|(shape, multiplicity)| {
-                [false, true]
-                    .into_iter()
-                    .map(move |pack16| (shape, multiplicity, pack16))
-            })
-            .collect::<Vec<_>>();
-        ensure!(
-            admission
-                .ld_offset_variants
-                .iter()
-                .map(|variant| (variant.shape, variant.multiplicity, variant.pack16))
-                .eq(expected_ld),
-            "compact tcgen05 offset load admission must list all 16 variants in canonical order"
-        );
-        let expected_st = TCGEN05_OFFSET_LDST_VARIANTS
-            .into_iter()
-            .flat_map(|(shape, multiplicity)| {
-                [false, true]
-                    .into_iter()
-                    .map(move |unpack16| (shape, multiplicity, unpack16))
-            })
-            .collect::<Vec<_>>();
-        ensure!(
-            admission
-                .st_offset_variants
-                .iter()
-                .map(|variant| (variant.shape, variant.multiplicity, variant.unpack16))
-                .eq(expected_st),
-            "compact tcgen05 offset store admission must list all 16 variants in canonical order"
-        );
-
-        let base = records
-            .iter()
-            .find(|record| record.id == "tcgen05_ld_16x256b_pure")
-            .expect("closed tcgen05 offset load/store base")
-            .clone();
-        let first_load = records.len();
-        for variant in &admission.ld_offset_variants {
-            validate_abi_id(&variant.abi_id)?;
-            records.push(materialize_tcgen05_ld_variant(&base, admission, variant));
-        }
-        for pair in records[first_load..].chunks_exact(2) {
-            let raw = pair[0].tcgen05.as_ref().and_then(|tcgen05| tcgen05.ld);
-            let packed = pair[1].tcgen05.as_ref().and_then(|tcgen05| tcgen05.ld);
-            ensure!(
-                raw.is_some_and(|ld| !ld.pack16)
-                    && packed.is_some_and(|ld| ld.pack16)
-                    && raw.map(|mut ld| {
-                        ld.pack16 = true;
-                        ld
-                    }) == packed
-                    && pair[0].source_record == pair[1].source_record
-                    && pair[0].llvm_symbol == pair[1].llvm_symbol,
-                "tcgen05 offset load source sharing must pair raw and pack16 leaves"
-            );
-        }
-
-        let first_store = records.len();
-        for variant in &admission.st_offset_variants {
-            validate_abi_id(&variant.abi_id)?;
-            records.push(materialize_tcgen05_st_variant(&base, admission, variant));
-        }
-        for pair in records[first_store..].chunks_exact(2) {
-            let raw = pair[0].tcgen05.as_ref().and_then(|tcgen05| tcgen05.st);
-            let unpacked = pair[1].tcgen05.as_ref().and_then(|tcgen05| tcgen05.st);
-            ensure!(
-                raw.is_some_and(|st| !st.unpack16)
-                    && unpacked.is_some_and(|st| st.unpack16)
-                    && raw.map(|mut st| {
-                        st.unpack16 = true;
-                        st
-                    }) == unpacked
-                    && pair[0].source_record == pair[1].source_record
-                    && pair[0].llvm_symbol == pair[1].llvm_symbol,
-                "tcgen05 offset store source sharing must pair raw and unpack16 leaves"
-            );
-        }
-    }
-
-    if admission.mma_variants.is_empty() {
-        ensure!(
-            admission.mma_llvm_evidence_profile.is_none()
-                && admission.mma_libnvvm_evidence_profile.is_none()
-                && admission.mma_llvm_target_contracts.is_empty()
-                && admission.mma_libnvvm_target_contracts.is_empty(),
-            "tcgen05 MMA profiles and target contracts require admitted variants"
-        );
-    } else {
-        ensure!(
-            admission
-                .mma_llvm_evidence_profile
-                .as_deref()
-                .is_some_and(|profile| !profile.trim().is_empty())
-                && admission
-                    .mma_libnvvm_evidence_profile
-                    .as_deref()
-                    .is_some_and(|profile| !profile.trim().is_empty()),
-            "compact tcgen05 MMA admission requires both backend evidence profiles"
-        );
-        let expected_variants = TCGEN05_MMA_FORMS
-            .into_iter()
-            .map(|form| (form, None))
-            .chain(
-                TCGEN05_MMA_ALIASES
-                    .into_iter()
-                    .map(|alias| (Tcgen05MmaForm::WsTensor, Some(alias))),
-            )
-            .chain(
-                TCGEN05_MMA_ALIASES
-                    .into_iter()
-                    .map(|alias| (Tcgen05MmaForm::Shared, Some(alias))),
-            )
-            .collect::<Vec<_>>();
-        ensure!(
-            admission
-                .mma_variants
-                .iter()
-                .map(|variant| (variant.form, variant.alias))
-                .eq(expected_variants),
-            "compact tcgen05 MMA admission must list all 24 APIs in canonical order"
-        );
-        for variant in &admission.mma_variants {
-            validate_abi_id(&variant.abi_id)?;
-        }
-        let expected_llvm = expected_tcgen05_mma_target_contracts(IntrinsicBackend::LlvmNvptx);
-        let expected_libnvvm = expected_tcgen05_mma_target_contracts(IntrinsicBackend::LibNvvm);
-        ensure!(
-            admission.mma_llvm_target_contracts == expected_llvm
-                && admission.mma_libnvvm_target_contracts == expected_libnvvm,
-            "tcgen05 MMA target contracts changed from the reviewed backend matrices"
-        );
-        let llvm_target =
-            resolve_target_contracts("tcgen05 MMA LLVM", &admission.mma_llvm_target_contracts)?;
-        let libnvvm_target = resolve_target_contracts(
-            "tcgen05 MMA libNVVM",
-            &admission.mma_libnvvm_target_contracts,
-        )?;
-        let fixed_selector = [TargetSelectorBinding {
-            name: "kind".into(),
-            value: "f8f6f4".into(),
-        }];
-        let fixed_llvm = resolve_target_contract(
-            "tcgen05 MMA LLVM alias",
-            &fixed_selector,
-            &admission.mma_llvm_target_contracts,
-        )?;
-        let fixed_libnvvm = resolve_target_contract(
-            "tcgen05 MMA libNVVM alias",
-            &fixed_selector,
-            &admission.mma_libnvvm_target_contracts,
-        )?;
-        for variant in &admission.mma_variants {
-            let (llvm, libnvvm) = if variant.alias.is_some() {
-                (&fixed_llvm, &fixed_libnvvm)
-            } else {
-                (&llvm_target, &libnvvm_target)
-            };
-            records.push(materialize_tcgen05_mma_variant(
-                admission, variant, llvm, libnvvm,
-            ));
-        }
-    }
-    Ok(records)
-}
-
-fn validate_tcgen05_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let tcgen05 = policy
-        .tcgen05
-        .as_ref()
-        .with_context(|| format!("{} has no closed tcgen05 contract", policy.id))?;
-    if let Some(mma) = &tcgen05.mma {
-        return validate_tcgen05_mma_policy(policy, declaration, tcgen05, mma);
-    }
-    if let Some(ld) = tcgen05.ld {
-        return validate_tcgen05_ld_policy(policy, declaration, tcgen05, ld);
-    }
-    if let Some(st) = tcgen05.st {
-        return validate_tcgen05_st_policy(policy, declaration, tcgen05, st);
-    }
-    if let Some(cp) = tcgen05.cp {
-        return validate_tcgen05_cp_policy(policy, declaration, tcgen05, cp);
-    }
-    ensure!(
-        !matches!(
-            tcgen05.operation,
-            Tcgen05Operation::Ld | Tcgen05Operation::St | Tcgen05Operation::Mma
-        ),
-        "{} has a tcgen05 load/store/MMA operation without its closed identity",
-        policy.id
-    );
-    let recipe = tcgen05_recipe(tcgen05.operation);
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none()
-            && declaration.source_record == recipe.source_record
-            && declaration.llvm_name == recipe.llvm_symbol,
-        "{} tcgen05 identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "tcgen05"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == recipe.rust_arguments
-            && policy.rust_result == recipe.rust_result
-            && policy.safe == recipe.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.as_deref() == recipe.safe_reason
-            && policy.public_rust_path == format!("cuda_intrinsics::tcgen05::{}", recipe.id)
-            && policy.compatibility_rust_paths == [format!("cuda_device::tcgen05::{}", recipe.id)],
-        "{} tcgen05 Rust API changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == recipe.dialect_operands
-            && policy.dialect_results == recipe.dialect_results
-            && policy.llvm_arguments == recipe.llvm_arguments
-            && policy.llvm_results == recipe.llvm_results
-            && declaration.arguments == recipe.llvm_arguments
-            && declaration.results == recipe.llvm_results
-            && declaration.classes == recipe.imported_classes
-            && declaration.properties == recipe.imported_properties
-            && policy.lowering == "generated_tcgen05",
-        "{} tcgen05 carrier or imported declaration changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == recipe.memory
-            && policy.convergent
-            && policy.execution_scope == recipe.operation.execution_scope()
-            && tcgen05.ld.is_none()
-            && tcgen05.st.is_none()
-            && tcgen05.adapter == recipe.adapter
-            && tcgen05.source_contract == recipe.source_contract
-            && tcgen05.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} tcgen05 semantics changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == "8.6"
-            && policy.minimum_sm.is_none()
-            && policy.targets == TCGEN05_LLVM_TARGETS
-            && policy.ptx_isa_version == "8.6"
-            && policy.ptx_result == recipe.rust_result
-            && policy.expected_ptx.mnemonic == "tcgen05"
-            && policy.expected_ptx.modifiers == recipe.modifiers
-            && policy.expected_ptx.operands == recipe.operands,
-        "{} tcgen05 target or PTX contract changed",
-        policy.id
-    );
-    validate_tcgen05_backend_routes(policy, "tcgen05")?;
-    validate_tcgen05_source_contract(&recipe, declaration)?;
-    ensure_no_other_family_contract(policy, "tcgen05")?;
-    Ok(())
-}
-
-fn validate_tcgen05_mma_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-    tcgen05: &Tcgen05,
-    mma: &Tcgen05Mma,
-) -> Result<()> {
-    let form = mma.form;
-    let alias = mma.alias;
-    ensure!(
-        match alias {
-            Some(alias) => {
-                matches!(form, Tcgen05MmaForm::Shared | Tcgen05MmaForm::WsTensor)
-                    && TCGEN05_MMA_ALIASES.contains(&alias)
-            }
-            None => TCGEN05_MMA_FORMS.contains(&form),
-        },
-        "{} has an unsupported tcgen05 MMA identity",
-        policy.id
-    );
-    let id = tcgen05_mma_public_id(form, alias);
-    let operation_key = tcgen05_mma_operation_key(form, alias);
-    let llvm_arguments = tcgen05_mma_llvm_arguments(form);
-    let expected_fixed = alias.map(|_| Tcgen05MmaFixedSelectors {
-        kind: Tcgen05MmaKind::F8f6f4,
-        b_buffer: 0,
-        b_usage: Tcgen05MmaBUsage::Discard,
-    });
-    ensure!(
-        policy.id == id
-            && policy.operation_key == operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(tcgen05_mma_source_record(form).as_str())
-            && policy.llvm_symbol.as_deref() == Some(tcgen05_mma_llvm_symbol(form).as_str())
-            && policy.resolved_llvm_symbol.is_none()
-            && declaration.source_record == tcgen05_mma_source_record(form)
-            && declaration.llvm_name == tcgen05_mma_llvm_symbol(form),
-        "{} tcgen05 MMA identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "tcgen05"
-            && policy.rust_name == id
-            && policy.rust_arguments == tcgen05_mma_rust_arguments(form, alias)
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::tcgen05::{id}")
-            && policy.compatibility_rust_paths
-                == [if alias.is_some() {
-                    format!("cuda_device::tcgen05::{id}")
-                } else {
-                    format!("cuda_device::tcgen05::__{id}")
-                }],
-        "{} tcgen05 MMA Rust API changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == TCGEN05_MMA_DIALECT_OP_TYPE
-            && policy.dialect_op_name == TCGEN05_MMA_DIALECT_OP_NAME
-            && policy.dialect_operands == tcgen05_mma_dialect_operands(form, alias)
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == llvm_arguments
-            && policy.llvm_results.is_empty()
-            && declaration.arguments == llvm_arguments
-            && declaration.results.is_empty()
-            && declaration.classes
-                == [
-                    "SDPatternOperator",
-                    "Intrinsic",
-                    "DefaultAttrsIntrinsic",
-                    "DefaultAttrsIntrinsicFlags",
-                ]
-            && declaration.properties == tcgen05_mma_imported_properties(form)
-            && policy.lowering == "generated_tcgen05_mma",
-        "{} tcgen05 MMA carrier or imported declaration changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read_write"
-            && policy.convergent
-            && policy.execution_scope == "thread"
-            && tcgen05.operation == Tcgen05Operation::Mma
-            && tcgen05.cp.is_none()
-            && tcgen05.ld.is_none()
-            && tcgen05.st.is_none()
-            && mma.selector_layout == tcgen05_mma_selector_layout(form)
-            && mma.fixed_selectors == expected_fixed
-            && tcgen05.adapter == tcgen05_mma_adapter(form, alias)
-            && tcgen05.source_contract == Tcgen05SourceContract::TablegenSelectionChangesPtx
-            && tcgen05.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} tcgen05 MMA semantics or selector contract changed",
-        policy.id
-    );
-
-    let expected_llvm_contracts =
-        expected_tcgen05_mma_target_contracts(IntrinsicBackend::LlvmNvptx);
-    let expected_libnvvm_contracts =
-        expected_tcgen05_mma_target_contracts(IntrinsicBackend::LibNvvm);
-    let selected = [TargetSelectorBinding {
-        name: "kind".into(),
-        value: "f8f6f4".into(),
-    }];
-    let expected_llvm = if alias.is_some() {
-        resolve_target_contract(
-            "tcgen05 MMA LLVM alias",
-            &selected,
-            &expected_llvm_contracts,
-        )?
-    } else {
-        resolve_target_contracts("tcgen05 MMA LLVM", &expected_llvm_contracts)?
-    };
-    let expected_libnvvm = if alias.is_some() {
-        resolve_target_contract(
-            "tcgen05 MMA libNVVM alias",
-            &selected,
-            &expected_libnvvm_contracts,
-        )?
-    } else {
-        resolve_target_contracts("tcgen05 MMA libNVVM", &expected_libnvvm_contracts)?
-    };
-    ensure!(
-        mma.llvm_target == expected_llvm
-            && mma.libnvvm_target == expected_libnvvm
-            && policy.minimum_ptx == "8.6"
-            && policy.minimum_sm.is_none()
-            && policy.targets == TCGEN05_LLVM_TARGETS
-            && policy.ptx_result == "()"
-            && policy.ptx_isa_version == "8.6"
-            && policy.expected_ptx == tcgen05_mma_expected_ptx(form, alias),
-        "{} tcgen05 MMA target or PTX contract changed",
-        policy.id
-    );
-    let backend_pairs = policy
-        .backend_lowerings
-        .iter()
-        .map(|route| (route.backend, route.mechanism))
-        .collect::<BTreeSet<_>>();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ])
-            && policy.backend_lowerings.iter().all(|route| {
-                !route.evidence_profile.trim().is_empty()
-                    && route.targets.is_none()
-                    && route.minimum_ptx.is_none()
-                    && route.minimum_sm.is_none()
-            }),
-        "{} tcgen05 MMA backend routes changed",
-        policy.id
-    );
-
-    let expected_all = tcgen05_mma_all_selection_asms(form);
-    let expected_valid = if alias.is_some() {
-        BTreeSet::from([if tcgen05_mma_is_ws(form) {
-            tcgen05_mma_selection_asm(
-                form,
-                Tcgen05MmaKind::F8f6f4,
-                1,
-                None,
-                Some(0),
-                Some(Tcgen05MmaBUsage::Discard),
-            )
-        } else {
-            tcgen05_mma_selection_asm(form, Tcgen05MmaKind::F8f6f4, 1, Some("discard"), None, None)
-        }])
-    } else {
-        tcgen05_mma_valid_selection_asms(form)
-    };
-    let mut source_records = BTreeSet::new();
-    let actual_all = declaration
-        .selections
-        .iter()
-        .map(|selection| {
-            ensure!(
-                !selection.source_record.is_empty()
-                    && source_records.insert(selection.source_record.as_str())
-                    && selection.constraints.is_empty(),
-                "{} tcgen05 MMA selection provenance changed",
-                policy.id
-            );
-            let predicate = if selection.asm.contains(".kind::i8.") {
-                "Subtarget->hasTcgen05MMAI8Kind()"
-            } else {
-                "Subtarget->hasTcgen05InstSupport()"
-            };
-            ensure!(
-                selection.predicates == [predicate],
-                "{} tcgen05 MMA selection predicate changed",
-                policy.id
-            );
-            Ok(selection.asm.clone())
-        })
-        .collect::<Result<BTreeSet<_>>>()?;
-    ensure!(
-        actual_all == expected_all
-            && declaration.selections.len() == expected_all.len()
-            && expected_valid.is_subset(&expected_all)
-            && expected_valid.len()
-                == if alias.is_some() {
-                    1
-                } else if tcgen05_mma_is_ws(form) {
-                    64
-                } else if tcgen05_mma_is_ashift(form) {
-                    16
-                } else {
-                    32
-                },
-        "{} tcgen05 MMA selection matrix changed",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "tcgen05 MMA")?;
-    Ok(())
-}
-
-fn validate_tcgen05_ld_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-    tcgen05: &Tcgen05,
-    ld: Tcgen05Ld,
-) -> Result<()> {
-    let has_half_split_offset = ld.shape == Tcgen05LdShape::M16x32bx2;
-    let variants: &[(Tcgen05LdShape, Tcgen05LdMultiplicity)] = if has_half_split_offset {
-        &TCGEN05_OFFSET_LDST_VARIANTS
-    } else {
-        &TCGEN05_LD_VARIANTS
-    };
-    ensure!(
-        variants.contains(&(ld.shape, ld.multiplicity)),
-        "{} has an unsupported tcgen05 load identity",
-        policy.id
-    );
-    let id = tcgen05_ld_id(ld);
-    let source_record = tcgen05_ld_source_record(ld);
-    let llvm_symbol = tcgen05_ld_llvm_symbol(ld);
-    let rust_result = tcgen05_ld_rust_result(ld);
-    let llvm_result = tcgen05_ld_llvm_result(ld);
-    let register_count = tcgen05_ld_register_count(ld);
-    let mode = if ld.pack16 { "pack16" } else { "raw" };
-    let expected_rust_arguments = if has_half_split_offset {
-        vec!["u32", "i64"]
-    } else {
-        vec!["u32"]
-    };
-    let compatibility_name = if has_half_split_offset {
-        format!("__{id}")
-    } else {
-        id.clone()
-    };
-    let expected_dialect_operands = if has_half_split_offset {
-        vec!["i32", "i64"]
-    } else {
-        vec!["i32"]
-    };
-    let expected_llvm_arguments = if has_half_split_offset {
-        vec!["tmem_ptr", "i64", "i1"]
-    } else {
-        vec!["tmem_ptr", "i1"]
-    };
-    let expected_properties = if has_half_split_offset {
-        vec![
-            "ImmArg<arg1>",
-            "ImmArg<arg2>",
-            "IntrArgMemOnly",
-            "IntrConvergent",
-            "NoCapture<arg0>",
-        ]
-    } else {
-        vec![
-            "ImmArg<arg1>",
-            "IntrArgMemOnly",
-            "IntrConvergent",
-            "NoCapture<arg0>",
-        ]
-    };
-    ensure!(
-        policy.id == id
-            && policy.operation_key
-                == format!(
-                    "tcgen05.ld.{}.{}.{}",
-                    tcgen05_ld_shape_name(ld.shape),
-                    tcgen05_ld_multiplicity_name(ld.multiplicity),
-                    mode
-                )
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(source_record.as_str())
-            && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none()
-            && declaration.source_record == source_record
-            && declaration.llvm_name == llvm_symbol,
-        "{} tcgen05 load identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "tcgen05"
-            && policy.rust_name == id
-            && policy.rust_arguments == expected_rust_arguments
-            && policy.rust_result == rust_result
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::tcgen05::{id}")
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::tcgen05::{compatibility_name}")],
-        "{} tcgen05 load Rust API changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == tcgen05_ld_op_type(ld)
-            && policy.dialect_op_name == format!("nvvm.{id}")
-            && policy.dialect_operands == expected_dialect_operands
-            && policy.dialect_results == vec!["i32"; register_count]
-            && policy.llvm_arguments == expected_llvm_arguments
-            && policy.llvm_results == [llvm_result.as_str()]
-            && declaration.arguments == expected_llvm_arguments
-            && declaration.results == [llvm_result.as_str()]
-            && declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_TCGEN05_LD"]
-            && declaration.properties == expected_properties
-            && declaration.selections.is_empty()
-            && policy.lowering == "generated_tcgen05",
-        "{} tcgen05 load carrier or imported declaration changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read"
-            && policy.convergent
-            && policy.execution_scope == Tcgen05Operation::Ld.execution_scope()
-            && tcgen05.operation == Tcgen05Operation::Ld
-            && tcgen05.cp.is_none()
-            && tcgen05.ld == Some(ld)
-            && tcgen05.st.is_none()
-            && tcgen05.adapter
-                == if has_half_split_offset {
-                    Tcgen05Adapter::TmemHalfSplitOffsetInjectPack16ToU32Registers
-                } else {
-                    Tcgen05Adapter::TmemInjectPack16ToU32Registers
-                }
-            && tcgen05.source_contract == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
-            && tcgen05.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} tcgen05 load semantics changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == "8.6"
-            && policy.minimum_sm.is_none()
-            && policy.targets == TCGEN05_LLVM_TARGETS
-            && policy.ptx_isa_version == "8.6"
-            && policy.ptx_result == rust_result
-            && policy.expected_ptx.mnemonic == "tcgen05"
-            && policy.expected_ptx.modifiers == tcgen05_ld_modifiers(ld)
-            && policy.expected_ptx.operands == tcgen05_ld_operands(ld),
-        "{} tcgen05 load target or PTX contract changed",
-        policy.id
-    );
-    validate_tcgen05_backend_routes(policy, "tcgen05 load")?;
-    ensure_no_other_family_contract(policy, "tcgen05 load")?;
-    Ok(())
-}
-
-fn validate_tcgen05_st_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-    tcgen05: &Tcgen05,
-    st: Tcgen05St,
-) -> Result<()> {
-    let has_half_split_offset = st.shape == Tcgen05LdShape::M16x32bx2;
-    let variants: &[(Tcgen05LdShape, Tcgen05LdMultiplicity)] = if has_half_split_offset {
-        &TCGEN05_OFFSET_LDST_VARIANTS
-    } else {
-        &TCGEN05_ST_VARIANTS
-    };
-    ensure!(
-        variants.contains(&(st.shape, st.multiplicity)),
-        "{} has an unsupported tcgen05 store identity",
-        policy.id
-    );
-    let id = tcgen05_st_id(st);
-    let source_record = tcgen05_st_source_record(st);
-    let llvm_symbol = tcgen05_st_llvm_symbol(st);
-    let rust_data = tcgen05_st_rust_data(st);
-    let llvm_data = tcgen05_st_llvm_data(st);
-    let register_count = tcgen05_st_register_count(st);
-    let mode = if st.unpack16 { "unpack16" } else { "raw" };
-    let expected_rust_arguments = if has_half_split_offset {
-        vec!["u32", "i64", rust_data.as_str()]
-    } else {
-        vec!["u32", rust_data.as_str()]
-    };
-    let compatibility_name = if has_half_split_offset {
-        format!("__{id}")
-    } else {
-        id.clone()
-    };
-    let expected_dialect_operands = std::iter::once("i32".to_owned())
-        .chain(has_half_split_offset.then(|| "i64".to_owned()))
-        .chain(std::iter::repeat_n("i32".to_owned(), register_count))
-        .collect::<Vec<_>>();
-    let expected_llvm_arguments = if has_half_split_offset {
-        vec!["tmem_ptr", "i64", llvm_data.as_str(), "i1"]
-    } else {
-        vec!["tmem_ptr", llvm_data.as_str(), "i1"]
-    };
-    let expected_properties = if has_half_split_offset {
-        vec![
-            "ImmArg<arg1>",
-            "ImmArg<arg3>",
-            "IntrArgMemOnly",
-            "IntrConvergent",
-            "NoCapture<arg0>",
-        ]
-    } else {
-        vec![
-            "ImmArg<arg2>",
-            "IntrArgMemOnly",
-            "IntrConvergent",
-            "NoCapture<arg0>",
-        ]
-    };
-    ensure!(
-        policy.id == id
-            && policy.operation_key
-                == format!(
-                    "tcgen05.st.{}.{}.{}",
-                    tcgen05_ld_shape_name(st.shape),
-                    tcgen05_ld_multiplicity_name(st.multiplicity),
-                    mode
-                )
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(source_record.as_str())
-            && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none()
-            && declaration.source_record == source_record
-            && declaration.llvm_name == llvm_symbol,
-        "{} tcgen05 store identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "tcgen05"
-            && policy.rust_name == id
-            && policy.rust_arguments == expected_rust_arguments
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::tcgen05::{id}")
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::tcgen05::{compatibility_name}")],
-        "{} tcgen05 store Rust API changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == tcgen05_st_op_type(st)
-            && policy.dialect_op_name == format!("nvvm.{id}")
-            && policy.dialect_operands == expected_dialect_operands
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == expected_llvm_arguments
-            && policy.llvm_results.is_empty()
-            && declaration.arguments == expected_llvm_arguments
-            && declaration.results.is_empty()
-            && declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_TCGEN05_ST"]
-            && declaration.properties == expected_properties
-            && declaration.selections.is_empty()
-            && policy.lowering == "generated_tcgen05",
-        "{} tcgen05 store carrier or imported declaration changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "write"
-            && policy.convergent
-            && policy.execution_scope == Tcgen05Operation::St.execution_scope()
-            && tcgen05.operation == Tcgen05Operation::St
-            && tcgen05.cp.is_none()
-            && tcgen05.ld.is_none()
-            && tcgen05.st == Some(st)
-            && tcgen05.adapter
-                == if has_half_split_offset {
-                    Tcgen05Adapter::TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid
-                } else {
-                    Tcgen05Adapter::TmemU32RegistersInjectUnpack16ToVoid
-                }
-            && tcgen05.source_contract == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
-            && tcgen05.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} tcgen05 store semantics changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == "8.6"
-            && policy.minimum_sm.is_none()
-            && policy.targets == TCGEN05_LLVM_TARGETS
-            && policy.ptx_isa_version == "8.6"
-            && policy.ptx_result == "()"
-            && policy.expected_ptx.mnemonic == "tcgen05"
-            && policy.expected_ptx.modifiers == tcgen05_st_modifiers(st)
-            && policy.expected_ptx.operands == tcgen05_st_operands(st),
-        "{} tcgen05 store target or PTX contract changed",
-        policy.id
-    );
-    validate_tcgen05_backend_routes(policy, "tcgen05 store")?;
-    ensure_no_other_family_contract(policy, "tcgen05 store")?;
-    Ok(())
-}
-
-fn validate_tcgen05_cp_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-    tcgen05: &Tcgen05,
-    cp: Tcgen05Cp,
-) -> Result<()> {
-    ensure!(
-        TCGEN05_CP_MEMBERS.contains(&cp.member),
-        "{} has an unsupported tcgen05 copy identity",
-        policy.id
-    );
-    let recipe = tcgen05_cp_member_recipe(cp.member);
-    let group = match cp.group {
-        Tcgen05CpGroup::Cg1 => 1,
-        Tcgen05CpGroup::Cg2 => 2,
-    };
-    let group_suffix = if group == 1 { "" } else { "_cg2" };
-    let id_suffix = recipe.llvm_suffix.replace('.', "_");
-    let id = format!("tcgen05_cp_{id_suffix}{group_suffix}");
-    let operation = if group == 1 {
-        Tcgen05Operation::CpSmemToTmem
-    } else {
-        Tcgen05Operation::CpSmemToTmemCg2
-    };
-    let op_type = format!(
-        "Tcgen05Cp{}{}Op",
-        recipe.op_suffix,
-        if group == 1 { "" } else { "Cg2" }
-    );
-    let source_record = format!("int_nvvm_tcgen05_cp_{}_cg{group}", id_suffix);
-    let llvm_symbol = format!("llvm.nvvm.tcgen05.cp.{}.cg{group}", recipe.llvm_suffix);
-    let modifiers = std::iter::once("cp".into())
-        .chain(std::iter::once(format!("cta_group::{group}")))
-        .chain(recipe.ptx_suffix.split('.').map(Into::into))
-        .collect::<Vec<String>>();
-    ensure!(
-        policy.id == id
-            && policy.operation_key == format!("tcgen05.cp.{}.cg{group}", recipe.llvm_suffix)
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(source_record.as_str())
-            && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none()
-            && declaration.source_record == source_record
-            && declaration.llvm_name == llvm_symbol,
-        "{} tcgen05 copy identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "tcgen05"
-            && policy.rust_name == id
-            && policy.rust_arguments == ["u32", "u64"]
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::tcgen05::{id}")
-            && policy.compatibility_rust_paths == [format!("cuda_device::tcgen05::{id}")],
-        "{} tcgen05 copy Rust API changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == op_type
-            && policy.dialect_op_name == format!("nvvm.{id}")
-            && policy.dialect_operands == ["i32", "i64"]
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == ["tmem_ptr", "i64"]
-            && policy.llvm_results.is_empty()
-            && declaration.arguments == ["tmem_ptr", "i64"]
-            && declaration.results.is_empty()
-            && declaration.classes == ["SDPatternOperator", "Intrinsic"]
-            && declaration.properties
-                == [
-                    "IntrConvergent",
-                    "IntrInaccessibleMemOrArgMemOnly",
-                    "NoCapture<arg0>",
-                ]
-            && policy.lowering == "generated_tcgen05",
-        "{} tcgen05 copy carrier or declaration changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read_write"
-            && policy.convergent
-            && policy.execution_scope == "thread"
-            && tcgen05.operation == operation
-            && tcgen05.ld.is_none()
-            && tcgen05.st.is_none()
-            && tcgen05.adapter == Tcgen05Adapter::TmemDescriptorToVoid
-            && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
-            && tcgen05.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} tcgen05 copy semantics changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == "8.6"
-            && policy.minimum_sm.is_none()
-            && policy.targets == TCGEN05_LLVM_TARGETS
-            && policy.ptx_isa_version == "8.6"
-            && policy.ptx_result == "()"
-            && policy.expected_ptx.mnemonic == "tcgen05"
-            && policy.expected_ptx.modifiers == modifiers
-            && policy.expected_ptx.operands == [OperandPattern::Address, OperandPattern::Register],
-        "{} tcgen05 copy target or PTX contract changed",
-        policy.id
-    );
-    validate_tcgen05_backend_routes(policy, "tcgen05 copy")?;
-    ensure!(
-        declaration.selections.len() == 1,
-        "{} must keep one exact tcgen05 copy selection",
-        policy.id
-    );
-    let selection = &declaration.selections[0];
-    ensure!(
-        selection.source_record == format!("TCGEN05_CP_{}_cg{group}", recipe.selection_stem)
-            && selection.asm
-                == format!(
-                    "tcgen05.cp.cta_group::{group}.{} \t[$tmem_addr], $sdesc;",
-                    recipe.ptx_suffix
-                )
-            && selection.predicates == ["Subtarget->hasTcgen05InstSupport()"]
-            && selection.constraints.is_empty(),
-        "{} exact tcgen05 copy selection changed",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "tcgen05 copy")?;
-    Ok(())
-}
-
-fn validate_tcgen05_backend_routes(policy: &OverlayIntrinsic, family: &str) -> Result<()> {
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && policy.backend_lowerings[0].backend == IntrinsicBackend::LlvmNvptx
-            && policy.backend_lowerings[1].backend == IntrinsicBackend::LibNvvm
-            && policy.backend_lowerings[0].targets.is_none()
-            && policy.backend_lowerings[1].targets.as_deref() == Some(TCGEN05_LIBNVVM_TARGETS)
-            && policy.backend_lowerings.iter().all(|route| {
-                route.mechanism == BackendLoweringMechanism::InlinePtx
-                    && route.minimum_ptx.as_deref() == Some("8.6")
-                    && route.minimum_sm.is_none()
-                    && !route.evidence_profile.trim().is_empty()
-            }),
-        "{} {family} backend route changed",
-        policy.id
-    );
-    Ok(())
-}
-
-fn validate_tcgen05_source_contract(
-    recipe: &Tcgen05Recipe,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    match recipe.source_contract {
-        Tcgen05SourceContract::ExactTablegenSelection => {
-            ensure!(
-                declaration.selections.len() == 1,
-                "{} must keep one exact tcgen05 selection",
-                recipe.id
-            );
-            let selection = &declaration.selections[0];
-            let expected_predicate = if matches!(
-                recipe.operation,
-                Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2
-            ) {
-                "Subtarget->hasTcgen05ShiftSupport()"
-            } else {
-                "Subtarget->hasTcgen05InstSupport()"
-            };
-            ensure!(
-                recipe.selection_record == Some(selection.source_record.as_str())
-                    && recipe.selection_asm == Some(selection.asm.as_str())
-                    && selection.predicates == [expected_predicate]
-                    && selection.constraints.is_empty(),
-                "{} exact tcgen05 selection changed",
-                recipe.id
-            );
-        }
-        Tcgen05SourceContract::TablegenSelectionChangesPtx
-            if matches!(
-                recipe.operation,
-                Tcgen05Operation::Commit | Tcgen05Operation::CommitCg2
-            ) =>
-        {
-            ensure!(
-                declaration.selections.len() == 1,
-                "{} must keep one canonical commit selection",
-                recipe.id
-            );
-            let selection = &declaration.selections[0];
-            ensure!(
-                recipe.selection_record == Some(selection.source_record.as_str())
-                    && recipe.selection_asm == Some(selection.asm.as_str())
-                    && selection.predicates == ["Subtarget->hasTcgen05InstSupport()"]
-                    && selection.constraints.is_empty()
-                    && !recipe.operands.is_empty(),
-                "{} canonical commit selection changed",
-                recipe.id
-            );
-        }
-        Tcgen05SourceContract::TablegenSelectionChangesPtx => {
-            ensure!(
-                declaration.selections.len() == 64,
-                "{} must keep the 64 collector selections",
-                recipe.id
-            );
-            let actual = declaration
-                .selections
-                .iter()
-                .map(|selection| {
-                    ensure!(
-                        selection.constraints.is_empty(),
-                        "{} collector selection gained constraints",
-                        recipe.id
-                    );
-                    let predicate = if selection.asm.contains(".kind::i8.") {
-                        "Subtarget->hasTcgen05MMAI8Kind()"
-                    } else {
-                        "Subtarget->hasTcgen05InstSupport()"
-                    };
-                    ensure!(
-                        selection.predicates == [predicate],
-                        "{} collector predicate changed",
-                        recipe.id
-                    );
-                    Ok(selection.asm.clone())
-                })
-                .collect::<Result<BTreeSet<_>>>()?;
-            let expected = ["f16", "tf32", "f8f6f4", "i8"]
-                .into_iter()
-                .flat_map(|kind| {
-                    ["b0", "b1", "b2", "b3"].into_iter().flat_map(move |collector| {
-                        ["discard", "fill", "use", "lastuse"].into_iter().map(move |action| {
-                            format!("tcgen05.mma.ws.cta_group::1.kind::{kind}.collector::{collector}::{action} [$dtmem], [$a], $b, $idesc, $enable_inp_d;")
-                        })
-                    })
-                })
-                .collect::<BTreeSet<_>>();
-            ensure!(
-                actual == expected,
-                "{} collector selection matrix changed",
-                recipe.id
-            );
-        }
-        Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection => ensure!(
-            declaration.selections.is_empty(),
-            "{} unexpectedly gained a TableGen selection; review the backend route",
-            recipe.id
-        ),
-    }
-    Ok(())
-}
-
-fn tma_imported_properties(operation: TmaOperation) -> Vec<String> {
-    assert_ne!(operation, TmaOperation::Reduce);
-    let dimensions = operation.dimensions();
-    if matches!(
-        operation,
-        TmaOperation::G2sTile1d
-            | TmaOperation::G2sTile2d
-            | TmaOperation::G2sTile2dMulticast
-            | TmaOperation::G2sTile2dMulticastCg2
-            | TmaOperation::G2sTile3d
-            | TmaOperation::G2sTile4d
-            | TmaOperation::G2sTile5d
-    ) {
-        let dimensions = dimensions.unwrap();
-        let mut properties = vec![
-            format!("ImmArg<arg{}>", dimensions + 5),
-            format!("ImmArg<arg{}>", dimensions + 6),
-            format!("ImmArg<arg{}>", dimensions + 7),
-            "IntrConvergent".into(),
-            format!("Range<arg{},0,3>", dimensions + 7),
-            "ReadOnly<arg2>".into(),
-            "WriteOnly<arg0>".into(),
-        ];
-        properties.sort();
-        return properties;
-    }
-    if matches!(
-        operation,
-        TmaOperation::S2gTile1d
-            | TmaOperation::S2gTile2d
-            | TmaOperation::S2gTile3d
-            | TmaOperation::S2gTile4d
-            | TmaOperation::S2gTile5d
-    ) {
-        return vec![
-            format!("ImmArg<arg{}>", dimensions.unwrap() + 3),
-            "IntrConvergent".into(),
-            "ReadOnly<arg0>".into(),
-            "ReadOnly<arg1>".into(),
-        ];
-    }
-    if operation == TmaOperation::CommitGroup {
-        return vec![];
-    }
-    if matches!(
-        operation,
-        TmaOperation::WaitGroup | TmaOperation::WaitGroupRead
-    ) {
-        return vec!["ImmArg<arg0>".into()];
-    }
-    if operation == TmaOperation::PrefetchTensorMap {
-        return vec![
-            "IntrArgMemOnly".into(),
-            "NoCapture<arg0>".into(),
-            "ReadOnly<arg0>".into(),
-        ];
-    }
-    if let Some(coordinate_count) = operation.prefetch_coordinate_count() {
-        return vec![
-            format!("ImmArg<arg{}>", coordinate_count + 2),
-            "IntrConvergent".into(),
-            "ReadOnly<arg0>".into(),
-        ];
-    }
-    if matches!(
-        operation,
-        TmaOperation::FenceProxyTensorMapAcquireCluster
-            | TmaOperation::FenceProxyTensorMapAcquireCta
-            | TmaOperation::FenceProxyTensorMapAcquireGpu
-            | TmaOperation::FenceProxyTensorMapAcquireSystem
-    ) {
-        return vec![
-            "ImmArg<arg1>".into(),
-            "IntrArgMemOnly".into(),
-            "IntrNoCallback".into(),
-            "Range<arg1,128,129>".into(),
-        ];
-    }
-    if matches!(
-        operation,
-        TmaOperation::FenceProxyTensorMapReleaseCluster
-            | TmaOperation::FenceProxyTensorMapReleaseCta
-            | TmaOperation::FenceProxyTensorMapReleaseGpu
-            | TmaOperation::FenceProxyTensorMapReleaseSystem
-    ) {
-        return vec!["IntrNoCallback".into()];
-    }
-
-    let mut properties = vec![
-        "IntrArgMemOnly".into(),
-        "IntrWriteMem".into(),
-        "NoCapture<arg0>".into(),
-    ];
-    match operation {
-        TmaOperation::ReplaceBoxDim
-        | TmaOperation::ReplaceElementStride
-        | TmaOperation::ReplaceGlobalDim
-        | TmaOperation::ReplaceGlobalStride => {
-            properties.push("ImmArg<arg1>".into());
-        }
-        TmaOperation::ReplaceElementType => {
-            properties.extend([
-                "ArgInfo<arg1>".into(),
-                "ImmArg<arg1>".into(),
-                "Range<arg1,0,16>".into(),
-            ]);
-        }
-        TmaOperation::ReplaceFillMode => {
-            properties.extend([
-                "ArgInfo<arg1>".into(),
-                "ImmArg<arg1>".into(),
-                "Range<arg1,0,2>".into(),
-            ]);
-        }
-        TmaOperation::ReplaceInterleaveLayout => {
-            properties.extend([
-                "ArgInfo<arg1>".into(),
-                "ImmArg<arg1>".into(),
-                "Range<arg1,0,3>".into(),
-            ]);
-        }
-        TmaOperation::ReplaceSwizzleAtomicity => {
-            properties.extend([
-                "ArgInfo<arg1>".into(),
-                "ImmArg<arg1>".into(),
-                "Range<arg1,0,4>".into(),
-            ]);
-        }
-        TmaOperation::ReplaceSwizzleMode => {
-            properties.extend([
-                "ArgInfo<arg1>".into(),
-                "ImmArg<arg1>".into(),
-                "Range<arg1,0,5>".into(),
-            ]);
-        }
-        TmaOperation::ReplaceGlobalAddress | TmaOperation::ReplaceRank => {}
-        _ => unreachable!("closed TMA operation property contract"),
-    }
-    properties.sort();
-    properties
-}
-
-fn tma_reduction_imported_properties(dimensions: usize) -> Vec<String> {
-    vec![
-        format!("ImmArg<arg{}>", dimensions + 3),
-        "IntrConvergent".into(),
-        "ReadOnly<arg0>".into(),
-        "ReadOnly<arg1>".into(),
-    ]
-}
-
-fn validate_sync_policy(policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic) -> Result<()> {
-    if let Some(scope) = threadfence_scope_for_id(&policy.id) {
-        return validate_threadfence_policy(policy, declaration, scope);
-    }
-    ensure!(
-        policy.id == "sync_threads"
-            && policy.abi_id == "i0034"
-            && policy.operation_key == "synchronization.cta.barrier.aligned.all"
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some("int_nvvm_barrier_cta_sync_aligned_all")
-            && policy.llvm_symbol.as_deref() == Some("llvm.nvvm.barrier.cta.sync.aligned.all")
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} sync identity does not match the closed sync_threads recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "thread"
-            && policy.rust_name == "sync_threads"
-            && policy.rust_arguments.is_empty()
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == "cuda_intrinsics::thread::sync_threads"
-            && policy.compatibility_rust_paths
-                == [
-                    "cuda_device::thread::sync_threads",
-                    "cuda_device::sync_threads",
-                ],
-        "{} must preserve the unsafe sync_threads raw API and both cuda-device compatibility paths",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == "Barrier0Op"
-            && policy.dialect_op_name == "nvvm.barrier0"
-            && policy.dialect_operands.is_empty()
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == ["i32"]
-            && policy.llvm_results.is_empty()
-            && policy.lowering == "generated_sync_threads",
-        "{} is outside the fixed-zero sync_threads lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read_write"
-            && policy.convergent
-            && policy.execution_scope == "cta"
-            && policy.minimum_ptx == "1.0"
-            && policy.minimum_sm.is_none()
-            && policy.ptx_result == "()"
-            && policy.targets == "all",
-        "{} sync effects or native target floor disagree with the closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier",
-        "{} sync PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.properties == ["IntrConvergent", "IntrNoCallback"],
-        "{} sync properties disagree with the imported LLVM declaration",
-        policy.id
-    );
-    ensure!(
-        policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with sync",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "bar"
-            && policy.expected_ptx.modifiers == ["sync"]
-            && policy.expected_ptx.operands == [OperandPattern::Exact { value: "0".into() }],
-        "{} expected PTX does not match literal bar.sync 0",
-        policy.id
-    );
-
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ]),
-        "{} must define exactly the reviewed LLVM typed and libNVVM inline-PTX routes",
-        policy.id
-    );
-    for lowering in &policy.backend_lowerings {
-        let floor_matches = match lowering.backend {
-            IntrinsicBackend::LlvmNvptx => {
-                lowering.mechanism == BackendLoweringMechanism::TypedNvvm
-                    && lowering.minimum_ptx.as_deref() == Some("3.2")
-                    && lowering.minimum_sm.as_deref() == Some("sm_20")
-            }
-            IntrinsicBackend::LibNvvm => {
-                lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    && lowering.minimum_ptx.is_none()
-                    && lowering.minimum_sm.as_deref() == Some("sm_75")
-            }
-        };
-        ensure!(
-            floor_matches && !lowering.evidence_profile.trim().is_empty(),
-            "{} backend {:?} does not carry its reviewed sync profile floor",
-            policy.id,
-            lowering.backend
-        );
-    }
-    Ok(())
-}
-
-fn validate_vote_policy(policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic) -> Result<()> {
-    let vote = policy
-        .vote
-        .as_ref()
-        .with_context(|| format!("{} has no closed vote contract", policy.id))?;
-    let recipe = vote_recipe(vote.mode);
-    ensure!(
-        vote.participation
-            == VoteParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask
-            && vote.legacy_pre_sm70
-                == PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive
-            && vote.adapter == VoteAdapter::DirectMaskPredicate
-            && vote.mask_encoding == MaskEncoding::RegisterOrImmediate,
-        "{} requests an unsupported vote participation, pre-sm70 rule, adapter, or mask encoding",
-        policy.id
-    );
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} vote identity does not match its closed mode recipe",
-        policy.id
-    );
-    let expected_compatibility_paths: Vec<String> = if recipe.has_compatibility_path {
-        vec![format!("cuda_device::warp::{}", recipe.rust_name)]
-    } else {
-        vec![]
-    };
-    ensure!(
-        policy.rust_module == "warp"
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == ["u32", "bool"]
-            && policy.rust_result == recipe.rust_result
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::warp::{}", recipe.rust_name)
-            && policy.compatibility_rust_paths == expected_compatibility_paths,
-        "{} must preserve its unsafe must-use vote raw API and reviewed compatibility path",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == ["i32", "i1"]
-            && policy.dialect_results == [recipe.llvm_result]
-            && policy.llvm_arguments == ["i32", "i1"]
-            && policy.llvm_results == [recipe.llvm_result]
-            && policy.lowering == "generated_vote",
-        "{} is outside the closed two-operand vote lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "inaccessible_read_write"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == "6.0"
-            && policy.minimum_sm.as_deref() == Some("sm_30")
-            && policy.ptx_result == recipe.rust_result
-            && policy.targets == "all",
-        "{} vote effects, carrier, or target floor disagree with its mode recipe",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == "9.7.14.10 Warp Vote Instructions: vote.sync"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-vote-sync",
-        "{} vote PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.properties
-            == [
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-        "{} vote memory and convergence effects disagree with the imported declaration",
-        policy.id
-    );
-    ensure!(
-        policy.backend_lowerings.is_empty()
-            && policy.packed_atomic.is_none()
-            && policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.redux.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with vote",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "vote"
-            && policy.expected_ptx.modifiers == ["sync", recipe.ptx_mode, recipe.ptx_type]
-            && policy.expected_ptx.operands
-                == [
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                    OperandPattern::RegisterOrImmediate,
-                ],
-        "{} expected PTX does not match its closed vote mode recipe",
-        policy.id
-    );
-
-    let expected_selection_records =
-        BTreeSet::from([recipe.immediate_selection, recipe.register_selection]);
-    let actual_selection_records: BTreeSet<_> = declaration
-        .selections
-        .iter()
-        .map(|selection| selection.source_record.as_str())
-        .collect();
-    ensure!(
-        declaration.selections.len() == 2 && actual_selection_records == expected_selection_records,
-        "{} vote declaration must contain exactly its immediate/register selection pair",
-        policy.id
-    );
-    let expected_asm = format!(
-        "vote.sync.{}.{} \t$dest, $pred, $mask;",
-        recipe.ptx_mode, recipe.ptx_type
-    );
-    for selection in &declaration.selections {
-        ensure!(
-            selection.asm == expected_asm
-                && selection.predicates
-                    == [
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30",
-                    ]
-                && selection.constraints.is_empty(),
-            "{} vote immediate/register selections disagree on PTX shape, target predicates, or constraints",
-            policy.id
-        );
-    }
-    Ok(())
-}
-
-struct VoteRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    rust_name: &'static str,
-    rust_result: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    llvm_result: &'static str,
-    ptx_mode: &'static str,
-    ptx_type: &'static str,
-    immediate_selection: &'static str,
-    register_selection: &'static str,
-    has_compatibility_path: bool,
-}
-
-fn vote_recipe(mode: VoteMode) -> VoteRecipe {
-    match mode {
-        VoteMode::All => VoteRecipe {
-            id: "all_sync",
-            abi_id: "i0040",
-            operation_key: "warp.vote.sync.all.pred",
-            source_record: "int_nvvm_vote_all_sync",
-            llvm_symbol: "llvm.nvvm.vote.all.sync",
-            rust_name: "all_sync",
-            rust_result: "bool",
-            dialect_op_type: "VoteSyncAllOp",
-            dialect_op_name: "nvvm.vote_sync_all",
-            llvm_result: "i1",
-            ptx_mode: "all",
-            ptx_type: "pred",
-            immediate_selection: "VOTE_SYNC_ALLi",
-            register_selection: "VOTE_SYNC_ALLr",
-            has_compatibility_path: true,
-        },
-        VoteMode::Any => VoteRecipe {
-            id: "any_sync",
-            abi_id: "i0041",
-            operation_key: "warp.vote.sync.any.pred",
-            source_record: "int_nvvm_vote_any_sync",
-            llvm_symbol: "llvm.nvvm.vote.any.sync",
-            rust_name: "any_sync",
-            rust_result: "bool",
-            dialect_op_type: "VoteSyncAnyOp",
-            dialect_op_name: "nvvm.vote_sync_any",
-            llvm_result: "i1",
-            ptx_mode: "any",
-            ptx_type: "pred",
-            immediate_selection: "VOTE_SYNC_ANYi",
-            register_selection: "VOTE_SYNC_ANYr",
-            has_compatibility_path: true,
-        },
-        VoteMode::Ballot => VoteRecipe {
-            id: "ballot_sync",
-            abi_id: "i0042",
-            operation_key: "warp.vote.sync.ballot.b32",
-            source_record: "int_nvvm_vote_ballot_sync",
-            llvm_symbol: "llvm.nvvm.vote.ballot.sync",
-            rust_name: "ballot_sync",
-            rust_result: "u32",
-            dialect_op_type: "VoteSyncBallotOp",
-            dialect_op_name: "nvvm.vote_sync_ballot",
-            llvm_result: "i32",
-            ptx_mode: "ballot",
-            ptx_type: "b32",
-            immediate_selection: "VOTE_SYNC_BALLOTi",
-            register_selection: "VOTE_SYNC_BALLOTr",
-            has_compatibility_path: true,
-        },
-        VoteMode::Uni => VoteRecipe {
-            id: "uni_sync",
-            abi_id: "i0043",
-            operation_key: "warp.vote.sync.uni.pred",
-            source_record: "int_nvvm_vote_uni_sync",
-            llvm_symbol: "llvm.nvvm.vote.uni.sync",
-            rust_name: "uni_sync",
-            rust_result: "bool",
-            dialect_op_type: "VoteSyncUniOp",
-            dialect_op_name: "nvvm.vote_sync_uni",
-            llvm_result: "i1",
-            ptx_mode: "uni",
-            ptx_type: "pred",
-            immediate_selection: "VOTE_SYNC_UNIi",
-            register_selection: "VOTE_SYNC_UNIr",
-            has_compatibility_path: false,
-        },
-    }
-}
-
-fn validate_active_mask_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let active_mask = policy
-        .active_mask
-        .as_ref()
-        .with_context(|| format!("{} has no closed active-mask contract", policy.id))?;
-    ensure!(
-        active_mask.observation == ActiveMaskObservation::ExecutingLanesAtInstruction
-            && active_mask.adapter == ActiveMaskAdapter::DirectZeroOperandMask,
-        "{} requests an unsupported active-mask observation or adapter",
-        policy.id
-    );
-    ensure!(
-        policy.id == "active_mask"
-            && policy.abi_id == "i0044"
-            && policy.operation_key == "warp.active_mask"
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some("int_nvvm_activemask")
-            && policy.llvm_symbol.as_deref() == Some("llvm.nvvm.activemask")
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} active-mask identity does not match the closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "warp"
-            && policy.rust_name == "active_mask"
-            && policy.rust_arguments.is_empty()
-            && policy.rust_result == "u32"
-            && policy.safe
-            && policy.must_use
-            && policy
-                .safe_allowlist_reason
-                .as_deref()
-                .is_some_and(|reason| !reason.is_empty())
-            && policy.public_rust_path == "cuda_intrinsics::warp::active_mask"
-            && policy.compatibility_rust_paths == ["cuda_device::warp::active_mask"],
-        "{} must preserve its safe must-use raw and compatibility APIs",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == "ActiveMaskOp"
-            && policy.dialect_op_name == "nvvm.activemask"
-            && policy.dialect_operands.is_empty()
-            && policy.dialect_results == ["i32"]
-            && policy.llvm_arguments.is_empty()
-            && policy.llvm_results == ["i32"]
-            && policy.lowering == "generated_active_mask",
-        "{} is outside the closed zero-operand active-mask lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "inaccessible_read_write"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == "6.2"
-            && policy.minimum_sm.as_deref() == Some("sm_30")
-            && policy.ptx_result == "u32"
-            && policy.targets == "all",
-        "{} active-mask effects or target floor disagree with the closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.14.12 Parallel Synchronization and Communication Instructions: activemask"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-activemask",
-        "{} active-mask PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.properties
-            == [
-                "IntrConvergent",
-                "IntrHasSideEffects",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ]
-            && declaration.selections.len() == 1
-            && declaration.selections[0].source_record == "ACTIVEMASK"
-            && declaration.selections[0].asm == "activemask.b32 \t$dest;"
-            && declaration.selections[0].predicates
-                == [
-                    "Subtarget->getSmVersion() >= 30",
-                    "Subtarget->getPTXVersion() >= 62",
-                ]
-            && declaration.selections[0].constraints.is_empty(),
-        "{} active-mask declaration or selection facts changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "activemask"
-            && policy.expected_ptx.modifiers == ["b32"]
-            && policy.expected_ptx.operands == [OperandPattern::Register],
-        "{} expected PTX does not match activemask.b32",
-        policy.id
-    );
-    ensure!(
-        policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with active_mask",
-        policy.id
-    );
-
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ]),
-        "{} must keep the LLVM typed and libNVVM inline-PTX routes explicit",
-        policy.id
-    );
-    for lowering in &policy.backend_lowerings {
-        let floor_matches = match lowering.backend {
-            IntrinsicBackend::LlvmNvptx => {
-                lowering.mechanism == BackendLoweringMechanism::TypedNvvm
-                    && lowering.minimum_ptx.as_deref() == Some("6.2")
-                    && lowering.minimum_sm.as_deref() == Some("sm_30")
-            }
-            IntrinsicBackend::LibNvvm => {
-                lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    && lowering.minimum_ptx.is_none()
-                    && lowering.minimum_sm.as_deref() == Some("sm_75")
-            }
-        };
-        ensure!(
-            floor_matches && !lowering.evidence_profile.trim().is_empty(),
-            "{} backend {:?} does not carry its reviewed active-mask floor",
-            policy.id,
-            lowering.backend
-        );
-    }
-    Ok(())
-}
-
-struct WarpMatchRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    rust_name: &'static str,
-    rust_value: &'static str,
-    llvm_value: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    ptx_mode: &'static str,
-    ptx_type: &'static str,
-    selections: [&'static str; 4],
-    adapter: WarpMatchAdapter,
-}
-
-fn warp_match_recipe(mode: WarpMatchMode, width: WarpMatchValueWidth) -> WarpMatchRecipe {
-    match (mode, width) {
-        (WarpMatchMode::Any, WarpMatchValueWidth::B32) => WarpMatchRecipe {
-            id: "match_any_sync",
-            abi_id: "i0045",
-            operation_key: "warp.match.sync.any.b32",
-            source_record: "int_nvvm_match_any_sync_i32",
-            llvm_symbol: "llvm.nvvm.match.any.sync.i32",
-            rust_name: "match_any_sync",
-            rust_value: "u32",
-            llvm_value: "i32",
-            dialect_op_type: "MatchAnySyncI32Op",
-            dialect_op_name: "nvvm.match_any_sync_i32",
-            ptx_mode: "any",
-            ptx_type: "b32",
-            selections: [
-                "MATCH_ANY_SYNC_32ii",
-                "MATCH_ANY_SYNC_32ir",
-                "MATCH_ANY_SYNC_32ri",
-                "MATCH_ANY_SYNC_32rr",
-            ],
-            adapter: WarpMatchAdapter::DirectMask,
-        },
-        (WarpMatchMode::Any, WarpMatchValueWidth::B64) => WarpMatchRecipe {
-            id: "match_any_i64_sync",
-            abi_id: "i0046",
-            operation_key: "warp.match.sync.any.b64",
-            source_record: "int_nvvm_match_any_sync_i64",
-            llvm_symbol: "llvm.nvvm.match.any.sync.i64",
-            rust_name: "match_any_i64_sync",
-            rust_value: "u64",
-            llvm_value: "i64",
-            dialect_op_type: "MatchAnySyncI64Op",
-            dialect_op_name: "nvvm.match_any_sync_i64",
-            ptx_mode: "any",
-            ptx_type: "b64",
-            selections: [
-                "MATCH_ANY_SYNC_64ii",
-                "MATCH_ANY_SYNC_64ir",
-                "MATCH_ANY_SYNC_64ri",
-                "MATCH_ANY_SYNC_64rr",
-            ],
-            adapter: WarpMatchAdapter::DirectMask,
-        },
-        (WarpMatchMode::All, WarpMatchValueWidth::B32) => WarpMatchRecipe {
-            id: "match_all_sync",
-            abi_id: "i0047",
-            operation_key: "warp.match.sync.all.b32",
-            source_record: "int_nvvm_match_all_sync_i32p",
-            llvm_symbol: "llvm.nvvm.match.all.sync.i32p",
-            rust_name: "match_all_sync",
-            rust_value: "u32",
-            llvm_value: "i32",
-            dialect_op_type: "MatchAllSyncI32Op",
-            dialect_op_name: "nvvm.match_all_sync_i32",
-            ptx_mode: "all",
-            ptx_type: "b32",
-            selections: [
-                "MATCH_ALLP_SYNC_32ii",
-                "MATCH_ALLP_SYNC_32ir",
-                "MATCH_ALLP_SYNC_32ri",
-                "MATCH_ALLP_SYNC_32rr",
-            ],
-            adapter: WarpMatchAdapter::ProjectMaskDiscardPredicate,
-        },
-        (WarpMatchMode::All, WarpMatchValueWidth::B64) => WarpMatchRecipe {
-            id: "match_all_i64_sync",
-            abi_id: "i0048",
-            operation_key: "warp.match.sync.all.b64",
-            source_record: "int_nvvm_match_all_sync_i64p",
-            llvm_symbol: "llvm.nvvm.match.all.sync.i64p",
-            rust_name: "match_all_i64_sync",
-            rust_value: "u64",
-            llvm_value: "i64",
-            dialect_op_type: "MatchAllSyncI64Op",
-            dialect_op_name: "nvvm.match_all_sync_i64",
-            ptx_mode: "all",
-            ptx_type: "b64",
-            selections: [
-                "MATCH_ALLP_SYNC_64ii",
-                "MATCH_ALLP_SYNC_64ir",
-                "MATCH_ALLP_SYNC_64ri",
-                "MATCH_ALLP_SYNC_64rr",
-            ],
-            adapter: WarpMatchAdapter::ProjectMaskDiscardPredicate,
-        },
-    }
-}
-
-fn validate_warp_match_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let warp_match = policy
-        .warp_match
-        .as_ref()
-        .with_context(|| format!("{} has no closed warp-match contract", policy.id))?;
-    let recipe = warp_match_recipe(warp_match.mode, warp_match.value_width);
-    ensure!(
-        warp_match.participation
-            == WarpMatchParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask
-            && warp_match.adapter == recipe.adapter
-            && warp_match.value_encoding == MatchOperandEncoding::RegisterOrImmediate
-            && warp_match.mask_encoding == MatchOperandEncoding::RegisterOrImmediate,
-        "{} requests an unsupported warp-match participation, adapter, or encoding",
-        policy.id
-    );
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} warp-match identity does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "warp"
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == ["u32", recipe.rust_value]
-            && policy.rust_result == "u32"
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::warp::{}", recipe.rust_name)
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::warp::{}", recipe.rust_name)],
-        "{} must preserve its unsafe raw and stable compatibility paths",
-        policy.id
-    );
-    let expected_llvm_results: &[&str] = match warp_match.mode {
-        WarpMatchMode::Any => &["i32"],
-        WarpMatchMode::All => &["i32", "i1"],
-    };
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == ["i32", recipe.llvm_value]
-            && policy.dialect_results == ["i32"]
-            && policy.llvm_arguments == ["i32", recipe.llvm_value]
-            && policy.llvm_results == expected_llvm_results
-            && policy.lowering == "generated_warp_match",
-        "{} is outside the closed two-operand warp-match lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "inaccessible_read_write"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == "6.0"
-            && policy.minimum_sm.as_deref() == Some("sm_70")
-            && policy.ptx_result == "u32"
-            && policy.targets == "all",
-        "{} warp-match effects, carrier, or target floor disagree with its recipe",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.14.11 Parallel Synchronization and Communication Instructions: match.sync"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-match-sync",
-        "{} warp-match PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.properties
-            == [
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-        "{} warp-match effects disagree with the imported declaration",
-        policy.id
-    );
-    ensure!(
-        policy.backend_lowerings.is_empty()
-            && policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with warp_match",
-        policy.id
-    );
-    let destination = match warp_match.mode {
-        WarpMatchMode::Any => OperandPattern::Register,
-        WarpMatchMode::All => OperandPattern::RegisterPredicatePair,
-    };
-    ensure!(
-        policy.expected_ptx.mnemonic == "match"
-            && policy.expected_ptx.modifiers == [recipe.ptx_mode, "sync", recipe.ptx_type]
-            && policy.expected_ptx.operands
-                == [
-                    destination,
-                    OperandPattern::RegisterOrImmediate,
-                    OperandPattern::RegisterOrImmediate,
-                ],
-        "{} expected PTX does not match its closed match.sync recipe",
-        policy.id
-    );
-    let actual_selection_records: BTreeSet<_> = declaration
-        .selections
-        .iter()
-        .map(|selection| selection.source_record.as_str())
-        .collect();
-    ensure!(
-        declaration.selections.len() == 4
-            && actual_selection_records == BTreeSet::from(recipe.selections),
-        "{} warp-match declaration must contain exactly ii/ir/ri/rr selections",
-        policy.id
-    );
-    let destination = if warp_match.mode == WarpMatchMode::All {
-        "$dest|$pred"
-    } else {
-        "$dest"
-    };
-    let expected_asm = format!(
-        "match.{}.sync.{} \t{}, $value, $mask;",
-        recipe.ptx_mode, recipe.ptx_type, destination
-    );
-    for selection in &declaration.selections {
-        ensure!(
-            selection.asm == expected_asm
-                && selection.predicates
-                    == [
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70",
-                    ]
-                && selection.constraints.is_empty(),
-            "{} warp-match selections disagree on PTX shape, predicates, or constraints",
-            policy.id
-        );
-    }
-    Ok(())
-}
-
-fn validate_elect_policy(policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic) -> Result<()> {
-    ensure!(
-        policy.id == "elect_sync"
-            && policy.abi_id == "i0367"
-            && policy.operation_key == "warp.elect.sync"
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some("int_nvvm_elect_sync")
-            && policy.llvm_symbol.as_deref() == Some("llvm.nvvm.elect.sync")
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} elect identity does not match the closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "warp"
-            && policy.rust_name == "elect_sync"
-            && policy.rust_arguments == ["u32"]
-            && policy.rust_result == "(u32, bool)"
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == "cuda_intrinsics::warp::elect_sync"
-            && policy.compatibility_rust_paths == ["cuda_device::warp::elect_sync"],
-        "{} must keep its unsafe raw API and stable compatibility path",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == "ElectSyncOp"
-            && policy.dialect_op_name == "nvvm.elect_sync"
-            && policy.dialect_operands == ["i32"]
-            && policy.dialect_results == ["i32", "i1"]
-            && policy.llvm_arguments == ["i32"]
-            && policy.llvm_results == ["i32", "i1"]
-            && policy.lowering == "generated_elect",
-        "{} is outside the closed elect lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "inaccessible_read_write"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == "8.0"
-            && policy.minimum_sm.as_deref() == Some("sm_90")
-            && policy.ptx_result == "(u32, bool)"
-            && policy.targets == "all",
-        "{} elect effects or target floor disagree with the closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.14.15 Parallel Synchronization and Communication Instructions: elect.sync"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-elect-sync",
-        "{} elect PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.classes == ["SDPatternOperator", "Intrinsic", "DefaultAttrsIntrinsic"]
-            && declaration.properties == ["IntrConvergent", "IntrInaccessibleMemOnly"]
-            && declaration.arguments == ["i32"]
-            && declaration.results == ["i32", "i1"],
-        "{} elect declaration facts changed",
-        policy.id
-    );
-    ensure!(
-        declaration.selections.len() == 2
-            && declaration.selections.iter().all(|selection| {
-                ["INT_ELECT_SYNC_I", "INT_ELECT_SYNC_R"].contains(&selection.source_record.as_str())
-                    && selection.asm == "elect.sync \t$dest|$pred, $mask;"
-                    && selection.predicates
-                        == [
-                            "Subtarget->getPTXVersion() >= 80",
-                            "Subtarget->getSmVersion() >= 90",
-                        ]
-                    && selection.constraints.is_empty()
-            }),
-        "{} elect selections changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "elect"
-            && policy.expected_ptx.modifiers == ["sync"]
-            && policy.expected_ptx.operands
-                == [
-                    OperandPattern::RegisterPredicatePair,
-                    OperandPattern::RegisterOrImmediate,
-                ],
-        "{} expected PTX does not match elect.sync",
-        policy.id
-    );
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && policy.backend_lowerings.iter().any(|route| {
-                route.backend == IntrinsicBackend::LlvmNvptx
-                    && route.mechanism == BackendLoweringMechanism::TypedNvvm
-                    && route.minimum_ptx.as_deref() == Some("8.0")
-                    && route.minimum_sm.as_deref() == Some("sm_90")
-                    && !route.evidence_profile.trim().is_empty()
-            })
-            && policy.backend_lowerings.iter().any(|route| {
-                route.backend == IntrinsicBackend::LibNvvm
-                    && route.mechanism == BackendLoweringMechanism::InlinePtx
-                    && route.minimum_ptx.as_deref() == Some("8.0")
-                    && route.minimum_sm.as_deref() == Some("sm_90")
-                    && !route.evidence_profile.trim().is_empty()
-            }),
-        "{} must keep the LLVM typed and libNVVM inline-PTX routes explicit",
-        policy.id
-    );
-    ensure!(
-        policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.cp_async_mbarrier.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.movmatrix.is_none()
-            && policy.mbarrier_extended.is_none()
-            && policy.register_mma.is_none()
-            && policy.sparse_mma.is_none()
-            && policy.prmt.is_none()
-            && policy.cluster_barrier.is_none()
-            && policy.wgmma_control.is_none()
-            && policy.special_register.is_none()
-            && policy.debug_control.is_none()
-            && policy.cluster_memory.is_none()
-            && policy.clc.is_none()
-            && policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with elect",
-        policy.id
-    );
-    Ok(())
-}
-
-fn validate_warp_barrier_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let barrier = policy
-        .warp_barrier
-        .as_ref()
-        .with_context(|| format!("{} has no closed warp-barrier contract", policy.id))?;
-    ensure!(
-        barrier.participation
-            == WarpBarrierParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask
-            && barrier.legacy_pre_sm70
-                == PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive
-            && barrier.adapter == WarpBarrierAdapter::DirectMemberMask
-            && barrier.mask_encoding == WarpBarrierMaskEncoding::RegisterOrImmediate
-            && barrier.memory_ordering == WarpBarrierMemoryOrdering::ParticipatingLanes,
-        "{} requests an unsupported warp-barrier participation, legacy rule, adapter, mask encoding, or memory ordering",
-        policy.id
-    );
-    ensure!(
-        policy.id == "sync_mask"
-            && policy.abi_id == "i0049"
-            && policy.operation_key == "warp.barrier.sync.masked"
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some("int_nvvm_bar_warp_sync")
-            && policy.llvm_symbol.as_deref() == Some("llvm.nvvm.bar.warp.sync")
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} warp-barrier identity does not match the closed sync_mask recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "warp"
-            && policy.rust_name == "sync_mask"
-            && policy.rust_arguments == ["u32"]
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == "cuda_intrinsics::warp::sync_mask"
-            && policy.compatibility_rust_paths == ["cuda_device::warp::sync_mask"],
-        "{} must keep its unsafe raw API and safe cuda-device compatibility path distinct",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == "BarWarpSyncOp"
-            && policy.dialect_op_name == "nvvm.bar_warp_sync"
-            && policy.dialect_operands == ["i32"]
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == ["i32"]
-            && policy.llvm_results.is_empty()
-            && policy.lowering == "generated_warp_barrier",
-        "{} is outside the closed one-mask warp-barrier lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read_write"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == "6.0"
-            && policy.minimum_sm.as_deref() == Some("sm_30")
-            && policy.ptx_result == "()"
-            && policy.targets == "all",
-        "{} warp-barrier effects or target floor disagree with the closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.14.2 Parallel Synchronization and Communication Instructions: bar.warp.sync"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-warp-sync",
-        "{} warp-barrier PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.properties == ["IntrConvergent", "IntrNoCallback"],
-        "{} warp-barrier effects disagree with the imported declaration",
-        policy.id
-    );
-    ensure!(
-        policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with warp_barrier",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "bar"
-            && policy.expected_ptx.modifiers == ["warp", "sync"]
-            && policy.expected_ptx.operands == [OperandPattern::RegisterOrImmediate],
-        "{} expected PTX does not match bar.warp.sync mask",
-        policy.id
-    );
-
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                ]),
-        "{} must define exactly the reviewed typed LLVM and libNVVM routes",
-        policy.id
-    );
-    for lowering in &policy.backend_lowerings {
-        let floor_matches = match lowering.backend {
-            IntrinsicBackend::LlvmNvptx => {
-                lowering.mechanism == BackendLoweringMechanism::TypedNvvm
-                    && lowering.minimum_ptx.as_deref() == Some("6.0")
-                    && lowering.minimum_sm.as_deref() == Some("sm_30")
-            }
-            IntrinsicBackend::LibNvvm => {
-                lowering.mechanism == BackendLoweringMechanism::TypedNvvm
-                    && lowering.minimum_ptx.as_deref() == Some("6.0")
-                    && lowering.minimum_sm.as_deref() == Some("sm_75")
-            }
-        };
-        ensure!(
-            floor_matches && !lowering.evidence_profile.trim().is_empty(),
-            "{} backend {:?} does not carry its reviewed warp-barrier profile floor",
-            policy.id,
-            lowering.backend
-        );
-    }
-
-    let expected_selection_records = BTreeSet::from(["INT_BAR_WARP_SYNC_I", "INT_BAR_WARP_SYNC_R"]);
-    let actual_selection_records: BTreeSet<_> = declaration
-        .selections
-        .iter()
-        .map(|selection| selection.source_record.as_str())
-        .collect();
-    ensure!(
-        declaration.selections.len() == 2 && actual_selection_records == expected_selection_records,
-        "{} warp-barrier declaration must contain exactly its immediate/register selection pair",
-        policy.id
-    );
-    for selection in &declaration.selections {
-        ensure!(
-            selection.asm == "bar.warp.sync \t$i;"
-                && selection.predicates
-                    == [
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30",
-                    ]
-                && selection.constraints.is_empty(),
-            "{} warp-barrier selections disagree on PTX shape, target predicates, or constraints",
-            policy.id
-        );
-    }
-    Ok(())
-}
-
-fn validate_warp_shuffle_policy(
-    policy: &OverlayIntrinsic,
-    declaration: Option<&ImportedIntrinsic>,
-) -> Result<()> {
-    let shuffle = policy
-        .warp_shuffle
-        .as_ref()
-        .with_context(|| format!("{} has no closed warp-shuffle contract", policy.id))?;
-    let recipe = warp_shuffle_recipe(shuffle.mode, shuffle.value_kind);
-    ensure!(
-        shuffle.participation
-            == WarpShuffleParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask
-            && shuffle.legacy_pre_sm70
-                == PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive
-            && shuffle.source_lane
-                == WarpShuffleSourceLane::InRangeSourceActiveAndNamedOutOfRangeCopiesSelf
-            && shuffle.adapter == recipe.adapter
-            && shuffle.clamp == recipe.clamp
-            && shuffle.lane_encoding == recipe.operand_encoding
-            && shuffle.mask_encoding == recipe.operand_encoding,
-        "{} requests an unsupported warp-shuffle semantic or operand contract",
-        policy.id
-    );
-
-    let source_matches = match recipe.source {
-        WarpShuffleRecipeSource::LlvmImported {
-            source_record,
-            llvm_symbol,
-        } => {
-            policy.source.is_none()
-                && policy.source_record.as_deref() == Some(source_record)
-                && policy.llvm_symbol.as_deref() == Some(llvm_symbol)
-                && policy.resolved_llvm_symbol.is_none()
-        }
-        WarpShuffleRecipeSource::PtxNative { instruction } => {
-            policy.source
-                == Some(IntrinsicSource::PtxNative {
-                    instruction: instruction.into(),
-                })
-                && policy.source_record.is_none()
-                && policy.llvm_symbol.is_none()
-                && policy.resolved_llvm_symbol.is_none()
-                && policy.llvm_arguments.is_empty()
-                && policy.llvm_results.is_empty()
-        }
-    };
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && source_matches,
-        "{} warp-shuffle identity does not match its closed mode and value recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "warp"
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == ["u32", recipe.rust_value, "u32"]
-            && policy.rust_result == recipe.rust_value
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::warp::{}", recipe.rust_name)
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::warp::{}", recipe.rust_name)],
-        "{} must preserve its unsafe must-use warp-shuffle raw API and compatibility path",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == ["i32", recipe.dialect_value, "i32"]
-            && policy.dialect_results == [recipe.dialect_value]
-            && policy.lowering == recipe.lowering
-            && match recipe.source {
-                WarpShuffleRecipeSource::LlvmImported { .. } => {
-                    policy.llvm_arguments == ["i32", recipe.dialect_value, "i32", "i32"]
-                        && policy.llvm_results == [recipe.dialect_value]
-                }
-                WarpShuffleRecipeSource::PtxNative { .. } => {
-                    policy.llvm_arguments.is_empty() && policy.llvm_results.is_empty()
-                }
-            },
-        "{} is outside the closed warp-shuffle lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "inaccessible_read_write"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == "6.0"
-            && policy.minimum_sm.as_deref() == Some("sm_30")
-            && policy.ptx_result == recipe.rust_value
-            && policy.targets == "all",
-        "{} warp-shuffle effects, carrier, or target floor disagree with its recipe",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.9.6 Data Movement and Conversion Instructions: shfl.sync"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-shfl-sync",
-        "{} warp-shuffle PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    if let Some(declaration) = declaration {
-        ensure!(
-            matches!(recipe.source, WarpShuffleRecipeSource::LlvmImported { .. })
-                && declaration.classes
-                    == [
-                        "ClangBuiltin",
-                        "NVVMBuiltin",
-                        "SDPatternOperator",
-                        "Intrinsic"
-                    ]
-                && declaration.properties
-                    == [
-                        "IntrConvergent",
-                        "IntrInaccessibleMemOnly",
-                        "IntrNoCallback",
-                    ],
-            "{} warp-shuffle class or effects disagree with the imported declaration",
-            policy.id
-        );
-    } else {
-        ensure!(
-            matches!(recipe.source, WarpShuffleRecipeSource::PtxNative { .. }),
-            "{} imported warp shuffle is missing its LLVM declaration",
-            policy.id
-        );
-    }
-    ensure!(
-        policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with warp_shuffle",
-        policy.id
-    );
-    let expected_operands = match recipe.adapter {
-        WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp => vec![
-            OperandPattern::Register,
-            OperandPattern::Register,
-            OperandPattern::RegisterOrImmediate,
-            OperandPattern::Exact {
-                value: recipe.clamp.to_string(),
-            },
-            OperandPattern::RegisterOrImmediate,
-        ],
-        WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble => vec![
-            OperandPattern::Exact { value: "lo".into() },
-            OperandPattern::Exact { value: "lo".into() },
-            OperandPattern::Register,
-            OperandPattern::Exact {
-                value: recipe.clamp.to_string(),
-            },
-            OperandPattern::Register,
-        ],
-    };
-    ensure!(
-        policy.expected_ptx.mnemonic == "shfl"
-            && policy.expected_ptx.modifiers == ["sync", recipe.ptx_mode, "b32"]
-            && policy.expected_ptx.operands == expected_operands,
-        "{} expected PTX does not match its closed shfl.sync recipe",
-        policy.id
-    );
-
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (IntrinsicBackend::LlvmNvptx, recipe.backend_mechanism),
-                    (IntrinsicBackend::LibNvvm, recipe.backend_mechanism),
-                ]),
-        "{} must define exactly the reviewed LLVM and libNVVM routes",
-        policy.id
-    );
-    for lowering in &policy.backend_lowerings {
-        let floor_matches = match lowering.backend {
-            IntrinsicBackend::LlvmNvptx => {
-                lowering.mechanism == recipe.backend_mechanism
-                    && lowering.minimum_ptx.as_deref() == Some("6.0")
-                    && lowering.minimum_sm.as_deref() == Some("sm_30")
-            }
-            IntrinsicBackend::LibNvvm => {
-                lowering.mechanism == recipe.backend_mechanism
-                    && lowering.minimum_ptx.as_deref() == Some("6.0")
-                    && lowering.minimum_sm.as_deref() == Some("sm_75")
-            }
-        };
-        ensure!(
-            floor_matches && !lowering.evidence_profile.trim().is_empty(),
-            "{} backend {:?} does not carry its reviewed warp-shuffle profile floor",
-            policy.id,
-            lowering.backend
-        );
-    }
-
-    if let Some(declaration) = declaration {
-        let selection_records: BTreeSet<_> = declaration
-            .selections
-            .iter()
-            .map(|selection| selection.source_record.as_str())
-            .collect();
-        ensure!(
-            declaration.selections.len() == 8
-                && selection_records.len() == 8
-                && selection_records
-                    .iter()
-                    .all(|source_record| !source_record.trim().is_empty()),
-            "{} warp-shuffle declaration must contain exactly eight distinct operand-encoding selections",
-            policy.id
-        );
-        let expected_asm = format!(
-            "shfl.sync.{}.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-            recipe.ptx_mode
-        );
-        for selection in &declaration.selections {
-            ensure!(
-                selection.asm == expected_asm
-                    && selection.predicates
-                        == [
-                            "Subtarget->getPTXVersion() >= 60",
-                            "Subtarget->getSmVersion() >= 30",
-                        ]
-                    && selection.constraints.is_empty(),
-                "{} warp-shuffle selections disagree on PTX shape, target predicates, or constraints",
-                policy.id
-            );
-        }
-    }
-    Ok(())
-}
-
-#[derive(Clone, Copy)]
-enum WarpShuffleRecipeSource {
-    LlvmImported {
-        source_record: &'static str,
-        llvm_symbol: &'static str,
-    },
-    PtxNative {
-        instruction: &'static str,
-    },
-}
-
-struct WarpShuffleRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    source: WarpShuffleRecipeSource,
-    rust_name: &'static str,
-    rust_value: &'static str,
-    dialect_value: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    ptx_mode: &'static str,
-    clamp: u32,
-    adapter: WarpShuffleAdapter,
-    operand_encoding: WarpShuffleOperandEncoding,
-    lowering: &'static str,
-    backend_mechanism: BackendLoweringMechanism,
-}
-
-fn warp_shuffle_recipe(
-    mode: WarpShuffleMode,
-    value_kind: WarpShuffleValueKind,
-) -> WarpShuffleRecipe {
-    match (mode, value_kind) {
-        (WarpShuffleMode::Idx, WarpShuffleValueKind::I32) => WarpShuffleRecipe {
-            id: "shuffle_sync",
-            abi_id: "i0050",
-            operation_key: "warp.shuffle.sync.idx.i32",
-            source: WarpShuffleRecipeSource::LlvmImported {
-                source_record: "int_nvvm_shfl_sync_idx_i32",
-                llvm_symbol: "llvm.nvvm.shfl.sync.idx.i32",
-            },
-            rust_name: "shuffle_sync",
-            rust_value: "u32",
-            dialect_value: "i32",
-            dialect_op_type: "ShflSyncIdxI32Op",
-            dialect_op_name: "nvvm.shfl_sync_idx_i32",
-            ptx_mode: "idx",
-            clamp: 31,
-            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
-            lowering: "generated_warp_shuffle",
-            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
-        },
-        (WarpShuffleMode::Bfly, WarpShuffleValueKind::I32) => WarpShuffleRecipe {
-            id: "shuffle_xor_sync",
-            abi_id: "i0051",
-            operation_key: "warp.shuffle.sync.bfly.i32",
-            source: WarpShuffleRecipeSource::LlvmImported {
-                source_record: "int_nvvm_shfl_sync_bfly_i32",
-                llvm_symbol: "llvm.nvvm.shfl.sync.bfly.i32",
-            },
-            rust_name: "shuffle_xor_sync",
-            rust_value: "u32",
-            dialect_value: "i32",
-            dialect_op_type: "ShflSyncBflyI32Op",
-            dialect_op_name: "nvvm.shfl_sync_bfly_i32",
-            ptx_mode: "bfly",
-            clamp: 31,
-            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
-            lowering: "generated_warp_shuffle",
-            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
-        },
-        (WarpShuffleMode::Down, WarpShuffleValueKind::I32) => WarpShuffleRecipe {
-            id: "shuffle_down_sync",
-            abi_id: "i0052",
-            operation_key: "warp.shuffle.sync.down.i32",
-            source: WarpShuffleRecipeSource::LlvmImported {
-                source_record: "int_nvvm_shfl_sync_down_i32",
-                llvm_symbol: "llvm.nvvm.shfl.sync.down.i32",
-            },
-            rust_name: "shuffle_down_sync",
-            rust_value: "u32",
-            dialect_value: "i32",
-            dialect_op_type: "ShflSyncDownI32Op",
-            dialect_op_name: "nvvm.shfl_sync_down_i32",
-            ptx_mode: "down",
-            clamp: 31,
-            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
-            lowering: "generated_warp_shuffle",
-            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
-        },
-        (WarpShuffleMode::Up, WarpShuffleValueKind::I32) => WarpShuffleRecipe {
-            id: "shuffle_up_sync",
-            abi_id: "i0053",
-            operation_key: "warp.shuffle.sync.up.i32",
-            source: WarpShuffleRecipeSource::LlvmImported {
-                source_record: "int_nvvm_shfl_sync_up_i32",
-                llvm_symbol: "llvm.nvvm.shfl.sync.up.i32",
-            },
-            rust_name: "shuffle_up_sync",
-            rust_value: "u32",
-            dialect_value: "i32",
-            dialect_op_type: "ShflSyncUpI32Op",
-            dialect_op_name: "nvvm.shfl_sync_up_i32",
-            ptx_mode: "up",
-            clamp: 0,
-            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
-            lowering: "generated_warp_shuffle",
-            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
-        },
-        (WarpShuffleMode::Idx, WarpShuffleValueKind::F32) => WarpShuffleRecipe {
-            id: "shuffle_f32_sync",
-            abi_id: "i0054",
-            operation_key: "warp.shuffle.sync.idx.f32",
-            source: WarpShuffleRecipeSource::LlvmImported {
-                source_record: "int_nvvm_shfl_sync_idx_f32",
-                llvm_symbol: "llvm.nvvm.shfl.sync.idx.f32",
-            },
-            rust_name: "shuffle_f32_sync",
-            rust_value: "f32",
-            dialect_value: "f32",
-            dialect_op_type: "ShflSyncIdxF32Op",
-            dialect_op_name: "nvvm.shfl_sync_idx_f32",
-            ptx_mode: "idx",
-            clamp: 31,
-            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
-            lowering: "generated_warp_shuffle",
-            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
-        },
-        (WarpShuffleMode::Bfly, WarpShuffleValueKind::F32) => WarpShuffleRecipe {
-            id: "shuffle_xor_f32_sync",
-            abi_id: "i0055",
-            operation_key: "warp.shuffle.sync.bfly.f32",
-            source: WarpShuffleRecipeSource::LlvmImported {
-                source_record: "int_nvvm_shfl_sync_bfly_f32",
-                llvm_symbol: "llvm.nvvm.shfl.sync.bfly.f32",
-            },
-            rust_name: "shuffle_xor_f32_sync",
-            rust_value: "f32",
-            dialect_value: "f32",
-            dialect_op_type: "ShflSyncBflyF32Op",
-            dialect_op_name: "nvvm.shfl_sync_bfly_f32",
-            ptx_mode: "bfly",
-            clamp: 31,
-            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
-            lowering: "generated_warp_shuffle",
-            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
-        },
-        (WarpShuffleMode::Down, WarpShuffleValueKind::F32) => WarpShuffleRecipe {
-            id: "shuffle_down_f32_sync",
-            abi_id: "i0056",
-            operation_key: "warp.shuffle.sync.down.f32",
-            source: WarpShuffleRecipeSource::LlvmImported {
-                source_record: "int_nvvm_shfl_sync_down_f32",
-                llvm_symbol: "llvm.nvvm.shfl.sync.down.f32",
-            },
-            rust_name: "shuffle_down_f32_sync",
-            rust_value: "f32",
-            dialect_value: "f32",
-            dialect_op_type: "ShflSyncDownF32Op",
-            dialect_op_name: "nvvm.shfl_sync_down_f32",
-            ptx_mode: "down",
-            clamp: 31,
-            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
-            lowering: "generated_warp_shuffle",
-            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
-        },
-        (WarpShuffleMode::Up, WarpShuffleValueKind::F32) => WarpShuffleRecipe {
-            id: "shuffle_up_f32_sync",
-            abi_id: "i0057",
-            operation_key: "warp.shuffle.sync.up.f32",
-            source: WarpShuffleRecipeSource::LlvmImported {
-                source_record: "int_nvvm_shfl_sync_up_f32",
-                llvm_symbol: "llvm.nvvm.shfl.sync.up.f32",
-            },
-            rust_name: "shuffle_up_f32_sync",
-            rust_value: "f32",
-            dialect_value: "f32",
-            dialect_op_type: "ShflSyncUpF32Op",
-            dialect_op_name: "nvvm.shfl_sync_up_f32",
-            ptx_mode: "up",
-            clamp: 0,
-            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
-            lowering: "generated_warp_shuffle",
-            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
-        },
-        (WarpShuffleMode::Idx, WarpShuffleValueKind::I64) => WarpShuffleRecipe {
-            id: "shuffle_u64_sync",
-            abi_id: "i0058",
-            operation_key: "warp.shuffle.sync.idx.i64",
-            source: WarpShuffleRecipeSource::PtxNative {
-                instruction: "shfl.sync.idx.b32",
-            },
-            rust_name: "shuffle_u64_sync",
-            rust_value: "u64",
-            dialect_value: "i64",
-            dialect_op_type: "ShflSyncIdxI64Op",
-            dialect_op_name: "nvvm.shfl_sync_idx_i64",
-            ptx_mode: "idx",
-            clamp: 31,
-            adapter:
-                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOnly,
-            lowering: "generated_warp_shuffle_i64_inline_ptx",
-            backend_mechanism: BackendLoweringMechanism::InlinePtx,
-        },
-        (WarpShuffleMode::Bfly, WarpShuffleValueKind::I64) => WarpShuffleRecipe {
-            id: "shuffle_xor_u64_sync",
-            abi_id: "i0059",
-            operation_key: "warp.shuffle.sync.bfly.i64",
-            source: WarpShuffleRecipeSource::PtxNative {
-                instruction: "shfl.sync.bfly.b32",
-            },
-            rust_name: "shuffle_xor_u64_sync",
-            rust_value: "u64",
-            dialect_value: "i64",
-            dialect_op_type: "ShflSyncBflyI64Op",
-            dialect_op_name: "nvvm.shfl_sync_bfly_i64",
-            ptx_mode: "bfly",
-            clamp: 31,
-            adapter:
-                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOnly,
-            lowering: "generated_warp_shuffle_i64_inline_ptx",
-            backend_mechanism: BackendLoweringMechanism::InlinePtx,
-        },
-        (WarpShuffleMode::Down, WarpShuffleValueKind::I64) => WarpShuffleRecipe {
-            id: "shuffle_down_u64_sync",
-            abi_id: "i0060",
-            operation_key: "warp.shuffle.sync.down.i64",
-            source: WarpShuffleRecipeSource::PtxNative {
-                instruction: "shfl.sync.down.b32",
-            },
-            rust_name: "shuffle_down_u64_sync",
-            rust_value: "u64",
-            dialect_value: "i64",
-            dialect_op_type: "ShflSyncDownI64Op",
-            dialect_op_name: "nvvm.shfl_sync_down_i64",
-            ptx_mode: "down",
-            clamp: 31,
-            adapter:
-                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOnly,
-            lowering: "generated_warp_shuffle_i64_inline_ptx",
-            backend_mechanism: BackendLoweringMechanism::InlinePtx,
-        },
-        (WarpShuffleMode::Up, WarpShuffleValueKind::I64) => WarpShuffleRecipe {
-            id: "shuffle_up_u64_sync",
-            abi_id: "i0061",
-            operation_key: "warp.shuffle.sync.up.i64",
-            source: WarpShuffleRecipeSource::PtxNative {
-                instruction: "shfl.sync.up.b32",
-            },
-            rust_name: "shuffle_up_u64_sync",
-            rust_value: "u64",
-            dialect_value: "i64",
-            dialect_op_type: "ShflSyncUpI64Op",
-            dialect_op_name: "nvvm.shfl_sync_up_i64",
-            ptx_mode: "up",
-            clamp: 0,
-            adapter:
-                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble,
-            operand_encoding: WarpShuffleOperandEncoding::RegisterOnly,
-            lowering: "generated_warp_shuffle_i64_inline_ptx",
-            backend_mechanism: BackendLoweringMechanism::InlinePtx,
-        },
-    }
-}
-
-fn validate_selected_target_predicates(
-    policy: &OverlayIntrinsic,
-    selection: &crate::model::ImportedSelection,
-) -> Result<()> {
-    if policy.family == "wgmma_control" {
-        ensure!(
-            selection.predicates == ["Subtarget->getPTXVersion() >= 80", "hasSM90a"]
-                && parse_ptx_version(&policy.minimum_ptx, &policy.id)?.encoded() == 80
-                && parse_hardware_target(policy)?
-                    == CatalogHardwareTarget::AnyOf {
-                        alternatives: vec![CatalogHardwareAlternative::ExactArchitecture {
-                            sm: 90,
-                        }],
-                    },
-            "{} WGMMA-control selection must retain the PTX 8.0 and sm_90a gates",
-            policy.id
-        );
-        return Ok(());
-    }
-    if policy.family == "register_control" {
-        let operation = ExecutionControlOperation::from_catalog_id(&policy.id)
-            .with_context(|| format!("{} has no closed register-control operation", policy.id))?;
-        ensure!(
-            matches!(
-                operation,
-                ExecutionControlOperation::SetMaxNRegInc | ExecutionControlOperation::SetMaxNRegDec
-            ) && selection.predicates == ["Subtarget->hasSetMaxNRegSupport()"]
-                && parse_ptx_version(&policy.minimum_ptx, &policy.id)?.encoded() == 80
-                && policy.minimum_sm.is_none()
-                && policy.targets == TENSOR_MAP_REPLACE_TARGETS,
-            "{} setmaxnreg selection must retain the helper predicate and reviewed PTX 8.0 target matrix",
-            policy.id
-        );
-        return Ok(());
-    }
-
-    let mma_family = matches!(policy.family.as_str(), "register_mma" | "sparse_mma");
-    let tcgen05_mma = policy
-        .tcgen05
-        .as_ref()
-        .and_then(|tcgen05| tcgen05.mma.as_ref());
-    let mut imported_ptx: Option<u16> = None;
-    let mut imported_sm: Option<u16> = None;
-    let mut has_dot_instructions = false;
-    let mut has_clc_multicast_support = false;
-    let mut has_tma_blackwell_support = false;
-    let mut has_tcgen05_support = false;
-    let mut has_tcgen05_shift_support = false;
-    let mut has_tcgen05_mma_i8_support = false;
-    let mut has_ldstmatrix_blackwell_support = false;
-    let mut has_mma_block_scale_support = false;
-    let mut has_redux_sync_f32_support = false;
-    for predicate in &selection.predicates {
-        if let Some(value) = predicate.strip_prefix("Subtarget->getPTXVersion() >= ") {
-            let value = value.parse::<u16>().with_context(|| {
-                format!("{} has malformed PTX predicate {predicate:?}", policy.id)
-            })?;
-            ensure!(
-                imported_ptx.is_none() || mma_family,
-                "{} has duplicate PTX predicates",
-                policy.id
-            );
-            imported_ptx = Some(imported_ptx.unwrap_or_default().max(value));
-        } else if let Some(value) = predicate.strip_prefix("Subtarget->getSmVersion() >= ") {
-            let value = value.parse::<u16>().with_context(|| {
-                format!("{} has malformed SM predicate {predicate:?}", policy.id)
-            })?;
-            ensure!(
-                imported_sm.is_none() || mma_family,
-                "{} has duplicate SM predicates",
-                policy.id
-            );
-            imported_sm = Some(imported_sm.unwrap_or_default().max(value));
-        } else if predicate == "hasDotInstructions" {
-            ensure!(
-                policy.family == "dotprod",
-                "{} selected instruction uses dot-product target gating outside the dotprod family",
-                policy.id
-            );
-            ensure!(
-                !has_dot_instructions && imported_ptx.is_none() && imported_sm.is_none(),
-                "{} has duplicate or conflicting dot-product target predicates",
-                policy.id
-            );
-            has_dot_instructions = true;
-            imported_ptx = Some(50);
-            imported_sm = Some(61);
-        } else if predicate == "Subtarget->hasClusterLaunchControlTryCancelMulticastSupport()" {
-            ensure!(
-                policy.family == "clc"
-                    && policy
-                        .clc
-                        .as_ref()
-                        .is_some_and(|clc| { clc.operation == ClcOperation::TryCancelMulticast }),
-                "{} uses the CLC multicast target predicate outside that operation",
-                policy.id
-            );
-            ensure!(
-                !has_clc_multicast_support
-                    && imported_ptx.is_none()
-                    && imported_sm.is_none()
-                    && !has_dot_instructions,
-                "{} has duplicate or conflicting CLC multicast target predicates",
-                policy.id
-            );
-            has_clc_multicast_support = true;
-        } else if predicate == "Subtarget->hasTMABlackwellSupport()" {
-            ensure!(
-                policy.family == "tma"
-                    && policy.tma.as_ref().is_some_and(|tma| {
-                        matches!(
-                            tma.operation,
-                            TmaOperation::G2sTile2dMulticastCg2
-                                | TmaOperation::PrefetchTileGather4TwoDimensional
-                                | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint
-                        )
-                    }),
-                "{} uses the Blackwell TMA target predicate outside the cta_group::2 operation",
-                policy.id
-            );
-            ensure!(
-                !has_tma_blackwell_support
-                    && imported_ptx.is_none()
-                    && imported_sm.is_none()
-                    && !has_dot_instructions
-                    && !has_clc_multicast_support,
-                "{} has duplicate or conflicting Blackwell TMA target predicates",
-                policy.id
-            );
-            has_tma_blackwell_support = true;
-        } else if predicate == "Subtarget->hasTcgen05InstSupport()" {
-            ensure!(
-                policy.family == "tcgen05" && policy.tcgen05.is_some(),
-                "{} uses the tcgen05 target predicate outside that family",
-                policy.id
-            );
-            ensure!(
-                !has_tcgen05_support
-                    && !has_tcgen05_shift_support
-                    && !has_tcgen05_mma_i8_support
-                    && imported_ptx.is_none()
-                    && imported_sm.is_none()
-                    && !has_dot_instructions
-                    && !has_clc_multicast_support
-                    && !has_tma_blackwell_support,
-                "{} has duplicate or conflicting tcgen05 target predicates",
-                policy.id
-            );
-            has_tcgen05_support = true;
-        } else if predicate == "Subtarget->hasTcgen05MMAI8Kind()" {
-            ensure!(
-                tcgen05_mma.is_some() && selection.asm.contains(".kind::i8."),
-                "{} uses the tcgen05 I8 predicate outside an I8 MMA selection",
-                policy.id
-            );
-            ensure!(
-                !has_tcgen05_mma_i8_support
-                    && !has_tcgen05_support
-                    && !has_tcgen05_shift_support
-                    && imported_ptx.is_none()
-                    && imported_sm.is_none()
-                    && !has_dot_instructions
-                    && !has_clc_multicast_support
-                    && !has_tma_blackwell_support,
-                "{} has duplicate or conflicting tcgen05 I8 predicates",
-                policy.id
-            );
-            has_tcgen05_mma_i8_support = true;
-        } else if predicate == "Subtarget->hasTcgen05ShiftSupport()" {
-            ensure!(
-                policy.family == "tcgen05"
-                    && policy.tcgen05.as_ref().is_some_and(|tcgen05| {
-                        matches!(
-                            tcgen05.operation,
-                            Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2
-                        )
-                    }),
-                "{} uses the tcgen05 shift target predicate outside a shift operation",
-                policy.id
-            );
-            ensure!(
-                !has_tcgen05_shift_support
-                    && !has_tcgen05_support
-                    && !has_tcgen05_mma_i8_support
-                    && imported_ptx.is_none()
-                    && imported_sm.is_none()
-                    && !has_dot_instructions
-                    && !has_clc_multicast_support
-                    && !has_tma_blackwell_support,
-                "{} has duplicate or conflicting tcgen05 shift target predicates",
-                policy.id
-            );
-            has_tcgen05_shift_support = true;
-        } else if predicate == "Subtarget->hasLdStmatrixBlackwellSupport()" {
-            ensure!(
-                policy.family == "ldmatrix"
-                    && policy.ldmatrix_variant.as_ref().is_some_and(|variant| {
-                        variant.shape != LdmatrixShape::M8n8
-                            && variant.element != LdmatrixElement::B16
-                    }),
-                "{} uses the Blackwell ld/stmatrix predicate outside a Blackwell ldmatrix variant",
-                policy.id
-            );
-            ensure!(
-                !has_ldstmatrix_blackwell_support
-                    && imported_ptx.is_none()
-                    && imported_sm.is_none()
-                    && !has_dot_instructions
-                    && !has_clc_multicast_support
-                    && !has_tma_blackwell_support
-                    && !has_tcgen05_support
-                    && !has_tcgen05_shift_support,
-                "{} has duplicate or conflicting Blackwell ldmatrix target predicates",
-                policy.id
-            );
-            has_ldstmatrix_blackwell_support = true;
-        } else if predicate == "Subtarget->hasMMABlockScale()" {
-            ensure!(
-                matches!(policy.family.as_str(), "register_mma" | "sparse_mma")
-                    && (policy.register_mma.is_some() || policy.sparse_mma.is_some()),
-                "{} uses the MMA block-scale target predicate outside a closed MMA family",
-                policy.id
-            );
-            ensure!(
-                !has_mma_block_scale_support
-                    && imported_ptx.is_none()
-                    && imported_sm.is_none()
-                    && !has_dot_instructions
-                    && !has_clc_multicast_support
-                    && !has_tma_blackwell_support
-                    && !has_tcgen05_support
-                    && !has_tcgen05_shift_support
-                    && !has_ldstmatrix_blackwell_support,
-                "{} has duplicate or conflicting MMA block-scale target predicates",
-                policy.id
-            );
-            has_mma_block_scale_support = true;
-        } else if predicate == "Subtarget->hasReduxSyncF32()" {
-            ensure!(
-                policy.family == "redux"
-                    && policy
-                        .redux
-                        .as_ref()
-                        .is_some_and(|redux| redux_recipe(redux.operation).value_type == "f32"),
-                "{} uses the f32 redux target predicate outside an f32 redux operation",
-                policy.id
-            );
-            ensure!(
-                !has_redux_sync_f32_support && imported_ptx.is_none() && imported_sm.is_none(),
-                "{} has duplicate or conflicting f32 redux target predicates",
-                policy.id
-            );
-            has_redux_sync_f32_support = true;
-        } else {
-            bail!(
-                "{} selected instruction has unsupported target predicate {predicate:?}; target gates must fail closed",
-                policy.id
-            );
-        }
-    }
-    let overlay_ptx = parse_ptx_version(&policy.minimum_ptx, &policy.id)?.encoded();
-    if let Some(mma) = tcgen05_mma {
-        let i8_selection = selection.asm.contains(".kind::i8.");
-        ensure!(
-            selection.predicates.len() == 1
-                && ((i8_selection && has_tcgen05_mma_i8_support && !has_tcgen05_support)
-                    || (!i8_selection && has_tcgen05_support && !has_tcgen05_mma_i8_support))
-                && !has_tcgen05_shift_support,
-            "{} tcgen05 MMA selection does not retain its exact kind predicate",
-            policy.id
-        );
-        let contracts = expected_tcgen05_mma_target_contracts(IntrinsicBackend::LlvmNvptx);
-        let expected_target = if let Some(fixed) = mma.fixed_selectors {
-            resolve_target_contract(
-                "tcgen05 MMA selected predicate",
-                &[TargetSelectorBinding {
-                    name: "kind".into(),
-                    value: tcgen05_mma_kind_name(fixed.kind).into(),
-                }],
-                &contracts,
-            )?
-        } else {
-            resolve_target_contracts("tcgen05 MMA selected predicate", &contracts)?
-        };
-        ensure!(
-            mma.llvm_target == expected_target,
-            "{} tcgen05 MMA predicate does not map to its closed LLVM target matrix",
-            policy.id
-        );
-        return Ok(());
-    }
-    if has_mma_block_scale_support {
-        let (minimum_ptx_matches, target_matches) = match policy.family.as_str() {
-            "register_mma" => (
-                overlay_ptx == 87,
-                policy.targets == "sm_120a|sm_120f|sm_121a|sm_121f" && policy.minimum_sm.is_none(),
-            ),
-            "sparse_mma" => (
-                overlay_ptx == 87,
-                policy.minimum_sm.is_none()
-                    && policy.sparse_mma.as_ref().is_some_and(|mma| {
-                        policy.targets
-                            == match mma.accumulator {
-                                SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 => {
-                                    SPARSE_MMA_F8F6F4_TARGETS
-                                }
-                                SparseMmaAccumulator::S32 => return false,
-                            }
-                    }),
-            ),
-            _ => (false, false),
-        };
-        ensure!(
-            minimum_ptx_matches && target_matches,
-            "{} MMA block-scale predicate requires its reviewed Blackwell target matrix",
-            policy.id
-        );
-        return Ok(());
-    }
-    if has_redux_sync_f32_support {
-        ensure!(
-            selection.predicates.len() == 1
-                && overlay_ptx == 86
-                && policy.targets == REDUX_F32_TARGETS
-                && policy.minimum_sm.is_none(),
-            "{} f32 redux selection must carry only the hasReduxSyncF32 predicate and its reviewed Blackwell target matrix",
-            policy.id
-        );
-        return Ok(());
-    }
-    // MMA uses reviewed inline PTX. Its imported predicates gate LLVM's typed
-    // selection, while the closed recipe and terminal evidence set the native
-    // PTX floor.
-    if mma_family {
-        return Ok(());
-    }
-    if let Some(imported_ptx) = imported_ptx {
-        ensure!(
-            overlay_ptx == imported_ptx,
-            "{} minimum PTX {} disagrees with selected instruction predicate PTX {}",
-            policy.id,
-            policy.minimum_ptx,
-            format_args!("{}.{}", imported_ptx / 10, imported_ptx % 10)
-        );
-    }
-    if let Some(imported_sm) = imported_sm {
-        if let Some(packed) = &policy.packed_alu {
-            ensure!(
-                packed.native_minimum_sm == imported_sm,
-                "{} native minimum SM {} disagrees with selected instruction predicate sm_{}",
-                policy.id,
-                packed.native_minimum_sm,
-                imported_sm
-            );
-        } else {
-            let overlay_target = parse_hardware_target(policy)?;
-            let target_matches = overlay_target
-                == CatalogHardwareTarget::AnyOf {
-                    alternatives: vec![CatalogHardwareAlternative::MinimumSm { sm: imported_sm }],
-                };
-            ensure!(
-                target_matches,
-                "{} minimum SM {:?} disagrees with selected instruction predicate sm_{}",
-                policy.id,
-                policy.minimum_sm,
-                imported_sm
-            );
-        }
-    }
-    if policy.family == "ldmatrix" {
-        if policy
-            .ldmatrix_variant
-            .as_ref()
-            .is_some_and(|variant| variant.shape == LdmatrixShape::M8n8)
-        {
-            ensure!(
-                imported_ptx.is_some() && imported_sm.is_some() && selection.predicates.len() == 2,
-                "{} classic ldmatrix selection must carry exactly its PTX and SM predicates",
-                policy.id
-            );
-        } else {
-            ensure!(
-                has_ldstmatrix_blackwell_support
-                    && selection.predicates.len() == 1
-                    && policy.targets == BLACKWELL_LDMATRIX_LLVM_TARGETS,
-                "{} Blackwell ldmatrix selection must retain its helper predicate and reviewed exact targets",
-                policy.id
-            );
-        }
-    } else if policy.family == "dotprod" {
-        ensure!(
-            has_dot_instructions && selection.predicates.len() == 1,
-            "{} dotprod selection must carry only the hasDotInstructions predicate",
-            policy.id
-        );
-    } else if policy.family == "clc" {
-        match policy.clc.as_ref().map(|clc| clc.operation) {
-            Some(ClcOperation::TryCancel) => ensure!(
-                imported_ptx.is_some() && imported_sm.is_some() && selection.predicates.len() == 2,
-                "{} selection must carry exactly its PTX and SM predicates",
-                policy.id
-            ),
-            Some(ClcOperation::TryCancelMulticast) => ensure!(
-                has_clc_multicast_support
-                    && selection.predicates.len() == 1
-                    && parse_hardware_target(policy)?
-                        == CatalogHardwareTarget::AnyOf {
-                            alternatives: vec![
-                                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                                CatalogHardwareAlternative::ExactArchitecture { sm: 120 },
-                                CatalogHardwareAlternative::ExactArchitecture { sm: 121 },
-                            ],
-                        },
-                "{} multicast target predicate must map to the reviewed exact architectures",
-                policy.id
-            ),
-            _ => bail!(
-                "{} query operation unexpectedly has an instruction selection",
-                policy.id
-            ),
-        }
-    } else if policy.family == "tma" {
-        if policy.tma.as_ref().is_some_and(|tma| {
-            matches!(
-                tma.operation,
-                TmaOperation::G2sTile2dMulticastCg2
-                    | TmaOperation::PrefetchTileGather4TwoDimensional
-                    | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint
-            )
-        }) {
-            ensure!(
-                has_tma_blackwell_support
-                    && selection.predicates.len() == 1
-                    && parse_hardware_target(policy)?
-                        == CatalogHardwareTarget::AnyOf {
-                            alternatives: vec![
-                                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                            ],
-                        },
-                "{} Blackwell TMA predicate must map to the reviewed exact architectures",
-                policy.id
-            );
-        } else {
-            ensure!(
-                imported_ptx.is_some() && imported_sm.is_some() && selection.predicates.len() == 2,
-                "{} TMA selection must carry exactly its PTX and SM predicates",
-                policy.id
-            );
-        }
-    } else if policy.family == "tcgen05" {
-        let shift = policy.tcgen05.as_ref().is_some_and(|tcgen05| {
-            matches!(
-                tcgen05.operation,
-                Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2
-            )
-        });
-        ensure!(
-            ((shift && has_tcgen05_shift_support && !has_tcgen05_support)
-                || (!shift && has_tcgen05_support && !has_tcgen05_shift_support))
-                && selection.predicates.len() == 1
-                && parse_hardware_target(policy)?
-                    == CatalogHardwareTarget::AnyOf {
-                        alternatives: vec![
-                            CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                            CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                            CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                            CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                        ],
-                    },
-            "{} tcgen05 selection must use the reviewed accelerated architectures",
-            policy.id
-        );
-    } else if matches!(
-        policy.family.as_str(),
-        "vote"
-            | "active_mask"
-            | "warp_match"
-            | "elect"
-            | "warp_barrier"
-            | "warp_shuffle"
-            | "cp_async_copy"
-            | "cp_async_control"
-            | "mbarrier_basic"
-            | "cluster_barrier"
-            | "scalar_conversion"
-            | "grid_dependency"
-    ) {
-        ensure!(
-            imported_ptx.is_some() && imported_sm.is_some() && selection.predicates.len() == 2,
-            "{} selection must carry exactly its PTX and SM predicates",
-            policy.id
-        );
-    }
-    Ok(())
-}
-
-const REVIEWED_SPECIAL_REGISTERS: [SpecialRegisterKind; 12] = [
-    SpecialRegisterKind::Clock,
-    SpecialRegisterKind::Clock64,
-    SpecialRegisterKind::Globaltimer,
-    SpecialRegisterKind::Envreg1,
-    SpecialRegisterKind::Envreg2,
-    SpecialRegisterKind::Smid,
-    SpecialRegisterKind::Nsmid,
-    SpecialRegisterKind::Gridid,
-    SpecialRegisterKind::Warpid,
-    SpecialRegisterKind::Nwarpid,
-    SpecialRegisterKind::DynamicSmemSize,
-    SpecialRegisterKind::TotalSmemSize,
-];
-
-#[derive(Clone, Copy)]
-struct SpecialRegisterRecipe {
-    kind: SpecialRegisterKind,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: Option<&'static str>,
-    llvm_symbol: Option<&'static str>,
-    rust_module: &'static str,
-    compatibility_paths: &'static [&'static str],
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    register_spelling: &'static str,
-    observation: SpecialRegisterObservation,
-    result_width: SpecialRegisterWidth,
-    ptx_type: SpecialRegisterPtxType,
-    output_constraint: SpecialRegisterOutputConstraint,
-    llvm_mechanism: BackendLoweringMechanism,
-    libnvvm_mechanism: BackendLoweringMechanism,
-    minimum_ptx: &'static str,
-    minimum_sm: Option<&'static str>,
-    execution_scope: &'static str,
-    ptx_isa_section: &'static str,
-    ptx_isa_url: &'static str,
-    selection_record: Option<&'static str>,
-    selection_asm: Option<&'static str>,
-    summary: &'static str,
-}
-
-fn special_register_recipe(kind: SpecialRegisterKind) -> SpecialRegisterRecipe {
-    use BackendLoweringMechanism::{InlinePtx, TypedNvvm};
-    use SpecialRegisterKind::*;
-    use SpecialRegisterObservation::{StablePure, VolatileObservation};
-    use SpecialRegisterOutputConstraint::{Register32, Register64};
-    use SpecialRegisterPtxType::{B32, U32, U64};
-    use SpecialRegisterWidth::{B32 as Width32, B64 as Width64};
-
-    match kind {
-        Clock => SpecialRegisterRecipe {
-            kind,
-            id: "clock",
-            operation_key: "debug.clock",
-            source_record: Some("int_nvvm_read_ptx_sreg_clock"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.clock"),
-            rust_module: "debug",
-            compatibility_paths: &["cuda_device::debug::clock"],
-            dialect_op_type: "ReadPtxSregClockOp",
-            dialect_op_name: "nvvm.read_ptx_sreg_clock",
-            register_spelling: "%clock",
-            observation: VolatileObservation,
-            result_width: Width32,
-            ptx_type: U32,
-            output_constraint: Register32,
-            llvm_mechanism: TypedNvvm,
-            libnvvm_mechanism: TypedNvvm,
-            minimum_ptx: "1.0",
-            minimum_sm: None,
-            execution_scope: "sm",
-            ptx_isa_section: "10.23 Special Registers: %clock, %clock_hi",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-clock-clock-hi",
-            selection_record: Some("SREG_CLOCK"),
-            selection_asm: Some("mov.u32 \t$d, %clock;"),
-            summary: "Samples the current SM's 32-bit clock counter.",
-        },
-        Clock64 => SpecialRegisterRecipe {
-            kind,
-            id: "clock64",
-            operation_key: "debug.clock64",
-            source_record: Some("int_nvvm_read_ptx_sreg_clock64"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.clock64"),
-            rust_module: "debug",
-            compatibility_paths: &["cuda_device::debug::clock64"],
-            dialect_op_type: "ReadPtxSregClock64Op",
-            dialect_op_name: "nvvm.read_ptx_sreg_clock64",
-            register_spelling: "%clock64",
-            observation: VolatileObservation,
-            result_width: Width64,
-            ptx_type: U64,
-            output_constraint: Register64,
-            llvm_mechanism: TypedNvvm,
-            libnvvm_mechanism: TypedNvvm,
-            minimum_ptx: "2.0",
-            minimum_sm: Some("sm_20"),
-            execution_scope: "sm",
-            ptx_isa_section: "10.24 Special Registers: %clock64",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-clock64",
-            selection_record: Some("SREG_CLOCK64"),
-            selection_asm: Some("mov.u64 \t$d, %clock64;"),
-            summary: "Samples the current SM's 64-bit clock counter.",
-        },
-        Globaltimer => SpecialRegisterRecipe {
-            kind,
-            id: "globaltimer",
-            operation_key: "debug.global_timer",
-            source_record: Some("int_nvvm_read_ptx_sreg_globaltimer"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.globaltimer"),
-            rust_module: "debug",
-            compatibility_paths: &["cuda_device::debug::globaltimer"],
-            dialect_op_type: "ReadPtxSregGlobaltimerOp",
-            dialect_op_name: "nvvm.read_ptx_sreg_globaltimer",
-            register_spelling: "%globaltimer",
-            observation: VolatileObservation,
-            result_width: Width64,
-            ptx_type: U64,
-            output_constraint: Register64,
-            llvm_mechanism: TypedNvvm,
-            libnvvm_mechanism: InlinePtx,
-            minimum_ptx: "3.1",
-            minimum_sm: Some("sm_30"),
-            execution_scope: "device",
-            ptx_isa_section: "10.28 Special Registers: %globaltimer, %globaltimer_lo, %globaltimer_hi",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-globaltimer",
-            selection_record: Some("SREG_GLOBALTIMER"),
-            selection_asm: Some("mov.u64 \t$d, %globaltimer;"),
-            summary: "Samples the device-wide 64-bit global timer.",
-        },
-        Envreg1 => SpecialRegisterRecipe {
-            kind,
-            id: "envreg1",
-            operation_key: "grid.environment_register.1",
-            source_record: Some("int_nvvm_read_ptx_sreg_envreg1"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.envreg1"),
-            rust_module: "grid",
-            compatibility_paths: &["cuda_device::grid::envreg1"],
-            dialect_op_type: "ReadPtxSregEnvReg1Op",
-            dialect_op_name: "nvvm.read_ptx_sreg_envreg1",
-            register_spelling: "%envreg1",
-            observation: StablePure,
-            result_width: Width32,
-            ptx_type: B32,
-            output_constraint: Register32,
-            llvm_mechanism: TypedNvvm,
-            libnvvm_mechanism: TypedNvvm,
-            minimum_ptx: "2.1",
-            minimum_sm: None,
-            execution_scope: "grid",
-            ptx_isa_section: "10.27 Special Registers: %envreg<32>",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-envreg",
-            selection_record: None,
-            selection_asm: None,
-            summary: "Reads PTX environment register 1.",
-        },
-        Envreg2 => SpecialRegisterRecipe {
-            kind,
-            id: "envreg2",
-            operation_key: "grid.environment_register.2",
-            source_record: Some("int_nvvm_read_ptx_sreg_envreg2"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.envreg2"),
-            rust_module: "grid",
-            compatibility_paths: &["cuda_device::grid::envreg2"],
-            dialect_op_type: "ReadPtxSregEnvReg2Op",
-            dialect_op_name: "nvvm.read_ptx_sreg_envreg2",
-            register_spelling: "%envreg2",
-            observation: StablePure,
-            result_width: Width32,
-            ptx_type: B32,
-            output_constraint: Register32,
-            llvm_mechanism: TypedNvvm,
-            libnvvm_mechanism: TypedNvvm,
-            minimum_ptx: "2.1",
-            minimum_sm: None,
-            execution_scope: "grid",
-            ptx_isa_section: "10.27 Special Registers: %envreg<32>",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-envreg",
-            selection_record: None,
-            selection_asm: None,
-            summary: "Reads PTX environment register 2.",
-        },
-        Smid => SpecialRegisterRecipe {
-            kind,
-            id: "smid",
-            operation_key: "execution.sm_identifier",
-            source_record: Some("int_nvvm_read_ptx_sreg_smid"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.smid"),
-            rust_module: "thread",
-            compatibility_paths: &["cuda_device::thread::smid", "cuda_device::smid"],
-            dialect_op_type: "ReadPtxSregSmIdOp",
-            dialect_op_name: "nvvm.read_ptx_sreg_smid",
-            register_spelling: "%smid",
-            observation: VolatileObservation,
-            result_width: Width32,
-            ptx_type: U32,
-            output_constraint: Register32,
-            llvm_mechanism: InlinePtx,
-            libnvvm_mechanism: InlinePtx,
-            minimum_ptx: "1.3",
-            minimum_sm: None,
-            execution_scope: "thread",
-            ptx_isa_section: "10.8 Special Registers: %smid",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-smid",
-            selection_record: Some("SREG_SMID"),
-            selection_asm: Some("mov.u32 \t$d, %smid;"),
-            summary: "Samples the SM currently executing this thread.",
-        },
-        Nsmid => SpecialRegisterRecipe {
-            kind,
-            id: "nsmid",
-            operation_key: "execution.sm_identifier_bound",
-            source_record: Some("int_nvvm_read_ptx_sreg_nsmid"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.nsmid"),
-            rust_module: "thread",
-            compatibility_paths: &["cuda_device::thread::nsmid", "cuda_device::nsmid"],
-            dialect_op_type: "ReadPtxSregNsmIdOp",
-            dialect_op_name: "nvvm.read_ptx_sreg_nsmid",
-            register_spelling: "%nsmid",
-            observation: StablePure,
-            result_width: Width32,
-            ptx_type: U32,
-            output_constraint: Register32,
-            llvm_mechanism: TypedNvvm,
-            libnvvm_mechanism: TypedNvvm,
-            minimum_ptx: "2.0",
-            minimum_sm: Some("sm_20"),
-            execution_scope: "device",
-            ptx_isa_section: "10.9 Special Registers: %nsmid",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-nsmid",
-            selection_record: Some("SREG_NSMID"),
-            selection_asm: Some("mov.u32 \t$d, %nsmid;"),
-            summary: "Returns the upper bound for SM identifiers.",
-        },
-        Gridid => SpecialRegisterRecipe {
-            kind,
-            id: "gridid",
-            operation_key: "launch.grid_identifier",
-            source_record: None,
-            llvm_symbol: None,
-            rust_module: "thread",
-            compatibility_paths: &["cuda_device::thread::gridid", "cuda_device::gridid"],
-            dialect_op_type: "ReadPtxSregGridIdOp",
-            dialect_op_name: "nvvm.read_ptx_sreg_gridid",
-            register_spelling: "%gridid",
-            observation: StablePure,
-            result_width: Width64,
-            ptx_type: U64,
-            output_constraint: Register64,
-            llvm_mechanism: InlinePtx,
-            libnvvm_mechanism: InlinePtx,
-            minimum_ptx: "3.0",
-            minimum_sm: Some("sm_30"),
-            execution_scope: "grid",
-            ptx_isa_section: "10.10 Special Registers: %gridid",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-gridid",
-            selection_record: None,
-            selection_asm: None,
-            summary: "Returns the full 64-bit temporal grid identifier.",
-        },
-        Warpid => SpecialRegisterRecipe {
-            kind,
-            id: "warpid",
-            operation_key: "warp.hardware_identifier",
-            source_record: Some("int_nvvm_read_ptx_sreg_warpid"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.warpid"),
-            rust_module: "warp",
-            compatibility_paths: &["cuda_device::warp::warpid"],
-            dialect_op_type: "ReadPtxSregWarpIdOp",
-            dialect_op_name: "nvvm.read_ptx_sreg_warpid",
-            register_spelling: "%warpid",
-            observation: VolatileObservation,
-            result_width: Width32,
-            ptx_type: U32,
-            output_constraint: Register32,
-            llvm_mechanism: InlinePtx,
-            libnvvm_mechanism: InlinePtx,
-            minimum_ptx: "1.3",
-            minimum_sm: None,
-            execution_scope: "cta",
-            ptx_isa_section: "10.4 Special Registers: %warpid",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-warpid",
-            selection_record: Some("SREG_WARPID"),
-            selection_asm: Some("mov.u32 \t$d, %warpid;"),
-            summary: "Samples the hardware warp currently executing this thread.",
-        },
-        Nwarpid => SpecialRegisterRecipe {
-            kind,
-            id: "nwarpid",
-            operation_key: "warp.hardware_identifier_bound",
-            source_record: Some("int_nvvm_read_ptx_sreg_nwarpid"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.nwarpid"),
-            rust_module: "warp",
-            compatibility_paths: &["cuda_device::warp::nwarpid"],
-            dialect_op_type: "ReadPtxSregNwarpIdOp",
-            dialect_op_name: "nvvm.read_ptx_sreg_nwarpid",
-            register_spelling: "%nwarpid",
-            observation: StablePure,
-            result_width: Width32,
-            ptx_type: U32,
-            output_constraint: Register32,
-            llvm_mechanism: TypedNvvm,
-            libnvvm_mechanism: TypedNvvm,
-            minimum_ptx: "2.0",
-            minimum_sm: Some("sm_20"),
-            execution_scope: "cta",
-            ptx_isa_section: "10.5 Special Registers: %nwarpid",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-nwarpid",
-            selection_record: Some("SREG_NWARPID"),
-            selection_asm: Some("mov.u32 \t$d, %nwarpid;"),
-            summary: "Returns the upper bound for hardware warp identifiers.",
-        },
-        DynamicSmemSize => SpecialRegisterRecipe {
-            kind,
-            id: "dynamic_smem_size",
-            operation_key: "shared.dynamic_size",
-            source_record: Some("int_nvvm_read_ptx_sreg_dynamic_smem_size"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.dynamic_smem_size"),
-            rust_module: "shared",
-            compatibility_paths: &["cuda_device::shared::dynamic_smem_size"],
-            dialect_op_type: "ReadPtxSregDynamicSmemSizeOp",
-            dialect_op_name: "nvvm.read_ptx_sreg_dynamic_smem_size",
-            register_spelling: "%dynamic_smem_size",
-            observation: StablePure,
-            result_width: Width32,
-            ptx_type: U32,
-            output_constraint: Register32,
-            llvm_mechanism: InlinePtx,
-            libnvvm_mechanism: InlinePtx,
-            minimum_ptx: "4.1",
-            minimum_sm: Some("sm_20"),
-            execution_scope: "cta",
-            ptx_isa_section: "10.32 Special Registers: %dynamic_smem_size",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-dynamic-smem-size",
-            selection_record: Some("INT_PTX_SREG_DYNAMIC_SMEM_SIZE"),
-            selection_asm: Some("mov.u32 \t$d, %dynamic_smem_size;"),
-            summary: "Returns the launch-time dynamic shared-memory size in bytes.",
-        },
-        TotalSmemSize => SpecialRegisterRecipe {
-            kind,
-            id: "total_smem_size",
-            operation_key: "shared.total_size",
-            source_record: Some("int_nvvm_read_ptx_sreg_total_smem_size"),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.total_smem_size"),
-            rust_module: "shared",
-            compatibility_paths: &["cuda_device::shared::total_smem_size"],
-            dialect_op_type: "ReadPtxSregTotalSmemSizeOp",
-            dialect_op_name: "nvvm.read_ptx_sreg_total_smem_size",
-            register_spelling: "%total_smem_size",
-            observation: StablePure,
-            result_width: Width32,
-            ptx_type: U32,
-            output_constraint: Register32,
-            llvm_mechanism: InlinePtx,
-            libnvvm_mechanism: InlinePtx,
-            minimum_ptx: "4.1",
-            minimum_sm: Some("sm_20"),
-            execution_scope: "cta",
-            ptx_isa_section: "10.30 Special Registers: %total_smem_size",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-total-smem-size",
-            selection_record: Some("INT_PTX_SREG_TOTAL_SMEM_SIZE"),
-            selection_asm: Some("mov.u32 \t$d, %total_smem_size;"),
-            summary: "Returns the total user shared-memory allocation in bytes.",
-        },
-    }
-}
-
-fn special_register_ptx_type(ptx_type: SpecialRegisterPtxType) -> &'static str {
-    match ptx_type {
-        SpecialRegisterPtxType::B32 => "b32",
-        SpecialRegisterPtxType::U32 => "u32",
-        SpecialRegisterPtxType::U64 => "u64",
-    }
-}
-
-fn special_register_backend_floor(
-    recipe: SpecialRegisterRecipe,
-    backend: IntrinsicBackend,
-) -> (Option<&'static str>, Option<&'static str>) {
-    match backend {
-        IntrinsicBackend::LlvmNvptx => {
-            let minimum_ptx = if matches!(recipe.minimum_ptx, "4.1") {
-                "4.1"
-            } else {
-                "3.2"
-            };
-            let minimum_sm = if recipe.minimum_sm == Some("sm_30") {
-                "sm_30"
-            } else {
-                "sm_20"
-            };
-            (Some(minimum_ptx), Some(minimum_sm))
-        }
-        IntrinsicBackend::LibNvvm => (None, Some("sm_75")),
-    }
-}
-
-fn special_register_contract(recipe: SpecialRegisterRecipe) -> SpecialRegister {
-    let llvm_exclusion =
-        (recipe.kind == SpecialRegisterKind::Gridid).then(|| SpecialRegisterLlvmExclusion {
-            source_record: "int_nvvm_read_ptx_sreg_gridid".into(),
-            llvm_symbol: "llvm.nvvm.read.ptx.sreg.gridid".into(),
-            imported_result_width: SpecialRegisterWidth::B32,
-            reason: SpecialRegisterLlvmExclusionReason::ResultWidthMismatch,
-        });
-    SpecialRegister {
-        register: recipe.kind,
-        observation: recipe.observation,
-        result_width: recipe.result_width,
-        ptx_type: recipe.ptx_type,
-        output_constraint: recipe.output_constraint,
-        llvm_exclusion,
-    }
-}
-
-fn expand_special_register_admission(
-    admission: &SpecialRegisterAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "special-register runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact special-register admission requires both backend evidence profiles"
-    );
-    ensure!(
-        admission.registers == REVIEWED_SPECIAL_REGISTERS
-            && admission.product_count == REVIEWED_SPECIAL_REGISTERS.len(),
-        "compact special-register admission must list the canonical 12 registers exactly once and in order"
-    );
-
-    admission
-        .registers
-        .iter()
-        .copied()
-        .map(|kind| {
-            let recipe = special_register_recipe(kind);
-            let width = recipe.result_width.bits();
-            let rust_result = format!("u{width}");
-            let dialect_result = format!("i{width}");
-            let source = match recipe.source_record {
-                Some(_) => None,
-                None => Some(IntrinsicSource::PtxNative {
-                    instruction: format!(
-                        "mov.{} {}",
-                        special_register_ptx_type(recipe.ptx_type),
-                        recipe.register_spelling
-                    ),
-                }),
-            };
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: String::new(),
-                operation_key: recipe.operation_key.into(),
-                family: "sreg".into(),
-                source,
-                source_record: recipe.source_record.map(str::to_owned),
-                rust_module: recipe.rust_module.into(),
-                rust_name: recipe.id.into(),
-                rust_arguments: vec![],
-                rust_result: rust_result.clone(),
-                safe: true,
-                must_use: false,
-                safe_allowlist_reason: Some(
-                    "reading this special register has no caller obligations.".into(),
-                ),
-                public_rust_path: format!("cuda_intrinsics::{}::{}", recipe.rust_module, recipe.id),
-                compatibility_rust_paths: recipe
-                    .compatibility_paths
-                    .iter()
-                    .map(|path| (*path).into())
-                    .collect(),
-                dialect_op_type: recipe.dialect_op_type.into(),
-                dialect_op_name: recipe.dialect_op_name.into(),
-                dialect_operands: vec![],
-                dialect_results: vec![dialect_result.clone()],
-                llvm_symbol: recipe.llvm_symbol.map(str::to_owned),
-                resolved_llvm_symbol: None,
-                llvm_arguments: vec![],
-                llvm_results: recipe
-                    .source_record
-                    .map(|_| dialect_result)
-                    .into_iter()
-                    .collect(),
-                pure: recipe.observation == SpecialRegisterObservation::StablePure,
-                memory: if matches!(
-                    recipe.kind,
-                    SpecialRegisterKind::Clock
-                        | SpecialRegisterKind::Clock64
-                        | SpecialRegisterKind::Globaltimer
-                ) {
-                    "inaccessible_read_write".into()
-                } else {
-                    "none".into()
-                },
-                convergent: false,
-                execution_scope: recipe.execution_scope.into(),
-                minimum_ptx: recipe.minimum_ptx.into(),
-                minimum_sm: recipe.minimum_sm.map(str::to_owned),
-                ptx_result: rust_result,
-                targets: "all".into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section: recipe.ptx_isa_section.into(),
-                ptx_isa_url: recipe.ptx_isa_url.into(),
-                lowering: "generated_special_register".into(),
-                backend_lowerings: [
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        recipe.llvm_mechanism,
-                        &admission.llvm_evidence_profile,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        recipe.libnvvm_mechanism,
-                        &admission.libnvvm_evidence_profile,
-                    ),
-                ]
-                .into_iter()
-                .map(
-                    |(backend, mechanism, evidence_profile)| OverlayBackendLowering {
-                        minimum_ptx: special_register_backend_floor(recipe, backend)
-                            .0
-                            .map(str::to_owned),
-                        minimum_sm: special_register_backend_floor(recipe, backend)
-                            .1
-                            .map(str::to_owned),
-                        backend,
-                        mechanism,
-                        evidence_profile: evidence_profile.clone(),
-                        targets: None,
-                    },
-                )
-                .collect(),
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: Some(special_register_contract(recipe)),
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: "mov".into(),
-                    modifiers: vec![special_register_ptx_type(recipe.ptx_type).into()],
-                    operands: vec![
-                        OperandPattern::Register,
-                        OperandPattern::Exact {
-                            value: recipe.register_spelling.into(),
-                        },
-                    ],
-                },
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect()
-}
-
-fn validate_special_register_policy(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-    declaration: Option<&ImportedIntrinsic>,
-) -> Result<()> {
-    let special = policy
-        .special_register
-        .as_ref()
-        .with_context(|| format!("{} has no closed special-register contract", policy.id))?;
-    let recipe = special_register_recipe(special.register);
-    ensure!(
-        special == &special_register_contract(recipe),
-        "{} special-register width, PTX type, constraint, observation, or LLVM exclusion changed",
-        policy.id
-    );
-    let expected_source = match recipe.source_record {
-        Some(source_record) => IntrinsicSource::LlvmImported {
-            source_record: source_record.into(),
-        },
-        None => IntrinsicSource::PtxNative {
-            instruction: format!(
-                "mov.{} {}",
-                special_register_ptx_type(recipe.ptx_type),
-                recipe.register_spelling
-            ),
-        },
-    };
-    ensure!(
-        policy.id == recipe.id
-            && policy.operation_key == recipe.operation_key
-            && source == &expected_source
-            && policy.source_record.as_deref() == recipe.source_record
-            && policy.llvm_symbol.as_deref() == recipe.llvm_symbol
-            && policy.resolved_llvm_symbol.is_none()
-            && policy.llvm_arguments.is_empty(),
-        "{} special-register identity or source changed",
-        policy.id
-    );
-    let width = recipe.result_width.bits();
-    let rust_result = format!("u{width}");
-    let dialect_result = format!("i{width}");
-    let expected_llvm_results = recipe
-        .source_record
-        .map(|_| dialect_result.clone())
-        .into_iter()
-        .collect::<Vec<_>>();
-    ensure!(
-        policy.rust_module == recipe.rust_module
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments.is_empty()
-            && policy.rust_result == rust_result
-            && policy.safe
-            && !policy.must_use
-            && policy.public_rust_path
-                == format!("cuda_intrinsics::{}::{}", recipe.rust_module, recipe.id)
-            && policy.compatibility_rust_paths
-                == recipe
-                    .compatibility_paths
-                    .iter()
-                    .map(|path| (*path).to_owned())
-                    .collect::<Vec<_>>(),
-        "{} special-register Rust API changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands.is_empty()
-            && policy.dialect_results == [dialect_result.as_str()]
-            && policy.llvm_results == expected_llvm_results
-            && policy.lowering == "generated_special_register",
-        "{} special-register carrier, result width, or lowering changed",
-        policy.id
-    );
-    let expected_pure = recipe.observation == SpecialRegisterObservation::StablePure;
-    let expected_memory = if matches!(
-        recipe.kind,
-        SpecialRegisterKind::Clock
-            | SpecialRegisterKind::Clock64
-            | SpecialRegisterKind::Globaltimer
-    ) {
-        "inaccessible_read_write"
-    } else {
-        "none"
-    };
-    ensure!(
-        policy.pure == expected_pure
-            && policy.memory == expected_memory
-            && !policy.convergent
-            && policy.execution_scope == recipe.execution_scope,
-        "{} special-register observation or effects changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == recipe.minimum_sm
-            && policy.ptx_result == rust_result
-            && policy.targets == "all"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.ptx_isa_section
-            && policy.ptx_isa_url == recipe.ptx_isa_url,
-        "{} special-register target floor or PTX provenance changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx
-            == InstructionPattern {
-                mnemonic: "mov".into(),
-                modifiers: vec![special_register_ptx_type(recipe.ptx_type).into()],
-                operands: vec![
-                    OperandPattern::Register,
-                    OperandPattern::Exact {
-                        value: recipe.register_spelling.into(),
-                    },
-                ],
-            },
-        "{} special-register PTX shape changed",
-        policy.id
-    );
-    let expected_routes = [
-        (
-            IntrinsicBackend::LlvmNvptx,
-            recipe.llvm_mechanism,
-            special_register_backend_floor(recipe, IntrinsicBackend::LlvmNvptx),
-        ),
-        (
-            IntrinsicBackend::LibNvvm,
-            recipe.libnvvm_mechanism,
-            special_register_backend_floor(recipe, IntrinsicBackend::LibNvvm),
-        ),
-    ];
-    ensure!(
-        policy.backend_lowerings.len() == expected_routes.len()
-            && policy.backend_lowerings.iter().zip(expected_routes).all(
-                |(actual, (backend, mechanism, (minimum_ptx, minimum_sm)))| {
-                    actual.backend == backend
-                        && actual.mechanism == mechanism
-                        && !actual.evidence_profile.trim().is_empty()
-                        && actual.minimum_ptx.as_deref() == minimum_ptx
-                        && actual.minimum_sm.as_deref() == minimum_sm
-                }
-            ),
-        "{} special-register backend routes changed",
-        policy.id
-    );
-    ensure!(
-        policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.cp_async_mbarrier.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.register_mma.is_none()
-            && policy.sparse_mma.is_none()
-            && policy.prmt.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with a special register",
-        policy.id
-    );
-
-    match (recipe.source_record, declaration) {
-        (None, None) => {}
-        (Some(_), Some(declaration)) => {
-            let timer = matches!(
-                recipe.kind,
-                SpecialRegisterKind::Clock
-                    | SpecialRegisterKind::Clock64
-                    | SpecialRegisterKind::Globaltimer
-            );
-            let expected_properties: &[&str] = if timer {
-                &[
-                    "IntrInaccessibleMemOnly",
-                    "IntrNoCallback",
-                    "IntrNoFree",
-                    "IntrWillReturn",
-                    "NoUndef<ret>",
-                ]
-            } else {
-                &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"]
-            };
-            ensure!(
-                declaration.arguments.is_empty()
-                    && declaration.results == [dialect_result.as_str()]
-                    && declaration.properties
-                        == expected_properties
-                            .iter()
-                            .map(|property| (*property).to_owned())
-                            .collect::<Vec<_>>()
-                    && if timer {
-                        declaration
-                            .classes
-                            .iter()
-                            .any(|class| class == "PTXReadNCSRegIntrinsic")
-                    } else {
-                        declaration
-                            .classes
-                            .iter()
-                            .any(|class| class == "NVVMPureIntrinsic")
-                    },
-                "{} imported special-register signature, class, or properties changed",
-                policy.id
-            );
-            match (recipe.selection_record, recipe.selection_asm) {
-                (None, None) => ensure!(
-                    declaration.selections.is_empty(),
-                    "{} selectionless environment-register contract changed",
-                    policy.id
-                ),
-                (Some(selection_record), Some(selection_asm)) => ensure!(
-                    declaration.selections.len() == 1
-                        && declaration.selections[0].source_record == selection_record
-                        && declaration.selections[0].asm == selection_asm
-                        && declaration.selections[0].predicates.is_empty()
-                        && declaration.selections[0].constraints.is_empty(),
-                    "{} imported special-register selection changed",
-                    policy.id
-                ),
-                _ => unreachable!("closed special-register selection recipe"),
-            }
-        }
-        _ => bail!(
-            "{} special-register source and imported declaration disagree",
-            policy.id
-        ),
-    }
-    Ok(())
-}
-
-fn validate_special_register_llvm_exclusion(
-    policy: &OverlayIntrinsic,
-    imported_by_record: &BTreeMap<&str, &ImportedIntrinsic>,
-) -> Result<()> {
-    let Some(exclusion) = policy
-        .special_register
-        .as_ref()
-        .and_then(|special| special.llvm_exclusion.as_ref())
-    else {
-        return Ok(());
-    };
-    let declaration = imported_by_record
-        .get(exclusion.source_record.as_str())
-        .with_context(|| {
-            format!(
-                "{} excludes missing imported LLVM record {}",
-                policy.id, exclusion.source_record
-            )
-        })?;
-    ensure!(
-        policy.id == "gridid"
-            && exclusion.reason == SpecialRegisterLlvmExclusionReason::ResultWidthMismatch
-            && exclusion.imported_result_width == SpecialRegisterWidth::B32
-            && declaration.llvm_name == exclusion.llvm_symbol
-            && declaration.arguments.is_empty()
-            && declaration.results == ["i32"]
-            && declaration.properties == ["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"]
-            && declaration.selections.len() == 1
-            && declaration.selections[0].source_record == "SREG_GRIDID"
-            && declaration.selections[0].asm == "mov.u32 \t$d, %gridid;"
-            && declaration.selections[0].predicates.is_empty()
-            && declaration.selections[0].constraints.is_empty()
-            && policy.rust_result == "u64"
-            && policy.dialect_results == ["i64"],
-        "{} LLVM exclusion no longer proves the reviewed i32-to-u64 gridid width mismatch",
-        policy.id
-    );
-    Ok(())
-}
-
-fn validate_sreg_policy(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-    declaration: Option<&ImportedIntrinsic>,
-) -> Result<()> {
-    if policy.special_register.is_some() {
-        return validate_special_register_policy(policy, source, declaration);
-    }
-    let declaration = declaration.context("sreg requires imported LLVM declaration")?;
-    ensure!(
-        policy.rust_arguments.is_empty() && policy.llvm_arguments.is_empty(),
-        "{} is not a zero-operand intrinsic; the sreg recipe cannot lower it",
-        policy.id
-    );
-    ensure!(
-        matches!(policy.rust_result.as_str(), "u32" | "u64"),
-        "{} has unsupported raw scalar result {}",
-        policy.id,
-        policy.rust_result
-    );
-    let expected_llvm_result = match policy.rust_result.as_str() {
-        "u32" => "i32",
-        "u64" => "i64",
-        _ => unreachable!(),
-    };
-    ensure!(
-        policy.llvm_results == [expected_llvm_result]
-            && policy.ptx_result == policy.rust_result
-            && policy.lowering == "direct_nvvm",
-        "{} has a signature or lowering outside the scalar direct-NVVM sreg recipe",
-        policy.id
-    );
-    ensure!(
-        policy.resolved_llvm_symbol.is_none()
-            && policy.backend_lowerings.is_empty()
-            && policy.special_register.is_none(),
-        "{} uses a backend contract outside the direct-NVVM sreg recipe",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "sreg")?;
-    if policy.id.starts_with("lanemask_") {
-        validate_lanemask_policy(policy, declaration)?;
-    }
-    if is_cluster_sreg_source(&declaration.source_record) {
-        validate_cluster_sreg_policy(policy, declaration)?;
-    }
-    Ok(())
-}
-
-fn is_cluster_sreg_source(source_record: &str) -> bool {
-    source_record == "int_nvvm_read_ptx_sreg_cluster_ctarank"
-        || source_record == "int_nvvm_read_ptx_sreg_cluster_nctarank"
-        || source_record.starts_with("int_nvvm_read_ptx_sreg_cluster_ctaid_")
-        || source_record.starts_with("int_nvvm_read_ptx_sreg_cluster_nctaid_")
-        || source_record.starts_with("int_nvvm_read_ptx_sreg_clusterid_")
-        || source_record.starts_with("int_nvvm_read_ptx_sreg_nclusterid_")
-}
-
-#[derive(Clone)]
-struct ClusterSregRecipe {
-    id: String,
-    operation_key: String,
-    source_suffix: String,
-    llvm_suffix: String,
-    selection_record: String,
-    ptx_register: String,
-    compatibility_path: Option<String>,
-    op_type: String,
-    scope: &'static str,
-    section: &'static str,
-    anchor: &'static str,
-    range: Option<&'static str>,
-    safe_reason: String,
-    summary: String,
-}
-
-#[derive(Clone, Copy)]
-struct ClusterSregXyzFamilyRecipe {
-    id_prefix: &'static str,
-    operation_key_prefix: &'static str,
-    source_prefix: &'static str,
-    llvm_prefix: &'static str,
-    selection_prefix: &'static str,
-    ptx_prefix: &'static str,
-    compatibility_prefix: Option<&'static str>,
-    op_type_prefix: &'static str,
-    scope: &'static str,
-    section: &'static str,
-    anchor: &'static str,
-    x_range: &'static str,
-    yz_range: &'static str,
-    safe_reason: &'static str,
-    summary: &'static str,
-}
-
-const CLUSTER_SREG_AXES: [&str; 3] = ["x", "y", "z"];
-
-const CLUSTER_SREG_XYZ_FAMILIES: [ClusterSregXyzFamilyRecipe; 4] = [
-    ClusterSregXyzFamilyRecipe {
-        id_prefix: "cluster_block_idx",
-        operation_key_prefix: "launch.cluster.block_index",
-        source_prefix: "cluster_ctaid_",
-        llvm_prefix: "cluster.ctaid.",
-        selection_prefix: "INT_PTX_SREG_CLUSTER_CTAID_",
-        ptx_prefix: "%cluster_ctaid.",
-        compatibility_prefix: Some("cuda_device::cluster::cluster_ctaid"),
-        op_type_prefix: "ReadPtxSregClusterCtaid",
-        scope: "cta",
-        section: "10.14 Special Registers: %cluster_ctaid",
-        anchor: "cluster-ctaid",
-        x_range: "Range<ret,0,2147483647>",
-        yz_range: "Range<ret,0,65535>",
-        safe_reason: "reading the read-only block index within its cluster has no caller obligations",
-        summary: "Returns the block's {axis} index within its thread block cluster.",
-    },
-    ClusterSregXyzFamilyRecipe {
-        id_prefix: "cluster_dim",
-        operation_key_prefix: "launch.cluster.dimension",
-        source_prefix: "cluster_nctaid_",
-        llvm_prefix: "cluster.nctaid.",
-        selection_prefix: "INT_PTX_SREG_CLUSTER_NCTAID_",
-        ptx_prefix: "%cluster_nctaid.",
-        compatibility_prefix: Some("cuda_device::cluster::cluster_nctaid"),
-        op_type_prefix: "ReadPtxSregClusterNctaid",
-        scope: "cluster",
-        section: "10.15 Special Registers: %cluster_nctaid",
-        anchor: "cluster-nctaid",
-        x_range: "Range<ret,1,2147483648>",
-        yz_range: "Range<ret,1,65536>",
-        safe_reason: "reading the read-only cluster dimension has no caller obligations",
-        summary: "Returns the number of blocks in the cluster's {axis} dimension.",
-    },
-    ClusterSregXyzFamilyRecipe {
-        id_prefix: "cluster_idx",
-        operation_key_prefix: "launch.cluster.index",
-        source_prefix: "clusterid_",
-        llvm_prefix: "clusterid.",
-        selection_prefix: "INT_PTX_SREG_CLUSTERID_",
-        ptx_prefix: "%clusterid.",
-        compatibility_prefix: Some("cuda_device::cluster::__cluster_idx"),
-        op_type_prefix: "ReadPtxSregClusterId",
-        scope: "cluster",
-        section: "10.12 Special Registers: %clusterid",
-        anchor: "clusterid",
-        x_range: "Range<ret,0,2147483647>",
-        yz_range: "Range<ret,0,65535>",
-        safe_reason: "reading the read-only cluster index has no caller obligations",
-        summary: "Returns the cluster's {axis} index within the grid.",
-    },
-    ClusterSregXyzFamilyRecipe {
-        id_prefix: "cluster_grid_dim",
-        operation_key_prefix: "launch.cluster.grid_dimension",
-        source_prefix: "nclusterid_",
-        llvm_prefix: "nclusterid.",
-        selection_prefix: "INT_PTX_SREG_NCLUSTERID_",
-        ptx_prefix: "%nclusterid.",
-        compatibility_prefix: Some("cuda_device::cluster::__cluster_grid_dim"),
-        op_type_prefix: "ReadPtxSregNclusterId",
-        scope: "grid",
-        section: "10.13 Special Registers: %nclusterid",
-        anchor: "nclusterid",
-        x_range: "Range<ret,1,2147483648>",
-        yz_range: "Range<ret,1,65536>",
-        safe_reason: "reading the read-only cluster-grid dimension has no caller obligations",
-        summary: "Returns the number of clusters in the grid's {axis} dimension.",
-    },
-];
-
-fn cluster_sreg_recipes() -> Vec<ClusterSregRecipe> {
-    let mut recipes = Vec::with_capacity(14);
-    for family in CLUSTER_SREG_XYZ_FAMILIES {
-        for axis in CLUSTER_SREG_AXES {
-            let axis_upper = axis.to_ascii_uppercase();
-            recipes.push(ClusterSregRecipe {
-                id: format!("{}_{axis}", family.id_prefix),
-                operation_key: format!("{}.{axis}", family.operation_key_prefix),
-                source_suffix: format!("{}{axis}", family.source_prefix),
-                llvm_suffix: format!("{}{axis}", family.llvm_prefix),
-                selection_record: format!("{}{axis}", family.selection_prefix),
-                ptx_register: format!("{}{axis}", family.ptx_prefix),
-                compatibility_path: family
-                    .compatibility_prefix
-                    .map(|prefix| format!("{prefix}{axis_upper}")),
-                op_type: format!("{}{axis_upper}Op", family.op_type_prefix),
-                scope: family.scope,
-                section: family.section,
-                anchor: family.anchor,
-                range: Some(if axis == "x" {
-                    family.x_range
-                } else {
-                    family.yz_range
-                }),
-                safe_reason: family.safe_reason.into(),
-                summary: family.summary.replace("{axis}", &axis_upper),
-            });
-        }
-    }
-    recipes.extend([
-        ClusterSregRecipe {
-            id: "cluster_block_rank".into(),
-            operation_key: "launch.cluster.block_rank".into(),
-            source_suffix: "cluster_ctarank".into(),
-            llvm_suffix: "cluster.ctarank".into(),
-            selection_record: "INT_PTX_SREG_CLUSTER_CTARANK".into(),
-            ptx_register: "%cluster_ctarank".into(),
-            compatibility_path: None,
-            op_type: "ReadPtxSregClusterCtarankOp".into(),
-            scope: "cta",
-            section: "10.16 Special Registers: %cluster_ctarank",
-            anchor: "cluster-ctarank",
-            range: None,
-            safe_reason:
-                "reading the read-only block rank within its cluster has no caller obligations"
-                    .into(),
-            summary: "Returns the block's linear rank within its thread block cluster.".into(),
-        },
-        ClusterSregRecipe {
-            id: "cluster_block_count".into(),
-            operation_key: "launch.cluster.block_count".into(),
-            source_suffix: "cluster_nctarank".into(),
-            llvm_suffix: "cluster.nctarank".into(),
-            selection_record: "INT_PTX_SREG_CLUSTER_NCTARANK".into(),
-            ptx_register: "%cluster_nctarank".into(),
-            compatibility_path: None,
-            op_type: "ReadPtxSregClusterNctarankOp".into(),
-            scope: "cluster",
-            section: "10.17 Special Registers: %cluster_nctarank",
-            anchor: "cluster-nctarank",
-            range: None,
-            safe_reason: "reading the read-only block count has no caller obligations".into(),
-            summary: "Returns the total number of blocks in the thread block cluster.".into(),
-        },
-    ]);
-    recipes
-}
-
-fn expand_cluster_sreg_admission(
-    admission: &ClusterSregAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.axes == CLUSTER_SREG_AXES,
-        "cluster-sreg axes must be exactly x, y, z"
-    );
-    ensure!(
-        admission.xyz_product_count == 12 && admission.record_count == 14,
-        "cluster-sreg admission must expand to 12 xyz and 14 total records"
-    );
-    let recipes = cluster_sreg_recipes();
-    ensure!(
-        recipes.len() == admission.record_count,
-        "cluster-sreg recipe count disagrees with its admission"
-    );
-    Ok(recipes.into_iter().map(cluster_sreg_policy).collect())
-}
-
-fn cluster_sreg_policy(recipe: ClusterSregRecipe) -> OverlayIntrinsic {
-    let compatibility_rust_paths = recipe.compatibility_path.iter().cloned().collect();
-    OverlayIntrinsic {
-        id: recipe.id.clone(),
-        abi_id: String::new(),
-        operation_key: recipe.operation_key,
-        family: "sreg".into(),
-        source: None,
-        source_record: Some(format!("int_nvvm_read_ptx_sreg_{}", recipe.source_suffix)),
-        rust_module: "sreg".into(),
-        rust_name: recipe.id.clone(),
-        rust_arguments: vec![],
-        rust_result: "u32".into(),
-        safe: true,
-        must_use: false,
-        safe_allowlist_reason: Some(recipe.safe_reason),
-        public_rust_path: format!("cuda_intrinsics::sreg::{}", recipe.id),
-        compatibility_rust_paths,
-        dialect_op_type: recipe.op_type,
-        dialect_op_name: format!("nvvm.read_ptx_sreg_{}", recipe.source_suffix),
-        dialect_operands: vec![],
-        dialect_results: vec![],
-        llvm_symbol: Some(format!("llvm.nvvm.read.ptx.sreg.{}", recipe.llvm_suffix)),
-        resolved_llvm_symbol: None,
-        llvm_arguments: vec![],
-        llvm_results: vec!["i32".into()],
-        pure: true,
-        memory: "none".into(),
-        convergent: false,
-        execution_scope: recipe.scope.into(),
-        minimum_ptx: "7.8".into(),
-        minimum_sm: Some("sm_90".into()),
-        ptx_result: "u32".into(),
-        targets: "all".into(),
-        ptx_isa_version: "9.3".into(),
-        ptx_isa_section: recipe.section.into(),
-        ptx_isa_url: format!(
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-{}",
-            recipe.anchor
-        ),
-        lowering: "direct_nvvm".into(),
-        backend_lowerings: vec![],
-        packed_atomic: None,
-        redux: None,
-        vote: None,
-        active_mask: None,
-        warp_match: None,
-        warp_barrier: None,
-        warp_shuffle: None,
-        dot_product: None,
-        packed_alu: None,
-        integer_minmax: None,
-        packed_conversion: None,
-        scalar_conversion: None,
-        scalar_arithmetic: None,
-        scalar_math: None,
-        extended_minmax: None,
-        cp_async_copy: None,
-        cp_async_control: None,
-        cp_async_mbarrier: None,
-        mbarrier_basic: None,
-        movmatrix: None,
-        mbarrier_extended: None,
-        register_mma: None,
-        sparse_mma: None,
-        prmt: None,
-        cluster_barrier: None,
-        wgmma_control: None,
-        special_register: None,
-        debug_control: None,
-        cluster_memory: None,
-        clc: None,
-        tma: None,
-        tcgen05: None,
-        ldmatrix_variant: None,
-        ldmatrix_safety: None,
-        ldmatrix_adapter: None,
-        selected_address_space: None,
-        expected_ptx: InstructionPattern {
-            mnemonic: "mov".into(),
-            modifiers: vec!["u32".into()],
-            operands: vec![
-                OperandPattern::Register,
-                OperandPattern::Exact {
-                    value: recipe.ptx_register,
-                },
-            ],
-        },
-        summary: recipe.summary,
-    }
-}
-
-fn validate_cluster_sreg_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    ensure!(
-        !declaration.source_record.ends_with("_w"),
-        "{} selects an unused always-zero fourth cluster-register component",
-        policy.id
-    );
-    let recipe = cluster_sreg_recipes()
-        .into_iter()
-        .find(|recipe| recipe.id == policy.id)
-        .with_context(|| format!("{} is not a reviewed cluster special register", policy.id))?;
-
-    let source_record = format!("int_nvvm_read_ptx_sreg_{}", recipe.source_suffix);
-    let llvm_symbol = format!("llvm.nvvm.read.ptx.sreg.{}", recipe.llvm_suffix);
-    let compatibility_paths = recipe
-        .compatibility_path
-        .iter()
-        .cloned()
-        .collect::<Vec<_>>();
-    ensure!(
-        policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(source_record.as_str())
-            && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} cluster-register identity does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "sreg"
-            && policy.rust_name == policy.id
-            && policy.rust_arguments.is_empty()
-            && policy.rust_result == "u32"
-            && policy.safe
-            && !policy.must_use
-            && policy
-                .safe_allowlist_reason
-                .as_deref()
-                .is_some_and(|reason| !reason.is_empty())
-            && policy.public_rust_path == format!("cuda_intrinsics::sreg::{}", policy.id)
-            && policy.compatibility_rust_paths == compatibility_paths,
-        "{} must preserve its reviewed raw and compatibility APIs",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.op_type
-            && policy.dialect_op_name == format!("nvvm.read_ptx_sreg_{}", recipe.source_suffix)
-            && policy.dialect_operands.is_empty()
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments.is_empty()
-            && policy.llvm_results == ["i32"]
-            && policy.lowering == "direct_nvvm",
-        "{} is outside the closed cluster-register lowering recipe",
-        policy.id
-    );
-    ensure!(
-        policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == recipe.scope
-            && policy.minimum_ptx == "7.8"
-            && policy.minimum_sm.as_deref() == Some("sm_90")
-            && policy.ptx_result == "u32"
-            && policy.targets == "all",
-        "{} cluster-register effects or target floor disagree with PTX",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.section
-            && policy.ptx_isa_url
-                == format!(
-                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-{}",
-                    recipe.anchor
-                ),
-        "{} cluster-register PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    let mut properties = vec!["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"];
-    properties.extend(recipe.range);
-    ensure!(
-        declaration.arguments.is_empty()
-            && declaration.results == ["i32"]
-            && declaration.classes
-                == [
-                    "SDPatternOperator",
-                    "Intrinsic",
-                    "DefaultAttrsIntrinsic",
-                    "NVVMPureIntrinsic",
-                    "PTXReadSRegIntrinsicNB_r32",
-                ]
-            && declaration.properties == properties,
-        "{} declaration shape or properties disagree with LLVM TableGen",
-        policy.id
-    );
-    let [selection] = declaration.selections.as_slice() else {
-        bail!("{} must have exactly one LLVM selection", policy.id);
-    };
-    ensure!(
-        selection.source_record == recipe.selection_record
-            && selection.asm == format!("mov.u32 \t$d, {};", recipe.ptx_register)
-            && selection.predicates
-                == [
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78",
-                ]
-            && selection.constraints.address_space.is_none()
-            && selection.constraints.immediate_bindings.is_empty(),
-        "{} selector disagrees with LLVM TableGen",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "mov"
-            && policy.expected_ptx.modifiers == ["u32"]
-            && policy.expected_ptx.operands
-                == [
-                    OperandPattern::Register,
-                    OperandPattern::Exact {
-                        value: recipe.ptx_register,
-                    },
-                ],
-        "{} expected PTX does not match its cluster register",
-        policy.id
-    );
-    Ok(())
-}
-
-fn validate_lanemask_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let (suffix, abi_id, section, op_type) = match policy.id.as_str() {
-        "lanemask_lt" => ("lt", "i0035", "10.13", "ReadPtxSregLanemaskLtOp"),
-        "lanemask_le" => ("le", "i0036", "10.12", "ReadPtxSregLanemaskLeOp"),
-        "lanemask_eq" => ("eq", "i0037", "10.11", "ReadPtxSregLanemaskEqOp"),
-        "lanemask_ge" => ("ge", "i0038", "10.14", "ReadPtxSregLanemaskGeOp"),
-        "lanemask_gt" => ("gt", "i0039", "10.15", "ReadPtxSregLanemaskGtOp"),
-        _ => bail!("{} is not a reviewed lane-mask special register", policy.id),
-    };
-    ensure!(
-        policy.abi_id == abi_id
-            && policy.operation_key == format!("warp.lane_mask.{suffix}")
-            && policy.source.is_none()
-            && policy.source_record.as_deref()
-                == Some(format!("int_nvvm_read_ptx_sreg_lanemask_{suffix}").as_str())
-            && policy.llvm_symbol.as_deref()
-                == Some(format!("llvm.nvvm.read.ptx.sreg.lanemask.{suffix}").as_str())
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} lane-mask identity does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "sreg"
-            && policy.rust_name == policy.id
-            && policy.rust_arguments.is_empty()
-            && policy.rust_result == "u32"
-            && policy.safe
-            && policy.must_use
-            && policy
-                .safe_allowlist_reason
-                .as_deref()
-                .is_some_and(|reason| !reason.is_empty())
-            && policy.public_rust_path == format!("cuda_intrinsics::sreg::{}", policy.id)
-            && policy.compatibility_rust_paths == [format!("cuda_device::warp::{}", policy.id)],
-        "{} must preserve its safe must-use raw and compatibility APIs",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == op_type
-            && policy.dialect_op_name == format!("nvvm.read_ptx_sreg_lanemask_{suffix}")
-            && policy.dialect_operands.is_empty()
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments.is_empty()
-            && policy.llvm_results == ["i32"]
-            && policy.lowering == "direct_nvvm",
-        "{} is outside the closed lane-mask lowering recipe",
-        policy.id
-    );
-    ensure!(
-        policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == "2.0"
-            && policy.minimum_sm.as_deref() == Some("sm_20")
-            && policy.ptx_result == "u32"
-            && policy.targets == "all",
-        "{} lane-mask effects or target floor disagree with PTX",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == format!("{section} Special Registers: %lanemask_{suffix}")
-            && policy.ptx_isa_url
-                == format!(
-                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-lanemask-{suffix}"
-                ),
-        "{} lane-mask PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.properties == ["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-        "{} lane-mask properties disagree with the imported LLVM declaration",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "mov"
-            && policy.expected_ptx.modifiers == ["u32"]
-            && policy.expected_ptx.operands
-                == [
-                    OperandPattern::Register,
-                    OperandPattern::Exact {
-                        value: format!("%lanemask_{suffix}"),
-                    },
-                ],
-        "{} expected PTX does not match its lane-mask register",
-        policy.id
-    );
-    Ok(())
-}
-
-fn validate_redux_policy(policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic) -> Result<()> {
-    let redux = policy
-        .redux
-        .as_ref()
-        .with_context(|| format!("{} has no closed redux contract", policy.id))?;
-    let recipe = redux_recipe(redux.operation);
-    ensure!(
-        redux.participation
-            == ReduxParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask
-            && redux.adapter == ReduxAdapter::MaskValueToSourceMemberMask,
-        "{} requests an unsupported redux participation contract or operand adapter",
-        policy.id
-    );
-    ensure!(
-        policy.id == recipe.id
-            && policy.operation_key == recipe.operation_key
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} redux identity does not match its closed operation recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "warp"
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == ["u32", recipe.rust_value]
-            && policy.rust_result == recipe.rust_value
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::warp::{}", recipe.rust_name)
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::warp::{}", recipe.rust_name)],
-        "{} must preserve the unsafe must-use redux raw API and legacy cuda-device compatibility DefPath",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == ["i32", recipe.value_type]
-            && policy.dialect_results == [recipe.value_type]
-            && policy.llvm_arguments == [recipe.value_type, "i32"]
-            && policy.llvm_results == [recipe.value_type]
-            && policy.lowering == "generated_redux",
-        "{} is outside the generated two-operand redux recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "inaccessible_read_write"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == recipe.minimum_sm
-            && policy.ptx_result == recipe.rust_value
-            && policy.targets == recipe.targets,
-        "{} redux effects, carrier, or target floor disagree with its operation recipe",
-        policy.id
-    );
-    ensure!(
-        declaration
-            .properties
-            .iter()
-            .any(|property| property == "IntrConvergent")
-            && declaration
-                .properties
-                .iter()
-                .any(|property| property == "IntrInaccessibleMemOnly")
-            && declaration
-                .properties
-                .iter()
-                .any(|property| property == "IntrNoCallback")
-            && !declaration.properties.iter().any(|property| matches!(
-                property.as_str(),
-                "IntrNoMem" | "IntrReadMem" | "IntrWriteMem"
-            )),
-        "{} redux memory and convergence effects disagree with the imported declaration",
-        policy.id
-    );
-    ensure!(
-        policy.backend_lowerings.is_empty()
-            && policy.packed_atomic.is_none()
-            && policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with redux",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "redux"
-            && policy.expected_ptx.modifiers == recipe.ptx_modifiers
-            && policy.expected_ptx.operands
-                == [
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                ],
-        "{} expected PTX does not match its closed redux operation recipe",
-        policy.id
-    );
-    Ok(())
-}
-
-// Pinned LLVM's hasReduxSyncF32(): accel {100} at PTX 8.6, family {100} at
-// PTX 8.8. The catalog carries the accel floor with the a/f target union.
-const REDUX_F32_TARGETS: &str = "sm_100a|sm_100f|sm_103a|sm_103f";
-
-struct ReduxRecipe {
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    rust_name: &'static str,
-    rust_value: &'static str,
-    value_type: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    ptx_modifiers: &'static [&'static str],
-    minimum_ptx: &'static str,
-    minimum_sm: Option<&'static str>,
-    targets: &'static str,
-}
-
-fn redux_recipe(operation: ReduxOperation) -> ReduxRecipe {
-    match operation {
-        ReduxOperation::Add => ReduxRecipe {
-            id: "redux_sync_add",
-            operation_key: "warp.redux.sync.add.wrap32",
-            source_record: "int_nvvm_redux_sync_add",
-            llvm_symbol: "llvm.nvvm.redux.sync.add",
-            rust_name: "redux_sync_add",
-            rust_value: "u32",
-            value_type: "i32",
-            dialect_op_type: "ReduxSyncAddOp",
-            dialect_op_name: "nvvm.redux_sync_add",
-            ptx_modifiers: &["sync", "add", "s32"],
-            minimum_ptx: "7.0",
-            minimum_sm: Some("sm_80"),
-            targets: "all",
-        },
-        ReduxOperation::Umin => ReduxRecipe {
-            id: "redux_sync_min_u32",
-            operation_key: "warp.redux.sync.min.u32",
-            source_record: "int_nvvm_redux_sync_umin",
-            llvm_symbol: "llvm.nvvm.redux.sync.umin",
-            rust_name: "redux_sync_min_u32",
-            rust_value: "u32",
-            value_type: "i32",
-            dialect_op_type: "ReduxSyncUminOp",
-            dialect_op_name: "nvvm.redux_sync_umin",
-            ptx_modifiers: &["sync", "min", "u32"],
-            minimum_ptx: "7.0",
-            minimum_sm: Some("sm_80"),
-            targets: "all",
-        },
-        ReduxOperation::Min => ReduxRecipe {
-            id: "redux_sync_min_i32",
-            operation_key: "warp.redux.sync.min.s32",
-            source_record: "int_nvvm_redux_sync_min",
-            llvm_symbol: "llvm.nvvm.redux.sync.min",
-            rust_name: "redux_sync_min_i32",
-            rust_value: "i32",
-            value_type: "i32",
-            dialect_op_type: "ReduxSyncMinOp",
-            dialect_op_name: "nvvm.redux_sync_min",
-            ptx_modifiers: &["sync", "min", "s32"],
-            minimum_ptx: "7.0",
-            minimum_sm: Some("sm_80"),
-            targets: "all",
-        },
-        ReduxOperation::Umax => ReduxRecipe {
-            id: "redux_sync_max_u32",
-            operation_key: "warp.redux.sync.max.u32",
-            source_record: "int_nvvm_redux_sync_umax",
-            llvm_symbol: "llvm.nvvm.redux.sync.umax",
-            rust_name: "redux_sync_max_u32",
-            rust_value: "u32",
-            value_type: "i32",
-            dialect_op_type: "ReduxSyncUmaxOp",
-            dialect_op_name: "nvvm.redux_sync_umax",
-            ptx_modifiers: &["sync", "max", "u32"],
-            minimum_ptx: "7.0",
-            minimum_sm: Some("sm_80"),
-            targets: "all",
-        },
-        ReduxOperation::Max => ReduxRecipe {
-            id: "redux_sync_max_i32",
-            operation_key: "warp.redux.sync.max.s32",
-            source_record: "int_nvvm_redux_sync_max",
-            llvm_symbol: "llvm.nvvm.redux.sync.max",
-            rust_name: "redux_sync_max_i32",
-            rust_value: "i32",
-            value_type: "i32",
-            dialect_op_type: "ReduxSyncMaxOp",
-            dialect_op_name: "nvvm.redux_sync_max",
-            ptx_modifiers: &["sync", "max", "s32"],
-            minimum_ptx: "7.0",
-            minimum_sm: Some("sm_80"),
-            targets: "all",
-        },
-        ReduxOperation::And => ReduxRecipe {
-            id: "redux_sync_and",
-            operation_key: "warp.redux.sync.and.b32",
-            source_record: "int_nvvm_redux_sync_and",
-            llvm_symbol: "llvm.nvvm.redux.sync.and",
-            rust_name: "redux_sync_and",
-            rust_value: "u32",
-            value_type: "i32",
-            dialect_op_type: "ReduxSyncAndOp",
-            dialect_op_name: "nvvm.redux_sync_and",
-            ptx_modifiers: &["sync", "and", "b32"],
-            minimum_ptx: "7.0",
-            minimum_sm: Some("sm_80"),
-            targets: "all",
-        },
-        ReduxOperation::Or => ReduxRecipe {
-            id: "redux_sync_or",
-            operation_key: "warp.redux.sync.or.b32",
-            source_record: "int_nvvm_redux_sync_or",
-            llvm_symbol: "llvm.nvvm.redux.sync.or",
-            rust_name: "redux_sync_or",
-            rust_value: "u32",
-            value_type: "i32",
-            dialect_op_type: "ReduxSyncOrOp",
-            dialect_op_name: "nvvm.redux_sync_or",
-            ptx_modifiers: &["sync", "or", "b32"],
-            minimum_ptx: "7.0",
-            minimum_sm: Some("sm_80"),
-            targets: "all",
-        },
-        ReduxOperation::Xor => ReduxRecipe {
-            id: "redux_sync_xor",
-            operation_key: "warp.redux.sync.xor.b32",
-            source_record: "int_nvvm_redux_sync_xor",
-            llvm_symbol: "llvm.nvvm.redux.sync.xor",
-            rust_name: "redux_sync_xor",
-            rust_value: "u32",
-            value_type: "i32",
-            dialect_op_type: "ReduxSyncXorOp",
-            dialect_op_name: "nvvm.redux_sync_xor",
-            ptx_modifiers: &["sync", "xor", "b32"],
-            minimum_ptx: "7.0",
-            minimum_sm: Some("sm_80"),
-            targets: "all",
-        },
-        ReduxOperation::Fmin => ReduxRecipe {
-            id: "redux_sync_min_f32",
-            operation_key: "warp.redux.sync.min.f32",
-            source_record: "int_nvvm_redux_sync_fmin",
-            llvm_symbol: "llvm.nvvm.redux.sync.fmin",
-            rust_name: "redux_sync_min_f32",
-            rust_value: "f32",
-            value_type: "f32",
-            dialect_op_type: "ReduxSyncFminOp",
-            dialect_op_name: "nvvm.redux_sync_fmin",
-            ptx_modifiers: &["sync", "min", "f32"],
-            minimum_ptx: "8.6",
-            minimum_sm: None,
-            targets: REDUX_F32_TARGETS,
-        },
-        ReduxOperation::FminNan => ReduxRecipe {
-            id: "redux_sync_min_nan_f32",
-            operation_key: "warp.redux.sync.min.nan.f32",
-            source_record: "int_nvvm_redux_sync_fmin_NaN",
-            llvm_symbol: "llvm.nvvm.redux.sync.fmin.NaN",
-            rust_name: "redux_sync_min_nan_f32",
-            rust_value: "f32",
-            value_type: "f32",
-            dialect_op_type: "ReduxSyncFminNanOp",
-            dialect_op_name: "nvvm.redux_sync_fmin_nan",
-            ptx_modifiers: &["sync", "min", "NaN", "f32"],
-            minimum_ptx: "8.6",
-            minimum_sm: None,
-            targets: REDUX_F32_TARGETS,
-        },
-        ReduxOperation::FminAbs => ReduxRecipe {
-            id: "redux_sync_min_abs_f32",
-            operation_key: "warp.redux.sync.min.abs.f32",
-            source_record: "int_nvvm_redux_sync_fmin_abs",
-            llvm_symbol: "llvm.nvvm.redux.sync.fmin.abs",
-            rust_name: "redux_sync_min_abs_f32",
-            rust_value: "f32",
-            value_type: "f32",
-            dialect_op_type: "ReduxSyncFminAbsOp",
-            dialect_op_name: "nvvm.redux_sync_fmin_abs",
-            ptx_modifiers: &["sync", "min", "abs", "f32"],
-            minimum_ptx: "8.6",
-            minimum_sm: None,
-            targets: REDUX_F32_TARGETS,
-        },
-        ReduxOperation::FminAbsNan => ReduxRecipe {
-            id: "redux_sync_min_abs_nan_f32",
-            operation_key: "warp.redux.sync.min.abs.nan.f32",
-            source_record: "int_nvvm_redux_sync_fmin_abs_NaN",
-            llvm_symbol: "llvm.nvvm.redux.sync.fmin.abs.NaN",
-            rust_name: "redux_sync_min_abs_nan_f32",
-            rust_value: "f32",
-            value_type: "f32",
-            dialect_op_type: "ReduxSyncFminAbsNanOp",
-            dialect_op_name: "nvvm.redux_sync_fmin_abs_nan",
-            ptx_modifiers: &["sync", "min", "abs", "NaN", "f32"],
-            minimum_ptx: "8.6",
-            minimum_sm: None,
-            targets: REDUX_F32_TARGETS,
-        },
-        ReduxOperation::Fmax => ReduxRecipe {
-            id: "redux_sync_max_f32",
-            operation_key: "warp.redux.sync.max.f32",
-            source_record: "int_nvvm_redux_sync_fmax",
-            llvm_symbol: "llvm.nvvm.redux.sync.fmax",
-            rust_name: "redux_sync_max_f32",
-            rust_value: "f32",
-            value_type: "f32",
-            dialect_op_type: "ReduxSyncFmaxOp",
-            dialect_op_name: "nvvm.redux_sync_fmax",
-            ptx_modifiers: &["sync", "max", "f32"],
-            minimum_ptx: "8.6",
-            minimum_sm: None,
-            targets: REDUX_F32_TARGETS,
-        },
-        ReduxOperation::FmaxNan => ReduxRecipe {
-            id: "redux_sync_max_nan_f32",
-            operation_key: "warp.redux.sync.max.nan.f32",
-            source_record: "int_nvvm_redux_sync_fmax_NaN",
-            llvm_symbol: "llvm.nvvm.redux.sync.fmax.NaN",
-            rust_name: "redux_sync_max_nan_f32",
-            rust_value: "f32",
-            value_type: "f32",
-            dialect_op_type: "ReduxSyncFmaxNanOp",
-            dialect_op_name: "nvvm.redux_sync_fmax_nan",
-            ptx_modifiers: &["sync", "max", "NaN", "f32"],
-            minimum_ptx: "8.6",
-            minimum_sm: None,
-            targets: REDUX_F32_TARGETS,
-        },
-        ReduxOperation::FmaxAbs => ReduxRecipe {
-            id: "redux_sync_max_abs_f32",
-            operation_key: "warp.redux.sync.max.abs.f32",
-            source_record: "int_nvvm_redux_sync_fmax_abs",
-            llvm_symbol: "llvm.nvvm.redux.sync.fmax.abs",
-            rust_name: "redux_sync_max_abs_f32",
-            rust_value: "f32",
-            value_type: "f32",
-            dialect_op_type: "ReduxSyncFmaxAbsOp",
-            dialect_op_name: "nvvm.redux_sync_fmax_abs",
-            ptx_modifiers: &["sync", "max", "abs", "f32"],
-            minimum_ptx: "8.6",
-            minimum_sm: None,
-            targets: REDUX_F32_TARGETS,
-        },
-        ReduxOperation::FmaxAbsNan => ReduxRecipe {
-            id: "redux_sync_max_abs_nan_f32",
-            operation_key: "warp.redux.sync.max.abs.nan.f32",
-            source_record: "int_nvvm_redux_sync_fmax_abs_NaN",
-            llvm_symbol: "llvm.nvvm.redux.sync.fmax.abs.NaN",
-            rust_name: "redux_sync_max_abs_nan_f32",
-            rust_value: "f32",
-            value_type: "f32",
-            dialect_op_type: "ReduxSyncFmaxAbsNanOp",
-            dialect_op_name: "nvvm.redux_sync_fmax_abs_nan",
-            ptx_modifiers: &["sync", "max", "abs", "NaN", "f32"],
-            minimum_ptx: "8.6",
-            minimum_sm: None,
-            targets: REDUX_F32_TARGETS,
-        },
-    }
-}
-
-fn validate_dot_product_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let dot_product = policy
-        .dot_product
-        .as_ref()
-        .with_context(|| format!("{} has no closed dot-product contract", policy.id))?;
-    let recipe = dot_product_recipe(dot_product.operation, dot_product.signedness);
-    ensure!(
-        dot_product.adapter == recipe.adapter,
-        "{} dot-product source adapter does not match its operation",
-        policy.id
-    );
-    ensure!(
-        policy.id == recipe.id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} dot-product identity does not match its closed operation recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "dotprod"
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == ["u32", "u32", recipe.rust_value]
-            && policy.rust_result == recipe.rust_value
-            && policy.safe
-            && !policy.must_use
-            && policy.public_rust_path == format!("cuda_intrinsics::dotprod::{}", recipe.rust_name)
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::dotprod::{}", recipe.rust_name)],
-        "{} must preserve the safe, non-must-use dotprod raw API and legacy cuda-device DefPath",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == ["i32", "i32", "i32"]
-            && policy.dialect_results == ["i32"]
-            && policy.llvm_arguments == recipe.llvm_arguments
-            && policy.llvm_results == ["i32"]
-            && policy.lowering == "generated_dotprod",
-        "{} is outside the closed three-operand dot-product lowering recipe",
-        policy.id
-    );
-    ensure!(
-        policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == "5.0"
-            && policy.minimum_sm.as_deref() == Some("sm_61")
-            && policy.ptx_result == recipe.rust_value
-            && policy.targets == "all",
-        "{} dot-product effects, carrier, or target floor disagree with its operation recipe",
-        policy.id
-    );
-    ensure!(
-        declaration
-            .classes
-            .iter()
-            .any(|class| class == "NVVMPureIntrinsic")
-            && declaration.properties == recipe.llvm_properties,
-        "{} dot-product effects or immediate contract disagree with the imported declaration",
-        policy.id
-    );
-    ensure!(
-        policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes another generated-family contract with dotprod",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == recipe.ptx_mnemonic
-            && policy.expected_ptx.modifiers == recipe.ptx_modifiers
-            && policy.expected_ptx.operands
-                == [
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                ],
-        "{} expected PTX does not match its closed dot-product recipe",
-        policy.id
-    );
-
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ]),
-        "{} must define exactly the reviewed LLVM typed and libNVVM inline-PTX routes",
-        policy.id
-    );
-    for lowering in &policy.backend_lowerings {
-        let floor_matches = match lowering.backend {
-            IntrinsicBackend::LlvmNvptx => {
-                lowering.mechanism == BackendLoweringMechanism::TypedNvvm
-                    && lowering.minimum_ptx.is_none()
-                    && lowering.minimum_sm.is_none()
-            }
-            IntrinsicBackend::LibNvvm => {
-                lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    && lowering.minimum_ptx.is_none()
-                    && lowering.minimum_sm.as_deref() == Some("sm_75")
-            }
-        };
-        ensure!(
-            floor_matches && !lowering.evidence_profile.trim().is_empty(),
-            "{} backend {:?} does not carry its reviewed dot-product profile floor",
-            policy.id,
-            lowering.backend
-        );
-    }
-    Ok(())
-}
-
-struct DotProductRecipe {
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    rust_name: &'static str,
-    rust_value: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    llvm_arguments: &'static [&'static str],
-    llvm_properties: &'static [&'static str],
-    adapter: DotProductAdapter,
-    ptx_mnemonic: &'static str,
-    ptx_modifiers: &'static [&'static str],
-}
-
-fn dot_product_recipe(
-    operation: DotProductOperation,
-    signedness: DotProductSignedness,
-) -> DotProductRecipe {
-    match (operation, signedness) {
-        (DotProductOperation::Dp4a, DotProductSignedness::Signed) => DotProductRecipe {
-            id: "dp4a_s32",
-            operation_key: "integer.dot_product.dp4a.s32",
-            source_record: "int_nvvm_idp4a_s_s",
-            llvm_symbol: "llvm.nvvm.idp4a.s.s",
-            rust_name: "dp4a_s32",
-            rust_value: "i32",
-            dialect_op_type: "Dp4aS32Op",
-            dialect_op_name: "nvvm.dp4a_s32",
-            llvm_arguments: &["i32", "i32", "i32"],
-            llvm_properties: &["IntrNoMem", "IntrSpeculatable"],
-            adapter: DotProductAdapter::DirectThreeOperands,
-            ptx_mnemonic: "dp4a",
-            ptx_modifiers: &["s32", "s32"],
-        },
-        (DotProductOperation::Dp4a, DotProductSignedness::Unsigned) => DotProductRecipe {
-            id: "dp4a_u32",
-            operation_key: "integer.dot_product.dp4a.u32",
-            source_record: "int_nvvm_idp4a_u_u",
-            llvm_symbol: "llvm.nvvm.idp4a.u.u",
-            rust_name: "dp4a_u32",
-            rust_value: "u32",
-            dialect_op_type: "Dp4aU32Op",
-            dialect_op_name: "nvvm.dp4a_u32",
-            llvm_arguments: &["i32", "i32", "i32"],
-            llvm_properties: &["IntrNoMem", "IntrSpeculatable"],
-            adapter: DotProductAdapter::DirectThreeOperands,
-            ptx_mnemonic: "dp4a",
-            ptx_modifiers: &["u32", "u32"],
-        },
-        (DotProductOperation::Dp2a, DotProductSignedness::Signed) => DotProductRecipe {
-            id: "dp2a_s32",
-            operation_key: "integer.dot_product.dp2a.lo.s32",
-            source_record: "int_nvvm_idp2a_s_s",
-            llvm_symbol: "llvm.nvvm.idp2a.s.s",
-            rust_name: "dp2a_s32",
-            rust_value: "i32",
-            dialect_op_type: "Dp2aS32Op",
-            dialect_op_name: "nvvm.dp2a_s32",
-            llvm_arguments: &["i32", "i32", "i1", "i32"],
-            llvm_properties: &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"],
-            adapter: DotProductAdapter::InsertLowHalfFalse,
-            ptx_mnemonic: "dp2a",
-            ptx_modifiers: &["lo", "s32", "s32"],
-        },
-        (DotProductOperation::Dp2a, DotProductSignedness::Unsigned) => DotProductRecipe {
-            id: "dp2a_u32",
-            operation_key: "integer.dot_product.dp2a.lo.u32",
-            source_record: "int_nvvm_idp2a_u_u",
-            llvm_symbol: "llvm.nvvm.idp2a.u.u",
-            rust_name: "dp2a_u32",
-            rust_value: "u32",
-            dialect_op_type: "Dp2aU32Op",
-            dialect_op_name: "nvvm.dp2a_u32",
-            llvm_arguments: &["i32", "i32", "i1", "i32"],
-            llvm_properties: &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"],
-            adapter: DotProductAdapter::InsertLowHalfFalse,
-            ptx_mnemonic: "dp2a",
-            ptx_modifiers: &["lo", "u32", "u32"],
-        },
-    }
-}
-
-#[derive(Clone, Copy)]
-struct StmatrixRecipe {
-    multiplicity: StmatrixMultiplicity,
-    layout: StmatrixLayout,
-    abi_id: &'static str,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    compatibility_name: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    summary: &'static str,
-}
-
-fn stmatrix_recipe(multiplicity: StmatrixMultiplicity, layout: StmatrixLayout) -> StmatrixRecipe {
-    match (multiplicity, layout) {
-        (StmatrixMultiplicity::X2, StmatrixLayout::Normal) => StmatrixRecipe {
-            multiplicity,
-            layout,
-            abi_id: "i0301",
-            id: "stmatrix_m8n8_x2_b16",
-            operation_key: "matrix.stmatrix.m8n8.x2.normal.b16.shared",
-            source_record: "int_nvvm_stmatrix_sync_aligned_m8n8_x2_b16",
-            llvm_symbol: "llvm.nvvm.stmatrix.sync.aligned.m8n8.x2.b16",
-            compatibility_name: "stmatrix_m8n8_x2",
-            dialect_op_type: "StmatrixM8n8X2Op",
-            dialect_op_name: "nvvm.stmatrix_m8n8_x2",
-            summary: "Stores two 8×8 b16 matrix fragments cooperatively to shared memory.",
-        },
-        (StmatrixMultiplicity::X2, StmatrixLayout::Transposed) => StmatrixRecipe {
-            multiplicity,
-            layout,
-            abi_id: "i0302",
-            id: "stmatrix_m8n8_x2_trans_b16",
-            operation_key: "matrix.stmatrix.m8n8.x2.transposed.b16.shared",
-            source_record: "int_nvvm_stmatrix_sync_aligned_m8n8_x2_trans_b16",
-            llvm_symbol: "llvm.nvvm.stmatrix.sync.aligned.m8n8.x2.trans.b16",
-            compatibility_name: "stmatrix_m8n8_x2_trans",
-            dialect_op_type: "StmatrixM8n8X2TransOp",
-            dialect_op_name: "nvvm.stmatrix_m8n8_x2_trans",
-            summary: "Stores two transposed 8×8 b16 matrix fragments cooperatively to shared memory.",
-        },
-        (StmatrixMultiplicity::X4, StmatrixLayout::Normal) => StmatrixRecipe {
-            multiplicity,
-            layout,
-            abi_id: "i0303",
-            id: "stmatrix_m8n8_x4_b16",
-            operation_key: "matrix.stmatrix.m8n8.x4.normal.b16.shared",
-            source_record: "int_nvvm_stmatrix_sync_aligned_m8n8_x4_b16",
-            llvm_symbol: "llvm.nvvm.stmatrix.sync.aligned.m8n8.x4.b16",
-            compatibility_name: "stmatrix_m8n8_x4",
-            dialect_op_type: "StmatrixM8n8X4Op",
-            dialect_op_name: "nvvm.stmatrix_m8n8_x4",
-            summary: "Stores four 8×8 b16 matrix fragments cooperatively to shared memory.",
-        },
-        (StmatrixMultiplicity::X4, StmatrixLayout::Transposed) => StmatrixRecipe {
-            multiplicity,
-            layout,
-            abi_id: "i0304",
-            id: "stmatrix_m8n8_x4_trans_b16",
-            operation_key: "matrix.stmatrix.m8n8.x4.transposed.b16.shared",
-            source_record: "int_nvvm_stmatrix_sync_aligned_m8n8_x4_trans_b16",
-            llvm_symbol: "llvm.nvvm.stmatrix.sync.aligned.m8n8.x4.trans.b16",
-            compatibility_name: "stmatrix_m8n8_x4_trans",
-            dialect_op_type: "StmatrixM8n8X4TransOp",
-            dialect_op_name: "nvvm.stmatrix_m8n8_x4_trans",
-            summary: "Stores four transposed 8×8 b16 matrix fragments cooperatively to shared memory.",
-        },
-    }
-}
-
-fn stmatrix_variant_for_id(id: &str) -> Option<(StmatrixMultiplicity, StmatrixLayout)> {
-    match id {
-        "stmatrix_m8n8_x2_b16" => Some((StmatrixMultiplicity::X2, StmatrixLayout::Normal)),
-        "stmatrix_m8n8_x2_trans_b16" => {
-            Some((StmatrixMultiplicity::X2, StmatrixLayout::Transposed))
-        }
-        "stmatrix_m8n8_x4_b16" => Some((StmatrixMultiplicity::X4, StmatrixLayout::Normal)),
-        "stmatrix_m8n8_x4_trans_b16" => {
-            Some((StmatrixMultiplicity::X4, StmatrixLayout::Transposed))
-        }
-        _ => None,
-    }
-}
-
-fn expand_stmatrix_admission(admission: &StmatrixAdmission) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "stmatrix runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact stmatrix admission requires both backend evidence profiles"
-    );
-    let expected_variants = [
-        (StmatrixMultiplicity::X2, StmatrixLayout::Normal),
-        (StmatrixMultiplicity::X2, StmatrixLayout::Transposed),
-        (StmatrixMultiplicity::X4, StmatrixLayout::Normal),
-        (StmatrixMultiplicity::X4, StmatrixLayout::Transposed),
-    ];
-    let actual_variants = admission
-        .variants
-        .iter()
-        .map(|variant| (variant.multiplicity, variant.layout))
-        .collect::<Vec<_>>();
-    ensure!(
-        actual_variants == expected_variants,
-        "compact stmatrix admission must contain the four reviewed variants in canonical order"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = stmatrix_recipe(variant.multiplicity, variant.layout);
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must keep reserved ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            let count = recipe.multiplicity.register_count();
-            let mut rust_arguments = vec!["*mut u8".to_owned()];
-            rust_arguments.extend(std::iter::repeat_n("u32".to_owned(), count));
-            let mut dialect_operands = vec!["ptr".to_owned()];
-            dialect_operands.extend(std::iter::repeat_n("i32".to_owned(), count));
-            let mut llvm_arguments = vec!["anyptr".to_owned()];
-            llvm_arguments.extend(std::iter::repeat_n("i32".to_owned(), count));
-            let multiplicity = match recipe.multiplicity {
-                StmatrixMultiplicity::X2 => "x2",
-                StmatrixMultiplicity::X4 => "x4",
-            };
-            let mut modifiers = vec![
-                "sync".into(),
-                "aligned".into(),
-                "m8n8".into(),
-                multiplicity.into(),
-            ];
-            if recipe.layout == StmatrixLayout::Transposed {
-                modifiers.push("trans".into());
-            }
-            modifiers.extend(["shared".into(), "b16".into()]);
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: variant.abi_id.clone(),
-                operation_key: recipe.operation_key.into(),
-                family: "stmatrix".into(),
-                source: None,
-                source_record: Some(recipe.source_record.into()),
-                rust_module: "matrix".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments,
-                rust_result: "()".into(),
-                safe: false,
-                must_use: false,
-                safe_allowlist_reason: None,
-                public_rust_path: format!("cuda_intrinsics::matrix::{}", recipe.id),
-                compatibility_rust_paths: vec![format!(
-                    "cuda_device::tcgen05::{}",
-                    recipe.compatibility_name
-                )],
-                dialect_op_type: recipe.dialect_op_type.into(),
-                dialect_op_name: recipe.dialect_op_name.into(),
-                dialect_operands,
-                dialect_results: vec![],
-                llvm_symbol: Some(recipe.llvm_symbol.into()),
-                resolved_llvm_symbol: Some(format!("{}.p3", recipe.llvm_symbol)),
-                llvm_arguments,
-                llvm_results: vec![],
-                pure: false,
-                memory: "write".into(),
-                convergent: true,
-                execution_scope: "warp".into(),
-                minimum_ptx: "7.8".into(),
-                minimum_sm: Some("sm_90".into()),
-                ptx_result: "()".into(),
-                targets: "all".into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section: "9.7.14.5.16 Warp-level matrix store instruction: stmatrix"
-                    .into(),
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-stmatrix".into(),
-                lowering: "generated_stmatrix".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: BackendLoweringMechanism::TypedNvvm,
-                        evidence_profile: admission.llvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some("7.8".into()),
-                        minimum_sm: Some("sm_90".into()),
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some("7.8".into()),
-                        minimum_sm: Some("sm_90".into()),
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: Some(ImportedAddressSpace::Shared),
-                expected_ptx: InstructionPattern {
-                    mnemonic: "stmatrix".into(),
-                    modifiers,
-                    operands: vec![
-                        OperandPattern::Address,
-                        OperandPattern::RegisterList { length: count },
-                    ],
-                },
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect()
-}
-
-fn validate_stmatrix_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let (multiplicity, layout) = stmatrix_variant_for_id(&policy.id)
-        .with_context(|| format!("{} has no closed stmatrix recipe", policy.id))?;
-    let recipe = stmatrix_recipe(multiplicity, layout);
-    let count = multiplicity.register_count();
-    let mut rust_arguments = vec!["*mut u8".to_owned()];
-    rust_arguments.extend(std::iter::repeat_n("u32".to_owned(), count));
-    let mut dialect_operands = vec!["ptr".to_owned()];
-    dialect_operands.extend(std::iter::repeat_n("i32".to_owned(), count));
-    let mut llvm_arguments = vec!["anyptr".to_owned()];
-    llvm_arguments.extend(std::iter::repeat_n("i32".to_owned(), count));
-
-    ensure!(
-        policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.as_deref()
-                == Some(format!("{}.p3", recipe.llvm_symbol).as_str()),
-        "{} stmatrix identity does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "matrix"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == rust_arguments
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::matrix::{}", recipe.id)
-            && policy.compatibility_rust_paths
-                == [format!(
-                    "cuda_device::tcgen05::{}",
-                    recipe.compatibility_name
-                )],
-        "{} stmatrix Rust API does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == dialect_operands
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == llvm_arguments
-            && policy.llvm_results.is_empty()
-            && policy.lowering == "generated_stmatrix"
-            && policy.selected_address_space == Some(ImportedAddressSpace::Shared),
-        "{} stmatrix carriers or lowering do not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.properties
-            == [
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>",
-            ]
-            && !policy.pure
-            && policy.memory == "write"
-            && policy.convergent
-            && policy.execution_scope == "warp",
-        "{} stmatrix effects disagree with the imported declaration",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == "7.8"
-            && policy.minimum_sm.as_deref() == Some("sm_90")
-            && policy.ptx_result == "()"
-            && policy.targets == "all"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.14.5.16 Warp-level matrix store instruction: stmatrix"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-stmatrix",
-        "{} stmatrix target floor or PTX provenance changed",
-        policy.id
-    );
-    let multiplicity_name = match multiplicity {
-        StmatrixMultiplicity::X2 => "x2",
-        StmatrixMultiplicity::X4 => "x4",
-    };
-    let mut modifiers = vec![
-        "sync".into(),
-        "aligned".into(),
-        "m8n8".into(),
-        multiplicity_name.into(),
-    ];
-    if layout == StmatrixLayout::Transposed {
-        modifiers.push("trans".into());
-    }
-    modifiers.extend(["shared".into(), "b16".into()]);
-    ensure!(
-        policy.expected_ptx
-            == (InstructionPattern {
-                mnemonic: "stmatrix".into(),
-                modifiers,
-                operands: vec![
-                    OperandPattern::Address,
-                    OperandPattern::RegisterList { length: count },
-                ],
-            }),
-        "{} expected PTX does not match its closed stmatrix shape",
-        policy.id
-    );
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && policy.backend_lowerings.iter().all(|route| {
-                !route.evidence_profile.trim().is_empty()
-                    && route.minimum_ptx.as_deref() == Some("7.8")
-                    && route.minimum_sm.as_deref() == Some("sm_90")
-            })
-            && policy.backend_lowerings.iter().any(|route| {
-                route.backend == IntrinsicBackend::LlvmNvptx
-                    && route.mechanism == BackendLoweringMechanism::TypedNvvm
-            })
-            && policy.backend_lowerings.iter().any(|route| {
-                route.backend == IntrinsicBackend::LibNvvm
-                    && route.mechanism == BackendLoweringMechanism::InlinePtx
-            }),
-        "{} must keep its reviewed typed-NVVM and inline-PTX routes",
-        policy.id
-    );
-    ensure!(
-        policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.cp_async_mbarrier.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.register_mma.is_none()
-            && policy.sparse_mma.is_none()
-            && policy.prmt.is_none()
-            && policy.cluster_barrier.is_none()
-            && policy.special_register.is_none()
-            && policy.debug_control.is_none(),
-        "{} mixes another generated-family contract with stmatrix",
-        policy.id
-    );
-    Ok(())
-}
-
-fn validate_ldmatrix_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let variant = policy
-        .ldmatrix_variant
-        .as_ref()
-        .with_context(|| format!("{} has no closed ldmatrix variant", policy.id))?;
-    let safety = policy
-        .ldmatrix_safety
-        .as_ref()
-        .with_context(|| format!("{} has no ldmatrix safety contract", policy.id))?;
-    let classic = variant.shape == LdmatrixShape::M8n8 && variant.element == LdmatrixElement::B16;
-    let blackwell = matches!(
-        (variant.shape, variant.layout, variant.element),
-        (
-            LdmatrixShape::M8n16,
-            LdmatrixLayout::Normal,
-            LdmatrixElement::B8x16B4x16P64 | LdmatrixElement::B8x16B6x16P32
-        ) | (
-            LdmatrixShape::M16n16,
-            LdmatrixLayout::Transposed,
-            LdmatrixElement::B8 | LdmatrixElement::B8x16B4x16P64 | LdmatrixElement::B8x16B6x16P32
-        )
-    );
-    ensure!(
-        variant.shape != LdmatrixShape::M16n16 || variant.multiplicity != LdmatrixMultiplicity::X4,
-        "{} requests unsupported m16n16.x4 ldmatrix",
-        policy.id
-    );
-    ensure!(
-        (classic || blackwell) && variant.state_space == LdmatrixStateSpace::Shared,
-        "{} requests an unsupported ldmatrix shape, element, or state space",
-        policy.id
-    );
-    let expected_participation = if classic {
-        LdmatrixParticipation::AllWarpLanesSameInstruction
-    } else {
-        LdmatrixParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes
-    };
-    let expected_address_contract = match variant.shape {
-        LdmatrixShape::M8n8 => {
-            LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadableWithSm75Replication
-        }
-        LdmatrixShape::M8n16 => {
-            LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadable
-        }
-        LdmatrixShape::M16n16 => {
-            LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedThirtyTwoBytesReadable
-        }
-    };
-    ensure!(
-        safety.participation == expected_participation
-            && safety.address_contract == expected_address_contract
-            && safety.memory_order == LdmatrixMemoryOrder::Weak
-            && safety.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} has an unsupported ldmatrix safety contract",
-        policy.id
-    );
-    let count = variant.register_count();
-    let count_name = match variant.multiplicity {
-        LdmatrixMultiplicity::X1 => "x1",
-        LdmatrixMultiplicity::X2 => "x2",
-        LdmatrixMultiplicity::X4 => "x4",
-    };
-    let trans_record = match variant.layout {
-        LdmatrixLayout::Normal => "",
-        LdmatrixLayout::Transposed => "_trans",
-    };
-    let trans_symbol = match variant.layout {
-        LdmatrixLayout::Normal => "",
-        LdmatrixLayout::Transposed => ".trans",
-    };
-    let layout_name = match variant.layout {
-        LdmatrixLayout::Normal => "normal",
-        LdmatrixLayout::Transposed => "transposed",
-    };
-    let shape_name = match variant.shape {
-        LdmatrixShape::M8n8 => "m8n8",
-        LdmatrixShape::M8n16 => "m8n16",
-        LdmatrixShape::M16n16 => "m16n16",
-    };
-    let (element_record, element_symbol) = match variant.element {
-        LdmatrixElement::B16 => ("b16", "b16"),
-        LdmatrixElement::B8 => ("b8", "b8"),
-        LdmatrixElement::B8x16B4x16P64 => ("b8x16_b4x16_p64", "b8x16.b4x16_p64"),
-        LdmatrixElement::B8x16B6x16P32 => ("b8x16_b6x16_p32", "b8x16.b6x16_p32"),
-    };
-    let expected_source = format!(
-        "int_nvvm_ldmatrix_sync_aligned_{shape_name}_{count_name}{trans_record}_{element_record}"
-    );
-    let expected_symbol = format!(
-        "llvm.nvvm.ldmatrix.sync.aligned.{shape_name}.{count_name}{trans_symbol}.{element_symbol}"
-    );
-    let expected_name =
-        format!("ldmatrix_{shape_name}_{count_name}{trans_record}_{element_record}");
-    let expected_result = if count == 1 {
-        "u32".to_owned()
-    } else {
-        format!("[u32; {count}]")
-    };
-    let expected_adapter = if count == 1 {
-        LdmatrixAdapter::SingleResultDirect
-    } else {
-        LdmatrixAdapter::MultipleResultsToArray
-    };
-    ensure!(
-        policy.source_record.as_deref() == Some(expected_source.as_str())
-            && policy.llvm_symbol.as_deref() == Some(expected_symbol.as_str()),
-        "{} ldmatrix variant does not match its imported source record or base LLVM symbol",
-        policy.id
-    );
-    ensure!(
-        policy.resolved_llvm_symbol.as_deref() == Some(format!("{expected_symbol}.p3").as_str()),
-        "{} must keep the imported base symbol distinct from the resolved `.p3` overload",
-        policy.id
-    );
-    ensure!(
-        policy.rust_arguments == [if classic { "*const u32" } else { "*const u8" }]
-            && policy.rust_result == expected_result
-            && policy.llvm_arguments == ["anyptr"]
-            && policy.llvm_results == vec!["i32"; count]
-            && policy.ptx_result == policy.rust_result,
-        "{} ldmatrix Rust, imported LLVM, and PTX carrier signatures disagree",
-        policy.id
-    );
-    ensure!(
-        policy.id == expected_name
-            && policy.operation_key
-                == format!(
-                    "matrix.ldmatrix.{shape_name}.{count_name}.{layout_name}.{element_record}.shared"
-                )
-            && policy.rust_module == "matrix"
-            && policy.rust_name == expected_name
-            && !policy.safe
-            && policy.must_use != classic
-            && policy.safe_allowlist_reason.is_none()
-            && {
-                let expected_compatibility_paths = if classic {
-                    vec![format!(
-                        "cuda_device::wmma::ldmatrix_{count_name}{trans_record}"
-                    )]
-                } else if matches!(
-                    policy.id.as_str(),
-                    "ldmatrix_m8n16_x2_b8x16_b4x16_p64" | "ldmatrix_m8n16_x4_b8x16_b4x16_p64"
-                ) {
-                    vec![format!("cuda_device::wmma::{expected_name}")]
-                } else {
-                    vec![]
-                };
-                policy.compatibility_rust_paths == expected_compatibility_paths
-            }
-            && policy.lowering == "generated_ldmatrix"
-            && policy.ldmatrix_adapter == Some(expected_adapter)
-            && policy.selected_address_space == Some(ImportedAddressSpace::Shared),
-        "{} must preserve the closed raw/compatibility ldmatrix API, result adapter, and shared selection",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && declaration
-                .properties
-                .iter()
-                .any(|property| property == "IntrArgMemOnly")
-            && declaration
-                .properties
-                .iter()
-                .any(|property| property == "IntrReadMem"),
-        "{} ldmatrix effects disagree with the imported declaration",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        backend_pairs
-            == BTreeSet::from([
-                (
-                    IntrinsicBackend::LlvmNvptx,
-                    BackendLoweringMechanism::TypedNvvm
-                ),
-                (
-                    IntrinsicBackend::LibNvvm,
-                    BackendLoweringMechanism::InlinePtx
-                ),
-            ]),
-        "{} must define exactly the reviewed LLVM typed and libNVVM inline-PTX lowerings",
-        policy.id
-    );
-    ensure!(
-        policy
-            .backend_lowerings
-            .iter()
-            .all(|lowering| !lowering.evidence_profile.trim().is_empty()),
-        "{} backend lowering omits its evidence profile",
-        policy.id
-    );
-    if blackwell {
-        ensure!(
-            policy.minimum_ptx == "8.6"
-                && policy.minimum_sm.is_none()
-                && policy.targets == BLACKWELL_LDMATRIX_LLVM_TARGETS,
-            "{} must retain the reviewed PTX 8.6 floor and exact LLVM Blackwell target set",
-            policy.id
-        );
-        let llvm = policy
-            .backend_lowerings
-            .iter()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-            .expect("validated LLVM route");
-        let libnvvm = policy
-            .backend_lowerings
-            .iter()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
-            .expect("validated libNVVM route");
-        ensure!(
-            llvm.targets.is_none()
-                && llvm.minimum_sm.is_none()
-                && backend_target_requirement(policy, llvm)?
-                    == CatalogTargetRequirement {
-                        minimum_ptx: parse_ptx_version("8.6", &policy.id)?,
-                        hardware: parse_hardware_target_fields(
-                            &policy.id,
-                            BLACKWELL_LDMATRIX_LLVM_TARGETS,
-                            None,
-                        )?,
-                    }
-                && libnvvm.targets.as_deref() == Some(BLACKWELL_LDMATRIX_LIBNVVM_TARGETS)
-                && libnvvm.minimum_sm.is_none()
-                && backend_target_requirement(policy, libnvvm)?
-                    == CatalogTargetRequirement {
-                        minimum_ptx: parse_ptx_version("8.6", &policy.id)?,
-                        hardware: parse_hardware_target_fields(
-                            &policy.id,
-                            BLACKWELL_LDMATRIX_LIBNVVM_TARGETS,
-                            None,
-                        )?,
-                    },
-            "{} backend routes do not preserve the reviewed LLVM/libNVVM Blackwell target split",
-            policy.id
-        );
-    }
-    ensure!(
-        policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.mbarrier_basic.is_none(),
-        "{} mixes another generated-family contract with ldmatrix",
-        policy.id
-    );
-    Ok(())
-}
-
-fn validate_packed_atomic_policy(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-) -> Result<()> {
-    let packed = policy
-        .packed_atomic
-        .as_ref()
-        .with_context(|| format!("{} has no closed packed-atomic contract", policy.id))?;
-    ensure!(
-        packed.operation == PackedAtomicOperation::Add
-            && packed.state_space == PackedAtomicStateSpace::Global
-            && packed.ordering == PackedAtomicOrdering::Relaxed
-            && packed.scope == PackedAtomicScope::Gpu
-            && packed.rounding == PackedAtomicRounding::NearestEven
-            && packed.subnormal == PackedAtomicSubnormal::Preserve
-            && packed.atomicity == PackedAtomicAtomicity::PerElement
-            && packed.pointer_contract == PackedAtomicPointerContract::MutableGlobalU32Aligned4
-            && packed.access_contract
-                == PackedAtomicAccessContract::NoMixedWholeWordOrNonAtomicAccess
-            && packed.scope_contract == PackedAtomicScopeContract::RacingAtomicsMutuallyInclusive
-            && packed.codegen_contract == PackedAtomicCodegenContract::ExactNativeInstruction
-            && packed.return_contract
-                == PackedAtomicReturnContract::OldValuesPerElementMayBeNoncoherent
-            && packed.adapter == PackedAtomicAdapter::OldPackedU32,
-        "{} requests an unsupported packed-atomic semantic or safety contract",
-        policy.id
-    );
-    let (format, native_sm, minimum_ptx, minimum_sm, public_name) = match packed.format {
-        PackedAtomicFormat::F16x2 => ("f16x2", 60, "6.2", "sm_70", "atom_add_f16x2"),
-        PackedAtomicFormat::Bf16x2 => ("bf16x2", 90, "7.8", "sm_90", "atom_add_bf16x2"),
-    };
-    ensure!(
-        packed.native_minimum_sm == native_sm,
-        "{} PTX-native hardware floor does not match the selected packed format",
-        policy.id
-    );
-    ensure!(
-        source
-            == &IntrinsicSource::PtxNative {
-                instruction: format!("atom.global.add.noftz.{format}"),
-            },
-        "{} PTX-native source does not match its packed format",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "atomic"
-            && policy.rust_name == public_name
-            && policy.rust_arguments == ["*mut u32", "u32"]
-            && policy.rust_result == "u32"
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::atomic::{public_name}")
-            && policy.compatibility_rust_paths == [format!("cuda_device::atomic::{public_name}")],
-        "{} must preserve the unsafe must-use packed atomic raw/compatibility API",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == "PackedAtomicAddOp"
-            && policy.dialect_op_name == "nvvm.packed_atomic_add"
-            && policy.dialect_operands == ["ptr", "i32"]
-            && policy.dialect_results == ["i32"]
-            && policy.lowering == "generated_packed_atomic_inline_ptx",
-        "{} is outside the one closed packed-atomic dialect recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read_write"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == minimum_ptx
-            && policy.minimum_sm.as_deref() == Some(minimum_sm)
-            && policy.targets == "all"
-            && policy.ptx_result == "u32"
-            && policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.packed_alu.is_none()
-            && policy.packed_conversion.is_none()
-            && policy.cp_async_copy.is_none()
-            && policy.cp_async_control.is_none()
-            && policy.mbarrier_basic.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} packed-atomic effects, carrier, or native target floor disagree",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "atom"
-            && policy.expected_ptx.modifiers == ["global", "add", "noftz", format]
-            && policy.expected_ptx.operands
-                == [
-                    OperandPattern::Register,
-                    OperandPattern::Address,
-                    OperandPattern::Register,
-                ],
-        "{} expected PTX must match the exact packed global add spelling",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        backend_pairs
-            == BTreeSet::from([
-                (
-                    IntrinsicBackend::LlvmNvptx,
-                    BackendLoweringMechanism::InlinePtx,
-                ),
-                (
-                    IntrinsicBackend::LibNvvm,
-                    BackendLoweringMechanism::InlinePtx,
-                ),
-            ]),
-        "{} must define exactly the reviewed LLVM-NVPTX and libNVVM inline-PTX routes",
-        policy.id
-    );
-    for lowering in &policy.backend_lowerings {
-        let expected_sm = match (packed.format, lowering.backend) {
-            (PackedAtomicFormat::F16x2, IntrinsicBackend::LlvmNvptx) => "sm_70",
-            (PackedAtomicFormat::F16x2, IntrinsicBackend::LibNvvm) => "sm_75",
-            (PackedAtomicFormat::Bf16x2, _) => "sm_90",
-        };
-        ensure!(
-            lowering.minimum_ptx.as_deref() == Some(minimum_ptx)
-                && lowering.minimum_sm.as_deref() == Some(expected_sm)
-                && !lowering.evidence_profile.trim().is_empty(),
-            "{} backend {:?} does not carry its exact reviewed profile floor",
-            policy.id,
-            lowering.backend
-        );
-    }
-    Ok(())
-}
-
-enum PackedAluRecipeSource {
-    Imported {
-        record: &'static str,
-        symbol: &'static str,
-        resolved_symbol: Option<&'static str>,
-        arguments: &'static [&'static str],
-        results: &'static [&'static str],
-        properties: &'static [&'static str],
-        selection: &'static str,
-        selection_asm: &'static str,
-    },
-    PtxNative,
-}
-
-struct PackedAluRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    rust_name: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    arity: usize,
-    must_use: bool,
-    ptx_mnemonic: &'static str,
-    modifiers: &'static [&'static str],
-    native_minimum_sm: u16,
-    minimum_ptx: &'static str,
-    minimum_sm: &'static str,
-    ptx_isa_section: &'static str,
-    ptx_isa_url: &'static str,
-    source: PackedAluRecipeSource,
-}
-
-/// Returns the closed recipe for a packed-ALU (format, operation) pair.
-///
-/// `None` means the pair is outside the family: the operation exists for some
-/// other format but this one has no reviewed lowering for it.
-fn packed_alu_recipe(
-    format: PackedAluFormat,
-    operation: PackedAluOperation,
-) -> Option<PackedAluRecipe> {
-    match format {
-        PackedAluFormat::Bf16x2 => packed_bf16x2_alu_recipe(operation),
-        PackedAluFormat::F16x2 => packed_f16x2_alu_recipe(operation),
-        PackedAluFormat::F32x2 => packed_f32x2_alu_recipe(operation),
-    }
-}
-
-fn packed_f32x2_alu_recipe(operation: PackedAluOperation) -> Option<PackedAluRecipe> {
-    let (
-        id,
-        abi_id,
-        operation_key,
-        rust_name,
-        dialect_op_type,
-        dialect_op_name,
-        arity,
-        head,
-        modifiers,
-        section,
-        url,
-    ) = match operation {
-        PackedAluOperation::Add => (
-            "add_f32x2",
-            "i0995",
-            "packed.alu.f32x2.add",
-            "add_f32x2",
-            "AddF32x2Op",
-            "nvvm.add_f32x2",
-            2,
-            "add.rn.f32x2",
-            &["rn", "f32x2"][..],
-            "9.7.3.1 Floating Point Instructions: add",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-add",
-        ),
-        PackedAluOperation::AddFtz => (
-            "add_ftz_f32x2",
-            "i0996",
-            "packed.alu.f32x2.add.ftz",
-            "add_ftz_f32x2",
-            "AddFtzF32x2Op",
-            "nvvm.add_ftz_f32x2",
-            2,
-            "add.rn.ftz.f32x2",
-            &["rn", "ftz", "f32x2"][..],
-            "9.7.3.1 Floating Point Instructions: add",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-add",
-        ),
-        PackedAluOperation::Sub => (
-            "sub_f32x2",
-            "i0997",
-            "packed.alu.f32x2.sub",
-            "sub_f32x2",
-            "SubF32x2Op",
-            "nvvm.sub_f32x2",
-            2,
-            "sub.rn.f32x2",
-            &["rn", "f32x2"][..],
-            "9.7.3.2 Floating Point Instructions: sub",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-sub",
-        ),
-        PackedAluOperation::SubFtz => (
-            "sub_ftz_f32x2",
-            "i0998",
-            "packed.alu.f32x2.sub.ftz",
-            "sub_ftz_f32x2",
-            "SubFtzF32x2Op",
-            "nvvm.sub_ftz_f32x2",
-            2,
-            "sub.rn.ftz.f32x2",
-            &["rn", "ftz", "f32x2"][..],
-            "9.7.3.2 Floating Point Instructions: sub",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-sub",
-        ),
-        PackedAluOperation::Mul => (
-            "mul_f32x2",
-            "i0999",
-            "packed.alu.f32x2.mul",
-            "mul_f32x2",
-            "MulF32x2Op",
-            "nvvm.mul_f32x2",
-            2,
-            "mul.rn.f32x2",
-            &["rn", "f32x2"][..],
-            "9.7.3.3 Floating Point Instructions: mul",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-mul",
-        ),
-        PackedAluOperation::MulFtz => (
-            "mul_ftz_f32x2",
-            "i1000",
-            "packed.alu.f32x2.mul.ftz",
-            "mul_ftz_f32x2",
-            "MulFtzF32x2Op",
-            "nvvm.mul_ftz_f32x2",
-            2,
-            "mul.rn.ftz.f32x2",
-            &["rn", "ftz", "f32x2"][..],
-            "9.7.3.3 Floating Point Instructions: mul",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-mul",
-        ),
-        PackedAluOperation::Fma => (
-            "fma_f32x2",
-            "i1001",
-            "packed.alu.f32x2.fma",
-            "fma_f32x2",
-            "FmaF32x2Op",
-            "nvvm.fma_f32x2",
-            3,
-            "fma.rn.f32x2",
-            &["rn", "f32x2"][..],
-            "9.7.3.4 Floating Point Instructions: fma",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-fma",
-        ),
-        PackedAluOperation::FmaFtz => (
-            "fma_ftz_f32x2",
-            "i1002",
-            "packed.alu.f32x2.fma.ftz",
-            "fma_ftz_f32x2",
-            "FmaFtzF32x2Op",
-            "nvvm.fma_ftz_f32x2",
-            3,
-            "fma.rn.ftz.f32x2",
-            &["rn", "ftz", "f32x2"][..],
-            "9.7.3.4 Floating Point Instructions: fma",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-fma",
-        ),
-        _ => return None,
-    };
-    Some(PackedAluRecipe {
-        id,
-        abi_id,
-        operation_key,
-        rust_name,
-        dialect_op_type,
-        dialect_op_name,
-        arity,
-        must_use: true,
-        ptx_mnemonic: head,
-        modifiers,
-        native_minimum_sm: 100,
-        minimum_ptx: "8.6",
-        minimum_sm: "sm_100",
-        ptx_isa_section: section,
-        ptx_isa_url: url,
-        source: PackedAluRecipeSource::PtxNative,
-    })
-}
-
-fn packed_bf16x2_alu_recipe(operation: PackedAluOperation) -> Option<PackedAluRecipe> {
-    const PURE: &[&str] = &["IntrNoMem", "IntrSpeculatable"];
-    const COMMUTATIVE_PURE: &[&str] = &["Commutative", "IntrNoMem", "IntrSpeculatable"];
-    Some(match operation {
-        PackedAluOperation::Fma => PackedAluRecipe {
-            id: "fma_bf16x2",
-            abi_id: "i0062",
-            operation_key: "packed.alu.bf16x2.fma",
-            rust_name: "fma_bf16x2",
-            dialect_op_type: "FmaBf16x2Op",
-            dialect_op_name: "nvvm.fma_bf16x2",
-            arity: 3,
-            must_use: false,
-            ptx_mnemonic: "fma.rn.bf16x2",
-            modifiers: &["rn", "bf16x2"],
-            native_minimum_sm: 80,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fma_rn_bf16x2",
-                symbol: "llvm.nvvm.fma.rn.bf16x2",
-                resolved_symbol: None,
-                arguments: &["v2bf16", "v2bf16", "v2bf16"],
-                results: &["v2bf16"],
-                properties: PURE,
-                selection: "INT_NVVM_FMA_rn_bf16x2",
-                selection_asm: "fma.rn.bf16x2 \t$dst, $src0, $src1, $src2;",
-            },
-        },
-        PackedAluOperation::FmaRelu => PackedAluRecipe {
-            id: "fma_relu_bf16x2",
-            abi_id: "i0063",
-            operation_key: "packed.alu.bf16x2.fma.relu",
-            rust_name: "fma_relu_bf16x2",
-            dialect_op_type: "FmaReluBf16x2Op",
-            dialect_op_name: "nvvm.fma_relu_bf16x2",
-            arity: 3,
-            must_use: false,
-            ptx_mnemonic: "fma.rn.relu.bf16x2",
-            modifiers: &["rn", "relu", "bf16x2"],
-            native_minimum_sm: 80,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fma_rn_relu_bf16x2",
-                symbol: "llvm.nvvm.fma.rn.relu.bf16x2",
-                resolved_symbol: None,
-                arguments: &["v2bf16", "v2bf16", "v2bf16"],
-                results: &["v2bf16"],
-                properties: PURE,
-                selection: "INT_NVVM_FMA_rn_relu_bf16x2",
-                selection_asm: "fma.rn.relu.bf16x2 \t$dst, $src0, $src1, $src2;",
-            },
-        },
-        PackedAluOperation::Add => PackedAluRecipe {
-            id: "add_bf16x2",
-            abi_id: "i0064",
-            operation_key: "packed.alu.bf16x2.add",
-            rust_name: "add_bf16x2",
-            dialect_op_type: "AddBf16x2Op",
-            dialect_op_name: "nvvm.add_bf16x2",
-            arity: 2,
-            must_use: false,
-            ptx_mnemonic: "add.rn.bf16x2",
-            modifiers: &["rn", "bf16x2"],
-            native_minimum_sm: 90,
-            minimum_ptx: "7.8",
-            minimum_sm: "sm_90",
-            ptx_isa_section: "9.7.4.1 Half Precision Floating Point Instructions: add",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-add",
-            source: PackedAluRecipeSource::PtxNative,
-        },
-        PackedAluOperation::Sub => PackedAluRecipe {
-            id: "sub_bf16x2",
-            abi_id: "i0065",
-            operation_key: "packed.alu.bf16x2.sub",
-            rust_name: "sub_bf16x2",
-            dialect_op_type: "SubBf16x2Op",
-            dialect_op_name: "nvvm.sub_bf16x2",
-            arity: 2,
-            must_use: false,
-            ptx_mnemonic: "sub.rn.bf16x2",
-            modifiers: &["rn", "bf16x2"],
-            native_minimum_sm: 90,
-            minimum_ptx: "7.8",
-            minimum_sm: "sm_90",
-            ptx_isa_section: "9.7.4.2 Half Precision Floating Point Instructions: sub",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-sub",
-            source: PackedAluRecipeSource::PtxNative,
-        },
-        PackedAluOperation::Mul => PackedAluRecipe {
-            id: "mul_bf16x2",
-            abi_id: "i0066",
-            operation_key: "packed.alu.bf16x2.mul",
-            rust_name: "mul_bf16x2",
-            dialect_op_type: "MulBf16x2Op",
-            dialect_op_name: "nvvm.mul_bf16x2",
-            arity: 2,
-            must_use: false,
-            ptx_mnemonic: "mul.rn.bf16x2",
-            modifiers: &["rn", "bf16x2"],
-            native_minimum_sm: 90,
-            minimum_ptx: "7.8",
-            minimum_sm: "sm_90",
-            ptx_isa_section: "9.7.4.3 Half Precision Floating Point Instructions: mul",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-mul",
-            source: PackedAluRecipeSource::PtxNative,
-        },
-        PackedAluOperation::Min => PackedAluRecipe {
-            id: "min_bf16x2",
-            abi_id: "i0067",
-            operation_key: "packed.alu.bf16x2.min",
-            rust_name: "min_bf16x2",
-            dialect_op_type: "MinBf16x2Op",
-            dialect_op_name: "nvvm.min_bf16x2",
-            arity: 2,
-            must_use: false,
-            ptx_mnemonic: "min.bf16x2",
-            modifiers: &["bf16x2"],
-            native_minimum_sm: 80,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_isa_section: "9.7.4.7 Half Precision Floating Point Instructions: min",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-min",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fmin_bf16x2",
-                symbol: "llvm.nvvm.fmin.bf16x2",
-                resolved_symbol: None,
-                arguments: &["v2bf16", "v2bf16"],
-                results: &["v2bf16"],
-                properties: COMMUTATIVE_PURE,
-                selection: "INT_NVVM_FMIN_bf16x2",
-                selection_asm: "min.bf16x2 \t$dst, $src0, $src1;",
-            },
-        },
-        PackedAluOperation::Max => PackedAluRecipe {
-            id: "max_bf16x2",
-            abi_id: "i0068",
-            operation_key: "packed.alu.bf16x2.max",
-            rust_name: "max_bf16x2",
-            dialect_op_type: "MaxBf16x2Op",
-            dialect_op_name: "nvvm.max_bf16x2",
-            arity: 2,
-            must_use: false,
-            ptx_mnemonic: "max.bf16x2",
-            modifiers: &["bf16x2"],
-            native_minimum_sm: 80,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_isa_section: "9.7.4.8 Half Precision Floating Point Instructions: max",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-max",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fmax_bf16x2",
-                symbol: "llvm.nvvm.fmax.bf16x2",
-                resolved_symbol: None,
-                arguments: &["v2bf16", "v2bf16"],
-                results: &["v2bf16"],
-                properties: COMMUTATIVE_PURE,
-                selection: "INT_NVVM_FMAN_bf16x2",
-                selection_asm: "max.bf16x2 \t$dst, $src0, $src1;",
-            },
-        },
-        PackedAluOperation::Neg => PackedAluRecipe {
-            id: "neg_bf16x2",
-            abi_id: "i0069",
-            operation_key: "packed.alu.bf16x2.neg",
-            rust_name: "neg_bf16x2",
-            dialect_op_type: "NegBf16x2Op",
-            dialect_op_name: "nvvm.neg_bf16x2",
-            arity: 1,
-            must_use: false,
-            ptx_mnemonic: "neg.bf16x2",
-            modifiers: &["bf16x2"],
-            native_minimum_sm: 80,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_isa_section: "9.7.4.5 Half Precision Floating Point Instructions: neg",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-neg",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_neg_bf16x2",
-                symbol: "llvm.nvvm.neg.bf16x2",
-                resolved_symbol: None,
-                arguments: &["v2bf16"],
-                results: &["v2bf16"],
-                properties: PURE,
-                selection: "INT_NVVM_NEG_BF16X2",
-                selection_asm: "neg.bf16x2 \t$dst, $src0;",
-            },
-        },
-        PackedAluOperation::Abs => PackedAluRecipe {
-            id: "abs_bf16x2",
-            abi_id: "i0070",
-            operation_key: "packed.alu.bf16x2.abs",
-            rust_name: "abs_bf16x2",
-            dialect_op_type: "AbsBf16x2Op",
-            dialect_op_name: "nvvm.abs_bf16x2",
-            arity: 1,
-            must_use: false,
-            ptx_mnemonic: "abs.bf16x2",
-            modifiers: &["bf16x2"],
-            native_minimum_sm: 80,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_isa_section: "9.7.4.6 Half Precision Floating Point Instructions: abs",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-abs",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fabs",
-                symbol: "llvm.nvvm.fabs",
-                resolved_symbol: Some("llvm.nvvm.fabs.v2bf16"),
-                arguments: &["anonymous_14"],
-                results: &["anyfloat"],
-                properties: PURE,
-                selection: "ABS_BF16X2",
-                selection_asm: "abs.bf16x2 \t$dst, $src0;",
-            },
-        },
-        // The f32x2-only operation keys are outside this admission. The ftz
-        // and sat fma forms also do not exist for bf16x2 in the PTX ISA at
-        // all: ptxas rejects hand-written `fma.rn.ftz.bf16x2` with
-        // "Illegal modifier '.ftz' for instruction 'fma'", and accepts
-        // `fma.rn.relu.bf16x2` beside it. LLVM declares the intrinsics anyway,
-        // so instruction selection is what fails first ("Cannot select:
-        // intrinsic %llvm.nvvm.fma.rn.ftz.bf16x2"), but the assembler is the
-        // authority here. Reject them rather than admit a recipe that has no
-        // instruction to lower to.
-        PackedAluOperation::AddFtz
-        | PackedAluOperation::SubFtz
-        | PackedAluOperation::MulFtz
-        | PackedAluOperation::FmaFtz
-        | PackedAluOperation::FmaSat
-        | PackedAluOperation::FmaFtzSat
-        | PackedAluOperation::FmaFtzRelu => return None,
-    })
-}
-
-fn packed_f16x2_alu_recipe(operation: PackedAluOperation) -> Option<PackedAluRecipe> {
-    const PURE: &[&str] = &["IntrNoMem", "IntrSpeculatable"];
-    const COMMUTATIVE_PURE: &[&str] = &["Commutative", "IntrNoMem", "IntrSpeculatable"];
-    Some(match operation {
-        PackedAluOperation::Fma => PackedAluRecipe {
-            id: "fma_f16x2",
-            abi_id: "i0072",
-            operation_key: "packed.alu.f16x2.fma",
-            rust_name: "fma_f16x2",
-            dialect_op_type: "FmaF16x2Op",
-            dialect_op_name: "nvvm.fma_f16x2",
-            arity: 3,
-            must_use: true,
-            ptx_mnemonic: "fma.rn.f16x2",
-            modifiers: &["rn", "f16x2"],
-            native_minimum_sm: 53,
-            minimum_ptx: "4.2",
-            minimum_sm: "sm_70",
-            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fma_rn_f16x2",
-                symbol: "llvm.nvvm.fma.rn.f16x2",
-                resolved_symbol: None,
-                arguments: &["v2f16", "v2f16", "v2f16"],
-                results: &["v2f16"],
-                properties: PURE,
-                selection: "INT_NVVM_FMA_rn_f16x2",
-                selection_asm: "fma.rn.f16x2 \t$dst, $src0, $src1, $src2;",
-            },
-        },
-        PackedAluOperation::FmaFtz => PackedAluRecipe {
-            id: "fma_ftz_f16x2",
-            abi_id: "i0854",
-            operation_key: "packed.alu.f16x2.fma.ftz",
-            rust_name: "fma_ftz_f16x2",
-            dialect_op_type: "FmaFtzF16x2Op",
-            dialect_op_name: "nvvm.fma_ftz_f16x2",
-            arity: 3,
-            must_use: true,
-            ptx_mnemonic: "fma.rn.ftz.f16x2",
-            modifiers: &["rn", "ftz", "f16x2"],
-            native_minimum_sm: 53,
-            minimum_ptx: "4.2",
-            minimum_sm: "sm_70",
-            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fma_rn_ftz_f16x2",
-                symbol: "llvm.nvvm.fma.rn.ftz.f16x2",
-                resolved_symbol: None,
-                arguments: &["v2f16", "v2f16", "v2f16"],
-                results: &["v2f16"],
-                properties: PURE,
-                selection: "INT_NVVM_FMA_rn_ftz_f16x2",
-                selection_asm: "fma.rn.ftz.f16x2 \t$dst, $src0, $src1, $src2;",
-            },
-        },
-        PackedAluOperation::FmaSat => PackedAluRecipe {
-            id: "fma_sat_f16x2",
-            abi_id: "i0855",
-            operation_key: "packed.alu.f16x2.fma.sat",
-            rust_name: "fma_sat_f16x2",
-            dialect_op_type: "FmaSatF16x2Op",
-            dialect_op_name: "nvvm.fma_sat_f16x2",
-            arity: 3,
-            must_use: true,
-            ptx_mnemonic: "fma.rn.sat.f16x2",
-            modifiers: &["rn", "sat", "f16x2"],
-            native_minimum_sm: 53,
-            minimum_ptx: "4.2",
-            minimum_sm: "sm_70",
-            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fma_rn_sat_f16x2",
-                symbol: "llvm.nvvm.fma.rn.sat.f16x2",
-                resolved_symbol: None,
-                arguments: &["v2f16", "v2f16", "v2f16"],
-                results: &["v2f16"],
-                properties: PURE,
-                selection: "INT_NVVM_FMA_rn_sat_f16x2",
-                selection_asm: "fma.rn.sat.f16x2 \t$dst, $src0, $src1, $src2;",
-            },
-        },
-        PackedAluOperation::FmaFtzSat => PackedAluRecipe {
-            id: "fma_ftz_sat_f16x2",
-            abi_id: "i0856",
-            operation_key: "packed.alu.f16x2.fma.ftz.sat",
-            rust_name: "fma_ftz_sat_f16x2",
-            dialect_op_type: "FmaFtzSatF16x2Op",
-            dialect_op_name: "nvvm.fma_ftz_sat_f16x2",
-            arity: 3,
-            must_use: true,
-            ptx_mnemonic: "fma.rn.ftz.sat.f16x2",
-            modifiers: &["rn", "ftz", "sat", "f16x2"],
-            native_minimum_sm: 53,
-            minimum_ptx: "4.2",
-            minimum_sm: "sm_70",
-            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fma_rn_ftz_sat_f16x2",
-                symbol: "llvm.nvvm.fma.rn.ftz.sat.f16x2",
-                resolved_symbol: None,
-                arguments: &["v2f16", "v2f16", "v2f16"],
-                results: &["v2f16"],
-                properties: PURE,
-                selection: "INT_NVVM_FMA_rn_ftz_sat_f16x2",
-                selection_asm: "fma.rn.ftz.sat.f16x2 \t$dst, $src0, $src1, $src2;",
-            },
-        },
-        PackedAluOperation::FmaRelu => PackedAluRecipe {
-            id: "fma_relu_f16x2",
-            abi_id: "i0073",
-            operation_key: "packed.alu.f16x2.fma.relu",
-            rust_name: "fma_relu_f16x2",
-            dialect_op_type: "FmaReluF16x2Op",
-            dialect_op_name: "nvvm.fma_relu_f16x2",
-            arity: 3,
-            must_use: true,
-            ptx_mnemonic: "fma.rn.relu.f16x2",
-            modifiers: &["rn", "relu", "f16x2"],
-            native_minimum_sm: 80,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fma_rn_relu_f16x2",
-                symbol: "llvm.nvvm.fma.rn.relu.f16x2",
-                resolved_symbol: None,
-                arguments: &["v2f16", "v2f16", "v2f16"],
-                results: &["v2f16"],
-                properties: PURE,
-                selection: "INT_NVVM_FMA_rn_relu_f16x2",
-                selection_asm: "fma.rn.relu.f16x2 \t$dst, $src0, $src1, $src2;",
-            },
-        },
-        PackedAluOperation::FmaFtzRelu => PackedAluRecipe {
-            id: "fma_ftz_relu_f16x2",
-            abi_id: "i0857",
-            operation_key: "packed.alu.f16x2.fma.ftz.relu",
-            rust_name: "fma_ftz_relu_f16x2",
-            dialect_op_type: "FmaFtzReluF16x2Op",
-            dialect_op_name: "nvvm.fma_ftz_relu_f16x2",
-            arity: 3,
-            must_use: true,
-            ptx_mnemonic: "fma.rn.ftz.relu.f16x2",
-            modifiers: &["rn", "ftz", "relu", "f16x2"],
-            native_minimum_sm: 80,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fma_rn_ftz_relu_f16x2",
-                symbol: "llvm.nvvm.fma.rn.ftz.relu.f16x2",
-                resolved_symbol: None,
-                arguments: &["v2f16", "v2f16", "v2f16"],
-                results: &["v2f16"],
-                properties: PURE,
-                selection: "INT_NVVM_FMA_rn_ftz_relu_f16x2",
-                selection_asm: "fma.rn.ftz.relu.f16x2 \t$dst, $src0, $src1, $src2;",
-            },
-        },
-        PackedAluOperation::Add => PackedAluRecipe {
-            id: "add_f16x2",
-            abi_id: "i0074",
-            operation_key: "packed.alu.f16x2.add",
-            rust_name: "add_f16x2",
-            dialect_op_type: "AddF16x2Op",
-            dialect_op_name: "nvvm.add_f16x2",
-            arity: 2,
-            must_use: true,
-            ptx_mnemonic: "add.rn.f16x2",
-            modifiers: &["rn", "f16x2"],
-            native_minimum_sm: 53,
-            minimum_ptx: "4.2",
-            minimum_sm: "sm_70",
-            ptx_isa_section: "9.7.4.1 Half Precision Floating Point Instructions: add",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-add",
-            source: PackedAluRecipeSource::PtxNative,
-        },
-        PackedAluOperation::Sub => PackedAluRecipe {
-            id: "sub_f16x2",
-            abi_id: "i0075",
-            operation_key: "packed.alu.f16x2.sub",
-            rust_name: "sub_f16x2",
-            dialect_op_type: "SubF16x2Op",
-            dialect_op_name: "nvvm.sub_f16x2",
-            arity: 2,
-            must_use: true,
-            ptx_mnemonic: "sub.rn.f16x2",
-            modifiers: &["rn", "f16x2"],
-            native_minimum_sm: 53,
-            minimum_ptx: "4.2",
-            minimum_sm: "sm_70",
-            ptx_isa_section: "9.7.4.2 Half Precision Floating Point Instructions: sub",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-sub",
-            source: PackedAluRecipeSource::PtxNative,
-        },
-        PackedAluOperation::Mul => PackedAluRecipe {
-            id: "mul_f16x2",
-            abi_id: "i0076",
-            operation_key: "packed.alu.f16x2.mul",
-            rust_name: "mul_f16x2",
-            dialect_op_type: "MulF16x2Op",
-            dialect_op_name: "nvvm.mul_f16x2",
-            arity: 2,
-            must_use: true,
-            ptx_mnemonic: "mul.rn.f16x2",
-            modifiers: &["rn", "f16x2"],
-            native_minimum_sm: 53,
-            minimum_ptx: "4.2",
-            minimum_sm: "sm_70",
-            ptx_isa_section: "9.7.4.3 Half Precision Floating Point Instructions: mul",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-mul",
-            source: PackedAluRecipeSource::PtxNative,
-        },
-        PackedAluOperation::Min => PackedAluRecipe {
-            id: "min_f16x2",
-            abi_id: "i0077",
-            operation_key: "packed.alu.f16x2.min",
-            rust_name: "min_f16x2",
-            dialect_op_type: "MinF16x2Op",
-            dialect_op_name: "nvvm.min_f16x2",
-            arity: 2,
-            must_use: true,
-            ptx_mnemonic: "min.f16x2",
-            modifiers: &["f16x2"],
-            native_minimum_sm: 80,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_isa_section: "9.7.4.7 Half Precision Floating Point Instructions: min",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-min",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fmin_f16x2",
-                symbol: "llvm.nvvm.fmin.f16x2",
-                resolved_symbol: None,
-                arguments: &["v2f16", "v2f16"],
-                results: &["v2f16"],
-                properties: COMMUTATIVE_PURE,
-                selection: "INT_NVVM_FMIN_f16x2",
-                selection_asm: "min.f16x2 \t$dst, $src0, $src1;",
-            },
-        },
-        PackedAluOperation::Max => PackedAluRecipe {
-            id: "max_f16x2",
-            abi_id: "i0078",
-            operation_key: "packed.alu.f16x2.max",
-            rust_name: "max_f16x2",
-            dialect_op_type: "MaxF16x2Op",
-            dialect_op_name: "nvvm.max_f16x2",
-            arity: 2,
-            must_use: true,
-            ptx_mnemonic: "max.f16x2",
-            modifiers: &["f16x2"],
-            native_minimum_sm: 80,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_isa_section: "9.7.4.8 Half Precision Floating Point Instructions: max",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-max",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fmax_f16x2",
-                symbol: "llvm.nvvm.fmax.f16x2",
-                resolved_symbol: None,
-                arguments: &["v2f16", "v2f16"],
-                results: &["v2f16"],
-                properties: COMMUTATIVE_PURE,
-                selection: "INT_NVVM_FMAN_f16x2",
-                selection_asm: "max.f16x2 \t$dst, $src0, $src1;",
-            },
-        },
-        PackedAluOperation::Neg => PackedAluRecipe {
-            id: "neg_f16x2",
-            abi_id: "i0079",
-            operation_key: "packed.alu.f16x2.neg",
-            rust_name: "neg_f16x2",
-            dialect_op_type: "NegF16x2Op",
-            dialect_op_name: "nvvm.neg_f16x2",
-            arity: 1,
-            must_use: true,
-            ptx_mnemonic: "neg.f16x2",
-            modifiers: &["f16x2"],
-            native_minimum_sm: 53,
-            minimum_ptx: "6.0",
-            minimum_sm: "sm_70",
-            ptx_isa_section: "9.7.4.5 Half Precision Floating Point Instructions: neg",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-neg",
-            source: PackedAluRecipeSource::PtxNative,
-        },
-        PackedAluOperation::Abs => PackedAluRecipe {
-            id: "abs_f16x2",
-            abi_id: "i0080",
-            operation_key: "packed.alu.f16x2.abs",
-            rust_name: "abs_f16x2",
-            dialect_op_type: "AbsF16x2Op",
-            dialect_op_name: "nvvm.abs_f16x2",
-            arity: 1,
-            must_use: true,
-            ptx_mnemonic: "abs.f16x2",
-            modifiers: &["f16x2"],
-            native_minimum_sm: 53,
-            minimum_ptx: "6.5",
-            minimum_sm: "sm_70",
-            ptx_isa_section: "9.7.4.6 Half Precision Floating Point Instructions: abs",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-abs",
-            source: PackedAluRecipeSource::Imported {
-                record: "int_nvvm_fabs",
-                symbol: "llvm.nvvm.fabs",
-                resolved_symbol: Some("llvm.nvvm.fabs.v2f16"),
-                arguments: &["anonymous_14"],
-                results: &["anyfloat"],
-                properties: PURE,
-                selection: "ABS_F16X2",
-                selection_asm: "abs.f16x2 \t$dst, $src0;",
-            },
-        },
-        // These operations were added for the f32x2 admission. Keeping them
-        // outside the f16x2 recipe avoids silently expanding this PR's scope,
-        // even where a similarly spelled PTX form may exist.
-        PackedAluOperation::AddFtz | PackedAluOperation::SubFtz | PackedAluOperation::MulFtz => {
-            return None;
-        }
-    })
-}
-
-/// Per-backend PTX and SM floors, which can sit above the recipe's own floor.
-///
-/// Takes the caller's already-resolved recipe rather than looking it up again,
-/// so this cannot be reached with a pair the family rejects.
-fn packed_alu_backend_floor(
-    recipe: &PackedAluRecipe,
-    format: PackedAluFormat,
-    operation: PackedAluOperation,
-    backend: IntrinsicBackend,
-) -> (&'static str, &'static str) {
-    match (format, operation, backend) {
-        (
-            PackedAluFormat::F16x2,
-            PackedAluOperation::Fma
-            | PackedAluOperation::Add
-            | PackedAluOperation::Sub
-            | PackedAluOperation::Mul,
-            IntrinsicBackend::LlvmNvptx,
-        ) => ("6.0", "sm_70"),
-        (
-            PackedAluFormat::F16x2,
-            PackedAluOperation::Fma
-            | PackedAluOperation::Add
-            | PackedAluOperation::Sub
-            | PackedAluOperation::Mul,
-            IntrinsicBackend::LibNvvm,
-        ) => ("4.2", "sm_75"),
-        // The ftz and sat fma forms share the plain fma floors: PTX 4.2 natively,
-        // but the pinned LLVM backend needs 6.0 and CUDA 13.3 ptxas no longer
-        // targets sm_70, so libNVVM is checked at sm_75.
-        (
-            PackedAluFormat::F16x2,
-            PackedAluOperation::FmaFtz | PackedAluOperation::FmaSat | PackedAluOperation::FmaFtzSat,
-            IntrinsicBackend::LlvmNvptx,
-        ) => ("6.0", "sm_70"),
-        (
-            PackedAluFormat::F16x2,
-            PackedAluOperation::FmaFtz | PackedAluOperation::FmaSat | PackedAluOperation::FmaFtzSat,
-            IntrinsicBackend::LibNvvm,
-        ) => ("4.2", "sm_75"),
-        (PackedAluFormat::F16x2, PackedAluOperation::Neg, IntrinsicBackend::LlvmNvptx) => {
-            ("6.0", "sm_70")
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::Neg, IntrinsicBackend::LibNvvm) => {
-            ("6.0", "sm_75")
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::Abs, IntrinsicBackend::LlvmNvptx) => {
-            ("6.5", "sm_70")
-        }
-        (PackedAluFormat::F16x2, PackedAluOperation::Abs, IntrinsicBackend::LibNvvm) => {
-            ("6.5", "sm_75")
-        }
-        _ => (recipe.minimum_ptx, recipe.minimum_sm),
-    }
-}
-
-fn validate_packed_alu_policy(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-    declaration: Option<&ImportedIntrinsic>,
-) -> Result<()> {
-    let packed = policy
-        .packed_alu
-        .as_ref()
-        .with_context(|| format!("{} has no closed packed-ALU contract", policy.id))?;
-    let recipe = packed_alu_recipe(packed.format, packed.operation)
-        .with_context(|| format!("{} is outside the closed packed-ALU recipe", policy.id))?;
-    let (rust_module, rust_type, dialect_type, expected_adapter) = match packed.format {
-        PackedAluFormat::Bf16x2 => ("bf16x2", "u32", "i32", PackedAluAdapter::DirectPackedU32),
-        PackedAluFormat::F16x2 => ("f16x2", "u32", "i32", PackedAluAdapter::DirectPackedU32),
-        PackedAluFormat::F32x2 => ("f32x2", "u64", "i64", PackedAluAdapter::DirectPackedU64),
-    };
-    ensure!(
-        packed.adapter == expected_adapter,
-        "{} requests an unsupported packed-ALU adapter",
-        policy.id
-    );
-    let rust_arguments = vec![rust_type; recipe.arity];
-    let dialect_operands = vec![dialect_type; recipe.arity];
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key,
-        "{} packed-ALU identity does not match its closed operation recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == rust_module
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == rust_arguments
-            && policy.rust_result == rust_type
-            && policy.safe
-            && policy.must_use == recipe.must_use
-            && policy
-                .safe_allowlist_reason
-                .as_deref()
-                .is_some_and(|reason| !reason.trim().is_empty())
-            && policy.public_rust_path
-                == format!("cuda_intrinsics::{rust_module}::{}", recipe.rust_name)
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::{rust_module}::{}", recipe.rust_name)],
-        "{} must preserve its reviewed safe packed-ALU API",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == dialect_operands
-            && policy.dialect_results == [dialect_type]
-            && policy.lowering == "generated_packed_alu_inline_ptx",
-        "{} is outside the closed packed-ALU dialect and lowering recipe",
-        policy.id
-    );
-    ensure!(
-        policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
-            && policy.ptx_result == rust_type
-            && policy.targets == "all"
-            && packed.native_minimum_sm == recipe.native_minimum_sm,
-        "{} packed-ALU effects, carrier, or target floor disagree",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.ptx_isa_section
-            && policy.ptx_isa_url == recipe.ptx_isa_url,
-        "{} packed-ALU PTX provenance does not match its reviewed instruction section",
-        policy.id
-    );
-    let expected_operands = vec![OperandPattern::Register; recipe.arity + 1];
-    ensure!(
-        policy.expected_ptx.mnemonic
-            == recipe.ptx_mnemonic.split('.').next().expect("PTX mnemonic")
-            && policy.expected_ptx.modifiers == recipe.modifiers
-            && policy.expected_ptx.operands == expected_operands,
-        "{} expected PTX does not match its exact packed-ALU instruction",
-        policy.id
-    );
-
-    match &recipe.source {
-        PackedAluRecipeSource::PtxNative => {
-            ensure!(
-                source
-                    == &IntrinsicSource::PtxNative {
-                        instruction: recipe.ptx_mnemonic.to_owned(),
-                    }
-                    && declaration.is_none(),
-                "{} packed-ALU source does not match its PTX-native recipe",
-                policy.id
-            );
-        }
-        PackedAluRecipeSource::Imported {
-            record,
-            symbol,
-            resolved_symbol,
-            arguments,
-            results,
-            properties,
-            selection,
-            selection_asm,
-        } => {
-            let declaration = declaration.context("imported packed ALU has no declaration")?;
-            ensure!(
-                source
-                    == &IntrinsicSource::LlvmImported {
-                        source_record: (*record).to_owned(),
-                    }
-                    && policy.llvm_symbol.as_deref() == Some(*symbol)
-                    && policy.resolved_llvm_symbol.as_deref() == *resolved_symbol
-                    && policy.llvm_arguments == *arguments
-                    && policy.llvm_results == *results,
-                "{} packed-ALU LLVM source or signature changed",
-                policy.id
-            );
-            let matching_selections: Vec<_> = declaration
-                .selections
-                .iter()
-                .filter(|candidate| candidate.source_record == *selection)
-                .collect();
-            let expected_selection_count = if *record == "int_nvvm_fabs" { 6 } else { 1 };
-            ensure!(
-                declaration.properties == *properties
-                    && declaration.selections.len() == expected_selection_count
-                    && matching_selections.len() == 1
-                    && matching_selections[0].asm == *selection_asm
-                    && matching_selections[0].predicates
-                        == [
-                            format!("Subtarget->getSmVersion() >= {}", recipe.native_minimum_sm),
-                            format!(
-                                "Subtarget->getPTXVersion() >= {}",
-                                recipe.minimum_ptx.replace('.', "")
-                            ),
-                        ]
-                    && matching_selections[0].constraints.is_empty(),
-                "{} packed-ALU imported properties or selection changed",
-                policy.id
-            );
-        }
-    }
-    let llvm_floor = packed_alu_backend_floor(
-        &recipe,
-        packed.format,
-        packed.operation,
-        IntrinsicBackend::LlvmNvptx,
-    );
-    let libnvvm_floor = packed_alu_backend_floor(
-        &recipe,
-        packed.format,
-        packed.operation,
-        IntrinsicBackend::LibNvvm,
-    );
-    ensure_exact_inline_ptx_backends(
-        policy,
-        [
-            (
-                IntrinsicBackend::LlvmNvptx,
-                llvm_floor.0,
-                Some(llvm_floor.1),
-            ),
-            (
-                IntrinsicBackend::LibNvvm,
-                libnvvm_floor.0,
-                Some(libnvvm_floor.1),
-            ),
-        ],
-        "packed-ALU",
-    )?;
-    ensure_no_other_family_contract(policy, "packed-ALU")?;
-    Ok(())
-}
-
-struct PackedConversionRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    rust_name: &'static str,
-    compatibility_path: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    llvm_result: &'static str,
-    summary: &'static str,
-}
-
-struct CpAsyncCopyRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    rust_name: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    selections: &'static [&'static str],
-    summary: &'static str,
-}
-
-fn cp_async_copy_recipe(copy: &crate::model::CpAsyncCopy) -> Option<CpAsyncCopyRecipe> {
-    match (copy.cache_policy, copy.copy_size, copy.source_size) {
-        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B4, CpAsyncSourceSize::Full) => {
-            Some(CpAsyncCopyRecipe {
-                id: "cp_async_ca_4",
-                abi_id: "i0086",
-                operation_key: "memory.copy.async.global_to_shared.ca.4.full",
-                rust_name: "cp_async_ca_4",
-                dialect_op_type: "CpAsyncCa4Op",
-                dialect_op_name: "nvvm.cp_async_ca_4",
-                source_record: "int_nvvm_cp_async_ca_shared_global_4",
-                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.4",
-                selections: &["CP_ASYNC_CA_SHARED_GLOBAL_4"],
-                summary: "Starts a four-byte cache-all asynchronous copy from global to shared memory.",
-            })
-        }
-        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B4, CpAsyncSourceSize::Runtime) => {
-            Some(CpAsyncCopyRecipe {
-                id: "cp_async_ca_zfill_4",
-                abi_id: "i0087",
-                operation_key: "memory.copy.async.global_to_shared.ca.4.runtime_source_size",
-                rust_name: "cp_async_ca_zfill_4",
-                dialect_op_type: "CpAsyncCaZfill4Op",
-                dialect_op_name: "nvvm.cp_async_ca_zfill_4",
-                source_record: "int_nvvm_cp_async_ca_shared_global_4_s",
-                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.4.s",
-                selections: &[
-                    "CP_ASYNC_CA_SHARED_GLOBAL_4_s",
-                    "CP_ASYNC_CA_SHARED_GLOBAL_4_si",
-                ],
-                summary: "Starts a four-byte cache-all asynchronous copy and zero-fills bytes beyond the runtime source size.",
-            })
-        }
-        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B8, CpAsyncSourceSize::Full) => {
-            Some(CpAsyncCopyRecipe {
-                id: "cp_async_ca_8",
-                abi_id: "i0088",
-                operation_key: "memory.copy.async.global_to_shared.ca.8.full",
-                rust_name: "cp_async_ca_8",
-                dialect_op_type: "CpAsyncCa8Op",
-                dialect_op_name: "nvvm.cp_async_ca_8",
-                source_record: "int_nvvm_cp_async_ca_shared_global_8",
-                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.8",
-                selections: &["CP_ASYNC_CA_SHARED_GLOBAL_8"],
-                summary: "Starts an eight-byte cache-all asynchronous copy from global to shared memory.",
-            })
-        }
-        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B8, CpAsyncSourceSize::Runtime) => {
-            Some(CpAsyncCopyRecipe {
-                id: "cp_async_ca_zfill_8",
-                abi_id: "i0089",
-                operation_key: "memory.copy.async.global_to_shared.ca.8.runtime_source_size",
-                rust_name: "cp_async_ca_zfill_8",
-                dialect_op_type: "CpAsyncCaZfill8Op",
-                dialect_op_name: "nvvm.cp_async_ca_zfill_8",
-                source_record: "int_nvvm_cp_async_ca_shared_global_8_s",
-                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.8.s",
-                selections: &[
-                    "CP_ASYNC_CA_SHARED_GLOBAL_8_s",
-                    "CP_ASYNC_CA_SHARED_GLOBAL_8_si",
-                ],
-                summary: "Starts an eight-byte cache-all asynchronous copy and zero-fills bytes beyond the runtime source size.",
-            })
-        }
-        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B16, CpAsyncSourceSize::Full) => {
-            Some(CpAsyncCopyRecipe {
-                id: "cp_async_ca_16",
-                abi_id: "i0090",
-                operation_key: "memory.copy.async.global_to_shared.ca.16.full",
-                rust_name: "cp_async_ca_16",
-                dialect_op_type: "CpAsyncCa16Op",
-                dialect_op_name: "nvvm.cp_async_ca_16",
-                source_record: "int_nvvm_cp_async_ca_shared_global_16",
-                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.16",
-                selections: &["CP_ASYNC_CA_SHARED_GLOBAL_16"],
-                summary: "Starts a sixteen-byte cache-all asynchronous copy from global to shared memory.",
-            })
-        }
-        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B16, CpAsyncSourceSize::Runtime) => {
-            Some(CpAsyncCopyRecipe {
-                id: "cp_async_ca_zfill_16",
-                abi_id: "i0091",
-                operation_key: "memory.copy.async.global_to_shared.ca.16.runtime_source_size",
-                rust_name: "cp_async_ca_zfill_16",
-                dialect_op_type: "CpAsyncCaZfill16Op",
-                dialect_op_name: "nvvm.cp_async_ca_zfill_16",
-                source_record: "int_nvvm_cp_async_ca_shared_global_16_s",
-                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.16.s",
-                selections: &[
-                    "CP_ASYNC_CA_SHARED_GLOBAL_16_s",
-                    "CP_ASYNC_CA_SHARED_GLOBAL_16_si",
-                ],
-                summary: "Starts a sixteen-byte cache-all asynchronous copy and zero-fills bytes beyond the runtime source size.",
-            })
-        }
-        (CpAsyncCachePolicy::Cg, CpAsyncCopySize::B16, CpAsyncSourceSize::Full) => {
-            Some(CpAsyncCopyRecipe {
-                id: "cp_async_cg_16",
-                abi_id: "i0092",
-                operation_key: "memory.copy.async.global_to_shared.cg.16.full",
-                rust_name: "cp_async_cg_16",
-                dialect_op_type: "CpAsyncCg16Op",
-                dialect_op_name: "nvvm.cp_async_cg_16",
-                source_record: "int_nvvm_cp_async_cg_shared_global_16",
-                llvm_symbol: "llvm.nvvm.cp.async.cg.shared.global.16",
-                selections: &["CP_ASYNC_CG_SHARED_GLOBAL_16"],
-                summary: "Starts a sixteen-byte cache-global asynchronous copy from global to shared memory.",
-            })
-        }
-        (CpAsyncCachePolicy::Cg, CpAsyncCopySize::B16, CpAsyncSourceSize::Runtime) => {
-            Some(CpAsyncCopyRecipe {
-                id: "cp_async_cg_zfill_16",
-                abi_id: "i0093",
-                operation_key: "memory.copy.async.global_to_shared.cg.16.runtime_source_size",
-                rust_name: "cp_async_cg_zfill_16",
-                dialect_op_type: "CpAsyncCgZfill16Op",
-                dialect_op_name: "nvvm.cp_async_cg_zfill_16",
-                source_record: "int_nvvm_cp_async_cg_shared_global_16_s",
-                llvm_symbol: "llvm.nvvm.cp.async.cg.shared.global.16.s",
-                selections: &[
-                    "CP_ASYNC_CG_SHARED_GLOBAL_16_s",
-                    "CP_ASYNC_CG_SHARED_GLOBAL_16_si",
-                ],
-                summary: "Starts a sixteen-byte cache-global asynchronous copy and zero-fills bytes beyond the runtime source size.",
-            })
-        }
-        _ => None,
-    }
-}
-
-fn validate_cp_async_copy_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let copy = policy
-        .cp_async_copy
-        .as_ref()
-        .with_context(|| format!("{} has no closed cp.async copy contract", policy.id))?;
-    let recipe = cp_async_copy_recipe(copy).with_context(|| {
-        format!(
-            "{} requests an unsupported classic cp.async copy form",
-            policy.id
-        )
-    })?;
-    let dynamic_source_size = copy.source_size == CpAsyncSourceSize::Runtime;
-    let expected_adapter = if dynamic_source_size {
-        CpAsyncAdapter::DirectPointersAndSourceSize
-    } else {
-        CpAsyncAdapter::DirectPointers
-    };
-    ensure!(
-        copy.adapter == expected_adapter,
-        "{} cp.async source-size form and adapter disagree",
-        policy.id
-    );
-    ensure!(
-        copy.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} cannot claim unrecorded cp.async runtime validation",
-        policy.id
-    );
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} cp.async identity does not match its closed recipe",
-        policy.id
-    );
-    let rust_arguments = if dynamic_source_size {
-        vec!["*mut u32", "*const u8", "u32"]
-    } else {
-        vec!["*mut u32", "*const u32"]
-    };
-    ensure!(
-        policy.rust_module == "async_copy"
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == rust_arguments
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path
-                == format!("cuda_intrinsics::async_copy::{}", recipe.rust_name)
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::async_copy::{}", recipe.rust_name)],
-        "{} must preserve its unsafe cp.async raw and compatibility API",
-        policy.id
-    );
-    let llvm_arguments = if dynamic_source_size {
-        vec!["shared_ptr", "global_ptr", "i32"]
-    } else {
-        vec!["shared_ptr", "global_ptr"]
-    };
-    let dialect_operands = if dynamic_source_size {
-        vec!["ptr", "ptr", "i32"]
-    } else {
-        vec!["ptr", "ptr"]
-    };
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == dialect_operands
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == llvm_arguments
-            && policy.llvm_results.is_empty()
-            && policy.lowering == "generated_cp_async_copy",
-        "{} is outside the closed cp.async signature and lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read_write"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == "7.0"
-            && policy.minimum_sm.as_deref() == Some("sm_80")
-            && policy.ptx_result == "()"
-            && policy.targets == "all",
-        "{} cp.async effects or target floor disagree with the closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.9.26.3.1 Data Movement and Conversion Instructions: cp.async"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async",
-        "{} cp.async PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.summary == recipe.summary,
-        "{} cp.async summary does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.properties
-            == [
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-        "{} cp.async effects disagree with the imported LLVM declaration",
-        policy.id
-    );
-    let cache = match copy.cache_policy {
-        CpAsyncCachePolicy::Ca => "ca",
-        CpAsyncCachePolicy::Cg => "cg",
-    };
-    let mut operands = vec![
-        OperandPattern::Address,
-        OperandPattern::Address,
-        OperandPattern::Exact {
-            value: copy.copy_size.bytes().to_string(),
-        },
-    ];
-    if dynamic_source_size {
-        operands.push(OperandPattern::RegisterOrImmediate);
-    }
-    ensure!(
-        policy.expected_ptx.mnemonic == "cp"
-            && policy.expected_ptx.modifiers == ["async", cache, "shared", "global"]
-            && policy.expected_ptx.operands == operands,
-        "{} expected PTX does not match its cp.async recipe",
-        policy.id
-    );
-    let actual_selections: BTreeSet<_> = declaration
-        .selections
-        .iter()
-        .map(|selection| selection.source_record.as_str())
-        .collect();
-    ensure!(
-        actual_selections == recipe.selections.iter().copied().collect(),
-        "{} imported cp.async selection set changed",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ])
-            && policy.backend_lowerings.iter().all(|lowering| {
-                lowering.minimum_ptx.is_none()
-                    && lowering.minimum_sm.is_none()
-                    && !lowering.evidence_profile.trim().is_empty()
-            }),
-        "{} must define the reviewed typed-LLVM and inline-PTX cp.async routes",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "cp_async_copy")?;
-    ensure!(
-        policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes ldmatrix state with cp_async_copy",
-        policy.id
-    );
-    Ok(())
-}
-
-struct CpAsyncControlRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    rust_name: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    selection: &'static str,
-    ptx_modifier: &'static str,
-    summary: &'static str,
-}
-
-fn cp_async_control_recipe(operation: CpAsyncControlOperation) -> CpAsyncControlRecipe {
-    match operation {
-        CpAsyncControlOperation::CommitGroup => CpAsyncControlRecipe {
-            id: "cp_async_commit_group",
-            abi_id: "i0094",
-            operation_key: "memory.copy.async.group.commit",
-            rust_name: "cp_async_commit_group",
-            dialect_op_type: "CpAsyncCommitGroupOp",
-            dialect_op_name: "nvvm.cp_async_commit_group",
-            source_record: "int_nvvm_cp_async_commit_group",
-            llvm_symbol: "llvm.nvvm.cp.async.commit.group",
-            selection: "CP_ASYNC_COMMIT_GROUP",
-            ptx_modifier: "commit_group",
-            summary: "Commits this thread's uncommitted asynchronous copies as one group.",
-        },
-        CpAsyncControlOperation::WaitAll => CpAsyncControlRecipe {
-            id: "cp_async_wait_all",
-            abi_id: "i0095",
-            operation_key: "memory.copy.async.group.wait_all",
-            rust_name: "cp_async_wait_all",
-            dialect_op_type: "CpAsyncWaitAllOp",
-            dialect_op_name: "nvvm.cp_async_wait_all",
-            source_record: "int_nvvm_cp_async_wait_all",
-            llvm_symbol: "llvm.nvvm.cp.async.wait.all",
-            selection: "CP_ASYNC_WAIT_ALL",
-            ptx_modifier: "wait_all",
-            summary: "Waits for all asynchronous copy groups issued by this thread.",
-        },
-        CpAsyncControlOperation::WaitGroup => CpAsyncControlRecipe {
-            id: "cp_async_wait_group",
-            abi_id: "i0096",
-            operation_key: "memory.copy.async.group.wait_max_pending",
-            rust_name: "cp_async_wait_group",
-            dialect_op_type: "CpAsyncWaitGroupOp",
-            dialect_op_name: "nvvm.cp_async_wait_group",
-            source_record: "int_nvvm_cp_async_wait_group",
-            llvm_symbol: "llvm.nvvm.cp.async.wait.group",
-            selection: "CP_ASYNC_WAIT_GROUP",
-            ptx_modifier: "wait_group",
-            summary: "Waits until at most the compile-time constant number of recent asynchronous copy groups remain pending.",
-        },
-    }
-}
-
-fn validate_cp_async_control_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let control = policy
-        .cp_async_control
-        .as_ref()
-        .with_context(|| format!("{} has no closed cp.async control contract", policy.id))?;
-    let recipe = cp_async_control_recipe(control.operation);
-    let has_operand = control.operation == CpAsyncControlOperation::WaitGroup;
-    let expected_adapter = if has_operand {
-        CpAsyncControlAdapter::CompileTimeConstantMaxPending
-    } else {
-        CpAsyncControlAdapter::NoOperands
-    };
-    ensure!(
-        control.adapter == expected_adapter,
-        "{} cp.async control and adapter disagree",
-        policy.id
-    );
-    ensure!(
-        control.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} cannot claim unrecorded cp.async control runtime validation",
-        policy.id
-    );
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} cp.async control identity does not match its closed recipe",
-        policy.id
-    );
-    let rust_arguments = if has_operand { vec!["u32"] } else { vec![] };
-    let dialect_operands = if has_operand { vec!["i32"] } else { vec![] };
-    ensure!(
-        policy.rust_module == "async_copy"
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == rust_arguments
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path
-                == format!("cuda_intrinsics::async_copy::{}", recipe.rust_name)
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::async_copy::{}", recipe.rust_name)]
-            && policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == dialect_operands
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == dialect_operands
-            && policy.llvm_results.is_empty()
-            && policy.lowering == "generated_cp_async_control",
-        "{} is outside the closed cp.async control API and lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read_write"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == "7.0"
-            && policy.minimum_sm.as_deref() == Some("sm_80")
-            && policy.ptx_result == "()"
-            && policy.targets == "all",
-        "{} cp.async control effects or target floor disagree with the closed recipe",
-        policy.id
-    );
-    let (ptx_isa_section, ptx_isa_url) = match control.operation {
-        CpAsyncControlOperation::CommitGroup => (
-            "9.7.9.26.3.2 Data Movement and Conversion Instructions: cp.async.commit_group",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-commit-group",
-        ),
-        CpAsyncControlOperation::WaitAll | CpAsyncControlOperation::WaitGroup => (
-            "9.7.9.26.3.3 Data Movement and Conversion Instructions: cp.async.wait_group / cp.async.wait_all",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-wait-group-cp-async-wait-all",
-        ),
-    };
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == ptx_isa_section
-            && policy.ptx_isa_url == ptx_isa_url,
-        "{} cp.async control PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.summary == recipe.summary,
-        "{} cp.async control summary does not match its closed recipe",
-        policy.id
-    );
-    let expected_properties: Vec<String> = if has_operand {
-        vec!["ImmArg<arg0>".into()]
-    } else {
-        vec![]
-    };
-    ensure!(
-        declaration.properties == expected_properties,
-        "{} cp.async control properties disagree with the imported declaration",
-        policy.id
-    );
-    let operands = if has_operand {
-        vec![OperandPattern::Immediate]
-    } else {
-        vec![]
-    };
-    ensure!(
-        policy.expected_ptx.mnemonic == "cp"
-            && policy.expected_ptx.modifiers == ["async", recipe.ptx_modifier]
-            && policy.expected_ptx.operands == operands
-            && declaration.selections.len() == 1
-            && declaration.selections[0].source_record == recipe.selection,
-        "{} expected PTX or imported selection disagrees with its cp.async control recipe",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ])
-            && policy.backend_lowerings.iter().all(|lowering| {
-                lowering.minimum_ptx.is_none()
-                    && lowering.minimum_sm.is_none()
-                    && !lowering.evidence_profile.trim().is_empty()
-            }),
-        "{} must define the reviewed typed-LLVM and inline-PTX cp.async control routes",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "cp_async_control")?;
-    ensure!(
-        policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && policy.selected_address_space.is_none(),
-        "{} mixes ldmatrix state with cp_async_control",
-        policy.id
-    );
-    Ok(())
-}
-
-struct CpAsyncMbarrierRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    llvm_argument: &'static str,
-    selection: &'static str,
-    selection_asm: &'static str,
-    modifiers: &'static [&'static str],
-    summary: &'static str,
-}
-
-fn cp_async_mbarrier_recipe(
-    operation: CpAsyncMbarrierOperation,
-    state_space: CpAsyncMbarrierStateSpace,
-) -> CpAsyncMbarrierRecipe {
-    match (operation, state_space) {
-        (CpAsyncMbarrierOperation::Arrive, CpAsyncMbarrierStateSpace::Generic) => {
-            CpAsyncMbarrierRecipe {
-                id: "cp_async_mbarrier_arrive",
-                abi_id: "i0101",
-                operation_key: "memory.copy.async.mbarrier.arrive.generic.increment",
-                dialect_op_type: "CpAsyncMbarrierArriveOp",
-                dialect_op_name: "nvvm.cp_async_mbarrier_arrive",
-                source_record: "int_nvvm_cp_async_mbarrier_arrive",
-                llvm_symbol: "llvm.nvvm.cp.async.mbarrier.arrive",
-                llvm_argument: "ptr",
-                selection: "CP_ASYNC_MBARRIER_ARRIVE",
-                selection_asm: "cp.async.mbarrier.arrive.b64 \t[$addr];",
-                modifiers: &["async", "mbarrier", "arrive", "b64"],
-                summary: "Associates this thread's prior asynchronous copies with a shared-memory barrier using balanced pending-count accounting.",
-            }
-        }
-        (CpAsyncMbarrierOperation::ArriveNoInc, CpAsyncMbarrierStateSpace::Generic) => {
-            CpAsyncMbarrierRecipe {
-                id: "cp_async_mbarrier_arrive_noinc",
-                abi_id: "i0103",
-                operation_key: "memory.copy.async.mbarrier.arrive.generic.no_increment",
-                dialect_op_type: "CpAsyncMbarrierArriveNoIncOp",
-                dialect_op_name: "nvvm.cp_async_mbarrier_arrive_noinc",
-                source_record: "int_nvvm_cp_async_mbarrier_arrive_noinc",
-                llvm_symbol: "llvm.nvvm.cp.async.mbarrier.arrive.noinc",
-                llvm_argument: "ptr",
-                selection: "CP_ASYNC_MBARRIER_ARRIVE_NOINC",
-                selection_asm: "cp.async.mbarrier.arrive.noinc.b64 \t[$addr];",
-                modifiers: &["async", "mbarrier", "arrive", "noinc", "b64"],
-                summary: "Associates this thread's prior asynchronous copies with a shared-memory barrier without incrementing its pending count.",
-            }
-        }
-        (CpAsyncMbarrierOperation::ArriveNoInc, CpAsyncMbarrierStateSpace::Shared) => {
-            CpAsyncMbarrierRecipe {
-                id: "cp_async_mbarrier_arrive_noinc_shared",
-                abi_id: "i0104",
-                operation_key: "memory.copy.async.mbarrier.arrive.shared.no_increment",
-                dialect_op_type: "CpAsyncMbarrierArriveNoIncSharedOp",
-                dialect_op_name: "nvvm.cp_async_mbarrier_arrive_noinc_shared",
-                source_record: "int_nvvm_cp_async_mbarrier_arrive_noinc_shared",
-                llvm_symbol: "llvm.nvvm.cp.async.mbarrier.arrive.noinc.shared",
-                llvm_argument: "shared_ptr",
-                selection: "CP_ASYNC_MBARRIER_ARRIVE_NOINC_SHARED",
-                selection_asm: "cp.async.mbarrier.arrive.noinc.shared.b64 \t[$addr];",
-                modifiers: &["async", "mbarrier", "arrive", "noinc", "shared", "b64"],
-                summary: "Associates this thread's prior asynchronous copies with a shared-address barrier without incrementing its pending count.",
-            }
-        }
-        (CpAsyncMbarrierOperation::Arrive, CpAsyncMbarrierStateSpace::Shared) => {
-            CpAsyncMbarrierRecipe {
-                id: "cp_async_mbarrier_arrive_shared",
-                abi_id: "i0102",
-                operation_key: "memory.copy.async.mbarrier.arrive.shared.increment",
-                dialect_op_type: "CpAsyncMbarrierArriveSharedOp",
-                dialect_op_name: "nvvm.cp_async_mbarrier_arrive_shared",
-                source_record: "int_nvvm_cp_async_mbarrier_arrive_shared",
-                llvm_symbol: "llvm.nvvm.cp.async.mbarrier.arrive.shared",
-                llvm_argument: "shared_ptr",
-                selection: "CP_ASYNC_MBARRIER_ARRIVE_SHARED",
-                selection_asm: "cp.async.mbarrier.arrive.shared.b64 \t[$addr];",
-                modifiers: &["async", "mbarrier", "arrive", "shared", "b64"],
-                summary: "Associates this thread's prior asynchronous copies with a shared-address barrier using balanced pending-count accounting.",
-            }
-        }
-    }
-}
-
-fn validate_cp_async_mbarrier_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let bridge = policy
-        .cp_async_mbarrier
-        .as_ref()
-        .with_context(|| format!("{} has no closed cp.async mbarrier contract", policy.id))?;
-    let recipe = cp_async_mbarrier_recipe(bridge.operation, bridge.state_space);
-    ensure!(
-        bridge.adapter == CpAsyncMbarrierAdapter::PointerToVoid,
-        "{} cp.async mbarrier adapter changed",
-        policy.id
-    );
-    ensure!(
-        bridge.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} cannot claim unrecorded cp.async mbarrier runtime validation",
-        policy.id
-    );
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} cp.async mbarrier identity does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "async_copy"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == ["*mut u64"]
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::async_copy::{}", recipe.id)
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::async_copy::{}", recipe.id)],
-        "{} is outside the closed cp.async mbarrier Rust API",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == ["ptr"]
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == [recipe.llvm_argument]
-            && policy.llvm_results.is_empty()
-            && policy.lowering == "generated_cp_async_mbarrier",
-        "{} is outside the closed cp.async mbarrier signature and lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read_write"
-            && policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == "7.0"
-            && policy.minimum_sm.as_deref() == Some("sm_80")
-            && policy.ptx_result == "()"
-            && policy.targets == "all",
-        "{} cp.async mbarrier effects or target floor disagree with the closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "9.7.14.16.18 Parallel Synchronization and Communication Instructions: cp.async.mbarrier.arrive"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-cp-async-mbarrier-arrive",
-        "{} cp.async mbarrier PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.summary == recipe.summary,
-        "{} cp.async mbarrier summary does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.properties == ["IntrConvergent", "IntrNoCallback"],
-        "{} cp.async mbarrier properties disagree with the imported declaration",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "cp"
-            && policy
-                .expected_ptx
-                .modifiers
-                .iter()
-                .map(String::as_str)
-                .eq(recipe.modifiers.iter().copied())
-            && policy.expected_ptx.operands == [OperandPattern::Address],
-        "{} expected PTX does not match its cp.async mbarrier recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.selections.len() == 1
-            && declaration.selections[0].source_record == recipe.selection
-            && declaration.selections[0].asm == recipe.selection_asm
-            && declaration.selections[0].predicates
-                == [
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ]
-            && declaration.selections[0].constraints.is_empty(),
-        "{} imported cp.async mbarrier selection changed",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ])
-            && policy.backend_lowerings.iter().all(|lowering| {
-                lowering.minimum_ptx.is_none()
-                    && lowering.minimum_sm.is_none()
-                    && !lowering.evidence_profile.trim().is_empty()
-            }),
-        "{} must define the reviewed typed-LLVM and inline-PTX cp.async mbarrier routes",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "cp_async_mbarrier")?;
-    Ok(())
-}
-
-struct MbarrierBasicRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    rust_arguments: &'static [&'static str],
-    rust_result: &'static str,
-    must_use: bool,
-    adapter: MbarrierBasicAdapter,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    dialect_operands: &'static [&'static str],
-    dialect_results: &'static [&'static str],
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    llvm_arguments: &'static [&'static str],
-    llvm_results: &'static [&'static str],
-    memory: &'static str,
-    ptx_result: &'static str,
-    selection: &'static str,
-    selection_asm: &'static str,
-    ptx_modifier: &'static str,
-    ptx_isa_section: &'static str,
-    ptx_isa_url: &'static str,
-    llvm_nvptx_mechanism: BackendLoweringMechanism,
-    lib_nvvm_mechanism: BackendLoweringMechanism,
-    properties: &'static [&'static str],
-    summary: &'static str,
-}
-
-fn mbarrier_basic_recipe(operation: MbarrierBasicOperation) -> MbarrierBasicRecipe {
-    match operation {
-        MbarrierBasicOperation::Init => MbarrierBasicRecipe {
-            id: "mbarrier_init",
-            abi_id: "i0097",
-            operation_key: "barrier.mbarrier.init.shared.cta",
-            rust_arguments: &["*mut u64", "u32"],
-            rust_result: "()",
-            must_use: false,
-            adapter: MbarrierBasicAdapter::InitPointerCountToVoid,
-            dialect_op_type: "MbarrierInitSharedOp",
-            dialect_op_name: "nvvm.mbarrier_init_shared",
-            dialect_operands: &["ptr", "i32"],
-            dialect_results: &[],
-            source_record: "int_nvvm_mbarrier_init_shared",
-            llvm_symbol: "llvm.nvvm.mbarrier.init.shared",
-            llvm_arguments: &["shared_ptr", "i32"],
-            llvm_results: &[],
-            memory: "read_write",
-            ptx_result: "()",
-            selection: "MBARRIER_INIT_SHARED",
-            selection_asm: "mbarrier.init.shared.b64 \t[$addr], $count;",
-            ptx_modifier: "init",
-            ptx_isa_section: "9.7.14.16.12 Parallel Synchronization and Communication Instructions: mbarrier.init",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-init",
-            llvm_nvptx_mechanism: BackendLoweringMechanism::TypedNvvm,
-            lib_nvvm_mechanism: BackendLoweringMechanism::InlinePtx,
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            summary: "Initializes a CTA shared-memory barrier with the expected arrival count.",
-        },
-        MbarrierBasicOperation::Arrive => MbarrierBasicRecipe {
-            id: "mbarrier_arrive",
-            abi_id: "i0098",
-            operation_key: "barrier.mbarrier.arrive.shared.cta",
-            rust_arguments: &["*const u64"],
-            rust_result: "u64",
-            must_use: true,
-            adapter: MbarrierBasicAdapter::ArrivePointerToToken,
-            dialect_op_type: "MbarrierArriveSharedOp",
-            dialect_op_name: "nvvm.mbarrier_arrive_shared",
-            dialect_operands: &["ptr"],
-            dialect_results: &["i64"],
-            source_record: "int_nvvm_mbarrier_arrive_shared",
-            llvm_symbol: "llvm.nvvm.mbarrier.arrive.shared",
-            llvm_arguments: &["shared_ptr"],
-            llvm_results: &["i64"],
-            memory: "read_write",
-            ptx_result: "u64",
-            selection: "MBARRIER_ARRIVE_SHARED",
-            selection_asm: "mbarrier.arrive.shared.b64 \t$state, [$addr];",
-            ptx_modifier: "arrive",
-            ptx_isa_section: "9.7.14.16.16 Parallel Synchronization and Communication Instructions: mbarrier.arrive",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-arrive",
-            llvm_nvptx_mechanism: BackendLoweringMechanism::TypedNvvm,
-            lib_nvvm_mechanism: BackendLoweringMechanism::InlinePtx,
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            summary: "Arrives at a CTA shared-memory barrier and returns its phase token.",
-        },
-        MbarrierBasicOperation::TestWait => MbarrierBasicRecipe {
-            id: "mbarrier_test_wait",
-            abi_id: "i0099",
-            operation_key: "barrier.mbarrier.test_wait.shared.cta",
-            rust_arguments: &["*const u64", "u64"],
-            rust_result: "bool",
-            must_use: true,
-            adapter: MbarrierBasicAdapter::TestWaitPointerTokenToPredicate,
-            dialect_op_type: "MbarrierTestWaitSharedOp",
-            dialect_op_name: "nvvm.mbarrier_test_wait_shared",
-            dialect_operands: &["ptr", "i64"],
-            dialect_results: &["i1"],
-            source_record: "int_nvvm_mbarrier_test_wait_shared",
-            llvm_symbol: "llvm.nvvm.mbarrier.test.wait.shared",
-            llvm_arguments: &["shared_ptr", "i64"],
-            llvm_results: &["i1"],
-            memory: "read_write",
-            ptx_result: "bool",
-            selection: "MBARRIER_TEST_WAIT_SHARED",
-            selection_asm: "mbarrier.test_wait.shared.b64 \t$res, [$addr], $state;",
-            ptx_modifier: "test_wait",
-            ptx_isa_section: "9.7.14.16.19 Parallel Synchronization and Communication Instructions: mbarrier.test_wait / mbarrier.try_wait",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-mbarrier-try-wait",
-            llvm_nvptx_mechanism: BackendLoweringMechanism::InlinePtx,
-            lib_nvvm_mechanism: BackendLoweringMechanism::InlinePtx,
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            summary: "Tests whether the CTA shared-memory barrier phase for a token is complete.",
-        },
-        MbarrierBasicOperation::Inval => MbarrierBasicRecipe {
-            id: "mbarrier_inval",
-            abi_id: "i0100",
-            operation_key: "barrier.mbarrier.inval.shared.cta",
-            rust_arguments: &["*mut u64"],
-            rust_result: "()",
-            must_use: false,
-            adapter: MbarrierBasicAdapter::InvalPointerToVoid,
-            dialect_op_type: "MbarrierInvalSharedOp",
-            dialect_op_name: "nvvm.mbarrier_inval_shared",
-            dialect_operands: &["ptr"],
-            dialect_results: &[],
-            source_record: "int_nvvm_mbarrier_inval_shared",
-            llvm_symbol: "llvm.nvvm.mbarrier.inval.shared",
-            llvm_arguments: &["shared_ptr"],
-            llvm_results: &[],
-            memory: "write",
-            ptx_result: "()",
-            selection: "MBARRIER_INVAL_SHARED",
-            selection_asm: "mbarrier.inval.shared.b64 \t[$addr];",
-            ptx_modifier: "inval",
-            ptx_isa_section: "9.7.14.16.13 Parallel Synchronization and Communication Instructions: mbarrier.inval",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-inval",
-            llvm_nvptx_mechanism: BackendLoweringMechanism::TypedNvvm,
-            lib_nvvm_mechanism: BackendLoweringMechanism::InlinePtx,
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>",
-            ],
-            summary: "Invalidates a CTA shared-memory barrier after its users have finished.",
-        },
-    }
-}
-
-fn mbarrier_expected_operands(operation: MbarrierBasicOperation) -> Vec<OperandPattern> {
-    match operation {
-        MbarrierBasicOperation::Init => {
-            vec![OperandPattern::Address, OperandPattern::RegisterOrImmediate]
-        }
-        MbarrierBasicOperation::Arrive => {
-            vec![OperandPattern::Register, OperandPattern::Address]
-        }
-        MbarrierBasicOperation::TestWait => vec![
-            OperandPattern::Register,
-            OperandPattern::Address,
-            OperandPattern::Register,
-        ],
-        MbarrierBasicOperation::Inval => vec![OperandPattern::Address],
-    }
-}
-
-fn validate_mbarrier_basic_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let mbarrier = policy
-        .mbarrier_basic
-        .as_ref()
-        .with_context(|| format!("{} has no closed basic mbarrier contract", policy.id))?;
-    let recipe = mbarrier_basic_recipe(mbarrier.operation);
-    ensure!(
-        mbarrier.state_space == MbarrierStateSpace::Shared && mbarrier.adapter == recipe.adapter,
-        "{} mbarrier operation, state space, and adapter disagree",
-        policy.id
-    );
-    ensure!(
-        mbarrier.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} cannot claim unrecorded mbarrier runtime validation",
-        policy.id
-    );
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} mbarrier identity does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "barrier"
-            && policy.rust_name == recipe.id
-            && policy
-                .rust_arguments
-                .iter()
-                .map(String::as_str)
-                .eq(recipe.rust_arguments.iter().copied())
-            && policy.rust_result == recipe.rust_result
-            && !policy.safe
-            && policy.must_use == recipe.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::barrier::{}", recipe.id)
-            && policy.compatibility_rust_paths == [format!("cuda_device::barrier::{}", recipe.id)],
-        "{} must preserve its unsafe mbarrier raw and compatibility API",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy
-                .dialect_operands
-                .iter()
-                .map(String::as_str)
-                .eq(recipe.dialect_operands.iter().copied())
-            && policy
-                .dialect_results
-                .iter()
-                .map(String::as_str)
-                .eq(recipe.dialect_results.iter().copied())
-            && policy
-                .llvm_arguments
-                .iter()
-                .map(String::as_str)
-                .eq(recipe.llvm_arguments.iter().copied())
-            && policy
-                .llvm_results
-                .iter()
-                .map(String::as_str)
-                .eq(recipe.llvm_results.iter().copied())
-            && policy.lowering == "generated_mbarrier_basic",
-        "{} is outside the closed mbarrier signature and lowering recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == recipe.memory
-            && policy.convergent
-            && policy.execution_scope == "cta"
-            && policy.minimum_ptx == "7.0"
-            && policy.minimum_sm.as_deref() == Some("sm_80")
-            && policy.ptx_result == recipe.ptx_result
-            && policy.targets == "all",
-        "{} mbarrier effects or target floor disagree with the closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.ptx_isa_section
-            && policy.ptx_isa_url == recipe.ptx_isa_url,
-        "{} mbarrier PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.summary == recipe.summary,
-        "{} mbarrier summary does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration
-            .properties
-            .iter()
-            .map(String::as_str)
-            .eq(recipe.properties.iter().copied()),
-        "{} mbarrier properties disagree with the imported LLVM declaration",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "mbarrier"
-            && policy.expected_ptx.modifiers == [recipe.ptx_modifier, "shared", "b64"]
-            && policy.expected_ptx.operands == mbarrier_expected_operands(mbarrier.operation),
-        "{} expected PTX does not match its mbarrier recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.selections.len() == 1
-            && declaration.selections[0].source_record == recipe.selection
-            && declaration.selections[0].asm == recipe.selection_asm
-            && declaration.selections[0].predicates
-                == [
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ]
-            && declaration.selections[0].constraints.is_empty(),
-        "{} imported mbarrier selection changed",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (IntrinsicBackend::LlvmNvptx, recipe.llvm_nvptx_mechanism),
-                    (IntrinsicBackend::LibNvvm, recipe.lib_nvvm_mechanism),
-                ])
-            && policy.backend_lowerings.iter().all(|lowering| {
-                lowering.minimum_ptx.is_none()
-                    && lowering.minimum_sm.is_none()
-                    && !lowering.evidence_profile.trim().is_empty()
-            }),
-        "{} must define exactly the reviewed mbarrier backend routes",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "mbarrier_basic")?;
-    Ok(())
-}
-
-fn packed_conversion_recipe(
-    conversion: &crate::model::PackedConversion,
-) -> Option<PackedConversionRecipe> {
-    match conversion.source_format {
-        PackedConversionSourceFormat::F32x2 => packed_conversion_recipe_f32x2(conversion),
-        PackedConversionSourceFormat::E4m3x2
-        | PackedConversionSourceFormat::E5m2x2
-        | PackedConversionSourceFormat::F16x2 => packed_conversion_recipe_fp8_f16x2(conversion),
-    }
-}
-
-/// Recipes for the packed FP8 conversions whose other side is `f16x2`.
-///
-/// Keyed on source as well as destination: unpacking to `f16x2` shares its
-/// destination, rounding, and saturation with the scalar-`f32` recipe for
-/// `cvt.rn.f16x2.f32`, so the source format is what separates them.
-fn packed_conversion_recipe_fp8_f16x2(
-    conversion: &crate::model::PackedConversion,
-) -> Option<PackedConversionRecipe> {
-    match (
-        conversion.source_format,
-        conversion.destination_format,
-        conversion.rounding,
-        conversion.saturation,
-    ) {
-        (
-            PackedConversionSourceFormat::F16x2,
-            PackedConversionDestinationFormat::E4m3x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::Satfinite,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_satfinite_e4m3x2_f16x2",
-            abi_id: "i0822",
-            operation_key: "packed.convert.f16x2.e4m3x2.nearest_even.satfinite",
-            rust_name: "cvt_rn_satfinite_e4m3x2_f16x2",
-            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2",
-            dialect_op_type: "CvtRnSatfiniteE4m3x2F16x2Op",
-            dialect_op_name: "nvvm.cvt_rn_satfinite_e4m3x2_f16x2",
-            source_record: "int_nvvm_f16x2_to_e4m3x2_rn",
-            llvm_symbol: "llvm.nvvm.f16x2.to.e4m3x2.rn",
-            llvm_result: "i16",
-            summary: "Converts packed f16x2 to packed e4m3x2 with nearest-even finite saturation, preserving half order.",
-        }),
-        (
-            PackedConversionSourceFormat::F16x2,
-            PackedConversionDestinationFormat::E4m3x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::SatfiniteRelu,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_satfinite_relu_e4m3x2_f16x2",
-            abi_id: "i0823",
-            operation_key: "packed.convert.f16x2.e4m3x2.nearest_even.satfinite.relu",
-            rust_name: "cvt_rn_satfinite_relu_e4m3x2_f16x2",
-            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2",
-            dialect_op_type: "CvtRnSatfiniteReluE4m3x2F16x2Op",
-            dialect_op_name: "nvvm.cvt_rn_satfinite_relu_e4m3x2_f16x2",
-            source_record: "int_nvvm_f16x2_to_e4m3x2_rn_relu",
-            llvm_symbol: "llvm.nvvm.f16x2.to.e4m3x2.rn.relu",
-            llvm_result: "i16",
-            summary: "Converts packed f16x2 to packed e4m3x2 with nearest-even finite saturation and ReLU, preserving half order.",
-        }),
-        (
-            PackedConversionSourceFormat::F16x2,
-            PackedConversionDestinationFormat::E5m2x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::Satfinite,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_satfinite_e5m2x2_f16x2",
-            abi_id: "i0824",
-            operation_key: "packed.convert.f16x2.e5m2x2.nearest_even.satfinite",
-            rust_name: "cvt_rn_satfinite_e5m2x2_f16x2",
-            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2",
-            dialect_op_type: "CvtRnSatfiniteE5m2x2F16x2Op",
-            dialect_op_name: "nvvm.cvt_rn_satfinite_e5m2x2_f16x2",
-            source_record: "int_nvvm_f16x2_to_e5m2x2_rn",
-            llvm_symbol: "llvm.nvvm.f16x2.to.e5m2x2.rn",
-            llvm_result: "i16",
-            summary: "Converts packed f16x2 to packed e5m2x2 with nearest-even finite saturation, preserving half order.",
-        }),
-        (
-            PackedConversionSourceFormat::F16x2,
-            PackedConversionDestinationFormat::E5m2x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::SatfiniteRelu,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_satfinite_relu_e5m2x2_f16x2",
-            abi_id: "i0825",
-            operation_key: "packed.convert.f16x2.e5m2x2.nearest_even.satfinite.relu",
-            rust_name: "cvt_rn_satfinite_relu_e5m2x2_f16x2",
-            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2",
-            dialect_op_type: "CvtRnSatfiniteReluE5m2x2F16x2Op",
-            dialect_op_name: "nvvm.cvt_rn_satfinite_relu_e5m2x2_f16x2",
-            source_record: "int_nvvm_f16x2_to_e5m2x2_rn_relu",
-            llvm_symbol: "llvm.nvvm.f16x2.to.e5m2x2.rn.relu",
-            llvm_result: "i16",
-            summary: "Converts packed f16x2 to packed e5m2x2 with nearest-even finite saturation and ReLU, preserving half order.",
-        }),
-        (
-            PackedConversionSourceFormat::E4m3x2,
-            PackedConversionDestinationFormat::F16x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::None,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_f16x2_e4m3x2",
-            abi_id: "i0826",
-            operation_key: "packed.convert.e4m3x2.f16x2.nearest_even",
-            rust_name: "cvt_rn_f16x2_e4m3x2",
-            compatibility_path: "cuda_device::convert::cvt_rn_f16x2_e4m3x2",
-            dialect_op_type: "CvtRnF16x2E4m3x2Op",
-            dialect_op_name: "nvvm.cvt_rn_f16x2_e4m3x2",
-            source_record: "int_nvvm_e4m3x2_to_f16x2_rn",
-            llvm_symbol: "llvm.nvvm.e4m3x2.to.f16x2.rn",
-            llvm_result: "v2f16",
-            summary: "Converts packed e4m3x2 to packed f16x2, preserving byte order.",
-        }),
-        (
-            PackedConversionSourceFormat::E4m3x2,
-            PackedConversionDestinationFormat::F16x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::Relu,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_relu_f16x2_e4m3x2",
-            abi_id: "i0827",
-            operation_key: "packed.convert.e4m3x2.f16x2.nearest_even.relu",
-            rust_name: "cvt_rn_relu_f16x2_e4m3x2",
-            compatibility_path: "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2",
-            dialect_op_type: "CvtRnReluF16x2E4m3x2Op",
-            dialect_op_name: "nvvm.cvt_rn_relu_f16x2_e4m3x2",
-            source_record: "int_nvvm_e4m3x2_to_f16x2_rn_relu",
-            llvm_symbol: "llvm.nvvm.e4m3x2.to.f16x2.rn.relu",
-            llvm_result: "v2f16",
-            summary: "Converts packed e4m3x2 to packed f16x2 with ReLU, preserving byte order.",
-        }),
-        (
-            PackedConversionSourceFormat::E5m2x2,
-            PackedConversionDestinationFormat::F16x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::None,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_f16x2_e5m2x2",
-            abi_id: "i0828",
-            operation_key: "packed.convert.e5m2x2.f16x2.nearest_even",
-            rust_name: "cvt_rn_f16x2_e5m2x2",
-            compatibility_path: "cuda_device::convert::cvt_rn_f16x2_e5m2x2",
-            dialect_op_type: "CvtRnF16x2E5m2x2Op",
-            dialect_op_name: "nvvm.cvt_rn_f16x2_e5m2x2",
-            source_record: "int_nvvm_e5m2x2_to_f16x2_rn",
-            llvm_symbol: "llvm.nvvm.e5m2x2.to.f16x2.rn",
-            llvm_result: "v2f16",
-            summary: "Converts packed e5m2x2 to packed f16x2, preserving byte order.",
-        }),
-        (
-            PackedConversionSourceFormat::E5m2x2,
-            PackedConversionDestinationFormat::F16x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::Relu,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_relu_f16x2_e5m2x2",
-            abi_id: "i0829",
-            operation_key: "packed.convert.e5m2x2.f16x2.nearest_even.relu",
-            rust_name: "cvt_rn_relu_f16x2_e5m2x2",
-            compatibility_path: "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2",
-            dialect_op_type: "CvtRnReluF16x2E5m2x2Op",
-            dialect_op_name: "nvvm.cvt_rn_relu_f16x2_e5m2x2",
-            source_record: "int_nvvm_e5m2x2_to_f16x2_rn_relu",
-            llvm_symbol: "llvm.nvvm.e5m2x2.to.f16x2.rn.relu",
-            llvm_result: "v2f16",
-            summary: "Converts packed e5m2x2 to packed f16x2 with ReLU, preserving byte order.",
-        }),
-        _ => None,
-    }
-}
-
-fn packed_conversion_recipe_f32x2(
-    conversion: &crate::model::PackedConversion,
-) -> Option<PackedConversionRecipe> {
-    match (
-        conversion.destination_format,
-        conversion.rounding,
-        conversion.saturation,
-    ) {
-        (
-            PackedConversionDestinationFormat::Bf16x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::None,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_f32x2_bf16x2",
-            abi_id: "i0071",
-            operation_key: "packed.convert.f32x2.bf16x2.nearest_even",
-            rust_name: "cvt_f32x2_bf16x2",
-            compatibility_path: "cuda_device::convert::cvt_bf16x2_f32",
-            dialect_op_type: "CvtF32x2Bf16x2Op",
-            dialect_op_name: "nvvm.cvt_f32x2_bf16x2",
-            source_record: "int_nvvm_ff2bf16x2_rn",
-            llvm_symbol: "llvm.nvvm.ff2bf16x2.rn",
-            llvm_result: "v2bf16",
-            summary: "Converts two f32 values to packed bf16x2 with the first argument in the low half.",
-        }),
-        (
-            PackedConversionDestinationFormat::F16x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::None,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_f16x2_f32",
-            abi_id: "i0081",
-            operation_key: "packed.convert.f32x2.f16x2.nearest_even",
-            rust_name: "cvt_f16x2_f32",
-            compatibility_path: "cuda_device::convert::cvt_f16x2_f32",
-            dialect_op_type: "CvtF16x2F32Op",
-            dialect_op_name: "nvvm.cvt_f16x2_f32",
-            source_record: "int_nvvm_ff2f16x2_rn",
-            llvm_symbol: "llvm.nvvm.ff2f16x2.rn",
-            llvm_result: "v2f16",
-            summary: "Converts two f32 values to packed f16x2 with nearest-even rounding and the first argument in the low half.",
-        }),
-        (
-            PackedConversionDestinationFormat::F16x2,
-            PackedConversionRounding::TowardZero,
-            PackedConversionSaturation::None,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rz_f16x2_f32",
-            abi_id: "i0082",
-            operation_key: "packed.convert.f32x2.f16x2.toward_zero",
-            rust_name: "cvt_rz_f16x2_f32",
-            compatibility_path: "cuda_device::convert::cvt_rz_f16x2_f32",
-            dialect_op_type: "CvtRzF16x2F32Op",
-            dialect_op_name: "nvvm.cvt_rz_f16x2_f32",
-            source_record: "int_nvvm_ff2f16x2_rz",
-            llvm_symbol: "llvm.nvvm.ff2f16x2.rz",
-            llvm_result: "v2f16",
-            summary: "Converts two f32 values to packed f16x2 with toward-zero rounding and the first argument in the low half.",
-        }),
-        (
-            PackedConversionDestinationFormat::F16x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::Relu,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_relu_f16x2_f32",
-            abi_id: "i0083",
-            operation_key: "packed.convert.f32x2.f16x2.nearest_even.relu",
-            rust_name: "cvt_rn_relu_f16x2_f32",
-            compatibility_path: "cuda_device::convert::cvt_rn_relu_f16x2_f32",
-            dialect_op_type: "CvtRnReluF16x2F32Op",
-            dialect_op_name: "nvvm.cvt_rn_relu_f16x2_f32",
-            source_record: "int_nvvm_ff2f16x2_rn_relu",
-            llvm_symbol: "llvm.nvvm.ff2f16x2.rn.relu",
-            llvm_result: "v2f16",
-            summary: "Converts two f32 values to packed f16x2 with nearest-even rounding, ReLU, and the first argument in the low half.",
-        }),
-        (
-            PackedConversionDestinationFormat::Bf16x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::Relu,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_relu_bf16x2_f32",
-            abi_id: "i0084",
-            operation_key: "packed.convert.f32x2.bf16x2.nearest_even.relu",
-            rust_name: "cvt_rn_relu_bf16x2_f32",
-            compatibility_path: "cuda_device::convert::cvt_rn_relu_bf16x2_f32",
-            dialect_op_type: "CvtRnReluBf16x2F32Op",
-            dialect_op_name: "nvvm.cvt_rn_relu_bf16x2_f32",
-            source_record: "int_nvvm_ff2bf16x2_rn_relu",
-            llvm_symbol: "llvm.nvvm.ff2bf16x2.rn.relu",
-            llvm_result: "v2bf16",
-            summary: "Converts two f32 values to packed bf16x2 with nearest-even rounding, ReLU, and the first argument in the low half.",
-        }),
-        (
-            PackedConversionDestinationFormat::Bf16x2,
-            PackedConversionRounding::TowardZero,
-            PackedConversionSaturation::None,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rz_bf16x2_f32",
-            abi_id: "i0085",
-            operation_key: "packed.convert.f32x2.bf16x2.toward_zero",
-            rust_name: "cvt_rz_bf16x2_f32",
-            compatibility_path: "cuda_device::convert::cvt_rz_bf16x2_f32",
-            dialect_op_type: "CvtRzBf16x2F32Op",
-            dialect_op_name: "nvvm.cvt_rz_bf16x2_f32",
-            source_record: "int_nvvm_ff2bf16x2_rz",
-            llvm_symbol: "llvm.nvvm.ff2bf16x2.rz",
-            llvm_result: "v2bf16",
-            summary: "Converts two f32 values to packed bf16x2 with toward-zero rounding and the first argument in the low half.",
-        }),
-        (
-            PackedConversionDestinationFormat::E4m3x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::Satfinite,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_satfinite_e4m3x2_f32",
-            abi_id: "i0259",
-            operation_key: "packed.convert.f32x2.e4m3x2.nearest_even.satfinite",
-            rust_name: "cvt_rn_satfinite_e4m3x2_f32",
-            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32",
-            dialect_op_type: "CvtRnSatfiniteE4m3x2F32Op",
-            dialect_op_name: "nvvm.cvt_rn_satfinite_e4m3x2_f32",
-            source_record: "int_nvvm_ff_to_e4m3x2_rn",
-            llvm_symbol: "llvm.nvvm.ff.to.e4m3x2.rn",
-            llvm_result: "i16",
-            summary: "Converts two f32 values to packed e4m3x2 with nearest-even finite saturation and the first argument in the low byte.",
-        }),
-        (
-            PackedConversionDestinationFormat::E4m3x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::SatfiniteRelu,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_satfinite_relu_e4m3x2_f32",
-            abi_id: "i0260",
-            operation_key: "packed.convert.f32x2.e4m3x2.nearest_even.satfinite.relu",
-            rust_name: "cvt_rn_satfinite_relu_e4m3x2_f32",
-            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32",
-            dialect_op_type: "CvtRnSatfiniteReluE4m3x2F32Op",
-            dialect_op_name: "nvvm.cvt_rn_satfinite_relu_e4m3x2_f32",
-            source_record: "int_nvvm_ff_to_e4m3x2_rn_relu",
-            llvm_symbol: "llvm.nvvm.ff.to.e4m3x2.rn.relu",
-            llvm_result: "i16",
-            summary: "Converts two f32 values to packed e4m3x2 with nearest-even finite saturation, ReLU, and the first argument in the low byte.",
-        }),
-        (
-            PackedConversionDestinationFormat::E5m2x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::Satfinite,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_satfinite_e5m2x2_f32",
-            abi_id: "i0261",
-            operation_key: "packed.convert.f32x2.e5m2x2.nearest_even.satfinite",
-            rust_name: "cvt_rn_satfinite_e5m2x2_f32",
-            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32",
-            dialect_op_type: "CvtRnSatfiniteE5m2x2F32Op",
-            dialect_op_name: "nvvm.cvt_rn_satfinite_e5m2x2_f32",
-            source_record: "int_nvvm_ff_to_e5m2x2_rn",
-            llvm_symbol: "llvm.nvvm.ff.to.e5m2x2.rn",
-            llvm_result: "i16",
-            summary: "Converts two f32 values to packed e5m2x2 with nearest-even finite saturation and the first argument in the low byte.",
-        }),
-        (
-            PackedConversionDestinationFormat::E5m2x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::SatfiniteRelu,
-        ) => Some(PackedConversionRecipe {
-            id: "cvt_rn_satfinite_relu_e5m2x2_f32",
-            abi_id: "i0262",
-            operation_key: "packed.convert.f32x2.e5m2x2.nearest_even.satfinite.relu",
-            rust_name: "cvt_rn_satfinite_relu_e5m2x2_f32",
-            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32",
-            dialect_op_type: "CvtRnSatfiniteReluE5m2x2F32Op",
-            dialect_op_name: "nvvm.cvt_rn_satfinite_relu_e5m2x2_f32",
-            source_record: "int_nvvm_ff_to_e5m2x2_rn_relu",
-            llvm_symbol: "llvm.nvvm.ff.to.e5m2x2.rn.relu",
-            llvm_result: "i16",
-            summary: "Converts two f32 values to packed e5m2x2 with nearest-even finite saturation, ReLU, and the first argument in the low byte.",
-        }),
-        _ => None,
-    }
-}
-
-fn packed_conversion_ptx_modifiers(
-    conversion: &crate::model::PackedConversion,
-) -> Vec<&'static str> {
-    let rounding = match conversion.rounding {
-        PackedConversionRounding::NearestEven => "rn",
-        PackedConversionRounding::TowardZero => "rz",
-    };
-    let format = match conversion.destination_format {
-        PackedConversionDestinationFormat::Bf16x2 => "bf16x2",
-        PackedConversionDestinationFormat::E4m3x2 => "e4m3x2",
-        PackedConversionDestinationFormat::E5m2x2 => "e5m2x2",
-        PackedConversionDestinationFormat::F16x2 => "f16x2",
-    };
-    let mut modifiers = vec![rounding];
-    match conversion.saturation {
-        PackedConversionSaturation::None => {}
-        PackedConversionSaturation::Relu => modifiers.push("relu"),
-        PackedConversionSaturation::Satfinite => modifiers.push("satfinite"),
-        PackedConversionSaturation::SatfiniteRelu => modifiers.extend(["satfinite", "relu"]),
-    }
-    modifiers.extend([format, conversion.source_format.ptx_token()]);
-    modifiers
-}
-
-/// Whether either side of the conversion is a packed FP8 format.
-fn packed_conversion_uses_fp8(conversion: &crate::model::PackedConversion) -> bool {
-    matches!(
-        conversion.source_format,
-        PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2
-    ) || matches!(
-        conversion.destination_format,
-        PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2
-    )
-}
-
-/// Source operand types, in Rust, dialect, and LLVM spellings.
-///
-/// A packed source arrives in one register; `f32x2` names two scalar operands.
-fn packed_conversion_source_types(
-    conversion: &crate::model::PackedConversion,
-) -> (Vec<String>, Vec<String>, Vec<String>) {
-    match conversion.source_format {
-        PackedConversionSourceFormat::F32x2 => (
-            vec!["f32".into(), "f32".into()],
-            vec!["f32".into(), "f32".into()],
-            vec!["f32".into(), "f32".into()],
-        ),
-        PackedConversionSourceFormat::F16x2 => {
-            (vec!["u32".into()], vec!["i32".into()], vec!["v2f16".into()])
-        }
-        PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2 => {
-            (vec!["u16".into()], vec!["i16".into()], vec!["i16".into()])
-        }
-    }
-}
-
-fn packed_conversion_result_width(conversion: &crate::model::PackedConversion) -> u32 {
-    match conversion.destination_format {
-        PackedConversionDestinationFormat::Bf16x2 | PackedConversionDestinationFormat::F16x2 => 32,
-        PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2 => 16,
-    }
-}
-
-fn packed_conversion_floor(
-    conversion: &crate::model::PackedConversion,
-) -> (&'static str, &'static str) {
-    // FP8 on either side carries the Ada floor, including when FP8 is the
-    // source and the destination is the older `f16x2`.
-    if packed_conversion_uses_fp8(conversion) {
-        return ("8.1", "sm_89");
-    }
-    match conversion.destination_format {
-        PackedConversionDestinationFormat::Bf16x2 | PackedConversionDestinationFormat::F16x2 => {
-            ("7.0", "sm_80")
-        }
-        PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2 => {
-            ("8.1", "sm_89")
-        }
-    }
-}
-
-fn packed_conversion_backend_mechanism(
-    conversion: &crate::model::PackedConversion,
-    backend: IntrinsicBackend,
-) -> BackendLoweringMechanism {
-    match (packed_conversion_uses_typed_nvvm(conversion), backend) {
-        (true, IntrinsicBackend::LlvmNvptx) => BackendLoweringMechanism::TypedNvvm,
-        _ => BackendLoweringMechanism::InlinePtx,
-    }
-}
-
-/// Whether the conversion lowers through a typed NVVM intrinsic call.
-///
-/// Only the scalar-`f32` pair does. The `f16x2` sources and destinations carry
-/// their halves in one integer register on the MIR side, while the typed
-/// intrinsics are declared over `<2 x half>`; routing them through inline PTX
-/// avoids a packed-half MIR type for no change in emitted code. The recorded
-/// evidence assembles both routes to a byte-identical cubin, so the typed route
-/// can be switched on later without changing the PTX contract.
-fn packed_conversion_uses_typed_nvvm(conversion: &crate::model::PackedConversion) -> bool {
-    conversion.source_format == PackedConversionSourceFormat::F32x2
-        && matches!(
-            conversion.destination_format,
-            PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2
-        )
-}
-
-fn packed_conversion_lowering(conversion: &crate::model::PackedConversion) -> &'static str {
-    if packed_conversion_uses_typed_nvvm(conversion) {
-        "generated_packed_conversion_backend"
-    } else {
-        "generated_packed_conversion_inline_ptx"
-    }
-}
-
-fn expand_packed_conversion_fp8_admission(
-    admission: &PackedConversionFp8Admission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "FP8 conversion runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        admission.destination_formats
-            == [
-                PackedConversionDestinationFormat::E4m3x2,
-                PackedConversionDestinationFormat::E5m2x2,
-            ],
-        "compact FP8 conversion admission must list the canonical two formats"
-    );
-    ensure!(
-        admission.saturations
-            == [
-                PackedConversionSaturation::Satfinite,
-                PackedConversionSaturation::SatfiniteRelu,
-            ],
-        "compact FP8 conversion admission must list base and ReLU finite saturation"
-    );
-    ensure!(
-        admission.product_count
-            == admission
-                .destination_formats
-                .len()
-                .checked_mul(admission.saturations.len())
-                .context("compact FP8 conversion product count overflow")?
-            && admission.product_count == 4,
-        "compact FP8 conversion product_count must be exactly 4"
-    );
-
-    let mut records = Vec::with_capacity(admission.product_count);
-    for &destination_format in &admission.destination_formats {
-        for &saturation in &admission.saturations {
-            let conversion = crate::model::PackedConversion {
-                source_format: PackedConversionSourceFormat::F32x2,
-                destination_format,
-                rounding: PackedConversionRounding::NearestEven,
-                saturation,
-                adapter: PackedConversionAdapter::ReverseHighLowOperands,
-            };
-            records.push(packed_conversion_overlay_record(
-                conversion,
-                &admission.llvm_evidence_profile,
-                &admission.libnvvm_evidence_profile,
-            )?);
-        }
-    }
-    ensure!(records.len() == admission.product_count);
-    Ok(records)
-}
-
-fn expand_packed_conversion_fp8_f16x2_admission(
-    admission: &PackedConversionFp8F16x2Admission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "FP8 f16x2 conversion runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        admission.fp8_formats
-            == [
-                PackedConversionFp8Format::E4m3x2,
-                PackedConversionFp8Format::E5m2x2,
-            ],
-        "compact FP8 f16x2 conversion admission must list the canonical two formats"
-    );
-    ensure!(
-        admission.directions
-            == [
-                PackedConversionFp8Direction::Pack,
-                PackedConversionFp8Direction::Unpack,
-            ],
-        "compact FP8 f16x2 conversion admission must list both conversion directions"
-    );
-    ensure!(
-        admission.relu_variants,
-        "compact FP8 f16x2 conversion admission must admit the ReLU variants"
-    );
-    ensure!(
-        admission.product_count
-            == admission
-                .fp8_formats
-                .len()
-                .checked_mul(admission.directions.len())
-                .and_then(|count| count.checked_mul(2))
-                .context("compact FP8 f16x2 conversion product count overflow")?
-            && admission.product_count == 8,
-        "compact FP8 f16x2 conversion product_count must be exactly 8"
-    );
-
-    let mut records = Vec::with_capacity(admission.product_count);
-    for &fp8_format in &admission.fp8_formats {
-        for &direction in &admission.directions {
-            for relu in [false, true] {
-                let conversion = match direction {
-                    // Narrowing to FP8 always saturates to finite.
-                    PackedConversionFp8Direction::Pack => crate::model::PackedConversion {
-                        source_format: PackedConversionSourceFormat::F16x2,
-                        destination_format: match fp8_format {
-                            PackedConversionFp8Format::E4m3x2 => {
-                                PackedConversionDestinationFormat::E4m3x2
-                            }
-                            PackedConversionFp8Format::E5m2x2 => {
-                                PackedConversionDestinationFormat::E5m2x2
-                            }
-                        },
-                        rounding: PackedConversionRounding::NearestEven,
-                        saturation: if relu {
-                            PackedConversionSaturation::SatfiniteRelu
-                        } else {
-                            PackedConversionSaturation::Satfinite
-                        },
-                        adapter: PackedConversionAdapter::Identity,
-                    },
-                    // Widening back to f16x2 is exact, so it carries no
-                    // saturation modifier of its own.
-                    PackedConversionFp8Direction::Unpack => crate::model::PackedConversion {
-                        source_format: match fp8_format {
-                            PackedConversionFp8Format::E4m3x2 => {
-                                PackedConversionSourceFormat::E4m3x2
-                            }
-                            PackedConversionFp8Format::E5m2x2 => {
-                                PackedConversionSourceFormat::E5m2x2
-                            }
-                        },
-                        destination_format: PackedConversionDestinationFormat::F16x2,
-                        rounding: PackedConversionRounding::NearestEven,
-                        saturation: if relu {
-                            PackedConversionSaturation::Relu
-                        } else {
-                            PackedConversionSaturation::None
-                        },
-                        adapter: PackedConversionAdapter::Identity,
-                    },
-                };
-                records.push(packed_conversion_overlay_record(
-                    conversion,
-                    &admission.llvm_evidence_profile,
-                    &admission.libnvvm_evidence_profile,
-                )?);
-            }
-        }
-    }
-    ensure!(records.len() == admission.product_count);
-    Ok(records)
-}
-
-fn packed_conversion_overlay_record(
-    conversion: crate::model::PackedConversion,
-    llvm_evidence_profile: &str,
-    libnvvm_evidence_profile: &str,
-) -> Result<OverlayIntrinsic> {
-    let recipe = packed_conversion_recipe(&conversion)
-        .context("compact FP8 conversion is outside the closed recipe set")?;
-    let result_width = packed_conversion_result_width(&conversion);
-    let rust_result = format!("u{result_width}");
-    let dialect_result = format!("i{result_width}");
-    let (minimum_ptx, minimum_sm) = packed_conversion_floor(&conversion);
-    let (rust_arguments, dialect_operands, llvm_arguments) =
-        packed_conversion_source_types(&conversion);
-    // `cvt` writes one destination and reads every source operand.
-    let ptx_operands = conversion
-        .source_format
-        .operand_count()
-        .checked_add(1)
-        .context("packed-conversion operand count overflow")?;
-    Ok(OverlayIntrinsic {
-        id: recipe.id.into(),
-        abi_id: String::new(),
-        operation_key: recipe.operation_key.into(),
-        family: "packed_conversion".into(),
-        source: None,
-        source_record: Some(recipe.source_record.into()),
-        rust_module: "convert".into(),
-        rust_name: recipe.rust_name.into(),
-        rust_arguments,
-        rust_result: rust_result.clone(),
-        safe: true,
-        must_use: false,
-        safe_allowlist_reason: Some("This conversion has no caller obligations.".into()),
-        public_rust_path: format!("cuda_intrinsics::convert::{}", recipe.rust_name),
-        compatibility_rust_paths: vec![recipe.compatibility_path.into()],
-        dialect_op_type: recipe.dialect_op_type.into(),
-        dialect_op_name: recipe.dialect_op_name.into(),
-        dialect_operands,
-        dialect_results: vec![dialect_result],
-        llvm_symbol: Some(recipe.llvm_symbol.into()),
-        resolved_llvm_symbol: None,
-        llvm_arguments,
-        llvm_results: vec![recipe.llvm_result.into()],
-        pure: true,
-        memory: "none".into(),
-        convergent: false,
-        execution_scope: "thread".into(),
-        minimum_ptx: minimum_ptx.into(),
-        minimum_sm: Some(minimum_sm.into()),
-        ptx_result: rust_result,
-        targets: "all".into(),
-        ptx_isa_version: "9.3".into(),
-        ptx_isa_section: "9.7.9.22 Data Movement and Conversion Instructions: cvt".into(),
-        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt".into(),
-        lowering: packed_conversion_lowering(&conversion).into(),
-        backend_lowerings: [
-            (IntrinsicBackend::LlvmNvptx, llvm_evidence_profile),
-            (IntrinsicBackend::LibNvvm, libnvvm_evidence_profile),
-        ]
-        .into_iter()
-        .map(|(backend, evidence_profile)| OverlayBackendLowering {
-            backend,
-            mechanism: packed_conversion_backend_mechanism(&conversion, backend),
-            evidence_profile: evidence_profile.into(),
-            targets: None,
-            minimum_ptx: Some(minimum_ptx.into()),
-            minimum_sm: Some(minimum_sm.into()),
-        })
-        .collect(),
-        packed_atomic: None,
-        redux: None,
-        vote: None,
-        active_mask: None,
-        warp_match: None,
-        warp_barrier: None,
-        warp_shuffle: None,
-        dot_product: None,
-        packed_alu: None,
-        integer_minmax: None,
-        packed_conversion: Some(conversion.clone()),
-        scalar_conversion: None,
-        scalar_arithmetic: None,
-        scalar_math: None,
-        extended_minmax: None,
-        cp_async_copy: None,
-        cp_async_control: None,
-        cp_async_mbarrier: None,
-        mbarrier_basic: None,
-        movmatrix: None,
-        mbarrier_extended: None,
-        register_mma: None,
-        sparse_mma: None,
-        prmt: None,
-        cluster_barrier: None,
-        wgmma_control: None,
-        special_register: None,
-        debug_control: None,
-        cluster_memory: None,
-        clc: None,
-        tma: None,
-        tcgen05: None,
-        ldmatrix_variant: None,
-        ldmatrix_safety: None,
-        ldmatrix_adapter: None,
-        selected_address_space: None,
-        expected_ptx: InstructionPattern {
-            mnemonic: "cvt".into(),
-            modifiers: packed_conversion_ptx_modifiers(&conversion)
-                .into_iter()
-                .map(str::to_owned)
-                .collect(),
-            operands: vec![OperandPattern::Register; ptx_operands],
-        },
-        summary: recipe.summary.into(),
-    })
-}
-
-fn validate_packed_conversion_policy(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-    declaration: Option<&ImportedIntrinsic>,
-) -> Result<()> {
-    let conversion = policy
-        .packed_conversion
-        .as_ref()
-        .with_context(|| format!("{} has no closed packed-conversion contract", policy.id))?;
-    // The adapter is a function of the source arity: two scalar operands are
-    // reversed so the first Rust argument lands in the low half, while a single
-    // packed operand is forwarded unchanged.
-    let expected_adapter = match conversion.source_format {
-        PackedConversionSourceFormat::F32x2 => PackedConversionAdapter::ReverseHighLowOperands,
-        PackedConversionSourceFormat::E4m3x2
-        | PackedConversionSourceFormat::E5m2x2
-        | PackedConversionSourceFormat::F16x2 => PackedConversionAdapter::Identity,
-    };
-    ensure!(
-        conversion.adapter == expected_adapter,
-        "{} requests an unsupported packed-conversion source or adapter",
-        policy.id
-    );
-    let recipe = packed_conversion_recipe(conversion).with_context(|| {
-        format!(
-            "{} requests an unsupported packed-conversion source, destination, rounding, or saturation combination",
-            policy.id
-        )
-    })?;
-    let result_width = packed_conversion_result_width(conversion);
-    let rust_result = format!("u{result_width}");
-    let dialect_result = format!("i{result_width}");
-    let (minimum_ptx, minimum_sm) = packed_conversion_floor(conversion);
-    let (expected_rust_arguments, expected_dialect_operands, expected_llvm_arguments) =
-        packed_conversion_source_types(conversion);
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && source
-                == &IntrinsicSource::LlvmImported {
-                    source_record: recipe.source_record.into(),
-                }
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none()
-            && policy.llvm_arguments == expected_llvm_arguments
-            && policy.llvm_results == [recipe.llvm_result],
-        "{} packed-conversion identity or LLVM source changed",
-        policy.id
-    );
-    let declaration = declaration.context("packed conversion has no imported declaration")?;
-    ensure!(
-        declaration.properties == ["IntrNoMem", "IntrSpeculatable"]
-            && declaration.selections.is_empty(),
-        "{} selectionless packed-conversion declaration changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "convert"
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == expected_rust_arguments
-            && policy.rust_result == rust_result
-            && policy.safe
-            && !policy.must_use
-            && policy
-                .safe_allowlist_reason
-                .as_deref()
-                .is_some_and(|reason| !reason.trim().is_empty())
-            && policy.public_rust_path == format!("cuda_intrinsics::convert::{}", recipe.rust_name)
-            && policy.compatibility_rust_paths == [recipe.compatibility_path],
-        "{} must preserve its safe non-must-use conversion API",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == expected_dialect_operands
-            && policy.dialect_results == [dialect_result.as_str()]
-            && policy.lowering == packed_conversion_lowering(conversion),
-        "{} is outside the closed packed-conversion dialect and lowering recipe",
-        policy.id
-    );
-    ensure!(
-        policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == minimum_ptx
-            && policy.minimum_sm.as_deref() == Some(minimum_sm)
-            && policy.ptx_result == rust_result
-            && policy.targets == "all"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == "9.7.9.22 Data Movement and Conversion Instructions: cvt"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt",
-        "{} packed-conversion effects, carrier, target floor, or PTX provenance disagree",
-        policy.id
-    );
-    let expected_ptx_operands = vec![
-        OperandPattern::Register;
-        conversion
-            .source_format
-            .operand_count()
-            .checked_add(1)
-            .context("packed-conversion operand count overflow")?
-    ];
-    ensure!(
-        policy.expected_ptx.mnemonic == "cvt"
-            && policy.expected_ptx.modifiers == packed_conversion_ptx_modifiers(conversion)
-            && policy.expected_ptx.operands == expected_ptx_operands,
-        "{} expected PTX does not match its closed conversion recipe",
-        policy.id
-    );
-    ensure!(
-        policy.summary == recipe.summary,
-        "{} packed-conversion summary does not match its closed recipe",
-        policy.id
-    );
-    let backend_pairs = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect::<BTreeSet<_>>();
-    let expected_pairs = [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
-        .map(|backend| {
-            (
-                backend,
-                packed_conversion_backend_mechanism(conversion, backend),
-            )
-        })
-        .into_iter()
-        .collect::<BTreeSet<_>>();
-    ensure!(
-        policy.backend_lowerings.len() == 2 && backend_pairs == expected_pairs,
-        "{} must define exactly the reviewed packed-conversion backend routes",
-        policy.id
-    );
-    for lowering in &policy.backend_lowerings {
-        ensure!(
-            lowering.minimum_ptx.as_deref() == Some(minimum_ptx)
-                && lowering.minimum_sm.as_deref() == Some(minimum_sm)
-                && !lowering.evidence_profile.trim().is_empty(),
-            "{} backend {:?} does not carry its exact packed-conversion floor",
-            policy.id,
-            lowering.backend
-        );
-    }
-    ensure_no_other_family_contract(policy, "packed conversion")?;
-    Ok(())
-}
-
-#[derive(Clone, Copy)]
-struct ScalarConversionRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    rust_name: &'static str,
-    selection_record: &'static str,
-    selection_asm: &'static str,
-    minimum_ptx: &'static str,
-    minimum_sm: &'static str,
-    ptx_modifiers: &'static [&'static str],
-}
-
-fn scalar_conversion_recipe(
-    rounding: ScalarConversionRounding,
-    saturation: ScalarConversionSaturation,
-) -> Option<ScalarConversionRecipe> {
-    use ScalarConversionRounding::{NearestAway, NearestEven, TowardZero};
-    use ScalarConversionSaturation::{None, Relu, ReluSatfinite, Satfinite};
-
-    Some(match (rounding, saturation) {
-        (NearestAway, None) => ScalarConversionRecipe {
-            id: "cvt_rna_tf32_f32",
-            abi_id: "i0368",
-            operation_key: "convert.f32.tf32.rna",
-            source_record: "int_nvvm_f2tf32_rna",
-            llvm_symbol: "llvm.nvvm.f2tf32.rna",
-            rust_name: "cvt_rna_tf32_f32",
-            selection_record: "CVT_to_tf32_rna",
-            selection_asm: "cvt.rna.tf32.f32 \t$dst, $src;",
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_modifiers: &["rna", "tf32", "f32"],
-        },
-        (NearestAway, Satfinite) => ScalarConversionRecipe {
-            id: "cvt_rna_satfinite_tf32_f32",
-            abi_id: "i0369",
-            operation_key: "convert.f32.tf32.rna.satfinite",
-            source_record: "int_nvvm_f2tf32_rna_satfinite",
-            llvm_symbol: "llvm.nvvm.f2tf32.rna.satfinite",
-            rust_name: "cvt_rna_satfinite_tf32_f32",
-            selection_record: "CVT_to_tf32_rna_satf",
-            selection_asm: "cvt.rna.satfinite.tf32.f32 \t$dst, $src;",
-            minimum_ptx: "8.1",
-            minimum_sm: "sm_80",
-            ptx_modifiers: &["rna", "satfinite", "tf32", "f32"],
-        },
-        (NearestEven, None) => ScalarConversionRecipe {
-            id: "cvt_rn_tf32_f32",
-            abi_id: "i0370",
-            operation_key: "convert.f32.tf32.rn",
-            source_record: "int_nvvm_f2tf32_rn",
-            llvm_symbol: "llvm.nvvm.f2tf32.rn",
-            rust_name: "cvt_rn_tf32_f32",
-            selection_record: "CVT_to_tf32_rn",
-            selection_asm: "cvt.rn.tf32.f32 \t$dst, $src;",
-            minimum_ptx: "7.8",
-            minimum_sm: "sm_90",
-            ptx_modifiers: &["rn", "tf32", "f32"],
-        },
-        (NearestEven, Relu) => ScalarConversionRecipe {
-            id: "cvt_rn_relu_tf32_f32",
-            abi_id: "i0371",
-            operation_key: "convert.f32.tf32.rn.relu",
-            source_record: "int_nvvm_f2tf32_rn_relu",
-            llvm_symbol: "llvm.nvvm.f2tf32.rn.relu",
-            rust_name: "cvt_rn_relu_tf32_f32",
-            selection_record: "CVT_to_tf32_rn_relu",
-            selection_asm: "cvt.rn.relu.tf32.f32 \t$dst, $src;",
-            minimum_ptx: "7.8",
-            minimum_sm: "sm_90",
-            ptx_modifiers: &["rn", "relu", "tf32", "f32"],
-        },
-        (NearestEven, Satfinite) => ScalarConversionRecipe {
-            id: "cvt_rn_satfinite_tf32_f32",
-            abi_id: "i0372",
-            operation_key: "convert.f32.tf32.rn.satfinite",
-            source_record: "int_nvvm_f2tf32_rn_satfinite",
-            llvm_symbol: "llvm.nvvm.f2tf32.rn.satfinite",
-            rust_name: "cvt_rn_satfinite_tf32_f32",
-            selection_record: "CVT_to_tf32_rn_satf",
-            selection_asm: "cvt.rn.satfinite.tf32.f32 \t$dst, $src;",
-            minimum_ptx: "8.6",
-            minimum_sm: "sm_100",
-            ptx_modifiers: &["rn", "satfinite", "tf32", "f32"],
-        },
-        (NearestEven, ReluSatfinite) => ScalarConversionRecipe {
-            id: "cvt_rn_relu_satfinite_tf32_f32",
-            abi_id: "i0373",
-            operation_key: "convert.f32.tf32.rn.relu.satfinite",
-            source_record: "int_nvvm_f2tf32_rn_relu_satfinite",
-            llvm_symbol: "llvm.nvvm.f2tf32.rn.relu.satfinite",
-            rust_name: "cvt_rn_relu_satfinite_tf32_f32",
-            selection_record: "CVT_to_tf32_rn_relu_satf",
-            selection_asm: "cvt.rn.relu.satfinite.tf32.f32 \t$dst, $src;",
-            minimum_ptx: "8.6",
-            minimum_sm: "sm_100",
-            ptx_modifiers: &["rn", "relu", "satfinite", "tf32", "f32"],
-        },
-        (TowardZero, None) => ScalarConversionRecipe {
-            id: "cvt_rz_tf32_f32",
-            abi_id: "i0374",
-            operation_key: "convert.f32.tf32.rz",
-            source_record: "int_nvvm_f2tf32_rz",
-            llvm_symbol: "llvm.nvvm.f2tf32.rz",
-            rust_name: "cvt_rz_tf32_f32",
-            selection_record: "CVT_to_tf32_rz",
-            selection_asm: "cvt.rz.tf32.f32 \t$dst, $src;",
-            minimum_ptx: "7.8",
-            minimum_sm: "sm_90",
-            ptx_modifiers: &["rz", "tf32", "f32"],
-        },
-        (TowardZero, Relu) => ScalarConversionRecipe {
-            id: "cvt_rz_relu_tf32_f32",
-            abi_id: "i0375",
-            operation_key: "convert.f32.tf32.rz.relu",
-            source_record: "int_nvvm_f2tf32_rz_relu",
-            llvm_symbol: "llvm.nvvm.f2tf32.rz.relu",
-            rust_name: "cvt_rz_relu_tf32_f32",
-            selection_record: "CVT_to_tf32_rz_relu",
-            selection_asm: "cvt.rz.relu.tf32.f32 \t$dst, $src;",
-            minimum_ptx: "7.8",
-            minimum_sm: "sm_90",
-            ptx_modifiers: &["rz", "relu", "tf32", "f32"],
-        },
-        (TowardZero, Satfinite) => ScalarConversionRecipe {
-            id: "cvt_rz_satfinite_tf32_f32",
-            abi_id: "i0376",
-            operation_key: "convert.f32.tf32.rz.satfinite",
-            source_record: "int_nvvm_f2tf32_rz_satfinite",
-            llvm_symbol: "llvm.nvvm.f2tf32.rz.satfinite",
-            rust_name: "cvt_rz_satfinite_tf32_f32",
-            selection_record: "CVT_to_tf32_rz_satf",
-            selection_asm: "cvt.rz.satfinite.tf32.f32 \t$dst, $src;",
-            minimum_ptx: "8.6",
-            minimum_sm: "sm_100",
-            ptx_modifiers: &["rz", "satfinite", "tf32", "f32"],
-        },
-        (TowardZero, ReluSatfinite) => ScalarConversionRecipe {
-            id: "cvt_rz_relu_satfinite_tf32_f32",
-            abi_id: "i0377",
-            operation_key: "convert.f32.tf32.rz.relu.satfinite",
-            source_record: "int_nvvm_f2tf32_rz_relu_satfinite",
-            llvm_symbol: "llvm.nvvm.f2tf32.rz.relu.satfinite",
-            rust_name: "cvt_rz_relu_satfinite_tf32_f32",
-            selection_record: "CVT_to_tf32_rz_relu_satf",
-            selection_asm: "cvt.rz.relu.satfinite.tf32.f32 \t$dst, $src;",
-            minimum_ptx: "8.6",
-            minimum_sm: "sm_100",
-            ptx_modifiers: &["rz", "relu", "satfinite", "tf32", "f32"],
-        },
-        _ => return Option::None,
-    })
-}
-
-fn expand_scalar_conversion_admission(
-    admission: &ScalarConversionAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "scalar-conversion runtime may be marked executed only with GPU evidence"
-    );
-    let expected = [
-        (
-            ScalarConversionRounding::NearestAway,
-            ScalarConversionSaturation::None,
-        ),
-        (
-            ScalarConversionRounding::NearestAway,
-            ScalarConversionSaturation::Satfinite,
-        ),
-        (
-            ScalarConversionRounding::NearestEven,
-            ScalarConversionSaturation::None,
-        ),
-        (
-            ScalarConversionRounding::NearestEven,
-            ScalarConversionSaturation::Relu,
-        ),
-        (
-            ScalarConversionRounding::NearestEven,
-            ScalarConversionSaturation::Satfinite,
-        ),
-        (
-            ScalarConversionRounding::NearestEven,
-            ScalarConversionSaturation::ReluSatfinite,
-        ),
-        (
-            ScalarConversionRounding::TowardZero,
-            ScalarConversionSaturation::None,
-        ),
-        (
-            ScalarConversionRounding::TowardZero,
-            ScalarConversionSaturation::Relu,
-        ),
-        (
-            ScalarConversionRounding::TowardZero,
-            ScalarConversionSaturation::Satfinite,
-        ),
-        (
-            ScalarConversionRounding::TowardZero,
-            ScalarConversionSaturation::ReluSatfinite,
-        ),
-    ];
-    let actual = admission
-        .variants
-        .iter()
-        .map(|variant| (variant.rounding, variant.saturation))
-        .collect::<Vec<_>>();
-    ensure!(
-        actual == expected,
-        "compact scalar-conversion admission must list the canonical ten variants"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = scalar_conversion_recipe(variant.rounding, variant.saturation)
-                .context("scalar conversion is outside the closed recipe set")?;
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must reserve ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            scalar_conversion_overlay_record(
-                recipe,
-                admission,
-                variant.rounding,
-                variant.saturation,
-            )
-        })
-        .collect()
-}
-
-fn scalar_conversion_overlay_record(
-    recipe: ScalarConversionRecipe,
-    admission: &ScalarConversionAdmission,
-    rounding: ScalarConversionRounding,
-    saturation: ScalarConversionSaturation,
-) -> Result<OverlayIntrinsic> {
-    Ok(OverlayIntrinsic {
-        id: recipe.id.into(),
-        abi_id: recipe.abi_id.into(),
-        operation_key: recipe.operation_key.into(),
-        family: "scalar_conversion".into(),
-        source: None,
-        source_record: Some(recipe.source_record.into()),
-        rust_module: "convert".into(),
-        rust_name: recipe.rust_name.into(),
-        rust_arguments: vec!["f32".into()],
-        rust_result: "u32".into(),
-        safe: true,
-        must_use: true,
-        safe_allowlist_reason: Some("This conversion has no caller obligations.".into()),
-        public_rust_path: format!("cuda_intrinsics::convert::{}", recipe.rust_name),
-        compatibility_rust_paths: vec![format!(
-            "cuda_device::convert::{}",
-            recipe.rust_name
-        )],
-        dialect_op_type: "ScalarConversionOp".into(),
-        dialect_op_name: "nvvm.scalar_conversion".into(),
-        dialect_operands: vec!["f32".into()],
-        dialect_results: vec!["i32".into()],
-        llvm_symbol: Some(recipe.llvm_symbol.into()),
-        resolved_llvm_symbol: None,
-        llvm_arguments: vec!["f32".into()],
-        llvm_results: vec!["i32".into()],
-        pure: true,
-        memory: "none".into(),
-        convergent: false,
-        execution_scope: "thread".into(),
-        minimum_ptx: recipe.minimum_ptx.into(),
-        minimum_sm: Some(recipe.minimum_sm.into()),
-        ptx_result: "u32".into(),
-        targets: "all".into(),
-        ptx_isa_version: "9.3".into(),
-        ptx_isa_section: "9.7.9.22 Data Movement and Conversion Instructions: cvt".into(),
-        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt".into(),
-        lowering: "generated_scalar_conversion".into(),
-        backend_lowerings: [
-            (IntrinsicBackend::LlvmNvptx, &admission.llvm_evidence_profile),
-            (IntrinsicBackend::LibNvvm, &admission.libnvvm_evidence_profile),
-        ]
-        .into_iter()
-        .map(|(backend, evidence_profile)| OverlayBackendLowering {
-            backend,
-            mechanism: match backend {
-                IntrinsicBackend::LlvmNvptx => BackendLoweringMechanism::TypedNvvm,
-                IntrinsicBackend::LibNvvm => BackendLoweringMechanism::InlinePtx,
-            },
-            evidence_profile: evidence_profile.clone(),
-            targets: None,
-            minimum_ptx: Some(recipe.minimum_ptx.into()),
-            minimum_sm: Some(recipe.minimum_sm.into()),
-        })
-        .collect(),
-        packed_atomic: None,
-        redux: None,
-        vote: None,
-        active_mask: None,
-        warp_match: None,
-        warp_barrier: None,
-        warp_shuffle: None,
-        dot_product: None,
-        packed_alu: None,
-        integer_minmax: None,
-        packed_conversion: None,
-        scalar_conversion: Some(ScalarConversion {
-            source_format: ScalarConversionSourceFormat::F32,
-            destination_format: ScalarConversionDestinationFormat::Tf32,
-            rounding,
-            saturation,
-            result_representation: ScalarConversionResultRepresentation::RawU32Bits,
-            adapter: ScalarConversionAdapter::DirectF32ToRawU32Bits,
-            runtime_validation: admission.runtime_validation,
-        }),
-        scalar_arithmetic: None,
-        scalar_math: None,
-        extended_minmax: None,
-        cp_async_copy: None,
-        cp_async_control: None,
-        cp_async_mbarrier: None,
-        mbarrier_basic: None,
-        movmatrix: None,
-        mbarrier_extended: None,
-        register_mma: None,
-        sparse_mma: None,
-        prmt: None,
-        cluster_barrier: None,
-        wgmma_control: None,
-        special_register: None,
-        debug_control: None,
-        cluster_memory: None,
-        clc: None,
-        tma: None,
-        tcgen05: None,
-        ldmatrix_variant: None,
-        ldmatrix_safety: None,
-        ldmatrix_adapter: None,
-        selected_address_space: None,
-        expected_ptx: InstructionPattern {
-            mnemonic: "cvt".into(),
-            modifiers: recipe.ptx_modifiers.iter().map(|value| (*value).into()).collect(),
-            operands: vec![OperandPattern::Register, OperandPattern::Register],
-        },
-        summary: format!(
-            "Converts one f32 value with {} and returns raw TF32 bits.",
-            recipe.ptx_modifiers[0]
-        ),
-    })
-}
-
-fn validate_scalar_conversion_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let conversion = policy
-        .scalar_conversion
-        .as_ref()
-        .with_context(|| format!("{} has no scalar-conversion contract", policy.id))?;
-    let recipe = scalar_conversion_recipe(conversion.rounding, conversion.saturation)
-        .with_context(|| {
-            format!(
-                "{} is outside the closed scalar-conversion recipe",
-                policy.id
-            )
-        })?;
-    ensure!(
-        conversion.source_format == ScalarConversionSourceFormat::F32
-            && conversion.destination_format == ScalarConversionDestinationFormat::Tf32
-            && conversion.result_representation == ScalarConversionResultRepresentation::RawU32Bits
-            && conversion.adapter == ScalarConversionAdapter::DirectF32ToRawU32Bits
-            && conversion.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} changed its scalar-conversion representation or adapter",
-        policy.id
-    );
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none()
-            && policy.llvm_arguments == ["f32"]
-            && policy.llvm_results == ["i32"],
-        "{} scalar-conversion identity or LLVM source changed",
-        policy.id
-    );
-    ensure!(
-        declaration.properties == ["IntrNoMem", "IntrSpeculatable"]
-            && declaration.selections.len() == 1
-            && declaration.selections[0].source_record == recipe.selection_record
-            && declaration.selections[0].asm == recipe.selection_asm
-            && declaration.selections[0].constraints.is_empty(),
-        "{} imported scalar-conversion declaration or selection changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "convert"
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == ["f32"]
-            && policy.rust_result == "u32"
-            && policy.safe
-            && policy.must_use
-            && policy.compatibility_rust_paths
-                == [format!("cuda_device::convert::{}", recipe.rust_name)]
-            && policy.dialect_op_type == "ScalarConversionOp"
-            && policy.dialect_op_name == "nvvm.scalar_conversion"
-            && policy.dialect_operands == ["f32"]
-            && policy.dialect_results == ["i32"]
-            && policy.lowering == "generated_scalar_conversion",
-        "{} changed its scalar-conversion API, carrier, or lowering",
-        policy.id
-    );
-    ensure!(
-        policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
-            && policy.ptx_result == "u32"
-            && policy.targets == "all",
-        "{} scalar-conversion effects or target floor changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx
-            == InstructionPattern {
-                mnemonic: "cvt".into(),
-                modifiers: recipe
-                    .ptx_modifiers
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                operands: vec![OperandPattern::Register, OperandPattern::Register],
-            },
-        "{} expected PTX changed",
-        policy.id
-    );
-    let expected_backends = [
-        (
-            IntrinsicBackend::LlvmNvptx,
-            BackendLoweringMechanism::TypedNvvm,
-        ),
-        (
-            IntrinsicBackend::LibNvvm,
-            BackendLoweringMechanism::InlinePtx,
-        ),
-    ];
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && expected_backends.into_iter().all(|(backend, mechanism)| {
-                policy.backend_lowerings.iter().any(|lowering| {
-                    lowering.backend == backend
-                        && lowering.mechanism == mechanism
-                        && lowering.minimum_ptx.as_deref() == Some(recipe.minimum_ptx)
-                        && lowering.minimum_sm.as_deref() == Some(recipe.minimum_sm)
-                        && !lowering.evidence_profile.trim().is_empty()
-                })
-            }),
-        "{} must define the typed LLVM and inline-PTX libNVVM routes",
-        policy.id
-    );
-    validate_selected_target_predicates(policy, &declaration.selections[0])?;
-    ensure_no_other_family_contract(policy, "scalar conversion")?;
-    Ok(())
-}
-
-#[derive(Clone)]
-struct ScalarArithmeticRecipe {
-    id: String,
-    operation_key: String,
-    source_record: String,
-    llvm_symbol: String,
-    selection_record: String,
-    selection_asm: String,
-    rust_type: &'static str,
-    argument_count: usize,
-    properties: Vec<&'static str>,
-    ptx_modifiers: Vec<String>,
-    ptx_isa_section: &'static str,
-    ptx_isa_url: &'static str,
-}
-
-type ScalarArithmeticVariant = (
-    ScalarArithmeticFormat,
-    ScalarArithmeticOperation,
-    ScalarArithmeticRounding,
-    ScalarArithmeticSubnormal,
-    ScalarArithmeticSaturation,
-);
-
-fn canonical_scalar_arithmetic_variants() -> Vec<ScalarArithmeticVariant> {
-    use ScalarArithmeticFormat::{F32, F64};
-    use ScalarArithmeticOperation::{Add, Div, Fma, Mul};
-    use ScalarArithmeticRounding::{Rm, Rn, Rp, Rz};
-    use ScalarArithmeticSaturation::{None, Sat};
-    use ScalarArithmeticSubnormal::{Ftz, Preserve};
-
-    let roundings = [Rn, Rz, Rm, Rp];
-    let mut variants = Vec::with_capacity(64);
-    for operation in [Mul, Div, Fma] {
-        for rounding in roundings {
-            variants.push((F64, operation, rounding, Preserve, None));
-        }
-    }
-    for operation in [Mul, Div] {
-        for rounding in roundings {
-            variants.push((F32, operation, rounding, Preserve, None));
-            variants.push((F32, operation, rounding, Ftz, None));
-        }
-    }
-    for rounding in roundings {
-        variants.push((F32, Fma, rounding, Preserve, None));
-        variants.push((F32, Fma, rounding, Ftz, None));
-        variants.push((F32, Fma, rounding, Preserve, Sat));
-        variants.push((F32, Fma, rounding, Ftz, Sat));
-    }
-    for rounding in roundings {
-        variants.push((F64, Add, rounding, Preserve, None));
-    }
-    for rounding in roundings {
-        variants.push((F32, Add, rounding, Preserve, None));
-        variants.push((F32, Add, rounding, Ftz, None));
-        variants.push((F32, Add, rounding, Preserve, Sat));
-        variants.push((F32, Add, rounding, Ftz, Sat));
-    }
-    variants
-}
-
-fn scalar_arithmetic_format_name(format: ScalarArithmeticFormat) -> &'static str {
-    match format {
-        ScalarArithmeticFormat::F32 => "f32",
-        ScalarArithmeticFormat::F64 => "f64",
-    }
-}
-
-fn scalar_arithmetic_operation_name(operation: ScalarArithmeticOperation) -> &'static str {
-    match operation {
-        ScalarArithmeticOperation::Mul => "mul",
-        ScalarArithmeticOperation::Div => "div",
-        ScalarArithmeticOperation::Fma => "fma",
-        ScalarArithmeticOperation::Add => "add",
-    }
-}
-
-fn scalar_arithmetic_rounding_name(rounding: ScalarArithmeticRounding) -> &'static str {
-    match rounding {
-        ScalarArithmeticRounding::Rn => "rn",
-        ScalarArithmeticRounding::Rz => "rz",
-        ScalarArithmeticRounding::Rm => "rm",
-        ScalarArithmeticRounding::Rp => "rp",
-    }
-}
-
-fn scalar_arithmetic_recipe(variant: ScalarArithmeticVariant) -> Option<ScalarArithmeticRecipe> {
-    if !canonical_scalar_arithmetic_variants().contains(&variant) {
-        return None;
-    }
-    let (format, operation, rounding, subnormal, saturation) = variant;
-    let operation_name = scalar_arithmetic_operation_name(operation);
-    let rounding_name = scalar_arithmetic_rounding_name(rounding);
-    let format_name = scalar_arithmetic_format_name(format);
-    let source_format = match format {
-        ScalarArithmeticFormat::F32 => "f",
-        ScalarArithmeticFormat::F64 => "d",
-    };
-
-    let mut modifier_names = vec![rounding_name];
-    if subnormal == ScalarArithmeticSubnormal::Ftz {
-        modifier_names.push("ftz");
-    }
-    if saturation == ScalarArithmeticSaturation::Sat {
-        modifier_names.push("sat");
-    }
-
-    let modifier_id = modifier_names.join("_");
-    let modifier_symbol = modifier_names.join(".");
-    let id = format!("{operation_name}_{modifier_id}_{format_name}");
-    let source_record = format!("int_nvvm_{operation_name}_{modifier_id}_{source_format}");
-    let llvm_symbol = format!("llvm.nvvm.{operation_name}.{modifier_symbol}.{source_format}");
-    let mut ptx_modifier_names = modifier_names.clone();
-    if operation == ScalarArithmeticOperation::Add
-        && subnormal == ScalarArithmeticSubnormal::Ftz
-        && saturation == ScalarArithmeticSaturation::Sat
-    {
-        ptx_modifier_names.swap(1, 2);
-    }
-    let ptx_modifiers = ptx_modifier_names
-        .iter()
-        .copied()
-        .chain(std::iter::once(format_name))
-        .map(str::to_owned)
-        .collect::<Vec<_>>();
-    let selection_record = match operation {
-        ScalarArithmeticOperation::Fma => {
-            format!("INT_NVVM_FMA_{modifier_id}_{format_name}")
-        }
-        ScalarArithmeticOperation::Mul | ScalarArithmeticOperation::Div => format!(
-            "INT_NVVM_{}_{}_{}",
-            operation_name.to_ascii_uppercase(),
-            modifier_id.to_ascii_uppercase(),
-            source_format.to_ascii_uppercase()
-        ),
-        ScalarArithmeticOperation::Add => {
-            let selection_modifier = ptx_modifier_names.join("_").to_ascii_uppercase();
-            format!(
-                "INT_NVVM_ADD_{selection_modifier}_{}",
-                source_format.to_ascii_uppercase()
-            )
-        }
-    };
-    let argument_count = if operation == ScalarArithmeticOperation::Fma {
-        3
-    } else {
-        2
-    };
-    let operands = (0..argument_count)
-        .map(|argument| format!("$src{argument}"))
-        .collect::<Vec<_>>()
-        .join(", ");
-    let ptx_modifier_symbol = ptx_modifier_names.join(".");
-    let selection_asm =
-        format!("{operation_name}.{ptx_modifier_symbol}.{format_name} \t$dst, {operands};");
-    let properties = match (operation, format) {
-        (ScalarArithmeticOperation::Mul | ScalarArithmeticOperation::Add, _) => {
-            vec!["Commutative", "IntrNoMem", "IntrSpeculatable"]
-        }
-        (ScalarArithmeticOperation::Div, _) => vec!["IntrNoMem"],
-        (ScalarArithmeticOperation::Fma, ScalarArithmeticFormat::F32) => {
-            vec!["IntrNoMem", "IntrSpeculatable"]
-        }
-        (ScalarArithmeticOperation::Fma, ScalarArithmeticFormat::F64) => {
-            vec!["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"]
-        }
-    };
-    let (ptx_isa_section, ptx_isa_url) = match operation {
-        ScalarArithmeticOperation::Mul => (
-            "9.7.3.5 Floating Point Instructions: mul",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-mul",
-        ),
-        ScalarArithmeticOperation::Fma => (
-            "9.7.3.6 Floating Point Instructions: fma",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-fma",
-        ),
-        ScalarArithmeticOperation::Div => (
-            "9.7.3.8 Floating Point Instructions: div",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-div",
-        ),
-        ScalarArithmeticOperation::Add => (
-            "9.7.3.3 Floating Point Instructions: add",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-add",
-        ),
-    };
-
-    Some(ScalarArithmeticRecipe {
-        id,
-        operation_key: format!(
-            "scalar.arithmetic.{operation_name}.{modifier_symbol}.{format_name}"
-        ),
-        source_record,
-        llvm_symbol,
-        selection_record,
-        selection_asm,
-        rust_type: format_name,
-        argument_count,
-        properties,
-        ptx_modifiers,
-        ptx_isa_section,
-        ptx_isa_url,
-    })
-}
-
-fn expand_scalar_arithmetic_admission(
-    admission: &ScalarArithmeticAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "scalar-arithmetic runtime may be marked executed only with GPU evidence"
-    );
-    let expected = canonical_scalar_arithmetic_variants();
-    let actual = admission
-        .variants
-        .iter()
-        .map(|variant| {
-            (
-                variant.format,
-                variant.operation,
-                variant.rounding,
-                variant.subnormal,
-                variant.saturation,
-            )
-        })
-        .collect::<Vec<_>>();
-    ensure!(
-        actual == expected,
-        "compact scalar-arithmetic admission must list the canonical 64 variants"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            validate_abi_id(&variant.abi_id)?;
-            let identity = (
-                variant.format,
-                variant.operation,
-                variant.rounding,
-                variant.subnormal,
-                variant.saturation,
-            );
-            let recipe = scalar_arithmetic_recipe(identity)
-                .context("scalar arithmetic is outside the closed recipe set")?;
-            scalar_arithmetic_overlay_record(recipe, admission, identity, &variant.abi_id)
-        })
-        .collect()
-}
-
-fn scalar_arithmetic_overlay_record(
-    recipe: ScalarArithmeticRecipe,
-    admission: &ScalarArithmeticAdmission,
-    variant: ScalarArithmeticVariant,
-    abi_id: &str,
-) -> Result<OverlayIntrinsic> {
-    let (format, operation, rounding, subnormal, saturation) = variant;
-    let rust_arguments = vec![recipe.rust_type.into(); recipe.argument_count];
-    let ptx_operands = vec![OperandPattern::Register; recipe.argument_count + 1];
-    let summary = format!(
-        "Computes scalar {} with explicit {} rounding.",
-        scalar_arithmetic_operation_name(operation),
-        scalar_arithmetic_rounding_name(rounding)
-    );
-    Ok(OverlayIntrinsic {
-        id: recipe.id.clone(),
-        abi_id: abi_id.into(),
-        operation_key: recipe.operation_key,
-        family: "scalar_arithmetic".into(),
-        source: None,
-        source_record: Some(recipe.source_record),
-        rust_module: "float".into(),
-        rust_name: recipe.id.clone(),
-        rust_arguments: rust_arguments.clone(),
-        rust_result: recipe.rust_type.into(),
-        safe: true,
-        must_use: true,
-        safe_allowlist_reason: Some("Scalar arithmetic has no caller obligations.".into()),
-        public_rust_path: format!("cuda_intrinsics::float::{}", recipe.id),
-        compatibility_rust_paths: vec![format!("cuda_device::float::{}", recipe.id)],
-        dialect_op_type: "ScalarArithmeticOp".into(),
-        dialect_op_name: "nvvm.scalar_arithmetic".into(),
-        dialect_operands: rust_arguments.clone(),
-        dialect_results: vec![recipe.rust_type.into()],
-        llvm_symbol: Some(recipe.llvm_symbol),
-        resolved_llvm_symbol: None,
-        llvm_arguments: rust_arguments,
-        llvm_results: vec![recipe.rust_type.into()],
-        pure: operation != ScalarArithmeticOperation::Div,
-        memory: "none".into(),
-        convergent: false,
-        execution_scope: "thread".into(),
-        minimum_ptx: "7.0".into(),
-        minimum_sm: Some("sm_80".into()),
-        ptx_result: recipe.rust_type.into(),
-        targets: "all".into(),
-        ptx_isa_version: "9.3".into(),
-        ptx_isa_section: recipe.ptx_isa_section.into(),
-        ptx_isa_url: recipe.ptx_isa_url.into(),
-        lowering: "generated_scalar_arithmetic".into(),
-        backend_lowerings: [
-            (
-                IntrinsicBackend::LlvmNvptx,
-                &admission.llvm_evidence_profile,
-            ),
-            (
-                IntrinsicBackend::LibNvvm,
-                &admission.libnvvm_evidence_profile,
-            ),
-        ]
-        .into_iter()
-        .map(|(backend, evidence_profile)| OverlayBackendLowering {
-            backend,
-            mechanism: match backend {
-                IntrinsicBackend::LlvmNvptx if saturation == ScalarArithmeticSaturation::Sat => {
-                    // LLVM 21 has no typed intrinsic for these LLVM 22 forms.
-                    BackendLoweringMechanism::InlinePtx
-                }
-                IntrinsicBackend::LlvmNvptx => BackendLoweringMechanism::TypedNvvm,
-                IntrinsicBackend::LibNvvm => BackendLoweringMechanism::InlinePtx,
-            },
-            evidence_profile: evidence_profile.clone(),
-            targets: None,
-            minimum_ptx: Some("7.0".into()),
-            minimum_sm: Some("sm_80".into()),
-        })
-        .collect(),
-        packed_atomic: None,
-        redux: None,
-        vote: None,
-        active_mask: None,
-        warp_match: None,
-        warp_barrier: None,
-        warp_shuffle: None,
-        dot_product: None,
-        packed_alu: None,
-        integer_minmax: None,
-        packed_conversion: None,
-        scalar_conversion: None,
-        scalar_arithmetic: Some(ScalarArithmetic {
-            format,
-            operation,
-            rounding,
-            subnormal,
-            saturation,
-            runtime_validation: admission.runtime_validation,
-        }),
-        scalar_math: None,
-        extended_minmax: None,
-        cp_async_copy: None,
-        cp_async_control: None,
-        cp_async_mbarrier: None,
-        mbarrier_basic: None,
-        movmatrix: None,
-        mbarrier_extended: None,
-        register_mma: None,
-        sparse_mma: None,
-        prmt: None,
-        cluster_barrier: None,
-        wgmma_control: None,
-        special_register: None,
-        debug_control: None,
-        cluster_memory: None,
-        clc: None,
-        tma: None,
-        tcgen05: None,
-        ldmatrix_variant: None,
-        ldmatrix_safety: None,
-        ldmatrix_adapter: None,
-        selected_address_space: None,
-        expected_ptx: InstructionPattern {
-            mnemonic: scalar_arithmetic_operation_name(operation).into(),
-            modifiers: recipe.ptx_modifiers,
-            operands: ptx_operands,
-        },
-        summary,
-    })
-}
-
-fn validate_scalar_arithmetic_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let arithmetic = policy
-        .scalar_arithmetic
-        .as_ref()
-        .with_context(|| format!("{} has no scalar-arithmetic contract", policy.id))?;
-    let variant = (
-        arithmetic.format,
-        arithmetic.operation,
-        arithmetic.rounding,
-        arithmetic.subnormal,
-        arithmetic.saturation,
-    );
-    let recipe = scalar_arithmetic_recipe(variant).with_context(|| {
-        format!(
-            "{} is outside the closed scalar-arithmetic recipe",
-            policy.id
-        )
-    })?;
-    ensure!(
-        arithmetic.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} scalar-arithmetic runtime may be executed only with GPU evidence",
-        policy.id
-    );
-    let signature = vec![recipe.rust_type.to_owned(); recipe.argument_count];
-    ensure!(
-        policy.id == recipe.id
-            && policy.operation_key == recipe.operation_key
-            && policy.source_record.as_deref() == Some(recipe.source_record.as_str())
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none()
-            && policy.llvm_arguments == signature
-            && policy.llvm_results == [recipe.rust_type],
-        "{} scalar-arithmetic identity or LLVM source changed",
-        policy.id
-    );
-    let expected_properties = recipe
-        .properties
-        .iter()
-        .map(|property| (*property).to_owned())
-        .collect::<Vec<_>>();
-    ensure!(
-        declaration.properties == expected_properties,
-        "{} imported scalar-arithmetic properties changed",
-        policy.id
-    );
-    let direct = declaration
-        .selections
-        .first()
-        .with_context(|| format!("{} has no imported scalar selection", policy.id))?;
-    ensure!(
-        direct.source_record == recipe.selection_record
-            && direct.asm == recipe.selection_asm
-            && direct.predicates.is_empty()
-            && direct.constraints.is_empty(),
-        "{} direct scalar-arithmetic selection changed",
-        policy.id
-    );
-    if arithmetic.operation == ScalarArithmeticOperation::Add {
-        let rounding = scalar_arithmetic_rounding_name(arithmetic.rounding);
-        let source_modifiers = [
-            Some(rounding),
-            (arithmetic.subnormal == ScalarArithmeticSubnormal::Ftz).then_some("ftz"),
-            (arithmetic.saturation == ScalarArithmeticSaturation::Sat).then_some("sat"),
-        ]
-        .into_iter()
-        .flatten()
-        .collect::<Vec<_>>()
-        .join("_");
-        let mut expected = Vec::new();
-        if arithmetic.format == ScalarArithmeticFormat::F32
-            && arithmetic.subnormal == ScalarArithmeticSubnormal::Preserve
-        {
-            let saturation = if arithmetic.saturation == ScalarArithmeticSaturation::Sat {
-                "_sat"
-            } else {
-                ""
-            };
-            for instruction in ["ADD", "SUB"] {
-                for input_format in ["bf16", "f16"] {
-                    expected.push((
-                        format!(
-                            "INT_NVVM_MIXED_{instruction}_{rounding}{saturation}_f32_{input_format}"
-                        ),
-                        format!(
-                            "{}.{rounding}{}.f32.{input_format} \t$dst, $a, $b;",
-                            instruction.to_ascii_lowercase(),
-                            if arithmetic.saturation == ScalarArithmeticSaturation::Sat {
-                                ".sat"
-                            } else {
-                                ""
-                            }
-                        ),
-                        vec![
-                            "Subtarget->getSmVersion() >= 100".to_owned(),
-                            "Subtarget->getPTXVersion() >= 86".to_owned(),
-                        ],
-                    ));
-                }
-            }
-        }
-        let source_format = match arithmetic.format {
-            ScalarArithmeticFormat::F32 => "F",
-            ScalarArithmeticFormat::F64 => "D",
-        };
-        expected.push((
-            format!("INT_NVVM_SUB_{source_modifiers}_{source_format}"),
-            format!("sub.{} \t$dst, $a, $b;", recipe.ptx_modifiers.join(".")),
-            Vec::new(),
-        ));
-        ensure!(
-            declaration.selections.len() == expected.len() + 1,
-            "{} must retain one direct add and the reviewed non-add alternatives",
-            policy.id
-        );
-        for (selection, (source_record, asm, predicates)) in
-            declaration.selections[1..].iter().zip(expected)
-        {
-            ensure!(
-                selection.source_record == source_record
-                    && selection.asm == asm
-                    && selection.predicates == predicates
-                    && selection.constraints.is_empty(),
-                "{} non-add scalar selection changed",
-                policy.id
-            );
-        }
-    } else if arithmetic.format == ScalarArithmeticFormat::F32
-        && arithmetic.operation == ScalarArithmeticOperation::Fma
-        && arithmetic.subnormal == ScalarArithmeticSubnormal::Preserve
-    {
-        ensure!(
-            declaration.selections.len() == 3,
-            "{} must retain one direct and two mixed-input selections",
-            policy.id
-        );
-        let rounding = scalar_arithmetic_rounding_name(arithmetic.rounding);
-        let saturation = if arithmetic.saturation == ScalarArithmeticSaturation::Sat {
-            "_sat"
-        } else {
-            ""
-        };
-        for (selection, input_format) in declaration.selections[1..].iter().zip(["bf16", "f16"]) {
-            ensure!(
-                selection.source_record
-                    == format!("INT_NVVM_MIXED_FMA_{rounding}{saturation}_f32_{input_format}")
-                    && selection.asm
-                        == format!(
-                            "fma.{rounding}{}.f32.{input_format} \t$dst, $a, $b, $c;",
-                            if arithmetic.saturation == ScalarArithmeticSaturation::Sat {
-                                ".sat"
-                            } else {
-                                ""
-                            }
-                        )
-                    && selection.predicates
-                        == [
-                            "Subtarget->getSmVersion() >= 100",
-                            "Subtarget->getPTXVersion() >= 86",
-                        ]
-                    && selection.constraints.is_empty(),
-                "{} mixed-input scalar-arithmetic selection changed",
-                policy.id
-            );
-        }
-    } else {
-        ensure!(
-            declaration.selections.len() == 1,
-            "{} gained an unreviewed scalar-arithmetic selection",
-            policy.id
-        );
-    }
-    let mut selected = Vec::new();
-    for selection in &declaration.selections {
-        if selection_matches_policy(policy, selection)? {
-            selected.push(selection);
-        }
-    }
-    ensure!(
-        selected.len() == 1 && selected[0].source_record == recipe.selection_record,
-        "{} must select only its direct scalar arithmetic instruction",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "float"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == signature
-            && policy.rust_result == recipe.rust_type
-            && policy.safe
-            && policy.must_use
-            && policy.compatibility_rust_paths == [format!("cuda_device::float::{}", recipe.id)]
-            && policy.dialect_op_type == "ScalarArithmeticOp"
-            && policy.dialect_op_name == "nvvm.scalar_arithmetic"
-            && policy.dialect_operands == signature
-            && policy.dialect_results == [recipe.rust_type]
-            && policy.lowering == "generated_scalar_arithmetic",
-        "{} changed its scalar-arithmetic API, carrier, or lowering",
-        policy.id
-    );
-    ensure!(
-        policy.pure == (arithmetic.operation != ScalarArithmeticOperation::Div)
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == "7.0"
-            && policy.minimum_sm.as_deref() == Some("sm_80")
-            && policy.ptx_result == recipe.rust_type
-            && policy.targets == "all"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.ptx_isa_section
-            && policy.ptx_isa_url == recipe.ptx_isa_url,
-        "{} scalar-arithmetic effects, provenance, or target floor changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx
-            == InstructionPattern {
-                mnemonic: scalar_arithmetic_operation_name(arithmetic.operation).into(),
-                modifiers: recipe.ptx_modifiers.clone(),
-                operands: vec![OperandPattern::Register; recipe.argument_count + 1],
-            },
-        "{} expected scalar-arithmetic PTX changed",
-        policy.id
-    );
-    let llvm_mechanism = if arithmetic.saturation == ScalarArithmeticSaturation::Sat {
-        BackendLoweringMechanism::InlinePtx
-    } else {
-        BackendLoweringMechanism::TypedNvvm
-    };
-    let expected_backends = [
-        (IntrinsicBackend::LlvmNvptx, llvm_mechanism),
-        (
-            IntrinsicBackend::LibNvvm,
-            BackendLoweringMechanism::InlinePtx,
-        ),
-    ];
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && expected_backends.into_iter().all(|(backend, mechanism)| {
-                policy.backend_lowerings.iter().any(|lowering| {
-                    lowering.backend == backend
-                        && lowering.mechanism == mechanism
-                        && lowering.minimum_ptx.as_deref() == Some("7.0")
-                        && lowering.minimum_sm.as_deref() == Some("sm_80")
-                        && !lowering.evidence_profile.trim().is_empty()
-                })
-            }),
-        "{} has the wrong reviewed scalar-arithmetic backend routes",
-        policy.id
-    );
-    validate_selected_target_predicates(policy, direct)?;
-    ensure_no_other_family_contract(policy, "scalar arithmetic")?;
-    Ok(())
-}
-
-type ScalarMathVariant = (
-    ScalarMathFormat,
-    ScalarMathOperation,
-    ScalarMathPrecision,
-    ScalarMathSubnormal,
-);
-
-#[derive(Clone, PartialEq, Eq)]
-enum ScalarMathRecipeSource {
-    /// Bound to a monomorphic tblgen record in the pinned import.
-    Imported {
-        source_record: String,
-        llvm_symbol: String,
-    },
-    /// Bound to an overloaded (polymorphic) tblgen record: the import
-    /// carries `anonymous_14`/`anyfloat` signature tokens and the concrete
-    /// f32 instantiation is recorded as the resolved symbol. Only ex2 uses
-    /// this (LLVM 22 models it as `int_nvvm_ex2_approx{,_ftz}` without a
-    /// per-format record).
-    ImportedOverloaded {
-        source_record: String,
-        llvm_symbol: String,
-        resolved_llvm_symbol: String,
-    },
-    /// No record exists in the pinned tblgen import at all. Only tanh uses
-    /// this: llc selects `llvm.nvvm.tanh.approx.f32` via NVVMIntrinsic-class
-    /// matching, but the import exports no record for it, so the op is
-    /// admitted directly against the PTX instruction.
-    PtxNative { instruction: String },
-}
-
-struct ScalarMathRecipe {
-    id: String,
-    operation_key: String,
-    source: ScalarMathRecipeSource,
-    rust_type: &'static str,
-    dialect_type: &'static str,
-    minimum_ptx: &'static str,
-    minimum_sm: &'static str,
-    properties: Vec<&'static str>,
-    ptx_modifiers: Vec<String>,
-    ptx_isa_section: &'static str,
-    ptx_isa_url: &'static str,
-    /// The generator's tblgen import found no DAG selection pattern for the
-    /// intrinsic, so the lowering routes it through inline PTX. Note this is
-    /// an import limitation, not an llc one: llc still selects these
-    /// intrinsics through NVVMIntrinsic-class pattern matching, which the
-    /// evidence import cannot see. Promoting them to typed calls once the
-    /// import understands those patterns would reopen them to LLVM
-    /// optimization.
-    force_inline_ptx: bool,
-}
-
-fn scalar_math_format_name(format: ScalarMathFormat) -> &'static str {
-    match format {
-        ScalarMathFormat::F16 => "f16",
-        ScalarMathFormat::F32 => "f32",
-        ScalarMathFormat::F64 => "f64",
-    }
-}
-
-fn scalar_math_operation_name(operation: ScalarMathOperation) -> &'static str {
-    match operation {
-        ScalarMathOperation::Sin => "sin",
-        ScalarMathOperation::Cos => "cos",
-        ScalarMathOperation::Ex2 => "ex2",
-        ScalarMathOperation::Lg2 => "lg2",
-        ScalarMathOperation::Rcp => "rcp",
-        ScalarMathOperation::Rsqrt => "rsqrt",
-        ScalarMathOperation::Sqrt => "sqrt",
-        ScalarMathOperation::Tanh => "tanh",
-    }
-}
-
-fn scalar_math_precision_name(precision: ScalarMathPrecision) -> &'static str {
-    match precision {
-        ScalarMathPrecision::Approx => "approx",
-        ScalarMathPrecision::Rn => "rn",
-        ScalarMathPrecision::Rz => "rz",
-        ScalarMathPrecision::Rm => "rm",
-        ScalarMathPrecision::Rp => "rp",
-    }
-}
-
-fn canonical_scalar_math_variants() -> Vec<ScalarMathVariant> {
-    use ScalarMathFormat::{F16, F32, F64};
-    use ScalarMathOperation::{Cos, Ex2, Lg2, Rcp, Rsqrt, Sin, Sqrt, Tanh};
-    use ScalarMathPrecision::{Approx, Rm, Rn, Rp, Rz};
-    use ScalarMathSubnormal::{Ftz, Preserve};
-
-    vec![
-        // sin: approx f32 only
-        (F32, Sin, Approx, Preserve),
-        (F32, Sin, Approx, Ftz),
-        // cos: approx f32 only
-        (F32, Cos, Approx, Preserve),
-        (F32, Cos, Approx, Ftz),
-        // lg2: approx f32 only (f64 approx produces invalid PTX)
-        (F32, Lg2, Approx, Preserve),
-        (F32, Lg2, Approx, Ftz),
-        // rcp: approx only with ftz, rounded for both formats
-        (F32, Rcp, Approx, Ftz),
-        (F32, Rcp, Rn, Preserve),
-        (F32, Rcp, Rn, Ftz),
-        (F32, Rcp, Rz, Preserve),
-        (F32, Rcp, Rz, Ftz),
-        (F32, Rcp, Rm, Preserve),
-        (F32, Rcp, Rm, Ftz),
-        (F32, Rcp, Rp, Preserve),
-        (F32, Rcp, Rp, Ftz),
-        (F64, Rcp, Approx, Ftz),
-        (F64, Rcp, Rn, Preserve),
-        (F64, Rcp, Rz, Preserve),
-        (F64, Rcp, Rm, Preserve),
-        (F64, Rcp, Rp, Preserve),
-        // rsqrt: approx only (PTX has no rounded rsqrt). The f64+ftz variant
-        // is valid PTX (`rsqrt.approx.ftz.f64` assembles for sm_80+, and LLVM
-        // selects `llvm.nvvm.rsqrt.approx.ftz.d` directly); it is deferred
-        // only because it has not been probed under the pinned evidence
-        // profile yet, not because the instruction is invalid.
-        (F32, Rsqrt, Approx, Preserve),
-        (F32, Rsqrt, Approx, Ftz),
-        (F64, Rsqrt, Approx, Preserve),
-        // sqrt: approx f32 only, rounded for both formats
-        (F32, Sqrt, Approx, Preserve),
-        (F32, Sqrt, Approx, Ftz),
-        (F32, Sqrt, Rn, Preserve),
-        (F32, Sqrt, Rn, Ftz),
-        (F32, Sqrt, Rz, Preserve),
-        (F32, Sqrt, Rz, Ftz),
-        (F32, Sqrt, Rm, Preserve),
-        (F32, Sqrt, Rm, Ftz),
-        (F32, Sqrt, Rp, Preserve),
-        (F32, Sqrt, Rp, Ftz),
-        (F64, Sqrt, Rn, Preserve),
-        (F64, Sqrt, Rz, Preserve),
-        (F64, Sqrt, Rm, Preserve),
-        (F64, Sqrt, Rp, Preserve),
-        // ex2: approx f32 only (PTX has no ex2.approx.f64). Appended after
-        // the original 37 so existing ABI ids stay stable.
-        (F32, Ex2, Approx, Preserve),
-        (F32, Ex2, Approx, Ftz),
-        // tanh: approx f32 only; the instruction has no ftz form (PTX ISA
-        // Table 29) and no rounded variants. Hardware floor is sm_75; the
-        // family contract gates it at the attested sm_80 evidence floor.
-        (F32, Tanh, Approx, Preserve),
-        // ex2.approx.f16 starts at PTX 7.0 / sm_75. LLVM 22 rejects the
-        // .ftz.f16 spelling; .ftz.bf16 is a separate PTX 7.8 / sm_90 variant.
-        (F16, Ex2, Approx, Preserve),
-    ]
-}
-
-fn scalar_math_recipe(variant: ScalarMathVariant) -> Option<ScalarMathRecipe> {
-    if !canonical_scalar_math_variants().contains(&variant) {
-        return None;
-    }
-    let (format, operation, precision, subnormal) = variant;
-    let operation_name = scalar_math_operation_name(operation);
-    let precision_name = scalar_math_precision_name(precision);
-    let format_name = scalar_math_format_name(format);
-    let source_format = match format {
-        ScalarMathFormat::F16 => "f16",
-        ScalarMathFormat::F32 => "f",
-        ScalarMathFormat::F64 => "d",
-    };
-
-    let mut modifier_names = vec![precision_name];
-    if subnormal == ScalarMathSubnormal::Ftz {
-        modifier_names.push("ftz");
-    }
-
-    let modifier_id = modifier_names.join("_");
-    let modifier_symbol = modifier_names.join(".");
-    let id = format!("{operation_name}_{modifier_id}_{format_name}");
-    let source = match operation {
-        // LLVM 22 models ex2 as overloaded records without a per-format
-        // suffix (`int_nvvm_ex2_approx{,_ftz}` over anyfloat); bind those
-        // for declaration-level checks and record the concrete f32
-        // instantiation as the resolved symbol.
-        ScalarMathOperation::Ex2 => ScalarMathRecipeSource::ImportedOverloaded {
-            source_record: format!("int_nvvm_{operation_name}_{modifier_id}"),
-            llvm_symbol: format!("llvm.nvvm.{operation_name}.{modifier_symbol}"),
-            resolved_llvm_symbol: format!(
-                "llvm.nvvm.{operation_name}.{modifier_symbol}.{format_name}"
-            ),
-        },
-        // LLVM 22.1.2's tblgen export has no record for tanh at all, so the
-        // op is admitted directly against the PTX instruction.
-        ScalarMathOperation::Tanh => ScalarMathRecipeSource::PtxNative {
-            instruction: format!("{operation_name}.{modifier_symbol}.{format_name}"),
-        },
-        _ => ScalarMathRecipeSource::Imported {
-            source_record: format!("int_nvvm_{operation_name}_{modifier_id}_{source_format}"),
-            llvm_symbol: format!("llvm.nvvm.{operation_name}.{modifier_symbol}.{source_format}"),
-        },
-    };
-    let ptx_modifiers = modifier_names
-        .iter()
-        .copied()
-        .chain(std::iter::once(format_name))
-        .map(str::to_owned)
-        .collect::<Vec<_>>();
-
-    // Operations whose llvm.nvvm.* records carry no *imported* DAG selection
-    // pattern in the pinned evidence (sel=0). llc itself still selects them
-    // (via NVVMIntrinsic-class patterns the tblgen import cannot see), but
-    // the evidence-driven contract only admits typed calls backed by an
-    // imported selection, so these route through inline PTX for now.
-    let force_inline_ptx = matches!(
-        operation,
-        ScalarMathOperation::Sin
-            | ScalarMathOperation::Cos
-            | ScalarMathOperation::Ex2
-            | ScalarMathOperation::Lg2
-            | ScalarMathOperation::Rsqrt
-            | ScalarMathOperation::Tanh
-    );
-
-    let (ptx_isa_section, ptx_isa_url) = match (operation, format) {
-        (ScalarMathOperation::Ex2, ScalarMathFormat::F16) => (
-            "9.7.4.10 Half Precision Floating Point Instructions: ex2",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-ex2",
-        ),
-        (ScalarMathOperation::Sin, _) => (
-            "9.7.3.10 Floating Point Instructions: sin",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-sin",
-        ),
-        (ScalarMathOperation::Cos, _) => (
-            "9.7.3.11 Floating Point Instructions: cos",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-cos",
-        ),
-        (ScalarMathOperation::Lg2, _) => (
-            "9.7.3.12 Floating Point Instructions: lg2",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-lg2",
-        ),
-        (ScalarMathOperation::Rcp, _) => (
-            "9.7.3.7 Floating Point Instructions: rcp",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-rcp",
-        ),
-        (ScalarMathOperation::Rsqrt, _) => (
-            "9.7.3.14 Floating Point Instructions: rsqrt",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-rsqrt",
-        ),
-        (ScalarMathOperation::Sqrt, _) => (
-            "9.7.3.9 Floating Point Instructions: sqrt",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-sqrt",
-        ),
-        (ScalarMathOperation::Ex2, _) => (
-            "9.7.3.13 Floating Point Instructions: ex2",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-ex2",
-        ),
-        (ScalarMathOperation::Tanh, _) => (
-            "9.7.3.15 Floating Point Instructions: tanh",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-tanh",
-        ),
-    };
-
-    let (rust_type, dialect_type, minimum_ptx, minimum_sm) = match format {
-        ScalarMathFormat::F16 => ("u16", "i16", "7.0", "sm_75"),
-        ScalarMathFormat::F32 => ("f32", "f32", "7.0", "sm_80"),
-        ScalarMathFormat::F64 => ("f64", "f64", "7.0", "sm_80"),
-    };
-    Some(ScalarMathRecipe {
-        id,
-        operation_key: format!("scalar.math.{operation_name}.{modifier_symbol}.{format_name}"),
-        source,
-        rust_type,
-        dialect_type,
-        minimum_ptx,
-        minimum_sm,
-        properties: vec!["IntrNoMem"],
-        ptx_modifiers,
-        ptx_isa_section,
-        ptx_isa_url,
-        force_inline_ptx,
-    })
-}
-
-fn expand_scalar_math_admission(admission: &ScalarMathAdmission) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "scalar-math runtime may be marked executed only with GPU evidence"
-    );
-    let expected = canonical_scalar_math_variants();
-    let actual = admission
-        .variants
-        .iter()
-        .map(|variant| {
-            (
-                variant.format,
-                variant.operation,
-                variant.precision,
-                variant.subnormal,
-            )
-        })
-        .collect::<Vec<_>>();
-    ensure!(
-        actual == expected,
-        "compact scalar-math admission must list the canonical 41 variants"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            validate_abi_id(&variant.abi_id)?;
-            let identity = (
-                variant.format,
-                variant.operation,
-                variant.precision,
-                variant.subnormal,
-            );
-            let recipe = scalar_math_recipe(identity)
-                .context("scalar math is outside the closed recipe set")?;
-            let libnvvm_evidence_profile = variant
-                .libnvvm_evidence_profile
-                .as_ref()
-                .unwrap_or(&admission.libnvvm_evidence_profile);
-            ensure!(
-                !libnvvm_evidence_profile.trim().is_empty(),
-                "scalar-math libNVVM evidence profile must not be empty"
-            );
-            scalar_math_overlay_record(
-                recipe,
-                admission,
-                identity,
-                &variant.abi_id,
-                libnvvm_evidence_profile,
-            )
-        })
-        .collect()
-}
-
-fn scalar_math_overlay_record(
-    recipe: ScalarMathRecipe,
-    admission: &ScalarMathAdmission,
-    variant: ScalarMathVariant,
-    abi_id: &str,
-    libnvvm_evidence_profile: &str,
-) -> Result<OverlayIntrinsic> {
-    let (format, operation, precision, subnormal) = variant;
-    let ptx_operands = vec![OperandPattern::Register; 2]; // 1 result + 1 operand
-    let summary = format!(
-        "Computes unary {} with {} precision.",
-        scalar_math_operation_name(operation),
-        scalar_math_precision_name(precision),
-    );
-    let (source, source_record, llvm_symbol, resolved_llvm_symbol, llvm_arguments, llvm_results) =
-        match &recipe.source {
-            ScalarMathRecipeSource::Imported {
-                source_record,
-                llvm_symbol,
-            } => (
-                None,
-                Some(source_record.clone()),
-                Some(llvm_symbol.clone()),
-                None,
-                vec![recipe.rust_type.to_owned()],
-                vec![recipe.rust_type.to_owned()],
-            ),
-            // The polymorphic signature tokens mirror the imported
-            // overloaded record verbatim (anyfloat over anonymous_14), the
-            // same shape packed_alu uses for llvm.nvvm.fabs.
-            ScalarMathRecipeSource::ImportedOverloaded {
-                source_record,
-                llvm_symbol,
-                resolved_llvm_symbol,
-            } => (
-                None,
-                Some(source_record.clone()),
-                Some(llvm_symbol.clone()),
-                Some(resolved_llvm_symbol.clone()),
-                vec!["anonymous_14".to_owned()],
-                vec!["anyfloat".to_owned()],
-            ),
-            ScalarMathRecipeSource::PtxNative { instruction } => (
-                Some(IntrinsicSource::PtxNative {
-                    instruction: instruction.clone(),
-                }),
-                None,
-                None,
-                None,
-                Vec::new(),
-                Vec::new(),
-            ),
-        };
-    Ok(OverlayIntrinsic {
-        id: recipe.id.clone(),
-        abi_id: abi_id.into(),
-        operation_key: recipe.operation_key,
-        family: "scalar_math".into(),
-        source,
-        source_record,
-        rust_module: "float".into(),
-        rust_name: recipe.id.clone(),
-        rust_arguments: vec![recipe.rust_type.into()],
-        rust_result: recipe.rust_type.into(),
-        safe: true,
-        must_use: true,
-        safe_allowlist_reason: Some("Scalar math has no caller obligations.".into()),
-        public_rust_path: format!("cuda_intrinsics::float::{}", recipe.id),
-        compatibility_rust_paths: vec![format!("cuda_device::float::{}", recipe.id)],
-        dialect_op_type: "ScalarMathOp".into(),
-        dialect_op_name: "nvvm.scalar_math".into(),
-        dialect_operands: vec![recipe.dialect_type.into()],
-        dialect_results: vec![recipe.dialect_type.into()],
-        llvm_symbol,
-        resolved_llvm_symbol,
-        llvm_arguments,
-        llvm_results,
-        pure: true,
-        memory: "none".into(),
-        convergent: false,
-        execution_scope: "thread".into(),
-        minimum_ptx: recipe.minimum_ptx.into(),
-        minimum_sm: Some(recipe.minimum_sm.into()),
-        ptx_result: recipe.rust_type.into(),
-        targets: "all".into(),
-        ptx_isa_version: "9.3".into(),
-        ptx_isa_section: recipe.ptx_isa_section.into(),
-        ptx_isa_url: recipe.ptx_isa_url.into(),
-        lowering: "generated_scalar_math".into(),
-        backend_lowerings: [
-            (
-                IntrinsicBackend::LlvmNvptx,
-                admission.llvm_evidence_profile.as_str(),
-            ),
-            (IntrinsicBackend::LibNvvm, libnvvm_evidence_profile),
-        ]
-        .into_iter()
-        .map(
-            |(backend, evidence_profile): (IntrinsicBackend, &str)| OverlayBackendLowering {
-                backend,
-                mechanism: match backend {
-                    IntrinsicBackend::LlvmNvptx if recipe.force_inline_ptx => {
-                        BackendLoweringMechanism::InlinePtx
-                    }
-                    IntrinsicBackend::LlvmNvptx => BackendLoweringMechanism::TypedNvvm,
-                    IntrinsicBackend::LibNvvm => BackendLoweringMechanism::InlinePtx,
-                },
-                evidence_profile: evidence_profile.to_owned(),
-                targets: None,
-                minimum_ptx: Some(recipe.minimum_ptx.into()),
-                minimum_sm: Some(recipe.minimum_sm.into()),
-            },
-        )
-        .collect(),
-        packed_atomic: None,
-        redux: None,
-        vote: None,
-        active_mask: None,
-        warp_match: None,
-        warp_barrier: None,
-        warp_shuffle: None,
-        dot_product: None,
-        packed_alu: None,
-        integer_minmax: None,
-        packed_conversion: None,
-        scalar_conversion: None,
-        scalar_arithmetic: None,
-        scalar_math: Some(ScalarMath {
-            format,
-            operation,
-            precision,
-            subnormal,
-            runtime_validation: admission.runtime_validation,
-        }),
-        extended_minmax: None,
-        cp_async_copy: None,
-        cp_async_control: None,
-        cp_async_mbarrier: None,
-        mbarrier_basic: None,
-        movmatrix: None,
-        mbarrier_extended: None,
-        register_mma: None,
-        sparse_mma: None,
-        prmt: None,
-        cluster_barrier: None,
-        wgmma_control: None,
-        special_register: None,
-        debug_control: None,
-        cluster_memory: None,
-        clc: None,
-        tma: None,
-        tcgen05: None,
-        ldmatrix_variant: None,
-        ldmatrix_safety: None,
-        ldmatrix_adapter: None,
-        selected_address_space: None,
-        expected_ptx: InstructionPattern {
-            mnemonic: scalar_math_operation_name(operation).into(),
-            modifiers: recipe.ptx_modifiers,
-            operands: ptx_operands,
-        },
-        summary,
-    })
-}
-
-fn validate_scalar_math_policy(
-    policy: &OverlayIntrinsic,
-    declaration: Option<&ImportedIntrinsic>,
-) -> Result<()> {
-    let math = policy
-        .scalar_math
-        .as_ref()
-        .with_context(|| format!("{} has no scalar-math contract", policy.id))?;
-    let variant = (math.format, math.operation, math.precision, math.subnormal);
-    let recipe = scalar_math_recipe(variant)
-        .with_context(|| format!("{} is outside the closed scalar-math recipe", policy.id))?;
-    ensure!(
-        math.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} scalar-math runtime may be executed only with GPU evidence",
-        policy.id
-    );
-    let signature = vec![recipe.rust_type.to_owned()];
-    let source_matches = match &recipe.source {
-        ScalarMathRecipeSource::Imported {
-            source_record,
-            llvm_symbol,
-        } => {
-            policy.source.is_none()
-                && policy.source_record.as_deref() == Some(source_record.as_str())
-                && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
-                && policy.resolved_llvm_symbol.is_none()
-                && policy.llvm_arguments == signature
-                && policy.llvm_results == [recipe.rust_type]
-        }
-        ScalarMathRecipeSource::ImportedOverloaded {
-            source_record,
-            llvm_symbol,
-            resolved_llvm_symbol,
-        } => {
-            policy.source.is_none()
-                && policy.source_record.as_deref() == Some(source_record.as_str())
-                && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
-                && policy.resolved_llvm_symbol.as_deref() == Some(resolved_llvm_symbol.as_str())
-                && policy.llvm_arguments == ["anonymous_14"]
-                && policy.llvm_results == ["anyfloat"]
-        }
-        ScalarMathRecipeSource::PtxNative { instruction } => {
-            policy.source
-                == Some(IntrinsicSource::PtxNative {
-                    instruction: instruction.clone(),
-                })
-                && policy.source_record.is_none()
-                && policy.llvm_symbol.is_none()
-                && policy.resolved_llvm_symbol.is_none()
-                && policy.llvm_arguments.is_empty()
-                && policy.llvm_results.is_empty()
-        }
-    };
-    ensure!(
-        policy.id == recipe.id && policy.operation_key == recipe.operation_key && source_matches,
-        "{} scalar-math identity or LLVM source changed",
-        policy.id
-    );
-    ensure!(
-        declaration.is_none() == matches!(recipe.source, ScalarMathRecipeSource::PtxNative { .. }),
-        "{} scalar-math source kind and imported declaration disagree",
-        policy.id
-    );
-    if let Some(declaration) = declaration {
-        let expected_properties = recipe
-            .properties
-            .iter()
-            .map(|property| (*property).to_owned())
-            .collect::<Vec<_>>();
-        ensure!(
-            declaration.properties == expected_properties,
-            "{} imported scalar-math properties changed",
-            policy.id
-        );
-        ensure!(
-            declaration.selections.len() <= 1,
-            "{} gained an unreviewed scalar-math selection",
-            policy.id
-        );
-        if let Some(direct) = declaration.selections.first() {
-            ensure!(
-                direct.predicates.is_empty() && direct.constraints.is_empty(),
-                "{} direct scalar-math selection changed",
-                policy.id
-            );
-        }
-    }
-    ensure!(
-        policy.rust_module == "float"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == signature
-            && policy.rust_result == recipe.rust_type
-            && policy.safe
-            && policy.must_use
-            && policy.compatibility_rust_paths == [format!("cuda_device::float::{}", recipe.id)]
-            && policy.dialect_op_type == "ScalarMathOp"
-            && policy.dialect_op_name == "nvvm.scalar_math"
-            && policy.dialect_operands == [recipe.dialect_type]
-            && policy.dialect_results == [recipe.dialect_type]
-            && policy.lowering == "generated_scalar_math",
-        "{} changed its scalar-math API, carrier, or lowering",
-        policy.id
-    );
-    ensure!(
-        policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
-            && policy.ptx_result == recipe.rust_type
-            && policy.targets == "all"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.ptx_isa_section
-            && policy.ptx_isa_url == recipe.ptx_isa_url,
-        "{} scalar-math effects, provenance, or target floor changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx
-            == InstructionPattern {
-                mnemonic: scalar_math_operation_name(math.operation).into(),
-                modifiers: recipe.ptx_modifiers.clone(),
-                operands: vec![OperandPattern::Register; 2],
-            },
-        "{} expected scalar-math PTX changed",
-        policy.id
-    );
-    let llvm_mechanism = if recipe.force_inline_ptx {
-        BackendLoweringMechanism::InlinePtx
-    } else {
-        BackendLoweringMechanism::TypedNvvm
-    };
-    let expected_backends = [
-        (
-            IntrinsicBackend::LlvmNvptx,
-            llvm_mechanism,
-            recipe.minimum_sm,
-        ),
-        (
-            IntrinsicBackend::LibNvvm,
-            BackendLoweringMechanism::InlinePtx,
-            recipe.minimum_sm,
-        ),
-    ];
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && expected_backends
-                .into_iter()
-                .all(|(backend, mechanism, minimum_sm)| {
-                    policy.backend_lowerings.iter().any(|lowering| {
-                        lowering.backend == backend
-                            && lowering.mechanism == mechanism
-                            && lowering.minimum_ptx.as_deref() == Some(recipe.minimum_ptx)
-                            && lowering.minimum_sm.as_deref() == Some(minimum_sm)
-                            && !lowering.evidence_profile.trim().is_empty()
-                    })
-                }),
-        "{} has the wrong reviewed scalar-math backend routes (expected {} / {})",
-        policy.id,
-        recipe.minimum_ptx,
-        recipe.minimum_sm
-    );
-    if let Some(direct) = declaration.and_then(|declaration| declaration.selections.first()) {
-        validate_selected_target_predicates(policy, direct)?;
-    }
-    ensure_no_other_family_contract(policy, "scalar math")?;
-    Ok(())
-}
-
-type ExtendedMinMaxVariant = (
-    ExtendedMinMaxFormat,
-    ExtendedMinMaxOperation,
-    ExtendedMinMaxSubnormal,
-    ExtendedMinMaxNan,
-    bool,
-);
-
-struct ExtendedMinMaxRecipe {
-    id: String,
-    operation_key: String,
-    source_record: String,
-    llvm_symbol: String,
-    llvm_type: &'static str,
-    rust_module: &'static str,
-    rust_type: &'static str,
-    dialect_type: &'static str,
-    adapter: ExtendedMinMaxAdapter,
-    selection_record: String,
-    selection_asm: String,
-    predicates: Vec<String>,
-    classes: Vec<&'static str>,
-    modifiers: Vec<String>,
-    minimum_ptx: &'static str,
-    minimum_sm: &'static str,
-    ptx_isa_section: &'static str,
-    ptx_isa_url: &'static str,
-}
-
-fn canonical_extended_minmax_variants() -> Vec<ExtendedMinMaxVariant> {
-    use ExtendedMinMaxFormat::{Bf16, Bf16x2, F16, F16x2, F32};
-    use ExtendedMinMaxNan::{Nan, Number};
-    use ExtendedMinMaxOperation::{Max, Min};
-    use ExtendedMinMaxSubnormal::{Ftz, Preserve};
-
-    let one_operation = |operation| {
-        [
-            (F16x2, operation, Ftz, Number, false),
-            (F16x2, operation, Ftz, Nan, false),
-            (F32, operation, Ftz, Nan, true),
-            (F16x2, operation, Ftz, Nan, true),
-            (F32, operation, Ftz, Number, true),
-            (F16x2, operation, Ftz, Number, true),
-            (Bf16x2, operation, Preserve, Nan, false),
-            (F16x2, operation, Preserve, Nan, false),
-            (Bf16x2, operation, Preserve, Nan, true),
-            (F32, operation, Preserve, Nan, true),
-            (F16x2, operation, Preserve, Nan, true),
-            (Bf16x2, operation, Preserve, Number, true),
-            (F32, operation, Preserve, Number, true),
-            (F16x2, operation, Preserve, Number, true),
-        ]
-    };
-    // The scalar 16-bit forms. LLVM declares every `f16` modifier combination
-    // and the four `bf16` combinations that do not request `ftz`; the four
-    // `bf16` `ftz` declarations exist but have no NVPTX selection pattern and
-    // fail instruction selection, so they are deliberately absent here.
-    //
-    // ABI identity is intentionally absent from this canonical list. Existing
-    // and future IDs are carried by admission entries and enforced by the
-    // global append-only ABI ledger.
-    let scalar_halves = |operation| {
-        [
-            (F16, operation, Preserve, Number, false),
-            (F16, operation, Ftz, Number, false),
-            (F16, operation, Preserve, Nan, false),
-            (F16, operation, Ftz, Nan, false),
-            (F16, operation, Preserve, Number, true),
-            (F16, operation, Ftz, Number, true),
-            (F16, operation, Preserve, Nan, true),
-            (F16, operation, Ftz, Nan, true),
-            (Bf16, operation, Preserve, Number, false),
-            (Bf16, operation, Preserve, Nan, false),
-            (Bf16, operation, Preserve, Number, true),
-            (Bf16, operation, Preserve, Nan, true),
-        ]
-    };
-    one_operation(Min)
-        .into_iter()
-        .chain(one_operation(Max))
-        .chain(scalar_halves(Min))
-        .chain(scalar_halves(Max))
-        .collect()
-}
-
-/// Joins an operation name, its modifiers, and its format into one identifier.
-///
-/// `min.f16` and `min.bf16` carry no modifier at all, so the separators have to
-/// come from joining the parts that are present rather than from a format
-/// string with fixed separators.
-fn extended_minmax_joined_name(
-    leading: &str,
-    trailing: &str,
-    modifiers: &[&str],
-    separator: &str,
-) -> String {
-    let mut parts = vec![leading];
-    parts.extend(modifiers.iter().copied());
-    parts.push(trailing);
-    parts.join(separator)
-}
-
-fn extended_minmax_format_name(format: ExtendedMinMaxFormat) -> &'static str {
-    match format {
-        ExtendedMinMaxFormat::F32 => "f32",
-        ExtendedMinMaxFormat::F16 => "f16",
-        ExtendedMinMaxFormat::Bf16 => "bf16",
-        ExtendedMinMaxFormat::F16x2 => "f16x2",
-        ExtendedMinMaxFormat::Bf16x2 => "bf16x2",
-    }
-}
-
-fn extended_minmax_operation_name(operation: ExtendedMinMaxOperation) -> &'static str {
-    match operation {
-        ExtendedMinMaxOperation::Min => "min",
-        ExtendedMinMaxOperation::Max => "max",
-    }
-}
-
-fn extended_minmax_recipe(variant: ExtendedMinMaxVariant) -> Option<ExtendedMinMaxRecipe> {
-    if !canonical_extended_minmax_variants().contains(&variant) {
-        return None;
-    }
-    let (format, operation, subnormal, nan, xorsign_abs) = variant;
-    let operation_name = extended_minmax_operation_name(operation);
-    let format_name = extended_minmax_format_name(format);
-    let source_type = if format == ExtendedMinMaxFormat::F32 {
-        "f"
-    } else {
-        format_name
-    };
-    let mut source_modifiers = Vec::new();
-    let mut ptx_modifiers = Vec::new();
-    if subnormal == ExtendedMinMaxSubnormal::Ftz {
-        source_modifiers.push("ftz");
-        ptx_modifiers.push("ftz".to_owned());
-    }
-    if nan == ExtendedMinMaxNan::Nan {
-        source_modifiers.push("nan");
-        ptx_modifiers.push("NaN".to_owned());
-    }
-    if xorsign_abs {
-        source_modifiers.extend(["xorsign", "abs"]);
-        ptx_modifiers.extend(["xorsign".to_owned(), "abs".to_owned()]);
-    }
-    let id = extended_minmax_joined_name(operation_name, format_name, &source_modifiers, "_");
-    let intrinsic_name = format!("f{operation_name}");
-    let source_record = format!(
-        "int_nvvm_{}",
-        extended_minmax_joined_name(&intrinsic_name, source_type, &source_modifiers, "_")
-    );
-    let llvm_symbol = format!(
-        "llvm.nvvm.{}",
-        extended_minmax_joined_name(&intrinsic_name, source_type, &source_modifiers, ".")
-    );
-    let selection_record = if format == ExtendedMinMaxFormat::F32 {
-        format!(
-            "INT_NVVM_{}",
-            source_record
-                .trim_start_matches("int_nvvm_")
-                .to_ascii_uppercase()
-        )
-    } else {
-        let prefix = match operation {
-            ExtendedMinMaxOperation::Min => "FMIN",
-            ExtendedMinMaxOperation::Max => "FMAN",
-        };
-        let selection_modifiers = source_modifiers
-            .iter()
-            .map(|modifier| if *modifier == "nan" { "NaN" } else { modifier })
-            .collect::<Vec<_>>();
-        format!(
-            "INT_NVVM_{}",
-            extended_minmax_joined_name(prefix, format_name, &selection_modifiers, "_")
-        )
-    };
-    let ptx_format = if format == ExtendedMinMaxFormat::F32 {
-        "f32"
-    } else {
-        format_name
-    };
-    ptx_modifiers.push(ptx_format.to_owned());
-    let selection_asm = format!(
-        "{operation_name}.{} \t$dst, $src0, $src1;",
-        ptx_modifiers.join(".")
-    );
-    let (minimum_ptx, minimum_sm, predicates) = if xorsign_abs {
-        (
-            "7.2",
-            "sm_86",
-            vec![
-                "Subtarget->getPTXVersion() >= 72".to_owned(),
-                "Subtarget->getSmVersion() >= 86".to_owned(),
-            ],
-        )
-    } else {
-        (
-            "7.0",
-            "sm_80",
-            vec![
-                "Subtarget->getSmVersion() >= 80".to_owned(),
-                "Subtarget->getPTXVersion() >= 70".to_owned(),
-            ],
-        )
-    };
-    let (llvm_type, rust_module, rust_type, dialect_type, adapter, classes) = match format {
-        ExtendedMinMaxFormat::F32 => (
-            "f32",
-            "float",
-            "f32",
-            "f32",
-            ExtendedMinMaxAdapter::DirectF32,
-            vec![
-                "ClangBuiltin",
-                "NVVMBuiltin",
-                "SDPatternOperator",
-                "Intrinsic",
-                "DefaultAttrsIntrinsic",
-            ],
-        ),
-        ExtendedMinMaxFormat::F16 => (
-            "f16",
-            "f16",
-            "u16",
-            "i16",
-            ExtendedMinMaxAdapter::DirectHalfU16,
-            vec!["SDPatternOperator", "Intrinsic", "DefaultAttrsIntrinsic"],
-        ),
-        ExtendedMinMaxFormat::Bf16 => (
-            "bf16",
-            "bf16",
-            "u16",
-            "i16",
-            ExtendedMinMaxAdapter::DirectHalfU16,
-            vec![
-                "ClangBuiltin",
-                "NVVMBuiltin",
-                "SDPatternOperator",
-                "Intrinsic",
-                "DefaultAttrsIntrinsic",
-            ],
-        ),
-        ExtendedMinMaxFormat::F16x2 => (
-            "v2f16",
-            "f16x2",
-            "u32",
-            "i32",
-            ExtendedMinMaxAdapter::DirectPackedU32,
-            vec!["SDPatternOperator", "Intrinsic", "DefaultAttrsIntrinsic"],
-        ),
-        ExtendedMinMaxFormat::Bf16x2 => (
-            "v2bf16",
-            "bf16x2",
-            "u32",
-            "i32",
-            ExtendedMinMaxAdapter::DirectPackedU32,
-            vec![
-                "ClangBuiltin",
-                "NVVMBuiltin",
-                "SDPatternOperator",
-                "Intrinsic",
-                "DefaultAttrsIntrinsic",
-            ],
-        ),
-    };
-    let (ptx_isa_section, ptx_isa_url) = match (format, operation) {
-        (ExtendedMinMaxFormat::F32, ExtendedMinMaxOperation::Min) => (
-            "9.7.3.9 Floating Point Instructions: min",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-min",
-        ),
-        (ExtendedMinMaxFormat::F32, ExtendedMinMaxOperation::Max) => (
-            "9.7.3.10 Floating Point Instructions: max",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-max",
-        ),
-        (_, ExtendedMinMaxOperation::Min) => (
-            "9.7.4.7 Half Precision Floating Point Instructions: min",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-min",
-        ),
-        (_, ExtendedMinMaxOperation::Max) => (
-            "9.7.4.8 Half Precision Floating Point Instructions: max",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-max",
-        ),
-    };
-    Some(ExtendedMinMaxRecipe {
-        id,
-        operation_key: format!(
-            "floating.minmax.{format_name}.{operation_name}.{}.{}.{}",
-            match subnormal {
-                ExtendedMinMaxSubnormal::Preserve => "preserve",
-                ExtendedMinMaxSubnormal::Ftz => "ftz",
-            },
-            match nan {
-                ExtendedMinMaxNan::Number => "number",
-                ExtendedMinMaxNan::Nan => "nan",
-            },
-            if xorsign_abs { "xorsign_abs" } else { "direct" }
-        ),
-        source_record,
-        llvm_symbol,
-        llvm_type,
-        rust_module,
-        rust_type,
-        dialect_type,
-        adapter,
-        selection_record,
-        selection_asm,
-        predicates,
-        classes,
-        modifiers: ptx_modifiers,
-        minimum_ptx,
-        minimum_sm,
-        ptx_isa_section,
-        ptx_isa_url,
-    })
-}
-
-fn expand_extended_minmax_admission(
-    admission: &ExtendedMinMaxAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "extended-minmax runtime may be marked executed only with GPU evidence"
-    );
-    let expected = canonical_extended_minmax_variants();
-    let actual = admission
-        .variants
-        .iter()
-        .map(|variant| {
-            (
-                variant.format,
-                variant.operation,
-                variant.subnormal,
-                variant.nan,
-                variant.xorsign_abs,
-            )
-        })
-        .collect::<Vec<_>>();
-    ensure!(
-        actual == expected,
-        "compact extended-minmax admission must list the exact canonical 28 variants"
-    );
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            validate_abi_id(&variant.abi_id)?;
-            let identity = (
-                variant.format,
-                variant.operation,
-                variant.subnormal,
-                variant.nan,
-                variant.xorsign_abs,
-            );
-            let recipe = extended_minmax_recipe(identity)
-                .context("extended min/max is outside the closed recipe set")?;
-            extended_minmax_overlay_record(recipe, admission, identity, &variant.abi_id)
-        })
-        .collect()
-}
-
-fn extended_minmax_overlay_record(
-    recipe: ExtendedMinMaxRecipe,
-    admission: &ExtendedMinMaxAdmission,
-    variant: ExtendedMinMaxVariant,
-    abi_id: &str,
-) -> Result<OverlayIntrinsic> {
-    let (format, operation, subnormal, nan, xorsign_abs) = variant;
-    let rust_arguments = vec![recipe.rust_type.to_owned(); 2];
-    let dialect_operands = vec![recipe.dialect_type.to_owned(); 2];
-    Ok(OverlayIntrinsic {
-        id: recipe.id.clone(),
-        abi_id: abi_id.into(),
-        operation_key: recipe.operation_key,
-        family: "extended_minmax".into(),
-        source: None,
-        source_record: Some(recipe.source_record),
-        rust_module: recipe.rust_module.into(),
-        rust_name: recipe.id.clone(),
-        rust_arguments: rust_arguments.clone(),
-        rust_result: recipe.rust_type.into(),
-        safe: true,
-        must_use: true,
-        safe_allowlist_reason: Some("Floating-point min/max has no caller obligations.".into()),
-        public_rust_path: format!("cuda_intrinsics::{}::{}", recipe.rust_module, recipe.id),
-        compatibility_rust_paths: vec![format!(
-            "cuda_device::{}::{}",
-            recipe.rust_module, recipe.id
-        )],
-        dialect_op_type: "ExtendedMinMaxOp".into(),
-        dialect_op_name: "nvvm.extended_minmax".into(),
-        dialect_operands: dialect_operands.clone(),
-        dialect_results: vec![recipe.dialect_type.into()],
-        llvm_symbol: Some(recipe.llvm_symbol),
-        resolved_llvm_symbol: None,
-        llvm_arguments: vec![recipe.llvm_type.into(); 2],
-        llvm_results: vec![recipe.llvm_type.into()],
-        pure: true,
-        memory: "none".into(),
-        convergent: false,
-        execution_scope: "thread".into(),
-        minimum_ptx: recipe.minimum_ptx.into(),
-        minimum_sm: Some(recipe.minimum_sm.into()),
-        ptx_result: recipe.rust_type.into(),
-        targets: "all".into(),
-        ptx_isa_version: "9.3".into(),
-        ptx_isa_section: recipe.ptx_isa_section.into(),
-        ptx_isa_url: recipe.ptx_isa_url.into(),
-        lowering: "generated_extended_minmax".into(),
-        backend_lowerings: [
-            (
-                IntrinsicBackend::LlvmNvptx,
-                &admission.llvm_evidence_profile,
-            ),
-            (
-                IntrinsicBackend::LibNvvm,
-                &admission.libnvvm_evidence_profile,
-            ),
-        ]
-        .into_iter()
-        .map(|(backend, evidence_profile)| OverlayBackendLowering {
-            backend,
-            mechanism: BackendLoweringMechanism::InlinePtx,
-            evidence_profile: evidence_profile.clone(),
-            targets: None,
-            minimum_ptx: Some(recipe.minimum_ptx.into()),
-            minimum_sm: Some(recipe.minimum_sm.into()),
-        })
-        .collect(),
-        packed_atomic: None,
-        redux: None,
-        vote: None,
-        active_mask: None,
-        warp_match: None,
-        warp_barrier: None,
-        warp_shuffle: None,
-        dot_product: None,
-        packed_alu: None,
-        integer_minmax: None,
-        packed_conversion: None,
-        scalar_conversion: None,
-        scalar_arithmetic: None,
-        scalar_math: None,
-        extended_minmax: Some(ExtendedMinMax {
-            format,
-            operation,
-            subnormal,
-            nan,
-            xorsign_abs,
-            adapter: recipe.adapter,
-            runtime_validation: admission.runtime_validation,
-        }),
-        cp_async_copy: None,
-        cp_async_control: None,
-        cp_async_mbarrier: None,
-        mbarrier_basic: None,
-        movmatrix: None,
-        mbarrier_extended: None,
-        register_mma: None,
-        sparse_mma: None,
-        prmt: None,
-        cluster_barrier: None,
-        wgmma_control: None,
-        special_register: None,
-        debug_control: None,
-        cluster_memory: None,
-        clc: None,
-        tma: None,
-        tcgen05: None,
-        ldmatrix_variant: None,
-        ldmatrix_safety: None,
-        ldmatrix_adapter: None,
-        selected_address_space: None,
-        expected_ptx: InstructionPattern {
-            mnemonic: extended_minmax_operation_name(operation).into(),
-            modifiers: recipe.modifiers,
-            operands: vec![OperandPattern::Register; 3],
-        },
-        summary: format!(
-            "Computes extended {} for {} values.",
-            extended_minmax_operation_name(operation),
-            extended_minmax_format_name(format)
-        ),
-    })
-}
-
-fn validate_extended_minmax_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let minmax = policy
-        .extended_minmax
-        .as_ref()
-        .with_context(|| format!("{} has no extended-minmax contract", policy.id))?;
-    let identity = (
-        minmax.format,
-        minmax.operation,
-        minmax.subnormal,
-        minmax.nan,
-        minmax.xorsign_abs,
-    );
-    let recipe = extended_minmax_recipe(identity)
-        .with_context(|| format!("{} is outside the closed extended-minmax recipe", policy.id))?;
-    ensure!(
-        minmax.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} extended-minmax runtime may be executed only with GPU evidence",
-        policy.id
-    );
-    let expected_adapter = match minmax.format {
-        ExtendedMinMaxFormat::F32 => ExtendedMinMaxAdapter::DirectF32,
-        ExtendedMinMaxFormat::F16 | ExtendedMinMaxFormat::Bf16 => {
-            ExtendedMinMaxAdapter::DirectHalfU16
-        }
-        ExtendedMinMaxFormat::F16x2 | ExtendedMinMaxFormat::Bf16x2 => {
-            ExtendedMinMaxAdapter::DirectPackedU32
-        }
-    };
-    ensure!(
-        minmax.adapter == expected_adapter,
-        "{} extended-minmax adapter does not match its format",
-        policy.id
-    );
-    ensure!(
-        policy.id == recipe.id
-            && policy.operation_key == recipe.operation_key
-            && policy.source_record.as_deref() == Some(recipe.source_record.as_str())
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none()
-            && policy.llvm_arguments == vec![recipe.llvm_type; 2]
-            && policy.llvm_results == [recipe.llvm_type],
-        "{} extended-minmax identity or LLVM source changed",
-        policy.id
-    );
-    ensure!(
-        declaration.classes == recipe.classes
-            && declaration.properties == ["Commutative", "IntrNoMem", "IntrSpeculatable"]
-            && declaration.selections.len() == 1,
-        "{} imported extended-minmax classes, properties, or selection count changed",
-        policy.id
-    );
-    let selection = &declaration.selections[0];
-    ensure!(
-        selection.source_record == recipe.selection_record
-            && selection.asm == recipe.selection_asm
-            && selection.predicates == recipe.predicates
-            && selection.constraints.is_empty(),
-        "{} imported extended-minmax instruction selection changed",
-        policy.id
-    );
-    let rust_arguments = vec![recipe.rust_type; 2];
-    let dialect_operands = vec![recipe.dialect_type; 2];
-    ensure!(
-        policy.rust_module == recipe.rust_module
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == rust_arguments
-            && policy.rust_result == recipe.rust_type
-            && policy.safe
-            && policy.must_use
-            && policy.public_rust_path
-                == format!("cuda_intrinsics::{}::{}", recipe.rust_module, recipe.id)
-            && policy.compatibility_rust_paths
-                == [format!(
-                    "cuda_device::{}::{}",
-                    recipe.rust_module, recipe.id
-                )]
-            && policy.dialect_op_type == "ExtendedMinMaxOp"
-            && policy.dialect_op_name == "nvvm.extended_minmax"
-            && policy.dialect_operands == dialect_operands
-            && policy.dialect_results == [recipe.dialect_type]
-            && policy.lowering == "generated_extended_minmax",
-        "{} changed its extended-minmax API, carrier, or lowering",
-        policy.id
-    );
-    ensure!(
-        policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
-            && policy.ptx_result == recipe.rust_type
-            && policy.targets == "all"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.ptx_isa_section
-            && policy.ptx_isa_url == recipe.ptx_isa_url,
-        "{} extended-minmax effects, provenance, or target floor changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx
-            == InstructionPattern {
-                mnemonic: extended_minmax_operation_name(minmax.operation).into(),
-                modifiers: recipe.modifiers,
-                operands: vec![OperandPattern::Register; 3],
-            },
-        "{} expected extended-minmax PTX changed",
-        policy.id
-    );
-    ensure_exact_inline_ptx_backends(
-        policy,
-        [
-            (
-                IntrinsicBackend::LlvmNvptx,
-                recipe.minimum_ptx,
-                Some(recipe.minimum_sm),
-            ),
-            (
-                IntrinsicBackend::LibNvvm,
-                recipe.minimum_ptx,
-                Some(recipe.minimum_sm),
-            ),
-        ],
-        "extended-minmax",
-    )?;
-    validate_selected_target_predicates(policy, selection)?;
-    ensure_no_other_family_contract(policy, "extended min/max")?;
-    Ok(())
-}
-
-struct RegisterMmaRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    rust_arguments: &'static [&'static str],
-    rust_result: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    dialect_operands: &'static [&'static str],
-    dialect_results: &'static [&'static str],
-    llvm_arguments: &'static [&'static str],
-    llvm_results: &'static [&'static str],
-    adapter: RegisterMmaAdapter,
-    compatibility_source: RegisterMmaCompatibilitySource,
-    minimum_ptx: &'static str,
-    minimum_sm: &'static str,
-    ptx_modifiers: Vec<&'static str>,
-    ptx_register_counts: [usize; 4],
-}
-
-fn integer_register_mma_recipe(mma: &RegisterMma, common: bool) -> Option<RegisterMmaRecipe> {
-    use RegisterMmaAdapter::{
-        C2I32A1U32B1U32ToD2I32, C4I32A2U32B1U32ToD4I32, C4I32A4U32B2U32ToD4I32,
-    };
-    use RegisterMmaCompatibilitySource::{ExistingStub, GeneratedStub};
-    use RegisterMmaElement::{S4, S8, U4, U8};
-    use RegisterMmaOverflow::{Satfinite, Wrapping};
-    use RegisterMmaShape::{M8n8k16, M8n8k32, M16n8k16, M16n8k32, M16n8k64};
-
-    if !common
-        || mma.operation != RegisterMmaOperation::Multiply
-        || mma.accumulator != RegisterMmaAccumulator::S32
-    {
-        return None;
-    }
-
-    let (id, abi_id, operation_key, source_record, llvm_symbol, compatibility_source) =
-        match (mma.shape, mma.a_element, mma.b_element, mma.overflow) {
-            (M16n8k32, S8, S8, Wrapping) => (
-                "mma_m16n8k32_s32_s8",
-                "i0108",
-                "matrix.mma.m16n8k32.row.col.s32.s8.s8.s32.wrapping",
-                "int_nvvm_mma_m16n8k32_row_col_s8",
-                "llvm.nvvm.mma.m16n8k32.row.col.s8",
-                ExistingStub,
-            ),
-            (M16n8k16, S8, S8, Wrapping) => (
-                "mma_m16n8k16_s32_s8",
-                "i0110",
-                "matrix.mma.m16n8k16.row.col.s32.s8.s8.s32.wrapping",
-                "int_nvvm_mma_m16n8k16_row_col_s8",
-                "llvm.nvvm.mma.m16n8k16.row.col.s8",
-                GeneratedStub,
-            ),
-            (M16n8k16, S8, U8, Wrapping) => (
-                "mma_m16n8k16_s32_s8_u8",
-                "i0111",
-                "matrix.mma.m16n8k16.row.col.s32.s8.u8.s32.wrapping",
-                "int_nvvm_mma_m16n8k16_row_col_s8_u8",
-                "llvm.nvvm.mma.m16n8k16.row.col.s8.u8",
-                GeneratedStub,
-            ),
-            (M16n8k16, U8, U8, Wrapping) => (
-                "mma_m16n8k16_s32_u8",
-                "i0112",
-                "matrix.mma.m16n8k16.row.col.s32.u8.u8.s32.wrapping",
-                "int_nvvm_mma_m16n8k16_row_col_u8",
-                "llvm.nvvm.mma.m16n8k16.row.col.u8",
-                GeneratedStub,
-            ),
-            (M16n8k16, U8, S8, Wrapping) => (
-                "mma_m16n8k16_s32_u8_s8",
-                "i0113",
-                "matrix.mma.m16n8k16.row.col.s32.u8.s8.s32.wrapping",
-                "int_nvvm_mma_m16n8k16_row_col_u8_s8",
-                "llvm.nvvm.mma.m16n8k16.row.col.u8.s8",
-                GeneratedStub,
-            ),
-            (M16n8k32, S8, U8, Wrapping) => (
-                "mma_m16n8k32_s32_s8_u8",
-                "i0114",
-                "matrix.mma.m16n8k32.row.col.s32.s8.u8.s32.wrapping",
-                "int_nvvm_mma_m16n8k32_row_col_s8_u8",
-                "llvm.nvvm.mma.m16n8k32.row.col.s8.u8",
-                GeneratedStub,
-            ),
-            (M16n8k32, U8, U8, Wrapping) => (
-                "mma_m16n8k32_s32_u8",
-                "i0115",
-                "matrix.mma.m16n8k32.row.col.s32.u8.u8.s32.wrapping",
-                "int_nvvm_mma_m16n8k32_row_col_u8",
-                "llvm.nvvm.mma.m16n8k32.row.col.u8",
-                GeneratedStub,
-            ),
-            (M16n8k32, U8, S8, Wrapping) => (
-                "mma_m16n8k32_s32_u8_s8",
-                "i0116",
-                "matrix.mma.m16n8k32.row.col.s32.u8.s8.s32.wrapping",
-                "int_nvvm_mma_m16n8k32_row_col_u8_s8",
-                "llvm.nvvm.mma.m16n8k32.row.col.u8.s8",
-                GeneratedStub,
-            ),
-            (M16n8k16, S8, S8, Satfinite) => (
-                "mma_m16n8k16_s32_s8_satfinite",
-                "i0117",
-                "matrix.mma.m16n8k16.row.col.s32.s8.s8.s32.satfinite",
-                "int_nvvm_mma_m16n8k16_row_col_satfinite_s8",
-                "llvm.nvvm.mma.m16n8k16.row.col.satfinite.s8",
-                GeneratedStub,
-            ),
-            (M16n8k16, S8, U8, Satfinite) => (
-                "mma_m16n8k16_s32_s8_u8_satfinite",
-                "i0118",
-                "matrix.mma.m16n8k16.row.col.s32.s8.u8.s32.satfinite",
-                "int_nvvm_mma_m16n8k16_row_col_satfinite_s8_u8",
-                "llvm.nvvm.mma.m16n8k16.row.col.satfinite.s8.u8",
-                GeneratedStub,
-            ),
-            (M16n8k16, U8, U8, Satfinite) => (
-                "mma_m16n8k16_s32_u8_satfinite",
-                "i0119",
-                "matrix.mma.m16n8k16.row.col.s32.u8.u8.s32.satfinite",
-                "int_nvvm_mma_m16n8k16_row_col_satfinite_u8",
-                "llvm.nvvm.mma.m16n8k16.row.col.satfinite.u8",
-                GeneratedStub,
-            ),
-            (M16n8k16, U8, S8, Satfinite) => (
-                "mma_m16n8k16_s32_u8_s8_satfinite",
-                "i0120",
-                "matrix.mma.m16n8k16.row.col.s32.u8.s8.s32.satfinite",
-                "int_nvvm_mma_m16n8k16_row_col_satfinite_u8_s8",
-                "llvm.nvvm.mma.m16n8k16.row.col.satfinite.u8.s8",
-                GeneratedStub,
-            ),
-            (M16n8k32, S8, S8, Satfinite) => (
-                "mma_m16n8k32_s32_s8_satfinite",
-                "i0121",
-                "matrix.mma.m16n8k32.row.col.s32.s8.s8.s32.satfinite",
-                "int_nvvm_mma_m16n8k32_row_col_satfinite_s8",
-                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.s8",
-                GeneratedStub,
-            ),
-            (M16n8k32, S8, U8, Satfinite) => (
-                "mma_m16n8k32_s32_s8_u8_satfinite",
-                "i0122",
-                "matrix.mma.m16n8k32.row.col.s32.s8.u8.s32.satfinite",
-                "int_nvvm_mma_m16n8k32_row_col_satfinite_s8_u8",
-                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.s8.u8",
-                GeneratedStub,
-            ),
-            (M16n8k32, U8, U8, Satfinite) => (
-                "mma_m16n8k32_s32_u8_satfinite",
-                "i0123",
-                "matrix.mma.m16n8k32.row.col.s32.u8.u8.s32.satfinite",
-                "int_nvvm_mma_m16n8k32_row_col_satfinite_u8",
-                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.u8",
-                GeneratedStub,
-            ),
-            (M16n8k32, U8, S8, Satfinite) => (
-                "mma_m16n8k32_s32_u8_s8_satfinite",
-                "i0124",
-                "matrix.mma.m16n8k32.row.col.s32.u8.s8.s32.satfinite",
-                "int_nvvm_mma_m16n8k32_row_col_satfinite_u8_s8",
-                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.u8.s8",
-                GeneratedStub,
-            ),
-            (M8n8k16, S8, S8, Wrapping) => (
-                "mma_m8n8k16_s32_s8",
-                "i0125",
-                "matrix.mma.m8n8k16.row.col.s32.s8.s8.s32.wrapping",
-                "int_nvvm_mma_m8n8k16_row_col_s8",
-                "llvm.nvvm.mma.m8n8k16.row.col.s8",
-                GeneratedStub,
-            ),
-            (M8n8k16, S8, U8, Wrapping) => (
-                "mma_m8n8k16_s32_s8_u8",
-                "i0126",
-                "matrix.mma.m8n8k16.row.col.s32.s8.u8.s32.wrapping",
-                "int_nvvm_mma_m8n8k16_row_col_s8_u8",
-                "llvm.nvvm.mma.m8n8k16.row.col.s8.u8",
-                GeneratedStub,
-            ),
-            (M8n8k16, U8, U8, Wrapping) => (
-                "mma_m8n8k16_s32_u8",
-                "i0127",
-                "matrix.mma.m8n8k16.row.col.s32.u8.u8.s32.wrapping",
-                "int_nvvm_mma_m8n8k16_row_col_u8",
-                "llvm.nvvm.mma.m8n8k16.row.col.u8",
-                GeneratedStub,
-            ),
-            (M8n8k16, U8, S8, Wrapping) => (
-                "mma_m8n8k16_s32_u8_s8",
-                "i0128",
-                "matrix.mma.m8n8k16.row.col.s32.u8.s8.s32.wrapping",
-                "int_nvvm_mma_m8n8k16_row_col_u8_s8",
-                "llvm.nvvm.mma.m8n8k16.row.col.u8.s8",
-                GeneratedStub,
-            ),
-            (M8n8k16, S8, S8, Satfinite) => (
-                "mma_m8n8k16_s32_s8_satfinite",
-                "i0129",
-                "matrix.mma.m8n8k16.row.col.s32.s8.s8.s32.satfinite",
-                "int_nvvm_mma_m8n8k16_row_col_satfinite_s8",
-                "llvm.nvvm.mma.m8n8k16.row.col.satfinite.s8",
-                GeneratedStub,
-            ),
-            (M8n8k16, S8, U8, Satfinite) => (
-                "mma_m8n8k16_s32_s8_u8_satfinite",
-                "i0130",
-                "matrix.mma.m8n8k16.row.col.s32.s8.u8.s32.satfinite",
-                "int_nvvm_mma_m8n8k16_row_col_satfinite_s8_u8",
-                "llvm.nvvm.mma.m8n8k16.row.col.satfinite.s8.u8",
-                GeneratedStub,
-            ),
-            (M8n8k16, U8, U8, Satfinite) => (
-                "mma_m8n8k16_s32_u8_satfinite",
-                "i0131",
-                "matrix.mma.m8n8k16.row.col.s32.u8.u8.s32.satfinite",
-                "int_nvvm_mma_m8n8k16_row_col_satfinite_u8",
-                "llvm.nvvm.mma.m8n8k16.row.col.satfinite.u8",
-                GeneratedStub,
-            ),
-            (M8n8k16, U8, S8, Satfinite) => (
-                "mma_m8n8k16_s32_u8_s8_satfinite",
-                "i0132",
-                "matrix.mma.m8n8k16.row.col.s32.u8.s8.s32.satfinite",
-                "int_nvvm_mma_m8n8k16_row_col_satfinite_u8_s8",
-                "llvm.nvvm.mma.m8n8k16.row.col.satfinite.u8.s8",
-                GeneratedStub,
-            ),
-            (M8n8k32, S4, S4, Wrapping) => (
-                "mma_m8n8k32_s32_s4",
-                "i0133",
-                "matrix.mma.m8n8k32.row.col.s32.s4.s4.s32.wrapping",
-                "int_nvvm_mma_m8n8k32_row_col_s4",
-                "llvm.nvvm.mma.m8n8k32.row.col.s4",
-                GeneratedStub,
-            ),
-            (M8n8k32, S4, U4, Wrapping) => (
-                "mma_m8n8k32_s32_s4_u4",
-                "i0134",
-                "matrix.mma.m8n8k32.row.col.s32.s4.u4.s32.wrapping",
-                "int_nvvm_mma_m8n8k32_row_col_s4_u4",
-                "llvm.nvvm.mma.m8n8k32.row.col.s4.u4",
-                GeneratedStub,
-            ),
-            (M8n8k32, U4, U4, Wrapping) => (
-                "mma_m8n8k32_s32_u4",
-                "i0135",
-                "matrix.mma.m8n8k32.row.col.s32.u4.u4.s32.wrapping",
-                "int_nvvm_mma_m8n8k32_row_col_u4",
-                "llvm.nvvm.mma.m8n8k32.row.col.u4",
-                GeneratedStub,
-            ),
-            (M8n8k32, U4, S4, Wrapping) => (
-                "mma_m8n8k32_s32_u4_s4",
-                "i0136",
-                "matrix.mma.m8n8k32.row.col.s32.u4.s4.s32.wrapping",
-                "int_nvvm_mma_m8n8k32_row_col_u4_s4",
-                "llvm.nvvm.mma.m8n8k32.row.col.u4.s4",
-                GeneratedStub,
-            ),
-            (M8n8k32, S4, S4, Satfinite) => (
-                "mma_m8n8k32_s32_s4_satfinite",
-                "i0137",
-                "matrix.mma.m8n8k32.row.col.s32.s4.s4.s32.satfinite",
-                "int_nvvm_mma_m8n8k32_row_col_satfinite_s4",
-                "llvm.nvvm.mma.m8n8k32.row.col.satfinite.s4",
-                GeneratedStub,
-            ),
-            (M8n8k32, S4, U4, Satfinite) => (
-                "mma_m8n8k32_s32_s4_u4_satfinite",
-                "i0138",
-                "matrix.mma.m8n8k32.row.col.s32.s4.u4.s32.satfinite",
-                "int_nvvm_mma_m8n8k32_row_col_satfinite_s4_u4",
-                "llvm.nvvm.mma.m8n8k32.row.col.satfinite.s4.u4",
-                GeneratedStub,
-            ),
-            (M8n8k32, U4, U4, Satfinite) => (
-                "mma_m8n8k32_s32_u4_satfinite",
-                "i0139",
-                "matrix.mma.m8n8k32.row.col.s32.u4.u4.s32.satfinite",
-                "int_nvvm_mma_m8n8k32_row_col_satfinite_u4",
-                "llvm.nvvm.mma.m8n8k32.row.col.satfinite.u4",
-                GeneratedStub,
-            ),
-            (M8n8k32, U4, S4, Satfinite) => (
-                "mma_m8n8k32_s32_u4_s4_satfinite",
-                "i0140",
-                "matrix.mma.m8n8k32.row.col.s32.u4.s4.s32.satfinite",
-                "int_nvvm_mma_m8n8k32_row_col_satfinite_u4_s4",
-                "llvm.nvvm.mma.m8n8k32.row.col.satfinite.u4.s4",
-                GeneratedStub,
-            ),
-            (M16n8k32, S4, S4, Wrapping) => (
-                "mma_m16n8k32_s32_s4",
-                "i0141",
-                "matrix.mma.m16n8k32.row.col.s32.s4.s4.s32.wrapping",
-                "int_nvvm_mma_m16n8k32_row_col_s4",
-                "llvm.nvvm.mma.m16n8k32.row.col.s4",
-                GeneratedStub,
-            ),
-            (M16n8k32, S4, U4, Wrapping) => (
-                "mma_m16n8k32_s32_s4_u4",
-                "i0142",
-                "matrix.mma.m16n8k32.row.col.s32.s4.u4.s32.wrapping",
-                "int_nvvm_mma_m16n8k32_row_col_s4_u4",
-                "llvm.nvvm.mma.m16n8k32.row.col.s4.u4",
-                GeneratedStub,
-            ),
-            (M16n8k32, U4, U4, Wrapping) => (
-                "mma_m16n8k32_s32_u4",
-                "i0143",
-                "matrix.mma.m16n8k32.row.col.s32.u4.u4.s32.wrapping",
-                "int_nvvm_mma_m16n8k32_row_col_u4",
-                "llvm.nvvm.mma.m16n8k32.row.col.u4",
-                GeneratedStub,
-            ),
-            (M16n8k32, U4, S4, Wrapping) => (
-                "mma_m16n8k32_s32_u4_s4",
-                "i0144",
-                "matrix.mma.m16n8k32.row.col.s32.u4.s4.s32.wrapping",
-                "int_nvvm_mma_m16n8k32_row_col_u4_s4",
-                "llvm.nvvm.mma.m16n8k32.row.col.u4.s4",
-                GeneratedStub,
-            ),
-            (M16n8k64, S4, S4, Wrapping) => (
-                "mma_m16n8k64_s32_s4",
-                "i0145",
-                "matrix.mma.m16n8k64.row.col.s32.s4.s4.s32.wrapping",
-                "int_nvvm_mma_m16n8k64_row_col_s4",
-                "llvm.nvvm.mma.m16n8k64.row.col.s4",
-                GeneratedStub,
-            ),
-            (M16n8k64, S4, U4, Wrapping) => (
-                "mma_m16n8k64_s32_s4_u4",
-                "i0146",
-                "matrix.mma.m16n8k64.row.col.s32.s4.u4.s32.wrapping",
-                "int_nvvm_mma_m16n8k64_row_col_s4_u4",
-                "llvm.nvvm.mma.m16n8k64.row.col.s4.u4",
-                GeneratedStub,
-            ),
-            (M16n8k64, U4, U4, Wrapping) => (
-                "mma_m16n8k64_s32_u4",
-                "i0147",
-                "matrix.mma.m16n8k64.row.col.s32.u4.u4.s32.wrapping",
-                "int_nvvm_mma_m16n8k64_row_col_u4",
-                "llvm.nvvm.mma.m16n8k64.row.col.u4",
-                GeneratedStub,
-            ),
-            (M16n8k64, U4, S4, Wrapping) => (
-                "mma_m16n8k64_s32_u4_s4",
-                "i0148",
-                "matrix.mma.m16n8k64.row.col.s32.u4.s4.s32.wrapping",
-                "int_nvvm_mma_m16n8k64_row_col_u4_s4",
-                "llvm.nvvm.mma.m16n8k64.row.col.u4.s4",
-                GeneratedStub,
-            ),
-            (M16n8k32, S4, S4, Satfinite) => (
-                "mma_m16n8k32_s32_s4_satfinite",
-                "i0149",
-                "matrix.mma.m16n8k32.row.col.s32.s4.s4.s32.satfinite",
-                "int_nvvm_mma_m16n8k32_row_col_satfinite_s4",
-                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.s4",
-                GeneratedStub,
-            ),
-            (M16n8k32, S4, U4, Satfinite) => (
-                "mma_m16n8k32_s32_s4_u4_satfinite",
-                "i0150",
-                "matrix.mma.m16n8k32.row.col.s32.s4.u4.s32.satfinite",
-                "int_nvvm_mma_m16n8k32_row_col_satfinite_s4_u4",
-                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.s4.u4",
-                GeneratedStub,
-            ),
-            (M16n8k32, U4, U4, Satfinite) => (
-                "mma_m16n8k32_s32_u4_satfinite",
-                "i0151",
-                "matrix.mma.m16n8k32.row.col.s32.u4.u4.s32.satfinite",
-                "int_nvvm_mma_m16n8k32_row_col_satfinite_u4",
-                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.u4",
-                GeneratedStub,
-            ),
-            (M16n8k32, U4, S4, Satfinite) => (
-                "mma_m16n8k32_s32_u4_s4_satfinite",
-                "i0152",
-                "matrix.mma.m16n8k32.row.col.s32.u4.s4.s32.satfinite",
-                "int_nvvm_mma_m16n8k32_row_col_satfinite_u4_s4",
-                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.u4.s4",
-                GeneratedStub,
-            ),
-            (M16n8k64, S4, S4, Satfinite) => (
-                "mma_m16n8k64_s32_s4_satfinite",
-                "i0153",
-                "matrix.mma.m16n8k64.row.col.s32.s4.s4.s32.satfinite",
-                "int_nvvm_mma_m16n8k64_row_col_satfinite_s4",
-                "llvm.nvvm.mma.m16n8k64.row.col.satfinite.s4",
-                GeneratedStub,
-            ),
-            (M16n8k64, S4, U4, Satfinite) => (
-                "mma_m16n8k64_s32_s4_u4_satfinite",
-                "i0154",
-                "matrix.mma.m16n8k64.row.col.s32.s4.u4.s32.satfinite",
-                "int_nvvm_mma_m16n8k64_row_col_satfinite_s4_u4",
-                "llvm.nvvm.mma.m16n8k64.row.col.satfinite.s4.u4",
-                GeneratedStub,
-            ),
-            (M16n8k64, U4, U4, Satfinite) => (
-                "mma_m16n8k64_s32_u4_satfinite",
-                "i0155",
-                "matrix.mma.m16n8k64.row.col.s32.u4.u4.s32.satfinite",
-                "int_nvvm_mma_m16n8k64_row_col_satfinite_u4",
-                "llvm.nvvm.mma.m16n8k64.row.col.satfinite.u4",
-                GeneratedStub,
-            ),
-            (M16n8k64, U4, S4, Satfinite) => (
-                "mma_m16n8k64_s32_u4_s4_satfinite",
-                "i0156",
-                "matrix.mma.m16n8k64.row.col.s32.u4.s4.s32.satfinite",
-                "int_nvvm_mma_m16n8k64_row_col_satfinite_u4_s4",
-                "llvm.nvvm.mma.m16n8k64.row.col.satfinite.u4.s4",
-                GeneratedStub,
-            ),
-            _ => return None,
-        };
-
-    let int4 = matches!(mma.a_element, S4 | U4);
-    let (rust_arguments, dialect_operands, llvm_arguments, adapter, shape, register_counts) =
-        match (mma.shape, int4) {
-            (M8n8k16, false) | (M8n8k32, true) => (
-                &["[i32; 2]", "u32", "u32"] as &'static [&'static str],
-                &["i32", "i32", "i32", "i32"] as &'static [&'static str],
-                &["i32", "i32", "i32", "i32"] as &'static [&'static str],
-                C2I32A1U32B1U32ToD2I32,
-                match mma.shape {
-                    M8n8k16 => "m8n8k16",
-                    M8n8k32 => "m8n8k32",
-                    _ => unreachable!(),
-                },
-                [2, 1, 1, 2],
-            ),
-            (M16n8k16, false) | (M16n8k32, true) => (
-                &["[i32; 4]", "[u32; 2]", "u32"] as &'static [&'static str],
-                &["i32", "i32", "i32", "i32", "i32", "i32", "i32"] as &'static [&'static str],
-                &["i32", "i32", "i32", "i32", "i32", "i32", "i32"] as &'static [&'static str],
-                C4I32A2U32B1U32ToD4I32,
-                match mma.shape {
-                    M16n8k16 => "m16n8k16",
-                    M16n8k32 => "m16n8k32",
-                    _ => unreachable!(),
-                },
-                [4, 2, 1, 4],
-            ),
-            (M16n8k32, false) | (M16n8k64, true) => (
-                &["[i32; 4]", "[u32; 4]", "[u32; 2]"] as &'static [&'static str],
-                &[
-                    "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32",
-                ] as &'static [&'static str],
-                &[
-                    "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32",
-                ] as &'static [&'static str],
-                C4I32A4U32B2U32ToD4I32,
-                match mma.shape {
-                    M16n8k32 => "m16n8k32",
-                    M16n8k64 => "m16n8k64",
-                    _ => unreachable!(),
-                },
-                [4, 4, 2, 4],
-            ),
-            _ => return None,
-        };
-    if mma.adapter != adapter {
-        return None;
-    }
-
-    let (rust_result, dialect_results, llvm_results, minimum_ptx, minimum_sm) = match mma.shape {
-        M8n8k16 | M8n8k32 => (
-            "[i32; 2]",
-            &["i32", "i32"] as &'static [&'static str],
-            &["i32", "i32"] as &'static [&'static str],
-            "6.5",
-            "sm_75",
-        ),
-        M16n8k16 | M16n8k32 | M16n8k64 => (
-            "[i32; 4]",
-            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
-            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
-            "7.0",
-            "sm_80",
-        ),
-        _ => return None,
-    };
-
-    let element = |element| match element {
-        S4 => Some("s4"),
-        U4 => Some("u4"),
-        S8 => Some("s8"),
-        U8 => Some("u8"),
-        _ => None,
-    };
-    let mut ptx_modifiers = vec!["sync", "aligned", shape, "row", "col"];
-    if mma.overflow == Satfinite {
-        ptx_modifiers.push("satfinite");
-    }
-    ptx_modifiers.extend([
-        "s32",
-        element(mma.a_element)?,
-        element(mma.b_element)?,
-        "s32",
-    ]);
-
-    Some(RegisterMmaRecipe {
-        id,
-        abi_id,
-        operation_key,
-        source_record,
-        llvm_symbol,
-        rust_arguments,
-        rust_result,
-        dialect_op_type: "RegisterMmaOp",
-        dialect_op_name: "nvvm.register_mma",
-        dialect_operands,
-        dialect_results,
-        llvm_arguments,
-        llvm_results,
-        adapter,
-        compatibility_source,
-        minimum_ptx,
-        minimum_sm,
-        ptx_modifiers,
-        ptx_register_counts: register_counts,
-    })
-}
-
-fn binary_register_mma_recipe(mma: &RegisterMma, common: bool) -> Option<RegisterMmaRecipe> {
-    use RegisterMmaAdapter::{
-        C2I32A1U32B1U32ToD2I32, C4I32A2U32B1U32ToD4I32, C4I32A4U32B2U32ToD4I32,
-    };
-    use RegisterMmaOperation::{AndPopc, XorPopc};
-    use RegisterMmaShape::{M8n8k128, M16n8k128, M16n8k256};
-
-    if !common
-        || mma.accumulator != RegisterMmaAccumulator::S32
-        || mma.a_element != RegisterMmaElement::B1
-        || mma.b_element != RegisterMmaElement::B1
-        || mma.overflow != RegisterMmaOverflow::Wrapping
-        || mma.compatibility_source != RegisterMmaCompatibilitySource::GeneratedStub
-    {
-        return None;
-    }
-
-    let (id, abi_id, operation_key, source_record, llvm_symbol, operation_name) =
-        match (mma.shape, mma.operation) {
-            (M8n8k128, XorPopc) => (
-                "mma_m8n8k128_s32_b1_xor_popc",
-                "i0157",
-                "matrix.mma.m8n8k128.row.col.s32.b1.b1.s32.xor.popc",
-                "int_nvvm_mma_xor_popc_m8n8k128_row_col_b1",
-                "llvm.nvvm.mma.xor.popc.m8n8k128.row.col.b1",
-                "xor",
-            ),
-            (M16n8k128, XorPopc) => (
-                "mma_m16n8k128_s32_b1_xor_popc",
-                "i0158",
-                "matrix.mma.m16n8k128.row.col.s32.b1.b1.s32.xor.popc",
-                "int_nvvm_mma_xor_popc_m16n8k128_row_col_b1",
-                "llvm.nvvm.mma.xor.popc.m16n8k128.row.col.b1",
-                "xor",
-            ),
-            (M16n8k256, XorPopc) => (
-                "mma_m16n8k256_s32_b1_xor_popc",
-                "i0159",
-                "matrix.mma.m16n8k256.row.col.s32.b1.b1.s32.xor.popc",
-                "int_nvvm_mma_xor_popc_m16n8k256_row_col_b1",
-                "llvm.nvvm.mma.xor.popc.m16n8k256.row.col.b1",
-                "xor",
-            ),
-            (M8n8k128, AndPopc) => (
-                "mma_m8n8k128_s32_b1_and_popc",
-                "i0160",
-                "matrix.mma.m8n8k128.row.col.s32.b1.b1.s32.and.popc",
-                "int_nvvm_mma_and_popc_m8n8k128_row_col_b1",
-                "llvm.nvvm.mma.and.popc.m8n8k128.row.col.b1",
-                "and",
-            ),
-            (M16n8k128, AndPopc) => (
-                "mma_m16n8k128_s32_b1_and_popc",
-                "i0161",
-                "matrix.mma.m16n8k128.row.col.s32.b1.b1.s32.and.popc",
-                "int_nvvm_mma_and_popc_m16n8k128_row_col_b1",
-                "llvm.nvvm.mma.and.popc.m16n8k128.row.col.b1",
-                "and",
-            ),
-            (M16n8k256, AndPopc) => (
-                "mma_m16n8k256_s32_b1_and_popc",
-                "i0162",
-                "matrix.mma.m16n8k256.row.col.s32.b1.b1.s32.and.popc",
-                "int_nvvm_mma_and_popc_m16n8k256_row_col_b1",
-                "llvm.nvvm.mma.and.popc.m16n8k256.row.col.b1",
-                "and",
-            ),
-            _ => return None,
-        };
-
-    let (
-        rust_arguments,
-        dialect_operands,
-        llvm_arguments,
-        rust_result,
-        result_types,
-        adapter,
-        counts,
-    ) = match mma.shape {
-        M8n8k128 => (
-            &["[i32; 2]", "u32", "u32"] as &'static [&'static str],
-            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
-            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
-            "[i32; 2]",
-            &["i32", "i32"] as &'static [&'static str],
-            C2I32A1U32B1U32ToD2I32,
-            [2, 1, 1, 2],
-        ),
-        M16n8k128 => (
-            &["[i32; 4]", "[u32; 2]", "u32"] as &'static [&'static str],
-            &["i32", "i32", "i32", "i32", "i32", "i32", "i32"] as &'static [&'static str],
-            &["i32", "i32", "i32", "i32", "i32", "i32", "i32"] as &'static [&'static str],
-            "[i32; 4]",
-            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
-            C4I32A2U32B1U32ToD4I32,
-            [4, 2, 1, 4],
-        ),
-        M16n8k256 => (
-            &["[i32; 4]", "[u32; 4]", "[u32; 2]"] as &'static [&'static str],
-            &[
-                "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32",
-            ] as &'static [&'static str],
-            &[
-                "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32",
-            ] as &'static [&'static str],
-            "[i32; 4]",
-            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
-            C4I32A4U32B2U32ToD4I32,
-            [4, 4, 2, 4],
-        ),
-        _ => return None,
-    };
-    if mma.adapter != adapter {
-        return None;
-    }
-
-    let (minimum_ptx, minimum_sm) = match (mma.operation, mma.shape) {
-        (XorPopc, M8n8k128) => ("7.0", "sm_75"),
-        (XorPopc, M16n8k128 | M16n8k256) => ("7.0", "sm_80"),
-        (AndPopc, M8n8k128 | M16n8k128 | M16n8k256) => ("7.1", "sm_80"),
-        _ => return None,
-    };
-    let shape = match mma.shape {
-        M8n8k128 => "m8n8k128",
-        M16n8k128 => "m16n8k128",
-        M16n8k256 => "m16n8k256",
-        _ => return None,
-    };
-
-    Some(RegisterMmaRecipe {
-        id,
-        abi_id,
-        operation_key,
-        source_record,
-        llvm_symbol,
-        rust_arguments,
-        rust_result,
-        dialect_op_type: "RegisterMmaOp",
-        dialect_op_name: "nvvm.register_mma",
-        dialect_operands,
-        dialect_results: result_types,
-        llvm_arguments,
-        llvm_results: result_types,
-        adapter,
-        compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-        minimum_ptx,
-        minimum_sm,
-        ptx_modifiers: vec![
-            "sync",
-            "aligned",
-            shape,
-            "row",
-            "col",
-            "s32",
-            "b1",
-            "b1",
-            "s32",
-            operation_name,
-            "popc",
-        ],
-        ptx_register_counts: counts,
-    })
-}
-
-fn register_mma_recipe(mma: &RegisterMma) -> Option<RegisterMmaRecipe> {
-    use RegisterMmaAccumulator::{F16 as F16Accumulator, F32, F64};
-    use RegisterMmaAdapter::{
-        C2F64A1F64B1F64ToD2F64, C2U32A2U32B1U32ToD2U32, C2U32A4U32B2U32ToD2U32,
-        C4F32A2U32B1U32ToD4F32, C4F32A4U32B2U32ToD4F32,
-    };
-    use RegisterMmaElement::{Bf16, F16 as F16Element, F64 as F64Element, Tf32};
-    use RegisterMmaShape::{M8n8k4, M16n8k4, M16n8k8, M16n8k16};
-
-    let common = mma.a_layout == RegisterMmaLayout::Row
-        && mma.b_layout == RegisterMmaLayout::Col
-        && mma.participation
-            == RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes;
-    if let Some(recipe) = integer_register_mma_recipe(mma, common) {
-        return Some(recipe);
-    }
-    if let Some(recipe) = binary_register_mma_recipe(mma, common) {
-        return Some(recipe);
-    }
-    if mma.operation != RegisterMmaOperation::Multiply {
-        return None;
-    }
-    match (
-        mma.shape,
-        mma.accumulator,
-        mma.a_element,
-        mma.b_element,
-        mma.overflow,
-        mma.adapter,
-        common,
-    ) {
-        (
-            M16n8k4,
-            F32,
-            Tf32,
-            Tf32,
-            RegisterMmaOverflow::NotApplicable,
-            C4F32A2U32B1U32ToD4F32,
-            true,
-        ) => Some(RegisterMmaRecipe {
-            id: "mma_m16n8k4_f32_tf32",
-            abi_id: "i0520",
-            operation_key: "matrix.mma.m16n8k4.row.col.f32.tf32.tf32.f32",
-            source_record: "int_nvvm_mma_m16n8k4_row_col_tf32",
-            llvm_symbol: "llvm.nvvm.mma.m16n8k4.row.col.tf32",
-            rust_arguments: &["[f32; 4]", "[u32; 2]", "u32"],
-            rust_result: "[f32; 4]",
-            dialect_op_type: "RegisterMmaOp",
-            dialect_op_name: "nvvm.register_mma",
-            dialect_operands: &["f32", "f32", "f32", "f32", "i32", "i32", "i32"],
-            dialect_results: &["f32", "f32", "f32", "f32"],
-            llvm_arguments: &["i32", "i32", "i32", "f32", "f32", "f32", "f32"],
-            llvm_results: &["f32", "f32", "f32", "f32"],
-            adapter: C4F32A2U32B1U32ToD4F32,
-            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_modifiers: vec![
-                "sync", "aligned", "m16n8k4", "row", "col", "f32", "tf32", "tf32", "f32",
-            ],
-            ptx_register_counts: [4, 2, 1, 4],
-        }),
-        (
-            M16n8k8,
-            F16Accumulator,
-            F16Element,
-            F16Element,
-            RegisterMmaOverflow::NotApplicable,
-            C2U32A2U32B1U32ToD2U32,
-            true,
-        ) => Some(RegisterMmaRecipe {
-            id: "mma_m16n8k8_f16_f16",
-            abi_id: "i0521",
-            operation_key: "matrix.mma.m16n8k8.row.col.f16.f16.f16.f16",
-            source_record: "int_nvvm_mma_m16n8k8_row_col_f16_f16",
-            llvm_symbol: "llvm.nvvm.mma.m16n8k8.row.col.f16.f16",
-            rust_arguments: &["[u32; 2]", "[u32; 2]", "u32"],
-            rust_result: "[u32; 2]",
-            dialect_op_type: "RegisterMmaOp",
-            dialect_op_name: "nvvm.register_mma",
-            dialect_operands: &["i32", "i32", "i32", "i32", "i32"],
-            dialect_results: &["i32", "i32"],
-            llvm_arguments: &["v2f16", "v2f16", "v2f16", "v2f16", "v2f16"],
-            llvm_results: &["v2f16", "v2f16"],
-            adapter: C2U32A2U32B1U32ToD2U32,
-            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_modifiers: vec![
-                "sync", "aligned", "m16n8k8", "row", "col", "f16", "f16", "f16", "f16",
-            ],
-            ptx_register_counts: [2, 2, 1, 2],
-        }),
-        (
-            M16n8k8,
-            F32,
-            Bf16,
-            Bf16,
-            RegisterMmaOverflow::NotApplicable,
-            C4F32A2U32B1U32ToD4F32,
-            true,
-        ) => Some(RegisterMmaRecipe {
-            id: "mma_m16n8k8_f32_bf16",
-            abi_id: "i0522",
-            operation_key: "matrix.mma.m16n8k8.row.col.f32.bf16.bf16.f32",
-            source_record: "int_nvvm_mma_m16n8k8_row_col_bf16",
-            llvm_symbol: "llvm.nvvm.mma.m16n8k8.row.col.bf16",
-            rust_arguments: &["[f32; 4]", "[u32; 2]", "u32"],
-            rust_result: "[f32; 4]",
-            dialect_op_type: "RegisterMmaOp",
-            dialect_op_name: "nvvm.register_mma",
-            dialect_operands: &["f32", "f32", "f32", "f32", "i32", "i32", "i32"],
-            dialect_results: &["f32", "f32", "f32", "f32"],
-            llvm_arguments: &["i32", "i32", "i32", "f32", "f32", "f32", "f32"],
-            llvm_results: &["f32", "f32", "f32", "f32"],
-            adapter: C4F32A2U32B1U32ToD4F32,
-            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_modifiers: vec![
-                "sync", "aligned", "m16n8k8", "row", "col", "f32", "bf16", "bf16", "f32",
-            ],
-            ptx_register_counts: [4, 2, 1, 4],
-        }),
-        (
-            M16n8k8,
-            F32,
-            F16Element,
-            F16Element,
-            RegisterMmaOverflow::NotApplicable,
-            C4F32A2U32B1U32ToD4F32,
-            true,
-        ) => Some(RegisterMmaRecipe {
-            id: "mma_m16n8k8_f32_f16",
-            abi_id: "i0523",
-            operation_key: "matrix.mma.m16n8k8.row.col.f32.f16.f16.f32",
-            source_record: "int_nvvm_mma_m16n8k8_row_col_f32_f32",
-            llvm_symbol: "llvm.nvvm.mma.m16n8k8.row.col.f32.f32",
-            rust_arguments: &["[f32; 4]", "[u32; 2]", "u32"],
-            rust_result: "[f32; 4]",
-            dialect_op_type: "RegisterMmaOp",
-            dialect_op_name: "nvvm.register_mma",
-            dialect_operands: &["f32", "f32", "f32", "f32", "i32", "i32", "i32"],
-            dialect_results: &["f32", "f32", "f32", "f32"],
-            llvm_arguments: &["v2f16", "v2f16", "v2f16", "f32", "f32", "f32", "f32"],
-            llvm_results: &["f32", "f32", "f32", "f32"],
-            adapter: C4F32A2U32B1U32ToD4F32,
-            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_modifiers: vec![
-                "sync", "aligned", "m16n8k8", "row", "col", "f32", "f16", "f16", "f32",
-            ],
-            ptx_register_counts: [4, 2, 1, 4],
-        }),
-        (
-            M16n8k16,
-            F16Accumulator,
-            F16Element,
-            F16Element,
-            RegisterMmaOverflow::NotApplicable,
-            C2U32A4U32B2U32ToD2U32,
-            true,
-        ) => Some(RegisterMmaRecipe {
-            id: "mma_m16n8k16_f16_f16",
-            abi_id: "i0524",
-            operation_key: "matrix.mma.m16n8k16.row.col.f16.f16.f16.f16",
-            source_record: "int_nvvm_mma_m16n8k16_row_col_f16_f16",
-            llvm_symbol: "llvm.nvvm.mma.m16n8k16.row.col.f16.f16",
-            rust_arguments: &["[u32; 2]", "[u32; 4]", "[u32; 2]"],
-            rust_result: "[u32; 2]",
-            dialect_op_type: "RegisterMmaOp",
-            dialect_op_name: "nvvm.register_mma",
-            dialect_operands: &["i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32"],
-            dialect_results: &["i32", "i32"],
-            llvm_arguments: &[
-                "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16",
-            ],
-            llvm_results: &["v2f16", "v2f16"],
-            adapter: C2U32A4U32B2U32ToD2U32,
-            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_modifiers: vec![
-                "sync", "aligned", "m16n8k16", "row", "col", "f16", "f16", "f16", "f16",
-            ],
-            ptx_register_counts: [2, 4, 2, 2],
-        }),
-        (
-            M16n8k16,
-            F32,
-            Bf16,
-            Bf16,
-            RegisterMmaOverflow::NotApplicable,
-            C4F32A4U32B2U32ToD4F32,
-            true,
-        ) => Some(RegisterMmaRecipe {
-            id: "mma_m16n8k16_f32_bf16",
-            abi_id: "i0105",
-            operation_key: "matrix.mma.m16n8k16.row.col.f32.bf16.bf16.f32",
-            source_record: "int_nvvm_mma_m16n8k16_row_col_bf16",
-            llvm_symbol: "llvm.nvvm.mma.m16n8k16.row.col.bf16",
-            rust_arguments: &["[f32; 4]", "[u32; 4]", "[u32; 2]"],
-            rust_result: "[f32; 4]",
-            dialect_op_type: "RegisterMmaOp",
-            dialect_op_name: "nvvm.register_mma",
-            dialect_operands: &[
-                "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32",
-            ],
-            dialect_results: &["f32", "f32", "f32", "f32"],
-            llvm_arguments: &[
-                "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32",
-            ],
-            llvm_results: &["f32", "f32", "f32", "f32"],
-            adapter: C4F32A4U32B2U32ToD4F32,
-            compatibility_source: RegisterMmaCompatibilitySource::ExistingStub,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_modifiers: vec![
-                "sync", "aligned", "m16n8k16", "row", "col", "f32", "bf16", "bf16", "f32",
-            ],
-            ptx_register_counts: [4, 4, 2, 4],
-        }),
-        (
-            M16n8k16,
-            F32,
-            F16Element,
-            F16Element,
-            RegisterMmaOverflow::NotApplicable,
-            C4F32A4U32B2U32ToD4F32,
-            true,
-        ) => Some(RegisterMmaRecipe {
-            id: "mma_m16n8k16_f32_f16",
-            abi_id: "i0106",
-            operation_key: "matrix.mma.m16n8k16.row.col.f32.f16.f16.f32",
-            source_record: "int_nvvm_mma_m16n8k16_row_col_f32_f32",
-            llvm_symbol: "llvm.nvvm.mma.m16n8k16.row.col.f32.f32",
-            rust_arguments: &["[f32; 4]", "[u32; 4]", "[u32; 2]"],
-            rust_result: "[f32; 4]",
-            dialect_op_type: "RegisterMmaOp",
-            dialect_op_name: "nvvm.register_mma",
-            dialect_operands: &[
-                "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32",
-            ],
-            dialect_results: &["f32", "f32", "f32", "f32"],
-            llvm_arguments: &[
-                "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "f32", "f32", "f32", "f32",
-            ],
-            llvm_results: &["f32", "f32", "f32", "f32"],
-            adapter: C4F32A4U32B2U32ToD4F32,
-            compatibility_source: RegisterMmaCompatibilitySource::ExistingStub,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_modifiers: vec![
-                "sync", "aligned", "m16n8k16", "row", "col", "f32", "f16", "f16", "f32",
-            ],
-            ptx_register_counts: [4, 4, 2, 4],
-        }),
-        (
-            M16n8k8,
-            F32,
-            Tf32,
-            Tf32,
-            RegisterMmaOverflow::NotApplicable,
-            C4F32A4U32B2U32ToD4F32,
-            true,
-        ) => Some(RegisterMmaRecipe {
-            id: "mma_m16n8k8_f32_tf32",
-            abi_id: "i0107",
-            operation_key: "matrix.mma.m16n8k8.row.col.f32.tf32.tf32.f32",
-            source_record: "int_nvvm_mma_m16n8k8_row_col_tf32",
-            llvm_symbol: "llvm.nvvm.mma.m16n8k8.row.col.tf32",
-            rust_arguments: &["[f32; 4]", "[u32; 4]", "[u32; 2]"],
-            rust_result: "[f32; 4]",
-            dialect_op_type: "RegisterMmaOp",
-            dialect_op_name: "nvvm.register_mma",
-            dialect_operands: &[
-                "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32",
-            ],
-            dialect_results: &["f32", "f32", "f32", "f32"],
-            llvm_arguments: &[
-                "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32",
-            ],
-            llvm_results: &["f32", "f32", "f32", "f32"],
-            adapter: C4F32A4U32B2U32ToD4F32,
-            compatibility_source: RegisterMmaCompatibilitySource::ExistingStub,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_modifiers: vec![
-                "sync", "aligned", "m16n8k8", "row", "col", "f32", "tf32", "tf32", "f32",
-            ],
-            ptx_register_counts: [4, 4, 2, 4],
-        }),
-        (
-            M8n8k4,
-            F64,
-            F64Element,
-            F64Element,
-            RegisterMmaOverflow::NotApplicable,
-            C2F64A1F64B1F64ToD2F64,
-            true,
-        ) => Some(RegisterMmaRecipe {
-            id: "mma_m8n8k4_f64",
-            abi_id: "i0109",
-            operation_key: "matrix.mma.m8n8k4.row.col.f64.f64.f64.f64",
-            source_record: "int_nvvm_mma_m8n8k4_row_col_f64",
-            llvm_symbol: "llvm.nvvm.mma.m8n8k4.row.col.f64",
-            rust_arguments: &["[f64; 2]", "f64", "f64"],
-            rust_result: "[f64; 2]",
-            dialect_op_type: "RegisterMmaOp",
-            dialect_op_name: "nvvm.register_mma",
-            dialect_operands: &["f64", "f64", "f64", "f64"],
-            dialect_results: &["f64", "f64"],
-            llvm_arguments: &["f64", "f64", "f64", "f64"],
-            llvm_results: &["f64", "f64"],
-            adapter: C2F64A1F64B1F64ToD2F64,
-            compatibility_source: RegisterMmaCompatibilitySource::ExistingStub,
-            minimum_ptx: "7.0",
-            minimum_sm: "sm_80",
-            ptx_modifiers: vec![
-                "sync", "aligned", "m8n8k4", "row", "col", "f64", "f64", "f64", "f64",
-            ],
-            ptx_register_counts: [2, 1, 1, 2],
-        }),
-        _ => None,
-    }
-}
-
-#[derive(Debug, Clone, Copy)]
-enum RegisterMmaIntegerKind {
-    Int4,
-    Int8,
-}
-
-impl RegisterMmaIntegerKind {
-    fn label(self) -> &'static str {
-        match self {
-            Self::Int4 => "INT4",
-            Self::Int8 => "INT8",
-        }
-    }
-
-    fn supports(self, shape: RegisterMmaShape, element: RegisterMmaElement) -> bool {
-        match self {
-            Self::Int4 => {
-                matches!(
-                    shape,
-                    RegisterMmaShape::M8n8k32
-                        | RegisterMmaShape::M16n8k32
-                        | RegisterMmaShape::M16n8k64
-                ) && matches!(element, RegisterMmaElement::S4 | RegisterMmaElement::U4)
-            }
-            Self::Int8 => {
-                matches!(
-                    shape,
-                    RegisterMmaShape::M8n8k16
-                        | RegisterMmaShape::M16n8k16
-                        | RegisterMmaShape::M16n8k32
-                ) && matches!(element, RegisterMmaElement::S8 | RegisterMmaElement::U8)
-            }
-        }
-    }
-}
-
-fn expand_register_mma_integer_admission(
-    kind: RegisterMmaIntegerKind,
-    admission: &RegisterMmaIntegerAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    use RegisterMmaAdapter::{
-        C2I32A1U32B1U32ToD2I32, C4I32A2U32B1U32ToD4I32, C4I32A4U32B2U32ToD4I32,
-    };
-    use RegisterMmaCompatibilitySource::GeneratedStub;
-    use RegisterMmaLayout::{Col, Row};
-    use RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes;
-    use RegisterMmaShape::{M8n8k16, M8n8k32, M16n8k16, M16n8k32, M16n8k64};
-
-    ensure!(
-        !admission.variants.is_empty(),
-        "compact {} MMA admission has no variants",
-        kind.label()
-    );
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "{} MMA runtime validation may be marked executed only with GPU evidence",
-        kind.label()
-    );
-
-    let mut seen = BTreeSet::new();
-    let mut records = Vec::with_capacity(admission.variants.len());
-    for variant in &admission.variants {
-        ensure!(
-            seen.insert((
-                variant.shape,
-                variant.a_element,
-                variant.b_element,
-                variant.overflow,
-            )),
-            "compact {} MMA admission contains a duplicate variant",
-            kind.label()
-        );
-        ensure!(
-            kind.supports(variant.shape, variant.a_element)
-                && kind.supports(variant.shape, variant.b_element),
-            "compact {} MMA admission contains an unsupported shape or element",
-            kind.label()
-        );
-        let adapter =
-            match (kind, variant.shape) {
-                (RegisterMmaIntegerKind::Int8, M8n8k16)
-                | (RegisterMmaIntegerKind::Int4, M8n8k32) => C2I32A1U32B1U32ToD2I32,
-                (RegisterMmaIntegerKind::Int8, M16n8k16)
-                | (RegisterMmaIntegerKind::Int4, M16n8k32) => C4I32A2U32B1U32ToD4I32,
-                (RegisterMmaIntegerKind::Int8, M16n8k32)
-                | (RegisterMmaIntegerKind::Int4, M16n8k64) => C4I32A4U32B2U32ToD4I32,
-                _ => bail!(
-                    "compact {} MMA admission contains an unsupported shape",
-                    kind.label()
-                ),
-            };
-        let mma = RegisterMma {
-            shape: variant.shape,
-            operation: RegisterMmaOperation::Multiply,
-            kind: None,
-            accumulator: RegisterMmaAccumulator::S32,
-            a_element: variant.a_element,
-            b_element: variant.b_element,
-            a_layout: Row,
-            b_layout: Col,
-            overflow: variant.overflow,
-            participation: AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-            adapter,
-            compatibility_source: GeneratedStub,
-            runtime_validation: admission.runtime_validation,
-        };
-        let recipe = register_mma_recipe(&mma).with_context(|| {
-            format!(
-                "compact {} MMA admission requests a variant outside the closed recipe set",
-                kind.label()
-            )
-        })?;
-        ensure!(
-            recipe.compatibility_source == GeneratedStub,
-            "compact {} MMA admission may only add generated compatibility stubs",
-            kind.label()
-        );
-
-        let element = |element| match (kind, element) {
-            (RegisterMmaIntegerKind::Int4, RegisterMmaElement::S4)
-            | (RegisterMmaIntegerKind::Int8, RegisterMmaElement::S8) => Ok("signed"),
-            (RegisterMmaIntegerKind::Int4, RegisterMmaElement::U4)
-            | (RegisterMmaIntegerKind::Int8, RegisterMmaElement::U8) => Ok("unsigned"),
-            _ => bail!(
-                "compact {} MMA admission contains an unsupported element",
-                kind.label()
-            ),
-        };
-        let overflow = match variant.overflow {
-            RegisterMmaOverflow::Wrapping => "wrapping",
-            RegisterMmaOverflow::Satfinite => "saturating",
-            RegisterMmaOverflow::NotApplicable => {
-                bail!(
-                    "compact {} MMA admission requires an integer overflow mode",
-                    kind.label()
-                )
-            }
-        };
-        let summary = format!(
-            "Multiplies warp-distributed {} A and {} B {} fragments and adds a {overflow} s32 accumulator.",
-            element(variant.a_element)?,
-            element(variant.b_element)?,
-            kind.label(),
-        );
-
-        records.push(OverlayIntrinsic {
-            id: recipe.id.into(),
-            abi_id: recipe.abi_id.into(),
-            operation_key: recipe.operation_key.into(),
-            family: "register_mma".into(),
-            source: None,
-            source_record: Some(recipe.source_record.into()),
-            rust_module: "matrix".into(),
-            rust_name: recipe.id.into(),
-            rust_arguments: recipe
-                .rust_arguments
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            rust_result: recipe.rust_result.into(),
-            safe: false,
-            must_use: true,
-            safe_allowlist_reason: None,
-            public_rust_path: format!("cuda_intrinsics::matrix::{}", recipe.id),
-            compatibility_rust_paths: vec![format!("cuda_device::wmma::{}", recipe.id)],
-            dialect_op_type: recipe.dialect_op_type.into(),
-            dialect_op_name: recipe.dialect_op_name.into(),
-            dialect_operands: recipe
-                .dialect_operands
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            dialect_results: recipe
-                .dialect_results
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            llvm_symbol: Some(recipe.llvm_symbol.into()),
-            resolved_llvm_symbol: None,
-            llvm_arguments: recipe
-                .llvm_arguments
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            llvm_results: recipe
-                .llvm_results
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            pure: false,
-            memory: "none".into(),
-            convergent: true,
-            execution_scope: "warp".into(),
-            minimum_ptx: recipe.minimum_ptx.into(),
-            minimum_sm: Some(recipe.minimum_sm.into()),
-            ptx_result: recipe.rust_result.into(),
-            targets: "all".into(),
-            ptx_isa_version: "9.3".into(),
-            ptx_isa_section: "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
-            lowering: "generated_register_mma".into(),
-            backend_lowerings: vec![
-                OverlayBackendLowering {
-                    backend: IntrinsicBackend::LlvmNvptx,
-                    mechanism: BackendLoweringMechanism::InlinePtx,
-                    evidence_profile: admission.llvm_evidence_profile.clone(),
-                    targets: None,
-                    minimum_ptx: Some(recipe.minimum_ptx.into()),
-                    minimum_sm: Some(recipe.minimum_sm.into()),
-                },
-                OverlayBackendLowering {
-                    backend: IntrinsicBackend::LibNvvm,
-                    mechanism: BackendLoweringMechanism::InlinePtx,
-                    evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                    targets: None,
-                    minimum_ptx: Some(recipe.minimum_ptx.into()),
-                    minimum_sm: Some(recipe.minimum_sm.into()),
-                },
-            ],
-            packed_atomic: None,
-            redux: None,
-            vote: None,
-            active_mask: None,
-            warp_match: None,
-            warp_barrier: None,
-            warp_shuffle: None,
-            dot_product: None,
-            packed_alu: None,
-        integer_minmax: None,
-            packed_conversion: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cp_async_copy: None,
-            cp_async_control: None,
-            cp_async_mbarrier: None,
-            mbarrier_basic: None,
-            movmatrix: None,
-            mbarrier_extended: None,
-            register_mma: Some(mma),
-            sparse_mma: None,
-            prmt: None,
-            cluster_barrier: None,
-            wgmma_control: None,
-            special_register: None,
-            debug_control: None,
-            cluster_memory: None,
-            clc: None,
-            tma: None,
-            tcgen05: None,
-            ldmatrix_variant: None,
-            ldmatrix_safety: None,
-            ldmatrix_adapter: None,
-            selected_address_space: None,
-            expected_ptx: InstructionPattern {
-                mnemonic: "mma".into(),
-                modifiers: recipe
-                    .ptx_modifiers
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                operands: recipe
-                    .ptx_register_counts
-                    .map(|length| OperandPattern::RegisterList { length })
-                    .into(),
-            },
-            summary,
-        });
-    }
-    Ok(records)
-}
-
-const REGISTER_MMA_F8F6F4_ELEMENTS: [RegisterMmaElement; 5] = [
-    RegisterMmaElement::E2m1,
-    RegisterMmaElement::E2m3,
-    RegisterMmaElement::E3m2,
-    RegisterMmaElement::E4m3,
-    RegisterMmaElement::E5m2,
-];
-
-fn register_mma_f8f6f4_element_name(element: RegisterMmaElement) -> Option<&'static str> {
-    match element {
-        RegisterMmaElement::E2m1 => Some("e2m1"),
-        RegisterMmaElement::E2m3 => Some("e2m3"),
-        RegisterMmaElement::E3m2 => Some("e3m2"),
-        RegisterMmaElement::E4m3 => Some("e4m3"),
-        RegisterMmaElement::E5m2 => Some("e5m2"),
-        _ => None,
-    }
-}
-
-fn is_dense_f8f6f4_register_mma_policy(policy: &OverlayIntrinsic) -> bool {
-    policy.family == "register_mma"
-        && policy.targets == REGISTER_MMA_F8F6F4_TARGETS
-        && policy.register_mma.as_ref().is_some_and(|mma| {
-            mma.kind != Some(RegisterMmaKind::Standard)
-                && mma.shape == RegisterMmaShape::M16n8k32
-                && mma.operation == RegisterMmaOperation::Multiply
-                && matches!(
-                    mma.accumulator,
-                    RegisterMmaAccumulator::F16 | RegisterMmaAccumulator::F32
-                )
-                && register_mma_f8f6f4_element_name(mma.a_element).is_some()
-                && register_mma_f8f6f4_element_name(mma.b_element).is_some()
-                && mma.a_layout == RegisterMmaLayout::Row
-                && mma.b_layout == RegisterMmaLayout::Col
-                && mma.overflow == RegisterMmaOverflow::NotApplicable
-        })
-}
-
-fn is_sparse_f8f6f4_f16_policy(policy: &OverlayIntrinsic) -> bool {
-    policy.family == "sparse_mma"
-        && policy.targets == SPARSE_MMA_F8F6F4_TARGETS
-        && policy.sparse_mma.as_ref().is_some_and(|mma| {
-            mma.shape == SparseMmaShape::M16n8k64
-                && mma.accumulator == SparseMmaAccumulator::F16
-                && SPARSE_MMA_F8F6F4_ELEMENTS.contains(&mma.a_element)
-                && SPARSE_MMA_F8F6F4_ELEMENTS.contains(&mma.b_element)
-                && mma.a_layout == SparseMmaLayout::Row
-                && mma.b_layout == SparseMmaLayout::Col
-                && mma.overflow == SparseMmaOverflow::NotApplicable
-                && mma.metadata == SparseMmaMetadata::Ordered
-                && mma.selector == SparseMmaSelector::ImmediateZero
-        })
-}
-
-fn is_f8f6f4_mma_target_matrix_policy(policy: &OverlayIntrinsic) -> bool {
-    is_dense_f8f6f4_register_mma_policy(policy) || is_sparse_f8f6f4_f16_policy(policy)
-}
-
-#[derive(Clone, Copy)]
-struct RegisterMmaF8F6F4Contract {
-    accumulator: RegisterMmaAccumulator,
-    scalar_name: &'static str,
-    rust_arguments: [&'static str; 3],
-    rust_result: &'static str,
-    dialect_operands: &'static [&'static str],
-    dialect_results: &'static [&'static str],
-    llvm_arguments: &'static [&'static str],
-    llvm_results: &'static [&'static str],
-    adapter: RegisterMmaAdapter,
-    ptx_register_counts: [usize; 4],
-    summary_accumulator: &'static str,
-}
-
-fn register_mma_f8f6f4_contract(
-    accumulator: RegisterMmaAccumulator,
-) -> Result<RegisterMmaF8F6F4Contract> {
-    match accumulator {
-        RegisterMmaAccumulator::F16 => Ok(RegisterMmaF8F6F4Contract {
-            accumulator,
-            scalar_name: "f16",
-            rust_arguments: ["[u32; 2]", "[u32; 4]", "[u32; 2]"],
-            rust_result: "[u32; 2]",
-            dialect_operands: &["i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32"],
-            dialect_results: &["i32", "i32"],
-            llvm_arguments: &["i32", "i32", "i32", "i32", "i32", "i32", "v2f16", "v2f16"],
-            llvm_results: &["v2f16", "v2f16"],
-            adapter: RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32,
-            ptx_register_counts: [2, 4, 2, 2],
-            summary_accumulator: "F16",
-        }),
-        RegisterMmaAccumulator::F32 => Ok(RegisterMmaF8F6F4Contract {
-            accumulator,
-            scalar_name: "f32",
-            rust_arguments: ["[f32; 4]", "[u32; 4]", "[u32; 2]"],
-            rust_result: "[f32; 4]",
-            dialect_operands: &[
-                "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32",
-            ],
-            dialect_results: &["f32", "f32", "f32", "f32"],
-            llvm_arguments: &[
-                "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32",
-            ],
-            llvm_results: &["f32", "f32", "f32", "f32"],
-            adapter: RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32,
-            ptx_register_counts: [4, 4, 2, 4],
-            summary_accumulator: "F32",
-        }),
-        _ => bail!("unsupported dense f8f6f4 MMA accumulator {accumulator:?}"),
-    }
-}
-
-fn expand_register_mma_f8f6f4_admission(
-    admission: &RegisterMmaF8F6F4Admission,
-    accumulator: RegisterMmaAccumulator,
-) -> Result<Vec<OverlayIntrinsic>> {
-    let contract = register_mma_f8f6f4_contract(accumulator)?;
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "dense f8f6f4 MMA runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "dense f8f6f4 MMA admission requires both backend evidence profiles"
-    );
-    ensure!(
-        admission.a_elements == REGISTER_MMA_F8F6F4_ELEMENTS
-            && admission.b_elements == REGISTER_MMA_F8F6F4_ELEMENTS
-            && admission.product_count == 25,
-        "dense f8f6f4 MMA admission must contain the canonical 5 by 5 element matrix"
-    );
-    let expected_targets = ["sm_120a", "sm_120f", "sm_121a", "sm_121f"];
-    ensure!(
-        admission
-            .targets
-            .iter()
-            .map(String::as_str)
-            .eq(expected_targets),
-        "dense f8f6f4 MMA admission must retain the reviewed Blackwell target set"
-    );
-
-    let mut records = Vec::with_capacity(admission.product_count);
-    for &a_element in &admission.a_elements {
-        for &b_element in &admission.b_elements {
-            let a = register_mma_f8f6f4_element_name(a_element)
-                .expect("validated dense f8f6f4 A element");
-            let b = register_mma_f8f6f4_element_name(b_element)
-                .expect("validated dense f8f6f4 B element");
-            let scalar = contract.scalar_name;
-            let id = format!("mma_m16n8k32_{scalar}_{a}_{b}");
-            let source_record =
-                format!("int_nvvm_mma_m16n8k32_row_col_kind_f8f6f4_{scalar}_{a}_{b}_{scalar}");
-            let llvm_symbol =
-                format!("llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.{scalar}.{a}.{b}.{scalar}");
-            let mma = RegisterMma {
-                shape: RegisterMmaShape::M16n8k32,
-                operation: RegisterMmaOperation::Multiply,
-                kind: None,
-                accumulator: contract.accumulator,
-                a_element,
-                b_element,
-                a_layout: RegisterMmaLayout::Row,
-                b_layout: RegisterMmaLayout::Col,
-                overflow: RegisterMmaOverflow::NotApplicable,
-                participation:
-                    RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-                adapter: contract.adapter,
-                compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-                runtime_validation: admission.runtime_validation,
-            };
-
-            records.push(OverlayIntrinsic {
-                id: id.clone(),
-                abi_id: String::new(),
-                operation_key: format!(
-                    "matrix.mma.m16n8k32.row.col.kind_f8f6f4.{scalar}.{a}.{b}.{scalar}"
-                ),
-                family: "register_mma".into(),
-                source: None,
-                source_record: Some(source_record),
-                rust_module: "matrix".into(),
-                rust_name: id.clone(),
-                rust_arguments: contract.rust_arguments.map(Into::into).into(),
-                rust_result: contract.rust_result.into(),
-                safe: false,
-                must_use: true,
-                safe_allowlist_reason: None,
-                public_rust_path: format!("cuda_intrinsics::matrix::{id}"),
-                compatibility_rust_paths: vec![format!("cuda_device::wmma::{id}")],
-                dialect_op_type: "RegisterMmaOp".into(),
-                dialect_op_name: "nvvm.register_mma".into(),
-                dialect_operands: contract
-                    .dialect_operands
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                dialect_results: contract
-                    .dialect_results
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                llvm_symbol: Some(llvm_symbol),
-                resolved_llvm_symbol: None,
-                llvm_arguments: contract
-                    .llvm_arguments
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                llvm_results: contract
-                    .llvm_results
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                pure: false,
-                memory: "none".into(),
-                convergent: true,
-                execution_scope: "warp".into(),
-                minimum_ptx: "8.7".into(),
-                minimum_sm: None,
-                ptx_result: contract.rust_result.into(),
-                targets: REGISTER_MMA_F8F6F4_TARGETS.into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section: "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
-                lowering: "generated_register_mma".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.llvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: None,
-                        minimum_sm: None,
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: None,
-                        minimum_sm: None,
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: Some(mma),
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: "mma".into(),
-                    modifiers: [
-                        "sync",
-                        "aligned",
-                        "m16n8k32",
-                        "row",
-                        "col",
-                        "kind::f8f6f4",
-                        scalar,
-                        a,
-                        b,
-                        scalar,
-                    ]
-                    .into_iter()
-                    .map(Into::into)
-                    .collect(),
-                    operands: contract
-                        .ptx_register_counts
-                        .map(|length| OperandPattern::RegisterList { length })
-                        .into(),
-                },
-                summary: format!(
-                    "Multiplies warp-distributed {a} A and {b} B fragments and adds an {} accumulator.",
-                    contract.summary_accumulator
-                ),
-            });
-        }
-    }
-    Ok(records)
-}
-
-fn expand_register_mma_mxf8f6f4_admission(
-    admission: &RegisterMmaF8F6F4Admission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "dense mxf8f6f4 MMA runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "dense mxf8f6f4 MMA admission requires both backend evidence profiles"
-    );
-    ensure!(
-        admission.a_elements == REGISTER_MMA_F8F6F4_ELEMENTS
-            && admission.b_elements == REGISTER_MMA_F8F6F4_ELEMENTS
-            && admission.product_count == 25,
-        "dense mxf8f6f4 MMA admission must contain the canonical 5 by 5 element matrix"
-    );
-    let expected_targets = ["sm_120a", "sm_120f", "sm_121a", "sm_121f"];
-    ensure!(
-        admission
-            .targets
-            .iter()
-            .map(String::as_str)
-            .eq(expected_targets),
-        "dense mxf8f6f4 MMA admission must retain the reviewed Blackwell target set"
-    );
-
-    let rust_arguments = [
-        "[f32; 4]", "[u32; 4]", "[u32; 2]", "u32", "u16", "u16", "u32", "u16", "u16",
-    ];
-    let dialect_operands = [
-        "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i16", "i16",
-        "i32", "i16", "i16",
-    ];
-    let llvm_arguments = [
-        "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32", "i32", "i16", "i16",
-        "i32", "i16", "i16",
-    ];
-    let dialect_results = ["f32", "f32", "f32", "f32"];
-
-    let mut records = Vec::with_capacity(admission.product_count);
-    for &a_element in &admission.a_elements {
-        for &b_element in &admission.b_elements {
-            let a = register_mma_f8f6f4_element_name(a_element)
-                .expect("validated dense mxf8f6f4 A element");
-            let b = register_mma_f8f6f4_element_name(b_element)
-                .expect("validated dense mxf8f6f4 B element");
-            let id = format!("mma_m16n8k32_mxf8f6f4_f32_{a}_{b}");
-            let source_record =
-                format!("int_nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_{a}_{b}_f32_ue8m0");
-            let llvm_symbol = format!(
-                "llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.{a}.{b}.f32.ue8m0"
-            );
-            let mma = RegisterMma {
-                shape: RegisterMmaShape::M16n8k32,
-                operation: RegisterMmaOperation::Multiply,
-                kind: Some(RegisterMmaKind::Mxf8f6f4),
-                accumulator: RegisterMmaAccumulator::F32,
-                a_element,
-                b_element,
-                a_layout: RegisterMmaLayout::Row,
-                b_layout: RegisterMmaLayout::Col,
-                overflow: RegisterMmaOverflow::NotApplicable,
-                participation:
-                    RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-                adapter: RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-                compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-                runtime_validation: admission.runtime_validation,
-            };
-
-            records.push(OverlayIntrinsic {
-                id: id.clone(),
-                abi_id: String::new(),
-                operation_key: format!(
-                    "matrix.mma.m16n8k32.row.col.kind_mxf8f6f4.scale_vec_1x.f32.{a}.{b}.f32.ue8m0"
-                ),
-                family: "register_mma".into(),
-                source: None,
-                source_record: Some(source_record),
-                rust_module: "matrix".into(),
-                rust_name: id.clone(),
-                rust_arguments: rust_arguments.map(Into::into).into(),
-                rust_result: "[f32; 4]".into(),
-                safe: false,
-                must_use: true,
-                safe_allowlist_reason: None,
-                public_rust_path: format!("cuda_intrinsics::matrix::{id}"),
-                compatibility_rust_paths: vec![format!("cuda_device::wmma::{id}")],
-                dialect_op_type: "RegisterMmaOp".into(),
-                dialect_op_name: "nvvm.register_mma".into(),
-                dialect_operands: dialect_operands.map(Into::into).into(),
-                dialect_results: dialect_results.map(Into::into).into(),
-                llvm_symbol: Some(llvm_symbol),
-                resolved_llvm_symbol: None,
-                llvm_arguments: llvm_arguments.map(Into::into).into(),
-                llvm_results: dialect_results.map(Into::into).into(),
-                pure: false,
-                memory: "none".into(),
-                convergent: true,
-                execution_scope: "warp".into(),
-                minimum_ptx: "8.7".into(),
-                minimum_sm: None,
-                ptx_result: "[f32; 4]".into(),
-                targets: REGISTER_MMA_F8F6F4_TARGETS.into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section:
-                    "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
-                lowering: "generated_register_mma".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.llvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: None,
-                        minimum_sm: None,
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: None,
-                        minimum_sm: None,
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: Some(mma),
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: "mma".into(),
-                    modifiers: [
-                        "sync",
-                        "aligned",
-                        "m16n8k32",
-                        "row",
-                        "col",
-                        "kind::mxf8f6f4",
-                        "block_scale",
-                        "f32",
-                        a,
-                        b,
-                        "f32",
-                        "ue8m0",
-                    ]
-                    .into_iter()
-                    .map(Into::into)
-                    .collect(),
-                    operands: vec![
-                        OperandPattern::RegisterList { length: 4 },
-                        OperandPattern::RegisterList { length: 4 },
-                        OperandPattern::RegisterList { length: 2 },
-                        OperandPattern::RegisterList { length: 4 },
-                        OperandPattern::Register,
-                        OperandPattern::RegisterList { length: 2 },
-                        OperandPattern::Register,
-                        OperandPattern::RegisterList { length: 2 },
-                    ],
-                },
-                summary: format!(
-                    "Multiplies block-scaled warp-distributed {a} A and {b} B fragments and adds an F32 accumulator."
-                ),
-            });
-        }
-    }
-    Ok(records)
-}
-
-const REGISTER_MMA_FP8_SHAPES: [RegisterMmaShape; 2] =
-    [RegisterMmaShape::M16n8k16, RegisterMmaShape::M16n8k32];
-const REGISTER_MMA_FP8_ACCUMULATORS: [RegisterMmaAccumulator; 2] =
-    [RegisterMmaAccumulator::F16, RegisterMmaAccumulator::F32];
-const REGISTER_MMA_FP8_ELEMENTS: [RegisterMmaElement; 2] =
-    [RegisterMmaElement::E4m3, RegisterMmaElement::E5m2];
-
-fn register_mma_fp8_element_name(element: RegisterMmaElement) -> Option<&'static str> {
-    match element {
-        RegisterMmaElement::E4m3 => Some("e4m3"),
-        RegisterMmaElement::E5m2 => Some("e5m2"),
-        _ => None,
-    }
-}
-
-fn register_mma_fp8_shape_contract(
-    shape: RegisterMmaShape,
-) -> Result<(&'static str, usize, usize)> {
-    match shape {
-        RegisterMmaShape::M16n8k16 => Ok(("m16n8k16", 2, 1)),
-        RegisterMmaShape::M16n8k32 => Ok(("m16n8k32", 4, 2)),
-        _ => bail!("unsupported standard FP8 register-MMA shape {shape:?}"),
-    }
-}
-
-fn register_mma_fp8_minimum_ptx(
-    shape: RegisterMmaShape,
-    accumulator: RegisterMmaAccumulator,
-) -> &'static str {
-    // ptxas requires PTX 8.7 for the k32 F16 form despite LLVM's 8.4 predicate.
-    match (shape, accumulator) {
-        (RegisterMmaShape::M16n8k32, RegisterMmaAccumulator::F32) => "8.4",
-        _ => "8.7",
-    }
-}
-
-fn expand_register_mma_fp8_admission(
-    admission: &RegisterMmaFp8Admission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "standard FP8 MMA runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "standard FP8 MMA admission requires both backend evidence profiles"
-    );
-    ensure!(
-        admission.shapes == REGISTER_MMA_FP8_SHAPES
-            && admission.accumulators == REGISTER_MMA_FP8_ACCUMULATORS
-            && admission.a_elements == REGISTER_MMA_FP8_ELEMENTS
-            && admission.b_elements == REGISTER_MMA_FP8_ELEMENTS
-            && admission.product_count == 16,
-        "standard FP8 MMA admission must retain the canonical 2 by 2 by 2 by 2 matrix"
-    );
-
-    let mut records = Vec::with_capacity(admission.product_count);
-    for &shape in &admission.shapes {
-        let (shape_name, a_count, b_count) = register_mma_fp8_shape_contract(shape)?;
-        for &accumulator in &admission.accumulators {
-            let minimum_ptx = register_mma_fp8_minimum_ptx(shape, accumulator);
-            let (scalar, rust_arguments, rust_result, dialect_operands, dialect_results, adapter) =
-                match accumulator {
-                    RegisterMmaAccumulator::F16 => (
-                        "f16",
-                        vec![
-                            "[u32; 2]".into(),
-                            format!("[u32; {a_count}]"),
-                            if b_count == 1 {
-                                "u32".into()
-                            } else {
-                                "[u32; 2]".into()
-                            },
-                        ],
-                        "[u32; 2]".to_owned(),
-                        [
-                            vec!["i32".into(); 2],
-                            vec!["i32".into(); a_count],
-                            vec!["i32".into(); b_count],
-                        ]
-                        .concat(),
-                        vec!["i32".into(); 2],
-                        if shape == RegisterMmaShape::M16n8k16 {
-                            RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32
-                        } else {
-                            RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32
-                        },
-                    ),
-                    RegisterMmaAccumulator::F32 => (
-                        "f32",
-                        vec![
-                            "[f32; 4]".into(),
-                            format!("[u32; {a_count}]"),
-                            if b_count == 1 {
-                                "u32".into()
-                            } else {
-                                "[u32; 2]".into()
-                            },
-                        ],
-                        "[f32; 4]".to_owned(),
-                        [
-                            vec!["f32".into(); 4],
-                            vec!["i32".into(); a_count],
-                            vec!["i32".into(); b_count],
-                        ]
-                        .concat(),
-                        vec!["f32".into(); 4],
-                        if shape == RegisterMmaShape::M16n8k16 {
-                            RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
-                        } else {
-                            RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32
-                        },
-                    ),
-                    _ => unreachable!("validated standard FP8 accumulator"),
-                };
-            let llvm_arguments = [
-                vec!["i32".into(); a_count + b_count],
-                if accumulator == RegisterMmaAccumulator::F16 {
-                    vec!["v2f16".into(); 2]
-                } else {
-                    vec!["f32".into(); 4]
-                },
-            ]
-            .concat();
-            let llvm_results = if accumulator == RegisterMmaAccumulator::F16 {
-                vec!["v2f16".into(); 2]
-            } else {
-                vec!["f32".into(); 4]
-            };
-            let result_count = dialect_results.len();
-
-            for &a_element in &admission.a_elements {
-                for &b_element in &admission.b_elements {
-                    let a = register_mma_fp8_element_name(a_element)
-                        .expect("validated standard FP8 A element");
-                    let b = register_mma_fp8_element_name(b_element)
-                        .expect("validated standard FP8 B element");
-                    let id = format!("mma_{shape_name}_fp8_{scalar}_{a}_{b}");
-                    let source_record =
-                        format!("int_nvvm_mma_{shape_name}_row_col_{scalar}_{a}_{b}_{scalar}");
-                    let llvm_symbol =
-                        format!("llvm.nvvm.mma.{shape_name}.row.col.{scalar}.{a}.{b}.{scalar}");
-                    let mma = RegisterMma {
-                        shape,
-                        operation: RegisterMmaOperation::Multiply,
-                        kind: Some(RegisterMmaKind::Standard),
-                        accumulator,
-                        a_element,
-                        b_element,
-                        a_layout: RegisterMmaLayout::Row,
-                        b_layout: RegisterMmaLayout::Col,
-                        overflow: RegisterMmaOverflow::NotApplicable,
-                        participation: RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-                        adapter,
-                        compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-                        runtime_validation: admission.runtime_validation,
-                    };
-                    records.push(OverlayIntrinsic {
-                        id: id.clone(),
-                        abi_id: String::new(),
-                        operation_key: format!(
-                            "matrix.mma.{shape_name}.row.col.standard_fp8.{scalar}.{a}.{b}.{scalar}"
-                        ),
-                        family: "register_mma".into(),
-                        source: None,
-                        source_record: Some(source_record),
-                        rust_module: "matrix".into(),
-                        rust_name: id.clone(),
-                        rust_arguments: rust_arguments.clone(),
-                        rust_result: rust_result.clone(),
-                        safe: false,
-                        must_use: true,
-                        safe_allowlist_reason: None,
-                        public_rust_path: format!("cuda_intrinsics::matrix::{id}"),
-                        compatibility_rust_paths: vec![format!("cuda_device::wmma::{id}")],
-                        dialect_op_type: "RegisterMmaOp".into(),
-                        dialect_op_name: "nvvm.register_mma".into(),
-                        dialect_operands: dialect_operands.clone(),
-                        dialect_results: dialect_results.clone(),
-                        llvm_symbol: Some(llvm_symbol),
-                        resolved_llvm_symbol: None,
-                        llvm_arguments: llvm_arguments.clone(),
-                        llvm_results: llvm_results.clone(),
-                        pure: false,
-                        memory: "none".into(),
-                        convergent: true,
-                        execution_scope: "warp".into(),
-                        minimum_ptx: minimum_ptx.into(),
-                        minimum_sm: Some("sm_89".into()),
-                        ptx_result: rust_result.clone(),
-                        targets: "all".into(),
-                        ptx_isa_version: "9.3".into(),
-                        ptx_isa_section: "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
-                        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
-                        lowering: "generated_register_mma".into(),
-                        backend_lowerings: [
-                            (IntrinsicBackend::LlvmNvptx, &admission.llvm_evidence_profile),
-                            (IntrinsicBackend::LibNvvm, &admission.libnvvm_evidence_profile),
-                        ]
-                        .into_iter()
-                        .map(|(backend, evidence_profile)| OverlayBackendLowering {
-                            backend,
-                            mechanism: BackendLoweringMechanism::InlinePtx,
-                            evidence_profile: evidence_profile.clone(),
-                            targets: None,
-                            minimum_ptx: Some(minimum_ptx.into()),
-                            minimum_sm: Some("sm_89".into()),
-                        })
-                        .collect(),
-                        packed_atomic: None,
-                        redux: None,
-                        vote: None,
-                        active_mask: None,
-                        warp_match: None,
-                        warp_barrier: None,
-                        warp_shuffle: None,
-                        dot_product: None,
-                        packed_alu: None,
-                integer_minmax: None,
-                        packed_conversion: None,
-                        scalar_conversion: None,
-                        scalar_arithmetic: None,
-                        scalar_math: None,
-                        extended_minmax: None,
-                        cp_async_copy: None,
-                        cp_async_control: None,
-                        cp_async_mbarrier: None,
-                        mbarrier_basic: None,
-                        movmatrix: None,
-                        mbarrier_extended: None,
-                        register_mma: Some(mma),
-                        sparse_mma: None,
-                        prmt: None,
-                        cluster_barrier: None,
-                        wgmma_control: None,
-                        special_register: None,
-                        debug_control: None,
-                        cluster_memory: None,
-                        clc: None,
-                        tma: None,
-                        tcgen05: None,
-                        ldmatrix_variant: None,
-                        ldmatrix_safety: None,
-                        ldmatrix_adapter: None,
-                        selected_address_space: None,
-                        expected_ptx: InstructionPattern {
-                            mnemonic: "mma".into(),
-                            modifiers: ["sync", "aligned", shape_name, "row", "col", scalar, a, b, scalar]
-                                .into_iter()
-                                .map(Into::into)
-                                .collect(),
-                            operands: [result_count, a_count, b_count, result_count]
-                                .map(|length| OperandPattern::RegisterList { length })
-                                .into(),
-                        },
-                        summary: format!(
-                            "Multiplies warp-distributed {a} A and {b} B fragments and adds an {scalar} accumulator."
-                        ),
-                    });
-                }
-            }
-        }
-    }
-    ensure!(records.len() == admission.product_count);
-    Ok(records)
-}
-
-const REGISTER_MMA_AMPERE_FLOAT_VARIANTS: [RegisterMmaAmpereFloatVariant; 5] = [
-    RegisterMmaAmpereFloatVariant {
-        shape: RegisterMmaShape::M16n8k4,
-        accumulator: RegisterMmaAccumulator::F32,
-        element: RegisterMmaElement::Tf32,
-    },
-    RegisterMmaAmpereFloatVariant {
-        shape: RegisterMmaShape::M16n8k8,
-        accumulator: RegisterMmaAccumulator::F16,
-        element: RegisterMmaElement::F16,
-    },
-    RegisterMmaAmpereFloatVariant {
-        shape: RegisterMmaShape::M16n8k8,
-        accumulator: RegisterMmaAccumulator::F32,
-        element: RegisterMmaElement::Bf16,
-    },
-    RegisterMmaAmpereFloatVariant {
-        shape: RegisterMmaShape::M16n8k8,
-        accumulator: RegisterMmaAccumulator::F32,
-        element: RegisterMmaElement::F16,
-    },
-    RegisterMmaAmpereFloatVariant {
-        shape: RegisterMmaShape::M16n8k16,
-        accumulator: RegisterMmaAccumulator::F16,
-        element: RegisterMmaElement::F16,
-    },
-];
-
-fn expand_register_mma_ampere_float_admission(
-    admission: &RegisterMmaAmpereFloatAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "Ampere floating-point MMA runtime validation requires GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "Ampere floating-point MMA admission requires both backend evidence profiles"
-    );
-    ensure!(
-        admission.product_count == REGISTER_MMA_AMPERE_FLOAT_VARIANTS.len()
-            && admission.variants == REGISTER_MMA_AMPERE_FLOAT_VARIANTS,
-        "Ampere floating-point MMA admission must retain the five reviewed variants in canonical order"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let adapter = match (variant.shape, variant.accumulator) {
-                (RegisterMmaShape::M16n8k4, RegisterMmaAccumulator::F32)
-                | (RegisterMmaShape::M16n8k8, RegisterMmaAccumulator::F32) => {
-                    RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
-                }
-                (RegisterMmaShape::M16n8k8, RegisterMmaAccumulator::F16) => {
-                    RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32
-                }
-                (RegisterMmaShape::M16n8k16, RegisterMmaAccumulator::F16) => {
-                    RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32
-                }
-                _ => bail!("Ampere floating-point MMA admission contains an unsupported carrier"),
-            };
-            let mma = RegisterMma {
-                shape: variant.shape,
-                operation: RegisterMmaOperation::Multiply,
-                kind: None,
-                accumulator: variant.accumulator,
-                a_element: variant.element,
-                b_element: variant.element,
-                a_layout: RegisterMmaLayout::Row,
-                b_layout: RegisterMmaLayout::Col,
-                overflow: RegisterMmaOverflow::NotApplicable,
-                participation: RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-                adapter,
-                compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-                runtime_validation: admission.runtime_validation,
-            };
-            let recipe = register_mma_recipe(&mma).with_context(|| {
-                "Ampere floating-point MMA admission requests a variant outside the closed recipe set"
-            })?;
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: String::new(),
-                operation_key: recipe.operation_key.into(),
-                family: "register_mma".into(),
-                source: None,
-                source_record: Some(recipe.source_record.into()),
-                rust_module: "matrix".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments: recipe.rust_arguments.iter().map(|value| (*value).into()).collect(),
-                rust_result: recipe.rust_result.into(),
-                safe: false,
-                must_use: true,
-                safe_allowlist_reason: None,
-                public_rust_path: format!("cuda_intrinsics::matrix::{}", recipe.id),
-                compatibility_rust_paths: vec![format!("cuda_device::wmma::{}", recipe.id)],
-                dialect_op_type: recipe.dialect_op_type.into(),
-                dialect_op_name: recipe.dialect_op_name.into(),
-                dialect_operands: recipe.dialect_operands.iter().map(|value| (*value).into()).collect(),
-                dialect_results: recipe.dialect_results.iter().map(|value| (*value).into()).collect(),
-                llvm_symbol: Some(recipe.llvm_symbol.into()),
-                resolved_llvm_symbol: None,
-                llvm_arguments: recipe.llvm_arguments.iter().map(|value| (*value).into()).collect(),
-                llvm_results: recipe.llvm_results.iter().map(|value| (*value).into()).collect(),
-                pure: false,
-                memory: "none".into(),
-                convergent: true,
-                execution_scope: "warp".into(),
-                minimum_ptx: recipe.minimum_ptx.into(),
-                minimum_sm: Some(recipe.minimum_sm.into()),
-                ptx_result: recipe.rust_result.into(),
-                targets: "all".into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section: "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
-                lowering: "generated_register_mma".into(),
-                backend_lowerings: [
-                    (IntrinsicBackend::LlvmNvptx, &admission.llvm_evidence_profile),
-                    (IntrinsicBackend::LibNvvm, &admission.libnvvm_evidence_profile),
-                ]
-                .into_iter()
-                .map(|(backend, evidence_profile)| OverlayBackendLowering {
-                    backend,
-                    mechanism: BackendLoweringMechanism::InlinePtx,
-                    evidence_profile: evidence_profile.clone(),
-                    targets: None,
-                    minimum_ptx: Some(recipe.minimum_ptx.into()),
-                    minimum_sm: Some(recipe.minimum_sm.into()),
-                })
-                .collect(),
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: Some(mma),
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: "mma".into(),
-                    modifiers: recipe.ptx_modifiers.iter().map(|value| (*value).into()).collect(),
-                    operands: recipe
-                        .ptx_register_counts
-                        .map(|length| OperandPattern::RegisterList { length })
-                        .into(),
-                },
-                summary: format!("Executes the {} Ampere floating-point MMA form.", recipe.id),
-            })
-        })
-        .collect()
-}
-
-fn expand_register_mma_binary_admission(
-    admission: &RegisterMmaBinaryAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    use RegisterMmaAdapter::{
-        C2I32A1U32B1U32ToD2I32, C4I32A2U32B1U32ToD4I32, C4I32A4U32B2U32ToD4I32,
-    };
-    use RegisterMmaLayout::{Col, Row};
-    use RegisterMmaOperation::{AndPopc, XorPopc};
-    use RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes;
-    use RegisterMmaShape::{M8n8k128, M16n8k128, M16n8k256};
-
-    ensure!(
-        !admission.variants.is_empty(),
-        "compact binary MMA admission has no variants"
-    );
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "binary MMA runtime validation may be marked executed only with GPU evidence"
-    );
-
-    let mut seen = BTreeSet::new();
-    let mut records = Vec::with_capacity(admission.variants.len());
-    for variant in &admission.variants {
-        ensure!(
-            seen.insert((variant.shape, variant.operation)),
-            "compact binary MMA admission contains a duplicate variant"
-        );
-        ensure!(
-            matches!(variant.operation, AndPopc | XorPopc),
-            "compact binary MMA admission contains a non-binary operation"
-        );
-        let adapter = match variant.shape {
-            M8n8k128 => C2I32A1U32B1U32ToD2I32,
-            M16n8k128 => C4I32A2U32B1U32ToD4I32,
-            M16n8k256 => C4I32A4U32B2U32ToD4I32,
-            _ => bail!("compact binary MMA admission contains an unsupported shape"),
-        };
-        let mma = RegisterMma {
-            shape: variant.shape,
-            operation: variant.operation,
-            kind: None,
-            accumulator: RegisterMmaAccumulator::S32,
-            a_element: RegisterMmaElement::B1,
-            b_element: RegisterMmaElement::B1,
-            a_layout: Row,
-            b_layout: Col,
-            overflow: RegisterMmaOverflow::Wrapping,
-            participation: AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-            adapter,
-            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
-            runtime_validation: admission.runtime_validation,
-        };
-        let recipe = register_mma_recipe(&mma).with_context(
-            || "compact binary MMA admission requests a variant outside the closed recipe set",
-        )?;
-        let operation = match variant.operation {
-            AndPopc => "AND and population count",
-            XorPopc => "XOR and population count",
-            RegisterMmaOperation::Multiply => unreachable!(),
-        };
-        let summary = format!(
-            "Computes warp-distributed binary matrix products with {operation}, then adds a wrapping s32 accumulator."
-        );
-
-        records.push(OverlayIntrinsic {
-            id: recipe.id.into(),
-            abi_id: recipe.abi_id.into(),
-            operation_key: recipe.operation_key.into(),
-            family: "register_mma".into(),
-            source: None,
-            source_record: Some(recipe.source_record.into()),
-            rust_module: "matrix".into(),
-            rust_name: recipe.id.into(),
-            rust_arguments: recipe
-                .rust_arguments
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            rust_result: recipe.rust_result.into(),
-            safe: false,
-            must_use: true,
-            safe_allowlist_reason: None,
-            public_rust_path: format!("cuda_intrinsics::matrix::{}", recipe.id),
-            compatibility_rust_paths: vec![format!("cuda_device::wmma::{}", recipe.id)],
-            dialect_op_type: recipe.dialect_op_type.into(),
-            dialect_op_name: recipe.dialect_op_name.into(),
-            dialect_operands: recipe
-                .dialect_operands
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            dialect_results: recipe
-                .dialect_results
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            llvm_symbol: Some(recipe.llvm_symbol.into()),
-            resolved_llvm_symbol: None,
-            llvm_arguments: recipe
-                .llvm_arguments
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            llvm_results: recipe
-                .llvm_results
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            pure: false,
-            memory: "none".into(),
-            convergent: true,
-            execution_scope: "warp".into(),
-            minimum_ptx: recipe.minimum_ptx.into(),
-            minimum_sm: Some(recipe.minimum_sm.into()),
-            ptx_result: recipe.rust_result.into(),
-            targets: "all".into(),
-            ptx_isa_version: "9.3".into(),
-            ptx_isa_section: "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
-            lowering: "generated_register_mma".into(),
-            backend_lowerings: vec![
-                OverlayBackendLowering {
-                    backend: IntrinsicBackend::LlvmNvptx,
-                    mechanism: BackendLoweringMechanism::InlinePtx,
-                    evidence_profile: admission.llvm_evidence_profile.clone(),
-                    targets: None,
-                    minimum_ptx: Some(recipe.minimum_ptx.into()),
-                    minimum_sm: Some(recipe.minimum_sm.into()),
-                },
-                OverlayBackendLowering {
-                    backend: IntrinsicBackend::LibNvvm,
-                    mechanism: BackendLoweringMechanism::InlinePtx,
-                    evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                    targets: None,
-                    minimum_ptx: Some(recipe.minimum_ptx.into()),
-                    minimum_sm: Some(recipe.minimum_sm.into()),
-                },
-            ],
-            packed_atomic: None,
-            redux: None,
-            vote: None,
-            active_mask: None,
-            warp_match: None,
-            warp_barrier: None,
-            warp_shuffle: None,
-            dot_product: None,
-            packed_alu: None,
-        integer_minmax: None,
-            packed_conversion: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cp_async_copy: None,
-            cp_async_control: None,
-            cp_async_mbarrier: None,
-            mbarrier_basic: None,
-            movmatrix: None,
-            mbarrier_extended: None,
-            register_mma: Some(mma),
-            sparse_mma: None,
-            prmt: None,
-            cluster_barrier: None,
-            wgmma_control: None,
-            special_register: None,
-            debug_control: None,
-            cluster_memory: None,
-            clc: None,
-            tma: None,
-            tcgen05: None,
-            ldmatrix_variant: None,
-            ldmatrix_safety: None,
-            ldmatrix_adapter: None,
-            selected_address_space: None,
-            expected_ptx: InstructionPattern {
-                mnemonic: "mma".into(),
-                modifiers: recipe
-                    .ptx_modifiers
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                operands: recipe
-                    .ptx_register_counts
-                    .map(|length| OperandPattern::RegisterList { length })
-                    .into(),
-            },
-            summary,
-        });
-    }
-    Ok(records)
-}
-
-#[derive(Clone, Copy)]
-struct SparseMmaCarrierRecipe {
-    adapter: SparseMmaAdapter,
-    llvm_adapter: SparseMmaLlvmAdapter,
-    accumulator: SparseMmaAccumulator,
-    selector: SparseMmaSelector,
-    a_registers: usize,
-    b_registers: usize,
-}
-
-impl SparseMmaCarrierRecipe {
-    fn accumulator_registers(self) -> usize {
-        match self.accumulator {
-            SparseMmaAccumulator::F16 => 2,
-            SparseMmaAccumulator::F32 | SparseMmaAccumulator::S32 => 4,
-        }
-    }
-
-    fn operand_count(self) -> usize {
-        self.accumulator_registers() + self.a_registers + self.b_registers + 2
-    }
-
-    fn selector_index(self) -> usize {
-        self.operand_count() - 1
-    }
-
-    fn selector_upper_exclusive(self) -> u8 {
-        match self.selector {
-            SparseMmaSelector::ImmediateZeroOrOne => 2,
-            SparseMmaSelector::ImmediateZero => 1,
-        }
-    }
-
-    fn rust_arguments(self) -> Vec<String> {
-        let accumulator = match self.accumulator {
-            SparseMmaAccumulator::F16 => "[u32; 2]",
-            SparseMmaAccumulator::F32 => "[f32; 4]",
-            SparseMmaAccumulator::S32 => "[i32; 4]",
-        };
-        vec![
-            accumulator.into(),
-            format!("[u32; {}]", self.a_registers),
-            format!("[u32; {}]", self.b_registers),
-            "u32".into(),
-            "u32".into(),
-        ]
-    }
-
-    fn dialect_operands(self) -> Vec<String> {
-        let accumulator = match self.accumulator {
-            SparseMmaAccumulator::F16 => "i32",
-            SparseMmaAccumulator::F32 => "f32",
-            SparseMmaAccumulator::S32 => "i32",
-        };
-        let accumulator_registers = self.accumulator_registers();
-        std::iter::repeat_n(accumulator.to_owned(), accumulator_registers)
-            .chain(std::iter::repeat_n(
-                "u32".to_owned(),
-                self.operand_count() - accumulator_registers,
-            ))
-            .collect()
-    }
-
-    fn llvm_arguments(self) -> Vec<String> {
-        let accumulator = match self.accumulator {
-            SparseMmaAccumulator::F16 => "v2f16",
-            SparseMmaAccumulator::F32 => "f32",
-            SparseMmaAccumulator::S32 => "i32",
-        };
-        std::iter::repeat_n("i32".to_owned(), self.a_registers + self.b_registers)
-            .chain(std::iter::repeat_n(
-                accumulator.to_owned(),
-                self.accumulator_registers(),
-            ))
-            .chain(std::iter::repeat_n("i32".to_owned(), 2))
-            .collect()
-    }
-
-    fn rust_result(self) -> String {
-        match self.accumulator {
-            SparseMmaAccumulator::F16 => "[u32; 2]",
-            SparseMmaAccumulator::F32 => "[f32; 4]",
-            SparseMmaAccumulator::S32 => "[i32; 4]",
-        }
-        .into()
-    }
-
-    fn dialect_results(self) -> Vec<String> {
-        match self.accumulator {
-            SparseMmaAccumulator::F16 => vec!["i32".into(); 2],
-            SparseMmaAccumulator::F32 => vec!["f32".into(); 4],
-            SparseMmaAccumulator::S32 => vec!["i32".into(); 4],
-        }
-    }
-
-    fn llvm_results(self) -> Vec<String> {
-        match self.accumulator {
-            SparseMmaAccumulator::F16 => vec!["v2f16".into(); 2],
-            SparseMmaAccumulator::F32 => vec!["f32".into(); 4],
-            SparseMmaAccumulator::S32 => vec!["i32".into(); 4],
-        }
-    }
-
-    fn expected_ptx_operands(self) -> Vec<OperandPattern> {
-        vec![
-            OperandPattern::RegisterList {
-                length: self.accumulator_registers(),
-            },
-            OperandPattern::RegisterList {
-                length: self.a_registers,
-            },
-            OperandPattern::RegisterList {
-                length: self.b_registers,
-            },
-            OperandPattern::RegisterList {
-                length: self.accumulator_registers(),
-            },
-            OperandPattern::Register,
-            OperandPattern::Immediate,
-        ]
-    }
-
-    fn imported_properties(self) -> Vec<String> {
-        let selector = self.selector_index();
-        vec![
-            format!("ImmArg<arg{selector}>"),
-            "IntrNoCallback".into(),
-            "IntrNoMem".into(),
-            format!("Range<arg{selector},0,{}>", self.selector_upper_exclusive()),
-        ]
-    }
-}
-
-fn sparse_mma_carrier_recipe(
-    shape: SparseMmaShape,
-    a_element: SparseMmaElement,
-    b_element: SparseMmaElement,
-) -> Option<SparseMmaCarrierRecipe> {
-    use SparseMmaElement::{E2m1, E2m3, E3m2, E4m3, E5m2, S4, S8, U4, U8};
-    use SparseMmaShape::{M16n8k32, M16n8k64, M16n8k128};
-
-    match (shape, a_element, b_element) {
-        (M16n8k32, S8 | U8, S8 | U8) | (M16n8k64, S4 | U4, S4 | U4) => {
-            Some(SparseMmaCarrierRecipe {
-                adapter: SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32,
-                llvm_adapter: SparseMmaLlvmAdapter::A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32,
-                accumulator: SparseMmaAccumulator::S32,
-                selector: SparseMmaSelector::ImmediateZeroOrOne,
-                a_registers: 2,
-                b_registers: 2,
-            })
-        }
-        (M16n8k64, S8 | U8, S8 | U8) => Some(SparseMmaCarrierRecipe {
-            adapter: SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32,
-            llvm_adapter: SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32,
-            accumulator: SparseMmaAccumulator::S32,
-            selector: SparseMmaSelector::ImmediateZero,
-            a_registers: 4,
-            b_registers: 4,
-        }),
-        (M16n8k128, S4 | U4, S4 | U4) => Some(SparseMmaCarrierRecipe {
-            adapter: SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32,
-            llvm_adapter: SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32,
-            accumulator: SparseMmaAccumulator::S32,
-            selector: SparseMmaSelector::ImmediateZero,
-            a_registers: 4,
-            b_registers: 4,
-        }),
-        (M16n8k64, E2m1 | E2m3 | E3m2 | E4m3 | E5m2, E2m1 | E2m3 | E3m2 | E4m3 | E5m2) => {
-            Some(SparseMmaCarrierRecipe {
-                adapter: SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32,
-                llvm_adapter: SparseMmaLlvmAdapter::A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32,
-                accumulator: SparseMmaAccumulator::F32,
-                selector: SparseMmaSelector::ImmediateZero,
-                a_registers: 4,
-                b_registers: 4,
-            })
-        }
-        _ => None,
-    }
-}
-
-fn sparse_mma_f8f6f4_f16_carrier_recipe(
-    shape: SparseMmaShape,
-    a_element: SparseMmaElement,
-    b_element: SparseMmaElement,
-) -> Option<SparseMmaCarrierRecipe> {
-    use SparseMmaElement::{E2m1, E2m3, E3m2, E4m3, E5m2};
-
-    if shape != SparseMmaShape::M16n8k64
-        || !matches!(a_element, E2m1 | E2m3 | E3m2 | E4m3 | E5m2)
-        || !matches!(b_element, E2m1 | E2m3 | E3m2 | E4m3 | E5m2)
-    {
-        return None;
-    }
-    Some(SparseMmaCarrierRecipe {
-        adapter: SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32,
-        llvm_adapter: SparseMmaLlvmAdapter::A4I32B4I32C2V2F16MetadataI32SelectorI32ToD2V2F16,
-        accumulator: SparseMmaAccumulator::F16,
-        selector: SparseMmaSelector::ImmediateZero,
-        a_registers: 4,
-        b_registers: 4,
-    })
-}
-
-struct SparseMmaIdentity {
-    id: String,
-    operation_key: String,
-    source_record: String,
-    llvm_symbol: String,
-    ptx_modifiers: Vec<&'static str>,
-}
-
-struct SparseMmaRecipe {
-    identity: SparseMmaIdentity,
-    carrier: SparseMmaCarrierRecipe,
-}
-
-fn sparse_mma_shape_name(shape: SparseMmaShape) -> &'static str {
-    match shape {
-        SparseMmaShape::M16n8k32 => "m16n8k32",
-        SparseMmaShape::M16n8k64 => "m16n8k64",
-        SparseMmaShape::M16n8k128 => "m16n8k128",
-    }
-}
-
-fn sparse_mma_element_name(element: SparseMmaElement) -> &'static str {
-    match element {
-        SparseMmaElement::E2m1 => "e2m1",
-        SparseMmaElement::E2m3 => "e2m3",
-        SparseMmaElement::E3m2 => "e3m2",
-        SparseMmaElement::E4m3 => "e4m3",
-        SparseMmaElement::E5m2 => "e5m2",
-        SparseMmaElement::S4 => "s4",
-        SparseMmaElement::U4 => "u4",
-        SparseMmaElement::S8 => "s8",
-        SparseMmaElement::U8 => "u8",
-    }
-}
-
-fn sparse_mma_identity(mma: &SparseMma) -> SparseMmaIdentity {
-    let shape = sparse_mma_shape_name(mma.shape);
-    let a_element = sparse_mma_element_name(mma.a_element);
-    let b_element = sparse_mma_element_name(mma.b_element);
-    if matches!(
-        mma.accumulator,
-        SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32
-    ) {
-        let scalar = match mma.accumulator {
-            SparseMmaAccumulator::F16 => "f16",
-            SparseMmaAccumulator::F32 => "f32",
-            SparseMmaAccumulator::S32 => unreachable!(),
-        };
-        return SparseMmaIdentity {
-            id: format!(
-                "mma_sp_ordered_metadata_{shape}_kind_f8f6f4_{scalar}_{a_element}_{b_element}_{scalar}"
-            ),
-            operation_key: format!(
-                "matrix.mma.sp.{shape}.row.col.kind_f8f6f4.{scalar}.{a_element}.{b_element}.{scalar}.not_applicable.ordered_metadata"
-            ),
-            source_record: format!(
-                "int_nvvm_mma_sp_ordered_metadata_{shape}_row_col_kind_f8f6f4_{scalar}_{a_element}_{b_element}_{scalar}"
-            ),
-            llvm_symbol: format!(
-                "llvm.nvvm.mma.sp.ordered.metadata.{shape}.row.col.kind.f8f6f4.{scalar}.{a_element}.{b_element}.{scalar}"
-            ),
-            ptx_modifiers: vec![
-                "sp::ordered_metadata",
-                "sync",
-                "aligned",
-                shape,
-                "row",
-                "col",
-                "kind::f8f6f4",
-                scalar,
-                a_element,
-                b_element,
-                scalar,
-            ],
-        };
-    }
-    let compact_elements = if mma.a_element == mma.b_element {
-        a_element.to_owned()
-    } else {
-        format!("{a_element}_{b_element}")
-    };
-    let dotted_elements = if mma.a_element == mma.b_element {
-        a_element.to_owned()
-    } else {
-        format!("{a_element}.{b_element}")
-    };
-    let metadata_id_prefix = match mma.metadata {
-        SparseMmaMetadata::Standard => "",
-        SparseMmaMetadata::Ordered => "ordered_metadata_",
-    };
-    let metadata_source_prefix = metadata_id_prefix;
-    let metadata_symbol_prefix = match mma.metadata {
-        SparseMmaMetadata::Standard => "",
-        SparseMmaMetadata::Ordered => "ordered.metadata.",
-    };
-    let metadata_key = match mma.metadata {
-        SparseMmaMetadata::Standard => "standard_metadata",
-        SparseMmaMetadata::Ordered => "ordered_metadata",
-    };
-    let overflow_id_suffix = match mma.overflow {
-        SparseMmaOverflow::NotApplicable => unreachable!("integer sparse MMA has overflow"),
-        SparseMmaOverflow::Wrapping => "",
-        SparseMmaOverflow::Satfinite => "_satfinite",
-    };
-    let overflow_source_prefix = match mma.overflow {
-        SparseMmaOverflow::NotApplicable => unreachable!("integer sparse MMA has overflow"),
-        SparseMmaOverflow::Wrapping => "",
-        SparseMmaOverflow::Satfinite => "satfinite_",
-    };
-    let overflow_symbol_prefix = match mma.overflow {
-        SparseMmaOverflow::NotApplicable => unreachable!("integer sparse MMA has overflow"),
-        SparseMmaOverflow::Wrapping => "",
-        SparseMmaOverflow::Satfinite => "satfinite.",
-    };
-    let overflow_key = match mma.overflow {
-        SparseMmaOverflow::NotApplicable => unreachable!("integer sparse MMA has overflow"),
-        SparseMmaOverflow::Wrapping => "wrapping",
-        SparseMmaOverflow::Satfinite => "satfinite",
-    };
-
-    let mut ptx_modifiers = vec![
-        match mma.metadata {
-            SparseMmaMetadata::Standard => "sp",
-            SparseMmaMetadata::Ordered => "sp::ordered_metadata",
-        },
-        "sync",
-        "aligned",
-        shape,
-        "row",
-        "col",
-    ];
-    if mma.overflow == SparseMmaOverflow::Satfinite {
-        ptx_modifiers.push("satfinite");
-    }
-    ptx_modifiers.extend(["s32", a_element, b_element, "s32"]);
-
-    SparseMmaIdentity {
-        id: format!(
-            "mma_sp_{metadata_id_prefix}{shape}_s32_{compact_elements}{overflow_id_suffix}"
-        ),
-        operation_key: format!(
-            "matrix.mma.sp.{shape}.row.col.s32.{a_element}.{b_element}.s32.{overflow_key}.{metadata_key}"
-        ),
-        source_record: format!(
-            "int_nvvm_mma_sp_{metadata_source_prefix}{shape}_row_col_{overflow_source_prefix}{compact_elements}"
-        ),
-        llvm_symbol: format!(
-            "llvm.nvvm.mma.sp.{metadata_symbol_prefix}{shape}.row.col.{overflow_symbol_prefix}{dotted_elements}"
-        ),
-        ptx_modifiers,
-    }
-}
-
-fn sparse_mma_recipe(mma: &SparseMma) -> Option<SparseMmaRecipe> {
-    let carrier = if mma.accumulator == SparseMmaAccumulator::F16 {
-        sparse_mma_f8f6f4_f16_carrier_recipe(mma.shape, mma.a_element, mma.b_element)?
-    } else {
-        sparse_mma_carrier_recipe(mma.shape, mma.a_element, mma.b_element)?
-    };
-
-    let scalar_contract = match carrier.accumulator {
-        SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 => {
-            mma.accumulator == carrier.accumulator
-                && mma.overflow == SparseMmaOverflow::NotApplicable
-                && mma.metadata == SparseMmaMetadata::Ordered
-        }
-        SparseMmaAccumulator::S32 => {
-            mma.accumulator == SparseMmaAccumulator::S32
-                && matches!(
-                    mma.overflow,
-                    SparseMmaOverflow::Wrapping | SparseMmaOverflow::Satfinite
-                )
-        }
-    };
-    if !scalar_contract
-        || mma.a_layout != SparseMmaLayout::Row
-        || mma.b_layout != SparseMmaLayout::Col
-        || mma.selector != carrier.selector
-        || mma.participation
-            != SparseMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes
-        || mma.adapter != carrier.adapter
-        || mma.llvm_adapter != carrier.llvm_adapter
-        || mma.compatibility_source != SparseMmaCompatibilitySource::GeneratedStub
-    {
-        return None;
-    }
-
-    Some(SparseMmaRecipe {
-        identity: sparse_mma_identity(mma),
-        carrier,
-    })
-}
-
-fn sparse_mma_minimum_ptx(mma: &SparseMma) -> &'static str {
-    if matches!(
-        mma.accumulator,
-        SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32
-    ) {
-        return "8.7";
-    }
-    match mma.metadata {
-        SparseMmaMetadata::Standard => "7.1",
-        SparseMmaMetadata::Ordered => "8.5",
-    }
-}
-
-fn sparse_mma_hardware(mma: &SparseMma) -> (&'static str, Option<&'static str>) {
-    match mma.accumulator {
-        SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 => (SPARSE_MMA_F8F6F4_TARGETS, None),
-        SparseMmaAccumulator::S32 => ("all", Some("sm_80")),
-    }
-}
-
-fn sparse_mma_ptx_section(_: SparseMmaMetadata) -> &'static str {
-    "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp"
-}
-
-fn expand_sparse_mma_integer_admission(
-    admission: &SparseMmaIntegerAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        !admission.variants.is_empty(),
-        "compact sparse integer MMA admission has no variants"
-    );
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "sparse integer MMA runtime validation may be marked executed only with GPU evidence"
-    );
-
-    let mut seen = BTreeSet::new();
-    let mut records = Vec::with_capacity(admission.variants.len());
-    for variant in &admission.variants {
-        ensure!(
-            seen.insert((
-                variant.shape,
-                variant.a_element,
-                variant.b_element,
-                variant.overflow,
-            )),
-            "compact sparse integer MMA admission contains a duplicate variant"
-        );
-        let carrier = sparse_mma_carrier_recipe(
-            variant.shape,
-            variant.a_element,
-            variant.b_element,
-        )
-        .with_context(
-            || "compact sparse integer MMA admission uses unsupported or mixed-width elements",
-        )?;
-        let mma = SparseMma {
-            shape: variant.shape,
-            accumulator: SparseMmaAccumulator::S32,
-            a_element: variant.a_element,
-            b_element: variant.b_element,
-            a_layout: SparseMmaLayout::Row,
-            b_layout: SparseMmaLayout::Col,
-            overflow: variant.overflow,
-            metadata: admission.metadata,
-            selector: carrier.selector,
-            participation:
-                SparseMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-            adapter: carrier.adapter,
-            llvm_adapter: carrier.llvm_adapter,
-            compatibility_source: SparseMmaCompatibilitySource::GeneratedStub,
-            runtime_validation: admission.runtime_validation,
-        };
-        let recipe = sparse_mma_recipe(&mma).with_context(
-            || "compact sparse integer MMA admission requests a variant outside the closed recipe set",
-        )?;
-        let signedness = |element| match element {
-            SparseMmaElement::S4 => "signed",
-            SparseMmaElement::U4 => "unsigned",
-            SparseMmaElement::S8 => "signed",
-            SparseMmaElement::U8 => "unsigned",
-            _ => unreachable!("integer admission rejects floating formats"),
-        };
-        let width = match (variant.a_element, variant.b_element) {
-            (
-                SparseMmaElement::S4 | SparseMmaElement::U4,
-                SparseMmaElement::S4 | SparseMmaElement::U4,
-            ) => "INT4",
-            (
-                SparseMmaElement::S8 | SparseMmaElement::U8,
-                SparseMmaElement::S8 | SparseMmaElement::U8,
-            ) => "INT8",
-            _ => unreachable!("carrier selection rejects mixed element widths"),
-        };
-        let overflow = match variant.overflow {
-            SparseMmaOverflow::NotApplicable => {
-                unreachable!("integer admission rejects inapplicable overflow")
-            }
-            SparseMmaOverflow::Wrapping => "wrapping",
-            SparseMmaOverflow::Satfinite => "saturating",
-        };
-        let metadata = match admission.metadata {
-            SparseMmaMetadata::Standard => "",
-            SparseMmaMetadata::Ordered => " with ordered sparsity metadata",
-        };
-        let summary = format!(
-            "Multiplies warp-distributed sparse {} A and {} B {width} fragments{metadata} and adds a {overflow} s32 accumulator.",
-            signedness(variant.a_element),
-            signedness(variant.b_element),
-        );
-        records.push(sparse_mma_overlay_record(
-            String::new(),
-            mma,
-            recipe,
-            &admission.llvm_evidence_profile,
-            &admission.libnvvm_evidence_profile,
-            summary,
-        ));
-    }
-    Ok(records)
-}
-
-fn expand_sparse_mma_f8f6f4_admission(
-    admission: &SparseMmaF8F6F4Admission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "sparse f8f6f4 MMA runtime validation may be marked executed only with GPU evidence"
-    );
-
-    let formats = vec![
-        SparseMmaElement::E2m1,
-        SparseMmaElement::E2m3,
-        SparseMmaElement::E3m2,
-        SparseMmaElement::E4m3,
-        SparseMmaElement::E5m2,
-    ];
-    ensure!(
-        admission.a_elements == formats,
-        "compact sparse f8f6f4 MMA admission must list the canonical five A formats"
-    );
-    ensure!(
-        admission.b_elements == formats,
-        "compact sparse f8f6f4 MMA admission must list the canonical five B formats"
-    );
-    ensure!(
-        admission.product_count
-            == admission
-                .a_elements
-                .len()
-                .checked_mul(admission.b_elements.len())
-                .context("compact sparse f8f6f4 MMA admission product count overflow")?
-            && admission.product_count == 25,
-        "compact sparse f8f6f4 MMA admission product_count must be exactly 25"
-    );
-    let mut records = Vec::with_capacity(admission.product_count);
-    for &a_element in &admission.a_elements {
-        for &b_element in &admission.b_elements {
-            let carrier = sparse_mma_carrier_recipe(SparseMmaShape::M16n8k64, a_element, b_element)
-                .with_context(
-                    || "compact sparse f8f6f4 MMA admission uses an unsupported format",
-                )?;
-            ensure!(
-                carrier.accumulator == SparseMmaAccumulator::F32,
-                "compact sparse f8f6f4 MMA admission contains an integer format"
-            );
-            let mma = SparseMma {
-                shape: SparseMmaShape::M16n8k64,
-                accumulator: SparseMmaAccumulator::F32,
-                a_element,
-                b_element,
-                a_layout: SparseMmaLayout::Row,
-                b_layout: SparseMmaLayout::Col,
-                overflow: SparseMmaOverflow::NotApplicable,
-                metadata: SparseMmaMetadata::Ordered,
-                selector: carrier.selector,
-                participation:
-                    SparseMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-                adapter: carrier.adapter,
-                llvm_adapter: carrier.llvm_adapter,
-                compatibility_source: SparseMmaCompatibilitySource::GeneratedStub,
-                runtime_validation: admission.runtime_validation,
-            };
-            let recipe = sparse_mma_recipe(&mma).with_context(|| {
-            "compact sparse f8f6f4 MMA admission requests a variant outside the closed recipe set"
-        })?;
-            let summary = format!(
-                "Multiplies warp-distributed sparse {} A and {} B fragments and adds an f32 accumulator.",
-                sparse_mma_element_name(a_element),
-                sparse_mma_element_name(b_element),
-            );
-            records.push(sparse_mma_overlay_record(
-                String::new(),
-                mma,
-                recipe,
-                &admission.llvm_evidence_profile,
-                &admission.libnvvm_evidence_profile,
-                summary,
-            ));
-        }
-    }
-    ensure!(records.len() == admission.product_count);
-    Ok(records)
-}
-
-const SPARSE_MMA_F8F6F4_ELEMENTS: [SparseMmaElement; 5] = [
-    SparseMmaElement::E2m1,
-    SparseMmaElement::E2m3,
-    SparseMmaElement::E3m2,
-    SparseMmaElement::E4m3,
-    SparseMmaElement::E5m2,
-];
-
-fn expand_sparse_mma_f8f6f4_f16_admission(
-    admission: &SparseMmaF8F6F4F16Admission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "sparse f8f6f4 F16 MMA runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "sparse f8f6f4 F16 MMA admission requires both backend evidence profiles"
-    );
-    ensure!(
-        admission.a_elements == SPARSE_MMA_F8F6F4_ELEMENTS
-            && admission.b_elements == SPARSE_MMA_F8F6F4_ELEMENTS
-            && admission.product_count == 25,
-        "sparse f8f6f4 F16 MMA admission must contain the canonical 5 by 5 element matrix"
-    );
-
-    let mut records = Vec::with_capacity(admission.product_count);
-    for &a_element in &admission.a_elements {
-        for &b_element in &admission.b_elements {
-            let carrier = sparse_mma_f8f6f4_f16_carrier_recipe(
-                SparseMmaShape::M16n8k64,
-                a_element,
-                b_element,
-            )
-            .context("compact sparse f8f6f4 F16 MMA admission uses an unsupported format")?;
-            let mma = SparseMma {
-                shape: SparseMmaShape::M16n8k64,
-                accumulator: SparseMmaAccumulator::F16,
-                a_element,
-                b_element,
-                a_layout: SparseMmaLayout::Row,
-                b_layout: SparseMmaLayout::Col,
-                overflow: SparseMmaOverflow::NotApplicable,
-                metadata: SparseMmaMetadata::Ordered,
-                selector: SparseMmaSelector::ImmediateZero,
-                participation:
-                    SparseMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
-                adapter: carrier.adapter,
-                llvm_adapter: carrier.llvm_adapter,
-                compatibility_source: SparseMmaCompatibilitySource::GeneratedStub,
-                runtime_validation: admission.runtime_validation,
-            };
-            let recipe = sparse_mma_recipe(&mma).context(
-                "compact sparse f8f6f4 F16 MMA admission requests a variant outside the closed recipe set",
-            )?;
-            let summary = format!(
-                "Multiplies warp-distributed sparse {} A and {} B fragments and adds a packed F16 accumulator.",
-                sparse_mma_element_name(a_element),
-                sparse_mma_element_name(b_element),
-            );
-            records.push(sparse_mma_overlay_record(
-                String::new(),
-                mma,
-                recipe,
-                &admission.llvm_evidence_profile,
-                &admission.libnvvm_evidence_profile,
-                summary,
-            ));
-        }
-    }
-    ensure!(records.len() == admission.product_count);
-    Ok(records)
-}
-
-fn sparse_mma_overlay_record(
-    abi_id: String,
-    mma: SparseMma,
-    recipe: SparseMmaRecipe,
-    llvm_evidence_profile: &str,
-    libnvvm_evidence_profile: &str,
-    summary: String,
-) -> OverlayIntrinsic {
-    let identity = &recipe.identity;
-    let minimum_ptx = sparse_mma_minimum_ptx(&mma);
-    let (targets, minimum_sm) = sparse_mma_hardware(&mma);
-    OverlayIntrinsic {
-        id: identity.id.clone(),
-        abi_id,
-        operation_key: identity.operation_key.clone(),
-        family: "sparse_mma".into(),
-        source: None,
-        source_record: Some(identity.source_record.clone()),
-        rust_module: "matrix".into(),
-        rust_name: identity.id.clone(),
-        rust_arguments: recipe.carrier.rust_arguments(),
-        rust_result: recipe.carrier.rust_result(),
-        safe: false,
-        must_use: true,
-        safe_allowlist_reason: None,
-        public_rust_path: format!("cuda_intrinsics::matrix::{}", identity.id),
-        compatibility_rust_paths: vec![format!("cuda_device::wmma::{}", identity.id)],
-        dialect_op_type: "SparseMmaOp".into(),
-        dialect_op_name: "nvvm.sparse_mma".into(),
-        dialect_operands: recipe.carrier.dialect_operands(),
-        dialect_results: recipe.carrier.dialect_results(),
-        llvm_symbol: Some(identity.llvm_symbol.clone()),
-        resolved_llvm_symbol: None,
-        llvm_arguments: recipe.carrier.llvm_arguments(),
-        llvm_results: recipe.carrier.llvm_results(),
-        pure: false,
-        memory: "none".into(),
-        convergent: true,
-        execution_scope: "warp".into(),
-        minimum_ptx: minimum_ptx.into(),
-        minimum_sm: minimum_sm.map(str::to_owned),
-        ptx_result: recipe.carrier.rust_result(),
-        targets: targets.into(),
-        ptx_isa_version: "9.3".into(),
-        ptx_isa_section: sparse_mma_ptx_section(mma.metadata).into(),
-        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp".into(),
-        lowering: "generated_sparse_mma".into(),
-        backend_lowerings: [
-            (IntrinsicBackend::LlvmNvptx, llvm_evidence_profile),
-            (IntrinsicBackend::LibNvvm, libnvvm_evidence_profile),
-        ]
-        .into_iter()
-        .map(|(backend, evidence_profile)| OverlayBackendLowering {
-            backend,
-            mechanism: BackendLoweringMechanism::InlinePtx,
-            evidence_profile: evidence_profile.into(),
-            targets: None,
-            minimum_ptx: Some(minimum_ptx.into()),
-            minimum_sm: minimum_sm.map(str::to_owned),
-        })
-        .collect(),
-        packed_atomic: None,
-        redux: None,
-        vote: None,
-        active_mask: None,
-        warp_match: None,
-        warp_barrier: None,
-        warp_shuffle: None,
-        dot_product: None,
-        packed_alu: None,
-        integer_minmax: None,
-        packed_conversion: None,
-        scalar_conversion: None,
-        scalar_arithmetic: None,
-        scalar_math: None,
-        extended_minmax: None,
-        cp_async_copy: None,
-        cp_async_control: None,
-        cp_async_mbarrier: None,
-        mbarrier_basic: None,
-        movmatrix: None,
-        mbarrier_extended: None,
-        register_mma: None,
-        sparse_mma: Some(mma),
-        prmt: None,
-        cluster_barrier: None,
-        wgmma_control: None,
-        special_register: None,
-        debug_control: None,
-        cluster_memory: None,
-        clc: None,
-        tma: None,
-        tcgen05: None,
-        ldmatrix_variant: None,
-        ldmatrix_safety: None,
-        ldmatrix_adapter: None,
-        selected_address_space: None,
-        expected_ptx: InstructionPattern {
-            mnemonic: "mma".into(),
-            modifiers: identity
-                .ptx_modifiers
-                .iter()
-                .map(|value| (*value).into())
-                .collect(),
-            operands: recipe.carrier.expected_ptx_operands(),
-        },
-        summary,
-    }
-}
-
-fn validate_sparse_mma_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let mma = policy
-        .sparse_mma
-        .as_ref()
-        .with_context(|| format!("{} has no closed sparse-MMA contract", policy.id))?;
-    let recipe = sparse_mma_recipe(mma)
-        .with_context(|| format!("{} requests an unsupported sparse-MMA variant", policy.id))?;
-    let identity = &recipe.identity;
-    let minimum_ptx = sparse_mma_minimum_ptx(mma);
-    let (targets, minimum_sm) = sparse_mma_hardware(mma);
-    ensure!(
-        policy.id == identity.id
-            && policy.operation_key == identity.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(identity.source_record.as_str())
-            && policy.llvm_symbol.as_deref() == Some(identity.llvm_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} sparse-MMA identity does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "matrix"
-            && policy.rust_name == identity.id
-            && policy.public_rust_path == format!("cuda_intrinsics::matrix::{}", identity.id)
-            && policy.rust_arguments == recipe.carrier.rust_arguments()
-            && policy.rust_result == recipe.carrier.rust_result()
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.compatibility_rust_paths == [format!("cuda_device::wmma::{}", identity.id)],
-        "{} must preserve its unsafe must-use Rust sparse-MMA API",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == "SparseMmaOp"
-            && policy.dialect_op_name == "nvvm.sparse_mma"
-            && policy.dialect_operands == recipe.carrier.dialect_operands()
-            && policy.dialect_results == recipe.carrier.dialect_results()
-            && policy.llvm_arguments == recipe.carrier.llvm_arguments()
-            && policy.llvm_results == recipe.carrier.llvm_results()
-            && policy.ptx_result == recipe.carrier.rust_result()
-            && policy.lowering == "generated_sparse_mma",
-        "{} sparse-MMA carrier or lowering adapter disagrees with its recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "none"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == minimum_ptx
-            && policy.minimum_sm.as_deref() == minimum_sm
-            && policy.targets == targets,
-        "{} sparse-MMA effects or target floor disagree with PTX",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == sparse_mma_ptx_section(mma.metadata)
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp",
-        "{} sparse-MMA PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA_SP"]
-            && declaration.properties == recipe.carrier.imported_properties()
-            && declaration.selections.len() == 1
-            && (!matches!(
-                mma.accumulator,
-                SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32
-            ) || declaration.selections[0].predicates == ["Subtarget->hasMMABlockScale()"])
-            && selection_matches_policy(policy, &declaration.selections[0])?,
-        "{} imported sparse MMA declaration changed its class, immediate range, properties, or exact selection contract",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "mma"
-            && policy.expected_ptx.modifiers == identity.ptx_modifiers
-            && policy.expected_ptx.operands == recipe.carrier.expected_ptx_operands(),
-        "{} expected PTX does not match its exact sparse-MMA spelling",
-        policy.id
-    );
-    ensure_exact_inline_ptx_backends(
-        policy,
-        [
-            (IntrinsicBackend::LlvmNvptx, minimum_ptx, minimum_sm),
-            (IntrinsicBackend::LibNvvm, minimum_ptx, minimum_sm),
-        ],
-        "sparse MMA",
-    )?;
-    ensure_no_other_family_contract(policy, "sparse MMA")?;
-    Ok(())
-}
-
-fn validate_register_mma_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let mma = policy
-        .register_mma
-        .as_ref()
-        .with_context(|| format!("{} has no closed register-MMA contract", policy.id))?;
-    match mma.kind {
-        Some(RegisterMmaKind::Standard) => {
-            return validate_register_mma_fp8_policy(policy, declaration, mma);
-        }
-        Some(RegisterMmaKind::F8f6f4) => {
-            return validate_register_mma_f8f6f4_policy(policy, declaration, mma);
-        }
-        Some(RegisterMmaKind::Mxf8f6f4) => {
-            return validate_register_mma_mxf8f6f4_policy(policy, declaration, mma);
-        }
-        None if register_mma_f8f6f4_element_name(mma.a_element).is_some()
-            || register_mma_f8f6f4_element_name(mma.b_element).is_some() =>
-        {
-            return validate_register_mma_f8f6f4_policy(policy, declaration, mma);
-        }
-        None => {}
-    }
-    let recipe = register_mma_recipe(mma)
-        .with_context(|| format!("{} requests an unsupported register-MMA variant", policy.id))?;
-    let abi_matches = matches!(
-        recipe.id,
-        "mma_m16n8k4_f32_tf32"
-            | "mma_m16n8k8_f16_f16"
-            | "mma_m16n8k8_f32_bf16"
-            | "mma_m16n8k8_f32_f16"
-            | "mma_m16n8k16_f16_f16"
-    ) || policy.abi_id == recipe.abi_id;
-    ensure!(
-        policy.id == recipe.id
-            && abi_matches
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} register-MMA identity does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "matrix"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == recipe.rust_arguments
-            && policy.rust_result == recipe.rust_result
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.compatibility_rust_paths == [format!("cuda_device::wmma::{}", recipe.id)],
-        "{} must preserve its unsafe must-use Rust MMA API",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == recipe.dialect_operands
-            && policy.dialect_results == recipe.dialect_results
-            && policy.llvm_arguments == recipe.llvm_arguments
-            && policy.llvm_results == recipe.llvm_results
-            && policy.ptx_result == recipe.rust_result
-            && mma.adapter == recipe.adapter
-            && mma.compatibility_source == recipe.compatibility_source
-            && policy.lowering == "generated_register_mma",
-        "{} register-MMA carrier or lowering adapter disagrees with its recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "none"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
-            && policy.targets == "all",
-        "{} register-MMA effects or target floor disagree with PTX",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma",
-        "{} register-MMA PTX provenance disagrees with the reviewed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.classes.iter().any(|class| class == "NVVM_MMA")
-            && declaration.properties == ["IntrNoCallback", "IntrNoMem"]
-            && declaration.selections.len() == 1
-            && selection_matches_policy(policy, &declaration.selections[0])?,
-        "{} imported MMA declaration changed its class, properties, or exact selection contract",
-        policy.id
-    );
-    // These are imported facts. The BF16 selection is underconstrained.
-    let ampere_float_predicates = match recipe.id {
-        "mma_m16n8k4_f32_tf32" | "mma_m16n8k16_f16_f16" => Some([
-            "Subtarget->getSmVersion() >= 80",
-            "Subtarget->getPTXVersion() >= 70",
-        ]),
-        "mma_m16n8k8_f16_f16" | "mma_m16n8k8_f32_bf16" | "mma_m16n8k8_f32_f16" => Some([
-            "Subtarget->getPTXVersion() >= 65",
-            "Subtarget->getSmVersion() >= 75",
-        ]),
-        _ => None,
-    };
-    if let Some(predicates) = ampere_float_predicates {
-        let selection = &declaration.selections[0];
-        ensure!(
-            declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA"]
-                && selection.predicates == predicates
-                && selection.constraints.is_empty()
-                && mma.kind.is_none()
-                && mma.runtime_validation == RuntimeValidation::Unexecuted,
-            "{} imported Ampere floating-point MMA contract changed",
-            policy.id
-        );
-    }
-    ensure!(
-        policy.expected_ptx.mnemonic == "mma"
-            && policy.expected_ptx.modifiers == recipe.ptx_modifiers
-            && policy.expected_ptx.operands
-                == recipe
-                    .ptx_register_counts
-                    .map(|length| OperandPattern::RegisterList { length }),
-        "{} expected PTX does not match its exact register-MMA spelling",
-        policy.id
-    );
-    ensure_exact_inline_ptx_backends(
-        policy,
-        [
-            (
-                IntrinsicBackend::LlvmNvptx,
-                recipe.minimum_ptx,
-                Some(recipe.minimum_sm),
-            ),
-            (
-                IntrinsicBackend::LibNvvm,
-                recipe.minimum_ptx,
-                Some(recipe.minimum_sm),
-            ),
-        ],
-        "register MMA",
-    )?;
-    ensure_no_other_family_contract(policy, "register MMA")?;
-    Ok(())
-}
-
-fn validate_register_mma_fp8_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-    mma: &RegisterMma,
-) -> Result<()> {
-    ensure!(
-        REGISTER_MMA_FP8_SHAPES.contains(&mma.shape),
-        "{} has an unsupported standard FP8 shape",
-        policy.id
-    );
-    ensure!(
-        REGISTER_MMA_FP8_ACCUMULATORS.contains(&mma.accumulator),
-        "{} has an unsupported standard FP8 accumulator",
-        policy.id
-    );
-    ensure!(
-        REGISTER_MMA_FP8_ELEMENTS.contains(&mma.a_element),
-        "{} has an unsupported standard FP8 A element",
-        policy.id
-    );
-    ensure!(
-        REGISTER_MMA_FP8_ELEMENTS.contains(&mma.b_element),
-        "{} has an unsupported standard FP8 B element",
-        policy.id
-    );
-    let (shape_name, a_count, b_count) = register_mma_fp8_shape_contract(mma.shape)?;
-    let minimum_ptx = register_mma_fp8_minimum_ptx(mma.shape, mma.accumulator);
-    let a = register_mma_fp8_element_name(mma.a_element).expect("validated A element");
-    let b = register_mma_fp8_element_name(mma.b_element).expect("validated B element");
-    let (
-        scalar,
-        rust_arguments,
-        rust_result,
-        dialect_operands,
-        dialect_results,
-        llvm_arguments,
-        llvm_results,
-        adapter,
-    ) = match mma.accumulator {
-        RegisterMmaAccumulator::F16 => (
-            "f16",
-            vec![
-                "[u32; 2]".into(),
-                format!("[u32; {a_count}]"),
-                if b_count == 1 {
-                    "u32".into()
-                } else {
-                    "[u32; 2]".into()
-                },
-            ],
-            "[u32; 2]".to_owned(),
-            [
-                vec!["i32".to_owned(); 2],
-                vec!["i32".to_owned(); a_count],
-                vec!["i32".to_owned(); b_count],
-            ]
-            .concat(),
-            vec!["i32".to_owned(); 2],
-            [
-                vec!["i32".to_owned(); a_count + b_count],
-                vec!["v2f16".to_owned(); 2],
-            ]
-            .concat(),
-            vec!["v2f16".to_owned(); 2],
-            if mma.shape == RegisterMmaShape::M16n8k16 {
-                RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32
-            } else {
-                RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32
-            },
-        ),
-        RegisterMmaAccumulator::F32 => (
-            "f32",
-            vec![
-                "[f32; 4]".into(),
-                format!("[u32; {a_count}]"),
-                if b_count == 1 {
-                    "u32".into()
-                } else {
-                    "[u32; 2]".into()
-                },
-            ],
-            "[f32; 4]".to_owned(),
-            [
-                vec!["f32".to_owned(); 4],
-                vec!["i32".to_owned(); a_count],
-                vec!["i32".to_owned(); b_count],
-            ]
-            .concat(),
-            vec!["f32".to_owned(); 4],
-            [
-                vec!["i32".to_owned(); a_count + b_count],
-                vec!["f32".to_owned(); 4],
-            ]
-            .concat(),
-            vec!["f32".to_owned(); 4],
-            if mma.shape == RegisterMmaShape::M16n8k16 {
-                RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
-            } else {
-                RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32
-            },
-        ),
-        _ => unreachable!("validated accumulator"),
-    };
-    let expected_id = format!("mma_{shape_name}_fp8_{scalar}_{a}_{b}");
-    let expected_source = format!("int_nvvm_mma_{shape_name}_row_col_{scalar}_{a}_{b}_{scalar}");
-    let expected_symbol = format!("llvm.nvvm.mma.{shape_name}.row.col.{scalar}.{a}.{b}.{scalar}");
-
-    ensure!(
-        policy.id == expected_id
-            && policy.operation_key
-                == format!(
-                    "matrix.mma.{shape_name}.row.col.standard_fp8.{scalar}.{a}.{b}.{scalar}"
-                )
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(expected_source.as_str())
-            && policy.llvm_symbol.as_deref() == Some(expected_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} standard FP8 MMA identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "matrix"
-            && policy.rust_name == expected_id
-            && policy.rust_arguments == rust_arguments
-            && policy.rust_result == rust_result
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::matrix::{expected_id}")
-            && policy.compatibility_rust_paths == [format!("cuda_device::wmma::{expected_id}")],
-        "{} must preserve its unsafe must-use standard FP8 API",
-        policy.id
-    );
-    ensure!(
-        mma.kind == Some(RegisterMmaKind::Standard)
-            && mma.operation == RegisterMmaOperation::Multiply
-            && mma.a_layout == RegisterMmaLayout::Row
-            && mma.b_layout == RegisterMmaLayout::Col
-            && mma.overflow == RegisterMmaOverflow::NotApplicable
-            && mma.participation
-                == RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes
-            && mma.adapter == adapter
-            && mma.compatibility_source == RegisterMmaCompatibilitySource::GeneratedStub
-            && mma.runtime_validation == RuntimeValidation::Unexecuted
-            && policy.dialect_op_type == "RegisterMmaOp"
-            && policy.dialect_op_name == "nvvm.register_mma"
-            && policy.dialect_operands == dialect_operands
-            && policy.dialect_results == dialect_results
-            && policy.llvm_arguments == llvm_arguments
-            && policy.llvm_results == llvm_results
-            && policy.ptx_result == rust_result
-            && policy.lowering == "generated_register_mma",
-        "{} standard FP8 MMA carrier or lowering changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "none"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == minimum_ptx
-            && policy.minimum_sm.as_deref() == Some("sm_89")
-            && policy.targets == "all",
-        "{} standard FP8 effects or target floor changed",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma",
-        "{} standard FP8 PTX provenance changed",
-        policy.id
-    );
-    let [selection] = declaration.selections.as_slice() else {
-        bail!(
-            "{} must retain exactly one standard FP8 selection",
-            policy.id
-        );
-    };
-    let expected_predicates = if mma.shape == RegisterMmaShape::M16n8k16 {
-        [
-            "Subtarget->getSmVersion() >= 89",
-            "Subtarget->getPTXVersion() >= 87",
-        ]
-    } else {
-        [
-            "Subtarget->getSmVersion() >= 89",
-            "Subtarget->getPTXVersion() >= 84",
-        ]
-    };
-    ensure!(
-        declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA"]
-            && declaration.properties == ["IntrNoCallback", "IntrNoMem"]
-            && selection_matches_policy(policy, selection)?
-            && selection.predicates == expected_predicates
-            && selection.constraints.is_empty(),
-        "{} imported standard FP8 declaration or selection changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx
-            == InstructionPattern {
-                mnemonic: "mma".into(),
-                modifiers: [
-                    "sync", "aligned", shape_name, "row", "col", scalar, a, b, scalar
-                ]
-                .into_iter()
-                .map(Into::into)
-                .collect(),
-                operands: [
-                    dialect_results.len(),
-                    a_count,
-                    b_count,
-                    dialect_results.len()
-                ]
-                .map(|length| OperandPattern::RegisterList { length })
-                .into(),
-            },
-        "{} expected standard FP8 PTX changed",
-        policy.id
-    );
-    ensure_exact_inline_ptx_backends(
-        policy,
-        [
-            (IntrinsicBackend::LlvmNvptx, minimum_ptx, Some("sm_89")),
-            (IntrinsicBackend::LibNvvm, minimum_ptx, Some("sm_89")),
-        ],
-        "standard FP8 register MMA",
-    )?;
-    ensure_no_other_family_contract(policy, "standard FP8 register MMA")?;
-    Ok(())
-}
-
-fn validate_register_mma_f8f6f4_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-    mma: &RegisterMma,
-) -> Result<()> {
-    let contract = register_mma_f8f6f4_contract(mma.accumulator)?;
-    let a = register_mma_f8f6f4_element_name(mma.a_element)
-        .with_context(|| format!("{} has a non-f8f6f4 A format", policy.id))?;
-    let b = register_mma_f8f6f4_element_name(mma.b_element)
-        .with_context(|| format!("{} has a non-f8f6f4 B format", policy.id))?;
-    let scalar = contract.scalar_name;
-    let expected_id = format!("mma_m16n8k32_{scalar}_{a}_{b}");
-    let expected_source =
-        format!("int_nvvm_mma_m16n8k32_row_col_kind_f8f6f4_{scalar}_{a}_{b}_{scalar}");
-    let expected_symbol =
-        format!("llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.{scalar}.{a}.{b}.{scalar}");
-    ensure!(
-        policy.id == expected_id
-            && policy.operation_key
-                == format!("matrix.mma.m16n8k32.row.col.kind_f8f6f4.{scalar}.{a}.{b}.{scalar}")
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(expected_source.as_str())
-            && policy.llvm_symbol.as_deref() == Some(expected_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} dense f8f6f4 MMA identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "matrix"
-            && policy.rust_name == expected_id
-            && policy.rust_arguments == contract.rust_arguments
-            && policy.rust_result == contract.rust_result
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::matrix::{expected_id}")
-            && policy.compatibility_rust_paths == [format!("cuda_device::wmma::{expected_id}")],
-        "{} must preserve the unsafe must-use dense f8f6f4 API",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == "RegisterMmaOp"
-            && policy.dialect_op_name == "nvvm.register_mma"
-            && policy.dialect_operands == contract.dialect_operands
-            && policy.dialect_results == contract.dialect_results
-            && policy.llvm_arguments == contract.llvm_arguments
-            && policy.llvm_results == contract.llvm_results
-            && policy.ptx_result == contract.rust_result
-            && mma.shape == RegisterMmaShape::M16n8k32
-            && matches!(mma.kind, None | Some(RegisterMmaKind::F8f6f4))
-            && mma.operation == RegisterMmaOperation::Multiply
-            && mma.accumulator == contract.accumulator
-            && mma.a_layout == RegisterMmaLayout::Row
-            && mma.b_layout == RegisterMmaLayout::Col
-            && mma.overflow == RegisterMmaOverflow::NotApplicable
-            && mma.participation
-                == RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes
-            && mma.adapter == contract.adapter
-            && mma.compatibility_source == RegisterMmaCompatibilitySource::GeneratedStub
-            && mma.runtime_validation == RuntimeValidation::Unexecuted
-            && policy.lowering == "generated_register_mma",
-        "{} dense f8f6f4 carrier or lowering changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "none"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == "8.7"
-            && policy.minimum_sm.is_none()
-            && policy.targets == REGISTER_MMA_F8F6F4_TARGETS,
-        "{} dense f8f6f4 effects or exact target set changed",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma",
-        "{} dense f8f6f4 PTX provenance changed",
-        policy.id
-    );
-    let [selection] = declaration.selections.as_slice() else {
-        bail!(
-            "{} must retain exactly one imported dense f8f6f4 instruction selection",
-            policy.id
-        );
-    };
-    ensure!(
-        declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA"]
-            && declaration.properties == ["IntrNoCallback", "IntrNoMem"]
-            && selection_matches_policy(policy, selection)?
-            && selection.predicates == ["Subtarget->hasMMABlockScale()"]
-            && selection.constraints.is_empty(),
-        "{} imported dense f8f6f4 declaration or selection changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx
-            == InstructionPattern {
-                mnemonic: "mma".into(),
-                modifiers: [
-                    "sync",
-                    "aligned",
-                    "m16n8k32",
-                    "row",
-                    "col",
-                    "kind::f8f6f4",
-                    scalar,
-                    a,
-                    b,
-                    scalar,
-                ]
-                .into_iter()
-                .map(Into::into)
-                .collect(),
-                operands: contract
-                    .ptx_register_counts
-                    .map(|length| OperandPattern::RegisterList { length })
-                    .into(),
-            },
-        "{} expected dense f8f6f4 PTX changed",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ])
-            && policy.backend_lowerings.iter().all(|lowering| {
-                lowering.targets.is_none()
-                    && lowering.minimum_ptx.is_none()
-                    && lowering.minimum_sm.is_none()
-                    && !lowering.evidence_profile.trim().is_empty()
-            }),
-        "{} must inherit the exact reviewed target set on both inline-PTX routes",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "dense f8f6f4 register MMA")?;
-    Ok(())
-}
-
-fn validate_register_mma_mxf8f6f4_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-    mma: &RegisterMma,
-) -> Result<()> {
-    let a = register_mma_f8f6f4_element_name(mma.a_element)
-        .with_context(|| format!("{} has a non-mxf8f6f4 A format", policy.id))?;
-    let b = register_mma_f8f6f4_element_name(mma.b_element)
-        .with_context(|| format!("{} has a non-mxf8f6f4 B format", policy.id))?;
-    let expected_id = format!("mma_m16n8k32_mxf8f6f4_f32_{a}_{b}");
-    let expected_source =
-        format!("int_nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_{a}_{b}_f32_ue8m0");
-    let expected_symbol =
-        format!("llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.{a}.{b}.f32.ue8m0");
-    let rust_arguments = [
-        "[f32; 4]", "[u32; 4]", "[u32; 2]", "u32", "u16", "u16", "u32", "u16", "u16",
-    ];
-    let dialect_operands = [
-        "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i16", "i16",
-        "i32", "i16", "i16",
-    ];
-    let llvm_arguments = [
-        "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32", "i32", "i16", "i16",
-        "i32", "i16", "i16",
-    ];
-    let results = ["f32", "f32", "f32", "f32"];
-    ensure!(
-        policy.id == expected_id
-            && policy.operation_key
-                == format!(
-                    "matrix.mma.m16n8k32.row.col.kind_mxf8f6f4.scale_vec_1x.f32.{a}.{b}.f32.ue8m0"
-                )
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(expected_source.as_str())
-            && policy.llvm_symbol.as_deref() == Some(expected_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} dense mxf8f6f4 MMA identity changed",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "matrix"
-            && policy.rust_name == expected_id
-            && policy.rust_arguments == rust_arguments
-            && policy.rust_result == "[f32; 4]"
-            && !policy.safe
-            && policy.must_use
-            && policy.safe_allowlist_reason.is_none()
-            && policy.public_rust_path == format!("cuda_intrinsics::matrix::{expected_id}")
-            && policy.compatibility_rust_paths == [format!("cuda_device::wmma::{expected_id}")],
-        "{} must preserve the unsafe must-use dense mxf8f6f4 API",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == "RegisterMmaOp"
-            && policy.dialect_op_name == "nvvm.register_mma"
-            && policy.dialect_operands == dialect_operands
-            && policy.dialect_results == results
-            && policy.llvm_arguments == llvm_arguments
-            && policy.llvm_results == results
-            && policy.ptx_result == "[f32; 4]"
-            && mma.shape == RegisterMmaShape::M16n8k32
-            && mma.kind == Some(RegisterMmaKind::Mxf8f6f4)
-            && mma.operation == RegisterMmaOperation::Multiply
-            && mma.accumulator == RegisterMmaAccumulator::F32
-            && mma.a_layout == RegisterMmaLayout::Row
-            && mma.b_layout == RegisterMmaLayout::Col
-            && mma.overflow == RegisterMmaOverflow::NotApplicable
-            && mma.participation
-                == RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes
-            && mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
-            && mma.compatibility_source == RegisterMmaCompatibilitySource::GeneratedStub
-            && mma.runtime_validation == RuntimeValidation::Unexecuted
-            && policy.lowering == "generated_register_mma",
-        "{} dense mxf8f6f4 carrier or lowering changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "none"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == "8.7"
-            && policy.minimum_sm.is_none()
-            && policy.targets == REGISTER_MMA_F8F6F4_TARGETS,
-        "{} dense mxf8f6f4 effects or exact target set changed",
-        policy.id
-    );
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma",
-        "{} dense mxf8f6f4 PTX provenance changed",
-        policy.id
-    );
-    let [selection] = declaration.selections.as_slice() else {
-        bail!(
-            "{} must retain exactly one imported dense mxf8f6f4 instruction selection",
-            policy.id
-        );
-    };
-    ensure!(
-        declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA_BLOCK_SCALE"]
-            && declaration.properties == ["IntrNoCallback", "IntrNoMem"]
-            && selection_matches_policy(policy, selection)?
-            && selection.predicates == ["Subtarget->hasMMABlockScale()"]
-            && selection.constraints.is_empty(),
-        "{} imported dense mxf8f6f4 declaration or selection changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx
-            == InstructionPattern {
-                mnemonic: "mma".into(),
-                modifiers: [
-                    "sync",
-                    "aligned",
-                    "m16n8k32",
-                    "row",
-                    "col",
-                    "kind::mxf8f6f4",
-                    "block_scale",
-                    "f32",
-                    a,
-                    b,
-                    "f32",
-                    "ue8m0",
-                ]
-                .into_iter()
-                .map(Into::into)
-                .collect(),
-                operands: vec![
-                    OperandPattern::RegisterList { length: 4 },
-                    OperandPattern::RegisterList { length: 4 },
-                    OperandPattern::RegisterList { length: 2 },
-                    OperandPattern::RegisterList { length: 4 },
-                    OperandPattern::Register,
-                    OperandPattern::RegisterList { length: 2 },
-                    OperandPattern::Register,
-                    OperandPattern::RegisterList { length: 2 },
-                ],
-            },
-        "{} expected dense mxf8f6f4 PTX changed",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ])
-            && policy.backend_lowerings.iter().all(|lowering| {
-                lowering.targets.is_none()
-                    && lowering.minimum_ptx.is_none()
-                    && lowering.minimum_sm.is_none()
-                    && !lowering.evidence_profile.trim().is_empty()
-            }),
-        "{} must inherit the exact reviewed target set on both inline-PTX routes",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "dense mxf8f6f4 register MMA")?;
-    Ok(())
-}
-
-#[derive(Clone, Copy)]
-struct PrmtRecipe {
-    abi_id: &'static str,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    llvm_symbol: &'static str,
-    modifier: Option<&'static str>,
-    adapter: PrmtAdapter,
-    summary: &'static str,
-}
-
-fn prmt_recipe(mode: PrmtMode) -> PrmtRecipe {
-    use PrmtAdapter::{DirectThreeOperands, InsertZeroSecondSource};
-    match mode {
-        PrmtMode::Generic => PrmtRecipe {
-            abi_id: "i0252",
-            id: "prmt",
-            operation_key: "integer.prmt.b32",
-            source_record: "int_nvvm_prmt",
-            llvm_symbol: "llvm.nvvm.prmt",
-            modifier: None,
-            adapter: DirectThreeOperands,
-            summary: "Permutes bytes selected from two 32-bit inputs.",
-        },
-        PrmtMode::F4e => PrmtRecipe {
-            abi_id: "i0253",
-            id: "prmt_f4e",
-            operation_key: "integer.prmt.b32.f4e",
-            source_record: "int_nvvm_prmt_f4e",
-            llvm_symbol: "llvm.nvvm.prmt.f4e",
-            modifier: Some("f4e"),
-            adapter: DirectThreeOperands,
-            summary: "Permutes bytes with the forward four-byte extract mode.",
-        },
-        PrmtMode::B4e => PrmtRecipe {
-            abi_id: "i0254",
-            id: "prmt_b4e",
-            operation_key: "integer.prmt.b32.b4e",
-            source_record: "int_nvvm_prmt_b4e",
-            llvm_symbol: "llvm.nvvm.prmt.b4e",
-            modifier: Some("b4e"),
-            adapter: DirectThreeOperands,
-            summary: "Permutes bytes with the backward four-byte extract mode.",
-        },
-        PrmtMode::Rc8 => PrmtRecipe {
-            abi_id: "i0255",
-            id: "prmt_rc8",
-            operation_key: "integer.prmt.b32.rc8",
-            source_record: "int_nvvm_prmt_rc8",
-            llvm_symbol: "llvm.nvvm.prmt.rc8",
-            modifier: Some("rc8"),
-            adapter: InsertZeroSecondSource,
-            summary: "Replicates a selected byte across the 32-bit result.",
-        },
-        PrmtMode::Ecl => PrmtRecipe {
-            abi_id: "i0256",
-            id: "prmt_ecl",
-            operation_key: "integer.prmt.b32.ecl",
-            source_record: "int_nvvm_prmt_ecl",
-            llvm_symbol: "llvm.nvvm.prmt.ecl",
-            modifier: Some("ecl"),
-            adapter: InsertZeroSecondSource,
-            summary: "Clamps a byte extract toward the least-significant byte.",
-        },
-        PrmtMode::Ecr => PrmtRecipe {
-            abi_id: "i0257",
-            id: "prmt_ecr",
-            operation_key: "integer.prmt.b32.ecr",
-            source_record: "int_nvvm_prmt_ecr",
-            llvm_symbol: "llvm.nvvm.prmt.ecr",
-            modifier: Some("ecr"),
-            adapter: InsertZeroSecondSource,
-            summary: "Clamps a byte extract toward the most-significant byte.",
-        },
-        PrmtMode::Rc16 => PrmtRecipe {
-            abi_id: "i0258",
-            id: "prmt_rc16",
-            operation_key: "integer.prmt.b32.rc16",
-            source_record: "int_nvvm_prmt_rc16",
-            llvm_symbol: "llvm.nvvm.prmt.rc16",
-            modifier: Some("rc16"),
-            adapter: InsertZeroSecondSource,
-            summary: "Replicates a selected 16-bit half across the result.",
-        },
-    }
-}
-
-fn expand_prmt_admission(admission: &PrmtAdmission) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "prmt runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact prmt admission requires both backend evidence profiles"
-    );
-    let expected_modes = BTreeSet::from([
-        PrmtMode::Generic,
-        PrmtMode::F4e,
-        PrmtMode::B4e,
-        PrmtMode::Rc8,
-        PrmtMode::Ecl,
-        PrmtMode::Ecr,
-        PrmtMode::Rc16,
-    ]);
-    let actual_modes: BTreeSet<_> = admission
-        .variants
-        .iter()
-        .map(|variant| variant.mode)
-        .collect();
-    ensure!(
-        admission.variants.len() == expected_modes.len() && actual_modes == expected_modes,
-        "compact prmt admission must contain each of the seven reviewed modes exactly once"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = prmt_recipe(variant.mode);
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must keep reserved ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            let three_operands = recipe.adapter == PrmtAdapter::DirectThreeOperands;
-            let rust_arguments = vec!["u32".into(); if three_operands { 3 } else { 2 }];
-            let llvm_arguments = vec!["i32".into(); if three_operands { 3 } else { 2 }];
-            let mut modifiers = vec!["b32".into()];
-            if let Some(modifier) = recipe.modifier {
-                modifiers.push(modifier.into());
-            }
-            let operands = if three_operands {
-                vec![
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                ]
-            } else {
-                vec![
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                    OperandPattern::Exact { value: "0".into() },
-                    OperandPattern::Register,
-                ]
-            };
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: variant.abi_id.clone(),
-                operation_key: recipe.operation_key.into(),
-                family: "prmt".into(),
-                source: None,
-                source_record: Some(recipe.source_record.into()),
-                rust_module: "prmt".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments,
-                rust_result: "u32".into(),
-                safe: true,
-                must_use: true,
-                safe_allowlist_reason: Some(
-                    "it only permutes register bytes and has no caller preconditions.".into(),
-                ),
-                public_rust_path: format!("cuda_intrinsics::prmt::{}", recipe.id),
-                compatibility_rust_paths: vec![format!("cuda_device::prmt::{}", recipe.id)],
-                dialect_op_type: "PrmtOp".into(),
-                dialect_op_name: "nvvm.prmt".into(),
-                dialect_operands: llvm_arguments.clone(),
-                dialect_results: vec!["i32".into()],
-                llvm_symbol: Some(recipe.llvm_symbol.into()),
-                resolved_llvm_symbol: None,
-                llvm_arguments,
-                llvm_results: vec!["i32".into()],
-                pure: true,
-                memory: "none".into(),
-                convergent: false,
-                execution_scope: "thread".into(),
-                minimum_ptx: "2.0".into(),
-                minimum_sm: Some("sm_20".into()),
-                ptx_result: "u32".into(),
-                targets: "all".into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section: "9.7.9.7 Data Movement and Conversion Instructions: prmt".into(),
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-prmt".into(),
-                lowering: "generated_prmt".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: BackendLoweringMechanism::TypedNvvm,
-                        evidence_profile: admission.llvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some("3.2".into()),
-                        minimum_sm: Some("sm_20".into()),
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: None,
-                        minimum_sm: Some("sm_75".into()),
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: Some(Prmt {
-                    mode: variant.mode,
-                    adapter: recipe.adapter,
-                }),
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: "prmt".into(),
-                    modifiers,
-                    operands,
-                },
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect()
-}
-
-fn validate_prmt_policy(policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic) -> Result<()> {
-    let prmt = policy
-        .prmt
-        .as_ref()
-        .with_context(|| format!("{} has no closed prmt contract", policy.id))?;
-    let recipe = prmt_recipe(prmt.mode);
-    let three_operands = recipe.adapter == PrmtAdapter::DirectThreeOperands;
-    ensure!(
-        prmt.adapter == recipe.adapter
-            && policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} prmt identity does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "prmt"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == vec!["u32"; if three_operands { 3 } else { 2 }]
-            && policy.rust_result == "u32"
-            && policy.safe
-            && policy.must_use
-            && policy.public_rust_path == format!("cuda_intrinsics::prmt::{}", recipe.id)
-            && policy.compatibility_rust_paths == [format!("cuda_device::prmt::{}", recipe.id)],
-        "{} prmt Rust API does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == "PrmtOp"
-            && policy.dialect_op_name == "nvvm.prmt"
-            && policy.dialect_operands == vec!["i32"; if three_operands { 3 } else { 2 }]
-            && policy.dialect_results == ["i32"]
-            && policy.llvm_arguments == policy.dialect_operands
-            && policy.llvm_results == ["i32"]
-            && policy.lowering == "generated_prmt",
-        "{} prmt carrier or lowering does not match its closed recipe",
-        policy.id
-    );
-    ensure!(
-        declaration
-            .classes
-            .iter()
-            .any(|class| class == "NVVMPureIntrinsic")
-            && declaration.properties == ["IntrNoMem", "IntrSpeculatable"]
-            && policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread",
-        "{} prmt effects disagree with the imported declaration",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == "2.0"
-            && policy.minimum_sm.as_deref() == Some("sm_20")
-            && policy.targets == "all"
-            && policy.ptx_result == "u32"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == "9.7.9.7 Data Movement and Conversion Instructions: prmt"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-prmt",
-        "{} prmt target floor or PTX provenance changed",
-        policy.id
-    );
-    let mut modifiers = vec!["b32"];
-    if let Some(modifier) = recipe.modifier {
-        modifiers.push(modifier);
-    }
-    let expected_operands = if three_operands {
-        vec![
-            OperandPattern::Register,
-            OperandPattern::Register,
-            OperandPattern::Register,
-            OperandPattern::Register,
-        ]
-    } else {
-        vec![
-            OperandPattern::Register,
-            OperandPattern::Register,
-            OperandPattern::Exact { value: "0".into() },
-            OperandPattern::Register,
-        ]
-    };
-    ensure!(
-        policy.expected_ptx.mnemonic == "prmt"
-            && policy.expected_ptx.modifiers == modifiers
-            && policy.expected_ptx.operands == expected_operands,
-        "{} expected PTX does not match its closed prmt mode",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ]),
-        "{} must define exactly the reviewed prmt backend routes",
-        policy.id
-    );
-    for lowering in &policy.backend_lowerings {
-        let floor_matches = match lowering.backend {
-            IntrinsicBackend::LlvmNvptx => {
-                lowering.minimum_ptx.as_deref() == Some("3.2")
-                    && lowering.minimum_sm.as_deref() == Some("sm_20")
-            }
-            IntrinsicBackend::LibNvvm => {
-                lowering.minimum_ptx.is_none() && lowering.minimum_sm.as_deref() == Some("sm_75")
-            }
-        };
-        ensure!(
-            floor_matches && !lowering.evidence_profile.trim().is_empty(),
-            "{} backend {:?} does not carry its reviewed prmt floor",
-            policy.id,
-            lowering.backend
-        );
-    }
-    ensure_no_other_family_contract(policy, "prmt")?;
-    Ok(())
-}
-
-#[derive(Clone, Copy)]
-struct ClusterBarrierRecipe {
-    mode: ClusterBarrierMode,
-    abi_id: &'static str,
-    id: &'static str,
-    suffix: &'static str,
-    minimum_ptx: &'static str,
-    ordering: ClusterBarrierOrdering,
-    aligned: bool,
-    summary: &'static str,
-}
-
-fn cluster_barrier_recipe(mode: ClusterBarrierMode) -> ClusterBarrierRecipe {
-    match mode {
-        ClusterBarrierMode::Arrive => ClusterBarrierRecipe {
-            mode,
-            abi_id: "i0277",
-            id: "barrier_cluster_arrive",
-            suffix: "arrive",
-            minimum_ptx: "7.8",
-            ordering: ClusterBarrierOrdering::Release,
-            aligned: false,
-            summary: "Arrives at the cluster barrier with release ordering.",
-        },
-        ClusterBarrierMode::ArriveAligned => ClusterBarrierRecipe {
-            mode,
-            abi_id: "i0278",
-            id: "barrier_cluster_arrive_aligned",
-            suffix: "arrive.aligned",
-            minimum_ptx: "7.8",
-            ordering: ClusterBarrierOrdering::Release,
-            aligned: true,
-            summary: "Arrives at the cluster barrier in aligned mode with release ordering.",
-        },
-        ClusterBarrierMode::ArriveRelaxed => ClusterBarrierRecipe {
-            mode,
-            abi_id: "i0279",
-            id: "barrier_cluster_arrive_relaxed",
-            suffix: "arrive.relaxed",
-            minimum_ptx: "8.0",
-            ordering: ClusterBarrierOrdering::Relaxed,
-            aligned: false,
-            summary: "Arrives at the cluster barrier without a release guarantee.",
-        },
-        ClusterBarrierMode::ArriveRelaxedAligned => ClusterBarrierRecipe {
-            mode,
-            abi_id: "i0280",
-            id: "barrier_cluster_arrive_relaxed_aligned",
-            suffix: "arrive.relaxed.aligned",
-            minimum_ptx: "8.0",
-            ordering: ClusterBarrierOrdering::Relaxed,
-            aligned: true,
-            summary: "Arrives at the cluster barrier in aligned mode without a release guarantee.",
-        },
-        ClusterBarrierMode::Wait => ClusterBarrierRecipe {
-            mode,
-            abi_id: "i0281",
-            id: "barrier_cluster_wait",
-            suffix: "wait",
-            minimum_ptx: "7.8",
-            ordering: ClusterBarrierOrdering::Acquire,
-            aligned: false,
-            summary: "Waits at the cluster barrier with acquire ordering.",
-        },
-        ClusterBarrierMode::WaitAligned => ClusterBarrierRecipe {
-            mode,
-            abi_id: "i0282",
-            id: "barrier_cluster_wait_aligned",
-            suffix: "wait.aligned",
-            minimum_ptx: "7.8",
-            ordering: ClusterBarrierOrdering::Acquire,
-            aligned: true,
-            summary: "Waits at the cluster barrier in aligned mode with acquire ordering.",
-        },
-    }
-}
-
-fn expand_cluster_barrier_admission(
-    admission: &ClusterBarrierAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "cluster-barrier runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact cluster-barrier admission requires both backend evidence profiles"
-    );
-    let expected_modes = BTreeSet::from([
-        ClusterBarrierMode::Arrive,
-        ClusterBarrierMode::ArriveAligned,
-        ClusterBarrierMode::ArriveRelaxed,
-        ClusterBarrierMode::ArriveRelaxedAligned,
-        ClusterBarrierMode::Wait,
-        ClusterBarrierMode::WaitAligned,
-    ]);
-    let actual_modes: BTreeSet<_> = admission
-        .variants
-        .iter()
-        .map(|variant| variant.mode)
-        .collect();
-    ensure!(
-        admission.variants.len() == expected_modes.len() && actual_modes == expected_modes,
-        "compact cluster-barrier admission must contain each reviewed mode exactly once"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = cluster_barrier_recipe(variant.mode);
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must keep reserved ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            let source_record = format!("int_nvvm_barrier_cluster_{}", recipe.suffix.replace('.', "_"));
-            let llvm_symbol = format!("llvm.nvvm.barrier.cluster.{}", recipe.suffix);
-            let modifiers: Vec<String> = recipe.suffix.split('.').map(str::to_owned).collect();
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: variant.abi_id.clone(),
-                operation_key: format!("cluster.barrier.{}", recipe.suffix),
-                family: "cluster_barrier".into(),
-                source: None,
-                source_record: Some(source_record),
-                rust_module: "cluster".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments: vec![],
-                rust_result: "()".into(),
-                safe: false,
-                must_use: false,
-                safe_allowlist_reason: None,
-                public_rust_path: format!("cuda_intrinsics::cluster::{}", recipe.id),
-                compatibility_rust_paths: vec![format!("cuda_device::cluster::{}", recipe.id)],
-                dialect_op_type: "ClusterBarrierOp".into(),
-                dialect_op_name: "nvvm.cluster_barrier".into(),
-                dialect_operands: vec![],
-                dialect_results: vec![],
-                llvm_symbol: Some(llvm_symbol),
-                resolved_llvm_symbol: None,
-                llvm_arguments: vec![],
-                llvm_results: vec![],
-                pure: false,
-                memory: "read_write".into(),
-                convergent: true,
-                execution_scope: "cluster".into(),
-                minimum_ptx: recipe.minimum_ptx.into(),
-                minimum_sm: Some("sm_90".into()),
-                ptx_result: "()".into(),
-                targets: "all".into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section:
-                    "Parallel Synchronization and Communication Instructions: barrier.cluster"
-                        .into(),
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-barrier-cluster".into(),
-                lowering: "generated_cluster_barrier".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: BackendLoweringMechanism::TypedNvvm,
-                        evidence_profile: admission.llvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some(recipe.minimum_ptx.into()),
-                        minimum_sm: Some("sm_90".into()),
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some(recipe.minimum_ptx.into()),
-                        minimum_sm: Some("sm_90".into()),
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: Some(ClusterBarrier {
-                    mode: recipe.mode,
-                    ordering: recipe.ordering,
-                    aligned: recipe.aligned,
-                }),
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: "barrier".into(),
-                    modifiers: std::iter::once("cluster".into()).chain(modifiers).collect(),
-                    operands: vec![],
-                },
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect()
-}
-
-fn validate_cluster_barrier_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let barrier = policy
-        .cluster_barrier
-        .as_ref()
-        .with_context(|| format!("{} has no closed cluster-barrier contract", policy.id))?;
-    let recipe = cluster_barrier_recipe(barrier.mode);
-    let source_record = format!(
-        "int_nvvm_barrier_cluster_{}",
-        recipe.suffix.replace('.', "_")
-    );
-    let llvm_symbol = format!("llvm.nvvm.barrier.cluster.{}", recipe.suffix);
-    ensure!(
-        barrier.ordering == recipe.ordering
-            && barrier.aligned == recipe.aligned
-            && policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == format!("cluster.barrier.{}", recipe.suffix)
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(source_record.as_str())
-            && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} identity or semantics do not match its closed cluster-barrier recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "cluster"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments.is_empty()
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.public_rust_path == format!("cuda_intrinsics::cluster::{}", recipe.id)
-            && policy.compatibility_rust_paths == [format!("cuda_device::cluster::{}", recipe.id)],
-        "{} Rust API does not match its closed cluster-barrier recipe",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == "ClusterBarrierOp"
-            && policy.dialect_op_name == "nvvm.cluster_barrier"
-            && policy.dialect_operands.is_empty()
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments.is_empty()
-            && policy.llvm_results.is_empty()
-            && policy.lowering == "generated_cluster_barrier",
-        "{} carrier or lowering does not match its closed cluster-barrier recipe",
-        policy.id
-    );
-    ensure!(
-        declaration.classes == ["SDPatternOperator", "Intrinsic"]
-            && declaration.properties == ["IntrConvergent", "IntrNoCallback"]
-            && !policy.pure
-            && policy.memory == "read_write"
-            && policy.convergent
-            && policy.execution_scope == "cluster",
-        "{} effects disagree with the imported cluster-barrier declaration",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == Some("sm_90")
-            && policy.targets == "all"
-            && policy.ptx_result == "()"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section
-                == "Parallel Synchronization and Communication Instructions: barrier.cluster"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-barrier-cluster",
-        "{} target floor or PTX provenance changed",
-        policy.id
-    );
-    let expected_modifiers: Vec<_> = std::iter::once("cluster")
-        .chain(recipe.suffix.split('.'))
-        .collect();
-    ensure!(
-        policy.expected_ptx.mnemonic == "barrier"
-            && policy.expected_ptx.modifiers == expected_modifiers
-            && policy.expected_ptx.operands.is_empty(),
-        "{} expected PTX does not match its exact cluster-barrier spelling",
-        policy.id
-    );
-    ensure!(
-        (recipe.ordering == ClusterBarrierOrdering::Relaxed) == recipe.suffix.contains(".relaxed")
-            && recipe.aligned == recipe.suffix.ends_with(".aligned")
-            && matches!(
-                (recipe.mode, recipe.ordering),
-                (
-                    ClusterBarrierMode::Arrive | ClusterBarrierMode::ArriveAligned,
-                    ClusterBarrierOrdering::Release
-                ) | (
-                    ClusterBarrierMode::ArriveRelaxed | ClusterBarrierMode::ArriveRelaxedAligned,
-                    ClusterBarrierOrdering::Relaxed
-                ) | (
-                    ClusterBarrierMode::Wait | ClusterBarrierMode::WaitAligned,
-                    ClusterBarrierOrdering::Acquire
-                )
-            ),
-        "{} cluster-barrier semantic recipe is inconsistent",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ])
-            && policy.backend_lowerings.iter().all(|lowering| {
-                lowering.minimum_ptx.as_deref() == Some(recipe.minimum_ptx)
-                    && lowering.minimum_sm.as_deref() == Some("sm_90")
-                    && !lowering.evidence_profile.trim().is_empty()
-            }),
-        "{} must define exactly the reviewed cluster-barrier backend routes",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "cluster barrier")?;
-    Ok(())
-}
-
-#[derive(Clone, Copy)]
-struct DebugControlRecipe {
-    id: &'static str,
-    operation_key: &'static str,
-    rust_name: &'static str,
-    rust_arguments: &'static [&'static str],
-    rust_result: &'static str,
-    compatibility_path: &'static str,
-    op_type: &'static str,
-    op_name: &'static str,
-    instruction: &'static str,
-    minimum_ptx: &'static str,
-    minimum_sm: Option<&'static str>,
-    section: &'static str,
-    anchor: &'static str,
-    adapter: DebugControlAdapter,
-    summary: &'static str,
-}
-
-fn debug_control_recipe(operation: DebugControlOperation) -> DebugControlRecipe {
-    match operation {
-        DebugControlOperation::Trap => DebugControlRecipe {
-            id: "trap",
-            operation_key: "debug.control.trap",
-            rust_name: "trap",
-            rust_arguments: &[],
-            rust_result: "!",
-            compatibility_path: "cuda_device::debug::trap",
-            op_type: "TrapOp",
-            op_name: "nvvm.trap",
-            instruction: "trap",
-            minimum_ptx: "1.0",
-            minimum_sm: None,
-            section: "9.7.20.4 Miscellaneous Instructions: trap",
-            anchor: "miscellaneous-instructions-trap",
-            adapter: DebugControlAdapter::Direct,
-            summary: "Aborts device execution and reports an interrupt to the host.",
-        },
-        DebugControlOperation::Breakpoint => DebugControlRecipe {
-            id: "breakpoint",
-            operation_key: "debug.control.breakpoint",
-            rust_name: "breakpoint",
-            rust_arguments: &[],
-            rust_result: "()",
-            compatibility_path: "cuda_device::debug::breakpoint",
-            op_type: "BreakpointOp",
-            op_name: "nvvm.brkpt",
-            instruction: "brkpt",
-            minimum_ptx: "1.0",
-            minimum_sm: Some("sm_11"),
-            section: "9.7.20.1 Miscellaneous Instructions: brkpt",
-            anchor: "miscellaneous-instructions-brkpt",
-            adapter: DebugControlAdapter::Direct,
-            summary: "Suspends device execution for a debugger breakpoint.",
-        },
-        DebugControlOperation::Pmevent => DebugControlRecipe {
-            id: "pmevent",
-            operation_key: "debug.profiler.event",
-            rust_name: "pmevent",
-            rust_arguments: &["u32"],
-            rust_result: "()",
-            compatibility_path: "cuda_device::debug::__prof_trigger",
-            op_type: "PmEventOp",
-            op_name: "nvvm.pmevent",
-            instruction: "pmevent",
-            minimum_ptx: "1.4",
-            minimum_sm: None,
-            section: "9.7.20.3 Miscellaneous Instructions: pmevent",
-            anchor: "miscellaneous-instructions-pmevent",
-            adapter: DebugControlAdapter::ConstGenericToImmediateU32,
-            summary: "Triggers one compile-time-selected performance monitor event.",
-        },
-    }
-}
-
-#[derive(Clone, Copy)]
-struct WgmmaControlRecipe {
-    mode: WgmmaControlMode,
-    abi_id: &'static str,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: &'static str,
-    selection_record: &'static str,
-    llvm_symbol: &'static str,
-    compatibility_path: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    suffix: &'static str,
-    adapter: WgmmaControlAdapter,
-    summary: &'static str,
-}
-
-fn wgmma_control_recipe(mode: WgmmaControlMode) -> WgmmaControlRecipe {
-    match mode {
-        WgmmaControlMode::Fence => WgmmaControlRecipe {
-            mode,
-            abi_id: "i0317",
-            id: "wgmma_fence",
-            operation_key: "wgmma.control.fence.sync.aligned",
-            source_record: "int_nvvm_wgmma_fence_sync_aligned",
-            selection_record: "WGMMA_FENCE_SYNC_ALIGNED",
-            llvm_symbol: "llvm.nvvm.wgmma.fence.sync.aligned",
-            compatibility_path: "cuda_device::wgmma::wgmma_fence",
-            dialect_op_type: "WgmmaFenceSyncAlignedOp",
-            dialect_op_name: "nvvm.wgmma_fence_sync_aligned",
-            suffix: "fence.sync.aligned",
-            adapter: WgmmaControlAdapter::NoArguments,
-            summary: "Orders register accesses before later WGMMA operations.",
-        },
-        WgmmaControlMode::CommitGroup => WgmmaControlRecipe {
-            mode,
-            abi_id: "i0318",
-            id: "wgmma_commit_group",
-            operation_key: "wgmma.control.commit_group.sync.aligned",
-            source_record: "int_nvvm_wgmma_commit_group_sync_aligned",
-            selection_record: "WGMMA_COMMIT_GROUP_SYNC_ALIGNED",
-            llvm_symbol: "llvm.nvvm.wgmma.commit_group.sync.aligned",
-            compatibility_path: "cuda_device::wgmma::wgmma_commit_group",
-            dialect_op_type: "WgmmaCommitGroupSyncAlignedOp",
-            dialect_op_name: "nvvm.wgmma_commit_group_sync_aligned",
-            suffix: "commit_group.sync.aligned",
-            adapter: WgmmaControlAdapter::NoArguments,
-            summary: "Commits prior uncommitted WGMMA operations as one group.",
-        },
-        WgmmaControlMode::WaitGroup => WgmmaControlRecipe {
-            mode,
-            abi_id: "i0319",
-            id: "wgmma_wait_group",
-            operation_key: "wgmma.control.wait_group.sync.aligned",
-            source_record: "int_nvvm_wgmma_wait_group_sync_aligned",
-            selection_record: "WGMMA_WAIT_GROUP_SYNC_ALIGNED",
-            llvm_symbol: "llvm.nvvm.wgmma.wait_group.sync.aligned",
-            compatibility_path: "cuda_device::wgmma::__wgmma_wait_group",
-            dialect_op_type: "WgmmaWaitGroupSyncAlignedOp",
-            dialect_op_name: "nvvm.wgmma_wait_group_sync_aligned",
-            suffix: "wait_group.sync.aligned",
-            adapter: WgmmaControlAdapter::ConstGenericU32ToI64Immediate,
-            summary: "Waits until at most the requested number of WGMMA groups remain pending.",
-        },
-    }
-}
-
-fn expand_debug_control_admission(
-    admission: &DebugControlAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "debug-control runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact debug-control admission requires both backend evidence profiles"
-    );
-    ensure!(
-        admission.operations
-            == [
-                DebugControlOperation::Trap,
-                DebugControlOperation::Breakpoint,
-                DebugControlOperation::Pmevent,
-            ],
-        "compact debug-control admission must list trap, breakpoint, and pmevent exactly once in canonical order"
-    );
-    ensure!(
-        admission.abi_ids.len() == admission.operations.len(),
-        "pending debug-control admission needs exactly three ABI IDs before aggregation"
-    );
-    let unique_abi_ids = admission.abi_ids.iter().collect::<BTreeSet<_>>();
-    ensure!(
-        unique_abi_ids.len() == admission.abi_ids.len(),
-        "debug-control ABI IDs must be unique"
-    );
-
-    admission
-        .operations
-        .iter()
-        .zip(&admission.abi_ids)
-        .map(|(&operation, abi_id)| {
-            validate_abi_id(abi_id)?;
-            let recipe = debug_control_recipe(operation);
-            let immediate = operation == DebugControlOperation::Pmevent;
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: abi_id.clone(),
-                operation_key: recipe.operation_key.into(),
-                family: "debug_control".into(),
-                source: Some(IntrinsicSource::PtxNative {
-                    instruction: recipe.instruction.into(),
-                }),
-                source_record: None,
-                rust_module: "debug".into(),
-                rust_name: recipe.rust_name.into(),
-                rust_arguments: recipe
-                    .rust_arguments
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                rust_result: recipe.rust_result.into(),
-                safe: true,
-                must_use: false,
-                safe_allowlist_reason: Some(
-                    match operation {
-                        DebugControlOperation::Trap => {
-                            "aborting the kernel has no memory-safety preconditions"
-                        }
-                        DebugControlOperation::Breakpoint => {
-                            "requesting a debugger breakpoint has no memory-safety preconditions"
-                        }
-                        DebugControlOperation::Pmevent => {
-                            "the importer accepts only the documented immediate event range"
-                        }
-                    }
-                    .into(),
-                ),
-                public_rust_path: format!("cuda_intrinsics::debug::{}", recipe.rust_name),
-                compatibility_rust_paths: vec![recipe.compatibility_path.into()],
-                dialect_op_type: recipe.op_type.into(),
-                dialect_op_name: recipe.op_name.into(),
-                dialect_operands: vec![],
-                dialect_results: vec![],
-                llvm_symbol: None,
-                resolved_llvm_symbol: None,
-                llvm_arguments: vec![],
-                llvm_results: vec![],
-                pure: false,
-                memory: "none".into(),
-                convergent: false,
-                execution_scope: "thread".into(),
-                minimum_ptx: recipe.minimum_ptx.into(),
-                minimum_sm: recipe.minimum_sm.map(Into::into),
-                ptx_result: "()".into(),
-                targets: "all".into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section: recipe.section.into(),
-                ptx_isa_url: format!(
-                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#{}",
-                    recipe.anchor
-                ),
-                lowering: "generated_debug_control".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.llvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some("3.2".into()),
-                        minimum_sm: Some("sm_20".into()),
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                        targets: None,
-                        // PTX floor is the inline-PTX mechanism floor, same as
-                        // the LlvmNvptx entry above; the hardware floor stays at
-                        // the probed sm_75 (backend-codegen evidence must sit
-                        // exactly at the hardware floor, and CUDA 13 cannot
-                        // probe older targets). Writing the probe PTX version
-                        // (9.3) here made every panic path unbuildable on the
-                        // NVVM-IR route: the floor exceeded the newest PTX
-                        // version cuda-oxide can request.
-                        minimum_ptx: Some("3.2".into()),
-                        minimum_sm: Some("sm_75".into()),
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: Some(DebugControl {
-                    operation,
-                    adapter: recipe.adapter,
-                    runtime_validation: admission.runtime_validation,
-                }),
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: recipe.instruction.into(),
-                    modifiers: vec![],
-                    operands: if immediate {
-                        vec![OperandPattern::Immediate]
-                    } else {
-                        vec![]
-                    },
-                },
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect()
-}
-
-fn validate_debug_control_policy(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-) -> Result<()> {
-    let debug = policy
-        .debug_control
-        .as_ref()
-        .with_context(|| format!("{} has no closed debug-control contract", policy.id))?;
-    let recipe = debug_control_recipe(debug.operation);
-    let immediate = debug.operation == DebugControlOperation::Pmevent;
-    ensure!(
-        debug.adapter == recipe.adapter
-            && debug.runtime_validation == RuntimeValidation::Unexecuted
-            && policy.id == recipe.id
-            && policy.operation_key == recipe.operation_key
-            && source
-                == &IntrinsicSource::PtxNative {
-                    instruction: recipe.instruction.into(),
-                }
-            && policy.source_record.is_none()
-            && policy.llvm_symbol.is_none()
-            && policy.resolved_llvm_symbol.is_none()
-            && policy.llvm_arguments.is_empty()
-            && policy.llvm_results.is_empty(),
-        "{} identity must remain PTX-native and match its closed debug-control recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "debug"
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == recipe.rust_arguments
-            && policy.rust_result == recipe.rust_result
-            && policy.safe
-            && !policy.must_use
-            && policy.public_rust_path == format!("cuda_intrinsics::debug::{}", recipe.rust_name)
-            && policy.compatibility_rust_paths == [recipe.compatibility_path],
-        "{} Rust API or compatibility adapter changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.op_type
-            && policy.dialect_op_name == recipe.op_name
-            && policy.dialect_operands.is_empty()
-            && policy.dialect_results.is_empty()
-            && policy.lowering == "generated_debug_control",
-        "{} dialect carrier or lowering changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread",
-        "{} debug-control effects changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == recipe.minimum_sm
-            && policy.targets == "all"
-            && policy.ptx_result == "()"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.section
-            && policy.ptx_isa_url
-                == format!(
-                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#{}",
-                    recipe.anchor
-                ),
-        "{} native target floor or PTX provenance changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == recipe.instruction
-            && policy.expected_ptx.modifiers.is_empty()
-            && policy.expected_ptx.operands
-                == if immediate {
-                    vec![OperandPattern::Immediate]
-                } else {
-                    vec![]
-                },
-        "{} expected PTX changed",
-        policy.id
-    );
-    ensure_exact_inline_ptx_backends(
-        policy,
-        [
-            (IntrinsicBackend::LlvmNvptx, "3.2", Some("sm_20")),
-            (IntrinsicBackend::LibNvvm, "3.2", Some("sm_75")),
-        ],
-        "debug-control",
-    )?;
-    ensure_no_other_family_contract(policy, "debug-control")?;
-    Ok(())
-}
-
-#[derive(Clone)]
-struct ClusterMemoryRecipe {
-    operation: ClusterMemoryOperation,
-    abi_id: &'static str,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: Option<&'static str>,
-    llvm_symbol: Option<&'static str>,
-    ptx_native_instruction: Option<&'static str>,
-    rust_arguments: &'static [&'static str],
-    rust_result: &'static str,
-    compatibility_paths: &'static [&'static str],
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    dialect_operands: &'static [&'static str],
-    dialect_results: &'static [&'static str],
-    llvm_arguments: &'static [&'static str],
-    llvm_results: &'static [&'static str],
-    adapter: ClusterMemoryAdapter,
-    source_contract: ClusterMemorySourceContract,
-    memory: &'static str,
-    expected_ptx: InstructionPattern,
-    inline_ptx: &'static str,
-    inline_constraints: &'static str,
-    ptx_isa_section: &'static str,
-    ptx_isa_anchor: &'static str,
-    summary: &'static str,
-}
-
-fn cluster_memory_recipe(operation: ClusterMemoryOperation) -> ClusterMemoryRecipe {
-    match operation {
-        ClusterMemoryOperation::MapSharedRank => ClusterMemoryRecipe {
-            operation,
-            abi_id: "i0320",
-            id: "map_shared_rank",
-            operation_key: "cluster.shared_address.map_rank",
-            source_record: Some("int_nvvm_mapa_shared_cluster"),
-            llvm_symbol: Some("llvm.nvvm.mapa.shared.cluster"),
-            ptx_native_instruction: None,
-            rust_arguments: &["*const u8", "u32"],
-            rust_result: "*const u8",
-            compatibility_paths: &[
-                "cuda_device::cluster::map_shared_rank",
-                "cuda_device::cluster::map_shared_rank_mut",
-            ],
-            dialect_op_type: "MapaSharedClusterOp",
-            dialect_op_name: "nvvm.mapa_shared_cluster",
-            dialect_operands: &["ptr", "i32"],
-            dialect_results: &["ptr"],
-            llvm_arguments: &["shared_ptr", "i32"],
-            llvm_results: &["shared_cluster_ptr"],
-            adapter: ClusterMemoryAdapter::GenericConstAndMutPointerRankToSamePointer,
-            source_contract: ClusterMemorySourceContract::LlvmMapaSharedClusterAs7IdentityInlinePtx,
-            memory: "none",
-            expected_ptx: InstructionPattern {
-                mnemonic: "mapa".into(),
-                modifiers: vec!["shared::cluster".into(), "u64".into()],
-                operands: vec![
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                    OperandPattern::Register,
-                ],
-            },
-            inline_ptx: "mapa.shared::cluster.u64 $0, $1, $2;",
-            inline_constraints: "=l,l,r",
-            ptx_isa_section: "9.7.9.24 Data Movement and Conversion Instructions: mapa",
-            ptx_isa_anchor: "data-movement-and-conversion-instructions-mapa",
-            summary: "Maps a CTA-shared address to the same offset in another cluster rank.",
-        },
-        ClusterMemoryOperation::ReadU32 => ClusterMemoryRecipe {
-            operation,
-            abi_id: "i0321",
-            id: "dsmem_read_u32",
-            operation_key: "cluster.shared_memory.map_rank_then_read_u32",
-            source_record: None,
-            llvm_symbol: None,
-            ptx_native_instruction: Some("mapa.shared::cluster.u64 + ld.shared::cluster.u32"),
-            rust_arguments: &["*const u32", "u32"],
-            rust_result: "u32",
-            compatibility_paths: &["cuda_device::cluster::dsmem_read_u32"],
-            dialect_op_type: "DsmemReadU32Op",
-            dialect_op_name: "nvvm.dsmem_read_u32",
-            dialect_operands: &["ptr", "i32"],
-            dialect_results: &["i32"],
-            llvm_arguments: &[],
-            llvm_results: &[],
-            adapter: ClusterMemoryAdapter::ConstU32PointerRankToU32,
-            source_contract: ClusterMemorySourceContract::PtxNativeMapaThenWeakClusterLoad,
-            memory: "read",
-            expected_ptx: InstructionPattern {
-                mnemonic: "ld".into(),
-                modifiers: vec!["shared::cluster".into(), "u32".into()],
-                operands: vec![OperandPattern::Register, OperandPattern::Address],
-            },
-            inline_ptx: "{ .reg .u64 %mapped; mapa.shared::cluster.u64 %mapped, $1, $2; ld.shared::cluster.u32 $0, [%mapped]; }",
-            inline_constraints: "=r,l,r,~{memory}",
-            ptx_isa_section: "9.7.9.8 Data Movement and Conversion Instructions: ld",
-            ptx_isa_anchor: "data-movement-and-conversion-instructions-ld",
-            summary: "Maps a CTA-shared address to another cluster rank and reads one weak u32 value.",
-        },
-    }
-}
-
-pub(crate) fn cluster_memory_inline_recipe(
-    operation: ClusterMemoryOperation,
-) -> (&'static str, &'static str) {
-    let recipe = cluster_memory_recipe(operation);
-    (recipe.inline_ptx, recipe.inline_constraints)
-}
-
-fn expand_cluster_memory_admission(
-    admission: &ClusterMemoryAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "cluster-memory runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact cluster-memory admission requires both backend evidence profiles"
-    );
-    let expected = [
-        ClusterMemoryOperation::MapSharedRank,
-        ClusterMemoryOperation::ReadU32,
-    ];
-    ensure!(
-        admission.variants.len() == expected.len()
-            && admission
-                .variants
-                .iter()
-                .map(|variant| variant.operation)
-                .eq(expected),
-        "compact cluster-memory admission must list map_shared_rank and read_u32 once in canonical order"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = cluster_memory_recipe(variant.operation);
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must keep reserved ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            let source =
-                recipe
-                    .ptx_native_instruction
-                    .map(|instruction| IntrinsicSource::PtxNative {
-                        instruction: instruction.into(),
-                    });
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: variant.abi_id.clone(),
-                operation_key: recipe.operation_key.into(),
-                family: "cluster_memory".into(),
-                source,
-                source_record: recipe.source_record.map(Into::into),
-                rust_module: "cluster".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments: recipe
-                    .rust_arguments
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                rust_result: recipe.rust_result.into(),
-                safe: false,
-                must_use: true,
-                safe_allowlist_reason: None,
-                public_rust_path: format!("cuda_intrinsics::cluster::{}", recipe.id),
-                compatibility_rust_paths: recipe
-                    .compatibility_paths
-                    .iter()
-                    .map(|path| (*path).into())
-                    .collect(),
-                dialect_op_type: recipe.dialect_op_type.into(),
-                dialect_op_name: recipe.dialect_op_name.into(),
-                dialect_operands: recipe
-                    .dialect_operands
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                dialect_results: recipe
-                    .dialect_results
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                llvm_symbol: recipe.llvm_symbol.map(Into::into),
-                resolved_llvm_symbol: None,
-                llvm_arguments: recipe
-                    .llvm_arguments
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                llvm_results: recipe
-                    .llvm_results
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                pure: false,
-                memory: recipe.memory.into(),
-                convergent: true,
-                execution_scope: "cluster".into(),
-                minimum_ptx: "7.8".into(),
-                minimum_sm: Some("sm_90".into()),
-                ptx_result: recipe.rust_result.into(),
-                targets: "all".into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section: recipe.ptx_isa_section.into(),
-                ptx_isa_url: format!(
-                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#{}",
-                    recipe.ptx_isa_anchor
-                ),
-                lowering: "generated_cluster_memory_inline_ptx".into(),
-                backend_lowerings: [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
-                    .into_iter()
-                    .map(|backend| OverlayBackendLowering {
-                        backend,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: match backend {
-                            IntrinsicBackend::LlvmNvptx => admission.llvm_evidence_profile.clone(),
-                            IntrinsicBackend::LibNvvm => admission.libnvvm_evidence_profile.clone(),
-                        },
-                        targets: None,
-                        minimum_ptx: Some("7.8".into()),
-                        minimum_sm: Some("sm_90".into()),
-                    })
-                    .collect(),
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: Some(ClusterMemory {
-                    operation: recipe.operation,
-                    adapter: recipe.adapter,
-                    source_contract: recipe.source_contract,
-                    runtime_validation: admission.runtime_validation,
-                }),
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: recipe.expected_ptx,
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect()
-}
-
-fn validate_cluster_memory_policy(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-    declaration: Option<&ImportedIntrinsic>,
-) -> Result<()> {
-    let cluster = policy
-        .cluster_memory
-        .as_ref()
-        .with_context(|| format!("{} has no closed cluster-memory contract", policy.id))?;
-    let recipe = cluster_memory_recipe(cluster.operation);
-    ensure!(
-        cluster.adapter == recipe.adapter
-            && cluster.source_contract == recipe.source_contract
-            && cluster.runtime_validation == RuntimeValidation::Unexecuted
-            && policy.id == recipe.id
-            && policy.operation_key == recipe.operation_key,
-        "{} does not match its closed cluster-memory identity",
-        policy.id
-    );
-    match cluster.source_contract {
-        ClusterMemorySourceContract::LlvmMapaSharedClusterAs7IdentityInlinePtx => {
-            let declaration = declaration.context("map_shared_rank requires its LLVM identity")?;
-            ensure!(
-                matches!(source, IntrinsicSource::LlvmImported { source_record }
-                    if source_record == "int_nvvm_mapa_shared_cluster")
-                    && policy.source.is_none()
-                    && policy.source_record.as_deref() == recipe.source_record
-                    && policy.llvm_symbol.as_deref() == recipe.llvm_symbol
-                    && declaration.arguments == ["shared_ptr", "i32"]
-                    && declaration.results == ["shared_cluster_ptr"]
-                    && declaration.properties
-                        == ["IntrNoMem", "IntrSpeculatable", "NoCapture<arg0>"],
-                "{} must retain the AS7-returning LLVM mapa record as identity only",
-                policy.id
-            );
-            let mut selections = Vec::new();
-            for selection in &declaration.selections {
-                if selection_matches_policy(policy, selection)? {
-                    selections.push(selection);
-                }
-            }
-            ensure!(
-                selections.len() == 2
-                    && selections
-                        .iter()
-                        .map(|selection| selection.source_record.as_str())
-                        .collect::<BTreeSet<_>>()
-                        == BTreeSet::from(["mapa_shared_cluster_64", "mapa_shared_cluster_64i",])
-                    && selections.iter().all(|selection| {
-                        selection.asm == "mapa.shared::cluster.u64 \t$d, $a, $b;"
-                            && selection.predicates
-                                == [
-                                    "Subtarget->getSmVersion() >= 90",
-                                    "Subtarget->getPTXVersion() >= 78",
-                                ]
-                    }),
-                "{} must retain both exact 64-bit mapa selections",
-                policy.id
-            );
-        }
-        ClusterMemorySourceContract::PtxNativeMapaThenWeakClusterLoad => ensure!(
-            matches!(source, IntrinsicSource::PtxNative { instruction }
-                if Some(instruction.as_str()) == recipe.ptx_native_instruction)
-                && policy.source_record.is_none()
-                && policy.llvm_symbol.is_none()
-                && declaration.is_none()
-                && policy.llvm_arguments.is_empty()
-                && policy.llvm_results.is_empty(),
-            "{} must remain a PTX-native mapa plus weak cluster-load composite",
-            policy.id
-        ),
-    }
-    ensure!(
-        policy.rust_module == "cluster"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == recipe.rust_arguments
-            && policy.rust_result == recipe.rust_result
-            && !policy.safe
-            && policy.must_use
-            && policy.public_rust_path == format!("cuda_intrinsics::cluster::{}", recipe.id)
-            && policy.compatibility_rust_paths == recipe.compatibility_paths,
-        "{} Rust API or compatibility paths changed",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == recipe.dialect_operands
-            && policy.dialect_results == recipe.dialect_results
-            && policy.llvm_arguments == recipe.llvm_arguments
-            && policy.llvm_results == recipe.llvm_results
-            && policy.lowering == "generated_cluster_memory_inline_ptx",
-        "{} dialect carrier or AS7 source boundary changed",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == recipe.memory
-            && policy.convergent
-            && policy.execution_scope == "cluster",
-        "{} effects changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == "7.8"
-            && policy.minimum_sm.as_deref() == Some("sm_90")
-            && policy.targets == "all"
-            && policy.ptx_result == recipe.rust_result
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.ptx_isa_section
-            && policy.ptx_isa_url
-                == format!(
-                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#{}",
-                    recipe.ptx_isa_anchor
-                ),
-        "{} PTX provenance or target floor changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx == recipe.expected_ptx,
-        "{} expected PTX changed",
-        policy.id
-    );
-    ensure_exact_inline_ptx_backends(
-        policy,
-        [
-            (IntrinsicBackend::LlvmNvptx, "7.8", Some("sm_90")),
-            (IntrinsicBackend::LibNvvm, "7.8", Some("sm_90")),
-        ],
-        "cluster-memory",
-    )?;
-    ensure_no_other_family_contract(policy, "cluster-memory")?;
-    Ok(())
-}
-
-#[derive(Clone)]
-struct MbarrierExtendedRecipe {
-    operation: MbarrierExtendedOperation,
-    abi_id: &'static str,
-    id: &'static str,
-    operation_key: &'static str,
-    source_record: Option<&'static str>,
-    llvm_symbol: Option<&'static str>,
-    ptx_native_instruction: Option<&'static str>,
-    rust_arguments: &'static [&'static str],
-    rust_result: &'static str,
-    must_use: bool,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    dialect_operands: &'static [&'static str],
-    dialect_results: &'static [&'static str],
-    llvm_arguments: &'static [&'static str],
-    llvm_results: &'static [&'static str],
-    llvm_properties: &'static [&'static str],
-    adapter: MbarrierExtendedAdapter,
-    source_contract: MbarrierExtendedSourceContract,
-    execution_scope: &'static str,
-    minimum_ptx: &'static str,
-    minimum_sm: &'static str,
-    ptx_result: &'static str,
-    expected_ptx: InstructionPattern,
-    inline_ptx: &'static str,
-    inline_constraints: &'static str,
-    ptx_isa_section: &'static str,
-    ptx_isa_url: &'static str,
-    summary: &'static str,
-}
-
-fn mbarrier_extended_recipe(operation: MbarrierExtendedOperation) -> MbarrierExtendedRecipe {
-    let instruction = |modifiers: &[&str], operands| InstructionPattern {
-        mnemonic: if modifiers.first() == Some(&"nanosleep") {
-            "nanosleep".into()
-        } else if modifiers.first() == Some(&"fence") {
-            "fence".into()
-        } else {
-            "mbarrier".into()
-        },
-        modifiers: modifiers[1..].iter().map(|value| (*value).into()).collect(),
-        operands,
-    };
-    match operation {
-        MbarrierExtendedOperation::ArriveExpectTxCta => MbarrierExtendedRecipe {
-            operation,
-            abi_id: "i0306",
-            id: "mbarrier_arrive_expect_tx",
-            operation_key: "barrier.mbarrier.arrive.expect_tx.shared.cta.release.cta",
-            source_record: Some("int_nvvm_mbarrier_arrive_expect_tx_scope_cta_space_cta"),
-            llvm_symbol: Some("llvm.nvvm.mbarrier.arrive.expect.tx.scope.cta.space.cta"),
-            ptx_native_instruction: None,
-            rust_arguments: &["*const u64", "u32", "u32"],
-            rust_result: "u64",
-            must_use: true,
-            dialect_op_type: "MbarrierArriveExpectTxSharedOp",
-            dialect_op_name: "nvvm.mbarrier_arrive_expect_tx_shared",
-            dialect_operands: &["ptr", "i32"],
-            dialect_results: &["i64"],
-            llvm_arguments: &["shared_ptr", "i32"],
-            llvm_results: &["i64"],
-            llvm_properties: &["IntrConvergent", "IntrNoCallback"],
-            adapter: MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount,
-            source_contract: MbarrierExtendedSourceContract::LlvmImported,
-            execution_scope: "cta",
-            minimum_ptx: "8.0",
-            minimum_sm: "sm_90",
-            ptx_result: "u64",
-            expected_ptx: instruction(
-                &[
-                    "mbarrier",
-                    "arrive",
-                    "expect_tx",
-                    "release",
-                    "cta",
-                    "shared::cta",
-                    "b64",
-                ],
-                vec![
-                    OperandPattern::Register,
-                    OperandPattern::Address,
-                    OperandPattern::Register,
-                ],
-            ),
-            inline_ptx: "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 $0, [$1], $2;",
-            inline_constraints: "=l,l,r,~{memory}",
-            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.arrive",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-arrive",
-            summary: "Arrives at a CTA-shared barrier and adds expected transaction bytes.",
-        },
-        MbarrierExtendedOperation::ArriveExpectTxCluster => MbarrierExtendedRecipe {
-            operation,
-            abi_id: "i0307",
-            id: "mbarrier_arrive_expect_tx_cluster",
-            operation_key: "barrier.mbarrier.arrive.expect_tx.shared.cta.relaxed.cluster",
-            source_record: Some(
-                "int_nvvm_mbarrier_arrive_expect_tx_relaxed_scope_cluster_space_cta",
-            ),
-            llvm_symbol: Some(
-                "llvm.nvvm.mbarrier.arrive.expect.tx.relaxed.scope.cluster.space.cta",
-            ),
-            ptx_native_instruction: None,
-            rust_arguments: &["*const u64", "u32", "u32"],
-            rust_result: "u64",
-            must_use: true,
-            dialect_op_type: "MbarrierArriveExpectTxClusterOp",
-            dialect_op_name: "nvvm.mbarrier_arrive_expect_tx_cluster",
-            dialect_operands: &["ptr", "i32"],
-            dialect_results: &["i64"],
-            llvm_arguments: &["shared_ptr", "i32"],
-            llvm_results: &["i64"],
-            llvm_properties: &["IntrArgMemOnly", "IntrConvergent", "IntrNoCallback"],
-            adapter: MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount,
-            source_contract: MbarrierExtendedSourceContract::LlvmImported,
-            execution_scope: "cluster",
-            minimum_ptx: "8.6",
-            minimum_sm: "sm_90",
-            ptx_result: "u64",
-            expected_ptx: instruction(
-                &[
-                    "mbarrier",
-                    "arrive",
-                    "expect_tx",
-                    "relaxed",
-                    "cluster",
-                    "shared::cta",
-                    "b64",
-                ],
-                vec![
-                    OperandPattern::Register,
-                    OperandPattern::Address,
-                    OperandPattern::Register,
-                ],
-            ),
-            inline_ptx: "mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 $0, [$1], $2;",
-            inline_constraints: "=l,l,r,~{memory}",
-            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.arrive",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-arrive",
-            summary: "Arrives at a CTA-shared barrier with cluster-scope transaction tracking.",
-        },
-        MbarrierExtendedOperation::ArriveRemoteCluster => MbarrierExtendedRecipe {
-            operation,
-            abi_id: "i0308",
-            id: "mbarrier_arrive_cluster",
-            operation_key: "barrier.mbarrier.arrive.shared.cluster.release.cluster.raw_address",
-            source_record: None,
-            llvm_symbol: None,
-            ptx_native_instruction: Some("mbarrier.arrive.release.cluster.shared::cluster.b64"),
-            rust_arguments: &["u64"],
-            rust_result: "()",
-            must_use: false,
-            dialect_op_type: "MbarrierArriveClusterOp",
-            dialect_op_name: "nvvm.mbarrier_arrive_cluster",
-            dialect_operands: &["i64"],
-            dialect_results: &[],
-            llvm_arguments: &[],
-            llvm_results: &[],
-            llvm_properties: &[],
-            adapter: MbarrierExtendedAdapter::RawClusterAddressToVoid,
-            source_contract: MbarrierExtendedSourceContract::PtxNativeRawClusterAddress,
-            execution_scope: "cluster",
-            minimum_ptx: "8.0",
-            minimum_sm: "sm_90",
-            ptx_result: "()",
-            expected_ptx: instruction(
-                &[
-                    "mbarrier",
-                    "arrive",
-                    "release",
-                    "cluster",
-                    "shared::cluster",
-                    "b64",
-                ],
-                vec![
-                    OperandPattern::Exact { value: "_".into() },
-                    OperandPattern::Address,
-                ],
-            ),
-            inline_ptx: "mbarrier.arrive.release.cluster.shared::cluster.b64 _, [$0];",
-            inline_constraints: "l,~{memory}",
-            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.arrive",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-arrive",
-            summary: "Arrives at a remote cluster-shared barrier through its raw address.",
-        },
-        MbarrierExtendedOperation::TryWaitTokenCta => MbarrierExtendedRecipe {
-            operation,
-            abi_id: "i0309",
-            id: "mbarrier_try_wait",
-            operation_key: "barrier.mbarrier.try_wait.shared.cta.token",
-            source_record: Some("int_nvvm_mbarrier_try_wait_scope_cta_space_cta"),
-            llvm_symbol: Some("llvm.nvvm.mbarrier.try.wait.scope.cta.space.cta"),
-            ptx_native_instruction: None,
-            rust_arguments: &["*const u64", "u64"],
-            rust_result: "bool",
-            must_use: true,
-            dialect_op_type: "MbarrierTryWaitSharedOp",
-            dialect_op_name: "nvvm.mbarrier_try_wait_shared",
-            dialect_operands: &["ptr", "i64"],
-            dialect_results: &["i1"],
-            llvm_arguments: &["shared_ptr", "i64"],
-            llvm_results: &["i1"],
-            llvm_properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
-            adapter: MbarrierExtendedAdapter::PointerTokenToPredicate,
-            source_contract: MbarrierExtendedSourceContract::LlvmImported,
-            execution_scope: "cta",
-            minimum_ptx: "7.8",
-            minimum_sm: "sm_90",
-            ptx_result: "bool",
-            expected_ptx: instruction(
-                &["mbarrier", "try_wait", "shared", "b64"],
-                vec![
-                    OperandPattern::Register,
-                    OperandPattern::Address,
-                    OperandPattern::Register,
-                ],
-            ),
-            inline_ptx: "{ .reg .pred %p0; mbarrier.try_wait.shared.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
-            inline_constraints: "=r,l,l,~{memory}",
-            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.test_wait / mbarrier.try_wait",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-mbarrier-try-wait",
-            summary: "Tests a CTA-shared barrier token with a scheduling hint.",
-        },
-        MbarrierExtendedOperation::TryWaitParityCta => MbarrierExtendedRecipe {
-            operation,
-            abi_id: "i0310",
-            id: "mbarrier_try_wait_parity",
-            operation_key: "barrier.mbarrier.try_wait.parity.shared.cta",
-            source_record: Some("int_nvvm_mbarrier_try_wait_parity_scope_cta_space_cta"),
-            llvm_symbol: Some("llvm.nvvm.mbarrier.try.wait.parity.scope.cta.space.cta"),
-            ptx_native_instruction: None,
-            rust_arguments: &["*const u64", "u32"],
-            rust_result: "bool",
-            must_use: true,
-            dialect_op_type: "MbarrierTryWaitParitySharedOp",
-            dialect_op_name: "nvvm.mbarrier_try_wait_parity_shared",
-            dialect_operands: &["ptr", "i32"],
-            dialect_results: &["i1"],
-            llvm_arguments: &["shared_ptr", "i32"],
-            llvm_results: &["i1"],
-            llvm_properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
-            adapter: MbarrierExtendedAdapter::PointerParityToPredicate,
-            source_contract: MbarrierExtendedSourceContract::LlvmImported,
-            execution_scope: "cta",
-            minimum_ptx: "7.8",
-            minimum_sm: "sm_90",
-            ptx_result: "bool",
-            expected_ptx: instruction(
-                &["mbarrier", "try_wait", "parity", "shared::cta", "b64"],
-                vec![
-                    OperandPattern::Register,
-                    OperandPattern::Address,
-                    OperandPattern::Register,
-                ],
-            ),
-            inline_ptx: "{ .reg .pred %p0; mbarrier.try_wait.parity.shared::cta.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
-            inline_constraints: "=r,l,r,~{memory}",
-            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.test_wait / mbarrier.try_wait",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-mbarrier-try-wait",
-            summary: "Tests a CTA-shared barrier phase by parity.",
-        },
-        MbarrierExtendedOperation::TryWaitParityCluster => MbarrierExtendedRecipe {
-            operation,
-            abi_id: "i0311",
-            id: "mbarrier_try_wait_parity_cluster",
-            operation_key: "barrier.mbarrier.try_wait.parity.shared.cta.acquire.cluster",
-            source_record: Some("int_nvvm_mbarrier_try_wait_parity_scope_cluster_space_cta"),
-            llvm_symbol: Some("llvm.nvvm.mbarrier.try.wait.parity.scope.cluster.space.cta"),
-            ptx_native_instruction: None,
-            rust_arguments: &["*const u64", "u32"],
-            rust_result: "bool",
-            must_use: true,
-            dialect_op_type: "MbarrierTryWaitParityClusterOp",
-            dialect_op_name: "nvvm.mbarrier_try_wait_parity_cluster",
-            dialect_operands: &["ptr", "i32"],
-            dialect_results: &["i1"],
-            llvm_arguments: &["shared_ptr", "i32"],
-            llvm_results: &["i1"],
-            llvm_properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
-            adapter: MbarrierExtendedAdapter::PointerParityToPredicate,
-            source_contract: MbarrierExtendedSourceContract::LlvmImported,
-            execution_scope: "cluster",
-            minimum_ptx: "8.0",
-            minimum_sm: "sm_90",
-            ptx_result: "bool",
-            expected_ptx: instruction(
-                &[
-                    "mbarrier",
-                    "try_wait",
-                    "parity",
-                    "acquire",
-                    "cluster",
-                    "shared::cta",
-                    "b64",
-                ],
-                vec![
-                    OperandPattern::Register,
-                    OperandPattern::Address,
-                    OperandPattern::Register,
-                ],
-            ),
-            inline_ptx: "{ .reg .pred %p0; mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
-            inline_constraints: "=r,l,r,~{memory}",
-            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.test_wait / mbarrier.try_wait",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-mbarrier-try-wait",
-            summary: "Tests barrier parity with cluster-scope acquire ordering.",
-        },
-        MbarrierExtendedOperation::FenceProxyAsyncSharedCta => MbarrierExtendedRecipe {
-            operation,
-            abi_id: "i0312",
-            id: "fence_proxy_async_shared_cta",
-            operation_key: "fence.proxy.async.shared.cta",
-            source_record: Some("int_nvvm_fence_proxy_async_shared_cta"),
-            llvm_symbol: Some("llvm.nvvm.fence.proxy.async.shared_cta"),
-            ptx_native_instruction: None,
-            rust_arguments: &[],
-            rust_result: "()",
-            must_use: false,
-            dialect_op_type: "FenceProxyAsyncSharedCtaOp",
-            dialect_op_name: "nvvm.fence_proxy_async_shared_cta",
-            dialect_operands: &[],
-            dialect_results: &[],
-            llvm_arguments: &[],
-            llvm_results: &[],
-            llvm_properties: &["IntrNoCallback"],
-            adapter: MbarrierExtendedAdapter::ZeroOperandsToVoid,
-            source_contract: MbarrierExtendedSourceContract::LlvmImported,
-            execution_scope: "cta",
-            minimum_ptx: "8.0",
-            minimum_sm: "sm_90",
-            ptx_result: "()",
-            expected_ptx: instruction(&["fence", "proxy", "async", "shared::cta"], vec![]),
-            inline_ptx: "fence.proxy.async.shared::cta;",
-            inline_constraints: "~{memory}",
-            ptx_isa_section: "Parallel Synchronization and Communication Instructions: fence.proxy",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-fence-proxy",
-            summary: "Makes CTA-shared generic-proxy writes visible to the async proxy.",
-        },
-        MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster => MbarrierExtendedRecipe {
-            operation,
-            abi_id: "i0313",
-            id: "fence_mbarrier_init_release_cluster",
-            operation_key: "fence.mbarrier_init.release.cluster",
-            source_record: Some("int_nvvm_fence_mbarrier_init_release_cluster"),
-            llvm_symbol: Some("llvm.nvvm.fence.mbarrier_init.release.cluster"),
-            ptx_native_instruction: None,
-            rust_arguments: &[],
-            rust_result: "()",
-            must_use: false,
-            dialect_op_type: "FenceMbarrierInitReleaseClusterOp",
-            dialect_op_name: "nvvm.fence_mbarrier_init_release_cluster",
-            dialect_operands: &[],
-            dialect_results: &[],
-            llvm_arguments: &[],
-            llvm_results: &[],
-            llvm_properties: &["IntrNoCallback"],
-            adapter: MbarrierExtendedAdapter::ZeroOperandsToVoid,
-            source_contract: MbarrierExtendedSourceContract::LlvmImported,
-            execution_scope: "cluster",
-            minimum_ptx: "8.0",
-            minimum_sm: "sm_90",
-            ptx_result: "()",
-            expected_ptx: instruction(&["fence", "mbarrier_init", "release", "cluster"], vec![]),
-            inline_ptx: "fence.mbarrier_init.release.cluster;",
-            inline_constraints: "~{memory}",
-            ptx_isa_section: "Parallel Synchronization and Communication Instructions: fence.mbarrier_init",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-fence-mbarrier-init",
-            summary: "Releases mbarrier initialization at cluster scope.",
-        },
-        MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster => {
-            MbarrierExtendedRecipe {
-                operation,
-                abi_id: "i0314",
-                id: "fence_proxy_async_generic_release_shared_cta_cluster",
-                operation_key: "fence.proxy.async_generic.release.sync_restrict.shared_cta.cluster",
-                source_record: Some(
-                    "int_nvvm_fence_proxy_async_generic_release_sync_restrict_space_cta_scope_cluster",
-                ),
-                llvm_symbol: Some(
-                    "llvm.nvvm.fence.proxy.async_generic.release.sync_restrict.space.cta.scope.cluster",
-                ),
-                ptx_native_instruction: None,
-                rust_arguments: &[],
-                rust_result: "()",
-                must_use: false,
-                dialect_op_type: "FenceProxyAsyncGenericReleaseSharedCtaClusterOp",
-                dialect_op_name: "nvvm.fence_proxy_async_generic_release_shared_cta_cluster",
-                dialect_operands: &[],
-                dialect_results: &[],
-                llvm_arguments: &[],
-                llvm_results: &[],
-                llvm_properties: &["IntrNoCallback"],
-                adapter: MbarrierExtendedAdapter::ZeroOperandsToVoid,
-                source_contract: MbarrierExtendedSourceContract::LlvmImported,
-                execution_scope: "cluster",
-                minimum_ptx: "8.6",
-                minimum_sm: "sm_90",
-                ptx_result: "()",
-                expected_ptx: instruction(
-                    &[
-                        "fence",
-                        "proxy",
-                        "async::generic",
-                        "release",
-                        "sync_restrict::shared::cta",
-                        "cluster",
-                    ],
-                    vec![],
-                ),
-                inline_ptx: "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
-                inline_constraints: "~{memory}",
-                ptx_isa_section: "Parallel Synchronization and Communication Instructions: fence.proxy",
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-fence-proxy",
-                summary: "Releases CTA-shared generic-proxy writes to the async proxy at cluster scope.",
-            }
-        }
-        MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster => {
-            MbarrierExtendedRecipe {
-                operation,
-                abi_id: "i0315",
-                id: "fence_proxy_async_generic_acquire_shared_cluster_cluster",
-                operation_key: "fence.proxy.async_generic.acquire.sync_restrict.shared_cluster.cluster",
-                source_record: Some(
-                    "int_nvvm_fence_proxy_async_generic_acquire_sync_restrict_space_cluster_scope_cluster",
-                ),
-                llvm_symbol: Some(
-                    "llvm.nvvm.fence.proxy.async_generic.acquire.sync_restrict.space.cluster.scope.cluster",
-                ),
-                ptx_native_instruction: None,
-                rust_arguments: &[],
-                rust_result: "()",
-                must_use: false,
-                dialect_op_type: "FenceProxyAsyncGenericAcquireSharedClusterClusterOp",
-                dialect_op_name: "nvvm.fence_proxy_async_generic_acquire_shared_cluster_cluster",
-                dialect_operands: &[],
-                dialect_results: &[],
-                llvm_arguments: &[],
-                llvm_results: &[],
-                llvm_properties: &["IntrNoCallback"],
-                adapter: MbarrierExtendedAdapter::ZeroOperandsToVoid,
-                source_contract: MbarrierExtendedSourceContract::LlvmImported,
-                execution_scope: "cluster",
-                minimum_ptx: "8.6",
-                minimum_sm: "sm_90",
-                ptx_result: "()",
-                expected_ptx: instruction(
-                    &[
-                        "fence",
-                        "proxy",
-                        "async::generic",
-                        "acquire",
-                        "sync_restrict::shared::cluster",
-                        "cluster",
-                    ],
-                    vec![],
-                ),
-                inline_ptx: "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;",
-                inline_constraints: "~{memory}",
-                ptx_isa_section: "Parallel Synchronization and Communication Instructions: fence.proxy",
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-fence-proxy",
-                summary: "Acquires cluster-shared async-proxy writes through the generic proxy.",
-            }
-        }
-        MbarrierExtendedOperation::Nanosleep => MbarrierExtendedRecipe {
-            operation,
-            abi_id: "i0316",
-            id: "nanosleep",
-            operation_key: "thread.nanosleep.u32",
-            source_record: Some("int_nvvm_nanosleep"),
-            llvm_symbol: Some("llvm.nvvm.nanosleep"),
-            ptx_native_instruction: None,
-            rust_arguments: &["u32"],
-            rust_result: "()",
-            must_use: false,
-            dialect_op_type: "NanosleepOp",
-            dialect_op_name: "nvvm.nanosleep",
-            dialect_operands: &["i32"],
-            dialect_results: &[],
-            llvm_arguments: &["i32"],
-            llvm_results: &[],
-            llvm_properties: &["IntrConvergent", "IntrHasSideEffects", "IntrNoMem"],
-            adapter: MbarrierExtendedAdapter::NanosecondsToVoid,
-            source_contract: MbarrierExtendedSourceContract::LlvmImported,
-            execution_scope: "thread",
-            minimum_ptx: "6.3",
-            minimum_sm: "sm_70",
-            ptx_result: "()",
-            expected_ptx: instruction(
-                &["nanosleep", "u32"],
-                vec![OperandPattern::RegisterOrImmediate],
-            ),
-            inline_ptx: "nanosleep.u32 $0;",
-            inline_constraints: "r,~{memory}",
-            ptx_isa_section: "Parallel Synchronization and Communication Instructions: nanosleep",
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-nanosleep",
-            summary: "Suspends the executing thread for approximately the requested nanoseconds.",
-        },
-    }
-}
-
-pub(crate) fn mbarrier_extended_inline_recipe(
-    operation: MbarrierExtendedOperation,
-) -> (&'static str, &'static str) {
-    let recipe = mbarrier_extended_recipe(operation);
-    (recipe.inline_ptx, recipe.inline_constraints)
-}
-
-fn mbarrier_extended_backend_floor(
-    operation: MbarrierExtendedOperation,
-    backend: IntrinsicBackend,
-) -> (&'static str, &'static str) {
-    let recipe = mbarrier_extended_recipe(operation);
-    match (operation, backend) {
-        (MbarrierExtendedOperation::Nanosleep, IntrinsicBackend::LibNvvm) => ("6.3", "sm_75"),
-        _ => (recipe.minimum_ptx, recipe.minimum_sm),
-    }
-}
-
-fn expand_mbarrier_extended_admission(
-    admission: &MbarrierExtendedAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "extended-mbarrier runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact extended-mbarrier admission requires both backend evidence profiles"
-    );
-    let expected_operations = BTreeSet::from([
-        MbarrierExtendedOperation::ArriveExpectTxCta,
-        MbarrierExtendedOperation::ArriveExpectTxCluster,
-        MbarrierExtendedOperation::ArriveRemoteCluster,
-        MbarrierExtendedOperation::TryWaitTokenCta,
-        MbarrierExtendedOperation::TryWaitParityCta,
-        MbarrierExtendedOperation::TryWaitParityCluster,
-        MbarrierExtendedOperation::FenceProxyAsyncSharedCta,
-        MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster,
-        MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster,
-        MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster,
-        MbarrierExtendedOperation::Nanosleep,
-    ]);
-    let actual_operations = admission
-        .variants
-        .iter()
-        .map(|variant| variant.operation)
-        .collect::<BTreeSet<_>>();
-    ensure!(
-        admission.variants.len() == expected_operations.len()
-            && actual_operations == expected_operations,
-        "compact extended-mbarrier admission must contain each reviewed operation exactly once"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = mbarrier_extended_recipe(variant.operation);
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must keep reserved ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            let source =
-                recipe
-                    .ptx_native_instruction
-                    .map(|instruction| IntrinsicSource::PtxNative {
-                        instruction: instruction.into(),
-                    });
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: variant.abi_id.clone(),
-                operation_key: recipe.operation_key.into(),
-                family: "mbarrier_extended".into(),
-                source,
-                source_record: recipe.source_record.map(str::to_owned),
-                rust_module: "barrier".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments: recipe
-                    .rust_arguments
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                rust_result: recipe.rust_result.into(),
-                safe: false,
-                must_use: recipe.must_use,
-                safe_allowlist_reason: None,
-                public_rust_path: format!("cuda_intrinsics::barrier::{}", recipe.id),
-                compatibility_rust_paths: vec![format!("cuda_device::barrier::{}", recipe.id)],
-                dialect_op_type: recipe.dialect_op_type.into(),
-                dialect_op_name: recipe.dialect_op_name.into(),
-                dialect_operands: recipe
-                    .dialect_operands
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                dialect_results: recipe
-                    .dialect_results
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                llvm_symbol: recipe.llvm_symbol.map(str::to_owned),
-                resolved_llvm_symbol: None,
-                llvm_arguments: recipe
-                    .llvm_arguments
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                llvm_results: recipe
-                    .llvm_results
-                    .iter()
-                    .map(|value| (*value).into())
-                    .collect(),
-                pure: false,
-                memory: "read_write".into(),
-                convergent: true,
-                execution_scope: recipe.execution_scope.into(),
-                minimum_ptx: recipe.minimum_ptx.into(),
-                minimum_sm: Some(recipe.minimum_sm.into()),
-                ptx_result: recipe.ptx_result.into(),
-                targets: "all".into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section: recipe.ptx_isa_section.into(),
-                ptx_isa_url: recipe.ptx_isa_url.into(),
-                lowering: "generated_mbarrier_extended_inline_ptx".into(),
-                backend_lowerings: [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
-                    .into_iter()
-                    .map(|backend| {
-                        let (minimum_ptx, minimum_sm) =
-                            mbarrier_extended_backend_floor(recipe.operation, backend);
-                        OverlayBackendLowering {
-                            backend,
-                            mechanism: BackendLoweringMechanism::InlinePtx,
-                            evidence_profile: match backend {
-                                IntrinsicBackend::LlvmNvptx => {
-                                    admission.llvm_evidence_profile.clone()
-                                }
-                                IntrinsicBackend::LibNvvm => {
-                                    admission.libnvvm_evidence_profile.clone()
-                                }
-                            },
-                            targets: None,
-                            minimum_ptx: Some(minimum_ptx.into()),
-                            minimum_sm: Some(minimum_sm.into()),
-                        }
-                    })
-                    .collect(),
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: Some(MbarrierExtended {
-                    operation: recipe.operation,
-                    adapter: recipe.adapter,
-                    source_contract: recipe.source_contract,
-                    runtime_validation: admission.runtime_validation,
-                }),
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: None,
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: recipe.expected_ptx,
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect()
-}
-
-fn validate_mbarrier_extended_policy(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-    declaration: Option<&ImportedIntrinsic>,
-) -> Result<()> {
-    let contract = policy
-        .mbarrier_extended
-        .as_ref()
-        .with_context(|| format!("{} has no closed extended-mbarrier contract", policy.id))?;
-    let recipe = mbarrier_extended_recipe(contract.operation);
-    ensure!(
-        contract.adapter == recipe.adapter
-            && contract.source_contract == recipe.source_contract
-            && policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key,
-        "{} identity or adapter does not match its closed extended-mbarrier recipe",
-        policy.id
-    );
-    match recipe.source_contract {
-        MbarrierExtendedSourceContract::LlvmImported => ensure!(
-            matches!(
-                source,
-                IntrinsicSource::LlvmImported { source_record }
-                    if Some(source_record.as_str()) == recipe.source_record
-            ) && policy.source.is_none()
-                && policy.source_record.as_deref() == recipe.source_record
-                && policy.llvm_symbol.as_deref() == recipe.llvm_symbol
-                && declaration.is_some_and(|record| {
-                    record.source_record == recipe.source_record.unwrap()
-                        && record.properties == recipe.llvm_properties
-                }),
-            "{} LLVM source contract changed",
-            policy.id
-        ),
-        MbarrierExtendedSourceContract::PtxNativeRawClusterAddress => ensure!(
-            matches!(
-                source,
-                IntrinsicSource::PtxNative { instruction }
-                    if Some(instruction.as_str()) == recipe.ptx_native_instruction
-            ) && policy.source_record.is_none()
-                && policy.llvm_symbol.is_none()
-                && declaration.is_none(),
-            "{} must remain the PTX-native raw-cluster-address carrier",
-            policy.id
-        ),
-    }
-    ensure!(
-        policy.rust_module == "barrier"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments == recipe.rust_arguments
-            && policy.rust_result == recipe.rust_result
-            && !policy.safe
-            && policy.must_use == recipe.must_use
-            && policy.public_rust_path == format!("cuda_intrinsics::barrier::{}", recipe.id)
-            && policy.compatibility_rust_paths == [format!("cuda_device::barrier::{}", recipe.id)],
-        "{} Rust API does not match its closed extended-mbarrier recipe",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == recipe.dialect_operands
-            && policy.dialect_results == recipe.dialect_results
-            && policy.llvm_arguments == recipe.llvm_arguments
-            && policy.llvm_results == recipe.llvm_results
-            && policy.lowering == "generated_mbarrier_extended_inline_ptx",
-        "{} carrier or lowering does not match its closed extended-mbarrier recipe",
-        policy.id
-    );
-    ensure!(
-        !policy.pure
-            && policy.memory == "read_write"
-            && policy.convergent
-            && policy.execution_scope == recipe.execution_scope,
-        "{} convergence, memory clobber, or execution scope changed",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == recipe.minimum_ptx
-            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
-            && policy.ptx_result == recipe.ptx_result
-            && policy.targets == "all"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == recipe.ptx_isa_section
-            && policy.ptx_isa_url == recipe.ptx_isa_url,
-        "{} target floor or PTX provenance changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx == recipe.expected_ptx,
-        "{} expected PTX does not match its closed extended-mbarrier recipe",
-        policy.id
-    );
-    ensure_exact_inline_ptx_backends(
-        policy,
-        [
-            (
-                IntrinsicBackend::LlvmNvptx,
-                mbarrier_extended_backend_floor(recipe.operation, IntrinsicBackend::LlvmNvptx).0,
-                Some(
-                    mbarrier_extended_backend_floor(recipe.operation, IntrinsicBackend::LlvmNvptx)
-                        .1,
-                ),
-            ),
-            (
-                IntrinsicBackend::LibNvvm,
-                mbarrier_extended_backend_floor(recipe.operation, IntrinsicBackend::LibNvvm).0,
-                Some(
-                    mbarrier_extended_backend_floor(recipe.operation, IntrinsicBackend::LibNvvm).1,
-                ),
-            ),
-        ],
-        "extended-mbarrier",
-    )?;
-    ensure_no_other_family_contract(policy, "extended mbarrier")?;
-    Ok(())
-}
-
-fn expand_wgmma_control_admission(
-    admission: &WgmmaControlAdmission,
-) -> Result<Vec<OverlayIntrinsic>> {
-    ensure!(
-        admission.runtime_validation == RuntimeValidation::Unexecuted,
-        "WGMMA-control runtime validation may be marked executed only with GPU evidence"
-    );
-    ensure!(
-        !admission.llvm_evidence_profile.trim().is_empty()
-            && !admission.libnvvm_evidence_profile.trim().is_empty(),
-        "compact WGMMA-control admission requires both backend evidence profiles"
-    );
-    let expected_modes = [
-        WgmmaControlMode::Fence,
-        WgmmaControlMode::CommitGroup,
-        WgmmaControlMode::WaitGroup,
-    ];
-    let actual_modes = admission
-        .variants
-        .iter()
-        .map(|variant| variant.mode)
-        .collect::<Vec<_>>();
-    ensure!(
-        actual_modes == expected_modes,
-        "compact WGMMA-control admission must contain each reviewed mode once in canonical order"
-    );
-
-    admission
-        .variants
-        .iter()
-        .map(|variant| {
-            let recipe = wgmma_control_recipe(variant.mode);
-            ensure!(
-                variant.abi_id == recipe.abi_id,
-                "{} must keep reserved ABI ID {}",
-                recipe.id,
-                recipe.abi_id
-            );
-            let wait = recipe.mode == WgmmaControlMode::WaitGroup;
-            Ok(OverlayIntrinsic {
-                id: recipe.id.into(),
-                abi_id: variant.abi_id.clone(),
-                operation_key: recipe.operation_key.into(),
-                family: "wgmma_control".into(),
-                source: None,
-                source_record: Some(recipe.source_record.into()),
-                rust_module: "wgmma".into(),
-                rust_name: recipe.id.into(),
-                rust_arguments: if wait { vec!["u64".into()] } else { vec![] },
-                rust_result: "()".into(),
-                safe: false,
-                must_use: false,
-                safe_allowlist_reason: None,
-                public_rust_path: format!("cuda_intrinsics::wgmma::{}", recipe.id),
-                compatibility_rust_paths: vec![recipe.compatibility_path.into()],
-                dialect_op_type: recipe.dialect_op_type.into(),
-                dialect_op_name: recipe.dialect_op_name.into(),
-                dialect_operands: if wait { vec!["i64".into()] } else { vec![] },
-                dialect_results: vec![],
-                llvm_symbol: Some(recipe.llvm_symbol.into()),
-                resolved_llvm_symbol: None,
-                llvm_arguments: if wait { vec!["i64".into()] } else { vec![] },
-                llvm_results: vec![],
-                pure: false,
-                memory: "read_write".into(),
-                convergent: true,
-                execution_scope: "warpgroup".into(),
-                minimum_ptx: "8.0".into(),
-                minimum_sm: None,
-                ptx_result: "()".into(),
-                targets: "sm_90a".into(),
-                ptx_isa_version: "9.3".into(),
-                ptx_isa_section:
-                    "Asynchronous Warpgroup Level Matrix Instructions: WGMMA control".into(),
-                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#asynchronous-warpgroup-level-matrix-instructions".into(),
-                lowering: "generated_wgmma_control".into(),
-                backend_lowerings: vec![
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LlvmNvptx,
-                        mechanism: BackendLoweringMechanism::TypedNvvm,
-                        evidence_profile: admission.llvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some("8.0".into()),
-                        minimum_sm: None,
-                    },
-                    OverlayBackendLowering {
-                        backend: IntrinsicBackend::LibNvvm,
-                        mechanism: BackendLoweringMechanism::InlinePtx,
-                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
-                        targets: None,
-                        minimum_ptx: Some("8.0".into()),
-                        minimum_sm: None,
-                    },
-                ],
-                packed_atomic: None,
-                redux: None,
-                vote: None,
-                active_mask: None,
-                warp_match: None,
-                warp_barrier: None,
-                warp_shuffle: None,
-                dot_product: None,
-                packed_alu: None,
-                integer_minmax: None,
-                packed_conversion: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cp_async_copy: None,
-                cp_async_control: None,
-                cp_async_mbarrier: None,
-                mbarrier_basic: None,
-                movmatrix: None,
-                mbarrier_extended: None,
-                register_mma: None,
-                sparse_mma: None,
-                prmt: None,
-                cluster_barrier: None,
-                wgmma_control: Some(WgmmaControl {
-                    mode: recipe.mode,
-                    adapter: recipe.adapter,
-                    participation: WgmmaControlParticipation::WarpgroupAllThreadsSameInstruction,
-                }),
-                special_register: None,
-                debug_control: None,
-                cluster_memory: None,
-                clc: None,
-                tma: None,
-                tcgen05: None,
-                ldmatrix_variant: None,
-                ldmatrix_safety: None,
-                ldmatrix_adapter: None,
-                selected_address_space: None,
-                expected_ptx: InstructionPattern {
-                    mnemonic: "wgmma".into(),
-                    modifiers: recipe.suffix.split('.').map(str::to_owned).collect(),
-                    operands: if wait {
-                        vec![OperandPattern::Immediate]
-                    } else {
-                        vec![]
-                    },
-                },
-                summary: recipe.summary.into(),
-            })
-        })
-        .collect()
-}
-
-fn validate_wgmma_control_policy(
-    policy: &OverlayIntrinsic,
-    declaration: &ImportedIntrinsic,
-) -> Result<()> {
-    let control = policy
-        .wgmma_control
-        .as_ref()
-        .with_context(|| format!("{} has no closed WGMMA-control contract", policy.id))?;
-    let recipe = wgmma_control_recipe(control.mode);
-    let wait = recipe.mode == WgmmaControlMode::WaitGroup;
-    ensure!(
-        control.adapter == recipe.adapter
-            && control.participation
-                == WgmmaControlParticipation::WarpgroupAllThreadsSameInstruction
-            && policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key
-            && policy.source.is_none()
-            && policy.source_record.as_deref() == Some(recipe.source_record)
-            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
-            && policy.resolved_llvm_symbol.is_none(),
-        "{} identity or semantics do not match its closed WGMMA-control recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == "wgmma"
-            && policy.rust_name == recipe.id
-            && policy.rust_arguments
-                == if wait {
-                    vec!["u64"]
-                } else {
-                    Vec::<&str>::new()
-                }
-            && policy.rust_result == "()"
-            && !policy.safe
-            && !policy.must_use
-            && policy.public_rust_path == format!("cuda_intrinsics::wgmma::{}", recipe.id)
-            && policy.compatibility_rust_paths == [recipe.compatibility_path],
-        "{} Rust API does not match its closed WGMMA-control recipe",
-        policy.id
-    );
-    let expected_arguments = if wait {
-        vec!["i64"]
-    } else {
-        Vec::<&str>::new()
-    };
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == expected_arguments
-            && policy.dialect_results.is_empty()
-            && policy.llvm_arguments == expected_arguments
-            && policy.llvm_results.is_empty()
-            && policy.lowering == "generated_wgmma_control",
-        "{} carrier or lowering does not match its closed WGMMA-control recipe",
-        policy.id
-    );
-    let expected_properties = if wait {
-        vec!["ImmArg<arg0>", "IntrConvergent"]
-    } else {
-        vec!["IntrConvergent"]
-    };
-    ensure!(
-        declaration.classes == ["SDPatternOperator", "Intrinsic"]
-            && declaration.properties == expected_properties
-            && !policy.pure
-            && policy.memory == "read_write"
-            && policy.convergent
-            && policy.execution_scope == "warpgroup",
-        "{} effects disagree with the imported WGMMA-control declaration",
-        policy.id
-    );
-    ensure!(
-        policy.minimum_ptx == "8.0"
-            && policy.minimum_sm.is_none()
-            && policy.targets == "sm_90a"
-            && policy.ptx_result == "()"
-            && policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_url
-                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#asynchronous-warpgroup-level-matrix-instructions",
-        "{} target floor or PTX provenance changed",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic == "wgmma"
-            && policy.expected_ptx.modifiers == recipe.suffix.split('.').collect::<Vec<_>>()
-            && policy.expected_ptx.operands
-                == if wait {
-                    vec![OperandPattern::Immediate]
-                } else {
-                    vec![]
-                },
-        "{} expected PTX does not match its exact WGMMA-control spelling",
-        policy.id
-    );
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::TypedNvvm,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ])
-            && policy.backend_lowerings.iter().all(|lowering| {
-                lowering.minimum_ptx.as_deref() == Some("8.0")
-                    && lowering.minimum_sm.is_none()
-                    && !lowering.evidence_profile.trim().is_empty()
-            }),
-        "{} must define exactly the reviewed WGMMA-control backend routes",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "WGMMA control")?;
-    Ok(())
-}
-
-fn ensure_exact_inline_ptx_backends(
-    policy: &OverlayIntrinsic,
-    requirements: [(IntrinsicBackend, &str, Option<&str>); 2],
-    family: &str,
-) -> Result<()> {
-    let backend_pairs: BTreeSet<_> = policy
-        .backend_lowerings
-        .iter()
-        .map(|lowering| (lowering.backend, lowering.mechanism))
-        .collect();
-    ensure!(
-        policy.backend_lowerings.len() == 2
-            && backend_pairs
-                == BTreeSet::from([
-                    (
-                        IntrinsicBackend::LlvmNvptx,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                    (
-                        IntrinsicBackend::LibNvvm,
-                        BackendLoweringMechanism::InlinePtx,
-                    ),
-                ]),
-        "{} must define exactly two reviewed {family} inline-PTX routes",
-        policy.id
-    );
-    let requirements: BTreeMap<_, _> = requirements
-        .into_iter()
-        .map(|(backend, ptx, minimum_sm)| (backend, (ptx, minimum_sm)))
-        .collect();
-    for lowering in &policy.backend_lowerings {
-        let (minimum_ptx, minimum_sm) = requirements[&lowering.backend];
-        ensure!(
-            lowering.minimum_ptx.as_deref() == Some(minimum_ptx)
-                && lowering.minimum_sm.as_deref() == minimum_sm
-                && !lowering.evidence_profile.trim().is_empty(),
-            "{} backend {:?} does not carry its exact {family} floor",
-            policy.id,
-            lowering.backend
-        );
-    }
-    Ok(())
-}
-
-fn validate_movmatrix_policy(policy: &OverlayIntrinsic, source: &IntrinsicSource) -> Result<()> {
-    let contract = policy
-        .movmatrix
-        .as_ref()
-        .context("movmatrix requires its closed contract")?;
-    ensure!(
-        policy.id == "movmatrix_trans_b16"
-            && policy.operation_key == "movmatrix.m8n8.trans.b16"
-            && matches!(
-                source,
-                IntrinsicSource::PtxNative { instruction }
-                    if instruction == "movmatrix.sync.aligned.m8n8.trans.b16"
-            )
-            && policy.rust_module == "matrix"
-            && policy.rust_name == "movmatrix_trans_b16"
-            && policy.rust_arguments == ["u32"]
-            && policy.rust_result == "u32"
-            && !policy.safe
-            && policy.must_use
-            && policy.public_rust_path == "cuda_intrinsics::matrix::movmatrix_trans_b16"
-            && policy.compatibility_rust_paths == ["cuda_device::wmma::movmatrix_trans_b16"]
-            && policy.dialect_op_type == "MovmatrixTransB16Op"
-            && policy.dialect_op_name == "nvvm.movmatrix_trans_b16"
-            && policy.dialect_operands == ["i32"]
-            && policy.dialect_results == ["i32"]
-            && !policy.pure
-            && policy.memory == "inaccessible_read_write"
-            && policy.convergent
-            && policy.execution_scope == "warp"
-            && policy.minimum_ptx == "7.8"
-            && policy.minimum_sm.as_deref() == Some("sm_75")
-            && policy.ptx_result == "u32"
-            && policy.targets == "all"
-            && policy.lowering == "generated_movmatrix_inline_ptx"
-            && policy.expected_ptx
-                == InstructionPattern {
-                    mnemonic: "movmatrix".into(),
-                    modifiers: ["sync", "aligned", "m8n8", "trans", "b16"]
-                        .into_iter()
-                        .map(str::to_owned)
-                        .collect(),
-                    operands: vec![OperandPattern::Register, OperandPattern::Register],
-                },
-        "{} is outside the closed movmatrix recipe",
-        policy.id
-    );
-    ensure!(
-        contract.participation == MovmatrixParticipation::AllWarpLanesSameInstructionNoExitedLanes
-            && contract.adapter == MovmatrixAdapter::PackedB16x2U32ToPackedB16x2U32,
-        "{} has an unreviewed movmatrix safety or adapter contract",
-        policy.id
-    );
-    ensure_exact_inline_ptx_backends(
-        policy,
-        [
-            (IntrinsicBackend::LlvmNvptx, "7.8", Some("sm_75")),
-            (IntrinsicBackend::LibNvvm, "7.8", Some("sm_75")),
-        ],
-        "movmatrix",
-    )?;
-    ensure_no_other_family_contract(policy, "movmatrix")?;
-    Ok(())
-}
-
-struct IntegerMinMaxRecipe {
-    id: &'static str,
-    abi_id: &'static str,
-    operation_key: &'static str,
-    rust_module: &'static str,
-    rust_name: &'static str,
-    /// Rust and PTX carrier type: `i32` for the scalar forms, `u32` for the
-    /// packed pairs.
-    scalar: &'static str,
-    dialect_op_type: &'static str,
-    dialect_op_name: &'static str,
-    ptx_mnemonic: &'static str,
-    modifiers: &'static [&'static str],
-}
-
-/// Returns the closed recipe for an extended integer min/max variant.
-///
-/// `None` means the combination is outside the family: `.relu` exists only
-/// for the signed formats, and the plain scalar forms are ordinary codegen
-/// (`min.s32`/`max.s32` from generic Rust min/max), not intrinsics.
-fn integer_minmax_recipe(
-    format: IntegerMinMaxFormat,
-    operation: IntegerMinMaxOperation,
-    relu: bool,
-) -> Option<IntegerMinMaxRecipe> {
-    use IntegerMinMaxFormat as Format;
-    use IntegerMinMaxOperation as Operation;
-    Some(match (format, operation, relu) {
-        (Format::S32, Operation::Min, true) => IntegerMinMaxRecipe {
-            id: "min_relu_s32",
-            abi_id: "i0987",
-            operation_key: "integer.minmax.s32.min.relu",
-            rust_module: "int",
-            rust_name: "min_relu_s32",
-            scalar: "i32",
-            dialect_op_type: "MinReluS32Op",
-            dialect_op_name: "nvvm.min_relu_s32",
-            ptx_mnemonic: "min.relu.s32",
-            modifiers: &["relu", "s32"],
-        },
-        (Format::S32, Operation::Max, true) => IntegerMinMaxRecipe {
-            id: "max_relu_s32",
-            abi_id: "i0988",
-            operation_key: "integer.minmax.s32.max.relu",
-            rust_module: "int",
-            rust_name: "max_relu_s32",
-            scalar: "i32",
-            dialect_op_type: "MaxReluS32Op",
-            dialect_op_name: "nvvm.max_relu_s32",
-            ptx_mnemonic: "max.relu.s32",
-            modifiers: &["relu", "s32"],
-        },
-        (Format::S16x2, Operation::Min, false) => IntegerMinMaxRecipe {
-            id: "min_s16x2",
-            abi_id: "i0989",
-            operation_key: "integer.minmax.s16x2.min",
-            rust_module: "i16x2",
-            rust_name: "min_s16x2",
-            scalar: "u32",
-            dialect_op_type: "MinS16x2Op",
-            dialect_op_name: "nvvm.min_s16x2",
-            ptx_mnemonic: "min.s16x2",
-            modifiers: &["s16x2"],
-        },
-        (Format::S16x2, Operation::Max, false) => IntegerMinMaxRecipe {
-            id: "max_s16x2",
-            abi_id: "i0990",
-            operation_key: "integer.minmax.s16x2.max",
-            rust_module: "i16x2",
-            rust_name: "max_s16x2",
-            scalar: "u32",
-            dialect_op_type: "MaxS16x2Op",
-            dialect_op_name: "nvvm.max_s16x2",
-            ptx_mnemonic: "max.s16x2",
-            modifiers: &["s16x2"],
-        },
-        (Format::U16x2, Operation::Min, false) => IntegerMinMaxRecipe {
-            id: "min_u16x2",
-            abi_id: "i0991",
-            operation_key: "integer.minmax.u16x2.min",
-            rust_module: "i16x2",
-            rust_name: "min_u16x2",
-            scalar: "u32",
-            dialect_op_type: "MinU16x2Op",
-            dialect_op_name: "nvvm.min_u16x2",
-            ptx_mnemonic: "min.u16x2",
-            modifiers: &["u16x2"],
-        },
-        (Format::U16x2, Operation::Max, false) => IntegerMinMaxRecipe {
-            id: "max_u16x2",
-            abi_id: "i0992",
-            operation_key: "integer.minmax.u16x2.max",
-            rust_module: "i16x2",
-            rust_name: "max_u16x2",
-            scalar: "u32",
-            dialect_op_type: "MaxU16x2Op",
-            dialect_op_name: "nvvm.max_u16x2",
-            ptx_mnemonic: "max.u16x2",
-            modifiers: &["u16x2"],
-        },
-        (Format::S16x2, Operation::Min, true) => IntegerMinMaxRecipe {
-            id: "min_relu_s16x2",
-            abi_id: "i0993",
-            operation_key: "integer.minmax.s16x2.min.relu",
-            rust_module: "i16x2",
-            rust_name: "min_relu_s16x2",
-            scalar: "u32",
-            dialect_op_type: "MinReluS16x2Op",
-            dialect_op_name: "nvvm.min_relu_s16x2",
-            ptx_mnemonic: "min.relu.s16x2",
-            modifiers: &["relu", "s16x2"],
-        },
-        (Format::S16x2, Operation::Max, true) => IntegerMinMaxRecipe {
-            id: "max_relu_s16x2",
-            abi_id: "i0994",
-            operation_key: "integer.minmax.s16x2.max.relu",
-            rust_module: "i16x2",
-            rust_name: "max_relu_s16x2",
-            scalar: "u32",
-            dialect_op_type: "MaxReluS16x2Op",
-            dialect_op_name: "nvvm.max_relu_s16x2",
-            ptx_mnemonic: "max.relu.s16x2",
-            modifiers: &["relu", "s16x2"],
-        },
-        (Format::S32, _, false) | (Format::U16x2, _, true) => return None,
-    })
-}
-
-fn integer_minmax_isa_reference(operation: IntegerMinMaxOperation) -> (&'static str, &'static str) {
-    match operation {
-        IntegerMinMaxOperation::Min => (
-            "9.7.1.13 Integer Arithmetic Instructions: min",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#integer-arithmetic-instructions-min",
-        ),
-        IntegerMinMaxOperation::Max => (
-            "9.7.1.14 Integer Arithmetic Instructions: max",
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#integer-arithmetic-instructions-max",
-        ),
-    }
-}
-
-fn validate_integer_minmax_policy(
-    policy: &OverlayIntrinsic,
-    source: &IntrinsicSource,
-    declaration: Option<&ImportedIntrinsic>,
-) -> Result<()> {
-    let minmax = policy
-        .integer_minmax
-        .as_ref()
-        .with_context(|| format!("{} has no closed integer-min/max contract", policy.id))?;
-    let recipe = integer_minmax_recipe(minmax.format, minmax.operation, minmax.relu)
-        .with_context(|| format!("{} is outside the closed integer-min/max recipe", policy.id))?;
-    ensure!(
-        policy.id == recipe.id
-            && policy.abi_id == recipe.abi_id
-            && policy.operation_key == recipe.operation_key,
-        "{} integer-min/max identity does not match its closed operation recipe",
-        policy.id
-    );
-    ensure!(
-        policy.rust_module == recipe.rust_module
-            && policy.rust_name == recipe.rust_name
-            && policy.rust_arguments == [recipe.scalar, recipe.scalar]
-            && policy.rust_result == recipe.scalar
-            && policy.safe
-            && policy.must_use
-            && policy
-                .safe_allowlist_reason
-                .as_deref()
-                .is_some_and(|reason| !reason.trim().is_empty())
-            && policy.public_rust_path
-                == format!(
-                    "cuda_intrinsics::{}::{}",
-                    recipe.rust_module, recipe.rust_name
-                )
-            && policy.compatibility_rust_paths
-                == [format!(
-                    "cuda_device::{}::{}",
-                    recipe.rust_module, recipe.rust_name
-                )],
-        "{} must preserve its reviewed safe integer-min/max API",
-        policy.id
-    );
-    ensure!(
-        policy.dialect_op_type == recipe.dialect_op_type
-            && policy.dialect_op_name == recipe.dialect_op_name
-            && policy.dialect_operands == ["i32", "i32"]
-            && policy.dialect_results == ["i32"]
-            && policy.lowering == "generated_integer_minmax_inline_ptx",
-        "{} is outside the closed integer-min/max dialect and lowering recipe",
-        policy.id
-    );
-    ensure!(
-        policy.pure
-            && policy.memory == "none"
-            && !policy.convergent
-            && policy.execution_scope == "thread"
-            && policy.minimum_ptx == "8.0"
-            && policy.minimum_sm.as_deref() == Some("sm_90")
-            && policy.ptx_result == recipe.scalar
-            && policy.targets == "all"
-            && minmax.native_minimum_sm == 90,
-        "{} integer-min/max effects, carrier, or target floor disagree",
-        policy.id
-    );
-    let (isa_section, isa_url) = integer_minmax_isa_reference(minmax.operation);
-    ensure!(
-        policy.ptx_isa_version == "9.3"
-            && policy.ptx_isa_section == isa_section
-            && policy.ptx_isa_url == isa_url,
-        "{} integer-min/max PTX provenance does not match its reviewed instruction section",
-        policy.id
-    );
-    ensure!(
-        policy.expected_ptx.mnemonic
-            == recipe.ptx_mnemonic.split('.').next().expect("PTX mnemonic")
-            && policy.expected_ptx.modifiers == recipe.modifiers
-            && policy.expected_ptx.operands == vec![OperandPattern::Register; 3],
-        "{} expected PTX does not match its exact integer-min/max instruction",
-        policy.id
-    );
-    ensure!(
-        source
-            == &IntrinsicSource::PtxNative {
-                instruction: recipe.ptx_mnemonic.to_owned(),
-            }
-            && declaration.is_none(),
-        "{} integer-min/max source does not match its PTX-native recipe",
-        policy.id
-    );
-    ensure!(
-        policy.backend_lowerings.len() == 1
-            && policy.backend_lowerings[0].backend == IntrinsicBackend::LlvmNvptx
-            && policy.backend_lowerings[0].mechanism == BackendLoweringMechanism::InlinePtx
-            && policy.backend_lowerings[0].targets.is_none()
-            && policy.backend_lowerings[0].minimum_ptx.is_none()
-            && policy.backend_lowerings[0].minimum_sm.is_none()
-            && !policy.backend_lowerings[0]
-                .evidence_profile
-                .trim()
-                .is_empty(),
-        "{} integer-min/max backend route changed",
-        policy.id
-    );
-    ensure_no_other_family_contract(policy, "integer_minmax")?;
-    Ok(())
-}
-
-fn ensure_no_other_family_contract(policy: &OverlayIntrinsic, family: &str) -> Result<()> {
-    ensure!(
-        policy.packed_atomic.is_none()
-            && policy.redux.is_none()
-            && policy.vote.is_none()
-            && policy.active_mask.is_none()
-            && policy.warp_match.is_none()
-            && policy.warp_barrier.is_none()
-            && policy.warp_shuffle.is_none()
-            && policy.dot_product.is_none()
-            && policy.ldmatrix_variant.is_none()
-            && policy.ldmatrix_safety.is_none()
-            && policy.ldmatrix_adapter.is_none()
-            && (policy.family == "tma" || policy.selected_address_space.is_none())
-            && (policy.family == "packed_alu") == policy.packed_alu.is_some()
-            && (policy.family == "integer_minmax") == policy.integer_minmax.is_some()
-            && (policy.family == "packed_conversion") == policy.packed_conversion.is_some()
-            && (policy.family == "scalar_conversion") == policy.scalar_conversion.is_some()
-            && (policy.family == "scalar_arithmetic") == policy.scalar_arithmetic.is_some()
-            && (policy.family == "scalar_math") == policy.scalar_math.is_some()
-            && (policy.family == "extended_minmax") == policy.extended_minmax.is_some()
-            && (policy.family == "cp_async_copy") == policy.cp_async_copy.is_some()
-            && (policy.family == "cp_async_control") == policy.cp_async_control.is_some()
-            && (policy.family == "cp_async_mbarrier") == policy.cp_async_mbarrier.is_some()
-            && (policy.family == "mbarrier_basic") == policy.mbarrier_basic.is_some()
-            && (policy.family == "movmatrix") == policy.movmatrix.is_some()
-            && (policy.family == "mbarrier_extended") == policy.mbarrier_extended.is_some()
-            && (policy.family == "register_mma") == policy.register_mma.is_some()
-            && (policy.family == "sparse_mma") == policy.sparse_mma.is_some()
-            && (policy.family == "prmt") == policy.prmt.is_some()
-            && (policy.family == "cluster_barrier") == policy.cluster_barrier.is_some()
-            && (policy.family == "wgmma_control") == policy.wgmma_control.is_some()
-            && (policy.family == "debug_control") == policy.debug_control.is_some()
-            && (policy.family == "cluster_memory") == policy.cluster_memory.is_some()
-            && (policy.family == "clc") == policy.clc.is_some()
-            && (policy.family == "tma") == policy.tma.is_some()
-            && (policy.family == "tcgen05") == policy.tcgen05.is_some(),
-        "{} mixes another generated-family contract with {family}",
-        policy.id
-    );
-    Ok(())
-}
-
-fn parse_ptx_version(value: &str, intrinsic_id: &str) -> Result<PtxVersion> {
-    value
-        .parse()
-        .map_err(|reason: String| anyhow::anyhow!("{intrinsic_id} minimum_ptx {value:?}: {reason}"))
-}
-
-fn parse_hardware_target(policy: &OverlayIntrinsic) -> Result<CatalogHardwareTarget> {
-    parse_hardware_target_fields(&policy.id, &policy.targets, policy.minimum_sm.as_deref())
-}
-
-/// Resolve every selector contract without merging target sets.
-pub(crate) fn resolve_target_contracts(
-    intrinsic_id: &str,
-    contracts: &[TargetContract],
-) -> Result<CatalogTargetRequirement> {
-    ensure!(
-        !contracts.is_empty(),
-        "{intrinsic_id} has no reviewed target contracts"
-    );
-
-    let expected_selector_names = contracts[0]
-        .selectors
-        .iter()
-        .map(|selector| selector.name.as_str())
-        .collect::<Vec<_>>();
-    let mut resolved_contracts = Vec::with_capacity(contracts.len());
-    for contract in contracts {
-        validate_selector_bindings(
-            intrinsic_id,
-            "target-contract selectors",
-            &contract.selectors,
-        )?;
-        ensure!(
-            contract
-                .selectors
-                .iter()
-                .map(|selector| selector.name.as_str())
-                .eq(expected_selector_names.iter().copied()),
-            "{intrinsic_id} target contracts must use one closed selector schema"
-        );
-        ensure!(
-            !contract.alternatives.is_empty(),
-            "{intrinsic_id} target contract {:?} has no alternatives",
-            contract.selectors
-        );
-
-        let alternatives = contract
-            .alternatives
-            .iter()
-            .map(|alternative| {
-                Ok(CatalogTargetAlternative {
-                    minimum_ptx: parse_ptx_version(&alternative.minimum_ptx, intrinsic_id)?,
-                    hardware: parse_target_contract_hardware(intrinsic_id, &alternative.target)?,
-                })
-            })
-            .collect::<Result<Vec<_>>>()?;
-        ensure!(
-            alternatives
-                .windows(2)
-                .all(|pair| target_hardware_sort_key(pair[0].hardware)
-                    < target_hardware_sort_key(pair[1].hardware)),
-            "{intrinsic_id} target contract {:?} alternatives must have unique, sorted hardware targets",
-            contract.selectors
-        );
-        let minimum_count = alternatives
-            .iter()
-            .filter(|alternative| {
-                matches!(
-                    alternative.hardware,
-                    CatalogHardwareAlternative::MinimumSm { .. }
-                )
-            })
-            .count();
-        ensure!(
-            minimum_count == 0 || alternatives.len() == 1,
-            "{intrinsic_id} target contract {:?} cannot mix a minimum-SM range with other alternatives",
-            contract.selectors
-        );
-        resolved_contracts.push(CatalogTargetContract {
-            selectors: contract.selectors.clone(),
-            alternatives,
-        });
-    }
-    ensure!(
-        resolved_contracts
-            .windows(2)
-            .all(|pair| pair[0].selectors < pair[1].selectors),
-        "{intrinsic_id} target contracts must have unique, sorted selector bindings"
-    );
-
-    let minimum_ptx = resolved_contracts
-        .iter()
-        .flat_map(|contract| contract.alternatives.iter())
-        .map(|alternative| alternative.minimum_ptx)
-        .min()
-        .unwrap();
-    Ok(CatalogTargetRequirement {
-        minimum_ptx,
-        hardware: CatalogHardwareTarget::TargetMatrix {
-            contracts: resolved_contracts,
-        },
-    })
-}
-
-/// Resolve one fixed selector tuple from a closed target matrix.
-pub(crate) fn resolve_target_contract(
-    intrinsic_id: &str,
-    selected: &[TargetSelectorBinding],
-    contracts: &[TargetContract],
-) -> Result<CatalogTargetRequirement> {
-    validate_selector_bindings(intrinsic_id, "selected target selectors", selected)?;
-    let resolved = resolve_target_contracts(intrinsic_id, contracts)?;
-    let CatalogHardwareTarget::TargetMatrix { contracts } = resolved.hardware else {
-        unreachable!("target-contract resolution always returns a matrix")
-    };
-
-    let matching = contracts
-        .into_iter()
-        .filter(|contract| contract.selectors == selected)
-        .collect::<Vec<_>>();
-    ensure!(
-        matching.len() == 1,
-        "{intrinsic_id} selected target selectors {:?} must match exactly one reviewed contract",
-        selected
-    );
-    let contract = matching.into_iter().next().unwrap();
-    let minimum_ptx = contract
-        .alternatives
-        .iter()
-        .map(|alternative| alternative.minimum_ptx)
-        .min()
-        .unwrap();
-    Ok(CatalogTargetRequirement {
-        minimum_ptx,
-        hardware: CatalogHardwareTarget::TargetMatrix {
-            contracts: vec![contract],
-        },
-    })
-}
-
-fn validate_selector_bindings(
-    intrinsic_id: &str,
-    label: &str,
-    selectors: &[TargetSelectorBinding],
-) -> Result<()> {
-    for selector in selectors {
-        ensure!(
-            is_target_selector_token(&selector.name) && is_target_selector_token(&selector.value),
-            "{intrinsic_id} {label} must use lowercase snake-case names and values"
-        );
-    }
-    ensure!(
-        selectors.windows(2).all(|pair| pair[0].name < pair[1].name),
-        "{intrinsic_id} {label} must have unique, sorted names"
-    );
-    Ok(())
-}
-
-fn is_target_selector_token(value: &str) -> bool {
-    value
-        .bytes()
-        .next()
-        .is_some_and(|byte| byte.is_ascii_lowercase())
-        && value
-            .bytes()
-            .all(|byte| byte.is_ascii_lowercase() || byte.is_ascii_digit() || byte == b'_')
-        && !value.ends_with('_')
-        && !value.contains("__")
-}
-
-fn parse_target_contract_hardware(
-    intrinsic_id: &str,
-    target: &str,
-) -> Result<CatalogHardwareAlternative> {
-    if let Some(minimum) = target.strip_suffix('+') {
-        let sm = parse_sm_spelling(intrinsic_id, "target contract", minimum, None)?;
-        return Ok(CatalogHardwareAlternative::MinimumSm { sm });
-    }
-    parse_exact_hardware_alternative(intrinsic_id, target)
-}
-
-fn target_hardware_sort_key(hardware: CatalogHardwareAlternative) -> (u16, u8) {
-    match hardware {
-        CatalogHardwareAlternative::MinimumSm { sm } => (sm, 0),
-        CatalogHardwareAlternative::ExactArchitecture { sm } => (sm, 1),
-        CatalogHardwareAlternative::FamilyTarget { sm } => (sm, 2),
-    }
-}
-
-fn parse_hardware_target_fields(
-    intrinsic_id: &str,
-    targets: &str,
-    minimum_sm: Option<&str>,
-) -> Result<CatalogHardwareTarget> {
-    if targets == "all" {
-        let Some(minimum_sm) = minimum_sm else {
-            return Ok(CatalogHardwareTarget::All);
-        };
-        let sm = parse_sm_spelling(intrinsic_id, "minimum_sm", minimum_sm, None)?;
-        return Ok(CatalogHardwareTarget::AnyOf {
-            alternatives: vec![CatalogHardwareAlternative::MinimumSm { sm }],
-        });
-    }
-
-    if targets.contains('|') {
-        ensure!(
-            minimum_sm.is_none(),
-            "{} target alternatives {:?} cannot be combined with minimum_sm",
-            intrinsic_id,
-            targets
-        );
-        let spellings = targets.split('|').collect::<Vec<_>>();
-        ensure!(
-            spellings.len() >= 2,
-            "{} target alternatives must contain at least two targets",
-            intrinsic_id
-        );
-        ensure!(
-            spellings.windows(2).all(|pair| pair[0] < pair[1]),
-            "{} target alternatives must be unique and sorted",
-            intrinsic_id
-        );
-        return Ok(CatalogHardwareTarget::AnyOf {
-            alternatives: spellings
-                .into_iter()
-                .map(|spelling| parse_exact_hardware_alternative(intrinsic_id, spelling))
-                .collect::<Result<Vec<_>>>()?,
-        });
-    }
-
-    ensure!(
-        minimum_sm.is_none(),
-        "{} exact targets {:?} cannot be combined with minimum_sm",
-        intrinsic_id,
-        targets
-    );
-    Ok(CatalogHardwareTarget::AnyOf {
-        alternatives: vec![parse_exact_hardware_alternative(intrinsic_id, targets)?],
-    })
-}
-
-fn parse_exact_hardware_alternative(
-    intrinsic_id: &str,
-    target: &str,
-) -> Result<CatalogHardwareAlternative> {
-    let suffix = target
-        .chars()
-        .last()
-        .filter(|suffix| matches!(suffix, 'a' | 'f'));
-    let Some(suffix) = suffix else {
-        bail!(
-            "{} targets {:?} must be `all`, exact `sm_Na`, or family `sm_Nf`",
-            intrinsic_id,
-            target
-        );
-    };
-    let sm = parse_sm_spelling(intrinsic_id, "targets", target, Some(suffix))?;
-    Ok(match suffix {
-        'a' => CatalogHardwareAlternative::ExactArchitecture { sm },
-        'f' => CatalogHardwareAlternative::FamilyTarget { sm },
-        _ => unreachable!(),
-    })
-}
-
-fn parse_sm_spelling(
-    intrinsic_id: &str,
-    field: &str,
-    value: &str,
-    suffix: Option<char>,
-) -> Result<u16> {
-    let body = value.strip_prefix("sm_").with_context(|| {
-        format!("{intrinsic_id} {field} {value:?} must use canonical sm_NN spelling")
-    })?;
-    let digits = match suffix {
-        Some(suffix) => body.strip_suffix(suffix).with_context(|| {
-            format!("{intrinsic_id} {field} {value:?} has the wrong target suffix")
-        })?,
-        None => body,
-    };
-    ensure!(
-        matches!(digits.len(), 2 | 3) && digits.bytes().all(|byte| byte.is_ascii_digit()),
-        "{} {} {:?} must use canonical sm_NN{} spelling",
-        intrinsic_id,
-        field,
-        value,
-        suffix.map_or("", |suffix| if suffix == 'a' { "a" } else { "f" })
-    );
-    let sm: u16 = digits
-        .parse()
-        .with_context(|| format!("{intrinsic_id} {field} target is too large"))?;
-    let canonical = match suffix {
-        Some(suffix) => format!("sm_{sm}{suffix}"),
-        None => format!("sm_{sm}"),
-    };
-    ensure!(
-        sm > 0 && canonical == value,
-        "{} {} {:?} is not canonical",
-        intrinsic_id,
-        field,
-        value
-    );
-    Ok(sm)
-}
-
-fn backend_target_requirement(
-    policy: &OverlayIntrinsic,
-    lowering: &crate::model::OverlayBackendLowering,
-) -> Result<CatalogTargetRequirement> {
-    if let Some(mma) = policy
-        .tcgen05
-        .as_ref()
-        .and_then(|tcgen05| tcgen05.mma.as_ref())
-    {
-        return Ok(match lowering.backend {
-            IntrinsicBackend::LlvmNvptx => mma.llvm_target.clone(),
-            IntrinsicBackend::LibNvvm => mma.libnvvm_target.clone(),
-        });
-    }
-    let minimum_ptx = lowering
-        .minimum_ptx
-        .as_deref()
-        .unwrap_or(&policy.minimum_ptx);
-    let targets = lowering.targets.as_deref().unwrap_or(&policy.targets);
-    let minimum_sm = lowering.minimum_sm.as_deref().or_else(|| {
-        if lowering.targets.is_none() {
-            policy.minimum_sm.as_deref()
-        } else {
-            None
-        }
-    });
-    Ok(CatalogTargetRequirement {
-        minimum_ptx: parse_ptx_version(minimum_ptx, &policy.id)?,
-        hardware: parse_hardware_target_fields(&policy.id, targets, minimum_sm)?,
-    })
-}
-
-fn read_evidence_file(path: &Path) -> Result<EvidenceFile> {
-    let bytes = fs::read(path).with_context(|| format!("read {}", path.display()))?;
-    parse_evidence_bytes(&bytes, &path.display().to_string())
-}
-
-fn parse_evidence_bytes(bytes: &[u8], source: &str) -> Result<EvidenceFile> {
-    #[derive(serde::Deserialize)]
-    struct Schema {
-        schema: u32,
-    }
-
-    let schema: Schema =
-        serde_json::from_slice(bytes).with_context(|| format!("parse JSON {source}"))?;
-    match schema.schema {
-        2..=5 => serde_json::from_slice(bytes)
-            .with_context(|| format!("parse legacy evidence JSON {source}")),
-        6 => {
-            let file: EvidenceFileV6 = serde_json::from_slice(bytes)
-                .with_context(|| format!("parse matrix evidence JSON {source}"))?;
-            expand_evidence_file_v6(file)
-                .with_context(|| format!("expand matrix evidence {source}"))
-        }
-        _ => bail!("unsupported evidence schema in {source}"),
-    }
-}
-
-fn expand_evidence_file_v6(file: EvidenceFileV6) -> Result<EvidenceFile> {
-    ensure!(file.schema == 6, "matrix evidence must use schema 6");
-    ensure!(
-        !file.records.is_empty() || !file.matrices.is_empty(),
-        "schema-6 evidence contains no records or matrices"
-    );
-    reject_default_placeholders(&file.defaults, "evidence defaults", false)?;
-
-    let mut fixture_by_id = BTreeMap::new();
-    let mut fixture_coverage = BTreeMap::new();
-    for fixture in &file.fixtures {
-        ensure!(
-            is_safe_matrix_token(&fixture.id),
-            "evidence fixture ID {:?} is not a safe token",
-            fixture.id
-        );
-        ensure!(
-            fixture.coverage_count > 0 && !fixture.stages.is_empty(),
-            "evidence fixture {} has no coverage or stages",
-            fixture.id
-        );
-        reject_stage_placeholders(&fixture.stages, &format!("fixture {}", fixture.id))?;
-        ensure!(
-            fixture_by_id.insert(fixture.id.as_str(), fixture).is_none(),
-            "duplicate evidence fixture ID {}",
-            fixture.id
-        );
-        fixture_coverage.insert(fixture.id.as_str(), 0usize);
-    }
-
-    let mut records = file.records;
-    let mut record_ids = BTreeSet::new();
-    for record in &records {
-        ensure!(
-            record_ids.insert(record.id.clone()),
-            "duplicate expanded evidence ID {}",
-            record.id
-        );
-        validate_stage_pairs(&record.stages, &record.id)?;
-    }
-
-    for matrix in &file.matrices {
-        let (expanded, referenced_fixtures) =
-            expand_evidence_matrix(matrix, &file.defaults, &fixture_by_id)?;
-        for fixture_id in referenced_fixtures {
-            *fixture_coverage
-                .get_mut(fixture_id.as_str())
-                .expect("validated fixture reference") += expanded.len();
-        }
-        for record in expanded {
-            ensure!(
-                record_ids.insert(record.id.clone()),
-                "duplicate expanded evidence ID {}",
-                record.id
-            );
-            records.push(record);
-        }
-    }
-
-    for fixture in &file.fixtures {
-        let actual = fixture_coverage[fixture.id.as_str()];
-        ensure!(
-            actual > 0,
-            "evidence fixture {} is not referenced by any matrix",
-            fixture.id
-        );
-        ensure!(
-            actual == fixture.coverage_count,
-            "evidence fixture {} covers {actual} expanded records, expected {}",
-            fixture.id,
-            fixture.coverage_count
-        );
-    }
-
-    Ok(EvidenceFile {
-        schema: file.schema,
-        backend_profile: file.backend_profile,
-        backend_kind: file.backend_kind,
-        llvm_revision: file.llvm_revision,
-        backend_version: file.backend_version,
-        backend_sha256: file.backend_sha256,
-        artifact_path: file.artifact_path,
-        build_id_prefix: file.build_id_prefix,
-        nvvm_ir_version: file.nvvm_ir_version,
-        debug_ir_version: file.debug_ir_version,
-        records,
-    })
-}
-
-fn expand_evidence_matrix(
-    matrix: &EvidenceMatrix,
-    defaults: &EvidenceRecordDefaults,
-    fixtures: &BTreeMap<&str, &crate::model::EvidenceFixture>,
-) -> Result<(Vec<EvidenceRecord>, Vec<String>)> {
-    ensure!(!matrix.axes.is_empty(), "evidence matrix has no axes");
-    let mut previous_axis: Option<&str> = None;
-    let mut product_count = 1usize;
-    let mut bindings = vec![BTreeMap::<String, String>::new()];
-    for axis in &matrix.axes {
-        ensure!(
-            is_safe_matrix_token(&axis.name),
-            "evidence matrix axis {:?} is not a safe token",
-            axis.name
-        );
-        if let Some(previous) = previous_axis {
-            ensure!(
-                previous < axis.name.as_str(),
-                "evidence matrix axes must be unique and sorted: {} follows {}",
-                axis.name,
-                previous
-            );
-        }
-        previous_axis = Some(&axis.name);
-        ensure!(
-            !axis.values.is_empty(),
-            "evidence matrix axis {} has no values",
-            axis.name
-        );
-        let mut values = BTreeSet::new();
-        for value in &axis.values {
-            ensure!(
-                is_safe_matrix_token(value),
-                "evidence matrix axis {} has unsafe value {:?}",
-                axis.name,
-                value
-            );
-            ensure!(
-                values.insert(value.as_str()),
-                "evidence matrix axis {} has duplicate value {:?}",
-                axis.name,
-                value
-            );
-        }
-        product_count = product_count
-            .checked_mul(axis.values.len())
-            .context("evidence matrix product count overflow")?;
-        let mut next = Vec::with_capacity(product_count);
-        for binding in bindings {
-            for value in &axis.values {
-                let mut expanded = binding.clone();
-                expanded.insert(axis.name.clone(), value.clone());
-                next.push(expanded);
-            }
-        }
-        bindings = next;
-    }
-    ensure!(
-        product_count == matrix.product_count,
-        "evidence matrix expands to {product_count} records, expected {}",
-        matrix.product_count
-    );
-    ensure!(
-        !matrix.fixtures.is_empty(),
-        "evidence matrix references no shared fixture"
-    );
-
-    let mut fixture_ids = BTreeSet::new();
-    let mut previous_fixture: Option<&str> = None;
-    let mut fixture_stages = Vec::new();
-    for fixture_id in &matrix.fixtures {
-        if let Some(previous) = previous_fixture {
-            ensure!(
-                previous < fixture_id.as_str(),
-                "evidence matrix fixtures must be unique and sorted: {fixture_id} follows {previous}"
-            );
-        }
-        previous_fixture = Some(fixture_id);
-        let fixture = fixtures
-            .get(fixture_id.as_str())
-            .with_context(|| format!("evidence matrix references unknown fixture {fixture_id}"))?;
-        fixture_ids.insert(fixture_id.clone());
-        fixture_stages.extend(fixture.stages.iter().cloned());
-    }
-
-    reject_default_placeholders(&matrix.template.facts, "matrix template facts", true)?;
-    validate_matrix_identity(&matrix.template)?;
-    let axis_names = matrix
-        .axes
-        .iter()
-        .map(|axis| axis.name.as_str())
-        .collect::<BTreeSet<_>>();
-    let mut used_axes = BTreeSet::new();
-    let mut records = Vec::with_capacity(product_count);
-    for binding in &bindings {
-        let record = materialize_evidence_record(
-            &matrix.template,
-            defaults,
-            binding,
-            &mut used_axes,
-            &fixture_stages,
-        )?;
-        validate_stage_pairs(&record.stages, &record.id)?;
-        records.push(record);
-    }
-    for axis in axis_names {
-        ensure!(
-            used_axes.contains(axis),
-            "evidence matrix declares unused axis {axis}"
-        );
-    }
-    Ok((records, fixture_ids.into_iter().collect()))
-}
-
-fn validate_matrix_identity(template: &EvidenceMatrixTemplate) -> Result<()> {
-    ensure!(
-        !template.id.is_empty(),
-        "evidence matrix template has an empty ID"
-    );
-    match (&template.source, &template.source_record) {
-        (Some(_), None) | (None, Some(_)) => {}
-        (Some(_), Some(_)) => bail!("evidence matrix template mixes source forms"),
-        (None, None) => bail!("evidence matrix template has no source"),
-    }
-    reject_disallowed_placeholder(&template.expected_ptx.mnemonic, "PTX mnemonic")?;
-    Ok(())
-}
-
-fn materialize_evidence_record(
-    template: &EvidenceMatrixTemplate,
-    defaults: &EvidenceRecordDefaults,
-    bindings: &BTreeMap<String, String>,
-    used_axes: &mut BTreeSet<String>,
-    fixture_stages: &[EvidenceStage],
-) -> Result<EvidenceRecord> {
-    let id = expand_axis_placeholders(&template.id, bindings, used_axes, "evidence ID")?;
-    let source = template
-        .source
-        .as_ref()
-        .map(|source| expand_evidence_source(source, bindings, used_axes))
-        .transpose()?;
-    let source_record = template
-        .source_record
-        .as_deref()
-        .map(|value| expand_axis_placeholders(value, bindings, used_axes, "source record"))
-        .transpose()?;
-    let llvm_symbol = template
-        .llvm_symbol
-        .as_deref()
-        .map(|value| expand_axis_placeholders(value, bindings, used_axes, "LLVM symbol"))
-        .transpose()?;
-    validate_expanded_matrix_identity(
-        &id,
-        source.as_ref(),
-        source_record.as_deref(),
-        llvm_symbol.as_deref(),
-    )?;
-    let resolved_llvm_symbol = select_fact(
-        &template.facts.resolved_llvm_symbol,
-        &defaults.resolved_llvm_symbol,
-    )
-    .map(|value| expand_axis_placeholders(&value, bindings, used_axes, "resolved LLVM symbol"))
-    .transpose()?;
-    let mut expected_ptx = template.expected_ptx.clone();
-    for modifier in &mut expected_ptx.modifiers {
-        *modifier = expand_axis_placeholders(modifier, bindings, used_axes, "PTX modifier")?;
-    }
-    for operand in &mut expected_ptx.operands {
-        if let OperandPattern::Exact { value } = operand {
-            *value = expand_axis_placeholders(value, bindings, used_axes, "exact PTX operand")?;
-        }
-    }
-
-    let mut stages = defaults.stages.clone();
-    stages.extend(template.facts.stages.iter().cloned());
-    stages.extend(fixture_stages.iter().cloned());
-    let target_triple = required_fact(
-        select_fact(&template.facts.target_triple, &defaults.target_triple),
-        &id,
-        "target triple",
-    )?;
-    let gpu_target = required_fact(
-        select_fact(&template.facts.gpu_target, &defaults.gpu_target),
-        &id,
-        "GPU target",
-    )?;
-    let ptx_feature = required_fact(
-        select_fact(&template.facts.ptx_feature, &defaults.ptx_feature),
-        &id,
-        "PTX feature",
-    )?;
-    let status = required_fact(
-        select_fact(&template.facts.status, &defaults.status),
-        &id,
-        "status",
-    )?;
-    let source_is_ptx_native = matches!(source, Some(IntrinsicSource::PtxNative { .. }));
-    Ok(EvidenceRecord {
-        id,
-        source,
-        source_record,
-        llvm_symbol,
-        resolved_llvm_symbol,
-        llvm_arguments: select_fact(&template.facts.llvm_arguments, &defaults.llvm_arguments)
-            .unwrap_or_default(),
-        llvm_results: select_fact(&template.facts.llvm_results, &defaults.llvm_results)
-            .unwrap_or_default(),
-        concrete_llvm_arguments: select_fact(
-            &template.facts.concrete_llvm_arguments,
-            &defaults.concrete_llvm_arguments,
-        )
-        .unwrap_or_default(),
-        concrete_llvm_results: select_fact(
-            &template.facts.concrete_llvm_results,
-            &defaults.concrete_llvm_results,
-        )
-        .unwrap_or_default(),
-        target_triple,
-        gpu_target,
-        ptx_feature,
-        status,
-        stages,
-        // Declaration canonicalization is a statement about an imported
-        // LLVM declaration; a PTX-native record has none, so the file-level
-        // default must not invent the fact for it.
-        declaration_attributes_canonicalized: if source_is_ptx_native {
-            template.facts.declaration_attributes_canonicalized
-        } else {
-            template
-                .facts
-                .declaration_attributes_canonicalized
-                .or(defaults.declaration_attributes_canonicalized)
-        },
-        runtime_validation: template
-            .facts
-            .runtime_validation
-            .or(defaults.runtime_validation),
-        expected_ptx,
-    })
-}
-
-fn validate_expanded_matrix_identity(
-    id: &str,
-    source: Option<&IntrinsicSource>,
-    source_record: Option<&str>,
-    llvm_symbol: Option<&str>,
-) -> Result<()> {
-    ensure!(!id.is_empty(), "expanded evidence has an empty ID");
-    let imported_source = match (source, source_record) {
-        (Some(IntrinsicSource::LlvmImported { source_record }), None) => {
-            ensure!(
-                !source_record.is_empty(),
-                "expanded evidence {id} has an empty source record"
-            );
-            true
-        }
-        (Some(IntrinsicSource::PtxNative { instruction }), None) => {
-            ensure!(
-                !instruction.is_empty(),
-                "expanded evidence {id} has an empty PTX source"
-            );
-            false
-        }
-        (None, Some(source_record)) => {
-            ensure!(
-                !source_record.is_empty(),
-                "expanded evidence {id} has an empty source record"
-            );
-            true
-        }
-        _ => unreachable!("matrix source shape was validated before expansion"),
-    };
-    if imported_source {
-        ensure!(
-            llvm_symbol.is_some_and(|symbol| !symbol.is_empty()),
-            "expanded imported evidence {id} has no LLVM symbol"
-        );
-    } else {
-        ensure!(
-            llvm_symbol.is_none(),
-            "expanded PTX-native evidence {id} invents an LLVM symbol"
-        );
-    }
-    Ok(())
-}
-
-fn select_fact<T: Clone>(specific: &Option<T>, default: &Option<T>) -> Option<T> {
-    specific.clone().or_else(|| default.clone())
-}
-
-fn required_fact(value: Option<String>, id: &str, field: &str) -> Result<String> {
-    let value = value.with_context(|| format!("expanded evidence {id} has no {field}"))?;
-    ensure!(
-        !value.trim().is_empty(),
-        "expanded evidence {id} has an empty {field}"
-    );
-    Ok(value)
-}
-
-fn expand_evidence_source(
-    source: &IntrinsicSource,
-    bindings: &BTreeMap<String, String>,
-    used_axes: &mut BTreeSet<String>,
-) -> Result<IntrinsicSource> {
-    Ok(match source {
-        IntrinsicSource::LlvmImported { source_record } => IntrinsicSource::LlvmImported {
-            source_record: expand_axis_placeholders(
-                source_record,
-                bindings,
-                used_axes,
-                "tagged source record",
-            )?,
-        },
-        IntrinsicSource::PtxNative { instruction } => IntrinsicSource::PtxNative {
-            instruction: expand_axis_placeholders(
-                instruction,
-                bindings,
-                used_axes,
-                "PTX-native source",
-            )?,
-        },
-    })
-}
-
-fn expand_axis_placeholders(
-    value: &str,
-    bindings: &BTreeMap<String, String>,
-    used_axes: &mut BTreeSet<String>,
-    field: &str,
-) -> Result<String> {
-    let mut output = String::with_capacity(value.len());
-    let mut rest = value;
-    while let Some(position) = rest.find('$') {
-        output.push_str(&rest[..position]);
-        let placeholder = &rest[position..];
-        ensure!(
-            placeholder.starts_with("${"),
-            "{field} contains malformed matrix placeholder {value:?}"
-        );
-        let close = placeholder
-            .find('}')
-            .with_context(|| format!("{field} contains an unterminated matrix placeholder"))?;
-        let axis = &placeholder[2..close];
-        ensure!(
-            is_safe_matrix_token(axis),
-            "{field} contains malformed matrix axis {axis:?}"
-        );
-        let replacement = bindings
-            .get(axis)
-            .with_context(|| format!("{field} references unknown matrix axis {axis}"))?;
-        output.push_str(replacement);
-        used_axes.insert(axis.to_owned());
-        rest = &placeholder[close + 1..];
-    }
-    output.push_str(rest);
-    Ok(output)
-}
-
-fn is_safe_matrix_token(value: &str) -> bool {
-    let mut bytes = value.bytes();
-    bytes.next().is_some_and(|byte| byte.is_ascii_lowercase())
-        && bytes.all(|byte| byte.is_ascii_lowercase() || byte.is_ascii_digit() || byte == b'_')
-}
-
-fn reject_default_placeholders(
-    defaults: &EvidenceRecordDefaults,
-    context: &str,
-    allow_resolved_symbol: bool,
-) -> Result<()> {
-    if !allow_resolved_symbol && let Some(value) = &defaults.resolved_llvm_symbol {
-        reject_disallowed_placeholder(value, context)?;
-    }
-    for value in defaults
-        .target_triple
-        .iter()
-        .chain(defaults.gpu_target.iter())
-        .chain(defaults.ptx_feature.iter())
-        .chain(defaults.status.iter())
-        .chain(defaults.llvm_arguments.iter().flatten())
-        .chain(defaults.llvm_results.iter().flatten())
-        .chain(defaults.concrete_llvm_arguments.iter().flatten())
-        .chain(defaults.concrete_llvm_results.iter().flatten())
-    {
-        reject_disallowed_placeholder(value, context)?;
-    }
-    reject_stage_placeholders(&defaults.stages, context)
-}
-
-fn reject_stage_placeholders(stages: &[EvidenceStage], context: &str) -> Result<()> {
-    for stage in stages {
-        for value in stage
-            .targets
-            .iter()
-            .chain(std::iter::once(&stage.representation))
-            .chain(std::iter::once(&stage.detail))
-            .chain(stage.tool_path.iter())
-            .chain(stage.tool_version.iter())
-            .chain(stage.tool_sha256.iter())
-        {
-            reject_disallowed_placeholder(value, context)?;
-        }
-    }
-    Ok(())
-}
-
-fn reject_disallowed_placeholder(value: &str, field: &str) -> Result<()> {
-    ensure!(
-        !value.contains("${"),
-        "{field} cannot contain matrix placeholders"
-    );
-    Ok(())
-}
-
-fn validate_stage_pairs(stages: &[EvidenceStage], id: &str) -> Result<()> {
-    let mut identities = Vec::new();
-    for stage in stages {
-        let identity = (stage.stage, stage.mechanism, stage.targets.clone());
-        ensure!(
-            !identities.contains(&identity),
-            "expanded evidence {id} has conflicting duplicate {:?}/{:?} stage targets {:?}",
-            stage.stage,
-            stage.mechanism,
-            stage.targets
-        );
-        identities.push(identity);
-    }
-    Ok(())
-}
-
-fn read_evidence(repo_root: &Path) -> Result<(Vec<EvidenceFile>, Vec<String>)> {
-    let directory = repo_root.join("intrinsics/evidence");
-    let mut paths: Vec<PathBuf> = fs::read_dir(&directory)
-        .with_context(|| format!("read {}", directory.display()))?
-        .filter_map(|entry| entry.ok().map(|entry| entry.path()))
-        .filter(|path| path.extension().and_then(|ext| ext.to_str()) == Some("json"))
-        .collect();
-    paths.sort();
-    ensure!(
-        !paths.is_empty(),
-        "no evidence JSON files in {}",
-        directory.display()
-    );
-    let mut files = Vec::with_capacity(paths.len());
-    let mut hashes = Vec::with_capacity(paths.len());
-    for path in paths {
-        let file = read_evidence_file(&path)?;
-        let name = path.file_name().unwrap().to_string_lossy();
-        hashes.push(format!("{name}:{}", sha256_file(&path)?));
-        files.push(file);
-    }
-    Ok((files, hashes))
-}
-
-#[derive(Debug, Clone, Copy)]
-struct IndexedEvidence<'a> {
-    file: &'a EvidenceFile,
-    record: &'a EvidenceRecord,
-    backend_version: &'a str,
-    backend_sha256: &'a str,
-}
-
-fn index_evidence<'a>(
-    files: &'a [EvidenceFile],
-    llvm_revision: &str,
-) -> Result<BTreeMap<(&'a str, &'a str), IndexedEvidence<'a>>> {
-    let mut result = BTreeMap::new();
-    for file in files {
-        ensure!(
-            !file.backend_profile.trim().is_empty() && !file.llvm_revision.trim().is_empty(),
-            "evidence file has no concrete backend profile or LLVM revision"
-        );
-        ensure!(
-            !file.backend_version.trim().is_empty() && !file.backend_sha256.trim().is_empty(),
-            "evidence does not identify the backend binary"
-        );
-        if file.backend_kind != Some(IntrinsicBackend::LibNvvm) {
-            ensure!(
-                file.llvm_revision == llvm_revision,
-                "selected evidence LLVM revision {} does not match pinned {}",
-                file.llvm_revision,
-                llvm_revision
-            );
-        }
-        for record in &file.records {
-            ensure!(
-                result
-                    .insert(
-                        (file.backend_profile.as_str(), record.id.as_str()),
-                        IndexedEvidence {
-                            file,
-                            record,
-                            backend_version: &file.backend_version,
-                            backend_sha256: &file.backend_sha256,
-                        },
-                    )
-                    .is_none(),
-                "duplicate evidence for catalog ID {}",
-                record.id
-            );
-        }
-    }
-    Ok(result)
-}
-
-fn validate_evidence(
-    policy: &OverlayIntrinsic,
-    evidence: &IndexedEvidence<'_>,
-    lowering: Option<&crate::model::OverlayBackendLowering>,
-) -> Result<()> {
-    let record = evidence.record;
-    record.expected_ptx.validate().map_err(|reason| {
-        anyhow::anyhow!(
-            "{} evidence has an invalid expected PTX pattern: {reason}",
-            policy.id
-        )
-    })?;
-    let policy_source = resolve_policy_source(policy)?;
-    let evidence_source = match (&record.source, &record.source_record) {
-        (None, Some(source_record)) => IntrinsicSource::LlvmImported {
-            source_record: source_record.clone(),
-        },
-        (Some(source), None) => source.clone(),
-        (Some(_), Some(_)) => bail!(
-            "{} evidence mixes tagged source with legacy source_record",
-            policy.id
-        ),
-        (None, None) => bail!("{} evidence has no source provenance", policy.id),
-    };
-    ensure!(
-        evidence_source == policy_source,
-        "{} evidence source provenance mismatch",
-        policy.id
-    );
-    ensure!(
-        record.llvm_symbol == policy.llvm_symbol
-            && record.llvm_arguments == policy.llvm_arguments
-            && record.llvm_results == policy.llvm_results,
-        "{} evidence signature mismatch",
-        policy.id
-    );
-    if matches!(policy_source, IntrinsicSource::PtxNative { .. }) {
-        ensure!(
-            record.llvm_symbol.is_none()
-                && record.resolved_llvm_symbol.is_none()
-                && record.llvm_arguments.is_empty()
-                && record.llvm_results.is_empty()
-                && record.concrete_llvm_arguments.is_empty()
-                && record.concrete_llvm_results.is_empty()
-                && record.declaration_attributes_canonicalized.is_none(),
-            "{} PTX-native evidence must not invent LLVM declaration facts",
-            policy.id
-        );
-    }
-    ensure!(
-        record.expected_ptx == policy.expected_ptx,
-        "{} evidence PTX expectation mismatch",
-        policy.id
-    );
-    ensure!(
-        matches!(record.status.as_str(), "lowered" | "validated" | "executed"),
-        "{} evidence status {} is too weak to generate a lowering",
-        policy.id,
-        record.status
-    );
-    ensure!(
-        !record.target_triple.is_empty()
-            && !record.gpu_target.is_empty()
-            && !record.ptx_feature.is_empty(),
-        "{} evidence omits its full target profile",
-        policy.id
-    );
-    if let Some(lowering) = lowering {
-        ensure!(
-            evidence.file.backend_kind == Some(lowering.backend),
-            "{} evidence profile {} has the wrong backend kind",
-            policy.id,
-            evidence.file.backend_profile
-        );
-        match record.status.as_str() {
-            "executed" => ensure!(
-                record.runtime_validation == Some(RuntimeValidation::Executed),
-                "{} executed evidence must record runtime_validation = executed",
-                policy.id
-            ),
-            _ => ensure!(
-                record.runtime_validation == Some(RuntimeValidation::Unexecuted),
-                "{} non-executed backend evidence must record runtime_validation = unexecuted",
-                policy.id
-            ),
-        }
-        ensure!(
-            !record.stages.is_empty(),
-            "{} backend evidence omits compilation stages",
-            policy.id
-        );
-        ensure!(
-            record.stages.iter().any(|stage| {
-                stage.stage == EvidenceStageKind::BackendCodegen
-                    && stage.mechanism == Some(lowering.mechanism)
-                    && stage.outcome == "succeeded"
-            }),
-            "{} evidence has no successful backend-codegen stage for {:?}",
-            policy.id,
-            lowering.mechanism
-        );
-        validate_selected_stage_targets(policy, record, lowering)?;
-        if lowering.mechanism == BackendLoweringMechanism::TypedNvvm {
-            validate_typed_llvm_evidence(policy, record)?;
-        }
-        validate_packed_conversion_backend_evidence(policy, record, lowering)?;
-        validate_scalar_conversion_backend_evidence(policy, record, lowering)?;
-        validate_scalar_arithmetic_backend_evidence(policy, record, lowering)?;
-        validate_inline_ptx_fallback_evidence(policy, record, lowering)?;
-        if lowering.backend == IntrinsicBackend::LlvmNvptx
-            && matches!(record.status.as_str(), "validated" | "executed")
-        {
-            ensure!(
-                has_valid_ptx_assembly_stage(record, lowering.mechanism),
-                "{} validated LLVM-NVPTX evidence requires a successful PTX-assembly stage with exact tool identity",
-                policy.id
-            );
-        } else if lowering.backend == IntrinsicBackend::LibNvvm
-            && matches!(record.status.as_str(), "validated" | "executed")
-        {
-            ensure!(
-                has_valid_cubin_device_link_stage(record, lowering.mechanism),
-                "{} validated libNVVM evidence requires a successful cubin-producing device-link stage with exact tool identity",
-                policy.id
-            );
-        }
-        if record.status == "executed" {
-            ensure!(
-                record.stages.iter().any(|stage| {
-                    stage.stage == EvidenceStageKind::Runtime
-                        && stage.mechanism == Some(lowering.mechanism)
-                        && stage.outcome == "succeeded"
-                }),
-                "{} executed evidence requires a successful runtime stage for the selected mechanism",
-                policy.id
-            );
-        }
-    }
-    Ok(())
-}
-
-fn validate_inline_ptx_fallback_evidence(
-    policy: &OverlayIntrinsic,
-    record: &EvidenceRecord,
-    lowering: &crate::model::OverlayBackendLowering,
-) -> Result<()> {
-    if !matches!(
-        policy.family.as_str(),
-        "cluster_barrier" | "wgmma_control" | "elect"
-    ) || lowering.backend != IntrinsicBackend::LibNvvm
-    {
-        return Ok(());
-    }
-    for stage in [
-        EvidenceStageKind::BackendCodegen,
-        EvidenceStageKind::DeviceLink,
-    ] {
-        ensure!(
-            record.stages.iter().any(|candidate| {
-                candidate.stage == stage
-                    && candidate.mechanism == Some(BackendLoweringMechanism::TypedNvvm)
-                    && candidate.outcome == "failed"
-            }),
-            "{} libNVVM inline-PTX evidence must record the failed typed-NVVM {:?} comparison",
-            policy.id,
-            stage
-        );
-    }
-    ensure!(
-        !record.stages.iter().any(|candidate| {
-            candidate.stage == EvidenceStageKind::DeviceLink
-                && candidate.mechanism == Some(BackendLoweringMechanism::TypedNvvm)
-                && candidate.outcome == "succeeded"
-        }),
-        "{} libNVVM evidence cannot select inline PTX after a successful typed-NVVM terminal",
-        policy.id
-    );
-    Ok(())
-}
-
-fn validate_packed_conversion_backend_evidence(
-    policy: &OverlayIntrinsic,
-    record: &EvidenceRecord,
-    lowering: &crate::model::OverlayBackendLowering,
-) -> Result<()> {
-    if policy.family != "packed_conversion" {
-        return Ok(());
-    }
-    match lowering.backend {
-        IntrinsicBackend::LlvmNvptx => {
-            validate_typed_llvm_evidence(policy, record)?;
-            for stage in [
-                EvidenceStageKind::DeclarationCanonicalization,
-                EvidenceStageKind::BackendCodegen,
-            ] {
-                ensure!(
-                    successful_stage(record, BackendLoweringMechanism::TypedNvvm, stage).is_some(),
-                    "{} LLVM packed-conversion evidence requires a successful auxiliary typed-NVVM {:?} stage",
-                    policy.id,
-                    stage
-                );
-            }
-            ensure!(
-                has_valid_ptx_assembly_stage(record, BackendLoweringMechanism::TypedNvvm),
-                "{} LLVM packed-conversion evidence requires a successful auxiliary typed-NVVM PTX-assembly stage with exact tool identity",
-                policy.id
-            );
-            ensure!(
-                matches!(record.status.as_str(), "validated" | "executed"),
-                "{} LLVM packed-conversion evidence requires validated evidence status for its auxiliary typed-NVVM terminal stage",
-                policy.id
-            );
-            let typed_lowering = crate::model::OverlayBackendLowering {
-                mechanism: BackendLoweringMechanism::TypedNvvm,
-                ..lowering.clone()
-            };
-            validate_selected_stage_targets(policy, record, &typed_lowering)?;
-            Ok(())
-        }
-        IntrinsicBackend::LibNvvm => {
-            ensure!(
-                record.resolved_llvm_symbol.is_none()
-                    && record.concrete_llvm_arguments.is_empty()
-                    && record.concrete_llvm_results.is_empty()
-                    && record.declaration_attributes_canonicalized.is_none()
-                    && !record.stages.iter().any(|stage| {
-                        stage.mechanism == Some(BackendLoweringMechanism::TypedNvvm)
-                    }),
-                "{} libNVVM inline-PTX evidence must not claim typed LLVM support",
-                policy.id
-            );
-            Ok(())
-        }
-    }
-}
-
-fn validate_scalar_conversion_backend_evidence(
-    policy: &OverlayIntrinsic,
-    record: &EvidenceRecord,
-    lowering: &crate::model::OverlayBackendLowering,
-) -> Result<()> {
-    if policy.family != "scalar_conversion" {
-        return Ok(());
-    }
-    match lowering.backend {
-        IntrinsicBackend::LlvmNvptx => ensure!(
-            successful_stage(
-                record,
-                BackendLoweringMechanism::TypedNvvm,
-                EvidenceStageKind::DeclarationCanonicalization,
-            )
-            .is_some(),
-            "{} LLVM scalar-conversion evidence must canonicalize the typed declaration",
-            policy.id
-        ),
-        IntrinsicBackend::LibNvvm => ensure!(
-            record.resolved_llvm_symbol.is_none()
-                && record.concrete_llvm_arguments.is_empty()
-                && record.concrete_llvm_results.is_empty()
-                && record.declaration_attributes_canonicalized.is_none(),
-            "{} libNVVM scalar-conversion evidence must describe the selected inline-PTX route",
-            policy.id
-        ),
-    };
-    Ok(())
-}
-
-fn validate_scalar_arithmetic_backend_evidence(
-    policy: &OverlayIntrinsic,
-    record: &EvidenceRecord,
-    lowering: &crate::model::OverlayBackendLowering,
-) -> Result<()> {
-    if policy.family != "scalar_arithmetic" {
-        return Ok(());
-    }
-    match (lowering.backend, lowering.mechanism) {
-        (IntrinsicBackend::LlvmNvptx, BackendLoweringMechanism::TypedNvvm) => ensure!(
-            successful_stage(
-                record,
-                BackendLoweringMechanism::TypedNvvm,
-                EvidenceStageKind::DeclarationCanonicalization,
-            )
-            .is_some(),
-            "{} typed LLVM scalar-arithmetic evidence must canonicalize the declaration",
-            policy.id
-        ),
-        (IntrinsicBackend::LlvmNvptx, BackendLoweringMechanism::InlinePtx) => {
-            validate_typed_llvm_evidence(policy, record)?;
-            ensure!(
-                successful_stage(
-                    record,
-                    BackendLoweringMechanism::TypedNvvm,
-                    EvidenceStageKind::DeclarationCanonicalization,
-                )
-                .is_some(),
-                "{} inline LLVM scalar-arithmetic evidence must canonicalize its imported declaration",
-                policy.id
-            );
-        }
-        (IntrinsicBackend::LibNvvm, _) => ensure!(
-            record.resolved_llvm_symbol.is_none()
-                && record.concrete_llvm_arguments.is_empty()
-                && record.concrete_llvm_results.is_empty()
-                && record.declaration_attributes_canonicalized.is_none(),
-            "{} libNVVM scalar-arithmetic evidence must describe the selected inline-PTX route",
-            policy.id
-        ),
-    };
-    Ok(())
-}
-
-fn validate_typed_llvm_evidence(policy: &OverlayIntrinsic, record: &EvidenceRecord) -> Result<()> {
-    let concrete_arguments = policy
-        .llvm_arguments
-        .iter()
-        .map(|argument| {
-            match argument.as_str() {
-                "shared_cluster_ptr" => return Ok("ptr addrspace(7)".into()),
-                "shared_ptr" => return Ok("ptr addrspace(3)".into()),
-                "global_ptr" => return Ok("ptr addrspace(1)".into()),
-                "ptr" => return Ok("ptr".into()),
-                "anyptr" => {}
-                _ => return Ok(argument.clone()),
-            }
-            match policy.selected_address_space.with_context(|| {
-                format!(
-                    "{} has a polymorphic LLVM pointer without a selected address space",
-                    policy.id
-                )
-            })? {
-                ImportedAddressSpace::Generic => Ok("ptr".into()),
-                ImportedAddressSpace::Shared => Ok("ptr addrspace(3)".into()),
-            }
-        })
-        .collect::<Result<Vec<_>>>()?;
-    ensure!(
-        record.resolved_llvm_symbol == policy.resolved_llvm_symbol
-            && record.concrete_llvm_arguments == concrete_arguments
-            && record.concrete_llvm_results == policy.llvm_results
-            && record.declaration_attributes_canonicalized == Some(true),
-        "{} typed LLVM evidence does not prove its resolved signature and canonical declaration attributes",
-        policy.id
-    );
-    Ok(())
-}
-
-fn validate_selected_stage_targets(
-    policy: &OverlayIntrinsic,
-    record: &EvidenceRecord,
-    lowering: &crate::model::OverlayBackendLowering,
-) -> Result<()> {
-    let requirement = backend_target_requirement(policy, lowering)?;
-    let blackwell_ldmatrix = policy.family == "ldmatrix"
-        && policy
-            .ldmatrix_variant
-            .as_ref()
-            .is_some_and(|variant| variant.shape != LdmatrixShape::M8n8);
-    let f8f6f4_mma = is_f8f6f4_mma_target_matrix_policy(policy);
-    let paired_alternatives = match &requirement.hardware {
-        CatalogHardwareTarget::TargetMatrix { contracts } => Some(
-            contracts
-                .iter()
-                .flat_map(|contract| contract.alternatives.iter().cloned())
-                .collect::<Vec<_>>(),
-        ),
-        _ => None,
-    };
-    let target_matrix_evidence = blackwell_ldmatrix || f8f6f4_mma || paired_alternatives.is_some();
-    if !target_matrix_evidence {
-        let mut pairs = Vec::new();
-        for stage in record.stages.iter().filter(|stage| {
-            stage.mechanism == Some(lowering.mechanism) && stage.outcome == "succeeded"
-        }) {
-            let pair = (stage.stage, stage.mechanism);
-            ensure!(
-                !pairs.contains(&pair),
-                "{} has multiple target-specific {:?}/{:?} stages outside reviewed target-matrix evidence",
-                policy.id,
-                stage.stage,
-                stage.mechanism
-            );
-            pairs.push(pair);
-        }
-    }
-    for stage in &record.stages {
-        ensure!(
-            !stage.targets.is_empty(),
-            "{} evidence stage {:?} has no targets",
-            policy.id,
-            stage.stage
-        );
-        for target in &stage.targets {
-            ensure!(
-                is_normalized_stage_target(target),
-                "{} evidence stage has unsupported target spelling {target:?}",
-                policy.id
-            );
-        }
-    }
-
-    let terminal_kind = match lowering.backend {
-        IntrinsicBackend::LlvmNvptx => EvidenceStageKind::PtxAssembly,
-        IntrinsicBackend::LibNvvm => EvidenceStageKind::DeviceLink,
-    };
-    let expected_ptx = requirement.minimum_ptx.encoded();
-    let expected_hardware = match &requirement.hardware {
-        CatalogHardwareTarget::AnyOf { alternatives } if !alternatives.is_empty() => {
-            alternatives.clone()
-        }
-        CatalogHardwareTarget::TargetMatrix { contracts } if !contracts.is_empty() => {
-            let mut alternatives = contracts
-                .iter()
-                .flat_map(|contract| contract.alternatives.iter())
-                .map(|alternative| alternative.hardware)
-                .collect::<Vec<_>>();
-            alternatives.sort_by_key(|hardware| target_hardware_sort_key(*hardware));
-            alternatives.dedup();
-            alternatives
-        }
-        _ => bail!(
-            "{} selected backend stages require a hardware target",
-            policy.id
-        ),
-    };
-    if target_matrix_evidence {
-        return validate_target_matrix_stage_targets(
-            policy,
-            record,
-            lowering,
-            terminal_kind,
-            &expected_hardware,
-            expected_ptx,
-            paired_alternatives.as_deref(),
-        );
-    }
-    let backend = successful_stage(
-        record,
-        lowering.mechanism,
-        EvidenceStageKind::BackendCodegen,
-    )
-    .with_context(|| {
-        format!(
-            "{} has no successful selected backend-codegen stage",
-            policy.id
-        )
-    })?;
-    let mut required_stages = vec![backend];
-    if matches!(record.status.as_str(), "validated" | "executed") {
-        required_stages.push(
-            successful_stage(record, lowering.mechanism, terminal_kind).with_context(|| {
-                format!("{} has no successful selected terminal stage", policy.id)
-            })?,
-        );
-    }
-    for stage in required_stages {
-        let (hardware, ptx) = selected_stage_floor(stage)?;
-        let allow_forward_minimum = stage.stage != EvidenceStageKind::BackendCodegen;
-        let hardware_matches = expected_hardware.iter().any(|expected| {
-            selected_stage_hardware_matches(hardware, *expected, allow_forward_minimum)
-        });
-        let ptx_matches = match lowering.backend {
-            IntrinsicBackend::LlvmNvptx => ptx == expected_ptx,
-            IntrinsicBackend::LibNvvm => ptx >= expected_ptx,
-        };
-        ensure!(
-            hardware_matches && ptx_matches,
-            "{} evidence stage {:?} targets {} / PTX {}.{} instead of a compatible target at catalog floor {} / PTX {}.{}",
-            policy.id,
-            stage.stage,
-            describe_stage_hardware(hardware),
-            ptx / 10,
-            ptx % 10,
-            expected_hardware
-                .iter()
-                .map(|hardware| describe_stage_hardware(*hardware))
-                .collect::<Vec<_>>()
-                .join(" or "),
-            expected_ptx / 10,
-            expected_ptx % 10
-        );
-    }
-    if record.status == "executed" {
-        let runtime = successful_stage(record, lowering.mechanism, EvidenceStageKind::Runtime)
-            .with_context(|| {
-                format!(
-                    "{} executed evidence has no successful runtime stage",
-                    policy.id
-                )
-            })?;
-        let (hardware, ptx) = selected_stage_floor(runtime)?;
-        let ptx_matches = match lowering.backend {
-            IntrinsicBackend::LlvmNvptx => ptx == expected_ptx,
-            IntrinsicBackend::LibNvvm => ptx >= expected_ptx,
-        };
-        ensure!(
-            expected_hardware
-                .iter()
-                .any(|expected| selected_stage_hardware_matches(hardware, *expected, true))
-                && ptx_matches,
-            "{} runtime stage target does not satisfy its catalog floor",
-            policy.id
-        );
-    }
-    Ok(())
-}
-
-fn validate_target_matrix_stage_targets(
-    policy: &OverlayIntrinsic,
-    record: &EvidenceRecord,
-    lowering: &OverlayBackendLowering,
-    terminal_kind: EvidenceStageKind,
-    expected_hardware: &[CatalogHardwareAlternative],
-    minimum_ptx: u16,
-    paired_alternatives: Option<&[CatalogTargetAlternative]>,
-) -> Result<()> {
-    let mut required_kinds = vec![EvidenceStageKind::BackendCodegen];
-    if matches!(record.status.as_str(), "validated" | "executed") {
-        if lowering.backend == IntrinsicBackend::LibNvvm {
-            required_kinds.push(EvidenceStageKind::PtxAssembly);
-        }
-        required_kinds.push(terminal_kind);
-    }
-
-    for kind in required_kinds {
-        let stages = record
-            .stages
-            .iter()
-            .filter(|stage| {
-                stage.stage == kind
-                    && stage.mechanism == Some(lowering.mechanism)
-                    && stage.outcome == "succeeded"
-            })
-            .collect::<Vec<_>>();
-        ensure!(
-            stages.len() == expected_hardware.len(),
-            "{} target-matrix {:?} evidence must contain one structured stage for each of its {} reviewed targets",
-            policy.id,
-            kind,
-            expected_hardware.len()
-        );
-
-        let mut covered = Vec::new();
-        for stage in stages {
-            let (hardware, ptx) = selected_stage_floor(stage)?;
-            ensure!(
-                expected_hardware.contains(&hardware) && !covered.contains(&hardware),
-                "{} target-matrix {:?} evidence has an unexpected or duplicate target {}",
-                policy.id,
-                kind,
-                describe_stage_hardware(hardware)
-            );
-            covered.push(hardware);
-            let exact_floor =
-                target_matrix_ptx_floor(policy, hardware, paired_alternatives, false)?;
-            let ptx_matches = match lowering.backend {
-                IntrinsicBackend::LlvmNvptx => ptx == exact_floor,
-                IntrinsicBackend::LibNvvm => {
-                    ptx >= paired_alternatives.map_or(minimum_ptx, |_| exact_floor)
-                }
-            };
-            ensure!(
-                ptx_matches,
-                "{} target-matrix {:?} evidence records the wrong PTX floor for {}",
-                policy.id,
-                kind,
-                describe_stage_hardware(hardware)
-            );
-            if matches!(
-                kind,
-                EvidenceStageKind::PtxAssembly | EvidenceStageKind::DeviceLink
-            ) {
-                ensure!(
-                    stage
-                        .tool_path
-                        .as_deref()
-                        .is_some_and(|value| !value.is_empty())
-                        && stage
-                            .tool_version
-                            .as_deref()
-                            .is_some_and(|value| !value.is_empty())
-                        && stage
-                            .tool_sha256
-                            .as_deref()
-                            .is_some_and(|value| !value.is_empty()),
-                    "{} target-matrix {:?} evidence for {} does not identify its tool",
-                    policy.id,
-                    kind,
-                    describe_stage_hardware(hardware)
-                );
-            }
-            if kind == EvidenceStageKind::DeviceLink {
-                ensure!(
-                    stage.artifact_kind == Some(EvidenceArtifactKind::Cubin),
-                    "{} target-matrix device-link evidence for {} is not a cubin",
-                    policy.id,
-                    describe_stage_hardware(hardware)
-                );
-            }
-        }
-    }
-
-    if record.status == "executed" {
-        let runtime = record
-            .stages
-            .iter()
-            .filter(|stage| {
-                stage.stage == EvidenceStageKind::Runtime
-                    && stage.mechanism == Some(lowering.mechanism)
-                    && stage.outcome == "succeeded"
-            })
-            .collect::<Vec<_>>();
-        ensure!(
-            runtime.len() == 1,
-            "{} executed target-matrix evidence requires one successful runtime stage",
-            policy.id
-        );
-        let (hardware, ptx) = selected_stage_floor(runtime[0])?;
-        ensure!(
-            expected_hardware
-                .iter()
-                .any(|expected| { selected_stage_hardware_matches(hardware, *expected, true) }),
-            "{} runtime target {} is outside its target matrix",
-            policy.id,
-            describe_stage_hardware(hardware)
-        );
-        let floor = target_matrix_ptx_floor(policy, hardware, paired_alternatives, true)?;
-        let ptx_matches = match lowering.backend {
-            IntrinsicBackend::LlvmNvptx => ptx == floor,
-            IntrinsicBackend::LibNvvm => ptx >= floor,
-        };
-        ensure!(
-            ptx_matches,
-            "{} runtime target {} records PTX {}.{} instead of its paired floor {}.{}",
-            policy.id,
-            describe_stage_hardware(hardware),
-            ptx / 10,
-            ptx % 10,
-            floor / 10,
-            floor % 10
-        );
-    }
-    Ok(())
-}
-
-fn target_matrix_ptx_floor(
-    policy: &OverlayIntrinsic,
-    hardware: CatalogHardwareAlternative,
-    paired_alternatives: Option<&[CatalogTargetAlternative]>,
-    allow_forward_minimum: bool,
-) -> Result<u16> {
-    if let Some(alternatives) = paired_alternatives {
-        return alternatives
-            .iter()
-            .filter(|alternative| {
-                selected_stage_hardware_matches(
-                    hardware,
-                    alternative.hardware,
-                    allow_forward_minimum,
-                )
-            })
-            .map(|alternative| alternative.minimum_ptx.encoded())
-            .min()
-            .with_context(|| {
-                format!(
-                    "{} target matrix has no PTX floor for {}",
-                    policy.id,
-                    describe_stage_hardware(hardware)
-                )
-            });
-    }
-    if is_f8f6f4_mma_target_matrix_policy(policy) {
-        f8f6f4_llvm_ptx_floor(hardware)
-    } else {
-        blackwell_ldmatrix_llvm_ptx_floor(hardware)
-    }
-}
-
-fn f8f6f4_llvm_ptx_floor(hardware: CatalogHardwareAlternative) -> Result<u16> {
-    match hardware {
-        CatalogHardwareAlternative::ExactArchitecture { sm: 120 }
-        | CatalogHardwareAlternative::FamilyTarget { sm: 120 }
-        | CatalogHardwareAlternative::ExactArchitecture { sm: 121 }
-        | CatalogHardwareAlternative::FamilyTarget { sm: 121 } => {
-            recorded_stage_ptx_floor(hardware, 87)
-        }
-        _ => bail!(
-            "{} is not a reviewed f8f6f4 MMA target",
-            describe_stage_hardware(hardware)
-        ),
-    }
-}
-
-fn blackwell_ldmatrix_llvm_ptx_floor(hardware: CatalogHardwareAlternative) -> Result<u16> {
-    match hardware {
-        CatalogHardwareAlternative::ExactArchitecture {
-            sm: 100 | 103 | 110 | 120 | 121,
-        }
-        | CatalogHardwareAlternative::FamilyTarget {
-            sm: 100 | 103 | 120 | 121,
-        }
-        | CatalogHardwareAlternative::FamilyTarget { sm: 110 } => {
-            recorded_stage_ptx_floor(hardware, 86)
-        }
-        _ => bail!(
-            "{} is not a reviewed Blackwell ldmatrix target",
-            describe_stage_hardware(hardware)
-        ),
-    }
-}
-
-fn recorded_stage_ptx_floor(
-    hardware: CatalogHardwareAlternative,
-    instruction_floor: u16,
-) -> Result<u16> {
-    let (sm, suffix) = match hardware {
-        CatalogHardwareAlternative::MinimumSm { sm } => (sm, None),
-        CatalogHardwareAlternative::ExactArchitecture { sm } => (sm, Some('a')),
-        CatalogHardwareAlternative::FamilyTarget { sm } => (sm, Some('f')),
-    };
-    let arch = CudaArch::new(u32::from(sm), suffix)?;
-    Ok(instruction_floor.max(recorded_ptx_floor(&arch)?))
-}
-
-fn successful_stage(
-    record: &EvidenceRecord,
-    mechanism: BackendLoweringMechanism,
-    kind: EvidenceStageKind,
-) -> Option<&crate::model::EvidenceStage> {
-    record.stages.iter().find(|stage| {
-        stage.stage == kind && stage.mechanism == Some(mechanism) && stage.outcome == "succeeded"
-    })
-}
-
-fn is_normalized_stage_target(target: &str) -> bool {
-    if let Some(value) = target.strip_prefix("ptx") {
-        return value.len() == 2 && value.bytes().all(|byte| byte.is_ascii_digit());
-    }
-    parse_stage_hardware(target).is_some()
-}
-
-fn parse_stage_hardware(target: &str) -> Option<CatalogHardwareAlternative> {
-    let arch = target.parse::<CudaArch>().ok()?;
-    let canonical = if target.starts_with("sm_") {
-        arch.sm()
-    } else if target.starts_with("compute_") {
-        arch.compute()
-    } else {
-        return None;
-    };
-    if canonical != target || !matches!(arch.capability().to_string().len(), 2 | 3) {
-        return None;
-    }
-    let sm = u16::try_from(arch.capability()).ok()?;
-    Some(match arch.suffix() {
-        None => CatalogHardwareAlternative::MinimumSm { sm },
-        Some('a') => CatalogHardwareAlternative::ExactArchitecture { sm },
-        Some('f') => CatalogHardwareAlternative::FamilyTarget { sm },
-        _ => unreachable!(),
-    })
-}
-
-fn selected_stage_hardware_matches(
-    actual: CatalogHardwareAlternative,
-    expected: CatalogHardwareAlternative,
-    allow_forward_minimum: bool,
-) -> bool {
-    match expected {
-        CatalogHardwareAlternative::MinimumSm { sm: expected } => {
-            if allow_forward_minimum {
-                match actual {
-                    CatalogHardwareAlternative::MinimumSm { sm }
-                    | CatalogHardwareAlternative::ExactArchitecture { sm }
-                    | CatalogHardwareAlternative::FamilyTarget { sm } => sm >= expected,
-                }
-            } else {
-                actual == CatalogHardwareAlternative::MinimumSm { sm: expected }
-            }
-        }
-        CatalogHardwareAlternative::ExactArchitecture { .. }
-        | CatalogHardwareAlternative::FamilyTarget { .. } => actual == expected,
-    }
-}
-
-fn describe_stage_hardware(hardware: CatalogHardwareAlternative) -> String {
-    match hardware {
-        CatalogHardwareAlternative::MinimumSm { sm } => format!("sm_{sm}"),
-        CatalogHardwareAlternative::ExactArchitecture { sm } => format!("sm_{sm}a"),
-        CatalogHardwareAlternative::FamilyTarget { sm } => format!("sm_{sm}f"),
-    }
-}
-
-fn selected_stage_floor(
-    stage: &crate::model::EvidenceStage,
-) -> Result<(CatalogHardwareAlternative, u16)> {
-    let mut hardware = None;
-    let mut ptx = None;
-    for target in &stage.targets {
-        if let Some(value) = target.strip_prefix("ptx") {
-            let value = value.parse::<u16>()?;
-            ensure!(
-                ptx.replace(value).is_none(),
-                "stage has duplicate PTX targets"
-            );
-        } else {
-            let value = parse_stage_hardware(target)
-                .with_context(|| format!("stage has unsupported target spelling {target:?}"))?;
-            ensure!(
-                hardware.replace(value).is_none(),
-                "stage has duplicate architecture targets"
-            );
-        }
-    }
-    Ok((
-        hardware.context("selected stage has no architecture target")?,
-        ptx.context("selected stage has no PTX target")?,
-    ))
-}
-
-fn has_valid_ptx_assembly_stage(
-    record: &EvidenceRecord,
-    mechanism: BackendLoweringMechanism,
-) -> bool {
-    has_valid_tool_stage(record, mechanism, EvidenceStageKind::PtxAssembly)
-}
-
-fn has_valid_cubin_device_link_stage(
-    record: &EvidenceRecord,
-    mechanism: BackendLoweringMechanism,
-) -> bool {
-    has_valid_tool_stage(record, mechanism, EvidenceStageKind::DeviceLink)
-        && successful_stage(record, mechanism, EvidenceStageKind::DeviceLink)
-            .is_some_and(|stage| stage.artifact_kind == Some(EvidenceArtifactKind::Cubin))
-}
-
-fn has_valid_tool_stage(
-    record: &EvidenceRecord,
-    mechanism: BackendLoweringMechanism,
-    stage_kind: EvidenceStageKind,
-) -> bool {
-    record.stages.iter().any(|stage| {
-        stage.stage == stage_kind
-            && stage.mechanism == Some(mechanism)
-            && stage.outcome == "succeeded"
-            && stage
-                .tool_path
-                .as_deref()
-                .is_some_and(|value| !value.is_empty())
-            && stage
-                .tool_version
-                .as_deref()
-                .is_some_and(|value| !value.is_empty())
-            && stage.tool_sha256.as_deref().is_some_and(|value| {
-                value.len() == 64 && value.bytes().all(|byte| byte.is_ascii_hexdigit())
-            })
-    })
-}
-
-fn resolve_backend_lowerings(
-    policy: &OverlayIntrinsic,
-    evidence_by_profile_id: &BTreeMap<(&str, &str), IndexedEvidence<'_>>,
-) -> Result<Vec<CatalogBackendLowering>> {
-    let mut resolved = Vec::with_capacity(policy.backend_lowerings.len());
-    let mut runtime_states = Vec::with_capacity(policy.backend_lowerings.len());
-    for lowering in &policy.backend_lowerings {
-        let evidence = evidence_by_profile_id
-            .get(&(lowering.evidence_profile.as_str(), policy.id.as_str()))
-            .with_context(|| {
-                format!(
-                    "{} has no evidence in backend profile {}",
-                    policy.id, lowering.evidence_profile
-                )
-            })?;
-        validate_evidence(policy, evidence, Some(lowering))?;
-        runtime_states.push(evidence.record.runtime_validation);
-        resolved.push(CatalogBackendLowering {
-            backend: lowering.backend,
-            mechanism: lowering.mechanism,
-            evidence_profile: lowering.evidence_profile.clone(),
-            target: backend_target_requirement(policy, lowering)?,
-            version: evidence.backend_version.to_owned(),
-            sha256: evidence.backend_sha256.to_owned(),
-            artifact_path: evidence.file.artifact_path.clone(),
-            build_id_prefix: evidence.file.build_id_prefix.clone(),
-            status: evidence.record.status.clone(),
-            stages: evidence.record.stages.clone(),
-        });
-    }
-    if let Some(safety) = &policy.ldmatrix_safety {
-        match safety.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} overlay says runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} overlay says runtime is executed but no backend evidence has an executed runtime stage",
-                policy.id
-            ),
-        }
-    }
-    if policy.family == "stmatrix" {
-        ensure!(
-            runtime_states
-                .iter()
-                .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-            "{} stmatrix source contract is unexecuted but backend evidence disagrees",
-            policy.id
-        );
-    }
-    if let Some(packed) = &policy.packed_atomic {
-        match packed.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} packed-atomic runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} packed-atomic runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(mbarrier) = &policy.mbarrier_basic {
-        match mbarrier.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} mbarrier runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} mbarrier runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(movmatrix) = &policy.movmatrix {
-        match movmatrix.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} movmatrix runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} movmatrix runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(mbarrier) = &policy.mbarrier_extended {
-        match mbarrier.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} extended-mbarrier runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} extended-mbarrier runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(bridge) = &policy.cp_async_mbarrier {
-        match bridge.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} cp.async mbarrier runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} cp.async mbarrier runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(mma) = &policy.register_mma {
-        match mma.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} register-MMA runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} register-MMA runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(mma) = &policy.sparse_mma {
-        match mma.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} sparse-MMA runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} sparse-MMA runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(debug) = &policy.debug_control {
-        match debug.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} debug-control runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} debug-control runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(cluster_memory) = &policy.cluster_memory {
-        match cluster_memory.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} cluster-memory runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} cluster-memory runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(clc) = &policy.clc {
-        match clc.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} CLC runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} CLC runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(conversion) = &policy.scalar_conversion {
-        match conversion.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} scalar-conversion runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} scalar-conversion runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    if let Some(arithmetic) = &policy.scalar_arithmetic {
-        match arithmetic.runtime_validation {
-            RuntimeValidation::Unexecuted => ensure!(
-                runtime_states
-                    .iter()
-                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
-                "{} scalar-arithmetic runtime is unexecuted but backend evidence disagrees",
-                policy.id
-            ),
-            RuntimeValidation::Executed => ensure!(
-                runtime_states.contains(&Some(RuntimeValidation::Executed)),
-                "{} scalar-arithmetic runtime is executed but no backend evidence records execution",
-                policy.id
-            ),
-        }
-    }
-    resolved.sort_by_key(|lowering| lowering.backend);
-    Ok(resolved)
-}
-
-#[allow(clippy::too_many_arguments)]
-fn resolve_record(
-    policy: &OverlayIntrinsic,
-    source: IntrinsicSource,
-    declaration: Option<&ImportedIntrinsic>,
-    evidence: &EvidenceRecord,
-    backend_profile: &str,
-    backend_version: &str,
-    backend_sha256: &str,
-    backend_lowerings: Vec<CatalogBackendLowering>,
-    intrinsic_abi: u32,
-) -> Result<CatalogIntrinsic> {
-    materialize_record(
-        policy,
-        source,
-        declaration,
-        CatalogBackend {
-            profile: backend_profile.to_owned(),
-            version: backend_version.to_owned(),
-            sha256: backend_sha256.to_owned(),
-            status: evidence.status.clone(),
-            target_triple: evidence.target_triple.clone(),
-            gpu_target: evidence.gpu_target.clone(),
-            ptx_feature: evidence.ptx_feature.clone(),
-        },
-        backend_lowerings,
-        intrinsic_abi,
-    )
-}
-
-fn materialize_record(
-    policy: &OverlayIntrinsic,
-    source: IntrinsicSource,
-    declaration: Option<&ImportedIntrinsic>,
-    backend: CatalogBackend,
-    backend_lowerings: Vec<CatalogBackendLowering>,
-    intrinsic_abi: u32,
-) -> Result<CatalogIntrinsic> {
-    let native_target = if let Some(mma) = policy
-        .tcgen05
-        .as_ref()
-        .and_then(|tcgen05| tcgen05.mma.as_ref())
-    {
-        mma.llvm_target.clone()
-    } else {
-        CatalogTargetRequirement {
-            minimum_ptx: parse_ptx_version(&policy.minimum_ptx, &policy.id)?,
-            hardware: parse_hardware_target(policy)?,
-        }
-    };
-    let llvm = if let Some(declaration) = declaration {
-        Some(CatalogLlvm {
-            symbol: policy
-                .llvm_symbol
-                .clone()
-                .expect("validated imported LLVM symbol"),
-            resolved_symbol: policy.resolved_llvm_symbol.clone(),
-            arguments: policy.llvm_arguments.clone(),
-            results: policy.llvm_results.clone(),
-            properties: declaration.properties.clone(),
-            result_facts: imported_result_facts(&declaration.properties)?,
-        })
-    } else {
-        None
-    };
-    let preserves_empty_dialect_signature = (policy.family == "sync"
-        && policy.id == "sync_threads")
-        || matches!(
-            ExecutionControlOperation::from_catalog_id(&policy.id),
-            Some(
-                ExecutionControlOperation::SetMaxNRegInc | ExecutionControlOperation::SetMaxNRegDec
-            )
-        );
-    let dialect_operands =
-        if policy.dialect_operands.is_empty() && !preserves_empty_dialect_signature {
-            policy.llvm_arguments.clone()
-        } else {
-            policy.dialect_operands.clone()
-        };
-    let dialect_results = if policy.dialect_results.is_empty() && !preserves_empty_dialect_signature
-    {
-        policy.llvm_results.clone()
-    } else {
-        policy.dialect_results.clone()
-    };
-    let mut selections = Vec::new();
-    for selection in declaration
-        .into_iter()
-        .flat_map(|declaration| declaration.selections.iter())
-    {
-        if selection_matches_policy(policy, selection)? {
-            selections.push(CatalogSelection {
-                source_record: selection.source_record.clone(),
-                asm: selection.asm.clone(),
-                predicates: selection.predicates.clone(),
-                constraints: selection.constraints.clone(),
-            });
-        }
-    }
-    Ok(CatalogIntrinsic {
-        id: policy.id.clone(),
-        operation_key: policy.operation_key.clone(),
-        family: policy.family.clone(),
-        source,
-        selections,
-        rust: CatalogRust {
-            abi_id: policy.abi_id.clone(),
-            module: policy.rust_module.clone(),
-            name: policy.rust_name.clone(),
-            arguments: policy.rust_arguments.clone(),
-            result: policy.rust_result.clone(),
-            safe: policy.safe,
-            must_use: policy.must_use,
-            safe_allowlist_reason: policy.safe_allowlist_reason.clone(),
-            canonical_path: canonical_rust_path(intrinsic_abi, &policy.abi_id),
-            public_path: policy.public_rust_path.clone(),
-            compatibility_paths: policy.compatibility_rust_paths.clone(),
-        },
-        dialect: CatalogDialect {
-            op_type: policy.dialect_op_type.clone(),
-            op_name: policy.dialect_op_name.clone(),
-            operands: dialect_operands,
-            results: dialect_results,
-        },
-        llvm,
-        semantics: CatalogSemantics {
-            pure: policy.pure,
-            memory: policy.memory.clone(),
-            convergent: policy.convergent,
-            execution_scope: policy.execution_scope.clone(),
-        },
-        target: CatalogTarget {
-            minimum_ptx: native_target.minimum_ptx,
-            hardware: native_target.hardware,
-            ptx_result: policy.ptx_result.clone(),
-            targets: policy.targets.clone(),
-            ptx_isa_version: policy.ptx_isa_version.clone(),
-            ptx_isa_section: policy.ptx_isa_section.clone(),
-            ptx_isa_url: policy.ptx_isa_url.clone(),
-        },
-        backend,
-        backend_lowerings,
-        packed_atomic: policy.packed_atomic.clone(),
-        redux: policy.redux.clone(),
-        vote: policy.vote.clone(),
-        active_mask: policy.active_mask.clone(),
-        warp_match: policy.warp_match.clone(),
-        warp_barrier: policy.warp_barrier.clone(),
-        warp_shuffle: policy.warp_shuffle.clone(),
-        dot_product: policy.dot_product.clone(),
-        packed_alu: policy.packed_alu.clone(),
-        integer_minmax: policy.integer_minmax.clone(),
-        packed_conversion: policy.packed_conversion.clone(),
-        scalar_conversion: policy.scalar_conversion.clone(),
-        scalar_arithmetic: policy.scalar_arithmetic.clone(),
-        scalar_math: policy.scalar_math.clone(),
-        extended_minmax: policy.extended_minmax.clone(),
-        cp_async_copy: policy.cp_async_copy.clone(),
-        cp_async_control: policy.cp_async_control.clone(),
-        cp_async_mbarrier: policy.cp_async_mbarrier.clone(),
-        mbarrier_basic: policy.mbarrier_basic.clone(),
-        movmatrix: policy.movmatrix.clone(),
-        mbarrier_extended: policy.mbarrier_extended.clone(),
-        register_mma: policy.register_mma.clone(),
-        sparse_mma: policy.sparse_mma.clone(),
-        prmt: policy.prmt.clone(),
-        cluster_barrier: policy.cluster_barrier.clone(),
-        wgmma_control: policy.wgmma_control.clone(),
-        special_register: policy.special_register.clone(),
-        debug_control: policy.debug_control.clone(),
-        cluster_memory: policy.cluster_memory.clone(),
-        clc: policy.clc.clone(),
-        tma: policy.tma.clone(),
-        tcgen05: policy.tcgen05.clone(),
-        ldmatrix: policy
-            .ldmatrix_variant
-            .clone()
-            .map(|variant| CatalogLdmatrix {
-                variant,
-                safety: policy
-                    .ldmatrix_safety
-                    .clone()
-                    .expect("validated ldmatrix safety"),
-                adapter: policy.ldmatrix_adapter.expect("validated ldmatrix adapter"),
-                selected_address_space: policy
-                    .selected_address_space
-                    .expect("validated ldmatrix address space"),
-            }),
-        lowering: policy.lowering.clone(),
-        expected_ptx: policy.expected_ptx.clone(),
-        summary: policy.summary.clone(),
-    })
-}
-
-fn imported_result_facts(properties: &[String]) -> Result<CatalogLlvmResultFacts> {
-    let no_undef = properties.iter().any(|property| property == "NoUndef<ret>");
-    let mut range = None;
-    for property in properties {
-        let Some(bounds) = property
-            .strip_prefix("Range<ret,")
-            .and_then(|value| value.strip_suffix('>'))
-        else {
-            continue;
-        };
-        let (lower, upper_exclusive) = bounds
-            .split_once(',')
-            .with_context(|| format!("malformed return range property {property:?}"))?;
-        ensure!(
-            !lower.is_empty() && !upper_exclusive.is_empty(),
-            "malformed return range property {property:?}"
-        );
-        ensure!(range.is_none(), "duplicate return range properties");
-        range = Some(CatalogHalfOpenRange {
-            lower: lower.to_owned(),
-            upper_exclusive: upper_exclusive.to_owned(),
-        });
-    }
-    Ok(CatalogLlvmResultFacts { no_undef, range })
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use crate::model::{ImportedSelection, ScalarConversionAdmissionVariant};
-
-    #[test]
-    fn f32_redux_recipes_match_pinned_llvm_records() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect();
-        let cases = [
-            (
-                ReduxOperation::Fmin,
-                "redux.sync.min.f32 \t$dst, $src, $mask;",
-                &["sync", "min", "f32"][..],
-            ),
-            (
-                ReduxOperation::FminNan,
-                "redux.sync.min.NaN.f32 \t$dst, $src, $mask;",
-                &["sync", "min", "NaN", "f32"],
-            ),
-            (
-                ReduxOperation::FminAbs,
-                "redux.sync.min.abs.f32 \t$dst, $src, $mask;",
-                &["sync", "min", "abs", "f32"],
-            ),
-            (
-                ReduxOperation::FminAbsNan,
-                "redux.sync.min.abs.NaN.f32 \t$dst, $src, $mask;",
-                &["sync", "min", "abs", "NaN", "f32"],
-            ),
-            (
-                ReduxOperation::Fmax,
-                "redux.sync.max.f32 \t$dst, $src, $mask;",
-                &["sync", "max", "f32"],
-            ),
-            (
-                ReduxOperation::FmaxNan,
-                "redux.sync.max.NaN.f32 \t$dst, $src, $mask;",
-                &["sync", "max", "NaN", "f32"],
-            ),
-            (
-                ReduxOperation::FmaxAbs,
-                "redux.sync.max.abs.f32 \t$dst, $src, $mask;",
-                &["sync", "max", "abs", "f32"],
-            ),
-            (
-                ReduxOperation::FmaxAbsNan,
-                "redux.sync.max.abs.NaN.f32 \t$dst, $src, $mask;",
-                &["sync", "max", "abs", "NaN", "f32"],
-            ),
-        ];
-
-        for (operation, expected_asm, expected_modifiers) in cases {
-            let recipe = redux_recipe(operation);
-            let declaration = declarations[recipe.source_record];
-            assert_eq!(declaration.llvm_name, recipe.llvm_symbol);
-            assert_eq!(declaration.arguments, ["f32", "i32"]);
-            assert_eq!(declaration.results, ["f32"]);
-            assert_eq!(declaration.selections.len(), 1);
-            assert_eq!(declaration.selections[0].asm, expected_asm);
-            assert_eq!(
-                declaration.selections[0].predicates,
-                ["Subtarget->hasReduxSyncF32()"]
-            );
-            assert_eq!(recipe.ptx_modifiers, expected_modifiers);
-            assert_eq!(recipe.minimum_ptx, "8.6");
-            assert_eq!(recipe.minimum_sm, None);
-            assert_eq!(recipe.targets, REDUX_F32_TARGETS);
-        }
-    }
-
-    fn sreg_pattern(special_register: &str) -> InstructionPattern {
-        InstructionPattern::new(
-            "mov",
-            &["u32"],
-            vec![
-                OperandPattern::Register,
-                OperandPattern::Exact {
-                    value: special_register.into(),
-                },
-            ],
-        )
-    }
-
-    fn policy() -> OverlayIntrinsic {
-        OverlayIntrinsic {
-            id: "thread_idx_x".into(),
-            abi_id: "i0001".into(),
-            operation_key: "launch.thread_index.x".into(),
-            family: "sreg".into(),
-            source: None,
-            source_record: Some("int_nvvm_read_ptx_sreg_tid_x".into()),
-            rust_module: "sreg".into(),
-            rust_name: "thread_idx_x".into(),
-            rust_arguments: vec![],
-            rust_result: "u32".into(),
-            safe: true,
-            must_use: false,
-            safe_allowlist_reason: Some("no caller obligations".into()),
-            public_rust_path: "cuda_intrinsics::sreg::thread_idx_x".into(),
-            compatibility_rust_paths: vec!["cuda_device::thread::threadIdx_x".into()],
-            dialect_op_type: "ReadPtxSregTidXOp".into(),
-            dialect_op_name: "nvvm.read_ptx_sreg_tid_x".into(),
-            dialect_operands: vec![],
-            dialect_results: vec![],
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.tid.x".into()),
-            resolved_llvm_symbol: None,
-            llvm_arguments: vec![],
-            llvm_results: vec!["i32".into()],
-            pure: true,
-            memory: "none".into(),
-            convergent: false,
-            execution_scope: "thread".into(),
-            minimum_ptx: "2.0".into(),
-            minimum_sm: None,
-            ptx_result: "u32".into(),
-            targets: "all".into(),
-            ptx_isa_version: "9.3".into(),
-            ptx_isa_section: "10.1 Special Registers: %tid".into(),
-            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/".into(),
-            lowering: "direct_nvvm".into(),
-            backend_lowerings: vec![],
-            packed_atomic: None,
-            redux: None,
-            vote: None,
-            active_mask: None,
-            warp_match: None,
-            warp_barrier: None,
-            warp_shuffle: None,
-            dot_product: None,
-            packed_alu: None,
-            integer_minmax: None,
-            packed_conversion: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cp_async_copy: None,
-            cp_async_control: None,
-            cp_async_mbarrier: None,
-            mbarrier_basic: None,
-            movmatrix: None,
-            mbarrier_extended: None,
-            register_mma: None,
-            sparse_mma: None,
-            prmt: None,
-            cluster_barrier: None,
-            wgmma_control: None,
-            special_register: None,
-            debug_control: None,
-            cluster_memory: None,
-            clc: None,
-            tma: None,
-            tcgen05: None,
-            ldmatrix_variant: None,
-            ldmatrix_safety: None,
-            ldmatrix_adapter: None,
-            selected_address_space: None,
-            expected_ptx: sreg_pattern("%tid.x"),
-            summary: "thread index".into(),
-        }
-    }
-
-    fn distinct_policy() -> OverlayIntrinsic {
-        let mut record = policy();
-        record.id = "thread_idx_y".into();
-        record.abi_id = "i0002".into();
-        record.operation_key = "launch.thread_index.y".into();
-        record.source_record = Some("int_nvvm_read_ptx_sreg_tid_y".into());
-        record.rust_name = "thread_idx_y".into();
-        record.public_rust_path = "cuda_intrinsics::sreg::thread_idx_y".into();
-        record.compatibility_rust_paths = vec!["cuda_device::thread::threadIdx_y".into()];
-        record.dialect_op_type = "ReadPtxSregTidYOp".into();
-        record.dialect_op_name = "nvvm.read_ptx_sreg_tid_y".into();
-        record.llvm_symbol = Some("llvm.nvvm.read.ptx.sreg.tid.y".into());
-        record.expected_ptx = sreg_pattern("%tid.y");
-        record
-    }
-
-    fn movmatrix_policy() -> OverlayIntrinsic {
-        let mut record = policy();
-        record.id = "movmatrix_trans_b16".into();
-        record.abi_id = "i0305".into();
-        record.operation_key = "movmatrix.m8n8.trans.b16".into();
-        record.family = "movmatrix".into();
-        record.source = Some(IntrinsicSource::PtxNative {
-            instruction: "movmatrix.sync.aligned.m8n8.trans.b16".into(),
-        });
-        record.source_record = None;
-        record.rust_module = "matrix".into();
-        record.rust_name = "movmatrix_trans_b16".into();
-        record.rust_arguments = vec!["u32".into()];
-        record.rust_result = "u32".into();
-        record.safe = false;
-        record.must_use = true;
-        record.safe_allowlist_reason = None;
-        record.public_rust_path = "cuda_intrinsics::matrix::movmatrix_trans_b16".into();
-        record.compatibility_rust_paths = vec!["cuda_device::wmma::movmatrix_trans_b16".into()];
-        record.dialect_op_type = "MovmatrixTransB16Op".into();
-        record.dialect_op_name = "nvvm.movmatrix_trans_b16".into();
-        record.dialect_operands = vec!["i32".into()];
-        record.dialect_results = vec!["i32".into()];
-        record.llvm_symbol = None;
-        record.resolved_llvm_symbol = None;
-        record.llvm_arguments.clear();
-        record.llvm_results.clear();
-        record.pure = false;
-        record.memory = "inaccessible_read_write".into();
-        record.convergent = true;
-        record.execution_scope = "warp".into();
-        record.minimum_ptx = "7.8".into();
-        record.minimum_sm = Some("sm_75".into());
-        record.ptx_result = "u32".into();
-        record.targets = "all".into();
-        record.ptx_isa_section =
-            "9.7.15.5.17 Warp-level matrix transpose instruction: movmatrix".into();
-        record.lowering = "generated_movmatrix_inline_ptx".into();
-        record.backend_lowerings = [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
-            .into_iter()
-            .map(|backend| OverlayBackendLowering {
-                backend,
-                mechanism: BackendLoweringMechanism::InlinePtx,
-                evidence_profile: match backend {
-                    IntrinsicBackend::LlvmNvptx => "llvm-test",
-                    IntrinsicBackend::LibNvvm => "libnvvm-test",
-                }
-                .into(),
-                targets: None,
-                minimum_ptx: Some("7.8".into()),
-                minimum_sm: Some("sm_75".into()),
-            })
-            .collect();
-        record.movmatrix = Some(crate::model::Movmatrix {
-            participation: MovmatrixParticipation::AllWarpLanesSameInstructionNoExitedLanes,
-            adapter: MovmatrixAdapter::PackedB16x2U32ToPackedB16x2U32,
-            runtime_validation: RuntimeValidation::Unexecuted,
-        });
-        record.expected_ptx = InstructionPattern::new(
-            "movmatrix",
-            &["sync", "aligned", "m8n8", "trans", "b16"],
-            vec![OperandPattern::Register, OperandPattern::Register],
-        );
-        record.summary = "Transposes one packed b16 matrix fragment across a warp.".into();
-        record
-    }
-
-    fn declaration() -> ImportedIntrinsic {
-        ImportedIntrinsic {
-            source_record: "int_nvvm_read_ptx_sreg_tid_x".into(),
-            llvm_name: "llvm.nvvm.read.ptx.sreg.tid.x".into(),
-            arguments: vec![],
-            results: vec!["i32".into()],
-            classes: vec!["NVVMPureIntrinsic".into()],
-            properties: vec![
-                "IntrNoMem".into(),
-                "IntrSpeculatable".into(),
-                "NoUndef<ret>".into(),
-                "Range<ret,0,1024>".into(),
-            ],
-            selections: vec![ImportedSelection {
-                source_record: "INT_PTX_SREG_TID_x".into(),
-                asm: "mov.u32 $d, %tid.x;".into(),
-                predicates: vec![],
-                constraints: Default::default(),
-            }],
-        }
-    }
-
-    fn evidence() -> EvidenceRecord {
-        EvidenceRecord {
-            id: "thread_idx_x".into(),
-            source: None,
-            source_record: Some("int_nvvm_read_ptx_sreg_tid_x".into()),
-            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.tid.x".into()),
-            resolved_llvm_symbol: None,
-            llvm_arguments: vec![],
-            llvm_results: vec!["i32".into()],
-            concrete_llvm_arguments: vec![],
-            concrete_llvm_results: vec![],
-            target_triple: "nvptx64-nvidia-cuda".into(),
-            gpu_target: "sm_70".into(),
-            ptx_feature: "+ptx60".into(),
-            status: "lowered".into(),
-            stages: vec![],
-            declaration_attributes_canonicalized: None,
-            runtime_validation: None,
-            expected_ptx: sreg_pattern("%tid.x"),
-        }
-    }
-
-    fn validate_test_evidence(policy: &OverlayIntrinsic, record: EvidenceRecord) -> Result<()> {
-        let file = EvidenceFile {
-            schema: 3,
-            backend_profile: "test".into(),
-            backend_kind: None,
-            llvm_revision: "test".into(),
-            backend_version: "LLVM version test".into(),
-            backend_sha256: "0123456789abcdef".into(),
-            artifact_path: None,
-            build_id_prefix: None,
-            nvvm_ir_version: None,
-            debug_ir_version: None,
-            records: vec![record],
-        };
-        let indexed = IndexedEvidence {
-            file: &file,
-            record: &file.records[0],
-            backend_version: &file.backend_version,
-            backend_sha256: &file.backend_sha256,
-        };
-        validate_evidence(policy, &indexed, None)
-    }
-
-    fn shared_matrix_stage() -> EvidenceStage {
-        EvidenceStage {
-            targets: vec!["sm_80".into(), "ptx71".into()],
-            representation: "shared fixture".into(),
-            stage: EvidenceStageKind::BackendCodegen,
-            mechanism: Some(BackendLoweringMechanism::InlinePtx),
-            outcome: "succeeded".into(),
-            detail: "$dst remains fixture text".into(),
-            artifact_kind: None,
-            tool_path: None,
-            tool_version: None,
-            tool_sha256: None,
-        }
-    }
-
-    fn synthetic_matrix_json() -> serde_json::Value {
-        serde_json::json!({
-            "schema": 6,
-            "backend_profile": "matrix-test",
-            "backend_kind": "llvm_nvptx",
-            "llvm_revision": "test",
-            "backend_version": "LLVM matrix test",
-            "backend_sha256": "0123456789abcdef",
-            "defaults": {
-                "llvm_arguments": ["i32"],
-                "llvm_results": ["i32"],
-                "target_triple": "nvptx64-nvidia-cuda",
-                "gpu_target": "sm_80",
-                "ptx_feature": "+ptx71",
-                "status": "lowered"
-            },
-            "fixtures": [{
-                "id": "shared",
-                "coverage_count": 2,
-                "stages": [{
-                    "targets": ["sm_80", "ptx71"],
-                    "representation": "shared fixture",
-                    "stage": "backend_codegen",
-                    "mechanism": "inline_ptx",
-                    "outcome": "succeeded",
-                    "detail": "$dst remains fixture text"
-                }]
-            }],
-            "matrices": [{
-                "axes": [{
-                    "name": "element",
-                    "values": ["s8", "u8"]
-                }],
-                "product_count": 2,
-                "fixtures": ["shared"],
-                "template": {
-                    "id": "synthetic_${element}",
-                    "source_record": "int_synthetic_${element}",
-                    "llvm_symbol": "llvm.synthetic.${element}",
-                    "expected_ptx": {
-                        "mnemonic": "mma",
-                        "modifiers": ["sync", "${element}"],
-                        "operands": [{"kind": "register"}]
-                    }
-                }
-            }],
-            "records": [{
-                "id": "synthetic_explicit",
-                "source_record": "int_synthetic_explicit",
-                "llvm_symbol": "llvm.synthetic.explicit",
-                "llvm_arguments": ["i32"],
-                "llvm_results": ["i32"],
-                "target_triple": "nvptx64-nvidia-cuda",
-                "gpu_target": "sm_80",
-                "ptx_feature": "+ptx71",
-                "status": "lowered",
-                "expected_ptx": {
-                    "mnemonic": "mma",
-                    "modifiers": ["sync", "explicit"],
-                    "operands": [{"kind": "register"}]
-                }
-            }]
-        })
-    }
-
-    fn policy_matrix_json() -> serde_json::Value {
-        serde_json::json!({
-            "schema": 6,
-            "backend_profile": "matrix-test",
-            "llvm_revision": "test",
-            "backend_version": "LLVM matrix test",
-            "backend_sha256": "0123456789abcdef",
-            "defaults": {
-                "llvm_arguments": [],
-                "llvm_results": ["i32"],
-                "target_triple": "nvptx64-nvidia-cuda",
-                "gpu_target": "sm_70",
-                "ptx_feature": "+ptx60",
-                "status": "lowered"
-            },
-            "fixtures": [{
-                "id": "policy_fixture",
-                "coverage_count": 1,
-                "stages": [{
-                    "targets": ["sm_70", "ptx60"],
-                    "representation": "policy fixture",
-                    "stage": "backend_codegen",
-                    "mechanism": "typed_nvvm",
-                    "outcome": "succeeded",
-                    "detail": "shared policy fixture"
-                }]
-            }],
-            "matrices": [{
-                "axes": [{
-                    "name": "axis",
-                    "values": ["x"]
-                }],
-                "product_count": 1,
-                "fixtures": ["policy_fixture"],
-                "template": {
-                    "id": "thread_idx_${axis}",
-                    "source_record": "int_nvvm_read_ptx_sreg_tid_${axis}",
-                    "llvm_symbol": "llvm.nvvm.read.ptx.sreg.tid.${axis}",
-                    "expected_ptx": {
-                        "mnemonic": "mov",
-                        "modifiers": ["u32"],
-                        "operands": [
-                            {"kind": "register"},
-                            {"kind": "exact", "value": "%tid.${axis}"}
-                        ]
-                    }
-                }
-            }]
-        })
-    }
-
-    fn parse_synthetic_evidence(value: &serde_json::Value) -> Result<EvidenceFile> {
-        parse_evidence_bytes(&serde_json::to_vec(value).unwrap(), "synthetic evidence")
-    }
-
-    fn assert_synthetic_evidence_error(value: &serde_json::Value, expected: &str) {
-        let error = parse_synthetic_evidence(value).unwrap_err();
-        let message = format!("{error:#}");
-        assert!(
-            message.contains(expected),
-            "expected {expected:?} in {message:?}"
-        );
-    }
-
-    fn overlay_file(records: Vec<OverlayIntrinsic>) -> OverlayFile {
-        OverlayFile {
-            schema: OVERLAY_SCHEMA,
-            catalog_version: "test".into(),
-            intrinsic_abi: 1,
-            backend_profile: "test".into(),
-            shards: vec![],
-            intrinsics: records,
-        }
-    }
-
-    fn bind_pinned_abi_ids(repo_root: &Path, overlay: &mut OverlayFile) {
-        let ledger_path = repo_root.join(format!("intrinsics/abi-v{}.toml", overlay.intrinsic_abi));
-        let ledger: AbiLedgerFile =
-            toml::from_str(&std::fs::read_to_string(ledger_path).unwrap()).unwrap();
-        bind_generated_abi_ids(overlay, &ledger).unwrap();
-    }
-
-    fn validate_imported_policy(
-        policy: &OverlayIntrinsic,
-        declaration: &ImportedIntrinsic,
-    ) -> Result<()> {
-        let source = resolve_policy_source(policy)?;
-        validate_policy(policy, &source, Some(declaration), 1)
-    }
-
-    fn pinned_active_mask_and_warp_match_records()
-    -> BTreeMap<String, (OverlayIntrinsic, ImportedIntrinsic)> {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .into_iter()
-            .map(|record| (record.source_record.clone(), record))
-            .collect();
-
-        overlay
-            .intrinsics
-            .into_iter()
-            .filter(|record| matches!(record.family.as_str(), "active_mask" | "warp_match"))
-            .map(|policy| {
-                let declaration = declarations[policy.source_record.as_deref().unwrap()].clone();
-                (policy.id.clone(), (policy, declaration))
-            })
-            .collect()
-    }
-
-    fn pinned_mbarrier_basic_records() -> BTreeMap<String, (OverlayIntrinsic, ImportedIntrinsic)> {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .into_iter()
-            .map(|record| (record.source_record.clone(), record))
-            .collect();
-
-        overlay
-            .intrinsics
-            .into_iter()
-            .filter(|record| record.family == "mbarrier_basic")
-            .map(|policy| {
-                let declaration = declarations[policy.source_record.as_deref().unwrap()].clone();
-                (policy.id.clone(), (policy, declaration))
-            })
-            .collect()
-    }
-
-    fn pinned_cp_async_mbarrier_records() -> BTreeMap<String, (OverlayIntrinsic, ImportedIntrinsic)>
-    {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .into_iter()
-            .map(|record| (record.source_record.clone(), record))
-            .collect();
-
-        overlay
-            .intrinsics
-            .into_iter()
-            .filter(|record| record.family == "cp_async_mbarrier")
-            .map(|policy| {
-                let declaration = declarations[policy.source_record.as_deref().unwrap()].clone();
-                (policy.id.clone(), (policy, declaration))
-            })
-            .collect()
-    }
-
-    fn packed_policy(id: &str) -> OverlayIntrinsic {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml"))
-            .unwrap()
-            .0
-            .intrinsics
-            .into_iter()
-            .find(|record| record.id == id)
-            .unwrap()
-    }
-
-    fn packed_alu_policy(
-        format: PackedAluFormat,
-        operation: PackedAluOperation,
-    ) -> OverlayIntrinsic {
-        let recipe = packed_alu_recipe(format, operation).expect("test recipe pair");
-        let (rust_module, rust_type, dialect_type, adapter) = match format {
-            PackedAluFormat::Bf16x2 => ("bf16x2", "u32", "i32", PackedAluAdapter::DirectPackedU32),
-            PackedAluFormat::F16x2 => ("f16x2", "u32", "i32", PackedAluAdapter::DirectPackedU32),
-            PackedAluFormat::F32x2 => ("f32x2", "u64", "i64", PackedAluAdapter::DirectPackedU64),
-        };
-        let mut record = policy();
-        record.id = recipe.id.into();
-        record.abi_id = recipe.abi_id.into();
-        record.operation_key = recipe.operation_key.into();
-        record.family = "packed_alu".into();
-        match &recipe.source {
-            PackedAluRecipeSource::Imported {
-                record: source_record,
-                symbol,
-                resolved_symbol,
-                arguments,
-                results,
-                ..
-            } => {
-                record.source = None;
-                record.source_record = Some((*source_record).into());
-                record.llvm_symbol = Some((*symbol).into());
-                record.resolved_llvm_symbol = resolved_symbol.map(str::to_owned);
-                record.llvm_arguments = arguments.iter().map(|value| (*value).into()).collect();
-                record.llvm_results = results.iter().map(|value| (*value).into()).collect();
-            }
-            PackedAluRecipeSource::PtxNative => {
-                record.source = Some(IntrinsicSource::PtxNative {
-                    instruction: recipe.ptx_mnemonic.into(),
-                });
-                record.source_record = None;
-                record.llvm_symbol = None;
-                record.resolved_llvm_symbol = None;
-                record.llvm_arguments.clear();
-                record.llvm_results.clear();
-            }
-        }
-        record.rust_module = rust_module.into();
-        record.rust_name = recipe.rust_name.into();
-        record.rust_arguments = vec![rust_type.into(); recipe.arity];
-        record.rust_result = rust_type.into();
-        record.safe = true;
-        record.must_use = recipe.must_use;
-        record.safe_allowlist_reason = Some("the operation has no caller obligations".into());
-        record.public_rust_path = format!("cuda_intrinsics::{rust_module}::{}", recipe.rust_name);
-        record.compatibility_rust_paths =
-            vec![format!("cuda_device::{rust_module}::{}", recipe.rust_name)];
-        record.dialect_op_type = recipe.dialect_op_type.into();
-        record.dialect_op_name = recipe.dialect_op_name.into();
-        record.dialect_operands = vec![dialect_type.into(); recipe.arity];
-        record.dialect_results = vec![dialect_type.into()];
-        record.pure = true;
-        record.memory = "none".into();
-        record.convergent = false;
-        record.execution_scope = "thread".into();
-        record.minimum_ptx = recipe.minimum_ptx.into();
-        record.minimum_sm = Some(recipe.minimum_sm.into());
-        record.ptx_result = rust_type.into();
-        record.ptx_isa_section = recipe.ptx_isa_section.into();
-        record.ptx_isa_url = recipe.ptx_isa_url.into();
-        record.lowering = "generated_packed_alu_inline_ptx".into();
-        record.backend_lowerings = [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
-            .into_iter()
-            .map(|backend| {
-                let (minimum_ptx, minimum_sm) =
-                    packed_alu_backend_floor(&recipe, format, operation, backend);
-                crate::model::OverlayBackendLowering {
-                    backend,
-                    mechanism: BackendLoweringMechanism::InlinePtx,
-                    evidence_profile: format!("{backend:?}-test"),
-                    targets: None,
-                    minimum_ptx: Some(minimum_ptx.into()),
-                    minimum_sm: Some(minimum_sm.into()),
-                }
-            })
-            .collect();
-        record.packed_alu = Some(crate::model::PackedAlu {
-            format,
-            native_minimum_sm: recipe.native_minimum_sm,
-            operation,
-            adapter,
-        });
-        record.expected_ptx = InstructionPattern::new(
-            recipe.ptx_mnemonic.split('.').next().unwrap(),
-            recipe.modifiers,
-            vec![OperandPattern::Register; recipe.arity + 1],
-        );
-        record.summary = format!("packed {rust_module} arithmetic");
-        record
-    }
-
-    fn packed_alu_declaration(
-        format: PackedAluFormat,
-        operation: PackedAluOperation,
-    ) -> Option<ImportedIntrinsic> {
-        let recipe = packed_alu_recipe(format, operation).expect("test recipe pair");
-        let PackedAluRecipeSource::Imported {
-            record,
-            symbol,
-            arguments,
-            results,
-            properties,
-            selection,
-            selection_asm,
-            ..
-        } = recipe.source
-        else {
-            return None;
-        };
-        let classes = if matches!(operation, PackedAluOperation::Min | PackedAluOperation::Max) {
-            vec!["Intrinsic".into()]
-        } else {
-            vec!["Intrinsic".into(), "NVVMPureIntrinsic".into()]
-        };
-        let mut selections = vec![ImportedSelection {
-            source_record: selection.into(),
-            asm: selection_asm.into(),
-            predicates: vec![
-                format!("Subtarget->getSmVersion() >= {}", recipe.native_minimum_sm),
-                format!(
-                    "Subtarget->getPTXVersion() >= {}",
-                    recipe.minimum_ptx.replace('.', "")
-                ),
-            ],
-            constraints: Default::default(),
-        }];
-        if operation == PackedAluOperation::Abs {
-            selections.extend((0..5).map(|index| ImportedSelection {
-                source_record: format!("OTHER_ABS_{index}"),
-                asm: "abs.f32 $dst, $src0;".into(),
-                predicates: vec![],
-                constraints: Default::default(),
-            }));
-        }
-        Some(ImportedIntrinsic {
-            source_record: record.into(),
-            llvm_name: symbol.into(),
-            arguments: arguments.iter().map(|value| (*value).into()).collect(),
-            results: results.iter().map(|value| (*value).into()).collect(),
-            classes,
-            properties: properties.iter().map(|value| (*value).into()).collect(),
-            selections,
-        })
-    }
-
-    fn packed_conversion_policy(
-        destination_format: PackedConversionDestinationFormat,
-        rounding: PackedConversionRounding,
-        saturation: PackedConversionSaturation,
-    ) -> OverlayIntrinsic {
-        let conversion = crate::model::PackedConversion {
-            source_format: PackedConversionSourceFormat::F32x2,
-            destination_format,
-            rounding,
-            saturation,
-            adapter: PackedConversionAdapter::ReverseHighLowOperands,
-        };
-        let recipe = packed_conversion_recipe(&conversion).expect("test packed-conversion recipe");
-        let mut record = policy();
-        record.id = recipe.id.into();
-        record.abi_id = recipe.abi_id.into();
-        record.operation_key = recipe.operation_key.into();
-        record.family = "packed_conversion".into();
-        record.source_record = Some(recipe.source_record.into());
-        record.rust_module = "convert".into();
-        record.rust_name = recipe.rust_name.into();
-        record.rust_arguments = vec!["f32".into(), "f32".into()];
-        let result_width = packed_conversion_result_width(&conversion);
-        record.rust_result = format!("u{result_width}");
-        record.safe = true;
-        record.must_use = false;
-        record.safe_allowlist_reason = Some("the operation has no caller obligations".into());
-        record.public_rust_path = format!("cuda_intrinsics::convert::{}", recipe.rust_name);
-        record.compatibility_rust_paths = vec![recipe.compatibility_path.into()];
-        record.dialect_op_type = recipe.dialect_op_type.into();
-        record.dialect_op_name = recipe.dialect_op_name.into();
-        record.dialect_operands = vec!["f32".into(), "f32".into()];
-        record.dialect_results = vec![format!("i{result_width}")];
-        record.llvm_symbol = Some(recipe.llvm_symbol.into());
-        record.llvm_arguments = vec!["f32".into(), "f32".into()];
-        record.llvm_results = vec![recipe.llvm_result.into()];
-        record.pure = true;
-        record.memory = "none".into();
-        record.convergent = false;
-        record.execution_scope = "thread".into();
-        let (minimum_ptx, minimum_sm) = packed_conversion_floor(&conversion);
-        record.minimum_ptx = minimum_ptx.into();
-        record.minimum_sm = Some(minimum_sm.into());
-        record.ptx_result = format!("u{result_width}");
-        record.ptx_isa_section = "9.7.9.22 Data Movement and Conversion Instructions: cvt".into();
-        record.ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt".into();
-        record.lowering = packed_conversion_lowering(&conversion).into();
-        record.backend_lowerings = [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
-            .into_iter()
-            .map(|backend| OverlayBackendLowering {
-                backend,
-                mechanism: packed_conversion_backend_mechanism(&conversion, backend),
-                evidence_profile: "test".into(),
-                targets: None,
-                minimum_ptx: Some(minimum_ptx.into()),
-                minimum_sm: Some(minimum_sm.into()),
-            })
-            .collect();
-        let modifiers = packed_conversion_ptx_modifiers(&conversion);
-        record.packed_conversion = Some(conversion);
-        record.expected_ptx =
-            InstructionPattern::new("cvt", &modifiers, vec![OperandPattern::Register; 3]);
-        record.summary = recipe.summary.into();
-        record
-    }
-
-    fn packed_conversion_declaration(policy: &OverlayIntrinsic) -> ImportedIntrinsic {
-        ImportedIntrinsic {
-            source_record: policy.source_record.clone().unwrap(),
-            llvm_name: policy.llvm_symbol.clone().unwrap(),
-            arguments: policy.llvm_arguments.clone(),
-            results: policy.llvm_results.clone(),
-            classes: vec!["Intrinsic".into(), "NVVMPureIntrinsic".into()],
-            properties: vec!["IntrNoMem".into(), "IntrSpeculatable".into()],
-            selections: vec![],
-        }
-    }
-
-    fn packed_conversion_evidence(policy: &OverlayIntrinsic) -> EvidenceRecord {
-        let mut record = evidence();
-        record.id = policy.id.clone();
-        record.source_record = policy.source_record.clone();
-        record.llvm_symbol = policy.llvm_symbol.clone();
-        record.resolved_llvm_symbol = policy.resolved_llvm_symbol.clone();
-        record.llvm_arguments = policy.llvm_arguments.clone();
-        record.llvm_results = policy.llvm_results.clone();
-        record.concrete_llvm_arguments = policy.llvm_arguments.clone();
-        record.concrete_llvm_results = policy.llvm_results.clone();
-        record.declaration_attributes_canonicalized = Some(true);
-        record.expected_ptx = policy.expected_ptx.clone();
-        record
-    }
-
-    fn redux_policy() -> OverlayIntrinsic {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml"))
-            .unwrap()
-            .0
-            .intrinsics
-            .into_iter()
-            .find(|record| record.id == "redux_sync_add")
-            .unwrap()
-    }
-
-    fn redux_declaration() -> ImportedIntrinsic {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let text = std::fs::read_to_string(repo_root.join("intrinsics/imported.json")).unwrap();
-        serde_json::from_str::<ImportedFile>(&text)
-            .unwrap()
-            .intrinsics
-            .into_iter()
-            .find(|record| record.source_record == "int_nvvm_redux_sync_add")
-            .unwrap()
-    }
-
-    fn sync_policy() -> OverlayIntrinsic {
-        packed_policy("sync_threads")
-    }
-
-    fn sync_declaration() -> ImportedIntrinsic {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let text = std::fs::read_to_string(repo_root.join("intrinsics/imported.json")).unwrap();
-        serde_json::from_str::<ImportedFile>(&text)
-            .unwrap()
-            .intrinsics
-            .into_iter()
-            .find(|record| record.source_record == "int_nvvm_barrier_cta_sync_aligned_all")
-            .unwrap()
-    }
-
-    fn warp_barrier_policy() -> OverlayIntrinsic {
-        packed_policy("sync_mask")
-    }
-
-    fn warp_barrier_declaration() -> ImportedIntrinsic {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let text = std::fs::read_to_string(repo_root.join("intrinsics/imported.json")).unwrap();
-        serde_json::from_str::<ImportedFile>(&text)
-            .unwrap()
-            .intrinsics
-            .into_iter()
-            .find(|record| record.source_record == "int_nvvm_bar_warp_sync")
-            .unwrap()
-    }
-
-    fn vote_policy(mode: VoteMode) -> OverlayIntrinsic {
-        let recipe = vote_recipe(mode);
-        let mut record = policy();
-        record.id = recipe.id.into();
-        record.abi_id = recipe.abi_id.into();
-        record.operation_key = recipe.operation_key.into();
-        record.family = "vote".into();
-        record.source_record = Some(recipe.source_record.into());
-        record.rust_module = "warp".into();
-        record.rust_name = recipe.rust_name.into();
-        record.rust_arguments = vec!["u32".into(), "bool".into()];
-        record.rust_result = recipe.rust_result.into();
-        record.safe = false;
-        record.must_use = true;
-        record.safe_allowlist_reason = None;
-        record.public_rust_path = format!("cuda_intrinsics::warp::{}", recipe.rust_name);
-        record.compatibility_rust_paths = if recipe.has_compatibility_path {
-            vec![format!("cuda_device::warp::{}", recipe.rust_name)]
-        } else {
-            vec![]
-        };
-        record.dialect_op_type = recipe.dialect_op_type.into();
-        record.dialect_op_name = recipe.dialect_op_name.into();
-        record.dialect_operands = vec!["i32".into(), "i1".into()];
-        record.dialect_results = vec![recipe.llvm_result.into()];
-        record.llvm_symbol = Some(recipe.llvm_symbol.into());
-        record.llvm_arguments = vec!["i32".into(), "i1".into()];
-        record.llvm_results = vec![recipe.llvm_result.into()];
-        record.pure = false;
-        record.memory = "inaccessible_read_write".into();
-        record.convergent = true;
-        record.execution_scope = "warp".into();
-        record.minimum_ptx = "6.0".into();
-        record.minimum_sm = Some("sm_30".into());
-        record.ptx_result = recipe.rust_result.into();
-        record.ptx_isa_section = "9.7.14.10 Warp Vote Instructions: vote.sync".into();
-        record.ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-vote-sync".into();
-        record.lowering = "generated_vote".into();
-        record.vote = Some(crate::model::Vote {
-            mode,
-            participation: VoteParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
-            legacy_pre_sm70: PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive,
-            adapter: VoteAdapter::DirectMaskPredicate,
-            mask_encoding: MaskEncoding::RegisterOrImmediate,
-        });
-        record.expected_ptx = InstructionPattern::new(
-            "vote",
-            &["sync", recipe.ptx_mode, recipe.ptx_type],
-            vec![
-                OperandPattern::Register,
-                OperandPattern::Register,
-                OperandPattern::RegisterOrImmediate,
-            ],
-        );
-        record.summary = "warp vote".into();
-        record
-    }
-
-    fn vote_declaration(mode: VoteMode) -> ImportedIntrinsic {
-        let recipe = vote_recipe(mode);
-        let selection = |source_record: &str| ImportedSelection {
-            source_record: source_record.into(),
-            asm: format!(
-                "vote.sync.{}.{} \t$dest, $pred, $mask;",
-                recipe.ptx_mode, recipe.ptx_type
-            ),
-            predicates: vec![
-                "Subtarget->getPTXVersion() >= 60".into(),
-                "Subtarget->getSmVersion() >= 30".into(),
-            ],
-            constraints: Default::default(),
-        };
-        ImportedIntrinsic {
-            source_record: recipe.source_record.into(),
-            llvm_name: recipe.llvm_symbol.into(),
-            arguments: vec!["i32".into(), "i1".into()],
-            results: vec![recipe.llvm_result.into()],
-            classes: vec![
-                "ClangBuiltin".into(),
-                "NVVMBuiltin".into(),
-                "SDPatternOperator".into(),
-                "Intrinsic".into(),
-            ],
-            properties: vec![
-                "IntrConvergent".into(),
-                "IntrInaccessibleMemOnly".into(),
-                "IntrNoCallback".into(),
-            ],
-            selections: vec![
-                selection(recipe.immediate_selection),
-                selection(recipe.register_selection),
-            ],
-        }
-    }
-
-    fn warp_shuffle_policy(
-        mode: WarpShuffleMode,
-        value_kind: WarpShuffleValueKind,
-    ) -> OverlayIntrinsic {
-        let recipe = warp_shuffle_recipe(mode, value_kind);
-        let mut record = policy();
-        record.id = recipe.id.into();
-        record.abi_id = recipe.abi_id.into();
-        record.operation_key = recipe.operation_key.into();
-        record.family = "warp_shuffle".into();
-        match recipe.source {
-            WarpShuffleRecipeSource::LlvmImported {
-                source_record,
-                llvm_symbol,
-            } => {
-                record.source_record = Some(source_record.into());
-                record.llvm_symbol = Some(llvm_symbol.into());
-                record.llvm_arguments = vec![
-                    "i32".into(),
-                    recipe.dialect_value.into(),
-                    "i32".into(),
-                    "i32".into(),
-                ];
-                record.llvm_results = vec![recipe.dialect_value.into()];
-            }
-            WarpShuffleRecipeSource::PtxNative { instruction } => {
-                record.source = Some(IntrinsicSource::PtxNative {
-                    instruction: instruction.into(),
-                });
-                record.source_record = None;
-                record.llvm_symbol = None;
-                record.llvm_arguments.clear();
-                record.llvm_results.clear();
-            }
-        }
-        record.rust_module = "warp".into();
-        record.rust_name = recipe.rust_name.into();
-        record.rust_arguments = vec!["u32".into(), recipe.rust_value.into(), "u32".into()];
-        record.rust_result = recipe.rust_value.into();
-        record.safe = false;
-        record.must_use = true;
-        record.safe_allowlist_reason = None;
-        record.public_rust_path = format!("cuda_intrinsics::warp::{}", recipe.rust_name);
-        record.compatibility_rust_paths = vec![format!("cuda_device::warp::{}", recipe.rust_name)];
-        record.dialect_op_type = recipe.dialect_op_type.into();
-        record.dialect_op_name = recipe.dialect_op_name.into();
-        record.dialect_operands = vec!["i32".into(), recipe.dialect_value.into(), "i32".into()];
-        record.dialect_results = vec![recipe.dialect_value.into()];
-        record.pure = false;
-        record.memory = "inaccessible_read_write".into();
-        record.convergent = true;
-        record.execution_scope = "warp".into();
-        record.minimum_ptx = "6.0".into();
-        record.minimum_sm = Some("sm_30".into());
-        record.ptx_result = recipe.rust_value.into();
-        record.targets = "all".into();
-        record.ptx_isa_section =
-            "9.7.9.6 Data Movement and Conversion Instructions: shfl.sync".into();
-        record.ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-shfl-sync".into();
-        record.lowering = recipe.lowering.into();
-        record.backend_lowerings = vec![
-            crate::model::OverlayBackendLowering {
-                backend: IntrinsicBackend::LlvmNvptx,
-                mechanism: recipe.backend_mechanism,
-                evidence_profile: "llvm-test".into(),
-                targets: None,
-                minimum_ptx: Some("6.0".into()),
-                minimum_sm: Some("sm_30".into()),
-            },
-            crate::model::OverlayBackendLowering {
-                backend: IntrinsicBackend::LibNvvm,
-                mechanism: recipe.backend_mechanism,
-                evidence_profile: "libnvvm-test".into(),
-                targets: None,
-                minimum_ptx: Some("6.0".into()),
-                minimum_sm: Some("sm_75".into()),
-            },
-        ];
-        record.warp_shuffle = Some(crate::model::WarpShuffle {
-            mode,
-            value_kind,
-            participation:
-                WarpShuffleParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
-            legacy_pre_sm70: PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive,
-            source_lane: WarpShuffleSourceLane::InRangeSourceActiveAndNamedOutOfRangeCopiesSelf,
-            adapter: recipe.adapter,
-            clamp: recipe.clamp,
-            lane_encoding: recipe.operand_encoding,
-            mask_encoding: recipe.operand_encoding,
-        });
-        let operands = match recipe.adapter {
-            WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp => vec![
-                OperandPattern::Register,
-                OperandPattern::Register,
-                OperandPattern::RegisterOrImmediate,
-                OperandPattern::Exact {
-                    value: recipe.clamp.to_string(),
-                },
-                OperandPattern::RegisterOrImmediate,
-            ],
-            WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble => {
-                vec![
-                    OperandPattern::Exact { value: "lo".into() },
-                    OperandPattern::Exact { value: "lo".into() },
-                    OperandPattern::Register,
-                    OperandPattern::Exact {
-                        value: recipe.clamp.to_string(),
-                    },
-                    OperandPattern::Register,
-                ]
-            }
-        };
-        record.expected_ptx =
-            InstructionPattern::new("shfl", &["sync", recipe.ptx_mode, "b32"], operands);
-        record.summary = "synchronized warp shuffle".into();
-        record
-    }
-
-    fn warp_shuffle_declaration(
-        mode: WarpShuffleMode,
-        value_kind: WarpShuffleValueKind,
-    ) -> ImportedIntrinsic {
-        let recipe = warp_shuffle_recipe(mode, value_kind);
-        let WarpShuffleRecipeSource::LlvmImported {
-            source_record,
-            llvm_symbol,
-        } = recipe.source
-        else {
-            panic!("PTX-native i64 shuffles have no imported declaration");
-        };
-        let selections = (0..8)
-            .map(|index| ImportedSelection {
-                source_record: format!("anonymous_test_{index}"),
-                asm: format!(
-                    "shfl.sync.{}.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    recipe.ptx_mode
-                ),
-                predicates: vec![
-                    "Subtarget->getPTXVersion() >= 60".into(),
-                    "Subtarget->getSmVersion() >= 30".into(),
-                ],
-                constraints: Default::default(),
-            })
-            .collect();
-        ImportedIntrinsic {
-            source_record: source_record.into(),
-            llvm_name: llvm_symbol.into(),
-            arguments: vec![
-                "i32".into(),
-                recipe.dialect_value.into(),
-                "i32".into(),
-                "i32".into(),
-            ],
-            results: vec![recipe.dialect_value.into()],
-            classes: vec![
-                "ClangBuiltin".into(),
-                "NVVMBuiltin".into(),
-                "SDPatternOperator".into(),
-                "Intrinsic".into(),
-            ],
-            properties: vec![
-                "IntrConvergent".into(),
-                "IntrInaccessibleMemOnly".into(),
-                "IntrNoCallback".into(),
-            ],
-            selections,
-        }
-    }
-
-    fn sync_evidence(policy: &OverlayIntrinsic) -> EvidenceRecord {
-        let mut record = evidence();
-        record.id = policy.id.clone();
-        record.source_record = policy.source_record.clone();
-        record.llvm_symbol = policy.llvm_symbol.clone();
-        record.llvm_arguments = policy.llvm_arguments.clone();
-        record.llvm_results = policy.llvm_results.clone();
-        record.expected_ptx = policy.expected_ptx.clone();
-        record
-    }
-
-    fn dot_product_policy(
-        operation: DotProductOperation,
-        signedness: DotProductSignedness,
-    ) -> OverlayIntrinsic {
-        let recipe = dot_product_recipe(operation, signedness);
-        let mut record = policy();
-        record.id = recipe.id.into();
-        record.abi_id = match (operation, signedness) {
-            (DotProductOperation::Dp4a, DotProductSignedness::Signed) => "i0030",
-            (DotProductOperation::Dp4a, DotProductSignedness::Unsigned) => "i0031",
-            (DotProductOperation::Dp2a, DotProductSignedness::Signed) => "i0032",
-            (DotProductOperation::Dp2a, DotProductSignedness::Unsigned) => "i0033",
-        }
-        .into();
-        record.operation_key = recipe.operation_key.into();
-        record.family = "dotprod".into();
-        record.source = None;
-        record.source_record = Some(recipe.source_record.into());
-        record.rust_module = "dotprod".into();
-        record.rust_name = recipe.rust_name.into();
-        record.rust_arguments = vec!["u32".into(), "u32".into(), recipe.rust_value.into()];
-        record.rust_result = recipe.rust_value.into();
-        record.safe = true;
-        record.must_use = false;
-        record.safe_allowlist_reason = Some(
-            "per-thread integer arithmetic has no memory, pointer, or participation obligations"
-                .into(),
-        );
-        record.public_rust_path = format!("cuda_intrinsics::dotprod::{}", recipe.rust_name);
-        record.compatibility_rust_paths =
-            vec![format!("cuda_device::dotprod::{}", recipe.rust_name)];
-        record.dialect_op_type = recipe.dialect_op_type.into();
-        record.dialect_op_name = recipe.dialect_op_name.into();
-        record.dialect_operands = vec!["i32".into(), "i32".into(), "i32".into()];
-        record.dialect_results = vec!["i32".into()];
-        record.llvm_symbol = Some(recipe.llvm_symbol.into());
-        record.resolved_llvm_symbol = None;
-        record.llvm_arguments = recipe
-            .llvm_arguments
-            .iter()
-            .map(|argument| (*argument).into())
-            .collect();
-        record.llvm_results = vec!["i32".into()];
-        record.pure = true;
-        record.memory = "none".into();
-        record.convergent = false;
-        record.execution_scope = "thread".into();
-        record.minimum_ptx = "5.0".into();
-        record.minimum_sm = Some("sm_61".into());
-        record.ptx_result = recipe.rust_value.into();
-        record.targets = "all".into();
-        record.lowering = "generated_dotprod".into();
-        record.backend_lowerings = vec![
-            crate::model::OverlayBackendLowering {
-                backend: IntrinsicBackend::LlvmNvptx,
-                mechanism: BackendLoweringMechanism::TypedNvvm,
-                evidence_profile: "llvm-test".into(),
-                targets: None,
-                minimum_ptx: None,
-                minimum_sm: None,
-            },
-            crate::model::OverlayBackendLowering {
-                backend: IntrinsicBackend::LibNvvm,
-                mechanism: BackendLoweringMechanism::InlinePtx,
-                evidence_profile: "libnvvm-test".into(),
-                targets: None,
-                minimum_ptx: None,
-                minimum_sm: Some("sm_75".into()),
-            },
-        ];
-        record.dot_product = Some(crate::model::DotProduct {
-            operation,
-            signedness,
-            adapter: recipe.adapter,
-        });
-        record.expected_ptx = InstructionPattern::new(
-            recipe.ptx_mnemonic,
-            recipe.ptx_modifiers,
-            vec![OperandPattern::Register; 4],
-        );
-        record.summary = "packed integer dot product".into();
-        record
-    }
-
-    fn dot_product_declaration(
-        operation: DotProductOperation,
-        signedness: DotProductSignedness,
-    ) -> ImportedIntrinsic {
-        let recipe = dot_product_recipe(operation, signedness);
-        let selection = |source_record: &str, half: Option<(&str, i64)>| ImportedSelection {
-            source_record: source_record.into(),
-            asm: format!(
-                "{}.{} $dst, $a, $b, $c;",
-                recipe.ptx_mnemonic,
-                match half {
-                    Some((name, _)) => {
-                        let types = &recipe.ptx_modifiers[1..];
-                        format!("{name}.{}", types.join("."))
-                    }
-                    None => recipe.ptx_modifiers.join("."),
-                }
-            ),
-            predicates: vec!["hasDotInstructions".into()],
-            constraints: crate::model::ImportedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: half
-                    .map(|(_, value)| {
-                        vec![crate::model::ImportedImmediateBinding {
-                            argument_index: 2,
-                            value,
-                        }]
-                    })
-                    .unwrap_or_default(),
-            },
-        };
-        let selections = match operation {
-            DotProductOperation::Dp4a => vec![selection("DOT4", None)],
-            DotProductOperation::Dp2a => vec![
-                selection("DOT2_hi", Some(("hi", -1))),
-                selection("DOT2_lo", Some(("lo", 0))),
-            ],
-        };
-        ImportedIntrinsic {
-            source_record: recipe.source_record.into(),
-            llvm_name: recipe.llvm_symbol.into(),
-            arguments: recipe
-                .llvm_arguments
-                .iter()
-                .map(|argument| (*argument).into())
-                .collect(),
-            results: vec!["i32".into()],
-            classes: vec!["NVVMPureIntrinsic".into()],
-            properties: recipe
-                .llvm_properties
-                .iter()
-                .map(|property| (*property).into())
-                .collect(),
-            selections,
-        }
-    }
-
-    fn dot_product_evidence(policy: &OverlayIntrinsic) -> EvidenceRecord {
-        let mut record = evidence();
-        record.id = policy.id.clone();
-        record.source_record = policy.source_record.clone();
-        record.llvm_symbol = policy.llvm_symbol.clone();
-        record.llvm_arguments = policy.llvm_arguments.clone();
-        record.llvm_results = policy.llvm_results.clone();
-        record.concrete_llvm_arguments = policy.llvm_arguments.clone();
-        record.concrete_llvm_results = policy.llvm_results.clone();
-        record.declaration_attributes_canonicalized = Some(true);
-        record.gpu_target = "sm_61".into();
-        record.ptx_feature = "+ptx50".into();
-        record.expected_ptx = policy.expected_ptx.clone();
-        record
-    }
-
-    fn validate_ptx_native_policy(policy: &OverlayIntrinsic) -> Result<()> {
-        let source = resolve_policy_source(policy)?;
-        validate_policy(policy, &source, None, 1)
-    }
-
-    fn ledger_entry(record: &OverlayIntrinsic) -> AbiLedgerEntry {
-        AbiLedgerEntry {
-            abi_id: record.abi_id.clone(),
-            status: "active".into(),
-            catalog_id: record.id.clone(),
-            operation_key: record.operation_key.clone(),
-            raw_rust_signature: raw_rust_signature(record),
-        }
-    }
-
-    fn ledger(entries: Vec<AbiLedgerEntry>) -> AbiLedgerFile {
-        AbiLedgerFile {
-            schema: 1,
-            intrinsic_abi: 1,
-            entries,
-        }
-    }
-
-    #[test]
-    fn duplicate_values_are_rejected() {
-        let mut values = BTreeSet::new();
-        insert_unique(&mut values, "thread_idx_x", "catalog ID").unwrap();
-        let error = insert_unique(&mut values, "thread_idx_x", "catalog ID").unwrap_err();
-        assert!(error.to_string().contains("duplicate catalog ID"));
-    }
-
-    #[test]
-    fn legacy_evidence_schema_is_unchanged_and_rejects_matrix_fields() {
-        let legacy = EvidenceFile {
-            schema: 5,
-            backend_profile: "legacy".into(),
-            backend_kind: None,
-            llvm_revision: "test".into(),
-            backend_version: "LLVM legacy test".into(),
-            backend_sha256: "0123456789abcdef".into(),
-            artifact_path: None,
-            build_id_prefix: None,
-            nvvm_ir_version: None,
-            debug_ir_version: None,
-            records: vec![evidence()],
-        };
-        let bytes = serde_json::to_vec(&legacy).unwrap();
-        assert_eq!(parse_evidence_bytes(&bytes, "legacy").unwrap(), legacy);
-
-        let mut with_matrix_field = serde_json::to_value(&legacy).unwrap();
-        with_matrix_field["matrices"] = serde_json::json!([]);
-        let error = parse_synthetic_evidence(&with_matrix_field).unwrap_err();
-        assert!(error.to_string().contains("legacy evidence"));
-        assert!(format!("{error:#}").contains("unknown field"));
-    }
-
-    #[test]
-    fn compact_evidence_matrix_equals_explicit_records() {
-        let expanded = parse_synthetic_evidence(&synthetic_matrix_json()).unwrap();
-        let mut expected = vec![EvidenceRecord {
-            id: "synthetic_explicit".into(),
-            source: None,
-            source_record: Some("int_synthetic_explicit".into()),
-            llvm_symbol: Some("llvm.synthetic.explicit".into()),
-            resolved_llvm_symbol: None,
-            llvm_arguments: vec!["i32".into()],
-            llvm_results: vec!["i32".into()],
-            concrete_llvm_arguments: vec![],
-            concrete_llvm_results: vec![],
-            target_triple: "nvptx64-nvidia-cuda".into(),
-            gpu_target: "sm_80".into(),
-            ptx_feature: "+ptx71".into(),
-            status: "lowered".into(),
-            stages: vec![],
-            declaration_attributes_canonicalized: None,
-            runtime_validation: None,
-            expected_ptx: InstructionPattern {
-                mnemonic: "mma".into(),
-                modifiers: vec!["sync".into(), "explicit".into()],
-                operands: vec![OperandPattern::Register],
-            },
-        }];
-        expected.extend(["s8", "u8"].into_iter().map(|element| EvidenceRecord {
-            id: format!("synthetic_{element}"),
-            source: None,
-            source_record: Some(format!("int_synthetic_{element}")),
-            llvm_symbol: Some(format!("llvm.synthetic.{element}")),
-            resolved_llvm_symbol: None,
-            llvm_arguments: vec!["i32".into()],
-            llvm_results: vec!["i32".into()],
-            concrete_llvm_arguments: vec![],
-            concrete_llvm_results: vec![],
-            target_triple: "nvptx64-nvidia-cuda".into(),
-            gpu_target: "sm_80".into(),
-            ptx_feature: "+ptx71".into(),
-            status: "lowered".into(),
-            stages: vec![shared_matrix_stage()],
-            declaration_attributes_canonicalized: None,
-            runtime_validation: None,
-            expected_ptx: InstructionPattern {
-                mnemonic: "mma".into(),
-                modifiers: vec!["sync".into(), element.into()],
-                operands: vec![OperandPattern::Register],
-            },
-        }));
-        assert_eq!(expanded.schema, 6);
-        assert_eq!(expanded.records, expected);
-    }
-
-    #[test]
-    fn matrix_identity_mutations_reach_existing_evidence_validation() {
-        let mut expanded = parse_synthetic_evidence(&policy_matrix_json()).unwrap();
-        let record = expanded.records.pop().unwrap();
-        validate_test_evidence(&policy(), record.clone()).unwrap();
-
-        let mut wrong_source = record.clone();
-        wrong_source.source_record = Some("int_nvvm_read_ptx_sreg_tid_y".into());
-        assert!(
-            validate_test_evidence(&policy(), wrong_source)
-                .unwrap_err()
-                .to_string()
-                .contains("source provenance mismatch")
-        );
-
-        let mut wrong_symbol = record.clone();
-        wrong_symbol.llvm_symbol = Some("llvm.nvvm.read.ptx.sreg.tid.y".into());
-        assert!(
-            validate_test_evidence(&policy(), wrong_symbol)
-                .unwrap_err()
-                .to_string()
-                .contains("signature mismatch")
-        );
-
-        let mut wrong_signature = record.clone();
-        wrong_signature.llvm_arguments.push("i32".into());
-        assert!(
-            validate_test_evidence(&policy(), wrong_signature)
-                .unwrap_err()
-                .to_string()
-                .contains("signature mismatch")
-        );
-
-        let mut wrong_ptx = record;
-        wrong_ptx.expected_ptx.modifiers.push("changed".into());
-        assert!(
-            validate_test_evidence(&policy(), wrong_ptx)
-                .unwrap_err()
-                .to_string()
-                .contains("PTX expectation mismatch")
-        );
-    }
-
-    #[test]
-    fn evidence_matrix_rejects_bad_counts_fixtures_placeholders_and_collisions() {
-        let base = synthetic_matrix_json();
-
-        let mut bad_product = base.clone();
-        bad_product["matrices"][0]["product_count"] = 3.into();
-        assert_synthetic_evidence_error(&bad_product, "expands to 2 records");
-
-        let mut unknown_fixture = base.clone();
-        unknown_fixture["matrices"][0]["fixtures"][0] = "missing".into();
-        assert_synthetic_evidence_error(&unknown_fixture, "unknown fixture");
-
-        let mut uncovered_fixture = base.clone();
-        let extra = uncovered_fixture["fixtures"][0].clone();
-        uncovered_fixture["fixtures"]
-            .as_array_mut()
-            .unwrap()
-            .push(extra);
-        uncovered_fixture["fixtures"][1]["id"] = "unused".into();
-        assert_synthetic_evidence_error(&uncovered_fixture, "not referenced");
-
-        let mut wrong_coverage = base.clone();
-        wrong_coverage["fixtures"][0]["coverage_count"] = 1.into();
-        assert_synthetic_evidence_error(&wrong_coverage, "covers 2 expanded records");
-
-        let mut malformed = base.clone();
-        malformed["matrices"][0]["template"]["id"] = "synthetic_$element".into();
-        assert_synthetic_evidence_error(&malformed, "malformed matrix placeholder");
-
-        let mut unknown_axis = base.clone();
-        unknown_axis["matrices"][0]["template"]["id"] = "synthetic_${other}".into();
-        assert_synthetic_evidence_error(&unknown_axis, "unknown matrix axis");
-
-        let mut collision = base.clone();
-        collision["matrices"][0]["template"]["id"] = "synthetic".into();
-        assert_synthetic_evidence_error(&collision, "duplicate expanded evidence ID");
-    }
-
-    #[test]
-    fn exact_operand_matrix_placeholders_fail_closed() {
-        let base = policy_matrix_json();
-
-        let mut unknown = base.clone();
-        unknown["matrices"][0]["template"]["expected_ptx"]["operands"][1]["value"] =
-            "%tid.${other}".into();
-        assert_synthetic_evidence_error(&unknown, "unknown matrix axis other");
-
-        let mut unterminated = base.clone();
-        unterminated["matrices"][0]["template"]["expected_ptx"]["operands"][1]["value"] =
-            "%tid.${axis".into();
-        assert_synthetic_evidence_error(&unterminated, "unterminated matrix placeholder");
-
-        let mut disallowed = base;
-        disallowed["matrices"][0]["template"]["expected_ptx"]["mnemonic"] = "mov.${axis}".into();
-        assert_synthetic_evidence_error(&disallowed, "PTX mnemonic cannot contain");
-    }
-
-    #[test]
-    fn evidence_matrix_rejects_bad_axes_fixture_ids_and_stage_conflicts() {
-        let base = synthetic_matrix_json();
-
-        let mut no_fixture = base.clone();
-        no_fixture["matrices"][0]["fixtures"] = serde_json::json!([]);
-        assert_synthetic_evidence_error(&no_fixture, "references no shared fixture");
-
-        let mut empty_axes = base.clone();
-        empty_axes["matrices"][0]["axes"] = serde_json::json!([]);
-        assert_synthetic_evidence_error(&empty_axes, "has no axes");
-
-        let mut duplicate_axis = base.clone();
-        let axis = duplicate_axis["matrices"][0]["axes"][0].clone();
-        duplicate_axis["matrices"][0]["axes"]
-            .as_array_mut()
-            .unwrap()
-            .push(axis);
-        duplicate_axis["matrices"][0]["product_count"] = 4.into();
-        assert_synthetic_evidence_error(&duplicate_axis, "axes must be unique and sorted");
-
-        let mut empty_values = base.clone();
-        empty_values["matrices"][0]["axes"][0]["values"] = serde_json::json!([]);
-        assert_synthetic_evidence_error(&empty_values, "has no values");
-
-        let mut empty_axis_name = base.clone();
-        empty_axis_name["matrices"][0]["axes"][0]["name"] = "".into();
-        assert_synthetic_evidence_error(&empty_axis_name, "is not a safe token");
-
-        let mut empty_value = base.clone();
-        empty_value["matrices"][0]["axes"][0]["values"][0] = "".into();
-        assert_synthetic_evidence_error(&empty_value, "unsafe value");
-
-        let mut duplicate_value = base.clone();
-        duplicate_value["matrices"][0]["axes"][0]["values"][1] = "s8".into();
-        assert_synthetic_evidence_error(&duplicate_value, "duplicate value");
-
-        let mut unsafe_value = base.clone();
-        unsafe_value["matrices"][0]["axes"][0]["values"][0] = "../s8".into();
-        assert_synthetic_evidence_error(&unsafe_value, "unsafe value");
-
-        let mut unused_axis = base.clone();
-        unused_axis["matrices"][0]["axes"]
-            .as_array_mut()
-            .unwrap()
-            .push(serde_json::json!({"name": "other", "values": ["x"]}));
-        assert_synthetic_evidence_error(&unused_axis, "unused axis");
-
-        let mut duplicate_fixture = base.clone();
-        let fixture = duplicate_fixture["fixtures"][0].clone();
-        duplicate_fixture["fixtures"]
-            .as_array_mut()
-            .unwrap()
-            .push(fixture);
-        assert_synthetic_evidence_error(&duplicate_fixture, "duplicate evidence fixture ID");
-
-        let mut fixture_placeholder = base.clone();
-        fixture_placeholder["fixtures"][0]["stages"][0]["detail"] = "covers ${element}".into();
-        assert_synthetic_evidence_error(&fixture_placeholder, "cannot contain matrix placeholders");
-
-        let mut missing_symbol = base.clone();
-        missing_symbol["matrices"][0]["template"]
-            .as_object_mut()
-            .unwrap()
-            .remove("llvm_symbol");
-        assert_synthetic_evidence_error(&missing_symbol, "missing field `llvm_symbol`");
-
-        let mut conflicting_stage = base;
-        conflicting_stage["matrices"][0]["template"]["facts"]["stages"] =
-            conflicting_stage["fixtures"][0]["stages"].clone();
-        assert_synthetic_evidence_error(&conflicting_stage, "conflicting duplicate");
-    }
-
-    #[test]
-    fn overloaded_symbols_require_distinct_resolved_identities() {
-        let bf16 = packed_alu_policy(PackedAluFormat::Bf16x2, PackedAluOperation::Abs);
-        let f16 = packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Abs);
-        validate_unique_overlay(&[bf16.clone(), f16.clone()], 1).unwrap();
-
-        let mut unresolved = f16.clone();
-        unresolved.resolved_llvm_symbol = None;
-        let error = validate_unique_overlay(&[bf16.clone(), unresolved], 1).unwrap_err();
-        assert!(error.to_string().contains("without a resolved symbol"));
-
-        let mut duplicate = f16;
-        duplicate.resolved_llvm_symbol = bf16.resolved_llvm_symbol.clone();
-        let error = validate_unique_overlay(&[bf16, duplicate], 1).unwrap_err();
-        assert!(error.to_string().contains("duplicate resolved LLVM symbol"));
-    }
-
-    #[test]
-    fn overlay_manifest_loads_sorted_family_shards() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (overlay, hash) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        assert_eq!(overlay.schema, OVERLAY_SCHEMA);
-        assert_eq!(overlay.shards.len(), 64);
-        assert_eq!(overlay.intrinsics.len(), 1016);
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "scalar_arithmetic")
-                .count(),
-            64
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "scalar_conversion")
-                .count(),
-            10
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "prmt")
-                .count(),
-            7
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "debug_control")
-                .count(),
-            3
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "stmatrix")
-                .count(),
-            4
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "packed_alu")
-                .count(),
-            30
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "packed_conversion")
-                .count(),
-            18
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "active_mask")
-                .count(),
-            1
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "dotprod")
-                .count(),
-            4
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "ldmatrix")
-                .count(),
-            18
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "register_mma")
-                .count(),
-            154
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "sparse_mma")
-                .count(),
-            114
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "cp_async_copy")
-                .count(),
-            8
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "cp_async_control")
-                .count(),
-            3
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "cp_async_mbarrier")
-                .count(),
-            4
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "mbarrier_basic")
-                .count(),
-            4
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "cluster_memory")
-                .count(),
-            2
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "clc")
-                .count(),
-            6
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "sync")
-                .count(),
-            4
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "vote")
-                .count(),
-            4
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "warp_barrier")
-                .count(),
-            1
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "warp_match")
-                .count(),
-            4
-        );
-        assert_eq!(
-            overlay
-                .intrinsics
-                .iter()
-                .filter(|record| record.family == "warp_shuffle")
-                .count(),
-            12
-        );
-        assert_eq!(hash.len(), 64);
-
-        for invalid in [
-            "../outside.toml",
-            "/absolute.toml",
-            "other/family.toml",
-            "overlay/../outside.toml",
-            "overlay/not-toml.json",
-        ] {
-            assert!(validate_overlay_shard_path(invalid).is_err(), "{invalid}");
-        }
-    }
-
-    fn test_f8f6f4_admission() -> SparseMmaF8F6F4Admission {
-        let formats = vec![
-            SparseMmaElement::E2m1,
-            SparseMmaElement::E2m3,
-            SparseMmaElement::E3m2,
-            SparseMmaElement::E4m3,
-            SparseMmaElement::E5m2,
-        ];
-        SparseMmaF8F6F4Admission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            a_elements: formats.clone(),
-            b_elements: formats,
-            product_count: 25,
-        }
-    }
-
-    fn test_sparse_mma_f8f6f4_f16_admission() -> SparseMmaF8F6F4F16Admission {
-        SparseMmaF8F6F4F16Admission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            _legacy_first_abi_id: Some("i0525".into()),
-            a_elements: SPARSE_MMA_F8F6F4_ELEMENTS.into(),
-            b_elements: SPARSE_MMA_F8F6F4_ELEMENTS.into(),
-            product_count: 25,
-        }
-    }
-
-    fn test_register_mma_f8f6f4_admission(
-        _accumulator: RegisterMmaAccumulator,
-    ) -> RegisterMmaF8F6F4Admission {
-        let formats = REGISTER_MMA_F8F6F4_ELEMENTS.to_vec();
-        RegisterMmaF8F6F4Admission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            _legacy_first_abi_id: None,
-            a_elements: formats.clone(),
-            b_elements: formats,
-            product_count: 25,
-            targets: ["sm_120a", "sm_120f", "sm_121a", "sm_121f"]
-                .map(Into::into)
-                .into(),
-        }
-    }
-
-    fn test_register_mma_fp8_admission() -> RegisterMmaFp8Admission {
-        RegisterMmaFp8Admission {
-            llvm_evidence_profile: "llvm-fp8-test".into(),
-            libnvvm_evidence_profile: "libnvvm-fp8-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            _legacy_first_abi_id: Some("i0504".into()),
-            shapes: REGISTER_MMA_FP8_SHAPES.into(),
-            accumulators: REGISTER_MMA_FP8_ACCUMULATORS.into(),
-            a_elements: REGISTER_MMA_FP8_ELEMENTS.into(),
-            b_elements: REGISTER_MMA_FP8_ELEMENTS.into(),
-            product_count: 16,
-        }
-    }
-
-    fn test_register_mma_ampere_float_admission() -> RegisterMmaAmpereFloatAdmission {
-        RegisterMmaAmpereFloatAdmission {
-            llvm_evidence_profile: "llvm-ampere-float-test".into(),
-            libnvvm_evidence_profile: "libnvvm-ampere-float-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            _legacy_first_abi_id: Some("i0520".into()),
-            product_count: 5,
-            variants: REGISTER_MMA_AMPERE_FLOAT_VARIANTS.into(),
-        }
-    }
-
-    fn test_prmt_admission() -> PrmtAdmission {
-        let variants = [
-            PrmtMode::Generic,
-            PrmtMode::F4e,
-            PrmtMode::B4e,
-            PrmtMode::Rc8,
-            PrmtMode::Ecl,
-            PrmtMode::Ecr,
-            PrmtMode::Rc16,
-        ]
-        .map(|mode| crate::model::PrmtAdmissionVariant {
-            abi_id: prmt_recipe(mode).abi_id.into(),
-            mode,
-        })
-        .into();
-        PrmtAdmission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants,
-        }
-    }
-
-    fn test_fp8_conversion_admission() -> PackedConversionFp8Admission {
-        PackedConversionFp8Admission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            destination_formats: vec![
-                PackedConversionDestinationFormat::E4m3x2,
-                PackedConversionDestinationFormat::E5m2x2,
-            ],
-            saturations: vec![
-                PackedConversionSaturation::Satfinite,
-                PackedConversionSaturation::SatfiniteRelu,
-            ],
-            product_count: 4,
-        }
-    }
-
-    fn test_fp8_f16x2_conversion_admission() -> PackedConversionFp8F16x2Admission {
-        PackedConversionFp8F16x2Admission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            fp8_formats: vec![
-                PackedConversionFp8Format::E4m3x2,
-                PackedConversionFp8Format::E5m2x2,
-            ],
-            directions: vec![
-                PackedConversionFp8Direction::Pack,
-                PackedConversionFp8Direction::Unpack,
-            ],
-            relu_variants: true,
-            product_count: 8,
-        }
-    }
-
-    fn test_cluster_barrier_admission() -> ClusterBarrierAdmission {
-        let variants = [
-            ClusterBarrierMode::Arrive,
-            ClusterBarrierMode::ArriveAligned,
-            ClusterBarrierMode::ArriveRelaxed,
-            ClusterBarrierMode::ArriveRelaxedAligned,
-            ClusterBarrierMode::Wait,
-            ClusterBarrierMode::WaitAligned,
-        ]
-        .map(|mode| crate::model::ClusterBarrierAdmissionVariant {
-            abi_id: cluster_barrier_recipe(mode).abi_id.into(),
-            mode,
-        })
-        .into();
-        ClusterBarrierAdmission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants,
-        }
-    }
-
-    fn test_wgmma_control_admission() -> WgmmaControlAdmission {
-        let variants = [
-            WgmmaControlMode::Fence,
-            WgmmaControlMode::CommitGroup,
-            WgmmaControlMode::WaitGroup,
-        ]
-        .map(|mode| crate::model::WgmmaControlAdmissionVariant {
-            abi_id: wgmma_control_recipe(mode).abi_id.into(),
-            mode,
-        })
-        .into();
-        WgmmaControlAdmission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants,
-        }
-    }
-
-    fn test_special_register_admission() -> SpecialRegisterAdmission {
-        SpecialRegisterAdmission {
-            llvm_evidence_profile: "rust-llvm-22.1.2-1cb4e383".into(),
-            libnvvm_evidence_profile: "cuda-13.3-libnvvm-13.3.33".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            registers: REVIEWED_SPECIAL_REGISTERS.into(),
-            product_count: REVIEWED_SPECIAL_REGISTERS.len(),
-        }
-    }
-
-    fn test_debug_control_admission() -> DebugControlAdmission {
-        DebugControlAdmission {
-            llvm_evidence_profile: "llvm-debug-test".into(),
-            libnvvm_evidence_profile: "libnvvm-debug-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            operations: vec![
-                DebugControlOperation::Trap,
-                DebugControlOperation::Breakpoint,
-                DebugControlOperation::Pmevent,
-            ],
-            abi_ids: vec!["i9001".into(), "i9002".into(), "i9003".into()],
-        }
-    }
-
-    fn test_clc_admission() -> ClcAdmission {
-        let operations = [
-            ClcOperation::TryCancel,
-            ClcOperation::TryCancelMulticast,
-            ClcOperation::QueryIsCanceled,
-            ClcOperation::QueryGetFirstCtaidX,
-            ClcOperation::QueryGetFirstCtaidY,
-            ClcOperation::QueryGetFirstCtaidZ,
-        ];
-        ClcAdmission {
-            llvm_evidence_profile: "llvm-clc-test".into(),
-            libnvvm_evidence_profile: "libnvvm-clc-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants: operations
-                .into_iter()
-                .map(|operation| crate::model::ClcAdmissionVariant {
-                    abi_id: clc_recipe(operation).abi_id.into(),
-                    operation,
-                })
-                .collect(),
-        }
-    }
-
-    fn test_tma_admission() -> TmaAdmission {
-        TmaAdmission {
-            llvm_evidence_profile: "llvm-tma-test".into(),
-            libnvvm_evidence_profile: "libnvvm-tma-test".into(),
-            reduce_llvm_evidence_profile: Some("llvm-tma-reduce-test".into()),
-            reduce_libnvvm_evidence_profile: Some("libnvvm-tma-reduce-test".into()),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants: TMA_OPERATIONS
-                .into_iter()
-                .map(|operation| crate::model::TmaAdmissionVariant {
-                    abi_id: tma_recipe(operation).abi_id.into(),
-                    operation,
-                })
-                .collect(),
-            reduce_variants: tma_reduction_admission_variants(),
-        }
-    }
-
-    fn test_tcgen05_admission() -> Tcgen05Admission {
-        let operations = [
-            Tcgen05Operation::Alloc,
-            Tcgen05Operation::Dealloc,
-            Tcgen05Operation::RelinquishAllocPermit,
-            Tcgen05Operation::FenceBeforeThreadSync,
-            Tcgen05Operation::FenceAfterThreadSync,
-            Tcgen05Operation::Commit,
-            Tcgen05Operation::CommitSharedCluster,
-            Tcgen05Operation::MmaWsF16,
-            Tcgen05Operation::MmaF16,
-            Tcgen05Operation::MmaWsBf16,
-            Tcgen05Operation::MmaWsTf32,
-            Tcgen05Operation::CpSmemToTmem,
-            Tcgen05Operation::Ld16x256bX8Pure,
-            Tcgen05Operation::Ld16x256bPure,
-            Tcgen05Operation::LoadWait,
-            Tcgen05Operation::StoreWait,
-            Tcgen05Operation::AllocCg2,
-            Tcgen05Operation::DeallocCg2,
-            Tcgen05Operation::RelinquishAllocPermitCg2,
-            Tcgen05Operation::MmaF16Cg2,
-            Tcgen05Operation::CommitCg2,
-            Tcgen05Operation::CommitSharedClusterCg2,
-            Tcgen05Operation::CommitMulticastCg2,
-            Tcgen05Operation::CpSmemToTmemCg2,
-            Tcgen05Operation::CommitMulticast,
-            Tcgen05Operation::ShiftDown,
-            Tcgen05Operation::ShiftDownCg2,
-        ];
-        Tcgen05Admission {
-            llvm_evidence_profile: "llvm-tcgen05-test".into(),
-            libnvvm_evidence_profile: "libnvvm-tcgen05-test".into(),
-            cp_llvm_evidence_profile: None,
-            cp_libnvvm_evidence_profile: None,
-            ld_llvm_evidence_profile: None,
-            ld_libnvvm_evidence_profile: None,
-            st_llvm_evidence_profile: None,
-            st_libnvvm_evidence_profile: None,
-            offset_llvm_evidence_profile: None,
-            offset_libnvvm_evidence_profile: None,
-            control_llvm_evidence_profile: Some("llvm-tcgen05-control-test".into()),
-            control_libnvvm_evidence_profile: Some("libnvvm-tcgen05-control-test".into()),
-            mma_llvm_evidence_profile: None,
-            mma_libnvvm_evidence_profile: None,
-            mma_llvm_target_contracts: vec![],
-            mma_libnvvm_target_contracts: vec![],
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants: operations
-                .into_iter()
-                .map(|operation| crate::model::Tcgen05AdmissionVariant {
-                    abi_id: tcgen05_recipe(operation).abi_id.into(),
-                    operation,
-                })
-                .collect(),
-            cp_variants: vec![],
-            ld_variants: vec![],
-            st_variants: vec![],
-            ld_offset_variants: vec![],
-            st_offset_variants: vec![],
-            mma_variants: vec![],
-        }
-    }
-
-    fn without_tcgen05_control(mut admission: Tcgen05Admission) -> Tcgen05Admission {
-        admission.variants.truncate(24);
-        admission.control_llvm_evidence_profile = None;
-        admission.control_libnvvm_evidence_profile = None;
-        admission
-    }
-
-    fn test_tcgen05_cp_admission() -> Tcgen05Admission {
-        let mut admission = test_tcgen05_admission();
-        admission.cp_llvm_evidence_profile = Some("llvm-tcgen05-cp-test".into());
-        admission.cp_libnvvm_evidence_profile = Some("libnvvm-tcgen05-cp-test".into());
-        admission.cp_variants = TCGEN05_CP_MEMBERS
-            .into_iter()
-            .flat_map(|member| {
-                [Tcgen05CpGroup::Cg1, Tcgen05CpGroup::Cg2]
-                    .into_iter()
-                    .map(move |group| (member, group))
-            })
-            .enumerate()
-            .map(|(index, (member, group))| Tcgen05CpAdmissionVariant {
-                abi_id: format!("i{:04}", 578 + index),
-                member,
-                group,
-            })
-            .collect();
-        admission
-    }
-
-    fn test_tcgen05_ld_admission() -> Tcgen05Admission {
-        let mut admission = test_tcgen05_cp_admission();
-        admission.ld_llvm_evidence_profile = Some("llvm-tcgen05-ld-test".into());
-        admission.ld_libnvvm_evidence_profile = Some("libnvvm-tcgen05-ld-test".into());
-        admission.ld_variants = TCGEN05_LD_VARIANTS
-            .into_iter()
-            .flat_map(|(shape, multiplicity)| {
-                [false, true]
-                    .into_iter()
-                    .map(move |pack16| (shape, multiplicity, pack16))
-            })
-            .enumerate()
-            .map(
-                |(index, (shape, multiplicity, pack16))| Tcgen05LdAdmissionVariant {
-                    abi_id: format!("i{:04}", 612 + index),
-                    shape,
-                    multiplicity,
-                    pack16,
-                },
-            )
-            .collect();
-        admission
-    }
-
-    fn test_tcgen05_st_admission() -> Tcgen05Admission {
-        let mut admission = test_tcgen05_ld_admission();
-        admission.st_llvm_evidence_profile = Some("llvm-tcgen05-st-test".into());
-        admission.st_libnvvm_evidence_profile = Some("libnvvm-tcgen05-st-test".into());
-        admission.st_variants = TCGEN05_ST_VARIANTS
-            .into_iter()
-            .flat_map(|(shape, multiplicity)| {
-                [false, true]
-                    .into_iter()
-                    .map(move |unpack16| (shape, multiplicity, unpack16))
-            })
-            .enumerate()
-            .map(
-                |(index, (shape, multiplicity, unpack16))| Tcgen05StAdmissionVariant {
-                    abi_id: format!("i{:04}", 670 + index),
-                    shape,
-                    multiplicity,
-                    unpack16,
-                },
-            )
-            .collect();
-        admission
-    }
-
-    fn test_tcgen05_offset_admission() -> Tcgen05Admission {
-        let mut admission = test_tcgen05_st_admission();
-        admission.offset_llvm_evidence_profile = Some("llvm-tcgen05-offset-test".into());
-        admission.offset_libnvvm_evidence_profile = Some("libnvvm-tcgen05-offset-test".into());
-        admission.ld_offset_variants = TCGEN05_OFFSET_LDST_VARIANTS
-            .into_iter()
-            .flat_map(|(shape, multiplicity)| {
-                [false, true]
-                    .into_iter()
-                    .map(move |pack16| (shape, multiplicity, pack16))
-            })
-            .enumerate()
-            .map(
-                |(index, (shape, multiplicity, pack16))| Tcgen05LdAdmissionVariant {
-                    abi_id: format!("i{:04}", 728 + index),
-                    shape,
-                    multiplicity,
-                    pack16,
-                },
-            )
-            .collect();
-        admission.st_offset_variants = TCGEN05_OFFSET_LDST_VARIANTS
-            .into_iter()
-            .flat_map(|(shape, multiplicity)| {
-                [false, true]
-                    .into_iter()
-                    .map(move |unpack16| (shape, multiplicity, unpack16))
-            })
-            .enumerate()
-            .map(
-                |(index, (shape, multiplicity, unpack16))| Tcgen05StAdmissionVariant {
-                    abi_id: format!("i{:04}", 744 + index),
-                    shape,
-                    multiplicity,
-                    unpack16,
-                },
-            )
-            .collect();
-        admission
-    }
-
-    fn test_tcgen05_mma_admission() -> Tcgen05Admission {
-        let mut admission = test_tcgen05_admission();
-        admission.mma_llvm_evidence_profile = Some("llvm-tcgen05-mma-test".into());
-        admission.mma_libnvvm_evidence_profile = Some("libnvvm-tcgen05-mma-test".into());
-        admission.mma_llvm_target_contracts =
-            expected_tcgen05_mma_target_contracts(IntrinsicBackend::LlvmNvptx);
-        admission.mma_libnvvm_target_contracts =
-            expected_tcgen05_mma_target_contracts(IntrinsicBackend::LibNvvm);
-        admission.mma_variants = TCGEN05_MMA_FORMS
-            .into_iter()
-            .map(|form| (form, None))
-            .chain(
-                TCGEN05_MMA_ALIASES
-                    .into_iter()
-                    .map(|alias| (Tcgen05MmaForm::WsTensor, Some(alias))),
-            )
-            .enumerate()
-            .map(|(index, (form, alias))| Tcgen05MmaAdmissionVariant {
-                abi_id: format!("i{:04}", 763 + index),
-                form,
-                alias,
-            })
-            .chain(
-                TCGEN05_MMA_ALIASES
-                    .into_iter()
-                    .enumerate()
-                    .map(|(index, alias)| Tcgen05MmaAdmissionVariant {
-                        abi_id: format!("i{:04}", 1011 + index),
-                        form: Tcgen05MmaForm::Shared,
-                        alias: Some(alias),
-                    }),
-            )
-            .collect();
-        admission
-    }
-
-    fn assert_tcgen05_backend_target_split(record: &OverlayIntrinsic) {
-        let llvm = &record.backend_lowerings[0];
-        let libnvvm = &record.backend_lowerings[1];
-        assert_eq!(record.targets, TCGEN05_LLVM_TARGETS);
-        assert_eq!(llvm.backend, IntrinsicBackend::LlvmNvptx);
-        assert_eq!(llvm.targets, None);
-        assert_eq!(libnvvm.backend, IntrinsicBackend::LibNvvm);
-        assert_eq!(libnvvm.targets.as_deref(), Some(TCGEN05_LIBNVVM_TARGETS));
-        assert_eq!(
-            backend_target_requirement(record, llvm).unwrap().hardware,
-            CatalogHardwareTarget::AnyOf {
-                alternatives: vec![
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                ],
-            }
-        );
-        assert_eq!(
-            backend_target_requirement(record, libnvvm)
-                .unwrap()
-                .hardware,
-            CatalogHardwareTarget::AnyOf {
-                alternatives: vec![
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                ],
-            }
-        );
-    }
-
-    fn test_threadfence_admission() -> ThreadfenceAdmission {
-        ThreadfenceAdmission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants: vec![
-                crate::model::ThreadfenceAdmissionVariant {
-                    abi_id: "i0298".into(),
-                    scope: ThreadfenceScope::Cta,
-                },
-                crate::model::ThreadfenceAdmissionVariant {
-                    abi_id: "i0299".into(),
-                    scope: ThreadfenceScope::Device,
-                },
-                crate::model::ThreadfenceAdmissionVariant {
-                    abi_id: "i0300".into(),
-                    scope: ThreadfenceScope::System,
-                },
-            ],
-        }
-    }
-
-    fn test_cluster_memory_admission() -> ClusterMemoryAdmission {
-        ClusterMemoryAdmission {
-            llvm_evidence_profile: "llvm-cluster-memory-test".into(),
-            libnvvm_evidence_profile: "libnvvm-cluster-memory-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants: vec![
-                crate::model::ClusterMemoryAdmissionVariant {
-                    abi_id: "i0320".into(),
-                    operation: ClusterMemoryOperation::MapSharedRank,
-                },
-                crate::model::ClusterMemoryAdmissionVariant {
-                    abi_id: "i0321".into(),
-                    operation: ClusterMemoryOperation::ReadU32,
-                },
-            ],
-        }
-    }
-
-    fn test_stmatrix_admission() -> StmatrixAdmission {
-        let variants = [
-            (StmatrixMultiplicity::X2, StmatrixLayout::Normal, "i0301"),
-            (
-                StmatrixMultiplicity::X2,
-                StmatrixLayout::Transposed,
-                "i0302",
-            ),
-            (StmatrixMultiplicity::X4, StmatrixLayout::Normal, "i0303"),
-            (
-                StmatrixMultiplicity::X4,
-                StmatrixLayout::Transposed,
-                "i0304",
-            ),
-        ]
-        .map(
-            |(multiplicity, layout, abi_id)| crate::model::StmatrixAdmissionVariant {
-                abi_id: abi_id.into(),
-                multiplicity,
-                layout,
-            },
-        )
-        .into();
-        StmatrixAdmission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants,
-        }
-    }
-
-    fn test_mbarrier_extended_admission() -> MbarrierExtendedAdmission {
-        let variants = [
-            MbarrierExtendedOperation::ArriveExpectTxCta,
-            MbarrierExtendedOperation::ArriveExpectTxCluster,
-            MbarrierExtendedOperation::ArriveRemoteCluster,
-            MbarrierExtendedOperation::TryWaitTokenCta,
-            MbarrierExtendedOperation::TryWaitParityCta,
-            MbarrierExtendedOperation::TryWaitParityCluster,
-            MbarrierExtendedOperation::FenceProxyAsyncSharedCta,
-            MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster,
-            MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster,
-            MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster,
-            MbarrierExtendedOperation::Nanosleep,
-        ]
-        .map(|operation| crate::model::MbarrierExtendedAdmissionVariant {
-            abi_id: mbarrier_extended_recipe(operation).abi_id.into(),
-            operation,
-        })
-        .into();
-        MbarrierExtendedAdmission {
-            llvm_evidence_profile: "llvm-test".into(),
-            libnvvm_evidence_profile: "libnvvm-test".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants,
-        }
-    }
-
-    #[test]
-    fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() {
-        let shard = |schema, sparse_mma_f8f6f4_f32, prmt| OverlayShardFile {
-            schema,
-            family: "sparse_mma".into(),
-            intrinsics: vec![],
-            register_mma_int4: None,
-            register_mma_int8: None,
-            register_mma_b1: None,
-            register_mma_f8f6f4_f32: None,
-            register_mma_f8f6f4_f16: None,
-            register_mma_mxf8f6f4_f32: None,
-            register_mma_fp8: None,
-            register_mma_ampere_float: None,
-            sparse_mma_integer: None,
-            sparse_mma_f8f6f4_f32,
-            sparse_mma_f8f6f4_f16: None,
-            prmt,
-            packed_conversion_fp8: None,
-            packed_conversion_fp8_f16x2: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cluster_sreg: None,
-            cluster_barrier: None,
-            mbarrier_extended: None,
-            special_registers: None,
-            debug_control: None,
-            threadfence: None,
-            cluster_memory: None,
-            stmatrix: None,
-            clc: None,
-            wgmma_controls: None,
-            tma: None,
-            tcgen05: None,
-        };
-        let path = Path::new("intrinsics/overlay/test.toml");
-        validate_overlay_shard_schema(&shard(26, None, None), path).unwrap();
-        validate_overlay_shard_schema(&shard(27, None, None), path).unwrap();
-        validate_overlay_shard_schema(&shard(28, None, None), path).unwrap();
-        validate_overlay_shard_schema(&shard(29, None, None), path).unwrap();
-        validate_overlay_shard_schema(&shard(30, None, None), path).unwrap();
-        validate_overlay_shard_schema(&shard(31, None, None), path).unwrap();
-        validate_overlay_shard_schema(&shard(32, None, None), path).unwrap();
-        validate_overlay_shard_schema(&shard(33, None, None), path).unwrap();
-        validate_overlay_shard_schema(&shard(34, None, None), path).unwrap();
-        validate_overlay_shard_schema(&shard(35, None, None), path).unwrap();
-        validate_overlay_shard_schema(&shard(27, Some(test_f8f6f4_admission()), None), path)
-            .unwrap();
-        validate_overlay_shard_schema_with_max(
-            &shard(27, Some(test_f8f6f4_admission()), None),
-            path,
-            30,
-        )
-        .unwrap();
-        validate_overlay_shard_schema(&shard(28, None, Some(test_prmt_admission())), path).unwrap();
-        validate_overlay_shard_schema_with_max(
-            &shard(28, None, Some(test_prmt_admission())),
-            path,
-            30,
-        )
-        .unwrap();
-
-        assert!(validate_overlay_shard_schema(&shard(25, None, None), path).is_err());
-        for schema in 35..=OVERLAY_SHARD_SCHEMA {
-            validate_overlay_shard_schema(&shard(schema, None, None), path).unwrap();
-        }
-        assert!(
-            validate_overlay_shard_schema(&shard(OVERLAY_SHARD_SCHEMA + 1, None, None), path)
-                .is_err()
-        );
-        let error =
-            validate_overlay_shard_schema(&shard(26, Some(test_f8f6f4_admission()), None), path)
-                .unwrap_err();
-        assert!(
-            error
-                .to_string()
-                .contains("requires overlay shard schema 27")
-        );
-        let error =
-            validate_overlay_shard_schema(&shard(27, None, Some(test_prmt_admission())), path)
-                .unwrap_err();
-        assert!(
-            error
-                .to_string()
-                .contains("requires overlay shard schema 28")
-        );
-        let mut f16_mma = shard(REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA, None, None);
-        f16_mma.family = "register_mma".into();
-        f16_mma.register_mma_f8f6f4_f16 = Some(test_register_mma_f8f6f4_admission(
-            RegisterMmaAccumulator::F16,
-        ));
-        validate_overlay_shard_schema(&f16_mma, path).unwrap();
-        f16_mma.schema -= 1;
-        assert!(
-            validate_overlay_shard_schema(&f16_mma, path)
-                .unwrap_err()
-                .to_string()
-                .contains("requires overlay shard schema 47")
-        );
-
-        let mut sparse_f16_mma = shard(SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA, None, None);
-        sparse_f16_mma.sparse_mma_f8f6f4_f16 = Some(test_sparse_mma_f8f6f4_f16_admission());
-        validate_overlay_shard_schema(&sparse_f16_mma, path).unwrap();
-        sparse_f16_mma.schema -= 1;
-        assert!(
-            validate_overlay_shard_schema(&sparse_f16_mma, path)
-                .unwrap_err()
-                .to_string()
-                .contains("requires overlay shard schema 50")
-        );
-
-        let mut standard_fp8_mma = shard(REGISTER_MMA_FP8_SHARD_SCHEMA, None, None);
-        standard_fp8_mma.family = "register_mma".into();
-        standard_fp8_mma.register_mma_fp8 = Some(test_register_mma_fp8_admission());
-        validate_overlay_shard_schema(&standard_fp8_mma, path).unwrap();
-        standard_fp8_mma.schema -= 1;
-        assert!(
-            validate_overlay_shard_schema(&standard_fp8_mma, path)
-                .unwrap_err()
-                .to_string()
-                .contains("requires overlay shard schema 48")
-        );
-
-        let fp8_shard = |schema| OverlayShardFile {
-            schema,
-            family: "packed_conversion".into(),
-            intrinsics: vec![],
-            register_mma_int4: None,
-            register_mma_int8: None,
-            register_mma_b1: None,
-            register_mma_f8f6f4_f32: None,
-            register_mma_f8f6f4_f16: None,
-            register_mma_mxf8f6f4_f32: None,
-            register_mma_fp8: None,
-            register_mma_ampere_float: None,
-            sparse_mma_integer: None,
-            sparse_mma_f8f6f4_f32: None,
-            sparse_mma_f8f6f4_f16: None,
-            prmt: None,
-            packed_conversion_fp8: Some(test_fp8_conversion_admission()),
-            packed_conversion_fp8_f16x2: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cluster_sreg: None,
-            cluster_barrier: None,
-            mbarrier_extended: None,
-            special_registers: None,
-            debug_control: None,
-            threadfence: None,
-            cluster_memory: None,
-            stmatrix: None,
-            clc: None,
-            wgmma_controls: None,
-            tma: None,
-            tcgen05: None,
-        };
-        validate_overlay_shard_schema(&fp8_shard(29), path).unwrap();
-        validate_overlay_shard_schema_with_max(&fp8_shard(29), path, 30).unwrap();
-        let error = validate_overlay_shard_schema(&fp8_shard(28), path).unwrap_err();
-        assert!(
-            error
-                .to_string()
-                .contains("requires overlay shard schema 29")
-        );
-
-        let cluster_shard = OverlayShardFile {
-            schema: 31,
-            family: "cluster_barrier".into(),
-            intrinsics: vec![],
-            register_mma_int4: None,
-            register_mma_int8: None,
-            register_mma_b1: None,
-            register_mma_f8f6f4_f32: None,
-            register_mma_f8f6f4_f16: None,
-            register_mma_mxf8f6f4_f32: None,
-            register_mma_fp8: None,
-            register_mma_ampere_float: None,
-            sparse_mma_integer: None,
-            sparse_mma_f8f6f4_f32: None,
-            sparse_mma_f8f6f4_f16: None,
-            prmt: None,
-            packed_conversion_fp8: None,
-            packed_conversion_fp8_f16x2: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cluster_sreg: None,
-            cluster_barrier: Some(test_cluster_barrier_admission()),
-            mbarrier_extended: None,
-            special_registers: None,
-            debug_control: None,
-            threadfence: None,
-            cluster_memory: None,
-            stmatrix: None,
-            clc: None,
-            wgmma_controls: None,
-            tma: None,
-            tcgen05: None,
-        };
-        validate_overlay_shard_schema_with_max(&cluster_shard, path, 31).unwrap();
-        let mut old_cluster_shard = cluster_shard;
-        old_cluster_shard.schema = 30;
-        assert!(
-            validate_overlay_shard_schema_with_max(&old_cluster_shard, path, 31)
-                .unwrap_err()
-                .to_string()
-                .contains("requires overlay shard schema 31")
-        );
-
-        let extended_shard = OverlayShardFile {
-            schema: MBARRIER_EXTENDED_SHARD_SCHEMA,
-            family: "mbarrier_extended".into(),
-            intrinsics: vec![],
-            register_mma_int4: None,
-            register_mma_int8: None,
-            register_mma_b1: None,
-            register_mma_f8f6f4_f32: None,
-            register_mma_f8f6f4_f16: None,
-            register_mma_mxf8f6f4_f32: None,
-            register_mma_fp8: None,
-            register_mma_ampere_float: None,
-            sparse_mma_integer: None,
-            sparse_mma_f8f6f4_f32: None,
-            sparse_mma_f8f6f4_f16: None,
-            prmt: None,
-            packed_conversion_fp8: None,
-            packed_conversion_fp8_f16x2: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cluster_sreg: None,
-            cluster_barrier: None,
-            mbarrier_extended: Some(test_mbarrier_extended_admission()),
-            special_registers: None,
-            debug_control: None,
-            threadfence: None,
-            cluster_memory: None,
-            stmatrix: None,
-            clc: None,
-            wgmma_controls: None,
-            tma: None,
-            tcgen05: None,
-        };
-        validate_overlay_shard_schema_with_max(
-            &extended_shard,
-            path,
-            MBARRIER_EXTENDED_SHARD_SCHEMA,
-        )
-        .unwrap();
-        let mut old_extended_shard = extended_shard;
-        old_extended_shard.schema = MBARRIER_EXTENDED_SHARD_SCHEMA - 1;
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &old_extended_shard,
-                path,
-                MBARRIER_EXTENDED_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("requires overlay shard schema 40")
-        );
-    }
-
-    #[test]
-    fn stmatrix_admission_is_closed_and_uses_schema_35() {
-        let shard = |schema| {
-            toml::from_str::<OverlayShardFile>(&format!(
-                r#"
-schema = {schema}
-family = "stmatrix"
-
-[stmatrix]
-llvm_evidence_profile = "llvm-test"
-libnvvm_evidence_profile = "libnvvm-test"
-runtime_validation = "unexecuted"
-
-[[stmatrix.variant]]
-abi_id = "i0301"
-multiplicity = "x2"
-layout = "normal"
-
-[[stmatrix.variant]]
-abi_id = "i0302"
-multiplicity = "x2"
-layout = "transposed"
-
-[[stmatrix.variant]]
-abi_id = "i0303"
-multiplicity = "x4"
-layout = "normal"
-
-[[stmatrix.variant]]
-abi_id = "i0304"
-multiplicity = "x4"
-layout = "transposed"
-"#
-            ))
-            .unwrap()
-        };
-        let path = Path::new("intrinsics/overlay/stmatrix.toml");
-
-        let old = shard(STMATRIX_SHARD_SCHEMA - 1);
-        assert!(
-            validate_overlay_shard_schema(&old, path)
-                .unwrap_err()
-                .to_string()
-                .contains("requires overlay shard schema 35")
-        );
-
-        let current = shard(STMATRIX_SHARD_SCHEMA);
-        validate_overlay_shard_schema(&current, path).unwrap();
-        let admission = current.stmatrix.unwrap();
-        let records = expand_stmatrix_admission(&admission).unwrap();
-        assert_eq!(
-            records
-                .iter()
-                .map(|record| (record.abi_id.as_str(), record.id.as_str()))
-                .collect::<Vec<_>>(),
-            [
-                ("i0301", "stmatrix_m8n8_x2_b16"),
-                ("i0302", "stmatrix_m8n8_x2_trans_b16"),
-                ("i0303", "stmatrix_m8n8_x4_b16"),
-                ("i0304", "stmatrix_m8n8_x4_trans_b16"),
-            ]
-        );
-
-        let mut reordered = admission.clone();
-        reordered.variants.swap(0, 1);
-        assert!(expand_stmatrix_admission(&reordered).is_err());
-
-        let mut wrong_id = admission.clone();
-        wrong_id.variants[0].abi_id = "i0302".into();
-        assert!(expand_stmatrix_admission(&wrong_id).is_err());
-
-        let mut executed = admission;
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_stmatrix_admission(&executed).is_err());
-    }
-
-    #[test]
-    fn pinned_stmatrix_records_match_llvm_and_reject_contract_drift() {
-        let records = expand_stmatrix_admission(&test_stmatrix_admission()).unwrap();
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-
-        for record in &records {
-            let declaration = declarations[record.source_record.as_deref().unwrap()];
-            assert!(declaration.selections.is_empty());
-            validate_imported_policy(record, declaration).unwrap();
-        }
-
-        let declaration = declarations["int_nvvm_stmatrix_sync_aligned_m8n8_x2_b16"];
-        let mut changed = records[0].clone();
-        changed.memory = "read_write".into();
-        assert!(validate_imported_policy(&changed, declaration).is_err());
-
-        let mut changed = records[0].clone();
-        changed.convergent = false;
-        assert!(validate_imported_policy(&changed, declaration).is_err());
-
-        let mut changed = records[0].clone();
-        changed.backend_lowerings[0].mechanism = BackendLoweringMechanism::InlinePtx;
-        assert!(validate_imported_policy(&changed, declaration).is_err());
-
-        let mut changed = records[0].clone();
-        changed.minimum_sm = Some("sm_80".into());
-        assert!(validate_imported_policy(&changed, declaration).is_err());
-    }
-
-    #[test]
-    fn cluster_sreg_admission_uses_its_fixed_introduction_schema() {
-        let shard = |schema| {
-            toml::from_str::<OverlayShardFile>(&format!(
-                r#"
-schema = {schema}
-family = "sreg"
-
-[cluster_sreg]
-axes = ["x", "y", "z"]
-xyz_product_count = 12
-record_count = 14
-"#
-            ))
-            .unwrap()
-        };
-        let path = Path::new("intrinsics/overlay/sreg_cluster.toml");
-
-        let old = shard(CLUSTER_SREG_SHARD_SCHEMA - 1);
-        assert!(
-            validate_overlay_shard_schema(&old, path)
-                .unwrap_err()
-                .to_string()
-                .contains("requires overlay shard schema 30")
-        );
-
-        let current = shard(CLUSTER_SREG_SHARD_SCHEMA);
-        validate_overlay_shard_schema(&current, path).unwrap();
-        let admission = current.cluster_sreg.unwrap();
-        assert_eq!(expand_cluster_sreg_admission(&admission).unwrap().len(), 14);
-
-        let mut wrong_axes = admission.clone();
-        wrong_axes.axes.swap(0, 1);
-        assert!(expand_cluster_sreg_admission(&wrong_axes).is_err());
-
-        let mut wrong_count = admission;
-        wrong_count.record_count = 13;
-        assert!(expand_cluster_sreg_admission(&wrong_count).is_err());
-    }
-
-    #[test]
-    fn special_register_admission_is_closed_and_schema_gated() {
-        let admission = test_special_register_admission();
-        let records = expand_special_register_admission(&admission).unwrap();
-        assert_eq!(records.len(), 12);
-        assert_eq!(
-            records
-                .iter()
-                .map(|record| record.id.as_str())
-                .collect::<Vec<_>>(),
-            [
-                "clock",
-                "clock64",
-                "globaltimer",
-                "envreg1",
-                "envreg2",
-                "smid",
-                "nsmid",
-                "gridid",
-                "warpid",
-                "nwarpid",
-                "dynamic_smem_size",
-                "total_smem_size",
-            ]
-        );
-
-        let mut reordered = admission.clone();
-        reordered.registers.swap(0, 1);
-        assert!(expand_special_register_admission(&reordered).is_err());
-
-        let mut wrong_count = admission.clone();
-        wrong_count.product_count -= 1;
-        assert!(expand_special_register_admission(&wrong_count).is_err());
-
-        let mut executed = admission.clone();
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_special_register_admission(&executed).is_err());
-
-        let shard = |schema| OverlayShardFile {
-            schema,
-            family: "sreg".into(),
-            intrinsics: vec![],
-            register_mma_int4: None,
-            register_mma_int8: None,
-            register_mma_b1: None,
-            register_mma_f8f6f4_f32: None,
-            register_mma_f8f6f4_f16: None,
-            register_mma_mxf8f6f4_f32: None,
-            register_mma_fp8: None,
-            register_mma_ampere_float: None,
-            sparse_mma_integer: None,
-            sparse_mma_f8f6f4_f32: None,
-            sparse_mma_f8f6f4_f16: None,
-            prmt: None,
-            packed_conversion_fp8: None,
-            packed_conversion_fp8_f16x2: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cluster_sreg: None,
-            cluster_barrier: None,
-            mbarrier_extended: None,
-            special_registers: Some(admission.clone()),
-            debug_control: None,
-            threadfence: None,
-            cluster_memory: None,
-            stmatrix: None,
-            clc: None,
-            wgmma_controls: None,
-            tma: None,
-            tcgen05: None,
-        };
-        let path = Path::new("intrinsics/overlay/sreg_special.toml");
-        validate_overlay_shard_schema(&shard(SPECIAL_REGISTER_SHARD_SCHEMA), path).unwrap();
-        assert!(
-            validate_overlay_shard_schema(&shard(SPECIAL_REGISTER_SHARD_SCHEMA - 1), path)
-                .unwrap_err()
-                .to_string()
-                .contains("requires overlay shard schema 32")
-        );
-    }
-
-    #[test]
-    fn pinned_special_registers_preserve_apis_widths_and_backend_routes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let base = load_resolution_base(&repo_root).unwrap();
-        let declarations = index_imported_intrinsics(&base.imported).unwrap();
-        let records = base
-            .overlay
-            .intrinsics
-            .iter()
-            .filter(|record| record.special_register.is_some())
-            .collect::<Vec<_>>();
-        assert_eq!(records.len(), 12);
-        assert_eq!(
-            records
-                .iter()
-                .map(|record| record.abi_id.clone())
-                .collect::<BTreeSet<_>>(),
-            (283..=294)
-                .map(|id| format!("i{id:04}"))
-                .collect::<BTreeSet<_>>()
-        );
-
-        for record in &records {
-            let source = resolve_policy_source(record).unwrap();
-            let declaration = resolve_imported_declaration(record, &source, &declarations).unwrap();
-            validate_special_register_policy(record, &source, declaration).unwrap();
-            validate_special_register_llvm_exclusion(record, &declarations).unwrap();
-        }
-
-        for (id, section, anchor) in [
-            ("clock", "10.23", "special-registers-clock-clock-hi"),
-            ("clock64", "10.24", "special-registers-clock64"),
-            ("globaltimer", "10.28", "special-registers-globaltimer"),
-            ("envreg1", "10.27", "special-registers-envreg"),
-            ("envreg2", "10.27", "special-registers-envreg"),
-            ("smid", "10.8", "special-registers-smid"),
-            ("nsmid", "10.9", "special-registers-nsmid"),
-            ("gridid", "10.10", "special-registers-gridid"),
-            ("warpid", "10.4", "special-registers-warpid"),
-            ("nwarpid", "10.5", "special-registers-nwarpid"),
-            (
-                "dynamic_smem_size",
-                "10.32",
-                "special-registers-dynamic-smem-size",
-            ),
-            (
-                "total_smem_size",
-                "10.30",
-                "special-registers-total-smem-size",
-            ),
-        ] {
-            let record = records.iter().find(|record| record.id == id).unwrap();
-            assert!(record.ptx_isa_section.starts_with(section));
-            assert!(record.ptx_isa_url.ends_with(anchor));
-        }
-
-        let gridid = records.iter().find(|record| record.id == "gridid").unwrap();
-        assert_eq!(gridid.rust_result, "u64");
-        assert_eq!(gridid.dialect_results, ["i64"]);
-        assert!(matches!(
-            resolve_policy_source(gridid).unwrap(),
-            IntrinsicSource::PtxNative { .. }
-        ));
-        assert!(
-            gridid
-                .special_register
-                .as_ref()
-                .unwrap()
-                .llvm_exclusion
-                .is_some()
-        );
-
-        let clock = records.iter().find(|record| record.id == "clock").unwrap();
-        let source = resolve_policy_source(clock).unwrap();
-        let declaration = resolve_imported_declaration(clock, &source, &declarations)
-            .unwrap()
-            .unwrap();
-
-        let mut wrong_effects = (*clock).clone();
-        wrong_effects.memory = "none".into();
-        assert!(
-            validate_special_register_policy(&wrong_effects, &source, Some(declaration)).is_err()
-        );
-
-        let mut wrong_contract = (*clock).clone();
-        wrong_contract
-            .special_register
-            .as_mut()
-            .unwrap()
-            .output_constraint = SpecialRegisterOutputConstraint::Register64;
-        assert!(
-            validate_special_register_policy(&wrong_contract, &source, Some(declaration)).is_err()
-        );
-
-        let mut wrong_route = (*clock).clone();
-        wrong_route.backend_lowerings[0].mechanism = BackendLoweringMechanism::InlinePtx;
-        assert!(
-            validate_special_register_policy(&wrong_route, &source, Some(declaration)).is_err()
-        );
-    }
-
-    #[test]
-    fn special_register_evidence_validates_both_backend_routes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let policies =
-            expand_special_register_admission(&test_special_register_admission()).unwrap();
-        let mut evidence_files = vec![
-            read_evidence_file(
-                &repo_root
-                    .join("intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-special-registers.json"),
-            )
-            .unwrap(),
-            read_evidence_file(
-                &repo_root
-                    .join("intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-special-registers.json"),
-            )
-            .unwrap(),
-        ];
-        let llvm_revision = "1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e";
-        let indexed = index_evidence(&evidence_files, llvm_revision).unwrap();
-        for policy in &policies {
-            for lowering in &policy.backend_lowerings {
-                let evidence = indexed
-                    .get(&(lowering.evidence_profile.as_str(), policy.id.as_str()))
-                    .unwrap();
-                validate_evidence(policy, evidence, Some(lowering)).unwrap();
-            }
-        }
-
-        let libnvvm = evidence_files
-            .iter_mut()
-            .find(|file| file.backend_kind == Some(IntrinsicBackend::LibNvvm))
-            .unwrap();
-        libnvvm
-            .records
-            .iter_mut()
-            .find(|record| record.id == "gridid")
-            .unwrap()
-            .stages
-            .retain(|stage| stage.stage != EvidenceStageKind::DeviceLink);
-        let indexed = index_evidence(&evidence_files, llvm_revision).unwrap();
-        let policy = policies
-            .iter()
-            .find(|policy| policy.id == "gridid")
-            .unwrap();
-        let lowering = policy
-            .backend_lowerings
-            .iter()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
-            .unwrap();
-        let evidence = indexed
-            .get(&(lowering.evidence_profile.as_str(), policy.id.as_str()))
-            .unwrap();
-        assert!(validate_evidence(policy, evidence, Some(lowering)).is_err());
-    }
-
-    #[test]
-    fn threadfence_admission_is_closed_and_uses_schema_34() {
-        let shard = |schema| {
-            toml::from_str::<OverlayShardFile>(&format!(
-                r#"
-schema = {schema}
-family = "sync"
-
-[threadfence]
-llvm_evidence_profile = "llvm-test"
-libnvvm_evidence_profile = "libnvvm-test"
-runtime_validation = "unexecuted"
-
-[[threadfence.variant]]
-abi_id = "i0298"
-scope = "cta"
-
-[[threadfence.variant]]
-abi_id = "i0299"
-scope = "device"
-
-[[threadfence.variant]]
-abi_id = "i0300"
-scope = "system"
-"#
-            ))
-            .unwrap()
-        };
-        let path = Path::new("intrinsics/overlay/threadfence.toml");
-
-        let old = shard(THREADFENCE_SHARD_SCHEMA - 1);
-        assert!(
-            validate_overlay_shard_schema(&old, path)
-                .unwrap_err()
-                .to_string()
-                .contains("requires overlay shard schema 34")
-        );
-
-        let current = shard(THREADFENCE_SHARD_SCHEMA);
-        validate_overlay_shard_schema(&current, path).unwrap();
-        let admission = current.threadfence.unwrap();
-        let records = expand_threadfence_admission(&admission).unwrap();
-        assert_eq!(records.len(), 3);
-        assert_eq!(
-            records
-                .iter()
-                .map(|record| (record.abi_id.as_str(), record.id.as_str()))
-                .collect::<Vec<_>>(),
-            [
-                ("i0298", "threadfence_block"),
-                ("i0299", "threadfence"),
-                ("i0300", "threadfence_system"),
-            ]
-        );
-
-        let mut reordered = admission.clone();
-        reordered.variants.swap(0, 1);
-        assert!(expand_threadfence_admission(&reordered).is_err());
-
-        let mut wrong_id = admission.clone();
-        wrong_id.variants[0].abi_id = "i0300".into();
-        assert!(expand_threadfence_admission(&wrong_id).is_err());
-
-        let mut executed = admission.clone();
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_threadfence_admission(&executed).is_err());
-    }
-
-    #[test]
-    fn pinned_threadfences_match_llvm_and_reject_contract_drift() {
-        let records = expand_threadfence_admission(&test_threadfence_admission()).unwrap();
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-
-        for record in &records {
-            let declaration = declarations[record.source_record.as_deref().unwrap()];
-            validate_imported_policy(record, declaration).unwrap();
-            assert_eq!(
-                declaration
-                    .selections
-                    .iter()
-                    .filter(|selection| selection_matches_policy(record, selection).unwrap())
-                    .count(),
-                1
-            );
-        }
-
-        let declaration = declarations["int_nvvm_membar_cta"];
-        let mut changed = records[0].clone();
-        changed.memory = "none".into();
-        assert!(validate_imported_policy(&changed, declaration).is_err());
-
-        let mut changed = records[0].clone();
-        changed.convergent = true;
-        assert!(validate_imported_policy(&changed, declaration).is_err());
-
-        let mut changed = records[0].clone();
-        changed.backend_lowerings[0].mechanism = BackendLoweringMechanism::InlinePtx;
-        assert!(validate_imported_policy(&changed, declaration).is_err());
-
-        let mut changed = records[0].clone();
-        changed.minimum_ptx = "2.0".into();
-        assert!(validate_imported_policy(&changed, declaration).is_err());
-    }
-
-    #[test]
-    fn pinned_cluster_sregs_preserve_helpers_and_reject_unused_w_components() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (mut overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        bind_pinned_abi_ids(&repo_root, &mut overlay);
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-        let records = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| {
-                record
-                    .source_record
-                    .as_deref()
-                    .is_some_and(is_cluster_sreg_source)
-            })
-            .collect::<Vec<_>>();
-
-        assert_eq!(records.len(), 14);
-        let actual_abi_ids = records
-            .iter()
-            .map(|record| record.abi_id.clone())
-            .collect::<BTreeSet<_>>();
-        let expected_abi_ids = (263..=276)
-            .map(|id| format!("i{id:04}"))
-            .collect::<BTreeSet<_>>();
-        assert_eq!(actual_abi_ids, expected_abi_ids);
-        for record in &records {
-            let declaration = declarations[record.source_record.as_deref().unwrap()];
-            validate_imported_policy(record, declaration).unwrap();
-            assert!(!declaration.source_record.ends_with("_w"));
-        }
-
-        let compatibility_paths = records
-            .iter()
-            .flat_map(|record| record.compatibility_rust_paths.iter().map(String::as_str))
-            .collect::<BTreeSet<_>>();
-        assert_eq!(
-            compatibility_paths,
-            [
-                "cuda_device::cluster::cluster_ctaidX",
-                "cuda_device::cluster::cluster_ctaidY",
-                "cuda_device::cluster::cluster_ctaidZ",
-                "cuda_device::cluster::cluster_nctaidX",
-                "cuda_device::cluster::cluster_nctaidY",
-                "cuda_device::cluster::cluster_nctaidZ",
-                "cuda_device::cluster::__cluster_grid_dimX",
-                "cuda_device::cluster::__cluster_grid_dimY",
-                "cuda_device::cluster::__cluster_grid_dimZ",
-                "cuda_device::cluster::__cluster_idxX",
-                "cuda_device::cluster::__cluster_idxY",
-                "cuda_device::cluster::__cluster_idxZ",
-            ]
-            .into_iter()
-            .collect()
-        );
-
-        let source = resolve_policy_source(records[0]).unwrap();
-        let error = validate_sreg_policy(
-            records[0],
-            &source,
-            Some(declarations["int_nvvm_read_ptx_sreg_cluster_ctaid_w"]),
-        )
-        .unwrap_err();
-        assert!(error.to_string().contains("unused always-zero"));
-
-        let mut mixed = (*records[0]).clone();
-        mixed.sparse_mma = overlay
-            .intrinsics
-            .iter()
-            .find_map(|record| record.sparse_mma.clone());
-        let source = resolve_policy_source(&mixed).unwrap();
-        let error = validate_sreg_policy(
-            &mixed,
-            &source,
-            Some(declarations[mixed.source_record.as_deref().unwrap()]),
-        )
-        .unwrap_err();
-        assert!(error.to_string().contains("mixes another generated-family"));
-    }
-
-    #[test]
-    fn compact_f8f6f4_axes_require_the_exact_canonical_matrix() {
-        let records = expand_sparse_mma_f8f6f4_admission(&test_f8f6f4_admission()).unwrap();
-        assert_eq!(records.len(), 25);
-        assert_eq!(
-            records[0].id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
-        );
-        assert_eq!(records[0].rust_arguments[0], "[f32; 4]");
-        assert_eq!(records[0].dialect_results, ["f32"; 4]);
-        assert_eq!(records[0].llvm_results, ["f32"; 4]);
-
-        let mut missing = test_f8f6f4_admission();
-        missing.a_elements.pop();
-        assert!(expand_sparse_mma_f8f6f4_admission(&missing).is_err());
-
-        let mut duplicate = test_f8f6f4_admission();
-        duplicate.a_elements[4] = SparseMmaElement::E4m3;
-        assert!(expand_sparse_mma_f8f6f4_admission(&duplicate).is_err());
-
-        let mut extra = test_f8f6f4_admission();
-        extra.b_elements.push(SparseMmaElement::S4);
-        assert!(expand_sparse_mma_f8f6f4_admission(&extra).is_err());
-
-        let mut unsorted = test_f8f6f4_admission();
-        unsorted.b_elements.swap(0, 1);
-        assert!(expand_sparse_mma_f8f6f4_admission(&unsorted).is_err());
-
-        let mut wrong_count = test_f8f6f4_admission();
-        wrong_count.product_count = 24;
-        assert!(expand_sparse_mma_f8f6f4_admission(&wrong_count).is_err());
-    }
-
-    #[test]
-    fn compact_sparse_f8f6f4_f16_admission_is_closed_and_ordered() {
-        let admission = test_sparse_mma_f8f6f4_f16_admission();
-        let records = expand_sparse_mma_f8f6f4_f16_admission(&admission).unwrap();
-        assert_eq!(records.len(), 25);
-        assert!(records.iter().all(|record| record.abi_id.is_empty()));
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let mut bound = overlay_file(records.clone());
-        bind_pinned_abi_ids(&repo_root, &mut bound);
-        assert_eq!(
-            bound
-                .intrinsics
-                .iter()
-                .map(|record| record.abi_id.clone())
-                .collect::<Vec<_>>(),
-            (525..=549)
-                .map(|id| format!("i{id:04}"))
-                .collect::<Vec<_>>()
-        );
-        assert_eq!(
-            records[0].id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
-        );
-        assert_eq!(
-            records[24].id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
-        );
-        let first = &records[0];
-        assert_eq!(
-            first.source_record.as_deref(),
-            Some("int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e2m1_f16")
-        );
-        assert_eq!(
-            first.llvm_symbol.as_deref(),
-            Some(
-                "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e2m1.f16"
-            )
-        );
-        assert_eq!(
-            first.rust_arguments,
-            ["[u32; 2]", "[u32; 4]", "[u32; 4]", "u32", "u32"]
-        );
-        assert_eq!(first.rust_result, "[u32; 2]");
-        assert_eq!(first.dialect_results, ["i32"; 2]);
-        assert_eq!(first.llvm_results, ["v2f16"; 2]);
-        assert_eq!(
-            first.llvm_arguments,
-            [
-                "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "v2f16", "v2f16", "i32",
-                "i32"
-            ]
-        );
-        assert_eq!(first.minimum_ptx, "8.7");
-        assert_eq!(first.minimum_sm, None);
-        assert_eq!(first.targets, SPARSE_MMA_F8F6F4_TARGETS);
-        assert!(first.convergent && !first.pure);
-        assert!(first.backend_lowerings.iter().all(|route| {
-            route.mechanism == BackendLoweringMechanism::InlinePtx
-                && route.minimum_ptx.as_deref() == Some("8.7")
-                && route.minimum_sm.is_none()
-        }));
-        let mma = first.sparse_mma.as_ref().unwrap();
-        assert_eq!(mma.accumulator, SparseMmaAccumulator::F16);
-        assert_eq!(mma.selector, SparseMmaSelector::ImmediateZero);
-        assert_eq!(
-            mma.adapter,
-            SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32
-        );
-        assert_eq!(
-            mma.llvm_adapter,
-            SparseMmaLlvmAdapter::A4I32B4I32C2V2F16MetadataI32SelectorI32ToD2V2F16
-        );
-        assert_eq!(
-            first.compatibility_rust_paths,
-            ["cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"]
-        );
-        assert_eq!(
-            first.expected_ptx.operands,
-            [
-                OperandPattern::RegisterList { length: 2 },
-                OperandPattern::RegisterList { length: 4 },
-                OperandPattern::RegisterList { length: 4 },
-                OperandPattern::RegisterList { length: 2 },
-                OperandPattern::Register,
-                OperandPattern::Immediate,
-            ]
-        );
-
-        let mut missing = admission.clone();
-        missing.a_elements.pop();
-        assert!(expand_sparse_mma_f8f6f4_f16_admission(&missing).is_err());
-
-        let mut reordered = admission.clone();
-        reordered.b_elements.swap(0, 1);
-        assert!(expand_sparse_mma_f8f6f4_f16_admission(&reordered).is_err());
-
-        let mut wrong_count = admission.clone();
-        wrong_count.product_count = 24;
-        assert!(expand_sparse_mma_f8f6f4_f16_admission(&wrong_count).is_err());
-
-        let mut legacy_first_id = admission.clone();
-        legacy_first_id._legacy_first_abi_id = Some("i9999".into());
-        assert!(
-            expand_sparse_mma_f8f6f4_f16_admission(&legacy_first_id)
-                .unwrap()
-                .iter()
-                .all(|record| record.abi_id.is_empty())
-        );
-
-        let mut missing_evidence = admission.clone();
-        missing_evidence.llvm_evidence_profile.clear();
-        assert!(expand_sparse_mma_f8f6f4_f16_admission(&missing_evidence).is_err());
-
-        let mut executed = admission;
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_sparse_mma_f8f6f4_f16_admission(&executed).is_err());
-    }
-
-    #[test]
-    fn sparse_f8f6f4_f16_candidate_floor_uses_the_resolved_policy() {
-        let policy =
-            expand_sparse_mma_f8f6f4_f16_admission(&test_sparse_mma_f8f6f4_f16_admission())
-                .unwrap()
-                .remove(0);
-        let (_, requirement) = candidate_llvm_route(&policy).unwrap();
-
-        validate_candidate_target(&policy, &requirement, "sm_120a", "+ptx87").unwrap();
-        validate_candidate_target(&policy, &requirement, "sm_120f", "+ptx88").unwrap();
-        validate_candidate_target(&policy, &requirement, "sm_121a", "+ptx88").unwrap();
-        validate_candidate_target(&policy, &requirement, "sm_121f", "+ptx88").unwrap();
-        for target in ["sm_120f", "sm_121a", "sm_121f"] {
-            assert!(
-                validate_candidate_target(&policy, &requirement, target, "+ptx87").is_err(),
-                "{target} must require PTX 8.8"
-            );
-        }
-    }
-
-    #[test]
-    fn compact_dense_f8f6f4_admission_is_closed() {
-        for (accumulator, first, first_id, last_id, rust_arguments, rust_result, adapter) in [
-            (
-                RegisterMmaAccumulator::F32,
-                454,
-                "mma_m16n8k32_f32_e2m1_e2m1",
-                "mma_m16n8k32_f32_e5m2_e5m2",
-                ["[f32; 4]", "[u32; 4]", "[u32; 2]"],
-                "[f32; 4]",
-                RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32,
-            ),
-            (
-                RegisterMmaAccumulator::F16,
-                479,
-                "mma_m16n8k32_f16_e2m1_e2m1",
-                "mma_m16n8k32_f16_e5m2_e5m2",
-                ["[u32; 2]", "[u32; 4]", "[u32; 2]"],
-                "[u32; 2]",
-                RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32,
-            ),
-        ] {
-            let admission = test_register_mma_f8f6f4_admission(accumulator);
-            let records = expand_register_mma_f8f6f4_admission(&admission, accumulator).unwrap();
-            assert_eq!(records.len(), 25);
-            assert!(records.iter().all(|record| record.abi_id.is_empty()));
-            let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-            let mut bound = overlay_file(records.clone());
-            bind_pinned_abi_ids(&repo_root, &mut bound);
-            assert_eq!(
-                bound
-                    .intrinsics
-                    .iter()
-                    .map(|record| record.abi_id.clone())
-                    .collect::<Vec<_>>(),
-                (first..first + 25)
-                    .map(|id| format!("i{id:04}"))
-                    .collect::<Vec<_>>()
-            );
-            assert_eq!(records[0].id, first_id);
-            assert_eq!(records[24].id, last_id);
-            assert!(records.iter().all(|record| {
-                record.rust_arguments == rust_arguments
-                    && record.rust_result == rust_result
-                    && record.register_mma.as_ref().unwrap().adapter == adapter
-                    && record.targets == REGISTER_MMA_F8F6F4_TARGETS
-                    && record.minimum_ptx == "8.7"
-                    && record.minimum_sm.is_none()
-                    && record.backend_lowerings.len() == 2
-                    && record
-                        .backend_lowerings
-                        .iter()
-                        .all(|route| route.mechanism == BackendLoweringMechanism::InlinePtx)
-            }));
-
-            let mut missing = admission.clone();
-            missing.a_elements.pop();
-            assert!(expand_register_mma_f8f6f4_admission(&missing, accumulator).is_err());
-
-            let mut reordered = admission.clone();
-            reordered.b_elements.swap(0, 1);
-            assert!(expand_register_mma_f8f6f4_admission(&reordered, accumulator).is_err());
-
-            let mut wrong_count = admission.clone();
-            wrong_count.product_count = 24;
-            assert!(expand_register_mma_f8f6f4_admission(&wrong_count, accumulator).is_err());
-
-            let mut legacy_first_id = admission.clone();
-            legacy_first_id._legacy_first_abi_id = Some("i9999".into());
-            assert!(
-                expand_register_mma_f8f6f4_admission(&legacy_first_id, accumulator)
-                    .unwrap()
-                    .iter()
-                    .all(|record| record.abi_id.is_empty())
-            );
-
-            let mut reordered_targets = admission.clone();
-            reordered_targets.targets.swap(0, 1);
-            assert!(expand_register_mma_f8f6f4_admission(&reordered_targets, accumulator).is_err());
-
-            let mut missing_evidence = admission.clone();
-            missing_evidence.llvm_evidence_profile.clear();
-            assert!(expand_register_mma_f8f6f4_admission(&missing_evidence, accumulator).is_err());
-
-            let mut executed = admission;
-            executed.runtime_validation = RuntimeValidation::Executed;
-            assert!(expand_register_mma_f8f6f4_admission(&executed, accumulator).is_err());
-        }
-
-        let admission = test_register_mma_f8f6f4_admission(RegisterMmaAccumulator::F32);
-        assert!(
-            expand_register_mma_f8f6f4_admission(&admission, RegisterMmaAccumulator::F64).is_err()
-        );
-    }
-
-    #[test]
-    fn compact_standard_fp8_admission_is_closed_and_ordered() {
-        let admission = test_register_mma_fp8_admission();
-        let records = expand_register_mma_fp8_admission(&admission).unwrap();
-        assert_eq!(records.len(), 16);
-        assert!(records.iter().all(|record| record.abi_id.is_empty()));
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let mut bound = overlay_file(records.clone());
-        bind_pinned_abi_ids(&repo_root, &mut bound);
-        assert_eq!(
-            bound
-                .intrinsics
-                .iter()
-                .map(|record| record.abi_id.clone())
-                .collect::<Vec<_>>(),
-            (504..=519)
-                .map(|id| format!("i{id:04}"))
-                .collect::<Vec<_>>()
-        );
-
-        let mut index = 0;
-        for &shape in &REGISTER_MMA_FP8_SHAPES {
-            let (shape_name, a_count, b_count) = register_mma_fp8_shape_contract(shape).unwrap();
-            for &accumulator in &REGISTER_MMA_FP8_ACCUMULATORS {
-                let (scalar, arguments, result, adapter, result_count) = match accumulator {
-                    RegisterMmaAccumulator::F16 => (
-                        "f16",
-                        vec![
-                            "[u32; 2]".to_owned(),
-                            format!("[u32; {a_count}]"),
-                            if b_count == 1 {
-                                "u32".to_owned()
-                            } else {
-                                "[u32; 2]".to_owned()
-                            },
-                        ],
-                        "[u32; 2]",
-                        if shape == RegisterMmaShape::M16n8k16 {
-                            RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32
-                        } else {
-                            RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32
-                        },
-                        2,
-                    ),
-                    RegisterMmaAccumulator::F32 => (
-                        "f32",
-                        vec![
-                            "[f32; 4]".to_owned(),
-                            format!("[u32; {a_count}]"),
-                            if b_count == 1 {
-                                "u32".to_owned()
-                            } else {
-                                "[u32; 2]".to_owned()
-                            },
-                        ],
-                        "[f32; 4]",
-                        if shape == RegisterMmaShape::M16n8k16 {
-                            RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
-                        } else {
-                            RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32
-                        },
-                        4,
-                    ),
-                    _ => unreachable!(),
-                };
-                for &a_element in &REGISTER_MMA_FP8_ELEMENTS {
-                    for &b_element in &REGISTER_MMA_FP8_ELEMENTS {
-                        let record = &records[index];
-                        let a = register_mma_fp8_element_name(a_element).unwrap();
-                        let b = register_mma_fp8_element_name(b_element).unwrap();
-                        assert_eq!(record.id, format!("mma_{shape_name}_fp8_{scalar}_{a}_{b}"));
-                        assert_eq!(
-                            record.operation_key,
-                            format!(
-                                "matrix.mma.{shape_name}.row.col.standard_fp8.{scalar}.{a}.{b}.{scalar}"
-                            )
-                        );
-                        assert_eq!(
-                            record.source_record.as_deref(),
-                            Some(
-                                format!(
-                                    "int_nvvm_mma_{shape_name}_row_col_{scalar}_{a}_{b}_{scalar}"
-                                )
-                                .as_str()
-                            )
-                        );
-                        assert_eq!(record.rust_arguments, arguments);
-                        assert_eq!(record.rust_result, result);
-                        assert_eq!(
-                            record.minimum_ptx,
-                            register_mma_fp8_minimum_ptx(shape, accumulator)
-                        );
-                        assert_eq!(record.minimum_sm.as_deref(), Some("sm_89"));
-                        assert_eq!(
-                            record.expected_ptx.operands,
-                            [result_count, a_count, b_count, result_count]
-                                .map(|length| OperandPattern::RegisterList { length })
-                        );
-                        let mma = record.register_mma.as_ref().unwrap();
-                        assert_eq!(mma.kind, Some(RegisterMmaKind::Standard));
-                        assert_eq!(mma.adapter, adapter);
-                        index += 1;
-                    }
-                }
-            }
-        }
-        assert_eq!(index, records.len());
-
-        let mut reordered = admission.clone();
-        reordered.shapes.swap(0, 1);
-        assert!(expand_register_mma_fp8_admission(&reordered).is_err());
-        let mut reordered = admission.clone();
-        reordered.accumulators.swap(0, 1);
-        assert!(expand_register_mma_fp8_admission(&reordered).is_err());
-        let mut reordered = admission.clone();
-        reordered.a_elements.swap(0, 1);
-        assert!(expand_register_mma_fp8_admission(&reordered).is_err());
-        let mut reordered = admission.clone();
-        reordered.b_elements.swap(0, 1);
-        assert!(expand_register_mma_fp8_admission(&reordered).is_err());
-        let mut wrong = admission.clone();
-        wrong.product_count = 15;
-        assert!(expand_register_mma_fp8_admission(&wrong).is_err());
-        let mut legacy_first_id = admission.clone();
-        legacy_first_id._legacy_first_abi_id = Some("i9999".into());
-        assert!(
-            expand_register_mma_fp8_admission(&legacy_first_id)
-                .unwrap()
-                .iter()
-                .all(|record| record.abi_id.is_empty())
-        );
-        let mut wrong = admission;
-        wrong.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_register_mma_fp8_admission(&wrong).is_err());
-    }
-
-    #[test]
-    fn compact_ampere_float_mma_admission_is_closed_and_ordered() {
-        let admission = test_register_mma_ampere_float_admission();
-        let records = expand_register_mma_ampere_float_admission(&admission).unwrap();
-        assert_eq!(records.len(), 5);
-        assert!(records.iter().all(|record| record.abi_id.is_empty()));
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let mut bound = overlay_file(records.clone());
-        bind_pinned_abi_ids(&repo_root, &mut bound);
-        assert_eq!(
-            bound
-                .intrinsics
-                .iter()
-                .map(|record| (record.abi_id.as_str(), record.id.as_str()))
-                .collect::<Vec<_>>(),
-            [
-                ("i0520", "mma_m16n8k4_f32_tf32"),
-                ("i0521", "mma_m16n8k8_f16_f16"),
-                ("i0522", "mma_m16n8k8_f32_bf16"),
-                ("i0523", "mma_m16n8k8_f32_f16"),
-                ("i0524", "mma_m16n8k16_f16_f16"),
-            ]
-        );
-        for record in &records {
-            assert_eq!(record.minimum_ptx, "7.0");
-            assert_eq!(record.minimum_sm.as_deref(), Some("sm_80"));
-            assert_eq!(record.backend_lowerings.len(), 2);
-            assert!(record.backend_lowerings.iter().all(|lowering| {
-                lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    && lowering.minimum_ptx.as_deref() == Some("7.0")
-                    && lowering.minimum_sm.as_deref() == Some("sm_80")
-            }));
-            let mma = record.register_mma.as_ref().unwrap();
-            assert_eq!(mma.kind, None);
-            assert_eq!(
-                mma.compatibility_source,
-                RegisterMmaCompatibilitySource::GeneratedStub
-            );
-        }
-
-        let mut reordered = admission.clone();
-        reordered.variants.swap(0, 1);
-        assert!(expand_register_mma_ampere_float_admission(&reordered).is_err());
-        let mut legacy_first_id = admission.clone();
-        legacy_first_id._legacy_first_abi_id = Some("i9999".into());
-        assert!(
-            expand_register_mma_ampere_float_admission(&legacy_first_id)
-                .unwrap()
-                .iter()
-                .all(|record| record.abi_id.is_empty())
-        );
-        let mut wrong = admission.clone();
-        wrong.product_count = 4;
-        assert!(expand_register_mma_ampere_float_admission(&wrong).is_err());
-        let mut wrong = admission.clone();
-        wrong.llvm_evidence_profile.clear();
-        assert!(expand_register_mma_ampere_float_admission(&wrong).is_err());
-        let mut wrong = admission;
-        wrong.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_register_mma_ampere_float_admission(&wrong).is_err());
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let path = repo_root.join("intrinsics/overlay/register_mma_ampere_float.toml");
-        let bytes = fs::read(&path).unwrap();
-        let mut shard: OverlayShardFile = toml::from_slice(&bytes).unwrap();
-        validate_overlay_shard_schema(&shard, &path).unwrap();
-        shard.schema = REGISTER_MMA_AMPERE_FLOAT_SHARD_SCHEMA - 1;
-        assert!(
-            validate_overlay_shard_schema(&shard, &path)
-                .unwrap_err()
-                .to_string()
-                .contains("requires overlay shard schema 49")
-        );
-    }
-
-    #[test]
-    fn ampere_float_mma_policies_match_llvm_and_fail_closed() {
-        let records =
-            expand_register_mma_ampere_float_admission(&test_register_mma_ampere_float_admission())
-                .unwrap();
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let mut overlay = overlay_file(records);
-        bind_pinned_abi_ids(&repo_root, &mut overlay);
-        let records = overlay.intrinsics;
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-
-        for record in &records {
-            let declaration = declarations[record.source_record.as_deref().unwrap()];
-            validate_imported_policy(record, declaration).unwrap();
-            let expected_predicates = match record.id.as_str() {
-                "mma_m16n8k4_f32_tf32" | "mma_m16n8k16_f16_f16" => [
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ],
-                _ => [
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75",
-                ],
-            };
-            assert_eq!(declaration.selections[0].predicates, expected_predicates);
-            assert_eq!(record.minimum_ptx, "7.0");
-            assert_eq!(record.minimum_sm.as_deref(), Some("sm_80"));
-        }
-
-        let valid = &records[2];
-        assert_eq!(valid.id, "mma_m16n8k8_f32_bf16");
-        assert_eq!(
-            declarations[valid.source_record.as_deref().unwrap()].selections[0].predicates,
-            [
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ]
-        );
-        assert_eq!(valid.minimum_ptx, "7.0");
-        assert_eq!(valid.minimum_sm.as_deref(), Some("sm_80"));
-        assert!(valid.backend_lowerings.iter().all(|lowering| {
-            lowering.minimum_ptx.as_deref() == Some("7.0")
-                && lowering.minimum_sm.as_deref() == Some("sm_80")
-        }));
-        let declaration = declarations[valid.source_record.as_deref().unwrap()];
-        let mut wrong = valid.clone();
-        wrong.minimum_ptx = "6.5".into();
-        assert!(validate_imported_policy(&wrong, declaration).is_err());
-        let mut wrong = valid.clone();
-        wrong.register_mma.as_mut().unwrap().adapter = RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32;
-        assert!(validate_imported_policy(&wrong, declaration).is_err());
-        let mut wrong = valid.clone();
-        wrong.register_mma.as_mut().unwrap().kind = Some(RegisterMmaKind::Standard);
-        assert!(validate_imported_policy(&wrong, declaration).is_err());
-        let mut wrong_declaration = declaration.clone();
-        wrong_declaration.selections[0].predicates[0] = "Subtarget->getPTXVersion() >= 70".into();
-        assert!(validate_imported_policy(valid, &wrong_declaration).is_err());
-    }
-
-    #[test]
-    fn standard_fp8_policies_match_llvm_and_fail_closed() {
-        let records =
-            expand_register_mma_fp8_admission(&test_register_mma_fp8_admission()).unwrap();
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let mut overlay = overlay_file(records);
-        bind_pinned_abi_ids(&repo_root, &mut overlay);
-        let records = overlay.intrinsics;
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-
-        for record in &records {
-            let declaration = declarations[record.source_record.as_deref().unwrap()];
-            validate_imported_policy(record, declaration).unwrap();
-            let mma = record.register_mma.as_ref().unwrap();
-            let source_floor = declaration.selections[0]
-                .predicates
-                .iter()
-                .find(|predicate| predicate.contains("getPTXVersion"))
-                .unwrap();
-            if mma.shape == RegisterMmaShape::M16n8k32 {
-                assert!(source_floor.ends_with(">= 84"));
-                if mma.accumulator == RegisterMmaAccumulator::F16 {
-                    assert_eq!(record.minimum_ptx, "8.7");
-                } else {
-                    assert_eq!(record.minimum_ptx, "8.4");
-                }
-            } else {
-                assert!(source_floor.ends_with(">= 87"));
-                assert_eq!(record.minimum_ptx, "8.7");
-            }
-        }
-
-        let valid = &records[0];
-        let declaration = declarations[valid.source_record.as_deref().unwrap()];
-        let mut wrong = valid.clone();
-        wrong.register_mma.as_mut().unwrap().kind = None;
-        assert!(validate_imported_policy(&wrong, declaration).is_err());
-        let mut wrong = valid.clone();
-        wrong.register_mma.as_mut().unwrap().adapter = RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32;
-        assert!(validate_imported_policy(&wrong, declaration).is_err());
-        let mut wrong_declaration = declaration.clone();
-        wrong_declaration.selections[0].predicates[1] = "Subtarget->getPTXVersion() >= 84".into();
-        assert!(validate_imported_policy(valid, &wrong_declaration).is_err());
-        let mut wrong = valid.clone();
-        wrong.minimum_ptx = "8.4".into();
-        assert!(validate_imported_policy(&wrong, declaration).is_err());
-
-        let mut old = expand_register_mma_f8f6f4_admission(
-            &test_register_mma_f8f6f4_admission(RegisterMmaAccumulator::F32),
-            RegisterMmaAccumulator::F32,
-        )
-        .unwrap()
-        .remove(18);
-        let mut standard = records[12].clone();
-        assert_ne!(old.id, standard.id);
-        standard.id = old.id.clone();
-        assert!(validate_unique_overlay(&[old.clone(), standard], 1).is_err());
-        old.register_mma.as_mut().unwrap().kind = Some(RegisterMmaKind::F8f6f4);
-        assert_eq!(
-            old.register_mma.as_ref().unwrap().kind,
-            Some(RegisterMmaKind::F8f6f4)
-        );
-    }
-
-    #[test]
-    fn standard_fp8_resolves_exact_routes_and_target_floors() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let catalog = resolve(&repo_root).unwrap();
-        let records = catalog
-            .intrinsics
-            .iter()
-            .filter(|record| {
-                record.rust.abi_id.as_str() >= "i0504" && record.rust.abi_id.as_str() <= "i0519"
-            })
-            .collect::<Vec<_>>();
-        let expected = [
-            (
-                "mma_m16n8k16_fp8_f16_e4m3_e4m3",
-                "i0504",
-                RegisterMmaShape::M16n8k16,
-                RegisterMmaAccumulator::F16,
-                87,
-            ),
-            (
-                "mma_m16n8k16_fp8_f16_e4m3_e5m2",
-                "i0505",
-                RegisterMmaShape::M16n8k16,
-                RegisterMmaAccumulator::F16,
-                87,
-            ),
-            (
-                "mma_m16n8k16_fp8_f16_e5m2_e4m3",
-                "i0506",
-                RegisterMmaShape::M16n8k16,
-                RegisterMmaAccumulator::F16,
-                87,
-            ),
-            (
-                "mma_m16n8k16_fp8_f16_e5m2_e5m2",
-                "i0507",
-                RegisterMmaShape::M16n8k16,
-                RegisterMmaAccumulator::F16,
-                87,
-            ),
-            (
-                "mma_m16n8k16_fp8_f32_e4m3_e4m3",
-                "i0508",
-                RegisterMmaShape::M16n8k16,
-                RegisterMmaAccumulator::F32,
-                87,
-            ),
-            (
-                "mma_m16n8k16_fp8_f32_e4m3_e5m2",
-                "i0509",
-                RegisterMmaShape::M16n8k16,
-                RegisterMmaAccumulator::F32,
-                87,
-            ),
-            (
-                "mma_m16n8k16_fp8_f32_e5m2_e4m3",
-                "i0510",
-                RegisterMmaShape::M16n8k16,
-                RegisterMmaAccumulator::F32,
-                87,
-            ),
-            (
-                "mma_m16n8k16_fp8_f32_e5m2_e5m2",
-                "i0511",
-                RegisterMmaShape::M16n8k16,
-                RegisterMmaAccumulator::F32,
-                87,
-            ),
-            (
-                "mma_m16n8k32_fp8_f16_e4m3_e4m3",
-                "i0512",
-                RegisterMmaShape::M16n8k32,
-                RegisterMmaAccumulator::F16,
-                87,
-            ),
-            (
-                "mma_m16n8k32_fp8_f16_e4m3_e5m2",
-                "i0513",
-                RegisterMmaShape::M16n8k32,
-                RegisterMmaAccumulator::F16,
-                87,
-            ),
-            (
-                "mma_m16n8k32_fp8_f16_e5m2_e4m3",
-                "i0514",
-                RegisterMmaShape::M16n8k32,
-                RegisterMmaAccumulator::F16,
-                87,
-            ),
-            (
-                "mma_m16n8k32_fp8_f16_e5m2_e5m2",
-                "i0515",
-                RegisterMmaShape::M16n8k32,
-                RegisterMmaAccumulator::F16,
-                87,
-            ),
-            (
-                "mma_m16n8k32_fp8_f32_e4m3_e4m3",
-                "i0516",
-                RegisterMmaShape::M16n8k32,
-                RegisterMmaAccumulator::F32,
-                84,
-            ),
-            (
-                "mma_m16n8k32_fp8_f32_e4m3_e5m2",
-                "i0517",
-                RegisterMmaShape::M16n8k32,
-                RegisterMmaAccumulator::F32,
-                84,
-            ),
-            (
-                "mma_m16n8k32_fp8_f32_e5m2_e4m3",
-                "i0518",
-                RegisterMmaShape::M16n8k32,
-                RegisterMmaAccumulator::F32,
-                84,
-            ),
-            (
-                "mma_m16n8k32_fp8_f32_e5m2_e5m2",
-                "i0519",
-                RegisterMmaShape::M16n8k32,
-                RegisterMmaAccumulator::F32,
-                84,
-            ),
-        ];
-        assert_eq!(records.len(), expected.len());
-        let sm_89 = CatalogHardwareTarget::AnyOf {
-            alternatives: vec![CatalogHardwareAlternative::MinimumSm { sm: 89 }],
-        };
-        let expected_routes = [
-            (
-                IntrinsicBackend::LlvmNvptx,
-                BackendLoweringMechanism::InlinePtx,
-                "rust-llvm-22.1.2-1cb4e383",
-            ),
-            (
-                IntrinsicBackend::LibNvvm,
-                BackendLoweringMechanism::InlinePtx,
-                "cuda-13.3-libnvvm-13.3.33",
-            ),
-        ];
-        let mut floor_groups = BTreeMap::new();
-
-        for (record, &(id, abi_id, shape, accumulator, minimum_ptx)) in
-            records.iter().zip(&expected)
-        {
-            assert_eq!(record.id, id);
-            assert_eq!(record.rust.abi_id, abi_id);
-            let mma = record.register_mma.as_ref().unwrap();
-            assert_eq!((mma.shape, mma.accumulator), (shape, accumulator));
-            assert_eq!(record.target.minimum_ptx.encoded(), minimum_ptx);
-            assert_eq!(record.target.hardware, sm_89);
-            assert_eq!(
-                record
-                    .backend_lowerings
-                    .iter()
-                    .map(|route| (
-                        route.backend,
-                        route.mechanism,
-                        route.evidence_profile.as_str()
-                    ))
-                    .collect::<Vec<_>>(),
-                expected_routes
-            );
-            for route in &record.backend_lowerings {
-                assert_eq!(route.target.minimum_ptx.encoded(), minimum_ptx);
-                assert_eq!(route.target.hardware, sm_89);
-            }
-            *floor_groups
-                .entry((shape, accumulator, minimum_ptx))
-                .or_insert(0) += 1;
-
-            if shape == RegisterMmaShape::M16n8k32 && accumulator == RegisterMmaAccumulator::F16 {
-                assert_eq!(
-                    record
-                        .selections
-                        .iter()
-                        .flat_map(|selection| &selection.predicates)
-                        .filter(|predicate| predicate.contains("getPTXVersion"))
-                        .map(String::as_str)
-                        .collect::<Vec<_>>(),
-                    ["Subtarget->getPTXVersion() >= 84"]
-                );
-                let llvm_route = &record.backend_lowerings[0];
-                assert!(llvm_route.stages.iter().any(|stage| {
-                    stage.stage == EvidenceStageKind::PtxAssembly
-                        && stage.mechanism == Some(BackendLoweringMechanism::InlinePtx)
-                        && stage.outcome == "succeeded"
-                        && stage.targets == ["sm_89", "ptx87"]
-                        && stage.artifact_kind == Some(EvidenceArtifactKind::Cubin)
-                }));
-                assert!(llvm_route.stages.iter().any(|stage| {
-                    stage.stage == EvidenceStageKind::PtxAssembly
-                        && stage.mechanism == Some(BackendLoweringMechanism::InlinePtx)
-                        && stage.outcome == "failed"
-                        && stage.targets == ["sm_89", "ptx86"]
-                }));
-            }
-        }
-        assert_eq!(
-            floor_groups,
-            BTreeMap::from([
-                (
-                    (RegisterMmaShape::M16n8k16, RegisterMmaAccumulator::F16, 87),
-                    4
-                ),
-                (
-                    (RegisterMmaShape::M16n8k16, RegisterMmaAccumulator::F32, 87),
-                    4
-                ),
-                (
-                    (RegisterMmaShape::M16n8k32, RegisterMmaAccumulator::F16, 87),
-                    4
-                ),
-                (
-                    (RegisterMmaShape::M16n8k32, RegisterMmaAccumulator::F32, 84),
-                    4
-                ),
-            ])
-        );
-    }
-
-    #[test]
-    fn existing_catalog_intrinsics_keep_their_json_shape_without_kind() {
-        fn abi_number(abi_id: &str) -> u16 {
-            validate_abi_id(abi_id).unwrap();
-            abi_id[1..].parse().unwrap()
-        }
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let original: serde_json::Value =
-            read_json(&repo_root.join("intrinsics/catalog.json")).unwrap();
-        let catalog: CatalogFile = read_json(&repo_root.join("intrinsics/catalog.json")).unwrap();
-        let serialized = serde_json::to_value(&catalog).unwrap();
-        let original_by_abi = original["intrinsics"]
-            .as_array()
-            .unwrap()
-            .iter()
-            .map(|record| {
-                let abi_id = record["rust"]["abi_id"].as_str().unwrap();
-                (abi_number(abi_id), record)
-            })
-            .collect::<BTreeMap<_, _>>();
-        let serialized_by_abi = serialized["intrinsics"]
-            .as_array()
-            .unwrap()
-            .iter()
-            .map(|record| {
-                let abi_id = record["rust"]["abi_id"].as_str().unwrap();
-                (abi_number(abi_id), record)
-            })
-            .collect::<BTreeMap<_, _>>();
-        for abi in 1..=503 {
-            assert_eq!(original_by_abi.get(&abi), serialized_by_abi.get(&abi));
-        }
-
-        let existing = catalog
-            .intrinsics
-            .iter()
-            .filter(|record| abi_number(&record.rust.abi_id) <= 503)
-            .collect::<Vec<_>>();
-        assert_eq!(existing.len(), 503);
-        assert!(existing.iter().all(|record| {
-            record
-                .register_mma
-                .as_ref()
-                .is_none_or(|mma| mma.kind.is_none())
-        }));
-
-        let standard_fp8 = catalog
-            .intrinsics
-            .iter()
-            .filter(|record| (504..=519).contains(&abi_number(&record.rust.abi_id)))
-            .collect::<Vec<_>>();
-        assert!(standard_fp8.is_empty() || standard_fp8.len() == 16);
-        if standard_fp8.len() == 16 {
-            assert!(standard_fp8.iter().all(|record| {
-                record
-                    .register_mma
-                    .as_ref()
-                    .is_some_and(|mma| mma.kind == Some(RegisterMmaKind::Standard))
-            }));
-            for abi in 504..=519 {
-                assert_eq!(original_by_abi[&abi]["register_mma"]["kind"], "standard");
-            }
-        }
-    }
-
-    #[test]
-    fn dense_f8f6f4_candidate_floor_uses_the_resolved_policy() {
-        for accumulator in [RegisterMmaAccumulator::F16, RegisterMmaAccumulator::F32] {
-            let policy = expand_register_mma_f8f6f4_admission(
-                &test_register_mma_f8f6f4_admission(accumulator),
-                accumulator,
-            )
-            .unwrap()
-            .remove(0);
-            let (_, requirement) = candidate_llvm_route(&policy).unwrap();
-
-            validate_candidate_target(&policy, &requirement, "sm_120a", "+ptx87").unwrap();
-            validate_candidate_target(&policy, &requirement, "sm_120f", "+ptx88").unwrap();
-            validate_candidate_target(&policy, &requirement, "sm_121a", "+ptx88").unwrap();
-            validate_candidate_target(&policy, &requirement, "sm_121f", "+ptx88").unwrap();
-            for target in ["sm_120f", "sm_121a", "sm_121f"] {
-                assert!(
-                    validate_candidate_target(&policy, &requirement, target, "+ptx87").is_err(),
-                    "{target} must require PTX 8.8"
-                );
-            }
-        }
-    }
-
-    #[test]
-    fn compact_prmt_admission_requires_every_mode_and_reserved_abi_id() {
-        assert_eq!(
-            expand_prmt_admission(&test_prmt_admission()).unwrap().len(),
-            7
-        );
-
-        let mut missing = test_prmt_admission();
-        missing.variants.pop();
-        assert!(expand_prmt_admission(&missing).is_err());
-
-        let mut duplicate = test_prmt_admission();
-        duplicate.variants[6].mode = PrmtMode::Rc8;
-        assert!(expand_prmt_admission(&duplicate).is_err());
-
-        let mut wrong_abi = test_prmt_admission();
-        wrong_abi.variants[0].abi_id = "i9999".into();
-        assert!(expand_prmt_admission(&wrong_abi).is_err());
-    }
-
-    #[test]
-    fn compact_fp8_conversion_axes_require_the_exact_closed_product() {
-        let records =
-            expand_packed_conversion_fp8_admission(&test_fp8_conversion_admission()).unwrap();
-        assert_eq!(records.len(), 4);
-        assert_eq!(records[0].id, "cvt_rn_satfinite_e4m3x2_f32");
-        assert_eq!(records[1].id, "cvt_rn_satfinite_relu_e4m3x2_f32");
-        assert_eq!(records[2].id, "cvt_rn_satfinite_e5m2x2_f32");
-        assert_eq!(records[3].id, "cvt_rn_satfinite_relu_e5m2x2_f32");
-        assert!(records.iter().all(|record| {
-            record.rust_result == "u16"
-                && record.dialect_results == ["i16"]
-                && record.llvm_results == ["i16"]
-                && record.minimum_ptx == "8.1"
-                && record.minimum_sm.as_deref() == Some("sm_89")
-                && record.pure
-                && !record.convergent
-        }));
-
-        let mut missing_format = test_fp8_conversion_admission();
-        missing_format.destination_formats.pop();
-        assert!(expand_packed_conversion_fp8_admission(&missing_format).is_err());
-
-        let mut reversed_formats = test_fp8_conversion_admission();
-        reversed_formats.destination_formats.reverse();
-        assert!(expand_packed_conversion_fp8_admission(&reversed_formats).is_err());
-
-        let mut missing_saturation = test_fp8_conversion_admission();
-        missing_saturation.saturations.pop();
-        assert!(expand_packed_conversion_fp8_admission(&missing_saturation).is_err());
-
-        let mut reversed_saturations = test_fp8_conversion_admission();
-        reversed_saturations.saturations.reverse();
-        assert!(expand_packed_conversion_fp8_admission(&reversed_saturations).is_err());
-
-        let mut wrong_count = test_fp8_conversion_admission();
-        wrong_count.product_count = 3;
-        assert!(expand_packed_conversion_fp8_admission(&wrong_count).is_err());
-
-        let mut executed = test_fp8_conversion_admission();
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_packed_conversion_fp8_admission(&executed).is_err());
-    }
-
-    #[test]
-    fn compact_fp8_f16x2_conversion_axes_require_the_exact_closed_product() {
-        let records =
-            expand_packed_conversion_fp8_f16x2_admission(&test_fp8_f16x2_conversion_admission())
-                .unwrap();
-        assert_eq!(records.len(), 8);
-        assert_eq!(records[0].id, "cvt_rn_satfinite_e4m3x2_f16x2");
-        assert_eq!(records[1].id, "cvt_rn_satfinite_relu_e4m3x2_f16x2");
-        assert_eq!(records[2].id, "cvt_rn_f16x2_e4m3x2");
-        assert_eq!(records[3].id, "cvt_rn_relu_f16x2_e4m3x2");
-        assert_eq!(records[4].id, "cvt_rn_satfinite_e5m2x2_f16x2");
-        assert_eq!(records[5].id, "cvt_rn_satfinite_relu_e5m2x2_f16x2");
-        assert_eq!(records[6].id, "cvt_rn_f16x2_e5m2x2");
-        assert_eq!(records[7].id, "cvt_rn_relu_f16x2_e5m2x2");
-
-        // Every form takes one packed operand and carries the Ada floor,
-        // including the unpacks whose destination is the older f16x2.
-        assert!(records.iter().all(|record| {
-            record.rust_arguments.len() == 1
-                && record.dialect_operands.len() == 1
-                && record.llvm_arguments.len() == 1
-                && record.expected_ptx.operands.len() == 2
-                && record.minimum_ptx == "8.1"
-                && record.minimum_sm.as_deref() == Some("sm_89")
-                && record.pure
-                && !record.convergent
-        }));
-
-        // Packing narrows f16x2 to a 16-bit FP8 pair; unpacking widens back.
-        assert!(
-            records
-                .iter()
-                .filter(|record| record.id.ends_with("_f16x2"))
-                .all(|record| {
-                    record.rust_arguments == ["u32"]
-                        && record.rust_result == "u16"
-                        && record.llvm_arguments == ["v2f16"]
-                        && record.llvm_results == ["i16"]
-                })
-        );
-        assert!(
-            records
-                .iter()
-                .filter(|record| !record.id.ends_with("_f16x2"))
-                .all(|record| {
-                    record.rust_arguments == ["u16"]
-                        && record.rust_result == "u32"
-                        && record.llvm_arguments == ["i16"]
-                        && record.llvm_results == ["v2f16"]
-                })
-        );
-
-        let mut missing_format = test_fp8_f16x2_conversion_admission();
-        missing_format.fp8_formats.pop();
-        assert!(expand_packed_conversion_fp8_f16x2_admission(&missing_format).is_err());
-
-        let mut reversed_formats = test_fp8_f16x2_conversion_admission();
-        reversed_formats.fp8_formats.reverse();
-        assert!(expand_packed_conversion_fp8_f16x2_admission(&reversed_formats).is_err());
-
-        let mut missing_direction = test_fp8_f16x2_conversion_admission();
-        missing_direction.directions.pop();
-        assert!(expand_packed_conversion_fp8_f16x2_admission(&missing_direction).is_err());
-
-        let mut reversed_directions = test_fp8_f16x2_conversion_admission();
-        reversed_directions.directions.reverse();
-        assert!(expand_packed_conversion_fp8_f16x2_admission(&reversed_directions).is_err());
-
-        let mut without_relu = test_fp8_f16x2_conversion_admission();
-        without_relu.relu_variants = false;
-        assert!(expand_packed_conversion_fp8_f16x2_admission(&without_relu).is_err());
-
-        let mut wrong_count = test_fp8_f16x2_conversion_admission();
-        wrong_count.product_count = 4;
-        assert!(expand_packed_conversion_fp8_f16x2_admission(&wrong_count).is_err());
-
-        let mut executed = test_fp8_f16x2_conversion_admission();
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_packed_conversion_fp8_f16x2_admission(&executed).is_err());
-    }
-
-    #[test]
-    fn compact_debug_control_admission_is_closed() {
-        let records = expand_debug_control_admission(&test_debug_control_admission()).unwrap();
-        assert_eq!(records.len(), 3);
-        assert_eq!(records[0].id, "trap");
-        assert_eq!(records[1].id, "breakpoint");
-        assert_eq!(records[2].id, "pmevent");
-        for record in &records {
-            validate_ptx_native_policy(record).unwrap();
-            assert_eq!(record.backend_lowerings.len(), 2);
-            assert!(
-                record
-                    .debug_control
-                    .as_ref()
-                    .is_some_and(|debug| debug.runtime_validation == RuntimeValidation::Unexecuted)
-            );
-        }
-        assert_eq!(records[0].minimum_ptx, "1.0");
-        assert_eq!(records[0].minimum_sm, None);
-        assert_eq!(records[1].minimum_ptx, "1.0");
-        assert_eq!(records[1].minimum_sm.as_deref(), Some("sm_11"));
-        assert_eq!(records[2].minimum_ptx, "1.4");
-        assert_eq!(
-            records[2].expected_ptx.operands,
-            [OperandPattern::Immediate]
-        );
-
-        let mut pending = test_debug_control_admission();
-        pending.abi_ids.clear();
-        assert!(expand_debug_control_admission(&pending).is_err());
-
-        let mut missing = test_debug_control_admission();
-        missing.operations.pop();
-        assert!(expand_debug_control_admission(&missing).is_err());
-
-        let mut duplicate_operation = test_debug_control_admission();
-        duplicate_operation.operations[2] = DebugControlOperation::Breakpoint;
-        assert!(expand_debug_control_admission(&duplicate_operation).is_err());
-
-        let mut duplicate_id = test_debug_control_admission();
-        duplicate_id.abi_ids[2] = duplicate_id.abi_ids[1].clone();
-        assert!(expand_debug_control_admission(&duplicate_id).is_err());
-
-        let mut malformed_id = test_debug_control_admission();
-        malformed_id.abi_ids[0] = "debug1".into();
-        assert!(expand_debug_control_admission(&malformed_id).is_err());
-
-        let mut executed = test_debug_control_admission();
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_debug_control_admission(&executed).is_err());
-
-        let mut wrong_source = records[0].clone();
-        wrong_source.source = Some(IntrinsicSource::LlvmImported {
-            source_record: "invented".into(),
-        });
-        assert!(validate_ptx_native_policy(&wrong_source).is_err());
-
-        let mut wrong_adapter = records[2].clone();
-        wrong_adapter.debug_control.as_mut().unwrap().adapter = DebugControlAdapter::Direct;
-        assert!(validate_ptx_native_policy(&wrong_adapter).is_err());
-
-        let mut wrong_immediate = records[2].clone();
-        wrong_immediate.expected_ptx.operands = vec![OperandPattern::Register];
-        assert!(validate_ptx_native_policy(&wrong_immediate).is_err());
-
-        let mut wrong_floor = records[1].clone();
-        wrong_floor.backend_lowerings[0].minimum_sm = Some("sm_75".into());
-        assert!(validate_ptx_native_policy(&wrong_floor).is_err());
-    }
-
-    #[test]
-    fn compact_clc_admission_matches_llvm_and_fails_closed() {
-        let records = expand_clc_admission(&test_clc_admission()).unwrap();
-        assert_eq!(records.len(), 6);
-        assert_eq!(
-            records
-                .iter()
-                .map(|record| (record.abi_id.as_str(), record.id.as_str()))
-                .collect::<Vec<_>>(),
-            [
-                ("i0322", "clc_try_cancel"),
-                ("i0323", "clc_try_cancel_multicast"),
-                ("i0324", "clc_query_is_canceled"),
-                ("i0325", "clc_query_get_first_ctaid_x"),
-                ("i0326", "clc_query_get_first_ctaid_y"),
-                ("i0327", "clc_query_get_first_ctaid_z"),
-            ]
-        );
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-        for record in &records {
-            let declaration = declarations[record.source_record.as_deref().unwrap()];
-            validate_imported_policy(record, declaration).unwrap();
-        }
-
-        assert_eq!(
-            parse_hardware_target(&records[1]).unwrap(),
-            CatalogHardwareTarget::AnyOf {
-                alternatives: vec![
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 120 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 121 },
-                ],
-            }
-        );
-
-        let mut missing = test_clc_admission();
-        missing.variants.pop();
-        assert!(expand_clc_admission(&missing).is_err());
-
-        let mut reordered = test_clc_admission();
-        reordered.variants.swap(0, 1);
-        assert!(expand_clc_admission(&reordered).is_err());
-
-        let mut wrong_abi = test_clc_admission();
-        wrong_abi.variants[0].abi_id = "i9999".into();
-        assert!(expand_clc_admission(&wrong_abi).is_err());
-
-        let mut executed = test_clc_admission();
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_clc_admission(&executed).is_err());
-
-        let declaration = declarations[records[2].source_record.as_deref().unwrap()];
-        let mut wrong_adapter = records[2].clone();
-        wrong_adapter.clc.as_mut().unwrap().adapter = ClcAdapter::PairU64ToI128U32;
-        assert!(validate_imported_policy(&wrong_adapter, declaration).is_err());
-
-        let mut unsorted_targets = records[1].clone();
-        unsorted_targets.targets = "sm_120a|sm_100a".into();
-        assert!(parse_hardware_target(&unsorted_targets).is_err());
-
-        let mut duplicate_targets = records[1].clone();
-        duplicate_targets.targets = "sm_100a|sm_100a".into();
-        assert!(parse_hardware_target(&duplicate_targets).is_err());
-    }
-
-    #[test]
-    fn clc_compact_schema_is_reserved_for_aggregation() {
-        let shard = |schema| OverlayShardFile {
-            schema,
-            family: "clc".into(),
-            intrinsics: vec![],
-            register_mma_int4: None,
-            register_mma_int8: None,
-            register_mma_b1: None,
-            register_mma_f8f6f4_f32: None,
-            register_mma_f8f6f4_f16: None,
-            register_mma_mxf8f6f4_f32: None,
-            register_mma_fp8: None,
-            register_mma_ampere_float: None,
-            sparse_mma_integer: None,
-            sparse_mma_f8f6f4_f32: None,
-            sparse_mma_f8f6f4_f16: None,
-            prmt: None,
-            packed_conversion_fp8: None,
-            packed_conversion_fp8_f16x2: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cluster_sreg: None,
-            cluster_barrier: None,
-            mbarrier_extended: None,
-            special_registers: None,
-            debug_control: None,
-            threadfence: None,
-            cluster_memory: None,
-            stmatrix: None,
-            clc: Some(test_clc_admission()),
-            wgmma_controls: None,
-            tma: None,
-            tcgen05: None,
-        };
-        let path = Path::new("intrinsics/overlay/clc.toml");
-        validate_overlay_shard_schema_with_max(&shard(CLC_SHARD_SCHEMA), path, CLC_SHARD_SCHEMA)
-            .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(CLC_SHARD_SCHEMA - 1),
-                path,
-                CLC_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("requires overlay shard schema 40")
-        );
-    }
-
-    #[test]
-    fn compact_tma_admission_matches_llvm_and_fails_closed() {
-        let records = expand_tma_admission(&test_tma_admission()).unwrap();
-        assert_eq!(
-            records.len(),
-            TMA_OPERATIONS.len() + tma_reduction_matrix().len()
-        );
-        assert!(records.iter().take(TMA_OPERATIONS.len()).all(|record| {
-            let operation = record.tma.as_ref().unwrap().operation;
-            let recipe = tma_recipe(operation);
-            record.backend_lowerings.iter().any(|route| {
-                route.backend == IntrinsicBackend::LlvmNvptx
-                    && route.mechanism == recipe.llvm_mechanism
-            }) && record.backend_lowerings.iter().any(|route| {
-                route.backend == IntrinsicBackend::LibNvvm
-                    && route.mechanism == BackendLoweringMechanism::InlinePtx
-            })
-        }));
-        assert_eq!(
-            records
-                .iter()
-                .filter(|record| {
-                    record
-                        .tma
-                        .as_ref()
-                        .unwrap()
-                        .operation
-                        .prefetch_coordinate_count()
-                        .is_some()
-                })
-                .count(),
-            12,
-            "the tile-prefetch subfamily must contain every plain/cache-hint pair"
-        );
-        assert_eq!(
-            records
-                .iter()
-                .take(TMA_OPERATIONS.len())
-                .map(|record| (record.abi_id.as_str(), record.id.as_str()))
-                .collect::<Vec<_>>(),
-            [
-                ("i0328", "cp_async_bulk_tensor_1d_g2s"),
-                ("i0329", "cp_async_bulk_tensor_2d_g2s"),
-                ("i0330", "cp_async_bulk_tensor_2d_g2s_multicast"),
-                ("i0331", "cp_async_bulk_tensor_2d_g2s_multicast_cg2"),
-                ("i0332", "cp_async_bulk_tensor_3d_g2s"),
-                ("i0333", "cp_async_bulk_tensor_4d_g2s"),
-                ("i0334", "cp_async_bulk_tensor_5d_g2s"),
-                ("i0335", "cp_async_bulk_tensor_1d_s2g"),
-                ("i0336", "cp_async_bulk_tensor_2d_s2g"),
-                ("i0337", "cp_async_bulk_tensor_3d_s2g"),
-                ("i0338", "cp_async_bulk_tensor_4d_s2g"),
-                ("i0339", "cp_async_bulk_tensor_5d_s2g"),
-                ("i0340", "cp_async_bulk_commit_group"),
-                ("i0341", "cp_async_bulk_wait_group"),
-                ("i0342", "cp_async_bulk_wait_group_read"),
-                ("i0887", "prefetch_tma_descriptor"),
-                ("i0888", "cp_async_bulk_prefetch_tensor_1d_l2"),
-                ("i0889", "cp_async_bulk_prefetch_tensor_2d_l2"),
-                ("i0890", "cp_async_bulk_prefetch_tensor_3d_l2"),
-                ("i0891", "cp_async_bulk_prefetch_tensor_4d_l2"),
-                ("i0892", "cp_async_bulk_prefetch_tensor_5d_l2"),
-                ("i0893", "cp_async_bulk_prefetch_tensor_gather4_2d_l2"),
-                ("i0894", "tensormap_replace_box_dim"),
-                ("i0895", "tensormap_replace_element_stride"),
-                ("i0896", "tensormap_replace_element_type"),
-                ("i0897", "tensormap_replace_fill_mode"),
-                ("i0898", "tensormap_replace_global_address"),
-                ("i0899", "tensormap_replace_global_dim"),
-                ("i0900", "tensormap_replace_global_stride"),
-                ("i0901", "tensormap_replace_interleave_layout"),
-                ("i0902", "tensormap_replace_rank"),
-                ("i0903", "tensormap_replace_swizzle_atomicity"),
-                ("i0904", "tensormap_replace_swizzle_mode"),
-                ("i0905", "fence_proxy_tensormap_generic_acquire_cluster"),
-                ("i0906", "fence_proxy_tensormap_generic_acquire_cta"),
-                ("i0907", "fence_proxy_tensormap_generic_acquire_gpu"),
-                ("i0908", "fence_proxy_tensormap_generic_acquire_system"),
-                ("i0909", "fence_proxy_tensormap_generic_release_cluster"),
-                ("i0910", "fence_proxy_tensormap_generic_release_cta"),
-                ("i0911", "fence_proxy_tensormap_generic_release_gpu"),
-                ("i0912", "fence_proxy_tensormap_generic_release_system"),
-                ("i0917", "cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"),
-                ("i0918", "cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"),
-                ("i0919", "cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"),
-                ("i0920", "cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"),
-                ("i0921", "cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"),
-                (
-                    "i0922",
-                    "cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
-                ),
-            ]
-        );
-
-        let reductions = &records[TMA_OPERATIONS.len()..];
-        assert_eq!(reductions.len(), 64);
-        assert_eq!(
-            (reductions[0].abi_id.as_str(), reductions[0].id.as_str()),
-            ("i0923", "cp_async_bulk_tensor_reduce_add_tile_1d")
-        );
-        assert_eq!(
-            (reductions[7].abi_id.as_str(), reductions[7].id.as_str()),
-            ("i0930", "cp_async_bulk_tensor_reduce_add_im2col_5d")
-        );
-        assert_eq!(
-            (reductions[63].abi_id.as_str(), reductions[63].id.as_str()),
-            ("i0986", "cp_async_bulk_tensor_reduce_xor_im2col_5d")
-        );
-        assert!(reductions.iter().all(|record| {
-            record.tma.as_ref().is_some_and(|tma| {
-                tma.operation == TmaOperation::Reduce
-                    && tma.reduction.is_some()
-                    && tma.adapter == TmaAdapter::ReductionPointersCoordinatesInjectDefaults
-            })
-        }));
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-        for record in &records {
-            let declaration = declarations[record.source_record.as_deref().unwrap()];
-            validate_imported_policy(record, declaration).unwrap();
-        }
-
-        assert_eq!(
-            parse_hardware_target(&records[3]).unwrap(),
-            CatalogHardwareTarget::AnyOf {
-                alternatives: vec![
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                ],
-            }
-        );
-
-        let mut missing = test_tma_admission();
-        missing.variants.pop();
-        assert!(expand_tma_admission(&missing).is_err());
-
-        let mut reordered = test_tma_admission();
-        reordered.variants.swap(0, 1);
-        assert!(expand_tma_admission(&reordered).is_err());
-
-        let mut wrong_abi = test_tma_admission();
-        wrong_abi.variants[0].abi_id = "i9999".into();
-        assert!(expand_tma_admission(&wrong_abi).is_err());
-
-        let mut missing_reduction = test_tma_admission();
-        missing_reduction.reduce_variants.pop();
-        assert!(expand_tma_admission(&missing_reduction).is_err());
-
-        let mut reordered_reduction = test_tma_admission();
-        reordered_reduction.reduce_variants.swap(0, 1);
-        assert!(expand_tma_admission(&reordered_reduction).is_err());
-
-        let mut non_contiguous_reduction_abi = test_tma_admission();
-        non_contiguous_reduction_abi.reduce_variants[0].abi_id = "i9999".into();
-        let records = expand_tma_admission(&non_contiguous_reduction_abi).unwrap();
-        assert_eq!(records[TMA_OPERATIONS.len()].abi_id, "i9999");
-
-        let mut executed = test_tma_admission();
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_tma_admission(&executed).is_err());
-
-        let declaration = declarations[records[0].source_record.as_deref().unwrap()];
-        let mut wrong_adapter = records[0].clone();
-        wrong_adapter.tma.as_mut().unwrap().adapter = TmaAdapter::NoOperands;
-        assert!(validate_imported_policy(&wrong_adapter, declaration).is_err());
-    }
-
-    #[test]
-    fn tma_compact_schema_is_reserved_for_aggregation() {
-        let shard = |schema: u32, include_reductions: bool| {
-            let mut admission = test_tma_admission();
-            if !include_reductions {
-                admission.reduce_variants.clear();
-            }
-            OverlayShardFile {
-                schema,
-                family: "tma".into(),
-                intrinsics: vec![],
-                register_mma_int4: None,
-                register_mma_int8: None,
-                register_mma_b1: None,
-                register_mma_f8f6f4_f32: None,
-                register_mma_f8f6f4_f16: None,
-                register_mma_mxf8f6f4_f32: None,
-                register_mma_fp8: None,
-                register_mma_ampere_float: None,
-                sparse_mma_integer: None,
-                sparse_mma_f8f6f4_f32: None,
-                sparse_mma_f8f6f4_f16: None,
-                prmt: None,
-                packed_conversion_fp8: None,
-                packed_conversion_fp8_f16x2: None,
-                scalar_conversion: None,
-                scalar_arithmetic: None,
-                scalar_math: None,
-                extended_minmax: None,
-                cluster_sreg: None,
-                cluster_barrier: None,
-                mbarrier_extended: None,
-                special_registers: None,
-                debug_control: None,
-                threadfence: None,
-                cluster_memory: None,
-                stmatrix: None,
-                clc: None,
-                wgmma_controls: None,
-                tma: Some(admission),
-                tcgen05: None,
-            }
-        };
-        let path = Path::new("intrinsics/overlay/tma.toml");
-
-        validate_overlay_shard_schema_with_max(
-            &shard(TMA_SHARD_SCHEMA, false),
-            path,
-            TMA_REDUCTION_SHARD_SCHEMA,
-        )
-        .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(TMA_SHARD_SCHEMA - 1, false),
-                path,
-                TMA_REDUCTION_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("compact TMA admission requires overlay shard schema 61")
-        );
-
-        validate_overlay_shard_schema_with_max(
-            &shard(TMA_REDUCTION_SHARD_SCHEMA, true),
-            path,
-            TMA_REDUCTION_SHARD_SCHEMA,
-        )
-        .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(TMA_REDUCTION_SHARD_SCHEMA - 1, true),
-                path,
-                TMA_REDUCTION_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("compact TMA reduction admission requires overlay shard schema 62")
-        );
-    }
-
-    #[test]
-    fn compact_tcgen05_admission_matches_llvm_and_fails_closed() {
-        let records = expand_tcgen05_admission(&test_tcgen05_admission()).unwrap();
-        assert_eq!(records.len(), 27);
-        assert_eq!(
-            records
-                .iter()
-                .map(|record| (record.abi_id.as_str(), record.id.as_str()))
-                .collect::<Vec<_>>(),
-            [
-                ("i0343", "tcgen05_alloc"),
-                ("i0344", "tcgen05_dealloc"),
-                ("i0345", "tcgen05_relinquish_alloc_permit"),
-                ("i0346", "tcgen05_fence_before_thread_sync"),
-                ("i0347", "tcgen05_fence_after_thread_sync"),
-                ("i0348", "tcgen05_commit"),
-                ("i0349", "tcgen05_commit_shared_cluster"),
-                ("i0350", "tcgen05_mma_ws_f16"),
-                ("i0351", "tcgen05_mma_f16"),
-                ("i0352", "tcgen05_mma_ws_bf16"),
-                ("i0353", "tcgen05_mma_ws_tf32"),
-                ("i0354", "tcgen05_cp_smem_to_tmem"),
-                ("i0355", "tcgen05_ld_16x256b_x8_pure"),
-                ("i0356", "tcgen05_ld_16x256b_pure"),
-                ("i0357", "tcgen05_load_wait"),
-                ("i0358", "tcgen05_store_wait"),
-                ("i0359", "tcgen05_alloc_cg2"),
-                ("i0360", "tcgen05_dealloc_cg2"),
-                ("i0361", "tcgen05_relinquish_alloc_permit_cg2"),
-                ("i0362", "tcgen05_mma_f16_cg2"),
-                ("i0363", "tcgen05_commit_cg2"),
-                ("i0364", "tcgen05_commit_shared_cluster_cg2"),
-                ("i0365", "tcgen05_commit_multicast_cg2"),
-                ("i0366", "tcgen05_cp_smem_to_tmem_cg2"),
-                ("i0760", "tcgen05_commit_multicast"),
-                ("i0761", "tcgen05_shift_down"),
-                ("i0762", "tcgen05_shift_down_cg2"),
-            ]
-        );
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-        for record in &records {
-            let declaration = declarations[record.source_record.as_deref().unwrap()];
-            validate_imported_policy(record, declaration).unwrap();
-            assert_tcgen05_backend_target_split(record);
-            assert_eq!(
-                record.execution_scope,
-                record.tcgen05.as_ref().unwrap().operation.execution_scope()
-            );
-        }
-
-        let bf16 = records
-            .iter()
-            .find(|record| record.id == "tcgen05_mma_ws_bf16")
-            .unwrap();
-        assert!(bf16.expected_ptx.modifiers.contains(&"kind::f16".into()));
-        assert!(!bf16.expected_ptx.modifiers.contains(&"kind::bf16".into()));
-        assert_eq!(
-            bf16.tcgen05.as_ref().unwrap().source_contract,
-            Tcgen05SourceContract::TablegenSelectionChangesPtx
-        );
-
-        let mma_f16 = records
-            .iter()
-            .find(|record| record.id == "tcgen05_mma_f16")
-            .unwrap();
-        assert!(mma_f16.expected_ptx.matches(
-            "tcgen05.mma.cta_group::1.kind::f16 [%r1], %rd1, %rd2, %r2, {%z, %z, %z, %z}, %enable_pred;"
-        ).unwrap());
-        assert!(!mma_f16.expected_ptx.matches(
-            "tcgen05.mma.cta_group::1.kind::f16 [%r1], %rd1, %rd2, %r2, {%clock64, %z, %z, %z}, %enable_pred;"
-        ).unwrap());
-        assert!(!mma_f16.expected_ptx.matches(
-            "tcgen05.mma.cta_group::1.kind::f16 [%r1], %rd1, %rd2, %r2, {%z, %z, %z, %z}, %other_pred;"
-        ).unwrap());
-
-        let mma_f16_cg2 = records
-            .iter()
-            .find(|record| record.id == "tcgen05_mma_f16_cg2")
-            .unwrap();
-        assert!(mma_f16_cg2.expected_ptx.matches(
-            "tcgen05.mma.cta_group::2.kind::f16 [%r1], %rd1, %rd2, %r2, {%z, %z, %z, %z, %z, %z, %z, %z}, %enable_pred;"
-        ).unwrap());
-        assert!(
-            !records
-                .iter()
-                .any(|record| { record.rust_name == "tcgen05_mma_ws_f16_with_collector" })
-        );
-        assert_eq!(
-            parse_hardware_target(&records[0]).unwrap(),
-            CatalogHardwareTarget::AnyOf {
-                alternatives: vec![
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-                    CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                ],
-            }
-        );
-
-        let legacy_records =
-            expand_tcgen05_admission(&without_tcgen05_control(test_tcgen05_admission())).unwrap();
-        assert_eq!(legacy_records.len(), 24);
-        assert!(legacy_records.iter().all(|record| {
-            record
-                .backend_lowerings
-                .iter()
-                .map(|lowering| lowering.evidence_profile.as_str())
-                .eq(["llvm-tcgen05-test", "libnvvm-tcgen05-test"])
-        }));
-
-        let multicast = records
-            .iter()
-            .find(|record| record.id == "tcgen05_commit_multicast")
-            .unwrap();
-        assert_eq!(multicast.abi_id, "i0760");
-        assert_eq!(multicast.rust_arguments, ["*mut u64", "u16"]);
-        assert_eq!(multicast.llvm_arguments, ["shared_ptr", "i16"]);
-        assert_eq!(multicast.execution_scope, "thread");
-        assert_eq!(
-            multicast.backend_lowerings[0].evidence_profile,
-            "llvm-tcgen05-control-test"
-        );
-        assert_eq!(
-            multicast.backend_lowerings[1].evidence_profile,
-            "libnvvm-tcgen05-control-test"
-        );
-
-        for (id, group) in [
-            ("tcgen05_shift_down", "cta_group::1"),
-            ("tcgen05_shift_down_cg2", "cta_group::2"),
-        ] {
-            let shift = records.iter().find(|record| record.id == id).unwrap();
-            assert_eq!(shift.rust_arguments, ["u32"]);
-            assert_eq!(shift.llvm_arguments, ["tmem_ptr"]);
-            assert_eq!(shift.execution_scope, "thread");
-            assert_eq!(shift.memory, "read_write");
-            assert_eq!(shift.expected_ptx.modifiers, ["shift", group, "down"]);
-            assert_eq!(shift.expected_ptx.operands, [OperandPattern::Address]);
-        }
-
-        let mut missing = test_tcgen05_admission();
-        missing.variants.pop();
-        assert!(expand_tcgen05_admission(&missing).is_err());
-
-        let mut reordered = test_tcgen05_admission();
-        reordered.variants.swap(0, 1);
-        assert!(expand_tcgen05_admission(&reordered).is_err());
-
-        let mut wrong_abi = test_tcgen05_admission();
-        wrong_abi.variants[0].abi_id = "i9999".into();
-        assert!(expand_tcgen05_admission(&wrong_abi).is_err());
-
-        let mut executed = test_tcgen05_admission();
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_tcgen05_admission(&executed).is_err());
-
-        let mut missing_control_evidence = test_tcgen05_admission();
-        missing_control_evidence.control_llvm_evidence_profile = None;
-        assert!(expand_tcgen05_admission(&missing_control_evidence).is_err());
-
-        let mut partial_control = without_tcgen05_control(test_tcgen05_admission());
-        partial_control
-            .variants
-            .push(test_tcgen05_admission().variants[24].clone());
-        assert!(expand_tcgen05_admission(&partial_control).is_err());
-
-        let shift = records
-            .iter()
-            .find(|record| record.id == "tcgen05_shift_down")
-            .unwrap();
-        let mut wrong_shift_declaration =
-            declarations[shift.source_record.as_deref().unwrap()].clone();
-        wrong_shift_declaration.selections[0].predicates =
-            vec!["Subtarget->hasTcgen05InstSupport()".into()];
-        assert!(validate_imported_policy(shift, &wrong_shift_declaration).is_err());
-
-        let declaration = declarations[records[0].source_record.as_deref().unwrap()];
-        let mut wrong_adapter = records[0].clone();
-        wrong_adapter.tcgen05.as_mut().unwrap().adapter = Tcgen05Adapter::NoOperands;
-        assert!(validate_imported_policy(&wrong_adapter, declaration).is_err());
-
-        let mut changed_declaration = declaration.clone();
-        changed_declaration.properties.pop();
-        assert!(validate_imported_policy(&records[0], &changed_declaration).is_err());
-
-        let mut broadened_libnvvm = records[0].clone();
-        broadened_libnvvm.backend_lowerings[1].targets = None;
-        assert!(validate_imported_policy(&broadened_libnvvm, declaration).is_err());
-
-        let mut wrong_alloc_scope = records[0].clone();
-        wrong_alloc_scope.execution_scope = "thread".into();
-        assert!(validate_imported_policy(&wrong_alloc_scope, declaration).is_err());
-
-        let pure_load = &records[12];
-        let pure_declaration = declarations[pure_load.source_record.as_deref().unwrap()];
-        let mut wrong_pure_load_scope = pure_load.clone();
-        wrong_pure_load_scope.execution_scope = "thread".into();
-        assert!(validate_imported_policy(&wrong_pure_load_scope, pure_declaration).is_err());
-    }
-
-    #[test]
-    fn compact_tcgen05_mma_admission_closes_sources_selectors_and_targets() {
-        let records = expand_tcgen05_admission(&test_tcgen05_mma_admission()).unwrap();
-        assert_eq!(records.len(), 51);
-        let mma = &records[27..];
-        assert_eq!(mma.len(), 24);
-        assert_eq!(
-            mma.iter()
-                .map(|record| (record.abi_id.as_str(), record.id.as_str()))
-                .collect::<Vec<_>>(),
-            [
-                ("i0763", "tcgen05_mma_shared"),
-                ("i0764", "tcgen05_mma_tensor"),
-                ("i0765", "tcgen05_mma_tensor_ashift"),
-                ("i0766", "tcgen05_mma_sp_shared"),
-                ("i0767", "tcgen05_mma_sp_tensor"),
-                ("i0768", "tcgen05_mma_sp_tensor_ashift"),
-                ("i0769", "tcgen05_mma_ws_shared"),
-                ("i0770", "tcgen05_mma_ws_shared_zero_col_mask"),
-                ("i0771", "tcgen05_mma_ws_sp_shared"),
-                ("i0772", "tcgen05_mma_ws_sp_shared_zero_col_mask"),
-                ("i0773", "tcgen05_mma_ws_sp_tensor"),
-                ("i0774", "tcgen05_mma_ws_sp_tensor_zero_col_mask"),
-                ("i0775", "tcgen05_mma_ws_tensor"),
-                ("i0776", "tcgen05_mma_ws_tensor_zero_col_mask"),
-                ("i0777", "tcgen05_mma_ws_e4m3"),
-                ("i0778", "tcgen05_mma_ws_e5m2"),
-                ("i0779", "tcgen05_mma_ws_e2m3"),
-                ("i0780", "tcgen05_mma_ws_e3m2"),
-                ("i0781", "tcgen05_mma_ws_e2m1"),
-                ("i1011", "tcgen05_mma_e4m3"),
-                ("i1012", "tcgen05_mma_e5m2"),
-                ("i1013", "tcgen05_mma_e2m3"),
-                ("i1014", "tcgen05_mma_e3m2"),
-                ("i1015", "tcgen05_mma_e2m1"),
-            ]
-        );
-        assert!(mma.iter().all(|record| {
-            record.dialect_op_type == TCGEN05_MMA_DIALECT_OP_TYPE
-                && record.dialect_op_name == TCGEN05_MMA_DIALECT_OP_NAME
-        }));
-        assert_eq!(
-            [
-                Tcgen05MmaBUsage::Discard,
-                Tcgen05MmaBUsage::LastUse,
-                Tcgen05MmaBUsage::Fill,
-                Tcgen05MmaBUsage::Use,
-            ]
-            .map(Tcgen05MmaBUsage::selector_value),
-            [0, 1, 2, 3]
-        );
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-        for record in mma {
-            let declaration = declarations[record.source_record.as_deref().unwrap()];
-            validate_imported_policy(record, declaration).unwrap();
-            assert_eq!(record.memory, "read_write");
-            assert!(record.convergent);
-            assert_eq!(record.execution_scope, "thread");
-            assert!(!record.safe);
-            assert_eq!(
-                record
-                    .expected_ptx
-                    .operands
-                    .iter()
-                    .filter(|operand| {
-                        **operand
-                            == (OperandPattern::Exact {
-                                value: "%enable_pred".into(),
-                            })
-                    })
-                    .count(),
-                1
-            );
-        }
-
-        let dense = &mma[0];
-        assert!(dense.expected_ptx.matches(
-            "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, %enable_pred;"
-        ).unwrap());
-        assert!(!dense.expected_ptx.matches(
-            "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, %clock64;"
-        ).unwrap());
-        assert!(mma[4].expected_ptx.matches(
-            "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [%r1], [%r2], %rd1, [%r3], %r4, %enable_pred;"
-        ).unwrap());
-        assert!(mma[7].expected_ptx.matches(
-            "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%r1], %rd1, %rd2, %r2, %enable_pred, %rd3;"
-        ).unwrap());
-        assert!(mma[14].expected_ptx.matches(
-            "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%r1], [%r2], %rd1, %r3, %enable_pred;"
-        ).unwrap());
-        assert!(mma[19].expected_ptx.matches(
-            "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [%r1], %rd1, %rd2, %r2, %enable_pred;"
-        ).unwrap());
-
-        let canonical = &mma[..14];
-        assert_eq!(
-            canonical
-                .iter()
-                .map(|record| record.source_record.as_deref().unwrap())
-                .collect::<BTreeSet<_>>()
-                .len(),
-            14
-        );
-        let selected_count = |record: &OverlayIntrinsic| {
-            declarations[record.source_record.as_deref().unwrap()]
-                .selections
-                .iter()
-                .filter(|selection| selection_matches_policy(record, selection).unwrap())
-                .count()
-        };
-        let newly_matched = canonical
-            .iter()
-            .filter(|record| record.id != "tcgen05_mma_ws_tensor")
-            .map(selected_count)
-            .sum::<usize>();
-        assert_eq!(newly_matched, 608);
-        assert_eq!(selected_count(&canonical[12]), 64);
-        assert_eq!(canonical.iter().map(selected_count).sum::<usize>(), 672);
-        assert_eq!(mma[14..].iter().map(selected_count).sum::<usize>(), 10);
-        assert_eq!(
-            [2, 5]
-                .into_iter()
-                .map(|index| {
-                    declarations[canonical[index].source_record.as_deref().unwrap()]
-                        .selections
-                        .len()
-                        - selected_count(&canonical[index])
-                })
-                .sum::<usize>(),
-            32
-        );
-
-        for record in canonical {
-            assert_eq!(
-                record.compatibility_rust_paths,
-                [format!("cuda_device::tcgen05::__{}", record.id)]
-            );
-            assert_eq!(
-                &record.rust_arguments[record.rust_arguments.len() - 3..],
-                ["u32", "u32", "u32"]
-            );
-            let contract = record.tcgen05.as_ref().unwrap().mma.as_ref().unwrap();
-            let CatalogHardwareTarget::TargetMatrix { contracts } = &contract.llvm_target.hardware
-            else {
-                panic!("generic LLVM tcgen05 MMA target must be a matrix")
-            };
-            assert_eq!(contracts.len(), 4);
-            assert_eq!(
-                contracts
-                    .iter()
-                    .map(|contract| contract.alternatives.len())
-                    .collect::<Vec<_>>(),
-                [8, 8, 3, 8]
-            );
-            let CatalogHardwareTarget::TargetMatrix { contracts } =
-                &contract.libnvvm_target.hardware
-            else {
-                panic!("generic libNVVM tcgen05 MMA target must be a matrix")
-            };
-            assert_eq!(contracts.len(), 4);
-            assert_eq!(
-                contracts
-                    .iter()
-                    .map(|contract| contract.alternatives.len())
-                    .collect::<Vec<_>>(),
-                [6, 6, 2, 6]
-            );
-        }
-        for record in &mma[14..19] {
-            assert_eq!(
-                record.compatibility_rust_paths,
-                [format!("cuda_device::tcgen05::{}", record.id)]
-            );
-            assert_eq!(
-                record.rust_arguments,
-                ["u32", "u32", "u64", "u64", "u32", "bool"]
-            );
-            assert_eq!(record.dialect_operands, ["i32", "i32", "i64", "i32", "i1"]);
-            let contract = record.tcgen05.as_ref().unwrap().mma.as_ref().unwrap();
-            assert_eq!(
-                contract.fixed_selectors,
-                Some(Tcgen05MmaFixedSelectors {
-                    kind: Tcgen05MmaKind::F8f6f4,
-                    b_buffer: 0,
-                    b_usage: Tcgen05MmaBUsage::Discard,
-                })
-            );
-            let CatalogHardwareTarget::TargetMatrix { contracts } = &contract.llvm_target.hardware
-            else {
-                panic!("fixed LLVM tcgen05 MMA target must be a matrix")
-            };
-            assert_eq!(contracts.len(), 1);
-            assert_eq!(contracts[0].selectors[0].value, "f8f6f4");
-        }
-        for record in &mma[19..] {
-            assert_eq!(
-                record.compatibility_rust_paths,
-                [format!("cuda_device::tcgen05::{}", record.id)]
-            );
-            assert_eq!(record.rust_arguments, ["u32", "u64", "u64", "u32", "bool"]);
-            assert_eq!(record.dialect_operands, ["i32", "i64", "i64", "i32", "i1"]);
-            let contract = record.tcgen05.as_ref().unwrap().mma.as_ref().unwrap();
-            assert_eq!(contract.form, Tcgen05MmaForm::Shared);
-            assert_eq!(
-                contract.fixed_selectors,
-                Some(Tcgen05MmaFixedSelectors {
-                    kind: Tcgen05MmaKind::F8f6f4,
-                    b_buffer: 0,
-                    b_usage: Tcgen05MmaBUsage::Discard,
-                })
-            );
-            assert_eq!(
-                record.tcgen05.as_ref().unwrap().adapter,
-                Tcgen05Adapter::MmaDirectSelectors
-            );
-            let CatalogHardwareTarget::TargetMatrix { contracts } = &contract.llvm_target.hardware
-            else {
-                panic!("fixed LLVM tcgen05 MMA target must be a matrix")
-            };
-            assert_eq!(contracts.len(), 1);
-            assert_eq!(contracts[0].selectors[0].value, "f8f6f4");
-        }
-
-        for legacy in [
-            "tcgen05_mma_ws_f16",
-            "tcgen05_mma_ws_bf16",
-            "tcgen05_mma_ws_tf32",
-        ] {
-            let old = &records[..27]
-                .iter()
-                .find(|record| record.id == legacy)
-                .unwrap();
-            assert!(old.tcgen05.as_ref().unwrap().mma.is_none());
-            assert!(old.abi_id.starts_with("i035"));
-            assert_eq!(
-                old.expected_ptx.operands.last(),
-                Some(&OperandPattern::Exact {
-                    value: "%enable_pred".into(),
-                })
-            );
-        }
-        let legacy_f16 = records
-            .iter()
-            .find(|record| record.id == "tcgen05_mma_ws_f16")
-            .unwrap();
-        assert!(
-            legacy_f16
-                .expected_ptx
-                .matches(
-                    "tcgen05.mma.ws.cta_group::1.kind::f16 [%r1], [%r2], %rd1, %r3, %enable_pred;"
-                )
-                .unwrap()
-        );
-        assert!(
-            !legacy_f16
-                .expected_ptx
-                .matches(
-                    "tcgen05.mma.ws.cta_group::1.kind::f16 [%r1], [%r2], %rd1, %r3, %other_pred;"
-                )
-                .unwrap()
-        );
-    }
-
-    #[test]
-    fn compact_tcgen05_mma_admission_fails_closed_on_drift() {
-        let mut missing = test_tcgen05_mma_admission();
-        missing.mma_variants.pop();
-        assert!(expand_tcgen05_admission(&missing).is_err());
-
-        let mut reordered = test_tcgen05_mma_admission();
-        reordered.mma_variants.swap(0, 1);
-        assert!(expand_tcgen05_admission(&reordered).is_err());
-
-        let mut non_contiguous_abi = test_tcgen05_mma_admission();
-        non_contiguous_abi.mma_variants[0].abi_id = "i9999".into();
-        let records = expand_tcgen05_admission(&non_contiguous_abi).unwrap();
-        assert!(records.iter().any(|record| record.abi_id == "i9999"));
-
-        let mut missing_target = test_tcgen05_mma_admission();
-        missing_target.mma_llvm_target_contracts[0]
-            .alternatives
-            .pop();
-        assert!(expand_tcgen05_admission(&missing_target).is_err());
-
-        let mut broadened_i8 = test_tcgen05_mma_admission();
-        broadened_i8.mma_libnvvm_target_contracts[2]
-            .alternatives
-            .insert(
-                1,
-                crate::model::TargetContractAlternative {
-                    target: "sm_103a".into(),
-                    minimum_ptx: "8.8".into(),
-                },
-            );
-        assert!(expand_tcgen05_admission(&broadened_i8).is_err());
-
-        let records = expand_tcgen05_admission(&test_tcgen05_mma_admission()).unwrap();
-        let record = records
-            .iter()
-            .find(|record| record.id == "tcgen05_mma_tensor_ashift")
-            .unwrap();
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declaration = imported
-            .intrinsics
-            .iter()
-            .find(|declaration| {
-                Some(declaration.source_record.as_str()) == record.source_record.as_deref()
-            })
-            .unwrap();
-
-        let mut wrong_layout = record.clone();
-        let mma = wrong_layout.tcgen05.as_mut().unwrap().mma.as_mut().unwrap();
-        mma.selector_layout = Tcgen05MmaSelectorLayout::Base {
-            kind_argument: 6,
-            cta_group_argument: 5,
-            collector_a_argument: 7,
-            collector_a_upper_exclusive: 2,
-        };
-        assert!(validate_imported_policy(&wrong_layout, declaration).is_err());
-
-        let mut wrong_properties = declaration.clone();
-        wrong_properties.properties.pop();
-        assert!(validate_imported_policy(record, &wrong_properties).is_err());
-
-        let mut wrong_range = declaration.clone();
-        let range = wrong_range
-            .properties
-            .iter_mut()
-            .find(|property| property.as_str() == "Range<arg7,0,2>")
-            .unwrap();
-        *range = "Range<arg7,0,4>".into();
-        assert!(validate_imported_policy(record, &wrong_range).is_err());
-
-        let mut wrong_predicate = declaration.clone();
-        wrong_predicate.selections[0].predicates = vec!["hasSM100a".into()];
-        assert!(validate_imported_policy(record, &wrong_predicate).is_err());
-
-        let mut wrong_memory = record.clone();
-        wrong_memory.memory = "write".into();
-        assert!(validate_imported_policy(&wrong_memory, declaration).is_err());
-
-        let mut wrong_convergence = record.clone();
-        wrong_convergence.convergent = false;
-        assert!(validate_imported_policy(&wrong_convergence, declaration).is_err());
-
-        let mut split_dialect_op = record.clone();
-        split_dialect_op.dialect_op_type = "Tcgen05MmaTensorAshiftOp".into();
-        split_dialect_op.dialect_op_name = "nvvm.tcgen05_mma_tensor_ashift".into();
-        assert!(validate_imported_policy(&split_dialect_op, declaration).is_err());
-    }
-
-    #[test]
-    fn compact_tcgen05_copy_admission_matches_all_llvm_records_and_fails_closed() {
-        let records = expand_tcgen05_admission(&test_tcgen05_cp_admission()).unwrap();
-        assert_eq!(records.len(), 61);
-        let copies = &records[27..];
-        assert_eq!(copies.len(), 34);
-        assert_eq!(
-            (copies[0].abi_id.as_str(), copies[0].id.as_str()),
-            ("i0578", "tcgen05_cp_128x128b_b4x16_p64")
-        );
-        assert_eq!(
-            (copies[33].abi_id.as_str(), copies[33].id.as_str()),
-            ("i0611", "tcgen05_cp_64x128b_warpx2_02_13_cg2")
-        );
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-        for record in copies {
-            let declaration = declarations[record.source_record.as_deref().unwrap()];
-            validate_imported_policy(record, declaration).unwrap();
-            assert_tcgen05_backend_target_split(record);
-            assert_eq!(record.rust_arguments, ["u32", "u64"]);
-            assert_eq!(record.rust_result, "()");
-            assert!(!record.safe);
-            assert!(record.convergent);
-            assert_eq!(record.memory, "read_write");
-            assert_eq!(record.targets, TCGEN05_LLVM_TARGETS);
-        }
-
-        let packed = copies
-            .iter()
-            .find(|record| record.id == "tcgen05_cp_128x128b_b4x16_p64")
-            .unwrap();
-        assert_eq!(
-            packed.expected_ptx.modifiers,
-            ["cp", "cta_group::1", "128x128b", "b8x16", "b4x16_p64"]
-        );
-        let warpx4 = copies
-            .iter()
-            .find(|record| record.id == "tcgen05_cp_32x128b_warpx4")
-            .unwrap();
-        assert_eq!(
-            warpx4.expected_ptx.modifiers,
-            ["cp", "cta_group::1", "32x128b", "warpx4"]
-        );
-        let pair_01_23 = copies
-            .iter()
-            .find(|record| record.id == "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2")
-            .unwrap();
-        assert_eq!(
-            pair_01_23.expected_ptx.modifiers,
-            [
-                "cp",
-                "cta_group::2",
-                "64x128b",
-                "warpx2::01_23",
-                "b8x16",
-                "b6x16_p32"
-            ]
-        );
-        let pair_02_13 = copies
-            .iter()
-            .find(|record| record.id == "tcgen05_cp_64x128b_warpx2_02_13")
-            .unwrap();
-        assert_eq!(
-            pair_02_13.expected_ptx.modifiers,
-            ["cp", "cta_group::1", "64x128b", "warpx2::02_13"]
-        );
-
-        let mut missing = test_tcgen05_cp_admission();
-        missing.cp_variants.pop();
-        assert!(expand_tcgen05_admission(&missing).is_err());
-
-        let mut reordered = test_tcgen05_cp_admission();
-        reordered.cp_variants.swap(0, 1);
-        assert!(expand_tcgen05_admission(&reordered).is_err());
-
-        let mut non_contiguous_abi = test_tcgen05_cp_admission();
-        non_contiguous_abi.cp_variants[0].abi_id = "i9999".into();
-        let records = expand_tcgen05_admission(&non_contiguous_abi).unwrap();
-        assert!(records.iter().any(|record| record.abi_id == "i9999"));
-
-        let mut missing_evidence = test_tcgen05_cp_admission();
-        missing_evidence.cp_llvm_evidence_profile = None;
-        assert!(expand_tcgen05_admission(&missing_evidence).is_err());
-
-        let declaration = declarations[copies[0].source_record.as_deref().unwrap()];
-        let mut wrong_spelling = copies[0].clone();
-        wrong_spelling.expected_ptx.modifiers.remove(3);
-        assert!(validate_imported_policy(&wrong_spelling, declaration).is_err());
-
-        let mut broadened_libnvvm = copies[0].clone();
-        broadened_libnvvm.backend_lowerings[1].targets = None;
-        assert!(validate_imported_policy(&broadened_libnvvm, declaration).is_err());
-    }
-
-    #[test]
-    fn compact_tcgen05_load_admission_matches_all_llvm_records_and_fails_closed() {
-        let records = expand_tcgen05_admission(&test_tcgen05_ld_admission()).unwrap();
-        assert_eq!(records.len(), 119);
-        let loads = &records[61..];
-        assert_eq!(loads.len(), 58);
-        assert_eq!(
-            (loads[0].abi_id.as_str(), loads[0].id.as_str()),
-            ("i0612", "tcgen05_ld_16x64b_x1_raw")
-        );
-        assert_eq!(
-            (loads[1].abi_id.as_str(), loads[1].id.as_str()),
-            ("i0613", "tcgen05_ld_16x64b_x1_pack16")
-        );
-        assert_eq!(
-            (loads[57].abi_id.as_str(), loads[57].id.as_str()),
-            ("i0669", "tcgen05_ld_32x32b_x128_pack16")
-        );
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-        let mut source_counts = BTreeMap::new();
-        for record in loads {
-            let source_record = record.source_record.as_deref().unwrap();
-            *source_counts.entry(source_record).or_insert(0) += 1;
-            let declaration = declarations[source_record];
-            validate_imported_policy(record, declaration).unwrap();
-            assert_tcgen05_backend_target_split(record);
-            assert_eq!(record.rust_arguments, ["u32"]);
-            assert!(record.must_use);
-            assert!(!record.safe);
-            assert!(!record.pure);
-            assert_eq!(record.memory, "read");
-            assert!(record.convergent);
-            assert_eq!(record.execution_scope, "warp");
-            assert!(
-                !record
-                    .rust_arguments
-                    .iter()
-                    .any(|argument| argument == "bool")
-            );
-            assert_eq!(record.dialect_operands, ["i32"]);
-            assert_eq!(record.llvm_arguments, ["tmem_ptr", "i1"]);
-            assert!(declaration.selections.is_empty());
-        }
-        assert_eq!(source_counts.len(), 29);
-        assert!(source_counts.values().all(|count| *count == 2));
-        assert_eq!(
-            records
-                .iter()
-                .filter(|record| {
-                    record.source_record.as_deref() == Some("int_nvvm_tcgen05_ld_16x256b_x1")
-                })
-                .count(),
-            3
-        );
-        assert_eq!(
-            records
-                .iter()
-                .filter(|record| {
-                    record.source_record.as_deref() == Some("int_nvvm_tcgen05_ld_16x256b_x8")
-                })
-                .count(),
-            3
-        );
-        validate_unique_overlay(&records, 1).unwrap();
-
-        let scalar_raw = &loads[0];
-        assert_eq!(scalar_raw.rust_result, "u32");
-        assert_eq!(scalar_raw.dialect_results, ["i32"]);
-        assert_eq!(scalar_raw.llvm_results, ["i32"]);
-        assert_eq!(
-            scalar_raw.expected_ptx.modifiers,
-            ["ld", "sync", "aligned", "16x64b", "x1", "b32"]
-        );
-        assert_eq!(
-            scalar_raw.expected_ptx.operands,
-            [
-                OperandPattern::RegisterList { length: 1 },
-                OperandPattern::Address,
-            ]
-        );
-        assert!(
-            scalar_raw
-                .expected_ptx
-                .matches("tcgen05.ld.sync.aligned.16x64b.x1.b32 {%r1}, [%r2];")
-                .unwrap()
-        );
-        assert!(
-            !scalar_raw
-                .expected_ptx
-                .matches("tcgen05.ld.sync.aligned.16x64b.x1.b32 %r1, [%r2];")
-                .unwrap()
-        );
-        let scalar_pack = &loads[1];
-        assert_eq!(
-            scalar_pack.expected_ptx.modifiers,
-            ["ld", "sync", "aligned", "16x64b", "x1", "pack::16b", "b32",]
-        );
-        let largest = &loads[57];
-        assert_eq!(largest.rust_result, "[u32; 128]");
-        assert_eq!(largest.dialect_results.len(), 128);
-        assert_eq!(largest.llvm_results, ["v128i32"]);
-        assert_eq!(
-            largest.expected_ptx.operands,
-            [
-                OperandPattern::RegisterList { length: 128 },
-                OperandPattern::Address,
-            ]
-        );
-
-        let mut missing = test_tcgen05_ld_admission();
-        missing.ld_variants.pop();
-        assert!(expand_tcgen05_admission(&missing).is_err());
-
-        let mut reordered = test_tcgen05_ld_admission();
-        reordered.ld_variants.swap(0, 1);
-        assert!(expand_tcgen05_admission(&reordered).is_err());
-
-        let mut non_contiguous_abi = test_tcgen05_ld_admission();
-        non_contiguous_abi.ld_variants[0].abi_id = "i9999".into();
-        let records = expand_tcgen05_admission(&non_contiguous_abi).unwrap();
-        assert!(records.iter().any(|record| record.abi_id == "i9999"));
-
-        let mut missing_evidence = test_tcgen05_ld_admission();
-        missing_evidence.ld_llvm_evidence_profile = None;
-        assert!(expand_tcgen05_admission(&missing_evidence).is_err());
-
-        let declaration = declarations[loads[0].source_record.as_deref().unwrap()];
-        let mut wrong_selector = loads[0].clone();
-        wrong_selector
-            .tcgen05
-            .as_mut()
-            .unwrap()
-            .ld
-            .as_mut()
-            .unwrap()
-            .pack16 = true;
-        assert!(validate_imported_policy(&wrong_selector, declaration).is_err());
-
-        let mut changed_declaration = declaration.clone();
-        changed_declaration.properties.pop();
-        assert!(validate_imported_policy(&loads[0], &changed_declaration).is_err());
-
-        let mut wrong_scope = loads[0].clone();
-        wrong_scope.execution_scope = "thread".into();
-        assert!(validate_imported_policy(&wrong_scope, declaration).is_err());
-
-        let mut unreviewed_sharing = records.clone();
-        unreviewed_sharing[62].tcgen05.as_mut().unwrap().operation = Tcgen05Operation::Alloc;
-        assert!(validate_unique_overlay(&unreviewed_sharing, 1).is_err());
-    }
-
-    #[test]
-    fn compact_tcgen05_store_admission_matches_all_llvm_records_and_fails_closed() {
-        let records = expand_tcgen05_admission(&test_tcgen05_st_admission()).unwrap();
-        assert_eq!(records.len(), 177);
-        let stores = &records[119..];
-        assert_eq!(stores.len(), 58);
-        assert_eq!(
-            (stores[0].abi_id.as_str(), stores[0].id.as_str()),
-            ("i0670", "tcgen05_st_16x64b_x1_raw")
-        );
-        assert_eq!(
-            (stores[1].abi_id.as_str(), stores[1].id.as_str()),
-            ("i0671", "tcgen05_st_16x64b_x1_unpack16")
-        );
-        assert_eq!(
-            (stores[57].abi_id.as_str(), stores[57].id.as_str()),
-            ("i0727", "tcgen05_st_32x32b_x128_unpack16")
-        );
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-        let mut source_counts = BTreeMap::new();
-        for record in stores {
-            let source_record = record.source_record.as_deref().unwrap();
-            *source_counts.entry(source_record).or_insert(0) += 1;
-            let declaration = declarations[source_record];
-            validate_imported_policy(record, declaration).unwrap();
-            assert_tcgen05_backend_target_split(record);
-            assert_eq!(record.rust_arguments.len(), 2);
-            assert_eq!(record.rust_result, "()");
-            assert!(!record.must_use);
-            assert!(!record.safe);
-            assert!(!record.pure);
-            assert_eq!(record.memory, "write");
-            assert!(record.convergent);
-            assert_eq!(record.execution_scope, "warp");
-            assert_eq!(record.dialect_results, Vec::<String>::new());
-            assert_eq!(record.llvm_results, Vec::<String>::new());
-            assert_eq!(record.llvm_arguments, declaration.arguments);
-            assert_eq!(
-                declaration.properties,
-                [
-                    "ImmArg<arg2>",
-                    "IntrArgMemOnly",
-                    "IntrConvergent",
-                    "NoCapture<arg0>",
-                ]
-            );
-            assert!(declaration.selections.is_empty());
-        }
-        assert_eq!(source_counts.len(), 29);
-        assert!(source_counts.values().all(|count| *count == 2));
-        validate_unique_overlay(&records, 1).unwrap();
-
-        let scalar_raw = &stores[0];
-        assert_eq!(scalar_raw.rust_arguments, ["u32", "u32"]);
-        assert_eq!(scalar_raw.dialect_operands, ["i32", "i32"]);
-        assert_eq!(scalar_raw.llvm_arguments, ["tmem_ptr", "i32", "i1"]);
-        assert_eq!(
-            scalar_raw.expected_ptx.modifiers,
-            ["st", "sync", "aligned", "16x64b", "x1", "b32"]
-        );
-        assert_eq!(
-            scalar_raw.expected_ptx.operands,
-            [
-                OperandPattern::Address,
-                OperandPattern::RegisterList { length: 1 },
-            ]
-        );
-        assert!(
-            scalar_raw
-                .expected_ptx
-                .matches("tcgen05.st.sync.aligned.16x64b.x1.b32 [%r1], {%r2};")
-                .unwrap()
-        );
-        assert!(
-            !scalar_raw
-                .expected_ptx
-                .matches("tcgen05.st.sync.aligned.16x64b.x1.b32 [%r1], %r2;")
-                .unwrap()
-        );
-        assert_eq!(
-            stores[1].expected_ptx.modifiers,
-            [
-                "st",
-                "sync",
-                "aligned",
-                "16x64b",
-                "x1",
-                "unpack::16b",
-                "b32",
-            ]
-        );
-        let largest = &stores[57];
-        assert_eq!(largest.rust_arguments, ["u32", "[u32; 128]"]);
-        assert_eq!(largest.dialect_operands.len(), 129);
-        assert_eq!(largest.llvm_arguments, ["tmem_ptr", "v128i32", "i1"]);
-        assert_eq!(
-            largest.expected_ptx.operands,
-            [
-                OperandPattern::Address,
-                OperandPattern::RegisterList { length: 128 },
-            ]
-        );
-
-        let mut missing = test_tcgen05_st_admission();
-        missing.st_variants.pop();
-        assert!(expand_tcgen05_admission(&missing).is_err());
-
-        let mut reordered = test_tcgen05_st_admission();
-        reordered.st_variants.swap(0, 1);
-        assert!(expand_tcgen05_admission(&reordered).is_err());
-
-        let mut non_contiguous_abi = test_tcgen05_st_admission();
-        non_contiguous_abi.st_variants[0].abi_id = "i9999".into();
-        let records = expand_tcgen05_admission(&non_contiguous_abi).unwrap();
-        assert!(records.iter().any(|record| record.abi_id == "i9999"));
-
-        let mut missing_evidence = test_tcgen05_st_admission();
-        missing_evidence.st_llvm_evidence_profile = None;
-        assert!(expand_tcgen05_admission(&missing_evidence).is_err());
-
-        let declaration = declarations[stores[0].source_record.as_deref().unwrap()];
-        let mut wrong_selector = stores[0].clone();
-        wrong_selector
-            .tcgen05
-            .as_mut()
-            .unwrap()
-            .st
-            .as_mut()
-            .unwrap()
-            .unpack16 = true;
-        assert!(validate_imported_policy(&wrong_selector, declaration).is_err());
-
-        let mut changed_declaration = declaration.clone();
-        changed_declaration.properties.pop();
-        assert!(validate_imported_policy(&stores[0], &changed_declaration).is_err());
-
-        let mut wrong_scope = stores[0].clone();
-        wrong_scope.execution_scope = "thread".into();
-        assert!(validate_imported_policy(&wrong_scope, declaration).is_err());
-
-        let mut unreviewed_sharing = records.clone();
-        unreviewed_sharing[120].tcgen05.as_mut().unwrap().operation = Tcgen05Operation::Alloc;
-        assert!(validate_unique_overlay(&unreviewed_sharing, 1).is_err());
-    }
-
-    #[test]
-    fn compact_tcgen05_offset_admission_is_exact_and_fails_closed() {
-        let records = expand_tcgen05_admission(&test_tcgen05_offset_admission()).unwrap();
-        assert_eq!(records.len(), 209);
-        let loads = &records[177..193];
-        let stores = &records[193..209];
-        assert_eq!(
-            (loads[0].abi_id.as_str(), loads[0].id.as_str()),
-            ("i0728", "tcgen05_ld_16x32bx2_x1_raw")
-        );
-        assert_eq!(
-            (loads[15].abi_id.as_str(), loads[15].id.as_str()),
-            ("i0743", "tcgen05_ld_16x32bx2_x128_pack16")
-        );
-        assert_eq!(
-            (stores[0].abi_id.as_str(), stores[0].id.as_str()),
-            ("i0744", "tcgen05_st_16x32bx2_x1_raw")
-        );
-        assert_eq!(
-            (stores[15].abi_id.as_str(), stores[15].id.as_str()),
-            ("i0759", "tcgen05_st_16x32bx2_x128_unpack16")
-        );
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect::<BTreeMap<_, _>>();
-        let mut load_sources = BTreeMap::new();
-        for record in loads {
-            let source = record.source_record.as_deref().unwrap();
-            *load_sources.entry(source).or_insert(0) += 1;
-            let declaration = declarations[source];
-            validate_imported_policy(record, declaration).unwrap();
-            assert_tcgen05_backend_target_split(record);
-            assert_eq!(record.rust_arguments, ["u32", "i64"]);
-            assert_eq!(record.dialect_operands, ["i32", "i64"]);
-            assert_eq!(record.llvm_arguments, ["tmem_ptr", "i64", "i1"]);
-            assert_eq!(record.execution_scope, "warp");
-            assert!(record.must_use);
-            assert_eq!(
-                record.compatibility_rust_paths,
-                [format!("cuda_device::tcgen05::__{}", record.id)]
-            );
-            assert_eq!(
-                record.expected_ptx.operands.last(),
-                Some(&OperandPattern::Immediate)
-            );
-            assert_eq!(
-                declaration.properties,
-                [
-                    "ImmArg<arg1>",
-                    "ImmArg<arg2>",
-                    "IntrArgMemOnly",
-                    "IntrConvergent",
-                    "NoCapture<arg0>",
-                ]
-            );
-        }
-        assert_eq!(load_sources.len(), 8);
-        assert!(load_sources.values().all(|count| *count == 2));
-
-        let mut store_sources = BTreeMap::new();
-        for record in stores {
-            let source = record.source_record.as_deref().unwrap();
-            *store_sources.entry(source).or_insert(0) += 1;
-            let declaration = declarations[source];
-            validate_imported_policy(record, declaration).unwrap();
-            assert_tcgen05_backend_target_split(record);
-            assert_eq!(record.rust_arguments[0..2], ["u32", "i64"]);
-            assert_eq!(record.dialect_operands[0..2], ["i32", "i64"]);
-            assert_eq!(record.llvm_arguments[0..2], ["tmem_ptr", "i64"]);
-            assert_eq!(record.execution_scope, "warp");
-            assert!(!record.must_use);
-            assert_eq!(
-                record.compatibility_rust_paths,
-                [format!("cuda_device::tcgen05::__{}", record.id)]
-            );
-            assert_eq!(
-                record.expected_ptx.operands.get(1),
-                Some(&OperandPattern::Immediate)
-            );
-            assert_eq!(
-                declaration.properties,
-                [
-                    "ImmArg<arg1>",
-                    "ImmArg<arg3>",
-                    "IntrArgMemOnly",
-                    "IntrConvergent",
-                    "NoCapture<arg0>",
-                ]
-            );
-        }
-        assert_eq!(store_sources.len(), 8);
-        assert!(store_sources.values().all(|count| *count == 2));
-        validate_unique_overlay(&records, 1).unwrap();
-
-        let scalar_pack = &loads[1];
-        assert_eq!(
-            scalar_pack.expected_ptx.operands,
-            [
-                OperandPattern::RegisterList { length: 1 },
-                OperandPattern::Address,
-                OperandPattern::Immediate,
-            ]
-        );
-        assert!(
-            scalar_pack
-                .expected_ptx
-                .matches("tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 {%r1}, [%r2], 16;")
-                .unwrap()
-        );
-
-        let scalar_unpack = &stores[1];
-        assert_eq!(
-            scalar_unpack.expected_ptx.operands,
-            [
-                OperandPattern::Address,
-                OperandPattern::Immediate,
-                OperandPattern::RegisterList { length: 1 },
-            ]
-        );
-        assert!(
-            scalar_unpack
-                .expected_ptx
-                .matches("tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [%r1], 16, {%r2};")
-                .unwrap()
-        );
-
-        let mut missing = test_tcgen05_offset_admission();
-        missing.ld_offset_variants.pop();
-        assert!(expand_tcgen05_admission(&missing).is_err());
-
-        let mut reordered = test_tcgen05_offset_admission();
-        reordered.st_offset_variants.swap(0, 1);
-        assert!(expand_tcgen05_admission(&reordered).is_err());
-
-        let mut non_contiguous_abi = test_tcgen05_offset_admission();
-        non_contiguous_abi.ld_offset_variants[0].abi_id = "i9999".into();
-        let records = expand_tcgen05_admission(&non_contiguous_abi).unwrap();
-        assert!(records.iter().any(|record| record.abi_id == "i9999"));
-
-        let mut missing_evidence = test_tcgen05_offset_admission();
-        missing_evidence.offset_llvm_evidence_profile = None;
-        assert!(expand_tcgen05_admission(&missing_evidence).is_err());
-
-        let load_declaration = declarations[loads[0].source_record.as_deref().unwrap()];
-        let mut wrong_offset_type = loads[0].clone();
-        wrong_offset_type.rust_arguments[1] = "i32".into();
-        assert!(validate_imported_policy(&wrong_offset_type, load_declaration).is_err());
-
-        let mut wrong_scope = loads[0].clone();
-        wrong_scope.execution_scope = "thread".into();
-        assert!(validate_imported_policy(&wrong_scope, load_declaration).is_err());
-
-        let mut missing_immediate = loads[0].clone();
-        missing_immediate.expected_ptx.operands.pop();
-        assert!(validate_imported_policy(&missing_immediate, load_declaration).is_err());
-
-        let store_declaration = declarations[stores[0].source_record.as_deref().unwrap()];
-        let mut wrong_adapter = stores[0].clone();
-        wrong_adapter.tcgen05.as_mut().unwrap().adapter =
-            Tcgen05Adapter::TmemU32RegistersInjectUnpack16ToVoid;
-        assert!(validate_imported_policy(&wrong_adapter, store_declaration).is_err());
-
-        let mut changed_declaration = store_declaration.clone();
-        changed_declaration.properties.remove(0);
-        assert!(validate_imported_policy(&stores[0], &changed_declaration).is_err());
-    }
-
-    #[test]
-    fn tcgen05_compact_schema_is_reserved_for_aggregation() {
-        let shard = |schema, admission| OverlayShardFile {
-            schema,
-            family: "tcgen05".into(),
-            intrinsics: vec![],
-            register_mma_int4: None,
-            register_mma_int8: None,
-            register_mma_b1: None,
-            register_mma_f8f6f4_f32: None,
-            register_mma_f8f6f4_f16: None,
-            register_mma_mxf8f6f4_f32: None,
-            register_mma_fp8: None,
-            register_mma_ampere_float: None,
-            sparse_mma_integer: None,
-            sparse_mma_f8f6f4_f32: None,
-            sparse_mma_f8f6f4_f16: None,
-            prmt: None,
-            packed_conversion_fp8: None,
-            packed_conversion_fp8_f16x2: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cluster_sreg: None,
-            cluster_barrier: None,
-            mbarrier_extended: None,
-            special_registers: None,
-            debug_control: None,
-            threadfence: None,
-            cluster_memory: None,
-            stmatrix: None,
-            clc: None,
-            wgmma_controls: None,
-            tma: None,
-            tcgen05: Some(admission),
-        };
-        let path = Path::new("intrinsics/overlay/tcgen05.toml");
-        validate_overlay_shard_schema_with_max(
-            &shard(
-                TCGEN05_SHARD_SCHEMA,
-                without_tcgen05_control(test_tcgen05_admission()),
-            ),
-            path,
-            TCGEN05_CP_SHARD_SCHEMA,
-        )
-        .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(
-                    TCGEN05_SHARD_SCHEMA - 1,
-                    without_tcgen05_control(test_tcgen05_admission()),
-                ),
-                path,
-                TCGEN05_CP_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("requires overlay shard schema 42")
-        );
-        validate_overlay_shard_schema_with_max(
-            &shard(
-                TCGEN05_CP_SHARD_SCHEMA,
-                without_tcgen05_control(test_tcgen05_cp_admission()),
-            ),
-            path,
-            TCGEN05_CP_SHARD_SCHEMA,
-        )
-        .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(
-                    TCGEN05_CP_SHARD_SCHEMA - 1,
-                    without_tcgen05_control(test_tcgen05_cp_admission()),
-                ),
-                path,
-                TCGEN05_CP_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("requires overlay shard schema 52")
-        );
-        validate_overlay_shard_schema_with_max(
-            &shard(
-                TCGEN05_LD_SHARD_SCHEMA,
-                without_tcgen05_control(test_tcgen05_ld_admission()),
-            ),
-            path,
-            TCGEN05_LD_SHARD_SCHEMA,
-        )
-        .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(
-                    TCGEN05_LD_SHARD_SCHEMA - 1,
-                    without_tcgen05_control(test_tcgen05_ld_admission()),
-                ),
-                path,
-                TCGEN05_LD_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("requires overlay shard schema 53")
-        );
-        validate_overlay_shard_schema_with_max(
-            &shard(
-                TCGEN05_ST_SHARD_SCHEMA,
-                without_tcgen05_control(test_tcgen05_st_admission()),
-            ),
-            path,
-            TCGEN05_ST_SHARD_SCHEMA,
-        )
-        .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(
-                    TCGEN05_ST_SHARD_SCHEMA - 1,
-                    without_tcgen05_control(test_tcgen05_st_admission()),
-                ),
-                path,
-                TCGEN05_ST_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("requires overlay shard schema 54")
-        );
-        validate_overlay_shard_schema_with_max(
-            &shard(
-                TCGEN05_OFFSET_LDST_SHARD_SCHEMA,
-                without_tcgen05_control(test_tcgen05_offset_admission()),
-            ),
-            path,
-            TCGEN05_OFFSET_LDST_SHARD_SCHEMA,
-        )
-        .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(
-                    TCGEN05_OFFSET_LDST_SHARD_SCHEMA - 1,
-                    without_tcgen05_control(test_tcgen05_offset_admission()),
-                ),
-                path,
-                TCGEN05_OFFSET_LDST_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("requires overlay shard schema 55")
-        );
-        validate_overlay_shard_schema_with_max(
-            &shard(
-                TCGEN05_CONTROL_SHARD_SCHEMA,
-                test_tcgen05_offset_admission(),
-            ),
-            path,
-            TCGEN05_CONTROL_SHARD_SCHEMA,
-        )
-        .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(
-                    TCGEN05_CONTROL_SHARD_SCHEMA,
-                    without_tcgen05_control(test_tcgen05_offset_admission()),
-                ),
-                path,
-                TCGEN05_CONTROL_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("requires all three control variants and both backend evidence profiles")
-        );
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(
-                    TCGEN05_CONTROL_SHARD_SCHEMA - 1,
-                    test_tcgen05_offset_admission(),
-                ),
-                path,
-                TCGEN05_CONTROL_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("requires overlay shard schema 56")
-        );
-        validate_overlay_shard_schema_with_max(
-            &shard(TCGEN05_MMA_SHARD_SCHEMA, test_tcgen05_mma_admission()),
-            path,
-            TCGEN05_MMA_SHARD_SCHEMA,
-        )
-        .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(TCGEN05_MMA_SHARD_SCHEMA - 1, test_tcgen05_mma_admission(),),
-                path,
-                TCGEN05_MMA_SHARD_SCHEMA,
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("requires overlay shard schema 57")
-        );
-    }
-
-    #[test]
-    fn debug_control_compact_schema_is_reserved_for_aggregation() {
-        let shard = |schema| OverlayShardFile {
-            schema,
-            family: "debug_control".into(),
-            intrinsics: vec![],
-            register_mma_int4: None,
-            register_mma_int8: None,
-            register_mma_b1: None,
-            register_mma_f8f6f4_f32: None,
-            register_mma_f8f6f4_f16: None,
-            register_mma_mxf8f6f4_f32: None,
-            register_mma_fp8: None,
-            register_mma_ampere_float: None,
-            sparse_mma_integer: None,
-            sparse_mma_f8f6f4_f32: None,
-            sparse_mma_f8f6f4_f16: None,
-            prmt: None,
-            packed_conversion_fp8: None,
-            packed_conversion_fp8_f16x2: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cluster_sreg: None,
-            cluster_barrier: None,
-            mbarrier_extended: None,
-            special_registers: None,
-            debug_control: Some(test_debug_control_admission()),
-            threadfence: None,
-            cluster_memory: None,
-            stmatrix: None,
-            clc: None,
-            wgmma_controls: None,
-            tma: None,
-            tcgen05: None,
-        };
-        let path = Path::new("intrinsics/overlay/debug_control.toml");
-        validate_overlay_shard_schema_with_max(&shard(33), path, 33).unwrap();
-        assert!(validate_overlay_shard_schema_with_max(&shard(33), path, 32).is_err());
-        let error = validate_overlay_shard_schema_with_max(&shard(32), path, 33).unwrap_err();
-        assert!(
-            error
-                .to_string()
-                .contains("requires overlay shard schema 33")
-        );
-    }
-
-    #[test]
-    fn cluster_memory_compact_schema_is_reserved_and_fail_closed() {
-        let shard = |schema| OverlayShardFile {
-            schema,
-            family: "cluster_memory".into(),
-            intrinsics: vec![],
-            register_mma_int4: None,
-            register_mma_int8: None,
-            register_mma_b1: None,
-            register_mma_f8f6f4_f32: None,
-            register_mma_f8f6f4_f16: None,
-            register_mma_mxf8f6f4_f32: None,
-            register_mma_fp8: None,
-            register_mma_ampere_float: None,
-            sparse_mma_integer: None,
-            sparse_mma_f8f6f4_f32: None,
-            sparse_mma_f8f6f4_f16: None,
-            prmt: None,
-            packed_conversion_fp8: None,
-            packed_conversion_fp8_f16x2: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cluster_sreg: None,
-            cluster_barrier: None,
-            mbarrier_extended: None,
-            special_registers: None,
-            debug_control: None,
-            threadfence: None,
-            cluster_memory: Some(test_cluster_memory_admission()),
-            stmatrix: None,
-            clc: None,
-            wgmma_controls: None,
-            tma: None,
-            tcgen05: None,
-        };
-        let path = Path::new("intrinsics/overlay/cluster_memory.toml");
-        validate_overlay_shard_schema_with_max(
-            &shard(CLUSTER_MEMORY_SHARD_SCHEMA),
-            path,
-            CLUSTER_MEMORY_SHARD_SCHEMA,
-        )
-        .unwrap();
-        assert!(
-            validate_overlay_shard_schema_with_max(
-                &shard(CLUSTER_MEMORY_SHARD_SCHEMA),
-                path,
-                CLUSTER_MEMORY_SHARD_SCHEMA - 1,
-            )
-            .is_err()
-        );
-        let error = validate_overlay_shard_schema_with_max(
-            &shard(CLUSTER_MEMORY_SHARD_SCHEMA - 1),
-            path,
-            CLUSTER_MEMORY_SHARD_SCHEMA,
-        )
-        .unwrap_err();
-        assert!(
-            error
-                .to_string()
-                .contains("requires overlay shard schema 39")
-        );
-    }
-
-    #[test]
-    fn cluster_memory_admission_preserves_mapa_identity_and_ptx_native_read() {
-        let admission = test_cluster_memory_admission();
-        let records = expand_cluster_memory_admission(&admission).unwrap();
-        assert_eq!(records.len(), 2);
-        assert_eq!(records[0].id, "map_shared_rank");
-        assert_eq!(records[1].id, "dsmem_read_u32");
-        assert_eq!(records[0].abi_id, "i0320");
-        assert_eq!(records[1].abi_id, "i0321");
-        assert_eq!(
-            cluster_memory_inline_recipe(ClusterMemoryOperation::MapSharedRank),
-            ("mapa.shared::cluster.u64 $0, $1, $2;", "=l,l,r")
-        );
-        assert_eq!(
-            cluster_memory_inline_recipe(ClusterMemoryOperation::ReadU32),
-            (
-                "{ .reg .u64 %mapped; mapa.shared::cluster.u64 %mapped, $1, $2; ld.shared::cluster.u32 $0, [%mapped]; }",
-                "=r,l,r,~{memory}"
-            )
-        );
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let mapa = &records[0];
-        let declaration = imported
-            .intrinsics
-            .iter()
-            .find(|declaration| declaration.source_record == "int_nvvm_mapa_shared_cluster")
-            .unwrap();
-        assert_eq!(declaration.arguments, ["shared_ptr", "i32"]);
-        assert_eq!(declaration.results, ["shared_cluster_ptr"]);
-        assert_eq!(
-            declaration.properties,
-            ["IntrNoMem", "IntrSpeculatable", "NoCapture<arg0>"]
-        );
-        validate_imported_policy(mapa, declaration).unwrap();
-        assert_eq!(
-            declaration
-                .selections
-                .iter()
-                .filter(|selection| selection.asm.starts_with("mapa.shared::cluster.u64"))
-                .map(|selection| selection.source_record.as_str())
-                .collect::<BTreeSet<_>>(),
-            BTreeSet::from(["mapa_shared_cluster_64", "mapa_shared_cluster_64i"])
-        );
-
-        let read = &records[1];
-        validate_ptx_native_policy(read).unwrap();
-        assert!(read.source_record.is_none());
-        assert!(read.llvm_symbol.is_none());
-        assert!(matches!(
-            resolve_policy_source(read).unwrap(),
-            IntrinsicSource::PtxNative { .. }
-        ));
-        assert_eq!(read.memory, "read");
-
-        let mut wrong_adapter = mapa.clone();
-        wrong_adapter.cluster_memory.as_mut().unwrap().adapter =
-            ClusterMemoryAdapter::ConstU32PointerRankToU32;
-        assert!(validate_imported_policy(&wrong_adapter, declaration).is_err());
-
-        let mut typed_as3 = mapa.clone();
-        typed_as3.llvm_results = vec!["shared_ptr".into()];
-        assert!(validate_imported_policy(&typed_as3, declaration).is_err());
-
-        let mut wrong_route = mapa.clone();
-        wrong_route.backend_lowerings[0].mechanism = BackendLoweringMechanism::TypedNvvm;
-        assert!(validate_imported_policy(&wrong_route, declaration).is_err());
-
-        let mut wrong_floor = read.clone();
-        wrong_floor.minimum_sm = Some("sm_80".into());
-        assert!(validate_ptx_native_policy(&wrong_floor).is_err());
-
-        let mut missing = admission.clone();
-        missing.variants.pop();
-        assert!(expand_cluster_memory_admission(&missing).is_err());
-
-        let mut duplicate = admission.clone();
-        duplicate.variants[1].operation = ClusterMemoryOperation::MapSharedRank;
-        assert!(expand_cluster_memory_admission(&duplicate).is_err());
-
-        let mut wrong_abi = admission.clone();
-        wrong_abi.variants[0].abi_id = "i9999".into();
-        assert!(expand_cluster_memory_admission(&wrong_abi).is_err());
-
-        let mut executed = admission;
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_cluster_memory_admission(&executed).is_err());
-    }
-
-    #[test]
-    fn active_debug_control_sources_parse_and_prove_both_backend_routes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let shard_path = repo_root.join("intrinsics/overlay/debug_control.toml");
-        let shard: OverlayShardFile =
-            toml::from_str(&fs::read_to_string(&shard_path).unwrap()).unwrap();
-        validate_overlay_shard_schema_with_max(&shard, &shard_path, 33).unwrap();
-        let admission = shard.debug_control.unwrap();
-        assert_eq!(admission.abi_ids, ["i0295", "i0296", "i0297"]);
-        let records = expand_debug_control_admission(&admission).unwrap();
-
-        let evidence = vec![
-            read_evidence_file(
-                &repo_root.join("intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-debug-control.json"),
-            )
-            .unwrap(),
-            read_evidence_file(
-                &repo_root.join("intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-debug-control.json"),
-            )
-            .unwrap(),
-        ];
-        let indexed =
-            index_evidence(&evidence, "1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e").unwrap();
-        for record in &records {
-            let routes = resolve_backend_lowerings(record, &indexed).unwrap();
-            assert_eq!(routes.len(), 2);
-            assert!(routes.iter().all(|route| {
-                route.mechanism == BackendLoweringMechanism::InlinePtx
-                    && route.status == "validated"
-            }));
-        }
-    }
-
-    #[test]
-    fn compact_cluster_barrier_admission_and_semantics_fail_closed() {
-        let records = expand_cluster_barrier_admission(&test_cluster_barrier_admission()).unwrap();
-        assert_eq!(records.len(), 6);
-
-        let imported: ImportedFile = read_json(
-            &Path::new(env!("CARGO_MANIFEST_DIR"))
-                .join("../..")
-                .join("intrinsics/imported.json"),
-        )
-        .unwrap();
-        for record in &records {
-            let declaration = imported
-                .intrinsics
-                .iter()
-                .find(|declaration| {
-                    Some(declaration.source_record.as_str()) == record.source_record.as_deref()
-                })
-                .unwrap();
-            validate_imported_policy(record, declaration).unwrap();
-        }
-
-        let declaration_for = |record: &OverlayIntrinsic| {
-            imported
-                .intrinsics
-                .iter()
-                .find(|declaration| {
-                    Some(declaration.source_record.as_str()) == record.source_record.as_deref()
-                })
-                .unwrap()
-        };
-        let base = records
-            .iter()
-            .find(|record| {
-                record
-                    .cluster_barrier
-                    .as_ref()
-                    .is_some_and(|barrier| barrier.mode == ClusterBarrierMode::ArriveAligned)
-            })
-            .unwrap();
-
-        let mut wrong_mode = base.clone();
-        wrong_mode.cluster_barrier.as_mut().unwrap().mode = ClusterBarrierMode::WaitAligned;
-        assert!(validate_imported_policy(&wrong_mode, declaration_for(base)).is_err());
-
-        let mut wrong_order = base.clone();
-        wrong_order.cluster_barrier.as_mut().unwrap().ordering = ClusterBarrierOrdering::Relaxed;
-        assert!(validate_imported_policy(&wrong_order, declaration_for(base)).is_err());
-
-        let mut wrong_alignment = base.clone();
-        wrong_alignment.cluster_barrier.as_mut().unwrap().aligned = false;
-        assert!(validate_imported_policy(&wrong_alignment, declaration_for(base)).is_err());
-
-        let mut missing = test_cluster_barrier_admission();
-        missing.variants.pop();
-        assert!(expand_cluster_barrier_admission(&missing).is_err());
-
-        let mut duplicate = test_cluster_barrier_admission();
-        duplicate.variants[5].mode = ClusterBarrierMode::Arrive;
-        assert!(expand_cluster_barrier_admission(&duplicate).is_err());
-
-        let mut wrong_abi = test_cluster_barrier_admission();
-        wrong_abi.variants[0].abi_id = "i9999".into();
-        assert!(expand_cluster_barrier_admission(&wrong_abi).is_err());
-    }
-
-    #[test]
-    fn compact_extended_mbarrier_admission_preserves_all_manual_contracts() {
-        let records =
-            expand_mbarrier_extended_admission(&test_mbarrier_extended_admission()).unwrap();
-        assert_eq!(records.len(), 11);
-        assert_eq!(
-            records
-                .iter()
-                .map(|record| record.abi_id.as_str())
-                .collect::<Vec<_>>(),
-            (306..=316)
-                .map(|id| format!("i{id:04}"))
-                .collect::<Vec<_>>()
-        );
-
-        let imported: ImportedFile = read_json(
-            &Path::new(env!("CARGO_MANIFEST_DIR"))
-                .join("../..")
-                .join("intrinsics/imported.json"),
-        )
-        .unwrap();
-        for record in &records {
-            let contract = record.mbarrier_extended.as_ref().unwrap();
-            let (template, constraints) = mbarrier_extended_inline_recipe(contract.operation);
-            assert!(template.ends_with(';') || template.ends_with("; }"));
-            assert!(constraints.contains("~{memory}"));
-            assert!(record.convergent && record.memory == "read_write");
-            assert!(
-                record
-                    .backend_lowerings
-                    .iter()
-                    .all(|lowering| { lowering.mechanism == BackendLoweringMechanism::InlinePtx })
-            );
-            match contract.source_contract {
-                MbarrierExtendedSourceContract::LlvmImported => {
-                    let declaration = imported
-                        .intrinsics
-                        .iter()
-                        .find(|declaration| {
-                            Some(declaration.source_record.as_str())
-                                == record.source_record.as_deref()
-                        })
-                        .unwrap();
-                    validate_imported_policy(record, declaration).unwrap();
-                }
-                MbarrierExtendedSourceContract::PtxNativeRawClusterAddress => {
-                    validate_ptx_native_policy(record).unwrap();
-                    assert_eq!(record.rust_arguments, ["u64"]);
-                    assert_eq!(record.dialect_operands, ["i64"]);
-                }
-            }
-        }
-
-        let base = records
-            .iter()
-            .find(|record| record.id == "mbarrier_arrive_expect_tx")
-            .unwrap();
-        let declaration = imported
-            .intrinsics
-            .iter()
-            .find(|declaration| {
-                Some(declaration.source_record.as_str()) == base.source_record.as_deref()
-            })
-            .unwrap();
-        let mut wrong_adapter = base.clone();
-        wrong_adapter.mbarrier_extended.as_mut().unwrap().adapter =
-            MbarrierExtendedAdapter::PointerTokenToPredicate;
-        assert!(validate_imported_policy(&wrong_adapter, declaration).is_err());
-        let mut wrong_floor = base.clone();
-        wrong_floor.minimum_ptx = "8.6".into();
-        assert!(validate_imported_policy(&wrong_floor, declaration).is_err());
-        let mut lost_clobber = base.clone();
-        lost_clobber.memory = "none".into();
-        assert!(validate_imported_policy(&lost_clobber, declaration).is_err());
-
-        let remote = records
-            .iter()
-            .find(|record| record.id == "mbarrier_arrive_cluster")
-            .unwrap();
-        let incompatible = imported
-            .intrinsics
-            .iter()
-            .find(|declaration| {
-                declaration.source_record == "int_nvvm_mbarrier_arrive_scope_cluster_space_cluster"
-            })
-            .unwrap();
-        assert_eq!(incompatible.arguments, ["shared_cluster_ptr", "i32"]);
-        assert!(
-            validate_mbarrier_extended_policy(
-                remote,
-                &IntrinsicSource::LlvmImported {
-                    source_record: incompatible.source_record.clone(),
-                },
-                Some(incompatible),
-            )
-            .is_err()
-        );
-
-        let mut missing = test_mbarrier_extended_admission();
-        missing.variants.pop();
-        assert!(expand_mbarrier_extended_admission(&missing).is_err());
-        let mut duplicate = test_mbarrier_extended_admission();
-        duplicate.variants[10].operation = MbarrierExtendedOperation::ArriveExpectTxCta;
-        assert!(expand_mbarrier_extended_admission(&duplicate).is_err());
-        let mut wrong_abi = test_mbarrier_extended_admission();
-        wrong_abi.variants[0].abi_id = "i9999".into();
-        assert!(expand_mbarrier_extended_admission(&wrong_abi).is_err());
-    }
-
-    #[test]
-    fn compact_wgmma_control_admission_and_semantics_fail_closed() {
-        let records = expand_wgmma_control_admission(&test_wgmma_control_admission()).unwrap();
-        assert_eq!(records.len(), 3);
-
-        let imported: ImportedFile = read_json(
-            &Path::new(env!("CARGO_MANIFEST_DIR"))
-                .join("../..")
-                .join("intrinsics/imported.json"),
-        )
-        .unwrap();
-        let declaration_for = |record: &OverlayIntrinsic| {
-            imported
-                .intrinsics
-                .iter()
-                .find(|declaration| {
-                    Some(declaration.source_record.as_str()) == record.source_record.as_deref()
-                })
-                .unwrap()
-        };
-        for record in &records {
-            validate_imported_policy(record, declaration_for(record)).unwrap();
-            assert_eq!(record.targets, "sm_90a");
-            assert_eq!(record.minimum_ptx, "8.0");
-            assert_eq!(record.backend_lowerings.len(), 2);
-        }
-
-        let wait = records
-            .iter()
-            .find(|record| {
-                record
-                    .wgmma_control
-                    .as_ref()
-                    .is_some_and(|control| control.mode == WgmmaControlMode::WaitGroup)
-            })
-            .unwrap();
-        assert_eq!(wait.rust_arguments, ["u64"]);
-        assert_eq!(wait.dialect_operands, ["i64"]);
-        assert_eq!(
-            wait.compatibility_rust_paths,
-            ["cuda_device::wgmma::__wgmma_wait_group"]
-        );
-
-        let mut wrong_adapter = wait.clone();
-        wrong_adapter.wgmma_control.as_mut().unwrap().adapter = WgmmaControlAdapter::NoArguments;
-        assert!(validate_imported_policy(&wrong_adapter, declaration_for(wait)).is_err());
-
-        let mut wrong_participation = wait.clone();
-        wrong_participation.execution_scope = "warp".into();
-        assert!(validate_imported_policy(&wrong_participation, declaration_for(wait)).is_err());
-
-        let mut wrong_route = wait.clone();
-        wrong_route.backend_lowerings[1].mechanism = BackendLoweringMechanism::TypedNvvm;
-        assert!(validate_imported_policy(&wrong_route, declaration_for(wait)).is_err());
-
-        let mut wrong_target = wait.clone();
-        wrong_target.targets = "all".into();
-        wrong_target.minimum_sm = Some("sm_90".into());
-        assert!(validate_imported_policy(&wrong_target, declaration_for(wait)).is_err());
-
-        let mut missing = test_wgmma_control_admission();
-        missing.variants.pop();
-        assert!(expand_wgmma_control_admission(&missing).is_err());
-
-        let mut reversed = test_wgmma_control_admission();
-        reversed.variants.reverse();
-        assert!(expand_wgmma_control_admission(&reversed).is_err());
-
-        let mut duplicate = test_wgmma_control_admission();
-        duplicate.variants[2].mode = WgmmaControlMode::Fence;
-        assert!(expand_wgmma_control_admission(&duplicate).is_err());
-
-        let mut wrong_abi = test_wgmma_control_admission();
-        wrong_abi.variants[0].abi_id = "i9999".into();
-        assert!(expand_wgmma_control_admission(&wrong_abi).is_err());
-
-        let mut executed = test_wgmma_control_admission();
-        executed.runtime_validation = RuntimeValidation::Executed;
-        assert!(expand_wgmma_control_admission(&executed).is_err());
-    }
-
-    #[test]
-    fn wgmma_control_compact_schema_is_reserved_for_aggregation() {
-        let shard = OverlayShardFile {
-            schema: WGMMA_CONTROL_SHARD_SCHEMA,
-            family: "wgmma_control".into(),
-            intrinsics: vec![],
-            register_mma_int4: None,
-            register_mma_int8: None,
-            register_mma_b1: None,
-            register_mma_f8f6f4_f32: None,
-            register_mma_f8f6f4_f16: None,
-            register_mma_mxf8f6f4_f32: None,
-            register_mma_fp8: None,
-            register_mma_ampere_float: None,
-            sparse_mma_integer: None,
-            sparse_mma_f8f6f4_f32: None,
-            sparse_mma_f8f6f4_f16: None,
-            prmt: None,
-            packed_conversion_fp8: None,
-            packed_conversion_fp8_f16x2: None,
-            scalar_conversion: None,
-            scalar_arithmetic: None,
-            scalar_math: None,
-            extended_minmax: None,
-            cluster_sreg: None,
-            cluster_barrier: None,
-            mbarrier_extended: None,
-            special_registers: None,
-            debug_control: None,
-            threadfence: None,
-            cluster_memory: None,
-            stmatrix: None,
-            clc: None,
-            wgmma_controls: Some(test_wgmma_control_admission()),
-            tma: None,
-            tcgen05: None,
-        };
-        let path = Path::new("intrinsics/overlay/wgmma_control.toml");
-        validate_overlay_shard_schema_with_max(&shard, path, WGMMA_CONTROL_SHARD_SCHEMA).unwrap();
-        let mut old = shard;
-        old.schema -= 1;
-        assert!(
-            validate_overlay_shard_schema_with_max(&old, path, WGMMA_CONTROL_SHARD_SCHEMA)
-                .unwrap_err()
-                .to_string()
-                .contains("requires overlay shard schema 38")
-        );
-    }
-
-    #[test]
-    fn cluster_barrier_evidence_validates_both_backend_routes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let mut admission = test_cluster_barrier_admission();
-        admission.llvm_evidence_profile = "rust-llvm-22.1.2-1cb4e383".into();
-        admission.libnvvm_evidence_profile = "cuda-13.3-libnvvm-13.3.33-cluster-barrier".into();
-        let policies = expand_cluster_barrier_admission(&admission).unwrap();
-        let evidence_files = vec![
-            read_evidence_file(
-                &repo_root
-                    .join("intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-cluster-barrier.json"),
-            )
-            .unwrap(),
-            read_evidence_file(
-                &repo_root
-                    .join("intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-cluster-barrier.json"),
-            )
-            .unwrap(),
-        ];
-        let indexed =
-            index_evidence(&evidence_files, "1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e").unwrap();
-
-        for policy in &policies {
-            for lowering in &policy.backend_lowerings {
-                let evidence = indexed
-                    .get(&(lowering.evidence_profile.as_str(), policy.id.as_str()))
-                    .unwrap();
-                validate_evidence(policy, evidence, Some(lowering)).unwrap();
-            }
-        }
-
-        let mut missing_typed_failure = evidence_files.clone();
-        let libnvvm = missing_typed_failure
-            .iter_mut()
-            .find(|file| file.backend_kind == Some(IntrinsicBackend::LibNvvm))
-            .unwrap();
-        for record in &mut libnvvm.records {
-            record.stages.retain(|stage| {
-                stage.mechanism != Some(BackendLoweringMechanism::TypedNvvm)
-                    || stage.stage != EvidenceStageKind::DeviceLink
-            });
-        }
-        let indexed = index_evidence(
-            &missing_typed_failure,
-            "1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e",
-        )
-        .unwrap();
-        let policy = &policies[0];
-        let lowering = policy
-            .backend_lowerings
-            .iter()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
-            .unwrap();
-        let evidence = indexed
-            .get(&(lowering.evidence_profile.as_str(), policy.id.as_str()))
-            .unwrap();
-        assert!(validate_evidence(policy, evidence, Some(lowering)).is_err());
-    }
-
-    #[test]
-    fn pinned_register_mma_records_match_the_closed_recipes_and_fail_closed() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (mut overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        bind_pinned_abi_ids(&repo_root, &mut overlay);
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect();
-        let records: Vec<_> = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| record.family == "register_mma")
-            .collect();
-        assert_eq!(records.len(), 154);
-
-        let dense_f8f6f4_records = records
-            .iter()
-            .copied()
-            .filter(|record| {
-                record.register_mma.as_ref().is_some_and(|mma| {
-                    matches!(mma.kind, None | Some(RegisterMmaKind::F8f6f4))
-                        && register_mma_f8f6f4_element_name(mma.a_element).is_some()
-                        && register_mma_f8f6f4_element_name(mma.b_element).is_some()
-                })
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(dense_f8f6f4_records.len(), 50);
-        for (accumulator, first_abi, last_abi, adapter) in [
-            (
-                RegisterMmaAccumulator::F32,
-                "i0454",
-                "i0478",
-                RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32,
-            ),
-            (
-                RegisterMmaAccumulator::F16,
-                "i0479",
-                "i0503",
-                RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32,
-            ),
-        ] {
-            let family = dense_f8f6f4_records
-                .iter()
-                .copied()
-                .filter(|record| record.register_mma.as_ref().unwrap().accumulator == accumulator)
-                .collect::<Vec<_>>();
-            assert_eq!(family.len(), 25);
-            assert_eq!(family[0].abi_id, first_abi);
-            assert_eq!(family[24].abi_id, last_abi);
-            assert!(
-                family
-                    .iter()
-                    .all(|record| record.register_mma.as_ref().unwrap().adapter == adapter)
-            );
-        }
-        assert!(dense_f8f6f4_records.iter().all(|record| {
-            record.minimum_ptx == "8.7"
-                && record.minimum_sm.is_none()
-                && record.targets == REGISTER_MMA_F8F6F4_TARGETS
-        }));
-
-        let mxf8f6f4_records = records
-            .iter()
-            .copied()
-            .filter(|record| {
-                record
-                    .register_mma
-                    .as_ref()
-                    .is_some_and(|mma| mma.kind == Some(RegisterMmaKind::Mxf8f6f4))
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(mxf8f6f4_records.len(), 25);
-        assert_eq!(mxf8f6f4_records[0].abi_id, "i0858");
-        assert_eq!(mxf8f6f4_records[24].abi_id, "i0882");
-        assert!(mxf8f6f4_records.iter().all(|record| {
-            let mma = record.register_mma.as_ref().unwrap();
-            mma.shape == RegisterMmaShape::M16n8k32
-                && mma.accumulator == RegisterMmaAccumulator::F32
-                && mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
-                && record.rust_arguments
-                    == [
-                        "[f32; 4]", "[u32; 4]", "[u32; 2]", "u32", "u16", "u16", "u32", "u16",
-                        "u16",
-                    ]
-                && record.rust_result == "[f32; 4]"
-                && record.minimum_ptx == "8.7"
-                && record.minimum_sm.is_none()
-                && record.targets == REGISTER_MMA_F8F6F4_TARGETS
-                && record
-                    .expected_ptx
-                    .modifiers
-                    .iter()
-                    .any(|modifier| modifier == "kind::mxf8f6f4")
-        }));
-
-        let integer_records: Vec<_> = records
-            .iter()
-            .copied()
-            .filter(|record| {
-                record.register_mma.as_ref().is_some_and(|mma| {
-                    mma.operation == RegisterMmaOperation::Multiply
-                        && mma.accumulator == RegisterMmaAccumulator::S32
-                })
-            })
-            .collect();
-        assert_eq!(integer_records.len(), 48);
-        let binary_records = records
-            .iter()
-            .copied()
-            .filter(|record| {
-                record
-                    .register_mma
-                    .as_ref()
-                    .is_some_and(|mma| mma.operation != RegisterMmaOperation::Multiply)
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(binary_records.len(), 6);
-        let int8_records = integer_records
-            .iter()
-            .copied()
-            .filter(|record| {
-                let mma = record.register_mma.as_ref().unwrap();
-                matches!(
-                    mma.a_element,
-                    RegisterMmaElement::S8 | RegisterMmaElement::U8
-                ) && matches!(
-                    mma.b_element,
-                    RegisterMmaElement::S8 | RegisterMmaElement::U8
-                )
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(int8_records.len(), 24);
-        let int4_records = integer_records
-            .iter()
-            .copied()
-            .filter(|record| {
-                let mma = record.register_mma.as_ref().unwrap();
-                matches!(
-                    mma.a_element,
-                    RegisterMmaElement::S4 | RegisterMmaElement::U4
-                ) && matches!(
-                    mma.b_element,
-                    RegisterMmaElement::S4 | RegisterMmaElement::U4
-                )
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(int4_records.len(), 24);
-        let actual_variants = integer_records
-            .iter()
-            .map(|record| {
-                let mma = record.register_mma.as_ref().unwrap();
-                (mma.shape, mma.a_element, mma.b_element, mma.overflow)
-            })
-            .collect::<BTreeSet<_>>();
-        let expected_int8_variants = [
-            RegisterMmaShape::M8n8k16,
-            RegisterMmaShape::M16n8k16,
-            RegisterMmaShape::M16n8k32,
-        ]
-        .into_iter()
-        .flat_map(|shape| {
-            [RegisterMmaElement::S8, RegisterMmaElement::U8]
-                .into_iter()
-                .flat_map(move |a_element| {
-                    [RegisterMmaElement::S8, RegisterMmaElement::U8]
-                        .into_iter()
-                        .flat_map(move |b_element| {
-                            [
-                                RegisterMmaOverflow::Wrapping,
-                                RegisterMmaOverflow::Satfinite,
-                            ]
-                            .into_iter()
-                            .map(move |overflow| (shape, a_element, b_element, overflow))
-                        })
-                })
-        })
-        .collect::<BTreeSet<_>>();
-        let expected_int4_variants = [
-            RegisterMmaShape::M8n8k32,
-            RegisterMmaShape::M16n8k32,
-            RegisterMmaShape::M16n8k64,
-        ]
-        .into_iter()
-        .flat_map(|shape| {
-            [RegisterMmaElement::S4, RegisterMmaElement::U4]
-                .into_iter()
-                .flat_map(move |a_element| {
-                    [RegisterMmaElement::S4, RegisterMmaElement::U4]
-                        .into_iter()
-                        .flat_map(move |b_element| {
-                            [
-                                RegisterMmaOverflow::Wrapping,
-                                RegisterMmaOverflow::Satfinite,
-                            ]
-                            .into_iter()
-                            .map(move |overflow| (shape, a_element, b_element, overflow))
-                        })
-                })
-        })
-        .collect::<BTreeSet<_>>();
-        let expected_variants = expected_int8_variants
-            .union(&expected_int4_variants)
-            .copied()
-            .collect::<BTreeSet<_>>();
-        assert_eq!(actual_variants, expected_variants);
-        assert_eq!(
-            integer_records
-                .iter()
-                .filter(|record| {
-                    record.register_mma.as_ref().unwrap().compatibility_source
-                        == RegisterMmaCompatibilitySource::GeneratedStub
-                })
-                .count(),
-            47
-        );
-
-        let actual_binary_variants = binary_records
-            .iter()
-            .map(|record| {
-                let mma = record.register_mma.as_ref().unwrap();
-                (mma.shape, mma.operation)
-            })
-            .collect::<BTreeSet<_>>();
-        let expected_binary_variants = [
-            RegisterMmaShape::M8n8k128,
-            RegisterMmaShape::M16n8k128,
-            RegisterMmaShape::M16n8k256,
-        ]
-        .into_iter()
-        .flat_map(|shape| {
-            [RegisterMmaOperation::XorPopc, RegisterMmaOperation::AndPopc]
-                .into_iter()
-                .map(move |operation| (shape, operation))
-        })
-        .collect::<BTreeSet<_>>();
-        assert_eq!(actual_binary_variants, expected_binary_variants);
-        assert!(binary_records.iter().all(|record| {
-            let mma = record.register_mma.as_ref().unwrap();
-            mma.accumulator == RegisterMmaAccumulator::S32
-                && mma.a_element == RegisterMmaElement::B1
-                && mma.b_element == RegisterMmaElement::B1
-                && mma.overflow == RegisterMmaOverflow::Wrapping
-                && mma.compatibility_source == RegisterMmaCompatibilitySource::GeneratedStub
-                && record.expected_ptx.modifiers.ends_with(&[
-                    match mma.operation {
-                        RegisterMmaOperation::XorPopc => "xor".into(),
-                        RegisterMmaOperation::AndPopc => "and".into(),
-                        RegisterMmaOperation::Multiply => unreachable!(),
-                    },
-                    "popc".into(),
-                ])
-        }));
-
-        for record in &binary_records {
-            let mma = record.register_mma.as_ref().unwrap();
-            let (arguments, result, adapter) = match mma.shape {
-                RegisterMmaShape::M8n8k128 => (
-                    &["[i32; 2]", "u32", "u32"] as &[_],
-                    "[i32; 2]",
-                    RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32,
-                ),
-                RegisterMmaShape::M16n8k128 => (
-                    &["[i32; 4]", "[u32; 2]", "u32"] as &[_],
-                    "[i32; 4]",
-                    RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32,
-                ),
-                RegisterMmaShape::M16n8k256 => (
-                    &["[i32; 4]", "[u32; 4]", "[u32; 2]"] as &[_],
-                    "[i32; 4]",
-                    RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32,
-                ),
-                _ => unreachable!(),
-            };
-            assert_eq!(record.rust_arguments, arguments);
-            assert_eq!(record.rust_result, result);
-            assert_eq!(mma.adapter, adapter);
-            let expected_floor = match (mma.shape, mma.operation) {
-                (RegisterMmaShape::M8n8k128, RegisterMmaOperation::XorPopc) => ("7.0", "sm_75"),
-                (_, RegisterMmaOperation::XorPopc) => ("7.0", "sm_80"),
-                (_, RegisterMmaOperation::AndPopc) => ("7.1", "sm_80"),
-                _ => unreachable!(),
-            };
-            assert_eq!(record.minimum_ptx, expected_floor.0);
-            assert_eq!(record.minimum_sm.as_deref(), Some(expected_floor.1));
-        }
-
-        for record in integer_records.iter().filter(|record| {
-            matches!(
-                record.register_mma.as_ref().unwrap().shape,
-                RegisterMmaShape::M8n8k16 | RegisterMmaShape::M8n8k32
-            )
-        }) {
-            assert_eq!(record.rust_arguments, ["[i32; 2]", "u32", "u32"]);
-            assert_eq!(record.rust_result, "[i32; 2]");
-            assert_eq!(record.minimum_ptx, "6.5");
-            assert_eq!(record.minimum_sm.as_deref(), Some("sm_75"));
-            assert_eq!(
-                record.register_mma.as_ref().unwrap().adapter,
-                RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32
-            );
-        }
-
-        for record in int4_records.iter().filter(|record| {
-            record.register_mma.as_ref().unwrap().shape == RegisterMmaShape::M16n8k32
-        }) {
-            assert_eq!(record.rust_arguments, ["[i32; 4]", "[u32; 2]", "u32"]);
-            assert_eq!(record.rust_result, "[i32; 4]");
-            assert_eq!(record.minimum_ptx, "7.0");
-            assert_eq!(record.minimum_sm.as_deref(), Some("sm_80"));
-            assert_eq!(
-                record.register_mma.as_ref().unwrap().adapter,
-                RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32
-            );
-        }
-
-        for record in int4_records.iter().filter(|record| {
-            record.register_mma.as_ref().unwrap().shape == RegisterMmaShape::M16n8k64
-        }) {
-            assert_eq!(record.rust_arguments, ["[i32; 4]", "[u32; 4]", "[u32; 2]"]);
-            assert_eq!(record.rust_result, "[i32; 4]");
-            assert_eq!(record.minimum_ptx, "7.0");
-            assert_eq!(record.minimum_sm.as_deref(), Some("sm_80"));
-            assert_eq!(
-                record.register_mma.as_ref().unwrap().adapter,
-                RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32
-            );
-        }
-
-        let actual_int4_abi_ids = int4_records
-            .iter()
-            .map(|record| record.abi_id.as_str())
-            .collect::<BTreeSet<_>>();
-        let expected_int4_abi_ids = (133..=156)
-            .map(|id| format!("i{id:04}"))
-            .collect::<BTreeSet<_>>();
-        assert_eq!(
-            actual_int4_abi_ids,
-            expected_int4_abi_ids
-                .iter()
-                .map(String::as_str)
-                .collect::<BTreeSet<_>>()
-        );
-
-        let int8_k32 = int8_records
-            .iter()
-            .find(|record| {
-                record.register_mma.as_ref().unwrap().shape == RegisterMmaShape::M16n8k32
-            })
-            .unwrap();
-        let int4_k32 = int4_records
-            .iter()
-            .find(|record| {
-                record.register_mma.as_ref().unwrap().shape == RegisterMmaShape::M16n8k32
-            })
-            .unwrap();
-        assert_eq!(
-            int8_k32.register_mma.as_ref().unwrap().adapter,
-            RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32
-        );
-        assert_eq!(
-            int4_k32.register_mma.as_ref().unwrap().adapter,
-            RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32
-        );
-
-        for policy in &records {
-            let declaration = declarations[policy.source_record.as_deref().unwrap()];
-            assert_eq!(declaration.selections.len(), 1);
-            assert!(
-                selection_matches_policy(policy, &declaration.selections[0]).unwrap(),
-                "{}",
-                policy.id
-            );
-            validate_imported_policy(policy, declaration).unwrap();
-        }
-
-        let valid = records[0];
-        let declaration = declarations[valid.source_record.as_deref().unwrap()];
-
-        let mut non_convergent = valid.clone();
-        non_convergent.convergent = false;
-        assert!(
-            validate_imported_policy(&non_convergent, declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("effects")
-        );
-
-        let mut typed_route = valid.clone();
-        typed_route.backend_lowerings[0].mechanism = BackendLoweringMechanism::TypedNvvm;
-        assert!(validate_imported_policy(&typed_route, declaration).is_err());
-
-        let mut selectionless = declaration.clone();
-        selectionless.selections.clear();
-        assert!(validate_imported_policy(valid, &selectionless).is_err());
-
-        let mut crossed_variant = valid.clone();
-        crossed_variant.register_mma.as_mut().unwrap().a_element = RegisterMmaElement::F16;
-        assert!(validate_imported_policy(&crossed_variant, declaration).is_err());
-
-        let generated = int8_records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_m16n8k16_s32_s8_u8_satfinite")
-            .unwrap();
-        let generated_declaration = declarations[generated.source_record.as_deref().unwrap()];
-
-        let mut wrong_stub_owner = generated.clone();
-        wrong_stub_owner
-            .register_mma
-            .as_mut()
-            .unwrap()
-            .compatibility_source = RegisterMmaCompatibilitySource::ExistingStub;
-        assert!(validate_imported_policy(&wrong_stub_owner, generated_declaration).is_err());
-
-        let mut wrong_b_element = generated.clone();
-        wrong_b_element.register_mma.as_mut().unwrap().b_element = RegisterMmaElement::S8;
-        assert!(validate_imported_policy(&wrong_b_element, generated_declaration).is_err());
-
-        let mut wrong_overflow = generated.clone();
-        wrong_overflow.register_mma.as_mut().unwrap().overflow = RegisterMmaOverflow::Wrapping;
-        assert!(validate_imported_policy(&wrong_overflow, generated_declaration).is_err());
-
-        let mut wrong_shape = generated.clone();
-        wrong_shape.register_mma.as_mut().unwrap().shape = RegisterMmaShape::M16n8k32;
-        assert!(validate_imported_policy(&wrong_shape, generated_declaration).is_err());
-
-        let mut wrong_adapter = generated.clone();
-        wrong_adapter.register_mma.as_mut().unwrap().adapter =
-            RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32;
-        assert!(validate_imported_policy(&wrong_adapter, generated_declaration).is_err());
-
-        let binary = binary_records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_m8n8k128_s32_b1_xor_popc")
-            .unwrap();
-        let binary_declaration = declarations[binary.source_record.as_deref().unwrap()];
-
-        let mut wrong_binary_operation = binary.clone();
-        wrong_binary_operation
-            .register_mma
-            .as_mut()
-            .unwrap()
-            .operation = RegisterMmaOperation::AndPopc;
-        assert!(validate_imported_policy(&wrong_binary_operation, binary_declaration).is_err());
-
-        let mut wrong_binary_floor = binary.clone();
-        wrong_binary_floor.minimum_sm = Some("sm_80".into());
-        assert!(validate_imported_policy(&wrong_binary_floor, binary_declaration).is_err());
-
-        let mut wrong_binary_element = binary.clone();
-        wrong_binary_element
-            .register_mma
-            .as_mut()
-            .unwrap()
-            .a_element = RegisterMmaElement::U4;
-        assert!(validate_imported_policy(&wrong_binary_element, binary_declaration).is_err());
-    }
-
-    #[test]
-    fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (mut overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        bind_pinned_abi_ids(&repo_root, &mut overlay);
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect();
-        let records = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| record.family == "sparse_mma")
-            .collect::<Vec<_>>();
-        assert_eq!(records.len(), 114);
-        assert_eq!(
-            records
-                .iter()
-                .map(|record| record.abi_id.clone())
-                .collect::<BTreeSet<_>>(),
-            (163..=251)
-                .chain(525..=549)
-                .map(|id| format!("i{id:04}"))
-                .collect::<BTreeSet<_>>()
-        );
-
-        let mut derived_ids = BTreeSet::new();
-        let mut derived_operation_keys = BTreeSet::new();
-        let mut derived_source_records = BTreeSet::new();
-        let mut derived_llvm_symbols = BTreeSet::new();
-        for record in &records {
-            let identity = &sparse_mma_recipe(record.sparse_mma.as_ref().unwrap())
-                .unwrap()
-                .identity;
-            assert_eq!(record.id, identity.id);
-            assert_eq!(record.operation_key, identity.operation_key);
-            assert_eq!(
-                record.source_record.as_deref(),
-                Some(identity.source_record.as_str())
-            );
-            assert_eq!(
-                record.llvm_symbol.as_deref(),
-                Some(identity.llvm_symbol.as_str())
-            );
-            assert_eq!(record.expected_ptx.modifiers, identity.ptx_modifiers);
-            assert!(derived_ids.insert(identity.id.clone()));
-            assert!(derived_operation_keys.insert(identity.operation_key.clone()));
-            assert!(derived_source_records.insert(identity.source_record.clone()));
-            assert!(derived_llvm_symbols.insert(identity.llvm_symbol.clone()));
-        }
-        assert_eq!(derived_ids.len(), 114);
-        assert_eq!(derived_operation_keys.len(), 114);
-        assert_eq!(derived_source_records.len(), 114);
-        assert_eq!(derived_llvm_symbols.len(), 114);
-
-        let integer_records = records
-            .iter()
-            .copied()
-            .filter(|record| {
-                record.sparse_mma.as_ref().unwrap().accumulator == SparseMmaAccumulator::S32
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(integer_records.len(), 64);
-        let f32_records = records
-            .iter()
-            .copied()
-            .filter(|record| {
-                record.sparse_mma.as_ref().unwrap().accumulator == SparseMmaAccumulator::F32
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(f32_records.len(), 25);
-        let f16_records = records
-            .iter()
-            .copied()
-            .filter(|record| {
-                record.sparse_mma.as_ref().unwrap().accumulator == SparseMmaAccumulator::F16
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(f16_records.len(), 25);
-
-        let variants = integer_records
-            .iter()
-            .map(|record| {
-                let mma = record.sparse_mma.as_ref().unwrap();
-                let carrier =
-                    sparse_mma_carrier_recipe(mma.shape, mma.a_element, mma.b_element).unwrap();
-                assert_eq!(mma.accumulator, SparseMmaAccumulator::S32);
-                assert_eq!(mma.selector, carrier.selector);
-                assert_eq!(mma.adapter, carrier.adapter);
-                assert_eq!(mma.llvm_adapter, carrier.llvm_adapter);
-                assert_eq!(record.rust_arguments, carrier.rust_arguments());
-                assert_eq!(record.dialect_operands, carrier.dialect_operands());
-                assert_eq!(record.llvm_arguments, carrier.llvm_arguments());
-                assert_eq!(
-                    record.expected_ptx.operands,
-                    carrier.expected_ptx_operands()
-                );
-                assert_eq!(record.minimum_ptx, sparse_mma_minimum_ptx(mma));
-                assert_eq!(record.minimum_sm.as_deref(), Some("sm_80"));
-                assert_eq!(
-                    record.expected_ptx.operands.last(),
-                    Some(&OperandPattern::Immediate)
-                );
-                assert_eq!(
-                    record.expected_ptx.modifiers.first().map(String::as_str),
-                    Some(match mma.metadata {
-                        SparseMmaMetadata::Standard => "sp",
-                        SparseMmaMetadata::Ordered => "sp::ordered_metadata",
-                    })
-                );
-                (
-                    mma.shape,
-                    mma.a_element,
-                    mma.b_element,
-                    mma.overflow,
-                    mma.metadata,
-                )
-            })
-            .collect::<BTreeSet<_>>();
-        let mut expected_variants = BTreeSet::new();
-        for shape in [SparseMmaShape::M16n8k32, SparseMmaShape::M16n8k64] {
-            let metadata = match shape {
-                SparseMmaShape::M16n8k32 => [
-                    Some(SparseMmaMetadata::Standard),
-                    Some(SparseMmaMetadata::Ordered),
-                ],
-                SparseMmaShape::M16n8k64 => [
-                    Some(SparseMmaMetadata::Standard),
-                    Some(SparseMmaMetadata::Ordered),
-                ],
-                SparseMmaShape::M16n8k128 => [None, None],
-            };
-            for a_element in [SparseMmaElement::S8, SparseMmaElement::U8] {
-                for b_element in [SparseMmaElement::S8, SparseMmaElement::U8] {
-                    for overflow in [SparseMmaOverflow::Wrapping, SparseMmaOverflow::Satfinite] {
-                        for metadata in metadata.into_iter().flatten() {
-                            expected_variants
-                                .insert((shape, a_element, b_element, overflow, metadata));
-                        }
-                    }
-                }
-            }
-        }
-        for shape in [SparseMmaShape::M16n8k64, SparseMmaShape::M16n8k128] {
-            for a_element in [SparseMmaElement::S4, SparseMmaElement::U4] {
-                for b_element in [SparseMmaElement::S4, SparseMmaElement::U4] {
-                    for overflow in [SparseMmaOverflow::Wrapping, SparseMmaOverflow::Satfinite] {
-                        for metadata in [SparseMmaMetadata::Standard, SparseMmaMetadata::Ordered] {
-                            expected_variants
-                                .insert((shape, a_element, b_element, overflow, metadata));
-                        }
-                    }
-                }
-            }
-        }
-        assert_eq!(variants, expected_variants);
-
-        let f8f6f4_formats = [
-            SparseMmaElement::E2m1,
-            SparseMmaElement::E2m3,
-            SparseMmaElement::E3m2,
-            SparseMmaElement::E4m3,
-            SparseMmaElement::E5m2,
-        ];
-        assert_eq!(
-            f32_records
-                .iter()
-                .map(|record| {
-                    let mma = record.sparse_mma.as_ref().unwrap();
-                    (mma.a_element, mma.b_element)
-                })
-                .collect::<BTreeSet<_>>(),
-            f8f6f4_formats
-                .into_iter()
-                .flat_map(|a| f8f6f4_formats.into_iter().map(move |b| (a, b)))
-                .collect()
-        );
-        assert_eq!(
-            f32_records
-                .iter()
-                .map(|record| record.abi_id.as_str())
-                .collect::<BTreeSet<_>>(),
-            (227..=251)
-                .map(|id| format!("i{id:04}"))
-                .collect::<BTreeSet<_>>()
-                .iter()
-                .map(String::as_str)
-                .collect()
-        );
-        assert_eq!(
-            f16_records
-                .iter()
-                .map(|record| {
-                    let mma = record.sparse_mma.as_ref().unwrap();
-                    (mma.a_element, mma.b_element)
-                })
-                .collect::<BTreeSet<_>>(),
-            f8f6f4_formats
-                .into_iter()
-                .flat_map(|a| f8f6f4_formats.into_iter().map(move |b| (a, b)))
-                .collect()
-        );
-        assert_eq!(
-            f16_records
-                .iter()
-                .map(|record| record.abi_id.as_str())
-                .collect::<BTreeSet<_>>(),
-            (525..=549)
-                .map(|id| format!("i{id:04}"))
-                .collect::<BTreeSet<_>>()
-                .iter()
-                .map(String::as_str)
-                .collect()
-        );
-        for record in &f32_records {
-            let mma = record.sparse_mma.as_ref().unwrap();
-            assert_eq!(mma.shape, SparseMmaShape::M16n8k64);
-            assert_eq!(mma.accumulator, SparseMmaAccumulator::F32);
-            assert_eq!(mma.overflow, SparseMmaOverflow::NotApplicable);
-            assert_eq!(mma.metadata, SparseMmaMetadata::Ordered);
-            assert_eq!(mma.selector, SparseMmaSelector::ImmediateZero);
-            assert_eq!(
-                mma.adapter,
-                SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32
-            );
-            assert_eq!(
-                mma.llvm_adapter,
-                SparseMmaLlvmAdapter::A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32
-            );
-            assert_eq!(
-                record.rust_arguments,
-                ["[f32; 4]", "[u32; 4]", "[u32; 4]", "u32", "u32"]
-            );
-            assert_eq!(record.rust_result, "[f32; 4]");
-            assert_eq!(
-                record.dialect_operands,
-                [
-                    "f32", "f32", "f32", "f32", "u32", "u32", "u32", "u32", "u32", "u32", "u32",
-                    "u32", "u32", "u32"
-                ]
-            );
-            assert_eq!(record.dialect_results, ["f32", "f32", "f32", "f32"]);
-            assert_eq!(
-                record.llvm_arguments,
-                [
-                    "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32",
-                    "f32", "i32", "i32"
-                ]
-            );
-            assert_eq!(record.llvm_results, ["f32", "f32", "f32", "f32"]);
-            assert_eq!(record.minimum_ptx, "8.7");
-            assert_eq!(record.minimum_sm, None);
-            // Same contract as the F16 accumulator: both float forms are gated
-            // on `hasMMABlockScale()`, so neither is narrower than the other.
-            assert_eq!(record.targets, SPARSE_MMA_F8F6F4_TARGETS);
-            assert_eq!(record.backend_lowerings.len(), 2);
-            assert!(record.backend_lowerings.iter().all(|lowering| {
-                lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    && lowering.minimum_ptx.as_deref() == Some("8.7")
-                    && lowering.minimum_sm.is_none()
-            }));
-            assert_eq!(
-                record.expected_ptx.operands,
-                [
-                    OperandPattern::RegisterList { length: 4 },
-                    OperandPattern::RegisterList { length: 4 },
-                    OperandPattern::RegisterList { length: 4 },
-                    OperandPattern::RegisterList { length: 4 },
-                    OperandPattern::Register,
-                    OperandPattern::Immediate,
-                ]
-            );
-        }
-
-        for record in &f16_records {
-            let mma = record.sparse_mma.as_ref().unwrap();
-            assert_eq!(mma.shape, SparseMmaShape::M16n8k64);
-            assert_eq!(mma.accumulator, SparseMmaAccumulator::F16);
-            assert_eq!(mma.overflow, SparseMmaOverflow::NotApplicable);
-            assert_eq!(mma.metadata, SparseMmaMetadata::Ordered);
-            assert_eq!(mma.selector, SparseMmaSelector::ImmediateZero);
-            assert_eq!(
-                mma.adapter,
-                SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32
-            );
-            assert_eq!(
-                mma.llvm_adapter,
-                SparseMmaLlvmAdapter::A4I32B4I32C2V2F16MetadataI32SelectorI32ToD2V2F16
-            );
-            assert_eq!(
-                record.rust_arguments,
-                ["[u32; 2]", "[u32; 4]", "[u32; 4]", "u32", "u32"]
-            );
-            assert_eq!(record.rust_result, "[u32; 2]");
-            assert_eq!(
-                record.dialect_operands,
-                [
-                    "i32", "i32", "u32", "u32", "u32", "u32", "u32", "u32", "u32", "u32", "u32",
-                    "u32"
-                ]
-            );
-            assert_eq!(record.dialect_results, ["i32", "i32"]);
-            assert_eq!(
-                record.llvm_arguments,
-                [
-                    "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "v2f16", "v2f16",
-                    "i32", "i32"
-                ]
-            );
-            assert_eq!(record.llvm_results, ["v2f16", "v2f16"]);
-            assert_eq!(record.minimum_ptx, "8.7");
-            assert_eq!(record.minimum_sm, None);
-            assert_eq!(record.targets, SPARSE_MMA_F8F6F4_TARGETS);
-            assert!(record.convergent && !record.pure);
-            assert!(record.backend_lowerings.iter().all(|lowering| {
-                lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                    && lowering.minimum_ptx.as_deref() == Some("8.7")
-                    && lowering.minimum_sm.is_none()
-            }));
-            assert_eq!(
-                record.expected_ptx.operands,
-                [
-                    OperandPattern::RegisterList { length: 2 },
-                    OperandPattern::RegisterList { length: 4 },
-                    OperandPattern::RegisterList { length: 4 },
-                    OperandPattern::RegisterList { length: 2 },
-                    OperandPattern::Register,
-                    OperandPattern::Immediate,
-                ]
-            );
-        }
-
-        for policy in &records {
-            let declaration = declarations[policy.source_record.as_deref().unwrap()];
-            assert_eq!(declaration.selections.len(), 1);
-            assert!(
-                selection_matches_policy(policy, &declaration.selections[0]).unwrap(),
-                "{}",
-                policy.id
-            );
-            validate_imported_policy(policy, declaration).unwrap();
-        }
-
-        let mut selectionless = declarations[records[0].source_record.as_deref().unwrap()].clone();
-        selectionless.selections.clear();
-        assert!(validate_imported_policy(records[0], &selectionless).is_err());
-
-        for (id, range_prefix, wrong_range) in [
-            ("mma_sp_m16n8k32_s32_s8", "Range<arg9", "Range<arg9,0,3>"),
-            ("mma_sp_m16n8k64_s32_s8", "Range<arg13", "Range<arg13,0,2>"),
-            (
-                "mma_sp_ordered_metadata_m16n8k64_s32_s4",
-                "Range<arg9",
-                "Range<arg9,0,1>",
-            ),
-            ("mma_sp_m16n8k64_s32_s4", "Range<arg9", "Range<arg9,0,1>"),
-            (
-                "mma_sp_ordered_metadata_m16n8k128_s32_s4",
-                "Range<arg13",
-                "Range<arg13,0,2>",
-            ),
-            ("mma_sp_m16n8k128_s32_s4", "Range<arg13", "Range<arg13,0,2>"),
-            (
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32",
-                "Range<arg13",
-                "Range<arg13,0,2>",
-            ),
-            (
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16",
-                "Range<arg11",
-                "Range<arg11,0,2>",
-            ),
-        ] {
-            let valid = records
-                .iter()
-                .copied()
-                .find(|record| record.id == id)
-                .unwrap();
-            let declaration = declarations[valid.source_record.as_deref().unwrap()];
-
-            let mut runtime_selector = valid.clone();
-            *runtime_selector.expected_ptx.operands.last_mut().unwrap() = OperandPattern::Register;
-            assert!(
-                validate_imported_policy(&runtime_selector, declaration)
-                    .unwrap_err()
-                    .to_string()
-                    .contains("exact selection")
-            );
-
-            let mut wrong_declaration = declaration.clone();
-            *wrong_declaration
-                .properties
-                .iter_mut()
-                .find(|property| property.starts_with(range_prefix))
-                .unwrap() = wrong_range.into();
-            assert!(
-                validate_imported_policy(valid, &wrong_declaration)
-                    .unwrap_err()
-                    .to_string()
-                    .contains("immediate range")
-            );
-        }
-
-        let k64 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_m16n8k64_s32_s8")
-            .unwrap();
-        let k64_declaration = declarations[k64.source_record.as_deref().unwrap()];
-        assert_eq!(k64.minimum_ptx, "7.1");
-        let ordered_k64 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k64_s32_s8")
-            .unwrap();
-        assert_eq!(ordered_k64.minimum_ptx, "8.5");
-
-        let f8f6f4 = f32_records[0];
-        let f8f6f4_declaration = declarations[f8f6f4.source_record.as_deref().unwrap()];
-        let mut widened_family = f8f6f4.clone();
-        widened_family.targets = "sm_120f".into();
-        assert!(validate_imported_policy(&widened_family, f8f6f4_declaration).is_err());
-        let mut widened_architecture = f8f6f4.clone();
-        widened_architecture.targets = "sm_121a".into();
-        assert!(validate_imported_policy(&widened_architecture, f8f6f4_declaration).is_err());
-
-        let f8f6f4_f16 = f16_records[0];
-        for block_scale in [f8f6f4, f8f6f4_f16] {
-            let mut missing_predicate =
-                declarations[block_scale.source_record.as_deref().unwrap()].clone();
-            missing_predicate.selections[0].predicates.clear();
-            assert!(
-                validate_imported_policy(block_scale, &missing_predicate)
-                    .unwrap_err()
-                    .to_string()
-                    .contains("exact selection")
-            );
-        }
-
-        let ordered_k64_int4 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k64_s32_s4")
-            .unwrap();
-        let ordered_k64_int4_declaration =
-            declarations[ordered_k64_int4.source_record.as_deref().unwrap()];
-        assert_eq!(ordered_k64_int4.minimum_ptx, "8.5");
-        assert_eq!(ordered_k64_int4.rust_arguments[1], "[u32; 2]");
-        assert_eq!(ordered_k64_int4.rust_arguments[2], "[u32; 2]");
-        assert_eq!(ordered_k64_int4.llvm_arguments.len(), 10);
-        assert_eq!(
-            ordered_k64_int4.sparse_mma.as_ref().unwrap().selector,
-            SparseMmaSelector::ImmediateZeroOrOne
-        );
-        assert_eq!(
-            ordered_k64_int4.sparse_mma.as_ref().unwrap().adapter,
-            SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32
-        );
-        assert_eq!(
-            ordered_k64_int4.sparse_mma.as_ref().unwrap().llvm_adapter,
-            SparseMmaLlvmAdapter::A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32
-        );
-        let standard_k64_int4 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_m16n8k64_s32_s4")
-            .unwrap();
-        assert_eq!(standard_k64_int4.minimum_ptx, "7.1");
-        assert_eq!(
-            standard_k64_int4.rust_arguments,
-            ordered_k64_int4.rust_arguments
-        );
-        assert_eq!(
-            standard_k64_int4.llvm_arguments,
-            ordered_k64_int4.llvm_arguments
-        );
-
-        let ordered_k128_int4 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k128_s32_s4")
-            .unwrap();
-        let ordered_k128_int4_declaration =
-            declarations[ordered_k128_int4.source_record.as_deref().unwrap()];
-        assert_eq!(ordered_k128_int4.minimum_ptx, "8.5");
-        assert_eq!(ordered_k128_int4.rust_arguments[1], "[u32; 4]");
-        assert_eq!(ordered_k128_int4.rust_arguments[2], "[u32; 4]");
-        assert_eq!(ordered_k128_int4.llvm_arguments.len(), 14);
-        assert_eq!(
-            ordered_k128_int4.sparse_mma.as_ref().unwrap().selector,
-            SparseMmaSelector::ImmediateZero
-        );
-        assert_eq!(
-            ordered_k128_int4.sparse_mma.as_ref().unwrap().adapter,
-            SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32
-        );
-        assert_eq!(
-            ordered_k128_int4.sparse_mma.as_ref().unwrap().llvm_adapter,
-            SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32
-        );
-        let standard_k128_int4 = records
-            .iter()
-            .copied()
-            .find(|record| record.id == "mma_sp_m16n8k128_s32_s4")
-            .unwrap();
-        assert_eq!(standard_k128_int4.minimum_ptx, "7.1");
-        assert_eq!(
-            standard_k128_int4.rust_arguments,
-            ordered_k128_int4.rust_arguments
-        );
-        assert_eq!(
-            standard_k128_int4.llvm_arguments,
-            ordered_k128_int4.llvm_arguments
-        );
-
-        let mut wrong_k128_selector = ordered_k128_int4.clone();
-        wrong_k128_selector.sparse_mma.as_mut().unwrap().selector =
-            SparseMmaSelector::ImmediateZeroOrOne;
-        assert!(
-            validate_imported_policy(&wrong_k128_selector, ordered_k128_int4_declaration).is_err()
-        );
-
-        let mut mixed_k128_width = ordered_k128_int4.clone();
-        mixed_k128_width.sparse_mma.as_mut().unwrap().b_element = SparseMmaElement::U8;
-        assert!(
-            validate_imported_policy(&mixed_k128_width, ordered_k128_int4_declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("unsupported sparse-MMA variant")
-        );
-
-        let mut mixed_width = ordered_k64_int4.clone();
-        mixed_width.sparse_mma.as_mut().unwrap().b_element = SparseMmaElement::U8;
-        assert!(
-            validate_imported_policy(&mixed_width, ordered_k64_int4_declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("unsupported sparse-MMA variant")
-        );
-
-        let mut wrong_k64_selector = k64.clone();
-        wrong_k64_selector.sparse_mma.as_mut().unwrap().selector =
-            SparseMmaSelector::ImmediateZeroOrOne;
-        assert!(validate_imported_policy(&wrong_k64_selector, k64_declaration).is_err());
-
-        let mut wrong_k64_adapter = k64.clone();
-        wrong_k64_adapter.sparse_mma.as_mut().unwrap().adapter =
-            SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32;
-        assert!(validate_imported_policy(&wrong_k64_adapter, k64_declaration).is_err());
-
-        let mut wrong_k64_llvm_adapter = k64.clone();
-        wrong_k64_llvm_adapter
-            .sparse_mma
-            .as_mut()
-            .unwrap()
-            .llvm_adapter = SparseMmaLlvmAdapter::A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32;
-        assert!(validate_imported_policy(&wrong_k64_llvm_adapter, k64_declaration).is_err());
-
-        let mut wrong_k64_shape = k64.clone();
-        wrong_k64_shape.sparse_mma.as_mut().unwrap().shape = SparseMmaShape::M16n8k32;
-        assert!(validate_imported_policy(&wrong_k64_shape, k64_declaration).is_err());
-
-        let mut wrong_k64_carriers = k64.clone();
-        wrong_k64_carriers.dialect_operands.pop();
-        assert!(validate_imported_policy(&wrong_k64_carriers, k64_declaration).is_err());
-
-        let mut wrong_k64_lowering = k64.clone();
-        wrong_k64_lowering.lowering = "generated_register_mma".into();
-        assert!(validate_imported_policy(&wrong_k64_lowering, k64_declaration).is_err());
-
-        let mut mismatched_metadata_identity = k64.clone();
-        mismatched_metadata_identity
-            .sparse_mma
-            .as_mut()
-            .unwrap()
-            .metadata = SparseMmaMetadata::Ordered;
-        assert!(validate_imported_policy(&mismatched_metadata_identity, k64_declaration).is_err());
-    }
-
-    #[test]
-    fn cp_async_copy_recipe_admits_only_classic_llvm_forms() {
-        let cases = [
-            (
-                CpAsyncCachePolicy::Ca,
-                CpAsyncCopySize::B4,
-                CpAsyncSourceSize::Full,
-                Some("cp_async_ca_4"),
-            ),
-            (
-                CpAsyncCachePolicy::Ca,
-                CpAsyncCopySize::B4,
-                CpAsyncSourceSize::Runtime,
-                Some("cp_async_ca_zfill_4"),
-            ),
-            (
-                CpAsyncCachePolicy::Ca,
-                CpAsyncCopySize::B8,
-                CpAsyncSourceSize::Full,
-                Some("cp_async_ca_8"),
-            ),
-            (
-                CpAsyncCachePolicy::Ca,
-                CpAsyncCopySize::B8,
-                CpAsyncSourceSize::Runtime,
-                Some("cp_async_ca_zfill_8"),
-            ),
-            (
-                CpAsyncCachePolicy::Ca,
-                CpAsyncCopySize::B16,
-                CpAsyncSourceSize::Full,
-                Some("cp_async_ca_16"),
-            ),
-            (
-                CpAsyncCachePolicy::Ca,
-                CpAsyncCopySize::B16,
-                CpAsyncSourceSize::Runtime,
-                Some("cp_async_ca_zfill_16"),
-            ),
-            (
-                CpAsyncCachePolicy::Cg,
-                CpAsyncCopySize::B4,
-                CpAsyncSourceSize::Full,
-                None,
-            ),
-            (
-                CpAsyncCachePolicy::Cg,
-                CpAsyncCopySize::B4,
-                CpAsyncSourceSize::Runtime,
-                None,
-            ),
-            (
-                CpAsyncCachePolicy::Cg,
-                CpAsyncCopySize::B8,
-                CpAsyncSourceSize::Full,
-                None,
-            ),
-            (
-                CpAsyncCachePolicy::Cg,
-                CpAsyncCopySize::B8,
-                CpAsyncSourceSize::Runtime,
-                None,
-            ),
-            (
-                CpAsyncCachePolicy::Cg,
-                CpAsyncCopySize::B16,
-                CpAsyncSourceSize::Full,
-                Some("cp_async_cg_16"),
-            ),
-            (
-                CpAsyncCachePolicy::Cg,
-                CpAsyncCopySize::B16,
-                CpAsyncSourceSize::Runtime,
-                Some("cp_async_cg_zfill_16"),
-            ),
-        ];
-
-        for (cache_policy, copy_size, source_size, expected) in cases {
-            let copy = crate::model::CpAsyncCopy {
-                cache_policy,
-                copy_size,
-                source_size,
-                adapter: if source_size == CpAsyncSourceSize::Runtime {
-                    CpAsyncAdapter::DirectPointersAndSourceSize
-                } else {
-                    CpAsyncAdapter::DirectPointers
-                },
-                runtime_validation: RuntimeValidation::Unexecuted,
-            };
-            assert_eq!(
-                cp_async_copy_recipe(&copy).map(|recipe| recipe.id),
-                expected
-            );
-        }
-    }
-
-    #[test]
-    fn pinned_cp_async_records_match_the_closed_recipes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect();
-        let policies: Vec<_> = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| matches!(record.family.as_str(), "cp_async_copy" | "cp_async_control"))
-            .collect();
-
-        assert_eq!(policies.len(), 11);
-        for policy in policies {
-            let declaration = declarations[policy.source_record.as_deref().unwrap()];
-            validate_imported_policy(policy, declaration).unwrap();
-        }
-    }
-
-    #[test]
-    fn pinned_cp_async_mbarrier_records_match_the_closed_recipes() {
-        let records = pinned_cp_async_mbarrier_records();
-        assert_eq!(records.len(), 4);
-
-        for (policy, declaration) in records.values() {
-            validate_imported_policy(policy, declaration).unwrap();
-        }
-    }
-
-    #[test]
-    fn cp_async_mbarrier_recipes_fail_closed() {
-        let records = pinned_cp_async_mbarrier_records();
-        let (arrive, declaration) = &records["cp_async_mbarrier_arrive"];
-        let reject =
-            |policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic, expected: &str| {
-                let error = validate_imported_policy(policy, declaration).unwrap_err();
-                let message = error.to_string();
-                assert!(message.contains(expected), "unexpected error: {message}");
-            };
-
-        let mut wrong_symbol = arrive.clone();
-        wrong_symbol.llvm_symbol = Some("llvm.nvvm.cp.async.mbarrier.changed".into());
-        reject(&wrong_symbol, declaration, "LLVM symbol mismatch");
-
-        let mut wrong_signature = arrive.clone();
-        wrong_signature.rust_arguments = vec!["*const u64".into()];
-        reject(
-            &wrong_signature,
-            declaration,
-            "closed cp.async mbarrier Rust API",
-        );
-
-        let mut wrong_operation = arrive.clone();
-        wrong_operation
-            .cp_async_mbarrier
-            .as_mut()
-            .unwrap()
-            .operation = CpAsyncMbarrierOperation::ArriveNoInc;
-        reject(&wrong_operation, declaration, "identity does not match");
-
-        let mut wrong_state_space = arrive.clone();
-        wrong_state_space
-            .cp_async_mbarrier
-            .as_mut()
-            .unwrap()
-            .state_space = CpAsyncMbarrierStateSpace::Shared;
-        reject(&wrong_state_space, declaration, "identity does not match");
-
-        let mut wrong_adapter = arrive.clone();
-        wrong_adapter.cp_async_mbarrier.as_mut().unwrap().adapter =
-            CpAsyncMbarrierAdapter::PointerToVoid;
-        wrong_adapter.rust_result = "u64".into();
-        reject(
-            &wrong_adapter,
-            declaration,
-            "closed cp.async mbarrier Rust API",
-        );
-
-        let mut executed_without_evidence = arrive.clone();
-        executed_without_evidence
-            .cp_async_mbarrier
-            .as_mut()
-            .unwrap()
-            .runtime_validation = RuntimeValidation::Executed;
-        reject(
-            &executed_without_evidence,
-            declaration,
-            "unrecorded cp.async mbarrier runtime validation",
-        );
-
-        let mut wrong_properties = declaration.clone();
-        wrong_properties.properties.pop();
-        reject(arrive, &wrong_properties, "cp.async mbarrier properties");
-
-        let mut wrong_selection = declaration.clone();
-        wrong_selection.selections[0].source_record = "CP_ASYNC_MBARRIER_CHANGED".into();
-        reject(
-            arrive,
-            &wrong_selection,
-            "imported cp.async mbarrier selection changed",
-        );
-
-        let mut wrong_floor = arrive.clone();
-        wrong_floor.minimum_sm = Some("sm_90".into());
-        reject(&wrong_floor, declaration, "effects or target floor");
-
-        let mut wrong_llvm_route = arrive.clone();
-        wrong_llvm_route
-            .backend_lowerings
-            .iter_mut()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-            .unwrap()
-            .mechanism = BackendLoweringMechanism::InlinePtx;
-        reject(&wrong_llvm_route, declaration, "reviewed typed-LLVM");
-
-        let mut wrong_lib_route = arrive.clone();
-        wrong_lib_route
-            .backend_lowerings
-            .iter_mut()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
-            .unwrap()
-            .mechanism = BackendLoweringMechanism::TypedNvvm;
-        reject(&wrong_lib_route, declaration, "reviewed typed-LLVM");
-
-        let mut mixed_family = arrive.clone();
-        mixed_family.cp_async_control = Some(crate::model::CpAsyncControl {
-            operation: CpAsyncControlOperation::CommitGroup,
-            adapter: CpAsyncControlAdapter::NoOperands,
-            runtime_validation: RuntimeValidation::Unexecuted,
-        });
-        reject(
-            &mixed_family,
-            declaration,
-            "mixes another generated-family contract",
-        );
-    }
-
-    #[test]
-    fn pinned_mbarrier_basic_records_match_the_closed_recipes() {
-        let records = pinned_mbarrier_basic_records();
-        assert_eq!(records.len(), 4);
-
-        for (policy, declaration) in records.values() {
-            validate_imported_policy(policy, declaration).unwrap();
-        }
-    }
-
-    #[test]
-    fn mbarrier_basic_recipes_fail_closed() {
-        let records = pinned_mbarrier_basic_records();
-        let (init, init_declaration) = &records["mbarrier_init"];
-        let reject =
-            |policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic, expected: &str| {
-                let error = validate_imported_policy(policy, declaration).unwrap_err();
-                let message = error.to_string();
-                assert!(message.contains(expected), "unexpected error: {message}");
-            };
-
-        let mut wrong_symbol = init.clone();
-        wrong_symbol.llvm_symbol = Some("llvm.nvvm.mbarrier.init.changed".into());
-        reject(&wrong_symbol, init_declaration, "LLVM symbol mismatch");
-
-        let mut wrong_signature = init.clone();
-        wrong_signature.rust_arguments = vec!["*mut u32".into(), "u32".into()];
-        reject(
-            &wrong_signature,
-            init_declaration,
-            "unsafe mbarrier raw and compatibility API",
-        );
-
-        let mut wrong_operation = init.clone();
-        wrong_operation.mbarrier_basic.as_mut().unwrap().operation = MbarrierBasicOperation::Arrive;
-        reject(
-            &wrong_operation,
-            init_declaration,
-            "operation, state space, and adapter disagree",
-        );
-
-        let mut wrong_adapter = init.clone();
-        wrong_adapter.mbarrier_basic.as_mut().unwrap().adapter =
-            MbarrierBasicAdapter::InvalPointerToVoid;
-        reject(
-            &wrong_adapter,
-            init_declaration,
-            "operation, state space, and adapter disagree",
-        );
-
-        let mut executed_without_evidence = init.clone();
-        executed_without_evidence
-            .mbarrier_basic
-            .as_mut()
-            .unwrap()
-            .runtime_validation = RuntimeValidation::Executed;
-        reject(
-            &executed_without_evidence,
-            init_declaration,
-            "unrecorded mbarrier runtime validation",
-        );
-
-        let mut wrong_properties = init_declaration.clone();
-        wrong_properties.properties.pop();
-        reject(init, &wrong_properties, "mbarrier properties");
-
-        let mut wrong_selection = init_declaration.clone();
-        wrong_selection.selections[0].source_record = "MBARRIER_INIT_CHANGED".into();
-        reject(
-            init,
-            &wrong_selection,
-            "imported mbarrier selection changed",
-        );
-
-        let mut wrong_ptx_floor = init.clone();
-        wrong_ptx_floor.minimum_ptx = "7.1".into();
-        reject(
-            &wrong_ptx_floor,
-            init_declaration,
-            "effects or target floor",
-        );
-
-        let mut wrong_sm_floor = init.clone();
-        wrong_sm_floor.minimum_sm = Some("sm_90".into());
-        reject(&wrong_sm_floor, init_declaration, "effects or target floor");
-
-        let mut wrong_llvm_route = init.clone();
-        wrong_llvm_route
-            .backend_lowerings
-            .iter_mut()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-            .unwrap()
-            .mechanism = BackendLoweringMechanism::InlinePtx;
-        reject(
-            &wrong_llvm_route,
-            init_declaration,
-            "reviewed mbarrier backend routes",
-        );
-
-        let mut wrong_lib_nvvm_route = init.clone();
-        wrong_lib_nvvm_route
-            .backend_lowerings
-            .iter_mut()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
-            .unwrap()
-            .mechanism = BackendLoweringMechanism::TypedNvvm;
-        reject(
-            &wrong_lib_nvvm_route,
-            init_declaration,
-            "reviewed mbarrier backend routes",
-        );
-
-        let mut route_with_unreviewed_floor = init.clone();
-        route_with_unreviewed_floor.backend_lowerings[0].minimum_sm = Some("sm_90".into());
-        reject(
-            &route_with_unreviewed_floor,
-            init_declaration,
-            "reviewed mbarrier backend routes",
-        );
-
-        let mut mixed_family = init.clone();
-        mixed_family.cp_async_control = Some(crate::model::CpAsyncControl {
-            operation: CpAsyncControlOperation::CommitGroup,
-            adapter: CpAsyncControlAdapter::NoOperands,
-            runtime_validation: RuntimeValidation::Unexecuted,
-        });
-        reject(
-            &mixed_family,
-            init_declaration,
-            "mixes another generated-family contract",
-        );
-    }
-
-    #[test]
-    fn pinned_active_mask_and_warp_match_recipes_resolve() {
-        let records = pinned_active_mask_and_warp_match_records();
-        assert_eq!(records.len(), 5);
-
-        for (policy, declaration) in records.values() {
-            validate_imported_policy(policy, declaration).unwrap();
-        }
-    }
-
-    #[test]
-    fn active_mask_and_warp_match_recipes_fail_closed() {
-        let records = pinned_active_mask_and_warp_match_records();
-        let reject =
-            |policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic, expected: &str| {
-                let error = validate_imported_policy(policy, declaration).unwrap_err();
-                let message = error.to_string();
-                assert!(message.contains(expected), "unexpected error: {message}");
-            };
-
-        let (active_mask, active_mask_declaration) = &records["active_mask"];
-        let mut wrong_identity = active_mask.clone();
-        wrong_identity.operation_key = "warp.active_mask.changed".into();
-        reject(
-            &wrong_identity,
-            active_mask_declaration,
-            "active-mask identity",
-        );
-
-        let mut wrong_effects = active_mask.clone();
-        wrong_effects.memory = "none".into();
-        reject(
-            &wrong_effects,
-            active_mask_declaration,
-            "active-mask effects or target floor",
-        );
-
-        let (match_any, match_any_declaration) = &records["match_any_sync"];
-        let mut wrong_adapter = match_any.clone();
-        wrong_adapter.warp_match.as_mut().unwrap().adapter =
-            WarpMatchAdapter::ProjectMaskDiscardPredicate;
-        reject(
-            &wrong_adapter,
-            match_any_declaration,
-            "warp-match participation, adapter, or encoding",
-        );
-
-        let (match_all, match_all_declaration) = &records["match_all_sync"];
-        let mut wrong_projection = match_all.clone();
-        wrong_projection.dialect_results.push("i1".into());
-        reject(
-            &wrong_projection,
-            match_all_declaration,
-            "two-operand warp-match lowering recipe",
-        );
-
-        let (match_any_i64, match_any_i64_declaration) = &records["match_any_i64_sync"];
-        let mut incomplete_selections = match_any_i64_declaration.clone();
-        incomplete_selections.selections.pop();
-        reject(
-            match_any_i64,
-            &incomplete_selections,
-            "exactly ii/ir/ri/rr selections",
-        );
-
-        let (match_all_i64, match_all_i64_declaration) = &records["match_all_i64_sync"];
-        let mut wrong_predicates = match_all_i64_declaration.clone();
-        wrong_predicates.selections[0].predicates[0] = "Subtarget->getPTXVersion() >= 61".into();
-        reject(
-            match_all_i64,
-            &wrong_predicates,
-            "PTX shape, predicates, or constraints",
-        );
-    }
-
-    #[test]
-    fn ptx_native_source_provenance_fails_closed() {
-        let mut mixed = packed_policy("packed_atomic_add_f16x2");
-        mixed.source_record = Some("invented_llvm_record".into());
-        assert!(
-            resolve_policy_source(&mixed)
-                .unwrap_err()
-                .to_string()
-                .contains("mixes tagged source provenance")
-        );
-
-        let mut fake_llvm = packed_policy("packed_atomic_add_f16x2");
-        fake_llvm.llvm_symbol = Some("llvm.fake.packed.atomic".into());
-        fake_llvm.llvm_arguments = vec!["ptr".into(), "i32".into()];
-        fake_llvm.llvm_results = vec!["i32".into()];
-        assert!(
-            validate_ptx_native_policy(&fake_llvm)
-                .unwrap_err()
-                .to_string()
-                .contains("must not invent LLVM source facts")
-        );
-
-        let mut wrong_instruction = packed_policy("packed_atomic_add_f16x2");
-        wrong_instruction.source = Some(IntrinsicSource::PtxNative {
-            instruction: "atom.global.add.noftz.bf16x2".into(),
-        });
-        assert!(
-            validate_ptx_native_policy(&wrong_instruction)
-                .unwrap_err()
-                .to_string()
-                .contains("does not match its packed format")
-        );
-
-        let mut wrong_kind = packed_policy("packed_atomic_add_f16x2");
-        wrong_kind.source = Some(IntrinsicSource::LlvmImported {
-            source_record: "invented_llvm_record".into(),
-        });
-        assert!(
-            validate_ptx_native_policy(&wrong_kind)
-                .unwrap_err()
-                .to_string()
-                .contains("source kind and imported declaration disagree")
-        );
-    }
-
-    #[test]
-    fn movmatrix_recipe_is_exact_and_fails_closed() {
-        let valid = movmatrix_policy();
-        validate_ptx_native_policy(&valid).unwrap();
-
-        let reject = |policy: &OverlayIntrinsic, expected: &str| {
-            let message = validate_ptx_native_policy(policy).unwrap_err().to_string();
-            assert!(message.contains(expected), "unexpected error: {message}");
-        };
-
-        let mut wrong_shape = valid.clone();
-        wrong_shape.expected_ptx.modifiers[2] = "m16n8".into();
-        reject(&wrong_shape, "closed movmatrix recipe");
-
-        let mut wrong_participation = valid.clone();
-        wrong_participation.convergent = false;
-        reject(&wrong_participation, "closed movmatrix recipe");
-
-        // A warp collective is not a function of its own operand, so the
-        // pure/no-memory pair every other collective avoids must stay rejected
-        // here too.
-        let mut wrong_purity = valid.clone();
-        wrong_purity.pure = true;
-        reject(&wrong_purity, "closed movmatrix recipe");
-
-        let mut wrong_memory = valid.clone();
-        wrong_memory.memory = "none".into();
-        reject(&wrong_memory, "closed movmatrix recipe");
-
-        let mut wrong_floor = valid.clone();
-        wrong_floor.backend_lowerings[0].minimum_ptx = Some("8.0".into());
-        reject(&wrong_floor, "exact movmatrix floor");
-
-        let mut mixed = valid;
-        mixed.warp_barrier = Some(crate::model::WarpBarrier {
-            participation:
-                WarpBarrierParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
-            legacy_pre_sm70: PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive,
-            adapter: WarpBarrierAdapter::DirectMemberMask,
-            mask_encoding: WarpBarrierMaskEncoding::RegisterOrImmediate,
-            memory_ordering: WarpBarrierMemoryOrdering::ParticipatingLanes,
-        });
-        reject(&mixed, "mixes another generated-family contract");
-    }
-
-    #[test]
-    fn packed_atomic_closed_semantics_reject_every_unreviewed_mutation() {
-        let valid = packed_policy("packed_atomic_add_f16x2");
-        validate_ptx_native_policy(&valid).unwrap();
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let overlay =
-            std::fs::read_to_string(repo_root.join("intrinsics/overlay/packed_atomic.toml"))
-                .unwrap();
-        for (field, accepted, rejected) in [
-            (
-                "state space",
-                "state_space = \"global\"",
-                "state_space = \"shared\"",
-            ),
-            (
-                "ordering",
-                "ordering = \"relaxed\"",
-                "ordering = \"acquire\"",
-            ),
-            ("scope", "scope = \"gpu\"", "scope = \"system\""),
-            (
-                "rounding",
-                "rounding = \"nearest_even\"",
-                "rounding = \"toward_zero\"",
-            ),
-            (
-                "subnormal",
-                "subnormal = \"preserve\"",
-                "subnormal = \"flush\"",
-            ),
-            (
-                "atomicity",
-                "atomicity = \"per_element\"",
-                "atomicity = \"coherent_pair\"",
-            ),
-            (
-                "pointer safety",
-                "pointer_contract = \"mutable_global_u32_aligned4\"",
-                "pointer_contract = \"unaligned\"",
-            ),
-            (
-                "mixed access safety",
-                "access_contract = \"no_mixed_whole_word_or_non_atomic_access\"",
-                "access_contract = \"mixed_access_allowed\"",
-            ),
-            (
-                "scope safety",
-                "scope_contract = \"racing_atomics_mutually_inclusive\"",
-                "scope_contract = \"scope_unchecked\"",
-            ),
-            (
-                "codegen",
-                "codegen_contract = \"exact_native_instruction\"",
-                "codegen_contract = \"semantic_equivalence\"",
-            ),
-        ] {
-            let mutated = overlay.replacen(accepted, rejected, 1);
-            let error = toml::from_str::<OverlayShardFile>(&mutated).unwrap_err();
-            assert!(
-                error
-                    .to_string()
-                    .contains(rejected.split(" = ").next().unwrap()),
-                "{field} mutation did not fail closed: {error}"
-            );
-        }
-
-        let mut safe = valid;
-        safe.safe = true;
-        safe.safe_allowlist_reason = Some("incorrectly claims no caller obligations".into());
-        assert!(
-            validate_ptx_native_policy(&safe)
-                .unwrap_err()
-                .to_string()
-                .contains("unsafe must-use packed atomic")
-        );
-    }
-
-    #[test]
-    fn redux_contract_validates_effects_participation_and_operand_adapter() {
-        let valid = redux_policy();
-        let imported = redux_declaration();
-        validate_imported_policy(&valid, &imported).unwrap();
-
-        assert_eq!(
-            valid.redux.as_ref().unwrap().adapter,
-            ReduxAdapter::MaskValueToSourceMemberMask
-        );
-
-        let mut missing_contract = valid.clone();
-        missing_contract.redux = None;
-        assert!(
-            validate_imported_policy(&missing_contract, &imported)
-                .unwrap_err()
-                .to_string()
-                .contains("closed redux contract")
-        );
-
-        let mut wrong_effect = valid.clone();
-        wrong_effect.memory = "none".into();
-        assert!(
-            validate_imported_policy(&wrong_effect, &imported)
-                .unwrap_err()
-                .to_string()
-                .contains("redux effects")
-        );
-
-        let mut missing_imported_effect = imported;
-        missing_imported_effect
-            .properties
-            .retain(|property| property != "IntrInaccessibleMemOnly");
-        assert!(
-            validate_imported_policy(&valid, &missing_imported_effect)
-                .unwrap_err()
-                .to_string()
-                .contains("memory and convergence effects")
-        );
-    }
-
-    #[test]
-    fn vote_modes_keep_exact_abi_identity_and_both_selection_encodings() {
-        for mode in [
-            VoteMode::All,
-            VoteMode::Any,
-            VoteMode::Ballot,
-            VoteMode::Uni,
-        ] {
-            let policy = vote_policy(mode);
-            let declaration = vote_declaration(mode);
-            validate_imported_policy(&policy, &declaration).unwrap();
-            assert_eq!(
-                policy.vote.as_ref().unwrap().legacy_pre_sm70,
-                PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive
-            );
-
-            let selected: Vec<_> = declaration
-                .selections
-                .iter()
-                .filter(|selection| selection_matches_policy(&policy, selection).unwrap())
-                .collect();
-            assert_eq!(selected.len(), 2);
-            assert!(selected.iter().any(|selection| {
-                selection.source_record == vote_recipe(mode).immediate_selection
-            }));
-            assert!(selected.iter().any(|selection| {
-                selection.source_record == vote_recipe(mode).register_selection
-            }));
-
-            let mut record = evidence();
-            record.id = policy.id.clone();
-            record.source_record = policy.source_record.clone();
-            record.llvm_symbol = policy.llvm_symbol.clone();
-            record.llvm_arguments = policy.llvm_arguments.clone();
-            record.llvm_results = policy.llvm_results.clone();
-            record.expected_ptx = policy.expected_ptx.clone();
-            let resolved = resolve_record(
-                &policy,
-                resolve_policy_source(&policy).unwrap(),
-                Some(&declaration),
-                &record,
-                "test",
-                "LLVM version test",
-                "0123456789abcdef",
-                vec![],
-                1,
-            )
-            .unwrap();
-            assert_eq!(resolved.selections.len(), 2);
-            assert_eq!(resolved.vote, policy.vote);
-        }
-    }
-
-    #[test]
-    fn vote_contract_rejects_unreviewed_identity_effect_and_selection_changes() {
-        let valid = vote_policy(VoteMode::All);
-        let declaration = vote_declaration(VoteMode::All);
-
-        let mut wrong_abi = valid.clone();
-        wrong_abi.abi_id = "i0041".into();
-        assert!(
-            validate_imported_policy(&wrong_abi, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("vote identity")
-        );
-
-        let mut safe = valid.clone();
-        safe.safe = true;
-        safe.safe_allowlist_reason = Some("incorrectly hides participation obligations".into());
-        assert!(
-            validate_imported_policy(&safe, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("unsafe must-use vote")
-        );
-
-        let mut wrong_memory = valid.clone();
-        wrong_memory.memory = "none".into();
-        assert!(
-            validate_imported_policy(&wrong_memory, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("vote effects")
-        );
-
-        let mut register_only_mask = valid.clone();
-        register_only_mask.expected_ptx.operands[2] = OperandPattern::Register;
-        assert!(
-            validate_imported_policy(&register_only_mask, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("expected PTX")
-        );
-
-        let mut one_selection = declaration.clone();
-        one_selection.selections.pop();
-        assert!(
-            validate_imported_policy(&valid, &one_selection)
-                .unwrap_err()
-                .to_string()
-                .contains("immediate/register selection pair")
-        );
-
-        let mut different_predicates = declaration;
-        different_predicates.selections[1].predicates[0] =
-            "Subtarget->getPTXVersion() >= 61".into();
-        assert!(
-            validate_imported_policy(&valid, &different_predicates)
-                .unwrap_err()
-                .to_string()
-                .contains("disagree on PTX shape")
-        );
-    }
-
-    #[test]
-    fn uni_vote_is_raw_only_while_existing_votes_keep_compatibility_paths() {
-        for mode in [VoteMode::All, VoteMode::Any, VoteMode::Ballot] {
-            assert_eq!(vote_policy(mode).compatibility_rust_paths.len(), 1);
-        }
-        let uni = vote_policy(VoteMode::Uni);
-        assert!(uni.compatibility_rust_paths.is_empty());
-
-        let mut invented_compatibility_path = uni.clone();
-        invented_compatibility_path.compatibility_rust_paths =
-            vec!["cuda_device::warp::uni_sync".into()];
-        assert!(
-            validate_imported_policy(
-                &invented_compatibility_path,
-                &vote_declaration(VoteMode::Uni),
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("reviewed compatibility path")
-        );
-    }
-
-    #[test]
-    fn warp_shuffle_variants_keep_exact_identity_clamp_and_eight_selections() {
-        for (mode, value_kind, clamp) in [
-            (WarpShuffleMode::Idx, WarpShuffleValueKind::I32, 31),
-            (WarpShuffleMode::Bfly, WarpShuffleValueKind::I32, 31),
-            (WarpShuffleMode::Down, WarpShuffleValueKind::I32, 31),
-            (WarpShuffleMode::Up, WarpShuffleValueKind::I32, 0),
-            (WarpShuffleMode::Idx, WarpShuffleValueKind::F32, 31),
-            (WarpShuffleMode::Bfly, WarpShuffleValueKind::F32, 31),
-            (WarpShuffleMode::Down, WarpShuffleValueKind::F32, 31),
-            (WarpShuffleMode::Up, WarpShuffleValueKind::F32, 0),
-        ] {
-            let policy = warp_shuffle_policy(mode, value_kind);
-            let declaration = warp_shuffle_declaration(mode, value_kind);
-            validate_imported_policy(&policy, &declaration).unwrap();
-
-            assert_eq!(policy.warp_shuffle.as_ref().unwrap().clamp, clamp);
-            assert_eq!(
-                declaration
-                    .selections
-                    .iter()
-                    .filter(|selection| selection_matches_policy(&policy, selection).unwrap())
-                    .count(),
-                8
-            );
-
-            let mut record = evidence();
-            record.id = policy.id.clone();
-            record.source_record = policy.source_record.clone();
-            record.llvm_symbol = policy.llvm_symbol.clone();
-            record.llvm_arguments = policy.llvm_arguments.clone();
-            record.llvm_results = policy.llvm_results.clone();
-            record.expected_ptx = policy.expected_ptx.clone();
-            let resolved = resolve_record(
-                &policy,
-                resolve_policy_source(&policy).unwrap(),
-                Some(&declaration),
-                &record,
-                "test",
-                "LLVM version test",
-                "0123456789abcdef",
-                vec![],
-                1,
-            )
-            .unwrap();
-            assert_eq!(resolved.selections.len(), 8);
-            assert_eq!(resolved.warp_shuffle, policy.warp_shuffle);
-        }
-    }
-
-    #[test]
-    fn pinned_warp_shuffle_records_match_the_closed_recipes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect();
-        let all_policies: Vec<_> = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| record.family == "warp_shuffle")
-            .collect();
-        assert_eq!(all_policies.len(), 12);
-        let native_policies: Vec<_> = all_policies
-            .iter()
-            .copied()
-            .filter(|record| record.source.is_some())
-            .collect();
-        assert_eq!(native_policies.len(), 4);
-        for policy in native_policies {
-            validate_ptx_native_policy(policy).unwrap();
-        }
-        let policies: Vec<_> = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| record.family == "warp_shuffle" && record.source_record.is_some())
-            .collect();
-        assert_eq!(policies.len(), 8);
-        for policy in policies {
-            let declaration = declarations[policy.source_record.as_deref().unwrap()];
-            validate_imported_policy(policy, declaration).unwrap();
-        }
-    }
-
-    #[test]
-    fn pinned_llvm_has_no_direct_i64_or_f64_shuffle_record() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let direct_64: Vec<_> = imported
-            .intrinsics
-            .iter()
-            .filter(|record| {
-                record.llvm_name.starts_with("llvm.nvvm.shfl")
-                    && (record.llvm_name.contains(".i64") || record.llvm_name.contains(".f64"))
-            })
-            .map(|record| record.llvm_name.as_str())
-            .collect();
-        assert!(
-            direct_64.is_empty(),
-            "unexpected LLVM records: {direct_64:?}"
-        );
-    }
-
-    #[test]
-    fn i64_warp_shuffle_recipes_are_exact_ptx_native_pairs() {
-        let cases = [
-            (
-                WarpShuffleMode::Idx,
-                "shuffle_u64_sync",
-                "i0058",
-                "warp.shuffle.sync.idx.i64",
-                "shfl.sync.idx.b32",
-                "idx",
-                31,
-                "ShflSyncIdxI64Op",
-                "nvvm.shfl_sync_idx_i64",
-            ),
-            (
-                WarpShuffleMode::Bfly,
-                "shuffle_xor_u64_sync",
-                "i0059",
-                "warp.shuffle.sync.bfly.i64",
-                "shfl.sync.bfly.b32",
-                "bfly",
-                31,
-                "ShflSyncBflyI64Op",
-                "nvvm.shfl_sync_bfly_i64",
-            ),
-            (
-                WarpShuffleMode::Down,
-                "shuffle_down_u64_sync",
-                "i0060",
-                "warp.shuffle.sync.down.i64",
-                "shfl.sync.down.b32",
-                "down",
-                31,
-                "ShflSyncDownI64Op",
-                "nvvm.shfl_sync_down_i64",
-            ),
-            (
-                WarpShuffleMode::Up,
-                "shuffle_up_u64_sync",
-                "i0061",
-                "warp.shuffle.sync.up.i64",
-                "shfl.sync.up.b32",
-                "up",
-                0,
-                "ShflSyncUpI64Op",
-                "nvvm.shfl_sync_up_i64",
-            ),
-        ];
-
-        for (mode, id, abi_id, operation_key, instruction, ptx_mode, clamp, op_type, op_name) in
-            cases
-        {
-            let policy = warp_shuffle_policy(mode, WarpShuffleValueKind::I64);
-            validate_ptx_native_policy(&policy).unwrap();
-
-            assert_eq!(policy.id, id);
-            assert_eq!(policy.abi_id, abi_id);
-            assert_eq!(policy.operation_key, operation_key);
-            assert_eq!(
-                policy.source,
-                Some(IntrinsicSource::PtxNative {
-                    instruction: instruction.into(),
-                })
-            );
-            assert!(policy.source_record.is_none());
-            assert!(policy.llvm_symbol.is_none());
-            assert!(policy.resolved_llvm_symbol.is_none());
-            assert!(policy.llvm_arguments.is_empty());
-            assert!(policy.llvm_results.is_empty());
-            assert_eq!(policy.rust_arguments, ["u32", "u64", "u32"]);
-            assert_eq!(policy.rust_result, "u64");
-            assert!(!policy.safe);
-            assert!(policy.must_use);
-            assert_eq!(policy.dialect_op_type, op_type);
-            assert_eq!(policy.dialect_op_name, op_name);
-            assert_eq!(policy.dialect_operands, ["i32", "i64", "i32"]);
-            assert_eq!(policy.dialect_results, ["i64"]);
-            assert_eq!(policy.lowering, "generated_warp_shuffle_i64_inline_ptx");
-
-            let shuffle = policy.warp_shuffle.as_ref().unwrap();
-            assert_eq!(shuffle.clamp, clamp);
-            assert_eq!(
-                shuffle.adapter,
-                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
-            );
-            assert_eq!(
-                shuffle.lane_encoding,
-                WarpShuffleOperandEncoding::RegisterOnly
-            );
-            assert_eq!(
-                shuffle.mask_encoding,
-                WarpShuffleOperandEncoding::RegisterOnly
-            );
-            assert_eq!(
-                policy.expected_ptx,
-                InstructionPattern::new(
-                    "shfl",
-                    &["sync", ptx_mode, "b32"],
-                    vec![
-                        OperandPattern::Exact { value: "lo".into() },
-                        OperandPattern::Exact { value: "lo".into() },
-                        OperandPattern::Register,
-                        OperandPattern::Exact {
-                            value: clamp.to_string(),
-                        },
-                        OperandPattern::Register,
-                    ],
-                )
-            );
-
-            let routes: BTreeMap<_, _> = policy
-                .backend_lowerings
-                .iter()
-                .map(|route| (route.backend, route))
-                .collect();
-            assert_eq!(routes.len(), 2);
-            for backend in [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm] {
-                assert_eq!(
-                    routes[&backend].mechanism,
-                    BackendLoweringMechanism::InlinePtx
-                );
-                assert_eq!(routes[&backend].minimum_ptx.as_deref(), Some("6.0"));
-            }
-            assert_eq!(
-                routes[&IntrinsicBackend::LlvmNvptx].minimum_sm.as_deref(),
-                Some("sm_30")
-            );
-            assert_eq!(
-                routes[&IntrinsicBackend::LibNvvm].minimum_sm.as_deref(),
-                Some("sm_75")
-            );
-
-            let mut record = evidence();
-            record.id = policy.id.clone();
-            record.source = policy.source.clone();
-            record.source_record = None;
-            record.llvm_symbol = None;
-            record.llvm_arguments.clear();
-            record.llvm_results.clear();
-            record.expected_ptx = policy.expected_ptx.clone();
-            let resolved = resolve_record(
-                &policy,
-                resolve_policy_source(&policy).unwrap(),
-                None,
-                &record,
-                "test",
-                "LLVM version test",
-                "0123456789abcdef",
-                vec![],
-                1,
-            )
-            .unwrap();
-            assert!(resolved.llvm.is_none());
-            assert!(resolved.selections.is_empty());
-            assert_eq!(resolved.warp_shuffle, policy.warp_shuffle);
-        }
-    }
-
-    #[test]
-    fn i64_warp_shuffle_contract_rejects_unreviewed_changes() {
-        let valid = warp_shuffle_policy(WarpShuffleMode::Idx, WarpShuffleValueKind::I64);
-        validate_ptx_native_policy(&valid).unwrap();
-
-        let reject = |policy: &OverlayIntrinsic, expected: &str| {
-            let error = validate_ptx_native_policy(policy).unwrap_err();
-            let message = error.to_string();
-            assert!(message.contains(expected), "unexpected error: {message}");
-        };
-
-        let mut fabricated_llvm = valid.clone();
-        fabricated_llvm.source = None;
-        fabricated_llvm.source_record = Some("int_nvvm_shfl_sync_idx_i64".into());
-        fabricated_llvm.llvm_symbol = Some("llvm.nvvm.shfl.sync.idx.i64".into());
-        fabricated_llvm.llvm_arguments =
-            vec!["i32".into(), "i64".into(), "i32".into(), "i32".into()];
-        fabricated_llvm.llvm_results = vec!["i64".into()];
-        reject(
-            &fabricated_llvm,
-            "source kind and imported declaration disagree",
-        );
-
-        let mut wrong_source = valid.clone();
-        wrong_source.source = Some(IntrinsicSource::PtxNative {
-            instruction: "shfl.sync.down.b32".into(),
-        });
-        reject(&wrong_source, "warp-shuffle identity");
-
-        let mut wrong_adapter = valid.clone();
-        wrong_adapter.warp_shuffle.as_mut().unwrap().adapter =
-            WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp;
-        reject(&wrong_adapter, "semantic or operand contract");
-
-        let mut wrong_mode = valid.clone();
-        wrong_mode.warp_shuffle.as_mut().unwrap().mode = WarpShuffleMode::Up;
-        wrong_mode.warp_shuffle.as_mut().unwrap().clamp = 0;
-        wrong_mode.expected_ptx.modifiers[1] = "up".into();
-        wrong_mode.expected_ptx.operands[3] = OperandPattern::Exact { value: "0".into() };
-        reject(&wrong_mode, "warp-shuffle identity");
-
-        let mut wrong_clamp = valid.clone();
-        wrong_clamp.warp_shuffle.as_mut().unwrap().clamp = 0;
-        reject(&wrong_clamp, "semantic or operand contract");
-
-        let mut broad_encoding = valid.clone();
-        broad_encoding.warp_shuffle.as_mut().unwrap().lane_encoding =
-            WarpShuffleOperandEncoding::RegisterOrImmediate;
-        reject(&broad_encoding, "semantic or operand contract");
-
-        let mut typed_backend = valid.clone();
-        typed_backend.backend_lowerings[0].mechanism = BackendLoweringMechanism::TypedNvvm;
-        reject(&typed_backend, "reviewed LLVM and libNVVM routes");
-
-        let mut wrong_native_floor = valid.clone();
-        wrong_native_floor.minimum_sm = Some("sm_70".into());
-        reject(&wrong_native_floor, "target floor");
-
-        let mut wrong_profile_floor = valid.clone();
-        wrong_profile_floor
-            .backend_lowerings
-            .iter_mut()
-            .find(|route| route.backend == IntrinsicBackend::LibNvvm)
-            .unwrap()
-            .minimum_sm = Some("sm_80".into());
-        reject(&wrong_profile_floor, "profile floor");
-
-        let mut safe = valid.clone();
-        safe.safe = true;
-        safe.safe_allowlist_reason = Some("incorrectly hides participation obligations".into());
-        reject(&safe, "unsafe must-use warp-shuffle");
-
-        let mut wrong_ptx = valid;
-        wrong_ptx.expected_ptx.operands[0] = OperandPattern::Register;
-        reject(&wrong_ptx, "closed shfl.sync recipe");
-    }
-
-    #[test]
-    fn warp_shuffle_contract_rejects_unreviewed_policy_changes() {
-        let valid = warp_shuffle_policy(WarpShuffleMode::Idx, WarpShuffleValueKind::I32);
-        let declaration = warp_shuffle_declaration(WarpShuffleMode::Idx, WarpShuffleValueKind::I32);
-
-        let reject_policy = |policy: &OverlayIntrinsic, expected: &str| {
-            let error = match validate_imported_policy(policy, &declaration) {
-                Ok(()) => panic!("{expected} mutation was accepted"),
-                Err(error) => error,
-            };
-            let message = error.to_string();
-            assert!(message.contains(expected), "unexpected error: {message}");
-        };
-
-        let mut wrong_identity = valid.clone();
-        wrong_identity.operation_key = "warp.shuffle.sync.idx.changed".into();
-        reject_policy(&wrong_identity, "warp-shuffle identity");
-
-        let mut safe = valid.clone();
-        safe.safe = true;
-        safe.safe_allowlist_reason = Some("incorrectly hides participation obligations".into());
-        reject_policy(&safe, "unsafe must-use warp-shuffle");
-
-        let mut wrong_signature = valid.clone();
-        wrong_signature.dialect_operands.pop();
-        reject_policy(&wrong_signature, "closed warp-shuffle lowering recipe");
-
-        let mut wrong_clamp = valid.clone();
-        wrong_clamp.warp_shuffle.as_mut().unwrap().clamp = 0;
-        reject_policy(&wrong_clamp, "semantic or operand contract");
-
-        let mut missing_contract = valid.clone();
-        missing_contract.warp_shuffle = None;
-        reject_policy(&missing_contract, "closed warp-shuffle contract");
-
-        let mut mixed_contract = valid.clone();
-        mixed_contract.vote = vote_policy(VoteMode::All).vote;
-        reject_policy(&mixed_contract, "mixes another generated-family contract");
-
-        let mut wrong_backend_floor = valid.clone();
-        wrong_backend_floor
-            .backend_lowerings
-            .iter_mut()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
-            .unwrap()
-            .minimum_sm = Some("sm_80".into());
-        reject_policy(&wrong_backend_floor, "profile floor");
-    }
-
-    #[test]
-    fn warp_shuffle_contract_rejects_selection_drift() {
-        let valid = warp_shuffle_policy(WarpShuffleMode::Down, WarpShuffleValueKind::F32);
-        let declaration =
-            warp_shuffle_declaration(WarpShuffleMode::Down, WarpShuffleValueKind::F32);
-        let reject = |declaration: &ImportedIntrinsic, expected: &str| {
-            let error = validate_imported_policy(&valid, declaration).unwrap_err();
-            let message = error.to_string();
-            assert!(message.contains(expected), "unexpected error: {message}");
-        };
-
-        let mut missing_selection = declaration.clone();
-        missing_selection.selections.pop();
-        reject(
-            &missing_selection,
-            "eight distinct operand-encoding selections",
-        );
-
-        let mut duplicate_selection = declaration.clone();
-        duplicate_selection.selections[7].source_record =
-            duplicate_selection.selections[0].source_record.clone();
-        reject(
-            &duplicate_selection,
-            "eight distinct operand-encoding selections",
-        );
-
-        let mut empty_selection_name = declaration.clone();
-        empty_selection_name.selections[7].source_record.clear();
-        reject(
-            &empty_selection_name,
-            "eight distinct operand-encoding selections",
-        );
-
-        let mut wrong_asm = declaration.clone();
-        wrong_asm.selections[0].asm =
-            "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;".into();
-        reject(&wrong_asm, "selections disagree on PTX shape");
-
-        let mut wrong_predicate = declaration.clone();
-        wrong_predicate.selections[0].predicates[0] = "Subtarget->getPTXVersion() >= 61".into();
-        reject(&wrong_predicate, "selections disagree on PTX shape");
-
-        let mut constrained = declaration;
-        constrained.selections[0]
-            .constraints
-            .immediate_bindings
-            .push(crate::model::ImportedImmediateBinding {
-                argument_index: 2,
-                value: 1,
-            });
-        reject(&constrained, "selections disagree on PTX shape");
-
-        let mut wrong_classes =
-            warp_shuffle_declaration(WarpShuffleMode::Down, WarpShuffleValueKind::F32);
-        wrong_classes.classes.pop();
-        reject(&wrong_classes, "class or effects");
-    }
-
-    #[test]
-    fn sync_threads_selects_only_the_fixed_immediate_barrier_recipe() {
-        let policy = sync_policy();
-        let declaration = sync_declaration();
-        validate_imported_policy(&policy, &declaration).unwrap();
-
-        let selected: Vec<_> = declaration
-            .selections
-            .iter()
-            .filter(|selection| selection_matches_policy(&policy, selection).unwrap())
-            .collect();
-        assert_eq!(selected.len(), 1);
-        assert_eq!(selected[0].source_record, "BARRIER_CTA_SYNC_ALIGNED_ALL_i");
-        assert_eq!(selected[0].asm, "bar.sync \t$i;");
-        assert!(policy.expected_ptx.matches("bar.sync 0;").unwrap());
-        assert!(!policy.expected_ptx.matches(&selected[0].asm).unwrap());
-        assert_eq!(policy.minimum_ptx, "1.0");
-        assert!(policy.minimum_sm.is_none());
-        let llvm_route = policy
-            .backend_lowerings
-            .iter()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-            .unwrap();
-        assert_eq!(llvm_route.minimum_ptx.as_deref(), Some("3.2"));
-        assert_eq!(llvm_route.minimum_sm.as_deref(), Some("sm_20"));
-
-        let resolved = resolve_record(
-            &policy,
-            resolve_policy_source(&policy).unwrap(),
-            Some(&declaration),
-            &sync_evidence(&policy),
-            "test",
-            "LLVM version test",
-            "0123456789abcdef",
-            vec![],
-            1,
-        )
-        .unwrap();
-        assert!(resolved.dialect.operands.is_empty());
-        assert!(resolved.dialect.results.is_empty());
-        assert_eq!(resolved.selections.len(), 1);
-        assert_eq!(
-            resolved.selections[0].source_record,
-            "BARRIER_CTA_SYNC_ALIGNED_ALL_i"
-        );
-    }
-
-    #[test]
-    fn sync_threads_recipe_rejects_unreviewed_selection_effect_and_floor_changes() {
-        let valid = sync_policy();
-        let declaration = sync_declaration();
-
-        let mut register_only = declaration.clone();
-        register_only
-            .selections
-            .retain(|selection| selection.source_record.ends_with("_r"));
-        assert!(
-            validate_imported_policy(&valid, &register_only)
-                .unwrap_err()
-                .to_string()
-                .contains("does not agree")
-        );
-
-        let mut wrong_properties = declaration.clone();
-        wrong_properties.properties.pop();
-        assert!(
-            validate_imported_policy(&valid, &wrong_properties)
-                .unwrap_err()
-                .to_string()
-                .contains("sync properties")
-        );
-
-        let mut wrong_source = valid.clone();
-        wrong_source.source_record = Some("int_nvvm_barrier0".into());
-        assert!(
-            validate_imported_policy(&wrong_source, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("sync identity")
-        );
-
-        let mut wrong_signature = valid.clone();
-        wrong_signature.llvm_arguments.clear();
-        assert!(
-            validate_imported_policy(&wrong_signature, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("LLVM argument signature mismatch")
-        );
-
-        let mut wrong_path = valid.clone();
-        wrong_path.compatibility_rust_paths.swap(0, 1);
-        assert!(
-            validate_imported_policy(&wrong_path, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("both cuda-device compatibility paths")
-        );
-
-        let mut safe = valid.clone();
-        safe.safe = true;
-        safe.safe_allowlist_reason = Some("incorrectly hides the participation contract".into());
-        assert!(
-            validate_imported_policy(&safe, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("unsafe sync_threads raw API")
-        );
-
-        let mut wrong_effect = valid.clone();
-        wrong_effect.memory = "none".into();
-        assert!(
-            validate_imported_policy(&wrong_effect, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("sync effects")
-        );
-
-        let mut native_floor = valid.clone();
-        native_floor.minimum_sm = Some("sm_75".into());
-        assert!(
-            validate_imported_policy(&native_floor, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("native target floor")
-        );
-
-        let mut missing_profile_floor = valid;
-        missing_profile_floor
-            .backend_lowerings
-            .iter_mut()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
-            .unwrap()
-            .minimum_sm = None;
-        assert!(
-            validate_imported_policy(&missing_profile_floor, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("profile floor")
-        );
-
-        let mut wrong_llvm_floor = sync_policy();
-        wrong_llvm_floor
-            .backend_lowerings
-            .iter_mut()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-            .unwrap()
-            .minimum_ptx = None;
-        assert!(
-            validate_imported_policy(&wrong_llvm_floor, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("profile floor")
-        );
-    }
-
-    #[test]
-    fn sync_mask_matches_the_closed_warp_barrier_recipe() {
-        let policy = warp_barrier_policy();
-        let declaration = warp_barrier_declaration();
-        validate_imported_policy(&policy, &declaration).unwrap();
-
-        let selected: Vec<_> = declaration
-            .selections
-            .iter()
-            .filter(|selection| selection_matches_policy(&policy, selection).unwrap())
-            .collect();
-        assert_eq!(selected.len(), 2);
-        assert_eq!(
-            selected
-                .iter()
-                .map(|selection| selection.source_record.as_str())
-                .collect::<BTreeSet<_>>(),
-            BTreeSet::from(["INT_BAR_WARP_SYNC_I", "INT_BAR_WARP_SYNC_R"])
-        );
-
-        let mut record = evidence();
-        record.id = policy.id.clone();
-        record.source_record = policy.source_record.clone();
-        record.llvm_symbol = policy.llvm_symbol.clone();
-        record.llvm_arguments = policy.llvm_arguments.clone();
-        record.llvm_results = policy.llvm_results.clone();
-        record.expected_ptx = policy.expected_ptx.clone();
-        let resolved = resolve_record(
-            &policy,
-            resolve_policy_source(&policy).unwrap(),
-            Some(&declaration),
-            &record,
-            "test",
-            "LLVM version test",
-            "0123456789abcdef",
-            vec![],
-            1,
-        )
-        .unwrap();
-        assert_eq!(resolved.selections.len(), 2);
-        assert_eq!(resolved.warp_barrier, policy.warp_barrier);
-    }
-
-    #[test]
-    fn sync_mask_recipe_rejects_unreviewed_contract_and_selection_changes() {
-        let valid = warp_barrier_policy();
-        let declaration = warp_barrier_declaration();
-
-        let mut wrong_identity = valid.clone();
-        wrong_identity.id = "bar_warp_sync".into();
-        assert!(
-            validate_imported_policy(&wrong_identity, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("warp-barrier identity")
-        );
-
-        let mut missing_contract = valid.clone();
-        missing_contract.warp_barrier = None;
-        assert!(
-            validate_imported_policy(&missing_contract, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("closed warp-barrier contract")
-        );
-
-        let mut safe_raw_api = valid.clone();
-        safe_raw_api.safe = true;
-        safe_raw_api.safe_allowlist_reason = Some("incorrectly hides participation rules".into());
-        assert!(
-            validate_imported_policy(&safe_raw_api, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("unsafe raw API")
-        );
-
-        let mut wrong_memory = valid.clone();
-        wrong_memory.memory = "none".into();
-        assert!(
-            validate_imported_policy(&wrong_memory, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("effects or target floor")
-        );
-
-        let mut register_only = valid.clone();
-        register_only.expected_ptx.operands[0] = OperandPattern::Register;
-        assert!(
-            validate_imported_policy(&register_only, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("expected PTX")
-        );
-
-        let mut one_selection = declaration.clone();
-        one_selection.selections.pop();
-        assert!(
-            validate_imported_policy(&valid, &one_selection)
-                .unwrap_err()
-                .to_string()
-                .contains("immediate/register selection pair")
-        );
-
-        let mut wrong_predicate = declaration.clone();
-        wrong_predicate.selections[1].predicates[0] = "Subtarget->getPTXVersion() >= 61".into();
-        assert!(
-            validate_imported_policy(&valid, &wrong_predicate)
-                .unwrap_err()
-                .to_string()
-                .contains("selections disagree")
-        );
-
-        let mut missing_libnvvm_floor = valid;
-        missing_libnvvm_floor
-            .backend_lowerings
-            .iter_mut()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
-            .unwrap()
-            .minimum_sm = None;
-        assert!(
-            validate_imported_policy(&missing_libnvvm_floor, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("profile floor")
-        );
-    }
-
-    #[test]
-    fn every_redux_variant_matches_its_closed_recipe() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        assert_eq!(imported.schema, IMPORTED_SCHEMA);
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect();
-        let redux: Vec<_> = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| record.family == "redux")
-            .collect();
-        assert_eq!(redux.len(), 16);
-
-        for policy in redux {
-            let declaration = declarations
-                .get(policy.source_record.as_deref().unwrap())
-                .unwrap();
-            validate_imported_policy(policy, declaration).unwrap();
-        }
-
-        let mut mismatched = packed_policy("redux_sync_min_u32");
-        mismatched.redux.as_mut().unwrap().operation = ReduxOperation::Umax;
-        let declaration = declarations["int_nvvm_redux_sync_umin"];
-        assert!(
-            validate_imported_policy(&mismatched, declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("closed operation recipe")
-        );
-    }
-
-    #[test]
-    fn every_dot_product_variant_matches_its_closed_recipe() {
-        let variants = [
-            (
-                DotProductOperation::Dp4a,
-                DotProductSignedness::Signed,
-                "dp4a_s32",
-                "int_nvvm_idp4a_s_s",
-                "integer.dot_product.dp4a.s32",
-            ),
-            (
-                DotProductOperation::Dp4a,
-                DotProductSignedness::Unsigned,
-                "dp4a_u32",
-                "int_nvvm_idp4a_u_u",
-                "integer.dot_product.dp4a.u32",
-            ),
-            (
-                DotProductOperation::Dp2a,
-                DotProductSignedness::Signed,
-                "dp2a_s32",
-                "int_nvvm_idp2a_s_s",
-                "integer.dot_product.dp2a.lo.s32",
-            ),
-            (
-                DotProductOperation::Dp2a,
-                DotProductSignedness::Unsigned,
-                "dp2a_u32",
-                "int_nvvm_idp2a_u_u",
-                "integer.dot_product.dp2a.lo.u32",
-            ),
-        ];
-
-        for (operation, signedness, id, source_record, operation_key) in variants {
-            let policy = dot_product_policy(operation, signedness);
-            let declaration = dot_product_declaration(operation, signedness);
-            assert_eq!(policy.id, id);
-            assert_eq!(policy.source_record.as_deref(), Some(source_record));
-            assert_eq!(policy.operation_key, operation_key);
-            validate_imported_policy(&policy, &declaration).unwrap();
-        }
-    }
-
-    #[test]
-    fn pinned_dot_product_records_match_the_reviewed_overlay() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect();
-        let dot_products: Vec<_> = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| record.family == "dotprod")
-            .collect();
-        assert_eq!(dot_products.len(), 4);
-
-        for policy in dot_products {
-            let declaration = declarations[policy.source_record.as_deref().unwrap()];
-            validate_imported_policy(policy, declaration).unwrap();
-            let selected: Vec<_> = declaration
-                .selections
-                .iter()
-                .filter(|selection| selection_matches_policy(policy, selection).unwrap())
-                .collect();
-            assert_eq!(selected.len(), 1);
-            if policy.id.starts_with("dp2a") {
-                assert_eq!(selected[0].constraints.immediate_bindings[0].value, 0);
-            }
-        }
-    }
-
-    #[test]
-    fn dp2a_selects_only_the_reviewed_low_half_binding() {
-        let policy = dot_product_policy(DotProductOperation::Dp2a, DotProductSignedness::Signed);
-        let declaration =
-            dot_product_declaration(DotProductOperation::Dp2a, DotProductSignedness::Signed);
-        let resolved = resolve_record(
-            &policy,
-            resolve_policy_source(&policy).unwrap(),
-            Some(&declaration),
-            &dot_product_evidence(&policy),
-            "test",
-            "LLVM version test",
-            "0123456789abcdef",
-            vec![],
-            1,
-        )
-        .unwrap();
-
-        assert_eq!(resolved.selections.len(), 1);
-        assert_eq!(resolved.selections[0].source_record, "DOT2_lo");
-        assert_eq!(
-            resolved.selections[0].constraints.immediate_bindings,
-            [crate::model::ImportedImmediateBinding {
-                argument_index: 2,
-                value: 0,
-            }]
-        );
-        assert_eq!(
-            resolved.dot_product.as_ref().unwrap().adapter,
-            DotProductAdapter::InsertLowHalfFalse
-        );
-
-        let mut wrong_binding = declaration;
-        wrong_binding.selections[1].constraints.immediate_bindings[0].value = -1;
-        let error = validate_imported_policy(&policy, &wrong_binding).unwrap_err();
-        assert!(error.to_string().contains("does not agree"));
-    }
-
-    #[test]
-    fn dot_product_recipe_rejects_unreviewed_api_and_adapter_changes() {
-        let valid = dot_product_policy(DotProductOperation::Dp2a, DotProductSignedness::Unsigned);
-        let declaration =
-            dot_product_declaration(DotProductOperation::Dp2a, DotProductSignedness::Unsigned);
-
-        let mut wrong_adapter = valid.clone();
-        wrong_adapter.dot_product.as_mut().unwrap().adapter =
-            DotProductAdapter::DirectThreeOperands;
-        assert!(
-            validate_imported_policy(&wrong_adapter, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("source adapter")
-        );
-
-        let mut must_use = valid.clone();
-        must_use.must_use = true;
-        assert!(
-            validate_imported_policy(&must_use, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("non-must-use")
-        );
-
-        let mut wrong_llvm_signature = valid;
-        wrong_llvm_signature.llvm_arguments = vec!["i32".into(); 3];
-        assert!(
-            validate_imported_policy(&wrong_llvm_signature, &declaration)
-                .unwrap_err()
-                .to_string()
-                .contains("LLVM argument signature mismatch")
-        );
-    }
-
-    #[test]
-    fn dot_product_target_predicate_is_closed_to_ptx50_and_sm61() {
-        let policy = dot_product_policy(DotProductOperation::Dp4a, DotProductSignedness::Signed);
-        let selection =
-            &dot_product_declaration(DotProductOperation::Dp4a, DotProductSignedness::Signed)
-                .selections[0];
-        validate_selected_target_predicates(&policy, selection).unwrap();
-
-        let mut wrong_ptx = policy.clone();
-        wrong_ptx.minimum_ptx = "5.1".into();
-        assert!(
-            validate_selected_target_predicates(&wrong_ptx, selection)
-                .unwrap_err()
-                .to_string()
-                .contains("minimum PTX")
-        );
-
-        let mut wrong_sm = policy;
-        wrong_sm.minimum_sm = Some("sm_60".into());
-        assert!(
-            validate_selected_target_predicates(&wrong_sm, selection)
-                .unwrap_err()
-                .to_string()
-                .contains("minimum SM")
-        );
-    }
-
-    #[test]
-    fn typed_evidence_accepts_direct_scalar_intrinsic_signatures() {
-        let policy = dot_product_policy(DotProductOperation::Dp2a, DotProductSignedness::Signed);
-        let mut record = dot_product_evidence(&policy);
-        validate_typed_llvm_evidence(&policy, &record).unwrap();
-
-        record.concrete_llvm_arguments.remove(2);
-        let error = validate_typed_llvm_evidence(&policy, &record).unwrap_err();
-        assert!(error.to_string().contains("resolved signature"));
-    }
-
-    #[test]
-    fn typed_evidence_maps_cluster_shared_pointers_to_address_space_seven() {
-        let mut policy =
-            dot_product_policy(DotProductOperation::Dp2a, DotProductSignedness::Signed);
-        let mut record = dot_product_evidence(&policy);
-        policy.llvm_arguments = vec![
-            "shared_cluster_ptr".into(),
-            "shared_ptr".into(),
-            "ptr".into(),
-        ];
-        record.concrete_llvm_arguments = vec![
-            "ptr addrspace(7)".into(),
-            "ptr addrspace(3)".into(),
-            "ptr".into(),
-        ];
-
-        validate_typed_llvm_evidence(&policy, &record).unwrap();
-    }
-
-    #[test]
-    fn packed_conversion_evidence_separates_llvm_declaration_facts_from_libnvvm() {
-        for (destination, result) in [
-            (PackedConversionDestinationFormat::Bf16x2, "v2bf16"),
-            (PackedConversionDestinationFormat::F16x2, "v2f16"),
-        ] {
-            let policy = packed_conversion_policy(
-                destination,
-                PackedConversionRounding::NearestEven,
-                PackedConversionSaturation::None,
-            );
-            let llvm = policy
-                .backend_lowerings
-                .iter()
-                .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-                .unwrap();
-            let mut record = packed_conversion_evidence(&policy);
-            record.status = "validated".into();
-            record.stages = [
-                EvidenceStageKind::DeclarationCanonicalization,
-                EvidenceStageKind::BackendCodegen,
-                EvidenceStageKind::PtxAssembly,
-            ]
-            .into_iter()
-            .map(|stage| {
-                evidence_stage(
-                    stage,
-                    BackendLoweringMechanism::TypedNvvm,
-                    &["sm_80", "ptx70"],
-                )
-            })
-            .collect();
-            let assembly = record
-                .stages
-                .iter_mut()
-                .find(|stage| stage.stage == EvidenceStageKind::PtxAssembly)
-                .unwrap();
-            assembly.tool_path = Some("/usr/local/cuda/bin/ptxas".into());
-            assembly.tool_version = Some("CUDA 13.3 V13.3.33".into());
-            assembly.tool_sha256 =
-                Some("7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb".into());
-            assert_eq!(record.concrete_llvm_results, [result]);
-            validate_packed_conversion_backend_evidence(&policy, &record, llvm).unwrap();
-
-            let mut lowered = record.clone();
-            lowered.status = "lowered".into();
-            let error =
-                validate_packed_conversion_backend_evidence(&policy, &lowered, llvm).unwrap_err();
-            assert!(
-                error.to_string().contains("validated evidence status"),
-                "{error:#}"
-            );
-
-            for required in [
-                EvidenceStageKind::DeclarationCanonicalization,
-                EvidenceStageKind::BackendCodegen,
-                EvidenceStageKind::PtxAssembly,
-            ] {
-                let mut missing = record.clone();
-                missing.stages.retain(|stage| stage.stage != required);
-                let error = validate_packed_conversion_backend_evidence(&policy, &missing, llvm)
-                    .unwrap_err();
-                assert!(
-                    error
-                        .to_string()
-                        .contains("successful auxiliary typed-NVVM"),
-                    "{error:#}"
-                );
-
-                let mut failed = record.clone();
-                failed
-                    .stages
-                    .iter_mut()
-                    .find(|stage| stage.stage == required)
-                    .unwrap()
-                    .outcome = "failed".into();
-                let error = validate_packed_conversion_backend_evidence(&policy, &failed, llvm)
-                    .unwrap_err();
-                assert!(
-                    error
-                        .to_string()
-                        .contains("successful auxiliary typed-NVVM"),
-                    "{error:#}"
-                );
-
-                let mut wrong_mechanism = record.clone();
-                wrong_mechanism
-                    .stages
-                    .iter_mut()
-                    .find(|stage| stage.stage == required)
-                    .unwrap()
-                    .mechanism = Some(BackendLoweringMechanism::InlinePtx);
-                let error =
-                    validate_packed_conversion_backend_evidence(&policy, &wrong_mechanism, llvm)
-                        .unwrap_err();
-                assert!(
-                    error
-                        .to_string()
-                        .contains("successful auxiliary typed-NVVM"),
-                    "{error:#}"
-                );
-            }
-
-            let mut missing_tool_identity = record.clone();
-            missing_tool_identity
-                .stages
-                .iter_mut()
-                .find(|stage| stage.stage == EvidenceStageKind::PtxAssembly)
-                .unwrap()
-                .tool_sha256 = None;
-            let error =
-                validate_packed_conversion_backend_evidence(&policy, &missing_tool_identity, llvm)
-                    .unwrap_err();
-            assert!(
-                error.to_string().contains("exact tool identity"),
-                "{error:#}"
-            );
-
-            for stage_kind in [
-                EvidenceStageKind::BackendCodegen,
-                EvidenceStageKind::PtxAssembly,
-            ] {
-                let mut wrong_floor = record.clone();
-                wrong_floor
-                    .stages
-                    .iter_mut()
-                    .find(|stage| stage.stage == stage_kind)
-                    .unwrap()
-                    .targets = vec!["sm_75".into(), "ptx70".into()];
-                let error =
-                    validate_packed_conversion_backend_evidence(&policy, &wrong_floor, llvm)
-                        .unwrap_err();
-                assert!(
-                    error.to_string().contains("catalog floor sm_80"),
-                    "{error:#}"
-                );
-            }
-
-            record.declaration_attributes_canonicalized = None;
-            let error =
-                validate_packed_conversion_backend_evidence(&policy, &record, llvm).unwrap_err();
-            assert!(
-                error
-                    .to_string()
-                    .contains("canonical declaration attributes")
-            );
-        }
-
-        let policy = packed_conversion_policy(
-            PackedConversionDestinationFormat::Bf16x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::None,
-        );
-        let libnvvm = policy
-            .backend_lowerings
-            .iter()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
-            .unwrap();
-        let mut record = packed_conversion_evidence(&policy);
-        record.concrete_llvm_arguments.clear();
-        record.concrete_llvm_results.clear();
-        record.declaration_attributes_canonicalized = None;
-        validate_packed_conversion_backend_evidence(&policy, &record, libnvvm).unwrap();
-
-        record.concrete_llvm_arguments = policy.llvm_arguments.clone();
-        let error =
-            validate_packed_conversion_backend_evidence(&policy, &record, libnvvm).unwrap_err();
-        assert!(
-            error
-                .to_string()
-                .contains("must not claim typed LLVM support")
-        );
-
-        record.concrete_llvm_arguments.clear();
-        record.stages.push(evidence_stage(
-            EvidenceStageKind::BackendCodegen,
-            BackendLoweringMechanism::TypedNvvm,
-            &["sm_80", "ptx70"],
-        ));
-        let error =
-            validate_packed_conversion_backend_evidence(&policy, &record, libnvvm).unwrap_err();
-        assert!(
-            error
-                .to_string()
-                .contains("must not claim typed LLVM support")
-        );
-    }
-
-    #[test]
-    fn duplicate_identity_surfaces_are_rejected_independently() {
-        let first = policy();
-
-        let mut second = distinct_policy();
-        second.abi_id = first.abi_id.clone();
-        assert!(
-            validate_unique_overlay(&[first.clone(), second], 1)
-                .unwrap_err()
-                .to_string()
-                .contains("duplicate intrinsic ABI ID")
-        );
-
-        let mut second = distinct_policy();
-        second.operation_key = first.operation_key.clone();
-        assert!(
-            validate_unique_overlay(&[first.clone(), second], 1)
-                .unwrap_err()
-                .to_string()
-                .contains("duplicate intrinsic operation key")
-        );
-
-        let mut second = distinct_policy();
-        second.public_rust_path = first.public_rust_path.clone();
-        assert!(
-            validate_unique_overlay(&[first.clone(), second], 1)
-                .unwrap_err()
-                .to_string()
-                .contains("duplicate public Rust path")
-        );
-
-        let mut second = distinct_policy();
-        second.dialect_op_name = first.dialect_op_name.clone();
-        assert!(
-            validate_unique_overlay(&[first.clone(), second], 1)
-                .unwrap_err()
-                .to_string()
-                .contains("duplicate dialect op variant")
-        );
-
-        let mut second = distinct_policy();
-        second.llvm_symbol = first.llvm_symbol.clone();
-        assert!(
-            validate_unique_overlay(&[first, second], 1)
-                .unwrap_err()
-                .to_string()
-                .contains("duplicate LLVM symbol")
-        );
-    }
-
-    #[test]
-    fn signature_and_evidence_mismatches_are_rejected() {
-        let mut imported = declaration();
-        imported.results = vec!["i64".into()];
-        assert!(
-            validate_imported_policy(&policy(), &imported)
-                .unwrap_err()
-                .to_string()
-                .contains("LLVM result signature mismatch")
-        );
-
-        let mut backend_evidence = evidence();
-        backend_evidence.llvm_results = vec!["i64".into()];
-        assert!(
-            validate_test_evidence(&policy(), backend_evidence)
-                .unwrap_err()
-                .to_string()
-                .contains("evidence signature mismatch")
-        );
-
-        let mut backend_evidence = evidence();
-        backend_evidence.expected_ptx = sreg_pattern("%tid.y");
-        assert!(
-            validate_test_evidence(&policy(), backend_evidence)
-                .unwrap_err()
-                .to_string()
-                .contains("evidence PTX expectation mismatch")
-        );
-    }
-
-    #[test]
-    fn validated_llvm_evidence_requires_exact_ptxas_identity() {
-        let mut record = evidence();
-        record.status = "validated".into();
-        record.stages.push(crate::model::EvidenceStage {
-            targets: vec!["sm_75".into()],
-            representation: "probe PTX".into(),
-            stage: EvidenceStageKind::PtxAssembly,
-            mechanism: Some(BackendLoweringMechanism::TypedNvvm),
-            outcome: "succeeded".into(),
-            detail: "accepted".into(),
-            artifact_kind: None,
-            tool_path: Some("/usr/local/cuda/bin/ptxas".into()),
-            tool_version: Some("CUDA 13.3 V13.3.33".into()),
-            tool_sha256: Some(
-                "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb".into(),
-            ),
-        });
-        assert!(has_valid_ptx_assembly_stage(
-            &record,
-            BackendLoweringMechanism::TypedNvvm
-        ));
-
-        let stage = record.stages.last_mut().unwrap();
-        stage.tool_path = None;
-        assert!(!has_valid_ptx_assembly_stage(
-            &record,
-            BackendLoweringMechanism::TypedNvvm
-        ));
-        record.stages.clear();
-        assert!(!has_valid_ptx_assembly_stage(
-            &record,
-            BackendLoweringMechanism::TypedNvvm
-        ));
-    }
-
-    #[test]
-    fn validated_libnvvm_evidence_requires_a_real_cubin_terminal() {
-        let mut record = evidence();
-        record.stages.push(crate::model::EvidenceStage {
-            targets: vec!["sm_90".into(), "ptx78".into()],
-            representation: "linked output".into(),
-            stage: EvidenceStageKind::DeviceLink,
-            mechanism: Some(BackendLoweringMechanism::InlinePtx),
-            outcome: "succeeded".into(),
-            detail: "test".into(),
-            artifact_kind: None,
-            tool_path: Some("/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33".into()),
-            tool_version: Some("V13.3.33".into()),
-            tool_sha256: Some(
-                "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8".into(),
-            ),
-        });
-        assert!(!has_valid_cubin_device_link_stage(
-            &record,
-            BackendLoweringMechanism::InlinePtx
-        ));
-        record.stages[0].artifact_kind = Some(EvidenceArtifactKind::Cubin);
-        assert!(has_valid_cubin_device_link_stage(
-            &record,
-            BackendLoweringMechanism::InlinePtx
-        ));
-    }
-
-    fn evidence_stage(
-        stage: EvidenceStageKind,
-        mechanism: BackendLoweringMechanism,
-        targets: &[&str],
-    ) -> crate::model::EvidenceStage {
-        crate::model::EvidenceStage {
-            targets: targets.iter().map(|target| (*target).into()).collect(),
-            representation: "test".into(),
-            stage,
-            mechanism: Some(mechanism),
-            outcome: "succeeded".into(),
-            detail: "test".into(),
-            artifact_kind: None,
-            tool_path: None,
-            tool_version: None,
-            tool_sha256: None,
-        }
-    }
-
-    #[test]
-    fn backend_stage_targets_and_executed_status_are_monotonic() {
-        let mut target_policy = policy();
-        target_policy.minimum_ptx = "6.5".into();
-        target_policy.minimum_sm = Some("sm_75".into());
-        let lowering = crate::model::OverlayBackendLowering {
-            backend: IntrinsicBackend::LlvmNvptx,
-            mechanism: BackendLoweringMechanism::TypedNvvm,
-            evidence_profile: "test".into(),
-            targets: None,
-            minimum_ptx: None,
-            minimum_sm: None,
-        };
-        let mut record = evidence();
-        record.status = "validated".into();
-        record.runtime_validation = Some(RuntimeValidation::Unexecuted);
-        record.stages = vec![
-            evidence_stage(
-                EvidenceStageKind::BackendCodegen,
-                BackendLoweringMechanism::TypedNvvm,
-                &["sm_75", "ptx65"],
-            ),
-            evidence_stage(
-                EvidenceStageKind::PtxAssembly,
-                BackendLoweringMechanism::TypedNvvm,
-                &["sm_75", "ptx65"],
-            ),
-        ];
-        validate_selected_stage_targets(&target_policy, &record, &lowering).unwrap();
-
-        record.stages[0].targets = vec!["sm_75a".into(), "ptx65".into()];
-        assert!(validate_selected_stage_targets(&target_policy, &record, &lowering).is_err());
-        record.stages[0].targets = vec!["sm_75".into(), "ptx65".into()];
-
-        record.stages[1].targets = vec!["sm_80".into(), "ptx65".into()];
-        validate_selected_stage_targets(&target_policy, &record, &lowering).unwrap();
-
-        record.stages[1].targets = vec!["sm_90a".into(), "ptx65".into()];
-        validate_selected_stage_targets(&target_policy, &record, &lowering).unwrap();
-
-        record.stages[1].targets = vec!["sm_74".into(), "ptx65".into()];
-        assert!(
-            validate_selected_stage_targets(&target_policy, &record, &lowering)
-                .unwrap_err()
-                .to_string()
-                .contains("catalog floor sm_75")
-        );
-
-        record.stages[1].targets = vec!["sm_75".into(), "ptx65".into()];
-        record.status = "executed".into();
-        record.runtime_validation = Some(RuntimeValidation::Executed);
-        assert!(
-            validate_selected_stage_targets(&target_policy, &record, &lowering)
-                .unwrap_err()
-                .to_string()
-                .contains("runtime stage")
-        );
-    }
-
-    #[test]
-    fn exact_and_family_evidence_targets_match_at_every_stage() {
-        let lowering = crate::model::OverlayBackendLowering {
-            backend: IntrinsicBackend::LlvmNvptx,
-            mechanism: BackendLoweringMechanism::InlinePtx,
-            evidence_profile: "test".into(),
-            targets: None,
-            minimum_ptx: None,
-            minimum_sm: None,
-        };
-
-        for (target, wrong_targets) in [
-            ("sm_120a", ["sm_120", "sm_120f", "sm_121a"]),
-            ("sm_120f", ["sm_120", "sm_120a", "sm_121f"]),
-        ] {
-            let mut target_policy = policy();
-            target_policy.minimum_ptx = "8.7".into();
-            target_policy.targets = target.into();
-            let mut record = evidence();
-            record.status = "validated".into();
-            record.runtime_validation = Some(RuntimeValidation::Unexecuted);
-            record.stages = vec![
-                evidence_stage(
-                    EvidenceStageKind::BackendCodegen,
-                    BackendLoweringMechanism::InlinePtx,
-                    &[target, "ptx87"],
-                ),
-                evidence_stage(
-                    EvidenceStageKind::PtxAssembly,
-                    BackendLoweringMechanism::InlinePtx,
-                    &[target, "ptx87"],
-                ),
-            ];
-            validate_selected_stage_targets(&target_policy, &record, &lowering).unwrap();
-
-            for wrong in wrong_targets {
-                record.stages[0].targets = vec![wrong.into(), "ptx87".into()];
-                let error = validate_selected_stage_targets(&target_policy, &record, &lowering)
-                    .unwrap_err()
-                    .to_string();
-                assert!(error.contains(target), "{error}");
-            }
-            record.stages[0].targets = vec![target.into(), "ptx87".into()];
-            for wrong in wrong_targets {
-                record.stages[1].targets = vec![wrong.into(), "ptx87".into()];
-                let error = validate_selected_stage_targets(&target_policy, &record, &lowering)
-                    .unwrap_err()
-                    .to_string();
-                assert!(error.contains(target), "{error}");
-            }
-        }
-    }
-
-    #[test]
-    fn suffixed_evidence_target_spellings_are_normalized() {
-        for target in ["sm_120a", "compute_120a", "sm_120f", "compute_120f"] {
-            assert!(is_normalized_stage_target(target), "{target}");
-        }
-        for target in ["sm_120", "compute_120", "ptx87"] {
-            assert!(is_normalized_stage_target(target), "{target}");
-        }
-        for target in ["sm_0120a", "sm_120af", "sm_120x", "compute_120A"] {
-            assert!(!is_normalized_stage_target(target), "{target}");
-        }
-    }
-
-    #[test]
-    fn libnvvm_stage_may_report_newer_ptx_than_the_native_instruction_floor() {
-        let mut target_policy = policy();
-        target_policy.minimum_ptx = "1.0".into();
-        target_policy.minimum_sm = None;
-        let lowering = crate::model::OverlayBackendLowering {
-            backend: IntrinsicBackend::LibNvvm,
-            mechanism: BackendLoweringMechanism::InlinePtx,
-            evidence_profile: "test".into(),
-            targets: None,
-            minimum_ptx: None,
-            minimum_sm: Some("sm_75".into()),
-        };
-        let mut record = evidence();
-        record.stages = vec![evidence_stage(
-            EvidenceStageKind::BackendCodegen,
-            BackendLoweringMechanism::InlinePtx,
-            &["sm_75", "ptx93"],
-        )];
-        validate_selected_stage_targets(&target_policy, &record, &lowering).unwrap();
-
-        record.stages[0].targets = vec!["sm_75".into(), "ptx09".into()];
-        assert!(
-            validate_selected_stage_targets(&target_policy, &record, &lowering)
-                .unwrap_err()
-                .to_string()
-                .contains("catalog floor sm_75 / PTX 1.0")
-        );
-
-        let llvm_lowering = crate::model::OverlayBackendLowering {
-            backend: IntrinsicBackend::LlvmNvptx,
-            mechanism: BackendLoweringMechanism::TypedNvvm,
-            evidence_profile: "test".into(),
-            targets: None,
-            minimum_ptx: Some("3.2".into()),
-            minimum_sm: Some("sm_20".into()),
-        };
-        record.stages = vec![evidence_stage(
-            EvidenceStageKind::BackendCodegen,
-            BackendLoweringMechanism::TypedNvvm,
-            &["sm_20", "ptx93"],
-        )];
-        assert!(
-            validate_selected_stage_targets(&target_policy, &record, &llvm_lowering)
-                .unwrap_err()
-                .to_string()
-                .contains("catalog floor sm_20 / PTX 3.2")
-        );
-    }
-
-    #[test]
-    fn imported_selection_must_match_the_full_ptx_shape() {
-        let mut imported = declaration();
-        imported.selections[0].asm = "mov.u32 $d, %tid.xy;".into();
-        let error = validate_imported_policy(&policy(), &imported).unwrap_err();
-        assert!(error.to_string().contains("does not agree"));
-
-        imported.selections[0].asm = "mov.u32.relaxed $d, %tid.x;".into();
-        let error = validate_imported_policy(&policy(), &imported).unwrap_err();
-        assert!(error.to_string().contains("does not agree"));
-
-        imported.selections[0].asm = "mov.u32 $d, %tid.x;".into();
-        validate_imported_policy(&policy(), &imported).unwrap();
-    }
-
-    #[test]
-    fn selected_target_predicates_fail_closed() {
-        let selection = ImportedSelection {
-            source_record: "selection".into(),
-            asm: "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {{$r0, $r1, $r2, $r3}}, [$src];".into(),
-            predicates: vec![
-                "Subtarget->getPTXVersion() >= 65".into(),
-                "Subtarget->getSmVersion() >= 75".into(),
-            ],
-            constraints: Default::default(),
-        };
-
-        let mut too_low_ptx = policy();
-        too_low_ptx.minimum_ptx = "6.4".into();
-        too_low_ptx.minimum_sm = Some("sm_75".into());
-        assert!(
-            validate_selected_target_predicates(&too_low_ptx, &selection)
-                .unwrap_err()
-                .to_string()
-                .contains("minimum PTX")
-        );
-
-        let mut too_low_sm = policy();
-        too_low_sm.minimum_ptx = "6.5".into();
-        too_low_sm.minimum_sm = Some("sm_74".into());
-        assert!(
-            validate_selected_target_predicates(&too_low_sm, &selection)
-                .unwrap_err()
-                .to_string()
-                .contains("minimum SM")
-        );
-
-        let mut unknown = selection;
-        unknown
-            .predicates
-            .push("Subtarget->hasMysteryFeature()".into());
-        assert!(
-            validate_selected_target_predicates(&too_low_sm, &unknown)
-                .unwrap_err()
-                .to_string()
-                .contains("fail closed")
-        );
-    }
-
-    #[test]
-    fn blackwell_ldmatrix_predicate_requires_the_reviewed_exact_target_set() {
-        let mut record = policy();
-        record.family = "ldmatrix".into();
-        record.minimum_ptx = "8.6".into();
-        record.minimum_sm = None;
-        record.targets = BLACKWELL_LDMATRIX_LLVM_TARGETS.into();
-        record.ldmatrix_variant = Some(crate::model::LdmatrixVariant {
-            shape: LdmatrixShape::M16n16,
-            multiplicity: LdmatrixMultiplicity::X1,
-            layout: LdmatrixLayout::Transposed,
-            element: LdmatrixElement::B8,
-            state_space: LdmatrixStateSpace::Shared,
-        });
-        let selection = ImportedSelection {
-            source_record: "selection".into(),
-            asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {{$r0, $r1}}, [$src];".into(),
-            predicates: vec!["Subtarget->hasLdStmatrixBlackwellSupport()".into()],
-            constraints: Default::default(),
-        };
-
-        validate_selected_target_predicates(&record, &selection).unwrap();
-
-        record.targets = "sm_100a|sm_101a".into();
-        assert!(validate_selected_target_predicates(&record, &selection).is_err());
-
-        record.targets = BLACKWELL_LDMATRIX_LLVM_TARGETS.into();
-        let mut conflicting = selection;
-        conflicting
-            .predicates
-            .push("Subtarget->getPTXVersion() >= 86".into());
-        assert!(validate_selected_target_predicates(&record, &conflicting).is_err());
-    }
-
-    #[test]
-    fn f32_redux_predicate_requires_the_reviewed_exact_target_matrix() {
-        let mut record = policy();
-        record.family = "redux".into();
-        record.minimum_ptx = "8.6".into();
-        record.minimum_sm = None;
-        record.targets = REDUX_F32_TARGETS.into();
-        record.redux = Some(crate::model::Redux {
-            operation: ReduxOperation::Fmin,
-            participation:
-                ReduxParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
-            adapter: ReduxAdapter::MaskValueToSourceMemberMask,
-        });
-        let selection = ImportedSelection {
-            source_record: "selection".into(),
-            asm: "redux.sync.min.f32 \t$dst, $src, $mask;".into(),
-            predicates: vec!["Subtarget->hasReduxSyncF32()".into()],
-            constraints: Default::default(),
-        };
-
-        validate_selected_target_predicates(&record, &selection).unwrap();
-
-        record.targets =
-            "sm_100a|sm_100f|sm_103a|sm_103f|sm_110a|sm_110f|sm_120a|sm_120f|sm_121a|sm_121f"
-                .into();
-        assert!(validate_selected_target_predicates(&record, &selection).is_err());
-
-        record.targets = REDUX_F32_TARGETS.into();
-        record.minimum_ptx = "8.8".into();
-        assert!(validate_selected_target_predicates(&record, &selection).is_err());
-
-        record.minimum_ptx = "8.6".into();
-        let mut conflicting = selection;
-        conflicting
-            .predicates
-            .push("Subtarget->getPTXVersion() >= 88".into());
-        assert!(validate_selected_target_predicates(&record, &conflicting).is_err());
-    }
-
-    #[test]
-    fn safe_record_requires_an_allowlist_reason() {
-        let mut record = policy();
-        record.safe_allowlist_reason = None;
-        assert!(
-            validate_imported_policy(&record, &declaration())
-                .unwrap_err()
-                .to_string()
-                .contains("safe_allowlist_reason")
-        );
-    }
-
-    #[test]
-    fn intrinsic_abi_identity_is_stable_and_explicit() {
-        let policy = policy();
-        let declaration = declaration();
-        let resolved = resolve_record(
-            &policy,
-            resolve_policy_source(&policy).unwrap(),
-            Some(&declaration),
-            &evidence(),
-            "test",
-            "LLVM version test",
-            "0123456789abcdef",
-            vec![],
-            1,
-        )
-        .unwrap();
-
-        assert_eq!(resolved.rust.abi_id, "i0001");
-        assert_eq!(
-            resolved.rust.canonical_path,
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
-        );
-        assert_eq!(
-            resolved.rust.public_path,
-            "cuda_intrinsics::sreg::thread_idx_x"
-        );
-        assert_eq!(
-            resolved.rust.compatibility_paths,
-            ["cuda_device::thread::threadIdx_x"]
-        );
-        assert_eq!(
-            resolved.llvm.as_ref().unwrap().properties,
-            [
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,1024>"
-            ]
-        );
-        assert!(resolved.llvm.as_ref().unwrap().result_facts.no_undef);
-        assert_eq!(
-            resolved.llvm.as_ref().unwrap().result_facts.range,
-            Some(CatalogHalfOpenRange {
-                lower: "0".into(),
-                upper_exclusive: "1024".into(),
-            })
-        );
-        assert_eq!(resolved.backend.version, "LLVM version test");
-        assert_eq!(resolved.backend.sha256, "0123456789abcdef");
-    }
-
-    #[test]
-    fn malformed_intrinsic_abi_ids_are_rejected() {
-        for abi_id in ["thread_idx_x", "i1", "x0001", "i00a1"] {
-            let mut record = policy();
-            record.abi_id = abi_id.into();
-            let error = validate_unique_overlay(&[record], 1).unwrap_err();
-            assert!(error.to_string().contains("stable `iNNNN` form"));
-        }
-    }
-
-    #[test]
-    fn ptx_versions_are_parsed_once_and_serialize_compatibly() {
-        for (text, encoded) in [("2.0", 20), ("6.5", 65), ("10.0", 100)] {
-            let version = parse_ptx_version(text, "test").unwrap();
-            assert_eq!(version.encoded(), encoded);
-            assert_eq!(
-                serde_json::to_string(&version).unwrap(),
-                format!("\"{text}\"")
-            );
-            assert_eq!(
-                serde_json::from_str::<PtxVersion>(&format!("\"{text}\"")).unwrap(),
-                version
-            );
-        }
-        for malformed in ["6", "6.05", " 6.5", "06.5", "6.5 "] {
-            assert!(parse_ptx_version(malformed, "test").is_err(), "{malformed}");
-        }
-    }
-
-    #[test]
-    fn hardware_targets_are_parsed_without_losing_suffix_semantics() {
-        let all = policy();
-        assert_eq!(
-            parse_hardware_target(&all).unwrap(),
-            CatalogHardwareTarget::All
-        );
-
-        let mut minimum = policy();
-        minimum.minimum_sm = Some("sm_75".into());
-        assert_eq!(
-            parse_hardware_target(&minimum).unwrap(),
-            CatalogHardwareTarget::AnyOf {
-                alternatives: vec![CatalogHardwareAlternative::MinimumSm { sm: 75 }],
-            }
-        );
-
-        let mut exact = policy();
-        exact.targets = "sm_120a".into();
-        assert_eq!(
-            parse_hardware_target(&exact).unwrap(),
-            CatalogHardwareTarget::AnyOf {
-                alternatives: vec![CatalogHardwareAlternative::ExactArchitecture { sm: 120 }],
-            }
-        );
-
-        let mut family = policy();
-        family.targets = "sm_120f".into();
-        assert_eq!(
-            parse_hardware_target(&family).unwrap(),
-            CatalogHardwareTarget::AnyOf {
-                alternatives: vec![CatalogHardwareAlternative::FamilyTarget { sm: 120 }],
-            }
-        );
-    }
-
-    #[test]
-    fn stage_hardware_shared_parser_preserves_canonical_evidence_language() {
-        for (target, expected) in [
-            ("sm_75", CatalogHardwareAlternative::MinimumSm { sm: 75 }),
-            (
-                "sm_120a",
-                CatalogHardwareAlternative::ExactArchitecture { sm: 120 },
-            ),
-            (
-                "compute_120f",
-                CatalogHardwareAlternative::FamilyTarget { sm: 120 },
-            ),
-        ] {
-            assert_eq!(parse_stage_hardware(target), Some(expected), "{target}");
-        }
-        for target in ["sm_090", "sm_1000"] {
-            assert_eq!(parse_stage_hardware(target), None, "{target}");
-        }
-    }
-
-    #[test]
-    fn reviewed_target_floors_equal_shared_backend_derivation() {
-        for (target, floor) in [
-            ("sm_120a", 87),
-            ("sm_120f", 88),
-            ("sm_121a", 88),
-            ("sm_121f", 88),
-        ] {
-            let hardware = parse_stage_hardware(target).unwrap();
-            assert_eq!(f8f6f4_llvm_ptx_floor(hardware).unwrap(), floor, "{target}");
-        }
-        for (target, floor) in [
-            ("sm_100a", 86),
-            ("sm_100f", 88),
-            ("sm_103a", 88),
-            ("sm_103f", 88),
-            ("sm_110a", 90),
-            ("sm_110f", 90),
-            ("sm_120a", 87),
-            ("sm_120f", 88),
-            ("sm_121a", 88),
-            ("sm_121f", 88),
-        ] {
-            let hardware = parse_stage_hardware(target).unwrap();
-            assert_eq!(
-                blackwell_ldmatrix_llvm_ptx_floor(hardware).unwrap(),
-                floor,
-                "{target}"
-            );
-        }
-    }
-
-    fn selector(name: &str, value: &str) -> TargetSelectorBinding {
-        TargetSelectorBinding {
-            name: name.into(),
-            value: value.into(),
-        }
-    }
-
-    fn target_contract(
-        selectors: Vec<TargetSelectorBinding>,
-        alternatives: &[(&str, &str)],
-    ) -> TargetContract {
-        TargetContract {
-            selectors,
-            alternatives: alternatives
-                .iter()
-                .map(
-                    |(target, minimum_ptx)| crate::model::TargetContractAlternative {
-                        target: (*target).into(),
-                        minimum_ptx: (*minimum_ptx).into(),
-                    },
-                )
-                .collect(),
-        }
-    }
-
-    #[test]
-    fn target_contracts_keep_selector_specific_ptx_hardware_pairs() {
-        let contracts = [
-            target_contract(
-                vec![selector("kind", "f16")],
-                &[
-                    ("sm_100a", "8.6"),
-                    ("sm_101a", "8.6"),
-                    ("sm_103a", "8.8"),
-                    ("sm_110a", "9.0"),
-                ],
-            ),
-            target_contract(
-                vec![selector("kind", "i8")],
-                &[("sm_100a", "8.6"), ("sm_101a", "8.6"), ("sm_110a", "9.0")],
-            ),
-        ];
-        let full_requirement = resolve_target_contracts("tcgen05_mma", &contracts).unwrap();
-        assert_eq!(full_requirement.minimum_ptx.encoded(), 86);
-        let CatalogHardwareTarget::TargetMatrix {
-            contracts: full_contracts,
-        } = &full_requirement.hardware
-        else {
-            panic!("full target contracts must remain a matrix")
-        };
-        assert_eq!(full_contracts.len(), 2);
-        assert_eq!(full_contracts[0].selectors, [selector("kind", "f16")]);
-        assert_eq!(full_contracts[1].selectors, [selector("kind", "i8")]);
-
-        let requirement =
-            resolve_target_contract("tcgen05_mma", &[selector("kind", "i8")], &contracts).unwrap();
-
-        assert_eq!(requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            requirement.hardware,
-            CatalogHardwareTarget::TargetMatrix {
-                contracts: vec![CatalogTargetContract {
-                    selectors: vec![selector("kind", "i8")],
-                    alternatives: vec![
-                        CatalogTargetAlternative {
-                            minimum_ptx: "8.6".parse().unwrap(),
-                            hardware: CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                        },
-                        CatalogTargetAlternative {
-                            minimum_ptx: "8.6".parse().unwrap(),
-                            hardware: CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
-                        },
-                        CatalogTargetAlternative {
-                            minimum_ptx: "9.0".parse().unwrap(),
-                            hardware: CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
-                        },
-                    ],
-                }],
-            }
-        );
-
-        let mut policy = policy();
-        policy.id = "tcgen05_mma".into();
-        validate_candidate_target(&policy, &requirement, "sm_100a", "+ptx86").unwrap();
-        assert!(validate_candidate_target(&policy, &requirement, "sm_103a", "+ptx88").is_err());
-        assert!(validate_candidate_target(&policy, &requirement, "sm_110a", "+ptx88").is_err());
-        validate_candidate_target(&policy, &requirement, "sm_110a", "+ptx90").unwrap();
-
-        let libnvvm = [target_contract(
-            vec![selector("kind", "i8")],
-            &[("sm_100a", "8.6"), ("sm_110a", "9.0")],
-        )];
-        let libnvvm_requirement =
-            resolve_target_contract("tcgen05_mma", &[selector("kind", "i8")], &libnvvm).unwrap();
-        assert_ne!(requirement, libnvvm_requirement);
-        validate_candidate_target(&policy, &requirement, "sm_101a", "+ptx86").unwrap();
-        assert!(
-            validate_candidate_target(&policy, &libnvvm_requirement, "sm_101a", "+ptx86").is_err()
-        );
-    }
-
-    #[test]
-    fn target_contract_selection_and_shape_fail_closed() {
-        resolve_target_contract(
-            "tcgen05_mma",
-            &[selector("kind", "f16")],
-            &[target_contract(
-                vec![selector("kind", "f16")],
-                &[("sm_100a", "8.6"), ("sm_100f", "8.8"), ("sm_103a", "8.8")],
-            )],
-        )
-        .unwrap();
-
-        let valid = target_contract(
-            vec![selector("kind", "f16"), selector("scale_d", "false")],
-            &[("sm_100a", "8.6"), ("sm_103a", "8.8")],
-        );
-        assert!(
-            resolve_target_contract(
-                "tcgen05_mma",
-                &[selector("kind", "i8"), selector("scale_d", "false")],
-                std::slice::from_ref(&valid),
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("exactly one reviewed contract")
-        );
-
-        for invalid in [
-            target_contract(
-                vec![selector("scale_d", "false"), selector("kind", "f16")],
-                &[("sm_100a", "8.6")],
-            ),
-            target_contract(vec![selector("kind", "F16")], &[("sm_100a", "8.6")]),
-            target_contract(vec![selector("kind_", "f16")], &[("sm_100a", "8.6")]),
-            target_contract(
-                vec![selector("kind", "f16")],
-                &[("sm_103a", "8.8"), ("sm_100a", "8.6")],
-            ),
-            target_contract(
-                vec![selector("kind", "f16")],
-                &[("sm_100+", "8.6"), ("sm_103a", "8.8")],
-            ),
-            target_contract(vec![selector("kind", "f16")], &[("sm_100a", "8.60")]),
-        ] {
-            assert!(
-                resolve_target_contract(
-                    "tcgen05_mma",
-                    &invalid.selectors,
-                    std::slice::from_ref(&invalid)
-                )
-                .is_err(),
-                "{invalid:?}"
-            );
-        }
-    }
-
-    #[test]
-    fn legacy_target_requirement_json_is_unchanged() {
-        let requirement = CatalogTargetRequirement {
-            minimum_ptx: "8.6".parse().unwrap(),
-            hardware: CatalogHardwareTarget::AnyOf {
-                alternatives: vec![CatalogHardwareAlternative::ExactArchitecture { sm: 100 }],
-            },
-        };
-        assert_eq!(
-            serde_json::to_value(requirement).unwrap(),
-            serde_json::json!({
-                "minimum_ptx": "8.6",
-                "hardware": {
-                    "kind": "any_of",
-                    "alternatives": [{ "kind": "exact_architecture", "sm": 100 }]
-                }
-            })
-        );
-    }
-
-    #[test]
-    fn malformed_or_conflicting_hardware_targets_are_rejected() {
-        for malformed in [
-            "sm_120",
-            "sm_120af",
-            "sm_120A",
-            "sm_0120a",
-            "sm_0a",
-            "sm_120+",
-            "compute_120a",
-            "all ",
-        ] {
-            let mut record = policy();
-            record.targets = malformed.into();
-            assert!(parse_hardware_target(&record).is_err(), "{malformed}");
-        }
-
-        let mut suffixed_minimum = policy();
-        suffixed_minimum.minimum_sm = Some("sm_90a".into());
-        assert!(parse_hardware_target(&suffixed_minimum).is_err());
-
-        for target in ["sm_120a", "sm_120f"] {
-            let mut conflicting = policy();
-            conflicting.targets = target.into();
-            conflicting.minimum_sm = Some("sm_120".into());
-            let error = parse_hardware_target(&conflicting).unwrap_err().to_string();
-            assert!(error.contains("cannot be combined"), "{error}");
-        }
-    }
-
-    #[test]
-    fn exact_inline_ptx_routes_can_inherit_exact_or_family_targets() {
-        for target in ["sm_120a", "sm_120f"] {
-            let mut record = policy();
-            record.minimum_ptx = "8.7".into();
-            record.targets = target.into();
-            record.backend_lowerings = [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
-                .into_iter()
-                .map(|backend| crate::model::OverlayBackendLowering {
-                    backend,
-                    mechanism: BackendLoweringMechanism::InlinePtx,
-                    evidence_profile: "test".into(),
-                    targets: None,
-                    minimum_ptx: Some("8.7".into()),
-                    minimum_sm: None,
-                })
-                .collect();
-
-            ensure_exact_inline_ptx_backends(
-                &record,
-                [
-                    (IntrinsicBackend::LlvmNvptx, "8.7", None),
-                    (IntrinsicBackend::LibNvvm, "8.7", None),
-                ],
-                "test",
-            )
-            .unwrap();
-            for lowering in &record.backend_lowerings {
-                assert_eq!(
-                    backend_target_requirement(&record, lowering)
-                        .unwrap()
-                        .hardware,
-                    parse_hardware_target(&record).unwrap()
-                );
-            }
-
-            record.backend_lowerings[0].minimum_sm = Some("sm_120".into());
-            assert!(
-                ensure_exact_inline_ptx_backends(
-                    &record,
-                    [
-                        (IntrinsicBackend::LlvmNvptx, "8.7", None),
-                        (IntrinsicBackend::LibNvvm, "8.7", None),
-                    ],
-                    "test",
-                )
-                .is_err()
-            );
-        }
-    }
-
-    #[test]
-    fn backend_route_target_override_is_exact_and_does_not_inherit_the_record_sm_floor() {
-        let mut record = policy();
-        record.minimum_ptx = "8.6".into();
-        record.minimum_sm = Some("sm_75".into());
-        record.targets = "all".into();
-        let lowering = crate::model::OverlayBackendLowering {
-            backend: IntrinsicBackend::LibNvvm,
-            mechanism: BackendLoweringMechanism::InlinePtx,
-            evidence_profile: "test".into(),
-            targets: Some("sm_100a|sm_120a".into()),
-            minimum_ptx: None,
-            minimum_sm: None,
-        };
-
-        assert_eq!(
-            backend_target_requirement(&record, &lowering).unwrap(),
-            CatalogTargetRequirement {
-                minimum_ptx: parse_ptx_version("8.6", &record.id).unwrap(),
-                hardware: CatalogHardwareTarget::AnyOf {
-                    alternatives: vec![
-                        CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-                        CatalogHardwareAlternative::ExactArchitecture { sm: 120 },
-                    ],
-                },
-            }
-        );
-    }
-
-    #[test]
-    fn blackwell_ldmatrix_evidence_covers_every_target_with_its_effective_ptx_floor() {
-        let mut policy = policy();
-        policy.family = "ldmatrix".into();
-        policy.minimum_ptx = "8.6".into();
-        policy.minimum_sm = None;
-        policy.targets = BLACKWELL_LDMATRIX_LLVM_TARGETS.into();
-        policy.ldmatrix_variant = Some(crate::model::LdmatrixVariant {
-            shape: LdmatrixShape::M16n16,
-            multiplicity: LdmatrixMultiplicity::X1,
-            layout: LdmatrixLayout::Transposed,
-            element: LdmatrixElement::B8,
-            state_space: LdmatrixStateSpace::Shared,
-        });
-        let lowering = OverlayBackendLowering {
-            backend: IntrinsicBackend::LlvmNvptx,
-            mechanism: BackendLoweringMechanism::TypedNvvm,
-            evidence_profile: "test".into(),
-            targets: None,
-            minimum_ptx: None,
-            minimum_sm: None,
-        };
-        let mut record = evidence();
-        record.status = "validated".into();
-        record.stages.clear();
-        for (target, ptx) in [
-            ("sm_100a", "ptx86"),
-            ("sm_100f", "ptx88"),
-            ("sm_103a", "ptx88"),
-            ("sm_103f", "ptx88"),
-            ("sm_110a", "ptx90"),
-            ("sm_110f", "ptx90"),
-            ("sm_120a", "ptx87"),
-            ("sm_120f", "ptx88"),
-            ("sm_121a", "ptx88"),
-            ("sm_121f", "ptx88"),
-        ] {
-            record.stages.push(evidence_stage(
-                EvidenceStageKind::BackendCodegen,
-                BackendLoweringMechanism::TypedNvvm,
-                &[target, ptx],
-            ));
-            let mut assembly = evidence_stage(
-                EvidenceStageKind::PtxAssembly,
-                BackendLoweringMechanism::TypedNvvm,
-                &[target, ptx],
-            );
-            assembly.tool_path = Some("/tool/ptxas".into());
-            assembly.tool_version = Some("test".into());
-            assembly.tool_sha256 = Some("0".repeat(64));
-            record.stages.push(assembly);
-        }
-        validate_selected_stage_targets(&policy, &record, &lowering).unwrap();
-
-        record.stages.retain(|stage| {
-            !(stage.stage == EvidenceStageKind::PtxAssembly
-                && stage.targets.iter().any(|target| target == "sm_121f"))
-        });
-        assert!(
-            validate_selected_stage_targets(&policy, &record, &lowering)
-                .unwrap_err()
-                .to_string()
-                .contains("one structured stage for each")
-        );
-    }
-
-    #[test]
-    fn paired_target_evidence_checks_backend_and_runtime_floors() {
-        let policy = policy();
-        let hardware = vec![
-            CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
-            CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
-        ];
-        let paired = vec![
-            CatalogTargetAlternative {
-                minimum_ptx: "8.6".parse().unwrap(),
-                hardware: hardware[0],
-            },
-            CatalogTargetAlternative {
-                minimum_ptx: "8.8".parse().unwrap(),
-                hardware: hardware[1],
-            },
-        ];
-        let llvm = OverlayBackendLowering {
-            backend: IntrinsicBackend::LlvmNvptx,
-            mechanism: BackendLoweringMechanism::InlinePtx,
-            evidence_profile: "test".into(),
-            targets: None,
-            minimum_ptx: None,
-            minimum_sm: None,
-        };
-        let mut llvm_record = evidence();
-        llvm_record.status = "validated".into();
-        llvm_record.stages.clear();
-        for (target, ptx) in [("sm_100a", "ptx86"), ("sm_103a", "ptx88")] {
-            llvm_record.stages.push(evidence_stage(
-                EvidenceStageKind::BackendCodegen,
-                llvm.mechanism,
-                &[target, ptx],
-            ));
-            let mut assembly = evidence_stage(
-                EvidenceStageKind::PtxAssembly,
-                llvm.mechanism,
-                &[target, ptx],
-            );
-            assembly.tool_path = Some("/tool/ptxas".into());
-            assembly.tool_version = Some("test".into());
-            assembly.tool_sha256 = Some("0".repeat(64));
-            llvm_record.stages.push(assembly);
-        }
-        validate_target_matrix_stage_targets(
-            &policy,
-            &llvm_record,
-            &llvm,
-            EvidenceStageKind::PtxAssembly,
-            &hardware,
-            86,
-            Some(&paired),
-        )
-        .unwrap();
-
-        let mut wrong_floor = llvm_record.clone();
-        wrong_floor
-            .stages
-            .iter_mut()
-            .find(|stage| {
-                stage.stage == EvidenceStageKind::BackendCodegen
-                    && stage.targets.iter().any(|target| target == "sm_103a")
-            })
-            .unwrap()
-            .targets = vec!["sm_103a".into(), "ptx86".into()];
-        assert!(
-            validate_target_matrix_stage_targets(
-                &policy,
-                &wrong_floor,
-                &llvm,
-                EvidenceStageKind::PtxAssembly,
-                &hardware,
-                86,
-                Some(&paired),
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("wrong PTX floor")
-        );
-
-        let libnvvm = OverlayBackendLowering {
-            backend: IntrinsicBackend::LibNvvm,
-            ..llvm.clone()
-        };
-        let mut libnvvm_record = evidence();
-        libnvvm_record.status = "validated".into();
-        libnvvm_record.stages.clear();
-        for (target, ptx) in [("sm_100a", "ptx88"), ("sm_103a", "ptx90")] {
-            libnvvm_record.stages.push(evidence_stage(
-                EvidenceStageKind::BackendCodegen,
-                libnvvm.mechanism,
-                &[target, ptx],
-            ));
-            let mut assembly = evidence_stage(
-                EvidenceStageKind::PtxAssembly,
-                libnvvm.mechanism,
-                &[target, ptx],
-            );
-            assembly.tool_path = Some("/tool/ptxas".into());
-            assembly.tool_version = Some("test".into());
-            assembly.tool_sha256 = Some("0".repeat(64));
-            libnvvm_record.stages.push(assembly);
-            let mut link = evidence_stage(
-                EvidenceStageKind::DeviceLink,
-                libnvvm.mechanism,
-                &[target, ptx],
-            );
-            link.artifact_kind = Some(EvidenceArtifactKind::Cubin);
-            link.tool_path = Some("/tool/nvlink".into());
-            link.tool_version = Some("test".into());
-            link.tool_sha256 = Some("0".repeat(64));
-            libnvvm_record.stages.push(link);
-        }
-        validate_target_matrix_stage_targets(
-            &policy,
-            &libnvvm_record,
-            &libnvvm,
-            EvidenceStageKind::DeviceLink,
-            &hardware,
-            86,
-            Some(&paired),
-        )
-        .unwrap();
-
-        let mut executed = llvm_record;
-        executed.status = "executed".into();
-        executed.stages.push(evidence_stage(
-            EvidenceStageKind::Runtime,
-            llvm.mechanism,
-            &["sm_103a", "ptx88"],
-        ));
-        validate_target_matrix_stage_targets(
-            &policy,
-            &executed,
-            &llvm,
-            EvidenceStageKind::PtxAssembly,
-            &hardware,
-            86,
-            Some(&paired),
-        )
-        .unwrap();
-
-        let mut wrong_runtime_ptx = executed.clone();
-        wrong_runtime_ptx.stages.last_mut().unwrap().targets =
-            vec!["sm_103a".into(), "ptx87".into()];
-        assert!(
-            validate_target_matrix_stage_targets(
-                &policy,
-                &wrong_runtime_ptx,
-                &llvm,
-                EvidenceStageKind::PtxAssembly,
-                &hardware,
-                86,
-                Some(&paired),
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("paired floor")
-        );
-
-        let mut wrong_runtime_hardware = executed;
-        wrong_runtime_hardware.stages.last_mut().unwrap().targets =
-            vec!["sm_110a".into(), "ptx90".into()];
-        assert!(
-            validate_target_matrix_stage_targets(
-                &policy,
-                &wrong_runtime_hardware,
-                &llvm,
-                EvidenceStageKind::PtxAssembly,
-                &hardware,
-                86,
-                Some(&paired),
-            )
-            .unwrap_err()
-            .to_string()
-            .contains("outside its target matrix")
-        );
-    }
-
-    #[test]
-    fn sparse_f8f6f4_f16_evidence_covers_every_target_and_floor() {
-        let policy =
-            expand_sparse_mma_f8f6f4_f16_admission(&test_sparse_mma_f8f6f4_f16_admission())
-                .unwrap()
-                .remove(0);
-        let lowering = policy
-            .backend_lowerings
-            .iter()
-            .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
-            .unwrap();
-        let mut record = evidence();
-        record.status = "validated".into();
-        record.stages.clear();
-        for (target, ptx) in [
-            ("sm_120a", "ptx87"),
-            ("sm_120f", "ptx88"),
-            ("sm_121a", "ptx88"),
-            ("sm_121f", "ptx88"),
-        ] {
-            record.stages.push(evidence_stage(
-                EvidenceStageKind::BackendCodegen,
-                BackendLoweringMechanism::InlinePtx,
-                &[target, ptx],
-            ));
-            let mut assembly = evidence_stage(
-                EvidenceStageKind::PtxAssembly,
-                BackendLoweringMechanism::InlinePtx,
-                &[target, ptx],
-            );
-            assembly.artifact_kind = Some(EvidenceArtifactKind::Cubin);
-            assembly.tool_path = Some("/tool/ptxas".into());
-            assembly.tool_version = Some("test".into());
-            assembly.tool_sha256 = Some("0".repeat(64));
-            record.stages.push(assembly);
-        }
-        validate_selected_stage_targets(&policy, &record, lowering).unwrap();
-
-        let valid = record.clone();
-        record.stages.retain(|stage| {
-            !(stage.stage == EvidenceStageKind::PtxAssembly
-                && stage.targets.iter().any(|target| target == "sm_121f"))
-        });
-        assert!(
-            validate_selected_stage_targets(&policy, &record, lowering)
-                .unwrap_err()
-                .to_string()
-                .contains("one structured stage for each")
-        );
-
-        record = valid;
-        record
-            .stages
-            .iter_mut()
-            .find(|stage| {
-                stage.stage == EvidenceStageKind::BackendCodegen
-                    && stage.targets.iter().any(|target| target == "sm_120f")
-            })
-            .unwrap()
-            .targets = vec!["sm_120f".into(), "ptx87".into()];
-        assert!(
-            validate_selected_stage_targets(&policy, &record, lowering)
-                .unwrap_err()
-                .to_string()
-                .contains("wrong PTX floor")
-        );
-    }
-
-    #[test]
-    fn non_blackwell_evidence_rejects_multiple_target_specific_stage_pairs() {
-        let policy = policy();
-        let lowering = OverlayBackendLowering {
-            backend: IntrinsicBackend::LlvmNvptx,
-            mechanism: BackendLoweringMechanism::TypedNvvm,
-            evidence_profile: "test".into(),
-            targets: None,
-            minimum_ptx: None,
-            minimum_sm: None,
-        };
-        let mut record = evidence();
-        record.stages = vec![
-            evidence_stage(
-                EvidenceStageKind::BackendCodegen,
-                BackendLoweringMechanism::TypedNvvm,
-                &["sm_20", "ptx20"],
-            ),
-            evidence_stage(
-                EvidenceStageKind::BackendCodegen,
-                BackendLoweringMechanism::TypedNvvm,
-                &["sm_21", "ptx20"],
-            ),
-        ];
-
-        assert!(
-            validate_selected_stage_targets(&policy, &record, &lowering)
-                .unwrap_err()
-                .to_string()
-                .contains("outside reviewed target-matrix evidence")
-        );
-    }
-
-    #[test]
-    fn abi_ledger_requires_exact_active_identity() {
-        let record = policy();
-        let frozen_entry = ledger_entry(&record);
-        validate_abi_ledger(
-            &overlay_file(vec![record.clone()]),
-            &ledger(vec![frozen_entry.clone()]),
-        )
-        .unwrap();
-
-        let mut reassigned = record.clone();
-        reassigned.id = "different_catalog_id".into();
-        let error = validate_abi_ledger(
-            &overlay_file(vec![reassigned]),
-            &ledger(vec![frozen_entry.clone()]),
-        )
-        .unwrap_err();
-        assert!(error.to_string().contains("catalog ID mismatch"));
-
-        let mut reassigned = record.clone();
-        reassigned.operation_key = "launch.block_index.x".into();
-        let error = validate_abi_ledger(
-            &overlay_file(vec![reassigned]),
-            &ledger(vec![frozen_entry.clone()]),
-        )
-        .unwrap_err();
-        assert!(error.to_string().contains("operation key mismatch"));
-
-        for mutate in [
-            |record: &mut OverlayIntrinsic| record.safe = false,
-            |record: &mut OverlayIntrinsic| record.rust_arguments.push("u32".into()),
-            |record: &mut OverlayIntrinsic| record.rust_result = "u64".into(),
-        ] {
-            let mut changed_signature = record.clone();
-            mutate(&mut changed_signature);
-            let error = validate_abi_ledger(
-                &overlay_file(vec![changed_signature]),
-                &ledger(vec![frozen_entry.clone()]),
-            )
-            .unwrap_err();
-            assert!(error.to_string().contains("raw Rust signature mismatch"));
-        }
-    }
-
-    #[test]
-    fn generated_abi_binding_uses_catalog_identity_not_axis_position() {
-        let mut record = policy();
-        let mut frozen = ledger_entry(&record);
-        frozen.abi_id = "i9001".into();
-        record.abi_id.clear();
-        let mut overlay = overlay_file(vec![record]);
-
-        bind_generated_abi_ids(&mut overlay, &ledger(vec![frozen])).unwrap();
-
-        assert_eq!(overlay.intrinsics[0].abi_id, "i9001");
-    }
-
-    #[test]
-    fn generated_abi_binding_rejects_missing_tombstoned_or_ambiguous_identity() {
-        let record = policy();
-        let mut unbound = record.clone();
-        unbound.abi_id.clear();
-
-        let error = bind_generated_abi_ids(
-            &mut overlay_file(vec![unbound.clone()]),
-            &ledger(vec![ledger_entry(&distinct_policy())]),
-        )
-        .unwrap_err();
-        assert!(error.to_string().contains("has no ABI ledger entry"));
-
-        let mut tombstone = ledger_entry(&record);
-        tombstone.status = "tombstone".into();
-        let error = bind_generated_abi_ids(
-            &mut overlay_file(vec![unbound.clone()]),
-            &ledger(vec![tombstone]),
-        )
-        .unwrap_err();
-        assert!(error.to_string().contains("non-active ABI ledger entry"));
-
-        let first = ledger_entry(&record);
-        let mut duplicate = first.clone();
-        duplicate.abi_id = "i9002".into();
-        let error = bind_generated_abi_ids(
-            &mut overlay_file(vec![unbound]),
-            &ledger(vec![first, duplicate]),
-        )
-        .unwrap_err();
-        assert!(
-            error
-                .to_string()
-                .contains("duplicate ABI ledger catalog ID")
-        );
-    }
-
-    #[test]
-    fn generated_abi_binding_checks_derived_operation_and_raw_signature() {
-        let record = policy();
-        let mut unbound = record.clone();
-        unbound.abi_id.clear();
-
-        let mut wrong_operation = ledger_entry(&record);
-        wrong_operation.operation_key = "launch.block_index.x".into();
-        let error = bind_generated_abi_ids(
-            &mut overlay_file(vec![unbound.clone()]),
-            &ledger(vec![wrong_operation]),
-        )
-        .unwrap_err();
-        assert!(error.to_string().contains("operation key mismatch"));
-
-        let mut wrong_signature = ledger_entry(&record);
-        wrong_signature
-            .raw_rust_signature
-            .arguments
-            .push("u32".into());
-        let error = bind_generated_abi_ids(
-            &mut overlay_file(vec![unbound]),
-            &ledger(vec![wrong_signature]),
-        )
-        .unwrap_err();
-        assert!(error.to_string().contains("raw Rust signature mismatch"));
-    }
-
-    #[test]
-    fn abi_ledger_does_not_freeze_public_or_backend_implementation_details() {
-        let record = policy();
-        let frozen_entry = ledger_entry(&record);
-        let mut evolved = record.clone();
-        evolved.rust_module = "coordinates".into();
-        evolved.rust_name = "thread_x".into();
-        evolved.public_rust_path = "cuda_intrinsics::coordinates::thread_x".into();
-        evolved.llvm_symbol = Some("llvm.nvvm.backend.v2.tid.x".into());
-        evolved.llvm_arguments = vec!["i8".into()];
-        evolved.llvm_results = vec!["i64".into()];
-        evolved.dialect_op_type = "ReadThreadIndexXOpV2".into();
-        evolved.dialect_op_name = "nvvm.read_thread_index_x_v2".into();
-        evolved.lowering = "backend_v2_adapter".into();
-
-        validate_abi_ledger(&overlay_file(vec![evolved]), &ledger(vec![frozen_entry])).unwrap();
-    }
-
-    #[test]
-    fn tombstoned_or_unlisted_abi_ids_cannot_reappear() {
-        let record = policy();
-        let mut tombstone = ledger_entry(&record);
-        tombstone.status = "tombstone".into();
-        let error = validate_abi_ledger(
-            &overlay_file(vec![record.clone()]),
-            &ledger(vec![tombstone]),
-        )
-        .unwrap_err();
-        assert!(error.to_string().contains("cannot reappear"));
-
-        let error = validate_abi_ledger(&overlay_file(vec![record]), &ledger(vec![])).unwrap_err();
-        assert!(error.to_string().contains("contains no entries"));
-    }
-
-    #[test]
-    fn every_active_ledger_entry_requires_an_overlay_record() {
-        let record = policy();
-        let error =
-            validate_abi_ledger(&overlay_file(vec![]), &ledger(vec![ledger_entry(&record)]))
-                .unwrap_err();
-        assert!(error.to_string().contains("has no overlay record"));
-    }
-
-    #[test]
-    fn return_range_properties_are_half_open_and_unique() {
-        let facts =
-            imported_result_facts(&["NoUndef<ret>".into(), "Range<ret,1,1025>".into()]).unwrap();
-        assert!(facts.no_undef);
-        let range = facts.range.unwrap();
-        assert_eq!(range.lower, "1");
-        assert_eq!(range.upper_exclusive, "1025");
-
-        let duplicate =
-            imported_result_facts(&["Range<ret,0,32>".into(), "Range<ret,0,64>".into()])
-                .unwrap_err();
-        assert!(duplicate.to_string().contains("duplicate return range"));
-    }
-
-    #[test]
-    fn packed_alu_recipes_accept_only_the_reviewed_source_shape_and_floor() {
-        let operations = [
-            PackedAluOperation::Add,
-            PackedAluOperation::Sub,
-            PackedAluOperation::Mul,
-            PackedAluOperation::Fma,
-            PackedAluOperation::FmaRelu,
-            PackedAluOperation::Min,
-            PackedAluOperation::Max,
-            PackedAluOperation::Neg,
-            PackedAluOperation::Abs,
-        ];
-        for format in [PackedAluFormat::Bf16x2, PackedAluFormat::F16x2] {
-            for operation in operations {
-                let policy = packed_alu_policy(format, operation);
-                match packed_alu_declaration(format, operation) {
-                    Some(declaration) => validate_imported_policy(&policy, &declaration).unwrap(),
-                    None => validate_ptx_native_policy(&policy).unwrap(),
-                }
-            }
-        }
-
-        let declaration =
-            packed_alu_declaration(PackedAluFormat::Bf16x2, PackedAluOperation::Fma).unwrap();
-        let reject_imported = |policy: &OverlayIntrinsic, message: &str| {
-            let error = validate_imported_policy(policy, &declaration).unwrap_err();
-            assert!(error.to_string().contains(message), "{error:#}");
-        };
-
-        let valid = packed_alu_policy(PackedAluFormat::Bf16x2, PackedAluOperation::Fma);
-        let mut wrong_source = valid.clone();
-        wrong_source.source_record = Some("int_nvvm_fma_rn_bf16".into());
-        reject_imported(&wrong_source, "source");
-
-        let mut wrong_format = valid.clone();
-        wrong_format.packed_alu.as_mut().unwrap().format = PackedAluFormat::F16x2;
-        reject_imported(&wrong_format, "identity");
-
-        let mut wrong_operation = valid.clone();
-        wrong_operation.packed_alu.as_mut().unwrap().operation = PackedAluOperation::Max;
-        reject_imported(&wrong_operation, "identity");
-
-        let mut wrong_floor = valid.clone();
-        wrong_floor.minimum_sm = Some("sm_90".into());
-        reject_imported(&wrong_floor, "target floor");
-
-        let mut wrong_effects = valid.clone();
-        wrong_effects.memory = "read".into();
-        reject_imported(&wrong_effects, "effects");
-
-        let mut wrong_section = valid.clone();
-        wrong_section.ptx_isa_section = "9.7.4 Floating Point Instructions".into();
-        reject_imported(&wrong_section, "PTX provenance");
-
-        let mut wrong_url = valid.clone();
-        wrong_url.ptx_isa_url =
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions"
-                .into();
-        reject_imported(&wrong_url, "PTX provenance");
-
-        let mut wrong_adapter = valid.clone();
-        wrong_adapter.lowering = "direct_nvvm".into();
-        reject_imported(&wrong_adapter, "lowering recipe");
-
-        let mut wrong_backend = valid;
-        wrong_backend.backend_lowerings[0].mechanism = BackendLoweringMechanism::TypedNvvm;
-        reject_imported(&wrong_backend, "inline-PTX routes");
-
-        let mut wrong_native = packed_alu_policy(PackedAluFormat::Bf16x2, PackedAluOperation::Add);
-        wrong_native.source = Some(IntrinsicSource::PtxNative {
-            instruction: "add.bf16x2".into(),
-        });
-        let error = validate_ptx_native_policy(&wrong_native).unwrap_err();
-        assert!(error.to_string().contains("PTX-native recipe"));
-
-        let mut invented_llvm = packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Add);
-        invented_llvm.llvm_symbol = Some("llvm.nvvm.add.rn.f16x2".into());
-        let error = validate_ptx_native_policy(&invented_llvm).unwrap_err();
-        assert!(
-            error
-                .to_string()
-                .contains("must not invent LLVM source facts")
-        );
-
-        let mut unreviewed_modifier =
-            packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Add);
-        unreviewed_modifier.expected_ptx.modifiers =
-            vec!["rn".into(), "ftz".into(), "f16x2".into()];
-        let error = validate_ptx_native_policy(&unreviewed_modifier).unwrap_err();
-        assert!(error.to_string().contains("exact packed-ALU instruction"));
-
-        let mut wrong_arity = packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Add);
-        wrong_arity.expected_ptx.operands.pop();
-        let error = validate_ptx_native_policy(&wrong_arity).unwrap_err();
-        assert!(error.to_string().contains("exact packed-ALU instruction"));
-
-        let f16_declaration =
-            packed_alu_declaration(PackedAluFormat::F16x2, PackedAluOperation::Fma).unwrap();
-        let reject_f16 = |policy: &OverlayIntrinsic, message: &str| {
-            let error = validate_imported_policy(policy, &f16_declaration).unwrap_err();
-            assert!(error.to_string().contains(message), "{error:#}");
-        };
-        let f16 = packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Fma);
-
-        let mut wrong_signature = f16.clone();
-        wrong_signature.llvm_arguments = vec!["v2bf16".into(); 3];
-        reject_f16(&wrong_signature, "LLVM argument signature mismatch");
-
-        let mut missing_must_use = f16.clone();
-        missing_must_use.must_use = false;
-        reject_f16(&missing_must_use, "reviewed safe packed-ALU API");
-
-        let mut wrong_native_floor = f16.clone();
-        wrong_native_floor
-            .packed_alu
-            .as_mut()
-            .unwrap()
-            .native_minimum_sm = 70;
-        reject_f16(&wrong_native_floor, "target floor");
-
-        let mut wrong_backend_floor = f16;
-        wrong_backend_floor.backend_lowerings[0].minimum_ptx = Some("4.2".into());
-        reject_f16(&wrong_backend_floor, "exact packed-ALU floor");
-
-        let abs_declaration =
-            packed_alu_declaration(PackedAluFormat::F16x2, PackedAluOperation::Abs).unwrap();
-        let mut wrong_abs = packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Abs);
-        wrong_abs.resolved_llvm_symbol = Some("llvm.nvvm.fabs.v2bf16".into());
-        let error = validate_imported_policy(&wrong_abs, &abs_declaration).unwrap_err();
-        assert!(error.to_string().contains("LLVM source or signature"));
-    }
-
-    #[test]
-    fn pinned_packed_alu_records_match_the_closed_recipes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect();
-        let packed: Vec<_> = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| record.family == "packed_alu")
-            .collect();
-        assert_eq!(packed.len(), 30);
-        for policy in packed {
-            let source = resolve_policy_source(policy).unwrap();
-            let declaration = policy
-                .source_record
-                .as_deref()
-                .map(|record| declarations[record]);
-            validate_policy(policy, &source, declaration, 1).unwrap();
-        }
-    }
-
-    #[test]
-    fn pinned_packed_conversion_records_match_the_closed_recipes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let overlay = load_resolution_base(&repo_root).unwrap().overlay;
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations: BTreeMap<_, _> = imported
-            .intrinsics
-            .iter()
-            .map(|record| (record.source_record.as_str(), record))
-            .collect();
-        let packed: Vec<_> = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| record.family == "packed_conversion")
-            .collect();
-        assert_eq!(packed.len(), 18);
-        for policy in packed {
-            let source = resolve_policy_source(policy).unwrap();
-            let declaration = policy
-                .source_record
-                .as_deref()
-                .map(|record| declarations[record]);
-            validate_policy(policy, &source, declaration, 1).unwrap();
-        }
-    }
-
-    #[test]
-    fn selectionless_packed_conversion_is_admitted_only_by_its_closed_recipe() {
-        let cases = [
-            (
-                PackedConversionDestinationFormat::Bf16x2,
-                PackedConversionRounding::NearestEven,
-                PackedConversionSaturation::None,
-            ),
-            (
-                PackedConversionDestinationFormat::F16x2,
-                PackedConversionRounding::NearestEven,
-                PackedConversionSaturation::None,
-            ),
-            (
-                PackedConversionDestinationFormat::F16x2,
-                PackedConversionRounding::TowardZero,
-                PackedConversionSaturation::None,
-            ),
-            (
-                PackedConversionDestinationFormat::F16x2,
-                PackedConversionRounding::NearestEven,
-                PackedConversionSaturation::Relu,
-            ),
-            (
-                PackedConversionDestinationFormat::Bf16x2,
-                PackedConversionRounding::NearestEven,
-                PackedConversionSaturation::Relu,
-            ),
-            (
-                PackedConversionDestinationFormat::Bf16x2,
-                PackedConversionRounding::TowardZero,
-                PackedConversionSaturation::None,
-            ),
-            (
-                PackedConversionDestinationFormat::E4m3x2,
-                PackedConversionRounding::NearestEven,
-                PackedConversionSaturation::Satfinite,
-            ),
-            (
-                PackedConversionDestinationFormat::E4m3x2,
-                PackedConversionRounding::NearestEven,
-                PackedConversionSaturation::SatfiniteRelu,
-            ),
-            (
-                PackedConversionDestinationFormat::E5m2x2,
-                PackedConversionRounding::NearestEven,
-                PackedConversionSaturation::Satfinite,
-            ),
-            (
-                PackedConversionDestinationFormat::E5m2x2,
-                PackedConversionRounding::NearestEven,
-                PackedConversionSaturation::SatfiniteRelu,
-            ),
-        ];
-        for (destination, rounding, saturation) in cases {
-            let policy = packed_conversion_policy(destination, rounding, saturation);
-            let declaration = packed_conversion_declaration(&policy);
-            validate_imported_policy(&policy, &declaration).unwrap();
-        }
-
-        let valid = packed_conversion_policy(
-            PackedConversionDestinationFormat::Bf16x2,
-            PackedConversionRounding::NearestEven,
-            PackedConversionSaturation::None,
-        );
-        let declaration = packed_conversion_declaration(&valid);
-
-        let reject = |policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic, message: &str| {
-            let error = validate_imported_policy(policy, declaration).unwrap_err();
-            assert!(error.to_string().contains(message), "{error:#}");
-        };
-
-        let mut wrong_source = valid.clone();
-        wrong_source.source_record = Some("int_nvvm_ff2bf16x2_rz".into());
-        reject(&wrong_source, &declaration, "identity or LLVM source");
-
-        let mut wrong_floor = valid.clone();
-        wrong_floor.minimum_ptx = "7.8".into();
-        reject(&wrong_floor, &declaration, "target floor");
-
-        let mut wrong_effect = valid.clone();
-        wrong_effect.pure = false;
-        reject(&wrong_effect, &declaration, "effects");
-
-        let mut wrong_section = valid.clone();
-        wrong_section.ptx_isa_section = "9.7.9 Data Movement and Conversion Instructions".into();
-        reject(&wrong_section, &declaration, "PTX provenance");
-
-        let mut wrong_url = valid.clone();
-        wrong_url.ptx_isa_url =
-            "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions"
-                .into();
-        reject(&wrong_url, &declaration, "PTX provenance");
-
-        let mut wrong_shape = valid.clone();
-        wrong_shape.expected_ptx.modifiers.swap(1, 2);
-        reject(&wrong_shape, &declaration, "expected PTX does not match");
-
-        let mut wrong_identity = valid.clone();
-        wrong_identity.id = "cvt_f16x2_f32".into();
-        reject(&wrong_identity, &declaration, "identity or LLVM source");
-
-        let mut unsupported = valid.clone();
-        let conversion = unsupported.packed_conversion.as_mut().unwrap();
-        conversion.rounding = PackedConversionRounding::TowardZero;
-        conversion.saturation = PackedConversionSaturation::Relu;
-        reject(
-            &unsupported,
-            &declaration,
-            "unsupported packed-conversion source, destination",
-        );
-
-        let mut wrong_compatibility = valid.clone();
-        wrong_compatibility.compatibility_rust_paths =
-            vec!["cuda_device::tcgen05::cvt_f32x2_bf16x2".into()];
-        reject(&wrong_compatibility, &declaration, "conversion API");
-
-        let mut wrong_result = valid.clone();
-        wrong_result.llvm_results = vec!["v2f16".into()];
-        reject(&wrong_result, &declaration, "result signature mismatch");
-
-        let mut selected = declaration.clone();
-        selected.selections.push(ImportedSelection {
-            source_record: "UNREVIEWED".into(),
-            asm: "cvt.rn.bf16x2.f32 $d, $a, $b;".into(),
-            predicates: vec![],
-            constraints: Default::default(),
-        });
-        reject(&valid, &selected, "selectionless");
-    }
-
-    #[test]
-    fn candidate_targets_are_canonical_and_satisfy_every_floor() {
-        let policy = policy();
-        let requirement = CatalogTargetRequirement {
-            minimum_ptx: "7.0".parse().unwrap(),
-            hardware: CatalogHardwareTarget::AnyOf {
-                alternatives: vec![CatalogHardwareAlternative::MinimumSm { sm: 80 }],
-            },
-        };
-        validate_candidate_target(&policy, &requirement, "sm_80", "+ptx70").unwrap();
-        validate_candidate_target(&policy, &requirement, "sm_90a", "+ptx86").unwrap();
-        assert!(
-            validate_candidate_target(&policy, &requirement, "sm_75", "+ptx70")
-                .unwrap_err()
-                .to_string()
-                .contains("hardware requirement")
-        );
-        assert!(
-            validate_candidate_target(&policy, &requirement, "sm_80", "+ptx69")
-                .unwrap_err()
-                .to_string()
-                .contains("PTX floor")
-        );
-        for malformed in ["compute_80", "sm_080", "sm_80x"] {
-            assert!(
-                validate_candidate_target(&policy, &requirement, malformed, "+ptx70").is_err(),
-                "{malformed}"
-            );
-        }
-        for malformed in ["ptx70", "+ptx7", "+ptx070"] {
-            assert!(
-                validate_candidate_target(&policy, &requirement, "sm_80", malformed).is_err(),
-                "{malformed}"
-            );
-        }
-
-        let exact = CatalogTargetRequirement {
-            minimum_ptx: "8.7".parse().unwrap(),
-            hardware: CatalogHardwareTarget::AnyOf {
-                alternatives: vec![CatalogHardwareAlternative::ExactArchitecture { sm: 120 }],
-            },
-        };
-        validate_candidate_target(&policy, &exact, "sm_120a", "+ptx87").unwrap();
-        assert!(validate_candidate_target(&policy, &exact, "sm_120a", "+ptx86").is_err());
-        assert!(validate_candidate_target(&policy, &exact, "sm_120", "+ptx87").is_err());
-        assert!(validate_candidate_target(&policy, &exact, "sm_120f", "+ptx87").is_err());
-
-        let family = CatalogTargetRequirement {
-            minimum_ptx: "8.7".parse().unwrap(),
-            hardware: CatalogHardwareTarget::AnyOf {
-                alternatives: vec![CatalogHardwareAlternative::FamilyTarget { sm: 120 }],
-            },
-        };
-        validate_candidate_target(&policy, &family, "sm_120f", "+ptx87").unwrap();
-        assert!(validate_candidate_target(&policy, &family, "sm_120a", "+ptx87").is_err());
-    }
-
-    #[test]
-    fn scalar_conversion_admission_is_closed_and_backend_specific() {
-        let variants = [
-            (
-                "i0368",
-                ScalarConversionRounding::NearestAway,
-                ScalarConversionSaturation::None,
-            ),
-            (
-                "i0369",
-                ScalarConversionRounding::NearestAway,
-                ScalarConversionSaturation::Satfinite,
-            ),
-            (
-                "i0370",
-                ScalarConversionRounding::NearestEven,
-                ScalarConversionSaturation::None,
-            ),
-            (
-                "i0371",
-                ScalarConversionRounding::NearestEven,
-                ScalarConversionSaturation::Relu,
-            ),
-            (
-                "i0372",
-                ScalarConversionRounding::NearestEven,
-                ScalarConversionSaturation::Satfinite,
-            ),
-            (
-                "i0373",
-                ScalarConversionRounding::NearestEven,
-                ScalarConversionSaturation::ReluSatfinite,
-            ),
-            (
-                "i0374",
-                ScalarConversionRounding::TowardZero,
-                ScalarConversionSaturation::None,
-            ),
-            (
-                "i0375",
-                ScalarConversionRounding::TowardZero,
-                ScalarConversionSaturation::Relu,
-            ),
-            (
-                "i0376",
-                ScalarConversionRounding::TowardZero,
-                ScalarConversionSaturation::Satfinite,
-            ),
-            (
-                "i0377",
-                ScalarConversionRounding::TowardZero,
-                ScalarConversionSaturation::ReluSatfinite,
-            ),
-        ];
-        let admission = ScalarConversionAdmission {
-            llvm_evidence_profile: "llvm-scalar".into(),
-            libnvvm_evidence_profile: "libnvvm-scalar".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants: variants
-                .iter()
-                .map(
-                    |(abi_id, rounding, saturation)| ScalarConversionAdmissionVariant {
-                        abi_id: (*abi_id).into(),
-                        rounding: *rounding,
-                        saturation: *saturation,
-                    },
-                )
-                .collect(),
-        };
-
-        let records = expand_scalar_conversion_admission(&admission).unwrap();
-        assert_eq!(records.len(), 10);
-        for (record, (abi_id, rounding, saturation)) in records.iter().zip(variants) {
-            assert_eq!(record.abi_id, abi_id);
-            assert_eq!(record.rust_arguments, ["f32"]);
-            assert_eq!(record.rust_result, "u32");
-            assert_eq!(
-                record.compatibility_rust_paths,
-                [format!("cuda_device::convert::{}", record.rust_name)]
-            );
-            let conversion = record.scalar_conversion.as_ref().unwrap();
-            assert_eq!(conversion.rounding, rounding);
-            assert_eq!(conversion.saturation, saturation);
-            assert!(record.backend_lowerings.iter().any(|lowering| {
-                lowering.backend == IntrinsicBackend::LlvmNvptx
-                    && lowering.mechanism == BackendLoweringMechanism::TypedNvvm
-            }));
-            assert!(record.backend_lowerings.iter().any(|lowering| {
-                lowering.backend == IntrinsicBackend::LibNvvm
-                    && lowering.mechanism == BackendLoweringMechanism::InlinePtx
-            }));
-        }
-
-        let mut reordered = admission.clone();
-        reordered.variants.swap(0, 1);
-        assert!(
-            expand_scalar_conversion_admission(&reordered)
-                .unwrap_err()
-                .to_string()
-                .contains("canonical ten variants")
-        );
-    }
-
-    #[test]
-    fn scalar_arithmetic_admission_is_closed_and_selects_only_direct_ptx() {
-        let variants = canonical_scalar_arithmetic_variants();
-        let admission = ScalarArithmeticAdmission {
-            llvm_evidence_profile: "llvm-scalar-arithmetic".into(),
-            libnvvm_evidence_profile: "libnvvm-scalar-arithmetic".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants: variants
-                .iter()
-                .copied()
-                .enumerate()
-                .map(
-                    |(index, variant)| crate::model::ScalarArithmeticAdmissionVariant {
-                        abi_id: format!("i{:04}", 390 + index),
-                        format: variant.0,
-                        operation: variant.1,
-                        rounding: variant.2,
-                        subnormal: variant.3,
-                        saturation: variant.4,
-                    },
-                )
-                .collect(),
-        };
-        let records = expand_scalar_arithmetic_admission(&admission).unwrap();
-        assert_eq!(records.len(), 64);
-        assert_eq!(records.first().unwrap().id, "mul_rn_f64");
-        assert_eq!(records.first().unwrap().abi_id, "i0390");
-        assert_eq!(records.last().unwrap().id, "add_rp_ftz_sat_f32");
-        assert_eq!(records.last().unwrap().abi_id, "i0453");
-        validate_unique_overlay(&records, 1).unwrap();
-        let llvm_inline_count = records
-            .iter()
-            .filter(|record| {
-                record.backend_lowerings.iter().any(|lowering| {
-                    lowering.backend == IntrinsicBackend::LlvmNvptx
-                        && lowering.mechanism == BackendLoweringMechanism::InlinePtx
-                })
-            })
-            .count();
-        assert_eq!(llvm_inline_count, 16);
-        assert!(records.iter().all(|record| {
-            let expected =
-                if record.scalar_arithmetic.as_ref().is_some_and(|arithmetic| {
-                    arithmetic.saturation == ScalarArithmeticSaturation::Sat
-                }) {
-                    BackendLoweringMechanism::InlinePtx
-                } else {
-                    BackendLoweringMechanism::TypedNvvm
-                };
-            record.backend_lowerings.iter().any(|lowering| {
-                lowering.backend == IntrinsicBackend::LlvmNvptx && lowering.mechanism == expected
-            })
-        }));
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .into_iter()
-            .map(|record| (record.source_record.clone(), record))
-            .collect::<BTreeMap<_, _>>();
-        let mut mixed_count = 0;
-        let mut add_two_selection_count = 0;
-        let mut add_six_selection_count = 0;
-        for record in &records {
-            let declaration = &declarations[record.source_record.as_ref().unwrap()];
-            validate_imported_policy(record, declaration).unwrap();
-            let selected = declaration
-                .selections
-                .iter()
-                .filter(|selection| selection_matches_policy(record, selection).unwrap())
-                .collect::<Vec<_>>();
-            assert_eq!(selected.len(), 1, "{}", record.id);
-            if declaration.selections.len() == 3 {
-                mixed_count += 1;
-            }
-            if record
-                .scalar_arithmetic
-                .as_ref()
-                .is_some_and(|contract| contract.operation == ScalarArithmeticOperation::Add)
-            {
-                match declaration.selections.len() {
-                    2 => add_two_selection_count += 1,
-                    6 => add_six_selection_count += 1,
-                    count => panic!("unexpected add selection count {count}"),
-                }
-            }
-        }
-        assert_eq!(mixed_count, 8);
-        assert_eq!(add_two_selection_count, 12);
-        assert_eq!(add_six_selection_count, 8);
-        let add_ftz_sat = records
-            .iter()
-            .find(|record| record.id == "add_rn_ftz_sat_f32")
-            .unwrap();
-        assert_eq!(
-            add_ftz_sat.expected_ptx.modifiers,
-            ["rn", "sat", "ftz", "f32"]
-        );
-
-        let mut non_contiguous_abi = admission.clone();
-        non_contiguous_abi.variants[0].abi_id = "i9999".into();
-        let non_contiguous_records =
-            expand_scalar_arithmetic_admission(&non_contiguous_abi).unwrap();
-        assert_eq!(non_contiguous_records[0].abi_id, "i9999");
-
-        let mut reordered = admission.clone();
-        reordered.variants.swap(0, 1);
-        assert!(
-            expand_scalar_arithmetic_admission(&reordered)
-                .unwrap_err()
-                .to_string()
-                .contains("canonical 64 variants")
-        );
-        assert!(
-            scalar_arithmetic_recipe((
-                ScalarArithmeticFormat::F64,
-                ScalarArithmeticOperation::Fma,
-                ScalarArithmeticRounding::Rn,
-                ScalarArithmeticSubnormal::Ftz,
-                ScalarArithmeticSaturation::None,
-            ))
-            .is_none()
-        );
-    }
-
-    #[test]
-    fn scalar_math_admission_keeps_semantic_order_but_accepts_non_contiguous_abi_ids() {
-        let variants = canonical_scalar_math_variants();
-        let admission = ScalarMathAdmission {
-            llvm_evidence_profile: "llvm-scalar-math".into(),
-            libnvvm_evidence_profile: "libnvvm-scalar-math".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants: variants
-                .iter()
-                .copied()
-                .enumerate()
-                .map(
-                    |(index, variant)| crate::model::ScalarMathAdmissionVariant {
-                        abi_id: format!("i{:04}", 782 + index),
-                        libnvvm_evidence_profile: (index == 40).then(|| "libnvvm-ex2-f16".into()),
-                        format: variant.0,
-                        operation: variant.1,
-                        precision: variant.2,
-                        subnormal: variant.3,
-                    },
-                )
-                .collect(),
-        };
-
-        let records = expand_scalar_math_admission(&admission).unwrap();
-        assert_eq!(records.len(), 41);
-        assert_eq!(records.first().unwrap().abi_id, "i0782");
-        assert_eq!(records.last().unwrap().abi_id, "i0822");
-        assert!(
-            records
-                .iter()
-                .all(|record| record.backend_lowerings.len() == 2)
-        );
-        assert_eq!(
-            records.last().unwrap().backend_lowerings[1].evidence_profile,
-            "libnvvm-ex2-f16"
-        );
-        assert!(records[..40].iter().all(|record| {
-            record.backend_lowerings[1].evidence_profile == "libnvvm-scalar-math"
-        }));
-
-        let mut non_contiguous_abi = admission.clone();
-        non_contiguous_abi.variants[40].abi_id = "i9999".into();
-        let records = expand_scalar_math_admission(&non_contiguous_abi).unwrap();
-        assert_eq!(records.last().unwrap().abi_id, "i9999");
-
-        let mut reordered = admission;
-        reordered.variants.swap(0, 1);
-        assert!(
-            expand_scalar_math_admission(&reordered)
-                .unwrap_err()
-                .to_string()
-                .contains("canonical 41 variants")
-        );
-    }
-
-    #[test]
-    fn checked_in_scalar_math_overlay_pins_the_current_libnvvm_override_set() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let (overlay, _) =
-            read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
-        let scalar_math = overlay
-            .intrinsics
-            .iter()
-            .filter(|record| record.family == "scalar_math")
-            .collect::<Vec<_>>();
-        assert_eq!(scalar_math.len(), 41);
-        assert!(
-            scalar_math
-                .iter()
-                .all(|record| record.backend_lowerings.len() == 2)
-        );
-
-        let family_profile = "cuda-13.3-libnvvm-13.3.33-scalar-math";
-        let overrides = scalar_math
-            .iter()
-            .filter_map(|record| {
-                let libnvvm = record
-                    .backend_lowerings
-                    .iter()
-                    .find(|route| route.backend == IntrinsicBackend::LibNvvm)
-                    .unwrap();
-                (libnvvm.evidence_profile != family_profile).then_some(record.id.as_str())
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(overrides, ["ex2_approx_f16"]);
-    }
-
-    #[test]
-    fn extended_minmax_admission_is_exact_and_fail_closed() {
-        let variants = canonical_extended_minmax_variants();
-        let admission = ExtendedMinMaxAdmission {
-            llvm_evidence_profile: "llvm-extended-minmax".into(),
-            libnvvm_evidence_profile: "libnvvm-extended-minmax".into(),
-            runtime_validation: RuntimeValidation::Unexecuted,
-            variants: variants
-                .iter()
-                .copied()
-                .enumerate()
-                .map(
-                    |(index, variant)| crate::model::ExtendedMinMaxAdmissionVariant {
-                        abi_id: if index < 28 {
-                            format!("i{:04}", 550 + index)
-                        } else {
-                            format!("i{:04}", 830 + index - 28)
-                        },
-                        format: variant.0,
-                        operation: variant.1,
-                        subnormal: variant.2,
-                        nan: variant.3,
-                        xorsign_abs: variant.4,
-                    },
-                )
-                .collect(),
-        };
-        let records = expand_extended_minmax_admission(&admission).unwrap();
-        assert_eq!(records.len(), 52);
-        assert_eq!(records.first().unwrap().id, "min_ftz_f16x2");
-        assert_eq!(records.first().unwrap().abi_id, "i0550");
-        // The first reserved block ends here; the scalar 16-bit forms admitted
-        // afterwards continue at a second base rather than at i0578.
-        assert_eq!(records[27].id, "max_xorsign_abs_f16x2");
-        assert_eq!(records[27].abi_id, "i0577");
-        assert_eq!(records[28].id, "min_f16");
-        assert_eq!(records[28].abi_id, "i0830");
-        assert_eq!(records.last().unwrap().id, "max_nan_xorsign_abs_bf16");
-        assert_eq!(records.last().unwrap().abi_id, "i0853");
-        validate_unique_overlay(&records, 1).unwrap();
-        assert_eq!(
-            records
-                .iter()
-                .filter(|record| record.minimum_sm.as_deref() == Some("sm_80"))
-                .count(),
-            20
-        );
-        assert_eq!(
-            records
-                .iter()
-                .filter(|record| record.minimum_sm.as_deref() == Some("sm_86"))
-                .count(),
-            32
-        );
-        assert!(records.iter().all(|record| {
-            record.backend_lowerings.len() == 2
-                && record
-                    .backend_lowerings
-                    .iter()
-                    .all(|lowering| lowering.mechanism == BackendLoweringMechanism::InlinePtx)
-        }));
-
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let imported: ImportedFile =
-            read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
-        let declarations = imported
-            .intrinsics
-            .into_iter()
-            .map(|record| (record.source_record.clone(), record))
-            .collect::<BTreeMap<_, _>>();
-        for record in &records {
-            let declaration = &declarations[record.source_record.as_ref().unwrap()];
-            assert_eq!(declaration.selections.len(), 1, "{}", record.id);
-            validate_imported_policy(record, declaration).unwrap();
-            assert_eq!(
-                declaration
-                    .selections
-                    .iter()
-                    .filter(|selection| selection_matches_policy(record, selection).unwrap())
-                    .count(),
-                1,
-                "{}",
-                record.id
-            );
-        }
-        let packed_max = records
-            .iter()
-            .find(|record| record.id == "max_nan_bf16x2")
-            .unwrap();
-        assert_eq!(
-            declarations[packed_max.source_record.as_ref().unwrap()].selections[0].source_record,
-            "INT_NVVM_FMAN_NaN_bf16x2"
-        );
-        assert_eq!(
-            declarations["int_nvvm_fmax_ftz_nan_xorsign_abs_f"].selections[0].source_record,
-            "INT_NVVM_FMAX_FTZ_NAN_XORSIGN_ABS_F"
-        );
-        assert!(
-            declarations["int_nvvm_fmax_ftz_nan_xorsign_abs_f"].selections[0]
-                .asm
-                .contains(".NaN.")
-        );
-        for excluded in [
-            "int_nvvm_fmin_ftz_bf16x2",
-            "int_nvvm_fmax_ftz_nan_bf16x2",
-            "int_nvvm_fmin_f",
-            "int_nvvm_fmax_nan_f",
-        ] {
-            assert!(declarations[excluded].selections.is_empty(), "{excluded}");
-            assert!(
-                records
-                    .iter()
-                    .all(|record| record.source_record.as_deref() != Some(excluded)),
-                "{excluded} was admitted without an instruction selection"
-            );
-        }
-
-        let catalog: CatalogFile = read_json(&repo_root.join("intrinsics/catalog.json")).unwrap();
-        for id in ["min_f16x2", "max_f16x2", "min_bf16x2", "max_bf16x2"] {
-            assert_eq!(
-                catalog
-                    .intrinsics
-                    .iter()
-                    .find(|record| record.id == id)
-                    .unwrap()
-                    .family,
-                "packed_alu"
-            );
-            assert!(records.iter().all(|record| record.id != id));
-        }
-
-        let mut non_contiguous_abi = admission.clone();
-        non_contiguous_abi.variants[0].abi_id = "i9999".into();
-        let non_contiguous_records = expand_extended_minmax_admission(&non_contiguous_abi).unwrap();
-        assert_eq!(non_contiguous_records[0].abi_id, "i9999");
-
-        let mut reordered = admission.clone();
-        reordered.variants.swap(0, 1);
-        assert!(
-            expand_extended_minmax_admission(&reordered)
-                .unwrap_err()
-                .to_string()
-                .contains("exact canonical 28 variants")
-        );
-        assert!(
-            extended_minmax_recipe((
-                ExtendedMinMaxFormat::Bf16x2,
-                ExtendedMinMaxOperation::Min,
-                ExtendedMinMaxSubnormal::Ftz,
-                ExtendedMinMaxNan::Nan,
-                false,
-            ))
-            .is_none()
-        );
-        let mut changed = declarations["int_nvvm_fmin_ftz_f16x2"].clone();
-        changed.selections[0].predicates.swap(0, 1);
-        assert!(validate_imported_policy(&records[0], &changed).is_err());
-    }
-
-    struct CandidateTestRepo(PathBuf);
-
-    impl Drop for CandidateTestRepo {
-        fn drop(&mut self) {
-            let _ = fs::remove_dir_all(&self.0);
-        }
-    }
-
-    fn repo_without_evidence() -> CandidateTestRepo {
-        use std::sync::atomic::{AtomicU64, Ordering};
-
-        static NEXT: AtomicU64 = AtomicU64::new(0);
-        let source = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let root = std::env::temp_dir().join(format!(
-            "cuda-intrinsics-candidate-{}-{}",
-            std::process::id(),
-            NEXT.fetch_add(1, Ordering::Relaxed)
-        ));
-        let input = root.join("intrinsics");
-        fs::create_dir_all(input.join("overlay")).unwrap();
-        for name in [
-            "upstream.lock",
-            "imported.json",
-            "overlay.toml",
-            "abi-v1.toml",
-        ] {
-            fs::copy(source.join("intrinsics").join(name), input.join(name)).unwrap();
-        }
-        for entry in fs::read_dir(source.join("intrinsics/overlay")).unwrap() {
-            let entry = entry.unwrap();
-            if entry.path().extension().and_then(|value| value.to_str()) == Some("toml") {
-                fs::copy(entry.path(), input.join("overlay").join(entry.file_name())).unwrap();
-            }
-        }
-        CandidateTestRepo(root)
-    }
-
-    #[test]
-    fn candidate_resolution_is_the_only_path_that_can_omit_evidence() {
-        let repo = repo_without_evidence();
-        let candidate = resolve_candidate(
-            &repo.0,
-            "thread_idx_x",
-            "LLVM version candidate",
-            &"a".repeat(64),
-            "sm_80",
-            "+ptx70",
-        )
-        .unwrap();
-        assert_eq!(candidate.catalog.intrinsics.len(), 1);
-        assert_eq!(candidate.catalog.intrinsics[0].id, "thread_idx_x");
-        assert_eq!(candidate.catalog.intrinsics[0].backend.status, "candidate");
-
-        let scalar = resolve_candidate(
-            &repo.0,
-            "i0390",
-            "LLVM version candidate",
-            &"a".repeat(64),
-            "sm_80",
-            "+ptx70",
-        )
-        .unwrap();
-        assert_eq!(scalar.catalog.intrinsics[0].id, "mul_rn_f64");
-        assert!(candidate.catalog.inputs.evidence_sha256.is_empty());
-
-        for (dense_id, abi_id) in [
-            ("mma_m16n8k32_f32_e2m1_e2m1", "i0454"),
-            ("mma_m16n8k32_f16_e2m1_e2m1", "i0479"),
-        ] {
-            let dense_by_name = resolve_candidate(
-                &repo.0,
-                dense_id,
-                "LLVM version candidate",
-                &"a".repeat(64),
-                "sm_120f",
-                "+ptx88",
-            )
-            .unwrap();
-            let dense_by_abi = resolve_candidate(
-                &repo.0,
-                abi_id,
-                "LLVM version candidate",
-                &"a".repeat(64),
-                "sm_120f",
-                "+ptx88",
-            )
-            .unwrap();
-            assert_eq!(
-                dense_by_name.catalog.intrinsics,
-                dense_by_abi.catalog.intrinsics
-            );
-            for lookup in [dense_id, abi_id] {
-                let error = resolve_candidate(
-                    &repo.0,
-                    lookup,
-                    "LLVM version candidate",
-                    &"a".repeat(64),
-                    "sm_120f",
-                    "+ptx87",
-                )
-                .unwrap_err();
-                assert!(error.to_string().contains(dense_id), "{error:#}");
-            }
-        }
-
-        let error = resolve(&repo.0).unwrap_err();
-        assert!(
-            error.to_string().contains("intrinsics/evidence"),
-            "{error:#}"
-        );
-        let error = resolve_candidate(
-            &repo.0,
-            "not_an_intrinsic",
-            "LLVM version candidate",
-            &"a".repeat(64),
-            "sm_80",
-            "+ptx70",
-        )
-        .unwrap_err();
-        assert!(error.to_string().contains("unknown overlay intrinsic"));
-    }
-
-    #[test]
-    fn candidate_resolution_cannot_change_normal_catalog_bytes() {
-        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
-        let before = crate::util::pretty_json(&resolve(&repo_root).unwrap()).unwrap();
-        resolve_candidate(
-            &repo_root,
-            "thread_idx_x",
-            "LLVM version candidate",
-            &"a".repeat(64),
-            "sm_80",
-            "+ptx70",
-        )
-        .unwrap();
-        let after = crate::util::pretty_json(&resolve(&repo_root).unwrap()).unwrap();
-        assert_eq!(before.as_bytes(), after.as_bytes());
-    }
-}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/abi_ledger.rs b/crates/cuda-intrinsics-gen/src/resolve/abi_ledger.rs
new file mode 100644
index 0000000000..0e2167de11
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/abi_ledger.rs
@@ -0,0 +1,231 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    AbiLedgerEntry, AbiLedgerFile, AbiRawRustSignature, OverlayFile, OverlayIntrinsic,
+};
+use anyhow::{Context, Result, bail, ensure};
+use std::collections::{BTreeMap, BTreeSet};
+
+use super::guards::*;
+
+pub(super) struct AbiLedgerIndex<'a> {
+    by_catalog_id: BTreeMap<&'a str, &'a AbiLedgerEntry>,
+}
+
+impl<'a> AbiLedgerIndex<'a> {
+    fn new(ledger: &'a AbiLedgerFile) -> Result<Self> {
+        let mut by_catalog_id = BTreeMap::new();
+        for entry in &ledger.entries {
+            ensure!(
+                by_catalog_id
+                    .insert(entry.catalog_id.as_str(), entry)
+                    .is_none(),
+                "duplicate ABI ledger catalog ID: {}",
+                entry.catalog_id
+            );
+        }
+        Ok(Self { by_catalog_id })
+    }
+
+    fn active(&self, catalog_id: &str) -> Result<&'a AbiLedgerEntry> {
+        let entry = self
+            .by_catalog_id
+            .get(catalog_id)
+            .copied()
+            .with_context(|| format!("generated intrinsic {catalog_id} has no ABI ledger entry"))?;
+        ensure!(
+            entry.status == "active",
+            "generated intrinsic {catalog_id} maps to non-active ABI ledger entry {}",
+            entry.abi_id
+        );
+        Ok(entry)
+    }
+}
+
+pub(super) fn bind_generated_abi_ids(
+    overlay: &mut OverlayFile,
+    ledger: &AbiLedgerFile,
+) -> Result<()> {
+    let index = AbiLedgerIndex::new(ledger)?;
+    for record in overlay
+        .intrinsics
+        .iter_mut()
+        .filter(|record| record.abi_id.is_empty())
+    {
+        let entry = index.active(&record.id)?;
+        ensure!(
+            entry.operation_key == record.operation_key,
+            "generated intrinsic {} operation key mismatch: ledger {:?}, derived {:?}",
+            record.id,
+            entry.operation_key,
+            record.operation_key
+        );
+        let derived_signature = raw_rust_signature(record);
+        ensure!(
+            entry.raw_rust_signature == derived_signature,
+            "generated intrinsic {} raw Rust signature mismatch: ledger {:?}, derived {:?}",
+            record.id,
+            entry.raw_rust_signature,
+            derived_signature
+        );
+        record.abi_id.clone_from(&entry.abi_id);
+    }
+    Ok(())
+}
+
+pub(super) fn validate_abi_ledger(overlay: &OverlayFile, ledger: &AbiLedgerFile) -> Result<()> {
+    ensure!(
+        ledger.schema == 1,
+        "unsupported ABI ledger schema {}",
+        ledger.schema
+    );
+    ensure!(
+        ledger.intrinsic_abi == overlay.intrinsic_abi,
+        "ABI ledger v{} does not match overlay ABI v{}",
+        ledger.intrinsic_abi,
+        overlay.intrinsic_abi
+    );
+    ensure!(!ledger.entries.is_empty(), "ABI ledger contains no entries");
+
+    let overlay_by_abi_id: BTreeMap<_, _> = overlay
+        .intrinsics
+        .iter()
+        .map(|record| (record.abi_id.as_str(), record))
+        .collect();
+    let mut abi_ids = BTreeSet::new();
+    let mut catalog_ids = BTreeSet::new();
+    let mut operation_keys = BTreeSet::new();
+    let mut previous_abi_id: Option<&str> = None;
+    for entry in &ledger.entries {
+        validate_abi_id(&entry.abi_id)?;
+        if let Some(previous) = previous_abi_id {
+            ensure!(
+                previous < entry.abi_id.as_str(),
+                "ABI ledger IDs must be unique and append-only in ascending order: {} follows {}",
+                entry.abi_id,
+                previous
+            );
+        }
+        previous_abi_id = Some(&entry.abi_id);
+        insert_unique(&mut abi_ids, &entry.abi_id, "ABI ledger ID")?;
+        insert_unique(&mut catalog_ids, &entry.catalog_id, "ABI ledger catalog ID")?;
+        validate_operation_key(&entry.operation_key)?;
+        insert_unique(
+            &mut operation_keys,
+            &entry.operation_key,
+            "ABI ledger operation key",
+        )?;
+        ensure!(
+            !entry.catalog_id.is_empty()
+                && !entry.raw_rust_signature.result.is_empty()
+                && entry
+                    .raw_rust_signature
+                    .arguments
+                    .iter()
+                    .all(|argument| !argument.is_empty()),
+            "ABI ledger entry {} has incomplete identity data",
+            entry.abi_id
+        );
+
+        let overlay_record = overlay_by_abi_id.get(entry.abi_id.as_str()).copied();
+        match entry.status.as_str() {
+            "active" => {
+                let record = overlay_record.with_context(|| {
+                    format!(
+                        "active ABI ledger entry {} ({}) has no overlay record",
+                        entry.abi_id, entry.catalog_id
+                    )
+                })?;
+                validate_active_ledger_entry(entry, record)?;
+            }
+            "tombstone" => ensure!(
+                overlay_record.is_none(),
+                "tombstoned ABI ID {} cannot reappear in the overlay",
+                entry.abi_id
+            ),
+            status => bail!(
+                "ABI ledger entry {} has unsupported status {status:?}; expected active or tombstone",
+                entry.abi_id
+            ),
+        }
+    }
+
+    for record in &overlay.intrinsics {
+        ensure!(
+            abi_ids.contains(&record.abi_id),
+            "overlay intrinsic {} uses ABI ID {} with no ledger entry",
+            record.id,
+            record.abi_id
+        );
+    }
+    Ok(())
+}
+
+pub(super) fn validate_active_ledger_entry(
+    entry: &AbiLedgerEntry,
+    record: &OverlayIntrinsic,
+) -> Result<()> {
+    let comparisons = [
+        ("catalog ID", entry.catalog_id.as_str(), record.id.as_str()),
+        (
+            "operation key",
+            entry.operation_key.as_str(),
+            record.operation_key.as_str(),
+        ),
+    ];
+    for (field, ledger_value, overlay_value) in comparisons {
+        ensure!(
+            ledger_value == overlay_value,
+            "ABI ledger {} {field} mismatch: ledger {ledger_value:?}, overlay {overlay_value:?}",
+            entry.abi_id
+        );
+    }
+    let expected_signature = raw_rust_signature(record);
+    ensure!(
+        entry.raw_rust_signature == expected_signature,
+        "ABI ledger {} raw Rust signature mismatch: ledger {:?}, overlay {:?}",
+        entry.abi_id,
+        entry.raw_rust_signature,
+        expected_signature
+    );
+    Ok(())
+}
+
+pub(super) fn raw_rust_signature(record: &OverlayIntrinsic) -> AbiRawRustSignature {
+    AbiRawRustSignature {
+        safe: record.safe,
+        arguments: record.rust_arguments.clone(),
+        result: record.rust_result.clone(),
+    }
+}
+
+pub(super) fn validate_abi_id(abi_id: &str) -> Result<()> {
+    ensure!(
+        abi_id.len() == 5
+            && abi_id.starts_with('i')
+            && abi_id[1..].bytes().all(|byte| byte.is_ascii_digit()),
+        "intrinsic ABI ID `{abi_id}` must use the stable `iNNNN` form"
+    );
+    Ok(())
+}
+
+pub(crate) fn validate_operation_key(operation_key: &str) -> Result<()> {
+    ensure!(
+        !operation_key.is_empty()
+            && operation_key.split('.').all(|segment| {
+                !segment.is_empty()
+                    && segment.bytes().all(|byte| {
+                        byte.is_ascii_lowercase() || byte.is_ascii_digit() || byte == b'_'
+                    })
+            }),
+        "intrinsic operation key `{operation_key}` must contain dot-separated lowercase semantic components"
+    );
+    Ok(())
+}
+
+pub(super) fn canonical_rust_path(intrinsic_abi: u32, abi_id: &str) -> String {
+    format!("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v{intrinsic_abi}::{abi_id}")
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/driver.rs b/crates/cuda-intrinsics-gen/src/resolve/driver.rs
new file mode 100644
index 0000000000..41a224c375
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/driver.rs
@@ -0,0 +1,765 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::extract::{IMPORTED_SCHEMA, read_upstream_lock};
+use crate::model::{
+    AbiLedgerFile, BackendLoweringMechanism, CatalogBackend, CatalogFile,
+    CatalogHardwareAlternative, CatalogHardwareTarget, CatalogInputs, CatalogSource,
+    CatalogTargetRequirement, ExecutionControlOperation, ImportedFile, ImportedIntrinsic,
+    IntrinsicBackend, IntrinsicSource, OverlayFile, OverlayIntrinsic, PtxVersion,
+};
+#[cfg(test)]
+use crate::model::{
+    CatalogBackendLowering, ClcAdmission, ClcOperation, RuntimeValidation, Tcgen05Admission,
+    Tcgen05LdAdmissionVariant, Tcgen05Operation, Tcgen05StAdmissionVariant, TmaAdmission,
+};
+use crate::util::{read_json, sha256_file};
+#[cfg(test)]
+use anyhow::bail;
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeMap;
+use std::fs;
+use std::path::Path;
+
+use super::abi_ledger::*;
+use super::evidence::*;
+use super::families::*;
+use super::materialize::*;
+use super::overlay::*;
+use super::policy::*;
+use super::targets::*;
+
+pub(super) struct ResolutionBase {
+    pub(super) overlay: OverlayFile,
+    pub(super) imported: ImportedFile,
+    pub(super) source: CatalogSource,
+    pub(super) imported_sha256: String,
+    pub(super) overlay_sha256: String,
+    pub(super) abi_ledger_sha256: String,
+}
+
+#[derive(Debug)]
+pub(crate) struct CandidateResolution {
+    pub catalog: CatalogFile,
+    pub mechanism: BackendLoweringMechanism,
+    pub requirement: CatalogTargetRequirement,
+}
+
+pub(super) fn primary_evidence_profile<'a>(
+    policy: &'a OverlayIntrinsic,
+    default_profile: &'a str,
+) -> Result<&'a str> {
+    let needs_family_profile = policy.tma.is_some()
+        || ExecutionControlOperation::from_catalog_id(&policy.id).is_some()
+        || policy
+            .tcgen05
+            .as_ref()
+            .and_then(|tcgen05| tcgen05.mma.as_ref())
+            .is_some();
+    if !needs_family_profile {
+        return Ok(default_profile);
+    }
+    policy
+        .backend_lowerings
+        .iter()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+        .map(|lowering| lowering.evidence_profile.as_str())
+        .with_context(|| format!("{} has no LLVM family evidence route", policy.id))
+}
+
+pub fn resolve(repo_root: &Path) -> Result<CatalogFile> {
+    let base = load_resolution_base(repo_root)?;
+    let ResolutionBase {
+        overlay,
+        imported,
+        source,
+        imported_sha256,
+        overlay_sha256,
+        abi_ledger_sha256,
+    } = base;
+    let imported_by_record = index_imported_intrinsics(&imported)?;
+    let llvm_revision = source.llvm_revision.clone();
+    let (evidence_files, evidence_hashes) = read_evidence(repo_root)?;
+    let evidence_by_profile_id = index_evidence(&evidence_files, &llvm_revision)?;
+
+    let mut intrinsics = Vec::with_capacity(overlay.intrinsics.len());
+    for policy in &overlay.intrinsics {
+        let source = resolve_policy_source(policy)?;
+        let declaration = resolve_imported_declaration(policy, &source, &imported_by_record)?;
+        validate_special_register_llvm_exclusion(policy, &imported_by_record)?;
+        validate_policy(policy, &source, declaration, overlay.intrinsic_abi)?;
+        let primary_profile = primary_evidence_profile(policy, &overlay.backend_profile)?;
+        let evidence = evidence_by_profile_id
+            .get(&(primary_profile, policy.id.as_str()))
+            .with_context(|| {
+                format!(
+                    "intrinsic {} has no evidence record in selected profile {}",
+                    policy.id, primary_profile
+                )
+            })?;
+        validate_evidence(policy, evidence, None)?;
+        let backend_lowerings = resolve_backend_lowerings(policy, &evidence_by_profile_id)?;
+        intrinsics.push(resolve_record(
+            policy,
+            source,
+            declaration,
+            evidence.record,
+            primary_profile,
+            evidence.backend_version,
+            evidence.backend_sha256,
+            backend_lowerings,
+            overlay.intrinsic_abi,
+        )?);
+    }
+    for (_, evidence_id) in evidence_by_profile_id.keys() {
+        ensure!(
+            overlay
+                .intrinsics
+                .iter()
+                .any(|record| record.id == *evidence_id),
+            "evidence exists for unknown catalog ID {evidence_id}"
+        );
+    }
+
+    Ok(CatalogFile {
+        schema: CATALOG_SCHEMA,
+        catalog_version: overlay.catalog_version,
+        intrinsic_abi: overlay.intrinsic_abi,
+        generator_version: env!("CARGO_PKG_VERSION").to_owned(),
+        source,
+        inputs: CatalogInputs {
+            imported_sha256,
+            overlay_sha256,
+            abi_ledger_sha256,
+            evidence_sha256: evidence_hashes,
+        },
+        intrinsics,
+    })
+}
+
+#[cfg(test)]
+pub(crate) fn test_catalog_with_clc(repo_root: &Path) -> Result<CatalogFile> {
+    let mut catalog = resolve(repo_root)?;
+    let active_count = catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "clc")
+        .count();
+    if active_count != 0 {
+        ensure!(
+            active_count == 6,
+            "active CLC family must contain six records"
+        );
+        return Ok(catalog);
+    }
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json"))?;
+    let imported_by_record = index_imported_intrinsics(&imported)?;
+    let operations = [
+        ClcOperation::TryCancel,
+        ClcOperation::TryCancelMulticast,
+        ClcOperation::QueryIsCanceled,
+        ClcOperation::QueryGetFirstCtaidX,
+        ClcOperation::QueryGetFirstCtaidY,
+        ClcOperation::QueryGetFirstCtaidZ,
+    ];
+    let admission = ClcAdmission {
+        llvm_evidence_profile: "llvm-clc-test".into(),
+        libnvvm_evidence_profile: "libnvvm-clc-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: operations
+            .into_iter()
+            .map(|operation| crate::model::ClcAdmissionVariant {
+                abi_id: clc_recipe(operation).abi_id.into(),
+                operation,
+            })
+            .collect(),
+    };
+    for policy in expand_clc_admission(&admission)? {
+        let source = resolve_policy_source(&policy)?;
+        let declaration = resolve_imported_declaration(&policy, &source, &imported_by_record)?;
+        validate_policy(&policy, &source, declaration, catalog.intrinsic_abi)?;
+        let backend_lowerings = policy
+            .backend_lowerings
+            .iter()
+            .map(|lowering| {
+                Ok(CatalogBackendLowering {
+                    backend: lowering.backend,
+                    mechanism: lowering.mechanism,
+                    evidence_profile: lowering.evidence_profile.clone(),
+                    target: backend_target_requirement(&policy, lowering)?,
+                    version: "test".into(),
+                    sha256: "0".repeat(64),
+                    artifact_path: None,
+                    build_id_prefix: None,
+                    status: "validated".into(),
+                    stages: vec![],
+                })
+            })
+            .collect::<Result<Vec<_>>>()?;
+        catalog.intrinsics.push(materialize_record(
+            &policy,
+            source,
+            declaration,
+            CatalogBackend {
+                profile: "clc-test".into(),
+                version: "test".into(),
+                sha256: "0".repeat(64),
+                status: "validated".into(),
+                target_triple: "nvptx64-nvidia-cuda".into(),
+                gpu_target: "sm_100".into(),
+                ptx_feature: "+ptx86".into(),
+            },
+            backend_lowerings,
+            catalog.intrinsic_abi,
+        )?);
+    }
+    catalog
+        .intrinsics
+        .sort_by(|left, right| left.id.cmp(&right.id));
+    Ok(catalog)
+}
+
+#[cfg(test)]
+pub(crate) fn test_catalog_with_tma(repo_root: &Path) -> Result<CatalogFile> {
+    let mut catalog = resolve(repo_root)?;
+    let active_count = catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.tma.is_some())
+        .count();
+    let expected_count = TMA_OPERATIONS.len() + tma_reduction_matrix().len();
+    if active_count == expected_count {
+        return Ok(catalog);
+    }
+    ensure!(
+        active_count == 0 || active_count == TMA_OPERATIONS.len(),
+        "active TMA catalog has {active_count} records; expected 0, {} base records, or {expected_count} total records",
+        TMA_OPERATIONS.len()
+    );
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json"))?;
+    let imported_by_record = index_imported_intrinsics(&imported)?;
+    let admission = TmaAdmission {
+        llvm_evidence_profile: "llvm-tma-test".into(),
+        libnvvm_evidence_profile: "libnvvm-tma-test".into(),
+        reduce_llvm_evidence_profile: Some("llvm-tma-reduce-test".into()),
+        reduce_libnvvm_evidence_profile: Some("libnvvm-tma-reduce-test".into()),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: TMA_OPERATIONS
+            .into_iter()
+            .map(|operation| crate::model::TmaAdmissionVariant {
+                abi_id: tma_recipe(operation).abi_id.into(),
+                operation,
+            })
+            .collect(),
+        reduce_variants: tma_reduction_admission_variants(),
+    };
+    for policy in expand_tma_admission(&admission)? {
+        if catalog
+            .intrinsics
+            .iter()
+            .any(|record| record.id.as_str() == policy.id.as_str())
+        {
+            continue;
+        }
+        let source = resolve_policy_source(&policy)?;
+        let declaration = resolve_imported_declaration(&policy, &source, &imported_by_record)?;
+        validate_policy(&policy, &source, declaration, catalog.intrinsic_abi)?;
+        let backend_lowerings = policy
+            .backend_lowerings
+            .iter()
+            .map(|lowering| {
+                Ok(CatalogBackendLowering {
+                    backend: lowering.backend,
+                    mechanism: lowering.mechanism,
+                    evidence_profile: lowering.evidence_profile.clone(),
+                    target: backend_target_requirement(&policy, lowering)?,
+                    version: "test".into(),
+                    sha256: "0".repeat(64),
+                    artifact_path: None,
+                    build_id_prefix: None,
+                    status: "validated".into(),
+                    stages: vec![],
+                })
+            })
+            .collect::<Result<Vec<_>>>()?;
+        catalog.intrinsics.push(materialize_record(
+            &policy,
+            source,
+            declaration,
+            CatalogBackend {
+                profile: "tma-test".into(),
+                version: "test".into(),
+                sha256: "0".repeat(64),
+                status: "validated".into(),
+                target_triple: "nvptx64-nvidia-cuda".into(),
+                gpu_target: "sm_90".into(),
+                ptx_feature: "+ptx80".into(),
+            },
+            backend_lowerings,
+            catalog.intrinsic_abi,
+        )?);
+    }
+    catalog
+        .intrinsics
+        .sort_by(|left, right| left.id.cmp(&right.id));
+    Ok(catalog)
+}
+
+#[cfg(test)]
+pub(crate) fn test_catalog_with_tcgen05(repo_root: &Path) -> Result<CatalogFile> {
+    let mut catalog = resolve(repo_root)?;
+    let active_count = catalog
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "tcgen05")
+        .count();
+    match active_count {
+        233 => return Ok(catalog),
+        0 => {}
+        count => bail!("active tcgen05 catalog has {count} of 233 records"),
+    }
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json"))?;
+    let imported_by_record = index_imported_intrinsics(&imported)?;
+    let operations = [
+        Tcgen05Operation::Alloc,
+        Tcgen05Operation::Dealloc,
+        Tcgen05Operation::RelinquishAllocPermit,
+        Tcgen05Operation::FenceBeforeThreadSync,
+        Tcgen05Operation::FenceAfterThreadSync,
+        Tcgen05Operation::Commit,
+        Tcgen05Operation::CommitSharedCluster,
+        Tcgen05Operation::MmaWsF16,
+        Tcgen05Operation::MmaF16,
+        Tcgen05Operation::MmaWsBf16,
+        Tcgen05Operation::MmaWsTf32,
+        Tcgen05Operation::CpSmemToTmem,
+        Tcgen05Operation::Ld16x256bX8Pure,
+        Tcgen05Operation::Ld16x256bPure,
+        Tcgen05Operation::LoadWait,
+        Tcgen05Operation::StoreWait,
+        Tcgen05Operation::AllocCg2,
+        Tcgen05Operation::DeallocCg2,
+        Tcgen05Operation::RelinquishAllocPermitCg2,
+        Tcgen05Operation::MmaF16Cg2,
+        Tcgen05Operation::CommitCg2,
+        Tcgen05Operation::CommitSharedClusterCg2,
+        Tcgen05Operation::CommitMulticastCg2,
+        Tcgen05Operation::CpSmemToTmemCg2,
+        Tcgen05Operation::CommitMulticast,
+        Tcgen05Operation::ShiftDown,
+        Tcgen05Operation::ShiftDownCg2,
+    ];
+    let admission = Tcgen05Admission {
+        llvm_evidence_profile: "llvm-tcgen05-test".into(),
+        libnvvm_evidence_profile: "libnvvm-tcgen05-test".into(),
+        cp_llvm_evidence_profile: None,
+        cp_libnvvm_evidence_profile: None,
+        ld_llvm_evidence_profile: None,
+        ld_libnvvm_evidence_profile: None,
+        st_llvm_evidence_profile: None,
+        st_libnvvm_evidence_profile: None,
+        offset_llvm_evidence_profile: Some("llvm-tcgen05-offset-test".into()),
+        offset_libnvvm_evidence_profile: Some("libnvvm-tcgen05-offset-test".into()),
+        control_llvm_evidence_profile: Some("llvm-tcgen05-control-test".into()),
+        control_libnvvm_evidence_profile: Some("libnvvm-tcgen05-control-test".into()),
+        mma_llvm_evidence_profile: None,
+        mma_libnvvm_evidence_profile: None,
+        mma_llvm_target_contracts: vec![],
+        mma_libnvvm_target_contracts: vec![],
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: operations
+            .into_iter()
+            .map(|operation| crate::model::Tcgen05AdmissionVariant {
+                abi_id: tcgen05_recipe(operation).abi_id.into(),
+                operation,
+            })
+            .collect(),
+        cp_variants: vec![],
+        ld_variants: vec![],
+        st_variants: vec![],
+        ld_offset_variants: TCGEN05_OFFSET_LDST_VARIANTS
+            .into_iter()
+            .flat_map(|(shape, multiplicity)| {
+                [false, true]
+                    .into_iter()
+                    .map(move |pack16| (shape, multiplicity, pack16))
+            })
+            .enumerate()
+            .map(
+                |(index, (shape, multiplicity, pack16))| Tcgen05LdAdmissionVariant {
+                    abi_id: format!("i{:04}", 728 + index),
+                    shape,
+                    multiplicity,
+                    pack16,
+                },
+            )
+            .collect(),
+        st_offset_variants: TCGEN05_OFFSET_LDST_VARIANTS
+            .into_iter()
+            .flat_map(|(shape, multiplicity)| {
+                [false, true]
+                    .into_iter()
+                    .map(move |unpack16| (shape, multiplicity, unpack16))
+            })
+            .enumerate()
+            .map(
+                |(index, (shape, multiplicity, unpack16))| Tcgen05StAdmissionVariant {
+                    abi_id: format!("i{:04}", 744 + index),
+                    shape,
+                    multiplicity,
+                    unpack16,
+                },
+            )
+            .collect(),
+        mma_variants: vec![],
+    };
+    for policy in expand_tcgen05_admission(&admission)? {
+        let source = resolve_policy_source(&policy)?;
+        let declaration = resolve_imported_declaration(&policy, &source, &imported_by_record)?;
+        validate_policy(&policy, &source, declaration, catalog.intrinsic_abi)?;
+        let backend_lowerings = policy
+            .backend_lowerings
+            .iter()
+            .map(|lowering| {
+                Ok(CatalogBackendLowering {
+                    backend: lowering.backend,
+                    mechanism: lowering.mechanism,
+                    evidence_profile: lowering.evidence_profile.clone(),
+                    target: backend_target_requirement(&policy, lowering)?,
+                    version: "test".into(),
+                    sha256: "0".repeat(64),
+                    artifact_path: None,
+                    build_id_prefix: None,
+                    status: "validated".into(),
+                    stages: vec![],
+                })
+            })
+            .collect::<Result<Vec<_>>>()?;
+        catalog.intrinsics.push(materialize_record(
+            &policy,
+            source,
+            declaration,
+            CatalogBackend {
+                profile: "tcgen05-test".into(),
+                version: "test".into(),
+                sha256: "0".repeat(64),
+                status: "validated".into(),
+                target_triple: "nvptx64-nvidia-cuda".into(),
+                gpu_target: "sm_100a".into(),
+                ptx_feature: "+ptx86".into(),
+            },
+            backend_lowerings,
+            catalog.intrinsic_abi,
+        )?);
+    }
+    catalog
+        .intrinsics
+        .sort_by(|left, right| left.id.cmp(&right.id));
+    Ok(catalog)
+}
+
+pub(super) fn load_resolution_base(repo_root: &Path) -> Result<ResolutionBase> {
+    let lock = read_upstream_lock(repo_root)?;
+    let imported_path = repo_root.join("intrinsics/imported.json");
+    let overlay_path = repo_root.join("intrinsics/overlay.toml");
+    let imported: ImportedFile = read_json(&imported_path)?;
+    let (mut overlay, overlay_sha256) = read_overlay(repo_root, &overlay_path)?;
+    let ledger_path = repo_root.join(format!("intrinsics/abi-v{}.toml", overlay.intrinsic_abi));
+    let ledger_text = fs::read_to_string(&ledger_path)
+        .with_context(|| format!("read {}", ledger_path.display()))?;
+    let ledger: AbiLedgerFile =
+        toml::from_str(&ledger_text).with_context(|| format!("parse {}", ledger_path.display()))?;
+
+    ensure!(
+        imported.schema == IMPORTED_SCHEMA,
+        "unsupported imported.json schema {}",
+        imported.schema
+    );
+    ensure!(
+        overlay.schema == OVERLAY_SCHEMA,
+        "unsupported overlay.toml schema {}",
+        overlay.schema
+    );
+    ensure!(
+        overlay.intrinsic_abi > 0,
+        "intrinsic_abi must be a positive integer"
+    );
+    ensure!(
+        imported.source.llvm_revision == lock.llvm.revision,
+        "imported facts use LLVM {}, but upstream.lock pins {}",
+        imported.source.llvm_revision,
+        lock.llvm.revision
+    );
+    ensure!(
+        imported.source.llvm_tblgen_source_revision == lock.llvm.revision,
+        "imported facts were not produced by llvm-tblgen built from the pinned source"
+    );
+    ensure!(
+        imported.source.llvm_tblgen_version == lock.llvm_tblgen.version_line,
+        "imported facts use llvm-tblgen {:?}, but upstream.lock pins {:?}",
+        imported.source.llvm_tblgen_version,
+        lock.llvm_tblgen.version_line
+    );
+    ensure!(
+        imported.source.intrinsics_json_sha256 == lock.dumps.intrinsics_sha256,
+        "imported intrinsic dump hash does not match upstream.lock"
+    );
+    ensure!(
+        imported.source.nvptx_json_sha256 == lock.dumps.nvptx_sha256,
+        "imported NVPTX dump hash does not match upstream.lock"
+    );
+    let imported_sha256 = sha256_file(&imported_path)?;
+    ensure!(
+        imported_sha256 == lock.dumps.normalized_imported_sha256,
+        "normalized imported.json hash mismatch: upstream.lock records {}, found {}; regenerate from the pinned dumps, and refresh the lock explicitly only for an intentional normalizer change",
+        lock.dumps.normalized_imported_sha256,
+        imported_sha256
+    );
+
+    bind_generated_abi_ids(&mut overlay, &ledger)?;
+    overlay
+        .intrinsics
+        .sort_by(|left, right| left.id.cmp(&right.id));
+    validate_execution_control_family_completeness(&overlay.intrinsics)?;
+    validate_unique_overlay(&overlay.intrinsics, overlay.intrinsic_abi)?;
+    validate_abi_ledger(&overlay, &ledger)?;
+    Ok(ResolutionBase {
+        overlay,
+        imported,
+        source: CatalogSource {
+            llvm_repository: lock.llvm.repository,
+            llvm_revision: lock.llvm.revision,
+            llvm_tblgen_version: lock.llvm_tblgen.version_line,
+            llvm_tblgen_source_revision: lock
+                .llvm_tblgen
+                .built_from_llvm_revision
+                .context("pinned llvm-tblgen has no source revision")?,
+        },
+        imported_sha256,
+        overlay_sha256,
+        abi_ledger_sha256: sha256_file(&ledger_path)?,
+    })
+}
+
+pub(super) fn index_imported_intrinsics(
+    imported: &ImportedFile,
+) -> Result<BTreeMap<&str, &ImportedIntrinsic>> {
+    let imported_by_record: BTreeMap<_, _> = imported
+        .intrinsics
+        .iter()
+        .map(|intrinsic| (intrinsic.source_record.as_str(), intrinsic))
+        .collect();
+    ensure!(
+        imported_by_record.len() == imported.intrinsics.len(),
+        "imported.json contains duplicate source records"
+    );
+    Ok(imported_by_record)
+}
+
+pub(super) fn resolve_imported_declaration<'a>(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+    imported_by_record: &'a BTreeMap<&str, &'a ImportedIntrinsic>,
+) -> Result<Option<&'a ImportedIntrinsic>> {
+    match source {
+        IntrinsicSource::LlvmImported { source_record } => Ok(Some(
+            *imported_by_record
+                .get(source_record.as_str())
+                .with_context(|| {
+                    format!(
+                        "overlay intrinsic {} references missing imported record {}",
+                        policy.id, source_record
+                    )
+                })?,
+        )),
+        IntrinsicSource::PtxNative { .. } => Ok(None),
+    }
+}
+
+pub(crate) fn resolve_candidate(
+    repo_root: &Path,
+    intrinsic_id: &str,
+    backend_version: &str,
+    backend_sha256: &str,
+    gpu_target: &str,
+    ptx_feature: &str,
+) -> Result<CandidateResolution> {
+    let base = load_resolution_base(repo_root)?;
+    let imported_by_record = index_imported_intrinsics(&base.imported)?;
+    let policy = base
+        .overlay
+        .intrinsics
+        .iter()
+        .find(|policy| policy.id == intrinsic_id || policy.abi_id == intrinsic_id)
+        .with_context(|| format!("unknown overlay intrinsic {intrinsic_id}"))?;
+    let source = resolve_policy_source(policy)?;
+    let declaration = resolve_imported_declaration(policy, &source, &imported_by_record)?;
+    validate_special_register_llvm_exclusion(policy, &imported_by_record)?;
+    validate_policy(policy, &source, declaration, base.overlay.intrinsic_abi)?;
+    ensure!(
+        !backend_version.trim().is_empty()
+            && backend_sha256.len() == 64
+            && backend_sha256.bytes().all(|byte| byte.is_ascii_hexdigit()),
+        "candidate backend identity is incomplete"
+    );
+    let (mechanism, target) = candidate_llvm_route(policy)?;
+    validate_candidate_target(policy, &target, gpu_target, ptx_feature)?;
+
+    let record = materialize_record(
+        policy,
+        source,
+        declaration,
+        CatalogBackend {
+            profile: "candidate-comparison".into(),
+            version: backend_version.into(),
+            sha256: backend_sha256.into(),
+            status: "candidate".into(),
+            target_triple: "nvptx64-nvidia-cuda".into(),
+            gpu_target: gpu_target.into(),
+            ptx_feature: ptx_feature.into(),
+        },
+        Vec::new(),
+        base.overlay.intrinsic_abi,
+    )?;
+    Ok(CandidateResolution {
+        catalog: CatalogFile {
+            schema: CATALOG_SCHEMA,
+            catalog_version: base.overlay.catalog_version,
+            intrinsic_abi: base.overlay.intrinsic_abi,
+            generator_version: env!("CARGO_PKG_VERSION").to_owned(),
+            source: base.source,
+            inputs: CatalogInputs {
+                imported_sha256: base.imported_sha256,
+                overlay_sha256: base.overlay_sha256,
+                abi_ledger_sha256: base.abi_ledger_sha256,
+                evidence_sha256: Vec::new(),
+            },
+            intrinsics: vec![record],
+        },
+        mechanism,
+        requirement: target,
+    })
+}
+
+pub(super) fn candidate_llvm_route(
+    policy: &OverlayIntrinsic,
+) -> Result<(BackendLoweringMechanism, CatalogTargetRequirement)> {
+    let routes = policy
+        .backend_lowerings
+        .iter()
+        .filter(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+        .collect::<Vec<_>>();
+    ensure!(
+        routes.len() <= 1,
+        "{} has more than one LLVM-NVPTX route",
+        policy.id
+    );
+    if let Some(route) = routes.first() {
+        return Ok((route.mechanism, backend_target_requirement(policy, route)?));
+    }
+    ensure!(
+        matches!(
+            resolve_policy_source(policy)?,
+            IntrinsicSource::LlvmImported { .. }
+        ),
+        "{} has no LLVM-NVPTX candidate route",
+        policy.id
+    );
+    Ok((
+        BackendLoweringMechanism::TypedNvvm,
+        CatalogTargetRequirement {
+            minimum_ptx: parse_ptx_version(&policy.minimum_ptx, &policy.id)?,
+            hardware: parse_hardware_target(policy)?,
+        },
+    ))
+}
+
+pub(super) fn validate_candidate_target(
+    policy: &OverlayIntrinsic,
+    requirement: &CatalogTargetRequirement,
+    gpu_target: &str,
+    ptx_feature: &str,
+) -> Result<()> {
+    ensure!(
+        gpu_target.starts_with("sm_"),
+        "candidate GPU target {gpu_target:?} must use sm_NN, sm_NNa, or sm_NNf"
+    );
+    let hardware = parse_stage_hardware(gpu_target).with_context(|| {
+        format!("candidate GPU target {gpu_target:?} must use sm_NN, sm_NNa, or sm_NNf")
+    })?;
+    ensure!(
+        describe_stage_hardware(hardware) == gpu_target,
+        "candidate GPU target {gpu_target:?} is not canonical"
+    );
+    let ptx = parse_candidate_ptx_feature(ptx_feature)?;
+    let effective_minimum_ptx = if is_f8f6f4_mma_target_matrix_policy(policy) {
+        f8f6f4_llvm_ptx_floor(hardware)?
+    } else {
+        target_requirement_ptx_floor(requirement, hardware, true).with_context(|| {
+            format!(
+                "candidate GPU target {gpu_target} does not satisfy {} hardware requirement {:?}",
+                policy.id, requirement.hardware
+            )
+        })?
+    };
+    ensure!(
+        ptx.encoded() >= effective_minimum_ptx,
+        "candidate target {gpu_target} / {ptx_feature} is below {} PTX floor {}.{}",
+        policy.id,
+        effective_minimum_ptx / 10,
+        effective_minimum_ptx % 10
+    );
+    let hardware_matches = target_requirement_ptx_floor(requirement, hardware, true).is_some();
+    ensure!(
+        hardware_matches,
+        "candidate GPU target {gpu_target} does not satisfy {} hardware requirement {:?}",
+        policy.id,
+        requirement.hardware
+    );
+    Ok(())
+}
+
+pub(super) fn target_requirement_ptx_floor(
+    requirement: &CatalogTargetRequirement,
+    hardware: CatalogHardwareAlternative,
+    allow_forward_minimum: bool,
+) -> Option<u16> {
+    match &requirement.hardware {
+        CatalogHardwareTarget::All => Some(requirement.minimum_ptx.encoded()),
+        CatalogHardwareTarget::AnyOf { alternatives } => alternatives
+            .iter()
+            .any(|expected| {
+                selected_stage_hardware_matches(hardware, *expected, allow_forward_minimum)
+            })
+            .then(|| requirement.minimum_ptx.encoded()),
+        CatalogHardwareTarget::TargetMatrix { contracts } => contracts
+            .iter()
+            .flat_map(|contract| contract.alternatives.iter())
+            .filter(|alternative| {
+                selected_stage_hardware_matches(
+                    hardware,
+                    alternative.hardware,
+                    allow_forward_minimum,
+                )
+            })
+            .map(|alternative| alternative.minimum_ptx.encoded())
+            .min(),
+    }
+}
+
+pub(super) fn parse_candidate_ptx_feature(value: &str) -> Result<PtxVersion> {
+    let digits = value
+        .strip_prefix("+ptx")
+        .with_context(|| format!("candidate PTX feature {value:?} must use +ptxNN"))?;
+    ensure!(
+        matches!(digits.len(), 2 | 3) && digits.bytes().all(|byte| byte.is_ascii_digit()),
+        "candidate PTX feature {value:?} must use +ptxNN"
+    );
+    let split = digits.len() - 1;
+    let version = format!("{}.{}", &digits[..split], &digits[split..]);
+    version
+        .parse()
+        .map_err(|reason: String| anyhow::anyhow!("candidate PTX feature {value:?}: {reason}"))
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/evidence.rs b/crates/cuda-intrinsics-gen/src/resolve/evidence.rs
new file mode 100644
index 0000000000..30387a6c9a
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/evidence.rs
@@ -0,0 +1,1504 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogHardwareAlternative, CatalogHardwareTarget,
+    CatalogTargetAlternative, EvidenceArtifactKind, EvidenceFile, EvidenceFileV6, EvidenceMatrix,
+    EvidenceMatrixTemplate, EvidenceRecord, EvidenceRecordDefaults, EvidenceStage,
+    EvidenceStageKind, ImportedAddressSpace, IntrinsicBackend, IntrinsicSource, LdmatrixShape,
+    OverlayBackendLowering, OverlayIntrinsic, RuntimeValidation,
+};
+use crate::ptx::OperandPattern;
+use crate::util::sha256_file;
+use anyhow::{Context, Result, bail, ensure};
+use cuda_target_spec::{CudaArch, recorded_ptx_floor};
+use std::collections::{BTreeMap, BTreeSet};
+use std::fs;
+use std::path::{Path, PathBuf};
+
+use super::families::*;
+use super::policy::*;
+use super::targets::*;
+
+pub(super) fn read_evidence_file(path: &Path) -> Result<EvidenceFile> {
+    let bytes = fs::read(path).with_context(|| format!("read {}", path.display()))?;
+    parse_evidence_bytes(&bytes, &path.display().to_string())
+}
+
+pub(super) fn parse_evidence_bytes(bytes: &[u8], source: &str) -> Result<EvidenceFile> {
+    #[derive(serde::Deserialize)]
+    struct Schema {
+        schema: u32,
+    }
+
+    let schema: Schema =
+        serde_json::from_slice(bytes).with_context(|| format!("parse JSON {source}"))?;
+    match schema.schema {
+        2..=5 => serde_json::from_slice(bytes)
+            .with_context(|| format!("parse legacy evidence JSON {source}")),
+        6 => {
+            let file: EvidenceFileV6 = serde_json::from_slice(bytes)
+                .with_context(|| format!("parse matrix evidence JSON {source}"))?;
+            expand_evidence_file_v6(file)
+                .with_context(|| format!("expand matrix evidence {source}"))
+        }
+        _ => bail!("unsupported evidence schema in {source}"),
+    }
+}
+
+pub(super) fn expand_evidence_file_v6(file: EvidenceFileV6) -> Result<EvidenceFile> {
+    ensure!(file.schema == 6, "matrix evidence must use schema 6");
+    ensure!(
+        !file.records.is_empty() || !file.matrices.is_empty(),
+        "schema-6 evidence contains no records or matrices"
+    );
+    reject_default_placeholders(&file.defaults, "evidence defaults", false)?;
+
+    let mut fixture_by_id = BTreeMap::new();
+    let mut fixture_coverage = BTreeMap::new();
+    for fixture in &file.fixtures {
+        ensure!(
+            is_safe_matrix_token(&fixture.id),
+            "evidence fixture ID {:?} is not a safe token",
+            fixture.id
+        );
+        ensure!(
+            fixture.coverage_count > 0 && !fixture.stages.is_empty(),
+            "evidence fixture {} has no coverage or stages",
+            fixture.id
+        );
+        reject_stage_placeholders(&fixture.stages, &format!("fixture {}", fixture.id))?;
+        ensure!(
+            fixture_by_id.insert(fixture.id.as_str(), fixture).is_none(),
+            "duplicate evidence fixture ID {}",
+            fixture.id
+        );
+        fixture_coverage.insert(fixture.id.as_str(), 0usize);
+    }
+
+    let mut records = file.records;
+    let mut record_ids = BTreeSet::new();
+    for record in &records {
+        ensure!(
+            record_ids.insert(record.id.clone()),
+            "duplicate expanded evidence ID {}",
+            record.id
+        );
+        validate_stage_pairs(&record.stages, &record.id)?;
+    }
+
+    for matrix in &file.matrices {
+        let (expanded, referenced_fixtures) =
+            expand_evidence_matrix(matrix, &file.defaults, &fixture_by_id)?;
+        for fixture_id in referenced_fixtures {
+            *fixture_coverage
+                .get_mut(fixture_id.as_str())
+                .expect("validated fixture reference") += expanded.len();
+        }
+        for record in expanded {
+            ensure!(
+                record_ids.insert(record.id.clone()),
+                "duplicate expanded evidence ID {}",
+                record.id
+            );
+            records.push(record);
+        }
+    }
+
+    for fixture in &file.fixtures {
+        let actual = fixture_coverage[fixture.id.as_str()];
+        ensure!(
+            actual > 0,
+            "evidence fixture {} is not referenced by any matrix",
+            fixture.id
+        );
+        ensure!(
+            actual == fixture.coverage_count,
+            "evidence fixture {} covers {actual} expanded records, expected {}",
+            fixture.id,
+            fixture.coverage_count
+        );
+    }
+
+    Ok(EvidenceFile {
+        schema: file.schema,
+        backend_profile: file.backend_profile,
+        backend_kind: file.backend_kind,
+        llvm_revision: file.llvm_revision,
+        backend_version: file.backend_version,
+        backend_sha256: file.backend_sha256,
+        artifact_path: file.artifact_path,
+        build_id_prefix: file.build_id_prefix,
+        nvvm_ir_version: file.nvvm_ir_version,
+        debug_ir_version: file.debug_ir_version,
+        records,
+    })
+}
+
+pub(super) fn expand_evidence_matrix(
+    matrix: &EvidenceMatrix,
+    defaults: &EvidenceRecordDefaults,
+    fixtures: &BTreeMap<&str, &crate::model::EvidenceFixture>,
+) -> Result<(Vec<EvidenceRecord>, Vec<String>)> {
+    ensure!(!matrix.axes.is_empty(), "evidence matrix has no axes");
+    let mut previous_axis: Option<&str> = None;
+    let mut product_count = 1usize;
+    let mut bindings = vec![BTreeMap::<String, String>::new()];
+    for axis in &matrix.axes {
+        ensure!(
+            is_safe_matrix_token(&axis.name),
+            "evidence matrix axis {:?} is not a safe token",
+            axis.name
+        );
+        if let Some(previous) = previous_axis {
+            ensure!(
+                previous < axis.name.as_str(),
+                "evidence matrix axes must be unique and sorted: {} follows {}",
+                axis.name,
+                previous
+            );
+        }
+        previous_axis = Some(&axis.name);
+        ensure!(
+            !axis.values.is_empty(),
+            "evidence matrix axis {} has no values",
+            axis.name
+        );
+        let mut values = BTreeSet::new();
+        for value in &axis.values {
+            ensure!(
+                is_safe_matrix_token(value),
+                "evidence matrix axis {} has unsafe value {:?}",
+                axis.name,
+                value
+            );
+            ensure!(
+                values.insert(value.as_str()),
+                "evidence matrix axis {} has duplicate value {:?}",
+                axis.name,
+                value
+            );
+        }
+        product_count = product_count
+            .checked_mul(axis.values.len())
+            .context("evidence matrix product count overflow")?;
+        let mut next = Vec::with_capacity(product_count);
+        for binding in bindings {
+            for value in &axis.values {
+                let mut expanded = binding.clone();
+                expanded.insert(axis.name.clone(), value.clone());
+                next.push(expanded);
+            }
+        }
+        bindings = next;
+    }
+    ensure!(
+        product_count == matrix.product_count,
+        "evidence matrix expands to {product_count} records, expected {}",
+        matrix.product_count
+    );
+    ensure!(
+        !matrix.fixtures.is_empty(),
+        "evidence matrix references no shared fixture"
+    );
+
+    let mut fixture_ids = BTreeSet::new();
+    let mut previous_fixture: Option<&str> = None;
+    let mut fixture_stages = Vec::new();
+    for fixture_id in &matrix.fixtures {
+        if let Some(previous) = previous_fixture {
+            ensure!(
+                previous < fixture_id.as_str(),
+                "evidence matrix fixtures must be unique and sorted: {fixture_id} follows {previous}"
+            );
+        }
+        previous_fixture = Some(fixture_id);
+        let fixture = fixtures
+            .get(fixture_id.as_str())
+            .with_context(|| format!("evidence matrix references unknown fixture {fixture_id}"))?;
+        fixture_ids.insert(fixture_id.clone());
+        fixture_stages.extend(fixture.stages.iter().cloned());
+    }
+
+    reject_default_placeholders(&matrix.template.facts, "matrix template facts", true)?;
+    validate_matrix_identity(&matrix.template)?;
+    let axis_names = matrix
+        .axes
+        .iter()
+        .map(|axis| axis.name.as_str())
+        .collect::<BTreeSet<_>>();
+    let mut used_axes = BTreeSet::new();
+    let mut records = Vec::with_capacity(product_count);
+    for binding in &bindings {
+        let record = materialize_evidence_record(
+            &matrix.template,
+            defaults,
+            binding,
+            &mut used_axes,
+            &fixture_stages,
+        )?;
+        validate_stage_pairs(&record.stages, &record.id)?;
+        records.push(record);
+    }
+    for axis in axis_names {
+        ensure!(
+            used_axes.contains(axis),
+            "evidence matrix declares unused axis {axis}"
+        );
+    }
+    Ok((records, fixture_ids.into_iter().collect()))
+}
+
+pub(super) fn validate_matrix_identity(template: &EvidenceMatrixTemplate) -> Result<()> {
+    ensure!(
+        !template.id.is_empty(),
+        "evidence matrix template has an empty ID"
+    );
+    match (&template.source, &template.source_record) {
+        (Some(_), None) | (None, Some(_)) => {}
+        (Some(_), Some(_)) => bail!("evidence matrix template mixes source forms"),
+        (None, None) => bail!("evidence matrix template has no source"),
+    }
+    reject_disallowed_placeholder(&template.expected_ptx.mnemonic, "PTX mnemonic")?;
+    Ok(())
+}
+
+pub(super) fn materialize_evidence_record(
+    template: &EvidenceMatrixTemplate,
+    defaults: &EvidenceRecordDefaults,
+    bindings: &BTreeMap<String, String>,
+    used_axes: &mut BTreeSet<String>,
+    fixture_stages: &[EvidenceStage],
+) -> Result<EvidenceRecord> {
+    let id = expand_axis_placeholders(&template.id, bindings, used_axes, "evidence ID")?;
+    let source = template
+        .source
+        .as_ref()
+        .map(|source| expand_evidence_source(source, bindings, used_axes))
+        .transpose()?;
+    let source_record = template
+        .source_record
+        .as_deref()
+        .map(|value| expand_axis_placeholders(value, bindings, used_axes, "source record"))
+        .transpose()?;
+    let llvm_symbol = template
+        .llvm_symbol
+        .as_deref()
+        .map(|value| expand_axis_placeholders(value, bindings, used_axes, "LLVM symbol"))
+        .transpose()?;
+    validate_expanded_matrix_identity(
+        &id,
+        source.as_ref(),
+        source_record.as_deref(),
+        llvm_symbol.as_deref(),
+    )?;
+    let resolved_llvm_symbol = select_fact(
+        &template.facts.resolved_llvm_symbol,
+        &defaults.resolved_llvm_symbol,
+    )
+    .map(|value| expand_axis_placeholders(&value, bindings, used_axes, "resolved LLVM symbol"))
+    .transpose()?;
+    let mut expected_ptx = template.expected_ptx.clone();
+    for modifier in &mut expected_ptx.modifiers {
+        *modifier = expand_axis_placeholders(modifier, bindings, used_axes, "PTX modifier")?;
+    }
+    for operand in &mut expected_ptx.operands {
+        if let OperandPattern::Exact { value } = operand {
+            *value = expand_axis_placeholders(value, bindings, used_axes, "exact PTX operand")?;
+        }
+    }
+
+    let mut stages = defaults.stages.clone();
+    stages.extend(template.facts.stages.iter().cloned());
+    stages.extend(fixture_stages.iter().cloned());
+    let target_triple = required_fact(
+        select_fact(&template.facts.target_triple, &defaults.target_triple),
+        &id,
+        "target triple",
+    )?;
+    let gpu_target = required_fact(
+        select_fact(&template.facts.gpu_target, &defaults.gpu_target),
+        &id,
+        "GPU target",
+    )?;
+    let ptx_feature = required_fact(
+        select_fact(&template.facts.ptx_feature, &defaults.ptx_feature),
+        &id,
+        "PTX feature",
+    )?;
+    let status = required_fact(
+        select_fact(&template.facts.status, &defaults.status),
+        &id,
+        "status",
+    )?;
+    let source_is_ptx_native = matches!(source, Some(IntrinsicSource::PtxNative { .. }));
+    Ok(EvidenceRecord {
+        id,
+        source,
+        source_record,
+        llvm_symbol,
+        resolved_llvm_symbol,
+        llvm_arguments: select_fact(&template.facts.llvm_arguments, &defaults.llvm_arguments)
+            .unwrap_or_default(),
+        llvm_results: select_fact(&template.facts.llvm_results, &defaults.llvm_results)
+            .unwrap_or_default(),
+        concrete_llvm_arguments: select_fact(
+            &template.facts.concrete_llvm_arguments,
+            &defaults.concrete_llvm_arguments,
+        )
+        .unwrap_or_default(),
+        concrete_llvm_results: select_fact(
+            &template.facts.concrete_llvm_results,
+            &defaults.concrete_llvm_results,
+        )
+        .unwrap_or_default(),
+        target_triple,
+        gpu_target,
+        ptx_feature,
+        status,
+        stages,
+        // Declaration canonicalization is a statement about an imported
+        // LLVM declaration; a PTX-native record has none, so the file-level
+        // default must not invent the fact for it.
+        declaration_attributes_canonicalized: if source_is_ptx_native {
+            template.facts.declaration_attributes_canonicalized
+        } else {
+            template
+                .facts
+                .declaration_attributes_canonicalized
+                .or(defaults.declaration_attributes_canonicalized)
+        },
+        runtime_validation: template
+            .facts
+            .runtime_validation
+            .or(defaults.runtime_validation),
+        expected_ptx,
+    })
+}
+
+pub(super) fn validate_expanded_matrix_identity(
+    id: &str,
+    source: Option<&IntrinsicSource>,
+    source_record: Option<&str>,
+    llvm_symbol: Option<&str>,
+) -> Result<()> {
+    ensure!(!id.is_empty(), "expanded evidence has an empty ID");
+    let imported_source = match (source, source_record) {
+        (Some(IntrinsicSource::LlvmImported { source_record }), None) => {
+            ensure!(
+                !source_record.is_empty(),
+                "expanded evidence {id} has an empty source record"
+            );
+            true
+        }
+        (Some(IntrinsicSource::PtxNative { instruction }), None) => {
+            ensure!(
+                !instruction.is_empty(),
+                "expanded evidence {id} has an empty PTX source"
+            );
+            false
+        }
+        (None, Some(source_record)) => {
+            ensure!(
+                !source_record.is_empty(),
+                "expanded evidence {id} has an empty source record"
+            );
+            true
+        }
+        _ => unreachable!("matrix source shape was validated before expansion"),
+    };
+    if imported_source {
+        ensure!(
+            llvm_symbol.is_some_and(|symbol| !symbol.is_empty()),
+            "expanded imported evidence {id} has no LLVM symbol"
+        );
+    } else {
+        ensure!(
+            llvm_symbol.is_none(),
+            "expanded PTX-native evidence {id} invents an LLVM symbol"
+        );
+    }
+    Ok(())
+}
+
+pub(super) fn select_fact<T: Clone>(specific: &Option<T>, default: &Option<T>) -> Option<T> {
+    specific.clone().or_else(|| default.clone())
+}
+
+pub(super) fn required_fact(value: Option<String>, id: &str, field: &str) -> Result<String> {
+    let value = value.with_context(|| format!("expanded evidence {id} has no {field}"))?;
+    ensure!(
+        !value.trim().is_empty(),
+        "expanded evidence {id} has an empty {field}"
+    );
+    Ok(value)
+}
+
+pub(super) fn expand_evidence_source(
+    source: &IntrinsicSource,
+    bindings: &BTreeMap<String, String>,
+    used_axes: &mut BTreeSet<String>,
+) -> Result<IntrinsicSource> {
+    Ok(match source {
+        IntrinsicSource::LlvmImported { source_record } => IntrinsicSource::LlvmImported {
+            source_record: expand_axis_placeholders(
+                source_record,
+                bindings,
+                used_axes,
+                "tagged source record",
+            )?,
+        },
+        IntrinsicSource::PtxNative { instruction } => IntrinsicSource::PtxNative {
+            instruction: expand_axis_placeholders(
+                instruction,
+                bindings,
+                used_axes,
+                "PTX-native source",
+            )?,
+        },
+    })
+}
+
+pub(super) fn expand_axis_placeholders(
+    value: &str,
+    bindings: &BTreeMap<String, String>,
+    used_axes: &mut BTreeSet<String>,
+    field: &str,
+) -> Result<String> {
+    let mut output = String::with_capacity(value.len());
+    let mut rest = value;
+    while let Some(position) = rest.find('$') {
+        output.push_str(&rest[..position]);
+        let placeholder = &rest[position..];
+        ensure!(
+            placeholder.starts_with("${"),
+            "{field} contains malformed matrix placeholder {value:?}"
+        );
+        let close = placeholder
+            .find('}')
+            .with_context(|| format!("{field} contains an unterminated matrix placeholder"))?;
+        let axis = &placeholder[2..close];
+        ensure!(
+            is_safe_matrix_token(axis),
+            "{field} contains malformed matrix axis {axis:?}"
+        );
+        let replacement = bindings
+            .get(axis)
+            .with_context(|| format!("{field} references unknown matrix axis {axis}"))?;
+        output.push_str(replacement);
+        used_axes.insert(axis.to_owned());
+        rest = &placeholder[close + 1..];
+    }
+    output.push_str(rest);
+    Ok(output)
+}
+
+pub(super) fn is_safe_matrix_token(value: &str) -> bool {
+    let mut bytes = value.bytes();
+    bytes.next().is_some_and(|byte| byte.is_ascii_lowercase())
+        && bytes.all(|byte| byte.is_ascii_lowercase() || byte.is_ascii_digit() || byte == b'_')
+}
+
+pub(super) fn reject_default_placeholders(
+    defaults: &EvidenceRecordDefaults,
+    context: &str,
+    allow_resolved_symbol: bool,
+) -> Result<()> {
+    if !allow_resolved_symbol && let Some(value) = &defaults.resolved_llvm_symbol {
+        reject_disallowed_placeholder(value, context)?;
+    }
+    for value in defaults
+        .target_triple
+        .iter()
+        .chain(defaults.gpu_target.iter())
+        .chain(defaults.ptx_feature.iter())
+        .chain(defaults.status.iter())
+        .chain(defaults.llvm_arguments.iter().flatten())
+        .chain(defaults.llvm_results.iter().flatten())
+        .chain(defaults.concrete_llvm_arguments.iter().flatten())
+        .chain(defaults.concrete_llvm_results.iter().flatten())
+    {
+        reject_disallowed_placeholder(value, context)?;
+    }
+    reject_stage_placeholders(&defaults.stages, context)
+}
+
+pub(super) fn reject_stage_placeholders(stages: &[EvidenceStage], context: &str) -> Result<()> {
+    for stage in stages {
+        for value in stage
+            .targets
+            .iter()
+            .chain(std::iter::once(&stage.representation))
+            .chain(std::iter::once(&stage.detail))
+            .chain(stage.tool_path.iter())
+            .chain(stage.tool_version.iter())
+            .chain(stage.tool_sha256.iter())
+        {
+            reject_disallowed_placeholder(value, context)?;
+        }
+    }
+    Ok(())
+}
+
+pub(super) fn reject_disallowed_placeholder(value: &str, field: &str) -> Result<()> {
+    ensure!(
+        !value.contains("${"),
+        "{field} cannot contain matrix placeholders"
+    );
+    Ok(())
+}
+
+pub(super) fn validate_stage_pairs(stages: &[EvidenceStage], id: &str) -> Result<()> {
+    let mut identities = Vec::new();
+    for stage in stages {
+        let identity = (stage.stage, stage.mechanism, stage.targets.clone());
+        ensure!(
+            !identities.contains(&identity),
+            "expanded evidence {id} has conflicting duplicate {:?}/{:?} stage targets {:?}",
+            stage.stage,
+            stage.mechanism,
+            stage.targets
+        );
+        identities.push(identity);
+    }
+    Ok(())
+}
+
+pub(super) fn read_evidence(repo_root: &Path) -> Result<(Vec<EvidenceFile>, Vec<String>)> {
+    let directory = repo_root.join("intrinsics/evidence");
+    let mut paths: Vec<PathBuf> = fs::read_dir(&directory)
+        .with_context(|| format!("read {}", directory.display()))?
+        .filter_map(|entry| entry.ok().map(|entry| entry.path()))
+        .filter(|path| path.extension().and_then(|ext| ext.to_str()) == Some("json"))
+        .collect();
+    paths.sort();
+    ensure!(
+        !paths.is_empty(),
+        "no evidence JSON files in {}",
+        directory.display()
+    );
+    let mut files = Vec::with_capacity(paths.len());
+    let mut hashes = Vec::with_capacity(paths.len());
+    for path in paths {
+        let file = read_evidence_file(&path)?;
+        let name = path.file_name().unwrap().to_string_lossy();
+        hashes.push(format!("{name}:{}", sha256_file(&path)?));
+        files.push(file);
+    }
+    Ok((files, hashes))
+}
+
+#[derive(Debug, Clone, Copy)]
+pub(super) struct IndexedEvidence<'a> {
+    pub(super) file: &'a EvidenceFile,
+    pub(super) record: &'a EvidenceRecord,
+    pub(super) backend_version: &'a str,
+    pub(super) backend_sha256: &'a str,
+}
+
+pub(super) fn index_evidence<'a>(
+    files: &'a [EvidenceFile],
+    llvm_revision: &str,
+) -> Result<BTreeMap<(&'a str, &'a str), IndexedEvidence<'a>>> {
+    let mut result = BTreeMap::new();
+    for file in files {
+        ensure!(
+            !file.backend_profile.trim().is_empty() && !file.llvm_revision.trim().is_empty(),
+            "evidence file has no concrete backend profile or LLVM revision"
+        );
+        ensure!(
+            !file.backend_version.trim().is_empty() && !file.backend_sha256.trim().is_empty(),
+            "evidence does not identify the backend binary"
+        );
+        if file.backend_kind != Some(IntrinsicBackend::LibNvvm) {
+            ensure!(
+                file.llvm_revision == llvm_revision,
+                "selected evidence LLVM revision {} does not match pinned {}",
+                file.llvm_revision,
+                llvm_revision
+            );
+        }
+        for record in &file.records {
+            ensure!(
+                result
+                    .insert(
+                        (file.backend_profile.as_str(), record.id.as_str()),
+                        IndexedEvidence {
+                            file,
+                            record,
+                            backend_version: &file.backend_version,
+                            backend_sha256: &file.backend_sha256,
+                        },
+                    )
+                    .is_none(),
+                "duplicate evidence for catalog ID {}",
+                record.id
+            );
+        }
+    }
+    Ok(result)
+}
+
+pub(super) fn validate_evidence(
+    policy: &OverlayIntrinsic,
+    evidence: &IndexedEvidence<'_>,
+    lowering: Option<&crate::model::OverlayBackendLowering>,
+) -> Result<()> {
+    let record = evidence.record;
+    record.expected_ptx.validate().map_err(|reason| {
+        anyhow::anyhow!(
+            "{} evidence has an invalid expected PTX pattern: {reason}",
+            policy.id
+        )
+    })?;
+    let policy_source = resolve_policy_source(policy)?;
+    let evidence_source = match (&record.source, &record.source_record) {
+        (None, Some(source_record)) => IntrinsicSource::LlvmImported {
+            source_record: source_record.clone(),
+        },
+        (Some(source), None) => source.clone(),
+        (Some(_), Some(_)) => bail!(
+            "{} evidence mixes tagged source with legacy source_record",
+            policy.id
+        ),
+        (None, None) => bail!("{} evidence has no source provenance", policy.id),
+    };
+    ensure!(
+        evidence_source == policy_source,
+        "{} evidence source provenance mismatch",
+        policy.id
+    );
+    ensure!(
+        record.llvm_symbol == policy.llvm_symbol
+            && record.llvm_arguments == policy.llvm_arguments
+            && record.llvm_results == policy.llvm_results,
+        "{} evidence signature mismatch",
+        policy.id
+    );
+    if matches!(policy_source, IntrinsicSource::PtxNative { .. }) {
+        ensure!(
+            record.llvm_symbol.is_none()
+                && record.resolved_llvm_symbol.is_none()
+                && record.llvm_arguments.is_empty()
+                && record.llvm_results.is_empty()
+                && record.concrete_llvm_arguments.is_empty()
+                && record.concrete_llvm_results.is_empty()
+                && record.declaration_attributes_canonicalized.is_none(),
+            "{} PTX-native evidence must not invent LLVM declaration facts",
+            policy.id
+        );
+    }
+    ensure!(
+        record.expected_ptx == policy.expected_ptx,
+        "{} evidence PTX expectation mismatch",
+        policy.id
+    );
+    ensure!(
+        matches!(record.status.as_str(), "lowered" | "validated" | "executed"),
+        "{} evidence status {} is too weak to generate a lowering",
+        policy.id,
+        record.status
+    );
+    ensure!(
+        !record.target_triple.is_empty()
+            && !record.gpu_target.is_empty()
+            && !record.ptx_feature.is_empty(),
+        "{} evidence omits its full target profile",
+        policy.id
+    );
+    if let Some(lowering) = lowering {
+        ensure!(
+            evidence.file.backend_kind == Some(lowering.backend),
+            "{} evidence profile {} has the wrong backend kind",
+            policy.id,
+            evidence.file.backend_profile
+        );
+        match record.status.as_str() {
+            "executed" => ensure!(
+                record.runtime_validation == Some(RuntimeValidation::Executed),
+                "{} executed evidence must record runtime_validation = executed",
+                policy.id
+            ),
+            _ => ensure!(
+                record.runtime_validation == Some(RuntimeValidation::Unexecuted),
+                "{} non-executed backend evidence must record runtime_validation = unexecuted",
+                policy.id
+            ),
+        }
+        ensure!(
+            !record.stages.is_empty(),
+            "{} backend evidence omits compilation stages",
+            policy.id
+        );
+        ensure!(
+            record.stages.iter().any(|stage| {
+                stage.stage == EvidenceStageKind::BackendCodegen
+                    && stage.mechanism == Some(lowering.mechanism)
+                    && stage.outcome == "succeeded"
+            }),
+            "{} evidence has no successful backend-codegen stage for {:?}",
+            policy.id,
+            lowering.mechanism
+        );
+        validate_selected_stage_targets(policy, record, lowering)?;
+        if lowering.mechanism == BackendLoweringMechanism::TypedNvvm {
+            validate_typed_llvm_evidence(policy, record)?;
+        }
+        validate_packed_conversion_backend_evidence(policy, record, lowering)?;
+        validate_scalar_conversion_backend_evidence(policy, record, lowering)?;
+        validate_scalar_arithmetic_backend_evidence(policy, record, lowering)?;
+        validate_inline_ptx_fallback_evidence(policy, record, lowering)?;
+        if lowering.backend == IntrinsicBackend::LlvmNvptx
+            && matches!(record.status.as_str(), "validated" | "executed")
+        {
+            ensure!(
+                has_valid_ptx_assembly_stage(record, lowering.mechanism),
+                "{} validated LLVM-NVPTX evidence requires a successful PTX-assembly stage with exact tool identity",
+                policy.id
+            );
+        } else if lowering.backend == IntrinsicBackend::LibNvvm
+            && matches!(record.status.as_str(), "validated" | "executed")
+        {
+            ensure!(
+                has_valid_cubin_device_link_stage(record, lowering.mechanism),
+                "{} validated libNVVM evidence requires a successful cubin-producing device-link stage with exact tool identity",
+                policy.id
+            );
+        }
+        if record.status == "executed" {
+            ensure!(
+                record.stages.iter().any(|stage| {
+                    stage.stage == EvidenceStageKind::Runtime
+                        && stage.mechanism == Some(lowering.mechanism)
+                        && stage.outcome == "succeeded"
+                }),
+                "{} executed evidence requires a successful runtime stage for the selected mechanism",
+                policy.id
+            );
+        }
+    }
+    Ok(())
+}
+
+pub(super) fn validate_inline_ptx_fallback_evidence(
+    policy: &OverlayIntrinsic,
+    record: &EvidenceRecord,
+    lowering: &crate::model::OverlayBackendLowering,
+) -> Result<()> {
+    if !matches!(
+        policy.family.as_str(),
+        "cluster_barrier" | "wgmma_control" | "elect"
+    ) || lowering.backend != IntrinsicBackend::LibNvvm
+    {
+        return Ok(());
+    }
+    for stage in [
+        EvidenceStageKind::BackendCodegen,
+        EvidenceStageKind::DeviceLink,
+    ] {
+        ensure!(
+            record.stages.iter().any(|candidate| {
+                candidate.stage == stage
+                    && candidate.mechanism == Some(BackendLoweringMechanism::TypedNvvm)
+                    && candidate.outcome == "failed"
+            }),
+            "{} libNVVM inline-PTX evidence must record the failed typed-NVVM {:?} comparison",
+            policy.id,
+            stage
+        );
+    }
+    ensure!(
+        !record.stages.iter().any(|candidate| {
+            candidate.stage == EvidenceStageKind::DeviceLink
+                && candidate.mechanism == Some(BackendLoweringMechanism::TypedNvvm)
+                && candidate.outcome == "succeeded"
+        }),
+        "{} libNVVM evidence cannot select inline PTX after a successful typed-NVVM terminal",
+        policy.id
+    );
+    Ok(())
+}
+
+pub(super) fn validate_packed_conversion_backend_evidence(
+    policy: &OverlayIntrinsic,
+    record: &EvidenceRecord,
+    lowering: &crate::model::OverlayBackendLowering,
+) -> Result<()> {
+    if policy.family != "packed_conversion" {
+        return Ok(());
+    }
+    match lowering.backend {
+        IntrinsicBackend::LlvmNvptx => {
+            validate_typed_llvm_evidence(policy, record)?;
+            for stage in [
+                EvidenceStageKind::DeclarationCanonicalization,
+                EvidenceStageKind::BackendCodegen,
+            ] {
+                ensure!(
+                    successful_stage(record, BackendLoweringMechanism::TypedNvvm, stage).is_some(),
+                    "{} LLVM packed-conversion evidence requires a successful auxiliary typed-NVVM {:?} stage",
+                    policy.id,
+                    stage
+                );
+            }
+            ensure!(
+                has_valid_ptx_assembly_stage(record, BackendLoweringMechanism::TypedNvvm),
+                "{} LLVM packed-conversion evidence requires a successful auxiliary typed-NVVM PTX-assembly stage with exact tool identity",
+                policy.id
+            );
+            ensure!(
+                matches!(record.status.as_str(), "validated" | "executed"),
+                "{} LLVM packed-conversion evidence requires validated evidence status for its auxiliary typed-NVVM terminal stage",
+                policy.id
+            );
+            let typed_lowering = crate::model::OverlayBackendLowering {
+                mechanism: BackendLoweringMechanism::TypedNvvm,
+                ..lowering.clone()
+            };
+            validate_selected_stage_targets(policy, record, &typed_lowering)?;
+            Ok(())
+        }
+        IntrinsicBackend::LibNvvm => {
+            ensure!(
+                record.resolved_llvm_symbol.is_none()
+                    && record.concrete_llvm_arguments.is_empty()
+                    && record.concrete_llvm_results.is_empty()
+                    && record.declaration_attributes_canonicalized.is_none()
+                    && !record.stages.iter().any(|stage| {
+                        stage.mechanism == Some(BackendLoweringMechanism::TypedNvvm)
+                    }),
+                "{} libNVVM inline-PTX evidence must not claim typed LLVM support",
+                policy.id
+            );
+            Ok(())
+        }
+    }
+}
+
+pub(super) fn validate_scalar_conversion_backend_evidence(
+    policy: &OverlayIntrinsic,
+    record: &EvidenceRecord,
+    lowering: &crate::model::OverlayBackendLowering,
+) -> Result<()> {
+    if policy.family != "scalar_conversion" {
+        return Ok(());
+    }
+    match lowering.backend {
+        IntrinsicBackend::LlvmNvptx => ensure!(
+            successful_stage(
+                record,
+                BackendLoweringMechanism::TypedNvvm,
+                EvidenceStageKind::DeclarationCanonicalization,
+            )
+            .is_some(),
+            "{} LLVM scalar-conversion evidence must canonicalize the typed declaration",
+            policy.id
+        ),
+        IntrinsicBackend::LibNvvm => ensure!(
+            record.resolved_llvm_symbol.is_none()
+                && record.concrete_llvm_arguments.is_empty()
+                && record.concrete_llvm_results.is_empty()
+                && record.declaration_attributes_canonicalized.is_none(),
+            "{} libNVVM scalar-conversion evidence must describe the selected inline-PTX route",
+            policy.id
+        ),
+    };
+    Ok(())
+}
+
+pub(super) fn validate_scalar_arithmetic_backend_evidence(
+    policy: &OverlayIntrinsic,
+    record: &EvidenceRecord,
+    lowering: &crate::model::OverlayBackendLowering,
+) -> Result<()> {
+    if policy.family != "scalar_arithmetic" {
+        return Ok(());
+    }
+    match (lowering.backend, lowering.mechanism) {
+        (IntrinsicBackend::LlvmNvptx, BackendLoweringMechanism::TypedNvvm) => ensure!(
+            successful_stage(
+                record,
+                BackendLoweringMechanism::TypedNvvm,
+                EvidenceStageKind::DeclarationCanonicalization,
+            )
+            .is_some(),
+            "{} typed LLVM scalar-arithmetic evidence must canonicalize the declaration",
+            policy.id
+        ),
+        (IntrinsicBackend::LlvmNvptx, BackendLoweringMechanism::InlinePtx) => {
+            validate_typed_llvm_evidence(policy, record)?;
+            ensure!(
+                successful_stage(
+                    record,
+                    BackendLoweringMechanism::TypedNvvm,
+                    EvidenceStageKind::DeclarationCanonicalization,
+                )
+                .is_some(),
+                "{} inline LLVM scalar-arithmetic evidence must canonicalize its imported declaration",
+                policy.id
+            );
+        }
+        (IntrinsicBackend::LibNvvm, _) => ensure!(
+            record.resolved_llvm_symbol.is_none()
+                && record.concrete_llvm_arguments.is_empty()
+                && record.concrete_llvm_results.is_empty()
+                && record.declaration_attributes_canonicalized.is_none(),
+            "{} libNVVM scalar-arithmetic evidence must describe the selected inline-PTX route",
+            policy.id
+        ),
+    };
+    Ok(())
+}
+
+pub(super) fn validate_typed_llvm_evidence(
+    policy: &OverlayIntrinsic,
+    record: &EvidenceRecord,
+) -> Result<()> {
+    let concrete_arguments = policy
+        .llvm_arguments
+        .iter()
+        .map(|argument| {
+            match argument.as_str() {
+                "shared_cluster_ptr" => return Ok("ptr addrspace(7)".into()),
+                "shared_ptr" => return Ok("ptr addrspace(3)".into()),
+                "global_ptr" => return Ok("ptr addrspace(1)".into()),
+                "ptr" => return Ok("ptr".into()),
+                "anyptr" => {}
+                _ => return Ok(argument.clone()),
+            }
+            match policy.selected_address_space.with_context(|| {
+                format!(
+                    "{} has a polymorphic LLVM pointer without a selected address space",
+                    policy.id
+                )
+            })? {
+                ImportedAddressSpace::Generic => Ok("ptr".into()),
+                ImportedAddressSpace::Shared => Ok("ptr addrspace(3)".into()),
+            }
+        })
+        .collect::<Result<Vec<_>>>()?;
+    ensure!(
+        record.resolved_llvm_symbol == policy.resolved_llvm_symbol
+            && record.concrete_llvm_arguments == concrete_arguments
+            && record.concrete_llvm_results == policy.llvm_results
+            && record.declaration_attributes_canonicalized == Some(true),
+        "{} typed LLVM evidence does not prove its resolved signature and canonical declaration attributes",
+        policy.id
+    );
+    Ok(())
+}
+
+pub(super) fn validate_selected_stage_targets(
+    policy: &OverlayIntrinsic,
+    record: &EvidenceRecord,
+    lowering: &crate::model::OverlayBackendLowering,
+) -> Result<()> {
+    let requirement = backend_target_requirement(policy, lowering)?;
+    let blackwell_ldmatrix = policy.family == "ldmatrix"
+        && policy
+            .ldmatrix_variant
+            .as_ref()
+            .is_some_and(|variant| variant.shape != LdmatrixShape::M8n8);
+    let f8f6f4_mma = is_f8f6f4_mma_target_matrix_policy(policy);
+    let paired_alternatives = match &requirement.hardware {
+        CatalogHardwareTarget::TargetMatrix { contracts } => Some(
+            contracts
+                .iter()
+                .flat_map(|contract| contract.alternatives.iter().cloned())
+                .collect::<Vec<_>>(),
+        ),
+        _ => None,
+    };
+    let target_matrix_evidence = blackwell_ldmatrix || f8f6f4_mma || paired_alternatives.is_some();
+    if !target_matrix_evidence {
+        let mut pairs = Vec::new();
+        for stage in record.stages.iter().filter(|stage| {
+            stage.mechanism == Some(lowering.mechanism) && stage.outcome == "succeeded"
+        }) {
+            let pair = (stage.stage, stage.mechanism);
+            ensure!(
+                !pairs.contains(&pair),
+                "{} has multiple target-specific {:?}/{:?} stages outside reviewed target-matrix evidence",
+                policy.id,
+                stage.stage,
+                stage.mechanism
+            );
+            pairs.push(pair);
+        }
+    }
+    for stage in &record.stages {
+        ensure!(
+            !stage.targets.is_empty(),
+            "{} evidence stage {:?} has no targets",
+            policy.id,
+            stage.stage
+        );
+        for target in &stage.targets {
+            ensure!(
+                is_normalized_stage_target(target),
+                "{} evidence stage has unsupported target spelling {target:?}",
+                policy.id
+            );
+        }
+    }
+
+    let terminal_kind = match lowering.backend {
+        IntrinsicBackend::LlvmNvptx => EvidenceStageKind::PtxAssembly,
+        IntrinsicBackend::LibNvvm => EvidenceStageKind::DeviceLink,
+    };
+    let expected_ptx = requirement.minimum_ptx.encoded();
+    let expected_hardware = match &requirement.hardware {
+        CatalogHardwareTarget::AnyOf { alternatives } if !alternatives.is_empty() => {
+            alternatives.clone()
+        }
+        CatalogHardwareTarget::TargetMatrix { contracts } if !contracts.is_empty() => {
+            let mut alternatives = contracts
+                .iter()
+                .flat_map(|contract| contract.alternatives.iter())
+                .map(|alternative| alternative.hardware)
+                .collect::<Vec<_>>();
+            alternatives.sort_by_key(|hardware| target_hardware_sort_key(*hardware));
+            alternatives.dedup();
+            alternatives
+        }
+        _ => bail!(
+            "{} selected backend stages require a hardware target",
+            policy.id
+        ),
+    };
+    if target_matrix_evidence {
+        return validate_target_matrix_stage_targets(
+            policy,
+            record,
+            lowering,
+            terminal_kind,
+            &expected_hardware,
+            expected_ptx,
+            paired_alternatives.as_deref(),
+        );
+    }
+    let backend = successful_stage(
+        record,
+        lowering.mechanism,
+        EvidenceStageKind::BackendCodegen,
+    )
+    .with_context(|| {
+        format!(
+            "{} has no successful selected backend-codegen stage",
+            policy.id
+        )
+    })?;
+    let mut required_stages = vec![backend];
+    if matches!(record.status.as_str(), "validated" | "executed") {
+        required_stages.push(
+            successful_stage(record, lowering.mechanism, terminal_kind).with_context(|| {
+                format!("{} has no successful selected terminal stage", policy.id)
+            })?,
+        );
+    }
+    for stage in required_stages {
+        let (hardware, ptx) = selected_stage_floor(stage)?;
+        let allow_forward_minimum = stage.stage != EvidenceStageKind::BackendCodegen;
+        let hardware_matches = expected_hardware.iter().any(|expected| {
+            selected_stage_hardware_matches(hardware, *expected, allow_forward_minimum)
+        });
+        let ptx_matches = match lowering.backend {
+            IntrinsicBackend::LlvmNvptx => ptx == expected_ptx,
+            IntrinsicBackend::LibNvvm => ptx >= expected_ptx,
+        };
+        ensure!(
+            hardware_matches && ptx_matches,
+            "{} evidence stage {:?} targets {} / PTX {}.{} instead of a compatible target at catalog floor {} / PTX {}.{}",
+            policy.id,
+            stage.stage,
+            describe_stage_hardware(hardware),
+            ptx / 10,
+            ptx % 10,
+            expected_hardware
+                .iter()
+                .map(|hardware| describe_stage_hardware(*hardware))
+                .collect::<Vec<_>>()
+                .join(" or "),
+            expected_ptx / 10,
+            expected_ptx % 10
+        );
+    }
+    if record.status == "executed" {
+        let runtime = successful_stage(record, lowering.mechanism, EvidenceStageKind::Runtime)
+            .with_context(|| {
+                format!(
+                    "{} executed evidence has no successful runtime stage",
+                    policy.id
+                )
+            })?;
+        let (hardware, ptx) = selected_stage_floor(runtime)?;
+        let ptx_matches = match lowering.backend {
+            IntrinsicBackend::LlvmNvptx => ptx == expected_ptx,
+            IntrinsicBackend::LibNvvm => ptx >= expected_ptx,
+        };
+        ensure!(
+            expected_hardware
+                .iter()
+                .any(|expected| selected_stage_hardware_matches(hardware, *expected, true))
+                && ptx_matches,
+            "{} runtime stage target does not satisfy its catalog floor",
+            policy.id
+        );
+    }
+    Ok(())
+}
+
+pub(super) fn validate_target_matrix_stage_targets(
+    policy: &OverlayIntrinsic,
+    record: &EvidenceRecord,
+    lowering: &OverlayBackendLowering,
+    terminal_kind: EvidenceStageKind,
+    expected_hardware: &[CatalogHardwareAlternative],
+    minimum_ptx: u16,
+    paired_alternatives: Option<&[CatalogTargetAlternative]>,
+) -> Result<()> {
+    let mut required_kinds = vec![EvidenceStageKind::BackendCodegen];
+    if matches!(record.status.as_str(), "validated" | "executed") {
+        if lowering.backend == IntrinsicBackend::LibNvvm {
+            required_kinds.push(EvidenceStageKind::PtxAssembly);
+        }
+        required_kinds.push(terminal_kind);
+    }
+
+    for kind in required_kinds {
+        let stages = record
+            .stages
+            .iter()
+            .filter(|stage| {
+                stage.stage == kind
+                    && stage.mechanism == Some(lowering.mechanism)
+                    && stage.outcome == "succeeded"
+            })
+            .collect::<Vec<_>>();
+        ensure!(
+            stages.len() == expected_hardware.len(),
+            "{} target-matrix {:?} evidence must contain one structured stage for each of its {} reviewed targets",
+            policy.id,
+            kind,
+            expected_hardware.len()
+        );
+
+        let mut covered = Vec::new();
+        for stage in stages {
+            let (hardware, ptx) = selected_stage_floor(stage)?;
+            ensure!(
+                expected_hardware.contains(&hardware) && !covered.contains(&hardware),
+                "{} target-matrix {:?} evidence has an unexpected or duplicate target {}",
+                policy.id,
+                kind,
+                describe_stage_hardware(hardware)
+            );
+            covered.push(hardware);
+            let exact_floor =
+                target_matrix_ptx_floor(policy, hardware, paired_alternatives, false)?;
+            let ptx_matches = match lowering.backend {
+                IntrinsicBackend::LlvmNvptx => ptx == exact_floor,
+                IntrinsicBackend::LibNvvm => {
+                    ptx >= paired_alternatives.map_or(minimum_ptx, |_| exact_floor)
+                }
+            };
+            ensure!(
+                ptx_matches,
+                "{} target-matrix {:?} evidence records the wrong PTX floor for {}",
+                policy.id,
+                kind,
+                describe_stage_hardware(hardware)
+            );
+            if matches!(
+                kind,
+                EvidenceStageKind::PtxAssembly | EvidenceStageKind::DeviceLink
+            ) {
+                ensure!(
+                    stage
+                        .tool_path
+                        .as_deref()
+                        .is_some_and(|value| !value.is_empty())
+                        && stage
+                            .tool_version
+                            .as_deref()
+                            .is_some_and(|value| !value.is_empty())
+                        && stage
+                            .tool_sha256
+                            .as_deref()
+                            .is_some_and(|value| !value.is_empty()),
+                    "{} target-matrix {:?} evidence for {} does not identify its tool",
+                    policy.id,
+                    kind,
+                    describe_stage_hardware(hardware)
+                );
+            }
+            if kind == EvidenceStageKind::DeviceLink {
+                ensure!(
+                    stage.artifact_kind == Some(EvidenceArtifactKind::Cubin),
+                    "{} target-matrix device-link evidence for {} is not a cubin",
+                    policy.id,
+                    describe_stage_hardware(hardware)
+                );
+            }
+        }
+    }
+
+    if record.status == "executed" {
+        let runtime = record
+            .stages
+            .iter()
+            .filter(|stage| {
+                stage.stage == EvidenceStageKind::Runtime
+                    && stage.mechanism == Some(lowering.mechanism)
+                    && stage.outcome == "succeeded"
+            })
+            .collect::<Vec<_>>();
+        ensure!(
+            runtime.len() == 1,
+            "{} executed target-matrix evidence requires one successful runtime stage",
+            policy.id
+        );
+        let (hardware, ptx) = selected_stage_floor(runtime[0])?;
+        ensure!(
+            expected_hardware
+                .iter()
+                .any(|expected| { selected_stage_hardware_matches(hardware, *expected, true) }),
+            "{} runtime target {} is outside its target matrix",
+            policy.id,
+            describe_stage_hardware(hardware)
+        );
+        let floor = target_matrix_ptx_floor(policy, hardware, paired_alternatives, true)?;
+        let ptx_matches = match lowering.backend {
+            IntrinsicBackend::LlvmNvptx => ptx == floor,
+            IntrinsicBackend::LibNvvm => ptx >= floor,
+        };
+        ensure!(
+            ptx_matches,
+            "{} runtime target {} records PTX {}.{} instead of its paired floor {}.{}",
+            policy.id,
+            describe_stage_hardware(hardware),
+            ptx / 10,
+            ptx % 10,
+            floor / 10,
+            floor % 10
+        );
+    }
+    Ok(())
+}
+
+pub(super) fn target_matrix_ptx_floor(
+    policy: &OverlayIntrinsic,
+    hardware: CatalogHardwareAlternative,
+    paired_alternatives: Option<&[CatalogTargetAlternative]>,
+    allow_forward_minimum: bool,
+) -> Result<u16> {
+    if let Some(alternatives) = paired_alternatives {
+        return alternatives
+            .iter()
+            .filter(|alternative| {
+                selected_stage_hardware_matches(
+                    hardware,
+                    alternative.hardware,
+                    allow_forward_minimum,
+                )
+            })
+            .map(|alternative| alternative.minimum_ptx.encoded())
+            .min()
+            .with_context(|| {
+                format!(
+                    "{} target matrix has no PTX floor for {}",
+                    policy.id,
+                    describe_stage_hardware(hardware)
+                )
+            });
+    }
+    if is_f8f6f4_mma_target_matrix_policy(policy) {
+        f8f6f4_llvm_ptx_floor(hardware)
+    } else {
+        blackwell_ldmatrix_llvm_ptx_floor(hardware)
+    }
+}
+
+pub(super) fn f8f6f4_llvm_ptx_floor(hardware: CatalogHardwareAlternative) -> Result<u16> {
+    match hardware {
+        CatalogHardwareAlternative::ExactArchitecture { sm: 120 }
+        | CatalogHardwareAlternative::FamilyTarget { sm: 120 }
+        | CatalogHardwareAlternative::ExactArchitecture { sm: 121 }
+        | CatalogHardwareAlternative::FamilyTarget { sm: 121 } => {
+            recorded_stage_ptx_floor(hardware, 87)
+        }
+        _ => bail!(
+            "{} is not a reviewed f8f6f4 MMA target",
+            describe_stage_hardware(hardware)
+        ),
+    }
+}
+
+pub(super) fn blackwell_ldmatrix_llvm_ptx_floor(
+    hardware: CatalogHardwareAlternative,
+) -> Result<u16> {
+    match hardware {
+        CatalogHardwareAlternative::ExactArchitecture {
+            sm: 100 | 103 | 110 | 120 | 121,
+        }
+        | CatalogHardwareAlternative::FamilyTarget {
+            sm: 100 | 103 | 120 | 121,
+        }
+        | CatalogHardwareAlternative::FamilyTarget { sm: 110 } => {
+            recorded_stage_ptx_floor(hardware, 86)
+        }
+        _ => bail!(
+            "{} is not a reviewed Blackwell ldmatrix target",
+            describe_stage_hardware(hardware)
+        ),
+    }
+}
+
+pub(super) fn recorded_stage_ptx_floor(
+    hardware: CatalogHardwareAlternative,
+    instruction_floor: u16,
+) -> Result<u16> {
+    let (sm, suffix) = match hardware {
+        CatalogHardwareAlternative::MinimumSm { sm } => (sm, None),
+        CatalogHardwareAlternative::ExactArchitecture { sm } => (sm, Some('a')),
+        CatalogHardwareAlternative::FamilyTarget { sm } => (sm, Some('f')),
+    };
+    let arch = CudaArch::new(u32::from(sm), suffix)?;
+    Ok(instruction_floor.max(recorded_ptx_floor(&arch)?))
+}
+
+pub(super) fn successful_stage(
+    record: &EvidenceRecord,
+    mechanism: BackendLoweringMechanism,
+    kind: EvidenceStageKind,
+) -> Option<&crate::model::EvidenceStage> {
+    record.stages.iter().find(|stage| {
+        stage.stage == kind && stage.mechanism == Some(mechanism) && stage.outcome == "succeeded"
+    })
+}
+
+pub(super) fn is_normalized_stage_target(target: &str) -> bool {
+    if let Some(value) = target.strip_prefix("ptx") {
+        return value.len() == 2 && value.bytes().all(|byte| byte.is_ascii_digit());
+    }
+    parse_stage_hardware(target).is_some()
+}
+
+pub(super) fn parse_stage_hardware(target: &str) -> Option<CatalogHardwareAlternative> {
+    let arch = target.parse::<CudaArch>().ok()?;
+    let canonical = if target.starts_with("sm_") {
+        arch.sm()
+    } else if target.starts_with("compute_") {
+        arch.compute()
+    } else {
+        return None;
+    };
+    if canonical != target || !matches!(arch.capability().to_string().len(), 2 | 3) {
+        return None;
+    }
+    let sm = u16::try_from(arch.capability()).ok()?;
+    Some(match arch.suffix() {
+        None => CatalogHardwareAlternative::MinimumSm { sm },
+        Some('a') => CatalogHardwareAlternative::ExactArchitecture { sm },
+        Some('f') => CatalogHardwareAlternative::FamilyTarget { sm },
+        _ => unreachable!(),
+    })
+}
+
+pub(super) fn selected_stage_hardware_matches(
+    actual: CatalogHardwareAlternative,
+    expected: CatalogHardwareAlternative,
+    allow_forward_minimum: bool,
+) -> bool {
+    match expected {
+        CatalogHardwareAlternative::MinimumSm { sm: expected } => {
+            if allow_forward_minimum {
+                match actual {
+                    CatalogHardwareAlternative::MinimumSm { sm }
+                    | CatalogHardwareAlternative::ExactArchitecture { sm }
+                    | CatalogHardwareAlternative::FamilyTarget { sm } => sm >= expected,
+                }
+            } else {
+                actual == CatalogHardwareAlternative::MinimumSm { sm: expected }
+            }
+        }
+        CatalogHardwareAlternative::ExactArchitecture { .. }
+        | CatalogHardwareAlternative::FamilyTarget { .. } => actual == expected,
+    }
+}
+
+pub(super) fn describe_stage_hardware(hardware: CatalogHardwareAlternative) -> String {
+    match hardware {
+        CatalogHardwareAlternative::MinimumSm { sm } => format!("sm_{sm}"),
+        CatalogHardwareAlternative::ExactArchitecture { sm } => format!("sm_{sm}a"),
+        CatalogHardwareAlternative::FamilyTarget { sm } => format!("sm_{sm}f"),
+    }
+}
+
+pub(super) fn selected_stage_floor(
+    stage: &crate::model::EvidenceStage,
+) -> Result<(CatalogHardwareAlternative, u16)> {
+    let mut hardware = None;
+    let mut ptx = None;
+    for target in &stage.targets {
+        if let Some(value) = target.strip_prefix("ptx") {
+            let value = value.parse::<u16>()?;
+            ensure!(
+                ptx.replace(value).is_none(),
+                "stage has duplicate PTX targets"
+            );
+        } else {
+            let value = parse_stage_hardware(target)
+                .with_context(|| format!("stage has unsupported target spelling {target:?}"))?;
+            ensure!(
+                hardware.replace(value).is_none(),
+                "stage has duplicate architecture targets"
+            );
+        }
+    }
+    Ok((
+        hardware.context("selected stage has no architecture target")?,
+        ptx.context("selected stage has no PTX target")?,
+    ))
+}
+
+pub(super) fn has_valid_ptx_assembly_stage(
+    record: &EvidenceRecord,
+    mechanism: BackendLoweringMechanism,
+) -> bool {
+    has_valid_tool_stage(record, mechanism, EvidenceStageKind::PtxAssembly)
+}
+
+pub(super) fn has_valid_cubin_device_link_stage(
+    record: &EvidenceRecord,
+    mechanism: BackendLoweringMechanism,
+) -> bool {
+    has_valid_tool_stage(record, mechanism, EvidenceStageKind::DeviceLink)
+        && successful_stage(record, mechanism, EvidenceStageKind::DeviceLink)
+            .is_some_and(|stage| stage.artifact_kind == Some(EvidenceArtifactKind::Cubin))
+}
+
+pub(super) fn has_valid_tool_stage(
+    record: &EvidenceRecord,
+    mechanism: BackendLoweringMechanism,
+    stage_kind: EvidenceStageKind,
+) -> bool {
+    record.stages.iter().any(|stage| {
+        stage.stage == stage_kind
+            && stage.mechanism == Some(mechanism)
+            && stage.outcome == "succeeded"
+            && stage
+                .tool_path
+                .as_deref()
+                .is_some_and(|value| !value.is_empty())
+            && stage
+                .tool_version
+                .as_deref()
+                .is_some_and(|value| !value.is_empty())
+            && stage.tool_sha256.as_deref().is_some_and(|value| {
+                value.len() == 64 && value.bytes().all(|byte| byte.is_ascii_hexdigit())
+            })
+    })
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/clc.rs b/crates/cuda-intrinsics-gen/src/resolve/families/clc.rs
new file mode 100644
index 0000000000..146af8f710
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/clc.rs
@@ -0,0 +1,472 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, Clc, ClcAdapter, ClcAdmission, ClcOperation, ImportedIntrinsic,
+    IntrinsicBackend, OverlayBackendLowering, OverlayIntrinsic, RuntimeValidation,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+
+use crate::resolve::guards::*;
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct ClcRecipe {
+    pub(in crate::resolve) operation: ClcOperation,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) rust_arguments: &'static [&'static str],
+    pub(in crate::resolve) llvm_arguments: &'static [&'static str],
+    pub(in crate::resolve) llvm_results: &'static [&'static str],
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) dialect_operands: &'static [&'static str],
+    pub(in crate::resolve) dialect_results: &'static [&'static str],
+    pub(in crate::resolve) adapter: ClcAdapter,
+    pub(in crate::resolve) modifiers: &'static [&'static str],
+    pub(in crate::resolve) operands: &'static [OperandPattern],
+    pub(in crate::resolve) targets: &'static str,
+    pub(in crate::resolve) minimum_sm: Option<&'static str>,
+    pub(in crate::resolve) pure: bool,
+    pub(in crate::resolve) memory: &'static str,
+    pub(in crate::resolve) execution_scope: &'static str,
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn clc_recipe(operation: ClcOperation) -> ClcRecipe {
+    const TRY_OPERANDS: &[OperandPattern] = &[OperandPattern::Address, OperandPattern::Address];
+    const QUERY_OPERANDS: &[OperandPattern] = &[OperandPattern::Register, OperandPattern::Register];
+    let (abi_id, id, operation_key, source_record, llvm_symbol, op_type, op_name) = match operation
+    {
+        ClcOperation::TryCancel => (
+            "i0322",
+            "clc_try_cancel",
+            "cluster.launch_control.try_cancel",
+            "int_nvvm_clusterlaunchcontrol_try_cancel_async_shared",
+            "llvm.nvvm.clusterlaunchcontrol.try_cancel.async.shared",
+            "ClcTryCancelOp",
+            "nvvm.clc_try_cancel",
+        ),
+        ClcOperation::TryCancelMulticast => (
+            "i0323",
+            "clc_try_cancel_multicast",
+            "cluster.launch_control.try_cancel.multicast",
+            "int_nvvm_clusterlaunchcontrol_try_cancel_async_multicast_shared",
+            "llvm.nvvm.clusterlaunchcontrol.try_cancel.async.multicast.shared",
+            "ClcTryCancelMulticastOp",
+            "nvvm.clc_try_cancel_multicast",
+        ),
+        ClcOperation::QueryIsCanceled => (
+            "i0324",
+            "clc_query_is_canceled",
+            "cluster.launch_control.query.is_canceled",
+            "int_nvvm_clusterlaunchcontrol_query_cancel_is_canceled",
+            "llvm.nvvm.clusterlaunchcontrol.query_cancel.is_canceled",
+            "ClcQueryIsCanceledOp",
+            "nvvm.clc_query_is_canceled",
+        ),
+        ClcOperation::QueryGetFirstCtaidX => (
+            "i0325",
+            "clc_query_get_first_ctaid_x",
+            "cluster.launch_control.query.first_ctaid.x",
+            "int_nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_x",
+            "llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.x",
+            "ClcQueryGetFirstCtaidXOp",
+            "nvvm.clc_query_get_first_ctaid_x",
+        ),
+        ClcOperation::QueryGetFirstCtaidY => (
+            "i0326",
+            "clc_query_get_first_ctaid_y",
+            "cluster.launch_control.query.first_ctaid.y",
+            "int_nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_y",
+            "llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.y",
+            "ClcQueryGetFirstCtaidYOp",
+            "nvvm.clc_query_get_first_ctaid_y",
+        ),
+        ClcOperation::QueryGetFirstCtaidZ => (
+            "i0327",
+            "clc_query_get_first_ctaid_z",
+            "cluster.launch_control.query.first_ctaid.z",
+            "int_nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_z",
+            "llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.z",
+            "ClcQueryGetFirstCtaidZOp",
+            "nvvm.clc_query_get_first_ctaid_z",
+        ),
+    };
+    match operation {
+        ClcOperation::TryCancel | ClcOperation::TryCancelMulticast => ClcRecipe {
+            operation,
+            abi_id,
+            id,
+            operation_key,
+            source_record,
+            llvm_symbol,
+            rust_arguments: &["*mut u8", "*mut u64"],
+            llvm_arguments: &["shared_ptr", "shared_ptr"],
+            llvm_results: &[],
+            dialect_op_type: op_type,
+            dialect_op_name: op_name,
+            dialect_operands: &["ptr", "ptr"],
+            dialect_results: &[],
+            adapter: ClcAdapter::GenericPointersToShared,
+            modifiers: if operation == ClcOperation::TryCancel {
+                &[
+                    "try_cancel",
+                    "async",
+                    "shared::cta",
+                    "mbarrier::complete_tx::bytes",
+                    "b128",
+                ]
+            } else {
+                &[
+                    "try_cancel",
+                    "async",
+                    "shared::cta",
+                    "mbarrier::complete_tx::bytes",
+                    "multicast::cluster::all",
+                    "b128",
+                ]
+            },
+            operands: TRY_OPERANDS,
+            targets: if operation == ClcOperation::TryCancel {
+                "all"
+            } else {
+                // LLVM 22 exposes 101a; CUDA 13.3 exposes the other toolkit names.
+                "sm_100a|sm_101a|sm_103a|sm_110a|sm_120a|sm_121a"
+            },
+            minimum_sm: if operation == ClcOperation::TryCancel {
+                Some("sm_100")
+            } else {
+                None
+            },
+            pure: false,
+            memory: "read_write",
+            execution_scope: "cta",
+            summary: if operation == ClcOperation::TryCancel {
+                "Requests one pending CTA and writes its response to shared memory."
+            } else {
+                "Requests one pending CTA and multicasts its response across the cluster."
+            },
+        },
+        ClcOperation::QueryIsCanceled
+        | ClcOperation::QueryGetFirstCtaidX
+        | ClcOperation::QueryGetFirstCtaidY
+        | ClcOperation::QueryGetFirstCtaidZ => {
+            let (adapter, modifiers, summary) = match operation {
+                ClcOperation::QueryIsCanceled => (
+                    ClcAdapter::PairU64ToI128BoolToU32,
+                    &["query_cancel", "is_canceled", "pred", "b128"] as &[_],
+                    "Returns whether the Cluster Launch Control request was canceled.",
+                ),
+                ClcOperation::QueryGetFirstCtaidX => (
+                    ClcAdapter::PairU64ToI128U32,
+                    &["query_cancel", "get_first_ctaid::x", "b32", "b128"] as &[_],
+                    "Returns the X coordinate from a successful cancellation response.",
+                ),
+                ClcOperation::QueryGetFirstCtaidY => (
+                    ClcAdapter::PairU64ToI128U32,
+                    &["query_cancel", "get_first_ctaid::y", "b32", "b128"] as &[_],
+                    "Returns the Y coordinate from a successful cancellation response.",
+                ),
+                ClcOperation::QueryGetFirstCtaidZ => (
+                    ClcAdapter::PairU64ToI128U32,
+                    &["query_cancel", "get_first_ctaid::z", "b32", "b128"] as &[_],
+                    "Returns the Z coordinate from a successful cancellation response.",
+                ),
+                _ => unreachable!(),
+            };
+            ClcRecipe {
+                operation,
+                abi_id,
+                id,
+                operation_key,
+                source_record,
+                llvm_symbol,
+                rust_arguments: &["u64", "u64"],
+                llvm_arguments: &["i128"],
+                llvm_results: if operation == ClcOperation::QueryIsCanceled {
+                    &["i1"]
+                } else {
+                    &["i32"]
+                },
+                dialect_op_type: op_type,
+                dialect_op_name: op_name,
+                dialect_operands: &["i64", "i64"],
+                dialect_results: &["i32"],
+                adapter,
+                modifiers,
+                operands: QUERY_OPERANDS,
+                targets: "all",
+                minimum_sm: Some("sm_100"),
+                pure: true,
+                memory: "none",
+                execution_scope: "thread",
+                summary,
+            }
+        }
+    }
+}
+
+pub(in crate::resolve) fn expand_clc_admission(
+    admission: &ClcAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "CLC runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact CLC admission requires both backend evidence profiles"
+    );
+    let expected = [
+        ClcOperation::TryCancel,
+        ClcOperation::TryCancelMulticast,
+        ClcOperation::QueryIsCanceled,
+        ClcOperation::QueryGetFirstCtaidX,
+        ClcOperation::QueryGetFirstCtaidY,
+        ClcOperation::QueryGetFirstCtaidZ,
+    ];
+    ensure!(
+        admission
+            .variants
+            .iter()
+            .map(|variant| variant.operation)
+            .eq(expected),
+        "compact CLC admission must list all six operations in canonical order"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = clc_recipe(variant.operation);
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must keep reserved ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            let query = recipe.pure;
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: variant.abi_id.clone(),
+                operation_key: recipe.operation_key.into(),
+                family: "clc".into(),
+                source: None,
+                source_record: Some(recipe.source_record.into()),
+                rust_module: "clc".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments: recipe.rust_arguments.iter().map(|value| (*value).into()).collect(),
+                rust_result: if query { "u32".into() } else { "()".into() },
+                safe: false,
+                must_use: false,
+                safe_allowlist_reason: None,
+                public_rust_path: format!("cuda_intrinsics::clc::{}", recipe.id),
+                compatibility_rust_paths: vec![format!("cuda_device::clc::{}", recipe.id)],
+                dialect_op_type: recipe.dialect_op_type.into(),
+                dialect_op_name: recipe.dialect_op_name.into(),
+                dialect_operands: recipe.dialect_operands.iter().map(|value| (*value).into()).collect(),
+                dialect_results: recipe.dialect_results.iter().map(|value| (*value).into()).collect(),
+                llvm_symbol: Some(recipe.llvm_symbol.into()),
+                resolved_llvm_symbol: None,
+                llvm_arguments: recipe.llvm_arguments.iter().map(|value| (*value).into()).collect(),
+                llvm_results: recipe.llvm_results.iter().map(|value| (*value).into()).collect(),
+                pure: recipe.pure,
+                memory: recipe.memory.into(),
+                convergent: false,
+                execution_scope: recipe.execution_scope.into(),
+                minimum_ptx: "8.6".into(),
+                minimum_sm: recipe.minimum_sm.map(Into::into),
+                ptx_result: if query { "u32".into() } else { "()".into() },
+                targets: recipe.targets.into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section: "9.7.14.18-19 Cluster Launch Control".into(),
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel".into(),
+                lowering: "generated_clc".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: BackendLoweringMechanism::TypedNvvm,
+                        evidence_profile: admission.llvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some("8.6".into()),
+                        minimum_sm: recipe.minimum_sm.map(Into::into),
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::TypedNvvm,
+                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some("8.6".into()),
+                        minimum_sm: recipe.minimum_sm.map(Into::into),
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: Some(Clc {
+                    operation: recipe.operation,
+                    adapter: recipe.adapter,
+                    runtime_validation: admission.runtime_validation,
+                }),
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: "clusterlaunchcontrol".into(),
+                    modifiers: recipe.modifiers.iter().map(|value| (*value).into()).collect(),
+                    operands: if query {
+                        vec![
+                            OperandPattern::Register,
+                            OperandPattern::Exact { value: "%clc_handle".into() },
+                        ]
+                    } else {
+                        recipe.operands.to_vec()
+                    },
+                },
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn validate_clc_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let clc = policy
+        .clc
+        .as_ref()
+        .with_context(|| format!("{} has no closed CLC contract", policy.id))?;
+    let recipe = clc_recipe(clc.operation);
+    let query = recipe.pure;
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none()
+            && declaration.source_record == recipe.source_record
+            && declaration.llvm_name == recipe.llvm_symbol,
+        "{} CLC identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "clc"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == recipe.rust_arguments
+            && policy.rust_result == if query { "u32" } else { "()" }
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::clc::{}", recipe.id)
+            && policy.compatibility_rust_paths == [format!("cuda_device::clc::{}", recipe.id)],
+        "{} CLC Rust API changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == recipe.dialect_operands
+            && policy.dialect_results == recipe.dialect_results
+            && policy.llvm_arguments == recipe.llvm_arguments
+            && policy.llvm_results == recipe.llvm_results
+            && policy.lowering == "generated_clc",
+        "{} CLC carrier or LLVM adapter changed",
+        policy.id
+    );
+    ensure!(
+        declaration.arguments == recipe.llvm_arguments
+            && declaration.results == recipe.llvm_results
+            && declaration.properties
+                == if query {
+                    vec!["IntrNoMem", "IntrSpeculatable"]
+                } else {
+                    vec!["IntrArgMemOnly", "IntrHasSideEffects"]
+                },
+        "{} imported CLC declaration changed",
+        policy.id
+    );
+    ensure!(
+        policy.pure == recipe.pure
+            && policy.memory == recipe.memory
+            && !policy.convergent
+            && policy.execution_scope == recipe.execution_scope
+            && clc.adapter == recipe.adapter
+            && clc.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} CLC semantics changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == "8.6"
+            && policy.minimum_sm.as_deref() == recipe.minimum_sm
+            && policy.targets == recipe.targets
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_result == if query { "u32" } else { "()" },
+        "{} CLC target contract changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "clusterlaunchcontrol"
+            && policy.expected_ptx.modifiers == recipe.modifiers
+            && policy.expected_ptx.operands
+                == if query {
+                    vec![
+                        OperandPattern::Register,
+                        OperandPattern::Exact {
+                            value: "%clc_handle".into(),
+                        },
+                    ]
+                } else {
+                    recipe.operands.to_vec()
+                }
+            && policy.backend_lowerings.len() == 2
+            && policy.backend_lowerings.iter().all(|route| {
+                route.mechanism == BackendLoweringMechanism::TypedNvvm
+                    && route.minimum_ptx.as_deref() == Some("8.6")
+                    && route.minimum_sm.as_deref() == recipe.minimum_sm
+                    && !route.evidence_profile.trim().is_empty()
+            }),
+        "{} CLC PTX shape or backend route changed",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "CLC")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/cluster.rs b/crates/cuda-intrinsics-gen/src/resolve/families/cluster.rs
new file mode 100644
index 0000000000..9a07382a9d
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/cluster.rs
@@ -0,0 +1,791 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ClusterBarrier, ClusterBarrierAdmission, ClusterBarrierMode,
+    ClusterBarrierOrdering, ClusterMemory, ClusterMemoryAdapter, ClusterMemoryAdmission,
+    ClusterMemoryOperation, ClusterMemorySourceContract, ImportedIntrinsic, IntrinsicBackend,
+    IntrinsicSource, OverlayBackendLowering, OverlayIntrinsic, RuntimeValidation,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use crate::resolve::guards::*;
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct ClusterBarrierRecipe {
+    pub(in crate::resolve) mode: ClusterBarrierMode,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) suffix: &'static str,
+    pub(in crate::resolve) minimum_ptx: &'static str,
+    pub(in crate::resolve) ordering: ClusterBarrierOrdering,
+    pub(in crate::resolve) aligned: bool,
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn cluster_barrier_recipe(mode: ClusterBarrierMode) -> ClusterBarrierRecipe {
+    match mode {
+        ClusterBarrierMode::Arrive => ClusterBarrierRecipe {
+            mode,
+            abi_id: "i0277",
+            id: "barrier_cluster_arrive",
+            suffix: "arrive",
+            minimum_ptx: "7.8",
+            ordering: ClusterBarrierOrdering::Release,
+            aligned: false,
+            summary: "Arrives at the cluster barrier with release ordering.",
+        },
+        ClusterBarrierMode::ArriveAligned => ClusterBarrierRecipe {
+            mode,
+            abi_id: "i0278",
+            id: "barrier_cluster_arrive_aligned",
+            suffix: "arrive.aligned",
+            minimum_ptx: "7.8",
+            ordering: ClusterBarrierOrdering::Release,
+            aligned: true,
+            summary: "Arrives at the cluster barrier in aligned mode with release ordering.",
+        },
+        ClusterBarrierMode::ArriveRelaxed => ClusterBarrierRecipe {
+            mode,
+            abi_id: "i0279",
+            id: "barrier_cluster_arrive_relaxed",
+            suffix: "arrive.relaxed",
+            minimum_ptx: "8.0",
+            ordering: ClusterBarrierOrdering::Relaxed,
+            aligned: false,
+            summary: "Arrives at the cluster barrier without a release guarantee.",
+        },
+        ClusterBarrierMode::ArriveRelaxedAligned => ClusterBarrierRecipe {
+            mode,
+            abi_id: "i0280",
+            id: "barrier_cluster_arrive_relaxed_aligned",
+            suffix: "arrive.relaxed.aligned",
+            minimum_ptx: "8.0",
+            ordering: ClusterBarrierOrdering::Relaxed,
+            aligned: true,
+            summary: "Arrives at the cluster barrier in aligned mode without a release guarantee.",
+        },
+        ClusterBarrierMode::Wait => ClusterBarrierRecipe {
+            mode,
+            abi_id: "i0281",
+            id: "barrier_cluster_wait",
+            suffix: "wait",
+            minimum_ptx: "7.8",
+            ordering: ClusterBarrierOrdering::Acquire,
+            aligned: false,
+            summary: "Waits at the cluster barrier with acquire ordering.",
+        },
+        ClusterBarrierMode::WaitAligned => ClusterBarrierRecipe {
+            mode,
+            abi_id: "i0282",
+            id: "barrier_cluster_wait_aligned",
+            suffix: "wait.aligned",
+            minimum_ptx: "7.8",
+            ordering: ClusterBarrierOrdering::Acquire,
+            aligned: true,
+            summary: "Waits at the cluster barrier in aligned mode with acquire ordering.",
+        },
+    }
+}
+
+pub(in crate::resolve) fn expand_cluster_barrier_admission(
+    admission: &ClusterBarrierAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "cluster-barrier runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact cluster-barrier admission requires both backend evidence profiles"
+    );
+    let expected_modes = BTreeSet::from([
+        ClusterBarrierMode::Arrive,
+        ClusterBarrierMode::ArriveAligned,
+        ClusterBarrierMode::ArriveRelaxed,
+        ClusterBarrierMode::ArriveRelaxedAligned,
+        ClusterBarrierMode::Wait,
+        ClusterBarrierMode::WaitAligned,
+    ]);
+    let actual_modes: BTreeSet<_> = admission
+        .variants
+        .iter()
+        .map(|variant| variant.mode)
+        .collect();
+    ensure!(
+        admission.variants.len() == expected_modes.len() && actual_modes == expected_modes,
+        "compact cluster-barrier admission must contain each reviewed mode exactly once"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = cluster_barrier_recipe(variant.mode);
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must keep reserved ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            let source_record = format!("int_nvvm_barrier_cluster_{}", recipe.suffix.replace('.', "_"));
+            let llvm_symbol = format!("llvm.nvvm.barrier.cluster.{}", recipe.suffix);
+            let modifiers: Vec<String> = recipe.suffix.split('.').map(str::to_owned).collect();
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: variant.abi_id.clone(),
+                operation_key: format!("cluster.barrier.{}", recipe.suffix),
+                family: "cluster_barrier".into(),
+                source: None,
+                source_record: Some(source_record),
+                rust_module: "cluster".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments: vec![],
+                rust_result: "()".into(),
+                safe: false,
+                must_use: false,
+                safe_allowlist_reason: None,
+                public_rust_path: format!("cuda_intrinsics::cluster::{}", recipe.id),
+                compatibility_rust_paths: vec![format!("cuda_device::cluster::{}", recipe.id)],
+                dialect_op_type: "ClusterBarrierOp".into(),
+                dialect_op_name: "nvvm.cluster_barrier".into(),
+                dialect_operands: vec![],
+                dialect_results: vec![],
+                llvm_symbol: Some(llvm_symbol),
+                resolved_llvm_symbol: None,
+                llvm_arguments: vec![],
+                llvm_results: vec![],
+                pure: false,
+                memory: "read_write".into(),
+                convergent: true,
+                execution_scope: "cluster".into(),
+                minimum_ptx: recipe.minimum_ptx.into(),
+                minimum_sm: Some("sm_90".into()),
+                ptx_result: "()".into(),
+                targets: "all".into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section:
+                    "Parallel Synchronization and Communication Instructions: barrier.cluster"
+                        .into(),
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-barrier-cluster".into(),
+                lowering: "generated_cluster_barrier".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: BackendLoweringMechanism::TypedNvvm,
+                        evidence_profile: admission.llvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some(recipe.minimum_ptx.into()),
+                        minimum_sm: Some("sm_90".into()),
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some(recipe.minimum_ptx.into()),
+                        minimum_sm: Some("sm_90".into()),
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: Some(ClusterBarrier {
+                    mode: recipe.mode,
+                    ordering: recipe.ordering,
+                    aligned: recipe.aligned,
+                }),
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: "barrier".into(),
+                    modifiers: std::iter::once("cluster".into()).chain(modifiers).collect(),
+                    operands: vec![],
+                },
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn validate_cluster_barrier_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let barrier = policy
+        .cluster_barrier
+        .as_ref()
+        .with_context(|| format!("{} has no closed cluster-barrier contract", policy.id))?;
+    let recipe = cluster_barrier_recipe(barrier.mode);
+    let source_record = format!(
+        "int_nvvm_barrier_cluster_{}",
+        recipe.suffix.replace('.', "_")
+    );
+    let llvm_symbol = format!("llvm.nvvm.barrier.cluster.{}", recipe.suffix);
+    ensure!(
+        barrier.ordering == recipe.ordering
+            && barrier.aligned == recipe.aligned
+            && policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == format!("cluster.barrier.{}", recipe.suffix)
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(source_record.as_str())
+            && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} identity or semantics do not match its closed cluster-barrier recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "cluster"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments.is_empty()
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.public_rust_path == format!("cuda_intrinsics::cluster::{}", recipe.id)
+            && policy.compatibility_rust_paths == [format!("cuda_device::cluster::{}", recipe.id)],
+        "{} Rust API does not match its closed cluster-barrier recipe",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == "ClusterBarrierOp"
+            && policy.dialect_op_name == "nvvm.cluster_barrier"
+            && policy.dialect_operands.is_empty()
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments.is_empty()
+            && policy.llvm_results.is_empty()
+            && policy.lowering == "generated_cluster_barrier",
+        "{} carrier or lowering does not match its closed cluster-barrier recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.classes == ["SDPatternOperator", "Intrinsic"]
+            && declaration.properties == ["IntrConvergent", "IntrNoCallback"]
+            && !policy.pure
+            && policy.memory == "read_write"
+            && policy.convergent
+            && policy.execution_scope == "cluster",
+        "{} effects disagree with the imported cluster-barrier declaration",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == Some("sm_90")
+            && policy.targets == "all"
+            && policy.ptx_result == "()"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "Parallel Synchronization and Communication Instructions: barrier.cluster"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-barrier-cluster",
+        "{} target floor or PTX provenance changed",
+        policy.id
+    );
+    let expected_modifiers: Vec<_> = std::iter::once("cluster")
+        .chain(recipe.suffix.split('.'))
+        .collect();
+    ensure!(
+        policy.expected_ptx.mnemonic == "barrier"
+            && policy.expected_ptx.modifiers == expected_modifiers
+            && policy.expected_ptx.operands.is_empty(),
+        "{} expected PTX does not match its exact cluster-barrier spelling",
+        policy.id
+    );
+    ensure!(
+        (recipe.ordering == ClusterBarrierOrdering::Relaxed) == recipe.suffix.contains(".relaxed")
+            && recipe.aligned == recipe.suffix.ends_with(".aligned")
+            && matches!(
+                (recipe.mode, recipe.ordering),
+                (
+                    ClusterBarrierMode::Arrive | ClusterBarrierMode::ArriveAligned,
+                    ClusterBarrierOrdering::Release
+                ) | (
+                    ClusterBarrierMode::ArriveRelaxed | ClusterBarrierMode::ArriveRelaxedAligned,
+                    ClusterBarrierOrdering::Relaxed
+                ) | (
+                    ClusterBarrierMode::Wait | ClusterBarrierMode::WaitAligned,
+                    ClusterBarrierOrdering::Acquire
+                )
+            ),
+        "{} cluster-barrier semantic recipe is inconsistent",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ])
+            && policy.backend_lowerings.iter().all(|lowering| {
+                lowering.minimum_ptx.as_deref() == Some(recipe.minimum_ptx)
+                    && lowering.minimum_sm.as_deref() == Some("sm_90")
+                    && !lowering.evidence_profile.trim().is_empty()
+            }),
+        "{} must define exactly the reviewed cluster-barrier backend routes",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "cluster barrier")?;
+    Ok(())
+}
+
+#[derive(Clone)]
+pub(in crate::resolve) struct ClusterMemoryRecipe {
+    operation: ClusterMemoryOperation,
+    abi_id: &'static str,
+    id: &'static str,
+    operation_key: &'static str,
+    source_record: Option<&'static str>,
+    llvm_symbol: Option<&'static str>,
+    ptx_native_instruction: Option<&'static str>,
+    rust_arguments: &'static [&'static str],
+    rust_result: &'static str,
+    compatibility_paths: &'static [&'static str],
+    dialect_op_type: &'static str,
+    dialect_op_name: &'static str,
+    dialect_operands: &'static [&'static str],
+    dialect_results: &'static [&'static str],
+    llvm_arguments: &'static [&'static str],
+    llvm_results: &'static [&'static str],
+    adapter: ClusterMemoryAdapter,
+    source_contract: ClusterMemorySourceContract,
+    memory: &'static str,
+    expected_ptx: InstructionPattern,
+    inline_ptx: &'static str,
+    inline_constraints: &'static str,
+    ptx_isa_section: &'static str,
+    ptx_isa_anchor: &'static str,
+    summary: &'static str,
+}
+
+pub(in crate::resolve) fn cluster_memory_recipe(
+    operation: ClusterMemoryOperation,
+) -> ClusterMemoryRecipe {
+    match operation {
+        ClusterMemoryOperation::MapSharedRank => ClusterMemoryRecipe {
+            operation,
+            abi_id: "i0320",
+            id: "map_shared_rank",
+            operation_key: "cluster.shared_address.map_rank",
+            source_record: Some("int_nvvm_mapa_shared_cluster"),
+            llvm_symbol: Some("llvm.nvvm.mapa.shared.cluster"),
+            ptx_native_instruction: None,
+            rust_arguments: &["*const u8", "u32"],
+            rust_result: "*const u8",
+            compatibility_paths: &[
+                "cuda_device::cluster::map_shared_rank",
+                "cuda_device::cluster::map_shared_rank_mut",
+            ],
+            dialect_op_type: "MapaSharedClusterOp",
+            dialect_op_name: "nvvm.mapa_shared_cluster",
+            dialect_operands: &["ptr", "i32"],
+            dialect_results: &["ptr"],
+            llvm_arguments: &["shared_ptr", "i32"],
+            llvm_results: &["shared_cluster_ptr"],
+            adapter: ClusterMemoryAdapter::GenericConstAndMutPointerRankToSamePointer,
+            source_contract: ClusterMemorySourceContract::LlvmMapaSharedClusterAs7IdentityInlinePtx,
+            memory: "none",
+            expected_ptx: InstructionPattern {
+                mnemonic: "mapa".into(),
+                modifiers: vec!["shared::cluster".into(), "u64".into()],
+                operands: vec![
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                ],
+            },
+            inline_ptx: "mapa.shared::cluster.u64 $0, $1, $2;",
+            inline_constraints: "=l,l,r",
+            ptx_isa_section: "9.7.9.24 Data Movement and Conversion Instructions: mapa",
+            ptx_isa_anchor: "data-movement-and-conversion-instructions-mapa",
+            summary: "Maps a CTA-shared address to the same offset in another cluster rank.",
+        },
+        ClusterMemoryOperation::ReadU32 => ClusterMemoryRecipe {
+            operation,
+            abi_id: "i0321",
+            id: "dsmem_read_u32",
+            operation_key: "cluster.shared_memory.map_rank_then_read_u32",
+            source_record: None,
+            llvm_symbol: None,
+            ptx_native_instruction: Some("mapa.shared::cluster.u64 + ld.shared::cluster.u32"),
+            rust_arguments: &["*const u32", "u32"],
+            rust_result: "u32",
+            compatibility_paths: &["cuda_device::cluster::dsmem_read_u32"],
+            dialect_op_type: "DsmemReadU32Op",
+            dialect_op_name: "nvvm.dsmem_read_u32",
+            dialect_operands: &["ptr", "i32"],
+            dialect_results: &["i32"],
+            llvm_arguments: &[],
+            llvm_results: &[],
+            adapter: ClusterMemoryAdapter::ConstU32PointerRankToU32,
+            source_contract: ClusterMemorySourceContract::PtxNativeMapaThenWeakClusterLoad,
+            memory: "read",
+            expected_ptx: InstructionPattern {
+                mnemonic: "ld".into(),
+                modifiers: vec!["shared::cluster".into(), "u32".into()],
+                operands: vec![OperandPattern::Register, OperandPattern::Address],
+            },
+            inline_ptx: "{ .reg .u64 %mapped; mapa.shared::cluster.u64 %mapped, $1, $2; ld.shared::cluster.u32 $0, [%mapped]; }",
+            inline_constraints: "=r,l,r,~{memory}",
+            ptx_isa_section: "9.7.9.8 Data Movement and Conversion Instructions: ld",
+            ptx_isa_anchor: "data-movement-and-conversion-instructions-ld",
+            summary: "Maps a CTA-shared address to another cluster rank and reads one weak u32 value.",
+        },
+    }
+}
+
+pub(crate) fn cluster_memory_inline_recipe(
+    operation: ClusterMemoryOperation,
+) -> (&'static str, &'static str) {
+    let recipe = cluster_memory_recipe(operation);
+    (recipe.inline_ptx, recipe.inline_constraints)
+}
+
+pub(in crate::resolve) fn expand_cluster_memory_admission(
+    admission: &ClusterMemoryAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "cluster-memory runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact cluster-memory admission requires both backend evidence profiles"
+    );
+    let expected = [
+        ClusterMemoryOperation::MapSharedRank,
+        ClusterMemoryOperation::ReadU32,
+    ];
+    ensure!(
+        admission.variants.len() == expected.len()
+            && admission
+                .variants
+                .iter()
+                .map(|variant| variant.operation)
+                .eq(expected),
+        "compact cluster-memory admission must list map_shared_rank and read_u32 once in canonical order"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = cluster_memory_recipe(variant.operation);
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must keep reserved ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            let source =
+                recipe
+                    .ptx_native_instruction
+                    .map(|instruction| IntrinsicSource::PtxNative {
+                        instruction: instruction.into(),
+                    });
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: variant.abi_id.clone(),
+                operation_key: recipe.operation_key.into(),
+                family: "cluster_memory".into(),
+                source,
+                source_record: recipe.source_record.map(Into::into),
+                rust_module: "cluster".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments: recipe
+                    .rust_arguments
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                rust_result: recipe.rust_result.into(),
+                safe: false,
+                must_use: true,
+                safe_allowlist_reason: None,
+                public_rust_path: format!("cuda_intrinsics::cluster::{}", recipe.id),
+                compatibility_rust_paths: recipe
+                    .compatibility_paths
+                    .iter()
+                    .map(|path| (*path).into())
+                    .collect(),
+                dialect_op_type: recipe.dialect_op_type.into(),
+                dialect_op_name: recipe.dialect_op_name.into(),
+                dialect_operands: recipe
+                    .dialect_operands
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                dialect_results: recipe
+                    .dialect_results
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                llvm_symbol: recipe.llvm_symbol.map(Into::into),
+                resolved_llvm_symbol: None,
+                llvm_arguments: recipe
+                    .llvm_arguments
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                llvm_results: recipe
+                    .llvm_results
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                pure: false,
+                memory: recipe.memory.into(),
+                convergent: true,
+                execution_scope: "cluster".into(),
+                minimum_ptx: "7.8".into(),
+                minimum_sm: Some("sm_90".into()),
+                ptx_result: recipe.rust_result.into(),
+                targets: "all".into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section: recipe.ptx_isa_section.into(),
+                ptx_isa_url: format!(
+                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#{}",
+                    recipe.ptx_isa_anchor
+                ),
+                lowering: "generated_cluster_memory_inline_ptx".into(),
+                backend_lowerings: [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
+                    .into_iter()
+                    .map(|backend| OverlayBackendLowering {
+                        backend,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: match backend {
+                            IntrinsicBackend::LlvmNvptx => admission.llvm_evidence_profile.clone(),
+                            IntrinsicBackend::LibNvvm => admission.libnvvm_evidence_profile.clone(),
+                        },
+                        targets: None,
+                        minimum_ptx: Some("7.8".into()),
+                        minimum_sm: Some("sm_90".into()),
+                    })
+                    .collect(),
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: Some(ClusterMemory {
+                    operation: recipe.operation,
+                    adapter: recipe.adapter,
+                    source_contract: recipe.source_contract,
+                    runtime_validation: admission.runtime_validation,
+                }),
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: recipe.expected_ptx,
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn validate_cluster_memory_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+    declaration: Option<&ImportedIntrinsic>,
+) -> Result<()> {
+    let cluster = policy
+        .cluster_memory
+        .as_ref()
+        .with_context(|| format!("{} has no closed cluster-memory contract", policy.id))?;
+    let recipe = cluster_memory_recipe(cluster.operation);
+    ensure!(
+        cluster.adapter == recipe.adapter
+            && cluster.source_contract == recipe.source_contract
+            && cluster.runtime_validation == RuntimeValidation::Unexecuted
+            && policy.id == recipe.id
+            && policy.operation_key == recipe.operation_key,
+        "{} does not match its closed cluster-memory identity",
+        policy.id
+    );
+    match cluster.source_contract {
+        ClusterMemorySourceContract::LlvmMapaSharedClusterAs7IdentityInlinePtx => {
+            let declaration = declaration.context("map_shared_rank requires its LLVM identity")?;
+            ensure!(
+                matches!(source, IntrinsicSource::LlvmImported { source_record }
+                    if source_record == "int_nvvm_mapa_shared_cluster")
+                    && policy.source.is_none()
+                    && policy.source_record.as_deref() == recipe.source_record
+                    && policy.llvm_symbol.as_deref() == recipe.llvm_symbol
+                    && declaration.arguments == ["shared_ptr", "i32"]
+                    && declaration.results == ["shared_cluster_ptr"]
+                    && declaration.properties
+                        == ["IntrNoMem", "IntrSpeculatable", "NoCapture<arg0>"],
+                "{} must retain the AS7-returning LLVM mapa record as identity only",
+                policy.id
+            );
+            let mut selections = Vec::new();
+            for selection in &declaration.selections {
+                if selection_matches_policy(policy, selection)? {
+                    selections.push(selection);
+                }
+            }
+            ensure!(
+                selections.len() == 2
+                    && selections
+                        .iter()
+                        .map(|selection| selection.source_record.as_str())
+                        .collect::<BTreeSet<_>>()
+                        == BTreeSet::from(["mapa_shared_cluster_64", "mapa_shared_cluster_64i",])
+                    && selections.iter().all(|selection| {
+                        selection.asm == "mapa.shared::cluster.u64 \t$d, $a, $b;"
+                            && selection.predicates
+                                == [
+                                    "Subtarget->getSmVersion() >= 90",
+                                    "Subtarget->getPTXVersion() >= 78",
+                                ]
+                    }),
+                "{} must retain both exact 64-bit mapa selections",
+                policy.id
+            );
+        }
+        ClusterMemorySourceContract::PtxNativeMapaThenWeakClusterLoad => ensure!(
+            matches!(source, IntrinsicSource::PtxNative { instruction }
+                if Some(instruction.as_str()) == recipe.ptx_native_instruction)
+                && policy.source_record.is_none()
+                && policy.llvm_symbol.is_none()
+                && declaration.is_none()
+                && policy.llvm_arguments.is_empty()
+                && policy.llvm_results.is_empty(),
+            "{} must remain a PTX-native mapa plus weak cluster-load composite",
+            policy.id
+        ),
+    }
+    ensure!(
+        policy.rust_module == "cluster"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == recipe.rust_arguments
+            && policy.rust_result == recipe.rust_result
+            && !policy.safe
+            && policy.must_use
+            && policy.public_rust_path == format!("cuda_intrinsics::cluster::{}", recipe.id)
+            && policy.compatibility_rust_paths == recipe.compatibility_paths,
+        "{} Rust API or compatibility paths changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == recipe.dialect_operands
+            && policy.dialect_results == recipe.dialect_results
+            && policy.llvm_arguments == recipe.llvm_arguments
+            && policy.llvm_results == recipe.llvm_results
+            && policy.lowering == "generated_cluster_memory_inline_ptx",
+        "{} dialect carrier or AS7 source boundary changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == recipe.memory
+            && policy.convergent
+            && policy.execution_scope == "cluster",
+        "{} effects changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == "7.8"
+            && policy.minimum_sm.as_deref() == Some("sm_90")
+            && policy.targets == "all"
+            && policy.ptx_result == recipe.rust_result
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.ptx_isa_section
+            && policy.ptx_isa_url
+                == format!(
+                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#{}",
+                    recipe.ptx_isa_anchor
+                ),
+        "{} PTX provenance or target floor changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx == recipe.expected_ptx,
+        "{} expected PTX changed",
+        policy.id
+    );
+    ensure_exact_inline_ptx_backends(
+        policy,
+        [
+            (IntrinsicBackend::LlvmNvptx, "7.8", Some("sm_90")),
+            (IntrinsicBackend::LibNvvm, "7.8", Some("sm_90")),
+        ],
+        "cluster-memory",
+    )?;
+    ensure_no_other_family_contract(policy, "cluster-memory")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/cp_async.rs b/crates/cuda-intrinsics-gen/src/resolve/families/cp_async.rs
new file mode 100644
index 0000000000..faf83aedbd
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/cp_async.rs
@@ -0,0 +1,1121 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CpAsyncAdapter, CpAsyncCachePolicy, CpAsyncControlAdapter,
+    CpAsyncControlOperation, CpAsyncCopySize, CpAsyncMbarrierAdapter, CpAsyncMbarrierOperation,
+    CpAsyncMbarrierStateSpace, CpAsyncSourceSize, ImportedIntrinsic, IntrinsicBackend,
+    MbarrierBasicAdapter, MbarrierBasicOperation, MbarrierStateSpace, OverlayIntrinsic,
+    RuntimeValidation,
+};
+use crate::ptx::OperandPattern;
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use crate::resolve::guards::*;
+
+pub(in crate::resolve) struct CpAsyncCopyRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) rust_name: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) selections: &'static [&'static str],
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn cp_async_copy_recipe(
+    copy: &crate::model::CpAsyncCopy,
+) -> Option<CpAsyncCopyRecipe> {
+    match (copy.cache_policy, copy.copy_size, copy.source_size) {
+        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B4, CpAsyncSourceSize::Full) => {
+            Some(CpAsyncCopyRecipe {
+                id: "cp_async_ca_4",
+                abi_id: "i0086",
+                operation_key: "memory.copy.async.global_to_shared.ca.4.full",
+                rust_name: "cp_async_ca_4",
+                dialect_op_type: "CpAsyncCa4Op",
+                dialect_op_name: "nvvm.cp_async_ca_4",
+                source_record: "int_nvvm_cp_async_ca_shared_global_4",
+                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.4",
+                selections: &["CP_ASYNC_CA_SHARED_GLOBAL_4"],
+                summary: "Starts a four-byte cache-all asynchronous copy from global to shared memory.",
+            })
+        }
+        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B4, CpAsyncSourceSize::Runtime) => {
+            Some(CpAsyncCopyRecipe {
+                id: "cp_async_ca_zfill_4",
+                abi_id: "i0087",
+                operation_key: "memory.copy.async.global_to_shared.ca.4.runtime_source_size",
+                rust_name: "cp_async_ca_zfill_4",
+                dialect_op_type: "CpAsyncCaZfill4Op",
+                dialect_op_name: "nvvm.cp_async_ca_zfill_4",
+                source_record: "int_nvvm_cp_async_ca_shared_global_4_s",
+                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.4.s",
+                selections: &[
+                    "CP_ASYNC_CA_SHARED_GLOBAL_4_s",
+                    "CP_ASYNC_CA_SHARED_GLOBAL_4_si",
+                ],
+                summary: "Starts a four-byte cache-all asynchronous copy and zero-fills bytes beyond the runtime source size.",
+            })
+        }
+        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B8, CpAsyncSourceSize::Full) => {
+            Some(CpAsyncCopyRecipe {
+                id: "cp_async_ca_8",
+                abi_id: "i0088",
+                operation_key: "memory.copy.async.global_to_shared.ca.8.full",
+                rust_name: "cp_async_ca_8",
+                dialect_op_type: "CpAsyncCa8Op",
+                dialect_op_name: "nvvm.cp_async_ca_8",
+                source_record: "int_nvvm_cp_async_ca_shared_global_8",
+                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.8",
+                selections: &["CP_ASYNC_CA_SHARED_GLOBAL_8"],
+                summary: "Starts an eight-byte cache-all asynchronous copy from global to shared memory.",
+            })
+        }
+        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B8, CpAsyncSourceSize::Runtime) => {
+            Some(CpAsyncCopyRecipe {
+                id: "cp_async_ca_zfill_8",
+                abi_id: "i0089",
+                operation_key: "memory.copy.async.global_to_shared.ca.8.runtime_source_size",
+                rust_name: "cp_async_ca_zfill_8",
+                dialect_op_type: "CpAsyncCaZfill8Op",
+                dialect_op_name: "nvvm.cp_async_ca_zfill_8",
+                source_record: "int_nvvm_cp_async_ca_shared_global_8_s",
+                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.8.s",
+                selections: &[
+                    "CP_ASYNC_CA_SHARED_GLOBAL_8_s",
+                    "CP_ASYNC_CA_SHARED_GLOBAL_8_si",
+                ],
+                summary: "Starts an eight-byte cache-all asynchronous copy and zero-fills bytes beyond the runtime source size.",
+            })
+        }
+        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B16, CpAsyncSourceSize::Full) => {
+            Some(CpAsyncCopyRecipe {
+                id: "cp_async_ca_16",
+                abi_id: "i0090",
+                operation_key: "memory.copy.async.global_to_shared.ca.16.full",
+                rust_name: "cp_async_ca_16",
+                dialect_op_type: "CpAsyncCa16Op",
+                dialect_op_name: "nvvm.cp_async_ca_16",
+                source_record: "int_nvvm_cp_async_ca_shared_global_16",
+                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.16",
+                selections: &["CP_ASYNC_CA_SHARED_GLOBAL_16"],
+                summary: "Starts a sixteen-byte cache-all asynchronous copy from global to shared memory.",
+            })
+        }
+        (CpAsyncCachePolicy::Ca, CpAsyncCopySize::B16, CpAsyncSourceSize::Runtime) => {
+            Some(CpAsyncCopyRecipe {
+                id: "cp_async_ca_zfill_16",
+                abi_id: "i0091",
+                operation_key: "memory.copy.async.global_to_shared.ca.16.runtime_source_size",
+                rust_name: "cp_async_ca_zfill_16",
+                dialect_op_type: "CpAsyncCaZfill16Op",
+                dialect_op_name: "nvvm.cp_async_ca_zfill_16",
+                source_record: "int_nvvm_cp_async_ca_shared_global_16_s",
+                llvm_symbol: "llvm.nvvm.cp.async.ca.shared.global.16.s",
+                selections: &[
+                    "CP_ASYNC_CA_SHARED_GLOBAL_16_s",
+                    "CP_ASYNC_CA_SHARED_GLOBAL_16_si",
+                ],
+                summary: "Starts a sixteen-byte cache-all asynchronous copy and zero-fills bytes beyond the runtime source size.",
+            })
+        }
+        (CpAsyncCachePolicy::Cg, CpAsyncCopySize::B16, CpAsyncSourceSize::Full) => {
+            Some(CpAsyncCopyRecipe {
+                id: "cp_async_cg_16",
+                abi_id: "i0092",
+                operation_key: "memory.copy.async.global_to_shared.cg.16.full",
+                rust_name: "cp_async_cg_16",
+                dialect_op_type: "CpAsyncCg16Op",
+                dialect_op_name: "nvvm.cp_async_cg_16",
+                source_record: "int_nvvm_cp_async_cg_shared_global_16",
+                llvm_symbol: "llvm.nvvm.cp.async.cg.shared.global.16",
+                selections: &["CP_ASYNC_CG_SHARED_GLOBAL_16"],
+                summary: "Starts a sixteen-byte cache-global asynchronous copy from global to shared memory.",
+            })
+        }
+        (CpAsyncCachePolicy::Cg, CpAsyncCopySize::B16, CpAsyncSourceSize::Runtime) => {
+            Some(CpAsyncCopyRecipe {
+                id: "cp_async_cg_zfill_16",
+                abi_id: "i0093",
+                operation_key: "memory.copy.async.global_to_shared.cg.16.runtime_source_size",
+                rust_name: "cp_async_cg_zfill_16",
+                dialect_op_type: "CpAsyncCgZfill16Op",
+                dialect_op_name: "nvvm.cp_async_cg_zfill_16",
+                source_record: "int_nvvm_cp_async_cg_shared_global_16_s",
+                llvm_symbol: "llvm.nvvm.cp.async.cg.shared.global.16.s",
+                selections: &[
+                    "CP_ASYNC_CG_SHARED_GLOBAL_16_s",
+                    "CP_ASYNC_CG_SHARED_GLOBAL_16_si",
+                ],
+                summary: "Starts a sixteen-byte cache-global asynchronous copy and zero-fills bytes beyond the runtime source size.",
+            })
+        }
+        _ => None,
+    }
+}
+
+pub(in crate::resolve) fn validate_cp_async_copy_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let copy = policy
+        .cp_async_copy
+        .as_ref()
+        .with_context(|| format!("{} has no closed cp.async copy contract", policy.id))?;
+    let recipe = cp_async_copy_recipe(copy).with_context(|| {
+        format!(
+            "{} requests an unsupported classic cp.async copy form",
+            policy.id
+        )
+    })?;
+    let dynamic_source_size = copy.source_size == CpAsyncSourceSize::Runtime;
+    let expected_adapter = if dynamic_source_size {
+        CpAsyncAdapter::DirectPointersAndSourceSize
+    } else {
+        CpAsyncAdapter::DirectPointers
+    };
+    ensure!(
+        copy.adapter == expected_adapter,
+        "{} cp.async source-size form and adapter disagree",
+        policy.id
+    );
+    ensure!(
+        copy.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} cannot claim unrecorded cp.async runtime validation",
+        policy.id
+    );
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} cp.async identity does not match its closed recipe",
+        policy.id
+    );
+    let rust_arguments = if dynamic_source_size {
+        vec!["*mut u32", "*const u8", "u32"]
+    } else {
+        vec!["*mut u32", "*const u32"]
+    };
+    ensure!(
+        policy.rust_module == "async_copy"
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == rust_arguments
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path
+                == format!("cuda_intrinsics::async_copy::{}", recipe.rust_name)
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::async_copy::{}", recipe.rust_name)],
+        "{} must preserve its unsafe cp.async raw and compatibility API",
+        policy.id
+    );
+    let llvm_arguments = if dynamic_source_size {
+        vec!["shared_ptr", "global_ptr", "i32"]
+    } else {
+        vec!["shared_ptr", "global_ptr"]
+    };
+    let dialect_operands = if dynamic_source_size {
+        vec!["ptr", "ptr", "i32"]
+    } else {
+        vec!["ptr", "ptr"]
+    };
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == dialect_operands
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == llvm_arguments
+            && policy.llvm_results.is_empty()
+            && policy.lowering == "generated_cp_async_copy",
+        "{} is outside the closed cp.async signature and lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read_write"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == "7.0"
+            && policy.minimum_sm.as_deref() == Some("sm_80")
+            && policy.ptx_result == "()"
+            && policy.targets == "all",
+        "{} cp.async effects or target floor disagree with the closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.9.26.3.1 Data Movement and Conversion Instructions: cp.async"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async",
+        "{} cp.async PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.summary == recipe.summary,
+        "{} cp.async summary does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.properties
+            == [
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "NoAlias<arg0>",
+                "NoAlias<arg1>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+        "{} cp.async effects disagree with the imported LLVM declaration",
+        policy.id
+    );
+    let cache = match copy.cache_policy {
+        CpAsyncCachePolicy::Ca => "ca",
+        CpAsyncCachePolicy::Cg => "cg",
+    };
+    let mut operands = vec![
+        OperandPattern::Address,
+        OperandPattern::Address,
+        OperandPattern::Exact {
+            value: copy.copy_size.bytes().to_string(),
+        },
+    ];
+    if dynamic_source_size {
+        operands.push(OperandPattern::RegisterOrImmediate);
+    }
+    ensure!(
+        policy.expected_ptx.mnemonic == "cp"
+            && policy.expected_ptx.modifiers == ["async", cache, "shared", "global"]
+            && policy.expected_ptx.operands == operands,
+        "{} expected PTX does not match its cp.async recipe",
+        policy.id
+    );
+    let actual_selections: BTreeSet<_> = declaration
+        .selections
+        .iter()
+        .map(|selection| selection.source_record.as_str())
+        .collect();
+    ensure!(
+        actual_selections == recipe.selections.iter().copied().collect(),
+        "{} imported cp.async selection set changed",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ])
+            && policy.backend_lowerings.iter().all(|lowering| {
+                lowering.minimum_ptx.is_none()
+                    && lowering.minimum_sm.is_none()
+                    && !lowering.evidence_profile.trim().is_empty()
+            }),
+        "{} must define the reviewed typed-LLVM and inline-PTX cp.async routes",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "cp_async_copy")?;
+    ensure!(
+        policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes ldmatrix state with cp_async_copy",
+        policy.id
+    );
+    Ok(())
+}
+
+pub(in crate::resolve) struct CpAsyncControlRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) rust_name: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) selection: &'static str,
+    pub(in crate::resolve) ptx_modifier: &'static str,
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn cp_async_control_recipe(
+    operation: CpAsyncControlOperation,
+) -> CpAsyncControlRecipe {
+    match operation {
+        CpAsyncControlOperation::CommitGroup => CpAsyncControlRecipe {
+            id: "cp_async_commit_group",
+            abi_id: "i0094",
+            operation_key: "memory.copy.async.group.commit",
+            rust_name: "cp_async_commit_group",
+            dialect_op_type: "CpAsyncCommitGroupOp",
+            dialect_op_name: "nvvm.cp_async_commit_group",
+            source_record: "int_nvvm_cp_async_commit_group",
+            llvm_symbol: "llvm.nvvm.cp.async.commit.group",
+            selection: "CP_ASYNC_COMMIT_GROUP",
+            ptx_modifier: "commit_group",
+            summary: "Commits this thread's uncommitted asynchronous copies as one group.",
+        },
+        CpAsyncControlOperation::WaitAll => CpAsyncControlRecipe {
+            id: "cp_async_wait_all",
+            abi_id: "i0095",
+            operation_key: "memory.copy.async.group.wait_all",
+            rust_name: "cp_async_wait_all",
+            dialect_op_type: "CpAsyncWaitAllOp",
+            dialect_op_name: "nvvm.cp_async_wait_all",
+            source_record: "int_nvvm_cp_async_wait_all",
+            llvm_symbol: "llvm.nvvm.cp.async.wait.all",
+            selection: "CP_ASYNC_WAIT_ALL",
+            ptx_modifier: "wait_all",
+            summary: "Waits for all asynchronous copy groups issued by this thread.",
+        },
+        CpAsyncControlOperation::WaitGroup => CpAsyncControlRecipe {
+            id: "cp_async_wait_group",
+            abi_id: "i0096",
+            operation_key: "memory.copy.async.group.wait_max_pending",
+            rust_name: "cp_async_wait_group",
+            dialect_op_type: "CpAsyncWaitGroupOp",
+            dialect_op_name: "nvvm.cp_async_wait_group",
+            source_record: "int_nvvm_cp_async_wait_group",
+            llvm_symbol: "llvm.nvvm.cp.async.wait.group",
+            selection: "CP_ASYNC_WAIT_GROUP",
+            ptx_modifier: "wait_group",
+            summary: "Waits until at most the compile-time constant number of recent asynchronous copy groups remain pending.",
+        },
+    }
+}
+
+pub(in crate::resolve) fn validate_cp_async_control_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let control = policy
+        .cp_async_control
+        .as_ref()
+        .with_context(|| format!("{} has no closed cp.async control contract", policy.id))?;
+    let recipe = cp_async_control_recipe(control.operation);
+    let has_operand = control.operation == CpAsyncControlOperation::WaitGroup;
+    let expected_adapter = if has_operand {
+        CpAsyncControlAdapter::CompileTimeConstantMaxPending
+    } else {
+        CpAsyncControlAdapter::NoOperands
+    };
+    ensure!(
+        control.adapter == expected_adapter,
+        "{} cp.async control and adapter disagree",
+        policy.id
+    );
+    ensure!(
+        control.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} cannot claim unrecorded cp.async control runtime validation",
+        policy.id
+    );
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} cp.async control identity does not match its closed recipe",
+        policy.id
+    );
+    let rust_arguments = if has_operand { vec!["u32"] } else { vec![] };
+    let dialect_operands = if has_operand { vec!["i32"] } else { vec![] };
+    ensure!(
+        policy.rust_module == "async_copy"
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == rust_arguments
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path
+                == format!("cuda_intrinsics::async_copy::{}", recipe.rust_name)
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::async_copy::{}", recipe.rust_name)]
+            && policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == dialect_operands
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == dialect_operands
+            && policy.llvm_results.is_empty()
+            && policy.lowering == "generated_cp_async_control",
+        "{} is outside the closed cp.async control API and lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read_write"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == "7.0"
+            && policy.minimum_sm.as_deref() == Some("sm_80")
+            && policy.ptx_result == "()"
+            && policy.targets == "all",
+        "{} cp.async control effects or target floor disagree with the closed recipe",
+        policy.id
+    );
+    let (ptx_isa_section, ptx_isa_url) = match control.operation {
+        CpAsyncControlOperation::CommitGroup => (
+            "9.7.9.26.3.2 Data Movement and Conversion Instructions: cp.async.commit_group",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-commit-group",
+        ),
+        CpAsyncControlOperation::WaitAll | CpAsyncControlOperation::WaitGroup => (
+            "9.7.9.26.3.3 Data Movement and Conversion Instructions: cp.async.wait_group / cp.async.wait_all",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-wait-group-cp-async-wait-all",
+        ),
+    };
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == ptx_isa_section
+            && policy.ptx_isa_url == ptx_isa_url,
+        "{} cp.async control PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.summary == recipe.summary,
+        "{} cp.async control summary does not match its closed recipe",
+        policy.id
+    );
+    let expected_properties: Vec<String> = if has_operand {
+        vec!["ImmArg<arg0>".into()]
+    } else {
+        vec![]
+    };
+    ensure!(
+        declaration.properties == expected_properties,
+        "{} cp.async control properties disagree with the imported declaration",
+        policy.id
+    );
+    let operands = if has_operand {
+        vec![OperandPattern::Immediate]
+    } else {
+        vec![]
+    };
+    ensure!(
+        policy.expected_ptx.mnemonic == "cp"
+            && policy.expected_ptx.modifiers == ["async", recipe.ptx_modifier]
+            && policy.expected_ptx.operands == operands
+            && declaration.selections.len() == 1
+            && declaration.selections[0].source_record == recipe.selection,
+        "{} expected PTX or imported selection disagrees with its cp.async control recipe",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ])
+            && policy.backend_lowerings.iter().all(|lowering| {
+                lowering.minimum_ptx.is_none()
+                    && lowering.minimum_sm.is_none()
+                    && !lowering.evidence_profile.trim().is_empty()
+            }),
+        "{} must define the reviewed typed-LLVM and inline-PTX cp.async control routes",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "cp_async_control")?;
+    ensure!(
+        policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes ldmatrix state with cp_async_control",
+        policy.id
+    );
+    Ok(())
+}
+
+pub(in crate::resolve) struct CpAsyncMbarrierRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) llvm_argument: &'static str,
+    pub(in crate::resolve) selection: &'static str,
+    pub(in crate::resolve) selection_asm: &'static str,
+    pub(in crate::resolve) modifiers: &'static [&'static str],
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn cp_async_mbarrier_recipe(
+    operation: CpAsyncMbarrierOperation,
+    state_space: CpAsyncMbarrierStateSpace,
+) -> CpAsyncMbarrierRecipe {
+    match (operation, state_space) {
+        (CpAsyncMbarrierOperation::Arrive, CpAsyncMbarrierStateSpace::Generic) => {
+            CpAsyncMbarrierRecipe {
+                id: "cp_async_mbarrier_arrive",
+                abi_id: "i0101",
+                operation_key: "memory.copy.async.mbarrier.arrive.generic.increment",
+                dialect_op_type: "CpAsyncMbarrierArriveOp",
+                dialect_op_name: "nvvm.cp_async_mbarrier_arrive",
+                source_record: "int_nvvm_cp_async_mbarrier_arrive",
+                llvm_symbol: "llvm.nvvm.cp.async.mbarrier.arrive",
+                llvm_argument: "ptr",
+                selection: "CP_ASYNC_MBARRIER_ARRIVE",
+                selection_asm: "cp.async.mbarrier.arrive.b64 \t[$addr];",
+                modifiers: &["async", "mbarrier", "arrive", "b64"],
+                summary: "Associates this thread's prior asynchronous copies with a shared-memory barrier using balanced pending-count accounting.",
+            }
+        }
+        (CpAsyncMbarrierOperation::ArriveNoInc, CpAsyncMbarrierStateSpace::Generic) => {
+            CpAsyncMbarrierRecipe {
+                id: "cp_async_mbarrier_arrive_noinc",
+                abi_id: "i0103",
+                operation_key: "memory.copy.async.mbarrier.arrive.generic.no_increment",
+                dialect_op_type: "CpAsyncMbarrierArriveNoIncOp",
+                dialect_op_name: "nvvm.cp_async_mbarrier_arrive_noinc",
+                source_record: "int_nvvm_cp_async_mbarrier_arrive_noinc",
+                llvm_symbol: "llvm.nvvm.cp.async.mbarrier.arrive.noinc",
+                llvm_argument: "ptr",
+                selection: "CP_ASYNC_MBARRIER_ARRIVE_NOINC",
+                selection_asm: "cp.async.mbarrier.arrive.noinc.b64 \t[$addr];",
+                modifiers: &["async", "mbarrier", "arrive", "noinc", "b64"],
+                summary: "Associates this thread's prior asynchronous copies with a shared-memory barrier without incrementing its pending count.",
+            }
+        }
+        (CpAsyncMbarrierOperation::ArriveNoInc, CpAsyncMbarrierStateSpace::Shared) => {
+            CpAsyncMbarrierRecipe {
+                id: "cp_async_mbarrier_arrive_noinc_shared",
+                abi_id: "i0104",
+                operation_key: "memory.copy.async.mbarrier.arrive.shared.no_increment",
+                dialect_op_type: "CpAsyncMbarrierArriveNoIncSharedOp",
+                dialect_op_name: "nvvm.cp_async_mbarrier_arrive_noinc_shared",
+                source_record: "int_nvvm_cp_async_mbarrier_arrive_noinc_shared",
+                llvm_symbol: "llvm.nvvm.cp.async.mbarrier.arrive.noinc.shared",
+                llvm_argument: "shared_ptr",
+                selection: "CP_ASYNC_MBARRIER_ARRIVE_NOINC_SHARED",
+                selection_asm: "cp.async.mbarrier.arrive.noinc.shared.b64 \t[$addr];",
+                modifiers: &["async", "mbarrier", "arrive", "noinc", "shared", "b64"],
+                summary: "Associates this thread's prior asynchronous copies with a shared-address barrier without incrementing its pending count.",
+            }
+        }
+        (CpAsyncMbarrierOperation::Arrive, CpAsyncMbarrierStateSpace::Shared) => {
+            CpAsyncMbarrierRecipe {
+                id: "cp_async_mbarrier_arrive_shared",
+                abi_id: "i0102",
+                operation_key: "memory.copy.async.mbarrier.arrive.shared.increment",
+                dialect_op_type: "CpAsyncMbarrierArriveSharedOp",
+                dialect_op_name: "nvvm.cp_async_mbarrier_arrive_shared",
+                source_record: "int_nvvm_cp_async_mbarrier_arrive_shared",
+                llvm_symbol: "llvm.nvvm.cp.async.mbarrier.arrive.shared",
+                llvm_argument: "shared_ptr",
+                selection: "CP_ASYNC_MBARRIER_ARRIVE_SHARED",
+                selection_asm: "cp.async.mbarrier.arrive.shared.b64 \t[$addr];",
+                modifiers: &["async", "mbarrier", "arrive", "shared", "b64"],
+                summary: "Associates this thread's prior asynchronous copies with a shared-address barrier using balanced pending-count accounting.",
+            }
+        }
+    }
+}
+
+pub(in crate::resolve) fn validate_cp_async_mbarrier_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let bridge = policy
+        .cp_async_mbarrier
+        .as_ref()
+        .with_context(|| format!("{} has no closed cp.async mbarrier contract", policy.id))?;
+    let recipe = cp_async_mbarrier_recipe(bridge.operation, bridge.state_space);
+    ensure!(
+        bridge.adapter == CpAsyncMbarrierAdapter::PointerToVoid,
+        "{} cp.async mbarrier adapter changed",
+        policy.id
+    );
+    ensure!(
+        bridge.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} cannot claim unrecorded cp.async mbarrier runtime validation",
+        policy.id
+    );
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} cp.async mbarrier identity does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "async_copy"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == ["*mut u64"]
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::async_copy::{}", recipe.id)
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::async_copy::{}", recipe.id)],
+        "{} is outside the closed cp.async mbarrier Rust API",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == ["ptr"]
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == [recipe.llvm_argument]
+            && policy.llvm_results.is_empty()
+            && policy.lowering == "generated_cp_async_mbarrier",
+        "{} is outside the closed cp.async mbarrier signature and lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read_write"
+            && policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == "7.0"
+            && policy.minimum_sm.as_deref() == Some("sm_80")
+            && policy.ptx_result == "()"
+            && policy.targets == "all",
+        "{} cp.async mbarrier effects or target floor disagree with the closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.14.16.18 Parallel Synchronization and Communication Instructions: cp.async.mbarrier.arrive"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-cp-async-mbarrier-arrive",
+        "{} cp.async mbarrier PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.summary == recipe.summary,
+        "{} cp.async mbarrier summary does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.properties == ["IntrConvergent", "IntrNoCallback"],
+        "{} cp.async mbarrier properties disagree with the imported declaration",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "cp"
+            && policy
+                .expected_ptx
+                .modifiers
+                .iter()
+                .map(String::as_str)
+                .eq(recipe.modifiers.iter().copied())
+            && policy.expected_ptx.operands == [OperandPattern::Address],
+        "{} expected PTX does not match its cp.async mbarrier recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.selections.len() == 1
+            && declaration.selections[0].source_record == recipe.selection
+            && declaration.selections[0].asm == recipe.selection_asm
+            && declaration.selections[0].predicates
+                == [
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70",
+                ]
+            && declaration.selections[0].constraints.is_empty(),
+        "{} imported cp.async mbarrier selection changed",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ])
+            && policy.backend_lowerings.iter().all(|lowering| {
+                lowering.minimum_ptx.is_none()
+                    && lowering.minimum_sm.is_none()
+                    && !lowering.evidence_profile.trim().is_empty()
+            }),
+        "{} must define the reviewed typed-LLVM and inline-PTX cp.async mbarrier routes",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "cp_async_mbarrier")?;
+    Ok(())
+}
+
+pub(in crate::resolve) struct MbarrierBasicRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) rust_arguments: &'static [&'static str],
+    pub(in crate::resolve) rust_result: &'static str,
+    pub(in crate::resolve) must_use: bool,
+    pub(in crate::resolve) adapter: MbarrierBasicAdapter,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) dialect_operands: &'static [&'static str],
+    pub(in crate::resolve) dialect_results: &'static [&'static str],
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) llvm_arguments: &'static [&'static str],
+    pub(in crate::resolve) llvm_results: &'static [&'static str],
+    pub(in crate::resolve) memory: &'static str,
+    pub(in crate::resolve) ptx_result: &'static str,
+    pub(in crate::resolve) selection: &'static str,
+    pub(in crate::resolve) selection_asm: &'static str,
+    pub(in crate::resolve) ptx_modifier: &'static str,
+    pub(in crate::resolve) ptx_isa_section: &'static str,
+    pub(in crate::resolve) ptx_isa_url: &'static str,
+    pub(in crate::resolve) llvm_nvptx_mechanism: BackendLoweringMechanism,
+    pub(in crate::resolve) lib_nvvm_mechanism: BackendLoweringMechanism,
+    pub(in crate::resolve) properties: &'static [&'static str],
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn mbarrier_basic_recipe(
+    operation: MbarrierBasicOperation,
+) -> MbarrierBasicRecipe {
+    match operation {
+        MbarrierBasicOperation::Init => MbarrierBasicRecipe {
+            id: "mbarrier_init",
+            abi_id: "i0097",
+            operation_key: "barrier.mbarrier.init.shared.cta",
+            rust_arguments: &["*mut u64", "u32"],
+            rust_result: "()",
+            must_use: false,
+            adapter: MbarrierBasicAdapter::InitPointerCountToVoid,
+            dialect_op_type: "MbarrierInitSharedOp",
+            dialect_op_name: "nvvm.mbarrier_init_shared",
+            dialect_operands: &["ptr", "i32"],
+            dialect_results: &[],
+            source_record: "int_nvvm_mbarrier_init_shared",
+            llvm_symbol: "llvm.nvvm.mbarrier.init.shared",
+            llvm_arguments: &["shared_ptr", "i32"],
+            llvm_results: &[],
+            memory: "read_write",
+            ptx_result: "()",
+            selection: "MBARRIER_INIT_SHARED",
+            selection_asm: "mbarrier.init.shared.b64 \t[$addr], $count;",
+            ptx_modifier: "init",
+            ptx_isa_section: "9.7.14.16.12 Parallel Synchronization and Communication Instructions: mbarrier.init",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-init",
+            llvm_nvptx_mechanism: BackendLoweringMechanism::TypedNvvm,
+            lib_nvvm_mechanism: BackendLoweringMechanism::InlinePtx,
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            summary: "Initializes a CTA shared-memory barrier with the expected arrival count.",
+        },
+        MbarrierBasicOperation::Arrive => MbarrierBasicRecipe {
+            id: "mbarrier_arrive",
+            abi_id: "i0098",
+            operation_key: "barrier.mbarrier.arrive.shared.cta",
+            rust_arguments: &["*const u64"],
+            rust_result: "u64",
+            must_use: true,
+            adapter: MbarrierBasicAdapter::ArrivePointerToToken,
+            dialect_op_type: "MbarrierArriveSharedOp",
+            dialect_op_name: "nvvm.mbarrier_arrive_shared",
+            dialect_operands: &["ptr"],
+            dialect_results: &["i64"],
+            source_record: "int_nvvm_mbarrier_arrive_shared",
+            llvm_symbol: "llvm.nvvm.mbarrier.arrive.shared",
+            llvm_arguments: &["shared_ptr"],
+            llvm_results: &["i64"],
+            memory: "read_write",
+            ptx_result: "u64",
+            selection: "MBARRIER_ARRIVE_SHARED",
+            selection_asm: "mbarrier.arrive.shared.b64 \t$state, [$addr];",
+            ptx_modifier: "arrive",
+            ptx_isa_section: "9.7.14.16.16 Parallel Synchronization and Communication Instructions: mbarrier.arrive",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-arrive",
+            llvm_nvptx_mechanism: BackendLoweringMechanism::TypedNvvm,
+            lib_nvvm_mechanism: BackendLoweringMechanism::InlinePtx,
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            summary: "Arrives at a CTA shared-memory barrier and returns its phase token.",
+        },
+        MbarrierBasicOperation::TestWait => MbarrierBasicRecipe {
+            id: "mbarrier_test_wait",
+            abi_id: "i0099",
+            operation_key: "barrier.mbarrier.test_wait.shared.cta",
+            rust_arguments: &["*const u64", "u64"],
+            rust_result: "bool",
+            must_use: true,
+            adapter: MbarrierBasicAdapter::TestWaitPointerTokenToPredicate,
+            dialect_op_type: "MbarrierTestWaitSharedOp",
+            dialect_op_name: "nvvm.mbarrier_test_wait_shared",
+            dialect_operands: &["ptr", "i64"],
+            dialect_results: &["i1"],
+            source_record: "int_nvvm_mbarrier_test_wait_shared",
+            llvm_symbol: "llvm.nvvm.mbarrier.test.wait.shared",
+            llvm_arguments: &["shared_ptr", "i64"],
+            llvm_results: &["i1"],
+            memory: "read_write",
+            ptx_result: "bool",
+            selection: "MBARRIER_TEST_WAIT_SHARED",
+            selection_asm: "mbarrier.test_wait.shared.b64 \t$res, [$addr], $state;",
+            ptx_modifier: "test_wait",
+            ptx_isa_section: "9.7.14.16.19 Parallel Synchronization and Communication Instructions: mbarrier.test_wait / mbarrier.try_wait",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-mbarrier-try-wait",
+            llvm_nvptx_mechanism: BackendLoweringMechanism::InlinePtx,
+            lib_nvvm_mechanism: BackendLoweringMechanism::InlinePtx,
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            summary: "Tests whether the CTA shared-memory barrier phase for a token is complete.",
+        },
+        MbarrierBasicOperation::Inval => MbarrierBasicRecipe {
+            id: "mbarrier_inval",
+            abi_id: "i0100",
+            operation_key: "barrier.mbarrier.inval.shared.cta",
+            rust_arguments: &["*mut u64"],
+            rust_result: "()",
+            must_use: false,
+            adapter: MbarrierBasicAdapter::InvalPointerToVoid,
+            dialect_op_type: "MbarrierInvalSharedOp",
+            dialect_op_name: "nvvm.mbarrier_inval_shared",
+            dialect_operands: &["ptr"],
+            dialect_results: &[],
+            source_record: "int_nvvm_mbarrier_inval_shared",
+            llvm_symbol: "llvm.nvvm.mbarrier.inval.shared",
+            llvm_arguments: &["shared_ptr"],
+            llvm_results: &[],
+            memory: "write",
+            ptx_result: "()",
+            selection: "MBARRIER_INVAL_SHARED",
+            selection_asm: "mbarrier.inval.shared.b64 \t[$addr];",
+            ptx_modifier: "inval",
+            ptx_isa_section: "9.7.14.16.13 Parallel Synchronization and Communication Instructions: mbarrier.inval",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-inval",
+            llvm_nvptx_mechanism: BackendLoweringMechanism::TypedNvvm,
+            lib_nvvm_mechanism: BackendLoweringMechanism::InlinePtx,
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "WriteOnly<arg0>",
+            ],
+            summary: "Invalidates a CTA shared-memory barrier after its users have finished.",
+        },
+    }
+}
+
+pub(in crate::resolve) fn mbarrier_expected_operands(
+    operation: MbarrierBasicOperation,
+) -> Vec<OperandPattern> {
+    match operation {
+        MbarrierBasicOperation::Init => {
+            vec![OperandPattern::Address, OperandPattern::RegisterOrImmediate]
+        }
+        MbarrierBasicOperation::Arrive => {
+            vec![OperandPattern::Register, OperandPattern::Address]
+        }
+        MbarrierBasicOperation::TestWait => vec![
+            OperandPattern::Register,
+            OperandPattern::Address,
+            OperandPattern::Register,
+        ],
+        MbarrierBasicOperation::Inval => vec![OperandPattern::Address],
+    }
+}
+
+pub(in crate::resolve) fn validate_mbarrier_basic_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let mbarrier = policy
+        .mbarrier_basic
+        .as_ref()
+        .with_context(|| format!("{} has no closed basic mbarrier contract", policy.id))?;
+    let recipe = mbarrier_basic_recipe(mbarrier.operation);
+    ensure!(
+        mbarrier.state_space == MbarrierStateSpace::Shared && mbarrier.adapter == recipe.adapter,
+        "{} mbarrier operation, state space, and adapter disagree",
+        policy.id
+    );
+    ensure!(
+        mbarrier.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} cannot claim unrecorded mbarrier runtime validation",
+        policy.id
+    );
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} mbarrier identity does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "barrier"
+            && policy.rust_name == recipe.id
+            && policy
+                .rust_arguments
+                .iter()
+                .map(String::as_str)
+                .eq(recipe.rust_arguments.iter().copied())
+            && policy.rust_result == recipe.rust_result
+            && !policy.safe
+            && policy.must_use == recipe.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::barrier::{}", recipe.id)
+            && policy.compatibility_rust_paths == [format!("cuda_device::barrier::{}", recipe.id)],
+        "{} must preserve its unsafe mbarrier raw and compatibility API",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy
+                .dialect_operands
+                .iter()
+                .map(String::as_str)
+                .eq(recipe.dialect_operands.iter().copied())
+            && policy
+                .dialect_results
+                .iter()
+                .map(String::as_str)
+                .eq(recipe.dialect_results.iter().copied())
+            && policy
+                .llvm_arguments
+                .iter()
+                .map(String::as_str)
+                .eq(recipe.llvm_arguments.iter().copied())
+            && policy
+                .llvm_results
+                .iter()
+                .map(String::as_str)
+                .eq(recipe.llvm_results.iter().copied())
+            && policy.lowering == "generated_mbarrier_basic",
+        "{} is outside the closed mbarrier signature and lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == recipe.memory
+            && policy.convergent
+            && policy.execution_scope == "cta"
+            && policy.minimum_ptx == "7.0"
+            && policy.minimum_sm.as_deref() == Some("sm_80")
+            && policy.ptx_result == recipe.ptx_result
+            && policy.targets == "all",
+        "{} mbarrier effects or target floor disagree with the closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.ptx_isa_section
+            && policy.ptx_isa_url == recipe.ptx_isa_url,
+        "{} mbarrier PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.summary == recipe.summary,
+        "{} mbarrier summary does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration
+            .properties
+            .iter()
+            .map(String::as_str)
+            .eq(recipe.properties.iter().copied()),
+        "{} mbarrier properties disagree with the imported LLVM declaration",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "mbarrier"
+            && policy.expected_ptx.modifiers == [recipe.ptx_modifier, "shared", "b64"]
+            && policy.expected_ptx.operands == mbarrier_expected_operands(mbarrier.operation),
+        "{} expected PTX does not match its mbarrier recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.selections.len() == 1
+            && declaration.selections[0].source_record == recipe.selection
+            && declaration.selections[0].asm == recipe.selection_asm
+            && declaration.selections[0].predicates
+                == [
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70",
+                ]
+            && declaration.selections[0].constraints.is_empty(),
+        "{} imported mbarrier selection changed",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (IntrinsicBackend::LlvmNvptx, recipe.llvm_nvptx_mechanism),
+                    (IntrinsicBackend::LibNvvm, recipe.lib_nvvm_mechanism),
+                ])
+            && policy.backend_lowerings.iter().all(|lowering| {
+                lowering.minimum_ptx.is_none()
+                    && lowering.minimum_sm.is_none()
+                    && !lowering.evidence_profile.trim().is_empty()
+            }),
+        "{} must define exactly the reviewed mbarrier backend routes",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "mbarrier_basic")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/debug_wgmma.rs b/crates/cuda-intrinsics-gen/src/resolve/families/debug_wgmma.rs
new file mode 100644
index 0000000000..2e61a3d18c
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/debug_wgmma.rs
@@ -0,0 +1,708 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, DebugControl, DebugControlAdapter, DebugControlAdmission,
+    DebugControlOperation, ImportedIntrinsic, IntrinsicBackend, IntrinsicSource,
+    OverlayBackendLowering, OverlayIntrinsic, RuntimeValidation, WgmmaControl, WgmmaControlAdapter,
+    WgmmaControlAdmission, WgmmaControlMode, WgmmaControlParticipation,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use crate::resolve::abi_ledger::*;
+use crate::resolve::guards::*;
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct DebugControlRecipe {
+    id: &'static str,
+    operation_key: &'static str,
+    rust_name: &'static str,
+    rust_arguments: &'static [&'static str],
+    rust_result: &'static str,
+    compatibility_path: &'static str,
+    op_type: &'static str,
+    op_name: &'static str,
+    instruction: &'static str,
+    minimum_ptx: &'static str,
+    minimum_sm: Option<&'static str>,
+    section: &'static str,
+    anchor: &'static str,
+    adapter: DebugControlAdapter,
+    summary: &'static str,
+}
+
+pub(in crate::resolve) fn debug_control_recipe(
+    operation: DebugControlOperation,
+) -> DebugControlRecipe {
+    match operation {
+        DebugControlOperation::Trap => DebugControlRecipe {
+            id: "trap",
+            operation_key: "debug.control.trap",
+            rust_name: "trap",
+            rust_arguments: &[],
+            rust_result: "!",
+            compatibility_path: "cuda_device::debug::trap",
+            op_type: "TrapOp",
+            op_name: "nvvm.trap",
+            instruction: "trap",
+            minimum_ptx: "1.0",
+            minimum_sm: None,
+            section: "9.7.20.4 Miscellaneous Instructions: trap",
+            anchor: "miscellaneous-instructions-trap",
+            adapter: DebugControlAdapter::Direct,
+            summary: "Aborts device execution and reports an interrupt to the host.",
+        },
+        DebugControlOperation::Breakpoint => DebugControlRecipe {
+            id: "breakpoint",
+            operation_key: "debug.control.breakpoint",
+            rust_name: "breakpoint",
+            rust_arguments: &[],
+            rust_result: "()",
+            compatibility_path: "cuda_device::debug::breakpoint",
+            op_type: "BreakpointOp",
+            op_name: "nvvm.brkpt",
+            instruction: "brkpt",
+            minimum_ptx: "1.0",
+            minimum_sm: Some("sm_11"),
+            section: "9.7.20.1 Miscellaneous Instructions: brkpt",
+            anchor: "miscellaneous-instructions-brkpt",
+            adapter: DebugControlAdapter::Direct,
+            summary: "Suspends device execution for a debugger breakpoint.",
+        },
+        DebugControlOperation::Pmevent => DebugControlRecipe {
+            id: "pmevent",
+            operation_key: "debug.profiler.event",
+            rust_name: "pmevent",
+            rust_arguments: &["u32"],
+            rust_result: "()",
+            compatibility_path: "cuda_device::debug::__prof_trigger",
+            op_type: "PmEventOp",
+            op_name: "nvvm.pmevent",
+            instruction: "pmevent",
+            minimum_ptx: "1.4",
+            minimum_sm: None,
+            section: "9.7.20.3 Miscellaneous Instructions: pmevent",
+            anchor: "miscellaneous-instructions-pmevent",
+            adapter: DebugControlAdapter::ConstGenericToImmediateU32,
+            summary: "Triggers one compile-time-selected performance monitor event.",
+        },
+    }
+}
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct WgmmaControlRecipe {
+    pub(in crate::resolve) mode: WgmmaControlMode,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) selection_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) compatibility_path: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) suffix: &'static str,
+    pub(in crate::resolve) adapter: WgmmaControlAdapter,
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn wgmma_control_recipe(mode: WgmmaControlMode) -> WgmmaControlRecipe {
+    match mode {
+        WgmmaControlMode::Fence => WgmmaControlRecipe {
+            mode,
+            abi_id: "i0317",
+            id: "wgmma_fence",
+            operation_key: "wgmma.control.fence.sync.aligned",
+            source_record: "int_nvvm_wgmma_fence_sync_aligned",
+            selection_record: "WGMMA_FENCE_SYNC_ALIGNED",
+            llvm_symbol: "llvm.nvvm.wgmma.fence.sync.aligned",
+            compatibility_path: "cuda_device::wgmma::wgmma_fence",
+            dialect_op_type: "WgmmaFenceSyncAlignedOp",
+            dialect_op_name: "nvvm.wgmma_fence_sync_aligned",
+            suffix: "fence.sync.aligned",
+            adapter: WgmmaControlAdapter::NoArguments,
+            summary: "Orders register accesses before later WGMMA operations.",
+        },
+        WgmmaControlMode::CommitGroup => WgmmaControlRecipe {
+            mode,
+            abi_id: "i0318",
+            id: "wgmma_commit_group",
+            operation_key: "wgmma.control.commit_group.sync.aligned",
+            source_record: "int_nvvm_wgmma_commit_group_sync_aligned",
+            selection_record: "WGMMA_COMMIT_GROUP_SYNC_ALIGNED",
+            llvm_symbol: "llvm.nvvm.wgmma.commit_group.sync.aligned",
+            compatibility_path: "cuda_device::wgmma::wgmma_commit_group",
+            dialect_op_type: "WgmmaCommitGroupSyncAlignedOp",
+            dialect_op_name: "nvvm.wgmma_commit_group_sync_aligned",
+            suffix: "commit_group.sync.aligned",
+            adapter: WgmmaControlAdapter::NoArguments,
+            summary: "Commits prior uncommitted WGMMA operations as one group.",
+        },
+        WgmmaControlMode::WaitGroup => WgmmaControlRecipe {
+            mode,
+            abi_id: "i0319",
+            id: "wgmma_wait_group",
+            operation_key: "wgmma.control.wait_group.sync.aligned",
+            source_record: "int_nvvm_wgmma_wait_group_sync_aligned",
+            selection_record: "WGMMA_WAIT_GROUP_SYNC_ALIGNED",
+            llvm_symbol: "llvm.nvvm.wgmma.wait_group.sync.aligned",
+            compatibility_path: "cuda_device::wgmma::__wgmma_wait_group",
+            dialect_op_type: "WgmmaWaitGroupSyncAlignedOp",
+            dialect_op_name: "nvvm.wgmma_wait_group_sync_aligned",
+            suffix: "wait_group.sync.aligned",
+            adapter: WgmmaControlAdapter::ConstGenericU32ToI64Immediate,
+            summary: "Waits until at most the requested number of WGMMA groups remain pending.",
+        },
+    }
+}
+
+pub(in crate::resolve) fn expand_debug_control_admission(
+    admission: &DebugControlAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "debug-control runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact debug-control admission requires both backend evidence profiles"
+    );
+    ensure!(
+        admission.operations
+            == [
+                DebugControlOperation::Trap,
+                DebugControlOperation::Breakpoint,
+                DebugControlOperation::Pmevent,
+            ],
+        "compact debug-control admission must list trap, breakpoint, and pmevent exactly once in canonical order"
+    );
+    ensure!(
+        admission.abi_ids.len() == admission.operations.len(),
+        "pending debug-control admission needs exactly three ABI IDs before aggregation"
+    );
+    let unique_abi_ids = admission.abi_ids.iter().collect::<BTreeSet<_>>();
+    ensure!(
+        unique_abi_ids.len() == admission.abi_ids.len(),
+        "debug-control ABI IDs must be unique"
+    );
+
+    admission
+        .operations
+        .iter()
+        .zip(&admission.abi_ids)
+        .map(|(&operation, abi_id)| {
+            validate_abi_id(abi_id)?;
+            let recipe = debug_control_recipe(operation);
+            let immediate = operation == DebugControlOperation::Pmevent;
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: abi_id.clone(),
+                operation_key: recipe.operation_key.into(),
+                family: "debug_control".into(),
+                source: Some(IntrinsicSource::PtxNative {
+                    instruction: recipe.instruction.into(),
+                }),
+                source_record: None,
+                rust_module: "debug".into(),
+                rust_name: recipe.rust_name.into(),
+                rust_arguments: recipe
+                    .rust_arguments
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                rust_result: recipe.rust_result.into(),
+                safe: true,
+                must_use: false,
+                safe_allowlist_reason: Some(
+                    match operation {
+                        DebugControlOperation::Trap => {
+                            "aborting the kernel has no memory-safety preconditions"
+                        }
+                        DebugControlOperation::Breakpoint => {
+                            "requesting a debugger breakpoint has no memory-safety preconditions"
+                        }
+                        DebugControlOperation::Pmevent => {
+                            "the importer accepts only the documented immediate event range"
+                        }
+                    }
+                    .into(),
+                ),
+                public_rust_path: format!("cuda_intrinsics::debug::{}", recipe.rust_name),
+                compatibility_rust_paths: vec![recipe.compatibility_path.into()],
+                dialect_op_type: recipe.op_type.into(),
+                dialect_op_name: recipe.op_name.into(),
+                dialect_operands: vec![],
+                dialect_results: vec![],
+                llvm_symbol: None,
+                resolved_llvm_symbol: None,
+                llvm_arguments: vec![],
+                llvm_results: vec![],
+                pure: false,
+                memory: "none".into(),
+                convergent: false,
+                execution_scope: "thread".into(),
+                minimum_ptx: recipe.minimum_ptx.into(),
+                minimum_sm: recipe.minimum_sm.map(Into::into),
+                ptx_result: "()".into(),
+                targets: "all".into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section: recipe.section.into(),
+                ptx_isa_url: format!(
+                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#{}",
+                    recipe.anchor
+                ),
+                lowering: "generated_debug_control".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.llvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some("3.2".into()),
+                        minimum_sm: Some("sm_20".into()),
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                        targets: None,
+                        // PTX floor is the inline-PTX mechanism floor, same as
+                        // the LlvmNvptx entry above; the hardware floor stays at
+                        // the probed sm_75 (backend-codegen evidence must sit
+                        // exactly at the hardware floor, and CUDA 13 cannot
+                        // probe older targets). Writing the probe PTX version
+                        // (9.3) here made every panic path unbuildable on the
+                        // NVVM-IR route: the floor exceeded the newest PTX
+                        // version cuda-oxide can request.
+                        minimum_ptx: Some("3.2".into()),
+                        minimum_sm: Some("sm_75".into()),
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: Some(DebugControl {
+                    operation,
+                    adapter: recipe.adapter,
+                    runtime_validation: admission.runtime_validation,
+                }),
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: recipe.instruction.into(),
+                    modifiers: vec![],
+                    operands: if immediate {
+                        vec![OperandPattern::Immediate]
+                    } else {
+                        vec![]
+                    },
+                },
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn validate_debug_control_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+) -> Result<()> {
+    let debug = policy
+        .debug_control
+        .as_ref()
+        .with_context(|| format!("{} has no closed debug-control contract", policy.id))?;
+    let recipe = debug_control_recipe(debug.operation);
+    let immediate = debug.operation == DebugControlOperation::Pmevent;
+    ensure!(
+        debug.adapter == recipe.adapter
+            && debug.runtime_validation == RuntimeValidation::Unexecuted
+            && policy.id == recipe.id
+            && policy.operation_key == recipe.operation_key
+            && source
+                == &IntrinsicSource::PtxNative {
+                    instruction: recipe.instruction.into(),
+                }
+            && policy.source_record.is_none()
+            && policy.llvm_symbol.is_none()
+            && policy.resolved_llvm_symbol.is_none()
+            && policy.llvm_arguments.is_empty()
+            && policy.llvm_results.is_empty(),
+        "{} identity must remain PTX-native and match its closed debug-control recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "debug"
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == recipe.rust_arguments
+            && policy.rust_result == recipe.rust_result
+            && policy.safe
+            && !policy.must_use
+            && policy.public_rust_path == format!("cuda_intrinsics::debug::{}", recipe.rust_name)
+            && policy.compatibility_rust_paths == [recipe.compatibility_path],
+        "{} Rust API or compatibility adapter changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.op_type
+            && policy.dialect_op_name == recipe.op_name
+            && policy.dialect_operands.is_empty()
+            && policy.dialect_results.is_empty()
+            && policy.lowering == "generated_debug_control",
+        "{} dialect carrier or lowering changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread",
+        "{} debug-control effects changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == recipe.minimum_sm
+            && policy.targets == "all"
+            && policy.ptx_result == "()"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.section
+            && policy.ptx_isa_url
+                == format!(
+                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#{}",
+                    recipe.anchor
+                ),
+        "{} native target floor or PTX provenance changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == recipe.instruction
+            && policy.expected_ptx.modifiers.is_empty()
+            && policy.expected_ptx.operands
+                == if immediate {
+                    vec![OperandPattern::Immediate]
+                } else {
+                    vec![]
+                },
+        "{} expected PTX changed",
+        policy.id
+    );
+    ensure_exact_inline_ptx_backends(
+        policy,
+        [
+            (IntrinsicBackend::LlvmNvptx, "3.2", Some("sm_20")),
+            (IntrinsicBackend::LibNvvm, "3.2", Some("sm_75")),
+        ],
+        "debug-control",
+    )?;
+    ensure_no_other_family_contract(policy, "debug-control")?;
+    Ok(())
+}
+
+pub(in crate::resolve) fn expand_wgmma_control_admission(
+    admission: &WgmmaControlAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "WGMMA-control runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact WGMMA-control admission requires both backend evidence profiles"
+    );
+    let expected_modes = [
+        WgmmaControlMode::Fence,
+        WgmmaControlMode::CommitGroup,
+        WgmmaControlMode::WaitGroup,
+    ];
+    let actual_modes = admission
+        .variants
+        .iter()
+        .map(|variant| variant.mode)
+        .collect::<Vec<_>>();
+    ensure!(
+        actual_modes == expected_modes,
+        "compact WGMMA-control admission must contain each reviewed mode once in canonical order"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = wgmma_control_recipe(variant.mode);
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must keep reserved ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            let wait = recipe.mode == WgmmaControlMode::WaitGroup;
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: variant.abi_id.clone(),
+                operation_key: recipe.operation_key.into(),
+                family: "wgmma_control".into(),
+                source: None,
+                source_record: Some(recipe.source_record.into()),
+                rust_module: "wgmma".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments: if wait { vec!["u64".into()] } else { vec![] },
+                rust_result: "()".into(),
+                safe: false,
+                must_use: false,
+                safe_allowlist_reason: None,
+                public_rust_path: format!("cuda_intrinsics::wgmma::{}", recipe.id),
+                compatibility_rust_paths: vec![recipe.compatibility_path.into()],
+                dialect_op_type: recipe.dialect_op_type.into(),
+                dialect_op_name: recipe.dialect_op_name.into(),
+                dialect_operands: if wait { vec!["i64".into()] } else { vec![] },
+                dialect_results: vec![],
+                llvm_symbol: Some(recipe.llvm_symbol.into()),
+                resolved_llvm_symbol: None,
+                llvm_arguments: if wait { vec!["i64".into()] } else { vec![] },
+                llvm_results: vec![],
+                pure: false,
+                memory: "read_write".into(),
+                convergent: true,
+                execution_scope: "warpgroup".into(),
+                minimum_ptx: "8.0".into(),
+                minimum_sm: None,
+                ptx_result: "()".into(),
+                targets: "sm_90a".into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section:
+                    "Asynchronous Warpgroup Level Matrix Instructions: WGMMA control".into(),
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#asynchronous-warpgroup-level-matrix-instructions".into(),
+                lowering: "generated_wgmma_control".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: BackendLoweringMechanism::TypedNvvm,
+                        evidence_profile: admission.llvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some("8.0".into()),
+                        minimum_sm: None,
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some("8.0".into()),
+                        minimum_sm: None,
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: Some(WgmmaControl {
+                    mode: recipe.mode,
+                    adapter: recipe.adapter,
+                    participation: WgmmaControlParticipation::WarpgroupAllThreadsSameInstruction,
+                }),
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: "wgmma".into(),
+                    modifiers: recipe.suffix.split('.').map(str::to_owned).collect(),
+                    operands: if wait {
+                        vec![OperandPattern::Immediate]
+                    } else {
+                        vec![]
+                    },
+                },
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn validate_wgmma_control_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let control = policy
+        .wgmma_control
+        .as_ref()
+        .with_context(|| format!("{} has no closed WGMMA-control contract", policy.id))?;
+    let recipe = wgmma_control_recipe(control.mode);
+    let wait = recipe.mode == WgmmaControlMode::WaitGroup;
+    ensure!(
+        control.adapter == recipe.adapter
+            && control.participation
+                == WgmmaControlParticipation::WarpgroupAllThreadsSameInstruction
+            && policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} identity or semantics do not match its closed WGMMA-control recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "wgmma"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments
+                == if wait {
+                    vec!["u64"]
+                } else {
+                    Vec::<&str>::new()
+                }
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.public_rust_path == format!("cuda_intrinsics::wgmma::{}", recipe.id)
+            && policy.compatibility_rust_paths == [recipe.compatibility_path],
+        "{} Rust API does not match its closed WGMMA-control recipe",
+        policy.id
+    );
+    let expected_arguments = if wait {
+        vec!["i64"]
+    } else {
+        Vec::<&str>::new()
+    };
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == expected_arguments
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == expected_arguments
+            && policy.llvm_results.is_empty()
+            && policy.lowering == "generated_wgmma_control",
+        "{} carrier or lowering does not match its closed WGMMA-control recipe",
+        policy.id
+    );
+    let expected_properties = if wait {
+        vec!["ImmArg<arg0>", "IntrConvergent"]
+    } else {
+        vec!["IntrConvergent"]
+    };
+    ensure!(
+        declaration.classes == ["SDPatternOperator", "Intrinsic"]
+            && declaration.properties == expected_properties
+            && !policy.pure
+            && policy.memory == "read_write"
+            && policy.convergent
+            && policy.execution_scope == "warpgroup",
+        "{} effects disagree with the imported WGMMA-control declaration",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == "8.0"
+            && policy.minimum_sm.is_none()
+            && policy.targets == "sm_90a"
+            && policy.ptx_result == "()"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#asynchronous-warpgroup-level-matrix-instructions",
+        "{} target floor or PTX provenance changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "wgmma"
+            && policy.expected_ptx.modifiers == recipe.suffix.split('.').collect::<Vec<_>>()
+            && policy.expected_ptx.operands
+                == if wait {
+                    vec![OperandPattern::Immediate]
+                } else {
+                    vec![]
+                },
+        "{} expected PTX does not match its exact WGMMA-control spelling",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ])
+            && policy.backend_lowerings.iter().all(|lowering| {
+                lowering.minimum_ptx.as_deref() == Some("8.0")
+                    && lowering.minimum_sm.is_none()
+                    && !lowering.evidence_profile.trim().is_empty()
+            }),
+        "{} must define exactly the reviewed WGMMA-control backend routes",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "WGMMA control")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/execution_control.rs b/crates/cuda-intrinsics-gen/src/resolve/families/execution_control.rs
new file mode 100644
index 0000000000..70c07709cc
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/execution_control.rs
@@ -0,0 +1,633 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ExecutionControlOperation, ImportedIntrinsic, IntrinsicBackend,
+    OverlayIntrinsic,
+};
+use crate::ptx::OperandPattern;
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use super::*;
+use crate::resolve::guards::*;
+
+pub(in crate::resolve) const EXECUTION_CONTROL_OPERATIONS: [ExecutionControlOperation; 8] = [
+    ExecutionControlOperation::BarrierCtaSync,
+    ExecutionControlOperation::BarrierCtaSyncAligned,
+    ExecutionControlOperation::BarrierCtaArrive,
+    ExecutionControlOperation::BarrierCtaArriveAligned,
+    ExecutionControlOperation::GridDependencyLaunchDependents,
+    ExecutionControlOperation::GridDependencyWait,
+    ExecutionControlOperation::SetMaxNRegInc,
+    ExecutionControlOperation::SetMaxNRegDec,
+];
+
+pub(in crate::resolve) fn validate_execution_control_family_completeness(
+    intrinsics: &[OverlayIntrinsic],
+) -> Result<()> {
+    let has_execution_control_family = intrinsics.iter().any(|policy| {
+        matches!(
+            policy.family.as_str(),
+            "counted_barrier" | "grid_dependency" | "register_control"
+        )
+    });
+    if !has_execution_control_family {
+        return Ok(());
+    }
+    let actual = intrinsics
+        .iter()
+        .filter_map(|policy| ExecutionControlOperation::from_catalog_id(&policy.id))
+        .collect::<BTreeSet<_>>();
+    let expected = EXECUTION_CONTROL_OPERATIONS
+        .into_iter()
+        .collect::<BTreeSet<_>>();
+    ensure!(
+        actual == expected,
+        "execution-control overlay must admit all four counted barriers, both grid-dependency controls, and both setmaxnreg operations"
+    );
+    for family in ["counted_barrier", "grid_dependency", "register_control"] {
+        ensure!(
+            intrinsics
+                .iter()
+                .filter(|policy| policy.family == family)
+                .all(|policy| {
+                    ExecutionControlOperation::from_catalog_id(&policy.id)
+                        .is_some_and(|operation| operation.family() == family)
+                }),
+            "{family} overlay contains an operation outside its closed instruction family"
+        );
+    }
+    Ok(())
+}
+
+#[derive(Clone)]
+pub(in crate::resolve) struct ExecutionControlRecipe {
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) rust_module: &'static str,
+    pub(in crate::resolve) rust_arguments: &'static [&'static str],
+    pub(in crate::resolve) compatibility_path: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) dialect_operands: &'static [&'static str],
+    pub(in crate::resolve) llvm_arguments: &'static [&'static str],
+    pub(in crate::resolve) imported_classes: &'static [&'static str],
+    pub(in crate::resolve) imported_properties: &'static [&'static str],
+    pub(in crate::resolve) memory: &'static str,
+    pub(in crate::resolve) convergent: bool,
+    pub(in crate::resolve) execution_scope: &'static str,
+    pub(in crate::resolve) minimum_ptx: &'static str,
+    pub(in crate::resolve) minimum_sm: Option<&'static str>,
+    pub(in crate::resolve) targets: &'static str,
+    pub(in crate::resolve) ptx_isa_section: &'static str,
+    pub(in crate::resolve) ptx_isa_url: &'static str,
+    pub(in crate::resolve) mnemonic: &'static str,
+    pub(in crate::resolve) modifiers: &'static [&'static str],
+    pub(in crate::resolve) operands: &'static [OperandPattern],
+    pub(in crate::resolve) selection_records: &'static [&'static str],
+    pub(in crate::resolve) selection_asm: &'static str,
+    pub(in crate::resolve) selection_predicates: &'static [&'static str],
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn execution_control_recipe(
+    operation: ExecutionControlOperation,
+) -> ExecutionControlRecipe {
+    use ExecutionControlOperation::*;
+
+    const EMPTY: &[&str] = &[];
+    const I32: &[&str] = &["i32"];
+    const I32_I32: &[&str] = &["i32", "i32"];
+    const U32: &[&str] = &["u32"];
+    const U32_U32: &[&str] = &["u32", "u32"];
+    const BASE_CLASSES: &[&str] = &["SDPatternOperator", "Intrinsic"];
+    const DEFAULT_CLASSES: &[&str] = &["SDPatternOperator", "Intrinsic", "DefaultAttrsIntrinsic"];
+    const BARRIER_PROPERTIES: &[&str] = &["IntrConvergent", "IntrNoCallback"];
+    const GRID_PROPERTIES: &[&str] = &["IntrHasSideEffects", "IntrNoMem"];
+    const SETMAX_PROPERTIES: &[&str] = &[
+        "ImmArg<arg0>",
+        "IntrConvergent",
+        "IntrHasSideEffects",
+        "IntrNoMem",
+        "Range<arg0,24,257>",
+    ];
+    const TWO_REGISTER_OR_IMMEDIATE: &[OperandPattern] = &[
+        OperandPattern::RegisterOrImmediate,
+        OperandPattern::RegisterOrImmediate,
+    ];
+    const ONE_IMMEDIATE: &[OperandPattern] = &[OperandPattern::Immediate];
+    const NO_OPERANDS: &[OperandPattern] = &[];
+    const BARRIER_SYNC_SELECTIONS: &[&str] = &[
+        "BARRIER_CTA_SYNC_ii",
+        "BARRIER_CTA_SYNC_ir",
+        "BARRIER_CTA_SYNC_ri",
+        "BARRIER_CTA_SYNC_rr",
+    ];
+    const BAR_SYNC_SELECTIONS: &[&str] = &[
+        "BARRIER_CTA_SYNC_ALIGNED_ii",
+        "BARRIER_CTA_SYNC_ALIGNED_ir",
+        "BARRIER_CTA_SYNC_ALIGNED_ri",
+        "BARRIER_CTA_SYNC_ALIGNED_rr",
+    ];
+    const BARRIER_ARRIVE_SELECTIONS: &[&str] = &[
+        "BARRIER_CTA_ARRIVE_ii",
+        "BARRIER_CTA_ARRIVE_ir",
+        "BARRIER_CTA_ARRIVE_ri",
+        "BARRIER_CTA_ARRIVE_rr",
+    ];
+    const BAR_ARRIVE_SELECTIONS: &[&str] = &[
+        "BARRIER_CTA_ARRIVE_ALIGNED_ii",
+        "BARRIER_CTA_ARRIVE_ALIGNED_ir",
+        "BARRIER_CTA_ARRIVE_ALIGNED_ri",
+        "BARRIER_CTA_ARRIVE_ALIGNED_rr",
+    ];
+    const PTX_60: &[&str] = &["Subtarget->getPTXVersion() >= 60"];
+    const GRID_PREDICATES: &[&str] = &[
+        "Subtarget->getSmVersion() >= 90",
+        "Subtarget->getPTXVersion() >= 78",
+    ];
+    const SETMAX_PREDICATES: &[&str] = &["Subtarget->hasSetMaxNRegSupport()"];
+    const SYNC_MODIFIERS: &[&str] = &["sync"];
+    const ARRIVE_MODIFIERS: &[&str] = &["arrive"];
+    const LAUNCH_DEPENDENTS_MODIFIERS: &[&str] = &["launch_dependents"];
+    const WAIT_MODIFIERS: &[&str] = &["wait"];
+    const SETMAX_INC_MODIFIERS: &[&str] = &["inc", "sync", "aligned", "u32"];
+    const SETMAX_DEC_MODIFIERS: &[&str] = &["dec", "sync", "aligned", "u32"];
+    const GRID_LAUNCH_SELECTIONS: &[&str] = &["GRIDDEPCONTROL_LAUNCH_DEPENDENTS"];
+    const GRID_WAIT_SELECTIONS: &[&str] = &["GRIDDEPCONTROL_WAIT"];
+    const SETMAX_INC_SELECTIONS: &[&str] = &["anonymous_22212"];
+    const SETMAX_DEC_SELECTIONS: &[&str] = &["anonymous_22214"];
+    const BAR_SECTION: &str =
+        "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier";
+    const BAR_URL: &str = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier";
+    const GRID_SECTION: &str =
+        "9.7.15.1 Parallel Synchronization and Communication Instructions: griddepcontrol";
+    const GRID_URL: &str = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-griddepcontrol";
+    const SETMAX_SECTION: &str = "9.7.16.5 Miscellaneous Instructions: setmaxnreg";
+    const SETMAX_URL: &str = "https://docs.nvidia.com/cuda/parallel-thread-execution/#miscellaneous-instructions-setmaxnreg";
+
+    let (
+        abi_id,
+        id,
+        operation_key,
+        source_record,
+        llvm_symbol,
+        rust_module,
+        rust_arguments,
+        compatibility_path,
+        dialect_op_type,
+        dialect_op_name,
+        dialect_operands,
+        llvm_arguments,
+        imported_classes,
+        imported_properties,
+        memory,
+        convergent,
+        execution_scope,
+        minimum_ptx,
+        minimum_sm,
+        targets,
+        ptx_isa_section,
+        ptx_isa_url,
+        mnemonic,
+        modifiers,
+        operands,
+        selection_records,
+        selection_asm,
+        selection_predicates,
+        summary,
+    ) = match operation {
+        BarrierCtaSync => (
+            "i0883",
+            "barrier_cta_sync",
+            "synchronization.cta.barrier.count",
+            "int_nvvm_barrier_cta_sync_count",
+            "llvm.nvvm.barrier.cta.sync.count",
+            "barrier",
+            U32_U32,
+            "cuda_device::barrier::barrier_cta_sync",
+            "BarrierCtaSyncCountOp",
+            "nvvm.barrier_cta_sync_count",
+            I32_I32,
+            I32_I32,
+            BASE_CLASSES,
+            BARRIER_PROPERTIES,
+            "read_write",
+            true,
+            "cta",
+            "6.0",
+            Some("sm_30"),
+            "all",
+            BAR_SECTION,
+            BAR_URL,
+            "barrier",
+            SYNC_MODIFIERS,
+            TWO_REGISTER_OR_IMMEDIATE,
+            BARRIER_SYNC_SELECTIONS,
+            "barrier.sync \t$i, $j;",
+            PTX_60,
+            "Synchronizes the requested number of CTA threads at a numbered barrier.",
+        ),
+        BarrierCtaSyncAligned => (
+            "i0884",
+            "barrier_cta_sync_aligned",
+            "synchronization.cta.bar.aligned.count",
+            "int_nvvm_barrier_cta_sync_aligned_count",
+            "llvm.nvvm.barrier.cta.sync.aligned.count",
+            "barrier",
+            U32_U32,
+            "cuda_device::barrier::barrier_cta_sync_aligned",
+            "BarrierCtaSyncAlignedCountOp",
+            "nvvm.barrier_cta_sync_aligned_count",
+            I32_I32,
+            I32_I32,
+            BASE_CLASSES,
+            BARRIER_PROPERTIES,
+            "read_write",
+            true,
+            "cta",
+            "1.0",
+            None,
+            "all",
+            BAR_SECTION,
+            BAR_URL,
+            "bar",
+            SYNC_MODIFIERS,
+            TWO_REGISTER_OR_IMMEDIATE,
+            BAR_SYNC_SELECTIONS,
+            "bar.sync \t$i, $j;",
+            EMPTY,
+            "Synchronizes the requested number of CTA threads at an aligned numbered barrier.",
+        ),
+        BarrierCtaArrive => (
+            "i0885",
+            "barrier_cta_arrive",
+            "synchronization.cta.barrier.arrive.count",
+            "int_nvvm_barrier_cta_arrive_count",
+            "llvm.nvvm.barrier.cta.arrive.count",
+            "barrier",
+            U32_U32,
+            "cuda_device::barrier::barrier_cta_arrive",
+            "BarrierCtaArriveCountOp",
+            "nvvm.barrier_cta_arrive_count",
+            I32_I32,
+            I32_I32,
+            BASE_CLASSES,
+            BARRIER_PROPERTIES,
+            "read_write",
+            true,
+            "cta",
+            "6.0",
+            Some("sm_30"),
+            "all",
+            BAR_SECTION,
+            BAR_URL,
+            "barrier",
+            ARRIVE_MODIFIERS,
+            TWO_REGISTER_OR_IMMEDIATE,
+            BARRIER_ARRIVE_SELECTIONS,
+            "barrier.arrive \t$i, $j;",
+            PTX_60,
+            "Signals arrival of the requested number of CTA threads at a numbered barrier without waiting.",
+        ),
+        BarrierCtaArriveAligned => (
+            "i0886",
+            "barrier_cta_arrive_aligned",
+            "synchronization.cta.bar.arrive.aligned.count",
+            "int_nvvm_barrier_cta_arrive_aligned_count",
+            "llvm.nvvm.barrier.cta.arrive.aligned.count",
+            "barrier",
+            U32_U32,
+            "cuda_device::barrier::barrier_cta_arrive_aligned",
+            "BarrierCtaArriveAlignedCountOp",
+            "nvvm.barrier_cta_arrive_aligned_count",
+            I32_I32,
+            I32_I32,
+            BASE_CLASSES,
+            BARRIER_PROPERTIES,
+            "read_write",
+            true,
+            "cta",
+            "1.0",
+            None,
+            "all",
+            BAR_SECTION,
+            BAR_URL,
+            "bar",
+            ARRIVE_MODIFIERS,
+            TWO_REGISTER_OR_IMMEDIATE,
+            BAR_ARRIVE_SELECTIONS,
+            "bar.arrive \t$i, $j;",
+            EMPTY,
+            "Signals arrival of the requested number of CTA threads at an aligned numbered barrier without waiting.",
+        ),
+        GridDependencyLaunchDependents => (
+            "i0913",
+            "grid_dependency_launch_dependents",
+            "synchronization.grid.dependency.launch_dependents",
+            "int_nvvm_griddepcontrol_launch_dependents",
+            "llvm.nvvm.griddepcontrol.launch.dependents",
+            "grid",
+            EMPTY,
+            "cuda_device::grid::dependency::trigger_dependents",
+            "GridDependencyLaunchDependentsOp",
+            "nvvm.grid_dependency_launch_dependents",
+            EMPTY,
+            EMPTY,
+            BASE_CLASSES,
+            GRID_PROPERTIES,
+            "none",
+            false,
+            "grid",
+            "7.8",
+            Some("sm_90"),
+            "all",
+            GRID_SECTION,
+            GRID_URL,
+            "griddepcontrol",
+            LAUNCH_DEPENDENTS_MODIFIERS,
+            NO_OPERANDS,
+            GRID_LAUNCH_SELECTIONS,
+            "griddepcontrol.launch_dependents;",
+            GRID_PREDICATES,
+            "Makes dependent grids eligible to launch before the current grid completes.",
+        ),
+        GridDependencyWait => (
+            "i0914",
+            "grid_dependency_wait",
+            "synchronization.grid.dependency.wait",
+            "int_nvvm_griddepcontrol_wait",
+            "llvm.nvvm.griddepcontrol.wait",
+            "grid",
+            EMPTY,
+            "cuda_device::grid::dependency::wait",
+            "GridDependencyWaitOp",
+            "nvvm.grid_dependency_wait",
+            EMPTY,
+            EMPTY,
+            BASE_CLASSES,
+            GRID_PROPERTIES,
+            "none",
+            false,
+            "grid",
+            "7.8",
+            Some("sm_90"),
+            "all",
+            GRID_SECTION,
+            GRID_URL,
+            "griddepcontrol",
+            WAIT_MODIFIERS,
+            NO_OPERANDS,
+            GRID_WAIT_SELECTIONS,
+            "griddepcontrol.wait;",
+            GRID_PREDICATES,
+            "Waits until all prerequisite grids have completed.",
+        ),
+        SetMaxNRegInc => (
+            "i0915",
+            "setmaxnreg_inc",
+            "register_control.warpgroup.setmaxnreg.increment",
+            "int_nvvm_setmaxnreg_inc_sync_aligned_u32",
+            "llvm.nvvm.setmaxnreg.inc.sync.aligned.u32",
+            "thread",
+            U32,
+            "cuda_device::thread::__setmaxnreg_inc",
+            "SetMaxNRegIncOp",
+            "nvvm.setmaxnreg_inc",
+            EMPTY,
+            I32,
+            DEFAULT_CLASSES,
+            SETMAX_PROPERTIES,
+            "none",
+            true,
+            "warpgroup",
+            "8.0",
+            None,
+            TENSOR_MAP_REPLACE_TARGETS,
+            SETMAX_SECTION,
+            SETMAX_URL,
+            "setmaxnreg",
+            SETMAX_INC_MODIFIERS,
+            ONE_IMMEDIATE,
+            SETMAX_INC_SELECTIONS,
+            "setmaxnreg.inc.sync.aligned.u32 \t$reg_count;",
+            SETMAX_PREDICATES,
+            "Increases the executing warpgroup's maximum register allocation to the immediate count.",
+        ),
+        SetMaxNRegDec => (
+            "i0916",
+            "setmaxnreg_dec",
+            "register_control.warpgroup.setmaxnreg.decrement",
+            "int_nvvm_setmaxnreg_dec_sync_aligned_u32",
+            "llvm.nvvm.setmaxnreg.dec.sync.aligned.u32",
+            "thread",
+            U32,
+            "cuda_device::thread::__setmaxnreg_dec",
+            "SetMaxNRegDecOp",
+            "nvvm.setmaxnreg_dec",
+            EMPTY,
+            I32,
+            DEFAULT_CLASSES,
+            SETMAX_PROPERTIES,
+            "none",
+            true,
+            "warpgroup",
+            "8.0",
+            None,
+            TENSOR_MAP_REPLACE_TARGETS,
+            SETMAX_SECTION,
+            SETMAX_URL,
+            "setmaxnreg",
+            SETMAX_DEC_MODIFIERS,
+            ONE_IMMEDIATE,
+            SETMAX_DEC_SELECTIONS,
+            "setmaxnreg.dec.sync.aligned.u32 \t$reg_count;",
+            SETMAX_PREDICATES,
+            "Decreases the executing warpgroup's maximum register allocation to the immediate count.",
+        ),
+    };
+
+    ExecutionControlRecipe {
+        abi_id,
+        id,
+        operation_key,
+        source_record,
+        llvm_symbol,
+        rust_module,
+        rust_arguments,
+        compatibility_path,
+        dialect_op_type,
+        dialect_op_name,
+        dialect_operands,
+        llvm_arguments,
+        imported_classes,
+        imported_properties,
+        memory,
+        convergent,
+        execution_scope,
+        minimum_ptx,
+        minimum_sm,
+        targets,
+        ptx_isa_section,
+        ptx_isa_url,
+        mnemonic,
+        modifiers,
+        operands,
+        selection_records,
+        selection_asm,
+        selection_predicates,
+        summary,
+    }
+}
+
+pub(in crate::resolve) fn execution_control_backend_floor(
+    operation: ExecutionControlOperation,
+    backend: IntrinsicBackend,
+) -> (&'static str, Option<&'static str>) {
+    use ExecutionControlOperation::*;
+
+    match (operation, backend) {
+        (BarrierCtaSync | BarrierCtaArrive, IntrinsicBackend::LlvmNvptx) => ("6.0", Some("sm_30")),
+        (BarrierCtaSync | BarrierCtaArrive, IntrinsicBackend::LibNvvm) => ("6.0", Some("sm_75")),
+        (BarrierCtaSyncAligned | BarrierCtaArriveAligned, IntrinsicBackend::LlvmNvptx) => {
+            ("3.2", Some("sm_20"))
+        }
+        (BarrierCtaSyncAligned | BarrierCtaArriveAligned, IntrinsicBackend::LibNvvm) => {
+            ("1.0", Some("sm_75"))
+        }
+        _ => {
+            let recipe = execution_control_recipe(operation);
+            (recipe.minimum_ptx, recipe.minimum_sm)
+        }
+    }
+}
+
+pub(in crate::resolve) fn validate_execution_control_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let operation = ExecutionControlOperation::from_catalog_id(&policy.id)
+        .with_context(|| format!("{} is not a closed execution-control operation", policy.id))?;
+    let recipe = execution_control_recipe(operation);
+    ensure!(
+        policy.family == operation.family()
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.summary == recipe.summary
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none()
+            && declaration.source_record == recipe.source_record
+            && declaration.llvm_name == recipe.llvm_symbol,
+        "{} execution-control identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == recipe.rust_module
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == recipe.rust_arguments
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path
+                == format!("cuda_intrinsics::{}::{}", recipe.rust_module, recipe.id)
+            && policy.compatibility_rust_paths == [recipe.compatibility_path],
+        "{} execution-control Rust API changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == recipe.dialect_operands
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == recipe.llvm_arguments
+            && policy.llvm_results.is_empty()
+            && declaration.arguments == recipe.llvm_arguments
+            && declaration.results.is_empty()
+            && policy.lowering == "generated_execution_control",
+        "{} execution-control carrier or LLVM adapter changed",
+        policy.id
+    );
+    ensure!(
+        declaration.classes == recipe.imported_classes
+            && declaration.properties == recipe.imported_properties,
+        "{} imported execution-control declaration changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == recipe.memory
+            && policy.convergent == recipe.convergent
+            && policy.execution_scope == recipe.execution_scope,
+        "{} execution-control semantics changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == recipe.minimum_sm
+            && policy.targets == recipe.targets
+            && policy.ptx_result == "()"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.ptx_isa_section
+            && policy.ptx_isa_url == recipe.ptx_isa_url
+            && policy.expected_ptx.mnemonic == recipe.mnemonic
+            && policy.expected_ptx.modifiers == recipe.modifiers
+            && policy.expected_ptx.operands == recipe.operands,
+        "{} execution-control target or PTX contract changed",
+        policy.id
+    );
+    let valid_route = |backend, mechanism| {
+        let (minimum_ptx, minimum_sm) = execution_control_backend_floor(operation, backend);
+        policy.backend_lowerings.iter().any(|route| {
+            route.backend == backend
+                && route.mechanism == mechanism
+                && route.minimum_ptx.as_deref() == Some(minimum_ptx)
+                && route.minimum_sm.as_deref() == minimum_sm
+                && !route.evidence_profile.trim().is_empty()
+        })
+    };
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && valid_route(
+                IntrinsicBackend::LlvmNvptx,
+                BackendLoweringMechanism::TypedNvvm,
+            )
+            && valid_route(
+                IntrinsicBackend::LibNvvm,
+                BackendLoweringMechanism::InlinePtx,
+            ),
+        "{} execution-control backend route changed",
+        policy.id
+    );
+    let expected_selections = recipe
+        .selection_records
+        .iter()
+        .copied()
+        .collect::<BTreeSet<_>>();
+    let actual_selections = declaration
+        .selections
+        .iter()
+        .map(|selection| selection.source_record.as_str())
+        .collect::<BTreeSet<_>>();
+    ensure!(
+        declaration.selections.len() == recipe.selection_records.len()
+            && actual_selections == expected_selections
+            && declaration.selections.iter().all(|selection| {
+                selection.asm == recipe.selection_asm
+                    && selection.predicates == recipe.selection_predicates
+                    && selection.constraints.is_empty()
+            }),
+        "{} imported execution-control selection family changed",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "execution-control")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/matrix_move.rs b/crates/cuda-intrinsics-gen/src/resolve/families/matrix_move.rs
new file mode 100644
index 0000000000..4eef5aec67
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/matrix_move.rs
@@ -0,0 +1,776 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogTargetRequirement, ImportedAddressSpace, ImportedIntrinsic,
+    IntrinsicBackend, IntrinsicSource, LdmatrixAdapter, LdmatrixAddressContract, LdmatrixElement,
+    LdmatrixLayout, LdmatrixMemoryOrder, LdmatrixMultiplicity, LdmatrixParticipation,
+    LdmatrixShape, LdmatrixStateSpace, MovmatrixAdapter, MovmatrixParticipation,
+    OverlayBackendLowering, OverlayIntrinsic, RuntimeValidation, StmatrixAdmission, StmatrixLayout,
+    StmatrixMultiplicity,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use crate::resolve::guards::*;
+use crate::resolve::targets::*;
+
+pub(in crate::resolve) const BLACKWELL_LDMATRIX_LLVM_TARGETS: &str =
+    "sm_100a|sm_100f|sm_103a|sm_103f|sm_110a|sm_110f|sm_120a|sm_120f|sm_121a|sm_121f";
+pub(in crate::resolve) const BLACKWELL_LDMATRIX_LIBNVVM_TARGETS: &str =
+    BLACKWELL_LDMATRIX_LLVM_TARGETS;
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct StmatrixRecipe {
+    multiplicity: StmatrixMultiplicity,
+    layout: StmatrixLayout,
+    abi_id: &'static str,
+    id: &'static str,
+    operation_key: &'static str,
+    source_record: &'static str,
+    llvm_symbol: &'static str,
+    compatibility_name: &'static str,
+    dialect_op_type: &'static str,
+    dialect_op_name: &'static str,
+    summary: &'static str,
+}
+
+pub(in crate::resolve) fn stmatrix_recipe(
+    multiplicity: StmatrixMultiplicity,
+    layout: StmatrixLayout,
+) -> StmatrixRecipe {
+    match (multiplicity, layout) {
+        (StmatrixMultiplicity::X2, StmatrixLayout::Normal) => StmatrixRecipe {
+            multiplicity,
+            layout,
+            abi_id: "i0301",
+            id: "stmatrix_m8n8_x2_b16",
+            operation_key: "matrix.stmatrix.m8n8.x2.normal.b16.shared",
+            source_record: "int_nvvm_stmatrix_sync_aligned_m8n8_x2_b16",
+            llvm_symbol: "llvm.nvvm.stmatrix.sync.aligned.m8n8.x2.b16",
+            compatibility_name: "stmatrix_m8n8_x2",
+            dialect_op_type: "StmatrixM8n8X2Op",
+            dialect_op_name: "nvvm.stmatrix_m8n8_x2",
+            summary: "Stores two 8×8 b16 matrix fragments cooperatively to shared memory.",
+        },
+        (StmatrixMultiplicity::X2, StmatrixLayout::Transposed) => StmatrixRecipe {
+            multiplicity,
+            layout,
+            abi_id: "i0302",
+            id: "stmatrix_m8n8_x2_trans_b16",
+            operation_key: "matrix.stmatrix.m8n8.x2.transposed.b16.shared",
+            source_record: "int_nvvm_stmatrix_sync_aligned_m8n8_x2_trans_b16",
+            llvm_symbol: "llvm.nvvm.stmatrix.sync.aligned.m8n8.x2.trans.b16",
+            compatibility_name: "stmatrix_m8n8_x2_trans",
+            dialect_op_type: "StmatrixM8n8X2TransOp",
+            dialect_op_name: "nvvm.stmatrix_m8n8_x2_trans",
+            summary: "Stores two transposed 8×8 b16 matrix fragments cooperatively to shared memory.",
+        },
+        (StmatrixMultiplicity::X4, StmatrixLayout::Normal) => StmatrixRecipe {
+            multiplicity,
+            layout,
+            abi_id: "i0303",
+            id: "stmatrix_m8n8_x4_b16",
+            operation_key: "matrix.stmatrix.m8n8.x4.normal.b16.shared",
+            source_record: "int_nvvm_stmatrix_sync_aligned_m8n8_x4_b16",
+            llvm_symbol: "llvm.nvvm.stmatrix.sync.aligned.m8n8.x4.b16",
+            compatibility_name: "stmatrix_m8n8_x4",
+            dialect_op_type: "StmatrixM8n8X4Op",
+            dialect_op_name: "nvvm.stmatrix_m8n8_x4",
+            summary: "Stores four 8×8 b16 matrix fragments cooperatively to shared memory.",
+        },
+        (StmatrixMultiplicity::X4, StmatrixLayout::Transposed) => StmatrixRecipe {
+            multiplicity,
+            layout,
+            abi_id: "i0304",
+            id: "stmatrix_m8n8_x4_trans_b16",
+            operation_key: "matrix.stmatrix.m8n8.x4.transposed.b16.shared",
+            source_record: "int_nvvm_stmatrix_sync_aligned_m8n8_x4_trans_b16",
+            llvm_symbol: "llvm.nvvm.stmatrix.sync.aligned.m8n8.x4.trans.b16",
+            compatibility_name: "stmatrix_m8n8_x4_trans",
+            dialect_op_type: "StmatrixM8n8X4TransOp",
+            dialect_op_name: "nvvm.stmatrix_m8n8_x4_trans",
+            summary: "Stores four transposed 8×8 b16 matrix fragments cooperatively to shared memory.",
+        },
+    }
+}
+
+pub(in crate::resolve) fn stmatrix_variant_for_id(
+    id: &str,
+) -> Option<(StmatrixMultiplicity, StmatrixLayout)> {
+    match id {
+        "stmatrix_m8n8_x2_b16" => Some((StmatrixMultiplicity::X2, StmatrixLayout::Normal)),
+        "stmatrix_m8n8_x2_trans_b16" => {
+            Some((StmatrixMultiplicity::X2, StmatrixLayout::Transposed))
+        }
+        "stmatrix_m8n8_x4_b16" => Some((StmatrixMultiplicity::X4, StmatrixLayout::Normal)),
+        "stmatrix_m8n8_x4_trans_b16" => {
+            Some((StmatrixMultiplicity::X4, StmatrixLayout::Transposed))
+        }
+        _ => None,
+    }
+}
+
+pub(in crate::resolve) fn expand_stmatrix_admission(
+    admission: &StmatrixAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "stmatrix runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact stmatrix admission requires both backend evidence profiles"
+    );
+    let expected_variants = [
+        (StmatrixMultiplicity::X2, StmatrixLayout::Normal),
+        (StmatrixMultiplicity::X2, StmatrixLayout::Transposed),
+        (StmatrixMultiplicity::X4, StmatrixLayout::Normal),
+        (StmatrixMultiplicity::X4, StmatrixLayout::Transposed),
+    ];
+    let actual_variants = admission
+        .variants
+        .iter()
+        .map(|variant| (variant.multiplicity, variant.layout))
+        .collect::<Vec<_>>();
+    ensure!(
+        actual_variants == expected_variants,
+        "compact stmatrix admission must contain the four reviewed variants in canonical order"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = stmatrix_recipe(variant.multiplicity, variant.layout);
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must keep reserved ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            let count = recipe.multiplicity.register_count();
+            let mut rust_arguments = vec!["*mut u8".to_owned()];
+            rust_arguments.extend(std::iter::repeat_n("u32".to_owned(), count));
+            let mut dialect_operands = vec!["ptr".to_owned()];
+            dialect_operands.extend(std::iter::repeat_n("i32".to_owned(), count));
+            let mut llvm_arguments = vec!["anyptr".to_owned()];
+            llvm_arguments.extend(std::iter::repeat_n("i32".to_owned(), count));
+            let multiplicity = match recipe.multiplicity {
+                StmatrixMultiplicity::X2 => "x2",
+                StmatrixMultiplicity::X4 => "x4",
+            };
+            let mut modifiers = vec![
+                "sync".into(),
+                "aligned".into(),
+                "m8n8".into(),
+                multiplicity.into(),
+            ];
+            if recipe.layout == StmatrixLayout::Transposed {
+                modifiers.push("trans".into());
+            }
+            modifiers.extend(["shared".into(), "b16".into()]);
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: variant.abi_id.clone(),
+                operation_key: recipe.operation_key.into(),
+                family: "stmatrix".into(),
+                source: None,
+                source_record: Some(recipe.source_record.into()),
+                rust_module: "matrix".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments,
+                rust_result: "()".into(),
+                safe: false,
+                must_use: false,
+                safe_allowlist_reason: None,
+                public_rust_path: format!("cuda_intrinsics::matrix::{}", recipe.id),
+                compatibility_rust_paths: vec![format!(
+                    "cuda_device::tcgen05::{}",
+                    recipe.compatibility_name
+                )],
+                dialect_op_type: recipe.dialect_op_type.into(),
+                dialect_op_name: recipe.dialect_op_name.into(),
+                dialect_operands,
+                dialect_results: vec![],
+                llvm_symbol: Some(recipe.llvm_symbol.into()),
+                resolved_llvm_symbol: Some(format!("{}.p3", recipe.llvm_symbol)),
+                llvm_arguments,
+                llvm_results: vec![],
+                pure: false,
+                memory: "write".into(),
+                convergent: true,
+                execution_scope: "warp".into(),
+                minimum_ptx: "7.8".into(),
+                minimum_sm: Some("sm_90".into()),
+                ptx_result: "()".into(),
+                targets: "all".into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section: "9.7.14.5.16 Warp-level matrix store instruction: stmatrix"
+                    .into(),
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-stmatrix".into(),
+                lowering: "generated_stmatrix".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: BackendLoweringMechanism::TypedNvvm,
+                        evidence_profile: admission.llvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some("7.8".into()),
+                        minimum_sm: Some("sm_90".into()),
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some("7.8".into()),
+                        minimum_sm: Some("sm_90".into()),
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: Some(ImportedAddressSpace::Shared),
+                expected_ptx: InstructionPattern {
+                    mnemonic: "stmatrix".into(),
+                    modifiers,
+                    operands: vec![
+                        OperandPattern::Address,
+                        OperandPattern::RegisterList { length: count },
+                    ],
+                },
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn validate_stmatrix_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let (multiplicity, layout) = stmatrix_variant_for_id(&policy.id)
+        .with_context(|| format!("{} has no closed stmatrix recipe", policy.id))?;
+    let recipe = stmatrix_recipe(multiplicity, layout);
+    let count = multiplicity.register_count();
+    let mut rust_arguments = vec!["*mut u8".to_owned()];
+    rust_arguments.extend(std::iter::repeat_n("u32".to_owned(), count));
+    let mut dialect_operands = vec!["ptr".to_owned()];
+    dialect_operands.extend(std::iter::repeat_n("i32".to_owned(), count));
+    let mut llvm_arguments = vec!["anyptr".to_owned()];
+    llvm_arguments.extend(std::iter::repeat_n("i32".to_owned(), count));
+
+    ensure!(
+        policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.as_deref()
+                == Some(format!("{}.p3", recipe.llvm_symbol).as_str()),
+        "{} stmatrix identity does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "matrix"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == rust_arguments
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::matrix::{}", recipe.id)
+            && policy.compatibility_rust_paths
+                == [format!(
+                    "cuda_device::tcgen05::{}",
+                    recipe.compatibility_name
+                )],
+        "{} stmatrix Rust API does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == dialect_operands
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == llvm_arguments
+            && policy.llvm_results.is_empty()
+            && policy.lowering == "generated_stmatrix"
+            && policy.selected_address_space == Some(ImportedAddressSpace::Shared),
+        "{} stmatrix carriers or lowering do not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.properties
+            == [
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "WriteOnly<arg0>",
+            ]
+            && !policy.pure
+            && policy.memory == "write"
+            && policy.convergent
+            && policy.execution_scope == "warp",
+        "{} stmatrix effects disagree with the imported declaration",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == "7.8"
+            && policy.minimum_sm.as_deref() == Some("sm_90")
+            && policy.ptx_result == "()"
+            && policy.targets == "all"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.14.5.16 Warp-level matrix store instruction: stmatrix"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-stmatrix",
+        "{} stmatrix target floor or PTX provenance changed",
+        policy.id
+    );
+    let multiplicity_name = match multiplicity {
+        StmatrixMultiplicity::X2 => "x2",
+        StmatrixMultiplicity::X4 => "x4",
+    };
+    let mut modifiers = vec![
+        "sync".into(),
+        "aligned".into(),
+        "m8n8".into(),
+        multiplicity_name.into(),
+    ];
+    if layout == StmatrixLayout::Transposed {
+        modifiers.push("trans".into());
+    }
+    modifiers.extend(["shared".into(), "b16".into()]);
+    ensure!(
+        policy.expected_ptx
+            == (InstructionPattern {
+                mnemonic: "stmatrix".into(),
+                modifiers,
+                operands: vec![
+                    OperandPattern::Address,
+                    OperandPattern::RegisterList { length: count },
+                ],
+            }),
+        "{} expected PTX does not match its closed stmatrix shape",
+        policy.id
+    );
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && policy.backend_lowerings.iter().all(|route| {
+                !route.evidence_profile.trim().is_empty()
+                    && route.minimum_ptx.as_deref() == Some("7.8")
+                    && route.minimum_sm.as_deref() == Some("sm_90")
+            })
+            && policy.backend_lowerings.iter().any(|route| {
+                route.backend == IntrinsicBackend::LlvmNvptx
+                    && route.mechanism == BackendLoweringMechanism::TypedNvvm
+            })
+            && policy.backend_lowerings.iter().any(|route| {
+                route.backend == IntrinsicBackend::LibNvvm
+                    && route.mechanism == BackendLoweringMechanism::InlinePtx
+            }),
+        "{} must keep its reviewed typed-NVVM and inline-PTX routes",
+        policy.id
+    );
+    ensure!(
+        policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.cp_async_mbarrier.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.register_mma.is_none()
+            && policy.sparse_mma.is_none()
+            && policy.prmt.is_none()
+            && policy.cluster_barrier.is_none()
+            && policy.special_register.is_none()
+            && policy.debug_control.is_none(),
+        "{} mixes another generated-family contract with stmatrix",
+        policy.id
+    );
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_ldmatrix_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let variant = policy
+        .ldmatrix_variant
+        .as_ref()
+        .with_context(|| format!("{} has no closed ldmatrix variant", policy.id))?;
+    let safety = policy
+        .ldmatrix_safety
+        .as_ref()
+        .with_context(|| format!("{} has no ldmatrix safety contract", policy.id))?;
+    let classic = variant.shape == LdmatrixShape::M8n8 && variant.element == LdmatrixElement::B16;
+    let blackwell = matches!(
+        (variant.shape, variant.layout, variant.element),
+        (
+            LdmatrixShape::M8n16,
+            LdmatrixLayout::Normal,
+            LdmatrixElement::B8x16B4x16P64 | LdmatrixElement::B8x16B6x16P32
+        ) | (
+            LdmatrixShape::M16n16,
+            LdmatrixLayout::Transposed,
+            LdmatrixElement::B8 | LdmatrixElement::B8x16B4x16P64 | LdmatrixElement::B8x16B6x16P32
+        )
+    );
+    ensure!(
+        variant.shape != LdmatrixShape::M16n16 || variant.multiplicity != LdmatrixMultiplicity::X4,
+        "{} requests unsupported m16n16.x4 ldmatrix",
+        policy.id
+    );
+    ensure!(
+        (classic || blackwell) && variant.state_space == LdmatrixStateSpace::Shared,
+        "{} requests an unsupported ldmatrix shape, element, or state space",
+        policy.id
+    );
+    let expected_participation = if classic {
+        LdmatrixParticipation::AllWarpLanesSameInstruction
+    } else {
+        LdmatrixParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes
+    };
+    let expected_address_contract = match variant.shape {
+        LdmatrixShape::M8n8 => {
+            LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadableWithSm75Replication
+        }
+        LdmatrixShape::M8n16 => {
+            LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedSixteenBytesReadable
+        }
+        LdmatrixShape::M16n16 => {
+            LdmatrixAddressContract::WarpLaneAddressesMappedByMultiplicitySixteenByteAlignedThirtyTwoBytesReadable
+        }
+    };
+    ensure!(
+        safety.participation == expected_participation
+            && safety.address_contract == expected_address_contract
+            && safety.memory_order == LdmatrixMemoryOrder::Weak
+            && safety.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} has an unsupported ldmatrix safety contract",
+        policy.id
+    );
+    let count = variant.register_count();
+    let count_name = match variant.multiplicity {
+        LdmatrixMultiplicity::X1 => "x1",
+        LdmatrixMultiplicity::X2 => "x2",
+        LdmatrixMultiplicity::X4 => "x4",
+    };
+    let trans_record = match variant.layout {
+        LdmatrixLayout::Normal => "",
+        LdmatrixLayout::Transposed => "_trans",
+    };
+    let trans_symbol = match variant.layout {
+        LdmatrixLayout::Normal => "",
+        LdmatrixLayout::Transposed => ".trans",
+    };
+    let layout_name = match variant.layout {
+        LdmatrixLayout::Normal => "normal",
+        LdmatrixLayout::Transposed => "transposed",
+    };
+    let shape_name = match variant.shape {
+        LdmatrixShape::M8n8 => "m8n8",
+        LdmatrixShape::M8n16 => "m8n16",
+        LdmatrixShape::M16n16 => "m16n16",
+    };
+    let (element_record, element_symbol) = match variant.element {
+        LdmatrixElement::B16 => ("b16", "b16"),
+        LdmatrixElement::B8 => ("b8", "b8"),
+        LdmatrixElement::B8x16B4x16P64 => ("b8x16_b4x16_p64", "b8x16.b4x16_p64"),
+        LdmatrixElement::B8x16B6x16P32 => ("b8x16_b6x16_p32", "b8x16.b6x16_p32"),
+    };
+    let expected_source = format!(
+        "int_nvvm_ldmatrix_sync_aligned_{shape_name}_{count_name}{trans_record}_{element_record}"
+    );
+    let expected_symbol = format!(
+        "llvm.nvvm.ldmatrix.sync.aligned.{shape_name}.{count_name}{trans_symbol}.{element_symbol}"
+    );
+    let expected_name =
+        format!("ldmatrix_{shape_name}_{count_name}{trans_record}_{element_record}");
+    let expected_result = if count == 1 {
+        "u32".to_owned()
+    } else {
+        format!("[u32; {count}]")
+    };
+    let expected_adapter = if count == 1 {
+        LdmatrixAdapter::SingleResultDirect
+    } else {
+        LdmatrixAdapter::MultipleResultsToArray
+    };
+    ensure!(
+        policy.source_record.as_deref() == Some(expected_source.as_str())
+            && policy.llvm_symbol.as_deref() == Some(expected_symbol.as_str()),
+        "{} ldmatrix variant does not match its imported source record or base LLVM symbol",
+        policy.id
+    );
+    ensure!(
+        policy.resolved_llvm_symbol.as_deref() == Some(format!("{expected_symbol}.p3").as_str()),
+        "{} must keep the imported base symbol distinct from the resolved `.p3` overload",
+        policy.id
+    );
+    ensure!(
+        policy.rust_arguments == [if classic { "*const u32" } else { "*const u8" }]
+            && policy.rust_result == expected_result
+            && policy.llvm_arguments == ["anyptr"]
+            && policy.llvm_results == vec!["i32"; count]
+            && policy.ptx_result == policy.rust_result,
+        "{} ldmatrix Rust, imported LLVM, and PTX carrier signatures disagree",
+        policy.id
+    );
+    ensure!(
+        policy.id == expected_name
+            && policy.operation_key
+                == format!(
+                    "matrix.ldmatrix.{shape_name}.{count_name}.{layout_name}.{element_record}.shared"
+                )
+            && policy.rust_module == "matrix"
+            && policy.rust_name == expected_name
+            && !policy.safe
+            && policy.must_use != classic
+            && policy.safe_allowlist_reason.is_none()
+            && {
+                let expected_compatibility_paths = if classic {
+                    vec![format!(
+                        "cuda_device::wmma::ldmatrix_{count_name}{trans_record}"
+                    )]
+                } else if matches!(
+                    policy.id.as_str(),
+                    "ldmatrix_m8n16_x2_b8x16_b4x16_p64" | "ldmatrix_m8n16_x4_b8x16_b4x16_p64"
+                ) {
+                    vec![format!("cuda_device::wmma::{expected_name}")]
+                } else {
+                    vec![]
+                };
+                policy.compatibility_rust_paths == expected_compatibility_paths
+            }
+            && policy.lowering == "generated_ldmatrix"
+            && policy.ldmatrix_adapter == Some(expected_adapter)
+            && policy.selected_address_space == Some(ImportedAddressSpace::Shared),
+        "{} must preserve the closed raw/compatibility ldmatrix API, result adapter, and shared selection",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && declaration
+                .properties
+                .iter()
+                .any(|property| property == "IntrArgMemOnly")
+            && declaration
+                .properties
+                .iter()
+                .any(|property| property == "IntrReadMem"),
+        "{} ldmatrix effects disagree with the imported declaration",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        backend_pairs
+            == BTreeSet::from([
+                (
+                    IntrinsicBackend::LlvmNvptx,
+                    BackendLoweringMechanism::TypedNvvm
+                ),
+                (
+                    IntrinsicBackend::LibNvvm,
+                    BackendLoweringMechanism::InlinePtx
+                ),
+            ]),
+        "{} must define exactly the reviewed LLVM typed and libNVVM inline-PTX lowerings",
+        policy.id
+    );
+    ensure!(
+        policy
+            .backend_lowerings
+            .iter()
+            .all(|lowering| !lowering.evidence_profile.trim().is_empty()),
+        "{} backend lowering omits its evidence profile",
+        policy.id
+    );
+    if blackwell {
+        ensure!(
+            policy.minimum_ptx == "8.6"
+                && policy.minimum_sm.is_none()
+                && policy.targets == BLACKWELL_LDMATRIX_LLVM_TARGETS,
+            "{} must retain the reviewed PTX 8.6 floor and exact LLVM Blackwell target set",
+            policy.id
+        );
+        let llvm = policy
+            .backend_lowerings
+            .iter()
+            .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+            .expect("validated LLVM route");
+        let libnvvm = policy
+            .backend_lowerings
+            .iter()
+            .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
+            .expect("validated libNVVM route");
+        ensure!(
+            llvm.targets.is_none()
+                && llvm.minimum_sm.is_none()
+                && backend_target_requirement(policy, llvm)?
+                    == CatalogTargetRequirement {
+                        minimum_ptx: parse_ptx_version("8.6", &policy.id)?,
+                        hardware: parse_hardware_target_fields(
+                            &policy.id,
+                            BLACKWELL_LDMATRIX_LLVM_TARGETS,
+                            None,
+                        )?,
+                    }
+                && libnvvm.targets.as_deref() == Some(BLACKWELL_LDMATRIX_LIBNVVM_TARGETS)
+                && libnvvm.minimum_sm.is_none()
+                && backend_target_requirement(policy, libnvvm)?
+                    == CatalogTargetRequirement {
+                        minimum_ptx: parse_ptx_version("8.6", &policy.id)?,
+                        hardware: parse_hardware_target_fields(
+                            &policy.id,
+                            BLACKWELL_LDMATRIX_LIBNVVM_TARGETS,
+                            None,
+                        )?,
+                    },
+            "{} backend routes do not preserve the reviewed LLVM/libNVVM Blackwell target split",
+            policy.id
+        );
+    }
+    ensure!(
+        policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.mbarrier_basic.is_none(),
+        "{} mixes another generated-family contract with ldmatrix",
+        policy.id
+    );
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_movmatrix_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+) -> Result<()> {
+    let contract = policy
+        .movmatrix
+        .as_ref()
+        .context("movmatrix requires its closed contract")?;
+    ensure!(
+        policy.id == "movmatrix_trans_b16"
+            && policy.operation_key == "movmatrix.m8n8.trans.b16"
+            && matches!(
+                source,
+                IntrinsicSource::PtxNative { instruction }
+                    if instruction == "movmatrix.sync.aligned.m8n8.trans.b16"
+            )
+            && policy.rust_module == "matrix"
+            && policy.rust_name == "movmatrix_trans_b16"
+            && policy.rust_arguments == ["u32"]
+            && policy.rust_result == "u32"
+            && !policy.safe
+            && policy.must_use
+            && policy.public_rust_path == "cuda_intrinsics::matrix::movmatrix_trans_b16"
+            && policy.compatibility_rust_paths == ["cuda_device::wmma::movmatrix_trans_b16"]
+            && policy.dialect_op_type == "MovmatrixTransB16Op"
+            && policy.dialect_op_name == "nvvm.movmatrix_trans_b16"
+            && policy.dialect_operands == ["i32"]
+            && policy.dialect_results == ["i32"]
+            && !policy.pure
+            && policy.memory == "inaccessible_read_write"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == "7.8"
+            && policy.minimum_sm.as_deref() == Some("sm_75")
+            && policy.ptx_result == "u32"
+            && policy.targets == "all"
+            && policy.lowering == "generated_movmatrix_inline_ptx"
+            && policy.expected_ptx
+                == InstructionPattern {
+                    mnemonic: "movmatrix".into(),
+                    modifiers: ["sync", "aligned", "m8n8", "trans", "b16"]
+                        .into_iter()
+                        .map(str::to_owned)
+                        .collect(),
+                    operands: vec![OperandPattern::Register, OperandPattern::Register],
+                },
+        "{} is outside the closed movmatrix recipe",
+        policy.id
+    );
+    ensure!(
+        contract.participation == MovmatrixParticipation::AllWarpLanesSameInstructionNoExitedLanes
+            && contract.adapter == MovmatrixAdapter::PackedB16x2U32ToPackedB16x2U32,
+        "{} has an unreviewed movmatrix safety or adapter contract",
+        policy.id
+    );
+    ensure_exact_inline_ptx_backends(
+        policy,
+        [
+            (IntrinsicBackend::LlvmNvptx, "7.8", Some("sm_75")),
+            (IntrinsicBackend::LibNvvm, "7.8", Some("sm_75")),
+        ],
+        "movmatrix",
+    )?;
+    ensure_no_other_family_contract(policy, "movmatrix")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/mbarrier_extended.rs b/crates/cuda-intrinsics-gen/src/resolve/families/mbarrier_extended.rs
new file mode 100644
index 0000000000..50800ed4e4
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/mbarrier_extended.rs
@@ -0,0 +1,835 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, IntrinsicSource,
+    MbarrierExtended, MbarrierExtendedAdapter, MbarrierExtendedAdmission,
+    MbarrierExtendedOperation, MbarrierExtendedSourceContract, OverlayBackendLowering,
+    OverlayIntrinsic, RuntimeValidation,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use crate::resolve::guards::*;
+
+#[derive(Clone)]
+pub(in crate::resolve) struct MbarrierExtendedRecipe {
+    pub(in crate::resolve) operation: MbarrierExtendedOperation,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: Option<&'static str>,
+    pub(in crate::resolve) llvm_symbol: Option<&'static str>,
+    pub(in crate::resolve) ptx_native_instruction: Option<&'static str>,
+    pub(in crate::resolve) rust_arguments: &'static [&'static str],
+    pub(in crate::resolve) rust_result: &'static str,
+    pub(in crate::resolve) must_use: bool,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) dialect_operands: &'static [&'static str],
+    pub(in crate::resolve) dialect_results: &'static [&'static str],
+    pub(in crate::resolve) llvm_arguments: &'static [&'static str],
+    pub(in crate::resolve) llvm_results: &'static [&'static str],
+    pub(in crate::resolve) llvm_properties: &'static [&'static str],
+    pub(in crate::resolve) adapter: MbarrierExtendedAdapter,
+    pub(in crate::resolve) source_contract: MbarrierExtendedSourceContract,
+    pub(in crate::resolve) execution_scope: &'static str,
+    pub(in crate::resolve) minimum_ptx: &'static str,
+    pub(in crate::resolve) minimum_sm: &'static str,
+    pub(in crate::resolve) ptx_result: &'static str,
+    pub(in crate::resolve) expected_ptx: InstructionPattern,
+    pub(in crate::resolve) inline_ptx: &'static str,
+    pub(in crate::resolve) inline_constraints: &'static str,
+    pub(in crate::resolve) ptx_isa_section: &'static str,
+    pub(in crate::resolve) ptx_isa_url: &'static str,
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn mbarrier_extended_recipe(
+    operation: MbarrierExtendedOperation,
+) -> MbarrierExtendedRecipe {
+    let instruction = |modifiers: &[&str], operands| InstructionPattern {
+        mnemonic: if modifiers.first() == Some(&"nanosleep") {
+            "nanosleep".into()
+        } else if modifiers.first() == Some(&"fence") {
+            "fence".into()
+        } else {
+            "mbarrier".into()
+        },
+        modifiers: modifiers[1..].iter().map(|value| (*value).into()).collect(),
+        operands,
+    };
+    match operation {
+        MbarrierExtendedOperation::ArriveExpectTxCta => MbarrierExtendedRecipe {
+            operation,
+            abi_id: "i0306",
+            id: "mbarrier_arrive_expect_tx",
+            operation_key: "barrier.mbarrier.arrive.expect_tx.shared.cta.release.cta",
+            source_record: Some("int_nvvm_mbarrier_arrive_expect_tx_scope_cta_space_cta"),
+            llvm_symbol: Some("llvm.nvvm.mbarrier.arrive.expect.tx.scope.cta.space.cta"),
+            ptx_native_instruction: None,
+            rust_arguments: &["*const u64", "u32", "u32"],
+            rust_result: "u64",
+            must_use: true,
+            dialect_op_type: "MbarrierArriveExpectTxSharedOp",
+            dialect_op_name: "nvvm.mbarrier_arrive_expect_tx_shared",
+            dialect_operands: &["ptr", "i32"],
+            dialect_results: &["i64"],
+            llvm_arguments: &["shared_ptr", "i32"],
+            llvm_results: &["i64"],
+            llvm_properties: &["IntrConvergent", "IntrNoCallback"],
+            adapter: MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount,
+            source_contract: MbarrierExtendedSourceContract::LlvmImported,
+            execution_scope: "cta",
+            minimum_ptx: "8.0",
+            minimum_sm: "sm_90",
+            ptx_result: "u64",
+            expected_ptx: instruction(
+                &[
+                    "mbarrier",
+                    "arrive",
+                    "expect_tx",
+                    "release",
+                    "cta",
+                    "shared::cta",
+                    "b64",
+                ],
+                vec![
+                    OperandPattern::Register,
+                    OperandPattern::Address,
+                    OperandPattern::Register,
+                ],
+            ),
+            inline_ptx: "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 $0, [$1], $2;",
+            inline_constraints: "=l,l,r,~{memory}",
+            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.arrive",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-arrive",
+            summary: "Arrives at a CTA-shared barrier and adds expected transaction bytes.",
+        },
+        MbarrierExtendedOperation::ArriveExpectTxCluster => MbarrierExtendedRecipe {
+            operation,
+            abi_id: "i0307",
+            id: "mbarrier_arrive_expect_tx_cluster",
+            operation_key: "barrier.mbarrier.arrive.expect_tx.shared.cta.relaxed.cluster",
+            source_record: Some(
+                "int_nvvm_mbarrier_arrive_expect_tx_relaxed_scope_cluster_space_cta",
+            ),
+            llvm_symbol: Some(
+                "llvm.nvvm.mbarrier.arrive.expect.tx.relaxed.scope.cluster.space.cta",
+            ),
+            ptx_native_instruction: None,
+            rust_arguments: &["*const u64", "u32", "u32"],
+            rust_result: "u64",
+            must_use: true,
+            dialect_op_type: "MbarrierArriveExpectTxClusterOp",
+            dialect_op_name: "nvvm.mbarrier_arrive_expect_tx_cluster",
+            dialect_operands: &["ptr", "i32"],
+            dialect_results: &["i64"],
+            llvm_arguments: &["shared_ptr", "i32"],
+            llvm_results: &["i64"],
+            llvm_properties: &["IntrArgMemOnly", "IntrConvergent", "IntrNoCallback"],
+            adapter: MbarrierExtendedAdapter::PointerTxCountBytesToTokenDroppingTxCount,
+            source_contract: MbarrierExtendedSourceContract::LlvmImported,
+            execution_scope: "cluster",
+            minimum_ptx: "8.6",
+            minimum_sm: "sm_90",
+            ptx_result: "u64",
+            expected_ptx: instruction(
+                &[
+                    "mbarrier",
+                    "arrive",
+                    "expect_tx",
+                    "relaxed",
+                    "cluster",
+                    "shared::cta",
+                    "b64",
+                ],
+                vec![
+                    OperandPattern::Register,
+                    OperandPattern::Address,
+                    OperandPattern::Register,
+                ],
+            ),
+            inline_ptx: "mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 $0, [$1], $2;",
+            inline_constraints: "=l,l,r,~{memory}",
+            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.arrive",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-arrive",
+            summary: "Arrives at a CTA-shared barrier with cluster-scope transaction tracking.",
+        },
+        MbarrierExtendedOperation::ArriveRemoteCluster => MbarrierExtendedRecipe {
+            operation,
+            abi_id: "i0308",
+            id: "mbarrier_arrive_cluster",
+            operation_key: "barrier.mbarrier.arrive.shared.cluster.release.cluster.raw_address",
+            source_record: None,
+            llvm_symbol: None,
+            ptx_native_instruction: Some("mbarrier.arrive.release.cluster.shared::cluster.b64"),
+            rust_arguments: &["u64"],
+            rust_result: "()",
+            must_use: false,
+            dialect_op_type: "MbarrierArriveClusterOp",
+            dialect_op_name: "nvvm.mbarrier_arrive_cluster",
+            dialect_operands: &["i64"],
+            dialect_results: &[],
+            llvm_arguments: &[],
+            llvm_results: &[],
+            llvm_properties: &[],
+            adapter: MbarrierExtendedAdapter::RawClusterAddressToVoid,
+            source_contract: MbarrierExtendedSourceContract::PtxNativeRawClusterAddress,
+            execution_scope: "cluster",
+            minimum_ptx: "8.0",
+            minimum_sm: "sm_90",
+            ptx_result: "()",
+            expected_ptx: instruction(
+                &[
+                    "mbarrier",
+                    "arrive",
+                    "release",
+                    "cluster",
+                    "shared::cluster",
+                    "b64",
+                ],
+                vec![
+                    OperandPattern::Exact { value: "_".into() },
+                    OperandPattern::Address,
+                ],
+            ),
+            inline_ptx: "mbarrier.arrive.release.cluster.shared::cluster.b64 _, [$0];",
+            inline_constraints: "l,~{memory}",
+            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.arrive",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-arrive",
+            summary: "Arrives at a remote cluster-shared barrier through its raw address.",
+        },
+        MbarrierExtendedOperation::TryWaitTokenCta => MbarrierExtendedRecipe {
+            operation,
+            abi_id: "i0309",
+            id: "mbarrier_try_wait",
+            operation_key: "barrier.mbarrier.try_wait.shared.cta.token",
+            source_record: Some("int_nvvm_mbarrier_try_wait_scope_cta_space_cta"),
+            llvm_symbol: Some("llvm.nvvm.mbarrier.try.wait.scope.cta.space.cta"),
+            ptx_native_instruction: None,
+            rust_arguments: &["*const u64", "u64"],
+            rust_result: "bool",
+            must_use: true,
+            dialect_op_type: "MbarrierTryWaitSharedOp",
+            dialect_op_name: "nvvm.mbarrier_try_wait_shared",
+            dialect_operands: &["ptr", "i64"],
+            dialect_results: &["i1"],
+            llvm_arguments: &["shared_ptr", "i64"],
+            llvm_results: &["i1"],
+            llvm_properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
+            adapter: MbarrierExtendedAdapter::PointerTokenToPredicate,
+            source_contract: MbarrierExtendedSourceContract::LlvmImported,
+            execution_scope: "cta",
+            minimum_ptx: "7.8",
+            minimum_sm: "sm_90",
+            ptx_result: "bool",
+            expected_ptx: instruction(
+                &["mbarrier", "try_wait", "shared", "b64"],
+                vec![
+                    OperandPattern::Register,
+                    OperandPattern::Address,
+                    OperandPattern::Register,
+                ],
+            ),
+            inline_ptx: "{ .reg .pred %p0; mbarrier.try_wait.shared.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
+            inline_constraints: "=r,l,l,~{memory}",
+            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.test_wait / mbarrier.try_wait",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-mbarrier-try-wait",
+            summary: "Tests a CTA-shared barrier token with a scheduling hint.",
+        },
+        MbarrierExtendedOperation::TryWaitParityCta => MbarrierExtendedRecipe {
+            operation,
+            abi_id: "i0310",
+            id: "mbarrier_try_wait_parity",
+            operation_key: "barrier.mbarrier.try_wait.parity.shared.cta",
+            source_record: Some("int_nvvm_mbarrier_try_wait_parity_scope_cta_space_cta"),
+            llvm_symbol: Some("llvm.nvvm.mbarrier.try.wait.parity.scope.cta.space.cta"),
+            ptx_native_instruction: None,
+            rust_arguments: &["*const u64", "u32"],
+            rust_result: "bool",
+            must_use: true,
+            dialect_op_type: "MbarrierTryWaitParitySharedOp",
+            dialect_op_name: "nvvm.mbarrier_try_wait_parity_shared",
+            dialect_operands: &["ptr", "i32"],
+            dialect_results: &["i1"],
+            llvm_arguments: &["shared_ptr", "i32"],
+            llvm_results: &["i1"],
+            llvm_properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
+            adapter: MbarrierExtendedAdapter::PointerParityToPredicate,
+            source_contract: MbarrierExtendedSourceContract::LlvmImported,
+            execution_scope: "cta",
+            minimum_ptx: "7.8",
+            minimum_sm: "sm_90",
+            ptx_result: "bool",
+            expected_ptx: instruction(
+                &["mbarrier", "try_wait", "parity", "shared::cta", "b64"],
+                vec![
+                    OperandPattern::Register,
+                    OperandPattern::Address,
+                    OperandPattern::Register,
+                ],
+            ),
+            inline_ptx: "{ .reg .pred %p0; mbarrier.try_wait.parity.shared::cta.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
+            inline_constraints: "=r,l,r,~{memory}",
+            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.test_wait / mbarrier.try_wait",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-mbarrier-try-wait",
+            summary: "Tests a CTA-shared barrier phase by parity.",
+        },
+        MbarrierExtendedOperation::TryWaitParityCluster => MbarrierExtendedRecipe {
+            operation,
+            abi_id: "i0311",
+            id: "mbarrier_try_wait_parity_cluster",
+            operation_key: "barrier.mbarrier.try_wait.parity.shared.cta.acquire.cluster",
+            source_record: Some("int_nvvm_mbarrier_try_wait_parity_scope_cluster_space_cta"),
+            llvm_symbol: Some("llvm.nvvm.mbarrier.try.wait.parity.scope.cluster.space.cta"),
+            ptx_native_instruction: None,
+            rust_arguments: &["*const u64", "u32"],
+            rust_result: "bool",
+            must_use: true,
+            dialect_op_type: "MbarrierTryWaitParityClusterOp",
+            dialect_op_name: "nvvm.mbarrier_try_wait_parity_cluster",
+            dialect_operands: &["ptr", "i32"],
+            dialect_results: &["i1"],
+            llvm_arguments: &["shared_ptr", "i32"],
+            llvm_results: &["i1"],
+            llvm_properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
+            adapter: MbarrierExtendedAdapter::PointerParityToPredicate,
+            source_contract: MbarrierExtendedSourceContract::LlvmImported,
+            execution_scope: "cluster",
+            minimum_ptx: "8.0",
+            minimum_sm: "sm_90",
+            ptx_result: "bool",
+            expected_ptx: instruction(
+                &[
+                    "mbarrier",
+                    "try_wait",
+                    "parity",
+                    "acquire",
+                    "cluster",
+                    "shared::cta",
+                    "b64",
+                ],
+                vec![
+                    OperandPattern::Register,
+                    OperandPattern::Address,
+                    OperandPattern::Register,
+                ],
+            ),
+            inline_ptx: "{ .reg .pred %p0; mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
+            inline_constraints: "=r,l,r,~{memory}",
+            ptx_isa_section: "Parallel Synchronization and Communication Instructions: mbarrier.test_wait / mbarrier.try_wait",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-mbarrier-try-wait",
+            summary: "Tests barrier parity with cluster-scope acquire ordering.",
+        },
+        MbarrierExtendedOperation::FenceProxyAsyncSharedCta => MbarrierExtendedRecipe {
+            operation,
+            abi_id: "i0312",
+            id: "fence_proxy_async_shared_cta",
+            operation_key: "fence.proxy.async.shared.cta",
+            source_record: Some("int_nvvm_fence_proxy_async_shared_cta"),
+            llvm_symbol: Some("llvm.nvvm.fence.proxy.async.shared_cta"),
+            ptx_native_instruction: None,
+            rust_arguments: &[],
+            rust_result: "()",
+            must_use: false,
+            dialect_op_type: "FenceProxyAsyncSharedCtaOp",
+            dialect_op_name: "nvvm.fence_proxy_async_shared_cta",
+            dialect_operands: &[],
+            dialect_results: &[],
+            llvm_arguments: &[],
+            llvm_results: &[],
+            llvm_properties: &["IntrNoCallback"],
+            adapter: MbarrierExtendedAdapter::ZeroOperandsToVoid,
+            source_contract: MbarrierExtendedSourceContract::LlvmImported,
+            execution_scope: "cta",
+            minimum_ptx: "8.0",
+            minimum_sm: "sm_90",
+            ptx_result: "()",
+            expected_ptx: instruction(&["fence", "proxy", "async", "shared::cta"], vec![]),
+            inline_ptx: "fence.proxy.async.shared::cta;",
+            inline_constraints: "~{memory}",
+            ptx_isa_section: "Parallel Synchronization and Communication Instructions: fence.proxy",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-fence-proxy",
+            summary: "Makes CTA-shared generic-proxy writes visible to the async proxy.",
+        },
+        MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster => MbarrierExtendedRecipe {
+            operation,
+            abi_id: "i0313",
+            id: "fence_mbarrier_init_release_cluster",
+            operation_key: "fence.mbarrier_init.release.cluster",
+            source_record: Some("int_nvvm_fence_mbarrier_init_release_cluster"),
+            llvm_symbol: Some("llvm.nvvm.fence.mbarrier_init.release.cluster"),
+            ptx_native_instruction: None,
+            rust_arguments: &[],
+            rust_result: "()",
+            must_use: false,
+            dialect_op_type: "FenceMbarrierInitReleaseClusterOp",
+            dialect_op_name: "nvvm.fence_mbarrier_init_release_cluster",
+            dialect_operands: &[],
+            dialect_results: &[],
+            llvm_arguments: &[],
+            llvm_results: &[],
+            llvm_properties: &["IntrNoCallback"],
+            adapter: MbarrierExtendedAdapter::ZeroOperandsToVoid,
+            source_contract: MbarrierExtendedSourceContract::LlvmImported,
+            execution_scope: "cluster",
+            minimum_ptx: "8.0",
+            minimum_sm: "sm_90",
+            ptx_result: "()",
+            expected_ptx: instruction(&["fence", "mbarrier_init", "release", "cluster"], vec![]),
+            inline_ptx: "fence.mbarrier_init.release.cluster;",
+            inline_constraints: "~{memory}",
+            ptx_isa_section: "Parallel Synchronization and Communication Instructions: fence.mbarrier_init",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-fence-mbarrier-init",
+            summary: "Releases mbarrier initialization at cluster scope.",
+        },
+        MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster => {
+            MbarrierExtendedRecipe {
+                operation,
+                abi_id: "i0314",
+                id: "fence_proxy_async_generic_release_shared_cta_cluster",
+                operation_key: "fence.proxy.async_generic.release.sync_restrict.shared_cta.cluster",
+                source_record: Some(
+                    "int_nvvm_fence_proxy_async_generic_release_sync_restrict_space_cta_scope_cluster",
+                ),
+                llvm_symbol: Some(
+                    "llvm.nvvm.fence.proxy.async_generic.release.sync_restrict.space.cta.scope.cluster",
+                ),
+                ptx_native_instruction: None,
+                rust_arguments: &[],
+                rust_result: "()",
+                must_use: false,
+                dialect_op_type: "FenceProxyAsyncGenericReleaseSharedCtaClusterOp",
+                dialect_op_name: "nvvm.fence_proxy_async_generic_release_shared_cta_cluster",
+                dialect_operands: &[],
+                dialect_results: &[],
+                llvm_arguments: &[],
+                llvm_results: &[],
+                llvm_properties: &["IntrNoCallback"],
+                adapter: MbarrierExtendedAdapter::ZeroOperandsToVoid,
+                source_contract: MbarrierExtendedSourceContract::LlvmImported,
+                execution_scope: "cluster",
+                minimum_ptx: "8.6",
+                minimum_sm: "sm_90",
+                ptx_result: "()",
+                expected_ptx: instruction(
+                    &[
+                        "fence",
+                        "proxy",
+                        "async::generic",
+                        "release",
+                        "sync_restrict::shared::cta",
+                        "cluster",
+                    ],
+                    vec![],
+                ),
+                inline_ptx: "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
+                inline_constraints: "~{memory}",
+                ptx_isa_section: "Parallel Synchronization and Communication Instructions: fence.proxy",
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-fence-proxy",
+                summary: "Releases CTA-shared generic-proxy writes to the async proxy at cluster scope.",
+            }
+        }
+        MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster => {
+            MbarrierExtendedRecipe {
+                operation,
+                abi_id: "i0315",
+                id: "fence_proxy_async_generic_acquire_shared_cluster_cluster",
+                operation_key: "fence.proxy.async_generic.acquire.sync_restrict.shared_cluster.cluster",
+                source_record: Some(
+                    "int_nvvm_fence_proxy_async_generic_acquire_sync_restrict_space_cluster_scope_cluster",
+                ),
+                llvm_symbol: Some(
+                    "llvm.nvvm.fence.proxy.async_generic.acquire.sync_restrict.space.cluster.scope.cluster",
+                ),
+                ptx_native_instruction: None,
+                rust_arguments: &[],
+                rust_result: "()",
+                must_use: false,
+                dialect_op_type: "FenceProxyAsyncGenericAcquireSharedClusterClusterOp",
+                dialect_op_name: "nvvm.fence_proxy_async_generic_acquire_shared_cluster_cluster",
+                dialect_operands: &[],
+                dialect_results: &[],
+                llvm_arguments: &[],
+                llvm_results: &[],
+                llvm_properties: &["IntrNoCallback"],
+                adapter: MbarrierExtendedAdapter::ZeroOperandsToVoid,
+                source_contract: MbarrierExtendedSourceContract::LlvmImported,
+                execution_scope: "cluster",
+                minimum_ptx: "8.6",
+                minimum_sm: "sm_90",
+                ptx_result: "()",
+                expected_ptx: instruction(
+                    &[
+                        "fence",
+                        "proxy",
+                        "async::generic",
+                        "acquire",
+                        "sync_restrict::shared::cluster",
+                        "cluster",
+                    ],
+                    vec![],
+                ),
+                inline_ptx: "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;",
+                inline_constraints: "~{memory}",
+                ptx_isa_section: "Parallel Synchronization and Communication Instructions: fence.proxy",
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-fence-proxy",
+                summary: "Acquires cluster-shared async-proxy writes through the generic proxy.",
+            }
+        }
+        MbarrierExtendedOperation::Nanosleep => MbarrierExtendedRecipe {
+            operation,
+            abi_id: "i0316",
+            id: "nanosleep",
+            operation_key: "thread.nanosleep.u32",
+            source_record: Some("int_nvvm_nanosleep"),
+            llvm_symbol: Some("llvm.nvvm.nanosleep"),
+            ptx_native_instruction: None,
+            rust_arguments: &["u32"],
+            rust_result: "()",
+            must_use: false,
+            dialect_op_type: "NanosleepOp",
+            dialect_op_name: "nvvm.nanosleep",
+            dialect_operands: &["i32"],
+            dialect_results: &[],
+            llvm_arguments: &["i32"],
+            llvm_results: &[],
+            llvm_properties: &["IntrConvergent", "IntrHasSideEffects", "IntrNoMem"],
+            adapter: MbarrierExtendedAdapter::NanosecondsToVoid,
+            source_contract: MbarrierExtendedSourceContract::LlvmImported,
+            execution_scope: "thread",
+            minimum_ptx: "6.3",
+            minimum_sm: "sm_70",
+            ptx_result: "()",
+            expected_ptx: instruction(
+                &["nanosleep", "u32"],
+                vec![OperandPattern::RegisterOrImmediate],
+            ),
+            inline_ptx: "nanosleep.u32 $0;",
+            inline_constraints: "r,~{memory}",
+            ptx_isa_section: "Parallel Synchronization and Communication Instructions: nanosleep",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-nanosleep",
+            summary: "Suspends the executing thread for approximately the requested nanoseconds.",
+        },
+    }
+}
+
+pub(crate) fn mbarrier_extended_inline_recipe(
+    operation: MbarrierExtendedOperation,
+) -> (&'static str, &'static str) {
+    let recipe = mbarrier_extended_recipe(operation);
+    (recipe.inline_ptx, recipe.inline_constraints)
+}
+
+pub(in crate::resolve) fn mbarrier_extended_backend_floor(
+    operation: MbarrierExtendedOperation,
+    backend: IntrinsicBackend,
+) -> (&'static str, &'static str) {
+    let recipe = mbarrier_extended_recipe(operation);
+    match (operation, backend) {
+        (MbarrierExtendedOperation::Nanosleep, IntrinsicBackend::LibNvvm) => ("6.3", "sm_75"),
+        _ => (recipe.minimum_ptx, recipe.minimum_sm),
+    }
+}
+
+pub(in crate::resolve) fn expand_mbarrier_extended_admission(
+    admission: &MbarrierExtendedAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "extended-mbarrier runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact extended-mbarrier admission requires both backend evidence profiles"
+    );
+    let expected_operations = BTreeSet::from([
+        MbarrierExtendedOperation::ArriveExpectTxCta,
+        MbarrierExtendedOperation::ArriveExpectTxCluster,
+        MbarrierExtendedOperation::ArriveRemoteCluster,
+        MbarrierExtendedOperation::TryWaitTokenCta,
+        MbarrierExtendedOperation::TryWaitParityCta,
+        MbarrierExtendedOperation::TryWaitParityCluster,
+        MbarrierExtendedOperation::FenceProxyAsyncSharedCta,
+        MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster,
+        MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster,
+        MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster,
+        MbarrierExtendedOperation::Nanosleep,
+    ]);
+    let actual_operations = admission
+        .variants
+        .iter()
+        .map(|variant| variant.operation)
+        .collect::<BTreeSet<_>>();
+    ensure!(
+        admission.variants.len() == expected_operations.len()
+            && actual_operations == expected_operations,
+        "compact extended-mbarrier admission must contain each reviewed operation exactly once"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = mbarrier_extended_recipe(variant.operation);
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must keep reserved ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            let source =
+                recipe
+                    .ptx_native_instruction
+                    .map(|instruction| IntrinsicSource::PtxNative {
+                        instruction: instruction.into(),
+                    });
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: variant.abi_id.clone(),
+                operation_key: recipe.operation_key.into(),
+                family: "mbarrier_extended".into(),
+                source,
+                source_record: recipe.source_record.map(str::to_owned),
+                rust_module: "barrier".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments: recipe
+                    .rust_arguments
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                rust_result: recipe.rust_result.into(),
+                safe: false,
+                must_use: recipe.must_use,
+                safe_allowlist_reason: None,
+                public_rust_path: format!("cuda_intrinsics::barrier::{}", recipe.id),
+                compatibility_rust_paths: vec![format!("cuda_device::barrier::{}", recipe.id)],
+                dialect_op_type: recipe.dialect_op_type.into(),
+                dialect_op_name: recipe.dialect_op_name.into(),
+                dialect_operands: recipe
+                    .dialect_operands
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                dialect_results: recipe
+                    .dialect_results
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                llvm_symbol: recipe.llvm_symbol.map(str::to_owned),
+                resolved_llvm_symbol: None,
+                llvm_arguments: recipe
+                    .llvm_arguments
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                llvm_results: recipe
+                    .llvm_results
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                pure: false,
+                memory: "read_write".into(),
+                convergent: true,
+                execution_scope: recipe.execution_scope.into(),
+                minimum_ptx: recipe.minimum_ptx.into(),
+                minimum_sm: Some(recipe.minimum_sm.into()),
+                ptx_result: recipe.ptx_result.into(),
+                targets: "all".into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section: recipe.ptx_isa_section.into(),
+                ptx_isa_url: recipe.ptx_isa_url.into(),
+                lowering: "generated_mbarrier_extended_inline_ptx".into(),
+                backend_lowerings: [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
+                    .into_iter()
+                    .map(|backend| {
+                        let (minimum_ptx, minimum_sm) =
+                            mbarrier_extended_backend_floor(recipe.operation, backend);
+                        OverlayBackendLowering {
+                            backend,
+                            mechanism: BackendLoweringMechanism::InlinePtx,
+                            evidence_profile: match backend {
+                                IntrinsicBackend::LlvmNvptx => {
+                                    admission.llvm_evidence_profile.clone()
+                                }
+                                IntrinsicBackend::LibNvvm => {
+                                    admission.libnvvm_evidence_profile.clone()
+                                }
+                            },
+                            targets: None,
+                            minimum_ptx: Some(minimum_ptx.into()),
+                            minimum_sm: Some(minimum_sm.into()),
+                        }
+                    })
+                    .collect(),
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: Some(MbarrierExtended {
+                    operation: recipe.operation,
+                    adapter: recipe.adapter,
+                    source_contract: recipe.source_contract,
+                    runtime_validation: admission.runtime_validation,
+                }),
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: recipe.expected_ptx,
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn validate_mbarrier_extended_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+    declaration: Option<&ImportedIntrinsic>,
+) -> Result<()> {
+    let contract = policy
+        .mbarrier_extended
+        .as_ref()
+        .with_context(|| format!("{} has no closed extended-mbarrier contract", policy.id))?;
+    let recipe = mbarrier_extended_recipe(contract.operation);
+    ensure!(
+        contract.adapter == recipe.adapter
+            && contract.source_contract == recipe.source_contract
+            && policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key,
+        "{} identity or adapter does not match its closed extended-mbarrier recipe",
+        policy.id
+    );
+    match recipe.source_contract {
+        MbarrierExtendedSourceContract::LlvmImported => ensure!(
+            matches!(
+                source,
+                IntrinsicSource::LlvmImported { source_record }
+                    if Some(source_record.as_str()) == recipe.source_record
+            ) && policy.source.is_none()
+                && policy.source_record.as_deref() == recipe.source_record
+                && policy.llvm_symbol.as_deref() == recipe.llvm_symbol
+                && declaration.is_some_and(|record| {
+                    record.source_record == recipe.source_record.unwrap()
+                        && record.properties == recipe.llvm_properties
+                }),
+            "{} LLVM source contract changed",
+            policy.id
+        ),
+        MbarrierExtendedSourceContract::PtxNativeRawClusterAddress => ensure!(
+            matches!(
+                source,
+                IntrinsicSource::PtxNative { instruction }
+                    if Some(instruction.as_str()) == recipe.ptx_native_instruction
+            ) && policy.source_record.is_none()
+                && policy.llvm_symbol.is_none()
+                && declaration.is_none(),
+            "{} must remain the PTX-native raw-cluster-address carrier",
+            policy.id
+        ),
+    }
+    ensure!(
+        policy.rust_module == "barrier"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == recipe.rust_arguments
+            && policy.rust_result == recipe.rust_result
+            && !policy.safe
+            && policy.must_use == recipe.must_use
+            && policy.public_rust_path == format!("cuda_intrinsics::barrier::{}", recipe.id)
+            && policy.compatibility_rust_paths == [format!("cuda_device::barrier::{}", recipe.id)],
+        "{} Rust API does not match its closed extended-mbarrier recipe",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == recipe.dialect_operands
+            && policy.dialect_results == recipe.dialect_results
+            && policy.llvm_arguments == recipe.llvm_arguments
+            && policy.llvm_results == recipe.llvm_results
+            && policy.lowering == "generated_mbarrier_extended_inline_ptx",
+        "{} carrier or lowering does not match its closed extended-mbarrier recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read_write"
+            && policy.convergent
+            && policy.execution_scope == recipe.execution_scope,
+        "{} convergence, memory clobber, or execution scope changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
+            && policy.ptx_result == recipe.ptx_result
+            && policy.targets == "all"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.ptx_isa_section
+            && policy.ptx_isa_url == recipe.ptx_isa_url,
+        "{} target floor or PTX provenance changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx == recipe.expected_ptx,
+        "{} expected PTX does not match its closed extended-mbarrier recipe",
+        policy.id
+    );
+    ensure_exact_inline_ptx_backends(
+        policy,
+        [
+            (
+                IntrinsicBackend::LlvmNvptx,
+                mbarrier_extended_backend_floor(recipe.operation, IntrinsicBackend::LlvmNvptx).0,
+                Some(
+                    mbarrier_extended_backend_floor(recipe.operation, IntrinsicBackend::LlvmNvptx)
+                        .1,
+                ),
+            ),
+            (
+                IntrinsicBackend::LibNvvm,
+                mbarrier_extended_backend_floor(recipe.operation, IntrinsicBackend::LibNvvm).0,
+                Some(
+                    mbarrier_extended_backend_floor(recipe.operation, IntrinsicBackend::LibNvvm).1,
+                ),
+            ),
+        ],
+        "extended-mbarrier",
+    )?;
+    ensure_no_other_family_contract(policy, "extended mbarrier")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/minmax.rs b/crates/cuda-intrinsics-gen/src/resolve/families/minmax.rs
new file mode 100644
index 0000000000..7a4478bd2a
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/minmax.rs
@@ -0,0 +1,891 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ExtendedMinMax, ExtendedMinMaxAdapter, ExtendedMinMaxAdmission,
+    ExtendedMinMaxFormat, ExtendedMinMaxNan, ExtendedMinMaxOperation, ExtendedMinMaxSubnormal,
+    ImportedIntrinsic, IntegerMinMaxFormat, IntegerMinMaxOperation, IntrinsicBackend,
+    IntrinsicSource, OverlayBackendLowering, OverlayIntrinsic, RuntimeValidation,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+
+use crate::resolve::abi_ledger::*;
+use crate::resolve::guards::*;
+use crate::resolve::targets::*;
+
+pub(in crate::resolve) type ExtendedMinMaxVariant = (
+    ExtendedMinMaxFormat,
+    ExtendedMinMaxOperation,
+    ExtendedMinMaxSubnormal,
+    ExtendedMinMaxNan,
+    bool,
+);
+
+pub(in crate::resolve) struct ExtendedMinMaxRecipe {
+    id: String,
+    operation_key: String,
+    source_record: String,
+    llvm_symbol: String,
+    llvm_type: &'static str,
+    rust_module: &'static str,
+    rust_type: &'static str,
+    dialect_type: &'static str,
+    adapter: ExtendedMinMaxAdapter,
+    selection_record: String,
+    selection_asm: String,
+    predicates: Vec<String>,
+    classes: Vec<&'static str>,
+    modifiers: Vec<String>,
+    minimum_ptx: &'static str,
+    minimum_sm: &'static str,
+    ptx_isa_section: &'static str,
+    ptx_isa_url: &'static str,
+}
+
+pub(in crate::resolve) fn canonical_extended_minmax_variants() -> Vec<ExtendedMinMaxVariant> {
+    use ExtendedMinMaxFormat::{Bf16, Bf16x2, F16, F16x2, F32};
+    use ExtendedMinMaxNan::{Nan, Number};
+    use ExtendedMinMaxOperation::{Max, Min};
+    use ExtendedMinMaxSubnormal::{Ftz, Preserve};
+
+    let one_operation = |operation| {
+        [
+            (F16x2, operation, Ftz, Number, false),
+            (F16x2, operation, Ftz, Nan, false),
+            (F32, operation, Ftz, Nan, true),
+            (F16x2, operation, Ftz, Nan, true),
+            (F32, operation, Ftz, Number, true),
+            (F16x2, operation, Ftz, Number, true),
+            (Bf16x2, operation, Preserve, Nan, false),
+            (F16x2, operation, Preserve, Nan, false),
+            (Bf16x2, operation, Preserve, Nan, true),
+            (F32, operation, Preserve, Nan, true),
+            (F16x2, operation, Preserve, Nan, true),
+            (Bf16x2, operation, Preserve, Number, true),
+            (F32, operation, Preserve, Number, true),
+            (F16x2, operation, Preserve, Number, true),
+        ]
+    };
+    // The scalar 16-bit forms. LLVM declares every `f16` modifier combination
+    // and the four `bf16` combinations that do not request `ftz`; the four
+    // `bf16` `ftz` declarations exist but have no NVPTX selection pattern and
+    // fail instruction selection, so they are deliberately absent here.
+    //
+    // ABI identity is intentionally absent from this canonical list. Existing
+    // and future IDs are carried by admission entries and enforced by the
+    // global append-only ABI ledger.
+    let scalar_halves = |operation| {
+        [
+            (F16, operation, Preserve, Number, false),
+            (F16, operation, Ftz, Number, false),
+            (F16, operation, Preserve, Nan, false),
+            (F16, operation, Ftz, Nan, false),
+            (F16, operation, Preserve, Number, true),
+            (F16, operation, Ftz, Number, true),
+            (F16, operation, Preserve, Nan, true),
+            (F16, operation, Ftz, Nan, true),
+            (Bf16, operation, Preserve, Number, false),
+            (Bf16, operation, Preserve, Nan, false),
+            (Bf16, operation, Preserve, Number, true),
+            (Bf16, operation, Preserve, Nan, true),
+        ]
+    };
+    one_operation(Min)
+        .into_iter()
+        .chain(one_operation(Max))
+        .chain(scalar_halves(Min))
+        .chain(scalar_halves(Max))
+        .collect()
+}
+
+/// Joins an operation name, its modifiers, and its format into one identifier.
+///
+/// `min.f16` and `min.bf16` carry no modifier at all, so the separators have to
+/// come from joining the parts that are present rather than from a format
+/// string with fixed separators.
+pub(in crate::resolve) fn extended_minmax_joined_name(
+    leading: &str,
+    trailing: &str,
+    modifiers: &[&str],
+    separator: &str,
+) -> String {
+    let mut parts = vec![leading];
+    parts.extend(modifiers.iter().copied());
+    parts.push(trailing);
+    parts.join(separator)
+}
+
+pub(in crate::resolve) fn extended_minmax_format_name(
+    format: ExtendedMinMaxFormat,
+) -> &'static str {
+    match format {
+        ExtendedMinMaxFormat::F32 => "f32",
+        ExtendedMinMaxFormat::F16 => "f16",
+        ExtendedMinMaxFormat::Bf16 => "bf16",
+        ExtendedMinMaxFormat::F16x2 => "f16x2",
+        ExtendedMinMaxFormat::Bf16x2 => "bf16x2",
+    }
+}
+
+pub(in crate::resolve) fn extended_minmax_operation_name(
+    operation: ExtendedMinMaxOperation,
+) -> &'static str {
+    match operation {
+        ExtendedMinMaxOperation::Min => "min",
+        ExtendedMinMaxOperation::Max => "max",
+    }
+}
+
+pub(in crate::resolve) fn extended_minmax_recipe(
+    variant: ExtendedMinMaxVariant,
+) -> Option<ExtendedMinMaxRecipe> {
+    if !canonical_extended_minmax_variants().contains(&variant) {
+        return None;
+    }
+    let (format, operation, subnormal, nan, xorsign_abs) = variant;
+    let operation_name = extended_minmax_operation_name(operation);
+    let format_name = extended_minmax_format_name(format);
+    let source_type = if format == ExtendedMinMaxFormat::F32 {
+        "f"
+    } else {
+        format_name
+    };
+    let mut source_modifiers = Vec::new();
+    let mut ptx_modifiers = Vec::new();
+    if subnormal == ExtendedMinMaxSubnormal::Ftz {
+        source_modifiers.push("ftz");
+        ptx_modifiers.push("ftz".to_owned());
+    }
+    if nan == ExtendedMinMaxNan::Nan {
+        source_modifiers.push("nan");
+        ptx_modifiers.push("NaN".to_owned());
+    }
+    if xorsign_abs {
+        source_modifiers.extend(["xorsign", "abs"]);
+        ptx_modifiers.extend(["xorsign".to_owned(), "abs".to_owned()]);
+    }
+    let id = extended_minmax_joined_name(operation_name, format_name, &source_modifiers, "_");
+    let intrinsic_name = format!("f{operation_name}");
+    let source_record = format!(
+        "int_nvvm_{}",
+        extended_minmax_joined_name(&intrinsic_name, source_type, &source_modifiers, "_")
+    );
+    let llvm_symbol = format!(
+        "llvm.nvvm.{}",
+        extended_minmax_joined_name(&intrinsic_name, source_type, &source_modifiers, ".")
+    );
+    let selection_record = if format == ExtendedMinMaxFormat::F32 {
+        format!(
+            "INT_NVVM_{}",
+            source_record
+                .trim_start_matches("int_nvvm_")
+                .to_ascii_uppercase()
+        )
+    } else {
+        let prefix = match operation {
+            ExtendedMinMaxOperation::Min => "FMIN",
+            ExtendedMinMaxOperation::Max => "FMAN",
+        };
+        let selection_modifiers = source_modifiers
+            .iter()
+            .map(|modifier| if *modifier == "nan" { "NaN" } else { modifier })
+            .collect::<Vec<_>>();
+        format!(
+            "INT_NVVM_{}",
+            extended_minmax_joined_name(prefix, format_name, &selection_modifiers, "_")
+        )
+    };
+    let ptx_format = if format == ExtendedMinMaxFormat::F32 {
+        "f32"
+    } else {
+        format_name
+    };
+    ptx_modifiers.push(ptx_format.to_owned());
+    let selection_asm = format!(
+        "{operation_name}.{} \t$dst, $src0, $src1;",
+        ptx_modifiers.join(".")
+    );
+    let (minimum_ptx, minimum_sm, predicates) = if xorsign_abs {
+        (
+            "7.2",
+            "sm_86",
+            vec![
+                "Subtarget->getPTXVersion() >= 72".to_owned(),
+                "Subtarget->getSmVersion() >= 86".to_owned(),
+            ],
+        )
+    } else {
+        (
+            "7.0",
+            "sm_80",
+            vec![
+                "Subtarget->getSmVersion() >= 80".to_owned(),
+                "Subtarget->getPTXVersion() >= 70".to_owned(),
+            ],
+        )
+    };
+    let (llvm_type, rust_module, rust_type, dialect_type, adapter, classes) = match format {
+        ExtendedMinMaxFormat::F32 => (
+            "f32",
+            "float",
+            "f32",
+            "f32",
+            ExtendedMinMaxAdapter::DirectF32,
+            vec![
+                "ClangBuiltin",
+                "NVVMBuiltin",
+                "SDPatternOperator",
+                "Intrinsic",
+                "DefaultAttrsIntrinsic",
+            ],
+        ),
+        ExtendedMinMaxFormat::F16 => (
+            "f16",
+            "f16",
+            "u16",
+            "i16",
+            ExtendedMinMaxAdapter::DirectHalfU16,
+            vec!["SDPatternOperator", "Intrinsic", "DefaultAttrsIntrinsic"],
+        ),
+        ExtendedMinMaxFormat::Bf16 => (
+            "bf16",
+            "bf16",
+            "u16",
+            "i16",
+            ExtendedMinMaxAdapter::DirectHalfU16,
+            vec![
+                "ClangBuiltin",
+                "NVVMBuiltin",
+                "SDPatternOperator",
+                "Intrinsic",
+                "DefaultAttrsIntrinsic",
+            ],
+        ),
+        ExtendedMinMaxFormat::F16x2 => (
+            "v2f16",
+            "f16x2",
+            "u32",
+            "i32",
+            ExtendedMinMaxAdapter::DirectPackedU32,
+            vec!["SDPatternOperator", "Intrinsic", "DefaultAttrsIntrinsic"],
+        ),
+        ExtendedMinMaxFormat::Bf16x2 => (
+            "v2bf16",
+            "bf16x2",
+            "u32",
+            "i32",
+            ExtendedMinMaxAdapter::DirectPackedU32,
+            vec![
+                "ClangBuiltin",
+                "NVVMBuiltin",
+                "SDPatternOperator",
+                "Intrinsic",
+                "DefaultAttrsIntrinsic",
+            ],
+        ),
+    };
+    let (ptx_isa_section, ptx_isa_url) = match (format, operation) {
+        (ExtendedMinMaxFormat::F32, ExtendedMinMaxOperation::Min) => (
+            "9.7.3.9 Floating Point Instructions: min",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-min",
+        ),
+        (ExtendedMinMaxFormat::F32, ExtendedMinMaxOperation::Max) => (
+            "9.7.3.10 Floating Point Instructions: max",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-max",
+        ),
+        (_, ExtendedMinMaxOperation::Min) => (
+            "9.7.4.7 Half Precision Floating Point Instructions: min",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-min",
+        ),
+        (_, ExtendedMinMaxOperation::Max) => (
+            "9.7.4.8 Half Precision Floating Point Instructions: max",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-max",
+        ),
+    };
+    Some(ExtendedMinMaxRecipe {
+        id,
+        operation_key: format!(
+            "floating.minmax.{format_name}.{operation_name}.{}.{}.{}",
+            match subnormal {
+                ExtendedMinMaxSubnormal::Preserve => "preserve",
+                ExtendedMinMaxSubnormal::Ftz => "ftz",
+            },
+            match nan {
+                ExtendedMinMaxNan::Number => "number",
+                ExtendedMinMaxNan::Nan => "nan",
+            },
+            if xorsign_abs { "xorsign_abs" } else { "direct" }
+        ),
+        source_record,
+        llvm_symbol,
+        llvm_type,
+        rust_module,
+        rust_type,
+        dialect_type,
+        adapter,
+        selection_record,
+        selection_asm,
+        predicates,
+        classes,
+        modifiers: ptx_modifiers,
+        minimum_ptx,
+        minimum_sm,
+        ptx_isa_section,
+        ptx_isa_url,
+    })
+}
+
+pub(in crate::resolve) fn expand_extended_minmax_admission(
+    admission: &ExtendedMinMaxAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "extended-minmax runtime may be marked executed only with GPU evidence"
+    );
+    let expected = canonical_extended_minmax_variants();
+    let actual = admission
+        .variants
+        .iter()
+        .map(|variant| {
+            (
+                variant.format,
+                variant.operation,
+                variant.subnormal,
+                variant.nan,
+                variant.xorsign_abs,
+            )
+        })
+        .collect::<Vec<_>>();
+    ensure!(
+        actual == expected,
+        "compact extended-minmax admission must list the exact canonical 28 variants"
+    );
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            validate_abi_id(&variant.abi_id)?;
+            let identity = (
+                variant.format,
+                variant.operation,
+                variant.subnormal,
+                variant.nan,
+                variant.xorsign_abs,
+            );
+            let recipe = extended_minmax_recipe(identity)
+                .context("extended min/max is outside the closed recipe set")?;
+            extended_minmax_overlay_record(recipe, admission, identity, &variant.abi_id)
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn extended_minmax_overlay_record(
+    recipe: ExtendedMinMaxRecipe,
+    admission: &ExtendedMinMaxAdmission,
+    variant: ExtendedMinMaxVariant,
+    abi_id: &str,
+) -> Result<OverlayIntrinsic> {
+    let (format, operation, subnormal, nan, xorsign_abs) = variant;
+    let rust_arguments = vec![recipe.rust_type.to_owned(); 2];
+    let dialect_operands = vec![recipe.dialect_type.to_owned(); 2];
+    Ok(OverlayIntrinsic {
+        id: recipe.id.clone(),
+        abi_id: abi_id.into(),
+        operation_key: recipe.operation_key,
+        family: "extended_minmax".into(),
+        source: None,
+        source_record: Some(recipe.source_record),
+        rust_module: recipe.rust_module.into(),
+        rust_name: recipe.id.clone(),
+        rust_arguments: rust_arguments.clone(),
+        rust_result: recipe.rust_type.into(),
+        safe: true,
+        must_use: true,
+        safe_allowlist_reason: Some("Floating-point min/max has no caller obligations.".into()),
+        public_rust_path: format!("cuda_intrinsics::{}::{}", recipe.rust_module, recipe.id),
+        compatibility_rust_paths: vec![format!(
+            "cuda_device::{}::{}",
+            recipe.rust_module, recipe.id
+        )],
+        dialect_op_type: "ExtendedMinMaxOp".into(),
+        dialect_op_name: "nvvm.extended_minmax".into(),
+        dialect_operands: dialect_operands.clone(),
+        dialect_results: vec![recipe.dialect_type.into()],
+        llvm_symbol: Some(recipe.llvm_symbol),
+        resolved_llvm_symbol: None,
+        llvm_arguments: vec![recipe.llvm_type.into(); 2],
+        llvm_results: vec![recipe.llvm_type.into()],
+        pure: true,
+        memory: "none".into(),
+        convergent: false,
+        execution_scope: "thread".into(),
+        minimum_ptx: recipe.minimum_ptx.into(),
+        minimum_sm: Some(recipe.minimum_sm.into()),
+        ptx_result: recipe.rust_type.into(),
+        targets: "all".into(),
+        ptx_isa_version: "9.3".into(),
+        ptx_isa_section: recipe.ptx_isa_section.into(),
+        ptx_isa_url: recipe.ptx_isa_url.into(),
+        lowering: "generated_extended_minmax".into(),
+        backend_lowerings: [
+            (
+                IntrinsicBackend::LlvmNvptx,
+                &admission.llvm_evidence_profile,
+            ),
+            (
+                IntrinsicBackend::LibNvvm,
+                &admission.libnvvm_evidence_profile,
+            ),
+        ]
+        .into_iter()
+        .map(|(backend, evidence_profile)| OverlayBackendLowering {
+            backend,
+            mechanism: BackendLoweringMechanism::InlinePtx,
+            evidence_profile: evidence_profile.clone(),
+            targets: None,
+            minimum_ptx: Some(recipe.minimum_ptx.into()),
+            minimum_sm: Some(recipe.minimum_sm.into()),
+        })
+        .collect(),
+        packed_atomic: None,
+        redux: None,
+        vote: None,
+        active_mask: None,
+        warp_match: None,
+        warp_barrier: None,
+        warp_shuffle: None,
+        dot_product: None,
+        packed_alu: None,
+        integer_minmax: None,
+        packed_conversion: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: Some(ExtendedMinMax {
+            format,
+            operation,
+            subnormal,
+            nan,
+            xorsign_abs,
+            adapter: recipe.adapter,
+            runtime_validation: admission.runtime_validation,
+        }),
+        cp_async_copy: None,
+        cp_async_control: None,
+        cp_async_mbarrier: None,
+        mbarrier_basic: None,
+        movmatrix: None,
+        mbarrier_extended: None,
+        register_mma: None,
+        sparse_mma: None,
+        prmt: None,
+        cluster_barrier: None,
+        wgmma_control: None,
+        special_register: None,
+        debug_control: None,
+        cluster_memory: None,
+        clc: None,
+        tma: None,
+        tcgen05: None,
+        ldmatrix_variant: None,
+        ldmatrix_safety: None,
+        ldmatrix_adapter: None,
+        selected_address_space: None,
+        expected_ptx: InstructionPattern {
+            mnemonic: extended_minmax_operation_name(operation).into(),
+            modifiers: recipe.modifiers,
+            operands: vec![OperandPattern::Register; 3],
+        },
+        summary: format!(
+            "Computes extended {} for {} values.",
+            extended_minmax_operation_name(operation),
+            extended_minmax_format_name(format)
+        ),
+    })
+}
+
+pub(in crate::resolve) fn validate_extended_minmax_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let minmax = policy
+        .extended_minmax
+        .as_ref()
+        .with_context(|| format!("{} has no extended-minmax contract", policy.id))?;
+    let identity = (
+        minmax.format,
+        minmax.operation,
+        minmax.subnormal,
+        minmax.nan,
+        minmax.xorsign_abs,
+    );
+    let recipe = extended_minmax_recipe(identity)
+        .with_context(|| format!("{} is outside the closed extended-minmax recipe", policy.id))?;
+    ensure!(
+        minmax.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} extended-minmax runtime may be executed only with GPU evidence",
+        policy.id
+    );
+    let expected_adapter = match minmax.format {
+        ExtendedMinMaxFormat::F32 => ExtendedMinMaxAdapter::DirectF32,
+        ExtendedMinMaxFormat::F16 | ExtendedMinMaxFormat::Bf16 => {
+            ExtendedMinMaxAdapter::DirectHalfU16
+        }
+        ExtendedMinMaxFormat::F16x2 | ExtendedMinMaxFormat::Bf16x2 => {
+            ExtendedMinMaxAdapter::DirectPackedU32
+        }
+    };
+    ensure!(
+        minmax.adapter == expected_adapter,
+        "{} extended-minmax adapter does not match its format",
+        policy.id
+    );
+    ensure!(
+        policy.id == recipe.id
+            && policy.operation_key == recipe.operation_key
+            && policy.source_record.as_deref() == Some(recipe.source_record.as_str())
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none()
+            && policy.llvm_arguments == vec![recipe.llvm_type; 2]
+            && policy.llvm_results == [recipe.llvm_type],
+        "{} extended-minmax identity or LLVM source changed",
+        policy.id
+    );
+    ensure!(
+        declaration.classes == recipe.classes
+            && declaration.properties == ["Commutative", "IntrNoMem", "IntrSpeculatable"]
+            && declaration.selections.len() == 1,
+        "{} imported extended-minmax classes, properties, or selection count changed",
+        policy.id
+    );
+    let selection = &declaration.selections[0];
+    ensure!(
+        selection.source_record == recipe.selection_record
+            && selection.asm == recipe.selection_asm
+            && selection.predicates == recipe.predicates
+            && selection.constraints.is_empty(),
+        "{} imported extended-minmax instruction selection changed",
+        policy.id
+    );
+    let rust_arguments = vec![recipe.rust_type; 2];
+    let dialect_operands = vec![recipe.dialect_type; 2];
+    ensure!(
+        policy.rust_module == recipe.rust_module
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == rust_arguments
+            && policy.rust_result == recipe.rust_type
+            && policy.safe
+            && policy.must_use
+            && policy.public_rust_path
+                == format!("cuda_intrinsics::{}::{}", recipe.rust_module, recipe.id)
+            && policy.compatibility_rust_paths
+                == [format!(
+                    "cuda_device::{}::{}",
+                    recipe.rust_module, recipe.id
+                )]
+            && policy.dialect_op_type == "ExtendedMinMaxOp"
+            && policy.dialect_op_name == "nvvm.extended_minmax"
+            && policy.dialect_operands == dialect_operands
+            && policy.dialect_results == [recipe.dialect_type]
+            && policy.lowering == "generated_extended_minmax",
+        "{} changed its extended-minmax API, carrier, or lowering",
+        policy.id
+    );
+    ensure!(
+        policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
+            && policy.ptx_result == recipe.rust_type
+            && policy.targets == "all"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.ptx_isa_section
+            && policy.ptx_isa_url == recipe.ptx_isa_url,
+        "{} extended-minmax effects, provenance, or target floor changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx
+            == InstructionPattern {
+                mnemonic: extended_minmax_operation_name(minmax.operation).into(),
+                modifiers: recipe.modifiers,
+                operands: vec![OperandPattern::Register; 3],
+            },
+        "{} expected extended-minmax PTX changed",
+        policy.id
+    );
+    ensure_exact_inline_ptx_backends(
+        policy,
+        [
+            (
+                IntrinsicBackend::LlvmNvptx,
+                recipe.minimum_ptx,
+                Some(recipe.minimum_sm),
+            ),
+            (
+                IntrinsicBackend::LibNvvm,
+                recipe.minimum_ptx,
+                Some(recipe.minimum_sm),
+            ),
+        ],
+        "extended-minmax",
+    )?;
+    validate_selected_target_predicates(policy, selection)?;
+    ensure_no_other_family_contract(policy, "extended min/max")?;
+    Ok(())
+}
+
+pub(in crate::resolve) struct IntegerMinMaxRecipe {
+    id: &'static str,
+    abi_id: &'static str,
+    operation_key: &'static str,
+    rust_module: &'static str,
+    rust_name: &'static str,
+    /// Rust and PTX carrier type: `i32` for the scalar forms, `u32` for the
+    /// packed pairs.
+    scalar: &'static str,
+    dialect_op_type: &'static str,
+    dialect_op_name: &'static str,
+    ptx_mnemonic: &'static str,
+    modifiers: &'static [&'static str],
+}
+
+/// Returns the closed recipe for an extended integer min/max variant.
+///
+/// `None` means the combination is outside the family: `.relu` exists only
+/// for the signed formats, and the plain scalar forms are ordinary codegen
+/// (`min.s32`/`max.s32` from generic Rust min/max), not intrinsics.
+pub(in crate::resolve) fn integer_minmax_recipe(
+    format: IntegerMinMaxFormat,
+    operation: IntegerMinMaxOperation,
+    relu: bool,
+) -> Option<IntegerMinMaxRecipe> {
+    use IntegerMinMaxFormat as Format;
+    use IntegerMinMaxOperation as Operation;
+    Some(match (format, operation, relu) {
+        (Format::S32, Operation::Min, true) => IntegerMinMaxRecipe {
+            id: "min_relu_s32",
+            abi_id: "i0987",
+            operation_key: "integer.minmax.s32.min.relu",
+            rust_module: "int",
+            rust_name: "min_relu_s32",
+            scalar: "i32",
+            dialect_op_type: "MinReluS32Op",
+            dialect_op_name: "nvvm.min_relu_s32",
+            ptx_mnemonic: "min.relu.s32",
+            modifiers: &["relu", "s32"],
+        },
+        (Format::S32, Operation::Max, true) => IntegerMinMaxRecipe {
+            id: "max_relu_s32",
+            abi_id: "i0988",
+            operation_key: "integer.minmax.s32.max.relu",
+            rust_module: "int",
+            rust_name: "max_relu_s32",
+            scalar: "i32",
+            dialect_op_type: "MaxReluS32Op",
+            dialect_op_name: "nvvm.max_relu_s32",
+            ptx_mnemonic: "max.relu.s32",
+            modifiers: &["relu", "s32"],
+        },
+        (Format::S16x2, Operation::Min, false) => IntegerMinMaxRecipe {
+            id: "min_s16x2",
+            abi_id: "i0989",
+            operation_key: "integer.minmax.s16x2.min",
+            rust_module: "i16x2",
+            rust_name: "min_s16x2",
+            scalar: "u32",
+            dialect_op_type: "MinS16x2Op",
+            dialect_op_name: "nvvm.min_s16x2",
+            ptx_mnemonic: "min.s16x2",
+            modifiers: &["s16x2"],
+        },
+        (Format::S16x2, Operation::Max, false) => IntegerMinMaxRecipe {
+            id: "max_s16x2",
+            abi_id: "i0990",
+            operation_key: "integer.minmax.s16x2.max",
+            rust_module: "i16x2",
+            rust_name: "max_s16x2",
+            scalar: "u32",
+            dialect_op_type: "MaxS16x2Op",
+            dialect_op_name: "nvvm.max_s16x2",
+            ptx_mnemonic: "max.s16x2",
+            modifiers: &["s16x2"],
+        },
+        (Format::U16x2, Operation::Min, false) => IntegerMinMaxRecipe {
+            id: "min_u16x2",
+            abi_id: "i0991",
+            operation_key: "integer.minmax.u16x2.min",
+            rust_module: "i16x2",
+            rust_name: "min_u16x2",
+            scalar: "u32",
+            dialect_op_type: "MinU16x2Op",
+            dialect_op_name: "nvvm.min_u16x2",
+            ptx_mnemonic: "min.u16x2",
+            modifiers: &["u16x2"],
+        },
+        (Format::U16x2, Operation::Max, false) => IntegerMinMaxRecipe {
+            id: "max_u16x2",
+            abi_id: "i0992",
+            operation_key: "integer.minmax.u16x2.max",
+            rust_module: "i16x2",
+            rust_name: "max_u16x2",
+            scalar: "u32",
+            dialect_op_type: "MaxU16x2Op",
+            dialect_op_name: "nvvm.max_u16x2",
+            ptx_mnemonic: "max.u16x2",
+            modifiers: &["u16x2"],
+        },
+        (Format::S16x2, Operation::Min, true) => IntegerMinMaxRecipe {
+            id: "min_relu_s16x2",
+            abi_id: "i0993",
+            operation_key: "integer.minmax.s16x2.min.relu",
+            rust_module: "i16x2",
+            rust_name: "min_relu_s16x2",
+            scalar: "u32",
+            dialect_op_type: "MinReluS16x2Op",
+            dialect_op_name: "nvvm.min_relu_s16x2",
+            ptx_mnemonic: "min.relu.s16x2",
+            modifiers: &["relu", "s16x2"],
+        },
+        (Format::S16x2, Operation::Max, true) => IntegerMinMaxRecipe {
+            id: "max_relu_s16x2",
+            abi_id: "i0994",
+            operation_key: "integer.minmax.s16x2.max.relu",
+            rust_module: "i16x2",
+            rust_name: "max_relu_s16x2",
+            scalar: "u32",
+            dialect_op_type: "MaxReluS16x2Op",
+            dialect_op_name: "nvvm.max_relu_s16x2",
+            ptx_mnemonic: "max.relu.s16x2",
+            modifiers: &["relu", "s16x2"],
+        },
+        (Format::S32, _, false) | (Format::U16x2, _, true) => return None,
+    })
+}
+
+pub(in crate::resolve) fn integer_minmax_isa_reference(
+    operation: IntegerMinMaxOperation,
+) -> (&'static str, &'static str) {
+    match operation {
+        IntegerMinMaxOperation::Min => (
+            "9.7.1.13 Integer Arithmetic Instructions: min",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#integer-arithmetic-instructions-min",
+        ),
+        IntegerMinMaxOperation::Max => (
+            "9.7.1.14 Integer Arithmetic Instructions: max",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#integer-arithmetic-instructions-max",
+        ),
+    }
+}
+
+pub(in crate::resolve) fn validate_integer_minmax_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+    declaration: Option<&ImportedIntrinsic>,
+) -> Result<()> {
+    let minmax = policy
+        .integer_minmax
+        .as_ref()
+        .with_context(|| format!("{} has no closed integer-min/max contract", policy.id))?;
+    let recipe = integer_minmax_recipe(minmax.format, minmax.operation, minmax.relu)
+        .with_context(|| format!("{} is outside the closed integer-min/max recipe", policy.id))?;
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key,
+        "{} integer-min/max identity does not match its closed operation recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == recipe.rust_module
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == [recipe.scalar, recipe.scalar]
+            && policy.rust_result == recipe.scalar
+            && policy.safe
+            && policy.must_use
+            && policy
+                .safe_allowlist_reason
+                .as_deref()
+                .is_some_and(|reason| !reason.trim().is_empty())
+            && policy.public_rust_path
+                == format!(
+                    "cuda_intrinsics::{}::{}",
+                    recipe.rust_module, recipe.rust_name
+                )
+            && policy.compatibility_rust_paths
+                == [format!(
+                    "cuda_device::{}::{}",
+                    recipe.rust_module, recipe.rust_name
+                )],
+        "{} must preserve its reviewed safe integer-min/max API",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == ["i32", "i32"]
+            && policy.dialect_results == ["i32"]
+            && policy.lowering == "generated_integer_minmax_inline_ptx",
+        "{} is outside the closed integer-min/max dialect and lowering recipe",
+        policy.id
+    );
+    ensure!(
+        policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == "8.0"
+            && policy.minimum_sm.as_deref() == Some("sm_90")
+            && policy.ptx_result == recipe.scalar
+            && policy.targets == "all"
+            && minmax.native_minimum_sm == 90,
+        "{} integer-min/max effects, carrier, or target floor disagree",
+        policy.id
+    );
+    let (isa_section, isa_url) = integer_minmax_isa_reference(minmax.operation);
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == isa_section
+            && policy.ptx_isa_url == isa_url,
+        "{} integer-min/max PTX provenance does not match its reviewed instruction section",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic
+            == recipe.ptx_mnemonic.split('.').next().expect("PTX mnemonic")
+            && policy.expected_ptx.modifiers == recipe.modifiers
+            && policy.expected_ptx.operands == vec![OperandPattern::Register; 3],
+        "{} expected PTX does not match its exact integer-min/max instruction",
+        policy.id
+    );
+    ensure!(
+        source
+            == &IntrinsicSource::PtxNative {
+                instruction: recipe.ptx_mnemonic.to_owned(),
+            }
+            && declaration.is_none(),
+        "{} integer-min/max source does not match its PTX-native recipe",
+        policy.id
+    );
+    ensure!(
+        policy.backend_lowerings.len() == 1
+            && policy.backend_lowerings[0].backend == IntrinsicBackend::LlvmNvptx
+            && policy.backend_lowerings[0].mechanism == BackendLoweringMechanism::InlinePtx
+            && policy.backend_lowerings[0].targets.is_none()
+            && policy.backend_lowerings[0].minimum_ptx.is_none()
+            && policy.backend_lowerings[0].minimum_sm.is_none()
+            && !policy.backend_lowerings[0]
+                .evidence_profile
+                .trim()
+                .is_empty(),
+        "{} integer-min/max backend route changed",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "integer_minmax")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/mma/mod.rs b/crates/cuda-intrinsics-gen/src/resolve/families/mma/mod.rs
new file mode 100644
index 0000000000..c4583a5153
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/mma/mod.rs
@@ -0,0 +1,14 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+pub(in crate::resolve) mod register;
+pub(in crate::resolve) mod register_admissions;
+pub(in crate::resolve) mod sparse;
+pub(in crate::resolve) mod validate;
+
+pub(in crate::resolve) use register::*;
+pub(in crate::resolve) use register_admissions::*;
+pub(in crate::resolve) use sparse::*;
+pub(in crate::resolve) use validate::*;
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/mma/register.rs b/crates/cuda-intrinsics-gen/src/resolve/families/mma/register.rs
new file mode 100644
index 0000000000..55b69af7ee
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/mma/register.rs
@@ -0,0 +1,1043 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    RegisterMma, RegisterMmaAccumulator, RegisterMmaAdapter, RegisterMmaCompatibilitySource,
+    RegisterMmaElement, RegisterMmaLayout, RegisterMmaOperation, RegisterMmaOverflow,
+    RegisterMmaParticipation, RegisterMmaShape,
+};
+
+pub(in crate::resolve) struct RegisterMmaRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) rust_arguments: &'static [&'static str],
+    pub(in crate::resolve) rust_result: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) dialect_operands: &'static [&'static str],
+    pub(in crate::resolve) dialect_results: &'static [&'static str],
+    pub(in crate::resolve) llvm_arguments: &'static [&'static str],
+    pub(in crate::resolve) llvm_results: &'static [&'static str],
+    pub(in crate::resolve) adapter: RegisterMmaAdapter,
+    pub(in crate::resolve) compatibility_source: RegisterMmaCompatibilitySource,
+    pub(in crate::resolve) minimum_ptx: &'static str,
+    pub(in crate::resolve) minimum_sm: &'static str,
+    pub(in crate::resolve) ptx_modifiers: Vec<&'static str>,
+    pub(in crate::resolve) ptx_register_counts: [usize; 4],
+}
+
+pub(in crate::resolve) fn integer_register_mma_recipe(
+    mma: &RegisterMma,
+    common: bool,
+) -> Option<RegisterMmaRecipe> {
+    use RegisterMmaAdapter::{
+        C2I32A1U32B1U32ToD2I32, C4I32A2U32B1U32ToD4I32, C4I32A4U32B2U32ToD4I32,
+    };
+    use RegisterMmaCompatibilitySource::{ExistingStub, GeneratedStub};
+    use RegisterMmaElement::{S4, S8, U4, U8};
+    use RegisterMmaOverflow::{Satfinite, Wrapping};
+    use RegisterMmaShape::{M8n8k16, M8n8k32, M16n8k16, M16n8k32, M16n8k64};
+
+    if !common
+        || mma.operation != RegisterMmaOperation::Multiply
+        || mma.accumulator != RegisterMmaAccumulator::S32
+    {
+        return None;
+    }
+
+    let (id, abi_id, operation_key, source_record, llvm_symbol, compatibility_source) =
+        match (mma.shape, mma.a_element, mma.b_element, mma.overflow) {
+            (M16n8k32, S8, S8, Wrapping) => (
+                "mma_m16n8k32_s32_s8",
+                "i0108",
+                "matrix.mma.m16n8k32.row.col.s32.s8.s8.s32.wrapping",
+                "int_nvvm_mma_m16n8k32_row_col_s8",
+                "llvm.nvvm.mma.m16n8k32.row.col.s8",
+                ExistingStub,
+            ),
+            (M16n8k16, S8, S8, Wrapping) => (
+                "mma_m16n8k16_s32_s8",
+                "i0110",
+                "matrix.mma.m16n8k16.row.col.s32.s8.s8.s32.wrapping",
+                "int_nvvm_mma_m16n8k16_row_col_s8",
+                "llvm.nvvm.mma.m16n8k16.row.col.s8",
+                GeneratedStub,
+            ),
+            (M16n8k16, S8, U8, Wrapping) => (
+                "mma_m16n8k16_s32_s8_u8",
+                "i0111",
+                "matrix.mma.m16n8k16.row.col.s32.s8.u8.s32.wrapping",
+                "int_nvvm_mma_m16n8k16_row_col_s8_u8",
+                "llvm.nvvm.mma.m16n8k16.row.col.s8.u8",
+                GeneratedStub,
+            ),
+            (M16n8k16, U8, U8, Wrapping) => (
+                "mma_m16n8k16_s32_u8",
+                "i0112",
+                "matrix.mma.m16n8k16.row.col.s32.u8.u8.s32.wrapping",
+                "int_nvvm_mma_m16n8k16_row_col_u8",
+                "llvm.nvvm.mma.m16n8k16.row.col.u8",
+                GeneratedStub,
+            ),
+            (M16n8k16, U8, S8, Wrapping) => (
+                "mma_m16n8k16_s32_u8_s8",
+                "i0113",
+                "matrix.mma.m16n8k16.row.col.s32.u8.s8.s32.wrapping",
+                "int_nvvm_mma_m16n8k16_row_col_u8_s8",
+                "llvm.nvvm.mma.m16n8k16.row.col.u8.s8",
+                GeneratedStub,
+            ),
+            (M16n8k32, S8, U8, Wrapping) => (
+                "mma_m16n8k32_s32_s8_u8",
+                "i0114",
+                "matrix.mma.m16n8k32.row.col.s32.s8.u8.s32.wrapping",
+                "int_nvvm_mma_m16n8k32_row_col_s8_u8",
+                "llvm.nvvm.mma.m16n8k32.row.col.s8.u8",
+                GeneratedStub,
+            ),
+            (M16n8k32, U8, U8, Wrapping) => (
+                "mma_m16n8k32_s32_u8",
+                "i0115",
+                "matrix.mma.m16n8k32.row.col.s32.u8.u8.s32.wrapping",
+                "int_nvvm_mma_m16n8k32_row_col_u8",
+                "llvm.nvvm.mma.m16n8k32.row.col.u8",
+                GeneratedStub,
+            ),
+            (M16n8k32, U8, S8, Wrapping) => (
+                "mma_m16n8k32_s32_u8_s8",
+                "i0116",
+                "matrix.mma.m16n8k32.row.col.s32.u8.s8.s32.wrapping",
+                "int_nvvm_mma_m16n8k32_row_col_u8_s8",
+                "llvm.nvvm.mma.m16n8k32.row.col.u8.s8",
+                GeneratedStub,
+            ),
+            (M16n8k16, S8, S8, Satfinite) => (
+                "mma_m16n8k16_s32_s8_satfinite",
+                "i0117",
+                "matrix.mma.m16n8k16.row.col.s32.s8.s8.s32.satfinite",
+                "int_nvvm_mma_m16n8k16_row_col_satfinite_s8",
+                "llvm.nvvm.mma.m16n8k16.row.col.satfinite.s8",
+                GeneratedStub,
+            ),
+            (M16n8k16, S8, U8, Satfinite) => (
+                "mma_m16n8k16_s32_s8_u8_satfinite",
+                "i0118",
+                "matrix.mma.m16n8k16.row.col.s32.s8.u8.s32.satfinite",
+                "int_nvvm_mma_m16n8k16_row_col_satfinite_s8_u8",
+                "llvm.nvvm.mma.m16n8k16.row.col.satfinite.s8.u8",
+                GeneratedStub,
+            ),
+            (M16n8k16, U8, U8, Satfinite) => (
+                "mma_m16n8k16_s32_u8_satfinite",
+                "i0119",
+                "matrix.mma.m16n8k16.row.col.s32.u8.u8.s32.satfinite",
+                "int_nvvm_mma_m16n8k16_row_col_satfinite_u8",
+                "llvm.nvvm.mma.m16n8k16.row.col.satfinite.u8",
+                GeneratedStub,
+            ),
+            (M16n8k16, U8, S8, Satfinite) => (
+                "mma_m16n8k16_s32_u8_s8_satfinite",
+                "i0120",
+                "matrix.mma.m16n8k16.row.col.s32.u8.s8.s32.satfinite",
+                "int_nvvm_mma_m16n8k16_row_col_satfinite_u8_s8",
+                "llvm.nvvm.mma.m16n8k16.row.col.satfinite.u8.s8",
+                GeneratedStub,
+            ),
+            (M16n8k32, S8, S8, Satfinite) => (
+                "mma_m16n8k32_s32_s8_satfinite",
+                "i0121",
+                "matrix.mma.m16n8k32.row.col.s32.s8.s8.s32.satfinite",
+                "int_nvvm_mma_m16n8k32_row_col_satfinite_s8",
+                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.s8",
+                GeneratedStub,
+            ),
+            (M16n8k32, S8, U8, Satfinite) => (
+                "mma_m16n8k32_s32_s8_u8_satfinite",
+                "i0122",
+                "matrix.mma.m16n8k32.row.col.s32.s8.u8.s32.satfinite",
+                "int_nvvm_mma_m16n8k32_row_col_satfinite_s8_u8",
+                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.s8.u8",
+                GeneratedStub,
+            ),
+            (M16n8k32, U8, U8, Satfinite) => (
+                "mma_m16n8k32_s32_u8_satfinite",
+                "i0123",
+                "matrix.mma.m16n8k32.row.col.s32.u8.u8.s32.satfinite",
+                "int_nvvm_mma_m16n8k32_row_col_satfinite_u8",
+                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.u8",
+                GeneratedStub,
+            ),
+            (M16n8k32, U8, S8, Satfinite) => (
+                "mma_m16n8k32_s32_u8_s8_satfinite",
+                "i0124",
+                "matrix.mma.m16n8k32.row.col.s32.u8.s8.s32.satfinite",
+                "int_nvvm_mma_m16n8k32_row_col_satfinite_u8_s8",
+                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.u8.s8",
+                GeneratedStub,
+            ),
+            (M8n8k16, S8, S8, Wrapping) => (
+                "mma_m8n8k16_s32_s8",
+                "i0125",
+                "matrix.mma.m8n8k16.row.col.s32.s8.s8.s32.wrapping",
+                "int_nvvm_mma_m8n8k16_row_col_s8",
+                "llvm.nvvm.mma.m8n8k16.row.col.s8",
+                GeneratedStub,
+            ),
+            (M8n8k16, S8, U8, Wrapping) => (
+                "mma_m8n8k16_s32_s8_u8",
+                "i0126",
+                "matrix.mma.m8n8k16.row.col.s32.s8.u8.s32.wrapping",
+                "int_nvvm_mma_m8n8k16_row_col_s8_u8",
+                "llvm.nvvm.mma.m8n8k16.row.col.s8.u8",
+                GeneratedStub,
+            ),
+            (M8n8k16, U8, U8, Wrapping) => (
+                "mma_m8n8k16_s32_u8",
+                "i0127",
+                "matrix.mma.m8n8k16.row.col.s32.u8.u8.s32.wrapping",
+                "int_nvvm_mma_m8n8k16_row_col_u8",
+                "llvm.nvvm.mma.m8n8k16.row.col.u8",
+                GeneratedStub,
+            ),
+            (M8n8k16, U8, S8, Wrapping) => (
+                "mma_m8n8k16_s32_u8_s8",
+                "i0128",
+                "matrix.mma.m8n8k16.row.col.s32.u8.s8.s32.wrapping",
+                "int_nvvm_mma_m8n8k16_row_col_u8_s8",
+                "llvm.nvvm.mma.m8n8k16.row.col.u8.s8",
+                GeneratedStub,
+            ),
+            (M8n8k16, S8, S8, Satfinite) => (
+                "mma_m8n8k16_s32_s8_satfinite",
+                "i0129",
+                "matrix.mma.m8n8k16.row.col.s32.s8.s8.s32.satfinite",
+                "int_nvvm_mma_m8n8k16_row_col_satfinite_s8",
+                "llvm.nvvm.mma.m8n8k16.row.col.satfinite.s8",
+                GeneratedStub,
+            ),
+            (M8n8k16, S8, U8, Satfinite) => (
+                "mma_m8n8k16_s32_s8_u8_satfinite",
+                "i0130",
+                "matrix.mma.m8n8k16.row.col.s32.s8.u8.s32.satfinite",
+                "int_nvvm_mma_m8n8k16_row_col_satfinite_s8_u8",
+                "llvm.nvvm.mma.m8n8k16.row.col.satfinite.s8.u8",
+                GeneratedStub,
+            ),
+            (M8n8k16, U8, U8, Satfinite) => (
+                "mma_m8n8k16_s32_u8_satfinite",
+                "i0131",
+                "matrix.mma.m8n8k16.row.col.s32.u8.u8.s32.satfinite",
+                "int_nvvm_mma_m8n8k16_row_col_satfinite_u8",
+                "llvm.nvvm.mma.m8n8k16.row.col.satfinite.u8",
+                GeneratedStub,
+            ),
+            (M8n8k16, U8, S8, Satfinite) => (
+                "mma_m8n8k16_s32_u8_s8_satfinite",
+                "i0132",
+                "matrix.mma.m8n8k16.row.col.s32.u8.s8.s32.satfinite",
+                "int_nvvm_mma_m8n8k16_row_col_satfinite_u8_s8",
+                "llvm.nvvm.mma.m8n8k16.row.col.satfinite.u8.s8",
+                GeneratedStub,
+            ),
+            (M8n8k32, S4, S4, Wrapping) => (
+                "mma_m8n8k32_s32_s4",
+                "i0133",
+                "matrix.mma.m8n8k32.row.col.s32.s4.s4.s32.wrapping",
+                "int_nvvm_mma_m8n8k32_row_col_s4",
+                "llvm.nvvm.mma.m8n8k32.row.col.s4",
+                GeneratedStub,
+            ),
+            (M8n8k32, S4, U4, Wrapping) => (
+                "mma_m8n8k32_s32_s4_u4",
+                "i0134",
+                "matrix.mma.m8n8k32.row.col.s32.s4.u4.s32.wrapping",
+                "int_nvvm_mma_m8n8k32_row_col_s4_u4",
+                "llvm.nvvm.mma.m8n8k32.row.col.s4.u4",
+                GeneratedStub,
+            ),
+            (M8n8k32, U4, U4, Wrapping) => (
+                "mma_m8n8k32_s32_u4",
+                "i0135",
+                "matrix.mma.m8n8k32.row.col.s32.u4.u4.s32.wrapping",
+                "int_nvvm_mma_m8n8k32_row_col_u4",
+                "llvm.nvvm.mma.m8n8k32.row.col.u4",
+                GeneratedStub,
+            ),
+            (M8n8k32, U4, S4, Wrapping) => (
+                "mma_m8n8k32_s32_u4_s4",
+                "i0136",
+                "matrix.mma.m8n8k32.row.col.s32.u4.s4.s32.wrapping",
+                "int_nvvm_mma_m8n8k32_row_col_u4_s4",
+                "llvm.nvvm.mma.m8n8k32.row.col.u4.s4",
+                GeneratedStub,
+            ),
+            (M8n8k32, S4, S4, Satfinite) => (
+                "mma_m8n8k32_s32_s4_satfinite",
+                "i0137",
+                "matrix.mma.m8n8k32.row.col.s32.s4.s4.s32.satfinite",
+                "int_nvvm_mma_m8n8k32_row_col_satfinite_s4",
+                "llvm.nvvm.mma.m8n8k32.row.col.satfinite.s4",
+                GeneratedStub,
+            ),
+            (M8n8k32, S4, U4, Satfinite) => (
+                "mma_m8n8k32_s32_s4_u4_satfinite",
+                "i0138",
+                "matrix.mma.m8n8k32.row.col.s32.s4.u4.s32.satfinite",
+                "int_nvvm_mma_m8n8k32_row_col_satfinite_s4_u4",
+                "llvm.nvvm.mma.m8n8k32.row.col.satfinite.s4.u4",
+                GeneratedStub,
+            ),
+            (M8n8k32, U4, U4, Satfinite) => (
+                "mma_m8n8k32_s32_u4_satfinite",
+                "i0139",
+                "matrix.mma.m8n8k32.row.col.s32.u4.u4.s32.satfinite",
+                "int_nvvm_mma_m8n8k32_row_col_satfinite_u4",
+                "llvm.nvvm.mma.m8n8k32.row.col.satfinite.u4",
+                GeneratedStub,
+            ),
+            (M8n8k32, U4, S4, Satfinite) => (
+                "mma_m8n8k32_s32_u4_s4_satfinite",
+                "i0140",
+                "matrix.mma.m8n8k32.row.col.s32.u4.s4.s32.satfinite",
+                "int_nvvm_mma_m8n8k32_row_col_satfinite_u4_s4",
+                "llvm.nvvm.mma.m8n8k32.row.col.satfinite.u4.s4",
+                GeneratedStub,
+            ),
+            (M16n8k32, S4, S4, Wrapping) => (
+                "mma_m16n8k32_s32_s4",
+                "i0141",
+                "matrix.mma.m16n8k32.row.col.s32.s4.s4.s32.wrapping",
+                "int_nvvm_mma_m16n8k32_row_col_s4",
+                "llvm.nvvm.mma.m16n8k32.row.col.s4",
+                GeneratedStub,
+            ),
+            (M16n8k32, S4, U4, Wrapping) => (
+                "mma_m16n8k32_s32_s4_u4",
+                "i0142",
+                "matrix.mma.m16n8k32.row.col.s32.s4.u4.s32.wrapping",
+                "int_nvvm_mma_m16n8k32_row_col_s4_u4",
+                "llvm.nvvm.mma.m16n8k32.row.col.s4.u4",
+                GeneratedStub,
+            ),
+            (M16n8k32, U4, U4, Wrapping) => (
+                "mma_m16n8k32_s32_u4",
+                "i0143",
+                "matrix.mma.m16n8k32.row.col.s32.u4.u4.s32.wrapping",
+                "int_nvvm_mma_m16n8k32_row_col_u4",
+                "llvm.nvvm.mma.m16n8k32.row.col.u4",
+                GeneratedStub,
+            ),
+            (M16n8k32, U4, S4, Wrapping) => (
+                "mma_m16n8k32_s32_u4_s4",
+                "i0144",
+                "matrix.mma.m16n8k32.row.col.s32.u4.s4.s32.wrapping",
+                "int_nvvm_mma_m16n8k32_row_col_u4_s4",
+                "llvm.nvvm.mma.m16n8k32.row.col.u4.s4",
+                GeneratedStub,
+            ),
+            (M16n8k64, S4, S4, Wrapping) => (
+                "mma_m16n8k64_s32_s4",
+                "i0145",
+                "matrix.mma.m16n8k64.row.col.s32.s4.s4.s32.wrapping",
+                "int_nvvm_mma_m16n8k64_row_col_s4",
+                "llvm.nvvm.mma.m16n8k64.row.col.s4",
+                GeneratedStub,
+            ),
+            (M16n8k64, S4, U4, Wrapping) => (
+                "mma_m16n8k64_s32_s4_u4",
+                "i0146",
+                "matrix.mma.m16n8k64.row.col.s32.s4.u4.s32.wrapping",
+                "int_nvvm_mma_m16n8k64_row_col_s4_u4",
+                "llvm.nvvm.mma.m16n8k64.row.col.s4.u4",
+                GeneratedStub,
+            ),
+            (M16n8k64, U4, U4, Wrapping) => (
+                "mma_m16n8k64_s32_u4",
+                "i0147",
+                "matrix.mma.m16n8k64.row.col.s32.u4.u4.s32.wrapping",
+                "int_nvvm_mma_m16n8k64_row_col_u4",
+                "llvm.nvvm.mma.m16n8k64.row.col.u4",
+                GeneratedStub,
+            ),
+            (M16n8k64, U4, S4, Wrapping) => (
+                "mma_m16n8k64_s32_u4_s4",
+                "i0148",
+                "matrix.mma.m16n8k64.row.col.s32.u4.s4.s32.wrapping",
+                "int_nvvm_mma_m16n8k64_row_col_u4_s4",
+                "llvm.nvvm.mma.m16n8k64.row.col.u4.s4",
+                GeneratedStub,
+            ),
+            (M16n8k32, S4, S4, Satfinite) => (
+                "mma_m16n8k32_s32_s4_satfinite",
+                "i0149",
+                "matrix.mma.m16n8k32.row.col.s32.s4.s4.s32.satfinite",
+                "int_nvvm_mma_m16n8k32_row_col_satfinite_s4",
+                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.s4",
+                GeneratedStub,
+            ),
+            (M16n8k32, S4, U4, Satfinite) => (
+                "mma_m16n8k32_s32_s4_u4_satfinite",
+                "i0150",
+                "matrix.mma.m16n8k32.row.col.s32.s4.u4.s32.satfinite",
+                "int_nvvm_mma_m16n8k32_row_col_satfinite_s4_u4",
+                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.s4.u4",
+                GeneratedStub,
+            ),
+            (M16n8k32, U4, U4, Satfinite) => (
+                "mma_m16n8k32_s32_u4_satfinite",
+                "i0151",
+                "matrix.mma.m16n8k32.row.col.s32.u4.u4.s32.satfinite",
+                "int_nvvm_mma_m16n8k32_row_col_satfinite_u4",
+                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.u4",
+                GeneratedStub,
+            ),
+            (M16n8k32, U4, S4, Satfinite) => (
+                "mma_m16n8k32_s32_u4_s4_satfinite",
+                "i0152",
+                "matrix.mma.m16n8k32.row.col.s32.u4.s4.s32.satfinite",
+                "int_nvvm_mma_m16n8k32_row_col_satfinite_u4_s4",
+                "llvm.nvvm.mma.m16n8k32.row.col.satfinite.u4.s4",
+                GeneratedStub,
+            ),
+            (M16n8k64, S4, S4, Satfinite) => (
+                "mma_m16n8k64_s32_s4_satfinite",
+                "i0153",
+                "matrix.mma.m16n8k64.row.col.s32.s4.s4.s32.satfinite",
+                "int_nvvm_mma_m16n8k64_row_col_satfinite_s4",
+                "llvm.nvvm.mma.m16n8k64.row.col.satfinite.s4",
+                GeneratedStub,
+            ),
+            (M16n8k64, S4, U4, Satfinite) => (
+                "mma_m16n8k64_s32_s4_u4_satfinite",
+                "i0154",
+                "matrix.mma.m16n8k64.row.col.s32.s4.u4.s32.satfinite",
+                "int_nvvm_mma_m16n8k64_row_col_satfinite_s4_u4",
+                "llvm.nvvm.mma.m16n8k64.row.col.satfinite.s4.u4",
+                GeneratedStub,
+            ),
+            (M16n8k64, U4, U4, Satfinite) => (
+                "mma_m16n8k64_s32_u4_satfinite",
+                "i0155",
+                "matrix.mma.m16n8k64.row.col.s32.u4.u4.s32.satfinite",
+                "int_nvvm_mma_m16n8k64_row_col_satfinite_u4",
+                "llvm.nvvm.mma.m16n8k64.row.col.satfinite.u4",
+                GeneratedStub,
+            ),
+            (M16n8k64, U4, S4, Satfinite) => (
+                "mma_m16n8k64_s32_u4_s4_satfinite",
+                "i0156",
+                "matrix.mma.m16n8k64.row.col.s32.u4.s4.s32.satfinite",
+                "int_nvvm_mma_m16n8k64_row_col_satfinite_u4_s4",
+                "llvm.nvvm.mma.m16n8k64.row.col.satfinite.u4.s4",
+                GeneratedStub,
+            ),
+            _ => return None,
+        };
+
+    let int4 = matches!(mma.a_element, S4 | U4);
+    let (rust_arguments, dialect_operands, llvm_arguments, adapter, shape, register_counts) =
+        match (mma.shape, int4) {
+            (M8n8k16, false) | (M8n8k32, true) => (
+                &["[i32; 2]", "u32", "u32"] as &'static [&'static str],
+                &["i32", "i32", "i32", "i32"] as &'static [&'static str],
+                &["i32", "i32", "i32", "i32"] as &'static [&'static str],
+                C2I32A1U32B1U32ToD2I32,
+                match mma.shape {
+                    M8n8k16 => "m8n8k16",
+                    M8n8k32 => "m8n8k32",
+                    _ => unreachable!(),
+                },
+                [2, 1, 1, 2],
+            ),
+            (M16n8k16, false) | (M16n8k32, true) => (
+                &["[i32; 4]", "[u32; 2]", "u32"] as &'static [&'static str],
+                &["i32", "i32", "i32", "i32", "i32", "i32", "i32"] as &'static [&'static str],
+                &["i32", "i32", "i32", "i32", "i32", "i32", "i32"] as &'static [&'static str],
+                C4I32A2U32B1U32ToD4I32,
+                match mma.shape {
+                    M16n8k16 => "m16n8k16",
+                    M16n8k32 => "m16n8k32",
+                    _ => unreachable!(),
+                },
+                [4, 2, 1, 4],
+            ),
+            (M16n8k32, false) | (M16n8k64, true) => (
+                &["[i32; 4]", "[u32; 4]", "[u32; 2]"] as &'static [&'static str],
+                &[
+                    "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32",
+                ] as &'static [&'static str],
+                &[
+                    "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32",
+                ] as &'static [&'static str],
+                C4I32A4U32B2U32ToD4I32,
+                match mma.shape {
+                    M16n8k32 => "m16n8k32",
+                    M16n8k64 => "m16n8k64",
+                    _ => unreachable!(),
+                },
+                [4, 4, 2, 4],
+            ),
+            _ => return None,
+        };
+    if mma.adapter != adapter {
+        return None;
+    }
+
+    let (rust_result, dialect_results, llvm_results, minimum_ptx, minimum_sm) = match mma.shape {
+        M8n8k16 | M8n8k32 => (
+            "[i32; 2]",
+            &["i32", "i32"] as &'static [&'static str],
+            &["i32", "i32"] as &'static [&'static str],
+            "6.5",
+            "sm_75",
+        ),
+        M16n8k16 | M16n8k32 | M16n8k64 => (
+            "[i32; 4]",
+            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
+            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
+            "7.0",
+            "sm_80",
+        ),
+        _ => return None,
+    };
+
+    let element = |element| match element {
+        S4 => Some("s4"),
+        U4 => Some("u4"),
+        S8 => Some("s8"),
+        U8 => Some("u8"),
+        _ => None,
+    };
+    let mut ptx_modifiers = vec!["sync", "aligned", shape, "row", "col"];
+    if mma.overflow == Satfinite {
+        ptx_modifiers.push("satfinite");
+    }
+    ptx_modifiers.extend([
+        "s32",
+        element(mma.a_element)?,
+        element(mma.b_element)?,
+        "s32",
+    ]);
+
+    Some(RegisterMmaRecipe {
+        id,
+        abi_id,
+        operation_key,
+        source_record,
+        llvm_symbol,
+        rust_arguments,
+        rust_result,
+        dialect_op_type: "RegisterMmaOp",
+        dialect_op_name: "nvvm.register_mma",
+        dialect_operands,
+        dialect_results,
+        llvm_arguments,
+        llvm_results,
+        adapter,
+        compatibility_source,
+        minimum_ptx,
+        minimum_sm,
+        ptx_modifiers,
+        ptx_register_counts: register_counts,
+    })
+}
+
+pub(in crate::resolve) fn binary_register_mma_recipe(
+    mma: &RegisterMma,
+    common: bool,
+) -> Option<RegisterMmaRecipe> {
+    use RegisterMmaAdapter::{
+        C2I32A1U32B1U32ToD2I32, C4I32A2U32B1U32ToD4I32, C4I32A4U32B2U32ToD4I32,
+    };
+    use RegisterMmaOperation::{AndPopc, XorPopc};
+    use RegisterMmaShape::{M8n8k128, M16n8k128, M16n8k256};
+
+    if !common
+        || mma.accumulator != RegisterMmaAccumulator::S32
+        || mma.a_element != RegisterMmaElement::B1
+        || mma.b_element != RegisterMmaElement::B1
+        || mma.overflow != RegisterMmaOverflow::Wrapping
+        || mma.compatibility_source != RegisterMmaCompatibilitySource::GeneratedStub
+    {
+        return None;
+    }
+
+    let (id, abi_id, operation_key, source_record, llvm_symbol, operation_name) =
+        match (mma.shape, mma.operation) {
+            (M8n8k128, XorPopc) => (
+                "mma_m8n8k128_s32_b1_xor_popc",
+                "i0157",
+                "matrix.mma.m8n8k128.row.col.s32.b1.b1.s32.xor.popc",
+                "int_nvvm_mma_xor_popc_m8n8k128_row_col_b1",
+                "llvm.nvvm.mma.xor.popc.m8n8k128.row.col.b1",
+                "xor",
+            ),
+            (M16n8k128, XorPopc) => (
+                "mma_m16n8k128_s32_b1_xor_popc",
+                "i0158",
+                "matrix.mma.m16n8k128.row.col.s32.b1.b1.s32.xor.popc",
+                "int_nvvm_mma_xor_popc_m16n8k128_row_col_b1",
+                "llvm.nvvm.mma.xor.popc.m16n8k128.row.col.b1",
+                "xor",
+            ),
+            (M16n8k256, XorPopc) => (
+                "mma_m16n8k256_s32_b1_xor_popc",
+                "i0159",
+                "matrix.mma.m16n8k256.row.col.s32.b1.b1.s32.xor.popc",
+                "int_nvvm_mma_xor_popc_m16n8k256_row_col_b1",
+                "llvm.nvvm.mma.xor.popc.m16n8k256.row.col.b1",
+                "xor",
+            ),
+            (M8n8k128, AndPopc) => (
+                "mma_m8n8k128_s32_b1_and_popc",
+                "i0160",
+                "matrix.mma.m8n8k128.row.col.s32.b1.b1.s32.and.popc",
+                "int_nvvm_mma_and_popc_m8n8k128_row_col_b1",
+                "llvm.nvvm.mma.and.popc.m8n8k128.row.col.b1",
+                "and",
+            ),
+            (M16n8k128, AndPopc) => (
+                "mma_m16n8k128_s32_b1_and_popc",
+                "i0161",
+                "matrix.mma.m16n8k128.row.col.s32.b1.b1.s32.and.popc",
+                "int_nvvm_mma_and_popc_m16n8k128_row_col_b1",
+                "llvm.nvvm.mma.and.popc.m16n8k128.row.col.b1",
+                "and",
+            ),
+            (M16n8k256, AndPopc) => (
+                "mma_m16n8k256_s32_b1_and_popc",
+                "i0162",
+                "matrix.mma.m16n8k256.row.col.s32.b1.b1.s32.and.popc",
+                "int_nvvm_mma_and_popc_m16n8k256_row_col_b1",
+                "llvm.nvvm.mma.and.popc.m16n8k256.row.col.b1",
+                "and",
+            ),
+            _ => return None,
+        };
+
+    let (
+        rust_arguments,
+        dialect_operands,
+        llvm_arguments,
+        rust_result,
+        result_types,
+        adapter,
+        counts,
+    ) = match mma.shape {
+        M8n8k128 => (
+            &["[i32; 2]", "u32", "u32"] as &'static [&'static str],
+            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
+            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
+            "[i32; 2]",
+            &["i32", "i32"] as &'static [&'static str],
+            C2I32A1U32B1U32ToD2I32,
+            [2, 1, 1, 2],
+        ),
+        M16n8k128 => (
+            &["[i32; 4]", "[u32; 2]", "u32"] as &'static [&'static str],
+            &["i32", "i32", "i32", "i32", "i32", "i32", "i32"] as &'static [&'static str],
+            &["i32", "i32", "i32", "i32", "i32", "i32", "i32"] as &'static [&'static str],
+            "[i32; 4]",
+            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
+            C4I32A2U32B1U32ToD4I32,
+            [4, 2, 1, 4],
+        ),
+        M16n8k256 => (
+            &["[i32; 4]", "[u32; 4]", "[u32; 2]"] as &'static [&'static str],
+            &[
+                "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32",
+            ] as &'static [&'static str],
+            &[
+                "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32",
+            ] as &'static [&'static str],
+            "[i32; 4]",
+            &["i32", "i32", "i32", "i32"] as &'static [&'static str],
+            C4I32A4U32B2U32ToD4I32,
+            [4, 4, 2, 4],
+        ),
+        _ => return None,
+    };
+    if mma.adapter != adapter {
+        return None;
+    }
+
+    let (minimum_ptx, minimum_sm) = match (mma.operation, mma.shape) {
+        (XorPopc, M8n8k128) => ("7.0", "sm_75"),
+        (XorPopc, M16n8k128 | M16n8k256) => ("7.0", "sm_80"),
+        (AndPopc, M8n8k128 | M16n8k128 | M16n8k256) => ("7.1", "sm_80"),
+        _ => return None,
+    };
+    let shape = match mma.shape {
+        M8n8k128 => "m8n8k128",
+        M16n8k128 => "m16n8k128",
+        M16n8k256 => "m16n8k256",
+        _ => return None,
+    };
+
+    Some(RegisterMmaRecipe {
+        id,
+        abi_id,
+        operation_key,
+        source_record,
+        llvm_symbol,
+        rust_arguments,
+        rust_result,
+        dialect_op_type: "RegisterMmaOp",
+        dialect_op_name: "nvvm.register_mma",
+        dialect_operands,
+        dialect_results: result_types,
+        llvm_arguments,
+        llvm_results: result_types,
+        adapter,
+        compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+        minimum_ptx,
+        minimum_sm,
+        ptx_modifiers: vec![
+            "sync",
+            "aligned",
+            shape,
+            "row",
+            "col",
+            "s32",
+            "b1",
+            "b1",
+            "s32",
+            operation_name,
+            "popc",
+        ],
+        ptx_register_counts: counts,
+    })
+}
+
+pub(in crate::resolve) fn register_mma_recipe(mma: &RegisterMma) -> Option<RegisterMmaRecipe> {
+    use RegisterMmaAccumulator::{F16 as F16Accumulator, F32, F64};
+    use RegisterMmaAdapter::{
+        C2F64A1F64B1F64ToD2F64, C2U32A2U32B1U32ToD2U32, C2U32A4U32B2U32ToD2U32,
+        C4F32A2U32B1U32ToD4F32, C4F32A4U32B2U32ToD4F32,
+    };
+    use RegisterMmaElement::{Bf16, F16 as F16Element, F64 as F64Element, Tf32};
+    use RegisterMmaShape::{M8n8k4, M16n8k4, M16n8k8, M16n8k16};
+
+    let common = mma.a_layout == RegisterMmaLayout::Row
+        && mma.b_layout == RegisterMmaLayout::Col
+        && mma.participation
+            == RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes;
+    if let Some(recipe) = integer_register_mma_recipe(mma, common) {
+        return Some(recipe);
+    }
+    if let Some(recipe) = binary_register_mma_recipe(mma, common) {
+        return Some(recipe);
+    }
+    if mma.operation != RegisterMmaOperation::Multiply {
+        return None;
+    }
+    match (
+        mma.shape,
+        mma.accumulator,
+        mma.a_element,
+        mma.b_element,
+        mma.overflow,
+        mma.adapter,
+        common,
+    ) {
+        (
+            M16n8k4,
+            F32,
+            Tf32,
+            Tf32,
+            RegisterMmaOverflow::NotApplicable,
+            C4F32A2U32B1U32ToD4F32,
+            true,
+        ) => Some(RegisterMmaRecipe {
+            id: "mma_m16n8k4_f32_tf32",
+            abi_id: "i0520",
+            operation_key: "matrix.mma.m16n8k4.row.col.f32.tf32.tf32.f32",
+            source_record: "int_nvvm_mma_m16n8k4_row_col_tf32",
+            llvm_symbol: "llvm.nvvm.mma.m16n8k4.row.col.tf32",
+            rust_arguments: &["[f32; 4]", "[u32; 2]", "u32"],
+            rust_result: "[f32; 4]",
+            dialect_op_type: "RegisterMmaOp",
+            dialect_op_name: "nvvm.register_mma",
+            dialect_operands: &["f32", "f32", "f32", "f32", "i32", "i32", "i32"],
+            dialect_results: &["f32", "f32", "f32", "f32"],
+            llvm_arguments: &["i32", "i32", "i32", "f32", "f32", "f32", "f32"],
+            llvm_results: &["f32", "f32", "f32", "f32"],
+            adapter: C4F32A2U32B1U32ToD4F32,
+            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_modifiers: vec![
+                "sync", "aligned", "m16n8k4", "row", "col", "f32", "tf32", "tf32", "f32",
+            ],
+            ptx_register_counts: [4, 2, 1, 4],
+        }),
+        (
+            M16n8k8,
+            F16Accumulator,
+            F16Element,
+            F16Element,
+            RegisterMmaOverflow::NotApplicable,
+            C2U32A2U32B1U32ToD2U32,
+            true,
+        ) => Some(RegisterMmaRecipe {
+            id: "mma_m16n8k8_f16_f16",
+            abi_id: "i0521",
+            operation_key: "matrix.mma.m16n8k8.row.col.f16.f16.f16.f16",
+            source_record: "int_nvvm_mma_m16n8k8_row_col_f16_f16",
+            llvm_symbol: "llvm.nvvm.mma.m16n8k8.row.col.f16.f16",
+            rust_arguments: &["[u32; 2]", "[u32; 2]", "u32"],
+            rust_result: "[u32; 2]",
+            dialect_op_type: "RegisterMmaOp",
+            dialect_op_name: "nvvm.register_mma",
+            dialect_operands: &["i32", "i32", "i32", "i32", "i32"],
+            dialect_results: &["i32", "i32"],
+            llvm_arguments: &["v2f16", "v2f16", "v2f16", "v2f16", "v2f16"],
+            llvm_results: &["v2f16", "v2f16"],
+            adapter: C2U32A2U32B1U32ToD2U32,
+            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_modifiers: vec![
+                "sync", "aligned", "m16n8k8", "row", "col", "f16", "f16", "f16", "f16",
+            ],
+            ptx_register_counts: [2, 2, 1, 2],
+        }),
+        (
+            M16n8k8,
+            F32,
+            Bf16,
+            Bf16,
+            RegisterMmaOverflow::NotApplicable,
+            C4F32A2U32B1U32ToD4F32,
+            true,
+        ) => Some(RegisterMmaRecipe {
+            id: "mma_m16n8k8_f32_bf16",
+            abi_id: "i0522",
+            operation_key: "matrix.mma.m16n8k8.row.col.f32.bf16.bf16.f32",
+            source_record: "int_nvvm_mma_m16n8k8_row_col_bf16",
+            llvm_symbol: "llvm.nvvm.mma.m16n8k8.row.col.bf16",
+            rust_arguments: &["[f32; 4]", "[u32; 2]", "u32"],
+            rust_result: "[f32; 4]",
+            dialect_op_type: "RegisterMmaOp",
+            dialect_op_name: "nvvm.register_mma",
+            dialect_operands: &["f32", "f32", "f32", "f32", "i32", "i32", "i32"],
+            dialect_results: &["f32", "f32", "f32", "f32"],
+            llvm_arguments: &["i32", "i32", "i32", "f32", "f32", "f32", "f32"],
+            llvm_results: &["f32", "f32", "f32", "f32"],
+            adapter: C4F32A2U32B1U32ToD4F32,
+            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_modifiers: vec![
+                "sync", "aligned", "m16n8k8", "row", "col", "f32", "bf16", "bf16", "f32",
+            ],
+            ptx_register_counts: [4, 2, 1, 4],
+        }),
+        (
+            M16n8k8,
+            F32,
+            F16Element,
+            F16Element,
+            RegisterMmaOverflow::NotApplicable,
+            C4F32A2U32B1U32ToD4F32,
+            true,
+        ) => Some(RegisterMmaRecipe {
+            id: "mma_m16n8k8_f32_f16",
+            abi_id: "i0523",
+            operation_key: "matrix.mma.m16n8k8.row.col.f32.f16.f16.f32",
+            source_record: "int_nvvm_mma_m16n8k8_row_col_f32_f32",
+            llvm_symbol: "llvm.nvvm.mma.m16n8k8.row.col.f32.f32",
+            rust_arguments: &["[f32; 4]", "[u32; 2]", "u32"],
+            rust_result: "[f32; 4]",
+            dialect_op_type: "RegisterMmaOp",
+            dialect_op_name: "nvvm.register_mma",
+            dialect_operands: &["f32", "f32", "f32", "f32", "i32", "i32", "i32"],
+            dialect_results: &["f32", "f32", "f32", "f32"],
+            llvm_arguments: &["v2f16", "v2f16", "v2f16", "f32", "f32", "f32", "f32"],
+            llvm_results: &["f32", "f32", "f32", "f32"],
+            adapter: C4F32A2U32B1U32ToD4F32,
+            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_modifiers: vec![
+                "sync", "aligned", "m16n8k8", "row", "col", "f32", "f16", "f16", "f32",
+            ],
+            ptx_register_counts: [4, 2, 1, 4],
+        }),
+        (
+            M16n8k16,
+            F16Accumulator,
+            F16Element,
+            F16Element,
+            RegisterMmaOverflow::NotApplicable,
+            C2U32A4U32B2U32ToD2U32,
+            true,
+        ) => Some(RegisterMmaRecipe {
+            id: "mma_m16n8k16_f16_f16",
+            abi_id: "i0524",
+            operation_key: "matrix.mma.m16n8k16.row.col.f16.f16.f16.f16",
+            source_record: "int_nvvm_mma_m16n8k16_row_col_f16_f16",
+            llvm_symbol: "llvm.nvvm.mma.m16n8k16.row.col.f16.f16",
+            rust_arguments: &["[u32; 2]", "[u32; 4]", "[u32; 2]"],
+            rust_result: "[u32; 2]",
+            dialect_op_type: "RegisterMmaOp",
+            dialect_op_name: "nvvm.register_mma",
+            dialect_operands: &["i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32"],
+            dialect_results: &["i32", "i32"],
+            llvm_arguments: &[
+                "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16",
+            ],
+            llvm_results: &["v2f16", "v2f16"],
+            adapter: C2U32A4U32B2U32ToD2U32,
+            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_modifiers: vec![
+                "sync", "aligned", "m16n8k16", "row", "col", "f16", "f16", "f16", "f16",
+            ],
+            ptx_register_counts: [2, 4, 2, 2],
+        }),
+        (
+            M16n8k16,
+            F32,
+            Bf16,
+            Bf16,
+            RegisterMmaOverflow::NotApplicable,
+            C4F32A4U32B2U32ToD4F32,
+            true,
+        ) => Some(RegisterMmaRecipe {
+            id: "mma_m16n8k16_f32_bf16",
+            abi_id: "i0105",
+            operation_key: "matrix.mma.m16n8k16.row.col.f32.bf16.bf16.f32",
+            source_record: "int_nvvm_mma_m16n8k16_row_col_bf16",
+            llvm_symbol: "llvm.nvvm.mma.m16n8k16.row.col.bf16",
+            rust_arguments: &["[f32; 4]", "[u32; 4]", "[u32; 2]"],
+            rust_result: "[f32; 4]",
+            dialect_op_type: "RegisterMmaOp",
+            dialect_op_name: "nvvm.register_mma",
+            dialect_operands: &[
+                "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32",
+            ],
+            dialect_results: &["f32", "f32", "f32", "f32"],
+            llvm_arguments: &[
+                "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32",
+            ],
+            llvm_results: &["f32", "f32", "f32", "f32"],
+            adapter: C4F32A4U32B2U32ToD4F32,
+            compatibility_source: RegisterMmaCompatibilitySource::ExistingStub,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_modifiers: vec![
+                "sync", "aligned", "m16n8k16", "row", "col", "f32", "bf16", "bf16", "f32",
+            ],
+            ptx_register_counts: [4, 4, 2, 4],
+        }),
+        (
+            M16n8k16,
+            F32,
+            F16Element,
+            F16Element,
+            RegisterMmaOverflow::NotApplicable,
+            C4F32A4U32B2U32ToD4F32,
+            true,
+        ) => Some(RegisterMmaRecipe {
+            id: "mma_m16n8k16_f32_f16",
+            abi_id: "i0106",
+            operation_key: "matrix.mma.m16n8k16.row.col.f32.f16.f16.f32",
+            source_record: "int_nvvm_mma_m16n8k16_row_col_f32_f32",
+            llvm_symbol: "llvm.nvvm.mma.m16n8k16.row.col.f32.f32",
+            rust_arguments: &["[f32; 4]", "[u32; 4]", "[u32; 2]"],
+            rust_result: "[f32; 4]",
+            dialect_op_type: "RegisterMmaOp",
+            dialect_op_name: "nvvm.register_mma",
+            dialect_operands: &[
+                "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32",
+            ],
+            dialect_results: &["f32", "f32", "f32", "f32"],
+            llvm_arguments: &[
+                "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "f32", "f32", "f32", "f32",
+            ],
+            llvm_results: &["f32", "f32", "f32", "f32"],
+            adapter: C4F32A4U32B2U32ToD4F32,
+            compatibility_source: RegisterMmaCompatibilitySource::ExistingStub,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_modifiers: vec![
+                "sync", "aligned", "m16n8k16", "row", "col", "f32", "f16", "f16", "f32",
+            ],
+            ptx_register_counts: [4, 4, 2, 4],
+        }),
+        (
+            M16n8k8,
+            F32,
+            Tf32,
+            Tf32,
+            RegisterMmaOverflow::NotApplicable,
+            C4F32A4U32B2U32ToD4F32,
+            true,
+        ) => Some(RegisterMmaRecipe {
+            id: "mma_m16n8k8_f32_tf32",
+            abi_id: "i0107",
+            operation_key: "matrix.mma.m16n8k8.row.col.f32.tf32.tf32.f32",
+            source_record: "int_nvvm_mma_m16n8k8_row_col_tf32",
+            llvm_symbol: "llvm.nvvm.mma.m16n8k8.row.col.tf32",
+            rust_arguments: &["[f32; 4]", "[u32; 4]", "[u32; 2]"],
+            rust_result: "[f32; 4]",
+            dialect_op_type: "RegisterMmaOp",
+            dialect_op_name: "nvvm.register_mma",
+            dialect_operands: &[
+                "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32",
+            ],
+            dialect_results: &["f32", "f32", "f32", "f32"],
+            llvm_arguments: &[
+                "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32",
+            ],
+            llvm_results: &["f32", "f32", "f32", "f32"],
+            adapter: C4F32A4U32B2U32ToD4F32,
+            compatibility_source: RegisterMmaCompatibilitySource::ExistingStub,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_modifiers: vec![
+                "sync", "aligned", "m16n8k8", "row", "col", "f32", "tf32", "tf32", "f32",
+            ],
+            ptx_register_counts: [4, 4, 2, 4],
+        }),
+        (
+            M8n8k4,
+            F64,
+            F64Element,
+            F64Element,
+            RegisterMmaOverflow::NotApplicable,
+            C2F64A1F64B1F64ToD2F64,
+            true,
+        ) => Some(RegisterMmaRecipe {
+            id: "mma_m8n8k4_f64",
+            abi_id: "i0109",
+            operation_key: "matrix.mma.m8n8k4.row.col.f64.f64.f64.f64",
+            source_record: "int_nvvm_mma_m8n8k4_row_col_f64",
+            llvm_symbol: "llvm.nvvm.mma.m8n8k4.row.col.f64",
+            rust_arguments: &["[f64; 2]", "f64", "f64"],
+            rust_result: "[f64; 2]",
+            dialect_op_type: "RegisterMmaOp",
+            dialect_op_name: "nvvm.register_mma",
+            dialect_operands: &["f64", "f64", "f64", "f64"],
+            dialect_results: &["f64", "f64"],
+            llvm_arguments: &["f64", "f64", "f64", "f64"],
+            llvm_results: &["f64", "f64"],
+            adapter: C2F64A1F64B1F64ToD2F64,
+            compatibility_source: RegisterMmaCompatibilitySource::ExistingStub,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_modifiers: vec![
+                "sync", "aligned", "m8n8k4", "row", "col", "f64", "f64", "f64", "f64",
+            ],
+            ptx_register_counts: [2, 1, 1, 2],
+        }),
+        _ => None,
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/mma/register_admissions.rs b/crates/cuda-intrinsics-gen/src/resolve/families/mma/register_admissions.rs
new file mode 100644
index 0000000000..c0a2d4b3d8
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/mma/register_admissions.rs
@@ -0,0 +1,1454 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, IntrinsicBackend, OverlayBackendLowering, OverlayIntrinsic,
+    RegisterMma, RegisterMmaAccumulator, RegisterMmaAdapter, RegisterMmaAmpereFloatAdmission,
+    RegisterMmaAmpereFloatVariant, RegisterMmaBinaryAdmission, RegisterMmaCompatibilitySource,
+    RegisterMmaElement, RegisterMmaF8F6F4Admission, RegisterMmaFp8Admission,
+    RegisterMmaIntegerAdmission, RegisterMmaKind, RegisterMmaLayout, RegisterMmaOperation,
+    RegisterMmaOverflow, RegisterMmaParticipation, RegisterMmaShape, RuntimeValidation,
+    SparseMmaAccumulator, SparseMmaLayout, SparseMmaMetadata, SparseMmaOverflow, SparseMmaSelector,
+    SparseMmaShape,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, bail, ensure};
+use std::collections::BTreeSet;
+
+use super::*;
+
+pub(in crate::resolve) const REGISTER_MMA_F8F6F4_TARGETS: &str = "sm_120a|sm_120f|sm_121a|sm_121f";
+#[derive(Debug, Clone, Copy)]
+pub(in crate::resolve) enum RegisterMmaIntegerKind {
+    Int4,
+    Int8,
+}
+
+impl RegisterMmaIntegerKind {
+    fn label(self) -> &'static str {
+        match self {
+            Self::Int4 => "INT4",
+            Self::Int8 => "INT8",
+        }
+    }
+
+    fn supports(self, shape: RegisterMmaShape, element: RegisterMmaElement) -> bool {
+        match self {
+            Self::Int4 => {
+                matches!(
+                    shape,
+                    RegisterMmaShape::M8n8k32
+                        | RegisterMmaShape::M16n8k32
+                        | RegisterMmaShape::M16n8k64
+                ) && matches!(element, RegisterMmaElement::S4 | RegisterMmaElement::U4)
+            }
+            Self::Int8 => {
+                matches!(
+                    shape,
+                    RegisterMmaShape::M8n8k16
+                        | RegisterMmaShape::M16n8k16
+                        | RegisterMmaShape::M16n8k32
+                ) && matches!(element, RegisterMmaElement::S8 | RegisterMmaElement::U8)
+            }
+        }
+    }
+}
+
+pub(in crate::resolve) fn expand_register_mma_integer_admission(
+    kind: RegisterMmaIntegerKind,
+    admission: &RegisterMmaIntegerAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    use RegisterMmaAdapter::{
+        C2I32A1U32B1U32ToD2I32, C4I32A2U32B1U32ToD4I32, C4I32A4U32B2U32ToD4I32,
+    };
+    use RegisterMmaCompatibilitySource::GeneratedStub;
+    use RegisterMmaLayout::{Col, Row};
+    use RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes;
+    use RegisterMmaShape::{M8n8k16, M8n8k32, M16n8k16, M16n8k32, M16n8k64};
+
+    ensure!(
+        !admission.variants.is_empty(),
+        "compact {} MMA admission has no variants",
+        kind.label()
+    );
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} MMA runtime validation may be marked executed only with GPU evidence",
+        kind.label()
+    );
+
+    let mut seen = BTreeSet::new();
+    let mut records = Vec::with_capacity(admission.variants.len());
+    for variant in &admission.variants {
+        ensure!(
+            seen.insert((
+                variant.shape,
+                variant.a_element,
+                variant.b_element,
+                variant.overflow,
+            )),
+            "compact {} MMA admission contains a duplicate variant",
+            kind.label()
+        );
+        ensure!(
+            kind.supports(variant.shape, variant.a_element)
+                && kind.supports(variant.shape, variant.b_element),
+            "compact {} MMA admission contains an unsupported shape or element",
+            kind.label()
+        );
+        let adapter =
+            match (kind, variant.shape) {
+                (RegisterMmaIntegerKind::Int8, M8n8k16)
+                | (RegisterMmaIntegerKind::Int4, M8n8k32) => C2I32A1U32B1U32ToD2I32,
+                (RegisterMmaIntegerKind::Int8, M16n8k16)
+                | (RegisterMmaIntegerKind::Int4, M16n8k32) => C4I32A2U32B1U32ToD4I32,
+                (RegisterMmaIntegerKind::Int8, M16n8k32)
+                | (RegisterMmaIntegerKind::Int4, M16n8k64) => C4I32A4U32B2U32ToD4I32,
+                _ => bail!(
+                    "compact {} MMA admission contains an unsupported shape",
+                    kind.label()
+                ),
+            };
+        let mma = RegisterMma {
+            shape: variant.shape,
+            operation: RegisterMmaOperation::Multiply,
+            kind: None,
+            accumulator: RegisterMmaAccumulator::S32,
+            a_element: variant.a_element,
+            b_element: variant.b_element,
+            a_layout: Row,
+            b_layout: Col,
+            overflow: variant.overflow,
+            participation: AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+            adapter,
+            compatibility_source: GeneratedStub,
+            runtime_validation: admission.runtime_validation,
+        };
+        let recipe = register_mma_recipe(&mma).with_context(|| {
+            format!(
+                "compact {} MMA admission requests a variant outside the closed recipe set",
+                kind.label()
+            )
+        })?;
+        ensure!(
+            recipe.compatibility_source == GeneratedStub,
+            "compact {} MMA admission may only add generated compatibility stubs",
+            kind.label()
+        );
+
+        let element = |element| match (kind, element) {
+            (RegisterMmaIntegerKind::Int4, RegisterMmaElement::S4)
+            | (RegisterMmaIntegerKind::Int8, RegisterMmaElement::S8) => Ok("signed"),
+            (RegisterMmaIntegerKind::Int4, RegisterMmaElement::U4)
+            | (RegisterMmaIntegerKind::Int8, RegisterMmaElement::U8) => Ok("unsigned"),
+            _ => bail!(
+                "compact {} MMA admission contains an unsupported element",
+                kind.label()
+            ),
+        };
+        let overflow = match variant.overflow {
+            RegisterMmaOverflow::Wrapping => "wrapping",
+            RegisterMmaOverflow::Satfinite => "saturating",
+            RegisterMmaOverflow::NotApplicable => {
+                bail!(
+                    "compact {} MMA admission requires an integer overflow mode",
+                    kind.label()
+                )
+            }
+        };
+        let summary = format!(
+            "Multiplies warp-distributed {} A and {} B {} fragments and adds a {overflow} s32 accumulator.",
+            element(variant.a_element)?,
+            element(variant.b_element)?,
+            kind.label(),
+        );
+
+        records.push(OverlayIntrinsic {
+            id: recipe.id.into(),
+            abi_id: recipe.abi_id.into(),
+            operation_key: recipe.operation_key.into(),
+            family: "register_mma".into(),
+            source: None,
+            source_record: Some(recipe.source_record.into()),
+            rust_module: "matrix".into(),
+            rust_name: recipe.id.into(),
+            rust_arguments: recipe
+                .rust_arguments
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            rust_result: recipe.rust_result.into(),
+            safe: false,
+            must_use: true,
+            safe_allowlist_reason: None,
+            public_rust_path: format!("cuda_intrinsics::matrix::{}", recipe.id),
+            compatibility_rust_paths: vec![format!("cuda_device::wmma::{}", recipe.id)],
+            dialect_op_type: recipe.dialect_op_type.into(),
+            dialect_op_name: recipe.dialect_op_name.into(),
+            dialect_operands: recipe
+                .dialect_operands
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            dialect_results: recipe
+                .dialect_results
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            llvm_symbol: Some(recipe.llvm_symbol.into()),
+            resolved_llvm_symbol: None,
+            llvm_arguments: recipe
+                .llvm_arguments
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            llvm_results: recipe
+                .llvm_results
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            pure: false,
+            memory: "none".into(),
+            convergent: true,
+            execution_scope: "warp".into(),
+            minimum_ptx: recipe.minimum_ptx.into(),
+            minimum_sm: Some(recipe.minimum_sm.into()),
+            ptx_result: recipe.rust_result.into(),
+            targets: "all".into(),
+            ptx_isa_version: "9.3".into(),
+            ptx_isa_section: "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
+            lowering: "generated_register_mma".into(),
+            backend_lowerings: vec![
+                OverlayBackendLowering {
+                    backend: IntrinsicBackend::LlvmNvptx,
+                    mechanism: BackendLoweringMechanism::InlinePtx,
+                    evidence_profile: admission.llvm_evidence_profile.clone(),
+                    targets: None,
+                    minimum_ptx: Some(recipe.minimum_ptx.into()),
+                    minimum_sm: Some(recipe.minimum_sm.into()),
+                },
+                OverlayBackendLowering {
+                    backend: IntrinsicBackend::LibNvvm,
+                    mechanism: BackendLoweringMechanism::InlinePtx,
+                    evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                    targets: None,
+                    minimum_ptx: Some(recipe.minimum_ptx.into()),
+                    minimum_sm: Some(recipe.minimum_sm.into()),
+                },
+            ],
+            packed_atomic: None,
+            redux: None,
+            vote: None,
+            active_mask: None,
+            warp_match: None,
+            warp_barrier: None,
+            warp_shuffle: None,
+            dot_product: None,
+            packed_alu: None,
+        integer_minmax: None,
+            packed_conversion: None,
+            scalar_conversion: None,
+            scalar_arithmetic: None,
+            scalar_math: None,
+            extended_minmax: None,
+            cp_async_copy: None,
+            cp_async_control: None,
+            cp_async_mbarrier: None,
+            mbarrier_basic: None,
+            movmatrix: None,
+            mbarrier_extended: None,
+            register_mma: Some(mma),
+            sparse_mma: None,
+            prmt: None,
+            cluster_barrier: None,
+            wgmma_control: None,
+            special_register: None,
+            debug_control: None,
+            cluster_memory: None,
+            clc: None,
+            tma: None,
+            tcgen05: None,
+            ldmatrix_variant: None,
+            ldmatrix_safety: None,
+            ldmatrix_adapter: None,
+            selected_address_space: None,
+            expected_ptx: InstructionPattern {
+                mnemonic: "mma".into(),
+                modifiers: recipe
+                    .ptx_modifiers
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                operands: recipe
+                    .ptx_register_counts
+                    .map(|length| OperandPattern::RegisterList { length })
+                    .into(),
+            },
+            summary,
+        });
+    }
+    Ok(records)
+}
+
+pub(in crate::resolve) const REGISTER_MMA_F8F6F4_ELEMENTS: [RegisterMmaElement; 5] = [
+    RegisterMmaElement::E2m1,
+    RegisterMmaElement::E2m3,
+    RegisterMmaElement::E3m2,
+    RegisterMmaElement::E4m3,
+    RegisterMmaElement::E5m2,
+];
+
+pub(in crate::resolve) fn register_mma_f8f6f4_element_name(
+    element: RegisterMmaElement,
+) -> Option<&'static str> {
+    match element {
+        RegisterMmaElement::E2m1 => Some("e2m1"),
+        RegisterMmaElement::E2m3 => Some("e2m3"),
+        RegisterMmaElement::E3m2 => Some("e3m2"),
+        RegisterMmaElement::E4m3 => Some("e4m3"),
+        RegisterMmaElement::E5m2 => Some("e5m2"),
+        _ => None,
+    }
+}
+
+pub(in crate::resolve) fn is_dense_f8f6f4_register_mma_policy(policy: &OverlayIntrinsic) -> bool {
+    policy.family == "register_mma"
+        && policy.targets == REGISTER_MMA_F8F6F4_TARGETS
+        && policy.register_mma.as_ref().is_some_and(|mma| {
+            mma.kind != Some(RegisterMmaKind::Standard)
+                && mma.shape == RegisterMmaShape::M16n8k32
+                && mma.operation == RegisterMmaOperation::Multiply
+                && matches!(
+                    mma.accumulator,
+                    RegisterMmaAccumulator::F16 | RegisterMmaAccumulator::F32
+                )
+                && register_mma_f8f6f4_element_name(mma.a_element).is_some()
+                && register_mma_f8f6f4_element_name(mma.b_element).is_some()
+                && mma.a_layout == RegisterMmaLayout::Row
+                && mma.b_layout == RegisterMmaLayout::Col
+                && mma.overflow == RegisterMmaOverflow::NotApplicable
+        })
+}
+
+pub(in crate::resolve) fn is_sparse_f8f6f4_f16_policy(policy: &OverlayIntrinsic) -> bool {
+    policy.family == "sparse_mma"
+        && policy.targets == SPARSE_MMA_F8F6F4_TARGETS
+        && policy.sparse_mma.as_ref().is_some_and(|mma| {
+            mma.shape == SparseMmaShape::M16n8k64
+                && mma.accumulator == SparseMmaAccumulator::F16
+                && SPARSE_MMA_F8F6F4_ELEMENTS.contains(&mma.a_element)
+                && SPARSE_MMA_F8F6F4_ELEMENTS.contains(&mma.b_element)
+                && mma.a_layout == SparseMmaLayout::Row
+                && mma.b_layout == SparseMmaLayout::Col
+                && mma.overflow == SparseMmaOverflow::NotApplicable
+                && mma.metadata == SparseMmaMetadata::Ordered
+                && mma.selector == SparseMmaSelector::ImmediateZero
+        })
+}
+
+pub(in crate::resolve) fn is_f8f6f4_mma_target_matrix_policy(policy: &OverlayIntrinsic) -> bool {
+    is_dense_f8f6f4_register_mma_policy(policy) || is_sparse_f8f6f4_f16_policy(policy)
+}
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct RegisterMmaF8F6F4Contract {
+    pub(in crate::resolve) accumulator: RegisterMmaAccumulator,
+    pub(in crate::resolve) scalar_name: &'static str,
+    pub(in crate::resolve) rust_arguments: [&'static str; 3],
+    pub(in crate::resolve) rust_result: &'static str,
+    pub(in crate::resolve) dialect_operands: &'static [&'static str],
+    pub(in crate::resolve) dialect_results: &'static [&'static str],
+    pub(in crate::resolve) llvm_arguments: &'static [&'static str],
+    pub(in crate::resolve) llvm_results: &'static [&'static str],
+    pub(in crate::resolve) adapter: RegisterMmaAdapter,
+    pub(in crate::resolve) ptx_register_counts: [usize; 4],
+    pub(in crate::resolve) summary_accumulator: &'static str,
+}
+
+pub(in crate::resolve) fn register_mma_f8f6f4_contract(
+    accumulator: RegisterMmaAccumulator,
+) -> Result<RegisterMmaF8F6F4Contract> {
+    match accumulator {
+        RegisterMmaAccumulator::F16 => Ok(RegisterMmaF8F6F4Contract {
+            accumulator,
+            scalar_name: "f16",
+            rust_arguments: ["[u32; 2]", "[u32; 4]", "[u32; 2]"],
+            rust_result: "[u32; 2]",
+            dialect_operands: &["i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32"],
+            dialect_results: &["i32", "i32"],
+            llvm_arguments: &["i32", "i32", "i32", "i32", "i32", "i32", "v2f16", "v2f16"],
+            llvm_results: &["v2f16", "v2f16"],
+            adapter: RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32,
+            ptx_register_counts: [2, 4, 2, 2],
+            summary_accumulator: "F16",
+        }),
+        RegisterMmaAccumulator::F32 => Ok(RegisterMmaF8F6F4Contract {
+            accumulator,
+            scalar_name: "f32",
+            rust_arguments: ["[f32; 4]", "[u32; 4]", "[u32; 2]"],
+            rust_result: "[f32; 4]",
+            dialect_operands: &[
+                "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32",
+            ],
+            dialect_results: &["f32", "f32", "f32", "f32"],
+            llvm_arguments: &[
+                "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32",
+            ],
+            llvm_results: &["f32", "f32", "f32", "f32"],
+            adapter: RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32,
+            ptx_register_counts: [4, 4, 2, 4],
+            summary_accumulator: "F32",
+        }),
+        _ => bail!("unsupported dense f8f6f4 MMA accumulator {accumulator:?}"),
+    }
+}
+
+pub(in crate::resolve) fn expand_register_mma_f8f6f4_admission(
+    admission: &RegisterMmaF8F6F4Admission,
+    accumulator: RegisterMmaAccumulator,
+) -> Result<Vec<OverlayIntrinsic>> {
+    let contract = register_mma_f8f6f4_contract(accumulator)?;
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "dense f8f6f4 MMA runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "dense f8f6f4 MMA admission requires both backend evidence profiles"
+    );
+    ensure!(
+        admission.a_elements == REGISTER_MMA_F8F6F4_ELEMENTS
+            && admission.b_elements == REGISTER_MMA_F8F6F4_ELEMENTS
+            && admission.product_count == 25,
+        "dense f8f6f4 MMA admission must contain the canonical 5 by 5 element matrix"
+    );
+    let expected_targets = ["sm_120a", "sm_120f", "sm_121a", "sm_121f"];
+    ensure!(
+        admission
+            .targets
+            .iter()
+            .map(String::as_str)
+            .eq(expected_targets),
+        "dense f8f6f4 MMA admission must retain the reviewed Blackwell target set"
+    );
+
+    let mut records = Vec::with_capacity(admission.product_count);
+    for &a_element in &admission.a_elements {
+        for &b_element in &admission.b_elements {
+            let a = register_mma_f8f6f4_element_name(a_element)
+                .expect("validated dense f8f6f4 A element");
+            let b = register_mma_f8f6f4_element_name(b_element)
+                .expect("validated dense f8f6f4 B element");
+            let scalar = contract.scalar_name;
+            let id = format!("mma_m16n8k32_{scalar}_{a}_{b}");
+            let source_record =
+                format!("int_nvvm_mma_m16n8k32_row_col_kind_f8f6f4_{scalar}_{a}_{b}_{scalar}");
+            let llvm_symbol =
+                format!("llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.{scalar}.{a}.{b}.{scalar}");
+            let mma = RegisterMma {
+                shape: RegisterMmaShape::M16n8k32,
+                operation: RegisterMmaOperation::Multiply,
+                kind: None,
+                accumulator: contract.accumulator,
+                a_element,
+                b_element,
+                a_layout: RegisterMmaLayout::Row,
+                b_layout: RegisterMmaLayout::Col,
+                overflow: RegisterMmaOverflow::NotApplicable,
+                participation:
+                    RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+                adapter: contract.adapter,
+                compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+                runtime_validation: admission.runtime_validation,
+            };
+
+            records.push(OverlayIntrinsic {
+                id: id.clone(),
+                abi_id: String::new(),
+                operation_key: format!(
+                    "matrix.mma.m16n8k32.row.col.kind_f8f6f4.{scalar}.{a}.{b}.{scalar}"
+                ),
+                family: "register_mma".into(),
+                source: None,
+                source_record: Some(source_record),
+                rust_module: "matrix".into(),
+                rust_name: id.clone(),
+                rust_arguments: contract.rust_arguments.map(Into::into).into(),
+                rust_result: contract.rust_result.into(),
+                safe: false,
+                must_use: true,
+                safe_allowlist_reason: None,
+                public_rust_path: format!("cuda_intrinsics::matrix::{id}"),
+                compatibility_rust_paths: vec![format!("cuda_device::wmma::{id}")],
+                dialect_op_type: "RegisterMmaOp".into(),
+                dialect_op_name: "nvvm.register_mma".into(),
+                dialect_operands: contract
+                    .dialect_operands
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                dialect_results: contract
+                    .dialect_results
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                llvm_symbol: Some(llvm_symbol),
+                resolved_llvm_symbol: None,
+                llvm_arguments: contract
+                    .llvm_arguments
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                llvm_results: contract
+                    .llvm_results
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                pure: false,
+                memory: "none".into(),
+                convergent: true,
+                execution_scope: "warp".into(),
+                minimum_ptx: "8.7".into(),
+                minimum_sm: None,
+                ptx_result: contract.rust_result.into(),
+                targets: REGISTER_MMA_F8F6F4_TARGETS.into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section: "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
+                lowering: "generated_register_mma".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.llvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: None,
+                        minimum_sm: None,
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: None,
+                        minimum_sm: None,
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: Some(mma),
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: "mma".into(),
+                    modifiers: [
+                        "sync",
+                        "aligned",
+                        "m16n8k32",
+                        "row",
+                        "col",
+                        "kind::f8f6f4",
+                        scalar,
+                        a,
+                        b,
+                        scalar,
+                    ]
+                    .into_iter()
+                    .map(Into::into)
+                    .collect(),
+                    operands: contract
+                        .ptx_register_counts
+                        .map(|length| OperandPattern::RegisterList { length })
+                        .into(),
+                },
+                summary: format!(
+                    "Multiplies warp-distributed {a} A and {b} B fragments and adds an {} accumulator.",
+                    contract.summary_accumulator
+                ),
+            });
+        }
+    }
+    Ok(records)
+}
+
+pub(in crate::resolve) fn expand_register_mma_mxf8f6f4_admission(
+    admission: &RegisterMmaF8F6F4Admission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "dense mxf8f6f4 MMA runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "dense mxf8f6f4 MMA admission requires both backend evidence profiles"
+    );
+    ensure!(
+        admission.a_elements == REGISTER_MMA_F8F6F4_ELEMENTS
+            && admission.b_elements == REGISTER_MMA_F8F6F4_ELEMENTS
+            && admission.product_count == 25,
+        "dense mxf8f6f4 MMA admission must contain the canonical 5 by 5 element matrix"
+    );
+    let expected_targets = ["sm_120a", "sm_120f", "sm_121a", "sm_121f"];
+    ensure!(
+        admission
+            .targets
+            .iter()
+            .map(String::as_str)
+            .eq(expected_targets),
+        "dense mxf8f6f4 MMA admission must retain the reviewed Blackwell target set"
+    );
+
+    let rust_arguments = [
+        "[f32; 4]", "[u32; 4]", "[u32; 2]", "u32", "u16", "u16", "u32", "u16", "u16",
+    ];
+    let dialect_operands = [
+        "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i16", "i16",
+        "i32", "i16", "i16",
+    ];
+    let llvm_arguments = [
+        "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32", "i32", "i16", "i16",
+        "i32", "i16", "i16",
+    ];
+    let dialect_results = ["f32", "f32", "f32", "f32"];
+
+    let mut records = Vec::with_capacity(admission.product_count);
+    for &a_element in &admission.a_elements {
+        for &b_element in &admission.b_elements {
+            let a = register_mma_f8f6f4_element_name(a_element)
+                .expect("validated dense mxf8f6f4 A element");
+            let b = register_mma_f8f6f4_element_name(b_element)
+                .expect("validated dense mxf8f6f4 B element");
+            let id = format!("mma_m16n8k32_mxf8f6f4_f32_{a}_{b}");
+            let source_record =
+                format!("int_nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_{a}_{b}_f32_ue8m0");
+            let llvm_symbol = format!(
+                "llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.{a}.{b}.f32.ue8m0"
+            );
+            let mma = RegisterMma {
+                shape: RegisterMmaShape::M16n8k32,
+                operation: RegisterMmaOperation::Multiply,
+                kind: Some(RegisterMmaKind::Mxf8f6f4),
+                accumulator: RegisterMmaAccumulator::F32,
+                a_element,
+                b_element,
+                a_layout: RegisterMmaLayout::Row,
+                b_layout: RegisterMmaLayout::Col,
+                overflow: RegisterMmaOverflow::NotApplicable,
+                participation:
+                    RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+                adapter: RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+                compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+                runtime_validation: admission.runtime_validation,
+            };
+
+            records.push(OverlayIntrinsic {
+                id: id.clone(),
+                abi_id: String::new(),
+                operation_key: format!(
+                    "matrix.mma.m16n8k32.row.col.kind_mxf8f6f4.scale_vec_1x.f32.{a}.{b}.f32.ue8m0"
+                ),
+                family: "register_mma".into(),
+                source: None,
+                source_record: Some(source_record),
+                rust_module: "matrix".into(),
+                rust_name: id.clone(),
+                rust_arguments: rust_arguments.map(Into::into).into(),
+                rust_result: "[f32; 4]".into(),
+                safe: false,
+                must_use: true,
+                safe_allowlist_reason: None,
+                public_rust_path: format!("cuda_intrinsics::matrix::{id}"),
+                compatibility_rust_paths: vec![format!("cuda_device::wmma::{id}")],
+                dialect_op_type: "RegisterMmaOp".into(),
+                dialect_op_name: "nvvm.register_mma".into(),
+                dialect_operands: dialect_operands.map(Into::into).into(),
+                dialect_results: dialect_results.map(Into::into).into(),
+                llvm_symbol: Some(llvm_symbol),
+                resolved_llvm_symbol: None,
+                llvm_arguments: llvm_arguments.map(Into::into).into(),
+                llvm_results: dialect_results.map(Into::into).into(),
+                pure: false,
+                memory: "none".into(),
+                convergent: true,
+                execution_scope: "warp".into(),
+                minimum_ptx: "8.7".into(),
+                minimum_sm: None,
+                ptx_result: "[f32; 4]".into(),
+                targets: REGISTER_MMA_F8F6F4_TARGETS.into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section:
+                    "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
+                lowering: "generated_register_mma".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.llvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: None,
+                        minimum_sm: None,
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: None,
+                        minimum_sm: None,
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: Some(mma),
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: "mma".into(),
+                    modifiers: [
+                        "sync",
+                        "aligned",
+                        "m16n8k32",
+                        "row",
+                        "col",
+                        "kind::mxf8f6f4",
+                        "block_scale",
+                        "f32",
+                        a,
+                        b,
+                        "f32",
+                        "ue8m0",
+                    ]
+                    .into_iter()
+                    .map(Into::into)
+                    .collect(),
+                    operands: vec![
+                        OperandPattern::RegisterList { length: 4 },
+                        OperandPattern::RegisterList { length: 4 },
+                        OperandPattern::RegisterList { length: 2 },
+                        OperandPattern::RegisterList { length: 4 },
+                        OperandPattern::Register,
+                        OperandPattern::RegisterList { length: 2 },
+                        OperandPattern::Register,
+                        OperandPattern::RegisterList { length: 2 },
+                    ],
+                },
+                summary: format!(
+                    "Multiplies block-scaled warp-distributed {a} A and {b} B fragments and adds an F32 accumulator."
+                ),
+            });
+        }
+    }
+    Ok(records)
+}
+
+pub(in crate::resolve) const REGISTER_MMA_FP8_SHAPES: [RegisterMmaShape; 2] =
+    [RegisterMmaShape::M16n8k16, RegisterMmaShape::M16n8k32];
+pub(in crate::resolve) const REGISTER_MMA_FP8_ACCUMULATORS: [RegisterMmaAccumulator; 2] =
+    [RegisterMmaAccumulator::F16, RegisterMmaAccumulator::F32];
+pub(in crate::resolve) const REGISTER_MMA_FP8_ELEMENTS: [RegisterMmaElement; 2] =
+    [RegisterMmaElement::E4m3, RegisterMmaElement::E5m2];
+
+pub(in crate::resolve) fn register_mma_fp8_element_name(
+    element: RegisterMmaElement,
+) -> Option<&'static str> {
+    match element {
+        RegisterMmaElement::E4m3 => Some("e4m3"),
+        RegisterMmaElement::E5m2 => Some("e5m2"),
+        _ => None,
+    }
+}
+
+pub(in crate::resolve) fn register_mma_fp8_shape_contract(
+    shape: RegisterMmaShape,
+) -> Result<(&'static str, usize, usize)> {
+    match shape {
+        RegisterMmaShape::M16n8k16 => Ok(("m16n8k16", 2, 1)),
+        RegisterMmaShape::M16n8k32 => Ok(("m16n8k32", 4, 2)),
+        _ => bail!("unsupported standard FP8 register-MMA shape {shape:?}"),
+    }
+}
+
+pub(in crate::resolve) fn register_mma_fp8_minimum_ptx(
+    shape: RegisterMmaShape,
+    accumulator: RegisterMmaAccumulator,
+) -> &'static str {
+    // ptxas requires PTX 8.7 for the k32 F16 form despite LLVM's 8.4 predicate.
+    match (shape, accumulator) {
+        (RegisterMmaShape::M16n8k32, RegisterMmaAccumulator::F32) => "8.4",
+        _ => "8.7",
+    }
+}
+
+pub(in crate::resolve) fn expand_register_mma_fp8_admission(
+    admission: &RegisterMmaFp8Admission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "standard FP8 MMA runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "standard FP8 MMA admission requires both backend evidence profiles"
+    );
+    ensure!(
+        admission.shapes == REGISTER_MMA_FP8_SHAPES
+            && admission.accumulators == REGISTER_MMA_FP8_ACCUMULATORS
+            && admission.a_elements == REGISTER_MMA_FP8_ELEMENTS
+            && admission.b_elements == REGISTER_MMA_FP8_ELEMENTS
+            && admission.product_count == 16,
+        "standard FP8 MMA admission must retain the canonical 2 by 2 by 2 by 2 matrix"
+    );
+
+    let mut records = Vec::with_capacity(admission.product_count);
+    for &shape in &admission.shapes {
+        let (shape_name, a_count, b_count) = register_mma_fp8_shape_contract(shape)?;
+        for &accumulator in &admission.accumulators {
+            let minimum_ptx = register_mma_fp8_minimum_ptx(shape, accumulator);
+            let (scalar, rust_arguments, rust_result, dialect_operands, dialect_results, adapter) =
+                match accumulator {
+                    RegisterMmaAccumulator::F16 => (
+                        "f16",
+                        vec![
+                            "[u32; 2]".into(),
+                            format!("[u32; {a_count}]"),
+                            if b_count == 1 {
+                                "u32".into()
+                            } else {
+                                "[u32; 2]".into()
+                            },
+                        ],
+                        "[u32; 2]".to_owned(),
+                        [
+                            vec!["i32".into(); 2],
+                            vec!["i32".into(); a_count],
+                            vec!["i32".into(); b_count],
+                        ]
+                        .concat(),
+                        vec!["i32".into(); 2],
+                        if shape == RegisterMmaShape::M16n8k16 {
+                            RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32
+                        } else {
+                            RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32
+                        },
+                    ),
+                    RegisterMmaAccumulator::F32 => (
+                        "f32",
+                        vec![
+                            "[f32; 4]".into(),
+                            format!("[u32; {a_count}]"),
+                            if b_count == 1 {
+                                "u32".into()
+                            } else {
+                                "[u32; 2]".into()
+                            },
+                        ],
+                        "[f32; 4]".to_owned(),
+                        [
+                            vec!["f32".into(); 4],
+                            vec!["i32".into(); a_count],
+                            vec!["i32".into(); b_count],
+                        ]
+                        .concat(),
+                        vec!["f32".into(); 4],
+                        if shape == RegisterMmaShape::M16n8k16 {
+                            RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
+                        } else {
+                            RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32
+                        },
+                    ),
+                    _ => unreachable!("validated standard FP8 accumulator"),
+                };
+            let llvm_arguments = [
+                vec!["i32".into(); a_count + b_count],
+                if accumulator == RegisterMmaAccumulator::F16 {
+                    vec!["v2f16".into(); 2]
+                } else {
+                    vec!["f32".into(); 4]
+                },
+            ]
+            .concat();
+            let llvm_results = if accumulator == RegisterMmaAccumulator::F16 {
+                vec!["v2f16".into(); 2]
+            } else {
+                vec!["f32".into(); 4]
+            };
+            let result_count = dialect_results.len();
+
+            for &a_element in &admission.a_elements {
+                for &b_element in &admission.b_elements {
+                    let a = register_mma_fp8_element_name(a_element)
+                        .expect("validated standard FP8 A element");
+                    let b = register_mma_fp8_element_name(b_element)
+                        .expect("validated standard FP8 B element");
+                    let id = format!("mma_{shape_name}_fp8_{scalar}_{a}_{b}");
+                    let source_record =
+                        format!("int_nvvm_mma_{shape_name}_row_col_{scalar}_{a}_{b}_{scalar}");
+                    let llvm_symbol =
+                        format!("llvm.nvvm.mma.{shape_name}.row.col.{scalar}.{a}.{b}.{scalar}");
+                    let mma = RegisterMma {
+                        shape,
+                        operation: RegisterMmaOperation::Multiply,
+                        kind: Some(RegisterMmaKind::Standard),
+                        accumulator,
+                        a_element,
+                        b_element,
+                        a_layout: RegisterMmaLayout::Row,
+                        b_layout: RegisterMmaLayout::Col,
+                        overflow: RegisterMmaOverflow::NotApplicable,
+                        participation: RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+                        adapter,
+                        compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+                        runtime_validation: admission.runtime_validation,
+                    };
+                    records.push(OverlayIntrinsic {
+                        id: id.clone(),
+                        abi_id: String::new(),
+                        operation_key: format!(
+                            "matrix.mma.{shape_name}.row.col.standard_fp8.{scalar}.{a}.{b}.{scalar}"
+                        ),
+                        family: "register_mma".into(),
+                        source: None,
+                        source_record: Some(source_record),
+                        rust_module: "matrix".into(),
+                        rust_name: id.clone(),
+                        rust_arguments: rust_arguments.clone(),
+                        rust_result: rust_result.clone(),
+                        safe: false,
+                        must_use: true,
+                        safe_allowlist_reason: None,
+                        public_rust_path: format!("cuda_intrinsics::matrix::{id}"),
+                        compatibility_rust_paths: vec![format!("cuda_device::wmma::{id}")],
+                        dialect_op_type: "RegisterMmaOp".into(),
+                        dialect_op_name: "nvvm.register_mma".into(),
+                        dialect_operands: dialect_operands.clone(),
+                        dialect_results: dialect_results.clone(),
+                        llvm_symbol: Some(llvm_symbol),
+                        resolved_llvm_symbol: None,
+                        llvm_arguments: llvm_arguments.clone(),
+                        llvm_results: llvm_results.clone(),
+                        pure: false,
+                        memory: "none".into(),
+                        convergent: true,
+                        execution_scope: "warp".into(),
+                        minimum_ptx: minimum_ptx.into(),
+                        minimum_sm: Some("sm_89".into()),
+                        ptx_result: rust_result.clone(),
+                        targets: "all".into(),
+                        ptx_isa_version: "9.3".into(),
+                        ptx_isa_section: "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
+                        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
+                        lowering: "generated_register_mma".into(),
+                        backend_lowerings: [
+                            (IntrinsicBackend::LlvmNvptx, &admission.llvm_evidence_profile),
+                            (IntrinsicBackend::LibNvvm, &admission.libnvvm_evidence_profile),
+                        ]
+                        .into_iter()
+                        .map(|(backend, evidence_profile)| OverlayBackendLowering {
+                            backend,
+                            mechanism: BackendLoweringMechanism::InlinePtx,
+                            evidence_profile: evidence_profile.clone(),
+                            targets: None,
+                            minimum_ptx: Some(minimum_ptx.into()),
+                            minimum_sm: Some("sm_89".into()),
+                        })
+                        .collect(),
+                        packed_atomic: None,
+                        redux: None,
+                        vote: None,
+                        active_mask: None,
+                        warp_match: None,
+                        warp_barrier: None,
+                        warp_shuffle: None,
+                        dot_product: None,
+                        packed_alu: None,
+                integer_minmax: None,
+                        packed_conversion: None,
+                        scalar_conversion: None,
+                        scalar_arithmetic: None,
+                        scalar_math: None,
+                        extended_minmax: None,
+                        cp_async_copy: None,
+                        cp_async_control: None,
+                        cp_async_mbarrier: None,
+                        mbarrier_basic: None,
+                        movmatrix: None,
+                        mbarrier_extended: None,
+                        register_mma: Some(mma),
+                        sparse_mma: None,
+                        prmt: None,
+                        cluster_barrier: None,
+                        wgmma_control: None,
+                        special_register: None,
+                        debug_control: None,
+                        cluster_memory: None,
+                        clc: None,
+                        tma: None,
+                        tcgen05: None,
+                        ldmatrix_variant: None,
+                        ldmatrix_safety: None,
+                        ldmatrix_adapter: None,
+                        selected_address_space: None,
+                        expected_ptx: InstructionPattern {
+                            mnemonic: "mma".into(),
+                            modifiers: ["sync", "aligned", shape_name, "row", "col", scalar, a, b, scalar]
+                                .into_iter()
+                                .map(Into::into)
+                                .collect(),
+                            operands: [result_count, a_count, b_count, result_count]
+                                .map(|length| OperandPattern::RegisterList { length })
+                                .into(),
+                        },
+                        summary: format!(
+                            "Multiplies warp-distributed {a} A and {b} B fragments and adds an {scalar} accumulator."
+                        ),
+                    });
+                }
+            }
+        }
+    }
+    ensure!(records.len() == admission.product_count);
+    Ok(records)
+}
+
+pub(in crate::resolve) const REGISTER_MMA_AMPERE_FLOAT_VARIANTS: [RegisterMmaAmpereFloatVariant;
+    5] = [
+    RegisterMmaAmpereFloatVariant {
+        shape: RegisterMmaShape::M16n8k4,
+        accumulator: RegisterMmaAccumulator::F32,
+        element: RegisterMmaElement::Tf32,
+    },
+    RegisterMmaAmpereFloatVariant {
+        shape: RegisterMmaShape::M16n8k8,
+        accumulator: RegisterMmaAccumulator::F16,
+        element: RegisterMmaElement::F16,
+    },
+    RegisterMmaAmpereFloatVariant {
+        shape: RegisterMmaShape::M16n8k8,
+        accumulator: RegisterMmaAccumulator::F32,
+        element: RegisterMmaElement::Bf16,
+    },
+    RegisterMmaAmpereFloatVariant {
+        shape: RegisterMmaShape::M16n8k8,
+        accumulator: RegisterMmaAccumulator::F32,
+        element: RegisterMmaElement::F16,
+    },
+    RegisterMmaAmpereFloatVariant {
+        shape: RegisterMmaShape::M16n8k16,
+        accumulator: RegisterMmaAccumulator::F16,
+        element: RegisterMmaElement::F16,
+    },
+];
+
+pub(in crate::resolve) fn expand_register_mma_ampere_float_admission(
+    admission: &RegisterMmaAmpereFloatAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "Ampere floating-point MMA runtime validation requires GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "Ampere floating-point MMA admission requires both backend evidence profiles"
+    );
+    ensure!(
+        admission.product_count == REGISTER_MMA_AMPERE_FLOAT_VARIANTS.len()
+            && admission.variants == REGISTER_MMA_AMPERE_FLOAT_VARIANTS,
+        "Ampere floating-point MMA admission must retain the five reviewed variants in canonical order"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let adapter = match (variant.shape, variant.accumulator) {
+                (RegisterMmaShape::M16n8k4, RegisterMmaAccumulator::F32)
+                | (RegisterMmaShape::M16n8k8, RegisterMmaAccumulator::F32) => {
+                    RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
+                }
+                (RegisterMmaShape::M16n8k8, RegisterMmaAccumulator::F16) => {
+                    RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32
+                }
+                (RegisterMmaShape::M16n8k16, RegisterMmaAccumulator::F16) => {
+                    RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32
+                }
+                _ => bail!("Ampere floating-point MMA admission contains an unsupported carrier"),
+            };
+            let mma = RegisterMma {
+                shape: variant.shape,
+                operation: RegisterMmaOperation::Multiply,
+                kind: None,
+                accumulator: variant.accumulator,
+                a_element: variant.element,
+                b_element: variant.element,
+                a_layout: RegisterMmaLayout::Row,
+                b_layout: RegisterMmaLayout::Col,
+                overflow: RegisterMmaOverflow::NotApplicable,
+                participation: RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+                adapter,
+                compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+                runtime_validation: admission.runtime_validation,
+            };
+            let recipe = register_mma_recipe(&mma).with_context(|| {
+                "Ampere floating-point MMA admission requests a variant outside the closed recipe set"
+            })?;
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: String::new(),
+                operation_key: recipe.operation_key.into(),
+                family: "register_mma".into(),
+                source: None,
+                source_record: Some(recipe.source_record.into()),
+                rust_module: "matrix".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments: recipe.rust_arguments.iter().map(|value| (*value).into()).collect(),
+                rust_result: recipe.rust_result.into(),
+                safe: false,
+                must_use: true,
+                safe_allowlist_reason: None,
+                public_rust_path: format!("cuda_intrinsics::matrix::{}", recipe.id),
+                compatibility_rust_paths: vec![format!("cuda_device::wmma::{}", recipe.id)],
+                dialect_op_type: recipe.dialect_op_type.into(),
+                dialect_op_name: recipe.dialect_op_name.into(),
+                dialect_operands: recipe.dialect_operands.iter().map(|value| (*value).into()).collect(),
+                dialect_results: recipe.dialect_results.iter().map(|value| (*value).into()).collect(),
+                llvm_symbol: Some(recipe.llvm_symbol.into()),
+                resolved_llvm_symbol: None,
+                llvm_arguments: recipe.llvm_arguments.iter().map(|value| (*value).into()).collect(),
+                llvm_results: recipe.llvm_results.iter().map(|value| (*value).into()).collect(),
+                pure: false,
+                memory: "none".into(),
+                convergent: true,
+                execution_scope: "warp".into(),
+                minimum_ptx: recipe.minimum_ptx.into(),
+                minimum_sm: Some(recipe.minimum_sm.into()),
+                ptx_result: recipe.rust_result.into(),
+                targets: "all".into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section: "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
+                lowering: "generated_register_mma".into(),
+                backend_lowerings: [
+                    (IntrinsicBackend::LlvmNvptx, &admission.llvm_evidence_profile),
+                    (IntrinsicBackend::LibNvvm, &admission.libnvvm_evidence_profile),
+                ]
+                .into_iter()
+                .map(|(backend, evidence_profile)| OverlayBackendLowering {
+                    backend,
+                    mechanism: BackendLoweringMechanism::InlinePtx,
+                    evidence_profile: evidence_profile.clone(),
+                    targets: None,
+                    minimum_ptx: Some(recipe.minimum_ptx.into()),
+                    minimum_sm: Some(recipe.minimum_sm.into()),
+                })
+                .collect(),
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: Some(mma),
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: "mma".into(),
+                    modifiers: recipe.ptx_modifiers.iter().map(|value| (*value).into()).collect(),
+                    operands: recipe
+                        .ptx_register_counts
+                        .map(|length| OperandPattern::RegisterList { length })
+                        .into(),
+                },
+                summary: format!("Executes the {} Ampere floating-point MMA form.", recipe.id),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn expand_register_mma_binary_admission(
+    admission: &RegisterMmaBinaryAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    use RegisterMmaAdapter::{
+        C2I32A1U32B1U32ToD2I32, C4I32A2U32B1U32ToD4I32, C4I32A4U32B2U32ToD4I32,
+    };
+    use RegisterMmaLayout::{Col, Row};
+    use RegisterMmaOperation::{AndPopc, XorPopc};
+    use RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes;
+    use RegisterMmaShape::{M8n8k128, M16n8k128, M16n8k256};
+
+    ensure!(
+        !admission.variants.is_empty(),
+        "compact binary MMA admission has no variants"
+    );
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "binary MMA runtime validation may be marked executed only with GPU evidence"
+    );
+
+    let mut seen = BTreeSet::new();
+    let mut records = Vec::with_capacity(admission.variants.len());
+    for variant in &admission.variants {
+        ensure!(
+            seen.insert((variant.shape, variant.operation)),
+            "compact binary MMA admission contains a duplicate variant"
+        );
+        ensure!(
+            matches!(variant.operation, AndPopc | XorPopc),
+            "compact binary MMA admission contains a non-binary operation"
+        );
+        let adapter = match variant.shape {
+            M8n8k128 => C2I32A1U32B1U32ToD2I32,
+            M16n8k128 => C4I32A2U32B1U32ToD4I32,
+            M16n8k256 => C4I32A4U32B2U32ToD4I32,
+            _ => bail!("compact binary MMA admission contains an unsupported shape"),
+        };
+        let mma = RegisterMma {
+            shape: variant.shape,
+            operation: variant.operation,
+            kind: None,
+            accumulator: RegisterMmaAccumulator::S32,
+            a_element: RegisterMmaElement::B1,
+            b_element: RegisterMmaElement::B1,
+            a_layout: Row,
+            b_layout: Col,
+            overflow: RegisterMmaOverflow::Wrapping,
+            participation: AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+            adapter,
+            compatibility_source: RegisterMmaCompatibilitySource::GeneratedStub,
+            runtime_validation: admission.runtime_validation,
+        };
+        let recipe = register_mma_recipe(&mma).with_context(
+            || "compact binary MMA admission requests a variant outside the closed recipe set",
+        )?;
+        let operation = match variant.operation {
+            AndPopc => "AND and population count",
+            XorPopc => "XOR and population count",
+            RegisterMmaOperation::Multiply => unreachable!(),
+        };
+        let summary = format!(
+            "Computes warp-distributed binary matrix products with {operation}, then adds a wrapping s32 accumulator."
+        );
+
+        records.push(OverlayIntrinsic {
+            id: recipe.id.into(),
+            abi_id: recipe.abi_id.into(),
+            operation_key: recipe.operation_key.into(),
+            family: "register_mma".into(),
+            source: None,
+            source_record: Some(recipe.source_record.into()),
+            rust_module: "matrix".into(),
+            rust_name: recipe.id.into(),
+            rust_arguments: recipe
+                .rust_arguments
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            rust_result: recipe.rust_result.into(),
+            safe: false,
+            must_use: true,
+            safe_allowlist_reason: None,
+            public_rust_path: format!("cuda_intrinsics::matrix::{}", recipe.id),
+            compatibility_rust_paths: vec![format!("cuda_device::wmma::{}", recipe.id)],
+            dialect_op_type: recipe.dialect_op_type.into(),
+            dialect_op_name: recipe.dialect_op_name.into(),
+            dialect_operands: recipe
+                .dialect_operands
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            dialect_results: recipe
+                .dialect_results
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            llvm_symbol: Some(recipe.llvm_symbol.into()),
+            resolved_llvm_symbol: None,
+            llvm_arguments: recipe
+                .llvm_arguments
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            llvm_results: recipe
+                .llvm_results
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            pure: false,
+            memory: "none".into(),
+            convergent: true,
+            execution_scope: "warp".into(),
+            minimum_ptx: recipe.minimum_ptx.into(),
+            minimum_sm: Some(recipe.minimum_sm.into()),
+            ptx_result: recipe.rust_result.into(),
+            targets: "all".into(),
+            ptx_isa_version: "9.3".into(),
+            ptx_isa_section: "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma".into(),
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma".into(),
+            lowering: "generated_register_mma".into(),
+            backend_lowerings: vec![
+                OverlayBackendLowering {
+                    backend: IntrinsicBackend::LlvmNvptx,
+                    mechanism: BackendLoweringMechanism::InlinePtx,
+                    evidence_profile: admission.llvm_evidence_profile.clone(),
+                    targets: None,
+                    minimum_ptx: Some(recipe.minimum_ptx.into()),
+                    minimum_sm: Some(recipe.minimum_sm.into()),
+                },
+                OverlayBackendLowering {
+                    backend: IntrinsicBackend::LibNvvm,
+                    mechanism: BackendLoweringMechanism::InlinePtx,
+                    evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                    targets: None,
+                    minimum_ptx: Some(recipe.minimum_ptx.into()),
+                    minimum_sm: Some(recipe.minimum_sm.into()),
+                },
+            ],
+            packed_atomic: None,
+            redux: None,
+            vote: None,
+            active_mask: None,
+            warp_match: None,
+            warp_barrier: None,
+            warp_shuffle: None,
+            dot_product: None,
+            packed_alu: None,
+        integer_minmax: None,
+            packed_conversion: None,
+            scalar_conversion: None,
+            scalar_arithmetic: None,
+            scalar_math: None,
+            extended_minmax: None,
+            cp_async_copy: None,
+            cp_async_control: None,
+            cp_async_mbarrier: None,
+            mbarrier_basic: None,
+            movmatrix: None,
+            mbarrier_extended: None,
+            register_mma: Some(mma),
+            sparse_mma: None,
+            prmt: None,
+            cluster_barrier: None,
+            wgmma_control: None,
+            special_register: None,
+            debug_control: None,
+            cluster_memory: None,
+            clc: None,
+            tma: None,
+            tcgen05: None,
+            ldmatrix_variant: None,
+            ldmatrix_safety: None,
+            ldmatrix_adapter: None,
+            selected_address_space: None,
+            expected_ptx: InstructionPattern {
+                mnemonic: "mma".into(),
+                modifiers: recipe
+                    .ptx_modifiers
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                operands: recipe
+                    .ptx_register_counts
+                    .map(|length| OperandPattern::RegisterList { length })
+                    .into(),
+            },
+            summary,
+        });
+    }
+    Ok(records)
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs b/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs
new file mode 100644
index 0000000000..4749642eb8
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs
@@ -0,0 +1,907 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, OverlayBackendLowering,
+    OverlayIntrinsic, RuntimeValidation, SparseMma, SparseMmaAccumulator, SparseMmaAdapter,
+    SparseMmaCompatibilitySource, SparseMmaElement, SparseMmaF8F6F4Admission,
+    SparseMmaF8F6F4F16Admission, SparseMmaIntegerAdmission, SparseMmaLayout, SparseMmaLlvmAdapter,
+    SparseMmaMetadata, SparseMmaOverflow, SparseMmaParticipation, SparseMmaSelector,
+    SparseMmaShape,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use crate::resolve::guards::*;
+
+pub(in crate::resolve) const SPARSE_MMA_F8F6F4_TARGETS: &str = "sm_120a|sm_120f|sm_121a|sm_121f";
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct SparseMmaCarrierRecipe {
+    pub(in crate::resolve) adapter: SparseMmaAdapter,
+    pub(in crate::resolve) llvm_adapter: SparseMmaLlvmAdapter,
+    pub(in crate::resolve) accumulator: SparseMmaAccumulator,
+    pub(in crate::resolve) selector: SparseMmaSelector,
+    pub(in crate::resolve) a_registers: usize,
+    pub(in crate::resolve) b_registers: usize,
+}
+
+impl SparseMmaCarrierRecipe {
+    fn accumulator_registers(self) -> usize {
+        match self.accumulator {
+            SparseMmaAccumulator::F16 => 2,
+            SparseMmaAccumulator::F32 | SparseMmaAccumulator::S32 => 4,
+        }
+    }
+
+    fn operand_count(self) -> usize {
+        self.accumulator_registers() + self.a_registers + self.b_registers + 2
+    }
+
+    fn selector_index(self) -> usize {
+        self.operand_count() - 1
+    }
+
+    fn selector_upper_exclusive(self) -> u8 {
+        match self.selector {
+            SparseMmaSelector::ImmediateZeroOrOne => 2,
+            SparseMmaSelector::ImmediateZero => 1,
+        }
+    }
+
+    pub(in crate::resolve) fn rust_arguments(self) -> Vec<String> {
+        let accumulator = match self.accumulator {
+            SparseMmaAccumulator::F16 => "[u32; 2]",
+            SparseMmaAccumulator::F32 => "[f32; 4]",
+            SparseMmaAccumulator::S32 => "[i32; 4]",
+        };
+        vec![
+            accumulator.into(),
+            format!("[u32; {}]", self.a_registers),
+            format!("[u32; {}]", self.b_registers),
+            "u32".into(),
+            "u32".into(),
+        ]
+    }
+
+    pub(in crate::resolve) fn dialect_operands(self) -> Vec<String> {
+        let accumulator = match self.accumulator {
+            SparseMmaAccumulator::F16 => "i32",
+            SparseMmaAccumulator::F32 => "f32",
+            SparseMmaAccumulator::S32 => "i32",
+        };
+        let accumulator_registers = self.accumulator_registers();
+        std::iter::repeat_n(accumulator.to_owned(), accumulator_registers)
+            .chain(std::iter::repeat_n(
+                "u32".to_owned(),
+                self.operand_count() - accumulator_registers,
+            ))
+            .collect()
+    }
+
+    pub(in crate::resolve) fn llvm_arguments(self) -> Vec<String> {
+        let accumulator = match self.accumulator {
+            SparseMmaAccumulator::F16 => "v2f16",
+            SparseMmaAccumulator::F32 => "f32",
+            SparseMmaAccumulator::S32 => "i32",
+        };
+        std::iter::repeat_n("i32".to_owned(), self.a_registers + self.b_registers)
+            .chain(std::iter::repeat_n(
+                accumulator.to_owned(),
+                self.accumulator_registers(),
+            ))
+            .chain(std::iter::repeat_n("i32".to_owned(), 2))
+            .collect()
+    }
+
+    fn rust_result(self) -> String {
+        match self.accumulator {
+            SparseMmaAccumulator::F16 => "[u32; 2]",
+            SparseMmaAccumulator::F32 => "[f32; 4]",
+            SparseMmaAccumulator::S32 => "[i32; 4]",
+        }
+        .into()
+    }
+
+    fn dialect_results(self) -> Vec<String> {
+        match self.accumulator {
+            SparseMmaAccumulator::F16 => vec!["i32".into(); 2],
+            SparseMmaAccumulator::F32 => vec!["f32".into(); 4],
+            SparseMmaAccumulator::S32 => vec!["i32".into(); 4],
+        }
+    }
+
+    fn llvm_results(self) -> Vec<String> {
+        match self.accumulator {
+            SparseMmaAccumulator::F16 => vec!["v2f16".into(); 2],
+            SparseMmaAccumulator::F32 => vec!["f32".into(); 4],
+            SparseMmaAccumulator::S32 => vec!["i32".into(); 4],
+        }
+    }
+
+    pub(in crate::resolve) fn expected_ptx_operands(self) -> Vec<OperandPattern> {
+        vec![
+            OperandPattern::RegisterList {
+                length: self.accumulator_registers(),
+            },
+            OperandPattern::RegisterList {
+                length: self.a_registers,
+            },
+            OperandPattern::RegisterList {
+                length: self.b_registers,
+            },
+            OperandPattern::RegisterList {
+                length: self.accumulator_registers(),
+            },
+            OperandPattern::Register,
+            OperandPattern::Immediate,
+        ]
+    }
+
+    fn imported_properties(self) -> Vec<String> {
+        let selector = self.selector_index();
+        vec![
+            format!("ImmArg<arg{selector}>"),
+            "IntrNoCallback".into(),
+            "IntrNoMem".into(),
+            format!("Range<arg{selector},0,{}>", self.selector_upper_exclusive()),
+        ]
+    }
+}
+
+pub(in crate::resolve) fn sparse_mma_carrier_recipe(
+    shape: SparseMmaShape,
+    a_element: SparseMmaElement,
+    b_element: SparseMmaElement,
+) -> Option<SparseMmaCarrierRecipe> {
+    use SparseMmaElement::{E2m1, E2m3, E3m2, E4m3, E5m2, S4, S8, U4, U8};
+    use SparseMmaShape::{M16n8k32, M16n8k64, M16n8k128};
+
+    match (shape, a_element, b_element) {
+        (M16n8k32, S8 | U8, S8 | U8) | (M16n8k64, S4 | U4, S4 | U4) => {
+            Some(SparseMmaCarrierRecipe {
+                adapter: SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32,
+                llvm_adapter: SparseMmaLlvmAdapter::A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32,
+                accumulator: SparseMmaAccumulator::S32,
+                selector: SparseMmaSelector::ImmediateZeroOrOne,
+                a_registers: 2,
+                b_registers: 2,
+            })
+        }
+        (M16n8k64, S8 | U8, S8 | U8) => Some(SparseMmaCarrierRecipe {
+            adapter: SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32,
+            llvm_adapter: SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32,
+            accumulator: SparseMmaAccumulator::S32,
+            selector: SparseMmaSelector::ImmediateZero,
+            a_registers: 4,
+            b_registers: 4,
+        }),
+        (M16n8k128, S4 | U4, S4 | U4) => Some(SparseMmaCarrierRecipe {
+            adapter: SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32,
+            llvm_adapter: SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32,
+            accumulator: SparseMmaAccumulator::S32,
+            selector: SparseMmaSelector::ImmediateZero,
+            a_registers: 4,
+            b_registers: 4,
+        }),
+        (M16n8k64, E2m1 | E2m3 | E3m2 | E4m3 | E5m2, E2m1 | E2m3 | E3m2 | E4m3 | E5m2) => {
+            Some(SparseMmaCarrierRecipe {
+                adapter: SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32,
+                llvm_adapter: SparseMmaLlvmAdapter::A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32,
+                accumulator: SparseMmaAccumulator::F32,
+                selector: SparseMmaSelector::ImmediateZero,
+                a_registers: 4,
+                b_registers: 4,
+            })
+        }
+        _ => None,
+    }
+}
+
+pub(in crate::resolve) fn sparse_mma_f8f6f4_f16_carrier_recipe(
+    shape: SparseMmaShape,
+    a_element: SparseMmaElement,
+    b_element: SparseMmaElement,
+) -> Option<SparseMmaCarrierRecipe> {
+    use SparseMmaElement::{E2m1, E2m3, E3m2, E4m3, E5m2};
+
+    if shape != SparseMmaShape::M16n8k64
+        || !matches!(a_element, E2m1 | E2m3 | E3m2 | E4m3 | E5m2)
+        || !matches!(b_element, E2m1 | E2m3 | E3m2 | E4m3 | E5m2)
+    {
+        return None;
+    }
+    Some(SparseMmaCarrierRecipe {
+        adapter: SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32,
+        llvm_adapter: SparseMmaLlvmAdapter::A4I32B4I32C2V2F16MetadataI32SelectorI32ToD2V2F16,
+        accumulator: SparseMmaAccumulator::F16,
+        selector: SparseMmaSelector::ImmediateZero,
+        a_registers: 4,
+        b_registers: 4,
+    })
+}
+
+pub(in crate::resolve) struct SparseMmaIdentity {
+    pub(in crate::resolve) id: String,
+    pub(in crate::resolve) operation_key: String,
+    pub(in crate::resolve) source_record: String,
+    pub(in crate::resolve) llvm_symbol: String,
+    pub(in crate::resolve) ptx_modifiers: Vec<&'static str>,
+}
+
+pub(in crate::resolve) struct SparseMmaRecipe {
+    pub(in crate::resolve) identity: SparseMmaIdentity,
+    pub(in crate::resolve) carrier: SparseMmaCarrierRecipe,
+}
+
+pub(in crate::resolve) fn sparse_mma_shape_name(shape: SparseMmaShape) -> &'static str {
+    match shape {
+        SparseMmaShape::M16n8k32 => "m16n8k32",
+        SparseMmaShape::M16n8k64 => "m16n8k64",
+        SparseMmaShape::M16n8k128 => "m16n8k128",
+    }
+}
+
+pub(in crate::resolve) fn sparse_mma_element_name(element: SparseMmaElement) -> &'static str {
+    match element {
+        SparseMmaElement::E2m1 => "e2m1",
+        SparseMmaElement::E2m3 => "e2m3",
+        SparseMmaElement::E3m2 => "e3m2",
+        SparseMmaElement::E4m3 => "e4m3",
+        SparseMmaElement::E5m2 => "e5m2",
+        SparseMmaElement::S4 => "s4",
+        SparseMmaElement::U4 => "u4",
+        SparseMmaElement::S8 => "s8",
+        SparseMmaElement::U8 => "u8",
+    }
+}
+
+pub(in crate::resolve) fn sparse_mma_identity(mma: &SparseMma) -> SparseMmaIdentity {
+    let shape = sparse_mma_shape_name(mma.shape);
+    let a_element = sparse_mma_element_name(mma.a_element);
+    let b_element = sparse_mma_element_name(mma.b_element);
+    if matches!(
+        mma.accumulator,
+        SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32
+    ) {
+        let scalar = match mma.accumulator {
+            SparseMmaAccumulator::F16 => "f16",
+            SparseMmaAccumulator::F32 => "f32",
+            SparseMmaAccumulator::S32 => unreachable!(),
+        };
+        return SparseMmaIdentity {
+            id: format!(
+                "mma_sp_ordered_metadata_{shape}_kind_f8f6f4_{scalar}_{a_element}_{b_element}_{scalar}"
+            ),
+            operation_key: format!(
+                "matrix.mma.sp.{shape}.row.col.kind_f8f6f4.{scalar}.{a_element}.{b_element}.{scalar}.not_applicable.ordered_metadata"
+            ),
+            source_record: format!(
+                "int_nvvm_mma_sp_ordered_metadata_{shape}_row_col_kind_f8f6f4_{scalar}_{a_element}_{b_element}_{scalar}"
+            ),
+            llvm_symbol: format!(
+                "llvm.nvvm.mma.sp.ordered.metadata.{shape}.row.col.kind.f8f6f4.{scalar}.{a_element}.{b_element}.{scalar}"
+            ),
+            ptx_modifiers: vec![
+                "sp::ordered_metadata",
+                "sync",
+                "aligned",
+                shape,
+                "row",
+                "col",
+                "kind::f8f6f4",
+                scalar,
+                a_element,
+                b_element,
+                scalar,
+            ],
+        };
+    }
+    let compact_elements = if mma.a_element == mma.b_element {
+        a_element.to_owned()
+    } else {
+        format!("{a_element}_{b_element}")
+    };
+    let dotted_elements = if mma.a_element == mma.b_element {
+        a_element.to_owned()
+    } else {
+        format!("{a_element}.{b_element}")
+    };
+    let metadata_id_prefix = match mma.metadata {
+        SparseMmaMetadata::Standard => "",
+        SparseMmaMetadata::Ordered => "ordered_metadata_",
+    };
+    let metadata_source_prefix = metadata_id_prefix;
+    let metadata_symbol_prefix = match mma.metadata {
+        SparseMmaMetadata::Standard => "",
+        SparseMmaMetadata::Ordered => "ordered.metadata.",
+    };
+    let metadata_key = match mma.metadata {
+        SparseMmaMetadata::Standard => "standard_metadata",
+        SparseMmaMetadata::Ordered => "ordered_metadata",
+    };
+    let overflow_id_suffix = match mma.overflow {
+        SparseMmaOverflow::NotApplicable => unreachable!("integer sparse MMA has overflow"),
+        SparseMmaOverflow::Wrapping => "",
+        SparseMmaOverflow::Satfinite => "_satfinite",
+    };
+    let overflow_source_prefix = match mma.overflow {
+        SparseMmaOverflow::NotApplicable => unreachable!("integer sparse MMA has overflow"),
+        SparseMmaOverflow::Wrapping => "",
+        SparseMmaOverflow::Satfinite => "satfinite_",
+    };
+    let overflow_symbol_prefix = match mma.overflow {
+        SparseMmaOverflow::NotApplicable => unreachable!("integer sparse MMA has overflow"),
+        SparseMmaOverflow::Wrapping => "",
+        SparseMmaOverflow::Satfinite => "satfinite.",
+    };
+    let overflow_key = match mma.overflow {
+        SparseMmaOverflow::NotApplicable => unreachable!("integer sparse MMA has overflow"),
+        SparseMmaOverflow::Wrapping => "wrapping",
+        SparseMmaOverflow::Satfinite => "satfinite",
+    };
+
+    let mut ptx_modifiers = vec![
+        match mma.metadata {
+            SparseMmaMetadata::Standard => "sp",
+            SparseMmaMetadata::Ordered => "sp::ordered_metadata",
+        },
+        "sync",
+        "aligned",
+        shape,
+        "row",
+        "col",
+    ];
+    if mma.overflow == SparseMmaOverflow::Satfinite {
+        ptx_modifiers.push("satfinite");
+    }
+    ptx_modifiers.extend(["s32", a_element, b_element, "s32"]);
+
+    SparseMmaIdentity {
+        id: format!(
+            "mma_sp_{metadata_id_prefix}{shape}_s32_{compact_elements}{overflow_id_suffix}"
+        ),
+        operation_key: format!(
+            "matrix.mma.sp.{shape}.row.col.s32.{a_element}.{b_element}.s32.{overflow_key}.{metadata_key}"
+        ),
+        source_record: format!(
+            "int_nvvm_mma_sp_{metadata_source_prefix}{shape}_row_col_{overflow_source_prefix}{compact_elements}"
+        ),
+        llvm_symbol: format!(
+            "llvm.nvvm.mma.sp.{metadata_symbol_prefix}{shape}.row.col.{overflow_symbol_prefix}{dotted_elements}"
+        ),
+        ptx_modifiers,
+    }
+}
+
+pub(in crate::resolve) fn sparse_mma_recipe(mma: &SparseMma) -> Option<SparseMmaRecipe> {
+    let carrier = if mma.accumulator == SparseMmaAccumulator::F16 {
+        sparse_mma_f8f6f4_f16_carrier_recipe(mma.shape, mma.a_element, mma.b_element)?
+    } else {
+        sparse_mma_carrier_recipe(mma.shape, mma.a_element, mma.b_element)?
+    };
+
+    let scalar_contract = match carrier.accumulator {
+        SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 => {
+            mma.accumulator == carrier.accumulator
+                && mma.overflow == SparseMmaOverflow::NotApplicable
+                && mma.metadata == SparseMmaMetadata::Ordered
+        }
+        SparseMmaAccumulator::S32 => {
+            mma.accumulator == SparseMmaAccumulator::S32
+                && matches!(
+                    mma.overflow,
+                    SparseMmaOverflow::Wrapping | SparseMmaOverflow::Satfinite
+                )
+        }
+    };
+    if !scalar_contract
+        || mma.a_layout != SparseMmaLayout::Row
+        || mma.b_layout != SparseMmaLayout::Col
+        || mma.selector != carrier.selector
+        || mma.participation
+            != SparseMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes
+        || mma.adapter != carrier.adapter
+        || mma.llvm_adapter != carrier.llvm_adapter
+        || mma.compatibility_source != SparseMmaCompatibilitySource::GeneratedStub
+    {
+        return None;
+    }
+
+    Some(SparseMmaRecipe {
+        identity: sparse_mma_identity(mma),
+        carrier,
+    })
+}
+
+pub(in crate::resolve) fn sparse_mma_minimum_ptx(mma: &SparseMma) -> &'static str {
+    if matches!(
+        mma.accumulator,
+        SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32
+    ) {
+        return "8.7";
+    }
+    match mma.metadata {
+        SparseMmaMetadata::Standard => "7.1",
+        SparseMmaMetadata::Ordered => "8.5",
+    }
+}
+
+pub(in crate::resolve) fn sparse_mma_hardware(
+    mma: &SparseMma,
+) -> (&'static str, Option<&'static str>) {
+    match mma.accumulator {
+        SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 => (SPARSE_MMA_F8F6F4_TARGETS, None),
+        SparseMmaAccumulator::S32 => ("all", Some("sm_80")),
+    }
+}
+
+pub(in crate::resolve) fn sparse_mma_ptx_section(_: SparseMmaMetadata) -> &'static str {
+    "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp"
+}
+
+pub(in crate::resolve) fn expand_sparse_mma_integer_admission(
+    admission: &SparseMmaIntegerAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        !admission.variants.is_empty(),
+        "compact sparse integer MMA admission has no variants"
+    );
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "sparse integer MMA runtime validation may be marked executed only with GPU evidence"
+    );
+
+    let mut seen = BTreeSet::new();
+    let mut records = Vec::with_capacity(admission.variants.len());
+    for variant in &admission.variants {
+        ensure!(
+            seen.insert((
+                variant.shape,
+                variant.a_element,
+                variant.b_element,
+                variant.overflow,
+            )),
+            "compact sparse integer MMA admission contains a duplicate variant"
+        );
+        let carrier = sparse_mma_carrier_recipe(
+            variant.shape,
+            variant.a_element,
+            variant.b_element,
+        )
+        .with_context(
+            || "compact sparse integer MMA admission uses unsupported or mixed-width elements",
+        )?;
+        let mma = SparseMma {
+            shape: variant.shape,
+            accumulator: SparseMmaAccumulator::S32,
+            a_element: variant.a_element,
+            b_element: variant.b_element,
+            a_layout: SparseMmaLayout::Row,
+            b_layout: SparseMmaLayout::Col,
+            overflow: variant.overflow,
+            metadata: admission.metadata,
+            selector: carrier.selector,
+            participation:
+                SparseMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+            adapter: carrier.adapter,
+            llvm_adapter: carrier.llvm_adapter,
+            compatibility_source: SparseMmaCompatibilitySource::GeneratedStub,
+            runtime_validation: admission.runtime_validation,
+        };
+        let recipe = sparse_mma_recipe(&mma).with_context(
+            || "compact sparse integer MMA admission requests a variant outside the closed recipe set",
+        )?;
+        let signedness = |element| match element {
+            SparseMmaElement::S4 => "signed",
+            SparseMmaElement::U4 => "unsigned",
+            SparseMmaElement::S8 => "signed",
+            SparseMmaElement::U8 => "unsigned",
+            _ => unreachable!("integer admission rejects floating formats"),
+        };
+        let width = match (variant.a_element, variant.b_element) {
+            (
+                SparseMmaElement::S4 | SparseMmaElement::U4,
+                SparseMmaElement::S4 | SparseMmaElement::U4,
+            ) => "INT4",
+            (
+                SparseMmaElement::S8 | SparseMmaElement::U8,
+                SparseMmaElement::S8 | SparseMmaElement::U8,
+            ) => "INT8",
+            _ => unreachable!("carrier selection rejects mixed element widths"),
+        };
+        let overflow = match variant.overflow {
+            SparseMmaOverflow::NotApplicable => {
+                unreachable!("integer admission rejects inapplicable overflow")
+            }
+            SparseMmaOverflow::Wrapping => "wrapping",
+            SparseMmaOverflow::Satfinite => "saturating",
+        };
+        let metadata = match admission.metadata {
+            SparseMmaMetadata::Standard => "",
+            SparseMmaMetadata::Ordered => " with ordered sparsity metadata",
+        };
+        let summary = format!(
+            "Multiplies warp-distributed sparse {} A and {} B {width} fragments{metadata} and adds a {overflow} s32 accumulator.",
+            signedness(variant.a_element),
+            signedness(variant.b_element),
+        );
+        records.push(sparse_mma_overlay_record(
+            String::new(),
+            mma,
+            recipe,
+            &admission.llvm_evidence_profile,
+            &admission.libnvvm_evidence_profile,
+            summary,
+        ));
+    }
+    Ok(records)
+}
+
+pub(in crate::resolve) fn expand_sparse_mma_f8f6f4_admission(
+    admission: &SparseMmaF8F6F4Admission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "sparse f8f6f4 MMA runtime validation may be marked executed only with GPU evidence"
+    );
+
+    let formats = vec![
+        SparseMmaElement::E2m1,
+        SparseMmaElement::E2m3,
+        SparseMmaElement::E3m2,
+        SparseMmaElement::E4m3,
+        SparseMmaElement::E5m2,
+    ];
+    ensure!(
+        admission.a_elements == formats,
+        "compact sparse f8f6f4 MMA admission must list the canonical five A formats"
+    );
+    ensure!(
+        admission.b_elements == formats,
+        "compact sparse f8f6f4 MMA admission must list the canonical five B formats"
+    );
+    ensure!(
+        admission.product_count
+            == admission
+                .a_elements
+                .len()
+                .checked_mul(admission.b_elements.len())
+                .context("compact sparse f8f6f4 MMA admission product count overflow")?
+            && admission.product_count == 25,
+        "compact sparse f8f6f4 MMA admission product_count must be exactly 25"
+    );
+    let mut records = Vec::with_capacity(admission.product_count);
+    for &a_element in &admission.a_elements {
+        for &b_element in &admission.b_elements {
+            let carrier = sparse_mma_carrier_recipe(SparseMmaShape::M16n8k64, a_element, b_element)
+                .with_context(
+                    || "compact sparse f8f6f4 MMA admission uses an unsupported format",
+                )?;
+            ensure!(
+                carrier.accumulator == SparseMmaAccumulator::F32,
+                "compact sparse f8f6f4 MMA admission contains an integer format"
+            );
+            let mma = SparseMma {
+                shape: SparseMmaShape::M16n8k64,
+                accumulator: SparseMmaAccumulator::F32,
+                a_element,
+                b_element,
+                a_layout: SparseMmaLayout::Row,
+                b_layout: SparseMmaLayout::Col,
+                overflow: SparseMmaOverflow::NotApplicable,
+                metadata: SparseMmaMetadata::Ordered,
+                selector: carrier.selector,
+                participation:
+                    SparseMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+                adapter: carrier.adapter,
+                llvm_adapter: carrier.llvm_adapter,
+                compatibility_source: SparseMmaCompatibilitySource::GeneratedStub,
+                runtime_validation: admission.runtime_validation,
+            };
+            let recipe = sparse_mma_recipe(&mma).with_context(|| {
+            "compact sparse f8f6f4 MMA admission requests a variant outside the closed recipe set"
+        })?;
+            let summary = format!(
+                "Multiplies warp-distributed sparse {} A and {} B fragments and adds an f32 accumulator.",
+                sparse_mma_element_name(a_element),
+                sparse_mma_element_name(b_element),
+            );
+            records.push(sparse_mma_overlay_record(
+                String::new(),
+                mma,
+                recipe,
+                &admission.llvm_evidence_profile,
+                &admission.libnvvm_evidence_profile,
+                summary,
+            ));
+        }
+    }
+    ensure!(records.len() == admission.product_count);
+    Ok(records)
+}
+
+pub(in crate::resolve) const SPARSE_MMA_F8F6F4_ELEMENTS: [SparseMmaElement; 5] = [
+    SparseMmaElement::E2m1,
+    SparseMmaElement::E2m3,
+    SparseMmaElement::E3m2,
+    SparseMmaElement::E4m3,
+    SparseMmaElement::E5m2,
+];
+
+pub(in crate::resolve) fn expand_sparse_mma_f8f6f4_f16_admission(
+    admission: &SparseMmaF8F6F4F16Admission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "sparse f8f6f4 F16 MMA runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "sparse f8f6f4 F16 MMA admission requires both backend evidence profiles"
+    );
+    ensure!(
+        admission.a_elements == SPARSE_MMA_F8F6F4_ELEMENTS
+            && admission.b_elements == SPARSE_MMA_F8F6F4_ELEMENTS
+            && admission.product_count == 25,
+        "sparse f8f6f4 F16 MMA admission must contain the canonical 5 by 5 element matrix"
+    );
+
+    let mut records = Vec::with_capacity(admission.product_count);
+    for &a_element in &admission.a_elements {
+        for &b_element in &admission.b_elements {
+            let carrier = sparse_mma_f8f6f4_f16_carrier_recipe(
+                SparseMmaShape::M16n8k64,
+                a_element,
+                b_element,
+            )
+            .context("compact sparse f8f6f4 F16 MMA admission uses an unsupported format")?;
+            let mma = SparseMma {
+                shape: SparseMmaShape::M16n8k64,
+                accumulator: SparseMmaAccumulator::F16,
+                a_element,
+                b_element,
+                a_layout: SparseMmaLayout::Row,
+                b_layout: SparseMmaLayout::Col,
+                overflow: SparseMmaOverflow::NotApplicable,
+                metadata: SparseMmaMetadata::Ordered,
+                selector: SparseMmaSelector::ImmediateZero,
+                participation:
+                    SparseMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes,
+                adapter: carrier.adapter,
+                llvm_adapter: carrier.llvm_adapter,
+                compatibility_source: SparseMmaCompatibilitySource::GeneratedStub,
+                runtime_validation: admission.runtime_validation,
+            };
+            let recipe = sparse_mma_recipe(&mma).context(
+                "compact sparse f8f6f4 F16 MMA admission requests a variant outside the closed recipe set",
+            )?;
+            let summary = format!(
+                "Multiplies warp-distributed sparse {} A and {} B fragments and adds a packed F16 accumulator.",
+                sparse_mma_element_name(a_element),
+                sparse_mma_element_name(b_element),
+            );
+            records.push(sparse_mma_overlay_record(
+                String::new(),
+                mma,
+                recipe,
+                &admission.llvm_evidence_profile,
+                &admission.libnvvm_evidence_profile,
+                summary,
+            ));
+        }
+    }
+    ensure!(records.len() == admission.product_count);
+    Ok(records)
+}
+
+pub(in crate::resolve) fn sparse_mma_overlay_record(
+    abi_id: String,
+    mma: SparseMma,
+    recipe: SparseMmaRecipe,
+    llvm_evidence_profile: &str,
+    libnvvm_evidence_profile: &str,
+    summary: String,
+) -> OverlayIntrinsic {
+    let identity = &recipe.identity;
+    let minimum_ptx = sparse_mma_minimum_ptx(&mma);
+    let (targets, minimum_sm) = sparse_mma_hardware(&mma);
+    OverlayIntrinsic {
+        id: identity.id.clone(),
+        abi_id,
+        operation_key: identity.operation_key.clone(),
+        family: "sparse_mma".into(),
+        source: None,
+        source_record: Some(identity.source_record.clone()),
+        rust_module: "matrix".into(),
+        rust_name: identity.id.clone(),
+        rust_arguments: recipe.carrier.rust_arguments(),
+        rust_result: recipe.carrier.rust_result(),
+        safe: false,
+        must_use: true,
+        safe_allowlist_reason: None,
+        public_rust_path: format!("cuda_intrinsics::matrix::{}", identity.id),
+        compatibility_rust_paths: vec![format!("cuda_device::wmma::{}", identity.id)],
+        dialect_op_type: "SparseMmaOp".into(),
+        dialect_op_name: "nvvm.sparse_mma".into(),
+        dialect_operands: recipe.carrier.dialect_operands(),
+        dialect_results: recipe.carrier.dialect_results(),
+        llvm_symbol: Some(identity.llvm_symbol.clone()),
+        resolved_llvm_symbol: None,
+        llvm_arguments: recipe.carrier.llvm_arguments(),
+        llvm_results: recipe.carrier.llvm_results(),
+        pure: false,
+        memory: "none".into(),
+        convergent: true,
+        execution_scope: "warp".into(),
+        minimum_ptx: minimum_ptx.into(),
+        minimum_sm: minimum_sm.map(str::to_owned),
+        ptx_result: recipe.carrier.rust_result(),
+        targets: targets.into(),
+        ptx_isa_version: "9.3".into(),
+        ptx_isa_section: sparse_mma_ptx_section(mma.metadata).into(),
+        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp".into(),
+        lowering: "generated_sparse_mma".into(),
+        backend_lowerings: [
+            (IntrinsicBackend::LlvmNvptx, llvm_evidence_profile),
+            (IntrinsicBackend::LibNvvm, libnvvm_evidence_profile),
+        ]
+        .into_iter()
+        .map(|(backend, evidence_profile)| OverlayBackendLowering {
+            backend,
+            mechanism: BackendLoweringMechanism::InlinePtx,
+            evidence_profile: evidence_profile.into(),
+            targets: None,
+            minimum_ptx: Some(minimum_ptx.into()),
+            minimum_sm: minimum_sm.map(str::to_owned),
+        })
+        .collect(),
+        packed_atomic: None,
+        redux: None,
+        vote: None,
+        active_mask: None,
+        warp_match: None,
+        warp_barrier: None,
+        warp_shuffle: None,
+        dot_product: None,
+        packed_alu: None,
+        integer_minmax: None,
+        packed_conversion: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cp_async_copy: None,
+        cp_async_control: None,
+        cp_async_mbarrier: None,
+        mbarrier_basic: None,
+        movmatrix: None,
+        mbarrier_extended: None,
+        register_mma: None,
+        sparse_mma: Some(mma),
+        prmt: None,
+        cluster_barrier: None,
+        wgmma_control: None,
+        special_register: None,
+        debug_control: None,
+        cluster_memory: None,
+        clc: None,
+        tma: None,
+        tcgen05: None,
+        ldmatrix_variant: None,
+        ldmatrix_safety: None,
+        ldmatrix_adapter: None,
+        selected_address_space: None,
+        expected_ptx: InstructionPattern {
+            mnemonic: "mma".into(),
+            modifiers: identity
+                .ptx_modifiers
+                .iter()
+                .map(|value| (*value).into())
+                .collect(),
+            operands: recipe.carrier.expected_ptx_operands(),
+        },
+        summary,
+    }
+}
+
+pub(in crate::resolve) fn validate_sparse_mma_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let mma = policy
+        .sparse_mma
+        .as_ref()
+        .with_context(|| format!("{} has no closed sparse-MMA contract", policy.id))?;
+    let recipe = sparse_mma_recipe(mma)
+        .with_context(|| format!("{} requests an unsupported sparse-MMA variant", policy.id))?;
+    let identity = &recipe.identity;
+    let minimum_ptx = sparse_mma_minimum_ptx(mma);
+    let (targets, minimum_sm) = sparse_mma_hardware(mma);
+    ensure!(
+        policy.id == identity.id
+            && policy.operation_key == identity.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(identity.source_record.as_str())
+            && policy.llvm_symbol.as_deref() == Some(identity.llvm_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} sparse-MMA identity does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "matrix"
+            && policy.rust_name == identity.id
+            && policy.public_rust_path == format!("cuda_intrinsics::matrix::{}", identity.id)
+            && policy.rust_arguments == recipe.carrier.rust_arguments()
+            && policy.rust_result == recipe.carrier.rust_result()
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.compatibility_rust_paths == [format!("cuda_device::wmma::{}", identity.id)],
+        "{} must preserve its unsafe must-use Rust sparse-MMA API",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == "SparseMmaOp"
+            && policy.dialect_op_name == "nvvm.sparse_mma"
+            && policy.dialect_operands == recipe.carrier.dialect_operands()
+            && policy.dialect_results == recipe.carrier.dialect_results()
+            && policy.llvm_arguments == recipe.carrier.llvm_arguments()
+            && policy.llvm_results == recipe.carrier.llvm_results()
+            && policy.ptx_result == recipe.carrier.rust_result()
+            && policy.lowering == "generated_sparse_mma",
+        "{} sparse-MMA carrier or lowering adapter disagrees with its recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "none"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == minimum_ptx
+            && policy.minimum_sm.as_deref() == minimum_sm
+            && policy.targets == targets,
+        "{} sparse-MMA effects or target floor disagree with PTX",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == sparse_mma_ptx_section(mma.metadata)
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp",
+        "{} sparse-MMA PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA_SP"]
+            && declaration.properties == recipe.carrier.imported_properties()
+            && declaration.selections.len() == 1
+            && (!matches!(
+                mma.accumulator,
+                SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32
+            ) || declaration.selections[0].predicates == ["Subtarget->hasMMABlockScale()"])
+            && selection_matches_policy(policy, &declaration.selections[0])?,
+        "{} imported sparse MMA declaration changed its class, immediate range, properties, or exact selection contract",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "mma"
+            && policy.expected_ptx.modifiers == identity.ptx_modifiers
+            && policy.expected_ptx.operands == recipe.carrier.expected_ptx_operands(),
+        "{} expected PTX does not match its exact sparse-MMA spelling",
+        policy.id
+    );
+    ensure_exact_inline_ptx_backends(
+        policy,
+        [
+            (IntrinsicBackend::LlvmNvptx, minimum_ptx, minimum_sm),
+            (IntrinsicBackend::LibNvvm, minimum_ptx, minimum_sm),
+        ],
+        "sparse MMA",
+    )?;
+    ensure_no_other_family_contract(policy, "sparse MMA")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/mma/validate.rs b/crates/cuda-intrinsics-gen/src/resolve/families/mma/validate.rs
new file mode 100644
index 0000000000..b76e4112bd
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/mma/validate.rs
@@ -0,0 +1,736 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, OverlayIntrinsic, RegisterMma,
+    RegisterMmaAccumulator, RegisterMmaAdapter, RegisterMmaCompatibilitySource, RegisterMmaKind,
+    RegisterMmaLayout, RegisterMmaOperation, RegisterMmaOverflow, RegisterMmaParticipation,
+    RegisterMmaShape, RuntimeValidation,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, bail, ensure};
+use std::collections::BTreeSet;
+
+use super::*;
+use crate::resolve::guards::*;
+
+pub(in crate::resolve) fn validate_register_mma_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let mma = policy
+        .register_mma
+        .as_ref()
+        .with_context(|| format!("{} has no closed register-MMA contract", policy.id))?;
+    match mma.kind {
+        Some(RegisterMmaKind::Standard) => {
+            return validate_register_mma_fp8_policy(policy, declaration, mma);
+        }
+        Some(RegisterMmaKind::F8f6f4) => {
+            return validate_register_mma_f8f6f4_policy(policy, declaration, mma);
+        }
+        Some(RegisterMmaKind::Mxf8f6f4) => {
+            return validate_register_mma_mxf8f6f4_policy(policy, declaration, mma);
+        }
+        None if register_mma_f8f6f4_element_name(mma.a_element).is_some()
+            || register_mma_f8f6f4_element_name(mma.b_element).is_some() =>
+        {
+            return validate_register_mma_f8f6f4_policy(policy, declaration, mma);
+        }
+        None => {}
+    }
+    let recipe = register_mma_recipe(mma)
+        .with_context(|| format!("{} requests an unsupported register-MMA variant", policy.id))?;
+    let abi_matches = matches!(
+        recipe.id,
+        "mma_m16n8k4_f32_tf32"
+            | "mma_m16n8k8_f16_f16"
+            | "mma_m16n8k8_f32_bf16"
+            | "mma_m16n8k8_f32_f16"
+            | "mma_m16n8k16_f16_f16"
+    ) || policy.abi_id == recipe.abi_id;
+    ensure!(
+        policy.id == recipe.id
+            && abi_matches
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} register-MMA identity does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "matrix"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == recipe.rust_arguments
+            && policy.rust_result == recipe.rust_result
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.compatibility_rust_paths == [format!("cuda_device::wmma::{}", recipe.id)],
+        "{} must preserve its unsafe must-use Rust MMA API",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == recipe.dialect_operands
+            && policy.dialect_results == recipe.dialect_results
+            && policy.llvm_arguments == recipe.llvm_arguments
+            && policy.llvm_results == recipe.llvm_results
+            && policy.ptx_result == recipe.rust_result
+            && mma.adapter == recipe.adapter
+            && mma.compatibility_source == recipe.compatibility_source
+            && policy.lowering == "generated_register_mma",
+        "{} register-MMA carrier or lowering adapter disagrees with its recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "none"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
+            && policy.targets == "all",
+        "{} register-MMA effects or target floor disagree with PTX",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma",
+        "{} register-MMA PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.classes.iter().any(|class| class == "NVVM_MMA")
+            && declaration.properties == ["IntrNoCallback", "IntrNoMem"]
+            && declaration.selections.len() == 1
+            && selection_matches_policy(policy, &declaration.selections[0])?,
+        "{} imported MMA declaration changed its class, properties, or exact selection contract",
+        policy.id
+    );
+    // These are imported facts. The BF16 selection is underconstrained.
+    let ampere_float_predicates = match recipe.id {
+        "mma_m16n8k4_f32_tf32" | "mma_m16n8k16_f16_f16" => Some([
+            "Subtarget->getSmVersion() >= 80",
+            "Subtarget->getPTXVersion() >= 70",
+        ]),
+        "mma_m16n8k8_f16_f16" | "mma_m16n8k8_f32_bf16" | "mma_m16n8k8_f32_f16" => Some([
+            "Subtarget->getPTXVersion() >= 65",
+            "Subtarget->getSmVersion() >= 75",
+        ]),
+        _ => None,
+    };
+    if let Some(predicates) = ampere_float_predicates {
+        let selection = &declaration.selections[0];
+        ensure!(
+            declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA"]
+                && selection.predicates == predicates
+                && selection.constraints.is_empty()
+                && mma.kind.is_none()
+                && mma.runtime_validation == RuntimeValidation::Unexecuted,
+            "{} imported Ampere floating-point MMA contract changed",
+            policy.id
+        );
+    }
+    ensure!(
+        policy.expected_ptx.mnemonic == "mma"
+            && policy.expected_ptx.modifiers == recipe.ptx_modifiers
+            && policy.expected_ptx.operands
+                == recipe
+                    .ptx_register_counts
+                    .map(|length| OperandPattern::RegisterList { length }),
+        "{} expected PTX does not match its exact register-MMA spelling",
+        policy.id
+    );
+    ensure_exact_inline_ptx_backends(
+        policy,
+        [
+            (
+                IntrinsicBackend::LlvmNvptx,
+                recipe.minimum_ptx,
+                Some(recipe.minimum_sm),
+            ),
+            (
+                IntrinsicBackend::LibNvvm,
+                recipe.minimum_ptx,
+                Some(recipe.minimum_sm),
+            ),
+        ],
+        "register MMA",
+    )?;
+    ensure_no_other_family_contract(policy, "register MMA")?;
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_register_mma_fp8_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+    mma: &RegisterMma,
+) -> Result<()> {
+    ensure!(
+        REGISTER_MMA_FP8_SHAPES.contains(&mma.shape),
+        "{} has an unsupported standard FP8 shape",
+        policy.id
+    );
+    ensure!(
+        REGISTER_MMA_FP8_ACCUMULATORS.contains(&mma.accumulator),
+        "{} has an unsupported standard FP8 accumulator",
+        policy.id
+    );
+    ensure!(
+        REGISTER_MMA_FP8_ELEMENTS.contains(&mma.a_element),
+        "{} has an unsupported standard FP8 A element",
+        policy.id
+    );
+    ensure!(
+        REGISTER_MMA_FP8_ELEMENTS.contains(&mma.b_element),
+        "{} has an unsupported standard FP8 B element",
+        policy.id
+    );
+    let (shape_name, a_count, b_count) = register_mma_fp8_shape_contract(mma.shape)?;
+    let minimum_ptx = register_mma_fp8_minimum_ptx(mma.shape, mma.accumulator);
+    let a = register_mma_fp8_element_name(mma.a_element).expect("validated A element");
+    let b = register_mma_fp8_element_name(mma.b_element).expect("validated B element");
+    let (
+        scalar,
+        rust_arguments,
+        rust_result,
+        dialect_operands,
+        dialect_results,
+        llvm_arguments,
+        llvm_results,
+        adapter,
+    ) = match mma.accumulator {
+        RegisterMmaAccumulator::F16 => (
+            "f16",
+            vec![
+                "[u32; 2]".into(),
+                format!("[u32; {a_count}]"),
+                if b_count == 1 {
+                    "u32".into()
+                } else {
+                    "[u32; 2]".into()
+                },
+            ],
+            "[u32; 2]".to_owned(),
+            [
+                vec!["i32".to_owned(); 2],
+                vec!["i32".to_owned(); a_count],
+                vec!["i32".to_owned(); b_count],
+            ]
+            .concat(),
+            vec!["i32".to_owned(); 2],
+            [
+                vec!["i32".to_owned(); a_count + b_count],
+                vec!["v2f16".to_owned(); 2],
+            ]
+            .concat(),
+            vec!["v2f16".to_owned(); 2],
+            if mma.shape == RegisterMmaShape::M16n8k16 {
+                RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32
+            } else {
+                RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32
+            },
+        ),
+        RegisterMmaAccumulator::F32 => (
+            "f32",
+            vec![
+                "[f32; 4]".into(),
+                format!("[u32; {a_count}]"),
+                if b_count == 1 {
+                    "u32".into()
+                } else {
+                    "[u32; 2]".into()
+                },
+            ],
+            "[f32; 4]".to_owned(),
+            [
+                vec!["f32".to_owned(); 4],
+                vec!["i32".to_owned(); a_count],
+                vec!["i32".to_owned(); b_count],
+            ]
+            .concat(),
+            vec!["f32".to_owned(); 4],
+            [
+                vec!["i32".to_owned(); a_count + b_count],
+                vec!["f32".to_owned(); 4],
+            ]
+            .concat(),
+            vec!["f32".to_owned(); 4],
+            if mma.shape == RegisterMmaShape::M16n8k16 {
+                RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
+            } else {
+                RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32
+            },
+        ),
+        _ => unreachable!("validated accumulator"),
+    };
+    let expected_id = format!("mma_{shape_name}_fp8_{scalar}_{a}_{b}");
+    let expected_source = format!("int_nvvm_mma_{shape_name}_row_col_{scalar}_{a}_{b}_{scalar}");
+    let expected_symbol = format!("llvm.nvvm.mma.{shape_name}.row.col.{scalar}.{a}.{b}.{scalar}");
+
+    ensure!(
+        policy.id == expected_id
+            && policy.operation_key
+                == format!(
+                    "matrix.mma.{shape_name}.row.col.standard_fp8.{scalar}.{a}.{b}.{scalar}"
+                )
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(expected_source.as_str())
+            && policy.llvm_symbol.as_deref() == Some(expected_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} standard FP8 MMA identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "matrix"
+            && policy.rust_name == expected_id
+            && policy.rust_arguments == rust_arguments
+            && policy.rust_result == rust_result
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::matrix::{expected_id}")
+            && policy.compatibility_rust_paths == [format!("cuda_device::wmma::{expected_id}")],
+        "{} must preserve its unsafe must-use standard FP8 API",
+        policy.id
+    );
+    ensure!(
+        mma.kind == Some(RegisterMmaKind::Standard)
+            && mma.operation == RegisterMmaOperation::Multiply
+            && mma.a_layout == RegisterMmaLayout::Row
+            && mma.b_layout == RegisterMmaLayout::Col
+            && mma.overflow == RegisterMmaOverflow::NotApplicable
+            && mma.participation
+                == RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes
+            && mma.adapter == adapter
+            && mma.compatibility_source == RegisterMmaCompatibilitySource::GeneratedStub
+            && mma.runtime_validation == RuntimeValidation::Unexecuted
+            && policy.dialect_op_type == "RegisterMmaOp"
+            && policy.dialect_op_name == "nvvm.register_mma"
+            && policy.dialect_operands == dialect_operands
+            && policy.dialect_results == dialect_results
+            && policy.llvm_arguments == llvm_arguments
+            && policy.llvm_results == llvm_results
+            && policy.ptx_result == rust_result
+            && policy.lowering == "generated_register_mma",
+        "{} standard FP8 MMA carrier or lowering changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "none"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == minimum_ptx
+            && policy.minimum_sm.as_deref() == Some("sm_89")
+            && policy.targets == "all",
+        "{} standard FP8 effects or target floor changed",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma",
+        "{} standard FP8 PTX provenance changed",
+        policy.id
+    );
+    let [selection] = declaration.selections.as_slice() else {
+        bail!(
+            "{} must retain exactly one standard FP8 selection",
+            policy.id
+        );
+    };
+    let expected_predicates = if mma.shape == RegisterMmaShape::M16n8k16 {
+        [
+            "Subtarget->getSmVersion() >= 89",
+            "Subtarget->getPTXVersion() >= 87",
+        ]
+    } else {
+        [
+            "Subtarget->getSmVersion() >= 89",
+            "Subtarget->getPTXVersion() >= 84",
+        ]
+    };
+    ensure!(
+        declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA"]
+            && declaration.properties == ["IntrNoCallback", "IntrNoMem"]
+            && selection_matches_policy(policy, selection)?
+            && selection.predicates == expected_predicates
+            && selection.constraints.is_empty(),
+        "{} imported standard FP8 declaration or selection changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx
+            == InstructionPattern {
+                mnemonic: "mma".into(),
+                modifiers: [
+                    "sync", "aligned", shape_name, "row", "col", scalar, a, b, scalar
+                ]
+                .into_iter()
+                .map(Into::into)
+                .collect(),
+                operands: [
+                    dialect_results.len(),
+                    a_count,
+                    b_count,
+                    dialect_results.len()
+                ]
+                .map(|length| OperandPattern::RegisterList { length })
+                .into(),
+            },
+        "{} expected standard FP8 PTX changed",
+        policy.id
+    );
+    ensure_exact_inline_ptx_backends(
+        policy,
+        [
+            (IntrinsicBackend::LlvmNvptx, minimum_ptx, Some("sm_89")),
+            (IntrinsicBackend::LibNvvm, minimum_ptx, Some("sm_89")),
+        ],
+        "standard FP8 register MMA",
+    )?;
+    ensure_no_other_family_contract(policy, "standard FP8 register MMA")?;
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_register_mma_f8f6f4_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+    mma: &RegisterMma,
+) -> Result<()> {
+    let contract = register_mma_f8f6f4_contract(mma.accumulator)?;
+    let a = register_mma_f8f6f4_element_name(mma.a_element)
+        .with_context(|| format!("{} has a non-f8f6f4 A format", policy.id))?;
+    let b = register_mma_f8f6f4_element_name(mma.b_element)
+        .with_context(|| format!("{} has a non-f8f6f4 B format", policy.id))?;
+    let scalar = contract.scalar_name;
+    let expected_id = format!("mma_m16n8k32_{scalar}_{a}_{b}");
+    let expected_source =
+        format!("int_nvvm_mma_m16n8k32_row_col_kind_f8f6f4_{scalar}_{a}_{b}_{scalar}");
+    let expected_symbol =
+        format!("llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.{scalar}.{a}.{b}.{scalar}");
+    ensure!(
+        policy.id == expected_id
+            && policy.operation_key
+                == format!("matrix.mma.m16n8k32.row.col.kind_f8f6f4.{scalar}.{a}.{b}.{scalar}")
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(expected_source.as_str())
+            && policy.llvm_symbol.as_deref() == Some(expected_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} dense f8f6f4 MMA identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "matrix"
+            && policy.rust_name == expected_id
+            && policy.rust_arguments == contract.rust_arguments
+            && policy.rust_result == contract.rust_result
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::matrix::{expected_id}")
+            && policy.compatibility_rust_paths == [format!("cuda_device::wmma::{expected_id}")],
+        "{} must preserve the unsafe must-use dense f8f6f4 API",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == "RegisterMmaOp"
+            && policy.dialect_op_name == "nvvm.register_mma"
+            && policy.dialect_operands == contract.dialect_operands
+            && policy.dialect_results == contract.dialect_results
+            && policy.llvm_arguments == contract.llvm_arguments
+            && policy.llvm_results == contract.llvm_results
+            && policy.ptx_result == contract.rust_result
+            && mma.shape == RegisterMmaShape::M16n8k32
+            && matches!(mma.kind, None | Some(RegisterMmaKind::F8f6f4))
+            && mma.operation == RegisterMmaOperation::Multiply
+            && mma.accumulator == contract.accumulator
+            && mma.a_layout == RegisterMmaLayout::Row
+            && mma.b_layout == RegisterMmaLayout::Col
+            && mma.overflow == RegisterMmaOverflow::NotApplicable
+            && mma.participation
+                == RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes
+            && mma.adapter == contract.adapter
+            && mma.compatibility_source == RegisterMmaCompatibilitySource::GeneratedStub
+            && mma.runtime_validation == RuntimeValidation::Unexecuted
+            && policy.lowering == "generated_register_mma",
+        "{} dense f8f6f4 carrier or lowering changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "none"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == "8.7"
+            && policy.minimum_sm.is_none()
+            && policy.targets == REGISTER_MMA_F8F6F4_TARGETS,
+        "{} dense f8f6f4 effects or exact target set changed",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma",
+        "{} dense f8f6f4 PTX provenance changed",
+        policy.id
+    );
+    let [selection] = declaration.selections.as_slice() else {
+        bail!(
+            "{} must retain exactly one imported dense f8f6f4 instruction selection",
+            policy.id
+        );
+    };
+    ensure!(
+        declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA"]
+            && declaration.properties == ["IntrNoCallback", "IntrNoMem"]
+            && selection_matches_policy(policy, selection)?
+            && selection.predicates == ["Subtarget->hasMMABlockScale()"]
+            && selection.constraints.is_empty(),
+        "{} imported dense f8f6f4 declaration or selection changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx
+            == InstructionPattern {
+                mnemonic: "mma".into(),
+                modifiers: [
+                    "sync",
+                    "aligned",
+                    "m16n8k32",
+                    "row",
+                    "col",
+                    "kind::f8f6f4",
+                    scalar,
+                    a,
+                    b,
+                    scalar,
+                ]
+                .into_iter()
+                .map(Into::into)
+                .collect(),
+                operands: contract
+                    .ptx_register_counts
+                    .map(|length| OperandPattern::RegisterList { length })
+                    .into(),
+            },
+        "{} expected dense f8f6f4 PTX changed",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ])
+            && policy.backend_lowerings.iter().all(|lowering| {
+                lowering.targets.is_none()
+                    && lowering.minimum_ptx.is_none()
+                    && lowering.minimum_sm.is_none()
+                    && !lowering.evidence_profile.trim().is_empty()
+            }),
+        "{} must inherit the exact reviewed target set on both inline-PTX routes",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "dense f8f6f4 register MMA")?;
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_register_mma_mxf8f6f4_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+    mma: &RegisterMma,
+) -> Result<()> {
+    let a = register_mma_f8f6f4_element_name(mma.a_element)
+        .with_context(|| format!("{} has a non-mxf8f6f4 A format", policy.id))?;
+    let b = register_mma_f8f6f4_element_name(mma.b_element)
+        .with_context(|| format!("{} has a non-mxf8f6f4 B format", policy.id))?;
+    let expected_id = format!("mma_m16n8k32_mxf8f6f4_f32_{a}_{b}");
+    let expected_source =
+        format!("int_nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_{a}_{b}_f32_ue8m0");
+    let expected_symbol =
+        format!("llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.{a}.{b}.f32.ue8m0");
+    let rust_arguments = [
+        "[f32; 4]", "[u32; 4]", "[u32; 2]", "u32", "u16", "u16", "u32", "u16", "u16",
+    ];
+    let dialect_operands = [
+        "f32", "f32", "f32", "f32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i16", "i16",
+        "i32", "i16", "i16",
+    ];
+    let llvm_arguments = [
+        "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32", "i32", "i16", "i16",
+        "i32", "i16", "i16",
+    ];
+    let results = ["f32", "f32", "f32", "f32"];
+    ensure!(
+        policy.id == expected_id
+            && policy.operation_key
+                == format!(
+                    "matrix.mma.m16n8k32.row.col.kind_mxf8f6f4.scale_vec_1x.f32.{a}.{b}.f32.ue8m0"
+                )
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(expected_source.as_str())
+            && policy.llvm_symbol.as_deref() == Some(expected_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} dense mxf8f6f4 MMA identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "matrix"
+            && policy.rust_name == expected_id
+            && policy.rust_arguments == rust_arguments
+            && policy.rust_result == "[f32; 4]"
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::matrix::{expected_id}")
+            && policy.compatibility_rust_paths == [format!("cuda_device::wmma::{expected_id}")],
+        "{} must preserve the unsafe must-use dense mxf8f6f4 API",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == "RegisterMmaOp"
+            && policy.dialect_op_name == "nvvm.register_mma"
+            && policy.dialect_operands == dialect_operands
+            && policy.dialect_results == results
+            && policy.llvm_arguments == llvm_arguments
+            && policy.llvm_results == results
+            && policy.ptx_result == "[f32; 4]"
+            && mma.shape == RegisterMmaShape::M16n8k32
+            && mma.kind == Some(RegisterMmaKind::Mxf8f6f4)
+            && mma.operation == RegisterMmaOperation::Multiply
+            && mma.accumulator == RegisterMmaAccumulator::F32
+            && mma.a_layout == RegisterMmaLayout::Row
+            && mma.b_layout == RegisterMmaLayout::Col
+            && mma.overflow == RegisterMmaOverflow::NotApplicable
+            && mma.participation
+                == RegisterMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes
+            && mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
+            && mma.compatibility_source == RegisterMmaCompatibilitySource::GeneratedStub
+            && mma.runtime_validation == RuntimeValidation::Unexecuted
+            && policy.lowering == "generated_register_mma",
+        "{} dense mxf8f6f4 carrier or lowering changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "none"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == "8.7"
+            && policy.minimum_sm.is_none()
+            && policy.targets == REGISTER_MMA_F8F6F4_TARGETS,
+        "{} dense mxf8f6f4 effects or exact target set changed",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == "9.7.15.5.14 Multiply-and-Accumulate Instruction: mma"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma",
+        "{} dense mxf8f6f4 PTX provenance changed",
+        policy.id
+    );
+    let [selection] = declaration.selections.as_slice() else {
+        bail!(
+            "{} must retain exactly one imported dense mxf8f6f4 instruction selection",
+            policy.id
+        );
+    };
+    ensure!(
+        declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA_BLOCK_SCALE"]
+            && declaration.properties == ["IntrNoCallback", "IntrNoMem"]
+            && selection_matches_policy(policy, selection)?
+            && selection.predicates == ["Subtarget->hasMMABlockScale()"]
+            && selection.constraints.is_empty(),
+        "{} imported dense mxf8f6f4 declaration or selection changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx
+            == InstructionPattern {
+                mnemonic: "mma".into(),
+                modifiers: [
+                    "sync",
+                    "aligned",
+                    "m16n8k32",
+                    "row",
+                    "col",
+                    "kind::mxf8f6f4",
+                    "block_scale",
+                    "f32",
+                    a,
+                    b,
+                    "f32",
+                    "ue8m0",
+                ]
+                .into_iter()
+                .map(Into::into)
+                .collect(),
+                operands: vec![
+                    OperandPattern::RegisterList { length: 4 },
+                    OperandPattern::RegisterList { length: 4 },
+                    OperandPattern::RegisterList { length: 2 },
+                    OperandPattern::RegisterList { length: 4 },
+                    OperandPattern::Register,
+                    OperandPattern::RegisterList { length: 2 },
+                    OperandPattern::Register,
+                    OperandPattern::RegisterList { length: 2 },
+                ],
+            },
+        "{} expected dense mxf8f6f4 PTX changed",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ])
+            && policy.backend_lowerings.iter().all(|lowering| {
+                lowering.targets.is_none()
+                    && lowering.minimum_ptx.is_none()
+                    && lowering.minimum_sm.is_none()
+                    && !lowering.evidence_profile.trim().is_empty()
+            }),
+        "{} must inherit the exact reviewed target set on both inline-PTX routes",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "dense mxf8f6f4 register MMA")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/mod.rs b/crates/cuda-intrinsics-gen/src/resolve/families/mod.rs
new file mode 100644
index 0000000000..797c0b060d
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/mod.rs
@@ -0,0 +1,48 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+pub(super) mod clc;
+pub(super) mod cluster;
+pub(super) mod cp_async;
+pub(super) mod debug_wgmma;
+pub(super) mod execution_control;
+pub(super) mod matrix_move;
+pub(super) mod mbarrier_extended;
+pub(super) mod minmax;
+pub(super) mod mma;
+pub(super) mod packed_alu;
+pub(super) mod packed_conversion;
+pub(super) mod prmt;
+pub(super) mod redux_dotprod;
+pub(super) mod scalar_arithmetic;
+pub(super) mod scalar_conversion;
+pub(super) mod scalar_math;
+pub(super) mod special_register;
+pub(super) mod tcgen05;
+pub(super) mod threadfence;
+pub(super) mod tma;
+pub(super) mod warp;
+
+pub(super) use clc::*;
+pub(super) use cluster::*;
+pub(super) use cp_async::*;
+pub(super) use debug_wgmma::*;
+pub(super) use execution_control::*;
+pub(super) use matrix_move::*;
+pub(super) use mbarrier_extended::*;
+pub(super) use minmax::*;
+pub(super) use mma::*;
+pub(super) use packed_alu::*;
+pub(super) use packed_conversion::*;
+pub(super) use prmt::*;
+pub(super) use redux_dotprod::*;
+pub(super) use scalar_arithmetic::*;
+pub(super) use scalar_conversion::*;
+pub(super) use scalar_math::*;
+pub(super) use special_register::*;
+pub(super) use tcgen05::*;
+pub(super) use threadfence::*;
+pub(super) use tma::*;
+pub(super) use warp::*;
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/packed_alu.rs b/crates/cuda-intrinsics-gen/src/resolve/families/packed_alu.rs
new file mode 100644
index 0000000000..91e49c5d5f
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/packed_alu.rs
@@ -0,0 +1,1158 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, IntrinsicSource,
+    OverlayIntrinsic, PackedAluAdapter, PackedAluFormat, PackedAluOperation,
+    PackedAtomicAccessContract, PackedAtomicAdapter, PackedAtomicAtomicity,
+    PackedAtomicCodegenContract, PackedAtomicFormat, PackedAtomicOperation, PackedAtomicOrdering,
+    PackedAtomicPointerContract, PackedAtomicReturnContract, PackedAtomicRounding,
+    PackedAtomicScope, PackedAtomicScopeContract, PackedAtomicStateSpace, PackedAtomicSubnormal,
+};
+use crate::ptx::OperandPattern;
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use crate::resolve::guards::*;
+
+pub(in crate::resolve) fn validate_packed_atomic_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+) -> Result<()> {
+    let packed = policy
+        .packed_atomic
+        .as_ref()
+        .with_context(|| format!("{} has no closed packed-atomic contract", policy.id))?;
+    ensure!(
+        packed.operation == PackedAtomicOperation::Add
+            && packed.state_space == PackedAtomicStateSpace::Global
+            && packed.ordering == PackedAtomicOrdering::Relaxed
+            && packed.scope == PackedAtomicScope::Gpu
+            && packed.rounding == PackedAtomicRounding::NearestEven
+            && packed.subnormal == PackedAtomicSubnormal::Preserve
+            && packed.atomicity == PackedAtomicAtomicity::PerElement
+            && packed.pointer_contract == PackedAtomicPointerContract::MutableGlobalU32Aligned4
+            && packed.access_contract
+                == PackedAtomicAccessContract::NoMixedWholeWordOrNonAtomicAccess
+            && packed.scope_contract == PackedAtomicScopeContract::RacingAtomicsMutuallyInclusive
+            && packed.codegen_contract == PackedAtomicCodegenContract::ExactNativeInstruction
+            && packed.return_contract
+                == PackedAtomicReturnContract::OldValuesPerElementMayBeNoncoherent
+            && packed.adapter == PackedAtomicAdapter::OldPackedU32,
+        "{} requests an unsupported packed-atomic semantic or safety contract",
+        policy.id
+    );
+    let (format, native_sm, minimum_ptx, minimum_sm, public_name) = match packed.format {
+        PackedAtomicFormat::F16x2 => ("f16x2", 60, "6.2", "sm_70", "atom_add_f16x2"),
+        PackedAtomicFormat::Bf16x2 => ("bf16x2", 90, "7.8", "sm_90", "atom_add_bf16x2"),
+    };
+    ensure!(
+        packed.native_minimum_sm == native_sm,
+        "{} PTX-native hardware floor does not match the selected packed format",
+        policy.id
+    );
+    ensure!(
+        source
+            == &IntrinsicSource::PtxNative {
+                instruction: format!("atom.global.add.noftz.{format}"),
+            },
+        "{} PTX-native source does not match its packed format",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "atomic"
+            && policy.rust_name == public_name
+            && policy.rust_arguments == ["*mut u32", "u32"]
+            && policy.rust_result == "u32"
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::atomic::{public_name}")
+            && policy.compatibility_rust_paths == [format!("cuda_device::atomic::{public_name}")],
+        "{} must preserve the unsafe must-use packed atomic raw/compatibility API",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == "PackedAtomicAddOp"
+            && policy.dialect_op_name == "nvvm.packed_atomic_add"
+            && policy.dialect_operands == ["ptr", "i32"]
+            && policy.dialect_results == ["i32"]
+            && policy.lowering == "generated_packed_atomic_inline_ptx",
+        "{} is outside the one closed packed-atomic dialect recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read_write"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == minimum_ptx
+            && policy.minimum_sm.as_deref() == Some(minimum_sm)
+            && policy.targets == "all"
+            && policy.ptx_result == "u32"
+            && policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} packed-atomic effects, carrier, or native target floor disagree",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "atom"
+            && policy.expected_ptx.modifiers == ["global", "add", "noftz", format]
+            && policy.expected_ptx.operands
+                == [
+                    OperandPattern::Register,
+                    OperandPattern::Address,
+                    OperandPattern::Register,
+                ],
+        "{} expected PTX must match the exact packed global add spelling",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        backend_pairs
+            == BTreeSet::from([
+                (
+                    IntrinsicBackend::LlvmNvptx,
+                    BackendLoweringMechanism::InlinePtx,
+                ),
+                (
+                    IntrinsicBackend::LibNvvm,
+                    BackendLoweringMechanism::InlinePtx,
+                ),
+            ]),
+        "{} must define exactly the reviewed LLVM-NVPTX and libNVVM inline-PTX routes",
+        policy.id
+    );
+    for lowering in &policy.backend_lowerings {
+        let expected_sm = match (packed.format, lowering.backend) {
+            (PackedAtomicFormat::F16x2, IntrinsicBackend::LlvmNvptx) => "sm_70",
+            (PackedAtomicFormat::F16x2, IntrinsicBackend::LibNvvm) => "sm_75",
+            (PackedAtomicFormat::Bf16x2, _) => "sm_90",
+        };
+        ensure!(
+            lowering.minimum_ptx.as_deref() == Some(minimum_ptx)
+                && lowering.minimum_sm.as_deref() == Some(expected_sm)
+                && !lowering.evidence_profile.trim().is_empty(),
+            "{} backend {:?} does not carry its exact reviewed profile floor",
+            policy.id,
+            lowering.backend
+        );
+    }
+    Ok(())
+}
+
+pub(in crate::resolve) enum PackedAluRecipeSource {
+    Imported {
+        record: &'static str,
+        symbol: &'static str,
+        resolved_symbol: Option<&'static str>,
+        arguments: &'static [&'static str],
+        results: &'static [&'static str],
+        properties: &'static [&'static str],
+        selection: &'static str,
+        selection_asm: &'static str,
+    },
+    PtxNative,
+}
+
+pub(in crate::resolve) struct PackedAluRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) rust_name: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) arity: usize,
+    pub(in crate::resolve) must_use: bool,
+    pub(in crate::resolve) ptx_mnemonic: &'static str,
+    pub(in crate::resolve) modifiers: &'static [&'static str],
+    pub(in crate::resolve) native_minimum_sm: u16,
+    pub(in crate::resolve) minimum_ptx: &'static str,
+    pub(in crate::resolve) minimum_sm: &'static str,
+    pub(in crate::resolve) ptx_isa_section: &'static str,
+    pub(in crate::resolve) ptx_isa_url: &'static str,
+    pub(in crate::resolve) source: PackedAluRecipeSource,
+}
+
+/// Returns the closed recipe for a packed-ALU (format, operation) pair.
+///
+/// `None` means the pair is outside the family: the operation exists for some
+/// other format but this one has no reviewed lowering for it.
+pub(in crate::resolve) fn packed_alu_recipe(
+    format: PackedAluFormat,
+    operation: PackedAluOperation,
+) -> Option<PackedAluRecipe> {
+    match format {
+        PackedAluFormat::Bf16x2 => packed_bf16x2_alu_recipe(operation),
+        PackedAluFormat::F16x2 => packed_f16x2_alu_recipe(operation),
+        PackedAluFormat::F32x2 => packed_f32x2_alu_recipe(operation),
+    }
+}
+
+pub(in crate::resolve) fn packed_f32x2_alu_recipe(
+    operation: PackedAluOperation,
+) -> Option<PackedAluRecipe> {
+    let (
+        id,
+        abi_id,
+        operation_key,
+        rust_name,
+        dialect_op_type,
+        dialect_op_name,
+        arity,
+        head,
+        modifiers,
+        section,
+        url,
+    ) = match operation {
+        PackedAluOperation::Add => (
+            "add_f32x2",
+            "i0995",
+            "packed.alu.f32x2.add",
+            "add_f32x2",
+            "AddF32x2Op",
+            "nvvm.add_f32x2",
+            2,
+            "add.rn.f32x2",
+            &["rn", "f32x2"][..],
+            "9.7.3.1 Floating Point Instructions: add",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-add",
+        ),
+        PackedAluOperation::AddFtz => (
+            "add_ftz_f32x2",
+            "i0996",
+            "packed.alu.f32x2.add.ftz",
+            "add_ftz_f32x2",
+            "AddFtzF32x2Op",
+            "nvvm.add_ftz_f32x2",
+            2,
+            "add.rn.ftz.f32x2",
+            &["rn", "ftz", "f32x2"][..],
+            "9.7.3.1 Floating Point Instructions: add",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-add",
+        ),
+        PackedAluOperation::Sub => (
+            "sub_f32x2",
+            "i0997",
+            "packed.alu.f32x2.sub",
+            "sub_f32x2",
+            "SubF32x2Op",
+            "nvvm.sub_f32x2",
+            2,
+            "sub.rn.f32x2",
+            &["rn", "f32x2"][..],
+            "9.7.3.2 Floating Point Instructions: sub",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-sub",
+        ),
+        PackedAluOperation::SubFtz => (
+            "sub_ftz_f32x2",
+            "i0998",
+            "packed.alu.f32x2.sub.ftz",
+            "sub_ftz_f32x2",
+            "SubFtzF32x2Op",
+            "nvvm.sub_ftz_f32x2",
+            2,
+            "sub.rn.ftz.f32x2",
+            &["rn", "ftz", "f32x2"][..],
+            "9.7.3.2 Floating Point Instructions: sub",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-sub",
+        ),
+        PackedAluOperation::Mul => (
+            "mul_f32x2",
+            "i0999",
+            "packed.alu.f32x2.mul",
+            "mul_f32x2",
+            "MulF32x2Op",
+            "nvvm.mul_f32x2",
+            2,
+            "mul.rn.f32x2",
+            &["rn", "f32x2"][..],
+            "9.7.3.3 Floating Point Instructions: mul",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-mul",
+        ),
+        PackedAluOperation::MulFtz => (
+            "mul_ftz_f32x2",
+            "i1000",
+            "packed.alu.f32x2.mul.ftz",
+            "mul_ftz_f32x2",
+            "MulFtzF32x2Op",
+            "nvvm.mul_ftz_f32x2",
+            2,
+            "mul.rn.ftz.f32x2",
+            &["rn", "ftz", "f32x2"][..],
+            "9.7.3.3 Floating Point Instructions: mul",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-mul",
+        ),
+        PackedAluOperation::Fma => (
+            "fma_f32x2",
+            "i1001",
+            "packed.alu.f32x2.fma",
+            "fma_f32x2",
+            "FmaF32x2Op",
+            "nvvm.fma_f32x2",
+            3,
+            "fma.rn.f32x2",
+            &["rn", "f32x2"][..],
+            "9.7.3.4 Floating Point Instructions: fma",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-fma",
+        ),
+        PackedAluOperation::FmaFtz => (
+            "fma_ftz_f32x2",
+            "i1002",
+            "packed.alu.f32x2.fma.ftz",
+            "fma_ftz_f32x2",
+            "FmaFtzF32x2Op",
+            "nvvm.fma_ftz_f32x2",
+            3,
+            "fma.rn.ftz.f32x2",
+            &["rn", "ftz", "f32x2"][..],
+            "9.7.3.4 Floating Point Instructions: fma",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-fma",
+        ),
+        _ => return None,
+    };
+    Some(PackedAluRecipe {
+        id,
+        abi_id,
+        operation_key,
+        rust_name,
+        dialect_op_type,
+        dialect_op_name,
+        arity,
+        must_use: true,
+        ptx_mnemonic: head,
+        modifiers,
+        native_minimum_sm: 100,
+        minimum_ptx: "8.6",
+        minimum_sm: "sm_100",
+        ptx_isa_section: section,
+        ptx_isa_url: url,
+        source: PackedAluRecipeSource::PtxNative,
+    })
+}
+
+pub(in crate::resolve) fn packed_bf16x2_alu_recipe(
+    operation: PackedAluOperation,
+) -> Option<PackedAluRecipe> {
+    const PURE: &[&str] = &["IntrNoMem", "IntrSpeculatable"];
+    const COMMUTATIVE_PURE: &[&str] = &["Commutative", "IntrNoMem", "IntrSpeculatable"];
+    Some(match operation {
+        PackedAluOperation::Fma => PackedAluRecipe {
+            id: "fma_bf16x2",
+            abi_id: "i0062",
+            operation_key: "packed.alu.bf16x2.fma",
+            rust_name: "fma_bf16x2",
+            dialect_op_type: "FmaBf16x2Op",
+            dialect_op_name: "nvvm.fma_bf16x2",
+            arity: 3,
+            must_use: false,
+            ptx_mnemonic: "fma.rn.bf16x2",
+            modifiers: &["rn", "bf16x2"],
+            native_minimum_sm: 80,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fma_rn_bf16x2",
+                symbol: "llvm.nvvm.fma.rn.bf16x2",
+                resolved_symbol: None,
+                arguments: &["v2bf16", "v2bf16", "v2bf16"],
+                results: &["v2bf16"],
+                properties: PURE,
+                selection: "INT_NVVM_FMA_rn_bf16x2",
+                selection_asm: "fma.rn.bf16x2 \t$dst, $src0, $src1, $src2;",
+            },
+        },
+        PackedAluOperation::FmaRelu => PackedAluRecipe {
+            id: "fma_relu_bf16x2",
+            abi_id: "i0063",
+            operation_key: "packed.alu.bf16x2.fma.relu",
+            rust_name: "fma_relu_bf16x2",
+            dialect_op_type: "FmaReluBf16x2Op",
+            dialect_op_name: "nvvm.fma_relu_bf16x2",
+            arity: 3,
+            must_use: false,
+            ptx_mnemonic: "fma.rn.relu.bf16x2",
+            modifiers: &["rn", "relu", "bf16x2"],
+            native_minimum_sm: 80,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fma_rn_relu_bf16x2",
+                symbol: "llvm.nvvm.fma.rn.relu.bf16x2",
+                resolved_symbol: None,
+                arguments: &["v2bf16", "v2bf16", "v2bf16"],
+                results: &["v2bf16"],
+                properties: PURE,
+                selection: "INT_NVVM_FMA_rn_relu_bf16x2",
+                selection_asm: "fma.rn.relu.bf16x2 \t$dst, $src0, $src1, $src2;",
+            },
+        },
+        PackedAluOperation::Add => PackedAluRecipe {
+            id: "add_bf16x2",
+            abi_id: "i0064",
+            operation_key: "packed.alu.bf16x2.add",
+            rust_name: "add_bf16x2",
+            dialect_op_type: "AddBf16x2Op",
+            dialect_op_name: "nvvm.add_bf16x2",
+            arity: 2,
+            must_use: false,
+            ptx_mnemonic: "add.rn.bf16x2",
+            modifiers: &["rn", "bf16x2"],
+            native_minimum_sm: 90,
+            minimum_ptx: "7.8",
+            minimum_sm: "sm_90",
+            ptx_isa_section: "9.7.4.1 Half Precision Floating Point Instructions: add",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-add",
+            source: PackedAluRecipeSource::PtxNative,
+        },
+        PackedAluOperation::Sub => PackedAluRecipe {
+            id: "sub_bf16x2",
+            abi_id: "i0065",
+            operation_key: "packed.alu.bf16x2.sub",
+            rust_name: "sub_bf16x2",
+            dialect_op_type: "SubBf16x2Op",
+            dialect_op_name: "nvvm.sub_bf16x2",
+            arity: 2,
+            must_use: false,
+            ptx_mnemonic: "sub.rn.bf16x2",
+            modifiers: &["rn", "bf16x2"],
+            native_minimum_sm: 90,
+            minimum_ptx: "7.8",
+            minimum_sm: "sm_90",
+            ptx_isa_section: "9.7.4.2 Half Precision Floating Point Instructions: sub",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-sub",
+            source: PackedAluRecipeSource::PtxNative,
+        },
+        PackedAluOperation::Mul => PackedAluRecipe {
+            id: "mul_bf16x2",
+            abi_id: "i0066",
+            operation_key: "packed.alu.bf16x2.mul",
+            rust_name: "mul_bf16x2",
+            dialect_op_type: "MulBf16x2Op",
+            dialect_op_name: "nvvm.mul_bf16x2",
+            arity: 2,
+            must_use: false,
+            ptx_mnemonic: "mul.rn.bf16x2",
+            modifiers: &["rn", "bf16x2"],
+            native_minimum_sm: 90,
+            minimum_ptx: "7.8",
+            minimum_sm: "sm_90",
+            ptx_isa_section: "9.7.4.3 Half Precision Floating Point Instructions: mul",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-mul",
+            source: PackedAluRecipeSource::PtxNative,
+        },
+        PackedAluOperation::Min => PackedAluRecipe {
+            id: "min_bf16x2",
+            abi_id: "i0067",
+            operation_key: "packed.alu.bf16x2.min",
+            rust_name: "min_bf16x2",
+            dialect_op_type: "MinBf16x2Op",
+            dialect_op_name: "nvvm.min_bf16x2",
+            arity: 2,
+            must_use: false,
+            ptx_mnemonic: "min.bf16x2",
+            modifiers: &["bf16x2"],
+            native_minimum_sm: 80,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_isa_section: "9.7.4.7 Half Precision Floating Point Instructions: min",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-min",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fmin_bf16x2",
+                symbol: "llvm.nvvm.fmin.bf16x2",
+                resolved_symbol: None,
+                arguments: &["v2bf16", "v2bf16"],
+                results: &["v2bf16"],
+                properties: COMMUTATIVE_PURE,
+                selection: "INT_NVVM_FMIN_bf16x2",
+                selection_asm: "min.bf16x2 \t$dst, $src0, $src1;",
+            },
+        },
+        PackedAluOperation::Max => PackedAluRecipe {
+            id: "max_bf16x2",
+            abi_id: "i0068",
+            operation_key: "packed.alu.bf16x2.max",
+            rust_name: "max_bf16x2",
+            dialect_op_type: "MaxBf16x2Op",
+            dialect_op_name: "nvvm.max_bf16x2",
+            arity: 2,
+            must_use: false,
+            ptx_mnemonic: "max.bf16x2",
+            modifiers: &["bf16x2"],
+            native_minimum_sm: 80,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_isa_section: "9.7.4.8 Half Precision Floating Point Instructions: max",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-max",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fmax_bf16x2",
+                symbol: "llvm.nvvm.fmax.bf16x2",
+                resolved_symbol: None,
+                arguments: &["v2bf16", "v2bf16"],
+                results: &["v2bf16"],
+                properties: COMMUTATIVE_PURE,
+                selection: "INT_NVVM_FMAN_bf16x2",
+                selection_asm: "max.bf16x2 \t$dst, $src0, $src1;",
+            },
+        },
+        PackedAluOperation::Neg => PackedAluRecipe {
+            id: "neg_bf16x2",
+            abi_id: "i0069",
+            operation_key: "packed.alu.bf16x2.neg",
+            rust_name: "neg_bf16x2",
+            dialect_op_type: "NegBf16x2Op",
+            dialect_op_name: "nvvm.neg_bf16x2",
+            arity: 1,
+            must_use: false,
+            ptx_mnemonic: "neg.bf16x2",
+            modifiers: &["bf16x2"],
+            native_minimum_sm: 80,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_isa_section: "9.7.4.5 Half Precision Floating Point Instructions: neg",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-neg",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_neg_bf16x2",
+                symbol: "llvm.nvvm.neg.bf16x2",
+                resolved_symbol: None,
+                arguments: &["v2bf16"],
+                results: &["v2bf16"],
+                properties: PURE,
+                selection: "INT_NVVM_NEG_BF16X2",
+                selection_asm: "neg.bf16x2 \t$dst, $src0;",
+            },
+        },
+        PackedAluOperation::Abs => PackedAluRecipe {
+            id: "abs_bf16x2",
+            abi_id: "i0070",
+            operation_key: "packed.alu.bf16x2.abs",
+            rust_name: "abs_bf16x2",
+            dialect_op_type: "AbsBf16x2Op",
+            dialect_op_name: "nvvm.abs_bf16x2",
+            arity: 1,
+            must_use: false,
+            ptx_mnemonic: "abs.bf16x2",
+            modifiers: &["bf16x2"],
+            native_minimum_sm: 80,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_isa_section: "9.7.4.6 Half Precision Floating Point Instructions: abs",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-abs",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fabs",
+                symbol: "llvm.nvvm.fabs",
+                resolved_symbol: Some("llvm.nvvm.fabs.v2bf16"),
+                arguments: &["anonymous_14"],
+                results: &["anyfloat"],
+                properties: PURE,
+                selection: "ABS_BF16X2",
+                selection_asm: "abs.bf16x2 \t$dst, $src0;",
+            },
+        },
+        // The f32x2-only operation keys are outside this admission. The ftz
+        // and sat fma forms also do not exist for bf16x2 in the PTX ISA at
+        // all: ptxas rejects hand-written `fma.rn.ftz.bf16x2` with
+        // "Illegal modifier '.ftz' for instruction 'fma'", and accepts
+        // `fma.rn.relu.bf16x2` beside it. LLVM declares the intrinsics anyway,
+        // so instruction selection is what fails first ("Cannot select:
+        // intrinsic %llvm.nvvm.fma.rn.ftz.bf16x2"), but the assembler is the
+        // authority here. Reject them rather than admit a recipe that has no
+        // instruction to lower to.
+        PackedAluOperation::AddFtz
+        | PackedAluOperation::SubFtz
+        | PackedAluOperation::MulFtz
+        | PackedAluOperation::FmaFtz
+        | PackedAluOperation::FmaSat
+        | PackedAluOperation::FmaFtzSat
+        | PackedAluOperation::FmaFtzRelu => return None,
+    })
+}
+
+pub(in crate::resolve) fn packed_f16x2_alu_recipe(
+    operation: PackedAluOperation,
+) -> Option<PackedAluRecipe> {
+    const PURE: &[&str] = &["IntrNoMem", "IntrSpeculatable"];
+    const COMMUTATIVE_PURE: &[&str] = &["Commutative", "IntrNoMem", "IntrSpeculatable"];
+    Some(match operation {
+        PackedAluOperation::Fma => PackedAluRecipe {
+            id: "fma_f16x2",
+            abi_id: "i0072",
+            operation_key: "packed.alu.f16x2.fma",
+            rust_name: "fma_f16x2",
+            dialect_op_type: "FmaF16x2Op",
+            dialect_op_name: "nvvm.fma_f16x2",
+            arity: 3,
+            must_use: true,
+            ptx_mnemonic: "fma.rn.f16x2",
+            modifiers: &["rn", "f16x2"],
+            native_minimum_sm: 53,
+            minimum_ptx: "4.2",
+            minimum_sm: "sm_70",
+            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fma_rn_f16x2",
+                symbol: "llvm.nvvm.fma.rn.f16x2",
+                resolved_symbol: None,
+                arguments: &["v2f16", "v2f16", "v2f16"],
+                results: &["v2f16"],
+                properties: PURE,
+                selection: "INT_NVVM_FMA_rn_f16x2",
+                selection_asm: "fma.rn.f16x2 \t$dst, $src0, $src1, $src2;",
+            },
+        },
+        PackedAluOperation::FmaFtz => PackedAluRecipe {
+            id: "fma_ftz_f16x2",
+            abi_id: "i0854",
+            operation_key: "packed.alu.f16x2.fma.ftz",
+            rust_name: "fma_ftz_f16x2",
+            dialect_op_type: "FmaFtzF16x2Op",
+            dialect_op_name: "nvvm.fma_ftz_f16x2",
+            arity: 3,
+            must_use: true,
+            ptx_mnemonic: "fma.rn.ftz.f16x2",
+            modifiers: &["rn", "ftz", "f16x2"],
+            native_minimum_sm: 53,
+            minimum_ptx: "4.2",
+            minimum_sm: "sm_70",
+            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fma_rn_ftz_f16x2",
+                symbol: "llvm.nvvm.fma.rn.ftz.f16x2",
+                resolved_symbol: None,
+                arguments: &["v2f16", "v2f16", "v2f16"],
+                results: &["v2f16"],
+                properties: PURE,
+                selection: "INT_NVVM_FMA_rn_ftz_f16x2",
+                selection_asm: "fma.rn.ftz.f16x2 \t$dst, $src0, $src1, $src2;",
+            },
+        },
+        PackedAluOperation::FmaSat => PackedAluRecipe {
+            id: "fma_sat_f16x2",
+            abi_id: "i0855",
+            operation_key: "packed.alu.f16x2.fma.sat",
+            rust_name: "fma_sat_f16x2",
+            dialect_op_type: "FmaSatF16x2Op",
+            dialect_op_name: "nvvm.fma_sat_f16x2",
+            arity: 3,
+            must_use: true,
+            ptx_mnemonic: "fma.rn.sat.f16x2",
+            modifiers: &["rn", "sat", "f16x2"],
+            native_minimum_sm: 53,
+            minimum_ptx: "4.2",
+            minimum_sm: "sm_70",
+            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fma_rn_sat_f16x2",
+                symbol: "llvm.nvvm.fma.rn.sat.f16x2",
+                resolved_symbol: None,
+                arguments: &["v2f16", "v2f16", "v2f16"],
+                results: &["v2f16"],
+                properties: PURE,
+                selection: "INT_NVVM_FMA_rn_sat_f16x2",
+                selection_asm: "fma.rn.sat.f16x2 \t$dst, $src0, $src1, $src2;",
+            },
+        },
+        PackedAluOperation::FmaFtzSat => PackedAluRecipe {
+            id: "fma_ftz_sat_f16x2",
+            abi_id: "i0856",
+            operation_key: "packed.alu.f16x2.fma.ftz.sat",
+            rust_name: "fma_ftz_sat_f16x2",
+            dialect_op_type: "FmaFtzSatF16x2Op",
+            dialect_op_name: "nvvm.fma_ftz_sat_f16x2",
+            arity: 3,
+            must_use: true,
+            ptx_mnemonic: "fma.rn.ftz.sat.f16x2",
+            modifiers: &["rn", "ftz", "sat", "f16x2"],
+            native_minimum_sm: 53,
+            minimum_ptx: "4.2",
+            minimum_sm: "sm_70",
+            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fma_rn_ftz_sat_f16x2",
+                symbol: "llvm.nvvm.fma.rn.ftz.sat.f16x2",
+                resolved_symbol: None,
+                arguments: &["v2f16", "v2f16", "v2f16"],
+                results: &["v2f16"],
+                properties: PURE,
+                selection: "INT_NVVM_FMA_rn_ftz_sat_f16x2",
+                selection_asm: "fma.rn.ftz.sat.f16x2 \t$dst, $src0, $src1, $src2;",
+            },
+        },
+        PackedAluOperation::FmaRelu => PackedAluRecipe {
+            id: "fma_relu_f16x2",
+            abi_id: "i0073",
+            operation_key: "packed.alu.f16x2.fma.relu",
+            rust_name: "fma_relu_f16x2",
+            dialect_op_type: "FmaReluF16x2Op",
+            dialect_op_name: "nvvm.fma_relu_f16x2",
+            arity: 3,
+            must_use: true,
+            ptx_mnemonic: "fma.rn.relu.f16x2",
+            modifiers: &["rn", "relu", "f16x2"],
+            native_minimum_sm: 80,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fma_rn_relu_f16x2",
+                symbol: "llvm.nvvm.fma.rn.relu.f16x2",
+                resolved_symbol: None,
+                arguments: &["v2f16", "v2f16", "v2f16"],
+                results: &["v2f16"],
+                properties: PURE,
+                selection: "INT_NVVM_FMA_rn_relu_f16x2",
+                selection_asm: "fma.rn.relu.f16x2 \t$dst, $src0, $src1, $src2;",
+            },
+        },
+        PackedAluOperation::FmaFtzRelu => PackedAluRecipe {
+            id: "fma_ftz_relu_f16x2",
+            abi_id: "i0857",
+            operation_key: "packed.alu.f16x2.fma.ftz.relu",
+            rust_name: "fma_ftz_relu_f16x2",
+            dialect_op_type: "FmaFtzReluF16x2Op",
+            dialect_op_name: "nvvm.fma_ftz_relu_f16x2",
+            arity: 3,
+            must_use: true,
+            ptx_mnemonic: "fma.rn.ftz.relu.f16x2",
+            modifiers: &["rn", "ftz", "relu", "f16x2"],
+            native_minimum_sm: 80,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_isa_section: "9.7.4.4 Half Precision Floating Point Instructions: fma",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-fma",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fma_rn_ftz_relu_f16x2",
+                symbol: "llvm.nvvm.fma.rn.ftz.relu.f16x2",
+                resolved_symbol: None,
+                arguments: &["v2f16", "v2f16", "v2f16"],
+                results: &["v2f16"],
+                properties: PURE,
+                selection: "INT_NVVM_FMA_rn_ftz_relu_f16x2",
+                selection_asm: "fma.rn.ftz.relu.f16x2 \t$dst, $src0, $src1, $src2;",
+            },
+        },
+        PackedAluOperation::Add => PackedAluRecipe {
+            id: "add_f16x2",
+            abi_id: "i0074",
+            operation_key: "packed.alu.f16x2.add",
+            rust_name: "add_f16x2",
+            dialect_op_type: "AddF16x2Op",
+            dialect_op_name: "nvvm.add_f16x2",
+            arity: 2,
+            must_use: true,
+            ptx_mnemonic: "add.rn.f16x2",
+            modifiers: &["rn", "f16x2"],
+            native_minimum_sm: 53,
+            minimum_ptx: "4.2",
+            minimum_sm: "sm_70",
+            ptx_isa_section: "9.7.4.1 Half Precision Floating Point Instructions: add",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-add",
+            source: PackedAluRecipeSource::PtxNative,
+        },
+        PackedAluOperation::Sub => PackedAluRecipe {
+            id: "sub_f16x2",
+            abi_id: "i0075",
+            operation_key: "packed.alu.f16x2.sub",
+            rust_name: "sub_f16x2",
+            dialect_op_type: "SubF16x2Op",
+            dialect_op_name: "nvvm.sub_f16x2",
+            arity: 2,
+            must_use: true,
+            ptx_mnemonic: "sub.rn.f16x2",
+            modifiers: &["rn", "f16x2"],
+            native_minimum_sm: 53,
+            minimum_ptx: "4.2",
+            minimum_sm: "sm_70",
+            ptx_isa_section: "9.7.4.2 Half Precision Floating Point Instructions: sub",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-sub",
+            source: PackedAluRecipeSource::PtxNative,
+        },
+        PackedAluOperation::Mul => PackedAluRecipe {
+            id: "mul_f16x2",
+            abi_id: "i0076",
+            operation_key: "packed.alu.f16x2.mul",
+            rust_name: "mul_f16x2",
+            dialect_op_type: "MulF16x2Op",
+            dialect_op_name: "nvvm.mul_f16x2",
+            arity: 2,
+            must_use: true,
+            ptx_mnemonic: "mul.rn.f16x2",
+            modifiers: &["rn", "f16x2"],
+            native_minimum_sm: 53,
+            minimum_ptx: "4.2",
+            minimum_sm: "sm_70",
+            ptx_isa_section: "9.7.4.3 Half Precision Floating Point Instructions: mul",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-mul",
+            source: PackedAluRecipeSource::PtxNative,
+        },
+        PackedAluOperation::Min => PackedAluRecipe {
+            id: "min_f16x2",
+            abi_id: "i0077",
+            operation_key: "packed.alu.f16x2.min",
+            rust_name: "min_f16x2",
+            dialect_op_type: "MinF16x2Op",
+            dialect_op_name: "nvvm.min_f16x2",
+            arity: 2,
+            must_use: true,
+            ptx_mnemonic: "min.f16x2",
+            modifiers: &["f16x2"],
+            native_minimum_sm: 80,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_isa_section: "9.7.4.7 Half Precision Floating Point Instructions: min",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-min",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fmin_f16x2",
+                symbol: "llvm.nvvm.fmin.f16x2",
+                resolved_symbol: None,
+                arguments: &["v2f16", "v2f16"],
+                results: &["v2f16"],
+                properties: COMMUTATIVE_PURE,
+                selection: "INT_NVVM_FMIN_f16x2",
+                selection_asm: "min.f16x2 \t$dst, $src0, $src1;",
+            },
+        },
+        PackedAluOperation::Max => PackedAluRecipe {
+            id: "max_f16x2",
+            abi_id: "i0078",
+            operation_key: "packed.alu.f16x2.max",
+            rust_name: "max_f16x2",
+            dialect_op_type: "MaxF16x2Op",
+            dialect_op_name: "nvvm.max_f16x2",
+            arity: 2,
+            must_use: true,
+            ptx_mnemonic: "max.f16x2",
+            modifiers: &["f16x2"],
+            native_minimum_sm: 80,
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_isa_section: "9.7.4.8 Half Precision Floating Point Instructions: max",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-max",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fmax_f16x2",
+                symbol: "llvm.nvvm.fmax.f16x2",
+                resolved_symbol: None,
+                arguments: &["v2f16", "v2f16"],
+                results: &["v2f16"],
+                properties: COMMUTATIVE_PURE,
+                selection: "INT_NVVM_FMAN_f16x2",
+                selection_asm: "max.f16x2 \t$dst, $src0, $src1;",
+            },
+        },
+        PackedAluOperation::Neg => PackedAluRecipe {
+            id: "neg_f16x2",
+            abi_id: "i0079",
+            operation_key: "packed.alu.f16x2.neg",
+            rust_name: "neg_f16x2",
+            dialect_op_type: "NegF16x2Op",
+            dialect_op_name: "nvvm.neg_f16x2",
+            arity: 1,
+            must_use: true,
+            ptx_mnemonic: "neg.f16x2",
+            modifiers: &["f16x2"],
+            native_minimum_sm: 53,
+            minimum_ptx: "6.0",
+            minimum_sm: "sm_70",
+            ptx_isa_section: "9.7.4.5 Half Precision Floating Point Instructions: neg",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-neg",
+            source: PackedAluRecipeSource::PtxNative,
+        },
+        PackedAluOperation::Abs => PackedAluRecipe {
+            id: "abs_f16x2",
+            abi_id: "i0080",
+            operation_key: "packed.alu.f16x2.abs",
+            rust_name: "abs_f16x2",
+            dialect_op_type: "AbsF16x2Op",
+            dialect_op_name: "nvvm.abs_f16x2",
+            arity: 1,
+            must_use: true,
+            ptx_mnemonic: "abs.f16x2",
+            modifiers: &["f16x2"],
+            native_minimum_sm: 53,
+            minimum_ptx: "6.5",
+            minimum_sm: "sm_70",
+            ptx_isa_section: "9.7.4.6 Half Precision Floating Point Instructions: abs",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-abs",
+            source: PackedAluRecipeSource::Imported {
+                record: "int_nvvm_fabs",
+                symbol: "llvm.nvvm.fabs",
+                resolved_symbol: Some("llvm.nvvm.fabs.v2f16"),
+                arguments: &["anonymous_14"],
+                results: &["anyfloat"],
+                properties: PURE,
+                selection: "ABS_F16X2",
+                selection_asm: "abs.f16x2 \t$dst, $src0;",
+            },
+        },
+        // These operations were added for the f32x2 admission. Keeping them
+        // outside the f16x2 recipe avoids silently expanding this PR's scope,
+        // even where a similarly spelled PTX form may exist.
+        PackedAluOperation::AddFtz | PackedAluOperation::SubFtz | PackedAluOperation::MulFtz => {
+            return None;
+        }
+    })
+}
+
+/// Per-backend PTX and SM floors, which can sit above the recipe's own floor.
+///
+/// Takes the caller's already-resolved recipe rather than looking it up again,
+/// so this cannot be reached with a pair the family rejects.
+pub(in crate::resolve) fn packed_alu_backend_floor(
+    recipe: &PackedAluRecipe,
+    format: PackedAluFormat,
+    operation: PackedAluOperation,
+    backend: IntrinsicBackend,
+) -> (&'static str, &'static str) {
+    match (format, operation, backend) {
+        (
+            PackedAluFormat::F16x2,
+            PackedAluOperation::Fma
+            | PackedAluOperation::Add
+            | PackedAluOperation::Sub
+            | PackedAluOperation::Mul,
+            IntrinsicBackend::LlvmNvptx,
+        ) => ("6.0", "sm_70"),
+        (
+            PackedAluFormat::F16x2,
+            PackedAluOperation::Fma
+            | PackedAluOperation::Add
+            | PackedAluOperation::Sub
+            | PackedAluOperation::Mul,
+            IntrinsicBackend::LibNvvm,
+        ) => ("4.2", "sm_75"),
+        // The ftz and sat fma forms share the plain fma floors: PTX 4.2 natively,
+        // but the pinned LLVM backend needs 6.0 and CUDA 13.3 ptxas no longer
+        // targets sm_70, so libNVVM is checked at sm_75.
+        (
+            PackedAluFormat::F16x2,
+            PackedAluOperation::FmaFtz | PackedAluOperation::FmaSat | PackedAluOperation::FmaFtzSat,
+            IntrinsicBackend::LlvmNvptx,
+        ) => ("6.0", "sm_70"),
+        (
+            PackedAluFormat::F16x2,
+            PackedAluOperation::FmaFtz | PackedAluOperation::FmaSat | PackedAluOperation::FmaFtzSat,
+            IntrinsicBackend::LibNvvm,
+        ) => ("4.2", "sm_75"),
+        (PackedAluFormat::F16x2, PackedAluOperation::Neg, IntrinsicBackend::LlvmNvptx) => {
+            ("6.0", "sm_70")
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::Neg, IntrinsicBackend::LibNvvm) => {
+            ("6.0", "sm_75")
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::Abs, IntrinsicBackend::LlvmNvptx) => {
+            ("6.5", "sm_70")
+        }
+        (PackedAluFormat::F16x2, PackedAluOperation::Abs, IntrinsicBackend::LibNvvm) => {
+            ("6.5", "sm_75")
+        }
+        _ => (recipe.minimum_ptx, recipe.minimum_sm),
+    }
+}
+
+pub(in crate::resolve) fn validate_packed_alu_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+    declaration: Option<&ImportedIntrinsic>,
+) -> Result<()> {
+    let packed = policy
+        .packed_alu
+        .as_ref()
+        .with_context(|| format!("{} has no closed packed-ALU contract", policy.id))?;
+    let recipe = packed_alu_recipe(packed.format, packed.operation)
+        .with_context(|| format!("{} is outside the closed packed-ALU recipe", policy.id))?;
+    let (rust_module, rust_type, dialect_type, expected_adapter) = match packed.format {
+        PackedAluFormat::Bf16x2 => ("bf16x2", "u32", "i32", PackedAluAdapter::DirectPackedU32),
+        PackedAluFormat::F16x2 => ("f16x2", "u32", "i32", PackedAluAdapter::DirectPackedU32),
+        PackedAluFormat::F32x2 => ("f32x2", "u64", "i64", PackedAluAdapter::DirectPackedU64),
+    };
+    ensure!(
+        packed.adapter == expected_adapter,
+        "{} requests an unsupported packed-ALU adapter",
+        policy.id
+    );
+    let rust_arguments = vec![rust_type; recipe.arity];
+    let dialect_operands = vec![dialect_type; recipe.arity];
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key,
+        "{} packed-ALU identity does not match its closed operation recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == rust_module
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == rust_arguments
+            && policy.rust_result == rust_type
+            && policy.safe
+            && policy.must_use == recipe.must_use
+            && policy
+                .safe_allowlist_reason
+                .as_deref()
+                .is_some_and(|reason| !reason.trim().is_empty())
+            && policy.public_rust_path
+                == format!("cuda_intrinsics::{rust_module}::{}", recipe.rust_name)
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::{rust_module}::{}", recipe.rust_name)],
+        "{} must preserve its reviewed safe packed-ALU API",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == dialect_operands
+            && policy.dialect_results == [dialect_type]
+            && policy.lowering == "generated_packed_alu_inline_ptx",
+        "{} is outside the closed packed-ALU dialect and lowering recipe",
+        policy.id
+    );
+    ensure!(
+        policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
+            && policy.ptx_result == rust_type
+            && policy.targets == "all"
+            && packed.native_minimum_sm == recipe.native_minimum_sm,
+        "{} packed-ALU effects, carrier, or target floor disagree",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.ptx_isa_section
+            && policy.ptx_isa_url == recipe.ptx_isa_url,
+        "{} packed-ALU PTX provenance does not match its reviewed instruction section",
+        policy.id
+    );
+    let expected_operands = vec![OperandPattern::Register; recipe.arity + 1];
+    ensure!(
+        policy.expected_ptx.mnemonic
+            == recipe.ptx_mnemonic.split('.').next().expect("PTX mnemonic")
+            && policy.expected_ptx.modifiers == recipe.modifiers
+            && policy.expected_ptx.operands == expected_operands,
+        "{} expected PTX does not match its exact packed-ALU instruction",
+        policy.id
+    );
+
+    match &recipe.source {
+        PackedAluRecipeSource::PtxNative => {
+            ensure!(
+                source
+                    == &IntrinsicSource::PtxNative {
+                        instruction: recipe.ptx_mnemonic.to_owned(),
+                    }
+                    && declaration.is_none(),
+                "{} packed-ALU source does not match its PTX-native recipe",
+                policy.id
+            );
+        }
+        PackedAluRecipeSource::Imported {
+            record,
+            symbol,
+            resolved_symbol,
+            arguments,
+            results,
+            properties,
+            selection,
+            selection_asm,
+        } => {
+            let declaration = declaration.context("imported packed ALU has no declaration")?;
+            ensure!(
+                source
+                    == &IntrinsicSource::LlvmImported {
+                        source_record: (*record).to_owned(),
+                    }
+                    && policy.llvm_symbol.as_deref() == Some(*symbol)
+                    && policy.resolved_llvm_symbol.as_deref() == *resolved_symbol
+                    && policy.llvm_arguments == *arguments
+                    && policy.llvm_results == *results,
+                "{} packed-ALU LLVM source or signature changed",
+                policy.id
+            );
+            let matching_selections: Vec<_> = declaration
+                .selections
+                .iter()
+                .filter(|candidate| candidate.source_record == *selection)
+                .collect();
+            let expected_selection_count = if *record == "int_nvvm_fabs" { 6 } else { 1 };
+            ensure!(
+                declaration.properties == *properties
+                    && declaration.selections.len() == expected_selection_count
+                    && matching_selections.len() == 1
+                    && matching_selections[0].asm == *selection_asm
+                    && matching_selections[0].predicates
+                        == [
+                            format!("Subtarget->getSmVersion() >= {}", recipe.native_minimum_sm),
+                            format!(
+                                "Subtarget->getPTXVersion() >= {}",
+                                recipe.minimum_ptx.replace('.', "")
+                            ),
+                        ]
+                    && matching_selections[0].constraints.is_empty(),
+                "{} packed-ALU imported properties or selection changed",
+                policy.id
+            );
+        }
+    }
+    let llvm_floor = packed_alu_backend_floor(
+        &recipe,
+        packed.format,
+        packed.operation,
+        IntrinsicBackend::LlvmNvptx,
+    );
+    let libnvvm_floor = packed_alu_backend_floor(
+        &recipe,
+        packed.format,
+        packed.operation,
+        IntrinsicBackend::LibNvvm,
+    );
+    ensure_exact_inline_ptx_backends(
+        policy,
+        [
+            (
+                IntrinsicBackend::LlvmNvptx,
+                llvm_floor.0,
+                Some(llvm_floor.1),
+            ),
+            (
+                IntrinsicBackend::LibNvvm,
+                libnvvm_floor.0,
+                Some(libnvvm_floor.1),
+            ),
+        ],
+        "packed-ALU",
+    )?;
+    ensure_no_other_family_contract(policy, "packed-ALU")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/packed_conversion.rs b/crates/cuda-intrinsics-gen/src/resolve/families/packed_conversion.rs
new file mode 100644
index 0000000000..3f42abc9c1
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/packed_conversion.rs
@@ -0,0 +1,928 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, IntrinsicSource,
+    OverlayBackendLowering, OverlayIntrinsic, PackedConversionAdapter,
+    PackedConversionDestinationFormat, PackedConversionFp8Admission, PackedConversionFp8Direction,
+    PackedConversionFp8F16x2Admission, PackedConversionFp8Format, PackedConversionRounding,
+    PackedConversionSaturation, PackedConversionSourceFormat, RuntimeValidation,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use crate::resolve::guards::*;
+
+pub(in crate::resolve) struct PackedConversionRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) rust_name: &'static str,
+    pub(in crate::resolve) compatibility_path: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) llvm_result: &'static str,
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn packed_conversion_recipe(
+    conversion: &crate::model::PackedConversion,
+) -> Option<PackedConversionRecipe> {
+    match conversion.source_format {
+        PackedConversionSourceFormat::F32x2 => packed_conversion_recipe_f32x2(conversion),
+        PackedConversionSourceFormat::E4m3x2
+        | PackedConversionSourceFormat::E5m2x2
+        | PackedConversionSourceFormat::F16x2 => packed_conversion_recipe_fp8_f16x2(conversion),
+    }
+}
+
+/// Recipes for the packed FP8 conversions whose other side is `f16x2`.
+///
+/// Keyed on source as well as destination: unpacking to `f16x2` shares its
+/// destination, rounding, and saturation with the scalar-`f32` recipe for
+/// `cvt.rn.f16x2.f32`, so the source format is what separates them.
+pub(in crate::resolve) fn packed_conversion_recipe_fp8_f16x2(
+    conversion: &crate::model::PackedConversion,
+) -> Option<PackedConversionRecipe> {
+    match (
+        conversion.source_format,
+        conversion.destination_format,
+        conversion.rounding,
+        conversion.saturation,
+    ) {
+        (
+            PackedConversionSourceFormat::F16x2,
+            PackedConversionDestinationFormat::E4m3x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Satfinite,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_satfinite_e4m3x2_f16x2",
+            abi_id: "i0822",
+            operation_key: "packed.convert.f16x2.e4m3x2.nearest_even.satfinite",
+            rust_name: "cvt_rn_satfinite_e4m3x2_f16x2",
+            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2",
+            dialect_op_type: "CvtRnSatfiniteE4m3x2F16x2Op",
+            dialect_op_name: "nvvm.cvt_rn_satfinite_e4m3x2_f16x2",
+            source_record: "int_nvvm_f16x2_to_e4m3x2_rn",
+            llvm_symbol: "llvm.nvvm.f16x2.to.e4m3x2.rn",
+            llvm_result: "i16",
+            summary: "Converts packed f16x2 to packed e4m3x2 with nearest-even finite saturation, preserving half order.",
+        }),
+        (
+            PackedConversionSourceFormat::F16x2,
+            PackedConversionDestinationFormat::E4m3x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::SatfiniteRelu,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_satfinite_relu_e4m3x2_f16x2",
+            abi_id: "i0823",
+            operation_key: "packed.convert.f16x2.e4m3x2.nearest_even.satfinite.relu",
+            rust_name: "cvt_rn_satfinite_relu_e4m3x2_f16x2",
+            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2",
+            dialect_op_type: "CvtRnSatfiniteReluE4m3x2F16x2Op",
+            dialect_op_name: "nvvm.cvt_rn_satfinite_relu_e4m3x2_f16x2",
+            source_record: "int_nvvm_f16x2_to_e4m3x2_rn_relu",
+            llvm_symbol: "llvm.nvvm.f16x2.to.e4m3x2.rn.relu",
+            llvm_result: "i16",
+            summary: "Converts packed f16x2 to packed e4m3x2 with nearest-even finite saturation and ReLU, preserving half order.",
+        }),
+        (
+            PackedConversionSourceFormat::F16x2,
+            PackedConversionDestinationFormat::E5m2x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Satfinite,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_satfinite_e5m2x2_f16x2",
+            abi_id: "i0824",
+            operation_key: "packed.convert.f16x2.e5m2x2.nearest_even.satfinite",
+            rust_name: "cvt_rn_satfinite_e5m2x2_f16x2",
+            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2",
+            dialect_op_type: "CvtRnSatfiniteE5m2x2F16x2Op",
+            dialect_op_name: "nvvm.cvt_rn_satfinite_e5m2x2_f16x2",
+            source_record: "int_nvvm_f16x2_to_e5m2x2_rn",
+            llvm_symbol: "llvm.nvvm.f16x2.to.e5m2x2.rn",
+            llvm_result: "i16",
+            summary: "Converts packed f16x2 to packed e5m2x2 with nearest-even finite saturation, preserving half order.",
+        }),
+        (
+            PackedConversionSourceFormat::F16x2,
+            PackedConversionDestinationFormat::E5m2x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::SatfiniteRelu,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_satfinite_relu_e5m2x2_f16x2",
+            abi_id: "i0825",
+            operation_key: "packed.convert.f16x2.e5m2x2.nearest_even.satfinite.relu",
+            rust_name: "cvt_rn_satfinite_relu_e5m2x2_f16x2",
+            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2",
+            dialect_op_type: "CvtRnSatfiniteReluE5m2x2F16x2Op",
+            dialect_op_name: "nvvm.cvt_rn_satfinite_relu_e5m2x2_f16x2",
+            source_record: "int_nvvm_f16x2_to_e5m2x2_rn_relu",
+            llvm_symbol: "llvm.nvvm.f16x2.to.e5m2x2.rn.relu",
+            llvm_result: "i16",
+            summary: "Converts packed f16x2 to packed e5m2x2 with nearest-even finite saturation and ReLU, preserving half order.",
+        }),
+        (
+            PackedConversionSourceFormat::E4m3x2,
+            PackedConversionDestinationFormat::F16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::None,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_f16x2_e4m3x2",
+            abi_id: "i0826",
+            operation_key: "packed.convert.e4m3x2.f16x2.nearest_even",
+            rust_name: "cvt_rn_f16x2_e4m3x2",
+            compatibility_path: "cuda_device::convert::cvt_rn_f16x2_e4m3x2",
+            dialect_op_type: "CvtRnF16x2E4m3x2Op",
+            dialect_op_name: "nvvm.cvt_rn_f16x2_e4m3x2",
+            source_record: "int_nvvm_e4m3x2_to_f16x2_rn",
+            llvm_symbol: "llvm.nvvm.e4m3x2.to.f16x2.rn",
+            llvm_result: "v2f16",
+            summary: "Converts packed e4m3x2 to packed f16x2, preserving byte order.",
+        }),
+        (
+            PackedConversionSourceFormat::E4m3x2,
+            PackedConversionDestinationFormat::F16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Relu,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_relu_f16x2_e4m3x2",
+            abi_id: "i0827",
+            operation_key: "packed.convert.e4m3x2.f16x2.nearest_even.relu",
+            rust_name: "cvt_rn_relu_f16x2_e4m3x2",
+            compatibility_path: "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2",
+            dialect_op_type: "CvtRnReluF16x2E4m3x2Op",
+            dialect_op_name: "nvvm.cvt_rn_relu_f16x2_e4m3x2",
+            source_record: "int_nvvm_e4m3x2_to_f16x2_rn_relu",
+            llvm_symbol: "llvm.nvvm.e4m3x2.to.f16x2.rn.relu",
+            llvm_result: "v2f16",
+            summary: "Converts packed e4m3x2 to packed f16x2 with ReLU, preserving byte order.",
+        }),
+        (
+            PackedConversionSourceFormat::E5m2x2,
+            PackedConversionDestinationFormat::F16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::None,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_f16x2_e5m2x2",
+            abi_id: "i0828",
+            operation_key: "packed.convert.e5m2x2.f16x2.nearest_even",
+            rust_name: "cvt_rn_f16x2_e5m2x2",
+            compatibility_path: "cuda_device::convert::cvt_rn_f16x2_e5m2x2",
+            dialect_op_type: "CvtRnF16x2E5m2x2Op",
+            dialect_op_name: "nvvm.cvt_rn_f16x2_e5m2x2",
+            source_record: "int_nvvm_e5m2x2_to_f16x2_rn",
+            llvm_symbol: "llvm.nvvm.e5m2x2.to.f16x2.rn",
+            llvm_result: "v2f16",
+            summary: "Converts packed e5m2x2 to packed f16x2, preserving byte order.",
+        }),
+        (
+            PackedConversionSourceFormat::E5m2x2,
+            PackedConversionDestinationFormat::F16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Relu,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_relu_f16x2_e5m2x2",
+            abi_id: "i0829",
+            operation_key: "packed.convert.e5m2x2.f16x2.nearest_even.relu",
+            rust_name: "cvt_rn_relu_f16x2_e5m2x2",
+            compatibility_path: "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2",
+            dialect_op_type: "CvtRnReluF16x2E5m2x2Op",
+            dialect_op_name: "nvvm.cvt_rn_relu_f16x2_e5m2x2",
+            source_record: "int_nvvm_e5m2x2_to_f16x2_rn_relu",
+            llvm_symbol: "llvm.nvvm.e5m2x2.to.f16x2.rn.relu",
+            llvm_result: "v2f16",
+            summary: "Converts packed e5m2x2 to packed f16x2 with ReLU, preserving byte order.",
+        }),
+        _ => None,
+    }
+}
+
+pub(in crate::resolve) fn packed_conversion_recipe_f32x2(
+    conversion: &crate::model::PackedConversion,
+) -> Option<PackedConversionRecipe> {
+    match (
+        conversion.destination_format,
+        conversion.rounding,
+        conversion.saturation,
+    ) {
+        (
+            PackedConversionDestinationFormat::Bf16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::None,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_f32x2_bf16x2",
+            abi_id: "i0071",
+            operation_key: "packed.convert.f32x2.bf16x2.nearest_even",
+            rust_name: "cvt_f32x2_bf16x2",
+            compatibility_path: "cuda_device::convert::cvt_bf16x2_f32",
+            dialect_op_type: "CvtF32x2Bf16x2Op",
+            dialect_op_name: "nvvm.cvt_f32x2_bf16x2",
+            source_record: "int_nvvm_ff2bf16x2_rn",
+            llvm_symbol: "llvm.nvvm.ff2bf16x2.rn",
+            llvm_result: "v2bf16",
+            summary: "Converts two f32 values to packed bf16x2 with the first argument in the low half.",
+        }),
+        (
+            PackedConversionDestinationFormat::F16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::None,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_f16x2_f32",
+            abi_id: "i0081",
+            operation_key: "packed.convert.f32x2.f16x2.nearest_even",
+            rust_name: "cvt_f16x2_f32",
+            compatibility_path: "cuda_device::convert::cvt_f16x2_f32",
+            dialect_op_type: "CvtF16x2F32Op",
+            dialect_op_name: "nvvm.cvt_f16x2_f32",
+            source_record: "int_nvvm_ff2f16x2_rn",
+            llvm_symbol: "llvm.nvvm.ff2f16x2.rn",
+            llvm_result: "v2f16",
+            summary: "Converts two f32 values to packed f16x2 with nearest-even rounding and the first argument in the low half.",
+        }),
+        (
+            PackedConversionDestinationFormat::F16x2,
+            PackedConversionRounding::TowardZero,
+            PackedConversionSaturation::None,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rz_f16x2_f32",
+            abi_id: "i0082",
+            operation_key: "packed.convert.f32x2.f16x2.toward_zero",
+            rust_name: "cvt_rz_f16x2_f32",
+            compatibility_path: "cuda_device::convert::cvt_rz_f16x2_f32",
+            dialect_op_type: "CvtRzF16x2F32Op",
+            dialect_op_name: "nvvm.cvt_rz_f16x2_f32",
+            source_record: "int_nvvm_ff2f16x2_rz",
+            llvm_symbol: "llvm.nvvm.ff2f16x2.rz",
+            llvm_result: "v2f16",
+            summary: "Converts two f32 values to packed f16x2 with toward-zero rounding and the first argument in the low half.",
+        }),
+        (
+            PackedConversionDestinationFormat::F16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Relu,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_relu_f16x2_f32",
+            abi_id: "i0083",
+            operation_key: "packed.convert.f32x2.f16x2.nearest_even.relu",
+            rust_name: "cvt_rn_relu_f16x2_f32",
+            compatibility_path: "cuda_device::convert::cvt_rn_relu_f16x2_f32",
+            dialect_op_type: "CvtRnReluF16x2F32Op",
+            dialect_op_name: "nvvm.cvt_rn_relu_f16x2_f32",
+            source_record: "int_nvvm_ff2f16x2_rn_relu",
+            llvm_symbol: "llvm.nvvm.ff2f16x2.rn.relu",
+            llvm_result: "v2f16",
+            summary: "Converts two f32 values to packed f16x2 with nearest-even rounding, ReLU, and the first argument in the low half.",
+        }),
+        (
+            PackedConversionDestinationFormat::Bf16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Relu,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_relu_bf16x2_f32",
+            abi_id: "i0084",
+            operation_key: "packed.convert.f32x2.bf16x2.nearest_even.relu",
+            rust_name: "cvt_rn_relu_bf16x2_f32",
+            compatibility_path: "cuda_device::convert::cvt_rn_relu_bf16x2_f32",
+            dialect_op_type: "CvtRnReluBf16x2F32Op",
+            dialect_op_name: "nvvm.cvt_rn_relu_bf16x2_f32",
+            source_record: "int_nvvm_ff2bf16x2_rn_relu",
+            llvm_symbol: "llvm.nvvm.ff2bf16x2.rn.relu",
+            llvm_result: "v2bf16",
+            summary: "Converts two f32 values to packed bf16x2 with nearest-even rounding, ReLU, and the first argument in the low half.",
+        }),
+        (
+            PackedConversionDestinationFormat::Bf16x2,
+            PackedConversionRounding::TowardZero,
+            PackedConversionSaturation::None,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rz_bf16x2_f32",
+            abi_id: "i0085",
+            operation_key: "packed.convert.f32x2.bf16x2.toward_zero",
+            rust_name: "cvt_rz_bf16x2_f32",
+            compatibility_path: "cuda_device::convert::cvt_rz_bf16x2_f32",
+            dialect_op_type: "CvtRzBf16x2F32Op",
+            dialect_op_name: "nvvm.cvt_rz_bf16x2_f32",
+            source_record: "int_nvvm_ff2bf16x2_rz",
+            llvm_symbol: "llvm.nvvm.ff2bf16x2.rz",
+            llvm_result: "v2bf16",
+            summary: "Converts two f32 values to packed bf16x2 with toward-zero rounding and the first argument in the low half.",
+        }),
+        (
+            PackedConversionDestinationFormat::E4m3x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Satfinite,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_satfinite_e4m3x2_f32",
+            abi_id: "i0259",
+            operation_key: "packed.convert.f32x2.e4m3x2.nearest_even.satfinite",
+            rust_name: "cvt_rn_satfinite_e4m3x2_f32",
+            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32",
+            dialect_op_type: "CvtRnSatfiniteE4m3x2F32Op",
+            dialect_op_name: "nvvm.cvt_rn_satfinite_e4m3x2_f32",
+            source_record: "int_nvvm_ff_to_e4m3x2_rn",
+            llvm_symbol: "llvm.nvvm.ff.to.e4m3x2.rn",
+            llvm_result: "i16",
+            summary: "Converts two f32 values to packed e4m3x2 with nearest-even finite saturation and the first argument in the low byte.",
+        }),
+        (
+            PackedConversionDestinationFormat::E4m3x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::SatfiniteRelu,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_satfinite_relu_e4m3x2_f32",
+            abi_id: "i0260",
+            operation_key: "packed.convert.f32x2.e4m3x2.nearest_even.satfinite.relu",
+            rust_name: "cvt_rn_satfinite_relu_e4m3x2_f32",
+            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32",
+            dialect_op_type: "CvtRnSatfiniteReluE4m3x2F32Op",
+            dialect_op_name: "nvvm.cvt_rn_satfinite_relu_e4m3x2_f32",
+            source_record: "int_nvvm_ff_to_e4m3x2_rn_relu",
+            llvm_symbol: "llvm.nvvm.ff.to.e4m3x2.rn.relu",
+            llvm_result: "i16",
+            summary: "Converts two f32 values to packed e4m3x2 with nearest-even finite saturation, ReLU, and the first argument in the low byte.",
+        }),
+        (
+            PackedConversionDestinationFormat::E5m2x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Satfinite,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_satfinite_e5m2x2_f32",
+            abi_id: "i0261",
+            operation_key: "packed.convert.f32x2.e5m2x2.nearest_even.satfinite",
+            rust_name: "cvt_rn_satfinite_e5m2x2_f32",
+            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32",
+            dialect_op_type: "CvtRnSatfiniteE5m2x2F32Op",
+            dialect_op_name: "nvvm.cvt_rn_satfinite_e5m2x2_f32",
+            source_record: "int_nvvm_ff_to_e5m2x2_rn",
+            llvm_symbol: "llvm.nvvm.ff.to.e5m2x2.rn",
+            llvm_result: "i16",
+            summary: "Converts two f32 values to packed e5m2x2 with nearest-even finite saturation and the first argument in the low byte.",
+        }),
+        (
+            PackedConversionDestinationFormat::E5m2x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::SatfiniteRelu,
+        ) => Some(PackedConversionRecipe {
+            id: "cvt_rn_satfinite_relu_e5m2x2_f32",
+            abi_id: "i0262",
+            operation_key: "packed.convert.f32x2.e5m2x2.nearest_even.satfinite.relu",
+            rust_name: "cvt_rn_satfinite_relu_e5m2x2_f32",
+            compatibility_path: "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32",
+            dialect_op_type: "CvtRnSatfiniteReluE5m2x2F32Op",
+            dialect_op_name: "nvvm.cvt_rn_satfinite_relu_e5m2x2_f32",
+            source_record: "int_nvvm_ff_to_e5m2x2_rn_relu",
+            llvm_symbol: "llvm.nvvm.ff.to.e5m2x2.rn.relu",
+            llvm_result: "i16",
+            summary: "Converts two f32 values to packed e5m2x2 with nearest-even finite saturation, ReLU, and the first argument in the low byte.",
+        }),
+        _ => None,
+    }
+}
+
+pub(in crate::resolve) fn packed_conversion_ptx_modifiers(
+    conversion: &crate::model::PackedConversion,
+) -> Vec<&'static str> {
+    let rounding = match conversion.rounding {
+        PackedConversionRounding::NearestEven => "rn",
+        PackedConversionRounding::TowardZero => "rz",
+    };
+    let format = match conversion.destination_format {
+        PackedConversionDestinationFormat::Bf16x2 => "bf16x2",
+        PackedConversionDestinationFormat::E4m3x2 => "e4m3x2",
+        PackedConversionDestinationFormat::E5m2x2 => "e5m2x2",
+        PackedConversionDestinationFormat::F16x2 => "f16x2",
+    };
+    let mut modifiers = vec![rounding];
+    match conversion.saturation {
+        PackedConversionSaturation::None => {}
+        PackedConversionSaturation::Relu => modifiers.push("relu"),
+        PackedConversionSaturation::Satfinite => modifiers.push("satfinite"),
+        PackedConversionSaturation::SatfiniteRelu => modifiers.extend(["satfinite", "relu"]),
+    }
+    modifiers.extend([format, conversion.source_format.ptx_token()]);
+    modifiers
+}
+
+/// Whether either side of the conversion is a packed FP8 format.
+pub(in crate::resolve) fn packed_conversion_uses_fp8(
+    conversion: &crate::model::PackedConversion,
+) -> bool {
+    matches!(
+        conversion.source_format,
+        PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2
+    ) || matches!(
+        conversion.destination_format,
+        PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2
+    )
+}
+
+/// Source operand types, in Rust, dialect, and LLVM spellings.
+///
+/// A packed source arrives in one register; `f32x2` names two scalar operands.
+pub(in crate::resolve) fn packed_conversion_source_types(
+    conversion: &crate::model::PackedConversion,
+) -> (Vec<String>, Vec<String>, Vec<String>) {
+    match conversion.source_format {
+        PackedConversionSourceFormat::F32x2 => (
+            vec!["f32".into(), "f32".into()],
+            vec!["f32".into(), "f32".into()],
+            vec!["f32".into(), "f32".into()],
+        ),
+        PackedConversionSourceFormat::F16x2 => {
+            (vec!["u32".into()], vec!["i32".into()], vec!["v2f16".into()])
+        }
+        PackedConversionSourceFormat::E4m3x2 | PackedConversionSourceFormat::E5m2x2 => {
+            (vec!["u16".into()], vec!["i16".into()], vec!["i16".into()])
+        }
+    }
+}
+
+pub(in crate::resolve) fn packed_conversion_result_width(
+    conversion: &crate::model::PackedConversion,
+) -> u32 {
+    match conversion.destination_format {
+        PackedConversionDestinationFormat::Bf16x2 | PackedConversionDestinationFormat::F16x2 => 32,
+        PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2 => 16,
+    }
+}
+
+pub(in crate::resolve) fn packed_conversion_floor(
+    conversion: &crate::model::PackedConversion,
+) -> (&'static str, &'static str) {
+    // FP8 on either side carries the Ada floor, including when FP8 is the
+    // source and the destination is the older `f16x2`.
+    if packed_conversion_uses_fp8(conversion) {
+        return ("8.1", "sm_89");
+    }
+    match conversion.destination_format {
+        PackedConversionDestinationFormat::Bf16x2 | PackedConversionDestinationFormat::F16x2 => {
+            ("7.0", "sm_80")
+        }
+        PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2 => {
+            ("8.1", "sm_89")
+        }
+    }
+}
+
+pub(in crate::resolve) fn packed_conversion_backend_mechanism(
+    conversion: &crate::model::PackedConversion,
+    backend: IntrinsicBackend,
+) -> BackendLoweringMechanism {
+    match (packed_conversion_uses_typed_nvvm(conversion), backend) {
+        (true, IntrinsicBackend::LlvmNvptx) => BackendLoweringMechanism::TypedNvvm,
+        _ => BackendLoweringMechanism::InlinePtx,
+    }
+}
+
+/// Whether the conversion lowers through a typed NVVM intrinsic call.
+///
+/// Only the scalar-`f32` pair does. The `f16x2` sources and destinations carry
+/// their halves in one integer register on the MIR side, while the typed
+/// intrinsics are declared over `<2 x half>`; routing them through inline PTX
+/// avoids a packed-half MIR type for no change in emitted code. The recorded
+/// evidence assembles both routes to a byte-identical cubin, so the typed route
+/// can be switched on later without changing the PTX contract.
+pub(in crate::resolve) fn packed_conversion_uses_typed_nvvm(
+    conversion: &crate::model::PackedConversion,
+) -> bool {
+    conversion.source_format == PackedConversionSourceFormat::F32x2
+        && matches!(
+            conversion.destination_format,
+            PackedConversionDestinationFormat::E4m3x2 | PackedConversionDestinationFormat::E5m2x2
+        )
+}
+
+pub(in crate::resolve) fn packed_conversion_lowering(
+    conversion: &crate::model::PackedConversion,
+) -> &'static str {
+    if packed_conversion_uses_typed_nvvm(conversion) {
+        "generated_packed_conversion_backend"
+    } else {
+        "generated_packed_conversion_inline_ptx"
+    }
+}
+
+pub(in crate::resolve) fn expand_packed_conversion_fp8_admission(
+    admission: &PackedConversionFp8Admission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "FP8 conversion runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        admission.destination_formats
+            == [
+                PackedConversionDestinationFormat::E4m3x2,
+                PackedConversionDestinationFormat::E5m2x2,
+            ],
+        "compact FP8 conversion admission must list the canonical two formats"
+    );
+    ensure!(
+        admission.saturations
+            == [
+                PackedConversionSaturation::Satfinite,
+                PackedConversionSaturation::SatfiniteRelu,
+            ],
+        "compact FP8 conversion admission must list base and ReLU finite saturation"
+    );
+    ensure!(
+        admission.product_count
+            == admission
+                .destination_formats
+                .len()
+                .checked_mul(admission.saturations.len())
+                .context("compact FP8 conversion product count overflow")?
+            && admission.product_count == 4,
+        "compact FP8 conversion product_count must be exactly 4"
+    );
+
+    let mut records = Vec::with_capacity(admission.product_count);
+    for &destination_format in &admission.destination_formats {
+        for &saturation in &admission.saturations {
+            let conversion = crate::model::PackedConversion {
+                source_format: PackedConversionSourceFormat::F32x2,
+                destination_format,
+                rounding: PackedConversionRounding::NearestEven,
+                saturation,
+                adapter: PackedConversionAdapter::ReverseHighLowOperands,
+            };
+            records.push(packed_conversion_overlay_record(
+                conversion,
+                &admission.llvm_evidence_profile,
+                &admission.libnvvm_evidence_profile,
+            )?);
+        }
+    }
+    ensure!(records.len() == admission.product_count);
+    Ok(records)
+}
+
+pub(in crate::resolve) fn expand_packed_conversion_fp8_f16x2_admission(
+    admission: &PackedConversionFp8F16x2Admission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "FP8 f16x2 conversion runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        admission.fp8_formats
+            == [
+                PackedConversionFp8Format::E4m3x2,
+                PackedConversionFp8Format::E5m2x2,
+            ],
+        "compact FP8 f16x2 conversion admission must list the canonical two formats"
+    );
+    ensure!(
+        admission.directions
+            == [
+                PackedConversionFp8Direction::Pack,
+                PackedConversionFp8Direction::Unpack,
+            ],
+        "compact FP8 f16x2 conversion admission must list both conversion directions"
+    );
+    ensure!(
+        admission.relu_variants,
+        "compact FP8 f16x2 conversion admission must admit the ReLU variants"
+    );
+    ensure!(
+        admission.product_count
+            == admission
+                .fp8_formats
+                .len()
+                .checked_mul(admission.directions.len())
+                .and_then(|count| count.checked_mul(2))
+                .context("compact FP8 f16x2 conversion product count overflow")?
+            && admission.product_count == 8,
+        "compact FP8 f16x2 conversion product_count must be exactly 8"
+    );
+
+    let mut records = Vec::with_capacity(admission.product_count);
+    for &fp8_format in &admission.fp8_formats {
+        for &direction in &admission.directions {
+            for relu in [false, true] {
+                let conversion = match direction {
+                    // Narrowing to FP8 always saturates to finite.
+                    PackedConversionFp8Direction::Pack => crate::model::PackedConversion {
+                        source_format: PackedConversionSourceFormat::F16x2,
+                        destination_format: match fp8_format {
+                            PackedConversionFp8Format::E4m3x2 => {
+                                PackedConversionDestinationFormat::E4m3x2
+                            }
+                            PackedConversionFp8Format::E5m2x2 => {
+                                PackedConversionDestinationFormat::E5m2x2
+                            }
+                        },
+                        rounding: PackedConversionRounding::NearestEven,
+                        saturation: if relu {
+                            PackedConversionSaturation::SatfiniteRelu
+                        } else {
+                            PackedConversionSaturation::Satfinite
+                        },
+                        adapter: PackedConversionAdapter::Identity,
+                    },
+                    // Widening back to f16x2 is exact, so it carries no
+                    // saturation modifier of its own.
+                    PackedConversionFp8Direction::Unpack => crate::model::PackedConversion {
+                        source_format: match fp8_format {
+                            PackedConversionFp8Format::E4m3x2 => {
+                                PackedConversionSourceFormat::E4m3x2
+                            }
+                            PackedConversionFp8Format::E5m2x2 => {
+                                PackedConversionSourceFormat::E5m2x2
+                            }
+                        },
+                        destination_format: PackedConversionDestinationFormat::F16x2,
+                        rounding: PackedConversionRounding::NearestEven,
+                        saturation: if relu {
+                            PackedConversionSaturation::Relu
+                        } else {
+                            PackedConversionSaturation::None
+                        },
+                        adapter: PackedConversionAdapter::Identity,
+                    },
+                };
+                records.push(packed_conversion_overlay_record(
+                    conversion,
+                    &admission.llvm_evidence_profile,
+                    &admission.libnvvm_evidence_profile,
+                )?);
+            }
+        }
+    }
+    ensure!(records.len() == admission.product_count);
+    Ok(records)
+}
+
+pub(in crate::resolve) fn packed_conversion_overlay_record(
+    conversion: crate::model::PackedConversion,
+    llvm_evidence_profile: &str,
+    libnvvm_evidence_profile: &str,
+) -> Result<OverlayIntrinsic> {
+    let recipe = packed_conversion_recipe(&conversion)
+        .context("compact FP8 conversion is outside the closed recipe set")?;
+    let result_width = packed_conversion_result_width(&conversion);
+    let rust_result = format!("u{result_width}");
+    let dialect_result = format!("i{result_width}");
+    let (minimum_ptx, minimum_sm) = packed_conversion_floor(&conversion);
+    let (rust_arguments, dialect_operands, llvm_arguments) =
+        packed_conversion_source_types(&conversion);
+    // `cvt` writes one destination and reads every source operand.
+    let ptx_operands = conversion
+        .source_format
+        .operand_count()
+        .checked_add(1)
+        .context("packed-conversion operand count overflow")?;
+    Ok(OverlayIntrinsic {
+        id: recipe.id.into(),
+        abi_id: String::new(),
+        operation_key: recipe.operation_key.into(),
+        family: "packed_conversion".into(),
+        source: None,
+        source_record: Some(recipe.source_record.into()),
+        rust_module: "convert".into(),
+        rust_name: recipe.rust_name.into(),
+        rust_arguments,
+        rust_result: rust_result.clone(),
+        safe: true,
+        must_use: false,
+        safe_allowlist_reason: Some("This conversion has no caller obligations.".into()),
+        public_rust_path: format!("cuda_intrinsics::convert::{}", recipe.rust_name),
+        compatibility_rust_paths: vec![recipe.compatibility_path.into()],
+        dialect_op_type: recipe.dialect_op_type.into(),
+        dialect_op_name: recipe.dialect_op_name.into(),
+        dialect_operands,
+        dialect_results: vec![dialect_result],
+        llvm_symbol: Some(recipe.llvm_symbol.into()),
+        resolved_llvm_symbol: None,
+        llvm_arguments,
+        llvm_results: vec![recipe.llvm_result.into()],
+        pure: true,
+        memory: "none".into(),
+        convergent: false,
+        execution_scope: "thread".into(),
+        minimum_ptx: minimum_ptx.into(),
+        minimum_sm: Some(minimum_sm.into()),
+        ptx_result: rust_result,
+        targets: "all".into(),
+        ptx_isa_version: "9.3".into(),
+        ptx_isa_section: "9.7.9.22 Data Movement and Conversion Instructions: cvt".into(),
+        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt".into(),
+        lowering: packed_conversion_lowering(&conversion).into(),
+        backend_lowerings: [
+            (IntrinsicBackend::LlvmNvptx, llvm_evidence_profile),
+            (IntrinsicBackend::LibNvvm, libnvvm_evidence_profile),
+        ]
+        .into_iter()
+        .map(|(backend, evidence_profile)| OverlayBackendLowering {
+            backend,
+            mechanism: packed_conversion_backend_mechanism(&conversion, backend),
+            evidence_profile: evidence_profile.into(),
+            targets: None,
+            minimum_ptx: Some(minimum_ptx.into()),
+            minimum_sm: Some(minimum_sm.into()),
+        })
+        .collect(),
+        packed_atomic: None,
+        redux: None,
+        vote: None,
+        active_mask: None,
+        warp_match: None,
+        warp_barrier: None,
+        warp_shuffle: None,
+        dot_product: None,
+        packed_alu: None,
+        integer_minmax: None,
+        packed_conversion: Some(conversion.clone()),
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cp_async_copy: None,
+        cp_async_control: None,
+        cp_async_mbarrier: None,
+        mbarrier_basic: None,
+        movmatrix: None,
+        mbarrier_extended: None,
+        register_mma: None,
+        sparse_mma: None,
+        prmt: None,
+        cluster_barrier: None,
+        wgmma_control: None,
+        special_register: None,
+        debug_control: None,
+        cluster_memory: None,
+        clc: None,
+        tma: None,
+        tcgen05: None,
+        ldmatrix_variant: None,
+        ldmatrix_safety: None,
+        ldmatrix_adapter: None,
+        selected_address_space: None,
+        expected_ptx: InstructionPattern {
+            mnemonic: "cvt".into(),
+            modifiers: packed_conversion_ptx_modifiers(&conversion)
+                .into_iter()
+                .map(str::to_owned)
+                .collect(),
+            operands: vec![OperandPattern::Register; ptx_operands],
+        },
+        summary: recipe.summary.into(),
+    })
+}
+
+pub(in crate::resolve) fn validate_packed_conversion_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+    declaration: Option<&ImportedIntrinsic>,
+) -> Result<()> {
+    let conversion = policy
+        .packed_conversion
+        .as_ref()
+        .with_context(|| format!("{} has no closed packed-conversion contract", policy.id))?;
+    // The adapter is a function of the source arity: two scalar operands are
+    // reversed so the first Rust argument lands in the low half, while a single
+    // packed operand is forwarded unchanged.
+    let expected_adapter = match conversion.source_format {
+        PackedConversionSourceFormat::F32x2 => PackedConversionAdapter::ReverseHighLowOperands,
+        PackedConversionSourceFormat::E4m3x2
+        | PackedConversionSourceFormat::E5m2x2
+        | PackedConversionSourceFormat::F16x2 => PackedConversionAdapter::Identity,
+    };
+    ensure!(
+        conversion.adapter == expected_adapter,
+        "{} requests an unsupported packed-conversion source or adapter",
+        policy.id
+    );
+    let recipe = packed_conversion_recipe(conversion).with_context(|| {
+        format!(
+            "{} requests an unsupported packed-conversion source, destination, rounding, or saturation combination",
+            policy.id
+        )
+    })?;
+    let result_width = packed_conversion_result_width(conversion);
+    let rust_result = format!("u{result_width}");
+    let dialect_result = format!("i{result_width}");
+    let (minimum_ptx, minimum_sm) = packed_conversion_floor(conversion);
+    let (expected_rust_arguments, expected_dialect_operands, expected_llvm_arguments) =
+        packed_conversion_source_types(conversion);
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && source
+                == &IntrinsicSource::LlvmImported {
+                    source_record: recipe.source_record.into(),
+                }
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none()
+            && policy.llvm_arguments == expected_llvm_arguments
+            && policy.llvm_results == [recipe.llvm_result],
+        "{} packed-conversion identity or LLVM source changed",
+        policy.id
+    );
+    let declaration = declaration.context("packed conversion has no imported declaration")?;
+    ensure!(
+        declaration.properties == ["IntrNoMem", "IntrSpeculatable"]
+            && declaration.selections.is_empty(),
+        "{} selectionless packed-conversion declaration changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "convert"
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == expected_rust_arguments
+            && policy.rust_result == rust_result
+            && policy.safe
+            && !policy.must_use
+            && policy
+                .safe_allowlist_reason
+                .as_deref()
+                .is_some_and(|reason| !reason.trim().is_empty())
+            && policy.public_rust_path == format!("cuda_intrinsics::convert::{}", recipe.rust_name)
+            && policy.compatibility_rust_paths == [recipe.compatibility_path],
+        "{} must preserve its safe non-must-use conversion API",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == expected_dialect_operands
+            && policy.dialect_results == [dialect_result.as_str()]
+            && policy.lowering == packed_conversion_lowering(conversion),
+        "{} is outside the closed packed-conversion dialect and lowering recipe",
+        policy.id
+    );
+    ensure!(
+        policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == minimum_ptx
+            && policy.minimum_sm.as_deref() == Some(minimum_sm)
+            && policy.ptx_result == rust_result
+            && policy.targets == "all"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == "9.7.9.22 Data Movement and Conversion Instructions: cvt"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt",
+        "{} packed-conversion effects, carrier, target floor, or PTX provenance disagree",
+        policy.id
+    );
+    let expected_ptx_operands = vec![
+        OperandPattern::Register;
+        conversion
+            .source_format
+            .operand_count()
+            .checked_add(1)
+            .context("packed-conversion operand count overflow")?
+    ];
+    ensure!(
+        policy.expected_ptx.mnemonic == "cvt"
+            && policy.expected_ptx.modifiers == packed_conversion_ptx_modifiers(conversion)
+            && policy.expected_ptx.operands == expected_ptx_operands,
+        "{} expected PTX does not match its closed conversion recipe",
+        policy.id
+    );
+    ensure!(
+        policy.summary == recipe.summary,
+        "{} packed-conversion summary does not match its closed recipe",
+        policy.id
+    );
+    let backend_pairs = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect::<BTreeSet<_>>();
+    let expected_pairs = [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
+        .map(|backend| {
+            (
+                backend,
+                packed_conversion_backend_mechanism(conversion, backend),
+            )
+        })
+        .into_iter()
+        .collect::<BTreeSet<_>>();
+    ensure!(
+        policy.backend_lowerings.len() == 2 && backend_pairs == expected_pairs,
+        "{} must define exactly the reviewed packed-conversion backend routes",
+        policy.id
+    );
+    for lowering in &policy.backend_lowerings {
+        ensure!(
+            lowering.minimum_ptx.as_deref() == Some(minimum_ptx)
+                && lowering.minimum_sm.as_deref() == Some(minimum_sm)
+                && !lowering.evidence_profile.trim().is_empty(),
+            "{} backend {:?} does not carry its exact packed-conversion floor",
+            policy.id,
+            lowering.backend
+        );
+    }
+    ensure_no_other_family_contract(policy, "packed conversion")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/prmt.rs b/crates/cuda-intrinsics-gen/src/resolve/families/prmt.rs
new file mode 100644
index 0000000000..2c25bda706
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/prmt.rs
@@ -0,0 +1,410 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, OverlayBackendLowering,
+    OverlayIntrinsic, Prmt, PrmtAdapter, PrmtAdmission, PrmtMode, RuntimeValidation,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use crate::resolve::guards::*;
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct PrmtRecipe {
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) modifier: Option<&'static str>,
+    pub(in crate::resolve) adapter: PrmtAdapter,
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn prmt_recipe(mode: PrmtMode) -> PrmtRecipe {
+    use PrmtAdapter::{DirectThreeOperands, InsertZeroSecondSource};
+    match mode {
+        PrmtMode::Generic => PrmtRecipe {
+            abi_id: "i0252",
+            id: "prmt",
+            operation_key: "integer.prmt.b32",
+            source_record: "int_nvvm_prmt",
+            llvm_symbol: "llvm.nvvm.prmt",
+            modifier: None,
+            adapter: DirectThreeOperands,
+            summary: "Permutes bytes selected from two 32-bit inputs.",
+        },
+        PrmtMode::F4e => PrmtRecipe {
+            abi_id: "i0253",
+            id: "prmt_f4e",
+            operation_key: "integer.prmt.b32.f4e",
+            source_record: "int_nvvm_prmt_f4e",
+            llvm_symbol: "llvm.nvvm.prmt.f4e",
+            modifier: Some("f4e"),
+            adapter: DirectThreeOperands,
+            summary: "Permutes bytes with the forward four-byte extract mode.",
+        },
+        PrmtMode::B4e => PrmtRecipe {
+            abi_id: "i0254",
+            id: "prmt_b4e",
+            operation_key: "integer.prmt.b32.b4e",
+            source_record: "int_nvvm_prmt_b4e",
+            llvm_symbol: "llvm.nvvm.prmt.b4e",
+            modifier: Some("b4e"),
+            adapter: DirectThreeOperands,
+            summary: "Permutes bytes with the backward four-byte extract mode.",
+        },
+        PrmtMode::Rc8 => PrmtRecipe {
+            abi_id: "i0255",
+            id: "prmt_rc8",
+            operation_key: "integer.prmt.b32.rc8",
+            source_record: "int_nvvm_prmt_rc8",
+            llvm_symbol: "llvm.nvvm.prmt.rc8",
+            modifier: Some("rc8"),
+            adapter: InsertZeroSecondSource,
+            summary: "Replicates a selected byte across the 32-bit result.",
+        },
+        PrmtMode::Ecl => PrmtRecipe {
+            abi_id: "i0256",
+            id: "prmt_ecl",
+            operation_key: "integer.prmt.b32.ecl",
+            source_record: "int_nvvm_prmt_ecl",
+            llvm_symbol: "llvm.nvvm.prmt.ecl",
+            modifier: Some("ecl"),
+            adapter: InsertZeroSecondSource,
+            summary: "Clamps a byte extract toward the least-significant byte.",
+        },
+        PrmtMode::Ecr => PrmtRecipe {
+            abi_id: "i0257",
+            id: "prmt_ecr",
+            operation_key: "integer.prmt.b32.ecr",
+            source_record: "int_nvvm_prmt_ecr",
+            llvm_symbol: "llvm.nvvm.prmt.ecr",
+            modifier: Some("ecr"),
+            adapter: InsertZeroSecondSource,
+            summary: "Clamps a byte extract toward the most-significant byte.",
+        },
+        PrmtMode::Rc16 => PrmtRecipe {
+            abi_id: "i0258",
+            id: "prmt_rc16",
+            operation_key: "integer.prmt.b32.rc16",
+            source_record: "int_nvvm_prmt_rc16",
+            llvm_symbol: "llvm.nvvm.prmt.rc16",
+            modifier: Some("rc16"),
+            adapter: InsertZeroSecondSource,
+            summary: "Replicates a selected 16-bit half across the result.",
+        },
+    }
+}
+
+pub(in crate::resolve) fn expand_prmt_admission(
+    admission: &PrmtAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "prmt runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact prmt admission requires both backend evidence profiles"
+    );
+    let expected_modes = BTreeSet::from([
+        PrmtMode::Generic,
+        PrmtMode::F4e,
+        PrmtMode::B4e,
+        PrmtMode::Rc8,
+        PrmtMode::Ecl,
+        PrmtMode::Ecr,
+        PrmtMode::Rc16,
+    ]);
+    let actual_modes: BTreeSet<_> = admission
+        .variants
+        .iter()
+        .map(|variant| variant.mode)
+        .collect();
+    ensure!(
+        admission.variants.len() == expected_modes.len() && actual_modes == expected_modes,
+        "compact prmt admission must contain each of the seven reviewed modes exactly once"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = prmt_recipe(variant.mode);
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must keep reserved ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            let three_operands = recipe.adapter == PrmtAdapter::DirectThreeOperands;
+            let rust_arguments = vec!["u32".into(); if three_operands { 3 } else { 2 }];
+            let llvm_arguments = vec!["i32".into(); if three_operands { 3 } else { 2 }];
+            let mut modifiers = vec!["b32".into()];
+            if let Some(modifier) = recipe.modifier {
+                modifiers.push(modifier.into());
+            }
+            let operands = if three_operands {
+                vec![
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                ]
+            } else {
+                vec![
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                    OperandPattern::Exact { value: "0".into() },
+                    OperandPattern::Register,
+                ]
+            };
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: variant.abi_id.clone(),
+                operation_key: recipe.operation_key.into(),
+                family: "prmt".into(),
+                source: None,
+                source_record: Some(recipe.source_record.into()),
+                rust_module: "prmt".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments,
+                rust_result: "u32".into(),
+                safe: true,
+                must_use: true,
+                safe_allowlist_reason: Some(
+                    "it only permutes register bytes and has no caller preconditions.".into(),
+                ),
+                public_rust_path: format!("cuda_intrinsics::prmt::{}", recipe.id),
+                compatibility_rust_paths: vec![format!("cuda_device::prmt::{}", recipe.id)],
+                dialect_op_type: "PrmtOp".into(),
+                dialect_op_name: "nvvm.prmt".into(),
+                dialect_operands: llvm_arguments.clone(),
+                dialect_results: vec!["i32".into()],
+                llvm_symbol: Some(recipe.llvm_symbol.into()),
+                resolved_llvm_symbol: None,
+                llvm_arguments,
+                llvm_results: vec!["i32".into()],
+                pure: true,
+                memory: "none".into(),
+                convergent: false,
+                execution_scope: "thread".into(),
+                minimum_ptx: "2.0".into(),
+                minimum_sm: Some("sm_20".into()),
+                ptx_result: "u32".into(),
+                targets: "all".into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section: "9.7.9.7 Data Movement and Conversion Instructions: prmt".into(),
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-prmt".into(),
+                lowering: "generated_prmt".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: BackendLoweringMechanism::TypedNvvm,
+                        evidence_profile: admission.llvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some("3.2".into()),
+                        minimum_sm: Some("sm_20".into()),
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: None,
+                        minimum_sm: Some("sm_75".into()),
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: Some(Prmt {
+                    mode: variant.mode,
+                    adapter: recipe.adapter,
+                }),
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: "prmt".into(),
+                    modifiers,
+                    operands,
+                },
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn validate_prmt_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let prmt = policy
+        .prmt
+        .as_ref()
+        .with_context(|| format!("{} has no closed prmt contract", policy.id))?;
+    let recipe = prmt_recipe(prmt.mode);
+    let three_operands = recipe.adapter == PrmtAdapter::DirectThreeOperands;
+    ensure!(
+        prmt.adapter == recipe.adapter
+            && policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} prmt identity does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "prmt"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == vec!["u32"; if three_operands { 3 } else { 2 }]
+            && policy.rust_result == "u32"
+            && policy.safe
+            && policy.must_use
+            && policy.public_rust_path == format!("cuda_intrinsics::prmt::{}", recipe.id)
+            && policy.compatibility_rust_paths == [format!("cuda_device::prmt::{}", recipe.id)],
+        "{} prmt Rust API does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == "PrmtOp"
+            && policy.dialect_op_name == "nvvm.prmt"
+            && policy.dialect_operands == vec!["i32"; if three_operands { 3 } else { 2 }]
+            && policy.dialect_results == ["i32"]
+            && policy.llvm_arguments == policy.dialect_operands
+            && policy.llvm_results == ["i32"]
+            && policy.lowering == "generated_prmt",
+        "{} prmt carrier or lowering does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration
+            .classes
+            .iter()
+            .any(|class| class == "NVVMPureIntrinsic")
+            && declaration.properties == ["IntrNoMem", "IntrSpeculatable"]
+            && policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread",
+        "{} prmt effects disagree with the imported declaration",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == "2.0"
+            && policy.minimum_sm.as_deref() == Some("sm_20")
+            && policy.targets == "all"
+            && policy.ptx_result == "u32"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == "9.7.9.7 Data Movement and Conversion Instructions: prmt"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-prmt",
+        "{} prmt target floor or PTX provenance changed",
+        policy.id
+    );
+    let mut modifiers = vec!["b32"];
+    if let Some(modifier) = recipe.modifier {
+        modifiers.push(modifier);
+    }
+    let expected_operands = if three_operands {
+        vec![
+            OperandPattern::Register,
+            OperandPattern::Register,
+            OperandPattern::Register,
+            OperandPattern::Register,
+        ]
+    } else {
+        vec![
+            OperandPattern::Register,
+            OperandPattern::Register,
+            OperandPattern::Exact { value: "0".into() },
+            OperandPattern::Register,
+        ]
+    };
+    ensure!(
+        policy.expected_ptx.mnemonic == "prmt"
+            && policy.expected_ptx.modifiers == modifiers
+            && policy.expected_ptx.operands == expected_operands,
+        "{} expected PTX does not match its closed prmt mode",
+        policy.id
+    );
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ]),
+        "{} must define exactly the reviewed prmt backend routes",
+        policy.id
+    );
+    for lowering in &policy.backend_lowerings {
+        let floor_matches = match lowering.backend {
+            IntrinsicBackend::LlvmNvptx => {
+                lowering.minimum_ptx.as_deref() == Some("3.2")
+                    && lowering.minimum_sm.as_deref() == Some("sm_20")
+            }
+            IntrinsicBackend::LibNvvm => {
+                lowering.minimum_ptx.is_none() && lowering.minimum_sm.as_deref() == Some("sm_75")
+            }
+        };
+        ensure!(
+            floor_matches && !lowering.evidence_profile.trim().is_empty(),
+            "{} backend {:?} does not carry its reviewed prmt floor",
+            policy.id,
+            lowering.backend
+        );
+    }
+    ensure_no_other_family_contract(policy, "prmt")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/redux_dotprod.rs b/crates/cuda-intrinsics-gen/src/resolve/families/redux_dotprod.rs
new file mode 100644
index 0000000000..2794b77211
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/redux_dotprod.rs
@@ -0,0 +1,627 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, DotProductAdapter, DotProductOperation, DotProductSignedness,
+    ImportedIntrinsic, IntrinsicBackend, OverlayIntrinsic, ReduxAdapter, ReduxOperation,
+    ReduxParticipation,
+};
+use crate::ptx::OperandPattern;
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+pub(in crate::resolve) fn validate_redux_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let redux = policy
+        .redux
+        .as_ref()
+        .with_context(|| format!("{} has no closed redux contract", policy.id))?;
+    let recipe = redux_recipe(redux.operation);
+    ensure!(
+        redux.participation
+            == ReduxParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask
+            && redux.adapter == ReduxAdapter::MaskValueToSourceMemberMask,
+        "{} requests an unsupported redux participation contract or operand adapter",
+        policy.id
+    );
+    ensure!(
+        policy.id == recipe.id
+            && policy.operation_key == recipe.operation_key
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} redux identity does not match its closed operation recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "warp"
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == ["u32", recipe.rust_value]
+            && policy.rust_result == recipe.rust_value
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::warp::{}", recipe.rust_name)
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::warp::{}", recipe.rust_name)],
+        "{} must preserve the unsafe must-use redux raw API and legacy cuda-device compatibility DefPath",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == ["i32", recipe.value_type]
+            && policy.dialect_results == [recipe.value_type]
+            && policy.llvm_arguments == [recipe.value_type, "i32"]
+            && policy.llvm_results == [recipe.value_type]
+            && policy.lowering == "generated_redux",
+        "{} is outside the generated two-operand redux recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "inaccessible_read_write"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == recipe.minimum_sm
+            && policy.ptx_result == recipe.rust_value
+            && policy.targets == recipe.targets,
+        "{} redux effects, carrier, or target floor disagree with its operation recipe",
+        policy.id
+    );
+    ensure!(
+        declaration
+            .properties
+            .iter()
+            .any(|property| property == "IntrConvergent")
+            && declaration
+                .properties
+                .iter()
+                .any(|property| property == "IntrInaccessibleMemOnly")
+            && declaration
+                .properties
+                .iter()
+                .any(|property| property == "IntrNoCallback")
+            && !declaration.properties.iter().any(|property| matches!(
+                property.as_str(),
+                "IntrNoMem" | "IntrReadMem" | "IntrWriteMem"
+            )),
+        "{} redux memory and convergence effects disagree with the imported declaration",
+        policy.id
+    );
+    ensure!(
+        policy.backend_lowerings.is_empty()
+            && policy.packed_atomic.is_none()
+            && policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with redux",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "redux"
+            && policy.expected_ptx.modifiers == recipe.ptx_modifiers
+            && policy.expected_ptx.operands
+                == [
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                ],
+        "{} expected PTX does not match its closed redux operation recipe",
+        policy.id
+    );
+    Ok(())
+}
+
+// Pinned LLVM's hasReduxSyncF32(): accel {100} at PTX 8.6, family {100} at
+// PTX 8.8. The catalog carries the accel floor with the a/f target union.
+pub(in crate::resolve) const REDUX_F32_TARGETS: &str = "sm_100a|sm_100f|sm_103a|sm_103f";
+
+pub(in crate::resolve) struct ReduxRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) rust_name: &'static str,
+    pub(in crate::resolve) rust_value: &'static str,
+    pub(in crate::resolve) value_type: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) ptx_modifiers: &'static [&'static str],
+    pub(in crate::resolve) minimum_ptx: &'static str,
+    pub(in crate::resolve) minimum_sm: Option<&'static str>,
+    pub(in crate::resolve) targets: &'static str,
+}
+
+pub(in crate::resolve) fn redux_recipe(operation: ReduxOperation) -> ReduxRecipe {
+    match operation {
+        ReduxOperation::Add => ReduxRecipe {
+            id: "redux_sync_add",
+            operation_key: "warp.redux.sync.add.wrap32",
+            source_record: "int_nvvm_redux_sync_add",
+            llvm_symbol: "llvm.nvvm.redux.sync.add",
+            rust_name: "redux_sync_add",
+            rust_value: "u32",
+            value_type: "i32",
+            dialect_op_type: "ReduxSyncAddOp",
+            dialect_op_name: "nvvm.redux_sync_add",
+            ptx_modifiers: &["sync", "add", "s32"],
+            minimum_ptx: "7.0",
+            minimum_sm: Some("sm_80"),
+            targets: "all",
+        },
+        ReduxOperation::Umin => ReduxRecipe {
+            id: "redux_sync_min_u32",
+            operation_key: "warp.redux.sync.min.u32",
+            source_record: "int_nvvm_redux_sync_umin",
+            llvm_symbol: "llvm.nvvm.redux.sync.umin",
+            rust_name: "redux_sync_min_u32",
+            rust_value: "u32",
+            value_type: "i32",
+            dialect_op_type: "ReduxSyncUminOp",
+            dialect_op_name: "nvvm.redux_sync_umin",
+            ptx_modifiers: &["sync", "min", "u32"],
+            minimum_ptx: "7.0",
+            minimum_sm: Some("sm_80"),
+            targets: "all",
+        },
+        ReduxOperation::Min => ReduxRecipe {
+            id: "redux_sync_min_i32",
+            operation_key: "warp.redux.sync.min.s32",
+            source_record: "int_nvvm_redux_sync_min",
+            llvm_symbol: "llvm.nvvm.redux.sync.min",
+            rust_name: "redux_sync_min_i32",
+            rust_value: "i32",
+            value_type: "i32",
+            dialect_op_type: "ReduxSyncMinOp",
+            dialect_op_name: "nvvm.redux_sync_min",
+            ptx_modifiers: &["sync", "min", "s32"],
+            minimum_ptx: "7.0",
+            minimum_sm: Some("sm_80"),
+            targets: "all",
+        },
+        ReduxOperation::Umax => ReduxRecipe {
+            id: "redux_sync_max_u32",
+            operation_key: "warp.redux.sync.max.u32",
+            source_record: "int_nvvm_redux_sync_umax",
+            llvm_symbol: "llvm.nvvm.redux.sync.umax",
+            rust_name: "redux_sync_max_u32",
+            rust_value: "u32",
+            value_type: "i32",
+            dialect_op_type: "ReduxSyncUmaxOp",
+            dialect_op_name: "nvvm.redux_sync_umax",
+            ptx_modifiers: &["sync", "max", "u32"],
+            minimum_ptx: "7.0",
+            minimum_sm: Some("sm_80"),
+            targets: "all",
+        },
+        ReduxOperation::Max => ReduxRecipe {
+            id: "redux_sync_max_i32",
+            operation_key: "warp.redux.sync.max.s32",
+            source_record: "int_nvvm_redux_sync_max",
+            llvm_symbol: "llvm.nvvm.redux.sync.max",
+            rust_name: "redux_sync_max_i32",
+            rust_value: "i32",
+            value_type: "i32",
+            dialect_op_type: "ReduxSyncMaxOp",
+            dialect_op_name: "nvvm.redux_sync_max",
+            ptx_modifiers: &["sync", "max", "s32"],
+            minimum_ptx: "7.0",
+            minimum_sm: Some("sm_80"),
+            targets: "all",
+        },
+        ReduxOperation::And => ReduxRecipe {
+            id: "redux_sync_and",
+            operation_key: "warp.redux.sync.and.b32",
+            source_record: "int_nvvm_redux_sync_and",
+            llvm_symbol: "llvm.nvvm.redux.sync.and",
+            rust_name: "redux_sync_and",
+            rust_value: "u32",
+            value_type: "i32",
+            dialect_op_type: "ReduxSyncAndOp",
+            dialect_op_name: "nvvm.redux_sync_and",
+            ptx_modifiers: &["sync", "and", "b32"],
+            minimum_ptx: "7.0",
+            minimum_sm: Some("sm_80"),
+            targets: "all",
+        },
+        ReduxOperation::Or => ReduxRecipe {
+            id: "redux_sync_or",
+            operation_key: "warp.redux.sync.or.b32",
+            source_record: "int_nvvm_redux_sync_or",
+            llvm_symbol: "llvm.nvvm.redux.sync.or",
+            rust_name: "redux_sync_or",
+            rust_value: "u32",
+            value_type: "i32",
+            dialect_op_type: "ReduxSyncOrOp",
+            dialect_op_name: "nvvm.redux_sync_or",
+            ptx_modifiers: &["sync", "or", "b32"],
+            minimum_ptx: "7.0",
+            minimum_sm: Some("sm_80"),
+            targets: "all",
+        },
+        ReduxOperation::Xor => ReduxRecipe {
+            id: "redux_sync_xor",
+            operation_key: "warp.redux.sync.xor.b32",
+            source_record: "int_nvvm_redux_sync_xor",
+            llvm_symbol: "llvm.nvvm.redux.sync.xor",
+            rust_name: "redux_sync_xor",
+            rust_value: "u32",
+            value_type: "i32",
+            dialect_op_type: "ReduxSyncXorOp",
+            dialect_op_name: "nvvm.redux_sync_xor",
+            ptx_modifiers: &["sync", "xor", "b32"],
+            minimum_ptx: "7.0",
+            minimum_sm: Some("sm_80"),
+            targets: "all",
+        },
+        ReduxOperation::Fmin => ReduxRecipe {
+            id: "redux_sync_min_f32",
+            operation_key: "warp.redux.sync.min.f32",
+            source_record: "int_nvvm_redux_sync_fmin",
+            llvm_symbol: "llvm.nvvm.redux.sync.fmin",
+            rust_name: "redux_sync_min_f32",
+            rust_value: "f32",
+            value_type: "f32",
+            dialect_op_type: "ReduxSyncFminOp",
+            dialect_op_name: "nvvm.redux_sync_fmin",
+            ptx_modifiers: &["sync", "min", "f32"],
+            minimum_ptx: "8.6",
+            minimum_sm: None,
+            targets: REDUX_F32_TARGETS,
+        },
+        ReduxOperation::FminNan => ReduxRecipe {
+            id: "redux_sync_min_nan_f32",
+            operation_key: "warp.redux.sync.min.nan.f32",
+            source_record: "int_nvvm_redux_sync_fmin_NaN",
+            llvm_symbol: "llvm.nvvm.redux.sync.fmin.NaN",
+            rust_name: "redux_sync_min_nan_f32",
+            rust_value: "f32",
+            value_type: "f32",
+            dialect_op_type: "ReduxSyncFminNanOp",
+            dialect_op_name: "nvvm.redux_sync_fmin_nan",
+            ptx_modifiers: &["sync", "min", "NaN", "f32"],
+            minimum_ptx: "8.6",
+            minimum_sm: None,
+            targets: REDUX_F32_TARGETS,
+        },
+        ReduxOperation::FminAbs => ReduxRecipe {
+            id: "redux_sync_min_abs_f32",
+            operation_key: "warp.redux.sync.min.abs.f32",
+            source_record: "int_nvvm_redux_sync_fmin_abs",
+            llvm_symbol: "llvm.nvvm.redux.sync.fmin.abs",
+            rust_name: "redux_sync_min_abs_f32",
+            rust_value: "f32",
+            value_type: "f32",
+            dialect_op_type: "ReduxSyncFminAbsOp",
+            dialect_op_name: "nvvm.redux_sync_fmin_abs",
+            ptx_modifiers: &["sync", "min", "abs", "f32"],
+            minimum_ptx: "8.6",
+            minimum_sm: None,
+            targets: REDUX_F32_TARGETS,
+        },
+        ReduxOperation::FminAbsNan => ReduxRecipe {
+            id: "redux_sync_min_abs_nan_f32",
+            operation_key: "warp.redux.sync.min.abs.nan.f32",
+            source_record: "int_nvvm_redux_sync_fmin_abs_NaN",
+            llvm_symbol: "llvm.nvvm.redux.sync.fmin.abs.NaN",
+            rust_name: "redux_sync_min_abs_nan_f32",
+            rust_value: "f32",
+            value_type: "f32",
+            dialect_op_type: "ReduxSyncFminAbsNanOp",
+            dialect_op_name: "nvvm.redux_sync_fmin_abs_nan",
+            ptx_modifiers: &["sync", "min", "abs", "NaN", "f32"],
+            minimum_ptx: "8.6",
+            minimum_sm: None,
+            targets: REDUX_F32_TARGETS,
+        },
+        ReduxOperation::Fmax => ReduxRecipe {
+            id: "redux_sync_max_f32",
+            operation_key: "warp.redux.sync.max.f32",
+            source_record: "int_nvvm_redux_sync_fmax",
+            llvm_symbol: "llvm.nvvm.redux.sync.fmax",
+            rust_name: "redux_sync_max_f32",
+            rust_value: "f32",
+            value_type: "f32",
+            dialect_op_type: "ReduxSyncFmaxOp",
+            dialect_op_name: "nvvm.redux_sync_fmax",
+            ptx_modifiers: &["sync", "max", "f32"],
+            minimum_ptx: "8.6",
+            minimum_sm: None,
+            targets: REDUX_F32_TARGETS,
+        },
+        ReduxOperation::FmaxNan => ReduxRecipe {
+            id: "redux_sync_max_nan_f32",
+            operation_key: "warp.redux.sync.max.nan.f32",
+            source_record: "int_nvvm_redux_sync_fmax_NaN",
+            llvm_symbol: "llvm.nvvm.redux.sync.fmax.NaN",
+            rust_name: "redux_sync_max_nan_f32",
+            rust_value: "f32",
+            value_type: "f32",
+            dialect_op_type: "ReduxSyncFmaxNanOp",
+            dialect_op_name: "nvvm.redux_sync_fmax_nan",
+            ptx_modifiers: &["sync", "max", "NaN", "f32"],
+            minimum_ptx: "8.6",
+            minimum_sm: None,
+            targets: REDUX_F32_TARGETS,
+        },
+        ReduxOperation::FmaxAbs => ReduxRecipe {
+            id: "redux_sync_max_abs_f32",
+            operation_key: "warp.redux.sync.max.abs.f32",
+            source_record: "int_nvvm_redux_sync_fmax_abs",
+            llvm_symbol: "llvm.nvvm.redux.sync.fmax.abs",
+            rust_name: "redux_sync_max_abs_f32",
+            rust_value: "f32",
+            value_type: "f32",
+            dialect_op_type: "ReduxSyncFmaxAbsOp",
+            dialect_op_name: "nvvm.redux_sync_fmax_abs",
+            ptx_modifiers: &["sync", "max", "abs", "f32"],
+            minimum_ptx: "8.6",
+            minimum_sm: None,
+            targets: REDUX_F32_TARGETS,
+        },
+        ReduxOperation::FmaxAbsNan => ReduxRecipe {
+            id: "redux_sync_max_abs_nan_f32",
+            operation_key: "warp.redux.sync.max.abs.nan.f32",
+            source_record: "int_nvvm_redux_sync_fmax_abs_NaN",
+            llvm_symbol: "llvm.nvvm.redux.sync.fmax.abs.NaN",
+            rust_name: "redux_sync_max_abs_nan_f32",
+            rust_value: "f32",
+            value_type: "f32",
+            dialect_op_type: "ReduxSyncFmaxAbsNanOp",
+            dialect_op_name: "nvvm.redux_sync_fmax_abs_nan",
+            ptx_modifiers: &["sync", "max", "abs", "NaN", "f32"],
+            minimum_ptx: "8.6",
+            minimum_sm: None,
+            targets: REDUX_F32_TARGETS,
+        },
+    }
+}
+
+pub(in crate::resolve) fn validate_dot_product_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let dot_product = policy
+        .dot_product
+        .as_ref()
+        .with_context(|| format!("{} has no closed dot-product contract", policy.id))?;
+    let recipe = dot_product_recipe(dot_product.operation, dot_product.signedness);
+    ensure!(
+        dot_product.adapter == recipe.adapter,
+        "{} dot-product source adapter does not match its operation",
+        policy.id
+    );
+    ensure!(
+        policy.id == recipe.id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} dot-product identity does not match its closed operation recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "dotprod"
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == ["u32", "u32", recipe.rust_value]
+            && policy.rust_result == recipe.rust_value
+            && policy.safe
+            && !policy.must_use
+            && policy.public_rust_path == format!("cuda_intrinsics::dotprod::{}", recipe.rust_name)
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::dotprod::{}", recipe.rust_name)],
+        "{} must preserve the safe, non-must-use dotprod raw API and legacy cuda-device DefPath",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == ["i32", "i32", "i32"]
+            && policy.dialect_results == ["i32"]
+            && policy.llvm_arguments == recipe.llvm_arguments
+            && policy.llvm_results == ["i32"]
+            && policy.lowering == "generated_dotprod",
+        "{} is outside the closed three-operand dot-product lowering recipe",
+        policy.id
+    );
+    ensure!(
+        policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == "5.0"
+            && policy.minimum_sm.as_deref() == Some("sm_61")
+            && policy.ptx_result == recipe.rust_value
+            && policy.targets == "all",
+        "{} dot-product effects, carrier, or target floor disagree with its operation recipe",
+        policy.id
+    );
+    ensure!(
+        declaration
+            .classes
+            .iter()
+            .any(|class| class == "NVVMPureIntrinsic")
+            && declaration.properties == recipe.llvm_properties,
+        "{} dot-product effects or immediate contract disagree with the imported declaration",
+        policy.id
+    );
+    ensure!(
+        policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with dotprod",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == recipe.ptx_mnemonic
+            && policy.expected_ptx.modifiers == recipe.ptx_modifiers
+            && policy.expected_ptx.operands
+                == [
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                ],
+        "{} expected PTX does not match its closed dot-product recipe",
+        policy.id
+    );
+
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ]),
+        "{} must define exactly the reviewed LLVM typed and libNVVM inline-PTX routes",
+        policy.id
+    );
+    for lowering in &policy.backend_lowerings {
+        let floor_matches = match lowering.backend {
+            IntrinsicBackend::LlvmNvptx => {
+                lowering.mechanism == BackendLoweringMechanism::TypedNvvm
+                    && lowering.minimum_ptx.is_none()
+                    && lowering.minimum_sm.is_none()
+            }
+            IntrinsicBackend::LibNvvm => {
+                lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                    && lowering.minimum_ptx.is_none()
+                    && lowering.minimum_sm.as_deref() == Some("sm_75")
+            }
+        };
+        ensure!(
+            floor_matches && !lowering.evidence_profile.trim().is_empty(),
+            "{} backend {:?} does not carry its reviewed dot-product profile floor",
+            policy.id,
+            lowering.backend
+        );
+    }
+    Ok(())
+}
+
+pub(in crate::resolve) struct DotProductRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) rust_name: &'static str,
+    pub(in crate::resolve) rust_value: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) llvm_arguments: &'static [&'static str],
+    pub(in crate::resolve) llvm_properties: &'static [&'static str],
+    pub(in crate::resolve) adapter: DotProductAdapter,
+    pub(in crate::resolve) ptx_mnemonic: &'static str,
+    pub(in crate::resolve) ptx_modifiers: &'static [&'static str],
+}
+
+pub(in crate::resolve) fn dot_product_recipe(
+    operation: DotProductOperation,
+    signedness: DotProductSignedness,
+) -> DotProductRecipe {
+    match (operation, signedness) {
+        (DotProductOperation::Dp4a, DotProductSignedness::Signed) => DotProductRecipe {
+            id: "dp4a_s32",
+            operation_key: "integer.dot_product.dp4a.s32",
+            source_record: "int_nvvm_idp4a_s_s",
+            llvm_symbol: "llvm.nvvm.idp4a.s.s",
+            rust_name: "dp4a_s32",
+            rust_value: "i32",
+            dialect_op_type: "Dp4aS32Op",
+            dialect_op_name: "nvvm.dp4a_s32",
+            llvm_arguments: &["i32", "i32", "i32"],
+            llvm_properties: &["IntrNoMem", "IntrSpeculatable"],
+            adapter: DotProductAdapter::DirectThreeOperands,
+            ptx_mnemonic: "dp4a",
+            ptx_modifiers: &["s32", "s32"],
+        },
+        (DotProductOperation::Dp4a, DotProductSignedness::Unsigned) => DotProductRecipe {
+            id: "dp4a_u32",
+            operation_key: "integer.dot_product.dp4a.u32",
+            source_record: "int_nvvm_idp4a_u_u",
+            llvm_symbol: "llvm.nvvm.idp4a.u.u",
+            rust_name: "dp4a_u32",
+            rust_value: "u32",
+            dialect_op_type: "Dp4aU32Op",
+            dialect_op_name: "nvvm.dp4a_u32",
+            llvm_arguments: &["i32", "i32", "i32"],
+            llvm_properties: &["IntrNoMem", "IntrSpeculatable"],
+            adapter: DotProductAdapter::DirectThreeOperands,
+            ptx_mnemonic: "dp4a",
+            ptx_modifiers: &["u32", "u32"],
+        },
+        (DotProductOperation::Dp2a, DotProductSignedness::Signed) => DotProductRecipe {
+            id: "dp2a_s32",
+            operation_key: "integer.dot_product.dp2a.lo.s32",
+            source_record: "int_nvvm_idp2a_s_s",
+            llvm_symbol: "llvm.nvvm.idp2a.s.s",
+            rust_name: "dp2a_s32",
+            rust_value: "i32",
+            dialect_op_type: "Dp2aS32Op",
+            dialect_op_name: "nvvm.dp2a_s32",
+            llvm_arguments: &["i32", "i32", "i1", "i32"],
+            llvm_properties: &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"],
+            adapter: DotProductAdapter::InsertLowHalfFalse,
+            ptx_mnemonic: "dp2a",
+            ptx_modifiers: &["lo", "s32", "s32"],
+        },
+        (DotProductOperation::Dp2a, DotProductSignedness::Unsigned) => DotProductRecipe {
+            id: "dp2a_u32",
+            operation_key: "integer.dot_product.dp2a.lo.u32",
+            source_record: "int_nvvm_idp2a_u_u",
+            llvm_symbol: "llvm.nvvm.idp2a.u.u",
+            rust_name: "dp2a_u32",
+            rust_value: "u32",
+            dialect_op_type: "Dp2aU32Op",
+            dialect_op_name: "nvvm.dp2a_u32",
+            llvm_arguments: &["i32", "i32", "i1", "i32"],
+            llvm_properties: &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"],
+            adapter: DotProductAdapter::InsertLowHalfFalse,
+            ptx_mnemonic: "dp2a",
+            ptx_modifiers: &["lo", "u32", "u32"],
+        },
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/scalar_arithmetic.rs b/crates/cuda-intrinsics-gen/src/resolve/families/scalar_arithmetic.rs
new file mode 100644
index 0000000000..17f39ba0bb
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/scalar_arithmetic.rs
@@ -0,0 +1,661 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, OverlayBackendLowering,
+    OverlayIntrinsic, RuntimeValidation, ScalarArithmetic, ScalarArithmeticAdmission,
+    ScalarArithmeticFormat, ScalarArithmeticOperation, ScalarArithmeticRounding,
+    ScalarArithmeticSaturation, ScalarArithmeticSubnormal,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+
+use crate::resolve::abi_ledger::*;
+use crate::resolve::guards::*;
+use crate::resolve::targets::*;
+
+#[derive(Clone)]
+pub(in crate::resolve) struct ScalarArithmeticRecipe {
+    id: String,
+    operation_key: String,
+    source_record: String,
+    llvm_symbol: String,
+    selection_record: String,
+    selection_asm: String,
+    rust_type: &'static str,
+    argument_count: usize,
+    properties: Vec<&'static str>,
+    ptx_modifiers: Vec<String>,
+    ptx_isa_section: &'static str,
+    ptx_isa_url: &'static str,
+}
+
+pub(in crate::resolve) type ScalarArithmeticVariant = (
+    ScalarArithmeticFormat,
+    ScalarArithmeticOperation,
+    ScalarArithmeticRounding,
+    ScalarArithmeticSubnormal,
+    ScalarArithmeticSaturation,
+);
+
+pub(in crate::resolve) fn canonical_scalar_arithmetic_variants() -> Vec<ScalarArithmeticVariant> {
+    use ScalarArithmeticFormat::{F32, F64};
+    use ScalarArithmeticOperation::{Add, Div, Fma, Mul};
+    use ScalarArithmeticRounding::{Rm, Rn, Rp, Rz};
+    use ScalarArithmeticSaturation::{None, Sat};
+    use ScalarArithmeticSubnormal::{Ftz, Preserve};
+
+    let roundings = [Rn, Rz, Rm, Rp];
+    let mut variants = Vec::with_capacity(64);
+    for operation in [Mul, Div, Fma] {
+        for rounding in roundings {
+            variants.push((F64, operation, rounding, Preserve, None));
+        }
+    }
+    for operation in [Mul, Div] {
+        for rounding in roundings {
+            variants.push((F32, operation, rounding, Preserve, None));
+            variants.push((F32, operation, rounding, Ftz, None));
+        }
+    }
+    for rounding in roundings {
+        variants.push((F32, Fma, rounding, Preserve, None));
+        variants.push((F32, Fma, rounding, Ftz, None));
+        variants.push((F32, Fma, rounding, Preserve, Sat));
+        variants.push((F32, Fma, rounding, Ftz, Sat));
+    }
+    for rounding in roundings {
+        variants.push((F64, Add, rounding, Preserve, None));
+    }
+    for rounding in roundings {
+        variants.push((F32, Add, rounding, Preserve, None));
+        variants.push((F32, Add, rounding, Ftz, None));
+        variants.push((F32, Add, rounding, Preserve, Sat));
+        variants.push((F32, Add, rounding, Ftz, Sat));
+    }
+    variants
+}
+
+pub(in crate::resolve) fn scalar_arithmetic_format_name(
+    format: ScalarArithmeticFormat,
+) -> &'static str {
+    match format {
+        ScalarArithmeticFormat::F32 => "f32",
+        ScalarArithmeticFormat::F64 => "f64",
+    }
+}
+
+pub(in crate::resolve) fn scalar_arithmetic_operation_name(
+    operation: ScalarArithmeticOperation,
+) -> &'static str {
+    match operation {
+        ScalarArithmeticOperation::Mul => "mul",
+        ScalarArithmeticOperation::Div => "div",
+        ScalarArithmeticOperation::Fma => "fma",
+        ScalarArithmeticOperation::Add => "add",
+    }
+}
+
+pub(in crate::resolve) fn scalar_arithmetic_rounding_name(
+    rounding: ScalarArithmeticRounding,
+) -> &'static str {
+    match rounding {
+        ScalarArithmeticRounding::Rn => "rn",
+        ScalarArithmeticRounding::Rz => "rz",
+        ScalarArithmeticRounding::Rm => "rm",
+        ScalarArithmeticRounding::Rp => "rp",
+    }
+}
+
+pub(in crate::resolve) fn scalar_arithmetic_recipe(
+    variant: ScalarArithmeticVariant,
+) -> Option<ScalarArithmeticRecipe> {
+    if !canonical_scalar_arithmetic_variants().contains(&variant) {
+        return None;
+    }
+    let (format, operation, rounding, subnormal, saturation) = variant;
+    let operation_name = scalar_arithmetic_operation_name(operation);
+    let rounding_name = scalar_arithmetic_rounding_name(rounding);
+    let format_name = scalar_arithmetic_format_name(format);
+    let source_format = match format {
+        ScalarArithmeticFormat::F32 => "f",
+        ScalarArithmeticFormat::F64 => "d",
+    };
+
+    let mut modifier_names = vec![rounding_name];
+    if subnormal == ScalarArithmeticSubnormal::Ftz {
+        modifier_names.push("ftz");
+    }
+    if saturation == ScalarArithmeticSaturation::Sat {
+        modifier_names.push("sat");
+    }
+
+    let modifier_id = modifier_names.join("_");
+    let modifier_symbol = modifier_names.join(".");
+    let id = format!("{operation_name}_{modifier_id}_{format_name}");
+    let source_record = format!("int_nvvm_{operation_name}_{modifier_id}_{source_format}");
+    let llvm_symbol = format!("llvm.nvvm.{operation_name}.{modifier_symbol}.{source_format}");
+    let mut ptx_modifier_names = modifier_names.clone();
+    if operation == ScalarArithmeticOperation::Add
+        && subnormal == ScalarArithmeticSubnormal::Ftz
+        && saturation == ScalarArithmeticSaturation::Sat
+    {
+        ptx_modifier_names.swap(1, 2);
+    }
+    let ptx_modifiers = ptx_modifier_names
+        .iter()
+        .copied()
+        .chain(std::iter::once(format_name))
+        .map(str::to_owned)
+        .collect::<Vec<_>>();
+    let selection_record = match operation {
+        ScalarArithmeticOperation::Fma => {
+            format!("INT_NVVM_FMA_{modifier_id}_{format_name}")
+        }
+        ScalarArithmeticOperation::Mul | ScalarArithmeticOperation::Div => format!(
+            "INT_NVVM_{}_{}_{}",
+            operation_name.to_ascii_uppercase(),
+            modifier_id.to_ascii_uppercase(),
+            source_format.to_ascii_uppercase()
+        ),
+        ScalarArithmeticOperation::Add => {
+            let selection_modifier = ptx_modifier_names.join("_").to_ascii_uppercase();
+            format!(
+                "INT_NVVM_ADD_{selection_modifier}_{}",
+                source_format.to_ascii_uppercase()
+            )
+        }
+    };
+    let argument_count = if operation == ScalarArithmeticOperation::Fma {
+        3
+    } else {
+        2
+    };
+    let operands = (0..argument_count)
+        .map(|argument| format!("$src{argument}"))
+        .collect::<Vec<_>>()
+        .join(", ");
+    let ptx_modifier_symbol = ptx_modifier_names.join(".");
+    let selection_asm =
+        format!("{operation_name}.{ptx_modifier_symbol}.{format_name} \t$dst, {operands};");
+    let properties = match (operation, format) {
+        (ScalarArithmeticOperation::Mul | ScalarArithmeticOperation::Add, _) => {
+            vec!["Commutative", "IntrNoMem", "IntrSpeculatable"]
+        }
+        (ScalarArithmeticOperation::Div, _) => vec!["IntrNoMem"],
+        (ScalarArithmeticOperation::Fma, ScalarArithmeticFormat::F32) => {
+            vec!["IntrNoMem", "IntrSpeculatable"]
+        }
+        (ScalarArithmeticOperation::Fma, ScalarArithmeticFormat::F64) => {
+            vec!["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"]
+        }
+    };
+    let (ptx_isa_section, ptx_isa_url) = match operation {
+        ScalarArithmeticOperation::Mul => (
+            "9.7.3.5 Floating Point Instructions: mul",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-mul",
+        ),
+        ScalarArithmeticOperation::Fma => (
+            "9.7.3.6 Floating Point Instructions: fma",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-fma",
+        ),
+        ScalarArithmeticOperation::Div => (
+            "9.7.3.8 Floating Point Instructions: div",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-div",
+        ),
+        ScalarArithmeticOperation::Add => (
+            "9.7.3.3 Floating Point Instructions: add",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-add",
+        ),
+    };
+
+    Some(ScalarArithmeticRecipe {
+        id,
+        operation_key: format!(
+            "scalar.arithmetic.{operation_name}.{modifier_symbol}.{format_name}"
+        ),
+        source_record,
+        llvm_symbol,
+        selection_record,
+        selection_asm,
+        rust_type: format_name,
+        argument_count,
+        properties,
+        ptx_modifiers,
+        ptx_isa_section,
+        ptx_isa_url,
+    })
+}
+
+pub(in crate::resolve) fn expand_scalar_arithmetic_admission(
+    admission: &ScalarArithmeticAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "scalar-arithmetic runtime may be marked executed only with GPU evidence"
+    );
+    let expected = canonical_scalar_arithmetic_variants();
+    let actual = admission
+        .variants
+        .iter()
+        .map(|variant| {
+            (
+                variant.format,
+                variant.operation,
+                variant.rounding,
+                variant.subnormal,
+                variant.saturation,
+            )
+        })
+        .collect::<Vec<_>>();
+    ensure!(
+        actual == expected,
+        "compact scalar-arithmetic admission must list the canonical 64 variants"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            validate_abi_id(&variant.abi_id)?;
+            let identity = (
+                variant.format,
+                variant.operation,
+                variant.rounding,
+                variant.subnormal,
+                variant.saturation,
+            );
+            let recipe = scalar_arithmetic_recipe(identity)
+                .context("scalar arithmetic is outside the closed recipe set")?;
+            scalar_arithmetic_overlay_record(recipe, admission, identity, &variant.abi_id)
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn scalar_arithmetic_overlay_record(
+    recipe: ScalarArithmeticRecipe,
+    admission: &ScalarArithmeticAdmission,
+    variant: ScalarArithmeticVariant,
+    abi_id: &str,
+) -> Result<OverlayIntrinsic> {
+    let (format, operation, rounding, subnormal, saturation) = variant;
+    let rust_arguments = vec![recipe.rust_type.into(); recipe.argument_count];
+    let ptx_operands = vec![OperandPattern::Register; recipe.argument_count + 1];
+    let summary = format!(
+        "Computes scalar {} with explicit {} rounding.",
+        scalar_arithmetic_operation_name(operation),
+        scalar_arithmetic_rounding_name(rounding)
+    );
+    Ok(OverlayIntrinsic {
+        id: recipe.id.clone(),
+        abi_id: abi_id.into(),
+        operation_key: recipe.operation_key,
+        family: "scalar_arithmetic".into(),
+        source: None,
+        source_record: Some(recipe.source_record),
+        rust_module: "float".into(),
+        rust_name: recipe.id.clone(),
+        rust_arguments: rust_arguments.clone(),
+        rust_result: recipe.rust_type.into(),
+        safe: true,
+        must_use: true,
+        safe_allowlist_reason: Some("Scalar arithmetic has no caller obligations.".into()),
+        public_rust_path: format!("cuda_intrinsics::float::{}", recipe.id),
+        compatibility_rust_paths: vec![format!("cuda_device::float::{}", recipe.id)],
+        dialect_op_type: "ScalarArithmeticOp".into(),
+        dialect_op_name: "nvvm.scalar_arithmetic".into(),
+        dialect_operands: rust_arguments.clone(),
+        dialect_results: vec![recipe.rust_type.into()],
+        llvm_symbol: Some(recipe.llvm_symbol),
+        resolved_llvm_symbol: None,
+        llvm_arguments: rust_arguments,
+        llvm_results: vec![recipe.rust_type.into()],
+        pure: operation != ScalarArithmeticOperation::Div,
+        memory: "none".into(),
+        convergent: false,
+        execution_scope: "thread".into(),
+        minimum_ptx: "7.0".into(),
+        minimum_sm: Some("sm_80".into()),
+        ptx_result: recipe.rust_type.into(),
+        targets: "all".into(),
+        ptx_isa_version: "9.3".into(),
+        ptx_isa_section: recipe.ptx_isa_section.into(),
+        ptx_isa_url: recipe.ptx_isa_url.into(),
+        lowering: "generated_scalar_arithmetic".into(),
+        backend_lowerings: [
+            (
+                IntrinsicBackend::LlvmNvptx,
+                &admission.llvm_evidence_profile,
+            ),
+            (
+                IntrinsicBackend::LibNvvm,
+                &admission.libnvvm_evidence_profile,
+            ),
+        ]
+        .into_iter()
+        .map(|(backend, evidence_profile)| OverlayBackendLowering {
+            backend,
+            mechanism: match backend {
+                IntrinsicBackend::LlvmNvptx if saturation == ScalarArithmeticSaturation::Sat => {
+                    // LLVM 21 has no typed intrinsic for these LLVM 22 forms.
+                    BackendLoweringMechanism::InlinePtx
+                }
+                IntrinsicBackend::LlvmNvptx => BackendLoweringMechanism::TypedNvvm,
+                IntrinsicBackend::LibNvvm => BackendLoweringMechanism::InlinePtx,
+            },
+            evidence_profile: evidence_profile.clone(),
+            targets: None,
+            minimum_ptx: Some("7.0".into()),
+            minimum_sm: Some("sm_80".into()),
+        })
+        .collect(),
+        packed_atomic: None,
+        redux: None,
+        vote: None,
+        active_mask: None,
+        warp_match: None,
+        warp_barrier: None,
+        warp_shuffle: None,
+        dot_product: None,
+        packed_alu: None,
+        integer_minmax: None,
+        packed_conversion: None,
+        scalar_conversion: None,
+        scalar_arithmetic: Some(ScalarArithmetic {
+            format,
+            operation,
+            rounding,
+            subnormal,
+            saturation,
+            runtime_validation: admission.runtime_validation,
+        }),
+        scalar_math: None,
+        extended_minmax: None,
+        cp_async_copy: None,
+        cp_async_control: None,
+        cp_async_mbarrier: None,
+        mbarrier_basic: None,
+        movmatrix: None,
+        mbarrier_extended: None,
+        register_mma: None,
+        sparse_mma: None,
+        prmt: None,
+        cluster_barrier: None,
+        wgmma_control: None,
+        special_register: None,
+        debug_control: None,
+        cluster_memory: None,
+        clc: None,
+        tma: None,
+        tcgen05: None,
+        ldmatrix_variant: None,
+        ldmatrix_safety: None,
+        ldmatrix_adapter: None,
+        selected_address_space: None,
+        expected_ptx: InstructionPattern {
+            mnemonic: scalar_arithmetic_operation_name(operation).into(),
+            modifiers: recipe.ptx_modifiers,
+            operands: ptx_operands,
+        },
+        summary,
+    })
+}
+
+pub(in crate::resolve) fn validate_scalar_arithmetic_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let arithmetic = policy
+        .scalar_arithmetic
+        .as_ref()
+        .with_context(|| format!("{} has no scalar-arithmetic contract", policy.id))?;
+    let variant = (
+        arithmetic.format,
+        arithmetic.operation,
+        arithmetic.rounding,
+        arithmetic.subnormal,
+        arithmetic.saturation,
+    );
+    let recipe = scalar_arithmetic_recipe(variant).with_context(|| {
+        format!(
+            "{} is outside the closed scalar-arithmetic recipe",
+            policy.id
+        )
+    })?;
+    ensure!(
+        arithmetic.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} scalar-arithmetic runtime may be executed only with GPU evidence",
+        policy.id
+    );
+    let signature = vec![recipe.rust_type.to_owned(); recipe.argument_count];
+    ensure!(
+        policy.id == recipe.id
+            && policy.operation_key == recipe.operation_key
+            && policy.source_record.as_deref() == Some(recipe.source_record.as_str())
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none()
+            && policy.llvm_arguments == signature
+            && policy.llvm_results == [recipe.rust_type],
+        "{} scalar-arithmetic identity or LLVM source changed",
+        policy.id
+    );
+    let expected_properties = recipe
+        .properties
+        .iter()
+        .map(|property| (*property).to_owned())
+        .collect::<Vec<_>>();
+    ensure!(
+        declaration.properties == expected_properties,
+        "{} imported scalar-arithmetic properties changed",
+        policy.id
+    );
+    let direct = declaration
+        .selections
+        .first()
+        .with_context(|| format!("{} has no imported scalar selection", policy.id))?;
+    ensure!(
+        direct.source_record == recipe.selection_record
+            && direct.asm == recipe.selection_asm
+            && direct.predicates.is_empty()
+            && direct.constraints.is_empty(),
+        "{} direct scalar-arithmetic selection changed",
+        policy.id
+    );
+    if arithmetic.operation == ScalarArithmeticOperation::Add {
+        let rounding = scalar_arithmetic_rounding_name(arithmetic.rounding);
+        let source_modifiers = [
+            Some(rounding),
+            (arithmetic.subnormal == ScalarArithmeticSubnormal::Ftz).then_some("ftz"),
+            (arithmetic.saturation == ScalarArithmeticSaturation::Sat).then_some("sat"),
+        ]
+        .into_iter()
+        .flatten()
+        .collect::<Vec<_>>()
+        .join("_");
+        let mut expected = Vec::new();
+        if arithmetic.format == ScalarArithmeticFormat::F32
+            && arithmetic.subnormal == ScalarArithmeticSubnormal::Preserve
+        {
+            let saturation = if arithmetic.saturation == ScalarArithmeticSaturation::Sat {
+                "_sat"
+            } else {
+                ""
+            };
+            for instruction in ["ADD", "SUB"] {
+                for input_format in ["bf16", "f16"] {
+                    expected.push((
+                        format!(
+                            "INT_NVVM_MIXED_{instruction}_{rounding}{saturation}_f32_{input_format}"
+                        ),
+                        format!(
+                            "{}.{rounding}{}.f32.{input_format} \t$dst, $a, $b;",
+                            instruction.to_ascii_lowercase(),
+                            if arithmetic.saturation == ScalarArithmeticSaturation::Sat {
+                                ".sat"
+                            } else {
+                                ""
+                            }
+                        ),
+                        vec![
+                            "Subtarget->getSmVersion() >= 100".to_owned(),
+                            "Subtarget->getPTXVersion() >= 86".to_owned(),
+                        ],
+                    ));
+                }
+            }
+        }
+        let source_format = match arithmetic.format {
+            ScalarArithmeticFormat::F32 => "F",
+            ScalarArithmeticFormat::F64 => "D",
+        };
+        expected.push((
+            format!("INT_NVVM_SUB_{source_modifiers}_{source_format}"),
+            format!("sub.{} \t$dst, $a, $b;", recipe.ptx_modifiers.join(".")),
+            Vec::new(),
+        ));
+        ensure!(
+            declaration.selections.len() == expected.len() + 1,
+            "{} must retain one direct add and the reviewed non-add alternatives",
+            policy.id
+        );
+        for (selection, (source_record, asm, predicates)) in
+            declaration.selections[1..].iter().zip(expected)
+        {
+            ensure!(
+                selection.source_record == source_record
+                    && selection.asm == asm
+                    && selection.predicates == predicates
+                    && selection.constraints.is_empty(),
+                "{} non-add scalar selection changed",
+                policy.id
+            );
+        }
+    } else if arithmetic.format == ScalarArithmeticFormat::F32
+        && arithmetic.operation == ScalarArithmeticOperation::Fma
+        && arithmetic.subnormal == ScalarArithmeticSubnormal::Preserve
+    {
+        ensure!(
+            declaration.selections.len() == 3,
+            "{} must retain one direct and two mixed-input selections",
+            policy.id
+        );
+        let rounding = scalar_arithmetic_rounding_name(arithmetic.rounding);
+        let saturation = if arithmetic.saturation == ScalarArithmeticSaturation::Sat {
+            "_sat"
+        } else {
+            ""
+        };
+        for (selection, input_format) in declaration.selections[1..].iter().zip(["bf16", "f16"]) {
+            ensure!(
+                selection.source_record
+                    == format!("INT_NVVM_MIXED_FMA_{rounding}{saturation}_f32_{input_format}")
+                    && selection.asm
+                        == format!(
+                            "fma.{rounding}{}.f32.{input_format} \t$dst, $a, $b, $c;",
+                            if arithmetic.saturation == ScalarArithmeticSaturation::Sat {
+                                ".sat"
+                            } else {
+                                ""
+                            }
+                        )
+                    && selection.predicates
+                        == [
+                            "Subtarget->getSmVersion() >= 100",
+                            "Subtarget->getPTXVersion() >= 86",
+                        ]
+                    && selection.constraints.is_empty(),
+                "{} mixed-input scalar-arithmetic selection changed",
+                policy.id
+            );
+        }
+    } else {
+        ensure!(
+            declaration.selections.len() == 1,
+            "{} gained an unreviewed scalar-arithmetic selection",
+            policy.id
+        );
+    }
+    let mut selected = Vec::new();
+    for selection in &declaration.selections {
+        if selection_matches_policy(policy, selection)? {
+            selected.push(selection);
+        }
+    }
+    ensure!(
+        selected.len() == 1 && selected[0].source_record == recipe.selection_record,
+        "{} must select only its direct scalar arithmetic instruction",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "float"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == signature
+            && policy.rust_result == recipe.rust_type
+            && policy.safe
+            && policy.must_use
+            && policy.compatibility_rust_paths == [format!("cuda_device::float::{}", recipe.id)]
+            && policy.dialect_op_type == "ScalarArithmeticOp"
+            && policy.dialect_op_name == "nvvm.scalar_arithmetic"
+            && policy.dialect_operands == signature
+            && policy.dialect_results == [recipe.rust_type]
+            && policy.lowering == "generated_scalar_arithmetic",
+        "{} changed its scalar-arithmetic API, carrier, or lowering",
+        policy.id
+    );
+    ensure!(
+        policy.pure == (arithmetic.operation != ScalarArithmeticOperation::Div)
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == "7.0"
+            && policy.minimum_sm.as_deref() == Some("sm_80")
+            && policy.ptx_result == recipe.rust_type
+            && policy.targets == "all"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.ptx_isa_section
+            && policy.ptx_isa_url == recipe.ptx_isa_url,
+        "{} scalar-arithmetic effects, provenance, or target floor changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx
+            == InstructionPattern {
+                mnemonic: scalar_arithmetic_operation_name(arithmetic.operation).into(),
+                modifiers: recipe.ptx_modifiers.clone(),
+                operands: vec![OperandPattern::Register; recipe.argument_count + 1],
+            },
+        "{} expected scalar-arithmetic PTX changed",
+        policy.id
+    );
+    let llvm_mechanism = if arithmetic.saturation == ScalarArithmeticSaturation::Sat {
+        BackendLoweringMechanism::InlinePtx
+    } else {
+        BackendLoweringMechanism::TypedNvvm
+    };
+    let expected_backends = [
+        (IntrinsicBackend::LlvmNvptx, llvm_mechanism),
+        (
+            IntrinsicBackend::LibNvvm,
+            BackendLoweringMechanism::InlinePtx,
+        ),
+    ];
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && expected_backends.into_iter().all(|(backend, mechanism)| {
+                policy.backend_lowerings.iter().any(|lowering| {
+                    lowering.backend == backend
+                        && lowering.mechanism == mechanism
+                        && lowering.minimum_ptx.as_deref() == Some("7.0")
+                        && lowering.minimum_sm.as_deref() == Some("sm_80")
+                        && !lowering.evidence_profile.trim().is_empty()
+                })
+            }),
+        "{} has the wrong reviewed scalar-arithmetic backend routes",
+        policy.id
+    );
+    validate_selected_target_predicates(policy, direct)?;
+    ensure_no_other_family_contract(policy, "scalar arithmetic")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/scalar_conversion.rs b/crates/cuda-intrinsics-gen/src/resolve/families/scalar_conversion.rs
new file mode 100644
index 0000000000..b683d5147e
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/scalar_conversion.rs
@@ -0,0 +1,490 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, OverlayBackendLowering,
+    OverlayIntrinsic, RuntimeValidation, ScalarConversion, ScalarConversionAdapter,
+    ScalarConversionAdmission, ScalarConversionDestinationFormat,
+    ScalarConversionResultRepresentation, ScalarConversionRounding, ScalarConversionSaturation,
+    ScalarConversionSourceFormat,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+
+use crate::resolve::guards::*;
+use crate::resolve::targets::*;
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct ScalarConversionRecipe {
+    id: &'static str,
+    abi_id: &'static str,
+    operation_key: &'static str,
+    source_record: &'static str,
+    llvm_symbol: &'static str,
+    rust_name: &'static str,
+    selection_record: &'static str,
+    selection_asm: &'static str,
+    minimum_ptx: &'static str,
+    minimum_sm: &'static str,
+    ptx_modifiers: &'static [&'static str],
+}
+
+pub(in crate::resolve) fn scalar_conversion_recipe(
+    rounding: ScalarConversionRounding,
+    saturation: ScalarConversionSaturation,
+) -> Option<ScalarConversionRecipe> {
+    use ScalarConversionRounding::{NearestAway, NearestEven, TowardZero};
+    use ScalarConversionSaturation::{None, Relu, ReluSatfinite, Satfinite};
+
+    Some(match (rounding, saturation) {
+        (NearestAway, None) => ScalarConversionRecipe {
+            id: "cvt_rna_tf32_f32",
+            abi_id: "i0368",
+            operation_key: "convert.f32.tf32.rna",
+            source_record: "int_nvvm_f2tf32_rna",
+            llvm_symbol: "llvm.nvvm.f2tf32.rna",
+            rust_name: "cvt_rna_tf32_f32",
+            selection_record: "CVT_to_tf32_rna",
+            selection_asm: "cvt.rna.tf32.f32 \t$dst, $src;",
+            minimum_ptx: "7.0",
+            minimum_sm: "sm_80",
+            ptx_modifiers: &["rna", "tf32", "f32"],
+        },
+        (NearestAway, Satfinite) => ScalarConversionRecipe {
+            id: "cvt_rna_satfinite_tf32_f32",
+            abi_id: "i0369",
+            operation_key: "convert.f32.tf32.rna.satfinite",
+            source_record: "int_nvvm_f2tf32_rna_satfinite",
+            llvm_symbol: "llvm.nvvm.f2tf32.rna.satfinite",
+            rust_name: "cvt_rna_satfinite_tf32_f32",
+            selection_record: "CVT_to_tf32_rna_satf",
+            selection_asm: "cvt.rna.satfinite.tf32.f32 \t$dst, $src;",
+            minimum_ptx: "8.1",
+            minimum_sm: "sm_80",
+            ptx_modifiers: &["rna", "satfinite", "tf32", "f32"],
+        },
+        (NearestEven, None) => ScalarConversionRecipe {
+            id: "cvt_rn_tf32_f32",
+            abi_id: "i0370",
+            operation_key: "convert.f32.tf32.rn",
+            source_record: "int_nvvm_f2tf32_rn",
+            llvm_symbol: "llvm.nvvm.f2tf32.rn",
+            rust_name: "cvt_rn_tf32_f32",
+            selection_record: "CVT_to_tf32_rn",
+            selection_asm: "cvt.rn.tf32.f32 \t$dst, $src;",
+            minimum_ptx: "7.8",
+            minimum_sm: "sm_90",
+            ptx_modifiers: &["rn", "tf32", "f32"],
+        },
+        (NearestEven, Relu) => ScalarConversionRecipe {
+            id: "cvt_rn_relu_tf32_f32",
+            abi_id: "i0371",
+            operation_key: "convert.f32.tf32.rn.relu",
+            source_record: "int_nvvm_f2tf32_rn_relu",
+            llvm_symbol: "llvm.nvvm.f2tf32.rn.relu",
+            rust_name: "cvt_rn_relu_tf32_f32",
+            selection_record: "CVT_to_tf32_rn_relu",
+            selection_asm: "cvt.rn.relu.tf32.f32 \t$dst, $src;",
+            minimum_ptx: "7.8",
+            minimum_sm: "sm_90",
+            ptx_modifiers: &["rn", "relu", "tf32", "f32"],
+        },
+        (NearestEven, Satfinite) => ScalarConversionRecipe {
+            id: "cvt_rn_satfinite_tf32_f32",
+            abi_id: "i0372",
+            operation_key: "convert.f32.tf32.rn.satfinite",
+            source_record: "int_nvvm_f2tf32_rn_satfinite",
+            llvm_symbol: "llvm.nvvm.f2tf32.rn.satfinite",
+            rust_name: "cvt_rn_satfinite_tf32_f32",
+            selection_record: "CVT_to_tf32_rn_satf",
+            selection_asm: "cvt.rn.satfinite.tf32.f32 \t$dst, $src;",
+            minimum_ptx: "8.6",
+            minimum_sm: "sm_100",
+            ptx_modifiers: &["rn", "satfinite", "tf32", "f32"],
+        },
+        (NearestEven, ReluSatfinite) => ScalarConversionRecipe {
+            id: "cvt_rn_relu_satfinite_tf32_f32",
+            abi_id: "i0373",
+            operation_key: "convert.f32.tf32.rn.relu.satfinite",
+            source_record: "int_nvvm_f2tf32_rn_relu_satfinite",
+            llvm_symbol: "llvm.nvvm.f2tf32.rn.relu.satfinite",
+            rust_name: "cvt_rn_relu_satfinite_tf32_f32",
+            selection_record: "CVT_to_tf32_rn_relu_satf",
+            selection_asm: "cvt.rn.relu.satfinite.tf32.f32 \t$dst, $src;",
+            minimum_ptx: "8.6",
+            minimum_sm: "sm_100",
+            ptx_modifiers: &["rn", "relu", "satfinite", "tf32", "f32"],
+        },
+        (TowardZero, None) => ScalarConversionRecipe {
+            id: "cvt_rz_tf32_f32",
+            abi_id: "i0374",
+            operation_key: "convert.f32.tf32.rz",
+            source_record: "int_nvvm_f2tf32_rz",
+            llvm_symbol: "llvm.nvvm.f2tf32.rz",
+            rust_name: "cvt_rz_tf32_f32",
+            selection_record: "CVT_to_tf32_rz",
+            selection_asm: "cvt.rz.tf32.f32 \t$dst, $src;",
+            minimum_ptx: "7.8",
+            minimum_sm: "sm_90",
+            ptx_modifiers: &["rz", "tf32", "f32"],
+        },
+        (TowardZero, Relu) => ScalarConversionRecipe {
+            id: "cvt_rz_relu_tf32_f32",
+            abi_id: "i0375",
+            operation_key: "convert.f32.tf32.rz.relu",
+            source_record: "int_nvvm_f2tf32_rz_relu",
+            llvm_symbol: "llvm.nvvm.f2tf32.rz.relu",
+            rust_name: "cvt_rz_relu_tf32_f32",
+            selection_record: "CVT_to_tf32_rz_relu",
+            selection_asm: "cvt.rz.relu.tf32.f32 \t$dst, $src;",
+            minimum_ptx: "7.8",
+            minimum_sm: "sm_90",
+            ptx_modifiers: &["rz", "relu", "tf32", "f32"],
+        },
+        (TowardZero, Satfinite) => ScalarConversionRecipe {
+            id: "cvt_rz_satfinite_tf32_f32",
+            abi_id: "i0376",
+            operation_key: "convert.f32.tf32.rz.satfinite",
+            source_record: "int_nvvm_f2tf32_rz_satfinite",
+            llvm_symbol: "llvm.nvvm.f2tf32.rz.satfinite",
+            rust_name: "cvt_rz_satfinite_tf32_f32",
+            selection_record: "CVT_to_tf32_rz_satf",
+            selection_asm: "cvt.rz.satfinite.tf32.f32 \t$dst, $src;",
+            minimum_ptx: "8.6",
+            minimum_sm: "sm_100",
+            ptx_modifiers: &["rz", "satfinite", "tf32", "f32"],
+        },
+        (TowardZero, ReluSatfinite) => ScalarConversionRecipe {
+            id: "cvt_rz_relu_satfinite_tf32_f32",
+            abi_id: "i0377",
+            operation_key: "convert.f32.tf32.rz.relu.satfinite",
+            source_record: "int_nvvm_f2tf32_rz_relu_satfinite",
+            llvm_symbol: "llvm.nvvm.f2tf32.rz.relu.satfinite",
+            rust_name: "cvt_rz_relu_satfinite_tf32_f32",
+            selection_record: "CVT_to_tf32_rz_relu_satf",
+            selection_asm: "cvt.rz.relu.satfinite.tf32.f32 \t$dst, $src;",
+            minimum_ptx: "8.6",
+            minimum_sm: "sm_100",
+            ptx_modifiers: &["rz", "relu", "satfinite", "tf32", "f32"],
+        },
+        _ => return Option::None,
+    })
+}
+
+pub(in crate::resolve) fn expand_scalar_conversion_admission(
+    admission: &ScalarConversionAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "scalar-conversion runtime may be marked executed only with GPU evidence"
+    );
+    let expected = [
+        (
+            ScalarConversionRounding::NearestAway,
+            ScalarConversionSaturation::None,
+        ),
+        (
+            ScalarConversionRounding::NearestAway,
+            ScalarConversionSaturation::Satfinite,
+        ),
+        (
+            ScalarConversionRounding::NearestEven,
+            ScalarConversionSaturation::None,
+        ),
+        (
+            ScalarConversionRounding::NearestEven,
+            ScalarConversionSaturation::Relu,
+        ),
+        (
+            ScalarConversionRounding::NearestEven,
+            ScalarConversionSaturation::Satfinite,
+        ),
+        (
+            ScalarConversionRounding::NearestEven,
+            ScalarConversionSaturation::ReluSatfinite,
+        ),
+        (
+            ScalarConversionRounding::TowardZero,
+            ScalarConversionSaturation::None,
+        ),
+        (
+            ScalarConversionRounding::TowardZero,
+            ScalarConversionSaturation::Relu,
+        ),
+        (
+            ScalarConversionRounding::TowardZero,
+            ScalarConversionSaturation::Satfinite,
+        ),
+        (
+            ScalarConversionRounding::TowardZero,
+            ScalarConversionSaturation::ReluSatfinite,
+        ),
+    ];
+    let actual = admission
+        .variants
+        .iter()
+        .map(|variant| (variant.rounding, variant.saturation))
+        .collect::<Vec<_>>();
+    ensure!(
+        actual == expected,
+        "compact scalar-conversion admission must list the canonical ten variants"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = scalar_conversion_recipe(variant.rounding, variant.saturation)
+                .context("scalar conversion is outside the closed recipe set")?;
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must reserve ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            scalar_conversion_overlay_record(
+                recipe,
+                admission,
+                variant.rounding,
+                variant.saturation,
+            )
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn scalar_conversion_overlay_record(
+    recipe: ScalarConversionRecipe,
+    admission: &ScalarConversionAdmission,
+    rounding: ScalarConversionRounding,
+    saturation: ScalarConversionSaturation,
+) -> Result<OverlayIntrinsic> {
+    Ok(OverlayIntrinsic {
+        id: recipe.id.into(),
+        abi_id: recipe.abi_id.into(),
+        operation_key: recipe.operation_key.into(),
+        family: "scalar_conversion".into(),
+        source: None,
+        source_record: Some(recipe.source_record.into()),
+        rust_module: "convert".into(),
+        rust_name: recipe.rust_name.into(),
+        rust_arguments: vec!["f32".into()],
+        rust_result: "u32".into(),
+        safe: true,
+        must_use: true,
+        safe_allowlist_reason: Some("This conversion has no caller obligations.".into()),
+        public_rust_path: format!("cuda_intrinsics::convert::{}", recipe.rust_name),
+        compatibility_rust_paths: vec![format!(
+            "cuda_device::convert::{}",
+            recipe.rust_name
+        )],
+        dialect_op_type: "ScalarConversionOp".into(),
+        dialect_op_name: "nvvm.scalar_conversion".into(),
+        dialect_operands: vec!["f32".into()],
+        dialect_results: vec!["i32".into()],
+        llvm_symbol: Some(recipe.llvm_symbol.into()),
+        resolved_llvm_symbol: None,
+        llvm_arguments: vec!["f32".into()],
+        llvm_results: vec!["i32".into()],
+        pure: true,
+        memory: "none".into(),
+        convergent: false,
+        execution_scope: "thread".into(),
+        minimum_ptx: recipe.minimum_ptx.into(),
+        minimum_sm: Some(recipe.minimum_sm.into()),
+        ptx_result: "u32".into(),
+        targets: "all".into(),
+        ptx_isa_version: "9.3".into(),
+        ptx_isa_section: "9.7.9.22 Data Movement and Conversion Instructions: cvt".into(),
+        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt".into(),
+        lowering: "generated_scalar_conversion".into(),
+        backend_lowerings: [
+            (IntrinsicBackend::LlvmNvptx, &admission.llvm_evidence_profile),
+            (IntrinsicBackend::LibNvvm, &admission.libnvvm_evidence_profile),
+        ]
+        .into_iter()
+        .map(|(backend, evidence_profile)| OverlayBackendLowering {
+            backend,
+            mechanism: match backend {
+                IntrinsicBackend::LlvmNvptx => BackendLoweringMechanism::TypedNvvm,
+                IntrinsicBackend::LibNvvm => BackendLoweringMechanism::InlinePtx,
+            },
+            evidence_profile: evidence_profile.clone(),
+            targets: None,
+            minimum_ptx: Some(recipe.minimum_ptx.into()),
+            minimum_sm: Some(recipe.minimum_sm.into()),
+        })
+        .collect(),
+        packed_atomic: None,
+        redux: None,
+        vote: None,
+        active_mask: None,
+        warp_match: None,
+        warp_barrier: None,
+        warp_shuffle: None,
+        dot_product: None,
+        packed_alu: None,
+        integer_minmax: None,
+        packed_conversion: None,
+        scalar_conversion: Some(ScalarConversion {
+            source_format: ScalarConversionSourceFormat::F32,
+            destination_format: ScalarConversionDestinationFormat::Tf32,
+            rounding,
+            saturation,
+            result_representation: ScalarConversionResultRepresentation::RawU32Bits,
+            adapter: ScalarConversionAdapter::DirectF32ToRawU32Bits,
+            runtime_validation: admission.runtime_validation,
+        }),
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cp_async_copy: None,
+        cp_async_control: None,
+        cp_async_mbarrier: None,
+        mbarrier_basic: None,
+        movmatrix: None,
+        mbarrier_extended: None,
+        register_mma: None,
+        sparse_mma: None,
+        prmt: None,
+        cluster_barrier: None,
+        wgmma_control: None,
+        special_register: None,
+        debug_control: None,
+        cluster_memory: None,
+        clc: None,
+        tma: None,
+        tcgen05: None,
+        ldmatrix_variant: None,
+        ldmatrix_safety: None,
+        ldmatrix_adapter: None,
+        selected_address_space: None,
+        expected_ptx: InstructionPattern {
+            mnemonic: "cvt".into(),
+            modifiers: recipe.ptx_modifiers.iter().map(|value| (*value).into()).collect(),
+            operands: vec![OperandPattern::Register, OperandPattern::Register],
+        },
+        summary: format!(
+            "Converts one f32 value with {} and returns raw TF32 bits.",
+            recipe.ptx_modifiers[0]
+        ),
+    })
+}
+
+pub(in crate::resolve) fn validate_scalar_conversion_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let conversion = policy
+        .scalar_conversion
+        .as_ref()
+        .with_context(|| format!("{} has no scalar-conversion contract", policy.id))?;
+    let recipe = scalar_conversion_recipe(conversion.rounding, conversion.saturation)
+        .with_context(|| {
+            format!(
+                "{} is outside the closed scalar-conversion recipe",
+                policy.id
+            )
+        })?;
+    ensure!(
+        conversion.source_format == ScalarConversionSourceFormat::F32
+            && conversion.destination_format == ScalarConversionDestinationFormat::Tf32
+            && conversion.result_representation == ScalarConversionResultRepresentation::RawU32Bits
+            && conversion.adapter == ScalarConversionAdapter::DirectF32ToRawU32Bits
+            && conversion.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} changed its scalar-conversion representation or adapter",
+        policy.id
+    );
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none()
+            && policy.llvm_arguments == ["f32"]
+            && policy.llvm_results == ["i32"],
+        "{} scalar-conversion identity or LLVM source changed",
+        policy.id
+    );
+    ensure!(
+        declaration.properties == ["IntrNoMem", "IntrSpeculatable"]
+            && declaration.selections.len() == 1
+            && declaration.selections[0].source_record == recipe.selection_record
+            && declaration.selections[0].asm == recipe.selection_asm
+            && declaration.selections[0].constraints.is_empty(),
+        "{} imported scalar-conversion declaration or selection changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "convert"
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == ["f32"]
+            && policy.rust_result == "u32"
+            && policy.safe
+            && policy.must_use
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::convert::{}", recipe.rust_name)]
+            && policy.dialect_op_type == "ScalarConversionOp"
+            && policy.dialect_op_name == "nvvm.scalar_conversion"
+            && policy.dialect_operands == ["f32"]
+            && policy.dialect_results == ["i32"]
+            && policy.lowering == "generated_scalar_conversion",
+        "{} changed its scalar-conversion API, carrier, or lowering",
+        policy.id
+    );
+    ensure!(
+        policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
+            && policy.ptx_result == "u32"
+            && policy.targets == "all",
+        "{} scalar-conversion effects or target floor changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx
+            == InstructionPattern {
+                mnemonic: "cvt".into(),
+                modifiers: recipe
+                    .ptx_modifiers
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                operands: vec![OperandPattern::Register, OperandPattern::Register],
+            },
+        "{} expected PTX changed",
+        policy.id
+    );
+    let expected_backends = [
+        (
+            IntrinsicBackend::LlvmNvptx,
+            BackendLoweringMechanism::TypedNvvm,
+        ),
+        (
+            IntrinsicBackend::LibNvvm,
+            BackendLoweringMechanism::InlinePtx,
+        ),
+    ];
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && expected_backends.into_iter().all(|(backend, mechanism)| {
+                policy.backend_lowerings.iter().any(|lowering| {
+                    lowering.backend == backend
+                        && lowering.mechanism == mechanism
+                        && lowering.minimum_ptx.as_deref() == Some(recipe.minimum_ptx)
+                        && lowering.minimum_sm.as_deref() == Some(recipe.minimum_sm)
+                        && !lowering.evidence_profile.trim().is_empty()
+                })
+            }),
+        "{} must define the typed LLVM and inline-PTX libNVVM routes",
+        policy.id
+    );
+    validate_selected_target_predicates(policy, &declaration.selections[0])?;
+    ensure_no_other_family_contract(policy, "scalar conversion")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/scalar_math.rs b/crates/cuda-intrinsics-gen/src/resolve/families/scalar_math.rs
new file mode 100644
index 0000000000..54b0c0f3cb
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/scalar_math.rs
@@ -0,0 +1,692 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, IntrinsicSource,
+    OverlayBackendLowering, OverlayIntrinsic, RuntimeValidation, ScalarMath, ScalarMathAdmission,
+    ScalarMathFormat, ScalarMathOperation, ScalarMathPrecision, ScalarMathSubnormal,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+
+use crate::resolve::abi_ledger::*;
+use crate::resolve::guards::*;
+use crate::resolve::targets::*;
+
+pub(in crate::resolve) type ScalarMathVariant = (
+    ScalarMathFormat,
+    ScalarMathOperation,
+    ScalarMathPrecision,
+    ScalarMathSubnormal,
+);
+
+#[derive(Clone, PartialEq, Eq)]
+pub(in crate::resolve) enum ScalarMathRecipeSource {
+    /// Bound to a monomorphic tblgen record in the pinned import.
+    Imported {
+        source_record: String,
+        llvm_symbol: String,
+    },
+    /// Bound to an overloaded (polymorphic) tblgen record: the import
+    /// carries `anonymous_14`/`anyfloat` signature tokens and the concrete
+    /// f32 instantiation is recorded as the resolved symbol. Only ex2 uses
+    /// this (LLVM 22 models it as `int_nvvm_ex2_approx{,_ftz}` without a
+    /// per-format record).
+    ImportedOverloaded {
+        source_record: String,
+        llvm_symbol: String,
+        resolved_llvm_symbol: String,
+    },
+    /// No record exists in the pinned tblgen import at all. Only tanh uses
+    /// this: llc selects `llvm.nvvm.tanh.approx.f32` via NVVMIntrinsic-class
+    /// matching, but the import exports no record for it, so the op is
+    /// admitted directly against the PTX instruction.
+    PtxNative { instruction: String },
+}
+
+pub(in crate::resolve) struct ScalarMathRecipe {
+    id: String,
+    operation_key: String,
+    source: ScalarMathRecipeSource,
+    rust_type: &'static str,
+    dialect_type: &'static str,
+    minimum_ptx: &'static str,
+    minimum_sm: &'static str,
+    properties: Vec<&'static str>,
+    ptx_modifiers: Vec<String>,
+    ptx_isa_section: &'static str,
+    ptx_isa_url: &'static str,
+    /// The generator's tblgen import found no DAG selection pattern for the
+    /// intrinsic, so the lowering routes it through inline PTX. Note this is
+    /// an import limitation, not an llc one: llc still selects these
+    /// intrinsics through NVVMIntrinsic-class pattern matching, which the
+    /// evidence import cannot see. Promoting them to typed calls once the
+    /// import understands those patterns would reopen them to LLVM
+    /// optimization.
+    force_inline_ptx: bool,
+}
+
+pub(in crate::resolve) fn scalar_math_format_name(format: ScalarMathFormat) -> &'static str {
+    match format {
+        ScalarMathFormat::F16 => "f16",
+        ScalarMathFormat::F32 => "f32",
+        ScalarMathFormat::F64 => "f64",
+    }
+}
+
+pub(in crate::resolve) fn scalar_math_operation_name(
+    operation: ScalarMathOperation,
+) -> &'static str {
+    match operation {
+        ScalarMathOperation::Sin => "sin",
+        ScalarMathOperation::Cos => "cos",
+        ScalarMathOperation::Ex2 => "ex2",
+        ScalarMathOperation::Lg2 => "lg2",
+        ScalarMathOperation::Rcp => "rcp",
+        ScalarMathOperation::Rsqrt => "rsqrt",
+        ScalarMathOperation::Sqrt => "sqrt",
+        ScalarMathOperation::Tanh => "tanh",
+    }
+}
+
+pub(in crate::resolve) fn scalar_math_precision_name(
+    precision: ScalarMathPrecision,
+) -> &'static str {
+    match precision {
+        ScalarMathPrecision::Approx => "approx",
+        ScalarMathPrecision::Rn => "rn",
+        ScalarMathPrecision::Rz => "rz",
+        ScalarMathPrecision::Rm => "rm",
+        ScalarMathPrecision::Rp => "rp",
+    }
+}
+
+pub(in crate::resolve) fn canonical_scalar_math_variants() -> Vec<ScalarMathVariant> {
+    use ScalarMathFormat::{F16, F32, F64};
+    use ScalarMathOperation::{Cos, Ex2, Lg2, Rcp, Rsqrt, Sin, Sqrt, Tanh};
+    use ScalarMathPrecision::{Approx, Rm, Rn, Rp, Rz};
+    use ScalarMathSubnormal::{Ftz, Preserve};
+
+    vec![
+        // sin: approx f32 only
+        (F32, Sin, Approx, Preserve),
+        (F32, Sin, Approx, Ftz),
+        // cos: approx f32 only
+        (F32, Cos, Approx, Preserve),
+        (F32, Cos, Approx, Ftz),
+        // lg2: approx f32 only (f64 approx produces invalid PTX)
+        (F32, Lg2, Approx, Preserve),
+        (F32, Lg2, Approx, Ftz),
+        // rcp: approx only with ftz, rounded for both formats
+        (F32, Rcp, Approx, Ftz),
+        (F32, Rcp, Rn, Preserve),
+        (F32, Rcp, Rn, Ftz),
+        (F32, Rcp, Rz, Preserve),
+        (F32, Rcp, Rz, Ftz),
+        (F32, Rcp, Rm, Preserve),
+        (F32, Rcp, Rm, Ftz),
+        (F32, Rcp, Rp, Preserve),
+        (F32, Rcp, Rp, Ftz),
+        (F64, Rcp, Approx, Ftz),
+        (F64, Rcp, Rn, Preserve),
+        (F64, Rcp, Rz, Preserve),
+        (F64, Rcp, Rm, Preserve),
+        (F64, Rcp, Rp, Preserve),
+        // rsqrt: approx only (PTX has no rounded rsqrt). The f64+ftz variant
+        // is valid PTX (`rsqrt.approx.ftz.f64` assembles for sm_80+, and LLVM
+        // selects `llvm.nvvm.rsqrt.approx.ftz.d` directly); it is deferred
+        // only because it has not been probed under the pinned evidence
+        // profile yet, not because the instruction is invalid.
+        (F32, Rsqrt, Approx, Preserve),
+        (F32, Rsqrt, Approx, Ftz),
+        (F64, Rsqrt, Approx, Preserve),
+        // sqrt: approx f32 only, rounded for both formats
+        (F32, Sqrt, Approx, Preserve),
+        (F32, Sqrt, Approx, Ftz),
+        (F32, Sqrt, Rn, Preserve),
+        (F32, Sqrt, Rn, Ftz),
+        (F32, Sqrt, Rz, Preserve),
+        (F32, Sqrt, Rz, Ftz),
+        (F32, Sqrt, Rm, Preserve),
+        (F32, Sqrt, Rm, Ftz),
+        (F32, Sqrt, Rp, Preserve),
+        (F32, Sqrt, Rp, Ftz),
+        (F64, Sqrt, Rn, Preserve),
+        (F64, Sqrt, Rz, Preserve),
+        (F64, Sqrt, Rm, Preserve),
+        (F64, Sqrt, Rp, Preserve),
+        // ex2: approx f32 only (PTX has no ex2.approx.f64). Appended after
+        // the original 37 so existing ABI ids stay stable.
+        (F32, Ex2, Approx, Preserve),
+        (F32, Ex2, Approx, Ftz),
+        // tanh: approx f32 only; the instruction has no ftz form (PTX ISA
+        // Table 29) and no rounded variants. Hardware floor is sm_75; the
+        // family contract gates it at the attested sm_80 evidence floor.
+        (F32, Tanh, Approx, Preserve),
+        // ex2.approx.f16 starts at PTX 7.0 / sm_75. LLVM 22 rejects the
+        // .ftz.f16 spelling; .ftz.bf16 is a separate PTX 7.8 / sm_90 variant.
+        (F16, Ex2, Approx, Preserve),
+    ]
+}
+
+pub(in crate::resolve) fn scalar_math_recipe(
+    variant: ScalarMathVariant,
+) -> Option<ScalarMathRecipe> {
+    if !canonical_scalar_math_variants().contains(&variant) {
+        return None;
+    }
+    let (format, operation, precision, subnormal) = variant;
+    let operation_name = scalar_math_operation_name(operation);
+    let precision_name = scalar_math_precision_name(precision);
+    let format_name = scalar_math_format_name(format);
+    let source_format = match format {
+        ScalarMathFormat::F16 => "f16",
+        ScalarMathFormat::F32 => "f",
+        ScalarMathFormat::F64 => "d",
+    };
+
+    let mut modifier_names = vec![precision_name];
+    if subnormal == ScalarMathSubnormal::Ftz {
+        modifier_names.push("ftz");
+    }
+
+    let modifier_id = modifier_names.join("_");
+    let modifier_symbol = modifier_names.join(".");
+    let id = format!("{operation_name}_{modifier_id}_{format_name}");
+    let source = match operation {
+        // LLVM 22 models ex2 as overloaded records without a per-format
+        // suffix (`int_nvvm_ex2_approx{,_ftz}` over anyfloat); bind those
+        // for declaration-level checks and record the concrete f32
+        // instantiation as the resolved symbol.
+        ScalarMathOperation::Ex2 => ScalarMathRecipeSource::ImportedOverloaded {
+            source_record: format!("int_nvvm_{operation_name}_{modifier_id}"),
+            llvm_symbol: format!("llvm.nvvm.{operation_name}.{modifier_symbol}"),
+            resolved_llvm_symbol: format!(
+                "llvm.nvvm.{operation_name}.{modifier_symbol}.{format_name}"
+            ),
+        },
+        // LLVM 22.1.2's tblgen export has no record for tanh at all, so the
+        // op is admitted directly against the PTX instruction.
+        ScalarMathOperation::Tanh => ScalarMathRecipeSource::PtxNative {
+            instruction: format!("{operation_name}.{modifier_symbol}.{format_name}"),
+        },
+        _ => ScalarMathRecipeSource::Imported {
+            source_record: format!("int_nvvm_{operation_name}_{modifier_id}_{source_format}"),
+            llvm_symbol: format!("llvm.nvvm.{operation_name}.{modifier_symbol}.{source_format}"),
+        },
+    };
+    let ptx_modifiers = modifier_names
+        .iter()
+        .copied()
+        .chain(std::iter::once(format_name))
+        .map(str::to_owned)
+        .collect::<Vec<_>>();
+
+    // Operations whose llvm.nvvm.* records carry no *imported* DAG selection
+    // pattern in the pinned evidence (sel=0). llc itself still selects them
+    // (via NVVMIntrinsic-class patterns the tblgen import cannot see), but
+    // the evidence-driven contract only admits typed calls backed by an
+    // imported selection, so these route through inline PTX for now.
+    let force_inline_ptx = matches!(
+        operation,
+        ScalarMathOperation::Sin
+            | ScalarMathOperation::Cos
+            | ScalarMathOperation::Ex2
+            | ScalarMathOperation::Lg2
+            | ScalarMathOperation::Rsqrt
+            | ScalarMathOperation::Tanh
+    );
+
+    let (ptx_isa_section, ptx_isa_url) = match (operation, format) {
+        (ScalarMathOperation::Ex2, ScalarMathFormat::F16) => (
+            "9.7.4.10 Half Precision Floating Point Instructions: ex2",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-ex2",
+        ),
+        (ScalarMathOperation::Sin, _) => (
+            "9.7.3.10 Floating Point Instructions: sin",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-sin",
+        ),
+        (ScalarMathOperation::Cos, _) => (
+            "9.7.3.11 Floating Point Instructions: cos",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-cos",
+        ),
+        (ScalarMathOperation::Lg2, _) => (
+            "9.7.3.12 Floating Point Instructions: lg2",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-lg2",
+        ),
+        (ScalarMathOperation::Rcp, _) => (
+            "9.7.3.7 Floating Point Instructions: rcp",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-rcp",
+        ),
+        (ScalarMathOperation::Rsqrt, _) => (
+            "9.7.3.14 Floating Point Instructions: rsqrt",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-rsqrt",
+        ),
+        (ScalarMathOperation::Sqrt, _) => (
+            "9.7.3.9 Floating Point Instructions: sqrt",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-sqrt",
+        ),
+        (ScalarMathOperation::Ex2, _) => (
+            "9.7.3.13 Floating Point Instructions: ex2",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-ex2",
+        ),
+        (ScalarMathOperation::Tanh, _) => (
+            "9.7.3.15 Floating Point Instructions: tanh",
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-tanh",
+        ),
+    };
+
+    let (rust_type, dialect_type, minimum_ptx, minimum_sm) = match format {
+        ScalarMathFormat::F16 => ("u16", "i16", "7.0", "sm_75"),
+        ScalarMathFormat::F32 => ("f32", "f32", "7.0", "sm_80"),
+        ScalarMathFormat::F64 => ("f64", "f64", "7.0", "sm_80"),
+    };
+    Some(ScalarMathRecipe {
+        id,
+        operation_key: format!("scalar.math.{operation_name}.{modifier_symbol}.{format_name}"),
+        source,
+        rust_type,
+        dialect_type,
+        minimum_ptx,
+        minimum_sm,
+        properties: vec!["IntrNoMem"],
+        ptx_modifiers,
+        ptx_isa_section,
+        ptx_isa_url,
+        force_inline_ptx,
+    })
+}
+
+pub(in crate::resolve) fn expand_scalar_math_admission(
+    admission: &ScalarMathAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "scalar-math runtime may be marked executed only with GPU evidence"
+    );
+    let expected = canonical_scalar_math_variants();
+    let actual = admission
+        .variants
+        .iter()
+        .map(|variant| {
+            (
+                variant.format,
+                variant.operation,
+                variant.precision,
+                variant.subnormal,
+            )
+        })
+        .collect::<Vec<_>>();
+    ensure!(
+        actual == expected,
+        "compact scalar-math admission must list the canonical 41 variants"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            validate_abi_id(&variant.abi_id)?;
+            let identity = (
+                variant.format,
+                variant.operation,
+                variant.precision,
+                variant.subnormal,
+            );
+            let recipe = scalar_math_recipe(identity)
+                .context("scalar math is outside the closed recipe set")?;
+            let libnvvm_evidence_profile = variant
+                .libnvvm_evidence_profile
+                .as_ref()
+                .unwrap_or(&admission.libnvvm_evidence_profile);
+            ensure!(
+                !libnvvm_evidence_profile.trim().is_empty(),
+                "scalar-math libNVVM evidence profile must not be empty"
+            );
+            scalar_math_overlay_record(
+                recipe,
+                admission,
+                identity,
+                &variant.abi_id,
+                libnvvm_evidence_profile,
+            )
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn scalar_math_overlay_record(
+    recipe: ScalarMathRecipe,
+    admission: &ScalarMathAdmission,
+    variant: ScalarMathVariant,
+    abi_id: &str,
+    libnvvm_evidence_profile: &str,
+) -> Result<OverlayIntrinsic> {
+    let (format, operation, precision, subnormal) = variant;
+    let ptx_operands = vec![OperandPattern::Register; 2]; // 1 result + 1 operand
+    let summary = format!(
+        "Computes unary {} with {} precision.",
+        scalar_math_operation_name(operation),
+        scalar_math_precision_name(precision),
+    );
+    let (source, source_record, llvm_symbol, resolved_llvm_symbol, llvm_arguments, llvm_results) =
+        match &recipe.source {
+            ScalarMathRecipeSource::Imported {
+                source_record,
+                llvm_symbol,
+            } => (
+                None,
+                Some(source_record.clone()),
+                Some(llvm_symbol.clone()),
+                None,
+                vec![recipe.rust_type.to_owned()],
+                vec![recipe.rust_type.to_owned()],
+            ),
+            // The polymorphic signature tokens mirror the imported
+            // overloaded record verbatim (anyfloat over anonymous_14), the
+            // same shape packed_alu uses for llvm.nvvm.fabs.
+            ScalarMathRecipeSource::ImportedOverloaded {
+                source_record,
+                llvm_symbol,
+                resolved_llvm_symbol,
+            } => (
+                None,
+                Some(source_record.clone()),
+                Some(llvm_symbol.clone()),
+                Some(resolved_llvm_symbol.clone()),
+                vec!["anonymous_14".to_owned()],
+                vec!["anyfloat".to_owned()],
+            ),
+            ScalarMathRecipeSource::PtxNative { instruction } => (
+                Some(IntrinsicSource::PtxNative {
+                    instruction: instruction.clone(),
+                }),
+                None,
+                None,
+                None,
+                Vec::new(),
+                Vec::new(),
+            ),
+        };
+    Ok(OverlayIntrinsic {
+        id: recipe.id.clone(),
+        abi_id: abi_id.into(),
+        operation_key: recipe.operation_key,
+        family: "scalar_math".into(),
+        source,
+        source_record,
+        rust_module: "float".into(),
+        rust_name: recipe.id.clone(),
+        rust_arguments: vec![recipe.rust_type.into()],
+        rust_result: recipe.rust_type.into(),
+        safe: true,
+        must_use: true,
+        safe_allowlist_reason: Some("Scalar math has no caller obligations.".into()),
+        public_rust_path: format!("cuda_intrinsics::float::{}", recipe.id),
+        compatibility_rust_paths: vec![format!("cuda_device::float::{}", recipe.id)],
+        dialect_op_type: "ScalarMathOp".into(),
+        dialect_op_name: "nvvm.scalar_math".into(),
+        dialect_operands: vec![recipe.dialect_type.into()],
+        dialect_results: vec![recipe.dialect_type.into()],
+        llvm_symbol,
+        resolved_llvm_symbol,
+        llvm_arguments,
+        llvm_results,
+        pure: true,
+        memory: "none".into(),
+        convergent: false,
+        execution_scope: "thread".into(),
+        minimum_ptx: recipe.minimum_ptx.into(),
+        minimum_sm: Some(recipe.minimum_sm.into()),
+        ptx_result: recipe.rust_type.into(),
+        targets: "all".into(),
+        ptx_isa_version: "9.3".into(),
+        ptx_isa_section: recipe.ptx_isa_section.into(),
+        ptx_isa_url: recipe.ptx_isa_url.into(),
+        lowering: "generated_scalar_math".into(),
+        backend_lowerings: [
+            (
+                IntrinsicBackend::LlvmNvptx,
+                admission.llvm_evidence_profile.as_str(),
+            ),
+            (IntrinsicBackend::LibNvvm, libnvvm_evidence_profile),
+        ]
+        .into_iter()
+        .map(
+            |(backend, evidence_profile): (IntrinsicBackend, &str)| OverlayBackendLowering {
+                backend,
+                mechanism: match backend {
+                    IntrinsicBackend::LlvmNvptx if recipe.force_inline_ptx => {
+                        BackendLoweringMechanism::InlinePtx
+                    }
+                    IntrinsicBackend::LlvmNvptx => BackendLoweringMechanism::TypedNvvm,
+                    IntrinsicBackend::LibNvvm => BackendLoweringMechanism::InlinePtx,
+                },
+                evidence_profile: evidence_profile.to_owned(),
+                targets: None,
+                minimum_ptx: Some(recipe.minimum_ptx.into()),
+                minimum_sm: Some(recipe.minimum_sm.into()),
+            },
+        )
+        .collect(),
+        packed_atomic: None,
+        redux: None,
+        vote: None,
+        active_mask: None,
+        warp_match: None,
+        warp_barrier: None,
+        warp_shuffle: None,
+        dot_product: None,
+        packed_alu: None,
+        integer_minmax: None,
+        packed_conversion: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: Some(ScalarMath {
+            format,
+            operation,
+            precision,
+            subnormal,
+            runtime_validation: admission.runtime_validation,
+        }),
+        extended_minmax: None,
+        cp_async_copy: None,
+        cp_async_control: None,
+        cp_async_mbarrier: None,
+        mbarrier_basic: None,
+        movmatrix: None,
+        mbarrier_extended: None,
+        register_mma: None,
+        sparse_mma: None,
+        prmt: None,
+        cluster_barrier: None,
+        wgmma_control: None,
+        special_register: None,
+        debug_control: None,
+        cluster_memory: None,
+        clc: None,
+        tma: None,
+        tcgen05: None,
+        ldmatrix_variant: None,
+        ldmatrix_safety: None,
+        ldmatrix_adapter: None,
+        selected_address_space: None,
+        expected_ptx: InstructionPattern {
+            mnemonic: scalar_math_operation_name(operation).into(),
+            modifiers: recipe.ptx_modifiers,
+            operands: ptx_operands,
+        },
+        summary,
+    })
+}
+
+pub(in crate::resolve) fn validate_scalar_math_policy(
+    policy: &OverlayIntrinsic,
+    declaration: Option<&ImportedIntrinsic>,
+) -> Result<()> {
+    let math = policy
+        .scalar_math
+        .as_ref()
+        .with_context(|| format!("{} has no scalar-math contract", policy.id))?;
+    let variant = (math.format, math.operation, math.precision, math.subnormal);
+    let recipe = scalar_math_recipe(variant)
+        .with_context(|| format!("{} is outside the closed scalar-math recipe", policy.id))?;
+    ensure!(
+        math.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} scalar-math runtime may be executed only with GPU evidence",
+        policy.id
+    );
+    let signature = vec![recipe.rust_type.to_owned()];
+    let source_matches = match &recipe.source {
+        ScalarMathRecipeSource::Imported {
+            source_record,
+            llvm_symbol,
+        } => {
+            policy.source.is_none()
+                && policy.source_record.as_deref() == Some(source_record.as_str())
+                && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
+                && policy.resolved_llvm_symbol.is_none()
+                && policy.llvm_arguments == signature
+                && policy.llvm_results == [recipe.rust_type]
+        }
+        ScalarMathRecipeSource::ImportedOverloaded {
+            source_record,
+            llvm_symbol,
+            resolved_llvm_symbol,
+        } => {
+            policy.source.is_none()
+                && policy.source_record.as_deref() == Some(source_record.as_str())
+                && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
+                && policy.resolved_llvm_symbol.as_deref() == Some(resolved_llvm_symbol.as_str())
+                && policy.llvm_arguments == ["anonymous_14"]
+                && policy.llvm_results == ["anyfloat"]
+        }
+        ScalarMathRecipeSource::PtxNative { instruction } => {
+            policy.source
+                == Some(IntrinsicSource::PtxNative {
+                    instruction: instruction.clone(),
+                })
+                && policy.source_record.is_none()
+                && policy.llvm_symbol.is_none()
+                && policy.resolved_llvm_symbol.is_none()
+                && policy.llvm_arguments.is_empty()
+                && policy.llvm_results.is_empty()
+        }
+    };
+    ensure!(
+        policy.id == recipe.id && policy.operation_key == recipe.operation_key && source_matches,
+        "{} scalar-math identity or LLVM source changed",
+        policy.id
+    );
+    ensure!(
+        declaration.is_none() == matches!(recipe.source, ScalarMathRecipeSource::PtxNative { .. }),
+        "{} scalar-math source kind and imported declaration disagree",
+        policy.id
+    );
+    if let Some(declaration) = declaration {
+        let expected_properties = recipe
+            .properties
+            .iter()
+            .map(|property| (*property).to_owned())
+            .collect::<Vec<_>>();
+        ensure!(
+            declaration.properties == expected_properties,
+            "{} imported scalar-math properties changed",
+            policy.id
+        );
+        ensure!(
+            declaration.selections.len() <= 1,
+            "{} gained an unreviewed scalar-math selection",
+            policy.id
+        );
+        if let Some(direct) = declaration.selections.first() {
+            ensure!(
+                direct.predicates.is_empty() && direct.constraints.is_empty(),
+                "{} direct scalar-math selection changed",
+                policy.id
+            );
+        }
+    }
+    ensure!(
+        policy.rust_module == "float"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == signature
+            && policy.rust_result == recipe.rust_type
+            && policy.safe
+            && policy.must_use
+            && policy.compatibility_rust_paths == [format!("cuda_device::float::{}", recipe.id)]
+            && policy.dialect_op_type == "ScalarMathOp"
+            && policy.dialect_op_name == "nvvm.scalar_math"
+            && policy.dialect_operands == [recipe.dialect_type]
+            && policy.dialect_results == [recipe.dialect_type]
+            && policy.lowering == "generated_scalar_math",
+        "{} changed its scalar-math API, carrier, or lowering",
+        policy.id
+    );
+    ensure!(
+        policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == Some(recipe.minimum_sm)
+            && policy.ptx_result == recipe.rust_type
+            && policy.targets == "all"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.ptx_isa_section
+            && policy.ptx_isa_url == recipe.ptx_isa_url,
+        "{} scalar-math effects, provenance, or target floor changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx
+            == InstructionPattern {
+                mnemonic: scalar_math_operation_name(math.operation).into(),
+                modifiers: recipe.ptx_modifiers.clone(),
+                operands: vec![OperandPattern::Register; 2],
+            },
+        "{} expected scalar-math PTX changed",
+        policy.id
+    );
+    let llvm_mechanism = if recipe.force_inline_ptx {
+        BackendLoweringMechanism::InlinePtx
+    } else {
+        BackendLoweringMechanism::TypedNvvm
+    };
+    let expected_backends = [
+        (
+            IntrinsicBackend::LlvmNvptx,
+            llvm_mechanism,
+            recipe.minimum_sm,
+        ),
+        (
+            IntrinsicBackend::LibNvvm,
+            BackendLoweringMechanism::InlinePtx,
+            recipe.minimum_sm,
+        ),
+    ];
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && expected_backends
+                .into_iter()
+                .all(|(backend, mechanism, minimum_sm)| {
+                    policy.backend_lowerings.iter().any(|lowering| {
+                        lowering.backend == backend
+                            && lowering.mechanism == mechanism
+                            && lowering.minimum_ptx.as_deref() == Some(recipe.minimum_ptx)
+                            && lowering.minimum_sm.as_deref() == Some(minimum_sm)
+                            && !lowering.evidence_profile.trim().is_empty()
+                    })
+                }),
+        "{} has the wrong reviewed scalar-math backend routes (expected {} / {})",
+        policy.id,
+        recipe.minimum_ptx,
+        recipe.minimum_sm
+    );
+    if let Some(direct) = declaration.and_then(|declaration| declaration.selections.first()) {
+        validate_selected_target_predicates(policy, direct)?;
+    }
+    ensure_no_other_family_contract(policy, "scalar math")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/special_register.rs b/crates/cuda-intrinsics-gen/src/resolve/families/special_register.rs
new file mode 100644
index 0000000000..be45a4cdab
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/special_register.rs
@@ -0,0 +1,1459 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ClusterSregAdmission, ImportedIntrinsic, IntrinsicBackend,
+    IntrinsicSource, OverlayBackendLowering, OverlayIntrinsic, RuntimeValidation, SpecialRegister,
+    SpecialRegisterAdmission, SpecialRegisterKind, SpecialRegisterLlvmExclusion,
+    SpecialRegisterLlvmExclusionReason, SpecialRegisterObservation,
+    SpecialRegisterOutputConstraint, SpecialRegisterPtxType, SpecialRegisterWidth,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, bail, ensure};
+use std::collections::BTreeMap;
+
+use crate::resolve::guards::*;
+
+pub(in crate::resolve) const REVIEWED_SPECIAL_REGISTERS: [SpecialRegisterKind; 12] = [
+    SpecialRegisterKind::Clock,
+    SpecialRegisterKind::Clock64,
+    SpecialRegisterKind::Globaltimer,
+    SpecialRegisterKind::Envreg1,
+    SpecialRegisterKind::Envreg2,
+    SpecialRegisterKind::Smid,
+    SpecialRegisterKind::Nsmid,
+    SpecialRegisterKind::Gridid,
+    SpecialRegisterKind::Warpid,
+    SpecialRegisterKind::Nwarpid,
+    SpecialRegisterKind::DynamicSmemSize,
+    SpecialRegisterKind::TotalSmemSize,
+];
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct SpecialRegisterRecipe {
+    kind: SpecialRegisterKind,
+    id: &'static str,
+    operation_key: &'static str,
+    source_record: Option<&'static str>,
+    llvm_symbol: Option<&'static str>,
+    rust_module: &'static str,
+    compatibility_paths: &'static [&'static str],
+    dialect_op_type: &'static str,
+    dialect_op_name: &'static str,
+    register_spelling: &'static str,
+    observation: SpecialRegisterObservation,
+    result_width: SpecialRegisterWidth,
+    ptx_type: SpecialRegisterPtxType,
+    output_constraint: SpecialRegisterOutputConstraint,
+    llvm_mechanism: BackendLoweringMechanism,
+    libnvvm_mechanism: BackendLoweringMechanism,
+    minimum_ptx: &'static str,
+    minimum_sm: Option<&'static str>,
+    execution_scope: &'static str,
+    ptx_isa_section: &'static str,
+    ptx_isa_url: &'static str,
+    selection_record: Option<&'static str>,
+    selection_asm: Option<&'static str>,
+    summary: &'static str,
+}
+
+pub(in crate::resolve) fn special_register_recipe(
+    kind: SpecialRegisterKind,
+) -> SpecialRegisterRecipe {
+    use BackendLoweringMechanism::{InlinePtx, TypedNvvm};
+    use SpecialRegisterKind::*;
+    use SpecialRegisterObservation::{StablePure, VolatileObservation};
+    use SpecialRegisterOutputConstraint::{Register32, Register64};
+    use SpecialRegisterPtxType::{B32, U32, U64};
+    use SpecialRegisterWidth::{B32 as Width32, B64 as Width64};
+
+    match kind {
+        Clock => SpecialRegisterRecipe {
+            kind,
+            id: "clock",
+            operation_key: "debug.clock",
+            source_record: Some("int_nvvm_read_ptx_sreg_clock"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.clock"),
+            rust_module: "debug",
+            compatibility_paths: &["cuda_device::debug::clock"],
+            dialect_op_type: "ReadPtxSregClockOp",
+            dialect_op_name: "nvvm.read_ptx_sreg_clock",
+            register_spelling: "%clock",
+            observation: VolatileObservation,
+            result_width: Width32,
+            ptx_type: U32,
+            output_constraint: Register32,
+            llvm_mechanism: TypedNvvm,
+            libnvvm_mechanism: TypedNvvm,
+            minimum_ptx: "1.0",
+            minimum_sm: None,
+            execution_scope: "sm",
+            ptx_isa_section: "10.23 Special Registers: %clock, %clock_hi",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-clock-clock-hi",
+            selection_record: Some("SREG_CLOCK"),
+            selection_asm: Some("mov.u32 \t$d, %clock;"),
+            summary: "Samples the current SM's 32-bit clock counter.",
+        },
+        Clock64 => SpecialRegisterRecipe {
+            kind,
+            id: "clock64",
+            operation_key: "debug.clock64",
+            source_record: Some("int_nvvm_read_ptx_sreg_clock64"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.clock64"),
+            rust_module: "debug",
+            compatibility_paths: &["cuda_device::debug::clock64"],
+            dialect_op_type: "ReadPtxSregClock64Op",
+            dialect_op_name: "nvvm.read_ptx_sreg_clock64",
+            register_spelling: "%clock64",
+            observation: VolatileObservation,
+            result_width: Width64,
+            ptx_type: U64,
+            output_constraint: Register64,
+            llvm_mechanism: TypedNvvm,
+            libnvvm_mechanism: TypedNvvm,
+            minimum_ptx: "2.0",
+            minimum_sm: Some("sm_20"),
+            execution_scope: "sm",
+            ptx_isa_section: "10.24 Special Registers: %clock64",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-clock64",
+            selection_record: Some("SREG_CLOCK64"),
+            selection_asm: Some("mov.u64 \t$d, %clock64;"),
+            summary: "Samples the current SM's 64-bit clock counter.",
+        },
+        Globaltimer => SpecialRegisterRecipe {
+            kind,
+            id: "globaltimer",
+            operation_key: "debug.global_timer",
+            source_record: Some("int_nvvm_read_ptx_sreg_globaltimer"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.globaltimer"),
+            rust_module: "debug",
+            compatibility_paths: &["cuda_device::debug::globaltimer"],
+            dialect_op_type: "ReadPtxSregGlobaltimerOp",
+            dialect_op_name: "nvvm.read_ptx_sreg_globaltimer",
+            register_spelling: "%globaltimer",
+            observation: VolatileObservation,
+            result_width: Width64,
+            ptx_type: U64,
+            output_constraint: Register64,
+            llvm_mechanism: TypedNvvm,
+            libnvvm_mechanism: InlinePtx,
+            minimum_ptx: "3.1",
+            minimum_sm: Some("sm_30"),
+            execution_scope: "device",
+            ptx_isa_section: "10.28 Special Registers: %globaltimer, %globaltimer_lo, %globaltimer_hi",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-globaltimer",
+            selection_record: Some("SREG_GLOBALTIMER"),
+            selection_asm: Some("mov.u64 \t$d, %globaltimer;"),
+            summary: "Samples the device-wide 64-bit global timer.",
+        },
+        Envreg1 => SpecialRegisterRecipe {
+            kind,
+            id: "envreg1",
+            operation_key: "grid.environment_register.1",
+            source_record: Some("int_nvvm_read_ptx_sreg_envreg1"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.envreg1"),
+            rust_module: "grid",
+            compatibility_paths: &["cuda_device::grid::envreg1"],
+            dialect_op_type: "ReadPtxSregEnvReg1Op",
+            dialect_op_name: "nvvm.read_ptx_sreg_envreg1",
+            register_spelling: "%envreg1",
+            observation: StablePure,
+            result_width: Width32,
+            ptx_type: B32,
+            output_constraint: Register32,
+            llvm_mechanism: TypedNvvm,
+            libnvvm_mechanism: TypedNvvm,
+            minimum_ptx: "2.1",
+            minimum_sm: None,
+            execution_scope: "grid",
+            ptx_isa_section: "10.27 Special Registers: %envreg<32>",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-envreg",
+            selection_record: None,
+            selection_asm: None,
+            summary: "Reads PTX environment register 1.",
+        },
+        Envreg2 => SpecialRegisterRecipe {
+            kind,
+            id: "envreg2",
+            operation_key: "grid.environment_register.2",
+            source_record: Some("int_nvvm_read_ptx_sreg_envreg2"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.envreg2"),
+            rust_module: "grid",
+            compatibility_paths: &["cuda_device::grid::envreg2"],
+            dialect_op_type: "ReadPtxSregEnvReg2Op",
+            dialect_op_name: "nvvm.read_ptx_sreg_envreg2",
+            register_spelling: "%envreg2",
+            observation: StablePure,
+            result_width: Width32,
+            ptx_type: B32,
+            output_constraint: Register32,
+            llvm_mechanism: TypedNvvm,
+            libnvvm_mechanism: TypedNvvm,
+            minimum_ptx: "2.1",
+            minimum_sm: None,
+            execution_scope: "grid",
+            ptx_isa_section: "10.27 Special Registers: %envreg<32>",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-envreg",
+            selection_record: None,
+            selection_asm: None,
+            summary: "Reads PTX environment register 2.",
+        },
+        Smid => SpecialRegisterRecipe {
+            kind,
+            id: "smid",
+            operation_key: "execution.sm_identifier",
+            source_record: Some("int_nvvm_read_ptx_sreg_smid"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.smid"),
+            rust_module: "thread",
+            compatibility_paths: &["cuda_device::thread::smid", "cuda_device::smid"],
+            dialect_op_type: "ReadPtxSregSmIdOp",
+            dialect_op_name: "nvvm.read_ptx_sreg_smid",
+            register_spelling: "%smid",
+            observation: VolatileObservation,
+            result_width: Width32,
+            ptx_type: U32,
+            output_constraint: Register32,
+            llvm_mechanism: InlinePtx,
+            libnvvm_mechanism: InlinePtx,
+            minimum_ptx: "1.3",
+            minimum_sm: None,
+            execution_scope: "thread",
+            ptx_isa_section: "10.8 Special Registers: %smid",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-smid",
+            selection_record: Some("SREG_SMID"),
+            selection_asm: Some("mov.u32 \t$d, %smid;"),
+            summary: "Samples the SM currently executing this thread.",
+        },
+        Nsmid => SpecialRegisterRecipe {
+            kind,
+            id: "nsmid",
+            operation_key: "execution.sm_identifier_bound",
+            source_record: Some("int_nvvm_read_ptx_sreg_nsmid"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.nsmid"),
+            rust_module: "thread",
+            compatibility_paths: &["cuda_device::thread::nsmid", "cuda_device::nsmid"],
+            dialect_op_type: "ReadPtxSregNsmIdOp",
+            dialect_op_name: "nvvm.read_ptx_sreg_nsmid",
+            register_spelling: "%nsmid",
+            observation: StablePure,
+            result_width: Width32,
+            ptx_type: U32,
+            output_constraint: Register32,
+            llvm_mechanism: TypedNvvm,
+            libnvvm_mechanism: TypedNvvm,
+            minimum_ptx: "2.0",
+            minimum_sm: Some("sm_20"),
+            execution_scope: "device",
+            ptx_isa_section: "10.9 Special Registers: %nsmid",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-nsmid",
+            selection_record: Some("SREG_NSMID"),
+            selection_asm: Some("mov.u32 \t$d, %nsmid;"),
+            summary: "Returns the upper bound for SM identifiers.",
+        },
+        Gridid => SpecialRegisterRecipe {
+            kind,
+            id: "gridid",
+            operation_key: "launch.grid_identifier",
+            source_record: None,
+            llvm_symbol: None,
+            rust_module: "thread",
+            compatibility_paths: &["cuda_device::thread::gridid", "cuda_device::gridid"],
+            dialect_op_type: "ReadPtxSregGridIdOp",
+            dialect_op_name: "nvvm.read_ptx_sreg_gridid",
+            register_spelling: "%gridid",
+            observation: StablePure,
+            result_width: Width64,
+            ptx_type: U64,
+            output_constraint: Register64,
+            llvm_mechanism: InlinePtx,
+            libnvvm_mechanism: InlinePtx,
+            minimum_ptx: "3.0",
+            minimum_sm: Some("sm_30"),
+            execution_scope: "grid",
+            ptx_isa_section: "10.10 Special Registers: %gridid",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-gridid",
+            selection_record: None,
+            selection_asm: None,
+            summary: "Returns the full 64-bit temporal grid identifier.",
+        },
+        Warpid => SpecialRegisterRecipe {
+            kind,
+            id: "warpid",
+            operation_key: "warp.hardware_identifier",
+            source_record: Some("int_nvvm_read_ptx_sreg_warpid"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.warpid"),
+            rust_module: "warp",
+            compatibility_paths: &["cuda_device::warp::warpid"],
+            dialect_op_type: "ReadPtxSregWarpIdOp",
+            dialect_op_name: "nvvm.read_ptx_sreg_warpid",
+            register_spelling: "%warpid",
+            observation: VolatileObservation,
+            result_width: Width32,
+            ptx_type: U32,
+            output_constraint: Register32,
+            llvm_mechanism: InlinePtx,
+            libnvvm_mechanism: InlinePtx,
+            minimum_ptx: "1.3",
+            minimum_sm: None,
+            execution_scope: "cta",
+            ptx_isa_section: "10.4 Special Registers: %warpid",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-warpid",
+            selection_record: Some("SREG_WARPID"),
+            selection_asm: Some("mov.u32 \t$d, %warpid;"),
+            summary: "Samples the hardware warp currently executing this thread.",
+        },
+        Nwarpid => SpecialRegisterRecipe {
+            kind,
+            id: "nwarpid",
+            operation_key: "warp.hardware_identifier_bound",
+            source_record: Some("int_nvvm_read_ptx_sreg_nwarpid"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.nwarpid"),
+            rust_module: "warp",
+            compatibility_paths: &["cuda_device::warp::nwarpid"],
+            dialect_op_type: "ReadPtxSregNwarpIdOp",
+            dialect_op_name: "nvvm.read_ptx_sreg_nwarpid",
+            register_spelling: "%nwarpid",
+            observation: StablePure,
+            result_width: Width32,
+            ptx_type: U32,
+            output_constraint: Register32,
+            llvm_mechanism: TypedNvvm,
+            libnvvm_mechanism: TypedNvvm,
+            minimum_ptx: "2.0",
+            minimum_sm: Some("sm_20"),
+            execution_scope: "cta",
+            ptx_isa_section: "10.5 Special Registers: %nwarpid",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-nwarpid",
+            selection_record: Some("SREG_NWARPID"),
+            selection_asm: Some("mov.u32 \t$d, %nwarpid;"),
+            summary: "Returns the upper bound for hardware warp identifiers.",
+        },
+        DynamicSmemSize => SpecialRegisterRecipe {
+            kind,
+            id: "dynamic_smem_size",
+            operation_key: "shared.dynamic_size",
+            source_record: Some("int_nvvm_read_ptx_sreg_dynamic_smem_size"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.dynamic_smem_size"),
+            rust_module: "shared",
+            compatibility_paths: &["cuda_device::shared::dynamic_smem_size"],
+            dialect_op_type: "ReadPtxSregDynamicSmemSizeOp",
+            dialect_op_name: "nvvm.read_ptx_sreg_dynamic_smem_size",
+            register_spelling: "%dynamic_smem_size",
+            observation: StablePure,
+            result_width: Width32,
+            ptx_type: U32,
+            output_constraint: Register32,
+            llvm_mechanism: InlinePtx,
+            libnvvm_mechanism: InlinePtx,
+            minimum_ptx: "4.1",
+            minimum_sm: Some("sm_20"),
+            execution_scope: "cta",
+            ptx_isa_section: "10.32 Special Registers: %dynamic_smem_size",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-dynamic-smem-size",
+            selection_record: Some("INT_PTX_SREG_DYNAMIC_SMEM_SIZE"),
+            selection_asm: Some("mov.u32 \t$d, %dynamic_smem_size;"),
+            summary: "Returns the launch-time dynamic shared-memory size in bytes.",
+        },
+        TotalSmemSize => SpecialRegisterRecipe {
+            kind,
+            id: "total_smem_size",
+            operation_key: "shared.total_size",
+            source_record: Some("int_nvvm_read_ptx_sreg_total_smem_size"),
+            llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.total_smem_size"),
+            rust_module: "shared",
+            compatibility_paths: &["cuda_device::shared::total_smem_size"],
+            dialect_op_type: "ReadPtxSregTotalSmemSizeOp",
+            dialect_op_name: "nvvm.read_ptx_sreg_total_smem_size",
+            register_spelling: "%total_smem_size",
+            observation: StablePure,
+            result_width: Width32,
+            ptx_type: U32,
+            output_constraint: Register32,
+            llvm_mechanism: InlinePtx,
+            libnvvm_mechanism: InlinePtx,
+            minimum_ptx: "4.1",
+            minimum_sm: Some("sm_20"),
+            execution_scope: "cta",
+            ptx_isa_section: "10.30 Special Registers: %total_smem_size",
+            ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-total-smem-size",
+            selection_record: Some("INT_PTX_SREG_TOTAL_SMEM_SIZE"),
+            selection_asm: Some("mov.u32 \t$d, %total_smem_size;"),
+            summary: "Returns the total user shared-memory allocation in bytes.",
+        },
+    }
+}
+
+pub(in crate::resolve) fn special_register_ptx_type(
+    ptx_type: SpecialRegisterPtxType,
+) -> &'static str {
+    match ptx_type {
+        SpecialRegisterPtxType::B32 => "b32",
+        SpecialRegisterPtxType::U32 => "u32",
+        SpecialRegisterPtxType::U64 => "u64",
+    }
+}
+
+pub(in crate::resolve) fn special_register_backend_floor(
+    recipe: SpecialRegisterRecipe,
+    backend: IntrinsicBackend,
+) -> (Option<&'static str>, Option<&'static str>) {
+    match backend {
+        IntrinsicBackend::LlvmNvptx => {
+            let minimum_ptx = if matches!(recipe.minimum_ptx, "4.1") {
+                "4.1"
+            } else {
+                "3.2"
+            };
+            let minimum_sm = if recipe.minimum_sm == Some("sm_30") {
+                "sm_30"
+            } else {
+                "sm_20"
+            };
+            (Some(minimum_ptx), Some(minimum_sm))
+        }
+        IntrinsicBackend::LibNvvm => (None, Some("sm_75")),
+    }
+}
+
+pub(in crate::resolve) fn special_register_contract(
+    recipe: SpecialRegisterRecipe,
+) -> SpecialRegister {
+    let llvm_exclusion =
+        (recipe.kind == SpecialRegisterKind::Gridid).then(|| SpecialRegisterLlvmExclusion {
+            source_record: "int_nvvm_read_ptx_sreg_gridid".into(),
+            llvm_symbol: "llvm.nvvm.read.ptx.sreg.gridid".into(),
+            imported_result_width: SpecialRegisterWidth::B32,
+            reason: SpecialRegisterLlvmExclusionReason::ResultWidthMismatch,
+        });
+    SpecialRegister {
+        register: recipe.kind,
+        observation: recipe.observation,
+        result_width: recipe.result_width,
+        ptx_type: recipe.ptx_type,
+        output_constraint: recipe.output_constraint,
+        llvm_exclusion,
+    }
+}
+
+pub(in crate::resolve) fn expand_special_register_admission(
+    admission: &SpecialRegisterAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "special-register runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact special-register admission requires both backend evidence profiles"
+    );
+    ensure!(
+        admission.registers == REVIEWED_SPECIAL_REGISTERS
+            && admission.product_count == REVIEWED_SPECIAL_REGISTERS.len(),
+        "compact special-register admission must list the canonical 12 registers exactly once and in order"
+    );
+
+    admission
+        .registers
+        .iter()
+        .copied()
+        .map(|kind| {
+            let recipe = special_register_recipe(kind);
+            let width = recipe.result_width.bits();
+            let rust_result = format!("u{width}");
+            let dialect_result = format!("i{width}");
+            let source = match recipe.source_record {
+                Some(_) => None,
+                None => Some(IntrinsicSource::PtxNative {
+                    instruction: format!(
+                        "mov.{} {}",
+                        special_register_ptx_type(recipe.ptx_type),
+                        recipe.register_spelling
+                    ),
+                }),
+            };
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: String::new(),
+                operation_key: recipe.operation_key.into(),
+                family: "sreg".into(),
+                source,
+                source_record: recipe.source_record.map(str::to_owned),
+                rust_module: recipe.rust_module.into(),
+                rust_name: recipe.id.into(),
+                rust_arguments: vec![],
+                rust_result: rust_result.clone(),
+                safe: true,
+                must_use: false,
+                safe_allowlist_reason: Some(
+                    "reading this special register has no caller obligations.".into(),
+                ),
+                public_rust_path: format!("cuda_intrinsics::{}::{}", recipe.rust_module, recipe.id),
+                compatibility_rust_paths: recipe
+                    .compatibility_paths
+                    .iter()
+                    .map(|path| (*path).into())
+                    .collect(),
+                dialect_op_type: recipe.dialect_op_type.into(),
+                dialect_op_name: recipe.dialect_op_name.into(),
+                dialect_operands: vec![],
+                dialect_results: vec![dialect_result.clone()],
+                llvm_symbol: recipe.llvm_symbol.map(str::to_owned),
+                resolved_llvm_symbol: None,
+                llvm_arguments: vec![],
+                llvm_results: recipe
+                    .source_record
+                    .map(|_| dialect_result)
+                    .into_iter()
+                    .collect(),
+                pure: recipe.observation == SpecialRegisterObservation::StablePure,
+                memory: if matches!(
+                    recipe.kind,
+                    SpecialRegisterKind::Clock
+                        | SpecialRegisterKind::Clock64
+                        | SpecialRegisterKind::Globaltimer
+                ) {
+                    "inaccessible_read_write".into()
+                } else {
+                    "none".into()
+                },
+                convergent: false,
+                execution_scope: recipe.execution_scope.into(),
+                minimum_ptx: recipe.minimum_ptx.into(),
+                minimum_sm: recipe.minimum_sm.map(str::to_owned),
+                ptx_result: rust_result,
+                targets: "all".into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section: recipe.ptx_isa_section.into(),
+                ptx_isa_url: recipe.ptx_isa_url.into(),
+                lowering: "generated_special_register".into(),
+                backend_lowerings: [
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        recipe.llvm_mechanism,
+                        &admission.llvm_evidence_profile,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        recipe.libnvvm_mechanism,
+                        &admission.libnvvm_evidence_profile,
+                    ),
+                ]
+                .into_iter()
+                .map(
+                    |(backend, mechanism, evidence_profile)| OverlayBackendLowering {
+                        minimum_ptx: special_register_backend_floor(recipe, backend)
+                            .0
+                            .map(str::to_owned),
+                        minimum_sm: special_register_backend_floor(recipe, backend)
+                            .1
+                            .map(str::to_owned),
+                        backend,
+                        mechanism,
+                        evidence_profile: evidence_profile.clone(),
+                        targets: None,
+                    },
+                )
+                .collect(),
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: Some(special_register_contract(recipe)),
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: "mov".into(),
+                    modifiers: vec![special_register_ptx_type(recipe.ptx_type).into()],
+                    operands: vec![
+                        OperandPattern::Register,
+                        OperandPattern::Exact {
+                            value: recipe.register_spelling.into(),
+                        },
+                    ],
+                },
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn validate_special_register_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+    declaration: Option<&ImportedIntrinsic>,
+) -> Result<()> {
+    let special = policy
+        .special_register
+        .as_ref()
+        .with_context(|| format!("{} has no closed special-register contract", policy.id))?;
+    let recipe = special_register_recipe(special.register);
+    ensure!(
+        special == &special_register_contract(recipe),
+        "{} special-register width, PTX type, constraint, observation, or LLVM exclusion changed",
+        policy.id
+    );
+    let expected_source = match recipe.source_record {
+        Some(source_record) => IntrinsicSource::LlvmImported {
+            source_record: source_record.into(),
+        },
+        None => IntrinsicSource::PtxNative {
+            instruction: format!(
+                "mov.{} {}",
+                special_register_ptx_type(recipe.ptx_type),
+                recipe.register_spelling
+            ),
+        },
+    };
+    ensure!(
+        policy.id == recipe.id
+            && policy.operation_key == recipe.operation_key
+            && source == &expected_source
+            && policy.source_record.as_deref() == recipe.source_record
+            && policy.llvm_symbol.as_deref() == recipe.llvm_symbol
+            && policy.resolved_llvm_symbol.is_none()
+            && policy.llvm_arguments.is_empty(),
+        "{} special-register identity or source changed",
+        policy.id
+    );
+    let width = recipe.result_width.bits();
+    let rust_result = format!("u{width}");
+    let dialect_result = format!("i{width}");
+    let expected_llvm_results = recipe
+        .source_record
+        .map(|_| dialect_result.clone())
+        .into_iter()
+        .collect::<Vec<_>>();
+    ensure!(
+        policy.rust_module == recipe.rust_module
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments.is_empty()
+            && policy.rust_result == rust_result
+            && policy.safe
+            && !policy.must_use
+            && policy.public_rust_path
+                == format!("cuda_intrinsics::{}::{}", recipe.rust_module, recipe.id)
+            && policy.compatibility_rust_paths
+                == recipe
+                    .compatibility_paths
+                    .iter()
+                    .map(|path| (*path).to_owned())
+                    .collect::<Vec<_>>(),
+        "{} special-register Rust API changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands.is_empty()
+            && policy.dialect_results == [dialect_result.as_str()]
+            && policy.llvm_results == expected_llvm_results
+            && policy.lowering == "generated_special_register",
+        "{} special-register carrier, result width, or lowering changed",
+        policy.id
+    );
+    let expected_pure = recipe.observation == SpecialRegisterObservation::StablePure;
+    let expected_memory = if matches!(
+        recipe.kind,
+        SpecialRegisterKind::Clock
+            | SpecialRegisterKind::Clock64
+            | SpecialRegisterKind::Globaltimer
+    ) {
+        "inaccessible_read_write"
+    } else {
+        "none"
+    };
+    ensure!(
+        policy.pure == expected_pure
+            && policy.memory == expected_memory
+            && !policy.convergent
+            && policy.execution_scope == recipe.execution_scope,
+        "{} special-register observation or effects changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == recipe.minimum_sm
+            && policy.ptx_result == rust_result
+            && policy.targets == "all"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.ptx_isa_section
+            && policy.ptx_isa_url == recipe.ptx_isa_url,
+        "{} special-register target floor or PTX provenance changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx
+            == InstructionPattern {
+                mnemonic: "mov".into(),
+                modifiers: vec![special_register_ptx_type(recipe.ptx_type).into()],
+                operands: vec![
+                    OperandPattern::Register,
+                    OperandPattern::Exact {
+                        value: recipe.register_spelling.into(),
+                    },
+                ],
+            },
+        "{} special-register PTX shape changed",
+        policy.id
+    );
+    let expected_routes = [
+        (
+            IntrinsicBackend::LlvmNvptx,
+            recipe.llvm_mechanism,
+            special_register_backend_floor(recipe, IntrinsicBackend::LlvmNvptx),
+        ),
+        (
+            IntrinsicBackend::LibNvvm,
+            recipe.libnvvm_mechanism,
+            special_register_backend_floor(recipe, IntrinsicBackend::LibNvvm),
+        ),
+    ];
+    ensure!(
+        policy.backend_lowerings.len() == expected_routes.len()
+            && policy.backend_lowerings.iter().zip(expected_routes).all(
+                |(actual, (backend, mechanism, (minimum_ptx, minimum_sm)))| {
+                    actual.backend == backend
+                        && actual.mechanism == mechanism
+                        && !actual.evidence_profile.trim().is_empty()
+                        && actual.minimum_ptx.as_deref() == minimum_ptx
+                        && actual.minimum_sm.as_deref() == minimum_sm
+                }
+            ),
+        "{} special-register backend routes changed",
+        policy.id
+    );
+    ensure!(
+        policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.cp_async_mbarrier.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.register_mma.is_none()
+            && policy.sparse_mma.is_none()
+            && policy.prmt.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with a special register",
+        policy.id
+    );
+
+    match (recipe.source_record, declaration) {
+        (None, None) => {}
+        (Some(_), Some(declaration)) => {
+            let timer = matches!(
+                recipe.kind,
+                SpecialRegisterKind::Clock
+                    | SpecialRegisterKind::Clock64
+                    | SpecialRegisterKind::Globaltimer
+            );
+            let expected_properties: &[&str] = if timer {
+                &[
+                    "IntrInaccessibleMemOnly",
+                    "IntrNoCallback",
+                    "IntrNoFree",
+                    "IntrWillReturn",
+                    "NoUndef<ret>",
+                ]
+            } else {
+                &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"]
+            };
+            ensure!(
+                declaration.arguments.is_empty()
+                    && declaration.results == [dialect_result.as_str()]
+                    && declaration.properties
+                        == expected_properties
+                            .iter()
+                            .map(|property| (*property).to_owned())
+                            .collect::<Vec<_>>()
+                    && if timer {
+                        declaration
+                            .classes
+                            .iter()
+                            .any(|class| class == "PTXReadNCSRegIntrinsic")
+                    } else {
+                        declaration
+                            .classes
+                            .iter()
+                            .any(|class| class == "NVVMPureIntrinsic")
+                    },
+                "{} imported special-register signature, class, or properties changed",
+                policy.id
+            );
+            match (recipe.selection_record, recipe.selection_asm) {
+                (None, None) => ensure!(
+                    declaration.selections.is_empty(),
+                    "{} selectionless environment-register contract changed",
+                    policy.id
+                ),
+                (Some(selection_record), Some(selection_asm)) => ensure!(
+                    declaration.selections.len() == 1
+                        && declaration.selections[0].source_record == selection_record
+                        && declaration.selections[0].asm == selection_asm
+                        && declaration.selections[0].predicates.is_empty()
+                        && declaration.selections[0].constraints.is_empty(),
+                    "{} imported special-register selection changed",
+                    policy.id
+                ),
+                _ => unreachable!("closed special-register selection recipe"),
+            }
+        }
+        _ => bail!(
+            "{} special-register source and imported declaration disagree",
+            policy.id
+        ),
+    }
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_special_register_llvm_exclusion(
+    policy: &OverlayIntrinsic,
+    imported_by_record: &BTreeMap<&str, &ImportedIntrinsic>,
+) -> Result<()> {
+    let Some(exclusion) = policy
+        .special_register
+        .as_ref()
+        .and_then(|special| special.llvm_exclusion.as_ref())
+    else {
+        return Ok(());
+    };
+    let declaration = imported_by_record
+        .get(exclusion.source_record.as_str())
+        .with_context(|| {
+            format!(
+                "{} excludes missing imported LLVM record {}",
+                policy.id, exclusion.source_record
+            )
+        })?;
+    ensure!(
+        policy.id == "gridid"
+            && exclusion.reason == SpecialRegisterLlvmExclusionReason::ResultWidthMismatch
+            && exclusion.imported_result_width == SpecialRegisterWidth::B32
+            && declaration.llvm_name == exclusion.llvm_symbol
+            && declaration.arguments.is_empty()
+            && declaration.results == ["i32"]
+            && declaration.properties == ["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"]
+            && declaration.selections.len() == 1
+            && declaration.selections[0].source_record == "SREG_GRIDID"
+            && declaration.selections[0].asm == "mov.u32 \t$d, %gridid;"
+            && declaration.selections[0].predicates.is_empty()
+            && declaration.selections[0].constraints.is_empty()
+            && policy.rust_result == "u64"
+            && policy.dialect_results == ["i64"],
+        "{} LLVM exclusion no longer proves the reviewed i32-to-u64 gridid width mismatch",
+        policy.id
+    );
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_sreg_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+    declaration: Option<&ImportedIntrinsic>,
+) -> Result<()> {
+    if policy.special_register.is_some() {
+        return validate_special_register_policy(policy, source, declaration);
+    }
+    let declaration = declaration.context("sreg requires imported LLVM declaration")?;
+    ensure!(
+        policy.rust_arguments.is_empty() && policy.llvm_arguments.is_empty(),
+        "{} is not a zero-operand intrinsic; the sreg recipe cannot lower it",
+        policy.id
+    );
+    ensure!(
+        matches!(policy.rust_result.as_str(), "u32" | "u64"),
+        "{} has unsupported raw scalar result {}",
+        policy.id,
+        policy.rust_result
+    );
+    let expected_llvm_result = match policy.rust_result.as_str() {
+        "u32" => "i32",
+        "u64" => "i64",
+        _ => unreachable!(),
+    };
+    ensure!(
+        policy.llvm_results == [expected_llvm_result]
+            && policy.ptx_result == policy.rust_result
+            && policy.lowering == "direct_nvvm",
+        "{} has a signature or lowering outside the scalar direct-NVVM sreg recipe",
+        policy.id
+    );
+    ensure!(
+        policy.resolved_llvm_symbol.is_none()
+            && policy.backend_lowerings.is_empty()
+            && policy.special_register.is_none(),
+        "{} uses a backend contract outside the direct-NVVM sreg recipe",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "sreg")?;
+    if policy.id.starts_with("lanemask_") {
+        validate_lanemask_policy(policy, declaration)?;
+    }
+    if is_cluster_sreg_source(&declaration.source_record) {
+        validate_cluster_sreg_policy(policy, declaration)?;
+    }
+    Ok(())
+}
+
+pub(in crate::resolve) fn is_cluster_sreg_source(source_record: &str) -> bool {
+    source_record == "int_nvvm_read_ptx_sreg_cluster_ctarank"
+        || source_record == "int_nvvm_read_ptx_sreg_cluster_nctarank"
+        || source_record.starts_with("int_nvvm_read_ptx_sreg_cluster_ctaid_")
+        || source_record.starts_with("int_nvvm_read_ptx_sreg_cluster_nctaid_")
+        || source_record.starts_with("int_nvvm_read_ptx_sreg_clusterid_")
+        || source_record.starts_with("int_nvvm_read_ptx_sreg_nclusterid_")
+}
+
+#[derive(Clone)]
+pub(in crate::resolve) struct ClusterSregRecipe {
+    id: String,
+    operation_key: String,
+    source_suffix: String,
+    llvm_suffix: String,
+    selection_record: String,
+    ptx_register: String,
+    compatibility_path: Option<String>,
+    op_type: String,
+    scope: &'static str,
+    section: &'static str,
+    anchor: &'static str,
+    range: Option<&'static str>,
+    safe_reason: String,
+    summary: String,
+}
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct ClusterSregXyzFamilyRecipe {
+    id_prefix: &'static str,
+    operation_key_prefix: &'static str,
+    source_prefix: &'static str,
+    llvm_prefix: &'static str,
+    selection_prefix: &'static str,
+    ptx_prefix: &'static str,
+    compatibility_prefix: Option<&'static str>,
+    op_type_prefix: &'static str,
+    scope: &'static str,
+    section: &'static str,
+    anchor: &'static str,
+    x_range: &'static str,
+    yz_range: &'static str,
+    safe_reason: &'static str,
+    summary: &'static str,
+}
+
+pub(in crate::resolve) const CLUSTER_SREG_AXES: [&str; 3] = ["x", "y", "z"];
+
+pub(in crate::resolve) const CLUSTER_SREG_XYZ_FAMILIES: [ClusterSregXyzFamilyRecipe; 4] = [
+    ClusterSregXyzFamilyRecipe {
+        id_prefix: "cluster_block_idx",
+        operation_key_prefix: "launch.cluster.block_index",
+        source_prefix: "cluster_ctaid_",
+        llvm_prefix: "cluster.ctaid.",
+        selection_prefix: "INT_PTX_SREG_CLUSTER_CTAID_",
+        ptx_prefix: "%cluster_ctaid.",
+        compatibility_prefix: Some("cuda_device::cluster::cluster_ctaid"),
+        op_type_prefix: "ReadPtxSregClusterCtaid",
+        scope: "cta",
+        section: "10.14 Special Registers: %cluster_ctaid",
+        anchor: "cluster-ctaid",
+        x_range: "Range<ret,0,2147483647>",
+        yz_range: "Range<ret,0,65535>",
+        safe_reason: "reading the read-only block index within its cluster has no caller obligations",
+        summary: "Returns the block's {axis} index within its thread block cluster.",
+    },
+    ClusterSregXyzFamilyRecipe {
+        id_prefix: "cluster_dim",
+        operation_key_prefix: "launch.cluster.dimension",
+        source_prefix: "cluster_nctaid_",
+        llvm_prefix: "cluster.nctaid.",
+        selection_prefix: "INT_PTX_SREG_CLUSTER_NCTAID_",
+        ptx_prefix: "%cluster_nctaid.",
+        compatibility_prefix: Some("cuda_device::cluster::cluster_nctaid"),
+        op_type_prefix: "ReadPtxSregClusterNctaid",
+        scope: "cluster",
+        section: "10.15 Special Registers: %cluster_nctaid",
+        anchor: "cluster-nctaid",
+        x_range: "Range<ret,1,2147483648>",
+        yz_range: "Range<ret,1,65536>",
+        safe_reason: "reading the read-only cluster dimension has no caller obligations",
+        summary: "Returns the number of blocks in the cluster's {axis} dimension.",
+    },
+    ClusterSregXyzFamilyRecipe {
+        id_prefix: "cluster_idx",
+        operation_key_prefix: "launch.cluster.index",
+        source_prefix: "clusterid_",
+        llvm_prefix: "clusterid.",
+        selection_prefix: "INT_PTX_SREG_CLUSTERID_",
+        ptx_prefix: "%clusterid.",
+        compatibility_prefix: Some("cuda_device::cluster::__cluster_idx"),
+        op_type_prefix: "ReadPtxSregClusterId",
+        scope: "cluster",
+        section: "10.12 Special Registers: %clusterid",
+        anchor: "clusterid",
+        x_range: "Range<ret,0,2147483647>",
+        yz_range: "Range<ret,0,65535>",
+        safe_reason: "reading the read-only cluster index has no caller obligations",
+        summary: "Returns the cluster's {axis} index within the grid.",
+    },
+    ClusterSregXyzFamilyRecipe {
+        id_prefix: "cluster_grid_dim",
+        operation_key_prefix: "launch.cluster.grid_dimension",
+        source_prefix: "nclusterid_",
+        llvm_prefix: "nclusterid.",
+        selection_prefix: "INT_PTX_SREG_NCLUSTERID_",
+        ptx_prefix: "%nclusterid.",
+        compatibility_prefix: Some("cuda_device::cluster::__cluster_grid_dim"),
+        op_type_prefix: "ReadPtxSregNclusterId",
+        scope: "grid",
+        section: "10.13 Special Registers: %nclusterid",
+        anchor: "nclusterid",
+        x_range: "Range<ret,1,2147483648>",
+        yz_range: "Range<ret,1,65536>",
+        safe_reason: "reading the read-only cluster-grid dimension has no caller obligations",
+        summary: "Returns the number of clusters in the grid's {axis} dimension.",
+    },
+];
+
+pub(in crate::resolve) fn cluster_sreg_recipes() -> Vec<ClusterSregRecipe> {
+    let mut recipes = Vec::with_capacity(14);
+    for family in CLUSTER_SREG_XYZ_FAMILIES {
+        for axis in CLUSTER_SREG_AXES {
+            let axis_upper = axis.to_ascii_uppercase();
+            recipes.push(ClusterSregRecipe {
+                id: format!("{}_{axis}", family.id_prefix),
+                operation_key: format!("{}.{axis}", family.operation_key_prefix),
+                source_suffix: format!("{}{axis}", family.source_prefix),
+                llvm_suffix: format!("{}{axis}", family.llvm_prefix),
+                selection_record: format!("{}{axis}", family.selection_prefix),
+                ptx_register: format!("{}{axis}", family.ptx_prefix),
+                compatibility_path: family
+                    .compatibility_prefix
+                    .map(|prefix| format!("{prefix}{axis_upper}")),
+                op_type: format!("{}{axis_upper}Op", family.op_type_prefix),
+                scope: family.scope,
+                section: family.section,
+                anchor: family.anchor,
+                range: Some(if axis == "x" {
+                    family.x_range
+                } else {
+                    family.yz_range
+                }),
+                safe_reason: family.safe_reason.into(),
+                summary: family.summary.replace("{axis}", &axis_upper),
+            });
+        }
+    }
+    recipes.extend([
+        ClusterSregRecipe {
+            id: "cluster_block_rank".into(),
+            operation_key: "launch.cluster.block_rank".into(),
+            source_suffix: "cluster_ctarank".into(),
+            llvm_suffix: "cluster.ctarank".into(),
+            selection_record: "INT_PTX_SREG_CLUSTER_CTARANK".into(),
+            ptx_register: "%cluster_ctarank".into(),
+            compatibility_path: None,
+            op_type: "ReadPtxSregClusterCtarankOp".into(),
+            scope: "cta",
+            section: "10.16 Special Registers: %cluster_ctarank",
+            anchor: "cluster-ctarank",
+            range: None,
+            safe_reason:
+                "reading the read-only block rank within its cluster has no caller obligations"
+                    .into(),
+            summary: "Returns the block's linear rank within its thread block cluster.".into(),
+        },
+        ClusterSregRecipe {
+            id: "cluster_block_count".into(),
+            operation_key: "launch.cluster.block_count".into(),
+            source_suffix: "cluster_nctarank".into(),
+            llvm_suffix: "cluster.nctarank".into(),
+            selection_record: "INT_PTX_SREG_CLUSTER_NCTARANK".into(),
+            ptx_register: "%cluster_nctarank".into(),
+            compatibility_path: None,
+            op_type: "ReadPtxSregClusterNctarankOp".into(),
+            scope: "cluster",
+            section: "10.17 Special Registers: %cluster_nctarank",
+            anchor: "cluster-nctarank",
+            range: None,
+            safe_reason: "reading the read-only block count has no caller obligations".into(),
+            summary: "Returns the total number of blocks in the thread block cluster.".into(),
+        },
+    ]);
+    recipes
+}
+
+pub(in crate::resolve) fn expand_cluster_sreg_admission(
+    admission: &ClusterSregAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.axes == CLUSTER_SREG_AXES,
+        "cluster-sreg axes must be exactly x, y, z"
+    );
+    ensure!(
+        admission.xyz_product_count == 12 && admission.record_count == 14,
+        "cluster-sreg admission must expand to 12 xyz and 14 total records"
+    );
+    let recipes = cluster_sreg_recipes();
+    ensure!(
+        recipes.len() == admission.record_count,
+        "cluster-sreg recipe count disagrees with its admission"
+    );
+    Ok(recipes.into_iter().map(cluster_sreg_policy).collect())
+}
+
+pub(in crate::resolve) fn cluster_sreg_policy(recipe: ClusterSregRecipe) -> OverlayIntrinsic {
+    let compatibility_rust_paths = recipe.compatibility_path.iter().cloned().collect();
+    OverlayIntrinsic {
+        id: recipe.id.clone(),
+        abi_id: String::new(),
+        operation_key: recipe.operation_key,
+        family: "sreg".into(),
+        source: None,
+        source_record: Some(format!("int_nvvm_read_ptx_sreg_{}", recipe.source_suffix)),
+        rust_module: "sreg".into(),
+        rust_name: recipe.id.clone(),
+        rust_arguments: vec![],
+        rust_result: "u32".into(),
+        safe: true,
+        must_use: false,
+        safe_allowlist_reason: Some(recipe.safe_reason),
+        public_rust_path: format!("cuda_intrinsics::sreg::{}", recipe.id),
+        compatibility_rust_paths,
+        dialect_op_type: recipe.op_type,
+        dialect_op_name: format!("nvvm.read_ptx_sreg_{}", recipe.source_suffix),
+        dialect_operands: vec![],
+        dialect_results: vec![],
+        llvm_symbol: Some(format!("llvm.nvvm.read.ptx.sreg.{}", recipe.llvm_suffix)),
+        resolved_llvm_symbol: None,
+        llvm_arguments: vec![],
+        llvm_results: vec!["i32".into()],
+        pure: true,
+        memory: "none".into(),
+        convergent: false,
+        execution_scope: recipe.scope.into(),
+        minimum_ptx: "7.8".into(),
+        minimum_sm: Some("sm_90".into()),
+        ptx_result: "u32".into(),
+        targets: "all".into(),
+        ptx_isa_version: "9.3".into(),
+        ptx_isa_section: recipe.section.into(),
+        ptx_isa_url: format!(
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-{}",
+            recipe.anchor
+        ),
+        lowering: "direct_nvvm".into(),
+        backend_lowerings: vec![],
+        packed_atomic: None,
+        redux: None,
+        vote: None,
+        active_mask: None,
+        warp_match: None,
+        warp_barrier: None,
+        warp_shuffle: None,
+        dot_product: None,
+        packed_alu: None,
+        integer_minmax: None,
+        packed_conversion: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cp_async_copy: None,
+        cp_async_control: None,
+        cp_async_mbarrier: None,
+        mbarrier_basic: None,
+        movmatrix: None,
+        mbarrier_extended: None,
+        register_mma: None,
+        sparse_mma: None,
+        prmt: None,
+        cluster_barrier: None,
+        wgmma_control: None,
+        special_register: None,
+        debug_control: None,
+        cluster_memory: None,
+        clc: None,
+        tma: None,
+        tcgen05: None,
+        ldmatrix_variant: None,
+        ldmatrix_safety: None,
+        ldmatrix_adapter: None,
+        selected_address_space: None,
+        expected_ptx: InstructionPattern {
+            mnemonic: "mov".into(),
+            modifiers: vec!["u32".into()],
+            operands: vec![
+                OperandPattern::Register,
+                OperandPattern::Exact {
+                    value: recipe.ptx_register,
+                },
+            ],
+        },
+        summary: recipe.summary,
+    }
+}
+
+pub(in crate::resolve) fn validate_cluster_sreg_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    ensure!(
+        !declaration.source_record.ends_with("_w"),
+        "{} selects an unused always-zero fourth cluster-register component",
+        policy.id
+    );
+    let recipe = cluster_sreg_recipes()
+        .into_iter()
+        .find(|recipe| recipe.id == policy.id)
+        .with_context(|| format!("{} is not a reviewed cluster special register", policy.id))?;
+
+    let source_record = format!("int_nvvm_read_ptx_sreg_{}", recipe.source_suffix);
+    let llvm_symbol = format!("llvm.nvvm.read.ptx.sreg.{}", recipe.llvm_suffix);
+    let compatibility_paths = recipe
+        .compatibility_path
+        .iter()
+        .cloned()
+        .collect::<Vec<_>>();
+    ensure!(
+        policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(source_record.as_str())
+            && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} cluster-register identity does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "sreg"
+            && policy.rust_name == policy.id
+            && policy.rust_arguments.is_empty()
+            && policy.rust_result == "u32"
+            && policy.safe
+            && !policy.must_use
+            && policy
+                .safe_allowlist_reason
+                .as_deref()
+                .is_some_and(|reason| !reason.is_empty())
+            && policy.public_rust_path == format!("cuda_intrinsics::sreg::{}", policy.id)
+            && policy.compatibility_rust_paths == compatibility_paths,
+        "{} must preserve its reviewed raw and compatibility APIs",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.op_type
+            && policy.dialect_op_name == format!("nvvm.read_ptx_sreg_{}", recipe.source_suffix)
+            && policy.dialect_operands.is_empty()
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments.is_empty()
+            && policy.llvm_results == ["i32"]
+            && policy.lowering == "direct_nvvm",
+        "{} is outside the closed cluster-register lowering recipe",
+        policy.id
+    );
+    ensure!(
+        policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == recipe.scope
+            && policy.minimum_ptx == "7.8"
+            && policy.minimum_sm.as_deref() == Some("sm_90")
+            && policy.ptx_result == "u32"
+            && policy.targets == "all",
+        "{} cluster-register effects or target floor disagree with PTX",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.section
+            && policy.ptx_isa_url
+                == format!(
+                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-{}",
+                    recipe.anchor
+                ),
+        "{} cluster-register PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    let mut properties = vec!["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"];
+    properties.extend(recipe.range);
+    ensure!(
+        declaration.arguments.is_empty()
+            && declaration.results == ["i32"]
+            && declaration.classes
+                == [
+                    "SDPatternOperator",
+                    "Intrinsic",
+                    "DefaultAttrsIntrinsic",
+                    "NVVMPureIntrinsic",
+                    "PTXReadSRegIntrinsicNB_r32",
+                ]
+            && declaration.properties == properties,
+        "{} declaration shape or properties disagree with LLVM TableGen",
+        policy.id
+    );
+    let [selection] = declaration.selections.as_slice() else {
+        bail!("{} must have exactly one LLVM selection", policy.id);
+    };
+    ensure!(
+        selection.source_record == recipe.selection_record
+            && selection.asm == format!("mov.u32 \t$d, {};", recipe.ptx_register)
+            && selection.predicates
+                == [
+                    "Subtarget->getSmVersion() >= 90",
+                    "Subtarget->getPTXVersion() >= 78",
+                ]
+            && selection.constraints.address_space.is_none()
+            && selection.constraints.immediate_bindings.is_empty(),
+        "{} selector disagrees with LLVM TableGen",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "mov"
+            && policy.expected_ptx.modifiers == ["u32"]
+            && policy.expected_ptx.operands
+                == [
+                    OperandPattern::Register,
+                    OperandPattern::Exact {
+                        value: recipe.ptx_register,
+                    },
+                ],
+        "{} expected PTX does not match its cluster register",
+        policy.id
+    );
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_lanemask_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let (suffix, abi_id, section, op_type) = match policy.id.as_str() {
+        "lanemask_lt" => ("lt", "i0035", "10.13", "ReadPtxSregLanemaskLtOp"),
+        "lanemask_le" => ("le", "i0036", "10.12", "ReadPtxSregLanemaskLeOp"),
+        "lanemask_eq" => ("eq", "i0037", "10.11", "ReadPtxSregLanemaskEqOp"),
+        "lanemask_ge" => ("ge", "i0038", "10.14", "ReadPtxSregLanemaskGeOp"),
+        "lanemask_gt" => ("gt", "i0039", "10.15", "ReadPtxSregLanemaskGtOp"),
+        _ => bail!("{} is not a reviewed lane-mask special register", policy.id),
+    };
+    ensure!(
+        policy.abi_id == abi_id
+            && policy.operation_key == format!("warp.lane_mask.{suffix}")
+            && policy.source.is_none()
+            && policy.source_record.as_deref()
+                == Some(format!("int_nvvm_read_ptx_sreg_lanemask_{suffix}").as_str())
+            && policy.llvm_symbol.as_deref()
+                == Some(format!("llvm.nvvm.read.ptx.sreg.lanemask.{suffix}").as_str())
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} lane-mask identity does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "sreg"
+            && policy.rust_name == policy.id
+            && policy.rust_arguments.is_empty()
+            && policy.rust_result == "u32"
+            && policy.safe
+            && policy.must_use
+            && policy
+                .safe_allowlist_reason
+                .as_deref()
+                .is_some_and(|reason| !reason.is_empty())
+            && policy.public_rust_path == format!("cuda_intrinsics::sreg::{}", policy.id)
+            && policy.compatibility_rust_paths == [format!("cuda_device::warp::{}", policy.id)],
+        "{} must preserve its safe must-use raw and compatibility APIs",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == op_type
+            && policy.dialect_op_name == format!("nvvm.read_ptx_sreg_lanemask_{suffix}")
+            && policy.dialect_operands.is_empty()
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments.is_empty()
+            && policy.llvm_results == ["i32"]
+            && policy.lowering == "direct_nvvm",
+        "{} is outside the closed lane-mask lowering recipe",
+        policy.id
+    );
+    ensure!(
+        policy.pure
+            && policy.memory == "none"
+            && !policy.convergent
+            && policy.execution_scope == "thread"
+            && policy.minimum_ptx == "2.0"
+            && policy.minimum_sm.as_deref() == Some("sm_20")
+            && policy.ptx_result == "u32"
+            && policy.targets == "all",
+        "{} lane-mask effects or target floor disagree with PTX",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == format!("{section} Special Registers: %lanemask_{suffix}")
+            && policy.ptx_isa_url
+                == format!(
+                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-lanemask-{suffix}"
+                ),
+        "{} lane-mask PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.properties == ["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+        "{} lane-mask properties disagree with the imported LLVM declaration",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "mov"
+            && policy.expected_ptx.modifiers == ["u32"]
+            && policy.expected_ptx.operands
+                == [
+                    OperandPattern::Register,
+                    OperandPattern::Exact {
+                        value: format!("%lanemask_{suffix}"),
+                    },
+                ],
+        "{} expected PTX does not match its lane-mask register",
+        policy.id
+    );
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/admission.rs b/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/admission.rs
new file mode 100644
index 0000000000..a30936a1b9
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/admission.rs
@@ -0,0 +1,850 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, OverlayBackendLowering,
+    OverlayIntrinsic, RuntimeValidation, TargetSelectorBinding, Tcgen05, Tcgen05Admission,
+    Tcgen05CpGroup, Tcgen05MmaBUsage, Tcgen05MmaForm, Tcgen05Operation, Tcgen05SourceContract,
+};
+use crate::ptx::InstructionPattern;
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use super::*;
+use crate::resolve::abi_ledger::*;
+use crate::resolve::guards::*;
+use crate::resolve::targets::*;
+
+pub(in crate::resolve) fn expand_tcgen05_admission(
+    admission: &Tcgen05Admission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "tcgen05 runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact tcgen05 admission requires both backend evidence profiles"
+    );
+    let expected = [
+        Tcgen05Operation::Alloc,
+        Tcgen05Operation::Dealloc,
+        Tcgen05Operation::RelinquishAllocPermit,
+        Tcgen05Operation::FenceBeforeThreadSync,
+        Tcgen05Operation::FenceAfterThreadSync,
+        Tcgen05Operation::Commit,
+        Tcgen05Operation::CommitSharedCluster,
+        Tcgen05Operation::MmaWsF16,
+        Tcgen05Operation::MmaF16,
+        Tcgen05Operation::MmaWsBf16,
+        Tcgen05Operation::MmaWsTf32,
+        Tcgen05Operation::CpSmemToTmem,
+        Tcgen05Operation::Ld16x256bX8Pure,
+        Tcgen05Operation::Ld16x256bPure,
+        Tcgen05Operation::LoadWait,
+        Tcgen05Operation::StoreWait,
+        Tcgen05Operation::AllocCg2,
+        Tcgen05Operation::DeallocCg2,
+        Tcgen05Operation::RelinquishAllocPermitCg2,
+        Tcgen05Operation::MmaF16Cg2,
+        Tcgen05Operation::CommitCg2,
+        Tcgen05Operation::CommitSharedClusterCg2,
+        Tcgen05Operation::CommitMulticastCg2,
+        Tcgen05Operation::CpSmemToTmemCg2,
+        Tcgen05Operation::CommitMulticast,
+        Tcgen05Operation::ShiftDown,
+        Tcgen05Operation::ShiftDownCg2,
+    ];
+    let has_control_variants = admission.variants.iter().any(|variant| {
+        matches!(
+            variant.operation,
+            Tcgen05Operation::CommitMulticast
+                | Tcgen05Operation::ShiftDown
+                | Tcgen05Operation::ShiftDownCg2
+        )
+    });
+    if has_control_variants {
+        ensure!(
+            admission
+                .control_llvm_evidence_profile
+                .as_deref()
+                .is_some_and(|profile| !profile.trim().is_empty())
+                && admission
+                    .control_libnvvm_evidence_profile
+                    .as_deref()
+                    .is_some_and(|profile| !profile.trim().is_empty()),
+            "compact tcgen05 control admission requires both backend evidence profiles"
+        );
+    }
+    let expected = if has_control_variants {
+        &expected[..]
+    } else {
+        &expected[..24]
+    };
+    ensure!(
+        admission
+            .variants
+            .iter()
+            .map(|variant| variant.operation)
+            .eq(expected.iter().copied()),
+        "compact tcgen05 admission must list all 24 base operations or all 27 current operations in canonical order"
+    );
+
+    let mut records = admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = tcgen05_recipe(variant.operation);
+            let control = matches!(
+                variant.operation,
+                Tcgen05Operation::CommitMulticast
+                    | Tcgen05Operation::ShiftDown
+                    | Tcgen05Operation::ShiftDownCg2
+            );
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must keep reserved ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: variant.abi_id.clone(),
+                operation_key: recipe.operation_key.into(),
+                family: "tcgen05".into(),
+                source: None,
+                source_record: Some(recipe.source_record.into()),
+                rust_module: "tcgen05".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments: recipe
+                    .rust_arguments
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                rust_result: recipe.rust_result.into(),
+                safe: recipe.safe,
+                must_use: false,
+                safe_allowlist_reason: recipe.safe_reason.map(Into::into),
+                public_rust_path: format!("cuda_intrinsics::tcgen05::{}", recipe.id),
+                compatibility_rust_paths: vec![format!("cuda_device::tcgen05::{}", recipe.id)],
+                dialect_op_type: recipe.dialect_op_type.into(),
+                dialect_op_name: recipe.dialect_op_name.into(),
+                dialect_operands: recipe
+                    .dialect_operands
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                dialect_results: recipe
+                    .dialect_results
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                llvm_symbol: Some(recipe.llvm_symbol.into()),
+                resolved_llvm_symbol: None,
+                llvm_arguments: recipe
+                    .llvm_arguments
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                llvm_results: recipe
+                    .llvm_results
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                pure: false,
+                memory: recipe.memory.into(),
+                convergent: true,
+                execution_scope: recipe.operation.execution_scope().into(),
+                minimum_ptx: "8.6".into(),
+                minimum_sm: None,
+                ptx_result: recipe.rust_result.into(),
+                targets: TCGEN05_LLVM_TARGETS.into(),
+                ptx_isa_version: "8.6".into(),
+                ptx_isa_section: "Tensor Memory tcgen05 instructions".into(),
+                ptx_isa_url:
+                    "https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-memory".into(),
+                lowering: "generated_tcgen05".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: if control {
+                            admission
+                                .control_llvm_evidence_profile
+                                .as_ref()
+                                .expect("validated tcgen05 control LLVM evidence profile")
+                                .clone()
+                        } else {
+                            admission.llvm_evidence_profile.clone()
+                        },
+                        targets: None,
+                        minimum_ptx: Some("8.6".into()),
+                        minimum_sm: None,
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: if control {
+                            admission
+                                .control_libnvvm_evidence_profile
+                                .as_ref()
+                                .expect("validated tcgen05 control libNVVM evidence profile")
+                                .clone()
+                        } else {
+                            admission.libnvvm_evidence_profile.clone()
+                        },
+                        targets: Some(TCGEN05_LIBNVVM_TARGETS.into()),
+                        minimum_ptx: Some("8.6".into()),
+                        minimum_sm: None,
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: Some(Tcgen05 {
+                    operation: recipe.operation,
+                    cp: None,
+                    ld: None,
+                    st: None,
+                    mma: None,
+                    adapter: recipe.adapter,
+                    source_contract: recipe.source_contract,
+                    runtime_validation: admission.runtime_validation,
+                }),
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: "tcgen05".into(),
+                    modifiers: recipe.modifiers,
+                    operands: recipe.operands,
+                },
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect::<Result<Vec<_>>>()?;
+
+    if admission.cp_variants.is_empty() {
+        ensure!(
+            admission.cp_llvm_evidence_profile.is_none()
+                && admission.cp_libnvvm_evidence_profile.is_none(),
+            "tcgen05 copy evidence profiles require admitted copy variants"
+        );
+    } else {
+        ensure!(
+            [
+                Tcgen05MmaBUsage::Discard,
+                Tcgen05MmaBUsage::LastUse,
+                Tcgen05MmaBUsage::Fill,
+                Tcgen05MmaBUsage::Use,
+            ]
+            .map(Tcgen05MmaBUsage::selector_value)
+                == [0, 1, 2, 3],
+            "tcgen05 MMA B-usage selector mapping changed"
+        );
+        ensure!(
+            admission
+                .cp_llvm_evidence_profile
+                .as_deref()
+                .is_some_and(|profile| !profile.trim().is_empty())
+                && admission
+                    .cp_libnvvm_evidence_profile
+                    .as_deref()
+                    .is_some_and(|profile| !profile.trim().is_empty()),
+            "compact tcgen05 copy admission requires both backend evidence profiles"
+        );
+
+        use Tcgen05CpGroup::{Cg1, Cg2};
+        let expected_cp = TCGEN05_CP_MEMBERS
+            .into_iter()
+            .flat_map(|member| [Cg1, Cg2].into_iter().map(move |group| (member, group)))
+            .collect::<Vec<_>>();
+        ensure!(
+            admission
+                .cp_variants
+                .iter()
+                .map(|variant| (variant.member, variant.group))
+                .eq(expected_cp),
+            "compact tcgen05 copy admission must list all 34 variants in canonical order"
+        );
+        for variant in &admission.cp_variants {
+            validate_abi_id(&variant.abi_id)?;
+            let base_id = if variant.group == Cg1 {
+                "tcgen05_cp_smem_to_tmem"
+            } else {
+                "tcgen05_cp_smem_to_tmem_cg2"
+            };
+            let base = records
+                .iter()
+                .find(|record| record.id == base_id)
+                .unwrap()
+                .clone();
+            records.push(materialize_tcgen05_cp_variant(&base, admission, variant));
+        }
+    }
+
+    if admission.ld_variants.is_empty() {
+        ensure!(
+            admission.ld_llvm_evidence_profile.is_none()
+                && admission.ld_libnvvm_evidence_profile.is_none(),
+            "tcgen05 load evidence profiles require admitted load variants"
+        );
+    } else {
+        ensure!(
+            admission
+                .ld_llvm_evidence_profile
+                .as_deref()
+                .is_some_and(|profile| !profile.trim().is_empty())
+                && admission
+                    .ld_libnvvm_evidence_profile
+                    .as_deref()
+                    .is_some_and(|profile| !profile.trim().is_empty()),
+            "compact tcgen05 load admission requires both backend evidence profiles"
+        );
+        let expected_ld = TCGEN05_LD_VARIANTS
+            .into_iter()
+            .flat_map(|(shape, multiplicity)| {
+                [false, true]
+                    .into_iter()
+                    .map(move |pack16| (shape, multiplicity, pack16))
+            })
+            .collect::<Vec<_>>();
+        ensure!(
+            admission
+                .ld_variants
+                .iter()
+                .map(|variant| (variant.shape, variant.multiplicity, variant.pack16))
+                .eq(expected_ld),
+            "compact tcgen05 load admission must list all 58 variants in canonical order"
+        );
+        let base = records
+            .iter()
+            .find(|record| record.id == "tcgen05_ld_16x256b_pure")
+            .expect("closed tcgen05 load base")
+            .clone();
+        let first_load = records.len();
+        for variant in &admission.ld_variants {
+            validate_abi_id(&variant.abi_id)?;
+            records.push(materialize_tcgen05_ld_variant(&base, admission, variant));
+        }
+        for pair in records[first_load..].chunks_exact(2) {
+            let raw = pair[0].tcgen05.as_ref().and_then(|tcgen05| tcgen05.ld);
+            let packed = pair[1].tcgen05.as_ref().and_then(|tcgen05| tcgen05.ld);
+            ensure!(
+                raw.is_some_and(|ld| !ld.pack16)
+                    && packed.is_some_and(|ld| ld.pack16)
+                    && raw.map(|mut ld| {
+                        ld.pack16 = true;
+                        ld
+                    }) == packed
+                    && pair[0].source_record == pair[1].source_record
+                    && pair[0].llvm_symbol == pair[1].llvm_symbol,
+                "tcgen05 load source sharing must pair raw and pack16 leaves"
+            );
+        }
+    }
+
+    if admission.st_variants.is_empty() {
+        ensure!(
+            admission.st_llvm_evidence_profile.is_none()
+                && admission.st_libnvvm_evidence_profile.is_none(),
+            "tcgen05 store evidence profiles require admitted store variants"
+        );
+    } else {
+        ensure!(
+            admission
+                .st_llvm_evidence_profile
+                .as_deref()
+                .is_some_and(|profile| !profile.trim().is_empty())
+                && admission
+                    .st_libnvvm_evidence_profile
+                    .as_deref()
+                    .is_some_and(|profile| !profile.trim().is_empty()),
+            "compact tcgen05 store admission requires both backend evidence profiles"
+        );
+        let expected_st = TCGEN05_ST_VARIANTS
+            .into_iter()
+            .flat_map(|(shape, multiplicity)| {
+                [false, true]
+                    .into_iter()
+                    .map(move |unpack16| (shape, multiplicity, unpack16))
+            })
+            .collect::<Vec<_>>();
+        ensure!(
+            admission
+                .st_variants
+                .iter()
+                .map(|variant| (variant.shape, variant.multiplicity, variant.unpack16))
+                .eq(expected_st),
+            "compact tcgen05 store admission must list all 58 variants in canonical order"
+        );
+        let base = records
+            .iter()
+            .find(|record| record.id == "tcgen05_ld_16x256b_pure")
+            .expect("closed tcgen05 store base")
+            .clone();
+        let first_store = records.len();
+        for variant in &admission.st_variants {
+            validate_abi_id(&variant.abi_id)?;
+            records.push(materialize_tcgen05_st_variant(&base, admission, variant));
+        }
+        for pair in records[first_store..].chunks_exact(2) {
+            let raw = pair[0].tcgen05.as_ref().and_then(|tcgen05| tcgen05.st);
+            let unpacked = pair[1].tcgen05.as_ref().and_then(|tcgen05| tcgen05.st);
+            ensure!(
+                raw.is_some_and(|st| !st.unpack16)
+                    && unpacked.is_some_and(|st| st.unpack16)
+                    && raw.map(|mut st| {
+                        st.unpack16 = true;
+                        st
+                    }) == unpacked
+                    && pair[0].source_record == pair[1].source_record
+                    && pair[0].llvm_symbol == pair[1].llvm_symbol,
+                "tcgen05 store source sharing must pair raw and unpack16 leaves"
+            );
+        }
+    }
+
+    if admission.ld_offset_variants.is_empty() && admission.st_offset_variants.is_empty() {
+        ensure!(
+            admission.offset_llvm_evidence_profile.is_none()
+                && admission.offset_libnvvm_evidence_profile.is_none(),
+            "tcgen05 offset evidence profiles require admitted offset load/store variants"
+        );
+    } else {
+        ensure!(
+            admission
+                .offset_llvm_evidence_profile
+                .as_deref()
+                .is_some_and(|profile| !profile.trim().is_empty())
+                && admission
+                    .offset_libnvvm_evidence_profile
+                    .as_deref()
+                    .is_some_and(|profile| !profile.trim().is_empty()),
+            "compact tcgen05 offset admission requires both backend evidence profiles"
+        );
+        let expected_ld = TCGEN05_OFFSET_LDST_VARIANTS
+            .into_iter()
+            .flat_map(|(shape, multiplicity)| {
+                [false, true]
+                    .into_iter()
+                    .map(move |pack16| (shape, multiplicity, pack16))
+            })
+            .collect::<Vec<_>>();
+        ensure!(
+            admission
+                .ld_offset_variants
+                .iter()
+                .map(|variant| (variant.shape, variant.multiplicity, variant.pack16))
+                .eq(expected_ld),
+            "compact tcgen05 offset load admission must list all 16 variants in canonical order"
+        );
+        let expected_st = TCGEN05_OFFSET_LDST_VARIANTS
+            .into_iter()
+            .flat_map(|(shape, multiplicity)| {
+                [false, true]
+                    .into_iter()
+                    .map(move |unpack16| (shape, multiplicity, unpack16))
+            })
+            .collect::<Vec<_>>();
+        ensure!(
+            admission
+                .st_offset_variants
+                .iter()
+                .map(|variant| (variant.shape, variant.multiplicity, variant.unpack16))
+                .eq(expected_st),
+            "compact tcgen05 offset store admission must list all 16 variants in canonical order"
+        );
+
+        let base = records
+            .iter()
+            .find(|record| record.id == "tcgen05_ld_16x256b_pure")
+            .expect("closed tcgen05 offset load/store base")
+            .clone();
+        let first_load = records.len();
+        for variant in &admission.ld_offset_variants {
+            validate_abi_id(&variant.abi_id)?;
+            records.push(materialize_tcgen05_ld_variant(&base, admission, variant));
+        }
+        for pair in records[first_load..].chunks_exact(2) {
+            let raw = pair[0].tcgen05.as_ref().and_then(|tcgen05| tcgen05.ld);
+            let packed = pair[1].tcgen05.as_ref().and_then(|tcgen05| tcgen05.ld);
+            ensure!(
+                raw.is_some_and(|ld| !ld.pack16)
+                    && packed.is_some_and(|ld| ld.pack16)
+                    && raw.map(|mut ld| {
+                        ld.pack16 = true;
+                        ld
+                    }) == packed
+                    && pair[0].source_record == pair[1].source_record
+                    && pair[0].llvm_symbol == pair[1].llvm_symbol,
+                "tcgen05 offset load source sharing must pair raw and pack16 leaves"
+            );
+        }
+
+        let first_store = records.len();
+        for variant in &admission.st_offset_variants {
+            validate_abi_id(&variant.abi_id)?;
+            records.push(materialize_tcgen05_st_variant(&base, admission, variant));
+        }
+        for pair in records[first_store..].chunks_exact(2) {
+            let raw = pair[0].tcgen05.as_ref().and_then(|tcgen05| tcgen05.st);
+            let unpacked = pair[1].tcgen05.as_ref().and_then(|tcgen05| tcgen05.st);
+            ensure!(
+                raw.is_some_and(|st| !st.unpack16)
+                    && unpacked.is_some_and(|st| st.unpack16)
+                    && raw.map(|mut st| {
+                        st.unpack16 = true;
+                        st
+                    }) == unpacked
+                    && pair[0].source_record == pair[1].source_record
+                    && pair[0].llvm_symbol == pair[1].llvm_symbol,
+                "tcgen05 offset store source sharing must pair raw and unpack16 leaves"
+            );
+        }
+    }
+
+    if admission.mma_variants.is_empty() {
+        ensure!(
+            admission.mma_llvm_evidence_profile.is_none()
+                && admission.mma_libnvvm_evidence_profile.is_none()
+                && admission.mma_llvm_target_contracts.is_empty()
+                && admission.mma_libnvvm_target_contracts.is_empty(),
+            "tcgen05 MMA profiles and target contracts require admitted variants"
+        );
+    } else {
+        ensure!(
+            admission
+                .mma_llvm_evidence_profile
+                .as_deref()
+                .is_some_and(|profile| !profile.trim().is_empty())
+                && admission
+                    .mma_libnvvm_evidence_profile
+                    .as_deref()
+                    .is_some_and(|profile| !profile.trim().is_empty()),
+            "compact tcgen05 MMA admission requires both backend evidence profiles"
+        );
+        let expected_variants = TCGEN05_MMA_FORMS
+            .into_iter()
+            .map(|form| (form, None))
+            .chain(
+                TCGEN05_MMA_ALIASES
+                    .into_iter()
+                    .map(|alias| (Tcgen05MmaForm::WsTensor, Some(alias))),
+            )
+            .chain(
+                TCGEN05_MMA_ALIASES
+                    .into_iter()
+                    .map(|alias| (Tcgen05MmaForm::Shared, Some(alias))),
+            )
+            .collect::<Vec<_>>();
+        ensure!(
+            admission
+                .mma_variants
+                .iter()
+                .map(|variant| (variant.form, variant.alias))
+                .eq(expected_variants),
+            "compact tcgen05 MMA admission must list all 24 APIs in canonical order"
+        );
+        for variant in &admission.mma_variants {
+            validate_abi_id(&variant.abi_id)?;
+        }
+        let expected_llvm = expected_tcgen05_mma_target_contracts(IntrinsicBackend::LlvmNvptx);
+        let expected_libnvvm = expected_tcgen05_mma_target_contracts(IntrinsicBackend::LibNvvm);
+        ensure!(
+            admission.mma_llvm_target_contracts == expected_llvm
+                && admission.mma_libnvvm_target_contracts == expected_libnvvm,
+            "tcgen05 MMA target contracts changed from the reviewed backend matrices"
+        );
+        let llvm_target =
+            resolve_target_contracts("tcgen05 MMA LLVM", &admission.mma_llvm_target_contracts)?;
+        let libnvvm_target = resolve_target_contracts(
+            "tcgen05 MMA libNVVM",
+            &admission.mma_libnvvm_target_contracts,
+        )?;
+        let fixed_selector = [TargetSelectorBinding {
+            name: "kind".into(),
+            value: "f8f6f4".into(),
+        }];
+        let fixed_llvm = resolve_target_contract(
+            "tcgen05 MMA LLVM alias",
+            &fixed_selector,
+            &admission.mma_llvm_target_contracts,
+        )?;
+        let fixed_libnvvm = resolve_target_contract(
+            "tcgen05 MMA libNVVM alias",
+            &fixed_selector,
+            &admission.mma_libnvvm_target_contracts,
+        )?;
+        for variant in &admission.mma_variants {
+            let (llvm, libnvvm) = if variant.alias.is_some() {
+                (&fixed_llvm, &fixed_libnvvm)
+            } else {
+                (&llvm_target, &libnvvm_target)
+            };
+            records.push(materialize_tcgen05_mma_variant(
+                admission, variant, llvm, libnvvm,
+            ));
+        }
+    }
+    Ok(records)
+}
+
+pub(in crate::resolve) fn validate_tcgen05_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let tcgen05 = policy
+        .tcgen05
+        .as_ref()
+        .with_context(|| format!("{} has no closed tcgen05 contract", policy.id))?;
+    if let Some(mma) = &tcgen05.mma {
+        return validate_tcgen05_mma_policy(policy, declaration, tcgen05, mma);
+    }
+    if let Some(ld) = tcgen05.ld {
+        return validate_tcgen05_ld_policy(policy, declaration, tcgen05, ld);
+    }
+    if let Some(st) = tcgen05.st {
+        return validate_tcgen05_st_policy(policy, declaration, tcgen05, st);
+    }
+    if let Some(cp) = tcgen05.cp {
+        return validate_tcgen05_cp_policy(policy, declaration, tcgen05, cp);
+    }
+    ensure!(
+        !matches!(
+            tcgen05.operation,
+            Tcgen05Operation::Ld | Tcgen05Operation::St | Tcgen05Operation::Mma
+        ),
+        "{} has a tcgen05 load/store/MMA operation without its closed identity",
+        policy.id
+    );
+    let recipe = tcgen05_recipe(tcgen05.operation);
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none()
+            && declaration.source_record == recipe.source_record
+            && declaration.llvm_name == recipe.llvm_symbol,
+        "{} tcgen05 identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "tcgen05"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == recipe.rust_arguments
+            && policy.rust_result == recipe.rust_result
+            && policy.safe == recipe.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.as_deref() == recipe.safe_reason
+            && policy.public_rust_path == format!("cuda_intrinsics::tcgen05::{}", recipe.id)
+            && policy.compatibility_rust_paths == [format!("cuda_device::tcgen05::{}", recipe.id)],
+        "{} tcgen05 Rust API changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == recipe.dialect_operands
+            && policy.dialect_results == recipe.dialect_results
+            && policy.llvm_arguments == recipe.llvm_arguments
+            && policy.llvm_results == recipe.llvm_results
+            && declaration.arguments == recipe.llvm_arguments
+            && declaration.results == recipe.llvm_results
+            && declaration.classes == recipe.imported_classes
+            && declaration.properties == recipe.imported_properties
+            && policy.lowering == "generated_tcgen05",
+        "{} tcgen05 carrier or imported declaration changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == recipe.memory
+            && policy.convergent
+            && policy.execution_scope == recipe.operation.execution_scope()
+            && tcgen05.ld.is_none()
+            && tcgen05.st.is_none()
+            && tcgen05.adapter == recipe.adapter
+            && tcgen05.source_contract == recipe.source_contract
+            && tcgen05.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} tcgen05 semantics changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == "8.6"
+            && policy.minimum_sm.is_none()
+            && policy.targets == TCGEN05_LLVM_TARGETS
+            && policy.ptx_isa_version == "8.6"
+            && policy.ptx_result == recipe.rust_result
+            && policy.expected_ptx.mnemonic == "tcgen05"
+            && policy.expected_ptx.modifiers == recipe.modifiers
+            && policy.expected_ptx.operands == recipe.operands,
+        "{} tcgen05 target or PTX contract changed",
+        policy.id
+    );
+    validate_tcgen05_backend_routes(policy, "tcgen05")?;
+    validate_tcgen05_source_contract(&recipe, declaration)?;
+    ensure_no_other_family_contract(policy, "tcgen05")?;
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_tcgen05_backend_routes(
+    policy: &OverlayIntrinsic,
+    family: &str,
+) -> Result<()> {
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && policy.backend_lowerings[0].backend == IntrinsicBackend::LlvmNvptx
+            && policy.backend_lowerings[1].backend == IntrinsicBackend::LibNvvm
+            && policy.backend_lowerings[0].targets.is_none()
+            && policy.backend_lowerings[1].targets.as_deref() == Some(TCGEN05_LIBNVVM_TARGETS)
+            && policy.backend_lowerings.iter().all(|route| {
+                route.mechanism == BackendLoweringMechanism::InlinePtx
+                    && route.minimum_ptx.as_deref() == Some("8.6")
+                    && route.minimum_sm.is_none()
+                    && !route.evidence_profile.trim().is_empty()
+            }),
+        "{} {family} backend route changed",
+        policy.id
+    );
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_tcgen05_source_contract(
+    recipe: &Tcgen05Recipe,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    match recipe.source_contract {
+        Tcgen05SourceContract::ExactTablegenSelection => {
+            ensure!(
+                declaration.selections.len() == 1,
+                "{} must keep one exact tcgen05 selection",
+                recipe.id
+            );
+            let selection = &declaration.selections[0];
+            let expected_predicate = if matches!(
+                recipe.operation,
+                Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2
+            ) {
+                "Subtarget->hasTcgen05ShiftSupport()"
+            } else {
+                "Subtarget->hasTcgen05InstSupport()"
+            };
+            ensure!(
+                recipe.selection_record == Some(selection.source_record.as_str())
+                    && recipe.selection_asm == Some(selection.asm.as_str())
+                    && selection.predicates == [expected_predicate]
+                    && selection.constraints.is_empty(),
+                "{} exact tcgen05 selection changed",
+                recipe.id
+            );
+        }
+        Tcgen05SourceContract::TablegenSelectionChangesPtx
+            if matches!(
+                recipe.operation,
+                Tcgen05Operation::Commit | Tcgen05Operation::CommitCg2
+            ) =>
+        {
+            ensure!(
+                declaration.selections.len() == 1,
+                "{} must keep one canonical commit selection",
+                recipe.id
+            );
+            let selection = &declaration.selections[0];
+            ensure!(
+                recipe.selection_record == Some(selection.source_record.as_str())
+                    && recipe.selection_asm == Some(selection.asm.as_str())
+                    && selection.predicates == ["Subtarget->hasTcgen05InstSupport()"]
+                    && selection.constraints.is_empty()
+                    && !recipe.operands.is_empty(),
+                "{} canonical commit selection changed",
+                recipe.id
+            );
+        }
+        Tcgen05SourceContract::TablegenSelectionChangesPtx => {
+            ensure!(
+                declaration.selections.len() == 64,
+                "{} must keep the 64 collector selections",
+                recipe.id
+            );
+            let actual = declaration
+                .selections
+                .iter()
+                .map(|selection| {
+                    ensure!(
+                        selection.constraints.is_empty(),
+                        "{} collector selection gained constraints",
+                        recipe.id
+                    );
+                    let predicate = if selection.asm.contains(".kind::i8.") {
+                        "Subtarget->hasTcgen05MMAI8Kind()"
+                    } else {
+                        "Subtarget->hasTcgen05InstSupport()"
+                    };
+                    ensure!(
+                        selection.predicates == [predicate],
+                        "{} collector predicate changed",
+                        recipe.id
+                    );
+                    Ok(selection.asm.clone())
+                })
+                .collect::<Result<BTreeSet<_>>>()?;
+            let expected = ["f16", "tf32", "f8f6f4", "i8"]
+                .into_iter()
+                .flat_map(|kind| {
+                    ["b0", "b1", "b2", "b3"].into_iter().flat_map(move |collector| {
+                        ["discard", "fill", "use", "lastuse"].into_iter().map(move |action| {
+                            format!("tcgen05.mma.ws.cta_group::1.kind::{kind}.collector::{collector}::{action} [$dtmem], [$a], $b, $idesc, $enable_inp_d;")
+                        })
+                    })
+                })
+                .collect::<BTreeSet<_>>();
+            ensure!(
+                actual == expected,
+                "{} collector selection matrix changed",
+                recipe.id
+            );
+        }
+        Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection => ensure!(
+            declaration.selections.is_empty(),
+            "{} unexpectedly gained a TableGen selection; review the backend route",
+            recipe.id
+        ),
+    }
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/ldst_cp.rs b/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/ldst_cp.rs
new file mode 100644
index 0000000000..ae64dc496b
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/ldst_cp.rs
@@ -0,0 +1,1081 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    ImportedIntrinsic, OverlayIntrinsic, RuntimeValidation, Tcgen05, Tcgen05Adapter,
+    Tcgen05Admission, Tcgen05Cp, Tcgen05CpAdmissionVariant, Tcgen05CpGroup, Tcgen05CpMember,
+    Tcgen05Ld, Tcgen05LdAdmissionVariant, Tcgen05LdMultiplicity, Tcgen05LdShape, Tcgen05Operation,
+    Tcgen05SourceContract, Tcgen05St, Tcgen05StAdmissionVariant,
+};
+use crate::ptx::OperandPattern;
+use anyhow::{Result, ensure};
+
+use super::*;
+use crate::resolve::guards::*;
+
+pub(in crate::resolve) struct Tcgen05CpMemberRecipe {
+    pub(in crate::resolve) llvm_suffix: &'static str,
+    pub(in crate::resolve) ptx_suffix: &'static str,
+    pub(in crate::resolve) op_suffix: &'static str,
+    pub(in crate::resolve) selection_stem: &'static str,
+}
+
+pub(in crate::resolve) const TCGEN05_CP_MEMBERS: [Tcgen05CpMember; 17] = [
+    Tcgen05CpMember::M128x128bB4x16P64,
+    Tcgen05CpMember::M128x128bB6x16P32,
+    Tcgen05CpMember::M128x128b,
+    Tcgen05CpMember::M128x256bB4x16P64,
+    Tcgen05CpMember::M128x256bB6x16P32,
+    Tcgen05CpMember::M32x128bWarpx4B4x16P64,
+    Tcgen05CpMember::M32x128bWarpx4B6x16P32,
+    Tcgen05CpMember::M32x128bWarpx4,
+    Tcgen05CpMember::M4x256bB4x16P64,
+    Tcgen05CpMember::M4x256bB6x16P32,
+    Tcgen05CpMember::M4x256b,
+    Tcgen05CpMember::M64x128bWarpx2Pair0123B4x16P64,
+    Tcgen05CpMember::M64x128bWarpx2Pair0123B6x16P32,
+    Tcgen05CpMember::M64x128bWarpx2Pair0123,
+    Tcgen05CpMember::M64x128bWarpx2Pair0213B4x16P64,
+    Tcgen05CpMember::M64x128bWarpx2Pair0213B6x16P32,
+    Tcgen05CpMember::M64x128bWarpx2Pair0213,
+];
+
+pub(in crate::resolve) fn tcgen05_cp_member_recipe(
+    member: Tcgen05CpMember,
+) -> Tcgen05CpMemberRecipe {
+    use Tcgen05CpMember::*;
+    let (llvm_suffix, ptx_suffix, op_suffix, selection_stem) = match member {
+        M128x128bB4x16P64 => (
+            "128x128b.b4x16_p64",
+            "128x128b.b8x16.b4x16_p64",
+            "128x128bB4x16P64",
+            "128x128bb4x16_p64",
+        ),
+        M128x128bB6x16P32 => (
+            "128x128b.b6x16_p32",
+            "128x128b.b8x16.b6x16_p32",
+            "128x128bB6x16P32",
+            "128x128bb6x16_p32",
+        ),
+        M128x128b => ("128x128b", "128x128b", "128x128b", "128x128b"),
+        M128x256bB4x16P64 => (
+            "128x256b.b4x16_p64",
+            "128x256b.b8x16.b4x16_p64",
+            "128x256bB4x16P64",
+            "128x256bb4x16_p64",
+        ),
+        M128x256bB6x16P32 => (
+            "128x256b.b6x16_p32",
+            "128x256b.b8x16.b6x16_p32",
+            "128x256bB6x16P32",
+            "128x256bb6x16_p32",
+        ),
+        M32x128bWarpx4B4x16P64 => (
+            "32x128b_warpx4.b4x16_p64",
+            "32x128b.warpx4.b8x16.b4x16_p64",
+            "32x128bWarpx4B4x16P64",
+            "32x128b4x16_p64",
+        ),
+        M32x128bWarpx4B6x16P32 => (
+            "32x128b_warpx4.b6x16_p32",
+            "32x128b.warpx4.b8x16.b6x16_p32",
+            "32x128bWarpx4B6x16P32",
+            "32x128b6x16_p32",
+        ),
+        M32x128bWarpx4 => (
+            "32x128b_warpx4",
+            "32x128b.warpx4",
+            "32x128bWarpx4",
+            "32x128",
+        ),
+        M4x256bB4x16P64 => (
+            "4x256b.b4x16_p64",
+            "4x256b.b8x16.b4x16_p64",
+            "4x256bB4x16P64",
+            "4x256bb4x16_p64",
+        ),
+        M4x256bB6x16P32 => (
+            "4x256b.b6x16_p32",
+            "4x256b.b8x16.b6x16_p32",
+            "4x256bB6x16P32",
+            "4x256bb6x16_p32",
+        ),
+        M4x256b => ("4x256b", "4x256b", "4x256b", "4x256b"),
+        M64x128bWarpx2Pair0123B4x16P64 => (
+            "64x128b_warpx2_01_23.b4x16_p64",
+            "64x128b.warpx2::01_23.b8x16.b4x16_p64",
+            "64x128bWarpx2Pair0123B4x16P64",
+            "64x128_2b4x16_p64",
+        ),
+        M64x128bWarpx2Pair0123B6x16P32 => (
+            "64x128b_warpx2_01_23.b6x16_p32",
+            "64x128b.warpx2::01_23.b8x16.b6x16_p32",
+            "64x128bWarpx2Pair0123B6x16P32",
+            "64x128_2b6x16_p32",
+        ),
+        M64x128bWarpx2Pair0123 => (
+            "64x128b_warpx2_01_23",
+            "64x128b.warpx2::01_23",
+            "64x128bWarpx2Pair0123",
+            "64x128_2",
+        ),
+        M64x128bWarpx2Pair0213B4x16P64 => (
+            "64x128b_warpx2_02_13.b4x16_p64",
+            "64x128b.warpx2::02_13.b8x16.b4x16_p64",
+            "64x128bWarpx2Pair0213B4x16P64",
+            "64x128_1b4x16_p64",
+        ),
+        M64x128bWarpx2Pair0213B6x16P32 => (
+            "64x128b_warpx2_02_13.b6x16_p32",
+            "64x128b.warpx2::02_13.b8x16.b6x16_p32",
+            "64x128bWarpx2Pair0213B6x16P32",
+            "64x128_1b6x16_p32",
+        ),
+        M64x128bWarpx2Pair0213 => (
+            "64x128b_warpx2_02_13",
+            "64x128b.warpx2::02_13",
+            "64x128bWarpx2Pair0213",
+            "64x128_1",
+        ),
+    };
+    Tcgen05CpMemberRecipe {
+        llvm_suffix,
+        ptx_suffix,
+        op_suffix,
+        selection_stem,
+    }
+}
+
+pub(in crate::resolve) fn materialize_tcgen05_cp_variant(
+    base: &OverlayIntrinsic,
+    admission: &Tcgen05Admission,
+    variant: &Tcgen05CpAdmissionVariant,
+) -> OverlayIntrinsic {
+    let recipe = tcgen05_cp_member_recipe(variant.member);
+    let group = match variant.group {
+        Tcgen05CpGroup::Cg1 => 1,
+        Tcgen05CpGroup::Cg2 => 2,
+    };
+    let group_suffix = if group == 1 { "" } else { "_cg2" };
+    let id_suffix = recipe.llvm_suffix.replace('.', "_");
+    let id = format!("tcgen05_cp_{id_suffix}{group_suffix}");
+    let mut record = base.clone();
+    record.id = id.clone();
+    record.abi_id = variant.abi_id.clone();
+    record.operation_key = format!("tcgen05.cp.{}.cg{group}", recipe.llvm_suffix);
+    record.source_record = Some(format!("int_nvvm_tcgen05_cp_{}_cg{group}", id_suffix));
+    record.rust_name = id.clone();
+    record.public_rust_path = format!("cuda_intrinsics::tcgen05::{id}");
+    record.compatibility_rust_paths = vec![format!("cuda_device::tcgen05::{id}")];
+    record.dialect_op_type = format!(
+        "Tcgen05Cp{}{}Op",
+        recipe.op_suffix,
+        if group == 1 { "" } else { "Cg2" }
+    );
+    record.dialect_op_name = format!("nvvm.{id}");
+    record.llvm_symbol = Some(format!(
+        "llvm.nvvm.tcgen05.cp.{}.cg{group}",
+        recipe.llvm_suffix
+    ));
+    record.backend_lowerings[0].evidence_profile = admission
+        .cp_llvm_evidence_profile
+        .as_ref()
+        .expect("validated tcgen05 copy LLVM evidence profile")
+        .clone();
+    record.backend_lowerings[1].evidence_profile = admission
+        .cp_libnvvm_evidence_profile
+        .as_ref()
+        .expect("validated tcgen05 copy libNVVM evidence profile")
+        .clone();
+    record.tcgen05 = Some(Tcgen05 {
+        operation: if group == 1 {
+            Tcgen05Operation::CpSmemToTmem
+        } else {
+            Tcgen05Operation::CpSmemToTmemCg2
+        },
+        cp: Some(Tcgen05Cp {
+            member: variant.member,
+            group: variant.group,
+        }),
+        ld: None,
+        st: None,
+        mma: None,
+        adapter: Tcgen05Adapter::TmemDescriptorToVoid,
+        source_contract: Tcgen05SourceContract::ExactTablegenSelection,
+        runtime_validation: admission.runtime_validation,
+    });
+    record.expected_ptx.modifiers = std::iter::once("cp".into())
+        .chain(std::iter::once(format!("cta_group::{group}")))
+        .chain(recipe.ptx_suffix.split('.').map(Into::into))
+        .collect();
+    record.summary = format!(
+        "Copies one {} tile from shared memory to tensor memory.",
+        recipe.ptx_suffix
+    );
+    record
+}
+
+pub(in crate::resolve) const TCGEN05_LD_VARIANTS: [(Tcgen05LdShape, Tcgen05LdMultiplicity); 29] = {
+    use Tcgen05LdMultiplicity::*;
+    use Tcgen05LdShape::*;
+    [
+        (M16x64b, X1),
+        (M16x64b, X2),
+        (M16x64b, X4),
+        (M16x64b, X8),
+        (M16x64b, X16),
+        (M16x64b, X32),
+        (M16x64b, X64),
+        (M16x64b, X128),
+        (M16x128b, X1),
+        (M16x128b, X2),
+        (M16x128b, X4),
+        (M16x128b, X8),
+        (M16x128b, X16),
+        (M16x128b, X32),
+        (M16x128b, X64),
+        (M16x256b, X1),
+        (M16x256b, X2),
+        (M16x256b, X4),
+        (M16x256b, X8),
+        (M16x256b, X16),
+        (M16x256b, X32),
+        (M32x32b, X1),
+        (M32x32b, X2),
+        (M32x32b, X4),
+        (M32x32b, X8),
+        (M32x32b, X16),
+        (M32x32b, X32),
+        (M32x32b, X64),
+        (M32x32b, X128),
+    ]
+};
+
+pub(in crate::resolve) const TCGEN05_OFFSET_LDST_VARIANTS: [(
+    Tcgen05LdShape,
+    Tcgen05LdMultiplicity,
+); 8] = {
+    use Tcgen05LdMultiplicity::*;
+    use Tcgen05LdShape::*;
+    [
+        (M16x32bx2, X1),
+        (M16x32bx2, X2),
+        (M16x32bx2, X4),
+        (M16x32bx2, X8),
+        (M16x32bx2, X16),
+        (M16x32bx2, X32),
+        (M16x32bx2, X64),
+        (M16x32bx2, X128),
+    ]
+};
+
+pub(in crate::resolve) fn tcgen05_ld_shape_name(shape: Tcgen05LdShape) -> &'static str {
+    match shape {
+        Tcgen05LdShape::M16x32bx2 => "16x32bx2",
+        Tcgen05LdShape::M16x64b => "16x64b",
+        Tcgen05LdShape::M16x128b => "16x128b",
+        Tcgen05LdShape::M16x256b => "16x256b",
+        Tcgen05LdShape::M32x32b => "32x32b",
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_ld_multiplicity_name(
+    multiplicity: Tcgen05LdMultiplicity,
+) -> &'static str {
+    match multiplicity {
+        Tcgen05LdMultiplicity::X1 => "x1",
+        Tcgen05LdMultiplicity::X2 => "x2",
+        Tcgen05LdMultiplicity::X4 => "x4",
+        Tcgen05LdMultiplicity::X8 => "x8",
+        Tcgen05LdMultiplicity::X16 => "x16",
+        Tcgen05LdMultiplicity::X32 => "x32",
+        Tcgen05LdMultiplicity::X64 => "x64",
+        Tcgen05LdMultiplicity::X128 => "x128",
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_ld_register_count(ld: Tcgen05Ld) -> usize {
+    ld.shape.register_multiplier() * ld.multiplicity.count()
+}
+
+pub(in crate::resolve) fn tcgen05_ld_id(ld: Tcgen05Ld) -> String {
+    format!(
+        "tcgen05_ld_{}_{}_{}",
+        tcgen05_ld_shape_name(ld.shape),
+        tcgen05_ld_multiplicity_name(ld.multiplicity),
+        if ld.pack16 { "pack16" } else { "raw" }
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_ld_source_record(ld: Tcgen05Ld) -> String {
+    format!(
+        "int_nvvm_tcgen05_ld_{}_{}",
+        tcgen05_ld_shape_name(ld.shape),
+        tcgen05_ld_multiplicity_name(ld.multiplicity)
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_ld_llvm_symbol(ld: Tcgen05Ld) -> String {
+    format!(
+        "llvm.nvvm.tcgen05.ld.{}.{}",
+        tcgen05_ld_shape_name(ld.shape),
+        tcgen05_ld_multiplicity_name(ld.multiplicity)
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_ld_rust_result(ld: Tcgen05Ld) -> String {
+    match tcgen05_ld_register_count(ld) {
+        1 => "u32".into(),
+        count => format!("[u32; {count}]"),
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_ld_llvm_result(ld: Tcgen05Ld) -> String {
+    match tcgen05_ld_register_count(ld) {
+        1 => "i32".into(),
+        count => format!("v{count}i32"),
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_ld_op_type(ld: Tcgen05Ld) -> String {
+    let shape = tcgen05_ld_shape_name(ld.shape);
+    let multiplicity = tcgen05_ld_multiplicity_name(ld.multiplicity)
+        .strip_prefix('x')
+        .unwrap();
+    format!(
+        "Tcgen05Ld{shape}X{multiplicity}{}Op",
+        if ld.pack16 { "Pack16" } else { "Raw" }
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_ld_modifiers(ld: Tcgen05Ld) -> Vec<String> {
+    let mut modifiers = vec![
+        "ld".into(),
+        "sync".into(),
+        "aligned".into(),
+        tcgen05_ld_shape_name(ld.shape).into(),
+        tcgen05_ld_multiplicity_name(ld.multiplicity).into(),
+    ];
+    if ld.pack16 {
+        modifiers.push("pack::16b".into());
+    }
+    modifiers.push("b32".into());
+    modifiers
+}
+
+pub(in crate::resolve) fn tcgen05_ld_operands(ld: Tcgen05Ld) -> Vec<OperandPattern> {
+    let result = OperandPattern::RegisterList {
+        length: tcgen05_ld_register_count(ld),
+    };
+    let mut operands = vec![result, OperandPattern::Address];
+    if ld.shape == Tcgen05LdShape::M16x32bx2 {
+        operands.push(OperandPattern::Immediate);
+    }
+    operands
+}
+
+pub(in crate::resolve) fn materialize_tcgen05_ld_variant(
+    base: &OverlayIntrinsic,
+    admission: &Tcgen05Admission,
+    variant: &Tcgen05LdAdmissionVariant,
+) -> OverlayIntrinsic {
+    let ld = Tcgen05Ld {
+        shape: variant.shape,
+        multiplicity: variant.multiplicity,
+        pack16: variant.pack16,
+    };
+    let id = tcgen05_ld_id(ld);
+    let register_count = tcgen05_ld_register_count(ld);
+    let rust_result = tcgen05_ld_rust_result(ld);
+    let llvm_result = tcgen05_ld_llvm_result(ld);
+    let mode = if ld.pack16 { "pack16" } else { "raw" };
+    let mut record = base.clone();
+    record.id = id.clone();
+    record.abi_id = variant.abi_id.clone();
+    record.operation_key = format!(
+        "tcgen05.ld.{}.{}.{}",
+        tcgen05_ld_shape_name(ld.shape),
+        tcgen05_ld_multiplicity_name(ld.multiplicity),
+        mode
+    );
+    record.source_record = Some(tcgen05_ld_source_record(ld));
+    record.rust_name = id.clone();
+    let has_half_split_offset = ld.shape == Tcgen05LdShape::M16x32bx2;
+    record.rust_arguments = if has_half_split_offset {
+        vec!["u32".into(), "i64".into()]
+    } else {
+        vec!["u32".into()]
+    };
+    record.rust_result = rust_result.clone();
+    record.must_use = true;
+    record.public_rust_path = format!("cuda_intrinsics::tcgen05::{id}");
+    record.compatibility_rust_paths = vec![format!(
+        "cuda_device::tcgen05::{}",
+        if has_half_split_offset {
+            format!("__{id}")
+        } else {
+            id.clone()
+        }
+    )];
+    record.dialect_op_type = tcgen05_ld_op_type(ld);
+    record.dialect_op_name = format!("nvvm.{id}");
+    record.dialect_operands = if has_half_split_offset {
+        vec!["i32".into(), "i64".into()]
+    } else {
+        vec!["i32".into()]
+    };
+    record.dialect_results = vec!["i32".into(); register_count];
+    record.llvm_symbol = Some(tcgen05_ld_llvm_symbol(ld));
+    record.resolved_llvm_symbol = None;
+    record.llvm_arguments = if has_half_split_offset {
+        vec!["tmem_ptr".into(), "i64".into(), "i1".into()]
+    } else {
+        vec!["tmem_ptr".into(), "i1".into()]
+    };
+    record.llvm_results = vec![llvm_result];
+    record.ptx_result = rust_result;
+    record.execution_scope = Tcgen05Operation::Ld.execution_scope().into();
+    record.backend_lowerings[0].evidence_profile = if has_half_split_offset {
+        &admission.offset_llvm_evidence_profile
+    } else {
+        &admission.ld_llvm_evidence_profile
+    }
+    .as_ref()
+    .expect("validated tcgen05 load LLVM evidence profile")
+    .clone();
+    record.backend_lowerings[1].evidence_profile = if has_half_split_offset {
+        &admission.offset_libnvvm_evidence_profile
+    } else {
+        &admission.ld_libnvvm_evidence_profile
+    }
+    .as_ref()
+    .expect("validated tcgen05 load libNVVM evidence profile")
+    .clone();
+    record.tcgen05 = Some(Tcgen05 {
+        operation: Tcgen05Operation::Ld,
+        cp: None,
+        ld: Some(ld),
+        st: None,
+        mma: None,
+        adapter: if has_half_split_offset {
+            Tcgen05Adapter::TmemHalfSplitOffsetInjectPack16ToU32Registers
+        } else {
+            Tcgen05Adapter::TmemInjectPack16ToU32Registers
+        },
+        source_contract: Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
+        runtime_validation: admission.runtime_validation,
+    });
+    record.expected_ptx.modifiers = tcgen05_ld_modifiers(ld);
+    record.expected_ptx.operands = tcgen05_ld_operands(ld);
+    record.summary = format!(
+        "Loads {register_count} {} 32-bit register value{} from tensor memory.",
+        if ld.pack16 { "packed" } else { "raw" },
+        if register_count == 1 { "" } else { "s" }
+    );
+    record
+}
+
+pub(in crate::resolve) const TCGEN05_ST_VARIANTS: [(Tcgen05LdShape, Tcgen05LdMultiplicity); 29] =
+    TCGEN05_LD_VARIANTS;
+
+pub(in crate::resolve) fn tcgen05_st_register_count(st: Tcgen05St) -> usize {
+    st.shape.register_multiplier() * st.multiplicity.count()
+}
+
+pub(in crate::resolve) fn tcgen05_st_id(st: Tcgen05St) -> String {
+    format!(
+        "tcgen05_st_{}_{}_{}",
+        tcgen05_ld_shape_name(st.shape),
+        tcgen05_ld_multiplicity_name(st.multiplicity),
+        if st.unpack16 { "unpack16" } else { "raw" }
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_st_source_record(st: Tcgen05St) -> String {
+    format!(
+        "int_nvvm_tcgen05_st_{}_{}",
+        tcgen05_ld_shape_name(st.shape),
+        tcgen05_ld_multiplicity_name(st.multiplicity)
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_st_llvm_symbol(st: Tcgen05St) -> String {
+    format!(
+        "llvm.nvvm.tcgen05.st.{}.{}",
+        tcgen05_ld_shape_name(st.shape),
+        tcgen05_ld_multiplicity_name(st.multiplicity)
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_st_rust_data(st: Tcgen05St) -> String {
+    match tcgen05_st_register_count(st) {
+        1 => "u32".into(),
+        count => format!("[u32; {count}]"),
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_st_llvm_data(st: Tcgen05St) -> String {
+    match tcgen05_st_register_count(st) {
+        1 => "i32".into(),
+        count => format!("v{count}i32"),
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_st_op_type(st: Tcgen05St) -> String {
+    let shape = tcgen05_ld_shape_name(st.shape);
+    let multiplicity = tcgen05_ld_multiplicity_name(st.multiplicity)
+        .strip_prefix('x')
+        .unwrap();
+    format!(
+        "Tcgen05St{shape}X{multiplicity}{}Op",
+        if st.unpack16 { "Unpack16" } else { "Raw" }
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_st_modifiers(st: Tcgen05St) -> Vec<String> {
+    let mut modifiers = vec![
+        "st".into(),
+        "sync".into(),
+        "aligned".into(),
+        tcgen05_ld_shape_name(st.shape).into(),
+        tcgen05_ld_multiplicity_name(st.multiplicity).into(),
+    ];
+    if st.unpack16 {
+        modifiers.push("unpack::16b".into());
+    }
+    modifiers.push("b32".into());
+    modifiers
+}
+
+pub(in crate::resolve) fn tcgen05_st_operands(st: Tcgen05St) -> Vec<OperandPattern> {
+    let data = OperandPattern::RegisterList {
+        length: tcgen05_st_register_count(st),
+    };
+    let mut operands = vec![OperandPattern::Address];
+    if st.shape == Tcgen05LdShape::M16x32bx2 {
+        operands.push(OperandPattern::Immediate);
+    }
+    operands.push(data);
+    operands
+}
+
+pub(in crate::resolve) fn materialize_tcgen05_st_variant(
+    base: &OverlayIntrinsic,
+    admission: &Tcgen05Admission,
+    variant: &Tcgen05StAdmissionVariant,
+) -> OverlayIntrinsic {
+    let st = Tcgen05St {
+        shape: variant.shape,
+        multiplicity: variant.multiplicity,
+        unpack16: variant.unpack16,
+    };
+    let id = tcgen05_st_id(st);
+    let register_count = tcgen05_st_register_count(st);
+    let rust_data = tcgen05_st_rust_data(st);
+    let llvm_data = tcgen05_st_llvm_data(st);
+    let mode = if st.unpack16 { "unpack16" } else { "raw" };
+    let mut record = base.clone();
+    record.id = id.clone();
+    record.abi_id = variant.abi_id.clone();
+    record.operation_key = format!(
+        "tcgen05.st.{}.{}.{}",
+        tcgen05_ld_shape_name(st.shape),
+        tcgen05_ld_multiplicity_name(st.multiplicity),
+        mode
+    );
+    record.source_record = Some(tcgen05_st_source_record(st));
+    record.rust_name = id.clone();
+    let has_half_split_offset = st.shape == Tcgen05LdShape::M16x32bx2;
+    record.rust_arguments = if has_half_split_offset {
+        vec!["u32".into(), "i64".into(), rust_data]
+    } else {
+        vec!["u32".into(), rust_data]
+    };
+    record.rust_result = "()".into();
+    record.must_use = false;
+    record.public_rust_path = format!("cuda_intrinsics::tcgen05::{id}");
+    record.compatibility_rust_paths = vec![format!(
+        "cuda_device::tcgen05::{}",
+        if has_half_split_offset {
+            format!("__{id}")
+        } else {
+            id.clone()
+        }
+    )];
+    record.dialect_op_type = tcgen05_st_op_type(st);
+    record.dialect_op_name = format!("nvvm.{id}");
+    record.dialect_operands = std::iter::once("i32".into())
+        .chain(has_half_split_offset.then(|| "i64".into()))
+        .chain(std::iter::repeat_n("i32".into(), register_count))
+        .collect();
+    record.dialect_results.clear();
+    record.llvm_symbol = Some(tcgen05_st_llvm_symbol(st));
+    record.resolved_llvm_symbol = None;
+    record.llvm_arguments = if has_half_split_offset {
+        vec!["tmem_ptr".into(), "i64".into(), llvm_data, "i1".into()]
+    } else {
+        vec!["tmem_ptr".into(), llvm_data, "i1".into()]
+    };
+    record.llvm_results.clear();
+    record.memory = "write".into();
+    record.ptx_result = "()".into();
+    record.execution_scope = Tcgen05Operation::St.execution_scope().into();
+    record.backend_lowerings[0].evidence_profile = if has_half_split_offset {
+        &admission.offset_llvm_evidence_profile
+    } else {
+        &admission.st_llvm_evidence_profile
+    }
+    .as_ref()
+    .expect("validated tcgen05 store LLVM evidence profile")
+    .clone();
+    record.backend_lowerings[1].evidence_profile = if has_half_split_offset {
+        &admission.offset_libnvvm_evidence_profile
+    } else {
+        &admission.st_libnvvm_evidence_profile
+    }
+    .as_ref()
+    .expect("validated tcgen05 store libNVVM evidence profile")
+    .clone();
+    record.tcgen05 = Some(Tcgen05 {
+        operation: Tcgen05Operation::St,
+        cp: None,
+        ld: None,
+        st: Some(st),
+        mma: None,
+        adapter: if has_half_split_offset {
+            Tcgen05Adapter::TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid
+        } else {
+            Tcgen05Adapter::TmemU32RegistersInjectUnpack16ToVoid
+        },
+        source_contract: Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
+        runtime_validation: admission.runtime_validation,
+    });
+    record.expected_ptx.modifiers = tcgen05_st_modifiers(st);
+    record.expected_ptx.operands = tcgen05_st_operands(st);
+    record.summary = format!(
+        "Stores {register_count} {} 32-bit register value{} to tensor memory.",
+        if st.unpack16 { "unpacked" } else { "raw" },
+        if register_count == 1 { "" } else { "s" }
+    );
+    record
+}
+
+pub(in crate::resolve) fn validate_tcgen05_ld_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+    tcgen05: &Tcgen05,
+    ld: Tcgen05Ld,
+) -> Result<()> {
+    let has_half_split_offset = ld.shape == Tcgen05LdShape::M16x32bx2;
+    let variants: &[(Tcgen05LdShape, Tcgen05LdMultiplicity)] = if has_half_split_offset {
+        &TCGEN05_OFFSET_LDST_VARIANTS
+    } else {
+        &TCGEN05_LD_VARIANTS
+    };
+    ensure!(
+        variants.contains(&(ld.shape, ld.multiplicity)),
+        "{} has an unsupported tcgen05 load identity",
+        policy.id
+    );
+    let id = tcgen05_ld_id(ld);
+    let source_record = tcgen05_ld_source_record(ld);
+    let llvm_symbol = tcgen05_ld_llvm_symbol(ld);
+    let rust_result = tcgen05_ld_rust_result(ld);
+    let llvm_result = tcgen05_ld_llvm_result(ld);
+    let register_count = tcgen05_ld_register_count(ld);
+    let mode = if ld.pack16 { "pack16" } else { "raw" };
+    let expected_rust_arguments = if has_half_split_offset {
+        vec!["u32", "i64"]
+    } else {
+        vec!["u32"]
+    };
+    let compatibility_name = if has_half_split_offset {
+        format!("__{id}")
+    } else {
+        id.clone()
+    };
+    let expected_dialect_operands = if has_half_split_offset {
+        vec!["i32", "i64"]
+    } else {
+        vec!["i32"]
+    };
+    let expected_llvm_arguments = if has_half_split_offset {
+        vec!["tmem_ptr", "i64", "i1"]
+    } else {
+        vec!["tmem_ptr", "i1"]
+    };
+    let expected_properties = if has_half_split_offset {
+        vec![
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>",
+        ]
+    } else {
+        vec![
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>",
+        ]
+    };
+    ensure!(
+        policy.id == id
+            && policy.operation_key
+                == format!(
+                    "tcgen05.ld.{}.{}.{}",
+                    tcgen05_ld_shape_name(ld.shape),
+                    tcgen05_ld_multiplicity_name(ld.multiplicity),
+                    mode
+                )
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(source_record.as_str())
+            && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none()
+            && declaration.source_record == source_record
+            && declaration.llvm_name == llvm_symbol,
+        "{} tcgen05 load identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "tcgen05"
+            && policy.rust_name == id
+            && policy.rust_arguments == expected_rust_arguments
+            && policy.rust_result == rust_result
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::tcgen05::{id}")
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::tcgen05::{compatibility_name}")],
+        "{} tcgen05 load Rust API changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == tcgen05_ld_op_type(ld)
+            && policy.dialect_op_name == format!("nvvm.{id}")
+            && policy.dialect_operands == expected_dialect_operands
+            && policy.dialect_results == vec!["i32"; register_count]
+            && policy.llvm_arguments == expected_llvm_arguments
+            && policy.llvm_results == [llvm_result.as_str()]
+            && declaration.arguments == expected_llvm_arguments
+            && declaration.results == [llvm_result.as_str()]
+            && declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_TCGEN05_LD"]
+            && declaration.properties == expected_properties
+            && declaration.selections.is_empty()
+            && policy.lowering == "generated_tcgen05",
+        "{} tcgen05 load carrier or imported declaration changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read"
+            && policy.convergent
+            && policy.execution_scope == Tcgen05Operation::Ld.execution_scope()
+            && tcgen05.operation == Tcgen05Operation::Ld
+            && tcgen05.cp.is_none()
+            && tcgen05.ld == Some(ld)
+            && tcgen05.st.is_none()
+            && tcgen05.adapter
+                == if has_half_split_offset {
+                    Tcgen05Adapter::TmemHalfSplitOffsetInjectPack16ToU32Registers
+                } else {
+                    Tcgen05Adapter::TmemInjectPack16ToU32Registers
+                }
+            && tcgen05.source_contract == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
+            && tcgen05.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} tcgen05 load semantics changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == "8.6"
+            && policy.minimum_sm.is_none()
+            && policy.targets == TCGEN05_LLVM_TARGETS
+            && policy.ptx_isa_version == "8.6"
+            && policy.ptx_result == rust_result
+            && policy.expected_ptx.mnemonic == "tcgen05"
+            && policy.expected_ptx.modifiers == tcgen05_ld_modifiers(ld)
+            && policy.expected_ptx.operands == tcgen05_ld_operands(ld),
+        "{} tcgen05 load target or PTX contract changed",
+        policy.id
+    );
+    validate_tcgen05_backend_routes(policy, "tcgen05 load")?;
+    ensure_no_other_family_contract(policy, "tcgen05 load")?;
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_tcgen05_st_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+    tcgen05: &Tcgen05,
+    st: Tcgen05St,
+) -> Result<()> {
+    let has_half_split_offset = st.shape == Tcgen05LdShape::M16x32bx2;
+    let variants: &[(Tcgen05LdShape, Tcgen05LdMultiplicity)] = if has_half_split_offset {
+        &TCGEN05_OFFSET_LDST_VARIANTS
+    } else {
+        &TCGEN05_ST_VARIANTS
+    };
+    ensure!(
+        variants.contains(&(st.shape, st.multiplicity)),
+        "{} has an unsupported tcgen05 store identity",
+        policy.id
+    );
+    let id = tcgen05_st_id(st);
+    let source_record = tcgen05_st_source_record(st);
+    let llvm_symbol = tcgen05_st_llvm_symbol(st);
+    let rust_data = tcgen05_st_rust_data(st);
+    let llvm_data = tcgen05_st_llvm_data(st);
+    let register_count = tcgen05_st_register_count(st);
+    let mode = if st.unpack16 { "unpack16" } else { "raw" };
+    let expected_rust_arguments = if has_half_split_offset {
+        vec!["u32", "i64", rust_data.as_str()]
+    } else {
+        vec!["u32", rust_data.as_str()]
+    };
+    let compatibility_name = if has_half_split_offset {
+        format!("__{id}")
+    } else {
+        id.clone()
+    };
+    let expected_dialect_operands = std::iter::once("i32".to_owned())
+        .chain(has_half_split_offset.then(|| "i64".to_owned()))
+        .chain(std::iter::repeat_n("i32".to_owned(), register_count))
+        .collect::<Vec<_>>();
+    let expected_llvm_arguments = if has_half_split_offset {
+        vec!["tmem_ptr", "i64", llvm_data.as_str(), "i1"]
+    } else {
+        vec!["tmem_ptr", llvm_data.as_str(), "i1"]
+    };
+    let expected_properties = if has_half_split_offset {
+        vec![
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>",
+        ]
+    } else {
+        vec![
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>",
+        ]
+    };
+    ensure!(
+        policy.id == id
+            && policy.operation_key
+                == format!(
+                    "tcgen05.st.{}.{}.{}",
+                    tcgen05_ld_shape_name(st.shape),
+                    tcgen05_ld_multiplicity_name(st.multiplicity),
+                    mode
+                )
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(source_record.as_str())
+            && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none()
+            && declaration.source_record == source_record
+            && declaration.llvm_name == llvm_symbol,
+        "{} tcgen05 store identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "tcgen05"
+            && policy.rust_name == id
+            && policy.rust_arguments == expected_rust_arguments
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::tcgen05::{id}")
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::tcgen05::{compatibility_name}")],
+        "{} tcgen05 store Rust API changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == tcgen05_st_op_type(st)
+            && policy.dialect_op_name == format!("nvvm.{id}")
+            && policy.dialect_operands == expected_dialect_operands
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == expected_llvm_arguments
+            && policy.llvm_results.is_empty()
+            && declaration.arguments == expected_llvm_arguments
+            && declaration.results.is_empty()
+            && declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_TCGEN05_ST"]
+            && declaration.properties == expected_properties
+            && declaration.selections.is_empty()
+            && policy.lowering == "generated_tcgen05",
+        "{} tcgen05 store carrier or imported declaration changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "write"
+            && policy.convergent
+            && policy.execution_scope == Tcgen05Operation::St.execution_scope()
+            && tcgen05.operation == Tcgen05Operation::St
+            && tcgen05.cp.is_none()
+            && tcgen05.ld.is_none()
+            && tcgen05.st == Some(st)
+            && tcgen05.adapter
+                == if has_half_split_offset {
+                    Tcgen05Adapter::TmemHalfSplitOffsetU32RegistersInjectUnpack16ToVoid
+                } else {
+                    Tcgen05Adapter::TmemU32RegistersInjectUnpack16ToVoid
+                }
+            && tcgen05.source_contract == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
+            && tcgen05.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} tcgen05 store semantics changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == "8.6"
+            && policy.minimum_sm.is_none()
+            && policy.targets == TCGEN05_LLVM_TARGETS
+            && policy.ptx_isa_version == "8.6"
+            && policy.ptx_result == "()"
+            && policy.expected_ptx.mnemonic == "tcgen05"
+            && policy.expected_ptx.modifiers == tcgen05_st_modifiers(st)
+            && policy.expected_ptx.operands == tcgen05_st_operands(st),
+        "{} tcgen05 store target or PTX contract changed",
+        policy.id
+    );
+    validate_tcgen05_backend_routes(policy, "tcgen05 store")?;
+    ensure_no_other_family_contract(policy, "tcgen05 store")?;
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_tcgen05_cp_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+    tcgen05: &Tcgen05,
+    cp: Tcgen05Cp,
+) -> Result<()> {
+    ensure!(
+        TCGEN05_CP_MEMBERS.contains(&cp.member),
+        "{} has an unsupported tcgen05 copy identity",
+        policy.id
+    );
+    let recipe = tcgen05_cp_member_recipe(cp.member);
+    let group = match cp.group {
+        Tcgen05CpGroup::Cg1 => 1,
+        Tcgen05CpGroup::Cg2 => 2,
+    };
+    let group_suffix = if group == 1 { "" } else { "_cg2" };
+    let id_suffix = recipe.llvm_suffix.replace('.', "_");
+    let id = format!("tcgen05_cp_{id_suffix}{group_suffix}");
+    let operation = if group == 1 {
+        Tcgen05Operation::CpSmemToTmem
+    } else {
+        Tcgen05Operation::CpSmemToTmemCg2
+    };
+    let op_type = format!(
+        "Tcgen05Cp{}{}Op",
+        recipe.op_suffix,
+        if group == 1 { "" } else { "Cg2" }
+    );
+    let source_record = format!("int_nvvm_tcgen05_cp_{}_cg{group}", id_suffix);
+    let llvm_symbol = format!("llvm.nvvm.tcgen05.cp.{}.cg{group}", recipe.llvm_suffix);
+    let modifiers = std::iter::once("cp".into())
+        .chain(std::iter::once(format!("cta_group::{group}")))
+        .chain(recipe.ptx_suffix.split('.').map(Into::into))
+        .collect::<Vec<String>>();
+    ensure!(
+        policy.id == id
+            && policy.operation_key == format!("tcgen05.cp.{}.cg{group}", recipe.llvm_suffix)
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(source_record.as_str())
+            && policy.llvm_symbol.as_deref() == Some(llvm_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none()
+            && declaration.source_record == source_record
+            && declaration.llvm_name == llvm_symbol,
+        "{} tcgen05 copy identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "tcgen05"
+            && policy.rust_name == id
+            && policy.rust_arguments == ["u32", "u64"]
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::tcgen05::{id}")
+            && policy.compatibility_rust_paths == [format!("cuda_device::tcgen05::{id}")],
+        "{} tcgen05 copy Rust API changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == op_type
+            && policy.dialect_op_name == format!("nvvm.{id}")
+            && policy.dialect_operands == ["i32", "i64"]
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == ["tmem_ptr", "i64"]
+            && policy.llvm_results.is_empty()
+            && declaration.arguments == ["tmem_ptr", "i64"]
+            && declaration.results.is_empty()
+            && declaration.classes == ["SDPatternOperator", "Intrinsic"]
+            && declaration.properties
+                == [
+                    "IntrConvergent",
+                    "IntrInaccessibleMemOrArgMemOnly",
+                    "NoCapture<arg0>",
+                ]
+            && policy.lowering == "generated_tcgen05",
+        "{} tcgen05 copy carrier or declaration changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read_write"
+            && policy.convergent
+            && policy.execution_scope == "thread"
+            && tcgen05.operation == operation
+            && tcgen05.ld.is_none()
+            && tcgen05.st.is_none()
+            && tcgen05.adapter == Tcgen05Adapter::TmemDescriptorToVoid
+            && tcgen05.source_contract == Tcgen05SourceContract::ExactTablegenSelection
+            && tcgen05.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} tcgen05 copy semantics changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == "8.6"
+            && policy.minimum_sm.is_none()
+            && policy.targets == TCGEN05_LLVM_TARGETS
+            && policy.ptx_isa_version == "8.6"
+            && policy.ptx_result == "()"
+            && policy.expected_ptx.mnemonic == "tcgen05"
+            && policy.expected_ptx.modifiers == modifiers
+            && policy.expected_ptx.operands == [OperandPattern::Address, OperandPattern::Register],
+        "{} tcgen05 copy target or PTX contract changed",
+        policy.id
+    );
+    validate_tcgen05_backend_routes(policy, "tcgen05 copy")?;
+    ensure!(
+        declaration.selections.len() == 1,
+        "{} must keep one exact tcgen05 copy selection",
+        policy.id
+    );
+    let selection = &declaration.selections[0];
+    ensure!(
+        selection.source_record == format!("TCGEN05_CP_{}_cg{group}", recipe.selection_stem)
+            && selection.asm
+                == format!(
+                    "tcgen05.cp.cta_group::{group}.{} \t[$tmem_addr], $sdesc;",
+                    recipe.ptx_suffix
+                )
+            && selection.predicates == ["Subtarget->hasTcgen05InstSupport()"]
+            && selection.constraints.is_empty(),
+        "{} exact tcgen05 copy selection changed",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "tcgen05 copy")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/mma.rs b/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/mma.rs
new file mode 100644
index 0000000000..d81f70fc2d
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/mma.rs
@@ -0,0 +1,937 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogTargetRequirement, ImportedIntrinsic, IntrinsicBackend,
+    OverlayBackendLowering, OverlayIntrinsic, RuntimeValidation, TargetContract,
+    TargetSelectorBinding, Tcgen05, Tcgen05Adapter, Tcgen05Admission, Tcgen05Mma,
+    Tcgen05MmaAdmissionVariant, Tcgen05MmaAlias, Tcgen05MmaBUsage, Tcgen05MmaFixedSelectors,
+    Tcgen05MmaForm, Tcgen05MmaKind, Tcgen05MmaSelectorLayout, Tcgen05Operation,
+    Tcgen05SourceContract,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Result, ensure};
+use std::collections::BTreeSet;
+
+use super::*;
+use crate::resolve::guards::*;
+use crate::resolve::targets::*;
+
+pub(in crate::resolve) const TCGEN05_MMA_FORMS: [Tcgen05MmaForm; 14] = [
+    Tcgen05MmaForm::Shared,
+    Tcgen05MmaForm::Tensor,
+    Tcgen05MmaForm::TensorAshift,
+    Tcgen05MmaForm::SpShared,
+    Tcgen05MmaForm::SpTensor,
+    Tcgen05MmaForm::SpTensorAshift,
+    Tcgen05MmaForm::WsShared,
+    Tcgen05MmaForm::WsSharedZeroColMask,
+    Tcgen05MmaForm::WsSpShared,
+    Tcgen05MmaForm::WsSpSharedZeroColMask,
+    Tcgen05MmaForm::WsSpTensor,
+    Tcgen05MmaForm::WsSpTensorZeroColMask,
+    Tcgen05MmaForm::WsTensor,
+    Tcgen05MmaForm::WsTensorZeroColMask,
+];
+pub(in crate::resolve) const TCGEN05_MMA_ALIASES: [Tcgen05MmaAlias; 5] = [
+    Tcgen05MmaAlias::E4m3,
+    Tcgen05MmaAlias::E5m2,
+    Tcgen05MmaAlias::E2m3,
+    Tcgen05MmaAlias::E3m2,
+    Tcgen05MmaAlias::E2m1,
+];
+pub(in crate::resolve) const TCGEN05_MMA_KINDS: [Tcgen05MmaKind; 4] = [
+    Tcgen05MmaKind::F16,
+    Tcgen05MmaKind::F8f6f4,
+    Tcgen05MmaKind::I8,
+    Tcgen05MmaKind::Tf32,
+];
+pub(in crate::resolve) const TCGEN05_MMA_DIALECT_OP_TYPE: &str = "Tcgen05MmaOp";
+pub(in crate::resolve) const TCGEN05_MMA_DIALECT_OP_NAME: &str = "nvvm.tcgen05_mma";
+pub(in crate::resolve) fn tcgen05_mma_form_name(form: Tcgen05MmaForm) -> &'static str {
+    match form {
+        Tcgen05MmaForm::Shared => "shared",
+        Tcgen05MmaForm::Tensor => "tensor",
+        Tcgen05MmaForm::TensorAshift => "tensor_ashift",
+        Tcgen05MmaForm::SpShared => "sp_shared",
+        Tcgen05MmaForm::SpTensor => "sp_tensor",
+        Tcgen05MmaForm::SpTensorAshift => "sp_tensor_ashift",
+        Tcgen05MmaForm::WsShared => "ws_shared",
+        Tcgen05MmaForm::WsSharedZeroColMask => "ws_shared_zero_col_mask",
+        Tcgen05MmaForm::WsSpShared => "ws_sp_shared",
+        Tcgen05MmaForm::WsSpSharedZeroColMask => "ws_sp_shared_zero_col_mask",
+        Tcgen05MmaForm::WsSpTensor => "ws_sp_tensor",
+        Tcgen05MmaForm::WsSpTensorZeroColMask => "ws_sp_tensor_zero_col_mask",
+        Tcgen05MmaForm::WsTensor => "ws_tensor",
+        Tcgen05MmaForm::WsTensorZeroColMask => "ws_tensor_zero_col_mask",
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_mma_alias_name(alias: Tcgen05MmaAlias) -> &'static str {
+    match alias {
+        Tcgen05MmaAlias::E4m3 => "e4m3",
+        Tcgen05MmaAlias::E5m2 => "e5m2",
+        Tcgen05MmaAlias::E2m3 => "e2m3",
+        Tcgen05MmaAlias::E3m2 => "e3m2",
+        Tcgen05MmaAlias::E2m1 => "e2m1",
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_mma_kind_name(kind: Tcgen05MmaKind) -> &'static str {
+    match kind {
+        Tcgen05MmaKind::F16 => "f16",
+        Tcgen05MmaKind::Tf32 => "tf32",
+        Tcgen05MmaKind::F8f6f4 => "f8f6f4",
+        Tcgen05MmaKind::I8 => "i8",
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_mma_b_usage_name(usage: Tcgen05MmaBUsage) -> &'static str {
+    match usage {
+        Tcgen05MmaBUsage::Discard => "discard",
+        Tcgen05MmaBUsage::Fill => "fill",
+        Tcgen05MmaBUsage::Use => "use",
+        Tcgen05MmaBUsage::LastUse => "lastuse",
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_mma_is_ws(form: Tcgen05MmaForm) -> bool {
+    matches!(
+        form,
+        Tcgen05MmaForm::WsShared
+            | Tcgen05MmaForm::WsSharedZeroColMask
+            | Tcgen05MmaForm::WsSpShared
+            | Tcgen05MmaForm::WsSpSharedZeroColMask
+            | Tcgen05MmaForm::WsSpTensor
+            | Tcgen05MmaForm::WsSpTensorZeroColMask
+            | Tcgen05MmaForm::WsTensor
+            | Tcgen05MmaForm::WsTensorZeroColMask
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_mma_is_sparse(form: Tcgen05MmaForm) -> bool {
+    matches!(
+        form,
+        Tcgen05MmaForm::SpShared
+            | Tcgen05MmaForm::SpTensor
+            | Tcgen05MmaForm::SpTensorAshift
+            | Tcgen05MmaForm::WsSpShared
+            | Tcgen05MmaForm::WsSpSharedZeroColMask
+            | Tcgen05MmaForm::WsSpTensor
+            | Tcgen05MmaForm::WsSpTensorZeroColMask
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_mma_is_tensor_a(form: Tcgen05MmaForm) -> bool {
+    matches!(
+        form,
+        Tcgen05MmaForm::Tensor
+            | Tcgen05MmaForm::TensorAshift
+            | Tcgen05MmaForm::SpTensor
+            | Tcgen05MmaForm::SpTensorAshift
+            | Tcgen05MmaForm::WsSpTensor
+            | Tcgen05MmaForm::WsSpTensorZeroColMask
+            | Tcgen05MmaForm::WsTensor
+            | Tcgen05MmaForm::WsTensorZeroColMask
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_mma_is_ashift(form: Tcgen05MmaForm) -> bool {
+    matches!(
+        form,
+        Tcgen05MmaForm::TensorAshift | Tcgen05MmaForm::SpTensorAshift
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_mma_has_zero_col_mask(form: Tcgen05MmaForm) -> bool {
+    matches!(
+        form,
+        Tcgen05MmaForm::WsSharedZeroColMask
+            | Tcgen05MmaForm::WsSpSharedZeroColMask
+            | Tcgen05MmaForm::WsSpTensorZeroColMask
+            | Tcgen05MmaForm::WsTensorZeroColMask
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_mma_source_record(form: Tcgen05MmaForm) -> String {
+    format!("int_nvvm_tcgen05_mma_{}", tcgen05_mma_form_name(form))
+}
+
+pub(in crate::resolve) fn tcgen05_mma_llvm_symbol(form: Tcgen05MmaForm) -> String {
+    let suffix = match form {
+        Tcgen05MmaForm::Shared => "shared",
+        Tcgen05MmaForm::Tensor => "tensor",
+        Tcgen05MmaForm::TensorAshift => "tensor.ashift",
+        Tcgen05MmaForm::SpShared => "sp.shared",
+        Tcgen05MmaForm::SpTensor => "sp.tensor",
+        Tcgen05MmaForm::SpTensorAshift => "sp.tensor.ashift",
+        Tcgen05MmaForm::WsShared => "ws.shared",
+        Tcgen05MmaForm::WsSharedZeroColMask => "ws.shared.zero_col_mask",
+        Tcgen05MmaForm::WsSpShared => "ws.sp.shared",
+        Tcgen05MmaForm::WsSpSharedZeroColMask => "ws.sp.shared.zero_col_mask",
+        Tcgen05MmaForm::WsSpTensor => "ws.sp.tensor",
+        Tcgen05MmaForm::WsSpTensorZeroColMask => "ws.sp.tensor.zero_col_mask",
+        Tcgen05MmaForm::WsTensor => "ws.tensor",
+        Tcgen05MmaForm::WsTensorZeroColMask => "ws.tensor.zero_col_mask",
+    };
+    format!("llvm.nvvm.tcgen05.mma.{suffix}")
+}
+
+pub(in crate::resolve) fn tcgen05_mma_llvm_arguments(form: Tcgen05MmaForm) -> Vec<String> {
+    let mut arguments = vec![
+        "tmem_ptr".into(),
+        if tcgen05_mma_is_tensor_a(form) {
+            "tmem_ptr".into()
+        } else {
+            "i64".into()
+        },
+        "i64".into(),
+        "i32".into(),
+        "i1".into(),
+    ];
+    if tcgen05_mma_is_sparse(form) {
+        arguments.push("tmem_ptr".into());
+    }
+    if tcgen05_mma_has_zero_col_mask(form) {
+        arguments.push("i64".into());
+    }
+    arguments.extend(["i32".into(), "i32".into(), "i32".into()]);
+    arguments
+}
+
+pub(in crate::resolve) fn tcgen05_mma_selector_layout(
+    form: Tcgen05MmaForm,
+) -> Tcgen05MmaSelectorLayout {
+    let first =
+        5 + u8::from(tcgen05_mma_is_sparse(form)) + u8::from(tcgen05_mma_has_zero_col_mask(form));
+    if tcgen05_mma_is_ws(form) {
+        Tcgen05MmaSelectorLayout::WarpSpecialized {
+            kind_argument: first,
+            b_buffer_argument: first + 1,
+            b_usage_argument: first + 2,
+        }
+    } else {
+        Tcgen05MmaSelectorLayout::Base {
+            kind_argument: first,
+            cta_group_argument: first + 1,
+            collector_a_argument: first + 2,
+            collector_a_upper_exclusive: if tcgen05_mma_is_ashift(form) { 2 } else { 4 },
+        }
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_mma_imported_properties(form: Tcgen05MmaForm) -> Vec<String> {
+    let layout = tcgen05_mma_selector_layout(form);
+    let (kind, second, third, second_lower, second_upper, third_upper) = match layout {
+        Tcgen05MmaSelectorLayout::Base {
+            kind_argument,
+            cta_group_argument,
+            collector_a_argument,
+            collector_a_upper_exclusive,
+        } => (
+            kind_argument,
+            cta_group_argument,
+            collector_a_argument,
+            1,
+            3,
+            collector_a_upper_exclusive,
+        ),
+        Tcgen05MmaSelectorLayout::WarpSpecialized {
+            kind_argument,
+            b_buffer_argument,
+            b_usage_argument,
+        } => (kind_argument, b_buffer_argument, b_usage_argument, 0, 4, 4),
+    };
+    let mut properties = vec![
+        format!("ImmArg<arg{kind}>"),
+        format!("ImmArg<arg{second}>"),
+        format!("ImmArg<arg{third}>"),
+        "IntrArgMemOnly".into(),
+        format!("Range<arg{kind},0,4>"),
+        format!("Range<arg{second},{second_lower},{second_upper}>"),
+        format!("Range<arg{third},0,{third_upper}>"),
+        "WriteOnly<arg0>".into(),
+    ];
+    if tcgen05_mma_is_tensor_a(form) {
+        properties.push("ReadOnly<arg1>".into());
+    }
+    if form == Tcgen05MmaForm::Tensor {
+        properties.extend([
+            "ArgInfo<arg5>".into(),
+            "ArgInfo<arg6>".into(),
+            "ArgInfo<arg7>".into(),
+        ]);
+    }
+    properties.sort();
+    properties
+}
+
+pub(in crate::resolve) fn tcgen05_mma_selection_asm(
+    form: Tcgen05MmaForm,
+    kind: Tcgen05MmaKind,
+    cta_group: u8,
+    collector_a: Option<&str>,
+    b_buffer: Option<u8>,
+    b_usage: Option<Tcgen05MmaBUsage>,
+) -> String {
+    let mut head = "tcgen05.mma".to_owned();
+    if tcgen05_mma_is_ws(form) {
+        head.push_str(".ws");
+    }
+    if tcgen05_mma_is_sparse(form) {
+        head.push_str(".sp");
+    }
+    head.push_str(&format!(
+        ".cta_group::{cta_group}.kind::{}",
+        tcgen05_mma_kind_name(kind)
+    ));
+    if tcgen05_mma_is_ws(form) {
+        head.push_str(&format!(
+            ".collector::b{}::{}",
+            b_buffer.expect("warp-specialized B buffer"),
+            tcgen05_mma_b_usage_name(b_usage.expect("warp-specialized B usage"))
+        ));
+    } else {
+        head.push_str(&format!(
+            ".collector::a::{}",
+            collector_a.expect("base collector A usage")
+        ));
+        if tcgen05_mma_is_ashift(form) {
+            head.push_str(".ashift");
+        }
+    }
+
+    let a = if tcgen05_mma_is_tensor_a(form) {
+        "[$a]"
+    } else {
+        "$a"
+    };
+    let mut operands = format!("[$dtmem], {a}, $b");
+    if tcgen05_mma_is_sparse(form) {
+        operands.push_str(", [$spmetadata]");
+    }
+    operands.push_str(", $idesc, $enable_inp_d");
+    if tcgen05_mma_has_zero_col_mask(form) {
+        operands.push_str(", $zero_col_mask");
+    }
+    format!("{head} {operands};")
+}
+
+pub(in crate::resolve) fn tcgen05_mma_all_selection_asms(form: Tcgen05MmaForm) -> BTreeSet<String> {
+    if tcgen05_mma_is_ws(form) {
+        return [
+            Tcgen05MmaBUsage::Discard,
+            Tcgen05MmaBUsage::LastUse,
+            Tcgen05MmaBUsage::Fill,
+            Tcgen05MmaBUsage::Use,
+        ]
+        .into_iter()
+        .flat_map(|usage| {
+            TCGEN05_MMA_KINDS.into_iter().flat_map(move |kind| {
+                (0..4).map(move |buffer| {
+                    tcgen05_mma_selection_asm(form, kind, 1, None, Some(buffer), Some(usage))
+                })
+            })
+        })
+        .collect();
+    }
+    TCGEN05_MMA_KINDS
+        .into_iter()
+        .flat_map(|kind| {
+            (1..=2).flat_map(move |group| {
+                ["discard", "lastuse", "fill", "use"].map(move |usage| {
+                    tcgen05_mma_selection_asm(form, kind, group, Some(usage), None, None)
+                })
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn tcgen05_mma_valid_selection_asms(
+    form: Tcgen05MmaForm,
+) -> BTreeSet<String> {
+    if !tcgen05_mma_is_ashift(form) {
+        return tcgen05_mma_all_selection_asms(form);
+    }
+    TCGEN05_MMA_KINDS
+        .into_iter()
+        .flat_map(|kind| {
+            (1..=2).flat_map(move |group| {
+                ["discard", "lastuse"].map(move |usage| {
+                    tcgen05_mma_selection_asm(form, kind, group, Some(usage), None, None)
+                })
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn tcgen05_mma_target_contract(
+    kind: Tcgen05MmaKind,
+    alternatives: &[(&str, &str)],
+) -> TargetContract {
+    TargetContract {
+        selectors: vec![TargetSelectorBinding {
+            name: "kind".into(),
+            value: tcgen05_mma_kind_name(kind).into(),
+        }],
+        alternatives: alternatives
+            .iter()
+            .map(
+                |(target, minimum_ptx)| crate::model::TargetContractAlternative {
+                    target: (*target).into(),
+                    minimum_ptx: (*minimum_ptx).into(),
+                },
+            )
+            .collect(),
+    }
+}
+
+pub(in crate::resolve) fn expected_tcgen05_mma_target_contracts(
+    backend: IntrinsicBackend,
+) -> Vec<TargetContract> {
+    const LLVM_COMMON: &[(&str, &str)] = &[
+        ("sm_100a", "8.6"),
+        ("sm_100f", "8.8"),
+        ("sm_101a", "8.6"),
+        ("sm_101f", "8.8"),
+        ("sm_103a", "8.8"),
+        ("sm_103f", "8.8"),
+        ("sm_110a", "9.0"),
+        ("sm_110f", "9.0"),
+    ];
+    const LLVM_I8: &[(&str, &str)] = &[("sm_100a", "8.6"), ("sm_101a", "8.6"), ("sm_110a", "9.0")];
+    const LIBNVVM_COMMON: &[(&str, &str)] = &[
+        ("sm_100a", "8.6"),
+        ("sm_100f", "8.8"),
+        ("sm_103a", "8.8"),
+        ("sm_103f", "8.8"),
+        ("sm_110a", "9.0"),
+        ("sm_110f", "9.0"),
+    ];
+    const LIBNVVM_I8: &[(&str, &str)] = &[("sm_100a", "8.6"), ("sm_110a", "9.0")];
+    TCGEN05_MMA_KINDS
+        .into_iter()
+        .map(|kind| {
+            let alternatives = match (backend, kind) {
+                (IntrinsicBackend::LlvmNvptx, Tcgen05MmaKind::I8) => LLVM_I8,
+                (IntrinsicBackend::LlvmNvptx, _) => LLVM_COMMON,
+                (IntrinsicBackend::LibNvvm, Tcgen05MmaKind::I8) => LIBNVVM_I8,
+                (IntrinsicBackend::LibNvvm, _) => LIBNVVM_COMMON,
+            };
+            tcgen05_mma_target_contract(kind, alternatives)
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn tcgen05_mma_expected_ptx(
+    form: Tcgen05MmaForm,
+    alias: Option<Tcgen05MmaAlias>,
+) -> InstructionPattern {
+    let kind = if alias.is_some() {
+        Tcgen05MmaKind::F8f6f4
+    } else {
+        Tcgen05MmaKind::F16
+    };
+    let asm = if tcgen05_mma_is_ws(form) {
+        tcgen05_mma_selection_asm(
+            form,
+            kind,
+            1,
+            None,
+            Some(0),
+            Some(Tcgen05MmaBUsage::Discard),
+        )
+    } else {
+        tcgen05_mma_selection_asm(form, kind, 1, Some("discard"), None, None)
+    };
+    let head = asm.split_whitespace().next().unwrap();
+    let mut components = head.split('.');
+    let mnemonic = components.next().unwrap().into();
+    let modifiers = components.map(str::to_owned).collect();
+    let mut operands = vec![OperandPattern::Address];
+    operands.push(if tcgen05_mma_is_tensor_a(form) {
+        OperandPattern::Address
+    } else {
+        OperandPattern::Register
+    });
+    operands.push(OperandPattern::Register);
+    if tcgen05_mma_is_sparse(form) {
+        operands.push(OperandPattern::Address);
+    }
+    operands.extend([
+        OperandPattern::Register,
+        OperandPattern::Exact {
+            value: "%enable_pred".into(),
+        },
+    ]);
+    if tcgen05_mma_has_zero_col_mask(form) {
+        operands.push(OperandPattern::Register);
+    }
+    InstructionPattern {
+        mnemonic,
+        modifiers,
+        operands,
+    }
+}
+
+pub(in crate::resolve) fn tcgen05_mma_rust_arguments(
+    form: Tcgen05MmaForm,
+    alias: Option<Tcgen05MmaAlias>,
+) -> Vec<String> {
+    if alias.is_some() && form == Tcgen05MmaForm::WsTensor {
+        return ["u32", "u32", "u64", "u64", "u32", "bool"]
+            .into_iter()
+            .map(str::to_owned)
+            .collect();
+    }
+    let mut arguments = tcgen05_mma_llvm_arguments(form);
+    if alias.is_some() {
+        arguments.truncate(arguments.len() - 3);
+    }
+    arguments
+        .iter()
+        .map(|argument| match argument.as_str() {
+            "tmem_ptr" | "i32" => "u32",
+            "i64" => "u64",
+            "i1" => "bool",
+            _ => unreachable!("closed tcgen05 MMA LLVM type"),
+        })
+        .map(str::to_owned)
+        .collect()
+}
+
+pub(in crate::resolve) fn tcgen05_mma_dialect_operands(
+    form: Tcgen05MmaForm,
+    _alias: Option<Tcgen05MmaAlias>,
+) -> Vec<String> {
+    let mut arguments = tcgen05_mma_llvm_arguments(form);
+    arguments.truncate(arguments.len() - 3);
+    arguments
+        .iter()
+        .map(|argument| match argument.as_str() {
+            "tmem_ptr" | "i32" => "i32",
+            "i64" => "i64",
+            "i1" => "i1",
+            _ => unreachable!("closed tcgen05 MMA LLVM type"),
+        })
+        .map(str::to_owned)
+        .collect()
+}
+
+pub(in crate::resolve) fn tcgen05_mma_public_id(
+    form: Tcgen05MmaForm,
+    alias: Option<Tcgen05MmaAlias>,
+) -> String {
+    alias.map_or_else(
+        || format!("tcgen05_mma_{}", tcgen05_mma_form_name(form)),
+        |alias| {
+            let alias = tcgen05_mma_alias_name(alias);
+            if form == Tcgen05MmaForm::WsTensor {
+                format!("tcgen05_mma_ws_{alias}")
+            } else {
+                format!("tcgen05_mma_{alias}")
+            }
+        },
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_mma_operation_key(
+    form: Tcgen05MmaForm,
+    alias: Option<Tcgen05MmaAlias>,
+) -> String {
+    let base = tcgen05_mma_form_name(form).replace('_', ".");
+    alias.map_or_else(
+        || format!("tcgen05.mma.{base}"),
+        |alias| format!("tcgen05.mma.{base}.{}", tcgen05_mma_alias_name(alias)),
+    )
+}
+
+pub(in crate::resolve) fn tcgen05_mma_adapter(
+    form: Tcgen05MmaForm,
+    alias: Option<Tcgen05MmaAlias>,
+) -> Tcgen05Adapter {
+    match alias {
+        Some(_) if form == Tcgen05MmaForm::WsTensor => {
+            Tcgen05Adapter::MmaWsFixedSelectorsDropLegacyADescriptor
+        }
+        _ => Tcgen05Adapter::MmaDirectSelectors,
+    }
+}
+
+pub(in crate::resolve) fn materialize_tcgen05_mma_variant(
+    admission: &Tcgen05Admission,
+    variant: &Tcgen05MmaAdmissionVariant,
+    llvm_target: &CatalogTargetRequirement,
+    libnvvm_target: &CatalogTargetRequirement,
+) -> OverlayIntrinsic {
+    let form = variant.form;
+    let alias = variant.alias;
+    let id = tcgen05_mma_public_id(form, alias);
+    let operation_key = tcgen05_mma_operation_key(form, alias);
+    let llvm_arguments = tcgen05_mma_llvm_arguments(form);
+    let rust_arguments = tcgen05_mma_rust_arguments(form, alias);
+    let dialect_operands = tcgen05_mma_dialect_operands(form, alias);
+    let fixed_selectors = alias.map(|_| Tcgen05MmaFixedSelectors {
+        kind: Tcgen05MmaKind::F8f6f4,
+        b_buffer: 0,
+        b_usage: Tcgen05MmaBUsage::Discard,
+    });
+
+    OverlayIntrinsic {
+        id: id.clone(),
+        abi_id: variant.abi_id.clone(),
+        operation_key,
+        family: "tcgen05".into(),
+        source: None,
+        source_record: Some(tcgen05_mma_source_record(form)),
+        rust_module: "tcgen05".into(),
+        rust_name: id.clone(),
+        rust_arguments,
+        rust_result: "()".into(),
+        safe: false,
+        must_use: false,
+        safe_allowlist_reason: None,
+        public_rust_path: format!("cuda_intrinsics::tcgen05::{id}"),
+        compatibility_rust_paths: vec![if alias.is_some() {
+            format!("cuda_device::tcgen05::{id}")
+        } else {
+            format!("cuda_device::tcgen05::__{id}")
+        }],
+        dialect_op_type: TCGEN05_MMA_DIALECT_OP_TYPE.into(),
+        dialect_op_name: TCGEN05_MMA_DIALECT_OP_NAME.into(),
+        dialect_operands,
+        dialect_results: vec![],
+        llvm_symbol: Some(tcgen05_mma_llvm_symbol(form)),
+        resolved_llvm_symbol: None,
+        llvm_arguments,
+        llvm_results: vec![],
+        pure: false,
+        memory: "read_write".into(),
+        // TableGen omits IntrConvergent, but collective MMA must not move across control flow.
+        convergent: true,
+        execution_scope: "thread".into(),
+        minimum_ptx: "8.6".into(),
+        minimum_sm: None,
+        ptx_result: "()".into(),
+        targets: TCGEN05_LLVM_TARGETS.into(),
+        ptx_isa_version: "8.6".into(),
+        ptx_isa_section: "Tensor Memory tcgen05 instructions".into(),
+        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-memory".into(),
+        lowering: "generated_tcgen05_mma".into(),
+        backend_lowerings: vec![
+            OverlayBackendLowering {
+                backend: IntrinsicBackend::LlvmNvptx,
+                mechanism: BackendLoweringMechanism::InlinePtx,
+                evidence_profile: admission
+                    .mma_llvm_evidence_profile
+                    .as_ref()
+                    .expect("validated tcgen05 MMA LLVM evidence profile")
+                    .clone(),
+                targets: None,
+                minimum_ptx: None,
+                minimum_sm: None,
+            },
+            OverlayBackendLowering {
+                backend: IntrinsicBackend::LibNvvm,
+                mechanism: BackendLoweringMechanism::InlinePtx,
+                evidence_profile: admission
+                    .mma_libnvvm_evidence_profile
+                    .as_ref()
+                    .expect("validated tcgen05 MMA libNVVM evidence profile")
+                    .clone(),
+                targets: None,
+                minimum_ptx: None,
+                minimum_sm: None,
+            },
+        ],
+        packed_atomic: None,
+        redux: None,
+        vote: None,
+        active_mask: None,
+        warp_match: None,
+        warp_barrier: None,
+        warp_shuffle: None,
+        dot_product: None,
+        packed_alu: None,
+        integer_minmax: None,
+        packed_conversion: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cp_async_copy: None,
+        cp_async_control: None,
+        cp_async_mbarrier: None,
+        mbarrier_basic: None,
+        movmatrix: None,
+        mbarrier_extended: None,
+        register_mma: None,
+        sparse_mma: None,
+        prmt: None,
+        cluster_barrier: None,
+        wgmma_control: None,
+        special_register: None,
+        debug_control: None,
+        cluster_memory: None,
+        clc: None,
+        tma: None,
+        tcgen05: Some(Tcgen05 {
+            operation: Tcgen05Operation::Mma,
+            cp: None,
+            ld: None,
+            st: None,
+            mma: Some(Tcgen05Mma {
+                form,
+                selector_layout: tcgen05_mma_selector_layout(form),
+                fixed_selectors,
+                alias,
+                llvm_target: llvm_target.clone(),
+                libnvvm_target: libnvvm_target.clone(),
+            }),
+            adapter: tcgen05_mma_adapter(form, alias),
+            source_contract: Tcgen05SourceContract::TablegenSelectionChangesPtx,
+            runtime_validation: admission.runtime_validation,
+        }),
+        ldmatrix_variant: None,
+        ldmatrix_safety: None,
+        ldmatrix_adapter: None,
+        selected_address_space: None,
+        expected_ptx: tcgen05_mma_expected_ptx(form, alias),
+        summary: match (form, alias) {
+            (Tcgen05MmaForm::WsTensor, Some(_)) => {
+                "Issues one f8f6f4 warp-specialized tensor-memory MMA.".into()
+            }
+            (Tcgen05MmaForm::Shared, Some(_)) => {
+                "Issues one f8f6f4 standard tensor-memory MMA.".into()
+            }
+            _ => "Issues one selector-controlled tensor-memory MMA.".into(),
+        },
+    }
+}
+
+pub(in crate::resolve) fn validate_tcgen05_mma_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+    tcgen05: &Tcgen05,
+    mma: &Tcgen05Mma,
+) -> Result<()> {
+    let form = mma.form;
+    let alias = mma.alias;
+    ensure!(
+        match alias {
+            Some(alias) => {
+                matches!(form, Tcgen05MmaForm::Shared | Tcgen05MmaForm::WsTensor)
+                    && TCGEN05_MMA_ALIASES.contains(&alias)
+            }
+            None => TCGEN05_MMA_FORMS.contains(&form),
+        },
+        "{} has an unsupported tcgen05 MMA identity",
+        policy.id
+    );
+    let id = tcgen05_mma_public_id(form, alias);
+    let operation_key = tcgen05_mma_operation_key(form, alias);
+    let llvm_arguments = tcgen05_mma_llvm_arguments(form);
+    let expected_fixed = alias.map(|_| Tcgen05MmaFixedSelectors {
+        kind: Tcgen05MmaKind::F8f6f4,
+        b_buffer: 0,
+        b_usage: Tcgen05MmaBUsage::Discard,
+    });
+    ensure!(
+        policy.id == id
+            && policy.operation_key == operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(tcgen05_mma_source_record(form).as_str())
+            && policy.llvm_symbol.as_deref() == Some(tcgen05_mma_llvm_symbol(form).as_str())
+            && policy.resolved_llvm_symbol.is_none()
+            && declaration.source_record == tcgen05_mma_source_record(form)
+            && declaration.llvm_name == tcgen05_mma_llvm_symbol(form),
+        "{} tcgen05 MMA identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "tcgen05"
+            && policy.rust_name == id
+            && policy.rust_arguments == tcgen05_mma_rust_arguments(form, alias)
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::tcgen05::{id}")
+            && policy.compatibility_rust_paths
+                == [if alias.is_some() {
+                    format!("cuda_device::tcgen05::{id}")
+                } else {
+                    format!("cuda_device::tcgen05::__{id}")
+                }],
+        "{} tcgen05 MMA Rust API changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == TCGEN05_MMA_DIALECT_OP_TYPE
+            && policy.dialect_op_name == TCGEN05_MMA_DIALECT_OP_NAME
+            && policy.dialect_operands == tcgen05_mma_dialect_operands(form, alias)
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == llvm_arguments
+            && policy.llvm_results.is_empty()
+            && declaration.arguments == llvm_arguments
+            && declaration.results.is_empty()
+            && declaration.classes
+                == [
+                    "SDPatternOperator",
+                    "Intrinsic",
+                    "DefaultAttrsIntrinsic",
+                    "DefaultAttrsIntrinsicFlags",
+                ]
+            && declaration.properties == tcgen05_mma_imported_properties(form)
+            && policy.lowering == "generated_tcgen05_mma",
+        "{} tcgen05 MMA carrier or imported declaration changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read_write"
+            && policy.convergent
+            && policy.execution_scope == "thread"
+            && tcgen05.operation == Tcgen05Operation::Mma
+            && tcgen05.cp.is_none()
+            && tcgen05.ld.is_none()
+            && tcgen05.st.is_none()
+            && mma.selector_layout == tcgen05_mma_selector_layout(form)
+            && mma.fixed_selectors == expected_fixed
+            && tcgen05.adapter == tcgen05_mma_adapter(form, alias)
+            && tcgen05.source_contract == Tcgen05SourceContract::TablegenSelectionChangesPtx
+            && tcgen05.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} tcgen05 MMA semantics or selector contract changed",
+        policy.id
+    );
+
+    let expected_llvm_contracts =
+        expected_tcgen05_mma_target_contracts(IntrinsicBackend::LlvmNvptx);
+    let expected_libnvvm_contracts =
+        expected_tcgen05_mma_target_contracts(IntrinsicBackend::LibNvvm);
+    let selected = [TargetSelectorBinding {
+        name: "kind".into(),
+        value: "f8f6f4".into(),
+    }];
+    let expected_llvm = if alias.is_some() {
+        resolve_target_contract(
+            "tcgen05 MMA LLVM alias",
+            &selected,
+            &expected_llvm_contracts,
+        )?
+    } else {
+        resolve_target_contracts("tcgen05 MMA LLVM", &expected_llvm_contracts)?
+    };
+    let expected_libnvvm = if alias.is_some() {
+        resolve_target_contract(
+            "tcgen05 MMA libNVVM alias",
+            &selected,
+            &expected_libnvvm_contracts,
+        )?
+    } else {
+        resolve_target_contracts("tcgen05 MMA libNVVM", &expected_libnvvm_contracts)?
+    };
+    ensure!(
+        mma.llvm_target == expected_llvm
+            && mma.libnvvm_target == expected_libnvvm
+            && policy.minimum_ptx == "8.6"
+            && policy.minimum_sm.is_none()
+            && policy.targets == TCGEN05_LLVM_TARGETS
+            && policy.ptx_result == "()"
+            && policy.ptx_isa_version == "8.6"
+            && policy.expected_ptx == tcgen05_mma_expected_ptx(form, alias),
+        "{} tcgen05 MMA target or PTX contract changed",
+        policy.id
+    );
+    let backend_pairs = policy
+        .backend_lowerings
+        .iter()
+        .map(|route| (route.backend, route.mechanism))
+        .collect::<BTreeSet<_>>();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ])
+            && policy.backend_lowerings.iter().all(|route| {
+                !route.evidence_profile.trim().is_empty()
+                    && route.targets.is_none()
+                    && route.minimum_ptx.is_none()
+                    && route.minimum_sm.is_none()
+            }),
+        "{} tcgen05 MMA backend routes changed",
+        policy.id
+    );
+
+    let expected_all = tcgen05_mma_all_selection_asms(form);
+    let expected_valid = if alias.is_some() {
+        BTreeSet::from([if tcgen05_mma_is_ws(form) {
+            tcgen05_mma_selection_asm(
+                form,
+                Tcgen05MmaKind::F8f6f4,
+                1,
+                None,
+                Some(0),
+                Some(Tcgen05MmaBUsage::Discard),
+            )
+        } else {
+            tcgen05_mma_selection_asm(form, Tcgen05MmaKind::F8f6f4, 1, Some("discard"), None, None)
+        }])
+    } else {
+        tcgen05_mma_valid_selection_asms(form)
+    };
+    let mut source_records = BTreeSet::new();
+    let actual_all = declaration
+        .selections
+        .iter()
+        .map(|selection| {
+            ensure!(
+                !selection.source_record.is_empty()
+                    && source_records.insert(selection.source_record.as_str())
+                    && selection.constraints.is_empty(),
+                "{} tcgen05 MMA selection provenance changed",
+                policy.id
+            );
+            let predicate = if selection.asm.contains(".kind::i8.") {
+                "Subtarget->hasTcgen05MMAI8Kind()"
+            } else {
+                "Subtarget->hasTcgen05InstSupport()"
+            };
+            ensure!(
+                selection.predicates == [predicate],
+                "{} tcgen05 MMA selection predicate changed",
+                policy.id
+            );
+            Ok(selection.asm.clone())
+        })
+        .collect::<Result<BTreeSet<_>>>()?;
+    ensure!(
+        actual_all == expected_all
+            && declaration.selections.len() == expected_all.len()
+            && expected_valid.is_subset(&expected_all)
+            && expected_valid.len()
+                == if alias.is_some() {
+                    1
+                } else if tcgen05_mma_is_ws(form) {
+                    64
+                } else if tcgen05_mma_is_ashift(form) {
+                    16
+                } else {
+                    32
+                },
+        "{} tcgen05 MMA selection matrix changed",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "tcgen05 MMA")?;
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/mod.rs b/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/mod.rs
new file mode 100644
index 0000000000..4792a0e0a0
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/mod.rs
@@ -0,0 +1,14 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+pub(in crate::resolve) mod admission;
+pub(in crate::resolve) mod ldst_cp;
+pub(in crate::resolve) mod mma;
+pub(in crate::resolve) mod recipes;
+
+pub(in crate::resolve) use admission::*;
+pub(in crate::resolve) use ldst_cp::*;
+pub(in crate::resolve) use mma::*;
+pub(in crate::resolve) use recipes::*;
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/recipes.rs b/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/recipes.rs
new file mode 100644
index 0000000000..8e4752757c
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/tcgen05/recipes.rs
@@ -0,0 +1,914 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{Tcgen05Adapter, Tcgen05Operation, Tcgen05SourceContract};
+use crate::ptx::OperandPattern;
+
+pub(in crate::resolve) const TCGEN05_LLVM_TARGETS: &str = "sm_100a|sm_101a|sm_103a|sm_110a";
+pub(in crate::resolve) const TCGEN05_LIBNVVM_TARGETS: &str = "sm_100a|sm_103a|sm_110a";
+pub(in crate::resolve) struct Tcgen05Recipe {
+    pub(in crate::resolve) operation: Tcgen05Operation,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) rust_arguments: &'static [&'static str],
+    pub(in crate::resolve) rust_result: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) dialect_operands: &'static [&'static str],
+    pub(in crate::resolve) dialect_results: &'static [&'static str],
+    pub(in crate::resolve) llvm_arguments: &'static [&'static str],
+    pub(in crate::resolve) llvm_results: &'static [&'static str],
+    pub(in crate::resolve) imported_classes: &'static [&'static str],
+    pub(in crate::resolve) imported_properties: &'static [&'static str],
+    pub(in crate::resolve) adapter: Tcgen05Adapter,
+    pub(in crate::resolve) source_contract: Tcgen05SourceContract,
+    pub(in crate::resolve) safe: bool,
+    pub(in crate::resolve) safe_reason: Option<&'static str>,
+    pub(in crate::resolve) memory: &'static str,
+    pub(in crate::resolve) modifiers: Vec<String>,
+    pub(in crate::resolve) operands: Vec<OperandPattern>,
+    pub(in crate::resolve) selection_record: Option<&'static str>,
+    pub(in crate::resolve) selection_asm: Option<&'static str>,
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn tcgen05_recipe(operation: Tcgen05Operation) -> Tcgen05Recipe {
+    const EMPTY: &[&str] = &[];
+    const F32_X4: &[&str] = &["f32", "f32", "f32", "f32"];
+    const F32_X32: &[&str] = &["f32"; 32];
+    const BASE_CLASSES: &[&str] = &["SDPatternOperator", "Intrinsic"];
+    const MMA_CLASSES: &[&str] = &[
+        "SDPatternOperator",
+        "Intrinsic",
+        "DefaultAttrsIntrinsic",
+        "DefaultAttrsIntrinsicFlags",
+    ];
+    const LOAD_CLASSES: &[&str] = &["SDPatternOperator", "Intrinsic", "NVVM_TCGEN05_LD"];
+    const CONVERGENT_ARG_MEMORY: &[&str] = &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"];
+    const CONVERGENT_INACCESSIBLE_ARG_MEMORY: &[&str] = &[
+        "IntrConvergent",
+        "IntrInaccessibleMemOrArgMemOnly",
+        "NoCapture<arg0>",
+    ];
+    const CONVERGENT_INACCESSIBLE_MEMORY: &[&str] = &["IntrConvergent", "IntrInaccessibleMemOnly"];
+    const ALLOC_PROPERTIES: &[&str] = &[
+        "IntrConvergent",
+        "IntrInaccessibleMemOrArgMemOnly",
+        "NoCapture<arg0>",
+        "WriteOnly<arg0>",
+    ];
+    const FENCE_PROPERTIES: &[&str] = &["IntrHasSideEffects", "IntrNoMem"];
+    const MMA_WS_PROPERTIES: &[&str] = &[
+        "ImmArg<arg5>",
+        "ImmArg<arg6>",
+        "ImmArg<arg7>",
+        "IntrArgMemOnly",
+        "Range<arg5,0,4>",
+        "Range<arg6,0,4>",
+        "Range<arg7,0,4>",
+        "ReadOnly<arg1>",
+        "WriteOnly<arg0>",
+    ];
+    const MMA_CG1_PROPERTIES: &[&str] = &[
+        "ImmArg<arg6>",
+        "ImmArg<arg7>",
+        "IntrArgMemOnly",
+        "Range<arg6,0,4>",
+        "Range<arg7,0,4>",
+        "WriteOnly<arg0>",
+    ];
+    const LOAD_PROPERTIES: &[&str] = &[
+        "ImmArg<arg1>",
+        "IntrArgMemOnly",
+        "IntrConvergent",
+        "NoCapture<arg0>",
+    ];
+
+    let (
+        abi_id,
+        id,
+        operation_key,
+        source_record,
+        llvm_symbol,
+        dialect_op_type,
+        dialect_op_name,
+        adapter,
+        source_contract,
+    ) = match operation {
+        Tcgen05Operation::Alloc => (
+            "i0343",
+            "tcgen05_alloc",
+            "tcgen05.alloc.cg1",
+            "int_nvvm_tcgen05_alloc_shared_cg1",
+            "llvm.nvvm.tcgen05.alloc.shared.cg1",
+            "Tcgen05AllocOp",
+            "nvvm.tcgen05_alloc",
+            Tcgen05Adapter::SharedPointerColumnsToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::Dealloc => (
+            "i0344",
+            "tcgen05_dealloc",
+            "tcgen05.dealloc.cg1",
+            "int_nvvm_tcgen05_dealloc_cg1",
+            "llvm.nvvm.tcgen05.dealloc.cg1",
+            "Tcgen05DeallocOp",
+            "nvvm.tcgen05_dealloc",
+            Tcgen05Adapter::TmemAddressColumnsToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::RelinquishAllocPermit => (
+            "i0345",
+            "tcgen05_relinquish_alloc_permit",
+            "tcgen05.relinquish_alloc_permit.cg1",
+            "int_nvvm_tcgen05_relinq_alloc_permit_cg1",
+            "llvm.nvvm.tcgen05.relinq.alloc.permit.cg1",
+            "Tcgen05RelinquishAllocPermitOp",
+            "nvvm.tcgen05_relinquish_alloc_permit",
+            Tcgen05Adapter::NoOperands,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::FenceBeforeThreadSync => (
+            "i0346",
+            "tcgen05_fence_before_thread_sync",
+            "tcgen05.fence.before_thread_sync",
+            "int_nvvm_tcgen05_fence_before_thread_sync",
+            "llvm.nvvm.tcgen05.fence.before.thread.sync",
+            "Tcgen05FenceBeforeThreadSyncOp",
+            "nvvm.tcgen05_fence_before_thread_sync",
+            Tcgen05Adapter::NoOperands,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::FenceAfterThreadSync => (
+            "i0347",
+            "tcgen05_fence_after_thread_sync",
+            "tcgen05.fence.after.thread.sync",
+            "int_nvvm_tcgen05_fence_after_thread_sync",
+            "llvm.nvvm.tcgen05.fence.after.thread.sync",
+            "Tcgen05FenceAfterThreadSyncOp",
+            "nvvm.tcgen05_fence_after_thread_sync",
+            Tcgen05Adapter::NoOperands,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::Commit => (
+            "i0348",
+            "tcgen05_commit",
+            "tcgen05.commit.cg1",
+            "int_nvvm_tcgen05_commit_cg1",
+            "llvm.nvvm.tcgen05.commit.cg1",
+            "Tcgen05CommitOp",
+            "nvvm.tcgen05_commit",
+            Tcgen05Adapter::BarrierPointerToVoid,
+            Tcgen05SourceContract::TablegenSelectionChangesPtx,
+        ),
+        Tcgen05Operation::CommitSharedCluster => (
+            "i0349",
+            "tcgen05_commit_shared_cluster",
+            "tcgen05.commit.shared_cluster.cg1",
+            "int_nvvm_tcgen05_commit_shared_cg1",
+            "llvm.nvvm.tcgen05.commit.shared.cg1",
+            "Tcgen05CommitSharedClusterOp",
+            "nvvm.tcgen05_commit_shared_cluster",
+            Tcgen05Adapter::BarrierPointerToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::MmaWsF16 => (
+            "i0350",
+            "tcgen05_mma_ws_f16",
+            "tcgen05.mma.ws.f16.cg1",
+            "int_nvvm_tcgen05_mma_ws_tensor",
+            "llvm.nvvm.tcgen05.mma.ws.tensor",
+            "Tcgen05MmaWsF16Op",
+            "nvvm.tcgen05_mma_ws_f16",
+            Tcgen05Adapter::MmaWsDropLegacyADescriptor,
+            Tcgen05SourceContract::TablegenSelectionChangesPtx,
+        ),
+        Tcgen05Operation::MmaF16 => (
+            "i0351",
+            "tcgen05_mma_f16",
+            "tcgen05.mma.f16.cg1",
+            "int_nvvm_tcgen05_mma_shared_disable_output_lane_cg1",
+            "llvm.nvvm.tcgen05.mma.shared.disable_output_lane.cg1",
+            "Tcgen05MmaF16Op",
+            "nvvm.tcgen05_mma_f16",
+            Tcgen05Adapter::MmaInjectZeroDisableLanes,
+            Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
+        ),
+        Tcgen05Operation::MmaWsBf16 => (
+            "i0352",
+            "tcgen05_mma_ws_bf16",
+            "tcgen05.mma.ws.bf16.cg1",
+            "int_nvvm_tcgen05_mma_ws_tensor",
+            "llvm.nvvm.tcgen05.mma.ws.tensor",
+            "Tcgen05MmaWsBf16Op",
+            "nvvm.tcgen05_mma_ws_bf16",
+            Tcgen05Adapter::MmaWsDropLegacyADescriptor,
+            Tcgen05SourceContract::TablegenSelectionChangesPtx,
+        ),
+        Tcgen05Operation::MmaWsTf32 => (
+            "i0353",
+            "tcgen05_mma_ws_tf32",
+            "tcgen05.mma.ws.tf32.cg1",
+            "int_nvvm_tcgen05_mma_ws_tensor",
+            "llvm.nvvm.tcgen05.mma.ws.tensor",
+            "Tcgen05MmaWsTf32Op",
+            "nvvm.tcgen05_mma_ws_tf32",
+            Tcgen05Adapter::MmaWsDropLegacyADescriptor,
+            Tcgen05SourceContract::TablegenSelectionChangesPtx,
+        ),
+        Tcgen05Operation::CpSmemToTmem => (
+            "i0354",
+            "tcgen05_cp_smem_to_tmem",
+            "tcgen05.cp.128x256b.cg1",
+            "int_nvvm_tcgen05_cp_128x256b_cg1",
+            "llvm.nvvm.tcgen05.cp.128x256b.cg1",
+            "Tcgen05CpSmemToTmemOp",
+            "nvvm.tcgen05_cp_smem_to_tmem",
+            Tcgen05Adapter::TmemDescriptorToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::Ld16x256bX8Pure => (
+            "i0355",
+            "tcgen05_ld_16x256b_x8_pure",
+            "tcgen05.ld.16x256b.x8",
+            "int_nvvm_tcgen05_ld_16x256b_x8",
+            "llvm.nvvm.tcgen05.ld.16x256b.x8",
+            "Tcgen05Ld16x256bX8PureOp",
+            "nvvm.tcgen05_ld_16x256b_x8_pure",
+            Tcgen05Adapter::TmemToF32x32,
+            Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
+        ),
+        Tcgen05Operation::Ld16x256bPure => (
+            "i0356",
+            "tcgen05_ld_16x256b_pure",
+            "tcgen05.ld.16x256b.x1",
+            "int_nvvm_tcgen05_ld_16x256b_x1",
+            "llvm.nvvm.tcgen05.ld.16x256b.x1",
+            "Tcgen05Ld16x256bPureOp",
+            "nvvm.tcgen05_ld_16x256b_pure",
+            Tcgen05Adapter::TmemToF32x4,
+            Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
+        ),
+        Tcgen05Operation::LoadWait => (
+            "i0357",
+            "tcgen05_load_wait",
+            "tcgen05.wait.ld",
+            "int_nvvm_tcgen05_wait_ld",
+            "llvm.nvvm.tcgen05.wait.ld",
+            "Tcgen05LoadWaitOp",
+            "nvvm.tcgen05_load_wait",
+            Tcgen05Adapter::NoOperands,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::StoreWait => (
+            "i0358",
+            "tcgen05_store_wait",
+            "tcgen05.wait.st",
+            "int_nvvm_tcgen05_wait_st",
+            "llvm.nvvm.tcgen05.wait.st",
+            "Tcgen05StoreWaitOp",
+            "nvvm.tcgen05_store_wait",
+            Tcgen05Adapter::NoOperands,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::AllocCg2 => (
+            "i0359",
+            "tcgen05_alloc_cg2",
+            "tcgen05.alloc.cg2",
+            "int_nvvm_tcgen05_alloc_shared_cg2",
+            "llvm.nvvm.tcgen05.alloc.shared.cg2",
+            "Tcgen05AllocCg2Op",
+            "nvvm.tcgen05_alloc_cg2",
+            Tcgen05Adapter::SharedPointerColumnsToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::DeallocCg2 => (
+            "i0360",
+            "tcgen05_dealloc_cg2",
+            "tcgen05.dealloc.cg2",
+            "int_nvvm_tcgen05_dealloc_cg2",
+            "llvm.nvvm.tcgen05.dealloc.cg2",
+            "Tcgen05DeallocCg2Op",
+            "nvvm.tcgen05_dealloc_cg2",
+            Tcgen05Adapter::TmemAddressColumnsToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::RelinquishAllocPermitCg2 => (
+            "i0361",
+            "tcgen05_relinquish_alloc_permit_cg2",
+            "tcgen05.relinquish_alloc_permit.cg2",
+            "int_nvvm_tcgen05_relinq_alloc_permit_cg2",
+            "llvm.nvvm.tcgen05.relinq.alloc.permit.cg2",
+            "Tcgen05RelinquishAllocPermitCg2Op",
+            "nvvm.tcgen05_relinquish_alloc_permit_cg2",
+            Tcgen05Adapter::NoOperands,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::MmaF16Cg2 => (
+            "i0362",
+            "tcgen05_mma_f16_cg2",
+            "tcgen05.mma.f16.cg2",
+            "int_nvvm_tcgen05_mma_shared_disable_output_lane_cg2",
+            "llvm.nvvm.tcgen05.mma.shared.disable_output_lane.cg2",
+            "Tcgen05MmaF16Cg2Op",
+            "nvvm.tcgen05_mma_f16_cg2",
+            Tcgen05Adapter::MmaInjectZeroDisableLanes,
+            Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection,
+        ),
+        Tcgen05Operation::CommitCg2 => (
+            "i0363",
+            "tcgen05_commit_cg2",
+            "tcgen05.commit.cg2",
+            "int_nvvm_tcgen05_commit_cg2",
+            "llvm.nvvm.tcgen05.commit.cg2",
+            "Tcgen05CommitCg2Op",
+            "nvvm.tcgen05_commit_cg2",
+            Tcgen05Adapter::BarrierPointerToVoid,
+            Tcgen05SourceContract::TablegenSelectionChangesPtx,
+        ),
+        Tcgen05Operation::CommitSharedClusterCg2 => (
+            "i0364",
+            "tcgen05_commit_shared_cluster_cg2",
+            "tcgen05.commit.shared_cluster.cg2",
+            "int_nvvm_tcgen05_commit_shared_cg2",
+            "llvm.nvvm.tcgen05.commit.shared.cg2",
+            "Tcgen05CommitSharedClusterCg2Op",
+            "nvvm.tcgen05_commit_shared_cluster_cg2",
+            Tcgen05Adapter::BarrierPointerToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::CommitMulticastCg2 => (
+            "i0365",
+            "tcgen05_commit_multicast_cg2",
+            "tcgen05.commit.multicast.cg2",
+            "int_nvvm_tcgen05_commit_mc_shared_cg2",
+            "llvm.nvvm.tcgen05.commit.mc.shared.cg2",
+            "Tcgen05CommitMulticastCg2Op",
+            "nvvm.tcgen05_commit_multicast_cg2",
+            Tcgen05Adapter::BarrierPointerMaskToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::CpSmemToTmemCg2 => (
+            "i0366",
+            "tcgen05_cp_smem_to_tmem_cg2",
+            "tcgen05.cp.128x256b.cg2",
+            "int_nvvm_tcgen05_cp_128x256b_cg2",
+            "llvm.nvvm.tcgen05.cp.128x256b.cg2",
+            "Tcgen05CpSmemToTmemCg2Op",
+            "nvvm.tcgen05_cp_smem_to_tmem_cg2",
+            Tcgen05Adapter::TmemDescriptorToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::CommitMulticast => (
+            "i0760",
+            "tcgen05_commit_multicast",
+            "tcgen05.commit.multicast.cg1",
+            "int_nvvm_tcgen05_commit_mc_shared_cg1",
+            "llvm.nvvm.tcgen05.commit.mc.shared.cg1",
+            "Tcgen05CommitMulticastOp",
+            "nvvm.tcgen05_commit_multicast",
+            Tcgen05Adapter::BarrierPointerMaskToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::ShiftDown => (
+            "i0761",
+            "tcgen05_shift_down",
+            "tcgen05.shift.down.cg1",
+            "int_nvvm_tcgen05_shift_down_cg1",
+            "llvm.nvvm.tcgen05.shift.down.cg1",
+            "Tcgen05ShiftDownOp",
+            "nvvm.tcgen05_shift_down",
+            Tcgen05Adapter::TmemAddressToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::ShiftDownCg2 => (
+            "i0762",
+            "tcgen05_shift_down_cg2",
+            "tcgen05.shift.down.cg2",
+            "int_nvvm_tcgen05_shift_down_cg2",
+            "llvm.nvvm.tcgen05.shift.down.cg2",
+            "Tcgen05ShiftDownCg2Op",
+            "nvvm.tcgen05_shift_down_cg2",
+            Tcgen05Adapter::TmemAddressToVoid,
+            Tcgen05SourceContract::ExactTablegenSelection,
+        ),
+        Tcgen05Operation::Ld | Tcgen05Operation::St | Tcgen05Operation::Mma => {
+            unreachable!("tcgen05 load/store variants use their compact recipes")
+        }
+    };
+
+    let cg2 = matches!(
+        operation,
+        Tcgen05Operation::AllocCg2
+            | Tcgen05Operation::DeallocCg2
+            | Tcgen05Operation::RelinquishAllocPermitCg2
+            | Tcgen05Operation::MmaF16Cg2
+            | Tcgen05Operation::CommitCg2
+            | Tcgen05Operation::CommitSharedClusterCg2
+            | Tcgen05Operation::CommitMulticastCg2
+            | Tcgen05Operation::CpSmemToTmemCg2
+            | Tcgen05Operation::ShiftDownCg2
+    );
+    let group = if cg2 { "cta_group::2" } else { "cta_group::1" };
+    let (
+        rust_arguments,
+        rust_result,
+        dialect_operands,
+        dialect_results,
+        llvm_arguments,
+        llvm_results,
+        imported_classes,
+        imported_properties,
+        safe,
+        safe_reason,
+        memory,
+        modifiers,
+        operands,
+        selection_record,
+        selection_asm,
+        summary,
+    ) = match operation {
+        Tcgen05Operation::Alloc | Tcgen05Operation::AllocCg2 => (
+            &["*mut u32", "u32"] as &[_],
+            "()",
+            &["ptr", "i32"] as &[_],
+            EMPTY,
+            &["shared_ptr", "i32"] as &[_],
+            EMPTY,
+            BASE_CLASSES,
+            ALLOC_PROPERTIES,
+            false,
+            None,
+            "write",
+            vec![
+                "alloc".into(),
+                group.into(),
+                "sync".into(),
+                "aligned".into(),
+                "shared::cta".into(),
+                "b32".into(),
+            ],
+            vec![OperandPattern::Address, OperandPattern::Register],
+            Some(if cg2 {
+                "TCGEN05_ALLOC_S64_CG2"
+            } else {
+                "TCGEN05_ALLOC_S64_CG1"
+            }),
+            Some(if cg2 {
+                "tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 \t[$dst], $ncols;"
+            } else {
+                "tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 \t[$dst], $ncols;"
+            }),
+            "Allocates tensor-memory columns and writes their address to shared memory.",
+        ),
+        Tcgen05Operation::Dealloc | Tcgen05Operation::DeallocCg2 => (
+            &["u32", "u32"] as &[_],
+            "()",
+            &["i32", "i32"] as &[_],
+            EMPTY,
+            &["tmem_ptr", "i32"] as &[_],
+            EMPTY,
+            BASE_CLASSES,
+            CONVERGENT_ARG_MEMORY,
+            false,
+            None,
+            "read_write",
+            vec![
+                "dealloc".into(),
+                group.into(),
+                "sync".into(),
+                "aligned".into(),
+                "b32".into(),
+            ],
+            vec![OperandPattern::Register, OperandPattern::Register],
+            Some(if cg2 {
+                "TCGEN05_DEALLOC_CG2"
+            } else {
+                "TCGEN05_DEALLOC_CG1"
+            }),
+            Some(if cg2 {
+                "tcgen05.dealloc.cta_group::2.sync.aligned.b32 \t$tmem_addr, $ncols;"
+            } else {
+                "tcgen05.dealloc.cta_group::1.sync.aligned.b32 \t$tmem_addr, $ncols;"
+            }),
+            "Releases tensor-memory columns allocated to the CTA group.",
+        ),
+        Tcgen05Operation::RelinquishAllocPermit | Tcgen05Operation::RelinquishAllocPermitCg2 => (
+            EMPTY,
+            "()",
+            EMPTY,
+            EMPTY,
+            EMPTY,
+            EMPTY,
+            BASE_CLASSES,
+            CONVERGENT_INACCESSIBLE_MEMORY,
+            true,
+            Some(
+                "The operation has no Rust memory operand and only releases this CTA group's allocation permit.",
+            ),
+            "read_write",
+            vec![
+                "relinquish_alloc_permit".into(),
+                group.into(),
+                "sync".into(),
+                "aligned".into(),
+            ],
+            vec![],
+            Some(if cg2 {
+                "TCGEN05_RELINQ_CG2"
+            } else {
+                "TCGEN05_RELINQ_CG1"
+            }),
+            Some(if cg2 {
+                "tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;"
+            } else {
+                "tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;"
+            }),
+            "Releases the CTA group's tensor-memory allocation permit.",
+        ),
+        Tcgen05Operation::FenceBeforeThreadSync | Tcgen05Operation::FenceAfterThreadSync => {
+            let before = operation == Tcgen05Operation::FenceBeforeThreadSync;
+            (
+                EMPTY,
+                "()",
+                EMPTY,
+                EMPTY,
+                EMPTY,
+                EMPTY,
+                BASE_CLASSES,
+                FENCE_PROPERTIES,
+                true,
+                Some("The operation only orders the calling thread's tcgen05 accesses."),
+                "none",
+                vec![if before {
+                    "fence::before_thread_sync".into()
+                } else {
+                    "fence::after_thread_sync".into()
+                }],
+                vec![],
+                Some(if before {
+                    "tcgen05_fence_before_thread_sync"
+                } else {
+                    "tcgen05_fence_after_thread_sync"
+                }),
+                Some(if before {
+                    "tcgen05.fence::before_thread_sync;"
+                } else {
+                    "tcgen05.fence::after_thread_sync;"
+                }),
+                if before {
+                    "Orders prior tcgen05 accesses before thread synchronization."
+                } else {
+                    "Orders later tcgen05 accesses after thread synchronization."
+                },
+            )
+        }
+        Tcgen05Operation::Commit
+        | Tcgen05Operation::CommitCg2
+        | Tcgen05Operation::CommitSharedCluster
+        | Tcgen05Operation::CommitSharedClusterCg2 => {
+            let shared = matches!(
+                operation,
+                Tcgen05Operation::CommitSharedCluster | Tcgen05Operation::CommitSharedClusterCg2
+            );
+            let llvm_args = if shared {
+                &["shared_ptr"] as &[_]
+            } else {
+                &["ptr"] as &[_]
+            };
+            let record = match (cg2, shared) {
+                (false, false) => "TCGEN05_COMMIT_CG1",
+                (true, false) => "TCGEN05_COMMIT_CG2",
+                (false, true) => "TCGEN05_COMMIT_S64_CG1",
+                (true, true) => "TCGEN05_COMMIT_S64_CG2",
+            };
+            let asm = match cg2 {
+                false => {
+                    "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];"
+                }
+                true => {
+                    "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];"
+                }
+            };
+            let mut modifiers = vec![
+                "commit".into(),
+                group.into(),
+                "mbarrier::arrive::one".into(),
+            ];
+            if shared {
+                modifiers.push("shared::cluster".into());
+            }
+            modifiers.push("b64".into());
+            (
+                &["*mut u64"] as &[_],
+                "()",
+                &["ptr"] as &[_],
+                EMPTY,
+                llvm_args,
+                EMPTY,
+                BASE_CLASSES,
+                CONVERGENT_INACCESSIBLE_ARG_MEMORY,
+                false,
+                None,
+                "read_write",
+                modifiers,
+                vec![OperandPattern::Address],
+                Some(record),
+                Some(asm),
+                if shared {
+                    "Commits tcgen05 completion to a cluster-shared mbarrier."
+                } else {
+                    "Commits tcgen05 completion to an mbarrier."
+                },
+            )
+        }
+        Tcgen05Operation::MmaWsF16 | Tcgen05Operation::MmaWsBf16 | Tcgen05Operation::MmaWsTf32 => {
+            let kind = if operation == Tcgen05Operation::MmaWsTf32 {
+                "kind::tf32"
+            } else {
+                "kind::f16"
+            };
+            (
+                &["u32", "u32", "u64", "u64", "u32", "bool"] as &[_],
+                "()",
+                &["i32", "i32", "i64", "i64", "i32", "i1"] as &[_],
+                EMPTY,
+                &[
+                    "tmem_ptr", "tmem_ptr", "i64", "i32", "i1", "i32", "i32", "i32",
+                ] as &[_],
+                EMPTY,
+                MMA_CLASSES,
+                MMA_WS_PROPERTIES,
+                false,
+                None,
+                "read_write",
+                vec![
+                    "mma".into(),
+                    "ws".into(),
+                    "cta_group::1".into(),
+                    kind.into(),
+                ],
+                vec![
+                    OperandPattern::Address,
+                    OperandPattern::Address,
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                    OperandPattern::Exact {
+                        value: "%enable_pred".into(),
+                    },
+                ],
+                None,
+                None,
+                match operation {
+                    Tcgen05Operation::MmaWsF16 => "Issues warp-specialized f16 tensor-memory MMA.",
+                    Tcgen05Operation::MmaWsBf16 => {
+                        "Issues warp-specialized bf16 tensor-memory MMA using the f16 instruction class."
+                    }
+                    _ => "Issues warp-specialized tf32 tensor-memory MMA.",
+                },
+            )
+        }
+        Tcgen05Operation::MmaF16 | Tcgen05Operation::MmaF16Cg2 => (
+            &["u32", "u64", "u64", "u32", "bool"] as &[_],
+            "()",
+            &["i32", "i64", "i64", "i32", "i1"] as &[_],
+            EMPTY,
+            if cg2 {
+                &["tmem_ptr", "i64", "i64", "i32", "i1", "v8i32", "i32", "i32"] as &[_]
+            } else {
+                &["tmem_ptr", "i64", "i64", "i32", "i1", "v4i32", "i32", "i32"] as &[_]
+            },
+            EMPTY,
+            MMA_CLASSES,
+            MMA_CG1_PROPERTIES,
+            false,
+            None,
+            "write",
+            vec!["mma".into(), group.into(), "kind::f16".into()],
+            vec![
+                OperandPattern::Address,
+                OperandPattern::Register,
+                OperandPattern::Register,
+                OperandPattern::Register,
+                OperandPattern::Exact {
+                    value: if cg2 {
+                        "{%z, %z, %z, %z, %z, %z, %z, %z}"
+                    } else {
+                        "{%z, %z, %z, %z}"
+                    }
+                    .into(),
+                },
+                OperandPattern::Exact {
+                    value: "%enable_pred".into(),
+                },
+            ],
+            None,
+            None,
+            "Issues f16 tensor-memory MMA with zeroed disable-output-lane controls.",
+        ),
+        Tcgen05Operation::CpSmemToTmem | Tcgen05Operation::CpSmemToTmemCg2 => (
+            &["u32", "u64"] as &[_],
+            "()",
+            &["i32", "i64"] as &[_],
+            EMPTY,
+            &["tmem_ptr", "i64"] as &[_],
+            EMPTY,
+            BASE_CLASSES,
+            CONVERGENT_INACCESSIBLE_ARG_MEMORY,
+            false,
+            None,
+            "read_write",
+            vec!["cp".into(), group.into(), "128x256b".into()],
+            vec![OperandPattern::Address, OperandPattern::Register],
+            Some(if cg2 {
+                "TCGEN05_CP_128x256b_cg2"
+            } else {
+                "TCGEN05_CP_128x256b_cg1"
+            }),
+            Some(if cg2 {
+                "tcgen05.cp.cta_group::2.128x256b \t[$tmem_addr], $sdesc;"
+            } else {
+                "tcgen05.cp.cta_group::1.128x256b \t[$tmem_addr], $sdesc;"
+            }),
+            "Copies one 128x256-bit tile from shared memory to tensor memory.",
+        ),
+        Tcgen05Operation::Ld16x256bX8Pure | Tcgen05Operation::Ld16x256bPure => {
+            let x8 = operation == Tcgen05Operation::Ld16x256bX8Pure;
+            (
+                &["u32"] as &[_],
+                if x8 { "[f32; 32]" } else { "[f32; 4]" },
+                &["i32"] as &[_],
+                if x8 { F32_X32 } else { F32_X4 },
+                &["tmem_ptr", "i1"] as &[_],
+                if x8 {
+                    &["v32i32"] as &[_]
+                } else {
+                    &["v4i32"] as &[_]
+                },
+                LOAD_CLASSES,
+                LOAD_PROPERTIES,
+                false,
+                None,
+                "read",
+                vec![
+                    "ld".into(),
+                    "sync".into(),
+                    "aligned".into(),
+                    "16x256b".into(),
+                    if x8 { "x8".into() } else { "x1".into() },
+                    "b32".into(),
+                ],
+                vec![
+                    OperandPattern::RegisterList {
+                        length: if x8 { 32 } else { 4 },
+                    },
+                    OperandPattern::Address,
+                ],
+                None,
+                None,
+                if x8 {
+                    "Loads 32 f32 register values from tensor memory."
+                } else {
+                    "Loads four f32 register values from tensor memory."
+                },
+            )
+        }
+        Tcgen05Operation::LoadWait | Tcgen05Operation::StoreWait => {
+            let load = operation == Tcgen05Operation::LoadWait;
+            (
+                EMPTY,
+                "()",
+                EMPTY,
+                EMPTY,
+                EMPTY,
+                EMPTY,
+                BASE_CLASSES,
+                CONVERGENT_INACCESSIBLE_MEMORY,
+                true,
+                Some("The operation only waits for the calling thread's prior tcgen05 access."),
+                "read_write",
+                vec![
+                    if load {
+                        "wait::ld".into()
+                    } else {
+                        "wait::st".into()
+                    },
+                    "sync".into(),
+                    "aligned".into(),
+                ],
+                vec![],
+                Some(if load {
+                    "tcgen05_wait_ld"
+                } else {
+                    "tcgen05_wait_st"
+                }),
+                Some(if load {
+                    "tcgen05.wait::ld.sync.aligned;"
+                } else {
+                    "tcgen05.wait::st.sync.aligned;"
+                }),
+                if load {
+                    "Waits for prior tensor-memory loads to complete."
+                } else {
+                    "Waits for prior tensor-memory stores to complete."
+                },
+            )
+        }
+        Tcgen05Operation::CommitMulticast | Tcgen05Operation::CommitMulticastCg2 => (
+            &["*mut u64", "u16"] as &[_],
+            "()",
+            &["ptr", "i16"] as &[_],
+            EMPTY,
+            &["shared_ptr", "i16"] as &[_],
+            EMPTY,
+            BASE_CLASSES,
+            CONVERGENT_INACCESSIBLE_ARG_MEMORY,
+            false,
+            None,
+            "read_write",
+            vec![
+                "commit".into(),
+                group.into(),
+                "mbarrier::arrive::one".into(),
+                "shared::cluster".into(),
+                "multicast::cluster".into(),
+                "b64".into(),
+            ],
+            vec![OperandPattern::Address, OperandPattern::Register],
+            Some(if cg2 {
+                "TCGEN05_COMMIT_S64_CG2_MC"
+            } else {
+                "TCGEN05_COMMIT_S64_CG1_MC"
+            }),
+            Some(if cg2 {
+                "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;"
+            } else {
+                "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;"
+            }),
+            "Commits tcgen05 completion to the selected cluster mbarriers.",
+        ),
+        Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2 => (
+            &["u32"] as &[_],
+            "()",
+            &["i32"] as &[_],
+            EMPTY,
+            &["tmem_ptr"] as &[_],
+            EMPTY,
+            BASE_CLASSES,
+            CONVERGENT_ARG_MEMORY,
+            false,
+            None,
+            "read_write",
+            vec!["shift".into(), group.into(), "down".into()],
+            vec![OperandPattern::Address],
+            Some(if cg2 {
+                "TCGEN05_SHIFT_CG2"
+            } else {
+                "TCGEN05_SHIFT_CG1"
+            }),
+            Some(if cg2 {
+                "tcgen05.shift.cta_group::2.down \t[$tmem_addr];"
+            } else {
+                "tcgen05.shift.cta_group::1.down \t[$tmem_addr];"
+            }),
+            "Shifts tensor-memory rows down by one row.",
+        ),
+        Tcgen05Operation::Ld | Tcgen05Operation::St | Tcgen05Operation::Mma => {
+            unreachable!("tcgen05 load/store variants use their compact recipes")
+        }
+    };
+
+    Tcgen05Recipe {
+        operation,
+        abi_id,
+        id,
+        operation_key,
+        source_record,
+        llvm_symbol,
+        rust_arguments,
+        rust_result,
+        dialect_op_type,
+        dialect_op_name,
+        dialect_operands,
+        dialect_results,
+        llvm_arguments,
+        llvm_results,
+        imported_classes,
+        imported_properties,
+        adapter,
+        source_contract,
+        safe,
+        safe_reason,
+        memory,
+        modifiers,
+        operands,
+        selection_record,
+        selection_asm,
+        summary,
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/threadfence.rs b/crates/cuda-intrinsics-gen/src/resolve/families/threadfence.rs
new file mode 100644
index 0000000000..d83e1741ac
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/threadfence.rs
@@ -0,0 +1,363 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedIntrinsic, IntrinsicBackend, OverlayBackendLowering,
+    OverlayIntrinsic, RuntimeValidation, ThreadfenceAdmission, ThreadfenceScope,
+};
+use crate::ptx::InstructionPattern;
+use anyhow::{Result, ensure};
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) struct ThreadfenceRecipe {
+    pub(in crate::resolve) scope: ThreadfenceScope,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) selection_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) ptx_level: &'static str,
+    pub(in crate::resolve) execution_scope: &'static str,
+    pub(in crate::resolve) minimum_ptx: &'static str,
+    pub(in crate::resolve) minimum_sm: Option<&'static str>,
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn threadfence_recipe(scope: ThreadfenceScope) -> ThreadfenceRecipe {
+    match scope {
+        ThreadfenceScope::Cta => ThreadfenceRecipe {
+            scope,
+            abi_id: "i0298",
+            id: "threadfence_block",
+            operation_key: "memory.fence.cta.sc",
+            source_record: "int_nvvm_membar_cta",
+            selection_record: "INT_MEMBAR_CTA",
+            llvm_symbol: "llvm.nvvm.membar.cta",
+            dialect_op_type: "ThreadfenceBlockOp",
+            dialect_op_name: "nvvm.threadfence_block",
+            ptx_level: "cta",
+            execution_scope: "cta",
+            minimum_ptx: "1.4",
+            minimum_sm: None,
+            summary: "Orders this thread's memory operations for observers in its CTA.",
+        },
+        ThreadfenceScope::Device => ThreadfenceRecipe {
+            scope,
+            abi_id: "i0299",
+            id: "threadfence",
+            operation_key: "memory.fence.device.sc",
+            source_record: "int_nvvm_membar_gl",
+            selection_record: "INT_MEMBAR_GL",
+            llvm_symbol: "llvm.nvvm.membar.gl",
+            dialect_op_type: "ThreadfenceOp",
+            dialect_op_name: "nvvm.threadfence",
+            ptx_level: "gl",
+            execution_scope: "device",
+            minimum_ptx: "1.4",
+            minimum_sm: None,
+            summary: "Orders this thread's memory operations for observers on its GPU.",
+        },
+        ThreadfenceScope::System => ThreadfenceRecipe {
+            scope,
+            abi_id: "i0300",
+            id: "threadfence_system",
+            operation_key: "memory.fence.system.sc",
+            source_record: "int_nvvm_membar_sys",
+            selection_record: "INT_MEMBAR_SYS",
+            llvm_symbol: "llvm.nvvm.membar.sys",
+            dialect_op_type: "ThreadfenceSystemOp",
+            dialect_op_name: "nvvm.threadfence_system",
+            ptx_level: "sys",
+            execution_scope: "system",
+            minimum_ptx: "2.0",
+            minimum_sm: Some("sm_20"),
+            summary: "Orders this thread's memory operations for system-wide observers.",
+        },
+    }
+}
+
+pub(in crate::resolve) fn threadfence_scope_for_id(id: &str) -> Option<ThreadfenceScope> {
+    match id {
+        "threadfence_block" => Some(ThreadfenceScope::Cta),
+        "threadfence" => Some(ThreadfenceScope::Device),
+        "threadfence_system" => Some(ThreadfenceScope::System),
+        _ => None,
+    }
+}
+
+pub(in crate::resolve) fn expand_threadfence_admission(
+    admission: &ThreadfenceAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "threadfence runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact threadfence admission requires both backend evidence profiles"
+    );
+    let expected_scopes = [
+        ThreadfenceScope::Cta,
+        ThreadfenceScope::Device,
+        ThreadfenceScope::System,
+    ];
+    let actual_scopes = admission
+        .variants
+        .iter()
+        .map(|variant| variant.scope)
+        .collect::<Vec<_>>();
+    ensure!(
+        actual_scopes == expected_scopes,
+        "compact threadfence admission must contain each reviewed scope exactly once in canonical order"
+    );
+
+    admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = threadfence_recipe(variant.scope);
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must keep reserved ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: variant.abi_id.clone(),
+                operation_key: recipe.operation_key.into(),
+                family: "sync".into(),
+                source: None,
+                source_record: Some(recipe.source_record.into()),
+                rust_module: "fence".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments: vec![],
+                rust_result: "()".into(),
+                safe: true,
+                must_use: false,
+                safe_allowlist_reason: Some(
+                    "a fence only orders the calling thread's memory operations and has no caller preconditions"
+                        .into(),
+                ),
+                public_rust_path: format!("cuda_intrinsics::fence::{}", recipe.id),
+                compatibility_rust_paths: vec![
+                    format!("cuda_device::fence::{}", recipe.id),
+                    format!("cuda_device::{}", recipe.id),
+                ],
+                dialect_op_type: recipe.dialect_op_type.into(),
+                dialect_op_name: recipe.dialect_op_name.into(),
+                dialect_operands: vec![],
+                dialect_results: vec![],
+                llvm_symbol: Some(recipe.llvm_symbol.into()),
+                resolved_llvm_symbol: None,
+                llvm_arguments: vec![],
+                llvm_results: vec![],
+                pure: false,
+                memory: "read_write".into(),
+                convergent: false,
+                execution_scope: recipe.execution_scope.into(),
+                minimum_ptx: recipe.minimum_ptx.into(),
+                minimum_sm: recipe.minimum_sm.map(Into::into),
+                ptx_result: "()".into(),
+                targets: "all".into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section:
+                    "9.7.14.4 Parallel Synchronization and Communication Instructions: membar / fence"
+                        .into(),
+                ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-membar-fence".into(),
+                lowering: "direct_nvvm".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: BackendLoweringMechanism::TypedNvvm,
+                        evidence_profile: admission.llvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some("3.2".into()),
+                        minimum_sm: Some("sm_20".into()),
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::TypedNvvm,
+                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some("7.0".into()),
+                        minimum_sm: Some("sm_80".into()),
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: None,
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: None,
+                expected_ptx: InstructionPattern {
+                    mnemonic: "membar".into(),
+                    modifiers: vec![recipe.ptx_level.into()],
+                    operands: vec![],
+                },
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn validate_threadfence_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+    scope: ThreadfenceScope,
+) -> Result<()> {
+    let recipe = threadfence_recipe(scope);
+    ensure!(
+        recipe.scope == scope
+            && policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} threadfence identity does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "fence"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments.is_empty()
+            && policy.rust_result == "()"
+            && policy.safe
+            && !policy.must_use
+            && policy.public_rust_path == format!("cuda_intrinsics::fence::{}", recipe.id)
+            && policy.compatibility_rust_paths
+                == [
+                    format!("cuda_device::fence::{}", recipe.id),
+                    format!("cuda_device::{}", recipe.id),
+                ],
+        "{} threadfence Rust API does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands.is_empty()
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments.is_empty()
+            && policy.llvm_results.is_empty()
+            && policy.lowering == "direct_nvvm",
+        "{} threadfence carrier or lowering does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.properties == ["IntrNoCallback"]
+            && !policy.pure
+            && policy.memory == "read_write"
+            && !policy.convergent
+            && policy.execution_scope == recipe.execution_scope,
+        "{} threadfence effects disagree with the imported declaration",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == recipe.minimum_sm
+            && policy.ptx_result == "()"
+            && policy.targets == "all"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.14.4 Parallel Synchronization and Communication Instructions: membar / fence"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-membar-fence",
+        "{} threadfence target floor or PTX provenance changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx
+            == (InstructionPattern {
+                mnemonic: "membar".into(),
+                modifiers: vec![recipe.ptx_level.into()],
+                operands: vec![],
+            }),
+        "{} expected PTX does not match its closed threadfence scope",
+        policy.id
+    );
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && policy.backend_lowerings.iter().any(|route| {
+                route.backend == IntrinsicBackend::LlvmNvptx
+                    && route.mechanism == BackendLoweringMechanism::TypedNvvm
+                    && route.minimum_ptx.as_deref() == Some("3.2")
+                    && route.minimum_sm.as_deref() == Some("sm_20")
+            })
+            && policy.backend_lowerings.iter().any(|route| {
+                route.backend == IntrinsicBackend::LibNvvm
+                    && route.mechanism == BackendLoweringMechanism::TypedNvvm
+                    && route.minimum_ptx.as_deref() == Some("7.0")
+                    && route.minimum_sm.as_deref() == Some("sm_80")
+            }),
+        "{} must keep both reviewed typed threadfence routes",
+        policy.id
+    );
+    ensure!(
+        policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.cp_async_mbarrier.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.register_mma.is_none()
+            && policy.sparse_mma.is_none()
+            && policy.prmt.is_none()
+            && policy.cluster_barrier.is_none()
+            && policy.special_register.is_none()
+            && policy.debug_control.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with threadfence",
+        policy.id
+    );
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/tma.rs b/crates/cuda-intrinsics-gen/src/resolve/families/tma.rs
new file mode 100644
index 0000000000..0f7d8a1d09
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/tma.rs
@@ -0,0 +1,1930 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedAddressSpace, ImportedIntrinsic, IntrinsicBackend,
+    OverlayBackendLowering, OverlayIntrinsic, RuntimeValidation, Tma, TmaAdapter, TmaAdmission,
+    TmaOperation, TmaReduction, TmaReductionAdmissionVariant, TmaReductionLoadMode,
+    TmaReductionOperation,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use anyhow::{Context, Result, ensure};
+
+use super::*;
+use crate::resolve::abi_ledger::*;
+use crate::resolve::guards::*;
+
+pub(in crate::resolve) const TMA_BLACKWELL_TARGETS: &str = "sm_100a|sm_101a|sm_103a|sm_110a";
+pub(in crate::resolve) const TENSOR_MAP_REPLACE_TARGETS: &str =
+    "sm_100a|sm_100f|sm_103a|sm_103f|sm_110a|sm_110f|sm_120a|sm_120f|sm_121a|sm_121f|sm_90a";
+pub(in crate::resolve) const TMA_OPERATIONS: [TmaOperation; 47] = [
+    TmaOperation::G2sTile1d,
+    TmaOperation::G2sTile2d,
+    TmaOperation::G2sTile2dMulticast,
+    TmaOperation::G2sTile2dMulticastCg2,
+    TmaOperation::G2sTile3d,
+    TmaOperation::G2sTile4d,
+    TmaOperation::G2sTile5d,
+    TmaOperation::S2gTile1d,
+    TmaOperation::S2gTile2d,
+    TmaOperation::S2gTile3d,
+    TmaOperation::S2gTile4d,
+    TmaOperation::S2gTile5d,
+    TmaOperation::CommitGroup,
+    TmaOperation::WaitGroup,
+    TmaOperation::WaitGroupRead,
+    TmaOperation::PrefetchTensorMap,
+    TmaOperation::PrefetchTile1d,
+    TmaOperation::PrefetchTile2d,
+    TmaOperation::PrefetchTile3d,
+    TmaOperation::PrefetchTile4d,
+    TmaOperation::PrefetchTile5d,
+    TmaOperation::PrefetchTileGather4TwoDimensional,
+    TmaOperation::ReplaceBoxDim,
+    TmaOperation::ReplaceElementStride,
+    TmaOperation::ReplaceElementType,
+    TmaOperation::ReplaceFillMode,
+    TmaOperation::ReplaceGlobalAddress,
+    TmaOperation::ReplaceGlobalDim,
+    TmaOperation::ReplaceGlobalStride,
+    TmaOperation::ReplaceInterleaveLayout,
+    TmaOperation::ReplaceRank,
+    TmaOperation::ReplaceSwizzleAtomicity,
+    TmaOperation::ReplaceSwizzleMode,
+    TmaOperation::FenceProxyTensorMapAcquireCluster,
+    TmaOperation::FenceProxyTensorMapAcquireCta,
+    TmaOperation::FenceProxyTensorMapAcquireGpu,
+    TmaOperation::FenceProxyTensorMapAcquireSystem,
+    TmaOperation::FenceProxyTensorMapReleaseCluster,
+    TmaOperation::FenceProxyTensorMapReleaseCta,
+    TmaOperation::FenceProxyTensorMapReleaseGpu,
+    TmaOperation::FenceProxyTensorMapReleaseSystem,
+    TmaOperation::PrefetchTile1dCacheHint,
+    TmaOperation::PrefetchTile2dCacheHint,
+    TmaOperation::PrefetchTile3dCacheHint,
+    TmaOperation::PrefetchTile4dCacheHint,
+    TmaOperation::PrefetchTile5dCacheHint,
+    TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint,
+];
+
+pub(in crate::resolve) const TMA_REDUCTION_OPERATIONS: [TmaReductionOperation; 8] = [
+    TmaReductionOperation::Add,
+    TmaReductionOperation::And,
+    TmaReductionOperation::Dec,
+    TmaReductionOperation::Inc,
+    TmaReductionOperation::Max,
+    TmaReductionOperation::Min,
+    TmaReductionOperation::Or,
+    TmaReductionOperation::Xor,
+];
+
+pub(in crate::resolve) fn tma_reduction_matrix() -> Vec<TmaReduction> {
+    let mut reductions = Vec::with_capacity(64);
+    for operation in TMA_REDUCTION_OPERATIONS {
+        for dimensions in 1..=5 {
+            reductions.push(TmaReduction {
+                operation,
+                load_mode: TmaReductionLoadMode::Tile,
+                dimensions,
+            });
+        }
+        for dimensions in 3..=5 {
+            reductions.push(TmaReduction {
+                operation,
+                load_mode: TmaReductionLoadMode::Im2col,
+                dimensions,
+            });
+        }
+    }
+    reductions
+}
+
+#[cfg(test)]
+pub(in crate::resolve) fn tma_reduction_admission_variants() -> Vec<TmaReductionAdmissionVariant> {
+    tma_reduction_matrix()
+        .into_iter()
+        .enumerate()
+        .map(|(index, reduction)| TmaReductionAdmissionVariant {
+            // Preserve the repository's current ledger assignments in this test fixture.
+            abi_id: format!("i{:04}", 923 + index),
+            operation: reduction.operation,
+            load_mode: reduction.load_mode,
+            dimensions: reduction.dimensions,
+        })
+        .collect()
+}
+
+pub(in crate::resolve) fn tma_reduction_operation_name(
+    operation: TmaReductionOperation,
+) -> (&'static str, &'static str) {
+    match operation {
+        TmaReductionOperation::Add => ("add", "Add"),
+        TmaReductionOperation::And => ("and", "And"),
+        TmaReductionOperation::Dec => ("dec", "Dec"),
+        TmaReductionOperation::Inc => ("inc", "Inc"),
+        TmaReductionOperation::Max => ("max", "Max"),
+        TmaReductionOperation::Min => ("min", "Min"),
+        TmaReductionOperation::Or => ("or", "Or"),
+        TmaReductionOperation::Xor => ("xor", "Xor"),
+    }
+}
+
+pub(in crate::resolve) fn tma_reduction_load_mode_name(
+    load_mode: TmaReductionLoadMode,
+) -> (&'static str, &'static str, &'static str) {
+    match load_mode {
+        TmaReductionLoadMode::Tile => ("tile", "Tile", "tile"),
+        TmaReductionLoadMode::Im2col => ("im2col", "Im2col", "im2col_no_offs"),
+    }
+}
+
+pub(in crate::resolve) struct TmaReductionRecipe {
+    id: String,
+    operation_key: String,
+    source_record: String,
+    llvm_symbol: String,
+    rust_arguments: Vec<&'static str>,
+    dialect_op_type: String,
+    dialect_op_name: String,
+    dialect_operands: Vec<&'static str>,
+    llvm_arguments: Vec<&'static str>,
+    modifiers: Vec<String>,
+    operands: Vec<OperandPattern>,
+    summary: String,
+}
+
+pub(in crate::resolve) fn tma_reduction_recipe(
+    reduction: TmaReduction,
+) -> Result<TmaReductionRecipe> {
+    ensure!(
+        (1..=5).contains(&reduction.dimensions),
+        "TMA reduction dimensionality must be in 1..=5"
+    );
+    ensure!(
+        reduction.load_mode != TmaReductionLoadMode::Im2col || reduction.dimensions >= 3,
+        "TMA reduction im2col mode requires at least three dimensions"
+    );
+
+    let (operation, operation_camel) = tma_reduction_operation_name(reduction.operation);
+    let (load_mode, load_mode_camel, ptx_load_mode) =
+        tma_reduction_load_mode_name(reduction.load_mode);
+    let dimensions = reduction.dimensions as usize;
+    let id = format!(
+        "cp_async_bulk_tensor_reduce_{operation}_{load_mode}_{}d",
+        reduction.dimensions
+    );
+    let mut rust_arguments = vec!["*const u8", "*const u8"];
+    rust_arguments.extend(std::iter::repeat_n("i32", dimensions));
+    let mut dialect_operands = vec!["ptr", "ptr"];
+    dialect_operands.extend(std::iter::repeat_n("i32", dimensions));
+    let mut llvm_arguments = vec!["shared_ptr", "ptr"];
+    llvm_arguments.extend(std::iter::repeat_n("i32", dimensions));
+    llvm_arguments.extend(["i64", "i1"]);
+
+    Ok(TmaReductionRecipe {
+        operation_key: format!(
+            "memory.reduce.async.bulk.tensor.{operation}.{load_mode}.{}d",
+            reduction.dimensions
+        ),
+        source_record: format!(
+            "int_nvvm_cp_async_bulk_tensor_reduce_{operation}_{load_mode}_{}d",
+            reduction.dimensions
+        ),
+        llvm_symbol: format!(
+            "llvm.nvvm.cp.async.bulk.tensor.reduce.{operation}.{load_mode}.{}d",
+            reduction.dimensions
+        ),
+        dialect_op_type: format!(
+            "CpAsyncBulkTensorReduce{operation_camel}{load_mode_camel}{}dOp",
+            reduction.dimensions
+        ),
+        dialect_op_name: format!(
+            "nvvm.cp_async_bulk_tensor_reduce_{operation}_{load_mode}_{}d",
+            reduction.dimensions
+        ),
+        rust_arguments,
+        dialect_operands,
+        llvm_arguments,
+        modifiers: vec![
+            "reduce".into(),
+            "async".into(),
+            "bulk".into(),
+            "tensor".into(),
+            format!("{}d", reduction.dimensions),
+            "global".into(),
+            "shared::cta".into(),
+            operation.into(),
+            ptx_load_mode.into(),
+            "bulk_group".into(),
+        ],
+        operands: vec![OperandPattern::Address, OperandPattern::Address],
+        summary: format!(
+            "Starts a TMA tensor {operation} reduction from shared to global memory in {load_mode} mode."
+        ),
+        id,
+    })
+}
+
+pub(in crate::resolve) fn expand_tma_reduction_variant(
+    admission: &TmaAdmission,
+    variant: &TmaReductionAdmissionVariant,
+) -> Result<OverlayIntrinsic> {
+    validate_abi_id(&variant.abi_id)?;
+    let reduction = TmaReduction {
+        operation: variant.operation,
+        load_mode: variant.load_mode,
+        dimensions: variant.dimensions,
+    };
+    let recipe = tma_reduction_recipe(reduction)?;
+
+    Ok(OverlayIntrinsic {
+        id: recipe.id.clone(),
+        abi_id: variant.abi_id.clone(),
+        operation_key: recipe.operation_key.clone(),
+        family: "tma".into(),
+        source: None,
+        source_record: Some(recipe.source_record.clone()),
+        rust_module: "tma".into(),
+        rust_name: recipe.id.clone(),
+        rust_arguments: recipe
+            .rust_arguments
+            .iter()
+            .map(|value| (*value).into())
+            .collect(),
+        rust_result: "()".into(),
+        safe: false,
+        must_use: false,
+        safe_allowlist_reason: None,
+        public_rust_path: format!("cuda_intrinsics::tma::{}", recipe.id),
+        compatibility_rust_paths: vec![format!("cuda_device::tma::{}", recipe.id)],
+        dialect_op_type: recipe.dialect_op_type.clone(),
+        dialect_op_name: recipe.dialect_op_name.clone(),
+        dialect_operands: recipe
+            .dialect_operands
+            .iter()
+            .map(|value| (*value).into())
+            .collect(),
+        dialect_results: vec![],
+        llvm_symbol: Some(recipe.llvm_symbol.clone()),
+        resolved_llvm_symbol: None,
+        llvm_arguments: recipe
+            .llvm_arguments
+            .iter()
+            .map(|value| (*value).into())
+            .collect(),
+        llvm_results: vec![],
+        pure: false,
+        memory: "read_write".into(),
+        convergent: true,
+        execution_scope: "thread".into(),
+        minimum_ptx: "8.0".into(),
+        minimum_sm: Some("sm_90".into()),
+        ptx_result: "()".into(),
+        targets: "all".into(),
+        ptx_isa_version: "9.3".into(),
+        ptx_isa_section:
+        "9.7.9.26.5.3 Data Movement and Conversion Instructions: cp.reduce.async.bulk.tensor"
+            .into(),
+        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor".into(),
+        lowering: "generated_tma".into(),
+        backend_lowerings: vec![
+            OverlayBackendLowering {
+                backend: IntrinsicBackend::LlvmNvptx,
+                mechanism: BackendLoweringMechanism::TypedNvvm,
+                evidence_profile: admission
+                    .reduce_llvm_evidence_profile
+                    .as_ref()
+                    .expect("validated TMA reduction LLVM evidence profile")
+                    .clone(),
+                targets: None,
+                minimum_ptx: Some("8.0".into()),
+                minimum_sm: Some("sm_90".into()),
+            },
+            OverlayBackendLowering {
+                backend: IntrinsicBackend::LibNvvm,
+                mechanism: BackendLoweringMechanism::InlinePtx,
+                evidence_profile: admission
+                    .reduce_libnvvm_evidence_profile
+                    .as_ref()
+                    .expect("validated TMA reduction libNVVM evidence profile")
+                    .clone(),
+                targets: None,
+                minimum_ptx: Some("8.0".into()),
+                minimum_sm: Some("sm_90".into()),
+            },
+        ],
+        packed_atomic: None,
+        redux: None,
+        vote: None,
+        active_mask: None,
+        warp_match: None,
+        warp_barrier: None,
+        warp_shuffle: None,
+        dot_product: None,
+        packed_alu: None,
+        integer_minmax: None,
+        packed_conversion: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cp_async_copy: None,
+        cp_async_control: None,
+        cp_async_mbarrier: None,
+        mbarrier_basic: None,
+        movmatrix: None,
+        mbarrier_extended: None,
+        register_mma: None,
+        sparse_mma: None,
+        prmt: None,
+        cluster_barrier: None,
+        wgmma_control: None,
+        special_register: None,
+        debug_control: None,
+        cluster_memory: None,
+        clc: None,
+        tma: Some(Tma {
+            operation: TmaOperation::Reduce,
+            reduction: Some(reduction),
+            adapter: TmaAdapter::ReductionPointersCoordinatesInjectDefaults,
+            runtime_validation: admission.runtime_validation,
+        }),
+        tcgen05: None,
+        ldmatrix_variant: None,
+        ldmatrix_safety: None,
+        ldmatrix_adapter: None,
+        selected_address_space: None,
+        expected_ptx: InstructionPattern {
+            mnemonic: "cp".into(),
+            modifiers: recipe.modifiers,
+            operands: recipe.operands,
+        },
+        summary: recipe.summary,
+    })
+}
+
+pub(in crate::resolve) struct TmaRecipe {
+    pub(in crate::resolve) operation: TmaOperation,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) resolved_llvm_symbol: Option<String>,
+    pub(in crate::resolve) selected_address_space: Option<ImportedAddressSpace>,
+    pub(in crate::resolve) llvm_mechanism: BackendLoweringMechanism,
+    pub(in crate::resolve) rust_arguments: Vec<&'static str>,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) dialect_operands: Vec<&'static str>,
+    pub(in crate::resolve) llvm_arguments: Vec<&'static str>,
+    pub(in crate::resolve) adapter: TmaAdapter,
+    pub(in crate::resolve) safe: bool,
+    pub(in crate::resolve) safe_reason: Option<&'static str>,
+    pub(in crate::resolve) convergent: bool,
+    pub(in crate::resolve) minimum_ptx: &'static str,
+    pub(in crate::resolve) minimum_sm: Option<&'static str>,
+    pub(in crate::resolve) targets: &'static str,
+    pub(in crate::resolve) memory: &'static str,
+    pub(in crate::resolve) ptx_isa_section: &'static str,
+    pub(in crate::resolve) ptx_isa_url: &'static str,
+    pub(in crate::resolve) mnemonic: &'static str,
+    pub(in crate::resolve) modifiers: Vec<String>,
+    pub(in crate::resolve) operands: Vec<OperandPattern>,
+    pub(in crate::resolve) summary: &'static str,
+}
+
+pub(in crate::resolve) fn tma_recipe(operation: TmaOperation) -> TmaRecipe {
+    let (abi_id, id, operation_key, source_record, llvm_symbol, op_type, op_name) = match operation
+    {
+        TmaOperation::Reduce => unreachable!("TMA reductions use tma_reduction_recipe"),
+        TmaOperation::G2sTile1d => (
+            "i0328",
+            "cp_async_bulk_tensor_1d_g2s",
+            "memory.copy.async.bulk.tensor.g2s.tile.1d",
+            "int_nvvm_cp_async_bulk_tensor_g2s_tile_1d",
+            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.1d",
+            "CpAsyncBulkTensorG2sTile1dOp",
+            "nvvm.cp_async_bulk_tensor_g2s_tile_1d",
+        ),
+        TmaOperation::G2sTile2d => (
+            "i0329",
+            "cp_async_bulk_tensor_2d_g2s",
+            "memory.copy.async.bulk.tensor.g2s.tile.2d",
+            "int_nvvm_cp_async_bulk_tensor_g2s_tile_2d",
+            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d",
+            "CpAsyncBulkTensorG2sTile2dOp",
+            "nvvm.cp_async_bulk_tensor_g2s_tile_2d",
+        ),
+        TmaOperation::G2sTile2dMulticast => (
+            "i0330",
+            "cp_async_bulk_tensor_2d_g2s_multicast",
+            "memory.copy.async.bulk.tensor.g2s.tile.2d.multicast",
+            "int_nvvm_cp_async_bulk_tensor_g2s_tile_2d",
+            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d",
+            "CpAsyncBulkTensorG2sTile2dMulticastOp",
+            "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast",
+        ),
+        TmaOperation::G2sTile2dMulticastCg2 => (
+            "i0331",
+            "cp_async_bulk_tensor_2d_g2s_multicast_cg2",
+            "memory.copy.async.bulk.tensor.g2s.tile.2d.multicast.cta_group_2",
+            "int_nvvm_cp_async_bulk_tensor_g2s_tile_2d",
+            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d",
+            "CpAsyncBulkTensorG2sTile2dMulticastCg2Op",
+            "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast_cg2",
+        ),
+        TmaOperation::G2sTile3d => (
+            "i0332",
+            "cp_async_bulk_tensor_3d_g2s",
+            "memory.copy.async.bulk.tensor.g2s.tile.3d",
+            "int_nvvm_cp_async_bulk_tensor_g2s_tile_3d",
+            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.3d",
+            "CpAsyncBulkTensorG2sTile3dOp",
+            "nvvm.cp_async_bulk_tensor_g2s_tile_3d",
+        ),
+        TmaOperation::G2sTile4d => (
+            "i0333",
+            "cp_async_bulk_tensor_4d_g2s",
+            "memory.copy.async.bulk.tensor.g2s.tile.4d",
+            "int_nvvm_cp_async_bulk_tensor_g2s_tile_4d",
+            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.4d",
+            "CpAsyncBulkTensorG2sTile4dOp",
+            "nvvm.cp_async_bulk_tensor_g2s_tile_4d",
+        ),
+        TmaOperation::G2sTile5d => (
+            "i0334",
+            "cp_async_bulk_tensor_5d_g2s",
+            "memory.copy.async.bulk.tensor.g2s.tile.5d",
+            "int_nvvm_cp_async_bulk_tensor_g2s_tile_5d",
+            "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.5d",
+            "CpAsyncBulkTensorG2sTile5dOp",
+            "nvvm.cp_async_bulk_tensor_g2s_tile_5d",
+        ),
+        TmaOperation::S2gTile1d => (
+            "i0335",
+            "cp_async_bulk_tensor_1d_s2g",
+            "memory.copy.async.bulk.tensor.s2g.tile.1d",
+            "int_nvvm_cp_async_bulk_tensor_s2g_tile_1d",
+            "llvm.nvvm.cp.async.bulk.tensor.s2g.tile.1d",
+            "CpAsyncBulkTensorS2gTile1dOp",
+            "nvvm.cp_async_bulk_tensor_s2g_tile_1d",
+        ),
+        TmaOperation::S2gTile2d => (
+            "i0336",
+            "cp_async_bulk_tensor_2d_s2g",
+            "memory.copy.async.bulk.tensor.s2g.tile.2d",
+            "int_nvvm_cp_async_bulk_tensor_s2g_tile_2d",
+            "llvm.nvvm.cp.async.bulk.tensor.s2g.tile.2d",
+            "CpAsyncBulkTensorS2gTile2dOp",
+            "nvvm.cp_async_bulk_tensor_s2g_tile_2d",
+        ),
+        TmaOperation::S2gTile3d => (
+            "i0337",
+            "cp_async_bulk_tensor_3d_s2g",
+            "memory.copy.async.bulk.tensor.s2g.tile.3d",
+            "int_nvvm_cp_async_bulk_tensor_s2g_tile_3d",
+            "llvm.nvvm.cp.async.bulk.tensor.s2g.tile.3d",
+            "CpAsyncBulkTensorS2gTile3dOp",
+            "nvvm.cp_async_bulk_tensor_s2g_tile_3d",
+        ),
+        TmaOperation::S2gTile4d => (
+            "i0338",
+            "cp_async_bulk_tensor_4d_s2g",
+            "memory.copy.async.bulk.tensor.s2g.tile.4d",
+            "int_nvvm_cp_async_bulk_tensor_s2g_tile_4d",
+            "llvm.nvvm.cp.async.bulk.tensor.s2g.tile.4d",
+            "CpAsyncBulkTensorS2gTile4dOp",
+            "nvvm.cp_async_bulk_tensor_s2g_tile_4d",
+        ),
+        TmaOperation::S2gTile5d => (
+            "i0339",
+            "cp_async_bulk_tensor_5d_s2g",
+            "memory.copy.async.bulk.tensor.s2g.tile.5d",
+            "int_nvvm_cp_async_bulk_tensor_s2g_tile_5d",
+            "llvm.nvvm.cp.async.bulk.tensor.s2g.tile.5d",
+            "CpAsyncBulkTensorS2gTile5dOp",
+            "nvvm.cp_async_bulk_tensor_s2g_tile_5d",
+        ),
+        TmaOperation::CommitGroup => (
+            "i0340",
+            "cp_async_bulk_commit_group",
+            "memory.copy.async.bulk.group.commit",
+            "int_nvvm_cp_async_bulk_commit_group",
+            "llvm.nvvm.cp.async.bulk.commit.group",
+            "CpAsyncBulkCommitGroupOp",
+            "nvvm.cp_async_bulk_commit_group",
+        ),
+        TmaOperation::WaitGroup => (
+            "i0341",
+            "cp_async_bulk_wait_group",
+            "memory.copy.async.bulk.group.wait_max_pending",
+            "int_nvvm_cp_async_bulk_wait_group",
+            "llvm.nvvm.cp.async.bulk.wait.group",
+            "CpAsyncBulkWaitGroupOp",
+            "nvvm.cp_async_bulk_wait_group",
+        ),
+        TmaOperation::WaitGroupRead => (
+            "i0342",
+            "cp_async_bulk_wait_group_read",
+            "memory.copy.async.bulk.group.wait_read_max_pending",
+            "int_nvvm_cp_async_bulk_wait_group_read",
+            "llvm.nvvm.cp.async.bulk.wait.group.read",
+            "CpAsyncBulkWaitGroupReadOp",
+            "nvvm.cp_async_bulk_wait_group_read",
+        ),
+        TmaOperation::PrefetchTensorMap => (
+            "i0887",
+            "prefetch_tma_descriptor",
+            "memory.prefetch.tensor_map",
+            "int_nvvm_prefetch_tensormap",
+            "llvm.nvvm.prefetch.tensormap",
+            "PrefetchTensorMapOp",
+            "nvvm.prefetch_tensormap",
+        ),
+        TmaOperation::PrefetchTile1d => (
+            "i0888",
+            "cp_async_bulk_prefetch_tensor_1d_l2",
+            "memory.prefetch.async.bulk.tensor.global.tile.1d.l2",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_1d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d",
+            "CpAsyncBulkPrefetchTensor1dL2Op",
+            "nvvm.cp_async_bulk_prefetch_tensor_1d_l2",
+        ),
+        TmaOperation::PrefetchTile2d => (
+            "i0889",
+            "cp_async_bulk_prefetch_tensor_2d_l2",
+            "memory.prefetch.async.bulk.tensor.global.tile.2d.l2",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_2d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d",
+            "CpAsyncBulkPrefetchTensor2dL2Op",
+            "nvvm.cp_async_bulk_prefetch_tensor_2d_l2",
+        ),
+        TmaOperation::PrefetchTile3d => (
+            "i0890",
+            "cp_async_bulk_prefetch_tensor_3d_l2",
+            "memory.prefetch.async.bulk.tensor.global.tile.3d.l2",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_3d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d",
+            "CpAsyncBulkPrefetchTensor3dL2Op",
+            "nvvm.cp_async_bulk_prefetch_tensor_3d_l2",
+        ),
+        TmaOperation::PrefetchTile4d => (
+            "i0891",
+            "cp_async_bulk_prefetch_tensor_4d_l2",
+            "memory.prefetch.async.bulk.tensor.global.tile.4d.l2",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_4d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d",
+            "CpAsyncBulkPrefetchTensor4dL2Op",
+            "nvvm.cp_async_bulk_prefetch_tensor_4d_l2",
+        ),
+        TmaOperation::PrefetchTile5d => (
+            "i0892",
+            "cp_async_bulk_prefetch_tensor_5d_l2",
+            "memory.prefetch.async.bulk.tensor.global.tile.5d.l2",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_5d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d",
+            "CpAsyncBulkPrefetchTensor5dL2Op",
+            "nvvm.cp_async_bulk_prefetch_tensor_5d_l2",
+        ),
+        TmaOperation::PrefetchTileGather4TwoDimensional => (
+            "i0893",
+            "cp_async_bulk_prefetch_tensor_gather4_2d_l2",
+            "memory.prefetch.async.bulk.tensor.global.tile.gather4.2d.l2",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_gather4_2d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.gather4.2d",
+            "CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op",
+            "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2",
+        ),
+        TmaOperation::PrefetchTile1dCacheHint => (
+            "i0917",
+            "cp_async_bulk_prefetch_tensor_1d_l2_cache_hint",
+            "memory.prefetch.async.bulk.tensor.global.tile.1d.l2.cache_hint",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_1d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d",
+            "CpAsyncBulkPrefetchTensor1dL2CacheHintOp",
+            "nvvm.cp_async_bulk_prefetch_tensor_1d_l2_cache_hint",
+        ),
+        TmaOperation::PrefetchTile2dCacheHint => (
+            "i0918",
+            "cp_async_bulk_prefetch_tensor_2d_l2_cache_hint",
+            "memory.prefetch.async.bulk.tensor.global.tile.2d.l2.cache_hint",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_2d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d",
+            "CpAsyncBulkPrefetchTensor2dL2CacheHintOp",
+            "nvvm.cp_async_bulk_prefetch_tensor_2d_l2_cache_hint",
+        ),
+        TmaOperation::PrefetchTile3dCacheHint => (
+            "i0919",
+            "cp_async_bulk_prefetch_tensor_3d_l2_cache_hint",
+            "memory.prefetch.async.bulk.tensor.global.tile.3d.l2.cache_hint",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_3d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d",
+            "CpAsyncBulkPrefetchTensor3dL2CacheHintOp",
+            "nvvm.cp_async_bulk_prefetch_tensor_3d_l2_cache_hint",
+        ),
+        TmaOperation::PrefetchTile4dCacheHint => (
+            "i0920",
+            "cp_async_bulk_prefetch_tensor_4d_l2_cache_hint",
+            "memory.prefetch.async.bulk.tensor.global.tile.4d.l2.cache_hint",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_4d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d",
+            "CpAsyncBulkPrefetchTensor4dL2CacheHintOp",
+            "nvvm.cp_async_bulk_prefetch_tensor_4d_l2_cache_hint",
+        ),
+        TmaOperation::PrefetchTile5dCacheHint => (
+            "i0921",
+            "cp_async_bulk_prefetch_tensor_5d_l2_cache_hint",
+            "memory.prefetch.async.bulk.tensor.global.tile.5d.l2.cache_hint",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_5d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d",
+            "CpAsyncBulkPrefetchTensor5dL2CacheHintOp",
+            "nvvm.cp_async_bulk_prefetch_tensor_5d_l2_cache_hint",
+        ),
+        TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint => (
+            "i0922",
+            "cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint",
+            "memory.prefetch.async.bulk.tensor.global.tile.gather4.2d.l2.cache_hint",
+            "int_nvvm_cp_async_bulk_tensor_prefetch_tile_gather4_2d",
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.gather4.2d",
+            "CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp",
+            "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint",
+        ),
+        TmaOperation::ReplaceBoxDim => (
+            "i0894",
+            "tensormap_replace_box_dim",
+            "memory.tensor_map.replace.box_dim",
+            "int_nvvm_tensormap_replace_box_dim",
+            "llvm.nvvm.tensormap.replace.box.dim",
+            "ReplaceTensorMapBoxDimOp",
+            "nvvm.tensormap_replace_box_dim",
+        ),
+        TmaOperation::ReplaceElementStride => (
+            "i0895",
+            "tensormap_replace_element_stride",
+            "memory.tensor_map.replace.element_stride",
+            "int_nvvm_tensormap_replace_element_stride",
+            "llvm.nvvm.tensormap.replace.element.stride",
+            "ReplaceTensorMapElementStrideOp",
+            "nvvm.tensormap_replace_element_stride",
+        ),
+        TmaOperation::ReplaceElementType => (
+            "i0896",
+            "tensormap_replace_element_type",
+            "memory.tensor_map.replace.element_type",
+            "int_nvvm_tensormap_replace_elemtype",
+            "llvm.nvvm.tensormap.replace.elemtype",
+            "ReplaceTensorMapElementTypeOp",
+            "nvvm.tensormap_replace_element_type",
+        ),
+        TmaOperation::ReplaceFillMode => (
+            "i0897",
+            "tensormap_replace_fill_mode",
+            "memory.tensor_map.replace.fill_mode",
+            "int_nvvm_tensormap_replace_fill_mode",
+            "llvm.nvvm.tensormap.replace.fill.mode",
+            "ReplaceTensorMapFillModeOp",
+            "nvvm.tensormap_replace_fill_mode",
+        ),
+        TmaOperation::ReplaceGlobalAddress => (
+            "i0898",
+            "tensormap_replace_global_address",
+            "memory.tensor_map.replace.global_address",
+            "int_nvvm_tensormap_replace_global_address",
+            "llvm.nvvm.tensormap.replace.global.address",
+            "ReplaceTensorMapGlobalAddressOp",
+            "nvvm.tensormap_replace_global_address",
+        ),
+        TmaOperation::ReplaceGlobalDim => (
+            "i0899",
+            "tensormap_replace_global_dim",
+            "memory.tensor_map.replace.global_dim",
+            "int_nvvm_tensormap_replace_global_dim",
+            "llvm.nvvm.tensormap.replace.global.dim",
+            "ReplaceTensorMapGlobalDimOp",
+            "nvvm.tensormap_replace_global_dim",
+        ),
+        TmaOperation::ReplaceGlobalStride => (
+            "i0900",
+            "tensormap_replace_global_stride",
+            "memory.tensor_map.replace.global_stride",
+            "int_nvvm_tensormap_replace_global_stride",
+            "llvm.nvvm.tensormap.replace.global.stride",
+            "ReplaceTensorMapGlobalStrideOp",
+            "nvvm.tensormap_replace_global_stride",
+        ),
+        TmaOperation::ReplaceInterleaveLayout => (
+            "i0901",
+            "tensormap_replace_interleave_layout",
+            "memory.tensor_map.replace.interleave_layout",
+            "int_nvvm_tensormap_replace_interleave_layout",
+            "llvm.nvvm.tensormap.replace.interleave.layout",
+            "ReplaceTensorMapInterleaveLayoutOp",
+            "nvvm.tensormap_replace_interleave_layout",
+        ),
+        TmaOperation::ReplaceRank => (
+            "i0902",
+            "tensormap_replace_rank",
+            "memory.tensor_map.replace.rank",
+            "int_nvvm_tensormap_replace_rank",
+            "llvm.nvvm.tensormap.replace.rank",
+            "ReplaceTensorMapRankOp",
+            "nvvm.tensormap_replace_rank",
+        ),
+        TmaOperation::ReplaceSwizzleAtomicity => (
+            "i0903",
+            "tensormap_replace_swizzle_atomicity",
+            "memory.tensor_map.replace.swizzle_atomicity",
+            "int_nvvm_tensormap_replace_swizzle_atomicity",
+            "llvm.nvvm.tensormap.replace.swizzle.atomicity",
+            "ReplaceTensorMapSwizzleAtomicityOp",
+            "nvvm.tensormap_replace_swizzle_atomicity",
+        ),
+        TmaOperation::ReplaceSwizzleMode => (
+            "i0904",
+            "tensormap_replace_swizzle_mode",
+            "memory.tensor_map.replace.swizzle_mode",
+            "int_nvvm_tensormap_replace_swizzle_mode",
+            "llvm.nvvm.tensormap.replace.swizzle.mode",
+            "ReplaceTensorMapSwizzleModeOp",
+            "nvvm.tensormap_replace_swizzle_mode",
+        ),
+        TmaOperation::FenceProxyTensorMapAcquireCluster => (
+            "i0905",
+            "fence_proxy_tensormap_generic_acquire_cluster",
+            "memory.fence.proxy.tensor_map.generic.acquire.cluster",
+            "int_nvvm_fence_proxy_tensormap_generic_acquire_cluster",
+            "llvm.nvvm.fence.proxy.tensormap_generic.acquire.cluster",
+            "FenceProxyTensorMapGenericAcquireClusterOp",
+            "nvvm.fence_proxy_tensormap_generic_acquire_cluster",
+        ),
+        TmaOperation::FenceProxyTensorMapAcquireCta => (
+            "i0906",
+            "fence_proxy_tensormap_generic_acquire_cta",
+            "memory.fence.proxy.tensor_map.generic.acquire.cta",
+            "int_nvvm_fence_proxy_tensormap_generic_acquire_cta",
+            "llvm.nvvm.fence.proxy.tensormap_generic.acquire.cta",
+            "FenceProxyTensorMapGenericAcquireCtaOp",
+            "nvvm.fence_proxy_tensormap_generic_acquire_cta",
+        ),
+        TmaOperation::FenceProxyTensorMapAcquireGpu => (
+            "i0907",
+            "fence_proxy_tensormap_generic_acquire_gpu",
+            "memory.fence.proxy.tensor_map.generic.acquire.gpu",
+            "int_nvvm_fence_proxy_tensormap_generic_acquire_gpu",
+            "llvm.nvvm.fence.proxy.tensormap_generic.acquire.gpu",
+            "FenceProxyTensorMapGenericAcquireGpuOp",
+            "nvvm.fence_proxy_tensormap_generic_acquire_gpu",
+        ),
+        TmaOperation::FenceProxyTensorMapAcquireSystem => (
+            "i0908",
+            "fence_proxy_tensormap_generic_acquire_system",
+            "memory.fence.proxy.tensor_map.generic.acquire.system",
+            "int_nvvm_fence_proxy_tensormap_generic_acquire_sys",
+            "llvm.nvvm.fence.proxy.tensormap_generic.acquire.sys",
+            "FenceProxyTensorMapGenericAcquireSystemOp",
+            "nvvm.fence_proxy_tensormap_generic_acquire_system",
+        ),
+        TmaOperation::FenceProxyTensorMapReleaseCluster => (
+            "i0909",
+            "fence_proxy_tensormap_generic_release_cluster",
+            "memory.fence.proxy.tensor_map.generic.release.cluster",
+            "int_nvvm_fence_proxy_tensormap_generic_release_cluster",
+            "llvm.nvvm.fence.proxy.tensormap_generic.release.cluster",
+            "FenceProxyTensorMapGenericReleaseClusterOp",
+            "nvvm.fence_proxy_tensormap_generic_release_cluster",
+        ),
+        TmaOperation::FenceProxyTensorMapReleaseCta => (
+            "i0910",
+            "fence_proxy_tensormap_generic_release_cta",
+            "memory.fence.proxy.tensor_map.generic.release.cta",
+            "int_nvvm_fence_proxy_tensormap_generic_release_cta",
+            "llvm.nvvm.fence.proxy.tensormap_generic.release.cta",
+            "FenceProxyTensorMapGenericReleaseCtaOp",
+            "nvvm.fence_proxy_tensormap_generic_release_cta",
+        ),
+        TmaOperation::FenceProxyTensorMapReleaseGpu => (
+            "i0911",
+            "fence_proxy_tensormap_generic_release_gpu",
+            "memory.fence.proxy.tensor_map.generic.release.gpu",
+            "int_nvvm_fence_proxy_tensormap_generic_release_gpu",
+            "llvm.nvvm.fence.proxy.tensormap_generic.release.gpu",
+            "FenceProxyTensorMapGenericReleaseGpuOp",
+            "nvvm.fence_proxy_tensormap_generic_release_gpu",
+        ),
+        TmaOperation::FenceProxyTensorMapReleaseSystem => (
+            "i0912",
+            "fence_proxy_tensormap_generic_release_system",
+            "memory.fence.proxy.tensor_map.generic.release.system",
+            "int_nvvm_fence_proxy_tensormap_generic_release_sys",
+            "llvm.nvvm.fence.proxy.tensormap_generic.release.sys",
+            "FenceProxyTensorMapGenericReleaseSystemOp",
+            "nvvm.fence_proxy_tensormap_generic_release_system",
+        ),
+    };
+
+    let dimensions = operation.dimensions();
+    let is_g2s = matches!(
+        operation,
+        TmaOperation::G2sTile1d
+            | TmaOperation::G2sTile2d
+            | TmaOperation::G2sTile2dMulticast
+            | TmaOperation::G2sTile2dMulticastCg2
+            | TmaOperation::G2sTile3d
+            | TmaOperation::G2sTile4d
+            | TmaOperation::G2sTile5d
+    );
+    let is_s2g = matches!(
+        operation,
+        TmaOperation::S2gTile1d
+            | TmaOperation::S2gTile2d
+            | TmaOperation::S2gTile3d
+            | TmaOperation::S2gTile4d
+            | TmaOperation::S2gTile5d
+    );
+    let multicast = matches!(
+        operation,
+        TmaOperation::G2sTile2dMulticast | TmaOperation::G2sTile2dMulticastCg2
+    );
+    let cg2 = operation == TmaOperation::G2sTile2dMulticastCg2;
+    let prefetch_coordinates = operation.prefetch_coordinate_count();
+    let is_release_fence = matches!(
+        operation,
+        TmaOperation::FenceProxyTensorMapReleaseCluster
+            | TmaOperation::FenceProxyTensorMapReleaseCta
+            | TmaOperation::FenceProxyTensorMapReleaseGpu
+            | TmaOperation::FenceProxyTensorMapReleaseSystem
+    );
+    let is_acquire_fence = matches!(
+        operation,
+        TmaOperation::FenceProxyTensorMapAcquireCluster
+            | TmaOperation::FenceProxyTensorMapAcquireCta
+            | TmaOperation::FenceProxyTensorMapAcquireGpu
+            | TmaOperation::FenceProxyTensorMapAcquireSystem
+    );
+
+    let mut rust_arguments = Vec::new();
+    let mut dialect_operands = Vec::new();
+    let mut llvm_arguments = Vec::new();
+    let (adapter, safe, safe_reason, convergent, summary) = if is_g2s {
+        rust_arguments.extend(["*mut u8", "*const u8"]);
+        rust_arguments.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
+        rust_arguments.push("*mut u64");
+        if multicast {
+            rust_arguments.push("u16");
+        }
+        dialect_operands.extend(["ptr", "ptr", "ptr"]);
+        dialect_operands.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
+        dialect_operands.extend(["i16", "i64"]);
+        llvm_arguments.extend(["shared_cluster_ptr", "shared_ptr", "ptr"]);
+        llvm_arguments.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
+        llvm_arguments.extend(["i16", "i64", "i1", "i1", "i32"]);
+        (
+            if multicast {
+                TmaAdapter::G2sPointersCoordinatesBarrierMaskInjectDefaults
+            } else {
+                TmaAdapter::G2sPointersCoordinatesBarrierInjectDefaults
+            },
+            false,
+            None,
+            true,
+            if multicast {
+                "Starts a multicast TMA tile copy from global to cluster shared memory."
+            } else {
+                "Starts a TMA tile copy from global to cluster shared memory."
+            },
+        )
+    } else if is_s2g {
+        rust_arguments.extend(["*const u8", "*const u8"]);
+        rust_arguments.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
+        dialect_operands.extend(["ptr", "ptr"]);
+        dialect_operands.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
+        llvm_arguments.extend(["shared_ptr", "ptr"]);
+        llvm_arguments.extend(std::iter::repeat_n("i32", dimensions.unwrap()));
+        llvm_arguments.extend(["i64", "i1"]);
+        (
+            TmaAdapter::S2gPointersCoordinatesInjectDefaults,
+            false,
+            None,
+            true,
+            "Starts a TMA tile copy from shared to global memory.",
+        )
+    } else if operation == TmaOperation::CommitGroup || is_release_fence {
+        (
+            TmaAdapter::NoOperands,
+            true,
+            Some(if operation == TmaOperation::CommitGroup {
+                "committing this thread's pending bulk-copy group has no Rust memory-safety precondition."
+            } else {
+                "publishing prior tensor-map writes has no Rust memory-safety precondition."
+            }),
+            false,
+            if operation == TmaOperation::CommitGroup {
+                "Commits this thread's pending asynchronous bulk copies as one group."
+            } else {
+                "Publishes prior generic-proxy tensor-map writes to the selected tensor-map proxy scope."
+            },
+        )
+    } else if operation == TmaOperation::PrefetchTensorMap {
+        rust_arguments.push("*const u8");
+        dialect_operands.push("ptr");
+        llvm_arguments.push("anyptr");
+        (
+            TmaAdapter::DescriptorPointer,
+            false,
+            None,
+            false,
+            "Prefetches a live tensor-map descriptor into the tensor-map cache.",
+        )
+    } else if let Some(coordinate_count) = prefetch_coordinates {
+        rust_arguments.push("*const u8");
+        rust_arguments.extend(std::iter::repeat_n("i32", coordinate_count));
+        dialect_operands.push("ptr");
+        dialect_operands.extend(std::iter::repeat_n("i32", coordinate_count));
+        if operation.uses_prefetch_cache_hint() {
+            rust_arguments.push("u64");
+            dialect_operands.push("i64");
+        }
+        llvm_arguments.push("ptr");
+        llvm_arguments.extend(std::iter::repeat_n("i32", coordinate_count));
+        llvm_arguments.extend(["i64", "i1"]);
+        (
+            if operation.uses_prefetch_cache_hint() {
+                TmaAdapter::DescriptorCoordinatesCacheHintInjectFlag
+            } else {
+                TmaAdapter::DescriptorCoordinatesInjectDefaults
+            },
+            false,
+            None,
+            true,
+            if operation.uses_prefetch_cache_hint() {
+                "Prefetches one tensor tile through a tensor map into L2 using an explicit cache hint."
+            } else {
+                "Prefetches one tensor tile through a tensor map into L2."
+            },
+        )
+    } else if operation == TmaOperation::ReplaceGlobalAddress {
+        rust_arguments.extend(["*mut u8", "*const u8"]);
+        dialect_operands.extend(["ptr", "ptr"]);
+        llvm_arguments.extend(["anyptr", "i64"]);
+        (
+            TmaAdapter::DescriptorAndAddressPointers,
+            false,
+            None,
+            false,
+            "Replaces the global base address stored in a writable tensor-map descriptor.",
+        )
+    } else if matches!(
+        operation,
+        TmaOperation::ReplaceBoxDim
+            | TmaOperation::ReplaceElementStride
+            | TmaOperation::ReplaceGlobalDim
+    ) {
+        rust_arguments.extend(["*mut u8", "u32", "u32"]);
+        dialect_operands.extend(["ptr", "i32", "i32"]);
+        llvm_arguments.extend(["anyptr", "i32", "i32"]);
+        (
+            TmaAdapter::DescriptorOrdinalAndU32,
+            false,
+            None,
+            false,
+            "Replaces one indexed 32-bit field in a writable tensor-map descriptor.",
+        )
+    } else if operation == TmaOperation::ReplaceGlobalStride {
+        rust_arguments.extend(["*mut u8", "u32", "u64"]);
+        dialect_operands.extend(["ptr", "i32", "i64"]);
+        llvm_arguments.extend(["anyptr", "i32", "i64"]);
+        (
+            TmaAdapter::DescriptorOrdinalAndU64,
+            false,
+            None,
+            false,
+            "Replaces one indexed 64-bit stride in a writable tensor-map descriptor.",
+        )
+    } else if matches!(
+        operation,
+        TmaOperation::ReplaceElementType
+            | TmaOperation::ReplaceFillMode
+            | TmaOperation::ReplaceInterleaveLayout
+            | TmaOperation::ReplaceSwizzleAtomicity
+            | TmaOperation::ReplaceSwizzleMode
+    ) {
+        rust_arguments.extend(["*mut u8", "u32"]);
+        dialect_operands.extend(["ptr", "i32"]);
+        llvm_arguments.extend(["anyptr", "i32"]);
+        (
+            TmaAdapter::DescriptorAndImmediateU32,
+            false,
+            None,
+            false,
+            "Replaces one immediate-valued field in a writable tensor-map descriptor.",
+        )
+    } else if operation == TmaOperation::ReplaceRank {
+        rust_arguments.extend(["*mut u8", "u32"]);
+        dialect_operands.extend(["ptr", "i32"]);
+        llvm_arguments.extend(["anyptr", "i32"]);
+        (
+            TmaAdapter::DescriptorAndRuntimeU32,
+            false,
+            None,
+            false,
+            "Replaces the rank stored in a writable tensor-map descriptor.",
+        )
+    } else if is_acquire_fence {
+        rust_arguments.push("*const u8");
+        dialect_operands.push("ptr");
+        llvm_arguments.extend(["ptr", "i32"]);
+        (
+            TmaAdapter::DescriptorPointerInjectBytes,
+            false,
+            None,
+            false,
+            "Acquires a published tensor-map descriptor into the selected tensor-map proxy scope.",
+        )
+    } else {
+        rust_arguments.push("u32");
+        dialect_operands.push("i32");
+        llvm_arguments.push("i32");
+        (
+            TmaAdapter::CompileTimeConstantMaxPending,
+            true,
+            Some(
+                "waiting on this thread's bulk-copy groups has no Rust memory-safety precondition.",
+            ),
+            false,
+            if operation == TmaOperation::WaitGroupRead {
+                "Waits for bulk-copy groups and completes their reads."
+            } else {
+                "Waits until at most the requested bulk-copy groups remain pending."
+            },
+        )
+    };
+
+    let is_replace = matches!(
+        operation,
+        TmaOperation::ReplaceBoxDim
+            | TmaOperation::ReplaceElementStride
+            | TmaOperation::ReplaceElementType
+            | TmaOperation::ReplaceFillMode
+            | TmaOperation::ReplaceGlobalAddress
+            | TmaOperation::ReplaceGlobalDim
+            | TmaOperation::ReplaceGlobalStride
+            | TmaOperation::ReplaceInterleaveLayout
+            | TmaOperation::ReplaceRank
+            | TmaOperation::ReplaceSwizzleAtomicity
+            | TmaOperation::ReplaceSwizzleMode
+    );
+    let is_fence = is_acquire_fence || is_release_fence;
+    let descriptor_control = operation == TmaOperation::PrefetchTensorMap
+        || prefetch_coordinates.is_some()
+        || is_replace
+        || is_fence;
+    let blackwell_tma = cg2
+        || matches!(
+            operation,
+            TmaOperation::PrefetchTileGather4TwoDimensional
+                | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint
+        );
+
+    let (mnemonic, modifiers, operands) = if is_g2s {
+        let mut modifiers = vec![
+            "async".into(),
+            "bulk".into(),
+            "tensor".into(),
+            format!("{}d", dimensions.unwrap()),
+            "shared::cluster".into(),
+            "global".into(),
+            "tile".into(),
+            "mbarrier::complete_tx::bytes".into(),
+        ];
+        if multicast {
+            modifiers.push("multicast::cluster".into());
+        }
+        if cg2 {
+            modifiers.push("cta_group::2".into());
+        }
+        let mut operands = vec![
+            OperandPattern::Address,
+            OperandPattern::Address,
+            OperandPattern::Address,
+        ];
+        if multicast {
+            operands.push(OperandPattern::Register);
+        }
+        ("cp", modifiers, operands)
+    } else if is_s2g {
+        (
+            "cp",
+            vec![
+                "async".into(),
+                "bulk".into(),
+                "tensor".into(),
+                format!("{}d", dimensions.unwrap()),
+                "global".into(),
+                "shared::cta".into(),
+                "tile".into(),
+                "bulk_group".into(),
+            ],
+            vec![OperandPattern::Address, OperandPattern::Address],
+        )
+    } else if operation == TmaOperation::CommitGroup {
+        (
+            "cp",
+            vec!["async".into(), "bulk".into(), "commit_group".into()],
+            vec![],
+        )
+    } else if matches!(
+        operation,
+        TmaOperation::WaitGroup | TmaOperation::WaitGroupRead
+    ) {
+        let mut modifiers = vec!["async".into(), "bulk".into(), "wait_group".into()];
+        if operation == TmaOperation::WaitGroupRead {
+            modifiers.push("read".into());
+        }
+        ("cp", modifiers, vec![OperandPattern::Immediate])
+    } else if operation == TmaOperation::PrefetchTensorMap {
+        (
+            "prefetch",
+            vec!["tensormap".into()],
+            vec![OperandPattern::Address],
+        )
+    } else if prefetch_coordinates.is_some() {
+        let (dimensionality, tile) = if matches!(
+            operation,
+            TmaOperation::PrefetchTileGather4TwoDimensional
+                | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint
+        ) {
+            ("2d", "tile::gather4")
+        } else {
+            (
+                match prefetch_coordinates.unwrap() {
+                    1 => "1d",
+                    2 => "2d",
+                    3 => "3d",
+                    4 => "4d",
+                    5 => "5d",
+                    _ => unreachable!("closed TMA prefetch dimensionality"),
+                },
+                "tile",
+            )
+        };
+        let mut modifiers = vec![
+            "async".into(),
+            "bulk".into(),
+            "prefetch".into(),
+            "tensor".into(),
+            dimensionality.into(),
+            "L2".into(),
+            "global".into(),
+            tile.into(),
+        ];
+        let mut operands = vec![OperandPattern::Address];
+        if operation.uses_prefetch_cache_hint() {
+            modifiers.push("L2::cache_hint".into());
+            operands.push(OperandPattern::Register);
+        }
+        ("cp", modifiers, operands)
+    } else if is_replace {
+        let (field, width, operands) = match operation {
+            TmaOperation::ReplaceGlobalAddress => (
+                "global_address",
+                "b64",
+                vec![OperandPattern::Address, OperandPattern::Register],
+            ),
+            TmaOperation::ReplaceRank => (
+                "rank",
+                "b32",
+                vec![OperandPattern::Address, OperandPattern::Register],
+            ),
+            TmaOperation::ReplaceBoxDim => (
+                "box_dim",
+                "b32",
+                vec![
+                    OperandPattern::Address,
+                    OperandPattern::Immediate,
+                    OperandPattern::Register,
+                ],
+            ),
+            TmaOperation::ReplaceElementStride => (
+                "element_stride",
+                "b32",
+                vec![
+                    OperandPattern::Address,
+                    OperandPattern::Immediate,
+                    OperandPattern::Register,
+                ],
+            ),
+            TmaOperation::ReplaceGlobalDim => (
+                "global_dim",
+                "b32",
+                vec![
+                    OperandPattern::Address,
+                    OperandPattern::Immediate,
+                    OperandPattern::Register,
+                ],
+            ),
+            TmaOperation::ReplaceGlobalStride => (
+                "global_stride",
+                "b64",
+                vec![
+                    OperandPattern::Address,
+                    OperandPattern::Immediate,
+                    OperandPattern::Register,
+                ],
+            ),
+            TmaOperation::ReplaceElementType => (
+                "elemtype",
+                "b32",
+                vec![OperandPattern::Address, OperandPattern::Immediate],
+            ),
+            TmaOperation::ReplaceFillMode => (
+                "fill_mode",
+                "b32",
+                vec![OperandPattern::Address, OperandPattern::Immediate],
+            ),
+            TmaOperation::ReplaceInterleaveLayout => (
+                "interleave_layout",
+                "b32",
+                vec![OperandPattern::Address, OperandPattern::Immediate],
+            ),
+            TmaOperation::ReplaceSwizzleAtomicity => (
+                "swizzle_atomicity",
+                "b32",
+                vec![OperandPattern::Address, OperandPattern::Immediate],
+            ),
+            TmaOperation::ReplaceSwizzleMode => (
+                "swizzle_mode",
+                "b32",
+                vec![OperandPattern::Address, OperandPattern::Immediate],
+            ),
+            _ => unreachable!("TMA tensor-map replace operation was matched"),
+        };
+        (
+            "tensormap",
+            vec![
+                "replace".into(),
+                "tile".into(),
+                field.into(),
+                "global".into(),
+                "b1024".into(),
+                width.into(),
+            ],
+            operands,
+        )
+    } else if is_fence {
+        let (semantics, scope) = match operation {
+            TmaOperation::FenceProxyTensorMapAcquireCluster => ("acquire", "cluster"),
+            TmaOperation::FenceProxyTensorMapAcquireCta => ("acquire", "cta"),
+            TmaOperation::FenceProxyTensorMapAcquireGpu => ("acquire", "gpu"),
+            TmaOperation::FenceProxyTensorMapAcquireSystem => ("acquire", "sys"),
+            TmaOperation::FenceProxyTensorMapReleaseCluster => ("release", "cluster"),
+            TmaOperation::FenceProxyTensorMapReleaseCta => ("release", "cta"),
+            TmaOperation::FenceProxyTensorMapReleaseGpu => ("release", "gpu"),
+            TmaOperation::FenceProxyTensorMapReleaseSystem => ("release", "sys"),
+            _ => unreachable!("TMA tensor-map fence operation was matched"),
+        };
+        (
+            "fence",
+            vec![
+                "proxy".into(),
+                "tensormap::generic".into(),
+                semantics.into(),
+                scope.into(),
+            ],
+            if is_acquire_fence {
+                vec![
+                    OperandPattern::Address,
+                    OperandPattern::Exact {
+                        value: "128".into(),
+                    },
+                ]
+            } else {
+                vec![]
+            },
+        )
+    } else {
+        unreachable!("TMA operation category was matched")
+    };
+
+    let minimum_ptx = if blackwell_tma || operation == TmaOperation::ReplaceSwizzleAtomicity {
+        "8.6"
+    } else if is_replace || is_fence {
+        "8.3"
+    } else {
+        "8.0"
+    };
+    let (minimum_sm, targets) = if blackwell_tma {
+        (None, TMA_BLACKWELL_TARGETS)
+    } else if operation == TmaOperation::ReplaceSwizzleAtomicity {
+        (None, BLACKWELL_LDMATRIX_LLVM_TARGETS)
+    } else if is_replace {
+        (None, TENSOR_MAP_REPLACE_TARGETS)
+    } else {
+        (Some("sm_90"), "all")
+    };
+    let memory = if operation == TmaOperation::PrefetchTensorMap || prefetch_coordinates.is_some() {
+        "read"
+    } else if is_replace {
+        "write"
+    } else {
+        "read_write"
+    };
+    let polymorphic_descriptor = operation == TmaOperation::PrefetchTensorMap;
+
+    TmaRecipe {
+        operation,
+        abi_id,
+        id,
+        operation_key,
+        source_record,
+        llvm_symbol,
+        resolved_llvm_symbol: polymorphic_descriptor.then(|| format!("{llvm_symbol}.p0")),
+        selected_address_space: polymorphic_descriptor.then_some(ImportedAddressSpace::Generic),
+        llvm_mechanism: if is_replace {
+            BackendLoweringMechanism::InlinePtx
+        } else {
+            BackendLoweringMechanism::TypedNvvm
+        },
+        rust_arguments,
+        dialect_op_type: op_type,
+        dialect_op_name: op_name,
+        dialect_operands,
+        llvm_arguments,
+        adapter,
+        safe,
+        safe_reason,
+        convergent,
+        minimum_ptx,
+        minimum_sm,
+        targets,
+        memory,
+        ptx_isa_section: if descriptor_control {
+            "Tensor-map descriptor and asynchronous bulk tensor operations"
+        } else {
+            "9.7.9.26.5 Asynchronous bulk tensor copy"
+        },
+        ptx_isa_url: if descriptor_control {
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-map"
+        } else {
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-tensor"
+        },
+        mnemonic,
+        modifiers,
+        operands,
+        summary,
+    }
+}
+
+pub(in crate::resolve) fn expand_tma_admission(
+    admission: &TmaAdmission,
+) -> Result<Vec<OverlayIntrinsic>> {
+    ensure!(
+        admission.runtime_validation == RuntimeValidation::Unexecuted,
+        "TMA runtime validation may be marked executed only with GPU evidence"
+    );
+    ensure!(
+        !admission.llvm_evidence_profile.trim().is_empty()
+            && !admission.libnvvm_evidence_profile.trim().is_empty(),
+        "compact TMA admission requires both backend evidence profiles"
+    );
+    ensure!(
+        admission
+            .variants
+            .iter()
+            .map(|variant| variant.operation)
+            .eq(TMA_OPERATIONS),
+        "compact TMA admission must list all {} operations in canonical order",
+        TMA_OPERATIONS.len()
+    );
+
+    let mut records = admission
+        .variants
+        .iter()
+        .map(|variant| {
+            let recipe = tma_recipe(variant.operation);
+            ensure!(
+                variant.abi_id == recipe.abi_id,
+                "{} must keep reserved ABI ID {}",
+                recipe.id,
+                recipe.abi_id
+            );
+            Ok(OverlayIntrinsic {
+                id: recipe.id.into(),
+                abi_id: variant.abi_id.clone(),
+                operation_key: recipe.operation_key.into(),
+                family: "tma".into(),
+                source: None,
+                source_record: Some(recipe.source_record.into()),
+                rust_module: "tma".into(),
+                rust_name: recipe.id.into(),
+                rust_arguments: recipe
+                    .rust_arguments
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                rust_result: "()".into(),
+                safe: recipe.safe,
+                must_use: false,
+                safe_allowlist_reason: recipe.safe_reason.map(Into::into),
+                public_rust_path: format!("cuda_intrinsics::tma::{}", recipe.id),
+                compatibility_rust_paths: vec![format!("cuda_device::tma::{}", recipe.id)],
+                dialect_op_type: recipe.dialect_op_type.into(),
+                dialect_op_name: recipe.dialect_op_name.into(),
+                dialect_operands: recipe
+                    .dialect_operands
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                dialect_results: vec![],
+                llvm_symbol: Some(recipe.llvm_symbol.into()),
+                resolved_llvm_symbol: recipe.resolved_llvm_symbol.clone(),
+                llvm_arguments: recipe
+                    .llvm_arguments
+                    .iter()
+                    .map(|value| (*value).into())
+                    .collect(),
+                llvm_results: vec![],
+                pure: false,
+                memory: recipe.memory.into(),
+                convergent: recipe.convergent,
+                execution_scope: "thread".into(),
+                minimum_ptx: recipe.minimum_ptx.into(),
+                minimum_sm: recipe.minimum_sm.map(Into::into),
+                ptx_result: "()".into(),
+                targets: recipe.targets.into(),
+                ptx_isa_version: "9.3".into(),
+                ptx_isa_section: recipe.ptx_isa_section.into(),
+                ptx_isa_url: recipe.ptx_isa_url.into(),
+                lowering: "generated_tma".into(),
+                backend_lowerings: vec![
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LlvmNvptx,
+                        mechanism: recipe.llvm_mechanism,
+                        evidence_profile: admission.llvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some(recipe.minimum_ptx.into()),
+                        minimum_sm: recipe.minimum_sm.map(Into::into),
+                    },
+                    OverlayBackendLowering {
+                        backend: IntrinsicBackend::LibNvvm,
+                        mechanism: BackendLoweringMechanism::InlinePtx,
+                        evidence_profile: admission.libnvvm_evidence_profile.clone(),
+                        targets: None,
+                        minimum_ptx: Some(recipe.minimum_ptx.into()),
+                        minimum_sm: recipe.minimum_sm.map(Into::into),
+                    },
+                ],
+                packed_atomic: None,
+                redux: None,
+                vote: None,
+                active_mask: None,
+                warp_match: None,
+                warp_barrier: None,
+                warp_shuffle: None,
+                dot_product: None,
+                packed_alu: None,
+                integer_minmax: None,
+                packed_conversion: None,
+                scalar_conversion: None,
+                scalar_arithmetic: None,
+                scalar_math: None,
+                extended_minmax: None,
+                cp_async_copy: None,
+                cp_async_control: None,
+                cp_async_mbarrier: None,
+                mbarrier_basic: None,
+                movmatrix: None,
+                mbarrier_extended: None,
+                register_mma: None,
+                sparse_mma: None,
+                prmt: None,
+                cluster_barrier: None,
+                wgmma_control: None,
+                special_register: None,
+                debug_control: None,
+                cluster_memory: None,
+                clc: None,
+                tma: Some(Tma {
+                    operation: recipe.operation,
+                    reduction: None,
+                    adapter: recipe.adapter,
+                    runtime_validation: admission.runtime_validation,
+                }),
+                tcgen05: None,
+                ldmatrix_variant: None,
+                ldmatrix_safety: None,
+                ldmatrix_adapter: None,
+                selected_address_space: recipe.selected_address_space,
+                expected_ptx: InstructionPattern {
+                    mnemonic: recipe.mnemonic.into(),
+                    modifiers: recipe.modifiers,
+                    operands: recipe.operands,
+                },
+                summary: recipe.summary.into(),
+            })
+        })
+        .collect::<Result<Vec<_>>>()?;
+
+    if !admission.reduce_variants.is_empty() {
+        ensure!(
+            admission.reduce_llvm_evidence_profile.is_some(),
+            "compact TMA reduction admission requires reduce_llvm_evidence_profile"
+        );
+        ensure!(
+            admission.reduce_libnvvm_evidence_profile.is_some(),
+            "compact TMA reduction admission requires reduce_libnvvm_evidence_profile"
+        );
+
+        let expected_reductions = tma_reduction_matrix();
+        ensure!(
+            admission.reduce_variants.len() == expected_reductions.len()
+                && admission
+                    .reduce_variants
+                    .iter()
+                    .zip(expected_reductions.iter())
+                    .all(|(variant, expected)| {
+                        variant.operation == expected.operation
+                            && variant.load_mode == expected.load_mode
+                            && variant.dimensions == expected.dimensions
+                    }),
+            "compact TMA reduction admission must list all 64 operations in canonical order"
+        );
+        for variant in &admission.reduce_variants {
+            records.push(expand_tma_reduction_variant(admission, variant)?);
+        }
+    }
+    Ok(records)
+}
+
+pub(in crate::resolve) fn validate_tma_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let tma = policy
+        .tma
+        .as_ref()
+        .with_context(|| format!("{} has no closed TMA contract", policy.id))?;
+    if tma.operation == TmaOperation::Reduce {
+        return validate_tma_reduction_policy(policy, declaration, tma);
+    }
+    ensure!(
+        tma.reduction.is_none(),
+        "{} non-reduction TMA operation carries a reduction contract",
+        policy.id
+    );
+    let recipe = tma_recipe(tma.operation);
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol == recipe.resolved_llvm_symbol
+            && declaration.source_record == recipe.source_record
+            && declaration.llvm_name == recipe.llvm_symbol,
+        "{} TMA identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "tma"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == recipe.rust_arguments
+            && policy.rust_result == "()"
+            && policy.safe == recipe.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.as_deref() == recipe.safe_reason
+            && policy.public_rust_path == format!("cuda_intrinsics::tma::{}", recipe.id)
+            && policy.compatibility_rust_paths == [format!("cuda_device::tma::{}", recipe.id)],
+        "{} TMA Rust API changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == recipe.dialect_operands
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == recipe.llvm_arguments
+            && policy.llvm_results.is_empty()
+            && declaration.arguments == recipe.llvm_arguments
+            && declaration.results.is_empty()
+            && policy.selected_address_space == recipe.selected_address_space
+            && policy.lowering == "generated_tma",
+        "{} TMA carrier or LLVM adapter changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == recipe.memory
+            && policy.convergent == recipe.convergent
+            && policy.execution_scope == "thread"
+            && tma.adapter == recipe.adapter
+            && tma.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} TMA semantics changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == recipe.minimum_ptx
+            && policy.minimum_sm.as_deref() == recipe.minimum_sm
+            && policy.targets == recipe.targets
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == recipe.ptx_isa_section
+            && policy.ptx_isa_url == recipe.ptx_isa_url
+            && policy.ptx_result == "()"
+            && policy.expected_ptx.mnemonic == recipe.mnemonic
+            && policy.expected_ptx.modifiers == recipe.modifiers
+            && policy.expected_ptx.operands == recipe.operands,
+        "{} TMA target or PTX contract changed",
+        policy.id
+    );
+    let valid_route = |backend, mechanism| {
+        policy.backend_lowerings.iter().any(|route| {
+            route.backend == backend
+                && route.mechanism == mechanism
+                && route.minimum_ptx.as_deref() == Some(recipe.minimum_ptx)
+                && route.minimum_sm.as_deref() == recipe.minimum_sm
+                && !route.evidence_profile.trim().is_empty()
+        })
+    };
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && valid_route(IntrinsicBackend::LlvmNvptx, recipe.llvm_mechanism,)
+            && valid_route(
+                IntrinsicBackend::LibNvvm,
+                BackendLoweringMechanism::InlinePtx,
+            ),
+        "{} TMA backend route changed",
+        policy.id
+    );
+    let expected_properties = tma_imported_properties(tma.operation);
+    ensure!(
+        declaration.properties == expected_properties,
+        "{} imported TMA declaration changed",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "TMA")?;
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_tma_reduction_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+    tma: &Tma,
+) -> Result<()> {
+    ensure!(
+        tma.operation == TmaOperation::Reduce,
+        "{} is not a TMA reduction",
+        policy.id
+    );
+    let reduction = tma
+        .reduction
+        .with_context(|| format!("{} has no TMA reduction contract", policy.id))?;
+    let recipe = tma_reduction_recipe(reduction)?;
+    ensure!(
+        policy.id == recipe.id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record.as_str())
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol.as_str())
+            && policy.resolved_llvm_symbol.is_none()
+            && declaration.source_record == recipe.source_record
+            && declaration.llvm_name == recipe.llvm_symbol,
+        "{} TMA reduction identity changed",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "tma"
+            && policy.rust_name == recipe.id
+            && policy.rust_arguments == recipe.rust_arguments
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::tma::{}", recipe.id)
+            && policy.compatibility_rust_paths == [format!("cuda_device::tma::{}", recipe.id)],
+        "{} TMA reduction Rust API changed",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == recipe.dialect_operands
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == recipe.llvm_arguments
+            && policy.llvm_results.is_empty()
+            && declaration.arguments == recipe.llvm_arguments
+            && declaration.results.is_empty()
+            && declaration.selections.is_empty()
+            && policy.lowering == "generated_tma",
+        "{} TMA reduction carrier or LLVM adapter changed",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read_write"
+            && policy.convergent
+            && policy.execution_scope == "thread"
+            && tma.adapter == TmaAdapter::ReductionPointersCoordinatesInjectDefaults
+            && tma.runtime_validation == RuntimeValidation::Unexecuted,
+        "{} TMA reduction semantics changed",
+        policy.id
+    );
+    ensure!(
+        policy.minimum_ptx == "8.0"
+            && policy.minimum_sm.as_deref() == Some("sm_90")
+            && policy.targets == "all"
+            && policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.9.26.5.3 Data Movement and Conversion Instructions: cp.reduce.async.bulk.tensor"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor"
+            && policy.ptx_result == "()"
+            && policy.expected_ptx.mnemonic == "cp"
+            && policy.expected_ptx.modifiers == recipe.modifiers
+            && policy.expected_ptx.operands == recipe.operands,
+        "{} TMA reduction target or PTX contract changed",
+        policy.id
+    );
+    let valid_route = |backend, mechanism| {
+        policy.backend_lowerings.iter().any(|route| {
+            route.backend == backend
+                && route.mechanism == mechanism
+                && route.minimum_ptx.as_deref() == Some("8.0")
+                && route.minimum_sm.as_deref() == Some("sm_90")
+                && !route.evidence_profile.trim().is_empty()
+        })
+    };
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && valid_route(
+                IntrinsicBackend::LlvmNvptx,
+                BackendLoweringMechanism::TypedNvvm,
+            )
+            && valid_route(
+                IntrinsicBackend::LibNvvm,
+                BackendLoweringMechanism::InlinePtx,
+            ),
+        "{} TMA reduction backend route changed",
+        policy.id
+    );
+    ensure!(
+        declaration.properties == tma_reduction_imported_properties(reduction.dimensions as usize),
+        "{} imported TMA reduction declaration changed",
+        policy.id
+    );
+    ensure_no_other_family_contract(policy, "TMA")?;
+    Ok(())
+}
+
+pub(in crate::resolve) fn tma_imported_properties(operation: TmaOperation) -> Vec<String> {
+    assert_ne!(operation, TmaOperation::Reduce);
+    let dimensions = operation.dimensions();
+    if matches!(
+        operation,
+        TmaOperation::G2sTile1d
+            | TmaOperation::G2sTile2d
+            | TmaOperation::G2sTile2dMulticast
+            | TmaOperation::G2sTile2dMulticastCg2
+            | TmaOperation::G2sTile3d
+            | TmaOperation::G2sTile4d
+            | TmaOperation::G2sTile5d
+    ) {
+        let dimensions = dimensions.unwrap();
+        let mut properties = vec![
+            format!("ImmArg<arg{}>", dimensions + 5),
+            format!("ImmArg<arg{}>", dimensions + 6),
+            format!("ImmArg<arg{}>", dimensions + 7),
+            "IntrConvergent".into(),
+            format!("Range<arg{},0,3>", dimensions + 7),
+            "ReadOnly<arg2>".into(),
+            "WriteOnly<arg0>".into(),
+        ];
+        properties.sort();
+        return properties;
+    }
+    if matches!(
+        operation,
+        TmaOperation::S2gTile1d
+            | TmaOperation::S2gTile2d
+            | TmaOperation::S2gTile3d
+            | TmaOperation::S2gTile4d
+            | TmaOperation::S2gTile5d
+    ) {
+        return vec![
+            format!("ImmArg<arg{}>", dimensions.unwrap() + 3),
+            "IntrConvergent".into(),
+            "ReadOnly<arg0>".into(),
+            "ReadOnly<arg1>".into(),
+        ];
+    }
+    if operation == TmaOperation::CommitGroup {
+        return vec![];
+    }
+    if matches!(
+        operation,
+        TmaOperation::WaitGroup | TmaOperation::WaitGroupRead
+    ) {
+        return vec!["ImmArg<arg0>".into()];
+    }
+    if operation == TmaOperation::PrefetchTensorMap {
+        return vec![
+            "IntrArgMemOnly".into(),
+            "NoCapture<arg0>".into(),
+            "ReadOnly<arg0>".into(),
+        ];
+    }
+    if let Some(coordinate_count) = operation.prefetch_coordinate_count() {
+        return vec![
+            format!("ImmArg<arg{}>", coordinate_count + 2),
+            "IntrConvergent".into(),
+            "ReadOnly<arg0>".into(),
+        ];
+    }
+    if matches!(
+        operation,
+        TmaOperation::FenceProxyTensorMapAcquireCluster
+            | TmaOperation::FenceProxyTensorMapAcquireCta
+            | TmaOperation::FenceProxyTensorMapAcquireGpu
+            | TmaOperation::FenceProxyTensorMapAcquireSystem
+    ) {
+        return vec![
+            "ImmArg<arg1>".into(),
+            "IntrArgMemOnly".into(),
+            "IntrNoCallback".into(),
+            "Range<arg1,128,129>".into(),
+        ];
+    }
+    if matches!(
+        operation,
+        TmaOperation::FenceProxyTensorMapReleaseCluster
+            | TmaOperation::FenceProxyTensorMapReleaseCta
+            | TmaOperation::FenceProxyTensorMapReleaseGpu
+            | TmaOperation::FenceProxyTensorMapReleaseSystem
+    ) {
+        return vec!["IntrNoCallback".into()];
+    }
+
+    let mut properties = vec![
+        "IntrArgMemOnly".into(),
+        "IntrWriteMem".into(),
+        "NoCapture<arg0>".into(),
+    ];
+    match operation {
+        TmaOperation::ReplaceBoxDim
+        | TmaOperation::ReplaceElementStride
+        | TmaOperation::ReplaceGlobalDim
+        | TmaOperation::ReplaceGlobalStride => {
+            properties.push("ImmArg<arg1>".into());
+        }
+        TmaOperation::ReplaceElementType => {
+            properties.extend([
+                "ArgInfo<arg1>".into(),
+                "ImmArg<arg1>".into(),
+                "Range<arg1,0,16>".into(),
+            ]);
+        }
+        TmaOperation::ReplaceFillMode => {
+            properties.extend([
+                "ArgInfo<arg1>".into(),
+                "ImmArg<arg1>".into(),
+                "Range<arg1,0,2>".into(),
+            ]);
+        }
+        TmaOperation::ReplaceInterleaveLayout => {
+            properties.extend([
+                "ArgInfo<arg1>".into(),
+                "ImmArg<arg1>".into(),
+                "Range<arg1,0,3>".into(),
+            ]);
+        }
+        TmaOperation::ReplaceSwizzleAtomicity => {
+            properties.extend([
+                "ArgInfo<arg1>".into(),
+                "ImmArg<arg1>".into(),
+                "Range<arg1,0,4>".into(),
+            ]);
+        }
+        TmaOperation::ReplaceSwizzleMode => {
+            properties.extend([
+                "ArgInfo<arg1>".into(),
+                "ImmArg<arg1>".into(),
+                "Range<arg1,0,5>".into(),
+            ]);
+        }
+        TmaOperation::ReplaceGlobalAddress | TmaOperation::ReplaceRank => {}
+        _ => unreachable!("closed TMA operation property contract"),
+    }
+    properties.sort();
+    properties
+}
+
+pub(in crate::resolve) fn tma_reduction_imported_properties(dimensions: usize) -> Vec<String> {
+    vec![
+        format!("ImmArg<arg{}>", dimensions + 3),
+        "IntrConvergent".into(),
+        "ReadOnly<arg0>".into(),
+        "ReadOnly<arg1>".into(),
+    ]
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/warp.rs b/crates/cuda-intrinsics-gen/src/resolve/families/warp.rs
new file mode 100644
index 0000000000..e9292c33b9
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/families/warp.rs
@@ -0,0 +1,1702 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    ActiveMaskAdapter, ActiveMaskObservation, BackendLoweringMechanism, ImportedIntrinsic,
+    IntrinsicBackend, IntrinsicSource, MaskEncoding, MatchOperandEncoding, OverlayIntrinsic,
+    PreSm70MemberMaskRule, VoteAdapter, VoteMode, VoteParticipation, WarpBarrierAdapter,
+    WarpBarrierMaskEncoding, WarpBarrierMemoryOrdering, WarpBarrierParticipation, WarpMatchAdapter,
+    WarpMatchMode, WarpMatchParticipation, WarpMatchValueWidth, WarpShuffleAdapter,
+    WarpShuffleMode, WarpShuffleOperandEncoding, WarpShuffleParticipation, WarpShuffleSourceLane,
+    WarpShuffleValueKind,
+};
+use crate::ptx::OperandPattern;
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeSet;
+
+use super::*;
+
+pub(in crate::resolve) fn validate_sync_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    if let Some(scope) = threadfence_scope_for_id(&policy.id) {
+        return validate_threadfence_policy(policy, declaration, scope);
+    }
+    ensure!(
+        policy.id == "sync_threads"
+            && policy.abi_id == "i0034"
+            && policy.operation_key == "synchronization.cta.barrier.aligned.all"
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some("int_nvvm_barrier_cta_sync_aligned_all")
+            && policy.llvm_symbol.as_deref() == Some("llvm.nvvm.barrier.cta.sync.aligned.all")
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} sync identity does not match the closed sync_threads recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "thread"
+            && policy.rust_name == "sync_threads"
+            && policy.rust_arguments.is_empty()
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == "cuda_intrinsics::thread::sync_threads"
+            && policy.compatibility_rust_paths
+                == [
+                    "cuda_device::thread::sync_threads",
+                    "cuda_device::sync_threads",
+                ],
+        "{} must preserve the unsafe sync_threads raw API and both cuda-device compatibility paths",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == "Barrier0Op"
+            && policy.dialect_op_name == "nvvm.barrier0"
+            && policy.dialect_operands.is_empty()
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == ["i32"]
+            && policy.llvm_results.is_empty()
+            && policy.lowering == "generated_sync_threads",
+        "{} is outside the fixed-zero sync_threads lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read_write"
+            && policy.convergent
+            && policy.execution_scope == "cta"
+            && policy.minimum_ptx == "1.0"
+            && policy.minimum_sm.is_none()
+            && policy.ptx_result == "()"
+            && policy.targets == "all",
+        "{} sync effects or native target floor disagree with the closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier",
+        "{} sync PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.properties == ["IntrConvergent", "IntrNoCallback"],
+        "{} sync properties disagree with the imported LLVM declaration",
+        policy.id
+    );
+    ensure!(
+        policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with sync",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "bar"
+            && policy.expected_ptx.modifiers == ["sync"]
+            && policy.expected_ptx.operands == [OperandPattern::Exact { value: "0".into() }],
+        "{} expected PTX does not match literal bar.sync 0",
+        policy.id
+    );
+
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ]),
+        "{} must define exactly the reviewed LLVM typed and libNVVM inline-PTX routes",
+        policy.id
+    );
+    for lowering in &policy.backend_lowerings {
+        let floor_matches = match lowering.backend {
+            IntrinsicBackend::LlvmNvptx => {
+                lowering.mechanism == BackendLoweringMechanism::TypedNvvm
+                    && lowering.minimum_ptx.as_deref() == Some("3.2")
+                    && lowering.minimum_sm.as_deref() == Some("sm_20")
+            }
+            IntrinsicBackend::LibNvvm => {
+                lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                    && lowering.minimum_ptx.is_none()
+                    && lowering.minimum_sm.as_deref() == Some("sm_75")
+            }
+        };
+        ensure!(
+            floor_matches && !lowering.evidence_profile.trim().is_empty(),
+            "{} backend {:?} does not carry its reviewed sync profile floor",
+            policy.id,
+            lowering.backend
+        );
+    }
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_vote_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let vote = policy
+        .vote
+        .as_ref()
+        .with_context(|| format!("{} has no closed vote contract", policy.id))?;
+    let recipe = vote_recipe(vote.mode);
+    ensure!(
+        vote.participation
+            == VoteParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask
+            && vote.legacy_pre_sm70
+                == PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive
+            && vote.adapter == VoteAdapter::DirectMaskPredicate
+            && vote.mask_encoding == MaskEncoding::RegisterOrImmediate,
+        "{} requests an unsupported vote participation, pre-sm70 rule, adapter, or mask encoding",
+        policy.id
+    );
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} vote identity does not match its closed mode recipe",
+        policy.id
+    );
+    let expected_compatibility_paths: Vec<String> = if recipe.has_compatibility_path {
+        vec![format!("cuda_device::warp::{}", recipe.rust_name)]
+    } else {
+        vec![]
+    };
+    ensure!(
+        policy.rust_module == "warp"
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == ["u32", "bool"]
+            && policy.rust_result == recipe.rust_result
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::warp::{}", recipe.rust_name)
+            && policy.compatibility_rust_paths == expected_compatibility_paths,
+        "{} must preserve its unsafe must-use vote raw API and reviewed compatibility path",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == ["i32", "i1"]
+            && policy.dialect_results == [recipe.llvm_result]
+            && policy.llvm_arguments == ["i32", "i1"]
+            && policy.llvm_results == [recipe.llvm_result]
+            && policy.lowering == "generated_vote",
+        "{} is outside the closed two-operand vote lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "inaccessible_read_write"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == "6.0"
+            && policy.minimum_sm.as_deref() == Some("sm_30")
+            && policy.ptx_result == recipe.rust_result
+            && policy.targets == "all",
+        "{} vote effects, carrier, or target floor disagree with its mode recipe",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section == "9.7.14.10 Warp Vote Instructions: vote.sync"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-vote-sync",
+        "{} vote PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.properties
+            == [
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+        "{} vote memory and convergence effects disagree with the imported declaration",
+        policy.id
+    );
+    ensure!(
+        policy.backend_lowerings.is_empty()
+            && policy.packed_atomic.is_none()
+            && policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.redux.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with vote",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "vote"
+            && policy.expected_ptx.modifiers == ["sync", recipe.ptx_mode, recipe.ptx_type]
+            && policy.expected_ptx.operands
+                == [
+                    OperandPattern::Register,
+                    OperandPattern::Register,
+                    OperandPattern::RegisterOrImmediate,
+                ],
+        "{} expected PTX does not match its closed vote mode recipe",
+        policy.id
+    );
+
+    let expected_selection_records =
+        BTreeSet::from([recipe.immediate_selection, recipe.register_selection]);
+    let actual_selection_records: BTreeSet<_> = declaration
+        .selections
+        .iter()
+        .map(|selection| selection.source_record.as_str())
+        .collect();
+    ensure!(
+        declaration.selections.len() == 2 && actual_selection_records == expected_selection_records,
+        "{} vote declaration must contain exactly its immediate/register selection pair",
+        policy.id
+    );
+    let expected_asm = format!(
+        "vote.sync.{}.{} \t$dest, $pred, $mask;",
+        recipe.ptx_mode, recipe.ptx_type
+    );
+    for selection in &declaration.selections {
+        ensure!(
+            selection.asm == expected_asm
+                && selection.predicates
+                    == [
+                        "Subtarget->getPTXVersion() >= 60",
+                        "Subtarget->getSmVersion() >= 30",
+                    ]
+                && selection.constraints.is_empty(),
+            "{} vote immediate/register selections disagree on PTX shape, target predicates, or constraints",
+            policy.id
+        );
+    }
+    Ok(())
+}
+
+pub(in crate::resolve) struct VoteRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) rust_name: &'static str,
+    pub(in crate::resolve) rust_result: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) llvm_result: &'static str,
+    pub(in crate::resolve) ptx_mode: &'static str,
+    pub(in crate::resolve) ptx_type: &'static str,
+    pub(in crate::resolve) immediate_selection: &'static str,
+    pub(in crate::resolve) register_selection: &'static str,
+    pub(in crate::resolve) has_compatibility_path: bool,
+}
+
+pub(in crate::resolve) fn vote_recipe(mode: VoteMode) -> VoteRecipe {
+    match mode {
+        VoteMode::All => VoteRecipe {
+            id: "all_sync",
+            abi_id: "i0040",
+            operation_key: "warp.vote.sync.all.pred",
+            source_record: "int_nvvm_vote_all_sync",
+            llvm_symbol: "llvm.nvvm.vote.all.sync",
+            rust_name: "all_sync",
+            rust_result: "bool",
+            dialect_op_type: "VoteSyncAllOp",
+            dialect_op_name: "nvvm.vote_sync_all",
+            llvm_result: "i1",
+            ptx_mode: "all",
+            ptx_type: "pred",
+            immediate_selection: "VOTE_SYNC_ALLi",
+            register_selection: "VOTE_SYNC_ALLr",
+            has_compatibility_path: true,
+        },
+        VoteMode::Any => VoteRecipe {
+            id: "any_sync",
+            abi_id: "i0041",
+            operation_key: "warp.vote.sync.any.pred",
+            source_record: "int_nvvm_vote_any_sync",
+            llvm_symbol: "llvm.nvvm.vote.any.sync",
+            rust_name: "any_sync",
+            rust_result: "bool",
+            dialect_op_type: "VoteSyncAnyOp",
+            dialect_op_name: "nvvm.vote_sync_any",
+            llvm_result: "i1",
+            ptx_mode: "any",
+            ptx_type: "pred",
+            immediate_selection: "VOTE_SYNC_ANYi",
+            register_selection: "VOTE_SYNC_ANYr",
+            has_compatibility_path: true,
+        },
+        VoteMode::Ballot => VoteRecipe {
+            id: "ballot_sync",
+            abi_id: "i0042",
+            operation_key: "warp.vote.sync.ballot.b32",
+            source_record: "int_nvvm_vote_ballot_sync",
+            llvm_symbol: "llvm.nvvm.vote.ballot.sync",
+            rust_name: "ballot_sync",
+            rust_result: "u32",
+            dialect_op_type: "VoteSyncBallotOp",
+            dialect_op_name: "nvvm.vote_sync_ballot",
+            llvm_result: "i32",
+            ptx_mode: "ballot",
+            ptx_type: "b32",
+            immediate_selection: "VOTE_SYNC_BALLOTi",
+            register_selection: "VOTE_SYNC_BALLOTr",
+            has_compatibility_path: true,
+        },
+        VoteMode::Uni => VoteRecipe {
+            id: "uni_sync",
+            abi_id: "i0043",
+            operation_key: "warp.vote.sync.uni.pred",
+            source_record: "int_nvvm_vote_uni_sync",
+            llvm_symbol: "llvm.nvvm.vote.uni.sync",
+            rust_name: "uni_sync",
+            rust_result: "bool",
+            dialect_op_type: "VoteSyncUniOp",
+            dialect_op_name: "nvvm.vote_sync_uni",
+            llvm_result: "i1",
+            ptx_mode: "uni",
+            ptx_type: "pred",
+            immediate_selection: "VOTE_SYNC_UNIi",
+            register_selection: "VOTE_SYNC_UNIr",
+            has_compatibility_path: false,
+        },
+    }
+}
+
+pub(in crate::resolve) fn validate_active_mask_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let active_mask = policy
+        .active_mask
+        .as_ref()
+        .with_context(|| format!("{} has no closed active-mask contract", policy.id))?;
+    ensure!(
+        active_mask.observation == ActiveMaskObservation::ExecutingLanesAtInstruction
+            && active_mask.adapter == ActiveMaskAdapter::DirectZeroOperandMask,
+        "{} requests an unsupported active-mask observation or adapter",
+        policy.id
+    );
+    ensure!(
+        policy.id == "active_mask"
+            && policy.abi_id == "i0044"
+            && policy.operation_key == "warp.active_mask"
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some("int_nvvm_activemask")
+            && policy.llvm_symbol.as_deref() == Some("llvm.nvvm.activemask")
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} active-mask identity does not match the closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "warp"
+            && policy.rust_name == "active_mask"
+            && policy.rust_arguments.is_empty()
+            && policy.rust_result == "u32"
+            && policy.safe
+            && policy.must_use
+            && policy
+                .safe_allowlist_reason
+                .as_deref()
+                .is_some_and(|reason| !reason.is_empty())
+            && policy.public_rust_path == "cuda_intrinsics::warp::active_mask"
+            && policy.compatibility_rust_paths == ["cuda_device::warp::active_mask"],
+        "{} must preserve its safe must-use raw and compatibility APIs",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == "ActiveMaskOp"
+            && policy.dialect_op_name == "nvvm.activemask"
+            && policy.dialect_operands.is_empty()
+            && policy.dialect_results == ["i32"]
+            && policy.llvm_arguments.is_empty()
+            && policy.llvm_results == ["i32"]
+            && policy.lowering == "generated_active_mask",
+        "{} is outside the closed zero-operand active-mask lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "inaccessible_read_write"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == "6.2"
+            && policy.minimum_sm.as_deref() == Some("sm_30")
+            && policy.ptx_result == "u32"
+            && policy.targets == "all",
+        "{} active-mask effects or target floor disagree with the closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.14.12 Parallel Synchronization and Communication Instructions: activemask"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-activemask",
+        "{} active-mask PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.properties
+            == [
+                "IntrConvergent",
+                "IntrHasSideEffects",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ]
+            && declaration.selections.len() == 1
+            && declaration.selections[0].source_record == "ACTIVEMASK"
+            && declaration.selections[0].asm == "activemask.b32 \t$dest;"
+            && declaration.selections[0].predicates
+                == [
+                    "Subtarget->getSmVersion() >= 30",
+                    "Subtarget->getPTXVersion() >= 62",
+                ]
+            && declaration.selections[0].constraints.is_empty(),
+        "{} active-mask declaration or selection facts changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "activemask"
+            && policy.expected_ptx.modifiers == ["b32"]
+            && policy.expected_ptx.operands == [OperandPattern::Register],
+        "{} expected PTX does not match activemask.b32",
+        policy.id
+    );
+    ensure!(
+        policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with active_mask",
+        policy.id
+    );
+
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ]),
+        "{} must keep the LLVM typed and libNVVM inline-PTX routes explicit",
+        policy.id
+    );
+    for lowering in &policy.backend_lowerings {
+        let floor_matches = match lowering.backend {
+            IntrinsicBackend::LlvmNvptx => {
+                lowering.mechanism == BackendLoweringMechanism::TypedNvvm
+                    && lowering.minimum_ptx.as_deref() == Some("6.2")
+                    && lowering.minimum_sm.as_deref() == Some("sm_30")
+            }
+            IntrinsicBackend::LibNvvm => {
+                lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                    && lowering.minimum_ptx.is_none()
+                    && lowering.minimum_sm.as_deref() == Some("sm_75")
+            }
+        };
+        ensure!(
+            floor_matches && !lowering.evidence_profile.trim().is_empty(),
+            "{} backend {:?} does not carry its reviewed active-mask floor",
+            policy.id,
+            lowering.backend
+        );
+    }
+    Ok(())
+}
+
+pub(in crate::resolve) struct WarpMatchRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source_record: &'static str,
+    pub(in crate::resolve) llvm_symbol: &'static str,
+    pub(in crate::resolve) rust_name: &'static str,
+    pub(in crate::resolve) rust_value: &'static str,
+    pub(in crate::resolve) llvm_value: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) ptx_mode: &'static str,
+    pub(in crate::resolve) ptx_type: &'static str,
+    pub(in crate::resolve) selections: [&'static str; 4],
+    pub(in crate::resolve) adapter: WarpMatchAdapter,
+}
+
+pub(in crate::resolve) fn warp_match_recipe(
+    mode: WarpMatchMode,
+    width: WarpMatchValueWidth,
+) -> WarpMatchRecipe {
+    match (mode, width) {
+        (WarpMatchMode::Any, WarpMatchValueWidth::B32) => WarpMatchRecipe {
+            id: "match_any_sync",
+            abi_id: "i0045",
+            operation_key: "warp.match.sync.any.b32",
+            source_record: "int_nvvm_match_any_sync_i32",
+            llvm_symbol: "llvm.nvvm.match.any.sync.i32",
+            rust_name: "match_any_sync",
+            rust_value: "u32",
+            llvm_value: "i32",
+            dialect_op_type: "MatchAnySyncI32Op",
+            dialect_op_name: "nvvm.match_any_sync_i32",
+            ptx_mode: "any",
+            ptx_type: "b32",
+            selections: [
+                "MATCH_ANY_SYNC_32ii",
+                "MATCH_ANY_SYNC_32ir",
+                "MATCH_ANY_SYNC_32ri",
+                "MATCH_ANY_SYNC_32rr",
+            ],
+            adapter: WarpMatchAdapter::DirectMask,
+        },
+        (WarpMatchMode::Any, WarpMatchValueWidth::B64) => WarpMatchRecipe {
+            id: "match_any_i64_sync",
+            abi_id: "i0046",
+            operation_key: "warp.match.sync.any.b64",
+            source_record: "int_nvvm_match_any_sync_i64",
+            llvm_symbol: "llvm.nvvm.match.any.sync.i64",
+            rust_name: "match_any_i64_sync",
+            rust_value: "u64",
+            llvm_value: "i64",
+            dialect_op_type: "MatchAnySyncI64Op",
+            dialect_op_name: "nvvm.match_any_sync_i64",
+            ptx_mode: "any",
+            ptx_type: "b64",
+            selections: [
+                "MATCH_ANY_SYNC_64ii",
+                "MATCH_ANY_SYNC_64ir",
+                "MATCH_ANY_SYNC_64ri",
+                "MATCH_ANY_SYNC_64rr",
+            ],
+            adapter: WarpMatchAdapter::DirectMask,
+        },
+        (WarpMatchMode::All, WarpMatchValueWidth::B32) => WarpMatchRecipe {
+            id: "match_all_sync",
+            abi_id: "i0047",
+            operation_key: "warp.match.sync.all.b32",
+            source_record: "int_nvvm_match_all_sync_i32p",
+            llvm_symbol: "llvm.nvvm.match.all.sync.i32p",
+            rust_name: "match_all_sync",
+            rust_value: "u32",
+            llvm_value: "i32",
+            dialect_op_type: "MatchAllSyncI32Op",
+            dialect_op_name: "nvvm.match_all_sync_i32",
+            ptx_mode: "all",
+            ptx_type: "b32",
+            selections: [
+                "MATCH_ALLP_SYNC_32ii",
+                "MATCH_ALLP_SYNC_32ir",
+                "MATCH_ALLP_SYNC_32ri",
+                "MATCH_ALLP_SYNC_32rr",
+            ],
+            adapter: WarpMatchAdapter::ProjectMaskDiscardPredicate,
+        },
+        (WarpMatchMode::All, WarpMatchValueWidth::B64) => WarpMatchRecipe {
+            id: "match_all_i64_sync",
+            abi_id: "i0048",
+            operation_key: "warp.match.sync.all.b64",
+            source_record: "int_nvvm_match_all_sync_i64p",
+            llvm_symbol: "llvm.nvvm.match.all.sync.i64p",
+            rust_name: "match_all_i64_sync",
+            rust_value: "u64",
+            llvm_value: "i64",
+            dialect_op_type: "MatchAllSyncI64Op",
+            dialect_op_name: "nvvm.match_all_sync_i64",
+            ptx_mode: "all",
+            ptx_type: "b64",
+            selections: [
+                "MATCH_ALLP_SYNC_64ii",
+                "MATCH_ALLP_SYNC_64ir",
+                "MATCH_ALLP_SYNC_64ri",
+                "MATCH_ALLP_SYNC_64rr",
+            ],
+            adapter: WarpMatchAdapter::ProjectMaskDiscardPredicate,
+        },
+    }
+}
+
+pub(in crate::resolve) fn validate_warp_match_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let warp_match = policy
+        .warp_match
+        .as_ref()
+        .with_context(|| format!("{} has no closed warp-match contract", policy.id))?;
+    let recipe = warp_match_recipe(warp_match.mode, warp_match.value_width);
+    ensure!(
+        warp_match.participation
+            == WarpMatchParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask
+            && warp_match.adapter == recipe.adapter
+            && warp_match.value_encoding == MatchOperandEncoding::RegisterOrImmediate
+            && warp_match.mask_encoding == MatchOperandEncoding::RegisterOrImmediate,
+        "{} requests an unsupported warp-match participation, adapter, or encoding",
+        policy.id
+    );
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some(recipe.source_record)
+            && policy.llvm_symbol.as_deref() == Some(recipe.llvm_symbol)
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} warp-match identity does not match its closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "warp"
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == ["u32", recipe.rust_value]
+            && policy.rust_result == "u32"
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::warp::{}", recipe.rust_name)
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::warp::{}", recipe.rust_name)],
+        "{} must preserve its unsafe raw and stable compatibility paths",
+        policy.id
+    );
+    let expected_llvm_results: &[&str] = match warp_match.mode {
+        WarpMatchMode::Any => &["i32"],
+        WarpMatchMode::All => &["i32", "i1"],
+    };
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == ["i32", recipe.llvm_value]
+            && policy.dialect_results == ["i32"]
+            && policy.llvm_arguments == ["i32", recipe.llvm_value]
+            && policy.llvm_results == expected_llvm_results
+            && policy.lowering == "generated_warp_match",
+        "{} is outside the closed two-operand warp-match lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "inaccessible_read_write"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == "6.0"
+            && policy.minimum_sm.as_deref() == Some("sm_70")
+            && policy.ptx_result == "u32"
+            && policy.targets == "all",
+        "{} warp-match effects, carrier, or target floor disagree with its recipe",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.14.11 Parallel Synchronization and Communication Instructions: match.sync"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-match-sync",
+        "{} warp-match PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.properties
+            == [
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+        "{} warp-match effects disagree with the imported declaration",
+        policy.id
+    );
+    ensure!(
+        policy.backend_lowerings.is_empty()
+            && policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with warp_match",
+        policy.id
+    );
+    let destination = match warp_match.mode {
+        WarpMatchMode::Any => OperandPattern::Register,
+        WarpMatchMode::All => OperandPattern::RegisterPredicatePair,
+    };
+    ensure!(
+        policy.expected_ptx.mnemonic == "match"
+            && policy.expected_ptx.modifiers == [recipe.ptx_mode, "sync", recipe.ptx_type]
+            && policy.expected_ptx.operands
+                == [
+                    destination,
+                    OperandPattern::RegisterOrImmediate,
+                    OperandPattern::RegisterOrImmediate,
+                ],
+        "{} expected PTX does not match its closed match.sync recipe",
+        policy.id
+    );
+    let actual_selection_records: BTreeSet<_> = declaration
+        .selections
+        .iter()
+        .map(|selection| selection.source_record.as_str())
+        .collect();
+    ensure!(
+        declaration.selections.len() == 4
+            && actual_selection_records == BTreeSet::from(recipe.selections),
+        "{} warp-match declaration must contain exactly ii/ir/ri/rr selections",
+        policy.id
+    );
+    let destination = if warp_match.mode == WarpMatchMode::All {
+        "$dest|$pred"
+    } else {
+        "$dest"
+    };
+    let expected_asm = format!(
+        "match.{}.sync.{} \t{}, $value, $mask;",
+        recipe.ptx_mode, recipe.ptx_type, destination
+    );
+    for selection in &declaration.selections {
+        ensure!(
+            selection.asm == expected_asm
+                && selection.predicates
+                    == [
+                        "Subtarget->getPTXVersion() >= 60",
+                        "Subtarget->getSmVersion() >= 70",
+                    ]
+                && selection.constraints.is_empty(),
+            "{} warp-match selections disagree on PTX shape, predicates, or constraints",
+            policy.id
+        );
+    }
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_elect_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    ensure!(
+        policy.id == "elect_sync"
+            && policy.abi_id == "i0367"
+            && policy.operation_key == "warp.elect.sync"
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some("int_nvvm_elect_sync")
+            && policy.llvm_symbol.as_deref() == Some("llvm.nvvm.elect.sync")
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} elect identity does not match the closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "warp"
+            && policy.rust_name == "elect_sync"
+            && policy.rust_arguments == ["u32"]
+            && policy.rust_result == "(u32, bool)"
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == "cuda_intrinsics::warp::elect_sync"
+            && policy.compatibility_rust_paths == ["cuda_device::warp::elect_sync"],
+        "{} must keep its unsafe raw API and stable compatibility path",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == "ElectSyncOp"
+            && policy.dialect_op_name == "nvvm.elect_sync"
+            && policy.dialect_operands == ["i32"]
+            && policy.dialect_results == ["i32", "i1"]
+            && policy.llvm_arguments == ["i32"]
+            && policy.llvm_results == ["i32", "i1"]
+            && policy.lowering == "generated_elect",
+        "{} is outside the closed elect lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "inaccessible_read_write"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == "8.0"
+            && policy.minimum_sm.as_deref() == Some("sm_90")
+            && policy.ptx_result == "(u32, bool)"
+            && policy.targets == "all",
+        "{} elect effects or target floor disagree with the closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.14.15 Parallel Synchronization and Communication Instructions: elect.sync"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-elect-sync",
+        "{} elect PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.classes == ["SDPatternOperator", "Intrinsic", "DefaultAttrsIntrinsic"]
+            && declaration.properties == ["IntrConvergent", "IntrInaccessibleMemOnly"]
+            && declaration.arguments == ["i32"]
+            && declaration.results == ["i32", "i1"],
+        "{} elect declaration facts changed",
+        policy.id
+    );
+    ensure!(
+        declaration.selections.len() == 2
+            && declaration.selections.iter().all(|selection| {
+                ["INT_ELECT_SYNC_I", "INT_ELECT_SYNC_R"].contains(&selection.source_record.as_str())
+                    && selection.asm == "elect.sync \t$dest|$pred, $mask;"
+                    && selection.predicates
+                        == [
+                            "Subtarget->getPTXVersion() >= 80",
+                            "Subtarget->getSmVersion() >= 90",
+                        ]
+                    && selection.constraints.is_empty()
+            }),
+        "{} elect selections changed",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "elect"
+            && policy.expected_ptx.modifiers == ["sync"]
+            && policy.expected_ptx.operands
+                == [
+                    OperandPattern::RegisterPredicatePair,
+                    OperandPattern::RegisterOrImmediate,
+                ],
+        "{} expected PTX does not match elect.sync",
+        policy.id
+    );
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && policy.backend_lowerings.iter().any(|route| {
+                route.backend == IntrinsicBackend::LlvmNvptx
+                    && route.mechanism == BackendLoweringMechanism::TypedNvvm
+                    && route.minimum_ptx.as_deref() == Some("8.0")
+                    && route.minimum_sm.as_deref() == Some("sm_90")
+                    && !route.evidence_profile.trim().is_empty()
+            })
+            && policy.backend_lowerings.iter().any(|route| {
+                route.backend == IntrinsicBackend::LibNvvm
+                    && route.mechanism == BackendLoweringMechanism::InlinePtx
+                    && route.minimum_ptx.as_deref() == Some("8.0")
+                    && route.minimum_sm.as_deref() == Some("sm_90")
+                    && !route.evidence_profile.trim().is_empty()
+            }),
+        "{} must keep the LLVM typed and libNVVM inline-PTX routes explicit",
+        policy.id
+    );
+    ensure!(
+        policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.cp_async_mbarrier.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.movmatrix.is_none()
+            && policy.mbarrier_extended.is_none()
+            && policy.register_mma.is_none()
+            && policy.sparse_mma.is_none()
+            && policy.prmt.is_none()
+            && policy.cluster_barrier.is_none()
+            && policy.wgmma_control.is_none()
+            && policy.special_register.is_none()
+            && policy.debug_control.is_none()
+            && policy.cluster_memory.is_none()
+            && policy.clc.is_none()
+            && policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with elect",
+        policy.id
+    );
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_warp_barrier_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let barrier = policy
+        .warp_barrier
+        .as_ref()
+        .with_context(|| format!("{} has no closed warp-barrier contract", policy.id))?;
+    ensure!(
+        barrier.participation
+            == WarpBarrierParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask
+            && barrier.legacy_pre_sm70
+                == PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive
+            && barrier.adapter == WarpBarrierAdapter::DirectMemberMask
+            && barrier.mask_encoding == WarpBarrierMaskEncoding::RegisterOrImmediate
+            && barrier.memory_ordering == WarpBarrierMemoryOrdering::ParticipatingLanes,
+        "{} requests an unsupported warp-barrier participation, legacy rule, adapter, mask encoding, or memory ordering",
+        policy.id
+    );
+    ensure!(
+        policy.id == "sync_mask"
+            && policy.abi_id == "i0049"
+            && policy.operation_key == "warp.barrier.sync.masked"
+            && policy.source.is_none()
+            && policy.source_record.as_deref() == Some("int_nvvm_bar_warp_sync")
+            && policy.llvm_symbol.as_deref() == Some("llvm.nvvm.bar.warp.sync")
+            && policy.resolved_llvm_symbol.is_none(),
+        "{} warp-barrier identity does not match the closed sync_mask recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "warp"
+            && policy.rust_name == "sync_mask"
+            && policy.rust_arguments == ["u32"]
+            && policy.rust_result == "()"
+            && !policy.safe
+            && !policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == "cuda_intrinsics::warp::sync_mask"
+            && policy.compatibility_rust_paths == ["cuda_device::warp::sync_mask"],
+        "{} must keep its unsafe raw API and safe cuda-device compatibility path distinct",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == "BarWarpSyncOp"
+            && policy.dialect_op_name == "nvvm.bar_warp_sync"
+            && policy.dialect_operands == ["i32"]
+            && policy.dialect_results.is_empty()
+            && policy.llvm_arguments == ["i32"]
+            && policy.llvm_results.is_empty()
+            && policy.lowering == "generated_warp_barrier",
+        "{} is outside the closed one-mask warp-barrier lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "read_write"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == "6.0"
+            && policy.minimum_sm.as_deref() == Some("sm_30")
+            && policy.ptx_result == "()"
+            && policy.targets == "all",
+        "{} warp-barrier effects or target floor disagree with the closed recipe",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.14.2 Parallel Synchronization and Communication Instructions: bar.warp.sync"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-warp-sync",
+        "{} warp-barrier PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    ensure!(
+        declaration.properties == ["IntrConvergent", "IntrNoCallback"],
+        "{} warp-barrier effects disagree with the imported declaration",
+        policy.id
+    );
+    ensure!(
+        policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with warp_barrier",
+        policy.id
+    );
+    ensure!(
+        policy.expected_ptx.mnemonic == "bar"
+            && policy.expected_ptx.modifiers == ["warp", "sync"]
+            && policy.expected_ptx.operands == [OperandPattern::RegisterOrImmediate],
+        "{} expected PTX does not match bar.warp.sync mask",
+        policy.id
+    );
+
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::TypedNvvm,
+                    ),
+                ]),
+        "{} must define exactly the reviewed typed LLVM and libNVVM routes",
+        policy.id
+    );
+    for lowering in &policy.backend_lowerings {
+        let floor_matches = match lowering.backend {
+            IntrinsicBackend::LlvmNvptx => {
+                lowering.mechanism == BackendLoweringMechanism::TypedNvvm
+                    && lowering.minimum_ptx.as_deref() == Some("6.0")
+                    && lowering.minimum_sm.as_deref() == Some("sm_30")
+            }
+            IntrinsicBackend::LibNvvm => {
+                lowering.mechanism == BackendLoweringMechanism::TypedNvvm
+                    && lowering.minimum_ptx.as_deref() == Some("6.0")
+                    && lowering.minimum_sm.as_deref() == Some("sm_75")
+            }
+        };
+        ensure!(
+            floor_matches && !lowering.evidence_profile.trim().is_empty(),
+            "{} backend {:?} does not carry its reviewed warp-barrier profile floor",
+            policy.id,
+            lowering.backend
+        );
+    }
+
+    let expected_selection_records = BTreeSet::from(["INT_BAR_WARP_SYNC_I", "INT_BAR_WARP_SYNC_R"]);
+    let actual_selection_records: BTreeSet<_> = declaration
+        .selections
+        .iter()
+        .map(|selection| selection.source_record.as_str())
+        .collect();
+    ensure!(
+        declaration.selections.len() == 2 && actual_selection_records == expected_selection_records,
+        "{} warp-barrier declaration must contain exactly its immediate/register selection pair",
+        policy.id
+    );
+    for selection in &declaration.selections {
+        ensure!(
+            selection.asm == "bar.warp.sync \t$i;"
+                && selection.predicates
+                    == [
+                        "Subtarget->getPTXVersion() >= 60",
+                        "Subtarget->getSmVersion() >= 30",
+                    ]
+                && selection.constraints.is_empty(),
+            "{} warp-barrier selections disagree on PTX shape, target predicates, or constraints",
+            policy.id
+        );
+    }
+    Ok(())
+}
+
+pub(in crate::resolve) fn validate_warp_shuffle_policy(
+    policy: &OverlayIntrinsic,
+    declaration: Option<&ImportedIntrinsic>,
+) -> Result<()> {
+    let shuffle = policy
+        .warp_shuffle
+        .as_ref()
+        .with_context(|| format!("{} has no closed warp-shuffle contract", policy.id))?;
+    let recipe = warp_shuffle_recipe(shuffle.mode, shuffle.value_kind);
+    ensure!(
+        shuffle.participation
+            == WarpShuffleParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask
+            && shuffle.legacy_pre_sm70
+                == PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive
+            && shuffle.source_lane
+                == WarpShuffleSourceLane::InRangeSourceActiveAndNamedOutOfRangeCopiesSelf
+            && shuffle.adapter == recipe.adapter
+            && shuffle.clamp == recipe.clamp
+            && shuffle.lane_encoding == recipe.operand_encoding
+            && shuffle.mask_encoding == recipe.operand_encoding,
+        "{} requests an unsupported warp-shuffle semantic or operand contract",
+        policy.id
+    );
+
+    let source_matches = match recipe.source {
+        WarpShuffleRecipeSource::LlvmImported {
+            source_record,
+            llvm_symbol,
+        } => {
+            policy.source.is_none()
+                && policy.source_record.as_deref() == Some(source_record)
+                && policy.llvm_symbol.as_deref() == Some(llvm_symbol)
+                && policy.resolved_llvm_symbol.is_none()
+        }
+        WarpShuffleRecipeSource::PtxNative { instruction } => {
+            policy.source
+                == Some(IntrinsicSource::PtxNative {
+                    instruction: instruction.into(),
+                })
+                && policy.source_record.is_none()
+                && policy.llvm_symbol.is_none()
+                && policy.resolved_llvm_symbol.is_none()
+                && policy.llvm_arguments.is_empty()
+                && policy.llvm_results.is_empty()
+        }
+    };
+    ensure!(
+        policy.id == recipe.id
+            && policy.abi_id == recipe.abi_id
+            && policy.operation_key == recipe.operation_key
+            && source_matches,
+        "{} warp-shuffle identity does not match its closed mode and value recipe",
+        policy.id
+    );
+    ensure!(
+        policy.rust_module == "warp"
+            && policy.rust_name == recipe.rust_name
+            && policy.rust_arguments == ["u32", recipe.rust_value, "u32"]
+            && policy.rust_result == recipe.rust_value
+            && !policy.safe
+            && policy.must_use
+            && policy.safe_allowlist_reason.is_none()
+            && policy.public_rust_path == format!("cuda_intrinsics::warp::{}", recipe.rust_name)
+            && policy.compatibility_rust_paths
+                == [format!("cuda_device::warp::{}", recipe.rust_name)],
+        "{} must preserve its unsafe must-use warp-shuffle raw API and compatibility path",
+        policy.id
+    );
+    ensure!(
+        policy.dialect_op_type == recipe.dialect_op_type
+            && policy.dialect_op_name == recipe.dialect_op_name
+            && policy.dialect_operands == ["i32", recipe.dialect_value, "i32"]
+            && policy.dialect_results == [recipe.dialect_value]
+            && policy.lowering == recipe.lowering
+            && match recipe.source {
+                WarpShuffleRecipeSource::LlvmImported { .. } => {
+                    policy.llvm_arguments == ["i32", recipe.dialect_value, "i32", "i32"]
+                        && policy.llvm_results == [recipe.dialect_value]
+                }
+                WarpShuffleRecipeSource::PtxNative { .. } => {
+                    policy.llvm_arguments.is_empty() && policy.llvm_results.is_empty()
+                }
+            },
+        "{} is outside the closed warp-shuffle lowering recipe",
+        policy.id
+    );
+    ensure!(
+        !policy.pure
+            && policy.memory == "inaccessible_read_write"
+            && policy.convergent
+            && policy.execution_scope == "warp"
+            && policy.minimum_ptx == "6.0"
+            && policy.minimum_sm.as_deref() == Some("sm_30")
+            && policy.ptx_result == recipe.rust_value
+            && policy.targets == "all",
+        "{} warp-shuffle effects, carrier, or target floor disagree with its recipe",
+        policy.id
+    );
+    ensure!(
+        policy.ptx_isa_version == "9.3"
+            && policy.ptx_isa_section
+                == "9.7.9.6 Data Movement and Conversion Instructions: shfl.sync"
+            && policy.ptx_isa_url
+                == "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-shfl-sync",
+        "{} warp-shuffle PTX provenance disagrees with the reviewed recipe",
+        policy.id
+    );
+    if let Some(declaration) = declaration {
+        ensure!(
+            matches!(recipe.source, WarpShuffleRecipeSource::LlvmImported { .. })
+                && declaration.classes
+                    == [
+                        "ClangBuiltin",
+                        "NVVMBuiltin",
+                        "SDPatternOperator",
+                        "Intrinsic"
+                    ]
+                && declaration.properties
+                    == [
+                        "IntrConvergent",
+                        "IntrInaccessibleMemOnly",
+                        "IntrNoCallback",
+                    ],
+            "{} warp-shuffle class or effects disagree with the imported declaration",
+            policy.id
+        );
+    } else {
+        ensure!(
+            matches!(recipe.source, WarpShuffleRecipeSource::PtxNative { .. }),
+            "{} imported warp shuffle is missing its LLVM declaration",
+            policy.id
+        );
+    }
+    ensure!(
+        policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.dot_product.is_none()
+            && policy.packed_alu.is_none()
+            && policy.packed_conversion.is_none()
+            && policy.cp_async_copy.is_none()
+            && policy.cp_async_control.is_none()
+            && policy.mbarrier_basic.is_none()
+            && policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && policy.selected_address_space.is_none(),
+        "{} mixes another generated-family contract with warp_shuffle",
+        policy.id
+    );
+    let expected_operands = match recipe.adapter {
+        WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp => vec![
+            OperandPattern::Register,
+            OperandPattern::Register,
+            OperandPattern::RegisterOrImmediate,
+            OperandPattern::Exact {
+                value: recipe.clamp.to_string(),
+            },
+            OperandPattern::RegisterOrImmediate,
+        ],
+        WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble => vec![
+            OperandPattern::Exact { value: "lo".into() },
+            OperandPattern::Exact { value: "lo".into() },
+            OperandPattern::Register,
+            OperandPattern::Exact {
+                value: recipe.clamp.to_string(),
+            },
+            OperandPattern::Register,
+        ],
+    };
+    ensure!(
+        policy.expected_ptx.mnemonic == "shfl"
+            && policy.expected_ptx.modifiers == ["sync", recipe.ptx_mode, "b32"]
+            && policy.expected_ptx.operands == expected_operands,
+        "{} expected PTX does not match its closed shfl.sync recipe",
+        policy.id
+    );
+
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (IntrinsicBackend::LlvmNvptx, recipe.backend_mechanism),
+                    (IntrinsicBackend::LibNvvm, recipe.backend_mechanism),
+                ]),
+        "{} must define exactly the reviewed LLVM and libNVVM routes",
+        policy.id
+    );
+    for lowering in &policy.backend_lowerings {
+        let floor_matches = match lowering.backend {
+            IntrinsicBackend::LlvmNvptx => {
+                lowering.mechanism == recipe.backend_mechanism
+                    && lowering.minimum_ptx.as_deref() == Some("6.0")
+                    && lowering.minimum_sm.as_deref() == Some("sm_30")
+            }
+            IntrinsicBackend::LibNvvm => {
+                lowering.mechanism == recipe.backend_mechanism
+                    && lowering.minimum_ptx.as_deref() == Some("6.0")
+                    && lowering.minimum_sm.as_deref() == Some("sm_75")
+            }
+        };
+        ensure!(
+            floor_matches && !lowering.evidence_profile.trim().is_empty(),
+            "{} backend {:?} does not carry its reviewed warp-shuffle profile floor",
+            policy.id,
+            lowering.backend
+        );
+    }
+
+    if let Some(declaration) = declaration {
+        let selection_records: BTreeSet<_> = declaration
+            .selections
+            .iter()
+            .map(|selection| selection.source_record.as_str())
+            .collect();
+        ensure!(
+            declaration.selections.len() == 8
+                && selection_records.len() == 8
+                && selection_records
+                    .iter()
+                    .all(|source_record| !source_record.trim().is_empty()),
+            "{} warp-shuffle declaration must contain exactly eight distinct operand-encoding selections",
+            policy.id
+        );
+        let expected_asm = format!(
+            "shfl.sync.{}.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+            recipe.ptx_mode
+        );
+        for selection in &declaration.selections {
+            ensure!(
+                selection.asm == expected_asm
+                    && selection.predicates
+                        == [
+                            "Subtarget->getPTXVersion() >= 60",
+                            "Subtarget->getSmVersion() >= 30",
+                        ]
+                    && selection.constraints.is_empty(),
+                "{} warp-shuffle selections disagree on PTX shape, target predicates, or constraints",
+                policy.id
+            );
+        }
+    }
+    Ok(())
+}
+
+#[derive(Clone, Copy)]
+pub(in crate::resolve) enum WarpShuffleRecipeSource {
+    LlvmImported {
+        source_record: &'static str,
+        llvm_symbol: &'static str,
+    },
+    PtxNative {
+        instruction: &'static str,
+    },
+}
+
+pub(in crate::resolve) struct WarpShuffleRecipe {
+    pub(in crate::resolve) id: &'static str,
+    pub(in crate::resolve) abi_id: &'static str,
+    pub(in crate::resolve) operation_key: &'static str,
+    pub(in crate::resolve) source: WarpShuffleRecipeSource,
+    pub(in crate::resolve) rust_name: &'static str,
+    pub(in crate::resolve) rust_value: &'static str,
+    pub(in crate::resolve) dialect_value: &'static str,
+    pub(in crate::resolve) dialect_op_type: &'static str,
+    pub(in crate::resolve) dialect_op_name: &'static str,
+    pub(in crate::resolve) ptx_mode: &'static str,
+    pub(in crate::resolve) clamp: u32,
+    pub(in crate::resolve) adapter: WarpShuffleAdapter,
+    pub(in crate::resolve) operand_encoding: WarpShuffleOperandEncoding,
+    pub(in crate::resolve) lowering: &'static str,
+    pub(in crate::resolve) backend_mechanism: BackendLoweringMechanism,
+}
+
+pub(in crate::resolve) fn warp_shuffle_recipe(
+    mode: WarpShuffleMode,
+    value_kind: WarpShuffleValueKind,
+) -> WarpShuffleRecipe {
+    match (mode, value_kind) {
+        (WarpShuffleMode::Idx, WarpShuffleValueKind::I32) => WarpShuffleRecipe {
+            id: "shuffle_sync",
+            abi_id: "i0050",
+            operation_key: "warp.shuffle.sync.idx.i32",
+            source: WarpShuffleRecipeSource::LlvmImported {
+                source_record: "int_nvvm_shfl_sync_idx_i32",
+                llvm_symbol: "llvm.nvvm.shfl.sync.idx.i32",
+            },
+            rust_name: "shuffle_sync",
+            rust_value: "u32",
+            dialect_value: "i32",
+            dialect_op_type: "ShflSyncIdxI32Op",
+            dialect_op_name: "nvvm.shfl_sync_idx_i32",
+            ptx_mode: "idx",
+            clamp: 31,
+            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
+            lowering: "generated_warp_shuffle",
+            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
+        },
+        (WarpShuffleMode::Bfly, WarpShuffleValueKind::I32) => WarpShuffleRecipe {
+            id: "shuffle_xor_sync",
+            abi_id: "i0051",
+            operation_key: "warp.shuffle.sync.bfly.i32",
+            source: WarpShuffleRecipeSource::LlvmImported {
+                source_record: "int_nvvm_shfl_sync_bfly_i32",
+                llvm_symbol: "llvm.nvvm.shfl.sync.bfly.i32",
+            },
+            rust_name: "shuffle_xor_sync",
+            rust_value: "u32",
+            dialect_value: "i32",
+            dialect_op_type: "ShflSyncBflyI32Op",
+            dialect_op_name: "nvvm.shfl_sync_bfly_i32",
+            ptx_mode: "bfly",
+            clamp: 31,
+            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
+            lowering: "generated_warp_shuffle",
+            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
+        },
+        (WarpShuffleMode::Down, WarpShuffleValueKind::I32) => WarpShuffleRecipe {
+            id: "shuffle_down_sync",
+            abi_id: "i0052",
+            operation_key: "warp.shuffle.sync.down.i32",
+            source: WarpShuffleRecipeSource::LlvmImported {
+                source_record: "int_nvvm_shfl_sync_down_i32",
+                llvm_symbol: "llvm.nvvm.shfl.sync.down.i32",
+            },
+            rust_name: "shuffle_down_sync",
+            rust_value: "u32",
+            dialect_value: "i32",
+            dialect_op_type: "ShflSyncDownI32Op",
+            dialect_op_name: "nvvm.shfl_sync_down_i32",
+            ptx_mode: "down",
+            clamp: 31,
+            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
+            lowering: "generated_warp_shuffle",
+            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
+        },
+        (WarpShuffleMode::Up, WarpShuffleValueKind::I32) => WarpShuffleRecipe {
+            id: "shuffle_up_sync",
+            abi_id: "i0053",
+            operation_key: "warp.shuffle.sync.up.i32",
+            source: WarpShuffleRecipeSource::LlvmImported {
+                source_record: "int_nvvm_shfl_sync_up_i32",
+                llvm_symbol: "llvm.nvvm.shfl.sync.up.i32",
+            },
+            rust_name: "shuffle_up_sync",
+            rust_value: "u32",
+            dialect_value: "i32",
+            dialect_op_type: "ShflSyncUpI32Op",
+            dialect_op_name: "nvvm.shfl_sync_up_i32",
+            ptx_mode: "up",
+            clamp: 0,
+            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
+            lowering: "generated_warp_shuffle",
+            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
+        },
+        (WarpShuffleMode::Idx, WarpShuffleValueKind::F32) => WarpShuffleRecipe {
+            id: "shuffle_f32_sync",
+            abi_id: "i0054",
+            operation_key: "warp.shuffle.sync.idx.f32",
+            source: WarpShuffleRecipeSource::LlvmImported {
+                source_record: "int_nvvm_shfl_sync_idx_f32",
+                llvm_symbol: "llvm.nvvm.shfl.sync.idx.f32",
+            },
+            rust_name: "shuffle_f32_sync",
+            rust_value: "f32",
+            dialect_value: "f32",
+            dialect_op_type: "ShflSyncIdxF32Op",
+            dialect_op_name: "nvvm.shfl_sync_idx_f32",
+            ptx_mode: "idx",
+            clamp: 31,
+            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
+            lowering: "generated_warp_shuffle",
+            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
+        },
+        (WarpShuffleMode::Bfly, WarpShuffleValueKind::F32) => WarpShuffleRecipe {
+            id: "shuffle_xor_f32_sync",
+            abi_id: "i0055",
+            operation_key: "warp.shuffle.sync.bfly.f32",
+            source: WarpShuffleRecipeSource::LlvmImported {
+                source_record: "int_nvvm_shfl_sync_bfly_f32",
+                llvm_symbol: "llvm.nvvm.shfl.sync.bfly.f32",
+            },
+            rust_name: "shuffle_xor_f32_sync",
+            rust_value: "f32",
+            dialect_value: "f32",
+            dialect_op_type: "ShflSyncBflyF32Op",
+            dialect_op_name: "nvvm.shfl_sync_bfly_f32",
+            ptx_mode: "bfly",
+            clamp: 31,
+            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
+            lowering: "generated_warp_shuffle",
+            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
+        },
+        (WarpShuffleMode::Down, WarpShuffleValueKind::F32) => WarpShuffleRecipe {
+            id: "shuffle_down_f32_sync",
+            abi_id: "i0056",
+            operation_key: "warp.shuffle.sync.down.f32",
+            source: WarpShuffleRecipeSource::LlvmImported {
+                source_record: "int_nvvm_shfl_sync_down_f32",
+                llvm_symbol: "llvm.nvvm.shfl.sync.down.f32",
+            },
+            rust_name: "shuffle_down_f32_sync",
+            rust_value: "f32",
+            dialect_value: "f32",
+            dialect_op_type: "ShflSyncDownF32Op",
+            dialect_op_name: "nvvm.shfl_sync_down_f32",
+            ptx_mode: "down",
+            clamp: 31,
+            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
+            lowering: "generated_warp_shuffle",
+            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
+        },
+        (WarpShuffleMode::Up, WarpShuffleValueKind::F32) => WarpShuffleRecipe {
+            id: "shuffle_up_f32_sync",
+            abi_id: "i0057",
+            operation_key: "warp.shuffle.sync.up.f32",
+            source: WarpShuffleRecipeSource::LlvmImported {
+                source_record: "int_nvvm_shfl_sync_up_f32",
+                llvm_symbol: "llvm.nvvm.shfl.sync.up.f32",
+            },
+            rust_name: "shuffle_up_f32_sync",
+            rust_value: "f32",
+            dialect_value: "f32",
+            dialect_op_type: "ShflSyncUpF32Op",
+            dialect_op_name: "nvvm.shfl_sync_up_f32",
+            ptx_mode: "up",
+            clamp: 0,
+            adapter: WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOrImmediate,
+            lowering: "generated_warp_shuffle",
+            backend_mechanism: BackendLoweringMechanism::TypedNvvm,
+        },
+        (WarpShuffleMode::Idx, WarpShuffleValueKind::I64) => WarpShuffleRecipe {
+            id: "shuffle_u64_sync",
+            abi_id: "i0058",
+            operation_key: "warp.shuffle.sync.idx.i64",
+            source: WarpShuffleRecipeSource::PtxNative {
+                instruction: "shfl.sync.idx.b32",
+            },
+            rust_name: "shuffle_u64_sync",
+            rust_value: "u64",
+            dialect_value: "i64",
+            dialect_op_type: "ShflSyncIdxI64Op",
+            dialect_op_name: "nvvm.shfl_sync_idx_i64",
+            ptx_mode: "idx",
+            clamp: 31,
+            adapter:
+                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOnly,
+            lowering: "generated_warp_shuffle_i64_inline_ptx",
+            backend_mechanism: BackendLoweringMechanism::InlinePtx,
+        },
+        (WarpShuffleMode::Bfly, WarpShuffleValueKind::I64) => WarpShuffleRecipe {
+            id: "shuffle_xor_u64_sync",
+            abi_id: "i0059",
+            operation_key: "warp.shuffle.sync.bfly.i64",
+            source: WarpShuffleRecipeSource::PtxNative {
+                instruction: "shfl.sync.bfly.b32",
+            },
+            rust_name: "shuffle_xor_u64_sync",
+            rust_value: "u64",
+            dialect_value: "i64",
+            dialect_op_type: "ShflSyncBflyI64Op",
+            dialect_op_name: "nvvm.shfl_sync_bfly_i64",
+            ptx_mode: "bfly",
+            clamp: 31,
+            adapter:
+                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOnly,
+            lowering: "generated_warp_shuffle_i64_inline_ptx",
+            backend_mechanism: BackendLoweringMechanism::InlinePtx,
+        },
+        (WarpShuffleMode::Down, WarpShuffleValueKind::I64) => WarpShuffleRecipe {
+            id: "shuffle_down_u64_sync",
+            abi_id: "i0060",
+            operation_key: "warp.shuffle.sync.down.i64",
+            source: WarpShuffleRecipeSource::PtxNative {
+                instruction: "shfl.sync.down.b32",
+            },
+            rust_name: "shuffle_down_u64_sync",
+            rust_value: "u64",
+            dialect_value: "i64",
+            dialect_op_type: "ShflSyncDownI64Op",
+            dialect_op_name: "nvvm.shfl_sync_down_i64",
+            ptx_mode: "down",
+            clamp: 31,
+            adapter:
+                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOnly,
+            lowering: "generated_warp_shuffle_i64_inline_ptx",
+            backend_mechanism: BackendLoweringMechanism::InlinePtx,
+        },
+        (WarpShuffleMode::Up, WarpShuffleValueKind::I64) => WarpShuffleRecipe {
+            id: "shuffle_up_u64_sync",
+            abi_id: "i0061",
+            operation_key: "warp.shuffle.sync.up.i64",
+            source: WarpShuffleRecipeSource::PtxNative {
+                instruction: "shfl.sync.up.b32",
+            },
+            rust_name: "shuffle_up_u64_sync",
+            rust_value: "u64",
+            dialect_value: "i64",
+            dialect_op_type: "ShflSyncUpI64Op",
+            dialect_op_name: "nvvm.shfl_sync_up_i64",
+            ptx_mode: "up",
+            clamp: 0,
+            adapter:
+                WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble,
+            operand_encoding: WarpShuffleOperandEncoding::RegisterOnly,
+            lowering: "generated_warp_shuffle_i64_inline_ptx",
+            backend_mechanism: BackendLoweringMechanism::InlinePtx,
+        },
+    }
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/guards.rs b/crates/cuda-intrinsics-gen/src/resolve/guards.rs
new file mode 100644
index 0000000000..9ee475cbf6
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/guards.rs
@@ -0,0 +1,602 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CpAsyncControlOperation, DotProductAdapter,
+    ExecutionControlOperation, IntrinsicBackend, OverlayIntrinsic, Tcgen05CpGroup,
+    Tcgen05MmaBUsage, Tcgen05MmaKind, Tcgen05SourceContract, TmaOperation, WgmmaControlMode,
+};
+use crate::ptx::OperandPattern;
+use anyhow::{Result, ensure};
+use ptx_parse::ParseError;
+use std::collections::{BTreeMap, BTreeSet};
+
+use super::families::*;
+
+pub(super) fn insert_unique(set: &mut BTreeSet<String>, value: &str, kind: &str) -> Result<()> {
+    ensure!(set.insert(value.to_owned()), "duplicate {kind}: {value}");
+    Ok(())
+}
+
+pub(super) fn selection_matches_policy(
+    policy: &OverlayIntrinsic,
+    selection: &crate::model::ImportedSelection,
+) -> Result<bool, ParseError> {
+    if policy.family == "wgmma_control" {
+        let Some(control) = &policy.wgmma_control else {
+            return Ok(false);
+        };
+        let recipe = wgmma_control_recipe(control.mode);
+        let selection_shape_matches = if control.mode == WgmmaControlMode::WaitGroup {
+            selection.asm == "wgmma.wait_group.sync.aligned \t$n;"
+        } else {
+            policy.expected_ptx.matches(&selection.asm)?
+        };
+        return Ok(selection.source_record == recipe.selection_record
+            && selection_shape_matches
+            && selection.predicates == ["Subtarget->getPTXVersion() >= 80", "hasSM90a"]
+            && selection.constraints.is_empty());
+    }
+
+    if policy.family == "tma" {
+        return Ok(selection_matches_tma_policy(policy, selection));
+    }
+    if matches!(
+        policy.family.as_str(),
+        "counted_barrier" | "grid_dependency" | "register_control"
+    ) {
+        let Some(operation) = ExecutionControlOperation::from_catalog_id(&policy.id) else {
+            return Ok(false);
+        };
+        let recipe = execution_control_recipe(operation);
+        return Ok(recipe
+            .selection_records
+            .contains(&selection.source_record.as_str())
+            && selection.asm == recipe.selection_asm
+            && selection.predicates == recipe.selection_predicates
+            && selection.constraints.is_empty());
+    }
+    if policy.family == "tcgen05" {
+        let Some(tcgen05) = &policy.tcgen05 else {
+            return Ok(false);
+        };
+        if let Some(mma) = &tcgen05.mma {
+            let expected = if mma.alias.is_some() {
+                BTreeSet::from([if tcgen05_mma_is_ws(mma.form) {
+                    tcgen05_mma_selection_asm(
+                        mma.form,
+                        Tcgen05MmaKind::F8f6f4,
+                        1,
+                        None,
+                        Some(0),
+                        Some(Tcgen05MmaBUsage::Discard),
+                    )
+                } else {
+                    tcgen05_mma_selection_asm(
+                        mma.form,
+                        Tcgen05MmaKind::F8f6f4,
+                        1,
+                        Some("discard"),
+                        None,
+                        None,
+                    )
+                }])
+            } else {
+                tcgen05_mma_valid_selection_asms(mma.form)
+            };
+            return Ok(expected.contains(&selection.asm)
+                && selection.predicates
+                    == [if selection.asm.contains(".kind::i8.") {
+                        "Subtarget->hasTcgen05MMAI8Kind()"
+                    } else {
+                        "Subtarget->hasTcgen05InstSupport()"
+                    }]
+                && selection.constraints.is_empty());
+        }
+        if tcgen05.source_contract != Tcgen05SourceContract::ExactTablegenSelection {
+            return Ok(false);
+        }
+        if let Some(cp) = tcgen05.cp {
+            let recipe = tcgen05_cp_member_recipe(cp.member);
+            let group = match cp.group {
+                Tcgen05CpGroup::Cg1 => 1,
+                Tcgen05CpGroup::Cg2 => 2,
+            };
+            return Ok(selection.source_record
+                == format!("TCGEN05_CP_{}_cg{group}", recipe.selection_stem)
+                && selection.asm
+                    == format!(
+                        "tcgen05.cp.cta_group::{group}.{} \t[$tmem_addr], $sdesc;",
+                        recipe.ptx_suffix
+                    )
+                && selection.predicates == ["Subtarget->hasTcgen05InstSupport()"]
+                && selection.constraints.is_empty());
+        }
+        let recipe = tcgen05_recipe(tcgen05.operation);
+        return Ok(
+            recipe.selection_record == Some(selection.source_record.as_str())
+                && recipe.selection_asm == Some(selection.asm.as_str())
+                && selection.constraints.is_empty(),
+        );
+    }
+    if policy.family == "sparse_mma" {
+        let Some(last) = policy.expected_ptx.operands.last() else {
+            return Ok(false);
+        };
+        if *last != OperandPattern::Immediate {
+            return Ok(false);
+        }
+        let mut selection_shape = policy.expected_ptx.clone();
+        *selection_shape.operands.last_mut().unwrap() = OperandPattern::RegisterOrImmediate;
+        return Ok(selection_shape.matches(&selection.asm)? && selection.constraints.is_empty());
+    }
+    if policy.family == "sync" {
+        if policy.id == "sync_threads" {
+            return Ok(selection.source_record == "BARRIER_CTA_SYNC_ALIGNED_ALL_i"
+                && selection.asm == "bar.sync \t$i;"
+                && selection.predicates.is_empty()
+                && selection.constraints.is_empty());
+        }
+        let Some(scope) = threadfence_scope_for_id(&policy.id) else {
+            return Ok(false);
+        };
+        let recipe = threadfence_recipe(scope);
+        return Ok(selection.source_record == recipe.selection_record
+            && selection.asm == format!("membar.{};", recipe.ptx_level)
+            && selection.predicates.is_empty()
+            && selection.constraints.is_empty());
+    }
+
+    if policy.family == "vote" {
+        let Some(vote) = &policy.vote else {
+            return Ok(false);
+        };
+        let recipe = vote_recipe(vote.mode);
+        return Ok([recipe.immediate_selection, recipe.register_selection]
+            .contains(&selection.source_record.as_str())
+            && policy.expected_ptx.matches(&selection.asm)?
+            && selection.constraints.address_space.is_none()
+            && selection.constraints.immediate_bindings.is_empty());
+    }
+
+    if policy.family == "warp_match" {
+        let Some(warp_match) = &policy.warp_match else {
+            return Ok(false);
+        };
+        let recipe = warp_match_recipe(warp_match.mode, warp_match.value_width);
+        return Ok(recipe
+            .selections
+            .contains(&selection.source_record.as_str())
+            && policy.expected_ptx.matches(&selection.asm)?
+            && selection.constraints.is_empty());
+    }
+
+    if policy.family == "elect" {
+        return Ok(["INT_ELECT_SYNC_I", "INT_ELECT_SYNC_R"]
+            .contains(&selection.source_record.as_str())
+            && selection.asm == "elect.sync \t$dest|$pred, $mask;"
+            && selection.constraints.is_empty());
+    }
+
+    if policy.family == "warp_barrier" {
+        return Ok(policy.warp_barrier.is_some()
+            && ["INT_BAR_WARP_SYNC_I", "INT_BAR_WARP_SYNC_R"]
+                .contains(&selection.source_record.as_str())
+            && policy.expected_ptx.matches(&selection.asm)?
+            && selection.constraints.is_empty());
+    }
+
+    if policy.family == "warp_shuffle" {
+        let Some(shuffle) = &policy.warp_shuffle else {
+            return Ok(false);
+        };
+        let recipe = warp_shuffle_recipe(shuffle.mode, shuffle.value_kind);
+        return Ok(selection.asm
+            == format!(
+                "shfl.sync.{}.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                recipe.ptx_mode
+            )
+            && selection.constraints.is_empty());
+    }
+
+    if policy.family == "cp_async_copy" {
+        let Some(copy) = &policy.cp_async_copy else {
+            return Ok(false);
+        };
+        let Some(recipe) = cp_async_copy_recipe(copy) else {
+            return Ok(false);
+        };
+        return Ok(recipe
+            .selections
+            .contains(&selection.source_record.as_str())
+            && policy.expected_ptx.matches(&selection.asm)?
+            && selection.constraints.is_empty());
+    }
+
+    if policy.family == "cp_async_control" {
+        let Some(control) = &policy.cp_async_control else {
+            return Ok(false);
+        };
+        let recipe = cp_async_control_recipe(control.operation);
+        let instruction_matches = if control.operation == CpAsyncControlOperation::WaitGroup {
+            selection.asm == "cp.async.wait_group \t$n;"
+        } else {
+            policy.expected_ptx.matches(&selection.asm)?
+        };
+        return Ok(selection.source_record == recipe.selection
+            && instruction_matches
+            && selection.constraints.is_empty());
+    }
+
+    if policy.family == "cp_async_mbarrier" {
+        let Some(bridge) = &policy.cp_async_mbarrier else {
+            return Ok(false);
+        };
+        let recipe = cp_async_mbarrier_recipe(bridge.operation, bridge.state_space);
+        return Ok(selection.source_record == recipe.selection
+            && selection.asm == recipe.selection_asm
+            && selection.constraints.is_empty());
+    }
+
+    if policy.family == "mbarrier_basic" {
+        let Some(mbarrier) = &policy.mbarrier_basic else {
+            return Ok(false);
+        };
+        let recipe = mbarrier_basic_recipe(mbarrier.operation);
+        return Ok(selection.source_record == recipe.selection
+            && policy.expected_ptx.matches(&selection.asm)?
+            && selection.constraints.is_empty());
+    }
+
+    if !policy.expected_ptx.matches(&selection.asm)?
+        || policy
+            .selected_address_space
+            .is_some_and(|address_space| selection.constraints.address_space != Some(address_space))
+    {
+        return Ok(false);
+    }
+
+    let Some(dot_product) = &policy.dot_product else {
+        return Ok(true);
+    };
+    if selection.constraints.address_space.is_some() {
+        return Ok(false);
+    }
+    Ok(match dot_product.adapter {
+        DotProductAdapter::DirectThreeOperands => {
+            selection.constraints.immediate_bindings.is_empty()
+        }
+        DotProductAdapter::InsertLowHalfFalse => {
+            selection.constraints.immediate_bindings.len() == 1
+                && selection.constraints.immediate_bindings[0].argument_index == 2
+                && selection.constraints.immediate_bindings[0].value == 0
+        }
+    })
+}
+
+pub(super) fn selection_matches_tma_policy(
+    policy: &OverlayIntrinsic,
+    selection: &crate::model::ImportedSelection,
+) -> bool {
+    let Some(tma) = &policy.tma else {
+        return false;
+    };
+    let operation = tma.operation;
+    if matches!(
+        operation,
+        TmaOperation::Reduce
+            | TmaOperation::PrefetchTensorMap
+            | TmaOperation::ReplaceBoxDim
+            | TmaOperation::ReplaceElementStride
+            | TmaOperation::ReplaceElementType
+            | TmaOperation::ReplaceFillMode
+            | TmaOperation::ReplaceGlobalAddress
+            | TmaOperation::ReplaceGlobalDim
+            | TmaOperation::ReplaceGlobalStride
+            | TmaOperation::ReplaceInterleaveLayout
+            | TmaOperation::ReplaceRank
+            | TmaOperation::ReplaceSwizzleAtomicity
+            | TmaOperation::ReplaceSwizzleMode
+    ) {
+        return false;
+    }
+    let (source_record, asm) = match operation {
+        TmaOperation::G2sTile1d => (
+            "TMA_G2S_TILE_CG0_1D",
+            "cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0}}], [$mbar];",
+        ),
+        TmaOperation::G2sTile2d => (
+            "TMA_G2S_TILE_CG0_2D",
+            "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar];",
+        ),
+        TmaOperation::G2sTile2dMulticast => (
+            "TMA_G2S_TILE_CG0_2D_MC",
+            "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
+        ),
+        TmaOperation::G2sTile2dMulticastCg2 => (
+            "TMA_G2S_TILE_2D_MC",
+            "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
+        ),
+        TmaOperation::G2sTile3d => (
+            "TMA_G2S_TILE_CG0_3D",
+            "cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2}}], [$mbar];",
+        ),
+        TmaOperation::G2sTile4d => (
+            "TMA_G2S_TILE_CG0_4D",
+            "cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3}}], [$mbar];",
+        ),
+        TmaOperation::G2sTile5d => (
+            "TMA_G2S_TILE_CG0_5D",
+            "cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$mbar];",
+        ),
+        TmaOperation::S2gTile1d => (
+            "TMA_TENSOR_S2G_TILE_1D",
+            "cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [$tmap, {{$d0}}], [$src];",
+        ),
+        TmaOperation::S2gTile2d => (
+            "TMA_TENSOR_S2G_TILE_2D",
+            "cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1}}], [$src];",
+        ),
+        TmaOperation::S2gTile3d => (
+            "TMA_TENSOR_S2G_TILE_3D",
+            "cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2}}], [$src];",
+        ),
+        TmaOperation::S2gTile4d => (
+            "TMA_TENSOR_S2G_TILE_4D",
+            "cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3}}], [$src];",
+        ),
+        TmaOperation::S2gTile5d => (
+            "TMA_TENSOR_S2G_TILE_5D",
+            "cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$src];",
+        ),
+        TmaOperation::CommitGroup => ("CP_ASYNC_BULK_COMMIT_GROUP", "cp.async.bulk.commit_group;"),
+        TmaOperation::WaitGroup => ("CP_ASYNC_BULK_WAIT_GROUP", "cp.async.bulk.wait_group \t$n;"),
+        TmaOperation::WaitGroupRead => (
+            "CP_ASYNC_BULK_WAIT_GROUP_READ",
+            "cp.async.bulk.wait_group.read \t$n;",
+        ),
+        TmaOperation::PrefetchTile1d => (
+            "TMA_TENSOR_PF_TILE_1D",
+            "cp.async.bulk.prefetch.tensor.1d.L2.global.tile [$tmap, {{$d0}}];",
+        ),
+        TmaOperation::PrefetchTile2d => (
+            "TMA_TENSOR_PF_TILE_2D",
+            "cp.async.bulk.prefetch.tensor.2d.L2.global.tile [$tmap, {{$d0, $d1}}];",
+        ),
+        TmaOperation::PrefetchTile3d => (
+            "TMA_TENSOR_PF_TILE_3D",
+            "cp.async.bulk.prefetch.tensor.3d.L2.global.tile [$tmap, {{$d0, $d1, $d2}}];",
+        ),
+        TmaOperation::PrefetchTile4d => (
+            "TMA_TENSOR_PF_TILE_4D",
+            "cp.async.bulk.prefetch.tensor.4d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3}}];",
+        ),
+        TmaOperation::PrefetchTile5d => (
+            "TMA_TENSOR_PF_TILE_5D",
+            "cp.async.bulk.prefetch.tensor.5d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
+        ),
+        TmaOperation::PrefetchTileGather4TwoDimensional => (
+            "TMA_TENSOR_PF_TILE_GATHER4_2D",
+            "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4 [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
+        ),
+        TmaOperation::PrefetchTile1dCacheHint => (
+            "TMA_TENSOR_PF_TILE_1D_CH",
+            "cp.async.bulk.prefetch.tensor.1d.L2.global.tile.L2::cache_hint [$tmap, {{$d0}}], $ch;",
+        ),
+        TmaOperation::PrefetchTile2dCacheHint => (
+            "TMA_TENSOR_PF_TILE_2D_CH",
+            "cp.async.bulk.prefetch.tensor.2d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1}}], $ch;",
+        ),
+        TmaOperation::PrefetchTile3dCacheHint => (
+            "TMA_TENSOR_PF_TILE_3D_CH",
+            "cp.async.bulk.prefetch.tensor.3d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2}}], $ch;",
+        ),
+        TmaOperation::PrefetchTile4dCacheHint => (
+            "TMA_TENSOR_PF_TILE_4D_CH",
+            "cp.async.bulk.prefetch.tensor.4d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3}}], $ch;",
+        ),
+        TmaOperation::PrefetchTile5dCacheHint => (
+            "TMA_TENSOR_PF_TILE_5D_CH",
+            "cp.async.bulk.prefetch.tensor.5d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
+        ),
+        TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint => (
+            "TMA_TENSOR_PF_TILE_GATHER4_2D_CH",
+            "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
+        ),
+        TmaOperation::FenceProxyTensorMapAcquireCluster => (
+            "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CLUSTER",
+            "fence.proxy.tensormap::generic.acquire.cluster [$addr], 128;",
+        ),
+        TmaOperation::FenceProxyTensorMapAcquireCta => (
+            "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CTA",
+            "fence.proxy.tensormap::generic.acquire.cta [$addr], 128;",
+        ),
+        TmaOperation::FenceProxyTensorMapAcquireGpu => (
+            "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_GPU",
+            "fence.proxy.tensormap::generic.acquire.gpu [$addr], 128;",
+        ),
+        TmaOperation::FenceProxyTensorMapAcquireSystem => (
+            "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_SYS",
+            "fence.proxy.tensormap::generic.acquire.sys [$addr], 128;",
+        ),
+        TmaOperation::FenceProxyTensorMapReleaseCluster => (
+            "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CLUSTER",
+            "fence.proxy.tensormap::generic.release.cluster;",
+        ),
+        TmaOperation::FenceProxyTensorMapReleaseCta => (
+            "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CTA",
+            "fence.proxy.tensormap::generic.release.cta;",
+        ),
+        TmaOperation::FenceProxyTensorMapReleaseGpu => (
+            "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_GPU",
+            "fence.proxy.tensormap::generic.release.gpu;",
+        ),
+        TmaOperation::FenceProxyTensorMapReleaseSystem => (
+            "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_SYS",
+            "fence.proxy.tensormap::generic.release.sys;",
+        ),
+        TmaOperation::Reduce
+        | TmaOperation::PrefetchTensorMap
+        | TmaOperation::ReplaceBoxDim
+        | TmaOperation::ReplaceElementStride
+        | TmaOperation::ReplaceElementType
+        | TmaOperation::ReplaceFillMode
+        | TmaOperation::ReplaceGlobalAddress
+        | TmaOperation::ReplaceGlobalDim
+        | TmaOperation::ReplaceGlobalStride
+        | TmaOperation::ReplaceInterleaveLayout
+        | TmaOperation::ReplaceRank
+        | TmaOperation::ReplaceSwizzleAtomicity
+        | TmaOperation::ReplaceSwizzleMode => unreachable!("selectionless TMA operation"),
+    };
+
+    let mut immediate_bindings = Vec::new();
+    if matches!(
+        operation,
+        TmaOperation::G2sTile1d
+            | TmaOperation::G2sTile2d
+            | TmaOperation::G2sTile2dMulticast
+            | TmaOperation::G2sTile2dMulticastCg2
+            | TmaOperation::G2sTile3d
+            | TmaOperation::G2sTile4d
+            | TmaOperation::G2sTile5d
+    ) {
+        let dimensions = operation.dimensions().unwrap();
+        immediate_bindings.push(crate::model::ImportedImmediateBinding {
+            argument_index: dimensions + 5,
+            value: if matches!(
+                operation,
+                TmaOperation::G2sTile2dMulticast | TmaOperation::G2sTile2dMulticastCg2
+            ) {
+                -1
+            } else {
+                0
+            },
+        });
+        immediate_bindings.push(crate::model::ImportedImmediateBinding {
+            argument_index: dimensions + 6,
+            value: 0,
+        });
+    } else if matches!(
+        operation,
+        TmaOperation::S2gTile1d
+            | TmaOperation::S2gTile2d
+            | TmaOperation::S2gTile3d
+            | TmaOperation::S2gTile4d
+            | TmaOperation::S2gTile5d
+    ) {
+        immediate_bindings.push(crate::model::ImportedImmediateBinding {
+            argument_index: operation.dimensions().unwrap() + 3,
+            value: 0,
+        });
+    } else if let Some(coordinate_count) = operation.prefetch_coordinate_count() {
+        immediate_bindings.push(crate::model::ImportedImmediateBinding {
+            argument_index: coordinate_count + 2,
+            value: if operation.uses_prefetch_cache_hint() {
+                -1
+            } else {
+                0
+            },
+        });
+    }
+
+    selection.source_record == source_record
+        && selection.asm == asm
+        && selection.constraints
+            == crate::model::ImportedSelectionConstraints {
+                address_space: None,
+                immediate_bindings,
+            }
+}
+
+pub(super) fn ensure_exact_inline_ptx_backends(
+    policy: &OverlayIntrinsic,
+    requirements: [(IntrinsicBackend, &str, Option<&str>); 2],
+    family: &str,
+) -> Result<()> {
+    let backend_pairs: BTreeSet<_> = policy
+        .backend_lowerings
+        .iter()
+        .map(|lowering| (lowering.backend, lowering.mechanism))
+        .collect();
+    ensure!(
+        policy.backend_lowerings.len() == 2
+            && backend_pairs
+                == BTreeSet::from([
+                    (
+                        IntrinsicBackend::LlvmNvptx,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                    (
+                        IntrinsicBackend::LibNvvm,
+                        BackendLoweringMechanism::InlinePtx,
+                    ),
+                ]),
+        "{} must define exactly two reviewed {family} inline-PTX routes",
+        policy.id
+    );
+    let requirements: BTreeMap<_, _> = requirements
+        .into_iter()
+        .map(|(backend, ptx, minimum_sm)| (backend, (ptx, minimum_sm)))
+        .collect();
+    for lowering in &policy.backend_lowerings {
+        let (minimum_ptx, minimum_sm) = requirements[&lowering.backend];
+        ensure!(
+            lowering.minimum_ptx.as_deref() == Some(minimum_ptx)
+                && lowering.minimum_sm.as_deref() == minimum_sm
+                && !lowering.evidence_profile.trim().is_empty(),
+            "{} backend {:?} does not carry its exact {family} floor",
+            policy.id,
+            lowering.backend
+        );
+    }
+    Ok(())
+}
+
+pub(super) fn ensure_no_other_family_contract(
+    policy: &OverlayIntrinsic,
+    family: &str,
+) -> Result<()> {
+    ensure!(
+        policy.packed_atomic.is_none()
+            && policy.redux.is_none()
+            && policy.vote.is_none()
+            && policy.active_mask.is_none()
+            && policy.warp_match.is_none()
+            && policy.warp_barrier.is_none()
+            && policy.warp_shuffle.is_none()
+            && policy.dot_product.is_none()
+            && policy.ldmatrix_variant.is_none()
+            && policy.ldmatrix_safety.is_none()
+            && policy.ldmatrix_adapter.is_none()
+            && (policy.family == "tma" || policy.selected_address_space.is_none())
+            && (policy.family == "packed_alu") == policy.packed_alu.is_some()
+            && (policy.family == "integer_minmax") == policy.integer_minmax.is_some()
+            && (policy.family == "packed_conversion") == policy.packed_conversion.is_some()
+            && (policy.family == "scalar_conversion") == policy.scalar_conversion.is_some()
+            && (policy.family == "scalar_arithmetic") == policy.scalar_arithmetic.is_some()
+            && (policy.family == "scalar_math") == policy.scalar_math.is_some()
+            && (policy.family == "extended_minmax") == policy.extended_minmax.is_some()
+            && (policy.family == "cp_async_copy") == policy.cp_async_copy.is_some()
+            && (policy.family == "cp_async_control") == policy.cp_async_control.is_some()
+            && (policy.family == "cp_async_mbarrier") == policy.cp_async_mbarrier.is_some()
+            && (policy.family == "mbarrier_basic") == policy.mbarrier_basic.is_some()
+            && (policy.family == "movmatrix") == policy.movmatrix.is_some()
+            && (policy.family == "mbarrier_extended") == policy.mbarrier_extended.is_some()
+            && (policy.family == "register_mma") == policy.register_mma.is_some()
+            && (policy.family == "sparse_mma") == policy.sparse_mma.is_some()
+            && (policy.family == "prmt") == policy.prmt.is_some()
+            && (policy.family == "cluster_barrier") == policy.cluster_barrier.is_some()
+            && (policy.family == "wgmma_control") == policy.wgmma_control.is_some()
+            && (policy.family == "debug_control") == policy.debug_control.is_some()
+            && (policy.family == "cluster_memory") == policy.cluster_memory.is_some()
+            && (policy.family == "clc") == policy.clc.is_some()
+            && (policy.family == "tma") == policy.tma.is_some()
+            && (policy.family == "tcgen05") == policy.tcgen05.is_some(),
+        "{} mixes another generated-family contract with {family}",
+        policy.id
+    );
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/materialize.rs b/crates/cuda-intrinsics-gen/src/resolve/materialize.rs
new file mode 100644
index 0000000000..2a5af0aa82
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/materialize.rs
@@ -0,0 +1,490 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    CatalogBackend, CatalogBackendLowering, CatalogDialect, CatalogHalfOpenRange, CatalogIntrinsic,
+    CatalogLdmatrix, CatalogLlvm, CatalogLlvmResultFacts, CatalogRust, CatalogSelection,
+    CatalogSemantics, CatalogTarget, CatalogTargetRequirement, EvidenceRecord,
+    ExecutionControlOperation, ImportedIntrinsic, IntrinsicSource, OverlayIntrinsic,
+    RuntimeValidation,
+};
+use anyhow::{Context, Result, ensure};
+use std::collections::BTreeMap;
+
+use super::abi_ledger::*;
+use super::evidence::*;
+use super::guards::*;
+use super::targets::*;
+
+pub(super) fn resolve_backend_lowerings(
+    policy: &OverlayIntrinsic,
+    evidence_by_profile_id: &BTreeMap<(&str, &str), IndexedEvidence<'_>>,
+) -> Result<Vec<CatalogBackendLowering>> {
+    let mut resolved = Vec::with_capacity(policy.backend_lowerings.len());
+    let mut runtime_states = Vec::with_capacity(policy.backend_lowerings.len());
+    for lowering in &policy.backend_lowerings {
+        let evidence = evidence_by_profile_id
+            .get(&(lowering.evidence_profile.as_str(), policy.id.as_str()))
+            .with_context(|| {
+                format!(
+                    "{} has no evidence in backend profile {}",
+                    policy.id, lowering.evidence_profile
+                )
+            })?;
+        validate_evidence(policy, evidence, Some(lowering))?;
+        runtime_states.push(evidence.record.runtime_validation);
+        resolved.push(CatalogBackendLowering {
+            backend: lowering.backend,
+            mechanism: lowering.mechanism,
+            evidence_profile: lowering.evidence_profile.clone(),
+            target: backend_target_requirement(policy, lowering)?,
+            version: evidence.backend_version.to_owned(),
+            sha256: evidence.backend_sha256.to_owned(),
+            artifact_path: evidence.file.artifact_path.clone(),
+            build_id_prefix: evidence.file.build_id_prefix.clone(),
+            status: evidence.record.status.clone(),
+            stages: evidence.record.stages.clone(),
+        });
+    }
+    if let Some(safety) = &policy.ldmatrix_safety {
+        match safety.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} overlay says runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} overlay says runtime is executed but no backend evidence has an executed runtime stage",
+                policy.id
+            ),
+        }
+    }
+    if policy.family == "stmatrix" {
+        ensure!(
+            runtime_states
+                .iter()
+                .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+            "{} stmatrix source contract is unexecuted but backend evidence disagrees",
+            policy.id
+        );
+    }
+    if let Some(packed) = &policy.packed_atomic {
+        match packed.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} packed-atomic runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} packed-atomic runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(mbarrier) = &policy.mbarrier_basic {
+        match mbarrier.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} mbarrier runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} mbarrier runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(movmatrix) = &policy.movmatrix {
+        match movmatrix.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} movmatrix runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} movmatrix runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(mbarrier) = &policy.mbarrier_extended {
+        match mbarrier.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} extended-mbarrier runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} extended-mbarrier runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(bridge) = &policy.cp_async_mbarrier {
+        match bridge.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} cp.async mbarrier runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} cp.async mbarrier runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(mma) = &policy.register_mma {
+        match mma.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} register-MMA runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} register-MMA runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(mma) = &policy.sparse_mma {
+        match mma.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} sparse-MMA runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} sparse-MMA runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(debug) = &policy.debug_control {
+        match debug.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} debug-control runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} debug-control runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(cluster_memory) = &policy.cluster_memory {
+        match cluster_memory.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} cluster-memory runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} cluster-memory runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(clc) = &policy.clc {
+        match clc.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} CLC runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} CLC runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(conversion) = &policy.scalar_conversion {
+        match conversion.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} scalar-conversion runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} scalar-conversion runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    if let Some(arithmetic) = &policy.scalar_arithmetic {
+        match arithmetic.runtime_validation {
+            RuntimeValidation::Unexecuted => ensure!(
+                runtime_states
+                    .iter()
+                    .all(|state| *state == Some(RuntimeValidation::Unexecuted)),
+                "{} scalar-arithmetic runtime is unexecuted but backend evidence disagrees",
+                policy.id
+            ),
+            RuntimeValidation::Executed => ensure!(
+                runtime_states.contains(&Some(RuntimeValidation::Executed)),
+                "{} scalar-arithmetic runtime is executed but no backend evidence records execution",
+                policy.id
+            ),
+        }
+    }
+    resolved.sort_by_key(|lowering| lowering.backend);
+    Ok(resolved)
+}
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn resolve_record(
+    policy: &OverlayIntrinsic,
+    source: IntrinsicSource,
+    declaration: Option<&ImportedIntrinsic>,
+    evidence: &EvidenceRecord,
+    backend_profile: &str,
+    backend_version: &str,
+    backend_sha256: &str,
+    backend_lowerings: Vec<CatalogBackendLowering>,
+    intrinsic_abi: u32,
+) -> Result<CatalogIntrinsic> {
+    materialize_record(
+        policy,
+        source,
+        declaration,
+        CatalogBackend {
+            profile: backend_profile.to_owned(),
+            version: backend_version.to_owned(),
+            sha256: backend_sha256.to_owned(),
+            status: evidence.status.clone(),
+            target_triple: evidence.target_triple.clone(),
+            gpu_target: evidence.gpu_target.clone(),
+            ptx_feature: evidence.ptx_feature.clone(),
+        },
+        backend_lowerings,
+        intrinsic_abi,
+    )
+}
+
+pub(super) fn materialize_record(
+    policy: &OverlayIntrinsic,
+    source: IntrinsicSource,
+    declaration: Option<&ImportedIntrinsic>,
+    backend: CatalogBackend,
+    backend_lowerings: Vec<CatalogBackendLowering>,
+    intrinsic_abi: u32,
+) -> Result<CatalogIntrinsic> {
+    let native_target = if let Some(mma) = policy
+        .tcgen05
+        .as_ref()
+        .and_then(|tcgen05| tcgen05.mma.as_ref())
+    {
+        mma.llvm_target.clone()
+    } else {
+        CatalogTargetRequirement {
+            minimum_ptx: parse_ptx_version(&policy.minimum_ptx, &policy.id)?,
+            hardware: parse_hardware_target(policy)?,
+        }
+    };
+    let llvm = if let Some(declaration) = declaration {
+        Some(CatalogLlvm {
+            symbol: policy
+                .llvm_symbol
+                .clone()
+                .expect("validated imported LLVM symbol"),
+            resolved_symbol: policy.resolved_llvm_symbol.clone(),
+            arguments: policy.llvm_arguments.clone(),
+            results: policy.llvm_results.clone(),
+            properties: declaration.properties.clone(),
+            result_facts: imported_result_facts(&declaration.properties)?,
+        })
+    } else {
+        None
+    };
+    let preserves_empty_dialect_signature = (policy.family == "sync"
+        && policy.id == "sync_threads")
+        || matches!(
+            ExecutionControlOperation::from_catalog_id(&policy.id),
+            Some(
+                ExecutionControlOperation::SetMaxNRegInc | ExecutionControlOperation::SetMaxNRegDec
+            )
+        );
+    let dialect_operands =
+        if policy.dialect_operands.is_empty() && !preserves_empty_dialect_signature {
+            policy.llvm_arguments.clone()
+        } else {
+            policy.dialect_operands.clone()
+        };
+    let dialect_results = if policy.dialect_results.is_empty() && !preserves_empty_dialect_signature
+    {
+        policy.llvm_results.clone()
+    } else {
+        policy.dialect_results.clone()
+    };
+    let mut selections = Vec::new();
+    for selection in declaration
+        .into_iter()
+        .flat_map(|declaration| declaration.selections.iter())
+    {
+        if selection_matches_policy(policy, selection)? {
+            selections.push(CatalogSelection {
+                source_record: selection.source_record.clone(),
+                asm: selection.asm.clone(),
+                predicates: selection.predicates.clone(),
+                constraints: selection.constraints.clone(),
+            });
+        }
+    }
+    Ok(CatalogIntrinsic {
+        id: policy.id.clone(),
+        operation_key: policy.operation_key.clone(),
+        family: policy.family.clone(),
+        source,
+        selections,
+        rust: CatalogRust {
+            abi_id: policy.abi_id.clone(),
+            module: policy.rust_module.clone(),
+            name: policy.rust_name.clone(),
+            arguments: policy.rust_arguments.clone(),
+            result: policy.rust_result.clone(),
+            safe: policy.safe,
+            must_use: policy.must_use,
+            safe_allowlist_reason: policy.safe_allowlist_reason.clone(),
+            canonical_path: canonical_rust_path(intrinsic_abi, &policy.abi_id),
+            public_path: policy.public_rust_path.clone(),
+            compatibility_paths: policy.compatibility_rust_paths.clone(),
+        },
+        dialect: CatalogDialect {
+            op_type: policy.dialect_op_type.clone(),
+            op_name: policy.dialect_op_name.clone(),
+            operands: dialect_operands,
+            results: dialect_results,
+        },
+        llvm,
+        semantics: CatalogSemantics {
+            pure: policy.pure,
+            memory: policy.memory.clone(),
+            convergent: policy.convergent,
+            execution_scope: policy.execution_scope.clone(),
+        },
+        target: CatalogTarget {
+            minimum_ptx: native_target.minimum_ptx,
+            hardware: native_target.hardware,
+            ptx_result: policy.ptx_result.clone(),
+            targets: policy.targets.clone(),
+            ptx_isa_version: policy.ptx_isa_version.clone(),
+            ptx_isa_section: policy.ptx_isa_section.clone(),
+            ptx_isa_url: policy.ptx_isa_url.clone(),
+        },
+        backend,
+        backend_lowerings,
+        packed_atomic: policy.packed_atomic.clone(),
+        redux: policy.redux.clone(),
+        vote: policy.vote.clone(),
+        active_mask: policy.active_mask.clone(),
+        warp_match: policy.warp_match.clone(),
+        warp_barrier: policy.warp_barrier.clone(),
+        warp_shuffle: policy.warp_shuffle.clone(),
+        dot_product: policy.dot_product.clone(),
+        packed_alu: policy.packed_alu.clone(),
+        integer_minmax: policy.integer_minmax.clone(),
+        packed_conversion: policy.packed_conversion.clone(),
+        scalar_conversion: policy.scalar_conversion.clone(),
+        scalar_arithmetic: policy.scalar_arithmetic.clone(),
+        scalar_math: policy.scalar_math.clone(),
+        extended_minmax: policy.extended_minmax.clone(),
+        cp_async_copy: policy.cp_async_copy.clone(),
+        cp_async_control: policy.cp_async_control.clone(),
+        cp_async_mbarrier: policy.cp_async_mbarrier.clone(),
+        mbarrier_basic: policy.mbarrier_basic.clone(),
+        movmatrix: policy.movmatrix.clone(),
+        mbarrier_extended: policy.mbarrier_extended.clone(),
+        register_mma: policy.register_mma.clone(),
+        sparse_mma: policy.sparse_mma.clone(),
+        prmt: policy.prmt.clone(),
+        cluster_barrier: policy.cluster_barrier.clone(),
+        wgmma_control: policy.wgmma_control.clone(),
+        special_register: policy.special_register.clone(),
+        debug_control: policy.debug_control.clone(),
+        cluster_memory: policy.cluster_memory.clone(),
+        clc: policy.clc.clone(),
+        tma: policy.tma.clone(),
+        tcgen05: policy.tcgen05.clone(),
+        ldmatrix: policy
+            .ldmatrix_variant
+            .clone()
+            .map(|variant| CatalogLdmatrix {
+                variant,
+                safety: policy
+                    .ldmatrix_safety
+                    .clone()
+                    .expect("validated ldmatrix safety"),
+                adapter: policy.ldmatrix_adapter.expect("validated ldmatrix adapter"),
+                selected_address_space: policy
+                    .selected_address_space
+                    .expect("validated ldmatrix address space"),
+            }),
+        lowering: policy.lowering.clone(),
+        expected_ptx: policy.expected_ptx.clone(),
+        summary: policy.summary.clone(),
+    })
+}
+
+pub(super) fn imported_result_facts(properties: &[String]) -> Result<CatalogLlvmResultFacts> {
+    let no_undef = properties.iter().any(|property| property == "NoUndef<ret>");
+    let mut range = None;
+    for property in properties {
+        let Some(bounds) = property
+            .strip_prefix("Range<ret,")
+            .and_then(|value| value.strip_suffix('>'))
+        else {
+            continue;
+        };
+        let (lower, upper_exclusive) = bounds
+            .split_once(',')
+            .with_context(|| format!("malformed return range property {property:?}"))?;
+        ensure!(
+            !lower.is_empty() && !upper_exclusive.is_empty(),
+            "malformed return range property {property:?}"
+        );
+        ensure!(range.is_none(), "duplicate return range properties");
+        range = Some(CatalogHalfOpenRange {
+            lower: lower.to_owned(),
+            upper_exclusive: upper_exclusive.to_owned(),
+        });
+    }
+    Ok(CatalogLlvmResultFacts { no_undef, range })
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/mod.rs b/crates/cuda-intrinsics-gen/src/resolve/mod.rs
new file mode 100644
index 0000000000..d35455dfa5
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/mod.rs
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+mod abi_ledger;
+mod driver;
+mod evidence;
+mod families;
+mod guards;
+mod materialize;
+mod overlay;
+mod policy;
+mod targets;
+#[cfg(test)]
+mod tests;
+
+pub(crate) use abi_ledger::validate_operation_key;
+pub use driver::resolve;
+pub(crate) use driver::resolve_candidate;
+// The remaining pre-split surface: nothing outside `resolve` names these
+// today, so the re-exports would otherwise trip `unused_imports`.
+#[allow(unused_imports)]
+pub(crate) use driver::CandidateResolution;
+#[cfg(test)]
+pub(crate) use driver::{test_catalog_with_clc, test_catalog_with_tcgen05, test_catalog_with_tma};
+pub(crate) use families::cluster::cluster_memory_inline_recipe;
+pub(crate) use families::mbarrier_extended::mbarrier_extended_inline_recipe;
+#[cfg(test)]
+pub(crate) use overlay::CATALOG_SCHEMA;
+#[allow(unused_imports)]
+pub(crate) use targets::{resolve_target_contract, resolve_target_contracts};
diff --git a/crates/cuda-intrinsics-gen/src/resolve/overlay.rs b/crates/cuda-intrinsics-gen/src/resolve/overlay.rs
new file mode 100644
index 0000000000..88d9f637c7
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/overlay.rs
@@ -0,0 +1,858 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    OverlayFile, OverlayIntrinsic, OverlayShardFile, RegisterMmaAccumulator, Tcgen05Operation,
+    TmaOperation,
+};
+use crate::util::sha256_bytes;
+use anyhow::{Context, Result, ensure};
+use std::collections::{BTreeMap, BTreeSet};
+use std::fs;
+use std::path::{Component, Path};
+
+use super::abi_ledger::*;
+use super::families::*;
+use super::guards::*;
+
+pub(super) const OVERLAY_SCHEMA: u32 = 44;
+pub(super) const MINIMUM_OVERLAY_SHARD_SCHEMA: u32 = 26;
+pub(super) const OVERLAY_SHARD_SCHEMA: u32 = 62;
+pub(super) const REGISTER_MMA_F8F6F4_SHARD_SCHEMA: u32 = 46;
+pub(super) const REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA: u32 = 47;
+pub(super) const REGISTER_MMA_MXF8F6F4_SHARD_SCHEMA: u32 = 60;
+pub(super) const REGISTER_MMA_FP8_SHARD_SCHEMA: u32 = 48;
+pub(super) const REGISTER_MMA_AMPERE_FLOAT_SHARD_SCHEMA: u32 = 49;
+pub(super) const SPARSE_MMA_F8F6F4_SHARD_SCHEMA: u32 = 27;
+pub(super) const SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA: u32 = 50;
+pub(super) const PRMT_SHARD_SCHEMA: u32 = 28;
+pub(super) const PACKED_CONVERSION_FP8_SHARD_SCHEMA: u32 = 29;
+pub(super) const PACKED_CONVERSION_FP8_F16X2_SHARD_SCHEMA: u32 = 59;
+pub(super) const CLUSTER_SREG_SHARD_SCHEMA: u32 = 30;
+pub(super) const CLUSTER_BARRIER_SHARD_SCHEMA: u32 = 31;
+pub(super) const SPECIAL_REGISTER_SHARD_SCHEMA: u32 = 32;
+pub(super) const DEBUG_CONTROL_SHARD_SCHEMA: u32 = 33;
+pub(super) const THREADFENCE_SHARD_SCHEMA: u32 = 34;
+pub(super) const STMATRIX_SHARD_SCHEMA: u32 = 35;
+pub(super) const CLUSTER_MEMORY_SHARD_SCHEMA: u32 = 39;
+pub(super) const CLC_SHARD_SCHEMA: u32 = 40;
+pub(super) const TMA_SHARD_SCHEMA: u32 = 61;
+pub(super) const TMA_REDUCTION_SHARD_SCHEMA: u32 = 62;
+pub(super) const MBARRIER_EXTENDED_SHARD_SCHEMA: u32 = 40;
+pub(super) const WGMMA_CONTROL_SHARD_SCHEMA: u32 = 38;
+pub(super) const TCGEN05_SHARD_SCHEMA: u32 = 42;
+pub(super) const SCALAR_CONVERSION_SHARD_SCHEMA: u32 = 43;
+pub(super) const SCALAR_ARITHMETIC_SHARD_SCHEMA: u32 = 45;
+pub(super) const EXTENDED_MINMAX_SHARD_SCHEMA: u32 = 60;
+pub(super) const TCGEN05_CP_SHARD_SCHEMA: u32 = 52;
+pub(super) const TCGEN05_LD_SHARD_SCHEMA: u32 = 53;
+pub(super) const TCGEN05_ST_SHARD_SCHEMA: u32 = 54;
+pub(super) const TCGEN05_OFFSET_LDST_SHARD_SCHEMA: u32 = 55;
+pub(super) const TCGEN05_CONTROL_SHARD_SCHEMA: u32 = 56;
+pub(super) const TCGEN05_MMA_SHARD_SCHEMA: u32 = 57;
+pub(super) const SCALAR_MATH_SHARD_SCHEMA: u32 = 58;
+pub(crate) const CATALOG_SCHEMA: u32 = 46;
+pub(super) fn read_overlay(
+    repo_root: &Path,
+    manifest_path: &Path,
+) -> Result<(OverlayFile, String)> {
+    let manifest_bytes =
+        fs::read(manifest_path).with_context(|| format!("read {}", manifest_path.display()))?;
+    let mut overlay: OverlayFile = toml::from_slice(&manifest_bytes)
+        .with_context(|| format!("parse {}", manifest_path.display()))?;
+
+    ensure!(
+        overlay.intrinsics.is_empty(),
+        "overlay.toml must list family shards instead of inline intrinsic records"
+    );
+    ensure!(
+        !overlay.shards.is_empty(),
+        "overlay.toml must list at least one family shard"
+    );
+
+    let mut previous = None;
+    let mut seen = BTreeSet::new();
+    let mut hash_input = Vec::new();
+    append_overlay_hash_input(&mut hash_input, "intrinsics/overlay.toml", &manifest_bytes);
+
+    for shard_name in &overlay.shards {
+        validate_overlay_shard_path(shard_name)?;
+        ensure!(
+            seen.insert(shard_name.as_str()),
+            "overlay.toml lists duplicate shard {shard_name}"
+        );
+        if let Some(previous) = previous {
+            ensure!(
+                previous < shard_name.as_str(),
+                "overlay.toml shards must be sorted"
+            );
+        }
+        previous = Some(shard_name.as_str());
+
+        let relative = Path::new("intrinsics").join(shard_name);
+        let path = repo_root.join(&relative);
+        let bytes = fs::read(&path).with_context(|| format!("read {}", path.display()))?;
+        let mut shard: OverlayShardFile =
+            toml::from_slice(&bytes).with_context(|| format!("parse {}", path.display()))?;
+        validate_overlay_shard_schema(&shard, &path)?;
+        let int4_mma_admission = shard.register_mma_int4.take();
+        let int8_mma_admission = shard.register_mma_int8.take();
+        let binary_mma_admission = shard.register_mma_b1.take();
+        let f8f6f4_f32_mma_admission = shard.register_mma_f8f6f4_f32.take();
+        let f8f6f4_f16_mma_admission = shard.register_mma_f8f6f4_f16.take();
+        let mxf8f6f4_f32_mma_admission = shard.register_mma_mxf8f6f4_f32.take();
+        let fp8_mma_admission = shard.register_mma_fp8.take();
+        let ampere_float_mma_admission = shard.register_mma_ampere_float.take();
+        let sparse_mma_admission = shard.sparse_mma_integer.take();
+        let sparse_mma_f8f6f4_admission = shard.sparse_mma_f8f6f4_f32.take();
+        let sparse_mma_f8f6f4_f16_admission = shard.sparse_mma_f8f6f4_f16.take();
+        let prmt_admission = shard.prmt.take();
+        let packed_conversion_fp8_admission = shard.packed_conversion_fp8.take();
+        let packed_conversion_fp8_f16x2_admission = shard.packed_conversion_fp8_f16x2.take();
+        let scalar_conversion_admission = shard.scalar_conversion.take();
+        let scalar_arithmetic_admission = shard.scalar_arithmetic.take();
+        let scalar_math_admission = shard.scalar_math.take();
+        let extended_minmax_admission = shard.extended_minmax.take();
+        let cluster_sreg_admission = shard.cluster_sreg.take();
+        let cluster_barrier_admission = shard.cluster_barrier.take();
+        let mbarrier_extended_admission = shard.mbarrier_extended.take();
+        let special_register_admission = shard.special_registers.take();
+        let debug_control_admission = shard.debug_control.take();
+        let threadfence_admission = shard.threadfence.take();
+        let cluster_memory_admission = shard.cluster_memory.take();
+        let stmatrix_admission = shard.stmatrix.take();
+        let clc_admission = shard.clc.take();
+        let wgmma_control_admission = shard.wgmma_controls.take();
+        let tma_admission = shard.tma.take();
+        let tcgen05_admission = shard.tcgen05.take();
+        let compact_mma_count = usize::from(int4_mma_admission.is_some())
+            + usize::from(int8_mma_admission.is_some())
+            + usize::from(binary_mma_admission.is_some())
+            + usize::from(f8f6f4_f32_mma_admission.is_some())
+            + usize::from(f8f6f4_f16_mma_admission.is_some())
+            + usize::from(mxf8f6f4_f32_mma_admission.is_some())
+            + usize::from(fp8_mma_admission.is_some())
+            + usize::from(ampere_float_mma_admission.is_some())
+            + usize::from(sparse_mma_admission.is_some())
+            + usize::from(sparse_mma_f8f6f4_admission.is_some())
+            + usize::from(sparse_mma_f8f6f4_f16_admission.is_some());
+        ensure!(
+            compact_mma_count <= 1,
+            "overlay shard {} contains more than one compact MMA admission",
+            path.display()
+        );
+        let integer_mma_admission = int4_mma_admission
+            .map(|admission| (RegisterMmaIntegerKind::Int4, admission))
+            .or_else(|| {
+                int8_mma_admission.map(|admission| (RegisterMmaIntegerKind::Int8, admission))
+            });
+        if let Some((kind, admission)) = integer_mma_admission {
+            ensure!(
+                shard.family == "register_mma" && shard.intrinsics.is_empty(),
+                "compact integer MMA admission must be the only content of a register_mma shard"
+            );
+            shard.intrinsics = expand_register_mma_integer_admission(kind, &admission)?;
+        }
+        if let Some(admission) = binary_mma_admission {
+            ensure!(
+                shard.family == "register_mma" && shard.intrinsics.is_empty(),
+                "compact binary MMA admission must be the only content of a register_mma shard"
+            );
+            shard.intrinsics = expand_register_mma_binary_admission(&admission)?;
+        }
+        if let Some(admission) = f8f6f4_f32_mma_admission {
+            ensure!(
+                shard.family == "register_mma" && shard.intrinsics.is_empty(),
+                "compact dense f8f6f4 MMA admission must be the only content of a register_mma shard"
+            );
+            shard.intrinsics =
+                expand_register_mma_f8f6f4_admission(&admission, RegisterMmaAccumulator::F32)?;
+        }
+        if let Some(admission) = f8f6f4_f16_mma_admission {
+            ensure!(
+                shard.family == "register_mma" && shard.intrinsics.is_empty(),
+                "compact dense f8f6f4 MMA admission must be the only content of a register_mma shard"
+            );
+            shard.intrinsics =
+                expand_register_mma_f8f6f4_admission(&admission, RegisterMmaAccumulator::F16)?;
+        }
+        if let Some(admission) = mxf8f6f4_f32_mma_admission {
+            ensure!(
+                shard.family == "register_mma" && shard.intrinsics.is_empty(),
+                "compact dense mxf8f6f4 MMA admission must be the only content of a register_mma shard"
+            );
+            shard.intrinsics = expand_register_mma_mxf8f6f4_admission(&admission)?;
+        }
+        if let Some(admission) = fp8_mma_admission {
+            ensure!(
+                shard.family == "register_mma" && shard.intrinsics.is_empty(),
+                "compact standard FP8 MMA admission must be the only content of a register_mma shard"
+            );
+            shard.intrinsics = expand_register_mma_fp8_admission(&admission)?;
+        }
+        if let Some(admission) = ampere_float_mma_admission {
+            ensure!(
+                shard.family == "register_mma" && shard.intrinsics.is_empty(),
+                "compact Ampere floating-point MMA admission must be the only content of a register_mma shard"
+            );
+            shard.intrinsics = expand_register_mma_ampere_float_admission(&admission)?;
+        }
+        if let Some(admission) = sparse_mma_admission {
+            ensure!(
+                shard.family == "sparse_mma" && shard.intrinsics.is_empty(),
+                "compact sparse MMA admission must be the only content of a sparse_mma shard"
+            );
+            shard.intrinsics = expand_sparse_mma_integer_admission(&admission)?;
+        }
+        if let Some(admission) = sparse_mma_f8f6f4_admission {
+            ensure!(
+                shard.family == "sparse_mma" && shard.intrinsics.is_empty(),
+                "compact sparse f8f6f4 MMA admission must be the only content of a sparse_mma shard"
+            );
+            shard.intrinsics = expand_sparse_mma_f8f6f4_admission(&admission)?;
+        }
+        if let Some(admission) = sparse_mma_f8f6f4_f16_admission {
+            ensure!(
+                shard.family == "sparse_mma" && shard.intrinsics.is_empty(),
+                "compact sparse f8f6f4 F16 MMA admission must be the only content of a sparse_mma shard"
+            );
+            shard.intrinsics = expand_sparse_mma_f8f6f4_f16_admission(&admission)?;
+        }
+        if let Some(admission) = prmt_admission {
+            ensure!(
+                shard.family == "prmt" && shard.intrinsics.is_empty(),
+                "compact prmt admission must be the only content of a prmt shard"
+            );
+            shard.intrinsics = expand_prmt_admission(&admission)?;
+        }
+        if let Some(admission) = packed_conversion_fp8_admission {
+            ensure!(
+                shard.family == "packed_conversion" && shard.intrinsics.is_empty(),
+                "compact FP8 conversion admission must be the only content of a packed_conversion shard"
+            );
+            shard.intrinsics = expand_packed_conversion_fp8_admission(&admission)?;
+        }
+        if let Some(admission) = packed_conversion_fp8_f16x2_admission {
+            ensure!(
+                shard.family == "packed_conversion" && shard.intrinsics.is_empty(),
+                "compact FP8 f16x2 conversion admission must be the only content of a packed_conversion shard"
+            );
+            shard.intrinsics = expand_packed_conversion_fp8_f16x2_admission(&admission)?;
+        }
+        if let Some(admission) = scalar_conversion_admission {
+            ensure!(
+                shard.family == "scalar_conversion" && shard.intrinsics.is_empty(),
+                "compact scalar-conversion admission must be the only content of its shard"
+            );
+            shard.intrinsics = expand_scalar_conversion_admission(&admission)?;
+        }
+        if let Some(admission) = scalar_arithmetic_admission {
+            ensure!(
+                shard.family == "scalar_arithmetic" && shard.intrinsics.is_empty(),
+                "compact scalar-arithmetic admission must be the only content of its shard"
+            );
+            shard.intrinsics = expand_scalar_arithmetic_admission(&admission)?;
+        }
+        if let Some(admission) = scalar_math_admission {
+            ensure!(
+                shard.family == "scalar_math" && shard.intrinsics.is_empty(),
+                "compact scalar-math admission must be the only content of its shard"
+            );
+            shard.intrinsics = expand_scalar_math_admission(&admission)?;
+        }
+        if let Some(admission) = extended_minmax_admission {
+            ensure!(
+                shard.family == "extended_minmax" && shard.intrinsics.is_empty(),
+                "compact extended-minmax admission must be the only content of its shard"
+            );
+            shard.intrinsics = expand_extended_minmax_admission(&admission)?;
+        }
+        if let Some(admission) = cluster_sreg_admission {
+            ensure!(
+                shard.family == "sreg" && shard.intrinsics.is_empty() && compact_mma_count == 0,
+                "compact cluster-sreg admission must be the only content of an sreg shard"
+            );
+            shard.intrinsics = expand_cluster_sreg_admission(&admission)?;
+        }
+        if let Some(admission) = cluster_barrier_admission {
+            ensure!(
+                shard.family == "cluster_barrier" && shard.intrinsics.is_empty(),
+                "compact cluster-barrier admission must be the only content of its shard"
+            );
+            shard.intrinsics = expand_cluster_barrier_admission(&admission)?;
+        }
+        if let Some(admission) = mbarrier_extended_admission {
+            ensure!(
+                shard.family == "mbarrier_extended" && shard.intrinsics.is_empty(),
+                "compact extended-mbarrier admission must be the only content of its shard"
+            );
+            shard.intrinsics = expand_mbarrier_extended_admission(&admission)?;
+        }
+        if let Some(admission) = special_register_admission {
+            ensure!(
+                shard.family == "sreg" && shard.intrinsics.is_empty(),
+                "compact special-register admission must be the only content of an sreg shard"
+            );
+            shard.intrinsics = expand_special_register_admission(&admission)?;
+        }
+        if let Some(admission) = debug_control_admission {
+            ensure!(
+                shard.family == "debug_control" && shard.intrinsics.is_empty(),
+                "compact debug-control admission must be the only content of a debug_control shard"
+            );
+            shard.intrinsics = expand_debug_control_admission(&admission)?;
+        }
+        if let Some(admission) = threadfence_admission {
+            ensure!(
+                shard.family == "sync" && shard.intrinsics.is_empty(),
+                "compact threadfence admission must be the only content of a sync shard"
+            );
+            shard.intrinsics = expand_threadfence_admission(&admission)?;
+        }
+        if let Some(admission) = cluster_memory_admission {
+            ensure!(
+                shard.family == "cluster_memory" && shard.intrinsics.is_empty(),
+                "compact cluster-memory admission must be the only content of its shard"
+            );
+            shard.intrinsics = expand_cluster_memory_admission(&admission)?;
+        }
+        if let Some(admission) = stmatrix_admission {
+            ensure!(
+                shard.family == "stmatrix" && shard.intrinsics.is_empty(),
+                "compact stmatrix admission must be the only content of its shard"
+            );
+            shard.intrinsics = expand_stmatrix_admission(&admission)?;
+        }
+        if let Some(admission) = clc_admission {
+            ensure!(
+                shard.family == "clc" && shard.intrinsics.is_empty(),
+                "compact CLC admission must be the only content of a clc shard"
+            );
+            shard.intrinsics = expand_clc_admission(&admission)?;
+        }
+        if let Some(admission) = wgmma_control_admission {
+            ensure!(
+                shard.family == "wgmma_control" && shard.intrinsics.is_empty(),
+                "compact WGMMA-control admission must be the only content of its shard"
+            );
+            shard.intrinsics = expand_wgmma_control_admission(&admission)?;
+        }
+        if let Some(admission) = tma_admission {
+            ensure!(
+                shard.family == "tma" && shard.intrinsics.is_empty(),
+                "compact TMA admission must be the only content of a tma shard"
+            );
+            shard.intrinsics = expand_tma_admission(&admission)?;
+        }
+        if let Some(admission) = tcgen05_admission {
+            ensure!(
+                shard.family == "tcgen05" && shard.intrinsics.is_empty(),
+                "compact tcgen05 admission must be the only content of a tcgen05 shard"
+            );
+            shard.intrinsics = expand_tcgen05_admission(&admission)?;
+        }
+        ensure!(
+            !shard.intrinsics.is_empty(),
+            "overlay shard {} contains no intrinsic records",
+            path.display()
+        );
+        for record in &shard.intrinsics {
+            ensure!(
+                record.family == shard.family,
+                "overlay shard {} declares family {}, but intrinsic {} uses family {}",
+                path.display(),
+                shard.family,
+                record.id,
+                record.family
+            );
+        }
+
+        append_overlay_hash_input(
+            &mut hash_input,
+            relative
+                .to_str()
+                .context("overlay shard path is not valid UTF-8")?,
+            &bytes,
+        );
+        overlay.intrinsics.extend(shard.intrinsics);
+    }
+
+    Ok((overlay, sha256_bytes(&hash_input)))
+}
+
+pub(super) fn validate_overlay_shard_schema(shard: &OverlayShardFile, path: &Path) -> Result<()> {
+    validate_overlay_shard_schema_with_max(shard, path, OVERLAY_SHARD_SCHEMA)
+}
+
+pub(super) fn validate_overlay_shard_schema_with_max(
+    shard: &OverlayShardFile,
+    path: &Path,
+    maximum_schema: u32,
+) -> Result<()> {
+    ensure!(
+        (MINIMUM_OVERLAY_SHARD_SCHEMA..=maximum_schema).contains(&shard.schema),
+        "unsupported overlay shard schema {} in {}",
+        shard.schema,
+        path.display()
+    );
+    ensure!(
+        shard.sparse_mma_f8f6f4_f32.is_none() || shard.schema >= SPARSE_MMA_F8F6F4_SHARD_SCHEMA,
+        "compact sparse f8f6f4 MMA admission requires overlay shard schema {}",
+        SPARSE_MMA_F8F6F4_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.sparse_mma_f8f6f4_f16.is_none() || shard.schema >= SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA,
+        "compact sparse f8f6f4 F16 MMA admission requires overlay shard schema {}",
+        SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.register_mma_f8f6f4_f32.is_none() || shard.schema >= REGISTER_MMA_F8F6F4_SHARD_SCHEMA,
+        "compact dense f8f6f4 MMA admission requires overlay shard schema {}",
+        REGISTER_MMA_F8F6F4_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.register_mma_f8f6f4_f16.is_none()
+            || shard.schema >= REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA,
+        "compact dense f8f6f4 F16 MMA admission requires overlay shard schema {}",
+        REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.register_mma_mxf8f6f4_f32.is_none()
+            || shard.schema >= REGISTER_MMA_MXF8F6F4_SHARD_SCHEMA,
+        "compact dense mxf8f6f4 MMA admission requires overlay shard schema {}",
+        REGISTER_MMA_MXF8F6F4_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.register_mma_fp8.is_none() || shard.schema >= REGISTER_MMA_FP8_SHARD_SCHEMA,
+        "compact standard FP8 MMA admission requires overlay shard schema {}",
+        REGISTER_MMA_FP8_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.register_mma_ampere_float.is_none()
+            || shard.schema >= REGISTER_MMA_AMPERE_FLOAT_SHARD_SCHEMA,
+        "compact Ampere floating-point MMA admission requires overlay shard schema {}",
+        REGISTER_MMA_AMPERE_FLOAT_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.prmt.is_none() || shard.schema >= PRMT_SHARD_SCHEMA,
+        "compact prmt admission requires overlay shard schema {}",
+        PRMT_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.packed_conversion_fp8.is_none() || shard.schema >= PACKED_CONVERSION_FP8_SHARD_SCHEMA,
+        "compact FP8 conversion admission requires overlay shard schema {}",
+        PACKED_CONVERSION_FP8_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.packed_conversion_fp8_f16x2.is_none()
+            || shard.schema >= PACKED_CONVERSION_FP8_F16X2_SHARD_SCHEMA,
+        "compact FP8 f16x2 conversion admission requires overlay shard schema {}",
+        PACKED_CONVERSION_FP8_F16X2_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.scalar_conversion.is_none() || shard.schema >= SCALAR_CONVERSION_SHARD_SCHEMA,
+        "compact scalar-conversion admission requires overlay shard schema {}",
+        SCALAR_CONVERSION_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.scalar_arithmetic.is_none() || shard.schema >= SCALAR_ARITHMETIC_SHARD_SCHEMA,
+        "compact scalar-arithmetic admission requires overlay shard schema {}",
+        SCALAR_ARITHMETIC_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.scalar_math.is_none() || shard.schema >= SCALAR_MATH_SHARD_SCHEMA,
+        "compact scalar-math admission requires overlay shard schema {}",
+        SCALAR_MATH_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.extended_minmax.is_none() || shard.schema >= EXTENDED_MINMAX_SHARD_SCHEMA,
+        "compact extended-minmax admission requires overlay shard schema {}",
+        EXTENDED_MINMAX_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.cluster_sreg.is_none() || shard.schema >= CLUSTER_SREG_SHARD_SCHEMA,
+        "compact cluster-sreg admission requires overlay shard schema {}",
+        CLUSTER_SREG_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.cluster_barrier.is_none() || shard.schema >= CLUSTER_BARRIER_SHARD_SCHEMA,
+        "compact cluster-barrier admission requires overlay shard schema {}",
+        CLUSTER_BARRIER_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.special_registers.is_none() || shard.schema >= SPECIAL_REGISTER_SHARD_SCHEMA,
+        "compact special-register admission requires overlay shard schema {}",
+        SPECIAL_REGISTER_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.debug_control.is_none() || shard.schema >= DEBUG_CONTROL_SHARD_SCHEMA,
+        "compact debug-control admission requires overlay shard schema {}",
+        DEBUG_CONTROL_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.threadfence.is_none() || shard.schema >= THREADFENCE_SHARD_SCHEMA,
+        "compact threadfence admission requires overlay shard schema {}",
+        THREADFENCE_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.cluster_memory.is_none() || shard.schema >= CLUSTER_MEMORY_SHARD_SCHEMA,
+        "compact cluster-memory admission requires overlay shard schema {}",
+        CLUSTER_MEMORY_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.stmatrix.is_none() || shard.schema >= STMATRIX_SHARD_SCHEMA,
+        "compact stmatrix admission requires overlay shard schema {}",
+        STMATRIX_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.clc.is_none() || shard.schema >= CLC_SHARD_SCHEMA,
+        "compact CLC admission requires overlay shard schema {}",
+        CLC_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.tma.is_none() || shard.schema >= TMA_SHARD_SCHEMA,
+        "compact TMA admission requires overlay shard schema {}",
+        TMA_SHARD_SCHEMA
+    );
+    ensure!(
+        shard
+            .tma
+            .as_ref()
+            .is_none_or(|admission| admission.reduce_variants.is_empty())
+            || shard.schema >= TMA_REDUCTION_SHARD_SCHEMA,
+        "compact TMA reduction admission requires overlay shard schema {}",
+        TMA_REDUCTION_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.mbarrier_extended.is_none() || shard.schema >= MBARRIER_EXTENDED_SHARD_SCHEMA,
+        "compact extended-mbarrier admission requires overlay shard schema {}",
+        MBARRIER_EXTENDED_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.wgmma_controls.is_none() || shard.schema >= WGMMA_CONTROL_SHARD_SCHEMA,
+        "compact WGMMA-control admission requires overlay shard schema {}",
+        WGMMA_CONTROL_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.tcgen05.is_none() || shard.schema >= TCGEN05_SHARD_SCHEMA,
+        "compact tcgen05 admission requires overlay shard schema {}",
+        TCGEN05_SHARD_SCHEMA
+    );
+    ensure!(
+        shard
+            .tcgen05
+            .as_ref()
+            .is_none_or(|admission| admission.cp_variants.is_empty())
+            || shard.schema >= TCGEN05_CP_SHARD_SCHEMA,
+        "compact tcgen05 copy admission requires overlay shard schema {}",
+        TCGEN05_CP_SHARD_SCHEMA
+    );
+    ensure!(
+        shard
+            .tcgen05
+            .as_ref()
+            .is_none_or(|admission| admission.ld_variants.is_empty())
+            || shard.schema >= TCGEN05_LD_SHARD_SCHEMA,
+        "compact tcgen05 load admission requires overlay shard schema {}",
+        TCGEN05_LD_SHARD_SCHEMA
+    );
+    ensure!(
+        shard
+            .tcgen05
+            .as_ref()
+            .is_none_or(|admission| admission.st_variants.is_empty())
+            || shard.schema >= TCGEN05_ST_SHARD_SCHEMA,
+        "compact tcgen05 store admission requires overlay shard schema {}",
+        TCGEN05_ST_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.tcgen05.as_ref().is_none_or(|admission| {
+            admission.ld_offset_variants.is_empty() && admission.st_offset_variants.is_empty()
+        }) || shard.schema >= TCGEN05_OFFSET_LDST_SHARD_SCHEMA,
+        "compact tcgen05 offset load/store admission requires overlay shard schema {}",
+        TCGEN05_OFFSET_LDST_SHARD_SCHEMA
+    );
+    ensure!(
+        shard.tcgen05.as_ref().is_none_or(|admission| {
+            admission.control_llvm_evidence_profile.is_none()
+                && admission.control_libnvvm_evidence_profile.is_none()
+                && !admission.variants.iter().any(|variant| {
+                    matches!(
+                        variant.operation,
+                        Tcgen05Operation::CommitMulticast
+                            | Tcgen05Operation::ShiftDown
+                            | Tcgen05Operation::ShiftDownCg2
+                    )
+                })
+        }) || shard.schema >= TCGEN05_CONTROL_SHARD_SCHEMA,
+        "compact tcgen05 control admission requires overlay shard schema {}",
+        TCGEN05_CONTROL_SHARD_SCHEMA
+    );
+    if let Some(admission) = &shard.tcgen05
+        && shard.schema >= TCGEN05_CONTROL_SHARD_SCHEMA
+    {
+        ensure!(
+            admission
+                .control_llvm_evidence_profile
+                .as_deref()
+                .is_some_and(|profile| !profile.trim().is_empty())
+                && admission
+                    .control_libnvvm_evidence_profile
+                    .as_deref()
+                    .is_some_and(|profile| !profile.trim().is_empty())
+                && [
+                    Tcgen05Operation::CommitMulticast,
+                    Tcgen05Operation::ShiftDown,
+                    Tcgen05Operation::ShiftDownCg2,
+                ]
+                .into_iter()
+                .all(|operation| admission
+                    .variants
+                    .iter()
+                    .any(|variant| variant.operation == operation)),
+            "compact tcgen05 schema {} requires all three control variants and both backend evidence profiles",
+            TCGEN05_CONTROL_SHARD_SCHEMA
+        );
+    }
+    ensure!(
+        shard.tcgen05.as_ref().is_none_or(|admission| {
+            admission.mma_variants.is_empty()
+                && admission.mma_llvm_evidence_profile.is_none()
+                && admission.mma_libnvvm_evidence_profile.is_none()
+                && admission.mma_llvm_target_contracts.is_empty()
+                && admission.mma_libnvvm_target_contracts.is_empty()
+        }) || shard.schema >= TCGEN05_MMA_SHARD_SCHEMA,
+        "compact tcgen05 MMA admission requires overlay shard schema {}",
+        TCGEN05_MMA_SHARD_SCHEMA
+    );
+    Ok(())
+}
+
+pub(super) fn validate_overlay_shard_path(path: &str) -> Result<()> {
+    let path = Path::new(path);
+    ensure!(
+        path.extension().and_then(|extension| extension.to_str()) == Some("toml"),
+        "overlay shard path must name a TOML file: {}",
+        path.display()
+    );
+    let components: Vec<_> = path.components().collect();
+    ensure!(
+        components.len() >= 2 && components[0] == Component::Normal("overlay".as_ref()),
+        "overlay shard path must stay under intrinsics/overlay: {}",
+        path.display()
+    );
+    ensure!(
+        components
+            .iter()
+            .all(|component| matches!(component, Component::Normal(_))),
+        "overlay shard path contains a non-normal component: {}",
+        path.display()
+    );
+    Ok(())
+}
+
+pub(super) fn append_overlay_hash_input(output: &mut Vec<u8>, path: &str, contents: &[u8]) {
+    output.extend_from_slice(&(path.len() as u64).to_le_bytes());
+    output.extend_from_slice(path.as_bytes());
+    output.extend_from_slice(&(contents.len() as u64).to_le_bytes());
+    output.extend_from_slice(contents);
+}
+
+pub(super) fn shares_tma_2d_g2s_symbol(record: &OverlayIntrinsic, symbol: &str) -> bool {
+    symbol == "llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d"
+        && record.tma.as_ref().is_some_and(|tma| {
+            matches!(
+                tma.operation,
+                TmaOperation::G2sTile2d
+                    | TmaOperation::G2sTile2dMulticast
+                    | TmaOperation::G2sTile2dMulticastCg2
+            )
+        })
+}
+
+pub(super) fn shares_tma_prefetch_tile_symbol(record: &OverlayIntrinsic, symbol: &str) -> bool {
+    let Some(tma) = record.tma.as_ref() else {
+        return false;
+    };
+    let expected_symbol = match tma.operation {
+        TmaOperation::PrefetchTile1d | TmaOperation::PrefetchTile1dCacheHint => {
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d"
+        }
+        TmaOperation::PrefetchTile2d | TmaOperation::PrefetchTile2dCacheHint => {
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d"
+        }
+        TmaOperation::PrefetchTile3d | TmaOperation::PrefetchTile3dCacheHint => {
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d"
+        }
+        TmaOperation::PrefetchTile4d | TmaOperation::PrefetchTile4dCacheHint => {
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d"
+        }
+        TmaOperation::PrefetchTile5d | TmaOperation::PrefetchTile5dCacheHint => {
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d"
+        }
+        TmaOperation::PrefetchTileGather4TwoDimensional
+        | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint => {
+            "llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.gather4.2d"
+        }
+        _ => return false,
+    };
+    symbol == expected_symbol
+}
+
+pub(super) fn shares_tcgen05_mma_symbol(record: &OverlayIntrinsic, symbol: &str) -> bool {
+    record.tcgen05.as_ref().is_some_and(|tcgen05| {
+        (symbol == "llvm.nvvm.tcgen05.mma.ws.tensor"
+            && matches!(
+                tcgen05.operation,
+                Tcgen05Operation::MmaWsF16
+                    | Tcgen05Operation::MmaWsBf16
+                    | Tcgen05Operation::MmaWsTf32
+            ))
+            || tcgen05
+                .mma
+                .as_ref()
+                .is_some_and(|mma| symbol == tcgen05_mma_llvm_symbol(mma.form))
+    })
+}
+
+pub(super) fn shares_tcgen05_ld_symbol(record: &OverlayIntrinsic, symbol: &str) -> bool {
+    let Some(tcgen05) = record.tcgen05.as_ref() else {
+        return false;
+    };
+    if let Some(ld) = tcgen05.ld {
+        return tcgen05.operation == Tcgen05Operation::Ld
+            && record.source_record.as_deref() == Some(tcgen05_ld_source_record(ld).as_str())
+            && symbol == tcgen05_ld_llvm_symbol(ld);
+    }
+    matches!(
+        (tcgen05.operation, record.source_record.as_deref(), symbol),
+        (
+            Tcgen05Operation::Ld16x256bPure,
+            Some("int_nvvm_tcgen05_ld_16x256b_x1"),
+            "llvm.nvvm.tcgen05.ld.16x256b.x1"
+        ) | (
+            Tcgen05Operation::Ld16x256bX8Pure,
+            Some("int_nvvm_tcgen05_ld_16x256b_x8"),
+            "llvm.nvvm.tcgen05.ld.16x256b.x8"
+        )
+    )
+}
+
+pub(super) fn shares_tcgen05_st_symbol(record: &OverlayIntrinsic, symbol: &str) -> bool {
+    record.tcgen05.as_ref().is_some_and(|tcgen05| {
+        tcgen05.st.is_some_and(|st| {
+            tcgen05.operation == Tcgen05Operation::St
+                && record.source_record.as_deref() == Some(tcgen05_st_source_record(st).as_str())
+                && symbol == tcgen05_st_llvm_symbol(st)
+        })
+    })
+}
+
+pub(super) fn validate_unique_overlay(
+    records: &[OverlayIntrinsic],
+    intrinsic_abi: u32,
+) -> Result<()> {
+    let mut ids = BTreeSet::new();
+    let mut abi_ids = BTreeSet::new();
+    let mut operation_keys = BTreeSet::new();
+    let mut paths = BTreeSet::new();
+    let mut op_variants = BTreeSet::new();
+    let mut op_type_names = BTreeMap::new();
+    let mut symbol_bases = BTreeMap::new();
+    let mut symbols = BTreeSet::new();
+    let mut rust_items = BTreeSet::new();
+    for record in records {
+        insert_unique(&mut ids, &record.id, "catalog ID")?;
+        validate_abi_id(&record.abi_id)?;
+        insert_unique(&mut abi_ids, &record.abi_id, "intrinsic ABI ID")?;
+        validate_operation_key(&record.operation_key)?;
+        insert_unique(
+            &mut operation_keys,
+            &record.operation_key,
+            "intrinsic operation key",
+        )?;
+        if let Some(previous_name) = op_type_names.insert(
+            record.dialect_op_type.as_str(),
+            record.dialect_op_name.as_str(),
+        ) {
+            ensure!(
+                previous_name == record.dialect_op_name,
+                "dialect op type {} maps to both {} and {}",
+                record.dialect_op_type,
+                previous_name,
+                record.dialect_op_name
+            );
+        }
+        let op_variant = format!(
+            "{}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}:{:?}",
+            record.dialect_op_name,
+            record.ldmatrix_variant,
+            record.packed_atomic,
+            record.redux,
+            record.vote,
+            record.active_mask,
+            record.warp_match,
+            record.warp_barrier,
+            record.warp_shuffle,
+            record.dot_product,
+            record.cp_async_copy,
+            record.cp_async_control,
+            record.cp_async_mbarrier,
+            record.mbarrier_basic,
+            record.movmatrix,
+            record.mbarrier_extended,
+            record.register_mma,
+            record.sparse_mma,
+            record.prmt,
+            record.cluster_barrier,
+            record.cluster_memory,
+            record.scalar_conversion,
+            record.scalar_arithmetic,
+            record.scalar_math,
+            record.extended_minmax,
+            record.tcgen05,
+        );
+        insert_unique(&mut op_variants, &op_variant, "dialect op variant")?;
+        if let Some(symbol) = &record.llvm_symbol {
+            let is_resolved = record.resolved_llvm_symbol.is_some();
+            let shares_reviewed_symbol = shares_tma_2d_g2s_symbol(record, symbol)
+                || shares_tma_prefetch_tile_symbol(record, symbol)
+                || shares_tcgen05_mma_symbol(record, symbol)
+                || shares_tcgen05_ld_symbol(record, symbol)
+                || shares_tcgen05_st_symbol(record, symbol);
+            if let Some((previous_was_resolved, previous_shared_symbol)) =
+                symbol_bases.insert(symbol, (is_resolved, shares_reviewed_symbol))
+            {
+                ensure!(
+                    (previous_was_resolved && is_resolved)
+                        || (previous_shared_symbol && shares_reviewed_symbol),
+                    "duplicate LLVM symbol {symbol} is reused without a resolved symbol"
+                );
+            }
+            if !shares_reviewed_symbol {
+                insert_unique(
+                    &mut symbols,
+                    record.resolved_llvm_symbol.as_ref().unwrap_or(symbol),
+                    "resolved LLVM symbol",
+                )?;
+            }
+        }
+        insert_unique(
+            &mut rust_items,
+            &format!("{}::{}", record.rust_module, record.rust_name),
+            "raw Rust item",
+        )?;
+        insert_unique(
+            &mut paths,
+            &canonical_rust_path(intrinsic_abi, &record.abi_id),
+            "canonical Rust path",
+        )?;
+        insert_unique(&mut paths, &record.public_rust_path, "public Rust path")?;
+        for path in &record.compatibility_rust_paths {
+            insert_unique(&mut paths, path, "compatibility Rust path")?;
+        }
+    }
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/policy.rs b/crates/cuda-intrinsics-gen/src/resolve/policy.rs
new file mode 100644
index 0000000000..77131f0bb7
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/policy.rs
@@ -0,0 +1,612 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ClcOperation, CpAsyncSourceSize, ImportedIntrinsic, IntrinsicSource,
+    MbarrierExtendedOperation, OverlayIntrinsic, ScalarMathOperation, SpecialRegisterKind,
+    Tcgen05SourceContract, TmaOperation,
+};
+use anyhow::{Context, Result, bail, ensure};
+
+use super::abi_ledger::*;
+use super::families::*;
+use super::guards::*;
+use super::targets::*;
+
+pub(super) fn resolve_policy_source(policy: &OverlayIntrinsic) -> Result<IntrinsicSource> {
+    match (&policy.source, &policy.source_record) {
+        (None, Some(source_record)) => Ok(IntrinsicSource::LlvmImported {
+            source_record: source_record.clone(),
+        }),
+        (Some(source @ IntrinsicSource::PtxNative { .. }), None) => Ok(source.clone()),
+        (Some(IntrinsicSource::LlvmImported { source_record }), None) => {
+            ensure!(
+                !source_record.trim().is_empty(),
+                "{} has an empty imported LLVM source record",
+                policy.id
+            );
+            Ok(IntrinsicSource::LlvmImported {
+                source_record: source_record.clone(),
+            })
+        }
+        (Some(_), Some(_)) => bail!(
+            "{} mixes tagged source provenance with the legacy source_record field",
+            policy.id
+        ),
+        (None, None) => bail!("{} has no intrinsic source provenance", policy.id),
+    }
+}
+
+pub(super) fn validate_policy(
+    policy: &OverlayIntrinsic,
+    source: &IntrinsicSource,
+    declaration: Option<&ImportedIntrinsic>,
+    intrinsic_abi: u32,
+) -> Result<()> {
+    validate_abi_id(&policy.abi_id)?;
+    parse_ptx_version(&policy.minimum_ptx, &policy.id)?;
+    parse_hardware_target(policy)?;
+    policy.expected_ptx.validate().map_err(|reason| {
+        anyhow::anyhow!(
+            "{} has an invalid expected PTX pattern: {reason}",
+            policy.id
+        )
+    })?;
+    let public_path = format!(
+        "cuda_intrinsics::{}::{}",
+        policy.rust_module, policy.rust_name
+    );
+    ensure!(
+        policy.public_rust_path == public_path,
+        "{} public Rust path must be {}",
+        policy.id,
+        public_path
+    );
+    let canonical_path = canonical_rust_path(intrinsic_abi, &policy.abi_id);
+    ensure!(
+        canonical_path != policy.public_rust_path
+            && !policy
+                .compatibility_rust_paths
+                .iter()
+                .any(|path| path == &canonical_path || path == &policy.public_rust_path),
+        "{} must keep canonical, public, and compatibility Rust paths distinct",
+        policy.id
+    );
+    match (source, declaration) {
+        (IntrinsicSource::LlvmImported { .. }, Some(declaration)) => {
+            ensure!(
+                policy.llvm_symbol.as_deref() == Some(declaration.llvm_name.as_str()),
+                "{} LLVM symbol mismatch: imported {}, overlay {:?}",
+                policy.id,
+                declaration.llvm_name,
+                policy.llvm_symbol
+            );
+            ensure!(
+                declaration.arguments == policy.llvm_arguments,
+                "{} LLVM argument signature mismatch: imported {:?}, overlay {:?}",
+                policy.id,
+                declaration.arguments,
+                policy.llvm_arguments
+            );
+            ensure!(
+                declaration.results == policy.llvm_results,
+                "{} LLVM result signature mismatch: imported {:?}, overlay {:?}",
+                policy.id,
+                declaration.results,
+                policy.llvm_results
+            );
+        }
+        (IntrinsicSource::PtxNative { instruction }, None) => ensure!(
+            !instruction.trim().is_empty()
+                && policy.llvm_symbol.is_none()
+                && policy.resolved_llvm_symbol.is_none()
+                && policy.llvm_arguments.is_empty()
+                && policy.llvm_results.is_empty(),
+            "{} PTX-native source must not invent LLVM source facts",
+            policy.id
+        ),
+        _ => bail!(
+            "{} source kind and imported declaration disagree",
+            policy.id
+        ),
+    }
+    match policy.family.as_str() {
+        "sreg" => validate_sreg_policy(policy, source, declaration)?,
+        "ldmatrix" => validate_ldmatrix_policy(
+            policy,
+            declaration.context("ldmatrix requires imported LLVM declaration")?,
+        )?,
+        "stmatrix" => validate_stmatrix_policy(
+            policy,
+            declaration.context("stmatrix requires imported LLVM declaration")?,
+        )?,
+        "packed_atomic" => validate_packed_atomic_policy(policy, source)?,
+        "redux" => validate_redux_policy(
+            policy,
+            declaration.context("redux requires imported LLVM declaration")?,
+        )?,
+        "dotprod" => validate_dot_product_policy(
+            policy,
+            declaration.context("dotprod requires imported LLVM declaration")?,
+        )?,
+        "sync" => validate_sync_policy(
+            policy,
+            declaration.context("sync requires imported LLVM declaration")?,
+        )?,
+        "vote" => validate_vote_policy(
+            policy,
+            declaration.context("vote requires imported LLVM declaration")?,
+        )?,
+        "active_mask" => validate_active_mask_policy(
+            policy,
+            declaration.context("active_mask requires imported LLVM declaration")?,
+        )?,
+        "warp_match" => validate_warp_match_policy(
+            policy,
+            declaration.context("warp_match requires imported LLVM declaration")?,
+        )?,
+        "elect" => validate_elect_policy(
+            policy,
+            declaration.context("elect requires imported LLVM declaration")?,
+        )?,
+        "warp_barrier" => validate_warp_barrier_policy(
+            policy,
+            declaration.context("warp_barrier requires imported LLVM declaration")?,
+        )?,
+        "warp_shuffle" => validate_warp_shuffle_policy(policy, declaration)?,
+        "packed_alu" => validate_packed_alu_policy(policy, source, declaration)?,
+        "integer_minmax" => validate_integer_minmax_policy(policy, source, declaration)?,
+        "packed_conversion" => validate_packed_conversion_policy(policy, source, declaration)?,
+        "scalar_conversion" => validate_scalar_conversion_policy(
+            policy,
+            declaration.context("scalar_conversion requires imported LLVM declaration")?,
+        )?,
+        "scalar_arithmetic" => validate_scalar_arithmetic_policy(
+            policy,
+            declaration.context("scalar_arithmetic requires imported LLVM declaration")?,
+        )?,
+        "scalar_math" => validate_scalar_math_policy(policy, declaration)?,
+        "extended_minmax" => validate_extended_minmax_policy(
+            policy,
+            declaration.context("extended_minmax requires imported LLVM declaration")?,
+        )?,
+        "cp_async_copy" => validate_cp_async_copy_policy(
+            policy,
+            declaration.context("cp_async_copy requires imported LLVM declaration")?,
+        )?,
+        "cp_async_control" => validate_cp_async_control_policy(
+            policy,
+            declaration.context("cp_async_control requires imported LLVM declaration")?,
+        )?,
+        "cp_async_mbarrier" => validate_cp_async_mbarrier_policy(
+            policy,
+            declaration.context("cp_async_mbarrier requires imported LLVM declaration")?,
+        )?,
+        "mbarrier_basic" => validate_mbarrier_basic_policy(
+            policy,
+            declaration.context("mbarrier_basic requires imported LLVM declaration")?,
+        )?,
+        "movmatrix" => validate_movmatrix_policy(policy, source)?,
+        "mbarrier_extended" => validate_mbarrier_extended_policy(policy, source, declaration)?,
+        "register_mma" => validate_register_mma_policy(
+            policy,
+            declaration.context("register_mma requires imported LLVM declaration")?,
+        )?,
+        "sparse_mma" => validate_sparse_mma_policy(
+            policy,
+            declaration.context("sparse_mma requires imported LLVM declaration")?,
+        )?,
+        "prmt" => validate_prmt_policy(
+            policy,
+            declaration.context("prmt requires imported LLVM declaration")?,
+        )?,
+        "cluster_barrier" => validate_cluster_barrier_policy(
+            policy,
+            declaration.context("cluster_barrier requires imported LLVM declaration")?,
+        )?,
+        "debug_control" => validate_debug_control_policy(policy, source)?,
+        "cluster_memory" => validate_cluster_memory_policy(policy, source, declaration)?,
+        "clc" => validate_clc_policy(
+            policy,
+            declaration.context("clc requires imported LLVM declaration")?,
+        )?,
+        "wgmma_control" => validate_wgmma_control_policy(
+            policy,
+            declaration.context("wgmma_control requires imported LLVM declaration")?,
+        )?,
+        "tma" => validate_tma_policy(
+            policy,
+            declaration.context("tma requires imported LLVM declaration")?,
+        )?,
+        "counted_barrier" | "grid_dependency" | "register_control" => {
+            validate_execution_control_policy(
+                policy,
+                declaration.context("execution-control requires imported LLVM declaration")?,
+            )?
+        }
+        "tcgen05" => validate_tcgen05_policy(
+            policy,
+            declaration.context("tcgen05 requires imported LLVM declaration")?,
+        )?,
+        family => bail!("{} uses unsupported generated family {family:?}", policy.id),
+    }
+    ensure!(
+        (policy.family == "movmatrix") == policy.movmatrix.is_some(),
+        "{} mixes the movmatrix contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "mbarrier_extended") == policy.mbarrier_extended.is_some(),
+        "{} mixes the extended-mbarrier contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "register_mma") == policy.register_mma.is_some(),
+        "{} mixes the register-MMA contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "sparse_mma") == policy.sparse_mma.is_some(),
+        "{} mixes the sparse-MMA contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "prmt") == policy.prmt.is_some(),
+        "{} mixes the prmt contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "cluster_barrier") == policy.cluster_barrier.is_some(),
+        "{} mixes the cluster-barrier contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "wgmma_control") == policy.wgmma_control.is_some(),
+        "{} mixes the WGMMA-control contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "tma") == policy.tma.is_some(),
+        "{} mixes the TMA contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        policy.special_register.is_none() || policy.family == "sreg",
+        "{} mixes the special-register contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "debug_control") == policy.debug_control.is_some(),
+        "{} mixes the debug-control contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "cluster_memory") == policy.cluster_memory.is_some(),
+        "{} mixes the cluster-memory contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "clc") == policy.clc.is_some(),
+        "{} mixes the CLC contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "tma") == policy.tma.is_some(),
+        "{} mixes the TMA contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "tcgen05") == policy.tcgen05.is_some(),
+        "{} mixes the tcgen05 contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "scalar_conversion") == policy.scalar_conversion.is_some(),
+        "{} mixes the scalar-conversion contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "scalar_arithmetic") == policy.scalar_arithmetic.is_some(),
+        "{} mixes the scalar-arithmetic contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "scalar_math") == policy.scalar_math.is_some(),
+        "{} mixes the scalar-math contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        (policy.family == "extended_minmax") == policy.extended_minmax.is_some(),
+        "{} mixes the extended-minmax contract with another generated family",
+        policy.id
+    );
+    ensure!(
+        !policy.execution_scope.trim().is_empty(),
+        "{} has no execution scope",
+        policy.id
+    );
+    ensure!(
+        !policy.ptx_isa_version.trim().is_empty()
+            && !policy.ptx_isa_section.trim().is_empty()
+            && policy.ptx_isa_url.starts_with("https://docs.nvidia.com/"),
+        "{} has incomplete or non-authoritative PTX ISA provenance",
+        policy.id
+    );
+    match (policy.safe, policy.safe_allowlist_reason.as_deref()) {
+        (true, Some(reason)) if !reason.trim().is_empty() => {}
+        (true, _) => bail!(
+            "{} is safe but has no nonempty safe_allowlist_reason",
+            policy.id
+        ),
+        (false, Some(reason)) if !reason.trim().is_empty() => bail!(
+            "{} is unsafe but has a safe_allowlist_reason; safe exceptions apply only to safe items",
+            policy.id
+        ),
+        (false, _) => {}
+    }
+    if let Some(declaration) = declaration {
+        if policy.pure {
+            ensure!(
+                declaration
+                    .classes
+                    .iter()
+                    .any(|class| class == "NVVMPureIntrinsic")
+                    || (matches!(
+                        policy.family.as_str(),
+                        "packed_alu" | "scalar_arithmetic" | "extended_minmax"
+                    ) && declaration
+                        .properties
+                        .iter()
+                        .any(|property| property == "IntrNoMem")
+                        && declaration
+                            .properties
+                            .iter()
+                            .any(|property| property == "IntrSpeculatable"))
+                    || (policy.family == "scalar_math"
+                        && declaration
+                            .properties
+                            .iter()
+                            .any(|property| property == "IntrNoMem")),
+                "{} is marked pure, but its imported declaration is not an NVVMPureIntrinsic",
+                policy.id
+            );
+        }
+        if policy.memory == "none" {
+            ensure!(
+                declaration
+                    .properties
+                    .iter()
+                    .any(|property| property == "IntrNoMem"),
+                "{} is marked no-memory, but its imported declaration lacks IntrNoMem",
+                policy.id
+            );
+        }
+        let imported_convergent = declaration
+            .properties
+            .iter()
+            .any(|property| property == "IntrConvergent");
+        let convergence_supplied_by_ptx =
+            (matches!(policy.family.as_str(), "register_mma" | "sparse_mma")
+                && (policy.register_mma.is_some() || policy.sparse_mma.is_some())
+                || (policy.family == "cluster_memory"
+                    && policy.cluster_memory.is_some()
+                    && policy.backend_lowerings.iter().all(|lowering| {
+                        lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                    }))
+                || (policy.family == "mbarrier_extended"
+                    && policy.mbarrier_extended.is_some()
+                    && policy.backend_lowerings.iter().all(|lowering| {
+                        lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                    }))
+                || (policy.family == "tcgen05"
+                    && policy.tcgen05.is_some()
+                    && policy.backend_lowerings.iter().all(|lowering| {
+                        lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                    })))
+                && policy.convergent
+                && !imported_convergent;
+        ensure!(
+            imported_convergent == policy.convergent || convergence_supplied_by_ptx,
+            "{} convergence mismatch: imported {}, overlay {}",
+            policy.id,
+            imported_convergent,
+            policy.convergent
+        );
+        let selectionless_closed_family = (policy.family == "packed_conversion"
+            && policy.packed_conversion.is_some())
+            || (policy.family == "prmt" && policy.prmt.is_some())
+            || (policy.family == "clc"
+                && policy.clc.as_ref().is_some_and(|clc| {
+                    matches!(
+                        clc.operation,
+                        ClcOperation::QueryIsCanceled
+                            | ClcOperation::QueryGetFirstCtaidX
+                            | ClcOperation::QueryGetFirstCtaidY
+                            | ClcOperation::QueryGetFirstCtaidZ
+                    )
+                }))
+            || (policy.family == "sreg"
+                && policy.special_register.as_ref().is_some_and(|special| {
+                    matches!(
+                        special.register,
+                        SpecialRegisterKind::Envreg1 | SpecialRegisterKind::Envreg2
+                    )
+                }))
+            || policy.family == "stmatrix"
+            || (policy.family == "tma"
+                && policy.tma.as_ref().is_some_and(|tma| {
+                    matches!(
+                        tma.operation,
+                        TmaOperation::Reduce
+                            | TmaOperation::PrefetchTensorMap
+                            | TmaOperation::ReplaceBoxDim
+                            | TmaOperation::ReplaceElementStride
+                            | TmaOperation::ReplaceElementType
+                            | TmaOperation::ReplaceFillMode
+                            | TmaOperation::ReplaceGlobalAddress
+                            | TmaOperation::ReplaceGlobalDim
+                            | TmaOperation::ReplaceGlobalStride
+                            | TmaOperation::ReplaceInterleaveLayout
+                            | TmaOperation::ReplaceRank
+                            | TmaOperation::ReplaceSwizzleAtomicity
+                            | TmaOperation::ReplaceSwizzleMode
+                    )
+                }))
+            || (policy.family == "tcgen05"
+                && policy.tcgen05.as_ref().is_some_and(|tcgen05| {
+                    tcgen05.source_contract
+                        == Tcgen05SourceContract::LlvmCustomLoweringWithoutSelection
+                }))
+            || (policy.family == "scalar_math"
+                && policy.scalar_math.as_ref().is_some_and(|sm| {
+                    // Tanh is absent here only because it is PTX-native (no
+                    // imported declaration), so this check never sees it.
+                    matches!(
+                        sm.operation,
+                        ScalarMathOperation::Sin
+                            | ScalarMathOperation::Cos
+                            | ScalarMathOperation::Ex2
+                            | ScalarMathOperation::Lg2
+                            | ScalarMathOperation::Rsqrt
+                    )
+                }));
+        ensure!(
+            !declaration.selections.is_empty() || selectionless_closed_family,
+            "{} has a declaration but no NVPTX TableGen selection record",
+            policy.id
+        );
+        let mut matching_selections = Vec::new();
+        for selection in &declaration.selections {
+            if selection_matches_policy(policy, selection)? {
+                matching_selections.push(selection);
+            }
+        }
+        let expected_selection_count = match policy.family.as_str() {
+            "vote" | "warp_barrier" | "elect" => 2,
+            "warp_match" => 4,
+            "warp_shuffle" => 8,
+            "counted_barrier" => 4,
+            "packed_conversion" | "prmt" | "stmatrix" => 0,
+            "tma"
+                if policy.tma.as_ref().is_some_and(|tma| {
+                    matches!(
+                        tma.operation,
+                        TmaOperation::Reduce
+                            | TmaOperation::PrefetchTensorMap
+                            | TmaOperation::ReplaceBoxDim
+                            | TmaOperation::ReplaceElementStride
+                            | TmaOperation::ReplaceElementType
+                            | TmaOperation::ReplaceFillMode
+                            | TmaOperation::ReplaceGlobalAddress
+                            | TmaOperation::ReplaceGlobalDim
+                            | TmaOperation::ReplaceGlobalStride
+                            | TmaOperation::ReplaceInterleaveLayout
+                            | TmaOperation::ReplaceRank
+                            | TmaOperation::ReplaceSwizzleAtomicity
+                            | TmaOperation::ReplaceSwizzleMode
+                    )
+                }) =>
+            {
+                0
+            }
+            "tcgen05"
+                if policy
+                    .tcgen05
+                    .as_ref()
+                    .and_then(|tcgen05| tcgen05.mma.as_ref())
+                    .is_some() =>
+            {
+                let mma = policy.tcgen05.as_ref().unwrap().mma.as_ref().unwrap();
+                if mma.alias.is_some() {
+                    1
+                } else if tcgen05_mma_is_ws(mma.form) {
+                    64
+                } else if tcgen05_mma_is_ashift(mma.form) {
+                    16
+                } else {
+                    32
+                }
+            }
+            "tcgen05"
+                if policy.tcgen05.as_ref().is_some_and(|tcgen05| {
+                    tcgen05.source_contract != Tcgen05SourceContract::ExactTablegenSelection
+                }) =>
+            {
+                0
+            }
+            "clc"
+                if policy.clc.as_ref().is_some_and(|clc| {
+                    matches!(
+                        clc.operation,
+                        ClcOperation::QueryIsCanceled
+                            | ClcOperation::QueryGetFirstCtaidX
+                            | ClcOperation::QueryGetFirstCtaidY
+                            | ClcOperation::QueryGetFirstCtaidZ
+                    )
+                }) =>
+            {
+                0
+            }
+            "sreg"
+                if policy.special_register.as_ref().is_some_and(|special| {
+                    matches!(
+                        special.register,
+                        SpecialRegisterKind::Envreg1 | SpecialRegisterKind::Envreg2
+                    )
+                }) =>
+            {
+                0
+            }
+            "mbarrier_extended"
+                if policy.mbarrier_extended.as_ref().is_some_and(|mbarrier| {
+                    matches!(
+                        mbarrier.operation,
+                        MbarrierExtendedOperation::ArriveExpectTxCta
+                            | MbarrierExtendedOperation::ArriveExpectTxCluster
+                            | MbarrierExtendedOperation::TryWaitParityCta
+                            | MbarrierExtendedOperation::TryWaitParityCluster
+                    )
+                }) =>
+            {
+                0
+            }
+            "mbarrier_extended" if policy.id == "nanosleep" => 2,
+            "cp_async_copy"
+                if policy
+                    .cp_async_copy
+                    .as_ref()
+                    .is_some_and(|copy| copy.source_size == CpAsyncSourceSize::Runtime) =>
+            {
+                2
+            }
+            "cluster_memory" if policy.id == "map_shared_rank" => 2,
+            "scalar_math"
+                if policy.scalar_math.as_ref().is_some_and(|sm| {
+                    matches!(
+                        sm.operation,
+                        ScalarMathOperation::Sin
+                            | ScalarMathOperation::Cos
+                            | ScalarMathOperation::Ex2
+                            | ScalarMathOperation::Lg2
+                            | ScalarMathOperation::Rsqrt
+                    )
+                }) =>
+            {
+                0
+            }
+            _ => 1,
+        };
+        ensure!(
+            matching_selections.len() == expected_selection_count,
+            "{} expected PTX {:?} does not agree with its closed imported selection set",
+            policy.id,
+            policy.expected_ptx
+        );
+        for selection in matching_selections {
+            validate_selected_target_predicates(policy, selection)?;
+        }
+    }
+    Ok(())
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/targets.rs b/crates/cuda-intrinsics-gen/src/resolve/targets.rs
new file mode 100644
index 0000000000..9289264d70
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/targets.rs
@@ -0,0 +1,852 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    CatalogHardwareAlternative, CatalogHardwareTarget, CatalogTargetAlternative,
+    CatalogTargetContract, CatalogTargetRequirement, ClcOperation, ExecutionControlOperation,
+    IntrinsicBackend, LdmatrixElement, LdmatrixShape, OverlayIntrinsic, PtxVersion,
+    SparseMmaAccumulator, TargetContract, TargetSelectorBinding, Tcgen05Operation, TmaOperation,
+};
+use anyhow::{Context, Result, bail, ensure};
+
+use super::families::*;
+
+pub(super) fn validate_selected_target_predicates(
+    policy: &OverlayIntrinsic,
+    selection: &crate::model::ImportedSelection,
+) -> Result<()> {
+    if policy.family == "wgmma_control" {
+        ensure!(
+            selection.predicates == ["Subtarget->getPTXVersion() >= 80", "hasSM90a"]
+                && parse_ptx_version(&policy.minimum_ptx, &policy.id)?.encoded() == 80
+                && parse_hardware_target(policy)?
+                    == CatalogHardwareTarget::AnyOf {
+                        alternatives: vec![CatalogHardwareAlternative::ExactArchitecture {
+                            sm: 90,
+                        }],
+                    },
+            "{} WGMMA-control selection must retain the PTX 8.0 and sm_90a gates",
+            policy.id
+        );
+        return Ok(());
+    }
+    if policy.family == "register_control" {
+        let operation = ExecutionControlOperation::from_catalog_id(&policy.id)
+            .with_context(|| format!("{} has no closed register-control operation", policy.id))?;
+        ensure!(
+            matches!(
+                operation,
+                ExecutionControlOperation::SetMaxNRegInc | ExecutionControlOperation::SetMaxNRegDec
+            ) && selection.predicates == ["Subtarget->hasSetMaxNRegSupport()"]
+                && parse_ptx_version(&policy.minimum_ptx, &policy.id)?.encoded() == 80
+                && policy.minimum_sm.is_none()
+                && policy.targets == TENSOR_MAP_REPLACE_TARGETS,
+            "{} setmaxnreg selection must retain the helper predicate and reviewed PTX 8.0 target matrix",
+            policy.id
+        );
+        return Ok(());
+    }
+
+    let mma_family = matches!(policy.family.as_str(), "register_mma" | "sparse_mma");
+    let tcgen05_mma = policy
+        .tcgen05
+        .as_ref()
+        .and_then(|tcgen05| tcgen05.mma.as_ref());
+    let mut imported_ptx: Option<u16> = None;
+    let mut imported_sm: Option<u16> = None;
+    let mut has_dot_instructions = false;
+    let mut has_clc_multicast_support = false;
+    let mut has_tma_blackwell_support = false;
+    let mut has_tcgen05_support = false;
+    let mut has_tcgen05_shift_support = false;
+    let mut has_tcgen05_mma_i8_support = false;
+    let mut has_ldstmatrix_blackwell_support = false;
+    let mut has_mma_block_scale_support = false;
+    let mut has_redux_sync_f32_support = false;
+    for predicate in &selection.predicates {
+        if let Some(value) = predicate.strip_prefix("Subtarget->getPTXVersion() >= ") {
+            let value = value.parse::<u16>().with_context(|| {
+                format!("{} has malformed PTX predicate {predicate:?}", policy.id)
+            })?;
+            ensure!(
+                imported_ptx.is_none() || mma_family,
+                "{} has duplicate PTX predicates",
+                policy.id
+            );
+            imported_ptx = Some(imported_ptx.unwrap_or_default().max(value));
+        } else if let Some(value) = predicate.strip_prefix("Subtarget->getSmVersion() >= ") {
+            let value = value.parse::<u16>().with_context(|| {
+                format!("{} has malformed SM predicate {predicate:?}", policy.id)
+            })?;
+            ensure!(
+                imported_sm.is_none() || mma_family,
+                "{} has duplicate SM predicates",
+                policy.id
+            );
+            imported_sm = Some(imported_sm.unwrap_or_default().max(value));
+        } else if predicate == "hasDotInstructions" {
+            ensure!(
+                policy.family == "dotprod",
+                "{} selected instruction uses dot-product target gating outside the dotprod family",
+                policy.id
+            );
+            ensure!(
+                !has_dot_instructions && imported_ptx.is_none() && imported_sm.is_none(),
+                "{} has duplicate or conflicting dot-product target predicates",
+                policy.id
+            );
+            has_dot_instructions = true;
+            imported_ptx = Some(50);
+            imported_sm = Some(61);
+        } else if predicate == "Subtarget->hasClusterLaunchControlTryCancelMulticastSupport()" {
+            ensure!(
+                policy.family == "clc"
+                    && policy
+                        .clc
+                        .as_ref()
+                        .is_some_and(|clc| { clc.operation == ClcOperation::TryCancelMulticast }),
+                "{} uses the CLC multicast target predicate outside that operation",
+                policy.id
+            );
+            ensure!(
+                !has_clc_multicast_support
+                    && imported_ptx.is_none()
+                    && imported_sm.is_none()
+                    && !has_dot_instructions,
+                "{} has duplicate or conflicting CLC multicast target predicates",
+                policy.id
+            );
+            has_clc_multicast_support = true;
+        } else if predicate == "Subtarget->hasTMABlackwellSupport()" {
+            ensure!(
+                policy.family == "tma"
+                    && policy.tma.as_ref().is_some_and(|tma| {
+                        matches!(
+                            tma.operation,
+                            TmaOperation::G2sTile2dMulticastCg2
+                                | TmaOperation::PrefetchTileGather4TwoDimensional
+                                | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint
+                        )
+                    }),
+                "{} uses the Blackwell TMA target predicate outside the cta_group::2 operation",
+                policy.id
+            );
+            ensure!(
+                !has_tma_blackwell_support
+                    && imported_ptx.is_none()
+                    && imported_sm.is_none()
+                    && !has_dot_instructions
+                    && !has_clc_multicast_support,
+                "{} has duplicate or conflicting Blackwell TMA target predicates",
+                policy.id
+            );
+            has_tma_blackwell_support = true;
+        } else if predicate == "Subtarget->hasTcgen05InstSupport()" {
+            ensure!(
+                policy.family == "tcgen05" && policy.tcgen05.is_some(),
+                "{} uses the tcgen05 target predicate outside that family",
+                policy.id
+            );
+            ensure!(
+                !has_tcgen05_support
+                    && !has_tcgen05_shift_support
+                    && !has_tcgen05_mma_i8_support
+                    && imported_ptx.is_none()
+                    && imported_sm.is_none()
+                    && !has_dot_instructions
+                    && !has_clc_multicast_support
+                    && !has_tma_blackwell_support,
+                "{} has duplicate or conflicting tcgen05 target predicates",
+                policy.id
+            );
+            has_tcgen05_support = true;
+        } else if predicate == "Subtarget->hasTcgen05MMAI8Kind()" {
+            ensure!(
+                tcgen05_mma.is_some() && selection.asm.contains(".kind::i8."),
+                "{} uses the tcgen05 I8 predicate outside an I8 MMA selection",
+                policy.id
+            );
+            ensure!(
+                !has_tcgen05_mma_i8_support
+                    && !has_tcgen05_support
+                    && !has_tcgen05_shift_support
+                    && imported_ptx.is_none()
+                    && imported_sm.is_none()
+                    && !has_dot_instructions
+                    && !has_clc_multicast_support
+                    && !has_tma_blackwell_support,
+                "{} has duplicate or conflicting tcgen05 I8 predicates",
+                policy.id
+            );
+            has_tcgen05_mma_i8_support = true;
+        } else if predicate == "Subtarget->hasTcgen05ShiftSupport()" {
+            ensure!(
+                policy.family == "tcgen05"
+                    && policy.tcgen05.as_ref().is_some_and(|tcgen05| {
+                        matches!(
+                            tcgen05.operation,
+                            Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2
+                        )
+                    }),
+                "{} uses the tcgen05 shift target predicate outside a shift operation",
+                policy.id
+            );
+            ensure!(
+                !has_tcgen05_shift_support
+                    && !has_tcgen05_support
+                    && !has_tcgen05_mma_i8_support
+                    && imported_ptx.is_none()
+                    && imported_sm.is_none()
+                    && !has_dot_instructions
+                    && !has_clc_multicast_support
+                    && !has_tma_blackwell_support,
+                "{} has duplicate or conflicting tcgen05 shift target predicates",
+                policy.id
+            );
+            has_tcgen05_shift_support = true;
+        } else if predicate == "Subtarget->hasLdStmatrixBlackwellSupport()" {
+            ensure!(
+                policy.family == "ldmatrix"
+                    && policy.ldmatrix_variant.as_ref().is_some_and(|variant| {
+                        variant.shape != LdmatrixShape::M8n8
+                            && variant.element != LdmatrixElement::B16
+                    }),
+                "{} uses the Blackwell ld/stmatrix predicate outside a Blackwell ldmatrix variant",
+                policy.id
+            );
+            ensure!(
+                !has_ldstmatrix_blackwell_support
+                    && imported_ptx.is_none()
+                    && imported_sm.is_none()
+                    && !has_dot_instructions
+                    && !has_clc_multicast_support
+                    && !has_tma_blackwell_support
+                    && !has_tcgen05_support
+                    && !has_tcgen05_shift_support,
+                "{} has duplicate or conflicting Blackwell ldmatrix target predicates",
+                policy.id
+            );
+            has_ldstmatrix_blackwell_support = true;
+        } else if predicate == "Subtarget->hasMMABlockScale()" {
+            ensure!(
+                matches!(policy.family.as_str(), "register_mma" | "sparse_mma")
+                    && (policy.register_mma.is_some() || policy.sparse_mma.is_some()),
+                "{} uses the MMA block-scale target predicate outside a closed MMA family",
+                policy.id
+            );
+            ensure!(
+                !has_mma_block_scale_support
+                    && imported_ptx.is_none()
+                    && imported_sm.is_none()
+                    && !has_dot_instructions
+                    && !has_clc_multicast_support
+                    && !has_tma_blackwell_support
+                    && !has_tcgen05_support
+                    && !has_tcgen05_shift_support
+                    && !has_ldstmatrix_blackwell_support,
+                "{} has duplicate or conflicting MMA block-scale target predicates",
+                policy.id
+            );
+            has_mma_block_scale_support = true;
+        } else if predicate == "Subtarget->hasReduxSyncF32()" {
+            ensure!(
+                policy.family == "redux"
+                    && policy
+                        .redux
+                        .as_ref()
+                        .is_some_and(|redux| redux_recipe(redux.operation).value_type == "f32"),
+                "{} uses the f32 redux target predicate outside an f32 redux operation",
+                policy.id
+            );
+            ensure!(
+                !has_redux_sync_f32_support && imported_ptx.is_none() && imported_sm.is_none(),
+                "{} has duplicate or conflicting f32 redux target predicates",
+                policy.id
+            );
+            has_redux_sync_f32_support = true;
+        } else {
+            bail!(
+                "{} selected instruction has unsupported target predicate {predicate:?}; target gates must fail closed",
+                policy.id
+            );
+        }
+    }
+    let overlay_ptx = parse_ptx_version(&policy.minimum_ptx, &policy.id)?.encoded();
+    if let Some(mma) = tcgen05_mma {
+        let i8_selection = selection.asm.contains(".kind::i8.");
+        ensure!(
+            selection.predicates.len() == 1
+                && ((i8_selection && has_tcgen05_mma_i8_support && !has_tcgen05_support)
+                    || (!i8_selection && has_tcgen05_support && !has_tcgen05_mma_i8_support))
+                && !has_tcgen05_shift_support,
+            "{} tcgen05 MMA selection does not retain its exact kind predicate",
+            policy.id
+        );
+        let contracts = expected_tcgen05_mma_target_contracts(IntrinsicBackend::LlvmNvptx);
+        let expected_target = if let Some(fixed) = mma.fixed_selectors {
+            resolve_target_contract(
+                "tcgen05 MMA selected predicate",
+                &[TargetSelectorBinding {
+                    name: "kind".into(),
+                    value: tcgen05_mma_kind_name(fixed.kind).into(),
+                }],
+                &contracts,
+            )?
+        } else {
+            resolve_target_contracts("tcgen05 MMA selected predicate", &contracts)?
+        };
+        ensure!(
+            mma.llvm_target == expected_target,
+            "{} tcgen05 MMA predicate does not map to its closed LLVM target matrix",
+            policy.id
+        );
+        return Ok(());
+    }
+    if has_mma_block_scale_support {
+        let (minimum_ptx_matches, target_matches) = match policy.family.as_str() {
+            "register_mma" => (
+                overlay_ptx == 87,
+                policy.targets == "sm_120a|sm_120f|sm_121a|sm_121f" && policy.minimum_sm.is_none(),
+            ),
+            "sparse_mma" => (
+                overlay_ptx == 87,
+                policy.minimum_sm.is_none()
+                    && policy.sparse_mma.as_ref().is_some_and(|mma| {
+                        policy.targets
+                            == match mma.accumulator {
+                                SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 => {
+                                    SPARSE_MMA_F8F6F4_TARGETS
+                                }
+                                SparseMmaAccumulator::S32 => return false,
+                            }
+                    }),
+            ),
+            _ => (false, false),
+        };
+        ensure!(
+            minimum_ptx_matches && target_matches,
+            "{} MMA block-scale predicate requires its reviewed Blackwell target matrix",
+            policy.id
+        );
+        return Ok(());
+    }
+    if has_redux_sync_f32_support {
+        ensure!(
+            selection.predicates.len() == 1
+                && overlay_ptx == 86
+                && policy.targets == REDUX_F32_TARGETS
+                && policy.minimum_sm.is_none(),
+            "{} f32 redux selection must carry only the hasReduxSyncF32 predicate and its reviewed Blackwell target matrix",
+            policy.id
+        );
+        return Ok(());
+    }
+    // MMA uses reviewed inline PTX. Its imported predicates gate LLVM's typed
+    // selection, while the closed recipe and terminal evidence set the native
+    // PTX floor.
+    if mma_family {
+        return Ok(());
+    }
+    if let Some(imported_ptx) = imported_ptx {
+        ensure!(
+            overlay_ptx == imported_ptx,
+            "{} minimum PTX {} disagrees with selected instruction predicate PTX {}",
+            policy.id,
+            policy.minimum_ptx,
+            format_args!("{}.{}", imported_ptx / 10, imported_ptx % 10)
+        );
+    }
+    if let Some(imported_sm) = imported_sm {
+        if let Some(packed) = &policy.packed_alu {
+            ensure!(
+                packed.native_minimum_sm == imported_sm,
+                "{} native minimum SM {} disagrees with selected instruction predicate sm_{}",
+                policy.id,
+                packed.native_minimum_sm,
+                imported_sm
+            );
+        } else {
+            let overlay_target = parse_hardware_target(policy)?;
+            let target_matches = overlay_target
+                == CatalogHardwareTarget::AnyOf {
+                    alternatives: vec![CatalogHardwareAlternative::MinimumSm { sm: imported_sm }],
+                };
+            ensure!(
+                target_matches,
+                "{} minimum SM {:?} disagrees with selected instruction predicate sm_{}",
+                policy.id,
+                policy.minimum_sm,
+                imported_sm
+            );
+        }
+    }
+    if policy.family == "ldmatrix" {
+        if policy
+            .ldmatrix_variant
+            .as_ref()
+            .is_some_and(|variant| variant.shape == LdmatrixShape::M8n8)
+        {
+            ensure!(
+                imported_ptx.is_some() && imported_sm.is_some() && selection.predicates.len() == 2,
+                "{} classic ldmatrix selection must carry exactly its PTX and SM predicates",
+                policy.id
+            );
+        } else {
+            ensure!(
+                has_ldstmatrix_blackwell_support
+                    && selection.predicates.len() == 1
+                    && policy.targets == BLACKWELL_LDMATRIX_LLVM_TARGETS,
+                "{} Blackwell ldmatrix selection must retain its helper predicate and reviewed exact targets",
+                policy.id
+            );
+        }
+    } else if policy.family == "dotprod" {
+        ensure!(
+            has_dot_instructions && selection.predicates.len() == 1,
+            "{} dotprod selection must carry only the hasDotInstructions predicate",
+            policy.id
+        );
+    } else if policy.family == "clc" {
+        match policy.clc.as_ref().map(|clc| clc.operation) {
+            Some(ClcOperation::TryCancel) => ensure!(
+                imported_ptx.is_some() && imported_sm.is_some() && selection.predicates.len() == 2,
+                "{} selection must carry exactly its PTX and SM predicates",
+                policy.id
+            ),
+            Some(ClcOperation::TryCancelMulticast) => ensure!(
+                has_clc_multicast_support
+                    && selection.predicates.len() == 1
+                    && parse_hardware_target(policy)?
+                        == CatalogHardwareTarget::AnyOf {
+                            alternatives: vec![
+                                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+                                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+                                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+                                CatalogHardwareAlternative::ExactArchitecture { sm: 120 },
+                                CatalogHardwareAlternative::ExactArchitecture { sm: 121 },
+                            ],
+                        },
+                "{} multicast target predicate must map to the reviewed exact architectures",
+                policy.id
+            ),
+            _ => bail!(
+                "{} query operation unexpectedly has an instruction selection",
+                policy.id
+            ),
+        }
+    } else if policy.family == "tma" {
+        if policy.tma.as_ref().is_some_and(|tma| {
+            matches!(
+                tma.operation,
+                TmaOperation::G2sTile2dMulticastCg2
+                    | TmaOperation::PrefetchTileGather4TwoDimensional
+                    | TmaOperation::PrefetchTileGather4TwoDimensionalCacheHint
+            )
+        }) {
+            ensure!(
+                has_tma_blackwell_support
+                    && selection.predicates.len() == 1
+                    && parse_hardware_target(policy)?
+                        == CatalogHardwareTarget::AnyOf {
+                            alternatives: vec![
+                                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+                                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+                                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+                            ],
+                        },
+                "{} Blackwell TMA predicate must map to the reviewed exact architectures",
+                policy.id
+            );
+        } else {
+            ensure!(
+                imported_ptx.is_some() && imported_sm.is_some() && selection.predicates.len() == 2,
+                "{} TMA selection must carry exactly its PTX and SM predicates",
+                policy.id
+            );
+        }
+    } else if policy.family == "tcgen05" {
+        let shift = policy.tcgen05.as_ref().is_some_and(|tcgen05| {
+            matches!(
+                tcgen05.operation,
+                Tcgen05Operation::ShiftDown | Tcgen05Operation::ShiftDownCg2
+            )
+        });
+        ensure!(
+            ((shift && has_tcgen05_shift_support && !has_tcgen05_support)
+                || (!shift && has_tcgen05_support && !has_tcgen05_shift_support))
+                && selection.predicates.len() == 1
+                && parse_hardware_target(policy)?
+                    == CatalogHardwareTarget::AnyOf {
+                        alternatives: vec![
+                            CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                            CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+                            CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+                            CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+                        ],
+                    },
+            "{} tcgen05 selection must use the reviewed accelerated architectures",
+            policy.id
+        );
+    } else if matches!(
+        policy.family.as_str(),
+        "vote"
+            | "active_mask"
+            | "warp_match"
+            | "elect"
+            | "warp_barrier"
+            | "warp_shuffle"
+            | "cp_async_copy"
+            | "cp_async_control"
+            | "mbarrier_basic"
+            | "cluster_barrier"
+            | "scalar_conversion"
+            | "grid_dependency"
+    ) {
+        ensure!(
+            imported_ptx.is_some() && imported_sm.is_some() && selection.predicates.len() == 2,
+            "{} selection must carry exactly its PTX and SM predicates",
+            policy.id
+        );
+    }
+    Ok(())
+}
+
+pub(super) fn parse_ptx_version(value: &str, intrinsic_id: &str) -> Result<PtxVersion> {
+    value
+        .parse()
+        .map_err(|reason: String| anyhow::anyhow!("{intrinsic_id} minimum_ptx {value:?}: {reason}"))
+}
+
+pub(super) fn parse_hardware_target(policy: &OverlayIntrinsic) -> Result<CatalogHardwareTarget> {
+    parse_hardware_target_fields(&policy.id, &policy.targets, policy.minimum_sm.as_deref())
+}
+
+/// Resolve every selector contract without merging target sets.
+pub(crate) fn resolve_target_contracts(
+    intrinsic_id: &str,
+    contracts: &[TargetContract],
+) -> Result<CatalogTargetRequirement> {
+    ensure!(
+        !contracts.is_empty(),
+        "{intrinsic_id} has no reviewed target contracts"
+    );
+
+    let expected_selector_names = contracts[0]
+        .selectors
+        .iter()
+        .map(|selector| selector.name.as_str())
+        .collect::<Vec<_>>();
+    let mut resolved_contracts = Vec::with_capacity(contracts.len());
+    for contract in contracts {
+        validate_selector_bindings(
+            intrinsic_id,
+            "target-contract selectors",
+            &contract.selectors,
+        )?;
+        ensure!(
+            contract
+                .selectors
+                .iter()
+                .map(|selector| selector.name.as_str())
+                .eq(expected_selector_names.iter().copied()),
+            "{intrinsic_id} target contracts must use one closed selector schema"
+        );
+        ensure!(
+            !contract.alternatives.is_empty(),
+            "{intrinsic_id} target contract {:?} has no alternatives",
+            contract.selectors
+        );
+
+        let alternatives = contract
+            .alternatives
+            .iter()
+            .map(|alternative| {
+                Ok(CatalogTargetAlternative {
+                    minimum_ptx: parse_ptx_version(&alternative.minimum_ptx, intrinsic_id)?,
+                    hardware: parse_target_contract_hardware(intrinsic_id, &alternative.target)?,
+                })
+            })
+            .collect::<Result<Vec<_>>>()?;
+        ensure!(
+            alternatives
+                .windows(2)
+                .all(|pair| target_hardware_sort_key(pair[0].hardware)
+                    < target_hardware_sort_key(pair[1].hardware)),
+            "{intrinsic_id} target contract {:?} alternatives must have unique, sorted hardware targets",
+            contract.selectors
+        );
+        let minimum_count = alternatives
+            .iter()
+            .filter(|alternative| {
+                matches!(
+                    alternative.hardware,
+                    CatalogHardwareAlternative::MinimumSm { .. }
+                )
+            })
+            .count();
+        ensure!(
+            minimum_count == 0 || alternatives.len() == 1,
+            "{intrinsic_id} target contract {:?} cannot mix a minimum-SM range with other alternatives",
+            contract.selectors
+        );
+        resolved_contracts.push(CatalogTargetContract {
+            selectors: contract.selectors.clone(),
+            alternatives,
+        });
+    }
+    ensure!(
+        resolved_contracts
+            .windows(2)
+            .all(|pair| pair[0].selectors < pair[1].selectors),
+        "{intrinsic_id} target contracts must have unique, sorted selector bindings"
+    );
+
+    let minimum_ptx = resolved_contracts
+        .iter()
+        .flat_map(|contract| contract.alternatives.iter())
+        .map(|alternative| alternative.minimum_ptx)
+        .min()
+        .unwrap();
+    Ok(CatalogTargetRequirement {
+        minimum_ptx,
+        hardware: CatalogHardwareTarget::TargetMatrix {
+            contracts: resolved_contracts,
+        },
+    })
+}
+
+/// Resolve one fixed selector tuple from a closed target matrix.
+pub(crate) fn resolve_target_contract(
+    intrinsic_id: &str,
+    selected: &[TargetSelectorBinding],
+    contracts: &[TargetContract],
+) -> Result<CatalogTargetRequirement> {
+    validate_selector_bindings(intrinsic_id, "selected target selectors", selected)?;
+    let resolved = resolve_target_contracts(intrinsic_id, contracts)?;
+    let CatalogHardwareTarget::TargetMatrix { contracts } = resolved.hardware else {
+        unreachable!("target-contract resolution always returns a matrix")
+    };
+
+    let matching = contracts
+        .into_iter()
+        .filter(|contract| contract.selectors == selected)
+        .collect::<Vec<_>>();
+    ensure!(
+        matching.len() == 1,
+        "{intrinsic_id} selected target selectors {:?} must match exactly one reviewed contract",
+        selected
+    );
+    let contract = matching.into_iter().next().unwrap();
+    let minimum_ptx = contract
+        .alternatives
+        .iter()
+        .map(|alternative| alternative.minimum_ptx)
+        .min()
+        .unwrap();
+    Ok(CatalogTargetRequirement {
+        minimum_ptx,
+        hardware: CatalogHardwareTarget::TargetMatrix {
+            contracts: vec![contract],
+        },
+    })
+}
+
+pub(super) fn validate_selector_bindings(
+    intrinsic_id: &str,
+    label: &str,
+    selectors: &[TargetSelectorBinding],
+) -> Result<()> {
+    for selector in selectors {
+        ensure!(
+            is_target_selector_token(&selector.name) && is_target_selector_token(&selector.value),
+            "{intrinsic_id} {label} must use lowercase snake-case names and values"
+        );
+    }
+    ensure!(
+        selectors.windows(2).all(|pair| pair[0].name < pair[1].name),
+        "{intrinsic_id} {label} must have unique, sorted names"
+    );
+    Ok(())
+}
+
+pub(super) fn is_target_selector_token(value: &str) -> bool {
+    value
+        .bytes()
+        .next()
+        .is_some_and(|byte| byte.is_ascii_lowercase())
+        && value
+            .bytes()
+            .all(|byte| byte.is_ascii_lowercase() || byte.is_ascii_digit() || byte == b'_')
+        && !value.ends_with('_')
+        && !value.contains("__")
+}
+
+pub(super) fn parse_target_contract_hardware(
+    intrinsic_id: &str,
+    target: &str,
+) -> Result<CatalogHardwareAlternative> {
+    if let Some(minimum) = target.strip_suffix('+') {
+        let sm = parse_sm_spelling(intrinsic_id, "target contract", minimum, None)?;
+        return Ok(CatalogHardwareAlternative::MinimumSm { sm });
+    }
+    parse_exact_hardware_alternative(intrinsic_id, target)
+}
+
+pub(super) fn target_hardware_sort_key(hardware: CatalogHardwareAlternative) -> (u16, u8) {
+    match hardware {
+        CatalogHardwareAlternative::MinimumSm { sm } => (sm, 0),
+        CatalogHardwareAlternative::ExactArchitecture { sm } => (sm, 1),
+        CatalogHardwareAlternative::FamilyTarget { sm } => (sm, 2),
+    }
+}
+
+pub(super) fn parse_hardware_target_fields(
+    intrinsic_id: &str,
+    targets: &str,
+    minimum_sm: Option<&str>,
+) -> Result<CatalogHardwareTarget> {
+    if targets == "all" {
+        let Some(minimum_sm) = minimum_sm else {
+            return Ok(CatalogHardwareTarget::All);
+        };
+        let sm = parse_sm_spelling(intrinsic_id, "minimum_sm", minimum_sm, None)?;
+        return Ok(CatalogHardwareTarget::AnyOf {
+            alternatives: vec![CatalogHardwareAlternative::MinimumSm { sm }],
+        });
+    }
+
+    if targets.contains('|') {
+        ensure!(
+            minimum_sm.is_none(),
+            "{} target alternatives {:?} cannot be combined with minimum_sm",
+            intrinsic_id,
+            targets
+        );
+        let spellings = targets.split('|').collect::<Vec<_>>();
+        ensure!(
+            spellings.len() >= 2,
+            "{} target alternatives must contain at least two targets",
+            intrinsic_id
+        );
+        ensure!(
+            spellings.windows(2).all(|pair| pair[0] < pair[1]),
+            "{} target alternatives must be unique and sorted",
+            intrinsic_id
+        );
+        return Ok(CatalogHardwareTarget::AnyOf {
+            alternatives: spellings
+                .into_iter()
+                .map(|spelling| parse_exact_hardware_alternative(intrinsic_id, spelling))
+                .collect::<Result<Vec<_>>>()?,
+        });
+    }
+
+    ensure!(
+        minimum_sm.is_none(),
+        "{} exact targets {:?} cannot be combined with minimum_sm",
+        intrinsic_id,
+        targets
+    );
+    Ok(CatalogHardwareTarget::AnyOf {
+        alternatives: vec![parse_exact_hardware_alternative(intrinsic_id, targets)?],
+    })
+}
+
+pub(super) fn parse_exact_hardware_alternative(
+    intrinsic_id: &str,
+    target: &str,
+) -> Result<CatalogHardwareAlternative> {
+    let suffix = target
+        .chars()
+        .last()
+        .filter(|suffix| matches!(suffix, 'a' | 'f'));
+    let Some(suffix) = suffix else {
+        bail!(
+            "{} targets {:?} must be `all`, exact `sm_Na`, or family `sm_Nf`",
+            intrinsic_id,
+            target
+        );
+    };
+    let sm = parse_sm_spelling(intrinsic_id, "targets", target, Some(suffix))?;
+    Ok(match suffix {
+        'a' => CatalogHardwareAlternative::ExactArchitecture { sm },
+        'f' => CatalogHardwareAlternative::FamilyTarget { sm },
+        _ => unreachable!(),
+    })
+}
+
+pub(super) fn parse_sm_spelling(
+    intrinsic_id: &str,
+    field: &str,
+    value: &str,
+    suffix: Option<char>,
+) -> Result<u16> {
+    let body = value.strip_prefix("sm_").with_context(|| {
+        format!("{intrinsic_id} {field} {value:?} must use canonical sm_NN spelling")
+    })?;
+    let digits = match suffix {
+        Some(suffix) => body.strip_suffix(suffix).with_context(|| {
+            format!("{intrinsic_id} {field} {value:?} has the wrong target suffix")
+        })?,
+        None => body,
+    };
+    ensure!(
+        matches!(digits.len(), 2 | 3) && digits.bytes().all(|byte| byte.is_ascii_digit()),
+        "{} {} {:?} must use canonical sm_NN{} spelling",
+        intrinsic_id,
+        field,
+        value,
+        suffix.map_or("", |suffix| if suffix == 'a' { "a" } else { "f" })
+    );
+    let sm: u16 = digits
+        .parse()
+        .with_context(|| format!("{intrinsic_id} {field} target is too large"))?;
+    let canonical = match suffix {
+        Some(suffix) => format!("sm_{sm}{suffix}"),
+        None => format!("sm_{sm}"),
+    };
+    ensure!(
+        sm > 0 && canonical == value,
+        "{} {} {:?} is not canonical",
+        intrinsic_id,
+        field,
+        value
+    );
+    Ok(sm)
+}
+
+pub(super) fn backend_target_requirement(
+    policy: &OverlayIntrinsic,
+    lowering: &crate::model::OverlayBackendLowering,
+) -> Result<CatalogTargetRequirement> {
+    if let Some(mma) = policy
+        .tcgen05
+        .as_ref()
+        .and_then(|tcgen05| tcgen05.mma.as_ref())
+    {
+        return Ok(match lowering.backend {
+            IntrinsicBackend::LlvmNvptx => mma.llvm_target.clone(),
+            IntrinsicBackend::LibNvvm => mma.libnvvm_target.clone(),
+        });
+    }
+    let minimum_ptx = lowering
+        .minimum_ptx
+        .as_deref()
+        .unwrap_or(&policy.minimum_ptx);
+    let targets = lowering.targets.as_deref().unwrap_or(&policy.targets);
+    let minimum_sm = lowering.minimum_sm.as_deref().or_else(|| {
+        if lowering.targets.is_none() {
+            policy.minimum_sm.as_deref()
+        } else {
+            None
+        }
+    });
+    Ok(CatalogTargetRequirement {
+        minimum_ptx: parse_ptx_version(minimum_ptx, &policy.id)?,
+        hardware: parse_hardware_target_fields(&policy.id, targets, minimum_sm)?,
+    })
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/evidence.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/evidence.rs
new file mode 100644
index 0000000000..c3ca1bead2
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/evidence.rs
@@ -0,0 +1,1129 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogHardwareAlternative, CatalogTargetAlternative,
+    DotProductOperation, DotProductSignedness, EvidenceArtifactKind, EvidenceFile, EvidenceRecord,
+    EvidenceStageKind, IntrinsicBackend, LdmatrixElement, LdmatrixLayout, LdmatrixMultiplicity,
+    LdmatrixShape, LdmatrixStateSpace, OverlayBackendLowering, PackedConversionDestinationFormat,
+    PackedConversionRounding, PackedConversionSaturation, RuntimeValidation,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+
+use super::fixtures::*;
+use crate::resolve::evidence::*;
+use crate::resolve::families::*;
+
+#[test]
+fn legacy_evidence_schema_is_unchanged_and_rejects_matrix_fields() {
+    let legacy = EvidenceFile {
+        schema: 5,
+        backend_profile: "legacy".into(),
+        backend_kind: None,
+        llvm_revision: "test".into(),
+        backend_version: "LLVM legacy test".into(),
+        backend_sha256: "0123456789abcdef".into(),
+        artifact_path: None,
+        build_id_prefix: None,
+        nvvm_ir_version: None,
+        debug_ir_version: None,
+        records: vec![evidence()],
+    };
+    let bytes = serde_json::to_vec(&legacy).unwrap();
+    assert_eq!(parse_evidence_bytes(&bytes, "legacy").unwrap(), legacy);
+
+    let mut with_matrix_field = serde_json::to_value(&legacy).unwrap();
+    with_matrix_field["matrices"] = serde_json::json!([]);
+    let error = parse_synthetic_evidence(&with_matrix_field).unwrap_err();
+    assert!(error.to_string().contains("legacy evidence"));
+    assert!(format!("{error:#}").contains("unknown field"));
+}
+
+#[test]
+fn compact_evidence_matrix_equals_explicit_records() {
+    let expanded = parse_synthetic_evidence(&synthetic_matrix_json()).unwrap();
+    let mut expected = vec![EvidenceRecord {
+        id: "synthetic_explicit".into(),
+        source: None,
+        source_record: Some("int_synthetic_explicit".into()),
+        llvm_symbol: Some("llvm.synthetic.explicit".into()),
+        resolved_llvm_symbol: None,
+        llvm_arguments: vec!["i32".into()],
+        llvm_results: vec!["i32".into()],
+        concrete_llvm_arguments: vec![],
+        concrete_llvm_results: vec![],
+        target_triple: "nvptx64-nvidia-cuda".into(),
+        gpu_target: "sm_80".into(),
+        ptx_feature: "+ptx71".into(),
+        status: "lowered".into(),
+        stages: vec![],
+        declaration_attributes_canonicalized: None,
+        runtime_validation: None,
+        expected_ptx: InstructionPattern {
+            mnemonic: "mma".into(),
+            modifiers: vec!["sync".into(), "explicit".into()],
+            operands: vec![OperandPattern::Register],
+        },
+    }];
+    expected.extend(["s8", "u8"].into_iter().map(|element| EvidenceRecord {
+        id: format!("synthetic_{element}"),
+        source: None,
+        source_record: Some(format!("int_synthetic_{element}")),
+        llvm_symbol: Some(format!("llvm.synthetic.{element}")),
+        resolved_llvm_symbol: None,
+        llvm_arguments: vec!["i32".into()],
+        llvm_results: vec!["i32".into()],
+        concrete_llvm_arguments: vec![],
+        concrete_llvm_results: vec![],
+        target_triple: "nvptx64-nvidia-cuda".into(),
+        gpu_target: "sm_80".into(),
+        ptx_feature: "+ptx71".into(),
+        status: "lowered".into(),
+        stages: vec![shared_matrix_stage()],
+        declaration_attributes_canonicalized: None,
+        runtime_validation: None,
+        expected_ptx: InstructionPattern {
+            mnemonic: "mma".into(),
+            modifiers: vec!["sync".into(), element.into()],
+            operands: vec![OperandPattern::Register],
+        },
+    }));
+    assert_eq!(expanded.schema, 6);
+    assert_eq!(expanded.records, expected);
+}
+
+#[test]
+fn matrix_identity_mutations_reach_existing_evidence_validation() {
+    let mut expanded = parse_synthetic_evidence(&policy_matrix_json()).unwrap();
+    let record = expanded.records.pop().unwrap();
+    validate_test_evidence(&policy(), record.clone()).unwrap();
+
+    let mut wrong_source = record.clone();
+    wrong_source.source_record = Some("int_nvvm_read_ptx_sreg_tid_y".into());
+    assert!(
+        validate_test_evidence(&policy(), wrong_source)
+            .unwrap_err()
+            .to_string()
+            .contains("source provenance mismatch")
+    );
+
+    let mut wrong_symbol = record.clone();
+    wrong_symbol.llvm_symbol = Some("llvm.nvvm.read.ptx.sreg.tid.y".into());
+    assert!(
+        validate_test_evidence(&policy(), wrong_symbol)
+            .unwrap_err()
+            .to_string()
+            .contains("signature mismatch")
+    );
+
+    let mut wrong_signature = record.clone();
+    wrong_signature.llvm_arguments.push("i32".into());
+    assert!(
+        validate_test_evidence(&policy(), wrong_signature)
+            .unwrap_err()
+            .to_string()
+            .contains("signature mismatch")
+    );
+
+    let mut wrong_ptx = record;
+    wrong_ptx.expected_ptx.modifiers.push("changed".into());
+    assert!(
+        validate_test_evidence(&policy(), wrong_ptx)
+            .unwrap_err()
+            .to_string()
+            .contains("PTX expectation mismatch")
+    );
+}
+
+#[test]
+fn evidence_matrix_rejects_bad_counts_fixtures_placeholders_and_collisions() {
+    let base = synthetic_matrix_json();
+
+    let mut bad_product = base.clone();
+    bad_product["matrices"][0]["product_count"] = 3.into();
+    assert_synthetic_evidence_error(&bad_product, "expands to 2 records");
+
+    let mut unknown_fixture = base.clone();
+    unknown_fixture["matrices"][0]["fixtures"][0] = "missing".into();
+    assert_synthetic_evidence_error(&unknown_fixture, "unknown fixture");
+
+    let mut uncovered_fixture = base.clone();
+    let extra = uncovered_fixture["fixtures"][0].clone();
+    uncovered_fixture["fixtures"]
+        .as_array_mut()
+        .unwrap()
+        .push(extra);
+    uncovered_fixture["fixtures"][1]["id"] = "unused".into();
+    assert_synthetic_evidence_error(&uncovered_fixture, "not referenced");
+
+    let mut wrong_coverage = base.clone();
+    wrong_coverage["fixtures"][0]["coverage_count"] = 1.into();
+    assert_synthetic_evidence_error(&wrong_coverage, "covers 2 expanded records");
+
+    let mut malformed = base.clone();
+    malformed["matrices"][0]["template"]["id"] = "synthetic_$element".into();
+    assert_synthetic_evidence_error(&malformed, "malformed matrix placeholder");
+
+    let mut unknown_axis = base.clone();
+    unknown_axis["matrices"][0]["template"]["id"] = "synthetic_${other}".into();
+    assert_synthetic_evidence_error(&unknown_axis, "unknown matrix axis");
+
+    let mut collision = base.clone();
+    collision["matrices"][0]["template"]["id"] = "synthetic".into();
+    assert_synthetic_evidence_error(&collision, "duplicate expanded evidence ID");
+}
+
+#[test]
+fn exact_operand_matrix_placeholders_fail_closed() {
+    let base = policy_matrix_json();
+
+    let mut unknown = base.clone();
+    unknown["matrices"][0]["template"]["expected_ptx"]["operands"][1]["value"] =
+        "%tid.${other}".into();
+    assert_synthetic_evidence_error(&unknown, "unknown matrix axis other");
+
+    let mut unterminated = base.clone();
+    unterminated["matrices"][0]["template"]["expected_ptx"]["operands"][1]["value"] =
+        "%tid.${axis".into();
+    assert_synthetic_evidence_error(&unterminated, "unterminated matrix placeholder");
+
+    let mut disallowed = base;
+    disallowed["matrices"][0]["template"]["expected_ptx"]["mnemonic"] = "mov.${axis}".into();
+    assert_synthetic_evidence_error(&disallowed, "PTX mnemonic cannot contain");
+}
+
+#[test]
+fn evidence_matrix_rejects_bad_axes_fixture_ids_and_stage_conflicts() {
+    let base = synthetic_matrix_json();
+
+    let mut no_fixture = base.clone();
+    no_fixture["matrices"][0]["fixtures"] = serde_json::json!([]);
+    assert_synthetic_evidence_error(&no_fixture, "references no shared fixture");
+
+    let mut empty_axes = base.clone();
+    empty_axes["matrices"][0]["axes"] = serde_json::json!([]);
+    assert_synthetic_evidence_error(&empty_axes, "has no axes");
+
+    let mut duplicate_axis = base.clone();
+    let axis = duplicate_axis["matrices"][0]["axes"][0].clone();
+    duplicate_axis["matrices"][0]["axes"]
+        .as_array_mut()
+        .unwrap()
+        .push(axis);
+    duplicate_axis["matrices"][0]["product_count"] = 4.into();
+    assert_synthetic_evidence_error(&duplicate_axis, "axes must be unique and sorted");
+
+    let mut empty_values = base.clone();
+    empty_values["matrices"][0]["axes"][0]["values"] = serde_json::json!([]);
+    assert_synthetic_evidence_error(&empty_values, "has no values");
+
+    let mut empty_axis_name = base.clone();
+    empty_axis_name["matrices"][0]["axes"][0]["name"] = "".into();
+    assert_synthetic_evidence_error(&empty_axis_name, "is not a safe token");
+
+    let mut empty_value = base.clone();
+    empty_value["matrices"][0]["axes"][0]["values"][0] = "".into();
+    assert_synthetic_evidence_error(&empty_value, "unsafe value");
+
+    let mut duplicate_value = base.clone();
+    duplicate_value["matrices"][0]["axes"][0]["values"][1] = "s8".into();
+    assert_synthetic_evidence_error(&duplicate_value, "duplicate value");
+
+    let mut unsafe_value = base.clone();
+    unsafe_value["matrices"][0]["axes"][0]["values"][0] = "../s8".into();
+    assert_synthetic_evidence_error(&unsafe_value, "unsafe value");
+
+    let mut unused_axis = base.clone();
+    unused_axis["matrices"][0]["axes"]
+        .as_array_mut()
+        .unwrap()
+        .push(serde_json::json!({"name": "other", "values": ["x"]}));
+    assert_synthetic_evidence_error(&unused_axis, "unused axis");
+
+    let mut duplicate_fixture = base.clone();
+    let fixture = duplicate_fixture["fixtures"][0].clone();
+    duplicate_fixture["fixtures"]
+        .as_array_mut()
+        .unwrap()
+        .push(fixture);
+    assert_synthetic_evidence_error(&duplicate_fixture, "duplicate evidence fixture ID");
+
+    let mut fixture_placeholder = base.clone();
+    fixture_placeholder["fixtures"][0]["stages"][0]["detail"] = "covers ${element}".into();
+    assert_synthetic_evidence_error(&fixture_placeholder, "cannot contain matrix placeholders");
+
+    let mut missing_symbol = base.clone();
+    missing_symbol["matrices"][0]["template"]
+        .as_object_mut()
+        .unwrap()
+        .remove("llvm_symbol");
+    assert_synthetic_evidence_error(&missing_symbol, "missing field `llvm_symbol`");
+
+    let mut conflicting_stage = base;
+    conflicting_stage["matrices"][0]["template"]["facts"]["stages"] =
+        conflicting_stage["fixtures"][0]["stages"].clone();
+    assert_synthetic_evidence_error(&conflicting_stage, "conflicting duplicate");
+}
+
+#[test]
+fn typed_evidence_accepts_direct_scalar_intrinsic_signatures() {
+    let policy = dot_product_policy(DotProductOperation::Dp2a, DotProductSignedness::Signed);
+    let mut record = dot_product_evidence(&policy);
+    validate_typed_llvm_evidence(&policy, &record).unwrap();
+
+    record.concrete_llvm_arguments.remove(2);
+    let error = validate_typed_llvm_evidence(&policy, &record).unwrap_err();
+    assert!(error.to_string().contains("resolved signature"));
+}
+
+#[test]
+fn typed_evidence_maps_cluster_shared_pointers_to_address_space_seven() {
+    let mut policy = dot_product_policy(DotProductOperation::Dp2a, DotProductSignedness::Signed);
+    let mut record = dot_product_evidence(&policy);
+    policy.llvm_arguments = vec![
+        "shared_cluster_ptr".into(),
+        "shared_ptr".into(),
+        "ptr".into(),
+    ];
+    record.concrete_llvm_arguments = vec![
+        "ptr addrspace(7)".into(),
+        "ptr addrspace(3)".into(),
+        "ptr".into(),
+    ];
+
+    validate_typed_llvm_evidence(&policy, &record).unwrap();
+}
+
+#[test]
+fn packed_conversion_evidence_separates_llvm_declaration_facts_from_libnvvm() {
+    for (destination, result) in [
+        (PackedConversionDestinationFormat::Bf16x2, "v2bf16"),
+        (PackedConversionDestinationFormat::F16x2, "v2f16"),
+    ] {
+        let policy = packed_conversion_policy(
+            destination,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::None,
+        );
+        let llvm = policy
+            .backend_lowerings
+            .iter()
+            .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+            .unwrap();
+        let mut record = packed_conversion_evidence(&policy);
+        record.status = "validated".into();
+        record.stages = [
+            EvidenceStageKind::DeclarationCanonicalization,
+            EvidenceStageKind::BackendCodegen,
+            EvidenceStageKind::PtxAssembly,
+        ]
+        .into_iter()
+        .map(|stage| {
+            evidence_stage(
+                stage,
+                BackendLoweringMechanism::TypedNvvm,
+                &["sm_80", "ptx70"],
+            )
+        })
+        .collect();
+        let assembly = record
+            .stages
+            .iter_mut()
+            .find(|stage| stage.stage == EvidenceStageKind::PtxAssembly)
+            .unwrap();
+        assembly.tool_path = Some("/usr/local/cuda/bin/ptxas".into());
+        assembly.tool_version = Some("CUDA 13.3 V13.3.33".into());
+        assembly.tool_sha256 =
+            Some("7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb".into());
+        assert_eq!(record.concrete_llvm_results, [result]);
+        validate_packed_conversion_backend_evidence(&policy, &record, llvm).unwrap();
+
+        let mut lowered = record.clone();
+        lowered.status = "lowered".into();
+        let error =
+            validate_packed_conversion_backend_evidence(&policy, &lowered, llvm).unwrap_err();
+        assert!(
+            error.to_string().contains("validated evidence status"),
+            "{error:#}"
+        );
+
+        for required in [
+            EvidenceStageKind::DeclarationCanonicalization,
+            EvidenceStageKind::BackendCodegen,
+            EvidenceStageKind::PtxAssembly,
+        ] {
+            let mut missing = record.clone();
+            missing.stages.retain(|stage| stage.stage != required);
+            let error =
+                validate_packed_conversion_backend_evidence(&policy, &missing, llvm).unwrap_err();
+            assert!(
+                error
+                    .to_string()
+                    .contains("successful auxiliary typed-NVVM"),
+                "{error:#}"
+            );
+
+            let mut failed = record.clone();
+            failed
+                .stages
+                .iter_mut()
+                .find(|stage| stage.stage == required)
+                .unwrap()
+                .outcome = "failed".into();
+            let error =
+                validate_packed_conversion_backend_evidence(&policy, &failed, llvm).unwrap_err();
+            assert!(
+                error
+                    .to_string()
+                    .contains("successful auxiliary typed-NVVM"),
+                "{error:#}"
+            );
+
+            let mut wrong_mechanism = record.clone();
+            wrong_mechanism
+                .stages
+                .iter_mut()
+                .find(|stage| stage.stage == required)
+                .unwrap()
+                .mechanism = Some(BackendLoweringMechanism::InlinePtx);
+            let error =
+                validate_packed_conversion_backend_evidence(&policy, &wrong_mechanism, llvm)
+                    .unwrap_err();
+            assert!(
+                error
+                    .to_string()
+                    .contains("successful auxiliary typed-NVVM"),
+                "{error:#}"
+            );
+        }
+
+        let mut missing_tool_identity = record.clone();
+        missing_tool_identity
+            .stages
+            .iter_mut()
+            .find(|stage| stage.stage == EvidenceStageKind::PtxAssembly)
+            .unwrap()
+            .tool_sha256 = None;
+        let error =
+            validate_packed_conversion_backend_evidence(&policy, &missing_tool_identity, llvm)
+                .unwrap_err();
+        assert!(
+            error.to_string().contains("exact tool identity"),
+            "{error:#}"
+        );
+
+        for stage_kind in [
+            EvidenceStageKind::BackendCodegen,
+            EvidenceStageKind::PtxAssembly,
+        ] {
+            let mut wrong_floor = record.clone();
+            wrong_floor
+                .stages
+                .iter_mut()
+                .find(|stage| stage.stage == stage_kind)
+                .unwrap()
+                .targets = vec!["sm_75".into(), "ptx70".into()];
+            let error = validate_packed_conversion_backend_evidence(&policy, &wrong_floor, llvm)
+                .unwrap_err();
+            assert!(
+                error.to_string().contains("catalog floor sm_80"),
+                "{error:#}"
+            );
+        }
+
+        record.declaration_attributes_canonicalized = None;
+        let error =
+            validate_packed_conversion_backend_evidence(&policy, &record, llvm).unwrap_err();
+        assert!(
+            error
+                .to_string()
+                .contains("canonical declaration attributes")
+        );
+    }
+
+    let policy = packed_conversion_policy(
+        PackedConversionDestinationFormat::Bf16x2,
+        PackedConversionRounding::NearestEven,
+        PackedConversionSaturation::None,
+    );
+    let libnvvm = policy
+        .backend_lowerings
+        .iter()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
+        .unwrap();
+    let mut record = packed_conversion_evidence(&policy);
+    record.concrete_llvm_arguments.clear();
+    record.concrete_llvm_results.clear();
+    record.declaration_attributes_canonicalized = None;
+    validate_packed_conversion_backend_evidence(&policy, &record, libnvvm).unwrap();
+
+    record.concrete_llvm_arguments = policy.llvm_arguments.clone();
+    let error = validate_packed_conversion_backend_evidence(&policy, &record, libnvvm).unwrap_err();
+    assert!(
+        error
+            .to_string()
+            .contains("must not claim typed LLVM support")
+    );
+
+    record.concrete_llvm_arguments.clear();
+    record.stages.push(evidence_stage(
+        EvidenceStageKind::BackendCodegen,
+        BackendLoweringMechanism::TypedNvvm,
+        &["sm_80", "ptx70"],
+    ));
+    let error = validate_packed_conversion_backend_evidence(&policy, &record, libnvvm).unwrap_err();
+    assert!(
+        error
+            .to_string()
+            .contains("must not claim typed LLVM support")
+    );
+}
+
+#[test]
+fn signature_and_evidence_mismatches_are_rejected() {
+    let mut imported = declaration();
+    imported.results = vec!["i64".into()];
+    assert!(
+        validate_imported_policy(&policy(), &imported)
+            .unwrap_err()
+            .to_string()
+            .contains("LLVM result signature mismatch")
+    );
+
+    let mut backend_evidence = evidence();
+    backend_evidence.llvm_results = vec!["i64".into()];
+    assert!(
+        validate_test_evidence(&policy(), backend_evidence)
+            .unwrap_err()
+            .to_string()
+            .contains("evidence signature mismatch")
+    );
+
+    let mut backend_evidence = evidence();
+    backend_evidence.expected_ptx = sreg_pattern("%tid.y");
+    assert!(
+        validate_test_evidence(&policy(), backend_evidence)
+            .unwrap_err()
+            .to_string()
+            .contains("evidence PTX expectation mismatch")
+    );
+}
+
+#[test]
+fn validated_llvm_evidence_requires_exact_ptxas_identity() {
+    let mut record = evidence();
+    record.status = "validated".into();
+    record.stages.push(crate::model::EvidenceStage {
+        targets: vec!["sm_75".into()],
+        representation: "probe PTX".into(),
+        stage: EvidenceStageKind::PtxAssembly,
+        mechanism: Some(BackendLoweringMechanism::TypedNvvm),
+        outcome: "succeeded".into(),
+        detail: "accepted".into(),
+        artifact_kind: None,
+        tool_path: Some("/usr/local/cuda/bin/ptxas".into()),
+        tool_version: Some("CUDA 13.3 V13.3.33".into()),
+        tool_sha256: Some(
+            "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb".into(),
+        ),
+    });
+    assert!(has_valid_ptx_assembly_stage(
+        &record,
+        BackendLoweringMechanism::TypedNvvm
+    ));
+
+    let stage = record.stages.last_mut().unwrap();
+    stage.tool_path = None;
+    assert!(!has_valid_ptx_assembly_stage(
+        &record,
+        BackendLoweringMechanism::TypedNvvm
+    ));
+    record.stages.clear();
+    assert!(!has_valid_ptx_assembly_stage(
+        &record,
+        BackendLoweringMechanism::TypedNvvm
+    ));
+}
+
+#[test]
+fn validated_libnvvm_evidence_requires_a_real_cubin_terminal() {
+    let mut record = evidence();
+    record.stages.push(crate::model::EvidenceStage {
+        targets: vec!["sm_90".into(), "ptx78".into()],
+        representation: "linked output".into(),
+        stage: EvidenceStageKind::DeviceLink,
+        mechanism: Some(BackendLoweringMechanism::InlinePtx),
+        outcome: "succeeded".into(),
+        detail: "test".into(),
+        artifact_kind: None,
+        tool_path: Some("/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33".into()),
+        tool_version: Some("V13.3.33".into()),
+        tool_sha256: Some(
+            "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8".into(),
+        ),
+    });
+    assert!(!has_valid_cubin_device_link_stage(
+        &record,
+        BackendLoweringMechanism::InlinePtx
+    ));
+    record.stages[0].artifact_kind = Some(EvidenceArtifactKind::Cubin);
+    assert!(has_valid_cubin_device_link_stage(
+        &record,
+        BackendLoweringMechanism::InlinePtx
+    ));
+}
+
+fn evidence_stage(
+    stage: EvidenceStageKind,
+    mechanism: BackendLoweringMechanism,
+    targets: &[&str],
+) -> crate::model::EvidenceStage {
+    crate::model::EvidenceStage {
+        targets: targets.iter().map(|target| (*target).into()).collect(),
+        representation: "test".into(),
+        stage,
+        mechanism: Some(mechanism),
+        outcome: "succeeded".into(),
+        detail: "test".into(),
+        artifact_kind: None,
+        tool_path: None,
+        tool_version: None,
+        tool_sha256: None,
+    }
+}
+
+#[test]
+fn backend_stage_targets_and_executed_status_are_monotonic() {
+    let mut target_policy = policy();
+    target_policy.minimum_ptx = "6.5".into();
+    target_policy.minimum_sm = Some("sm_75".into());
+    let lowering = crate::model::OverlayBackendLowering {
+        backend: IntrinsicBackend::LlvmNvptx,
+        mechanism: BackendLoweringMechanism::TypedNvvm,
+        evidence_profile: "test".into(),
+        targets: None,
+        minimum_ptx: None,
+        minimum_sm: None,
+    };
+    let mut record = evidence();
+    record.status = "validated".into();
+    record.runtime_validation = Some(RuntimeValidation::Unexecuted);
+    record.stages = vec![
+        evidence_stage(
+            EvidenceStageKind::BackendCodegen,
+            BackendLoweringMechanism::TypedNvvm,
+            &["sm_75", "ptx65"],
+        ),
+        evidence_stage(
+            EvidenceStageKind::PtxAssembly,
+            BackendLoweringMechanism::TypedNvvm,
+            &["sm_75", "ptx65"],
+        ),
+    ];
+    validate_selected_stage_targets(&target_policy, &record, &lowering).unwrap();
+
+    record.stages[0].targets = vec!["sm_75a".into(), "ptx65".into()];
+    assert!(validate_selected_stage_targets(&target_policy, &record, &lowering).is_err());
+    record.stages[0].targets = vec!["sm_75".into(), "ptx65".into()];
+
+    record.stages[1].targets = vec!["sm_80".into(), "ptx65".into()];
+    validate_selected_stage_targets(&target_policy, &record, &lowering).unwrap();
+
+    record.stages[1].targets = vec!["sm_90a".into(), "ptx65".into()];
+    validate_selected_stage_targets(&target_policy, &record, &lowering).unwrap();
+
+    record.stages[1].targets = vec!["sm_74".into(), "ptx65".into()];
+    assert!(
+        validate_selected_stage_targets(&target_policy, &record, &lowering)
+            .unwrap_err()
+            .to_string()
+            .contains("catalog floor sm_75")
+    );
+
+    record.stages[1].targets = vec!["sm_75".into(), "ptx65".into()];
+    record.status = "executed".into();
+    record.runtime_validation = Some(RuntimeValidation::Executed);
+    assert!(
+        validate_selected_stage_targets(&target_policy, &record, &lowering)
+            .unwrap_err()
+            .to_string()
+            .contains("runtime stage")
+    );
+}
+
+#[test]
+fn exact_and_family_evidence_targets_match_at_every_stage() {
+    let lowering = crate::model::OverlayBackendLowering {
+        backend: IntrinsicBackend::LlvmNvptx,
+        mechanism: BackendLoweringMechanism::InlinePtx,
+        evidence_profile: "test".into(),
+        targets: None,
+        minimum_ptx: None,
+        minimum_sm: None,
+    };
+
+    for (target, wrong_targets) in [
+        ("sm_120a", ["sm_120", "sm_120f", "sm_121a"]),
+        ("sm_120f", ["sm_120", "sm_120a", "sm_121f"]),
+    ] {
+        let mut target_policy = policy();
+        target_policy.minimum_ptx = "8.7".into();
+        target_policy.targets = target.into();
+        let mut record = evidence();
+        record.status = "validated".into();
+        record.runtime_validation = Some(RuntimeValidation::Unexecuted);
+        record.stages = vec![
+            evidence_stage(
+                EvidenceStageKind::BackendCodegen,
+                BackendLoweringMechanism::InlinePtx,
+                &[target, "ptx87"],
+            ),
+            evidence_stage(
+                EvidenceStageKind::PtxAssembly,
+                BackendLoweringMechanism::InlinePtx,
+                &[target, "ptx87"],
+            ),
+        ];
+        validate_selected_stage_targets(&target_policy, &record, &lowering).unwrap();
+
+        for wrong in wrong_targets {
+            record.stages[0].targets = vec![wrong.into(), "ptx87".into()];
+            let error = validate_selected_stage_targets(&target_policy, &record, &lowering)
+                .unwrap_err()
+                .to_string();
+            assert!(error.contains(target), "{error}");
+        }
+        record.stages[0].targets = vec![target.into(), "ptx87".into()];
+        for wrong in wrong_targets {
+            record.stages[1].targets = vec![wrong.into(), "ptx87".into()];
+            let error = validate_selected_stage_targets(&target_policy, &record, &lowering)
+                .unwrap_err()
+                .to_string();
+            assert!(error.contains(target), "{error}");
+        }
+    }
+}
+
+#[test]
+fn suffixed_evidence_target_spellings_are_normalized() {
+    for target in ["sm_120a", "compute_120a", "sm_120f", "compute_120f"] {
+        assert!(is_normalized_stage_target(target), "{target}");
+    }
+    for target in ["sm_120", "compute_120", "ptx87"] {
+        assert!(is_normalized_stage_target(target), "{target}");
+    }
+    for target in ["sm_0120a", "sm_120af", "sm_120x", "compute_120A"] {
+        assert!(!is_normalized_stage_target(target), "{target}");
+    }
+}
+
+#[test]
+fn libnvvm_stage_may_report_newer_ptx_than_the_native_instruction_floor() {
+    let mut target_policy = policy();
+    target_policy.minimum_ptx = "1.0".into();
+    target_policy.minimum_sm = None;
+    let lowering = crate::model::OverlayBackendLowering {
+        backend: IntrinsicBackend::LibNvvm,
+        mechanism: BackendLoweringMechanism::InlinePtx,
+        evidence_profile: "test".into(),
+        targets: None,
+        minimum_ptx: None,
+        minimum_sm: Some("sm_75".into()),
+    };
+    let mut record = evidence();
+    record.stages = vec![evidence_stage(
+        EvidenceStageKind::BackendCodegen,
+        BackendLoweringMechanism::InlinePtx,
+        &["sm_75", "ptx93"],
+    )];
+    validate_selected_stage_targets(&target_policy, &record, &lowering).unwrap();
+
+    record.stages[0].targets = vec!["sm_75".into(), "ptx09".into()];
+    assert!(
+        validate_selected_stage_targets(&target_policy, &record, &lowering)
+            .unwrap_err()
+            .to_string()
+            .contains("catalog floor sm_75 / PTX 1.0")
+    );
+
+    let llvm_lowering = crate::model::OverlayBackendLowering {
+        backend: IntrinsicBackend::LlvmNvptx,
+        mechanism: BackendLoweringMechanism::TypedNvvm,
+        evidence_profile: "test".into(),
+        targets: None,
+        minimum_ptx: Some("3.2".into()),
+        minimum_sm: Some("sm_20".into()),
+    };
+    record.stages = vec![evidence_stage(
+        EvidenceStageKind::BackendCodegen,
+        BackendLoweringMechanism::TypedNvvm,
+        &["sm_20", "ptx93"],
+    )];
+    assert!(
+        validate_selected_stage_targets(&target_policy, &record, &llvm_lowering)
+            .unwrap_err()
+            .to_string()
+            .contains("catalog floor sm_20 / PTX 3.2")
+    );
+}
+
+#[test]
+fn imported_selection_must_match_the_full_ptx_shape() {
+    let mut imported = declaration();
+    imported.selections[0].asm = "mov.u32 $d, %tid.xy;".into();
+    let error = validate_imported_policy(&policy(), &imported).unwrap_err();
+    assert!(error.to_string().contains("does not agree"));
+
+    imported.selections[0].asm = "mov.u32.relaxed $d, %tid.x;".into();
+    let error = validate_imported_policy(&policy(), &imported).unwrap_err();
+    assert!(error.to_string().contains("does not agree"));
+
+    imported.selections[0].asm = "mov.u32 $d, %tid.x;".into();
+    validate_imported_policy(&policy(), &imported).unwrap();
+}
+
+#[test]
+fn blackwell_ldmatrix_evidence_covers_every_target_with_its_effective_ptx_floor() {
+    let mut policy = policy();
+    policy.family = "ldmatrix".into();
+    policy.minimum_ptx = "8.6".into();
+    policy.minimum_sm = None;
+    policy.targets = BLACKWELL_LDMATRIX_LLVM_TARGETS.into();
+    policy.ldmatrix_variant = Some(crate::model::LdmatrixVariant {
+        shape: LdmatrixShape::M16n16,
+        multiplicity: LdmatrixMultiplicity::X1,
+        layout: LdmatrixLayout::Transposed,
+        element: LdmatrixElement::B8,
+        state_space: LdmatrixStateSpace::Shared,
+    });
+    let lowering = OverlayBackendLowering {
+        backend: IntrinsicBackend::LlvmNvptx,
+        mechanism: BackendLoweringMechanism::TypedNvvm,
+        evidence_profile: "test".into(),
+        targets: None,
+        minimum_ptx: None,
+        minimum_sm: None,
+    };
+    let mut record = evidence();
+    record.status = "validated".into();
+    record.stages.clear();
+    for (target, ptx) in [
+        ("sm_100a", "ptx86"),
+        ("sm_100f", "ptx88"),
+        ("sm_103a", "ptx88"),
+        ("sm_103f", "ptx88"),
+        ("sm_110a", "ptx90"),
+        ("sm_110f", "ptx90"),
+        ("sm_120a", "ptx87"),
+        ("sm_120f", "ptx88"),
+        ("sm_121a", "ptx88"),
+        ("sm_121f", "ptx88"),
+    ] {
+        record.stages.push(evidence_stage(
+            EvidenceStageKind::BackendCodegen,
+            BackendLoweringMechanism::TypedNvvm,
+            &[target, ptx],
+        ));
+        let mut assembly = evidence_stage(
+            EvidenceStageKind::PtxAssembly,
+            BackendLoweringMechanism::TypedNvvm,
+            &[target, ptx],
+        );
+        assembly.tool_path = Some("/tool/ptxas".into());
+        assembly.tool_version = Some("test".into());
+        assembly.tool_sha256 = Some("0".repeat(64));
+        record.stages.push(assembly);
+    }
+    validate_selected_stage_targets(&policy, &record, &lowering).unwrap();
+
+    record.stages.retain(|stage| {
+        !(stage.stage == EvidenceStageKind::PtxAssembly
+            && stage.targets.iter().any(|target| target == "sm_121f"))
+    });
+    assert!(
+        validate_selected_stage_targets(&policy, &record, &lowering)
+            .unwrap_err()
+            .to_string()
+            .contains("one structured stage for each")
+    );
+}
+
+#[test]
+fn paired_target_evidence_checks_backend_and_runtime_floors() {
+    let policy = policy();
+    let hardware = vec![
+        CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+        CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+    ];
+    let paired = vec![
+        CatalogTargetAlternative {
+            minimum_ptx: "8.6".parse().unwrap(),
+            hardware: hardware[0],
+        },
+        CatalogTargetAlternative {
+            minimum_ptx: "8.8".parse().unwrap(),
+            hardware: hardware[1],
+        },
+    ];
+    let llvm = OverlayBackendLowering {
+        backend: IntrinsicBackend::LlvmNvptx,
+        mechanism: BackendLoweringMechanism::InlinePtx,
+        evidence_profile: "test".into(),
+        targets: None,
+        minimum_ptx: None,
+        minimum_sm: None,
+    };
+    let mut llvm_record = evidence();
+    llvm_record.status = "validated".into();
+    llvm_record.stages.clear();
+    for (target, ptx) in [("sm_100a", "ptx86"), ("sm_103a", "ptx88")] {
+        llvm_record.stages.push(evidence_stage(
+            EvidenceStageKind::BackendCodegen,
+            llvm.mechanism,
+            &[target, ptx],
+        ));
+        let mut assembly = evidence_stage(
+            EvidenceStageKind::PtxAssembly,
+            llvm.mechanism,
+            &[target, ptx],
+        );
+        assembly.tool_path = Some("/tool/ptxas".into());
+        assembly.tool_version = Some("test".into());
+        assembly.tool_sha256 = Some("0".repeat(64));
+        llvm_record.stages.push(assembly);
+    }
+    validate_target_matrix_stage_targets(
+        &policy,
+        &llvm_record,
+        &llvm,
+        EvidenceStageKind::PtxAssembly,
+        &hardware,
+        86,
+        Some(&paired),
+    )
+    .unwrap();
+
+    let mut wrong_floor = llvm_record.clone();
+    wrong_floor
+        .stages
+        .iter_mut()
+        .find(|stage| {
+            stage.stage == EvidenceStageKind::BackendCodegen
+                && stage.targets.iter().any(|target| target == "sm_103a")
+        })
+        .unwrap()
+        .targets = vec!["sm_103a".into(), "ptx86".into()];
+    assert!(
+        validate_target_matrix_stage_targets(
+            &policy,
+            &wrong_floor,
+            &llvm,
+            EvidenceStageKind::PtxAssembly,
+            &hardware,
+            86,
+            Some(&paired),
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("wrong PTX floor")
+    );
+
+    let libnvvm = OverlayBackendLowering {
+        backend: IntrinsicBackend::LibNvvm,
+        ..llvm.clone()
+    };
+    let mut libnvvm_record = evidence();
+    libnvvm_record.status = "validated".into();
+    libnvvm_record.stages.clear();
+    for (target, ptx) in [("sm_100a", "ptx88"), ("sm_103a", "ptx90")] {
+        libnvvm_record.stages.push(evidence_stage(
+            EvidenceStageKind::BackendCodegen,
+            libnvvm.mechanism,
+            &[target, ptx],
+        ));
+        let mut assembly = evidence_stage(
+            EvidenceStageKind::PtxAssembly,
+            libnvvm.mechanism,
+            &[target, ptx],
+        );
+        assembly.tool_path = Some("/tool/ptxas".into());
+        assembly.tool_version = Some("test".into());
+        assembly.tool_sha256 = Some("0".repeat(64));
+        libnvvm_record.stages.push(assembly);
+        let mut link = evidence_stage(
+            EvidenceStageKind::DeviceLink,
+            libnvvm.mechanism,
+            &[target, ptx],
+        );
+        link.artifact_kind = Some(EvidenceArtifactKind::Cubin);
+        link.tool_path = Some("/tool/nvlink".into());
+        link.tool_version = Some("test".into());
+        link.tool_sha256 = Some("0".repeat(64));
+        libnvvm_record.stages.push(link);
+    }
+    validate_target_matrix_stage_targets(
+        &policy,
+        &libnvvm_record,
+        &libnvvm,
+        EvidenceStageKind::DeviceLink,
+        &hardware,
+        86,
+        Some(&paired),
+    )
+    .unwrap();
+
+    let mut executed = llvm_record;
+    executed.status = "executed".into();
+    executed.stages.push(evidence_stage(
+        EvidenceStageKind::Runtime,
+        llvm.mechanism,
+        &["sm_103a", "ptx88"],
+    ));
+    validate_target_matrix_stage_targets(
+        &policy,
+        &executed,
+        &llvm,
+        EvidenceStageKind::PtxAssembly,
+        &hardware,
+        86,
+        Some(&paired),
+    )
+    .unwrap();
+
+    let mut wrong_runtime_ptx = executed.clone();
+    wrong_runtime_ptx.stages.last_mut().unwrap().targets = vec!["sm_103a".into(), "ptx87".into()];
+    assert!(
+        validate_target_matrix_stage_targets(
+            &policy,
+            &wrong_runtime_ptx,
+            &llvm,
+            EvidenceStageKind::PtxAssembly,
+            &hardware,
+            86,
+            Some(&paired),
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("paired floor")
+    );
+
+    let mut wrong_runtime_hardware = executed;
+    wrong_runtime_hardware.stages.last_mut().unwrap().targets =
+        vec!["sm_110a".into(), "ptx90".into()];
+    assert!(
+        validate_target_matrix_stage_targets(
+            &policy,
+            &wrong_runtime_hardware,
+            &llvm,
+            EvidenceStageKind::PtxAssembly,
+            &hardware,
+            86,
+            Some(&paired),
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("outside its target matrix")
+    );
+}
+
+#[test]
+fn sparse_f8f6f4_f16_evidence_covers_every_target_and_floor() {
+    let policy = expand_sparse_mma_f8f6f4_f16_admission(&test_sparse_mma_f8f6f4_f16_admission())
+        .unwrap()
+        .remove(0);
+    let lowering = policy
+        .backend_lowerings
+        .iter()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+        .unwrap();
+    let mut record = evidence();
+    record.status = "validated".into();
+    record.stages.clear();
+    for (target, ptx) in [
+        ("sm_120a", "ptx87"),
+        ("sm_120f", "ptx88"),
+        ("sm_121a", "ptx88"),
+        ("sm_121f", "ptx88"),
+    ] {
+        record.stages.push(evidence_stage(
+            EvidenceStageKind::BackendCodegen,
+            BackendLoweringMechanism::InlinePtx,
+            &[target, ptx],
+        ));
+        let mut assembly = evidence_stage(
+            EvidenceStageKind::PtxAssembly,
+            BackendLoweringMechanism::InlinePtx,
+            &[target, ptx],
+        );
+        assembly.artifact_kind = Some(EvidenceArtifactKind::Cubin);
+        assembly.tool_path = Some("/tool/ptxas".into());
+        assembly.tool_version = Some("test".into());
+        assembly.tool_sha256 = Some("0".repeat(64));
+        record.stages.push(assembly);
+    }
+    validate_selected_stage_targets(&policy, &record, lowering).unwrap();
+
+    let valid = record.clone();
+    record.stages.retain(|stage| {
+        !(stage.stage == EvidenceStageKind::PtxAssembly
+            && stage.targets.iter().any(|target| target == "sm_121f"))
+    });
+    assert!(
+        validate_selected_stage_targets(&policy, &record, lowering)
+            .unwrap_err()
+            .to_string()
+            .contains("one structured stage for each")
+    );
+
+    record = valid;
+    record
+        .stages
+        .iter_mut()
+        .find(|stage| {
+            stage.stage == EvidenceStageKind::BackendCodegen
+                && stage.targets.iter().any(|target| target == "sm_120f")
+        })
+        .unwrap()
+        .targets = vec!["sm_120f".into(), "ptx87".into()];
+    assert!(
+        validate_selected_stage_targets(&policy, &record, lowering)
+            .unwrap_err()
+            .to_string()
+            .contains("wrong PTX floor")
+    );
+}
+
+#[test]
+fn non_blackwell_evidence_rejects_multiple_target_specific_stage_pairs() {
+    let policy = policy();
+    let lowering = OverlayBackendLowering {
+        backend: IntrinsicBackend::LlvmNvptx,
+        mechanism: BackendLoweringMechanism::TypedNvvm,
+        evidence_profile: "test".into(),
+        targets: None,
+        minimum_ptx: None,
+        minimum_sm: None,
+    };
+    let mut record = evidence();
+    record.stages = vec![
+        evidence_stage(
+            EvidenceStageKind::BackendCodegen,
+            BackendLoweringMechanism::TypedNvvm,
+            &["sm_20", "ptx20"],
+        ),
+        evidence_stage(
+            EvidenceStageKind::BackendCodegen,
+            BackendLoweringMechanism::TypedNvvm,
+            &["sm_21", "ptx20"],
+        ),
+    ];
+
+    assert!(
+        validate_selected_stage_targets(&policy, &record, &lowering)
+            .unwrap_err()
+            .to_string()
+            .contains("outside reviewed target-matrix evidence")
+    );
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/fixtures.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/fixtures.rs
new file mode 100644
index 0000000000..44e749fd0e
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/fixtures.rs
@@ -0,0 +1,1904 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    AbiLedgerEntry, AbiLedgerFile, BackendLoweringMechanism, CatalogHardwareAlternative,
+    CatalogHardwareTarget, ClcAdmission, ClcOperation, ClusterBarrierAdmission, ClusterBarrierMode,
+    ClusterMemoryAdmission, ClusterMemoryOperation, DebugControlAdmission, DebugControlOperation,
+    DotProductOperation, DotProductSignedness, EvidenceFile, EvidenceRecord, EvidenceStage,
+    EvidenceStageKind, ImportedFile, ImportedIntrinsic, IntrinsicBackend, IntrinsicSource,
+    MaskEncoding, MbarrierExtendedAdmission, MbarrierExtendedOperation, MovmatrixAdapter,
+    MovmatrixParticipation, OverlayBackendLowering, OverlayFile, OverlayIntrinsic,
+    PackedAluAdapter, PackedAluFormat, PackedAluOperation, PackedConversionAdapter,
+    PackedConversionDestinationFormat, PackedConversionFp8Admission, PackedConversionFp8Direction,
+    PackedConversionFp8F16x2Admission, PackedConversionFp8Format, PackedConversionRounding,
+    PackedConversionSaturation, PackedConversionSourceFormat, PreSm70MemberMaskRule, PrmtAdmission,
+    PrmtMode, RegisterMmaAccumulator, RegisterMmaAmpereFloatAdmission, RegisterMmaF8F6F4Admission,
+    RegisterMmaFp8Admission, RuntimeValidation, SparseMmaElement, SparseMmaF8F6F4Admission,
+    SparseMmaF8F6F4F16Admission, SpecialRegisterAdmission, StmatrixAdmission, StmatrixLayout,
+    StmatrixMultiplicity, Tcgen05Admission, Tcgen05CpAdmissionVariant, Tcgen05CpGroup,
+    Tcgen05LdAdmissionVariant, Tcgen05MmaAdmissionVariant, Tcgen05MmaForm, Tcgen05Operation,
+    Tcgen05StAdmissionVariant, ThreadfenceAdmission, ThreadfenceScope, TmaAdmission, VoteAdapter,
+    VoteMode, VoteParticipation, WarpShuffleAdapter, WarpShuffleMode, WarpShuffleParticipation,
+    WarpShuffleSourceLane, WarpShuffleValueKind, WgmmaControlAdmission, WgmmaControlMode,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use crate::util::read_json;
+use anyhow::Result;
+use std::collections::BTreeMap;
+use std::fs;
+use std::path::{Path, PathBuf};
+
+use crate::model::ImportedSelection;
+use crate::resolve::abi_ledger::*;
+use crate::resolve::evidence::*;
+use crate::resolve::families::*;
+use crate::resolve::overlay::*;
+use crate::resolve::policy::*;
+use crate::resolve::targets::*;
+
+pub(super) fn sreg_pattern(special_register: &str) -> InstructionPattern {
+    InstructionPattern::new(
+        "mov",
+        &["u32"],
+        vec![
+            OperandPattern::Register,
+            OperandPattern::Exact {
+                value: special_register.into(),
+            },
+        ],
+    )
+}
+
+pub(super) fn policy() -> OverlayIntrinsic {
+    OverlayIntrinsic {
+        id: "thread_idx_x".into(),
+        abi_id: "i0001".into(),
+        operation_key: "launch.thread_index.x".into(),
+        family: "sreg".into(),
+        source: None,
+        source_record: Some("int_nvvm_read_ptx_sreg_tid_x".into()),
+        rust_module: "sreg".into(),
+        rust_name: "thread_idx_x".into(),
+        rust_arguments: vec![],
+        rust_result: "u32".into(),
+        safe: true,
+        must_use: false,
+        safe_allowlist_reason: Some("no caller obligations".into()),
+        public_rust_path: "cuda_intrinsics::sreg::thread_idx_x".into(),
+        compatibility_rust_paths: vec!["cuda_device::thread::threadIdx_x".into()],
+        dialect_op_type: "ReadPtxSregTidXOp".into(),
+        dialect_op_name: "nvvm.read_ptx_sreg_tid_x".into(),
+        dialect_operands: vec![],
+        dialect_results: vec![],
+        llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.tid.x".into()),
+        resolved_llvm_symbol: None,
+        llvm_arguments: vec![],
+        llvm_results: vec!["i32".into()],
+        pure: true,
+        memory: "none".into(),
+        convergent: false,
+        execution_scope: "thread".into(),
+        minimum_ptx: "2.0".into(),
+        minimum_sm: None,
+        ptx_result: "u32".into(),
+        targets: "all".into(),
+        ptx_isa_version: "9.3".into(),
+        ptx_isa_section: "10.1 Special Registers: %tid".into(),
+        ptx_isa_url: "https://docs.nvidia.com/cuda/parallel-thread-execution/".into(),
+        lowering: "direct_nvvm".into(),
+        backend_lowerings: vec![],
+        packed_atomic: None,
+        redux: None,
+        vote: None,
+        active_mask: None,
+        warp_match: None,
+        warp_barrier: None,
+        warp_shuffle: None,
+        dot_product: None,
+        packed_alu: None,
+        integer_minmax: None,
+        packed_conversion: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cp_async_copy: None,
+        cp_async_control: None,
+        cp_async_mbarrier: None,
+        mbarrier_basic: None,
+        movmatrix: None,
+        mbarrier_extended: None,
+        register_mma: None,
+        sparse_mma: None,
+        prmt: None,
+        cluster_barrier: None,
+        wgmma_control: None,
+        special_register: None,
+        debug_control: None,
+        cluster_memory: None,
+        clc: None,
+        tma: None,
+        tcgen05: None,
+        ldmatrix_variant: None,
+        ldmatrix_safety: None,
+        ldmatrix_adapter: None,
+        selected_address_space: None,
+        expected_ptx: sreg_pattern("%tid.x"),
+        summary: "thread index".into(),
+    }
+}
+
+pub(super) fn distinct_policy() -> OverlayIntrinsic {
+    let mut record = policy();
+    record.id = "thread_idx_y".into();
+    record.abi_id = "i0002".into();
+    record.operation_key = "launch.thread_index.y".into();
+    record.source_record = Some("int_nvvm_read_ptx_sreg_tid_y".into());
+    record.rust_name = "thread_idx_y".into();
+    record.public_rust_path = "cuda_intrinsics::sreg::thread_idx_y".into();
+    record.compatibility_rust_paths = vec!["cuda_device::thread::threadIdx_y".into()];
+    record.dialect_op_type = "ReadPtxSregTidYOp".into();
+    record.dialect_op_name = "nvvm.read_ptx_sreg_tid_y".into();
+    record.llvm_symbol = Some("llvm.nvvm.read.ptx.sreg.tid.y".into());
+    record.expected_ptx = sreg_pattern("%tid.y");
+    record
+}
+
+pub(super) fn movmatrix_policy() -> OverlayIntrinsic {
+    let mut record = policy();
+    record.id = "movmatrix_trans_b16".into();
+    record.abi_id = "i0305".into();
+    record.operation_key = "movmatrix.m8n8.trans.b16".into();
+    record.family = "movmatrix".into();
+    record.source = Some(IntrinsicSource::PtxNative {
+        instruction: "movmatrix.sync.aligned.m8n8.trans.b16".into(),
+    });
+    record.source_record = None;
+    record.rust_module = "matrix".into();
+    record.rust_name = "movmatrix_trans_b16".into();
+    record.rust_arguments = vec!["u32".into()];
+    record.rust_result = "u32".into();
+    record.safe = false;
+    record.must_use = true;
+    record.safe_allowlist_reason = None;
+    record.public_rust_path = "cuda_intrinsics::matrix::movmatrix_trans_b16".into();
+    record.compatibility_rust_paths = vec!["cuda_device::wmma::movmatrix_trans_b16".into()];
+    record.dialect_op_type = "MovmatrixTransB16Op".into();
+    record.dialect_op_name = "nvvm.movmatrix_trans_b16".into();
+    record.dialect_operands = vec!["i32".into()];
+    record.dialect_results = vec!["i32".into()];
+    record.llvm_symbol = None;
+    record.resolved_llvm_symbol = None;
+    record.llvm_arguments.clear();
+    record.llvm_results.clear();
+    record.pure = false;
+    record.memory = "inaccessible_read_write".into();
+    record.convergent = true;
+    record.execution_scope = "warp".into();
+    record.minimum_ptx = "7.8".into();
+    record.minimum_sm = Some("sm_75".into());
+    record.ptx_result = "u32".into();
+    record.targets = "all".into();
+    record.ptx_isa_section =
+        "9.7.15.5.17 Warp-level matrix transpose instruction: movmatrix".into();
+    record.lowering = "generated_movmatrix_inline_ptx".into();
+    record.backend_lowerings = [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
+        .into_iter()
+        .map(|backend| OverlayBackendLowering {
+            backend,
+            mechanism: BackendLoweringMechanism::InlinePtx,
+            evidence_profile: match backend {
+                IntrinsicBackend::LlvmNvptx => "llvm-test",
+                IntrinsicBackend::LibNvvm => "libnvvm-test",
+            }
+            .into(),
+            targets: None,
+            minimum_ptx: Some("7.8".into()),
+            minimum_sm: Some("sm_75".into()),
+        })
+        .collect();
+    record.movmatrix = Some(crate::model::Movmatrix {
+        participation: MovmatrixParticipation::AllWarpLanesSameInstructionNoExitedLanes,
+        adapter: MovmatrixAdapter::PackedB16x2U32ToPackedB16x2U32,
+        runtime_validation: RuntimeValidation::Unexecuted,
+    });
+    record.expected_ptx = InstructionPattern::new(
+        "movmatrix",
+        &["sync", "aligned", "m8n8", "trans", "b16"],
+        vec![OperandPattern::Register, OperandPattern::Register],
+    );
+    record.summary = "Transposes one packed b16 matrix fragment across a warp.".into();
+    record
+}
+
+pub(super) fn declaration() -> ImportedIntrinsic {
+    ImportedIntrinsic {
+        source_record: "int_nvvm_read_ptx_sreg_tid_x".into(),
+        llvm_name: "llvm.nvvm.read.ptx.sreg.tid.x".into(),
+        arguments: vec![],
+        results: vec!["i32".into()],
+        classes: vec!["NVVMPureIntrinsic".into()],
+        properties: vec![
+            "IntrNoMem".into(),
+            "IntrSpeculatable".into(),
+            "NoUndef<ret>".into(),
+            "Range<ret,0,1024>".into(),
+        ],
+        selections: vec![ImportedSelection {
+            source_record: "INT_PTX_SREG_TID_x".into(),
+            asm: "mov.u32 $d, %tid.x;".into(),
+            predicates: vec![],
+            constraints: Default::default(),
+        }],
+    }
+}
+
+pub(super) fn evidence() -> EvidenceRecord {
+    EvidenceRecord {
+        id: "thread_idx_x".into(),
+        source: None,
+        source_record: Some("int_nvvm_read_ptx_sreg_tid_x".into()),
+        llvm_symbol: Some("llvm.nvvm.read.ptx.sreg.tid.x".into()),
+        resolved_llvm_symbol: None,
+        llvm_arguments: vec![],
+        llvm_results: vec!["i32".into()],
+        concrete_llvm_arguments: vec![],
+        concrete_llvm_results: vec![],
+        target_triple: "nvptx64-nvidia-cuda".into(),
+        gpu_target: "sm_70".into(),
+        ptx_feature: "+ptx60".into(),
+        status: "lowered".into(),
+        stages: vec![],
+        declaration_attributes_canonicalized: None,
+        runtime_validation: None,
+        expected_ptx: sreg_pattern("%tid.x"),
+    }
+}
+
+pub(super) fn validate_test_evidence(
+    policy: &OverlayIntrinsic,
+    record: EvidenceRecord,
+) -> Result<()> {
+    let file = EvidenceFile {
+        schema: 3,
+        backend_profile: "test".into(),
+        backend_kind: None,
+        llvm_revision: "test".into(),
+        backend_version: "LLVM version test".into(),
+        backend_sha256: "0123456789abcdef".into(),
+        artifact_path: None,
+        build_id_prefix: None,
+        nvvm_ir_version: None,
+        debug_ir_version: None,
+        records: vec![record],
+    };
+    let indexed = IndexedEvidence {
+        file: &file,
+        record: &file.records[0],
+        backend_version: &file.backend_version,
+        backend_sha256: &file.backend_sha256,
+    };
+    validate_evidence(policy, &indexed, None)
+}
+
+pub(super) fn shared_matrix_stage() -> EvidenceStage {
+    EvidenceStage {
+        targets: vec!["sm_80".into(), "ptx71".into()],
+        representation: "shared fixture".into(),
+        stage: EvidenceStageKind::BackendCodegen,
+        mechanism: Some(BackendLoweringMechanism::InlinePtx),
+        outcome: "succeeded".into(),
+        detail: "$dst remains fixture text".into(),
+        artifact_kind: None,
+        tool_path: None,
+        tool_version: None,
+        tool_sha256: None,
+    }
+}
+
+pub(super) fn synthetic_matrix_json() -> serde_json::Value {
+    serde_json::json!({
+        "schema": 6,
+        "backend_profile": "matrix-test",
+        "backend_kind": "llvm_nvptx",
+        "llvm_revision": "test",
+        "backend_version": "LLVM matrix test",
+        "backend_sha256": "0123456789abcdef",
+        "defaults": {
+            "llvm_arguments": ["i32"],
+            "llvm_results": ["i32"],
+            "target_triple": "nvptx64-nvidia-cuda",
+            "gpu_target": "sm_80",
+            "ptx_feature": "+ptx71",
+            "status": "lowered"
+        },
+        "fixtures": [{
+            "id": "shared",
+            "coverage_count": 2,
+            "stages": [{
+                "targets": ["sm_80", "ptx71"],
+                "representation": "shared fixture",
+                "stage": "backend_codegen",
+                "mechanism": "inline_ptx",
+                "outcome": "succeeded",
+                "detail": "$dst remains fixture text"
+            }]
+        }],
+        "matrices": [{
+            "axes": [{
+                "name": "element",
+                "values": ["s8", "u8"]
+            }],
+            "product_count": 2,
+            "fixtures": ["shared"],
+            "template": {
+                "id": "synthetic_${element}",
+                "source_record": "int_synthetic_${element}",
+                "llvm_symbol": "llvm.synthetic.${element}",
+                "expected_ptx": {
+                    "mnemonic": "mma",
+                    "modifiers": ["sync", "${element}"],
+                    "operands": [{"kind": "register"}]
+                }
+            }
+        }],
+        "records": [{
+            "id": "synthetic_explicit",
+            "source_record": "int_synthetic_explicit",
+            "llvm_symbol": "llvm.synthetic.explicit",
+            "llvm_arguments": ["i32"],
+            "llvm_results": ["i32"],
+            "target_triple": "nvptx64-nvidia-cuda",
+            "gpu_target": "sm_80",
+            "ptx_feature": "+ptx71",
+            "status": "lowered",
+            "expected_ptx": {
+                "mnemonic": "mma",
+                "modifiers": ["sync", "explicit"],
+                "operands": [{"kind": "register"}]
+            }
+        }]
+    })
+}
+
+pub(super) fn policy_matrix_json() -> serde_json::Value {
+    serde_json::json!({
+        "schema": 6,
+        "backend_profile": "matrix-test",
+        "llvm_revision": "test",
+        "backend_version": "LLVM matrix test",
+        "backend_sha256": "0123456789abcdef",
+        "defaults": {
+            "llvm_arguments": [],
+            "llvm_results": ["i32"],
+            "target_triple": "nvptx64-nvidia-cuda",
+            "gpu_target": "sm_70",
+            "ptx_feature": "+ptx60",
+            "status": "lowered"
+        },
+        "fixtures": [{
+            "id": "policy_fixture",
+            "coverage_count": 1,
+            "stages": [{
+                "targets": ["sm_70", "ptx60"],
+                "representation": "policy fixture",
+                "stage": "backend_codegen",
+                "mechanism": "typed_nvvm",
+                "outcome": "succeeded",
+                "detail": "shared policy fixture"
+            }]
+        }],
+        "matrices": [{
+            "axes": [{
+                "name": "axis",
+                "values": ["x"]
+            }],
+            "product_count": 1,
+            "fixtures": ["policy_fixture"],
+            "template": {
+                "id": "thread_idx_${axis}",
+                "source_record": "int_nvvm_read_ptx_sreg_tid_${axis}",
+                "llvm_symbol": "llvm.nvvm.read.ptx.sreg.tid.${axis}",
+                "expected_ptx": {
+                    "mnemonic": "mov",
+                    "modifiers": ["u32"],
+                    "operands": [
+                        {"kind": "register"},
+                        {"kind": "exact", "value": "%tid.${axis}"}
+                    ]
+                }
+            }
+        }]
+    })
+}
+
+pub(super) fn parse_synthetic_evidence(value: &serde_json::Value) -> Result<EvidenceFile> {
+    parse_evidence_bytes(&serde_json::to_vec(value).unwrap(), "synthetic evidence")
+}
+
+pub(super) fn assert_synthetic_evidence_error(value: &serde_json::Value, expected: &str) {
+    let error = parse_synthetic_evidence(value).unwrap_err();
+    let message = format!("{error:#}");
+    assert!(
+        message.contains(expected),
+        "expected {expected:?} in {message:?}"
+    );
+}
+
+pub(super) fn overlay_file(records: Vec<OverlayIntrinsic>) -> OverlayFile {
+    OverlayFile {
+        schema: OVERLAY_SCHEMA,
+        catalog_version: "test".into(),
+        intrinsic_abi: 1,
+        backend_profile: "test".into(),
+        shards: vec![],
+        intrinsics: records,
+    }
+}
+
+pub(super) fn bind_pinned_abi_ids(repo_root: &Path, overlay: &mut OverlayFile) {
+    let ledger_path = repo_root.join(format!("intrinsics/abi-v{}.toml", overlay.intrinsic_abi));
+    let ledger: AbiLedgerFile =
+        toml::from_str(&std::fs::read_to_string(ledger_path).unwrap()).unwrap();
+    bind_generated_abi_ids(overlay, &ledger).unwrap();
+}
+
+pub(super) fn validate_imported_policy(
+    policy: &OverlayIntrinsic,
+    declaration: &ImportedIntrinsic,
+) -> Result<()> {
+    let source = resolve_policy_source(policy)?;
+    validate_policy(policy, &source, Some(declaration), 1)
+}
+
+pub(super) fn pinned_active_mask_and_warp_match_records()
+-> BTreeMap<String, (OverlayIntrinsic, ImportedIntrinsic)> {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .into_iter()
+        .map(|record| (record.source_record.clone(), record))
+        .collect();
+
+    overlay
+        .intrinsics
+        .into_iter()
+        .filter(|record| matches!(record.family.as_str(), "active_mask" | "warp_match"))
+        .map(|policy| {
+            let declaration = declarations[policy.source_record.as_deref().unwrap()].clone();
+            (policy.id.clone(), (policy, declaration))
+        })
+        .collect()
+}
+
+pub(super) fn pinned_mbarrier_basic_records()
+-> BTreeMap<String, (OverlayIntrinsic, ImportedIntrinsic)> {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .into_iter()
+        .map(|record| (record.source_record.clone(), record))
+        .collect();
+
+    overlay
+        .intrinsics
+        .into_iter()
+        .filter(|record| record.family == "mbarrier_basic")
+        .map(|policy| {
+            let declaration = declarations[policy.source_record.as_deref().unwrap()].clone();
+            (policy.id.clone(), (policy, declaration))
+        })
+        .collect()
+}
+
+pub(super) fn pinned_cp_async_mbarrier_records()
+-> BTreeMap<String, (OverlayIntrinsic, ImportedIntrinsic)> {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .into_iter()
+        .map(|record| (record.source_record.clone(), record))
+        .collect();
+
+    overlay
+        .intrinsics
+        .into_iter()
+        .filter(|record| record.family == "cp_async_mbarrier")
+        .map(|policy| {
+            let declaration = declarations[policy.source_record.as_deref().unwrap()].clone();
+            (policy.id.clone(), (policy, declaration))
+        })
+        .collect()
+}
+
+pub(super) fn packed_policy(id: &str) -> OverlayIntrinsic {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml"))
+        .unwrap()
+        .0
+        .intrinsics
+        .into_iter()
+        .find(|record| record.id == id)
+        .unwrap()
+}
+
+pub(super) fn packed_alu_policy(
+    format: PackedAluFormat,
+    operation: PackedAluOperation,
+) -> OverlayIntrinsic {
+    let recipe = packed_alu_recipe(format, operation).expect("test recipe pair");
+    let (rust_module, rust_type, dialect_type, adapter) = match format {
+        PackedAluFormat::Bf16x2 => ("bf16x2", "u32", "i32", PackedAluAdapter::DirectPackedU32),
+        PackedAluFormat::F16x2 => ("f16x2", "u32", "i32", PackedAluAdapter::DirectPackedU32),
+        PackedAluFormat::F32x2 => ("f32x2", "u64", "i64", PackedAluAdapter::DirectPackedU64),
+    };
+    let mut record = policy();
+    record.id = recipe.id.into();
+    record.abi_id = recipe.abi_id.into();
+    record.operation_key = recipe.operation_key.into();
+    record.family = "packed_alu".into();
+    match &recipe.source {
+        PackedAluRecipeSource::Imported {
+            record: source_record,
+            symbol,
+            resolved_symbol,
+            arguments,
+            results,
+            ..
+        } => {
+            record.source = None;
+            record.source_record = Some((*source_record).into());
+            record.llvm_symbol = Some((*symbol).into());
+            record.resolved_llvm_symbol = resolved_symbol.map(str::to_owned);
+            record.llvm_arguments = arguments.iter().map(|value| (*value).into()).collect();
+            record.llvm_results = results.iter().map(|value| (*value).into()).collect();
+        }
+        PackedAluRecipeSource::PtxNative => {
+            record.source = Some(IntrinsicSource::PtxNative {
+                instruction: recipe.ptx_mnemonic.into(),
+            });
+            record.source_record = None;
+            record.llvm_symbol = None;
+            record.resolved_llvm_symbol = None;
+            record.llvm_arguments.clear();
+            record.llvm_results.clear();
+        }
+    }
+    record.rust_module = rust_module.into();
+    record.rust_name = recipe.rust_name.into();
+    record.rust_arguments = vec![rust_type.into(); recipe.arity];
+    record.rust_result = rust_type.into();
+    record.safe = true;
+    record.must_use = recipe.must_use;
+    record.safe_allowlist_reason = Some("the operation has no caller obligations".into());
+    record.public_rust_path = format!("cuda_intrinsics::{rust_module}::{}", recipe.rust_name);
+    record.compatibility_rust_paths =
+        vec![format!("cuda_device::{rust_module}::{}", recipe.rust_name)];
+    record.dialect_op_type = recipe.dialect_op_type.into();
+    record.dialect_op_name = recipe.dialect_op_name.into();
+    record.dialect_operands = vec![dialect_type.into(); recipe.arity];
+    record.dialect_results = vec![dialect_type.into()];
+    record.pure = true;
+    record.memory = "none".into();
+    record.convergent = false;
+    record.execution_scope = "thread".into();
+    record.minimum_ptx = recipe.minimum_ptx.into();
+    record.minimum_sm = Some(recipe.minimum_sm.into());
+    record.ptx_result = rust_type.into();
+    record.ptx_isa_section = recipe.ptx_isa_section.into();
+    record.ptx_isa_url = recipe.ptx_isa_url.into();
+    record.lowering = "generated_packed_alu_inline_ptx".into();
+    record.backend_lowerings = [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
+        .into_iter()
+        .map(|backend| {
+            let (minimum_ptx, minimum_sm) =
+                packed_alu_backend_floor(&recipe, format, operation, backend);
+            crate::model::OverlayBackendLowering {
+                backend,
+                mechanism: BackendLoweringMechanism::InlinePtx,
+                evidence_profile: format!("{backend:?}-test"),
+                targets: None,
+                minimum_ptx: Some(minimum_ptx.into()),
+                minimum_sm: Some(minimum_sm.into()),
+            }
+        })
+        .collect();
+    record.packed_alu = Some(crate::model::PackedAlu {
+        format,
+        native_minimum_sm: recipe.native_minimum_sm,
+        operation,
+        adapter,
+    });
+    record.expected_ptx = InstructionPattern::new(
+        recipe.ptx_mnemonic.split('.').next().unwrap(),
+        recipe.modifiers,
+        vec![OperandPattern::Register; recipe.arity + 1],
+    );
+    record.summary = format!("packed {rust_module} arithmetic");
+    record
+}
+
+pub(super) fn packed_alu_declaration(
+    format: PackedAluFormat,
+    operation: PackedAluOperation,
+) -> Option<ImportedIntrinsic> {
+    let recipe = packed_alu_recipe(format, operation).expect("test recipe pair");
+    let PackedAluRecipeSource::Imported {
+        record,
+        symbol,
+        arguments,
+        results,
+        properties,
+        selection,
+        selection_asm,
+        ..
+    } = recipe.source
+    else {
+        return None;
+    };
+    let classes = if matches!(operation, PackedAluOperation::Min | PackedAluOperation::Max) {
+        vec!["Intrinsic".into()]
+    } else {
+        vec!["Intrinsic".into(), "NVVMPureIntrinsic".into()]
+    };
+    let mut selections = vec![ImportedSelection {
+        source_record: selection.into(),
+        asm: selection_asm.into(),
+        predicates: vec![
+            format!("Subtarget->getSmVersion() >= {}", recipe.native_minimum_sm),
+            format!(
+                "Subtarget->getPTXVersion() >= {}",
+                recipe.minimum_ptx.replace('.', "")
+            ),
+        ],
+        constraints: Default::default(),
+    }];
+    if operation == PackedAluOperation::Abs {
+        selections.extend((0..5).map(|index| ImportedSelection {
+            source_record: format!("OTHER_ABS_{index}"),
+            asm: "abs.f32 $dst, $src0;".into(),
+            predicates: vec![],
+            constraints: Default::default(),
+        }));
+    }
+    Some(ImportedIntrinsic {
+        source_record: record.into(),
+        llvm_name: symbol.into(),
+        arguments: arguments.iter().map(|value| (*value).into()).collect(),
+        results: results.iter().map(|value| (*value).into()).collect(),
+        classes,
+        properties: properties.iter().map(|value| (*value).into()).collect(),
+        selections,
+    })
+}
+
+pub(super) fn packed_conversion_policy(
+    destination_format: PackedConversionDestinationFormat,
+    rounding: PackedConversionRounding,
+    saturation: PackedConversionSaturation,
+) -> OverlayIntrinsic {
+    let conversion = crate::model::PackedConversion {
+        source_format: PackedConversionSourceFormat::F32x2,
+        destination_format,
+        rounding,
+        saturation,
+        adapter: PackedConversionAdapter::ReverseHighLowOperands,
+    };
+    let recipe = packed_conversion_recipe(&conversion).expect("test packed-conversion recipe");
+    let mut record = policy();
+    record.id = recipe.id.into();
+    record.abi_id = recipe.abi_id.into();
+    record.operation_key = recipe.operation_key.into();
+    record.family = "packed_conversion".into();
+    record.source_record = Some(recipe.source_record.into());
+    record.rust_module = "convert".into();
+    record.rust_name = recipe.rust_name.into();
+    record.rust_arguments = vec!["f32".into(), "f32".into()];
+    let result_width = packed_conversion_result_width(&conversion);
+    record.rust_result = format!("u{result_width}");
+    record.safe = true;
+    record.must_use = false;
+    record.safe_allowlist_reason = Some("the operation has no caller obligations".into());
+    record.public_rust_path = format!("cuda_intrinsics::convert::{}", recipe.rust_name);
+    record.compatibility_rust_paths = vec![recipe.compatibility_path.into()];
+    record.dialect_op_type = recipe.dialect_op_type.into();
+    record.dialect_op_name = recipe.dialect_op_name.into();
+    record.dialect_operands = vec!["f32".into(), "f32".into()];
+    record.dialect_results = vec![format!("i{result_width}")];
+    record.llvm_symbol = Some(recipe.llvm_symbol.into());
+    record.llvm_arguments = vec!["f32".into(), "f32".into()];
+    record.llvm_results = vec![recipe.llvm_result.into()];
+    record.pure = true;
+    record.memory = "none".into();
+    record.convergent = false;
+    record.execution_scope = "thread".into();
+    let (minimum_ptx, minimum_sm) = packed_conversion_floor(&conversion);
+    record.minimum_ptx = minimum_ptx.into();
+    record.minimum_sm = Some(minimum_sm.into());
+    record.ptx_result = format!("u{result_width}");
+    record.ptx_isa_section = "9.7.9.22 Data Movement and Conversion Instructions: cvt".into();
+    record.ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt".into();
+    record.lowering = packed_conversion_lowering(&conversion).into();
+    record.backend_lowerings = [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
+        .into_iter()
+        .map(|backend| OverlayBackendLowering {
+            backend,
+            mechanism: packed_conversion_backend_mechanism(&conversion, backend),
+            evidence_profile: "test".into(),
+            targets: None,
+            minimum_ptx: Some(minimum_ptx.into()),
+            minimum_sm: Some(minimum_sm.into()),
+        })
+        .collect();
+    let modifiers = packed_conversion_ptx_modifiers(&conversion);
+    record.packed_conversion = Some(conversion);
+    record.expected_ptx =
+        InstructionPattern::new("cvt", &modifiers, vec![OperandPattern::Register; 3]);
+    record.summary = recipe.summary.into();
+    record
+}
+
+pub(super) fn packed_conversion_declaration(policy: &OverlayIntrinsic) -> ImportedIntrinsic {
+    ImportedIntrinsic {
+        source_record: policy.source_record.clone().unwrap(),
+        llvm_name: policy.llvm_symbol.clone().unwrap(),
+        arguments: policy.llvm_arguments.clone(),
+        results: policy.llvm_results.clone(),
+        classes: vec!["Intrinsic".into(), "NVVMPureIntrinsic".into()],
+        properties: vec!["IntrNoMem".into(), "IntrSpeculatable".into()],
+        selections: vec![],
+    }
+}
+
+pub(super) fn packed_conversion_evidence(policy: &OverlayIntrinsic) -> EvidenceRecord {
+    let mut record = evidence();
+    record.id = policy.id.clone();
+    record.source_record = policy.source_record.clone();
+    record.llvm_symbol = policy.llvm_symbol.clone();
+    record.resolved_llvm_symbol = policy.resolved_llvm_symbol.clone();
+    record.llvm_arguments = policy.llvm_arguments.clone();
+    record.llvm_results = policy.llvm_results.clone();
+    record.concrete_llvm_arguments = policy.llvm_arguments.clone();
+    record.concrete_llvm_results = policy.llvm_results.clone();
+    record.declaration_attributes_canonicalized = Some(true);
+    record.expected_ptx = policy.expected_ptx.clone();
+    record
+}
+
+pub(super) fn redux_policy() -> OverlayIntrinsic {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml"))
+        .unwrap()
+        .0
+        .intrinsics
+        .into_iter()
+        .find(|record| record.id == "redux_sync_add")
+        .unwrap()
+}
+
+pub(super) fn redux_declaration() -> ImportedIntrinsic {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let text = std::fs::read_to_string(repo_root.join("intrinsics/imported.json")).unwrap();
+    serde_json::from_str::<ImportedFile>(&text)
+        .unwrap()
+        .intrinsics
+        .into_iter()
+        .find(|record| record.source_record == "int_nvvm_redux_sync_add")
+        .unwrap()
+}
+
+pub(super) fn sync_policy() -> OverlayIntrinsic {
+    packed_policy("sync_threads")
+}
+
+pub(super) fn sync_declaration() -> ImportedIntrinsic {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let text = std::fs::read_to_string(repo_root.join("intrinsics/imported.json")).unwrap();
+    serde_json::from_str::<ImportedFile>(&text)
+        .unwrap()
+        .intrinsics
+        .into_iter()
+        .find(|record| record.source_record == "int_nvvm_barrier_cta_sync_aligned_all")
+        .unwrap()
+}
+
+pub(super) fn warp_barrier_policy() -> OverlayIntrinsic {
+    packed_policy("sync_mask")
+}
+
+pub(super) fn warp_barrier_declaration() -> ImportedIntrinsic {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let text = std::fs::read_to_string(repo_root.join("intrinsics/imported.json")).unwrap();
+    serde_json::from_str::<ImportedFile>(&text)
+        .unwrap()
+        .intrinsics
+        .into_iter()
+        .find(|record| record.source_record == "int_nvvm_bar_warp_sync")
+        .unwrap()
+}
+
+pub(super) fn vote_policy(mode: VoteMode) -> OverlayIntrinsic {
+    let recipe = vote_recipe(mode);
+    let mut record = policy();
+    record.id = recipe.id.into();
+    record.abi_id = recipe.abi_id.into();
+    record.operation_key = recipe.operation_key.into();
+    record.family = "vote".into();
+    record.source_record = Some(recipe.source_record.into());
+    record.rust_module = "warp".into();
+    record.rust_name = recipe.rust_name.into();
+    record.rust_arguments = vec!["u32".into(), "bool".into()];
+    record.rust_result = recipe.rust_result.into();
+    record.safe = false;
+    record.must_use = true;
+    record.safe_allowlist_reason = None;
+    record.public_rust_path = format!("cuda_intrinsics::warp::{}", recipe.rust_name);
+    record.compatibility_rust_paths = if recipe.has_compatibility_path {
+        vec![format!("cuda_device::warp::{}", recipe.rust_name)]
+    } else {
+        vec![]
+    };
+    record.dialect_op_type = recipe.dialect_op_type.into();
+    record.dialect_op_name = recipe.dialect_op_name.into();
+    record.dialect_operands = vec!["i32".into(), "i1".into()];
+    record.dialect_results = vec![recipe.llvm_result.into()];
+    record.llvm_symbol = Some(recipe.llvm_symbol.into());
+    record.llvm_arguments = vec!["i32".into(), "i1".into()];
+    record.llvm_results = vec![recipe.llvm_result.into()];
+    record.pure = false;
+    record.memory = "inaccessible_read_write".into();
+    record.convergent = true;
+    record.execution_scope = "warp".into();
+    record.minimum_ptx = "6.0".into();
+    record.minimum_sm = Some("sm_30".into());
+    record.ptx_result = recipe.rust_result.into();
+    record.ptx_isa_section = "9.7.14.10 Warp Vote Instructions: vote.sync".into();
+    record.ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-vote-sync".into();
+    record.lowering = "generated_vote".into();
+    record.vote = Some(crate::model::Vote {
+        mode,
+        participation: VoteParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
+        legacy_pre_sm70: PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive,
+        adapter: VoteAdapter::DirectMaskPredicate,
+        mask_encoding: MaskEncoding::RegisterOrImmediate,
+    });
+    record.expected_ptx = InstructionPattern::new(
+        "vote",
+        &["sync", recipe.ptx_mode, recipe.ptx_type],
+        vec![
+            OperandPattern::Register,
+            OperandPattern::Register,
+            OperandPattern::RegisterOrImmediate,
+        ],
+    );
+    record.summary = "warp vote".into();
+    record
+}
+
+pub(super) fn vote_declaration(mode: VoteMode) -> ImportedIntrinsic {
+    let recipe = vote_recipe(mode);
+    let selection = |source_record: &str| ImportedSelection {
+        source_record: source_record.into(),
+        asm: format!(
+            "vote.sync.{}.{} \t$dest, $pred, $mask;",
+            recipe.ptx_mode, recipe.ptx_type
+        ),
+        predicates: vec![
+            "Subtarget->getPTXVersion() >= 60".into(),
+            "Subtarget->getSmVersion() >= 30".into(),
+        ],
+        constraints: Default::default(),
+    };
+    ImportedIntrinsic {
+        source_record: recipe.source_record.into(),
+        llvm_name: recipe.llvm_symbol.into(),
+        arguments: vec!["i32".into(), "i1".into()],
+        results: vec![recipe.llvm_result.into()],
+        classes: vec![
+            "ClangBuiltin".into(),
+            "NVVMBuiltin".into(),
+            "SDPatternOperator".into(),
+            "Intrinsic".into(),
+        ],
+        properties: vec![
+            "IntrConvergent".into(),
+            "IntrInaccessibleMemOnly".into(),
+            "IntrNoCallback".into(),
+        ],
+        selections: vec![
+            selection(recipe.immediate_selection),
+            selection(recipe.register_selection),
+        ],
+    }
+}
+
+pub(super) fn warp_shuffle_policy(
+    mode: WarpShuffleMode,
+    value_kind: WarpShuffleValueKind,
+) -> OverlayIntrinsic {
+    let recipe = warp_shuffle_recipe(mode, value_kind);
+    let mut record = policy();
+    record.id = recipe.id.into();
+    record.abi_id = recipe.abi_id.into();
+    record.operation_key = recipe.operation_key.into();
+    record.family = "warp_shuffle".into();
+    match recipe.source {
+        WarpShuffleRecipeSource::LlvmImported {
+            source_record,
+            llvm_symbol,
+        } => {
+            record.source_record = Some(source_record.into());
+            record.llvm_symbol = Some(llvm_symbol.into());
+            record.llvm_arguments = vec![
+                "i32".into(),
+                recipe.dialect_value.into(),
+                "i32".into(),
+                "i32".into(),
+            ];
+            record.llvm_results = vec![recipe.dialect_value.into()];
+        }
+        WarpShuffleRecipeSource::PtxNative { instruction } => {
+            record.source = Some(IntrinsicSource::PtxNative {
+                instruction: instruction.into(),
+            });
+            record.source_record = None;
+            record.llvm_symbol = None;
+            record.llvm_arguments.clear();
+            record.llvm_results.clear();
+        }
+    }
+    record.rust_module = "warp".into();
+    record.rust_name = recipe.rust_name.into();
+    record.rust_arguments = vec!["u32".into(), recipe.rust_value.into(), "u32".into()];
+    record.rust_result = recipe.rust_value.into();
+    record.safe = false;
+    record.must_use = true;
+    record.safe_allowlist_reason = None;
+    record.public_rust_path = format!("cuda_intrinsics::warp::{}", recipe.rust_name);
+    record.compatibility_rust_paths = vec![format!("cuda_device::warp::{}", recipe.rust_name)];
+    record.dialect_op_type = recipe.dialect_op_type.into();
+    record.dialect_op_name = recipe.dialect_op_name.into();
+    record.dialect_operands = vec!["i32".into(), recipe.dialect_value.into(), "i32".into()];
+    record.dialect_results = vec![recipe.dialect_value.into()];
+    record.pure = false;
+    record.memory = "inaccessible_read_write".into();
+    record.convergent = true;
+    record.execution_scope = "warp".into();
+    record.minimum_ptx = "6.0".into();
+    record.minimum_sm = Some("sm_30".into());
+    record.ptx_result = recipe.rust_value.into();
+    record.targets = "all".into();
+    record.ptx_isa_section = "9.7.9.6 Data Movement and Conversion Instructions: shfl.sync".into();
+    record.ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-shfl-sync".into();
+    record.lowering = recipe.lowering.into();
+    record.backend_lowerings = vec![
+        crate::model::OverlayBackendLowering {
+            backend: IntrinsicBackend::LlvmNvptx,
+            mechanism: recipe.backend_mechanism,
+            evidence_profile: "llvm-test".into(),
+            targets: None,
+            minimum_ptx: Some("6.0".into()),
+            minimum_sm: Some("sm_30".into()),
+        },
+        crate::model::OverlayBackendLowering {
+            backend: IntrinsicBackend::LibNvvm,
+            mechanism: recipe.backend_mechanism,
+            evidence_profile: "libnvvm-test".into(),
+            targets: None,
+            minimum_ptx: Some("6.0".into()),
+            minimum_sm: Some("sm_75".into()),
+        },
+    ];
+    record.warp_shuffle = Some(crate::model::WarpShuffle {
+        mode,
+        value_kind,
+        participation:
+            WarpShuffleParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
+        legacy_pre_sm70: PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive,
+        source_lane: WarpShuffleSourceLane::InRangeSourceActiveAndNamedOutOfRangeCopiesSelf,
+        adapter: recipe.adapter,
+        clamp: recipe.clamp,
+        lane_encoding: recipe.operand_encoding,
+        mask_encoding: recipe.operand_encoding,
+    });
+    let operands = match recipe.adapter {
+        WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp => vec![
+            OperandPattern::Register,
+            OperandPattern::Register,
+            OperandPattern::RegisterOrImmediate,
+            OperandPattern::Exact {
+                value: recipe.clamp.to_string(),
+            },
+            OperandPattern::RegisterOrImmediate,
+        ],
+        WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble => {
+            vec![
+                OperandPattern::Exact { value: "lo".into() },
+                OperandPattern::Exact { value: "lo".into() },
+                OperandPattern::Register,
+                OperandPattern::Exact {
+                    value: recipe.clamp.to_string(),
+                },
+                OperandPattern::Register,
+            ]
+        }
+    };
+    record.expected_ptx =
+        InstructionPattern::new("shfl", &["sync", recipe.ptx_mode, "b32"], operands);
+    record.summary = "synchronized warp shuffle".into();
+    record
+}
+
+pub(super) fn warp_shuffle_declaration(
+    mode: WarpShuffleMode,
+    value_kind: WarpShuffleValueKind,
+) -> ImportedIntrinsic {
+    let recipe = warp_shuffle_recipe(mode, value_kind);
+    let WarpShuffleRecipeSource::LlvmImported {
+        source_record,
+        llvm_symbol,
+    } = recipe.source
+    else {
+        panic!("PTX-native i64 shuffles have no imported declaration");
+    };
+    let selections = (0..8)
+        .map(|index| ImportedSelection {
+            source_record: format!("anonymous_test_{index}"),
+            asm: format!(
+                "shfl.sync.{}.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                recipe.ptx_mode
+            ),
+            predicates: vec![
+                "Subtarget->getPTXVersion() >= 60".into(),
+                "Subtarget->getSmVersion() >= 30".into(),
+            ],
+            constraints: Default::default(),
+        })
+        .collect();
+    ImportedIntrinsic {
+        source_record: source_record.into(),
+        llvm_name: llvm_symbol.into(),
+        arguments: vec![
+            "i32".into(),
+            recipe.dialect_value.into(),
+            "i32".into(),
+            "i32".into(),
+        ],
+        results: vec![recipe.dialect_value.into()],
+        classes: vec![
+            "ClangBuiltin".into(),
+            "NVVMBuiltin".into(),
+            "SDPatternOperator".into(),
+            "Intrinsic".into(),
+        ],
+        properties: vec![
+            "IntrConvergent".into(),
+            "IntrInaccessibleMemOnly".into(),
+            "IntrNoCallback".into(),
+        ],
+        selections,
+    }
+}
+
+pub(super) fn sync_evidence(policy: &OverlayIntrinsic) -> EvidenceRecord {
+    let mut record = evidence();
+    record.id = policy.id.clone();
+    record.source_record = policy.source_record.clone();
+    record.llvm_symbol = policy.llvm_symbol.clone();
+    record.llvm_arguments = policy.llvm_arguments.clone();
+    record.llvm_results = policy.llvm_results.clone();
+    record.expected_ptx = policy.expected_ptx.clone();
+    record
+}
+
+pub(super) fn dot_product_policy(
+    operation: DotProductOperation,
+    signedness: DotProductSignedness,
+) -> OverlayIntrinsic {
+    let recipe = dot_product_recipe(operation, signedness);
+    let mut record = policy();
+    record.id = recipe.id.into();
+    record.abi_id = match (operation, signedness) {
+        (DotProductOperation::Dp4a, DotProductSignedness::Signed) => "i0030",
+        (DotProductOperation::Dp4a, DotProductSignedness::Unsigned) => "i0031",
+        (DotProductOperation::Dp2a, DotProductSignedness::Signed) => "i0032",
+        (DotProductOperation::Dp2a, DotProductSignedness::Unsigned) => "i0033",
+    }
+    .into();
+    record.operation_key = recipe.operation_key.into();
+    record.family = "dotprod".into();
+    record.source = None;
+    record.source_record = Some(recipe.source_record.into());
+    record.rust_module = "dotprod".into();
+    record.rust_name = recipe.rust_name.into();
+    record.rust_arguments = vec!["u32".into(), "u32".into(), recipe.rust_value.into()];
+    record.rust_result = recipe.rust_value.into();
+    record.safe = true;
+    record.must_use = false;
+    record.safe_allowlist_reason = Some(
+        "per-thread integer arithmetic has no memory, pointer, or participation obligations".into(),
+    );
+    record.public_rust_path = format!("cuda_intrinsics::dotprod::{}", recipe.rust_name);
+    record.compatibility_rust_paths = vec![format!("cuda_device::dotprod::{}", recipe.rust_name)];
+    record.dialect_op_type = recipe.dialect_op_type.into();
+    record.dialect_op_name = recipe.dialect_op_name.into();
+    record.dialect_operands = vec!["i32".into(), "i32".into(), "i32".into()];
+    record.dialect_results = vec!["i32".into()];
+    record.llvm_symbol = Some(recipe.llvm_symbol.into());
+    record.resolved_llvm_symbol = None;
+    record.llvm_arguments = recipe
+        .llvm_arguments
+        .iter()
+        .map(|argument| (*argument).into())
+        .collect();
+    record.llvm_results = vec!["i32".into()];
+    record.pure = true;
+    record.memory = "none".into();
+    record.convergent = false;
+    record.execution_scope = "thread".into();
+    record.minimum_ptx = "5.0".into();
+    record.minimum_sm = Some("sm_61".into());
+    record.ptx_result = recipe.rust_value.into();
+    record.targets = "all".into();
+    record.lowering = "generated_dotprod".into();
+    record.backend_lowerings = vec![
+        crate::model::OverlayBackendLowering {
+            backend: IntrinsicBackend::LlvmNvptx,
+            mechanism: BackendLoweringMechanism::TypedNvvm,
+            evidence_profile: "llvm-test".into(),
+            targets: None,
+            minimum_ptx: None,
+            minimum_sm: None,
+        },
+        crate::model::OverlayBackendLowering {
+            backend: IntrinsicBackend::LibNvvm,
+            mechanism: BackendLoweringMechanism::InlinePtx,
+            evidence_profile: "libnvvm-test".into(),
+            targets: None,
+            minimum_ptx: None,
+            minimum_sm: Some("sm_75".into()),
+        },
+    ];
+    record.dot_product = Some(crate::model::DotProduct {
+        operation,
+        signedness,
+        adapter: recipe.adapter,
+    });
+    record.expected_ptx = InstructionPattern::new(
+        recipe.ptx_mnemonic,
+        recipe.ptx_modifiers,
+        vec![OperandPattern::Register; 4],
+    );
+    record.summary = "packed integer dot product".into();
+    record
+}
+
+pub(super) fn dot_product_declaration(
+    operation: DotProductOperation,
+    signedness: DotProductSignedness,
+) -> ImportedIntrinsic {
+    let recipe = dot_product_recipe(operation, signedness);
+    let selection = |source_record: &str, half: Option<(&str, i64)>| ImportedSelection {
+        source_record: source_record.into(),
+        asm: format!(
+            "{}.{} $dst, $a, $b, $c;",
+            recipe.ptx_mnemonic,
+            match half {
+                Some((name, _)) => {
+                    let types = &recipe.ptx_modifiers[1..];
+                    format!("{name}.{}", types.join("."))
+                }
+                None => recipe.ptx_modifiers.join("."),
+            }
+        ),
+        predicates: vec!["hasDotInstructions".into()],
+        constraints: crate::model::ImportedSelectionConstraints {
+            address_space: None,
+            immediate_bindings: half
+                .map(|(_, value)| {
+                    vec![crate::model::ImportedImmediateBinding {
+                        argument_index: 2,
+                        value,
+                    }]
+                })
+                .unwrap_or_default(),
+        },
+    };
+    let selections = match operation {
+        DotProductOperation::Dp4a => vec![selection("DOT4", None)],
+        DotProductOperation::Dp2a => vec![
+            selection("DOT2_hi", Some(("hi", -1))),
+            selection("DOT2_lo", Some(("lo", 0))),
+        ],
+    };
+    ImportedIntrinsic {
+        source_record: recipe.source_record.into(),
+        llvm_name: recipe.llvm_symbol.into(),
+        arguments: recipe
+            .llvm_arguments
+            .iter()
+            .map(|argument| (*argument).into())
+            .collect(),
+        results: vec!["i32".into()],
+        classes: vec!["NVVMPureIntrinsic".into()],
+        properties: recipe
+            .llvm_properties
+            .iter()
+            .map(|property| (*property).into())
+            .collect(),
+        selections,
+    }
+}
+
+pub(super) fn dot_product_evidence(policy: &OverlayIntrinsic) -> EvidenceRecord {
+    let mut record = evidence();
+    record.id = policy.id.clone();
+    record.source_record = policy.source_record.clone();
+    record.llvm_symbol = policy.llvm_symbol.clone();
+    record.llvm_arguments = policy.llvm_arguments.clone();
+    record.llvm_results = policy.llvm_results.clone();
+    record.concrete_llvm_arguments = policy.llvm_arguments.clone();
+    record.concrete_llvm_results = policy.llvm_results.clone();
+    record.declaration_attributes_canonicalized = Some(true);
+    record.gpu_target = "sm_61".into();
+    record.ptx_feature = "+ptx50".into();
+    record.expected_ptx = policy.expected_ptx.clone();
+    record
+}
+
+pub(super) fn validate_ptx_native_policy(policy: &OverlayIntrinsic) -> Result<()> {
+    let source = resolve_policy_source(policy)?;
+    validate_policy(policy, &source, None, 1)
+}
+
+pub(super) fn ledger_entry(record: &OverlayIntrinsic) -> AbiLedgerEntry {
+    AbiLedgerEntry {
+        abi_id: record.abi_id.clone(),
+        status: "active".into(),
+        catalog_id: record.id.clone(),
+        operation_key: record.operation_key.clone(),
+        raw_rust_signature: raw_rust_signature(record),
+    }
+}
+
+pub(super) fn ledger(entries: Vec<AbiLedgerEntry>) -> AbiLedgerFile {
+    AbiLedgerFile {
+        schema: 1,
+        intrinsic_abi: 1,
+        entries,
+    }
+}
+
+pub(super) fn test_f8f6f4_admission() -> SparseMmaF8F6F4Admission {
+    let formats = vec![
+        SparseMmaElement::E2m1,
+        SparseMmaElement::E2m3,
+        SparseMmaElement::E3m2,
+        SparseMmaElement::E4m3,
+        SparseMmaElement::E5m2,
+    ];
+    SparseMmaF8F6F4Admission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        a_elements: formats.clone(),
+        b_elements: formats,
+        product_count: 25,
+    }
+}
+
+pub(super) fn test_sparse_mma_f8f6f4_f16_admission() -> SparseMmaF8F6F4F16Admission {
+    SparseMmaF8F6F4F16Admission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        _legacy_first_abi_id: Some("i0525".into()),
+        a_elements: SPARSE_MMA_F8F6F4_ELEMENTS.into(),
+        b_elements: SPARSE_MMA_F8F6F4_ELEMENTS.into(),
+        product_count: 25,
+    }
+}
+
+pub(super) fn test_register_mma_f8f6f4_admission(
+    _accumulator: RegisterMmaAccumulator,
+) -> RegisterMmaF8F6F4Admission {
+    let formats = REGISTER_MMA_F8F6F4_ELEMENTS.to_vec();
+    RegisterMmaF8F6F4Admission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        _legacy_first_abi_id: None,
+        a_elements: formats.clone(),
+        b_elements: formats,
+        product_count: 25,
+        targets: ["sm_120a", "sm_120f", "sm_121a", "sm_121f"]
+            .map(Into::into)
+            .into(),
+    }
+}
+
+pub(super) fn test_register_mma_fp8_admission() -> RegisterMmaFp8Admission {
+    RegisterMmaFp8Admission {
+        llvm_evidence_profile: "llvm-fp8-test".into(),
+        libnvvm_evidence_profile: "libnvvm-fp8-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        _legacy_first_abi_id: Some("i0504".into()),
+        shapes: REGISTER_MMA_FP8_SHAPES.into(),
+        accumulators: REGISTER_MMA_FP8_ACCUMULATORS.into(),
+        a_elements: REGISTER_MMA_FP8_ELEMENTS.into(),
+        b_elements: REGISTER_MMA_FP8_ELEMENTS.into(),
+        product_count: 16,
+    }
+}
+
+pub(super) fn test_register_mma_ampere_float_admission() -> RegisterMmaAmpereFloatAdmission {
+    RegisterMmaAmpereFloatAdmission {
+        llvm_evidence_profile: "llvm-ampere-float-test".into(),
+        libnvvm_evidence_profile: "libnvvm-ampere-float-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        _legacy_first_abi_id: Some("i0520".into()),
+        product_count: 5,
+        variants: REGISTER_MMA_AMPERE_FLOAT_VARIANTS.into(),
+    }
+}
+
+pub(super) fn test_prmt_admission() -> PrmtAdmission {
+    let variants = [
+        PrmtMode::Generic,
+        PrmtMode::F4e,
+        PrmtMode::B4e,
+        PrmtMode::Rc8,
+        PrmtMode::Ecl,
+        PrmtMode::Ecr,
+        PrmtMode::Rc16,
+    ]
+    .map(|mode| crate::model::PrmtAdmissionVariant {
+        abi_id: prmt_recipe(mode).abi_id.into(),
+        mode,
+    })
+    .into();
+    PrmtAdmission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants,
+    }
+}
+
+pub(super) fn test_fp8_conversion_admission() -> PackedConversionFp8Admission {
+    PackedConversionFp8Admission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        destination_formats: vec![
+            PackedConversionDestinationFormat::E4m3x2,
+            PackedConversionDestinationFormat::E5m2x2,
+        ],
+        saturations: vec![
+            PackedConversionSaturation::Satfinite,
+            PackedConversionSaturation::SatfiniteRelu,
+        ],
+        product_count: 4,
+    }
+}
+
+pub(super) fn test_fp8_f16x2_conversion_admission() -> PackedConversionFp8F16x2Admission {
+    PackedConversionFp8F16x2Admission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        fp8_formats: vec![
+            PackedConversionFp8Format::E4m3x2,
+            PackedConversionFp8Format::E5m2x2,
+        ],
+        directions: vec![
+            PackedConversionFp8Direction::Pack,
+            PackedConversionFp8Direction::Unpack,
+        ],
+        relu_variants: true,
+        product_count: 8,
+    }
+}
+
+pub(super) fn test_cluster_barrier_admission() -> ClusterBarrierAdmission {
+    let variants = [
+        ClusterBarrierMode::Arrive,
+        ClusterBarrierMode::ArriveAligned,
+        ClusterBarrierMode::ArriveRelaxed,
+        ClusterBarrierMode::ArriveRelaxedAligned,
+        ClusterBarrierMode::Wait,
+        ClusterBarrierMode::WaitAligned,
+    ]
+    .map(|mode| crate::model::ClusterBarrierAdmissionVariant {
+        abi_id: cluster_barrier_recipe(mode).abi_id.into(),
+        mode,
+    })
+    .into();
+    ClusterBarrierAdmission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants,
+    }
+}
+
+pub(super) fn test_wgmma_control_admission() -> WgmmaControlAdmission {
+    let variants = [
+        WgmmaControlMode::Fence,
+        WgmmaControlMode::CommitGroup,
+        WgmmaControlMode::WaitGroup,
+    ]
+    .map(|mode| crate::model::WgmmaControlAdmissionVariant {
+        abi_id: wgmma_control_recipe(mode).abi_id.into(),
+        mode,
+    })
+    .into();
+    WgmmaControlAdmission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants,
+    }
+}
+
+pub(super) fn test_special_register_admission() -> SpecialRegisterAdmission {
+    SpecialRegisterAdmission {
+        llvm_evidence_profile: "rust-llvm-22.1.2-1cb4e383".into(),
+        libnvvm_evidence_profile: "cuda-13.3-libnvvm-13.3.33".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        registers: REVIEWED_SPECIAL_REGISTERS.into(),
+        product_count: REVIEWED_SPECIAL_REGISTERS.len(),
+    }
+}
+
+pub(super) fn test_debug_control_admission() -> DebugControlAdmission {
+    DebugControlAdmission {
+        llvm_evidence_profile: "llvm-debug-test".into(),
+        libnvvm_evidence_profile: "libnvvm-debug-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        operations: vec![
+            DebugControlOperation::Trap,
+            DebugControlOperation::Breakpoint,
+            DebugControlOperation::Pmevent,
+        ],
+        abi_ids: vec!["i9001".into(), "i9002".into(), "i9003".into()],
+    }
+}
+
+pub(super) fn test_clc_admission() -> ClcAdmission {
+    let operations = [
+        ClcOperation::TryCancel,
+        ClcOperation::TryCancelMulticast,
+        ClcOperation::QueryIsCanceled,
+        ClcOperation::QueryGetFirstCtaidX,
+        ClcOperation::QueryGetFirstCtaidY,
+        ClcOperation::QueryGetFirstCtaidZ,
+    ];
+    ClcAdmission {
+        llvm_evidence_profile: "llvm-clc-test".into(),
+        libnvvm_evidence_profile: "libnvvm-clc-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: operations
+            .into_iter()
+            .map(|operation| crate::model::ClcAdmissionVariant {
+                abi_id: clc_recipe(operation).abi_id.into(),
+                operation,
+            })
+            .collect(),
+    }
+}
+
+pub(super) fn test_tma_admission() -> TmaAdmission {
+    TmaAdmission {
+        llvm_evidence_profile: "llvm-tma-test".into(),
+        libnvvm_evidence_profile: "libnvvm-tma-test".into(),
+        reduce_llvm_evidence_profile: Some("llvm-tma-reduce-test".into()),
+        reduce_libnvvm_evidence_profile: Some("libnvvm-tma-reduce-test".into()),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: TMA_OPERATIONS
+            .into_iter()
+            .map(|operation| crate::model::TmaAdmissionVariant {
+                abi_id: tma_recipe(operation).abi_id.into(),
+                operation,
+            })
+            .collect(),
+        reduce_variants: tma_reduction_admission_variants(),
+    }
+}
+
+pub(super) fn test_tcgen05_admission() -> Tcgen05Admission {
+    let operations = [
+        Tcgen05Operation::Alloc,
+        Tcgen05Operation::Dealloc,
+        Tcgen05Operation::RelinquishAllocPermit,
+        Tcgen05Operation::FenceBeforeThreadSync,
+        Tcgen05Operation::FenceAfterThreadSync,
+        Tcgen05Operation::Commit,
+        Tcgen05Operation::CommitSharedCluster,
+        Tcgen05Operation::MmaWsF16,
+        Tcgen05Operation::MmaF16,
+        Tcgen05Operation::MmaWsBf16,
+        Tcgen05Operation::MmaWsTf32,
+        Tcgen05Operation::CpSmemToTmem,
+        Tcgen05Operation::Ld16x256bX8Pure,
+        Tcgen05Operation::Ld16x256bPure,
+        Tcgen05Operation::LoadWait,
+        Tcgen05Operation::StoreWait,
+        Tcgen05Operation::AllocCg2,
+        Tcgen05Operation::DeallocCg2,
+        Tcgen05Operation::RelinquishAllocPermitCg2,
+        Tcgen05Operation::MmaF16Cg2,
+        Tcgen05Operation::CommitCg2,
+        Tcgen05Operation::CommitSharedClusterCg2,
+        Tcgen05Operation::CommitMulticastCg2,
+        Tcgen05Operation::CpSmemToTmemCg2,
+        Tcgen05Operation::CommitMulticast,
+        Tcgen05Operation::ShiftDown,
+        Tcgen05Operation::ShiftDownCg2,
+    ];
+    Tcgen05Admission {
+        llvm_evidence_profile: "llvm-tcgen05-test".into(),
+        libnvvm_evidence_profile: "libnvvm-tcgen05-test".into(),
+        cp_llvm_evidence_profile: None,
+        cp_libnvvm_evidence_profile: None,
+        ld_llvm_evidence_profile: None,
+        ld_libnvvm_evidence_profile: None,
+        st_llvm_evidence_profile: None,
+        st_libnvvm_evidence_profile: None,
+        offset_llvm_evidence_profile: None,
+        offset_libnvvm_evidence_profile: None,
+        control_llvm_evidence_profile: Some("llvm-tcgen05-control-test".into()),
+        control_libnvvm_evidence_profile: Some("libnvvm-tcgen05-control-test".into()),
+        mma_llvm_evidence_profile: None,
+        mma_libnvvm_evidence_profile: None,
+        mma_llvm_target_contracts: vec![],
+        mma_libnvvm_target_contracts: vec![],
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: operations
+            .into_iter()
+            .map(|operation| crate::model::Tcgen05AdmissionVariant {
+                abi_id: tcgen05_recipe(operation).abi_id.into(),
+                operation,
+            })
+            .collect(),
+        cp_variants: vec![],
+        ld_variants: vec![],
+        st_variants: vec![],
+        ld_offset_variants: vec![],
+        st_offset_variants: vec![],
+        mma_variants: vec![],
+    }
+}
+
+pub(super) fn without_tcgen05_control(mut admission: Tcgen05Admission) -> Tcgen05Admission {
+    admission.variants.truncate(24);
+    admission.control_llvm_evidence_profile = None;
+    admission.control_libnvvm_evidence_profile = None;
+    admission
+}
+
+pub(super) fn test_tcgen05_cp_admission() -> Tcgen05Admission {
+    let mut admission = test_tcgen05_admission();
+    admission.cp_llvm_evidence_profile = Some("llvm-tcgen05-cp-test".into());
+    admission.cp_libnvvm_evidence_profile = Some("libnvvm-tcgen05-cp-test".into());
+    admission.cp_variants = TCGEN05_CP_MEMBERS
+        .into_iter()
+        .flat_map(|member| {
+            [Tcgen05CpGroup::Cg1, Tcgen05CpGroup::Cg2]
+                .into_iter()
+                .map(move |group| (member, group))
+        })
+        .enumerate()
+        .map(|(index, (member, group))| Tcgen05CpAdmissionVariant {
+            abi_id: format!("i{:04}", 578 + index),
+            member,
+            group,
+        })
+        .collect();
+    admission
+}
+
+pub(super) fn test_tcgen05_ld_admission() -> Tcgen05Admission {
+    let mut admission = test_tcgen05_cp_admission();
+    admission.ld_llvm_evidence_profile = Some("llvm-tcgen05-ld-test".into());
+    admission.ld_libnvvm_evidence_profile = Some("libnvvm-tcgen05-ld-test".into());
+    admission.ld_variants = TCGEN05_LD_VARIANTS
+        .into_iter()
+        .flat_map(|(shape, multiplicity)| {
+            [false, true]
+                .into_iter()
+                .map(move |pack16| (shape, multiplicity, pack16))
+        })
+        .enumerate()
+        .map(
+            |(index, (shape, multiplicity, pack16))| Tcgen05LdAdmissionVariant {
+                abi_id: format!("i{:04}", 612 + index),
+                shape,
+                multiplicity,
+                pack16,
+            },
+        )
+        .collect();
+    admission
+}
+
+pub(super) fn test_tcgen05_st_admission() -> Tcgen05Admission {
+    let mut admission = test_tcgen05_ld_admission();
+    admission.st_llvm_evidence_profile = Some("llvm-tcgen05-st-test".into());
+    admission.st_libnvvm_evidence_profile = Some("libnvvm-tcgen05-st-test".into());
+    admission.st_variants = TCGEN05_ST_VARIANTS
+        .into_iter()
+        .flat_map(|(shape, multiplicity)| {
+            [false, true]
+                .into_iter()
+                .map(move |unpack16| (shape, multiplicity, unpack16))
+        })
+        .enumerate()
+        .map(
+            |(index, (shape, multiplicity, unpack16))| Tcgen05StAdmissionVariant {
+                abi_id: format!("i{:04}", 670 + index),
+                shape,
+                multiplicity,
+                unpack16,
+            },
+        )
+        .collect();
+    admission
+}
+
+pub(super) fn test_tcgen05_offset_admission() -> Tcgen05Admission {
+    let mut admission = test_tcgen05_st_admission();
+    admission.offset_llvm_evidence_profile = Some("llvm-tcgen05-offset-test".into());
+    admission.offset_libnvvm_evidence_profile = Some("libnvvm-tcgen05-offset-test".into());
+    admission.ld_offset_variants = TCGEN05_OFFSET_LDST_VARIANTS
+        .into_iter()
+        .flat_map(|(shape, multiplicity)| {
+            [false, true]
+                .into_iter()
+                .map(move |pack16| (shape, multiplicity, pack16))
+        })
+        .enumerate()
+        .map(
+            |(index, (shape, multiplicity, pack16))| Tcgen05LdAdmissionVariant {
+                abi_id: format!("i{:04}", 728 + index),
+                shape,
+                multiplicity,
+                pack16,
+            },
+        )
+        .collect();
+    admission.st_offset_variants = TCGEN05_OFFSET_LDST_VARIANTS
+        .into_iter()
+        .flat_map(|(shape, multiplicity)| {
+            [false, true]
+                .into_iter()
+                .map(move |unpack16| (shape, multiplicity, unpack16))
+        })
+        .enumerate()
+        .map(
+            |(index, (shape, multiplicity, unpack16))| Tcgen05StAdmissionVariant {
+                abi_id: format!("i{:04}", 744 + index),
+                shape,
+                multiplicity,
+                unpack16,
+            },
+        )
+        .collect();
+    admission
+}
+
+pub(super) fn test_tcgen05_mma_admission() -> Tcgen05Admission {
+    let mut admission = test_tcgen05_admission();
+    admission.mma_llvm_evidence_profile = Some("llvm-tcgen05-mma-test".into());
+    admission.mma_libnvvm_evidence_profile = Some("libnvvm-tcgen05-mma-test".into());
+    admission.mma_llvm_target_contracts =
+        expected_tcgen05_mma_target_contracts(IntrinsicBackend::LlvmNvptx);
+    admission.mma_libnvvm_target_contracts =
+        expected_tcgen05_mma_target_contracts(IntrinsicBackend::LibNvvm);
+    admission.mma_variants = TCGEN05_MMA_FORMS
+        .into_iter()
+        .map(|form| (form, None))
+        .chain(
+            TCGEN05_MMA_ALIASES
+                .into_iter()
+                .map(|alias| (Tcgen05MmaForm::WsTensor, Some(alias))),
+        )
+        .enumerate()
+        .map(|(index, (form, alias))| Tcgen05MmaAdmissionVariant {
+            abi_id: format!("i{:04}", 763 + index),
+            form,
+            alias,
+        })
+        .chain(
+            TCGEN05_MMA_ALIASES
+                .into_iter()
+                .enumerate()
+                .map(|(index, alias)| Tcgen05MmaAdmissionVariant {
+                    abi_id: format!("i{:04}", 1011 + index),
+                    form: Tcgen05MmaForm::Shared,
+                    alias: Some(alias),
+                }),
+        )
+        .collect();
+    admission
+}
+
+pub(super) fn assert_tcgen05_backend_target_split(record: &OverlayIntrinsic) {
+    let llvm = &record.backend_lowerings[0];
+    let libnvvm = &record.backend_lowerings[1];
+    assert_eq!(record.targets, TCGEN05_LLVM_TARGETS);
+    assert_eq!(llvm.backend, IntrinsicBackend::LlvmNvptx);
+    assert_eq!(llvm.targets, None);
+    assert_eq!(libnvvm.backend, IntrinsicBackend::LibNvvm);
+    assert_eq!(libnvvm.targets.as_deref(), Some(TCGEN05_LIBNVVM_TARGETS));
+    assert_eq!(
+        backend_target_requirement(record, llvm).unwrap().hardware,
+        CatalogHardwareTarget::AnyOf {
+            alternatives: vec![
+                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+            ],
+        }
+    );
+    assert_eq!(
+        backend_target_requirement(record, libnvvm)
+            .unwrap()
+            .hardware,
+        CatalogHardwareTarget::AnyOf {
+            alternatives: vec![
+                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+            ],
+        }
+    );
+}
+
+pub(super) fn test_threadfence_admission() -> ThreadfenceAdmission {
+    ThreadfenceAdmission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: vec![
+            crate::model::ThreadfenceAdmissionVariant {
+                abi_id: "i0298".into(),
+                scope: ThreadfenceScope::Cta,
+            },
+            crate::model::ThreadfenceAdmissionVariant {
+                abi_id: "i0299".into(),
+                scope: ThreadfenceScope::Device,
+            },
+            crate::model::ThreadfenceAdmissionVariant {
+                abi_id: "i0300".into(),
+                scope: ThreadfenceScope::System,
+            },
+        ],
+    }
+}
+
+pub(super) fn test_cluster_memory_admission() -> ClusterMemoryAdmission {
+    ClusterMemoryAdmission {
+        llvm_evidence_profile: "llvm-cluster-memory-test".into(),
+        libnvvm_evidence_profile: "libnvvm-cluster-memory-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: vec![
+            crate::model::ClusterMemoryAdmissionVariant {
+                abi_id: "i0320".into(),
+                operation: ClusterMemoryOperation::MapSharedRank,
+            },
+            crate::model::ClusterMemoryAdmissionVariant {
+                abi_id: "i0321".into(),
+                operation: ClusterMemoryOperation::ReadU32,
+            },
+        ],
+    }
+}
+
+pub(super) fn test_stmatrix_admission() -> StmatrixAdmission {
+    let variants = [
+        (StmatrixMultiplicity::X2, StmatrixLayout::Normal, "i0301"),
+        (
+            StmatrixMultiplicity::X2,
+            StmatrixLayout::Transposed,
+            "i0302",
+        ),
+        (StmatrixMultiplicity::X4, StmatrixLayout::Normal, "i0303"),
+        (
+            StmatrixMultiplicity::X4,
+            StmatrixLayout::Transposed,
+            "i0304",
+        ),
+    ]
+    .map(
+        |(multiplicity, layout, abi_id)| crate::model::StmatrixAdmissionVariant {
+            abi_id: abi_id.into(),
+            multiplicity,
+            layout,
+        },
+    )
+    .into();
+    StmatrixAdmission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants,
+    }
+}
+
+pub(super) fn test_mbarrier_extended_admission() -> MbarrierExtendedAdmission {
+    let variants = [
+        MbarrierExtendedOperation::ArriveExpectTxCta,
+        MbarrierExtendedOperation::ArriveExpectTxCluster,
+        MbarrierExtendedOperation::ArriveRemoteCluster,
+        MbarrierExtendedOperation::TryWaitTokenCta,
+        MbarrierExtendedOperation::TryWaitParityCta,
+        MbarrierExtendedOperation::TryWaitParityCluster,
+        MbarrierExtendedOperation::FenceProxyAsyncSharedCta,
+        MbarrierExtendedOperation::FenceMbarrierInitReleaseCluster,
+        MbarrierExtendedOperation::FenceProxyAsyncGenericReleaseSharedCtaCluster,
+        MbarrierExtendedOperation::FenceProxyAsyncGenericAcquireSharedClusterCluster,
+        MbarrierExtendedOperation::Nanosleep,
+    ]
+    .map(|operation| crate::model::MbarrierExtendedAdmissionVariant {
+        abi_id: mbarrier_extended_recipe(operation).abi_id.into(),
+        operation,
+    })
+    .into();
+    MbarrierExtendedAdmission {
+        llvm_evidence_profile: "llvm-test".into(),
+        libnvvm_evidence_profile: "libnvvm-test".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants,
+    }
+}
+
+pub(super) struct CandidateTestRepo(pub(super) PathBuf);
+
+impl Drop for CandidateTestRepo {
+    fn drop(&mut self) {
+        let _ = fs::remove_dir_all(&self.0);
+    }
+}
+
+pub(super) fn repo_without_evidence() -> CandidateTestRepo {
+    use std::sync::atomic::{AtomicU64, Ordering};
+
+    static NEXT: AtomicU64 = AtomicU64::new(0);
+    let source = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let root = std::env::temp_dir().join(format!(
+        "cuda-intrinsics-candidate-{}-{}",
+        std::process::id(),
+        NEXT.fetch_add(1, Ordering::Relaxed)
+    ));
+    let input = root.join("intrinsics");
+    fs::create_dir_all(input.join("overlay")).unwrap();
+    for name in [
+        "upstream.lock",
+        "imported.json",
+        "overlay.toml",
+        "abi-v1.toml",
+    ] {
+        fs::copy(source.join("intrinsics").join(name), input.join(name)).unwrap();
+    }
+    for entry in fs::read_dir(source.join("intrinsics/overlay")).unwrap() {
+        let entry = entry.unwrap();
+        if entry.path().extension().and_then(|value| value.to_str()) == Some("toml") {
+            fs::copy(entry.path(), input.join("overlay").join(entry.file_name())).unwrap();
+        }
+    }
+    CandidateTestRepo(root)
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs
new file mode 100644
index 0000000000..42777630a3
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs
@@ -0,0 +1,1123 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::extract::IMPORTED_SCHEMA;
+use crate::model::{
+    BackendLoweringMechanism, CpAsyncAdapter, CpAsyncCachePolicy, CpAsyncControlAdapter,
+    CpAsyncControlOperation, CpAsyncCopySize, CpAsyncMbarrierAdapter, CpAsyncMbarrierOperation,
+    CpAsyncMbarrierStateSpace, CpAsyncSourceSize, DebugControlAdapter, DebugControlOperation,
+    DotProductAdapter, DotProductOperation, DotProductSignedness, ImportedFile, ImportedIntrinsic,
+    IntrinsicBackend, IntrinsicSource, MbarrierBasicAdapter, MbarrierBasicOperation,
+    MbarrierExtendedAdapter, MbarrierExtendedOperation, MbarrierExtendedSourceContract,
+    OverlayIntrinsic, OverlayShardFile, ReduxAdapter, ReduxOperation, RuntimeValidation,
+    WgmmaControlAdapter, WgmmaControlMode,
+};
+use crate::ptx::OperandPattern;
+use crate::util::read_json;
+use std::collections::BTreeMap;
+use std::fs;
+use std::path::Path;
+
+use super::fixtures::*;
+use crate::resolve::evidence::*;
+use crate::resolve::families::*;
+use crate::resolve::guards::*;
+use crate::resolve::materialize::*;
+use crate::resolve::overlay::*;
+use crate::resolve::policy::*;
+use crate::resolve::targets::*;
+
+#[test]
+fn f32_redux_recipes_match_pinned_llvm_records() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect();
+    let cases = [
+        (
+            ReduxOperation::Fmin,
+            "redux.sync.min.f32 \t$dst, $src, $mask;",
+            &["sync", "min", "f32"][..],
+        ),
+        (
+            ReduxOperation::FminNan,
+            "redux.sync.min.NaN.f32 \t$dst, $src, $mask;",
+            &["sync", "min", "NaN", "f32"],
+        ),
+        (
+            ReduxOperation::FminAbs,
+            "redux.sync.min.abs.f32 \t$dst, $src, $mask;",
+            &["sync", "min", "abs", "f32"],
+        ),
+        (
+            ReduxOperation::FminAbsNan,
+            "redux.sync.min.abs.NaN.f32 \t$dst, $src, $mask;",
+            &["sync", "min", "abs", "NaN", "f32"],
+        ),
+        (
+            ReduxOperation::Fmax,
+            "redux.sync.max.f32 \t$dst, $src, $mask;",
+            &["sync", "max", "f32"],
+        ),
+        (
+            ReduxOperation::FmaxNan,
+            "redux.sync.max.NaN.f32 \t$dst, $src, $mask;",
+            &["sync", "max", "NaN", "f32"],
+        ),
+        (
+            ReduxOperation::FmaxAbs,
+            "redux.sync.max.abs.f32 \t$dst, $src, $mask;",
+            &["sync", "max", "abs", "f32"],
+        ),
+        (
+            ReduxOperation::FmaxAbsNan,
+            "redux.sync.max.abs.NaN.f32 \t$dst, $src, $mask;",
+            &["sync", "max", "abs", "NaN", "f32"],
+        ),
+    ];
+
+    for (operation, expected_asm, expected_modifiers) in cases {
+        let recipe = redux_recipe(operation);
+        let declaration = declarations[recipe.source_record];
+        assert_eq!(declaration.llvm_name, recipe.llvm_symbol);
+        assert_eq!(declaration.arguments, ["f32", "i32"]);
+        assert_eq!(declaration.results, ["f32"]);
+        assert_eq!(declaration.selections.len(), 1);
+        assert_eq!(declaration.selections[0].asm, expected_asm);
+        assert_eq!(
+            declaration.selections[0].predicates,
+            ["Subtarget->hasReduxSyncF32()"]
+        );
+        assert_eq!(recipe.ptx_modifiers, expected_modifiers);
+        assert_eq!(recipe.minimum_ptx, "8.6");
+        assert_eq!(recipe.minimum_sm, None);
+        assert_eq!(recipe.targets, REDUX_F32_TARGETS);
+    }
+}
+
+#[test]
+fn compact_debug_control_admission_is_closed() {
+    let records = expand_debug_control_admission(&test_debug_control_admission()).unwrap();
+    assert_eq!(records.len(), 3);
+    assert_eq!(records[0].id, "trap");
+    assert_eq!(records[1].id, "breakpoint");
+    assert_eq!(records[2].id, "pmevent");
+    for record in &records {
+        validate_ptx_native_policy(record).unwrap();
+        assert_eq!(record.backend_lowerings.len(), 2);
+        assert!(
+            record
+                .debug_control
+                .as_ref()
+                .is_some_and(|debug| debug.runtime_validation == RuntimeValidation::Unexecuted)
+        );
+    }
+    assert_eq!(records[0].minimum_ptx, "1.0");
+    assert_eq!(records[0].minimum_sm, None);
+    assert_eq!(records[1].minimum_ptx, "1.0");
+    assert_eq!(records[1].minimum_sm.as_deref(), Some("sm_11"));
+    assert_eq!(records[2].minimum_ptx, "1.4");
+    assert_eq!(
+        records[2].expected_ptx.operands,
+        [OperandPattern::Immediate]
+    );
+
+    let mut pending = test_debug_control_admission();
+    pending.abi_ids.clear();
+    assert!(expand_debug_control_admission(&pending).is_err());
+
+    let mut missing = test_debug_control_admission();
+    missing.operations.pop();
+    assert!(expand_debug_control_admission(&missing).is_err());
+
+    let mut duplicate_operation = test_debug_control_admission();
+    duplicate_operation.operations[2] = DebugControlOperation::Breakpoint;
+    assert!(expand_debug_control_admission(&duplicate_operation).is_err());
+
+    let mut duplicate_id = test_debug_control_admission();
+    duplicate_id.abi_ids[2] = duplicate_id.abi_ids[1].clone();
+    assert!(expand_debug_control_admission(&duplicate_id).is_err());
+
+    let mut malformed_id = test_debug_control_admission();
+    malformed_id.abi_ids[0] = "debug1".into();
+    assert!(expand_debug_control_admission(&malformed_id).is_err());
+
+    let mut executed = test_debug_control_admission();
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_debug_control_admission(&executed).is_err());
+
+    let mut wrong_source = records[0].clone();
+    wrong_source.source = Some(IntrinsicSource::LlvmImported {
+        source_record: "invented".into(),
+    });
+    assert!(validate_ptx_native_policy(&wrong_source).is_err());
+
+    let mut wrong_adapter = records[2].clone();
+    wrong_adapter.debug_control.as_mut().unwrap().adapter = DebugControlAdapter::Direct;
+    assert!(validate_ptx_native_policy(&wrong_adapter).is_err());
+
+    let mut wrong_immediate = records[2].clone();
+    wrong_immediate.expected_ptx.operands = vec![OperandPattern::Register];
+    assert!(validate_ptx_native_policy(&wrong_immediate).is_err());
+
+    let mut wrong_floor = records[1].clone();
+    wrong_floor.backend_lowerings[0].minimum_sm = Some("sm_75".into());
+    assert!(validate_ptx_native_policy(&wrong_floor).is_err());
+}
+
+#[test]
+fn debug_control_compact_schema_is_reserved_for_aggregation() {
+    let shard = |schema| OverlayShardFile {
+        schema,
+        family: "debug_control".into(),
+        intrinsics: vec![],
+        register_mma_int4: None,
+        register_mma_int8: None,
+        register_mma_b1: None,
+        register_mma_f8f6f4_f32: None,
+        register_mma_f8f6f4_f16: None,
+        register_mma_mxf8f6f4_f32: None,
+        register_mma_fp8: None,
+        register_mma_ampere_float: None,
+        sparse_mma_integer: None,
+        sparse_mma_f8f6f4_f32: None,
+        sparse_mma_f8f6f4_f16: None,
+        prmt: None,
+        packed_conversion_fp8: None,
+        packed_conversion_fp8_f16x2: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cluster_sreg: None,
+        cluster_barrier: None,
+        mbarrier_extended: None,
+        special_registers: None,
+        debug_control: Some(test_debug_control_admission()),
+        threadfence: None,
+        cluster_memory: None,
+        stmatrix: None,
+        clc: None,
+        wgmma_controls: None,
+        tma: None,
+        tcgen05: None,
+    };
+    let path = Path::new("intrinsics/overlay/debug_control.toml");
+    validate_overlay_shard_schema_with_max(&shard(33), path, 33).unwrap();
+    assert!(validate_overlay_shard_schema_with_max(&shard(33), path, 32).is_err());
+    let error = validate_overlay_shard_schema_with_max(&shard(32), path, 33).unwrap_err();
+    assert!(
+        error
+            .to_string()
+            .contains("requires overlay shard schema 33")
+    );
+}
+
+#[test]
+fn active_debug_control_sources_parse_and_prove_both_backend_routes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let shard_path = repo_root.join("intrinsics/overlay/debug_control.toml");
+    let shard: OverlayShardFile =
+        toml::from_str(&fs::read_to_string(&shard_path).unwrap()).unwrap();
+    validate_overlay_shard_schema_with_max(&shard, &shard_path, 33).unwrap();
+    let admission = shard.debug_control.unwrap();
+    assert_eq!(admission.abi_ids, ["i0295", "i0296", "i0297"]);
+    let records = expand_debug_control_admission(&admission).unwrap();
+
+    let evidence = vec![
+        read_evidence_file(
+            &repo_root.join("intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-debug-control.json"),
+        )
+        .unwrap(),
+        read_evidence_file(
+            &repo_root.join("intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-debug-control.json"),
+        )
+        .unwrap(),
+    ];
+    let indexed = index_evidence(&evidence, "1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e").unwrap();
+    for record in &records {
+        let routes = resolve_backend_lowerings(record, &indexed).unwrap();
+        assert_eq!(routes.len(), 2);
+        assert!(routes.iter().all(|route| {
+            route.mechanism == BackendLoweringMechanism::InlinePtx && route.status == "validated"
+        }));
+    }
+}
+
+#[test]
+fn compact_extended_mbarrier_admission_preserves_all_manual_contracts() {
+    let records = expand_mbarrier_extended_admission(&test_mbarrier_extended_admission()).unwrap();
+    assert_eq!(records.len(), 11);
+    assert_eq!(
+        records
+            .iter()
+            .map(|record| record.abi_id.as_str())
+            .collect::<Vec<_>>(),
+        (306..=316)
+            .map(|id| format!("i{id:04}"))
+            .collect::<Vec<_>>()
+    );
+
+    let imported: ImportedFile = read_json(
+        &Path::new(env!("CARGO_MANIFEST_DIR"))
+            .join("../..")
+            .join("intrinsics/imported.json"),
+    )
+    .unwrap();
+    for record in &records {
+        let contract = record.mbarrier_extended.as_ref().unwrap();
+        let (template, constraints) = mbarrier_extended_inline_recipe(contract.operation);
+        assert!(template.ends_with(';') || template.ends_with("; }"));
+        assert!(constraints.contains("~{memory}"));
+        assert!(record.convergent && record.memory == "read_write");
+        assert!(
+            record
+                .backend_lowerings
+                .iter()
+                .all(|lowering| { lowering.mechanism == BackendLoweringMechanism::InlinePtx })
+        );
+        match contract.source_contract {
+            MbarrierExtendedSourceContract::LlvmImported => {
+                let declaration = imported
+                    .intrinsics
+                    .iter()
+                    .find(|declaration| {
+                        Some(declaration.source_record.as_str()) == record.source_record.as_deref()
+                    })
+                    .unwrap();
+                validate_imported_policy(record, declaration).unwrap();
+            }
+            MbarrierExtendedSourceContract::PtxNativeRawClusterAddress => {
+                validate_ptx_native_policy(record).unwrap();
+                assert_eq!(record.rust_arguments, ["u64"]);
+                assert_eq!(record.dialect_operands, ["i64"]);
+            }
+        }
+    }
+
+    let base = records
+        .iter()
+        .find(|record| record.id == "mbarrier_arrive_expect_tx")
+        .unwrap();
+    let declaration = imported
+        .intrinsics
+        .iter()
+        .find(|declaration| {
+            Some(declaration.source_record.as_str()) == base.source_record.as_deref()
+        })
+        .unwrap();
+    let mut wrong_adapter = base.clone();
+    wrong_adapter.mbarrier_extended.as_mut().unwrap().adapter =
+        MbarrierExtendedAdapter::PointerTokenToPredicate;
+    assert!(validate_imported_policy(&wrong_adapter, declaration).is_err());
+    let mut wrong_floor = base.clone();
+    wrong_floor.minimum_ptx = "8.6".into();
+    assert!(validate_imported_policy(&wrong_floor, declaration).is_err());
+    let mut lost_clobber = base.clone();
+    lost_clobber.memory = "none".into();
+    assert!(validate_imported_policy(&lost_clobber, declaration).is_err());
+
+    let remote = records
+        .iter()
+        .find(|record| record.id == "mbarrier_arrive_cluster")
+        .unwrap();
+    let incompatible = imported
+        .intrinsics
+        .iter()
+        .find(|declaration| {
+            declaration.source_record == "int_nvvm_mbarrier_arrive_scope_cluster_space_cluster"
+        })
+        .unwrap();
+    assert_eq!(incompatible.arguments, ["shared_cluster_ptr", "i32"]);
+    assert!(
+        validate_mbarrier_extended_policy(
+            remote,
+            &IntrinsicSource::LlvmImported {
+                source_record: incompatible.source_record.clone(),
+            },
+            Some(incompatible),
+        )
+        .is_err()
+    );
+
+    let mut missing = test_mbarrier_extended_admission();
+    missing.variants.pop();
+    assert!(expand_mbarrier_extended_admission(&missing).is_err());
+    let mut duplicate = test_mbarrier_extended_admission();
+    duplicate.variants[10].operation = MbarrierExtendedOperation::ArriveExpectTxCta;
+    assert!(expand_mbarrier_extended_admission(&duplicate).is_err());
+    let mut wrong_abi = test_mbarrier_extended_admission();
+    wrong_abi.variants[0].abi_id = "i9999".into();
+    assert!(expand_mbarrier_extended_admission(&wrong_abi).is_err());
+}
+
+#[test]
+fn compact_wgmma_control_admission_and_semantics_fail_closed() {
+    let records = expand_wgmma_control_admission(&test_wgmma_control_admission()).unwrap();
+    assert_eq!(records.len(), 3);
+
+    let imported: ImportedFile = read_json(
+        &Path::new(env!("CARGO_MANIFEST_DIR"))
+            .join("../..")
+            .join("intrinsics/imported.json"),
+    )
+    .unwrap();
+    let declaration_for = |record: &OverlayIntrinsic| {
+        imported
+            .intrinsics
+            .iter()
+            .find(|declaration| {
+                Some(declaration.source_record.as_str()) == record.source_record.as_deref()
+            })
+            .unwrap()
+    };
+    for record in &records {
+        validate_imported_policy(record, declaration_for(record)).unwrap();
+        assert_eq!(record.targets, "sm_90a");
+        assert_eq!(record.minimum_ptx, "8.0");
+        assert_eq!(record.backend_lowerings.len(), 2);
+    }
+
+    let wait = records
+        .iter()
+        .find(|record| {
+            record
+                .wgmma_control
+                .as_ref()
+                .is_some_and(|control| control.mode == WgmmaControlMode::WaitGroup)
+        })
+        .unwrap();
+    assert_eq!(wait.rust_arguments, ["u64"]);
+    assert_eq!(wait.dialect_operands, ["i64"]);
+    assert_eq!(
+        wait.compatibility_rust_paths,
+        ["cuda_device::wgmma::__wgmma_wait_group"]
+    );
+
+    let mut wrong_adapter = wait.clone();
+    wrong_adapter.wgmma_control.as_mut().unwrap().adapter = WgmmaControlAdapter::NoArguments;
+    assert!(validate_imported_policy(&wrong_adapter, declaration_for(wait)).is_err());
+
+    let mut wrong_participation = wait.clone();
+    wrong_participation.execution_scope = "warp".into();
+    assert!(validate_imported_policy(&wrong_participation, declaration_for(wait)).is_err());
+
+    let mut wrong_route = wait.clone();
+    wrong_route.backend_lowerings[1].mechanism = BackendLoweringMechanism::TypedNvvm;
+    assert!(validate_imported_policy(&wrong_route, declaration_for(wait)).is_err());
+
+    let mut wrong_target = wait.clone();
+    wrong_target.targets = "all".into();
+    wrong_target.minimum_sm = Some("sm_90".into());
+    assert!(validate_imported_policy(&wrong_target, declaration_for(wait)).is_err());
+
+    let mut missing = test_wgmma_control_admission();
+    missing.variants.pop();
+    assert!(expand_wgmma_control_admission(&missing).is_err());
+
+    let mut reversed = test_wgmma_control_admission();
+    reversed.variants.reverse();
+    assert!(expand_wgmma_control_admission(&reversed).is_err());
+
+    let mut duplicate = test_wgmma_control_admission();
+    duplicate.variants[2].mode = WgmmaControlMode::Fence;
+    assert!(expand_wgmma_control_admission(&duplicate).is_err());
+
+    let mut wrong_abi = test_wgmma_control_admission();
+    wrong_abi.variants[0].abi_id = "i9999".into();
+    assert!(expand_wgmma_control_admission(&wrong_abi).is_err());
+
+    let mut executed = test_wgmma_control_admission();
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_wgmma_control_admission(&executed).is_err());
+}
+
+#[test]
+fn wgmma_control_compact_schema_is_reserved_for_aggregation() {
+    let shard = OverlayShardFile {
+        schema: WGMMA_CONTROL_SHARD_SCHEMA,
+        family: "wgmma_control".into(),
+        intrinsics: vec![],
+        register_mma_int4: None,
+        register_mma_int8: None,
+        register_mma_b1: None,
+        register_mma_f8f6f4_f32: None,
+        register_mma_f8f6f4_f16: None,
+        register_mma_mxf8f6f4_f32: None,
+        register_mma_fp8: None,
+        register_mma_ampere_float: None,
+        sparse_mma_integer: None,
+        sparse_mma_f8f6f4_f32: None,
+        sparse_mma_f8f6f4_f16: None,
+        prmt: None,
+        packed_conversion_fp8: None,
+        packed_conversion_fp8_f16x2: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cluster_sreg: None,
+        cluster_barrier: None,
+        mbarrier_extended: None,
+        special_registers: None,
+        debug_control: None,
+        threadfence: None,
+        cluster_memory: None,
+        stmatrix: None,
+        clc: None,
+        wgmma_controls: Some(test_wgmma_control_admission()),
+        tma: None,
+        tcgen05: None,
+    };
+    let path = Path::new("intrinsics/overlay/wgmma_control.toml");
+    validate_overlay_shard_schema_with_max(&shard, path, WGMMA_CONTROL_SHARD_SCHEMA).unwrap();
+    let mut old = shard;
+    old.schema -= 1;
+    assert!(
+        validate_overlay_shard_schema_with_max(&old, path, WGMMA_CONTROL_SHARD_SCHEMA)
+            .unwrap_err()
+            .to_string()
+            .contains("requires overlay shard schema 38")
+    );
+}
+
+#[test]
+fn cp_async_copy_recipe_admits_only_classic_llvm_forms() {
+    let cases = [
+        (
+            CpAsyncCachePolicy::Ca,
+            CpAsyncCopySize::B4,
+            CpAsyncSourceSize::Full,
+            Some("cp_async_ca_4"),
+        ),
+        (
+            CpAsyncCachePolicy::Ca,
+            CpAsyncCopySize::B4,
+            CpAsyncSourceSize::Runtime,
+            Some("cp_async_ca_zfill_4"),
+        ),
+        (
+            CpAsyncCachePolicy::Ca,
+            CpAsyncCopySize::B8,
+            CpAsyncSourceSize::Full,
+            Some("cp_async_ca_8"),
+        ),
+        (
+            CpAsyncCachePolicy::Ca,
+            CpAsyncCopySize::B8,
+            CpAsyncSourceSize::Runtime,
+            Some("cp_async_ca_zfill_8"),
+        ),
+        (
+            CpAsyncCachePolicy::Ca,
+            CpAsyncCopySize::B16,
+            CpAsyncSourceSize::Full,
+            Some("cp_async_ca_16"),
+        ),
+        (
+            CpAsyncCachePolicy::Ca,
+            CpAsyncCopySize::B16,
+            CpAsyncSourceSize::Runtime,
+            Some("cp_async_ca_zfill_16"),
+        ),
+        (
+            CpAsyncCachePolicy::Cg,
+            CpAsyncCopySize::B4,
+            CpAsyncSourceSize::Full,
+            None,
+        ),
+        (
+            CpAsyncCachePolicy::Cg,
+            CpAsyncCopySize::B4,
+            CpAsyncSourceSize::Runtime,
+            None,
+        ),
+        (
+            CpAsyncCachePolicy::Cg,
+            CpAsyncCopySize::B8,
+            CpAsyncSourceSize::Full,
+            None,
+        ),
+        (
+            CpAsyncCachePolicy::Cg,
+            CpAsyncCopySize::B8,
+            CpAsyncSourceSize::Runtime,
+            None,
+        ),
+        (
+            CpAsyncCachePolicy::Cg,
+            CpAsyncCopySize::B16,
+            CpAsyncSourceSize::Full,
+            Some("cp_async_cg_16"),
+        ),
+        (
+            CpAsyncCachePolicy::Cg,
+            CpAsyncCopySize::B16,
+            CpAsyncSourceSize::Runtime,
+            Some("cp_async_cg_zfill_16"),
+        ),
+    ];
+
+    for (cache_policy, copy_size, source_size, expected) in cases {
+        let copy = crate::model::CpAsyncCopy {
+            cache_policy,
+            copy_size,
+            source_size,
+            adapter: if source_size == CpAsyncSourceSize::Runtime {
+                CpAsyncAdapter::DirectPointersAndSourceSize
+            } else {
+                CpAsyncAdapter::DirectPointers
+            },
+            runtime_validation: RuntimeValidation::Unexecuted,
+        };
+        assert_eq!(
+            cp_async_copy_recipe(&copy).map(|recipe| recipe.id),
+            expected
+        );
+    }
+}
+
+#[test]
+fn pinned_cp_async_records_match_the_closed_recipes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect();
+    let policies: Vec<_> = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| matches!(record.family.as_str(), "cp_async_copy" | "cp_async_control"))
+        .collect();
+
+    assert_eq!(policies.len(), 11);
+    for policy in policies {
+        let declaration = declarations[policy.source_record.as_deref().unwrap()];
+        validate_imported_policy(policy, declaration).unwrap();
+    }
+}
+
+#[test]
+fn pinned_cp_async_mbarrier_records_match_the_closed_recipes() {
+    let records = pinned_cp_async_mbarrier_records();
+    assert_eq!(records.len(), 4);
+
+    for (policy, declaration) in records.values() {
+        validate_imported_policy(policy, declaration).unwrap();
+    }
+}
+
+#[test]
+fn cp_async_mbarrier_recipes_fail_closed() {
+    let records = pinned_cp_async_mbarrier_records();
+    let (arrive, declaration) = &records["cp_async_mbarrier_arrive"];
+    let reject = |policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic, expected: &str| {
+        let error = validate_imported_policy(policy, declaration).unwrap_err();
+        let message = error.to_string();
+        assert!(message.contains(expected), "unexpected error: {message}");
+    };
+
+    let mut wrong_symbol = arrive.clone();
+    wrong_symbol.llvm_symbol = Some("llvm.nvvm.cp.async.mbarrier.changed".into());
+    reject(&wrong_symbol, declaration, "LLVM symbol mismatch");
+
+    let mut wrong_signature = arrive.clone();
+    wrong_signature.rust_arguments = vec!["*const u64".into()];
+    reject(
+        &wrong_signature,
+        declaration,
+        "closed cp.async mbarrier Rust API",
+    );
+
+    let mut wrong_operation = arrive.clone();
+    wrong_operation
+        .cp_async_mbarrier
+        .as_mut()
+        .unwrap()
+        .operation = CpAsyncMbarrierOperation::ArriveNoInc;
+    reject(&wrong_operation, declaration, "identity does not match");
+
+    let mut wrong_state_space = arrive.clone();
+    wrong_state_space
+        .cp_async_mbarrier
+        .as_mut()
+        .unwrap()
+        .state_space = CpAsyncMbarrierStateSpace::Shared;
+    reject(&wrong_state_space, declaration, "identity does not match");
+
+    let mut wrong_adapter = arrive.clone();
+    wrong_adapter.cp_async_mbarrier.as_mut().unwrap().adapter =
+        CpAsyncMbarrierAdapter::PointerToVoid;
+    wrong_adapter.rust_result = "u64".into();
+    reject(
+        &wrong_adapter,
+        declaration,
+        "closed cp.async mbarrier Rust API",
+    );
+
+    let mut executed_without_evidence = arrive.clone();
+    executed_without_evidence
+        .cp_async_mbarrier
+        .as_mut()
+        .unwrap()
+        .runtime_validation = RuntimeValidation::Executed;
+    reject(
+        &executed_without_evidence,
+        declaration,
+        "unrecorded cp.async mbarrier runtime validation",
+    );
+
+    let mut wrong_properties = declaration.clone();
+    wrong_properties.properties.pop();
+    reject(arrive, &wrong_properties, "cp.async mbarrier properties");
+
+    let mut wrong_selection = declaration.clone();
+    wrong_selection.selections[0].source_record = "CP_ASYNC_MBARRIER_CHANGED".into();
+    reject(
+        arrive,
+        &wrong_selection,
+        "imported cp.async mbarrier selection changed",
+    );
+
+    let mut wrong_floor = arrive.clone();
+    wrong_floor.minimum_sm = Some("sm_90".into());
+    reject(&wrong_floor, declaration, "effects or target floor");
+
+    let mut wrong_llvm_route = arrive.clone();
+    wrong_llvm_route
+        .backend_lowerings
+        .iter_mut()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+        .unwrap()
+        .mechanism = BackendLoweringMechanism::InlinePtx;
+    reject(&wrong_llvm_route, declaration, "reviewed typed-LLVM");
+
+    let mut wrong_lib_route = arrive.clone();
+    wrong_lib_route
+        .backend_lowerings
+        .iter_mut()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
+        .unwrap()
+        .mechanism = BackendLoweringMechanism::TypedNvvm;
+    reject(&wrong_lib_route, declaration, "reviewed typed-LLVM");
+
+    let mut mixed_family = arrive.clone();
+    mixed_family.cp_async_control = Some(crate::model::CpAsyncControl {
+        operation: CpAsyncControlOperation::CommitGroup,
+        adapter: CpAsyncControlAdapter::NoOperands,
+        runtime_validation: RuntimeValidation::Unexecuted,
+    });
+    reject(
+        &mixed_family,
+        declaration,
+        "mixes another generated-family contract",
+    );
+}
+
+#[test]
+fn pinned_mbarrier_basic_records_match_the_closed_recipes() {
+    let records = pinned_mbarrier_basic_records();
+    assert_eq!(records.len(), 4);
+
+    for (policy, declaration) in records.values() {
+        validate_imported_policy(policy, declaration).unwrap();
+    }
+}
+
+#[test]
+fn mbarrier_basic_recipes_fail_closed() {
+    let records = pinned_mbarrier_basic_records();
+    let (init, init_declaration) = &records["mbarrier_init"];
+    let reject = |policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic, expected: &str| {
+        let error = validate_imported_policy(policy, declaration).unwrap_err();
+        let message = error.to_string();
+        assert!(message.contains(expected), "unexpected error: {message}");
+    };
+
+    let mut wrong_symbol = init.clone();
+    wrong_symbol.llvm_symbol = Some("llvm.nvvm.mbarrier.init.changed".into());
+    reject(&wrong_symbol, init_declaration, "LLVM symbol mismatch");
+
+    let mut wrong_signature = init.clone();
+    wrong_signature.rust_arguments = vec!["*mut u32".into(), "u32".into()];
+    reject(
+        &wrong_signature,
+        init_declaration,
+        "unsafe mbarrier raw and compatibility API",
+    );
+
+    let mut wrong_operation = init.clone();
+    wrong_operation.mbarrier_basic.as_mut().unwrap().operation = MbarrierBasicOperation::Arrive;
+    reject(
+        &wrong_operation,
+        init_declaration,
+        "operation, state space, and adapter disagree",
+    );
+
+    let mut wrong_adapter = init.clone();
+    wrong_adapter.mbarrier_basic.as_mut().unwrap().adapter =
+        MbarrierBasicAdapter::InvalPointerToVoid;
+    reject(
+        &wrong_adapter,
+        init_declaration,
+        "operation, state space, and adapter disagree",
+    );
+
+    let mut executed_without_evidence = init.clone();
+    executed_without_evidence
+        .mbarrier_basic
+        .as_mut()
+        .unwrap()
+        .runtime_validation = RuntimeValidation::Executed;
+    reject(
+        &executed_without_evidence,
+        init_declaration,
+        "unrecorded mbarrier runtime validation",
+    );
+
+    let mut wrong_properties = init_declaration.clone();
+    wrong_properties.properties.pop();
+    reject(init, &wrong_properties, "mbarrier properties");
+
+    let mut wrong_selection = init_declaration.clone();
+    wrong_selection.selections[0].source_record = "MBARRIER_INIT_CHANGED".into();
+    reject(
+        init,
+        &wrong_selection,
+        "imported mbarrier selection changed",
+    );
+
+    let mut wrong_ptx_floor = init.clone();
+    wrong_ptx_floor.minimum_ptx = "7.1".into();
+    reject(
+        &wrong_ptx_floor,
+        init_declaration,
+        "effects or target floor",
+    );
+
+    let mut wrong_sm_floor = init.clone();
+    wrong_sm_floor.minimum_sm = Some("sm_90".into());
+    reject(&wrong_sm_floor, init_declaration, "effects or target floor");
+
+    let mut wrong_llvm_route = init.clone();
+    wrong_llvm_route
+        .backend_lowerings
+        .iter_mut()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+        .unwrap()
+        .mechanism = BackendLoweringMechanism::InlinePtx;
+    reject(
+        &wrong_llvm_route,
+        init_declaration,
+        "reviewed mbarrier backend routes",
+    );
+
+    let mut wrong_lib_nvvm_route = init.clone();
+    wrong_lib_nvvm_route
+        .backend_lowerings
+        .iter_mut()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
+        .unwrap()
+        .mechanism = BackendLoweringMechanism::TypedNvvm;
+    reject(
+        &wrong_lib_nvvm_route,
+        init_declaration,
+        "reviewed mbarrier backend routes",
+    );
+
+    let mut route_with_unreviewed_floor = init.clone();
+    route_with_unreviewed_floor.backend_lowerings[0].minimum_sm = Some("sm_90".into());
+    reject(
+        &route_with_unreviewed_floor,
+        init_declaration,
+        "reviewed mbarrier backend routes",
+    );
+
+    let mut mixed_family = init.clone();
+    mixed_family.cp_async_control = Some(crate::model::CpAsyncControl {
+        operation: CpAsyncControlOperation::CommitGroup,
+        adapter: CpAsyncControlAdapter::NoOperands,
+        runtime_validation: RuntimeValidation::Unexecuted,
+    });
+    reject(
+        &mixed_family,
+        init_declaration,
+        "mixes another generated-family contract",
+    );
+}
+
+#[test]
+fn redux_contract_validates_effects_participation_and_operand_adapter() {
+    let valid = redux_policy();
+    let imported = redux_declaration();
+    validate_imported_policy(&valid, &imported).unwrap();
+
+    assert_eq!(
+        valid.redux.as_ref().unwrap().adapter,
+        ReduxAdapter::MaskValueToSourceMemberMask
+    );
+
+    let mut missing_contract = valid.clone();
+    missing_contract.redux = None;
+    assert!(
+        validate_imported_policy(&missing_contract, &imported)
+            .unwrap_err()
+            .to_string()
+            .contains("closed redux contract")
+    );
+
+    let mut wrong_effect = valid.clone();
+    wrong_effect.memory = "none".into();
+    assert!(
+        validate_imported_policy(&wrong_effect, &imported)
+            .unwrap_err()
+            .to_string()
+            .contains("redux effects")
+    );
+
+    let mut missing_imported_effect = imported;
+    missing_imported_effect
+        .properties
+        .retain(|property| property != "IntrInaccessibleMemOnly");
+    assert!(
+        validate_imported_policy(&valid, &missing_imported_effect)
+            .unwrap_err()
+            .to_string()
+            .contains("memory and convergence effects")
+    );
+}
+
+#[test]
+fn every_redux_variant_matches_its_closed_recipe() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    assert_eq!(imported.schema, IMPORTED_SCHEMA);
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect();
+    let redux: Vec<_> = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "redux")
+        .collect();
+    assert_eq!(redux.len(), 16);
+
+    for policy in redux {
+        let declaration = declarations
+            .get(policy.source_record.as_deref().unwrap())
+            .unwrap();
+        validate_imported_policy(policy, declaration).unwrap();
+    }
+
+    let mut mismatched = packed_policy("redux_sync_min_u32");
+    mismatched.redux.as_mut().unwrap().operation = ReduxOperation::Umax;
+    let declaration = declarations["int_nvvm_redux_sync_umin"];
+    assert!(
+        validate_imported_policy(&mismatched, declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("closed operation recipe")
+    );
+}
+
+#[test]
+fn every_dot_product_variant_matches_its_closed_recipe() {
+    let variants = [
+        (
+            DotProductOperation::Dp4a,
+            DotProductSignedness::Signed,
+            "dp4a_s32",
+            "int_nvvm_idp4a_s_s",
+            "integer.dot_product.dp4a.s32",
+        ),
+        (
+            DotProductOperation::Dp4a,
+            DotProductSignedness::Unsigned,
+            "dp4a_u32",
+            "int_nvvm_idp4a_u_u",
+            "integer.dot_product.dp4a.u32",
+        ),
+        (
+            DotProductOperation::Dp2a,
+            DotProductSignedness::Signed,
+            "dp2a_s32",
+            "int_nvvm_idp2a_s_s",
+            "integer.dot_product.dp2a.lo.s32",
+        ),
+        (
+            DotProductOperation::Dp2a,
+            DotProductSignedness::Unsigned,
+            "dp2a_u32",
+            "int_nvvm_idp2a_u_u",
+            "integer.dot_product.dp2a.lo.u32",
+        ),
+    ];
+
+    for (operation, signedness, id, source_record, operation_key) in variants {
+        let policy = dot_product_policy(operation, signedness);
+        let declaration = dot_product_declaration(operation, signedness);
+        assert_eq!(policy.id, id);
+        assert_eq!(policy.source_record.as_deref(), Some(source_record));
+        assert_eq!(policy.operation_key, operation_key);
+        validate_imported_policy(&policy, &declaration).unwrap();
+    }
+}
+
+#[test]
+fn pinned_dot_product_records_match_the_reviewed_overlay() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect();
+    let dot_products: Vec<_> = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "dotprod")
+        .collect();
+    assert_eq!(dot_products.len(), 4);
+
+    for policy in dot_products {
+        let declaration = declarations[policy.source_record.as_deref().unwrap()];
+        validate_imported_policy(policy, declaration).unwrap();
+        let selected: Vec<_> = declaration
+            .selections
+            .iter()
+            .filter(|selection| selection_matches_policy(policy, selection).unwrap())
+            .collect();
+        assert_eq!(selected.len(), 1);
+        if policy.id.starts_with("dp2a") {
+            assert_eq!(selected[0].constraints.immediate_bindings[0].value, 0);
+        }
+    }
+}
+
+#[test]
+fn dp2a_selects_only_the_reviewed_low_half_binding() {
+    let policy = dot_product_policy(DotProductOperation::Dp2a, DotProductSignedness::Signed);
+    let declaration =
+        dot_product_declaration(DotProductOperation::Dp2a, DotProductSignedness::Signed);
+    let resolved = resolve_record(
+        &policy,
+        resolve_policy_source(&policy).unwrap(),
+        Some(&declaration),
+        &dot_product_evidence(&policy),
+        "test",
+        "LLVM version test",
+        "0123456789abcdef",
+        vec![],
+        1,
+    )
+    .unwrap();
+
+    assert_eq!(resolved.selections.len(), 1);
+    assert_eq!(resolved.selections[0].source_record, "DOT2_lo");
+    assert_eq!(
+        resolved.selections[0].constraints.immediate_bindings,
+        [crate::model::ImportedImmediateBinding {
+            argument_index: 2,
+            value: 0,
+        }]
+    );
+    assert_eq!(
+        resolved.dot_product.as_ref().unwrap().adapter,
+        DotProductAdapter::InsertLowHalfFalse
+    );
+
+    let mut wrong_binding = declaration;
+    wrong_binding.selections[1].constraints.immediate_bindings[0].value = -1;
+    let error = validate_imported_policy(&policy, &wrong_binding).unwrap_err();
+    assert!(error.to_string().contains("does not agree"));
+}
+
+#[test]
+fn dot_product_recipe_rejects_unreviewed_api_and_adapter_changes() {
+    let valid = dot_product_policy(DotProductOperation::Dp2a, DotProductSignedness::Unsigned);
+    let declaration =
+        dot_product_declaration(DotProductOperation::Dp2a, DotProductSignedness::Unsigned);
+
+    let mut wrong_adapter = valid.clone();
+    wrong_adapter.dot_product.as_mut().unwrap().adapter = DotProductAdapter::DirectThreeOperands;
+    assert!(
+        validate_imported_policy(&wrong_adapter, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("source adapter")
+    );
+
+    let mut must_use = valid.clone();
+    must_use.must_use = true;
+    assert!(
+        validate_imported_policy(&must_use, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("non-must-use")
+    );
+
+    let mut wrong_llvm_signature = valid;
+    wrong_llvm_signature.llvm_arguments = vec!["i32".into(); 3];
+    assert!(
+        validate_imported_policy(&wrong_llvm_signature, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("LLVM argument signature mismatch")
+    );
+}
+
+#[test]
+fn dot_product_target_predicate_is_closed_to_ptx50_and_sm61() {
+    let policy = dot_product_policy(DotProductOperation::Dp4a, DotProductSignedness::Signed);
+    let selection =
+        &dot_product_declaration(DotProductOperation::Dp4a, DotProductSignedness::Signed)
+            .selections[0];
+    validate_selected_target_predicates(&policy, selection).unwrap();
+
+    let mut wrong_ptx = policy.clone();
+    wrong_ptx.minimum_ptx = "5.1".into();
+    assert!(
+        validate_selected_target_predicates(&wrong_ptx, selection)
+            .unwrap_err()
+            .to_string()
+            .contains("minimum PTX")
+    );
+
+    let mut wrong_sm = policy;
+    wrong_sm.minimum_sm = Some("sm_60".into());
+    assert!(
+        validate_selected_target_predicates(&wrong_sm, selection)
+            .unwrap_err()
+            .to_string()
+            .contains("minimum SM")
+    );
+}
+
+#[test]
+fn return_range_properties_are_half_open_and_unique() {
+    let facts =
+        imported_result_facts(&["NoUndef<ret>".into(), "Range<ret,1,1025>".into()]).unwrap();
+    assert!(facts.no_undef);
+    let range = facts.range.unwrap();
+    assert_eq!(range.lower, "1");
+    assert_eq!(range.upper_exclusive, "1025");
+
+    let duplicate =
+        imported_result_facts(&["Range<ret,0,32>".into(), "Range<ret,0,64>".into()]).unwrap_err();
+    assert!(duplicate.to_string().contains("duplicate return range"));
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs
new file mode 100644
index 0000000000..11d336b15e
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs
@@ -0,0 +1,2064 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogHardwareAlternative, CatalogHardwareTarget,
+    EvidenceArtifactKind, EvidenceStageKind, ImportedFile, IntrinsicBackend, OverlayIntrinsic,
+    OverlayShardFile, PreSm70MemberMaskRule, RegisterMmaAccumulator, RegisterMmaAdapter,
+    RegisterMmaCompatibilitySource, RegisterMmaElement, RegisterMmaKind, RegisterMmaOperation,
+    RegisterMmaOverflow, RegisterMmaShape, RuntimeValidation, SparseMmaAccumulator,
+    SparseMmaAdapter, SparseMmaElement, SparseMmaLlvmAdapter, SparseMmaMetadata, SparseMmaOverflow,
+    SparseMmaSelector, SparseMmaShape, WarpBarrierAdapter, WarpBarrierMaskEncoding,
+    WarpBarrierMemoryOrdering, WarpBarrierParticipation,
+};
+use crate::ptx::OperandPattern;
+use crate::util::read_json;
+use std::collections::{BTreeMap, BTreeSet};
+use std::fs;
+use std::path::Path;
+
+use super::fixtures::*;
+use crate::resolve::driver::*;
+use crate::resolve::families::*;
+use crate::resolve::guards::*;
+use crate::resolve::overlay::*;
+
+#[test]
+fn stmatrix_admission_is_closed_and_uses_schema_35() {
+    let shard = |schema| {
+        toml::from_str::<OverlayShardFile>(&format!(
+            r#"
+schema = {schema}
+family = "stmatrix"
+
+[stmatrix]
+llvm_evidence_profile = "llvm-test"
+libnvvm_evidence_profile = "libnvvm-test"
+runtime_validation = "unexecuted"
+
+[[stmatrix.variant]]
+abi_id = "i0301"
+multiplicity = "x2"
+layout = "normal"
+
+[[stmatrix.variant]]
+abi_id = "i0302"
+multiplicity = "x2"
+layout = "transposed"
+
+[[stmatrix.variant]]
+abi_id = "i0303"
+multiplicity = "x4"
+layout = "normal"
+
+[[stmatrix.variant]]
+abi_id = "i0304"
+multiplicity = "x4"
+layout = "transposed"
+"#
+        ))
+        .unwrap()
+    };
+    let path = Path::new("intrinsics/overlay/stmatrix.toml");
+
+    let old = shard(STMATRIX_SHARD_SCHEMA - 1);
+    assert!(
+        validate_overlay_shard_schema(&old, path)
+            .unwrap_err()
+            .to_string()
+            .contains("requires overlay shard schema 35")
+    );
+
+    let current = shard(STMATRIX_SHARD_SCHEMA);
+    validate_overlay_shard_schema(&current, path).unwrap();
+    let admission = current.stmatrix.unwrap();
+    let records = expand_stmatrix_admission(&admission).unwrap();
+    assert_eq!(
+        records
+            .iter()
+            .map(|record| (record.abi_id.as_str(), record.id.as_str()))
+            .collect::<Vec<_>>(),
+        [
+            ("i0301", "stmatrix_m8n8_x2_b16"),
+            ("i0302", "stmatrix_m8n8_x2_trans_b16"),
+            ("i0303", "stmatrix_m8n8_x4_b16"),
+            ("i0304", "stmatrix_m8n8_x4_trans_b16"),
+        ]
+    );
+
+    let mut reordered = admission.clone();
+    reordered.variants.swap(0, 1);
+    assert!(expand_stmatrix_admission(&reordered).is_err());
+
+    let mut wrong_id = admission.clone();
+    wrong_id.variants[0].abi_id = "i0302".into();
+    assert!(expand_stmatrix_admission(&wrong_id).is_err());
+
+    let mut executed = admission;
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_stmatrix_admission(&executed).is_err());
+}
+
+#[test]
+fn pinned_stmatrix_records_match_llvm_and_reject_contract_drift() {
+    let records = expand_stmatrix_admission(&test_stmatrix_admission()).unwrap();
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+
+    for record in &records {
+        let declaration = declarations[record.source_record.as_deref().unwrap()];
+        assert!(declaration.selections.is_empty());
+        validate_imported_policy(record, declaration).unwrap();
+    }
+
+    let declaration = declarations["int_nvvm_stmatrix_sync_aligned_m8n8_x2_b16"];
+    let mut changed = records[0].clone();
+    changed.memory = "read_write".into();
+    assert!(validate_imported_policy(&changed, declaration).is_err());
+
+    let mut changed = records[0].clone();
+    changed.convergent = false;
+    assert!(validate_imported_policy(&changed, declaration).is_err());
+
+    let mut changed = records[0].clone();
+    changed.backend_lowerings[0].mechanism = BackendLoweringMechanism::InlinePtx;
+    assert!(validate_imported_policy(&changed, declaration).is_err());
+
+    let mut changed = records[0].clone();
+    changed.minimum_sm = Some("sm_80".into());
+    assert!(validate_imported_policy(&changed, declaration).is_err());
+}
+
+#[test]
+fn compact_f8f6f4_axes_require_the_exact_canonical_matrix() {
+    let records = expand_sparse_mma_f8f6f4_admission(&test_f8f6f4_admission()).unwrap();
+    assert_eq!(records.len(), 25);
+    assert_eq!(
+        records[0].id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
+    );
+    assert_eq!(records[0].rust_arguments[0], "[f32; 4]");
+    assert_eq!(records[0].dialect_results, ["f32"; 4]);
+    assert_eq!(records[0].llvm_results, ["f32"; 4]);
+
+    let mut missing = test_f8f6f4_admission();
+    missing.a_elements.pop();
+    assert!(expand_sparse_mma_f8f6f4_admission(&missing).is_err());
+
+    let mut duplicate = test_f8f6f4_admission();
+    duplicate.a_elements[4] = SparseMmaElement::E4m3;
+    assert!(expand_sparse_mma_f8f6f4_admission(&duplicate).is_err());
+
+    let mut extra = test_f8f6f4_admission();
+    extra.b_elements.push(SparseMmaElement::S4);
+    assert!(expand_sparse_mma_f8f6f4_admission(&extra).is_err());
+
+    let mut unsorted = test_f8f6f4_admission();
+    unsorted.b_elements.swap(0, 1);
+    assert!(expand_sparse_mma_f8f6f4_admission(&unsorted).is_err());
+
+    let mut wrong_count = test_f8f6f4_admission();
+    wrong_count.product_count = 24;
+    assert!(expand_sparse_mma_f8f6f4_admission(&wrong_count).is_err());
+}
+
+#[test]
+fn compact_sparse_f8f6f4_f16_admission_is_closed_and_ordered() {
+    let admission = test_sparse_mma_f8f6f4_f16_admission();
+    let records = expand_sparse_mma_f8f6f4_f16_admission(&admission).unwrap();
+    assert_eq!(records.len(), 25);
+    assert!(records.iter().all(|record| record.abi_id.is_empty()));
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let mut bound = overlay_file(records.clone());
+    bind_pinned_abi_ids(&repo_root, &mut bound);
+    assert_eq!(
+        bound
+            .intrinsics
+            .iter()
+            .map(|record| record.abi_id.clone())
+            .collect::<Vec<_>>(),
+        (525..=549)
+            .map(|id| format!("i{id:04}"))
+            .collect::<Vec<_>>()
+    );
+    assert_eq!(
+        records[0].id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
+    );
+    assert_eq!(
+        records[24].id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
+    );
+    let first = &records[0];
+    assert_eq!(
+        first.source_record.as_deref(),
+        Some("int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e2m1_f16")
+    );
+    assert_eq!(
+        first.llvm_symbol.as_deref(),
+        Some("llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e2m1.f16")
+    );
+    assert_eq!(
+        first.rust_arguments,
+        ["[u32; 2]", "[u32; 4]", "[u32; 4]", "u32", "u32"]
+    );
+    assert_eq!(first.rust_result, "[u32; 2]");
+    assert_eq!(first.dialect_results, ["i32"; 2]);
+    assert_eq!(first.llvm_results, ["v2f16"; 2]);
+    assert_eq!(
+        first.llvm_arguments,
+        [
+            "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "v2f16", "v2f16", "i32", "i32"
+        ]
+    );
+    assert_eq!(first.minimum_ptx, "8.7");
+    assert_eq!(first.minimum_sm, None);
+    assert_eq!(first.targets, SPARSE_MMA_F8F6F4_TARGETS);
+    assert!(first.convergent && !first.pure);
+    assert!(first.backend_lowerings.iter().all(|route| {
+        route.mechanism == BackendLoweringMechanism::InlinePtx
+            && route.minimum_ptx.as_deref() == Some("8.7")
+            && route.minimum_sm.is_none()
+    }));
+    let mma = first.sparse_mma.as_ref().unwrap();
+    assert_eq!(mma.accumulator, SparseMmaAccumulator::F16);
+    assert_eq!(mma.selector, SparseMmaSelector::ImmediateZero);
+    assert_eq!(
+        mma.adapter,
+        SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32
+    );
+    assert_eq!(
+        mma.llvm_adapter,
+        SparseMmaLlvmAdapter::A4I32B4I32C2V2F16MetadataI32SelectorI32ToD2V2F16
+    );
+    assert_eq!(
+        first.compatibility_rust_paths,
+        ["cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"]
+    );
+    assert_eq!(
+        first.expected_ptx.operands,
+        [
+            OperandPattern::RegisterList { length: 2 },
+            OperandPattern::RegisterList { length: 4 },
+            OperandPattern::RegisterList { length: 4 },
+            OperandPattern::RegisterList { length: 2 },
+            OperandPattern::Register,
+            OperandPattern::Immediate,
+        ]
+    );
+
+    let mut missing = admission.clone();
+    missing.a_elements.pop();
+    assert!(expand_sparse_mma_f8f6f4_f16_admission(&missing).is_err());
+
+    let mut reordered = admission.clone();
+    reordered.b_elements.swap(0, 1);
+    assert!(expand_sparse_mma_f8f6f4_f16_admission(&reordered).is_err());
+
+    let mut wrong_count = admission.clone();
+    wrong_count.product_count = 24;
+    assert!(expand_sparse_mma_f8f6f4_f16_admission(&wrong_count).is_err());
+
+    let mut legacy_first_id = admission.clone();
+    legacy_first_id._legacy_first_abi_id = Some("i9999".into());
+    assert!(
+        expand_sparse_mma_f8f6f4_f16_admission(&legacy_first_id)
+            .unwrap()
+            .iter()
+            .all(|record| record.abi_id.is_empty())
+    );
+
+    let mut missing_evidence = admission.clone();
+    missing_evidence.llvm_evidence_profile.clear();
+    assert!(expand_sparse_mma_f8f6f4_f16_admission(&missing_evidence).is_err());
+
+    let mut executed = admission;
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_sparse_mma_f8f6f4_f16_admission(&executed).is_err());
+}
+
+#[test]
+fn sparse_f8f6f4_f16_candidate_floor_uses_the_resolved_policy() {
+    let policy = expand_sparse_mma_f8f6f4_f16_admission(&test_sparse_mma_f8f6f4_f16_admission())
+        .unwrap()
+        .remove(0);
+    let (_, requirement) = candidate_llvm_route(&policy).unwrap();
+
+    validate_candidate_target(&policy, &requirement, "sm_120a", "+ptx87").unwrap();
+    validate_candidate_target(&policy, &requirement, "sm_120f", "+ptx88").unwrap();
+    validate_candidate_target(&policy, &requirement, "sm_121a", "+ptx88").unwrap();
+    validate_candidate_target(&policy, &requirement, "sm_121f", "+ptx88").unwrap();
+    for target in ["sm_120f", "sm_121a", "sm_121f"] {
+        assert!(
+            validate_candidate_target(&policy, &requirement, target, "+ptx87").is_err(),
+            "{target} must require PTX 8.8"
+        );
+    }
+}
+
+#[test]
+fn compact_dense_f8f6f4_admission_is_closed() {
+    for (accumulator, first, first_id, last_id, rust_arguments, rust_result, adapter) in [
+        (
+            RegisterMmaAccumulator::F32,
+            454,
+            "mma_m16n8k32_f32_e2m1_e2m1",
+            "mma_m16n8k32_f32_e5m2_e5m2",
+            ["[f32; 4]", "[u32; 4]", "[u32; 2]"],
+            "[f32; 4]",
+            RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32,
+        ),
+        (
+            RegisterMmaAccumulator::F16,
+            479,
+            "mma_m16n8k32_f16_e2m1_e2m1",
+            "mma_m16n8k32_f16_e5m2_e5m2",
+            ["[u32; 2]", "[u32; 4]", "[u32; 2]"],
+            "[u32; 2]",
+            RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32,
+        ),
+    ] {
+        let admission = test_register_mma_f8f6f4_admission(accumulator);
+        let records = expand_register_mma_f8f6f4_admission(&admission, accumulator).unwrap();
+        assert_eq!(records.len(), 25);
+        assert!(records.iter().all(|record| record.abi_id.is_empty()));
+        let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+        let mut bound = overlay_file(records.clone());
+        bind_pinned_abi_ids(&repo_root, &mut bound);
+        assert_eq!(
+            bound
+                .intrinsics
+                .iter()
+                .map(|record| record.abi_id.clone())
+                .collect::<Vec<_>>(),
+            (first..first + 25)
+                .map(|id| format!("i{id:04}"))
+                .collect::<Vec<_>>()
+        );
+        assert_eq!(records[0].id, first_id);
+        assert_eq!(records[24].id, last_id);
+        assert!(records.iter().all(|record| {
+            record.rust_arguments == rust_arguments
+                && record.rust_result == rust_result
+                && record.register_mma.as_ref().unwrap().adapter == adapter
+                && record.targets == REGISTER_MMA_F8F6F4_TARGETS
+                && record.minimum_ptx == "8.7"
+                && record.minimum_sm.is_none()
+                && record.backend_lowerings.len() == 2
+                && record
+                    .backend_lowerings
+                    .iter()
+                    .all(|route| route.mechanism == BackendLoweringMechanism::InlinePtx)
+        }));
+
+        let mut missing = admission.clone();
+        missing.a_elements.pop();
+        assert!(expand_register_mma_f8f6f4_admission(&missing, accumulator).is_err());
+
+        let mut reordered = admission.clone();
+        reordered.b_elements.swap(0, 1);
+        assert!(expand_register_mma_f8f6f4_admission(&reordered, accumulator).is_err());
+
+        let mut wrong_count = admission.clone();
+        wrong_count.product_count = 24;
+        assert!(expand_register_mma_f8f6f4_admission(&wrong_count, accumulator).is_err());
+
+        let mut legacy_first_id = admission.clone();
+        legacy_first_id._legacy_first_abi_id = Some("i9999".into());
+        assert!(
+            expand_register_mma_f8f6f4_admission(&legacy_first_id, accumulator)
+                .unwrap()
+                .iter()
+                .all(|record| record.abi_id.is_empty())
+        );
+
+        let mut reordered_targets = admission.clone();
+        reordered_targets.targets.swap(0, 1);
+        assert!(expand_register_mma_f8f6f4_admission(&reordered_targets, accumulator).is_err());
+
+        let mut missing_evidence = admission.clone();
+        missing_evidence.llvm_evidence_profile.clear();
+        assert!(expand_register_mma_f8f6f4_admission(&missing_evidence, accumulator).is_err());
+
+        let mut executed = admission;
+        executed.runtime_validation = RuntimeValidation::Executed;
+        assert!(expand_register_mma_f8f6f4_admission(&executed, accumulator).is_err());
+    }
+
+    let admission = test_register_mma_f8f6f4_admission(RegisterMmaAccumulator::F32);
+    assert!(expand_register_mma_f8f6f4_admission(&admission, RegisterMmaAccumulator::F64).is_err());
+}
+
+#[test]
+fn compact_standard_fp8_admission_is_closed_and_ordered() {
+    let admission = test_register_mma_fp8_admission();
+    let records = expand_register_mma_fp8_admission(&admission).unwrap();
+    assert_eq!(records.len(), 16);
+    assert!(records.iter().all(|record| record.abi_id.is_empty()));
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let mut bound = overlay_file(records.clone());
+    bind_pinned_abi_ids(&repo_root, &mut bound);
+    assert_eq!(
+        bound
+            .intrinsics
+            .iter()
+            .map(|record| record.abi_id.clone())
+            .collect::<Vec<_>>(),
+        (504..=519)
+            .map(|id| format!("i{id:04}"))
+            .collect::<Vec<_>>()
+    );
+
+    let mut index = 0;
+    for &shape in &REGISTER_MMA_FP8_SHAPES {
+        let (shape_name, a_count, b_count) = register_mma_fp8_shape_contract(shape).unwrap();
+        for &accumulator in &REGISTER_MMA_FP8_ACCUMULATORS {
+            let (scalar, arguments, result, adapter, result_count) = match accumulator {
+                RegisterMmaAccumulator::F16 => (
+                    "f16",
+                    vec![
+                        "[u32; 2]".to_owned(),
+                        format!("[u32; {a_count}]"),
+                        if b_count == 1 {
+                            "u32".to_owned()
+                        } else {
+                            "[u32; 2]".to_owned()
+                        },
+                    ],
+                    "[u32; 2]",
+                    if shape == RegisterMmaShape::M16n8k16 {
+                        RegisterMmaAdapter::C2U32A2U32B1U32ToD2U32
+                    } else {
+                        RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32
+                    },
+                    2,
+                ),
+                RegisterMmaAccumulator::F32 => (
+                    "f32",
+                    vec![
+                        "[f32; 4]".to_owned(),
+                        format!("[u32; {a_count}]"),
+                        if b_count == 1 {
+                            "u32".to_owned()
+                        } else {
+                            "[u32; 2]".to_owned()
+                        },
+                    ],
+                    "[f32; 4]",
+                    if shape == RegisterMmaShape::M16n8k16 {
+                        RegisterMmaAdapter::C4F32A2U32B1U32ToD4F32
+                    } else {
+                        RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32
+                    },
+                    4,
+                ),
+                _ => unreachable!(),
+            };
+            for &a_element in &REGISTER_MMA_FP8_ELEMENTS {
+                for &b_element in &REGISTER_MMA_FP8_ELEMENTS {
+                    let record = &records[index];
+                    let a = register_mma_fp8_element_name(a_element).unwrap();
+                    let b = register_mma_fp8_element_name(b_element).unwrap();
+                    assert_eq!(record.id, format!("mma_{shape_name}_fp8_{scalar}_{a}_{b}"));
+                    assert_eq!(
+                        record.operation_key,
+                        format!(
+                            "matrix.mma.{shape_name}.row.col.standard_fp8.{scalar}.{a}.{b}.{scalar}"
+                        )
+                    );
+                    assert_eq!(
+                        record.source_record.as_deref(),
+                        Some(
+                            format!("int_nvvm_mma_{shape_name}_row_col_{scalar}_{a}_{b}_{scalar}")
+                                .as_str()
+                        )
+                    );
+                    assert_eq!(record.rust_arguments, arguments);
+                    assert_eq!(record.rust_result, result);
+                    assert_eq!(
+                        record.minimum_ptx,
+                        register_mma_fp8_minimum_ptx(shape, accumulator)
+                    );
+                    assert_eq!(record.minimum_sm.as_deref(), Some("sm_89"));
+                    assert_eq!(
+                        record.expected_ptx.operands,
+                        [result_count, a_count, b_count, result_count]
+                            .map(|length| OperandPattern::RegisterList { length })
+                    );
+                    let mma = record.register_mma.as_ref().unwrap();
+                    assert_eq!(mma.kind, Some(RegisterMmaKind::Standard));
+                    assert_eq!(mma.adapter, adapter);
+                    index += 1;
+                }
+            }
+        }
+    }
+    assert_eq!(index, records.len());
+
+    let mut reordered = admission.clone();
+    reordered.shapes.swap(0, 1);
+    assert!(expand_register_mma_fp8_admission(&reordered).is_err());
+    let mut reordered = admission.clone();
+    reordered.accumulators.swap(0, 1);
+    assert!(expand_register_mma_fp8_admission(&reordered).is_err());
+    let mut reordered = admission.clone();
+    reordered.a_elements.swap(0, 1);
+    assert!(expand_register_mma_fp8_admission(&reordered).is_err());
+    let mut reordered = admission.clone();
+    reordered.b_elements.swap(0, 1);
+    assert!(expand_register_mma_fp8_admission(&reordered).is_err());
+    let mut wrong = admission.clone();
+    wrong.product_count = 15;
+    assert!(expand_register_mma_fp8_admission(&wrong).is_err());
+    let mut legacy_first_id = admission.clone();
+    legacy_first_id._legacy_first_abi_id = Some("i9999".into());
+    assert!(
+        expand_register_mma_fp8_admission(&legacy_first_id)
+            .unwrap()
+            .iter()
+            .all(|record| record.abi_id.is_empty())
+    );
+    let mut wrong = admission;
+    wrong.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_register_mma_fp8_admission(&wrong).is_err());
+}
+
+#[test]
+fn compact_ampere_float_mma_admission_is_closed_and_ordered() {
+    let admission = test_register_mma_ampere_float_admission();
+    let records = expand_register_mma_ampere_float_admission(&admission).unwrap();
+    assert_eq!(records.len(), 5);
+    assert!(records.iter().all(|record| record.abi_id.is_empty()));
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let mut bound = overlay_file(records.clone());
+    bind_pinned_abi_ids(&repo_root, &mut bound);
+    assert_eq!(
+        bound
+            .intrinsics
+            .iter()
+            .map(|record| (record.abi_id.as_str(), record.id.as_str()))
+            .collect::<Vec<_>>(),
+        [
+            ("i0520", "mma_m16n8k4_f32_tf32"),
+            ("i0521", "mma_m16n8k8_f16_f16"),
+            ("i0522", "mma_m16n8k8_f32_bf16"),
+            ("i0523", "mma_m16n8k8_f32_f16"),
+            ("i0524", "mma_m16n8k16_f16_f16"),
+        ]
+    );
+    for record in &records {
+        assert_eq!(record.minimum_ptx, "7.0");
+        assert_eq!(record.minimum_sm.as_deref(), Some("sm_80"));
+        assert_eq!(record.backend_lowerings.len(), 2);
+        assert!(record.backend_lowerings.iter().all(|lowering| {
+            lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                && lowering.minimum_ptx.as_deref() == Some("7.0")
+                && lowering.minimum_sm.as_deref() == Some("sm_80")
+        }));
+        let mma = record.register_mma.as_ref().unwrap();
+        assert_eq!(mma.kind, None);
+        assert_eq!(
+            mma.compatibility_source,
+            RegisterMmaCompatibilitySource::GeneratedStub
+        );
+    }
+
+    let mut reordered = admission.clone();
+    reordered.variants.swap(0, 1);
+    assert!(expand_register_mma_ampere_float_admission(&reordered).is_err());
+    let mut legacy_first_id = admission.clone();
+    legacy_first_id._legacy_first_abi_id = Some("i9999".into());
+    assert!(
+        expand_register_mma_ampere_float_admission(&legacy_first_id)
+            .unwrap()
+            .iter()
+            .all(|record| record.abi_id.is_empty())
+    );
+    let mut wrong = admission.clone();
+    wrong.product_count = 4;
+    assert!(expand_register_mma_ampere_float_admission(&wrong).is_err());
+    let mut wrong = admission.clone();
+    wrong.llvm_evidence_profile.clear();
+    assert!(expand_register_mma_ampere_float_admission(&wrong).is_err());
+    let mut wrong = admission;
+    wrong.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_register_mma_ampere_float_admission(&wrong).is_err());
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let path = repo_root.join("intrinsics/overlay/register_mma_ampere_float.toml");
+    let bytes = fs::read(&path).unwrap();
+    let mut shard: OverlayShardFile = toml::from_slice(&bytes).unwrap();
+    validate_overlay_shard_schema(&shard, &path).unwrap();
+    shard.schema = REGISTER_MMA_AMPERE_FLOAT_SHARD_SCHEMA - 1;
+    assert!(
+        validate_overlay_shard_schema(&shard, &path)
+            .unwrap_err()
+            .to_string()
+            .contains("requires overlay shard schema 49")
+    );
+}
+
+#[test]
+fn ampere_float_mma_policies_match_llvm_and_fail_closed() {
+    let records =
+        expand_register_mma_ampere_float_admission(&test_register_mma_ampere_float_admission())
+            .unwrap();
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let mut overlay = overlay_file(records);
+    bind_pinned_abi_ids(&repo_root, &mut overlay);
+    let records = overlay.intrinsics;
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+
+    for record in &records {
+        let declaration = declarations[record.source_record.as_deref().unwrap()];
+        validate_imported_policy(record, declaration).unwrap();
+        let expected_predicates = match record.id.as_str() {
+            "mma_m16n8k4_f32_tf32" | "mma_m16n8k16_f16_f16" => [
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            _ => [
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+        };
+        assert_eq!(declaration.selections[0].predicates, expected_predicates);
+        assert_eq!(record.minimum_ptx, "7.0");
+        assert_eq!(record.minimum_sm.as_deref(), Some("sm_80"));
+    }
+
+    let valid = &records[2];
+    assert_eq!(valid.id, "mma_m16n8k8_f32_bf16");
+    assert_eq!(
+        declarations[valid.source_record.as_deref().unwrap()].selections[0].predicates,
+        [
+            "Subtarget->getPTXVersion() >= 65",
+            "Subtarget->getSmVersion() >= 75",
+        ]
+    );
+    assert_eq!(valid.minimum_ptx, "7.0");
+    assert_eq!(valid.minimum_sm.as_deref(), Some("sm_80"));
+    assert!(valid.backend_lowerings.iter().all(|lowering| {
+        lowering.minimum_ptx.as_deref() == Some("7.0")
+            && lowering.minimum_sm.as_deref() == Some("sm_80")
+    }));
+    let declaration = declarations[valid.source_record.as_deref().unwrap()];
+    let mut wrong = valid.clone();
+    wrong.minimum_ptx = "6.5".into();
+    assert!(validate_imported_policy(&wrong, declaration).is_err());
+    let mut wrong = valid.clone();
+    wrong.register_mma.as_mut().unwrap().adapter = RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32;
+    assert!(validate_imported_policy(&wrong, declaration).is_err());
+    let mut wrong = valid.clone();
+    wrong.register_mma.as_mut().unwrap().kind = Some(RegisterMmaKind::Standard);
+    assert!(validate_imported_policy(&wrong, declaration).is_err());
+    let mut wrong_declaration = declaration.clone();
+    wrong_declaration.selections[0].predicates[0] = "Subtarget->getPTXVersion() >= 70".into();
+    assert!(validate_imported_policy(valid, &wrong_declaration).is_err());
+}
+
+#[test]
+fn standard_fp8_policies_match_llvm_and_fail_closed() {
+    let records = expand_register_mma_fp8_admission(&test_register_mma_fp8_admission()).unwrap();
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let mut overlay = overlay_file(records);
+    bind_pinned_abi_ids(&repo_root, &mut overlay);
+    let records = overlay.intrinsics;
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+
+    for record in &records {
+        let declaration = declarations[record.source_record.as_deref().unwrap()];
+        validate_imported_policy(record, declaration).unwrap();
+        let mma = record.register_mma.as_ref().unwrap();
+        let source_floor = declaration.selections[0]
+            .predicates
+            .iter()
+            .find(|predicate| predicate.contains("getPTXVersion"))
+            .unwrap();
+        if mma.shape == RegisterMmaShape::M16n8k32 {
+            assert!(source_floor.ends_with(">= 84"));
+            if mma.accumulator == RegisterMmaAccumulator::F16 {
+                assert_eq!(record.minimum_ptx, "8.7");
+            } else {
+                assert_eq!(record.minimum_ptx, "8.4");
+            }
+        } else {
+            assert!(source_floor.ends_with(">= 87"));
+            assert_eq!(record.minimum_ptx, "8.7");
+        }
+    }
+
+    let valid = &records[0];
+    let declaration = declarations[valid.source_record.as_deref().unwrap()];
+    let mut wrong = valid.clone();
+    wrong.register_mma.as_mut().unwrap().kind = None;
+    assert!(validate_imported_policy(&wrong, declaration).is_err());
+    let mut wrong = valid.clone();
+    wrong.register_mma.as_mut().unwrap().adapter = RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32;
+    assert!(validate_imported_policy(&wrong, declaration).is_err());
+    let mut wrong_declaration = declaration.clone();
+    wrong_declaration.selections[0].predicates[1] = "Subtarget->getPTXVersion() >= 84".into();
+    assert!(validate_imported_policy(valid, &wrong_declaration).is_err());
+    let mut wrong = valid.clone();
+    wrong.minimum_ptx = "8.4".into();
+    assert!(validate_imported_policy(&wrong, declaration).is_err());
+
+    let mut old = expand_register_mma_f8f6f4_admission(
+        &test_register_mma_f8f6f4_admission(RegisterMmaAccumulator::F32),
+        RegisterMmaAccumulator::F32,
+    )
+    .unwrap()
+    .remove(18);
+    let mut standard = records[12].clone();
+    assert_ne!(old.id, standard.id);
+    standard.id = old.id.clone();
+    assert!(validate_unique_overlay(&[old.clone(), standard], 1).is_err());
+    old.register_mma.as_mut().unwrap().kind = Some(RegisterMmaKind::F8f6f4);
+    assert_eq!(
+        old.register_mma.as_ref().unwrap().kind,
+        Some(RegisterMmaKind::F8f6f4)
+    );
+}
+
+#[test]
+fn standard_fp8_resolves_exact_routes_and_target_floors() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let catalog = resolve(&repo_root).unwrap();
+    let records = catalog
+        .intrinsics
+        .iter()
+        .filter(|record| {
+            record.rust.abi_id.as_str() >= "i0504" && record.rust.abi_id.as_str() <= "i0519"
+        })
+        .collect::<Vec<_>>();
+    let expected = [
+        (
+            "mma_m16n8k16_fp8_f16_e4m3_e4m3",
+            "i0504",
+            RegisterMmaShape::M16n8k16,
+            RegisterMmaAccumulator::F16,
+            87,
+        ),
+        (
+            "mma_m16n8k16_fp8_f16_e4m3_e5m2",
+            "i0505",
+            RegisterMmaShape::M16n8k16,
+            RegisterMmaAccumulator::F16,
+            87,
+        ),
+        (
+            "mma_m16n8k16_fp8_f16_e5m2_e4m3",
+            "i0506",
+            RegisterMmaShape::M16n8k16,
+            RegisterMmaAccumulator::F16,
+            87,
+        ),
+        (
+            "mma_m16n8k16_fp8_f16_e5m2_e5m2",
+            "i0507",
+            RegisterMmaShape::M16n8k16,
+            RegisterMmaAccumulator::F16,
+            87,
+        ),
+        (
+            "mma_m16n8k16_fp8_f32_e4m3_e4m3",
+            "i0508",
+            RegisterMmaShape::M16n8k16,
+            RegisterMmaAccumulator::F32,
+            87,
+        ),
+        (
+            "mma_m16n8k16_fp8_f32_e4m3_e5m2",
+            "i0509",
+            RegisterMmaShape::M16n8k16,
+            RegisterMmaAccumulator::F32,
+            87,
+        ),
+        (
+            "mma_m16n8k16_fp8_f32_e5m2_e4m3",
+            "i0510",
+            RegisterMmaShape::M16n8k16,
+            RegisterMmaAccumulator::F32,
+            87,
+        ),
+        (
+            "mma_m16n8k16_fp8_f32_e5m2_e5m2",
+            "i0511",
+            RegisterMmaShape::M16n8k16,
+            RegisterMmaAccumulator::F32,
+            87,
+        ),
+        (
+            "mma_m16n8k32_fp8_f16_e4m3_e4m3",
+            "i0512",
+            RegisterMmaShape::M16n8k32,
+            RegisterMmaAccumulator::F16,
+            87,
+        ),
+        (
+            "mma_m16n8k32_fp8_f16_e4m3_e5m2",
+            "i0513",
+            RegisterMmaShape::M16n8k32,
+            RegisterMmaAccumulator::F16,
+            87,
+        ),
+        (
+            "mma_m16n8k32_fp8_f16_e5m2_e4m3",
+            "i0514",
+            RegisterMmaShape::M16n8k32,
+            RegisterMmaAccumulator::F16,
+            87,
+        ),
+        (
+            "mma_m16n8k32_fp8_f16_e5m2_e5m2",
+            "i0515",
+            RegisterMmaShape::M16n8k32,
+            RegisterMmaAccumulator::F16,
+            87,
+        ),
+        (
+            "mma_m16n8k32_fp8_f32_e4m3_e4m3",
+            "i0516",
+            RegisterMmaShape::M16n8k32,
+            RegisterMmaAccumulator::F32,
+            84,
+        ),
+        (
+            "mma_m16n8k32_fp8_f32_e4m3_e5m2",
+            "i0517",
+            RegisterMmaShape::M16n8k32,
+            RegisterMmaAccumulator::F32,
+            84,
+        ),
+        (
+            "mma_m16n8k32_fp8_f32_e5m2_e4m3",
+            "i0518",
+            RegisterMmaShape::M16n8k32,
+            RegisterMmaAccumulator::F32,
+            84,
+        ),
+        (
+            "mma_m16n8k32_fp8_f32_e5m2_e5m2",
+            "i0519",
+            RegisterMmaShape::M16n8k32,
+            RegisterMmaAccumulator::F32,
+            84,
+        ),
+    ];
+    assert_eq!(records.len(), expected.len());
+    let sm_89 = CatalogHardwareTarget::AnyOf {
+        alternatives: vec![CatalogHardwareAlternative::MinimumSm { sm: 89 }],
+    };
+    let expected_routes = [
+        (
+            IntrinsicBackend::LlvmNvptx,
+            BackendLoweringMechanism::InlinePtx,
+            "rust-llvm-22.1.2-1cb4e383",
+        ),
+        (
+            IntrinsicBackend::LibNvvm,
+            BackendLoweringMechanism::InlinePtx,
+            "cuda-13.3-libnvvm-13.3.33",
+        ),
+    ];
+    let mut floor_groups = BTreeMap::new();
+
+    for (record, &(id, abi_id, shape, accumulator, minimum_ptx)) in records.iter().zip(&expected) {
+        assert_eq!(record.id, id);
+        assert_eq!(record.rust.abi_id, abi_id);
+        let mma = record.register_mma.as_ref().unwrap();
+        assert_eq!((mma.shape, mma.accumulator), (shape, accumulator));
+        assert_eq!(record.target.minimum_ptx.encoded(), minimum_ptx);
+        assert_eq!(record.target.hardware, sm_89);
+        assert_eq!(
+            record
+                .backend_lowerings
+                .iter()
+                .map(|route| (
+                    route.backend,
+                    route.mechanism,
+                    route.evidence_profile.as_str()
+                ))
+                .collect::<Vec<_>>(),
+            expected_routes
+        );
+        for route in &record.backend_lowerings {
+            assert_eq!(route.target.minimum_ptx.encoded(), minimum_ptx);
+            assert_eq!(route.target.hardware, sm_89);
+        }
+        *floor_groups
+            .entry((shape, accumulator, minimum_ptx))
+            .or_insert(0) += 1;
+
+        if shape == RegisterMmaShape::M16n8k32 && accumulator == RegisterMmaAccumulator::F16 {
+            assert_eq!(
+                record
+                    .selections
+                    .iter()
+                    .flat_map(|selection| &selection.predicates)
+                    .filter(|predicate| predicate.contains("getPTXVersion"))
+                    .map(String::as_str)
+                    .collect::<Vec<_>>(),
+                ["Subtarget->getPTXVersion() >= 84"]
+            );
+            let llvm_route = &record.backend_lowerings[0];
+            assert!(llvm_route.stages.iter().any(|stage| {
+                stage.stage == EvidenceStageKind::PtxAssembly
+                    && stage.mechanism == Some(BackendLoweringMechanism::InlinePtx)
+                    && stage.outcome == "succeeded"
+                    && stage.targets == ["sm_89", "ptx87"]
+                    && stage.artifact_kind == Some(EvidenceArtifactKind::Cubin)
+            }));
+            assert!(llvm_route.stages.iter().any(|stage| {
+                stage.stage == EvidenceStageKind::PtxAssembly
+                    && stage.mechanism == Some(BackendLoweringMechanism::InlinePtx)
+                    && stage.outcome == "failed"
+                    && stage.targets == ["sm_89", "ptx86"]
+            }));
+        }
+    }
+    assert_eq!(
+        floor_groups,
+        BTreeMap::from([
+            (
+                (RegisterMmaShape::M16n8k16, RegisterMmaAccumulator::F16, 87),
+                4
+            ),
+            (
+                (RegisterMmaShape::M16n8k16, RegisterMmaAccumulator::F32, 87),
+                4
+            ),
+            (
+                (RegisterMmaShape::M16n8k32, RegisterMmaAccumulator::F16, 87),
+                4
+            ),
+            (
+                (RegisterMmaShape::M16n8k32, RegisterMmaAccumulator::F32, 84),
+                4
+            ),
+        ])
+    );
+}
+
+#[test]
+fn dense_f8f6f4_candidate_floor_uses_the_resolved_policy() {
+    for accumulator in [RegisterMmaAccumulator::F16, RegisterMmaAccumulator::F32] {
+        let policy = expand_register_mma_f8f6f4_admission(
+            &test_register_mma_f8f6f4_admission(accumulator),
+            accumulator,
+        )
+        .unwrap()
+        .remove(0);
+        let (_, requirement) = candidate_llvm_route(&policy).unwrap();
+
+        validate_candidate_target(&policy, &requirement, "sm_120a", "+ptx87").unwrap();
+        validate_candidate_target(&policy, &requirement, "sm_120f", "+ptx88").unwrap();
+        validate_candidate_target(&policy, &requirement, "sm_121a", "+ptx88").unwrap();
+        validate_candidate_target(&policy, &requirement, "sm_121f", "+ptx88").unwrap();
+        for target in ["sm_120f", "sm_121a", "sm_121f"] {
+            assert!(
+                validate_candidate_target(&policy, &requirement, target, "+ptx87").is_err(),
+                "{target} must require PTX 8.8"
+            );
+        }
+    }
+}
+
+#[test]
+fn pinned_register_mma_records_match_the_closed_recipes_and_fail_closed() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (mut overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    bind_pinned_abi_ids(&repo_root, &mut overlay);
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect();
+    let records: Vec<_> = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "register_mma")
+        .collect();
+    assert_eq!(records.len(), 154);
+
+    let dense_f8f6f4_records = records
+        .iter()
+        .copied()
+        .filter(|record| {
+            record.register_mma.as_ref().is_some_and(|mma| {
+                matches!(mma.kind, None | Some(RegisterMmaKind::F8f6f4))
+                    && register_mma_f8f6f4_element_name(mma.a_element).is_some()
+                    && register_mma_f8f6f4_element_name(mma.b_element).is_some()
+            })
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(dense_f8f6f4_records.len(), 50);
+    for (accumulator, first_abi, last_abi, adapter) in [
+        (
+            RegisterMmaAccumulator::F32,
+            "i0454",
+            "i0478",
+            RegisterMmaAdapter::C4F32A4U32B2U32ToD4F32,
+        ),
+        (
+            RegisterMmaAccumulator::F16,
+            "i0479",
+            "i0503",
+            RegisterMmaAdapter::C2U32A4U32B2U32ToD2U32,
+        ),
+    ] {
+        let family = dense_f8f6f4_records
+            .iter()
+            .copied()
+            .filter(|record| record.register_mma.as_ref().unwrap().accumulator == accumulator)
+            .collect::<Vec<_>>();
+        assert_eq!(family.len(), 25);
+        assert_eq!(family[0].abi_id, first_abi);
+        assert_eq!(family[24].abi_id, last_abi);
+        assert!(
+            family
+                .iter()
+                .all(|record| record.register_mma.as_ref().unwrap().adapter == adapter)
+        );
+    }
+    assert!(dense_f8f6f4_records.iter().all(|record| {
+        record.minimum_ptx == "8.7"
+            && record.minimum_sm.is_none()
+            && record.targets == REGISTER_MMA_F8F6F4_TARGETS
+    }));
+
+    let mxf8f6f4_records = records
+        .iter()
+        .copied()
+        .filter(|record| {
+            record
+                .register_mma
+                .as_ref()
+                .is_some_and(|mma| mma.kind == Some(RegisterMmaKind::Mxf8f6f4))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(mxf8f6f4_records.len(), 25);
+    assert_eq!(mxf8f6f4_records[0].abi_id, "i0858");
+    assert_eq!(mxf8f6f4_records[24].abi_id, "i0882");
+    assert!(mxf8f6f4_records.iter().all(|record| {
+        let mma = record.register_mma.as_ref().unwrap();
+        mma.shape == RegisterMmaShape::M16n8k32
+            && mma.accumulator == RegisterMmaAccumulator::F32
+            && mma.adapter == RegisterMmaAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
+            && record.rust_arguments
+                == [
+                    "[f32; 4]", "[u32; 4]", "[u32; 2]", "u32", "u16", "u16", "u32", "u16", "u16",
+                ]
+            && record.rust_result == "[f32; 4]"
+            && record.minimum_ptx == "8.7"
+            && record.minimum_sm.is_none()
+            && record.targets == REGISTER_MMA_F8F6F4_TARGETS
+            && record
+                .expected_ptx
+                .modifiers
+                .iter()
+                .any(|modifier| modifier == "kind::mxf8f6f4")
+    }));
+
+    let integer_records: Vec<_> = records
+        .iter()
+        .copied()
+        .filter(|record| {
+            record.register_mma.as_ref().is_some_and(|mma| {
+                mma.operation == RegisterMmaOperation::Multiply
+                    && mma.accumulator == RegisterMmaAccumulator::S32
+            })
+        })
+        .collect();
+    assert_eq!(integer_records.len(), 48);
+    let binary_records = records
+        .iter()
+        .copied()
+        .filter(|record| {
+            record
+                .register_mma
+                .as_ref()
+                .is_some_and(|mma| mma.operation != RegisterMmaOperation::Multiply)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(binary_records.len(), 6);
+    let int8_records = integer_records
+        .iter()
+        .copied()
+        .filter(|record| {
+            let mma = record.register_mma.as_ref().unwrap();
+            matches!(
+                mma.a_element,
+                RegisterMmaElement::S8 | RegisterMmaElement::U8
+            ) && matches!(
+                mma.b_element,
+                RegisterMmaElement::S8 | RegisterMmaElement::U8
+            )
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(int8_records.len(), 24);
+    let int4_records = integer_records
+        .iter()
+        .copied()
+        .filter(|record| {
+            let mma = record.register_mma.as_ref().unwrap();
+            matches!(
+                mma.a_element,
+                RegisterMmaElement::S4 | RegisterMmaElement::U4
+            ) && matches!(
+                mma.b_element,
+                RegisterMmaElement::S4 | RegisterMmaElement::U4
+            )
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(int4_records.len(), 24);
+    let actual_variants = integer_records
+        .iter()
+        .map(|record| {
+            let mma = record.register_mma.as_ref().unwrap();
+            (mma.shape, mma.a_element, mma.b_element, mma.overflow)
+        })
+        .collect::<BTreeSet<_>>();
+    let expected_int8_variants = [
+        RegisterMmaShape::M8n8k16,
+        RegisterMmaShape::M16n8k16,
+        RegisterMmaShape::M16n8k32,
+    ]
+    .into_iter()
+    .flat_map(|shape| {
+        [RegisterMmaElement::S8, RegisterMmaElement::U8]
+            .into_iter()
+            .flat_map(move |a_element| {
+                [RegisterMmaElement::S8, RegisterMmaElement::U8]
+                    .into_iter()
+                    .flat_map(move |b_element| {
+                        [
+                            RegisterMmaOverflow::Wrapping,
+                            RegisterMmaOverflow::Satfinite,
+                        ]
+                        .into_iter()
+                        .map(move |overflow| (shape, a_element, b_element, overflow))
+                    })
+            })
+    })
+    .collect::<BTreeSet<_>>();
+    let expected_int4_variants = [
+        RegisterMmaShape::M8n8k32,
+        RegisterMmaShape::M16n8k32,
+        RegisterMmaShape::M16n8k64,
+    ]
+    .into_iter()
+    .flat_map(|shape| {
+        [RegisterMmaElement::S4, RegisterMmaElement::U4]
+            .into_iter()
+            .flat_map(move |a_element| {
+                [RegisterMmaElement::S4, RegisterMmaElement::U4]
+                    .into_iter()
+                    .flat_map(move |b_element| {
+                        [
+                            RegisterMmaOverflow::Wrapping,
+                            RegisterMmaOverflow::Satfinite,
+                        ]
+                        .into_iter()
+                        .map(move |overflow| (shape, a_element, b_element, overflow))
+                    })
+            })
+    })
+    .collect::<BTreeSet<_>>();
+    let expected_variants = expected_int8_variants
+        .union(&expected_int4_variants)
+        .copied()
+        .collect::<BTreeSet<_>>();
+    assert_eq!(actual_variants, expected_variants);
+    assert_eq!(
+        integer_records
+            .iter()
+            .filter(|record| {
+                record.register_mma.as_ref().unwrap().compatibility_source
+                    == RegisterMmaCompatibilitySource::GeneratedStub
+            })
+            .count(),
+        47
+    );
+
+    let actual_binary_variants = binary_records
+        .iter()
+        .map(|record| {
+            let mma = record.register_mma.as_ref().unwrap();
+            (mma.shape, mma.operation)
+        })
+        .collect::<BTreeSet<_>>();
+    let expected_binary_variants = [
+        RegisterMmaShape::M8n8k128,
+        RegisterMmaShape::M16n8k128,
+        RegisterMmaShape::M16n8k256,
+    ]
+    .into_iter()
+    .flat_map(|shape| {
+        [RegisterMmaOperation::XorPopc, RegisterMmaOperation::AndPopc]
+            .into_iter()
+            .map(move |operation| (shape, operation))
+    })
+    .collect::<BTreeSet<_>>();
+    assert_eq!(actual_binary_variants, expected_binary_variants);
+    assert!(binary_records.iter().all(|record| {
+        let mma = record.register_mma.as_ref().unwrap();
+        mma.accumulator == RegisterMmaAccumulator::S32
+            && mma.a_element == RegisterMmaElement::B1
+            && mma.b_element == RegisterMmaElement::B1
+            && mma.overflow == RegisterMmaOverflow::Wrapping
+            && mma.compatibility_source == RegisterMmaCompatibilitySource::GeneratedStub
+            && record.expected_ptx.modifiers.ends_with(&[
+                match mma.operation {
+                    RegisterMmaOperation::XorPopc => "xor".into(),
+                    RegisterMmaOperation::AndPopc => "and".into(),
+                    RegisterMmaOperation::Multiply => unreachable!(),
+                },
+                "popc".into(),
+            ])
+    }));
+
+    for record in &binary_records {
+        let mma = record.register_mma.as_ref().unwrap();
+        let (arguments, result, adapter) = match mma.shape {
+            RegisterMmaShape::M8n8k128 => (
+                &["[i32; 2]", "u32", "u32"] as &[_],
+                "[i32; 2]",
+                RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32,
+            ),
+            RegisterMmaShape::M16n8k128 => (
+                &["[i32; 4]", "[u32; 2]", "u32"] as &[_],
+                "[i32; 4]",
+                RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32,
+            ),
+            RegisterMmaShape::M16n8k256 => (
+                &["[i32; 4]", "[u32; 4]", "[u32; 2]"] as &[_],
+                "[i32; 4]",
+                RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32,
+            ),
+            _ => unreachable!(),
+        };
+        assert_eq!(record.rust_arguments, arguments);
+        assert_eq!(record.rust_result, result);
+        assert_eq!(mma.adapter, adapter);
+        let expected_floor = match (mma.shape, mma.operation) {
+            (RegisterMmaShape::M8n8k128, RegisterMmaOperation::XorPopc) => ("7.0", "sm_75"),
+            (_, RegisterMmaOperation::XorPopc) => ("7.0", "sm_80"),
+            (_, RegisterMmaOperation::AndPopc) => ("7.1", "sm_80"),
+            _ => unreachable!(),
+        };
+        assert_eq!(record.minimum_ptx, expected_floor.0);
+        assert_eq!(record.minimum_sm.as_deref(), Some(expected_floor.1));
+    }
+
+    for record in integer_records.iter().filter(|record| {
+        matches!(
+            record.register_mma.as_ref().unwrap().shape,
+            RegisterMmaShape::M8n8k16 | RegisterMmaShape::M8n8k32
+        )
+    }) {
+        assert_eq!(record.rust_arguments, ["[i32; 2]", "u32", "u32"]);
+        assert_eq!(record.rust_result, "[i32; 2]");
+        assert_eq!(record.minimum_ptx, "6.5");
+        assert_eq!(record.minimum_sm.as_deref(), Some("sm_75"));
+        assert_eq!(
+            record.register_mma.as_ref().unwrap().adapter,
+            RegisterMmaAdapter::C2I32A1U32B1U32ToD2I32
+        );
+    }
+
+    for record in int4_records
+        .iter()
+        .filter(|record| record.register_mma.as_ref().unwrap().shape == RegisterMmaShape::M16n8k32)
+    {
+        assert_eq!(record.rust_arguments, ["[i32; 4]", "[u32; 2]", "u32"]);
+        assert_eq!(record.rust_result, "[i32; 4]");
+        assert_eq!(record.minimum_ptx, "7.0");
+        assert_eq!(record.minimum_sm.as_deref(), Some("sm_80"));
+        assert_eq!(
+            record.register_mma.as_ref().unwrap().adapter,
+            RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32
+        );
+    }
+
+    for record in int4_records
+        .iter()
+        .filter(|record| record.register_mma.as_ref().unwrap().shape == RegisterMmaShape::M16n8k64)
+    {
+        assert_eq!(record.rust_arguments, ["[i32; 4]", "[u32; 4]", "[u32; 2]"]);
+        assert_eq!(record.rust_result, "[i32; 4]");
+        assert_eq!(record.minimum_ptx, "7.0");
+        assert_eq!(record.minimum_sm.as_deref(), Some("sm_80"));
+        assert_eq!(
+            record.register_mma.as_ref().unwrap().adapter,
+            RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32
+        );
+    }
+
+    let actual_int4_abi_ids = int4_records
+        .iter()
+        .map(|record| record.abi_id.as_str())
+        .collect::<BTreeSet<_>>();
+    let expected_int4_abi_ids = (133..=156)
+        .map(|id| format!("i{id:04}"))
+        .collect::<BTreeSet<_>>();
+    assert_eq!(
+        actual_int4_abi_ids,
+        expected_int4_abi_ids
+            .iter()
+            .map(String::as_str)
+            .collect::<BTreeSet<_>>()
+    );
+
+    let int8_k32 = int8_records
+        .iter()
+        .find(|record| record.register_mma.as_ref().unwrap().shape == RegisterMmaShape::M16n8k32)
+        .unwrap();
+    let int4_k32 = int4_records
+        .iter()
+        .find(|record| record.register_mma.as_ref().unwrap().shape == RegisterMmaShape::M16n8k32)
+        .unwrap();
+    assert_eq!(
+        int8_k32.register_mma.as_ref().unwrap().adapter,
+        RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32
+    );
+    assert_eq!(
+        int4_k32.register_mma.as_ref().unwrap().adapter,
+        RegisterMmaAdapter::C4I32A2U32B1U32ToD4I32
+    );
+
+    for policy in &records {
+        let declaration = declarations[policy.source_record.as_deref().unwrap()];
+        assert_eq!(declaration.selections.len(), 1);
+        assert!(
+            selection_matches_policy(policy, &declaration.selections[0]).unwrap(),
+            "{}",
+            policy.id
+        );
+        validate_imported_policy(policy, declaration).unwrap();
+    }
+
+    let valid = records[0];
+    let declaration = declarations[valid.source_record.as_deref().unwrap()];
+
+    let mut non_convergent = valid.clone();
+    non_convergent.convergent = false;
+    assert!(
+        validate_imported_policy(&non_convergent, declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("effects")
+    );
+
+    let mut typed_route = valid.clone();
+    typed_route.backend_lowerings[0].mechanism = BackendLoweringMechanism::TypedNvvm;
+    assert!(validate_imported_policy(&typed_route, declaration).is_err());
+
+    let mut selectionless = declaration.clone();
+    selectionless.selections.clear();
+    assert!(validate_imported_policy(valid, &selectionless).is_err());
+
+    let mut crossed_variant = valid.clone();
+    crossed_variant.register_mma.as_mut().unwrap().a_element = RegisterMmaElement::F16;
+    assert!(validate_imported_policy(&crossed_variant, declaration).is_err());
+
+    let generated = int8_records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_m16n8k16_s32_s8_u8_satfinite")
+        .unwrap();
+    let generated_declaration = declarations[generated.source_record.as_deref().unwrap()];
+
+    let mut wrong_stub_owner = generated.clone();
+    wrong_stub_owner
+        .register_mma
+        .as_mut()
+        .unwrap()
+        .compatibility_source = RegisterMmaCompatibilitySource::ExistingStub;
+    assert!(validate_imported_policy(&wrong_stub_owner, generated_declaration).is_err());
+
+    let mut wrong_b_element = generated.clone();
+    wrong_b_element.register_mma.as_mut().unwrap().b_element = RegisterMmaElement::S8;
+    assert!(validate_imported_policy(&wrong_b_element, generated_declaration).is_err());
+
+    let mut wrong_overflow = generated.clone();
+    wrong_overflow.register_mma.as_mut().unwrap().overflow = RegisterMmaOverflow::Wrapping;
+    assert!(validate_imported_policy(&wrong_overflow, generated_declaration).is_err());
+
+    let mut wrong_shape = generated.clone();
+    wrong_shape.register_mma.as_mut().unwrap().shape = RegisterMmaShape::M16n8k32;
+    assert!(validate_imported_policy(&wrong_shape, generated_declaration).is_err());
+
+    let mut wrong_adapter = generated.clone();
+    wrong_adapter.register_mma.as_mut().unwrap().adapter =
+        RegisterMmaAdapter::C4I32A4U32B2U32ToD4I32;
+    assert!(validate_imported_policy(&wrong_adapter, generated_declaration).is_err());
+
+    let binary = binary_records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_m8n8k128_s32_b1_xor_popc")
+        .unwrap();
+    let binary_declaration = declarations[binary.source_record.as_deref().unwrap()];
+
+    let mut wrong_binary_operation = binary.clone();
+    wrong_binary_operation
+        .register_mma
+        .as_mut()
+        .unwrap()
+        .operation = RegisterMmaOperation::AndPopc;
+    assert!(validate_imported_policy(&wrong_binary_operation, binary_declaration).is_err());
+
+    let mut wrong_binary_floor = binary.clone();
+    wrong_binary_floor.minimum_sm = Some("sm_80".into());
+    assert!(validate_imported_policy(&wrong_binary_floor, binary_declaration).is_err());
+
+    let mut wrong_binary_element = binary.clone();
+    wrong_binary_element
+        .register_mma
+        .as_mut()
+        .unwrap()
+        .a_element = RegisterMmaElement::U4;
+    assert!(validate_imported_policy(&wrong_binary_element, binary_declaration).is_err());
+}
+
+#[test]
+fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (mut overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    bind_pinned_abi_ids(&repo_root, &mut overlay);
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect();
+    let records = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "sparse_mma")
+        .collect::<Vec<_>>();
+    assert_eq!(records.len(), 114);
+    assert_eq!(
+        records
+            .iter()
+            .map(|record| record.abi_id.clone())
+            .collect::<BTreeSet<_>>(),
+        (163..=251)
+            .chain(525..=549)
+            .map(|id| format!("i{id:04}"))
+            .collect::<BTreeSet<_>>()
+    );
+
+    let mut derived_ids = BTreeSet::new();
+    let mut derived_operation_keys = BTreeSet::new();
+    let mut derived_source_records = BTreeSet::new();
+    let mut derived_llvm_symbols = BTreeSet::new();
+    for record in &records {
+        let identity = &sparse_mma_recipe(record.sparse_mma.as_ref().unwrap())
+            .unwrap()
+            .identity;
+        assert_eq!(record.id, identity.id);
+        assert_eq!(record.operation_key, identity.operation_key);
+        assert_eq!(
+            record.source_record.as_deref(),
+            Some(identity.source_record.as_str())
+        );
+        assert_eq!(
+            record.llvm_symbol.as_deref(),
+            Some(identity.llvm_symbol.as_str())
+        );
+        assert_eq!(record.expected_ptx.modifiers, identity.ptx_modifiers);
+        assert!(derived_ids.insert(identity.id.clone()));
+        assert!(derived_operation_keys.insert(identity.operation_key.clone()));
+        assert!(derived_source_records.insert(identity.source_record.clone()));
+        assert!(derived_llvm_symbols.insert(identity.llvm_symbol.clone()));
+    }
+    assert_eq!(derived_ids.len(), 114);
+    assert_eq!(derived_operation_keys.len(), 114);
+    assert_eq!(derived_source_records.len(), 114);
+    assert_eq!(derived_llvm_symbols.len(), 114);
+
+    let integer_records = records
+        .iter()
+        .copied()
+        .filter(|record| {
+            record.sparse_mma.as_ref().unwrap().accumulator == SparseMmaAccumulator::S32
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(integer_records.len(), 64);
+    let f32_records = records
+        .iter()
+        .copied()
+        .filter(|record| {
+            record.sparse_mma.as_ref().unwrap().accumulator == SparseMmaAccumulator::F32
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(f32_records.len(), 25);
+    let f16_records = records
+        .iter()
+        .copied()
+        .filter(|record| {
+            record.sparse_mma.as_ref().unwrap().accumulator == SparseMmaAccumulator::F16
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(f16_records.len(), 25);
+
+    let variants = integer_records
+        .iter()
+        .map(|record| {
+            let mma = record.sparse_mma.as_ref().unwrap();
+            let carrier =
+                sparse_mma_carrier_recipe(mma.shape, mma.a_element, mma.b_element).unwrap();
+            assert_eq!(mma.accumulator, SparseMmaAccumulator::S32);
+            assert_eq!(mma.selector, carrier.selector);
+            assert_eq!(mma.adapter, carrier.adapter);
+            assert_eq!(mma.llvm_adapter, carrier.llvm_adapter);
+            assert_eq!(record.rust_arguments, carrier.rust_arguments());
+            assert_eq!(record.dialect_operands, carrier.dialect_operands());
+            assert_eq!(record.llvm_arguments, carrier.llvm_arguments());
+            assert_eq!(
+                record.expected_ptx.operands,
+                carrier.expected_ptx_operands()
+            );
+            assert_eq!(record.minimum_ptx, sparse_mma_minimum_ptx(mma));
+            assert_eq!(record.minimum_sm.as_deref(), Some("sm_80"));
+            assert_eq!(
+                record.expected_ptx.operands.last(),
+                Some(&OperandPattern::Immediate)
+            );
+            assert_eq!(
+                record.expected_ptx.modifiers.first().map(String::as_str),
+                Some(match mma.metadata {
+                    SparseMmaMetadata::Standard => "sp",
+                    SparseMmaMetadata::Ordered => "sp::ordered_metadata",
+                })
+            );
+            (
+                mma.shape,
+                mma.a_element,
+                mma.b_element,
+                mma.overflow,
+                mma.metadata,
+            )
+        })
+        .collect::<BTreeSet<_>>();
+    let mut expected_variants = BTreeSet::new();
+    for shape in [SparseMmaShape::M16n8k32, SparseMmaShape::M16n8k64] {
+        let metadata = match shape {
+            SparseMmaShape::M16n8k32 => [
+                Some(SparseMmaMetadata::Standard),
+                Some(SparseMmaMetadata::Ordered),
+            ],
+            SparseMmaShape::M16n8k64 => [
+                Some(SparseMmaMetadata::Standard),
+                Some(SparseMmaMetadata::Ordered),
+            ],
+            SparseMmaShape::M16n8k128 => [None, None],
+        };
+        for a_element in [SparseMmaElement::S8, SparseMmaElement::U8] {
+            for b_element in [SparseMmaElement::S8, SparseMmaElement::U8] {
+                for overflow in [SparseMmaOverflow::Wrapping, SparseMmaOverflow::Satfinite] {
+                    for metadata in metadata.into_iter().flatten() {
+                        expected_variants.insert((shape, a_element, b_element, overflow, metadata));
+                    }
+                }
+            }
+        }
+    }
+    for shape in [SparseMmaShape::M16n8k64, SparseMmaShape::M16n8k128] {
+        for a_element in [SparseMmaElement::S4, SparseMmaElement::U4] {
+            for b_element in [SparseMmaElement::S4, SparseMmaElement::U4] {
+                for overflow in [SparseMmaOverflow::Wrapping, SparseMmaOverflow::Satfinite] {
+                    for metadata in [SparseMmaMetadata::Standard, SparseMmaMetadata::Ordered] {
+                        expected_variants.insert((shape, a_element, b_element, overflow, metadata));
+                    }
+                }
+            }
+        }
+    }
+    assert_eq!(variants, expected_variants);
+
+    let f8f6f4_formats = [
+        SparseMmaElement::E2m1,
+        SparseMmaElement::E2m3,
+        SparseMmaElement::E3m2,
+        SparseMmaElement::E4m3,
+        SparseMmaElement::E5m2,
+    ];
+    assert_eq!(
+        f32_records
+            .iter()
+            .map(|record| {
+                let mma = record.sparse_mma.as_ref().unwrap();
+                (mma.a_element, mma.b_element)
+            })
+            .collect::<BTreeSet<_>>(),
+        f8f6f4_formats
+            .into_iter()
+            .flat_map(|a| f8f6f4_formats.into_iter().map(move |b| (a, b)))
+            .collect()
+    );
+    assert_eq!(
+        f32_records
+            .iter()
+            .map(|record| record.abi_id.as_str())
+            .collect::<BTreeSet<_>>(),
+        (227..=251)
+            .map(|id| format!("i{id:04}"))
+            .collect::<BTreeSet<_>>()
+            .iter()
+            .map(String::as_str)
+            .collect()
+    );
+    assert_eq!(
+        f16_records
+            .iter()
+            .map(|record| {
+                let mma = record.sparse_mma.as_ref().unwrap();
+                (mma.a_element, mma.b_element)
+            })
+            .collect::<BTreeSet<_>>(),
+        f8f6f4_formats
+            .into_iter()
+            .flat_map(|a| f8f6f4_formats.into_iter().map(move |b| (a, b)))
+            .collect()
+    );
+    assert_eq!(
+        f16_records
+            .iter()
+            .map(|record| record.abi_id.as_str())
+            .collect::<BTreeSet<_>>(),
+        (525..=549)
+            .map(|id| format!("i{id:04}"))
+            .collect::<BTreeSet<_>>()
+            .iter()
+            .map(String::as_str)
+            .collect()
+    );
+    for record in &f32_records {
+        let mma = record.sparse_mma.as_ref().unwrap();
+        assert_eq!(mma.shape, SparseMmaShape::M16n8k64);
+        assert_eq!(mma.accumulator, SparseMmaAccumulator::F32);
+        assert_eq!(mma.overflow, SparseMmaOverflow::NotApplicable);
+        assert_eq!(mma.metadata, SparseMmaMetadata::Ordered);
+        assert_eq!(mma.selector, SparseMmaSelector::ImmediateZero);
+        assert_eq!(
+            mma.adapter,
+            SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32
+        );
+        assert_eq!(
+            mma.llvm_adapter,
+            SparseMmaLlvmAdapter::A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32
+        );
+        assert_eq!(
+            record.rust_arguments,
+            ["[f32; 4]", "[u32; 4]", "[u32; 4]", "u32", "u32"]
+        );
+        assert_eq!(record.rust_result, "[f32; 4]");
+        assert_eq!(
+            record.dialect_operands,
+            [
+                "f32", "f32", "f32", "f32", "u32", "u32", "u32", "u32", "u32", "u32", "u32", "u32",
+                "u32", "u32"
+            ]
+        );
+        assert_eq!(record.dialect_results, ["f32", "f32", "f32", "f32"]);
+        assert_eq!(
+            record.llvm_arguments,
+            [
+                "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32",
+                "i32", "i32"
+            ]
+        );
+        assert_eq!(record.llvm_results, ["f32", "f32", "f32", "f32"]);
+        assert_eq!(record.minimum_ptx, "8.7");
+        assert_eq!(record.minimum_sm, None);
+        // Same contract as the F16 accumulator: both float forms are gated
+        // on `hasMMABlockScale()`, so neither is narrower than the other.
+        assert_eq!(record.targets, SPARSE_MMA_F8F6F4_TARGETS);
+        assert_eq!(record.backend_lowerings.len(), 2);
+        assert!(record.backend_lowerings.iter().all(|lowering| {
+            lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                && lowering.minimum_ptx.as_deref() == Some("8.7")
+                && lowering.minimum_sm.is_none()
+        }));
+        assert_eq!(
+            record.expected_ptx.operands,
+            [
+                OperandPattern::RegisterList { length: 4 },
+                OperandPattern::RegisterList { length: 4 },
+                OperandPattern::RegisterList { length: 4 },
+                OperandPattern::RegisterList { length: 4 },
+                OperandPattern::Register,
+                OperandPattern::Immediate,
+            ]
+        );
+    }
+
+    for record in &f16_records {
+        let mma = record.sparse_mma.as_ref().unwrap();
+        assert_eq!(mma.shape, SparseMmaShape::M16n8k64);
+        assert_eq!(mma.accumulator, SparseMmaAccumulator::F16);
+        assert_eq!(mma.overflow, SparseMmaOverflow::NotApplicable);
+        assert_eq!(mma.metadata, SparseMmaMetadata::Ordered);
+        assert_eq!(mma.selector, SparseMmaSelector::ImmediateZero);
+        assert_eq!(
+            mma.adapter,
+            SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32
+        );
+        assert_eq!(
+            mma.llvm_adapter,
+            SparseMmaLlvmAdapter::A4I32B4I32C2V2F16MetadataI32SelectorI32ToD2V2F16
+        );
+        assert_eq!(
+            record.rust_arguments,
+            ["[u32; 2]", "[u32; 4]", "[u32; 4]", "u32", "u32"]
+        );
+        assert_eq!(record.rust_result, "[u32; 2]");
+        assert_eq!(
+            record.dialect_operands,
+            [
+                "i32", "i32", "u32", "u32", "u32", "u32", "u32", "u32", "u32", "u32", "u32", "u32"
+            ]
+        );
+        assert_eq!(record.dialect_results, ["i32", "i32"]);
+        assert_eq!(
+            record.llvm_arguments,
+            [
+                "i32", "i32", "i32", "i32", "i32", "i32", "i32", "i32", "v2f16", "v2f16", "i32",
+                "i32"
+            ]
+        );
+        assert_eq!(record.llvm_results, ["v2f16", "v2f16"]);
+        assert_eq!(record.minimum_ptx, "8.7");
+        assert_eq!(record.minimum_sm, None);
+        assert_eq!(record.targets, SPARSE_MMA_F8F6F4_TARGETS);
+        assert!(record.convergent && !record.pure);
+        assert!(record.backend_lowerings.iter().all(|lowering| {
+            lowering.mechanism == BackendLoweringMechanism::InlinePtx
+                && lowering.minimum_ptx.as_deref() == Some("8.7")
+                && lowering.minimum_sm.is_none()
+        }));
+        assert_eq!(
+            record.expected_ptx.operands,
+            [
+                OperandPattern::RegisterList { length: 2 },
+                OperandPattern::RegisterList { length: 4 },
+                OperandPattern::RegisterList { length: 4 },
+                OperandPattern::RegisterList { length: 2 },
+                OperandPattern::Register,
+                OperandPattern::Immediate,
+            ]
+        );
+    }
+
+    for policy in &records {
+        let declaration = declarations[policy.source_record.as_deref().unwrap()];
+        assert_eq!(declaration.selections.len(), 1);
+        assert!(
+            selection_matches_policy(policy, &declaration.selections[0]).unwrap(),
+            "{}",
+            policy.id
+        );
+        validate_imported_policy(policy, declaration).unwrap();
+    }
+
+    let mut selectionless = declarations[records[0].source_record.as_deref().unwrap()].clone();
+    selectionless.selections.clear();
+    assert!(validate_imported_policy(records[0], &selectionless).is_err());
+
+    for (id, range_prefix, wrong_range) in [
+        ("mma_sp_m16n8k32_s32_s8", "Range<arg9", "Range<arg9,0,3>"),
+        ("mma_sp_m16n8k64_s32_s8", "Range<arg13", "Range<arg13,0,2>"),
+        (
+            "mma_sp_ordered_metadata_m16n8k64_s32_s4",
+            "Range<arg9",
+            "Range<arg9,0,1>",
+        ),
+        ("mma_sp_m16n8k64_s32_s4", "Range<arg9", "Range<arg9,0,1>"),
+        (
+            "mma_sp_ordered_metadata_m16n8k128_s32_s4",
+            "Range<arg13",
+            "Range<arg13,0,2>",
+        ),
+        ("mma_sp_m16n8k128_s32_s4", "Range<arg13", "Range<arg13,0,2>"),
+        (
+            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32",
+            "Range<arg13",
+            "Range<arg13,0,2>",
+        ),
+        (
+            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16",
+            "Range<arg11",
+            "Range<arg11,0,2>",
+        ),
+    ] {
+        let valid = records
+            .iter()
+            .copied()
+            .find(|record| record.id == id)
+            .unwrap();
+        let declaration = declarations[valid.source_record.as_deref().unwrap()];
+
+        let mut runtime_selector = valid.clone();
+        *runtime_selector.expected_ptx.operands.last_mut().unwrap() = OperandPattern::Register;
+        assert!(
+            validate_imported_policy(&runtime_selector, declaration)
+                .unwrap_err()
+                .to_string()
+                .contains("exact selection")
+        );
+
+        let mut wrong_declaration = declaration.clone();
+        *wrong_declaration
+            .properties
+            .iter_mut()
+            .find(|property| property.starts_with(range_prefix))
+            .unwrap() = wrong_range.into();
+        assert!(
+            validate_imported_policy(valid, &wrong_declaration)
+                .unwrap_err()
+                .to_string()
+                .contains("immediate range")
+        );
+    }
+
+    let k64 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_m16n8k64_s32_s8")
+        .unwrap();
+    let k64_declaration = declarations[k64.source_record.as_deref().unwrap()];
+    assert_eq!(k64.minimum_ptx, "7.1");
+    let ordered_k64 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k64_s32_s8")
+        .unwrap();
+    assert_eq!(ordered_k64.minimum_ptx, "8.5");
+
+    let f8f6f4 = f32_records[0];
+    let f8f6f4_declaration = declarations[f8f6f4.source_record.as_deref().unwrap()];
+    let mut widened_family = f8f6f4.clone();
+    widened_family.targets = "sm_120f".into();
+    assert!(validate_imported_policy(&widened_family, f8f6f4_declaration).is_err());
+    let mut widened_architecture = f8f6f4.clone();
+    widened_architecture.targets = "sm_121a".into();
+    assert!(validate_imported_policy(&widened_architecture, f8f6f4_declaration).is_err());
+
+    let f8f6f4_f16 = f16_records[0];
+    for block_scale in [f8f6f4, f8f6f4_f16] {
+        let mut missing_predicate =
+            declarations[block_scale.source_record.as_deref().unwrap()].clone();
+        missing_predicate.selections[0].predicates.clear();
+        assert!(
+            validate_imported_policy(block_scale, &missing_predicate)
+                .unwrap_err()
+                .to_string()
+                .contains("exact selection")
+        );
+    }
+
+    let ordered_k64_int4 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k64_s32_s4")
+        .unwrap();
+    let ordered_k64_int4_declaration =
+        declarations[ordered_k64_int4.source_record.as_deref().unwrap()];
+    assert_eq!(ordered_k64_int4.minimum_ptx, "8.5");
+    assert_eq!(ordered_k64_int4.rust_arguments[1], "[u32; 2]");
+    assert_eq!(ordered_k64_int4.rust_arguments[2], "[u32; 2]");
+    assert_eq!(ordered_k64_int4.llvm_arguments.len(), 10);
+    assert_eq!(
+        ordered_k64_int4.sparse_mma.as_ref().unwrap().selector,
+        SparseMmaSelector::ImmediateZeroOrOne
+    );
+    assert_eq!(
+        ordered_k64_int4.sparse_mma.as_ref().unwrap().adapter,
+        SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32
+    );
+    assert_eq!(
+        ordered_k64_int4.sparse_mma.as_ref().unwrap().llvm_adapter,
+        SparseMmaLlvmAdapter::A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32
+    );
+    let standard_k64_int4 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_m16n8k64_s32_s4")
+        .unwrap();
+    assert_eq!(standard_k64_int4.minimum_ptx, "7.1");
+    assert_eq!(
+        standard_k64_int4.rust_arguments,
+        ordered_k64_int4.rust_arguments
+    );
+    assert_eq!(
+        standard_k64_int4.llvm_arguments,
+        ordered_k64_int4.llvm_arguments
+    );
+
+    let ordered_k128_int4 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k128_s32_s4")
+        .unwrap();
+    let ordered_k128_int4_declaration =
+        declarations[ordered_k128_int4.source_record.as_deref().unwrap()];
+    assert_eq!(ordered_k128_int4.minimum_ptx, "8.5");
+    assert_eq!(ordered_k128_int4.rust_arguments[1], "[u32; 4]");
+    assert_eq!(ordered_k128_int4.rust_arguments[2], "[u32; 4]");
+    assert_eq!(ordered_k128_int4.llvm_arguments.len(), 14);
+    assert_eq!(
+        ordered_k128_int4.sparse_mma.as_ref().unwrap().selector,
+        SparseMmaSelector::ImmediateZero
+    );
+    assert_eq!(
+        ordered_k128_int4.sparse_mma.as_ref().unwrap().adapter,
+        SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32
+    );
+    assert_eq!(
+        ordered_k128_int4.sparse_mma.as_ref().unwrap().llvm_adapter,
+        SparseMmaLlvmAdapter::A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32
+    );
+    let standard_k128_int4 = records
+        .iter()
+        .copied()
+        .find(|record| record.id == "mma_sp_m16n8k128_s32_s4")
+        .unwrap();
+    assert_eq!(standard_k128_int4.minimum_ptx, "7.1");
+    assert_eq!(
+        standard_k128_int4.rust_arguments,
+        ordered_k128_int4.rust_arguments
+    );
+    assert_eq!(
+        standard_k128_int4.llvm_arguments,
+        ordered_k128_int4.llvm_arguments
+    );
+
+    let mut wrong_k128_selector = ordered_k128_int4.clone();
+    wrong_k128_selector.sparse_mma.as_mut().unwrap().selector =
+        SparseMmaSelector::ImmediateZeroOrOne;
+    assert!(validate_imported_policy(&wrong_k128_selector, ordered_k128_int4_declaration).is_err());
+
+    let mut mixed_k128_width = ordered_k128_int4.clone();
+    mixed_k128_width.sparse_mma.as_mut().unwrap().b_element = SparseMmaElement::U8;
+    assert!(
+        validate_imported_policy(&mixed_k128_width, ordered_k128_int4_declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("unsupported sparse-MMA variant")
+    );
+
+    let mut mixed_width = ordered_k64_int4.clone();
+    mixed_width.sparse_mma.as_mut().unwrap().b_element = SparseMmaElement::U8;
+    assert!(
+        validate_imported_policy(&mixed_width, ordered_k64_int4_declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("unsupported sparse-MMA variant")
+    );
+
+    let mut wrong_k64_selector = k64.clone();
+    wrong_k64_selector.sparse_mma.as_mut().unwrap().selector =
+        SparseMmaSelector::ImmediateZeroOrOne;
+    assert!(validate_imported_policy(&wrong_k64_selector, k64_declaration).is_err());
+
+    let mut wrong_k64_adapter = k64.clone();
+    wrong_k64_adapter.sparse_mma.as_mut().unwrap().adapter =
+        SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32;
+    assert!(validate_imported_policy(&wrong_k64_adapter, k64_declaration).is_err());
+
+    let mut wrong_k64_llvm_adapter = k64.clone();
+    wrong_k64_llvm_adapter
+        .sparse_mma
+        .as_mut()
+        .unwrap()
+        .llvm_adapter = SparseMmaLlvmAdapter::A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32;
+    assert!(validate_imported_policy(&wrong_k64_llvm_adapter, k64_declaration).is_err());
+
+    let mut wrong_k64_shape = k64.clone();
+    wrong_k64_shape.sparse_mma.as_mut().unwrap().shape = SparseMmaShape::M16n8k32;
+    assert!(validate_imported_policy(&wrong_k64_shape, k64_declaration).is_err());
+
+    let mut wrong_k64_carriers = k64.clone();
+    wrong_k64_carriers.dialect_operands.pop();
+    assert!(validate_imported_policy(&wrong_k64_carriers, k64_declaration).is_err());
+
+    let mut wrong_k64_lowering = k64.clone();
+    wrong_k64_lowering.lowering = "generated_register_mma".into();
+    assert!(validate_imported_policy(&wrong_k64_lowering, k64_declaration).is_err());
+
+    let mut mismatched_metadata_identity = k64.clone();
+    mismatched_metadata_identity
+        .sparse_mma
+        .as_mut()
+        .unwrap()
+        .metadata = SparseMmaMetadata::Ordered;
+    assert!(validate_imported_policy(&mismatched_metadata_identity, k64_declaration).is_err());
+}
+
+#[test]
+fn movmatrix_recipe_is_exact_and_fails_closed() {
+    let valid = movmatrix_policy();
+    validate_ptx_native_policy(&valid).unwrap();
+
+    let reject = |policy: &OverlayIntrinsic, expected: &str| {
+        let message = validate_ptx_native_policy(policy).unwrap_err().to_string();
+        assert!(message.contains(expected), "unexpected error: {message}");
+    };
+
+    let mut wrong_shape = valid.clone();
+    wrong_shape.expected_ptx.modifiers[2] = "m16n8".into();
+    reject(&wrong_shape, "closed movmatrix recipe");
+
+    let mut wrong_participation = valid.clone();
+    wrong_participation.convergent = false;
+    reject(&wrong_participation, "closed movmatrix recipe");
+
+    // A warp collective is not a function of its own operand, so the
+    // pure/no-memory pair every other collective avoids must stay rejected
+    // here too.
+    let mut wrong_purity = valid.clone();
+    wrong_purity.pure = true;
+    reject(&wrong_purity, "closed movmatrix recipe");
+
+    let mut wrong_memory = valid.clone();
+    wrong_memory.memory = "none".into();
+    reject(&wrong_memory, "closed movmatrix recipe");
+
+    let mut wrong_floor = valid.clone();
+    wrong_floor.backend_lowerings[0].minimum_ptx = Some("8.0".into());
+    reject(&wrong_floor, "exact movmatrix floor");
+
+    let mut mixed = valid;
+    mixed.warp_barrier = Some(crate::model::WarpBarrier {
+        participation:
+            WarpBarrierParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
+        legacy_pre_sm70: PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive,
+        adapter: WarpBarrierAdapter::DirectMemberMask,
+        mask_encoding: WarpBarrierMaskEncoding::RegisterOrImmediate,
+        memory_ordering: WarpBarrierMemoryOrdering::ParticipatingLanes,
+    });
+    reject(&mixed, "mixes another generated-family contract");
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/mod.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/mod.rs
new file mode 100644
index 0000000000..d98fc552a5
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/mod.rs
@@ -0,0 +1,16 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+mod evidence;
+mod fixtures;
+mod misc_families;
+mod mma;
+mod overlay_schema;
+mod scalar_packed;
+mod sreg_threadfence;
+mod targets_abi;
+mod tcgen05;
+mod tma_clc_cluster;
+mod warp;
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs
new file mode 100644
index 0000000000..946333f7cf
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs
@@ -0,0 +1,736 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    CatalogFile, OverlayShardFile, PackedAluFormat, PackedAluOperation, RegisterMmaAccumulator,
+    RegisterMmaKind,
+};
+use crate::util::read_json;
+use std::collections::{BTreeMap, BTreeSet};
+use std::path::Path;
+
+use super::fixtures::*;
+use crate::resolve::abi_ledger::*;
+use crate::resolve::driver::*;
+use crate::resolve::guards::*;
+use crate::resolve::overlay::*;
+
+#[test]
+fn duplicate_values_are_rejected() {
+    let mut values = BTreeSet::new();
+    insert_unique(&mut values, "thread_idx_x", "catalog ID").unwrap();
+    let error = insert_unique(&mut values, "thread_idx_x", "catalog ID").unwrap_err();
+    assert!(error.to_string().contains("duplicate catalog ID"));
+}
+
+#[test]
+fn overloaded_symbols_require_distinct_resolved_identities() {
+    let bf16 = packed_alu_policy(PackedAluFormat::Bf16x2, PackedAluOperation::Abs);
+    let f16 = packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Abs);
+    validate_unique_overlay(&[bf16.clone(), f16.clone()], 1).unwrap();
+
+    let mut unresolved = f16.clone();
+    unresolved.resolved_llvm_symbol = None;
+    let error = validate_unique_overlay(&[bf16.clone(), unresolved], 1).unwrap_err();
+    assert!(error.to_string().contains("without a resolved symbol"));
+
+    let mut duplicate = f16;
+    duplicate.resolved_llvm_symbol = bf16.resolved_llvm_symbol.clone();
+    let error = validate_unique_overlay(&[bf16, duplicate], 1).unwrap_err();
+    assert!(error.to_string().contains("duplicate resolved LLVM symbol"));
+}
+
+#[test]
+fn overlay_manifest_loads_sorted_family_shards() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (overlay, hash) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    assert_eq!(overlay.schema, OVERLAY_SCHEMA);
+    assert_eq!(overlay.shards.len(), 64);
+    assert_eq!(overlay.intrinsics.len(), 1016);
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "scalar_arithmetic")
+            .count(),
+        64
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "scalar_conversion")
+            .count(),
+        10
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "prmt")
+            .count(),
+        7
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "debug_control")
+            .count(),
+        3
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "stmatrix")
+            .count(),
+        4
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "packed_alu")
+            .count(),
+        30
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "packed_conversion")
+            .count(),
+        18
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "active_mask")
+            .count(),
+        1
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "dotprod")
+            .count(),
+        4
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "ldmatrix")
+            .count(),
+        18
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "register_mma")
+            .count(),
+        154
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "sparse_mma")
+            .count(),
+        114
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "cp_async_copy")
+            .count(),
+        8
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "cp_async_control")
+            .count(),
+        3
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "cp_async_mbarrier")
+            .count(),
+        4
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "mbarrier_basic")
+            .count(),
+        4
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "cluster_memory")
+            .count(),
+        2
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "clc")
+            .count(),
+        6
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "sync")
+            .count(),
+        4
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "vote")
+            .count(),
+        4
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "warp_barrier")
+            .count(),
+        1
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "warp_match")
+            .count(),
+        4
+    );
+    assert_eq!(
+        overlay
+            .intrinsics
+            .iter()
+            .filter(|record| record.family == "warp_shuffle")
+            .count(),
+        12
+    );
+    assert_eq!(hash.len(), 64);
+
+    for invalid in [
+        "../outside.toml",
+        "/absolute.toml",
+        "other/family.toml",
+        "overlay/../outside.toml",
+        "overlay/not-toml.json",
+    ] {
+        assert!(validate_overlay_shard_path(invalid).is_err(), "{invalid}");
+    }
+}
+
+#[test]
+fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() {
+    let shard = |schema, sparse_mma_f8f6f4_f32, prmt| OverlayShardFile {
+        schema,
+        family: "sparse_mma".into(),
+        intrinsics: vec![],
+        register_mma_int4: None,
+        register_mma_int8: None,
+        register_mma_b1: None,
+        register_mma_f8f6f4_f32: None,
+        register_mma_f8f6f4_f16: None,
+        register_mma_mxf8f6f4_f32: None,
+        register_mma_fp8: None,
+        register_mma_ampere_float: None,
+        sparse_mma_integer: None,
+        sparse_mma_f8f6f4_f32,
+        sparse_mma_f8f6f4_f16: None,
+        prmt,
+        packed_conversion_fp8: None,
+        packed_conversion_fp8_f16x2: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cluster_sreg: None,
+        cluster_barrier: None,
+        mbarrier_extended: None,
+        special_registers: None,
+        debug_control: None,
+        threadfence: None,
+        cluster_memory: None,
+        stmatrix: None,
+        clc: None,
+        wgmma_controls: None,
+        tma: None,
+        tcgen05: None,
+    };
+    let path = Path::new("intrinsics/overlay/test.toml");
+    validate_overlay_shard_schema(&shard(26, None, None), path).unwrap();
+    validate_overlay_shard_schema(&shard(27, None, None), path).unwrap();
+    validate_overlay_shard_schema(&shard(28, None, None), path).unwrap();
+    validate_overlay_shard_schema(&shard(29, None, None), path).unwrap();
+    validate_overlay_shard_schema(&shard(30, None, None), path).unwrap();
+    validate_overlay_shard_schema(&shard(31, None, None), path).unwrap();
+    validate_overlay_shard_schema(&shard(32, None, None), path).unwrap();
+    validate_overlay_shard_schema(&shard(33, None, None), path).unwrap();
+    validate_overlay_shard_schema(&shard(34, None, None), path).unwrap();
+    validate_overlay_shard_schema(&shard(35, None, None), path).unwrap();
+    validate_overlay_shard_schema(&shard(27, Some(test_f8f6f4_admission()), None), path).unwrap();
+    validate_overlay_shard_schema_with_max(
+        &shard(27, Some(test_f8f6f4_admission()), None),
+        path,
+        30,
+    )
+    .unwrap();
+    validate_overlay_shard_schema(&shard(28, None, Some(test_prmt_admission())), path).unwrap();
+    validate_overlay_shard_schema_with_max(&shard(28, None, Some(test_prmt_admission())), path, 30)
+        .unwrap();
+
+    assert!(validate_overlay_shard_schema(&shard(25, None, None), path).is_err());
+    for schema in 35..=OVERLAY_SHARD_SCHEMA {
+        validate_overlay_shard_schema(&shard(schema, None, None), path).unwrap();
+    }
+    assert!(
+        validate_overlay_shard_schema(&shard(OVERLAY_SHARD_SCHEMA + 1, None, None), path).is_err()
+    );
+    let error =
+        validate_overlay_shard_schema(&shard(26, Some(test_f8f6f4_admission()), None), path)
+            .unwrap_err();
+    assert!(
+        error
+            .to_string()
+            .contains("requires overlay shard schema 27")
+    );
+    let error = validate_overlay_shard_schema(&shard(27, None, Some(test_prmt_admission())), path)
+        .unwrap_err();
+    assert!(
+        error
+            .to_string()
+            .contains("requires overlay shard schema 28")
+    );
+    let mut f16_mma = shard(REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA, None, None);
+    f16_mma.family = "register_mma".into();
+    f16_mma.register_mma_f8f6f4_f16 = Some(test_register_mma_f8f6f4_admission(
+        RegisterMmaAccumulator::F16,
+    ));
+    validate_overlay_shard_schema(&f16_mma, path).unwrap();
+    f16_mma.schema -= 1;
+    assert!(
+        validate_overlay_shard_schema(&f16_mma, path)
+            .unwrap_err()
+            .to_string()
+            .contains("requires overlay shard schema 47")
+    );
+
+    let mut sparse_f16_mma = shard(SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA, None, None);
+    sparse_f16_mma.sparse_mma_f8f6f4_f16 = Some(test_sparse_mma_f8f6f4_f16_admission());
+    validate_overlay_shard_schema(&sparse_f16_mma, path).unwrap();
+    sparse_f16_mma.schema -= 1;
+    assert!(
+        validate_overlay_shard_schema(&sparse_f16_mma, path)
+            .unwrap_err()
+            .to_string()
+            .contains("requires overlay shard schema 50")
+    );
+
+    let mut standard_fp8_mma = shard(REGISTER_MMA_FP8_SHARD_SCHEMA, None, None);
+    standard_fp8_mma.family = "register_mma".into();
+    standard_fp8_mma.register_mma_fp8 = Some(test_register_mma_fp8_admission());
+    validate_overlay_shard_schema(&standard_fp8_mma, path).unwrap();
+    standard_fp8_mma.schema -= 1;
+    assert!(
+        validate_overlay_shard_schema(&standard_fp8_mma, path)
+            .unwrap_err()
+            .to_string()
+            .contains("requires overlay shard schema 48")
+    );
+
+    let fp8_shard = |schema| OverlayShardFile {
+        schema,
+        family: "packed_conversion".into(),
+        intrinsics: vec![],
+        register_mma_int4: None,
+        register_mma_int8: None,
+        register_mma_b1: None,
+        register_mma_f8f6f4_f32: None,
+        register_mma_f8f6f4_f16: None,
+        register_mma_mxf8f6f4_f32: None,
+        register_mma_fp8: None,
+        register_mma_ampere_float: None,
+        sparse_mma_integer: None,
+        sparse_mma_f8f6f4_f32: None,
+        sparse_mma_f8f6f4_f16: None,
+        prmt: None,
+        packed_conversion_fp8: Some(test_fp8_conversion_admission()),
+        packed_conversion_fp8_f16x2: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cluster_sreg: None,
+        cluster_barrier: None,
+        mbarrier_extended: None,
+        special_registers: None,
+        debug_control: None,
+        threadfence: None,
+        cluster_memory: None,
+        stmatrix: None,
+        clc: None,
+        wgmma_controls: None,
+        tma: None,
+        tcgen05: None,
+    };
+    validate_overlay_shard_schema(&fp8_shard(29), path).unwrap();
+    validate_overlay_shard_schema_with_max(&fp8_shard(29), path, 30).unwrap();
+    let error = validate_overlay_shard_schema(&fp8_shard(28), path).unwrap_err();
+    assert!(
+        error
+            .to_string()
+            .contains("requires overlay shard schema 29")
+    );
+
+    let cluster_shard = OverlayShardFile {
+        schema: 31,
+        family: "cluster_barrier".into(),
+        intrinsics: vec![],
+        register_mma_int4: None,
+        register_mma_int8: None,
+        register_mma_b1: None,
+        register_mma_f8f6f4_f32: None,
+        register_mma_f8f6f4_f16: None,
+        register_mma_mxf8f6f4_f32: None,
+        register_mma_fp8: None,
+        register_mma_ampere_float: None,
+        sparse_mma_integer: None,
+        sparse_mma_f8f6f4_f32: None,
+        sparse_mma_f8f6f4_f16: None,
+        prmt: None,
+        packed_conversion_fp8: None,
+        packed_conversion_fp8_f16x2: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cluster_sreg: None,
+        cluster_barrier: Some(test_cluster_barrier_admission()),
+        mbarrier_extended: None,
+        special_registers: None,
+        debug_control: None,
+        threadfence: None,
+        cluster_memory: None,
+        stmatrix: None,
+        clc: None,
+        wgmma_controls: None,
+        tma: None,
+        tcgen05: None,
+    };
+    validate_overlay_shard_schema_with_max(&cluster_shard, path, 31).unwrap();
+    let mut old_cluster_shard = cluster_shard;
+    old_cluster_shard.schema = 30;
+    assert!(
+        validate_overlay_shard_schema_with_max(&old_cluster_shard, path, 31)
+            .unwrap_err()
+            .to_string()
+            .contains("requires overlay shard schema 31")
+    );
+
+    let extended_shard = OverlayShardFile {
+        schema: MBARRIER_EXTENDED_SHARD_SCHEMA,
+        family: "mbarrier_extended".into(),
+        intrinsics: vec![],
+        register_mma_int4: None,
+        register_mma_int8: None,
+        register_mma_b1: None,
+        register_mma_f8f6f4_f32: None,
+        register_mma_f8f6f4_f16: None,
+        register_mma_mxf8f6f4_f32: None,
+        register_mma_fp8: None,
+        register_mma_ampere_float: None,
+        sparse_mma_integer: None,
+        sparse_mma_f8f6f4_f32: None,
+        sparse_mma_f8f6f4_f16: None,
+        prmt: None,
+        packed_conversion_fp8: None,
+        packed_conversion_fp8_f16x2: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cluster_sreg: None,
+        cluster_barrier: None,
+        mbarrier_extended: Some(test_mbarrier_extended_admission()),
+        special_registers: None,
+        debug_control: None,
+        threadfence: None,
+        cluster_memory: None,
+        stmatrix: None,
+        clc: None,
+        wgmma_controls: None,
+        tma: None,
+        tcgen05: None,
+    };
+    validate_overlay_shard_schema_with_max(&extended_shard, path, MBARRIER_EXTENDED_SHARD_SCHEMA)
+        .unwrap();
+    let mut old_extended_shard = extended_shard;
+    old_extended_shard.schema = MBARRIER_EXTENDED_SHARD_SCHEMA - 1;
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &old_extended_shard,
+            path,
+            MBARRIER_EXTENDED_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("requires overlay shard schema 40")
+    );
+}
+
+#[test]
+fn existing_catalog_intrinsics_keep_their_json_shape_without_kind() {
+    fn abi_number(abi_id: &str) -> u16 {
+        validate_abi_id(abi_id).unwrap();
+        abi_id[1..].parse().unwrap()
+    }
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let original: serde_json::Value =
+        read_json(&repo_root.join("intrinsics/catalog.json")).unwrap();
+    let catalog: CatalogFile = read_json(&repo_root.join("intrinsics/catalog.json")).unwrap();
+    let serialized = serde_json::to_value(&catalog).unwrap();
+    let original_by_abi = original["intrinsics"]
+        .as_array()
+        .unwrap()
+        .iter()
+        .map(|record| {
+            let abi_id = record["rust"]["abi_id"].as_str().unwrap();
+            (abi_number(abi_id), record)
+        })
+        .collect::<BTreeMap<_, _>>();
+    let serialized_by_abi = serialized["intrinsics"]
+        .as_array()
+        .unwrap()
+        .iter()
+        .map(|record| {
+            let abi_id = record["rust"]["abi_id"].as_str().unwrap();
+            (abi_number(abi_id), record)
+        })
+        .collect::<BTreeMap<_, _>>();
+    for abi in 1..=503 {
+        assert_eq!(original_by_abi.get(&abi), serialized_by_abi.get(&abi));
+    }
+
+    let existing = catalog
+        .intrinsics
+        .iter()
+        .filter(|record| abi_number(&record.rust.abi_id) <= 503)
+        .collect::<Vec<_>>();
+    assert_eq!(existing.len(), 503);
+    assert!(existing.iter().all(|record| {
+        record
+            .register_mma
+            .as_ref()
+            .is_none_or(|mma| mma.kind.is_none())
+    }));
+
+    let standard_fp8 = catalog
+        .intrinsics
+        .iter()
+        .filter(|record| (504..=519).contains(&abi_number(&record.rust.abi_id)))
+        .collect::<Vec<_>>();
+    assert!(standard_fp8.is_empty() || standard_fp8.len() == 16);
+    if standard_fp8.len() == 16 {
+        assert!(standard_fp8.iter().all(|record| {
+            record
+                .register_mma
+                .as_ref()
+                .is_some_and(|mma| mma.kind == Some(RegisterMmaKind::Standard))
+        }));
+        for abi in 504..=519 {
+            assert_eq!(original_by_abi[&abi]["register_mma"]["kind"], "standard");
+        }
+    }
+}
+
+#[test]
+fn duplicate_identity_surfaces_are_rejected_independently() {
+    let first = policy();
+
+    let mut second = distinct_policy();
+    second.abi_id = first.abi_id.clone();
+    assert!(
+        validate_unique_overlay(&[first.clone(), second], 1)
+            .unwrap_err()
+            .to_string()
+            .contains("duplicate intrinsic ABI ID")
+    );
+
+    let mut second = distinct_policy();
+    second.operation_key = first.operation_key.clone();
+    assert!(
+        validate_unique_overlay(&[first.clone(), second], 1)
+            .unwrap_err()
+            .to_string()
+            .contains("duplicate intrinsic operation key")
+    );
+
+    let mut second = distinct_policy();
+    second.public_rust_path = first.public_rust_path.clone();
+    assert!(
+        validate_unique_overlay(&[first.clone(), second], 1)
+            .unwrap_err()
+            .to_string()
+            .contains("duplicate public Rust path")
+    );
+
+    let mut second = distinct_policy();
+    second.dialect_op_name = first.dialect_op_name.clone();
+    assert!(
+        validate_unique_overlay(&[first.clone(), second], 1)
+            .unwrap_err()
+            .to_string()
+            .contains("duplicate dialect op variant")
+    );
+
+    let mut second = distinct_policy();
+    second.llvm_symbol = first.llvm_symbol.clone();
+    assert!(
+        validate_unique_overlay(&[first, second], 1)
+            .unwrap_err()
+            .to_string()
+            .contains("duplicate LLVM symbol")
+    );
+}
+
+#[test]
+fn safe_record_requires_an_allowlist_reason() {
+    let mut record = policy();
+    record.safe_allowlist_reason = None;
+    assert!(
+        validate_imported_policy(&record, &declaration())
+            .unwrap_err()
+            .to_string()
+            .contains("safe_allowlist_reason")
+    );
+}
+
+#[test]
+fn candidate_resolution_is_the_only_path_that_can_omit_evidence() {
+    let repo = repo_without_evidence();
+    let candidate = resolve_candidate(
+        &repo.0,
+        "thread_idx_x",
+        "LLVM version candidate",
+        &"a".repeat(64),
+        "sm_80",
+        "+ptx70",
+    )
+    .unwrap();
+    assert_eq!(candidate.catalog.intrinsics.len(), 1);
+    assert_eq!(candidate.catalog.intrinsics[0].id, "thread_idx_x");
+    assert_eq!(candidate.catalog.intrinsics[0].backend.status, "candidate");
+
+    let scalar = resolve_candidate(
+        &repo.0,
+        "i0390",
+        "LLVM version candidate",
+        &"a".repeat(64),
+        "sm_80",
+        "+ptx70",
+    )
+    .unwrap();
+    assert_eq!(scalar.catalog.intrinsics[0].id, "mul_rn_f64");
+    assert!(candidate.catalog.inputs.evidence_sha256.is_empty());
+
+    for (dense_id, abi_id) in [
+        ("mma_m16n8k32_f32_e2m1_e2m1", "i0454"),
+        ("mma_m16n8k32_f16_e2m1_e2m1", "i0479"),
+    ] {
+        let dense_by_name = resolve_candidate(
+            &repo.0,
+            dense_id,
+            "LLVM version candidate",
+            &"a".repeat(64),
+            "sm_120f",
+            "+ptx88",
+        )
+        .unwrap();
+        let dense_by_abi = resolve_candidate(
+            &repo.0,
+            abi_id,
+            "LLVM version candidate",
+            &"a".repeat(64),
+            "sm_120f",
+            "+ptx88",
+        )
+        .unwrap();
+        assert_eq!(
+            dense_by_name.catalog.intrinsics,
+            dense_by_abi.catalog.intrinsics
+        );
+        for lookup in [dense_id, abi_id] {
+            let error = resolve_candidate(
+                &repo.0,
+                lookup,
+                "LLVM version candidate",
+                &"a".repeat(64),
+                "sm_120f",
+                "+ptx87",
+            )
+            .unwrap_err();
+            assert!(error.to_string().contains(dense_id), "{error:#}");
+        }
+    }
+
+    let error = resolve(&repo.0).unwrap_err();
+    assert!(
+        error.to_string().contains("intrinsics/evidence"),
+        "{error:#}"
+    );
+    let error = resolve_candidate(
+        &repo.0,
+        "not_an_intrinsic",
+        "LLVM version candidate",
+        &"a".repeat(64),
+        "sm_80",
+        "+ptx70",
+    )
+    .unwrap_err();
+    assert!(error.to_string().contains("unknown overlay intrinsic"));
+}
+
+#[test]
+fn candidate_resolution_cannot_change_normal_catalog_bytes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let before = crate::util::pretty_json(&resolve(&repo_root).unwrap()).unwrap();
+    resolve_candidate(
+        &repo_root,
+        "thread_idx_x",
+        "LLVM version candidate",
+        &"a".repeat(64),
+        "sm_80",
+        "+ptx70",
+    )
+    .unwrap();
+    let after = crate::util::pretty_json(&resolve(&repo_root).unwrap()).unwrap();
+    assert_eq!(before.as_bytes(), after.as_bytes());
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/scalar_packed.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/scalar_packed.rs
new file mode 100644
index 0000000000..213107132c
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/scalar_packed.rs
@@ -0,0 +1,1041 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogFile, ExtendedMinMaxAdmission, ExtendedMinMaxFormat,
+    ExtendedMinMaxNan, ExtendedMinMaxOperation, ExtendedMinMaxSubnormal, ImportedFile,
+    ImportedIntrinsic, IntrinsicBackend, IntrinsicSource, OverlayIntrinsic, OverlayShardFile,
+    PackedAluFormat, PackedAluOperation, PackedConversionDestinationFormat,
+    PackedConversionRounding, PackedConversionSaturation, PrmtMode, RuntimeValidation,
+    ScalarArithmeticAdmission, ScalarArithmeticFormat, ScalarArithmeticOperation,
+    ScalarArithmeticRounding, ScalarArithmeticSaturation, ScalarArithmeticSubnormal,
+    ScalarConversionAdmission, ScalarConversionRounding, ScalarConversionSaturation,
+    ScalarMathAdmission,
+};
+use crate::util::read_json;
+use std::collections::BTreeMap;
+use std::path::Path;
+
+use super::fixtures::*;
+use crate::model::{ImportedSelection, ScalarConversionAdmissionVariant};
+use crate::resolve::driver::*;
+use crate::resolve::families::*;
+use crate::resolve::guards::*;
+use crate::resolve::overlay::*;
+use crate::resolve::policy::*;
+
+#[test]
+fn compact_prmt_admission_requires_every_mode_and_reserved_abi_id() {
+    assert_eq!(
+        expand_prmt_admission(&test_prmt_admission()).unwrap().len(),
+        7
+    );
+
+    let mut missing = test_prmt_admission();
+    missing.variants.pop();
+    assert!(expand_prmt_admission(&missing).is_err());
+
+    let mut duplicate = test_prmt_admission();
+    duplicate.variants[6].mode = PrmtMode::Rc8;
+    assert!(expand_prmt_admission(&duplicate).is_err());
+
+    let mut wrong_abi = test_prmt_admission();
+    wrong_abi.variants[0].abi_id = "i9999".into();
+    assert!(expand_prmt_admission(&wrong_abi).is_err());
+}
+
+#[test]
+fn compact_fp8_conversion_axes_require_the_exact_closed_product() {
+    let records = expand_packed_conversion_fp8_admission(&test_fp8_conversion_admission()).unwrap();
+    assert_eq!(records.len(), 4);
+    assert_eq!(records[0].id, "cvt_rn_satfinite_e4m3x2_f32");
+    assert_eq!(records[1].id, "cvt_rn_satfinite_relu_e4m3x2_f32");
+    assert_eq!(records[2].id, "cvt_rn_satfinite_e5m2x2_f32");
+    assert_eq!(records[3].id, "cvt_rn_satfinite_relu_e5m2x2_f32");
+    assert!(records.iter().all(|record| {
+        record.rust_result == "u16"
+            && record.dialect_results == ["i16"]
+            && record.llvm_results == ["i16"]
+            && record.minimum_ptx == "8.1"
+            && record.minimum_sm.as_deref() == Some("sm_89")
+            && record.pure
+            && !record.convergent
+    }));
+
+    let mut missing_format = test_fp8_conversion_admission();
+    missing_format.destination_formats.pop();
+    assert!(expand_packed_conversion_fp8_admission(&missing_format).is_err());
+
+    let mut reversed_formats = test_fp8_conversion_admission();
+    reversed_formats.destination_formats.reverse();
+    assert!(expand_packed_conversion_fp8_admission(&reversed_formats).is_err());
+
+    let mut missing_saturation = test_fp8_conversion_admission();
+    missing_saturation.saturations.pop();
+    assert!(expand_packed_conversion_fp8_admission(&missing_saturation).is_err());
+
+    let mut reversed_saturations = test_fp8_conversion_admission();
+    reversed_saturations.saturations.reverse();
+    assert!(expand_packed_conversion_fp8_admission(&reversed_saturations).is_err());
+
+    let mut wrong_count = test_fp8_conversion_admission();
+    wrong_count.product_count = 3;
+    assert!(expand_packed_conversion_fp8_admission(&wrong_count).is_err());
+
+    let mut executed = test_fp8_conversion_admission();
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_packed_conversion_fp8_admission(&executed).is_err());
+}
+
+#[test]
+fn compact_fp8_f16x2_conversion_axes_require_the_exact_closed_product() {
+    let records =
+        expand_packed_conversion_fp8_f16x2_admission(&test_fp8_f16x2_conversion_admission())
+            .unwrap();
+    assert_eq!(records.len(), 8);
+    assert_eq!(records[0].id, "cvt_rn_satfinite_e4m3x2_f16x2");
+    assert_eq!(records[1].id, "cvt_rn_satfinite_relu_e4m3x2_f16x2");
+    assert_eq!(records[2].id, "cvt_rn_f16x2_e4m3x2");
+    assert_eq!(records[3].id, "cvt_rn_relu_f16x2_e4m3x2");
+    assert_eq!(records[4].id, "cvt_rn_satfinite_e5m2x2_f16x2");
+    assert_eq!(records[5].id, "cvt_rn_satfinite_relu_e5m2x2_f16x2");
+    assert_eq!(records[6].id, "cvt_rn_f16x2_e5m2x2");
+    assert_eq!(records[7].id, "cvt_rn_relu_f16x2_e5m2x2");
+
+    // Every form takes one packed operand and carries the Ada floor,
+    // including the unpacks whose destination is the older f16x2.
+    assert!(records.iter().all(|record| {
+        record.rust_arguments.len() == 1
+            && record.dialect_operands.len() == 1
+            && record.llvm_arguments.len() == 1
+            && record.expected_ptx.operands.len() == 2
+            && record.minimum_ptx == "8.1"
+            && record.minimum_sm.as_deref() == Some("sm_89")
+            && record.pure
+            && !record.convergent
+    }));
+
+    // Packing narrows f16x2 to a 16-bit FP8 pair; unpacking widens back.
+    assert!(
+        records
+            .iter()
+            .filter(|record| record.id.ends_with("_f16x2"))
+            .all(|record| {
+                record.rust_arguments == ["u32"]
+                    && record.rust_result == "u16"
+                    && record.llvm_arguments == ["v2f16"]
+                    && record.llvm_results == ["i16"]
+            })
+    );
+    assert!(
+        records
+            .iter()
+            .filter(|record| !record.id.ends_with("_f16x2"))
+            .all(|record| {
+                record.rust_arguments == ["u16"]
+                    && record.rust_result == "u32"
+                    && record.llvm_arguments == ["i16"]
+                    && record.llvm_results == ["v2f16"]
+            })
+    );
+
+    let mut missing_format = test_fp8_f16x2_conversion_admission();
+    missing_format.fp8_formats.pop();
+    assert!(expand_packed_conversion_fp8_f16x2_admission(&missing_format).is_err());
+
+    let mut reversed_formats = test_fp8_f16x2_conversion_admission();
+    reversed_formats.fp8_formats.reverse();
+    assert!(expand_packed_conversion_fp8_f16x2_admission(&reversed_formats).is_err());
+
+    let mut missing_direction = test_fp8_f16x2_conversion_admission();
+    missing_direction.directions.pop();
+    assert!(expand_packed_conversion_fp8_f16x2_admission(&missing_direction).is_err());
+
+    let mut reversed_directions = test_fp8_f16x2_conversion_admission();
+    reversed_directions.directions.reverse();
+    assert!(expand_packed_conversion_fp8_f16x2_admission(&reversed_directions).is_err());
+
+    let mut without_relu = test_fp8_f16x2_conversion_admission();
+    without_relu.relu_variants = false;
+    assert!(expand_packed_conversion_fp8_f16x2_admission(&without_relu).is_err());
+
+    let mut wrong_count = test_fp8_f16x2_conversion_admission();
+    wrong_count.product_count = 4;
+    assert!(expand_packed_conversion_fp8_f16x2_admission(&wrong_count).is_err());
+
+    let mut executed = test_fp8_f16x2_conversion_admission();
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_packed_conversion_fp8_f16x2_admission(&executed).is_err());
+}
+
+#[test]
+fn packed_atomic_closed_semantics_reject_every_unreviewed_mutation() {
+    let valid = packed_policy("packed_atomic_add_f16x2");
+    validate_ptx_native_policy(&valid).unwrap();
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let overlay =
+        std::fs::read_to_string(repo_root.join("intrinsics/overlay/packed_atomic.toml")).unwrap();
+    for (field, accepted, rejected) in [
+        (
+            "state space",
+            "state_space = \"global\"",
+            "state_space = \"shared\"",
+        ),
+        (
+            "ordering",
+            "ordering = \"relaxed\"",
+            "ordering = \"acquire\"",
+        ),
+        ("scope", "scope = \"gpu\"", "scope = \"system\""),
+        (
+            "rounding",
+            "rounding = \"nearest_even\"",
+            "rounding = \"toward_zero\"",
+        ),
+        (
+            "subnormal",
+            "subnormal = \"preserve\"",
+            "subnormal = \"flush\"",
+        ),
+        (
+            "atomicity",
+            "atomicity = \"per_element\"",
+            "atomicity = \"coherent_pair\"",
+        ),
+        (
+            "pointer safety",
+            "pointer_contract = \"mutable_global_u32_aligned4\"",
+            "pointer_contract = \"unaligned\"",
+        ),
+        (
+            "mixed access safety",
+            "access_contract = \"no_mixed_whole_word_or_non_atomic_access\"",
+            "access_contract = \"mixed_access_allowed\"",
+        ),
+        (
+            "scope safety",
+            "scope_contract = \"racing_atomics_mutually_inclusive\"",
+            "scope_contract = \"scope_unchecked\"",
+        ),
+        (
+            "codegen",
+            "codegen_contract = \"exact_native_instruction\"",
+            "codegen_contract = \"semantic_equivalence\"",
+        ),
+    ] {
+        let mutated = overlay.replacen(accepted, rejected, 1);
+        let error = toml::from_str::<OverlayShardFile>(&mutated).unwrap_err();
+        assert!(
+            error
+                .to_string()
+                .contains(rejected.split(" = ").next().unwrap()),
+            "{field} mutation did not fail closed: {error}"
+        );
+    }
+
+    let mut safe = valid;
+    safe.safe = true;
+    safe.safe_allowlist_reason = Some("incorrectly claims no caller obligations".into());
+    assert!(
+        validate_ptx_native_policy(&safe)
+            .unwrap_err()
+            .to_string()
+            .contains("unsafe must-use packed atomic")
+    );
+}
+
+#[test]
+fn packed_alu_recipes_accept_only_the_reviewed_source_shape_and_floor() {
+    let operations = [
+        PackedAluOperation::Add,
+        PackedAluOperation::Sub,
+        PackedAluOperation::Mul,
+        PackedAluOperation::Fma,
+        PackedAluOperation::FmaRelu,
+        PackedAluOperation::Min,
+        PackedAluOperation::Max,
+        PackedAluOperation::Neg,
+        PackedAluOperation::Abs,
+    ];
+    for format in [PackedAluFormat::Bf16x2, PackedAluFormat::F16x2] {
+        for operation in operations {
+            let policy = packed_alu_policy(format, operation);
+            match packed_alu_declaration(format, operation) {
+                Some(declaration) => validate_imported_policy(&policy, &declaration).unwrap(),
+                None => validate_ptx_native_policy(&policy).unwrap(),
+            }
+        }
+    }
+
+    let declaration =
+        packed_alu_declaration(PackedAluFormat::Bf16x2, PackedAluOperation::Fma).unwrap();
+    let reject_imported = |policy: &OverlayIntrinsic, message: &str| {
+        let error = validate_imported_policy(policy, &declaration).unwrap_err();
+        assert!(error.to_string().contains(message), "{error:#}");
+    };
+
+    let valid = packed_alu_policy(PackedAluFormat::Bf16x2, PackedAluOperation::Fma);
+    let mut wrong_source = valid.clone();
+    wrong_source.source_record = Some("int_nvvm_fma_rn_bf16".into());
+    reject_imported(&wrong_source, "source");
+
+    let mut wrong_format = valid.clone();
+    wrong_format.packed_alu.as_mut().unwrap().format = PackedAluFormat::F16x2;
+    reject_imported(&wrong_format, "identity");
+
+    let mut wrong_operation = valid.clone();
+    wrong_operation.packed_alu.as_mut().unwrap().operation = PackedAluOperation::Max;
+    reject_imported(&wrong_operation, "identity");
+
+    let mut wrong_floor = valid.clone();
+    wrong_floor.minimum_sm = Some("sm_90".into());
+    reject_imported(&wrong_floor, "target floor");
+
+    let mut wrong_effects = valid.clone();
+    wrong_effects.memory = "read".into();
+    reject_imported(&wrong_effects, "effects");
+
+    let mut wrong_section = valid.clone();
+    wrong_section.ptx_isa_section = "9.7.4 Floating Point Instructions".into();
+    reject_imported(&wrong_section, "PTX provenance");
+
+    let mut wrong_url = valid.clone();
+    wrong_url.ptx_isa_url =
+        "https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions"
+            .into();
+    reject_imported(&wrong_url, "PTX provenance");
+
+    let mut wrong_adapter = valid.clone();
+    wrong_adapter.lowering = "direct_nvvm".into();
+    reject_imported(&wrong_adapter, "lowering recipe");
+
+    let mut wrong_backend = valid;
+    wrong_backend.backend_lowerings[0].mechanism = BackendLoweringMechanism::TypedNvvm;
+    reject_imported(&wrong_backend, "inline-PTX routes");
+
+    let mut wrong_native = packed_alu_policy(PackedAluFormat::Bf16x2, PackedAluOperation::Add);
+    wrong_native.source = Some(IntrinsicSource::PtxNative {
+        instruction: "add.bf16x2".into(),
+    });
+    let error = validate_ptx_native_policy(&wrong_native).unwrap_err();
+    assert!(error.to_string().contains("PTX-native recipe"));
+
+    let mut invented_llvm = packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Add);
+    invented_llvm.llvm_symbol = Some("llvm.nvvm.add.rn.f16x2".into());
+    let error = validate_ptx_native_policy(&invented_llvm).unwrap_err();
+    assert!(
+        error
+            .to_string()
+            .contains("must not invent LLVM source facts")
+    );
+
+    let mut unreviewed_modifier =
+        packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Add);
+    unreviewed_modifier.expected_ptx.modifiers = vec!["rn".into(), "ftz".into(), "f16x2".into()];
+    let error = validate_ptx_native_policy(&unreviewed_modifier).unwrap_err();
+    assert!(error.to_string().contains("exact packed-ALU instruction"));
+
+    let mut wrong_arity = packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Add);
+    wrong_arity.expected_ptx.operands.pop();
+    let error = validate_ptx_native_policy(&wrong_arity).unwrap_err();
+    assert!(error.to_string().contains("exact packed-ALU instruction"));
+
+    let f16_declaration =
+        packed_alu_declaration(PackedAluFormat::F16x2, PackedAluOperation::Fma).unwrap();
+    let reject_f16 = |policy: &OverlayIntrinsic, message: &str| {
+        let error = validate_imported_policy(policy, &f16_declaration).unwrap_err();
+        assert!(error.to_string().contains(message), "{error:#}");
+    };
+    let f16 = packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Fma);
+
+    let mut wrong_signature = f16.clone();
+    wrong_signature.llvm_arguments = vec!["v2bf16".into(); 3];
+    reject_f16(&wrong_signature, "LLVM argument signature mismatch");
+
+    let mut missing_must_use = f16.clone();
+    missing_must_use.must_use = false;
+    reject_f16(&missing_must_use, "reviewed safe packed-ALU API");
+
+    let mut wrong_native_floor = f16.clone();
+    wrong_native_floor
+        .packed_alu
+        .as_mut()
+        .unwrap()
+        .native_minimum_sm = 70;
+    reject_f16(&wrong_native_floor, "target floor");
+
+    let mut wrong_backend_floor = f16;
+    wrong_backend_floor.backend_lowerings[0].minimum_ptx = Some("4.2".into());
+    reject_f16(&wrong_backend_floor, "exact packed-ALU floor");
+
+    let abs_declaration =
+        packed_alu_declaration(PackedAluFormat::F16x2, PackedAluOperation::Abs).unwrap();
+    let mut wrong_abs = packed_alu_policy(PackedAluFormat::F16x2, PackedAluOperation::Abs);
+    wrong_abs.resolved_llvm_symbol = Some("llvm.nvvm.fabs.v2bf16".into());
+    let error = validate_imported_policy(&wrong_abs, &abs_declaration).unwrap_err();
+    assert!(error.to_string().contains("LLVM source or signature"));
+}
+
+#[test]
+fn pinned_packed_alu_records_match_the_closed_recipes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect();
+    let packed: Vec<_> = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "packed_alu")
+        .collect();
+    assert_eq!(packed.len(), 30);
+    for policy in packed {
+        let source = resolve_policy_source(policy).unwrap();
+        let declaration = policy
+            .source_record
+            .as_deref()
+            .map(|record| declarations[record]);
+        validate_policy(policy, &source, declaration, 1).unwrap();
+    }
+}
+
+#[test]
+fn pinned_packed_conversion_records_match_the_closed_recipes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let overlay = load_resolution_base(&repo_root).unwrap().overlay;
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect();
+    let packed: Vec<_> = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "packed_conversion")
+        .collect();
+    assert_eq!(packed.len(), 18);
+    for policy in packed {
+        let source = resolve_policy_source(policy).unwrap();
+        let declaration = policy
+            .source_record
+            .as_deref()
+            .map(|record| declarations[record]);
+        validate_policy(policy, &source, declaration, 1).unwrap();
+    }
+}
+
+#[test]
+fn selectionless_packed_conversion_is_admitted_only_by_its_closed_recipe() {
+    let cases = [
+        (
+            PackedConversionDestinationFormat::Bf16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::None,
+        ),
+        (
+            PackedConversionDestinationFormat::F16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::None,
+        ),
+        (
+            PackedConversionDestinationFormat::F16x2,
+            PackedConversionRounding::TowardZero,
+            PackedConversionSaturation::None,
+        ),
+        (
+            PackedConversionDestinationFormat::F16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Relu,
+        ),
+        (
+            PackedConversionDestinationFormat::Bf16x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Relu,
+        ),
+        (
+            PackedConversionDestinationFormat::Bf16x2,
+            PackedConversionRounding::TowardZero,
+            PackedConversionSaturation::None,
+        ),
+        (
+            PackedConversionDestinationFormat::E4m3x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Satfinite,
+        ),
+        (
+            PackedConversionDestinationFormat::E4m3x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::SatfiniteRelu,
+        ),
+        (
+            PackedConversionDestinationFormat::E5m2x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::Satfinite,
+        ),
+        (
+            PackedConversionDestinationFormat::E5m2x2,
+            PackedConversionRounding::NearestEven,
+            PackedConversionSaturation::SatfiniteRelu,
+        ),
+    ];
+    for (destination, rounding, saturation) in cases {
+        let policy = packed_conversion_policy(destination, rounding, saturation);
+        let declaration = packed_conversion_declaration(&policy);
+        validate_imported_policy(&policy, &declaration).unwrap();
+    }
+
+    let valid = packed_conversion_policy(
+        PackedConversionDestinationFormat::Bf16x2,
+        PackedConversionRounding::NearestEven,
+        PackedConversionSaturation::None,
+    );
+    let declaration = packed_conversion_declaration(&valid);
+
+    let reject = |policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic, message: &str| {
+        let error = validate_imported_policy(policy, declaration).unwrap_err();
+        assert!(error.to_string().contains(message), "{error:#}");
+    };
+
+    let mut wrong_source = valid.clone();
+    wrong_source.source_record = Some("int_nvvm_ff2bf16x2_rz".into());
+    reject(&wrong_source, &declaration, "identity or LLVM source");
+
+    let mut wrong_floor = valid.clone();
+    wrong_floor.minimum_ptx = "7.8".into();
+    reject(&wrong_floor, &declaration, "target floor");
+
+    let mut wrong_effect = valid.clone();
+    wrong_effect.pure = false;
+    reject(&wrong_effect, &declaration, "effects");
+
+    let mut wrong_section = valid.clone();
+    wrong_section.ptx_isa_section = "9.7.9 Data Movement and Conversion Instructions".into();
+    reject(&wrong_section, &declaration, "PTX provenance");
+
+    let mut wrong_url = valid.clone();
+    wrong_url.ptx_isa_url =
+            "https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions"
+                .into();
+    reject(&wrong_url, &declaration, "PTX provenance");
+
+    let mut wrong_shape = valid.clone();
+    wrong_shape.expected_ptx.modifiers.swap(1, 2);
+    reject(&wrong_shape, &declaration, "expected PTX does not match");
+
+    let mut wrong_identity = valid.clone();
+    wrong_identity.id = "cvt_f16x2_f32".into();
+    reject(&wrong_identity, &declaration, "identity or LLVM source");
+
+    let mut unsupported = valid.clone();
+    let conversion = unsupported.packed_conversion.as_mut().unwrap();
+    conversion.rounding = PackedConversionRounding::TowardZero;
+    conversion.saturation = PackedConversionSaturation::Relu;
+    reject(
+        &unsupported,
+        &declaration,
+        "unsupported packed-conversion source, destination",
+    );
+
+    let mut wrong_compatibility = valid.clone();
+    wrong_compatibility.compatibility_rust_paths =
+        vec!["cuda_device::tcgen05::cvt_f32x2_bf16x2".into()];
+    reject(&wrong_compatibility, &declaration, "conversion API");
+
+    let mut wrong_result = valid.clone();
+    wrong_result.llvm_results = vec!["v2f16".into()];
+    reject(&wrong_result, &declaration, "result signature mismatch");
+
+    let mut selected = declaration.clone();
+    selected.selections.push(ImportedSelection {
+        source_record: "UNREVIEWED".into(),
+        asm: "cvt.rn.bf16x2.f32 $d, $a, $b;".into(),
+        predicates: vec![],
+        constraints: Default::default(),
+    });
+    reject(&valid, &selected, "selectionless");
+}
+
+#[test]
+fn scalar_conversion_admission_is_closed_and_backend_specific() {
+    let variants = [
+        (
+            "i0368",
+            ScalarConversionRounding::NearestAway,
+            ScalarConversionSaturation::None,
+        ),
+        (
+            "i0369",
+            ScalarConversionRounding::NearestAway,
+            ScalarConversionSaturation::Satfinite,
+        ),
+        (
+            "i0370",
+            ScalarConversionRounding::NearestEven,
+            ScalarConversionSaturation::None,
+        ),
+        (
+            "i0371",
+            ScalarConversionRounding::NearestEven,
+            ScalarConversionSaturation::Relu,
+        ),
+        (
+            "i0372",
+            ScalarConversionRounding::NearestEven,
+            ScalarConversionSaturation::Satfinite,
+        ),
+        (
+            "i0373",
+            ScalarConversionRounding::NearestEven,
+            ScalarConversionSaturation::ReluSatfinite,
+        ),
+        (
+            "i0374",
+            ScalarConversionRounding::TowardZero,
+            ScalarConversionSaturation::None,
+        ),
+        (
+            "i0375",
+            ScalarConversionRounding::TowardZero,
+            ScalarConversionSaturation::Relu,
+        ),
+        (
+            "i0376",
+            ScalarConversionRounding::TowardZero,
+            ScalarConversionSaturation::Satfinite,
+        ),
+        (
+            "i0377",
+            ScalarConversionRounding::TowardZero,
+            ScalarConversionSaturation::ReluSatfinite,
+        ),
+    ];
+    let admission = ScalarConversionAdmission {
+        llvm_evidence_profile: "llvm-scalar".into(),
+        libnvvm_evidence_profile: "libnvvm-scalar".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: variants
+            .iter()
+            .map(
+                |(abi_id, rounding, saturation)| ScalarConversionAdmissionVariant {
+                    abi_id: (*abi_id).into(),
+                    rounding: *rounding,
+                    saturation: *saturation,
+                },
+            )
+            .collect(),
+    };
+
+    let records = expand_scalar_conversion_admission(&admission).unwrap();
+    assert_eq!(records.len(), 10);
+    for (record, (abi_id, rounding, saturation)) in records.iter().zip(variants) {
+        assert_eq!(record.abi_id, abi_id);
+        assert_eq!(record.rust_arguments, ["f32"]);
+        assert_eq!(record.rust_result, "u32");
+        assert_eq!(
+            record.compatibility_rust_paths,
+            [format!("cuda_device::convert::{}", record.rust_name)]
+        );
+        let conversion = record.scalar_conversion.as_ref().unwrap();
+        assert_eq!(conversion.rounding, rounding);
+        assert_eq!(conversion.saturation, saturation);
+        assert!(record.backend_lowerings.iter().any(|lowering| {
+            lowering.backend == IntrinsicBackend::LlvmNvptx
+                && lowering.mechanism == BackendLoweringMechanism::TypedNvvm
+        }));
+        assert!(record.backend_lowerings.iter().any(|lowering| {
+            lowering.backend == IntrinsicBackend::LibNvvm
+                && lowering.mechanism == BackendLoweringMechanism::InlinePtx
+        }));
+    }
+
+    let mut reordered = admission.clone();
+    reordered.variants.swap(0, 1);
+    assert!(
+        expand_scalar_conversion_admission(&reordered)
+            .unwrap_err()
+            .to_string()
+            .contains("canonical ten variants")
+    );
+}
+
+#[test]
+fn scalar_arithmetic_admission_is_closed_and_selects_only_direct_ptx() {
+    let variants = canonical_scalar_arithmetic_variants();
+    let admission = ScalarArithmeticAdmission {
+        llvm_evidence_profile: "llvm-scalar-arithmetic".into(),
+        libnvvm_evidence_profile: "libnvvm-scalar-arithmetic".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: variants
+            .iter()
+            .copied()
+            .enumerate()
+            .map(
+                |(index, variant)| crate::model::ScalarArithmeticAdmissionVariant {
+                    abi_id: format!("i{:04}", 390 + index),
+                    format: variant.0,
+                    operation: variant.1,
+                    rounding: variant.2,
+                    subnormal: variant.3,
+                    saturation: variant.4,
+                },
+            )
+            .collect(),
+    };
+    let records = expand_scalar_arithmetic_admission(&admission).unwrap();
+    assert_eq!(records.len(), 64);
+    assert_eq!(records.first().unwrap().id, "mul_rn_f64");
+    assert_eq!(records.first().unwrap().abi_id, "i0390");
+    assert_eq!(records.last().unwrap().id, "add_rp_ftz_sat_f32");
+    assert_eq!(records.last().unwrap().abi_id, "i0453");
+    validate_unique_overlay(&records, 1).unwrap();
+    let llvm_inline_count = records
+        .iter()
+        .filter(|record| {
+            record.backend_lowerings.iter().any(|lowering| {
+                lowering.backend == IntrinsicBackend::LlvmNvptx
+                    && lowering.mechanism == BackendLoweringMechanism::InlinePtx
+            })
+        })
+        .count();
+    assert_eq!(llvm_inline_count, 16);
+    assert!(records.iter().all(|record| {
+        let expected = if record
+            .scalar_arithmetic
+            .as_ref()
+            .is_some_and(|arithmetic| arithmetic.saturation == ScalarArithmeticSaturation::Sat)
+        {
+            BackendLoweringMechanism::InlinePtx
+        } else {
+            BackendLoweringMechanism::TypedNvvm
+        };
+        record.backend_lowerings.iter().any(|lowering| {
+            lowering.backend == IntrinsicBackend::LlvmNvptx && lowering.mechanism == expected
+        })
+    }));
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .into_iter()
+        .map(|record| (record.source_record.clone(), record))
+        .collect::<BTreeMap<_, _>>();
+    let mut mixed_count = 0;
+    let mut add_two_selection_count = 0;
+    let mut add_six_selection_count = 0;
+    for record in &records {
+        let declaration = &declarations[record.source_record.as_ref().unwrap()];
+        validate_imported_policy(record, declaration).unwrap();
+        let selected = declaration
+            .selections
+            .iter()
+            .filter(|selection| selection_matches_policy(record, selection).unwrap())
+            .collect::<Vec<_>>();
+        assert_eq!(selected.len(), 1, "{}", record.id);
+        if declaration.selections.len() == 3 {
+            mixed_count += 1;
+        }
+        if record
+            .scalar_arithmetic
+            .as_ref()
+            .is_some_and(|contract| contract.operation == ScalarArithmeticOperation::Add)
+        {
+            match declaration.selections.len() {
+                2 => add_two_selection_count += 1,
+                6 => add_six_selection_count += 1,
+                count => panic!("unexpected add selection count {count}"),
+            }
+        }
+    }
+    assert_eq!(mixed_count, 8);
+    assert_eq!(add_two_selection_count, 12);
+    assert_eq!(add_six_selection_count, 8);
+    let add_ftz_sat = records
+        .iter()
+        .find(|record| record.id == "add_rn_ftz_sat_f32")
+        .unwrap();
+    assert_eq!(
+        add_ftz_sat.expected_ptx.modifiers,
+        ["rn", "sat", "ftz", "f32"]
+    );
+
+    let mut non_contiguous_abi = admission.clone();
+    non_contiguous_abi.variants[0].abi_id = "i9999".into();
+    let non_contiguous_records = expand_scalar_arithmetic_admission(&non_contiguous_abi).unwrap();
+    assert_eq!(non_contiguous_records[0].abi_id, "i9999");
+
+    let mut reordered = admission.clone();
+    reordered.variants.swap(0, 1);
+    assert!(
+        expand_scalar_arithmetic_admission(&reordered)
+            .unwrap_err()
+            .to_string()
+            .contains("canonical 64 variants")
+    );
+    assert!(
+        scalar_arithmetic_recipe((
+            ScalarArithmeticFormat::F64,
+            ScalarArithmeticOperation::Fma,
+            ScalarArithmeticRounding::Rn,
+            ScalarArithmeticSubnormal::Ftz,
+            ScalarArithmeticSaturation::None,
+        ))
+        .is_none()
+    );
+}
+
+#[test]
+fn scalar_math_admission_keeps_semantic_order_but_accepts_non_contiguous_abi_ids() {
+    let variants = canonical_scalar_math_variants();
+    let admission = ScalarMathAdmission {
+        llvm_evidence_profile: "llvm-scalar-math".into(),
+        libnvvm_evidence_profile: "libnvvm-scalar-math".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: variants
+            .iter()
+            .copied()
+            .enumerate()
+            .map(
+                |(index, variant)| crate::model::ScalarMathAdmissionVariant {
+                    abi_id: format!("i{:04}", 782 + index),
+                    libnvvm_evidence_profile: (index == 40).then(|| "libnvvm-ex2-f16".into()),
+                    format: variant.0,
+                    operation: variant.1,
+                    precision: variant.2,
+                    subnormal: variant.3,
+                },
+            )
+            .collect(),
+    };
+
+    let records = expand_scalar_math_admission(&admission).unwrap();
+    assert_eq!(records.len(), 41);
+    assert_eq!(records.first().unwrap().abi_id, "i0782");
+    assert_eq!(records.last().unwrap().abi_id, "i0822");
+    assert!(
+        records
+            .iter()
+            .all(|record| record.backend_lowerings.len() == 2)
+    );
+    assert_eq!(
+        records.last().unwrap().backend_lowerings[1].evidence_profile,
+        "libnvvm-ex2-f16"
+    );
+    assert!(
+        records[..40].iter().all(|record| {
+            record.backend_lowerings[1].evidence_profile == "libnvvm-scalar-math"
+        })
+    );
+
+    let mut non_contiguous_abi = admission.clone();
+    non_contiguous_abi.variants[40].abi_id = "i9999".into();
+    let records = expand_scalar_math_admission(&non_contiguous_abi).unwrap();
+    assert_eq!(records.last().unwrap().abi_id, "i9999");
+
+    let mut reordered = admission;
+    reordered.variants.swap(0, 1);
+    assert!(
+        expand_scalar_math_admission(&reordered)
+            .unwrap_err()
+            .to_string()
+            .contains("canonical 41 variants")
+    );
+}
+
+#[test]
+fn checked_in_scalar_math_overlay_pins_the_current_libnvvm_override_set() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    let scalar_math = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "scalar_math")
+        .collect::<Vec<_>>();
+    assert_eq!(scalar_math.len(), 41);
+    assert!(
+        scalar_math
+            .iter()
+            .all(|record| record.backend_lowerings.len() == 2)
+    );
+
+    let family_profile = "cuda-13.3-libnvvm-13.3.33-scalar-math";
+    let overrides = scalar_math
+        .iter()
+        .filter_map(|record| {
+            let libnvvm = record
+                .backend_lowerings
+                .iter()
+                .find(|route| route.backend == IntrinsicBackend::LibNvvm)
+                .unwrap();
+            (libnvvm.evidence_profile != family_profile).then_some(record.id.as_str())
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(overrides, ["ex2_approx_f16"]);
+}
+
+#[test]
+fn extended_minmax_admission_is_exact_and_fail_closed() {
+    let variants = canonical_extended_minmax_variants();
+    let admission = ExtendedMinMaxAdmission {
+        llvm_evidence_profile: "llvm-extended-minmax".into(),
+        libnvvm_evidence_profile: "libnvvm-extended-minmax".into(),
+        runtime_validation: RuntimeValidation::Unexecuted,
+        variants: variants
+            .iter()
+            .copied()
+            .enumerate()
+            .map(
+                |(index, variant)| crate::model::ExtendedMinMaxAdmissionVariant {
+                    abi_id: if index < 28 {
+                        format!("i{:04}", 550 + index)
+                    } else {
+                        format!("i{:04}", 830 + index - 28)
+                    },
+                    format: variant.0,
+                    operation: variant.1,
+                    subnormal: variant.2,
+                    nan: variant.3,
+                    xorsign_abs: variant.4,
+                },
+            )
+            .collect(),
+    };
+    let records = expand_extended_minmax_admission(&admission).unwrap();
+    assert_eq!(records.len(), 52);
+    assert_eq!(records.first().unwrap().id, "min_ftz_f16x2");
+    assert_eq!(records.first().unwrap().abi_id, "i0550");
+    // The first reserved block ends here; the scalar 16-bit forms admitted
+    // afterwards continue at a second base rather than at i0578.
+    assert_eq!(records[27].id, "max_xorsign_abs_f16x2");
+    assert_eq!(records[27].abi_id, "i0577");
+    assert_eq!(records[28].id, "min_f16");
+    assert_eq!(records[28].abi_id, "i0830");
+    assert_eq!(records.last().unwrap().id, "max_nan_xorsign_abs_bf16");
+    assert_eq!(records.last().unwrap().abi_id, "i0853");
+    validate_unique_overlay(&records, 1).unwrap();
+    assert_eq!(
+        records
+            .iter()
+            .filter(|record| record.minimum_sm.as_deref() == Some("sm_80"))
+            .count(),
+        20
+    );
+    assert_eq!(
+        records
+            .iter()
+            .filter(|record| record.minimum_sm.as_deref() == Some("sm_86"))
+            .count(),
+        32
+    );
+    assert!(records.iter().all(|record| {
+        record.backend_lowerings.len() == 2
+            && record
+                .backend_lowerings
+                .iter()
+                .all(|lowering| lowering.mechanism == BackendLoweringMechanism::InlinePtx)
+    }));
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .into_iter()
+        .map(|record| (record.source_record.clone(), record))
+        .collect::<BTreeMap<_, _>>();
+    for record in &records {
+        let declaration = &declarations[record.source_record.as_ref().unwrap()];
+        assert_eq!(declaration.selections.len(), 1, "{}", record.id);
+        validate_imported_policy(record, declaration).unwrap();
+        assert_eq!(
+            declaration
+                .selections
+                .iter()
+                .filter(|selection| selection_matches_policy(record, selection).unwrap())
+                .count(),
+            1,
+            "{}",
+            record.id
+        );
+    }
+    let packed_max = records
+        .iter()
+        .find(|record| record.id == "max_nan_bf16x2")
+        .unwrap();
+    assert_eq!(
+        declarations[packed_max.source_record.as_ref().unwrap()].selections[0].source_record,
+        "INT_NVVM_FMAN_NaN_bf16x2"
+    );
+    assert_eq!(
+        declarations["int_nvvm_fmax_ftz_nan_xorsign_abs_f"].selections[0].source_record,
+        "INT_NVVM_FMAX_FTZ_NAN_XORSIGN_ABS_F"
+    );
+    assert!(
+        declarations["int_nvvm_fmax_ftz_nan_xorsign_abs_f"].selections[0]
+            .asm
+            .contains(".NaN.")
+    );
+    for excluded in [
+        "int_nvvm_fmin_ftz_bf16x2",
+        "int_nvvm_fmax_ftz_nan_bf16x2",
+        "int_nvvm_fmin_f",
+        "int_nvvm_fmax_nan_f",
+    ] {
+        assert!(declarations[excluded].selections.is_empty(), "{excluded}");
+        assert!(
+            records
+                .iter()
+                .all(|record| record.source_record.as_deref() != Some(excluded)),
+            "{excluded} was admitted without an instruction selection"
+        );
+    }
+
+    let catalog: CatalogFile = read_json(&repo_root.join("intrinsics/catalog.json")).unwrap();
+    for id in ["min_f16x2", "max_f16x2", "min_bf16x2", "max_bf16x2"] {
+        assert_eq!(
+            catalog
+                .intrinsics
+                .iter()
+                .find(|record| record.id == id)
+                .unwrap()
+                .family,
+            "packed_alu"
+        );
+        assert!(records.iter().all(|record| record.id != id));
+    }
+
+    let mut non_contiguous_abi = admission.clone();
+    non_contiguous_abi.variants[0].abi_id = "i9999".into();
+    let non_contiguous_records = expand_extended_minmax_admission(&non_contiguous_abi).unwrap();
+    assert_eq!(non_contiguous_records[0].abi_id, "i9999");
+
+    let mut reordered = admission.clone();
+    reordered.variants.swap(0, 1);
+    assert!(
+        expand_extended_minmax_admission(&reordered)
+            .unwrap_err()
+            .to_string()
+            .contains("exact canonical 28 variants")
+    );
+    assert!(
+        extended_minmax_recipe((
+            ExtendedMinMaxFormat::Bf16x2,
+            ExtendedMinMaxOperation::Min,
+            ExtendedMinMaxSubnormal::Ftz,
+            ExtendedMinMaxNan::Nan,
+            false,
+        ))
+        .is_none()
+    );
+    let mut changed = declarations["int_nvvm_fmin_ftz_f16x2"].clone();
+    changed.selections[0].predicates.swap(0, 1);
+    assert!(validate_imported_policy(&records[0], &changed).is_err());
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs
new file mode 100644
index 0000000000..b5ae466941
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs
@@ -0,0 +1,486 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, EvidenceStageKind, ImportedFile, IntrinsicBackend, IntrinsicSource,
+    OverlayShardFile, RuntimeValidation, SpecialRegisterOutputConstraint,
+};
+use crate::util::read_json;
+use std::collections::{BTreeMap, BTreeSet};
+use std::path::Path;
+
+use super::fixtures::*;
+use crate::resolve::driver::*;
+use crate::resolve::evidence::*;
+use crate::resolve::families::*;
+use crate::resolve::guards::*;
+use crate::resolve::overlay::*;
+use crate::resolve::policy::*;
+
+#[test]
+fn cluster_sreg_admission_uses_its_fixed_introduction_schema() {
+    let shard = |schema| {
+        toml::from_str::<OverlayShardFile>(&format!(
+            r#"
+schema = {schema}
+family = "sreg"
+
+[cluster_sreg]
+axes = ["x", "y", "z"]
+xyz_product_count = 12
+record_count = 14
+"#
+        ))
+        .unwrap()
+    };
+    let path = Path::new("intrinsics/overlay/sreg_cluster.toml");
+
+    let old = shard(CLUSTER_SREG_SHARD_SCHEMA - 1);
+    assert!(
+        validate_overlay_shard_schema(&old, path)
+            .unwrap_err()
+            .to_string()
+            .contains("requires overlay shard schema 30")
+    );
+
+    let current = shard(CLUSTER_SREG_SHARD_SCHEMA);
+    validate_overlay_shard_schema(&current, path).unwrap();
+    let admission = current.cluster_sreg.unwrap();
+    assert_eq!(expand_cluster_sreg_admission(&admission).unwrap().len(), 14);
+
+    let mut wrong_axes = admission.clone();
+    wrong_axes.axes.swap(0, 1);
+    assert!(expand_cluster_sreg_admission(&wrong_axes).is_err());
+
+    let mut wrong_count = admission;
+    wrong_count.record_count = 13;
+    assert!(expand_cluster_sreg_admission(&wrong_count).is_err());
+}
+
+#[test]
+fn special_register_admission_is_closed_and_schema_gated() {
+    let admission = test_special_register_admission();
+    let records = expand_special_register_admission(&admission).unwrap();
+    assert_eq!(records.len(), 12);
+    assert_eq!(
+        records
+            .iter()
+            .map(|record| record.id.as_str())
+            .collect::<Vec<_>>(),
+        [
+            "clock",
+            "clock64",
+            "globaltimer",
+            "envreg1",
+            "envreg2",
+            "smid",
+            "nsmid",
+            "gridid",
+            "warpid",
+            "nwarpid",
+            "dynamic_smem_size",
+            "total_smem_size",
+        ]
+    );
+
+    let mut reordered = admission.clone();
+    reordered.registers.swap(0, 1);
+    assert!(expand_special_register_admission(&reordered).is_err());
+
+    let mut wrong_count = admission.clone();
+    wrong_count.product_count -= 1;
+    assert!(expand_special_register_admission(&wrong_count).is_err());
+
+    let mut executed = admission.clone();
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_special_register_admission(&executed).is_err());
+
+    let shard = |schema| OverlayShardFile {
+        schema,
+        family: "sreg".into(),
+        intrinsics: vec![],
+        register_mma_int4: None,
+        register_mma_int8: None,
+        register_mma_b1: None,
+        register_mma_f8f6f4_f32: None,
+        register_mma_f8f6f4_f16: None,
+        register_mma_mxf8f6f4_f32: None,
+        register_mma_fp8: None,
+        register_mma_ampere_float: None,
+        sparse_mma_integer: None,
+        sparse_mma_f8f6f4_f32: None,
+        sparse_mma_f8f6f4_f16: None,
+        prmt: None,
+        packed_conversion_fp8: None,
+        packed_conversion_fp8_f16x2: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cluster_sreg: None,
+        cluster_barrier: None,
+        mbarrier_extended: None,
+        special_registers: Some(admission.clone()),
+        debug_control: None,
+        threadfence: None,
+        cluster_memory: None,
+        stmatrix: None,
+        clc: None,
+        wgmma_controls: None,
+        tma: None,
+        tcgen05: None,
+    };
+    let path = Path::new("intrinsics/overlay/sreg_special.toml");
+    validate_overlay_shard_schema(&shard(SPECIAL_REGISTER_SHARD_SCHEMA), path).unwrap();
+    assert!(
+        validate_overlay_shard_schema(&shard(SPECIAL_REGISTER_SHARD_SCHEMA - 1), path)
+            .unwrap_err()
+            .to_string()
+            .contains("requires overlay shard schema 32")
+    );
+}
+
+#[test]
+fn pinned_special_registers_preserve_apis_widths_and_backend_routes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let base = load_resolution_base(&repo_root).unwrap();
+    let declarations = index_imported_intrinsics(&base.imported).unwrap();
+    let records = base
+        .overlay
+        .intrinsics
+        .iter()
+        .filter(|record| record.special_register.is_some())
+        .collect::<Vec<_>>();
+    assert_eq!(records.len(), 12);
+    assert_eq!(
+        records
+            .iter()
+            .map(|record| record.abi_id.clone())
+            .collect::<BTreeSet<_>>(),
+        (283..=294)
+            .map(|id| format!("i{id:04}"))
+            .collect::<BTreeSet<_>>()
+    );
+
+    for record in &records {
+        let source = resolve_policy_source(record).unwrap();
+        let declaration = resolve_imported_declaration(record, &source, &declarations).unwrap();
+        validate_special_register_policy(record, &source, declaration).unwrap();
+        validate_special_register_llvm_exclusion(record, &declarations).unwrap();
+    }
+
+    for (id, section, anchor) in [
+        ("clock", "10.23", "special-registers-clock-clock-hi"),
+        ("clock64", "10.24", "special-registers-clock64"),
+        ("globaltimer", "10.28", "special-registers-globaltimer"),
+        ("envreg1", "10.27", "special-registers-envreg"),
+        ("envreg2", "10.27", "special-registers-envreg"),
+        ("smid", "10.8", "special-registers-smid"),
+        ("nsmid", "10.9", "special-registers-nsmid"),
+        ("gridid", "10.10", "special-registers-gridid"),
+        ("warpid", "10.4", "special-registers-warpid"),
+        ("nwarpid", "10.5", "special-registers-nwarpid"),
+        (
+            "dynamic_smem_size",
+            "10.32",
+            "special-registers-dynamic-smem-size",
+        ),
+        (
+            "total_smem_size",
+            "10.30",
+            "special-registers-total-smem-size",
+        ),
+    ] {
+        let record = records.iter().find(|record| record.id == id).unwrap();
+        assert!(record.ptx_isa_section.starts_with(section));
+        assert!(record.ptx_isa_url.ends_with(anchor));
+    }
+
+    let gridid = records.iter().find(|record| record.id == "gridid").unwrap();
+    assert_eq!(gridid.rust_result, "u64");
+    assert_eq!(gridid.dialect_results, ["i64"]);
+    assert!(matches!(
+        resolve_policy_source(gridid).unwrap(),
+        IntrinsicSource::PtxNative { .. }
+    ));
+    assert!(
+        gridid
+            .special_register
+            .as_ref()
+            .unwrap()
+            .llvm_exclusion
+            .is_some()
+    );
+
+    let clock = records.iter().find(|record| record.id == "clock").unwrap();
+    let source = resolve_policy_source(clock).unwrap();
+    let declaration = resolve_imported_declaration(clock, &source, &declarations)
+        .unwrap()
+        .unwrap();
+
+    let mut wrong_effects = (*clock).clone();
+    wrong_effects.memory = "none".into();
+    assert!(validate_special_register_policy(&wrong_effects, &source, Some(declaration)).is_err());
+
+    let mut wrong_contract = (*clock).clone();
+    wrong_contract
+        .special_register
+        .as_mut()
+        .unwrap()
+        .output_constraint = SpecialRegisterOutputConstraint::Register64;
+    assert!(validate_special_register_policy(&wrong_contract, &source, Some(declaration)).is_err());
+
+    let mut wrong_route = (*clock).clone();
+    wrong_route.backend_lowerings[0].mechanism = BackendLoweringMechanism::InlinePtx;
+    assert!(validate_special_register_policy(&wrong_route, &source, Some(declaration)).is_err());
+}
+
+#[test]
+fn special_register_evidence_validates_both_backend_routes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let policies = expand_special_register_admission(&test_special_register_admission()).unwrap();
+    let mut evidence_files = vec![
+        read_evidence_file(
+            &repo_root.join("intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-special-registers.json"),
+        )
+        .unwrap(),
+        read_evidence_file(
+            &repo_root.join("intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-special-registers.json"),
+        )
+        .unwrap(),
+    ];
+    let llvm_revision = "1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e";
+    let indexed = index_evidence(&evidence_files, llvm_revision).unwrap();
+    for policy in &policies {
+        for lowering in &policy.backend_lowerings {
+            let evidence = indexed
+                .get(&(lowering.evidence_profile.as_str(), policy.id.as_str()))
+                .unwrap();
+            validate_evidence(policy, evidence, Some(lowering)).unwrap();
+        }
+    }
+
+    let libnvvm = evidence_files
+        .iter_mut()
+        .find(|file| file.backend_kind == Some(IntrinsicBackend::LibNvvm))
+        .unwrap();
+    libnvvm
+        .records
+        .iter_mut()
+        .find(|record| record.id == "gridid")
+        .unwrap()
+        .stages
+        .retain(|stage| stage.stage != EvidenceStageKind::DeviceLink);
+    let indexed = index_evidence(&evidence_files, llvm_revision).unwrap();
+    let policy = policies
+        .iter()
+        .find(|policy| policy.id == "gridid")
+        .unwrap();
+    let lowering = policy
+        .backend_lowerings
+        .iter()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
+        .unwrap();
+    let evidence = indexed
+        .get(&(lowering.evidence_profile.as_str(), policy.id.as_str()))
+        .unwrap();
+    assert!(validate_evidence(policy, evidence, Some(lowering)).is_err());
+}
+
+#[test]
+fn threadfence_admission_is_closed_and_uses_schema_34() {
+    let shard = |schema| {
+        toml::from_str::<OverlayShardFile>(&format!(
+            r#"
+schema = {schema}
+family = "sync"
+
+[threadfence]
+llvm_evidence_profile = "llvm-test"
+libnvvm_evidence_profile = "libnvvm-test"
+runtime_validation = "unexecuted"
+
+[[threadfence.variant]]
+abi_id = "i0298"
+scope = "cta"
+
+[[threadfence.variant]]
+abi_id = "i0299"
+scope = "device"
+
+[[threadfence.variant]]
+abi_id = "i0300"
+scope = "system"
+"#
+        ))
+        .unwrap()
+    };
+    let path = Path::new("intrinsics/overlay/threadfence.toml");
+
+    let old = shard(THREADFENCE_SHARD_SCHEMA - 1);
+    assert!(
+        validate_overlay_shard_schema(&old, path)
+            .unwrap_err()
+            .to_string()
+            .contains("requires overlay shard schema 34")
+    );
+
+    let current = shard(THREADFENCE_SHARD_SCHEMA);
+    validate_overlay_shard_schema(&current, path).unwrap();
+    let admission = current.threadfence.unwrap();
+    let records = expand_threadfence_admission(&admission).unwrap();
+    assert_eq!(records.len(), 3);
+    assert_eq!(
+        records
+            .iter()
+            .map(|record| (record.abi_id.as_str(), record.id.as_str()))
+            .collect::<Vec<_>>(),
+        [
+            ("i0298", "threadfence_block"),
+            ("i0299", "threadfence"),
+            ("i0300", "threadfence_system"),
+        ]
+    );
+
+    let mut reordered = admission.clone();
+    reordered.variants.swap(0, 1);
+    assert!(expand_threadfence_admission(&reordered).is_err());
+
+    let mut wrong_id = admission.clone();
+    wrong_id.variants[0].abi_id = "i0300".into();
+    assert!(expand_threadfence_admission(&wrong_id).is_err());
+
+    let mut executed = admission.clone();
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_threadfence_admission(&executed).is_err());
+}
+
+#[test]
+fn pinned_threadfences_match_llvm_and_reject_contract_drift() {
+    let records = expand_threadfence_admission(&test_threadfence_admission()).unwrap();
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+
+    for record in &records {
+        let declaration = declarations[record.source_record.as_deref().unwrap()];
+        validate_imported_policy(record, declaration).unwrap();
+        assert_eq!(
+            declaration
+                .selections
+                .iter()
+                .filter(|selection| selection_matches_policy(record, selection).unwrap())
+                .count(),
+            1
+        );
+    }
+
+    let declaration = declarations["int_nvvm_membar_cta"];
+    let mut changed = records[0].clone();
+    changed.memory = "none".into();
+    assert!(validate_imported_policy(&changed, declaration).is_err());
+
+    let mut changed = records[0].clone();
+    changed.convergent = true;
+    assert!(validate_imported_policy(&changed, declaration).is_err());
+
+    let mut changed = records[0].clone();
+    changed.backend_lowerings[0].mechanism = BackendLoweringMechanism::InlinePtx;
+    assert!(validate_imported_policy(&changed, declaration).is_err());
+
+    let mut changed = records[0].clone();
+    changed.minimum_ptx = "2.0".into();
+    assert!(validate_imported_policy(&changed, declaration).is_err());
+}
+
+#[test]
+fn pinned_cluster_sregs_preserve_helpers_and_reject_unused_w_components() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (mut overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    bind_pinned_abi_ids(&repo_root, &mut overlay);
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+    let records = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| {
+            record
+                .source_record
+                .as_deref()
+                .is_some_and(is_cluster_sreg_source)
+        })
+        .collect::<Vec<_>>();
+
+    assert_eq!(records.len(), 14);
+    let actual_abi_ids = records
+        .iter()
+        .map(|record| record.abi_id.clone())
+        .collect::<BTreeSet<_>>();
+    let expected_abi_ids = (263..=276)
+        .map(|id| format!("i{id:04}"))
+        .collect::<BTreeSet<_>>();
+    assert_eq!(actual_abi_ids, expected_abi_ids);
+    for record in &records {
+        let declaration = declarations[record.source_record.as_deref().unwrap()];
+        validate_imported_policy(record, declaration).unwrap();
+        assert!(!declaration.source_record.ends_with("_w"));
+    }
+
+    let compatibility_paths = records
+        .iter()
+        .flat_map(|record| record.compatibility_rust_paths.iter().map(String::as_str))
+        .collect::<BTreeSet<_>>();
+    assert_eq!(
+        compatibility_paths,
+        [
+            "cuda_device::cluster::cluster_ctaidX",
+            "cuda_device::cluster::cluster_ctaidY",
+            "cuda_device::cluster::cluster_ctaidZ",
+            "cuda_device::cluster::cluster_nctaidX",
+            "cuda_device::cluster::cluster_nctaidY",
+            "cuda_device::cluster::cluster_nctaidZ",
+            "cuda_device::cluster::__cluster_grid_dimX",
+            "cuda_device::cluster::__cluster_grid_dimY",
+            "cuda_device::cluster::__cluster_grid_dimZ",
+            "cuda_device::cluster::__cluster_idxX",
+            "cuda_device::cluster::__cluster_idxY",
+            "cuda_device::cluster::__cluster_idxZ",
+        ]
+        .into_iter()
+        .collect()
+    );
+
+    let source = resolve_policy_source(records[0]).unwrap();
+    let error = validate_sreg_policy(
+        records[0],
+        &source,
+        Some(declarations["int_nvvm_read_ptx_sreg_cluster_ctaid_w"]),
+    )
+    .unwrap_err();
+    assert!(error.to_string().contains("unused always-zero"));
+
+    let mut mixed = (*records[0]).clone();
+    mixed.sparse_mma = overlay
+        .intrinsics
+        .iter()
+        .find_map(|record| record.sparse_mma.clone());
+    let source = resolve_policy_source(&mixed).unwrap();
+    let error = validate_sreg_policy(
+        &mixed,
+        &source,
+        Some(declarations[mixed.source_record.as_deref().unwrap()]),
+    )
+    .unwrap_err();
+    assert!(error.to_string().contains("mixes another generated-family"));
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/targets_abi.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/targets_abi.rs
new file mode 100644
index 0000000000..29bb145d4d
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/targets_abi.rs
@@ -0,0 +1,813 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogHalfOpenRange, CatalogHardwareAlternative,
+    CatalogHardwareTarget, CatalogTargetAlternative, CatalogTargetContract,
+    CatalogTargetRequirement, IntrinsicBackend, LdmatrixElement, LdmatrixLayout,
+    LdmatrixMultiplicity, LdmatrixShape, LdmatrixStateSpace, OverlayIntrinsic, PtxVersion,
+    ReduxAdapter, ReduxOperation, ReduxParticipation, TargetContract, TargetSelectorBinding,
+};
+
+use super::fixtures::*;
+use crate::model::ImportedSelection;
+use crate::resolve::abi_ledger::*;
+use crate::resolve::driver::*;
+use crate::resolve::evidence::*;
+use crate::resolve::families::*;
+use crate::resolve::guards::*;
+use crate::resolve::materialize::*;
+use crate::resolve::overlay::*;
+use crate::resolve::policy::*;
+use crate::resolve::targets::*;
+
+#[test]
+fn selected_target_predicates_fail_closed() {
+    let selection = ImportedSelection {
+        source_record: "selection".into(),
+        asm: "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {{$r0, $r1, $r2, $r3}}, [$src];".into(),
+        predicates: vec![
+            "Subtarget->getPTXVersion() >= 65".into(),
+            "Subtarget->getSmVersion() >= 75".into(),
+        ],
+        constraints: Default::default(),
+    };
+
+    let mut too_low_ptx = policy();
+    too_low_ptx.minimum_ptx = "6.4".into();
+    too_low_ptx.minimum_sm = Some("sm_75".into());
+    assert!(
+        validate_selected_target_predicates(&too_low_ptx, &selection)
+            .unwrap_err()
+            .to_string()
+            .contains("minimum PTX")
+    );
+
+    let mut too_low_sm = policy();
+    too_low_sm.minimum_ptx = "6.5".into();
+    too_low_sm.minimum_sm = Some("sm_74".into());
+    assert!(
+        validate_selected_target_predicates(&too_low_sm, &selection)
+            .unwrap_err()
+            .to_string()
+            .contains("minimum SM")
+    );
+
+    let mut unknown = selection;
+    unknown
+        .predicates
+        .push("Subtarget->hasMysteryFeature()".into());
+    assert!(
+        validate_selected_target_predicates(&too_low_sm, &unknown)
+            .unwrap_err()
+            .to_string()
+            .contains("fail closed")
+    );
+}
+
+#[test]
+fn blackwell_ldmatrix_predicate_requires_the_reviewed_exact_target_set() {
+    let mut record = policy();
+    record.family = "ldmatrix".into();
+    record.minimum_ptx = "8.6".into();
+    record.minimum_sm = None;
+    record.targets = BLACKWELL_LDMATRIX_LLVM_TARGETS.into();
+    record.ldmatrix_variant = Some(crate::model::LdmatrixVariant {
+        shape: LdmatrixShape::M16n16,
+        multiplicity: LdmatrixMultiplicity::X1,
+        layout: LdmatrixLayout::Transposed,
+        element: LdmatrixElement::B8,
+        state_space: LdmatrixStateSpace::Shared,
+    });
+    let selection = ImportedSelection {
+        source_record: "selection".into(),
+        asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {{$r0, $r1}}, [$src];".into(),
+        predicates: vec!["Subtarget->hasLdStmatrixBlackwellSupport()".into()],
+        constraints: Default::default(),
+    };
+
+    validate_selected_target_predicates(&record, &selection).unwrap();
+
+    record.targets = "sm_100a|sm_101a".into();
+    assert!(validate_selected_target_predicates(&record, &selection).is_err());
+
+    record.targets = BLACKWELL_LDMATRIX_LLVM_TARGETS.into();
+    let mut conflicting = selection;
+    conflicting
+        .predicates
+        .push("Subtarget->getPTXVersion() >= 86".into());
+    assert!(validate_selected_target_predicates(&record, &conflicting).is_err());
+}
+
+#[test]
+fn f32_redux_predicate_requires_the_reviewed_exact_target_matrix() {
+    let mut record = policy();
+    record.family = "redux".into();
+    record.minimum_ptx = "8.6".into();
+    record.minimum_sm = None;
+    record.targets = REDUX_F32_TARGETS.into();
+    record.redux = Some(crate::model::Redux {
+        operation: ReduxOperation::Fmin,
+        participation: ReduxParticipation::ExecutingLaneNamedAllNamedLanesSameInstructionAndMask,
+        adapter: ReduxAdapter::MaskValueToSourceMemberMask,
+    });
+    let selection = ImportedSelection {
+        source_record: "selection".into(),
+        asm: "redux.sync.min.f32 \t$dst, $src, $mask;".into(),
+        predicates: vec!["Subtarget->hasReduxSyncF32()".into()],
+        constraints: Default::default(),
+    };
+
+    validate_selected_target_predicates(&record, &selection).unwrap();
+
+    record.targets =
+        "sm_100a|sm_100f|sm_103a|sm_103f|sm_110a|sm_110f|sm_120a|sm_120f|sm_121a|sm_121f".into();
+    assert!(validate_selected_target_predicates(&record, &selection).is_err());
+
+    record.targets = REDUX_F32_TARGETS.into();
+    record.minimum_ptx = "8.8".into();
+    assert!(validate_selected_target_predicates(&record, &selection).is_err());
+
+    record.minimum_ptx = "8.6".into();
+    let mut conflicting = selection;
+    conflicting
+        .predicates
+        .push("Subtarget->getPTXVersion() >= 88".into());
+    assert!(validate_selected_target_predicates(&record, &conflicting).is_err());
+}
+
+#[test]
+fn intrinsic_abi_identity_is_stable_and_explicit() {
+    let policy = policy();
+    let declaration = declaration();
+    let resolved = resolve_record(
+        &policy,
+        resolve_policy_source(&policy).unwrap(),
+        Some(&declaration),
+        &evidence(),
+        "test",
+        "LLVM version test",
+        "0123456789abcdef",
+        vec![],
+        1,
+    )
+    .unwrap();
+
+    assert_eq!(resolved.rust.abi_id, "i0001");
+    assert_eq!(
+        resolved.rust.canonical_path,
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
+    );
+    assert_eq!(
+        resolved.rust.public_path,
+        "cuda_intrinsics::sreg::thread_idx_x"
+    );
+    assert_eq!(
+        resolved.rust.compatibility_paths,
+        ["cuda_device::thread::threadIdx_x"]
+    );
+    assert_eq!(
+        resolved.llvm.as_ref().unwrap().properties,
+        [
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,1024>"
+        ]
+    );
+    assert!(resolved.llvm.as_ref().unwrap().result_facts.no_undef);
+    assert_eq!(
+        resolved.llvm.as_ref().unwrap().result_facts.range,
+        Some(CatalogHalfOpenRange {
+            lower: "0".into(),
+            upper_exclusive: "1024".into(),
+        })
+    );
+    assert_eq!(resolved.backend.version, "LLVM version test");
+    assert_eq!(resolved.backend.sha256, "0123456789abcdef");
+}
+
+#[test]
+fn malformed_intrinsic_abi_ids_are_rejected() {
+    for abi_id in ["thread_idx_x", "i1", "x0001", "i00a1"] {
+        let mut record = policy();
+        record.abi_id = abi_id.into();
+        let error = validate_unique_overlay(&[record], 1).unwrap_err();
+        assert!(error.to_string().contains("stable `iNNNN` form"));
+    }
+}
+
+#[test]
+fn ptx_versions_are_parsed_once_and_serialize_compatibly() {
+    for (text, encoded) in [("2.0", 20), ("6.5", 65), ("10.0", 100)] {
+        let version = parse_ptx_version(text, "test").unwrap();
+        assert_eq!(version.encoded(), encoded);
+        assert_eq!(
+            serde_json::to_string(&version).unwrap(),
+            format!("\"{text}\"")
+        );
+        assert_eq!(
+            serde_json::from_str::<PtxVersion>(&format!("\"{text}\"")).unwrap(),
+            version
+        );
+    }
+    for malformed in ["6", "6.05", " 6.5", "06.5", "6.5 "] {
+        assert!(parse_ptx_version(malformed, "test").is_err(), "{malformed}");
+    }
+}
+
+#[test]
+fn hardware_targets_are_parsed_without_losing_suffix_semantics() {
+    let all = policy();
+    assert_eq!(
+        parse_hardware_target(&all).unwrap(),
+        CatalogHardwareTarget::All
+    );
+
+    let mut minimum = policy();
+    minimum.minimum_sm = Some("sm_75".into());
+    assert_eq!(
+        parse_hardware_target(&minimum).unwrap(),
+        CatalogHardwareTarget::AnyOf {
+            alternatives: vec![CatalogHardwareAlternative::MinimumSm { sm: 75 }],
+        }
+    );
+
+    let mut exact = policy();
+    exact.targets = "sm_120a".into();
+    assert_eq!(
+        parse_hardware_target(&exact).unwrap(),
+        CatalogHardwareTarget::AnyOf {
+            alternatives: vec![CatalogHardwareAlternative::ExactArchitecture { sm: 120 }],
+        }
+    );
+
+    let mut family = policy();
+    family.targets = "sm_120f".into();
+    assert_eq!(
+        parse_hardware_target(&family).unwrap(),
+        CatalogHardwareTarget::AnyOf {
+            alternatives: vec![CatalogHardwareAlternative::FamilyTarget { sm: 120 }],
+        }
+    );
+}
+
+#[test]
+fn stage_hardware_shared_parser_preserves_canonical_evidence_language() {
+    for (target, expected) in [
+        ("sm_75", CatalogHardwareAlternative::MinimumSm { sm: 75 }),
+        (
+            "sm_120a",
+            CatalogHardwareAlternative::ExactArchitecture { sm: 120 },
+        ),
+        (
+            "compute_120f",
+            CatalogHardwareAlternative::FamilyTarget { sm: 120 },
+        ),
+    ] {
+        assert_eq!(parse_stage_hardware(target), Some(expected), "{target}");
+    }
+    for target in ["sm_090", "sm_1000"] {
+        assert_eq!(parse_stage_hardware(target), None, "{target}");
+    }
+}
+
+#[test]
+fn reviewed_target_floors_equal_shared_backend_derivation() {
+    for (target, floor) in [
+        ("sm_120a", 87),
+        ("sm_120f", 88),
+        ("sm_121a", 88),
+        ("sm_121f", 88),
+    ] {
+        let hardware = parse_stage_hardware(target).unwrap();
+        assert_eq!(f8f6f4_llvm_ptx_floor(hardware).unwrap(), floor, "{target}");
+    }
+    for (target, floor) in [
+        ("sm_100a", 86),
+        ("sm_100f", 88),
+        ("sm_103a", 88),
+        ("sm_103f", 88),
+        ("sm_110a", 90),
+        ("sm_110f", 90),
+        ("sm_120a", 87),
+        ("sm_120f", 88),
+        ("sm_121a", 88),
+        ("sm_121f", 88),
+    ] {
+        let hardware = parse_stage_hardware(target).unwrap();
+        assert_eq!(
+            blackwell_ldmatrix_llvm_ptx_floor(hardware).unwrap(),
+            floor,
+            "{target}"
+        );
+    }
+}
+
+fn selector(name: &str, value: &str) -> TargetSelectorBinding {
+    TargetSelectorBinding {
+        name: name.into(),
+        value: value.into(),
+    }
+}
+
+fn target_contract(
+    selectors: Vec<TargetSelectorBinding>,
+    alternatives: &[(&str, &str)],
+) -> TargetContract {
+    TargetContract {
+        selectors,
+        alternatives: alternatives
+            .iter()
+            .map(
+                |(target, minimum_ptx)| crate::model::TargetContractAlternative {
+                    target: (*target).into(),
+                    minimum_ptx: (*minimum_ptx).into(),
+                },
+            )
+            .collect(),
+    }
+}
+
+#[test]
+fn target_contracts_keep_selector_specific_ptx_hardware_pairs() {
+    let contracts = [
+        target_contract(
+            vec![selector("kind", "f16")],
+            &[
+                ("sm_100a", "8.6"),
+                ("sm_101a", "8.6"),
+                ("sm_103a", "8.8"),
+                ("sm_110a", "9.0"),
+            ],
+        ),
+        target_contract(
+            vec![selector("kind", "i8")],
+            &[("sm_100a", "8.6"), ("sm_101a", "8.6"), ("sm_110a", "9.0")],
+        ),
+    ];
+    let full_requirement = resolve_target_contracts("tcgen05_mma", &contracts).unwrap();
+    assert_eq!(full_requirement.minimum_ptx.encoded(), 86);
+    let CatalogHardwareTarget::TargetMatrix {
+        contracts: full_contracts,
+    } = &full_requirement.hardware
+    else {
+        panic!("full target contracts must remain a matrix")
+    };
+    assert_eq!(full_contracts.len(), 2);
+    assert_eq!(full_contracts[0].selectors, [selector("kind", "f16")]);
+    assert_eq!(full_contracts[1].selectors, [selector("kind", "i8")]);
+
+    let requirement =
+        resolve_target_contract("tcgen05_mma", &[selector("kind", "i8")], &contracts).unwrap();
+
+    assert_eq!(requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        requirement.hardware,
+        CatalogHardwareTarget::TargetMatrix {
+            contracts: vec![CatalogTargetContract {
+                selectors: vec![selector("kind", "i8")],
+                alternatives: vec![
+                    CatalogTargetAlternative {
+                        minimum_ptx: "8.6".parse().unwrap(),
+                        hardware: CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                    },
+                    CatalogTargetAlternative {
+                        minimum_ptx: "8.6".parse().unwrap(),
+                        hardware: CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+                    },
+                    CatalogTargetAlternative {
+                        minimum_ptx: "9.0".parse().unwrap(),
+                        hardware: CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+                    },
+                ],
+            }],
+        }
+    );
+
+    let mut policy = policy();
+    policy.id = "tcgen05_mma".into();
+    validate_candidate_target(&policy, &requirement, "sm_100a", "+ptx86").unwrap();
+    assert!(validate_candidate_target(&policy, &requirement, "sm_103a", "+ptx88").is_err());
+    assert!(validate_candidate_target(&policy, &requirement, "sm_110a", "+ptx88").is_err());
+    validate_candidate_target(&policy, &requirement, "sm_110a", "+ptx90").unwrap();
+
+    let libnvvm = [target_contract(
+        vec![selector("kind", "i8")],
+        &[("sm_100a", "8.6"), ("sm_110a", "9.0")],
+    )];
+    let libnvvm_requirement =
+        resolve_target_contract("tcgen05_mma", &[selector("kind", "i8")], &libnvvm).unwrap();
+    assert_ne!(requirement, libnvvm_requirement);
+    validate_candidate_target(&policy, &requirement, "sm_101a", "+ptx86").unwrap();
+    assert!(validate_candidate_target(&policy, &libnvvm_requirement, "sm_101a", "+ptx86").is_err());
+}
+
+#[test]
+fn target_contract_selection_and_shape_fail_closed() {
+    resolve_target_contract(
+        "tcgen05_mma",
+        &[selector("kind", "f16")],
+        &[target_contract(
+            vec![selector("kind", "f16")],
+            &[("sm_100a", "8.6"), ("sm_100f", "8.8"), ("sm_103a", "8.8")],
+        )],
+    )
+    .unwrap();
+
+    let valid = target_contract(
+        vec![selector("kind", "f16"), selector("scale_d", "false")],
+        &[("sm_100a", "8.6"), ("sm_103a", "8.8")],
+    );
+    assert!(
+        resolve_target_contract(
+            "tcgen05_mma",
+            &[selector("kind", "i8"), selector("scale_d", "false")],
+            std::slice::from_ref(&valid),
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("exactly one reviewed contract")
+    );
+
+    for invalid in [
+        target_contract(
+            vec![selector("scale_d", "false"), selector("kind", "f16")],
+            &[("sm_100a", "8.6")],
+        ),
+        target_contract(vec![selector("kind", "F16")], &[("sm_100a", "8.6")]),
+        target_contract(vec![selector("kind_", "f16")], &[("sm_100a", "8.6")]),
+        target_contract(
+            vec![selector("kind", "f16")],
+            &[("sm_103a", "8.8"), ("sm_100a", "8.6")],
+        ),
+        target_contract(
+            vec![selector("kind", "f16")],
+            &[("sm_100+", "8.6"), ("sm_103a", "8.8")],
+        ),
+        target_contract(vec![selector("kind", "f16")], &[("sm_100a", "8.60")]),
+    ] {
+        assert!(
+            resolve_target_contract(
+                "tcgen05_mma",
+                &invalid.selectors,
+                std::slice::from_ref(&invalid)
+            )
+            .is_err(),
+            "{invalid:?}"
+        );
+    }
+}
+
+#[test]
+fn legacy_target_requirement_json_is_unchanged() {
+    let requirement = CatalogTargetRequirement {
+        minimum_ptx: "8.6".parse().unwrap(),
+        hardware: CatalogHardwareTarget::AnyOf {
+            alternatives: vec![CatalogHardwareAlternative::ExactArchitecture { sm: 100 }],
+        },
+    };
+    assert_eq!(
+        serde_json::to_value(requirement).unwrap(),
+        serde_json::json!({
+            "minimum_ptx": "8.6",
+            "hardware": {
+                "kind": "any_of",
+                "alternatives": [{ "kind": "exact_architecture", "sm": 100 }]
+            }
+        })
+    );
+}
+
+#[test]
+fn malformed_or_conflicting_hardware_targets_are_rejected() {
+    for malformed in [
+        "sm_120",
+        "sm_120af",
+        "sm_120A",
+        "sm_0120a",
+        "sm_0a",
+        "sm_120+",
+        "compute_120a",
+        "all ",
+    ] {
+        let mut record = policy();
+        record.targets = malformed.into();
+        assert!(parse_hardware_target(&record).is_err(), "{malformed}");
+    }
+
+    let mut suffixed_minimum = policy();
+    suffixed_minimum.minimum_sm = Some("sm_90a".into());
+    assert!(parse_hardware_target(&suffixed_minimum).is_err());
+
+    for target in ["sm_120a", "sm_120f"] {
+        let mut conflicting = policy();
+        conflicting.targets = target.into();
+        conflicting.minimum_sm = Some("sm_120".into());
+        let error = parse_hardware_target(&conflicting).unwrap_err().to_string();
+        assert!(error.contains("cannot be combined"), "{error}");
+    }
+}
+
+#[test]
+fn exact_inline_ptx_routes_can_inherit_exact_or_family_targets() {
+    for target in ["sm_120a", "sm_120f"] {
+        let mut record = policy();
+        record.minimum_ptx = "8.7".into();
+        record.targets = target.into();
+        record.backend_lowerings = [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm]
+            .into_iter()
+            .map(|backend| crate::model::OverlayBackendLowering {
+                backend,
+                mechanism: BackendLoweringMechanism::InlinePtx,
+                evidence_profile: "test".into(),
+                targets: None,
+                minimum_ptx: Some("8.7".into()),
+                minimum_sm: None,
+            })
+            .collect();
+
+        ensure_exact_inline_ptx_backends(
+            &record,
+            [
+                (IntrinsicBackend::LlvmNvptx, "8.7", None),
+                (IntrinsicBackend::LibNvvm, "8.7", None),
+            ],
+            "test",
+        )
+        .unwrap();
+        for lowering in &record.backend_lowerings {
+            assert_eq!(
+                backend_target_requirement(&record, lowering)
+                    .unwrap()
+                    .hardware,
+                parse_hardware_target(&record).unwrap()
+            );
+        }
+
+        record.backend_lowerings[0].minimum_sm = Some("sm_120".into());
+        assert!(
+            ensure_exact_inline_ptx_backends(
+                &record,
+                [
+                    (IntrinsicBackend::LlvmNvptx, "8.7", None),
+                    (IntrinsicBackend::LibNvvm, "8.7", None),
+                ],
+                "test",
+            )
+            .is_err()
+        );
+    }
+}
+
+#[test]
+fn backend_route_target_override_is_exact_and_does_not_inherit_the_record_sm_floor() {
+    let mut record = policy();
+    record.minimum_ptx = "8.6".into();
+    record.minimum_sm = Some("sm_75".into());
+    record.targets = "all".into();
+    let lowering = crate::model::OverlayBackendLowering {
+        backend: IntrinsicBackend::LibNvvm,
+        mechanism: BackendLoweringMechanism::InlinePtx,
+        evidence_profile: "test".into(),
+        targets: Some("sm_100a|sm_120a".into()),
+        minimum_ptx: None,
+        minimum_sm: None,
+    };
+
+    assert_eq!(
+        backend_target_requirement(&record, &lowering).unwrap(),
+        CatalogTargetRequirement {
+            minimum_ptx: parse_ptx_version("8.6", &record.id).unwrap(),
+            hardware: CatalogHardwareTarget::AnyOf {
+                alternatives: vec![
+                    CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                    CatalogHardwareAlternative::ExactArchitecture { sm: 120 },
+                ],
+            },
+        }
+    );
+}
+
+#[test]
+fn abi_ledger_requires_exact_active_identity() {
+    let record = policy();
+    let frozen_entry = ledger_entry(&record);
+    validate_abi_ledger(
+        &overlay_file(vec![record.clone()]),
+        &ledger(vec![frozen_entry.clone()]),
+    )
+    .unwrap();
+
+    let mut reassigned = record.clone();
+    reassigned.id = "different_catalog_id".into();
+    let error = validate_abi_ledger(
+        &overlay_file(vec![reassigned]),
+        &ledger(vec![frozen_entry.clone()]),
+    )
+    .unwrap_err();
+    assert!(error.to_string().contains("catalog ID mismatch"));
+
+    let mut reassigned = record.clone();
+    reassigned.operation_key = "launch.block_index.x".into();
+    let error = validate_abi_ledger(
+        &overlay_file(vec![reassigned]),
+        &ledger(vec![frozen_entry.clone()]),
+    )
+    .unwrap_err();
+    assert!(error.to_string().contains("operation key mismatch"));
+
+    for mutate in [
+        |record: &mut OverlayIntrinsic| record.safe = false,
+        |record: &mut OverlayIntrinsic| record.rust_arguments.push("u32".into()),
+        |record: &mut OverlayIntrinsic| record.rust_result = "u64".into(),
+    ] {
+        let mut changed_signature = record.clone();
+        mutate(&mut changed_signature);
+        let error = validate_abi_ledger(
+            &overlay_file(vec![changed_signature]),
+            &ledger(vec![frozen_entry.clone()]),
+        )
+        .unwrap_err();
+        assert!(error.to_string().contains("raw Rust signature mismatch"));
+    }
+}
+
+#[test]
+fn generated_abi_binding_uses_catalog_identity_not_axis_position() {
+    let mut record = policy();
+    let mut frozen = ledger_entry(&record);
+    frozen.abi_id = "i9001".into();
+    record.abi_id.clear();
+    let mut overlay = overlay_file(vec![record]);
+
+    bind_generated_abi_ids(&mut overlay, &ledger(vec![frozen])).unwrap();
+
+    assert_eq!(overlay.intrinsics[0].abi_id, "i9001");
+}
+
+#[test]
+fn generated_abi_binding_rejects_missing_tombstoned_or_ambiguous_identity() {
+    let record = policy();
+    let mut unbound = record.clone();
+    unbound.abi_id.clear();
+
+    let error = bind_generated_abi_ids(
+        &mut overlay_file(vec![unbound.clone()]),
+        &ledger(vec![ledger_entry(&distinct_policy())]),
+    )
+    .unwrap_err();
+    assert!(error.to_string().contains("has no ABI ledger entry"));
+
+    let mut tombstone = ledger_entry(&record);
+    tombstone.status = "tombstone".into();
+    let error = bind_generated_abi_ids(
+        &mut overlay_file(vec![unbound.clone()]),
+        &ledger(vec![tombstone]),
+    )
+    .unwrap_err();
+    assert!(error.to_string().contains("non-active ABI ledger entry"));
+
+    let first = ledger_entry(&record);
+    let mut duplicate = first.clone();
+    duplicate.abi_id = "i9002".into();
+    let error = bind_generated_abi_ids(
+        &mut overlay_file(vec![unbound]),
+        &ledger(vec![first, duplicate]),
+    )
+    .unwrap_err();
+    assert!(
+        error
+            .to_string()
+            .contains("duplicate ABI ledger catalog ID")
+    );
+}
+
+#[test]
+fn generated_abi_binding_checks_derived_operation_and_raw_signature() {
+    let record = policy();
+    let mut unbound = record.clone();
+    unbound.abi_id.clear();
+
+    let mut wrong_operation = ledger_entry(&record);
+    wrong_operation.operation_key = "launch.block_index.x".into();
+    let error = bind_generated_abi_ids(
+        &mut overlay_file(vec![unbound.clone()]),
+        &ledger(vec![wrong_operation]),
+    )
+    .unwrap_err();
+    assert!(error.to_string().contains("operation key mismatch"));
+
+    let mut wrong_signature = ledger_entry(&record);
+    wrong_signature
+        .raw_rust_signature
+        .arguments
+        .push("u32".into());
+    let error = bind_generated_abi_ids(
+        &mut overlay_file(vec![unbound]),
+        &ledger(vec![wrong_signature]),
+    )
+    .unwrap_err();
+    assert!(error.to_string().contains("raw Rust signature mismatch"));
+}
+
+#[test]
+fn abi_ledger_does_not_freeze_public_or_backend_implementation_details() {
+    let record = policy();
+    let frozen_entry = ledger_entry(&record);
+    let mut evolved = record.clone();
+    evolved.rust_module = "coordinates".into();
+    evolved.rust_name = "thread_x".into();
+    evolved.public_rust_path = "cuda_intrinsics::coordinates::thread_x".into();
+    evolved.llvm_symbol = Some("llvm.nvvm.backend.v2.tid.x".into());
+    evolved.llvm_arguments = vec!["i8".into()];
+    evolved.llvm_results = vec!["i64".into()];
+    evolved.dialect_op_type = "ReadThreadIndexXOpV2".into();
+    evolved.dialect_op_name = "nvvm.read_thread_index_x_v2".into();
+    evolved.lowering = "backend_v2_adapter".into();
+
+    validate_abi_ledger(&overlay_file(vec![evolved]), &ledger(vec![frozen_entry])).unwrap();
+}
+
+#[test]
+fn tombstoned_or_unlisted_abi_ids_cannot_reappear() {
+    let record = policy();
+    let mut tombstone = ledger_entry(&record);
+    tombstone.status = "tombstone".into();
+    let error = validate_abi_ledger(
+        &overlay_file(vec![record.clone()]),
+        &ledger(vec![tombstone]),
+    )
+    .unwrap_err();
+    assert!(error.to_string().contains("cannot reappear"));
+
+    let error = validate_abi_ledger(&overlay_file(vec![record]), &ledger(vec![])).unwrap_err();
+    assert!(error.to_string().contains("contains no entries"));
+}
+
+#[test]
+fn every_active_ledger_entry_requires_an_overlay_record() {
+    let record = policy();
+    let error = validate_abi_ledger(&overlay_file(vec![]), &ledger(vec![ledger_entry(&record)]))
+        .unwrap_err();
+    assert!(error.to_string().contains("has no overlay record"));
+}
+
+#[test]
+fn candidate_targets_are_canonical_and_satisfy_every_floor() {
+    let policy = policy();
+    let requirement = CatalogTargetRequirement {
+        minimum_ptx: "7.0".parse().unwrap(),
+        hardware: CatalogHardwareTarget::AnyOf {
+            alternatives: vec![CatalogHardwareAlternative::MinimumSm { sm: 80 }],
+        },
+    };
+    validate_candidate_target(&policy, &requirement, "sm_80", "+ptx70").unwrap();
+    validate_candidate_target(&policy, &requirement, "sm_90a", "+ptx86").unwrap();
+    assert!(
+        validate_candidate_target(&policy, &requirement, "sm_75", "+ptx70")
+            .unwrap_err()
+            .to_string()
+            .contains("hardware requirement")
+    );
+    assert!(
+        validate_candidate_target(&policy, &requirement, "sm_80", "+ptx69")
+            .unwrap_err()
+            .to_string()
+            .contains("PTX floor")
+    );
+    for malformed in ["compute_80", "sm_080", "sm_80x"] {
+        assert!(
+            validate_candidate_target(&policy, &requirement, malformed, "+ptx70").is_err(),
+            "{malformed}"
+        );
+    }
+    for malformed in ["ptx70", "+ptx7", "+ptx070"] {
+        assert!(
+            validate_candidate_target(&policy, &requirement, "sm_80", malformed).is_err(),
+            "{malformed}"
+        );
+    }
+
+    let exact = CatalogTargetRequirement {
+        minimum_ptx: "8.7".parse().unwrap(),
+        hardware: CatalogHardwareTarget::AnyOf {
+            alternatives: vec![CatalogHardwareAlternative::ExactArchitecture { sm: 120 }],
+        },
+    };
+    validate_candidate_target(&policy, &exact, "sm_120a", "+ptx87").unwrap();
+    assert!(validate_candidate_target(&policy, &exact, "sm_120a", "+ptx86").is_err());
+    assert!(validate_candidate_target(&policy, &exact, "sm_120", "+ptx87").is_err());
+    assert!(validate_candidate_target(&policy, &exact, "sm_120f", "+ptx87").is_err());
+
+    let family = CatalogTargetRequirement {
+        minimum_ptx: "8.7".parse().unwrap(),
+        hardware: CatalogHardwareTarget::AnyOf {
+            alternatives: vec![CatalogHardwareAlternative::FamilyTarget { sm: 120 }],
+        },
+    };
+    validate_candidate_target(&policy, &family, "sm_120f", "+ptx87").unwrap();
+    assert!(validate_candidate_target(&policy, &family, "sm_120a", "+ptx87").is_err());
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs
new file mode 100644
index 0000000000..90766e5124
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs
@@ -0,0 +1,1366 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    CatalogHardwareAlternative, CatalogHardwareTarget, ImportedFile, OverlayIntrinsic,
+    OverlayShardFile, RuntimeValidation, Tcgen05Adapter, Tcgen05MmaBUsage,
+    Tcgen05MmaFixedSelectors, Tcgen05MmaForm, Tcgen05MmaKind, Tcgen05MmaSelectorLayout,
+    Tcgen05Operation, Tcgen05SourceContract,
+};
+use crate::ptx::OperandPattern;
+use crate::util::read_json;
+use std::collections::{BTreeMap, BTreeSet};
+use std::path::Path;
+
+use super::fixtures::*;
+use crate::resolve::families::*;
+use crate::resolve::guards::*;
+use crate::resolve::overlay::*;
+use crate::resolve::targets::*;
+
+#[test]
+fn compact_tcgen05_admission_matches_llvm_and_fails_closed() {
+    let records = expand_tcgen05_admission(&test_tcgen05_admission()).unwrap();
+    assert_eq!(records.len(), 27);
+    assert_eq!(
+        records
+            .iter()
+            .map(|record| (record.abi_id.as_str(), record.id.as_str()))
+            .collect::<Vec<_>>(),
+        [
+            ("i0343", "tcgen05_alloc"),
+            ("i0344", "tcgen05_dealloc"),
+            ("i0345", "tcgen05_relinquish_alloc_permit"),
+            ("i0346", "tcgen05_fence_before_thread_sync"),
+            ("i0347", "tcgen05_fence_after_thread_sync"),
+            ("i0348", "tcgen05_commit"),
+            ("i0349", "tcgen05_commit_shared_cluster"),
+            ("i0350", "tcgen05_mma_ws_f16"),
+            ("i0351", "tcgen05_mma_f16"),
+            ("i0352", "tcgen05_mma_ws_bf16"),
+            ("i0353", "tcgen05_mma_ws_tf32"),
+            ("i0354", "tcgen05_cp_smem_to_tmem"),
+            ("i0355", "tcgen05_ld_16x256b_x8_pure"),
+            ("i0356", "tcgen05_ld_16x256b_pure"),
+            ("i0357", "tcgen05_load_wait"),
+            ("i0358", "tcgen05_store_wait"),
+            ("i0359", "tcgen05_alloc_cg2"),
+            ("i0360", "tcgen05_dealloc_cg2"),
+            ("i0361", "tcgen05_relinquish_alloc_permit_cg2"),
+            ("i0362", "tcgen05_mma_f16_cg2"),
+            ("i0363", "tcgen05_commit_cg2"),
+            ("i0364", "tcgen05_commit_shared_cluster_cg2"),
+            ("i0365", "tcgen05_commit_multicast_cg2"),
+            ("i0366", "tcgen05_cp_smem_to_tmem_cg2"),
+            ("i0760", "tcgen05_commit_multicast"),
+            ("i0761", "tcgen05_shift_down"),
+            ("i0762", "tcgen05_shift_down_cg2"),
+        ]
+    );
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+    for record in &records {
+        let declaration = declarations[record.source_record.as_deref().unwrap()];
+        validate_imported_policy(record, declaration).unwrap();
+        assert_tcgen05_backend_target_split(record);
+        assert_eq!(
+            record.execution_scope,
+            record.tcgen05.as_ref().unwrap().operation.execution_scope()
+        );
+    }
+
+    let bf16 = records
+        .iter()
+        .find(|record| record.id == "tcgen05_mma_ws_bf16")
+        .unwrap();
+    assert!(bf16.expected_ptx.modifiers.contains(&"kind::f16".into()));
+    assert!(!bf16.expected_ptx.modifiers.contains(&"kind::bf16".into()));
+    assert_eq!(
+        bf16.tcgen05.as_ref().unwrap().source_contract,
+        Tcgen05SourceContract::TablegenSelectionChangesPtx
+    );
+
+    let mma_f16 = records
+        .iter()
+        .find(|record| record.id == "tcgen05_mma_f16")
+        .unwrap();
+    assert!(mma_f16.expected_ptx.matches(
+            "tcgen05.mma.cta_group::1.kind::f16 [%r1], %rd1, %rd2, %r2, {%z, %z, %z, %z}, %enable_pred;"
+        ).unwrap());
+    assert!(!mma_f16.expected_ptx.matches(
+            "tcgen05.mma.cta_group::1.kind::f16 [%r1], %rd1, %rd2, %r2, {%clock64, %z, %z, %z}, %enable_pred;"
+        ).unwrap());
+    assert!(!mma_f16.expected_ptx.matches(
+            "tcgen05.mma.cta_group::1.kind::f16 [%r1], %rd1, %rd2, %r2, {%z, %z, %z, %z}, %other_pred;"
+        ).unwrap());
+
+    let mma_f16_cg2 = records
+        .iter()
+        .find(|record| record.id == "tcgen05_mma_f16_cg2")
+        .unwrap();
+    assert!(mma_f16_cg2.expected_ptx.matches(
+            "tcgen05.mma.cta_group::2.kind::f16 [%r1], %rd1, %rd2, %r2, {%z, %z, %z, %z, %z, %z, %z, %z}, %enable_pred;"
+        ).unwrap());
+    assert!(
+        !records
+            .iter()
+            .any(|record| { record.rust_name == "tcgen05_mma_ws_f16_with_collector" })
+    );
+    assert_eq!(
+        parse_hardware_target(&records[0]).unwrap(),
+        CatalogHardwareTarget::AnyOf {
+            alternatives: vec![
+                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+            ],
+        }
+    );
+
+    let legacy_records =
+        expand_tcgen05_admission(&without_tcgen05_control(test_tcgen05_admission())).unwrap();
+    assert_eq!(legacy_records.len(), 24);
+    assert!(legacy_records.iter().all(|record| {
+        record
+            .backend_lowerings
+            .iter()
+            .map(|lowering| lowering.evidence_profile.as_str())
+            .eq(["llvm-tcgen05-test", "libnvvm-tcgen05-test"])
+    }));
+
+    let multicast = records
+        .iter()
+        .find(|record| record.id == "tcgen05_commit_multicast")
+        .unwrap();
+    assert_eq!(multicast.abi_id, "i0760");
+    assert_eq!(multicast.rust_arguments, ["*mut u64", "u16"]);
+    assert_eq!(multicast.llvm_arguments, ["shared_ptr", "i16"]);
+    assert_eq!(multicast.execution_scope, "thread");
+    assert_eq!(
+        multicast.backend_lowerings[0].evidence_profile,
+        "llvm-tcgen05-control-test"
+    );
+    assert_eq!(
+        multicast.backend_lowerings[1].evidence_profile,
+        "libnvvm-tcgen05-control-test"
+    );
+
+    for (id, group) in [
+        ("tcgen05_shift_down", "cta_group::1"),
+        ("tcgen05_shift_down_cg2", "cta_group::2"),
+    ] {
+        let shift = records.iter().find(|record| record.id == id).unwrap();
+        assert_eq!(shift.rust_arguments, ["u32"]);
+        assert_eq!(shift.llvm_arguments, ["tmem_ptr"]);
+        assert_eq!(shift.execution_scope, "thread");
+        assert_eq!(shift.memory, "read_write");
+        assert_eq!(shift.expected_ptx.modifiers, ["shift", group, "down"]);
+        assert_eq!(shift.expected_ptx.operands, [OperandPattern::Address]);
+    }
+
+    let mut missing = test_tcgen05_admission();
+    missing.variants.pop();
+    assert!(expand_tcgen05_admission(&missing).is_err());
+
+    let mut reordered = test_tcgen05_admission();
+    reordered.variants.swap(0, 1);
+    assert!(expand_tcgen05_admission(&reordered).is_err());
+
+    let mut wrong_abi = test_tcgen05_admission();
+    wrong_abi.variants[0].abi_id = "i9999".into();
+    assert!(expand_tcgen05_admission(&wrong_abi).is_err());
+
+    let mut executed = test_tcgen05_admission();
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_tcgen05_admission(&executed).is_err());
+
+    let mut missing_control_evidence = test_tcgen05_admission();
+    missing_control_evidence.control_llvm_evidence_profile = None;
+    assert!(expand_tcgen05_admission(&missing_control_evidence).is_err());
+
+    let mut partial_control = without_tcgen05_control(test_tcgen05_admission());
+    partial_control
+        .variants
+        .push(test_tcgen05_admission().variants[24].clone());
+    assert!(expand_tcgen05_admission(&partial_control).is_err());
+
+    let shift = records
+        .iter()
+        .find(|record| record.id == "tcgen05_shift_down")
+        .unwrap();
+    let mut wrong_shift_declaration = declarations[shift.source_record.as_deref().unwrap()].clone();
+    wrong_shift_declaration.selections[0].predicates =
+        vec!["Subtarget->hasTcgen05InstSupport()".into()];
+    assert!(validate_imported_policy(shift, &wrong_shift_declaration).is_err());
+
+    let declaration = declarations[records[0].source_record.as_deref().unwrap()];
+    let mut wrong_adapter = records[0].clone();
+    wrong_adapter.tcgen05.as_mut().unwrap().adapter = Tcgen05Adapter::NoOperands;
+    assert!(validate_imported_policy(&wrong_adapter, declaration).is_err());
+
+    let mut changed_declaration = declaration.clone();
+    changed_declaration.properties.pop();
+    assert!(validate_imported_policy(&records[0], &changed_declaration).is_err());
+
+    let mut broadened_libnvvm = records[0].clone();
+    broadened_libnvvm.backend_lowerings[1].targets = None;
+    assert!(validate_imported_policy(&broadened_libnvvm, declaration).is_err());
+
+    let mut wrong_alloc_scope = records[0].clone();
+    wrong_alloc_scope.execution_scope = "thread".into();
+    assert!(validate_imported_policy(&wrong_alloc_scope, declaration).is_err());
+
+    let pure_load = &records[12];
+    let pure_declaration = declarations[pure_load.source_record.as_deref().unwrap()];
+    let mut wrong_pure_load_scope = pure_load.clone();
+    wrong_pure_load_scope.execution_scope = "thread".into();
+    assert!(validate_imported_policy(&wrong_pure_load_scope, pure_declaration).is_err());
+}
+
+#[test]
+fn compact_tcgen05_mma_admission_closes_sources_selectors_and_targets() {
+    let records = expand_tcgen05_admission(&test_tcgen05_mma_admission()).unwrap();
+    assert_eq!(records.len(), 51);
+    let mma = &records[27..];
+    assert_eq!(mma.len(), 24);
+    assert_eq!(
+        mma.iter()
+            .map(|record| (record.abi_id.as_str(), record.id.as_str()))
+            .collect::<Vec<_>>(),
+        [
+            ("i0763", "tcgen05_mma_shared"),
+            ("i0764", "tcgen05_mma_tensor"),
+            ("i0765", "tcgen05_mma_tensor_ashift"),
+            ("i0766", "tcgen05_mma_sp_shared"),
+            ("i0767", "tcgen05_mma_sp_tensor"),
+            ("i0768", "tcgen05_mma_sp_tensor_ashift"),
+            ("i0769", "tcgen05_mma_ws_shared"),
+            ("i0770", "tcgen05_mma_ws_shared_zero_col_mask"),
+            ("i0771", "tcgen05_mma_ws_sp_shared"),
+            ("i0772", "tcgen05_mma_ws_sp_shared_zero_col_mask"),
+            ("i0773", "tcgen05_mma_ws_sp_tensor"),
+            ("i0774", "tcgen05_mma_ws_sp_tensor_zero_col_mask"),
+            ("i0775", "tcgen05_mma_ws_tensor"),
+            ("i0776", "tcgen05_mma_ws_tensor_zero_col_mask"),
+            ("i0777", "tcgen05_mma_ws_e4m3"),
+            ("i0778", "tcgen05_mma_ws_e5m2"),
+            ("i0779", "tcgen05_mma_ws_e2m3"),
+            ("i0780", "tcgen05_mma_ws_e3m2"),
+            ("i0781", "tcgen05_mma_ws_e2m1"),
+            ("i1011", "tcgen05_mma_e4m3"),
+            ("i1012", "tcgen05_mma_e5m2"),
+            ("i1013", "tcgen05_mma_e2m3"),
+            ("i1014", "tcgen05_mma_e3m2"),
+            ("i1015", "tcgen05_mma_e2m1"),
+        ]
+    );
+    assert!(mma.iter().all(|record| {
+        record.dialect_op_type == TCGEN05_MMA_DIALECT_OP_TYPE
+            && record.dialect_op_name == TCGEN05_MMA_DIALECT_OP_NAME
+    }));
+    assert_eq!(
+        [
+            Tcgen05MmaBUsage::Discard,
+            Tcgen05MmaBUsage::LastUse,
+            Tcgen05MmaBUsage::Fill,
+            Tcgen05MmaBUsage::Use,
+        ]
+        .map(Tcgen05MmaBUsage::selector_value),
+        [0, 1, 2, 3]
+    );
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+    for record in mma {
+        let declaration = declarations[record.source_record.as_deref().unwrap()];
+        validate_imported_policy(record, declaration).unwrap();
+        assert_eq!(record.memory, "read_write");
+        assert!(record.convergent);
+        assert_eq!(record.execution_scope, "thread");
+        assert!(!record.safe);
+        assert_eq!(
+            record
+                .expected_ptx
+                .operands
+                .iter()
+                .filter(|operand| {
+                    **operand
+                        == (OperandPattern::Exact {
+                            value: "%enable_pred".into(),
+                        })
+                })
+                .count(),
+            1
+        );
+    }
+
+    let dense = &mma[0];
+    assert!(dense.expected_ptx.matches(
+            "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, %enable_pred;"
+        ).unwrap());
+    assert!(!dense.expected_ptx.matches(
+            "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, %clock64;"
+        ).unwrap());
+    assert!(mma[4].expected_ptx.matches(
+            "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [%r1], [%r2], %rd1, [%r3], %r4, %enable_pred;"
+        ).unwrap());
+    assert!(mma[7].expected_ptx.matches(
+            "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%r1], %rd1, %rd2, %r2, %enable_pred, %rd3;"
+        ).unwrap());
+    assert!(mma[14].expected_ptx.matches(
+            "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%r1], [%r2], %rd1, %r3, %enable_pred;"
+        ).unwrap());
+    assert!(mma[19].expected_ptx.matches(
+            "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [%r1], %rd1, %rd2, %r2, %enable_pred;"
+        ).unwrap());
+
+    let canonical = &mma[..14];
+    assert_eq!(
+        canonical
+            .iter()
+            .map(|record| record.source_record.as_deref().unwrap())
+            .collect::<BTreeSet<_>>()
+            .len(),
+        14
+    );
+    let selected_count = |record: &OverlayIntrinsic| {
+        declarations[record.source_record.as_deref().unwrap()]
+            .selections
+            .iter()
+            .filter(|selection| selection_matches_policy(record, selection).unwrap())
+            .count()
+    };
+    let newly_matched = canonical
+        .iter()
+        .filter(|record| record.id != "tcgen05_mma_ws_tensor")
+        .map(selected_count)
+        .sum::<usize>();
+    assert_eq!(newly_matched, 608);
+    assert_eq!(selected_count(&canonical[12]), 64);
+    assert_eq!(canonical.iter().map(selected_count).sum::<usize>(), 672);
+    assert_eq!(mma[14..].iter().map(selected_count).sum::<usize>(), 10);
+    assert_eq!(
+        [2, 5]
+            .into_iter()
+            .map(|index| {
+                declarations[canonical[index].source_record.as_deref().unwrap()]
+                    .selections
+                    .len()
+                    - selected_count(&canonical[index])
+            })
+            .sum::<usize>(),
+        32
+    );
+
+    for record in canonical {
+        assert_eq!(
+            record.compatibility_rust_paths,
+            [format!("cuda_device::tcgen05::__{}", record.id)]
+        );
+        assert_eq!(
+            &record.rust_arguments[record.rust_arguments.len() - 3..],
+            ["u32", "u32", "u32"]
+        );
+        let contract = record.tcgen05.as_ref().unwrap().mma.as_ref().unwrap();
+        let CatalogHardwareTarget::TargetMatrix { contracts } = &contract.llvm_target.hardware
+        else {
+            panic!("generic LLVM tcgen05 MMA target must be a matrix")
+        };
+        assert_eq!(contracts.len(), 4);
+        assert_eq!(
+            contracts
+                .iter()
+                .map(|contract| contract.alternatives.len())
+                .collect::<Vec<_>>(),
+            [8, 8, 3, 8]
+        );
+        let CatalogHardwareTarget::TargetMatrix { contracts } = &contract.libnvvm_target.hardware
+        else {
+            panic!("generic libNVVM tcgen05 MMA target must be a matrix")
+        };
+        assert_eq!(contracts.len(), 4);
+        assert_eq!(
+            contracts
+                .iter()
+                .map(|contract| contract.alternatives.len())
+                .collect::<Vec<_>>(),
+            [6, 6, 2, 6]
+        );
+    }
+    for record in &mma[14..19] {
+        assert_eq!(
+            record.compatibility_rust_paths,
+            [format!("cuda_device::tcgen05::{}", record.id)]
+        );
+        assert_eq!(
+            record.rust_arguments,
+            ["u32", "u32", "u64", "u64", "u32", "bool"]
+        );
+        assert_eq!(record.dialect_operands, ["i32", "i32", "i64", "i32", "i1"]);
+        let contract = record.tcgen05.as_ref().unwrap().mma.as_ref().unwrap();
+        assert_eq!(
+            contract.fixed_selectors,
+            Some(Tcgen05MmaFixedSelectors {
+                kind: Tcgen05MmaKind::F8f6f4,
+                b_buffer: 0,
+                b_usage: Tcgen05MmaBUsage::Discard,
+            })
+        );
+        let CatalogHardwareTarget::TargetMatrix { contracts } = &contract.llvm_target.hardware
+        else {
+            panic!("fixed LLVM tcgen05 MMA target must be a matrix")
+        };
+        assert_eq!(contracts.len(), 1);
+        assert_eq!(contracts[0].selectors[0].value, "f8f6f4");
+    }
+    for record in &mma[19..] {
+        assert_eq!(
+            record.compatibility_rust_paths,
+            [format!("cuda_device::tcgen05::{}", record.id)]
+        );
+        assert_eq!(record.rust_arguments, ["u32", "u64", "u64", "u32", "bool"]);
+        assert_eq!(record.dialect_operands, ["i32", "i64", "i64", "i32", "i1"]);
+        let contract = record.tcgen05.as_ref().unwrap().mma.as_ref().unwrap();
+        assert_eq!(contract.form, Tcgen05MmaForm::Shared);
+        assert_eq!(
+            contract.fixed_selectors,
+            Some(Tcgen05MmaFixedSelectors {
+                kind: Tcgen05MmaKind::F8f6f4,
+                b_buffer: 0,
+                b_usage: Tcgen05MmaBUsage::Discard,
+            })
+        );
+        assert_eq!(
+            record.tcgen05.as_ref().unwrap().adapter,
+            Tcgen05Adapter::MmaDirectSelectors
+        );
+        let CatalogHardwareTarget::TargetMatrix { contracts } = &contract.llvm_target.hardware
+        else {
+            panic!("fixed LLVM tcgen05 MMA target must be a matrix")
+        };
+        assert_eq!(contracts.len(), 1);
+        assert_eq!(contracts[0].selectors[0].value, "f8f6f4");
+    }
+
+    for legacy in [
+        "tcgen05_mma_ws_f16",
+        "tcgen05_mma_ws_bf16",
+        "tcgen05_mma_ws_tf32",
+    ] {
+        let old = &records[..27]
+            .iter()
+            .find(|record| record.id == legacy)
+            .unwrap();
+        assert!(old.tcgen05.as_ref().unwrap().mma.is_none());
+        assert!(old.abi_id.starts_with("i035"));
+        assert_eq!(
+            old.expected_ptx.operands.last(),
+            Some(&OperandPattern::Exact {
+                value: "%enable_pred".into(),
+            })
+        );
+    }
+    let legacy_f16 = records
+        .iter()
+        .find(|record| record.id == "tcgen05_mma_ws_f16")
+        .unwrap();
+    assert!(
+        legacy_f16
+            .expected_ptx
+            .matches("tcgen05.mma.ws.cta_group::1.kind::f16 [%r1], [%r2], %rd1, %r3, %enable_pred;")
+            .unwrap()
+    );
+    assert!(
+        !legacy_f16
+            .expected_ptx
+            .matches("tcgen05.mma.ws.cta_group::1.kind::f16 [%r1], [%r2], %rd1, %r3, %other_pred;")
+            .unwrap()
+    );
+}
+
+#[test]
+fn compact_tcgen05_mma_admission_fails_closed_on_drift() {
+    let mut missing = test_tcgen05_mma_admission();
+    missing.mma_variants.pop();
+    assert!(expand_tcgen05_admission(&missing).is_err());
+
+    let mut reordered = test_tcgen05_mma_admission();
+    reordered.mma_variants.swap(0, 1);
+    assert!(expand_tcgen05_admission(&reordered).is_err());
+
+    let mut non_contiguous_abi = test_tcgen05_mma_admission();
+    non_contiguous_abi.mma_variants[0].abi_id = "i9999".into();
+    let records = expand_tcgen05_admission(&non_contiguous_abi).unwrap();
+    assert!(records.iter().any(|record| record.abi_id == "i9999"));
+
+    let mut missing_target = test_tcgen05_mma_admission();
+    missing_target.mma_llvm_target_contracts[0]
+        .alternatives
+        .pop();
+    assert!(expand_tcgen05_admission(&missing_target).is_err());
+
+    let mut broadened_i8 = test_tcgen05_mma_admission();
+    broadened_i8.mma_libnvvm_target_contracts[2]
+        .alternatives
+        .insert(
+            1,
+            crate::model::TargetContractAlternative {
+                target: "sm_103a".into(),
+                minimum_ptx: "8.8".into(),
+            },
+        );
+    assert!(expand_tcgen05_admission(&broadened_i8).is_err());
+
+    let records = expand_tcgen05_admission(&test_tcgen05_mma_admission()).unwrap();
+    let record = records
+        .iter()
+        .find(|record| record.id == "tcgen05_mma_tensor_ashift")
+        .unwrap();
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declaration = imported
+        .intrinsics
+        .iter()
+        .find(|declaration| {
+            Some(declaration.source_record.as_str()) == record.source_record.as_deref()
+        })
+        .unwrap();
+
+    let mut wrong_layout = record.clone();
+    let mma = wrong_layout.tcgen05.as_mut().unwrap().mma.as_mut().unwrap();
+    mma.selector_layout = Tcgen05MmaSelectorLayout::Base {
+        kind_argument: 6,
+        cta_group_argument: 5,
+        collector_a_argument: 7,
+        collector_a_upper_exclusive: 2,
+    };
+    assert!(validate_imported_policy(&wrong_layout, declaration).is_err());
+
+    let mut wrong_properties = declaration.clone();
+    wrong_properties.properties.pop();
+    assert!(validate_imported_policy(record, &wrong_properties).is_err());
+
+    let mut wrong_range = declaration.clone();
+    let range = wrong_range
+        .properties
+        .iter_mut()
+        .find(|property| property.as_str() == "Range<arg7,0,2>")
+        .unwrap();
+    *range = "Range<arg7,0,4>".into();
+    assert!(validate_imported_policy(record, &wrong_range).is_err());
+
+    let mut wrong_predicate = declaration.clone();
+    wrong_predicate.selections[0].predicates = vec!["hasSM100a".into()];
+    assert!(validate_imported_policy(record, &wrong_predicate).is_err());
+
+    let mut wrong_memory = record.clone();
+    wrong_memory.memory = "write".into();
+    assert!(validate_imported_policy(&wrong_memory, declaration).is_err());
+
+    let mut wrong_convergence = record.clone();
+    wrong_convergence.convergent = false;
+    assert!(validate_imported_policy(&wrong_convergence, declaration).is_err());
+
+    let mut split_dialect_op = record.clone();
+    split_dialect_op.dialect_op_type = "Tcgen05MmaTensorAshiftOp".into();
+    split_dialect_op.dialect_op_name = "nvvm.tcgen05_mma_tensor_ashift".into();
+    assert!(validate_imported_policy(&split_dialect_op, declaration).is_err());
+}
+
+#[test]
+fn compact_tcgen05_copy_admission_matches_all_llvm_records_and_fails_closed() {
+    let records = expand_tcgen05_admission(&test_tcgen05_cp_admission()).unwrap();
+    assert_eq!(records.len(), 61);
+    let copies = &records[27..];
+    assert_eq!(copies.len(), 34);
+    assert_eq!(
+        (copies[0].abi_id.as_str(), copies[0].id.as_str()),
+        ("i0578", "tcgen05_cp_128x128b_b4x16_p64")
+    );
+    assert_eq!(
+        (copies[33].abi_id.as_str(), copies[33].id.as_str()),
+        ("i0611", "tcgen05_cp_64x128b_warpx2_02_13_cg2")
+    );
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+    for record in copies {
+        let declaration = declarations[record.source_record.as_deref().unwrap()];
+        validate_imported_policy(record, declaration).unwrap();
+        assert_tcgen05_backend_target_split(record);
+        assert_eq!(record.rust_arguments, ["u32", "u64"]);
+        assert_eq!(record.rust_result, "()");
+        assert!(!record.safe);
+        assert!(record.convergent);
+        assert_eq!(record.memory, "read_write");
+        assert_eq!(record.targets, TCGEN05_LLVM_TARGETS);
+    }
+
+    let packed = copies
+        .iter()
+        .find(|record| record.id == "tcgen05_cp_128x128b_b4x16_p64")
+        .unwrap();
+    assert_eq!(
+        packed.expected_ptx.modifiers,
+        ["cp", "cta_group::1", "128x128b", "b8x16", "b4x16_p64"]
+    );
+    let warpx4 = copies
+        .iter()
+        .find(|record| record.id == "tcgen05_cp_32x128b_warpx4")
+        .unwrap();
+    assert_eq!(
+        warpx4.expected_ptx.modifiers,
+        ["cp", "cta_group::1", "32x128b", "warpx4"]
+    );
+    let pair_01_23 = copies
+        .iter()
+        .find(|record| record.id == "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2")
+        .unwrap();
+    assert_eq!(
+        pair_01_23.expected_ptx.modifiers,
+        [
+            "cp",
+            "cta_group::2",
+            "64x128b",
+            "warpx2::01_23",
+            "b8x16",
+            "b6x16_p32"
+        ]
+    );
+    let pair_02_13 = copies
+        .iter()
+        .find(|record| record.id == "tcgen05_cp_64x128b_warpx2_02_13")
+        .unwrap();
+    assert_eq!(
+        pair_02_13.expected_ptx.modifiers,
+        ["cp", "cta_group::1", "64x128b", "warpx2::02_13"]
+    );
+
+    let mut missing = test_tcgen05_cp_admission();
+    missing.cp_variants.pop();
+    assert!(expand_tcgen05_admission(&missing).is_err());
+
+    let mut reordered = test_tcgen05_cp_admission();
+    reordered.cp_variants.swap(0, 1);
+    assert!(expand_tcgen05_admission(&reordered).is_err());
+
+    let mut non_contiguous_abi = test_tcgen05_cp_admission();
+    non_contiguous_abi.cp_variants[0].abi_id = "i9999".into();
+    let records = expand_tcgen05_admission(&non_contiguous_abi).unwrap();
+    assert!(records.iter().any(|record| record.abi_id == "i9999"));
+
+    let mut missing_evidence = test_tcgen05_cp_admission();
+    missing_evidence.cp_llvm_evidence_profile = None;
+    assert!(expand_tcgen05_admission(&missing_evidence).is_err());
+
+    let declaration = declarations[copies[0].source_record.as_deref().unwrap()];
+    let mut wrong_spelling = copies[0].clone();
+    wrong_spelling.expected_ptx.modifiers.remove(3);
+    assert!(validate_imported_policy(&wrong_spelling, declaration).is_err());
+
+    let mut broadened_libnvvm = copies[0].clone();
+    broadened_libnvvm.backend_lowerings[1].targets = None;
+    assert!(validate_imported_policy(&broadened_libnvvm, declaration).is_err());
+}
+
+#[test]
+fn compact_tcgen05_load_admission_matches_all_llvm_records_and_fails_closed() {
+    let records = expand_tcgen05_admission(&test_tcgen05_ld_admission()).unwrap();
+    assert_eq!(records.len(), 119);
+    let loads = &records[61..];
+    assert_eq!(loads.len(), 58);
+    assert_eq!(
+        (loads[0].abi_id.as_str(), loads[0].id.as_str()),
+        ("i0612", "tcgen05_ld_16x64b_x1_raw")
+    );
+    assert_eq!(
+        (loads[1].abi_id.as_str(), loads[1].id.as_str()),
+        ("i0613", "tcgen05_ld_16x64b_x1_pack16")
+    );
+    assert_eq!(
+        (loads[57].abi_id.as_str(), loads[57].id.as_str()),
+        ("i0669", "tcgen05_ld_32x32b_x128_pack16")
+    );
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+    let mut source_counts = BTreeMap::new();
+    for record in loads {
+        let source_record = record.source_record.as_deref().unwrap();
+        *source_counts.entry(source_record).or_insert(0) += 1;
+        let declaration = declarations[source_record];
+        validate_imported_policy(record, declaration).unwrap();
+        assert_tcgen05_backend_target_split(record);
+        assert_eq!(record.rust_arguments, ["u32"]);
+        assert!(record.must_use);
+        assert!(!record.safe);
+        assert!(!record.pure);
+        assert_eq!(record.memory, "read");
+        assert!(record.convergent);
+        assert_eq!(record.execution_scope, "warp");
+        assert!(
+            !record
+                .rust_arguments
+                .iter()
+                .any(|argument| argument == "bool")
+        );
+        assert_eq!(record.dialect_operands, ["i32"]);
+        assert_eq!(record.llvm_arguments, ["tmem_ptr", "i1"]);
+        assert!(declaration.selections.is_empty());
+    }
+    assert_eq!(source_counts.len(), 29);
+    assert!(source_counts.values().all(|count| *count == 2));
+    assert_eq!(
+        records
+            .iter()
+            .filter(|record| {
+                record.source_record.as_deref() == Some("int_nvvm_tcgen05_ld_16x256b_x1")
+            })
+            .count(),
+        3
+    );
+    assert_eq!(
+        records
+            .iter()
+            .filter(|record| {
+                record.source_record.as_deref() == Some("int_nvvm_tcgen05_ld_16x256b_x8")
+            })
+            .count(),
+        3
+    );
+    validate_unique_overlay(&records, 1).unwrap();
+
+    let scalar_raw = &loads[0];
+    assert_eq!(scalar_raw.rust_result, "u32");
+    assert_eq!(scalar_raw.dialect_results, ["i32"]);
+    assert_eq!(scalar_raw.llvm_results, ["i32"]);
+    assert_eq!(
+        scalar_raw.expected_ptx.modifiers,
+        ["ld", "sync", "aligned", "16x64b", "x1", "b32"]
+    );
+    assert_eq!(
+        scalar_raw.expected_ptx.operands,
+        [
+            OperandPattern::RegisterList { length: 1 },
+            OperandPattern::Address,
+        ]
+    );
+    assert!(
+        scalar_raw
+            .expected_ptx
+            .matches("tcgen05.ld.sync.aligned.16x64b.x1.b32 {%r1}, [%r2];")
+            .unwrap()
+    );
+    assert!(
+        !scalar_raw
+            .expected_ptx
+            .matches("tcgen05.ld.sync.aligned.16x64b.x1.b32 %r1, [%r2];")
+            .unwrap()
+    );
+    let scalar_pack = &loads[1];
+    assert_eq!(
+        scalar_pack.expected_ptx.modifiers,
+        ["ld", "sync", "aligned", "16x64b", "x1", "pack::16b", "b32",]
+    );
+    let largest = &loads[57];
+    assert_eq!(largest.rust_result, "[u32; 128]");
+    assert_eq!(largest.dialect_results.len(), 128);
+    assert_eq!(largest.llvm_results, ["v128i32"]);
+    assert_eq!(
+        largest.expected_ptx.operands,
+        [
+            OperandPattern::RegisterList { length: 128 },
+            OperandPattern::Address,
+        ]
+    );
+
+    let mut missing = test_tcgen05_ld_admission();
+    missing.ld_variants.pop();
+    assert!(expand_tcgen05_admission(&missing).is_err());
+
+    let mut reordered = test_tcgen05_ld_admission();
+    reordered.ld_variants.swap(0, 1);
+    assert!(expand_tcgen05_admission(&reordered).is_err());
+
+    let mut non_contiguous_abi = test_tcgen05_ld_admission();
+    non_contiguous_abi.ld_variants[0].abi_id = "i9999".into();
+    let records = expand_tcgen05_admission(&non_contiguous_abi).unwrap();
+    assert!(records.iter().any(|record| record.abi_id == "i9999"));
+
+    let mut missing_evidence = test_tcgen05_ld_admission();
+    missing_evidence.ld_llvm_evidence_profile = None;
+    assert!(expand_tcgen05_admission(&missing_evidence).is_err());
+
+    let declaration = declarations[loads[0].source_record.as_deref().unwrap()];
+    let mut wrong_selector = loads[0].clone();
+    wrong_selector
+        .tcgen05
+        .as_mut()
+        .unwrap()
+        .ld
+        .as_mut()
+        .unwrap()
+        .pack16 = true;
+    assert!(validate_imported_policy(&wrong_selector, declaration).is_err());
+
+    let mut changed_declaration = declaration.clone();
+    changed_declaration.properties.pop();
+    assert!(validate_imported_policy(&loads[0], &changed_declaration).is_err());
+
+    let mut wrong_scope = loads[0].clone();
+    wrong_scope.execution_scope = "thread".into();
+    assert!(validate_imported_policy(&wrong_scope, declaration).is_err());
+
+    let mut unreviewed_sharing = records.clone();
+    unreviewed_sharing[62].tcgen05.as_mut().unwrap().operation = Tcgen05Operation::Alloc;
+    assert!(validate_unique_overlay(&unreviewed_sharing, 1).is_err());
+}
+
+#[test]
+fn compact_tcgen05_store_admission_matches_all_llvm_records_and_fails_closed() {
+    let records = expand_tcgen05_admission(&test_tcgen05_st_admission()).unwrap();
+    assert_eq!(records.len(), 177);
+    let stores = &records[119..];
+    assert_eq!(stores.len(), 58);
+    assert_eq!(
+        (stores[0].abi_id.as_str(), stores[0].id.as_str()),
+        ("i0670", "tcgen05_st_16x64b_x1_raw")
+    );
+    assert_eq!(
+        (stores[1].abi_id.as_str(), stores[1].id.as_str()),
+        ("i0671", "tcgen05_st_16x64b_x1_unpack16")
+    );
+    assert_eq!(
+        (stores[57].abi_id.as_str(), stores[57].id.as_str()),
+        ("i0727", "tcgen05_st_32x32b_x128_unpack16")
+    );
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+    let mut source_counts = BTreeMap::new();
+    for record in stores {
+        let source_record = record.source_record.as_deref().unwrap();
+        *source_counts.entry(source_record).or_insert(0) += 1;
+        let declaration = declarations[source_record];
+        validate_imported_policy(record, declaration).unwrap();
+        assert_tcgen05_backend_target_split(record);
+        assert_eq!(record.rust_arguments.len(), 2);
+        assert_eq!(record.rust_result, "()");
+        assert!(!record.must_use);
+        assert!(!record.safe);
+        assert!(!record.pure);
+        assert_eq!(record.memory, "write");
+        assert!(record.convergent);
+        assert_eq!(record.execution_scope, "warp");
+        assert_eq!(record.dialect_results, Vec::<String>::new());
+        assert_eq!(record.llvm_results, Vec::<String>::new());
+        assert_eq!(record.llvm_arguments, declaration.arguments);
+        assert_eq!(
+            declaration.properties,
+            [
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ]
+        );
+        assert!(declaration.selections.is_empty());
+    }
+    assert_eq!(source_counts.len(), 29);
+    assert!(source_counts.values().all(|count| *count == 2));
+    validate_unique_overlay(&records, 1).unwrap();
+
+    let scalar_raw = &stores[0];
+    assert_eq!(scalar_raw.rust_arguments, ["u32", "u32"]);
+    assert_eq!(scalar_raw.dialect_operands, ["i32", "i32"]);
+    assert_eq!(scalar_raw.llvm_arguments, ["tmem_ptr", "i32", "i1"]);
+    assert_eq!(
+        scalar_raw.expected_ptx.modifiers,
+        ["st", "sync", "aligned", "16x64b", "x1", "b32"]
+    );
+    assert_eq!(
+        scalar_raw.expected_ptx.operands,
+        [
+            OperandPattern::Address,
+            OperandPattern::RegisterList { length: 1 },
+        ]
+    );
+    assert!(
+        scalar_raw
+            .expected_ptx
+            .matches("tcgen05.st.sync.aligned.16x64b.x1.b32 [%r1], {%r2};")
+            .unwrap()
+    );
+    assert!(
+        !scalar_raw
+            .expected_ptx
+            .matches("tcgen05.st.sync.aligned.16x64b.x1.b32 [%r1], %r2;")
+            .unwrap()
+    );
+    assert_eq!(
+        stores[1].expected_ptx.modifiers,
+        [
+            "st",
+            "sync",
+            "aligned",
+            "16x64b",
+            "x1",
+            "unpack::16b",
+            "b32",
+        ]
+    );
+    let largest = &stores[57];
+    assert_eq!(largest.rust_arguments, ["u32", "[u32; 128]"]);
+    assert_eq!(largest.dialect_operands.len(), 129);
+    assert_eq!(largest.llvm_arguments, ["tmem_ptr", "v128i32", "i1"]);
+    assert_eq!(
+        largest.expected_ptx.operands,
+        [
+            OperandPattern::Address,
+            OperandPattern::RegisterList { length: 128 },
+        ]
+    );
+
+    let mut missing = test_tcgen05_st_admission();
+    missing.st_variants.pop();
+    assert!(expand_tcgen05_admission(&missing).is_err());
+
+    let mut reordered = test_tcgen05_st_admission();
+    reordered.st_variants.swap(0, 1);
+    assert!(expand_tcgen05_admission(&reordered).is_err());
+
+    let mut non_contiguous_abi = test_tcgen05_st_admission();
+    non_contiguous_abi.st_variants[0].abi_id = "i9999".into();
+    let records = expand_tcgen05_admission(&non_contiguous_abi).unwrap();
+    assert!(records.iter().any(|record| record.abi_id == "i9999"));
+
+    let mut missing_evidence = test_tcgen05_st_admission();
+    missing_evidence.st_llvm_evidence_profile = None;
+    assert!(expand_tcgen05_admission(&missing_evidence).is_err());
+
+    let declaration = declarations[stores[0].source_record.as_deref().unwrap()];
+    let mut wrong_selector = stores[0].clone();
+    wrong_selector
+        .tcgen05
+        .as_mut()
+        .unwrap()
+        .st
+        .as_mut()
+        .unwrap()
+        .unpack16 = true;
+    assert!(validate_imported_policy(&wrong_selector, declaration).is_err());
+
+    let mut changed_declaration = declaration.clone();
+    changed_declaration.properties.pop();
+    assert!(validate_imported_policy(&stores[0], &changed_declaration).is_err());
+
+    let mut wrong_scope = stores[0].clone();
+    wrong_scope.execution_scope = "thread".into();
+    assert!(validate_imported_policy(&wrong_scope, declaration).is_err());
+
+    let mut unreviewed_sharing = records.clone();
+    unreviewed_sharing[120].tcgen05.as_mut().unwrap().operation = Tcgen05Operation::Alloc;
+    assert!(validate_unique_overlay(&unreviewed_sharing, 1).is_err());
+}
+
+#[test]
+fn compact_tcgen05_offset_admission_is_exact_and_fails_closed() {
+    let records = expand_tcgen05_admission(&test_tcgen05_offset_admission()).unwrap();
+    assert_eq!(records.len(), 209);
+    let loads = &records[177..193];
+    let stores = &records[193..209];
+    assert_eq!(
+        (loads[0].abi_id.as_str(), loads[0].id.as_str()),
+        ("i0728", "tcgen05_ld_16x32bx2_x1_raw")
+    );
+    assert_eq!(
+        (loads[15].abi_id.as_str(), loads[15].id.as_str()),
+        ("i0743", "tcgen05_ld_16x32bx2_x128_pack16")
+    );
+    assert_eq!(
+        (stores[0].abi_id.as_str(), stores[0].id.as_str()),
+        ("i0744", "tcgen05_st_16x32bx2_x1_raw")
+    );
+    assert_eq!(
+        (stores[15].abi_id.as_str(), stores[15].id.as_str()),
+        ("i0759", "tcgen05_st_16x32bx2_x128_unpack16")
+    );
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+    let mut load_sources = BTreeMap::new();
+    for record in loads {
+        let source = record.source_record.as_deref().unwrap();
+        *load_sources.entry(source).or_insert(0) += 1;
+        let declaration = declarations[source];
+        validate_imported_policy(record, declaration).unwrap();
+        assert_tcgen05_backend_target_split(record);
+        assert_eq!(record.rust_arguments, ["u32", "i64"]);
+        assert_eq!(record.dialect_operands, ["i32", "i64"]);
+        assert_eq!(record.llvm_arguments, ["tmem_ptr", "i64", "i1"]);
+        assert_eq!(record.execution_scope, "warp");
+        assert!(record.must_use);
+        assert_eq!(
+            record.compatibility_rust_paths,
+            [format!("cuda_device::tcgen05::__{}", record.id)]
+        );
+        assert_eq!(
+            record.expected_ptx.operands.last(),
+            Some(&OperandPattern::Immediate)
+        );
+        assert_eq!(
+            declaration.properties,
+            [
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ]
+        );
+    }
+    assert_eq!(load_sources.len(), 8);
+    assert!(load_sources.values().all(|count| *count == 2));
+
+    let mut store_sources = BTreeMap::new();
+    for record in stores {
+        let source = record.source_record.as_deref().unwrap();
+        *store_sources.entry(source).or_insert(0) += 1;
+        let declaration = declarations[source];
+        validate_imported_policy(record, declaration).unwrap();
+        assert_tcgen05_backend_target_split(record);
+        assert_eq!(record.rust_arguments[0..2], ["u32", "i64"]);
+        assert_eq!(record.dialect_operands[0..2], ["i32", "i64"]);
+        assert_eq!(record.llvm_arguments[0..2], ["tmem_ptr", "i64"]);
+        assert_eq!(record.execution_scope, "warp");
+        assert!(!record.must_use);
+        assert_eq!(
+            record.compatibility_rust_paths,
+            [format!("cuda_device::tcgen05::__{}", record.id)]
+        );
+        assert_eq!(
+            record.expected_ptx.operands.get(1),
+            Some(&OperandPattern::Immediate)
+        );
+        assert_eq!(
+            declaration.properties,
+            [
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ]
+        );
+    }
+    assert_eq!(store_sources.len(), 8);
+    assert!(store_sources.values().all(|count| *count == 2));
+    validate_unique_overlay(&records, 1).unwrap();
+
+    let scalar_pack = &loads[1];
+    assert_eq!(
+        scalar_pack.expected_ptx.operands,
+        [
+            OperandPattern::RegisterList { length: 1 },
+            OperandPattern::Address,
+            OperandPattern::Immediate,
+        ]
+    );
+    assert!(
+        scalar_pack
+            .expected_ptx
+            .matches("tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 {%r1}, [%r2], 16;")
+            .unwrap()
+    );
+
+    let scalar_unpack = &stores[1];
+    assert_eq!(
+        scalar_unpack.expected_ptx.operands,
+        [
+            OperandPattern::Address,
+            OperandPattern::Immediate,
+            OperandPattern::RegisterList { length: 1 },
+        ]
+    );
+    assert!(
+        scalar_unpack
+            .expected_ptx
+            .matches("tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [%r1], 16, {%r2};")
+            .unwrap()
+    );
+
+    let mut missing = test_tcgen05_offset_admission();
+    missing.ld_offset_variants.pop();
+    assert!(expand_tcgen05_admission(&missing).is_err());
+
+    let mut reordered = test_tcgen05_offset_admission();
+    reordered.st_offset_variants.swap(0, 1);
+    assert!(expand_tcgen05_admission(&reordered).is_err());
+
+    let mut non_contiguous_abi = test_tcgen05_offset_admission();
+    non_contiguous_abi.ld_offset_variants[0].abi_id = "i9999".into();
+    let records = expand_tcgen05_admission(&non_contiguous_abi).unwrap();
+    assert!(records.iter().any(|record| record.abi_id == "i9999"));
+
+    let mut missing_evidence = test_tcgen05_offset_admission();
+    missing_evidence.offset_llvm_evidence_profile = None;
+    assert!(expand_tcgen05_admission(&missing_evidence).is_err());
+
+    let load_declaration = declarations[loads[0].source_record.as_deref().unwrap()];
+    let mut wrong_offset_type = loads[0].clone();
+    wrong_offset_type.rust_arguments[1] = "i32".into();
+    assert!(validate_imported_policy(&wrong_offset_type, load_declaration).is_err());
+
+    let mut wrong_scope = loads[0].clone();
+    wrong_scope.execution_scope = "thread".into();
+    assert!(validate_imported_policy(&wrong_scope, load_declaration).is_err());
+
+    let mut missing_immediate = loads[0].clone();
+    missing_immediate.expected_ptx.operands.pop();
+    assert!(validate_imported_policy(&missing_immediate, load_declaration).is_err());
+
+    let store_declaration = declarations[stores[0].source_record.as_deref().unwrap()];
+    let mut wrong_adapter = stores[0].clone();
+    wrong_adapter.tcgen05.as_mut().unwrap().adapter =
+        Tcgen05Adapter::TmemU32RegistersInjectUnpack16ToVoid;
+    assert!(validate_imported_policy(&wrong_adapter, store_declaration).is_err());
+
+    let mut changed_declaration = store_declaration.clone();
+    changed_declaration.properties.remove(0);
+    assert!(validate_imported_policy(&stores[0], &changed_declaration).is_err());
+}
+
+#[test]
+fn tcgen05_compact_schema_is_reserved_for_aggregation() {
+    let shard = |schema, admission| OverlayShardFile {
+        schema,
+        family: "tcgen05".into(),
+        intrinsics: vec![],
+        register_mma_int4: None,
+        register_mma_int8: None,
+        register_mma_b1: None,
+        register_mma_f8f6f4_f32: None,
+        register_mma_f8f6f4_f16: None,
+        register_mma_mxf8f6f4_f32: None,
+        register_mma_fp8: None,
+        register_mma_ampere_float: None,
+        sparse_mma_integer: None,
+        sparse_mma_f8f6f4_f32: None,
+        sparse_mma_f8f6f4_f16: None,
+        prmt: None,
+        packed_conversion_fp8: None,
+        packed_conversion_fp8_f16x2: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cluster_sreg: None,
+        cluster_barrier: None,
+        mbarrier_extended: None,
+        special_registers: None,
+        debug_control: None,
+        threadfence: None,
+        cluster_memory: None,
+        stmatrix: None,
+        clc: None,
+        wgmma_controls: None,
+        tma: None,
+        tcgen05: Some(admission),
+    };
+    let path = Path::new("intrinsics/overlay/tcgen05.toml");
+    validate_overlay_shard_schema_with_max(
+        &shard(
+            TCGEN05_SHARD_SCHEMA,
+            without_tcgen05_control(test_tcgen05_admission()),
+        ),
+        path,
+        TCGEN05_CP_SHARD_SCHEMA,
+    )
+    .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(
+                TCGEN05_SHARD_SCHEMA - 1,
+                without_tcgen05_control(test_tcgen05_admission()),
+            ),
+            path,
+            TCGEN05_CP_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("requires overlay shard schema 42")
+    );
+    validate_overlay_shard_schema_with_max(
+        &shard(
+            TCGEN05_CP_SHARD_SCHEMA,
+            without_tcgen05_control(test_tcgen05_cp_admission()),
+        ),
+        path,
+        TCGEN05_CP_SHARD_SCHEMA,
+    )
+    .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(
+                TCGEN05_CP_SHARD_SCHEMA - 1,
+                without_tcgen05_control(test_tcgen05_cp_admission()),
+            ),
+            path,
+            TCGEN05_CP_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("requires overlay shard schema 52")
+    );
+    validate_overlay_shard_schema_with_max(
+        &shard(
+            TCGEN05_LD_SHARD_SCHEMA,
+            without_tcgen05_control(test_tcgen05_ld_admission()),
+        ),
+        path,
+        TCGEN05_LD_SHARD_SCHEMA,
+    )
+    .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(
+                TCGEN05_LD_SHARD_SCHEMA - 1,
+                without_tcgen05_control(test_tcgen05_ld_admission()),
+            ),
+            path,
+            TCGEN05_LD_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("requires overlay shard schema 53")
+    );
+    validate_overlay_shard_schema_with_max(
+        &shard(
+            TCGEN05_ST_SHARD_SCHEMA,
+            without_tcgen05_control(test_tcgen05_st_admission()),
+        ),
+        path,
+        TCGEN05_ST_SHARD_SCHEMA,
+    )
+    .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(
+                TCGEN05_ST_SHARD_SCHEMA - 1,
+                without_tcgen05_control(test_tcgen05_st_admission()),
+            ),
+            path,
+            TCGEN05_ST_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("requires overlay shard schema 54")
+    );
+    validate_overlay_shard_schema_with_max(
+        &shard(
+            TCGEN05_OFFSET_LDST_SHARD_SCHEMA,
+            without_tcgen05_control(test_tcgen05_offset_admission()),
+        ),
+        path,
+        TCGEN05_OFFSET_LDST_SHARD_SCHEMA,
+    )
+    .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(
+                TCGEN05_OFFSET_LDST_SHARD_SCHEMA - 1,
+                without_tcgen05_control(test_tcgen05_offset_admission()),
+            ),
+            path,
+            TCGEN05_OFFSET_LDST_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("requires overlay shard schema 55")
+    );
+    validate_overlay_shard_schema_with_max(
+        &shard(
+            TCGEN05_CONTROL_SHARD_SCHEMA,
+            test_tcgen05_offset_admission(),
+        ),
+        path,
+        TCGEN05_CONTROL_SHARD_SCHEMA,
+    )
+    .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(
+                TCGEN05_CONTROL_SHARD_SCHEMA,
+                without_tcgen05_control(test_tcgen05_offset_admission()),
+            ),
+            path,
+            TCGEN05_CONTROL_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("requires all three control variants and both backend evidence profiles")
+    );
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(
+                TCGEN05_CONTROL_SHARD_SCHEMA - 1,
+                test_tcgen05_offset_admission(),
+            ),
+            path,
+            TCGEN05_CONTROL_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("requires overlay shard schema 56")
+    );
+    validate_overlay_shard_schema_with_max(
+        &shard(TCGEN05_MMA_SHARD_SCHEMA, test_tcgen05_mma_admission()),
+        path,
+        TCGEN05_MMA_SHARD_SCHEMA,
+    )
+    .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(TCGEN05_MMA_SHARD_SCHEMA - 1, test_tcgen05_mma_admission(),),
+            path,
+            TCGEN05_MMA_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("requires overlay shard schema 57")
+    );
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs
new file mode 100644
index 0000000000..9301eeb28c
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs
@@ -0,0 +1,680 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, CatalogHardwareAlternative, CatalogHardwareTarget, ClcAdapter,
+    ClusterBarrierMode, ClusterBarrierOrdering, ClusterMemoryAdapter, ClusterMemoryOperation,
+    EvidenceStageKind, ImportedFile, IntrinsicBackend, IntrinsicSource, OverlayIntrinsic,
+    OverlayShardFile, RuntimeValidation, TmaAdapter, TmaOperation,
+};
+use crate::util::read_json;
+use std::collections::{BTreeMap, BTreeSet};
+use std::path::Path;
+
+use super::fixtures::*;
+use crate::resolve::evidence::*;
+use crate::resolve::families::*;
+use crate::resolve::overlay::*;
+use crate::resolve::policy::*;
+use crate::resolve::targets::*;
+
+#[test]
+fn compact_clc_admission_matches_llvm_and_fails_closed() {
+    let records = expand_clc_admission(&test_clc_admission()).unwrap();
+    assert_eq!(records.len(), 6);
+    assert_eq!(
+        records
+            .iter()
+            .map(|record| (record.abi_id.as_str(), record.id.as_str()))
+            .collect::<Vec<_>>(),
+        [
+            ("i0322", "clc_try_cancel"),
+            ("i0323", "clc_try_cancel_multicast"),
+            ("i0324", "clc_query_is_canceled"),
+            ("i0325", "clc_query_get_first_ctaid_x"),
+            ("i0326", "clc_query_get_first_ctaid_y"),
+            ("i0327", "clc_query_get_first_ctaid_z"),
+        ]
+    );
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+    for record in &records {
+        let declaration = declarations[record.source_record.as_deref().unwrap()];
+        validate_imported_policy(record, declaration).unwrap();
+    }
+
+    assert_eq!(
+        parse_hardware_target(&records[1]).unwrap(),
+        CatalogHardwareTarget::AnyOf {
+            alternatives: vec![
+                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 120 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 121 },
+            ],
+        }
+    );
+
+    let mut missing = test_clc_admission();
+    missing.variants.pop();
+    assert!(expand_clc_admission(&missing).is_err());
+
+    let mut reordered = test_clc_admission();
+    reordered.variants.swap(0, 1);
+    assert!(expand_clc_admission(&reordered).is_err());
+
+    let mut wrong_abi = test_clc_admission();
+    wrong_abi.variants[0].abi_id = "i9999".into();
+    assert!(expand_clc_admission(&wrong_abi).is_err());
+
+    let mut executed = test_clc_admission();
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_clc_admission(&executed).is_err());
+
+    let declaration = declarations[records[2].source_record.as_deref().unwrap()];
+    let mut wrong_adapter = records[2].clone();
+    wrong_adapter.clc.as_mut().unwrap().adapter = ClcAdapter::PairU64ToI128U32;
+    assert!(validate_imported_policy(&wrong_adapter, declaration).is_err());
+
+    let mut unsorted_targets = records[1].clone();
+    unsorted_targets.targets = "sm_120a|sm_100a".into();
+    assert!(parse_hardware_target(&unsorted_targets).is_err());
+
+    let mut duplicate_targets = records[1].clone();
+    duplicate_targets.targets = "sm_100a|sm_100a".into();
+    assert!(parse_hardware_target(&duplicate_targets).is_err());
+}
+
+#[test]
+fn clc_compact_schema_is_reserved_for_aggregation() {
+    let shard = |schema| OverlayShardFile {
+        schema,
+        family: "clc".into(),
+        intrinsics: vec![],
+        register_mma_int4: None,
+        register_mma_int8: None,
+        register_mma_b1: None,
+        register_mma_f8f6f4_f32: None,
+        register_mma_f8f6f4_f16: None,
+        register_mma_mxf8f6f4_f32: None,
+        register_mma_fp8: None,
+        register_mma_ampere_float: None,
+        sparse_mma_integer: None,
+        sparse_mma_f8f6f4_f32: None,
+        sparse_mma_f8f6f4_f16: None,
+        prmt: None,
+        packed_conversion_fp8: None,
+        packed_conversion_fp8_f16x2: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cluster_sreg: None,
+        cluster_barrier: None,
+        mbarrier_extended: None,
+        special_registers: None,
+        debug_control: None,
+        threadfence: None,
+        cluster_memory: None,
+        stmatrix: None,
+        clc: Some(test_clc_admission()),
+        wgmma_controls: None,
+        tma: None,
+        tcgen05: None,
+    };
+    let path = Path::new("intrinsics/overlay/clc.toml");
+    validate_overlay_shard_schema_with_max(&shard(CLC_SHARD_SCHEMA), path, CLC_SHARD_SCHEMA)
+        .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(CLC_SHARD_SCHEMA - 1),
+            path,
+            CLC_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("requires overlay shard schema 40")
+    );
+}
+
+#[test]
+fn compact_tma_admission_matches_llvm_and_fails_closed() {
+    let records = expand_tma_admission(&test_tma_admission()).unwrap();
+    assert_eq!(
+        records.len(),
+        TMA_OPERATIONS.len() + tma_reduction_matrix().len()
+    );
+    assert!(records.iter().take(TMA_OPERATIONS.len()).all(|record| {
+        let operation = record.tma.as_ref().unwrap().operation;
+        let recipe = tma_recipe(operation);
+        record.backend_lowerings.iter().any(|route| {
+            route.backend == IntrinsicBackend::LlvmNvptx && route.mechanism == recipe.llvm_mechanism
+        }) && record.backend_lowerings.iter().any(|route| {
+            route.backend == IntrinsicBackend::LibNvvm
+                && route.mechanism == BackendLoweringMechanism::InlinePtx
+        })
+    }));
+    assert_eq!(
+        records
+            .iter()
+            .filter(|record| {
+                record
+                    .tma
+                    .as_ref()
+                    .unwrap()
+                    .operation
+                    .prefetch_coordinate_count()
+                    .is_some()
+            })
+            .count(),
+        12,
+        "the tile-prefetch subfamily must contain every plain/cache-hint pair"
+    );
+    assert_eq!(
+        records
+            .iter()
+            .take(TMA_OPERATIONS.len())
+            .map(|record| (record.abi_id.as_str(), record.id.as_str()))
+            .collect::<Vec<_>>(),
+        [
+            ("i0328", "cp_async_bulk_tensor_1d_g2s"),
+            ("i0329", "cp_async_bulk_tensor_2d_g2s"),
+            ("i0330", "cp_async_bulk_tensor_2d_g2s_multicast"),
+            ("i0331", "cp_async_bulk_tensor_2d_g2s_multicast_cg2"),
+            ("i0332", "cp_async_bulk_tensor_3d_g2s"),
+            ("i0333", "cp_async_bulk_tensor_4d_g2s"),
+            ("i0334", "cp_async_bulk_tensor_5d_g2s"),
+            ("i0335", "cp_async_bulk_tensor_1d_s2g"),
+            ("i0336", "cp_async_bulk_tensor_2d_s2g"),
+            ("i0337", "cp_async_bulk_tensor_3d_s2g"),
+            ("i0338", "cp_async_bulk_tensor_4d_s2g"),
+            ("i0339", "cp_async_bulk_tensor_5d_s2g"),
+            ("i0340", "cp_async_bulk_commit_group"),
+            ("i0341", "cp_async_bulk_wait_group"),
+            ("i0342", "cp_async_bulk_wait_group_read"),
+            ("i0887", "prefetch_tma_descriptor"),
+            ("i0888", "cp_async_bulk_prefetch_tensor_1d_l2"),
+            ("i0889", "cp_async_bulk_prefetch_tensor_2d_l2"),
+            ("i0890", "cp_async_bulk_prefetch_tensor_3d_l2"),
+            ("i0891", "cp_async_bulk_prefetch_tensor_4d_l2"),
+            ("i0892", "cp_async_bulk_prefetch_tensor_5d_l2"),
+            ("i0893", "cp_async_bulk_prefetch_tensor_gather4_2d_l2"),
+            ("i0894", "tensormap_replace_box_dim"),
+            ("i0895", "tensormap_replace_element_stride"),
+            ("i0896", "tensormap_replace_element_type"),
+            ("i0897", "tensormap_replace_fill_mode"),
+            ("i0898", "tensormap_replace_global_address"),
+            ("i0899", "tensormap_replace_global_dim"),
+            ("i0900", "tensormap_replace_global_stride"),
+            ("i0901", "tensormap_replace_interleave_layout"),
+            ("i0902", "tensormap_replace_rank"),
+            ("i0903", "tensormap_replace_swizzle_atomicity"),
+            ("i0904", "tensormap_replace_swizzle_mode"),
+            ("i0905", "fence_proxy_tensormap_generic_acquire_cluster"),
+            ("i0906", "fence_proxy_tensormap_generic_acquire_cta"),
+            ("i0907", "fence_proxy_tensormap_generic_acquire_gpu"),
+            ("i0908", "fence_proxy_tensormap_generic_acquire_system"),
+            ("i0909", "fence_proxy_tensormap_generic_release_cluster"),
+            ("i0910", "fence_proxy_tensormap_generic_release_cta"),
+            ("i0911", "fence_proxy_tensormap_generic_release_gpu"),
+            ("i0912", "fence_proxy_tensormap_generic_release_system"),
+            ("i0917", "cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"),
+            ("i0918", "cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"),
+            ("i0919", "cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"),
+            ("i0920", "cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"),
+            ("i0921", "cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"),
+            (
+                "i0922",
+                "cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
+            ),
+        ]
+    );
+
+    let reductions = &records[TMA_OPERATIONS.len()..];
+    assert_eq!(reductions.len(), 64);
+    assert_eq!(
+        (reductions[0].abi_id.as_str(), reductions[0].id.as_str()),
+        ("i0923", "cp_async_bulk_tensor_reduce_add_tile_1d")
+    );
+    assert_eq!(
+        (reductions[7].abi_id.as_str(), reductions[7].id.as_str()),
+        ("i0930", "cp_async_bulk_tensor_reduce_add_im2col_5d")
+    );
+    assert_eq!(
+        (reductions[63].abi_id.as_str(), reductions[63].id.as_str()),
+        ("i0986", "cp_async_bulk_tensor_reduce_xor_im2col_5d")
+    );
+    assert!(reductions.iter().all(|record| {
+        record.tma.as_ref().is_some_and(|tma| {
+            tma.operation == TmaOperation::Reduce
+                && tma.reduction.is_some()
+                && tma.adapter == TmaAdapter::ReductionPointersCoordinatesInjectDefaults
+        })
+    }));
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect::<BTreeMap<_, _>>();
+    for record in &records {
+        let declaration = declarations[record.source_record.as_deref().unwrap()];
+        validate_imported_policy(record, declaration).unwrap();
+    }
+
+    assert_eq!(
+        parse_hardware_target(&records[3]).unwrap(),
+        CatalogHardwareTarget::AnyOf {
+            alternatives: vec![
+                CatalogHardwareAlternative::ExactArchitecture { sm: 100 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 101 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 103 },
+                CatalogHardwareAlternative::ExactArchitecture { sm: 110 },
+            ],
+        }
+    );
+
+    let mut missing = test_tma_admission();
+    missing.variants.pop();
+    assert!(expand_tma_admission(&missing).is_err());
+
+    let mut reordered = test_tma_admission();
+    reordered.variants.swap(0, 1);
+    assert!(expand_tma_admission(&reordered).is_err());
+
+    let mut wrong_abi = test_tma_admission();
+    wrong_abi.variants[0].abi_id = "i9999".into();
+    assert!(expand_tma_admission(&wrong_abi).is_err());
+
+    let mut missing_reduction = test_tma_admission();
+    missing_reduction.reduce_variants.pop();
+    assert!(expand_tma_admission(&missing_reduction).is_err());
+
+    let mut reordered_reduction = test_tma_admission();
+    reordered_reduction.reduce_variants.swap(0, 1);
+    assert!(expand_tma_admission(&reordered_reduction).is_err());
+
+    let mut non_contiguous_reduction_abi = test_tma_admission();
+    non_contiguous_reduction_abi.reduce_variants[0].abi_id = "i9999".into();
+    let records = expand_tma_admission(&non_contiguous_reduction_abi).unwrap();
+    assert_eq!(records[TMA_OPERATIONS.len()].abi_id, "i9999");
+
+    let mut executed = test_tma_admission();
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_tma_admission(&executed).is_err());
+
+    let declaration = declarations[records[0].source_record.as_deref().unwrap()];
+    let mut wrong_adapter = records[0].clone();
+    wrong_adapter.tma.as_mut().unwrap().adapter = TmaAdapter::NoOperands;
+    assert!(validate_imported_policy(&wrong_adapter, declaration).is_err());
+}
+
+#[test]
+fn tma_compact_schema_is_reserved_for_aggregation() {
+    let shard = |schema: u32, include_reductions: bool| {
+        let mut admission = test_tma_admission();
+        if !include_reductions {
+            admission.reduce_variants.clear();
+        }
+        OverlayShardFile {
+            schema,
+            family: "tma".into(),
+            intrinsics: vec![],
+            register_mma_int4: None,
+            register_mma_int8: None,
+            register_mma_b1: None,
+            register_mma_f8f6f4_f32: None,
+            register_mma_f8f6f4_f16: None,
+            register_mma_mxf8f6f4_f32: None,
+            register_mma_fp8: None,
+            register_mma_ampere_float: None,
+            sparse_mma_integer: None,
+            sparse_mma_f8f6f4_f32: None,
+            sparse_mma_f8f6f4_f16: None,
+            prmt: None,
+            packed_conversion_fp8: None,
+            packed_conversion_fp8_f16x2: None,
+            scalar_conversion: None,
+            scalar_arithmetic: None,
+            scalar_math: None,
+            extended_minmax: None,
+            cluster_sreg: None,
+            cluster_barrier: None,
+            mbarrier_extended: None,
+            special_registers: None,
+            debug_control: None,
+            threadfence: None,
+            cluster_memory: None,
+            stmatrix: None,
+            clc: None,
+            wgmma_controls: None,
+            tma: Some(admission),
+            tcgen05: None,
+        }
+    };
+    let path = Path::new("intrinsics/overlay/tma.toml");
+
+    validate_overlay_shard_schema_with_max(
+        &shard(TMA_SHARD_SCHEMA, false),
+        path,
+        TMA_REDUCTION_SHARD_SCHEMA,
+    )
+    .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(TMA_SHARD_SCHEMA - 1, false),
+            path,
+            TMA_REDUCTION_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("compact TMA admission requires overlay shard schema 61")
+    );
+
+    validate_overlay_shard_schema_with_max(
+        &shard(TMA_REDUCTION_SHARD_SCHEMA, true),
+        path,
+        TMA_REDUCTION_SHARD_SCHEMA,
+    )
+    .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(TMA_REDUCTION_SHARD_SCHEMA - 1, true),
+            path,
+            TMA_REDUCTION_SHARD_SCHEMA,
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("compact TMA reduction admission requires overlay shard schema 62")
+    );
+}
+
+#[test]
+fn cluster_memory_compact_schema_is_reserved_and_fail_closed() {
+    let shard = |schema| OverlayShardFile {
+        schema,
+        family: "cluster_memory".into(),
+        intrinsics: vec![],
+        register_mma_int4: None,
+        register_mma_int8: None,
+        register_mma_b1: None,
+        register_mma_f8f6f4_f32: None,
+        register_mma_f8f6f4_f16: None,
+        register_mma_mxf8f6f4_f32: None,
+        register_mma_fp8: None,
+        register_mma_ampere_float: None,
+        sparse_mma_integer: None,
+        sparse_mma_f8f6f4_f32: None,
+        sparse_mma_f8f6f4_f16: None,
+        prmt: None,
+        packed_conversion_fp8: None,
+        packed_conversion_fp8_f16x2: None,
+        scalar_conversion: None,
+        scalar_arithmetic: None,
+        scalar_math: None,
+        extended_minmax: None,
+        cluster_sreg: None,
+        cluster_barrier: None,
+        mbarrier_extended: None,
+        special_registers: None,
+        debug_control: None,
+        threadfence: None,
+        cluster_memory: Some(test_cluster_memory_admission()),
+        stmatrix: None,
+        clc: None,
+        wgmma_controls: None,
+        tma: None,
+        tcgen05: None,
+    };
+    let path = Path::new("intrinsics/overlay/cluster_memory.toml");
+    validate_overlay_shard_schema_with_max(
+        &shard(CLUSTER_MEMORY_SHARD_SCHEMA),
+        path,
+        CLUSTER_MEMORY_SHARD_SCHEMA,
+    )
+    .unwrap();
+    assert!(
+        validate_overlay_shard_schema_with_max(
+            &shard(CLUSTER_MEMORY_SHARD_SCHEMA),
+            path,
+            CLUSTER_MEMORY_SHARD_SCHEMA - 1,
+        )
+        .is_err()
+    );
+    let error = validate_overlay_shard_schema_with_max(
+        &shard(CLUSTER_MEMORY_SHARD_SCHEMA - 1),
+        path,
+        CLUSTER_MEMORY_SHARD_SCHEMA,
+    )
+    .unwrap_err();
+    assert!(
+        error
+            .to_string()
+            .contains("requires overlay shard schema 39")
+    );
+}
+
+#[test]
+fn cluster_memory_admission_preserves_mapa_identity_and_ptx_native_read() {
+    let admission = test_cluster_memory_admission();
+    let records = expand_cluster_memory_admission(&admission).unwrap();
+    assert_eq!(records.len(), 2);
+    assert_eq!(records[0].id, "map_shared_rank");
+    assert_eq!(records[1].id, "dsmem_read_u32");
+    assert_eq!(records[0].abi_id, "i0320");
+    assert_eq!(records[1].abi_id, "i0321");
+    assert_eq!(
+        cluster_memory_inline_recipe(ClusterMemoryOperation::MapSharedRank),
+        ("mapa.shared::cluster.u64 $0, $1, $2;", "=l,l,r")
+    );
+    assert_eq!(
+        cluster_memory_inline_recipe(ClusterMemoryOperation::ReadU32),
+        (
+            "{ .reg .u64 %mapped; mapa.shared::cluster.u64 %mapped, $1, $2; ld.shared::cluster.u32 $0, [%mapped]; }",
+            "=r,l,r,~{memory}"
+        )
+    );
+
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let mapa = &records[0];
+    let declaration = imported
+        .intrinsics
+        .iter()
+        .find(|declaration| declaration.source_record == "int_nvvm_mapa_shared_cluster")
+        .unwrap();
+    assert_eq!(declaration.arguments, ["shared_ptr", "i32"]);
+    assert_eq!(declaration.results, ["shared_cluster_ptr"]);
+    assert_eq!(
+        declaration.properties,
+        ["IntrNoMem", "IntrSpeculatable", "NoCapture<arg0>"]
+    );
+    validate_imported_policy(mapa, declaration).unwrap();
+    assert_eq!(
+        declaration
+            .selections
+            .iter()
+            .filter(|selection| selection.asm.starts_with("mapa.shared::cluster.u64"))
+            .map(|selection| selection.source_record.as_str())
+            .collect::<BTreeSet<_>>(),
+        BTreeSet::from(["mapa_shared_cluster_64", "mapa_shared_cluster_64i"])
+    );
+
+    let read = &records[1];
+    validate_ptx_native_policy(read).unwrap();
+    assert!(read.source_record.is_none());
+    assert!(read.llvm_symbol.is_none());
+    assert!(matches!(
+        resolve_policy_source(read).unwrap(),
+        IntrinsicSource::PtxNative { .. }
+    ));
+    assert_eq!(read.memory, "read");
+
+    let mut wrong_adapter = mapa.clone();
+    wrong_adapter.cluster_memory.as_mut().unwrap().adapter =
+        ClusterMemoryAdapter::ConstU32PointerRankToU32;
+    assert!(validate_imported_policy(&wrong_adapter, declaration).is_err());
+
+    let mut typed_as3 = mapa.clone();
+    typed_as3.llvm_results = vec!["shared_ptr".into()];
+    assert!(validate_imported_policy(&typed_as3, declaration).is_err());
+
+    let mut wrong_route = mapa.clone();
+    wrong_route.backend_lowerings[0].mechanism = BackendLoweringMechanism::TypedNvvm;
+    assert!(validate_imported_policy(&wrong_route, declaration).is_err());
+
+    let mut wrong_floor = read.clone();
+    wrong_floor.minimum_sm = Some("sm_80".into());
+    assert!(validate_ptx_native_policy(&wrong_floor).is_err());
+
+    let mut missing = admission.clone();
+    missing.variants.pop();
+    assert!(expand_cluster_memory_admission(&missing).is_err());
+
+    let mut duplicate = admission.clone();
+    duplicate.variants[1].operation = ClusterMemoryOperation::MapSharedRank;
+    assert!(expand_cluster_memory_admission(&duplicate).is_err());
+
+    let mut wrong_abi = admission.clone();
+    wrong_abi.variants[0].abi_id = "i9999".into();
+    assert!(expand_cluster_memory_admission(&wrong_abi).is_err());
+
+    let mut executed = admission;
+    executed.runtime_validation = RuntimeValidation::Executed;
+    assert!(expand_cluster_memory_admission(&executed).is_err());
+}
+
+#[test]
+fn compact_cluster_barrier_admission_and_semantics_fail_closed() {
+    let records = expand_cluster_barrier_admission(&test_cluster_barrier_admission()).unwrap();
+    assert_eq!(records.len(), 6);
+
+    let imported: ImportedFile = read_json(
+        &Path::new(env!("CARGO_MANIFEST_DIR"))
+            .join("../..")
+            .join("intrinsics/imported.json"),
+    )
+    .unwrap();
+    for record in &records {
+        let declaration = imported
+            .intrinsics
+            .iter()
+            .find(|declaration| {
+                Some(declaration.source_record.as_str()) == record.source_record.as_deref()
+            })
+            .unwrap();
+        validate_imported_policy(record, declaration).unwrap();
+    }
+
+    let declaration_for = |record: &OverlayIntrinsic| {
+        imported
+            .intrinsics
+            .iter()
+            .find(|declaration| {
+                Some(declaration.source_record.as_str()) == record.source_record.as_deref()
+            })
+            .unwrap()
+    };
+    let base = records
+        .iter()
+        .find(|record| {
+            record
+                .cluster_barrier
+                .as_ref()
+                .is_some_and(|barrier| barrier.mode == ClusterBarrierMode::ArriveAligned)
+        })
+        .unwrap();
+
+    let mut wrong_mode = base.clone();
+    wrong_mode.cluster_barrier.as_mut().unwrap().mode = ClusterBarrierMode::WaitAligned;
+    assert!(validate_imported_policy(&wrong_mode, declaration_for(base)).is_err());
+
+    let mut wrong_order = base.clone();
+    wrong_order.cluster_barrier.as_mut().unwrap().ordering = ClusterBarrierOrdering::Relaxed;
+    assert!(validate_imported_policy(&wrong_order, declaration_for(base)).is_err());
+
+    let mut wrong_alignment = base.clone();
+    wrong_alignment.cluster_barrier.as_mut().unwrap().aligned = false;
+    assert!(validate_imported_policy(&wrong_alignment, declaration_for(base)).is_err());
+
+    let mut missing = test_cluster_barrier_admission();
+    missing.variants.pop();
+    assert!(expand_cluster_barrier_admission(&missing).is_err());
+
+    let mut duplicate = test_cluster_barrier_admission();
+    duplicate.variants[5].mode = ClusterBarrierMode::Arrive;
+    assert!(expand_cluster_barrier_admission(&duplicate).is_err());
+
+    let mut wrong_abi = test_cluster_barrier_admission();
+    wrong_abi.variants[0].abi_id = "i9999".into();
+    assert!(expand_cluster_barrier_admission(&wrong_abi).is_err());
+}
+
+#[test]
+fn cluster_barrier_evidence_validates_both_backend_routes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let mut admission = test_cluster_barrier_admission();
+    admission.llvm_evidence_profile = "rust-llvm-22.1.2-1cb4e383".into();
+    admission.libnvvm_evidence_profile = "cuda-13.3-libnvvm-13.3.33-cluster-barrier".into();
+    let policies = expand_cluster_barrier_admission(&admission).unwrap();
+    let evidence_files = vec![
+        read_evidence_file(
+            &repo_root.join("intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-cluster-barrier.json"),
+        )
+        .unwrap(),
+        read_evidence_file(
+            &repo_root.join("intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-cluster-barrier.json"),
+        )
+        .unwrap(),
+    ];
+    let indexed =
+        index_evidence(&evidence_files, "1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e").unwrap();
+
+    for policy in &policies {
+        for lowering in &policy.backend_lowerings {
+            let evidence = indexed
+                .get(&(lowering.evidence_profile.as_str(), policy.id.as_str()))
+                .unwrap();
+            validate_evidence(policy, evidence, Some(lowering)).unwrap();
+        }
+    }
+
+    let mut missing_typed_failure = evidence_files.clone();
+    let libnvvm = missing_typed_failure
+        .iter_mut()
+        .find(|file| file.backend_kind == Some(IntrinsicBackend::LibNvvm))
+        .unwrap();
+    for record in &mut libnvvm.records {
+        record.stages.retain(|stage| {
+            stage.mechanism != Some(BackendLoweringMechanism::TypedNvvm)
+                || stage.stage != EvidenceStageKind::DeviceLink
+        });
+    }
+    let indexed = index_evidence(
+        &missing_typed_failure,
+        "1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e",
+    )
+    .unwrap();
+    let policy = &policies[0];
+    let lowering = policy
+        .backend_lowerings
+        .iter()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
+        .unwrap();
+    let evidence = indexed
+        .get(&(lowering.evidence_profile.as_str(), policy.id.as_str()))
+        .unwrap();
+    assert!(validate_evidence(policy, evidence, Some(lowering)).is_err());
+}
diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/warp.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/warp.rs
new file mode 100644
index 0000000000..65c4260068
--- /dev/null
+++ b/crates/cuda-intrinsics-gen/src/resolve/tests/warp.rs
@@ -0,0 +1,1008 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::model::{
+    BackendLoweringMechanism, ImportedFile, ImportedIntrinsic, IntrinsicBackend, IntrinsicSource,
+    OverlayIntrinsic, PreSm70MemberMaskRule, VoteMode, WarpMatchAdapter, WarpShuffleAdapter,
+    WarpShuffleMode, WarpShuffleOperandEncoding, WarpShuffleValueKind,
+};
+use crate::ptx::{InstructionPattern, OperandPattern};
+use crate::util::read_json;
+use std::collections::{BTreeMap, BTreeSet};
+use std::path::Path;
+
+use super::fixtures::*;
+use crate::resolve::families::*;
+use crate::resolve::guards::*;
+use crate::resolve::materialize::*;
+use crate::resolve::overlay::*;
+use crate::resolve::policy::*;
+
+#[test]
+fn pinned_active_mask_and_warp_match_recipes_resolve() {
+    let records = pinned_active_mask_and_warp_match_records();
+    assert_eq!(records.len(), 5);
+
+    for (policy, declaration) in records.values() {
+        validate_imported_policy(policy, declaration).unwrap();
+    }
+}
+
+#[test]
+fn active_mask_and_warp_match_recipes_fail_closed() {
+    let records = pinned_active_mask_and_warp_match_records();
+    let reject = |policy: &OverlayIntrinsic, declaration: &ImportedIntrinsic, expected: &str| {
+        let error = validate_imported_policy(policy, declaration).unwrap_err();
+        let message = error.to_string();
+        assert!(message.contains(expected), "unexpected error: {message}");
+    };
+
+    let (active_mask, active_mask_declaration) = &records["active_mask"];
+    let mut wrong_identity = active_mask.clone();
+    wrong_identity.operation_key = "warp.active_mask.changed".into();
+    reject(
+        &wrong_identity,
+        active_mask_declaration,
+        "active-mask identity",
+    );
+
+    let mut wrong_effects = active_mask.clone();
+    wrong_effects.memory = "none".into();
+    reject(
+        &wrong_effects,
+        active_mask_declaration,
+        "active-mask effects or target floor",
+    );
+
+    let (match_any, match_any_declaration) = &records["match_any_sync"];
+    let mut wrong_adapter = match_any.clone();
+    wrong_adapter.warp_match.as_mut().unwrap().adapter =
+        WarpMatchAdapter::ProjectMaskDiscardPredicate;
+    reject(
+        &wrong_adapter,
+        match_any_declaration,
+        "warp-match participation, adapter, or encoding",
+    );
+
+    let (match_all, match_all_declaration) = &records["match_all_sync"];
+    let mut wrong_projection = match_all.clone();
+    wrong_projection.dialect_results.push("i1".into());
+    reject(
+        &wrong_projection,
+        match_all_declaration,
+        "two-operand warp-match lowering recipe",
+    );
+
+    let (match_any_i64, match_any_i64_declaration) = &records["match_any_i64_sync"];
+    let mut incomplete_selections = match_any_i64_declaration.clone();
+    incomplete_selections.selections.pop();
+    reject(
+        match_any_i64,
+        &incomplete_selections,
+        "exactly ii/ir/ri/rr selections",
+    );
+
+    let (match_all_i64, match_all_i64_declaration) = &records["match_all_i64_sync"];
+    let mut wrong_predicates = match_all_i64_declaration.clone();
+    wrong_predicates.selections[0].predicates[0] = "Subtarget->getPTXVersion() >= 61".into();
+    reject(
+        match_all_i64,
+        &wrong_predicates,
+        "PTX shape, predicates, or constraints",
+    );
+}
+
+#[test]
+fn ptx_native_source_provenance_fails_closed() {
+    let mut mixed = packed_policy("packed_atomic_add_f16x2");
+    mixed.source_record = Some("invented_llvm_record".into());
+    assert!(
+        resolve_policy_source(&mixed)
+            .unwrap_err()
+            .to_string()
+            .contains("mixes tagged source provenance")
+    );
+
+    let mut fake_llvm = packed_policy("packed_atomic_add_f16x2");
+    fake_llvm.llvm_symbol = Some("llvm.fake.packed.atomic".into());
+    fake_llvm.llvm_arguments = vec!["ptr".into(), "i32".into()];
+    fake_llvm.llvm_results = vec!["i32".into()];
+    assert!(
+        validate_ptx_native_policy(&fake_llvm)
+            .unwrap_err()
+            .to_string()
+            .contains("must not invent LLVM source facts")
+    );
+
+    let mut wrong_instruction = packed_policy("packed_atomic_add_f16x2");
+    wrong_instruction.source = Some(IntrinsicSource::PtxNative {
+        instruction: "atom.global.add.noftz.bf16x2".into(),
+    });
+    assert!(
+        validate_ptx_native_policy(&wrong_instruction)
+            .unwrap_err()
+            .to_string()
+            .contains("does not match its packed format")
+    );
+
+    let mut wrong_kind = packed_policy("packed_atomic_add_f16x2");
+    wrong_kind.source = Some(IntrinsicSource::LlvmImported {
+        source_record: "invented_llvm_record".into(),
+    });
+    assert!(
+        validate_ptx_native_policy(&wrong_kind)
+            .unwrap_err()
+            .to_string()
+            .contains("source kind and imported declaration disagree")
+    );
+}
+
+#[test]
+fn vote_modes_keep_exact_abi_identity_and_both_selection_encodings() {
+    for mode in [
+        VoteMode::All,
+        VoteMode::Any,
+        VoteMode::Ballot,
+        VoteMode::Uni,
+    ] {
+        let policy = vote_policy(mode);
+        let declaration = vote_declaration(mode);
+        validate_imported_policy(&policy, &declaration).unwrap();
+        assert_eq!(
+            policy.vote.as_ref().unwrap().legacy_pre_sm70,
+            PreSm70MemberMaskRule::AllNamedLanesConvergedAndOnlyNamedLanesActive
+        );
+
+        let selected: Vec<_> = declaration
+            .selections
+            .iter()
+            .filter(|selection| selection_matches_policy(&policy, selection).unwrap())
+            .collect();
+        assert_eq!(selected.len(), 2);
+        assert!(
+            selected.iter().any(|selection| {
+                selection.source_record == vote_recipe(mode).immediate_selection
+            })
+        );
+        assert!(
+            selected.iter().any(|selection| {
+                selection.source_record == vote_recipe(mode).register_selection
+            })
+        );
+
+        let mut record = evidence();
+        record.id = policy.id.clone();
+        record.source_record = policy.source_record.clone();
+        record.llvm_symbol = policy.llvm_symbol.clone();
+        record.llvm_arguments = policy.llvm_arguments.clone();
+        record.llvm_results = policy.llvm_results.clone();
+        record.expected_ptx = policy.expected_ptx.clone();
+        let resolved = resolve_record(
+            &policy,
+            resolve_policy_source(&policy).unwrap(),
+            Some(&declaration),
+            &record,
+            "test",
+            "LLVM version test",
+            "0123456789abcdef",
+            vec![],
+            1,
+        )
+        .unwrap();
+        assert_eq!(resolved.selections.len(), 2);
+        assert_eq!(resolved.vote, policy.vote);
+    }
+}
+
+#[test]
+fn vote_contract_rejects_unreviewed_identity_effect_and_selection_changes() {
+    let valid = vote_policy(VoteMode::All);
+    let declaration = vote_declaration(VoteMode::All);
+
+    let mut wrong_abi = valid.clone();
+    wrong_abi.abi_id = "i0041".into();
+    assert!(
+        validate_imported_policy(&wrong_abi, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("vote identity")
+    );
+
+    let mut safe = valid.clone();
+    safe.safe = true;
+    safe.safe_allowlist_reason = Some("incorrectly hides participation obligations".into());
+    assert!(
+        validate_imported_policy(&safe, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("unsafe must-use vote")
+    );
+
+    let mut wrong_memory = valid.clone();
+    wrong_memory.memory = "none".into();
+    assert!(
+        validate_imported_policy(&wrong_memory, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("vote effects")
+    );
+
+    let mut register_only_mask = valid.clone();
+    register_only_mask.expected_ptx.operands[2] = OperandPattern::Register;
+    assert!(
+        validate_imported_policy(&register_only_mask, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("expected PTX")
+    );
+
+    let mut one_selection = declaration.clone();
+    one_selection.selections.pop();
+    assert!(
+        validate_imported_policy(&valid, &one_selection)
+            .unwrap_err()
+            .to_string()
+            .contains("immediate/register selection pair")
+    );
+
+    let mut different_predicates = declaration;
+    different_predicates.selections[1].predicates[0] = "Subtarget->getPTXVersion() >= 61".into();
+    assert!(
+        validate_imported_policy(&valid, &different_predicates)
+            .unwrap_err()
+            .to_string()
+            .contains("disagree on PTX shape")
+    );
+}
+
+#[test]
+fn uni_vote_is_raw_only_while_existing_votes_keep_compatibility_paths() {
+    for mode in [VoteMode::All, VoteMode::Any, VoteMode::Ballot] {
+        assert_eq!(vote_policy(mode).compatibility_rust_paths.len(), 1);
+    }
+    let uni = vote_policy(VoteMode::Uni);
+    assert!(uni.compatibility_rust_paths.is_empty());
+
+    let mut invented_compatibility_path = uni.clone();
+    invented_compatibility_path.compatibility_rust_paths =
+        vec!["cuda_device::warp::uni_sync".into()];
+    assert!(
+        validate_imported_policy(
+            &invented_compatibility_path,
+            &vote_declaration(VoteMode::Uni),
+        )
+        .unwrap_err()
+        .to_string()
+        .contains("reviewed compatibility path")
+    );
+}
+
+#[test]
+fn warp_shuffle_variants_keep_exact_identity_clamp_and_eight_selections() {
+    for (mode, value_kind, clamp) in [
+        (WarpShuffleMode::Idx, WarpShuffleValueKind::I32, 31),
+        (WarpShuffleMode::Bfly, WarpShuffleValueKind::I32, 31),
+        (WarpShuffleMode::Down, WarpShuffleValueKind::I32, 31),
+        (WarpShuffleMode::Up, WarpShuffleValueKind::I32, 0),
+        (WarpShuffleMode::Idx, WarpShuffleValueKind::F32, 31),
+        (WarpShuffleMode::Bfly, WarpShuffleValueKind::F32, 31),
+        (WarpShuffleMode::Down, WarpShuffleValueKind::F32, 31),
+        (WarpShuffleMode::Up, WarpShuffleValueKind::F32, 0),
+    ] {
+        let policy = warp_shuffle_policy(mode, value_kind);
+        let declaration = warp_shuffle_declaration(mode, value_kind);
+        validate_imported_policy(&policy, &declaration).unwrap();
+
+        assert_eq!(policy.warp_shuffle.as_ref().unwrap().clamp, clamp);
+        assert_eq!(
+            declaration
+                .selections
+                .iter()
+                .filter(|selection| selection_matches_policy(&policy, selection).unwrap())
+                .count(),
+            8
+        );
+
+        let mut record = evidence();
+        record.id = policy.id.clone();
+        record.source_record = policy.source_record.clone();
+        record.llvm_symbol = policy.llvm_symbol.clone();
+        record.llvm_arguments = policy.llvm_arguments.clone();
+        record.llvm_results = policy.llvm_results.clone();
+        record.expected_ptx = policy.expected_ptx.clone();
+        let resolved = resolve_record(
+            &policy,
+            resolve_policy_source(&policy).unwrap(),
+            Some(&declaration),
+            &record,
+            "test",
+            "LLVM version test",
+            "0123456789abcdef",
+            vec![],
+            1,
+        )
+        .unwrap();
+        assert_eq!(resolved.selections.len(), 8);
+        assert_eq!(resolved.warp_shuffle, policy.warp_shuffle);
+    }
+}
+
+#[test]
+fn pinned_warp_shuffle_records_match_the_closed_recipes() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let (overlay, _) =
+        read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap();
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let declarations: BTreeMap<_, _> = imported
+        .intrinsics
+        .iter()
+        .map(|record| (record.source_record.as_str(), record))
+        .collect();
+    let all_policies: Vec<_> = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "warp_shuffle")
+        .collect();
+    assert_eq!(all_policies.len(), 12);
+    let native_policies: Vec<_> = all_policies
+        .iter()
+        .copied()
+        .filter(|record| record.source.is_some())
+        .collect();
+    assert_eq!(native_policies.len(), 4);
+    for policy in native_policies {
+        validate_ptx_native_policy(policy).unwrap();
+    }
+    let policies: Vec<_> = overlay
+        .intrinsics
+        .iter()
+        .filter(|record| record.family == "warp_shuffle" && record.source_record.is_some())
+        .collect();
+    assert_eq!(policies.len(), 8);
+    for policy in policies {
+        let declaration = declarations[policy.source_record.as_deref().unwrap()];
+        validate_imported_policy(policy, declaration).unwrap();
+    }
+}
+
+#[test]
+fn pinned_llvm_has_no_direct_i64_or_f64_shuffle_record() {
+    let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../..");
+    let imported: ImportedFile = read_json(&repo_root.join("intrinsics/imported.json")).unwrap();
+    let direct_64: Vec<_> = imported
+        .intrinsics
+        .iter()
+        .filter(|record| {
+            record.llvm_name.starts_with("llvm.nvvm.shfl")
+                && (record.llvm_name.contains(".i64") || record.llvm_name.contains(".f64"))
+        })
+        .map(|record| record.llvm_name.as_str())
+        .collect();
+    assert!(
+        direct_64.is_empty(),
+        "unexpected LLVM records: {direct_64:?}"
+    );
+}
+
+#[test]
+fn i64_warp_shuffle_recipes_are_exact_ptx_native_pairs() {
+    let cases = [
+        (
+            WarpShuffleMode::Idx,
+            "shuffle_u64_sync",
+            "i0058",
+            "warp.shuffle.sync.idx.i64",
+            "shfl.sync.idx.b32",
+            "idx",
+            31,
+            "ShflSyncIdxI64Op",
+            "nvvm.shfl_sync_idx_i64",
+        ),
+        (
+            WarpShuffleMode::Bfly,
+            "shuffle_xor_u64_sync",
+            "i0059",
+            "warp.shuffle.sync.bfly.i64",
+            "shfl.sync.bfly.b32",
+            "bfly",
+            31,
+            "ShflSyncBflyI64Op",
+            "nvvm.shfl_sync_bfly_i64",
+        ),
+        (
+            WarpShuffleMode::Down,
+            "shuffle_down_u64_sync",
+            "i0060",
+            "warp.shuffle.sync.down.i64",
+            "shfl.sync.down.b32",
+            "down",
+            31,
+            "ShflSyncDownI64Op",
+            "nvvm.shfl_sync_down_i64",
+        ),
+        (
+            WarpShuffleMode::Up,
+            "shuffle_up_u64_sync",
+            "i0061",
+            "warp.shuffle.sync.up.i64",
+            "shfl.sync.up.b32",
+            "up",
+            0,
+            "ShflSyncUpI64Op",
+            "nvvm.shfl_sync_up_i64",
+        ),
+    ];
+
+    for (mode, id, abi_id, operation_key, instruction, ptx_mode, clamp, op_type, op_name) in cases {
+        let policy = warp_shuffle_policy(mode, WarpShuffleValueKind::I64);
+        validate_ptx_native_policy(&policy).unwrap();
+
+        assert_eq!(policy.id, id);
+        assert_eq!(policy.abi_id, abi_id);
+        assert_eq!(policy.operation_key, operation_key);
+        assert_eq!(
+            policy.source,
+            Some(IntrinsicSource::PtxNative {
+                instruction: instruction.into(),
+            })
+        );
+        assert!(policy.source_record.is_none());
+        assert!(policy.llvm_symbol.is_none());
+        assert!(policy.resolved_llvm_symbol.is_none());
+        assert!(policy.llvm_arguments.is_empty());
+        assert!(policy.llvm_results.is_empty());
+        assert_eq!(policy.rust_arguments, ["u32", "u64", "u32"]);
+        assert_eq!(policy.rust_result, "u64");
+        assert!(!policy.safe);
+        assert!(policy.must_use);
+        assert_eq!(policy.dialect_op_type, op_type);
+        assert_eq!(policy.dialect_op_name, op_name);
+        assert_eq!(policy.dialect_operands, ["i32", "i64", "i32"]);
+        assert_eq!(policy.dialect_results, ["i64"]);
+        assert_eq!(policy.lowering, "generated_warp_shuffle_i64_inline_ptx");
+
+        let shuffle = policy.warp_shuffle.as_ref().unwrap();
+        assert_eq!(shuffle.clamp, clamp);
+        assert_eq!(
+            shuffle.adapter,
+            WarpShuffleAdapter::MaskValueLaneOrDeltaSplitI64LowHighB32InsertClampReassemble
+        );
+        assert_eq!(
+            shuffle.lane_encoding,
+            WarpShuffleOperandEncoding::RegisterOnly
+        );
+        assert_eq!(
+            shuffle.mask_encoding,
+            WarpShuffleOperandEncoding::RegisterOnly
+        );
+        assert_eq!(
+            policy.expected_ptx,
+            InstructionPattern::new(
+                "shfl",
+                &["sync", ptx_mode, "b32"],
+                vec![
+                    OperandPattern::Exact { value: "lo".into() },
+                    OperandPattern::Exact { value: "lo".into() },
+                    OperandPattern::Register,
+                    OperandPattern::Exact {
+                        value: clamp.to_string(),
+                    },
+                    OperandPattern::Register,
+                ],
+            )
+        );
+
+        let routes: BTreeMap<_, _> = policy
+            .backend_lowerings
+            .iter()
+            .map(|route| (route.backend, route))
+            .collect();
+        assert_eq!(routes.len(), 2);
+        for backend in [IntrinsicBackend::LlvmNvptx, IntrinsicBackend::LibNvvm] {
+            assert_eq!(
+                routes[&backend].mechanism,
+                BackendLoweringMechanism::InlinePtx
+            );
+            assert_eq!(routes[&backend].minimum_ptx.as_deref(), Some("6.0"));
+        }
+        assert_eq!(
+            routes[&IntrinsicBackend::LlvmNvptx].minimum_sm.as_deref(),
+            Some("sm_30")
+        );
+        assert_eq!(
+            routes[&IntrinsicBackend::LibNvvm].minimum_sm.as_deref(),
+            Some("sm_75")
+        );
+
+        let mut record = evidence();
+        record.id = policy.id.clone();
+        record.source = policy.source.clone();
+        record.source_record = None;
+        record.llvm_symbol = None;
+        record.llvm_arguments.clear();
+        record.llvm_results.clear();
+        record.expected_ptx = policy.expected_ptx.clone();
+        let resolved = resolve_record(
+            &policy,
+            resolve_policy_source(&policy).unwrap(),
+            None,
+            &record,
+            "test",
+            "LLVM version test",
+            "0123456789abcdef",
+            vec![],
+            1,
+        )
+        .unwrap();
+        assert!(resolved.llvm.is_none());
+        assert!(resolved.selections.is_empty());
+        assert_eq!(resolved.warp_shuffle, policy.warp_shuffle);
+    }
+}
+
+#[test]
+fn i64_warp_shuffle_contract_rejects_unreviewed_changes() {
+    let valid = warp_shuffle_policy(WarpShuffleMode::Idx, WarpShuffleValueKind::I64);
+    validate_ptx_native_policy(&valid).unwrap();
+
+    let reject = |policy: &OverlayIntrinsic, expected: &str| {
+        let error = validate_ptx_native_policy(policy).unwrap_err();
+        let message = error.to_string();
+        assert!(message.contains(expected), "unexpected error: {message}");
+    };
+
+    let mut fabricated_llvm = valid.clone();
+    fabricated_llvm.source = None;
+    fabricated_llvm.source_record = Some("int_nvvm_shfl_sync_idx_i64".into());
+    fabricated_llvm.llvm_symbol = Some("llvm.nvvm.shfl.sync.idx.i64".into());
+    fabricated_llvm.llvm_arguments = vec!["i32".into(), "i64".into(), "i32".into(), "i32".into()];
+    fabricated_llvm.llvm_results = vec!["i64".into()];
+    reject(
+        &fabricated_llvm,
+        "source kind and imported declaration disagree",
+    );
+
+    let mut wrong_source = valid.clone();
+    wrong_source.source = Some(IntrinsicSource::PtxNative {
+        instruction: "shfl.sync.down.b32".into(),
+    });
+    reject(&wrong_source, "warp-shuffle identity");
+
+    let mut wrong_adapter = valid.clone();
+    wrong_adapter.warp_shuffle.as_mut().unwrap().adapter =
+        WarpShuffleAdapter::MaskValueLaneOrDeltaInsertClamp;
+    reject(&wrong_adapter, "semantic or operand contract");
+
+    let mut wrong_mode = valid.clone();
+    wrong_mode.warp_shuffle.as_mut().unwrap().mode = WarpShuffleMode::Up;
+    wrong_mode.warp_shuffle.as_mut().unwrap().clamp = 0;
+    wrong_mode.expected_ptx.modifiers[1] = "up".into();
+    wrong_mode.expected_ptx.operands[3] = OperandPattern::Exact { value: "0".into() };
+    reject(&wrong_mode, "warp-shuffle identity");
+
+    let mut wrong_clamp = valid.clone();
+    wrong_clamp.warp_shuffle.as_mut().unwrap().clamp = 0;
+    reject(&wrong_clamp, "semantic or operand contract");
+
+    let mut broad_encoding = valid.clone();
+    broad_encoding.warp_shuffle.as_mut().unwrap().lane_encoding =
+        WarpShuffleOperandEncoding::RegisterOrImmediate;
+    reject(&broad_encoding, "semantic or operand contract");
+
+    let mut typed_backend = valid.clone();
+    typed_backend.backend_lowerings[0].mechanism = BackendLoweringMechanism::TypedNvvm;
+    reject(&typed_backend, "reviewed LLVM and libNVVM routes");
+
+    let mut wrong_native_floor = valid.clone();
+    wrong_native_floor.minimum_sm = Some("sm_70".into());
+    reject(&wrong_native_floor, "target floor");
+
+    let mut wrong_profile_floor = valid.clone();
+    wrong_profile_floor
+        .backend_lowerings
+        .iter_mut()
+        .find(|route| route.backend == IntrinsicBackend::LibNvvm)
+        .unwrap()
+        .minimum_sm = Some("sm_80".into());
+    reject(&wrong_profile_floor, "profile floor");
+
+    let mut safe = valid.clone();
+    safe.safe = true;
+    safe.safe_allowlist_reason = Some("incorrectly hides participation obligations".into());
+    reject(&safe, "unsafe must-use warp-shuffle");
+
+    let mut wrong_ptx = valid;
+    wrong_ptx.expected_ptx.operands[0] = OperandPattern::Register;
+    reject(&wrong_ptx, "closed shfl.sync recipe");
+}
+
+#[test]
+fn warp_shuffle_contract_rejects_unreviewed_policy_changes() {
+    let valid = warp_shuffle_policy(WarpShuffleMode::Idx, WarpShuffleValueKind::I32);
+    let declaration = warp_shuffle_declaration(WarpShuffleMode::Idx, WarpShuffleValueKind::I32);
+
+    let reject_policy = |policy: &OverlayIntrinsic, expected: &str| {
+        let error = match validate_imported_policy(policy, &declaration) {
+            Ok(()) => panic!("{expected} mutation was accepted"),
+            Err(error) => error,
+        };
+        let message = error.to_string();
+        assert!(message.contains(expected), "unexpected error: {message}");
+    };
+
+    let mut wrong_identity = valid.clone();
+    wrong_identity.operation_key = "warp.shuffle.sync.idx.changed".into();
+    reject_policy(&wrong_identity, "warp-shuffle identity");
+
+    let mut safe = valid.clone();
+    safe.safe = true;
+    safe.safe_allowlist_reason = Some("incorrectly hides participation obligations".into());
+    reject_policy(&safe, "unsafe must-use warp-shuffle");
+
+    let mut wrong_signature = valid.clone();
+    wrong_signature.dialect_operands.pop();
+    reject_policy(&wrong_signature, "closed warp-shuffle lowering recipe");
+
+    let mut wrong_clamp = valid.clone();
+    wrong_clamp.warp_shuffle.as_mut().unwrap().clamp = 0;
+    reject_policy(&wrong_clamp, "semantic or operand contract");
+
+    let mut missing_contract = valid.clone();
+    missing_contract.warp_shuffle = None;
+    reject_policy(&missing_contract, "closed warp-shuffle contract");
+
+    let mut mixed_contract = valid.clone();
+    mixed_contract.vote = vote_policy(VoteMode::All).vote;
+    reject_policy(&mixed_contract, "mixes another generated-family contract");
+
+    let mut wrong_backend_floor = valid.clone();
+    wrong_backend_floor
+        .backend_lowerings
+        .iter_mut()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
+        .unwrap()
+        .minimum_sm = Some("sm_80".into());
+    reject_policy(&wrong_backend_floor, "profile floor");
+}
+
+#[test]
+fn warp_shuffle_contract_rejects_selection_drift() {
+    let valid = warp_shuffle_policy(WarpShuffleMode::Down, WarpShuffleValueKind::F32);
+    let declaration = warp_shuffle_declaration(WarpShuffleMode::Down, WarpShuffleValueKind::F32);
+    let reject = |declaration: &ImportedIntrinsic, expected: &str| {
+        let error = validate_imported_policy(&valid, declaration).unwrap_err();
+        let message = error.to_string();
+        assert!(message.contains(expected), "unexpected error: {message}");
+    };
+
+    let mut missing_selection = declaration.clone();
+    missing_selection.selections.pop();
+    reject(
+        &missing_selection,
+        "eight distinct operand-encoding selections",
+    );
+
+    let mut duplicate_selection = declaration.clone();
+    duplicate_selection.selections[7].source_record =
+        duplicate_selection.selections[0].source_record.clone();
+    reject(
+        &duplicate_selection,
+        "eight distinct operand-encoding selections",
+    );
+
+    let mut empty_selection_name = declaration.clone();
+    empty_selection_name.selections[7].source_record.clear();
+    reject(
+        &empty_selection_name,
+        "eight distinct operand-encoding selections",
+    );
+
+    let mut wrong_asm = declaration.clone();
+    wrong_asm.selections[0].asm =
+        "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;".into();
+    reject(&wrong_asm, "selections disagree on PTX shape");
+
+    let mut wrong_predicate = declaration.clone();
+    wrong_predicate.selections[0].predicates[0] = "Subtarget->getPTXVersion() >= 61".into();
+    reject(&wrong_predicate, "selections disagree on PTX shape");
+
+    let mut constrained = declaration;
+    constrained.selections[0]
+        .constraints
+        .immediate_bindings
+        .push(crate::model::ImportedImmediateBinding {
+            argument_index: 2,
+            value: 1,
+        });
+    reject(&constrained, "selections disagree on PTX shape");
+
+    let mut wrong_classes =
+        warp_shuffle_declaration(WarpShuffleMode::Down, WarpShuffleValueKind::F32);
+    wrong_classes.classes.pop();
+    reject(&wrong_classes, "class or effects");
+}
+
+#[test]
+fn sync_threads_selects_only_the_fixed_immediate_barrier_recipe() {
+    let policy = sync_policy();
+    let declaration = sync_declaration();
+    validate_imported_policy(&policy, &declaration).unwrap();
+
+    let selected: Vec<_> = declaration
+        .selections
+        .iter()
+        .filter(|selection| selection_matches_policy(&policy, selection).unwrap())
+        .collect();
+    assert_eq!(selected.len(), 1);
+    assert_eq!(selected[0].source_record, "BARRIER_CTA_SYNC_ALIGNED_ALL_i");
+    assert_eq!(selected[0].asm, "bar.sync \t$i;");
+    assert!(policy.expected_ptx.matches("bar.sync 0;").unwrap());
+    assert!(!policy.expected_ptx.matches(&selected[0].asm).unwrap());
+    assert_eq!(policy.minimum_ptx, "1.0");
+    assert!(policy.minimum_sm.is_none());
+    let llvm_route = policy
+        .backend_lowerings
+        .iter()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+        .unwrap();
+    assert_eq!(llvm_route.minimum_ptx.as_deref(), Some("3.2"));
+    assert_eq!(llvm_route.minimum_sm.as_deref(), Some("sm_20"));
+
+    let resolved = resolve_record(
+        &policy,
+        resolve_policy_source(&policy).unwrap(),
+        Some(&declaration),
+        &sync_evidence(&policy),
+        "test",
+        "LLVM version test",
+        "0123456789abcdef",
+        vec![],
+        1,
+    )
+    .unwrap();
+    assert!(resolved.dialect.operands.is_empty());
+    assert!(resolved.dialect.results.is_empty());
+    assert_eq!(resolved.selections.len(), 1);
+    assert_eq!(
+        resolved.selections[0].source_record,
+        "BARRIER_CTA_SYNC_ALIGNED_ALL_i"
+    );
+}
+
+#[test]
+fn sync_threads_recipe_rejects_unreviewed_selection_effect_and_floor_changes() {
+    let valid = sync_policy();
+    let declaration = sync_declaration();
+
+    let mut register_only = declaration.clone();
+    register_only
+        .selections
+        .retain(|selection| selection.source_record.ends_with("_r"));
+    assert!(
+        validate_imported_policy(&valid, &register_only)
+            .unwrap_err()
+            .to_string()
+            .contains("does not agree")
+    );
+
+    let mut wrong_properties = declaration.clone();
+    wrong_properties.properties.pop();
+    assert!(
+        validate_imported_policy(&valid, &wrong_properties)
+            .unwrap_err()
+            .to_string()
+            .contains("sync properties")
+    );
+
+    let mut wrong_source = valid.clone();
+    wrong_source.source_record = Some("int_nvvm_barrier0".into());
+    assert!(
+        validate_imported_policy(&wrong_source, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("sync identity")
+    );
+
+    let mut wrong_signature = valid.clone();
+    wrong_signature.llvm_arguments.clear();
+    assert!(
+        validate_imported_policy(&wrong_signature, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("LLVM argument signature mismatch")
+    );
+
+    let mut wrong_path = valid.clone();
+    wrong_path.compatibility_rust_paths.swap(0, 1);
+    assert!(
+        validate_imported_policy(&wrong_path, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("both cuda-device compatibility paths")
+    );
+
+    let mut safe = valid.clone();
+    safe.safe = true;
+    safe.safe_allowlist_reason = Some("incorrectly hides the participation contract".into());
+    assert!(
+        validate_imported_policy(&safe, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("unsafe sync_threads raw API")
+    );
+
+    let mut wrong_effect = valid.clone();
+    wrong_effect.memory = "none".into();
+    assert!(
+        validate_imported_policy(&wrong_effect, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("sync effects")
+    );
+
+    let mut native_floor = valid.clone();
+    native_floor.minimum_sm = Some("sm_75".into());
+    assert!(
+        validate_imported_policy(&native_floor, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("native target floor")
+    );
+
+    let mut missing_profile_floor = valid;
+    missing_profile_floor
+        .backend_lowerings
+        .iter_mut()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
+        .unwrap()
+        .minimum_sm = None;
+    assert!(
+        validate_imported_policy(&missing_profile_floor, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("profile floor")
+    );
+
+    let mut wrong_llvm_floor = sync_policy();
+    wrong_llvm_floor
+        .backend_lowerings
+        .iter_mut()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LlvmNvptx)
+        .unwrap()
+        .minimum_ptx = None;
+    assert!(
+        validate_imported_policy(&wrong_llvm_floor, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("profile floor")
+    );
+}
+
+#[test]
+fn sync_mask_matches_the_closed_warp_barrier_recipe() {
+    let policy = warp_barrier_policy();
+    let declaration = warp_barrier_declaration();
+    validate_imported_policy(&policy, &declaration).unwrap();
+
+    let selected: Vec<_> = declaration
+        .selections
+        .iter()
+        .filter(|selection| selection_matches_policy(&policy, selection).unwrap())
+        .collect();
+    assert_eq!(selected.len(), 2);
+    assert_eq!(
+        selected
+            .iter()
+            .map(|selection| selection.source_record.as_str())
+            .collect::<BTreeSet<_>>(),
+        BTreeSet::from(["INT_BAR_WARP_SYNC_I", "INT_BAR_WARP_SYNC_R"])
+    );
+
+    let mut record = evidence();
+    record.id = policy.id.clone();
+    record.source_record = policy.source_record.clone();
+    record.llvm_symbol = policy.llvm_symbol.clone();
+    record.llvm_arguments = policy.llvm_arguments.clone();
+    record.llvm_results = policy.llvm_results.clone();
+    record.expected_ptx = policy.expected_ptx.clone();
+    let resolved = resolve_record(
+        &policy,
+        resolve_policy_source(&policy).unwrap(),
+        Some(&declaration),
+        &record,
+        "test",
+        "LLVM version test",
+        "0123456789abcdef",
+        vec![],
+        1,
+    )
+    .unwrap();
+    assert_eq!(resolved.selections.len(), 2);
+    assert_eq!(resolved.warp_barrier, policy.warp_barrier);
+}
+
+#[test]
+fn sync_mask_recipe_rejects_unreviewed_contract_and_selection_changes() {
+    let valid = warp_barrier_policy();
+    let declaration = warp_barrier_declaration();
+
+    let mut wrong_identity = valid.clone();
+    wrong_identity.id = "bar_warp_sync".into();
+    assert!(
+        validate_imported_policy(&wrong_identity, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("warp-barrier identity")
+    );
+
+    let mut missing_contract = valid.clone();
+    missing_contract.warp_barrier = None;
+    assert!(
+        validate_imported_policy(&missing_contract, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("closed warp-barrier contract")
+    );
+
+    let mut safe_raw_api = valid.clone();
+    safe_raw_api.safe = true;
+    safe_raw_api.safe_allowlist_reason = Some("incorrectly hides participation rules".into());
+    assert!(
+        validate_imported_policy(&safe_raw_api, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("unsafe raw API")
+    );
+
+    let mut wrong_memory = valid.clone();
+    wrong_memory.memory = "none".into();
+    assert!(
+        validate_imported_policy(&wrong_memory, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("effects or target floor")
+    );
+
+    let mut register_only = valid.clone();
+    register_only.expected_ptx.operands[0] = OperandPattern::Register;
+    assert!(
+        validate_imported_policy(&register_only, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("expected PTX")
+    );
+
+    let mut one_selection = declaration.clone();
+    one_selection.selections.pop();
+    assert!(
+        validate_imported_policy(&valid, &one_selection)
+            .unwrap_err()
+            .to_string()
+            .contains("immediate/register selection pair")
+    );
+
+    let mut wrong_predicate = declaration.clone();
+    wrong_predicate.selections[1].predicates[0] = "Subtarget->getPTXVersion() >= 61".into();
+    assert!(
+        validate_imported_policy(&valid, &wrong_predicate)
+            .unwrap_err()
+            .to_string()
+            .contains("selections disagree")
+    );
+
+    let mut missing_libnvvm_floor = valid;
+    missing_libnvvm_floor
+        .backend_lowerings
+        .iter_mut()
+        .find(|lowering| lowering.backend == IntrinsicBackend::LibNvvm)
+        .unwrap()
+        .minimum_sm = None;
+    assert!(
+        validate_imported_policy(&missing_libnvvm_floor, &declaration)
+            .unwrap_err()
+            .to_string()
+            .contains("profile floor")
+    );
+}
diff --git a/crates/cuda-macros/src/common.rs b/crates/cuda-macros/src/common.rs
new file mode 100644
index 0000000000..9a4d1b453d
--- /dev/null
+++ b/crates/cuda-macros/src/common.rs
@@ -0,0 +1,147 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Hygiene-critical identifier construction, attribute helpers, and
+//! reserved-name checks shared by every macro in this crate.
+
+use proc_macro::TokenStream;
+use reserved_oxide_symbols::{
+    CODEGEN_FINGERPRINT_ENV, MATERIALIZE_CUBIN_ENV, MATERIALIZER_PROVENANCE_ENV, RESERVED_ROOT,
+};
+use syn::{FnArg, Ident, ItemFn, visit::Visit};
+
+/// Record cuda-oxide's exact device-codegen identity in the consuming crate's
+/// dep-info. Cargo then rebuilds only crates that can own or instantiate device
+/// code when output mode, architecture, policy, or tool provenance changes.
+pub(crate) fn track_codegen_environment() {
+    let _ = proc_macro::tracked::env_var(CODEGEN_FINGERPRINT_ENV);
+    let _ = proc_macro::tracked::env_var(MATERIALIZE_CUBIN_ENV);
+    let _ = proc_macro::tracked::env_var(MATERIALIZER_PROVENANCE_ENV);
+}
+
+/// Build a private identifier that cannot capture, or be captured by, a name
+/// written in the user's kernel signature.
+pub(crate) fn internal_ident(name: &str) -> Ident {
+    let span = if proc_macro::is_available() {
+        proc_macro::Span::def_site().into()
+    } else {
+        // Expansion helpers are also exercised as ordinary unit tests, where
+        // the compiler's procedural-macro bridge is intentionally unavailable.
+        proc_macro2::Span::call_site()
+    };
+    Ident::new(name, span)
+}
+
+pub(crate) fn cuda_module_async_lifetime() -> syn::Lifetime {
+    let ident = internal_ident("__cuda_oxide_async");
+    syn::Lifetime::new(&format!("'{}", ident), ident.span())
+}
+
+struct IdentFinder<'a> {
+    name: &'a str,
+    found: bool,
+}
+
+impl<'ast> Visit<'ast> for IdentFinder<'_> {
+    fn visit_ident(&mut self, ident: &'ast Ident) {
+        self.found |= ident == self.name;
+    }
+}
+
+pub(crate) fn call_site_ident_avoiding_item(name: &str, item: &ItemFn) -> Ident {
+    let mut candidate = name.to_owned();
+    loop {
+        let mut finder = IdentFinder {
+            name: &candidate,
+            found: false,
+        };
+        finder.visit_item_fn(item);
+        if !finder.found {
+            break;
+        }
+        candidate.push('_');
+    }
+    Ident::new(&candidate, proc_macro2::Span::call_site())
+}
+
+/// Reject function names that start with the reserved cuda-oxide prefix
+/// (`cuda_oxide_`).
+///
+/// User code must not define functions in the cuda-oxide internal naming
+/// namespace. Two failure modes this guards against:
+///
+/// 1. **Cosmetic.** `#[kernel] fn cuda_oxide_kernel_foo()` would expand to
+///    a doubly-nested name like
+///    `fn cuda_oxide_kernel_<hash>_cuda_oxide_kernel_foo()`, producing
+///    confusing symbol names in MIR dumps and stack traces.
+/// 2. **Forward-compatibility.** Future refactors may extend the namespace;
+///    rejecting it at the source level keeps the contract clean.
+///
+/// Returns `Some(compile_error)` to be returned from the macro entry point,
+/// or `None` if the name is safe.
+pub(crate) fn reject_reserved_name(name: &Ident) -> Option<TokenStream> {
+    let name_str = name.to_string();
+    if name_str.starts_with(RESERVED_ROOT) {
+        let msg = format!(
+            "function name `{name_str}` starts with the reserved cuda-oxide \
+             prefix `{RESERVED_ROOT}`; rename your function — this namespace \
+             is reserved for cuda-oxide internal symbol mangling \
+             (see crates/reserved-oxide-symbols)"
+        );
+        Some(syn::Error::new(name.span(), msg).to_compile_error().into())
+    } else {
+        None
+    }
+}
+
+/// Reject argument-position `impl Trait`, which rustc represents as a hidden
+/// type parameter that procedural macros cannot name at launch sites.
+///
+/// Without this check the host emits a non-generic lookup name while the
+/// backend correctly emits a `_TID_...` specialization, causing a runtime
+/// function-not-found error. A named generic preserves the same source-level
+/// intent and gives both sides an explicit specialization identity.
+pub(crate) fn impl_trait_parameter_error(input: &ItemFn, item_kind: &str) -> Option<syn::Error> {
+    #[derive(Default)]
+    struct Finder {
+        first: Option<syn::TypeImplTrait>,
+    }
+
+    impl<'ast> syn::visit::Visit<'ast> for Finder {
+        fn visit_type_impl_trait(&mut self, node: &'ast syn::TypeImplTrait) {
+            if self.first.is_none() {
+                self.first = Some(node.clone());
+            }
+        }
+    }
+
+    let mut finder = Finder::default();
+    for arg in &input.sig.inputs {
+        if let FnArg::Typed(pat_type) = arg {
+            syn::visit::Visit::visit_type(&mut finder, &pat_type.ty);
+        }
+    }
+
+    finder.first.map(|impl_trait| {
+        syn::Error::new_spanned(
+            impl_trait,
+            format!(
+                "{item_kind} parameters cannot use `impl Trait`; name the type parameter explicitly (for example, `fn named<T: Trait>(value: T)`) so host and device specialization identities agree"
+            ),
+        )
+    })
+}
+
+pub(crate) fn has_attr_named(attrs: &[syn::Attribute], name: &str) -> bool {
+    attrs.iter().any(|attr| attr_path_ends_with(attr, name))
+}
+
+pub(crate) fn attr_path_ends_with(attr: &syn::Attribute, name: &str) -> bool {
+    attr.path()
+        .segments
+        .last()
+        .map(|segment| segment.ident == name)
+        .unwrap_or(false)
+}
diff --git a/crates/cuda-macros/src/cuda_module/constants.rs b/crates/cuda-macros/src/cuda_module/constants.rs
new file mode 100644
index 0000000000..775a9e984d
--- /dev/null
+++ b/crates/cuda-macros/src/cuda_module/constants.rs
@@ -0,0 +1,279 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Constant-memory (`#[constant]` statics inside `#[cuda_module]`)
+//! support: collection, symbol naming, and loader plumbing.
+
+use crate::common::{attr_path_ends_with, has_attr_named};
+use crate::cuda_module::{cuda_module_cfg_attrs, cuda_module_method_attrs};
+use proc_macro2::TokenStream as TokenStream2;
+use quote::{format_ident, quote};
+use reserved_oxide_symbols::constant_symbol;
+use syn::{Ident, Item, LitStr, Type, parse_quote};
+
+/// A `#[constant]` static collected from a `#[cuda_module]` body.
+pub(super) struct CudaModuleConstant {
+    pub(super) ident: Ident,
+    pub(super) ty: Box<Type>,
+    pub(super) cfg_attrs: Vec<syn::Attribute>,
+    pub(super) method_attrs: Vec<syn::Attribute>,
+    pub(super) symbol: String,
+}
+
+pub(super) fn collect_cuda_module_constants(
+    items: &[Item],
+    module_ident: &Ident,
+) -> syn::Result<Vec<CudaModuleConstant>> {
+    let mut constants = Vec::new();
+    for item in items {
+        let Item::Static(item_static) = item else {
+            continue;
+        };
+        if !has_attr_named(&item_static.attrs, "constant") {
+            continue;
+        }
+        if extract_constant_inner_ty(&item_static.ty).is_none() {
+            return Err(syn::Error::new_spanned(
+                &item_static.ty,
+                concat!(
+                    "#[constant] static must have type `ConstantMemory<T>` ",
+                    "(e.g. `static FOO: ConstantMemory<[f32; 4]> = ConstantMemory::UNINIT;`). ",
+                    "The wrapper prevents the compiler from constant-folding the initializer into kernel bodies.",
+                ),
+            ));
+        }
+        constants.push(CudaModuleConstant {
+            ident: item_static.ident.clone(),
+            ty: item_static.ty.clone(),
+            cfg_attrs: cuda_module_cfg_attrs(&item_static.attrs)?,
+            method_attrs: cuda_module_method_attrs(&item_static.attrs),
+            symbol: cuda_module_constant_symbol(module_ident, &item_static.ident),
+        });
+    }
+    Ok(constants)
+}
+
+fn cuda_module_constant_symbol(module_ident: &Ident, ident: &Ident) -> String {
+    let start = ident.span().start();
+    let base = format!(
+        "{}_L{}C{}_{}",
+        module_ident, start.line, start.column, ident
+    );
+    constant_symbol(&base)
+}
+
+pub(super) fn cuda_module_items_with_constant_symbols(
+    items: &[Item],
+    constants: &[CudaModuleConstant],
+) -> Vec<TokenStream2> {
+    let mut constants = constants.iter();
+    items
+        .iter()
+        .map(|item| {
+            let Item::Static(item_static) = item else {
+                return quote! { #item };
+            };
+            if !has_attr_named(&item_static.attrs, "constant") {
+                return quote! { #item };
+            }
+            let constant = constants
+                .next()
+                .expect("constant collection and rewrite order drifted");
+
+            let mut item_static = item_static.clone();
+            let symbol = LitStr::new(&constant.symbol, constant.ident.span());
+            item_static.attrs = item_static
+                .attrs
+                .into_iter()
+                .map(|attr| {
+                    if attr_path_ends_with(&attr, "constant") {
+                        let path = attr.path().clone();
+                        parse_quote!(#[#path(export_name = #symbol)])
+                    } else {
+                        attr
+                    }
+                })
+                .collect();
+            quote! { #item_static }
+        })
+        .collect()
+}
+
+fn cuda_module_constant_field_ident(ident: &Ident) -> Ident {
+    format_ident!("__{}", ident)
+}
+
+fn cuda_module_constant_resolver_ident(ident: &Ident) -> Ident {
+    format_ident!("__resolve_{}", ident)
+}
+
+/// Extract `T` from a `ConstantMemory<T>` type path. Returns `None` for anything
+/// that's not a path ending in `ConstantMemory<...>` with one generic argument.
+pub(crate) fn extract_constant_inner_ty(ty: &Type) -> Option<&Type> {
+    let Type::Path(type_path) = ty else {
+        return None;
+    };
+    let last = type_path.path.segments.last()?;
+    if last.ident != "ConstantMemory" {
+        return None;
+    }
+    let syn::PathArguments::AngleBracketed(args) = &last.arguments else {
+        return None;
+    };
+    if args.args.len() != 1 {
+        return None;
+    }
+    args.args.iter().find_map(|a| match a {
+        syn::GenericArgument::Type(t) => Some(t),
+        _ => None,
+    })
+}
+
+/// Like [`extract_constant_inner_ty`] but for sites that have already been
+/// gated by `#[constant]`'s type-path validation, so extraction failure is
+/// a compiler-internal invariant violation, not a user error.
+fn constant_inner_ty(ty: &Type) -> &Type {
+    extract_constant_inner_ty(ty).unwrap_or_else(|| {
+        panic!(
+            "#[cuda_module] collected a #[constant] static whose type is not ConstantMemory<T>; \
+             this should have been rejected by the #[constant] attribute"
+        )
+    })
+}
+
+pub(super) fn generate_cuda_module_constant_field(constant: &CudaModuleConstant) -> TokenStream2 {
+    let CudaModuleConstant {
+        ident, cfg_attrs, ..
+    } = constant;
+    let field = cuda_module_constant_field_ident(ident);
+    quote! {
+        #(#cfg_attrs)*
+        #field: ::std::sync::Arc<::std::sync::Mutex<::core::option::Option<::cuda_core::ConstantHandle>>>,
+    }
+}
+
+pub(super) fn generate_cuda_module_constant_initializer(
+    constant: &CudaModuleConstant,
+) -> TokenStream2 {
+    let CudaModuleConstant {
+        ident, cfg_attrs, ..
+    } = constant;
+    let field = cuda_module_constant_field_ident(ident);
+    quote! {
+        #(#cfg_attrs)*
+        #field: ::std::sync::Arc::new(::std::sync::Mutex::new(::core::option::Option::None)),
+    }
+}
+
+pub(super) fn generate_cuda_module_constant_resolver_method(
+    constant: &CudaModuleConstant,
+) -> TokenStream2 {
+    let CudaModuleConstant {
+        ident,
+        ty,
+        cfg_attrs,
+        symbol,
+        ..
+    } = constant;
+    let field = cuda_module_constant_field_ident(ident);
+    let resolver = cuda_module_constant_resolver_ident(ident);
+    let symbol_lit = LitStr::new(symbol, ident.span());
+    let inner_ty = constant_inner_ty(ty);
+    let mismatch_msg = format!(
+        "host/device size mismatch for #[constant] static `{ident}`: \
+         device size {{}} bytes, host expected {{}} bytes (PTX symbol `{symbol}`)"
+    );
+    quote! {
+        #(#cfg_attrs)*
+        #[allow(non_snake_case)]
+        fn #resolver(&self) -> ::core::result::Result<::cuda_core::ConstantHandle, ::cuda_core::DriverError> {
+            let mut slot = self
+                .#field
+                .lock()
+                .expect("cuda constant handle cache mutex poisoned");
+            if let ::core::option::Option::Some(handle) = *slot {
+                return ::core::result::Result::Ok(handle);
+            }
+
+            let (dptr, size) = self.__module.get_global(#symbol_lit)?;
+            assert_eq!(
+                size,
+                ::core::mem::size_of::<#inner_ty>(),
+                #mismatch_msg,
+                size,
+                ::core::mem::size_of::<#inner_ty>(),
+            );
+            // SAFETY: `dptr` was just resolved by `cuModuleGetGlobal` for a
+            // module that the LoadedModule keeps alive, and the size matches
+            // `size_of::<#inner_ty>()` (asserted above).
+            let handle = unsafe { ::cuda_core::ConstantHandle::from_raw(dptr) };
+            *slot = ::core::option::Option::Some(handle);
+            ::core::result::Result::Ok(handle)
+        }
+    }
+}
+
+/// Generate stream-ordered `set_<name>` and one-shot `set_<name>_blocking`
+/// methods on `LoadedModule`. The async setter stages owned host bytes so
+/// temporaries remain valid until CUDA reaches the stream callback.
+pub(super) fn generate_cuda_module_set_constant_method(
+    constant: &CudaModuleConstant,
+) -> TokenStream2 {
+    let CudaModuleConstant {
+        ident,
+        ty,
+        cfg_attrs,
+        method_attrs,
+        ..
+    } = constant;
+    let method_suffix = ident.to_string().to_ascii_lowercase();
+    let method_name = format_ident!("set_{}", method_suffix);
+    let blocking_name = format_ident!("set_{}_blocking", method_suffix);
+    let resolver = cuda_module_constant_resolver_ident(ident);
+    let inner_ty = constant_inner_ty(ty);
+
+    quote! {
+        #(#cfg_attrs)*
+        #(#method_attrs)*
+        #[allow(non_snake_case)]
+        pub fn #method_name(
+            &self,
+            stream: &::cuda_core::CudaStream,
+            value: &#inner_ty,
+        ) -> ::core::result::Result<(), ::cuda_core::DriverError> {
+            let handle = self.#resolver()?;
+            let num_bytes = ::core::mem::size_of::<#inner_ty>();
+            let mut bytes = ::std::boxed::Box::<[u8]>::new_uninit_slice(num_bytes);
+            unsafe {
+                ::core::ptr::copy_nonoverlapping(
+                    value as *const #inner_ty as *const u8,
+                    bytes.as_mut_ptr() as *mut u8,
+                    num_bytes,
+                );
+            }
+            handle.write_async_staged(stream, bytes)
+        }
+
+        #(#cfg_attrs)*
+        #(#method_attrs)*
+        #[allow(non_snake_case)]
+        pub fn #blocking_name(
+            &self,
+            value: &#inner_ty,
+        ) -> ::core::result::Result<(), ::cuda_core::DriverError> {
+            let handle = self.#resolver()?;
+            // SAFETY: handle was size-checked against `#inner_ty` by the lazy
+            // resolver; `value` is a valid host pointer for
+            // `size_of::<#inner_ty>()`.
+            unsafe {
+                handle.write_blocking(
+                    &self.__module,
+                    value as *const #inner_ty as *const u8,
+                    ::core::mem::size_of::<#inner_ty>(),
+                )
+            }
+        }
+    }
+}
diff --git a/crates/cuda-macros/src/cuda_module/contract.rs b/crates/cuda-macros/src/cuda_module/contract.rs
new file mode 100644
index 0000000000..1281fd70d9
--- /dev/null
+++ b/crates/cuda-macros/src/cuda_module/contract.rs
@@ -0,0 +1,842 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Launch-contract parsing and validation for `#[cuda_module]`,
+//! including the `requires` relation pipeline.
+
+use crate::common::{attr_path_ends_with, internal_ident};
+use crate::cuda_module::model::{
+    CudaModuleKernel, CudaModuleParam, CudaModuleParamMarshal, ScalarIntClass,
+};
+use crate::launch_attrs::{ClusterArgs, ConstU32Expr, LaunchBoundsArgs};
+use proc_macro2::TokenStream as TokenStream2;
+use quote::quote;
+use syn::{
+    Expr, Ident, Token, parenthesized,
+    parse::{Parse, ParseStream},
+    punctuated::Punctuated,
+    spanned::Spanned,
+};
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub(crate) enum DynamicSharedContract {
+    Exact(u32),
+    Range { min_bytes: u32, max_bytes: u32 },
+}
+
+#[derive(Clone)]
+pub(super) struct CudaModuleLaunchContract {
+    pub(super) domain: u8,
+    pub(super) u32_coordinates: bool,
+    pub(super) exact_block: Option<(u32, u32, u32)>,
+    pub(super) max_block_threads: Option<ConstU32Expr>,
+    pub(super) dynamic_shared: DynamicSharedContract,
+    pub(super) dynamic_shared_alignment: u32,
+    pub(super) min_compute_capability: (u32, u32),
+    /// Size requirements over the kernel's own parameters, validated
+    /// against the parameter list at expansion time. Each relation becomes an
+    /// overflow-safe host-side check in every checked launcher.
+    pub(super) requires: Vec<Expr>,
+}
+
+/// Arguments accepted by `#[launch_contract(...)]`.
+///
+/// The attribute is intentionally declarative. The kernel author states the
+/// launch domain and resource envelope; `#[cuda_module]` turns that statement
+/// into a branded host configuration and validates it against the live
+/// function/device once during preparation.
+#[derive(Clone)]
+pub(crate) struct LaunchContractArgs {
+    pub(crate) domain: u8,
+    pub(crate) u32_coordinates: bool,
+    pub(crate) exact_block: Option<(u32, u32, u32)>,
+    pub(crate) dynamic_shared: DynamicSharedContract,
+    pub(crate) dynamic_shared_alignment: u32,
+    pub(crate) min_compute_capability: (u32, u32),
+    pub(crate) requires: Vec<Expr>,
+}
+
+impl Parse for LaunchContractArgs {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let mut domain = None;
+        let mut exact_block = None;
+        let mut coordinates = None;
+        let mut dynamic_shared = None;
+        let mut dynamic_shared_range = None;
+        let mut dynamic_shared_alignment = None;
+        let mut min_compute_capability = None;
+        let mut requires = None;
+
+        while !input.is_empty() {
+            let key: Ident = input.parse()?;
+            input.parse::<Token![=]>()?;
+            match key.to_string().as_str() {
+                "domain" => {
+                    reject_duplicate(&key, domain.is_some())?;
+                    let value: syn::LitInt = input.parse()?;
+                    domain = Some(value.base10_parse::<u8>()?);
+                }
+                "block" => {
+                    reject_duplicate(&key, exact_block.is_some())?;
+                    exact_block = Some(parse_u32_triplet(input, "block")?);
+                }
+                "coordinates" => {
+                    reject_duplicate(&key, coordinates.is_some())?;
+                    let width: Ident = input.parse()?;
+                    if width != "u32" {
+                        return Err(syn::Error::new(
+                            width.span(),
+                            "launch_contract coordinates currently supports only `u32`",
+                        ));
+                    }
+                    coordinates = Some(true);
+                }
+                "dynamic_shared" => {
+                    reject_duplicate(&key, dynamic_shared.is_some())?;
+                    let value: syn::LitInt = input.parse()?;
+                    dynamic_shared = Some(value.base10_parse::<u32>()?);
+                }
+                "dynamic_shared_range" => {
+                    reject_duplicate(&key, dynamic_shared_range.is_some())?;
+                    dynamic_shared_range = Some(parse_u32_pair(input, "dynamic_shared_range")?);
+                }
+                "dynamic_shared_alignment" => {
+                    reject_duplicate(&key, dynamic_shared_alignment.is_some())?;
+                    let value: syn::LitInt = input.parse()?;
+                    dynamic_shared_alignment = Some(value.base10_parse::<u32>()?);
+                }
+                "min_compute_capability" => {
+                    reject_duplicate(&key, min_compute_capability.is_some())?;
+                    let (major, minor) = parse_u32_pair(input, "min_compute_capability")?;
+                    min_compute_capability = Some((major, minor));
+                }
+                "requires" => {
+                    reject_duplicate(&key, requires.is_some())?;
+                    requires = Some(parse_requires_relations(input)?);
+                }
+                _ => {
+                    return Err(syn::Error::new(
+                        key.span(),
+                        "unknown launch_contract field; expected domain, coordinates, block, dynamic_shared, dynamic_shared_range, dynamic_shared_alignment, min_compute_capability, or requires",
+                    ));
+                }
+            }
+
+            if input.is_empty() {
+                break;
+            }
+            input.parse::<Token![,]>()?;
+        }
+
+        let domain = domain.ok_or_else(|| {
+            syn::Error::new(
+                input.span(),
+                "launch_contract requires `domain = 1`, `2`, or `3`",
+            )
+        })?;
+        if !(1..=3).contains(&domain) {
+            return Err(syn::Error::new(
+                input.span(),
+                "launch_contract domain must be 1, 2, or 3",
+            ));
+        }
+        if dynamic_shared.is_some() && dynamic_shared_range.is_some() {
+            return Err(syn::Error::new(
+                input.span(),
+                "launch_contract accepts either `dynamic_shared` or `dynamic_shared_range`, not both",
+            ));
+        }
+        let dynamic_shared = match (dynamic_shared, dynamic_shared_range) {
+            (Some(bytes), None) => DynamicSharedContract::Exact(bytes),
+            (None, Some((min_bytes, max_bytes))) if min_bytes <= max_bytes => {
+                DynamicSharedContract::Range {
+                    min_bytes,
+                    max_bytes,
+                }
+            }
+            (None, Some(_)) => {
+                return Err(syn::Error::new(
+                    input.span(),
+                    "dynamic_shared_range minimum cannot exceed its maximum",
+                ));
+            }
+            (None, None) => DynamicSharedContract::Exact(0),
+            (Some(_), Some(_)) => unreachable!(),
+        };
+        let dynamic_shared_alignment = dynamic_shared_alignment.unwrap_or_else(|| {
+            if dynamic_shared_max(dynamic_shared) == 0 {
+                1
+            } else {
+                16
+            }
+        });
+        if dynamic_shared_alignment == 0 || !dynamic_shared_alignment.is_power_of_two() {
+            return Err(syn::Error::new(
+                input.span(),
+                "dynamic_shared_alignment must be a non-zero power of two",
+            ));
+        }
+        if exact_block.is_none() {
+            // A missing exact shape is valid only when #[launch_bounds]
+            // supplies the compiled maximum. This is checked after all kernel
+            // attributes have been collected so the two attributes remain one
+            // source of truth rather than duplicate integers.
+        }
+        let min_compute_capability = min_compute_capability.unwrap_or((0, 0));
+        Ok(Self {
+            domain,
+            u32_coordinates: coordinates.unwrap_or(false),
+            exact_block,
+            dynamic_shared,
+            dynamic_shared_alignment,
+            min_compute_capability,
+            requires: requires.unwrap_or_default(),
+        })
+    }
+}
+
+/// Parses `requires = (relation, relation, ...)`: a parenthesized,
+/// comma-separated, non-empty list of relation expressions. The grammar of
+/// each relation is validated later, once the kernel's parameter list is
+/// known (see [`validate_requires_relations`]).
+fn parse_requires_relations(input: ParseStream) -> syn::Result<Vec<Expr>> {
+    let content;
+    parenthesized!(content in input);
+    let relations: Punctuated<Expr, Token![,]> = Punctuated::parse_terminated(&content)?;
+    if relations.is_empty() {
+        return Err(syn::Error::new(
+            content.span(),
+            "requires needs at least one relation, e.g. `requires = (a.len() >= n)`",
+        ));
+    }
+    Ok(relations.into_iter().collect())
+}
+
+pub(crate) fn dynamic_shared_max(contract: DynamicSharedContract) -> u32 {
+    match contract {
+        DynamicSharedContract::Exact(bytes) => bytes,
+        DynamicSharedContract::Range { max_bytes, .. } => max_bytes,
+    }
+}
+
+fn reject_duplicate(key: &Ident, duplicate: bool) -> syn::Result<()> {
+    if duplicate {
+        Err(syn::Error::new(
+            key.span(),
+            format!("duplicate launch_contract field `{key}`"),
+        ))
+    } else {
+        Ok(())
+    }
+}
+
+fn parse_u32_triplet(input: ParseStream, field: &str) -> syn::Result<(u32, u32, u32)> {
+    let content;
+    parenthesized!(content in input);
+    let values: Punctuated<syn::LitInt, Token![,]> = Punctuated::parse_terminated(&content)?;
+    if values.len() != 3 {
+        return Err(syn::Error::new(
+            content.span(),
+            format!("{field} must be a three-dimensional tuple `(x, y, z)`"),
+        ));
+    }
+    let mut values = values.iter();
+    Ok((
+        values.next().unwrap().base10_parse()?,
+        values.next().unwrap().base10_parse()?,
+        values.next().unwrap().base10_parse()?,
+    ))
+}
+
+fn parse_u32_pair(input: ParseStream, field: &str) -> syn::Result<(u32, u32)> {
+    let content;
+    parenthesized!(content in input);
+    let values: Punctuated<syn::LitInt, Token![,]> = Punctuated::parse_terminated(&content)?;
+    if values.len() != 2 {
+        return Err(syn::Error::new(
+            content.span(),
+            format!("{field} must be a two-value tuple"),
+        ));
+    }
+    let mut values = values.iter();
+    Ok((
+        values.next().unwrap().base10_parse()?,
+        values.next().unwrap().base10_parse()?,
+    ))
+}
+
+pub(super) fn cuda_module_cluster_dim(
+    attrs: &[syn::Attribute],
+) -> syn::Result<Option<(u32, u32, u32)>> {
+    for attr in attrs {
+        if attr_path_ends_with(attr, "cluster_launch") {
+            let args = attr.parse_args::<ClusterArgs>()?;
+            return Ok(Some((args.x, args.y, args.z)));
+        }
+    }
+    Ok(None)
+}
+
+pub(super) fn cuda_module_cooperative(attrs: &[syn::Attribute]) -> syn::Result<bool> {
+    for attr in attrs {
+        if attr_path_ends_with(attr, "cooperative_launch") {
+            if !matches!(attr.meta, syn::Meta::Path(_)) {
+                return Err(syn::Error::new_spanned(
+                    attr,
+                    "cooperative_launch takes no arguments: use a bare #[cooperative_launch]",
+                ));
+            }
+            return Ok(true);
+        }
+    }
+    Ok(false)
+}
+
+pub(super) fn cuda_module_launch_contract(
+    attrs: &[syn::Attribute],
+    _fn_name: &Ident,
+    params: &[CudaModuleParam],
+    cluster_dim: Option<(u32, u32, u32)>,
+) -> syn::Result<Option<CudaModuleLaunchContract>> {
+    let contract_attrs: Vec<_> = attrs
+        .iter()
+        .filter(|attr| attr_path_ends_with(attr, "launch_contract"))
+        .collect();
+    if contract_attrs.len() > 1 {
+        return Err(syn::Error::new_spanned(
+            contract_attrs[1],
+            "a kernel may have only one launch_contract",
+        ));
+    }
+    let Some(attr) = contract_attrs.first() else {
+        return Ok(None);
+    };
+    let args = attr.parse_args::<LaunchContractArgs>()?;
+
+    if let Some(param) = params.iter().find(|param| param.mutable_slice) {
+        return Err(syn::Error::new(
+            param.name.span(),
+            "contracted kernels cannot take `&mut [T]`; use `DisjointSlice<T, IndexSpace>` so the launch domain and per-thread write ownership are explicit",
+        ));
+    }
+    if let Some(block) = args.exact_block {
+        validate_dimensions_for_domain(block, args.domain, "block", attr.span())?;
+    }
+    if let Some(cluster) = cluster_dim {
+        validate_dimensions_for_domain(cluster, args.domain, "cluster", attr.span())?;
+    }
+
+    let launch_bounds = cuda_module_launch_bounds(attrs)?;
+    if args.exact_block.is_none() && launch_bounds.is_none() {
+        return Err(syn::Error::new_spanned(
+            attr,
+            "launch_contract requires either an exact `block = (x, y, z)` or #[launch_bounds(max_threads)]",
+        ));
+    }
+    let max_block_threads = launch_bounds.map(|bounds| bounds.max_threads);
+    if let (Some(exact), Some(maximum)) = (
+        args.exact_block,
+        max_block_threads
+            .as_ref()
+            .and_then(|maximum| maximum.literal_value),
+    ) {
+        let exact_threads = u64::from(exact.0)
+            .checked_mul(u64::from(exact.1))
+            .and_then(|xy| xy.checked_mul(u64::from(exact.2)))
+            .ok_or_else(|| {
+                syn::Error::new_spanned(attr, "launch_contract block thread count overflows u64")
+            })?;
+        if exact_threads > u64::from(maximum) {
+            return Err(syn::Error::new_spanned(
+                attr,
+                format!(
+                    "launch_contract block {exact:?} has {exact_threads} threads, exceeding #[launch_bounds({maximum})]"
+                ),
+            ));
+        }
+    }
+
+    let min_compute_capability = match cluster_dim {
+        Some(_) if args.min_compute_capability < (9, 0) => (9, 0),
+        _ => args.min_compute_capability,
+    };
+
+    validate_requires_relations(&args.requires, params)?;
+
+    Ok(Some(CudaModuleLaunchContract {
+        domain: args.domain,
+        u32_coordinates: args.u32_coordinates,
+        exact_block: args.exact_block,
+        max_block_threads,
+        dynamic_shared: args.dynamic_shared,
+        dynamic_shared_alignment: args.dynamic_shared_alignment,
+        min_compute_capability,
+        requires: args.requires,
+    }))
+}
+
+/// One-line reminder of the accepted `requires` grammar, appended to every
+/// rejection so authors see what is allowed and which parameters exist.
+fn requires_grammar_help(params: &[CudaModuleParam]) -> String {
+    let mut names = Vec::new();
+    for param in params {
+        let name = &param.name;
+        match param.marshal {
+            // Only scalars that can actually appear in a relation are
+            // offered; signed and non-integer scalars would be rejected.
+            CudaModuleParamMarshal::Scalar => {
+                if param.scalar_int == ScalarIntClass::Unsigned {
+                    names.push(format!("`{name}`"));
+                }
+            }
+            CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. }
+            | CudaModuleParamMarshal::WritableDeviceBuffer { .. }
+            | CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
+                names.push(format!("`{name}.len()`"));
+            }
+        }
+    }
+    let available = if names.is_empty() {
+        "(none of this kernel's parameters can appear in requires)".to_string()
+    } else {
+        names.join(", ")
+    };
+    format!(
+        "each requires relation is one comparison (`>=`, `>`, `<=`, `<`, `==`, `!=`) between \
+         expressions built from slice parameters as `<param>.len()`, unsigned integer scalar \
+         parameters (u8/u16/u32/u64/usize), integer literals, parentheses, and `+`, `-`, `*`; \
+         available operands: {available}"
+    )
+}
+
+/// Validates every `requires` relation against the kernel's own parameter
+/// list at expansion time, so a malformed relation is a compile error at the
+/// attribute instead of a surprise at launch.
+pub(crate) fn validate_requires_relations(
+    relations: &[Expr],
+    params: &[CudaModuleParam],
+) -> syn::Result<()> {
+    for relation in relations {
+        let Expr::Binary(binary) = relation else {
+            return Err(syn::Error::new_spanned(
+                relation,
+                format!(
+                    "requires relation must be a comparison between two expressions; {}",
+                    requires_grammar_help(params)
+                ),
+            ));
+        };
+        if !requires_comparison_op(&binary.op) {
+            return Err(syn::Error::new_spanned(
+                relation,
+                format!(
+                    "requires relation must compare with `>=`, `>`, `<=`, `<`, `==`, or `!=`; {}",
+                    requires_grammar_help(params)
+                ),
+            ));
+        }
+        validate_requires_operand(&binary.left, params)?;
+        validate_requires_operand(&binary.right, params)?;
+    }
+    Ok(())
+}
+
+fn requires_comparison_op(op: &syn::BinOp) -> bool {
+    matches!(
+        op,
+        syn::BinOp::Ge(_)
+            | syn::BinOp::Gt(_)
+            | syn::BinOp::Le(_)
+            | syn::BinOp::Lt(_)
+            | syn::BinOp::Eq(_)
+            | syn::BinOp::Ne(_)
+    )
+}
+
+fn requires_arithmetic_op(op: &syn::BinOp) -> bool {
+    matches!(
+        op,
+        syn::BinOp::Add(_) | syn::BinOp::Sub(_) | syn::BinOp::Mul(_)
+    )
+}
+
+/// Validates one side of a `requires` comparison: an arithmetic expression
+/// over `.len()` of slice-like parameters, unsigned integer scalar
+/// parameters, and integer literals.
+fn validate_requires_operand(expr: &Expr, params: &[CudaModuleParam]) -> syn::Result<()> {
+    match expr {
+        Expr::Lit(literal) => match &literal.lit {
+            syn::Lit::Int(int) => {
+                int.base10_parse::<u64>().map_err(|_| {
+                    syn::Error::new_spanned(literal, "integer literal in requires must fit in u64")
+                })?;
+                Ok(())
+            }
+            _ => Err(syn::Error::new_spanned(
+                literal,
+                format!(
+                    "only integer literals are allowed in requires; {}",
+                    requires_grammar_help(params)
+                ),
+            )),
+        },
+        Expr::Path(path) => {
+            let Some(ident) = path.path.get_ident() else {
+                return Err(syn::Error::new_spanned(
+                    path,
+                    format!(
+                        "paths in requires must be bare kernel parameter names; {}",
+                        requires_grammar_help(params)
+                    ),
+                ));
+            };
+            let Some(param) = params.iter().find(|param| param.name == *ident) else {
+                return Err(syn::Error::new_spanned(
+                    path,
+                    format!(
+                        "unknown identifier `{ident}` in requires: relations may only reference \
+                         this kernel's parameters; {}",
+                        requires_grammar_help(params)
+                    ),
+                ));
+            };
+            match param.marshal {
+                CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. }
+                | CudaModuleParamMarshal::WritableDeviceBuffer { .. }
+                | CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
+                    Err(syn::Error::new_spanned(
+                        path,
+                        format!(
+                            "slice parameter `{ident}` may only appear in requires as \
+                             `{ident}.len()`; {}",
+                            requires_grammar_help(params)
+                        ),
+                    ))
+                }
+                CudaModuleParamMarshal::Scalar => match param.scalar_int {
+                    ScalarIntClass::Unsigned => Ok(()),
+                    ScalarIntClass::Signed => Err(syn::Error::new_spanned(
+                        path,
+                        format!(
+                            "signed integer parameter `{ident}` is not supported in requires: \
+                             relations are evaluated in u64 and signed widening semantics are \
+                             not defined for v1; {}",
+                            requires_grammar_help(params)
+                        ),
+                    )),
+                    ScalarIntClass::Other => Err(syn::Error::new_spanned(
+                        path,
+                        format!(
+                            "parameter `{ident}` is not an unsigned integer scalar, so it \
+                             cannot appear in requires; {}",
+                            requires_grammar_help(params)
+                        ),
+                    )),
+                },
+            }
+        }
+        Expr::MethodCall(call) => {
+            if call.method != "len" {
+                return Err(syn::Error::new_spanned(
+                    &call.method,
+                    format!(
+                        "only the `.len()` method is allowed in requires; {}",
+                        requires_grammar_help(params)
+                    ),
+                ));
+            }
+            if !call.args.is_empty() || call.turbofish.is_some() {
+                return Err(syn::Error::new_spanned(
+                    call,
+                    "`.len()` in requires takes no arguments or turbofish",
+                ));
+            }
+            let receiver_ident = match &*call.receiver {
+                Expr::Path(path) => path.path.get_ident(),
+                _ => None,
+            };
+            let Some(ident) = receiver_ident else {
+                return Err(syn::Error::new_spanned(
+                    &call.receiver,
+                    format!(
+                        "`.len()` in requires must be called directly on a slice parameter; {}",
+                        requires_grammar_help(params)
+                    ),
+                ));
+            };
+            let Some(param) = params.iter().find(|param| param.name == *ident) else {
+                return Err(syn::Error::new_spanned(
+                    &call.receiver,
+                    format!(
+                        "unknown identifier `{ident}` in requires: relations may only reference \
+                         this kernel's parameters; {}",
+                        requires_grammar_help(params)
+                    ),
+                ));
+            };
+            match param.marshal {
+                CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. }
+                | CudaModuleParamMarshal::WritableDeviceBuffer { .. }
+                | CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => Ok(()),
+                CudaModuleParamMarshal::Scalar => Err(syn::Error::new_spanned(
+                    call,
+                    format!(
+                        "`.len()` in requires is only available on slice or DisjointSlice \
+                         parameters; `{ident}` is a scalar; {}",
+                        requires_grammar_help(params)
+                    ),
+                )),
+            }
+        }
+        Expr::Paren(paren) => validate_requires_operand(&paren.expr, params),
+        Expr::Group(group) => validate_requires_operand(&group.expr, params),
+        Expr::Binary(binary) if requires_arithmetic_op(&binary.op) => {
+            validate_requires_operand(&binary.left, params)?;
+            validate_requires_operand(&binary.right, params)
+        }
+        Expr::Binary(binary) if requires_comparison_op(&binary.op) => Err(syn::Error::new_spanned(
+            binary,
+            "nested comparisons are not supported in requires: each relation is exactly one \
+                 comparison; split it into multiple comma-separated relations instead",
+        )),
+        Expr::Binary(binary) => {
+            let op = &binary.op;
+            Err(syn::Error::new_spanned(
+                binary,
+                format!(
+                    "operator `{}` is not supported in requires; {}",
+                    quote! { #op },
+                    requires_grammar_help(params)
+                ),
+            ))
+        }
+        other => Err(syn::Error::new_spanned(
+            other,
+            format!(
+                "unsupported expression in requires; {}",
+                requires_grammar_help(params)
+            ),
+        )),
+    }
+}
+
+/// How a generated `requires` check reads the length of a slice-like
+/// parameter. Each checked launcher flavor sees slice arguments as a
+/// different host type.
+#[derive(Clone, Copy)]
+pub(super) enum RequiresLenAccess {
+    /// Sync prepared launcher: slice parameters are `&DeviceBuffer<T>` or
+    /// `&mut DeviceBuffer<T>`, so `.len()` resolves to the inherent method.
+    SyncBuffer,
+    /// Async prepared launcher: slice parameters are `&impl KernelSliceArg`
+    /// or `&mut impl KernelSliceArgMut`.
+    AsyncRef,
+    /// Owned async launcher: slice parameters are owned
+    /// `R: KernelSliceArg(Mut)` resources.
+    OwnedValue,
+}
+
+/// Renders a validated `requires` relation back to compact source text for
+/// error messages, e.g. `a.len() >= m * k`.
+fn render_requires_expr(expr: &Expr) -> String {
+    match expr {
+        Expr::Lit(literal) => {
+            let lit = &literal.lit;
+            quote!(#lit).to_string()
+        }
+        Expr::Path(path) => match path.path.get_ident() {
+            Some(ident) => ident.to_string(),
+            None => quote!(#path).to_string(),
+        },
+        Expr::MethodCall(call) => format!("{}.len()", render_requires_expr(&call.receiver)),
+        Expr::Paren(paren) => format!("({})", render_requires_expr(&paren.expr)),
+        Expr::Group(group) => render_requires_expr(&group.expr),
+        Expr::Binary(binary) => {
+            let op = &binary.op;
+            format!(
+                "{} {} {}",
+                render_requires_expr(&binary.left),
+                quote!(#op),
+                render_requires_expr(&binary.right)
+            )
+        }
+        other => quote!(#other).to_string(),
+    }
+}
+
+/// Generates the host-side size checks for a contracted kernel, or
+/// `None` when the contract declares no `requires` relations.
+///
+/// Every operand is widened to `u64` and every `+`/`-`/`*` goes through the
+/// corresponding checked operation, so a relation whose arithmetic leaves the
+/// `u64` range fails with `LaunchContractError::SizeRequirementOverflow` instead of wrapping. A
+/// relation that evaluates to false fails with `LaunchContractError::SizeRequirementViolated`
+/// carrying the relation's source text and both evaluated sides.
+pub(super) fn generate_requires_checks(
+    kernel: &CudaModuleKernel,
+    access: RequiresLenAccess,
+) -> Option<TokenStream2> {
+    let contract = kernel.launch_contract.as_ref()?;
+    if contract.requires.is_empty() {
+        return None;
+    }
+    let kernel_name = kernel.fn_name.to_string();
+    let lhs_binding = internal_ident("__cuda_oxide_requires_lhs");
+    let rhs_binding = internal_ident("__cuda_oxide_requires_rhs");
+    let checks = contract.requires.iter().map(|relation| {
+        let Expr::Binary(binary) = relation else {
+            unreachable!("requires relations are validated during contract construction");
+        };
+        let relation_text = render_requires_expr(relation);
+        let op = &binary.op;
+        let lhs = requires_operand_tokens(&binary.left, access, &kernel_name, &relation_text);
+        let rhs = requires_operand_tokens(&binary.right, access, &kernel_name, &relation_text);
+        quote! {
+            {
+                let #lhs_binding: u64 = #lhs;
+                let #rhs_binding: u64 = #rhs;
+                if !(#lhs_binding #op #rhs_binding) {
+                    return ::core::result::Result::Err(
+                        ::cuda_core::LaunchContractError::SizeRequirementViolated {
+                            kernel: #kernel_name,
+                            relation: #relation_text,
+                            lhs: #lhs_binding,
+                            rhs: #rhs_binding,
+                        },
+                    );
+                }
+            }
+        }
+    });
+    Some(quote! { #(#checks)* })
+}
+
+/// Transliterates one validated side of a `requires` comparison into a `u64`
+/// expression with checked arithmetic.
+fn requires_operand_tokens(
+    expr: &Expr,
+    access: RequiresLenAccess,
+    kernel_name: &str,
+    relation_text: &str,
+) -> TokenStream2 {
+    match expr {
+        Expr::Lit(literal) => {
+            let syn::Lit::Int(int) = &literal.lit else {
+                unreachable!("requires literals are validated during contract construction");
+            };
+            let value = int
+                .base10_parse::<u64>()
+                .expect("requires literals are validated during contract construction");
+            quote! { #value }
+        }
+        Expr::Path(path) => {
+            // Validated: a bare unsigned integer scalar parameter, so `as
+            // u64` is a lossless widening.
+            quote! { (#path as u64) }
+        }
+        Expr::MethodCall(call) => {
+            let receiver = &call.receiver;
+            match access {
+                RequiresLenAccess::SyncBuffer => quote! { (#receiver.len() as u64) },
+                RequiresLenAccess::AsyncRef => {
+                    quote! { (::cuda_host::KernelSliceArg::len(#receiver) as u64) }
+                }
+                RequiresLenAccess::OwnedValue => {
+                    quote! { (::cuda_host::KernelSliceArg::len(&#receiver) as u64) }
+                }
+            }
+        }
+        Expr::Paren(paren) => {
+            requires_operand_tokens(&paren.expr, access, kernel_name, relation_text)
+        }
+        Expr::Group(group) => {
+            requires_operand_tokens(&group.expr, access, kernel_name, relation_text)
+        }
+        Expr::Binary(binary) => {
+            let lhs = requires_operand_tokens(&binary.left, access, kernel_name, relation_text);
+            let rhs = requires_operand_tokens(&binary.right, access, kernel_name, relation_text);
+            let checked = match binary.op {
+                syn::BinOp::Add(_) => quote! { checked_add },
+                syn::BinOp::Sub(_) => quote! { checked_sub },
+                syn::BinOp::Mul(_) => quote! { checked_mul },
+                _ => unreachable!("requires operators are validated during contract construction"),
+            };
+            quote! {
+                #lhs.#checked(#rhs).ok_or(
+                    ::cuda_core::LaunchContractError::SizeRequirementOverflow {
+                        kernel: #kernel_name,
+                        relation: #relation_text,
+                    },
+                )?
+            }
+        }
+        _ => unreachable!("requires operands are validated during contract construction"),
+    }
+}
+
+#[derive(Clone)]
+struct ContractLaunchBounds {
+    max_threads: ConstU32Expr,
+}
+
+fn cuda_module_launch_bounds(
+    attrs: &[syn::Attribute],
+) -> syn::Result<Option<ContractLaunchBounds>> {
+    let matching: Vec<_> = attrs
+        .iter()
+        .filter(|attr| attr_path_ends_with(attr, "launch_bounds"))
+        .collect();
+    if matching.len() > 1 {
+        return Err(syn::Error::new_spanned(
+            matching[1],
+            "a kernel may have only one launch_bounds attribute",
+        ));
+    }
+    let Some(attr) = matching.first() else {
+        return Ok(None);
+    };
+    let args = attr.parse_args::<LaunchBoundsArgs>()?;
+    Ok(Some(ContractLaunchBounds {
+        max_threads: args.max_threads,
+    }))
+}
+
+fn validate_dimensions_for_domain(
+    dimensions: (u32, u32, u32),
+    domain: u8,
+    kind: &str,
+    span: proc_macro2::Span,
+) -> syn::Result<()> {
+    if dimensions.0 == 0 || dimensions.1 == 0 || dimensions.2 == 0 {
+        return Err(syn::Error::new(
+            span,
+            format!("launch_contract {kind} dimensions must be non-zero"),
+        ));
+    }
+    let outside_domain = match domain {
+        1 => dimensions.1 != 1 || dimensions.2 != 1,
+        2 => dimensions.2 != 1,
+        3 => false,
+        _ => unreachable!(),
+    };
+    if outside_domain {
+        return Err(syn::Error::new(
+            span,
+            format!(
+                "launch_contract {kind} dimensions {dimensions:?} exceed the declared {domain}D domain"
+            ),
+        ));
+    }
+    Ok(())
+}
+
+impl CudaModuleLaunchContract {
+    pub(super) fn cluster_tokens(
+        &self,
+        cluster_dim: Option<(u32, u32, u32)>,
+    ) -> Option<TokenStream2> {
+        cluster_dim.map(|(x, y, z)| quote! { .with_cluster((#x, #y, #z)) })
+    }
+}
diff --git a/crates/cuda-macros/src/cuda_module/launchers.rs b/crates/cuda-macros/src/cuda_module/launchers.rs
new file mode 100644
index 0000000000..d6e7814c50
--- /dev/null
+++ b/crates/cuda-macros/src/cuda_module/launchers.rs
@@ -0,0 +1,1208 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Generated host-side launch method families for `#[cuda_module]`
+//! kernels: sync, prepared, async, and owned-async.
+
+use crate::common::{cuda_module_async_lifetime, internal_ident};
+use crate::cuda_module::contract::{
+    DynamicSharedContract, RequiresLenAccess, generate_requires_checks,
+};
+use crate::cuda_module::model::{
+    CudaModuleKernel, CudaModuleParam, CudaModuleParamMarshal, cuda_module_kernel_marker_type,
+};
+use proc_macro2::TokenStream as TokenStream2;
+use quote::{format_ident, quote};
+use syn::{GenericParam, Ident};
+
+pub(super) fn generate_cuda_module_launch_contract_impl(
+    kernel: &CudaModuleKernel,
+) -> Option<TokenStream2> {
+    let contract = kernel.launch_contract.as_ref()?;
+    let cfg_attrs = &kernel.cfg_attrs;
+    let marker_ty = cuda_module_kernel_marker_type(kernel);
+    // `#[kernel]` erases lifetime-only generic lists because lifetimes do not
+    // create codegen instances. Mirror the marker that `#[kernel]` actually
+    // emits instead of applying erased lifetimes to a non-generic marker.
+    let generics = if kernel.is_generic {
+        kernel.generics.clone()
+    } else {
+        syn::Generics::default()
+    };
+    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
+    let config_ty = match contract.domain {
+        1 => quote! { ::cuda_core::LaunchConfig1D },
+        2 => quote! { ::cuda_core::LaunchConfig2D },
+        3 => quote! { ::cuda_core::LaunchConfig3D },
+        _ => unreachable!(),
+    };
+    let max_threads_binding = internal_ident("__cuda_oxide_max_threads");
+    let block = if let Some((x, y, z)) = contract.exact_block {
+        quote! { ::cuda_core::BlockRequirement::Exact((#x, #y, #z)) }
+    } else {
+        contract
+            .max_block_threads
+            .as_ref()
+            .expect("validated contract without exact block has launch bounds");
+        quote! { ::cuda_core::BlockRequirement::MaxThreads(#max_threads_binding) }
+    };
+    let launch_bounds_assertions = contract.max_block_threads.as_ref().map(|maximum| {
+        let maximum = &maximum.expr;
+        let exact_assertion = contract.exact_block.map(|(x, y, z)| {
+            let exact_threads = u128::from(x) * u128::from(y) * u128::from(z);
+            quote! {
+                assert!(
+                    #exact_threads <= (#max_threads_binding) as u128,
+                    "launch_contract exact block exceeds launch_bounds maximum threads",
+                );
+            }
+        });
+        quote! {
+            let #max_threads_binding: u32 = #maximum;
+            assert!(
+                #max_threads_binding > 0,
+                "launch_bounds maximum threads must be greater than zero",
+            );
+            #exact_assertion
+        }
+    });
+    let alignment = contract.dynamic_shared_alignment;
+    let dynamic_shared = match contract.dynamic_shared {
+        DynamicSharedContract::Exact(bytes) => quote! {
+            ::cuda_core::DynamicSharedMemoryRequirement::Exact {
+                bytes: #bytes,
+                min_alignment: #alignment,
+            }
+        },
+        DynamicSharedContract::Range {
+            min_bytes,
+            max_bytes,
+        } => quote! {
+            ::cuda_core::DynamicSharedMemoryRequirement::Range {
+                min_bytes: #min_bytes,
+                max_bytes: #max_bytes,
+                min_alignment: #alignment,
+            }
+        },
+    };
+    let kernel_name = kernel.fn_name.to_string();
+    let cluster = contract.cluster_tokens(kernel.cluster_dim);
+    let cooperative = kernel.cooperative.then(|| quote! { .with_cooperative() });
+    let (major, minor) = contract.min_compute_capability;
+    let compute_capability = ((major, minor) != (0, 0)).then(|| {
+        quote! { .with_min_compute_capability(#major, #minor) }
+    });
+    let coordinates = contract
+        .u32_coordinates
+        .then(|| quote! { .with_u32_coordinates() });
+
+    Some(quote! {
+        #(#cfg_attrs)*
+        impl #impl_generics ::cuda_core::KernelLaunchContract for #marker_ty
+        #where_clause
+        {
+            type Config = #config_ty;
+            const SPEC: ::cuda_core::LaunchContractSpec = {
+                #launch_bounds_assertions
+                ::cuda_core::LaunchContractSpec::new(#kernel_name, #block, #dynamic_shared)
+                    #cluster
+                    #cooperative
+                    #compute_capability
+                    #coordinates
+            };
+        }
+    })
+}
+
+pub(super) fn generate_cuda_module_prepare_launch_methods(
+    kernel: &CudaModuleKernel,
+) -> Option<TokenStream2> {
+    kernel.launch_contract.as_ref()?;
+    let vis = &kernel.vis;
+    let cfg_attrs = &kernel.cfg_attrs;
+    let fn_name = &kernel.fn_name;
+    let prepare_name = format_ident!("prepare_{}", fn_name);
+    let prepare_for_name = format_ident!("prepare_{}_for", fn_name);
+    let marker_ty = cuda_module_kernel_marker_type(kernel);
+    let generics = kernel.generics.clone();
+    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
+    let function_binding = cuda_module_function_binding(kernel);
+    let function = internal_ident("__cuda_oxide_function");
+    let config = internal_ident("__cuda_oxide_config");
+    let codegen_args = codegen_generic_arguments(&kernel.generics);
+    let turbofish = if codegen_args.is_empty() {
+        quote! {}
+    } else {
+        quote! { ::<#(#codegen_args),*> }
+    };
+    let type_params: Vec<_> = kernel
+        .generics
+        .params
+        .iter()
+        .filter_map(|param| match param {
+            GenericParam::Type(type_param) => Some(&type_param.ident),
+            GenericParam::Lifetime(_) | GenericParam::Const(_) => None,
+        })
+        .collect();
+    let witness_params = type_params.iter().enumerate().map(|(index, ty)| {
+        let name = internal_ident(&format!("__cuda_oxide_type_witness_{index}"));
+        quote! { #name: &#ty }
+    });
+    let prepare_for = (!type_params.is_empty()).then(|| {
+        quote! {
+            #(#cfg_attrs)*
+            #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+            #vis fn #prepare_for_name #impl_generics (
+                &self,
+                #(#witness_params,)*
+                #config: <#marker_ty as ::cuda_core::KernelLaunchContract>::Config,
+            ) -> ::core::result::Result<
+                ::cuda_core::PreparedLaunch<#marker_ty>,
+                ::cuda_core::LaunchContractError,
+            >
+            #where_clause
+            {
+                self.#prepare_name #turbofish (#config)
+            }
+        }
+    });
+
+    Some(quote! {
+        #(#cfg_attrs)*
+        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+        #vis fn #prepare_name #impl_generics (
+            &self,
+            #config: <#marker_ty as ::cuda_core::KernelLaunchContract>::Config,
+        ) -> ::core::result::Result<
+            ::cuda_core::PreparedLaunch<#marker_ty>,
+            ::cuda_core::LaunchContractError,
+        >
+        #where_clause
+        {
+            #function_binding
+            unsafe {
+                ::cuda_core::PreparedLaunch::<#marker_ty>::__prepare(
+                    #function.clone(),
+                    #config,
+                )
+            }
+        }
+
+        #prepare_for
+    })
+}
+
+pub(super) fn generate_cuda_module_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
+    if kernel.launch_contract.is_some() {
+        generate_cuda_module_prepared_launch_method(kernel)
+    } else {
+        generate_cuda_module_legacy_launch_method(kernel)
+    }
+}
+
+fn generate_cuda_module_legacy_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
+    let vis = &kernel.vis;
+    let cfg_attrs = &kernel.cfg_attrs;
+    let method_attrs = &kernel.method_attrs;
+    let fn_name = &kernel.fn_name;
+    let generics = cuda_module_launch_generics(kernel);
+    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
+    let params = kernel.params.iter().map(|param| {
+        let name = &param.name;
+        let host_ty = &param.sync_host_ty;
+        quote! { #name: #host_ty }
+    });
+    let arg_marshalling = kernel
+        .params
+        .iter()
+        .enumerate()
+        .map(|(index, param)| cuda_module_arg_marshalling(index, param));
+    let function_binding = cuda_module_function_binding(kernel);
+    let launch_call = cuda_module_launch_call(kernel);
+    let stream = internal_ident("__cuda_oxide_stream");
+    let config = internal_ident("__cuda_oxide_config");
+    let args = internal_ident("__cuda_oxide_args");
+
+    quote! {
+        #(#cfg_attrs)*
+        #(#method_attrs)*
+        #[doc = "Launches this kernel with an unverified raw launch configuration."]
+        #[doc = ""]
+        #[doc = "# Safety"]
+        #[doc = "The launch dimensions and resources must satisfy every indexing, memory-access, launch-bounds, and dynamic-shared-memory assumption made by the kernel. Dimensions not represented by the kernel's index model must not introduce overlapping or out-of-bounds accesses. The caller must also uphold any safety requirements documented on the kernel itself."]
+        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+        #vis unsafe fn #fn_name #impl_generics (
+            &self,
+            #stream: &::cuda_core::CudaStream,
+            #config: ::cuda_core::LaunchConfig,
+            #(#params),*
+        ) -> ::core::result::Result<(), ::cuda_core::DriverError>
+        #where_clause
+        {
+            #function_binding
+            let mut #args: ::std::vec::Vec<*mut ::std::ffi::c_void> = ::std::vec::Vec::new();
+            #(#arg_marshalling)*
+            #launch_call
+        }
+    }
+}
+
+fn generate_cuda_module_prepared_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
+    let vis = &kernel.vis;
+    let cfg_attrs = &kernel.cfg_attrs;
+    let method_attrs = &kernel.method_attrs;
+    let unsafety = &kernel.unsafety;
+    let fn_name = &kernel.fn_name;
+    let unchecked_name = format_ident!("{}_unchecked", fn_name);
+    let marker_ty = cuda_module_kernel_marker_type(kernel);
+    let generics = cuda_module_launch_generics(kernel);
+    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
+    let params: Vec<_> = kernel
+        .params
+        .iter()
+        .map(|param| {
+            let name = &param.name;
+            let host_ty = &param.sync_host_ty;
+            quote! { #name: #host_ty }
+        })
+        .collect();
+    let prepared_arg_marshalling = kernel
+        .params
+        .iter()
+        .enumerate()
+        .map(|(index, param)| cuda_module_arg_marshalling(index, param));
+    let unchecked_arg_marshalling = kernel
+        .params
+        .iter()
+        .enumerate()
+        .map(|(index, param)| cuda_module_arg_marshalling(index, param));
+    let unchecked_function_binding = cuda_module_function_binding(kernel);
+    let launch_call = cuda_module_launch_call(kernel);
+    let unchecked_launch_call = cuda_module_launch_call(kernel);
+    let requires_checks = generate_requires_checks(kernel, RequiresLenAccess::SyncBuffer);
+    let stream = internal_ident("__cuda_oxide_stream");
+    let prepared = internal_ident("__cuda_oxide_prepared");
+    let function = internal_ident("__cuda_oxide_function");
+    let config = internal_ident("__cuda_oxide_config");
+    let args = internal_ident("__cuda_oxide_args");
+
+    quote! {
+        #(#cfg_attrs)*
+        #(#method_attrs)*
+        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+        #vis #unsafety fn #fn_name #impl_generics (
+            &self,
+            #stream: &::cuda_core::CudaStream,
+            #prepared: &::cuda_core::PreparedLaunch<#marker_ty>,
+            #(#params),*
+        ) -> ::core::result::Result<(), ::cuda_core::LaunchContractError>
+        #where_clause
+        {
+            #prepared.validate_stream(#stream)?;
+            #requires_checks
+            let #function = #prepared.function();
+            let #config = #prepared.__raw_config();
+            let mut #args: ::std::vec::Vec<*mut ::std::ffi::c_void> = ::std::vec::Vec::new();
+            #(#prepared_arg_marshalling)*
+            (#launch_call).map_err(::cuda_core::LaunchContractError::from)
+        }
+
+        #(#cfg_attrs)*
+        #[doc = "Unchecked launch escape hatch for this contracted kernel."]
+        #[doc = ""]
+        #[doc = "# Safety"]
+        #[doc = "The caller must uphold the kernel's declared geometry, resource, capability, and context contract, including any `requires` size requirements. This escape hatch intentionally skips the contract's checks, so an undersized buffer is not caught before the kernel runs."]
+        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+        #vis unsafe fn #unchecked_name #impl_generics (
+            &self,
+            #stream: &::cuda_core::CudaStream,
+            #config: ::cuda_core::LaunchConfig,
+            #(#params),*
+        ) -> ::core::result::Result<(), ::cuda_core::DriverError>
+        #where_clause
+        {
+            #unchecked_function_binding
+            let mut #args: ::std::vec::Vec<*mut ::std::ffi::c_void> = ::std::vec::Vec::new();
+            #(#unchecked_arg_marshalling)*
+            #unchecked_launch_call
+        }
+    }
+}
+
+pub(super) fn generate_cuda_module_async_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
+    if kernel.launch_contract.is_some() {
+        generate_cuda_module_prepared_async_launch_method(kernel)
+    } else {
+        generate_cuda_module_legacy_async_launch_method(kernel)
+    }
+}
+
+fn generate_cuda_module_legacy_async_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
+    let vis = &kernel.vis;
+    let cfg_attrs = &kernel.cfg_attrs;
+    let method_attrs = &kernel.method_attrs;
+    let fn_name = format_ident!("{}_async", kernel.fn_name);
+    let generics = cuda_module_async_launch_generics(kernel);
+    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
+    let params = kernel.params.iter().map(|param| {
+        let name = &param.name;
+        let host_ty = &param.async_host_ty;
+        quote! { #name: #host_ty }
+    });
+    let arg_marshalling = kernel.params.iter().map(cuda_module_async_arg_marshalling);
+    let function_binding = cuda_module_function_binding(kernel);
+    let config = internal_ident("__cuda_oxide_config");
+    let function = internal_ident("__cuda_oxide_function");
+    let launch = internal_ident("__cuda_oxide_launch");
+    let async_lifetime = cuda_module_async_lifetime();
+    let cluster_dim = kernel.cluster_dim.map(|(x, y, z)| quote! { (#x, #y, #z) });
+    let set_cluster_dim = cluster_dim.map(|cluster_dim| {
+        quote! {
+            ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim);
+        }
+    });
+    let set_cooperative = kernel.cooperative.then(|| {
+        quote! {
+            ::cuda_host::set_async_kernel_cooperative(&mut #launch, true);
+        }
+    });
+
+    quote! {
+        #(#cfg_attrs)*
+        #(#method_attrs)*
+        #[doc = "Builds a lazy async launch from an unverified raw launch configuration."]
+        #[doc = ""]
+        #[doc = "# Safety"]
+        #[doc = "Before scheduling the returned operation, the launch dimensions and resources must satisfy every indexing, memory-access, launch-bounds, and dynamic-shared-memory assumption made by the kernel. Dimensions not represented by the kernel's index model must not introduce overlapping or out-of-bounds accesses. The caller must also uphold any safety requirements documented on the kernel itself."]
+        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+        #vis unsafe fn #fn_name #impl_generics (
+            &self,
+            #config: ::cuda_core::LaunchConfig,
+            #(#params),*
+        ) -> ::core::result::Result<::cuda_host::AsyncKernelLaunch<#async_lifetime>, ::cuda_core::DriverError>
+        #where_clause
+        {
+            #function_binding
+            let mut #launch = ::cuda_host::new_async_kernel_launch_builder(#function.clone());
+            #set_cluster_dim
+            #set_cooperative
+            #(#arg_marshalling)*
+            // SAFETY: this method is unsafe and its caller must uphold the raw
+            // launch configuration contract documented above.
+            Ok(unsafe { #launch.finalize_unchecked(#config) })
+        }
+    }
+}
+
+fn generate_cuda_module_prepared_async_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
+    let vis = &kernel.vis;
+    let cfg_attrs = &kernel.cfg_attrs;
+    let method_attrs = &kernel.method_attrs;
+    let unsafety = &kernel.unsafety;
+    let fn_name = format_ident!("{}_async", kernel.fn_name);
+    let unchecked_name = format_ident!("{}_async_unchecked", kernel.fn_name);
+    let marker_ty = cuda_module_kernel_marker_type(kernel);
+    let generics = cuda_module_async_launch_generics(kernel);
+    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
+    let params: Vec<_> = kernel
+        .params
+        .iter()
+        .map(|param| {
+            let name = &param.name;
+            let host_ty = &param.async_host_ty;
+            quote! { #name: #host_ty }
+        })
+        .collect();
+    let prepared_marshalling = kernel.params.iter().map(cuda_module_async_arg_marshalling);
+    let unchecked_marshalling = kernel.params.iter().map(cuda_module_async_arg_marshalling);
+    let unchecked_function_binding = cuda_module_function_binding(kernel);
+    let prepared = internal_ident("__cuda_oxide_prepared");
+    let config = internal_ident("__cuda_oxide_config");
+    let function = internal_ident("__cuda_oxide_function");
+    let launch = internal_ident("__cuda_oxide_launch");
+    let async_lifetime = cuda_module_async_lifetime();
+    let cluster_dim = kernel.cluster_dim.map(|(x, y, z)| quote! { (#x, #y, #z) });
+    let prepared_cluster = cluster_dim.as_ref().map(|cluster_dim| {
+        quote! { ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim); }
+    });
+    let unchecked_cluster = cluster_dim.as_ref().map(|cluster_dim| {
+        quote! { ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim); }
+    });
+    let prepared_cooperative = kernel.cooperative.then(|| {
+        quote! { ::cuda_host::set_async_kernel_cooperative(&mut #launch, true); }
+    });
+    let unchecked_cooperative = kernel.cooperative.then(|| {
+        quote! { ::cuda_host::set_async_kernel_cooperative(&mut #launch, true); }
+    });
+    let requires_checks = generate_requires_checks(kernel, RequiresLenAccess::AsyncRef);
+    let launch_ty = quote! {
+        ::cuda_host::PreparedAsyncKernelLaunch<#async_lifetime, #marker_ty>
+    };
+    let final_value = quote! {
+        unsafe {
+            ::cuda_host::new_prepared_async_kernel_launch(
+                #launch,
+                (*#prepared).clone(),
+            )
+        }
+    };
+    // Size requirements are evaluated eagerly, before the launch is
+    // enqueued, so a violated relation must surface as a typed error. Only
+    // contracts that declare `requires` pay for the `Result` wrapper.
+    let (return_ty, final_expr, requires_doc) = if requires_checks.is_some() {
+        (
+            quote! {
+                ::core::result::Result<#launch_ty, ::cuda_core::LaunchContractError>
+            },
+            quote! { ::core::result::Result::Ok(#final_value) },
+            Some(quote! {
+                #[doc = ""]
+                #[doc = "Returns a `LaunchContractError` without enqueueing anything if a declared `requires` size requirement does not hold for the supplied arguments."]
+            }),
+        )
+    } else {
+        (launch_ty, final_value, None)
+    };
+
+    quote! {
+        #(#cfg_attrs)*
+        #(#method_attrs)*
+        #requires_doc
+        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+        #vis #unsafety fn #fn_name #impl_generics (
+            &self,
+            #prepared: &::cuda_core::PreparedLaunch<#marker_ty>,
+            #(#params),*
+        ) -> #return_ty
+        #where_clause
+        {
+            #requires_checks
+            let mut #launch =
+                ::cuda_host::new_async_kernel_launch_builder(#prepared.function().clone());
+            #prepared_cluster
+            #prepared_cooperative
+            #(#prepared_marshalling)*
+            // SAFETY: PreparedLaunch validated this kernel-branded config and
+            // the builder has not exposed a way to mutate it after finalization.
+            let #launch = unsafe {
+                #launch.finalize_unchecked(#prepared.__raw_config())
+            };
+            #final_expr
+        }
+
+        #(#cfg_attrs)*
+        #[doc = "Unchecked async launch escape hatch for this contracted kernel."]
+        #[doc = ""]
+        #[doc = "# Safety"]
+        #[doc = "The caller must uphold the kernel's declared geometry, resource, capability, and context contract when the returned operation is scheduled, including any `requires` size requirements. This escape hatch intentionally skips the contract's checks, so an undersized buffer is not caught before the kernel runs."]
+        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+        #vis unsafe fn #unchecked_name #impl_generics (
+            &self,
+            #config: ::cuda_core::LaunchConfig,
+            #(#params),*
+        ) -> ::core::result::Result<
+            ::cuda_host::AsyncKernelLaunch<#async_lifetime>,
+            ::cuda_core::DriverError,
+        >
+        #where_clause
+        {
+            #unchecked_function_binding
+            let mut #launch =
+                ::cuda_host::new_async_kernel_launch_builder(#function.clone());
+            #unchecked_cluster
+            #unchecked_cooperative
+            #(#unchecked_marshalling)*
+            // SAFETY: this method is unsafe and its caller must uphold the
+            // contracted kernel's raw launch requirements documented above.
+            Ok(unsafe { #launch.finalize_unchecked(#config) })
+        }
+    }
+}
+
+pub(super) fn generate_cuda_module_owned_async_launch_method(
+    kernel: &CudaModuleKernel,
+) -> TokenStream2 {
+    if kernel.launch_contract.is_some() {
+        generate_cuda_module_prepared_owned_async_launch_method(kernel)
+    } else {
+        generate_cuda_module_legacy_owned_async_launch_method(kernel)
+    }
+}
+
+fn generate_cuda_module_legacy_owned_async_launch_method(
+    kernel: &CudaModuleKernel,
+) -> TokenStream2 {
+    let vis = &kernel.vis;
+    let cfg_attrs = &kernel.cfg_attrs;
+    let method_attrs = &kernel.method_attrs;
+    let fn_name = format_ident!("{}_async_owned", kernel.fn_name);
+    let resources = cuda_module_owned_resource_params(kernel);
+    let generics = cuda_module_owned_async_launch_generics(kernel, &resources);
+    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
+    let params = kernel.params.iter().enumerate().map(|(index, param)| {
+        let name = &param.name;
+        match &param.marshal {
+            CudaModuleParamMarshal::Scalar => {
+                let host_ty = &param.async_host_ty;
+                quote! { #name: #host_ty }
+            }
+            CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. } => {
+                let resource_ty = cuda_module_owned_resource_type(index);
+                quote! { #name: #resource_ty }
+            }
+            CudaModuleParamMarshal::WritableDeviceBuffer { .. } => {
+                let resource_ty = cuda_module_owned_resource_type(index);
+                quote! { mut #name: #resource_ty }
+            }
+            // The owned resource carries the buffer; `RowWidthOwned` adds the
+            // row width the kernel will index it by.
+            CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
+                let resource_ty = cuda_module_owned_resource_type(index);
+                quote! { mut #name: ::cuda_host::RowWidthOwned<#resource_ty> }
+            }
+        }
+    });
+    let arg_marshalling = kernel
+        .params
+        .iter()
+        .map(cuda_module_owned_async_arg_marshalling);
+    let function_binding = cuda_module_function_binding(kernel);
+    let config = internal_ident("__cuda_oxide_config");
+    let function = internal_ident("__cuda_oxide_function");
+    let launch = internal_ident("__cuda_oxide_launch");
+    let cluster_dim = kernel.cluster_dim.map(|(x, y, z)| quote! { (#x, #y, #z) });
+    let set_cluster_dim = cluster_dim.map(|cluster_dim| {
+        quote! {
+            ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim);
+        }
+    });
+    let set_cooperative = kernel.cooperative.then(|| {
+        quote! {
+            ::cuda_host::set_async_kernel_cooperative(&mut #launch, true);
+        }
+    });
+    let resources_ty = cuda_module_owned_resources_ty(&resources);
+    let resource_names = resources.iter().map(|(_, name, _, _, _)| name);
+    let resources_expr = if resources.is_empty() {
+        quote! { () }
+    } else {
+        quote! { (#(#resource_names),*) }
+    };
+
+    quote! {
+        #(#cfg_attrs)*
+        #(#method_attrs)*
+        #[doc = "Builds a lazy owned async launch from an unverified raw launch configuration."]
+        #[doc = ""]
+        #[doc = "# Safety"]
+        #[doc = "Before scheduling the returned operation, the launch dimensions and resources must satisfy every indexing, memory-access, launch-bounds, and dynamic-shared-memory assumption made by the kernel. Dimensions not represented by the kernel's index model must not introduce overlapping or out-of-bounds accesses. The caller must also uphold any safety requirements documented on the kernel itself."]
+        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+        #vis unsafe fn #fn_name #impl_generics (
+            &self,
+            #config: ::cuda_core::LaunchConfig,
+            #(#params),*
+        ) -> ::core::result::Result<::cuda_host::OwnedAsyncKernelLaunch<#resources_ty>, ::cuda_core::DriverError>
+        #where_clause
+        {
+            #function_binding
+            let mut #launch =
+                ::cuda_host::new_async_kernel_launch_builder(#function.clone());
+            #set_cluster_dim
+            #set_cooperative
+            #(#arg_marshalling)*
+            // SAFETY: this method is unsafe and its caller must uphold the raw
+            // launch configuration contract documented above.
+            let #launch: ::cuda_host::AsyncKernelLaunch<'static> =
+                unsafe { #launch.finalize_unchecked(#config) };
+            Ok(::cuda_host::new_owned_async_kernel_launch(#launch, #resources_expr))
+        }
+    }
+}
+
+fn generate_cuda_module_prepared_owned_async_launch_method(
+    kernel: &CudaModuleKernel,
+) -> TokenStream2 {
+    let vis = &kernel.vis;
+    let cfg_attrs = &kernel.cfg_attrs;
+    let method_attrs = &kernel.method_attrs;
+    let unsafety = &kernel.unsafety;
+    let fn_name = format_ident!("{}_async_owned", kernel.fn_name);
+    let unchecked_name = format_ident!("{}_async_owned_unchecked", kernel.fn_name);
+    let marker_ty = cuda_module_kernel_marker_type(kernel);
+    let resources = cuda_module_owned_resource_params(kernel);
+    let generics = cuda_module_owned_async_launch_generics(kernel, &resources);
+    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
+    let params: Vec<_> = kernel
+        .params
+        .iter()
+        .enumerate()
+        .map(|(index, param)| {
+            let name = &param.name;
+            match &param.marshal {
+                CudaModuleParamMarshal::Scalar => {
+                    let host_ty = &param.async_host_ty;
+                    quote! { #name: #host_ty }
+                }
+                CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. } => {
+                    let resource_ty = cuda_module_owned_resource_type(index);
+                    quote! { #name: #resource_ty }
+                }
+                CudaModuleParamMarshal::WritableDeviceBuffer { .. } => {
+                    let resource_ty = cuda_module_owned_resource_type(index);
+                    quote! { mut #name: #resource_ty }
+                }
+                // The owned resource carries the buffer; `RowWidthOwned` adds
+                // the row width the kernel will index it by.
+                CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
+                    let resource_ty = cuda_module_owned_resource_type(index);
+                    quote! { mut #name: ::cuda_host::RowWidthOwned<#resource_ty> }
+                }
+            }
+        })
+        .collect();
+    let prepared_marshalling = kernel
+        .params
+        .iter()
+        .map(cuda_module_owned_async_arg_marshalling);
+    let unchecked_marshalling = kernel
+        .params
+        .iter()
+        .map(cuda_module_owned_async_arg_marshalling);
+    let unchecked_function_binding = cuda_module_function_binding(kernel);
+    let prepared = internal_ident("__cuda_oxide_prepared");
+    let config = internal_ident("__cuda_oxide_config");
+    let function = internal_ident("__cuda_oxide_function");
+    let launch = internal_ident("__cuda_oxide_launch");
+    let owned = internal_ident("__cuda_oxide_owned");
+    let cluster_dim = kernel.cluster_dim.map(|(x, y, z)| quote! { (#x, #y, #z) });
+    let prepared_cluster = cluster_dim.as_ref().map(|cluster_dim| {
+        quote! { ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim); }
+    });
+    let unchecked_cluster = cluster_dim.as_ref().map(|cluster_dim| {
+        quote! { ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim); }
+    });
+    let prepared_cooperative = kernel.cooperative.then(|| {
+        quote! { ::cuda_host::set_async_kernel_cooperative(&mut #launch, true); }
+    });
+    let unchecked_cooperative = kernel.cooperative.then(|| {
+        quote! { ::cuda_host::set_async_kernel_cooperative(&mut #launch, true); }
+    });
+    let resources_ty = cuda_module_owned_resources_ty(&resources);
+    let prepared_resource_names = resources.iter().map(|(_, name, _, _, _)| name);
+    let unchecked_resource_names = resources.iter().map(|(_, name, _, _, _)| name);
+    let prepared_resources_expr = if resources.is_empty() {
+        quote! { () }
+    } else {
+        quote! { (#(#prepared_resource_names),*) }
+    };
+    let unchecked_resources_expr = if resources.is_empty() {
+        quote! { () }
+    } else {
+        quote! { (#(#unchecked_resource_names),*) }
+    };
+    let requires_checks = generate_requires_checks(kernel, RequiresLenAccess::OwnedValue);
+    let launch_ty = quote! {
+        ::cuda_host::PreparedOwnedAsyncKernelLaunch<#resources_ty, #marker_ty>
+    };
+    let final_value = quote! {
+        unsafe {
+            ::cuda_host::new_prepared_owned_async_kernel_launch(
+                #owned,
+                (*#prepared).clone(),
+            )
+        }
+    };
+    // Same policy as the borrowed async launcher: `requires` relations are
+    // checked eagerly, before any resource is moved into the launch, and a
+    // violation surfaces as a typed error instead of an enqueued fault.
+    let (return_ty, final_expr, requires_doc) = if requires_checks.is_some() {
+        (
+            quote! {
+                ::core::result::Result<#launch_ty, ::cuda_core::LaunchContractError>
+            },
+            quote! { ::core::result::Result::Ok(#final_value) },
+            Some(quote! {
+                #[doc = ""]
+                #[doc = "Returns a `LaunchContractError` without enqueueing anything if a declared `requires` size requirement does not hold for the supplied arguments."]
+            }),
+        )
+    } else {
+        (launch_ty, final_value, None)
+    };
+
+    quote! {
+        #(#cfg_attrs)*
+        #(#method_attrs)*
+        #requires_doc
+        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+        #vis #unsafety fn #fn_name #impl_generics (
+            &self,
+            #prepared: &::cuda_core::PreparedLaunch<#marker_ty>,
+            #(#params),*
+        ) -> #return_ty
+        #where_clause
+        {
+            #requires_checks
+            let mut #launch =
+                ::cuda_host::new_async_kernel_launch_builder(#prepared.function().clone());
+            #prepared_cluster
+            #prepared_cooperative
+            #(#prepared_marshalling)*
+            // SAFETY: PreparedLaunch validated this kernel-branded config and
+            // the builder has not exposed a way to mutate it after finalization.
+            let #launch: ::cuda_host::AsyncKernelLaunch<'static> = unsafe {
+                #launch.finalize_unchecked(#prepared.__raw_config())
+            };
+            let #owned =
+                ::cuda_host::new_owned_async_kernel_launch(#launch, #prepared_resources_expr);
+            #final_expr
+        }
+
+        #(#cfg_attrs)*
+        #[doc = "Unchecked owned-async launch escape hatch for this contracted kernel."]
+        #[doc = ""]
+        #[doc = "# Safety"]
+        #[doc = "The caller must uphold the kernel's declared geometry, resource, capability, and context contract when the returned operation is scheduled, including any `requires` size requirements. This escape hatch intentionally skips the contract's checks, so an undersized buffer is not caught before the kernel runs."]
+        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
+        #vis unsafe fn #unchecked_name #impl_generics (
+            &self,
+            #config: ::cuda_core::LaunchConfig,
+            #(#params),*
+        ) -> ::core::result::Result<
+            ::cuda_host::OwnedAsyncKernelLaunch<#resources_ty>,
+            ::cuda_core::DriverError,
+        >
+        #where_clause
+        {
+            #unchecked_function_binding
+            let mut #launch =
+                ::cuda_host::new_async_kernel_launch_builder(#function.clone());
+            #unchecked_cluster
+            #unchecked_cooperative
+            #(#unchecked_marshalling)*
+            // SAFETY: this method is unsafe and its caller must uphold the
+            // contracted kernel's raw launch requirements documented above.
+            let #launch: ::cuda_host::AsyncKernelLaunch<'static> =
+                unsafe { #launch.finalize_unchecked(#config) };
+            Ok(::cuda_host::new_owned_async_kernel_launch(
+                #launch,
+                #unchecked_resources_expr,
+            ))
+        }
+    }
+}
+
+fn cuda_module_launch_generics(kernel: &CudaModuleKernel) -> syn::Generics {
+    let mut generics = kernel.generics.clone();
+    for param in &kernel.params {
+        if matches!(param.marshal, CudaModuleParamMarshal::Scalar) {
+            let host_ty = &param.sync_host_ty;
+            generics
+                .make_where_clause()
+                .predicates
+                .push(syn::parse_quote! { #host_ty: ::cuda_host::KernelScalar });
+        }
+    }
+    generics
+}
+
+fn cuda_module_owned_async_launch_generics(
+    kernel: &CudaModuleKernel,
+    resources: &[(usize, Ident, TokenStream2, bool, bool)],
+) -> syn::Generics {
+    let mut generics = kernel.generics.clone();
+    for (index, _, elem_ty, writable, _) in resources {
+        let resource_ty = cuda_module_owned_resource_type(*index);
+        generics.params.push(syn::parse_quote! { #resource_ty });
+        let predicate: syn::WherePredicate = if *writable {
+            syn::parse_quote! {
+                #resource_ty: ::cuda_host::KernelSliceArgMut<Elem = #elem_ty> + Send + 'static
+            }
+        } else {
+            syn::parse_quote! {
+                #resource_ty: ::cuda_host::KernelSliceArg<Elem = #elem_ty> + Send + 'static
+            }
+        };
+        generics.make_where_clause().predicates.push(predicate);
+    }
+    for param in &kernel.params {
+        if matches!(param.marshal, CudaModuleParamMarshal::Scalar) {
+            let host_ty = &param.async_host_ty;
+            generics
+                .make_where_clause()
+                .predicates
+                .push(syn::parse_quote! { #host_ty: ::cuda_host::KernelScalar + 'static });
+        }
+    }
+    generics
+}
+
+fn cuda_module_async_launch_generics(kernel: &CudaModuleKernel) -> syn::Generics {
+    let mut generics = kernel.generics.clone();
+    let async_lifetime = cuda_module_async_lifetime();
+    let lifetime_param = syn::LifetimeParam::new(async_lifetime.clone());
+    generics
+        .params
+        .insert(0, syn::GenericParam::Lifetime(lifetime_param));
+    for param in &kernel.params {
+        if matches!(param.marshal, CudaModuleParamMarshal::Scalar) {
+            let host_ty = &param.async_host_ty;
+            generics
+                .make_where_clause()
+                .predicates
+                .push(syn::parse_quote! { #host_ty: ::cuda_host::KernelScalar + #async_lifetime });
+        }
+    }
+    generics
+}
+
+fn cuda_module_owned_resource_params(
+    kernel: &CudaModuleKernel,
+) -> Vec<(usize, Ident, TokenStream2, bool, bool)> {
+    kernel
+        .params
+        .iter()
+        .enumerate()
+        .filter_map(|(index, param)| match &param.marshal {
+            CudaModuleParamMarshal::Scalar => None,
+            CudaModuleParamMarshal::ReadOnlyDeviceBuffer { elem_ty } => {
+                Some((index, param.name.clone(), elem_ty.clone(), false, false))
+            }
+            CudaModuleParamMarshal::WritableDeviceBuffer { elem_ty } => {
+                Some((index, param.name.clone(), elem_ty.clone(), true, false))
+            }
+            // A row-width slice still owns a buffer resource; the width
+            // rides beside it in `RowWidthOwned`.
+            CudaModuleParamMarshal::RowWidthDeviceBuffer { elem_ty } => {
+                Some((index, param.name.clone(), elem_ty.clone(), true, true))
+            }
+        })
+        .collect()
+}
+
+fn cuda_module_owned_resource_type(index: usize) -> Ident {
+    internal_ident(&format!("__CudaModuleArg{index}"))
+}
+
+fn cuda_module_owned_resources_ty(
+    resources: &[(usize, Ident, TokenStream2, bool, bool)],
+) -> TokenStream2 {
+    if resources.is_empty() {
+        quote! { () }
+    } else {
+        let resource_tys = resources.iter().map(|(index, _, _, _, has_row_width)| {
+            let resource_ty = cuda_module_owned_resource_type(*index);
+            if *has_row_width {
+                quote! { ::cuda_host::RowWidthOwned<#resource_ty> }
+            } else {
+                quote! { #resource_ty }
+            }
+        });
+        quote! { (#(#resource_tys),*) }
+    }
+}
+
+fn cuda_module_arg_marshalling(index: usize, param: &CudaModuleParam) -> TokenStream2 {
+    let name = &param.name;
+    let args = internal_ident("__cuda_oxide_args");
+    let value_name = internal_ident(&format!("__cuda_oxide_arg_{index}"));
+    match param.marshal {
+        CudaModuleParamMarshal::Scalar => {
+            quote! {
+                let mut #value_name = #name;
+                ::cuda_host::push_kernel_scalar(&mut #args, &mut #value_name);
+            }
+        }
+        CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. } => {
+            let ptr_name = internal_ident(&format!("__cuda_oxide_arg_{index}_ptr"));
+            let len_name = internal_ident(&format!("__cuda_oxide_arg_{index}_len"));
+            quote! {
+                let (mut #ptr_name, mut #len_name) =
+                    ::cuda_host::read_only_device_buffer_arg(#name);
+                ::cuda_host::push_kernel_device_slice(
+                    &mut #args,
+                    &mut #ptr_name,
+                    &mut #len_name,
+                );
+            }
+        }
+        CudaModuleParamMarshal::WritableDeviceBuffer { .. } => {
+            let ptr_name = internal_ident(&format!("__cuda_oxide_arg_{index}_ptr"));
+            let len_name = internal_ident(&format!("__cuda_oxide_arg_{index}_len"));
+            quote! {
+                let (mut #ptr_name, mut #len_name) =
+                    ::cuda_host::writable_device_buffer_arg(#name);
+                ::cuda_host::push_kernel_device_slice(
+                    &mut #args,
+                    &mut #ptr_name,
+                    &mut #len_name,
+                );
+            }
+        }
+        CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
+            let ptr_name = internal_ident(&format!("__cuda_oxide_arg_{index}_ptr"));
+            let len_name = internal_ident(&format!("__cuda_oxide_arg_{index}_len"));
+            let width_name = internal_ident(&format!("__cuda_oxide_arg_{index}_row_width"));
+            quote! {
+                let (mut #ptr_name, mut #len_name, mut #width_name) =
+                    ::cuda_host::row_width_device_buffer_arg(#name);
+                ::cuda_host::push_kernel_row_width_device_slice(
+                    &mut #args,
+                    &mut #ptr_name,
+                    &mut #len_name,
+                    &mut #width_name,
+                );
+            }
+        }
+    }
+}
+
+fn cuda_module_owned_async_arg_marshalling(param: &CudaModuleParam) -> TokenStream2 {
+    let name = &param.name;
+    let launch = internal_ident("__cuda_oxide_launch");
+    match param.marshal {
+        CudaModuleParamMarshal::Scalar => {
+            quote! {
+                ::cuda_host::push_async_kernel_scalar(&mut #launch, #name);
+            }
+        }
+        CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. } => {
+            quote! {
+                ::cuda_host::push_async_read_only_device_slice(&mut #launch, &#name);
+            }
+        }
+        CudaModuleParamMarshal::WritableDeviceBuffer { .. } => {
+            quote! {
+                ::cuda_host::push_async_writable_device_slice(&mut #launch, &mut #name);
+            }
+        }
+        CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
+            quote! {
+                ::cuda_host::push_async_owned_row_width_device_slice(&mut #launch, &mut #name);
+            }
+        }
+    }
+}
+
+fn cuda_module_async_arg_marshalling(param: &CudaModuleParam) -> TokenStream2 {
+    let name = &param.name;
+    let launch = internal_ident("__cuda_oxide_launch");
+    match param.marshal {
+        CudaModuleParamMarshal::Scalar => {
+            quote! {
+                ::cuda_host::push_async_kernel_scalar(&mut #launch, #name);
+            }
+        }
+        CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. } => {
+            quote! {
+                ::cuda_host::push_async_read_only_device_slice(&mut #launch, #name);
+            }
+        }
+        CudaModuleParamMarshal::WritableDeviceBuffer { .. } => {
+            quote! {
+                ::cuda_host::push_async_writable_device_slice(&mut #launch, #name);
+            }
+        }
+        CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
+            quote! {
+                ::cuda_host::push_async_row_width_device_slice(&mut #launch, #name);
+            }
+        }
+    }
+}
+
+fn cuda_module_function_binding(kernel: &CudaModuleKernel) -> TokenStream2 {
+    let function = internal_ident("__cuda_oxide_function");
+    if kernel.is_generic {
+        let ptx_name_fn = format_ident!("{}_ptx_name", kernel.fn_name);
+        let codegen_args = codegen_generic_arguments(&kernel.generics);
+        let turbofish = if codegen_args.is_empty() {
+            quote! {}
+        } else {
+            quote! { ::<#(#codegen_args),*> }
+        };
+        let ptx_name = internal_ident("__cuda_oxide_ptx_name");
+        let function_storage = internal_ident("__cuda_oxide_function_storage");
+        let cache = internal_ident("__cuda_oxide_function_cache");
+        quote! {
+            let #ptx_name = #ptx_name_fn #turbofish ();
+            let #function_storage = {
+                let mut #cache = self
+                    .__generic_functions
+                    .lock()
+                    .expect("cuda_module generic function cache poisoned");
+                if let Some(#function) = #cache.get(#ptx_name) {
+                    #function.clone()
+                } else {
+                    let #function = self.__module.load_function(#ptx_name)?;
+                    #cache.insert(#ptx_name, #function.clone());
+                    #function
+                }
+            };
+            let #function = &#function_storage;
+        }
+    } else {
+        let field = cuda_module_function_field(&kernel.fn_name);
+        quote! {
+            let #function = &self.#field;
+        }
+    }
+}
+
+fn cuda_module_launch_call(kernel: &CudaModuleKernel) -> TokenStream2 {
+    let function = internal_ident("__cuda_oxide_function");
+    let stream = internal_ident("__cuda_oxide_stream");
+    let config = internal_ident("__cuda_oxide_config");
+    let args = internal_ident("__cuda_oxide_args");
+    let cluster_dim = kernel.cluster_dim.map(|(x, y, z)| quote! { (#x, #y, #z) });
+    match (cluster_dim, kernel.cooperative) {
+        (Some(cluster_dim), true) => quote! {
+            unsafe {
+                ::cuda_core::launch_kernel_ex_cooperative_on_stream(
+                    #function,
+                    #config.grid_dim,
+                    #config.block_dim,
+                    #config.shared_mem_bytes,
+                    #cluster_dim,
+                    #stream,
+                    &mut #args,
+                )
+            }
+        },
+        (Some(cluster_dim), false) => quote! {
+            unsafe {
+                ::cuda_core::launch_kernel_ex_on_stream(
+                    #function,
+                    #config.grid_dim,
+                    #config.block_dim,
+                    #config.shared_mem_bytes,
+                    #cluster_dim,
+                    #stream,
+                    &mut #args,
+                )
+            }
+        },
+        (None, true) => quote! {
+            unsafe {
+                ::cuda_core::launch_kernel_cooperative_on_stream(
+                    #function,
+                    #config.grid_dim,
+                    #config.block_dim,
+                    #config.shared_mem_bytes,
+                    #stream,
+                    &mut #args,
+                )
+            }
+        },
+        (None, false) => quote! {
+            unsafe {
+                ::cuda_core::launch_kernel_on_stream(
+                    #function,
+                    #config.grid_dim,
+                    #config.block_dim,
+                    #config.shared_mem_bytes,
+                    #stream,
+                    &mut #args,
+                )
+            }
+        },
+    }
+}
+
+/// Whether rustc must create distinct code for this generic parameter list.
+///
+/// Lifetimes are deliberately excluded: rustc erases them before codegen, so
+/// they cannot distinguish PTX entry points. Type and const parameters both
+/// participate in monomorphization and therefore in kernel identity.
+pub(crate) fn has_codegen_generics(generics: &syn::Generics) -> bool {
+    generics
+        .params
+        .iter()
+        .any(|param| matches!(param, GenericParam::Type(_) | GenericParam::Const(_)))
+}
+
+/// Ordered generic arguments accepted by a function turbofish.
+///
+/// Rust function turbofish syntax omits lifetime arguments. Type and const
+/// identifiers must remain in declaration order so mixed `<T, const N>`
+/// kernels instantiate the exact function item requested by the caller.
+pub(crate) fn codegen_generic_arguments(generics: &syn::Generics) -> Vec<TokenStream2> {
+    generics
+        .params
+        .iter()
+        .filter_map(|param| match param {
+            GenericParam::Type(type_param) => {
+                let ident = &type_param.ident;
+                Some(quote! { #ident })
+            }
+            GenericParam::Const(const_param) => {
+                let ident = &const_param.ident;
+                Some(quote! { #ident })
+            }
+            GenericParam::Lifetime(_) => None,
+        })
+        .collect()
+}
+
+/// Ordered arguments for applying a generated marker type.
+///
+/// Unlike function turbofish syntax, a type application retains lifetime
+/// parameters. The specialization hash still ignores their identity because
+/// rustc's `TypeId` pipeline erases regions.
+pub(crate) fn generic_arguments(generics: &syn::Generics) -> Vec<TokenStream2> {
+    generics
+        .params
+        .iter()
+        .map(|param| match param {
+            GenericParam::Lifetime(lifetime_param) => {
+                let lifetime = &lifetime_param.lifetime;
+                quote! { #lifetime }
+            }
+            GenericParam::Type(type_param) => {
+                let ident = &type_param.ident;
+                quote! { #ident }
+            }
+            GenericParam::Const(const_param) => {
+                let ident = &const_param.ident;
+                quote! { #ident }
+            }
+        })
+        .collect()
+}
+
+/// Types used by `PhantomData` so generated marker types correctly witness
+/// every lifetime and type parameter. Const parameters are part of the marker
+/// type by construction and need no field-level witness.
+pub(crate) fn generic_phantom_type(generics: &syn::Generics) -> TokenStream2 {
+    let witnesses: Vec<TokenStream2> = generics
+        .params
+        .iter()
+        .filter_map(|param| match param {
+            GenericParam::Lifetime(lifetime_param) => {
+                let lifetime = &lifetime_param.lifetime;
+                Some(quote! { &#lifetime () })
+            }
+            GenericParam::Type(type_param) => {
+                let ident = &type_param.ident;
+                Some(quote! { *const #ident })
+            }
+            GenericParam::Const(_) => None,
+        })
+        .collect();
+
+    if witnesses.is_empty() {
+        quote! { () }
+    } else {
+        quote! { (#(#witnesses,)*) }
+    }
+}
+
+pub(super) fn cuda_module_function_field(fn_name: &Ident) -> Ident {
+    format_ident!("__{}_function", fn_name)
+}
+
+pub(super) fn cuda_kernel_marker_name(fn_name: &Ident) -> Ident {
+    format_ident!("__{}_CudaKernel", fn_name)
+}
diff --git a/crates/cuda-macros/src/cuda_module/mod.rs b/crates/cuda-macros/src/cuda_module/mod.rs
new file mode 100644
index 0000000000..c01d58c0b0
--- /dev/null
+++ b/crates/cuda-macros/src/cuda_module/mod.rs
@@ -0,0 +1,981 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! `#[cuda_module]` expansion driver, including nested-module support.
+
+pub(crate) mod constants;
+pub(crate) mod contract;
+pub(crate) mod launchers;
+pub(crate) mod model;
+
+use crate::common::{
+    attr_path_ends_with, has_attr_named, impl_trait_parameter_error, internal_ident,
+    track_codegen_environment,
+};
+use crate::cuda_module::constants::{
+    collect_cuda_module_constants, cuda_module_items_with_constant_symbols,
+    generate_cuda_module_constant_field, generate_cuda_module_constant_initializer,
+    generate_cuda_module_constant_resolver_method, generate_cuda_module_set_constant_method,
+};
+use crate::cuda_module::contract::{
+    cuda_module_cluster_dim, cuda_module_cooperative, cuda_module_launch_contract,
+};
+use crate::cuda_module::launchers::{
+    cuda_kernel_marker_name, cuda_module_function_field, generate_cuda_module_async_launch_method,
+    generate_cuda_module_launch_contract_impl, generate_cuda_module_launch_method,
+    generate_cuda_module_owned_async_launch_method, generate_cuda_module_prepare_launch_methods,
+    has_codegen_generics,
+};
+use crate::cuda_module::model::{
+    CudaModuleKernel, add_cuda_module_disjoint_abi_bounds,
+    add_cuda_module_disjoint_contract_bounds, add_cuda_module_uniform_bounds, cuda_module_params,
+};
+use crate::launch_attrs::{add_launch_bounds_evaluatability_from_attrs, rewrite_loop_unroll_attrs};
+use proc_macro::TokenStream;
+use proc_macro2::TokenStream as TokenStream2;
+use quote::quote;
+use reserved_oxide_symbols::{
+    DEVICE_CODEGEN_CRATE_ENV, artifact_anchor_symbol, artifact_anchor_symbol_v2,
+    ptx_merge_required_marker,
+};
+use syn::{
+    Ident, Item, ItemFn, ItemMod, LitStr, Token, parse_macro_input, parse_quote,
+    punctuated::Punctuated,
+};
+
+pub(crate) fn cuda_module_entry(attr: TokenStream, item: TokenStream) -> TokenStream {
+    track_codegen_environment();
+    if !attr.is_empty() {
+        return syn::Error::new(
+            proc_macro2::Span::call_site(),
+            "cuda_module does not take arguments yet",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    let input = parse_macro_input!(item as ItemMod);
+    match expand_cuda_module(input) {
+        Ok(tokens) => tokens.into(),
+        Err(error) => error.to_compile_error().into(),
+    }
+}
+
+/// Expands `#[cuda_module]`, emitting the host surface when the `host`
+/// feature is on.
+pub(crate) fn expand_cuda_module(module: ItemMod) -> syn::Result<TokenStream2> {
+    expand_cuda_module_inner(module, cfg!(feature = "host"))
+}
+
+/// `expand_cuda_module` with the host-surface decision passed in.
+///
+/// The decision is a parameter rather than a `cfg!` read inside the body so
+/// that tests can exercise both settings from one build. They otherwise
+/// could not: this crate dev-depends on `cuda-host`, which turns the `host`
+/// feature back on under feature unification even for
+/// `cargo test --no-default-features`.
+pub(crate) fn expand_cuda_module_inner(
+    module: ItemMod,
+    emit_host: bool,
+) -> syn::Result<TokenStream2> {
+    let module_attrs = &module.attrs;
+    let vis = &module.vis;
+    let ident = &module.ident;
+    let Some((_brace, items)) = &module.content else {
+        return Err(syn::Error::new_spanned(
+            &module.ident,
+            "cuda_module requires an inline module so kernel signatures are visible",
+        ));
+    };
+
+    let constants = collect_cuda_module_constants(items, ident)?;
+    let transformed = transform_cuda_module_items(items, &mut Vec::new(), &[], false, emit_host)?;
+    if transformed.kernels.is_empty() {
+        return Err(syn::Error::new_spanned(
+            &module.ident,
+            "cuda_module found no #[kernel] functions in this module",
+        ));
+    }
+    reject_conflicting_kernel_names(&transformed.kernels)?;
+    reject_reserved_loaded_module(items)?;
+
+    let direct_kernels = &transformed.kernels[..transformed.direct_kernel_count];
+    reject_reserved_loaded_module_methods(direct_kernels, false)?;
+    let module_items = cuda_module_items_with_constant_symbols(&transformed.items, &constants);
+
+    let non_generic_kernels = direct_kernels.iter().filter(|kernel| !kernel.is_generic);
+    let function_fields = non_generic_kernels.clone().map(|kernel| {
+        let cfg_attrs = &kernel.cfg_attrs;
+        let field = cuda_module_function_field(&kernel.fn_name);
+        quote! {
+            #(#cfg_attrs)*
+            #field: ::cuda_core::CudaFunction,
+        }
+    });
+
+    let function_initializers = non_generic_kernels.map(|kernel| {
+        let cfg_attrs = &kernel.cfg_attrs;
+        let field = cuda_module_function_field(&kernel.fn_name);
+        let marker = cuda_kernel_marker_name(&kernel.fn_name);
+        quote! {
+            #(#cfg_attrs)*
+            #field: module.load_function(<#marker as ::cuda_host::CudaKernel>::PTX_NAME)?,
+        }
+    });
+
+    let artifact_anchor_statements = cuda_module_artifact_anchor_statements(&transformed.kernels)?;
+    let has_generic = transformed.kernels.iter().any(|k| k.is_generic);
+    let ptx_merge_required_markers = transformed.kernels.iter().filter_map(|kernel| {
+        if !kernel.is_generic {
+            return None;
+        }
+        let marker = internal_ident(&ptx_merge_required_marker(&kernel.fn_name.to_string()));
+        let cfg_attrs = &kernel.effective_cfg_attrs;
+        Some(quote! {
+            #(#cfg_attrs)*
+            // Consumed by the codegen collector. This enabled generic kernel
+            // requires run-time PTX bundle merging, which ahead-of-time cubin
+            // materialization cannot represent yet.
+            #[doc(hidden)]
+            #[used]
+            #[allow(dead_code, non_upper_case_globals)]
+            static #marker: u8 = 0;
+        })
+    });
+    let enable_generic_loader_statements = transformed.kernels.iter().filter_map(|kernel| {
+        if !kernel.is_generic {
+            return None;
+        }
+        let cfg_attrs = &kernel.effective_cfg_attrs;
+        Some(quote! {
+            #(#cfg_attrs)*
+            let _ = {
+                __cuda_oxide_has_enabled_generic_kernel = true;
+            };
+        })
+    });
+    let has_launch_contract = transformed
+        .kernels
+        .iter()
+        .any(|kernel| kernel.launch_contract.is_some());
+    let module_loader = if has_generic {
+        // A syntactically present generic kernel may be removed by cfg. Make
+        // the loader decision under the exact same effective cfg chain as its
+        // marker, so eligibility and run-time behavior cannot disagree.
+        quote! {
+            #[allow(unused_mut)]
+            let mut __cuda_oxide_has_enabled_generic_kernel = false;
+            #(#enable_generic_loader_statements)*
+            let module = if __cuda_oxide_has_enabled_generic_kernel {
+                let _ = name; // merged load ignores the crate-name hint
+                ::cuda_host::load_all_ptx_bundles_merged(ctx)?
+            } else {
+                ::cuda_host::load_embedded_module(ctx, name)?
+            };
+        }
+    } else {
+        quote! {
+            let module = ::cuda_host::load_embedded_module(ctx, name)?;
+        }
+    };
+    let constant_fields = constants.iter().map(generate_cuda_module_constant_field);
+    let constant_initializers = constants
+        .iter()
+        .map(generate_cuda_module_constant_initializer);
+    let launch_contract_impls = direct_kernels
+        .iter()
+        .filter_map(generate_cuda_module_launch_contract_impl);
+    let prepare_launch_methods = direct_kernels
+        .iter()
+        .filter_map(generate_cuda_module_prepare_launch_methods);
+    let launch_methods = direct_kernels
+        .iter()
+        .map(generate_cuda_module_launch_method);
+    let constant_resolver_methods = constants
+        .iter()
+        .map(generate_cuda_module_constant_resolver_method);
+    let set_constant_methods = constants
+        .iter()
+        .map(generate_cuda_module_set_constant_method);
+    let async_module_items = if cfg!(feature = "async") && has_launch_contract {
+        quote! {
+            /// Loads this package's embedded artifact for a contracted module.
+            ///
+            /// # Safety
+            ///
+            /// For a non-generic module, the selected package bundle must be
+            /// the artifact compiled from this `cuda_module`; package names are
+            /// not yet unique across all library and binary targets. For a
+            /// generic module, the merged PTX set must contain each matching
+            /// specialization and no conflicting entry definition.
+            pub unsafe fn load_async(
+                device_id: usize,
+            ) -> ::core::result::Result<LoadedModule, ::cuda_host::cuda_async::error::DeviceError> {
+                // SAFETY: upheld by this function's caller.
+                unsafe { load_async_named(device_id, env!("CARGO_PKG_NAME")) }
+            }
+
+            /// Loads a caller-selected artifact for this contracted module.
+            ///
+            /// # Safety
+            ///
+            /// Every selected kernel must have the exact ABI and resource
+            /// semantics declared by this `cuda_module`. A matching symbol
+            /// name alone is not sufficient.
+            pub unsafe fn load_async_named(
+                device_id: usize,
+                name: &str,
+            ) -> ::core::result::Result<LoadedModule, ::cuda_host::cuda_async::error::DeviceError> {
+                ::cuda_host::load_cuda_module_from_async_context(device_id, |ctx| {
+                    // SAFETY: upheld by this function's caller.
+                    unsafe { load_named(ctx, name) }
+                })
+            }
+        }
+    } else if cfg!(feature = "async") {
+        quote! {
+            pub fn load_async(
+                device_id: usize,
+            ) -> ::core::result::Result<LoadedModule, ::cuda_host::cuda_async::error::DeviceError> {
+                load_async_named(device_id, env!("CARGO_PKG_NAME"))
+            }
+
+            pub fn load_async_named(
+                device_id: usize,
+                name: &str,
+            ) -> ::core::result::Result<LoadedModule, ::cuda_host::cuda_async::error::DeviceError> {
+                ::cuda_host::load_cuda_module_from_async_context(device_id, |ctx| load_named(ctx, name))
+            }
+        }
+    } else {
+        TokenStream2::new()
+    };
+    let load_definition = if has_launch_contract {
+        quote! {
+            /// Loads this package's embedded artifact for a contracted module.
+            ///
+            /// # Safety
+            ///
+            /// For a non-generic module, the selected package bundle must be
+            /// the artifact compiled from this `cuda_module`; package names are
+            /// not yet unique across all library and binary targets. For a
+            /// generic module, the merged PTX set must contain each matching
+            /// specialization and no conflicting entry definition.
+            pub unsafe fn load(
+                ctx: &::std::sync::Arc<::cuda_core::CudaContext>,
+            ) -> ::core::result::Result<LoadedModule, ::cuda_host::EmbeddedModuleError> {
+                // SAFETY: upheld by this function's caller.
+                unsafe { load_named(ctx, env!("CARGO_PKG_NAME")) }
+            }
+        }
+    } else {
+        quote! {
+            pub fn load(
+                ctx: &::std::sync::Arc<::cuda_core::CudaContext>,
+            ) -> ::core::result::Result<LoadedModule, ::cuda_host::EmbeddedModuleError> {
+                load_named(ctx, env!("CARGO_PKG_NAME"))
+            }
+        }
+    };
+    let load_named_definition = if has_launch_contract {
+        quote! {
+            /// Loads a caller-selected artifact for this contracted module.
+            ///
+            /// # Safety
+            ///
+            /// Every selected kernel must have the exact ABI and resource
+            /// semantics declared by this `cuda_module`. A matching symbol
+            /// name alone is not sufficient.
+            pub unsafe fn load_named(
+                ctx: &::std::sync::Arc<::cuda_core::CudaContext>,
+                name: &str,
+            ) -> ::core::result::Result<LoadedModule, ::cuda_host::EmbeddedModuleError> {
+                #artifact_anchor_statements
+                #module_loader
+                // SAFETY: upheld by this function's caller.
+                unsafe { from_module(module) }.map_err(::cuda_host::EmbeddedModuleError::Driver)
+            }
+        }
+    } else {
+        quote! {
+            pub fn load_named(
+                ctx: &::std::sync::Arc<::cuda_core::CudaContext>,
+                name: &str,
+            ) -> ::core::result::Result<LoadedModule, ::cuda_host::EmbeddedModuleError> {
+                #artifact_anchor_statements
+                #module_loader
+                from_module(module).map_err(::cuda_host::EmbeddedModuleError::Driver)
+            }
+        }
+    };
+    let from_module_definition = if has_launch_contract {
+        quote! {
+            /// Binds caller-provided CUDA code to this module's launch API.
+            ///
+            /// # Safety
+            ///
+            /// Every loaded kernel must have the exact ABI and resource
+            /// semantics declared by this `cuda_module`. A matching symbol
+            /// name alone is not sufficient.
+            pub unsafe fn from_module(
+                module: ::std::sync::Arc<::cuda_core::CudaModule>,
+            ) -> ::core::result::Result<LoadedModule, ::cuda_core::DriverError> {
+                Ok(LoadedModule {
+                    __module: module.clone(),
+                    __generic_functions: ::std::sync::Arc::new(
+                        ::std::sync::Mutex::new(::std::collections::HashMap::new())
+                    ),
+                    #(#function_initializers)*
+                    #(#constant_initializers)*
+                })
+            }
+        }
+    } else {
+        quote! {
+            pub fn from_module(
+                module: ::std::sync::Arc<::cuda_core::CudaModule>,
+            ) -> ::core::result::Result<LoadedModule, ::cuda_core::DriverError> {
+                Ok(LoadedModule {
+                    __module: module.clone(),
+                    __generic_functions: ::std::sync::Arc::new(
+                        ::std::sync::Mutex::new(::std::collections::HashMap::new())
+                    ),
+                    #(#function_initializers)*
+                    #(#constant_initializers)*
+                })
+            }
+        }
+    };
+    let async_launch_methods = if cfg!(feature = "async") {
+        let async_launch_methods = direct_kernels
+            .iter()
+            .map(generate_cuda_module_async_launch_method);
+        let owned_async_launch_methods = direct_kernels
+            .iter()
+            .map(generate_cuda_module_owned_async_launch_method);
+        quote! {
+            #(#async_launch_methods)*
+            #(#owned_async_launch_methods)*
+        }
+    } else {
+        TokenStream2::new()
+    };
+
+    // Everything below names `::cuda_host` or `::cuda_core`. The kernels
+    // themselves, and the PTX-merge markers the codegen collector consumes, do
+    // not -- so a crate that only compiles kernels can take cuda-macros with
+    // `default-features = false` and stop depending on the host stack.
+    let host_items = if emit_host {
+        quote! {
+            #(#launch_contract_impls)*
+
+            #[derive(Clone, Debug)]
+            #[allow(non_snake_case)]
+            pub struct LoadedModule {
+                __module: ::std::sync::Arc<::cuda_core::CudaModule>,
+                __generic_functions: ::std::sync::Arc<
+                    ::std::sync::Mutex<
+                        ::std::collections::HashMap<&'static str, ::cuda_core::CudaFunction>
+                    >
+                >,
+                #(#function_fields)*
+                #(#constant_fields)*
+            }
+
+            #load_definition
+
+            #load_named_definition
+
+            #from_module_definition
+
+            #async_module_items
+
+            impl LoadedModule {
+                pub fn as_cuda_module(&self) -> &::std::sync::Arc<::cuda_core::CudaModule> {
+                    &self.__module
+                }
+
+                #(#launch_methods)*
+                #(#prepare_launch_methods)*
+                #(#constant_resolver_methods)*
+                #(#set_constant_methods)*
+                #async_launch_methods
+            }
+        }
+    } else {
+        TokenStream2::new()
+    };
+
+    Ok(quote! {
+        #(#module_attrs)*
+        #vis mod #ident {
+            #(#module_items)*
+            #(#ptx_merge_required_markers)*
+            #host_items
+        }
+    })
+}
+
+pub(crate) struct CudaModuleLevel {
+    pub(crate) items: Vec<Item>,
+    pub(crate) kernels: Vec<CudaModuleKernel>,
+    pub(crate) direct_kernel_count: usize,
+}
+
+/// Recursively rewrite only inline child modules.
+///
+/// Every module that owns a kernel (or contains a deeper module that does)
+/// receives its own `LoadedModule`. That keeps generated method signatures in
+/// the same Rust scope as the source kernel. File-backed modules and
+/// `include!` invocations are preserved but not traversed: their contents are
+/// not present in an attribute macro's input token stream, and reproducing
+/// rustc's module loader in a proc macro is neither complete nor hygienic.
+pub(crate) fn transform_cuda_module_items(
+    items: &[Item],
+    module_path: &mut Vec<Ident>,
+    ancestor_cfg_attrs: &[syn::Attribute],
+    generate_nested_support: bool,
+    emit_host: bool,
+) -> syn::Result<CudaModuleLevel> {
+    let mut transformed_items = Vec::with_capacity(items.len());
+    let mut direct_kernels = Vec::new();
+    let mut descendant_kernels = Vec::new();
+
+    for item in items {
+        match item {
+            Item::Fn(item_fn) => {
+                if let Some(kernel) = cuda_module_kernel(item_fn, module_path, ancestor_cfg_attrs)?
+                {
+                    direct_kernels.push(kernel);
+                }
+                transformed_items.push(item.clone());
+            }
+            Item::Mod(item_mod) => {
+                let Some((_brace, nested_items)) = &item_mod.content else {
+                    // Attribute macros receive the declaration, not the file's
+                    // contents. Preserve it exactly, but do not pretend that
+                    // kernels behind this boundary were discovered.
+                    transformed_items.push(item.clone());
+                    continue;
+                };
+
+                module_path.push(item_mod.ident.clone());
+                let mut nested_cfg_attrs = ancestor_cfg_attrs.to_vec();
+                nested_cfg_attrs.extend(cuda_module_cfg_attrs(&item_mod.attrs)?);
+                let nested = transform_cuda_module_items(
+                    nested_items,
+                    module_path,
+                    &nested_cfg_attrs,
+                    true,
+                    emit_host,
+                )?;
+                module_path.pop();
+
+                let mut transformed_mod = item_mod.clone();
+                transformed_mod
+                    .content
+                    .as_mut()
+                    .expect("inline module content disappeared")
+                    .1 = nested.items;
+                descendant_kernels.extend(nested.kernels);
+                transformed_items.push(Item::Mod(transformed_mod));
+            }
+            _ => transformed_items.push(item.clone()),
+        }
+    }
+
+    let direct_kernel_count = direct_kernels.len();
+    let mut kernels = direct_kernels;
+    kernels.extend(descendant_kernels);
+
+    if generate_nested_support && !kernels.is_empty() {
+        reject_reserved_loaded_module(items)?;
+        reject_reserved_loaded_module_methods(&kernels[..direct_kernel_count], true)?;
+        let support =
+            generate_nested_cuda_module_support(&kernels[..direct_kernel_count], emit_host);
+        let mut support_items = syn::parse2::<syn::File>(support)?.items;
+        transformed_items.append(&mut support_items);
+    }
+
+    Ok(CudaModuleLevel {
+        items: transformed_items,
+        kernels,
+        direct_kernel_count,
+    })
+}
+
+fn reject_reserved_loaded_module(items: &[Item]) -> syn::Result<()> {
+    for item in items {
+        let ident = match item {
+            Item::Const(item) => Some(&item.ident),
+            Item::Enum(item) => Some(&item.ident),
+            Item::ExternCrate(item) => item
+                .rename
+                .as_ref()
+                .map(|(_as_token, rename)| rename)
+                .or(Some(&item.ident)),
+            Item::Fn(item) => Some(&item.sig.ident),
+            Item::Mod(item) => Some(&item.ident),
+            Item::Static(item) => Some(&item.ident),
+            Item::Struct(item) => Some(&item.ident),
+            Item::Trait(item) => Some(&item.ident),
+            Item::TraitAlias(item) => Some(&item.ident),
+            Item::Type(item) => Some(&item.ident),
+            Item::Union(item) => Some(&item.ident),
+            Item::Use(item) => cuda_module_loaded_module_use_binding(&item.tree),
+            _ => None,
+        };
+        if ident.is_some_and(|ident| cuda_module_ident_key(ident) == "LoadedModule") {
+            return Err(syn::Error::new_spanned(
+                ident.expect("checked above"),
+                "#[cuda_module] reserves the name `LoadedModule` in every inline namespace that contains kernels",
+            ));
+        }
+    }
+    Ok(())
+}
+
+fn reject_reserved_loaded_module_methods(
+    kernels: &[CudaModuleKernel],
+    nested: bool,
+) -> syn::Result<()> {
+    for kernel in kernels {
+        let name = cuda_module_ident_key(&kernel.fn_name);
+        let reserved = name == "as_cuda_module" || (nested && name == "from_parent");
+        if reserved {
+            let scope = if name == "from_parent" {
+                "nested kernel namespaces"
+            } else {
+                "every kernel namespace"
+            };
+            return Err(syn::Error::new_spanned(
+                &kernel.fn_name,
+                format!(
+                    "#[cuda_module] reserves launcher method name `{name}` in {scope}; rename the kernel"
+                ),
+            ));
+        }
+    }
+    Ok(())
+}
+
+/// Return the collision key for generated Rust and PTX namespaces.
+///
+/// `syn::Ident::to_string()` preserves a raw prefix, but `step` and `r#step`
+/// name the same Rust identifier and must collide in cuda-oxide's bare PTX
+/// namespace. Guards compare this normalized key before generating anything.
+fn cuda_module_ident_key(ident: &Ident) -> String {
+    let spelling = ident.to_string();
+    spelling.strip_prefix("r#").unwrap_or(&spelling).to_string()
+}
+
+fn cuda_module_loaded_module_use_binding(tree: &syn::UseTree) -> Option<&Ident> {
+    match tree {
+        syn::UseTree::Path(path) => cuda_module_loaded_module_use_binding(&path.tree),
+        syn::UseTree::Name(name) => {
+            (cuda_module_ident_key(&name.ident) == "LoadedModule").then_some(&name.ident)
+        }
+        syn::UseTree::Rename(rename) => {
+            (cuda_module_ident_key(&rename.rename) == "LoadedModule").then_some(&rename.rename)
+        }
+        syn::UseTree::Group(group) => group
+            .items
+            .iter()
+            .find_map(cuda_module_loaded_module_use_binding),
+        syn::UseTree::Glob(_) => None,
+    }
+}
+
+fn cuda_module_kernel(
+    item_fn: &ItemFn,
+    module_path: &[Ident],
+    ancestor_cfg_attrs: &[syn::Attribute],
+) -> syn::Result<Option<CudaModuleKernel>> {
+    if !has_attr_named(&item_fn.attrs, "kernel") {
+        return Ok(None);
+    }
+    if let Some(err) = impl_trait_parameter_error(item_fn, "kernel") {
+        return Err(err);
+    }
+    let cluster_dim = cuda_module_cluster_dim(&item_fn.attrs)?;
+    let cooperative = cuda_module_cooperative(&item_fn.attrs)?;
+    let params = cuda_module_params(item_fn)?;
+    let launch_contract =
+        cuda_module_launch_contract(&item_fn.attrs, &item_fn.sig.ident, &params, cluster_dim)?;
+    // `#[cuda_module]` expands before both the nested function attributes and
+    // the recursive module rewrite. Mirror the evaluatability predicates that
+    // `#[launch_bounds]` and `#[kernel]` add to each concrete entry while
+    // retaining the nested module's path and inherited cfg attributes.
+    let mut configured_item = item_fn.clone();
+    rewrite_loop_unroll_attrs(&mut configured_item)?;
+    add_launch_bounds_evaluatability_from_attrs(&mut configured_item)?;
+    let mut generics = configured_item.sig.generics;
+    if let Some(contract) = launch_contract.as_ref() {
+        add_cuda_module_disjoint_contract_bounds(&mut generics, &params, contract.domain);
+    }
+    // A `Uniform` parameter carries its proof with or without a launch
+    // contract, so this bound is not conditional on one.
+    add_cuda_module_uniform_bounds(&mut generics, &params);
+    // The launch packet's shape (two or three words per slice) must match the
+    // resolved device type with or without a launch contract, so this bound
+    // is unconditional too.
+    add_cuda_module_disjoint_abi_bounds(&mut generics, &params);
+    let is_generic = has_codegen_generics(&item_fn.sig.generics);
+    let cfg_attrs = cuda_module_cfg_attrs(&item_fn.attrs)?;
+    let mut effective_cfg_attrs = ancestor_cfg_attrs.to_vec();
+    effective_cfg_attrs.extend(cfg_attrs.clone());
+    Ok(Some(CudaModuleKernel {
+        module_path: module_path.to_vec(),
+        vis: item_fn.vis.clone(),
+        cfg_attrs,
+        effective_cfg_attrs,
+        method_attrs: cuda_module_method_attrs(&item_fn.attrs),
+        unsafety: item_fn.sig.unsafety,
+        fn_name: item_fn.sig.ident.clone(),
+        generics,
+        params,
+        cluster_dim,
+        cooperative,
+        launch_contract,
+        is_generic,
+    }))
+}
+
+fn generate_nested_cuda_module_support(
+    kernels: &[CudaModuleKernel],
+    emit_host: bool,
+) -> TokenStream2 {
+    let launch_contract_impls = kernels
+        .iter()
+        .filter_map(generate_cuda_module_launch_contract_impl);
+    let prepare_launch_methods = kernels
+        .iter()
+        .filter_map(generate_cuda_module_prepare_launch_methods);
+    let non_generic_kernels = kernels.iter().filter(|kernel| !kernel.is_generic);
+    let function_fields = non_generic_kernels.clone().map(|kernel| {
+        let cfg_attrs = &kernel.cfg_attrs;
+        let field = cuda_module_function_field(&kernel.fn_name);
+        quote! {
+            #(#cfg_attrs)*
+            #field: ::cuda_core::CudaFunction,
+        }
+    });
+    let function_initializers = non_generic_kernels.map(|kernel| {
+        let cfg_attrs = &kernel.cfg_attrs;
+        let field = cuda_module_function_field(&kernel.fn_name);
+        let marker = cuda_kernel_marker_name(&kernel.fn_name);
+        quote! {
+            #(#cfg_attrs)*
+            #field: module.load_function(<#marker as ::cuda_host::CudaKernel>::PTX_NAME)?,
+        }
+    });
+    let launch_methods = kernels.iter().map(generate_cuda_module_launch_method);
+    let async_launch_methods = if cfg!(feature = "async") {
+        let borrowed = kernels.iter().map(generate_cuda_module_async_launch_method);
+        let owned = kernels
+            .iter()
+            .map(generate_cuda_module_owned_async_launch_method);
+        quote! {
+            #(#borrowed)*
+            #(#owned)*
+        }
+    } else {
+        TokenStream2::new()
+    };
+
+    // Host-only, exactly as in `expand_cuda_module_inner`; see the note there.
+    if !emit_host {
+        return TokenStream2::new();
+    }
+
+    quote! {
+        #(#launch_contract_impls)*
+
+        #[derive(Clone, Debug)]
+        #[allow(non_snake_case)]
+        pub struct LoadedModule {
+            __module: ::std::sync::Arc<::cuda_core::CudaModule>,
+            __generic_functions: ::std::sync::Arc<
+                ::std::sync::Mutex<
+                    ::std::collections::HashMap<&'static str, ::cuda_core::CudaFunction>
+                >
+            >,
+            #(#function_fields)*
+        }
+
+        impl LoadedModule {
+            /// Bind this namespace's launchers to a module loaded by its
+            /// immediate parent namespace.
+            pub fn from_parent(
+                parent: &super::LoadedModule,
+            ) -> ::core::result::Result<Self, ::cuda_core::DriverError> {
+                let module = parent.as_cuda_module().clone();
+                Ok(Self {
+                    __module: module.clone(),
+                    __generic_functions: parent.__generic_functions.clone(),
+                    #(#function_initializers)*
+                })
+            }
+
+            pub fn as_cuda_module(&self) -> &::std::sync::Arc<::cuda_core::CudaModule> {
+                &self.__module
+            }
+
+            #(#launch_methods)*
+            #(#prepare_launch_methods)*
+            #async_launch_methods
+        }
+    }
+}
+
+/// Reject duplicate bare kernel names anywhere in one `#[cuda_module]` tree.
+///
+/// Launcher methods are namespace-qualified, but cuda-oxide's current PTX
+/// entry naming is not: `stage1::step` and `stage2::step` both export `step`.
+/// Until the backend and `#[kernel]` share a qualified entry-name contract,
+/// accepting the pair would risk resolving a launcher to the wrong entry.
+/// The restriction is therefore syntactic and also applies to cfg-gated
+/// alternatives; proc macros cannot prove that arbitrary cfg predicates are
+/// mutually exclusive.
+fn reject_conflicting_kernel_names(kernels: &[CudaModuleKernel]) -> syn::Result<()> {
+    let mut names: std::collections::HashMap<String, &CudaModuleKernel> =
+        std::collections::HashMap::new();
+    for kernel in kernels {
+        let name = cuda_module_ident_key(&kernel.fn_name);
+        if let Some(previous) = names.insert(name.clone(), kernel) {
+            return Err(syn::Error::new(
+                kernel.fn_name.span(),
+                format!(
+                    "cuda-oxide PTX entry names are currently bare function names, so \
+                     #[cuda_module] requires kernel names to be unique across its inline \
+                     module tree: `{name}` in {second} conflicts with `{name}` in {first}; \
+                     rename one of the kernels",
+                    name = name,
+                    first = cuda_module_path_description(&previous.module_path),
+                    second = cuda_module_path_description(&kernel.module_path),
+                ),
+            ));
+        }
+    }
+    Ok(())
+}
+
+fn cuda_module_path_description(module_path: &[Ident]) -> String {
+    if module_path.is_empty() {
+        "the module root".to_string()
+    } else {
+        format!(
+            "`{}`",
+            module_path
+                .iter()
+                .map(Ident::to_string)
+                .collect::<Vec<_>>()
+                .join("::")
+        )
+    }
+}
+
+/// Generate the statements that pin this crate's embedded device artifact
+/// into the final binary.
+///
+/// The codegen backend stores each crate's compiled device code (PTX,
+/// cubin, NVVM IR, or LTOIR) in a `.oxart` data section of a small extra
+/// object file. When the crate that holds the `#[cuda_module]` is a
+/// *library*, that object becomes one member of the crate's `.rlib`
+/// archive, and linkers only extract an archive member when it defines a
+/// symbol that some already-linked object references. The backend defines
+/// a global anchor symbol inside the artifact object for exactly this
+/// purpose; here we emit the matching reference. Reading the anchor's
+/// address through `black_box` inside `load_named()` means that any
+/// program calling `load()` carries an undefined reference to the anchor,
+/// which forces the linker to pull the artifact member out of the rlib.
+/// Without this handshake the bundle was silently dropped and `load()`
+/// failed at runtime with `ModuleNotFound` (issue #72).
+///
+/// Without an owner filter, both sides keep using the legacy package+version
+/// anchor for compatibility with older wrappers and backends. A non-empty
+/// owner filter activates the v2 package+version+crate+binary identity. That
+/// target-specific identity prevents an unselected binary from satisfying a
+/// selected library's reference (or vice versa); an unselected new macro emits
+/// no reference at all. The backend also keeps a weak legacy alias for older
+/// macro expansions in mixed-version builds.
+///
+/// The reference is only emitted when the module is guaranteed to produce
+/// an artifact for this crate. Generic kernels are monomorphized (and
+/// their PTX embedded) in the *consuming* crate, so a module with only
+/// generic kernels yields no artifact here, and an anchor reference would
+/// be an undefined-symbol link error. The same reasoning extends to
+/// cfg-gated kernels: root `load()` emits one equivalent guarded reference per
+/// concrete kernel in the complete inline tree. Each reference carries the
+/// kernel's effective ancestor-plus-local availability attributes, so a module
+/// containing only nested kernels is still independently loadable while no
+/// anchor is referenced when every concrete kernel is absent.
+fn cuda_module_artifact_anchor_statements(
+    kernels: &[CudaModuleKernel],
+) -> syn::Result<TokenStream2> {
+    let (Ok(package_name), Ok(package_version), Ok(crate_name)) = (
+        std::env::var("CARGO_PKG_NAME"),
+        std::env::var("CARGO_PKG_VERSION"),
+        std::env::var("CARGO_CRATE_NAME"),
+    ) else {
+        // Not built by cargo (e.g. a raw rustc invocation): the backend
+        // falls back to crate-name-based bundle naming and we cannot
+        // reproduce it exactly, so skip the anchor rather than risk an
+        // undefined symbol.
+        return Ok(TokenStream2::new());
+    };
+
+    let owner_filter = proc_macro::tracked::env_var(DEVICE_CODEGEN_CRATE_ENV).ok();
+    let owner_selection = device_codegen_owner_selection(owner_filter.as_deref(), &crate_name);
+    if owner_selection == Some(false) {
+        // The backend deliberately omits this crate's artifact. Omitting the
+        // reference as well keeps the host link valid without pretending that
+        // a loadable bundle exists.
+        return Ok(TokenStream2::new());
+    }
+
+    if !kernels.iter().any(|kernel| !kernel.is_generic) {
+        return Ok(TokenStream2::new());
+    }
+
+    let binary_name = std::env::var("CARGO_BIN_NAME").ok();
+    let anchor = if owner_selection.is_some() {
+        artifact_anchor_symbol_v2(
+            &package_name,
+            &package_version,
+            &crate_name,
+            binary_name.as_deref(),
+        )
+    } else {
+        artifact_anchor_symbol(&package_name, &package_version)
+    };
+    let anchor_name = LitStr::new(&anchor, proc_macro2::Span::call_site());
+    let references = kernels
+        .iter()
+        .filter(|kernel| !kernel.is_generic)
+        .map(|kernel| {
+            let cfg_attrs = &kernel.effective_cfg_attrs;
+            quote! {
+                #(#cfg_attrs)*
+                let _artifact_anchor: *const ::core::primitive::u8 = {
+                    unsafe extern "C" {
+                        #[link_name = #anchor_name]
+                        static CUDA_OXIDE_BUNDLE_ANCHOR: ::core::primitive::u8;
+                    }
+                    ::std::hint::black_box(unsafe {
+                        ::core::ptr::addr_of!(CUDA_OXIDE_BUNDLE_ANCHOR)
+                    })
+                };
+            }
+        });
+    Ok(quote! {
+        // Keep-alive handshake with the codegen backend: see the macro
+        // crate's `cuda_module_artifact_anchor_statements` for details.
+        #(#references)*
+    })
+}
+
+pub(crate) fn device_codegen_owner_selection(raw: Option<&str>, crate_name: &str) -> Option<bool> {
+    let crate_name = crate_name.trim().replace('-', "_");
+    raw.and_then(|raw| {
+        let owners: Vec<_> = raw
+            .split(',')
+            .map(|name| name.trim().replace('-', "_"))
+            .filter(|name| !name.is_empty())
+            .collect();
+        (!owners.is_empty()).then(|| owners.iter().any(|owner| owner == &crate_name))
+    })
+}
+
+pub(super) fn cuda_module_method_attrs(attrs: &[syn::Attribute]) -> Vec<syn::Attribute> {
+    attrs
+        .iter()
+        .filter(|attr| attr_path_ends_with(attr, "doc"))
+        .cloned()
+        .collect()
+}
+
+/// Copy only the part of `cfg` / `cfg_attr` that controls whether an item
+/// exists. A kernel may use `cfg_attr` for function-only attributes such as
+/// `inline`; copying those onto generated fields or statements would be
+/// invalid. The nested `cfg` / `cfg_attr` availability semantics are retained;
+/// unrelated conditional attributes are omitted from generated items.
+pub(super) fn cuda_module_cfg_attrs(attrs: &[syn::Attribute]) -> syn::Result<Vec<syn::Attribute>> {
+    let mut filtered = Vec::new();
+    for attr in attrs {
+        if attr_path_ends_with(attr, "cfg") {
+            filtered.push(attr.clone());
+        } else if attr_path_ends_with(attr, "cfg_attr")
+            && let Some(attr) = filter_cuda_module_cfg_attr(attr)?
+        {
+            filtered.push(attr);
+        }
+    }
+    Ok(filtered)
+}
+
+fn filter_cuda_module_cfg_attr(attr: &syn::Attribute) -> syn::Result<Option<syn::Attribute>> {
+    let syn::Meta::List(list) = &attr.meta else {
+        return Err(syn::Error::new_spanned(attr, "cfg_attr requires arguments"));
+    };
+    let parser = Punctuated::<syn::Meta, Token![,]>::parse_terminated;
+    let mut args = syn::parse::Parser::parse2(parser, list.tokens.clone())?.into_iter();
+    let predicate = args
+        .next()
+        .ok_or_else(|| syn::Error::new_spanned(attr, "cfg_attr requires a predicate"))?;
+    let mut nested = Vec::new();
+    for meta in args {
+        if let Some(meta) = filter_cuda_module_cfg_meta(meta)? {
+            nested.push(meta);
+        }
+    }
+    if nested.is_empty() {
+        Ok(None)
+    } else {
+        Ok(Some(parse_quote!(#[cfg_attr(#predicate, #(#nested),*)])))
+    }
+}
+
+fn filter_cuda_module_cfg_meta(meta: syn::Meta) -> syn::Result<Option<syn::Meta>> {
+    if meta
+        .path()
+        .segments
+        .last()
+        .is_some_and(|segment| segment.ident == "cfg")
+    {
+        return Ok(Some(meta));
+    }
+    if meta
+        .path()
+        .segments
+        .last()
+        .is_none_or(|segment| segment.ident != "cfg_attr")
+    {
+        return Ok(None);
+    }
+    filter_cuda_module_nested_cfg_attr(meta)
+}
+
+fn filter_cuda_module_nested_cfg_attr(meta: syn::Meta) -> syn::Result<Option<syn::Meta>> {
+    let syn::Meta::List(list) = &meta else {
+        return Err(syn::Error::new_spanned(meta, "cfg_attr requires arguments"));
+    };
+    let parser = Punctuated::<syn::Meta, Token![,]>::parse_terminated;
+    let mut args = syn::parse::Parser::parse2(parser, list.tokens.clone())?.into_iter();
+    let predicate = args
+        .next()
+        .ok_or_else(|| syn::Error::new_spanned(&meta, "cfg_attr requires a predicate"))?;
+    let mut nested = Vec::new();
+    for meta in args {
+        if let Some(meta) = filter_cuda_module_cfg_meta(meta)? {
+            nested.push(meta);
+        }
+    }
+    if nested.is_empty() {
+        Ok(None)
+    } else {
+        Ok(Some(parse_quote!(cfg_attr(#predicate, #(#nested),*))))
+    }
+}
diff --git a/crates/cuda-macros/src/cuda_module/model.rs b/crates/cuda-macros/src/cuda_module/model.rs
new file mode 100644
index 0000000000..7dcaa2ee87
--- /dev/null
+++ b/crates/cuda-macros/src/cuda_module/model.rs
@@ -0,0 +1,445 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Kernel and parameter models for `#[cuda_module]`: marshalling
+//! classification and host-side type mapping.
+
+use crate::common::{cuda_module_async_lifetime, internal_ident};
+use crate::cuda_module::contract::CudaModuleLaunchContract;
+use crate::cuda_module::launchers::{cuda_kernel_marker_name, generic_arguments};
+use proc_macro2::TokenStream as TokenStream2;
+use quote::quote;
+use syn::{FnArg, GenericArgument, Ident, ItemFn, Pat, PathArguments, Token, Type, parse_quote};
+
+pub(crate) struct CudaModuleKernel {
+    pub(super) module_path: Vec<Ident>,
+    pub(super) vis: syn::Visibility,
+    /// Availability attributes written directly on the kernel. Generated
+    /// fields and methods live in the same module, so ancestor attributes are
+    /// already inherited there.
+    pub(crate) cfg_attrs: Vec<syn::Attribute>,
+    /// Availability attributes from every enclosing inline module followed by
+    /// the kernel's own attributes. Root-level artifact references need the
+    /// complete chain because they live outside those child modules.
+    pub(crate) effective_cfg_attrs: Vec<syn::Attribute>,
+    pub(super) method_attrs: Vec<syn::Attribute>,
+    pub(super) unsafety: Option<Token![unsafe]>,
+    pub(crate) fn_name: Ident,
+    pub(super) generics: syn::Generics,
+    pub(super) params: Vec<CudaModuleParam>,
+    pub(super) cluster_dim: Option<(u32, u32, u32)>,
+    pub(super) cooperative: bool,
+    pub(super) launch_contract: Option<CudaModuleLaunchContract>,
+    pub(super) is_generic: bool,
+}
+
+pub(crate) struct CudaModuleParam {
+    pub(crate) name: Ident,
+    pub(crate) sync_host_ty: TokenStream2,
+    pub(crate) async_host_ty: TokenStream2,
+    pub(crate) marshal: CudaModuleParamMarshal,
+    pub(crate) mutable_slice: bool,
+    pub(crate) disjoint_slice_ty: Option<Type>,
+    pub(crate) disjoint_slice_elem: Option<TokenStream2>,
+    /// Declared type and carried scalar of a `Uniform<T>` parameter, used to
+    /// bound the generated impl by the sealed proof trait so a local type also
+    /// named `Uniform` cannot borrow the scalar host ABI.
+    pub(crate) uniform_ty: Option<Type>,
+    pub(crate) uniform_scalar: Option<TokenStream2>,
+    /// Integer classification of a scalar parameter's declared type, used to
+    /// decide which scalars may appear in `requires` relations. Always
+    /// `Other` for non-scalar parameters.
+    pub(crate) scalar_int: ScalarIntClass,
+}
+
+pub(crate) enum CudaModuleParamMarshal {
+    Scalar,
+    ReadOnlyDeviceBuffer {
+        elem_ty: TokenStream2,
+    },
+    WritableDeviceBuffer {
+        elem_ty: TokenStream2,
+    },
+    /// A writable buffer whose index space carries a runtime row width, so
+    /// the host supplies the width and the packet gains a third slot.
+    RowWidthDeviceBuffer {
+        elem_ty: TokenStream2,
+    },
+}
+
+/// Integer classification of a kernel scalar parameter as declared in source.
+///
+/// `requires` relations widen every operand to `u64`, which is lossless for
+/// unsigned scalars but raises sign-extension questions for signed ones, so
+/// v1 accepts only `Unsigned` scalars and rejects the rest at expansion time.
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub(crate) enum ScalarIntClass {
+    /// `u8`, `u16`, `u32`, `u64`, or `usize`.
+    Unsigned,
+    /// `i8`, `i16`, `i32`, `i64`, or `isize`.
+    Signed,
+    /// Anything else (floats, pointers, generics, non-scalar parameters).
+    Other,
+}
+
+pub(crate) fn scalar_int_class(ty: &Type) -> ScalarIntClass {
+    // A `Uniform<T>` parameter is marshalled as `T` and is evaluated as `T` on
+    // the host, so a relation over it has the same widening behaviour as one
+    // over the bare scalar.
+    if let Some(scalar) = cuda_module_uniform_scalar(ty)
+        && let Ok(scalar) = syn::parse2::<Type>(scalar)
+    {
+        return scalar_int_class(&scalar);
+    }
+
+    let Type::Path(type_path) = ty else {
+        return ScalarIntClass::Other;
+    };
+    if type_path.qself.is_some() {
+        return ScalarIntClass::Other;
+    }
+    let Some(ident) = type_path.path.get_ident() else {
+        return ScalarIntClass::Other;
+    };
+    match ident.to_string().as_str() {
+        "u8" | "u16" | "u32" | "u64" | "usize" => ScalarIntClass::Unsigned,
+        "i8" | "i16" | "i32" | "i64" | "isize" => ScalarIntClass::Signed,
+        _ => ScalarIntClass::Other,
+    }
+}
+
+pub(super) fn cuda_module_params(item_fn: &ItemFn) -> syn::Result<Vec<CudaModuleParam>> {
+    item_fn
+        .sig
+        .inputs
+        .iter()
+        .map(|arg| match arg {
+            FnArg::Receiver(receiver) => Err(syn::Error::new_spanned(
+                receiver,
+                "cuda_module kernels cannot take self parameters",
+            )),
+            FnArg::Typed(pat_type) => cuda_module_param_from_typed(pat_type),
+        })
+        .collect()
+}
+
+pub(crate) fn cuda_module_param_from_typed(
+    pat_type: &syn::PatType,
+) -> syn::Result<CudaModuleParam> {
+    let Pat::Ident(pat_ident) = &*pat_type.pat else {
+        return Err(syn::Error::new_spanned(
+            &pat_type.pat,
+            "cuda_module only supports simple identifier kernel parameters",
+        ));
+    };
+    let name = pat_ident.ident.clone();
+    let (sync_host_ty, async_host_ty, marshal) = cuda_module_host_type(&pat_type.ty)?;
+    let mutable_slice = cuda_module_slice_elem(&pat_type.ty).is_some_and(|(_, mutable)| mutable);
+    let disjoint_slice_elem = cuda_module_disjoint_slice_elem(&pat_type.ty);
+    let disjoint_slice_ty = disjoint_slice_elem
+        .as_ref()
+        .map(|_| pat_type.ty.as_ref().clone());
+    let uniform_scalar = cuda_module_uniform_scalar(&pat_type.ty);
+    let uniform_ty = uniform_scalar
+        .as_ref()
+        .map(|_| pat_type.ty.as_ref().clone());
+    Ok(CudaModuleParam {
+        name,
+        sync_host_ty,
+        async_host_ty,
+        marshal,
+        mutable_slice,
+        disjoint_slice_ty,
+        disjoint_slice_elem,
+        uniform_ty,
+        uniform_scalar,
+        scalar_int: scalar_int_class(&pat_type.ty),
+    })
+}
+
+fn cuda_module_host_type(
+    ty: &Type,
+) -> syn::Result<(TokenStream2, TokenStream2, CudaModuleParamMarshal)> {
+    let async_lifetime = cuda_module_async_lifetime();
+    if let Some((elem_ty, mutable)) = cuda_module_slice_elem(ty) {
+        let sync_host_ty = if mutable {
+            quote! { &mut ::cuda_core::DeviceBuffer<#elem_ty> }
+        } else {
+            quote! { &::cuda_core::DeviceBuffer<#elem_ty> }
+        };
+        let (async_host_ty, marshal) = if mutable {
+            (
+                quote! { &#async_lifetime mut impl ::cuda_host::KernelSliceArgMut<Elem = #elem_ty> },
+                CudaModuleParamMarshal::WritableDeviceBuffer {
+                    elem_ty: quote! { #elem_ty },
+                },
+            )
+        } else {
+            (
+                quote! { &#async_lifetime impl ::cuda_host::KernelSliceArg<Elem = #elem_ty> },
+                CudaModuleParamMarshal::ReadOnlyDeviceBuffer {
+                    elem_ty: quote! { #elem_ty },
+                },
+            )
+        };
+        return Ok((sync_host_ty, async_host_ty, marshal));
+    }
+
+    if let Some(elem_ty) = cuda_module_disjoint_slice_elem(ty) {
+        if cuda_module_disjoint_slice_has_row_width(ty) {
+            return Ok((
+                quote! { ::cuda_host::RowWidth<'_, #elem_ty> },
+                quote! { ::cuda_host::RowWidth<#async_lifetime, #elem_ty> },
+                CudaModuleParamMarshal::RowWidthDeviceBuffer {
+                    elem_ty: quote! { #elem_ty },
+                },
+            ));
+        }
+        return Ok((
+            quote! { &mut ::cuda_core::DeviceBuffer<#elem_ty> },
+            quote! { &#async_lifetime mut impl ::cuda_host::KernelSliceArgMut<Elem = #elem_ty> },
+            CudaModuleParamMarshal::WritableDeviceBuffer {
+                elem_ty: quote! { #elem_ty },
+            },
+        ));
+    }
+
+    // A `Uniform<T>` parameter is marshalled exactly like `T`. The host takes
+    // the bare scalar because the host is what makes the value uniform: one
+    // marshalled value reaches every thread of the launch.
+    if let Some(scalar) = cuda_module_uniform_scalar(ty) {
+        return Ok((
+            quote! { #scalar },
+            quote! { #scalar },
+            CudaModuleParamMarshal::Scalar,
+        ));
+    }
+
+    if matches!(ty, Type::Reference(_)) {
+        return Err(syn::Error::new_spanned(
+            ty,
+            "cuda_module only supports slice references; use &[T], &mut [T], DisjointSlice<T>, a raw pointer, or a by-value KernelScalar",
+        ));
+    }
+
+    Ok((
+        quote! { #ty },
+        quote! { #ty },
+        CudaModuleParamMarshal::Scalar,
+    ))
+}
+
+fn cuda_module_slice_elem(ty: &Type) -> Option<(TokenStream2, bool)> {
+    let Type::Reference(type_ref) = ty else {
+        return None;
+    };
+    let Type::Slice(slice) = &*type_ref.elem else {
+        return None;
+    };
+    let elem = &slice.elem;
+    Some((quote! { #elem }, type_ref.mutability.is_some()))
+}
+
+/// Scalar carried by a `Uniform<T>` kernel parameter, if the type is spelled
+/// that way.
+///
+/// The host method takes the bare `T`: the host is the source of the
+/// uniformity proof, since it marshals one value into the launch packet for
+/// the whole grid. `Uniform<T>` is `#[repr(transparent)]`, so the launch packet
+/// is byte-identical either way.
+fn cuda_module_uniform_scalar(ty: &Type) -> Option<TokenStream2> {
+    let Type::Path(type_path) = ty else {
+        return None;
+    };
+    let segment = type_path.path.segments.last()?;
+    if segment.ident != "Uniform" {
+        return None;
+    }
+    let PathArguments::AngleBracketed(args) = &segment.arguments else {
+        return None;
+    };
+    let scalar = args.args.iter().find_map(|arg| match arg {
+        GenericArgument::Type(ty) => Some(ty),
+        _ => None,
+    })?;
+    Some(quote! { #scalar })
+}
+
+/// True when a `DisjointSlice`'s index space carries a runtime row width.
+///
+/// Matched on the spelling of the index-space argument, exactly as the element
+/// type is. The spelling only selects the host ABI; `SpaceLayout` is what
+/// decides whether the device type really carries the width, and a mismatch
+/// between the two is a type error at the generated call rather than a silent
+/// packet-shape difference.
+fn cuda_module_disjoint_slice_has_row_width(ty: &Type) -> bool {
+    let Type::Path(type_path) = ty else {
+        return false;
+    };
+    let Some(segment) = type_path.path.segments.last() else {
+        return false;
+    };
+    if segment.ident != "DisjointSlice" {
+        return false;
+    }
+    let PathArguments::AngleBracketed(args) = &segment.arguments else {
+        return false;
+    };
+    let mut space = args.args.iter().filter_map(|arg| match arg {
+        GenericArgument::Type(ty) => Some(ty),
+        _ => None,
+    });
+    space.nth(1).is_some_and(|space| {
+        let Type::Path(space_path) = space else {
+            return false;
+        };
+        space_path.path.segments.last().is_some_and(|segment| {
+            segment.ident == "RuntimeRowMajorTiles" || segment.ident == "Runtime2DIndex"
+        })
+    })
+}
+
+fn cuda_module_disjoint_slice_elem(ty: &Type) -> Option<TokenStream2> {
+    let Type::Path(type_path) = ty else {
+        return None;
+    };
+    let segment = type_path.path.segments.last()?;
+    if segment.ident != "DisjointSlice" {
+        return None;
+    }
+    let PathArguments::AngleBracketed(args) = &segment.arguments else {
+        return None;
+    };
+    let type_args: Vec<_> = args
+        .args
+        .iter()
+        .filter_map(|arg| match arg {
+            GenericArgument::Type(ty) => Some(ty),
+            _ => None,
+        })
+        .collect();
+    let elem = *type_args.first()?;
+    Some(quote! { #elem })
+}
+
+/// Adds a semantic launch-domain proof for every writable device slice.
+///
+/// The macro only uses the outer `DisjointSlice` spelling to select the host
+/// ABI. The Rust compiler decides whether the *resolved, complete type* is a
+/// genuine cuda-device slice with a compatible index space. This makes type
+/// aliases work without letting a local look-alike bypass the contract.
+pub(super) fn add_cuda_module_disjoint_contract_bounds(
+    generics: &mut syn::Generics,
+    params: &[CudaModuleParam],
+    domain: u8,
+) {
+    for param in params {
+        let (Some(device_ty), Some(element_ty)) =
+            (&param.disjoint_slice_ty, &param.disjoint_slice_elem)
+        else {
+            continue;
+        };
+        let (device_ty, bound_lifetime) = cuda_module_disjoint_bound_type(device_ty);
+        generics.make_where_clause().predicates.push(parse_quote! {
+            for<#bound_lifetime> #device_ty:
+                ::cuda_device::__LaunchContractDisjointSlice<#element_ty, #domain>
+        });
+    }
+}
+
+/// Requires every `DisjointSlice` parameter's resolved type to carry exactly
+/// the launch-packet shape the macro chose for it.
+///
+/// The macro picks the two-word `(ptr, len)` or three-word `(ptr, len, width)`
+/// host marshalling from the index space's spelling, which type aliases can
+/// defeat: `type Rt = RuntimeRowMajorTiles<1, 1>;` spells a flat slice over a
+/// runtime-width space, and the launch would then push two kernel parameters
+/// for a three-parameter kernel, making the driver read past the argument
+/// array. The sealed `__LaunchContractDisjointSliceAbi` trait is the semantic
+/// authority: only the genuine `DisjointSlice` whose index space really has
+/// (`true`) or really lacks (`false`) a runtime row width satisfies the bound, so
+/// a spelling/semantics mismatch is a compile error instead of a malformed
+/// launch packet.
+pub(super) fn add_cuda_module_disjoint_abi_bounds(
+    generics: &mut syn::Generics,
+    params: &[CudaModuleParam],
+) {
+    for param in params {
+        let (Some(device_ty), Some(element_ty)) =
+            (&param.disjoint_slice_ty, &param.disjoint_slice_elem)
+        else {
+            continue;
+        };
+        let has_row_width = matches!(
+            param.marshal,
+            CudaModuleParamMarshal::RowWidthDeviceBuffer { .. }
+        );
+        let (device_ty, bound_lifetime) = cuda_module_disjoint_bound_type(device_ty);
+        generics.make_where_clause().predicates.push(parse_quote! {
+            for<#bound_lifetime> #device_ty:
+                ::cuda_device::__LaunchContractDisjointSliceAbi<#element_ty, #has_row_width>
+        });
+    }
+}
+
+/// Requires every `Uniform<T>` parameter to be cuda-device's own type.
+///
+/// The host ABI for these parameters is chosen from the spelling `Uniform<T>`,
+/// so without this bound a local type of the same name would be marshalled as
+/// a bare `T` while presenting whatever layout it liked.
+pub(super) fn add_cuda_module_uniform_bounds(
+    generics: &mut syn::Generics,
+    params: &[CudaModuleParam],
+) {
+    for param in params {
+        let (Some(device_ty), Some(scalar_ty)) = (&param.uniform_ty, &param.uniform_scalar) else {
+            continue;
+        };
+        generics.make_where_clause().predicates.push(parse_quote! {
+            #device_ty: ::cuda_device::__LaunchContractUniform<#scalar_ty>
+        });
+    }
+}
+
+/// Makes the elided `DisjointSlice` lifetime explicit so the complete device
+/// type can appear in an impl-level where-clause.
+fn cuda_module_disjoint_bound_type(ty: &Type) -> (Type, syn::Lifetime) {
+    let mut ty = ty.clone();
+    let Type::Path(type_path) = &mut ty else {
+        unreachable!("only recognized DisjointSlice paths reach this helper");
+    };
+    let segment = type_path
+        .path
+        .segments
+        .last_mut()
+        .expect("recognized DisjointSlice path has a final segment");
+    let PathArguments::AngleBracketed(args) = &mut segment.arguments else {
+        unreachable!("recognized DisjointSlice path has generic arguments");
+    };
+    let bound_ident = internal_ident("__cuda_oxide_disjoint");
+    let bound_lifetime = syn::Lifetime::new(&format!("'{}", bound_ident), bound_ident.span());
+    if let Some(GenericArgument::Lifetime(lifetime)) = args.args.first_mut() {
+        *lifetime = bound_lifetime.clone();
+    } else {
+        let previous = core::mem::take(&mut args.args);
+        args.args
+            .push(GenericArgument::Lifetime(bound_lifetime.clone()));
+        args.args.extend(previous);
+    }
+    (ty, bound_lifetime)
+}
+
+pub(super) fn cuda_module_kernel_marker_type(kernel: &CudaModuleKernel) -> TokenStream2 {
+    let marker = cuda_kernel_marker_name(&kernel.fn_name);
+    if !kernel.is_generic {
+        return quote! { #marker };
+    }
+    let marker_args = generic_arguments(&kernel.generics);
+    if marker_args.is_empty() {
+        quote! { #marker }
+    } else {
+        quote! { #marker<#(#marker_args),*> }
+    }
+}
diff --git a/crates/cuda-macros/src/device.rs b/crates/cuda-macros/src/device.rs
new file mode 100644
index 0000000000..bda0e02b18
--- /dev/null
+++ b/crates/cuda-macros/src/device.rs
@@ -0,0 +1,323 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! `#[device]` functions and extern blocks, plus `#[constant]` statics.
+
+use crate::common::{impl_trait_parameter_error, reject_reserved_name, track_codegen_environment};
+use crate::cuda_module::constants::extract_constant_inner_ty;
+use crate::cuda_module::launchers::{codegen_generic_arguments, has_codegen_generics};
+use crate::kernel::scope::{forwarding_inputs, inject_device_thread_index_scope};
+use crate::launch_attrs::rewrite_loop_unroll_attrs;
+use proc_macro::TokenStream;
+use quote::{format_ident, quote};
+use reserved_oxide_symbols::{DEVICE_EXTERN_PREFIX, DEVICE_PREFIX, constant_symbol};
+use syn::{
+    ForeignItem, Ident, ItemFn, ItemForeignMod, LitStr, Token,
+    parse::{Parse, ParseStream},
+    parse_macro_input,
+};
+
+struct ConstantArgs {
+    export_name: Option<LitStr>,
+}
+
+impl Parse for ConstantArgs {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        if input.is_empty() {
+            return Ok(Self { export_name: None });
+        }
+
+        let key: Ident = input.parse()?;
+        if key != "export_name" {
+            return Err(syn::Error::new_spanned(
+                key,
+                "#[constant] does not take public arguments",
+            ));
+        }
+        input.parse::<Token![=]>()?;
+        let export_name = input.parse()?;
+        if !input.is_empty() {
+            input.parse::<Token![,]>()?;
+            if !input.is_empty() {
+                return Err(input.error("unexpected tokens after #[constant] export_name"));
+            }
+        }
+        Ok(Self {
+            export_name: Some(export_name),
+        })
+    }
+}
+
+pub(crate) fn constant_entry(attr: TokenStream, item: TokenStream) -> TokenStream {
+    track_codegen_environment();
+    let args = parse_macro_input!(attr as ConstantArgs);
+    let input = parse_macro_input!(item as syn::ItemStatic);
+
+    if let Some(err) = reject_reserved_name(&input.ident) {
+        return err;
+    }
+
+    if extract_constant_inner_ty(&input.ty).is_none() {
+        return syn::Error::new_spanned(
+            &input.ty,
+            "#[constant] static must have type `ConstantMemory<T>` \
+             (e.g. `static FOO: ConstantMemory<[f32; 4]> = ConstantMemory::UNINIT;`). \
+             The wrapper prevents the compiler from constant-folding the \
+             initializer into kernel bodies.",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    let export_name = args.export_name.unwrap_or_else(|| {
+        LitStr::new(
+            &constant_symbol(&input.ident.to_string()),
+            input.ident.span(),
+        )
+    });
+
+    quote! {
+        #[unsafe(export_name = #export_name)]
+        #input
+    }
+    .into()
+}
+
+pub(crate) fn device_entry(_attr: TokenStream, item: TokenStream) -> TokenStream {
+    track_codegen_environment();
+    // Try parsing as a function definition first
+    if let Ok(input) = syn::parse::<ItemFn>(item.clone()) {
+        return generate_device_function(input);
+    }
+
+    // Try parsing as an extern block
+    if let Ok(input) = syn::parse::<ItemForeignMod>(item.clone()) {
+        return generate_device_extern_block(input);
+    }
+
+    // Neither worked - emit error
+    syn::Error::new_spanned(
+        proc_macro2::TokenStream::from(item),
+        "#[device] can only be applied to functions or extern blocks",
+    )
+    .to_compile_error()
+    .into()
+}
+
+/// Generate a device function definition.
+///
+/// Renames the function into the reserved `cuda_oxide_device_<hash>_` namespace
+/// for collector detection, and generates a thin wrapper with the original name
+/// so user code can call `my_func()` rather than the mangled internal symbol.
+///
+/// Handles both non-generic and generic device functions:
+/// - **Non-generic**: `#[no_mangle]` on the prefixed function, `#[inline(always)]` wrapper.
+/// - **Generic**: No `#[no_mangle]` (generics use mangled symbols), `#[inline(never)]` on
+///   the prefixed function (so monomorphizations appear in CGUs for the collector),
+///   `#[inline(always)]` wrapper with generics + turbofish forwarding.
+///
+/// This mirrors the pattern used by `#[kernel]` for generic kernels
+/// (see `generate_generic_kernel_no_instantiation`).
+fn generate_device_function(mut input: ItemFn) -> TokenStream {
+    if let Some(err) = reject_reserved_name(&input.sig.ident) {
+        return err;
+    }
+    if let Some(err) = impl_trait_parameter_error(&input, "device function") {
+        return err.to_compile_error().into();
+    }
+    if let Err(err) = rewrite_loop_unroll_attrs(&mut input) {
+        return err.to_compile_error().into();
+    }
+    inject_device_thread_index_scope(&mut input);
+
+    let fn_name = input.sig.ident.clone();
+    let vis = input.vis.clone();
+    let new_name = format_ident!("{}{}", DEVICE_PREFIX, fn_name);
+
+    // Type and const parameters both create device monomorphizations.
+    let has_generics = has_codegen_generics(&input.sig.generics);
+
+    let return_type = &input.sig.output;
+    let generics = &input.sig.generics;
+    let where_clause = &input.sig.generics.where_clause;
+    let constness = &input.sig.constness;
+    let unsafety = &input.sig.unsafety;
+    let abi = &input.sig.abi;
+
+    let (wrapper_inputs, params) = match forwarding_inputs(&input.sig.inputs) {
+        Ok(forwarding) => forwarding,
+        Err(err) => return err.to_compile_error().into(),
+    };
+
+    // Rename the original function with the prefix
+    input.sig.ident = new_name.clone();
+
+    if has_generics {
+        // Generic device function: mirrors the generic kernel pattern.
+        //
+        // - No #[no_mangle] — generic functions use mangled symbol names per
+        //   monomorphization (e.g., `cuda_oxide_device_<hash>_add::<f32>` gets a
+        //   unique mangled name). #[no_mangle] requires a single concrete symbol.
+        //
+        // - #[inline(never)] on the prefixed function — ensures each monomorphization
+        //   appears as a distinct CGU item so the collector can find it. If it were
+        //   inlined, the function would disappear from the CGU.
+        //
+        // - The wrapper forwards type parameters via turbofish:
+        //   `cuda_oxide_device_<hash>_add::<T>(a, b)`.
+
+        let codegen_args = codegen_generic_arguments(generics);
+        let turbofish = quote! { ::<#(#codegen_args),*> };
+        let call = quote! { #new_name #turbofish (#(#params),*) };
+        let call = if unsafety.is_some() {
+            quote! { unsafe { #call } }
+        } else {
+            call
+        };
+
+        let expanded = quote! {
+            #[inline(never)]
+            #input
+
+            /// Wrapper for the generic device function with the original name.
+            #[inline(always)]
+            #vis #constness #unsafety #abi fn #fn_name #generics (#(#wrapper_inputs),*) #return_type #where_clause {
+                #call
+            }
+        };
+
+        TokenStream::from(expanded)
+    } else {
+        let call = quote! { #new_name(#(#params),*) };
+        let call = if unsafety.is_some() {
+            quote! { unsafe { #call } }
+        } else {
+            call
+        };
+        // Non-generic device function: simple case.
+        let expanded = quote! {
+            #[unsafe(no_mangle)]
+            #input
+
+            /// Wrapper for the device function with the original name.
+            #[inline(always)]
+            #vis #constness #unsafety #abi fn #fn_name #generics (#(#wrapper_inputs),*) #return_type #where_clause {
+                #call
+            }
+        };
+
+        TokenStream::from(expanded)
+    }
+}
+
+/// Generate device extern block declarations (for FFI with external LTOIR).
+///
+/// For each function in the extern block:
+/// 1. Rename it into the reserved `cuda_oxide_device_extern_<hash>_` namespace
+///    (for collector detection)
+/// 2. Generate a wrapper function with the original name (for user code)
+///
+/// User code calls `foo()` while the collector sees the hash-suffixed reserved
+/// form. The `#[link_name]` attribute restores the original name in the binary
+/// so external LTOIR resolves correctly.
+fn generate_device_extern_block(mut input: ItemForeignMod) -> TokenStream {
+    // Device extern declarations use CUDA's C calling convention. Reject
+    // other Rust ABIs because their argument and return conventions may differ.
+    if input
+        .abi
+        .name
+        .as_ref()
+        .is_some_and(|name| name.value() != "C")
+    {
+        return syn::Error::new_spanned(
+            &input.abi,
+            "#[device] extern blocks must use `extern \"C\"`",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    let mut wrappers = Vec::new();
+
+    // Process each item in the extern block
+    for item in &mut input.items {
+        if let ForeignItem::Fn(foreign_fn) = item {
+            if let Some(err) = reject_reserved_name(&foreign_fn.sig.ident) {
+                return err;
+            }
+
+            // `...` is purely syntactic, so it can be refused here rather than
+            // in device codegen. That gives the user a span on the offending
+            // tokens instead of a signature-less error at final-binary codegen,
+            // and it also catches a variadic extern that is declared but never
+            // called -- the collector only registers externs reached from
+            // kernel MIR, so that one used to compile clean.
+            //
+            // The codegen rejection stays: the collector recognises device
+            // externs by their reserved name prefix, so a hand-written extern
+            // block never passes through this macro at all.
+            if let Some(variadic) = &foreign_fn.sig.variadic {
+                return syn::Error::new_spanned(variadic, "#[device] externs cannot be variadic")
+                    .to_compile_error()
+                    .into();
+            }
+
+            // Save original info for wrapper generation
+            let original_name = foreign_fn.sig.ident.clone();
+            let original_attrs = foreign_fn.attrs.clone();
+            let original_sig = foreign_fn.sig.clone();
+
+            let new_name = format_ident!("{}{}", DEVICE_EXTERN_PREFIX, original_name);
+            foreign_fn.sig.ident = new_name.clone();
+
+            // Store original name as link_name for the linker
+            let original_name_str = original_name.to_string();
+            foreign_fn.attrs.push(syn::parse_quote! {
+                #[doc(hidden)]
+            });
+            foreign_fn.attrs.push(syn::parse_quote! {
+                #[link_name = #original_name_str]
+            });
+
+            // Generate wrapper function with the original name. User code
+            // calls `foo()`; the wrapper forwards to the reserved internal
+            // symbol the macro just produced.
+            let params: Vec<_> = original_sig
+                .inputs
+                .iter()
+                .filter_map(|arg| {
+                    if let syn::FnArg::Typed(pat_type) = arg
+                        && let syn::Pat::Ident(pat_ident) = &*pat_type.pat
+                    {
+                        return Some(pat_ident.ident.clone());
+                    }
+                    None
+                })
+                .collect();
+
+            let return_type = &original_sig.output;
+            let inputs = &original_sig.inputs;
+
+            // Keep user's attributes (like #[convergent]) on the wrapper
+            let wrapper = quote! {
+                #(#original_attrs)*
+                #[inline(always)]
+                #[allow(non_snake_case)]
+                pub unsafe fn #original_name(#inputs) #return_type {
+                    #new_name(#(#params),*)
+                }
+            };
+            wrappers.push(wrapper);
+        }
+    }
+
+    let expanded = quote! {
+        #input
+
+        #(#wrappers)*
+    };
+
+    TokenStream::from(expanded)
+}
diff --git a/crates/cuda-macros/src/kernel/codegen.rs b/crates/cuda-macros/src/kernel/codegen.rs
new file mode 100644
index 0000000000..4ca8f69fff
--- /dev/null
+++ b/crates/cuda-macros/src/kernel/codegen.rs
@@ -0,0 +1,687 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Kernel body generation: simple kernels, generic instantiations, and
+//! the hidden device twins.
+
+use crate::common::{attr_path_ends_with, internal_ident};
+use crate::cuda_module::launchers::{
+    codegen_generic_arguments, generic_arguments, generic_phantom_type,
+};
+use crate::kernel::scope::{
+    append_kernel_scope_parameter, explicit_kernel_scope, explicit_kernel_scope_bindings,
+    find_closure_generic, find_closure_param, forwarding_inputs, inject_thread_index_scope,
+    is_unchecked_indexing_config_marker, kernel_scope_binding, rewrite_thread_index_calls,
+    strip_unchecked_indexing_config_marker, top_level_kernel_configuration_markers,
+    unchecked_indexing_impl_clone,
+};
+use crate::launch_attrs::validate_routed_launch_contract_requires;
+use proc_macro::TokenStream;
+use proc_macro2::TokenStream as TokenStream2;
+use quote::{format_ident, quote};
+use reserved_oxide_symbols::{INSTANTIATE_PREFIX, KERNEL_PREFIX};
+use syn::{FnArg, GenericParam, Ident, ItemFn, Pat, Type};
+
+/// Generate a generic kernel that will be instantiated from call sites (nvcc-style)
+pub(super) fn generate_generic_kernel_no_instantiation(
+    input: ItemFn,
+    explicit_scope: Option<Ident>,
+) -> TokenStream {
+    generic_kernel_no_instantiation_tokens(input, explicit_scope).into()
+}
+
+/// Expansion body of [`generate_generic_kernel_no_instantiation`], split out
+/// so unit tests can inspect the generated items without a live proc-macro
+/// bridge.
+pub(crate) fn generic_kernel_no_instantiation_tokens(
+    mut input: ItemFn,
+    explicit_scope: Option<Ident>,
+) -> TokenStream2 {
+    let entry_inputs = input.sig.inputs.clone();
+    // A routed `#[launch_contract]` expands later on the generated entry
+    // wrapper, whose synthetic parameter names cannot resolve source-level
+    // `requires` identifiers, so those relations are validated here while the
+    // original signature is still in scope.
+    if let Err(error) = validate_routed_launch_contract_requires(&input.attrs, &entry_inputs) {
+        return error.to_compile_error();
+    }
+    let has_explicit_scope = explicit_scope.is_some();
+    let rewritten_scope = if let Some(ident) = explicit_scope {
+        Some(explicit_kernel_scope(&mut input, ident))
+    } else {
+        rewrite_thread_index_calls(&mut input, false)
+    };
+    if let Some(scope) = &rewritten_scope {
+        append_kernel_scope_parameter(&mut input, scope);
+    }
+
+    // Attributes written below `#[kernel]` still belong to the source item
+    // when this macro runs. Route CUDA entry directives to the generated entry
+    // function, keep ordinary Rust attributes on the user-facing
+    // implementation, and copy cfg gates to every generated item.
+    let (implementation_attrs, entry_attrs, cfg_attrs) = route_generic_kernel_attrs(&input.attrs);
+    let entry_config_markers = top_level_kernel_configuration_markers(&input);
+    // The unchecked-indexing marker may only live in generated kernel entry
+    // functions and their hidden unchecked twin, never in the user-named
+    // implementation helper: a marker left in the helper would extend
+    // bounds-check elision to every other kernel that calls (and inlines)
+    // the helper, without those kernels opting in.
+    let unchecked_indexing = input
+        .block
+        .stmts
+        .iter()
+        .any(is_unchecked_indexing_config_marker);
+    if unchecked_indexing {
+        strip_unchecked_indexing_config_marker(&mut input);
+    }
+    let unchecked_impl =
+        unchecked_indexing.then(|| unchecked_indexing_impl_clone(&input, &implementation_attrs));
+    // The entry calls the hidden twin, so a private opted kernel's user-named
+    // helper may otherwise be dead code; it stays emitted (bounds-checked)
+    // for other device code to call.
+    let helper_dead_code = if unchecked_indexing {
+        quote! { #[allow(dead_code)] }
+    } else {
+        quote! {}
+    };
+    let fn_name = &input.sig.ident;
+    let vis = &input.vis;
+    let generics = &input.sig.generics;
+    let where_clause = &input.sig.generics.where_clause;
+    let inputs = &input.sig.inputs;
+    let output = &input.sig.output;
+    let constness = &input.sig.constness;
+    let unsafety = &input.sig.unsafety;
+    let abi = &input.sig.abi;
+    let block = &input.block;
+
+    let kernel_name = format_ident!("{}{}", KERNEL_PREFIX, fn_name);
+    let instantiate_name = format_ident!("{}{}", INSTANTIATE_PREFIX, fn_name);
+
+    let (wrapper_inputs, arg_names) = match forwarding_inputs(&entry_inputs) {
+        Ok(forwarding) => forwarding,
+        Err(err) => return err.to_compile_error(),
+    };
+    let args_info: Vec<_> = arg_names
+        .iter()
+        .zip(entry_inputs.iter())
+        .filter_map(|(name, arg)| {
+            let FnArg::Typed(pat_type) = arg else {
+                return None;
+            };
+            Some((name, &*pat_type.ty))
+        })
+        .collect();
+
+    // Find the closure generic type (looks for Fn/FnMut/FnOnce bounds)
+    let closure_generic = find_closure_generic(generics);
+
+    // Function turbofish arguments contain both types and consts in source
+    // order. Lifetimes are inferred and therefore do not appear here.
+    let codegen_args = codegen_generic_arguments(generics);
+    let kernel_turbofish = if codegen_args.is_empty() {
+        quote! {}
+    } else {
+        quote! { ::<#(#codegen_args),*> }
+    };
+    let ptx_name_fn = format_ident!("{}_ptx_name", fn_name);
+    let instantiate_helper = if let Some(closure_type_name) = closure_generic {
+        if let Some((_closure_idx, (_closure_name, closure_type))) =
+            find_closure_param(&args_info, &closure_type_name)
+        {
+            quote! {
+                /// Auto-generated helper to force kernel monomorphization.
+                ///
+                /// Takes the closure by *reference* so its anonymous type
+                /// is bound to the generic parameter `F` at the call site
+                /// without moving the closure — the caller still needs the
+                /// closure value to push as the kernel argument right
+                /// after. Then forces rustc to emit a CGU entry for the
+                /// concrete `#kernel_name::<...>` instantiation. Returns
+                /// the PTX export name produced by the kernel's
+                /// `GenericCudaKernel::ptx_name()` impl, which is the
+                /// single source of truth for the on-wire name on the
+                /// host side.
+                ///
+                /// Bound is intentionally not `'static`: closures that
+                /// borrow non-`'static` data (e.g. capture `&[T]`) still
+                /// monomorphize cleanly. The caller is responsible for
+                /// keeping that borrow alive across the asynchronous
+                /// launch — `cuda_host::type_id_u128` does not enforce
+                /// this.
+                #[doc(hidden)]
+                #(#cfg_attrs)*
+                #[inline(never)]
+                #vis fn #instantiate_name #generics (_: &#closure_type) -> &'static str #where_clause {
+                    #ptx_name_fn #kernel_turbofish ()
+                }
+            }
+        } else {
+            quote! {}
+        }
+    } else {
+        quote! {}
+    };
+
+    // Generate the GenericCudaKernel trait implementation for unified compilation
+    let generic_cuda_kernel_impl =
+        generate_generic_cuda_kernel_impl(fn_name, vis, generics, where_clause, &cfg_attrs);
+    let mut implementation_args: Vec<TokenStream2> =
+        arg_names.iter().map(|name| quote! { #name }).collect();
+    if let Some(scope) = &rewritten_scope {
+        let scope_ident = &scope.ident;
+        if has_explicit_scope {
+            implementation_args.push(quote! { #scope_ident });
+        } else {
+            implementation_args.push(quote! { &#scope_ident });
+        }
+    }
+    let scope_bindings = rewritten_scope
+        .as_ref()
+        .map(|scope| {
+            if has_explicit_scope {
+                explicit_kernel_scope_bindings(scope)
+            } else {
+                vec![kernel_scope_binding(scope)]
+            }
+        })
+        .unwrap_or_default();
+    // An opted-in kernel's entry calls the hidden unchecked twin; everyone
+    // else (user code included) calls the user-named, bounds-checked helper.
+    let (implementation_target, unchecked_impl_item) = match &unchecked_impl {
+        Some((clone_name, tokens)) => (quote! { #clone_name }, tokens.clone()),
+        None => (quote! { #fn_name }, quote! {}),
+    };
+    let implementation_call =
+        quote! { #implementation_target #kernel_turbofish (#(#implementation_args),*) };
+    let implementation_call = if unsafety.is_some() {
+        quote! { unsafe { #implementation_call } }
+    } else {
+        implementation_call
+    };
+
+    quote! {
+        // Original generic kernel implementation
+        #(#implementation_attrs)*
+        #helper_dead_code
+        #[inline(always)]
+        #vis #constness #unsafety #abi fn #fn_name #generics (#inputs) #output #where_clause
+        #block
+
+        #unchecked_impl_item
+
+        // Entry point for collector - NOT inlined so we can detect it
+        // When called with concrete types, this instantiates the kernel
+        // Synthetic wrapper parameter names make every irrefutable source
+        // pattern forwardable without carrying local binding `mut`.
+        #(#entry_attrs)*
+        #[inline(never)]
+        #vis #constness #unsafety #abi fn #kernel_name #generics (#(#wrapper_inputs),*) #output #where_clause {
+            #(#entry_config_markers)*
+            #(#scope_bindings)*
+            #implementation_call
+        }
+
+        #instantiate_helper
+
+        #generic_cuda_kernel_impl
+    }
+}
+
+/// Route attributes when one generic source function becomes several items.
+///
+/// CUDA entry directives must decorate the generated collector entry, not the
+/// inline implementation helper. Configuration gates must decorate every item
+/// to avoid leaving a marker or helper behind for a disabled kernel. Other
+/// user-facing attributes (documentation, lints, deprecation, etc.) stay on
+/// the implementation with the original Rust name.
+pub(crate) fn route_generic_kernel_attrs(
+    attrs: &[syn::Attribute],
+) -> (
+    Vec<syn::Attribute>,
+    Vec<syn::Attribute>,
+    Vec<syn::Attribute>,
+) {
+    let is_cfg = |attr: &syn::Attribute| {
+        attr_path_ends_with(attr, "cfg") || attr_path_ends_with(attr, "cfg_attr")
+    };
+    let is_entry_directive = |attr: &syn::Attribute| {
+        attr_path_ends_with(attr, "launch_bounds")
+            || attr_path_ends_with(attr, "launch_contract")
+            || attr_path_ends_with(attr, "cluster_launch")
+            || attr_path_ends_with(attr, "cooperative_launch")
+    };
+
+    let cfg_attrs = attrs.iter().filter(|attr| is_cfg(attr)).cloned().collect();
+    let implementation_attrs = attrs
+        .iter()
+        .filter(|attr| !is_entry_directive(attr) && !attr_path_ends_with(attr, "inline"))
+        .cloned()
+        .collect();
+    let entry_attrs = attrs
+        .iter()
+        .filter(|attr| is_cfg(attr) || is_entry_directive(attr))
+        .cloned()
+        .collect();
+
+    (implementation_attrs, entry_attrs, cfg_attrs)
+}
+
+/// Generate a dummy binding for a given type.
+/// Used by instantiate! helper to create zero-valued arguments.
+///
+/// The generated values are never actually executed - they exist only to force
+/// rustc to monomorphize the kernel with the correct types.
+fn _generate_dummy_binding(name: &Ident, ty: &Type) -> TokenStream2 {
+    match ty {
+        // Special case: &[T] or &mut [T] → empty slice literal
+        // (slices don't implement Default and can't be safely zeroed)
+        Type::Reference(type_ref) if matches!(&*type_ref.elem, Type::Slice(_)) => {
+            if let Type::Slice(slice) = &*type_ref.elem {
+                let elem_ty = &slice.elem;
+                if type_ref.mutability.is_some() {
+                    quote! { let #name: &mut [#elem_ty] = &mut []; }
+                } else {
+                    quote! { let #name: &[#elem_ty] = &[]; }
+                }
+            } else {
+                unreachable!()
+            }
+        }
+
+        // Everything else: use mem::zeroed()
+        // Safe because this code never actually runs - it only exists to
+        // force monomorphization of the kernel with the correct types.
+        _ => {
+            quote! { let #name: #ty = unsafe { core::mem::zeroed() }; }
+        }
+    }
+}
+
+/// Generate a simple non-generic kernel
+pub(super) fn generate_simple_kernel(
+    mut input: ItemFn,
+    explicit_scope: Option<Ident>,
+) -> TokenStream {
+    if let Some(ident) = explicit_scope {
+        let scope = explicit_kernel_scope(&mut input, ident);
+        let bindings = explicit_kernel_scope_bindings(&scope);
+        input.block.stmts.splice(0..0, bindings);
+    } else {
+        inject_thread_index_scope(&mut input);
+    }
+
+    let fn_name = input.sig.ident.clone();
+    let new_name = format_ident!("{}{}", KERNEL_PREFIX, fn_name);
+
+    // Clone the original function for the CudaKernel impl
+    let original_fn = input.clone();
+    input.sig.ident = new_name;
+
+    // PTX entry name is the unprefixed user name; the collector strips
+    // KERNEL_PREFIX when generating PTX.
+    let ptx_entry_name = fn_name.to_string();
+
+    // Generate the CudaKernel trait implementation (host-side only)
+    // This provides the PTX name for cuda_launch! to look up
+    let cuda_kernel_impl = generate_cuda_kernel_impl(
+        &fn_name,
+        &ptx_entry_name,
+        &original_fn,
+        cfg!(feature = "host"),
+    );
+
+    let expanded = quote! {
+        #[unsafe(no_mangle)]
+        #input
+
+        #cuda_kernel_impl
+    };
+
+    TokenStream::from(expanded)
+}
+
+/// Generate the GenericCudaKernel trait implementation for a generic kernel.
+///
+/// For generic kernels like `fn tile<T, const N: usize>()`, emits:
+///
+/// ```ignore
+/// pub struct __tile_CudaKernel<T, const N: usize>(PhantomData<*const T>);
+/// impl<T, const N: usize> GenericCudaKernel for __tile_CudaKernel<T, N> {
+///     fn ptx_name() -> &'static str {
+///         // "tile_TID_<hex32>" — one 32-char hash of the concrete
+///         // generated kernel function-item type.
+///     }
+/// }
+/// pub fn tile_ptx_name<T, const N: usize>() -> &'static str {
+///     // Retains `kernel_entry::<T, N>` and delegates to the marker above.
+/// }
+/// ```
+///
+/// The body computes the same string the backend writes into the PTX:
+/// `<base>_TID_<hex32>`, where `<hex32>` is
+/// `cuda_host::type_id_u128_of_val(&kernel_entry::<T, N>)` rendered as 32
+/// lowercase hex chars. The backend hashes the same concrete `FnDef` type,
+/// whose ordered generic arguments include both types and const values.
+///
+/// Bound on the impl is `where_clause` verbatim — typically `Copy` on
+/// each value-passed generic. We deliberately do not add `'static`:
+/// `type_id_u128` has bound `T: ?Sized`, so closure types that borrow
+/// non-`'static` data still satisfy the marker's bounds and can be
+/// launched through the typed `module.<kernel>(...)` path. Keeping the
+/// borrow alive across `stream.synchronize()` remains the caller's
+/// responsibility, exactly as it was under the previous `type_name`
+/// scheme.
+///
+/// Deliberately NOT gated by the `host` feature: generic kernels remain
+/// host-coupled by design for now, because the TypeId naming machinery
+/// lives in `cuda_host`.
+fn generate_generic_cuda_kernel_impl(
+    fn_name: &Ident,
+    vis: &syn::Visibility,
+    generics: &syn::Generics,
+    where_clause: &Option<syn::WhereClause>,
+    cfg_attrs: &[syn::Attribute],
+) -> TokenStream2 {
+    let marker_name = format_ident!("__{}_CudaKernel", fn_name);
+    let ptx_name_fn = format_ident!("{}_ptx_name", fn_name);
+    let kernel_name = format_ident!("{}{}", KERNEL_PREFIX, fn_name);
+    let base_name = fn_name.to_string();
+    let generic_params: Vec<_> = generics.params.iter().collect();
+    let marker_args = generic_arguments(generics);
+    let codegen_args = codegen_generic_arguments(generics);
+    let phantom_type = generic_phantom_type(generics);
+    let marker_type = if marker_args.is_empty() {
+        quote! { #marker_name }
+    } else {
+        quote! { #marker_name <#(#marker_args),*> }
+    };
+    let kernel_turbofish = if codegen_args.is_empty() {
+        quote! {}
+    } else {
+        quote! { ::<#(#codegen_args),*> }
+    };
+    let (impl_generics, _, _) = generics.split_for_impl();
+    let hash = internal_ident("__cuda_oxide_kernel_hash");
+    let kernel_ptr = internal_ident("__cuda_oxide_kernel_ptr");
+    let force_mono = internal_ident("__cuda_oxide_force_mono");
+
+    quote! {
+        /// Marker type for a generic kernel; implements `GenericCudaKernel`.
+        /// Its generic parameters mirror the kernel's generic parameters.
+        #(#cfg_attrs)*
+        #[doc(hidden)]
+        #[allow(non_camel_case_types)]
+        pub struct #marker_name<#(#generic_params),*>(
+            core::marker::PhantomData<#phantom_type>
+        ) #where_clause;
+
+        #(#cfg_attrs)*
+        impl #impl_generics ::cuda_host::GenericCudaKernel for #marker_type
+        #where_clause
+        {
+            fn ptx_name() -> &'static str {
+                let #hash = ::cuda_host::type_id_u128_of_val(
+                    &#kernel_name #kernel_turbofish
+                );
+                ::cuda_host::__intern_generic_kernel_name(#base_name, #hash)
+            }
+        }
+
+        /// Retains this concrete kernel specialization and returns its PTX entry name.
+        #(#cfg_attrs)*
+        #[inline(never)]
+        #vis fn #ptx_name_fn #generics () -> &'static str #where_clause {
+            let #kernel_ptr = #kernel_name #kernel_turbofish as *const ();
+            unsafe {
+                let mut #force_mono: *const () = ::core::ptr::null();
+                ::core::ptr::write_volatile(&mut #force_mono, #kernel_ptr);
+                let _ = ::core::ptr::read_volatile(&#force_mono);
+            }
+            <#marker_type as ::cuda_host::GenericCudaKernel>::ptx_name()
+        }
+    }
+}
+
+/// Generate the CudaKernel trait implementation for a kernel function.
+///
+/// This generates a marker struct that implements `CudaKernel`, allowing
+/// `cuda_launch!` to look up the PTX entry point name at compile time.
+///
+/// Emitted only under the `host` feature: the impl names `cuda_host`, and a
+/// crate that only compiles kernels never looks a PTX entry name up.
+pub(crate) fn generate_cuda_kernel_impl(
+    fn_name: &Ident,
+    ptx_name: &str,
+    _func: &ItemFn,
+    emit_host: bool,
+) -> TokenStream2 {
+    if !emit_host {
+        return TokenStream2::new();
+    }
+
+    // Create a marker struct for this kernel
+    // We use a struct because Rust doesn't allow trait impls on function pointers easily
+    let marker_name = format_ident!("__{}_CudaKernel", fn_name);
+
+    quote! {
+        /// Marker type for the kernel, implements CudaKernel trait.
+        /// This enables cuda_launch! to look up the PTX entry point name.
+        #[doc(hidden)]
+        #[allow(non_camel_case_types)]
+        pub struct #marker_name;
+
+        impl cuda_host::CudaKernel for #marker_name {
+            const PTX_NAME: &'static str = #ptx_name;
+        }
+    }
+}
+
+/// Generate wrapper kernels for a generic kernel
+pub(super) fn generate_generic_kernel(
+    input: ItemFn,
+    instantiate_types: Vec<Type>,
+    explicit_scope: Option<Ident>,
+) -> TokenStream {
+    generic_kernel_instantiation_tokens(input, instantiate_types, explicit_scope).into()
+}
+
+/// Expansion body of [`generate_generic_kernel`] (legacy `#[kernel(Type, ...)]`
+/// instantiation), split out so unit tests can inspect the generated items
+/// without a live proc-macro bridge.
+pub(crate) fn generic_kernel_instantiation_tokens(
+    mut input: ItemFn,
+    instantiate_types: Vec<Type>,
+    explicit_scope: Option<Ident>,
+) -> TokenStream2 {
+    let entry_inputs = input.sig.inputs.clone();
+    // Same as the no-instantiation path: `requires` relations of a routed
+    // `#[launch_contract]` must be validated against the source parameter
+    // names before they are lost to the generated wrappers.
+    if let Err(error) = validate_routed_launch_contract_requires(&input.attrs, &entry_inputs) {
+        return error.to_compile_error();
+    }
+    let has_explicit_scope = explicit_scope.is_some();
+    let rewritten_scope = if let Some(ident) = explicit_scope {
+        Some(explicit_kernel_scope(&mut input, ident))
+    } else {
+        rewrite_thread_index_calls(&mut input, false)
+    };
+    if let Some(scope) = &rewritten_scope {
+        append_kernel_scope_parameter(&mut input, scope);
+    }
+
+    let (implementation_attrs, entry_attrs, _cfg_attrs) = route_generic_kernel_attrs(&input.attrs);
+    let entry_config_markers = top_level_kernel_configuration_markers(&input);
+    input.attrs.clear();
+    // Same containment rule as the no-instantiation path: the marker never
+    // stays in the re-emitted user-named helper; opted entries call a hidden
+    // unchecked twin instead.
+    let unchecked_indexing = input
+        .block
+        .stmts
+        .iter()
+        .any(is_unchecked_indexing_config_marker);
+    if unchecked_indexing {
+        strip_unchecked_indexing_config_marker(&mut input);
+    }
+    let unchecked_impl =
+        unchecked_indexing.then(|| unchecked_indexing_impl_clone(&input, &implementation_attrs));
+    // The wrappers call the hidden twin, so a private opted kernel's
+    // user-named helper may otherwise be dead code; it stays emitted
+    // (bounds-checked) for other device code to call.
+    let helper_dead_code = if unchecked_indexing {
+        quote! { #[allow(dead_code)] }
+    } else {
+        quote! {}
+    };
+    let fn_name = &input.sig.ident;
+    let vis = &input.vis;
+    let generics = &input.sig.generics;
+    let (implementation_target, unchecked_impl_item) = match &unchecked_impl {
+        Some((clone_name, tokens)) => (quote! { #clone_name }, tokens.clone()),
+        None => (quote! { #fn_name }, quote! {}),
+    };
+
+    // Extract the type parameter name (assume single type param for now)
+    let type_param = generics
+        .params
+        .iter()
+        .find_map(|p| {
+            if let GenericParam::Type(tp) = p {
+                Some(&tp.ident)
+            } else {
+                None
+            }
+        })
+        .expect("Expected type parameter");
+
+    // Extract function arguments (excluding self)
+    let args: Vec<_> = entry_inputs.iter().collect();
+
+    // Build the argument pattern and types for wrappers
+    let arg_names: Vec<TokenStream2> = args
+        .iter()
+        .filter_map(|arg| {
+            if let FnArg::Typed(pat_type) = arg
+                && let Pat::Ident(pat_ident) = &*pat_type.pat
+            {
+                return Some(quote! { #pat_ident });
+            }
+            None
+        })
+        .collect();
+
+    // For each instantiation type, generate a wrapper that substitutes the type
+    let wrappers: Vec<TokenStream2> = instantiate_types
+        .iter()
+        .map(|inst_type| {
+            let entry_attrs = &entry_attrs;
+            let entry_config_markers = &entry_config_markers;
+            let implementation_target = &implementation_target;
+            // Get a clean name for the type (for the kernel name suffix)
+            let type_name = get_type_name(inst_type);
+            let wrapper_name = format_ident!("{}{}_{}", KERNEL_PREFIX, fn_name, type_name);
+
+            // Export name (what appears in PTX)
+            let export_name_str = format!("{}_{}", fn_name, type_name);
+            let scope_bindings = rewritten_scope
+                .as_ref()
+                .map(|scope| {
+                    if has_explicit_scope {
+                        explicit_kernel_scope_bindings(scope)
+                    } else {
+                        vec![kernel_scope_binding(scope)]
+                    }
+                })
+                .unwrap_or_default();
+            let mut implementation_args = arg_names.clone();
+            if let Some(scope) = &rewritten_scope {
+                let scope_ident = &scope.ident;
+                if has_explicit_scope {
+                    implementation_args.push(quote! { #scope_ident });
+                } else {
+                    implementation_args.push(quote! { &#scope_ident });
+                }
+            }
+
+            // Generate wrapper function args with substituted types
+            let wrapper_args: Vec<TokenStream2> = args
+                .iter()
+                .map(|arg| {
+                    if let FnArg::Typed(pat_type) = arg {
+                        let pat = &pat_type.pat;
+                        let ty = &pat_type.ty;
+                        // Substitute type parameter with concrete type
+                        let subst_ty = substitute_type(ty, type_param, inst_type);
+                        quote! { #pat: #subst_ty }
+                    } else {
+                        quote! { #arg }
+                    }
+                })
+                .collect();
+
+            quote! {
+                #(#entry_attrs)*
+                #[unsafe(no_mangle)]
+                #[unsafe(export_name = #export_name_str)]
+                #vis fn #wrapper_name(#(#wrapper_args),*) {
+                    #(#entry_config_markers)*
+                    #(#scope_bindings)*
+                    #implementation_target::<#inst_type>(#(#implementation_args),*);
+                }
+            }
+        })
+        .collect();
+
+    // Keep the original generic function (without #[no_mangle] - it's not an entry point)
+    // and add all the wrapper kernels
+    quote! {
+        #(#implementation_attrs)*
+        #helper_dead_code
+        #[inline(always)]
+        #input
+
+        #unchecked_impl_item
+
+        #(#wrappers)*
+    }
+}
+
+/// Get a clean name from a type for use in function names
+fn get_type_name(ty: &Type) -> String {
+    match ty {
+        Type::Path(type_path) => {
+            // Get the last segment (e.g., "Scale" from "crate::Scale")
+            type_path
+                .path
+                .segments
+                .last()
+                .map(|s| s.ident.to_string())
+                .unwrap_or_else(|| "Unknown".to_string())
+        }
+        _ => "Unknown".to_string(),
+    }
+}
+
+/// Substitute a type parameter with a concrete type in a type expression
+fn substitute_type(ty: &Type, param: &syn::Ident, replacement: &Type) -> TokenStream2 {
+    match ty {
+        Type::Path(type_path) => {
+            // Check if this is just the type parameter
+            if type_path.path.is_ident(param) {
+                return quote! { #replacement };
+            }
+            quote! { #ty }
+        }
+        Type::Reference(type_ref) => {
+            let elem = substitute_type(&type_ref.elem, param, replacement);
+            let lifetime = &type_ref.lifetime;
+            let mutability = &type_ref.mutability;
+            quote! { &#lifetime #mutability #elem }
+        }
+        _ => quote! { #ty },
+    }
+}
diff --git a/crates/cuda-macros/src/kernel/mod.rs b/crates/cuda-macros/src/kernel/mod.rs
new file mode 100644
index 0000000000..844730edeb
--- /dev/null
+++ b/crates/cuda-macros/src/kernel/mod.rs
@@ -0,0 +1,262 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! `#[kernel]` argument parsing, validation, and expansion dispatch.
+
+pub(crate) mod codegen;
+pub(crate) mod scope;
+
+use crate::common::{impl_trait_parameter_error, reject_reserved_name, track_codegen_environment};
+use crate::cuda_module::launchers::has_codegen_generics;
+use crate::kernel::codegen::{
+    generate_generic_kernel, generate_generic_kernel_no_instantiation, generate_simple_kernel,
+};
+use crate::launch_attrs::{add_launch_bounds_evaluatability_from_attrs, rewrite_loop_unroll_attrs};
+use proc_macro::TokenStream;
+use syn::{
+    FnArg, GenericParam, Ident, ItemFn, Token, Type,
+    parse::{Parse, ParseStream},
+    parse_macro_input,
+};
+
+/// Attribute arguments for `#[kernel(...)]`.
+///
+/// Legacy explicit-instantiation types, the optional launch-context binding,
+/// and the bare `unchecked_indexing` flag may appear in any order:
+///
+/// ```ignore
+/// #[kernel(launch_context = launch_context)]
+/// #[kernel(f32, f64, launch_context = launch_context)]
+/// #[kernel(unchecked_indexing)]
+/// #[kernel(f32, unchecked_indexing)]
+/// #[kernel(launch_context = launch_context, unchecked_indexing)]
+/// ```
+pub(crate) struct KernelArgs {
+    /// Types to instantiate generic kernels for
+    pub(crate) instantiate_types: Vec<Type>,
+    /// User-selected name for the entry's typed launch context.
+    pub(crate) launch_context: Option<Ident>,
+    /// Elide slice/array bounds checks in this kernel's body (UB contract).
+    pub(crate) unchecked_indexing: bool,
+}
+
+/// Returns true when the next attribute argument is exactly the bare flag
+/// word `flag` (an identifier followed by `,` or end of input, never `=`).
+///
+/// A bare identifier also parses as a `Type`, so this peek must run before
+/// the legacy instantiation-type fallback to keep flag words from being
+/// swallowed as type arguments.
+fn peek_bare_kernel_flag(input: ParseStream, flag: &str) -> bool {
+    if !input.peek(Ident) || input.peek2(Token![=]) {
+        return false;
+    }
+    let fork = input.fork();
+    match fork.parse::<Ident>() {
+        Ok(ident) => ident == flag && (fork.is_empty() || fork.peek(Token![,])),
+        Err(_) => false,
+    }
+}
+
+impl Parse for KernelArgs {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let mut instantiate_types = Vec::new();
+        let mut launch_context = None;
+        let mut unchecked_indexing = false;
+
+        while !input.is_empty() {
+            if input.peek(Ident) && input.peek2(Token![=]) {
+                let name: Ident = input.parse()?;
+                input.parse::<Token![=]>()?;
+                if name != "launch_context" {
+                    return Err(syn::Error::new(
+                        name.span(),
+                        format!(
+                            "unknown #[kernel] named argument `{name}`; expected `launch_context = IDENT`"
+                        ),
+                    ));
+                }
+                let value: Ident = input.parse().map_err(|_| {
+                    syn::Error::new(
+                        input.span(),
+                        "`launch_context` must be a single Rust identifier",
+                    )
+                })?;
+                if launch_context.replace(value).is_some() {
+                    return Err(syn::Error::new(
+                        name.span(),
+                        "duplicate `launch_context` argument in #[kernel]",
+                    ));
+                }
+            } else if peek_bare_kernel_flag(input, "unchecked_indexing") {
+                let flag: Ident = input.parse()?;
+                if unchecked_indexing {
+                    return Err(syn::Error::new(
+                        flag.span(),
+                        "duplicate `unchecked_indexing` argument in #[kernel]",
+                    ));
+                }
+                unchecked_indexing = true;
+            } else {
+                instantiate_types.push(input.parse::<Type>()?);
+            }
+
+            if input.is_empty() {
+                break;
+            }
+            input.parse::<Token![,]>()?;
+        }
+
+        Ok(KernelArgs {
+            instantiate_types,
+            launch_context,
+            unchecked_indexing,
+        })
+    }
+}
+
+fn scope_parameter_collision(input: &ItemFn, scope: &Ident) -> Option<Ident> {
+    struct Finder<'a> {
+        scope: &'a Ident,
+        found: Option<Ident>,
+    }
+
+    impl<'ast> syn::visit::Visit<'ast> for Finder<'_> {
+        fn visit_pat_ident(&mut self, pattern: &'ast syn::PatIdent) {
+            if self.found.is_none() && pattern.ident == *self.scope {
+                self.found = Some(pattern.ident.clone());
+            }
+            syn::visit::visit_pat_ident(self, pattern);
+        }
+    }
+
+    let mut finder = Finder { scope, found: None };
+    for argument in &input.sig.inputs {
+        if let FnArg::Typed(argument) = argument {
+            syn::visit::Visit::visit_pat(&mut finder, &argument.pat);
+        }
+    }
+    finder.found
+}
+
+pub(crate) fn kernel_entry(attr: TokenStream, item: TokenStream) -> TokenStream {
+    track_codegen_environment();
+    let args = parse_macro_input!(attr as KernelArgs);
+    let mut input = parse_macro_input!(item as ItemFn);
+
+    let KernelArgs {
+        instantiate_types,
+        launch_context,
+        unchecked_indexing,
+    } = args;
+
+    if let Some(err) = reject_reserved_name(&input.sig.ident) {
+        return err;
+    }
+    if let Some(err) = impl_trait_parameter_error(&input, "kernel") {
+        return err.to_compile_error().into();
+    }
+    if let Some(launch_context) = &launch_context
+        && let Some(parameter) = scope_parameter_collision(&input, launch_context)
+    {
+        return syn::Error::new_spanned(
+            parameter,
+            format!(
+                "kernel launch-context binding `{launch_context}` conflicts with a function parameter; choose a distinct name in `#[kernel(launch_context = ...)]`"
+            ),
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    // Consume any `#[unroll]` / `#[unroll(N)]` attributes written directly on
+    // loops inside the kernel body. We strip the attribute from the loop
+    // expression (so rustc never sees an expression attribute, keeping us off
+    // nightly `stmt_expr_attributes`) and inject an
+    // `__unroll_config::<FACTOR>()` marker into the loop body. If the visitor
+    // hits a malformed attribute it records the error so we can surface it as a
+    // compile error below.
+    if let Err(err) = rewrite_loop_unroll_attrs(&mut input) {
+        return err.to_compile_error().into();
+    }
+    if let Err(err) = add_launch_bounds_evaluatability_from_attrs(&mut input) {
+        return err.to_compile_error().into();
+    }
+
+    // Insert the unchecked-indexing compiler marker at the top of the kernel
+    // body. The MIR importer detects the call, elides bounds-check asserts in
+    // the translated body, and strips the call before code generation. For
+    // simple kernels the function itself becomes the entry, so the marker
+    // stays put. Generic kernel generation strips the marker from the
+    // re-emitted user-named implementation helper and confines it to the
+    // generated entry wrapper (forwarded via
+    // `top_level_kernel_configuration_markers`) plus a hidden unchecked twin
+    // of the implementation that only the entry calls; see
+    // `strip_unchecked_indexing_config_marker` and
+    // `unchecked_indexing_impl_clone`.
+    if unchecked_indexing {
+        let marker_call: syn::Stmt = syn::parse_quote! {
+            ::cuda_device::thread::__unchecked_indexing_config::<true>();
+        };
+        input.block.stmts.insert(0, marker_call);
+    }
+
+    // Only type and const parameters create distinct codegen instances.
+    // Lifetimes are erased before monomorphization.
+    let has_generics = has_codegen_generics(&input.sig.generics);
+
+    if has_generics && !instantiate_types.is_empty() {
+        let type_param_count = input
+            .sig
+            .generics
+            .params
+            .iter()
+            .filter(|param| matches!(param, GenericParam::Type(_)))
+            .count();
+        let has_const_params = input
+            .sig
+            .generics
+            .params
+            .iter()
+            .any(|param| matches!(param, GenericParam::Const(_)));
+        let has_lifetime_params = input
+            .sig
+            .generics
+            .params
+            .iter()
+            .any(|param| matches!(param, GenericParam::Lifetime(_)));
+        if type_param_count != 1 || has_const_params || has_lifetime_params {
+            return syn::Error::new_spanned(
+                &input.sig.generics,
+                "legacy #[kernel(Type, ...)] instantiation supports exactly one type parameter and no lifetime or const parameters; use #[kernel] and instantiate the kernel with a normal turbofish at the launch site",
+            )
+            .to_compile_error()
+            .into();
+        }
+    }
+
+    if has_generics && instantiate_types.is_empty() {
+        // Generic kernel without explicit types - allow it!
+        // Instantiation will happen from call sites (nvcc-style)
+        return generate_generic_kernel_no_instantiation(input, launch_context);
+    }
+
+    if !has_generics && !instantiate_types.is_empty() {
+        // Non-generic kernel with instantiation types - error
+        return syn::Error::new_spanned(
+            &input.sig.ident,
+            "Instantiation types only apply to generic kernels",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    if has_generics {
+        // Generate wrapper kernels for each instantiation type
+        generate_generic_kernel(input, instantiate_types, launch_context)
+    } else {
+        // Simple non-generic kernel
+        generate_simple_kernel(input, launch_context)
+    }
+}
diff --git a/crates/cuda-macros/src/kernel/scope.rs b/crates/cuda-macros/src/kernel/scope.rs
new file mode 100644
index 0000000000..587455bb5e
--- /dev/null
+++ b/crates/cuda-macros/src/kernel/scope.rs
@@ -0,0 +1,697 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Thread-index call rewriting, kernel launch-context scopes, and
+//! configuration-marker handling.
+
+use crate::common::{attr_path_ends_with, call_site_ident_avoiding_item, internal_ident};
+use crate::cuda_module::contract::LaunchContractArgs;
+use proc_macro2::TokenStream as TokenStream2;
+use quote::quote;
+use reserved_oxide_symbols::KERNEL_SCOPE_LOCAL;
+use syn::{
+    Expr, ExprCall, ExprMethodCall, ExprPath, FnArg, GenericArgument, Ident, ItemFn, Path,
+    PathArguments, Stmt, Type, parse_quote, parse_quote_spanned,
+    spanned::Spanned,
+    visit_mut::{self, VisitMut},
+};
+
+/// Find the generic type parameter that has a Fn/FnMut/FnOnce bound (the closure type).
+/// Returns the type parameter name if found.
+pub(super) fn find_closure_generic(generics: &syn::Generics) -> Option<syn::Ident> {
+    for param in &generics.params {
+        if let syn::GenericParam::Type(type_param) = param {
+            for bound in &type_param.bounds {
+                if is_fn_trait_bound(bound) {
+                    return Some(type_param.ident.clone());
+                }
+            }
+        }
+    }
+
+    if let Some(where_clause) = &generics.where_clause {
+        for predicate in &where_clause.predicates {
+            let syn::WherePredicate::Type(predicate_type) = predicate else {
+                continue;
+            };
+            if !predicate_type.bounds.iter().any(is_fn_trait_bound) {
+                continue;
+            }
+            let Type::Path(type_path) = &predicate_type.bounded_ty else {
+                continue;
+            };
+            if type_path.qself.is_none()
+                && type_path.path.segments.len() == 1
+                && let Some(segment) = type_path.path.segments.first()
+            {
+                return Some(segment.ident.clone());
+            }
+        }
+    }
+
+    None
+}
+
+fn is_fn_trait_bound(bound: &syn::TypeParamBound) -> bool {
+    let syn::TypeParamBound::Trait(trait_bound) = bound else {
+        return false;
+    };
+    trait_bound.path.segments.last().is_some_and(|segment| {
+        matches!(
+            segment.ident.to_string().as_str(),
+            "Fn" | "FnMut" | "FnOnce"
+        )
+    })
+}
+
+/// Find which function parameter uses the closure type.
+/// Returns the index and info of the closure parameter.
+pub(super) fn find_closure_param<'a>(
+    args_info: &'a [(&'a Ident, &'a Type)],
+    closure_type_name: &syn::Ident,
+) -> Option<(usize, &'a (&'a Ident, &'a Type))> {
+    for (idx, (_name, ty)) in args_info.iter().enumerate() {
+        // Check if the type is a simple path matching our closure generic
+        if let Type::Path(type_path) = *ty
+            && type_path.qself.is_none()
+            && let Some(segment) = type_path.path.segments.first()
+            && type_path.path.segments.len() == 1
+            && segment.ident == *closure_type_name
+        {
+            return Some((idx, &args_info[idx]));
+        }
+    }
+    None
+}
+
+/// Build wrapper parameters that can always be forwarded by value.
+///
+/// User functions may use any irrefutable parameter pattern, including `_` or
+/// tuple destructuring. A generated wrapper cannot refer to those patterns
+/// again, so every parameter gets a private synthetic identifier while keeping
+/// its original type and attributes. The original implementation retains the
+/// user's pattern.
+pub(crate) fn forwarding_inputs(
+    inputs: &syn::punctuated::Punctuated<FnArg, syn::token::Comma>,
+) -> syn::Result<(Vec<FnArg>, Vec<Ident>)> {
+    let mut wrapper_inputs = Vec::with_capacity(inputs.len());
+    let mut forwarding_names = Vec::with_capacity(inputs.len());
+
+    for (index, arg) in inputs.iter().enumerate() {
+        let FnArg::Typed(pat_type) = arg else {
+            return Err(syn::Error::new_spanned(
+                arg,
+                "CUDA kernels and device functions cannot take self parameters",
+            ));
+        };
+        let name = internal_ident(&format!("__cuda_oxide_arg_{index}"));
+        let mut wrapper_param = pat_type.clone();
+        wrapper_param.pat = Box::new(parse_quote! { #name });
+        wrapper_inputs.push(FnArg::Typed(wrapper_param));
+        forwarding_names.push(name);
+    }
+
+    Ok((wrapper_inputs, forwarding_names))
+}
+
+/// True when `path`'s *last* segment is `name`.
+///
+/// We deliberately match on the tail only, so all of these resolve to the
+/// same intrinsic:
+///
+/// ```ignore
+/// index_1d()
+/// thread::index_1d()
+/// cuda_device::thread::index_1d()
+/// ::cuda_device::thread::index_1d()
+/// ```
+///
+/// And imports/aliases work too:
+///
+/// ```ignore
+/// use cuda_device::thread::index_1d;          // bare ident → matches
+/// use cuda_device::thread::index_1d as foo;   // aliased    → won't match (path tail is `foo`)
+/// ```
+///
+/// The aliased form is intentionally not rewritten — if the user picked a
+/// new name, they get the bare-stub-panic behaviour, not silent capture.
+///
+/// Caveat: if the user defines a *local* `fn index_1d` (or any other
+/// reserved name) and calls it from inside `#[kernel]` / `#[device]`,
+/// that call gets rewritten too. See the `Reserved names` section in
+/// `ThreadIndex`'s doc-block — the convention is to pick a different
+/// name (e.g. `compute_index_1d`) for any helper you want to keep.
+fn is_thread_index_path(path: &Path, name: &str) -> bool {
+    path.segments.last().is_some_and(|seg| seg.ident == name)
+}
+
+/// Build the rewritten path that points the user's call at the
+/// `__internal::<name>` shim, preserving whatever prefix the user wrote.
+///
+/// The motivation is unused-import hygiene. If the user wrote
+/// `use cuda_device::thread;` and called `thread::index_1d()`, replacing
+/// the whole call with an absolute path makes rustc see the `thread`
+/// import as unused. Instead, we splice `__internal` in front of the
+/// last segment and keep everything before it intact:
+///
+/// ```text
+/// thread::index_1d()                   →  thread::__internal::index_1d(&scope)
+/// cuda_device::thread::index_1d()      →  cuda_device::thread::__internal::index_1d(&scope)
+/// ::cuda_device::thread::index_1d()    →  ::cuda_device::thread::__internal::index_1d(&scope)
+/// ```
+///
+/// Bare-ident calls are the only shape that can't carry a prefix, so for
+/// those we fall back to the absolute path (the user wasn't naming
+/// anything to import; see the bare-ident case in `is_thread_index_path`'s
+/// doc-comment for why we still rewrite those):
+///
+/// ```text
+/// index_1d()                           →  ::cuda_device::thread::__internal::index_1d(&scope)
+/// ```
+fn internal_thread_path(
+    user_path: &Path,
+    name: &str,
+    arguments: syn::PathArguments,
+    call_span: proc_macro2::Span,
+) -> Path {
+    let ident = Ident::new(name, call_span);
+    let internal = Ident::new("__internal", call_span);
+
+    if user_path.segments.len() == 1 {
+        let mut absolute: Path =
+            parse_quote_spanned! { call_span => ::cuda_device::thread::#internal::#ident };
+        if let Some(last) = absolute.segments.last_mut() {
+            last.arguments = arguments;
+        }
+        return absolute;
+    }
+
+    let leading_colon = user_path.leading_colon;
+    let prefix_segments: Vec<&syn::PathSegment> = user_path
+        .segments
+        .iter()
+        .take(user_path.segments.len() - 1)
+        .collect();
+    let mut rewritten: Path = parse_quote_spanned! {
+        call_span => #leading_colon #(#prefix_segments)::* :: #internal :: #ident
+    };
+    if let Some(last) = rewritten.segments.last_mut() {
+        last.arguments = arguments;
+    }
+    rewritten
+}
+
+/// One scoped intrinsic the rewriter knows about.
+///
+/// Adding a new `thread::*` function that needs the `'kernel` scope is a
+/// one-line entry here, plus the matching public stub and `__internal::*`
+/// impl in `cuda-device`.
+struct ScopedIntrinsic {
+    /// The unqualified function name (last segment of the path we match).
+    name: &'static str,
+    /// If true, copy the call-site's turbofish onto the rewritten path
+    /// (e.g. `index_2d::<S>` → `__internal::index_2d::<S>`).
+    preserve_turbofish: bool,
+    /// If true, forward the original call arguments after the scope ref
+    /// (e.g. `index_2d_runtime(s)` → `__internal::index_2d_runtime(&scope, s)`).
+    forward_args: bool,
+}
+
+const SCOPED_INTRINSICS: &[ScopedIntrinsic] = &[
+    ScopedIntrinsic {
+        name: "index_1d",
+        preserve_turbofish: false,
+        forward_args: false,
+    },
+    ScopedIntrinsic {
+        name: "index_2d",
+        preserve_turbofish: true,
+        forward_args: false,
+    },
+    ScopedIntrinsic {
+        name: "index_2d_runtime",
+        preserve_turbofish: false,
+        forward_args: true,
+    },
+    ScopedIntrinsic {
+        name: "warp_index",
+        preserve_turbofish: false,
+        forward_args: false,
+    },
+];
+
+/// Method names whose zero-arg call sites get the kernel scope spliced in
+/// as a leading `&scope` argument.
+///
+/// These are matched on the *method name only* (not the receiver type, which
+/// the macro can't see anyway). The scope is only injected when the user
+/// wrote a zero-arg call like `slice.get_mut_indexed()`; if they passed
+/// arguments themselves, we leave the call alone and let typeck decide.
+///
+/// Same caveat as `SCOPED_INTRINSICS`: a local method on an unrelated type
+/// with the same name and a zero-arg form will get the scope appended,
+/// which will cause a typeck error ("expected 0 arguments, got 1"). Pick
+/// a different name (e.g. `pop_indexed`) for any helper you want to keep.
+const SCOPED_METHODS: &[&str] = &["get_mut_indexed"];
+
+fn is_scoped_method(method: &Ident) -> bool {
+    SCOPED_METHODS.iter().any(|name| method == name)
+}
+
+struct ThreadIndexCallRewriter {
+    scope_ident: Ident,
+    borrow_scope: bool,
+    rewrote_index_call: bool,
+}
+
+fn ident_located_at(ident: &Ident, location: proc_macro2::Span) -> Ident {
+    let mut relocated = ident.clone();
+    relocated.set_span(ident.span().located_at(location));
+    relocated
+}
+
+impl VisitMut for ThreadIndexCallRewriter {
+    fn visit_expr_mut(&mut self, expr: &mut Expr) {
+        visit_mut::visit_expr_mut(self, expr);
+
+        match expr {
+            Expr::Call(call) => {
+                let call_span = call.span();
+                let ExprCall { func, args, .. } = call;
+                let Expr::Path(ExprPath { path, .. }) = &mut **func else {
+                    return;
+                };
+                let Some(intrinsic) = SCOPED_INTRINSICS
+                    .iter()
+                    .find(|i| is_thread_index_path(path, i.name))
+                else {
+                    return;
+                };
+
+                let last_args = path
+                    .segments
+                    .last()
+                    .map(|seg| seg.arguments.clone())
+                    .unwrap_or(syn::PathArguments::None);
+                let path_args = if intrinsic.preserve_turbofish {
+                    last_args
+                } else {
+                    syn::PathArguments::None
+                };
+                *path = internal_thread_path(path, intrinsic.name, path_args, call_span);
+                // Keep the binding's name-resolution hygiene, but make this
+                // generated reference part of the user's indexing expression
+                // for diagnostics and line-table purposes.
+                let scope_ident = ident_located_at(&self.scope_ident, call_span);
+                let scope_arg: Expr = if self.borrow_scope {
+                    parse_quote_spanned! { call_span => &#scope_ident }
+                } else {
+                    parse_quote_spanned! { call_span => #scope_ident }
+                };
+
+                if intrinsic.forward_args {
+                    args.insert(0, scope_arg);
+                } else {
+                    args.clear();
+                    args.push(scope_arg);
+                }
+                self.rewrote_index_call = true;
+            }
+            Expr::MethodCall(method_call) => {
+                let call_span = method_call.span();
+                let ExprMethodCall { method, args, .. } = method_call;
+                if !is_scoped_method(method) || !args.is_empty() {
+                    return;
+                }
+                let scope_ident = ident_located_at(&self.scope_ident, call_span);
+                if self.borrow_scope {
+                    args.push(parse_quote_spanned! { call_span => &#scope_ident });
+                } else {
+                    args.push(parse_quote_spanned! { call_span => #scope_ident });
+                }
+                self.rewrote_index_call = true;
+            }
+            _ => {}
+        }
+    }
+}
+
+#[derive(Clone)]
+pub(crate) struct RewrittenKernelScope {
+    pub(crate) ident: Ident,
+    pub(crate) domain: TokenStream2,
+    pub(crate) coordinates: TokenStream2,
+}
+
+pub(super) fn rewrite_thread_index_calls(
+    input: &mut ItemFn,
+    borrow_scope: bool,
+) -> Option<RewrittenKernelScope> {
+    // Keep the ordinary call-site span so borrow-checker diagnostics continue
+    // to point at the user's `#[kernel]` / `#[device]` item. Only rename the
+    // binding when a generic parameter has deliberately taken the usual name.
+    let scope_ident = call_site_ident_avoiding_item(KERNEL_SCOPE_LOCAL, input);
+    if !rewrite_thread_index_calls_with_scope(input, &scope_ident, borrow_scope) {
+        return None;
+    }
+
+    Some(kernel_scope_spec(input, scope_ident))
+}
+
+fn rewrite_thread_index_calls_with_scope(
+    input: &mut ItemFn,
+    scope_ident: &Ident,
+    borrow_scope: bool,
+) -> bool {
+    let mut rewriter = ThreadIndexCallRewriter {
+        scope_ident: scope_ident.clone(),
+        borrow_scope,
+        rewrote_index_call: false,
+    };
+    rewriter.visit_block_mut(&mut input.block);
+    rewriter.rewrote_index_call
+}
+
+fn kernel_scope_spec(input: &ItemFn, ident: Ident) -> RewrittenKernelScope {
+    let (domain, coordinates) = kernel_scope_marker_types(input);
+    RewrittenKernelScope {
+        ident,
+        domain,
+        coordinates,
+    }
+}
+
+pub(crate) fn explicit_kernel_scope(input: &mut ItemFn, ident: Ident) -> RewrittenKernelScope {
+    // Legacy helpers still receive the same capability, but only their
+    // established names are rewritten. The new fast functions are ordinary
+    // Rust calls that take this reference explicitly.
+    rewrite_thread_index_calls_with_scope(input, &ident, false);
+    kernel_scope_spec(input, ident)
+}
+
+pub(super) fn kernel_scope_binding(scope: &RewrittenKernelScope) -> Stmt {
+    let RewrittenKernelScope {
+        ident,
+        domain,
+        coordinates,
+    } = scope;
+    parse_quote! {
+        let #ident = unsafe {
+            ::cuda_device::thread::__internal::make_kernel_scope::<#domain, #coordinates>()
+        };
+    }
+}
+
+pub(crate) fn explicit_kernel_scope_bindings(scope: &RewrittenKernelScope) -> Vec<Stmt> {
+    let RewrittenKernelScope {
+        ident,
+        domain,
+        coordinates,
+    } = scope;
+    // Def-site-like hygiene keeps this generated storage binding distinct
+    // from any source binding with the same text. Both its declaration and
+    // reference are emitted by this one proc-macro expansion.
+    let storage = Ident::new(
+        &format!("{KERNEL_SCOPE_LOCAL}_storage"),
+        proc_macro2::Span::mixed_site(),
+    );
+    vec![
+        parse_quote! {
+            let #storage = unsafe {
+                ::cuda_device::thread::__internal::make_kernel_scope::<#domain, #coordinates>()
+            };
+        },
+        parse_quote! {
+            let #ident: ::cuda_device::thread::LaunchContextRef<'_, #domain, #coordinates> =
+                &#storage;
+        },
+    ]
+}
+
+pub(super) fn append_kernel_scope_parameter(input: &mut ItemFn, scope: &RewrittenKernelScope) {
+    let RewrittenKernelScope {
+        ident,
+        domain,
+        coordinates,
+    } = scope;
+    input.sig.inputs.push(parse_quote! {
+        #ident: ::cuda_device::thread::LaunchContextRef<'_, #domain, #coordinates>
+    });
+}
+
+pub(crate) fn inject_thread_index_scope(input: &mut ItemFn) {
+    if let Some(scope) = rewrite_thread_index_calls(input, true) {
+        input.block.stmts.insert(0, kernel_scope_binding(&scope));
+    }
+}
+
+pub(crate) fn inject_device_thread_index_scope(input: &mut ItemFn) {
+    let Some(mut scope) = rewrite_thread_index_calls(input, true) else {
+        return;
+    };
+    // A device helper has no host preparation boundary of its own. It may use
+    // checked legacy witnesses, but it cannot mint a contract-backed fast
+    // witness; callers must pass that witness or a checked view explicitly.
+    scope.domain = quote! { ::cuda_device::thread::__internal::UnknownDomain };
+    scope.coordinates = quote! { ::cuda_device::thread::__internal::NativeCoordinates };
+    input.block.stmts.insert(0, kernel_scope_binding(&scope));
+}
+
+fn kernel_scope_marker_types(input: &ItemFn) -> (TokenStream2, TokenStream2) {
+    let contract = input
+        .attrs
+        .iter()
+        .find(|attr| attr_path_ends_with(attr, "launch_contract"))
+        .and_then(|attr| attr.parse_args::<LaunchContractArgs>().ok())
+        .map(|args| (args.domain, args.u32_coordinates))
+        .or_else(|| {
+            input
+                .block
+                .stmts
+                .iter()
+                .find_map(launch_contract_marker_values)
+        });
+
+    let (domain, u32_coordinates) = contract.unwrap_or((0, false));
+    let domain = match domain {
+        1 => quote! { ::cuda_device::thread::__internal::Domain1 },
+        2 => quote! { ::cuda_device::thread::__internal::Domain2 },
+        3 => quote! { ::cuda_device::thread::__internal::Domain3 },
+        _ => quote! { ::cuda_device::thread::__internal::UnknownDomain },
+    };
+    let coordinates = if u32_coordinates {
+        quote! { ::cuda_device::thread::__internal::U32Coordinates }
+    } else {
+        quote! { ::cuda_device::thread::__internal::NativeCoordinates }
+    };
+    (domain, coordinates)
+}
+
+fn launch_contract_marker_values(statement: &Stmt) -> Option<(u8, bool)> {
+    let (call, unsafe_wrapped) = configuration_marker_call(statement)?;
+    if !unsafe_wrapped {
+        return None;
+    }
+    if !call.args.is_empty() {
+        return None;
+    }
+    let Expr::Path(ExprPath {
+        qself: None, path, ..
+    }) = &*call.func
+    else {
+        return None;
+    };
+    let segments: Vec<_> = path.segments.iter().collect();
+    if path.leading_colon.is_none()
+        || segments.len() != 3
+        || segments[0].ident != "cuda_device"
+        || segments[1].ident != "thread"
+        || segments[2].ident != "__launch_contract_config"
+    {
+        return None;
+    }
+    let PathArguments::AngleBracketed(arguments) = &segments[2].arguments else {
+        return None;
+    };
+    let mut arguments = arguments.args.iter();
+    let GenericArgument::Const(Expr::Lit(domain)) = arguments.next()? else {
+        return None;
+    };
+    let syn::Lit::Int(domain) = &domain.lit else {
+        return None;
+    };
+    let GenericArgument::Const(Expr::Lit(coordinates)) = arguments.next()? else {
+        return None;
+    };
+    let syn::Lit::Bool(coordinates) = &coordinates.lit else {
+        return None;
+    };
+    if arguments.next().is_some() {
+        return None;
+    }
+    Some((domain.base10_parse().ok()?, coordinates.value))
+}
+
+fn configuration_marker_call(statement: &Stmt) -> Option<(&ExprCall, bool)> {
+    match statement {
+        Stmt::Expr(Expr::Call(call), Some(_semicolon)) => Some((call, false)),
+        Stmt::Expr(Expr::Unsafe(unsafe_block), _) if unsafe_block.block.stmts.len() == 1 => {
+            let Stmt::Expr(Expr::Call(call), Some(_semicolon)) = &unsafe_block.block.stmts[0]
+            else {
+                return None;
+            };
+            Some((call, true))
+        }
+        _ => None,
+    }
+}
+
+/// Return compiler configuration markers already materialized in a generic
+/// kernel body by attributes that expanded before `#[kernel]`.
+///
+/// Only exact, zero-argument calls to cuda-oxide's internal marker paths are
+/// forwarded. The launch-contract marker additionally retains its generated
+/// `unsafe` boundary. Nested calls and unrelated top-level calls remain solely
+/// in the helper body.
+pub(crate) fn top_level_kernel_configuration_markers(input: &ItemFn) -> Vec<Stmt> {
+    input
+        .block
+        .stmts
+        .iter()
+        .filter(|statement| is_kernel_configuration_marker(statement))
+        .cloned()
+        .collect()
+}
+
+pub(crate) fn is_kernel_configuration_marker(statement: &Stmt) -> bool {
+    let Some((call, unsafe_wrapped)) = configuration_marker_call(statement) else {
+        return false;
+    };
+    if !call.args.is_empty() {
+        return false;
+    }
+    let Expr::Path(ExprPath {
+        qself: None, path, ..
+    }) = &*call.func
+    else {
+        return false;
+    };
+    let segments: Vec<_> = path.segments.iter().collect();
+    if path.leading_colon.is_none()
+        || segments.len() != 3
+        || segments[0].ident != "cuda_device"
+        || !matches!(segments[0].arguments, PathArguments::None)
+        || !matches!(segments[1].arguments, PathArguments::None)
+        || !matches!(segments[2].arguments, PathArguments::AngleBracketed(_))
+    {
+        return false;
+    }
+
+    let module = &segments[1].ident;
+    let marker = &segments[2].ident;
+    if unsafe_wrapped {
+        module == "thread" && marker == "__launch_contract_config"
+    } else {
+        (module == "thread"
+            && (marker == "__launch_bounds_config"
+                || marker == "__launch_contract_block_config"
+                || marker == "__unchecked_indexing_config"))
+            || (module == "cluster" && marker == "__cluster_config")
+            || (module == "shared" && marker == "__dynamic_shared_alignment")
+    }
+}
+
+/// True when `statement` is exactly the `__unchecked_indexing_config` marker
+/// call that `#[kernel(unchecked_indexing)]` injects.
+pub(crate) fn is_unchecked_indexing_config_marker(statement: &Stmt) -> bool {
+    if !is_kernel_configuration_marker(statement) {
+        return false;
+    }
+    let Some((call, _)) = configuration_marker_call(statement) else {
+        return false;
+    };
+    let Expr::Path(ExprPath { path, .. }) = &*call.func else {
+        return false;
+    };
+    path.segments
+        .last()
+        .is_some_and(|segment| segment.ident == "__unchecked_indexing_config")
+}
+
+/// Remove the `__unchecked_indexing_config` marker from a function body that
+/// is about to be re-emitted as the user-named implementation helper of a
+/// generic kernel.
+///
+/// The marker may only live in generated kernel ENTRY functions (the
+/// `cuda_oxide_*kernel*`-prefixed symbols); the entry wrapper receives it via
+/// `top_level_kernel_configuration_markers`. The helper is ordinary callable
+/// Rust: if the marker stayed in its body, rustc's MIR inliner could splice
+/// it into a different, non-opted kernel that calls the helper, and the MIR
+/// importer would then elide that caller's bounds checks body-wide without
+/// any opt-in. Stripping is fail-closed: if the helper is ever not
+/// MIR-inlined into its own entry wrapper, the helper body simply keeps its
+/// bounds checks.
+pub(super) fn strip_unchecked_indexing_config_marker(input: &mut ItemFn) {
+    input
+        .block
+        .stmts
+        .retain(|statement| !is_unchecked_indexing_config_marker(statement));
+}
+
+/// Build the hidden unchecked twin of an opted-in generic kernel's
+/// implementation, returning the identifier the generated entry wrapper must
+/// call plus the emitted item.
+///
+/// `input` must already have the marker stripped (it is the exact body that
+/// becomes the user-named helper); the clone re-inserts the marker as its
+/// first statement.
+///
+/// Why a clone at all: the device pipeline translates the
+/// `#[inline(always)]` implementation as its own device function (LLVM
+/// inlines it into the entry later), so a marker on the entry wrapper alone
+/// cannot elide the implementation body's bounds checks, and a marker left
+/// in the user-named helper leaks elision into every other kernel that calls
+/// the helper. The clone carries the marker instead. It is private,
+/// `#[doc(hidden)]`, and named with a def-site (hygienic) identifier, so the
+/// generated `cuda_oxide_*kernel*` entry wrapper of this same expansion is
+/// its only possible caller: bounds-check elision stays confined to launches
+/// of the opted kernel, and the user-named helper keeps every bounds check.
+pub(super) fn unchecked_indexing_impl_clone(
+    input: &ItemFn,
+    helper_attrs: &[syn::Attribute],
+) -> (Ident, TokenStream2) {
+    // `Display` of a raw identifier keeps its `r#` prefix (e.g. `r#gen`),
+    // which `Ident::new` rejects; strip it like `format_ident!` would.
+    let implementation_name = input.sig.ident.to_string();
+    let implementation_name = implementation_name
+        .strip_prefix("r#")
+        .unwrap_or(&implementation_name);
+    let clone_name = internal_ident(&format!(
+        "__cuda_oxide_unchecked_impl_{implementation_name}"
+    ));
+    let mut clone_fn = input.clone();
+    clone_fn.sig.ident = clone_name.clone();
+    clone_fn.vis = syn::Visibility::Inherited;
+    // The twin's body is byte-identical to the user-named helper's, so it
+    // carries the same routed attributes (cfg gates, lint levels such as
+    // `#[allow]`/`#[expect]`, deprecation): a lint the author suppressed on
+    // the helper must not re-fire on the twin. Entry directives and
+    // `#[inline]` were already routed away by `route_generic_kernel_attrs`.
+    clone_fn.attrs = helper_attrs.to_vec();
+    let marker_call: Stmt = parse_quote! {
+        ::cuda_device::thread::__unchecked_indexing_config::<true>();
+    };
+    clone_fn.block.stmts.insert(0, marker_call);
+    let tokens = quote! {
+        /// Hidden unchecked twin of the kernel implementation. Only the
+        /// generated kernel entry calls it; its marker elides bounds checks
+        /// solely for launches of the opted kernel.
+        #[doc(hidden)]
+        #[inline(always)]
+        #[allow(non_snake_case)]
+        #clone_fn
+    };
+    (clone_name, tokens)
+}
diff --git a/crates/cuda-macros/src/launch.rs b/crates/cuda-macros/src/launch.rs
new file mode 100644
index 0000000000..9daf479ca5
--- /dev/null
+++ b/crates/cuda-macros/src/launch.rs
@@ -0,0 +1,730 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! `cuda_launch!` and `cuda_launch_async!` input parsing and expansion.
+
+use crate::common::internal_ident;
+use proc_macro2::TokenStream as TokenStream2;
+use quote::{format_ident, quote};
+use reserved_oxide_symbols::INSTANTIATE_PREFIX;
+use syn::{
+    Ident, Token, bracketed, parenthesized,
+    parse::{Parse, ParseStream},
+    punctuated::Punctuated,
+    spanned::Spanned,
+};
+
+// ============================================================================
+// cuda_launch! Macro (unified compilation)
+// ============================================================================
+
+/// Try to extract closure from an expression.
+///
+/// Closure marshalling no longer needs per-capture extraction: the
+/// backend emits a single byval `.param` for the whole closure struct,
+/// and the host pushes one scalar. The closure literal is still parsed
+/// out of the launch args so the `instantiate_name` helper has a
+/// concrete `&F` to bind the kernel's generic closure type to.
+fn as_closure_expr(expr: &syn::Expr) -> Option<&syn::ExprClosure> {
+    match expr {
+        syn::Expr::Closure(closure) => Some(closure),
+        syn::Expr::Group(group) => as_closure_expr(&group.expr),
+        syn::Expr::Paren(paren) => as_closure_expr(&paren.expr),
+        _ => None,
+    }
+}
+
+/// Argument type for cuda_launch! - same as LaunchArg but renamed for clarity
+pub(crate) enum CudaLaunchArg {
+    /// Direct expression - passed via .arg()
+    Direct(syn::Expr),
+    /// Slice with explicit length - passed as ptr + len
+    SliceWithLen(syn::Expr),
+    /// Mutable slice with explicit length - passed as ptr + len
+    SliceMutWithLen(syn::Expr),
+    /// Closure expression. The closure value is pushed as a single byval
+    /// scalar argument; the backend emits a matching single .param entry
+    /// for aggregate kernel parameters. No per-capture decomposition.
+    Closure { closure_expr: syn::ExprClosure },
+}
+
+impl Parse for CudaLaunchArg {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        // Check for tagged arguments
+        if input.peek(Ident) {
+            let ident: Ident = input.fork().parse()?;
+            match ident.to_string().as_str() {
+                "slice" => {
+                    input.parse::<Ident>()?;
+                    let content;
+                    parenthesized!(content in input);
+                    let expr: syn::Expr = content.parse()?;
+                    return Ok(CudaLaunchArg::SliceWithLen(expr));
+                }
+                "slice_mut" => {
+                    input.parse::<Ident>()?;
+                    let content;
+                    parenthesized!(content in input);
+                    let expr: syn::Expr = content.parse()?;
+                    return Ok(CudaLaunchArg::SliceMutWithLen(expr));
+                }
+                // "move" keyword starts a move closure
+                "move" => {
+                    // Parse the full closure expression (move |args| body)
+                    let expr: syn::Expr = input.parse()?;
+                    if let Some(closure) = as_closure_expr(&expr) {
+                        return Ok(CudaLaunchArg::Closure {
+                            closure_expr: closure.clone(),
+                        });
+                    }
+                    // Not a closure, treat as direct expression
+                    return Ok(CudaLaunchArg::Direct(expr));
+                }
+                _ => {}
+            }
+        }
+
+        // Check for closure starting with `|` (non-move closure)
+        if input.peek(Token![|]) {
+            let expr: syn::Expr = input.parse()?;
+            if let Some(closure) = as_closure_expr(&expr) {
+                return Ok(CudaLaunchArg::Closure {
+                    closure_expr: closure.clone(),
+                });
+            }
+            // Shouldn't happen, but fallback to direct
+            return Ok(CudaLaunchArg::Direct(expr));
+        }
+
+        // Default: direct expression
+        let expr: syn::Expr = input.parse()?;
+
+        // Check if the parsed expression happens to be a closure
+        if let Some(closure) = as_closure_expr(&expr) {
+            return Ok(CudaLaunchArg::Closure {
+                closure_expr: closure.clone(),
+            });
+        }
+
+        Ok(CudaLaunchArg::Direct(expr))
+    }
+}
+
+/// Input for cuda_launch! macro
+pub(crate) struct CudaLaunchInput {
+    /// Kernel path - can be simple name or path with generics: `scale` or `scale::<f32>`
+    pub(crate) kernel: syn::Path,
+    pub(crate) stream: syn::Expr,
+    pub(crate) module: syn::Expr,
+    pub(crate) config: syn::Expr,
+    pub(crate) args: Vec<CudaLaunchArg>,
+    /// Optional cluster dimensions (x, y, z) for thread block cluster launches.
+    /// When present, uses `cuLaunchKernelEx` via `launch_cluster()` instead of `cuLaunchKernel`.
+    pub(crate) cluster_dim: Option<syn::Expr>,
+    /// Optional cooperative-launch flag. When `true`, the kernel is launched
+    /// via `cuLaunchKernelEx` with `CU_LAUNCH_ATTRIBUTE_COOPERATIVE = 1`,
+    /// which is required for `cuda_device::grid::sync()` to work.
+    pub(crate) cooperative: Option<syn::Expr>,
+}
+
+/// Return the generated sibling of a kernel while preserving its module path
+/// and explicit generic arguments.
+///
+/// For example, `kernels::map::<F, 4>` becomes
+/// `kernels::__map_CudaKernel::<F, 4>` when `sibling_name` is the marker name.
+pub(crate) fn kernel_sibling_path(kernel: &syn::Path, sibling_name: Ident) -> syn::Path {
+    let mut sibling = kernel.clone();
+    sibling
+        .segments
+        .last_mut()
+        .expect("kernel path must have segments")
+        .ident = sibling_name;
+    sibling
+}
+
+impl CudaLaunchInput {
+    /// Extract the base kernel name (without generics) and generic arguments
+    fn kernel_parts(&self) -> (Ident, Option<&syn::PathArguments>) {
+        let last_segment = self
+            .kernel
+            .segments
+            .last()
+            .expect("kernel path must have segments");
+        let base_name = last_segment.ident.clone();
+        let generics = match &last_segment.arguments {
+            syn::PathArguments::None => None,
+            args => Some(args),
+        };
+        (base_name, generics)
+    }
+
+    /// Check if this is a generic kernel (has type parameters)
+    fn is_generic(&self) -> bool {
+        self.kernel
+            .segments
+            .last()
+            .map(|seg| !matches!(seg.arguments, syn::PathArguments::None))
+            .unwrap_or(false)
+    }
+}
+
+impl Parse for CudaLaunchInput {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let mut kernel = None;
+        let mut stream = None;
+        let mut module = None;
+        let mut config = None;
+        let mut args = Vec::new();
+        let mut cluster_dim = None;
+        let mut cooperative = None;
+
+        while !input.is_empty() {
+            let key: Ident = input.parse()?;
+            input.parse::<Token![:]>()?;
+
+            match key.to_string().as_str() {
+                "kernel" => kernel = Some(input.parse()?),
+                "stream" => stream = Some(input.parse()?),
+                "module" => module = Some(input.parse()?),
+                "config" => config = Some(input.parse()?),
+                "cluster_dim" => cluster_dim = Some(input.parse()?),
+                "cooperative" => cooperative = Some(input.parse()?),
+                "args" => {
+                    let content;
+                    bracketed!(content in input);
+                    if !content.is_empty() {
+                        let parsed: Punctuated<CudaLaunchArg, Token![,]> =
+                            Punctuated::parse_terminated(&content)?;
+                        args = parsed.into_iter().collect();
+                    }
+                }
+                _ => {
+                    return Err(syn::Error::new(
+                        key.span(),
+                        format!(
+                            "unknown field: {}. Expected: kernel, stream, module, config, cluster_dim, cooperative, args",
+                            key
+                        ),
+                    ));
+                }
+            }
+
+            let _ = input.parse::<Token![,]>();
+        }
+
+        Ok(CudaLaunchInput {
+            kernel: kernel.ok_or_else(|| syn::Error::new(input.span(), "missing 'kernel'"))?,
+            stream: stream.ok_or_else(|| syn::Error::new(input.span(), "missing 'stream'"))?,
+            module: module.ok_or_else(|| syn::Error::new(input.span(), "missing 'module'"))?,
+            config: config.ok_or_else(|| syn::Error::new(input.span(), "missing 'config'"))?,
+            args,
+            cluster_dim,
+            cooperative,
+        })
+    }
+}
+
+pub(crate) fn expand_cuda_launch(input: CudaLaunchInput) -> TokenStream2 {
+    let stream = &input.stream;
+    let module = &input.module;
+    let config = &input.config;
+    let cluster_dim = &input.cluster_dim;
+    let cooperative = &input.cooperative;
+
+    // Get base kernel name and generic arguments
+    let (kernel_base, _generics) = input.kernel_parts();
+
+    // Build the marker type name for CudaKernel lookup
+    let marker = kernel_sibling_path(&input.kernel, format_ident!("__{}_CudaKernel", kernel_base));
+    let ptx_name_helper =
+        kernel_sibling_path(&input.kernel, format_ident!("{}_ptx_name", kernel_base));
+    let args_ident = internal_ident("__cuda_oxide_args");
+    let closure_ident = internal_ident("__cuda_oxide_closure");
+    let ptx_name_ident = internal_ident("__cuda_oxide_ptx_name");
+    let function_ident = internal_ident("__cuda_oxide_function");
+    let config_ident = internal_ident("__cuda_oxide_config");
+    let cooperative_ident = internal_ident("__cuda_oxide_cooperative");
+    let error_ident = internal_ident("__cuda_oxide_error");
+    let static_ptx_name_ident = internal_ident("__CUDA_OXIDE_PTX_NAME");
+
+    // Check if any argument is a closure (for special handling)
+    let has_closure = input
+        .args
+        .iter()
+        .any(|arg| matches!(arg, CudaLaunchArg::Closure { .. }));
+
+    // Extract closure info if present (for monomorphization). Only the
+    // first closure is treated as the type-inference anchor; the macro
+    // currently supports at most one closure parameter per kernel.
+    let closure_info: Option<&syn::ExprClosure> = input.args.iter().find_map(|arg| {
+        if let CudaLaunchArg::Closure { closure_expr } = arg {
+            Some(closure_expr)
+        } else {
+            None
+        }
+    });
+
+    // Generate argument marshaling code.
+    //
+    // Each argument becomes a stack-local variable whose address is pushed
+    // into a `Vec<*mut c_void>`. This directly matches what cuLaunchKernel
+    // expects: an array of pointers-to-argument-values. No trait dispatch
+    // (PushKernelArg) or heap allocation per arg.
+    let arg_code: Vec<TokenStream2> = input
+        .args
+        .iter()
+        .enumerate()
+        .map(|(i, arg)| {
+            let val_name = internal_ident(&format!("__cuda_oxide_arg_{i}"));
+            match arg {
+                CudaLaunchArg::Direct(expr) => {
+                    quote! {
+                        let mut #val_name = #expr;
+                        #args_ident.push(&mut #val_name as *mut _ as *mut std::ffi::c_void);
+                    }
+                }
+                CudaLaunchArg::SliceWithLen(expr) => {
+                    let ptr_name = internal_ident(&format!("__cuda_oxide_arg_{i}_ptr"));
+                    let len_name = internal_ident(&format!("__cuda_oxide_arg_{i}_len"));
+                    quote! {
+                        let #val_name = &#expr;
+                        let mut #ptr_name = #val_name.cu_deviceptr();
+                        let mut #len_name = #val_name.len() as u64;
+                        #args_ident.push(&mut #ptr_name as *mut _ as *mut std::ffi::c_void);
+                        #args_ident.push(&mut #len_name as *mut _ as *mut std::ffi::c_void);
+                    }
+                }
+                CudaLaunchArg::SliceMutWithLen(expr) => {
+                    let ptr_name = internal_ident(&format!("__cuda_oxide_arg_{i}_ptr"));
+                    let len_name = internal_ident(&format!("__cuda_oxide_arg_{i}_len"));
+                    quote! {
+                        let #val_name = &mut #expr;
+                        let mut #ptr_name = #val_name.cu_deviceptr();
+                        let mut #len_name = #val_name.len() as u64;
+                        #args_ident.push(&mut #ptr_name as *mut _ as *mut std::ffi::c_void);
+                        #args_ident.push(&mut #len_name as *mut _ as *mut std::ffi::c_void);
+                    }
+                }
+                CudaLaunchArg::Closure { .. } => {
+                    // Push the whole closure as a single byval scalar. The
+                    // backend emits a single byval kernel parameter for
+                    // aggregate (struct / closure) entry-point args, so
+                    // pushing `__closure` once matches what the device-side
+                    // `.param` declaration expects.
+                    //
+                    // Routed through `push_kernel_scalar` so ZST closures
+                    // (zero captures) are dropped from the host packet —
+                    // matching the backend, which drops their `.param`
+                    // declaration too. Move closures push by value;
+                    // non-move closures push the closure struct (which
+                    // contains host references the GPU dereferences via
+                    // HMM).
+                    let _ = i;
+                    quote! {
+                        ::cuda_host::push_kernel_scalar(&mut #args_ident, &mut #closure_ident);
+                    }
+                }
+            }
+        })
+        .collect();
+
+    // Build the instantiate helper name (for closures)
+    let instantiate = kernel_sibling_path(
+        &input.kernel,
+        format_ident!("{}{}", INSTANTIATE_PREFIX, kernel_base),
+    );
+
+    // Generate the launch call — regular, cluster, cooperative, or both.
+    //
+    // All paths use the stream-aware cuda_core helpers. Those helpers bind the
+    // stream's owning CUDA context to the calling thread and then delegate to
+    // the raw cuLaunchKernel/cuLaunchKernelEx wrappers.
+    let launch_call = match (&cluster_dim, &cooperative) {
+        (Some(cdim), Some(coop)) => quote! {
+            {
+                let #config_ident = #config;
+                let #cooperative_ident: bool = #coop;
+                if #cooperative_ident {
+                    cuda_core::launch_kernel_ex_cooperative_on_stream(
+                        &#function_ident,
+                        #config_ident.grid_dim,
+                        #config_ident.block_dim,
+                        #config_ident.shared_mem_bytes,
+                        #cdim,
+                        (#stream).as_ref(),
+                        &mut #args_ident,
+                    )
+                } else {
+                    cuda_core::launch_kernel_ex_on_stream(
+                        &#function_ident,
+                        #config_ident.grid_dim,
+                        #config_ident.block_dim,
+                        #config_ident.shared_mem_bytes,
+                        #cdim,
+                        (#stream).as_ref(),
+                        &mut #args_ident,
+                    )
+                }
+            }
+        },
+        (Some(cdim), None) => quote! {
+            {
+                let #config_ident = #config;
+                cuda_core::launch_kernel_ex_on_stream(
+                    &#function_ident,
+                    #config_ident.grid_dim,
+                    #config_ident.block_dim,
+                    #config_ident.shared_mem_bytes,
+                    #cdim,
+                    (#stream).as_ref(),
+                    &mut #args_ident,
+                )
+            }
+        },
+        (None, Some(coop)) => quote! {
+            {
+                let #config_ident = #config;
+                let #cooperative_ident: bool = #coop;
+                if #cooperative_ident {
+                    cuda_core::launch_kernel_cooperative_on_stream(
+                        &#function_ident,
+                        #config_ident.grid_dim,
+                        #config_ident.block_dim,
+                        #config_ident.shared_mem_bytes,
+                        (#stream).as_ref(),
+                        &mut #args_ident,
+                    )
+                } else {
+                    cuda_core::launch_kernel_on_stream(
+                        &#function_ident,
+                        #config_ident.grid_dim,
+                        #config_ident.block_dim,
+                        #config_ident.shared_mem_bytes,
+                        (#stream).as_ref(),
+                        &mut #args_ident,
+                    )
+                }
+            }
+        },
+        (None, None) => quote! {
+            {
+                let #config_ident = #config;
+                cuda_core::launch_kernel_on_stream(
+                    &#function_ident,
+                    #config_ident.grid_dim,
+                    #config_ident.block_dim,
+                    #config_ident.shared_mem_bytes,
+                    (#stream).as_ref(),
+                    &mut #args_ident,
+                )
+            }
+        },
+    };
+
+    if has_closure {
+        let closure_expr = closure_info.expect("has_closure but no closure_info");
+
+        // The on-wire PTX name comes from the kernel's
+        // GenericCudaKernel::ptx_name() impl (via the instantiate helper).
+        // The helper takes `&F` so we can keep ownership of `__closure`
+        // and push it as the byval kernel argument right after — the
+        // backend's kernel-boundary ABI emits a single .param for the
+        // whole closure struct, matching this single push.
+        let _ = closure_expr.span();
+
+        quote! {
+            {
+                let mut #closure_ident = #closure_expr;
+                let #ptx_name_ident: &'static str = #instantiate(&#closure_ident);
+                let #function_ident = #module.load_function(#ptx_name_ident).unwrap_or_else(|#error_ident| {
+                    panic!(
+                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
+                        stringify!(#kernel_base),
+                        #ptx_name_ident,
+                        #error_ident,
+                    )
+                });
+
+                let mut #args_ident: Vec<*mut std::ffi::c_void> = Vec::new();
+                #(#arg_code)*
+
+                #launch_call
+            }
+        }
+    } else if input.is_generic() {
+        quote! {
+            {
+                let #ptx_name_ident = #ptx_name_helper();
+                let #function_ident = #module.load_function(#ptx_name_ident).unwrap_or_else(|#error_ident| {
+                    panic!(
+                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
+                        stringify!(#kernel_base),
+                        #ptx_name_ident,
+                        #error_ident,
+                    )
+                });
+
+                let mut #args_ident: Vec<*mut std::ffi::c_void> = Vec::new();
+                #(#arg_code)*
+
+                #launch_call
+            }
+        }
+    } else {
+        quote! {
+            {
+                const #static_ptx_name_ident: &str = <#marker as cuda_host::CudaKernel>::PTX_NAME;
+                let #function_ident = #module.load_function(#static_ptx_name_ident).unwrap_or_else(|#error_ident| {
+                    panic!(
+                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
+                        stringify!(#kernel_base),
+                        #static_ptx_name_ident,
+                        #error_ident,
+                    )
+                });
+
+                let mut #args_ident: Vec<*mut std::ffi::c_void> = Vec::new();
+                #(#arg_code)*
+
+                #launch_call
+            }
+        }
+    }
+}
+
+// ============================================================================
+// cuda_launch_async! Macro (async path via cuda-async)
+// ============================================================================
+
+/// Parsed input for the [`cuda_launch_async!`](crate::cuda_launch_async) macro.
+///
+/// Unlike [`CudaLaunchInput`], this struct has no `stream` field. The stream
+/// is assigned later by the `SchedulingPolicy` when the returned
+/// `AsyncKernelLaunch` is `.sync()`'d or `.await`'d.
+pub(crate) struct CudaLaunchAsyncInput {
+    /// Path to the `#[kernel]` function, possibly with generic arguments.
+    kernel: syn::Path,
+    /// Expression resolving to an `Arc<CudaModule>` that contains the compiled PTX.
+    module: syn::Expr,
+    /// Expression resolving to a [`LaunchConfig`](https://docs.rs/cuda-core/latest/cuda_core/struct.LaunchConfig.html) (grid/block dims, shared mem).
+    config: syn::Expr,
+    /// Kernel arguments: `slice(x)`, `slice_mut(x)`, direct values, or closures.
+    args: Vec<CudaLaunchArg>,
+}
+
+impl CudaLaunchAsyncInput {
+    /// Splits the kernel path into its base identifier and optional generic arguments.
+    /// For `vecadd::<f32>` returns `("vecadd", Some(<f32>))`.
+    fn kernel_parts(&self) -> (Ident, Option<&syn::PathArguments>) {
+        let last_segment = self
+            .kernel
+            .segments
+            .last()
+            .expect("kernel path must have segments");
+        let base_name = last_segment.ident.clone();
+        let generics = match &last_segment.arguments {
+            syn::PathArguments::None => None,
+            args => Some(args),
+        };
+        (base_name, generics)
+    }
+
+    /// Returns `true` if the kernel path has explicit generic type arguments.
+    fn is_generic(&self) -> bool {
+        self.kernel
+            .segments
+            .last()
+            .map(|seg| !matches!(seg.arguments, syn::PathArguments::None))
+            .unwrap_or(false)
+    }
+}
+
+/// Parses the `cuda_launch_async! { kernel: ..., module: ..., config: ..., args: [...] }` syntax.
+///
+/// Fields can appear in any order. The `args` field uses bracket syntax with the same
+/// argument forms as `cuda_launch!`: `slice(x)`, `slice_mut(x)`, direct values, or closures.
+impl Parse for CudaLaunchAsyncInput {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let mut kernel = None;
+        let mut module = None;
+        let mut config = None;
+        let mut args = Vec::new();
+
+        while !input.is_empty() {
+            let key: Ident = input.parse()?;
+            input.parse::<Token![:]>()?;
+
+            match key.to_string().as_str() {
+                "kernel" => kernel = Some(input.parse()?),
+                "module" => module = Some(input.parse()?),
+                "config" => config = Some(input.parse()?),
+                "args" => {
+                    let content;
+                    bracketed!(content in input);
+                    if !content.is_empty() {
+                        let parsed: Punctuated<CudaLaunchArg, Token![,]> =
+                            Punctuated::parse_terminated(&content)?;
+                        args = parsed.into_iter().collect();
+                    }
+                }
+                _ => {
+                    return Err(syn::Error::new(
+                        key.span(),
+                        format!(
+                            "unknown field: {}. Expected: kernel, module, config, args",
+                            key
+                        ),
+                    ));
+                }
+            }
+
+            let _ = input.parse::<Token![,]>();
+        }
+
+        Ok(CudaLaunchAsyncInput {
+            kernel: kernel.ok_or_else(|| syn::Error::new(input.span(), "missing 'kernel'"))?,
+            module: module.ok_or_else(|| syn::Error::new(input.span(), "missing 'module'"))?,
+            config: config.ok_or_else(|| syn::Error::new(input.span(), "missing 'config'"))?,
+            args,
+        })
+    }
+}
+
+pub(crate) fn expand_cuda_launch_async(input: CudaLaunchAsyncInput) -> TokenStream2 {
+    let module = &input.module;
+    let config = &input.config;
+    let (kernel_base, _generics) = input.kernel_parts();
+    let marker = kernel_sibling_path(&input.kernel, format_ident!("__{}_CudaKernel", kernel_base));
+    let ptx_name_helper =
+        kernel_sibling_path(&input.kernel, format_ident!("{}_ptx_name", kernel_base));
+    let instantiate = kernel_sibling_path(
+        &input.kernel,
+        format_ident!("{}{}", INSTANTIATE_PREFIX, kernel_base),
+    );
+    let has_closure = input
+        .args
+        .iter()
+        .any(|arg| matches!(arg, CudaLaunchArg::Closure { .. }));
+    let closure_expr = input.args.iter().find_map(|arg| {
+        if let CudaLaunchArg::Closure { closure_expr } = arg {
+            Some(closure_expr)
+        } else {
+            None
+        }
+    });
+    let closure_ident = internal_ident("__cuda_oxide_closure");
+    let ptx_name_ident = internal_ident("__cuda_oxide_ptx_name");
+    let function_ident = internal_ident("__cuda_oxide_function");
+    let launch_ident = internal_ident("__cuda_oxide_launch");
+    let error_ident = internal_ident("__cuda_oxide_error");
+    let static_ptx_name_ident = internal_ident("__CUDA_OXIDE_PTX_NAME");
+
+    let arg_code: Vec<TokenStream2> = input
+        .args
+        .iter()
+        .enumerate()
+        .map(|(i, arg)| {
+            let tmp_name = internal_ident(&format!("__cuda_oxide_arg_{i}"));
+            match arg {
+                CudaLaunchArg::Direct(expr) => {
+                    quote! {
+                        #launch_ident.push_scalar_arg(#expr);
+                    }
+                }
+                CudaLaunchArg::SliceWithLen(expr) => {
+                    let len_name = internal_ident(&format!("__cuda_oxide_arg_{i}_len"));
+                    quote! {
+                        let #tmp_name = &#expr;
+                        #launch_ident.push_arg(Box::new(#tmp_name.cu_deviceptr()));
+                        let #len_name = #tmp_name.len() as u64;
+                        #launch_ident.push_arg(Box::new(#len_name));
+                    }
+                }
+                CudaLaunchArg::SliceMutWithLen(expr) => {
+                    let len_name = internal_ident(&format!("__cuda_oxide_arg_{i}_len"));
+                    quote! {
+                        let #tmp_name = &mut #expr;
+                        #launch_ident.push_arg(Box::new(#tmp_name.cu_deviceptr()));
+                        let #len_name = #tmp_name.len() as u64;
+                        #launch_ident.push_arg(Box::new(#len_name));
+                    }
+                }
+                CudaLaunchArg::Closure { .. } => {
+                    // Push the whole closure as one byval scalar so the
+                    // host packet matches the single aggregate `.param`
+                    // at the kernel boundary. ZST closures are omitted
+                    // to keep later packet slots aligned.
+                    quote! {
+                        if ::core::mem::size_of_val(&#closure_ident) != 0 {
+                            #launch_ident.push_scalar_arg(#closure_ident);
+                        }
+                    }
+                }
+            }
+        })
+        .collect();
+
+    if has_closure {
+        let closure_expr = closure_expr.expect("has_closure but no closure expression");
+        quote! {
+            {
+                let #closure_ident = #closure_expr;
+                let #ptx_name_ident: &'static str = #instantiate(&#closure_ident);
+                let #function_ident = #module.load_function(#ptx_name_ident).unwrap_or_else(|#error_ident| {
+                    panic!(
+                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
+                        stringify!(#kernel_base),
+                        #ptx_name_ident,
+                        #error_ident,
+                    )
+                });
+                let mut #launch_ident = cuda_async::launch::AsyncKernelLaunchBuilder::new(
+                    std::sync::Arc::new(#function_ident),
+                );
+                #(#arg_code)*
+                #launch_ident.finalize_unchecked(#config)
+            }
+        }
+    } else if input.is_generic() {
+        quote! {
+            {
+                let #ptx_name_ident = #ptx_name_helper();
+                let #function_ident = #module.load_function(#ptx_name_ident).unwrap_or_else(|#error_ident| {
+                    panic!(
+                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
+                        stringify!(#kernel_base),
+                        #ptx_name_ident,
+                        #error_ident,
+                    )
+                });
+                let mut #launch_ident = cuda_async::launch::AsyncKernelLaunchBuilder::new(
+                    std::sync::Arc::new(#function_ident),
+                );
+                #(#arg_code)*
+                #launch_ident.finalize_unchecked(#config)
+            }
+        }
+    } else {
+        quote! {
+            {
+                const #static_ptx_name_ident: &str =
+                    <#marker as cuda_host::CudaKernel>::PTX_NAME;
+                let #function_ident = #module.load_function(#static_ptx_name_ident).unwrap_or_else(|#error_ident| {
+                    panic!(
+                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
+                        stringify!(#kernel_base),
+                        #static_ptx_name_ident,
+                        #error_ident,
+                    )
+                });
+                let mut #launch_ident = cuda_async::launch::AsyncKernelLaunchBuilder::new(
+                    std::sync::Arc::new(#function_ident),
+                );
+                #(#arg_code)*
+                #launch_ident.finalize_unchecked(#config)
+            }
+        }
+    }
+}
diff --git a/crates/cuda-macros/src/launch_attrs.rs b/crates/cuda-macros/src/launch_attrs.rs
new file mode 100644
index 0000000000..5877a9409d
--- /dev/null
+++ b/crates/cuda-macros/src/launch_attrs.rs
@@ -0,0 +1,612 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Launch-configuration attributes: `#[launch_bounds]`,
+//! `#[launch_contract]`, `#[cluster_launch]`, `#[cooperative_launch]`,
+//! and `#[unroll]` loop-attribute rewriting.
+
+use crate::common::attr_path_ends_with;
+use crate::cuda_module::contract::{
+    LaunchContractArgs, dynamic_shared_max, validate_requires_relations,
+};
+use crate::cuda_module::model::{
+    CudaModuleParam, CudaModuleParamMarshal, cuda_module_param_from_typed, scalar_int_class,
+};
+use proc_macro::TokenStream;
+use quote::quote;
+use syn::{
+    Expr, FnArg, GenericParam, Ident, ItemFn, Pat, Path, Stmt, Token,
+    parse::{Parse, ParseStream},
+    parse_macro_input, parse_quote,
+    punctuated::Punctuated,
+    visit::{self, Visit},
+    visit_mut::{self, VisitMut},
+};
+
+pub(crate) fn launch_bounds_entry(attr: TokenStream, item: TokenStream) -> TokenStream {
+    let args: LaunchBoundsArgs = parse_macro_input!(attr as LaunchBoundsArgs);
+    let mut input = parse_macro_input!(item as ItemFn);
+
+    let max_threads = &args.max_threads.expr;
+    let min_blocks = &args.min_blocks.expr;
+
+    add_const_evaluatable_bound(&mut input.sig.generics, &args.max_threads);
+    add_const_evaluatable_bound(&mut input.sig.generics, &args.min_blocks);
+
+    // Inject the launch bounds config marker at the start of the function body
+    let marker_call: syn::Stmt = syn::parse_quote! {
+        ::cuda_device::thread::__launch_bounds_config::<{ #max_threads }, { #min_blocks }>();
+    };
+
+    // Prepend the marker to the function body
+    input.block.stmts.insert(0, marker_call);
+
+    quote! {
+        #input
+    }
+    .into()
+}
+
+pub(crate) fn launch_contract_entry(attr: TokenStream, item: TokenStream) -> TokenStream {
+    let args = parse_macro_input!(attr as LaunchContractArgs);
+    let mut input = parse_macro_input!(item as ItemFn);
+
+    // Validate `requires` here too, so a standalone contract (outside any
+    // #[cuda_module]) rejects typos and bad grammar at the attribute site
+    // instead of silently dropping the relations. Inside a #[cuda_module]
+    // the module macro validates first against the source signature; a
+    // module-level rejection replaces the whole module with the error, so
+    // this attribute never expands there and the two validations cannot
+    // stack duplicate diagnostics.
+    if !args.requires.is_empty()
+        && let Some(params) = standalone_requires_params(&input)
+        && let Err(error) = validate_requires_relations(&args.requires, &params)
+    {
+        return error.to_compile_error().into();
+    }
+
+    inject_launch_contract_markers(&args, &mut input);
+
+    quote! { #input }.into()
+}
+
+/// Best-effort parameter model for validating `requires` relations on the
+/// function the `launch_contract` attribute macro receives.
+///
+/// Returns `None` when the function is a macro-generated generic entry
+/// wrapper: its parameters carry synthetic `__cuda_oxide_arg_*` names, so
+/// source-level relation identifiers cannot be resolved against it. Those
+/// relations were already validated against the source signature, either by
+/// the `#[cuda_module]` expansion or by `#[kernel]`'s generic routing (see
+/// [`validate_routed_launch_contract_requires`]). Parameter shapes the
+/// module marshaller rejects, reachable only outside `#[cuda_module]`, are
+/// modelled as opaque scalars: referencing one in `requires` then fails with
+/// the precise grammar error rather than a misleading "unknown identifier".
+pub(crate) fn standalone_requires_params(item_fn: &ItemFn) -> Option<Vec<CudaModuleParam>> {
+    requires_params_from_inputs(&item_fn.sig.inputs)
+}
+
+/// Shared core of [`standalone_requires_params`], usable with a saved copy
+/// of a kernel's original inputs before scope parameters are appended or
+/// wrapper signatures are synthesized.
+fn requires_params_from_inputs(
+    inputs: &syn::punctuated::Punctuated<FnArg, syn::token::Comma>,
+) -> Option<Vec<CudaModuleParam>> {
+    let mut params = Vec::new();
+    for arg in inputs {
+        let FnArg::Typed(pat_type) = arg else {
+            continue;
+        };
+        let Pat::Ident(pat_ident) = &*pat_type.pat else {
+            continue;
+        };
+        if pat_ident.ident.to_string().starts_with("__cuda_oxide_arg_") {
+            return None;
+        }
+        let ty = &pat_type.ty;
+        let param = cuda_module_param_from_typed(pat_type).unwrap_or_else(|_| CudaModuleParam {
+            name: pat_ident.ident.clone(),
+            sync_host_ty: quote! { #ty },
+            async_host_ty: quote! { #ty },
+            marshal: CudaModuleParamMarshal::Scalar,
+            mutable_slice: false,
+            disjoint_slice_ty: None,
+            disjoint_slice_elem: None,
+            uniform_ty: None,
+            uniform_scalar: None,
+            scalar_int: scalar_int_class(ty),
+        });
+        params.push(param);
+    }
+    Some(params)
+}
+
+/// Validate the `requires` relations of any `#[launch_contract]` attribute
+/// that `#[kernel]` is about to route onto a generated generic entry
+/// wrapper.
+///
+/// The wrapper's parameters carry synthetic `__cuda_oxide_arg_*` names, so
+/// when the attribute macro finally expands there it cannot resolve
+/// source-level identifiers and deliberately stands down (see
+/// [`standalone_requires_params`]). Without this check, a typo'd relation on
+/// a standalone generic kernel would compile clean while the identical
+/// non-generic kernel errors. Malformed argument lists are skipped here: the
+/// attribute macro reports those itself when it expands.
+pub(crate) fn validate_routed_launch_contract_requires(
+    attrs: &[syn::Attribute],
+    source_inputs: &syn::punctuated::Punctuated<FnArg, syn::token::Comma>,
+) -> syn::Result<()> {
+    for attr in attrs {
+        if !attr_path_ends_with(attr, "launch_contract") {
+            continue;
+        }
+        let Ok(args) = attr.parse_args::<LaunchContractArgs>() else {
+            continue;
+        };
+        if args.requires.is_empty() {
+            continue;
+        }
+        if let Some(params) = requires_params_from_inputs(source_inputs) {
+            validate_requires_relations(&args.requires, &params)?;
+        }
+    }
+    Ok(())
+}
+
+pub(crate) fn inject_launch_contract_markers(args: &LaunchContractArgs, input: &mut ItemFn) {
+    let domain = args.domain;
+    let u32_coordinates = args.u32_coordinates;
+    let contract_marker: syn::Stmt = parse_quote! {
+        unsafe {
+            ::cuda_device::thread::__launch_contract_config::<#domain, #u32_coordinates>();
+        }
+    };
+    input.block.stmts.insert(0, contract_marker);
+    let mut next = 1;
+
+    // Give the exact block shape to the device compiler as well, so ptxas
+    // emits `.reqntid` and the driver rejects a mismatched block on every
+    // axis. Without this the shape is known only to the host check.
+    if let Some((x, y, z)) = args.exact_block {
+        let block_marker: syn::Stmt = parse_quote! {
+            ::cuda_device::thread::__launch_contract_block_config::<#x, #y, #z>();
+        };
+        input.block.stmts.insert(next, block_marker);
+        next += 1;
+    }
+
+    if dynamic_shared_max(args.dynamic_shared) != 0 {
+        let alignment = args.dynamic_shared_alignment as usize;
+        let alignment_marker: syn::Stmt = parse_quote! {
+            ::cuda_device::shared::__dynamic_shared_alignment::<#alignment>();
+        };
+        input.block.stmts.insert(next, alignment_marker);
+    }
+}
+
+/// Arguments for `#[launch_bounds(...)]` attribute.
+#[derive(Clone)]
+pub(crate) struct LaunchBoundsArgs {
+    pub(crate) max_threads: ConstU32Expr,
+    pub(crate) min_blocks: ConstU32Expr,
+}
+
+impl Parse for LaunchBoundsArgs {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let args: Punctuated<Expr, Token![,]> = Punctuated::parse_terminated(input)?;
+        let values = args
+            .into_iter()
+            .map(ConstU32Expr::new)
+            .collect::<syn::Result<Vec<_>>>()?;
+
+        match values.len() {
+            1 => {
+                let max_threads = values.into_iter().next().unwrap();
+                validate_literal_max_threads(&max_threads)?;
+                Ok(LaunchBoundsArgs {
+                    max_threads,
+                    min_blocks: ConstU32Expr::literal(0),
+                })
+            }
+            2 => {
+                let mut values = values.into_iter();
+                let max_threads = values.next().unwrap();
+                let min_blocks = values.next().unwrap();
+                validate_literal_max_threads(&max_threads)?;
+                Ok(LaunchBoundsArgs {
+                    max_threads,
+                    min_blocks,
+                })
+            }
+            _ => Err(syn::Error::new(
+                input.span(),
+                "launch_bounds expects 1 or 2 parameters: #[launch_bounds(max_threads)] or #[launch_bounds(max_threads, min_blocks)]",
+            )),
+        }
+    }
+}
+
+/// A source expression whose expected type is `u32` at the generated marker.
+///
+/// Literal values are retained for early source-time diagnostics. Every other
+/// expression stays as typed Rust syntax: rustc, not this procedural macro,
+/// resolves associated constants and arithmetic for both device metadata and
+/// each monomorphized host launch contract.
+#[derive(Clone)]
+pub(crate) struct ConstU32Expr {
+    pub(crate) expr: Expr,
+    pub(crate) literal_value: Option<u32>,
+}
+
+impl ConstU32Expr {
+    pub(crate) fn new(expr: Expr) -> syn::Result<Self> {
+        let literal_value = match &expr {
+            Expr::Lit(expr_lit) => match &expr_lit.lit {
+                syn::Lit::Int(value) => Some(value.base10_parse::<u32>()?),
+                _ => None,
+            },
+            _ => None,
+        };
+        Ok(Self {
+            expr,
+            literal_value,
+        })
+    }
+
+    pub(crate) fn literal(value: u32) -> Self {
+        Self {
+            expr: parse_quote! { #value },
+            literal_value: Some(value),
+        }
+    }
+}
+
+fn validate_literal_max_threads(value: &ConstU32Expr) -> syn::Result<()> {
+    if value.literal_value == Some(0) {
+        Err(syn::Error::new_spanned(
+            &value.expr,
+            "launch_bounds maximum threads must be greater than zero",
+        ))
+    } else {
+        Ok(())
+    }
+}
+
+/// Returns whether an expression names one of the function's type or const
+/// parameters and therefore needs a signature-level evaluatability witness.
+///
+/// Non-generic paths deliberately return false. In particular, a const item
+/// declared inside the function body is in scope at the generated marker but
+/// is not in scope in the function signature.
+fn const_expr_depends_on_generics(expr: &Expr, generics: &syn::Generics) -> bool {
+    let generic_names: Vec<&Ident> = generics
+        .params
+        .iter()
+        .filter_map(|parameter| match parameter {
+            GenericParam::Type(parameter) => Some(&parameter.ident),
+            GenericParam::Const(parameter) => Some(&parameter.ident),
+            GenericParam::Lifetime(_) => None,
+        })
+        .collect();
+    if generic_names.is_empty() {
+        return false;
+    }
+
+    struct GenericReference<'a> {
+        generic_names: &'a [&'a Ident],
+        found: bool,
+    }
+
+    impl<'ast> Visit<'ast> for GenericReference<'_> {
+        fn visit_path(&mut self, path: &'ast Path) {
+            if path.segments.iter().any(|segment| {
+                self.generic_names
+                    .iter()
+                    .any(|generic| segment.ident == **generic)
+            }) {
+                self.found = true;
+                return;
+            }
+            visit::visit_path(self, path);
+        }
+    }
+
+    let mut visitor = GenericReference {
+        generic_names: &generic_names,
+        found: false,
+    };
+    visitor.visit_expr(expr);
+    visitor.found
+}
+
+/// Make a generic constant expression evaluatable at each monomorphization.
+///
+/// rustc requires this bound for expressions such as `P::MAX_THREADS`. The
+/// marker itself supplies the expected `u32` type; the array length is only an
+/// evaluatability witness and never reaches device code.
+pub(crate) fn add_const_evaluatable_bound(generics: &mut syn::Generics, value: &ConstU32Expr) {
+    if value.literal_value.is_some() || !const_expr_depends_on_generics(&value.expr, generics) {
+        return;
+    }
+    let expr = &value.expr;
+    let predicate: syn::WherePredicate = parse_quote! {
+        [(); (#expr) as usize]:
+    };
+    generics.make_where_clause().predicates.push(predicate);
+}
+
+pub(crate) fn add_launch_bounds_evaluatability_from_attrs(input: &mut ItemFn) -> syn::Result<()> {
+    let matching: Vec<_> = input
+        .attrs
+        .iter()
+        .filter(|attr| attr_path_ends_with(attr, "launch_bounds"))
+        .collect();
+    if matching.len() > 1 {
+        return Err(syn::Error::new_spanned(
+            matching[1],
+            "a kernel may have only one launch_bounds attribute",
+        ));
+    }
+    let Some(attr) = matching.first() else {
+        return Ok(());
+    };
+    let bounds = attr.parse_args::<LaunchBoundsArgs>()?;
+    let max_threads = bounds.max_threads.clone();
+    let min_blocks = bounds.min_blocks.clone();
+    add_const_evaluatable_bound(&mut input.sig.generics, &max_threads);
+    add_const_evaluatable_bound(&mut input.sig.generics, &min_blocks);
+    Ok(())
+}
+
+/// Arguments for the `#[unroll]` / `#[unroll(N)]` attribute.
+///
+/// Bare `#[unroll]` parses to factor `0` (full unroll); `#[unroll(N)]` requires
+/// `N >= 2`.
+pub(crate) struct UnrollArgs {
+    pub(crate) factor: ConstU32Expr,
+}
+
+impl Parse for UnrollArgs {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        // Bare `#[unroll]` => full unroll (factor 0).
+        if input.is_empty() {
+            return Ok(UnrollArgs {
+                factor: ConstU32Expr::literal(0),
+            });
+        }
+
+        let args: Punctuated<Expr, Token![,]> = Punctuated::parse_terminated(input)?;
+        let mut values = args
+            .into_iter()
+            .map(ConstU32Expr::new)
+            .collect::<syn::Result<Vec<_>>>()?;
+
+        match values.len() {
+            1 => {
+                let factor = values.pop().unwrap();
+                match factor.literal_value {
+                    Some(0 | 1) => Err(syn::Error::new_spanned(
+                        &factor.expr,
+                        "partial unroll factor must be at least 2; use #[unroll] for full unrolling",
+                    )),
+                    Some(value) if value > 1024 => Err(syn::Error::new_spanned(
+                        &factor.expr,
+                        "partial unroll factor cannot exceed 1024",
+                    )),
+                    _ => Ok(UnrollArgs { factor }),
+                }
+            }
+            _ => Err(syn::Error::new(
+                input.span(),
+                "unroll expects no argument (full unroll) or one factor: #[unroll] or #[unroll(N)]",
+            )),
+        }
+    }
+}
+
+/// `VisitMut` pass that consumes `#[unroll]` / `#[unroll(N)]` attributes written
+/// directly on loops inside a `#[kernel]` (or `#[device]`) function body.
+///
+/// This mirrors how CubeCL's `#[cube]` macro handles per-loop `#[unroll]`: the
+/// enclosing function macro owns the whole body AST, so it can strip the inner
+/// attribute and lower it into a marker BEFORE rustc ever sees it. That keeps us
+/// off the nightly `stmt_expr_attributes` feature (rustc otherwise rejects
+/// attributes on expressions).
+///
+/// For every `for` / `while` / `loop` expression carrying an outer `#[unroll]`
+/// attribute, the visitor:
+///
+/// 1. removes the `unroll` attribute from the loop expr's `attrs`, and
+/// 2. inserts `cuda_device::thread::__unroll_config::<FACTOR>();` as the FIRST
+///    statement of that loop's body block.
+///
+/// `FACTOR` follows [`UnrollArgs`]: bare `#[unroll]` => `0` (full unroll),
+/// `#[unroll(N)]` => `N`. The importer reads the marker from the block it lands
+/// in, so the request applies to that loop only.
+///
+/// The visitor recurses through nested blocks/loops/ifs via the default
+/// `visit_mut` traversal, so an annotated loop anywhere in the function is
+/// handled. Loops without an `#[unroll]` attribute are left untouched, so a
+/// kernel with no per-loop annotations expands byte-identically to before.
+#[derive(Default)]
+pub(crate) struct LoopUnrollAttrVisitor {
+    /// First parse error encountered (e.g. a malformed `#[unroll(...)]`). The
+    /// caller surfaces this as a compile error.
+    pub(crate) error: Option<syn::Error>,
+    pub(crate) const_expressions: Vec<ConstU32Expr>,
+}
+
+impl LoopUnrollAttrVisitor {
+    /// If `attrs` contains an outer `#[unroll]` / `#[unroll(N)]`, remove it and
+    /// return the parsed factor. Returns `None` when no `unroll` attribute is
+    /// present (leaving `attrs` untouched). Records a parse error and returns
+    /// `None` if the attribute is malformed.
+    fn take_unroll_factor(&mut self, attrs: &mut Vec<syn::Attribute>) -> Option<ConstU32Expr> {
+        let idx = attrs
+            .iter()
+            .position(|attr| attr.path().is_ident("unroll"))?;
+        let attr = attrs.remove(idx);
+
+        // `#[unroll]` (bare) is `Meta::Path`; `#[unroll(N)]` is `Meta::List`.
+        let factor = match &attr.meta {
+            syn::Meta::Path(_) => ConstU32Expr::literal(0),
+            syn::Meta::List(list) => match list.parse_args::<UnrollArgs>() {
+                Ok(parsed) => parsed.factor,
+                Err(err) => {
+                    if self.error.is_none() {
+                        self.error = Some(err);
+                    }
+                    return None;
+                }
+            },
+            syn::Meta::NameValue(_) => {
+                if self.error.is_none() {
+                    self.error = Some(syn::Error::new_spanned(
+                        &attr,
+                        "unroll expects no argument (full unroll) or one factor: #[unroll] or #[unroll(N)]",
+                    ));
+                }
+                return None;
+            }
+        };
+        if factor.literal_value.is_none() {
+            self.const_expressions.push(factor.clone());
+        }
+        Some(factor)
+    }
+
+    /// Build the `__unroll_config::<FACTOR>()` marker statement.
+    fn marker_stmt(factor: &ConstU32Expr) -> Stmt {
+        let expr = &factor.expr;
+        parse_quote! {
+            cuda_device::thread::__unroll_config::<{ #expr }>();
+        }
+    }
+}
+
+impl VisitMut for LoopUnrollAttrVisitor {
+    fn visit_expr_mut(&mut self, expr: &mut Expr) {
+        // Pull the unroll factor (if any) off this loop expr and inject the
+        // marker into its body. We act only on loop expressions; everything
+        // else falls through to the default recursion below.
+        match expr {
+            Expr::ForLoop(for_loop) => {
+                if let Some(factor) = self.take_unroll_factor(&mut for_loop.attrs) {
+                    for_loop.body.stmts.insert(0, Self::marker_stmt(&factor));
+                }
+            }
+            Expr::While(while_loop) => {
+                if let Some(factor) = self.take_unroll_factor(&mut while_loop.attrs) {
+                    while_loop.body.stmts.insert(0, Self::marker_stmt(&factor));
+                }
+            }
+            Expr::Loop(loop_expr) => {
+                if let Some(factor) = self.take_unroll_factor(&mut loop_expr.attrs) {
+                    loop_expr.body.stmts.insert(0, Self::marker_stmt(&factor));
+                }
+            }
+            _ => {}
+        }
+
+        // Recurse into nested expressions/blocks so annotated loops nested
+        // inside other loops, `if`s, or blocks are also handled.
+        visit_mut::visit_expr_mut(self, expr);
+    }
+}
+
+/// Consume per-loop unroll annotations in a kernel or device function and
+/// replace them with the marker calls understood by the MIR importer.
+pub(crate) fn rewrite_loop_unroll_attrs(input: &mut ItemFn) -> syn::Result<()> {
+    let mut visitor = LoopUnrollAttrVisitor::default();
+    visitor.visit_block_mut(&mut input.block);
+    if let Some(err) = visitor.error {
+        return Err(err);
+    }
+    for expression in &visitor.const_expressions {
+        add_const_evaluatable_bound(&mut input.sig.generics, expression);
+    }
+    Ok(())
+}
+
+pub(crate) fn cluster_launch_entry(attr: TokenStream, item: TokenStream) -> TokenStream {
+    let args: ClusterArgs = parse_macro_input!(attr as ClusterArgs);
+    let mut input = parse_macro_input!(item as ItemFn);
+
+    let x = args.x;
+    let y = args.y;
+    let z = args.z;
+
+    // Inject the cluster config marker at the start of the function body
+    let marker_call: syn::Stmt = syn::parse_quote! {
+        ::cuda_device::cluster::__cluster_config::<#x, #y, #z>();
+    };
+
+    // Prepend the marker to the function body
+    input.block.stmts.insert(0, marker_call);
+
+    quote! {
+        #input
+    }
+    .into()
+}
+
+/// Arguments for `#[cluster_launch(...)]` attribute.
+pub(crate) struct ClusterArgs {
+    pub(crate) x: u32,
+    pub(crate) y: u32,
+    pub(crate) z: u32,
+}
+
+impl Parse for ClusterArgs {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let args: Punctuated<syn::LitInt, Token![,]> = Punctuated::parse_terminated(input)?;
+        let values: Vec<u32> = args
+            .iter()
+            .map(|lit| lit.base10_parse::<u32>())
+            .collect::<Result<Vec<_>, _>>()?;
+
+        match values.len() {
+            1 => Ok(ClusterArgs {
+                x: values[0],
+                y: 1,
+                z: 1,
+            }),
+            2 => Ok(ClusterArgs {
+                x: values[0],
+                y: values[1],
+                z: 1,
+            }),
+            3 => Ok(ClusterArgs {
+                x: values[0],
+                y: values[1],
+                z: values[2],
+            }),
+            _ => Err(syn::Error::new_spanned(
+                args.first().unwrap(),
+                "cluster expects 1, 2, or 3 dimensions: #[cluster(x)], #[cluster(x, y)], or #[cluster(x, y, z)]",
+            )),
+        }
+    }
+}
+
+pub(crate) fn cooperative_launch_entry(attr: TokenStream, item: TokenStream) -> TokenStream {
+    if !attr.is_empty() {
+        return syn::Error::new(
+            proc_macro2::Span::call_site(),
+            "cooperative_launch takes no arguments: use a bare #[cooperative_launch]",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    // Launch-time only: the marker is consumed by #[cuda_module]; the kernel
+    // body and PTX are unchanged. Parse as a function so misuse on other
+    // items is rejected with a clear error.
+    let input = parse_macro_input!(item as ItemFn);
+    quote! {
+        #input
+    }
+    .into()
+}
diff --git a/crates/cuda-macros/src/lib.rs b/crates/cuda-macros/src/lib.rs
index 01a486a892..537a1fa9a9 100644
--- a/crates/cuda-macros/src/lib.rs
+++ b/crates/cuda-macros/src/lib.rs
@@ -31,12 +31,28 @@
 
 #![feature(proc_macro_def_site, proc_macro_tracked_env)]
 
+mod common;
+mod cuda_module;
+mod device;
 mod device_copy;
+mod kernel;
+mod launch;
+mod launch_attrs;
 mod printf;
 mod ptx_asm;
 
+#[cfg(test)]
+mod tests;
+
 use proc_macro::TokenStream;
 
+use crate::common::track_codegen_environment;
+use crate::launch::{
+    CudaLaunchAsyncInput, CudaLaunchInput, expand_cuda_launch, expand_cuda_launch_async,
+};
+use quote::quote;
+use syn::parse_macro_input;
+
 /// GPU printf macro for formatted output from GPU kernels.
 ///
 /// This macro translates Rust-style format strings to C-style and calls
@@ -164,266 +180,6 @@ pub fn device_copy(input: TokenStream) -> TokenStream {
     let code = device_copy::impl_device_copy(&ast, quote!(::cuda_core::DeviceCopy));
     code.into()
 }
-use proc_macro2::TokenStream as TokenStream2;
-use quote::{format_ident, quote};
-use reserved_oxide_symbols::{
-    CODEGEN_FINGERPRINT_ENV, DEVICE_CODEGEN_CRATE_ENV, DEVICE_EXTERN_PREFIX, DEVICE_PREFIX,
-    INSTANTIATE_PREFIX, KERNEL_PREFIX, KERNEL_SCOPE_LOCAL, MATERIALIZE_CUBIN_ENV,
-    MATERIALIZER_PROVENANCE_ENV, RESERVED_ROOT, artifact_anchor_symbol, artifact_anchor_symbol_v2,
-    constant_symbol, ptx_merge_required_marker,
-};
-use syn::{
-    Expr, ExprCall, ExprMethodCall, ExprPath, FnArg, ForeignItem, GenericArgument, GenericParam,
-    Ident, Item, ItemFn, ItemForeignMod, ItemMod, LitStr, Pat, Path, PathArguments, Stmt, Token,
-    Type, bracketed, parenthesized,
-    parse::{Parse, ParseStream},
-    parse_macro_input, parse_quote, parse_quote_spanned,
-    punctuated::Punctuated,
-    spanned::Spanned,
-    visit::{self, Visit},
-    visit_mut::{self, VisitMut},
-};
-
-/// Record cuda-oxide's exact device-codegen identity in the consuming crate's
-/// dep-info. Cargo then rebuilds only crates that can own or instantiate device
-/// code when output mode, architecture, policy, or tool provenance changes.
-fn track_codegen_environment() {
-    let _ = proc_macro::tracked::env_var(CODEGEN_FINGERPRINT_ENV);
-    let _ = proc_macro::tracked::env_var(MATERIALIZE_CUBIN_ENV);
-    let _ = proc_macro::tracked::env_var(MATERIALIZER_PROVENANCE_ENV);
-}
-
-/// Build a private identifier that cannot capture, or be captured by, a name
-/// written in the user's kernel signature.
-fn internal_ident(name: &str) -> Ident {
-    let span = if proc_macro::is_available() {
-        proc_macro::Span::def_site().into()
-    } else {
-        // Expansion helpers are also exercised as ordinary unit tests, where
-        // the compiler's procedural-macro bridge is intentionally unavailable.
-        proc_macro2::Span::call_site()
-    };
-    Ident::new(name, span)
-}
-
-fn cuda_module_async_lifetime() -> syn::Lifetime {
-    let ident = internal_ident("__cuda_oxide_async");
-    syn::Lifetime::new(&format!("'{}", ident), ident.span())
-}
-
-struct IdentFinder<'a> {
-    name: &'a str,
-    found: bool,
-}
-
-impl<'ast> Visit<'ast> for IdentFinder<'_> {
-    fn visit_ident(&mut self, ident: &'ast Ident) {
-        self.found |= ident == self.name;
-    }
-}
-
-fn call_site_ident_avoiding_item(name: &str, item: &ItemFn) -> Ident {
-    let mut candidate = name.to_owned();
-    loop {
-        let mut finder = IdentFinder {
-            name: &candidate,
-            found: false,
-        };
-        finder.visit_item_fn(item);
-        if !finder.found {
-            break;
-        }
-        candidate.push('_');
-    }
-    Ident::new(&candidate, proc_macro2::Span::call_site())
-}
-
-/// Reject function names that start with the reserved cuda-oxide prefix
-/// (`cuda_oxide_`).
-///
-/// User code must not define functions in the cuda-oxide internal naming
-/// namespace. Two failure modes this guards against:
-///
-/// 1. **Cosmetic.** `#[kernel] fn cuda_oxide_kernel_foo()` would expand to
-///    a doubly-nested name like
-///    `fn cuda_oxide_kernel_<hash>_cuda_oxide_kernel_foo()`, producing
-///    confusing symbol names in MIR dumps and stack traces.
-/// 2. **Forward-compatibility.** Future refactors may extend the namespace;
-///    rejecting it at the source level keeps the contract clean.
-///
-/// Returns `Some(compile_error)` to be returned from the macro entry point,
-/// or `None` if the name is safe.
-fn reject_reserved_name(name: &Ident) -> Option<TokenStream> {
-    let name_str = name.to_string();
-    if name_str.starts_with(RESERVED_ROOT) {
-        let msg = format!(
-            "function name `{name_str}` starts with the reserved cuda-oxide \
-             prefix `{RESERVED_ROOT}`; rename your function — this namespace \
-             is reserved for cuda-oxide internal symbol mangling \
-             (see crates/reserved-oxide-symbols)"
-        );
-        Some(syn::Error::new(name.span(), msg).to_compile_error().into())
-    } else {
-        None
-    }
-}
-
-/// Reject argument-position `impl Trait`, which rustc represents as a hidden
-/// type parameter that procedural macros cannot name at launch sites.
-///
-/// Without this check the host emits a non-generic lookup name while the
-/// backend correctly emits a `_TID_...` specialization, causing a runtime
-/// function-not-found error. A named generic preserves the same source-level
-/// intent and gives both sides an explicit specialization identity.
-fn impl_trait_parameter_error(input: &ItemFn, item_kind: &str) -> Option<syn::Error> {
-    #[derive(Default)]
-    struct Finder {
-        first: Option<syn::TypeImplTrait>,
-    }
-
-    impl<'ast> syn::visit::Visit<'ast> for Finder {
-        fn visit_type_impl_trait(&mut self, node: &'ast syn::TypeImplTrait) {
-            if self.first.is_none() {
-                self.first = Some(node.clone());
-            }
-        }
-    }
-
-    let mut finder = Finder::default();
-    for arg in &input.sig.inputs {
-        if let FnArg::Typed(pat_type) = arg {
-            syn::visit::Visit::visit_type(&mut finder, &pat_type.ty);
-        }
-    }
-
-    finder.first.map(|impl_trait| {
-        syn::Error::new_spanned(
-            impl_trait,
-            format!(
-                "{item_kind} parameters cannot use `impl Trait`; name the type parameter explicitly (for example, `fn named<T: Trait>(value: T)`) so host and device specialization identities agree"
-            ),
-        )
-    })
-}
-
-/// Attribute arguments for `#[kernel(...)]`.
-///
-/// Legacy explicit-instantiation types, the optional launch-context binding,
-/// and the bare `unchecked_indexing` flag may appear in any order:
-///
-/// ```ignore
-/// #[kernel(launch_context = launch_context)]
-/// #[kernel(f32, f64, launch_context = launch_context)]
-/// #[kernel(unchecked_indexing)]
-/// #[kernel(f32, unchecked_indexing)]
-/// #[kernel(launch_context = launch_context, unchecked_indexing)]
-/// ```
-struct KernelArgs {
-    /// Types to instantiate generic kernels for
-    instantiate_types: Vec<Type>,
-    /// User-selected name for the entry's typed launch context.
-    launch_context: Option<Ident>,
-    /// Elide slice/array bounds checks in this kernel's body (UB contract).
-    unchecked_indexing: bool,
-}
-
-/// Returns true when the next attribute argument is exactly the bare flag
-/// word `flag` (an identifier followed by `,` or end of input, never `=`).
-///
-/// A bare identifier also parses as a `Type`, so this peek must run before
-/// the legacy instantiation-type fallback to keep flag words from being
-/// swallowed as type arguments.
-fn peek_bare_kernel_flag(input: ParseStream, flag: &str) -> bool {
-    if !input.peek(Ident) || input.peek2(Token![=]) {
-        return false;
-    }
-    let fork = input.fork();
-    match fork.parse::<Ident>() {
-        Ok(ident) => ident == flag && (fork.is_empty() || fork.peek(Token![,])),
-        Err(_) => false,
-    }
-}
-
-impl Parse for KernelArgs {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        let mut instantiate_types = Vec::new();
-        let mut launch_context = None;
-        let mut unchecked_indexing = false;
-
-        while !input.is_empty() {
-            if input.peek(Ident) && input.peek2(Token![=]) {
-                let name: Ident = input.parse()?;
-                input.parse::<Token![=]>()?;
-                if name != "launch_context" {
-                    return Err(syn::Error::new(
-                        name.span(),
-                        format!(
-                            "unknown #[kernel] named argument `{name}`; expected `launch_context = IDENT`"
-                        ),
-                    ));
-                }
-                let value: Ident = input.parse().map_err(|_| {
-                    syn::Error::new(
-                        input.span(),
-                        "`launch_context` must be a single Rust identifier",
-                    )
-                })?;
-                if launch_context.replace(value).is_some() {
-                    return Err(syn::Error::new(
-                        name.span(),
-                        "duplicate `launch_context` argument in #[kernel]",
-                    ));
-                }
-            } else if peek_bare_kernel_flag(input, "unchecked_indexing") {
-                let flag: Ident = input.parse()?;
-                if unchecked_indexing {
-                    return Err(syn::Error::new(
-                        flag.span(),
-                        "duplicate `unchecked_indexing` argument in #[kernel]",
-                    ));
-                }
-                unchecked_indexing = true;
-            } else {
-                instantiate_types.push(input.parse::<Type>()?);
-            }
-
-            if input.is_empty() {
-                break;
-            }
-            input.parse::<Token![,]>()?;
-        }
-
-        Ok(KernelArgs {
-            instantiate_types,
-            launch_context,
-            unchecked_indexing,
-        })
-    }
-}
-
-fn scope_parameter_collision(input: &ItemFn, scope: &Ident) -> Option<Ident> {
-    struct Finder<'a> {
-        scope: &'a Ident,
-        found: Option<Ident>,
-    }
-
-    impl<'ast> syn::visit::Visit<'ast> for Finder<'_> {
-        fn visit_pat_ident(&mut self, pattern: &'ast syn::PatIdent) {
-            if self.found.is_none() && pattern.ident == *self.scope {
-                self.found = Some(pattern.ident.clone());
-            }
-            syn::visit::visit_pat_ident(self, pattern);
-        }
-    }
-
-    let mut finder = Finder { scope, found: None };
-    for argument in &input.sig.inputs {
-        if let FnArg::Typed(argument) = argument {
-            syn::visit::Visit::visit_pat(&mut finder, &argument.pat);
-        }
-    }
-    finder.found
-}
 
 /// Generates a typed host-side loader and launch surface for the kernels in an
 /// inline module.
@@ -513,5340 +269,205 @@ fn scope_parameter_collision(input: &ItemFn, scope: &Ident) -> Option<Ident> {
 /// when the source kernel itself is safe.
 #[proc_macro_attribute]
 pub fn cuda_module(attr: TokenStream, item: TokenStream) -> TokenStream {
-    track_codegen_environment();
-    if !attr.is_empty() {
-        return syn::Error::new(
-            proc_macro2::Span::call_site(),
-            "cuda_module does not take arguments yet",
-        )
-        .to_compile_error()
-        .into();
-    }
-
-    let input = parse_macro_input!(item as ItemMod);
-    match expand_cuda_module(input) {
-        Ok(tokens) => tokens.into(),
-        Err(error) => error.to_compile_error().into(),
-    }
-}
-
-struct CudaModuleKernel {
-    module_path: Vec<Ident>,
-    vis: syn::Visibility,
-    /// Availability attributes written directly on the kernel. Generated
-    /// fields and methods live in the same module, so ancestor attributes are
-    /// already inherited there.
-    cfg_attrs: Vec<syn::Attribute>,
-    /// Availability attributes from every enclosing inline module followed by
-    /// the kernel's own attributes. Root-level artifact references need the
-    /// complete chain because they live outside those child modules.
-    effective_cfg_attrs: Vec<syn::Attribute>,
-    method_attrs: Vec<syn::Attribute>,
-    unsafety: Option<Token![unsafe]>,
-    fn_name: Ident,
-    generics: syn::Generics,
-    params: Vec<CudaModuleParam>,
-    cluster_dim: Option<(u32, u32, u32)>,
-    cooperative: bool,
-    launch_contract: Option<CudaModuleLaunchContract>,
-    is_generic: bool,
+    cuda_module::cuda_module_entry(attr, item)
 }
 
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-enum DynamicSharedContract {
-    Exact(u32),
-    Range { min_bytes: u32, max_bytes: u32 },
-}
-
-#[derive(Clone)]
-struct CudaModuleLaunchContract {
-    domain: u8,
-    u32_coordinates: bool,
-    exact_block: Option<(u32, u32, u32)>,
-    max_block_threads: Option<ConstU32Expr>,
-    dynamic_shared: DynamicSharedContract,
-    dynamic_shared_alignment: u32,
-    min_compute_capability: (u32, u32),
-    /// Size requirements over the kernel's own parameters, validated
-    /// against the parameter list at expansion time. Each relation becomes an
-    /// overflow-safe host-side check in every checked launcher.
-    requires: Vec<Expr>,
-}
-
-/// Arguments accepted by `#[launch_contract(...)]`.
-///
-/// The attribute is intentionally declarative. The kernel author states the
-/// launch domain and resource envelope; `#[cuda_module]` turns that statement
-/// into a branded host configuration and validates it against the live
-/// function/device once during preparation.
-#[derive(Clone)]
-struct LaunchContractArgs {
-    domain: u8,
-    u32_coordinates: bool,
-    exact_block: Option<(u32, u32, u32)>,
-    dynamic_shared: DynamicSharedContract,
-    dynamic_shared_alignment: u32,
-    min_compute_capability: (u32, u32),
-    requires: Vec<Expr>,
-}
-
-impl Parse for LaunchContractArgs {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        let mut domain = None;
-        let mut exact_block = None;
-        let mut coordinates = None;
-        let mut dynamic_shared = None;
-        let mut dynamic_shared_range = None;
-        let mut dynamic_shared_alignment = None;
-        let mut min_compute_capability = None;
-        let mut requires = None;
-
-        while !input.is_empty() {
-            let key: Ident = input.parse()?;
-            input.parse::<Token![=]>()?;
-            match key.to_string().as_str() {
-                "domain" => {
-                    reject_duplicate(&key, domain.is_some())?;
-                    let value: syn::LitInt = input.parse()?;
-                    domain = Some(value.base10_parse::<u8>()?);
-                }
-                "block" => {
-                    reject_duplicate(&key, exact_block.is_some())?;
-                    exact_block = Some(parse_u32_triplet(input, "block")?);
-                }
-                "coordinates" => {
-                    reject_duplicate(&key, coordinates.is_some())?;
-                    let width: Ident = input.parse()?;
-                    if width != "u32" {
-                        return Err(syn::Error::new(
-                            width.span(),
-                            "launch_contract coordinates currently supports only `u32`",
-                        ));
-                    }
-                    coordinates = Some(true);
-                }
-                "dynamic_shared" => {
-                    reject_duplicate(&key, dynamic_shared.is_some())?;
-                    let value: syn::LitInt = input.parse()?;
-                    dynamic_shared = Some(value.base10_parse::<u32>()?);
-                }
-                "dynamic_shared_range" => {
-                    reject_duplicate(&key, dynamic_shared_range.is_some())?;
-                    dynamic_shared_range = Some(parse_u32_pair(input, "dynamic_shared_range")?);
-                }
-                "dynamic_shared_alignment" => {
-                    reject_duplicate(&key, dynamic_shared_alignment.is_some())?;
-                    let value: syn::LitInt = input.parse()?;
-                    dynamic_shared_alignment = Some(value.base10_parse::<u32>()?);
-                }
-                "min_compute_capability" => {
-                    reject_duplicate(&key, min_compute_capability.is_some())?;
-                    let (major, minor) = parse_u32_pair(input, "min_compute_capability")?;
-                    min_compute_capability = Some((major, minor));
-                }
-                "requires" => {
-                    reject_duplicate(&key, requires.is_some())?;
-                    requires = Some(parse_requires_relations(input)?);
-                }
-                _ => {
-                    return Err(syn::Error::new(
-                        key.span(),
-                        "unknown launch_contract field; expected domain, coordinates, block, dynamic_shared, dynamic_shared_range, dynamic_shared_alignment, min_compute_capability, or requires",
-                    ));
-                }
-            }
-
-            if input.is_empty() {
-                break;
-            }
-            input.parse::<Token![,]>()?;
-        }
-
-        let domain = domain.ok_or_else(|| {
-            syn::Error::new(
-                input.span(),
-                "launch_contract requires `domain = 1`, `2`, or `3`",
-            )
-        })?;
-        if !(1..=3).contains(&domain) {
-            return Err(syn::Error::new(
-                input.span(),
-                "launch_contract domain must be 1, 2, or 3",
-            ));
-        }
-        if dynamic_shared.is_some() && dynamic_shared_range.is_some() {
-            return Err(syn::Error::new(
-                input.span(),
-                "launch_contract accepts either `dynamic_shared` or `dynamic_shared_range`, not both",
-            ));
-        }
-        let dynamic_shared = match (dynamic_shared, dynamic_shared_range) {
-            (Some(bytes), None) => DynamicSharedContract::Exact(bytes),
-            (None, Some((min_bytes, max_bytes))) if min_bytes <= max_bytes => {
-                DynamicSharedContract::Range {
-                    min_bytes,
-                    max_bytes,
-                }
-            }
-            (None, Some(_)) => {
-                return Err(syn::Error::new(
-                    input.span(),
-                    "dynamic_shared_range minimum cannot exceed its maximum",
-                ));
-            }
-            (None, None) => DynamicSharedContract::Exact(0),
-            (Some(_), Some(_)) => unreachable!(),
-        };
-        let dynamic_shared_alignment = dynamic_shared_alignment.unwrap_or_else(|| {
-            if dynamic_shared_max(dynamic_shared) == 0 {
-                1
-            } else {
-                16
-            }
-        });
-        if dynamic_shared_alignment == 0 || !dynamic_shared_alignment.is_power_of_two() {
-            return Err(syn::Error::new(
-                input.span(),
-                "dynamic_shared_alignment must be a non-zero power of two",
-            ));
-        }
-        if exact_block.is_none() {
-            // A missing exact shape is valid only when #[launch_bounds]
-            // supplies the compiled maximum. This is checked after all kernel
-            // attributes have been collected so the two attributes remain one
-            // source of truth rather than duplicate integers.
-        }
-        let min_compute_capability = min_compute_capability.unwrap_or((0, 0));
-        Ok(Self {
-            domain,
-            u32_coordinates: coordinates.unwrap_or(false),
-            exact_block,
-            dynamic_shared,
-            dynamic_shared_alignment,
-            min_compute_capability,
-            requires: requires.unwrap_or_default(),
-        })
-    }
-}
-
-/// Parses `requires = (relation, relation, ...)`: a parenthesized,
-/// comma-separated, non-empty list of relation expressions. The grammar of
-/// each relation is validated later, once the kernel's parameter list is
-/// known (see [`validate_requires_relations`]).
-fn parse_requires_relations(input: ParseStream) -> syn::Result<Vec<Expr>> {
-    let content;
-    parenthesized!(content in input);
-    let relations: Punctuated<Expr, Token![,]> = Punctuated::parse_terminated(&content)?;
-    if relations.is_empty() {
-        return Err(syn::Error::new(
-            content.span(),
-            "requires needs at least one relation, e.g. `requires = (a.len() >= n)`",
-        ));
-    }
-    Ok(relations.into_iter().collect())
-}
-
-fn dynamic_shared_max(contract: DynamicSharedContract) -> u32 {
-    match contract {
-        DynamicSharedContract::Exact(bytes) => bytes,
-        DynamicSharedContract::Range { max_bytes, .. } => max_bytes,
-    }
-}
-
-fn reject_duplicate(key: &Ident, duplicate: bool) -> syn::Result<()> {
-    if duplicate {
-        Err(syn::Error::new(
-            key.span(),
-            format!("duplicate launch_contract field `{key}`"),
-        ))
-    } else {
-        Ok(())
-    }
+/// Marks a function as a CUDA kernel.
+///
+/// This attribute:
+/// 1. Adds `#[no_mangle]` to preserve the function name in the binary
+/// 2. Marks the function for detection by the `rustc-codegen-cuda` backend
+///
+/// # Generic Kernels
+///
+/// For generic kernels (like `template<class F> __global__` in CUDA C++),
+/// specify the types to instantiate:
+///
+/// ```ignore
+/// #[kernel(Scale, Fma, Square)]
+/// pub fn map<F: GpuFn>(f: F, input: &[i32], output: DisjointSlice<i32>) {
+///     // ...
+/// }
+/// ```
+///
+/// This generates three PTX entry points: `map_Scale`, `map_Fma`, `map_Square`.
+/// Each is a monomorphized version of the generic kernel.
+///
+/// # Example (non-generic)
+///
+/// ```ignore
+/// #[kernel]
+/// pub fn simple_kernel(data: &mut [i32]) {
+///     // ...
+/// }
+/// ```
+///
+/// Kernels that use contract-backed fast coordinates name their launch
+/// capability explicitly. It is a local device-only binding, not an ABI
+/// parameter:
+///
+/// ```ignore
+/// #[kernel(launch_context = launch_context)]
+/// #[launch_contract(domain = 1, coordinates = u32, block = (256, 1, 1))]
+/// pub fn map(mut output: DisjointSlice<u32>) {
+///     let index = thread::index_1d_u32(launch_context);
+///     // ...
+/// }
+/// ```
+///
+/// # Unchecked indexing (opt-in, trust-me contract)
+///
+/// `#[kernel(unchecked_indexing)]` tells the compiler to **delete the safety
+/// check behind slice/array indexing** (`a[i]`) in this kernel. Normally
+/// every `a[i]` compiles to "is `i` inside the slice? if not, stop the
+/// kernel"; with this flag the access happens unconditionally. You are
+/// promising that every index is in bounds, the same promise as
+/// [`slice::get_unchecked`]. If the promise is wrong, the result is
+/// **undefined behavior**: no guard, no trap, possibly silent corruption of
+/// unrelated data. Turn it on only after the checked build is proven correct
+/// (for example under `compute-sanitizer`).
+///
+/// ```ignore
+/// #[kernel(unchecked_indexing)]
+/// pub fn hot_loop(a: &[f32], b: &[f32], mut c: DisjointSlice<f32>) {
+///     let idx = thread::index_1d().get();
+///     if let Some(out) = c.get_mut(thread::index_1d()) {
+///         *out = a[idx] + b[idx]; // no bounds guard or trap emitted
+///     }
+/// }
+/// ```
+///
+/// The flag composes with the other kernel arguments, e.g.
+/// `#[kernel(f32, unchecked_indexing)]` or
+/// `#[kernel(launch_context = lc, unchecked_indexing)]`.
+///
+/// The bare word `unchecked_indexing` is **reserved** in the `#[kernel]`
+/// argument list: it always parses as this flag, never as a legacy
+/// instantiation type. A user type literally named `unchecked_indexing` can
+/// still be instantiated by spelling it as a path, e.g.
+/// `#[kernel(self::unchecked_indexing)]` or
+/// `#[kernel(crate::unchecked_indexing)]`, which parses as a type.
+///
+/// Scope and caveats:
+///
+/// - Only the checks behind indexing (`a[i]`) are removed. Arithmetic
+///   overflow, division/remainder by zero, misaligned-pointer checks, and
+///   every other safety check keep their normal compare-and-trap behavior.
+/// - Range-indexing failures (`&a[i..j]`) and explicit panics arrive as calls
+///   to `core::panicking::*`, not as MIR asserts, so they still trap.
+/// - The flag covers the kernel's translated MIR body, including everything
+///   rustc MIR-inlined into it. Separately translated `#[device]` functions
+///   are **not** covered; the whole-build switch
+///   `CUDA_OXIDE_UNCHECKED_INDEXING=1` (or `cargo oxide ...
+///   --unchecked-indexing`) covers every translated body.
+/// - Elision never leaks out of the opted kernel. For generic kernels
+///   (including legacy `#[kernel(T, ...)]` instantiation), the expansion
+///   keeps the elision marker on the generated entry function plus a hidden
+///   unchecked twin of the implementation that only that entry calls. The
+///   user-named implementation function stays ordinary bounds-checked Rust,
+///   so a different kernel or `#[device]` function that calls it keeps its
+///   own bounds checks (fail-closed).
+///
+/// # Loop unrolling
+///
+/// Put `#[unroll]` on a loop with a compile-time-known trip count to request full
+/// unrolling. Use `#[unroll(N)]`, where `N >= 2`, to request `N` iterations of
+/// work per trip; a remainder loop handles any leftovers.
+///
+/// ```ignore
+/// #[kernel]
+/// pub fn example(n: u32) {
+///     let mut i = 0;
+///     #[unroll]
+///     while i < 4 { work(i); i += 1; }
+///
+///     let mut j = 0;
+///     #[unroll(4)]
+///     while j < n { work(j); j += 1; }
+/// }
+/// ```
+///
+/// A factor may also be a typed `u32` policy constant, such as
+/// `#[unroll(P::UNROLL)]`. A generic expression currently requires Rust's
+/// `generic_const_exprs` feature. Partial factors must be in `2..=1024`; an
+/// invalid specialization fails compilation instead of becoming a no-op.
+///
+/// The pass currently recognizes explicit counted `while` loops. Range-based
+/// `for` loops are not yet recognized.
+///
+/// Only the annotated loop is unrolled. Inner loops are copied intact unless
+/// they carry their own annotation. Several `continue` paths (multiple
+/// back-edges) are supported.
+///
+/// Full `#[unroll]` preserves `break` paths and multiple exit targets. Partial
+/// `#[unroll(N)]` currently requires the loop condition to be the only exit. If
+/// the loop has a `break` or another extra exit, the compiler warns and skips
+/// partial unrolling for that loop.
+///
+/// Partial unrolling also requires a positive counter step, a `<` or `<=` test,
+/// and a limit that does not change inside the loop. One annotation may create
+/// at most 1,024 body copies, 8,192 cloned basic blocks, and 65,536 cloned
+/// operations. Factors above 1,024 are rejected; unsupported loop shapes warn
+/// and are not unrolled.
+#[proc_macro_attribute]
+pub fn kernel(attr: TokenStream, item: TokenStream) -> TokenStream {
+    kernel::kernel_entry(attr, item)
 }
 
-fn parse_u32_triplet(input: ParseStream, field: &str) -> syn::Result<(u32, u32, u32)> {
-    let content;
-    parenthesized!(content in input);
-    let values: Punctuated<syn::LitInt, Token![,]> = Punctuated::parse_terminated(&content)?;
-    if values.len() != 3 {
-        return Err(syn::Error::new(
-            content.span(),
-            format!("{field} must be a three-dimensional tuple `(x, y, z)`"),
-        ));
-    }
-    let mut values = values.iter();
-    Ok((
-        values.next().unwrap().base10_parse()?,
-        values.next().unwrap().base10_parse()?,
-        values.next().unwrap().base10_parse()?,
-    ))
-}
-
-fn parse_u32_pair(input: ParseStream, field: &str) -> syn::Result<(u32, u32)> {
-    let content;
-    parenthesized!(content in input);
-    let values: Punctuated<syn::LitInt, Token![,]> = Punctuated::parse_terminated(&content)?;
-    if values.len() != 2 {
-        return Err(syn::Error::new(
-            content.span(),
-            format!("{field} must be a two-value tuple"),
-        ));
-    }
-    let mut values = values.iter();
-    Ok((
-        values.next().unwrap().base10_parse()?,
-        values.next().unwrap().base10_parse()?,
-    ))
-}
-
-struct CudaModuleParam {
-    name: Ident,
-    sync_host_ty: TokenStream2,
-    async_host_ty: TokenStream2,
-    marshal: CudaModuleParamMarshal,
-    mutable_slice: bool,
-    disjoint_slice_ty: Option<Type>,
-    disjoint_slice_elem: Option<TokenStream2>,
-    /// Declared type and carried scalar of a `Uniform<T>` parameter, used to
-    /// bound the generated impl by the sealed proof trait so a local type also
-    /// named `Uniform` cannot borrow the scalar host ABI.
-    uniform_ty: Option<Type>,
-    uniform_scalar: Option<TokenStream2>,
-    /// Integer classification of a scalar parameter's declared type, used to
-    /// decide which scalars may appear in `requires` relations. Always
-    /// `Other` for non-scalar parameters.
-    scalar_int: ScalarIntClass,
-}
-
-enum CudaModuleParamMarshal {
-    Scalar,
-    ReadOnlyDeviceBuffer {
-        elem_ty: TokenStream2,
-    },
-    WritableDeviceBuffer {
-        elem_ty: TokenStream2,
-    },
-    /// A writable buffer whose index space carries a runtime row width, so
-    /// the host supplies the width and the packet gains a third slot.
-    RowWidthDeviceBuffer {
-        elem_ty: TokenStream2,
-    },
-}
-
-/// Integer classification of a kernel scalar parameter as declared in source.
-///
-/// `requires` relations widen every operand to `u64`, which is lossless for
-/// unsigned scalars but raises sign-extension questions for signed ones, so
-/// v1 accepts only `Unsigned` scalars and rejects the rest at expansion time.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-enum ScalarIntClass {
-    /// `u8`, `u16`, `u32`, `u64`, or `usize`.
-    Unsigned,
-    /// `i8`, `i16`, `i32`, `i64`, or `isize`.
-    Signed,
-    /// Anything else (floats, pointers, generics, non-scalar parameters).
-    Other,
-}
-
-fn scalar_int_class(ty: &Type) -> ScalarIntClass {
-    // A `Uniform<T>` parameter is marshalled as `T` and is evaluated as `T` on
-    // the host, so a relation over it has the same widening behaviour as one
-    // over the bare scalar.
-    if let Some(scalar) = cuda_module_uniform_scalar(ty)
-        && let Ok(scalar) = syn::parse2::<Type>(scalar)
-    {
-        return scalar_int_class(&scalar);
-    }
-
-    let Type::Path(type_path) = ty else {
-        return ScalarIntClass::Other;
-    };
-    if type_path.qself.is_some() {
-        return ScalarIntClass::Other;
-    }
-    let Some(ident) = type_path.path.get_ident() else {
-        return ScalarIntClass::Other;
-    };
-    match ident.to_string().as_str() {
-        "u8" | "u16" | "u32" | "u64" | "usize" => ScalarIntClass::Unsigned,
-        "i8" | "i16" | "i32" | "i64" | "isize" => ScalarIntClass::Signed,
-        _ => ScalarIntClass::Other,
-    }
-}
-
-/// Expands `#[cuda_module]`, emitting the host surface when the `host`
-/// feature is on.
-fn expand_cuda_module(module: ItemMod) -> syn::Result<TokenStream2> {
-    expand_cuda_module_inner(module, cfg!(feature = "host"))
-}
-
-/// `expand_cuda_module` with the host-surface decision passed in.
-///
-/// The decision is a parameter rather than a `cfg!` read inside the body so
-/// that tests can exercise both settings from one build. They otherwise
-/// could not: this crate dev-depends on `cuda-host`, which turns the `host`
-/// feature back on under feature unification even for
-/// `cargo test --no-default-features`.
-fn expand_cuda_module_inner(module: ItemMod, emit_host: bool) -> syn::Result<TokenStream2> {
-    let module_attrs = &module.attrs;
-    let vis = &module.vis;
-    let ident = &module.ident;
-    let Some((_brace, items)) = &module.content else {
-        return Err(syn::Error::new_spanned(
-            &module.ident,
-            "cuda_module requires an inline module so kernel signatures are visible",
-        ));
-    };
-
-    let constants = collect_cuda_module_constants(items, ident)?;
-    let transformed = transform_cuda_module_items(items, &mut Vec::new(), &[], false, emit_host)?;
-    if transformed.kernels.is_empty() {
-        return Err(syn::Error::new_spanned(
-            &module.ident,
-            "cuda_module found no #[kernel] functions in this module",
-        ));
-    }
-    reject_conflicting_kernel_names(&transformed.kernels)?;
-    reject_reserved_loaded_module(items)?;
-
-    let direct_kernels = &transformed.kernels[..transformed.direct_kernel_count];
-    reject_reserved_loaded_module_methods(direct_kernels, false)?;
-    let module_items = cuda_module_items_with_constant_symbols(&transformed.items, &constants);
-
-    let non_generic_kernels = direct_kernels.iter().filter(|kernel| !kernel.is_generic);
-    let function_fields = non_generic_kernels.clone().map(|kernel| {
-        let cfg_attrs = &kernel.cfg_attrs;
-        let field = cuda_module_function_field(&kernel.fn_name);
-        quote! {
-            #(#cfg_attrs)*
-            #field: ::cuda_core::CudaFunction,
-        }
-    });
-
-    let function_initializers = non_generic_kernels.map(|kernel| {
-        let cfg_attrs = &kernel.cfg_attrs;
-        let field = cuda_module_function_field(&kernel.fn_name);
-        let marker = cuda_kernel_marker_name(&kernel.fn_name);
-        quote! {
-            #(#cfg_attrs)*
-            #field: module.load_function(<#marker as ::cuda_host::CudaKernel>::PTX_NAME)?,
-        }
-    });
-
-    let artifact_anchor_statements = cuda_module_artifact_anchor_statements(&transformed.kernels)?;
-    let has_generic = transformed.kernels.iter().any(|k| k.is_generic);
-    let ptx_merge_required_markers = transformed.kernels.iter().filter_map(|kernel| {
-        if !kernel.is_generic {
-            return None;
-        }
-        let marker = internal_ident(&ptx_merge_required_marker(&kernel.fn_name.to_string()));
-        let cfg_attrs = &kernel.effective_cfg_attrs;
-        Some(quote! {
-            #(#cfg_attrs)*
-            // Consumed by the codegen collector. This enabled generic kernel
-            // requires run-time PTX bundle merging, which ahead-of-time cubin
-            // materialization cannot represent yet.
-            #[doc(hidden)]
-            #[used]
-            #[allow(dead_code, non_upper_case_globals)]
-            static #marker: u8 = 0;
-        })
-    });
-    let enable_generic_loader_statements = transformed.kernels.iter().filter_map(|kernel| {
-        if !kernel.is_generic {
-            return None;
-        }
-        let cfg_attrs = &kernel.effective_cfg_attrs;
-        Some(quote! {
-            #(#cfg_attrs)*
-            let _ = {
-                __cuda_oxide_has_enabled_generic_kernel = true;
-            };
-        })
-    });
-    let has_launch_contract = transformed
-        .kernels
-        .iter()
-        .any(|kernel| kernel.launch_contract.is_some());
-    let module_loader = if has_generic {
-        // A syntactically present generic kernel may be removed by cfg. Make
-        // the loader decision under the exact same effective cfg chain as its
-        // marker, so eligibility and run-time behavior cannot disagree.
-        quote! {
-            #[allow(unused_mut)]
-            let mut __cuda_oxide_has_enabled_generic_kernel = false;
-            #(#enable_generic_loader_statements)*
-            let module = if __cuda_oxide_has_enabled_generic_kernel {
-                let _ = name; // merged load ignores the crate-name hint
-                ::cuda_host::load_all_ptx_bundles_merged(ctx)?
-            } else {
-                ::cuda_host::load_embedded_module(ctx, name)?
-            };
-        }
-    } else {
-        quote! {
-            let module = ::cuda_host::load_embedded_module(ctx, name)?;
-        }
-    };
-    let constant_fields = constants.iter().map(generate_cuda_module_constant_field);
-    let constant_initializers = constants
-        .iter()
-        .map(generate_cuda_module_constant_initializer);
-    let launch_contract_impls = direct_kernels
-        .iter()
-        .filter_map(generate_cuda_module_launch_contract_impl);
-    let prepare_launch_methods = direct_kernels
-        .iter()
-        .filter_map(generate_cuda_module_prepare_launch_methods);
-    let launch_methods = direct_kernels
-        .iter()
-        .map(generate_cuda_module_launch_method);
-    let constant_resolver_methods = constants
-        .iter()
-        .map(generate_cuda_module_constant_resolver_method);
-    let set_constant_methods = constants
-        .iter()
-        .map(generate_cuda_module_set_constant_method);
-    let async_module_items = if cfg!(feature = "async") && has_launch_contract {
-        quote! {
-            /// Loads this package's embedded artifact for a contracted module.
-            ///
-            /// # Safety
-            ///
-            /// For a non-generic module, the selected package bundle must be
-            /// the artifact compiled from this `cuda_module`; package names are
-            /// not yet unique across all library and binary targets. For a
-            /// generic module, the merged PTX set must contain each matching
-            /// specialization and no conflicting entry definition.
-            pub unsafe fn load_async(
-                device_id: usize,
-            ) -> ::core::result::Result<LoadedModule, ::cuda_host::cuda_async::error::DeviceError> {
-                // SAFETY: upheld by this function's caller.
-                unsafe { load_async_named(device_id, env!("CARGO_PKG_NAME")) }
-            }
-
-            /// Loads a caller-selected artifact for this contracted module.
-            ///
-            /// # Safety
-            ///
-            /// Every selected kernel must have the exact ABI and resource
-            /// semantics declared by this `cuda_module`. A matching symbol
-            /// name alone is not sufficient.
-            pub unsafe fn load_async_named(
-                device_id: usize,
-                name: &str,
-            ) -> ::core::result::Result<LoadedModule, ::cuda_host::cuda_async::error::DeviceError> {
-                ::cuda_host::load_cuda_module_from_async_context(device_id, |ctx| {
-                    // SAFETY: upheld by this function's caller.
-                    unsafe { load_named(ctx, name) }
-                })
-            }
-        }
-    } else if cfg!(feature = "async") {
-        quote! {
-            pub fn load_async(
-                device_id: usize,
-            ) -> ::core::result::Result<LoadedModule, ::cuda_host::cuda_async::error::DeviceError> {
-                load_async_named(device_id, env!("CARGO_PKG_NAME"))
-            }
-
-            pub fn load_async_named(
-                device_id: usize,
-                name: &str,
-            ) -> ::core::result::Result<LoadedModule, ::cuda_host::cuda_async::error::DeviceError> {
-                ::cuda_host::load_cuda_module_from_async_context(device_id, |ctx| load_named(ctx, name))
-            }
-        }
-    } else {
-        TokenStream2::new()
-    };
-    let load_definition = if has_launch_contract {
-        quote! {
-            /// Loads this package's embedded artifact for a contracted module.
-            ///
-            /// # Safety
-            ///
-            /// For a non-generic module, the selected package bundle must be
-            /// the artifact compiled from this `cuda_module`; package names are
-            /// not yet unique across all library and binary targets. For a
-            /// generic module, the merged PTX set must contain each matching
-            /// specialization and no conflicting entry definition.
-            pub unsafe fn load(
-                ctx: &::std::sync::Arc<::cuda_core::CudaContext>,
-            ) -> ::core::result::Result<LoadedModule, ::cuda_host::EmbeddedModuleError> {
-                // SAFETY: upheld by this function's caller.
-                unsafe { load_named(ctx, env!("CARGO_PKG_NAME")) }
-            }
-        }
-    } else {
-        quote! {
-            pub fn load(
-                ctx: &::std::sync::Arc<::cuda_core::CudaContext>,
-            ) -> ::core::result::Result<LoadedModule, ::cuda_host::EmbeddedModuleError> {
-                load_named(ctx, env!("CARGO_PKG_NAME"))
-            }
-        }
-    };
-    let load_named_definition = if has_launch_contract {
-        quote! {
-            /// Loads a caller-selected artifact for this contracted module.
-            ///
-            /// # Safety
-            ///
-            /// Every selected kernel must have the exact ABI and resource
-            /// semantics declared by this `cuda_module`. A matching symbol
-            /// name alone is not sufficient.
-            pub unsafe fn load_named(
-                ctx: &::std::sync::Arc<::cuda_core::CudaContext>,
-                name: &str,
-            ) -> ::core::result::Result<LoadedModule, ::cuda_host::EmbeddedModuleError> {
-                #artifact_anchor_statements
-                #module_loader
-                // SAFETY: upheld by this function's caller.
-                unsafe { from_module(module) }.map_err(::cuda_host::EmbeddedModuleError::Driver)
-            }
-        }
-    } else {
-        quote! {
-            pub fn load_named(
-                ctx: &::std::sync::Arc<::cuda_core::CudaContext>,
-                name: &str,
-            ) -> ::core::result::Result<LoadedModule, ::cuda_host::EmbeddedModuleError> {
-                #artifact_anchor_statements
-                #module_loader
-                from_module(module).map_err(::cuda_host::EmbeddedModuleError::Driver)
-            }
-        }
-    };
-    let from_module_definition = if has_launch_contract {
-        quote! {
-            /// Binds caller-provided CUDA code to this module's launch API.
-            ///
-            /// # Safety
-            ///
-            /// Every loaded kernel must have the exact ABI and resource
-            /// semantics declared by this `cuda_module`. A matching symbol
-            /// name alone is not sufficient.
-            pub unsafe fn from_module(
-                module: ::std::sync::Arc<::cuda_core::CudaModule>,
-            ) -> ::core::result::Result<LoadedModule, ::cuda_core::DriverError> {
-                Ok(LoadedModule {
-                    __module: module.clone(),
-                    __generic_functions: ::std::sync::Arc::new(
-                        ::std::sync::Mutex::new(::std::collections::HashMap::new())
-                    ),
-                    #(#function_initializers)*
-                    #(#constant_initializers)*
-                })
-            }
-        }
-    } else {
-        quote! {
-            pub fn from_module(
-                module: ::std::sync::Arc<::cuda_core::CudaModule>,
-            ) -> ::core::result::Result<LoadedModule, ::cuda_core::DriverError> {
-                Ok(LoadedModule {
-                    __module: module.clone(),
-                    __generic_functions: ::std::sync::Arc::new(
-                        ::std::sync::Mutex::new(::std::collections::HashMap::new())
-                    ),
-                    #(#function_initializers)*
-                    #(#constant_initializers)*
-                })
-            }
-        }
-    };
-    let async_launch_methods = if cfg!(feature = "async") {
-        let async_launch_methods = direct_kernels
-            .iter()
-            .map(generate_cuda_module_async_launch_method);
-        let owned_async_launch_methods = direct_kernels
-            .iter()
-            .map(generate_cuda_module_owned_async_launch_method);
-        quote! {
-            #(#async_launch_methods)*
-            #(#owned_async_launch_methods)*
-        }
-    } else {
-        TokenStream2::new()
-    };
-
-    // Everything below names `::cuda_host` or `::cuda_core`. The kernels
-    // themselves, and the PTX-merge markers the codegen collector consumes, do
-    // not -- so a crate that only compiles kernels can take cuda-macros with
-    // `default-features = false` and stop depending on the host stack.
-    let host_items = if emit_host {
-        quote! {
-            #(#launch_contract_impls)*
-
-            #[derive(Clone, Debug)]
-            #[allow(non_snake_case)]
-            pub struct LoadedModule {
-                __module: ::std::sync::Arc<::cuda_core::CudaModule>,
-                __generic_functions: ::std::sync::Arc<
-                    ::std::sync::Mutex<
-                        ::std::collections::HashMap<&'static str, ::cuda_core::CudaFunction>
-                    >
-                >,
-                #(#function_fields)*
-                #(#constant_fields)*
-            }
-
-            #load_definition
-
-            #load_named_definition
-
-            #from_module_definition
-
-            #async_module_items
-
-            impl LoadedModule {
-                pub fn as_cuda_module(&self) -> &::std::sync::Arc<::cuda_core::CudaModule> {
-                    &self.__module
-                }
-
-                #(#launch_methods)*
-                #(#prepare_launch_methods)*
-                #(#constant_resolver_methods)*
-                #(#set_constant_methods)*
-                #async_launch_methods
-            }
-        }
-    } else {
-        TokenStream2::new()
-    };
-
-    Ok(quote! {
-        #(#module_attrs)*
-        #vis mod #ident {
-            #(#module_items)*
-            #(#ptx_merge_required_markers)*
-            #host_items
-        }
-    })
-}
-
-struct CudaModuleLevel {
-    items: Vec<Item>,
-    kernels: Vec<CudaModuleKernel>,
-    direct_kernel_count: usize,
-}
-
-/// Recursively rewrite only inline child modules.
-///
-/// Every module that owns a kernel (or contains a deeper module that does)
-/// receives its own `LoadedModule`. That keeps generated method signatures in
-/// the same Rust scope as the source kernel. File-backed modules and
-/// `include!` invocations are preserved but not traversed: their contents are
-/// not present in an attribute macro's input token stream, and reproducing
-/// rustc's module loader in a proc macro is neither complete nor hygienic.
-fn transform_cuda_module_items(
-    items: &[Item],
-    module_path: &mut Vec<Ident>,
-    ancestor_cfg_attrs: &[syn::Attribute],
-    generate_nested_support: bool,
-    emit_host: bool,
-) -> syn::Result<CudaModuleLevel> {
-    let mut transformed_items = Vec::with_capacity(items.len());
-    let mut direct_kernels = Vec::new();
-    let mut descendant_kernels = Vec::new();
-
-    for item in items {
-        match item {
-            Item::Fn(item_fn) => {
-                if let Some(kernel) = cuda_module_kernel(item_fn, module_path, ancestor_cfg_attrs)?
-                {
-                    direct_kernels.push(kernel);
-                }
-                transformed_items.push(item.clone());
-            }
-            Item::Mod(item_mod) => {
-                let Some((_brace, nested_items)) = &item_mod.content else {
-                    // Attribute macros receive the declaration, not the file's
-                    // contents. Preserve it exactly, but do not pretend that
-                    // kernels behind this boundary were discovered.
-                    transformed_items.push(item.clone());
-                    continue;
-                };
-
-                module_path.push(item_mod.ident.clone());
-                let mut nested_cfg_attrs = ancestor_cfg_attrs.to_vec();
-                nested_cfg_attrs.extend(cuda_module_cfg_attrs(&item_mod.attrs)?);
-                let nested = transform_cuda_module_items(
-                    nested_items,
-                    module_path,
-                    &nested_cfg_attrs,
-                    true,
-                    emit_host,
-                )?;
-                module_path.pop();
-
-                let mut transformed_mod = item_mod.clone();
-                transformed_mod
-                    .content
-                    .as_mut()
-                    .expect("inline module content disappeared")
-                    .1 = nested.items;
-                descendant_kernels.extend(nested.kernels);
-                transformed_items.push(Item::Mod(transformed_mod));
-            }
-            _ => transformed_items.push(item.clone()),
-        }
-    }
-
-    let direct_kernel_count = direct_kernels.len();
-    let mut kernels = direct_kernels;
-    kernels.extend(descendant_kernels);
-
-    if generate_nested_support && !kernels.is_empty() {
-        reject_reserved_loaded_module(items)?;
-        reject_reserved_loaded_module_methods(&kernels[..direct_kernel_count], true)?;
-        let support =
-            generate_nested_cuda_module_support(&kernels[..direct_kernel_count], emit_host);
-        let mut support_items = syn::parse2::<syn::File>(support)?.items;
-        transformed_items.append(&mut support_items);
-    }
-
-    Ok(CudaModuleLevel {
-        items: transformed_items,
-        kernels,
-        direct_kernel_count,
-    })
-}
-
-fn reject_reserved_loaded_module(items: &[Item]) -> syn::Result<()> {
-    for item in items {
-        let ident = match item {
-            Item::Const(item) => Some(&item.ident),
-            Item::Enum(item) => Some(&item.ident),
-            Item::ExternCrate(item) => item
-                .rename
-                .as_ref()
-                .map(|(_as_token, rename)| rename)
-                .or(Some(&item.ident)),
-            Item::Fn(item) => Some(&item.sig.ident),
-            Item::Mod(item) => Some(&item.ident),
-            Item::Static(item) => Some(&item.ident),
-            Item::Struct(item) => Some(&item.ident),
-            Item::Trait(item) => Some(&item.ident),
-            Item::TraitAlias(item) => Some(&item.ident),
-            Item::Type(item) => Some(&item.ident),
-            Item::Union(item) => Some(&item.ident),
-            Item::Use(item) => cuda_module_loaded_module_use_binding(&item.tree),
-            _ => None,
-        };
-        if ident.is_some_and(|ident| cuda_module_ident_key(ident) == "LoadedModule") {
-            return Err(syn::Error::new_spanned(
-                ident.expect("checked above"),
-                "#[cuda_module] reserves the name `LoadedModule` in every inline namespace that contains kernels",
-            ));
-        }
-    }
-    Ok(())
-}
-
-fn reject_reserved_loaded_module_methods(
-    kernels: &[CudaModuleKernel],
-    nested: bool,
-) -> syn::Result<()> {
-    for kernel in kernels {
-        let name = cuda_module_ident_key(&kernel.fn_name);
-        let reserved = name == "as_cuda_module" || (nested && name == "from_parent");
-        if reserved {
-            let scope = if name == "from_parent" {
-                "nested kernel namespaces"
-            } else {
-                "every kernel namespace"
-            };
-            return Err(syn::Error::new_spanned(
-                &kernel.fn_name,
-                format!(
-                    "#[cuda_module] reserves launcher method name `{name}` in {scope}; rename the kernel"
-                ),
-            ));
-        }
-    }
-    Ok(())
-}
-
-/// Return the collision key for generated Rust and PTX namespaces.
-///
-/// `syn::Ident::to_string()` preserves a raw prefix, but `step` and `r#step`
-/// name the same Rust identifier and must collide in cuda-oxide's bare PTX
-/// namespace. Guards compare this normalized key before generating anything.
-fn cuda_module_ident_key(ident: &Ident) -> String {
-    let spelling = ident.to_string();
-    spelling.strip_prefix("r#").unwrap_or(&spelling).to_string()
-}
-
-fn cuda_module_loaded_module_use_binding(tree: &syn::UseTree) -> Option<&Ident> {
-    match tree {
-        syn::UseTree::Path(path) => cuda_module_loaded_module_use_binding(&path.tree),
-        syn::UseTree::Name(name) => {
-            (cuda_module_ident_key(&name.ident) == "LoadedModule").then_some(&name.ident)
-        }
-        syn::UseTree::Rename(rename) => {
-            (cuda_module_ident_key(&rename.rename) == "LoadedModule").then_some(&rename.rename)
-        }
-        syn::UseTree::Group(group) => group
-            .items
-            .iter()
-            .find_map(cuda_module_loaded_module_use_binding),
-        syn::UseTree::Glob(_) => None,
-    }
-}
-
-fn cuda_module_kernel(
-    item_fn: &ItemFn,
-    module_path: &[Ident],
-    ancestor_cfg_attrs: &[syn::Attribute],
-) -> syn::Result<Option<CudaModuleKernel>> {
-    if !has_attr_named(&item_fn.attrs, "kernel") {
-        return Ok(None);
-    }
-    if let Some(err) = impl_trait_parameter_error(item_fn, "kernel") {
-        return Err(err);
-    }
-    let cluster_dim = cuda_module_cluster_dim(&item_fn.attrs)?;
-    let cooperative = cuda_module_cooperative(&item_fn.attrs)?;
-    let params = cuda_module_params(item_fn)?;
-    let launch_contract =
-        cuda_module_launch_contract(&item_fn.attrs, &item_fn.sig.ident, &params, cluster_dim)?;
-    // `#[cuda_module]` expands before both the nested function attributes and
-    // the recursive module rewrite. Mirror the evaluatability predicates that
-    // `#[launch_bounds]` and `#[kernel]` add to each concrete entry while
-    // retaining the nested module's path and inherited cfg attributes.
-    let mut configured_item = item_fn.clone();
-    rewrite_loop_unroll_attrs(&mut configured_item)?;
-    add_launch_bounds_evaluatability_from_attrs(&mut configured_item)?;
-    let mut generics = configured_item.sig.generics;
-    if let Some(contract) = launch_contract.as_ref() {
-        add_cuda_module_disjoint_contract_bounds(&mut generics, &params, contract.domain);
-    }
-    // A `Uniform` parameter carries its proof with or without a launch
-    // contract, so this bound is not conditional on one.
-    add_cuda_module_uniform_bounds(&mut generics, &params);
-    // The launch packet's shape (two or three words per slice) must match the
-    // resolved device type with or without a launch contract, so this bound
-    // is unconditional too.
-    add_cuda_module_disjoint_abi_bounds(&mut generics, &params);
-    let is_generic = has_codegen_generics(&item_fn.sig.generics);
-    let cfg_attrs = cuda_module_cfg_attrs(&item_fn.attrs)?;
-    let mut effective_cfg_attrs = ancestor_cfg_attrs.to_vec();
-    effective_cfg_attrs.extend(cfg_attrs.clone());
-    Ok(Some(CudaModuleKernel {
-        module_path: module_path.to_vec(),
-        vis: item_fn.vis.clone(),
-        cfg_attrs,
-        effective_cfg_attrs,
-        method_attrs: cuda_module_method_attrs(&item_fn.attrs),
-        unsafety: item_fn.sig.unsafety,
-        fn_name: item_fn.sig.ident.clone(),
-        generics,
-        params,
-        cluster_dim,
-        cooperative,
-        launch_contract,
-        is_generic,
-    }))
-}
-
-fn generate_nested_cuda_module_support(
-    kernels: &[CudaModuleKernel],
-    emit_host: bool,
-) -> TokenStream2 {
-    let launch_contract_impls = kernels
-        .iter()
-        .filter_map(generate_cuda_module_launch_contract_impl);
-    let prepare_launch_methods = kernels
-        .iter()
-        .filter_map(generate_cuda_module_prepare_launch_methods);
-    let non_generic_kernels = kernels.iter().filter(|kernel| !kernel.is_generic);
-    let function_fields = non_generic_kernels.clone().map(|kernel| {
-        let cfg_attrs = &kernel.cfg_attrs;
-        let field = cuda_module_function_field(&kernel.fn_name);
-        quote! {
-            #(#cfg_attrs)*
-            #field: ::cuda_core::CudaFunction,
-        }
-    });
-    let function_initializers = non_generic_kernels.map(|kernel| {
-        let cfg_attrs = &kernel.cfg_attrs;
-        let field = cuda_module_function_field(&kernel.fn_name);
-        let marker = cuda_kernel_marker_name(&kernel.fn_name);
-        quote! {
-            #(#cfg_attrs)*
-            #field: module.load_function(<#marker as ::cuda_host::CudaKernel>::PTX_NAME)?,
-        }
-    });
-    let launch_methods = kernels.iter().map(generate_cuda_module_launch_method);
-    let async_launch_methods = if cfg!(feature = "async") {
-        let borrowed = kernels.iter().map(generate_cuda_module_async_launch_method);
-        let owned = kernels
-            .iter()
-            .map(generate_cuda_module_owned_async_launch_method);
-        quote! {
-            #(#borrowed)*
-            #(#owned)*
-        }
-    } else {
-        TokenStream2::new()
-    };
-
-    // Host-only, exactly as in `expand_cuda_module_inner`; see the note there.
-    if !emit_host {
-        return TokenStream2::new();
-    }
-
-    quote! {
-        #(#launch_contract_impls)*
-
-        #[derive(Clone, Debug)]
-        #[allow(non_snake_case)]
-        pub struct LoadedModule {
-            __module: ::std::sync::Arc<::cuda_core::CudaModule>,
-            __generic_functions: ::std::sync::Arc<
-                ::std::sync::Mutex<
-                    ::std::collections::HashMap<&'static str, ::cuda_core::CudaFunction>
-                >
-            >,
-            #(#function_fields)*
-        }
-
-        impl LoadedModule {
-            /// Bind this namespace's launchers to a module loaded by its
-            /// immediate parent namespace.
-            pub fn from_parent(
-                parent: &super::LoadedModule,
-            ) -> ::core::result::Result<Self, ::cuda_core::DriverError> {
-                let module = parent.as_cuda_module().clone();
-                Ok(Self {
-                    __module: module.clone(),
-                    __generic_functions: parent.__generic_functions.clone(),
-                    #(#function_initializers)*
-                })
-            }
-
-            pub fn as_cuda_module(&self) -> &::std::sync::Arc<::cuda_core::CudaModule> {
-                &self.__module
-            }
-
-            #(#launch_methods)*
-            #(#prepare_launch_methods)*
-            #async_launch_methods
-        }
-    }
-}
-
-/// Reject duplicate bare kernel names anywhere in one `#[cuda_module]` tree.
-///
-/// Launcher methods are namespace-qualified, but cuda-oxide's current PTX
-/// entry naming is not: `stage1::step` and `stage2::step` both export `step`.
-/// Until the backend and `#[kernel]` share a qualified entry-name contract,
-/// accepting the pair would risk resolving a launcher to the wrong entry.
-/// The restriction is therefore syntactic and also applies to cfg-gated
-/// alternatives; proc macros cannot prove that arbitrary cfg predicates are
-/// mutually exclusive.
-fn reject_conflicting_kernel_names(kernels: &[CudaModuleKernel]) -> syn::Result<()> {
-    let mut names: std::collections::HashMap<String, &CudaModuleKernel> =
-        std::collections::HashMap::new();
-    for kernel in kernels {
-        let name = cuda_module_ident_key(&kernel.fn_name);
-        if let Some(previous) = names.insert(name.clone(), kernel) {
-            return Err(syn::Error::new(
-                kernel.fn_name.span(),
-                format!(
-                    "cuda-oxide PTX entry names are currently bare function names, so \
-                     #[cuda_module] requires kernel names to be unique across its inline \
-                     module tree: `{name}` in {second} conflicts with `{name}` in {first}; \
-                     rename one of the kernels",
-                    name = name,
-                    first = cuda_module_path_description(&previous.module_path),
-                    second = cuda_module_path_description(&kernel.module_path),
-                ),
-            ));
-        }
-    }
-    Ok(())
-}
-
-fn cuda_module_path_description(module_path: &[Ident]) -> String {
-    if module_path.is_empty() {
-        "the module root".to_string()
-    } else {
-        format!(
-            "`{}`",
-            module_path
-                .iter()
-                .map(Ident::to_string)
-                .collect::<Vec<_>>()
-                .join("::")
-        )
-    }
-}
-
-/// Generate the statements that pin this crate's embedded device artifact
-/// into the final binary.
-///
-/// The codegen backend stores each crate's compiled device code (PTX,
-/// cubin, NVVM IR, or LTOIR) in a `.oxart` data section of a small extra
-/// object file. When the crate that holds the `#[cuda_module]` is a
-/// *library*, that object becomes one member of the crate's `.rlib`
-/// archive, and linkers only extract an archive member when it defines a
-/// symbol that some already-linked object references. The backend defines
-/// a global anchor symbol inside the artifact object for exactly this
-/// purpose; here we emit the matching reference. Reading the anchor's
-/// address through `black_box` inside `load_named()` means that any
-/// program calling `load()` carries an undefined reference to the anchor,
-/// which forces the linker to pull the artifact member out of the rlib.
-/// Without this handshake the bundle was silently dropped and `load()`
-/// failed at runtime with `ModuleNotFound` (issue #72).
-///
-/// Without an owner filter, both sides keep using the legacy package+version
-/// anchor for compatibility with older wrappers and backends. A non-empty
-/// owner filter activates the v2 package+version+crate+binary identity. That
-/// target-specific identity prevents an unselected binary from satisfying a
-/// selected library's reference (or vice versa); an unselected new macro emits
-/// no reference at all. The backend also keeps a weak legacy alias for older
-/// macro expansions in mixed-version builds.
-///
-/// The reference is only emitted when the module is guaranteed to produce
-/// an artifact for this crate. Generic kernels are monomorphized (and
-/// their PTX embedded) in the *consuming* crate, so a module with only
-/// generic kernels yields no artifact here, and an anchor reference would
-/// be an undefined-symbol link error. The same reasoning extends to
-/// cfg-gated kernels: root `load()` emits one equivalent guarded reference per
-/// concrete kernel in the complete inline tree. Each reference carries the
-/// kernel's effective ancestor-plus-local availability attributes, so a module
-/// containing only nested kernels is still independently loadable while no
-/// anchor is referenced when every concrete kernel is absent.
-fn cuda_module_artifact_anchor_statements(
-    kernels: &[CudaModuleKernel],
-) -> syn::Result<TokenStream2> {
-    let (Ok(package_name), Ok(package_version), Ok(crate_name)) = (
-        std::env::var("CARGO_PKG_NAME"),
-        std::env::var("CARGO_PKG_VERSION"),
-        std::env::var("CARGO_CRATE_NAME"),
-    ) else {
-        // Not built by cargo (e.g. a raw rustc invocation): the backend
-        // falls back to crate-name-based bundle naming and we cannot
-        // reproduce it exactly, so skip the anchor rather than risk an
-        // undefined symbol.
-        return Ok(TokenStream2::new());
-    };
-
-    let owner_filter = proc_macro::tracked::env_var(DEVICE_CODEGEN_CRATE_ENV).ok();
-    let owner_selection = device_codegen_owner_selection(owner_filter.as_deref(), &crate_name);
-    if owner_selection == Some(false) {
-        // The backend deliberately omits this crate's artifact. Omitting the
-        // reference as well keeps the host link valid without pretending that
-        // a loadable bundle exists.
-        return Ok(TokenStream2::new());
-    }
-
-    if !kernels.iter().any(|kernel| !kernel.is_generic) {
-        return Ok(TokenStream2::new());
-    }
-
-    let binary_name = std::env::var("CARGO_BIN_NAME").ok();
-    let anchor = if owner_selection.is_some() {
-        artifact_anchor_symbol_v2(
-            &package_name,
-            &package_version,
-            &crate_name,
-            binary_name.as_deref(),
-        )
-    } else {
-        artifact_anchor_symbol(&package_name, &package_version)
-    };
-    let anchor_name = LitStr::new(&anchor, proc_macro2::Span::call_site());
-    let references = kernels
-        .iter()
-        .filter(|kernel| !kernel.is_generic)
-        .map(|kernel| {
-            let cfg_attrs = &kernel.effective_cfg_attrs;
-            quote! {
-                #(#cfg_attrs)*
-                let _artifact_anchor: *const ::core::primitive::u8 = {
-                    unsafe extern "C" {
-                        #[link_name = #anchor_name]
-                        static CUDA_OXIDE_BUNDLE_ANCHOR: ::core::primitive::u8;
-                    }
-                    ::std::hint::black_box(unsafe {
-                        ::core::ptr::addr_of!(CUDA_OXIDE_BUNDLE_ANCHOR)
-                    })
-                };
-            }
-        });
-    Ok(quote! {
-        // Keep-alive handshake with the codegen backend: see the macro
-        // crate's `cuda_module_artifact_anchor_statements` for details.
-        #(#references)*
-    })
-}
-
-fn device_codegen_owner_selection(raw: Option<&str>, crate_name: &str) -> Option<bool> {
-    let crate_name = crate_name.trim().replace('-', "_");
-    raw.and_then(|raw| {
-        let owners: Vec<_> = raw
-            .split(',')
-            .map(|name| name.trim().replace('-', "_"))
-            .filter(|name| !name.is_empty())
-            .collect();
-        (!owners.is_empty()).then(|| owners.iter().any(|owner| owner == &crate_name))
-    })
-}
-
-/// A `#[constant]` static collected from a `#[cuda_module]` body.
-struct CudaModuleConstant {
-    ident: Ident,
-    ty: Box<Type>,
-    cfg_attrs: Vec<syn::Attribute>,
-    method_attrs: Vec<syn::Attribute>,
-    symbol: String,
-}
-
-fn collect_cuda_module_constants(
-    items: &[Item],
-    module_ident: &Ident,
-) -> syn::Result<Vec<CudaModuleConstant>> {
-    let mut constants = Vec::new();
-    for item in items {
-        let Item::Static(item_static) = item else {
-            continue;
-        };
-        if !has_attr_named(&item_static.attrs, "constant") {
-            continue;
-        }
-        if extract_constant_inner_ty(&item_static.ty).is_none() {
-            return Err(syn::Error::new_spanned(
-                &item_static.ty,
-                concat!(
-                    "#[constant] static must have type `ConstantMemory<T>` ",
-                    "(e.g. `static FOO: ConstantMemory<[f32; 4]> = ConstantMemory::UNINIT;`). ",
-                    "The wrapper prevents the compiler from constant-folding the initializer into kernel bodies.",
-                ),
-            ));
-        }
-        constants.push(CudaModuleConstant {
-            ident: item_static.ident.clone(),
-            ty: item_static.ty.clone(),
-            cfg_attrs: cuda_module_cfg_attrs(&item_static.attrs)?,
-            method_attrs: cuda_module_method_attrs(&item_static.attrs),
-            symbol: cuda_module_constant_symbol(module_ident, &item_static.ident),
-        });
-    }
-    Ok(constants)
-}
-
-fn cuda_module_constant_symbol(module_ident: &Ident, ident: &Ident) -> String {
-    let start = ident.span().start();
-    let base = format!(
-        "{}_L{}C{}_{}",
-        module_ident, start.line, start.column, ident
-    );
-    constant_symbol(&base)
-}
-
-fn cuda_module_items_with_constant_symbols(
-    items: &[Item],
-    constants: &[CudaModuleConstant],
-) -> Vec<TokenStream2> {
-    let mut constants = constants.iter();
-    items
-        .iter()
-        .map(|item| {
-            let Item::Static(item_static) = item else {
-                return quote! { #item };
-            };
-            if !has_attr_named(&item_static.attrs, "constant") {
-                return quote! { #item };
-            }
-            let constant = constants
-                .next()
-                .expect("constant collection and rewrite order drifted");
-
-            let mut item_static = item_static.clone();
-            let symbol = LitStr::new(&constant.symbol, constant.ident.span());
-            item_static.attrs = item_static
-                .attrs
-                .into_iter()
-                .map(|attr| {
-                    if attr_path_ends_with(&attr, "constant") {
-                        let path = attr.path().clone();
-                        parse_quote!(#[#path(export_name = #symbol)])
-                    } else {
-                        attr
-                    }
-                })
-                .collect();
-            quote! { #item_static }
-        })
-        .collect()
-}
-
-fn cuda_module_constant_field_ident(ident: &Ident) -> Ident {
-    format_ident!("__{}", ident)
-}
-
-fn cuda_module_constant_resolver_ident(ident: &Ident) -> Ident {
-    format_ident!("__resolve_{}", ident)
-}
-
-/// Extract `T` from a `ConstantMemory<T>` type path. Returns `None` for anything
-/// that's not a path ending in `ConstantMemory<...>` with one generic argument.
-fn extract_constant_inner_ty(ty: &Type) -> Option<&Type> {
-    let Type::Path(type_path) = ty else {
-        return None;
-    };
-    let last = type_path.path.segments.last()?;
-    if last.ident != "ConstantMemory" {
-        return None;
-    }
-    let syn::PathArguments::AngleBracketed(args) = &last.arguments else {
-        return None;
-    };
-    if args.args.len() != 1 {
-        return None;
-    }
-    args.args.iter().find_map(|a| match a {
-        syn::GenericArgument::Type(t) => Some(t),
-        _ => None,
-    })
-}
-
-/// Like [`extract_constant_inner_ty`] but for sites that have already been
-/// gated by `#[constant]`'s type-path validation, so extraction failure is
-/// a compiler-internal invariant violation, not a user error.
-fn constant_inner_ty(ty: &Type) -> &Type {
-    extract_constant_inner_ty(ty).unwrap_or_else(|| {
-        panic!(
-            "#[cuda_module] collected a #[constant] static whose type is not ConstantMemory<T>; \
-             this should have been rejected by the #[constant] attribute"
-        )
-    })
-}
-
-fn generate_cuda_module_constant_field(constant: &CudaModuleConstant) -> TokenStream2 {
-    let CudaModuleConstant {
-        ident, cfg_attrs, ..
-    } = constant;
-    let field = cuda_module_constant_field_ident(ident);
-    quote! {
-        #(#cfg_attrs)*
-        #field: ::std::sync::Arc<::std::sync::Mutex<::core::option::Option<::cuda_core::ConstantHandle>>>,
-    }
-}
-
-fn generate_cuda_module_constant_initializer(constant: &CudaModuleConstant) -> TokenStream2 {
-    let CudaModuleConstant {
-        ident, cfg_attrs, ..
-    } = constant;
-    let field = cuda_module_constant_field_ident(ident);
-    quote! {
-        #(#cfg_attrs)*
-        #field: ::std::sync::Arc::new(::std::sync::Mutex::new(::core::option::Option::None)),
-    }
-}
-
-fn generate_cuda_module_constant_resolver_method(constant: &CudaModuleConstant) -> TokenStream2 {
-    let CudaModuleConstant {
-        ident,
-        ty,
-        cfg_attrs,
-        symbol,
-        ..
-    } = constant;
-    let field = cuda_module_constant_field_ident(ident);
-    let resolver = cuda_module_constant_resolver_ident(ident);
-    let symbol_lit = LitStr::new(symbol, ident.span());
-    let inner_ty = constant_inner_ty(ty);
-    let mismatch_msg = format!(
-        "host/device size mismatch for #[constant] static `{ident}`: \
-         device size {{}} bytes, host expected {{}} bytes (PTX symbol `{symbol}`)"
-    );
-    quote! {
-        #(#cfg_attrs)*
-        #[allow(non_snake_case)]
-        fn #resolver(&self) -> ::core::result::Result<::cuda_core::ConstantHandle, ::cuda_core::DriverError> {
-            let mut slot = self
-                .#field
-                .lock()
-                .expect("cuda constant handle cache mutex poisoned");
-            if let ::core::option::Option::Some(handle) = *slot {
-                return ::core::result::Result::Ok(handle);
-            }
-
-            let (dptr, size) = self.__module.get_global(#symbol_lit)?;
-            assert_eq!(
-                size,
-                ::core::mem::size_of::<#inner_ty>(),
-                #mismatch_msg,
-                size,
-                ::core::mem::size_of::<#inner_ty>(),
-            );
-            // SAFETY: `dptr` was just resolved by `cuModuleGetGlobal` for a
-            // module that the LoadedModule keeps alive, and the size matches
-            // `size_of::<#inner_ty>()` (asserted above).
-            let handle = unsafe { ::cuda_core::ConstantHandle::from_raw(dptr) };
-            *slot = ::core::option::Option::Some(handle);
-            ::core::result::Result::Ok(handle)
-        }
-    }
-}
-
-/// Generate stream-ordered `set_<name>` and one-shot `set_<name>_blocking`
-/// methods on `LoadedModule`. The async setter stages owned host bytes so
-/// temporaries remain valid until CUDA reaches the stream callback.
-fn generate_cuda_module_set_constant_method(constant: &CudaModuleConstant) -> TokenStream2 {
-    let CudaModuleConstant {
-        ident,
-        ty,
-        cfg_attrs,
-        method_attrs,
-        ..
-    } = constant;
-    let method_suffix = ident.to_string().to_ascii_lowercase();
-    let method_name = format_ident!("set_{}", method_suffix);
-    let blocking_name = format_ident!("set_{}_blocking", method_suffix);
-    let resolver = cuda_module_constant_resolver_ident(ident);
-    let inner_ty = constant_inner_ty(ty);
-
-    quote! {
-        #(#cfg_attrs)*
-        #(#method_attrs)*
-        #[allow(non_snake_case)]
-        pub fn #method_name(
-            &self,
-            stream: &::cuda_core::CudaStream,
-            value: &#inner_ty,
-        ) -> ::core::result::Result<(), ::cuda_core::DriverError> {
-            let handle = self.#resolver()?;
-            let num_bytes = ::core::mem::size_of::<#inner_ty>();
-            let mut bytes = ::std::boxed::Box::<[u8]>::new_uninit_slice(num_bytes);
-            unsafe {
-                ::core::ptr::copy_nonoverlapping(
-                    value as *const #inner_ty as *const u8,
-                    bytes.as_mut_ptr() as *mut u8,
-                    num_bytes,
-                );
-            }
-            handle.write_async_staged(stream, bytes)
-        }
-
-        #(#cfg_attrs)*
-        #(#method_attrs)*
-        #[allow(non_snake_case)]
-        pub fn #blocking_name(
-            &self,
-            value: &#inner_ty,
-        ) -> ::core::result::Result<(), ::cuda_core::DriverError> {
-            let handle = self.#resolver()?;
-            // SAFETY: handle was size-checked against `#inner_ty` by the lazy
-            // resolver; `value` is a valid host pointer for
-            // `size_of::<#inner_ty>()`.
-            unsafe {
-                handle.write_blocking(
-                    &self.__module,
-                    value as *const #inner_ty as *const u8,
-                    ::core::mem::size_of::<#inner_ty>(),
-                )
-            }
-        }
-    }
-}
-
-fn cuda_module_method_attrs(attrs: &[syn::Attribute]) -> Vec<syn::Attribute> {
-    attrs
-        .iter()
-        .filter(|attr| attr_path_ends_with(attr, "doc"))
-        .cloned()
-        .collect()
-}
-
-/// Copy only the part of `cfg` / `cfg_attr` that controls whether an item
-/// exists. A kernel may use `cfg_attr` for function-only attributes such as
-/// `inline`; copying those onto generated fields or statements would be
-/// invalid. The nested `cfg` / `cfg_attr` availability semantics are retained;
-/// unrelated conditional attributes are omitted from generated items.
-fn cuda_module_cfg_attrs(attrs: &[syn::Attribute]) -> syn::Result<Vec<syn::Attribute>> {
-    let mut filtered = Vec::new();
-    for attr in attrs {
-        if attr_path_ends_with(attr, "cfg") {
-            filtered.push(attr.clone());
-        } else if attr_path_ends_with(attr, "cfg_attr")
-            && let Some(attr) = filter_cuda_module_cfg_attr(attr)?
-        {
-            filtered.push(attr);
-        }
-    }
-    Ok(filtered)
-}
-
-fn filter_cuda_module_cfg_attr(attr: &syn::Attribute) -> syn::Result<Option<syn::Attribute>> {
-    let syn::Meta::List(list) = &attr.meta else {
-        return Err(syn::Error::new_spanned(attr, "cfg_attr requires arguments"));
-    };
-    let parser = Punctuated::<syn::Meta, Token![,]>::parse_terminated;
-    let mut args = syn::parse::Parser::parse2(parser, list.tokens.clone())?.into_iter();
-    let predicate = args
-        .next()
-        .ok_or_else(|| syn::Error::new_spanned(attr, "cfg_attr requires a predicate"))?;
-    let mut nested = Vec::new();
-    for meta in args {
-        if let Some(meta) = filter_cuda_module_cfg_meta(meta)? {
-            nested.push(meta);
-        }
-    }
-    if nested.is_empty() {
-        Ok(None)
-    } else {
-        Ok(Some(parse_quote!(#[cfg_attr(#predicate, #(#nested),*)])))
-    }
-}
-
-fn filter_cuda_module_cfg_meta(meta: syn::Meta) -> syn::Result<Option<syn::Meta>> {
-    if meta
-        .path()
-        .segments
-        .last()
-        .is_some_and(|segment| segment.ident == "cfg")
-    {
-        return Ok(Some(meta));
-    }
-    if meta
-        .path()
-        .segments
-        .last()
-        .is_none_or(|segment| segment.ident != "cfg_attr")
-    {
-        return Ok(None);
-    }
-    filter_cuda_module_nested_cfg_attr(meta)
-}
-
-fn filter_cuda_module_nested_cfg_attr(meta: syn::Meta) -> syn::Result<Option<syn::Meta>> {
-    let syn::Meta::List(list) = &meta else {
-        return Err(syn::Error::new_spanned(meta, "cfg_attr requires arguments"));
-    };
-    let parser = Punctuated::<syn::Meta, Token![,]>::parse_terminated;
-    let mut args = syn::parse::Parser::parse2(parser, list.tokens.clone())?.into_iter();
-    let predicate = args
-        .next()
-        .ok_or_else(|| syn::Error::new_spanned(&meta, "cfg_attr requires a predicate"))?;
-    let mut nested = Vec::new();
-    for meta in args {
-        if let Some(meta) = filter_cuda_module_cfg_meta(meta)? {
-            nested.push(meta);
-        }
-    }
-    if nested.is_empty() {
-        Ok(None)
-    } else {
-        Ok(Some(parse_quote!(cfg_attr(#predicate, #(#nested),*))))
-    }
-}
-
-fn has_attr_named(attrs: &[syn::Attribute], name: &str) -> bool {
-    attrs.iter().any(|attr| attr_path_ends_with(attr, name))
-}
-
-fn attr_path_ends_with(attr: &syn::Attribute, name: &str) -> bool {
-    attr.path()
-        .segments
-        .last()
-        .map(|segment| segment.ident == name)
-        .unwrap_or(false)
-}
-
-fn cuda_module_cluster_dim(attrs: &[syn::Attribute]) -> syn::Result<Option<(u32, u32, u32)>> {
-    for attr in attrs {
-        if attr_path_ends_with(attr, "cluster_launch") {
-            let args = attr.parse_args::<ClusterArgs>()?;
-            return Ok(Some((args.x, args.y, args.z)));
-        }
-    }
-    Ok(None)
-}
-
-fn cuda_module_cooperative(attrs: &[syn::Attribute]) -> syn::Result<bool> {
-    for attr in attrs {
-        if attr_path_ends_with(attr, "cooperative_launch") {
-            if !matches!(attr.meta, syn::Meta::Path(_)) {
-                return Err(syn::Error::new_spanned(
-                    attr,
-                    "cooperative_launch takes no arguments: use a bare #[cooperative_launch]",
-                ));
-            }
-            return Ok(true);
-        }
-    }
-    Ok(false)
-}
-
-fn cuda_module_launch_contract(
-    attrs: &[syn::Attribute],
-    _fn_name: &Ident,
-    params: &[CudaModuleParam],
-    cluster_dim: Option<(u32, u32, u32)>,
-) -> syn::Result<Option<CudaModuleLaunchContract>> {
-    let contract_attrs: Vec<_> = attrs
-        .iter()
-        .filter(|attr| attr_path_ends_with(attr, "launch_contract"))
-        .collect();
-    if contract_attrs.len() > 1 {
-        return Err(syn::Error::new_spanned(
-            contract_attrs[1],
-            "a kernel may have only one launch_contract",
-        ));
-    }
-    let Some(attr) = contract_attrs.first() else {
-        return Ok(None);
-    };
-    let args = attr.parse_args::<LaunchContractArgs>()?;
-
-    if let Some(param) = params.iter().find(|param| param.mutable_slice) {
-        return Err(syn::Error::new(
-            param.name.span(),
-            "contracted kernels cannot take `&mut [T]`; use `DisjointSlice<T, IndexSpace>` so the launch domain and per-thread write ownership are explicit",
-        ));
-    }
-    if let Some(block) = args.exact_block {
-        validate_dimensions_for_domain(block, args.domain, "block", attr.span())?;
-    }
-    if let Some(cluster) = cluster_dim {
-        validate_dimensions_for_domain(cluster, args.domain, "cluster", attr.span())?;
-    }
-
-    let launch_bounds = cuda_module_launch_bounds(attrs)?;
-    if args.exact_block.is_none() && launch_bounds.is_none() {
-        return Err(syn::Error::new_spanned(
-            attr,
-            "launch_contract requires either an exact `block = (x, y, z)` or #[launch_bounds(max_threads)]",
-        ));
-    }
-    let max_block_threads = launch_bounds.map(|bounds| bounds.max_threads);
-    if let (Some(exact), Some(maximum)) = (
-        args.exact_block,
-        max_block_threads
-            .as_ref()
-            .and_then(|maximum| maximum.literal_value),
-    ) {
-        let exact_threads = u64::from(exact.0)
-            .checked_mul(u64::from(exact.1))
-            .and_then(|xy| xy.checked_mul(u64::from(exact.2)))
-            .ok_or_else(|| {
-                syn::Error::new_spanned(attr, "launch_contract block thread count overflows u64")
-            })?;
-        if exact_threads > u64::from(maximum) {
-            return Err(syn::Error::new_spanned(
-                attr,
-                format!(
-                    "launch_contract block {exact:?} has {exact_threads} threads, exceeding #[launch_bounds({maximum})]"
-                ),
-            ));
-        }
-    }
-
-    let min_compute_capability = match cluster_dim {
-        Some(_) if args.min_compute_capability < (9, 0) => (9, 0),
-        _ => args.min_compute_capability,
-    };
-
-    validate_requires_relations(&args.requires, params)?;
-
-    Ok(Some(CudaModuleLaunchContract {
-        domain: args.domain,
-        u32_coordinates: args.u32_coordinates,
-        exact_block: args.exact_block,
-        max_block_threads,
-        dynamic_shared: args.dynamic_shared,
-        dynamic_shared_alignment: args.dynamic_shared_alignment,
-        min_compute_capability,
-        requires: args.requires,
-    }))
-}
-
-/// One-line reminder of the accepted `requires` grammar, appended to every
-/// rejection so authors see what is allowed and which parameters exist.
-fn requires_grammar_help(params: &[CudaModuleParam]) -> String {
-    let mut names = Vec::new();
-    for param in params {
-        let name = &param.name;
-        match param.marshal {
-            // Only scalars that can actually appear in a relation are
-            // offered; signed and non-integer scalars would be rejected.
-            CudaModuleParamMarshal::Scalar => {
-                if param.scalar_int == ScalarIntClass::Unsigned {
-                    names.push(format!("`{name}`"));
-                }
-            }
-            CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. }
-            | CudaModuleParamMarshal::WritableDeviceBuffer { .. }
-            | CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
-                names.push(format!("`{name}.len()`"));
-            }
-        }
-    }
-    let available = if names.is_empty() {
-        "(none of this kernel's parameters can appear in requires)".to_string()
-    } else {
-        names.join(", ")
-    };
-    format!(
-        "each requires relation is one comparison (`>=`, `>`, `<=`, `<`, `==`, `!=`) between \
-         expressions built from slice parameters as `<param>.len()`, unsigned integer scalar \
-         parameters (u8/u16/u32/u64/usize), integer literals, parentheses, and `+`, `-`, `*`; \
-         available operands: {available}"
-    )
-}
-
-/// Validates every `requires` relation against the kernel's own parameter
-/// list at expansion time, so a malformed relation is a compile error at the
-/// attribute instead of a surprise at launch.
-fn validate_requires_relations(relations: &[Expr], params: &[CudaModuleParam]) -> syn::Result<()> {
-    for relation in relations {
-        let Expr::Binary(binary) = relation else {
-            return Err(syn::Error::new_spanned(
-                relation,
-                format!(
-                    "requires relation must be a comparison between two expressions; {}",
-                    requires_grammar_help(params)
-                ),
-            ));
-        };
-        if !requires_comparison_op(&binary.op) {
-            return Err(syn::Error::new_spanned(
-                relation,
-                format!(
-                    "requires relation must compare with `>=`, `>`, `<=`, `<`, `==`, or `!=`; {}",
-                    requires_grammar_help(params)
-                ),
-            ));
-        }
-        validate_requires_operand(&binary.left, params)?;
-        validate_requires_operand(&binary.right, params)?;
-    }
-    Ok(())
-}
-
-fn requires_comparison_op(op: &syn::BinOp) -> bool {
-    matches!(
-        op,
-        syn::BinOp::Ge(_)
-            | syn::BinOp::Gt(_)
-            | syn::BinOp::Le(_)
-            | syn::BinOp::Lt(_)
-            | syn::BinOp::Eq(_)
-            | syn::BinOp::Ne(_)
-    )
-}
-
-fn requires_arithmetic_op(op: &syn::BinOp) -> bool {
-    matches!(
-        op,
-        syn::BinOp::Add(_) | syn::BinOp::Sub(_) | syn::BinOp::Mul(_)
-    )
-}
-
-/// Validates one side of a `requires` comparison: an arithmetic expression
-/// over `.len()` of slice-like parameters, unsigned integer scalar
-/// parameters, and integer literals.
-fn validate_requires_operand(expr: &Expr, params: &[CudaModuleParam]) -> syn::Result<()> {
-    match expr {
-        Expr::Lit(literal) => match &literal.lit {
-            syn::Lit::Int(int) => {
-                int.base10_parse::<u64>().map_err(|_| {
-                    syn::Error::new_spanned(literal, "integer literal in requires must fit in u64")
-                })?;
-                Ok(())
-            }
-            _ => Err(syn::Error::new_spanned(
-                literal,
-                format!(
-                    "only integer literals are allowed in requires; {}",
-                    requires_grammar_help(params)
-                ),
-            )),
-        },
-        Expr::Path(path) => {
-            let Some(ident) = path.path.get_ident() else {
-                return Err(syn::Error::new_spanned(
-                    path,
-                    format!(
-                        "paths in requires must be bare kernel parameter names; {}",
-                        requires_grammar_help(params)
-                    ),
-                ));
-            };
-            let Some(param) = params.iter().find(|param| param.name == *ident) else {
-                return Err(syn::Error::new_spanned(
-                    path,
-                    format!(
-                        "unknown identifier `{ident}` in requires: relations may only reference \
-                         this kernel's parameters; {}",
-                        requires_grammar_help(params)
-                    ),
-                ));
-            };
-            match param.marshal {
-                CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. }
-                | CudaModuleParamMarshal::WritableDeviceBuffer { .. }
-                | CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
-                    Err(syn::Error::new_spanned(
-                        path,
-                        format!(
-                            "slice parameter `{ident}` may only appear in requires as \
-                             `{ident}.len()`; {}",
-                            requires_grammar_help(params)
-                        ),
-                    ))
-                }
-                CudaModuleParamMarshal::Scalar => match param.scalar_int {
-                    ScalarIntClass::Unsigned => Ok(()),
-                    ScalarIntClass::Signed => Err(syn::Error::new_spanned(
-                        path,
-                        format!(
-                            "signed integer parameter `{ident}` is not supported in requires: \
-                             relations are evaluated in u64 and signed widening semantics are \
-                             not defined for v1; {}",
-                            requires_grammar_help(params)
-                        ),
-                    )),
-                    ScalarIntClass::Other => Err(syn::Error::new_spanned(
-                        path,
-                        format!(
-                            "parameter `{ident}` is not an unsigned integer scalar, so it \
-                             cannot appear in requires; {}",
-                            requires_grammar_help(params)
-                        ),
-                    )),
-                },
-            }
-        }
-        Expr::MethodCall(call) => {
-            if call.method != "len" {
-                return Err(syn::Error::new_spanned(
-                    &call.method,
-                    format!(
-                        "only the `.len()` method is allowed in requires; {}",
-                        requires_grammar_help(params)
-                    ),
-                ));
-            }
-            if !call.args.is_empty() || call.turbofish.is_some() {
-                return Err(syn::Error::new_spanned(
-                    call,
-                    "`.len()` in requires takes no arguments or turbofish",
-                ));
-            }
-            let receiver_ident = match &*call.receiver {
-                Expr::Path(path) => path.path.get_ident(),
-                _ => None,
-            };
-            let Some(ident) = receiver_ident else {
-                return Err(syn::Error::new_spanned(
-                    &call.receiver,
-                    format!(
-                        "`.len()` in requires must be called directly on a slice parameter; {}",
-                        requires_grammar_help(params)
-                    ),
-                ));
-            };
-            let Some(param) = params.iter().find(|param| param.name == *ident) else {
-                return Err(syn::Error::new_spanned(
-                    &call.receiver,
-                    format!(
-                        "unknown identifier `{ident}` in requires: relations may only reference \
-                         this kernel's parameters; {}",
-                        requires_grammar_help(params)
-                    ),
-                ));
-            };
-            match param.marshal {
-                CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. }
-                | CudaModuleParamMarshal::WritableDeviceBuffer { .. }
-                | CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => Ok(()),
-                CudaModuleParamMarshal::Scalar => Err(syn::Error::new_spanned(
-                    call,
-                    format!(
-                        "`.len()` in requires is only available on slice or DisjointSlice \
-                         parameters; `{ident}` is a scalar; {}",
-                        requires_grammar_help(params)
-                    ),
-                )),
-            }
-        }
-        Expr::Paren(paren) => validate_requires_operand(&paren.expr, params),
-        Expr::Group(group) => validate_requires_operand(&group.expr, params),
-        Expr::Binary(binary) if requires_arithmetic_op(&binary.op) => {
-            validate_requires_operand(&binary.left, params)?;
-            validate_requires_operand(&binary.right, params)
-        }
-        Expr::Binary(binary) if requires_comparison_op(&binary.op) => Err(syn::Error::new_spanned(
-            binary,
-            "nested comparisons are not supported in requires: each relation is exactly one \
-                 comparison; split it into multiple comma-separated relations instead",
-        )),
-        Expr::Binary(binary) => {
-            let op = &binary.op;
-            Err(syn::Error::new_spanned(
-                binary,
-                format!(
-                    "operator `{}` is not supported in requires; {}",
-                    quote! { #op },
-                    requires_grammar_help(params)
-                ),
-            ))
-        }
-        other => Err(syn::Error::new_spanned(
-            other,
-            format!(
-                "unsupported expression in requires; {}",
-                requires_grammar_help(params)
-            ),
-        )),
-    }
-}
-
-/// How a generated `requires` check reads the length of a slice-like
-/// parameter. Each checked launcher flavor sees slice arguments as a
-/// different host type.
-#[derive(Clone, Copy)]
-enum RequiresLenAccess {
-    /// Sync prepared launcher: slice parameters are `&DeviceBuffer<T>` or
-    /// `&mut DeviceBuffer<T>`, so `.len()` resolves to the inherent method.
-    SyncBuffer,
-    /// Async prepared launcher: slice parameters are `&impl KernelSliceArg`
-    /// or `&mut impl KernelSliceArgMut`.
-    AsyncRef,
-    /// Owned async launcher: slice parameters are owned
-    /// `R: KernelSliceArg(Mut)` resources.
-    OwnedValue,
-}
-
-/// Renders a validated `requires` relation back to compact source text for
-/// error messages, e.g. `a.len() >= m * k`.
-fn render_requires_expr(expr: &Expr) -> String {
-    match expr {
-        Expr::Lit(literal) => {
-            let lit = &literal.lit;
-            quote!(#lit).to_string()
-        }
-        Expr::Path(path) => match path.path.get_ident() {
-            Some(ident) => ident.to_string(),
-            None => quote!(#path).to_string(),
-        },
-        Expr::MethodCall(call) => format!("{}.len()", render_requires_expr(&call.receiver)),
-        Expr::Paren(paren) => format!("({})", render_requires_expr(&paren.expr)),
-        Expr::Group(group) => render_requires_expr(&group.expr),
-        Expr::Binary(binary) => {
-            let op = &binary.op;
-            format!(
-                "{} {} {}",
-                render_requires_expr(&binary.left),
-                quote!(#op),
-                render_requires_expr(&binary.right)
-            )
-        }
-        other => quote!(#other).to_string(),
-    }
-}
-
-/// Generates the host-side size checks for a contracted kernel, or
-/// `None` when the contract declares no `requires` relations.
-///
-/// Every operand is widened to `u64` and every `+`/`-`/`*` goes through the
-/// corresponding checked operation, so a relation whose arithmetic leaves the
-/// `u64` range fails with `LaunchContractError::SizeRequirementOverflow` instead of wrapping. A
-/// relation that evaluates to false fails with `LaunchContractError::SizeRequirementViolated`
-/// carrying the relation's source text and both evaluated sides.
-fn generate_requires_checks(
-    kernel: &CudaModuleKernel,
-    access: RequiresLenAccess,
-) -> Option<TokenStream2> {
-    let contract = kernel.launch_contract.as_ref()?;
-    if contract.requires.is_empty() {
-        return None;
-    }
-    let kernel_name = kernel.fn_name.to_string();
-    let lhs_binding = internal_ident("__cuda_oxide_requires_lhs");
-    let rhs_binding = internal_ident("__cuda_oxide_requires_rhs");
-    let checks = contract.requires.iter().map(|relation| {
-        let Expr::Binary(binary) = relation else {
-            unreachable!("requires relations are validated during contract construction");
-        };
-        let relation_text = render_requires_expr(relation);
-        let op = &binary.op;
-        let lhs = requires_operand_tokens(&binary.left, access, &kernel_name, &relation_text);
-        let rhs = requires_operand_tokens(&binary.right, access, &kernel_name, &relation_text);
-        quote! {
-            {
-                let #lhs_binding: u64 = #lhs;
-                let #rhs_binding: u64 = #rhs;
-                if !(#lhs_binding #op #rhs_binding) {
-                    return ::core::result::Result::Err(
-                        ::cuda_core::LaunchContractError::SizeRequirementViolated {
-                            kernel: #kernel_name,
-                            relation: #relation_text,
-                            lhs: #lhs_binding,
-                            rhs: #rhs_binding,
-                        },
-                    );
-                }
-            }
-        }
-    });
-    Some(quote! { #(#checks)* })
-}
-
-/// Transliterates one validated side of a `requires` comparison into a `u64`
-/// expression with checked arithmetic.
-fn requires_operand_tokens(
-    expr: &Expr,
-    access: RequiresLenAccess,
-    kernel_name: &str,
-    relation_text: &str,
-) -> TokenStream2 {
-    match expr {
-        Expr::Lit(literal) => {
-            let syn::Lit::Int(int) = &literal.lit else {
-                unreachable!("requires literals are validated during contract construction");
-            };
-            let value = int
-                .base10_parse::<u64>()
-                .expect("requires literals are validated during contract construction");
-            quote! { #value }
-        }
-        Expr::Path(path) => {
-            // Validated: a bare unsigned integer scalar parameter, so `as
-            // u64` is a lossless widening.
-            quote! { (#path as u64) }
-        }
-        Expr::MethodCall(call) => {
-            let receiver = &call.receiver;
-            match access {
-                RequiresLenAccess::SyncBuffer => quote! { (#receiver.len() as u64) },
-                RequiresLenAccess::AsyncRef => {
-                    quote! { (::cuda_host::KernelSliceArg::len(#receiver) as u64) }
-                }
-                RequiresLenAccess::OwnedValue => {
-                    quote! { (::cuda_host::KernelSliceArg::len(&#receiver) as u64) }
-                }
-            }
-        }
-        Expr::Paren(paren) => {
-            requires_operand_tokens(&paren.expr, access, kernel_name, relation_text)
-        }
-        Expr::Group(group) => {
-            requires_operand_tokens(&group.expr, access, kernel_name, relation_text)
-        }
-        Expr::Binary(binary) => {
-            let lhs = requires_operand_tokens(&binary.left, access, kernel_name, relation_text);
-            let rhs = requires_operand_tokens(&binary.right, access, kernel_name, relation_text);
-            let checked = match binary.op {
-                syn::BinOp::Add(_) => quote! { checked_add },
-                syn::BinOp::Sub(_) => quote! { checked_sub },
-                syn::BinOp::Mul(_) => quote! { checked_mul },
-                _ => unreachable!("requires operators are validated during contract construction"),
-            };
-            quote! {
-                #lhs.#checked(#rhs).ok_or(
-                    ::cuda_core::LaunchContractError::SizeRequirementOverflow {
-                        kernel: #kernel_name,
-                        relation: #relation_text,
-                    },
-                )?
-            }
-        }
-        _ => unreachable!("requires operands are validated during contract construction"),
-    }
-}
-
-#[derive(Clone)]
-struct ContractLaunchBounds {
-    max_threads: ConstU32Expr,
-}
-
-fn cuda_module_launch_bounds(
-    attrs: &[syn::Attribute],
-) -> syn::Result<Option<ContractLaunchBounds>> {
-    let matching: Vec<_> = attrs
-        .iter()
-        .filter(|attr| attr_path_ends_with(attr, "launch_bounds"))
-        .collect();
-    if matching.len() > 1 {
-        return Err(syn::Error::new_spanned(
-            matching[1],
-            "a kernel may have only one launch_bounds attribute",
-        ));
-    }
-    let Some(attr) = matching.first() else {
-        return Ok(None);
-    };
-    let args = attr.parse_args::<LaunchBoundsArgs>()?;
-    Ok(Some(ContractLaunchBounds {
-        max_threads: args.max_threads,
-    }))
-}
-
-fn validate_dimensions_for_domain(
-    dimensions: (u32, u32, u32),
-    domain: u8,
-    kind: &str,
-    span: proc_macro2::Span,
-) -> syn::Result<()> {
-    if dimensions.0 == 0 || dimensions.1 == 0 || dimensions.2 == 0 {
-        return Err(syn::Error::new(
-            span,
-            format!("launch_contract {kind} dimensions must be non-zero"),
-        ));
-    }
-    let outside_domain = match domain {
-        1 => dimensions.1 != 1 || dimensions.2 != 1,
-        2 => dimensions.2 != 1,
-        3 => false,
-        _ => unreachable!(),
-    };
-    if outside_domain {
-        return Err(syn::Error::new(
-            span,
-            format!(
-                "launch_contract {kind} dimensions {dimensions:?} exceed the declared {domain}D domain"
-            ),
-        ));
-    }
-    Ok(())
-}
-
-fn cuda_module_params(item_fn: &ItemFn) -> syn::Result<Vec<CudaModuleParam>> {
-    item_fn
-        .sig
-        .inputs
-        .iter()
-        .map(|arg| match arg {
-            FnArg::Receiver(receiver) => Err(syn::Error::new_spanned(
-                receiver,
-                "cuda_module kernels cannot take self parameters",
-            )),
-            FnArg::Typed(pat_type) => cuda_module_param_from_typed(pat_type),
-        })
-        .collect()
-}
-
-fn cuda_module_param_from_typed(pat_type: &syn::PatType) -> syn::Result<CudaModuleParam> {
-    let Pat::Ident(pat_ident) = &*pat_type.pat else {
-        return Err(syn::Error::new_spanned(
-            &pat_type.pat,
-            "cuda_module only supports simple identifier kernel parameters",
-        ));
-    };
-    let name = pat_ident.ident.clone();
-    let (sync_host_ty, async_host_ty, marshal) = cuda_module_host_type(&pat_type.ty)?;
-    let mutable_slice = cuda_module_slice_elem(&pat_type.ty).is_some_and(|(_, mutable)| mutable);
-    let disjoint_slice_elem = cuda_module_disjoint_slice_elem(&pat_type.ty);
-    let disjoint_slice_ty = disjoint_slice_elem
-        .as_ref()
-        .map(|_| pat_type.ty.as_ref().clone());
-    let uniform_scalar = cuda_module_uniform_scalar(&pat_type.ty);
-    let uniform_ty = uniform_scalar
-        .as_ref()
-        .map(|_| pat_type.ty.as_ref().clone());
-    Ok(CudaModuleParam {
-        name,
-        sync_host_ty,
-        async_host_ty,
-        marshal,
-        mutable_slice,
-        disjoint_slice_ty,
-        disjoint_slice_elem,
-        uniform_ty,
-        uniform_scalar,
-        scalar_int: scalar_int_class(&pat_type.ty),
-    })
-}
-
-fn cuda_module_host_type(
-    ty: &Type,
-) -> syn::Result<(TokenStream2, TokenStream2, CudaModuleParamMarshal)> {
-    let async_lifetime = cuda_module_async_lifetime();
-    if let Some((elem_ty, mutable)) = cuda_module_slice_elem(ty) {
-        let sync_host_ty = if mutable {
-            quote! { &mut ::cuda_core::DeviceBuffer<#elem_ty> }
-        } else {
-            quote! { &::cuda_core::DeviceBuffer<#elem_ty> }
-        };
-        let (async_host_ty, marshal) = if mutable {
-            (
-                quote! { &#async_lifetime mut impl ::cuda_host::KernelSliceArgMut<Elem = #elem_ty> },
-                CudaModuleParamMarshal::WritableDeviceBuffer {
-                    elem_ty: quote! { #elem_ty },
-                },
-            )
-        } else {
-            (
-                quote! { &#async_lifetime impl ::cuda_host::KernelSliceArg<Elem = #elem_ty> },
-                CudaModuleParamMarshal::ReadOnlyDeviceBuffer {
-                    elem_ty: quote! { #elem_ty },
-                },
-            )
-        };
-        return Ok((sync_host_ty, async_host_ty, marshal));
-    }
-
-    if let Some(elem_ty) = cuda_module_disjoint_slice_elem(ty) {
-        if cuda_module_disjoint_slice_has_row_width(ty) {
-            return Ok((
-                quote! { ::cuda_host::RowWidth<'_, #elem_ty> },
-                quote! { ::cuda_host::RowWidth<#async_lifetime, #elem_ty> },
-                CudaModuleParamMarshal::RowWidthDeviceBuffer {
-                    elem_ty: quote! { #elem_ty },
-                },
-            ));
-        }
-        return Ok((
-            quote! { &mut ::cuda_core::DeviceBuffer<#elem_ty> },
-            quote! { &#async_lifetime mut impl ::cuda_host::KernelSliceArgMut<Elem = #elem_ty> },
-            CudaModuleParamMarshal::WritableDeviceBuffer {
-                elem_ty: quote! { #elem_ty },
-            },
-        ));
-    }
-
-    // A `Uniform<T>` parameter is marshalled exactly like `T`. The host takes
-    // the bare scalar because the host is what makes the value uniform: one
-    // marshalled value reaches every thread of the launch.
-    if let Some(scalar) = cuda_module_uniform_scalar(ty) {
-        return Ok((
-            quote! { #scalar },
-            quote! { #scalar },
-            CudaModuleParamMarshal::Scalar,
-        ));
-    }
-
-    if matches!(ty, Type::Reference(_)) {
-        return Err(syn::Error::new_spanned(
-            ty,
-            "cuda_module only supports slice references; use &[T], &mut [T], DisjointSlice<T>, a raw pointer, or a by-value KernelScalar",
-        ));
-    }
-
-    Ok((
-        quote! { #ty },
-        quote! { #ty },
-        CudaModuleParamMarshal::Scalar,
-    ))
-}
-
-fn cuda_module_slice_elem(ty: &Type) -> Option<(TokenStream2, bool)> {
-    let Type::Reference(type_ref) = ty else {
-        return None;
-    };
-    let Type::Slice(slice) = &*type_ref.elem else {
-        return None;
-    };
-    let elem = &slice.elem;
-    Some((quote! { #elem }, type_ref.mutability.is_some()))
-}
-
-/// Scalar carried by a `Uniform<T>` kernel parameter, if the type is spelled
-/// that way.
-///
-/// The host method takes the bare `T`: the host is the source of the
-/// uniformity proof, since it marshals one value into the launch packet for
-/// the whole grid. `Uniform<T>` is `#[repr(transparent)]`, so the launch packet
-/// is byte-identical either way.
-fn cuda_module_uniform_scalar(ty: &Type) -> Option<TokenStream2> {
-    let Type::Path(type_path) = ty else {
-        return None;
-    };
-    let segment = type_path.path.segments.last()?;
-    if segment.ident != "Uniform" {
-        return None;
-    }
-    let PathArguments::AngleBracketed(args) = &segment.arguments else {
-        return None;
-    };
-    let scalar = args.args.iter().find_map(|arg| match arg {
-        GenericArgument::Type(ty) => Some(ty),
-        _ => None,
-    })?;
-    Some(quote! { #scalar })
-}
-
-/// True when a `DisjointSlice`'s index space carries a runtime row width.
-///
-/// Matched on the spelling of the index-space argument, exactly as the element
-/// type is. The spelling only selects the host ABI; `SpaceLayout` is what
-/// decides whether the device type really carries the width, and a mismatch
-/// between the two is a type error at the generated call rather than a silent
-/// packet-shape difference.
-fn cuda_module_disjoint_slice_has_row_width(ty: &Type) -> bool {
-    let Type::Path(type_path) = ty else {
-        return false;
-    };
-    let Some(segment) = type_path.path.segments.last() else {
-        return false;
-    };
-    if segment.ident != "DisjointSlice" {
-        return false;
-    }
-    let PathArguments::AngleBracketed(args) = &segment.arguments else {
-        return false;
-    };
-    let mut space = args.args.iter().filter_map(|arg| match arg {
-        GenericArgument::Type(ty) => Some(ty),
-        _ => None,
-    });
-    space.nth(1).is_some_and(|space| {
-        let Type::Path(space_path) = space else {
-            return false;
-        };
-        space_path.path.segments.last().is_some_and(|segment| {
-            segment.ident == "RuntimeRowMajorTiles" || segment.ident == "Runtime2DIndex"
-        })
-    })
-}
-
-fn cuda_module_disjoint_slice_elem(ty: &Type) -> Option<TokenStream2> {
-    let Type::Path(type_path) = ty else {
-        return None;
-    };
-    let segment = type_path.path.segments.last()?;
-    if segment.ident != "DisjointSlice" {
-        return None;
-    }
-    let PathArguments::AngleBracketed(args) = &segment.arguments else {
-        return None;
-    };
-    let type_args: Vec<_> = args
-        .args
-        .iter()
-        .filter_map(|arg| match arg {
-            GenericArgument::Type(ty) => Some(ty),
-            _ => None,
-        })
-        .collect();
-    let elem = *type_args.first()?;
-    Some(quote! { #elem })
-}
-
-/// Adds a semantic launch-domain proof for every writable device slice.
-///
-/// The macro only uses the outer `DisjointSlice` spelling to select the host
-/// ABI. The Rust compiler decides whether the *resolved, complete type* is a
-/// genuine cuda-device slice with a compatible index space. This makes type
-/// aliases work without letting a local look-alike bypass the contract.
-fn add_cuda_module_disjoint_contract_bounds(
-    generics: &mut syn::Generics,
-    params: &[CudaModuleParam],
-    domain: u8,
-) {
-    for param in params {
-        let (Some(device_ty), Some(element_ty)) =
-            (&param.disjoint_slice_ty, &param.disjoint_slice_elem)
-        else {
-            continue;
-        };
-        let (device_ty, bound_lifetime) = cuda_module_disjoint_bound_type(device_ty);
-        generics.make_where_clause().predicates.push(parse_quote! {
-            for<#bound_lifetime> #device_ty:
-                ::cuda_device::__LaunchContractDisjointSlice<#element_ty, #domain>
-        });
-    }
-}
-
-/// Requires every `DisjointSlice` parameter's resolved type to carry exactly
-/// the launch-packet shape the macro chose for it.
-///
-/// The macro picks the two-word `(ptr, len)` or three-word `(ptr, len, width)`
-/// host marshalling from the index space's spelling, which type aliases can
-/// defeat: `type Rt = RuntimeRowMajorTiles<1, 1>;` spells a flat slice over a
-/// runtime-width space, and the launch would then push two kernel parameters
-/// for a three-parameter kernel, making the driver read past the argument
-/// array. The sealed `__LaunchContractDisjointSliceAbi` trait is the semantic
-/// authority: only the genuine `DisjointSlice` whose index space really has
-/// (`true`) or really lacks (`false`) a runtime row width satisfies the bound, so
-/// a spelling/semantics mismatch is a compile error instead of a malformed
-/// launch packet.
-fn add_cuda_module_disjoint_abi_bounds(generics: &mut syn::Generics, params: &[CudaModuleParam]) {
-    for param in params {
-        let (Some(device_ty), Some(element_ty)) =
-            (&param.disjoint_slice_ty, &param.disjoint_slice_elem)
-        else {
-            continue;
-        };
-        let has_row_width = matches!(
-            param.marshal,
-            CudaModuleParamMarshal::RowWidthDeviceBuffer { .. }
-        );
-        let (device_ty, bound_lifetime) = cuda_module_disjoint_bound_type(device_ty);
-        generics.make_where_clause().predicates.push(parse_quote! {
-            for<#bound_lifetime> #device_ty:
-                ::cuda_device::__LaunchContractDisjointSliceAbi<#element_ty, #has_row_width>
-        });
-    }
-}
-
-/// Requires every `Uniform<T>` parameter to be cuda-device's own type.
-///
-/// The host ABI for these parameters is chosen from the spelling `Uniform<T>`,
-/// so without this bound a local type of the same name would be marshalled as
-/// a bare `T` while presenting whatever layout it liked.
-fn add_cuda_module_uniform_bounds(generics: &mut syn::Generics, params: &[CudaModuleParam]) {
-    for param in params {
-        let (Some(device_ty), Some(scalar_ty)) = (&param.uniform_ty, &param.uniform_scalar) else {
-            continue;
-        };
-        generics.make_where_clause().predicates.push(parse_quote! {
-            #device_ty: ::cuda_device::__LaunchContractUniform<#scalar_ty>
-        });
-    }
-}
-
-/// Makes the elided `DisjointSlice` lifetime explicit so the complete device
-/// type can appear in an impl-level where-clause.
-fn cuda_module_disjoint_bound_type(ty: &Type) -> (Type, syn::Lifetime) {
-    let mut ty = ty.clone();
-    let Type::Path(type_path) = &mut ty else {
-        unreachable!("only recognized DisjointSlice paths reach this helper");
-    };
-    let segment = type_path
-        .path
-        .segments
-        .last_mut()
-        .expect("recognized DisjointSlice path has a final segment");
-    let PathArguments::AngleBracketed(args) = &mut segment.arguments else {
-        unreachable!("recognized DisjointSlice path has generic arguments");
-    };
-    let bound_ident = internal_ident("__cuda_oxide_disjoint");
-    let bound_lifetime = syn::Lifetime::new(&format!("'{}", bound_ident), bound_ident.span());
-    if let Some(GenericArgument::Lifetime(lifetime)) = args.args.first_mut() {
-        *lifetime = bound_lifetime.clone();
-    } else {
-        let previous = core::mem::take(&mut args.args);
-        args.args
-            .push(GenericArgument::Lifetime(bound_lifetime.clone()));
-        args.args.extend(previous);
-    }
-    (ty, bound_lifetime)
-}
-
-fn cuda_module_kernel_marker_type(kernel: &CudaModuleKernel) -> TokenStream2 {
-    let marker = cuda_kernel_marker_name(&kernel.fn_name);
-    if !kernel.is_generic {
-        return quote! { #marker };
-    }
-    let marker_args = generic_arguments(&kernel.generics);
-    if marker_args.is_empty() {
-        quote! { #marker }
-    } else {
-        quote! { #marker<#(#marker_args),*> }
-    }
-}
-
-fn generate_cuda_module_launch_contract_impl(kernel: &CudaModuleKernel) -> Option<TokenStream2> {
-    let contract = kernel.launch_contract.as_ref()?;
-    let cfg_attrs = &kernel.cfg_attrs;
-    let marker_ty = cuda_module_kernel_marker_type(kernel);
-    // `#[kernel]` erases lifetime-only generic lists because lifetimes do not
-    // create codegen instances. Mirror the marker that `#[kernel]` actually
-    // emits instead of applying erased lifetimes to a non-generic marker.
-    let generics = if kernel.is_generic {
-        kernel.generics.clone()
-    } else {
-        syn::Generics::default()
-    };
-    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
-    let config_ty = match contract.domain {
-        1 => quote! { ::cuda_core::LaunchConfig1D },
-        2 => quote! { ::cuda_core::LaunchConfig2D },
-        3 => quote! { ::cuda_core::LaunchConfig3D },
-        _ => unreachable!(),
-    };
-    let max_threads_binding = internal_ident("__cuda_oxide_max_threads");
-    let block = if let Some((x, y, z)) = contract.exact_block {
-        quote! { ::cuda_core::BlockRequirement::Exact((#x, #y, #z)) }
-    } else {
-        contract
-            .max_block_threads
-            .as_ref()
-            .expect("validated contract without exact block has launch bounds");
-        quote! { ::cuda_core::BlockRequirement::MaxThreads(#max_threads_binding) }
-    };
-    let launch_bounds_assertions = contract.max_block_threads.as_ref().map(|maximum| {
-        let maximum = &maximum.expr;
-        let exact_assertion = contract.exact_block.map(|(x, y, z)| {
-            let exact_threads = u128::from(x) * u128::from(y) * u128::from(z);
-            quote! {
-                assert!(
-                    #exact_threads <= (#max_threads_binding) as u128,
-                    "launch_contract exact block exceeds launch_bounds maximum threads",
-                );
-            }
-        });
-        quote! {
-            let #max_threads_binding: u32 = #maximum;
-            assert!(
-                #max_threads_binding > 0,
-                "launch_bounds maximum threads must be greater than zero",
-            );
-            #exact_assertion
-        }
-    });
-    let alignment = contract.dynamic_shared_alignment;
-    let dynamic_shared = match contract.dynamic_shared {
-        DynamicSharedContract::Exact(bytes) => quote! {
-            ::cuda_core::DynamicSharedMemoryRequirement::Exact {
-                bytes: #bytes,
-                min_alignment: #alignment,
-            }
-        },
-        DynamicSharedContract::Range {
-            min_bytes,
-            max_bytes,
-        } => quote! {
-            ::cuda_core::DynamicSharedMemoryRequirement::Range {
-                min_bytes: #min_bytes,
-                max_bytes: #max_bytes,
-                min_alignment: #alignment,
-            }
-        },
-    };
-    let kernel_name = kernel.fn_name.to_string();
-    let cluster = contract.cluster_tokens(kernel.cluster_dim);
-    let cooperative = kernel.cooperative.then(|| quote! { .with_cooperative() });
-    let (major, minor) = contract.min_compute_capability;
-    let compute_capability = ((major, minor) != (0, 0)).then(|| {
-        quote! { .with_min_compute_capability(#major, #minor) }
-    });
-    let coordinates = contract
-        .u32_coordinates
-        .then(|| quote! { .with_u32_coordinates() });
-
-    Some(quote! {
-        #(#cfg_attrs)*
-        impl #impl_generics ::cuda_core::KernelLaunchContract for #marker_ty
-        #where_clause
-        {
-            type Config = #config_ty;
-            const SPEC: ::cuda_core::LaunchContractSpec = {
-                #launch_bounds_assertions
-                ::cuda_core::LaunchContractSpec::new(#kernel_name, #block, #dynamic_shared)
-                    #cluster
-                    #cooperative
-                    #compute_capability
-                    #coordinates
-            };
-        }
-    })
-}
-
-impl CudaModuleLaunchContract {
-    fn cluster_tokens(&self, cluster_dim: Option<(u32, u32, u32)>) -> Option<TokenStream2> {
-        cluster_dim.map(|(x, y, z)| quote! { .with_cluster((#x, #y, #z)) })
-    }
-}
-
-fn generate_cuda_module_prepare_launch_methods(kernel: &CudaModuleKernel) -> Option<TokenStream2> {
-    kernel.launch_contract.as_ref()?;
-    let vis = &kernel.vis;
-    let cfg_attrs = &kernel.cfg_attrs;
-    let fn_name = &kernel.fn_name;
-    let prepare_name = format_ident!("prepare_{}", fn_name);
-    let prepare_for_name = format_ident!("prepare_{}_for", fn_name);
-    let marker_ty = cuda_module_kernel_marker_type(kernel);
-    let generics = kernel.generics.clone();
-    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
-    let function_binding = cuda_module_function_binding(kernel);
-    let function = internal_ident("__cuda_oxide_function");
-    let config = internal_ident("__cuda_oxide_config");
-    let codegen_args = codegen_generic_arguments(&kernel.generics);
-    let turbofish = if codegen_args.is_empty() {
-        quote! {}
-    } else {
-        quote! { ::<#(#codegen_args),*> }
-    };
-    let type_params: Vec<_> = kernel
-        .generics
-        .params
-        .iter()
-        .filter_map(|param| match param {
-            GenericParam::Type(type_param) => Some(&type_param.ident),
-            GenericParam::Lifetime(_) | GenericParam::Const(_) => None,
-        })
-        .collect();
-    let witness_params = type_params.iter().enumerate().map(|(index, ty)| {
-        let name = internal_ident(&format!("__cuda_oxide_type_witness_{index}"));
-        quote! { #name: &#ty }
-    });
-    let prepare_for = (!type_params.is_empty()).then(|| {
-        quote! {
-            #(#cfg_attrs)*
-            #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-            #vis fn #prepare_for_name #impl_generics (
-                &self,
-                #(#witness_params,)*
-                #config: <#marker_ty as ::cuda_core::KernelLaunchContract>::Config,
-            ) -> ::core::result::Result<
-                ::cuda_core::PreparedLaunch<#marker_ty>,
-                ::cuda_core::LaunchContractError,
-            >
-            #where_clause
-            {
-                self.#prepare_name #turbofish (#config)
-            }
-        }
-    });
-
-    Some(quote! {
-        #(#cfg_attrs)*
-        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-        #vis fn #prepare_name #impl_generics (
-            &self,
-            #config: <#marker_ty as ::cuda_core::KernelLaunchContract>::Config,
-        ) -> ::core::result::Result<
-            ::cuda_core::PreparedLaunch<#marker_ty>,
-            ::cuda_core::LaunchContractError,
-        >
-        #where_clause
-        {
-            #function_binding
-            unsafe {
-                ::cuda_core::PreparedLaunch::<#marker_ty>::__prepare(
-                    #function.clone(),
-                    #config,
-                )
-            }
-        }
-
-        #prepare_for
-    })
-}
-
-fn generate_cuda_module_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
-    if kernel.launch_contract.is_some() {
-        generate_cuda_module_prepared_launch_method(kernel)
-    } else {
-        generate_cuda_module_legacy_launch_method(kernel)
-    }
-}
-
-fn generate_cuda_module_legacy_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
-    let vis = &kernel.vis;
-    let cfg_attrs = &kernel.cfg_attrs;
-    let method_attrs = &kernel.method_attrs;
-    let fn_name = &kernel.fn_name;
-    let generics = cuda_module_launch_generics(kernel);
-    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
-    let params = kernel.params.iter().map(|param| {
-        let name = &param.name;
-        let host_ty = &param.sync_host_ty;
-        quote! { #name: #host_ty }
-    });
-    let arg_marshalling = kernel
-        .params
-        .iter()
-        .enumerate()
-        .map(|(index, param)| cuda_module_arg_marshalling(index, param));
-    let function_binding = cuda_module_function_binding(kernel);
-    let launch_call = cuda_module_launch_call(kernel);
-    let stream = internal_ident("__cuda_oxide_stream");
-    let config = internal_ident("__cuda_oxide_config");
-    let args = internal_ident("__cuda_oxide_args");
-
-    quote! {
-        #(#cfg_attrs)*
-        #(#method_attrs)*
-        #[doc = "Launches this kernel with an unverified raw launch configuration."]
-        #[doc = ""]
-        #[doc = "# Safety"]
-        #[doc = "The launch dimensions and resources must satisfy every indexing, memory-access, launch-bounds, and dynamic-shared-memory assumption made by the kernel. Dimensions not represented by the kernel's index model must not introduce overlapping or out-of-bounds accesses. The caller must also uphold any safety requirements documented on the kernel itself."]
-        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-        #vis unsafe fn #fn_name #impl_generics (
-            &self,
-            #stream: &::cuda_core::CudaStream,
-            #config: ::cuda_core::LaunchConfig,
-            #(#params),*
-        ) -> ::core::result::Result<(), ::cuda_core::DriverError>
-        #where_clause
-        {
-            #function_binding
-            let mut #args: ::std::vec::Vec<*mut ::std::ffi::c_void> = ::std::vec::Vec::new();
-            #(#arg_marshalling)*
-            #launch_call
-        }
-    }
-}
-
-fn generate_cuda_module_prepared_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
-    let vis = &kernel.vis;
-    let cfg_attrs = &kernel.cfg_attrs;
-    let method_attrs = &kernel.method_attrs;
-    let unsafety = &kernel.unsafety;
-    let fn_name = &kernel.fn_name;
-    let unchecked_name = format_ident!("{}_unchecked", fn_name);
-    let marker_ty = cuda_module_kernel_marker_type(kernel);
-    let generics = cuda_module_launch_generics(kernel);
-    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
-    let params: Vec<_> = kernel
-        .params
-        .iter()
-        .map(|param| {
-            let name = &param.name;
-            let host_ty = &param.sync_host_ty;
-            quote! { #name: #host_ty }
-        })
-        .collect();
-    let prepared_arg_marshalling = kernel
-        .params
-        .iter()
-        .enumerate()
-        .map(|(index, param)| cuda_module_arg_marshalling(index, param));
-    let unchecked_arg_marshalling = kernel
-        .params
-        .iter()
-        .enumerate()
-        .map(|(index, param)| cuda_module_arg_marshalling(index, param));
-    let unchecked_function_binding = cuda_module_function_binding(kernel);
-    let launch_call = cuda_module_launch_call(kernel);
-    let unchecked_launch_call = cuda_module_launch_call(kernel);
-    let requires_checks = generate_requires_checks(kernel, RequiresLenAccess::SyncBuffer);
-    let stream = internal_ident("__cuda_oxide_stream");
-    let prepared = internal_ident("__cuda_oxide_prepared");
-    let function = internal_ident("__cuda_oxide_function");
-    let config = internal_ident("__cuda_oxide_config");
-    let args = internal_ident("__cuda_oxide_args");
-
-    quote! {
-        #(#cfg_attrs)*
-        #(#method_attrs)*
-        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-        #vis #unsafety fn #fn_name #impl_generics (
-            &self,
-            #stream: &::cuda_core::CudaStream,
-            #prepared: &::cuda_core::PreparedLaunch<#marker_ty>,
-            #(#params),*
-        ) -> ::core::result::Result<(), ::cuda_core::LaunchContractError>
-        #where_clause
-        {
-            #prepared.validate_stream(#stream)?;
-            #requires_checks
-            let #function = #prepared.function();
-            let #config = #prepared.__raw_config();
-            let mut #args: ::std::vec::Vec<*mut ::std::ffi::c_void> = ::std::vec::Vec::new();
-            #(#prepared_arg_marshalling)*
-            (#launch_call).map_err(::cuda_core::LaunchContractError::from)
-        }
-
-        #(#cfg_attrs)*
-        #[doc = "Unchecked launch escape hatch for this contracted kernel."]
-        #[doc = ""]
-        #[doc = "# Safety"]
-        #[doc = "The caller must uphold the kernel's declared geometry, resource, capability, and context contract, including any `requires` size requirements. This escape hatch intentionally skips the contract's checks, so an undersized buffer is not caught before the kernel runs."]
-        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-        #vis unsafe fn #unchecked_name #impl_generics (
-            &self,
-            #stream: &::cuda_core::CudaStream,
-            #config: ::cuda_core::LaunchConfig,
-            #(#params),*
-        ) -> ::core::result::Result<(), ::cuda_core::DriverError>
-        #where_clause
-        {
-            #unchecked_function_binding
-            let mut #args: ::std::vec::Vec<*mut ::std::ffi::c_void> = ::std::vec::Vec::new();
-            #(#unchecked_arg_marshalling)*
-            #unchecked_launch_call
-        }
-    }
-}
-
-fn generate_cuda_module_async_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
-    if kernel.launch_contract.is_some() {
-        generate_cuda_module_prepared_async_launch_method(kernel)
-    } else {
-        generate_cuda_module_legacy_async_launch_method(kernel)
-    }
-}
-
-fn generate_cuda_module_legacy_async_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
-    let vis = &kernel.vis;
-    let cfg_attrs = &kernel.cfg_attrs;
-    let method_attrs = &kernel.method_attrs;
-    let fn_name = format_ident!("{}_async", kernel.fn_name);
-    let generics = cuda_module_async_launch_generics(kernel);
-    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
-    let params = kernel.params.iter().map(|param| {
-        let name = &param.name;
-        let host_ty = &param.async_host_ty;
-        quote! { #name: #host_ty }
-    });
-    let arg_marshalling = kernel.params.iter().map(cuda_module_async_arg_marshalling);
-    let function_binding = cuda_module_function_binding(kernel);
-    let config = internal_ident("__cuda_oxide_config");
-    let function = internal_ident("__cuda_oxide_function");
-    let launch = internal_ident("__cuda_oxide_launch");
-    let async_lifetime = cuda_module_async_lifetime();
-    let cluster_dim = kernel.cluster_dim.map(|(x, y, z)| quote! { (#x, #y, #z) });
-    let set_cluster_dim = cluster_dim.map(|cluster_dim| {
-        quote! {
-            ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim);
-        }
-    });
-    let set_cooperative = kernel.cooperative.then(|| {
-        quote! {
-            ::cuda_host::set_async_kernel_cooperative(&mut #launch, true);
-        }
-    });
-
-    quote! {
-        #(#cfg_attrs)*
-        #(#method_attrs)*
-        #[doc = "Builds a lazy async launch from an unverified raw launch configuration."]
-        #[doc = ""]
-        #[doc = "# Safety"]
-        #[doc = "Before scheduling the returned operation, the launch dimensions and resources must satisfy every indexing, memory-access, launch-bounds, and dynamic-shared-memory assumption made by the kernel. Dimensions not represented by the kernel's index model must not introduce overlapping or out-of-bounds accesses. The caller must also uphold any safety requirements documented on the kernel itself."]
-        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-        #vis unsafe fn #fn_name #impl_generics (
-            &self,
-            #config: ::cuda_core::LaunchConfig,
-            #(#params),*
-        ) -> ::core::result::Result<::cuda_host::AsyncKernelLaunch<#async_lifetime>, ::cuda_core::DriverError>
-        #where_clause
-        {
-            #function_binding
-            let mut #launch = ::cuda_host::new_async_kernel_launch_builder(#function.clone());
-            #set_cluster_dim
-            #set_cooperative
-            #(#arg_marshalling)*
-            // SAFETY: this method is unsafe and its caller must uphold the raw
-            // launch configuration contract documented above.
-            Ok(unsafe { #launch.finalize_unchecked(#config) })
-        }
-    }
-}
-
-fn generate_cuda_module_prepared_async_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
-    let vis = &kernel.vis;
-    let cfg_attrs = &kernel.cfg_attrs;
-    let method_attrs = &kernel.method_attrs;
-    let unsafety = &kernel.unsafety;
-    let fn_name = format_ident!("{}_async", kernel.fn_name);
-    let unchecked_name = format_ident!("{}_async_unchecked", kernel.fn_name);
-    let marker_ty = cuda_module_kernel_marker_type(kernel);
-    let generics = cuda_module_async_launch_generics(kernel);
-    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
-    let params: Vec<_> = kernel
-        .params
-        .iter()
-        .map(|param| {
-            let name = &param.name;
-            let host_ty = &param.async_host_ty;
-            quote! { #name: #host_ty }
-        })
-        .collect();
-    let prepared_marshalling = kernel.params.iter().map(cuda_module_async_arg_marshalling);
-    let unchecked_marshalling = kernel.params.iter().map(cuda_module_async_arg_marshalling);
-    let unchecked_function_binding = cuda_module_function_binding(kernel);
-    let prepared = internal_ident("__cuda_oxide_prepared");
-    let config = internal_ident("__cuda_oxide_config");
-    let function = internal_ident("__cuda_oxide_function");
-    let launch = internal_ident("__cuda_oxide_launch");
-    let async_lifetime = cuda_module_async_lifetime();
-    let cluster_dim = kernel.cluster_dim.map(|(x, y, z)| quote! { (#x, #y, #z) });
-    let prepared_cluster = cluster_dim.as_ref().map(|cluster_dim| {
-        quote! { ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim); }
-    });
-    let unchecked_cluster = cluster_dim.as_ref().map(|cluster_dim| {
-        quote! { ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim); }
-    });
-    let prepared_cooperative = kernel.cooperative.then(|| {
-        quote! { ::cuda_host::set_async_kernel_cooperative(&mut #launch, true); }
-    });
-    let unchecked_cooperative = kernel.cooperative.then(|| {
-        quote! { ::cuda_host::set_async_kernel_cooperative(&mut #launch, true); }
-    });
-    let requires_checks = generate_requires_checks(kernel, RequiresLenAccess::AsyncRef);
-    let launch_ty = quote! {
-        ::cuda_host::PreparedAsyncKernelLaunch<#async_lifetime, #marker_ty>
-    };
-    let final_value = quote! {
-        unsafe {
-            ::cuda_host::new_prepared_async_kernel_launch(
-                #launch,
-                (*#prepared).clone(),
-            )
-        }
-    };
-    // Size requirements are evaluated eagerly, before the launch is
-    // enqueued, so a violated relation must surface as a typed error. Only
-    // contracts that declare `requires` pay for the `Result` wrapper.
-    let (return_ty, final_expr, requires_doc) = if requires_checks.is_some() {
-        (
-            quote! {
-                ::core::result::Result<#launch_ty, ::cuda_core::LaunchContractError>
-            },
-            quote! { ::core::result::Result::Ok(#final_value) },
-            Some(quote! {
-                #[doc = ""]
-                #[doc = "Returns a `LaunchContractError` without enqueueing anything if a declared `requires` size requirement does not hold for the supplied arguments."]
-            }),
-        )
-    } else {
-        (launch_ty, final_value, None)
-    };
-
-    quote! {
-        #(#cfg_attrs)*
-        #(#method_attrs)*
-        #requires_doc
-        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-        #vis #unsafety fn #fn_name #impl_generics (
-            &self,
-            #prepared: &::cuda_core::PreparedLaunch<#marker_ty>,
-            #(#params),*
-        ) -> #return_ty
-        #where_clause
-        {
-            #requires_checks
-            let mut #launch =
-                ::cuda_host::new_async_kernel_launch_builder(#prepared.function().clone());
-            #prepared_cluster
-            #prepared_cooperative
-            #(#prepared_marshalling)*
-            // SAFETY: PreparedLaunch validated this kernel-branded config and
-            // the builder has not exposed a way to mutate it after finalization.
-            let #launch = unsafe {
-                #launch.finalize_unchecked(#prepared.__raw_config())
-            };
-            #final_expr
-        }
-
-        #(#cfg_attrs)*
-        #[doc = "Unchecked async launch escape hatch for this contracted kernel."]
-        #[doc = ""]
-        #[doc = "# Safety"]
-        #[doc = "The caller must uphold the kernel's declared geometry, resource, capability, and context contract when the returned operation is scheduled, including any `requires` size requirements. This escape hatch intentionally skips the contract's checks, so an undersized buffer is not caught before the kernel runs."]
-        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-        #vis unsafe fn #unchecked_name #impl_generics (
-            &self,
-            #config: ::cuda_core::LaunchConfig,
-            #(#params),*
-        ) -> ::core::result::Result<
-            ::cuda_host::AsyncKernelLaunch<#async_lifetime>,
-            ::cuda_core::DriverError,
-        >
-        #where_clause
-        {
-            #unchecked_function_binding
-            let mut #launch =
-                ::cuda_host::new_async_kernel_launch_builder(#function.clone());
-            #unchecked_cluster
-            #unchecked_cooperative
-            #(#unchecked_marshalling)*
-            // SAFETY: this method is unsafe and its caller must uphold the
-            // contracted kernel's raw launch requirements documented above.
-            Ok(unsafe { #launch.finalize_unchecked(#config) })
-        }
-    }
-}
-
-fn generate_cuda_module_owned_async_launch_method(kernel: &CudaModuleKernel) -> TokenStream2 {
-    if kernel.launch_contract.is_some() {
-        generate_cuda_module_prepared_owned_async_launch_method(kernel)
-    } else {
-        generate_cuda_module_legacy_owned_async_launch_method(kernel)
-    }
-}
-
-fn generate_cuda_module_legacy_owned_async_launch_method(
-    kernel: &CudaModuleKernel,
-) -> TokenStream2 {
-    let vis = &kernel.vis;
-    let cfg_attrs = &kernel.cfg_attrs;
-    let method_attrs = &kernel.method_attrs;
-    let fn_name = format_ident!("{}_async_owned", kernel.fn_name);
-    let resources = cuda_module_owned_resource_params(kernel);
-    let generics = cuda_module_owned_async_launch_generics(kernel, &resources);
-    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
-    let params = kernel.params.iter().enumerate().map(|(index, param)| {
-        let name = &param.name;
-        match &param.marshal {
-            CudaModuleParamMarshal::Scalar => {
-                let host_ty = &param.async_host_ty;
-                quote! { #name: #host_ty }
-            }
-            CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. } => {
-                let resource_ty = cuda_module_owned_resource_type(index);
-                quote! { #name: #resource_ty }
-            }
-            CudaModuleParamMarshal::WritableDeviceBuffer { .. } => {
-                let resource_ty = cuda_module_owned_resource_type(index);
-                quote! { mut #name: #resource_ty }
-            }
-            // The owned resource carries the buffer; `RowWidthOwned` adds the
-            // row width the kernel will index it by.
-            CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
-                let resource_ty = cuda_module_owned_resource_type(index);
-                quote! { mut #name: ::cuda_host::RowWidthOwned<#resource_ty> }
-            }
-        }
-    });
-    let arg_marshalling = kernel
-        .params
-        .iter()
-        .map(cuda_module_owned_async_arg_marshalling);
-    let function_binding = cuda_module_function_binding(kernel);
-    let config = internal_ident("__cuda_oxide_config");
-    let function = internal_ident("__cuda_oxide_function");
-    let launch = internal_ident("__cuda_oxide_launch");
-    let cluster_dim = kernel.cluster_dim.map(|(x, y, z)| quote! { (#x, #y, #z) });
-    let set_cluster_dim = cluster_dim.map(|cluster_dim| {
-        quote! {
-            ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim);
-        }
-    });
-    let set_cooperative = kernel.cooperative.then(|| {
-        quote! {
-            ::cuda_host::set_async_kernel_cooperative(&mut #launch, true);
-        }
-    });
-    let resources_ty = cuda_module_owned_resources_ty(&resources);
-    let resource_names = resources.iter().map(|(_, name, _, _, _)| name);
-    let resources_expr = if resources.is_empty() {
-        quote! { () }
-    } else {
-        quote! { (#(#resource_names),*) }
-    };
-
-    quote! {
-        #(#cfg_attrs)*
-        #(#method_attrs)*
-        #[doc = "Builds a lazy owned async launch from an unverified raw launch configuration."]
-        #[doc = ""]
-        #[doc = "# Safety"]
-        #[doc = "Before scheduling the returned operation, the launch dimensions and resources must satisfy every indexing, memory-access, launch-bounds, and dynamic-shared-memory assumption made by the kernel. Dimensions not represented by the kernel's index model must not introduce overlapping or out-of-bounds accesses. The caller must also uphold any safety requirements documented on the kernel itself."]
-        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-        #vis unsafe fn #fn_name #impl_generics (
-            &self,
-            #config: ::cuda_core::LaunchConfig,
-            #(#params),*
-        ) -> ::core::result::Result<::cuda_host::OwnedAsyncKernelLaunch<#resources_ty>, ::cuda_core::DriverError>
-        #where_clause
-        {
-            #function_binding
-            let mut #launch =
-                ::cuda_host::new_async_kernel_launch_builder(#function.clone());
-            #set_cluster_dim
-            #set_cooperative
-            #(#arg_marshalling)*
-            // SAFETY: this method is unsafe and its caller must uphold the raw
-            // launch configuration contract documented above.
-            let #launch: ::cuda_host::AsyncKernelLaunch<'static> =
-                unsafe { #launch.finalize_unchecked(#config) };
-            Ok(::cuda_host::new_owned_async_kernel_launch(#launch, #resources_expr))
-        }
-    }
-}
-
-fn generate_cuda_module_prepared_owned_async_launch_method(
-    kernel: &CudaModuleKernel,
-) -> TokenStream2 {
-    let vis = &kernel.vis;
-    let cfg_attrs = &kernel.cfg_attrs;
-    let method_attrs = &kernel.method_attrs;
-    let unsafety = &kernel.unsafety;
-    let fn_name = format_ident!("{}_async_owned", kernel.fn_name);
-    let unchecked_name = format_ident!("{}_async_owned_unchecked", kernel.fn_name);
-    let marker_ty = cuda_module_kernel_marker_type(kernel);
-    let resources = cuda_module_owned_resource_params(kernel);
-    let generics = cuda_module_owned_async_launch_generics(kernel, &resources);
-    let (impl_generics, _ty_generics, where_clause) = generics.split_for_impl();
-    let params: Vec<_> = kernel
-        .params
-        .iter()
-        .enumerate()
-        .map(|(index, param)| {
-            let name = &param.name;
-            match &param.marshal {
-                CudaModuleParamMarshal::Scalar => {
-                    let host_ty = &param.async_host_ty;
-                    quote! { #name: #host_ty }
-                }
-                CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. } => {
-                    let resource_ty = cuda_module_owned_resource_type(index);
-                    quote! { #name: #resource_ty }
-                }
-                CudaModuleParamMarshal::WritableDeviceBuffer { .. } => {
-                    let resource_ty = cuda_module_owned_resource_type(index);
-                    quote! { mut #name: #resource_ty }
-                }
-                // The owned resource carries the buffer; `RowWidthOwned` adds
-                // the row width the kernel will index it by.
-                CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
-                    let resource_ty = cuda_module_owned_resource_type(index);
-                    quote! { mut #name: ::cuda_host::RowWidthOwned<#resource_ty> }
-                }
-            }
-        })
-        .collect();
-    let prepared_marshalling = kernel
-        .params
-        .iter()
-        .map(cuda_module_owned_async_arg_marshalling);
-    let unchecked_marshalling = kernel
-        .params
-        .iter()
-        .map(cuda_module_owned_async_arg_marshalling);
-    let unchecked_function_binding = cuda_module_function_binding(kernel);
-    let prepared = internal_ident("__cuda_oxide_prepared");
-    let config = internal_ident("__cuda_oxide_config");
-    let function = internal_ident("__cuda_oxide_function");
-    let launch = internal_ident("__cuda_oxide_launch");
-    let owned = internal_ident("__cuda_oxide_owned");
-    let cluster_dim = kernel.cluster_dim.map(|(x, y, z)| quote! { (#x, #y, #z) });
-    let prepared_cluster = cluster_dim.as_ref().map(|cluster_dim| {
-        quote! { ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim); }
-    });
-    let unchecked_cluster = cluster_dim.as_ref().map(|cluster_dim| {
-        quote! { ::cuda_host::set_async_kernel_cluster_dim(&mut #launch, #cluster_dim); }
-    });
-    let prepared_cooperative = kernel.cooperative.then(|| {
-        quote! { ::cuda_host::set_async_kernel_cooperative(&mut #launch, true); }
-    });
-    let unchecked_cooperative = kernel.cooperative.then(|| {
-        quote! { ::cuda_host::set_async_kernel_cooperative(&mut #launch, true); }
-    });
-    let resources_ty = cuda_module_owned_resources_ty(&resources);
-    let prepared_resource_names = resources.iter().map(|(_, name, _, _, _)| name);
-    let unchecked_resource_names = resources.iter().map(|(_, name, _, _, _)| name);
-    let prepared_resources_expr = if resources.is_empty() {
-        quote! { () }
-    } else {
-        quote! { (#(#prepared_resource_names),*) }
-    };
-    let unchecked_resources_expr = if resources.is_empty() {
-        quote! { () }
-    } else {
-        quote! { (#(#unchecked_resource_names),*) }
-    };
-    let requires_checks = generate_requires_checks(kernel, RequiresLenAccess::OwnedValue);
-    let launch_ty = quote! {
-        ::cuda_host::PreparedOwnedAsyncKernelLaunch<#resources_ty, #marker_ty>
-    };
-    let final_value = quote! {
-        unsafe {
-            ::cuda_host::new_prepared_owned_async_kernel_launch(
-                #owned,
-                (*#prepared).clone(),
-            )
-        }
-    };
-    // Same policy as the borrowed async launcher: `requires` relations are
-    // checked eagerly, before any resource is moved into the launch, and a
-    // violation surfaces as a typed error instead of an enqueued fault.
-    let (return_ty, final_expr, requires_doc) = if requires_checks.is_some() {
-        (
-            quote! {
-                ::core::result::Result<#launch_ty, ::cuda_core::LaunchContractError>
-            },
-            quote! { ::core::result::Result::Ok(#final_value) },
-            Some(quote! {
-                #[doc = ""]
-                #[doc = "Returns a `LaunchContractError` without enqueueing anything if a declared `requires` size requirement does not hold for the supplied arguments."]
-            }),
-        )
-    } else {
-        (launch_ty, final_value, None)
-    };
-
-    quote! {
-        #(#cfg_attrs)*
-        #(#method_attrs)*
-        #requires_doc
-        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-        #vis #unsafety fn #fn_name #impl_generics (
-            &self,
-            #prepared: &::cuda_core::PreparedLaunch<#marker_ty>,
-            #(#params),*
-        ) -> #return_ty
-        #where_clause
-        {
-            #requires_checks
-            let mut #launch =
-                ::cuda_host::new_async_kernel_launch_builder(#prepared.function().clone());
-            #prepared_cluster
-            #prepared_cooperative
-            #(#prepared_marshalling)*
-            // SAFETY: PreparedLaunch validated this kernel-branded config and
-            // the builder has not exposed a way to mutate it after finalization.
-            let #launch: ::cuda_host::AsyncKernelLaunch<'static> = unsafe {
-                #launch.finalize_unchecked(#prepared.__raw_config())
-            };
-            let #owned =
-                ::cuda_host::new_owned_async_kernel_launch(#launch, #prepared_resources_expr);
-            #final_expr
-        }
-
-        #(#cfg_attrs)*
-        #[doc = "Unchecked owned-async launch escape hatch for this contracted kernel."]
-        #[doc = ""]
-        #[doc = "# Safety"]
-        #[doc = "The caller must uphold the kernel's declared geometry, resource, capability, and context contract when the returned operation is scheduled, including any `requires` size requirements. This escape hatch intentionally skips the contract's checks, so an undersized buffer is not caught before the kernel runs."]
-        #[allow(clippy::multiple_bound_locations, clippy::too_many_arguments)]
-        #vis unsafe fn #unchecked_name #impl_generics (
-            &self,
-            #config: ::cuda_core::LaunchConfig,
-            #(#params),*
-        ) -> ::core::result::Result<
-            ::cuda_host::OwnedAsyncKernelLaunch<#resources_ty>,
-            ::cuda_core::DriverError,
-        >
-        #where_clause
-        {
-            #unchecked_function_binding
-            let mut #launch =
-                ::cuda_host::new_async_kernel_launch_builder(#function.clone());
-            #unchecked_cluster
-            #unchecked_cooperative
-            #(#unchecked_marshalling)*
-            // SAFETY: this method is unsafe and its caller must uphold the
-            // contracted kernel's raw launch requirements documented above.
-            let #launch: ::cuda_host::AsyncKernelLaunch<'static> =
-                unsafe { #launch.finalize_unchecked(#config) };
-            Ok(::cuda_host::new_owned_async_kernel_launch(
-                #launch,
-                #unchecked_resources_expr,
-            ))
-        }
-    }
-}
-
-fn cuda_module_launch_generics(kernel: &CudaModuleKernel) -> syn::Generics {
-    let mut generics = kernel.generics.clone();
-    for param in &kernel.params {
-        if matches!(param.marshal, CudaModuleParamMarshal::Scalar) {
-            let host_ty = &param.sync_host_ty;
-            generics
-                .make_where_clause()
-                .predicates
-                .push(syn::parse_quote! { #host_ty: ::cuda_host::KernelScalar });
-        }
-    }
-    generics
-}
-
-fn cuda_module_owned_async_launch_generics(
-    kernel: &CudaModuleKernel,
-    resources: &[(usize, Ident, TokenStream2, bool, bool)],
-) -> syn::Generics {
-    let mut generics = kernel.generics.clone();
-    for (index, _, elem_ty, writable, _) in resources {
-        let resource_ty = cuda_module_owned_resource_type(*index);
-        generics.params.push(syn::parse_quote! { #resource_ty });
-        let predicate: syn::WherePredicate = if *writable {
-            syn::parse_quote! {
-                #resource_ty: ::cuda_host::KernelSliceArgMut<Elem = #elem_ty> + Send + 'static
-            }
-        } else {
-            syn::parse_quote! {
-                #resource_ty: ::cuda_host::KernelSliceArg<Elem = #elem_ty> + Send + 'static
-            }
-        };
-        generics.make_where_clause().predicates.push(predicate);
-    }
-    for param in &kernel.params {
-        if matches!(param.marshal, CudaModuleParamMarshal::Scalar) {
-            let host_ty = &param.async_host_ty;
-            generics
-                .make_where_clause()
-                .predicates
-                .push(syn::parse_quote! { #host_ty: ::cuda_host::KernelScalar + 'static });
-        }
-    }
-    generics
-}
-
-fn cuda_module_async_launch_generics(kernel: &CudaModuleKernel) -> syn::Generics {
-    let mut generics = kernel.generics.clone();
-    let async_lifetime = cuda_module_async_lifetime();
-    let lifetime_param = syn::LifetimeParam::new(async_lifetime.clone());
-    generics
-        .params
-        .insert(0, syn::GenericParam::Lifetime(lifetime_param));
-    for param in &kernel.params {
-        if matches!(param.marshal, CudaModuleParamMarshal::Scalar) {
-            let host_ty = &param.async_host_ty;
-            generics
-                .make_where_clause()
-                .predicates
-                .push(syn::parse_quote! { #host_ty: ::cuda_host::KernelScalar + #async_lifetime });
-        }
-    }
-    generics
-}
-
-fn cuda_module_owned_resource_params(
-    kernel: &CudaModuleKernel,
-) -> Vec<(usize, Ident, TokenStream2, bool, bool)> {
-    kernel
-        .params
-        .iter()
-        .enumerate()
-        .filter_map(|(index, param)| match &param.marshal {
-            CudaModuleParamMarshal::Scalar => None,
-            CudaModuleParamMarshal::ReadOnlyDeviceBuffer { elem_ty } => {
-                Some((index, param.name.clone(), elem_ty.clone(), false, false))
-            }
-            CudaModuleParamMarshal::WritableDeviceBuffer { elem_ty } => {
-                Some((index, param.name.clone(), elem_ty.clone(), true, false))
-            }
-            // A row-width slice still owns a buffer resource; the width
-            // rides beside it in `RowWidthOwned`.
-            CudaModuleParamMarshal::RowWidthDeviceBuffer { elem_ty } => {
-                Some((index, param.name.clone(), elem_ty.clone(), true, true))
-            }
-        })
-        .collect()
-}
-
-fn cuda_module_owned_resource_type(index: usize) -> Ident {
-    internal_ident(&format!("__CudaModuleArg{index}"))
-}
-
-fn cuda_module_owned_resources_ty(
-    resources: &[(usize, Ident, TokenStream2, bool, bool)],
-) -> TokenStream2 {
-    if resources.is_empty() {
-        quote! { () }
-    } else {
-        let resource_tys = resources.iter().map(|(index, _, _, _, has_row_width)| {
-            let resource_ty = cuda_module_owned_resource_type(*index);
-            if *has_row_width {
-                quote! { ::cuda_host::RowWidthOwned<#resource_ty> }
-            } else {
-                quote! { #resource_ty }
-            }
-        });
-        quote! { (#(#resource_tys),*) }
-    }
-}
-
-fn cuda_module_arg_marshalling(index: usize, param: &CudaModuleParam) -> TokenStream2 {
-    let name = &param.name;
-    let args = internal_ident("__cuda_oxide_args");
-    let value_name = internal_ident(&format!("__cuda_oxide_arg_{index}"));
-    match param.marshal {
-        CudaModuleParamMarshal::Scalar => {
-            quote! {
-                let mut #value_name = #name;
-                ::cuda_host::push_kernel_scalar(&mut #args, &mut #value_name);
-            }
-        }
-        CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. } => {
-            let ptr_name = internal_ident(&format!("__cuda_oxide_arg_{index}_ptr"));
-            let len_name = internal_ident(&format!("__cuda_oxide_arg_{index}_len"));
-            quote! {
-                let (mut #ptr_name, mut #len_name) =
-                    ::cuda_host::read_only_device_buffer_arg(#name);
-                ::cuda_host::push_kernel_device_slice(
-                    &mut #args,
-                    &mut #ptr_name,
-                    &mut #len_name,
-                );
-            }
-        }
-        CudaModuleParamMarshal::WritableDeviceBuffer { .. } => {
-            let ptr_name = internal_ident(&format!("__cuda_oxide_arg_{index}_ptr"));
-            let len_name = internal_ident(&format!("__cuda_oxide_arg_{index}_len"));
-            quote! {
-                let (mut #ptr_name, mut #len_name) =
-                    ::cuda_host::writable_device_buffer_arg(#name);
-                ::cuda_host::push_kernel_device_slice(
-                    &mut #args,
-                    &mut #ptr_name,
-                    &mut #len_name,
-                );
-            }
-        }
-        CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
-            let ptr_name = internal_ident(&format!("__cuda_oxide_arg_{index}_ptr"));
-            let len_name = internal_ident(&format!("__cuda_oxide_arg_{index}_len"));
-            let width_name = internal_ident(&format!("__cuda_oxide_arg_{index}_row_width"));
-            quote! {
-                let (mut #ptr_name, mut #len_name, mut #width_name) =
-                    ::cuda_host::row_width_device_buffer_arg(#name);
-                ::cuda_host::push_kernel_row_width_device_slice(
-                    &mut #args,
-                    &mut #ptr_name,
-                    &mut #len_name,
-                    &mut #width_name,
-                );
-            }
-        }
-    }
-}
-
-fn cuda_module_owned_async_arg_marshalling(param: &CudaModuleParam) -> TokenStream2 {
-    let name = &param.name;
-    let launch = internal_ident("__cuda_oxide_launch");
-    match param.marshal {
-        CudaModuleParamMarshal::Scalar => {
-            quote! {
-                ::cuda_host::push_async_kernel_scalar(&mut #launch, #name);
-            }
-        }
-        CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. } => {
-            quote! {
-                ::cuda_host::push_async_read_only_device_slice(&mut #launch, &#name);
-            }
-        }
-        CudaModuleParamMarshal::WritableDeviceBuffer { .. } => {
-            quote! {
-                ::cuda_host::push_async_writable_device_slice(&mut #launch, &mut #name);
-            }
-        }
-        CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
-            quote! {
-                ::cuda_host::push_async_owned_row_width_device_slice(&mut #launch, &mut #name);
-            }
-        }
-    }
-}
-
-fn cuda_module_async_arg_marshalling(param: &CudaModuleParam) -> TokenStream2 {
-    let name = &param.name;
-    let launch = internal_ident("__cuda_oxide_launch");
-    match param.marshal {
-        CudaModuleParamMarshal::Scalar => {
-            quote! {
-                ::cuda_host::push_async_kernel_scalar(&mut #launch, #name);
-            }
-        }
-        CudaModuleParamMarshal::ReadOnlyDeviceBuffer { .. } => {
-            quote! {
-                ::cuda_host::push_async_read_only_device_slice(&mut #launch, #name);
-            }
-        }
-        CudaModuleParamMarshal::WritableDeviceBuffer { .. } => {
-            quote! {
-                ::cuda_host::push_async_writable_device_slice(&mut #launch, #name);
-            }
-        }
-        CudaModuleParamMarshal::RowWidthDeviceBuffer { .. } => {
-            quote! {
-                ::cuda_host::push_async_row_width_device_slice(&mut #launch, #name);
-            }
-        }
-    }
-}
-
-fn cuda_module_function_binding(kernel: &CudaModuleKernel) -> TokenStream2 {
-    let function = internal_ident("__cuda_oxide_function");
-    if kernel.is_generic {
-        let ptx_name_fn = format_ident!("{}_ptx_name", kernel.fn_name);
-        let codegen_args = codegen_generic_arguments(&kernel.generics);
-        let turbofish = if codegen_args.is_empty() {
-            quote! {}
-        } else {
-            quote! { ::<#(#codegen_args),*> }
-        };
-        let ptx_name = internal_ident("__cuda_oxide_ptx_name");
-        let function_storage = internal_ident("__cuda_oxide_function_storage");
-        let cache = internal_ident("__cuda_oxide_function_cache");
-        quote! {
-            let #ptx_name = #ptx_name_fn #turbofish ();
-            let #function_storage = {
-                let mut #cache = self
-                    .__generic_functions
-                    .lock()
-                    .expect("cuda_module generic function cache poisoned");
-                if let Some(#function) = #cache.get(#ptx_name) {
-                    #function.clone()
-                } else {
-                    let #function = self.__module.load_function(#ptx_name)?;
-                    #cache.insert(#ptx_name, #function.clone());
-                    #function
-                }
-            };
-            let #function = &#function_storage;
-        }
-    } else {
-        let field = cuda_module_function_field(&kernel.fn_name);
-        quote! {
-            let #function = &self.#field;
-        }
-    }
-}
-
-fn cuda_module_launch_call(kernel: &CudaModuleKernel) -> TokenStream2 {
-    let function = internal_ident("__cuda_oxide_function");
-    let stream = internal_ident("__cuda_oxide_stream");
-    let config = internal_ident("__cuda_oxide_config");
-    let args = internal_ident("__cuda_oxide_args");
-    let cluster_dim = kernel.cluster_dim.map(|(x, y, z)| quote! { (#x, #y, #z) });
-    match (cluster_dim, kernel.cooperative) {
-        (Some(cluster_dim), true) => quote! {
-            unsafe {
-                ::cuda_core::launch_kernel_ex_cooperative_on_stream(
-                    #function,
-                    #config.grid_dim,
-                    #config.block_dim,
-                    #config.shared_mem_bytes,
-                    #cluster_dim,
-                    #stream,
-                    &mut #args,
-                )
-            }
-        },
-        (Some(cluster_dim), false) => quote! {
-            unsafe {
-                ::cuda_core::launch_kernel_ex_on_stream(
-                    #function,
-                    #config.grid_dim,
-                    #config.block_dim,
-                    #config.shared_mem_bytes,
-                    #cluster_dim,
-                    #stream,
-                    &mut #args,
-                )
-            }
-        },
-        (None, true) => quote! {
-            unsafe {
-                ::cuda_core::launch_kernel_cooperative_on_stream(
-                    #function,
-                    #config.grid_dim,
-                    #config.block_dim,
-                    #config.shared_mem_bytes,
-                    #stream,
-                    &mut #args,
-                )
-            }
-        },
-        (None, false) => quote! {
-            unsafe {
-                ::cuda_core::launch_kernel_on_stream(
-                    #function,
-                    #config.grid_dim,
-                    #config.block_dim,
-                    #config.shared_mem_bytes,
-                    #stream,
-                    &mut #args,
-                )
-            }
-        },
-    }
-}
-
-/// Whether rustc must create distinct code for this generic parameter list.
-///
-/// Lifetimes are deliberately excluded: rustc erases them before codegen, so
-/// they cannot distinguish PTX entry points. Type and const parameters both
-/// participate in monomorphization and therefore in kernel identity.
-fn has_codegen_generics(generics: &syn::Generics) -> bool {
-    generics
-        .params
-        .iter()
-        .any(|param| matches!(param, GenericParam::Type(_) | GenericParam::Const(_)))
-}
-
-/// Ordered generic arguments accepted by a function turbofish.
-///
-/// Rust function turbofish syntax omits lifetime arguments. Type and const
-/// identifiers must remain in declaration order so mixed `<T, const N>`
-/// kernels instantiate the exact function item requested by the caller.
-fn codegen_generic_arguments(generics: &syn::Generics) -> Vec<TokenStream2> {
-    generics
-        .params
-        .iter()
-        .filter_map(|param| match param {
-            GenericParam::Type(type_param) => {
-                let ident = &type_param.ident;
-                Some(quote! { #ident })
-            }
-            GenericParam::Const(const_param) => {
-                let ident = &const_param.ident;
-                Some(quote! { #ident })
-            }
-            GenericParam::Lifetime(_) => None,
-        })
-        .collect()
-}
-
-/// Ordered arguments for applying a generated marker type.
-///
-/// Unlike function turbofish syntax, a type application retains lifetime
-/// parameters. The specialization hash still ignores their identity because
-/// rustc's `TypeId` pipeline erases regions.
-fn generic_arguments(generics: &syn::Generics) -> Vec<TokenStream2> {
-    generics
-        .params
-        .iter()
-        .map(|param| match param {
-            GenericParam::Lifetime(lifetime_param) => {
-                let lifetime = &lifetime_param.lifetime;
-                quote! { #lifetime }
-            }
-            GenericParam::Type(type_param) => {
-                let ident = &type_param.ident;
-                quote! { #ident }
-            }
-            GenericParam::Const(const_param) => {
-                let ident = &const_param.ident;
-                quote! { #ident }
-            }
-        })
-        .collect()
-}
-
-/// Types used by `PhantomData` so generated marker types correctly witness
-/// every lifetime and type parameter. Const parameters are part of the marker
-/// type by construction and need no field-level witness.
-fn generic_phantom_type(generics: &syn::Generics) -> TokenStream2 {
-    let witnesses: Vec<TokenStream2> = generics
-        .params
-        .iter()
-        .filter_map(|param| match param {
-            GenericParam::Lifetime(lifetime_param) => {
-                let lifetime = &lifetime_param.lifetime;
-                Some(quote! { &#lifetime () })
-            }
-            GenericParam::Type(type_param) => {
-                let ident = &type_param.ident;
-                Some(quote! { *const #ident })
-            }
-            GenericParam::Const(_) => None,
-        })
-        .collect();
-
-    if witnesses.is_empty() {
-        quote! { () }
-    } else {
-        quote! { (#(#witnesses,)*) }
-    }
-}
-
-fn cuda_module_function_field(fn_name: &Ident) -> Ident {
-    format_ident!("__{}_function", fn_name)
-}
-
-fn cuda_kernel_marker_name(fn_name: &Ident) -> Ident {
-    format_ident!("__{}_CudaKernel", fn_name)
-}
-
-/// Marks a function as a CUDA kernel.
-///
-/// This attribute:
-/// 1. Adds `#[no_mangle]` to preserve the function name in the binary
-/// 2. Marks the function for detection by the `rustc-codegen-cuda` backend
-///
-/// # Generic Kernels
-///
-/// For generic kernels (like `template<class F> __global__` in CUDA C++),
-/// specify the types to instantiate:
-///
-/// ```ignore
-/// #[kernel(Scale, Fma, Square)]
-/// pub fn map<F: GpuFn>(f: F, input: &[i32], output: DisjointSlice<i32>) {
-///     // ...
-/// }
-/// ```
-///
-/// This generates three PTX entry points: `map_Scale`, `map_Fma`, `map_Square`.
-/// Each is a monomorphized version of the generic kernel.
-///
-/// # Example (non-generic)
-///
-/// ```ignore
-/// #[kernel]
-/// pub fn simple_kernel(data: &mut [i32]) {
-///     // ...
-/// }
-/// ```
-///
-/// Kernels that use contract-backed fast coordinates name their launch
-/// capability explicitly. It is a local device-only binding, not an ABI
-/// parameter:
-///
-/// ```ignore
-/// #[kernel(launch_context = launch_context)]
-/// #[launch_contract(domain = 1, coordinates = u32, block = (256, 1, 1))]
-/// pub fn map(mut output: DisjointSlice<u32>) {
-///     let index = thread::index_1d_u32(launch_context);
-///     // ...
-/// }
-/// ```
-///
-/// # Unchecked indexing (opt-in, trust-me contract)
-///
-/// `#[kernel(unchecked_indexing)]` tells the compiler to **delete the safety
-/// check behind slice/array indexing** (`a[i]`) in this kernel. Normally
-/// every `a[i]` compiles to "is `i` inside the slice? if not, stop the
-/// kernel"; with this flag the access happens unconditionally. You are
-/// promising that every index is in bounds, the same promise as
-/// [`slice::get_unchecked`]. If the promise is wrong, the result is
-/// **undefined behavior**: no guard, no trap, possibly silent corruption of
-/// unrelated data. Turn it on only after the checked build is proven correct
-/// (for example under `compute-sanitizer`).
-///
-/// ```ignore
-/// #[kernel(unchecked_indexing)]
-/// pub fn hot_loop(a: &[f32], b: &[f32], mut c: DisjointSlice<f32>) {
-///     let idx = thread::index_1d().get();
-///     if let Some(out) = c.get_mut(thread::index_1d()) {
-///         *out = a[idx] + b[idx]; // no bounds guard or trap emitted
-///     }
-/// }
-/// ```
-///
-/// The flag composes with the other kernel arguments, e.g.
-/// `#[kernel(f32, unchecked_indexing)]` or
-/// `#[kernel(launch_context = lc, unchecked_indexing)]`.
-///
-/// The bare word `unchecked_indexing` is **reserved** in the `#[kernel]`
-/// argument list: it always parses as this flag, never as a legacy
-/// instantiation type. A user type literally named `unchecked_indexing` can
-/// still be instantiated by spelling it as a path, e.g.
-/// `#[kernel(self::unchecked_indexing)]` or
-/// `#[kernel(crate::unchecked_indexing)]`, which parses as a type.
-///
-/// Scope and caveats:
-///
-/// - Only the checks behind indexing (`a[i]`) are removed. Arithmetic
-///   overflow, division/remainder by zero, misaligned-pointer checks, and
-///   every other safety check keep their normal compare-and-trap behavior.
-/// - Range-indexing failures (`&a[i..j]`) and explicit panics arrive as calls
-///   to `core::panicking::*`, not as MIR asserts, so they still trap.
-/// - The flag covers the kernel's translated MIR body, including everything
-///   rustc MIR-inlined into it. Separately translated `#[device]` functions
-///   are **not** covered; the whole-build switch
-///   `CUDA_OXIDE_UNCHECKED_INDEXING=1` (or `cargo oxide ...
-///   --unchecked-indexing`) covers every translated body.
-/// - Elision never leaks out of the opted kernel. For generic kernels
-///   (including legacy `#[kernel(T, ...)]` instantiation), the expansion
-///   keeps the elision marker on the generated entry function plus a hidden
-///   unchecked twin of the implementation that only that entry calls. The
-///   user-named implementation function stays ordinary bounds-checked Rust,
-///   so a different kernel or `#[device]` function that calls it keeps its
-///   own bounds checks (fail-closed).
-///
-/// # Loop unrolling
-///
-/// Put `#[unroll]` on a loop with a compile-time-known trip count to request full
-/// unrolling. Use `#[unroll(N)]`, where `N >= 2`, to request `N` iterations of
-/// work per trip; a remainder loop handles any leftovers.
-///
-/// ```ignore
-/// #[kernel]
-/// pub fn example(n: u32) {
-///     let mut i = 0;
-///     #[unroll]
-///     while i < 4 { work(i); i += 1; }
-///
-///     let mut j = 0;
-///     #[unroll(4)]
-///     while j < n { work(j); j += 1; }
-/// }
-/// ```
-///
-/// A factor may also be a typed `u32` policy constant, such as
-/// `#[unroll(P::UNROLL)]`. A generic expression currently requires Rust's
-/// `generic_const_exprs` feature. Partial factors must be in `2..=1024`; an
-/// invalid specialization fails compilation instead of becoming a no-op.
-///
-/// The pass currently recognizes explicit counted `while` loops. Range-based
-/// `for` loops are not yet recognized.
-///
-/// Only the annotated loop is unrolled. Inner loops are copied intact unless
-/// they carry their own annotation. Several `continue` paths (multiple
-/// back-edges) are supported.
-///
-/// Full `#[unroll]` preserves `break` paths and multiple exit targets. Partial
-/// `#[unroll(N)]` currently requires the loop condition to be the only exit. If
-/// the loop has a `break` or another extra exit, the compiler warns and skips
-/// partial unrolling for that loop.
-///
-/// Partial unrolling also requires a positive counter step, a `<` or `<=` test,
-/// and a limit that does not change inside the loop. One annotation may create
-/// at most 1,024 body copies, 8,192 cloned basic blocks, and 65,536 cloned
-/// operations. Factors above 1,024 are rejected; unsupported loop shapes warn
-/// and are not unrolled.
-#[proc_macro_attribute]
-pub fn kernel(attr: TokenStream, item: TokenStream) -> TokenStream {
-    track_codegen_environment();
-    let args = parse_macro_input!(attr as KernelArgs);
-    let mut input = parse_macro_input!(item as ItemFn);
-
-    let KernelArgs {
-        instantiate_types,
-        launch_context,
-        unchecked_indexing,
-    } = args;
-
-    if let Some(err) = reject_reserved_name(&input.sig.ident) {
-        return err;
-    }
-    if let Some(err) = impl_trait_parameter_error(&input, "kernel") {
-        return err.to_compile_error().into();
-    }
-    if let Some(launch_context) = &launch_context
-        && let Some(parameter) = scope_parameter_collision(&input, launch_context)
-    {
-        return syn::Error::new_spanned(
-            parameter,
-            format!(
-                "kernel launch-context binding `{launch_context}` conflicts with a function parameter; choose a distinct name in `#[kernel(launch_context = ...)]`"
-            ),
-        )
-        .to_compile_error()
-        .into();
-    }
-
-    // Consume any `#[unroll]` / `#[unroll(N)]` attributes written directly on
-    // loops inside the kernel body. We strip the attribute from the loop
-    // expression (so rustc never sees an expression attribute, keeping us off
-    // nightly `stmt_expr_attributes`) and inject an
-    // `__unroll_config::<FACTOR>()` marker into the loop body. If the visitor
-    // hits a malformed attribute it records the error so we can surface it as a
-    // compile error below.
-    if let Err(err) = rewrite_loop_unroll_attrs(&mut input) {
-        return err.to_compile_error().into();
-    }
-    if let Err(err) = add_launch_bounds_evaluatability_from_attrs(&mut input) {
-        return err.to_compile_error().into();
-    }
-
-    // Insert the unchecked-indexing compiler marker at the top of the kernel
-    // body. The MIR importer detects the call, elides bounds-check asserts in
-    // the translated body, and strips the call before code generation. For
-    // simple kernels the function itself becomes the entry, so the marker
-    // stays put. Generic kernel generation strips the marker from the
-    // re-emitted user-named implementation helper and confines it to the
-    // generated entry wrapper (forwarded via
-    // `top_level_kernel_configuration_markers`) plus a hidden unchecked twin
-    // of the implementation that only the entry calls; see
-    // `strip_unchecked_indexing_config_marker` and
-    // `unchecked_indexing_impl_clone`.
-    if unchecked_indexing {
-        let marker_call: syn::Stmt = syn::parse_quote! {
-            ::cuda_device::thread::__unchecked_indexing_config::<true>();
-        };
-        input.block.stmts.insert(0, marker_call);
-    }
-
-    // Only type and const parameters create distinct codegen instances.
-    // Lifetimes are erased before monomorphization.
-    let has_generics = has_codegen_generics(&input.sig.generics);
-
-    if has_generics && !instantiate_types.is_empty() {
-        let type_param_count = input
-            .sig
-            .generics
-            .params
-            .iter()
-            .filter(|param| matches!(param, GenericParam::Type(_)))
-            .count();
-        let has_const_params = input
-            .sig
-            .generics
-            .params
-            .iter()
-            .any(|param| matches!(param, GenericParam::Const(_)));
-        let has_lifetime_params = input
-            .sig
-            .generics
-            .params
-            .iter()
-            .any(|param| matches!(param, GenericParam::Lifetime(_)));
-        if type_param_count != 1 || has_const_params || has_lifetime_params {
-            return syn::Error::new_spanned(
-                &input.sig.generics,
-                "legacy #[kernel(Type, ...)] instantiation supports exactly one type parameter and no lifetime or const parameters; use #[kernel] and instantiate the kernel with a normal turbofish at the launch site",
-            )
-            .to_compile_error()
-            .into();
-        }
-    }
-
-    if has_generics && instantiate_types.is_empty() {
-        // Generic kernel without explicit types - allow it!
-        // Instantiation will happen from call sites (nvcc-style)
-        return generate_generic_kernel_no_instantiation(input, launch_context);
-    }
-
-    if !has_generics && !instantiate_types.is_empty() {
-        // Non-generic kernel with instantiation types - error
-        return syn::Error::new_spanned(
-            &input.sig.ident,
-            "Instantiation types only apply to generic kernels",
-        )
-        .to_compile_error()
-        .into();
-    }
-
-    if has_generics {
-        // Generate wrapper kernels for each instantiation type
-        generate_generic_kernel(input, instantiate_types, launch_context)
-    } else {
-        // Simple non-generic kernel
-        generate_simple_kernel(input, launch_context)
-    }
-}
-
-struct ConstantArgs {
-    export_name: Option<LitStr>,
-}
-
-impl Parse for ConstantArgs {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        if input.is_empty() {
-            return Ok(Self { export_name: None });
-        }
-
-        let key: Ident = input.parse()?;
-        if key != "export_name" {
-            return Err(syn::Error::new_spanned(
-                key,
-                "#[constant] does not take public arguments",
-            ));
-        }
-        input.parse::<Token![=]>()?;
-        let export_name = input.parse()?;
-        if !input.is_empty() {
-            input.parse::<Token![,]>()?;
-            if !input.is_empty() {
-                return Err(input.error("unexpected tokens after #[constant] export_name"));
-            }
-        }
-        Ok(Self {
-            export_name: Some(export_name),
-        })
-    }
-}
-
-/// Mark a module-scope `static` as a CUDA constant-memory global.
-///
-/// The static must be typed `ConstantMemory<T>` (see
-/// [`cuda_device::ConstantMemory`](../../cuda_device/struct.ConstantMemory.html)). The
-/// `ConstantMemory<T>` wrapper has `UnsafeCell<T>` semantics on the device,
-/// preventing the compiler from constant-folding the initializer and making
-/// the host's `cuMemcpyHtoD` updates observable from kernels.
-///
-/// The macro adds a reserved `#[unsafe(export_name = "cuda_oxide_const_246e25db_...")]`
-/// so the PTX symbol carries a name the host can resolve via
-/// `cuModuleGetGlobal`. When used inside `#[cuda_module]`, the generated name
-/// includes module/source-location context to avoid collisions between constants
-/// that share the same Rust identifier. The host-side `#[cuda_module]` expansion
-/// separately generates per-constant setter methods on the loaded module:
-///
-/// - `module.set_<name>(&stream, &value)` — stream-ordered async write
-///   (recommended; orders correctly against surrounding kernel launches).
-/// - `module.set_<name>_blocking(&value)` — synchronous `cuMemcpyHtoD`
-///   for one-shot initialization where no stream is in scope.
-///
-/// # Restrictions
-///
-/// - The static must be typed `ConstantMemory<T>`.
-/// - The initializer must be `ConstantMemory::UNINIT` (or any other all-zeros
-///   value). Honoring arbitrary non-zero initializers is not yet
-///   implemented; populate from the host before any kernel reads the value.
-/// - The attribute must appear inside a `#[cuda_module]`. Placed elsewhere
-///   it silently produces an unreachable symbol (no setter is generated).
-/// - The identifier must not start with the reserved cuda-oxide prefix.
-///
-/// # Example
-///
-/// ```ignore
-/// #[cuda_module]
-/// mod kernels {
-///     #[constant]
-///     static COEFFS: ConstantMemory<[f32; 4]> = ConstantMemory::UNINIT;
-///
-///     #[kernel]
-///     pub fn compute(mut out: DisjointSlice<f32>) {
-///         let c = COEFFS.get();
-///         let i = thread::index_1d().get();
-///         if let Some(e) = out.get_mut(thread::index_1d()) {
-///             *e = c[0] * (i as f32) + c[1];
-///         }
-///     }
-/// }
-///
-/// // Host
-/// module.set_coeffs(&stream, &[1.0, 2.0, 3.0, 4.0])?;
-/// ```
-#[proc_macro_attribute]
-pub fn constant(attr: TokenStream, item: TokenStream) -> TokenStream {
-    track_codegen_environment();
-    let args = parse_macro_input!(attr as ConstantArgs);
-    let input = parse_macro_input!(item as syn::ItemStatic);
-
-    if let Some(err) = reject_reserved_name(&input.ident) {
-        return err;
-    }
-
-    if extract_constant_inner_ty(&input.ty).is_none() {
-        return syn::Error::new_spanned(
-            &input.ty,
-            "#[constant] static must have type `ConstantMemory<T>` \
-             (e.g. `static FOO: ConstantMemory<[f32; 4]> = ConstantMemory::UNINIT;`). \
-             The wrapper prevents the compiler from constant-folding the \
-             initializer into kernel bodies.",
-        )
-        .to_compile_error()
-        .into();
-    }
-
-    let export_name = args.export_name.unwrap_or_else(|| {
-        LitStr::new(
-            &constant_symbol(&input.ident.to_string()),
-            input.ident.span(),
-        )
-    });
-
-    quote! {
-        #[unsafe(export_name = #export_name)]
-        #input
-    }
-    .into()
-}
-
-/// Find the generic type parameter that has a Fn/FnMut/FnOnce bound (the closure type).
-/// Returns the type parameter name if found.
-fn find_closure_generic(generics: &syn::Generics) -> Option<syn::Ident> {
-    for param in &generics.params {
-        if let syn::GenericParam::Type(type_param) = param {
-            for bound in &type_param.bounds {
-                if is_fn_trait_bound(bound) {
-                    return Some(type_param.ident.clone());
-                }
-            }
-        }
-    }
-
-    if let Some(where_clause) = &generics.where_clause {
-        for predicate in &where_clause.predicates {
-            let syn::WherePredicate::Type(predicate_type) = predicate else {
-                continue;
-            };
-            if !predicate_type.bounds.iter().any(is_fn_trait_bound) {
-                continue;
-            }
-            let Type::Path(type_path) = &predicate_type.bounded_ty else {
-                continue;
-            };
-            if type_path.qself.is_none()
-                && type_path.path.segments.len() == 1
-                && let Some(segment) = type_path.path.segments.first()
-            {
-                return Some(segment.ident.clone());
-            }
-        }
-    }
-
-    None
-}
-
-fn is_fn_trait_bound(bound: &syn::TypeParamBound) -> bool {
-    let syn::TypeParamBound::Trait(trait_bound) = bound else {
-        return false;
-    };
-    trait_bound.path.segments.last().is_some_and(|segment| {
-        matches!(
-            segment.ident.to_string().as_str(),
-            "Fn" | "FnMut" | "FnOnce"
-        )
-    })
-}
-
-/// Find which function parameter uses the closure type.
-/// Returns the index and info of the closure parameter.
-fn find_closure_param<'a>(
-    args_info: &'a [(&'a Ident, &'a Type)],
-    closure_type_name: &syn::Ident,
-) -> Option<(usize, &'a (&'a Ident, &'a Type))> {
-    for (idx, (_name, ty)) in args_info.iter().enumerate() {
-        // Check if the type is a simple path matching our closure generic
-        if let Type::Path(type_path) = *ty
-            && type_path.qself.is_none()
-            && let Some(segment) = type_path.path.segments.first()
-            && type_path.path.segments.len() == 1
-            && segment.ident == *closure_type_name
-        {
-            return Some((idx, &args_info[idx]));
-        }
-    }
-    None
-}
-
-/// Build wrapper parameters that can always be forwarded by value.
-///
-/// User functions may use any irrefutable parameter pattern, including `_` or
-/// tuple destructuring. A generated wrapper cannot refer to those patterns
-/// again, so every parameter gets a private synthetic identifier while keeping
-/// its original type and attributes. The original implementation retains the
-/// user's pattern.
-fn forwarding_inputs(
-    inputs: &syn::punctuated::Punctuated<FnArg, syn::token::Comma>,
-) -> syn::Result<(Vec<FnArg>, Vec<Ident>)> {
-    let mut wrapper_inputs = Vec::with_capacity(inputs.len());
-    let mut forwarding_names = Vec::with_capacity(inputs.len());
-
-    for (index, arg) in inputs.iter().enumerate() {
-        let FnArg::Typed(pat_type) = arg else {
-            return Err(syn::Error::new_spanned(
-                arg,
-                "CUDA kernels and device functions cannot take self parameters",
-            ));
-        };
-        let name = internal_ident(&format!("__cuda_oxide_arg_{index}"));
-        let mut wrapper_param = pat_type.clone();
-        wrapper_param.pat = Box::new(parse_quote! { #name });
-        wrapper_inputs.push(FnArg::Typed(wrapper_param));
-        forwarding_names.push(name);
-    }
-
-    Ok((wrapper_inputs, forwarding_names))
-}
-
-/// True when `path`'s *last* segment is `name`.
-///
-/// We deliberately match on the tail only, so all of these resolve to the
-/// same intrinsic:
-///
-/// ```ignore
-/// index_1d()
-/// thread::index_1d()
-/// cuda_device::thread::index_1d()
-/// ::cuda_device::thread::index_1d()
-/// ```
-///
-/// And imports/aliases work too:
-///
-/// ```ignore
-/// use cuda_device::thread::index_1d;          // bare ident → matches
-/// use cuda_device::thread::index_1d as foo;   // aliased    → won't match (path tail is `foo`)
-/// ```
-///
-/// The aliased form is intentionally not rewritten — if the user picked a
-/// new name, they get the bare-stub-panic behaviour, not silent capture.
-///
-/// Caveat: if the user defines a *local* `fn index_1d` (or any other
-/// reserved name) and calls it from inside `#[kernel]` / `#[device]`,
-/// that call gets rewritten too. See the `Reserved names` section in
-/// `ThreadIndex`'s doc-block — the convention is to pick a different
-/// name (e.g. `compute_index_1d`) for any helper you want to keep.
-fn is_thread_index_path(path: &Path, name: &str) -> bool {
-    path.segments.last().is_some_and(|seg| seg.ident == name)
-}
-
-/// Build the rewritten path that points the user's call at the
-/// `__internal::<name>` shim, preserving whatever prefix the user wrote.
-///
-/// The motivation is unused-import hygiene. If the user wrote
-/// `use cuda_device::thread;` and called `thread::index_1d()`, replacing
-/// the whole call with an absolute path makes rustc see the `thread`
-/// import as unused. Instead, we splice `__internal` in front of the
-/// last segment and keep everything before it intact:
-///
-/// ```text
-/// thread::index_1d()                   →  thread::__internal::index_1d(&scope)
-/// cuda_device::thread::index_1d()      →  cuda_device::thread::__internal::index_1d(&scope)
-/// ::cuda_device::thread::index_1d()    →  ::cuda_device::thread::__internal::index_1d(&scope)
-/// ```
-///
-/// Bare-ident calls are the only shape that can't carry a prefix, so for
-/// those we fall back to the absolute path (the user wasn't naming
-/// anything to import; see the bare-ident case in `is_thread_index_path`'s
-/// doc-comment for why we still rewrite those):
-///
-/// ```text
-/// index_1d()                           →  ::cuda_device::thread::__internal::index_1d(&scope)
-/// ```
-fn internal_thread_path(
-    user_path: &Path,
-    name: &str,
-    arguments: syn::PathArguments,
-    call_span: proc_macro2::Span,
-) -> Path {
-    let ident = Ident::new(name, call_span);
-    let internal = Ident::new("__internal", call_span);
-
-    if user_path.segments.len() == 1 {
-        let mut absolute: Path =
-            parse_quote_spanned! { call_span => ::cuda_device::thread::#internal::#ident };
-        if let Some(last) = absolute.segments.last_mut() {
-            last.arguments = arguments;
-        }
-        return absolute;
-    }
-
-    let leading_colon = user_path.leading_colon;
-    let prefix_segments: Vec<&syn::PathSegment> = user_path
-        .segments
-        .iter()
-        .take(user_path.segments.len() - 1)
-        .collect();
-    let mut rewritten: Path = parse_quote_spanned! {
-        call_span => #leading_colon #(#prefix_segments)::* :: #internal :: #ident
-    };
-    if let Some(last) = rewritten.segments.last_mut() {
-        last.arguments = arguments;
-    }
-    rewritten
-}
-
-/// One scoped intrinsic the rewriter knows about.
-///
-/// Adding a new `thread::*` function that needs the `'kernel` scope is a
-/// one-line entry here, plus the matching public stub and `__internal::*`
-/// impl in `cuda-device`.
-struct ScopedIntrinsic {
-    /// The unqualified function name (last segment of the path we match).
-    name: &'static str,
-    /// If true, copy the call-site's turbofish onto the rewritten path
-    /// (e.g. `index_2d::<S>` → `__internal::index_2d::<S>`).
-    preserve_turbofish: bool,
-    /// If true, forward the original call arguments after the scope ref
-    /// (e.g. `index_2d_runtime(s)` → `__internal::index_2d_runtime(&scope, s)`).
-    forward_args: bool,
-}
-
-const SCOPED_INTRINSICS: &[ScopedIntrinsic] = &[
-    ScopedIntrinsic {
-        name: "index_1d",
-        preserve_turbofish: false,
-        forward_args: false,
-    },
-    ScopedIntrinsic {
-        name: "index_2d",
-        preserve_turbofish: true,
-        forward_args: false,
-    },
-    ScopedIntrinsic {
-        name: "index_2d_runtime",
-        preserve_turbofish: false,
-        forward_args: true,
-    },
-    ScopedIntrinsic {
-        name: "warp_index",
-        preserve_turbofish: false,
-        forward_args: false,
-    },
-];
-
-/// Method names whose zero-arg call sites get the kernel scope spliced in
-/// as a leading `&scope` argument.
-///
-/// These are matched on the *method name only* (not the receiver type, which
-/// the macro can't see anyway). The scope is only injected when the user
-/// wrote a zero-arg call like `slice.get_mut_indexed()`; if they passed
-/// arguments themselves, we leave the call alone and let typeck decide.
-///
-/// Same caveat as `SCOPED_INTRINSICS`: a local method on an unrelated type
-/// with the same name and a zero-arg form will get the scope appended,
-/// which will cause a typeck error ("expected 0 arguments, got 1"). Pick
-/// a different name (e.g. `pop_indexed`) for any helper you want to keep.
-const SCOPED_METHODS: &[&str] = &["get_mut_indexed"];
-
-fn is_scoped_method(method: &Ident) -> bool {
-    SCOPED_METHODS.iter().any(|name| method == name)
-}
-
-struct ThreadIndexCallRewriter {
-    scope_ident: Ident,
-    borrow_scope: bool,
-    rewrote_index_call: bool,
-}
-
-fn ident_located_at(ident: &Ident, location: proc_macro2::Span) -> Ident {
-    let mut relocated = ident.clone();
-    relocated.set_span(ident.span().located_at(location));
-    relocated
-}
-
-impl VisitMut for ThreadIndexCallRewriter {
-    fn visit_expr_mut(&mut self, expr: &mut Expr) {
-        visit_mut::visit_expr_mut(self, expr);
-
-        match expr {
-            Expr::Call(call) => {
-                let call_span = call.span();
-                let ExprCall { func, args, .. } = call;
-                let Expr::Path(ExprPath { path, .. }) = &mut **func else {
-                    return;
-                };
-                let Some(intrinsic) = SCOPED_INTRINSICS
-                    .iter()
-                    .find(|i| is_thread_index_path(path, i.name))
-                else {
-                    return;
-                };
-
-                let last_args = path
-                    .segments
-                    .last()
-                    .map(|seg| seg.arguments.clone())
-                    .unwrap_or(syn::PathArguments::None);
-                let path_args = if intrinsic.preserve_turbofish {
-                    last_args
-                } else {
-                    syn::PathArguments::None
-                };
-                *path = internal_thread_path(path, intrinsic.name, path_args, call_span);
-                // Keep the binding's name-resolution hygiene, but make this
-                // generated reference part of the user's indexing expression
-                // for diagnostics and line-table purposes.
-                let scope_ident = ident_located_at(&self.scope_ident, call_span);
-                let scope_arg: Expr = if self.borrow_scope {
-                    parse_quote_spanned! { call_span => &#scope_ident }
-                } else {
-                    parse_quote_spanned! { call_span => #scope_ident }
-                };
-
-                if intrinsic.forward_args {
-                    args.insert(0, scope_arg);
-                } else {
-                    args.clear();
-                    args.push(scope_arg);
-                }
-                self.rewrote_index_call = true;
-            }
-            Expr::MethodCall(method_call) => {
-                let call_span = method_call.span();
-                let ExprMethodCall { method, args, .. } = method_call;
-                if !is_scoped_method(method) || !args.is_empty() {
-                    return;
-                }
-                let scope_ident = ident_located_at(&self.scope_ident, call_span);
-                if self.borrow_scope {
-                    args.push(parse_quote_spanned! { call_span => &#scope_ident });
-                } else {
-                    args.push(parse_quote_spanned! { call_span => #scope_ident });
-                }
-                self.rewrote_index_call = true;
-            }
-            _ => {}
-        }
-    }
-}
-
-#[derive(Clone)]
-struct RewrittenKernelScope {
-    ident: Ident,
-    domain: TokenStream2,
-    coordinates: TokenStream2,
-}
-
-fn rewrite_thread_index_calls(
-    input: &mut ItemFn,
-    borrow_scope: bool,
-) -> Option<RewrittenKernelScope> {
-    // Keep the ordinary call-site span so borrow-checker diagnostics continue
-    // to point at the user's `#[kernel]` / `#[device]` item. Only rename the
-    // binding when a generic parameter has deliberately taken the usual name.
-    let scope_ident = call_site_ident_avoiding_item(KERNEL_SCOPE_LOCAL, input);
-    if !rewrite_thread_index_calls_with_scope(input, &scope_ident, borrow_scope) {
-        return None;
-    }
-
-    Some(kernel_scope_spec(input, scope_ident))
-}
-
-fn rewrite_thread_index_calls_with_scope(
-    input: &mut ItemFn,
-    scope_ident: &Ident,
-    borrow_scope: bool,
-) -> bool {
-    let mut rewriter = ThreadIndexCallRewriter {
-        scope_ident: scope_ident.clone(),
-        borrow_scope,
-        rewrote_index_call: false,
-    };
-    rewriter.visit_block_mut(&mut input.block);
-    rewriter.rewrote_index_call
-}
-
-fn kernel_scope_spec(input: &ItemFn, ident: Ident) -> RewrittenKernelScope {
-    let (domain, coordinates) = kernel_scope_marker_types(input);
-    RewrittenKernelScope {
-        ident,
-        domain,
-        coordinates,
-    }
-}
-
-fn explicit_kernel_scope(input: &mut ItemFn, ident: Ident) -> RewrittenKernelScope {
-    // Legacy helpers still receive the same capability, but only their
-    // established names are rewritten. The new fast functions are ordinary
-    // Rust calls that take this reference explicitly.
-    rewrite_thread_index_calls_with_scope(input, &ident, false);
-    kernel_scope_spec(input, ident)
-}
-
-fn kernel_scope_binding(scope: &RewrittenKernelScope) -> Stmt {
-    let RewrittenKernelScope {
-        ident,
-        domain,
-        coordinates,
-    } = scope;
-    parse_quote! {
-        let #ident = unsafe {
-            ::cuda_device::thread::__internal::make_kernel_scope::<#domain, #coordinates>()
-        };
-    }
-}
-
-fn explicit_kernel_scope_bindings(scope: &RewrittenKernelScope) -> Vec<Stmt> {
-    let RewrittenKernelScope {
-        ident,
-        domain,
-        coordinates,
-    } = scope;
-    // Def-site-like hygiene keeps this generated storage binding distinct
-    // from any source binding with the same text. Both its declaration and
-    // reference are emitted by this one proc-macro expansion.
-    let storage = Ident::new(
-        &format!("{KERNEL_SCOPE_LOCAL}_storage"),
-        proc_macro2::Span::mixed_site(),
-    );
-    vec![
-        parse_quote! {
-            let #storage = unsafe {
-                ::cuda_device::thread::__internal::make_kernel_scope::<#domain, #coordinates>()
-            };
-        },
-        parse_quote! {
-            let #ident: ::cuda_device::thread::LaunchContextRef<'_, #domain, #coordinates> =
-                &#storage;
-        },
-    ]
-}
-
-fn append_kernel_scope_parameter(input: &mut ItemFn, scope: &RewrittenKernelScope) {
-    let RewrittenKernelScope {
-        ident,
-        domain,
-        coordinates,
-    } = scope;
-    input.sig.inputs.push(parse_quote! {
-        #ident: ::cuda_device::thread::LaunchContextRef<'_, #domain, #coordinates>
-    });
-}
-
-fn inject_thread_index_scope(input: &mut ItemFn) {
-    if let Some(scope) = rewrite_thread_index_calls(input, true) {
-        input.block.stmts.insert(0, kernel_scope_binding(&scope));
-    }
-}
-
-fn inject_device_thread_index_scope(input: &mut ItemFn) {
-    let Some(mut scope) = rewrite_thread_index_calls(input, true) else {
-        return;
-    };
-    // A device helper has no host preparation boundary of its own. It may use
-    // checked legacy witnesses, but it cannot mint a contract-backed fast
-    // witness; callers must pass that witness or a checked view explicitly.
-    scope.domain = quote! { ::cuda_device::thread::__internal::UnknownDomain };
-    scope.coordinates = quote! { ::cuda_device::thread::__internal::NativeCoordinates };
-    input.block.stmts.insert(0, kernel_scope_binding(&scope));
-}
-
-fn kernel_scope_marker_types(input: &ItemFn) -> (TokenStream2, TokenStream2) {
-    let contract = input
-        .attrs
-        .iter()
-        .find(|attr| attr_path_ends_with(attr, "launch_contract"))
-        .and_then(|attr| attr.parse_args::<LaunchContractArgs>().ok())
-        .map(|args| (args.domain, args.u32_coordinates))
-        .or_else(|| {
-            input
-                .block
-                .stmts
-                .iter()
-                .find_map(launch_contract_marker_values)
-        });
-
-    let (domain, u32_coordinates) = contract.unwrap_or((0, false));
-    let domain = match domain {
-        1 => quote! { ::cuda_device::thread::__internal::Domain1 },
-        2 => quote! { ::cuda_device::thread::__internal::Domain2 },
-        3 => quote! { ::cuda_device::thread::__internal::Domain3 },
-        _ => quote! { ::cuda_device::thread::__internal::UnknownDomain },
-    };
-    let coordinates = if u32_coordinates {
-        quote! { ::cuda_device::thread::__internal::U32Coordinates }
-    } else {
-        quote! { ::cuda_device::thread::__internal::NativeCoordinates }
-    };
-    (domain, coordinates)
-}
-
-fn launch_contract_marker_values(statement: &Stmt) -> Option<(u8, bool)> {
-    let (call, unsafe_wrapped) = configuration_marker_call(statement)?;
-    if !unsafe_wrapped {
-        return None;
-    }
-    if !call.args.is_empty() {
-        return None;
-    }
-    let Expr::Path(ExprPath {
-        qself: None, path, ..
-    }) = &*call.func
-    else {
-        return None;
-    };
-    let segments: Vec<_> = path.segments.iter().collect();
-    if path.leading_colon.is_none()
-        || segments.len() != 3
-        || segments[0].ident != "cuda_device"
-        || segments[1].ident != "thread"
-        || segments[2].ident != "__launch_contract_config"
-    {
-        return None;
-    }
-    let PathArguments::AngleBracketed(arguments) = &segments[2].arguments else {
-        return None;
-    };
-    let mut arguments = arguments.args.iter();
-    let GenericArgument::Const(Expr::Lit(domain)) = arguments.next()? else {
-        return None;
-    };
-    let syn::Lit::Int(domain) = &domain.lit else {
-        return None;
-    };
-    let GenericArgument::Const(Expr::Lit(coordinates)) = arguments.next()? else {
-        return None;
-    };
-    let syn::Lit::Bool(coordinates) = &coordinates.lit else {
-        return None;
-    };
-    if arguments.next().is_some() {
-        return None;
-    }
-    Some((domain.base10_parse().ok()?, coordinates.value))
-}
-
-fn configuration_marker_call(statement: &Stmt) -> Option<(&ExprCall, bool)> {
-    match statement {
-        Stmt::Expr(Expr::Call(call), Some(_semicolon)) => Some((call, false)),
-        Stmt::Expr(Expr::Unsafe(unsafe_block), _) if unsafe_block.block.stmts.len() == 1 => {
-            let Stmt::Expr(Expr::Call(call), Some(_semicolon)) = &unsafe_block.block.stmts[0]
-            else {
-                return None;
-            };
-            Some((call, true))
-        }
-        _ => None,
-    }
-}
-
-/// Return compiler configuration markers already materialized in a generic
-/// kernel body by attributes that expanded before `#[kernel]`.
-///
-/// Only exact, zero-argument calls to cuda-oxide's internal marker paths are
-/// forwarded. The launch-contract marker additionally retains its generated
-/// `unsafe` boundary. Nested calls and unrelated top-level calls remain solely
-/// in the helper body.
-fn top_level_kernel_configuration_markers(input: &ItemFn) -> Vec<Stmt> {
-    input
-        .block
-        .stmts
-        .iter()
-        .filter(|statement| is_kernel_configuration_marker(statement))
-        .cloned()
-        .collect()
-}
-
-fn is_kernel_configuration_marker(statement: &Stmt) -> bool {
-    let Some((call, unsafe_wrapped)) = configuration_marker_call(statement) else {
-        return false;
-    };
-    if !call.args.is_empty() {
-        return false;
-    }
-    let Expr::Path(ExprPath {
-        qself: None, path, ..
-    }) = &*call.func
-    else {
-        return false;
-    };
-    let segments: Vec<_> = path.segments.iter().collect();
-    if path.leading_colon.is_none()
-        || segments.len() != 3
-        || segments[0].ident != "cuda_device"
-        || !matches!(segments[0].arguments, PathArguments::None)
-        || !matches!(segments[1].arguments, PathArguments::None)
-        || !matches!(segments[2].arguments, PathArguments::AngleBracketed(_))
-    {
-        return false;
-    }
-
-    let module = &segments[1].ident;
-    let marker = &segments[2].ident;
-    if unsafe_wrapped {
-        module == "thread" && marker == "__launch_contract_config"
-    } else {
-        (module == "thread"
-            && (marker == "__launch_bounds_config"
-                || marker == "__launch_contract_block_config"
-                || marker == "__unchecked_indexing_config"))
-            || (module == "cluster" && marker == "__cluster_config")
-            || (module == "shared" && marker == "__dynamic_shared_alignment")
-    }
-}
-
-/// True when `statement` is exactly the `__unchecked_indexing_config` marker
-/// call that `#[kernel(unchecked_indexing)]` injects.
-fn is_unchecked_indexing_config_marker(statement: &Stmt) -> bool {
-    if !is_kernel_configuration_marker(statement) {
-        return false;
-    }
-    let Some((call, _)) = configuration_marker_call(statement) else {
-        return false;
-    };
-    let Expr::Path(ExprPath { path, .. }) = &*call.func else {
-        return false;
-    };
-    path.segments
-        .last()
-        .is_some_and(|segment| segment.ident == "__unchecked_indexing_config")
-}
-
-/// Remove the `__unchecked_indexing_config` marker from a function body that
-/// is about to be re-emitted as the user-named implementation helper of a
-/// generic kernel.
-///
-/// The marker may only live in generated kernel ENTRY functions (the
-/// `cuda_oxide_*kernel*`-prefixed symbols); the entry wrapper receives it via
-/// `top_level_kernel_configuration_markers`. The helper is ordinary callable
-/// Rust: if the marker stayed in its body, rustc's MIR inliner could splice
-/// it into a different, non-opted kernel that calls the helper, and the MIR
-/// importer would then elide that caller's bounds checks body-wide without
-/// any opt-in. Stripping is fail-closed: if the helper is ever not
-/// MIR-inlined into its own entry wrapper, the helper body simply keeps its
-/// bounds checks.
-fn strip_unchecked_indexing_config_marker(input: &mut ItemFn) {
-    input
-        .block
-        .stmts
-        .retain(|statement| !is_unchecked_indexing_config_marker(statement));
-}
-
-/// Build the hidden unchecked twin of an opted-in generic kernel's
-/// implementation, returning the identifier the generated entry wrapper must
-/// call plus the emitted item.
-///
-/// `input` must already have the marker stripped (it is the exact body that
-/// becomes the user-named helper); the clone re-inserts the marker as its
-/// first statement.
-///
-/// Why a clone at all: the device pipeline translates the
-/// `#[inline(always)]` implementation as its own device function (LLVM
-/// inlines it into the entry later), so a marker on the entry wrapper alone
-/// cannot elide the implementation body's bounds checks, and a marker left
-/// in the user-named helper leaks elision into every other kernel that calls
-/// the helper. The clone carries the marker instead. It is private,
-/// `#[doc(hidden)]`, and named with a def-site (hygienic) identifier, so the
-/// generated `cuda_oxide_*kernel*` entry wrapper of this same expansion is
-/// its only possible caller: bounds-check elision stays confined to launches
-/// of the opted kernel, and the user-named helper keeps every bounds check.
-fn unchecked_indexing_impl_clone(
-    input: &ItemFn,
-    helper_attrs: &[syn::Attribute],
-) -> (Ident, TokenStream2) {
-    // `Display` of a raw identifier keeps its `r#` prefix (e.g. `r#gen`),
-    // which `Ident::new` rejects; strip it like `format_ident!` would.
-    let implementation_name = input.sig.ident.to_string();
-    let implementation_name = implementation_name
-        .strip_prefix("r#")
-        .unwrap_or(&implementation_name);
-    let clone_name = internal_ident(&format!(
-        "__cuda_oxide_unchecked_impl_{implementation_name}"
-    ));
-    let mut clone_fn = input.clone();
-    clone_fn.sig.ident = clone_name.clone();
-    clone_fn.vis = syn::Visibility::Inherited;
-    // The twin's body is byte-identical to the user-named helper's, so it
-    // carries the same routed attributes (cfg gates, lint levels such as
-    // `#[allow]`/`#[expect]`, deprecation): a lint the author suppressed on
-    // the helper must not re-fire on the twin. Entry directives and
-    // `#[inline]` were already routed away by `route_generic_kernel_attrs`.
-    clone_fn.attrs = helper_attrs.to_vec();
-    let marker_call: Stmt = parse_quote! {
-        ::cuda_device::thread::__unchecked_indexing_config::<true>();
-    };
-    clone_fn.block.stmts.insert(0, marker_call);
-    let tokens = quote! {
-        /// Hidden unchecked twin of the kernel implementation. Only the
-        /// generated kernel entry calls it; its marker elides bounds checks
-        /// solely for launches of the opted kernel.
-        #[doc(hidden)]
-        #[inline(always)]
-        #[allow(non_snake_case)]
-        #clone_fn
-    };
-    (clone_name, tokens)
-}
-
-/// Generate a generic kernel that will be instantiated from call sites (nvcc-style)
-fn generate_generic_kernel_no_instantiation(
-    input: ItemFn,
-    explicit_scope: Option<Ident>,
-) -> TokenStream {
-    generic_kernel_no_instantiation_tokens(input, explicit_scope).into()
-}
-
-/// Expansion body of [`generate_generic_kernel_no_instantiation`], split out
-/// so unit tests can inspect the generated items without a live proc-macro
-/// bridge.
-fn generic_kernel_no_instantiation_tokens(
-    mut input: ItemFn,
-    explicit_scope: Option<Ident>,
-) -> TokenStream2 {
-    let entry_inputs = input.sig.inputs.clone();
-    // A routed `#[launch_contract]` expands later on the generated entry
-    // wrapper, whose synthetic parameter names cannot resolve source-level
-    // `requires` identifiers, so those relations are validated here while the
-    // original signature is still in scope.
-    if let Err(error) = validate_routed_launch_contract_requires(&input.attrs, &entry_inputs) {
-        return error.to_compile_error();
-    }
-    let has_explicit_scope = explicit_scope.is_some();
-    let rewritten_scope = if let Some(ident) = explicit_scope {
-        Some(explicit_kernel_scope(&mut input, ident))
-    } else {
-        rewrite_thread_index_calls(&mut input, false)
-    };
-    if let Some(scope) = &rewritten_scope {
-        append_kernel_scope_parameter(&mut input, scope);
-    }
-
-    // Attributes written below `#[kernel]` still belong to the source item
-    // when this macro runs. Route CUDA entry directives to the generated entry
-    // function, keep ordinary Rust attributes on the user-facing
-    // implementation, and copy cfg gates to every generated item.
-    let (implementation_attrs, entry_attrs, cfg_attrs) = route_generic_kernel_attrs(&input.attrs);
-    let entry_config_markers = top_level_kernel_configuration_markers(&input);
-    // The unchecked-indexing marker may only live in generated kernel entry
-    // functions and their hidden unchecked twin, never in the user-named
-    // implementation helper: a marker left in the helper would extend
-    // bounds-check elision to every other kernel that calls (and inlines)
-    // the helper, without those kernels opting in.
-    let unchecked_indexing = input
-        .block
-        .stmts
-        .iter()
-        .any(is_unchecked_indexing_config_marker);
-    if unchecked_indexing {
-        strip_unchecked_indexing_config_marker(&mut input);
-    }
-    let unchecked_impl =
-        unchecked_indexing.then(|| unchecked_indexing_impl_clone(&input, &implementation_attrs));
-    // The entry calls the hidden twin, so a private opted kernel's user-named
-    // helper may otherwise be dead code; it stays emitted (bounds-checked)
-    // for other device code to call.
-    let helper_dead_code = if unchecked_indexing {
-        quote! { #[allow(dead_code)] }
-    } else {
-        quote! {}
-    };
-    let fn_name = &input.sig.ident;
-    let vis = &input.vis;
-    let generics = &input.sig.generics;
-    let where_clause = &input.sig.generics.where_clause;
-    let inputs = &input.sig.inputs;
-    let output = &input.sig.output;
-    let constness = &input.sig.constness;
-    let unsafety = &input.sig.unsafety;
-    let abi = &input.sig.abi;
-    let block = &input.block;
-
-    let kernel_name = format_ident!("{}{}", KERNEL_PREFIX, fn_name);
-    let instantiate_name = format_ident!("{}{}", INSTANTIATE_PREFIX, fn_name);
-
-    let (wrapper_inputs, arg_names) = match forwarding_inputs(&entry_inputs) {
-        Ok(forwarding) => forwarding,
-        Err(err) => return err.to_compile_error(),
-    };
-    let args_info: Vec<_> = arg_names
-        .iter()
-        .zip(entry_inputs.iter())
-        .filter_map(|(name, arg)| {
-            let FnArg::Typed(pat_type) = arg else {
-                return None;
-            };
-            Some((name, &*pat_type.ty))
-        })
-        .collect();
-
-    // Find the closure generic type (looks for Fn/FnMut/FnOnce bounds)
-    let closure_generic = find_closure_generic(generics);
-
-    // Function turbofish arguments contain both types and consts in source
-    // order. Lifetimes are inferred and therefore do not appear here.
-    let codegen_args = codegen_generic_arguments(generics);
-    let kernel_turbofish = if codegen_args.is_empty() {
-        quote! {}
-    } else {
-        quote! { ::<#(#codegen_args),*> }
-    };
-    let ptx_name_fn = format_ident!("{}_ptx_name", fn_name);
-    let instantiate_helper = if let Some(closure_type_name) = closure_generic {
-        if let Some((_closure_idx, (_closure_name, closure_type))) =
-            find_closure_param(&args_info, &closure_type_name)
-        {
-            quote! {
-                /// Auto-generated helper to force kernel monomorphization.
-                ///
-                /// Takes the closure by *reference* so its anonymous type
-                /// is bound to the generic parameter `F` at the call site
-                /// without moving the closure — the caller still needs the
-                /// closure value to push as the kernel argument right
-                /// after. Then forces rustc to emit a CGU entry for the
-                /// concrete `#kernel_name::<...>` instantiation. Returns
-                /// the PTX export name produced by the kernel's
-                /// `GenericCudaKernel::ptx_name()` impl, which is the
-                /// single source of truth for the on-wire name on the
-                /// host side.
-                ///
-                /// Bound is intentionally not `'static`: closures that
-                /// borrow non-`'static` data (e.g. capture `&[T]`) still
-                /// monomorphize cleanly. The caller is responsible for
-                /// keeping that borrow alive across the asynchronous
-                /// launch — `cuda_host::type_id_u128` does not enforce
-                /// this.
-                #[doc(hidden)]
-                #(#cfg_attrs)*
-                #[inline(never)]
-                #vis fn #instantiate_name #generics (_: &#closure_type) -> &'static str #where_clause {
-                    #ptx_name_fn #kernel_turbofish ()
-                }
-            }
-        } else {
-            quote! {}
-        }
-    } else {
-        quote! {}
-    };
-
-    // Generate the GenericCudaKernel trait implementation for unified compilation
-    let generic_cuda_kernel_impl =
-        generate_generic_cuda_kernel_impl(fn_name, vis, generics, where_clause, &cfg_attrs);
-    let mut implementation_args: Vec<TokenStream2> =
-        arg_names.iter().map(|name| quote! { #name }).collect();
-    if let Some(scope) = &rewritten_scope {
-        let scope_ident = &scope.ident;
-        if has_explicit_scope {
-            implementation_args.push(quote! { #scope_ident });
-        } else {
-            implementation_args.push(quote! { &#scope_ident });
-        }
-    }
-    let scope_bindings = rewritten_scope
-        .as_ref()
-        .map(|scope| {
-            if has_explicit_scope {
-                explicit_kernel_scope_bindings(scope)
-            } else {
-                vec![kernel_scope_binding(scope)]
-            }
-        })
-        .unwrap_or_default();
-    // An opted-in kernel's entry calls the hidden unchecked twin; everyone
-    // else (user code included) calls the user-named, bounds-checked helper.
-    let (implementation_target, unchecked_impl_item) = match &unchecked_impl {
-        Some((clone_name, tokens)) => (quote! { #clone_name }, tokens.clone()),
-        None => (quote! { #fn_name }, quote! {}),
-    };
-    let implementation_call =
-        quote! { #implementation_target #kernel_turbofish (#(#implementation_args),*) };
-    let implementation_call = if unsafety.is_some() {
-        quote! { unsafe { #implementation_call } }
-    } else {
-        implementation_call
-    };
-
-    quote! {
-        // Original generic kernel implementation
-        #(#implementation_attrs)*
-        #helper_dead_code
-        #[inline(always)]
-        #vis #constness #unsafety #abi fn #fn_name #generics (#inputs) #output #where_clause
-        #block
-
-        #unchecked_impl_item
-
-        // Entry point for collector - NOT inlined so we can detect it
-        // When called with concrete types, this instantiates the kernel
-        // Synthetic wrapper parameter names make every irrefutable source
-        // pattern forwardable without carrying local binding `mut`.
-        #(#entry_attrs)*
-        #[inline(never)]
-        #vis #constness #unsafety #abi fn #kernel_name #generics (#(#wrapper_inputs),*) #output #where_clause {
-            #(#entry_config_markers)*
-            #(#scope_bindings)*
-            #implementation_call
-        }
-
-        #instantiate_helper
-
-        #generic_cuda_kernel_impl
-    }
-}
-
-/// Route attributes when one generic source function becomes several items.
-///
-/// CUDA entry directives must decorate the generated collector entry, not the
-/// inline implementation helper. Configuration gates must decorate every item
-/// to avoid leaving a marker or helper behind for a disabled kernel. Other
-/// user-facing attributes (documentation, lints, deprecation, etc.) stay on
-/// the implementation with the original Rust name.
-fn route_generic_kernel_attrs(
-    attrs: &[syn::Attribute],
-) -> (
-    Vec<syn::Attribute>,
-    Vec<syn::Attribute>,
-    Vec<syn::Attribute>,
-) {
-    let is_cfg = |attr: &syn::Attribute| {
-        attr_path_ends_with(attr, "cfg") || attr_path_ends_with(attr, "cfg_attr")
-    };
-    let is_entry_directive = |attr: &syn::Attribute| {
-        attr_path_ends_with(attr, "launch_bounds")
-            || attr_path_ends_with(attr, "launch_contract")
-            || attr_path_ends_with(attr, "cluster_launch")
-            || attr_path_ends_with(attr, "cooperative_launch")
-    };
-
-    let cfg_attrs = attrs.iter().filter(|attr| is_cfg(attr)).cloned().collect();
-    let implementation_attrs = attrs
-        .iter()
-        .filter(|attr| !is_entry_directive(attr) && !attr_path_ends_with(attr, "inline"))
-        .cloned()
-        .collect();
-    let entry_attrs = attrs
-        .iter()
-        .filter(|attr| is_cfg(attr) || is_entry_directive(attr))
-        .cloned()
-        .collect();
-
-    (implementation_attrs, entry_attrs, cfg_attrs)
-}
-
-/// Generate a dummy binding for a given type.
-/// Used by instantiate! helper to create zero-valued arguments.
-///
-/// The generated values are never actually executed - they exist only to force
-/// rustc to monomorphize the kernel with the correct types.
-fn _generate_dummy_binding(name: &Ident, ty: &Type) -> TokenStream2 {
-    match ty {
-        // Special case: &[T] or &mut [T] → empty slice literal
-        // (slices don't implement Default and can't be safely zeroed)
-        Type::Reference(type_ref) if matches!(&*type_ref.elem, Type::Slice(_)) => {
-            if let Type::Slice(slice) = &*type_ref.elem {
-                let elem_ty = &slice.elem;
-                if type_ref.mutability.is_some() {
-                    quote! { let #name: &mut [#elem_ty] = &mut []; }
-                } else {
-                    quote! { let #name: &[#elem_ty] = &[]; }
-                }
-            } else {
-                unreachable!()
-            }
-        }
-
-        // Everything else: use mem::zeroed()
-        // Safe because this code never actually runs - it only exists to
-        // force monomorphization of the kernel with the correct types.
-        _ => {
-            quote! { let #name: #ty = unsafe { core::mem::zeroed() }; }
-        }
-    }
-}
-
-/// Generate a simple non-generic kernel
-fn generate_simple_kernel(mut input: ItemFn, explicit_scope: Option<Ident>) -> TokenStream {
-    if let Some(ident) = explicit_scope {
-        let scope = explicit_kernel_scope(&mut input, ident);
-        let bindings = explicit_kernel_scope_bindings(&scope);
-        input.block.stmts.splice(0..0, bindings);
-    } else {
-        inject_thread_index_scope(&mut input);
-    }
-
-    let fn_name = input.sig.ident.clone();
-    let new_name = format_ident!("{}{}", KERNEL_PREFIX, fn_name);
-
-    // Clone the original function for the CudaKernel impl
-    let original_fn = input.clone();
-    input.sig.ident = new_name;
-
-    // PTX entry name is the unprefixed user name; the collector strips
-    // KERNEL_PREFIX when generating PTX.
-    let ptx_entry_name = fn_name.to_string();
-
-    // Generate the CudaKernel trait implementation (host-side only)
-    // This provides the PTX name for cuda_launch! to look up
-    let cuda_kernel_impl = generate_cuda_kernel_impl(
-        &fn_name,
-        &ptx_entry_name,
-        &original_fn,
-        cfg!(feature = "host"),
-    );
-
-    let expanded = quote! {
-        #[unsafe(no_mangle)]
-        #input
-
-        #cuda_kernel_impl
-    };
-
-    TokenStream::from(expanded)
-}
-
-/// Generate the GenericCudaKernel trait implementation for a generic kernel.
-///
-/// For generic kernels like `fn tile<T, const N: usize>()`, emits:
-///
-/// ```ignore
-/// pub struct __tile_CudaKernel<T, const N: usize>(PhantomData<*const T>);
-/// impl<T, const N: usize> GenericCudaKernel for __tile_CudaKernel<T, N> {
-///     fn ptx_name() -> &'static str {
-///         // "tile_TID_<hex32>" — one 32-char hash of the concrete
-///         // generated kernel function-item type.
-///     }
-/// }
-/// pub fn tile_ptx_name<T, const N: usize>() -> &'static str {
-///     // Retains `kernel_entry::<T, N>` and delegates to the marker above.
-/// }
-/// ```
-///
-/// The body computes the same string the backend writes into the PTX:
-/// `<base>_TID_<hex32>`, where `<hex32>` is
-/// `cuda_host::type_id_u128_of_val(&kernel_entry::<T, N>)` rendered as 32
-/// lowercase hex chars. The backend hashes the same concrete `FnDef` type,
-/// whose ordered generic arguments include both types and const values.
-///
-/// Bound on the impl is `where_clause` verbatim — typically `Copy` on
-/// each value-passed generic. We deliberately do not add `'static`:
-/// `type_id_u128` has bound `T: ?Sized`, so closure types that borrow
-/// non-`'static` data still satisfy the marker's bounds and can be
-/// launched through the typed `module.<kernel>(...)` path. Keeping the
-/// borrow alive across `stream.synchronize()` remains the caller's
-/// responsibility, exactly as it was under the previous `type_name`
-/// scheme.
-///
-/// Deliberately NOT gated by the `host` feature: generic kernels remain
-/// host-coupled by design for now, because the TypeId naming machinery
-/// lives in `cuda_host`.
-fn generate_generic_cuda_kernel_impl(
-    fn_name: &Ident,
-    vis: &syn::Visibility,
-    generics: &syn::Generics,
-    where_clause: &Option<syn::WhereClause>,
-    cfg_attrs: &[syn::Attribute],
-) -> TokenStream2 {
-    let marker_name = format_ident!("__{}_CudaKernel", fn_name);
-    let ptx_name_fn = format_ident!("{}_ptx_name", fn_name);
-    let kernel_name = format_ident!("{}{}", KERNEL_PREFIX, fn_name);
-    let base_name = fn_name.to_string();
-    let generic_params: Vec<_> = generics.params.iter().collect();
-    let marker_args = generic_arguments(generics);
-    let codegen_args = codegen_generic_arguments(generics);
-    let phantom_type = generic_phantom_type(generics);
-    let marker_type = if marker_args.is_empty() {
-        quote! { #marker_name }
-    } else {
-        quote! { #marker_name <#(#marker_args),*> }
-    };
-    let kernel_turbofish = if codegen_args.is_empty() {
-        quote! {}
-    } else {
-        quote! { ::<#(#codegen_args),*> }
-    };
-    let (impl_generics, _, _) = generics.split_for_impl();
-    let hash = internal_ident("__cuda_oxide_kernel_hash");
-    let kernel_ptr = internal_ident("__cuda_oxide_kernel_ptr");
-    let force_mono = internal_ident("__cuda_oxide_force_mono");
-
-    quote! {
-        /// Marker type for a generic kernel; implements `GenericCudaKernel`.
-        /// Its generic parameters mirror the kernel's generic parameters.
-        #(#cfg_attrs)*
-        #[doc(hidden)]
-        #[allow(non_camel_case_types)]
-        pub struct #marker_name<#(#generic_params),*>(
-            core::marker::PhantomData<#phantom_type>
-        ) #where_clause;
-
-        #(#cfg_attrs)*
-        impl #impl_generics ::cuda_host::GenericCudaKernel for #marker_type
-        #where_clause
-        {
-            fn ptx_name() -> &'static str {
-                let #hash = ::cuda_host::type_id_u128_of_val(
-                    &#kernel_name #kernel_turbofish
-                );
-                ::cuda_host::__intern_generic_kernel_name(#base_name, #hash)
-            }
-        }
-
-        /// Retains this concrete kernel specialization and returns its PTX entry name.
-        #(#cfg_attrs)*
-        #[inline(never)]
-        #vis fn #ptx_name_fn #generics () -> &'static str #where_clause {
-            let #kernel_ptr = #kernel_name #kernel_turbofish as *const ();
-            unsafe {
-                let mut #force_mono: *const () = ::core::ptr::null();
-                ::core::ptr::write_volatile(&mut #force_mono, #kernel_ptr);
-                let _ = ::core::ptr::read_volatile(&#force_mono);
-            }
-            <#marker_type as ::cuda_host::GenericCudaKernel>::ptx_name()
-        }
-    }
-}
-
-/// Generate the CudaKernel trait implementation for a kernel function.
-///
-/// This generates a marker struct that implements `CudaKernel`, allowing
-/// `cuda_launch!` to look up the PTX entry point name at compile time.
-///
-/// Emitted only under the `host` feature: the impl names `cuda_host`, and a
-/// crate that only compiles kernels never looks a PTX entry name up.
-fn generate_cuda_kernel_impl(
-    fn_name: &Ident,
-    ptx_name: &str,
-    _func: &ItemFn,
-    emit_host: bool,
-) -> TokenStream2 {
-    if !emit_host {
-        return TokenStream2::new();
-    }
-
-    // Create a marker struct for this kernel
-    // We use a struct because Rust doesn't allow trait impls on function pointers easily
-    let marker_name = format_ident!("__{}_CudaKernel", fn_name);
-
-    quote! {
-        /// Marker type for the kernel, implements CudaKernel trait.
-        /// This enables cuda_launch! to look up the PTX entry point name.
-        #[doc(hidden)]
-        #[allow(non_camel_case_types)]
-        pub struct #marker_name;
-
-        impl cuda_host::CudaKernel for #marker_name {
-            const PTX_NAME: &'static str = #ptx_name;
-        }
-    }
-}
-
-/// Generate wrapper kernels for a generic kernel
-fn generate_generic_kernel(
-    input: ItemFn,
-    instantiate_types: Vec<Type>,
-    explicit_scope: Option<Ident>,
-) -> TokenStream {
-    generic_kernel_instantiation_tokens(input, instantiate_types, explicit_scope).into()
-}
-
-/// Expansion body of [`generate_generic_kernel`] (legacy `#[kernel(Type, ...)]`
-/// instantiation), split out so unit tests can inspect the generated items
-/// without a live proc-macro bridge.
-fn generic_kernel_instantiation_tokens(
-    mut input: ItemFn,
-    instantiate_types: Vec<Type>,
-    explicit_scope: Option<Ident>,
-) -> TokenStream2 {
-    let entry_inputs = input.sig.inputs.clone();
-    // Same as the no-instantiation path: `requires` relations of a routed
-    // `#[launch_contract]` must be validated against the source parameter
-    // names before they are lost to the generated wrappers.
-    if let Err(error) = validate_routed_launch_contract_requires(&input.attrs, &entry_inputs) {
-        return error.to_compile_error();
-    }
-    let has_explicit_scope = explicit_scope.is_some();
-    let rewritten_scope = if let Some(ident) = explicit_scope {
-        Some(explicit_kernel_scope(&mut input, ident))
-    } else {
-        rewrite_thread_index_calls(&mut input, false)
-    };
-    if let Some(scope) = &rewritten_scope {
-        append_kernel_scope_parameter(&mut input, scope);
-    }
-
-    let (implementation_attrs, entry_attrs, _cfg_attrs) = route_generic_kernel_attrs(&input.attrs);
-    let entry_config_markers = top_level_kernel_configuration_markers(&input);
-    input.attrs.clear();
-    // Same containment rule as the no-instantiation path: the marker never
-    // stays in the re-emitted user-named helper; opted entries call a hidden
-    // unchecked twin instead.
-    let unchecked_indexing = input
-        .block
-        .stmts
-        .iter()
-        .any(is_unchecked_indexing_config_marker);
-    if unchecked_indexing {
-        strip_unchecked_indexing_config_marker(&mut input);
-    }
-    let unchecked_impl =
-        unchecked_indexing.then(|| unchecked_indexing_impl_clone(&input, &implementation_attrs));
-    // The wrappers call the hidden twin, so a private opted kernel's
-    // user-named helper may otherwise be dead code; it stays emitted
-    // (bounds-checked) for other device code to call.
-    let helper_dead_code = if unchecked_indexing {
-        quote! { #[allow(dead_code)] }
-    } else {
-        quote! {}
-    };
-    let fn_name = &input.sig.ident;
-    let vis = &input.vis;
-    let generics = &input.sig.generics;
-    let (implementation_target, unchecked_impl_item) = match &unchecked_impl {
-        Some((clone_name, tokens)) => (quote! { #clone_name }, tokens.clone()),
-        None => (quote! { #fn_name }, quote! {}),
-    };
-
-    // Extract the type parameter name (assume single type param for now)
-    let type_param = generics
-        .params
-        .iter()
-        .find_map(|p| {
-            if let GenericParam::Type(tp) = p {
-                Some(&tp.ident)
-            } else {
-                None
-            }
-        })
-        .expect("Expected type parameter");
-
-    // Extract function arguments (excluding self)
-    let args: Vec<_> = entry_inputs.iter().collect();
-
-    // Build the argument pattern and types for wrappers
-    let arg_names: Vec<TokenStream2> = args
-        .iter()
-        .filter_map(|arg| {
-            if let FnArg::Typed(pat_type) = arg
-                && let Pat::Ident(pat_ident) = &*pat_type.pat
-            {
-                return Some(quote! { #pat_ident });
-            }
-            None
-        })
-        .collect();
-
-    // For each instantiation type, generate a wrapper that substitutes the type
-    let wrappers: Vec<TokenStream2> = instantiate_types
-        .iter()
-        .map(|inst_type| {
-            let entry_attrs = &entry_attrs;
-            let entry_config_markers = &entry_config_markers;
-            let implementation_target = &implementation_target;
-            // Get a clean name for the type (for the kernel name suffix)
-            let type_name = get_type_name(inst_type);
-            let wrapper_name = format_ident!("{}{}_{}", KERNEL_PREFIX, fn_name, type_name);
-
-            // Export name (what appears in PTX)
-            let export_name_str = format!("{}_{}", fn_name, type_name);
-            let scope_bindings = rewritten_scope
-                .as_ref()
-                .map(|scope| {
-                    if has_explicit_scope {
-                        explicit_kernel_scope_bindings(scope)
-                    } else {
-                        vec![kernel_scope_binding(scope)]
-                    }
-                })
-                .unwrap_or_default();
-            let mut implementation_args = arg_names.clone();
-            if let Some(scope) = &rewritten_scope {
-                let scope_ident = &scope.ident;
-                if has_explicit_scope {
-                    implementation_args.push(quote! { #scope_ident });
-                } else {
-                    implementation_args.push(quote! { &#scope_ident });
-                }
-            }
-
-            // Generate wrapper function args with substituted types
-            let wrapper_args: Vec<TokenStream2> = args
-                .iter()
-                .map(|arg| {
-                    if let FnArg::Typed(pat_type) = arg {
-                        let pat = &pat_type.pat;
-                        let ty = &pat_type.ty;
-                        // Substitute type parameter with concrete type
-                        let subst_ty = substitute_type(ty, type_param, inst_type);
-                        quote! { #pat: #subst_ty }
-                    } else {
-                        quote! { #arg }
-                    }
-                })
-                .collect();
-
-            quote! {
-                #(#entry_attrs)*
-                #[unsafe(no_mangle)]
-                #[unsafe(export_name = #export_name_str)]
-                #vis fn #wrapper_name(#(#wrapper_args),*) {
-                    #(#entry_config_markers)*
-                    #(#scope_bindings)*
-                    #implementation_target::<#inst_type>(#(#implementation_args),*);
-                }
-            }
-        })
-        .collect();
-
-    // Keep the original generic function (without #[no_mangle] - it's not an entry point)
-    // and add all the wrapper kernels
-    quote! {
-        #(#implementation_attrs)*
-        #helper_dead_code
-        #[inline(always)]
-        #input
-
-        #unchecked_impl_item
-
-        #(#wrappers)*
-    }
-}
-
-/// Get a clean name from a type for use in function names
-fn get_type_name(ty: &Type) -> String {
-    match ty {
-        Type::Path(type_path) => {
-            // Get the last segment (e.g., "Scale" from "crate::Scale")
-            type_path
-                .path
-                .segments
-                .last()
-                .map(|s| s.ident.to_string())
-                .unwrap_or_else(|| "Unknown".to_string())
-        }
-        _ => "Unknown".to_string(),
-    }
-}
-
-/// Substitute a type parameter with a concrete type in a type expression
-fn substitute_type(ty: &Type, param: &syn::Ident, replacement: &Type) -> TokenStream2 {
-    match ty {
-        Type::Path(type_path) => {
-            // Check if this is just the type parameter
-            if type_path.path.is_ident(param) {
-                return quote! { #replacement };
-            }
-            quote! { #ty }
-        }
-        Type::Reference(type_ref) => {
-            let elem = substitute_type(&type_ref.elem, param, replacement);
-            let lifetime = &type_ref.lifetime;
-            let mutability = &type_ref.mutability;
-            quote! { &#lifetime #mutability #elem }
-        }
-        _ => quote! { #ty },
-    }
+/// Mark a module-scope `static` as a CUDA constant-memory global.
+///
+/// The static must be typed `ConstantMemory<T>` (see
+/// [`cuda_device::ConstantMemory`](../../cuda_device/struct.ConstantMemory.html)). The
+/// `ConstantMemory<T>` wrapper has `UnsafeCell<T>` semantics on the device,
+/// preventing the compiler from constant-folding the initializer and making
+/// the host's `cuMemcpyHtoD` updates observable from kernels.
+///
+/// The macro adds a reserved `#[unsafe(export_name = "cuda_oxide_const_246e25db_...")]`
+/// so the PTX symbol carries a name the host can resolve via
+/// `cuModuleGetGlobal`. When used inside `#[cuda_module]`, the generated name
+/// includes module/source-location context to avoid collisions between constants
+/// that share the same Rust identifier. The host-side `#[cuda_module]` expansion
+/// separately generates per-constant setter methods on the loaded module:
+///
+/// - `module.set_<name>(&stream, &value)` — stream-ordered async write
+///   (recommended; orders correctly against surrounding kernel launches).
+/// - `module.set_<name>_blocking(&value)` — synchronous `cuMemcpyHtoD`
+///   for one-shot initialization where no stream is in scope.
+///
+/// # Restrictions
+///
+/// - The static must be typed `ConstantMemory<T>`.
+/// - The initializer must be `ConstantMemory::UNINIT` (or any other all-zeros
+///   value). Honoring arbitrary non-zero initializers is not yet
+///   implemented; populate from the host before any kernel reads the value.
+/// - The attribute must appear inside a `#[cuda_module]`. Placed elsewhere
+///   it silently produces an unreachable symbol (no setter is generated).
+/// - The identifier must not start with the reserved cuda-oxide prefix.
+///
+/// # Example
+///
+/// ```ignore
+/// #[cuda_module]
+/// mod kernels {
+///     #[constant]
+///     static COEFFS: ConstantMemory<[f32; 4]> = ConstantMemory::UNINIT;
+///
+///     #[kernel]
+///     pub fn compute(mut out: DisjointSlice<f32>) {
+///         let c = COEFFS.get();
+///         let i = thread::index_1d().get();
+///         if let Some(e) = out.get_mut(thread::index_1d()) {
+///             *e = c[0] * (i as f32) + c[1];
+///         }
+///     }
+/// }
+///
+/// // Host
+/// module.set_coeffs(&stream, &[1.0, 2.0, 3.0, 4.0])?;
+/// ```
+#[proc_macro_attribute]
+pub fn constant(attr: TokenStream, item: TokenStream) -> TokenStream {
+    device::constant_entry(attr, item)
 }
 
 /// Specifies launch bounds for a kernel (max threads per block, min blocks per SM).
@@ -5918,27 +539,7 @@ fn substitute_type(ty: &Type, param: &syn::Ident, replacement: &Type) -> TokenSt
 /// ```
 #[proc_macro_attribute]
 pub fn launch_bounds(attr: TokenStream, item: TokenStream) -> TokenStream {
-    let args: LaunchBoundsArgs = parse_macro_input!(attr as LaunchBoundsArgs);
-    let mut input = parse_macro_input!(item as ItemFn);
-
-    let max_threads = &args.max_threads.expr;
-    let min_blocks = &args.min_blocks.expr;
-
-    add_const_evaluatable_bound(&mut input.sig.generics, &args.max_threads);
-    add_const_evaluatable_bound(&mut input.sig.generics, &args.min_blocks);
-
-    // Inject the launch bounds config marker at the start of the function body
-    let marker_call: syn::Stmt = syn::parse_quote! {
-        ::cuda_device::thread::__launch_bounds_config::<{ #max_threads }, { #min_blocks }>();
-    };
-
-    // Prepend the marker to the function body
-    input.block.stmts.insert(0, marker_call);
-
-    quote! {
-        #input
-    }
-    .into()
+    launch_attrs::launch_bounds_entry(attr, item)
 }
 
 /// Declares the host launch geometry and resource contract for a kernel.
@@ -6055,484 +656,7 @@ pub fn launch_bounds(attr: TokenStream, item: TokenStream) -> TokenStream {
 /// `#[launch_bounds]` would otherwise contribute.
 #[proc_macro_attribute]
 pub fn launch_contract(attr: TokenStream, item: TokenStream) -> TokenStream {
-    let args = parse_macro_input!(attr as LaunchContractArgs);
-    let mut input = parse_macro_input!(item as ItemFn);
-
-    // Validate `requires` here too, so a standalone contract (outside any
-    // #[cuda_module]) rejects typos and bad grammar at the attribute site
-    // instead of silently dropping the relations. Inside a #[cuda_module]
-    // the module macro validates first against the source signature; a
-    // module-level rejection replaces the whole module with the error, so
-    // this attribute never expands there and the two validations cannot
-    // stack duplicate diagnostics.
-    if !args.requires.is_empty()
-        && let Some(params) = standalone_requires_params(&input)
-        && let Err(error) = validate_requires_relations(&args.requires, &params)
-    {
-        return error.to_compile_error().into();
-    }
-
-    inject_launch_contract_markers(&args, &mut input);
-
-    quote! { #input }.into()
-}
-
-/// Best-effort parameter model for validating `requires` relations on the
-/// function the `launch_contract` attribute macro receives.
-///
-/// Returns `None` when the function is a macro-generated generic entry
-/// wrapper: its parameters carry synthetic `__cuda_oxide_arg_*` names, so
-/// source-level relation identifiers cannot be resolved against it. Those
-/// relations were already validated against the source signature, either by
-/// the `#[cuda_module]` expansion or by `#[kernel]`'s generic routing (see
-/// [`validate_routed_launch_contract_requires`]). Parameter shapes the
-/// module marshaller rejects, reachable only outside `#[cuda_module]`, are
-/// modelled as opaque scalars: referencing one in `requires` then fails with
-/// the precise grammar error rather than a misleading "unknown identifier".
-fn standalone_requires_params(item_fn: &ItemFn) -> Option<Vec<CudaModuleParam>> {
-    requires_params_from_inputs(&item_fn.sig.inputs)
-}
-
-/// Shared core of [`standalone_requires_params`], usable with a saved copy
-/// of a kernel's original inputs before scope parameters are appended or
-/// wrapper signatures are synthesized.
-fn requires_params_from_inputs(
-    inputs: &syn::punctuated::Punctuated<FnArg, syn::token::Comma>,
-) -> Option<Vec<CudaModuleParam>> {
-    let mut params = Vec::new();
-    for arg in inputs {
-        let FnArg::Typed(pat_type) = arg else {
-            continue;
-        };
-        let Pat::Ident(pat_ident) = &*pat_type.pat else {
-            continue;
-        };
-        if pat_ident.ident.to_string().starts_with("__cuda_oxide_arg_") {
-            return None;
-        }
-        let ty = &pat_type.ty;
-        let param = cuda_module_param_from_typed(pat_type).unwrap_or_else(|_| CudaModuleParam {
-            name: pat_ident.ident.clone(),
-            sync_host_ty: quote! { #ty },
-            async_host_ty: quote! { #ty },
-            marshal: CudaModuleParamMarshal::Scalar,
-            mutable_slice: false,
-            disjoint_slice_ty: None,
-            disjoint_slice_elem: None,
-            uniform_ty: None,
-            uniform_scalar: None,
-            scalar_int: scalar_int_class(ty),
-        });
-        params.push(param);
-    }
-    Some(params)
-}
-
-/// Validate the `requires` relations of any `#[launch_contract]` attribute
-/// that `#[kernel]` is about to route onto a generated generic entry
-/// wrapper.
-///
-/// The wrapper's parameters carry synthetic `__cuda_oxide_arg_*` names, so
-/// when the attribute macro finally expands there it cannot resolve
-/// source-level identifiers and deliberately stands down (see
-/// [`standalone_requires_params`]). Without this check, a typo'd relation on
-/// a standalone generic kernel would compile clean while the identical
-/// non-generic kernel errors. Malformed argument lists are skipped here: the
-/// attribute macro reports those itself when it expands.
-fn validate_routed_launch_contract_requires(
-    attrs: &[syn::Attribute],
-    source_inputs: &syn::punctuated::Punctuated<FnArg, syn::token::Comma>,
-) -> syn::Result<()> {
-    for attr in attrs {
-        if !attr_path_ends_with(attr, "launch_contract") {
-            continue;
-        }
-        let Ok(args) = attr.parse_args::<LaunchContractArgs>() else {
-            continue;
-        };
-        if args.requires.is_empty() {
-            continue;
-        }
-        if let Some(params) = requires_params_from_inputs(source_inputs) {
-            validate_requires_relations(&args.requires, &params)?;
-        }
-    }
-    Ok(())
-}
-
-fn inject_launch_contract_markers(args: &LaunchContractArgs, input: &mut ItemFn) {
-    let domain = args.domain;
-    let u32_coordinates = args.u32_coordinates;
-    let contract_marker: syn::Stmt = parse_quote! {
-        unsafe {
-            ::cuda_device::thread::__launch_contract_config::<#domain, #u32_coordinates>();
-        }
-    };
-    input.block.stmts.insert(0, contract_marker);
-    let mut next = 1;
-
-    // Give the exact block shape to the device compiler as well, so ptxas
-    // emits `.reqntid` and the driver rejects a mismatched block on every
-    // axis. Without this the shape is known only to the host check.
-    if let Some((x, y, z)) = args.exact_block {
-        let block_marker: syn::Stmt = parse_quote! {
-            ::cuda_device::thread::__launch_contract_block_config::<#x, #y, #z>();
-        };
-        input.block.stmts.insert(next, block_marker);
-        next += 1;
-    }
-
-    if dynamic_shared_max(args.dynamic_shared) != 0 {
-        let alignment = args.dynamic_shared_alignment as usize;
-        let alignment_marker: syn::Stmt = parse_quote! {
-            ::cuda_device::shared::__dynamic_shared_alignment::<#alignment>();
-        };
-        input.block.stmts.insert(next, alignment_marker);
-    }
-}
-
-/// Arguments for `#[launch_bounds(...)]` attribute.
-#[derive(Clone)]
-struct LaunchBoundsArgs {
-    max_threads: ConstU32Expr,
-    min_blocks: ConstU32Expr,
-}
-
-impl Parse for LaunchBoundsArgs {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        let args: Punctuated<Expr, Token![,]> = Punctuated::parse_terminated(input)?;
-        let values = args
-            .into_iter()
-            .map(ConstU32Expr::new)
-            .collect::<syn::Result<Vec<_>>>()?;
-
-        match values.len() {
-            1 => {
-                let max_threads = values.into_iter().next().unwrap();
-                validate_literal_max_threads(&max_threads)?;
-                Ok(LaunchBoundsArgs {
-                    max_threads,
-                    min_blocks: ConstU32Expr::literal(0),
-                })
-            }
-            2 => {
-                let mut values = values.into_iter();
-                let max_threads = values.next().unwrap();
-                let min_blocks = values.next().unwrap();
-                validate_literal_max_threads(&max_threads)?;
-                Ok(LaunchBoundsArgs {
-                    max_threads,
-                    min_blocks,
-                })
-            }
-            _ => Err(syn::Error::new(
-                input.span(),
-                "launch_bounds expects 1 or 2 parameters: #[launch_bounds(max_threads)] or #[launch_bounds(max_threads, min_blocks)]",
-            )),
-        }
-    }
-}
-
-/// A source expression whose expected type is `u32` at the generated marker.
-///
-/// Literal values are retained for early source-time diagnostics. Every other
-/// expression stays as typed Rust syntax: rustc, not this procedural macro,
-/// resolves associated constants and arithmetic for both device metadata and
-/// each monomorphized host launch contract.
-#[derive(Clone)]
-struct ConstU32Expr {
-    expr: Expr,
-    literal_value: Option<u32>,
-}
-
-impl ConstU32Expr {
-    fn new(expr: Expr) -> syn::Result<Self> {
-        let literal_value = match &expr {
-            Expr::Lit(expr_lit) => match &expr_lit.lit {
-                syn::Lit::Int(value) => Some(value.base10_parse::<u32>()?),
-                _ => None,
-            },
-            _ => None,
-        };
-        Ok(Self {
-            expr,
-            literal_value,
-        })
-    }
-
-    fn literal(value: u32) -> Self {
-        Self {
-            expr: parse_quote! { #value },
-            literal_value: Some(value),
-        }
-    }
-}
-
-fn validate_literal_max_threads(value: &ConstU32Expr) -> syn::Result<()> {
-    if value.literal_value == Some(0) {
-        Err(syn::Error::new_spanned(
-            &value.expr,
-            "launch_bounds maximum threads must be greater than zero",
-        ))
-    } else {
-        Ok(())
-    }
-}
-
-/// Returns whether an expression names one of the function's type or const
-/// parameters and therefore needs a signature-level evaluatability witness.
-///
-/// Non-generic paths deliberately return false. In particular, a const item
-/// declared inside the function body is in scope at the generated marker but
-/// is not in scope in the function signature.
-fn const_expr_depends_on_generics(expr: &Expr, generics: &syn::Generics) -> bool {
-    let generic_names: Vec<&Ident> = generics
-        .params
-        .iter()
-        .filter_map(|parameter| match parameter {
-            GenericParam::Type(parameter) => Some(&parameter.ident),
-            GenericParam::Const(parameter) => Some(&parameter.ident),
-            GenericParam::Lifetime(_) => None,
-        })
-        .collect();
-    if generic_names.is_empty() {
-        return false;
-    }
-
-    struct GenericReference<'a> {
-        generic_names: &'a [&'a Ident],
-        found: bool,
-    }
-
-    impl<'ast> Visit<'ast> for GenericReference<'_> {
-        fn visit_path(&mut self, path: &'ast Path) {
-            if path.segments.iter().any(|segment| {
-                self.generic_names
-                    .iter()
-                    .any(|generic| segment.ident == **generic)
-            }) {
-                self.found = true;
-                return;
-            }
-            visit::visit_path(self, path);
-        }
-    }
-
-    let mut visitor = GenericReference {
-        generic_names: &generic_names,
-        found: false,
-    };
-    visitor.visit_expr(expr);
-    visitor.found
-}
-
-/// Make a generic constant expression evaluatable at each monomorphization.
-///
-/// rustc requires this bound for expressions such as `P::MAX_THREADS`. The
-/// marker itself supplies the expected `u32` type; the array length is only an
-/// evaluatability witness and never reaches device code.
-fn add_const_evaluatable_bound(generics: &mut syn::Generics, value: &ConstU32Expr) {
-    if value.literal_value.is_some() || !const_expr_depends_on_generics(&value.expr, generics) {
-        return;
-    }
-    let expr = &value.expr;
-    let predicate: syn::WherePredicate = parse_quote! {
-        [(); (#expr) as usize]:
-    };
-    generics.make_where_clause().predicates.push(predicate);
-}
-
-fn add_launch_bounds_evaluatability_from_attrs(input: &mut ItemFn) -> syn::Result<()> {
-    let matching: Vec<_> = input
-        .attrs
-        .iter()
-        .filter(|attr| attr_path_ends_with(attr, "launch_bounds"))
-        .collect();
-    if matching.len() > 1 {
-        return Err(syn::Error::new_spanned(
-            matching[1],
-            "a kernel may have only one launch_bounds attribute",
-        ));
-    }
-    let Some(attr) = matching.first() else {
-        return Ok(());
-    };
-    let bounds = attr.parse_args::<LaunchBoundsArgs>()?;
-    let max_threads = bounds.max_threads.clone();
-    let min_blocks = bounds.min_blocks.clone();
-    add_const_evaluatable_bound(&mut input.sig.generics, &max_threads);
-    add_const_evaluatable_bound(&mut input.sig.generics, &min_blocks);
-    Ok(())
-}
-
-/// Arguments for the `#[unroll]` / `#[unroll(N)]` attribute.
-///
-/// Bare `#[unroll]` parses to factor `0` (full unroll); `#[unroll(N)]` requires
-/// `N >= 2`.
-struct UnrollArgs {
-    factor: ConstU32Expr,
-}
-
-impl Parse for UnrollArgs {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        // Bare `#[unroll]` => full unroll (factor 0).
-        if input.is_empty() {
-            return Ok(UnrollArgs {
-                factor: ConstU32Expr::literal(0),
-            });
-        }
-
-        let args: Punctuated<Expr, Token![,]> = Punctuated::parse_terminated(input)?;
-        let mut values = args
-            .into_iter()
-            .map(ConstU32Expr::new)
-            .collect::<syn::Result<Vec<_>>>()?;
-
-        match values.len() {
-            1 => {
-                let factor = values.pop().unwrap();
-                match factor.literal_value {
-                    Some(0 | 1) => Err(syn::Error::new_spanned(
-                        &factor.expr,
-                        "partial unroll factor must be at least 2; use #[unroll] for full unrolling",
-                    )),
-                    Some(value) if value > 1024 => Err(syn::Error::new_spanned(
-                        &factor.expr,
-                        "partial unroll factor cannot exceed 1024",
-                    )),
-                    _ => Ok(UnrollArgs { factor }),
-                }
-            }
-            _ => Err(syn::Error::new(
-                input.span(),
-                "unroll expects no argument (full unroll) or one factor: #[unroll] or #[unroll(N)]",
-            )),
-        }
-    }
-}
-
-/// `VisitMut` pass that consumes `#[unroll]` / `#[unroll(N)]` attributes written
-/// directly on loops inside a `#[kernel]` (or `#[device]`) function body.
-///
-/// This mirrors how CubeCL's `#[cube]` macro handles per-loop `#[unroll]`: the
-/// enclosing function macro owns the whole body AST, so it can strip the inner
-/// attribute and lower it into a marker BEFORE rustc ever sees it. That keeps us
-/// off the nightly `stmt_expr_attributes` feature (rustc otherwise rejects
-/// attributes on expressions).
-///
-/// For every `for` / `while` / `loop` expression carrying an outer `#[unroll]`
-/// attribute, the visitor:
-///
-/// 1. removes the `unroll` attribute from the loop expr's `attrs`, and
-/// 2. inserts `cuda_device::thread::__unroll_config::<FACTOR>();` as the FIRST
-///    statement of that loop's body block.
-///
-/// `FACTOR` follows [`UnrollArgs`]: bare `#[unroll]` => `0` (full unroll),
-/// `#[unroll(N)]` => `N`. The importer reads the marker from the block it lands
-/// in, so the request applies to that loop only.
-///
-/// The visitor recurses through nested blocks/loops/ifs via the default
-/// `visit_mut` traversal, so an annotated loop anywhere in the function is
-/// handled. Loops without an `#[unroll]` attribute are left untouched, so a
-/// kernel with no per-loop annotations expands byte-identically to before.
-#[derive(Default)]
-struct LoopUnrollAttrVisitor {
-    /// First parse error encountered (e.g. a malformed `#[unroll(...)]`). The
-    /// caller surfaces this as a compile error.
-    error: Option<syn::Error>,
-    const_expressions: Vec<ConstU32Expr>,
-}
-
-impl LoopUnrollAttrVisitor {
-    /// If `attrs` contains an outer `#[unroll]` / `#[unroll(N)]`, remove it and
-    /// return the parsed factor. Returns `None` when no `unroll` attribute is
-    /// present (leaving `attrs` untouched). Records a parse error and returns
-    /// `None` if the attribute is malformed.
-    fn take_unroll_factor(&mut self, attrs: &mut Vec<syn::Attribute>) -> Option<ConstU32Expr> {
-        let idx = attrs
-            .iter()
-            .position(|attr| attr.path().is_ident("unroll"))?;
-        let attr = attrs.remove(idx);
-
-        // `#[unroll]` (bare) is `Meta::Path`; `#[unroll(N)]` is `Meta::List`.
-        let factor = match &attr.meta {
-            syn::Meta::Path(_) => ConstU32Expr::literal(0),
-            syn::Meta::List(list) => match list.parse_args::<UnrollArgs>() {
-                Ok(parsed) => parsed.factor,
-                Err(err) => {
-                    if self.error.is_none() {
-                        self.error = Some(err);
-                    }
-                    return None;
-                }
-            },
-            syn::Meta::NameValue(_) => {
-                if self.error.is_none() {
-                    self.error = Some(syn::Error::new_spanned(
-                        &attr,
-                        "unroll expects no argument (full unroll) or one factor: #[unroll] or #[unroll(N)]",
-                    ));
-                }
-                return None;
-            }
-        };
-        if factor.literal_value.is_none() {
-            self.const_expressions.push(factor.clone());
-        }
-        Some(factor)
-    }
-
-    /// Build the `__unroll_config::<FACTOR>()` marker statement.
-    fn marker_stmt(factor: &ConstU32Expr) -> Stmt {
-        let expr = &factor.expr;
-        parse_quote! {
-            cuda_device::thread::__unroll_config::<{ #expr }>();
-        }
-    }
-}
-
-impl VisitMut for LoopUnrollAttrVisitor {
-    fn visit_expr_mut(&mut self, expr: &mut Expr) {
-        // Pull the unroll factor (if any) off this loop expr and inject the
-        // marker into its body. We act only on loop expressions; everything
-        // else falls through to the default recursion below.
-        match expr {
-            Expr::ForLoop(for_loop) => {
-                if let Some(factor) = self.take_unroll_factor(&mut for_loop.attrs) {
-                    for_loop.body.stmts.insert(0, Self::marker_stmt(&factor));
-                }
-            }
-            Expr::While(while_loop) => {
-                if let Some(factor) = self.take_unroll_factor(&mut while_loop.attrs) {
-                    while_loop.body.stmts.insert(0, Self::marker_stmt(&factor));
-                }
-            }
-            Expr::Loop(loop_expr) => {
-                if let Some(factor) = self.take_unroll_factor(&mut loop_expr.attrs) {
-                    loop_expr.body.stmts.insert(0, Self::marker_stmt(&factor));
-                }
-            }
-            _ => {}
-        }
-
-        // Recurse into nested expressions/blocks so annotated loops nested
-        // inside other loops, `if`s, or blocks are also handled.
-        visit_mut::visit_expr_mut(self, expr);
-    }
-}
-
-/// Consume per-loop unroll annotations in a kernel or device function and
-/// replace them with the marker calls understood by the MIR importer.
-fn rewrite_loop_unroll_attrs(input: &mut ItemFn) -> syn::Result<()> {
-    let mut visitor = LoopUnrollAttrVisitor::default();
-    visitor.visit_block_mut(&mut input.block);
-    if let Some(err) = visitor.error {
-        return Err(err);
-    }
-    for expression in &visitor.const_expressions {
-        add_const_evaluatable_bound(&mut input.sig.generics, expression);
-    }
-    Ok(())
+    launch_attrs::launch_contract_entry(attr, item)
 }
 
 /// Specifies compile-time cluster dimensions for a kernel.
@@ -6594,64 +718,7 @@ fn rewrite_loop_unroll_attrs(input: &mut ItemFn) -> syn::Result<()> {
 /// | `cuLaunchKernelEx` (runtime) | Dynamic cluster sizes | Requires FFI, complex setup |
 #[proc_macro_attribute]
 pub fn cluster_launch(attr: TokenStream, item: TokenStream) -> TokenStream {
-    let args: ClusterArgs = parse_macro_input!(attr as ClusterArgs);
-    let mut input = parse_macro_input!(item as ItemFn);
-
-    let x = args.x;
-    let y = args.y;
-    let z = args.z;
-
-    // Inject the cluster config marker at the start of the function body
-    let marker_call: syn::Stmt = syn::parse_quote! {
-        ::cuda_device::cluster::__cluster_config::<#x, #y, #z>();
-    };
-
-    // Prepend the marker to the function body
-    input.block.stmts.insert(0, marker_call);
-
-    quote! {
-        #input
-    }
-    .into()
-}
-
-/// Arguments for `#[cluster_launch(...)]` attribute.
-struct ClusterArgs {
-    x: u32,
-    y: u32,
-    z: u32,
-}
-
-impl Parse for ClusterArgs {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        let args: Punctuated<syn::LitInt, Token![,]> = Punctuated::parse_terminated(input)?;
-        let values: Vec<u32> = args
-            .iter()
-            .map(|lit| lit.base10_parse::<u32>())
-            .collect::<Result<Vec<_>, _>>()?;
-
-        match values.len() {
-            1 => Ok(ClusterArgs {
-                x: values[0],
-                y: 1,
-                z: 1,
-            }),
-            2 => Ok(ClusterArgs {
-                x: values[0],
-                y: values[1],
-                z: 1,
-            }),
-            3 => Ok(ClusterArgs {
-                x: values[0],
-                y: values[1],
-                z: values[2],
-            }),
-            _ => Err(syn::Error::new_spanned(
-                args.first().unwrap(),
-                "cluster expects 1, 2, or 3 dimensions: #[cluster(x)], #[cluster(x, y)], or #[cluster(x, y, z)]",
-            )),
-        }
-    }
+    launch_attrs::cluster_launch_entry(attr, item)
 }
 
 /// Marks a kernel for cooperative launch (`CU_LAUNCH_ATTRIBUTE_COOPERATIVE`).
@@ -6700,23 +767,7 @@ impl Parse for ClusterArgs {
 /// macro offers the same behaviour through its `cooperative: true` field.
 #[proc_macro_attribute]
 pub fn cooperative_launch(attr: TokenStream, item: TokenStream) -> TokenStream {
-    if !attr.is_empty() {
-        return syn::Error::new(
-            proc_macro2::Span::call_site(),
-            "cooperative_launch takes no arguments: use a bare #[cooperative_launch]",
-        )
-        .to_compile_error()
-        .into();
-    }
-
-    // Launch-time only: the marker is consumed by #[cuda_module]; the kernel
-    // body and PTX are unchanged. Parse as a function so misuse on other
-    // items is rejected with a clear error.
-    let input = parse_macro_input!(item as ItemFn);
-    quote! {
-        #input
-    }
-    .into()
+    launch_attrs::cooperative_launch_entry(attr, item)
 }
 
 /// Marks a function as a CUDA device function.
@@ -6788,240 +839,7 @@ pub fn cooperative_launch(attr: TokenStream, item: TokenStream) -> TokenStream {
 /// ```
 #[proc_macro_attribute]
 pub fn device(_attr: TokenStream, item: TokenStream) -> TokenStream {
-    track_codegen_environment();
-    // Try parsing as a function definition first
-    if let Ok(input) = syn::parse::<ItemFn>(item.clone()) {
-        return generate_device_function(input);
-    }
-
-    // Try parsing as an extern block
-    if let Ok(input) = syn::parse::<ItemForeignMod>(item.clone()) {
-        return generate_device_extern_block(input);
-    }
-
-    // Neither worked - emit error
-    syn::Error::new_spanned(
-        proc_macro2::TokenStream::from(item),
-        "#[device] can only be applied to functions or extern blocks",
-    )
-    .to_compile_error()
-    .into()
-}
-
-/// Generate a device function definition.
-///
-/// Renames the function into the reserved `cuda_oxide_device_<hash>_` namespace
-/// for collector detection, and generates a thin wrapper with the original name
-/// so user code can call `my_func()` rather than the mangled internal symbol.
-///
-/// Handles both non-generic and generic device functions:
-/// - **Non-generic**: `#[no_mangle]` on the prefixed function, `#[inline(always)]` wrapper.
-/// - **Generic**: No `#[no_mangle]` (generics use mangled symbols), `#[inline(never)]` on
-///   the prefixed function (so monomorphizations appear in CGUs for the collector),
-///   `#[inline(always)]` wrapper with generics + turbofish forwarding.
-///
-/// This mirrors the pattern used by `#[kernel]` for generic kernels
-/// (see `generate_generic_kernel_no_instantiation`).
-fn generate_device_function(mut input: ItemFn) -> TokenStream {
-    if let Some(err) = reject_reserved_name(&input.sig.ident) {
-        return err;
-    }
-    if let Some(err) = impl_trait_parameter_error(&input, "device function") {
-        return err.to_compile_error().into();
-    }
-    if let Err(err) = rewrite_loop_unroll_attrs(&mut input) {
-        return err.to_compile_error().into();
-    }
-    inject_device_thread_index_scope(&mut input);
-
-    let fn_name = input.sig.ident.clone();
-    let vis = input.vis.clone();
-    let new_name = format_ident!("{}{}", DEVICE_PREFIX, fn_name);
-
-    // Type and const parameters both create device monomorphizations.
-    let has_generics = has_codegen_generics(&input.sig.generics);
-
-    let return_type = &input.sig.output;
-    let generics = &input.sig.generics;
-    let where_clause = &input.sig.generics.where_clause;
-    let constness = &input.sig.constness;
-    let unsafety = &input.sig.unsafety;
-    let abi = &input.sig.abi;
-
-    let (wrapper_inputs, params) = match forwarding_inputs(&input.sig.inputs) {
-        Ok(forwarding) => forwarding,
-        Err(err) => return err.to_compile_error().into(),
-    };
-
-    // Rename the original function with the prefix
-    input.sig.ident = new_name.clone();
-
-    if has_generics {
-        // Generic device function: mirrors the generic kernel pattern.
-        //
-        // - No #[no_mangle] — generic functions use mangled symbol names per
-        //   monomorphization (e.g., `cuda_oxide_device_<hash>_add::<f32>` gets a
-        //   unique mangled name). #[no_mangle] requires a single concrete symbol.
-        //
-        // - #[inline(never)] on the prefixed function — ensures each monomorphization
-        //   appears as a distinct CGU item so the collector can find it. If it were
-        //   inlined, the function would disappear from the CGU.
-        //
-        // - The wrapper forwards type parameters via turbofish:
-        //   `cuda_oxide_device_<hash>_add::<T>(a, b)`.
-
-        let codegen_args = codegen_generic_arguments(generics);
-        let turbofish = quote! { ::<#(#codegen_args),*> };
-        let call = quote! { #new_name #turbofish (#(#params),*) };
-        let call = if unsafety.is_some() {
-            quote! { unsafe { #call } }
-        } else {
-            call
-        };
-
-        let expanded = quote! {
-            #[inline(never)]
-            #input
-
-            /// Wrapper for the generic device function with the original name.
-            #[inline(always)]
-            #vis #constness #unsafety #abi fn #fn_name #generics (#(#wrapper_inputs),*) #return_type #where_clause {
-                #call
-            }
-        };
-
-        TokenStream::from(expanded)
-    } else {
-        let call = quote! { #new_name(#(#params),*) };
-        let call = if unsafety.is_some() {
-            quote! { unsafe { #call } }
-        } else {
-            call
-        };
-        // Non-generic device function: simple case.
-        let expanded = quote! {
-            #[unsafe(no_mangle)]
-            #input
-
-            /// Wrapper for the device function with the original name.
-            #[inline(always)]
-            #vis #constness #unsafety #abi fn #fn_name #generics (#(#wrapper_inputs),*) #return_type #where_clause {
-                #call
-            }
-        };
-
-        TokenStream::from(expanded)
-    }
-}
-
-/// Generate device extern block declarations (for FFI with external LTOIR).
-///
-/// For each function in the extern block:
-/// 1. Rename it into the reserved `cuda_oxide_device_extern_<hash>_` namespace
-///    (for collector detection)
-/// 2. Generate a wrapper function with the original name (for user code)
-///
-/// User code calls `foo()` while the collector sees the hash-suffixed reserved
-/// form. The `#[link_name]` attribute restores the original name in the binary
-/// so external LTOIR resolves correctly.
-fn generate_device_extern_block(mut input: ItemForeignMod) -> TokenStream {
-    // Device extern declarations use CUDA's C calling convention. Reject
-    // other Rust ABIs because their argument and return conventions may differ.
-    if input
-        .abi
-        .name
-        .as_ref()
-        .is_some_and(|name| name.value() != "C")
-    {
-        return syn::Error::new_spanned(
-            &input.abi,
-            "#[device] extern blocks must use `extern \"C\"`",
-        )
-        .to_compile_error()
-        .into();
-    }
-
-    let mut wrappers = Vec::new();
-
-    // Process each item in the extern block
-    for item in &mut input.items {
-        if let ForeignItem::Fn(foreign_fn) = item {
-            if let Some(err) = reject_reserved_name(&foreign_fn.sig.ident) {
-                return err;
-            }
-
-            // `...` is purely syntactic, so it can be refused here rather than
-            // in device codegen. That gives the user a span on the offending
-            // tokens instead of a signature-less error at final-binary codegen,
-            // and it also catches a variadic extern that is declared but never
-            // called -- the collector only registers externs reached from
-            // kernel MIR, so that one used to compile clean.
-            //
-            // The codegen rejection stays: the collector recognises device
-            // externs by their reserved name prefix, so a hand-written extern
-            // block never passes through this macro at all.
-            if let Some(variadic) = &foreign_fn.sig.variadic {
-                return syn::Error::new_spanned(variadic, "#[device] externs cannot be variadic")
-                    .to_compile_error()
-                    .into();
-            }
-
-            // Save original info for wrapper generation
-            let original_name = foreign_fn.sig.ident.clone();
-            let original_attrs = foreign_fn.attrs.clone();
-            let original_sig = foreign_fn.sig.clone();
-
-            let new_name = format_ident!("{}{}", DEVICE_EXTERN_PREFIX, original_name);
-            foreign_fn.sig.ident = new_name.clone();
-
-            // Store original name as link_name for the linker
-            let original_name_str = original_name.to_string();
-            foreign_fn.attrs.push(syn::parse_quote! {
-                #[doc(hidden)]
-            });
-            foreign_fn.attrs.push(syn::parse_quote! {
-                #[link_name = #original_name_str]
-            });
-
-            // Generate wrapper function with the original name. User code
-            // calls `foo()`; the wrapper forwards to the reserved internal
-            // symbol the macro just produced.
-            let params: Vec<_> = original_sig
-                .inputs
-                .iter()
-                .filter_map(|arg| {
-                    if let syn::FnArg::Typed(pat_type) = arg
-                        && let syn::Pat::Ident(pat_ident) = &*pat_type.pat
-                    {
-                        return Some(pat_ident.ident.clone());
-                    }
-                    None
-                })
-                .collect();
-
-            let return_type = &original_sig.output;
-            let inputs = &original_sig.inputs;
-
-            // Keep user's attributes (like #[convergent]) on the wrapper
-            let wrapper = quote! {
-                #(#original_attrs)*
-                #[inline(always)]
-                #[allow(non_snake_case)]
-                pub unsafe fn #original_name(#inputs) #return_type {
-                    #new_name(#(#params),*)
-                }
-            };
-            wrappers.push(wrapper);
-        }
-    }
-
-    let expanded = quote! {
-        #input
-
-        #(#wrappers)*
-    };
-
-    TokenStream::from(expanded)
+    device::device_entry(_attr, item)
 }
 
 // ============================================================================
@@ -7108,232 +926,22 @@ pub fn pure(_attr: TokenStream, item: TokenStream) -> TokenStream {
 ///
 /// ```ignore
 /// #[device]
-/// extern "C" {
-///     #[readonly]
-///     fn lookup_table(table: *const f32, idx: i32) -> f32;
-/// }
-/// ```
-///
-/// # Generated LLVM IR
-///
-/// ```llvm
-/// declare float @lookup_table(ptr, i32) #0
-/// attributes #0 = { nounwind readonly }
-/// ```
-#[proc_macro_attribute]
-pub fn readonly(_attr: TokenStream, item: TokenStream) -> TokenStream {
-    // Marker attribute - collector will read and apply LLVM readonly attribute
-    item
-}
-
-// ============================================================================
-// cuda_launch! Macro (unified compilation)
-// ============================================================================
-
-/// Try to extract closure from an expression.
-///
-/// Closure marshalling no longer needs per-capture extraction: the
-/// backend emits a single byval `.param` for the whole closure struct,
-/// and the host pushes one scalar. The closure literal is still parsed
-/// out of the launch args so the `instantiate_name` helper has a
-/// concrete `&F` to bind the kernel's generic closure type to.
-fn as_closure_expr(expr: &syn::Expr) -> Option<&syn::ExprClosure> {
-    match expr {
-        syn::Expr::Closure(closure) => Some(closure),
-        syn::Expr::Group(group) => as_closure_expr(&group.expr),
-        syn::Expr::Paren(paren) => as_closure_expr(&paren.expr),
-        _ => None,
-    }
-}
-
-/// Argument type for cuda_launch! - same as LaunchArg but renamed for clarity
-enum CudaLaunchArg {
-    /// Direct expression - passed via .arg()
-    Direct(syn::Expr),
-    /// Slice with explicit length - passed as ptr + len
-    SliceWithLen(syn::Expr),
-    /// Mutable slice with explicit length - passed as ptr + len
-    SliceMutWithLen(syn::Expr),
-    /// Closure expression. The closure value is pushed as a single byval
-    /// scalar argument; the backend emits a matching single .param entry
-    /// for aggregate kernel parameters. No per-capture decomposition.
-    Closure { closure_expr: syn::ExprClosure },
-}
-
-impl Parse for CudaLaunchArg {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        // Check for tagged arguments
-        if input.peek(Ident) {
-            let ident: Ident = input.fork().parse()?;
-            match ident.to_string().as_str() {
-                "slice" => {
-                    input.parse::<Ident>()?;
-                    let content;
-                    parenthesized!(content in input);
-                    let expr: syn::Expr = content.parse()?;
-                    return Ok(CudaLaunchArg::SliceWithLen(expr));
-                }
-                "slice_mut" => {
-                    input.parse::<Ident>()?;
-                    let content;
-                    parenthesized!(content in input);
-                    let expr: syn::Expr = content.parse()?;
-                    return Ok(CudaLaunchArg::SliceMutWithLen(expr));
-                }
-                // "move" keyword starts a move closure
-                "move" => {
-                    // Parse the full closure expression (move |args| body)
-                    let expr: syn::Expr = input.parse()?;
-                    if let Some(closure) = as_closure_expr(&expr) {
-                        return Ok(CudaLaunchArg::Closure {
-                            closure_expr: closure.clone(),
-                        });
-                    }
-                    // Not a closure, treat as direct expression
-                    return Ok(CudaLaunchArg::Direct(expr));
-                }
-                _ => {}
-            }
-        }
-
-        // Check for closure starting with `|` (non-move closure)
-        if input.peek(Token![|]) {
-            let expr: syn::Expr = input.parse()?;
-            if let Some(closure) = as_closure_expr(&expr) {
-                return Ok(CudaLaunchArg::Closure {
-                    closure_expr: closure.clone(),
-                });
-            }
-            // Shouldn't happen, but fallback to direct
-            return Ok(CudaLaunchArg::Direct(expr));
-        }
-
-        // Default: direct expression
-        let expr: syn::Expr = input.parse()?;
-
-        // Check if the parsed expression happens to be a closure
-        if let Some(closure) = as_closure_expr(&expr) {
-            return Ok(CudaLaunchArg::Closure {
-                closure_expr: closure.clone(),
-            });
-        }
-
-        Ok(CudaLaunchArg::Direct(expr))
-    }
-}
-
-/// Input for cuda_launch! macro
-struct CudaLaunchInput {
-    /// Kernel path - can be simple name or path with generics: `scale` or `scale::<f32>`
-    kernel: syn::Path,
-    stream: syn::Expr,
-    module: syn::Expr,
-    config: syn::Expr,
-    args: Vec<CudaLaunchArg>,
-    /// Optional cluster dimensions (x, y, z) for thread block cluster launches.
-    /// When present, uses `cuLaunchKernelEx` via `launch_cluster()` instead of `cuLaunchKernel`.
-    cluster_dim: Option<syn::Expr>,
-    /// Optional cooperative-launch flag. When `true`, the kernel is launched
-    /// via `cuLaunchKernelEx` with `CU_LAUNCH_ATTRIBUTE_COOPERATIVE = 1`,
-    /// which is required for `cuda_device::grid::sync()` to work.
-    cooperative: Option<syn::Expr>,
-}
-
-/// Return the generated sibling of a kernel while preserving its module path
-/// and explicit generic arguments.
-///
-/// For example, `kernels::map::<F, 4>` becomes
-/// `kernels::__map_CudaKernel::<F, 4>` when `sibling_name` is the marker name.
-fn kernel_sibling_path(kernel: &syn::Path, sibling_name: Ident) -> syn::Path {
-    let mut sibling = kernel.clone();
-    sibling
-        .segments
-        .last_mut()
-        .expect("kernel path must have segments")
-        .ident = sibling_name;
-    sibling
-}
-
-impl CudaLaunchInput {
-    /// Extract the base kernel name (without generics) and generic arguments
-    fn kernel_parts(&self) -> (Ident, Option<&syn::PathArguments>) {
-        let last_segment = self
-            .kernel
-            .segments
-            .last()
-            .expect("kernel path must have segments");
-        let base_name = last_segment.ident.clone();
-        let generics = match &last_segment.arguments {
-            syn::PathArguments::None => None,
-            args => Some(args),
-        };
-        (base_name, generics)
-    }
-
-    /// Check if this is a generic kernel (has type parameters)
-    fn is_generic(&self) -> bool {
-        self.kernel
-            .segments
-            .last()
-            .map(|seg| !matches!(seg.arguments, syn::PathArguments::None))
-            .unwrap_or(false)
-    }
-}
-
-impl Parse for CudaLaunchInput {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        let mut kernel = None;
-        let mut stream = None;
-        let mut module = None;
-        let mut config = None;
-        let mut args = Vec::new();
-        let mut cluster_dim = None;
-        let mut cooperative = None;
-
-        while !input.is_empty() {
-            let key: Ident = input.parse()?;
-            input.parse::<Token![:]>()?;
-
-            match key.to_string().as_str() {
-                "kernel" => kernel = Some(input.parse()?),
-                "stream" => stream = Some(input.parse()?),
-                "module" => module = Some(input.parse()?),
-                "config" => config = Some(input.parse()?),
-                "cluster_dim" => cluster_dim = Some(input.parse()?),
-                "cooperative" => cooperative = Some(input.parse()?),
-                "args" => {
-                    let content;
-                    bracketed!(content in input);
-                    if !content.is_empty() {
-                        let parsed: Punctuated<CudaLaunchArg, Token![,]> =
-                            Punctuated::parse_terminated(&content)?;
-                        args = parsed.into_iter().collect();
-                    }
-                }
-                _ => {
-                    return Err(syn::Error::new(
-                        key.span(),
-                        format!(
-                            "unknown field: {}. Expected: kernel, stream, module, config, cluster_dim, cooperative, args",
-                            key
-                        ),
-                    ));
-                }
-            }
-
-            let _ = input.parse::<Token![,]>();
-        }
-
-        Ok(CudaLaunchInput {
-            kernel: kernel.ok_or_else(|| syn::Error::new(input.span(), "missing 'kernel'"))?,
-            stream: stream.ok_or_else(|| syn::Error::new(input.span(), "missing 'stream'"))?,
-            module: module.ok_or_else(|| syn::Error::new(input.span(), "missing 'module'"))?,
-            config: config.ok_or_else(|| syn::Error::new(input.span(), "missing 'config'"))?,
-            args,
-            cluster_dim,
-            cooperative,
-        })
-    }
+/// extern "C" {
+///     #[readonly]
+///     fn lookup_table(table: *const f32, idx: i32) -> f32;
+/// }
+/// ```
+///
+/// # Generated LLVM IR
+///
+/// ```llvm
+/// declare float @lookup_table(ptr, i32) #0
+/// attributes #0 = { nounwind readonly }
+/// ```
+#[proc_macro_attribute]
+pub fn readonly(_attr: TokenStream, item: TokenStream) -> TokenStream {
+    // Marker attribute - collector will read and apply LLVM readonly attribute
+    item
 }
 
 /// Launch a CUDA kernel synchronously on a given stream. **Unsafe**: the
@@ -7424,372 +1032,6 @@ pub fn cuda_launch(input: TokenStream) -> TokenStream {
     expand_cuda_launch(input).into()
 }
 
-fn expand_cuda_launch(input: CudaLaunchInput) -> TokenStream2 {
-    let stream = &input.stream;
-    let module = &input.module;
-    let config = &input.config;
-    let cluster_dim = &input.cluster_dim;
-    let cooperative = &input.cooperative;
-
-    // Get base kernel name and generic arguments
-    let (kernel_base, _generics) = input.kernel_parts();
-
-    // Build the marker type name for CudaKernel lookup
-    let marker = kernel_sibling_path(&input.kernel, format_ident!("__{}_CudaKernel", kernel_base));
-    let ptx_name_helper =
-        kernel_sibling_path(&input.kernel, format_ident!("{}_ptx_name", kernel_base));
-    let args_ident = internal_ident("__cuda_oxide_args");
-    let closure_ident = internal_ident("__cuda_oxide_closure");
-    let ptx_name_ident = internal_ident("__cuda_oxide_ptx_name");
-    let function_ident = internal_ident("__cuda_oxide_function");
-    let config_ident = internal_ident("__cuda_oxide_config");
-    let cooperative_ident = internal_ident("__cuda_oxide_cooperative");
-    let error_ident = internal_ident("__cuda_oxide_error");
-    let static_ptx_name_ident = internal_ident("__CUDA_OXIDE_PTX_NAME");
-
-    // Check if any argument is a closure (for special handling)
-    let has_closure = input
-        .args
-        .iter()
-        .any(|arg| matches!(arg, CudaLaunchArg::Closure { .. }));
-
-    // Extract closure info if present (for monomorphization). Only the
-    // first closure is treated as the type-inference anchor; the macro
-    // currently supports at most one closure parameter per kernel.
-    let closure_info: Option<&syn::ExprClosure> = input.args.iter().find_map(|arg| {
-        if let CudaLaunchArg::Closure { closure_expr } = arg {
-            Some(closure_expr)
-        } else {
-            None
-        }
-    });
-
-    // Generate argument marshaling code.
-    //
-    // Each argument becomes a stack-local variable whose address is pushed
-    // into a `Vec<*mut c_void>`. This directly matches what cuLaunchKernel
-    // expects: an array of pointers-to-argument-values. No trait dispatch
-    // (PushKernelArg) or heap allocation per arg.
-    let arg_code: Vec<TokenStream2> = input
-        .args
-        .iter()
-        .enumerate()
-        .map(|(i, arg)| {
-            let val_name = internal_ident(&format!("__cuda_oxide_arg_{i}"));
-            match arg {
-                CudaLaunchArg::Direct(expr) => {
-                    quote! {
-                        let mut #val_name = #expr;
-                        #args_ident.push(&mut #val_name as *mut _ as *mut std::ffi::c_void);
-                    }
-                }
-                CudaLaunchArg::SliceWithLen(expr) => {
-                    let ptr_name = internal_ident(&format!("__cuda_oxide_arg_{i}_ptr"));
-                    let len_name = internal_ident(&format!("__cuda_oxide_arg_{i}_len"));
-                    quote! {
-                        let #val_name = &#expr;
-                        let mut #ptr_name = #val_name.cu_deviceptr();
-                        let mut #len_name = #val_name.len() as u64;
-                        #args_ident.push(&mut #ptr_name as *mut _ as *mut std::ffi::c_void);
-                        #args_ident.push(&mut #len_name as *mut _ as *mut std::ffi::c_void);
-                    }
-                }
-                CudaLaunchArg::SliceMutWithLen(expr) => {
-                    let ptr_name = internal_ident(&format!("__cuda_oxide_arg_{i}_ptr"));
-                    let len_name = internal_ident(&format!("__cuda_oxide_arg_{i}_len"));
-                    quote! {
-                        let #val_name = &mut #expr;
-                        let mut #ptr_name = #val_name.cu_deviceptr();
-                        let mut #len_name = #val_name.len() as u64;
-                        #args_ident.push(&mut #ptr_name as *mut _ as *mut std::ffi::c_void);
-                        #args_ident.push(&mut #len_name as *mut _ as *mut std::ffi::c_void);
-                    }
-                }
-                CudaLaunchArg::Closure { .. } => {
-                    // Push the whole closure as a single byval scalar. The
-                    // backend emits a single byval kernel parameter for
-                    // aggregate (struct / closure) entry-point args, so
-                    // pushing `__closure` once matches what the device-side
-                    // `.param` declaration expects.
-                    //
-                    // Routed through `push_kernel_scalar` so ZST closures
-                    // (zero captures) are dropped from the host packet —
-                    // matching the backend, which drops their `.param`
-                    // declaration too. Move closures push by value;
-                    // non-move closures push the closure struct (which
-                    // contains host references the GPU dereferences via
-                    // HMM).
-                    let _ = i;
-                    quote! {
-                        ::cuda_host::push_kernel_scalar(&mut #args_ident, &mut #closure_ident);
-                    }
-                }
-            }
-        })
-        .collect();
-
-    // Build the instantiate helper name (for closures)
-    let instantiate = kernel_sibling_path(
-        &input.kernel,
-        format_ident!("{}{}", INSTANTIATE_PREFIX, kernel_base),
-    );
-
-    // Generate the launch call — regular, cluster, cooperative, or both.
-    //
-    // All paths use the stream-aware cuda_core helpers. Those helpers bind the
-    // stream's owning CUDA context to the calling thread and then delegate to
-    // the raw cuLaunchKernel/cuLaunchKernelEx wrappers.
-    let launch_call = match (&cluster_dim, &cooperative) {
-        (Some(cdim), Some(coop)) => quote! {
-            {
-                let #config_ident = #config;
-                let #cooperative_ident: bool = #coop;
-                if #cooperative_ident {
-                    cuda_core::launch_kernel_ex_cooperative_on_stream(
-                        &#function_ident,
-                        #config_ident.grid_dim,
-                        #config_ident.block_dim,
-                        #config_ident.shared_mem_bytes,
-                        #cdim,
-                        (#stream).as_ref(),
-                        &mut #args_ident,
-                    )
-                } else {
-                    cuda_core::launch_kernel_ex_on_stream(
-                        &#function_ident,
-                        #config_ident.grid_dim,
-                        #config_ident.block_dim,
-                        #config_ident.shared_mem_bytes,
-                        #cdim,
-                        (#stream).as_ref(),
-                        &mut #args_ident,
-                    )
-                }
-            }
-        },
-        (Some(cdim), None) => quote! {
-            {
-                let #config_ident = #config;
-                cuda_core::launch_kernel_ex_on_stream(
-                    &#function_ident,
-                    #config_ident.grid_dim,
-                    #config_ident.block_dim,
-                    #config_ident.shared_mem_bytes,
-                    #cdim,
-                    (#stream).as_ref(),
-                    &mut #args_ident,
-                )
-            }
-        },
-        (None, Some(coop)) => quote! {
-            {
-                let #config_ident = #config;
-                let #cooperative_ident: bool = #coop;
-                if #cooperative_ident {
-                    cuda_core::launch_kernel_cooperative_on_stream(
-                        &#function_ident,
-                        #config_ident.grid_dim,
-                        #config_ident.block_dim,
-                        #config_ident.shared_mem_bytes,
-                        (#stream).as_ref(),
-                        &mut #args_ident,
-                    )
-                } else {
-                    cuda_core::launch_kernel_on_stream(
-                        &#function_ident,
-                        #config_ident.grid_dim,
-                        #config_ident.block_dim,
-                        #config_ident.shared_mem_bytes,
-                        (#stream).as_ref(),
-                        &mut #args_ident,
-                    )
-                }
-            }
-        },
-        (None, None) => quote! {
-            {
-                let #config_ident = #config;
-                cuda_core::launch_kernel_on_stream(
-                    &#function_ident,
-                    #config_ident.grid_dim,
-                    #config_ident.block_dim,
-                    #config_ident.shared_mem_bytes,
-                    (#stream).as_ref(),
-                    &mut #args_ident,
-                )
-            }
-        },
-    };
-
-    if has_closure {
-        let closure_expr = closure_info.expect("has_closure but no closure_info");
-
-        // The on-wire PTX name comes from the kernel's
-        // GenericCudaKernel::ptx_name() impl (via the instantiate helper).
-        // The helper takes `&F` so we can keep ownership of `__closure`
-        // and push it as the byval kernel argument right after — the
-        // backend's kernel-boundary ABI emits a single .param for the
-        // whole closure struct, matching this single push.
-        let _ = closure_expr.span();
-
-        quote! {
-            {
-                let mut #closure_ident = #closure_expr;
-                let #ptx_name_ident: &'static str = #instantiate(&#closure_ident);
-                let #function_ident = #module.load_function(#ptx_name_ident).unwrap_or_else(|#error_ident| {
-                    panic!(
-                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
-                        stringify!(#kernel_base),
-                        #ptx_name_ident,
-                        #error_ident,
-                    )
-                });
-
-                let mut #args_ident: Vec<*mut std::ffi::c_void> = Vec::new();
-                #(#arg_code)*
-
-                #launch_call
-            }
-        }
-    } else if input.is_generic() {
-        quote! {
-            {
-                let #ptx_name_ident = #ptx_name_helper();
-                let #function_ident = #module.load_function(#ptx_name_ident).unwrap_or_else(|#error_ident| {
-                    panic!(
-                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
-                        stringify!(#kernel_base),
-                        #ptx_name_ident,
-                        #error_ident,
-                    )
-                });
-
-                let mut #args_ident: Vec<*mut std::ffi::c_void> = Vec::new();
-                #(#arg_code)*
-
-                #launch_call
-            }
-        }
-    } else {
-        quote! {
-            {
-                const #static_ptx_name_ident: &str = <#marker as cuda_host::CudaKernel>::PTX_NAME;
-                let #function_ident = #module.load_function(#static_ptx_name_ident).unwrap_or_else(|#error_ident| {
-                    panic!(
-                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
-                        stringify!(#kernel_base),
-                        #static_ptx_name_ident,
-                        #error_ident,
-                    )
-                });
-
-                let mut #args_ident: Vec<*mut std::ffi::c_void> = Vec::new();
-                #(#arg_code)*
-
-                #launch_call
-            }
-        }
-    }
-}
-
-// ============================================================================
-// cuda_launch_async! Macro (async path via cuda-async)
-// ============================================================================
-
-/// Parsed input for the [`cuda_launch_async!`] macro.
-///
-/// Unlike [`CudaLaunchInput`], this struct has no `stream` field. The stream
-/// is assigned later by the `SchedulingPolicy` when the returned
-/// `AsyncKernelLaunch` is `.sync()`'d or `.await`'d.
-struct CudaLaunchAsyncInput {
-    /// Path to the `#[kernel]` function, possibly with generic arguments.
-    kernel: syn::Path,
-    /// Expression resolving to an `Arc<CudaModule>` that contains the compiled PTX.
-    module: syn::Expr,
-    /// Expression resolving to a [`LaunchConfig`](https://docs.rs/cuda-core/latest/cuda_core/struct.LaunchConfig.html) (grid/block dims, shared mem).
-    config: syn::Expr,
-    /// Kernel arguments: `slice(x)`, `slice_mut(x)`, direct values, or closures.
-    args: Vec<CudaLaunchArg>,
-}
-
-impl CudaLaunchAsyncInput {
-    /// Splits the kernel path into its base identifier and optional generic arguments.
-    /// For `vecadd::<f32>` returns `("vecadd", Some(<f32>))`.
-    fn kernel_parts(&self) -> (Ident, Option<&syn::PathArguments>) {
-        let last_segment = self
-            .kernel
-            .segments
-            .last()
-            .expect("kernel path must have segments");
-        let base_name = last_segment.ident.clone();
-        let generics = match &last_segment.arguments {
-            syn::PathArguments::None => None,
-            args => Some(args),
-        };
-        (base_name, generics)
-    }
-
-    /// Returns `true` if the kernel path has explicit generic type arguments.
-    fn is_generic(&self) -> bool {
-        self.kernel
-            .segments
-            .last()
-            .map(|seg| !matches!(seg.arguments, syn::PathArguments::None))
-            .unwrap_or(false)
-    }
-}
-
-/// Parses the `cuda_launch_async! { kernel: ..., module: ..., config: ..., args: [...] }` syntax.
-///
-/// Fields can appear in any order. The `args` field uses bracket syntax with the same
-/// argument forms as `cuda_launch!`: `slice(x)`, `slice_mut(x)`, direct values, or closures.
-impl Parse for CudaLaunchAsyncInput {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        let mut kernel = None;
-        let mut module = None;
-        let mut config = None;
-        let mut args = Vec::new();
-
-        while !input.is_empty() {
-            let key: Ident = input.parse()?;
-            input.parse::<Token![:]>()?;
-
-            match key.to_string().as_str() {
-                "kernel" => kernel = Some(input.parse()?),
-                "module" => module = Some(input.parse()?),
-                "config" => config = Some(input.parse()?),
-                "args" => {
-                    let content;
-                    bracketed!(content in input);
-                    if !content.is_empty() {
-                        let parsed: Punctuated<CudaLaunchArg, Token![,]> =
-                            Punctuated::parse_terminated(&content)?;
-                        args = parsed.into_iter().collect();
-                    }
-                }
-                _ => {
-                    return Err(syn::Error::new(
-                        key.span(),
-                        format!(
-                            "unknown field: {}. Expected: kernel, module, config, args",
-                            key
-                        ),
-                    ));
-                }
-            }
-
-            let _ = input.parse::<Token![,]>();
-        }
-
-        Ok(CudaLaunchAsyncInput {
-            kernel: kernel.ok_or_else(|| syn::Error::new(input.span(), "missing 'kernel'"))?,
-            module: module.ok_or_else(|| syn::Error::new(input.span(), "missing 'module'"))?,
-            config: config.ok_or_else(|| syn::Error::new(input.span(), "missing 'config'"))?,
-            args,
-        })
-    }
-}
-
 /// Launch a CUDA kernel asynchronously, returning a lazy `AsyncKernelLaunch`.
 ///
 /// Unlike [`cuda_launch!`], this macro does **not** take a `stream:` parameter. The
@@ -7864,2447 +1106,3 @@ pub fn cuda_launch_async(input: TokenStream) -> TokenStream {
     let input = parse_macro_input!(input as CudaLaunchAsyncInput);
     expand_cuda_launch_async(input).into()
 }
-
-fn expand_cuda_launch_async(input: CudaLaunchAsyncInput) -> TokenStream2 {
-    let module = &input.module;
-    let config = &input.config;
-    let (kernel_base, _generics) = input.kernel_parts();
-    let marker = kernel_sibling_path(&input.kernel, format_ident!("__{}_CudaKernel", kernel_base));
-    let ptx_name_helper =
-        kernel_sibling_path(&input.kernel, format_ident!("{}_ptx_name", kernel_base));
-    let instantiate = kernel_sibling_path(
-        &input.kernel,
-        format_ident!("{}{}", INSTANTIATE_PREFIX, kernel_base),
-    );
-    let has_closure = input
-        .args
-        .iter()
-        .any(|arg| matches!(arg, CudaLaunchArg::Closure { .. }));
-    let closure_expr = input.args.iter().find_map(|arg| {
-        if let CudaLaunchArg::Closure { closure_expr } = arg {
-            Some(closure_expr)
-        } else {
-            None
-        }
-    });
-    let closure_ident = internal_ident("__cuda_oxide_closure");
-    let ptx_name_ident = internal_ident("__cuda_oxide_ptx_name");
-    let function_ident = internal_ident("__cuda_oxide_function");
-    let launch_ident = internal_ident("__cuda_oxide_launch");
-    let error_ident = internal_ident("__cuda_oxide_error");
-    let static_ptx_name_ident = internal_ident("__CUDA_OXIDE_PTX_NAME");
-
-    let arg_code: Vec<TokenStream2> = input
-        .args
-        .iter()
-        .enumerate()
-        .map(|(i, arg)| {
-            let tmp_name = internal_ident(&format!("__cuda_oxide_arg_{i}"));
-            match arg {
-                CudaLaunchArg::Direct(expr) => {
-                    quote! {
-                        #launch_ident.push_scalar_arg(#expr);
-                    }
-                }
-                CudaLaunchArg::SliceWithLen(expr) => {
-                    let len_name = internal_ident(&format!("__cuda_oxide_arg_{i}_len"));
-                    quote! {
-                        let #tmp_name = &#expr;
-                        #launch_ident.push_arg(Box::new(#tmp_name.cu_deviceptr()));
-                        let #len_name = #tmp_name.len() as u64;
-                        #launch_ident.push_arg(Box::new(#len_name));
-                    }
-                }
-                CudaLaunchArg::SliceMutWithLen(expr) => {
-                    let len_name = internal_ident(&format!("__cuda_oxide_arg_{i}_len"));
-                    quote! {
-                        let #tmp_name = &mut #expr;
-                        #launch_ident.push_arg(Box::new(#tmp_name.cu_deviceptr()));
-                        let #len_name = #tmp_name.len() as u64;
-                        #launch_ident.push_arg(Box::new(#len_name));
-                    }
-                }
-                CudaLaunchArg::Closure { .. } => {
-                    // Push the whole closure as one byval scalar so the
-                    // host packet matches the single aggregate `.param`
-                    // at the kernel boundary. ZST closures are omitted
-                    // to keep later packet slots aligned.
-                    quote! {
-                        if ::core::mem::size_of_val(&#closure_ident) != 0 {
-                            #launch_ident.push_scalar_arg(#closure_ident);
-                        }
-                    }
-                }
-            }
-        })
-        .collect();
-
-    if has_closure {
-        let closure_expr = closure_expr.expect("has_closure but no closure expression");
-        quote! {
-            {
-                let #closure_ident = #closure_expr;
-                let #ptx_name_ident: &'static str = #instantiate(&#closure_ident);
-                let #function_ident = #module.load_function(#ptx_name_ident).unwrap_or_else(|#error_ident| {
-                    panic!(
-                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
-                        stringify!(#kernel_base),
-                        #ptx_name_ident,
-                        #error_ident,
-                    )
-                });
-                let mut #launch_ident = cuda_async::launch::AsyncKernelLaunchBuilder::new(
-                    std::sync::Arc::new(#function_ident),
-                );
-                #(#arg_code)*
-                #launch_ident.finalize_unchecked(#config)
-            }
-        }
-    } else if input.is_generic() {
-        quote! {
-            {
-                let #ptx_name_ident = #ptx_name_helper();
-                let #function_ident = #module.load_function(#ptx_name_ident).unwrap_or_else(|#error_ident| {
-                    panic!(
-                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
-                        stringify!(#kernel_base),
-                        #ptx_name_ident,
-                        #error_ident,
-                    )
-                });
-                let mut #launch_ident = cuda_async::launch::AsyncKernelLaunchBuilder::new(
-                    std::sync::Arc::new(#function_ident),
-                );
-                #(#arg_code)*
-                #launch_ident.finalize_unchecked(#config)
-            }
-        }
-    } else {
-        quote! {
-            {
-                const #static_ptx_name_ident: &str =
-                    <#marker as cuda_host::CudaKernel>::PTX_NAME;
-                let #function_ident = #module.load_function(#static_ptx_name_ident).unwrap_or_else(|#error_ident| {
-                    panic!(
-                        "Failed to load kernel `{}` (expected PTX entry `{}`): {:?}",
-                        stringify!(#kernel_base),
-                        #static_ptx_name_ident,
-                        #error_ident,
-                    )
-                });
-                let mut #launch_ident = cuda_async::launch::AsyncKernelLaunchBuilder::new(
-                    std::sync::Arc::new(#function_ident),
-                );
-                #(#arg_code)*
-                #launch_ident.finalize_unchecked(#config)
-            }
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use reserved_oxide_symbols::PTX_MERGE_REQUIRED_PREFIX;
-
-    /// Expands a `#[cuda_module]` body and returns the generated tokens as a
-    /// whitespace-free string, so tests can assert on call paths without
-    /// caring how `quote!` spaces out `::` separators.
-    fn expand_to_compact_string(module: ItemMod) -> String {
-        expand_cuda_module(module)
-            .expect("cuda_module expansion failed")
-            .to_string()
-            .replace(' ', "")
-    }
-
-    /// Expands a `#[cuda_module]` body with the host surface suppressed.
-    fn expand_device_only_to_compact_string(module: ItemMod) -> String {
-        expand_cuda_module_inner(module, false)
-            .expect("cuda_module expansion failed")
-            .to_string()
-            .replace(' ', "")
-    }
-
-    fn one_kernel_module() -> ItemMod {
-        parse_quote! {
-            mod kernels {
-                #[kernel]
-                fn scale(out: *mut f32) {}
-            }
-        }
-    }
-
-    /// With the host surface off, nothing in the expansion may name the
-    /// `cuda-host` -> `cuda-core` -> `cuda-bindings` -> `cuda.h` stack. That is
-    /// the whole point of the feature: a crate that only compiles kernels
-    /// should not have to build it.
-    #[test]
-    fn device_only_cuda_module_names_no_host_crate() {
-        let expanded = expand_device_only_to_compact_string(one_kernel_module());
-        assert!(
-            !expanded.contains("cuda_host"),
-            "device-only expansion must not name cuda_host: {expanded}"
-        );
-        assert!(
-            !expanded.contains("cuda_core"),
-            "device-only expansion must not name cuda_core: {expanded}"
-        );
-        assert!(
-            !expanded.contains("LoadedModule"),
-            "device-only expansion must not emit the loader type: {expanded}"
-        );
-    }
-
-    /// Gating must remove only the host surface. The kernel itself still has
-    /// to reach the codegen collector.
-    #[test]
-    fn device_only_cuda_module_still_emits_the_kernel() {
-        let expanded = expand_device_only_to_compact_string(one_kernel_module());
-        assert!(
-            expanded.contains("#[kernel]fnscale"),
-            "the kernel must survive gating: {expanded}"
-        );
-    }
-
-    /// The default build is unchanged: this is the additive half of the
-    /// contract, and existing consumers depend on it.
-    #[test]
-    fn host_cuda_module_still_emits_the_loader() {
-        let expanded = expand_to_compact_string(one_kernel_module());
-        assert!(
-            expanded.contains("::cuda_host::") && expanded.contains("LoadedModule"),
-            "host expansion must keep the loader: {expanded}"
-        );
-    }
-
-    /// A nested inline module gets its own `LoadedModule`, so it needs the
-    /// same gate as the outer one.
-    #[test]
-    fn device_only_nested_module_emits_no_loader() {
-        let module: ItemMod = parse_quote! {
-            mod outer {
-                mod inner {
-                    #[kernel]
-                    fn scale(out: *mut f32) {}
-                }
-            }
-        };
-        let expanded = expand_device_only_to_compact_string(module);
-        assert!(
-            !expanded.contains("LoadedModule") && !expanded.contains("cuda_host"),
-            "nested device-only expansion must emit no loader: {expanded}"
-        );
-    }
-
-    /// A bare `#[kernel]` outside any `#[cuda_module]` carries its own
-    /// `CudaKernel` impl, the other reference a kernel-only crate cannot
-    /// resolve.
-    #[test]
-    fn bare_kernel_marker_impl_is_host_only() {
-        let func: ItemFn = parse_quote! {
-            fn scale(out: *mut f32) {}
-        };
-        let name = format_ident!("scale");
-
-        let device_only = generate_cuda_kernel_impl(&name, "scale", &func, false).to_string();
-        assert!(
-            device_only.is_empty(),
-            "device-only build must emit no marker impl: {device_only}"
-        );
-
-        let host = generate_cuda_kernel_impl(&name, "scale", &func, true).to_string();
-        assert!(
-            host.contains("CudaKernel"),
-            "host build must keep the marker impl: {host}"
-        );
-    }
-
-    #[test]
-    fn generated_kernel_siblings_preserve_qualified_paths_and_generics() {
-        let kernel: syn::Path = parse_quote! { kernels::map::<_, 4> };
-        let instantiate = kernel_sibling_path(&kernel, format_ident!("{}map", INSTANTIATE_PREFIX));
-        let marker = kernel_sibling_path(&kernel, format_ident!("__map_CudaKernel"));
-        let ptx_name = kernel_sibling_path(&kernel, format_ident!("map_ptx_name"));
-
-        let instantiate = quote! { #instantiate }.to_string().replace(' ', "");
-        let marker = quote! { #marker }.to_string().replace(' ', "");
-        let ptx_name = quote! { #ptx_name }.to_string().replace(' ', "");
-        assert_eq!(
-            instantiate,
-            format!("kernels::{}map::<_,4>", INSTANTIATE_PREFIX)
-        );
-        assert_eq!(marker, "kernels::__map_CudaKernel::<_,4>");
-        assert_eq!(ptx_name, "kernels::map_ptx_name::<_,4>");
-    }
-
-    #[test]
-    fn forwarding_inputs_name_every_irrefutable_parameter_pattern() {
-        let function: ItemFn = parse_quote! {
-            fn patterns(_: u32, (left, right): (u16, u16), mut value: u8) {}
-        };
-        let (inputs, names) = forwarding_inputs(&function.sig.inputs).unwrap();
-        let forwarded = quote! {
-            fn wrapper(#(#inputs),*) {
-                target(#(#names),*)
-            }
-        }
-        .to_string()
-        .replace(' ', "");
-
-        assert!(forwarded.contains("__cuda_oxide_arg_0:u32"));
-        assert!(forwarded.contains("__cuda_oxide_arg_1:(u16,u16)"));
-        assert!(forwarded.contains("__cuda_oxide_arg_2:u8"));
-        assert!(
-            forwarded.contains("target(__cuda_oxide_arg_0,__cuda_oxide_arg_1,__cuda_oxide_arg_2)")
-        );
-    }
-
-    #[test]
-    fn device_codegen_owner_selection_matches_backend_name_rules() {
-        assert_eq!(device_codegen_owner_selection(None, "gpu_lib"), None);
-        assert_eq!(device_codegen_owner_selection(Some(" , "), "gpu_lib"), None);
-        assert_eq!(
-            device_codegen_owner_selection(Some("gpu-lib, math_gpu"), "gpu_lib"),
-            Some(true)
-        );
-        assert_eq!(
-            device_codegen_owner_selection(Some("gpu-lib, math_gpu"), "host_app"),
-            Some(false)
-        );
-    }
-
-    #[test]
-    fn cooperative_kernel_launches_through_cooperative_driver_call() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[cooperative_launch]
-                pub fn grid_sync_kernel(mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        // The sync launch method must route through the cooperative driver
-        // entry point (cuLaunchKernelEx + CU_LAUNCH_ATTRIBUTE_COOPERATIVE)
-        // instead of plain cuLaunchKernel.
-        assert!(
-            expanded.contains("launch_kernel_cooperative_on_stream"),
-            "expected cooperative launch call in generated tokens:\n{expanded}"
-        );
-        assert!(
-            !expanded.contains("launch_kernel_on_stream"),
-            "plain launch call should be replaced by the cooperative one:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn plain_kernel_keeps_plain_driver_call() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn plain_kernel(mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(
-            expanded.contains("launch_kernel_on_stream"),
-            "expected plain launch call in generated tokens:\n{expanded}"
-        );
-        assert!(
-            !expanded.contains("launch_kernel_cooperative_on_stream"),
-            "cooperative call must not appear without #[cooperative_launch]:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn cuda_module_routes_type_and_const_generics_through_name_helper() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn mixed<'a, T: Copy + 'a, const N: usize>(
-                    input: &'a [T],
-                    output: &mut [T],
-                ) {
-                }
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(
-            expanded.contains("mixed_ptx_name::<T,N>()"),
-            "typed launch must forward type and const arguments to the name helper:\n{expanded}"
-        );
-        assert!(
-            expanded.contains(PTX_MERGE_REQUIRED_PREFIX),
-            "generic cuda_module must emit the compiler-visible PTX-merge marker:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn non_generic_cuda_module_does_not_emit_ptx_merge_marker() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn plain(output: &mut [u32]) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(
-            !expanded.contains(PTX_MERGE_REQUIRED_PREFIX),
-            "non-generic cuda_module must remain eligible for cubin materialization:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn cfg_gated_generic_uses_the_same_gate_for_marker_and_loader() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn plain(output: &mut [u32]) {}
-
-                #[cfg(feature = "generic")]
-                #[kernel]
-                pub fn optional<T: Copy>(value: T) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-        let marker = ptx_merge_required_marker("optional");
-
-        assert!(
-            expanded.contains(&format!(
-                "#[cfg(feature=\"generic\")]#[doc(hidden)]#[used]#[allow(dead_code,non_upper_case_globals)]static{marker}:u8=0"
-            )),
-            "marker must inherit the generic kernel's cfg:\n{expanded}"
-        );
-        assert!(
-            expanded.contains(
-                "#[cfg(feature=\"generic\")]let_={__cuda_oxide_has_enabled_generic_kernel=true;};"
-            ),
-            "loader selection must inherit the generic kernel's cfg:\n{expanded}"
-        );
-        assert!(
-            expanded.contains("if__cuda_oxide_has_enabled_generic_kernel{let_=name;::cuda_host::load_all_ptx_bundles_merged(ctx)?}else{::cuda_host::load_embedded_module(ctx,name)?}"),
-            "loader must fall back to the embedded artifact when no generic kernel is enabled:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn nested_generic_marker_inherits_every_ancestor_cfg() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[cfg(feature = "outer")]
-                mod nested {
-                    #[cfg(target_os = "linux")]
-                    #[kernel]
-                    pub fn map<T: Copy>(value: T) {}
-                }
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-        let marker = ptx_merge_required_marker("map");
-        assert!(
-            expanded.contains(&format!(
-                "#[cfg(feature=\"outer\")]#[cfg(target_os=\"linux\")]#[doc(hidden)]#[used]#[allow(dead_code,non_upper_case_globals)]static{marker}:u8=0"
-            )),
-            "root marker must use the nested kernel's effective cfg chain:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn generic_kernel_routes_entry_directives_without_losing_cfg() {
-        let function: ItemFn = parse_quote! {
-            #[doc = "configured kernel"]
-            #[cfg(feature = "configured")]
-            #[launch_bounds(256, 2)]
-            #[cluster_launch(2, 1, 1)]
-            fn configured<const N: usize>() {}
-        };
-
-        let (implementation, entry, cfg) = route_generic_kernel_attrs(&function.attrs);
-
-        assert!(
-            implementation
-                .iter()
-                .any(|attr| attr_path_ends_with(attr, "doc"))
-        );
-        assert!(
-            implementation
-                .iter()
-                .any(|attr| attr_path_ends_with(attr, "cfg"))
-        );
-        assert!(
-            !implementation
-                .iter()
-                .any(|attr| attr_path_ends_with(attr, "launch_bounds"))
-        );
-        assert!(
-            !implementation
-                .iter()
-                .any(|attr| attr_path_ends_with(attr, "cluster_launch"))
-        );
-
-        assert!(entry.iter().any(|attr| attr_path_ends_with(attr, "cfg")));
-        assert!(
-            entry
-                .iter()
-                .any(|attr| attr_path_ends_with(attr, "launch_bounds"))
-        );
-        assert!(
-            entry
-                .iter()
-                .any(|attr| attr_path_ends_with(attr, "cluster_launch"))
-        );
-        assert!(!entry.iter().any(|attr| attr_path_ends_with(attr, "doc")));
-
-        assert_eq!(cfg.len(), 1);
-        assert!(attr_path_ends_with(&cfg[0], "cfg"));
-    }
-
-    #[test]
-    fn cooperative_plus_cluster_kernel_uses_combined_driver_call() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[cluster_launch(2, 1, 1)]
-                #[cooperative_launch]
-                pub fn clustered_grid_sync_kernel(mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        // cuLaunchKernelEx accepts both attributes in one attrs array, so the
-        // combination is allowed and routes through the combined helper.
-        assert!(
-            expanded.contains("launch_kernel_ex_cooperative_on_stream"),
-            "expected combined cluster+cooperative launch call:\n{expanded}"
-        );
-        assert!(
-            !expanded.contains("launch_kernel_ex_on_stream"),
-            "cluster-only call should be replaced by the combined one:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn cuda_launch_accepts_combined_cluster_and_cooperative() {
-        let input: CudaLaunchInput = parse_quote! {
-            kernel: clustered_grid_sync_kernel,
-            stream: stream,
-            module: module,
-            config: config,
-            cluster_dim: (2, 1, 1),
-            cooperative: true,
-            args: []
-        };
-        assert!(input.cluster_dim.is_some());
-        assert!(input.cooperative.is_some());
-
-        let expanded = expand_cuda_launch(input).to_string().replace(' ', "");
-        assert!(
-            expanded.contains("launch_kernel_ex_cooperative_on_stream"),
-            "expected combined cluster+cooperative cuda_launch expansion:\n{expanded}"
-        );
-        assert!(
-            !expanded.contains("launch_kernel_cooperative_on_stream"),
-            "non-cluster cooperative helper must not be used when cluster_dim is set:\n{expanded}"
-        );
-    }
-
-    #[cfg(feature = "async")]
-    #[test]
-    fn cooperative_kernel_sets_async_builder_knob() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[cooperative_launch]
-                pub fn grid_sync_kernel(mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        // Both the borrowed-async and owned-async builder methods set the
-        // cooperative knob, exactly like set_async_kernel_cluster_dim is set
-        // for #[cluster_launch].
-        assert_eq!(
-            expanded.matches("set_async_kernel_cooperative").count(),
-            2,
-            "expected the cooperative knob in both async builder methods:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn cooperative_launch_with_arguments_is_rejected() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[cooperative_launch(4)]
-                pub fn grid_sync_kernel(mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let error = expand_cuda_module(module).expect_err("expected expansion to fail");
-        assert!(
-            error
-                .to_string()
-                .contains("cooperative_launch takes no arguments"),
-            "unexpected error message: {error}"
-        );
-    }
-
-    #[test]
-    fn nested_inline_module_kernels_generate_namespace_local_launchers() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn top(mut out: DisjointSlice<u32>) {}
-
-                pub mod stage1 {
-                    #[kernel]
-                    pub fn scale(mut out: DisjointSlice<f32>) {}
-                }
-
-                pub mod stage2 {
-                    pub mod inner {
-                        #[kernel]
-                        pub fn shift(mut out: DisjointSlice<f32>) {}
-                    }
-                }
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-        assert!(
-            expanded.contains("pubmodstage1{#[kernel]pubfnscale")
-                && expanded.contains("<__scale_CudaKernelas::cuda_host::CudaKernel>"),
-            "expected the stage1 launcher to resolve its marker locally:\n{expanded}"
-        );
-        assert!(
-            expanded.contains("pubmodinner{#[kernel]pubfnshift")
-                && expanded.contains("<__shift_CudaKernelas::cuda_host::CudaKernel>"),
-            "expected the doubly nested launcher to resolve its marker locally:\n{expanded}"
-        );
-        assert!(
-            expanded.matches("pubstructLoadedModule").count() == 4,
-            "expected root, stage1, stage2, and inner module views:\n{expanded}"
-        );
-        assert!(
-            expanded.contains("from_parent(parent:&super::LoadedModule")
-                && expanded.contains("parent.__generic_functions.clone()"),
-            "expected nested views to share the parent module and cache:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn nested_launch_contract_stays_in_its_namespace_and_taints_root_loading() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                pub mod stage {
-                    #[kernel]
-                    #[launch_contract(domain = 1, block = (64, 1, 1))]
-                    pub fn map(mut out: DisjointSlice<u32>) {}
-                }
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert_eq!(
-            expanded
-                .matches("impl::cuda_core::KernelLaunchContract")
-                .count(),
-            1,
-            "the contract impl must be emitted once in the child namespace:\n{expanded}"
-        );
-        assert_eq!(
-            expanded.matches("fnprepare_map(").count(),
-            1,
-            "the prepared launcher must be emitted once in the child namespace:\n{expanded}"
-        );
-        assert!(
-            expanded.contains("pubunsafefnload("),
-            "a descendant contract must make root artifact binding unsafe:\n{expanded}"
-        );
-        assert!(
-            expanded.contains("pubmodstage{")
-                && expanded.contains("from_parent(parent:&super::LoadedModule"),
-            "main's nested module view must remain intact:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn nested_generic_kernel_uses_local_ptx_name_helper() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn top(mut out: DisjointSlice<u32>) {}
-
-                pub mod stage1 {
-                    #[kernel]
-                    pub fn map<F: Fn(f32) -> f32 + Copy>(f: F, mut out: DisjointSlice<f32>) {}
-                }
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-        assert!(
-            expanded.contains("let__cuda_oxide_ptx_name=map_ptx_name::<F>()"),
-            "expected the generic binding to call the namespace-local ptx-name helper:\n{expanded}"
-        );
-        assert!(
-            !expanded.contains("stage1::map_ptx_name"),
-            "the nested launcher must not resolve its private helper from the parent:\n{expanded}"
-        );
-    }
-
-    #[test]
-    fn nested_kernel_tracks_local_and_effective_cfg_availability() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[cfg(feature = "outer")]
-                mod outer {
-                    #[cfg_attr(feature = "inner", cfg(target_os = "linux"), allow(dead_code))]
-                    mod inner {
-                        #[cfg(target_arch = "x86_64")]
-                        #[kernel]
-                        fn nested() {}
-                    }
-                }
-            }
-        };
-        let items = &module.content.expect("inline module").1;
-        let transformed =
-            transform_cuda_module_items(items, &mut Vec::new(), &[], false, true).unwrap();
-        let kernel = transformed
-            .kernels
-            .iter()
-            .find(|kernel| kernel.fn_name == "nested")
-            .expect("nested kernel was not collected");
-        let local_attrs = &kernel.cfg_attrs;
-        let effective_attrs = &kernel.effective_cfg_attrs;
-        let local = quote!(#(#local_attrs)*).to_string().replace(' ', "");
-        let effective = quote!(#(#effective_attrs)*).to_string().replace(' ', "");
-
-        assert_eq!(local, "#[cfg(target_arch=\"x86_64\")]");
-        assert!(effective.contains("#[cfg(feature=\"outer\")]"));
-        assert!(effective.contains("#[cfg_attr(feature=\"inner\",cfg(target_os=\"linux\"))]"));
-        assert!(!effective.contains("allow(dead_code)"));
-        assert!(effective.ends_with("#[cfg(target_arch=\"x86_64\")]"));
-    }
-
-    #[test]
-    fn conflicting_kernel_names_across_modules_are_rejected() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                pub mod stage1 {
-                    #[kernel]
-                    pub fn step(mut out: DisjointSlice<f32>) {}
-                }
-
-                pub mod stage2 {
-                    #[kernel]
-                    pub fn step(mut out: DisjointSlice<f32>) {}
-                }
-            }
-        };
-        let error = expand_cuda_module(module).expect_err("expected expansion to fail");
-        let message = error.to_string();
-        assert!(
-            message.contains("requires kernel names to be unique")
-                && message.contains("stage1")
-                && message.contains("stage2"),
-            "unexpected error message: {message}"
-        );
-    }
-
-    #[test]
-    fn launch_contract_generates_prepared_and_unsafe_raw_paths() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_bounds(256)]
-                #[launch_contract(
-                    domain = 1,
-                    coordinates = u32,
-                    block = (256, 1, 1),
-                    dynamic_shared = 1024,
-                    dynamic_shared_alignment = 128,
-                    min_compute_capability = (8, 0),
-                )]
-                pub fn map(input: &[u32], mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(expanded.contains("impl::cuda_core::KernelLaunchContractfor__map_CudaKernel"));
-        assert!(expanded.contains("typeConfig=::cuda_core::LaunchConfig1D"));
-        assert!(expanded.contains("fnprepare_map("));
-        assert!(expanded.contains("PreparedLaunch<__map_CudaKernel>"));
-        assert!(expanded.contains("fnmap("));
-        assert!(
-            !expanded.contains("unsafefnmap("),
-            "a safe source kernel must keep its prepared launch method safe: {expanded}"
-        );
-        assert!(
-            expanded
-                .contains("__cuda_oxide_prepared:&::cuda_core::PreparedLaunch<__map_CudaKernel>")
-        );
-        assert!(expanded.contains("unsafefnmap_unchecked("));
-        assert!(expanded.contains("__cuda_oxide_config:::cuda_core::LaunchConfig"));
-        assert!(expanded.contains("min_alignment:128u32"));
-        assert!(expanded.contains("with_min_compute_capability(8u32,0u32)"));
-        assert!(expanded.contains("with_u32_coordinates()"));
-    }
-
-    #[test]
-    fn kernel_launch_context_uses_the_contract_domain_and_coordinate_width_in_either_order() {
-        let mut attributed: ItemFn = parse_quote! {
-            #[launch_contract(domain = 1, coordinates = u32, block = (64, 1, 1))]
-            fn attributed() {
-                let _ = thread::index_1d_u32(launch_context);
-            }
-        };
-        let scope = explicit_kernel_scope(&mut attributed, format_ident!("launch_context"));
-        attributed
-            .block
-            .stmts
-            .splice(0..0, explicit_kernel_scope_bindings(&scope));
-        let attributed = quote!(#attributed).to_string().replace(' ', "");
-        assert!(attributed.contains("make_kernel_scope::<::cuda_device::thread::__internal::Domain1,::cuda_device::thread::__internal::U32Coordinates>"));
-        assert!(attributed.contains("letlaunch_context:::cuda_device::thread::LaunchContextRef"));
-
-        let mut expanded_first: ItemFn = parse_quote! {
-            fn expanded_first() {
-                unsafe {
-                    ::cuda_device::thread::__launch_contract_config::<1, true>();
-                }
-                let _ = thread::index_1d_u32(launch_context);
-            }
-        };
-        let scope = explicit_kernel_scope(&mut expanded_first, format_ident!("launch_context"));
-        expanded_first
-            .block
-            .stmts
-            .splice(0..0, explicit_kernel_scope_bindings(&scope));
-        let expanded_first = quote!(#expanded_first).to_string().replace(' ', "");
-        assert!(expanded_first.contains("make_kernel_scope::<::cuda_device::thread::__internal::Domain1,::cuda_device::thread::__internal::U32Coordinates>"));
-
-        let mut two_dimensional: ItemFn = parse_quote! {
-            #[launch_contract(domain = 2, coordinates = u32, block = (8, 8, 1))]
-            fn two_dimensional() {
-                let _ = thread::coord_2d_u32(launch_context);
-            }
-        };
-        let scope = explicit_kernel_scope(&mut two_dimensional, format_ident!("launch_context"));
-        two_dimensional
-            .block
-            .stmts
-            .splice(0..0, explicit_kernel_scope_bindings(&scope));
-        let two_dimensional = quote!(#two_dimensional).to_string().replace(' ', "");
-        assert!(two_dimensional.contains("make_kernel_scope::<::cuda_device::thread::__internal::Domain2,::cuda_device::thread::__internal::U32Coordinates>"));
-    }
-
-    #[test]
-    fn thread_index_rewrite_preserves_the_user_call_span_with_multiple_attributes() {
-        let mut input: ItemFn = syn::parse_str(
-            r#"
-/// The documentation and neighboring attributes must not become line-table
-/// locations for the first executable indexing expression.
-#[allow(dead_code)]
-#[launch_bounds(256, 2)]
-fn documented_kernel() {
-    let idx = thread::index_1d();
-    consume(idx);
-}
-"#,
-        )
-        .unwrap();
-        let source_attr_count = input.attrs.len();
-
-        let Stmt::Local(original_local) = &input.block.stmts[0] else {
-            panic!("fixture starts with a local")
-        };
-        let original_call = original_local
-            .init
-            .as_ref()
-            .map(|init| &*init.expr)
-            .and_then(|expr| match expr {
-                Expr::Call(call) => Some(call),
-                _ => None,
-            })
-            .expect("fixture local is initialized by a call");
-        let user_call_start = original_call.span().start();
-        assert!(
-            user_call_start.line > 5,
-            "fixture must distinguish attributes"
-        );
-
-        inject_thread_index_scope(&mut input);
-
-        assert_eq!(
-            input.attrs.len(),
-            source_attr_count,
-            "all source attributes stay on the item"
-        );
-        let Stmt::Local(rewritten_local) = &input.block.stmts[1] else {
-            panic!("the user local follows the generated scope binding")
-        };
-        let rewritten_call = rewritten_local
-            .init
-            .as_ref()
-            .map(|init| &*init.expr)
-            .and_then(|expr| match expr {
-                Expr::Call(call) => Some(call),
-                _ => None,
-            })
-            .expect("rewritten local remains a call expression");
-
-        assert_eq!(
-            rewritten_call.span().start(),
-            user_call_start,
-            "rewriting must not relocate the user expression onto an attribute"
-        );
-        let Expr::Path(path) = &*rewritten_call.func else {
-            panic!("rewritten callee remains a path")
-        };
-        assert!(
-            path.path
-                .segments
-                .iter()
-                .any(|segment| segment.ident == "__internal")
-        );
-        assert_eq!(
-            rewritten_call.args[0].span().start(),
-            user_call_start,
-            "the injected scope reference belongs to the user's call site"
-        );
-    }
-
-    #[test]
-    fn kernel_launch_context_argument_composes_with_legacy_instantiations() {
-        let args: KernelArgs = syn::parse_str("f32, launch_context = launch_context, f64").unwrap();
-        assert_eq!(args.instantiate_types.len(), 2);
-        assert_eq!(args.launch_context.unwrap(), "launch_context");
-
-        let duplicate =
-            syn::parse_str::<KernelArgs>("launch_context = first, launch_context = second")
-                .err()
-                .unwrap();
-        assert!(duplicate.to_string().contains("duplicate `launch_context`"));
-
-        let unknown = syn::parse_str::<KernelArgs>("context = launch_context")
-            .err()
-            .unwrap();
-        assert!(
-            unknown
-                .to_string()
-                .contains("unknown #[kernel] named argument")
-        );
-    }
-
-    #[test]
-    fn kernel_unchecked_indexing_flag_parses_and_composes() {
-        let bare: KernelArgs = syn::parse_str("unchecked_indexing").unwrap();
-        assert!(bare.unchecked_indexing);
-        assert!(bare.instantiate_types.is_empty());
-        assert!(bare.launch_context.is_none());
-
-        let composed: KernelArgs =
-            syn::parse_str("f32, launch_context = launch_context, unchecked_indexing").unwrap();
-        assert!(composed.unchecked_indexing);
-        assert_eq!(composed.instantiate_types.len(), 1);
-        assert_eq!(composed.launch_context.unwrap(), "launch_context");
-
-        let leading: KernelArgs = syn::parse_str("unchecked_indexing, f32").unwrap();
-        assert!(leading.unchecked_indexing);
-        assert_eq!(leading.instantiate_types.len(), 1);
-
-        let default: KernelArgs = syn::parse_str("f32, launch_context = launch_context").unwrap();
-        assert!(!default.unchecked_indexing);
-
-        let duplicate = syn::parse_str::<KernelArgs>("unchecked_indexing, unchecked_indexing")
-            .err()
-            .unwrap();
-        assert!(
-            duplicate
-                .to_string()
-                .contains("duplicate `unchecked_indexing`")
-        );
-
-        // The flag is a bare word, never a named argument.
-        let named = syn::parse_str::<KernelArgs>("unchecked_indexing = true")
-            .err()
-            .unwrap();
-        assert!(
-            named
-                .to_string()
-                .contains("unknown #[kernel] named argument")
-        );
-    }
-
-    #[test]
-    fn unchecked_indexing_marker_is_a_forwardable_configuration_marker() {
-        // The exact statement the `#[kernel]` macro injects must be recognized
-        // by the generic-entry marker forwarding, so the flag reaches the
-        // generated entry wrapper even when the implementation helper is
-        // translated separately.
-        let marker: Stmt = parse_quote! {
-            ::cuda_device::thread::__unchecked_indexing_config::<true>();
-        };
-        assert!(is_kernel_configuration_marker(&marker));
-        assert!(is_unchecked_indexing_config_marker(&marker));
-
-        let kernel: ItemFn = parse_quote! {
-            fn body() {
-                ::cuda_device::thread::__unchecked_indexing_config::<true>();
-                work();
-            }
-        };
-        let markers = top_level_kernel_configuration_markers(&kernel);
-        assert_eq!(markers.len(), 1);
-    }
-
-    /// Renders the function item named `name` from an expansion, panicking
-    /// with the full expansion when it is missing.
-    fn expansion_fn_source(expanded: &TokenStream2, name: &str) -> String {
-        let file: syn::File =
-            syn::parse2(expanded.clone()).expect("generated tokens must parse as items");
-        let function = file
-            .items
-            .iter()
-            .find_map(|item| match item {
-                syn::Item::Fn(item_fn) if item_fn.sig.ident == name => Some(item_fn),
-                _ => None,
-            })
-            .unwrap_or_else(|| panic!("expansion has no fn `{name}`:\n{expanded}"));
-        quote!(#function).to_string().replace(' ', "")
-    }
-
-    /// The kernel body exactly as `kernel()` hands it to the generic
-    /// expansion paths: the unchecked-indexing marker is already statement 0.
-    fn opted_generic_kernel() -> ItemFn {
-        parse_quote! {
-            pub fn scaled_gather<T: Copy>(a: &[T], mut c: DisjointSlice<T>) {
-                ::cuda_device::thread::__unchecked_indexing_config::<true>();
-                work(a, &mut c);
-            }
-        }
-    }
-
-    #[test]
-    fn generic_expansion_confines_unchecked_marker_to_entry_and_hidden_twin() {
-        let expanded = generic_kernel_no_instantiation_tokens(opted_generic_kernel(), None);
-
-        // The user-named implementation helper is ordinary callable Rust and
-        // must NOT carry the marker: rustc may inline it into other kernels
-        // that never opted in.
-        let helper = expansion_fn_source(&expanded, "scaled_gather");
-        assert!(
-            !helper.contains("__unchecked_indexing_config"),
-            "helper leaked the marker:\n{helper}"
-        );
-
-        // The generated entry wrapper keeps the forwarded marker and calls
-        // the hidden unchecked twin instead of the user-named helper.
-        let entry = expansion_fn_source(&expanded, &format!("{KERNEL_PREFIX}scaled_gather"));
-        assert!(
-            entry.contains("__unchecked_indexing_config"),
-            "entry wrapper lost the marker:\n{entry}"
-        );
-        assert!(
-            entry.contains("__cuda_oxide_unchecked_impl_scaled_gather::<T>"),
-            "entry wrapper does not call the unchecked twin:\n{entry}"
-        );
-
-        let twin = expansion_fn_source(&expanded, "__cuda_oxide_unchecked_impl_scaled_gather");
-        assert!(twin.contains("__unchecked_indexing_config"));
-    }
-
-    #[test]
-    fn legacy_instantiation_confines_unchecked_marker_to_entry_and_hidden_twin() {
-        // Legacy `#[kernel(Type, ...)]` instantiation supports by-value
-        // parameters of the single type parameter (see
-        // `kernel_launch_context_api.rs`'s `explicit` kernel).
-        let kernel: ItemFn = parse_quote! {
-            pub fn scaled_gather<T: Copy>(value: T) {
-                ::cuda_device::thread::__unchecked_indexing_config::<true>();
-                work(value);
-            }
-        };
-        let expanded =
-            generic_kernel_instantiation_tokens(kernel, vec![parse_quote! { f32 }], None);
-
-        let helper = expansion_fn_source(&expanded, "scaled_gather");
-        assert!(
-            !helper.contains("__unchecked_indexing_config"),
-            "helper leaked the marker:\n{helper}"
-        );
-
-        let entry = expansion_fn_source(&expanded, &format!("{KERNEL_PREFIX}scaled_gather_f32"));
-        assert!(
-            entry.contains("__unchecked_indexing_config"),
-            "entry wrapper lost the marker:\n{entry}"
-        );
-        assert!(
-            entry.contains("__cuda_oxide_unchecked_impl_scaled_gather::<f32>"),
-            "entry wrapper does not call the unchecked twin:\n{entry}"
-        );
-
-        let twin = expansion_fn_source(&expanded, "__cuda_oxide_unchecked_impl_scaled_gather");
-        assert!(twin.contains("__unchecked_indexing_config"));
-    }
-
-    #[test]
-    fn non_opted_generic_expansion_has_no_unchecked_twin_or_marker() {
-        let kernel: ItemFn = parse_quote! {
-            pub fn plain<T: Copy>(a: &[T], mut c: DisjointSlice<T>) {
-                work(a, &mut c);
-            }
-        };
-        let expanded = generic_kernel_no_instantiation_tokens(kernel, None).to_string();
-        assert!(!expanded.contains("__unchecked_indexing_config"));
-        assert!(!expanded.contains("__cuda_oxide_unchecked_impl"));
-        assert!(!expanded.contains("dead_code"));
-    }
-
-    #[test]
-    fn unchecked_twin_carries_helper_lint_attributes() {
-        // A lint the author suppressed on the kernel must not re-fire on the
-        // byte-identical twin body (that would break -Dwarnings builds), and
-        // the user-named helper must be allowed to go dead: the generated
-        // entry calls the twin instead.
-        let kernel: ItemFn = parse_quote! {
-            #[allow(unused_variables)]
-            pub fn scaled_gather<T: Copy>(a: &[T], mut c: DisjointSlice<T>) {
-                ::cuda_device::thread::__unchecked_indexing_config::<true>();
-                work(a, &mut c);
-            }
-        };
-        let expanded = generic_kernel_no_instantiation_tokens(kernel, None);
-
-        let twin = expansion_fn_source(&expanded, "__cuda_oxide_unchecked_impl_scaled_gather");
-        assert!(
-            twin.contains("allow(unused_variables)"),
-            "twin dropped the helper's lint attributes:\n{twin}"
-        );
-
-        let helper = expansion_fn_source(&expanded, "scaled_gather");
-        assert!(helper.contains("allow(unused_variables)"));
-        assert!(
-            helper.contains("allow(dead_code)"),
-            "opted helper is not allowed to go dead:\n{helper}"
-        );
-
-        // The entry wrapper is the live path; it must not be dead-code
-        // suppressed.
-        let entry = expansion_fn_source(&expanded, &format!("{KERNEL_PREFIX}scaled_gather"));
-        assert!(!entry.contains("dead_code"));
-    }
-
-    #[test]
-    fn raw_identifier_kernel_names_build_a_valid_unchecked_twin() {
-        // `Display` of `r#gen` keeps the `r#` prefix, which `Ident::new`
-        // rejects; twin naming must strip it like `format_ident!` does.
-        let kernel: ItemFn = parse_quote! {
-            pub fn r#gen<T: Copy>(value: T) {
-                ::cuda_device::thread::__unchecked_indexing_config::<true>();
-                work(value);
-            }
-        };
-
-        let expanded = generic_kernel_no_instantiation_tokens(kernel.clone(), None);
-        let twin = expansion_fn_source(&expanded, "__cuda_oxide_unchecked_impl_gen");
-        assert!(twin.contains("__unchecked_indexing_config"));
-
-        let expanded =
-            generic_kernel_instantiation_tokens(kernel, vec![parse_quote! { f32 }], None);
-        let twin = expansion_fn_source(&expanded, "__cuda_oxide_unchecked_impl_gen");
-        assert!(twin.contains("__unchecked_indexing_config"));
-    }
-
-    #[test]
-    fn generic_kernels_validate_routed_launch_contract_requires_at_source_names() {
-        // A #[launch_contract] written below #[kernel] is routed onto the
-        // generated entry wrapper, whose synthetic parameter names defeat
-        // attribute-site validation; #[kernel] must validate the relations
-        // against the original signature instead.
-        let typo: ItemFn = parse_quote! {
-            #[cuda_device::launch_contract(
-                domain = 1,
-                block = (64, 1, 1),
-                requires = (input.len() >= n),
-            )]
-            pub fn scaled<T: Copy>(input: &[T]) {}
-        };
-        let expanded = generic_kernel_no_instantiation_tokens(typo.clone(), None).to_string();
-        assert!(expanded.contains("compile_error"), "{expanded}");
-        assert!(expanded.contains("unknown identifier `n`"), "{expanded}");
-
-        let expanded =
-            generic_kernel_instantiation_tokens(typo, vec![parse_quote! { f32 }], None).to_string();
-        assert!(expanded.contains("compile_error"), "{expanded}");
-        assert!(expanded.contains("unknown identifier `n`"), "{expanded}");
-
-        let well_formed: ItemFn = parse_quote! {
-            #[cuda_device::launch_contract(
-                domain = 1,
-                block = (64, 1, 1),
-                requires = (input.len() >= n),
-            )]
-            pub fn scaled<T: Copy>(n: u32, input: &[T]) {}
-        };
-        let expanded = generic_kernel_no_instantiation_tokens(well_formed, None).to_string();
-        assert!(!expanded.contains("compile_error"), "{expanded}");
-    }
-
-    #[test]
-    fn path_spelled_unchecked_indexing_still_parses_as_instantiation_type() {
-        // The bare word is reserved for the flag, but a type literally named
-        // `unchecked_indexing` remains reachable through any path spelling.
-        for spelling in [
-            "self::unchecked_indexing",
-            "crate::unchecked_indexing",
-            "types::unchecked_indexing",
-        ] {
-            let args: KernelArgs = syn::parse_str(spelling).unwrap();
-            assert!(!args.unchecked_indexing, "`{spelling}` parsed as the flag");
-            assert_eq!(
-                args.instantiate_types.len(),
-                1,
-                "`{spelling}` did not parse as an instantiation type"
-            );
-        }
-    }
-
-    #[test]
-    fn standalone_launch_contract_validates_requires_against_fn_signature() {
-        let kernel: ItemFn = parse_quote! {
-            pub fn scaled(n: u32, input: &[f32], mut output: DisjointSlice<f32>) {}
-        };
-        let params = standalone_requires_params(&kernel).expect("source-named params must model");
-
-        let good: LaunchContractArgs = syn::parse_str(
-            "domain = 1, block = (64, 1, 1), requires = (input.len() >= n, output.len() >= n)",
-        )
-        .unwrap();
-        assert!(validate_requires_relations(&good.requires, &params).is_ok());
-
-        let typo: LaunchContractArgs =
-            syn::parse_str("domain = 1, block = (64, 1, 1), requires = (input.len() >= m)")
-                .unwrap();
-        let error = validate_requires_relations(&typo.requires, &params).unwrap_err();
-        assert!(
-            error.to_string().contains("unknown identifier `m`"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn standalone_requires_validation_skips_generated_generic_entry_wrappers() {
-        // Generic entry wrappers carry synthetic parameter names; the source
-        // relations were already validated by #[cuda_module] (or are written
-        // against names this wrapper no longer has), so the attribute-site
-        // validation must stand down rather than reject valid contracts.
-        let wrapper: ItemFn = parse_quote! {
-            fn entry<T>(__cuda_oxide_arg_0: &[T], __cuda_oxide_arg_1: u32) {}
-        };
-        assert!(standalone_requires_params(&wrapper).is_none());
-    }
-
-    #[test]
-    fn standalone_requires_models_unmarshallable_params_as_opaque_scalars() {
-        // `&bool` is rejected by the cuda_module marshaller; standalone
-        // validation still names the parameter precisely instead of calling
-        // it an unknown identifier.
-        let kernel: ItemFn = parse_quote! {
-            pub fn odd(flag: &bool, n: u32) {}
-        };
-        let params = standalone_requires_params(&kernel).unwrap();
-        let args: LaunchContractArgs =
-            syn::parse_str("domain = 1, block = (64, 1, 1), requires = (n >= flag)").unwrap();
-        let error = validate_requires_relations(&args.requires, &params).unwrap_err();
-        assert!(
-            error.to_string().contains("not an unsigned integer scalar"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn explicit_fast_functions_are_not_syntax_rewritten() {
-        let mut function: ItemFn = parse_quote! {
-            #[launch_contract(domain = 1, coordinates = u32, block = (64, 1, 1))]
-            fn ordinary_names() {
-                let local = index_1d_u32();
-                let proof = alias(launch_context);
-                consume(local, proof);
-            }
-        };
-        let scope = explicit_kernel_scope(&mut function, format_ident!("launch_context"));
-        let expanded = quote!(#function).to_string().replace(' ', "");
-
-        assert!(expanded.contains("index_1d_u32()"));
-        assert!(expanded.contains("alias(launch_context)"));
-        assert!(!expanded.contains("__internal::index_1d_u32"));
-        assert_eq!(scope.ident, "launch_context");
-    }
-
-    #[test]
-    fn uncontracted_sync_launch_is_always_unsafe() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn map(input: &[u32], mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(expanded.contains("pubunsafefnmap("));
-        assert!(expanded.contains("#Safety"));
-        assert!(expanded.contains("unverifiedrawlaunchconfiguration"));
-    }
-
-    #[test]
-    fn unsafe_source_kernel_keeps_prepared_launch_unsafe() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_contract(domain = 1, block = (64, 1, 1))]
-                pub unsafe fn map(mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(expanded.contains("pubunsafefnmap("));
-        assert!(expanded.contains("pubunsafefnmap_unchecked("));
-        #[cfg(feature = "async")]
-        {
-            assert!(expanded.contains("pubunsafefnmap_async"));
-            assert!(expanded.contains("pubunsafefnmap_async_owned"));
-        }
-    }
-
-    #[test]
-    fn contracted_module_requires_provenance_for_every_loader() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_contract(domain = 1, block = (64, 1, 1))]
-                pub fn map(mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(expanded.contains("pubunsafefnload("));
-        assert!(expanded.contains("pubunsafefnload_named("));
-        assert!(expanded.contains("pubunsafefnfrom_module("));
-        assert!(expanded.contains("#Safety"));
-        #[cfg(feature = "async")]
-        {
-            assert!(expanded.contains("pubunsafefnload_async("));
-            assert!(expanded.contains("pubunsafefnload_async_named("));
-        }
-    }
-
-    #[test]
-    fn uncontracted_module_preserves_safe_custom_loaders() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn map(mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(expanded.contains("pubfnload_named("));
-        assert!(expanded.contains("pubfnfrom_module("));
-        assert!(!expanded.contains("pubunsafefnload_named("));
-        assert!(!expanded.contains("pubunsafefnfrom_module("));
-        #[cfg(feature = "async")]
-        assert!(expanded.contains("pubfnload_async_named("));
-    }
-
-    #[test]
-    fn generic_contract_brand_and_prepare_witness_keep_specialization_type() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_bounds(128)]
-                #[launch_contract(domain = 1, dynamic_shared = 0)]
-                pub fn apply<F: Fn(u32) -> u32 + Copy>(op: F, out: *mut u32) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(expanded.contains("KernelLaunchContractfor__apply_CudaKernel<F>"));
-        assert!(expanded.contains("PreparedLaunch<__apply_CudaKernel<F>>"));
-        assert!(expanded.contains("fnprepare_apply_for<F"));
-        assert!(expanded.contains("__cuda_oxide_type_witness_0:&F"));
-        assert!(
-            expanded.contains("let__cuda_oxide_max_threads:u32=128"),
-            "{expanded}"
-        );
-        assert!(expanded.contains("BlockRequirement::MaxThreads(__cuda_oxide_max_threads)"));
-    }
-
-    #[test]
-    fn generic_kernel_routes_launch_contract_to_entry_only() {
-        let kernel: ItemFn = parse_quote! {
-            #[doc = "kept on the helper"]
-            #[cuda_device::launch_bounds(128)]
-            #[cuda_device::launch_contract(
-                domain = 1,
-                dynamic_shared = 256,
-                dynamic_shared_alignment = 64,
-            )]
-            #[cuda_device::cluster_launch(2, 1, 1)]
-            #[cuda_device::cooperative_launch]
-            pub fn map<T: Copy>(value: T) {}
-        };
-
-        let (implementation, entry, _cfg) = route_generic_kernel_attrs(&kernel.attrs);
-        let entry_names: Vec<_> = entry
-            .iter()
-            .map(|attr| attr.path().segments.last().unwrap().ident.to_string())
-            .collect();
-        let implementation_names: Vec<_> = implementation
-            .iter()
-            .map(|attr| attr.path().segments.last().unwrap().ident.to_string())
-            .collect();
-
-        assert_eq!(
-            entry_names,
-            [
-                "launch_bounds",
-                "launch_contract",
-                "cluster_launch",
-                "cooperative_launch",
-            ]
-        );
-        assert_eq!(implementation_names, ["doc"]);
-    }
-
-    #[test]
-    fn generic_kernel_forwards_only_exact_top_level_configuration_markers() {
-        let kernel: ItemFn = parse_quote! {
-            fn map<T>() {
-                ::cuda_device::thread::__launch_bounds_config::<64, 2>();
-                unsafe {
-                    ::cuda_device::thread::__launch_contract_config::<1, true>();
-                }
-                ::cuda_device::thread::__launch_contract_block_config::<64, 1, 1>();
-                ::cuda_device::cluster::__cluster_config::<2, 1, 1>();
-                ::cuda_device::shared::__dynamic_shared_alignment::<128>();
-                cuda_device::thread::__launch_bounds_config::<4, 1>();
-                unrelated();
-                other::cuda_device::thread::__launch_bounds_config::<32, 1>();
-                cuda_device::thread::__launch_bounds_config::<16, 1>(7);
-                {
-                    cuda_device::thread::__launch_bounds_config::<8, 1>();
-                }
-            }
-        };
-
-        let markers = top_level_kernel_configuration_markers(&kernel);
-        let forwarded = quote!(#(#markers)*).to_string().replace(' ', "");
-
-        assert_eq!(markers.len(), 5);
-        assert!(forwarded.contains("__launch_bounds_config::<64,2>()"));
-        assert!(forwarded.contains("__launch_contract_config::<1,true>()"));
-        assert!(forwarded.contains("__launch_contract_block_config::<64,1,1>()"));
-        assert!(forwarded.contains("__cluster_config::<2,1,1>()"));
-        assert!(forwarded.contains("__dynamic_shared_alignment::<128>()"));
-        assert!(!forwarded.contains("unrelated"));
-        assert!(!forwarded.contains("::<4,1>()"));
-        assert!(!forwarded.contains("other::cuda_device"));
-        assert!(!forwarded.contains("::<16,1>(7)"));
-        assert!(!forwarded.contains("::<8,1>()"));
-    }
-
-    #[test]
-    fn launch_contract_injects_one_alignment_marker_only_when_shared_is_used() {
-        let args: LaunchContractArgs =
-            syn::parse_str("domain = 1, dynamic_shared = 256, dynamic_shared_alignment = 64")
-                .unwrap();
-        let mut helper: ItemFn = parse_quote! { fn helper<T>() {} };
-        inject_launch_contract_markers(&args, &mut helper);
-        let expanded = quote!(#helper).to_string();
-        assert_eq!(expanded.matches("__launch_contract_config").count(), 1);
-        assert_eq!(expanded.matches("__dynamic_shared_alignment").count(), 1);
-        assert!(expanded.contains("64usize"));
-
-        let zero_args: LaunchContractArgs =
-            syn::parse_str("domain = 1, dynamic_shared = 0").unwrap();
-        let mut zero_helper: ItemFn = parse_quote! { fn zero_helper<T>() {} };
-        inject_launch_contract_markers(&zero_args, &mut zero_helper);
-        assert!(
-            !quote!(#zero_helper)
-                .to_string()
-                .contains("__dynamic_shared_alignment")
-        );
-        assert_eq!(
-            quote!(#zero_helper)
-                .to_string()
-                .matches("__launch_contract_config")
-                .count(),
-            1
-        );
-    }
-
-    #[test]
-    fn launch_contract_injects_the_block_marker_only_for_an_exact_block() {
-        let exact: LaunchContractArgs =
-            syn::parse_str("domain = 2, block = (8, 8, 1), dynamic_shared = 0").unwrap();
-        let mut kernel: ItemFn = parse_quote! { fn kernel() {} };
-        inject_launch_contract_markers(&exact, &mut kernel);
-        let expanded = quote!(#kernel).to_string().replace(' ', "");
-        assert_eq!(
-            expanded.matches("__launch_contract_block_config").count(),
-            1
-        );
-        assert!(expanded.contains("__launch_contract_block_config::<8u32,8u32,1u32>"));
-
-        // Without an exact block the kernel keeps whatever `#[launch_bounds]`
-        // declares, so no exact shape reaches the device compiler.
-        let bounded: LaunchContractArgs = syn::parse_str("domain = 1, dynamic_shared = 0").unwrap();
-        let mut unbounded_kernel: ItemFn = parse_quote! { fn unbounded_kernel() {} };
-        inject_launch_contract_markers(&bounded, &mut unbounded_kernel);
-        assert!(
-            !quote!(#unbounded_kernel)
-                .to_string()
-                .contains("__launch_contract_block_config")
-        );
-    }
-
-    #[test]
-    fn launch_contract_keeps_every_marker_when_block_and_shared_are_both_declared() {
-        let args: LaunchContractArgs = syn::parse_str(
-            "domain = 1, block = (256, 1, 1), dynamic_shared = 128, dynamic_shared_alignment = 32",
-        )
-        .unwrap();
-        let mut kernel: ItemFn = parse_quote! { fn kernel() {} };
-        inject_launch_contract_markers(&args, &mut kernel);
-        let expanded = quote!(#kernel).to_string();
-        assert_eq!(expanded.matches("__launch_contract_config").count(), 1);
-        assert_eq!(
-            expanded.matches("__launch_contract_block_config").count(),
-            1
-        );
-        assert_eq!(expanded.matches("__dynamic_shared_alignment").count(), 1);
-    }
-
-    /// The `requires` demo module used by the size-requirement tests: two
-    /// relations, one with arithmetic, over a scalar pair and two buffers.
-    fn requires_demo_module() -> ItemMod {
-        parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_contract(
-                    domain = 1,
-                    block = (128, 1, 1),
-                    requires = (input.len() >= n * stride, output.len() >= n),
-                )]
-                pub fn scaled_copy(
-                    n: u32,
-                    stride: u32,
-                    input: &[f32],
-                    mut output: DisjointSlice<f32>,
-                ) {
-                }
-            }
-        }
-    }
-
-    #[test]
-    fn requires_relations_generate_overflow_safe_checks_in_checked_launchers_only() {
-        let expanded = expand_to_compact_string(requires_demo_module());
-
-        // Every operand is widened to u64 and arithmetic goes through
-        // checked ops with a typed overflow error.
-        assert!(expanded.contains("SizeRequirementViolated"), "{expanded}");
-        assert!(expanded.contains("SizeRequirementOverflow"), "{expanded}");
-        assert!(expanded.contains("checked_mul"), "{expanded}");
-        assert!(expanded.contains("(nasu64)"), "{expanded}");
-        // The relation's source text rides along for the error message.
-        // (`expand_to_compact_string` strips spaces inside string literals
-        // too, so the expected text is compacted.)
-        assert!(expanded.contains("\"input.len()>=n*stride\""), "{expanded}");
-        assert!(expanded.contains("\"output.len()>=n\""), "{expanded}");
-
-        // Each checked launcher evaluates both relations; the `_unchecked`
-        // escape hatches never do. Without the async feature only the sync
-        // prepared launcher exists (2 relations); with it, the `_async` and
-        // `_async_owned` twins check too (2 relations each).
-        #[cfg(not(feature = "async"))]
-        assert_eq!(
-            expanded.matches("SizeRequirementViolated").count(),
-            2,
-            "{expanded}"
-        );
-        #[cfg(feature = "async")]
-        assert_eq!(
-            expanded.matches("SizeRequirementViolated").count(),
-            6,
-            "{expanded}"
-        );
-    }
-
-    #[cfg(feature = "async")]
-    #[test]
-    fn requires_relations_wrap_async_launchers_in_result() {
-        let expanded = expand_to_compact_string(requires_demo_module());
-
-        // The async launchers report a violated relation as a typed error
-        // instead of enqueueing, so their return types gain a Result.
-        assert!(
-            expanded.contains("::core::result::Result<::cuda_host::PreparedAsyncKernelLaunch<"),
-            "{expanded}"
-        );
-        assert!(
-            expanded
-                .contains("::core::result::Result<::cuda_host::PreparedOwnedAsyncKernelLaunch<"),
-            "{expanded}"
-        );
-        // Slice lengths come from the KernelSliceArg trait: by reference for
-        // the borrowed async launcher, by value for the owned one.
-        assert!(
-            expanded.contains("KernelSliceArg::len(input)"),
-            "{expanded}"
-        );
-        assert!(
-            expanded.contains("KernelSliceArg::len(&input)"),
-            "{expanded}"
-        );
-
-        // A contract without `requires` keeps the plain infallible async
-        // signatures.
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_contract(domain = 1, block = (128, 1, 1))]
-                pub fn plain(input: &[f32], mut output: DisjointSlice<f32>) {}
-            }
-        };
-        let plain = expand_to_compact_string(module);
-        assert!(
-            !plain.contains("Result<::cuda_host::PreparedAsyncKernelLaunch<"),
-            "{plain}"
-        );
-        assert!(
-            !plain.contains("Result<::cuda_host::PreparedOwnedAsyncKernelLaunch<"),
-            "{plain}"
-        );
-    }
-
-    #[test]
-    fn requires_rejects_relations_outside_the_v1_grammar() {
-        let expand_with_requires = |requires: &str| {
-            let attr = format!("domain = 1, block = (64, 1, 1), requires = ({requires})");
-            let attr: TokenStream2 = attr.parse().expect("attr tokens");
-            let module: ItemMod = parse_quote! {
-                mod kernels {
-                    #[kernel]
-                    #[launch_contract(#attr)]
-                    pub fn bad(n: u32, input: &[f32], mut output: DisjointSlice<f32>) {}
-                }
-            };
-            expand_cuda_module(module)
-        };
-        let reject = |requires: &str, expected: &str| {
-            let error = expand_with_requires(requires)
-                .expect_err(&format!("`{requires}` should be rejected"))
-                .to_string();
-            assert!(
-                error.contains(expected),
-                "`{requires}` produced unexpected error: {error}"
-            );
-        };
-
-        reject("input.len() >= 1.5", "only integer literals");
-        reject("input.len() >= 1 && output.len() >= 1", "must compare with");
-        reject("input.len() + n", "must compare with");
-        reject("input", "must be a comparison");
-        reject("input.len() as u64 >= 1", "unsupported expression");
-        reject("input.capacity() >= n", "only the `.len()` method");
-        reject(
-            "input.len() >= (n >= 1)",
-            "nested comparisons are not supported",
-        );
-        reject("input.len() >= self::n", "bare kernel parameter names");
-
-        // The full accepted grammar expands cleanly.
-        expand_with_requires("(input.len() - 1) * 2 + 0 >= n * 3")
-            .expect("grammar-conformant relation must expand");
-    }
-
-    #[test]
-    fn requires_parser_accepts_relation_lists_and_rejects_degenerate_forms() {
-        let args: LaunchContractArgs =
-            syn::parse_str("domain = 1, requires = (a.len() >= n, b.len() >= n * 2)").unwrap();
-        assert_eq!(args.requires.len(), 2);
-
-        // `.err()` instead of `.unwrap_err()`: LaunchContractArgs holds
-        // syn::Expr, which has no Debug without syn's extra-traits feature.
-        let empty = syn::parse_str::<LaunchContractArgs>("domain = 1, requires = ()")
-            .err()
-            .expect("empty requires list must be rejected");
-        assert!(empty.to_string().contains("at least one relation"));
-
-        let duplicate = syn::parse_str::<LaunchContractArgs>(
-            "domain = 1, requires = (a.len() >= 1), requires = (b.len() >= 1)",
-        )
-        .err()
-        .expect("duplicate requires key must be rejected");
-        assert!(
-            duplicate
-                .to_string()
-                .contains("duplicate launch_contract field")
-        );
-    }
-
-    #[test]
-    fn cfg_gated_duplicate_kernel_names_are_rejected_until_ptx_names_are_qualified() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[cfg(feature = "fast")]
-                pub fn step(mut out: DisjointSlice<f32>) {}
-
-                #[kernel]
-                #[cfg(not(feature = "fast"))]
-                pub fn step(mut out: DisjointSlice<f32>) {}
-            }
-        };
-        let error = expand_cuda_module(module).expect_err("bare PTX names still collide");
-        assert!(
-            error
-                .to_string()
-                .contains("PTX entry names are currently bare"),
-            "unexpected error message: {error}"
-        );
-    }
-
-    #[test]
-    fn contract_without_block_or_launch_bounds_is_rejected() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_contract(domain = 1, dynamic_shared = 0)]
-                pub fn missing_block(input: &[u32]) {}
-            }
-        };
-        let error = expand_cuda_module(module).expect_err("contract should fail closed");
-        assert!(
-            error
-                .to_string()
-                .contains("requires either an exact `block = (x, y, z)` or #[launch_bounds")
-        );
-    }
-
-    #[test]
-    fn file_backed_modules_and_include_macros_are_preserved_without_being_walked() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn top() {}
-
-                mod helper;
-                include!("helper_items.rs");
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-        assert!(
-            expanded.contains("modhelper;"),
-            "file module was changed: {expanded}"
-        );
-        assert!(
-            expanded.contains("include!(\"helper_items.rs\");"),
-            "include invocation was changed: {expanded}"
-        );
-    }
-
-    #[test]
-    fn loaded_module_is_reserved_in_nested_kernel_namespaces() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn top() {}
-
-                mod child {
-                    struct LoadedModule;
-
-                    #[kernel]
-                    pub fn nested() {}
-                }
-            }
-        };
-        let error = expand_cuda_module(module).expect_err("reserved type name must fail clearly");
-        assert!(
-            error
-                .to_string()
-                .contains("reserves the name `LoadedModule`"),
-            "unexpected error message: {error}"
-        );
-    }
-
-    #[test]
-    fn raw_and_plain_kernel_spellings_share_one_conflict_key() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                mod plain {
-                    #[kernel]
-                    fn step() {}
-                }
-
-                mod raw {
-                    #[kernel]
-                    fn r#step() {}
-                }
-            }
-        };
-        let error = expand_cuda_module(module).expect_err("raw prefix must not evade PTX guard");
-        let message = error.to_string();
-        assert!(
-            message.contains("`step`") && message.contains("plain") && message.contains("raw"),
-            "unexpected error message: {message}"
-        );
-    }
-
-    #[test]
-    fn raw_loaded_module_spelling_is_reserved() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                mod child {
-                    struct r#LoadedModule;
-
-                    #[kernel]
-                    fn nested() {}
-                }
-            }
-        };
-        let error = expand_cuda_module(module).expect_err("raw prefix must not evade reservation");
-        assert!(
-            error
-                .to_string()
-                .contains("reserves the name `LoadedModule`"),
-            "unexpected error message: {error}"
-        );
-    }
-
-    #[test]
-    fn renamed_extern_crate_cannot_claim_loaded_module() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                extern crate core as r#LoadedModule;
-
-                #[kernel]
-                fn root() {}
-            }
-        };
-        let error = expand_cuda_module(module).expect_err("extern-crate rename must be checked");
-        assert!(
-            error
-                .to_string()
-                .contains("reserves the name `LoadedModule`"),
-            "unexpected error message: {error}"
-        );
-    }
-
-    #[test]
-    fn generated_loaded_module_method_names_are_reserved() {
-        let root: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                fn as_cuda_module() {}
-            }
-        };
-        let error = expand_cuda_module(root).expect_err("root accessor name must be reserved");
-        assert!(
-            error.to_string().contains("method name `as_cuda_module`"),
-            "unexpected error message: {error}"
-        );
-
-        let nested: ItemMod = parse_quote! {
-            mod kernels {
-                mod child {
-                    #[kernel]
-                    fn from_parent() {}
-                }
-            }
-        };
-        let error =
-            expand_cuda_module(nested).expect_err("nested constructor name must be reserved");
-        assert!(
-            error.to_string().contains("method name `from_parent`"),
-            "unexpected error message: {error}"
-        );
-    }
-
-    #[test]
-    fn contracted_mut_slice_is_rejected_in_favor_of_disjoint_slice() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_contract(domain = 1, block = (64, 1, 1))]
-                pub fn aliased(out: &mut [u32]) {}
-            }
-        };
-        let error = expand_cuda_module(module).expect_err("mutable slice must fail closed");
-        assert!(
-            error
-                .to_string()
-                .contains("contracted kernels cannot take `&mut [T]`")
-        );
-    }
-
-    #[test]
-    fn disjoint_slice_packet_shape_is_bound_to_the_resolved_type() {
-        // The spelling `Rt` hides a runtime row width, so the macro selects
-        // the two-word host ABI. The generated launch methods must carry the
-        // semantic `HAS_ROW_WIDTH = false` bound for Rust to reject at the call
-        // site once `Rt` resolves to a runtime-width index space.
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                type Rt = RuntimeRowMajorTiles<1, 1>;
-
-                #[kernel]
-                pub fn alias_hides_row_width(mut out: DisjointSlice<f32, Rt>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-        assert!(
-            expanded.contains(
-                "for<'__cuda_oxide_disjoint>DisjointSlice<'__cuda_oxide_disjoint,f32,Rt>:\
-                 ::cuda_device::__LaunchContractDisjointSliceAbi<f32,false>"
-            ),
-            "flat spelling must bind HAS_ROW_WIDTH = false: {expanded}"
-        );
-
-        // The direct spelling selects the three-word ABI and must bind
-        // `HAS_ROW_WIDTH = true`.
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn really_has_row_width(mut out: DisjointSlice<f32, Runtime2DIndex>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-        assert!(
-            expanded.contains(
-                "for<'__cuda_oxide_disjoint>DisjointSlice<'__cuda_oxide_disjoint,f32,\
-                 Runtime2DIndex>:::cuda_device::__LaunchContractDisjointSliceAbi<f32,true>"
-            ),
-            "runtime-width spelling must bind HAS_ROW_WIDTH = true: {expanded}"
-        );
-    }
-
-    #[test]
-    fn aliased_disjoint_index_space_is_checked_by_rust_type_resolution() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                type Alias = Index2D<128>;
-
-                #[kernel]
-                #[launch_contract(domain = 2, block = (16, 16, 1))]
-                pub fn aliased(mut out: DisjointSlice<u32, Alias>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(
-            expanded.contains(
-                "for<'__cuda_oxide_disjoint>DisjointSlice<'__cuda_oxide_disjoint,u32,Alias>:"
-            ),
-            "the bound must preserve the original index-space alias: {expanded}"
-        );
-        assert!(expanded.contains("__LaunchContractDisjointSlice<u32,2u8>"));
-    }
-
-    #[test]
-    fn one_dimensional_index_space_is_not_accepted_by_identifier_spelling() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                type Index2D = Index1D;
-
-                #[kernel]
-                #[launch_contract(domain = 2, block = (16, 16, 1))]
-                pub fn wrong_rank(mut out: DisjointSlice<u32, Index2D>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(
-            expanded.contains(
-                "for<'__cuda_oxide_disjoint>DisjointSlice<'__cuda_oxide_disjoint,u32,Index2D>:"
-            ),
-            "the bound must preserve the misleading alias for Rust to resolve: {expanded}"
-        );
-        assert!(expanded.contains("__LaunchContractDisjointSlice<u32,2u8>"));
-    }
-
-    #[test]
-    fn local_disjoint_slice_lookalike_gets_the_genuine_type_bound() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                struct DisjointSlice<'a, T, IndexSpace = Index1D> {
-                    value: &'a mut T,
-                    index: PhantomData<IndexSpace>,
-                }
-
-                #[kernel]
-                #[launch_contract(domain = 1, block = (64, 1, 1))]
-                pub fn fake(mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(
-            expanded
-                .contains("for<'__cuda_oxide_disjoint>DisjointSlice<'__cuda_oxide_disjoint,u32>:"),
-            "the look-alike must receive the genuine cuda-device trait bound: {expanded}"
-        );
-        assert!(expanded.contains("__LaunchContractDisjointSlice<u32,1u8>"));
-    }
-
-    #[test]
-    fn launch_bounds_accepts_a_two_dimensional_block_with_the_same_product() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_bounds(256)]
-                #[launch_contract(domain = 2, block = (16, 16, 1))]
-                pub fn tiled(input: &[u32]) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-        assert!(expanded.contains("BlockRequirement::Exact((16u32,16u32,1u32))"));
-    }
-
-    #[test]
-    fn exact_block_cannot_exceed_compiled_launch_bounds_thread_count() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_bounds(256)]
-                #[launch_contract(domain = 2, block = (17, 16, 1))]
-                pub fn impossible(input: &[u32]) {}
-            }
-        };
-        let error = expand_cuda_module(module).expect_err("bounds mismatch must fail closed");
-        assert!(error.to_string().contains("272 threads"));
-        assert!(error.to_string().contains("launch_bounds(256)"));
-    }
-
-    #[cfg(feature = "async")]
-    #[test]
-    fn contracted_async_methods_return_immutable_wrappers() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_contract(domain = 1, block = (64, 1, 1))]
-                pub fn map(input: &[u32], mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(
-            expanded.contains("PreparedAsyncKernelLaunch<'__cuda_oxide_async,__map_CudaKernel>")
-        );
-        assert!(expanded.contains("PreparedOwnedAsyncKernelLaunch<"));
-        assert!(expanded.contains("fnmap_async_unchecked"));
-        assert!(expanded.contains("fnmap_async_owned_unchecked"));
-        assert!(expanded.matches("unsafe").count() >= 4);
-    }
-
-    #[cfg(feature = "async")]
-    #[test]
-    fn uncontracted_async_launch_methods_are_always_unsafe() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                pub fn map(input: &[u32], mut out: DisjointSlice<u32>) {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(expanded.contains("pubunsafefnmap_async"));
-        assert!(expanded.contains("pubunsafefnmap_async_owned"));
-        assert_eq!(
-            expanded.matches("new_async_kernel_launch_builder").count(),
-            2
-        );
-        assert_eq!(expanded.matches("finalize_unchecked").count(), 2);
-    }
-
-    #[test]
-    fn raw_async_launch_macro_leaves_finalization_caller_unsafe() {
-        let inputs: [CudaLaunchAsyncInput; 3] = [
-            parse_quote! {
-                kernel: kernels::map,
-                module: module,
-                config: config,
-                args: []
-            },
-            parse_quote! {
-                kernel: kernels::map::<u32>,
-                module: module,
-                config: config,
-                args: []
-            },
-            parse_quote! {
-                kernel: kernels::map,
-                module: module,
-                config: config,
-                args: [|value: u32| value]
-            },
-        ];
-
-        for input in inputs {
-            let expanded = expand_cuda_launch_async(input).to_string().replace(' ', "");
-            assert!(expanded.contains("AsyncKernelLaunchBuilder::new"));
-            assert!(expanded.contains(".finalize_unchecked(config)"));
-            assert!(!expanded.contains("set_launch_config"));
-            assert!(
-                !expanded.contains("unsafe{"),
-                "the macro must not hide its raw-launch safety obligation: {expanded}"
-            );
-        }
-    }
-
-    /// Runs the per-loop `#[unroll]` visitor over `func`'s body and returns the
-    /// rewritten function as a whitespace-free string, panicking on any
-    /// recorded parse error.
-    fn run_loop_unroll_visitor(mut func: ItemFn) -> String {
-        rewrite_loop_unroll_attrs(&mut func)
-            .unwrap_or_else(|err| panic!("unexpected unroll-attr error: {err}"));
-        quote!(#func).to_string().replace(' ', "")
-    }
-
-    #[test]
-    fn bare_unroll_on_while_injects_factor_zero_marker() {
-        let func: ItemFn = parse_quote! {
-            fn k() {
-                let mut i = 0u32;
-                #[unroll]
-                while i < 4 { i += 1; }
-            }
-        };
-        let out = run_loop_unroll_visitor(func);
-        // Bare #[unroll] => full unroll (factor 0).
-        assert!(
-            out.contains("cuda_device::thread::__unroll_config::<{0u32}>()"),
-            "expected factor-0 marker:\n{out}"
-        );
-        // The expression attribute must be stripped so rustc never sees it.
-        assert!(
-            !out.contains("#[unroll]"),
-            "the #[unroll] attribute should be removed:\n{out}"
-        );
-    }
-
-    #[test]
-    fn unroll_n_on_for_loop_injects_factor_n_marker() {
-        let func: ItemFn = parse_quote! {
-            fn k() {
-                #[unroll(4)]
-                for i in 0..8 { let _ = i; }
-            }
-        };
-        let out = run_loop_unroll_visitor(func);
-        assert!(
-            out.contains("cuda_device::thread::__unroll_config::<{4}>()"),
-            "expected factor-4 marker:\n{out}"
-        );
-        assert!(
-            !out.contains("#[unroll"),
-            "attribute should be removed:\n{out}"
-        );
-    }
-
-    #[test]
-    fn unroll_on_bare_loop_injects_marker() {
-        let func: ItemFn = parse_quote! {
-            fn k() {
-                #[unroll(2)]
-                loop { break; }
-            }
-        };
-        let out = run_loop_unroll_visitor(func);
-        assert!(
-            out.contains("cuda_device::thread::__unroll_config::<{2}>()"),
-            "expected factor-2 marker on `loop`:\n{out}"
-        );
-    }
-
-    #[test]
-    fn nested_annotated_loop_is_handled() {
-        let func: ItemFn = parse_quote! {
-            fn k() {
-                for outer in 0..2 {
-                    if outer == 0 {
-                        #[unroll(3)]
-                        for inner in 0..4 { let _ = inner; }
-                    }
-                }
-            }
-        };
-        let out = run_loop_unroll_visitor(func);
-        assert!(
-            out.contains("cuda_device::thread::__unroll_config::<{3}>()"),
-            "expected marker injected into nested loop:\n{out}"
-        );
-    }
-
-    #[test]
-    fn loop_without_unroll_attr_is_unchanged() {
-        // A function whose loops carry no #[unroll] must be byte-identical
-        // before and after the visitor runs (no marker, no edits).
-        let src: ItemFn = parse_quote! {
-            fn k() {
-                let mut i = 0u32;
-                while i < 4 { i += 1; }
-                for j in 0..2 { let _ = j; }
-            }
-        };
-        let before = quote!(#src).to_string();
-        let after = run_loop_unroll_visitor(src);
-        assert_eq!(
-            before.replace(' ', ""),
-            after,
-            "loops without #[unroll] must not be modified"
-        );
-        assert!(
-            !after.contains("__unroll_config"),
-            "no marker should be injected without #[unroll]:\n{after}"
-        );
-    }
-
-    #[test]
-    fn malformed_unroll_attr_records_error() {
-        // `#[unroll(1, 2)]` has too many args; the visitor must record an error.
-        let mut func: ItemFn = parse_quote! {
-            fn k() {
-                #[unroll(1, 2)]
-                for i in 0..4 { let _ = i; }
-            }
-        };
-        let mut visitor = LoopUnrollAttrVisitor::default();
-        visitor.visit_block_mut(&mut func.block);
-        assert!(
-            visitor.error.is_some(),
-            "malformed #[unroll(1, 2)] should record a parse error"
-        );
-    }
-
-    #[test]
-    fn partial_unroll_factor_must_be_at_least_two() {
-        assert!(syn::parse_str::<UnrollArgs>("0").is_err());
-        assert!(syn::parse_str::<UnrollArgs>("1").is_err());
-        assert_eq!(
-            syn::parse_str::<UnrollArgs>("2")
-                .unwrap()
-                .factor
-                .literal_value,
-            Some(2)
-        );
-        assert!(syn::parse_str::<UnrollArgs>("1025").is_err());
-    }
-
-    #[test]
-    fn launch_bounds_keeps_policy_expressions_typed() {
-        let mut function: ItemFn = parse_quote! {
-            fn configured<P: Policy>() {}
-        };
-        let args: LaunchBoundsArgs = syn::parse_str("P::MAX_THREADS * 2, P::MIN_BLOCKS").unwrap();
-        add_const_evaluatable_bound(&mut function.sig.generics, &args.max_threads);
-        add_const_evaluatable_bound(&mut function.sig.generics, &args.min_blocks);
-
-        let max_threads = &args.max_threads.expr;
-        let min_blocks = &args.min_blocks.expr;
-        let marker: Stmt = parse_quote! {
-            ::cuda_device::thread::__launch_bounds_config::<
-                { #max_threads },
-                { #min_blocks },
-            >();
-        };
-        function.block.stmts.insert(0, marker);
-        let output = quote!(#function).to_string().replace(' ', "");
-
-        assert!(
-            output.contains("__launch_bounds_config"),
-            "missing marker: {output}"
-        );
-        assert!(output.contains("{P::MAX_THREADS*2}"), "{output}");
-        assert!(output.contains("{P::MIN_BLOCKS}"), "{output}");
-        assert!(output.contains("[();(P::MAX_THREADS*2)asusize]:"));
-        assert!(output.contains("[();(P::MIN_BLOCKS)asusize]:"));
-    }
-
-    #[test]
-    fn policy_unroll_expression_gets_marker_and_evaluatability_bound() {
-        let func: ItemFn = parse_quote! {
-            fn k<P: Policy>() {
-                let mut i = 0u32;
-                #[unroll(P::UNROLL)]
-                while i < 8 { i += 1; }
-            }
-        };
-        let output = run_loop_unroll_visitor(func);
-
-        assert!(output.contains("__unroll_config::<{P::UNROLL}>()"));
-        assert!(output.contains("[();(P::UNROLL)asusize]:"));
-    }
-
-    #[test]
-    fn function_local_unroll_const_stays_in_block_scope() {
-        let func: ItemFn = parse_quote! {
-            fn k() {
-                const FACTOR: u32 = 4;
-                let mut i = 0u32;
-                #[unroll(FACTOR)]
-                while i < 8 { i += 1; }
-            }
-        };
-        let output = run_loop_unroll_visitor(func);
-
-        assert!(output.contains("__unroll_config::<{FACTOR}>()"));
-        assert!(
-            !output.contains("[();(FACTOR)asusize]:"),
-            "a block-local const must not be copied into the function signature: {output}"
-        );
-    }
-
-    #[test]
-    fn cuda_module_host_methods_keep_policy_expression_bounds() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_bounds(P::MAX_THREADS, P::MIN_BLOCKS)]
-                pub fn configured<P: Policy>() {
-                    let mut i = 0u32;
-                    #[unroll(P::UNROLL)]
-                    while i < 8 { i += 1; }
-                }
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(expanded.contains("[();(P::MAX_THREADS)asusize]:"));
-        assert!(expanded.contains("[();(P::MIN_BLOCKS)asusize]:"));
-        assert!(expanded.contains("[();(P::UNROLL)asusize]:"));
-        assert!(expanded.contains("pubfnconfigured<P:Policy>"));
-    }
-
-    #[test]
-    fn nested_cuda_module_host_methods_keep_policy_expression_bounds() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                pub mod stage {
-                    use super::*;
-
-                    #[kernel]
-                    #[launch_bounds(P::MAX_THREADS, P::MIN_BLOCKS)]
-                    pub fn configured<P: Policy>() {
-                        let mut i = 0u32;
-                        #[unroll(P::UNROLL)]
-                        while i < 8 { i += 1; }
-                    }
-                }
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(expanded.contains("pubmodstage"));
-        assert!(expanded.contains("from_parent(parent:&super::LoadedModule"));
-        assert!(expanded.contains("[();(P::MAX_THREADS)asusize]:"));
-        assert!(expanded.contains("[();(P::MIN_BLOCKS)asusize]:"));
-        assert!(expanded.contains("[();(P::UNROLL)asusize]:"));
-        assert!(expanded.contains("pubfnconfigured<P:Policy>"));
-    }
-
-    #[test]
-    fn launch_contract_carries_deferred_launch_bounds_into_host_spec() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_bounds(P::MAX_THREADS)]
-                #[launch_contract(domain = 1)]
-                pub fn configured<P: Policy>() {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(
-            expanded.contains("let__cuda_oxide_max_threads:u32=P::MAX_THREADS"),
-            "policy maximum must be part of the host contract: {expanded}"
-        );
-        assert!(
-            expanded.contains("__cuda_oxide_max_threads>0"),
-            "{expanded}"
-        );
-        assert!(expanded.contains("BlockRequirement::MaxThreads(__cuda_oxide_max_threads)"));
-        assert!(expanded.contains("[();(P::MAX_THREADS)asusize]:"));
-    }
-
-    #[test]
-    fn exact_block_checks_a_deferred_launch_bound_per_specialization() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_bounds(P::MAX_THREADS)]
-                #[launch_contract(domain = 1, block = (64, 1, 1))]
-                pub fn configured<P: Policy>() {}
-            }
-        };
-        let expanded = expand_to_compact_string(module);
-
-        assert!(
-            expanded.contains("BlockRequirement::Exact((64u32,1u32,1u32))"),
-            "an explicit block must remain exact: {expanded}"
-        );
-        assert!(
-            expanded.contains("64u128<=(__cuda_oxide_max_threads)asu128"),
-            "the policy bound must be checked for each specialization: {expanded}"
-        );
-    }
-
-    #[test]
-    fn launch_contract_allows_deferred_minimum_blocks() {
-        let module: ItemMod = parse_quote! {
-            mod kernels {
-                #[kernel]
-                #[launch_bounds(256, P::MIN_BLOCKS)]
-                #[launch_contract(domain = 1)]
-                pub fn configured<P: Policy>() {}
-            }
-        };
-
-        expand_cuda_module(module).expect(
-            "minimum blocks affects device occupancy metadata, not the host launch contract",
-        );
-    }
-
-    /// The two hygiene regressions for the injected launch-context scope spell
-    /// `KERNEL_SCOPE_LOCAL`-derived names as *identifiers*, so no compiler
-    /// check ties them back to the constant. Rename the constant and both
-    /// fixtures quietly stop colliding with the generated bindings: they keep
-    /// passing while testing nothing, because there is no longer anything to
-    /// collide with. Pin the coupling so a rename fails here and names the
-    /// fixtures that have to move with it.
-    #[test]
-    fn hygiene_fixtures_still_collide_with_the_generated_scope_names() {
-        let storage = format!("{KERNEL_SCOPE_LOCAL}_storage");
-
-        let launch_context = include_str!("../tests/pass/kernel_launch_context_api.rs");
-        assert!(
-            launch_context.contains(&storage),
-            "tests/pass/kernel_launch_context_api.rs must bind `{storage}` so \
-             `generated_storage_name_is_hygienic` exercises the mixed-site \
-             hygiene of the generated storage binding"
-        );
-
-        let const_generic =
-            include_str!("../../rustc-codegen-cuda/examples/const_generic/src/main.rs");
-        assert!(
-            const_generic.contains(KERNEL_SCOPE_LOCAL),
-            "examples/const_generic must declare a const generic named \
-             `{KERNEL_SCOPE_LOCAL}` so `call_site_ident_avoiding_item` is \
-             forced down its rename path"
-        );
-    }
-}
diff --git a/crates/cuda-macros/src/tests/cuda_module.rs b/crates/cuda-macros/src/tests/cuda_module.rs
new file mode 100644
index 0000000000..3f5cebc413
--- /dev/null
+++ b/crates/cuda-macros/src/tests/cuda_module.rs
@@ -0,0 +1,1266 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::cuda_module::contract::LaunchContractArgs;
+use crate::cuda_module::{
+    device_codegen_owner_selection, expand_cuda_module, expand_cuda_module_inner,
+    transform_cuda_module_items,
+};
+use proc_macro2::TokenStream as TokenStream2;
+use quote::quote;
+use reserved_oxide_symbols::PTX_MERGE_REQUIRED_PREFIX;
+use reserved_oxide_symbols::ptx_merge_required_marker;
+use syn::{ItemMod, parse_quote};
+
+/// Expands a `#[cuda_module]` body and returns the generated tokens as a
+/// whitespace-free string, so tests can assert on call paths without
+/// caring how `quote!` spaces out `::` separators.
+fn expand_to_compact_string(module: ItemMod) -> String {
+    expand_cuda_module(module)
+        .expect("cuda_module expansion failed")
+        .to_string()
+        .replace(' ', "")
+}
+
+/// Expands a `#[cuda_module]` body with the host surface suppressed.
+fn expand_device_only_to_compact_string(module: ItemMod) -> String {
+    expand_cuda_module_inner(module, false)
+        .expect("cuda_module expansion failed")
+        .to_string()
+        .replace(' ', "")
+}
+
+fn one_kernel_module() -> ItemMod {
+    parse_quote! {
+        mod kernels {
+            #[kernel]
+            fn scale(out: *mut f32) {}
+        }
+    }
+}
+
+/// With the host surface off, nothing in the expansion may name the
+/// `cuda-host` -> `cuda-core` -> `cuda-bindings` -> `cuda.h` stack. That is
+/// the whole point of the feature: a crate that only compiles kernels
+/// should not have to build it.
+#[test]
+fn device_only_cuda_module_names_no_host_crate() {
+    let expanded = expand_device_only_to_compact_string(one_kernel_module());
+    assert!(
+        !expanded.contains("cuda_host"),
+        "device-only expansion must not name cuda_host: {expanded}"
+    );
+    assert!(
+        !expanded.contains("cuda_core"),
+        "device-only expansion must not name cuda_core: {expanded}"
+    );
+    assert!(
+        !expanded.contains("LoadedModule"),
+        "device-only expansion must not emit the loader type: {expanded}"
+    );
+}
+
+/// Gating must remove only the host surface. The kernel itself still has
+/// to reach the codegen collector.
+#[test]
+fn device_only_cuda_module_still_emits_the_kernel() {
+    let expanded = expand_device_only_to_compact_string(one_kernel_module());
+    assert!(
+        expanded.contains("#[kernel]fnscale"),
+        "the kernel must survive gating: {expanded}"
+    );
+}
+
+/// The default build is unchanged: this is the additive half of the
+/// contract, and existing consumers depend on it.
+#[test]
+fn host_cuda_module_still_emits_the_loader() {
+    let expanded = expand_to_compact_string(one_kernel_module());
+    assert!(
+        expanded.contains("::cuda_host::") && expanded.contains("LoadedModule"),
+        "host expansion must keep the loader: {expanded}"
+    );
+}
+
+/// A nested inline module gets its own `LoadedModule`, so it needs the
+/// same gate as the outer one.
+#[test]
+fn device_only_nested_module_emits_no_loader() {
+    let module: ItemMod = parse_quote! {
+        mod outer {
+            mod inner {
+                #[kernel]
+                fn scale(out: *mut f32) {}
+            }
+        }
+    };
+    let expanded = expand_device_only_to_compact_string(module);
+    assert!(
+        !expanded.contains("LoadedModule") && !expanded.contains("cuda_host"),
+        "nested device-only expansion must emit no loader: {expanded}"
+    );
+}
+
+#[test]
+fn device_codegen_owner_selection_matches_backend_name_rules() {
+    assert_eq!(device_codegen_owner_selection(None, "gpu_lib"), None);
+    assert_eq!(device_codegen_owner_selection(Some(" , "), "gpu_lib"), None);
+    assert_eq!(
+        device_codegen_owner_selection(Some("gpu-lib, math_gpu"), "gpu_lib"),
+        Some(true)
+    );
+    assert_eq!(
+        device_codegen_owner_selection(Some("gpu-lib, math_gpu"), "host_app"),
+        Some(false)
+    );
+}
+
+#[test]
+fn cooperative_kernel_launches_through_cooperative_driver_call() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[cooperative_launch]
+            pub fn grid_sync_kernel(mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    // The sync launch method must route through the cooperative driver
+    // entry point (cuLaunchKernelEx + CU_LAUNCH_ATTRIBUTE_COOPERATIVE)
+    // instead of plain cuLaunchKernel.
+    assert!(
+        expanded.contains("launch_kernel_cooperative_on_stream"),
+        "expected cooperative launch call in generated tokens:\n{expanded}"
+    );
+    assert!(
+        !expanded.contains("launch_kernel_on_stream"),
+        "plain launch call should be replaced by the cooperative one:\n{expanded}"
+    );
+}
+
+#[test]
+fn plain_kernel_keeps_plain_driver_call() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn plain_kernel(mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(
+        expanded.contains("launch_kernel_on_stream"),
+        "expected plain launch call in generated tokens:\n{expanded}"
+    );
+    assert!(
+        !expanded.contains("launch_kernel_cooperative_on_stream"),
+        "cooperative call must not appear without #[cooperative_launch]:\n{expanded}"
+    );
+}
+
+#[test]
+fn cuda_module_routes_type_and_const_generics_through_name_helper() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn mixed<'a, T: Copy + 'a, const N: usize>(
+                input: &'a [T],
+                output: &mut [T],
+            ) {
+            }
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(
+        expanded.contains("mixed_ptx_name::<T,N>()"),
+        "typed launch must forward type and const arguments to the name helper:\n{expanded}"
+    );
+    assert!(
+        expanded.contains(PTX_MERGE_REQUIRED_PREFIX),
+        "generic cuda_module must emit the compiler-visible PTX-merge marker:\n{expanded}"
+    );
+}
+
+#[test]
+fn non_generic_cuda_module_does_not_emit_ptx_merge_marker() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn plain(output: &mut [u32]) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(
+        !expanded.contains(PTX_MERGE_REQUIRED_PREFIX),
+        "non-generic cuda_module must remain eligible for cubin materialization:\n{expanded}"
+    );
+}
+
+#[test]
+fn cfg_gated_generic_uses_the_same_gate_for_marker_and_loader() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn plain(output: &mut [u32]) {}
+
+            #[cfg(feature = "generic")]
+            #[kernel]
+            pub fn optional<T: Copy>(value: T) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+    let marker = ptx_merge_required_marker("optional");
+
+    assert!(
+            expanded.contains(&format!(
+                "#[cfg(feature=\"generic\")]#[doc(hidden)]#[used]#[allow(dead_code,non_upper_case_globals)]static{marker}:u8=0"
+            )),
+            "marker must inherit the generic kernel's cfg:\n{expanded}"
+        );
+    assert!(
+        expanded.contains(
+            "#[cfg(feature=\"generic\")]let_={__cuda_oxide_has_enabled_generic_kernel=true;};"
+        ),
+        "loader selection must inherit the generic kernel's cfg:\n{expanded}"
+    );
+    assert!(
+            expanded.contains("if__cuda_oxide_has_enabled_generic_kernel{let_=name;::cuda_host::load_all_ptx_bundles_merged(ctx)?}else{::cuda_host::load_embedded_module(ctx,name)?}"),
+            "loader must fall back to the embedded artifact when no generic kernel is enabled:\n{expanded}"
+        );
+}
+
+#[test]
+fn nested_generic_marker_inherits_every_ancestor_cfg() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[cfg(feature = "outer")]
+            mod nested {
+                #[cfg(target_os = "linux")]
+                #[kernel]
+                pub fn map<T: Copy>(value: T) {}
+            }
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+    let marker = ptx_merge_required_marker("map");
+    assert!(
+            expanded.contains(&format!(
+                "#[cfg(feature=\"outer\")]#[cfg(target_os=\"linux\")]#[doc(hidden)]#[used]#[allow(dead_code,non_upper_case_globals)]static{marker}:u8=0"
+            )),
+            "root marker must use the nested kernel's effective cfg chain:\n{expanded}"
+        );
+}
+
+#[test]
+fn cooperative_plus_cluster_kernel_uses_combined_driver_call() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[cluster_launch(2, 1, 1)]
+            #[cooperative_launch]
+            pub fn clustered_grid_sync_kernel(mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    // cuLaunchKernelEx accepts both attributes in one attrs array, so the
+    // combination is allowed and routes through the combined helper.
+    assert!(
+        expanded.contains("launch_kernel_ex_cooperative_on_stream"),
+        "expected combined cluster+cooperative launch call:\n{expanded}"
+    );
+    assert!(
+        !expanded.contains("launch_kernel_ex_on_stream"),
+        "cluster-only call should be replaced by the combined one:\n{expanded}"
+    );
+}
+
+#[cfg(feature = "async")]
+#[test]
+fn cooperative_kernel_sets_async_builder_knob() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[cooperative_launch]
+            pub fn grid_sync_kernel(mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    // Both the borrowed-async and owned-async builder methods set the
+    // cooperative knob, exactly like set_async_kernel_cluster_dim is set
+    // for #[cluster_launch].
+    assert_eq!(
+        expanded.matches("set_async_kernel_cooperative").count(),
+        2,
+        "expected the cooperative knob in both async builder methods:\n{expanded}"
+    );
+}
+
+#[test]
+fn cooperative_launch_with_arguments_is_rejected() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[cooperative_launch(4)]
+            pub fn grid_sync_kernel(mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let error = expand_cuda_module(module).expect_err("expected expansion to fail");
+    assert!(
+        error
+            .to_string()
+            .contains("cooperative_launch takes no arguments"),
+        "unexpected error message: {error}"
+    );
+}
+
+#[test]
+fn nested_inline_module_kernels_generate_namespace_local_launchers() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn top(mut out: DisjointSlice<u32>) {}
+
+            pub mod stage1 {
+                #[kernel]
+                pub fn scale(mut out: DisjointSlice<f32>) {}
+            }
+
+            pub mod stage2 {
+                pub mod inner {
+                    #[kernel]
+                    pub fn shift(mut out: DisjointSlice<f32>) {}
+                }
+            }
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+    assert!(
+        expanded.contains("pubmodstage1{#[kernel]pubfnscale")
+            && expanded.contains("<__scale_CudaKernelas::cuda_host::CudaKernel>"),
+        "expected the stage1 launcher to resolve its marker locally:\n{expanded}"
+    );
+    assert!(
+        expanded.contains("pubmodinner{#[kernel]pubfnshift")
+            && expanded.contains("<__shift_CudaKernelas::cuda_host::CudaKernel>"),
+        "expected the doubly nested launcher to resolve its marker locally:\n{expanded}"
+    );
+    assert!(
+        expanded.matches("pubstructLoadedModule").count() == 4,
+        "expected root, stage1, stage2, and inner module views:\n{expanded}"
+    );
+    assert!(
+        expanded.contains("from_parent(parent:&super::LoadedModule")
+            && expanded.contains("parent.__generic_functions.clone()"),
+        "expected nested views to share the parent module and cache:\n{expanded}"
+    );
+}
+
+#[test]
+fn nested_launch_contract_stays_in_its_namespace_and_taints_root_loading() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            pub mod stage {
+                #[kernel]
+                #[launch_contract(domain = 1, block = (64, 1, 1))]
+                pub fn map(mut out: DisjointSlice<u32>) {}
+            }
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert_eq!(
+        expanded
+            .matches("impl::cuda_core::KernelLaunchContract")
+            .count(),
+        1,
+        "the contract impl must be emitted once in the child namespace:\n{expanded}"
+    );
+    assert_eq!(
+        expanded.matches("fnprepare_map(").count(),
+        1,
+        "the prepared launcher must be emitted once in the child namespace:\n{expanded}"
+    );
+    assert!(
+        expanded.contains("pubunsafefnload("),
+        "a descendant contract must make root artifact binding unsafe:\n{expanded}"
+    );
+    assert!(
+        expanded.contains("pubmodstage{")
+            && expanded.contains("from_parent(parent:&super::LoadedModule"),
+        "main's nested module view must remain intact:\n{expanded}"
+    );
+}
+
+#[test]
+fn nested_generic_kernel_uses_local_ptx_name_helper() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn top(mut out: DisjointSlice<u32>) {}
+
+            pub mod stage1 {
+                #[kernel]
+                pub fn map<F: Fn(f32) -> f32 + Copy>(f: F, mut out: DisjointSlice<f32>) {}
+            }
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+    assert!(
+        expanded.contains("let__cuda_oxide_ptx_name=map_ptx_name::<F>()"),
+        "expected the generic binding to call the namespace-local ptx-name helper:\n{expanded}"
+    );
+    assert!(
+        !expanded.contains("stage1::map_ptx_name"),
+        "the nested launcher must not resolve its private helper from the parent:\n{expanded}"
+    );
+}
+
+#[test]
+fn nested_kernel_tracks_local_and_effective_cfg_availability() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[cfg(feature = "outer")]
+            mod outer {
+                #[cfg_attr(feature = "inner", cfg(target_os = "linux"), allow(dead_code))]
+                mod inner {
+                    #[cfg(target_arch = "x86_64")]
+                    #[kernel]
+                    fn nested() {}
+                }
+            }
+        }
+    };
+    let items = &module.content.expect("inline module").1;
+    let transformed =
+        transform_cuda_module_items(items, &mut Vec::new(), &[], false, true).unwrap();
+    let kernel = transformed
+        .kernels
+        .iter()
+        .find(|kernel| kernel.fn_name == "nested")
+        .expect("nested kernel was not collected");
+    let local_attrs = &kernel.cfg_attrs;
+    let effective_attrs = &kernel.effective_cfg_attrs;
+    let local = quote!(#(#local_attrs)*).to_string().replace(' ', "");
+    let effective = quote!(#(#effective_attrs)*).to_string().replace(' ', "");
+
+    assert_eq!(local, "#[cfg(target_arch=\"x86_64\")]");
+    assert!(effective.contains("#[cfg(feature=\"outer\")]"));
+    assert!(effective.contains("#[cfg_attr(feature=\"inner\",cfg(target_os=\"linux\"))]"));
+    assert!(!effective.contains("allow(dead_code)"));
+    assert!(effective.ends_with("#[cfg(target_arch=\"x86_64\")]"));
+}
+
+#[test]
+fn conflicting_kernel_names_across_modules_are_rejected() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            pub mod stage1 {
+                #[kernel]
+                pub fn step(mut out: DisjointSlice<f32>) {}
+            }
+
+            pub mod stage2 {
+                #[kernel]
+                pub fn step(mut out: DisjointSlice<f32>) {}
+            }
+        }
+    };
+    let error = expand_cuda_module(module).expect_err("expected expansion to fail");
+    let message = error.to_string();
+    assert!(
+        message.contains("requires kernel names to be unique")
+            && message.contains("stage1")
+            && message.contains("stage2"),
+        "unexpected error message: {message}"
+    );
+}
+
+#[test]
+fn launch_contract_generates_prepared_and_unsafe_raw_paths() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_bounds(256)]
+            #[launch_contract(
+                domain = 1,
+                coordinates = u32,
+                block = (256, 1, 1),
+                dynamic_shared = 1024,
+                dynamic_shared_alignment = 128,
+                min_compute_capability = (8, 0),
+            )]
+            pub fn map(input: &[u32], mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(expanded.contains("impl::cuda_core::KernelLaunchContractfor__map_CudaKernel"));
+    assert!(expanded.contains("typeConfig=::cuda_core::LaunchConfig1D"));
+    assert!(expanded.contains("fnprepare_map("));
+    assert!(expanded.contains("PreparedLaunch<__map_CudaKernel>"));
+    assert!(expanded.contains("fnmap("));
+    assert!(
+        !expanded.contains("unsafefnmap("),
+        "a safe source kernel must keep its prepared launch method safe: {expanded}"
+    );
+    assert!(
+        expanded.contains("__cuda_oxide_prepared:&::cuda_core::PreparedLaunch<__map_CudaKernel>")
+    );
+    assert!(expanded.contains("unsafefnmap_unchecked("));
+    assert!(expanded.contains("__cuda_oxide_config:::cuda_core::LaunchConfig"));
+    assert!(expanded.contains("min_alignment:128u32"));
+    assert!(expanded.contains("with_min_compute_capability(8u32,0u32)"));
+    assert!(expanded.contains("with_u32_coordinates()"));
+}
+
+#[test]
+fn uncontracted_sync_launch_is_always_unsafe() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn map(input: &[u32], mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(expanded.contains("pubunsafefnmap("));
+    assert!(expanded.contains("#Safety"));
+    assert!(expanded.contains("unverifiedrawlaunchconfiguration"));
+}
+
+#[test]
+fn unsafe_source_kernel_keeps_prepared_launch_unsafe() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_contract(domain = 1, block = (64, 1, 1))]
+            pub unsafe fn map(mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(expanded.contains("pubunsafefnmap("));
+    assert!(expanded.contains("pubunsafefnmap_unchecked("));
+    #[cfg(feature = "async")]
+    {
+        assert!(expanded.contains("pubunsafefnmap_async"));
+        assert!(expanded.contains("pubunsafefnmap_async_owned"));
+    }
+}
+
+#[test]
+fn contracted_module_requires_provenance_for_every_loader() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_contract(domain = 1, block = (64, 1, 1))]
+            pub fn map(mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(expanded.contains("pubunsafefnload("));
+    assert!(expanded.contains("pubunsafefnload_named("));
+    assert!(expanded.contains("pubunsafefnfrom_module("));
+    assert!(expanded.contains("#Safety"));
+    #[cfg(feature = "async")]
+    {
+        assert!(expanded.contains("pubunsafefnload_async("));
+        assert!(expanded.contains("pubunsafefnload_async_named("));
+    }
+}
+
+#[test]
+fn uncontracted_module_preserves_safe_custom_loaders() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn map(mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(expanded.contains("pubfnload_named("));
+    assert!(expanded.contains("pubfnfrom_module("));
+    assert!(!expanded.contains("pubunsafefnload_named("));
+    assert!(!expanded.contains("pubunsafefnfrom_module("));
+    #[cfg(feature = "async")]
+    assert!(expanded.contains("pubfnload_async_named("));
+}
+
+#[test]
+fn generic_contract_brand_and_prepare_witness_keep_specialization_type() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_bounds(128)]
+            #[launch_contract(domain = 1, dynamic_shared = 0)]
+            pub fn apply<F: Fn(u32) -> u32 + Copy>(op: F, out: *mut u32) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(expanded.contains("KernelLaunchContractfor__apply_CudaKernel<F>"));
+    assert!(expanded.contains("PreparedLaunch<__apply_CudaKernel<F>>"));
+    assert!(expanded.contains("fnprepare_apply_for<F"));
+    assert!(expanded.contains("__cuda_oxide_type_witness_0:&F"));
+    assert!(
+        expanded.contains("let__cuda_oxide_max_threads:u32=128"),
+        "{expanded}"
+    );
+    assert!(expanded.contains("BlockRequirement::MaxThreads(__cuda_oxide_max_threads)"));
+}
+
+/// The `requires` demo module used by the size-requirement tests: two
+/// relations, one with arithmetic, over a scalar pair and two buffers.
+fn requires_demo_module() -> ItemMod {
+    parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_contract(
+                domain = 1,
+                block = (128, 1, 1),
+                requires = (input.len() >= n * stride, output.len() >= n),
+            )]
+            pub fn scaled_copy(
+                n: u32,
+                stride: u32,
+                input: &[f32],
+                mut output: DisjointSlice<f32>,
+            ) {
+            }
+        }
+    }
+}
+
+#[test]
+fn requires_relations_generate_overflow_safe_checks_in_checked_launchers_only() {
+    let expanded = expand_to_compact_string(requires_demo_module());
+
+    // Every operand is widened to u64 and arithmetic goes through
+    // checked ops with a typed overflow error.
+    assert!(expanded.contains("SizeRequirementViolated"), "{expanded}");
+    assert!(expanded.contains("SizeRequirementOverflow"), "{expanded}");
+    assert!(expanded.contains("checked_mul"), "{expanded}");
+    assert!(expanded.contains("(nasu64)"), "{expanded}");
+    // The relation's source text rides along for the error message.
+    // (`expand_to_compact_string` strips spaces inside string literals
+    // too, so the expected text is compacted.)
+    assert!(expanded.contains("\"input.len()>=n*stride\""), "{expanded}");
+    assert!(expanded.contains("\"output.len()>=n\""), "{expanded}");
+
+    // Each checked launcher evaluates both relations; the `_unchecked`
+    // escape hatches never do. Without the async feature only the sync
+    // prepared launcher exists (2 relations); with it, the `_async` and
+    // `_async_owned` twins check too (2 relations each).
+    #[cfg(not(feature = "async"))]
+    assert_eq!(
+        expanded.matches("SizeRequirementViolated").count(),
+        2,
+        "{expanded}"
+    );
+    #[cfg(feature = "async")]
+    assert_eq!(
+        expanded.matches("SizeRequirementViolated").count(),
+        6,
+        "{expanded}"
+    );
+}
+
+#[cfg(feature = "async")]
+#[test]
+fn requires_relations_wrap_async_launchers_in_result() {
+    let expanded = expand_to_compact_string(requires_demo_module());
+
+    // The async launchers report a violated relation as a typed error
+    // instead of enqueueing, so their return types gain a Result.
+    assert!(
+        expanded.contains("::core::result::Result<::cuda_host::PreparedAsyncKernelLaunch<"),
+        "{expanded}"
+    );
+    assert!(
+        expanded.contains("::core::result::Result<::cuda_host::PreparedOwnedAsyncKernelLaunch<"),
+        "{expanded}"
+    );
+    // Slice lengths come from the KernelSliceArg trait: by reference for
+    // the borrowed async launcher, by value for the owned one.
+    assert!(
+        expanded.contains("KernelSliceArg::len(input)"),
+        "{expanded}"
+    );
+    assert!(
+        expanded.contains("KernelSliceArg::len(&input)"),
+        "{expanded}"
+    );
+
+    // A contract without `requires` keeps the plain infallible async
+    // signatures.
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_contract(domain = 1, block = (128, 1, 1))]
+            pub fn plain(input: &[f32], mut output: DisjointSlice<f32>) {}
+        }
+    };
+    let plain = expand_to_compact_string(module);
+    assert!(
+        !plain.contains("Result<::cuda_host::PreparedAsyncKernelLaunch<"),
+        "{plain}"
+    );
+    assert!(
+        !plain.contains("Result<::cuda_host::PreparedOwnedAsyncKernelLaunch<"),
+        "{plain}"
+    );
+}
+
+#[test]
+fn requires_rejects_relations_outside_the_v1_grammar() {
+    let expand_with_requires = |requires: &str| {
+        let attr = format!("domain = 1, block = (64, 1, 1), requires = ({requires})");
+        let attr: TokenStream2 = attr.parse().expect("attr tokens");
+        let module: ItemMod = parse_quote! {
+            mod kernels {
+                #[kernel]
+                #[launch_contract(#attr)]
+                pub fn bad(n: u32, input: &[f32], mut output: DisjointSlice<f32>) {}
+            }
+        };
+        expand_cuda_module(module)
+    };
+    let reject = |requires: &str, expected: &str| {
+        let error = expand_with_requires(requires)
+            .expect_err(&format!("`{requires}` should be rejected"))
+            .to_string();
+        assert!(
+            error.contains(expected),
+            "`{requires}` produced unexpected error: {error}"
+        );
+    };
+
+    reject("input.len() >= 1.5", "only integer literals");
+    reject("input.len() >= 1 && output.len() >= 1", "must compare with");
+    reject("input.len() + n", "must compare with");
+    reject("input", "must be a comparison");
+    reject("input.len() as u64 >= 1", "unsupported expression");
+    reject("input.capacity() >= n", "only the `.len()` method");
+    reject(
+        "input.len() >= (n >= 1)",
+        "nested comparisons are not supported",
+    );
+    reject("input.len() >= self::n", "bare kernel parameter names");
+
+    // The full accepted grammar expands cleanly.
+    expand_with_requires("(input.len() - 1) * 2 + 0 >= n * 3")
+        .expect("grammar-conformant relation must expand");
+}
+
+#[test]
+fn requires_parser_accepts_relation_lists_and_rejects_degenerate_forms() {
+    let args: LaunchContractArgs =
+        syn::parse_str("domain = 1, requires = (a.len() >= n, b.len() >= n * 2)").unwrap();
+    assert_eq!(args.requires.len(), 2);
+
+    // `.err()` instead of `.unwrap_err()`: LaunchContractArgs holds
+    // syn::Expr, which has no Debug without syn's extra-traits feature.
+    let empty = syn::parse_str::<LaunchContractArgs>("domain = 1, requires = ()")
+        .err()
+        .expect("empty requires list must be rejected");
+    assert!(empty.to_string().contains("at least one relation"));
+
+    let duplicate = syn::parse_str::<LaunchContractArgs>(
+        "domain = 1, requires = (a.len() >= 1), requires = (b.len() >= 1)",
+    )
+    .err()
+    .expect("duplicate requires key must be rejected");
+    assert!(
+        duplicate
+            .to_string()
+            .contains("duplicate launch_contract field")
+    );
+}
+
+#[test]
+fn cfg_gated_duplicate_kernel_names_are_rejected_until_ptx_names_are_qualified() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[cfg(feature = "fast")]
+            pub fn step(mut out: DisjointSlice<f32>) {}
+
+            #[kernel]
+            #[cfg(not(feature = "fast"))]
+            pub fn step(mut out: DisjointSlice<f32>) {}
+        }
+    };
+    let error = expand_cuda_module(module).expect_err("bare PTX names still collide");
+    assert!(
+        error
+            .to_string()
+            .contains("PTX entry names are currently bare"),
+        "unexpected error message: {error}"
+    );
+}
+
+#[test]
+fn contract_without_block_or_launch_bounds_is_rejected() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_contract(domain = 1, dynamic_shared = 0)]
+            pub fn missing_block(input: &[u32]) {}
+        }
+    };
+    let error = expand_cuda_module(module).expect_err("contract should fail closed");
+    assert!(
+        error
+            .to_string()
+            .contains("requires either an exact `block = (x, y, z)` or #[launch_bounds")
+    );
+}
+
+#[test]
+fn file_backed_modules_and_include_macros_are_preserved_without_being_walked() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn top() {}
+
+            mod helper;
+            include!("helper_items.rs");
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+    assert!(
+        expanded.contains("modhelper;"),
+        "file module was changed: {expanded}"
+    );
+    assert!(
+        expanded.contains("include!(\"helper_items.rs\");"),
+        "include invocation was changed: {expanded}"
+    );
+}
+
+#[test]
+fn loaded_module_is_reserved_in_nested_kernel_namespaces() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn top() {}
+
+            mod child {
+                struct LoadedModule;
+
+                #[kernel]
+                pub fn nested() {}
+            }
+        }
+    };
+    let error = expand_cuda_module(module).expect_err("reserved type name must fail clearly");
+    assert!(
+        error
+            .to_string()
+            .contains("reserves the name `LoadedModule`"),
+        "unexpected error message: {error}"
+    );
+}
+
+#[test]
+fn raw_and_plain_kernel_spellings_share_one_conflict_key() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            mod plain {
+                #[kernel]
+                fn step() {}
+            }
+
+            mod raw {
+                #[kernel]
+                fn r#step() {}
+            }
+        }
+    };
+    let error = expand_cuda_module(module).expect_err("raw prefix must not evade PTX guard");
+    let message = error.to_string();
+    assert!(
+        message.contains("`step`") && message.contains("plain") && message.contains("raw"),
+        "unexpected error message: {message}"
+    );
+}
+
+#[test]
+fn raw_loaded_module_spelling_is_reserved() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            mod child {
+                struct r#LoadedModule;
+
+                #[kernel]
+                fn nested() {}
+            }
+        }
+    };
+    let error = expand_cuda_module(module).expect_err("raw prefix must not evade reservation");
+    assert!(
+        error
+            .to_string()
+            .contains("reserves the name `LoadedModule`"),
+        "unexpected error message: {error}"
+    );
+}
+
+#[test]
+fn renamed_extern_crate_cannot_claim_loaded_module() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            extern crate core as r#LoadedModule;
+
+            #[kernel]
+            fn root() {}
+        }
+    };
+    let error = expand_cuda_module(module).expect_err("extern-crate rename must be checked");
+    assert!(
+        error
+            .to_string()
+            .contains("reserves the name `LoadedModule`"),
+        "unexpected error message: {error}"
+    );
+}
+
+#[test]
+fn generated_loaded_module_method_names_are_reserved() {
+    let root: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            fn as_cuda_module() {}
+        }
+    };
+    let error = expand_cuda_module(root).expect_err("root accessor name must be reserved");
+    assert!(
+        error.to_string().contains("method name `as_cuda_module`"),
+        "unexpected error message: {error}"
+    );
+
+    let nested: ItemMod = parse_quote! {
+        mod kernels {
+            mod child {
+                #[kernel]
+                fn from_parent() {}
+            }
+        }
+    };
+    let error = expand_cuda_module(nested).expect_err("nested constructor name must be reserved");
+    assert!(
+        error.to_string().contains("method name `from_parent`"),
+        "unexpected error message: {error}"
+    );
+}
+
+#[test]
+fn contracted_mut_slice_is_rejected_in_favor_of_disjoint_slice() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_contract(domain = 1, block = (64, 1, 1))]
+            pub fn aliased(out: &mut [u32]) {}
+        }
+    };
+    let error = expand_cuda_module(module).expect_err("mutable slice must fail closed");
+    assert!(
+        error
+            .to_string()
+            .contains("contracted kernels cannot take `&mut [T]`")
+    );
+}
+
+#[test]
+fn disjoint_slice_packet_shape_is_bound_to_the_resolved_type() {
+    // The spelling `Rt` hides a runtime row width, so the macro selects
+    // the two-word host ABI. The generated launch methods must carry the
+    // semantic `HAS_ROW_WIDTH = false` bound for Rust to reject at the call
+    // site once `Rt` resolves to a runtime-width index space.
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            type Rt = RuntimeRowMajorTiles<1, 1>;
+
+            #[kernel]
+            pub fn alias_hides_row_width(mut out: DisjointSlice<f32, Rt>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+    assert!(
+        expanded.contains(
+            "for<'__cuda_oxide_disjoint>DisjointSlice<'__cuda_oxide_disjoint,f32,Rt>:\
+                 ::cuda_device::__LaunchContractDisjointSliceAbi<f32,false>"
+        ),
+        "flat spelling must bind HAS_ROW_WIDTH = false: {expanded}"
+    );
+
+    // The direct spelling selects the three-word ABI and must bind
+    // `HAS_ROW_WIDTH = true`.
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn really_has_row_width(mut out: DisjointSlice<f32, Runtime2DIndex>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+    assert!(
+        expanded.contains(
+            "for<'__cuda_oxide_disjoint>DisjointSlice<'__cuda_oxide_disjoint,f32,\
+                 Runtime2DIndex>:::cuda_device::__LaunchContractDisjointSliceAbi<f32,true>"
+        ),
+        "runtime-width spelling must bind HAS_ROW_WIDTH = true: {expanded}"
+    );
+}
+
+#[test]
+fn aliased_disjoint_index_space_is_checked_by_rust_type_resolution() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            type Alias = Index2D<128>;
+
+            #[kernel]
+            #[launch_contract(domain = 2, block = (16, 16, 1))]
+            pub fn aliased(mut out: DisjointSlice<u32, Alias>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(
+        expanded.contains(
+            "for<'__cuda_oxide_disjoint>DisjointSlice<'__cuda_oxide_disjoint,u32,Alias>:"
+        ),
+        "the bound must preserve the original index-space alias: {expanded}"
+    );
+    assert!(expanded.contains("__LaunchContractDisjointSlice<u32,2u8>"));
+}
+
+#[test]
+fn one_dimensional_index_space_is_not_accepted_by_identifier_spelling() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            type Index2D = Index1D;
+
+            #[kernel]
+            #[launch_contract(domain = 2, block = (16, 16, 1))]
+            pub fn wrong_rank(mut out: DisjointSlice<u32, Index2D>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(
+        expanded.contains(
+            "for<'__cuda_oxide_disjoint>DisjointSlice<'__cuda_oxide_disjoint,u32,Index2D>:"
+        ),
+        "the bound must preserve the misleading alias for Rust to resolve: {expanded}"
+    );
+    assert!(expanded.contains("__LaunchContractDisjointSlice<u32,2u8>"));
+}
+
+#[test]
+fn local_disjoint_slice_lookalike_gets_the_genuine_type_bound() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            struct DisjointSlice<'a, T, IndexSpace = Index1D> {
+                value: &'a mut T,
+                index: PhantomData<IndexSpace>,
+            }
+
+            #[kernel]
+            #[launch_contract(domain = 1, block = (64, 1, 1))]
+            pub fn fake(mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(
+        expanded.contains("for<'__cuda_oxide_disjoint>DisjointSlice<'__cuda_oxide_disjoint,u32>:"),
+        "the look-alike must receive the genuine cuda-device trait bound: {expanded}"
+    );
+    assert!(expanded.contains("__LaunchContractDisjointSlice<u32,1u8>"));
+}
+
+#[test]
+fn launch_bounds_accepts_a_two_dimensional_block_with_the_same_product() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_bounds(256)]
+            #[launch_contract(domain = 2, block = (16, 16, 1))]
+            pub fn tiled(input: &[u32]) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+    assert!(expanded.contains("BlockRequirement::Exact((16u32,16u32,1u32))"));
+}
+
+#[test]
+fn exact_block_cannot_exceed_compiled_launch_bounds_thread_count() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_bounds(256)]
+            #[launch_contract(domain = 2, block = (17, 16, 1))]
+            pub fn impossible(input: &[u32]) {}
+        }
+    };
+    let error = expand_cuda_module(module).expect_err("bounds mismatch must fail closed");
+    assert!(error.to_string().contains("272 threads"));
+    assert!(error.to_string().contains("launch_bounds(256)"));
+}
+
+#[cfg(feature = "async")]
+#[test]
+fn contracted_async_methods_return_immutable_wrappers() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_contract(domain = 1, block = (64, 1, 1))]
+            pub fn map(input: &[u32], mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(expanded.contains("PreparedAsyncKernelLaunch<'__cuda_oxide_async,__map_CudaKernel>"));
+    assert!(expanded.contains("PreparedOwnedAsyncKernelLaunch<"));
+    assert!(expanded.contains("fnmap_async_unchecked"));
+    assert!(expanded.contains("fnmap_async_owned_unchecked"));
+    assert!(expanded.matches("unsafe").count() >= 4);
+}
+
+#[cfg(feature = "async")]
+#[test]
+fn uncontracted_async_launch_methods_are_always_unsafe() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            pub fn map(input: &[u32], mut out: DisjointSlice<u32>) {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(expanded.contains("pubunsafefnmap_async"));
+    assert!(expanded.contains("pubunsafefnmap_async_owned"));
+    assert_eq!(
+        expanded.matches("new_async_kernel_launch_builder").count(),
+        2
+    );
+    assert_eq!(expanded.matches("finalize_unchecked").count(), 2);
+}
+
+#[test]
+fn cuda_module_host_methods_keep_policy_expression_bounds() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_bounds(P::MAX_THREADS, P::MIN_BLOCKS)]
+            pub fn configured<P: Policy>() {
+                let mut i = 0u32;
+                #[unroll(P::UNROLL)]
+                while i < 8 { i += 1; }
+            }
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(expanded.contains("[();(P::MAX_THREADS)asusize]:"));
+    assert!(expanded.contains("[();(P::MIN_BLOCKS)asusize]:"));
+    assert!(expanded.contains("[();(P::UNROLL)asusize]:"));
+    assert!(expanded.contains("pubfnconfigured<P:Policy>"));
+}
+
+#[test]
+fn nested_cuda_module_host_methods_keep_policy_expression_bounds() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            pub mod stage {
+                use super::*;
+
+                #[kernel]
+                #[launch_bounds(P::MAX_THREADS, P::MIN_BLOCKS)]
+                pub fn configured<P: Policy>() {
+                    let mut i = 0u32;
+                    #[unroll(P::UNROLL)]
+                    while i < 8 { i += 1; }
+                }
+            }
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(expanded.contains("pubmodstage"));
+    assert!(expanded.contains("from_parent(parent:&super::LoadedModule"));
+    assert!(expanded.contains("[();(P::MAX_THREADS)asusize]:"));
+    assert!(expanded.contains("[();(P::MIN_BLOCKS)asusize]:"));
+    assert!(expanded.contains("[();(P::UNROLL)asusize]:"));
+    assert!(expanded.contains("pubfnconfigured<P:Policy>"));
+}
+
+#[test]
+fn launch_contract_carries_deferred_launch_bounds_into_host_spec() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_bounds(P::MAX_THREADS)]
+            #[launch_contract(domain = 1)]
+            pub fn configured<P: Policy>() {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(
+        expanded.contains("let__cuda_oxide_max_threads:u32=P::MAX_THREADS"),
+        "policy maximum must be part of the host contract: {expanded}"
+    );
+    assert!(
+        expanded.contains("__cuda_oxide_max_threads>0"),
+        "{expanded}"
+    );
+    assert!(expanded.contains("BlockRequirement::MaxThreads(__cuda_oxide_max_threads)"));
+    assert!(expanded.contains("[();(P::MAX_THREADS)asusize]:"));
+}
+
+#[test]
+fn exact_block_checks_a_deferred_launch_bound_per_specialization() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_bounds(P::MAX_THREADS)]
+            #[launch_contract(domain = 1, block = (64, 1, 1))]
+            pub fn configured<P: Policy>() {}
+        }
+    };
+    let expanded = expand_to_compact_string(module);
+
+    assert!(
+        expanded.contains("BlockRequirement::Exact((64u32,1u32,1u32))"),
+        "an explicit block must remain exact: {expanded}"
+    );
+    assert!(
+        expanded.contains("64u128<=(__cuda_oxide_max_threads)asu128"),
+        "the policy bound must be checked for each specialization: {expanded}"
+    );
+}
+
+#[test]
+fn launch_contract_allows_deferred_minimum_blocks() {
+    let module: ItemMod = parse_quote! {
+        mod kernels {
+            #[kernel]
+            #[launch_bounds(256, P::MIN_BLOCKS)]
+            #[launch_contract(domain = 1)]
+            pub fn configured<P: Policy>() {}
+        }
+    };
+
+    expand_cuda_module(module)
+        .expect("minimum blocks affects device occupancy metadata, not the host launch contract");
+}
diff --git a/crates/cuda-macros/src/tests/kernel.rs b/crates/cuda-macros/src/tests/kernel.rs
new file mode 100644
index 0000000000..c6a420b08f
--- /dev/null
+++ b/crates/cuda-macros/src/tests/kernel.rs
@@ -0,0 +1,652 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::common::attr_path_ends_with;
+use crate::kernel::KernelArgs;
+use crate::kernel::codegen::{
+    generate_cuda_kernel_impl, generic_kernel_instantiation_tokens,
+    generic_kernel_no_instantiation_tokens, route_generic_kernel_attrs,
+};
+use crate::kernel::scope::{
+    explicit_kernel_scope, explicit_kernel_scope_bindings, forwarding_inputs,
+    inject_thread_index_scope, is_kernel_configuration_marker, is_unchecked_indexing_config_marker,
+    top_level_kernel_configuration_markers,
+};
+use proc_macro2::TokenStream as TokenStream2;
+use quote::{format_ident, quote};
+use reserved_oxide_symbols::{KERNEL_PREFIX, KERNEL_SCOPE_LOCAL};
+use syn::{Expr, ItemFn, Stmt, parse_quote, spanned::Spanned};
+
+/// A bare `#[kernel]` outside any `#[cuda_module]` carries its own
+/// `CudaKernel` impl, the other reference a kernel-only crate cannot
+/// resolve.
+#[test]
+fn bare_kernel_marker_impl_is_host_only() {
+    let func: ItemFn = parse_quote! {
+        fn scale(out: *mut f32) {}
+    };
+    let name = format_ident!("scale");
+
+    let device_only = generate_cuda_kernel_impl(&name, "scale", &func, false).to_string();
+    assert!(
+        device_only.is_empty(),
+        "device-only build must emit no marker impl: {device_only}"
+    );
+
+    let host = generate_cuda_kernel_impl(&name, "scale", &func, true).to_string();
+    assert!(
+        host.contains("CudaKernel"),
+        "host build must keep the marker impl: {host}"
+    );
+}
+
+#[test]
+fn forwarding_inputs_name_every_irrefutable_parameter_pattern() {
+    let function: ItemFn = parse_quote! {
+        fn patterns(_: u32, (left, right): (u16, u16), mut value: u8) {}
+    };
+    let (inputs, names) = forwarding_inputs(&function.sig.inputs).unwrap();
+    let forwarded = quote! {
+        fn wrapper(#(#inputs),*) {
+            target(#(#names),*)
+        }
+    }
+    .to_string()
+    .replace(' ', "");
+
+    assert!(forwarded.contains("__cuda_oxide_arg_0:u32"));
+    assert!(forwarded.contains("__cuda_oxide_arg_1:(u16,u16)"));
+    assert!(forwarded.contains("__cuda_oxide_arg_2:u8"));
+    assert!(forwarded.contains("target(__cuda_oxide_arg_0,__cuda_oxide_arg_1,__cuda_oxide_arg_2)"));
+}
+
+#[test]
+fn generic_kernel_routes_entry_directives_without_losing_cfg() {
+    let function: ItemFn = parse_quote! {
+        #[doc = "configured kernel"]
+        #[cfg(feature = "configured")]
+        #[launch_bounds(256, 2)]
+        #[cluster_launch(2, 1, 1)]
+        fn configured<const N: usize>() {}
+    };
+
+    let (implementation, entry, cfg) = route_generic_kernel_attrs(&function.attrs);
+
+    assert!(
+        implementation
+            .iter()
+            .any(|attr| attr_path_ends_with(attr, "doc"))
+    );
+    assert!(
+        implementation
+            .iter()
+            .any(|attr| attr_path_ends_with(attr, "cfg"))
+    );
+    assert!(
+        !implementation
+            .iter()
+            .any(|attr| attr_path_ends_with(attr, "launch_bounds"))
+    );
+    assert!(
+        !implementation
+            .iter()
+            .any(|attr| attr_path_ends_with(attr, "cluster_launch"))
+    );
+
+    assert!(entry.iter().any(|attr| attr_path_ends_with(attr, "cfg")));
+    assert!(
+        entry
+            .iter()
+            .any(|attr| attr_path_ends_with(attr, "launch_bounds"))
+    );
+    assert!(
+        entry
+            .iter()
+            .any(|attr| attr_path_ends_with(attr, "cluster_launch"))
+    );
+    assert!(!entry.iter().any(|attr| attr_path_ends_with(attr, "doc")));
+
+    assert_eq!(cfg.len(), 1);
+    assert!(attr_path_ends_with(&cfg[0], "cfg"));
+}
+
+#[test]
+fn kernel_launch_context_uses_the_contract_domain_and_coordinate_width_in_either_order() {
+    let mut attributed: ItemFn = parse_quote! {
+        #[launch_contract(domain = 1, coordinates = u32, block = (64, 1, 1))]
+        fn attributed() {
+            let _ = thread::index_1d_u32(launch_context);
+        }
+    };
+    let scope = explicit_kernel_scope(&mut attributed, format_ident!("launch_context"));
+    attributed
+        .block
+        .stmts
+        .splice(0..0, explicit_kernel_scope_bindings(&scope));
+    let attributed = quote!(#attributed).to_string().replace(' ', "");
+    assert!(attributed.contains("make_kernel_scope::<::cuda_device::thread::__internal::Domain1,::cuda_device::thread::__internal::U32Coordinates>"));
+    assert!(attributed.contains("letlaunch_context:::cuda_device::thread::LaunchContextRef"));
+
+    let mut expanded_first: ItemFn = parse_quote! {
+        fn expanded_first() {
+            unsafe {
+                ::cuda_device::thread::__launch_contract_config::<1, true>();
+            }
+            let _ = thread::index_1d_u32(launch_context);
+        }
+    };
+    let scope = explicit_kernel_scope(&mut expanded_first, format_ident!("launch_context"));
+    expanded_first
+        .block
+        .stmts
+        .splice(0..0, explicit_kernel_scope_bindings(&scope));
+    let expanded_first = quote!(#expanded_first).to_string().replace(' ', "");
+    assert!(expanded_first.contains("make_kernel_scope::<::cuda_device::thread::__internal::Domain1,::cuda_device::thread::__internal::U32Coordinates>"));
+
+    let mut two_dimensional: ItemFn = parse_quote! {
+        #[launch_contract(domain = 2, coordinates = u32, block = (8, 8, 1))]
+        fn two_dimensional() {
+            let _ = thread::coord_2d_u32(launch_context);
+        }
+    };
+    let scope = explicit_kernel_scope(&mut two_dimensional, format_ident!("launch_context"));
+    two_dimensional
+        .block
+        .stmts
+        .splice(0..0, explicit_kernel_scope_bindings(&scope));
+    let two_dimensional = quote!(#two_dimensional).to_string().replace(' ', "");
+    assert!(two_dimensional.contains("make_kernel_scope::<::cuda_device::thread::__internal::Domain2,::cuda_device::thread::__internal::U32Coordinates>"));
+}
+
+#[test]
+fn thread_index_rewrite_preserves_the_user_call_span_with_multiple_attributes() {
+    let mut input: ItemFn = syn::parse_str(
+        r#"
+/// The documentation and neighboring attributes must not become line-table
+/// locations for the first executable indexing expression.
+#[allow(dead_code)]
+#[launch_bounds(256, 2)]
+fn documented_kernel() {
+    let idx = thread::index_1d();
+    consume(idx);
+}
+"#,
+    )
+    .unwrap();
+    let source_attr_count = input.attrs.len();
+
+    let Stmt::Local(original_local) = &input.block.stmts[0] else {
+        panic!("fixture starts with a local")
+    };
+    let original_call = original_local
+        .init
+        .as_ref()
+        .map(|init| &*init.expr)
+        .and_then(|expr| match expr {
+            Expr::Call(call) => Some(call),
+            _ => None,
+        })
+        .expect("fixture local is initialized by a call");
+    let user_call_start = original_call.span().start();
+    assert!(
+        user_call_start.line > 5,
+        "fixture must distinguish attributes"
+    );
+
+    inject_thread_index_scope(&mut input);
+
+    assert_eq!(
+        input.attrs.len(),
+        source_attr_count,
+        "all source attributes stay on the item"
+    );
+    let Stmt::Local(rewritten_local) = &input.block.stmts[1] else {
+        panic!("the user local follows the generated scope binding")
+    };
+    let rewritten_call = rewritten_local
+        .init
+        .as_ref()
+        .map(|init| &*init.expr)
+        .and_then(|expr| match expr {
+            Expr::Call(call) => Some(call),
+            _ => None,
+        })
+        .expect("rewritten local remains a call expression");
+
+    assert_eq!(
+        rewritten_call.span().start(),
+        user_call_start,
+        "rewriting must not relocate the user expression onto an attribute"
+    );
+    let Expr::Path(path) = &*rewritten_call.func else {
+        panic!("rewritten callee remains a path")
+    };
+    assert!(
+        path.path
+            .segments
+            .iter()
+            .any(|segment| segment.ident == "__internal")
+    );
+    assert_eq!(
+        rewritten_call.args[0].span().start(),
+        user_call_start,
+        "the injected scope reference belongs to the user's call site"
+    );
+}
+
+#[test]
+fn kernel_launch_context_argument_composes_with_legacy_instantiations() {
+    let args: KernelArgs = syn::parse_str("f32, launch_context = launch_context, f64").unwrap();
+    assert_eq!(args.instantiate_types.len(), 2);
+    assert_eq!(args.launch_context.unwrap(), "launch_context");
+
+    let duplicate = syn::parse_str::<KernelArgs>("launch_context = first, launch_context = second")
+        .err()
+        .unwrap();
+    assert!(duplicate.to_string().contains("duplicate `launch_context`"));
+
+    let unknown = syn::parse_str::<KernelArgs>("context = launch_context")
+        .err()
+        .unwrap();
+    assert!(
+        unknown
+            .to_string()
+            .contains("unknown #[kernel] named argument")
+    );
+}
+
+#[test]
+fn kernel_unchecked_indexing_flag_parses_and_composes() {
+    let bare: KernelArgs = syn::parse_str("unchecked_indexing").unwrap();
+    assert!(bare.unchecked_indexing);
+    assert!(bare.instantiate_types.is_empty());
+    assert!(bare.launch_context.is_none());
+
+    let composed: KernelArgs =
+        syn::parse_str("f32, launch_context = launch_context, unchecked_indexing").unwrap();
+    assert!(composed.unchecked_indexing);
+    assert_eq!(composed.instantiate_types.len(), 1);
+    assert_eq!(composed.launch_context.unwrap(), "launch_context");
+
+    let leading: KernelArgs = syn::parse_str("unchecked_indexing, f32").unwrap();
+    assert!(leading.unchecked_indexing);
+    assert_eq!(leading.instantiate_types.len(), 1);
+
+    let default: KernelArgs = syn::parse_str("f32, launch_context = launch_context").unwrap();
+    assert!(!default.unchecked_indexing);
+
+    let duplicate = syn::parse_str::<KernelArgs>("unchecked_indexing, unchecked_indexing")
+        .err()
+        .unwrap();
+    assert!(
+        duplicate
+            .to_string()
+            .contains("duplicate `unchecked_indexing`")
+    );
+
+    // The flag is a bare word, never a named argument.
+    let named = syn::parse_str::<KernelArgs>("unchecked_indexing = true")
+        .err()
+        .unwrap();
+    assert!(
+        named
+            .to_string()
+            .contains("unknown #[kernel] named argument")
+    );
+}
+
+#[test]
+fn unchecked_indexing_marker_is_a_forwardable_configuration_marker() {
+    // The exact statement the `#[kernel]` macro injects must be recognized
+    // by the generic-entry marker forwarding, so the flag reaches the
+    // generated entry wrapper even when the implementation helper is
+    // translated separately.
+    let marker: Stmt = parse_quote! {
+        ::cuda_device::thread::__unchecked_indexing_config::<true>();
+    };
+    assert!(is_kernel_configuration_marker(&marker));
+    assert!(is_unchecked_indexing_config_marker(&marker));
+
+    let kernel: ItemFn = parse_quote! {
+        fn body() {
+            ::cuda_device::thread::__unchecked_indexing_config::<true>();
+            work();
+        }
+    };
+    let markers = top_level_kernel_configuration_markers(&kernel);
+    assert_eq!(markers.len(), 1);
+}
+
+/// Renders the function item named `name` from an expansion, panicking
+/// with the full expansion when it is missing.
+fn expansion_fn_source(expanded: &TokenStream2, name: &str) -> String {
+    let file: syn::File =
+        syn::parse2(expanded.clone()).expect("generated tokens must parse as items");
+    let function = file
+        .items
+        .iter()
+        .find_map(|item| match item {
+            syn::Item::Fn(item_fn) if item_fn.sig.ident == name => Some(item_fn),
+            _ => None,
+        })
+        .unwrap_or_else(|| panic!("expansion has no fn `{name}`:\n{expanded}"));
+    quote!(#function).to_string().replace(' ', "")
+}
+
+/// The kernel body exactly as `kernel()` hands it to the generic
+/// expansion paths: the unchecked-indexing marker is already statement 0.
+fn opted_generic_kernel() -> ItemFn {
+    parse_quote! {
+        pub fn scaled_gather<T: Copy>(a: &[T], mut c: DisjointSlice<T>) {
+            ::cuda_device::thread::__unchecked_indexing_config::<true>();
+            work(a, &mut c);
+        }
+    }
+}
+
+#[test]
+fn generic_expansion_confines_unchecked_marker_to_entry_and_hidden_twin() {
+    let expanded = generic_kernel_no_instantiation_tokens(opted_generic_kernel(), None);
+
+    // The user-named implementation helper is ordinary callable Rust and
+    // must NOT carry the marker: rustc may inline it into other kernels
+    // that never opted in.
+    let helper = expansion_fn_source(&expanded, "scaled_gather");
+    assert!(
+        !helper.contains("__unchecked_indexing_config"),
+        "helper leaked the marker:\n{helper}"
+    );
+
+    // The generated entry wrapper keeps the forwarded marker and calls
+    // the hidden unchecked twin instead of the user-named helper.
+    let entry = expansion_fn_source(&expanded, &format!("{KERNEL_PREFIX}scaled_gather"));
+    assert!(
+        entry.contains("__unchecked_indexing_config"),
+        "entry wrapper lost the marker:\n{entry}"
+    );
+    assert!(
+        entry.contains("__cuda_oxide_unchecked_impl_scaled_gather::<T>"),
+        "entry wrapper does not call the unchecked twin:\n{entry}"
+    );
+
+    let twin = expansion_fn_source(&expanded, "__cuda_oxide_unchecked_impl_scaled_gather");
+    assert!(twin.contains("__unchecked_indexing_config"));
+}
+
+#[test]
+fn legacy_instantiation_confines_unchecked_marker_to_entry_and_hidden_twin() {
+    // Legacy `#[kernel(Type, ...)]` instantiation supports by-value
+    // parameters of the single type parameter (see
+    // `kernel_launch_context_api.rs`'s `explicit` kernel).
+    let kernel: ItemFn = parse_quote! {
+        pub fn scaled_gather<T: Copy>(value: T) {
+            ::cuda_device::thread::__unchecked_indexing_config::<true>();
+            work(value);
+        }
+    };
+    let expanded = generic_kernel_instantiation_tokens(kernel, vec![parse_quote! { f32 }], None);
+
+    let helper = expansion_fn_source(&expanded, "scaled_gather");
+    assert!(
+        !helper.contains("__unchecked_indexing_config"),
+        "helper leaked the marker:\n{helper}"
+    );
+
+    let entry = expansion_fn_source(&expanded, &format!("{KERNEL_PREFIX}scaled_gather_f32"));
+    assert!(
+        entry.contains("__unchecked_indexing_config"),
+        "entry wrapper lost the marker:\n{entry}"
+    );
+    assert!(
+        entry.contains("__cuda_oxide_unchecked_impl_scaled_gather::<f32>"),
+        "entry wrapper does not call the unchecked twin:\n{entry}"
+    );
+
+    let twin = expansion_fn_source(&expanded, "__cuda_oxide_unchecked_impl_scaled_gather");
+    assert!(twin.contains("__unchecked_indexing_config"));
+}
+
+#[test]
+fn non_opted_generic_expansion_has_no_unchecked_twin_or_marker() {
+    let kernel: ItemFn = parse_quote! {
+        pub fn plain<T: Copy>(a: &[T], mut c: DisjointSlice<T>) {
+            work(a, &mut c);
+        }
+    };
+    let expanded = generic_kernel_no_instantiation_tokens(kernel, None).to_string();
+    assert!(!expanded.contains("__unchecked_indexing_config"));
+    assert!(!expanded.contains("__cuda_oxide_unchecked_impl"));
+    assert!(!expanded.contains("dead_code"));
+}
+
+#[test]
+fn unchecked_twin_carries_helper_lint_attributes() {
+    // A lint the author suppressed on the kernel must not re-fire on the
+    // byte-identical twin body (that would break -Dwarnings builds), and
+    // the user-named helper must be allowed to go dead: the generated
+    // entry calls the twin instead.
+    let kernel: ItemFn = parse_quote! {
+        #[allow(unused_variables)]
+        pub fn scaled_gather<T: Copy>(a: &[T], mut c: DisjointSlice<T>) {
+            ::cuda_device::thread::__unchecked_indexing_config::<true>();
+            work(a, &mut c);
+        }
+    };
+    let expanded = generic_kernel_no_instantiation_tokens(kernel, None);
+
+    let twin = expansion_fn_source(&expanded, "__cuda_oxide_unchecked_impl_scaled_gather");
+    assert!(
+        twin.contains("allow(unused_variables)"),
+        "twin dropped the helper's lint attributes:\n{twin}"
+    );
+
+    let helper = expansion_fn_source(&expanded, "scaled_gather");
+    assert!(helper.contains("allow(unused_variables)"));
+    assert!(
+        helper.contains("allow(dead_code)"),
+        "opted helper is not allowed to go dead:\n{helper}"
+    );
+
+    // The entry wrapper is the live path; it must not be dead-code
+    // suppressed.
+    let entry = expansion_fn_source(&expanded, &format!("{KERNEL_PREFIX}scaled_gather"));
+    assert!(!entry.contains("dead_code"));
+}
+
+#[test]
+fn raw_identifier_kernel_names_build_a_valid_unchecked_twin() {
+    // `Display` of `r#gen` keeps the `r#` prefix, which `Ident::new`
+    // rejects; twin naming must strip it like `format_ident!` does.
+    let kernel: ItemFn = parse_quote! {
+        pub fn r#gen<T: Copy>(value: T) {
+            ::cuda_device::thread::__unchecked_indexing_config::<true>();
+            work(value);
+        }
+    };
+
+    let expanded = generic_kernel_no_instantiation_tokens(kernel.clone(), None);
+    let twin = expansion_fn_source(&expanded, "__cuda_oxide_unchecked_impl_gen");
+    assert!(twin.contains("__unchecked_indexing_config"));
+
+    let expanded = generic_kernel_instantiation_tokens(kernel, vec![parse_quote! { f32 }], None);
+    let twin = expansion_fn_source(&expanded, "__cuda_oxide_unchecked_impl_gen");
+    assert!(twin.contains("__unchecked_indexing_config"));
+}
+
+#[test]
+fn generic_kernels_validate_routed_launch_contract_requires_at_source_names() {
+    // A #[launch_contract] written below #[kernel] is routed onto the
+    // generated entry wrapper, whose synthetic parameter names defeat
+    // attribute-site validation; #[kernel] must validate the relations
+    // against the original signature instead.
+    let typo: ItemFn = parse_quote! {
+        #[cuda_device::launch_contract(
+            domain = 1,
+            block = (64, 1, 1),
+            requires = (input.len() >= n),
+        )]
+        pub fn scaled<T: Copy>(input: &[T]) {}
+    };
+    let expanded = generic_kernel_no_instantiation_tokens(typo.clone(), None).to_string();
+    assert!(expanded.contains("compile_error"), "{expanded}");
+    assert!(expanded.contains("unknown identifier `n`"), "{expanded}");
+
+    let expanded =
+        generic_kernel_instantiation_tokens(typo, vec![parse_quote! { f32 }], None).to_string();
+    assert!(expanded.contains("compile_error"), "{expanded}");
+    assert!(expanded.contains("unknown identifier `n`"), "{expanded}");
+
+    let well_formed: ItemFn = parse_quote! {
+        #[cuda_device::launch_contract(
+            domain = 1,
+            block = (64, 1, 1),
+            requires = (input.len() >= n),
+        )]
+        pub fn scaled<T: Copy>(n: u32, input: &[T]) {}
+    };
+    let expanded = generic_kernel_no_instantiation_tokens(well_formed, None).to_string();
+    assert!(!expanded.contains("compile_error"), "{expanded}");
+}
+
+#[test]
+fn path_spelled_unchecked_indexing_still_parses_as_instantiation_type() {
+    // The bare word is reserved for the flag, but a type literally named
+    // `unchecked_indexing` remains reachable through any path spelling.
+    for spelling in [
+        "self::unchecked_indexing",
+        "crate::unchecked_indexing",
+        "types::unchecked_indexing",
+    ] {
+        let args: KernelArgs = syn::parse_str(spelling).unwrap();
+        assert!(!args.unchecked_indexing, "`{spelling}` parsed as the flag");
+        assert_eq!(
+            args.instantiate_types.len(),
+            1,
+            "`{spelling}` did not parse as an instantiation type"
+        );
+    }
+}
+
+#[test]
+fn explicit_fast_functions_are_not_syntax_rewritten() {
+    let mut function: ItemFn = parse_quote! {
+        #[launch_contract(domain = 1, coordinates = u32, block = (64, 1, 1))]
+        fn ordinary_names() {
+            let local = index_1d_u32();
+            let proof = alias(launch_context);
+            consume(local, proof);
+        }
+    };
+    let scope = explicit_kernel_scope(&mut function, format_ident!("launch_context"));
+    let expanded = quote!(#function).to_string().replace(' ', "");
+
+    assert!(expanded.contains("index_1d_u32()"));
+    assert!(expanded.contains("alias(launch_context)"));
+    assert!(!expanded.contains("__internal::index_1d_u32"));
+    assert_eq!(scope.ident, "launch_context");
+}
+
+#[test]
+fn generic_kernel_routes_launch_contract_to_entry_only() {
+    let kernel: ItemFn = parse_quote! {
+        #[doc = "kept on the helper"]
+        #[cuda_device::launch_bounds(128)]
+        #[cuda_device::launch_contract(
+            domain = 1,
+            dynamic_shared = 256,
+            dynamic_shared_alignment = 64,
+        )]
+        #[cuda_device::cluster_launch(2, 1, 1)]
+        #[cuda_device::cooperative_launch]
+        pub fn map<T: Copy>(value: T) {}
+    };
+
+    let (implementation, entry, _cfg) = route_generic_kernel_attrs(&kernel.attrs);
+    let entry_names: Vec<_> = entry
+        .iter()
+        .map(|attr| attr.path().segments.last().unwrap().ident.to_string())
+        .collect();
+    let implementation_names: Vec<_> = implementation
+        .iter()
+        .map(|attr| attr.path().segments.last().unwrap().ident.to_string())
+        .collect();
+
+    assert_eq!(
+        entry_names,
+        [
+            "launch_bounds",
+            "launch_contract",
+            "cluster_launch",
+            "cooperative_launch",
+        ]
+    );
+    assert_eq!(implementation_names, ["doc"]);
+}
+
+#[test]
+fn generic_kernel_forwards_only_exact_top_level_configuration_markers() {
+    let kernel: ItemFn = parse_quote! {
+        fn map<T>() {
+            ::cuda_device::thread::__launch_bounds_config::<64, 2>();
+            unsafe {
+                ::cuda_device::thread::__launch_contract_config::<1, true>();
+            }
+            ::cuda_device::thread::__launch_contract_block_config::<64, 1, 1>();
+            ::cuda_device::cluster::__cluster_config::<2, 1, 1>();
+            ::cuda_device::shared::__dynamic_shared_alignment::<128>();
+            cuda_device::thread::__launch_bounds_config::<4, 1>();
+            unrelated();
+            other::cuda_device::thread::__launch_bounds_config::<32, 1>();
+            cuda_device::thread::__launch_bounds_config::<16, 1>(7);
+            {
+                cuda_device::thread::__launch_bounds_config::<8, 1>();
+            }
+        }
+    };
+
+    let markers = top_level_kernel_configuration_markers(&kernel);
+    let forwarded = quote!(#(#markers)*).to_string().replace(' ', "");
+
+    assert_eq!(markers.len(), 5);
+    assert!(forwarded.contains("__launch_bounds_config::<64,2>()"));
+    assert!(forwarded.contains("__launch_contract_config::<1,true>()"));
+    assert!(forwarded.contains("__launch_contract_block_config::<64,1,1>()"));
+    assert!(forwarded.contains("__cluster_config::<2,1,1>()"));
+    assert!(forwarded.contains("__dynamic_shared_alignment::<128>()"));
+    assert!(!forwarded.contains("unrelated"));
+    assert!(!forwarded.contains("::<4,1>()"));
+    assert!(!forwarded.contains("other::cuda_device"));
+    assert!(!forwarded.contains("::<16,1>(7)"));
+    assert!(!forwarded.contains("::<8,1>()"));
+}
+
+/// The two hygiene regressions for the injected launch-context scope spell
+/// `KERNEL_SCOPE_LOCAL`-derived names as *identifiers*, so no compiler
+/// check ties them back to the constant. Rename the constant and both
+/// fixtures quietly stop colliding with the generated bindings: they keep
+/// passing while testing nothing, because there is no longer anything to
+/// collide with. Pin the coupling so a rename fails here and names the
+/// fixtures that have to move with it.
+#[test]
+fn hygiene_fixtures_still_collide_with_the_generated_scope_names() {
+    let storage = format!("{KERNEL_SCOPE_LOCAL}_storage");
+
+    let launch_context = include_str!("../../tests/pass/kernel_launch_context_api.rs");
+    assert!(
+        launch_context.contains(&storage),
+        "tests/pass/kernel_launch_context_api.rs must bind `{storage}` so \
+             `generated_storage_name_is_hygienic` exercises the mixed-site \
+             hygiene of the generated storage binding"
+    );
+
+    let const_generic =
+        include_str!("../../../rustc-codegen-cuda/examples/const_generic/src/main.rs");
+    assert!(
+        const_generic.contains(KERNEL_SCOPE_LOCAL),
+        "examples/const_generic must declare a const generic named \
+             `{KERNEL_SCOPE_LOCAL}` so `call_site_ident_avoiding_item` is \
+             forced down its rename path"
+    );
+}
diff --git a/crates/cuda-macros/src/tests/launch.rs b/crates/cuda-macros/src/tests/launch.rs
new file mode 100644
index 0000000000..4fa54eeb4c
--- /dev/null
+++ b/crates/cuda-macros/src/tests/launch.rs
@@ -0,0 +1,420 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::cuda_module::contract::{LaunchContractArgs, validate_requires_relations};
+use crate::launch::{
+    CudaLaunchAsyncInput, CudaLaunchInput, expand_cuda_launch, expand_cuda_launch_async,
+    kernel_sibling_path,
+};
+use crate::launch_attrs::{
+    LaunchBoundsArgs, LoopUnrollAttrVisitor, UnrollArgs, add_const_evaluatable_bound,
+    inject_launch_contract_markers, rewrite_loop_unroll_attrs, standalone_requires_params,
+};
+use quote::{format_ident, quote};
+use reserved_oxide_symbols::INSTANTIATE_PREFIX;
+use syn::{ItemFn, Stmt, parse_quote, visit_mut::VisitMut};
+
+#[test]
+fn generated_kernel_siblings_preserve_qualified_paths_and_generics() {
+    let kernel: syn::Path = parse_quote! { kernels::map::<_, 4> };
+    let instantiate = kernel_sibling_path(&kernel, format_ident!("{}map", INSTANTIATE_PREFIX));
+    let marker = kernel_sibling_path(&kernel, format_ident!("__map_CudaKernel"));
+    let ptx_name = kernel_sibling_path(&kernel, format_ident!("map_ptx_name"));
+
+    let instantiate = quote! { #instantiate }.to_string().replace(' ', "");
+    let marker = quote! { #marker }.to_string().replace(' ', "");
+    let ptx_name = quote! { #ptx_name }.to_string().replace(' ', "");
+    assert_eq!(
+        instantiate,
+        format!("kernels::{}map::<_,4>", INSTANTIATE_PREFIX)
+    );
+    assert_eq!(marker, "kernels::__map_CudaKernel::<_,4>");
+    assert_eq!(ptx_name, "kernels::map_ptx_name::<_,4>");
+}
+
+#[test]
+fn cuda_launch_accepts_combined_cluster_and_cooperative() {
+    let input: CudaLaunchInput = parse_quote! {
+        kernel: clustered_grid_sync_kernel,
+        stream: stream,
+        module: module,
+        config: config,
+        cluster_dim: (2, 1, 1),
+        cooperative: true,
+        args: []
+    };
+    assert!(input.cluster_dim.is_some());
+    assert!(input.cooperative.is_some());
+
+    let expanded = expand_cuda_launch(input).to_string().replace(' ', "");
+    assert!(
+        expanded.contains("launch_kernel_ex_cooperative_on_stream"),
+        "expected combined cluster+cooperative cuda_launch expansion:\n{expanded}"
+    );
+    assert!(
+        !expanded.contains("launch_kernel_cooperative_on_stream"),
+        "non-cluster cooperative helper must not be used when cluster_dim is set:\n{expanded}"
+    );
+}
+
+#[test]
+fn standalone_launch_contract_validates_requires_against_fn_signature() {
+    let kernel: ItemFn = parse_quote! {
+        pub fn scaled(n: u32, input: &[f32], mut output: DisjointSlice<f32>) {}
+    };
+    let params = standalone_requires_params(&kernel).expect("source-named params must model");
+
+    let good: LaunchContractArgs = syn::parse_str(
+        "domain = 1, block = (64, 1, 1), requires = (input.len() >= n, output.len() >= n)",
+    )
+    .unwrap();
+    assert!(validate_requires_relations(&good.requires, &params).is_ok());
+
+    let typo: LaunchContractArgs =
+        syn::parse_str("domain = 1, block = (64, 1, 1), requires = (input.len() >= m)").unwrap();
+    let error = validate_requires_relations(&typo.requires, &params).unwrap_err();
+    assert!(
+        error.to_string().contains("unknown identifier `m`"),
+        "{error}"
+    );
+}
+
+#[test]
+fn standalone_requires_validation_skips_generated_generic_entry_wrappers() {
+    // Generic entry wrappers carry synthetic parameter names; the source
+    // relations were already validated by #[cuda_module] (or are written
+    // against names this wrapper no longer has), so the attribute-site
+    // validation must stand down rather than reject valid contracts.
+    let wrapper: ItemFn = parse_quote! {
+        fn entry<T>(__cuda_oxide_arg_0: &[T], __cuda_oxide_arg_1: u32) {}
+    };
+    assert!(standalone_requires_params(&wrapper).is_none());
+}
+
+#[test]
+fn standalone_requires_models_unmarshallable_params_as_opaque_scalars() {
+    // `&bool` is rejected by the cuda_module marshaller; standalone
+    // validation still names the parameter precisely instead of calling
+    // it an unknown identifier.
+    let kernel: ItemFn = parse_quote! {
+        pub fn odd(flag: &bool, n: u32) {}
+    };
+    let params = standalone_requires_params(&kernel).unwrap();
+    let args: LaunchContractArgs =
+        syn::parse_str("domain = 1, block = (64, 1, 1), requires = (n >= flag)").unwrap();
+    let error = validate_requires_relations(&args.requires, &params).unwrap_err();
+    assert!(
+        error.to_string().contains("not an unsigned integer scalar"),
+        "{error}"
+    );
+}
+
+#[test]
+fn launch_contract_injects_one_alignment_marker_only_when_shared_is_used() {
+    let args: LaunchContractArgs =
+        syn::parse_str("domain = 1, dynamic_shared = 256, dynamic_shared_alignment = 64").unwrap();
+    let mut helper: ItemFn = parse_quote! { fn helper<T>() {} };
+    inject_launch_contract_markers(&args, &mut helper);
+    let expanded = quote!(#helper).to_string();
+    assert_eq!(expanded.matches("__launch_contract_config").count(), 1);
+    assert_eq!(expanded.matches("__dynamic_shared_alignment").count(), 1);
+    assert!(expanded.contains("64usize"));
+
+    let zero_args: LaunchContractArgs = syn::parse_str("domain = 1, dynamic_shared = 0").unwrap();
+    let mut zero_helper: ItemFn = parse_quote! { fn zero_helper<T>() {} };
+    inject_launch_contract_markers(&zero_args, &mut zero_helper);
+    assert!(
+        !quote!(#zero_helper)
+            .to_string()
+            .contains("__dynamic_shared_alignment")
+    );
+    assert_eq!(
+        quote!(#zero_helper)
+            .to_string()
+            .matches("__launch_contract_config")
+            .count(),
+        1
+    );
+}
+
+#[test]
+fn launch_contract_injects_the_block_marker_only_for_an_exact_block() {
+    let exact: LaunchContractArgs =
+        syn::parse_str("domain = 2, block = (8, 8, 1), dynamic_shared = 0").unwrap();
+    let mut kernel: ItemFn = parse_quote! { fn kernel() {} };
+    inject_launch_contract_markers(&exact, &mut kernel);
+    let expanded = quote!(#kernel).to_string().replace(' ', "");
+    assert_eq!(
+        expanded.matches("__launch_contract_block_config").count(),
+        1
+    );
+    assert!(expanded.contains("__launch_contract_block_config::<8u32,8u32,1u32>"));
+
+    // Without an exact block the kernel keeps whatever `#[launch_bounds]`
+    // declares, so no exact shape reaches the device compiler.
+    let bounded: LaunchContractArgs = syn::parse_str("domain = 1, dynamic_shared = 0").unwrap();
+    let mut unbounded_kernel: ItemFn = parse_quote! { fn unbounded_kernel() {} };
+    inject_launch_contract_markers(&bounded, &mut unbounded_kernel);
+    assert!(
+        !quote!(#unbounded_kernel)
+            .to_string()
+            .contains("__launch_contract_block_config")
+    );
+}
+
+#[test]
+fn launch_contract_keeps_every_marker_when_block_and_shared_are_both_declared() {
+    let args: LaunchContractArgs = syn::parse_str(
+        "domain = 1, block = (256, 1, 1), dynamic_shared = 128, dynamic_shared_alignment = 32",
+    )
+    .unwrap();
+    let mut kernel: ItemFn = parse_quote! { fn kernel() {} };
+    inject_launch_contract_markers(&args, &mut kernel);
+    let expanded = quote!(#kernel).to_string();
+    assert_eq!(expanded.matches("__launch_contract_config").count(), 1);
+    assert_eq!(
+        expanded.matches("__launch_contract_block_config").count(),
+        1
+    );
+    assert_eq!(expanded.matches("__dynamic_shared_alignment").count(), 1);
+}
+
+#[test]
+fn raw_async_launch_macro_leaves_finalization_caller_unsafe() {
+    let inputs: [CudaLaunchAsyncInput; 3] = [
+        parse_quote! {
+            kernel: kernels::map,
+            module: module,
+            config: config,
+            args: []
+        },
+        parse_quote! {
+            kernel: kernels::map::<u32>,
+            module: module,
+            config: config,
+            args: []
+        },
+        parse_quote! {
+            kernel: kernels::map,
+            module: module,
+            config: config,
+            args: [|value: u32| value]
+        },
+    ];
+
+    for input in inputs {
+        let expanded = expand_cuda_launch_async(input).to_string().replace(' ', "");
+        assert!(expanded.contains("AsyncKernelLaunchBuilder::new"));
+        assert!(expanded.contains(".finalize_unchecked(config)"));
+        assert!(!expanded.contains("set_launch_config"));
+        assert!(
+            !expanded.contains("unsafe{"),
+            "the macro must not hide its raw-launch safety obligation: {expanded}"
+        );
+    }
+}
+
+/// Runs the per-loop `#[unroll]` visitor over `func`'s body and returns the
+/// rewritten function as a whitespace-free string, panicking on any
+/// recorded parse error.
+fn run_loop_unroll_visitor(mut func: ItemFn) -> String {
+    rewrite_loop_unroll_attrs(&mut func)
+        .unwrap_or_else(|err| panic!("unexpected unroll-attr error: {err}"));
+    quote!(#func).to_string().replace(' ', "")
+}
+
+#[test]
+fn bare_unroll_on_while_injects_factor_zero_marker() {
+    let func: ItemFn = parse_quote! {
+        fn k() {
+            let mut i = 0u32;
+            #[unroll]
+            while i < 4 { i += 1; }
+        }
+    };
+    let out = run_loop_unroll_visitor(func);
+    // Bare #[unroll] => full unroll (factor 0).
+    assert!(
+        out.contains("cuda_device::thread::__unroll_config::<{0u32}>()"),
+        "expected factor-0 marker:\n{out}"
+    );
+    // The expression attribute must be stripped so rustc never sees it.
+    assert!(
+        !out.contains("#[unroll]"),
+        "the #[unroll] attribute should be removed:\n{out}"
+    );
+}
+
+#[test]
+fn unroll_n_on_for_loop_injects_factor_n_marker() {
+    let func: ItemFn = parse_quote! {
+        fn k() {
+            #[unroll(4)]
+            for i in 0..8 { let _ = i; }
+        }
+    };
+    let out = run_loop_unroll_visitor(func);
+    assert!(
+        out.contains("cuda_device::thread::__unroll_config::<{4}>()"),
+        "expected factor-4 marker:\n{out}"
+    );
+    assert!(
+        !out.contains("#[unroll"),
+        "attribute should be removed:\n{out}"
+    );
+}
+
+#[test]
+fn unroll_on_bare_loop_injects_marker() {
+    let func: ItemFn = parse_quote! {
+        fn k() {
+            #[unroll(2)]
+            loop { break; }
+        }
+    };
+    let out = run_loop_unroll_visitor(func);
+    assert!(
+        out.contains("cuda_device::thread::__unroll_config::<{2}>()"),
+        "expected factor-2 marker on `loop`:\n{out}"
+    );
+}
+
+#[test]
+fn nested_annotated_loop_is_handled() {
+    let func: ItemFn = parse_quote! {
+        fn k() {
+            for outer in 0..2 {
+                if outer == 0 {
+                    #[unroll(3)]
+                    for inner in 0..4 { let _ = inner; }
+                }
+            }
+        }
+    };
+    let out = run_loop_unroll_visitor(func);
+    assert!(
+        out.contains("cuda_device::thread::__unroll_config::<{3}>()"),
+        "expected marker injected into nested loop:\n{out}"
+    );
+}
+
+#[test]
+fn loop_without_unroll_attr_is_unchanged() {
+    // A function whose loops carry no #[unroll] must be byte-identical
+    // before and after the visitor runs (no marker, no edits).
+    let src: ItemFn = parse_quote! {
+        fn k() {
+            let mut i = 0u32;
+            while i < 4 { i += 1; }
+            for j in 0..2 { let _ = j; }
+        }
+    };
+    let before = quote!(#src).to_string();
+    let after = run_loop_unroll_visitor(src);
+    assert_eq!(
+        before.replace(' ', ""),
+        after,
+        "loops without #[unroll] must not be modified"
+    );
+    assert!(
+        !after.contains("__unroll_config"),
+        "no marker should be injected without #[unroll]:\n{after}"
+    );
+}
+
+#[test]
+fn malformed_unroll_attr_records_error() {
+    // `#[unroll(1, 2)]` has too many args; the visitor must record an error.
+    let mut func: ItemFn = parse_quote! {
+        fn k() {
+            #[unroll(1, 2)]
+            for i in 0..4 { let _ = i; }
+        }
+    };
+    let mut visitor = LoopUnrollAttrVisitor::default();
+    visitor.visit_block_mut(&mut func.block);
+    assert!(
+        visitor.error.is_some(),
+        "malformed #[unroll(1, 2)] should record a parse error"
+    );
+}
+
+#[test]
+fn partial_unroll_factor_must_be_at_least_two() {
+    assert!(syn::parse_str::<UnrollArgs>("0").is_err());
+    assert!(syn::parse_str::<UnrollArgs>("1").is_err());
+    assert_eq!(
+        syn::parse_str::<UnrollArgs>("2")
+            .unwrap()
+            .factor
+            .literal_value,
+        Some(2)
+    );
+    assert!(syn::parse_str::<UnrollArgs>("1025").is_err());
+}
+
+#[test]
+fn launch_bounds_keeps_policy_expressions_typed() {
+    let mut function: ItemFn = parse_quote! {
+        fn configured<P: Policy>() {}
+    };
+    let args: LaunchBoundsArgs = syn::parse_str("P::MAX_THREADS * 2, P::MIN_BLOCKS").unwrap();
+    add_const_evaluatable_bound(&mut function.sig.generics, &args.max_threads);
+    add_const_evaluatable_bound(&mut function.sig.generics, &args.min_blocks);
+
+    let max_threads = &args.max_threads.expr;
+    let min_blocks = &args.min_blocks.expr;
+    let marker: Stmt = parse_quote! {
+        ::cuda_device::thread::__launch_bounds_config::<
+            { #max_threads },
+            { #min_blocks },
+        >();
+    };
+    function.block.stmts.insert(0, marker);
+    let output = quote!(#function).to_string().replace(' ', "");
+
+    assert!(
+        output.contains("__launch_bounds_config"),
+        "missing marker: {output}"
+    );
+    assert!(output.contains("{P::MAX_THREADS*2}"), "{output}");
+    assert!(output.contains("{P::MIN_BLOCKS}"), "{output}");
+    assert!(output.contains("[();(P::MAX_THREADS*2)asusize]:"));
+    assert!(output.contains("[();(P::MIN_BLOCKS)asusize]:"));
+}
+
+#[test]
+fn policy_unroll_expression_gets_marker_and_evaluatability_bound() {
+    let func: ItemFn = parse_quote! {
+        fn k<P: Policy>() {
+            let mut i = 0u32;
+            #[unroll(P::UNROLL)]
+            while i < 8 { i += 1; }
+        }
+    };
+    let output = run_loop_unroll_visitor(func);
+
+    assert!(output.contains("__unroll_config::<{P::UNROLL}>()"));
+    assert!(output.contains("[();(P::UNROLL)asusize]:"));
+}
+
+#[test]
+fn function_local_unroll_const_stays_in_block_scope() {
+    let func: ItemFn = parse_quote! {
+        fn k() {
+            const FACTOR: u32 = 4;
+            let mut i = 0u32;
+            #[unroll(FACTOR)]
+            while i < 8 { i += 1; }
+        }
+    };
+    let output = run_loop_unroll_visitor(func);
+
+    assert!(output.contains("__unroll_config::<{FACTOR}>()"));
+    assert!(
+        !output.contains("[();(FACTOR)asusize]:"),
+        "a block-local const must not be copied into the function signature: {output}"
+    );
+}
diff --git a/crates/cuda-macros/src/tests/mod.rs b/crates/cuda-macros/src/tests/mod.rs
new file mode 100644
index 0000000000..8e7851e3b5
--- /dev/null
+++ b/crates/cuda-macros/src/tests/mod.rs
@@ -0,0 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+mod cuda_module;
+mod kernel;
+mod launch;
diff --git a/crates/cuda-oxide-codegen/src/generated.rs b/crates/cuda-oxide-codegen/src/generated.rs
index 42e99903d1..98b09360af 100644
--- a/crates/cuda-oxide-codegen/src/generated.rs
+++ b/crates/cuda-oxide-codegen/src/generated.rs
@@ -408,9 +408,9 @@ fn generated_requirement_error(
 mod tests {
     use super::*;
     use crate::generated_intrinsic_targets::{
-        GENERATED_INTRINSIC_MARKER_ATTR, GENERATED_INTRINSIC_TARGETS, GeneratedHardwareAlternative,
-        GeneratedHardwareTarget, GeneratedPtxVersion, GeneratedTargetAlternative,
-        GeneratedTcgen05MmaForm,
+        GENERATED_INTRINSIC_MARKER_ATTR, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+        GeneratedPtxVersion, GeneratedTargetAlternative, GeneratedTcgen05MmaForm,
+        generated_intrinsic_targets,
     };
     use dialect_nvvm::ops::{
         ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr,
@@ -2113,8 +2113,7 @@ mod tests {
 
     #[test]
     fn tcgen05_mma_kind_contracts_are_retained_per_marker_and_kind() {
-        let target = GENERATED_INTRINSIC_TARGETS
-            .iter()
+        let target = generated_intrinsic_targets()
             .find(|target| target.id == "tcgen05_mma_shared")
             .expect("generated tcgen05 shared MMA target");
         assert_eq!(target.marker, "v1:i0763");
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets.rs
deleted file mode 100644
index 7ad87cdff5..0000000000
--- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets.rs
+++ /dev/null
@@ -1,147261 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
-// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
-// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
-
-//! Generated target requirements and separately imported LLVM/selection facts.
-
-pub const GENERATED_INTRINSIC_MARKER_ATTR: &str = "cuda_oxide_intrinsic_marker";
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
-pub struct GeneratedPtxVersion(u16);
-impl GeneratedPtxVersion {
-    pub const fn from_encoded(encoded: u16) -> Self {
-        Self(encoded)
-    }
-    pub const fn encoded(self) -> u16 {
-        self.0
-    }
-    pub const fn major(self) -> u16 {
-        self.0 / 10
-    }
-    pub const fn minor(self) -> u16 {
-        self.0 % 10
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedHardwareAlternative {
-    MinimumSm(u16),
-    ExactArchitecture(u16),
-    FamilyTarget(u16),
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedTargetSelectorBinding {
-    pub name: &'static str,
-    pub value: &'static str,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedTargetAlternative {
-    pub minimum_ptx: GeneratedPtxVersion,
-    pub hardware: GeneratedHardwareAlternative,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedTargetContract {
-    pub selectors: &'static [GeneratedTargetSelectorBinding],
-    pub alternatives: &'static [GeneratedTargetAlternative],
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedHardwareTarget {
-    All,
-    AnyOf(&'static [GeneratedHardwareAlternative]),
-    TargetMatrix {
-        contracts: &'static [GeneratedTargetContract],
-    },
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedTargetRequirement {
-    pub minimum_ptx: GeneratedPtxVersion,
-    pub hardware: GeneratedHardwareTarget,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedIntrinsicBackend {
-    LlvmNvptx,
-    LibNvvm,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedBackendRequirement {
-    pub backend: GeneratedIntrinsicBackend,
-    pub requirement: GeneratedTargetRequirement,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedSelectionAddressSpace {
-    Generic,
-    Shared,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedImmediateBinding {
-    pub argument_index: usize,
-    pub value: i64,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedSelectionConstraints {
-    pub address_space: Option<GeneratedSelectionAddressSpace>,
-    pub immediate_bindings: &'static [GeneratedImmediateBinding],
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedSelectionAlternative {
-    pub source_record: &'static str,
-    pub asm: &'static str,
-    pub predicates: &'static [&'static str],
-    pub constraints: GeneratedSelectionConstraints,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedIntrinsicRange {
-    pub lower: &'static str,
-    pub upper_exclusive: &'static str,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedLlvmFacts {
-    pub properties: &'static [&'static str],
-    pub result_no_undef: bool,
-    pub result_range: Option<GeneratedIntrinsicRange>,
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedLdmatrixShape {
-    M8n8,
-    M8n16,
-    M16n16,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedLdmatrixMultiplicity {
-    X1,
-    X2,
-    X4,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedLdmatrixLayout {
-    Normal,
-    Transposed,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedLdmatrixElement {
-    B16,
-    B8,
-    B8x16B4x16P64,
-    B8x16B6x16P32,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedPackedAtomicFormat {
-    F16x2,
-    Bf16x2,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedRegisterMmaShape {
-    M8n8k4,
-    M8n8k16,
-    M8n8k32,
-    M8n8k128,
-    M16n8k4,
-    M16n8k8,
-    M16n8k16,
-    M16n8k32,
-    M16n8k64,
-    M16n8k128,
-    M16n8k256,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedRegisterMmaOperation {
-    Multiply,
-    AndPopc,
-    XorPopc,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedRegisterMmaKind {
-    Standard,
-    F8f6f4,
-    Mxf8f6f4,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedRegisterMmaAccumulator {
-    F16,
-    F32,
-    F64,
-    S32,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedRegisterMmaElement {
-    Bf16,
-    E2m1,
-    E2m3,
-    E3m2,
-    E4m3,
-    E5m2,
-    F16,
-    Tf32,
-    F64,
-    B1,
-    S4,
-    U4,
-    S8,
-    U8,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedRegisterMmaLayout {
-    Row,
-    Col,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedRegisterMmaOverflow {
-    NotApplicable,
-    Wrapping,
-    Satfinite,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedSparseMmaShape {
-    M16n8k32,
-    M16n8k64,
-    M16n8k128,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedSparseMmaAccumulator {
-    F16,
-    F32,
-    S32,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedSparseMmaElement {
-    E2m1,
-    E2m3,
-    E3m2,
-    E4m3,
-    E5m2,
-    S4,
-    U4,
-    S8,
-    U8,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedSparseMmaLayout {
-    Row,
-    Col,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedSparseMmaOverflow {
-    NotApplicable,
-    Wrapping,
-    Satfinite,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedSparseMmaMetadata {
-    Standard,
-    Ordered,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedSparseMmaSelector {
-    ImmediateZeroOrOne,
-    ImmediateZero,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedPrmtMode {
-    Generic,
-    F4e,
-    B4e,
-    Rc8,
-    Ecl,
-    Ecr,
-    Rc16,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedClusterBarrierMode {
-    Arrive,
-    ArriveAligned,
-    ArriveRelaxed,
-    ArriveRelaxedAligned,
-    Wait,
-    WaitAligned,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedScalarConversionRounding {
-    NearestAway,
-    NearestEven,
-    TowardZero,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedScalarConversionSaturation {
-    None,
-    Relu,
-    Satfinite,
-    ReluSatfinite,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedWgmmaControlMode {
-    Fence,
-    CommitGroup,
-    WaitGroup,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedScalarArithmeticFormat {
-    F32,
-    F64,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedScalarArithmeticOperation {
-    Mul,
-    Div,
-    Fma,
-    Add,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedScalarArithmeticRounding {
-    Rn,
-    Rz,
-    Rm,
-    Rp,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedScalarArithmeticSubnormal {
-    Preserve,
-    Ftz,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedScalarArithmeticSaturation {
-    None,
-    Sat,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedExtendedMinMaxFormat {
-    F32,
-    F16,
-    Bf16,
-    F16x2,
-    Bf16x2,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedExtendedMinMaxOperation {
-    Min,
-    Max,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedExtendedMinMaxSubnormal {
-    Preserve,
-    Ftz,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedExtendedMinMaxNan {
-    Number,
-    Nan,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedTcgen05MmaForm {
-    Shared,
-    Tensor,
-    TensorAshift,
-    SpShared,
-    SpTensor,
-    SpTensorAshift,
-    WsShared,
-    WsSharedZeroColMask,
-    WsSpShared,
-    WsSpSharedZeroColMask,
-    WsSpTensor,
-    WsSpTensorZeroColMask,
-    WsTensor,
-    WsTensorZeroColMask,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedTcgen05MmaTargetSelector {
-    Kind,
-}
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum GeneratedIntrinsicVariant {
-    Scalar,
-    Ldmatrix {
-        shape: GeneratedLdmatrixShape,
-        multiplicity: GeneratedLdmatrixMultiplicity,
-        layout: GeneratedLdmatrixLayout,
-        element: GeneratedLdmatrixElement,
-    },
-    PackedAtomic {
-        format: GeneratedPackedAtomicFormat,
-    },
-    RegisterMma {
-        shape: GeneratedRegisterMmaShape,
-        operation: GeneratedRegisterMmaOperation,
-        kind: GeneratedRegisterMmaKind,
-        accumulator: GeneratedRegisterMmaAccumulator,
-        a_element: GeneratedRegisterMmaElement,
-        b_element: GeneratedRegisterMmaElement,
-        a_layout: GeneratedRegisterMmaLayout,
-        b_layout: GeneratedRegisterMmaLayout,
-        overflow: GeneratedRegisterMmaOverflow,
-    },
-    SparseMma {
-        shape: GeneratedSparseMmaShape,
-        accumulator: GeneratedSparseMmaAccumulator,
-        a_element: GeneratedSparseMmaElement,
-        b_element: GeneratedSparseMmaElement,
-        a_layout: GeneratedSparseMmaLayout,
-        b_layout: GeneratedSparseMmaLayout,
-        overflow: GeneratedSparseMmaOverflow,
-        metadata: GeneratedSparseMmaMetadata,
-        selector: GeneratedSparseMmaSelector,
-    },
-    Prmt {
-        mode: GeneratedPrmtMode,
-    },
-    ClusterBarrier {
-        mode: GeneratedClusterBarrierMode,
-    },
-    ScalarConversion {
-        rounding: GeneratedScalarConversionRounding,
-        saturation: GeneratedScalarConversionSaturation,
-    },
-    WgmmaControl {
-        mode: GeneratedWgmmaControlMode,
-    },
-    ScalarArithmetic {
-        format: GeneratedScalarArithmeticFormat,
-        operation: GeneratedScalarArithmeticOperation,
-        rounding: GeneratedScalarArithmeticRounding,
-        subnormal: GeneratedScalarArithmeticSubnormal,
-        saturation: GeneratedScalarArithmeticSaturation,
-    },
-    ExtendedMinMax {
-        format: GeneratedExtendedMinMaxFormat,
-        operation: GeneratedExtendedMinMaxOperation,
-        subnormal: GeneratedExtendedMinMaxSubnormal,
-        nan: GeneratedExtendedMinMaxNan,
-        xorsign_abs: bool,
-    },
-    Tcgen05Mma {
-        form: GeneratedTcgen05MmaForm,
-        target_selector: GeneratedTcgen05MmaTargetSelector,
-        compatibility_alias: bool,
-    },
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct GeneratedIntrinsicTarget {
-    pub marker: &'static str,
-    pub id: &'static str,
-    pub abi_id: &'static str,
-    pub dialect_op: &'static str,
-    pub variant: GeneratedIntrinsicVariant,
-    pub requirement: GeneratedTargetRequirement,
-    pub backend_requirements: &'static [GeneratedBackendRequirement],
-    pub selections: &'static [GeneratedSelectionAlternative],
-    pub llvm: Option<GeneratedLlvmFacts>,
-}
-
-impl GeneratedHardwareTarget {
-    pub fn contract_for_selector(
-        self,
-        name: &str,
-        value: &str,
-    ) -> Option<&'static GeneratedTargetContract> {
-        let Self::TargetMatrix { contracts } = self else {
-            return None;
-        };
-        let mut matching = contracts.iter().filter(|contract| {
-            matches!(contract.selectors, [binding] if binding.name == name && binding.value == value)
-        });
-        let contract = matching.next()?;
-        if matching.next().is_some() {
-            None
-        } else {
-            Some(contract)
-        }
-    }
-}
-
-impl GeneratedIntrinsicTarget {
-    pub fn requirement_for_backend(
-        &self,
-        backend: GeneratedIntrinsicBackend,
-    ) -> GeneratedTargetRequirement {
-        self.backend_requirements
-            .iter()
-            .find(|entry| entry.backend == backend)
-            .map(|entry| entry.requirement)
-            .unwrap_or(self.requirement)
-    }
-
-    pub fn target_contract_for_backend_selector(
-        &self,
-        backend: GeneratedIntrinsicBackend,
-        name: &str,
-        value: &str,
-    ) -> Option<&'static GeneratedTargetContract> {
-        self.requirement_for_backend(backend)
-            .hardware
-            .contract_for_selector(name, value)
-    }
-}
-
-pub const GENERATED_INTRINSIC_TARGETS: &[GeneratedIntrinsicTarget] = &[
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0001",
-        id: "thread_idx_x",
-        abi_id: "i0001",
-        dialect_op: "nvvm.read_ptx_sreg_tid_x",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_TID_x",
-            asm: "mov.u32 \t$d, %tid.x;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,1024>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "1024",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0002",
-        id: "block_idx_x",
-        abi_id: "i0002",
-        dialect_op: "nvvm.read_ptx_sreg_ctaid_x",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CTAID_x",
-            asm: "mov.u32 \t$d, %ctaid.x;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,2147483647>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "2147483647",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0003",
-        id: "block_dim_x",
-        abi_id: "i0003",
-        dialect_op: "nvvm.read_ptx_sreg_ntid_x",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_NTID_x",
-            asm: "mov.u32 \t$d, %ntid.x;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,1025>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "1025",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0004",
-        id: "grid_dim_x",
-        abi_id: "i0004",
-        dialect_op: "nvvm.read_ptx_sreg_nctaid_x",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_NCTAID_x",
-            asm: "mov.u32 \t$d, %nctaid.x;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,2147483648>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "2147483648",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0005",
-        id: "thread_idx_y",
-        abi_id: "i0005",
-        dialect_op: "nvvm.read_ptx_sreg_tid_y",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_TID_y",
-            asm: "mov.u32 \t$d, %tid.y;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,1024>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "1024",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0006",
-        id: "block_idx_y",
-        abi_id: "i0006",
-        dialect_op: "nvvm.read_ptx_sreg_ctaid_y",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CTAID_y",
-            asm: "mov.u32 \t$d, %ctaid.y;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "65535",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0007",
-        id: "block_dim_y",
-        abi_id: "i0007",
-        dialect_op: "nvvm.read_ptx_sreg_ntid_y",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_NTID_y",
-            asm: "mov.u32 \t$d, %ntid.y;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,1025>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "1025",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0008",
-        id: "grid_dim_y",
-        abi_id: "i0008",
-        dialect_op: "nvvm.read_ptx_sreg_nctaid_y",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_NCTAID_y",
-            asm: "mov.u32 \t$d, %nctaid.y;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "65536",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0009",
-        id: "thread_idx_z",
-        abi_id: "i0009",
-        dialect_op: "nvvm.read_ptx_sreg_tid_z",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_TID_z",
-            asm: "mov.u32 \t$d, %tid.z;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,64>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "64",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0010",
-        id: "block_idx_z",
-        abi_id: "i0010",
-        dialect_op: "nvvm.read_ptx_sreg_ctaid_z",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CTAID_z",
-            asm: "mov.u32 \t$d, %ctaid.z;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "65535",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0011",
-        id: "block_dim_z",
-        abi_id: "i0011",
-        dialect_op: "nvvm.read_ptx_sreg_ntid_z",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_NTID_z",
-            asm: "mov.u32 \t$d, %ntid.z;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "65",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0012",
-        id: "grid_dim_z",
-        abi_id: "i0012",
-        dialect_op: "nvvm.read_ptx_sreg_nctaid_z",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_NCTAID_z",
-            asm: "mov.u32 \t$d, %nctaid.z;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "65536",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0013",
-        id: "ldmatrix_m8n8_x4_b16",
-        abi_id: "i0013",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n8,
-            multiplicity: GeneratedLdmatrixMultiplicity::X4,
-            layout: GeneratedLdmatrixLayout::Normal,
-            element: GeneratedLdmatrixElement::B16,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20697",
-            asm: "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0014",
-        id: "packed_atomic_add_f16x2",
-        abi_id: "i0014",
-        dialect_op: "nvvm.packed_atomic_add",
-        variant: GeneratedIntrinsicVariant::PackedAtomic {
-            format: GeneratedPackedAtomicFormat::F16x2,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(62),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(62),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(62),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0015",
-        id: "packed_atomic_add_bf16x2",
-        abi_id: "i0015",
-        dialect_op: "nvvm.packed_atomic_add",
-        variant: GeneratedIntrinsicVariant::PackedAtomic {
-            format: GeneratedPackedAtomicFormat::Bf16x2,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0016",
-        id: "lane_id",
-        abi_id: "i0016",
-        dialect_op: "nvvm.read_ptx_sreg_laneid",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(13),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "SREG_LANEID",
-            asm: "mov.u32 \t$d, %laneid;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,32>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "32",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0017",
-        id: "redux_sync_add",
-        abi_id: "i0017",
-        dialect_op: "nvvm.redux_sync_add",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15029",
-            asm: "redux.sync.add.s32 \t$dst, $src, $mask;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0018",
-        id: "redux_sync_min_u32",
-        abi_id: "i0018",
-        dialect_op: "nvvm.redux_sync_umin",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15027",
-            asm: "redux.sync.min.u32 \t$dst, $src, $mask;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0019",
-        id: "redux_sync_min_i32",
-        abi_id: "i0019",
-        dialect_op: "nvvm.redux_sync_min",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15030",
-            asm: "redux.sync.min.s32 \t$dst, $src, $mask;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0020",
-        id: "redux_sync_max_u32",
-        abi_id: "i0020",
-        dialect_op: "nvvm.redux_sync_umax",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15028",
-            asm: "redux.sync.max.u32 \t$dst, $src, $mask;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0021",
-        id: "redux_sync_max_i32",
-        abi_id: "i0021",
-        dialect_op: "nvvm.redux_sync_max",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15031",
-            asm: "redux.sync.max.s32 \t$dst, $src, $mask;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0022",
-        id: "redux_sync_and",
-        abi_id: "i0022",
-        dialect_op: "nvvm.redux_sync_and",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15032",
-            asm: "redux.sync.and.b32 \t$dst, $src, $mask;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0023",
-        id: "redux_sync_or",
-        abi_id: "i0023",
-        dialect_op: "nvvm.redux_sync_or",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15034",
-            asm: "redux.sync.or.b32 \t$dst, $src, $mask;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0024",
-        id: "redux_sync_xor",
-        abi_id: "i0024",
-        dialect_op: "nvvm.redux_sync_xor",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15033",
-            asm: "redux.sync.xor.b32 \t$dst, $src, $mask;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0025",
-        id: "ldmatrix_m8n8_x1_b16",
-        abi_id: "i0025",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n8,
-            multiplicity: GeneratedLdmatrixMultiplicity::X1,
-            layout: GeneratedLdmatrixLayout::Normal,
-            element: GeneratedLdmatrixElement::B16,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20675",
-            asm: "ldmatrix.sync.aligned.m8n8.x1.shared.b16 {{$rx10}}, [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0026",
-        id: "ldmatrix_m8n8_x1_trans_b16",
-        abi_id: "i0026",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n8,
-            multiplicity: GeneratedLdmatrixMultiplicity::X1,
-            layout: GeneratedLdmatrixLayout::Transposed,
-            element: GeneratedLdmatrixElement::B16,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20758",
-            asm: "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16 {{$rx10}}, [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0027",
-        id: "ldmatrix_m8n8_x2_b16",
-        abi_id: "i0027",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n8,
-            multiplicity: GeneratedLdmatrixMultiplicity::X2,
-            layout: GeneratedLdmatrixLayout::Normal,
-            element: GeneratedLdmatrixElement::B16,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20687",
-            asm: "ldmatrix.sync.aligned.m8n8.x2.shared.b16 {{$rx20, $rx21}}, [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0028",
-        id: "ldmatrix_m8n8_x2_trans_b16",
-        abi_id: "i0028",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n8,
-            multiplicity: GeneratedLdmatrixMultiplicity::X2,
-            layout: GeneratedLdmatrixLayout::Transposed,
-            element: GeneratedLdmatrixElement::B16,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20762",
-            asm: "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16 {{$rx20, $rx21}}, [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0029",
-        id: "ldmatrix_m8n8_x4_trans_b16",
-        abi_id: "i0029",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n8,
-            multiplicity: GeneratedLdmatrixMultiplicity::X4,
-            layout: GeneratedLdmatrixLayout::Transposed,
-            element: GeneratedLdmatrixElement::B16,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20766",
-            asm: "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0030",
-        id: "dp4a_s32",
-        abi_id: "i0030",
-        dialect_op: "nvvm.dp4a_s32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                61,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(61),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "DOT4_ss",
-            asm: "dp4a.s32.s32 \t$dst, $a, $b, $c;",
-            predicates: &["hasDotInstructions"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0031",
-        id: "dp4a_u32",
-        abi_id: "i0031",
-        dialect_op: "nvvm.dp4a_u32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                61,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(61),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "DOT4_uu",
-            asm: "dp4a.u32.u32 \t$dst, $a, $b, $c;",
-            predicates: &["hasDotInstructions"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0032",
-        id: "dp2a_s32",
-        abi_id: "i0032",
-        dialect_op: "nvvm.dp2a_s32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                61,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(61),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "DOT2_lo_ss",
-            asm: "dp2a.lo.s32.s32 \t$dst, $a, $b, $c;",
-            predicates: &["hasDotInstructions"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 2,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0033",
-        id: "dp2a_u32",
-        abi_id: "i0033",
-        dialect_op: "nvvm.dp2a_u32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                61,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(61),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "DOT2_lo_uu",
-            asm: "dp2a.lo.u32.u32 \t$dst, $a, $b, $c;",
-            predicates: &["hasDotInstructions"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 2,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0034",
-        id: "sync_threads",
-        abi_id: "i0034",
-        dialect_op: "nvvm.barrier0",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "BARRIER_CTA_SYNC_ALIGNED_ALL_i",
-            asm: "bar.sync \t$i;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0035",
-        id: "lanemask_lt",
-        abi_id: "i0035",
-        dialect_op: "nvvm.read_ptx_sreg_lanemask_lt",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_LANEMASK_LT",
-            asm: "mov.u32 \t$d, %lanemask_lt;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0036",
-        id: "lanemask_le",
-        abi_id: "i0036",
-        dialect_op: "nvvm.read_ptx_sreg_lanemask_le",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_LANEMASK_LE",
-            asm: "mov.u32 \t$d, %lanemask_le;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0037",
-        id: "lanemask_eq",
-        abi_id: "i0037",
-        dialect_op: "nvvm.read_ptx_sreg_lanemask_eq",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_LANEMASK_EQ",
-            asm: "mov.u32 \t$d, %lanemask_eq;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0038",
-        id: "lanemask_ge",
-        abi_id: "i0038",
-        dialect_op: "nvvm.read_ptx_sreg_lanemask_ge",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_LANEMASK_GE",
-            asm: "mov.u32 \t$d, %lanemask_ge;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0039",
-        id: "lanemask_gt",
-        abi_id: "i0039",
-        dialect_op: "nvvm.read_ptx_sreg_lanemask_gt",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_LANEMASK_GT",
-            asm: "mov.u32 \t$d, %lanemask_gt;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0040",
-        id: "all_sync",
-        abi_id: "i0040",
-        dialect_op: "nvvm.vote_sync_all",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "VOTE_SYNC_ALLi",
-                asm: "vote.sync.all.pred \t$dest, $pred, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "VOTE_SYNC_ALLr",
-                asm: "vote.sync.all.pred \t$dest, $pred, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0041",
-        id: "any_sync",
-        abi_id: "i0041",
-        dialect_op: "nvvm.vote_sync_any",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "VOTE_SYNC_ANYi",
-                asm: "vote.sync.any.pred \t$dest, $pred, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "VOTE_SYNC_ANYr",
-                asm: "vote.sync.any.pred \t$dest, $pred, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0042",
-        id: "ballot_sync",
-        abi_id: "i0042",
-        dialect_op: "nvvm.vote_sync_ballot",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "VOTE_SYNC_BALLOTi",
-                asm: "vote.sync.ballot.b32 \t$dest, $pred, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "VOTE_SYNC_BALLOTr",
-                asm: "vote.sync.ballot.b32 \t$dest, $pred, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0043",
-        id: "uni_sync",
-        abi_id: "i0043",
-        dialect_op: "nvvm.vote_sync_uni",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "VOTE_SYNC_UNIi",
-                asm: "vote.sync.uni.pred \t$dest, $pred, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "VOTE_SYNC_UNIr",
-                asm: "vote.sync.uni.pred \t$dest, $pred, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0044",
-        id: "active_mask",
-        abi_id: "i0044",
-        dialect_op: "nvvm.activemask",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(62),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(62),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(62),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "ACTIVEMASK",
-            asm: "activemask.b32 \t$dest;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 30",
-                "Subtarget->getPTXVersion() >= 62",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrHasSideEffects",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0045",
-        id: "match_any_sync",
-        abi_id: "i0045",
-        dialect_op: "nvvm.match_any_sync_i32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ANY_SYNC_32ii",
-                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ANY_SYNC_32ir",
-                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ANY_SYNC_32ri",
-                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ANY_SYNC_32rr",
-                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0046",
-        id: "match_any_i64_sync",
-        abi_id: "i0046",
-        dialect_op: "nvvm.match_any_sync_i64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ANY_SYNC_64ii",
-                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ANY_SYNC_64ir",
-                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ANY_SYNC_64ri",
-                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ANY_SYNC_64rr",
-                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0047",
-        id: "match_all_sync",
-        abi_id: "i0047",
-        dialect_op: "nvvm.match_all_sync_i32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ALLP_SYNC_32ii",
-                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ALLP_SYNC_32ir",
-                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ALLP_SYNC_32ri",
-                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ALLP_SYNC_32rr",
-                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0048",
-        id: "match_all_i64_sync",
-        abi_id: "i0048",
-        dialect_op: "nvvm.match_all_sync_i64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ALLP_SYNC_64ii",
-                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ALLP_SYNC_64ir",
-                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ALLP_SYNC_64ri",
-                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "MATCH_ALLP_SYNC_64rr",
-                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0049",
-        id: "sync_mask",
-        abi_id: "i0049",
-        dialect_op: "nvvm.bar_warp_sync",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "INT_BAR_WARP_SYNC_I",
-                asm: "bar.warp.sync \t$i;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "INT_BAR_WARP_SYNC_R",
-                asm: "bar.warp.sync \t$i;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0050",
-        id: "shuffle_sync",
-        abi_id: "i0050",
-        dialect_op: "nvvm.shfl_sync_idx_i32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14989",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14990",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14991",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14992",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14993",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14994",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14995",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14996",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0051",
-        id: "shuffle_xor_sync",
-        abi_id: "i0051",
-        dialect_op: "nvvm.shfl_sync_bfly_i32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14957",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14958",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14959",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14960",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14961",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14962",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14963",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14964",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0052",
-        id: "shuffle_down_sync",
-        abi_id: "i0052",
-        dialect_op: "nvvm.shfl_sync_down_i32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14925",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14926",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14927",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14928",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14929",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14930",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14931",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14932",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0053",
-        id: "shuffle_up_sync",
-        abi_id: "i0053",
-        dialect_op: "nvvm.shfl_sync_up_i32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14893",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14894",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14895",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14896",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14897",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14898",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14899",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14900",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0054",
-        id: "shuffle_f32_sync",
-        abi_id: "i0054",
-        dialect_op: "nvvm.shfl_sync_idx_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_15005",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_15006",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_15007",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_15008",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_15009",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_15010",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_15011",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_15012",
-                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0055",
-        id: "shuffle_xor_f32_sync",
-        abi_id: "i0055",
-        dialect_op: "nvvm.shfl_sync_bfly_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14973",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14974",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14975",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14976",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14977",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14978",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14979",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14980",
-                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0056",
-        id: "shuffle_down_f32_sync",
-        abi_id: "i0056",
-        dialect_op: "nvvm.shfl_sync_down_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14941",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14942",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14943",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14944",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14945",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14946",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14947",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14948",
-                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0057",
-        id: "shuffle_up_f32_sync",
-        abi_id: "i0057",
-        dialect_op: "nvvm.shfl_sync_up_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14909",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14910",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14911",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14912",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14913",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14914",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14915",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_14916",
-                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 60",
-                    "Subtarget->getSmVersion() >= 30",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0058",
-        id: "shuffle_u64_sync",
-        abi_id: "i0058",
-        dialect_op: "nvvm.shfl_sync_idx_i64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0059",
-        id: "shuffle_xor_u64_sync",
-        abi_id: "i0059",
-        dialect_op: "nvvm.shfl_sync_bfly_i64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0060",
-        id: "shuffle_down_u64_sync",
-        abi_id: "i0060",
-        dialect_op: "nvvm.shfl_sync_down_i64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0061",
-        id: "shuffle_up_u64_sync",
-        abi_id: "i0061",
-        dialect_op: "nvvm.shfl_sync_up_i64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0062",
-        id: "fma_bf16x2",
-        abi_id: "i0062",
-        dialect_op: "nvvm.fma_bf16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_bf16x2",
-            asm: "fma.rn.bf16x2 \t$dst, $src0, $src1, $src2;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0063",
-        id: "fma_relu_bf16x2",
-        abi_id: "i0063",
-        dialect_op: "nvvm.fma_relu_bf16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_relu_bf16x2",
-            asm: "fma.rn.relu.bf16x2 \t$dst, $src0, $src1, $src2;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0064",
-        id: "add_bf16x2",
-        abi_id: "i0064",
-        dialect_op: "nvvm.add_bf16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0065",
-        id: "sub_bf16x2",
-        abi_id: "i0065",
-        dialect_op: "nvvm.sub_bf16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0066",
-        id: "mul_bf16x2",
-        abi_id: "i0066",
-        dialect_op: "nvvm.mul_bf16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0067",
-        id: "min_bf16x2",
-        abi_id: "i0067",
-        dialect_op: "nvvm.min_bf16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_bf16x2",
-            asm: "min.bf16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0068",
-        id: "max_bf16x2",
-        abi_id: "i0068",
-        dialect_op: "nvvm.max_bf16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_bf16x2",
-            asm: "max.bf16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0069",
-        id: "neg_bf16x2",
-        abi_id: "i0069",
-        dialect_op: "nvvm.neg_bf16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_NEG_BF16X2",
-            asm: "neg.bf16x2 \t$dst, $src0;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0070",
-        id: "abs_bf16x2",
-        abi_id: "i0070",
-        dialect_op: "nvvm.abs_bf16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "ABS_BF16X2",
-            asm: "abs.bf16x2 \t$dst, $src0;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0071",
-        id: "cvt_f32x2_bf16x2",
-        abi_id: "i0071",
-        dialect_op: "nvvm.cvt_f32x2_bf16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0072",
-        id: "fma_f16x2",
-        abi_id: "i0072",
-        dialect_op: "nvvm.fma_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_f16x2",
-            asm: "fma.rn.f16x2 \t$dst, $src0, $src1, $src2;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 53",
-                "Subtarget->getPTXVersion() >= 42",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0073",
-        id: "fma_relu_f16x2",
-        abi_id: "i0073",
-        dialect_op: "nvvm.fma_relu_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_relu_f16x2",
-            asm: "fma.rn.relu.f16x2 \t$dst, $src0, $src1, $src2;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0074",
-        id: "add_f16x2",
-        abi_id: "i0074",
-        dialect_op: "nvvm.add_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0075",
-        id: "sub_f16x2",
-        abi_id: "i0075",
-        dialect_op: "nvvm.sub_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0076",
-        id: "mul_f16x2",
-        abi_id: "i0076",
-        dialect_op: "nvvm.mul_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0077",
-        id: "min_f16x2",
-        abi_id: "i0077",
-        dialect_op: "nvvm.min_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_f16x2",
-            asm: "min.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0078",
-        id: "max_f16x2",
-        abi_id: "i0078",
-        dialect_op: "nvvm.max_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_f16x2",
-            asm: "max.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0079",
-        id: "neg_f16x2",
-        abi_id: "i0079",
-        dialect_op: "nvvm.neg_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0080",
-        id: "abs_f16x2",
-        abi_id: "i0080",
-        dialect_op: "nvvm.abs_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "ABS_F16X2",
-            asm: "abs.f16x2 \t$dst, $src0;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 53",
-                "Subtarget->getPTXVersion() >= 65",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0081",
-        id: "cvt_f16x2_f32",
-        abi_id: "i0081",
-        dialect_op: "nvvm.cvt_f16x2_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0082",
-        id: "cvt_rz_f16x2_f32",
-        abi_id: "i0082",
-        dialect_op: "nvvm.cvt_rz_f16x2_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0083",
-        id: "cvt_rn_relu_f16x2_f32",
-        abi_id: "i0083",
-        dialect_op: "nvvm.cvt_rn_relu_f16x2_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0084",
-        id: "cvt_rn_relu_bf16x2_f32",
-        abi_id: "i0084",
-        dialect_op: "nvvm.cvt_rn_relu_bf16x2_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0085",
-        id: "cvt_rz_bf16x2_f32",
-        abi_id: "i0085",
-        dialect_op: "nvvm.cvt_rz_bf16x2_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0086",
-        id: "cp_async_ca_4",
-        abi_id: "i0086",
-        dialect_op: "nvvm.cp_async_ca_4",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4",
-            asm: "cp.async.ca.shared.global [$dst], [$src], 4;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0087",
-        id: "cp_async_ca_zfill_4",
-        abi_id: "i0087",
-        dialect_op: "nvvm.cp_async_ca_zfill_4",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4_s",
-                asm: "cp.async.ca.shared.global [$dst], [$src], 4, $src_size;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4_si",
-                asm: "cp.async.ca.shared.global [$dst], [$src], 4, $src_size;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0088",
-        id: "cp_async_ca_8",
-        abi_id: "i0088",
-        dialect_op: "nvvm.cp_async_ca_8",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8",
-            asm: "cp.async.ca.shared.global [$dst], [$src], 8;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0089",
-        id: "cp_async_ca_zfill_8",
-        abi_id: "i0089",
-        dialect_op: "nvvm.cp_async_ca_zfill_8",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8_s",
-                asm: "cp.async.ca.shared.global [$dst], [$src], 8, $src_size;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8_si",
-                asm: "cp.async.ca.shared.global [$dst], [$src], 8, $src_size;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0090",
-        id: "cp_async_ca_16",
-        abi_id: "i0090",
-        dialect_op: "nvvm.cp_async_ca_16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16",
-            asm: "cp.async.ca.shared.global [$dst], [$src], 16;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0091",
-        id: "cp_async_ca_zfill_16",
-        abi_id: "i0091",
-        dialect_op: "nvvm.cp_async_ca_zfill_16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16_s",
-                asm: "cp.async.ca.shared.global [$dst], [$src], 16, $src_size;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16_si",
-                asm: "cp.async.ca.shared.global [$dst], [$src], 16, $src_size;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0092",
-        id: "cp_async_cg_16",
-        abi_id: "i0092",
-        dialect_op: "nvvm.cp_async_cg_16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16",
-            asm: "cp.async.cg.shared.global [$dst], [$src], 16;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0093",
-        id: "cp_async_cg_zfill_16",
-        abi_id: "i0093",
-        dialect_op: "nvvm.cp_async_cg_zfill_16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16_s",
-                asm: "cp.async.cg.shared.global [$dst], [$src], 16, $src_size;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16_si",
-                asm: "cp.async.cg.shared.global [$dst], [$src], 16, $src_size;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0094",
-        id: "cp_async_commit_group",
-        abi_id: "i0094",
-        dialect_op: "nvvm.cp_async_commit_group",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_COMMIT_GROUP",
-            asm: "cp.async.commit_group;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0095",
-        id: "cp_async_wait_all",
-        abi_id: "i0095",
-        dialect_op: "nvvm.cp_async_wait_all",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_WAIT_ALL",
-            asm: "cp.async.wait_all;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0096",
-        id: "cp_async_wait_group",
-        abi_id: "i0096",
-        dialect_op: "nvvm.cp_async_wait_group",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_WAIT_GROUP",
-            asm: "cp.async.wait_group \t$n;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0097",
-        id: "mbarrier_init",
-        abi_id: "i0097",
-        dialect_op: "nvvm.mbarrier_init_shared",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "MBARRIER_INIT_SHARED",
-            asm: "mbarrier.init.shared.b64 \t[$addr], $count;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0098",
-        id: "mbarrier_arrive",
-        abi_id: "i0098",
-        dialect_op: "nvvm.mbarrier_arrive_shared",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "MBARRIER_ARRIVE_SHARED",
-            asm: "mbarrier.arrive.shared.b64 \t$state, [$addr];",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0099",
-        id: "mbarrier_test_wait",
-        abi_id: "i0099",
-        dialect_op: "nvvm.mbarrier_test_wait_shared",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "MBARRIER_TEST_WAIT_SHARED",
-            asm: "mbarrier.test_wait.shared.b64 \t$res, [$addr], $state;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0100",
-        id: "mbarrier_inval",
-        abi_id: "i0100",
-        dialect_op: "nvvm.mbarrier_inval_shared",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "MBARRIER_INVAL_SHARED",
-            asm: "mbarrier.inval.shared.b64 \t[$addr];",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0101",
-        id: "cp_async_mbarrier_arrive",
-        abi_id: "i0101",
-        dialect_op: "nvvm.cp_async_mbarrier_arrive",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_MBARRIER_ARRIVE",
-            asm: "cp.async.mbarrier.arrive.b64 \t[$addr];",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0102",
-        id: "cp_async_mbarrier_arrive_shared",
-        abi_id: "i0102",
-        dialect_op: "nvvm.cp_async_mbarrier_arrive_shared",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_MBARRIER_ARRIVE_SHARED",
-            asm: "cp.async.mbarrier.arrive.shared.b64 \t[$addr];",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0103",
-        id: "cp_async_mbarrier_arrive_noinc",
-        abi_id: "i0103",
-        dialect_op: "nvvm.cp_async_mbarrier_arrive_noinc",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_MBARRIER_ARRIVE_NOINC",
-            asm: "cp.async.mbarrier.arrive.noinc.b64 \t[$addr];",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0104",
-        id: "cp_async_mbarrier_arrive_noinc_shared",
-        abi_id: "i0104",
-        dialect_op: "nvvm.cp_async_mbarrier_arrive_noinc_shared",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_MBARRIER_ARRIVE_NOINC_SHARED",
-            asm: "cp.async.mbarrier.arrive.noinc.shared.b64 \t[$addr];",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0105",
-        id: "mma_m16n8k16_f32_bf16",
-        abi_id: "i0105",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::Bf16,
-            b_element: GeneratedRegisterMmaElement::Bf16,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_18973",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0106",
-        id: "mma_m16n8k16_f32_f16",
-        abi_id: "i0106",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::F16,
-            b_element: GeneratedRegisterMmaElement::F16,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19051",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0107",
-        id: "mma_m16n8k8_f32_tf32",
-        abi_id: "i0107",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k8,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::Tf32,
-            b_element: GeneratedRegisterMmaElement::Tf32,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_18964",
-            asm: "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0108",
-        id: "mma_m16n8k32_s32_s8",
-        abi_id: "i0108",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19407",
-            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0109",
-        id: "mma_m8n8k4_f64",
-        abi_id: "i0109",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k4,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F64,
-            a_element: GeneratedRegisterMmaElement::F64,
-            b_element: GeneratedRegisterMmaElement::F64,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_18989",
-            asm: "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0110",
-        id: "mma_m16n8k16_s32_s8",
-        abi_id: "i0110",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19383",
-            asm: "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0111",
-        id: "mma_m16n8k16_s32_s8_u8",
-        abi_id: "i0111",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19388",
-            asm: "mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0112",
-        id: "mma_m16n8k16_s32_u8",
-        abi_id: "i0112",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19398",
-            asm: "mma.sync.aligned.m16n8k16.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0113",
-        id: "mma_m16n8k16_s32_u8_s8",
-        abi_id: "i0113",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19394",
-            asm: "mma.sync.aligned.m16n8k16.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0114",
-        id: "mma_m16n8k32_s32_s8_u8",
-        abi_id: "i0114",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19412",
-            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0115",
-        id: "mma_m16n8k32_s32_u8",
-        abi_id: "i0115",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19422",
-            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0116",
-        id: "mma_m16n8k32_s32_u8_s8",
-        abi_id: "i0116",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19418",
-            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0117",
-        id: "mma_m16n8k16_s32_s8_satfinite",
-        abi_id: "i0117",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19546",
-            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0118",
-        id: "mma_m16n8k16_s32_s8_u8_satfinite",
-        abi_id: "i0118",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19549",
-            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0119",
-        id: "mma_m16n8k16_s32_u8_satfinite",
-        abi_id: "i0119",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19555",
-            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0120",
-        id: "mma_m16n8k16_s32_u8_s8_satfinite",
-        abi_id: "i0120",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19552",
-            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0121",
-        id: "mma_m16n8k32_s32_s8_satfinite",
-        abi_id: "i0121",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19558",
-            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0122",
-        id: "mma_m16n8k32_s32_s8_u8_satfinite",
-        abi_id: "i0122",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19561",
-            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0123",
-        id: "mma_m16n8k32_s32_u8_satfinite",
-        abi_id: "i0123",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19567",
-            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0124",
-        id: "mma_m16n8k32_s32_u8_s8_satfinite",
-        abi_id: "i0124",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19564",
-            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0125",
-        id: "mma_m8n8k16_s32_s8",
-        abi_id: "i0125",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19359",
-            asm: "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0126",
-        id: "mma_m8n8k16_s32_s8_u8",
-        abi_id: "i0126",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19364",
-            asm: "mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0127",
-        id: "mma_m8n8k16_s32_u8",
-        abi_id: "i0127",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19374",
-            asm: "mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0128",
-        id: "mma_m8n8k16_s32_u8_s8",
-        abi_id: "i0128",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19370",
-            asm: "mma.sync.aligned.m8n8k16.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0129",
-        id: "mma_m8n8k16_s32_s8_satfinite",
-        abi_id: "i0129",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19534",
-            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0130",
-        id: "mma_m8n8k16_s32_s8_u8_satfinite",
-        abi_id: "i0130",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19537",
-            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0131",
-        id: "mma_m8n8k16_s32_u8_satfinite",
-        abi_id: "i0131",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::U8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19543",
-            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0132",
-        id: "mma_m8n8k16_s32_u8_s8_satfinite",
-        abi_id: "i0132",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U8,
-            b_element: GeneratedRegisterMmaElement::S8,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19540",
-            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0133",
-        id: "mma_m8n8k32_s32_s4",
-        abi_id: "i0133",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19431",
-            asm: "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0134",
-        id: "mma_m8n8k32_s32_s4_u4",
-        abi_id: "i0134",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19436",
-            asm: "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0135",
-        id: "mma_m8n8k32_s32_u4",
-        abi_id: "i0135",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19446",
-            asm: "mma.sync.aligned.m8n8k32.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0136",
-        id: "mma_m8n8k32_s32_u4_s4",
-        abi_id: "i0136",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19442",
-            asm: "mma.sync.aligned.m8n8k32.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0137",
-        id: "mma_m8n8k32_s32_s4_satfinite",
-        abi_id: "i0137",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19570",
-            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0138",
-        id: "mma_m8n8k32_s32_s4_u4_satfinite",
-        abi_id: "i0138",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19573",
-            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0139",
-        id: "mma_m8n8k32_s32_u4_satfinite",
-        abi_id: "i0139",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19579",
-            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0140",
-        id: "mma_m8n8k32_s32_u4_s4_satfinite",
-        abi_id: "i0140",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19576",
-            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0141",
-        id: "mma_m16n8k32_s32_s4",
-        abi_id: "i0141",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19453",
-            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0142",
-        id: "mma_m16n8k32_s32_s4_u4",
-        abi_id: "i0142",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19458",
-            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0143",
-        id: "mma_m16n8k32_s32_u4",
-        abi_id: "i0143",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19468",
-            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0144",
-        id: "mma_m16n8k32_s32_u4_s4",
-        abi_id: "i0144",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19464",
-            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0145",
-        id: "mma_m16n8k64_s32_s4",
-        abi_id: "i0145",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k64,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19477",
-            asm: "mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0146",
-        id: "mma_m16n8k64_s32_s4_u4",
-        abi_id: "i0146",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k64,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19482",
-            asm: "mma.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0147",
-        id: "mma_m16n8k64_s32_u4",
-        abi_id: "i0147",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k64,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19492",
-            asm: "mma.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0148",
-        id: "mma_m16n8k64_s32_u4_s4",
-        abi_id: "i0148",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k64,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19488",
-            asm: "mma.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0149",
-        id: "mma_m16n8k32_s32_s4_satfinite",
-        abi_id: "i0149",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19582",
-            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0150",
-        id: "mma_m16n8k32_s32_s4_u4_satfinite",
-        abi_id: "i0150",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19585",
-            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0151",
-        id: "mma_m16n8k32_s32_u4_satfinite",
-        abi_id: "i0151",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19591",
-            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0152",
-        id: "mma_m16n8k32_s32_u4_s4_satfinite",
-        abi_id: "i0152",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19588",
-            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0153",
-        id: "mma_m16n8k64_s32_s4_satfinite",
-        abi_id: "i0153",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k64,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19594",
-            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0154",
-        id: "mma_m16n8k64_s32_s4_u4_satfinite",
-        abi_id: "i0154",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k64,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::S4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19597",
-            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0155",
-        id: "mma_m16n8k64_s32_u4_satfinite",
-        abi_id: "i0155",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k64,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::U4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19603",
-            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0156",
-        id: "mma_m16n8k64_s32_u4_s4_satfinite",
-        abi_id: "i0156",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k64,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::U4,
-            b_element: GeneratedRegisterMmaElement::S4,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19600",
-            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0157",
-        id: "mma_m8n8k128_s32_b1_xor_popc",
-        abi_id: "i0157",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k128,
-            operation: GeneratedRegisterMmaOperation::XorPopc,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::B1,
-            b_element: GeneratedRegisterMmaElement::B1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19501",
-            asm: "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0158",
-        id: "mma_m16n8k128_s32_b1_xor_popc",
-        abi_id: "i0158",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k128,
-            operation: GeneratedRegisterMmaOperation::XorPopc,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::B1,
-            b_element: GeneratedRegisterMmaElement::B1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19514",
-            asm: "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0159",
-        id: "mma_m16n8k256_s32_b1_xor_popc",
-        abi_id: "i0159",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k256,
-            operation: GeneratedRegisterMmaOperation::XorPopc,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::B1,
-            b_element: GeneratedRegisterMmaElement::B1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19527",
-            asm: "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0160",
-        id: "mma_m8n8k128_s32_b1_and_popc",
-        abi_id: "i0160",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M8n8k128,
-            operation: GeneratedRegisterMmaOperation::AndPopc,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::B1,
-            b_element: GeneratedRegisterMmaElement::B1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19505",
-            asm: "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0161",
-        id: "mma_m16n8k128_s32_b1_and_popc",
-        abi_id: "i0161",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k128,
-            operation: GeneratedRegisterMmaOperation::AndPopc,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::B1,
-            b_element: GeneratedRegisterMmaElement::B1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19518",
-            asm: "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0162",
-        id: "mma_m16n8k256_s32_b1_and_popc",
-        abi_id: "i0162",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k256,
-            operation: GeneratedRegisterMmaOperation::AndPopc,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::S32,
-            a_element: GeneratedRegisterMmaElement::B1,
-            b_element: GeneratedRegisterMmaElement::B1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::Wrapping,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19531",
-            asm: "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0163",
-        id: "mma_sp_m16n8k32_s32_s8",
-        abi_id: "i0163",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19958",
-            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0164",
-        id: "mma_sp_m16n8k32_s32_s8_u8",
-        abi_id: "i0164",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19963",
-            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0165",
-        id: "mma_sp_m16n8k32_s32_u8",
-        abi_id: "i0165",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19972",
-            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0166",
-        id: "mma_sp_m16n8k32_s32_u8_s8",
-        abi_id: "i0166",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19968",
-            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0167",
-        id: "mma_sp_m16n8k32_s32_s8_satfinite",
-        abi_id: "i0167",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20019",
-            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0168",
-        id: "mma_sp_m16n8k32_s32_s8_u8_satfinite",
-        abi_id: "i0168",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20022",
-            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0169",
-        id: "mma_sp_m16n8k32_s32_u8_satfinite",
-        abi_id: "i0169",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20028",
-            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0170",
-        id: "mma_sp_m16n8k32_s32_u8_s8_satfinite",
-        abi_id: "i0170",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20025",
-            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0171",
-        id: "mma_sp_ordered_metadata_m16n8k32_s32_s8",
-        abi_id: "i0171",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20168",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0172",
-        id: "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8",
-        abi_id: "i0172",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20173",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0173",
-        id: "mma_sp_ordered_metadata_m16n8k32_s32_u8",
-        abi_id: "i0173",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20182",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0174",
-        id: "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8",
-        abi_id: "i0174",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20178",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0175",
-        id: "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite",
-        abi_id: "i0175",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20229",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0176",
-        id: "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite",
-        abi_id: "i0176",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20232",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0177",
-        id: "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite",
-        abi_id: "i0177",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20238",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0178",
-        id: "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite",
-        abi_id: "i0178",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k32,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20235",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0179",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_s8",
-        abi_id: "i0179",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20188",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0180",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8",
-        abi_id: "i0180",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20193",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0181",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_u8",
-        abi_id: "i0181",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20202",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0182",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8",
-        abi_id: "i0182",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20198",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0183",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite",
-        abi_id: "i0183",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20241",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0184",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite",
-        abi_id: "i0184",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20244",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0185",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite",
-        abi_id: "i0185",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20250",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0186",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite",
-        abi_id: "i0186",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20247",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0187",
-        id: "mma_sp_m16n8k64_s32_s8",
-        abi_id: "i0187",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19978",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0188",
-        id: "mma_sp_m16n8k64_s32_s8_u8",
-        abi_id: "i0188",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19983",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0189",
-        id: "mma_sp_m16n8k64_s32_u8",
-        abi_id: "i0189",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19992",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0190",
-        id: "mma_sp_m16n8k64_s32_u8_s8",
-        abi_id: "i0190",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19988",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0191",
-        id: "mma_sp_m16n8k64_s32_s8_satfinite",
-        abi_id: "i0191",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20031",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0192",
-        id: "mma_sp_m16n8k64_s32_s8_u8_satfinite",
-        abi_id: "i0192",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20034",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0193",
-        id: "mma_sp_m16n8k64_s32_u8_satfinite",
-        abi_id: "i0193",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::U8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20040",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0194",
-        id: "mma_sp_m16n8k64_s32_u8_s8_satfinite",
-        abi_id: "i0194",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U8,
-            b_element: GeneratedSparseMmaElement::S8,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20037",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0195",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_s4",
-        abi_id: "i0195",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20124",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0196",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4",
-        abi_id: "i0196",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20129",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0197",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_u4",
-        abi_id: "i0197",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20138",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0198",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4",
-        abi_id: "i0198",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20134",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0199",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite",
-        abi_id: "i0199",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20205",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0200",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite",
-        abi_id: "i0200",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20208",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0201",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite",
-        abi_id: "i0201",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20214",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0202",
-        id: "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite",
-        abi_id: "i0202",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20211",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0203",
-        id: "mma_sp_ordered_metadata_m16n8k128_s32_s4",
-        abi_id: "i0203",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20146",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0204",
-        id: "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4",
-        abi_id: "i0204",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20151",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0205",
-        id: "mma_sp_ordered_metadata_m16n8k128_s32_u4",
-        abi_id: "i0205",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20160",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0206",
-        id: "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4",
-        abi_id: "i0206",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20156",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0207",
-        id: "mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite",
-        abi_id: "i0207",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20217",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0208",
-        id: "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite",
-        abi_id: "i0208",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20220",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0209",
-        id: "mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite",
-        abi_id: "i0209",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20226",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0210",
-        id: "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite",
-        abi_id: "i0210",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20223",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 85",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0211",
-        id: "mma_sp_m16n8k64_s32_s4",
-        abi_id: "i0211",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19914",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0212",
-        id: "mma_sp_m16n8k64_s32_s4_u4",
-        abi_id: "i0212",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19919",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0213",
-        id: "mma_sp_m16n8k64_s32_u4",
-        abi_id: "i0213",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19928",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0214",
-        id: "mma_sp_m16n8k64_s32_u4_s4",
-        abi_id: "i0214",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19924",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0215",
-        id: "mma_sp_m16n8k64_s32_s4_satfinite",
-        abi_id: "i0215",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19995",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0216",
-        id: "mma_sp_m16n8k64_s32_s4_u4_satfinite",
-        abi_id: "i0216",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19998",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0217",
-        id: "mma_sp_m16n8k64_s32_u4_satfinite",
-        abi_id: "i0217",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20004",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0218",
-        id: "mma_sp_m16n8k64_s32_u4_s4_satfinite",
-        abi_id: "i0218",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20001",
-            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0219",
-        id: "mma_sp_m16n8k128_s32_s4",
-        abi_id: "i0219",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19936",
-            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0220",
-        id: "mma_sp_m16n8k128_s32_s4_u4",
-        abi_id: "i0220",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19941",
-            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0221",
-        id: "mma_sp_m16n8k128_s32_u4",
-        abi_id: "i0221",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19950",
-            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0222",
-        id: "mma_sp_m16n8k128_s32_u4_s4",
-        abi_id: "i0222",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Wrapping,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19946",
-            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0223",
-        id: "mma_sp_m16n8k128_s32_s4_satfinite",
-        abi_id: "i0223",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20007",
-            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0224",
-        id: "mma_sp_m16n8k128_s32_s4_u4_satfinite",
-        abi_id: "i0224",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::S4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20010",
-            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0225",
-        id: "mma_sp_m16n8k128_s32_u4_satfinite",
-        abi_id: "i0225",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::U4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20016",
-            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0226",
-        id: "mma_sp_m16n8k128_s32_u4_s4_satfinite",
-        abi_id: "i0226",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k128,
-            accumulator: GeneratedSparseMmaAccumulator::S32,
-            a_element: GeneratedSparseMmaElement::U4,
-            b_element: GeneratedSparseMmaElement::S4,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::Satfinite,
-            metadata: GeneratedSparseMmaMetadata::Standard,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20013",
-            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 71",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0227",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32",
-        abi_id: "i0227",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E2m1,
-            b_element: GeneratedSparseMmaElement::E2m1,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20464",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0228",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32",
-        abi_id: "i0228",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E2m1,
-            b_element: GeneratedSparseMmaElement::E2m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20456",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0229",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32",
-        abi_id: "i0229",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E2m1,
-            b_element: GeneratedSparseMmaElement::E3m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20448",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0230",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32",
-        abi_id: "i0230",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E2m1,
-            b_element: GeneratedSparseMmaElement::E4m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20432",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0231",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32",
-        abi_id: "i0231",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E2m1,
-            b_element: GeneratedSparseMmaElement::E5m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20440",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0232",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32",
-        abi_id: "i0232",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E2m3,
-            b_element: GeneratedSparseMmaElement::E2m1,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20423",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0233",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32",
-        abi_id: "i0233",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E2m3,
-            b_element: GeneratedSparseMmaElement::E2m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20415",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0234",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32",
-        abi_id: "i0234",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E2m3,
-            b_element: GeneratedSparseMmaElement::E3m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20407",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0235",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32",
-        abi_id: "i0235",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E2m3,
-            b_element: GeneratedSparseMmaElement::E4m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20391",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0236",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32",
-        abi_id: "i0236",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E2m3,
-            b_element: GeneratedSparseMmaElement::E5m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20399",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0237",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32",
-        abi_id: "i0237",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E3m2,
-            b_element: GeneratedSparseMmaElement::E2m1,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20382",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0238",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32",
-        abi_id: "i0238",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E3m2,
-            b_element: GeneratedSparseMmaElement::E2m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20374",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0239",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32",
-        abi_id: "i0239",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E3m2,
-            b_element: GeneratedSparseMmaElement::E3m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20366",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0240",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32",
-        abi_id: "i0240",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E3m2,
-            b_element: GeneratedSparseMmaElement::E4m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20350",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0241",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32",
-        abi_id: "i0241",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E3m2,
-            b_element: GeneratedSparseMmaElement::E5m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20358",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0242",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32",
-        abi_id: "i0242",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E4m3,
-            b_element: GeneratedSparseMmaElement::E2m1,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20300",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0243",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32",
-        abi_id: "i0243",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E4m3,
-            b_element: GeneratedSparseMmaElement::E2m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20291",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0244",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32",
-        abi_id: "i0244",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E4m3,
-            b_element: GeneratedSparseMmaElement::E3m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20282",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0245",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32",
-        abi_id: "i0245",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E4m3,
-            b_element: GeneratedSparseMmaElement::E4m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20264",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0246",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32",
-        abi_id: "i0246",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E4m3,
-            b_element: GeneratedSparseMmaElement::E5m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20273",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0247",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32",
-        abi_id: "i0247",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E5m2,
-            b_element: GeneratedSparseMmaElement::E2m1,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20341",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0248",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32",
-        abi_id: "i0248",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E5m2,
-            b_element: GeneratedSparseMmaElement::E2m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20333",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0249",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32",
-        abi_id: "i0249",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E5m2,
-            b_element: GeneratedSparseMmaElement::E3m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20325",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0250",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32",
-        abi_id: "i0250",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E5m2,
-            b_element: GeneratedSparseMmaElement::E4m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20309",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0251",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32",
-        abi_id: "i0251",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F32,
-            a_element: GeneratedSparseMmaElement::E5m2,
-            b_element: GeneratedSparseMmaElement::E5m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20317",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0252",
-        id: "prmt",
-        abi_id: "i0252",
-        dialect_op: "nvvm.prmt",
-        variant: GeneratedIntrinsicVariant::Prmt {
-            mode: GeneratedPrmtMode::Generic,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0253",
-        id: "prmt_f4e",
-        abi_id: "i0253",
-        dialect_op: "nvvm.prmt",
-        variant: GeneratedIntrinsicVariant::Prmt {
-            mode: GeneratedPrmtMode::F4e,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0254",
-        id: "prmt_b4e",
-        abi_id: "i0254",
-        dialect_op: "nvvm.prmt",
-        variant: GeneratedIntrinsicVariant::Prmt {
-            mode: GeneratedPrmtMode::B4e,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0255",
-        id: "prmt_rc8",
-        abi_id: "i0255",
-        dialect_op: "nvvm.prmt",
-        variant: GeneratedIntrinsicVariant::Prmt {
-            mode: GeneratedPrmtMode::Rc8,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0256",
-        id: "prmt_ecl",
-        abi_id: "i0256",
-        dialect_op: "nvvm.prmt",
-        variant: GeneratedIntrinsicVariant::Prmt {
-            mode: GeneratedPrmtMode::Ecl,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0257",
-        id: "prmt_ecr",
-        abi_id: "i0257",
-        dialect_op: "nvvm.prmt",
-        variant: GeneratedIntrinsicVariant::Prmt {
-            mode: GeneratedPrmtMode::Ecr,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0258",
-        id: "prmt_rc16",
-        abi_id: "i0258",
-        dialect_op: "nvvm.prmt",
-        variant: GeneratedIntrinsicVariant::Prmt {
-            mode: GeneratedPrmtMode::Rc16,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0259",
-        id: "cvt_rn_satfinite_e4m3x2_f32",
-        abi_id: "i0259",
-        dialect_op: "nvvm.cvt_rn_satfinite_e4m3x2_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0260",
-        id: "cvt_rn_satfinite_relu_e4m3x2_f32",
-        abi_id: "i0260",
-        dialect_op: "nvvm.cvt_rn_satfinite_relu_e4m3x2_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0261",
-        id: "cvt_rn_satfinite_e5m2x2_f32",
-        abi_id: "i0261",
-        dialect_op: "nvvm.cvt_rn_satfinite_e5m2x2_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0262",
-        id: "cvt_rn_satfinite_relu_e5m2x2_f32",
-        abi_id: "i0262",
-        dialect_op: "nvvm.cvt_rn_satfinite_relu_e5m2x2_f32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0263",
-        id: "cluster_block_idx_x",
-        abi_id: "i0263",
-        dialect_op: "nvvm.read_ptx_sreg_cluster_ctaid_x",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTER_CTAID_x",
-            asm: "mov.u32 \t$d, %cluster_ctaid.x;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,2147483647>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "2147483647",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0264",
-        id: "cluster_block_idx_y",
-        abi_id: "i0264",
-        dialect_op: "nvvm.read_ptx_sreg_cluster_ctaid_y",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTER_CTAID_y",
-            asm: "mov.u32 \t$d, %cluster_ctaid.y;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "65535",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0265",
-        id: "cluster_block_idx_z",
-        abi_id: "i0265",
-        dialect_op: "nvvm.read_ptx_sreg_cluster_ctaid_z",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTER_CTAID_z",
-            asm: "mov.u32 \t$d, %cluster_ctaid.z;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "65535",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0266",
-        id: "cluster_dim_x",
-        abi_id: "i0266",
-        dialect_op: "nvvm.read_ptx_sreg_cluster_nctaid_x",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTER_NCTAID_x",
-            asm: "mov.u32 \t$d, %cluster_nctaid.x;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,2147483648>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "2147483648",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0267",
-        id: "cluster_dim_y",
-        abi_id: "i0267",
-        dialect_op: "nvvm.read_ptx_sreg_cluster_nctaid_y",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTER_NCTAID_y",
-            asm: "mov.u32 \t$d, %cluster_nctaid.y;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "65536",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0268",
-        id: "cluster_dim_z",
-        abi_id: "i0268",
-        dialect_op: "nvvm.read_ptx_sreg_cluster_nctaid_z",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTER_NCTAID_z",
-            asm: "mov.u32 \t$d, %cluster_nctaid.z;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "65536",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0269",
-        id: "cluster_idx_x",
-        abi_id: "i0269",
-        dialect_op: "nvvm.read_ptx_sreg_clusterid_x",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTERID_x",
-            asm: "mov.u32 \t$d, %clusterid.x;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,2147483647>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "2147483647",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0270",
-        id: "cluster_idx_y",
-        abi_id: "i0270",
-        dialect_op: "nvvm.read_ptx_sreg_clusterid_y",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTERID_y",
-            asm: "mov.u32 \t$d, %clusterid.y;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "65535",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0271",
-        id: "cluster_idx_z",
-        abi_id: "i0271",
-        dialect_op: "nvvm.read_ptx_sreg_clusterid_z",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTERID_z",
-            asm: "mov.u32 \t$d, %clusterid.z;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "0",
-                upper_exclusive: "65535",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0272",
-        id: "cluster_grid_dim_x",
-        abi_id: "i0272",
-        dialect_op: "nvvm.read_ptx_sreg_nclusterid_x",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_NCLUSTERID_x",
-            asm: "mov.u32 \t$d, %nclusterid.x;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,2147483648>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "2147483648",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0273",
-        id: "cluster_grid_dim_y",
-        abi_id: "i0273",
-        dialect_op: "nvvm.read_ptx_sreg_nclusterid_y",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_NCLUSTERID_y",
-            asm: "mov.u32 \t$d, %nclusterid.y;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "65536",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0274",
-        id: "cluster_grid_dim_z",
-        abi_id: "i0274",
-        dialect_op: "nvvm.read_ptx_sreg_nclusterid_z",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_NCLUSTERID_z",
-            asm: "mov.u32 \t$d, %nclusterid.z;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>",
-            ],
-            result_no_undef: true,
-            result_range: Some(GeneratedIntrinsicRange {
-                lower: "1",
-                upper_exclusive: "65536",
-            }),
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0275",
-        id: "cluster_block_rank",
-        abi_id: "i0275",
-        dialect_op: "nvvm.read_ptx_sreg_cluster_ctarank",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTER_CTARANK",
-            asm: "mov.u32 \t$d, %cluster_ctarank;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0276",
-        id: "cluster_block_count",
-        abi_id: "i0276",
-        dialect_op: "nvvm.read_ptx_sreg_cluster_nctarank",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_CLUSTER_NCTARANK",
-            asm: "mov.u32 \t$d, %cluster_nctarank;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0277",
-        id: "barrier_cluster_arrive",
-        abi_id: "i0277",
-        dialect_op: "nvvm.cluster_barrier",
-        variant: GeneratedIntrinsicVariant::ClusterBarrier {
-            mode: GeneratedClusterBarrierMode::Arrive,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "barrier_cluster_arrive",
-            asm: "barrier.cluster.arrive;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0278",
-        id: "barrier_cluster_arrive_aligned",
-        abi_id: "i0278",
-        dialect_op: "nvvm.cluster_barrier",
-        variant: GeneratedIntrinsicVariant::ClusterBarrier {
-            mode: GeneratedClusterBarrierMode::ArriveAligned,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "barrier_cluster_arrive_aligned",
-            asm: "barrier.cluster.arrive.aligned;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0279",
-        id: "barrier_cluster_arrive_relaxed",
-        abi_id: "i0279",
-        dialect_op: "nvvm.cluster_barrier",
-        variant: GeneratedIntrinsicVariant::ClusterBarrier {
-            mode: GeneratedClusterBarrierMode::ArriveRelaxed,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "barrier_cluster_arrive_relaxed",
-            asm: "barrier.cluster.arrive.relaxed;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0280",
-        id: "barrier_cluster_arrive_relaxed_aligned",
-        abi_id: "i0280",
-        dialect_op: "nvvm.cluster_barrier",
-        variant: GeneratedIntrinsicVariant::ClusterBarrier {
-            mode: GeneratedClusterBarrierMode::ArriveRelaxedAligned,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "barrier_cluster_arrive_relaxed_aligned",
-            asm: "barrier.cluster.arrive.relaxed.aligned;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0281",
-        id: "barrier_cluster_wait",
-        abi_id: "i0281",
-        dialect_op: "nvvm.cluster_barrier",
-        variant: GeneratedIntrinsicVariant::ClusterBarrier {
-            mode: GeneratedClusterBarrierMode::Wait,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "barrier_cluster_wait",
-            asm: "barrier.cluster.wait;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0282",
-        id: "barrier_cluster_wait_aligned",
-        abi_id: "i0282",
-        dialect_op: "nvvm.cluster_barrier",
-        variant: GeneratedIntrinsicVariant::ClusterBarrier {
-            mode: GeneratedClusterBarrierMode::WaitAligned,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "barrier_cluster_wait_aligned",
-            asm: "barrier.cluster.wait.aligned;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0283",
-        id: "clock",
-        abi_id: "i0283",
-        dialect_op: "nvvm.read_ptx_sreg_clock",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "SREG_CLOCK",
-            asm: "mov.u32 \t$d, %clock;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-                "IntrNoFree",
-                "IntrWillReturn",
-                "NoUndef<ret>",
-            ],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0284",
-        id: "clock64",
-        abi_id: "i0284",
-        dialect_op: "nvvm.read_ptx_sreg_clock64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "SREG_CLOCK64",
-            asm: "mov.u64 \t$d, %clock64;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-                "IntrNoFree",
-                "IntrWillReturn",
-                "NoUndef<ret>",
-            ],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0285",
-        id: "globaltimer",
-        abi_id: "i0285",
-        dialect_op: "nvvm.read_ptx_sreg_globaltimer",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(31),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(31),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "SREG_GLOBALTIMER",
-            asm: "mov.u64 \t$d, %globaltimer;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-                "IntrNoFree",
-                "IntrWillReturn",
-                "NoUndef<ret>",
-            ],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0286",
-        id: "envreg1",
-        abi_id: "i0286",
-        dialect_op: "nvvm.read_ptx_sreg_envreg1",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(21),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(21),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0287",
-        id: "envreg2",
-        abi_id: "i0287",
-        dialect_op: "nvvm.read_ptx_sreg_envreg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(21),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(21),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0288",
-        id: "smid",
-        abi_id: "i0288",
-        dialect_op: "nvvm.read_ptx_sreg_smid",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(13),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(13),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "SREG_SMID",
-            asm: "mov.u32 \t$d, %smid;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0289",
-        id: "nsmid",
-        abi_id: "i0289",
-        dialect_op: "nvvm.read_ptx_sreg_nsmid",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "SREG_NSMID",
-            asm: "mov.u32 \t$d, %nsmid;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0290",
-        id: "gridid",
-        abi_id: "i0290",
-        dialect_op: "nvvm.read_ptx_sreg_gridid",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(30),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(30),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0291",
-        id: "warpid",
-        abi_id: "i0291",
-        dialect_op: "nvvm.read_ptx_sreg_warpid",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(13),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(13),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "SREG_WARPID",
-            asm: "mov.u32 \t$d, %warpid;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0292",
-        id: "nwarpid",
-        abi_id: "i0292",
-        dialect_op: "nvvm.read_ptx_sreg_nwarpid",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "SREG_NWARPID",
-            asm: "mov.u32 \t$d, %nwarpid;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0293",
-        id: "dynamic_smem_size",
-        abi_id: "i0293",
-        dialect_op: "nvvm.read_ptx_sreg_dynamic_smem_size",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(41),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(41),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(41),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_DYNAMIC_SMEM_SIZE",
-            asm: "mov.u32 \t$d, %dynamic_smem_size;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0294",
-        id: "total_smem_size",
-        abi_id: "i0294",
-        dialect_op: "nvvm.read_ptx_sreg_total_smem_size",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(41),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(41),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(41),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_PTX_SREG_TOTAL_SMEM_SIZE",
-            asm: "mov.u32 \t$d, %total_smem_size;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
-            result_no_undef: true,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0295",
-        id: "trap",
-        abi_id: "i0295",
-        dialect_op: "nvvm.trap",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0296",
-        id: "breakpoint",
-        abi_id: "i0296",
-        dialect_op: "nvvm.brkpt",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                11,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0297",
-        id: "pmevent",
-        abi_id: "i0297",
-        dialect_op: "nvvm.pmevent",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(14),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0298",
-        id: "threadfence_block",
-        abi_id: "i0298",
-        dialect_op: "nvvm.threadfence_block",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(14),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_MEMBAR_CTA",
-            asm: "membar.cta;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0299",
-        id: "threadfence",
-        abi_id: "i0299",
-        dialect_op: "nvvm.threadfence",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(14),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_MEMBAR_GL",
-            asm: "membar.gl;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0300",
-        id: "threadfence_system",
-        abi_id: "i0300",
-        dialect_op: "nvvm.threadfence_system",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                20,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_MEMBAR_SYS",
-            asm: "membar.sys;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0301",
-        id: "stmatrix_m8n8_x2_b16",
-        abi_id: "i0301",
-        dialect_op: "nvvm.stmatrix_m8n8_x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0302",
-        id: "stmatrix_m8n8_x2_trans_b16",
-        abi_id: "i0302",
-        dialect_op: "nvvm.stmatrix_m8n8_x2_trans",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0303",
-        id: "stmatrix_m8n8_x4_b16",
-        abi_id: "i0303",
-        dialect_op: "nvvm.stmatrix_m8n8_x4",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0304",
-        id: "stmatrix_m8n8_x4_trans_b16",
-        abi_id: "i0304",
-        dialect_op: "nvvm.stmatrix_m8n8_x4_trans",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0305",
-        id: "movmatrix_trans_b16",
-        abi_id: "i0305",
-        dialect_op: "nvvm.movmatrix_trans_b16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0306",
-        id: "mbarrier_arrive_expect_tx",
-        abi_id: "i0306",
-        dialect_op: "nvvm.mbarrier_arrive_expect_tx_shared",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0307",
-        id: "mbarrier_arrive_expect_tx_cluster",
-        abi_id: "i0307",
-        dialect_op: "nvvm.mbarrier_arrive_expect_tx_cluster",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrArgMemOnly", "IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0308",
-        id: "mbarrier_arrive_cluster",
-        abi_id: "i0308",
-        dialect_op: "nvvm.mbarrier_arrive_cluster",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0309",
-        id: "mbarrier_try_wait",
-        abi_id: "i0309",
-        dialect_op: "nvvm.mbarrier_try_wait_shared",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "mbar_try_wait_scope_cta_acquire_STATE",
-            asm: "mbarrier.try_wait.shared.b64 $res, [$addr], $state;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0310",
-        id: "mbarrier_try_wait_parity",
-        abi_id: "i0310",
-        dialect_op: "nvvm.mbarrier_try_wait_parity_shared",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0311",
-        id: "mbarrier_try_wait_parity_cluster",
-        abi_id: "i0311",
-        dialect_op: "nvvm.mbarrier_try_wait_parity_cluster",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0312",
-        id: "fence_proxy_async_shared_cta",
-        abi_id: "i0312",
-        dialect_op: "nvvm.fence_proxy_async_shared_cta",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15048",
-            asm: "fence.proxy.async.shared::cta;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0313",
-        id: "fence_mbarrier_init_release_cluster",
-        abi_id: "i0313",
-        dialect_op: "nvvm.fence_mbarrier_init_release_cluster",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_FENCE_MBARRIER_INIT_RELEASE_CLUSTER",
-            asm: "fence.mbarrier_init.release.cluster;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0314",
-        id: "fence_proxy_async_generic_release_shared_cta_cluster",
-        abi_id: "i0314",
-        dialect_op: "nvvm.fence_proxy_async_generic_release_shared_cta_cluster",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FENCE_PROXY_ASYNC_GENERIC_RELEASE_SYNC_RESTRICT_SPACE_CTA_SCOPE_CLUSTER",
-            asm: "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0315",
-        id: "fence_proxy_async_generic_acquire_shared_cluster_cluster",
-        abi_id: "i0315",
-        dialect_op: "nvvm.fence_proxy_async_generic_acquire_shared_cluster_cluster",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FENCE_PROXY_ASYNC_GENERIC_ACQUIRE_SYNC_RESTRICT_SPACE_CLUSTER_SCOPE_CLUSTER",
-            asm: "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0316",
-        id: "nanosleep",
-        abi_id: "i0316",
-        dialect_op: "nvvm.nanosleep",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(63),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(63),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(63),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_NANOSLEEP_I",
-                asm: "nanosleep.u32 \t$i;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 70",
-                    "Subtarget->getPTXVersion() >= 63",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_NANOSLEEP_R",
-                asm: "nanosleep.u32 \t$i;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 70",
-                    "Subtarget->getPTXVersion() >= 63",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrHasSideEffects", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0317",
-        id: "wgmma_fence",
-        abi_id: "i0317",
-        dialect_op: "nvvm.wgmma_fence_sync_aligned",
-        variant: GeneratedIntrinsicVariant::WgmmaControl {
-            mode: GeneratedWgmmaControlMode::Fence,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "WGMMA_FENCE_SYNC_ALIGNED",
-            asm: "wgmma.fence.sync.aligned;",
-            predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0318",
-        id: "wgmma_commit_group",
-        abi_id: "i0318",
-        dialect_op: "nvvm.wgmma_commit_group_sync_aligned",
-        variant: GeneratedIntrinsicVariant::WgmmaControl {
-            mode: GeneratedWgmmaControlMode::CommitGroup,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "WGMMA_COMMIT_GROUP_SYNC_ALIGNED",
-            asm: "wgmma.commit_group.sync.aligned;",
-            predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0319",
-        id: "wgmma_wait_group",
-        abi_id: "i0319",
-        dialect_op: "nvvm.wgmma_wait_group_sync_aligned",
-        variant: GeneratedIntrinsicVariant::WgmmaControl {
-            mode: GeneratedWgmmaControlMode::WaitGroup,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "WGMMA_WAIT_GROUP_SYNC_ALIGNED",
-            asm: "wgmma.wait_group.sync.aligned \t$n;",
-            predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg0>", "IntrConvergent"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0320",
-        id: "map_shared_rank",
-        abi_id: "i0320",
-        dialect_op: "nvvm.mapa_shared_cluster",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "mapa_shared_cluster_64",
-                asm: "mapa.shared::cluster.u64 \t$d, $a, $b;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "mapa_shared_cluster_64i",
-                asm: "mapa.shared::cluster.u64 \t$d, $a, $b;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable", "NoCapture<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0321",
-        id: "dsmem_read_u32",
-        abi_id: "i0321",
-        dialect_op: "nvvm.dsmem_read_u32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0322",
-        id: "clc_try_cancel",
-        abi_id: "i0322",
-        dialect_op: "nvvm.clc_try_cancel",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CLUSTERLAUNCHCONTRL_TRY_CANCEL",
-            asm: "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 \t[$addr], [$mbar];",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 100",
-                "Subtarget->getPTXVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrArgMemOnly", "IntrHasSideEffects"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0323",
-        id: "clc_try_cancel_multicast",
-        abi_id: "i0323",
-        dialect_op: "nvvm.clc_try_cancel_multicast",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CLUSTERLAUNCHCONTRL_TRY_CANCEL_MULTICAST",
-            asm: "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 \t[$addr], [$mbar];",
-            predicates: &["Subtarget->hasClusterLaunchControlTryCancelMulticastSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrArgMemOnly", "IntrHasSideEffects"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0324",
-        id: "clc_query_is_canceled",
-        abi_id: "i0324",
-        dialect_op: "nvvm.clc_query_is_canceled",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0325",
-        id: "clc_query_get_first_ctaid_x",
-        abi_id: "i0325",
-        dialect_op: "nvvm.clc_query_get_first_ctaid_x",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0326",
-        id: "clc_query_get_first_ctaid_y",
-        abi_id: "i0326",
-        dialect_op: "nvvm.clc_query_get_first_ctaid_y",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0327",
-        id: "clc_query_get_first_ctaid_z",
-        abi_id: "i0327",
-        dialect_op: "nvvm.clc_query_get_first_ctaid_z",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0328",
-        id: "cp_async_bulk_tensor_1d_g2s",
-        abi_id: "i0328",
-        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_1d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_G2S_TILE_CG0_1D",
-            asm: "cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0}}], [$mbar];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[
-                    GeneratedImmediateBinding {
-                        argument_index: 6,
-                        value: 0,
-                    },
-                    GeneratedImmediateBinding {
-                        argument_index: 7,
-                        value: 0,
-                    },
-                ],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "Range<arg8,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0329",
-        id: "cp_async_bulk_tensor_2d_g2s",
-        abi_id: "i0329",
-        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_2d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_G2S_TILE_CG0_2D",
-            asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[
-                    GeneratedImmediateBinding {
-                        argument_index: 7,
-                        value: 0,
-                    },
-                    GeneratedImmediateBinding {
-                        argument_index: 8,
-                        value: 0,
-                    },
-                ],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrConvergent",
-                "Range<arg9,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0330",
-        id: "cp_async_bulk_tensor_2d_g2s_multicast",
-        abi_id: "i0330",
-        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_G2S_TILE_CG0_2D_MC",
-            asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[
-                    GeneratedImmediateBinding {
-                        argument_index: 7,
-                        value: -1,
-                    },
-                    GeneratedImmediateBinding {
-                        argument_index: 8,
-                        value: 0,
-                    },
-                ],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrConvergent",
-                "Range<arg9,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0331",
-        id: "cp_async_bulk_tensor_2d_g2s_multicast_cg2",
-        abi_id: "i0331",
-        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_G2S_TILE_2D_MC",
-            asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
-            predicates: &["Subtarget->hasTMABlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[
-                    GeneratedImmediateBinding {
-                        argument_index: 7,
-                        value: -1,
-                    },
-                    GeneratedImmediateBinding {
-                        argument_index: 8,
-                        value: 0,
-                    },
-                ],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrConvergent",
-                "Range<arg9,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0332",
-        id: "cp_async_bulk_tensor_3d_g2s",
-        abi_id: "i0332",
-        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_G2S_TILE_CG0_3D",
-            asm: "cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2}}], [$mbar];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[
-                    GeneratedImmediateBinding {
-                        argument_index: 8,
-                        value: 0,
-                    },
-                    GeneratedImmediateBinding {
-                        argument_index: 9,
-                        value: 0,
-                    },
-                ],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg10>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrConvergent",
-                "Range<arg10,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0333",
-        id: "cp_async_bulk_tensor_4d_g2s",
-        abi_id: "i0333",
-        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_G2S_TILE_CG0_4D",
-            asm: "cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3}}], [$mbar];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[
-                    GeneratedImmediateBinding {
-                        argument_index: 9,
-                        value: 0,
-                    },
-                    GeneratedImmediateBinding {
-                        argument_index: 10,
-                        value: 0,
-                    },
-                ],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg10>",
-                "ImmArg<arg11>",
-                "ImmArg<arg9>",
-                "IntrConvergent",
-                "Range<arg11,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0334",
-        id: "cp_async_bulk_tensor_5d_g2s",
-        abi_id: "i0334",
-        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_G2S_TILE_CG0_5D",
-            asm: "cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$mbar];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[
-                    GeneratedImmediateBinding {
-                        argument_index: 10,
-                        value: 0,
-                    },
-                    GeneratedImmediateBinding {
-                        argument_index: 11,
-                        value: 0,
-                    },
-                ],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg10>",
-                "ImmArg<arg11>",
-                "ImmArg<arg12>",
-                "IntrConvergent",
-                "Range<arg12,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0335",
-        id: "cp_async_bulk_tensor_1d_s2g",
-        abi_id: "i0335",
-        dialect_op: "nvvm.cp_async_bulk_tensor_s2g_tile_1d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_S2G_TILE_1D",
-            asm: "cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [$tmap, {{$d0}}], [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 4,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0336",
-        id: "cp_async_bulk_tensor_2d_s2g",
-        abi_id: "i0336",
-        dialect_op: "nvvm.cp_async_bulk_tensor_s2g_tile_2d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_S2G_TILE_2D",
-            asm: "cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1}}], [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 5,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0337",
-        id: "cp_async_bulk_tensor_3d_s2g",
-        abi_id: "i0337",
-        dialect_op: "nvvm.cp_async_bulk_tensor_s2g_tile_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_S2G_TILE_3D",
-            asm: "cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2}}], [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 6,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0338",
-        id: "cp_async_bulk_tensor_4d_s2g",
-        abi_id: "i0338",
-        dialect_op: "nvvm.cp_async_bulk_tensor_s2g_tile_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_S2G_TILE_4D",
-            asm: "cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3}}], [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 7,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0339",
-        id: "cp_async_bulk_tensor_5d_s2g",
-        abi_id: "i0339",
-        dialect_op: "nvvm.cp_async_bulk_tensor_s2g_tile_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_S2G_TILE_5D",
-            asm: "cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$src];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 8,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0340",
-        id: "cp_async_bulk_commit_group",
-        abi_id: "i0340",
-        dialect_op: "nvvm.cp_async_bulk_commit_group",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_BULK_COMMIT_GROUP",
-            asm: "cp.async.bulk.commit_group;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0341",
-        id: "cp_async_bulk_wait_group",
-        abi_id: "i0341",
-        dialect_op: "nvvm.cp_async_bulk_wait_group",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_BULK_WAIT_GROUP",
-            asm: "cp.async.bulk.wait_group \t$n;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0342",
-        id: "cp_async_bulk_wait_group_read",
-        abi_id: "i0342",
-        dialect_op: "nvvm.cp_async_bulk_wait_group_read",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CP_ASYNC_BULK_WAIT_GROUP_READ",
-            asm: "cp.async.bulk.wait_group.read \t$n;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0343",
-        id: "tcgen05_alloc",
-        abi_id: "i0343",
-        dialect_op: "nvvm.tcgen05_alloc",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_ALLOC_S64_CG1",
-            asm: "tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 \t[$dst], $ncols;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0344",
-        id: "tcgen05_dealloc",
-        abi_id: "i0344",
-        dialect_op: "nvvm.tcgen05_dealloc",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_DEALLOC_CG1",
-            asm: "tcgen05.dealloc.cta_group::1.sync.aligned.b32 \t$tmem_addr, $ncols;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0345",
-        id: "tcgen05_relinquish_alloc_permit",
-        abi_id: "i0345",
-        dialect_op: "nvvm.tcgen05_relinquish_alloc_permit",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_RELINQ_CG1",
-            asm: "tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrInaccessibleMemOnly"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0346",
-        id: "tcgen05_fence_before_thread_sync",
-        abi_id: "i0346",
-        dialect_op: "nvvm.tcgen05_fence_before_thread_sync",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "tcgen05_fence_before_thread_sync",
-            asm: "tcgen05.fence::before_thread_sync;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrHasSideEffects", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0347",
-        id: "tcgen05_fence_after_thread_sync",
-        abi_id: "i0347",
-        dialect_op: "nvvm.tcgen05_fence_after_thread_sync",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "tcgen05_fence_after_thread_sync",
-            asm: "tcgen05.fence::after_thread_sync;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrHasSideEffects", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0348",
-        id: "tcgen05_commit",
-        abi_id: "i0348",
-        dialect_op: "nvvm.tcgen05_commit",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0349",
-        id: "tcgen05_commit_shared_cluster",
-        abi_id: "i0349",
-        dialect_op: "nvvm.tcgen05_commit_shared_cluster",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_COMMIT_S64_CG1",
-            asm: "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0350",
-        id: "tcgen05_mma_ws_f16",
-        abi_id: "i0350",
-        dialect_op: "nvvm.tcgen05_mma_ws_f16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0351",
-        id: "tcgen05_mma_f16",
-        abi_id: "i0351",
-        dialect_op: "nvvm.tcgen05_mma_f16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0352",
-        id: "tcgen05_mma_ws_bf16",
-        abi_id: "i0352",
-        dialect_op: "nvvm.tcgen05_mma_ws_bf16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0353",
-        id: "tcgen05_mma_ws_tf32",
-        abi_id: "i0353",
-        dialect_op: "nvvm.tcgen05_mma_ws_tf32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0354",
-        id: "tcgen05_cp_smem_to_tmem",
-        abi_id: "i0354",
-        dialect_op: "nvvm.tcgen05_cp_smem_to_tmem",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x256b_cg1",
-            asm: "tcgen05.cp.cta_group::1.128x256b \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0355",
-        id: "tcgen05_ld_16x256b_x8_pure",
-        abi_id: "i0355",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x8_pure",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0356",
-        id: "tcgen05_ld_16x256b_pure",
-        abi_id: "i0356",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_pure",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0357",
-        id: "tcgen05_load_wait",
-        abi_id: "i0357",
-        dialect_op: "nvvm.tcgen05_load_wait",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "tcgen05_wait_ld",
-            asm: "tcgen05.wait::ld.sync.aligned;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrInaccessibleMemOnly"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0358",
-        id: "tcgen05_store_wait",
-        abi_id: "i0358",
-        dialect_op: "nvvm.tcgen05_store_wait",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "tcgen05_wait_st",
-            asm: "tcgen05.wait::st.sync.aligned;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrInaccessibleMemOnly"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0359",
-        id: "tcgen05_alloc_cg2",
-        abi_id: "i0359",
-        dialect_op: "nvvm.tcgen05_alloc_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_ALLOC_S64_CG2",
-            asm: "tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 \t[$dst], $ncols;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0360",
-        id: "tcgen05_dealloc_cg2",
-        abi_id: "i0360",
-        dialect_op: "nvvm.tcgen05_dealloc_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_DEALLOC_CG2",
-            asm: "tcgen05.dealloc.cta_group::2.sync.aligned.b32 \t$tmem_addr, $ncols;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0361",
-        id: "tcgen05_relinquish_alloc_permit_cg2",
-        abi_id: "i0361",
-        dialect_op: "nvvm.tcgen05_relinquish_alloc_permit_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_RELINQ_CG2",
-            asm: "tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrInaccessibleMemOnly"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0362",
-        id: "tcgen05_mma_f16_cg2",
-        abi_id: "i0362",
-        dialect_op: "nvvm.tcgen05_mma_f16_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0363",
-        id: "tcgen05_commit_cg2",
-        abi_id: "i0363",
-        dialect_op: "nvvm.tcgen05_commit_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0364",
-        id: "tcgen05_commit_shared_cluster_cg2",
-        abi_id: "i0364",
-        dialect_op: "nvvm.tcgen05_commit_shared_cluster_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_COMMIT_S64_CG2",
-            asm: "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0365",
-        id: "tcgen05_commit_multicast_cg2",
-        abi_id: "i0365",
-        dialect_op: "nvvm.tcgen05_commit_multicast_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_COMMIT_S64_CG2_MC",
-            asm: "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0366",
-        id: "tcgen05_cp_smem_to_tmem_cg2",
-        abi_id: "i0366",
-        dialect_op: "nvvm.tcgen05_cp_smem_to_tmem_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x256b_cg2",
-            asm: "tcgen05.cp.cta_group::2.128x256b \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0367",
-        id: "elect_sync",
-        abi_id: "i0367",
-        dialect_op: "nvvm.elect_sync",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "INT_ELECT_SYNC_I",
-                asm: "elect.sync \t$dest|$pred, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "INT_ELECT_SYNC_R",
-                asm: "elect.sync \t$dest|$pred, $mask;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90",
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrInaccessibleMemOnly"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0368",
-        id: "cvt_rna_tf32_f32",
-        abi_id: "i0368",
-        dialect_op: "nvvm.scalar_conversion",
-        variant: GeneratedIntrinsicVariant::ScalarConversion {
-            rounding: GeneratedScalarConversionRounding::NearestAway,
-            saturation: GeneratedScalarConversionSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CVT_to_tf32_rna",
-            asm: "cvt.rna.tf32.f32 \t$dst, $src;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0369",
-        id: "cvt_rna_satfinite_tf32_f32",
-        abi_id: "i0369",
-        dialect_op: "nvvm.scalar_conversion",
-        variant: GeneratedIntrinsicVariant::ScalarConversion {
-            rounding: GeneratedScalarConversionRounding::NearestAway,
-            saturation: GeneratedScalarConversionSaturation::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CVT_to_tf32_rna_satf",
-            asm: "cvt.rna.satfinite.tf32.f32 \t$dst, $src;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 81",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0370",
-        id: "cvt_rn_tf32_f32",
-        abi_id: "i0370",
-        dialect_op: "nvvm.scalar_conversion",
-        variant: GeneratedIntrinsicVariant::ScalarConversion {
-            rounding: GeneratedScalarConversionRounding::NearestEven,
-            saturation: GeneratedScalarConversionSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CVT_to_tf32_rn",
-            asm: "cvt.rn.tf32.f32 \t$dst, $src;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0371",
-        id: "cvt_rn_relu_tf32_f32",
-        abi_id: "i0371",
-        dialect_op: "nvvm.scalar_conversion",
-        variant: GeneratedIntrinsicVariant::ScalarConversion {
-            rounding: GeneratedScalarConversionRounding::NearestEven,
-            saturation: GeneratedScalarConversionSaturation::Relu,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CVT_to_tf32_rn_relu",
-            asm: "cvt.rn.relu.tf32.f32 \t$dst, $src;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0372",
-        id: "cvt_rn_satfinite_tf32_f32",
-        abi_id: "i0372",
-        dialect_op: "nvvm.scalar_conversion",
-        variant: GeneratedIntrinsicVariant::ScalarConversion {
-            rounding: GeneratedScalarConversionRounding::NearestEven,
-            saturation: GeneratedScalarConversionSaturation::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CVT_to_tf32_rn_satf",
-            asm: "cvt.rn.satfinite.tf32.f32 \t$dst, $src;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 100",
-                "Subtarget->getPTXVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0373",
-        id: "cvt_rn_relu_satfinite_tf32_f32",
-        abi_id: "i0373",
-        dialect_op: "nvvm.scalar_conversion",
-        variant: GeneratedIntrinsicVariant::ScalarConversion {
-            rounding: GeneratedScalarConversionRounding::NearestEven,
-            saturation: GeneratedScalarConversionSaturation::ReluSatfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CVT_to_tf32_rn_relu_satf",
-            asm: "cvt.rn.relu.satfinite.tf32.f32 \t$dst, $src;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 100",
-                "Subtarget->getPTXVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0374",
-        id: "cvt_rz_tf32_f32",
-        abi_id: "i0374",
-        dialect_op: "nvvm.scalar_conversion",
-        variant: GeneratedIntrinsicVariant::ScalarConversion {
-            rounding: GeneratedScalarConversionRounding::TowardZero,
-            saturation: GeneratedScalarConversionSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CVT_to_tf32_rz",
-            asm: "cvt.rz.tf32.f32 \t$dst, $src;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0375",
-        id: "cvt_rz_relu_tf32_f32",
-        abi_id: "i0375",
-        dialect_op: "nvvm.scalar_conversion",
-        variant: GeneratedIntrinsicVariant::ScalarConversion {
-            rounding: GeneratedScalarConversionRounding::TowardZero,
-            saturation: GeneratedScalarConversionSaturation::Relu,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CVT_to_tf32_rz_relu",
-            asm: "cvt.rz.relu.tf32.f32 \t$dst, $src;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0376",
-        id: "cvt_rz_satfinite_tf32_f32",
-        abi_id: "i0376",
-        dialect_op: "nvvm.scalar_conversion",
-        variant: GeneratedIntrinsicVariant::ScalarConversion {
-            rounding: GeneratedScalarConversionRounding::TowardZero,
-            saturation: GeneratedScalarConversionSaturation::Satfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CVT_to_tf32_rz_satf",
-            asm: "cvt.rz.satfinite.tf32.f32 \t$dst, $src;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 100",
-                "Subtarget->getPTXVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0377",
-        id: "cvt_rz_relu_satfinite_tf32_f32",
-        abi_id: "i0377",
-        dialect_op: "nvvm.scalar_conversion",
-        variant: GeneratedIntrinsicVariant::ScalarConversion {
-            rounding: GeneratedScalarConversionRounding::TowardZero,
-            saturation: GeneratedScalarConversionSaturation::ReluSatfinite,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "CVT_to_tf32_rz_relu_satf",
-            asm: "cvt.rz.relu.satfinite.tf32.f32 \t$dst, $src;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 100",
-                "Subtarget->getPTXVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0378",
-        id: "ldmatrix_m16n16_x1_trans_b8",
-        abi_id: "i0378",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M16n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X1,
-            layout: GeneratedLdmatrixLayout::Transposed,
-            element: GeneratedLdmatrixElement::B8,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20772",
-            asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {{$rx10, $rx11}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0379",
-        id: "ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64",
-        abi_id: "i0379",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M16n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X1,
-            layout: GeneratedLdmatrixLayout::Transposed,
-            element: GeneratedLdmatrixElement::B8x16B4x16P64,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20782",
-            asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b4x16_p64 {{$rx10, $rx11}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0380",
-        id: "ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32",
-        abi_id: "i0380",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M16n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X1,
-            layout: GeneratedLdmatrixLayout::Transposed,
-            element: GeneratedLdmatrixElement::B8x16B6x16P32,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20777",
-            asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b6x16_p32 {{$rx10, $rx11}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0381",
-        id: "ldmatrix_m16n16_x2_trans_b8",
-        abi_id: "i0381",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M16n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X2,
-            layout: GeneratedLdmatrixLayout::Transposed,
-            element: GeneratedLdmatrixElement::B8,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20789",
-            asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0382",
-        id: "ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64",
-        abi_id: "i0382",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M16n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X2,
-            layout: GeneratedLdmatrixLayout::Transposed,
-            element: GeneratedLdmatrixElement::B8x16B4x16P64,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20799",
-            asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b4x16_p64 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0383",
-        id: "ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32",
-        abi_id: "i0383",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M16n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X2,
-            layout: GeneratedLdmatrixLayout::Transposed,
-            element: GeneratedLdmatrixElement::B8x16B6x16P32,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20794",
-            asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b6x16_p32 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0384",
-        id: "ldmatrix_m8n16_x1_b8x16_b4x16_p64",
-        abi_id: "i0384",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X1,
-            layout: GeneratedLdmatrixLayout::Normal,
-            element: GeneratedLdmatrixElement::B8x16B4x16P64,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20707",
-            asm: "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b4x16_p64 {{$rx10}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0385",
-        id: "ldmatrix_m8n16_x1_b8x16_b6x16_p32",
-        abi_id: "i0385",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X1,
-            layout: GeneratedLdmatrixLayout::Normal,
-            element: GeneratedLdmatrixElement::B8x16B6x16P32,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20702",
-            asm: "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b6x16_p32 {{$rx10}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0386",
-        id: "ldmatrix_m8n16_x2_b8x16_b4x16_p64",
-        abi_id: "i0386",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X2,
-            layout: GeneratedLdmatrixLayout::Normal,
-            element: GeneratedLdmatrixElement::B8x16B4x16P64,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20717",
-            asm: "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b4x16_p64 {{$rx20, $rx21}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0387",
-        id: "ldmatrix_m8n16_x2_b8x16_b6x16_p32",
-        abi_id: "i0387",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X2,
-            layout: GeneratedLdmatrixLayout::Normal,
-            element: GeneratedLdmatrixElement::B8x16B6x16P32,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20712",
-            asm: "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b6x16_p32 {{$rx20, $rx21}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0388",
-        id: "ldmatrix_m8n16_x4_b8x16_b4x16_p64",
-        abi_id: "i0388",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X4,
-            layout: GeneratedLdmatrixLayout::Normal,
-            element: GeneratedLdmatrixElement::B8x16B4x16P64,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20727",
-            asm: "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b4x16_p64 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0389",
-        id: "ldmatrix_m8n16_x4_b8x16_b6x16_p32",
-        abi_id: "i0389",
-        dialect_op: "nvvm.ldmatrix",
-        variant: GeneratedIntrinsicVariant::Ldmatrix {
-            shape: GeneratedLdmatrixShape::M8n16,
-            multiplicity: GeneratedLdmatrixMultiplicity::X4,
-            layout: GeneratedLdmatrixLayout::Normal,
-            element: GeneratedLdmatrixElement::B8x16B6x16P32,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20722",
-            asm: "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b6x16_p32 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
-            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0390",
-        id: "mul_rn_f64",
-        abi_id: "i0390",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RN_D",
-            asm: "mul.rn.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0391",
-        id: "mul_rz_f64",
-        abi_id: "i0391",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RZ_D",
-            asm: "mul.rz.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0392",
-        id: "mul_rm_f64",
-        abi_id: "i0392",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RM_D",
-            asm: "mul.rm.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0393",
-        id: "mul_rp_f64",
-        abi_id: "i0393",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RP_D",
-            asm: "mul.rp.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0394",
-        id: "div_rn_f64",
-        abi_id: "i0394",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RN_D",
-            asm: "div.rn.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0395",
-        id: "div_rz_f64",
-        abi_id: "i0395",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RZ_D",
-            asm: "div.rz.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0396",
-        id: "div_rm_f64",
-        abi_id: "i0396",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RM_D",
-            asm: "div.rm.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0397",
-        id: "div_rp_f64",
-        abi_id: "i0397",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RP_D",
-            asm: "div.rp.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0398",
-        id: "fma_rn_f64",
-        abi_id: "i0398",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_f64",
-            asm: "fma.rn.f64 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0399",
-        id: "fma_rz_f64",
-        abi_id: "i0399",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rz_f64",
-            asm: "fma.rz.f64 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0400",
-        id: "fma_rm_f64",
-        abi_id: "i0400",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rm_f64",
-            asm: "fma.rm.f64 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0401",
-        id: "fma_rp_f64",
-        abi_id: "i0401",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rp_f64",
-            asm: "fma.rp.f64 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0402",
-        id: "mul_rn_f32",
-        abi_id: "i0402",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RN_F",
-            asm: "mul.rn.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0403",
-        id: "mul_rn_ftz_f32",
-        abi_id: "i0403",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RN_FTZ_F",
-            asm: "mul.rn.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0404",
-        id: "mul_rz_f32",
-        abi_id: "i0404",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RZ_F",
-            asm: "mul.rz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0405",
-        id: "mul_rz_ftz_f32",
-        abi_id: "i0405",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RZ_FTZ_F",
-            asm: "mul.rz.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0406",
-        id: "mul_rm_f32",
-        abi_id: "i0406",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RM_F",
-            asm: "mul.rm.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0407",
-        id: "mul_rm_ftz_f32",
-        abi_id: "i0407",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RM_FTZ_F",
-            asm: "mul.rm.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0408",
-        id: "mul_rp_f32",
-        abi_id: "i0408",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RP_F",
-            asm: "mul.rp.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0409",
-        id: "mul_rp_ftz_f32",
-        abi_id: "i0409",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Mul,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_MUL_RP_FTZ_F",
-            asm: "mul.rp.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0410",
-        id: "div_rn_f32",
-        abi_id: "i0410",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RN_F",
-            asm: "div.rn.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0411",
-        id: "div_rn_ftz_f32",
-        abi_id: "i0411",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RN_FTZ_F",
-            asm: "div.rn.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0412",
-        id: "div_rz_f32",
-        abi_id: "i0412",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RZ_F",
-            asm: "div.rz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0413",
-        id: "div_rz_ftz_f32",
-        abi_id: "i0413",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RZ_FTZ_F",
-            asm: "div.rz.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0414",
-        id: "div_rm_f32",
-        abi_id: "i0414",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RM_F",
-            asm: "div.rm.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0415",
-        id: "div_rm_ftz_f32",
-        abi_id: "i0415",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RM_FTZ_F",
-            asm: "div.rm.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0416",
-        id: "div_rp_f32",
-        abi_id: "i0416",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RP_F",
-            asm: "div.rp.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0417",
-        id: "div_rp_ftz_f32",
-        abi_id: "i0417",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Div,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_DIV_RP_FTZ_F",
-            asm: "div.rp.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0418",
-        id: "fma_rn_f32",
-        abi_id: "i0418",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_f32",
-            asm: "fma.rn.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0419",
-        id: "fma_rn_ftz_f32",
-        abi_id: "i0419",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_ftz_f32",
-            asm: "fma.rn.ftz.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0420",
-        id: "fma_rn_sat_f32",
-        abi_id: "i0420",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_sat_f32",
-            asm: "fma.rn.sat.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0421",
-        id: "fma_rn_ftz_sat_f32",
-        abi_id: "i0421",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_ftz_sat_f32",
-            asm: "fma.rn.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0422",
-        id: "fma_rz_f32",
-        abi_id: "i0422",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rz_f32",
-            asm: "fma.rz.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0423",
-        id: "fma_rz_ftz_f32",
-        abi_id: "i0423",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rz_ftz_f32",
-            asm: "fma.rz.ftz.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0424",
-        id: "fma_rz_sat_f32",
-        abi_id: "i0424",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rz_sat_f32",
-            asm: "fma.rz.sat.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0425",
-        id: "fma_rz_ftz_sat_f32",
-        abi_id: "i0425",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rz_ftz_sat_f32",
-            asm: "fma.rz.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0426",
-        id: "fma_rm_f32",
-        abi_id: "i0426",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rm_f32",
-            asm: "fma.rm.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0427",
-        id: "fma_rm_ftz_f32",
-        abi_id: "i0427",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rm_ftz_f32",
-            asm: "fma.rm.ftz.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0428",
-        id: "fma_rm_sat_f32",
-        abi_id: "i0428",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rm_sat_f32",
-            asm: "fma.rm.sat.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0429",
-        id: "fma_rm_ftz_sat_f32",
-        abi_id: "i0429",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rm_ftz_sat_f32",
-            asm: "fma.rm.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0430",
-        id: "fma_rp_f32",
-        abi_id: "i0430",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rp_f32",
-            asm: "fma.rp.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0431",
-        id: "fma_rp_ftz_f32",
-        abi_id: "i0431",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rp_ftz_f32",
-            asm: "fma.rp.ftz.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0432",
-        id: "fma_rp_sat_f32",
-        abi_id: "i0432",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rp_sat_f32",
-            asm: "fma.rp.sat.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0433",
-        id: "fma_rp_ftz_sat_f32",
-        abi_id: "i0433",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Fma,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rp_ftz_sat_f32",
-            asm: "fma.rp.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0434",
-        id: "add_rn_f64",
-        abi_id: "i0434",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RN_D",
-            asm: "add.rn.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0435",
-        id: "add_rz_f64",
-        abi_id: "i0435",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RZ_D",
-            asm: "add.rz.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0436",
-        id: "add_rm_f64",
-        abi_id: "i0436",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RM_D",
-            asm: "add.rm.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0437",
-        id: "add_rp_f64",
-        abi_id: "i0437",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F64,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RP_D",
-            asm: "add.rp.f64 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0438",
-        id: "add_rn_f32",
-        abi_id: "i0438",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RN_F",
-            asm: "add.rn.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0439",
-        id: "add_rn_ftz_f32",
-        abi_id: "i0439",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RN_FTZ_F",
-            asm: "add.rn.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0440",
-        id: "add_rn_sat_f32",
-        abi_id: "i0440",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RN_SAT_F",
-            asm: "add.rn.sat.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0441",
-        id: "add_rn_ftz_sat_f32",
-        abi_id: "i0441",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rn,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RN_SAT_FTZ_F",
-            asm: "add.rn.sat.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0442",
-        id: "add_rz_f32",
-        abi_id: "i0442",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RZ_F",
-            asm: "add.rz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0443",
-        id: "add_rz_ftz_f32",
-        abi_id: "i0443",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RZ_FTZ_F",
-            asm: "add.rz.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0444",
-        id: "add_rz_sat_f32",
-        abi_id: "i0444",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RZ_SAT_F",
-            asm: "add.rz.sat.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0445",
-        id: "add_rz_ftz_sat_f32",
-        abi_id: "i0445",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rz,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RZ_SAT_FTZ_F",
-            asm: "add.rz.sat.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0446",
-        id: "add_rm_f32",
-        abi_id: "i0446",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RM_F",
-            asm: "add.rm.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0447",
-        id: "add_rm_ftz_f32",
-        abi_id: "i0447",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RM_FTZ_F",
-            asm: "add.rm.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0448",
-        id: "add_rm_sat_f32",
-        abi_id: "i0448",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RM_SAT_F",
-            asm: "add.rm.sat.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0449",
-        id: "add_rm_ftz_sat_f32",
-        abi_id: "i0449",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rm,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RM_SAT_FTZ_F",
-            asm: "add.rm.sat.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0450",
-        id: "add_rp_f32",
-        abi_id: "i0450",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RP_F",
-            asm: "add.rp.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0451",
-        id: "add_rp_ftz_f32",
-        abi_id: "i0451",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::None,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RP_FTZ_F",
-            asm: "add.rp.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0452",
-        id: "add_rp_sat_f32",
-        abi_id: "i0452",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RP_SAT_F",
-            asm: "add.rp.sat.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0453",
-        id: "add_rp_ftz_sat_f32",
-        abi_id: "i0453",
-        dialect_op: "nvvm.scalar_arithmetic",
-        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
-            format: GeneratedScalarArithmeticFormat::F32,
-            operation: GeneratedScalarArithmeticOperation::Add,
-            rounding: GeneratedScalarArithmeticRounding::Rp,
-            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-            saturation: GeneratedScalarArithmeticSaturation::Sat,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_ADD_RP_SAT_FTZ_F",
-            asm: "add.rp.sat.ftz.f32 \t$dst, $src0, $src1;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0454",
-        id: "mma_m16n8k32_f32_e2m1_e2m1",
-        abi_id: "i0454",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19350",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0455",
-        id: "mma_m16n8k32_f32_e2m1_e2m3",
-        abi_id: "i0455",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19342",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0456",
-        id: "mma_m16n8k32_f32_e2m1_e3m2",
-        abi_id: "i0456",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19334",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0457",
-        id: "mma_m16n8k32_f32_e2m1_e4m3",
-        abi_id: "i0457",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19318",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0458",
-        id: "mma_m16n8k32_f32_e2m1_e5m2",
-        abi_id: "i0458",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19326",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0459",
-        id: "mma_m16n8k32_f32_e2m3_e2m1",
-        abi_id: "i0459",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19308",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0460",
-        id: "mma_m16n8k32_f32_e2m3_e2m3",
-        abi_id: "i0460",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19300",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0461",
-        id: "mma_m16n8k32_f32_e2m3_e3m2",
-        abi_id: "i0461",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19292",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0462",
-        id: "mma_m16n8k32_f32_e2m3_e4m3",
-        abi_id: "i0462",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19276",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0463",
-        id: "mma_m16n8k32_f32_e2m3_e5m2",
-        abi_id: "i0463",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19284",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0464",
-        id: "mma_m16n8k32_f32_e3m2_e2m1",
-        abi_id: "i0464",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19266",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0465",
-        id: "mma_m16n8k32_f32_e3m2_e2m3",
-        abi_id: "i0465",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19258",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0466",
-        id: "mma_m16n8k32_f32_e3m2_e3m2",
-        abi_id: "i0466",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19250",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0467",
-        id: "mma_m16n8k32_f32_e3m2_e4m3",
-        abi_id: "i0467",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19234",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0468",
-        id: "mma_m16n8k32_f32_e3m2_e5m2",
-        abi_id: "i0468",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19242",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0469",
-        id: "mma_m16n8k32_f32_e4m3_e2m1",
-        abi_id: "i0469",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19164",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0470",
-        id: "mma_m16n8k32_f32_e4m3_e2m3",
-        abi_id: "i0470",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19155",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0471",
-        id: "mma_m16n8k32_f32_e4m3_e3m2",
-        abi_id: "i0471",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19146",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0472",
-        id: "mma_m16n8k32_f32_e4m3_e4m3",
-        abi_id: "i0472",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19119",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0473",
-        id: "mma_m16n8k32_f32_e4m3_e5m2",
-        abi_id: "i0473",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19137",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0474",
-        id: "mma_m16n8k32_f32_e5m2_e2m1",
-        abi_id: "i0474",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19224",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0475",
-        id: "mma_m16n8k32_f32_e5m2_e2m3",
-        abi_id: "i0475",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19216",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0476",
-        id: "mma_m16n8k32_f32_e5m2_e3m2",
-        abi_id: "i0476",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19208",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0477",
-        id: "mma_m16n8k32_f32_e5m2_e4m3",
-        abi_id: "i0477",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19184",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0478",
-        id: "mma_m16n8k32_f32_e5m2_e5m2",
-        abi_id: "i0478",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19200",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0479",
-        id: "mma_m16n8k32_f16_e2m1_e2m1",
-        abi_id: "i0479",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19346",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0480",
-        id: "mma_m16n8k32_f16_e2m1_e2m3",
-        abi_id: "i0480",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19338",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0481",
-        id: "mma_m16n8k32_f16_e2m1_e3m2",
-        abi_id: "i0481",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19330",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0482",
-        id: "mma_m16n8k32_f16_e2m1_e4m3",
-        abi_id: "i0482",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19314",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0483",
-        id: "mma_m16n8k32_f16_e2m1_e5m2",
-        abi_id: "i0483",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19322",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0484",
-        id: "mma_m16n8k32_f16_e2m3_e2m1",
-        abi_id: "i0484",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19304",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0485",
-        id: "mma_m16n8k32_f16_e2m3_e2m3",
-        abi_id: "i0485",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19296",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0486",
-        id: "mma_m16n8k32_f16_e2m3_e3m2",
-        abi_id: "i0486",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19288",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0487",
-        id: "mma_m16n8k32_f16_e2m3_e4m3",
-        abi_id: "i0487",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19272",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0488",
-        id: "mma_m16n8k32_f16_e2m3_e5m2",
-        abi_id: "i0488",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19280",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0489",
-        id: "mma_m16n8k32_f16_e3m2_e2m1",
-        abi_id: "i0489",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19262",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0490",
-        id: "mma_m16n8k32_f16_e3m2_e2m3",
-        abi_id: "i0490",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19254",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0491",
-        id: "mma_m16n8k32_f16_e3m2_e3m2",
-        abi_id: "i0491",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19246",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0492",
-        id: "mma_m16n8k32_f16_e3m2_e4m3",
-        abi_id: "i0492",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19230",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0493",
-        id: "mma_m16n8k32_f16_e3m2_e5m2",
-        abi_id: "i0493",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19238",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0494",
-        id: "mma_m16n8k32_f16_e4m3_e2m1",
-        abi_id: "i0494",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19160",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0495",
-        id: "mma_m16n8k32_f16_e4m3_e2m3",
-        abi_id: "i0495",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19151",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0496",
-        id: "mma_m16n8k32_f16_e4m3_e3m2",
-        abi_id: "i0496",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19142",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0497",
-        id: "mma_m16n8k32_f16_e4m3_e4m3",
-        abi_id: "i0497",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19107",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0498",
-        id: "mma_m16n8k32_f16_e4m3_e5m2",
-        abi_id: "i0498",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19129",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0499",
-        id: "mma_m16n8k32_f16_e5m2_e2m1",
-        abi_id: "i0499",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19220",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0500",
-        id: "mma_m16n8k32_f16_e5m2_e2m3",
-        abi_id: "i0500",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19212",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0501",
-        id: "mma_m16n8k32_f16_e5m2_e3m2",
-        abi_id: "i0501",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19204",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0502",
-        id: "mma_m16n8k32_f16_e5m2_e4m3",
-        abi_id: "i0502",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19176",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0503",
-        id: "mma_m16n8k32_f16_e5m2_e5m2",
-        abi_id: "i0503",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::F8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19192",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0504",
-        id: "mma_m16n8k16_fp8_f16_e4m3_e4m3",
-        abi_id: "i0504",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19058",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 87",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0505",
-        id: "mma_m16n8k16_fp8_f16_e4m3_e5m2",
-        abi_id: "i0505",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19067",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 87",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0506",
-        id: "mma_m16n8k16_fp8_f16_e5m2_e4m3",
-        abi_id: "i0506",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19077",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 87",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0507",
-        id: "mma_m16n8k16_fp8_f16_e5m2_e5m2",
-        abi_id: "i0507",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19085",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 87",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0508",
-        id: "mma_m16n8k16_fp8_f32_e4m3_e4m3",
-        abi_id: "i0508",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19062",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 87",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0509",
-        id: "mma_m16n8k16_fp8_f32_e4m3_e5m2",
-        abi_id: "i0509",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19071",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 87",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0510",
-        id: "mma_m16n8k16_fp8_f32_e5m2_e4m3",
-        abi_id: "i0510",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19081",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 87",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0511",
-        id: "mma_m16n8k16_fp8_f32_e5m2_e5m2",
-        abi_id: "i0511",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19089",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 87",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0512",
-        id: "mma_m16n8k32_fp8_f16_e4m3_e4m3",
-        abi_id: "i0512",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19098",
-            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 84",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0513",
-        id: "mma_m16n8k32_fp8_f16_e4m3_e5m2",
-        abi_id: "i0513",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19124",
-            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 84",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0514",
-        id: "mma_m16n8k32_fp8_f16_e5m2_e4m3",
-        abi_id: "i0514",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19170",
-            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 84",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0515",
-        id: "mma_m16n8k32_fp8_f16_e5m2_e5m2",
-        abi_id: "i0515",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19188",
-            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 84",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0516",
-        id: "mma_m16n8k32_fp8_f32_e4m3_e4m3",
-        abi_id: "i0516",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19113",
-            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 84",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0517",
-        id: "mma_m16n8k32_fp8_f32_e4m3_e5m2",
-        abi_id: "i0517",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19133",
-            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 84",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0518",
-        id: "mma_m16n8k32_fp8_f32_e5m2_e4m3",
-        abi_id: "i0518",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19180",
-            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 84",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0519",
-        id: "mma_m16n8k32_fp8_f32_e5m2_e5m2",
-        abi_id: "i0519",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19196",
-            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 89",
-                "Subtarget->getPTXVersion() >= 84",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0520",
-        id: "mma_m16n8k4_f32_tf32",
-        abi_id: "i0520",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k4,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::Tf32,
-            b_element: GeneratedRegisterMmaElement::Tf32,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_18955",
-            asm: "mma.sync.aligned.m16n8k4.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0521",
-        id: "mma_m16n8k8_f16_f16",
-        abi_id: "i0521",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k8,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::F16,
-            b_element: GeneratedRegisterMmaElement::F16,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19034",
-            asm: "mma.sync.aligned.m16n8k8.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0522",
-        id: "mma_m16n8k8_f32_bf16",
-        abi_id: "i0522",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k8,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::Bf16,
-            b_element: GeneratedRegisterMmaElement::Bf16,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_18980",
-            asm: "mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0523",
-        id: "mma_m16n8k8_f32_f16",
-        abi_id: "i0523",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k8,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::F16,
-            b_element: GeneratedRegisterMmaElement::F16,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19038",
-            asm: "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 65",
-                "Subtarget->getSmVersion() >= 75",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0524",
-        id: "mma_m16n8k16_f16_f16",
-        abi_id: "i0524",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k16,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Standard,
-            accumulator: GeneratedRegisterMmaAccumulator::F16,
-            a_element: GeneratedRegisterMmaElement::F16,
-            b_element: GeneratedRegisterMmaElement::F16,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19047",
-            asm: "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0525",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16",
-        abi_id: "i0525",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E2m1,
-            b_element: GeneratedSparseMmaElement::E2m1,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20460",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0526",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16",
-        abi_id: "i0526",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E2m1,
-            b_element: GeneratedSparseMmaElement::E2m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20452",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0527",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16",
-        abi_id: "i0527",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E2m1,
-            b_element: GeneratedSparseMmaElement::E3m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20444",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0528",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16",
-        abi_id: "i0528",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E2m1,
-            b_element: GeneratedSparseMmaElement::E4m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20428",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0529",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16",
-        abi_id: "i0529",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E2m1,
-            b_element: GeneratedSparseMmaElement::E5m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20436",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0530",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16",
-        abi_id: "i0530",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E2m3,
-            b_element: GeneratedSparseMmaElement::E2m1,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20419",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0531",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16",
-        abi_id: "i0531",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E2m3,
-            b_element: GeneratedSparseMmaElement::E2m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20411",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0532",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16",
-        abi_id: "i0532",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E2m3,
-            b_element: GeneratedSparseMmaElement::E3m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20403",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0533",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16",
-        abi_id: "i0533",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E2m3,
-            b_element: GeneratedSparseMmaElement::E4m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20387",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0534",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16",
-        abi_id: "i0534",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E2m3,
-            b_element: GeneratedSparseMmaElement::E5m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20395",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0535",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16",
-        abi_id: "i0535",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E3m2,
-            b_element: GeneratedSparseMmaElement::E2m1,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20378",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0536",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16",
-        abi_id: "i0536",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E3m2,
-            b_element: GeneratedSparseMmaElement::E2m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20370",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0537",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16",
-        abi_id: "i0537",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E3m2,
-            b_element: GeneratedSparseMmaElement::E3m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20362",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0538",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16",
-        abi_id: "i0538",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E3m2,
-            b_element: GeneratedSparseMmaElement::E4m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20346",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0539",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16",
-        abi_id: "i0539",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E3m2,
-            b_element: GeneratedSparseMmaElement::E5m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20354",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0540",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16",
-        abi_id: "i0540",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E4m3,
-            b_element: GeneratedSparseMmaElement::E2m1,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20296",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0541",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16",
-        abi_id: "i0541",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E4m3,
-            b_element: GeneratedSparseMmaElement::E2m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20287",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0542",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16",
-        abi_id: "i0542",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E4m3,
-            b_element: GeneratedSparseMmaElement::E3m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20278",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0543",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16",
-        abi_id: "i0543",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E4m3,
-            b_element: GeneratedSparseMmaElement::E4m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20258",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0544",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16",
-        abi_id: "i0544",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E4m3,
-            b_element: GeneratedSparseMmaElement::E5m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20269",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0545",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16",
-        abi_id: "i0545",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E5m2,
-            b_element: GeneratedSparseMmaElement::E2m1,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20337",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0546",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16",
-        abi_id: "i0546",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E5m2,
-            b_element: GeneratedSparseMmaElement::E2m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20329",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0547",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16",
-        abi_id: "i0547",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E5m2,
-            b_element: GeneratedSparseMmaElement::E3m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20321",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0548",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16",
-        abi_id: "i0548",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E5m2,
-            b_element: GeneratedSparseMmaElement::E4m3,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20305",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0549",
-        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16",
-        abi_id: "i0549",
-        dialect_op: "nvvm.sparse_mma",
-        variant: GeneratedIntrinsicVariant::SparseMma {
-            shape: GeneratedSparseMmaShape::M16n8k64,
-            accumulator: GeneratedSparseMmaAccumulator::F16,
-            a_element: GeneratedSparseMmaElement::E5m2,
-            b_element: GeneratedSparseMmaElement::E5m2,
-            a_layout: GeneratedSparseMmaLayout::Row,
-            b_layout: GeneratedSparseMmaLayout::Col,
-            overflow: GeneratedSparseMmaOverflow::NotApplicable,
-            metadata: GeneratedSparseMmaMetadata::Ordered,
-            selector: GeneratedSparseMmaSelector::ImmediateZero,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_20313",
-            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0550",
-        id: "min_ftz_f16x2",
-        abi_id: "i0550",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_ftz_f16x2",
-            asm: "min.ftz.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0551",
-        id: "min_ftz_nan_f16x2",
-        abi_id: "i0551",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_ftz_NaN_f16x2",
-            asm: "min.ftz.NaN.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0552",
-        id: "min_ftz_nan_xorsign_abs_f32",
-        abi_id: "i0552",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F32,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_FTZ_NAN_XORSIGN_ABS_F",
-            asm: "min.ftz.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0553",
-        id: "min_ftz_nan_xorsign_abs_f16x2",
-        abi_id: "i0553",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_ftz_NaN_xorsign_abs_f16x2",
-            asm: "min.ftz.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0554",
-        id: "min_ftz_xorsign_abs_f32",
-        abi_id: "i0554",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F32,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_FTZ_XORSIGN_ABS_F",
-            asm: "min.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0555",
-        id: "min_ftz_xorsign_abs_f16x2",
-        abi_id: "i0555",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_ftz_xorsign_abs_f16x2",
-            asm: "min.ftz.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0556",
-        id: "min_nan_bf16x2",
-        abi_id: "i0556",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16x2,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_NaN_bf16x2",
-            asm: "min.NaN.bf16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0557",
-        id: "min_nan_f16x2",
-        abi_id: "i0557",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_NaN_f16x2",
-            asm: "min.NaN.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0558",
-        id: "min_nan_xorsign_abs_bf16x2",
-        abi_id: "i0558",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16x2,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_bf16x2",
-            asm: "min.NaN.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0559",
-        id: "min_nan_xorsign_abs_f32",
-        abi_id: "i0559",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F32,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_NAN_XORSIGN_ABS_F",
-            asm: "min.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0560",
-        id: "min_nan_xorsign_abs_f16x2",
-        abi_id: "i0560",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_f16x2",
-            asm: "min.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0561",
-        id: "min_xorsign_abs_bf16x2",
-        abi_id: "i0561",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16x2,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_xorsign_abs_bf16x2",
-            asm: "min.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0562",
-        id: "min_xorsign_abs_f32",
-        abi_id: "i0562",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F32,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_XORSIGN_ABS_F",
-            asm: "min.xorsign.abs.f32 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0563",
-        id: "min_xorsign_abs_f16x2",
-        abi_id: "i0563",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_xorsign_abs_f16x2",
-            asm: "min.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0564",
-        id: "max_ftz_f16x2",
-        abi_id: "i0564",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_ftz_f16x2",
-            asm: "max.ftz.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0565",
-        id: "max_ftz_nan_f16x2",
-        abi_id: "i0565",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_ftz_NaN_f16x2",
-            asm: "max.ftz.NaN.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0566",
-        id: "max_ftz_nan_xorsign_abs_f32",
-        abi_id: "i0566",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F32,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAX_FTZ_NAN_XORSIGN_ABS_F",
-            asm: "max.ftz.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0567",
-        id: "max_ftz_nan_xorsign_abs_f16x2",
-        abi_id: "i0567",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_ftz_NaN_xorsign_abs_f16x2",
-            asm: "max.ftz.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0568",
-        id: "max_ftz_xorsign_abs_f32",
-        abi_id: "i0568",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F32,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAX_FTZ_XORSIGN_ABS_F",
-            asm: "max.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0569",
-        id: "max_ftz_xorsign_abs_f16x2",
-        abi_id: "i0569",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_ftz_xorsign_abs_f16x2",
-            asm: "max.ftz.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0570",
-        id: "max_nan_bf16x2",
-        abi_id: "i0570",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16x2,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_NaN_bf16x2",
-            asm: "max.NaN.bf16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0571",
-        id: "max_nan_f16x2",
-        abi_id: "i0571",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_NaN_f16x2",
-            asm: "max.NaN.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0572",
-        id: "max_nan_xorsign_abs_bf16x2",
-        abi_id: "i0572",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16x2,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_bf16x2",
-            asm: "max.NaN.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0573",
-        id: "max_nan_xorsign_abs_f32",
-        abi_id: "i0573",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F32,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAX_NAN_XORSIGN_ABS_F",
-            asm: "max.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0574",
-        id: "max_nan_xorsign_abs_f16x2",
-        abi_id: "i0574",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_f16x2",
-            asm: "max.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0575",
-        id: "max_xorsign_abs_bf16x2",
-        abi_id: "i0575",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16x2,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_xorsign_abs_bf16x2",
-            asm: "max.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0576",
-        id: "max_xorsign_abs_f32",
-        abi_id: "i0576",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F32,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAX_XORSIGN_ABS_F",
-            asm: "max.xorsign.abs.f32 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0577",
-        id: "max_xorsign_abs_f16x2",
-        abi_id: "i0577",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16x2,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_xorsign_abs_f16x2",
-            asm: "max.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0578",
-        id: "tcgen05_cp_128x128b_b4x16_p64",
-        abi_id: "i0578",
-        dialect_op: "nvvm.tcgen05_cp_128x128b_b4x16_p64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x128bb4x16_p64_cg1",
-            asm: "tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0579",
-        id: "tcgen05_cp_128x128b_b4x16_p64_cg2",
-        abi_id: "i0579",
-        dialect_op: "nvvm.tcgen05_cp_128x128b_b4x16_p64_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x128bb4x16_p64_cg2",
-            asm: "tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0580",
-        id: "tcgen05_cp_128x128b_b6x16_p32",
-        abi_id: "i0580",
-        dialect_op: "nvvm.tcgen05_cp_128x128b_b6x16_p32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x128bb6x16_p32_cg1",
-            asm: "tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0581",
-        id: "tcgen05_cp_128x128b_b6x16_p32_cg2",
-        abi_id: "i0581",
-        dialect_op: "nvvm.tcgen05_cp_128x128b_b6x16_p32_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x128bb6x16_p32_cg2",
-            asm: "tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0582",
-        id: "tcgen05_cp_128x128b",
-        abi_id: "i0582",
-        dialect_op: "nvvm.tcgen05_cp_128x128b",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x128b_cg1",
-            asm: "tcgen05.cp.cta_group::1.128x128b \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0583",
-        id: "tcgen05_cp_128x128b_cg2",
-        abi_id: "i0583",
-        dialect_op: "nvvm.tcgen05_cp_128x128b_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x128b_cg2",
-            asm: "tcgen05.cp.cta_group::2.128x128b \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0584",
-        id: "tcgen05_cp_128x256b_b4x16_p64",
-        abi_id: "i0584",
-        dialect_op: "nvvm.tcgen05_cp_128x256b_b4x16_p64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x256bb4x16_p64_cg1",
-            asm: "tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0585",
-        id: "tcgen05_cp_128x256b_b4x16_p64_cg2",
-        abi_id: "i0585",
-        dialect_op: "nvvm.tcgen05_cp_128x256b_b4x16_p64_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x256bb4x16_p64_cg2",
-            asm: "tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0586",
-        id: "tcgen05_cp_128x256b_b6x16_p32",
-        abi_id: "i0586",
-        dialect_op: "nvvm.tcgen05_cp_128x256b_b6x16_p32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x256bb6x16_p32_cg1",
-            asm: "tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0587",
-        id: "tcgen05_cp_128x256b_b6x16_p32_cg2",
-        abi_id: "i0587",
-        dialect_op: "nvvm.tcgen05_cp_128x256b_b6x16_p32_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_128x256bb6x16_p32_cg2",
-            asm: "tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0588",
-        id: "tcgen05_cp_32x128b_warpx4_b4x16_p64",
-        abi_id: "i0588",
-        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4_b4x16_p64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_32x128b4x16_p64_cg1",
-            asm: "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0589",
-        id: "tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2",
-        abi_id: "i0589",
-        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_32x128b4x16_p64_cg2",
-            asm: "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0590",
-        id: "tcgen05_cp_32x128b_warpx4_b6x16_p32",
-        abi_id: "i0590",
-        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4_b6x16_p32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_32x128b6x16_p32_cg1",
-            asm: "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0591",
-        id: "tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2",
-        abi_id: "i0591",
-        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_32x128b6x16_p32_cg2",
-            asm: "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0592",
-        id: "tcgen05_cp_32x128b_warpx4",
-        abi_id: "i0592",
-        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_32x128_cg1",
-            asm: "tcgen05.cp.cta_group::1.32x128b.warpx4 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0593",
-        id: "tcgen05_cp_32x128b_warpx4_cg2",
-        abi_id: "i0593",
-        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_32x128_cg2",
-            asm: "tcgen05.cp.cta_group::2.32x128b.warpx4 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0594",
-        id: "tcgen05_cp_4x256b_b4x16_p64",
-        abi_id: "i0594",
-        dialect_op: "nvvm.tcgen05_cp_4x256b_b4x16_p64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_4x256bb4x16_p64_cg1",
-            asm: "tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0595",
-        id: "tcgen05_cp_4x256b_b4x16_p64_cg2",
-        abi_id: "i0595",
-        dialect_op: "nvvm.tcgen05_cp_4x256b_b4x16_p64_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_4x256bb4x16_p64_cg2",
-            asm: "tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0596",
-        id: "tcgen05_cp_4x256b_b6x16_p32",
-        abi_id: "i0596",
-        dialect_op: "nvvm.tcgen05_cp_4x256b_b6x16_p32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_4x256bb6x16_p32_cg1",
-            asm: "tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0597",
-        id: "tcgen05_cp_4x256b_b6x16_p32_cg2",
-        abi_id: "i0597",
-        dialect_op: "nvvm.tcgen05_cp_4x256b_b6x16_p32_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_4x256bb6x16_p32_cg2",
-            asm: "tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0598",
-        id: "tcgen05_cp_4x256b",
-        abi_id: "i0598",
-        dialect_op: "nvvm.tcgen05_cp_4x256b",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_4x256b_cg1",
-            asm: "tcgen05.cp.cta_group::1.4x256b \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0599",
-        id: "tcgen05_cp_4x256b_cg2",
-        abi_id: "i0599",
-        dialect_op: "nvvm.tcgen05_cp_4x256b_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_4x256b_cg2",
-            asm: "tcgen05.cp.cta_group::2.4x256b \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0600",
-        id: "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64",
-        abi_id: "i0600",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_2b4x16_p64_cg1",
-            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0601",
-        id: "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2",
-        abi_id: "i0601",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_2b4x16_p64_cg2",
-            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0602",
-        id: "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32",
-        abi_id: "i0602",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_2b6x16_p32_cg1",
-            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0603",
-        id: "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2",
-        abi_id: "i0603",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_2b6x16_p32_cg2",
-            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0604",
-        id: "tcgen05_cp_64x128b_warpx2_01_23",
-        abi_id: "i0604",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_2_cg1",
-            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0605",
-        id: "tcgen05_cp_64x128b_warpx2_01_23_cg2",
-        abi_id: "i0605",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_2_cg2",
-            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0606",
-        id: "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64",
-        abi_id: "i0606",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_1b4x16_p64_cg1",
-            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0607",
-        id: "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2",
-        abi_id: "i0607",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_1b4x16_p64_cg2",
-            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0608",
-        id: "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32",
-        abi_id: "i0608",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_1b6x16_p32_cg1",
-            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0609",
-        id: "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2",
-        abi_id: "i0609",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_1b6x16_p32_cg2",
-            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0610",
-        id: "tcgen05_cp_64x128b_warpx2_02_13",
-        abi_id: "i0610",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_1_cg1",
-            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0611",
-        id: "tcgen05_cp_64x128b_warpx2_02_13_cg2",
-        abi_id: "i0611",
-        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_CP_64x128_1_cg2",
-            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 \t[$tmem_addr], $sdesc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0612",
-        id: "tcgen05_ld_16x64b_x1_raw",
-        abi_id: "i0612",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x1_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0613",
-        id: "tcgen05_ld_16x64b_x1_pack16",
-        abi_id: "i0613",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x1_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0614",
-        id: "tcgen05_ld_16x64b_x2_raw",
-        abi_id: "i0614",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x2_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0615",
-        id: "tcgen05_ld_16x64b_x2_pack16",
-        abi_id: "i0615",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x2_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0616",
-        id: "tcgen05_ld_16x64b_x4_raw",
-        abi_id: "i0616",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x4_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0617",
-        id: "tcgen05_ld_16x64b_x4_pack16",
-        abi_id: "i0617",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x4_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0618",
-        id: "tcgen05_ld_16x64b_x8_raw",
-        abi_id: "i0618",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x8_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0619",
-        id: "tcgen05_ld_16x64b_x8_pack16",
-        abi_id: "i0619",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x8_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0620",
-        id: "tcgen05_ld_16x64b_x16_raw",
-        abi_id: "i0620",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x16_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0621",
-        id: "tcgen05_ld_16x64b_x16_pack16",
-        abi_id: "i0621",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x16_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0622",
-        id: "tcgen05_ld_16x64b_x32_raw",
-        abi_id: "i0622",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x32_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0623",
-        id: "tcgen05_ld_16x64b_x32_pack16",
-        abi_id: "i0623",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x32_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0624",
-        id: "tcgen05_ld_16x64b_x64_raw",
-        abi_id: "i0624",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x64_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0625",
-        id: "tcgen05_ld_16x64b_x64_pack16",
-        abi_id: "i0625",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x64_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0626",
-        id: "tcgen05_ld_16x64b_x128_raw",
-        abi_id: "i0626",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x128_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0627",
-        id: "tcgen05_ld_16x64b_x128_pack16",
-        abi_id: "i0627",
-        dialect_op: "nvvm.tcgen05_ld_16x64b_x128_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0628",
-        id: "tcgen05_ld_16x128b_x1_raw",
-        abi_id: "i0628",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x1_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0629",
-        id: "tcgen05_ld_16x128b_x1_pack16",
-        abi_id: "i0629",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x1_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0630",
-        id: "tcgen05_ld_16x128b_x2_raw",
-        abi_id: "i0630",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x2_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0631",
-        id: "tcgen05_ld_16x128b_x2_pack16",
-        abi_id: "i0631",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x2_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0632",
-        id: "tcgen05_ld_16x128b_x4_raw",
-        abi_id: "i0632",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x4_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0633",
-        id: "tcgen05_ld_16x128b_x4_pack16",
-        abi_id: "i0633",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x4_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0634",
-        id: "tcgen05_ld_16x128b_x8_raw",
-        abi_id: "i0634",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x8_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0635",
-        id: "tcgen05_ld_16x128b_x8_pack16",
-        abi_id: "i0635",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x8_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0636",
-        id: "tcgen05_ld_16x128b_x16_raw",
-        abi_id: "i0636",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x16_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0637",
-        id: "tcgen05_ld_16x128b_x16_pack16",
-        abi_id: "i0637",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x16_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0638",
-        id: "tcgen05_ld_16x128b_x32_raw",
-        abi_id: "i0638",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x32_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0639",
-        id: "tcgen05_ld_16x128b_x32_pack16",
-        abi_id: "i0639",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x32_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0640",
-        id: "tcgen05_ld_16x128b_x64_raw",
-        abi_id: "i0640",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x64_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0641",
-        id: "tcgen05_ld_16x128b_x64_pack16",
-        abi_id: "i0641",
-        dialect_op: "nvvm.tcgen05_ld_16x128b_x64_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0642",
-        id: "tcgen05_ld_16x256b_x1_raw",
-        abi_id: "i0642",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x1_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0643",
-        id: "tcgen05_ld_16x256b_x1_pack16",
-        abi_id: "i0643",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x1_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0644",
-        id: "tcgen05_ld_16x256b_x2_raw",
-        abi_id: "i0644",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x2_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0645",
-        id: "tcgen05_ld_16x256b_x2_pack16",
-        abi_id: "i0645",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x2_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0646",
-        id: "tcgen05_ld_16x256b_x4_raw",
-        abi_id: "i0646",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x4_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0647",
-        id: "tcgen05_ld_16x256b_x4_pack16",
-        abi_id: "i0647",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x4_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0648",
-        id: "tcgen05_ld_16x256b_x8_raw",
-        abi_id: "i0648",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x8_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0649",
-        id: "tcgen05_ld_16x256b_x8_pack16",
-        abi_id: "i0649",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x8_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0650",
-        id: "tcgen05_ld_16x256b_x16_raw",
-        abi_id: "i0650",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x16_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0651",
-        id: "tcgen05_ld_16x256b_x16_pack16",
-        abi_id: "i0651",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x16_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0652",
-        id: "tcgen05_ld_16x256b_x32_raw",
-        abi_id: "i0652",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x32_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0653",
-        id: "tcgen05_ld_16x256b_x32_pack16",
-        abi_id: "i0653",
-        dialect_op: "nvvm.tcgen05_ld_16x256b_x32_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0654",
-        id: "tcgen05_ld_32x32b_x1_raw",
-        abi_id: "i0654",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x1_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0655",
-        id: "tcgen05_ld_32x32b_x1_pack16",
-        abi_id: "i0655",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x1_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0656",
-        id: "tcgen05_ld_32x32b_x2_raw",
-        abi_id: "i0656",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x2_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0657",
-        id: "tcgen05_ld_32x32b_x2_pack16",
-        abi_id: "i0657",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x2_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0658",
-        id: "tcgen05_ld_32x32b_x4_raw",
-        abi_id: "i0658",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x4_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0659",
-        id: "tcgen05_ld_32x32b_x4_pack16",
-        abi_id: "i0659",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x4_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0660",
-        id: "tcgen05_ld_32x32b_x8_raw",
-        abi_id: "i0660",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x8_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0661",
-        id: "tcgen05_ld_32x32b_x8_pack16",
-        abi_id: "i0661",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x8_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0662",
-        id: "tcgen05_ld_32x32b_x16_raw",
-        abi_id: "i0662",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x16_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0663",
-        id: "tcgen05_ld_32x32b_x16_pack16",
-        abi_id: "i0663",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x16_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0664",
-        id: "tcgen05_ld_32x32b_x32_raw",
-        abi_id: "i0664",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x32_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0665",
-        id: "tcgen05_ld_32x32b_x32_pack16",
-        abi_id: "i0665",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x32_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0666",
-        id: "tcgen05_ld_32x32b_x64_raw",
-        abi_id: "i0666",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x64_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0667",
-        id: "tcgen05_ld_32x32b_x64_pack16",
-        abi_id: "i0667",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x64_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0668",
-        id: "tcgen05_ld_32x32b_x128_raw",
-        abi_id: "i0668",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x128_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0669",
-        id: "tcgen05_ld_32x32b_x128_pack16",
-        abi_id: "i0669",
-        dialect_op: "nvvm.tcgen05_ld_32x32b_x128_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0670",
-        id: "tcgen05_st_16x64b_x1_raw",
-        abi_id: "i0670",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x1_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0671",
-        id: "tcgen05_st_16x64b_x1_unpack16",
-        abi_id: "i0671",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x1_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0672",
-        id: "tcgen05_st_16x64b_x2_raw",
-        abi_id: "i0672",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x2_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0673",
-        id: "tcgen05_st_16x64b_x2_unpack16",
-        abi_id: "i0673",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x2_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0674",
-        id: "tcgen05_st_16x64b_x4_raw",
-        abi_id: "i0674",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x4_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0675",
-        id: "tcgen05_st_16x64b_x4_unpack16",
-        abi_id: "i0675",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x4_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0676",
-        id: "tcgen05_st_16x64b_x8_raw",
-        abi_id: "i0676",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x8_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0677",
-        id: "tcgen05_st_16x64b_x8_unpack16",
-        abi_id: "i0677",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x8_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0678",
-        id: "tcgen05_st_16x64b_x16_raw",
-        abi_id: "i0678",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x16_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0679",
-        id: "tcgen05_st_16x64b_x16_unpack16",
-        abi_id: "i0679",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x16_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0680",
-        id: "tcgen05_st_16x64b_x32_raw",
-        abi_id: "i0680",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x32_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0681",
-        id: "tcgen05_st_16x64b_x32_unpack16",
-        abi_id: "i0681",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x32_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0682",
-        id: "tcgen05_st_16x64b_x64_raw",
-        abi_id: "i0682",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x64_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0683",
-        id: "tcgen05_st_16x64b_x64_unpack16",
-        abi_id: "i0683",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x64_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0684",
-        id: "tcgen05_st_16x64b_x128_raw",
-        abi_id: "i0684",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x128_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0685",
-        id: "tcgen05_st_16x64b_x128_unpack16",
-        abi_id: "i0685",
-        dialect_op: "nvvm.tcgen05_st_16x64b_x128_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0686",
-        id: "tcgen05_st_16x128b_x1_raw",
-        abi_id: "i0686",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x1_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0687",
-        id: "tcgen05_st_16x128b_x1_unpack16",
-        abi_id: "i0687",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x1_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0688",
-        id: "tcgen05_st_16x128b_x2_raw",
-        abi_id: "i0688",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x2_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0689",
-        id: "tcgen05_st_16x128b_x2_unpack16",
-        abi_id: "i0689",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x2_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0690",
-        id: "tcgen05_st_16x128b_x4_raw",
-        abi_id: "i0690",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x4_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0691",
-        id: "tcgen05_st_16x128b_x4_unpack16",
-        abi_id: "i0691",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x4_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0692",
-        id: "tcgen05_st_16x128b_x8_raw",
-        abi_id: "i0692",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x8_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0693",
-        id: "tcgen05_st_16x128b_x8_unpack16",
-        abi_id: "i0693",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x8_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0694",
-        id: "tcgen05_st_16x128b_x16_raw",
-        abi_id: "i0694",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x16_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0695",
-        id: "tcgen05_st_16x128b_x16_unpack16",
-        abi_id: "i0695",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x16_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0696",
-        id: "tcgen05_st_16x128b_x32_raw",
-        abi_id: "i0696",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x32_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0697",
-        id: "tcgen05_st_16x128b_x32_unpack16",
-        abi_id: "i0697",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x32_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0698",
-        id: "tcgen05_st_16x128b_x64_raw",
-        abi_id: "i0698",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x64_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0699",
-        id: "tcgen05_st_16x128b_x64_unpack16",
-        abi_id: "i0699",
-        dialect_op: "nvvm.tcgen05_st_16x128b_x64_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0700",
-        id: "tcgen05_st_16x256b_x1_raw",
-        abi_id: "i0700",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x1_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0701",
-        id: "tcgen05_st_16x256b_x1_unpack16",
-        abi_id: "i0701",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x1_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0702",
-        id: "tcgen05_st_16x256b_x2_raw",
-        abi_id: "i0702",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x2_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0703",
-        id: "tcgen05_st_16x256b_x2_unpack16",
-        abi_id: "i0703",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x2_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0704",
-        id: "tcgen05_st_16x256b_x4_raw",
-        abi_id: "i0704",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x4_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0705",
-        id: "tcgen05_st_16x256b_x4_unpack16",
-        abi_id: "i0705",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x4_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0706",
-        id: "tcgen05_st_16x256b_x8_raw",
-        abi_id: "i0706",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x8_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0707",
-        id: "tcgen05_st_16x256b_x8_unpack16",
-        abi_id: "i0707",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x8_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0708",
-        id: "tcgen05_st_16x256b_x16_raw",
-        abi_id: "i0708",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x16_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0709",
-        id: "tcgen05_st_16x256b_x16_unpack16",
-        abi_id: "i0709",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x16_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0710",
-        id: "tcgen05_st_16x256b_x32_raw",
-        abi_id: "i0710",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x32_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0711",
-        id: "tcgen05_st_16x256b_x32_unpack16",
-        abi_id: "i0711",
-        dialect_op: "nvvm.tcgen05_st_16x256b_x32_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0712",
-        id: "tcgen05_st_32x32b_x1_raw",
-        abi_id: "i0712",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x1_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0713",
-        id: "tcgen05_st_32x32b_x1_unpack16",
-        abi_id: "i0713",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x1_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0714",
-        id: "tcgen05_st_32x32b_x2_raw",
-        abi_id: "i0714",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x2_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0715",
-        id: "tcgen05_st_32x32b_x2_unpack16",
-        abi_id: "i0715",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x2_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0716",
-        id: "tcgen05_st_32x32b_x4_raw",
-        abi_id: "i0716",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x4_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0717",
-        id: "tcgen05_st_32x32b_x4_unpack16",
-        abi_id: "i0717",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x4_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0718",
-        id: "tcgen05_st_32x32b_x8_raw",
-        abi_id: "i0718",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x8_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0719",
-        id: "tcgen05_st_32x32b_x8_unpack16",
-        abi_id: "i0719",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x8_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0720",
-        id: "tcgen05_st_32x32b_x16_raw",
-        abi_id: "i0720",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x16_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0721",
-        id: "tcgen05_st_32x32b_x16_unpack16",
-        abi_id: "i0721",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x16_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0722",
-        id: "tcgen05_st_32x32b_x32_raw",
-        abi_id: "i0722",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x32_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0723",
-        id: "tcgen05_st_32x32b_x32_unpack16",
-        abi_id: "i0723",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x32_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0724",
-        id: "tcgen05_st_32x32b_x64_raw",
-        abi_id: "i0724",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x64_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0725",
-        id: "tcgen05_st_32x32b_x64_unpack16",
-        abi_id: "i0725",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x64_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0726",
-        id: "tcgen05_st_32x32b_x128_raw",
-        abi_id: "i0726",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x128_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0727",
-        id: "tcgen05_st_32x32b_x128_unpack16",
-        abi_id: "i0727",
-        dialect_op: "nvvm.tcgen05_st_32x32b_x128_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0728",
-        id: "tcgen05_ld_16x32bx2_x1_raw",
-        abi_id: "i0728",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x1_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0729",
-        id: "tcgen05_ld_16x32bx2_x1_pack16",
-        abi_id: "i0729",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x1_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0730",
-        id: "tcgen05_ld_16x32bx2_x2_raw",
-        abi_id: "i0730",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x2_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0731",
-        id: "tcgen05_ld_16x32bx2_x2_pack16",
-        abi_id: "i0731",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x2_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0732",
-        id: "tcgen05_ld_16x32bx2_x4_raw",
-        abi_id: "i0732",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x4_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0733",
-        id: "tcgen05_ld_16x32bx2_x4_pack16",
-        abi_id: "i0733",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x4_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0734",
-        id: "tcgen05_ld_16x32bx2_x8_raw",
-        abi_id: "i0734",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x8_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0735",
-        id: "tcgen05_ld_16x32bx2_x8_pack16",
-        abi_id: "i0735",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x8_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0736",
-        id: "tcgen05_ld_16x32bx2_x16_raw",
-        abi_id: "i0736",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x16_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0737",
-        id: "tcgen05_ld_16x32bx2_x16_pack16",
-        abi_id: "i0737",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x16_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0738",
-        id: "tcgen05_ld_16x32bx2_x32_raw",
-        abi_id: "i0738",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x32_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0739",
-        id: "tcgen05_ld_16x32bx2_x32_pack16",
-        abi_id: "i0739",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x32_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0740",
-        id: "tcgen05_ld_16x32bx2_x64_raw",
-        abi_id: "i0740",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x64_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0741",
-        id: "tcgen05_ld_16x32bx2_x64_pack16",
-        abi_id: "i0741",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x64_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0742",
-        id: "tcgen05_ld_16x32bx2_x128_raw",
-        abi_id: "i0742",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x128_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0743",
-        id: "tcgen05_ld_16x32bx2_x128_pack16",
-        abi_id: "i0743",
-        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x128_pack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0744",
-        id: "tcgen05_st_16x32bx2_x1_raw",
-        abi_id: "i0744",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x1_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0745",
-        id: "tcgen05_st_16x32bx2_x1_unpack16",
-        abi_id: "i0745",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x1_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0746",
-        id: "tcgen05_st_16x32bx2_x2_raw",
-        abi_id: "i0746",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x2_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0747",
-        id: "tcgen05_st_16x32bx2_x2_unpack16",
-        abi_id: "i0747",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x2_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0748",
-        id: "tcgen05_st_16x32bx2_x4_raw",
-        abi_id: "i0748",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x4_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0749",
-        id: "tcgen05_st_16x32bx2_x4_unpack16",
-        abi_id: "i0749",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x4_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0750",
-        id: "tcgen05_st_16x32bx2_x8_raw",
-        abi_id: "i0750",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x8_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0751",
-        id: "tcgen05_st_16x32bx2_x8_unpack16",
-        abi_id: "i0751",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x8_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0752",
-        id: "tcgen05_st_16x32bx2_x16_raw",
-        abi_id: "i0752",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x16_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0753",
-        id: "tcgen05_st_16x32bx2_x16_unpack16",
-        abi_id: "i0753",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x16_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0754",
-        id: "tcgen05_st_16x32bx2_x32_raw",
-        abi_id: "i0754",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x32_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0755",
-        id: "tcgen05_st_16x32bx2_x32_unpack16",
-        abi_id: "i0755",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x32_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0756",
-        id: "tcgen05_st_16x32bx2_x64_raw",
-        abi_id: "i0756",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x64_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0757",
-        id: "tcgen05_st_16x32bx2_x64_unpack16",
-        abi_id: "i0757",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x64_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0758",
-        id: "tcgen05_st_16x32bx2_x128_raw",
-        abi_id: "i0758",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x128_raw",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0759",
-        id: "tcgen05_st_16x32bx2_x128_unpack16",
-        abi_id: "i0759",
-        dialect_op: "nvvm.tcgen05_st_16x32bx2_x128_unpack16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0760",
-        id: "tcgen05_commit_multicast",
-        abi_id: "i0760",
-        dialect_op: "nvvm.tcgen05_commit_multicast",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_COMMIT_S64_CG1_MC",
-            asm: "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0761",
-        id: "tcgen05_shift_down",
-        abi_id: "i0761",
-        dialect_op: "nvvm.tcgen05_shift_down",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_SHIFT_CG1",
-            asm: "tcgen05.shift.cta_group::1.down \t[$tmem_addr];",
-            predicates: &["Subtarget->hasTcgen05ShiftSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0762",
-        id: "tcgen05_shift_down_cg2",
-        abi_id: "i0762",
-        dialect_op: "nvvm.tcgen05_shift_down_cg2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TCGEN05_SHIFT_CG2",
-            asm: "tcgen05.shift.cta_group::2.down \t[$tmem_addr];",
-            predicates: &["Subtarget->hasTcgen05ShiftSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0763",
-        id: "tcgen05_mma_shared",
-        abi_id: "i0763",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::Shared,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22502",
-                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22504",
-                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22506",
-                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22508",
-                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22510",
-                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22512",
-                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22514",
-                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22516",
-                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22518",
-                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22520",
-                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22522",
-                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22524",
-                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22526",
-                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22528",
-                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22530",
-                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22532",
-                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22534",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22535",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22536",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22537",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22538",
-                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22539",
-                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22540",
-                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22541",
-                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22542",
-                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22543",
-                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22544",
-                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22545",
-                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22546",
-                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22547",
-                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22548",
-                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22549",
-                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0764",
-        id: "tcgen05_mma_tensor",
-        abi_id: "i0764",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::Tensor,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22406",
-                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22410",
-                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22414",
-                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22418",
-                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22422",
-                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22426",
-                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22430",
-                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22434",
-                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22438",
-                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22442",
-                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22446",
-                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22450",
-                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22454",
-                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22458",
-                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22462",
-                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22466",
-                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22470",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22472",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22474",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22476",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22478",
-                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22480",
-                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22482",
-                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22484",
-                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22486",
-                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22488",
-                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22490",
-                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22492",
-                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22494",
-                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22496",
-                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22498",
-                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22500",
-                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ArgInfo<arg5>",
-                "ArgInfo<arg6>",
-                "ArgInfo<arg7>",
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0765",
-        id: "tcgen05_mma_tensor_ashift",
-        abi_id: "i0765",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::TensorAshift,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22407",
-                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22411",
-                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22423",
-                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22427",
-                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22439",
-                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22443",
-                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22455",
-                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22459",
-                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22471",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22473",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22479",
-                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22481",
-                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22487",
-                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22489",
-                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22495",
-                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22497",
-                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,2>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0766",
-        id: "tcgen05_mma_sp_shared",
-        abi_id: "i0766",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::SpShared,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22646",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22648",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22650",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22652",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22654",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22656",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22658",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22660",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22662",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22664",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22666",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22668",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22670",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22672",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22674",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22676",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22678",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22679",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22680",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22681",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22682",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22683",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22684",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22685",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22686",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22687",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22688",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22689",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22690",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22691",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22692",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22693",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,1,3>",
-                "Range<arg8,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0767",
-        id: "tcgen05_mma_sp_tensor",
-        abi_id: "i0767",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::SpTensor,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22550",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22554",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22558",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22562",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22566",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22570",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22574",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22578",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22582",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22586",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22590",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22594",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22598",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22602",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22606",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22610",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22614",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22616",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22618",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22620",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22622",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22624",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22626",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22628",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22630",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22632",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22634",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22636",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22638",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22640",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22642",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22644",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,1,3>",
-                "Range<arg8,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0768",
-        id: "tcgen05_mma_sp_tensor_ashift",
-        abi_id: "i0768",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::SpTensorAshift,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22551",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22555",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22567",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22571",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22583",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22587",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22599",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22603",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22615",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22617",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22623",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22625",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22631",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22633",
-                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22639",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_22641",
-                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,1,3>",
-                "Range<arg8,0,2>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0769",
-        id: "tcgen05_mma_ws_shared",
-        abi_id: "i0769",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsShared,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23232",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23234",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23236",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23238",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23240",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23242",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23244",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23246",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23248",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23250",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23252",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23254",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23256",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23258",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23260",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23262",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23264",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23266",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23268",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23270",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23272",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23274",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23276",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23278",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23280",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23282",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23284",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23286",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23288",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23290",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23292",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23294",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23296",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23298",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23300",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23302",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23304",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23306",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23308",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23310",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23312",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23314",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23316",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23318",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23320",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23322",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23324",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23326",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23328",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23330",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23332",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23334",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23336",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23338",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23340",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23342",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23344",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23346",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23348",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23350",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23352",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23354",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23356",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23358",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0770",
-        id: "tcgen05_mma_ws_shared_zero_col_mask",
-        abi_id: "i0770",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsSharedZeroColMask,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23233",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23235",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23237",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23239",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23241",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23243",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23245",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23247",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23249",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23251",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23253",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23255",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23257",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23259",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23261",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23263",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23265",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23267",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23269",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23271",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23273",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23275",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23277",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23279",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23281",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23283",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23285",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23287",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23289",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23291",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23293",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23295",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23297",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23299",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23301",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23303",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23305",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23307",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23309",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23311",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23313",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23315",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23317",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23319",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23321",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23323",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23325",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23327",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23329",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23331",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23333",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23335",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23337",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23339",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23341",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23343",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23345",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23347",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23349",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23351",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23353",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23355",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23357",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23359",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0771",
-        id: "tcgen05_mma_ws_sp_shared",
-        abi_id: "i0771",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsSpShared,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23488",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23490",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23492",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23494",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23496",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23498",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23500",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23502",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23504",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23506",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23508",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23510",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23512",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23514",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23516",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23518",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23520",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23522",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23524",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23526",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23528",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23530",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23532",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23534",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23536",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23538",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23540",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23542",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23544",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23546",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23548",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23550",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23552",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23554",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23556",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23558",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23560",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23562",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23564",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23566",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23568",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23570",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23572",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23574",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23576",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23578",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23580",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23582",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23584",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23586",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23588",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23590",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23592",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23594",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23596",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23598",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23600",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23602",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23604",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23606",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23608",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23610",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23612",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23614",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0772",
-        id: "tcgen05_mma_ws_sp_shared_zero_col_mask",
-        abi_id: "i0772",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsSpSharedZeroColMask,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23489",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23491",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23493",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23495",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23497",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23499",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23501",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23503",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23505",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23507",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23509",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23511",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23513",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23515",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23517",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23519",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23521",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23523",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23525",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23527",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23529",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23531",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23533",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23535",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23537",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23539",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23541",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23543",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23545",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23547",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23549",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23551",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23553",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23555",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23557",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23559",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23561",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23563",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23565",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23567",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23569",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23571",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23573",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23575",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23577",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23579",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23581",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23583",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23585",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23587",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23589",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23591",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23593",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23595",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23597",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23599",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23601",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23603",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23605",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23607",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23609",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23611",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23613",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23615",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrArgMemOnly",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "Range<arg9,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0773",
-        id: "tcgen05_mma_ws_sp_tensor",
-        abi_id: "i0773",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsSpTensor,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23616",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23618",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23620",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23622",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23624",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23626",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23628",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23630",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23632",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23634",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23636",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23638",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23640",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23642",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23644",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23646",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23648",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23650",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23652",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23654",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23656",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23658",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23660",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23662",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23664",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23666",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23668",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23670",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23672",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23674",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23676",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23678",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23680",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23682",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23684",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23686",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23688",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23690",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23692",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23694",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23696",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23698",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23700",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23702",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23704",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23706",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23708",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23710",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23712",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23714",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23716",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23718",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23720",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23722",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23724",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23726",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23728",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23730",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23732",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23734",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23736",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23738",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23740",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23742",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0774",
-        id: "tcgen05_mma_ws_sp_tensor_zero_col_mask",
-        abi_id: "i0774",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsSpTensorZeroColMask,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23617",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23619",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23621",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23623",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23625",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23627",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23629",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23631",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23633",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23635",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23637",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23639",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23641",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23643",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23645",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23647",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23649",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23651",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23653",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23655",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23657",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23659",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23661",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23663",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23665",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23667",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23669",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23671",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23673",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23675",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23677",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23679",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23681",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23683",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23685",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23687",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23689",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23691",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23693",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23695",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23697",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23699",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23701",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23703",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23705",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23707",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23709",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23711",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23713",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23715",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23717",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23719",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23721",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23723",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23725",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23727",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23729",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23731",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23733",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23735",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23737",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23739",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23741",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23743",
-                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrArgMemOnly",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "Range<arg9,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0775",
-        id: "tcgen05_mma_ws_tensor",
-        abi_id: "i0775",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsTensor,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23360",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23362",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23364",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23366",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23368",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23370",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23372",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23374",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23376",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23378",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23380",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23382",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23384",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23386",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23388",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23390",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23392",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23394",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23396",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23398",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23400",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23402",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23404",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23406",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23408",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23410",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23412",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23414",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23416",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23418",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23420",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23422",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23424",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23426",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23428",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23430",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23432",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23434",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23436",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23438",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23440",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23442",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23444",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23446",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23448",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23450",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23452",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23454",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23456",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23458",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23460",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23462",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23464",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23466",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23468",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23470",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23472",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23474",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23476",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23478",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23480",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23482",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23484",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23486",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0776",
-        id: "tcgen05_mma_ws_tensor_zero_col_mask",
-        abi_id: "i0776",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsTensorZeroColMask,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f16",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "i8",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                        ],
-                    },
-                    GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "tf32",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    },
-                ],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            101,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f16",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "f8f6f4",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "i8",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                ],
-                            },
-                            GeneratedTargetContract {
-                                selectors: &[GeneratedTargetSelectorBinding {
-                                    name: "kind",
-                                    value: "tf32",
-                                }],
-                                alternatives: &[
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            100,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            103,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
-                                            110,
-                                        ),
-                                    },
-                                    GeneratedTargetAlternative {
-                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                    },
-                                ],
-                            },
-                        ],
-                    },
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23361",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23363",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23365",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23367",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23369",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23371",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23373",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23375",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23377",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23379",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23381",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23383",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23385",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23387",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23389",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23391",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23393",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23395",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23397",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23399",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23401",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23403",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23405",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23407",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23409",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23411",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23413",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23415",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23417",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23419",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23421",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23423",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23425",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23427",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23429",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23431",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23433",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23435",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23437",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23439",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23441",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23443",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23445",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23447",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23449",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23451",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23453",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23455",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23457",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23459",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23461",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23463",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23465",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23467",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23469",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23471",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23473",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23475",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23477",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23479",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23481",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23483",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23485",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "anonymous_23487",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0777",
-        id: "tcgen05_mma_ws_e4m3",
-        abi_id: "i0777",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsTensor,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[GeneratedTargetContract {
-                    selectors: &[GeneratedTargetSelectorBinding {
-                        name: "kind",
-                        value: "f8f6f4",
-                    }],
-                    alternatives: &[
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                        },
-                    ],
-                }],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_23424",
-            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0778",
-        id: "tcgen05_mma_ws_e5m2",
-        abi_id: "i0778",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsTensor,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[GeneratedTargetContract {
-                    selectors: &[GeneratedTargetSelectorBinding {
-                        name: "kind",
-                        value: "f8f6f4",
-                    }],
-                    alternatives: &[
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                        },
-                    ],
-                }],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_23424",
-            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0779",
-        id: "tcgen05_mma_ws_e2m3",
-        abi_id: "i0779",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsTensor,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[GeneratedTargetContract {
-                    selectors: &[GeneratedTargetSelectorBinding {
-                        name: "kind",
-                        value: "f8f6f4",
-                    }],
-                    alternatives: &[
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                        },
-                    ],
-                }],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_23424",
-            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0780",
-        id: "tcgen05_mma_ws_e3m2",
-        abi_id: "i0780",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsTensor,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[GeneratedTargetContract {
-                    selectors: &[GeneratedTargetSelectorBinding {
-                        name: "kind",
-                        value: "f8f6f4",
-                    }],
-                    alternatives: &[
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                        },
-                    ],
-                }],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_23424",
-            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0781",
-        id: "tcgen05_mma_ws_e2m1",
-        abi_id: "i0781",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::WsTensor,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[GeneratedTargetContract {
-                    selectors: &[GeneratedTargetSelectorBinding {
-                        name: "kind",
-                        value: "f8f6f4",
-                    }],
-                    alternatives: &[
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                        },
-                    ],
-                }],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_23424",
-            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0782",
-        id: "sin_approx_f32",
-        abi_id: "i0782",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0783",
-        id: "sin_approx_ftz_f32",
-        abi_id: "i0783",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0784",
-        id: "cos_approx_f32",
-        abi_id: "i0784",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0785",
-        id: "cos_approx_ftz_f32",
-        abi_id: "i0785",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0786",
-        id: "lg2_approx_f32",
-        abi_id: "i0786",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0787",
-        id: "lg2_approx_ftz_f32",
-        abi_id: "i0787",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0788",
-        id: "rcp_approx_ftz_f32",
-        abi_id: "i0788",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_APPROX_FTZ_F",
-            asm: "rcp.approx.ftz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0789",
-        id: "rcp_rn_f32",
-        abi_id: "i0789",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RN_F",
-            asm: "rcp.rn.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0790",
-        id: "rcp_rn_ftz_f32",
-        abi_id: "i0790",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RN_FTZ_F",
-            asm: "rcp.rn.ftz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0791",
-        id: "rcp_rz_f32",
-        abi_id: "i0791",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RZ_F",
-            asm: "rcp.rz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0792",
-        id: "rcp_rz_ftz_f32",
-        abi_id: "i0792",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RZ_FTZ_F",
-            asm: "rcp.rz.ftz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0793",
-        id: "rcp_rm_f32",
-        abi_id: "i0793",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RM_F",
-            asm: "rcp.rm.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0794",
-        id: "rcp_rm_ftz_f32",
-        abi_id: "i0794",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RM_FTZ_F",
-            asm: "rcp.rm.ftz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0795",
-        id: "rcp_rp_f32",
-        abi_id: "i0795",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RP_F",
-            asm: "rcp.rp.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0796",
-        id: "rcp_rp_ftz_f32",
-        abi_id: "i0796",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RP_FTZ_F",
-            asm: "rcp.rp.ftz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0797",
-        id: "rcp_approx_ftz_f64",
-        abi_id: "i0797",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_APPROX_FTZ_D",
-            asm: "rcp.approx.ftz.f64 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0798",
-        id: "rcp_rn_f64",
-        abi_id: "i0798",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RN_D",
-            asm: "rcp.rn.f64 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0799",
-        id: "rcp_rz_f64",
-        abi_id: "i0799",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RZ_D",
-            asm: "rcp.rz.f64 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0800",
-        id: "rcp_rm_f64",
-        abi_id: "i0800",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RM_D",
-            asm: "rcp.rm.f64 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0801",
-        id: "rcp_rp_f64",
-        abi_id: "i0801",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_RCP_RP_D",
-            asm: "rcp.rp.f64 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0802",
-        id: "rsqrt_approx_f32",
-        abi_id: "i0802",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0803",
-        id: "rsqrt_approx_ftz_f32",
-        abi_id: "i0803",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0804",
-        id: "rsqrt_approx_f64",
-        abi_id: "i0804",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0805",
-        id: "sqrt_approx_f32",
-        abi_id: "i0805",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_APPROX_F",
-            asm: "sqrt.approx.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0806",
-        id: "sqrt_approx_ftz_f32",
-        abi_id: "i0806",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_APPROX_FTZ_F",
-            asm: "sqrt.approx.ftz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0807",
-        id: "sqrt_rn_f32",
-        abi_id: "i0807",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RN_F",
-            asm: "sqrt.rn.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0808",
-        id: "sqrt_rn_ftz_f32",
-        abi_id: "i0808",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RN_FTZ_F",
-            asm: "sqrt.rn.ftz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0809",
-        id: "sqrt_rz_f32",
-        abi_id: "i0809",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RZ_F",
-            asm: "sqrt.rz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0810",
-        id: "sqrt_rz_ftz_f32",
-        abi_id: "i0810",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RZ_FTZ_F",
-            asm: "sqrt.rz.ftz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0811",
-        id: "sqrt_rm_f32",
-        abi_id: "i0811",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RM_F",
-            asm: "sqrt.rm.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0812",
-        id: "sqrt_rm_ftz_f32",
-        abi_id: "i0812",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RM_FTZ_F",
-            asm: "sqrt.rm.ftz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0813",
-        id: "sqrt_rp_f32",
-        abi_id: "i0813",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RP_F",
-            asm: "sqrt.rp.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0814",
-        id: "sqrt_rp_ftz_f32",
-        abi_id: "i0814",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RP_FTZ_F",
-            asm: "sqrt.rp.ftz.f32 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0815",
-        id: "sqrt_rn_f64",
-        abi_id: "i0815",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RN_D",
-            asm: "sqrt.rn.f64 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0816",
-        id: "sqrt_rz_f64",
-        abi_id: "i0816",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RZ_D",
-            asm: "sqrt.rz.f64 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0817",
-        id: "sqrt_rm_f64",
-        abi_id: "i0817",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RM_D",
-            asm: "sqrt.rm.f64 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0818",
-        id: "sqrt_rp_f64",
-        abi_id: "i0818",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_SQRT_RP_D",
-            asm: "sqrt.rp.f64 \t$dst, $src0;",
-            predicates: &[],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0819",
-        id: "ex2_approx_f32",
-        abi_id: "i0819",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0820",
-        id: "ex2_approx_ftz_f32",
-        abi_id: "i0820",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0821",
-        id: "tanh_approx_f32",
-        abi_id: "i0821",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0822",
-        id: "cvt_rn_satfinite_e4m3x2_f16x2",
-        abi_id: "i0822",
-        dialect_op: "nvvm.cvt_rn_satfinite_e4m3x2_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0823",
-        id: "cvt_rn_satfinite_relu_e4m3x2_f16x2",
-        abi_id: "i0823",
-        dialect_op: "nvvm.cvt_rn_satfinite_relu_e4m3x2_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0824",
-        id: "cvt_rn_satfinite_e5m2x2_f16x2",
-        abi_id: "i0824",
-        dialect_op: "nvvm.cvt_rn_satfinite_e5m2x2_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0825",
-        id: "cvt_rn_satfinite_relu_e5m2x2_f16x2",
-        abi_id: "i0825",
-        dialect_op: "nvvm.cvt_rn_satfinite_relu_e5m2x2_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0826",
-        id: "cvt_rn_f16x2_e4m3x2",
-        abi_id: "i0826",
-        dialect_op: "nvvm.cvt_rn_f16x2_e4m3x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0827",
-        id: "cvt_rn_relu_f16x2_e4m3x2",
-        abi_id: "i0827",
-        dialect_op: "nvvm.cvt_rn_relu_f16x2_e4m3x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0828",
-        id: "cvt_rn_f16x2_e5m2x2",
-        abi_id: "i0828",
-        dialect_op: "nvvm.cvt_rn_f16x2_e5m2x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0829",
-        id: "cvt_rn_relu_f16x2_e5m2x2",
-        abi_id: "i0829",
-        dialect_op: "nvvm.cvt_rn_relu_f16x2_e5m2x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                89,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(89),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0830",
-        id: "min_f16",
-        abi_id: "i0830",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_f16",
-            asm: "min.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0831",
-        id: "min_ftz_f16",
-        abi_id: "i0831",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_ftz_f16",
-            asm: "min.ftz.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0832",
-        id: "min_nan_f16",
-        abi_id: "i0832",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_NaN_f16",
-            asm: "min.NaN.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0833",
-        id: "min_ftz_nan_f16",
-        abi_id: "i0833",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_ftz_NaN_f16",
-            asm: "min.ftz.NaN.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0834",
-        id: "min_xorsign_abs_f16",
-        abi_id: "i0834",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_xorsign_abs_f16",
-            asm: "min.xorsign.abs.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0835",
-        id: "min_ftz_xorsign_abs_f16",
-        abi_id: "i0835",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_ftz_xorsign_abs_f16",
-            asm: "min.ftz.xorsign.abs.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0836",
-        id: "min_nan_xorsign_abs_f16",
-        abi_id: "i0836",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_f16",
-            asm: "min.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0837",
-        id: "min_ftz_nan_xorsign_abs_f16",
-        abi_id: "i0837",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_ftz_NaN_xorsign_abs_f16",
-            asm: "min.ftz.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0838",
-        id: "min_bf16",
-        abi_id: "i0838",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_bf16",
-            asm: "min.bf16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0839",
-        id: "min_nan_bf16",
-        abi_id: "i0839",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_NaN_bf16",
-            asm: "min.NaN.bf16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0840",
-        id: "min_xorsign_abs_bf16",
-        abi_id: "i0840",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_xorsign_abs_bf16",
-            asm: "min.xorsign.abs.bf16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0841",
-        id: "min_nan_xorsign_abs_bf16",
-        abi_id: "i0841",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16,
-            operation: GeneratedExtendedMinMaxOperation::Min,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_bf16",
-            asm: "min.NaN.xorsign.abs.bf16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0842",
-        id: "max_f16",
-        abi_id: "i0842",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_f16",
-            asm: "max.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0843",
-        id: "max_ftz_f16",
-        abi_id: "i0843",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_ftz_f16",
-            asm: "max.ftz.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0844",
-        id: "max_nan_f16",
-        abi_id: "i0844",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_NaN_f16",
-            asm: "max.NaN.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0845",
-        id: "max_ftz_nan_f16",
-        abi_id: "i0845",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_ftz_NaN_f16",
-            asm: "max.ftz.NaN.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0846",
-        id: "max_xorsign_abs_f16",
-        abi_id: "i0846",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_xorsign_abs_f16",
-            asm: "max.xorsign.abs.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0847",
-        id: "max_ftz_xorsign_abs_f16",
-        abi_id: "i0847",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_ftz_xorsign_abs_f16",
-            asm: "max.ftz.xorsign.abs.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0848",
-        id: "max_nan_xorsign_abs_f16",
-        abi_id: "i0848",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_f16",
-            asm: "max.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0849",
-        id: "max_ftz_nan_xorsign_abs_f16",
-        abi_id: "i0849",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::F16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_ftz_NaN_xorsign_abs_f16",
-            asm: "max.ftz.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0850",
-        id: "max_bf16",
-        abi_id: "i0850",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_bf16",
-            asm: "max.bf16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0851",
-        id: "max_nan_bf16",
-        abi_id: "i0851",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: false,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_NaN_bf16",
-            asm: "max.NaN.bf16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0852",
-        id: "max_xorsign_abs_bf16",
-        abi_id: "i0852",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Number,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_xorsign_abs_bf16",
-            asm: "max.xorsign.abs.bf16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0853",
-        id: "max_nan_xorsign_abs_bf16",
-        abi_id: "i0853",
-        dialect_op: "nvvm.extended_minmax",
-        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
-            format: GeneratedExtendedMinMaxFormat::Bf16,
-            operation: GeneratedExtendedMinMaxOperation::Max,
-            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-            nan: GeneratedExtendedMinMaxNan::Nan,
-            xorsign_abs: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                86,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(86),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_bf16",
-            asm: "max.NaN.xorsign.abs.bf16 \t$dst, $src0, $src1;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 72",
-                "Subtarget->getSmVersion() >= 86",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0854",
-        id: "fma_ftz_f16x2",
-        abi_id: "i0854",
-        dialect_op: "nvvm.fma_ftz_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_ftz_f16x2",
-            asm: "fma.rn.ftz.f16x2 \t$dst, $src0, $src1, $src2;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 53",
-                "Subtarget->getPTXVersion() >= 42",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0855",
-        id: "fma_sat_f16x2",
-        abi_id: "i0855",
-        dialect_op: "nvvm.fma_sat_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_sat_f16x2",
-            asm: "fma.rn.sat.f16x2 \t$dst, $src0, $src1, $src2;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 53",
-                "Subtarget->getPTXVersion() >= 42",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0856",
-        id: "fma_ftz_sat_f16x2",
-        abi_id: "i0856",
-        dialect_op: "nvvm.fma_ftz_sat_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                70,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(70),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_ftz_sat_f16x2",
-            asm: "fma.rn.ftz.sat.f16x2 \t$dst, $src0, $src1, $src2;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 53",
-                "Subtarget->getPTXVersion() >= 42",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0857",
-        id: "fma_ftz_relu_f16x2",
-        abi_id: "i0857",
-        dialect_op: "nvvm.fma_ftz_relu_f16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                80,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(80),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_NVVM_FMA_rn_ftz_relu_f16x2",
-            asm: "fma.rn.ftz.relu.f16x2 \t$dst, $src0, $src1, $src2;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 80",
-                "Subtarget->getPTXVersion() >= 70",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem", "IntrSpeculatable"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0858",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1",
-        abi_id: "i0858",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19651",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0859",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3",
-        abi_id: "i0859",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19656",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0860",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2",
-        abi_id: "i0860",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19661",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0861",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3",
-        abi_id: "i0861",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19671",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0862",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2",
-        abi_id: "i0862",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m1,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19666",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0863",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1",
-        abi_id: "i0863",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19676",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0864",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3",
-        abi_id: "i0864",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19680",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0865",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2",
-        abi_id: "i0865",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19684",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0866",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3",
-        abi_id: "i0866",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19692",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0867",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2",
-        abi_id: "i0867",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E2m3,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19688",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0868",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1",
-        abi_id: "i0868",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19697",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0869",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3",
-        abi_id: "i0869",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19701",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0870",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2",
-        abi_id: "i0870",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19705",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0871",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3",
-        abi_id: "i0871",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19713",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0872",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2",
-        abi_id: "i0872",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E3m2,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19709",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0873",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1",
-        abi_id: "i0873",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19739",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0874",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3",
-        abi_id: "i0874",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19743",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0875",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2",
-        abi_id: "i0875",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19747",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0876",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3",
-        abi_id: "i0876",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19755",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0877",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2",
-        abi_id: "i0877",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E4m3,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19751",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0878",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1",
-        abi_id: "i0878",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E2m1,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19718",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0879",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3",
-        abi_id: "i0879",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E2m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19722",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0880",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2",
-        abi_id: "i0880",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E3m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19726",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0881",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3",
-        abi_id: "i0881",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E4m3,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19734",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0882",
-        id: "mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2",
-        abi_id: "i0882",
-        dialect_op: "nvvm.register_mma",
-        variant: GeneratedIntrinsicVariant::RegisterMma {
-            shape: GeneratedRegisterMmaShape::M16n8k32,
-            operation: GeneratedRegisterMmaOperation::Multiply,
-            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-            accumulator: GeneratedRegisterMmaAccumulator::F32,
-            a_element: GeneratedRegisterMmaElement::E5m2,
-            b_element: GeneratedRegisterMmaElement::E5m2,
-            a_layout: GeneratedRegisterMmaLayout::Row,
-            b_layout: GeneratedRegisterMmaLayout::Col,
-            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_19730",
-            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-            predicates: &["Subtarget->hasMMABlockScale()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0883",
-        id: "barrier_cta_sync",
-        abi_id: "i0883",
-        dialect_op: "nvvm.barrier_cta_sync_count",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_SYNC_ii",
-                asm: "barrier.sync \t$i, $j;",
-                predicates: &["Subtarget->getPTXVersion() >= 60"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_SYNC_ir",
-                asm: "barrier.sync \t$i, $j;",
-                predicates: &["Subtarget->getPTXVersion() >= 60"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_SYNC_ri",
-                asm: "barrier.sync \t$i, $j;",
-                predicates: &["Subtarget->getPTXVersion() >= 60"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_SYNC_rr",
-                asm: "barrier.sync \t$i, $j;",
-                predicates: &["Subtarget->getPTXVersion() >= 60"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0884",
-        id: "barrier_cta_sync_aligned",
-        abi_id: "i0884",
-        dialect_op: "nvvm.barrier_cta_sync_aligned_count",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_SYNC_ALIGNED_ii",
-                asm: "bar.sync \t$i, $j;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_SYNC_ALIGNED_ir",
-                asm: "bar.sync \t$i, $j;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_SYNC_ALIGNED_ri",
-                asm: "bar.sync \t$i, $j;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_SYNC_ALIGNED_rr",
-                asm: "bar.sync \t$i, $j;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0885",
-        id: "barrier_cta_arrive",
-        abi_id: "i0885",
-        dialect_op: "nvvm.barrier_cta_arrive_count",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                30,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(30),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_ARRIVE_ii",
-                asm: "barrier.arrive \t$i, $j;",
-                predicates: &["Subtarget->getPTXVersion() >= 60"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_ARRIVE_ir",
-                asm: "barrier.arrive \t$i, $j;",
-                predicates: &["Subtarget->getPTXVersion() >= 60"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_ARRIVE_ri",
-                asm: "barrier.arrive \t$i, $j;",
-                predicates: &["Subtarget->getPTXVersion() >= 60"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_ARRIVE_rr",
-                asm: "barrier.arrive \t$i, $j;",
-                predicates: &["Subtarget->getPTXVersion() >= 60"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0886",
-        id: "barrier_cta_arrive_aligned",
-        abi_id: "i0886",
-        dialect_op: "nvvm.barrier_cta_arrive_aligned_count",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(20),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ii",
-                asm: "bar.arrive \t$i, $j;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ir",
-                asm: "bar.arrive \t$i, $j;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ri",
-                asm: "bar.arrive \t$i, $j;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-            GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_rr",
-                asm: "bar.arrive \t$i, $j;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[],
-                },
-            },
-        ],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrConvergent", "IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0887",
-        id: "prefetch_tma_descriptor",
-        abi_id: "i0887",
-        dialect_op: "nvvm.prefetch_tensormap",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrArgMemOnly", "NoCapture<arg0>", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0888",
-        id: "cp_async_bulk_prefetch_tensor_1d_l2",
-        abi_id: "i0888",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_1d_l2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_1D",
-            asm: "cp.async.bulk.prefetch.tensor.1d.L2.global.tile [$tmap, {{$d0}}];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 3,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg3>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0889",
-        id: "cp_async_bulk_prefetch_tensor_2d_l2",
-        abi_id: "i0889",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_2d_l2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_2D",
-            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile [$tmap, {{$d0, $d1}}];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 4,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg4>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0890",
-        id: "cp_async_bulk_prefetch_tensor_3d_l2",
-        abi_id: "i0890",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_3d_l2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_3D",
-            asm: "cp.async.bulk.prefetch.tensor.3d.L2.global.tile [$tmap, {{$d0, $d1, $d2}}];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 5,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg5>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0891",
-        id: "cp_async_bulk_prefetch_tensor_4d_l2",
-        abi_id: "i0891",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_4d_l2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_4D",
-            asm: "cp.async.bulk.prefetch.tensor.4d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3}}];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 6,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg6>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0892",
-        id: "cp_async_bulk_prefetch_tensor_5d_l2",
-        abi_id: "i0892",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_5d_l2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_5D",
-            asm: "cp.async.bulk.prefetch.tensor.5d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 7,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0893",
-        id: "cp_async_bulk_prefetch_tensor_gather4_2d_l2",
-        abi_id: "i0893",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_GATHER4_2D",
-            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4 [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
-            predicates: &["Subtarget->hasTMABlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 7,
-                    value: 0,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0894",
-        id: "tensormap_replace_box_dim",
-        abi_id: "i0894",
-        dialect_op: "nvvm.tensormap_replace_box_dim",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0895",
-        id: "tensormap_replace_element_stride",
-        abi_id: "i0895",
-        dialect_op: "nvvm.tensormap_replace_element_stride",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0896",
-        id: "tensormap_replace_element_type",
-        abi_id: "i0896",
-        dialect_op: "nvvm.tensormap_replace_element_type",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ArgInfo<arg1>",
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "Range<arg1,0,16>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0897",
-        id: "tensormap_replace_fill_mode",
-        abi_id: "i0897",
-        dialect_op: "nvvm.tensormap_replace_fill_mode",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ArgInfo<arg1>",
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "Range<arg1,0,2>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0898",
-        id: "tensormap_replace_global_address",
-        abi_id: "i0898",
-        dialect_op: "nvvm.tensormap_replace_global_address",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrArgMemOnly", "IntrWriteMem", "NoCapture<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0899",
-        id: "tensormap_replace_global_dim",
-        abi_id: "i0899",
-        dialect_op: "nvvm.tensormap_replace_global_dim",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0900",
-        id: "tensormap_replace_global_stride",
-        abi_id: "i0900",
-        dialect_op: "nvvm.tensormap_replace_global_stride",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0901",
-        id: "tensormap_replace_interleave_layout",
-        abi_id: "i0901",
-        dialect_op: "nvvm.tensormap_replace_interleave_layout",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ArgInfo<arg1>",
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "Range<arg1,0,3>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0902",
-        id: "tensormap_replace_rank",
-        abi_id: "i0902",
-        dialect_op: "nvvm.tensormap_replace_rank",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrArgMemOnly", "IntrWriteMem", "NoCapture<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0903",
-        id: "tensormap_replace_swizzle_atomicity",
-        abi_id: "i0903",
-        dialect_op: "nvvm.tensormap_replace_swizzle_atomicity",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ArgInfo<arg1>",
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "Range<arg1,0,4>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0904",
-        id: "tensormap_replace_swizzle_mode",
-        abi_id: "i0904",
-        dialect_op: "nvvm.tensormap_replace_swizzle_mode",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ArgInfo<arg1>",
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "Range<arg1,0,5>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0905",
-        id: "fence_proxy_tensormap_generic_acquire_cluster",
-        abi_id: "i0905",
-        dialect_op: "nvvm.fence_proxy_tensormap_generic_acquire_cluster",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CLUSTER",
-            asm: "fence.proxy.tensormap::generic.acquire.cluster [$addr], 128;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 83",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "Range<arg1,128,129>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0906",
-        id: "fence_proxy_tensormap_generic_acquire_cta",
-        abi_id: "i0906",
-        dialect_op: "nvvm.fence_proxy_tensormap_generic_acquire_cta",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CTA",
-            asm: "fence.proxy.tensormap::generic.acquire.cta [$addr], 128;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 83",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "Range<arg1,128,129>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0907",
-        id: "fence_proxy_tensormap_generic_acquire_gpu",
-        abi_id: "i0907",
-        dialect_op: "nvvm.fence_proxy_tensormap_generic_acquire_gpu",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_GPU",
-            asm: "fence.proxy.tensormap::generic.acquire.gpu [$addr], 128;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 83",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "Range<arg1,128,129>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0908",
-        id: "fence_proxy_tensormap_generic_acquire_system",
-        abi_id: "i0908",
-        dialect_op: "nvvm.fence_proxy_tensormap_generic_acquire_system",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_SYS",
-            asm: "fence.proxy.tensormap::generic.acquire.sys [$addr], 128;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 83",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "Range<arg1,128,129>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0909",
-        id: "fence_proxy_tensormap_generic_release_cluster",
-        abi_id: "i0909",
-        dialect_op: "nvvm.fence_proxy_tensormap_generic_release_cluster",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CLUSTER",
-            asm: "fence.proxy.tensormap::generic.release.cluster;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 83",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0910",
-        id: "fence_proxy_tensormap_generic_release_cta",
-        abi_id: "i0910",
-        dialect_op: "nvvm.fence_proxy_tensormap_generic_release_cta",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CTA",
-            asm: "fence.proxy.tensormap::generic.release.cta;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 83",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0911",
-        id: "fence_proxy_tensormap_generic_release_gpu",
-        abi_id: "i0911",
-        dialect_op: "nvvm.fence_proxy_tensormap_generic_release_gpu",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_GPU",
-            asm: "fence.proxy.tensormap::generic.release.gpu;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 83",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0912",
-        id: "fence_proxy_tensormap_generic_release_system",
-        abi_id: "i0912",
-        dialect_op: "nvvm.fence_proxy_tensormap_generic_release_system",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_SYS",
-            asm: "fence.proxy.tensormap::generic.release.sys;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 83",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoCallback"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0913",
-        id: "grid_dependency_launch_dependents",
-        abi_id: "i0913",
-        dialect_op: "nvvm.grid_dependency_launch_dependents",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "GRIDDEPCONTROL_LAUNCH_DEPENDENTS",
-            asm: "griddepcontrol.launch_dependents;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrHasSideEffects", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0914",
-        id: "grid_dependency_wait",
-        abi_id: "i0914",
-        dialect_op: "nvvm.grid_dependency_wait",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "GRIDDEPCONTROL_WAIT",
-            asm: "griddepcontrol.wait;",
-            predicates: &[
-                "Subtarget->getSmVersion() >= 90",
-                "Subtarget->getPTXVersion() >= 78",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrHasSideEffects", "IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0915",
-        id: "setmaxnreg_inc",
-        abi_id: "i0915",
-        dialect_op: "nvvm.setmaxnreg_inc",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_22212",
-            asm: "setmaxnreg.inc.sync.aligned.u32 \t$reg_count;",
-            predicates: &["Subtarget->hasSetMaxNRegSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg0>",
-                "IntrConvergent",
-                "IntrHasSideEffects",
-                "IntrNoMem",
-                "Range<arg0,24,257>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0916",
-        id: "setmaxnreg_dec",
-        abi_id: "i0916",
-        dialect_op: "nvvm.setmaxnreg_dec",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-                GeneratedHardwareAlternative::FamilyTarget(110),
-                GeneratedHardwareAlternative::ExactArchitecture(120),
-                GeneratedHardwareAlternative::FamilyTarget(120),
-                GeneratedHardwareAlternative::ExactArchitecture(121),
-                GeneratedHardwareAlternative::FamilyTarget(121),
-                GeneratedHardwareAlternative::ExactArchitecture(90),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::FamilyTarget(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::FamilyTarget(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                        GeneratedHardwareAlternative::FamilyTarget(110),
-                        GeneratedHardwareAlternative::ExactArchitecture(120),
-                        GeneratedHardwareAlternative::FamilyTarget(120),
-                        GeneratedHardwareAlternative::ExactArchitecture(121),
-                        GeneratedHardwareAlternative::FamilyTarget(121),
-                        GeneratedHardwareAlternative::ExactArchitecture(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_22214",
-            asm: "setmaxnreg.dec.sync.aligned.u32 \t$reg_count;",
-            predicates: &["Subtarget->hasSetMaxNRegSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg0>",
-                "IntrConvergent",
-                "IntrHasSideEffects",
-                "IntrNoMem",
-                "Range<arg0,24,257>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0917",
-        id: "cp_async_bulk_prefetch_tensor_1d_l2_cache_hint",
-        abi_id: "i0917",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_1d_l2_cache_hint",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_1D_CH",
-            asm: "cp.async.bulk.prefetch.tensor.1d.L2.global.tile.L2::cache_hint [$tmap, {{$d0}}], $ch;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 3,
-                    value: -1,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg3>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0918",
-        id: "cp_async_bulk_prefetch_tensor_2d_l2_cache_hint",
-        abi_id: "i0918",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_2d_l2_cache_hint",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_2D_CH",
-            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1}}], $ch;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 4,
-                    value: -1,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg4>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0919",
-        id: "cp_async_bulk_prefetch_tensor_3d_l2_cache_hint",
-        abi_id: "i0919",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_3d_l2_cache_hint",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_3D_CH",
-            asm: "cp.async.bulk.prefetch.tensor.3d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2}}], $ch;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 5,
-                    value: -1,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg5>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0920",
-        id: "cp_async_bulk_prefetch_tensor_4d_l2_cache_hint",
-        abi_id: "i0920",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_4d_l2_cache_hint",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_4D_CH",
-            asm: "cp.async.bulk.prefetch.tensor.4d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3}}], $ch;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 6,
-                    value: -1,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg6>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0921",
-        id: "cp_async_bulk_prefetch_tensor_5d_l2_cache_hint",
-        abi_id: "i0921",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_5d_l2_cache_hint",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_5D_CH",
-            asm: "cp.async.bulk.prefetch.tensor.5d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
-            predicates: &[
-                "Subtarget->getPTXVersion() >= 80",
-                "Subtarget->getSmVersion() >= 90",
-            ],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 7,
-                    value: -1,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0922",
-        id: "cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint",
-        abi_id: "i0922",
-        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::ExactArchitecture(101),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::ExactArchitecture(110),
-            ]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::ExactArchitecture(100),
-                        GeneratedHardwareAlternative::ExactArchitecture(101),
-                        GeneratedHardwareAlternative::ExactArchitecture(103),
-                        GeneratedHardwareAlternative::ExactArchitecture(110),
-                    ]),
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "TMA_TENSOR_PF_TILE_GATHER4_2D_CH",
-            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
-            predicates: &["Subtarget->hasTMABlackwellSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[GeneratedImmediateBinding {
-                    argument_index: 7,
-                    value: -1,
-                }],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0923",
-        id: "cp_async_bulk_tensor_reduce_add_tile_1d",
-        abi_id: "i0923",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_tile_1d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0924",
-        id: "cp_async_bulk_tensor_reduce_add_tile_2d",
-        abi_id: "i0924",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_tile_2d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0925",
-        id: "cp_async_bulk_tensor_reduce_add_tile_3d",
-        abi_id: "i0925",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_tile_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0926",
-        id: "cp_async_bulk_tensor_reduce_add_tile_4d",
-        abi_id: "i0926",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_tile_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0927",
-        id: "cp_async_bulk_tensor_reduce_add_tile_5d",
-        abi_id: "i0927",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_tile_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0928",
-        id: "cp_async_bulk_tensor_reduce_add_im2col_3d",
-        abi_id: "i0928",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_im2col_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0929",
-        id: "cp_async_bulk_tensor_reduce_add_im2col_4d",
-        abi_id: "i0929",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_im2col_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0930",
-        id: "cp_async_bulk_tensor_reduce_add_im2col_5d",
-        abi_id: "i0930",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_im2col_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0931",
-        id: "cp_async_bulk_tensor_reduce_and_tile_1d",
-        abi_id: "i0931",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_tile_1d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0932",
-        id: "cp_async_bulk_tensor_reduce_and_tile_2d",
-        abi_id: "i0932",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_tile_2d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0933",
-        id: "cp_async_bulk_tensor_reduce_and_tile_3d",
-        abi_id: "i0933",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_tile_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0934",
-        id: "cp_async_bulk_tensor_reduce_and_tile_4d",
-        abi_id: "i0934",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_tile_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0935",
-        id: "cp_async_bulk_tensor_reduce_and_tile_5d",
-        abi_id: "i0935",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_tile_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0936",
-        id: "cp_async_bulk_tensor_reduce_and_im2col_3d",
-        abi_id: "i0936",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_im2col_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0937",
-        id: "cp_async_bulk_tensor_reduce_and_im2col_4d",
-        abi_id: "i0937",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_im2col_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0938",
-        id: "cp_async_bulk_tensor_reduce_and_im2col_5d",
-        abi_id: "i0938",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_im2col_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0939",
-        id: "cp_async_bulk_tensor_reduce_dec_tile_1d",
-        abi_id: "i0939",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_tile_1d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0940",
-        id: "cp_async_bulk_tensor_reduce_dec_tile_2d",
-        abi_id: "i0940",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_tile_2d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0941",
-        id: "cp_async_bulk_tensor_reduce_dec_tile_3d",
-        abi_id: "i0941",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_tile_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0942",
-        id: "cp_async_bulk_tensor_reduce_dec_tile_4d",
-        abi_id: "i0942",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_tile_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0943",
-        id: "cp_async_bulk_tensor_reduce_dec_tile_5d",
-        abi_id: "i0943",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_tile_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0944",
-        id: "cp_async_bulk_tensor_reduce_dec_im2col_3d",
-        abi_id: "i0944",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0945",
-        id: "cp_async_bulk_tensor_reduce_dec_im2col_4d",
-        abi_id: "i0945",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0946",
-        id: "cp_async_bulk_tensor_reduce_dec_im2col_5d",
-        abi_id: "i0946",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0947",
-        id: "cp_async_bulk_tensor_reduce_inc_tile_1d",
-        abi_id: "i0947",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_tile_1d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0948",
-        id: "cp_async_bulk_tensor_reduce_inc_tile_2d",
-        abi_id: "i0948",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_tile_2d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0949",
-        id: "cp_async_bulk_tensor_reduce_inc_tile_3d",
-        abi_id: "i0949",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_tile_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0950",
-        id: "cp_async_bulk_tensor_reduce_inc_tile_4d",
-        abi_id: "i0950",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_tile_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0951",
-        id: "cp_async_bulk_tensor_reduce_inc_tile_5d",
-        abi_id: "i0951",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_tile_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0952",
-        id: "cp_async_bulk_tensor_reduce_inc_im2col_3d",
-        abi_id: "i0952",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0953",
-        id: "cp_async_bulk_tensor_reduce_inc_im2col_4d",
-        abi_id: "i0953",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0954",
-        id: "cp_async_bulk_tensor_reduce_inc_im2col_5d",
-        abi_id: "i0954",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0955",
-        id: "cp_async_bulk_tensor_reduce_max_tile_1d",
-        abi_id: "i0955",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_tile_1d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0956",
-        id: "cp_async_bulk_tensor_reduce_max_tile_2d",
-        abi_id: "i0956",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_tile_2d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0957",
-        id: "cp_async_bulk_tensor_reduce_max_tile_3d",
-        abi_id: "i0957",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_tile_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0958",
-        id: "cp_async_bulk_tensor_reduce_max_tile_4d",
-        abi_id: "i0958",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_tile_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0959",
-        id: "cp_async_bulk_tensor_reduce_max_tile_5d",
-        abi_id: "i0959",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_tile_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0960",
-        id: "cp_async_bulk_tensor_reduce_max_im2col_3d",
-        abi_id: "i0960",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_im2col_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0961",
-        id: "cp_async_bulk_tensor_reduce_max_im2col_4d",
-        abi_id: "i0961",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_im2col_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0962",
-        id: "cp_async_bulk_tensor_reduce_max_im2col_5d",
-        abi_id: "i0962",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_im2col_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0963",
-        id: "cp_async_bulk_tensor_reduce_min_tile_1d",
-        abi_id: "i0963",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_tile_1d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0964",
-        id: "cp_async_bulk_tensor_reduce_min_tile_2d",
-        abi_id: "i0964",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_tile_2d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0965",
-        id: "cp_async_bulk_tensor_reduce_min_tile_3d",
-        abi_id: "i0965",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_tile_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0966",
-        id: "cp_async_bulk_tensor_reduce_min_tile_4d",
-        abi_id: "i0966",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_tile_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0967",
-        id: "cp_async_bulk_tensor_reduce_min_tile_5d",
-        abi_id: "i0967",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_tile_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0968",
-        id: "cp_async_bulk_tensor_reduce_min_im2col_3d",
-        abi_id: "i0968",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_im2col_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0969",
-        id: "cp_async_bulk_tensor_reduce_min_im2col_4d",
-        abi_id: "i0969",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_im2col_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0970",
-        id: "cp_async_bulk_tensor_reduce_min_im2col_5d",
-        abi_id: "i0970",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_im2col_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0971",
-        id: "cp_async_bulk_tensor_reduce_or_tile_1d",
-        abi_id: "i0971",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_tile_1d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0972",
-        id: "cp_async_bulk_tensor_reduce_or_tile_2d",
-        abi_id: "i0972",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_tile_2d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0973",
-        id: "cp_async_bulk_tensor_reduce_or_tile_3d",
-        abi_id: "i0973",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_tile_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0974",
-        id: "cp_async_bulk_tensor_reduce_or_tile_4d",
-        abi_id: "i0974",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_tile_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0975",
-        id: "cp_async_bulk_tensor_reduce_or_tile_5d",
-        abi_id: "i0975",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_tile_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0976",
-        id: "cp_async_bulk_tensor_reduce_or_im2col_3d",
-        abi_id: "i0976",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_im2col_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0977",
-        id: "cp_async_bulk_tensor_reduce_or_im2col_4d",
-        abi_id: "i0977",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_im2col_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0978",
-        id: "cp_async_bulk_tensor_reduce_or_im2col_5d",
-        abi_id: "i0978",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_im2col_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0979",
-        id: "cp_async_bulk_tensor_reduce_xor_tile_1d",
-        abi_id: "i0979",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_tile_1d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0980",
-        id: "cp_async_bulk_tensor_reduce_xor_tile_2d",
-        abi_id: "i0980",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_tile_2d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0981",
-        id: "cp_async_bulk_tensor_reduce_xor_tile_3d",
-        abi_id: "i0981",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_tile_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0982",
-        id: "cp_async_bulk_tensor_reduce_xor_tile_4d",
-        abi_id: "i0982",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_tile_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0983",
-        id: "cp_async_bulk_tensor_reduce_xor_tile_5d",
-        abi_id: "i0983",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_tile_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0984",
-        id: "cp_async_bulk_tensor_reduce_xor_im2col_3d",
-        abi_id: "i0984",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_3d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0985",
-        id: "cp_async_bulk_tensor_reduce_xor_im2col_4d",
-        abi_id: "i0985",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_4d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0986",
-        id: "cp_async_bulk_tensor_reduce_xor_im2col_5d",
-        abi_id: "i0986",
-        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_5d",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(90),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0987",
-        id: "min_relu_s32",
-        abi_id: "i0987",
-        dialect_op: "nvvm.min_relu_s32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[GeneratedBackendRequirement {
-            backend: GeneratedIntrinsicBackend::LlvmNvptx,
-            requirement: GeneratedTargetRequirement {
-                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                hardware: GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::MinimumSm(90),
-                ]),
-            },
-        }],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0988",
-        id: "max_relu_s32",
-        abi_id: "i0988",
-        dialect_op: "nvvm.max_relu_s32",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[GeneratedBackendRequirement {
-            backend: GeneratedIntrinsicBackend::LlvmNvptx,
-            requirement: GeneratedTargetRequirement {
-                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                hardware: GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::MinimumSm(90),
-                ]),
-            },
-        }],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0989",
-        id: "min_s16x2",
-        abi_id: "i0989",
-        dialect_op: "nvvm.min_s16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[GeneratedBackendRequirement {
-            backend: GeneratedIntrinsicBackend::LlvmNvptx,
-            requirement: GeneratedTargetRequirement {
-                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                hardware: GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::MinimumSm(90),
-                ]),
-            },
-        }],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0990",
-        id: "max_s16x2",
-        abi_id: "i0990",
-        dialect_op: "nvvm.max_s16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[GeneratedBackendRequirement {
-            backend: GeneratedIntrinsicBackend::LlvmNvptx,
-            requirement: GeneratedTargetRequirement {
-                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                hardware: GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::MinimumSm(90),
-                ]),
-            },
-        }],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0991",
-        id: "min_u16x2",
-        abi_id: "i0991",
-        dialect_op: "nvvm.min_u16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[GeneratedBackendRequirement {
-            backend: GeneratedIntrinsicBackend::LlvmNvptx,
-            requirement: GeneratedTargetRequirement {
-                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                hardware: GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::MinimumSm(90),
-                ]),
-            },
-        }],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0992",
-        id: "max_u16x2",
-        abi_id: "i0992",
-        dialect_op: "nvvm.max_u16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[GeneratedBackendRequirement {
-            backend: GeneratedIntrinsicBackend::LlvmNvptx,
-            requirement: GeneratedTargetRequirement {
-                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                hardware: GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::MinimumSm(90),
-                ]),
-            },
-        }],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0993",
-        id: "min_relu_s16x2",
-        abi_id: "i0993",
-        dialect_op: "nvvm.min_relu_s16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[GeneratedBackendRequirement {
-            backend: GeneratedIntrinsicBackend::LlvmNvptx,
-            requirement: GeneratedTargetRequirement {
-                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                hardware: GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::MinimumSm(90),
-                ]),
-            },
-        }],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0994",
-        id: "max_relu_s16x2",
-        abi_id: "i0994",
-        dialect_op: "nvvm.max_relu_s16x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                90,
-            )]),
-        },
-        backend_requirements: &[GeneratedBackendRequirement {
-            backend: GeneratedIntrinsicBackend::LlvmNvptx,
-            requirement: GeneratedTargetRequirement {
-                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                hardware: GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::MinimumSm(90),
-                ]),
-            },
-        }],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0995",
-        id: "add_f32x2",
-        abi_id: "i0995",
-        dialect_op: "nvvm.add_f32x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0996",
-        id: "add_ftz_f32x2",
-        abi_id: "i0996",
-        dialect_op: "nvvm.add_ftz_f32x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0997",
-        id: "sub_f32x2",
-        abi_id: "i0997",
-        dialect_op: "nvvm.sub_f32x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0998",
-        id: "sub_ftz_f32x2",
-        abi_id: "i0998",
-        dialect_op: "nvvm.sub_ftz_f32x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i0999",
-        id: "mul_f32x2",
-        abi_id: "i0999",
-        dialect_op: "nvvm.mul_f32x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1000",
-        id: "mul_ftz_f32x2",
-        abi_id: "i1000",
-        dialect_op: "nvvm.mul_ftz_f32x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1001",
-        id: "fma_f32x2",
-        abi_id: "i1001",
-        dialect_op: "nvvm.fma_f32x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1002",
-        id: "fma_ftz_f32x2",
-        abi_id: "i1002",
-        dialect_op: "nvvm.fma_ftz_f32x2",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                100,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(100),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: None,
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1003",
-        id: "redux_sync_min_f32",
-        abi_id: "i1003",
-        dialect_op: "nvvm.redux_sync_fmin",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-            ]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15035",
-            asm: "redux.sync.min.f32 \t$dst, $src, $mask;",
-            predicates: &["Subtarget->hasReduxSyncF32()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1004",
-        id: "redux_sync_min_nan_f32",
-        abi_id: "i1004",
-        dialect_op: "nvvm.redux_sync_fmin_nan",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-            ]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15038",
-            asm: "redux.sync.min.NaN.f32 \t$dst, $src, $mask;",
-            predicates: &["Subtarget->hasReduxSyncF32()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1005",
-        id: "redux_sync_min_abs_f32",
-        abi_id: "i1005",
-        dialect_op: "nvvm.redux_sync_fmin_abs",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-            ]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15037",
-            asm: "redux.sync.min.abs.f32 \t$dst, $src, $mask;",
-            predicates: &["Subtarget->hasReduxSyncF32()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1006",
-        id: "redux_sync_min_abs_nan_f32",
-        abi_id: "i1006",
-        dialect_op: "nvvm.redux_sync_fmin_abs_nan",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-            ]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15039",
-            asm: "redux.sync.min.abs.NaN.f32 \t$dst, $src, $mask;",
-            predicates: &["Subtarget->hasReduxSyncF32()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1007",
-        id: "redux_sync_max_f32",
-        abi_id: "i1007",
-        dialect_op: "nvvm.redux_sync_fmax",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-            ]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15040",
-            asm: "redux.sync.max.f32 \t$dst, $src, $mask;",
-            predicates: &["Subtarget->hasReduxSyncF32()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1008",
-        id: "redux_sync_max_nan_f32",
-        abi_id: "i1008",
-        dialect_op: "nvvm.redux_sync_fmax_nan",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-            ]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15042",
-            asm: "redux.sync.max.NaN.f32 \t$dst, $src, $mask;",
-            predicates: &["Subtarget->hasReduxSyncF32()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1009",
-        id: "redux_sync_max_abs_f32",
-        abi_id: "i1009",
-        dialect_op: "nvvm.redux_sync_fmax_abs",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-            ]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15041",
-            asm: "redux.sync.max.abs.f32 \t$dst, $src, $mask;",
-            predicates: &["Subtarget->hasReduxSyncF32()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1010",
-        id: "redux_sync_max_abs_nan_f32",
-        abi_id: "i1010",
-        dialect_op: "nvvm.redux_sync_fmax_abs_nan",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::AnyOf(&[
-                GeneratedHardwareAlternative::ExactArchitecture(100),
-                GeneratedHardwareAlternative::FamilyTarget(100),
-                GeneratedHardwareAlternative::ExactArchitecture(103),
-                GeneratedHardwareAlternative::FamilyTarget(103),
-            ]),
-        },
-        backend_requirements: &[],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_15043",
-            asm: "redux.sync.max.abs.NaN.f32 \t$dst, $src, $mask;",
-            predicates: &["Subtarget->hasReduxSyncF32()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1011",
-        id: "tcgen05_mma_e4m3",
-        abi_id: "i1011",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::Shared,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[GeneratedTargetContract {
-                    selectors: &[GeneratedTargetSelectorBinding {
-                        name: "kind",
-                        value: "f8f6f4",
-                    }],
-                    alternatives: &[
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                        },
-                    ],
-                }],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_22534",
-            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1012",
-        id: "tcgen05_mma_e5m2",
-        abi_id: "i1012",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::Shared,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[GeneratedTargetContract {
-                    selectors: &[GeneratedTargetSelectorBinding {
-                        name: "kind",
-                        value: "f8f6f4",
-                    }],
-                    alternatives: &[
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                        },
-                    ],
-                }],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_22534",
-            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1013",
-        id: "tcgen05_mma_e2m3",
-        abi_id: "i1013",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::Shared,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[GeneratedTargetContract {
-                    selectors: &[GeneratedTargetSelectorBinding {
-                        name: "kind",
-                        value: "f8f6f4",
-                    }],
-                    alternatives: &[
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                        },
-                    ],
-                }],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_22534",
-            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1014",
-        id: "tcgen05_mma_e3m2",
-        abi_id: "i1014",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::Shared,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[GeneratedTargetContract {
-                    selectors: &[GeneratedTargetSelectorBinding {
-                        name: "kind",
-                        value: "f8f6f4",
-                    }],
-                    alternatives: &[
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                        },
-                    ],
-                }],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_22534",
-            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1015",
-        id: "tcgen05_mma_e2m1",
-        abi_id: "i1015",
-        dialect_op: "nvvm.tcgen05_mma",
-        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
-            form: GeneratedTcgen05MmaForm::Shared,
-            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-            compatibility_alias: true,
-        },
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: &[GeneratedTargetContract {
-                    selectors: &[GeneratedTargetSelectorBinding {
-                        name: "kind",
-                        value: "f8f6f4",
-                    }],
-                    alternatives: &[
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                        },
-                        GeneratedTargetAlternative {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                        },
-                    ],
-                }],
-            },
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                    hardware: GeneratedHardwareTarget::TargetMatrix {
-                        contracts: &[GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        }],
-                    },
-                },
-            },
-        ],
-        selections: &[GeneratedSelectionAlternative {
-            source_record: "anonymous_22534",
-            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-            predicates: &["Subtarget->hasTcgen05InstSupport()"],
-            constraints: GeneratedSelectionConstraints {
-                address_space: None,
-                immediate_bindings: &[],
-            },
-        }],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>",
-            ],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-    GeneratedIntrinsicTarget {
-        marker: "v1:i1016",
-        id: "ex2_approx_f16",
-        abi_id: "i1016",
-        dialect_op: "nvvm.scalar_math",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
-                75,
-            )]),
-        },
-        backend_requirements: &[
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-            GeneratedBackendRequirement {
-                backend: GeneratedIntrinsicBackend::LibNvvm,
-                requirement: GeneratedTargetRequirement {
-                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                    hardware: GeneratedHardwareTarget::AnyOf(&[
-                        GeneratedHardwareAlternative::MinimumSm(75),
-                    ]),
-                },
-            },
-        ],
-        selections: &[],
-        llvm: Some(GeneratedLlvmFacts {
-            properties: &["IntrNoMem"],
-            result_no_undef: false,
-            result_range: None,
-        }),
-    },
-];
-
-fn generated_intrinsic_compatibility_marker_by_op_name(op_name: &str) -> Option<&'static str> {
-    match op_name {
-        "nvvm.ldmatrix_x1" => Some("v1:i0025"),
-        "nvvm.ldmatrix_x1_trans" => Some("v1:i0026"),
-        "nvvm.ldmatrix_x2" => Some("v1:i0027"),
-        "nvvm.ldmatrix_x2_trans" => Some("v1:i0028"),
-        "nvvm.ldmatrix_x4" => Some("v1:i0013"),
-        "nvvm.ldmatrix_x4_trans" => Some("v1:i0029"),
-        _ => None,
-    }
-}
-
-pub fn generated_intrinsic_target_by_marker(
-    marker: &str,
-) -> Option<&'static GeneratedIntrinsicTarget> {
-    GENERATED_INTRINSIC_TARGETS
-        .iter()
-        .find(|target| target.marker == marker)
-}
-
-pub fn generated_intrinsic_targets_by_op_name(
-    op_name: &str,
-) -> impl Iterator<Item = &'static GeneratedIntrinsicTarget> + '_ {
-    let compatibility_marker = generated_intrinsic_compatibility_marker_by_op_name(op_name);
-    GENERATED_INTRINSIC_TARGETS.iter().filter(move |target| {
-        target.dialect_op == op_name || compatibility_marker == Some(target.marker)
-    })
-}
-
-pub fn generated_intrinsic_target_by_op_name(
-    op_name: &str,
-) -> Option<&'static GeneratedIntrinsicTarget> {
-    generated_intrinsic_targets_by_op_name(op_name).next()
-}
-
-pub fn generated_intrinsic_target(op_name: &str) -> Option<&'static GeneratedIntrinsicTarget> {
-    generated_intrinsic_target_by_op_name(op_name)
-}
-
-pub fn generated_intrinsic_target_is_direct_dialect_candidate(
-    target: &GeneratedIntrinsicTarget,
-) -> bool {
-    !matches!(
-        target.variant,
-        GeneratedIntrinsicVariant::Tcgen05Mma {
-            compatibility_alias: true,
-            ..
-        }
-    )
-}
-
-pub fn generated_intrinsic_operation_matches(
-    ctx: &Context,
-    target: &GeneratedIntrinsicTarget,
-    operation: Ptr<Operation>,
-) -> bool {
-    match target.variant {
-        GeneratedIntrinsicVariant::Scalar => true,
-        GeneratedIntrinsicVariant::Tcgen05Mma {
-            form,
-            target_selector,
-            compatibility_alias,
-        } => {
-            let Some(op) = Operation::get_op::<Tcgen05MmaOp>(operation, ctx) else {
-                return false;
-            };
-            let form_matches = match form {
-                GeneratedTcgen05MmaForm::Shared => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::Shared)
-                }
-                GeneratedTcgen05MmaForm::Tensor => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::Tensor)
-                }
-                GeneratedTcgen05MmaForm::TensorAshift => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::TensorAshift)
-                }
-                GeneratedTcgen05MmaForm::SpShared => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::SpShared)
-                }
-                GeneratedTcgen05MmaForm::SpTensor => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::SpTensor)
-                }
-                GeneratedTcgen05MmaForm::SpTensorAshift => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::SpTensorAshift)
-                }
-                GeneratedTcgen05MmaForm::WsShared => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::WsShared)
-                }
-                GeneratedTcgen05MmaForm::WsSharedZeroColMask => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::WsSharedZeroColMask)
-                }
-                GeneratedTcgen05MmaForm::WsSpShared => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::WsSpShared)
-                }
-                GeneratedTcgen05MmaForm::WsSpSharedZeroColMask => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::WsSpSharedZeroColMask)
-                }
-                GeneratedTcgen05MmaForm::WsSpTensor => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::WsSpTensor)
-                }
-                GeneratedTcgen05MmaForm::WsSpTensorZeroColMask => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::WsSpTensorZeroColMask)
-                }
-                GeneratedTcgen05MmaForm::WsTensor => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::WsTensor)
-                }
-                GeneratedTcgen05MmaForm::WsTensorZeroColMask => {
-                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
-                        == Some(&Tcgen05MmaFormAttr::WsTensorZeroColMask)
-                }
-            };
-            let selector_matches =
-                matches!(target_selector, GeneratedTcgen05MmaTargetSelector::Kind)
-                    && op.get_attr_nvvm_tcgen05_mma_kind(ctx).is_some();
-            let alias_matches = !compatibility_alias
-                || (op.get_attr_nvvm_tcgen05_mma_kind(ctx).as_deref()
-                    == Some(&Tcgen05MmaKindAttr::F8f6f4)
-                    && match form {
-                        GeneratedTcgen05MmaForm::Shared => {
-                            op.get_attr_nvvm_tcgen05_mma_cta_group(ctx).as_deref()
-                                == Some(&Tcgen05MmaCtaGroupAttr::Cg1)
-                                && op.get_attr_nvvm_tcgen05_mma_collector_a(ctx).as_deref()
-                                    == Some(&Tcgen05MmaCollectorAAttr::Discard)
-                        }
-                        GeneratedTcgen05MmaForm::WsTensor => {
-                            op.get_attr_nvvm_tcgen05_mma_b_buffer(ctx).as_deref()
-                                == Some(&Tcgen05MmaBBufferAttr::B0)
-                                && op.get_attr_nvvm_tcgen05_mma_b_usage(ctx).as_deref()
-                                    == Some(&Tcgen05MmaBUsageAttr::Discard)
-                        }
-                        _ => false,
-                    });
-            form_matches && selector_matches && alias_matches
-        }
-        GeneratedIntrinsicVariant::Ldmatrix {
-            shape,
-            multiplicity,
-            layout,
-            element,
-        } => {
-            let operation_name = Operation::get_opid(operation, ctx).to_string();
-            if let Some(marker) =
-                generated_intrinsic_compatibility_marker_by_op_name(&operation_name)
-            {
-                return marker == target.marker;
-            }
-            let Some(op) = Operation::get_op::<LdmatrixOp>(operation, ctx) else {
-                return false;
-            };
-            let shape_matches = match shape {
-                GeneratedLdmatrixShape::M8n8 => {
-                    op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref()
-                        == Some(&LdmatrixShapeAttr::M8n8)
-                }
-                GeneratedLdmatrixShape::M8n16 => {
-                    op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref()
-                        == Some(&LdmatrixShapeAttr::M8n16)
-                }
-                GeneratedLdmatrixShape::M16n16 => {
-                    op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref()
-                        == Some(&LdmatrixShapeAttr::M16n16)
-                }
-            };
-            let multiplicity_matches = match multiplicity {
-                GeneratedLdmatrixMultiplicity::X1 => {
-                    op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref()
-                        == Some(&LdmatrixMultiplicityAttr::X1)
-                }
-                GeneratedLdmatrixMultiplicity::X2 => {
-                    op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref()
-                        == Some(&LdmatrixMultiplicityAttr::X2)
-                }
-                GeneratedLdmatrixMultiplicity::X4 => {
-                    op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref()
-                        == Some(&LdmatrixMultiplicityAttr::X4)
-                }
-            };
-            let layout_matches = match layout {
-                GeneratedLdmatrixLayout::Normal => {
-                    op.get_attr_nvvm_ldmatrix_layout(ctx).as_deref()
-                        == Some(&LdmatrixLayoutAttr::Normal)
-                }
-                GeneratedLdmatrixLayout::Transposed => {
-                    op.get_attr_nvvm_ldmatrix_layout(ctx).as_deref()
-                        == Some(&LdmatrixLayoutAttr::Transposed)
-                }
-            };
-            let element_matches = match element {
-                GeneratedLdmatrixElement::B16 => {
-                    op.get_attr_nvvm_ldmatrix_element(ctx).as_deref()
-                        == Some(&LdmatrixElementAttr::B16)
-                }
-                GeneratedLdmatrixElement::B8 => {
-                    op.get_attr_nvvm_ldmatrix_element(ctx).as_deref()
-                        == Some(&LdmatrixElementAttr::B8)
-                }
-                GeneratedLdmatrixElement::B8x16B4x16P64 => {
-                    op.get_attr_nvvm_ldmatrix_element(ctx).as_deref()
-                        == Some(&LdmatrixElementAttr::B8x16B4x16P64)
-                }
-                GeneratedLdmatrixElement::B8x16B6x16P32 => {
-                    op.get_attr_nvvm_ldmatrix_element(ctx).as_deref()
-                        == Some(&LdmatrixElementAttr::B8x16B6x16P32)
-                }
-            };
-            shape_matches
-                && multiplicity_matches
-                && layout_matches
-                && element_matches
-                && op.get_attr_nvvm_ldmatrix_state_space(ctx).as_deref()
-                    == Some(&LdmatrixStateSpaceAttr::Shared)
-        }
-        GeneratedIntrinsicVariant::PackedAtomic { format } => {
-            let Some(op) = Operation::get_op::<PackedAtomicAddOp>(operation, ctx) else {
-                return false;
-            };
-            let format_matches = match format {
-                GeneratedPackedAtomicFormat::F16x2 => {
-                    op.get_attr_nvvm_packed_atomic_format(ctx).as_deref()
-                        == Some(&PackedAtomicFormatAttr::F16x2)
-                }
-                GeneratedPackedAtomicFormat::Bf16x2 => {
-                    op.get_attr_nvvm_packed_atomic_format(ctx).as_deref()
-                        == Some(&PackedAtomicFormatAttr::Bf16x2)
-                }
-            };
-            format_matches
-                && op.get_attr_nvvm_packed_atomic_state_space(ctx).as_deref()
-                    == Some(&PackedAtomicStateSpaceAttr::Global)
-                && op.get_attr_nvvm_packed_atomic_ordering(ctx).as_deref()
-                    == Some(&PackedAtomicOrderingAttr::Relaxed)
-                && op.get_attr_nvvm_packed_atomic_scope(ctx).as_deref()
-                    == Some(&PackedAtomicScopeAttr::Gpu)
-                && op.get_attr_nvvm_packed_atomic_rounding(ctx).as_deref()
-                    == Some(&PackedAtomicRoundingAttr::Rn)
-                && op.get_attr_nvvm_packed_atomic_subnormal(ctx).as_deref()
-                    == Some(&PackedAtomicSubnormalAttr::NoFtz)
-                && op.get_attr_nvvm_packed_atomic_atomicity(ctx).as_deref()
-                    == Some(&PackedAtomicAtomicityAttr::PerElement)
-        }
-        GeneratedIntrinsicVariant::RegisterMma {
-            shape,
-            operation: mma_operation,
-            kind,
-            accumulator,
-            a_element,
-            b_element,
-            a_layout,
-            b_layout,
-            overflow,
-        } => {
-            let Some(op) = Operation::get_op::<RegisterMmaOp>(operation, ctx) else {
-                return false;
-            };
-            let shape_matches = match shape {
-                GeneratedRegisterMmaShape::M8n8k4 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M8n8k4)
-                }
-                GeneratedRegisterMmaShape::M8n8k16 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M8n8k16)
-                }
-                GeneratedRegisterMmaShape::M8n8k32 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M8n8k32)
-                }
-                GeneratedRegisterMmaShape::M8n8k128 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M8n8k128)
-                }
-                GeneratedRegisterMmaShape::M16n8k4 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M16n8k4)
-                }
-                GeneratedRegisterMmaShape::M16n8k8 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M16n8k8)
-                }
-                GeneratedRegisterMmaShape::M16n8k16 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M16n8k16)
-                }
-                GeneratedRegisterMmaShape::M16n8k32 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M16n8k32)
-                }
-                GeneratedRegisterMmaShape::M16n8k64 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M16n8k64)
-                }
-                GeneratedRegisterMmaShape::M16n8k128 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M16n8k128)
-                }
-                GeneratedRegisterMmaShape::M16n8k256 => {
-                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
-                        == Some(&RegisterMmaShapeAttr::M16n8k256)
-                }
-            };
-            let operation_matches = match mma_operation {
-                GeneratedRegisterMmaOperation::Multiply => {
-                    op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::Multiply
-                }
-                GeneratedRegisterMmaOperation::AndPopc => {
-                    op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::AndPopc
-                }
-                GeneratedRegisterMmaOperation::XorPopc => {
-                    op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::XorPopc
-                }
-            };
-            let kind_matches = match kind {
-                GeneratedRegisterMmaKind::Standard => {
-                    op.kind_or_inferred(ctx) == RegisterMmaKindAttr::Standard
-                }
-                GeneratedRegisterMmaKind::F8f6f4 => {
-                    op.kind_or_inferred(ctx) == RegisterMmaKindAttr::F8f6f4
-                }
-                GeneratedRegisterMmaKind::Mxf8f6f4 => {
-                    op.kind_or_inferred(ctx) == RegisterMmaKindAttr::Mxf8f6f4
-                }
-            };
-            let accumulator_matches = match accumulator {
-                GeneratedRegisterMmaAccumulator::F16 => {
-                    op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref()
-                        == Some(&RegisterMmaAccumulatorAttr::F16)
-                }
-                GeneratedRegisterMmaAccumulator::F32 => {
-                    op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref()
-                        == Some(&RegisterMmaAccumulatorAttr::F32)
-                }
-                GeneratedRegisterMmaAccumulator::F64 => {
-                    op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref()
-                        == Some(&RegisterMmaAccumulatorAttr::F64)
-                }
-                GeneratedRegisterMmaAccumulator::S32 => {
-                    op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref()
-                        == Some(&RegisterMmaAccumulatorAttr::S32)
-                }
-            };
-            let element_matches = |expected, actual: Option<&RegisterMmaElementAttr>| match expected
-            {
-                GeneratedRegisterMmaElement::Bf16 => actual == Some(&RegisterMmaElementAttr::Bf16),
-                GeneratedRegisterMmaElement::F16 => actual == Some(&RegisterMmaElementAttr::F16),
-                GeneratedRegisterMmaElement::Tf32 => actual == Some(&RegisterMmaElementAttr::Tf32),
-                GeneratedRegisterMmaElement::F64 => actual == Some(&RegisterMmaElementAttr::F64),
-                GeneratedRegisterMmaElement::E2m1 => actual == Some(&RegisterMmaElementAttr::E2m1),
-                GeneratedRegisterMmaElement::E2m3 => actual == Some(&RegisterMmaElementAttr::E2m3),
-                GeneratedRegisterMmaElement::E3m2 => actual == Some(&RegisterMmaElementAttr::E3m2),
-                GeneratedRegisterMmaElement::E4m3 => actual == Some(&RegisterMmaElementAttr::E4m3),
-                GeneratedRegisterMmaElement::E5m2 => actual == Some(&RegisterMmaElementAttr::E5m2),
-                GeneratedRegisterMmaElement::B1 => actual == Some(&RegisterMmaElementAttr::B1),
-                GeneratedRegisterMmaElement::S4 => actual == Some(&RegisterMmaElementAttr::S4),
-                GeneratedRegisterMmaElement::U4 => actual == Some(&RegisterMmaElementAttr::U4),
-                GeneratedRegisterMmaElement::S8 => actual == Some(&RegisterMmaElementAttr::S8),
-                GeneratedRegisterMmaElement::U8 => actual == Some(&RegisterMmaElementAttr::U8),
-            };
-            let layout_matches = |expected, actual: Option<&RegisterMmaLayoutAttr>| match expected {
-                GeneratedRegisterMmaLayout::Row => actual == Some(&RegisterMmaLayoutAttr::Row),
-                GeneratedRegisterMmaLayout::Col => actual == Some(&RegisterMmaLayoutAttr::Col),
-            };
-            let overflow_matches = match overflow {
-                GeneratedRegisterMmaOverflow::NotApplicable => {
-                    op.get_attr_nvvm_register_mma_overflow(ctx).as_deref()
-                        == Some(&RegisterMmaOverflowAttr::NotApplicable)
-                }
-                GeneratedRegisterMmaOverflow::Wrapping => {
-                    op.get_attr_nvvm_register_mma_overflow(ctx).as_deref()
-                        == Some(&RegisterMmaOverflowAttr::Wrapping)
-                }
-                GeneratedRegisterMmaOverflow::Satfinite => {
-                    op.get_attr_nvvm_register_mma_overflow(ctx).as_deref()
-                        == Some(&RegisterMmaOverflowAttr::Satfinite)
-                }
-            };
-            shape_matches
-                && operation_matches
-                && kind_matches
-                && accumulator_matches
-                && element_matches(
-                    a_element,
-                    op.get_attr_nvvm_register_mma_a_element(ctx).as_deref(),
-                )
-                && element_matches(
-                    b_element,
-                    op.get_attr_nvvm_register_mma_b_element(ctx).as_deref(),
-                )
-                && layout_matches(
-                    a_layout,
-                    op.get_attr_nvvm_register_mma_a_layout(ctx).as_deref(),
-                )
-                && layout_matches(
-                    b_layout,
-                    op.get_attr_nvvm_register_mma_b_layout(ctx).as_deref(),
-                )
-                && overflow_matches
-        }
-        GeneratedIntrinsicVariant::SparseMma {
-            shape,
-            accumulator,
-            a_element,
-            b_element,
-            a_layout,
-            b_layout,
-            overflow,
-            metadata,
-            selector,
-        } => {
-            let Some(op) = Operation::get_op::<SparseMmaOp>(operation, ctx) else {
-                return false;
-            };
-            let element_matches = |expected, actual: Option<&SparseMmaElementAttr>| match expected {
-                GeneratedSparseMmaElement::E2m1 => actual == Some(&SparseMmaElementAttr::E2m1),
-                GeneratedSparseMmaElement::E2m3 => actual == Some(&SparseMmaElementAttr::E2m3),
-                GeneratedSparseMmaElement::E3m2 => actual == Some(&SparseMmaElementAttr::E3m2),
-                GeneratedSparseMmaElement::E4m3 => actual == Some(&SparseMmaElementAttr::E4m3),
-                GeneratedSparseMmaElement::E5m2 => actual == Some(&SparseMmaElementAttr::E5m2),
-                GeneratedSparseMmaElement::S4 => actual == Some(&SparseMmaElementAttr::S4),
-                GeneratedSparseMmaElement::U4 => actual == Some(&SparseMmaElementAttr::U4),
-                GeneratedSparseMmaElement::S8 => actual == Some(&SparseMmaElementAttr::S8),
-                GeneratedSparseMmaElement::U8 => actual == Some(&SparseMmaElementAttr::U8),
-            };
-            let layout_matches = |expected, actual: Option<&SparseMmaLayoutAttr>| match expected {
-                GeneratedSparseMmaLayout::Row => actual == Some(&SparseMmaLayoutAttr::Row),
-                GeneratedSparseMmaLayout::Col => actual == Some(&SparseMmaLayoutAttr::Col),
-            };
-            let overflow_matches = match overflow {
-                GeneratedSparseMmaOverflow::NotApplicable => {
-                    op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref()
-                        == Some(&SparseMmaOverflowAttr::NotApplicable)
-                }
-                GeneratedSparseMmaOverflow::Wrapping => {
-                    op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref()
-                        == Some(&SparseMmaOverflowAttr::Wrapping)
-                }
-                GeneratedSparseMmaOverflow::Satfinite => {
-                    op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref()
-                        == Some(&SparseMmaOverflowAttr::Satfinite)
-                }
-            };
-            let metadata_matches = match metadata {
-                GeneratedSparseMmaMetadata::Standard => {
-                    op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref()
-                        == Some(&SparseMmaMetadataAttr::Standard)
-                }
-                GeneratedSparseMmaMetadata::Ordered => {
-                    op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref()
-                        == Some(&SparseMmaMetadataAttr::Ordered)
-                }
-            };
-            let shape_matches = match shape {
-                GeneratedSparseMmaShape::M16n8k32 => {
-                    op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref()
-                        == Some(&SparseMmaShapeAttr::M16n8k32)
-                }
-                GeneratedSparseMmaShape::M16n8k64 => {
-                    op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref()
-                        == Some(&SparseMmaShapeAttr::M16n8k64)
-                }
-                GeneratedSparseMmaShape::M16n8k128 => {
-                    op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref()
-                        == Some(&SparseMmaShapeAttr::M16n8k128)
-                }
-            };
-            let accumulator_matches = match accumulator {
-                GeneratedSparseMmaAccumulator::F16 => {
-                    op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref()
-                        == Some(&SparseMmaAccumulatorAttr::F16)
-                }
-                GeneratedSparseMmaAccumulator::F32 => {
-                    op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref()
-                        == Some(&SparseMmaAccumulatorAttr::F32)
-                }
-                GeneratedSparseMmaAccumulator::S32 => {
-                    op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref()
-                        == Some(&SparseMmaAccumulatorAttr::S32)
-                }
-            };
-            let selector_matches = match selector {
-                GeneratedSparseMmaSelector::ImmediateZeroOrOne => {
-                    op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref()
-                        == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne)
-                }
-                GeneratedSparseMmaSelector::ImmediateZero => {
-                    op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref()
-                        == Some(&SparseMmaSelectorAttr::ImmediateZero)
-                }
-            };
-            shape_matches
-                && accumulator_matches
-                && element_matches(
-                    a_element,
-                    op.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref(),
-                )
-                && element_matches(
-                    b_element,
-                    op.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref(),
-                )
-                && layout_matches(
-                    a_layout,
-                    op.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref(),
-                )
-                && layout_matches(
-                    b_layout,
-                    op.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref(),
-                )
-                && overflow_matches
-                && metadata_matches
-                && selector_matches
-        }
-        GeneratedIntrinsicVariant::Prmt { mode } => {
-            let Some(op) = Operation::get_op::<PrmtOp>(operation, ctx) else {
-                return false;
-            };
-            match mode {
-                GeneratedPrmtMode::Generic => {
-                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Generic)
-                }
-                GeneratedPrmtMode::F4e => {
-                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::F4e)
-                }
-                GeneratedPrmtMode::B4e => {
-                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::B4e)
-                }
-                GeneratedPrmtMode::Rc8 => {
-                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Rc8)
-                }
-                GeneratedPrmtMode::Ecl => {
-                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Ecl)
-                }
-                GeneratedPrmtMode::Ecr => {
-                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Ecr)
-                }
-                GeneratedPrmtMode::Rc16 => {
-                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Rc16)
-                }
-            }
-        }
-        GeneratedIntrinsicVariant::ClusterBarrier { mode } => {
-            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else {
-                return false;
-            };
-            match mode {
-                GeneratedClusterBarrierMode::Arrive => {
-                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
-                        == Some(&ClusterBarrierModeAttr::Arrive)
-                }
-                GeneratedClusterBarrierMode::ArriveAligned => {
-                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
-                        == Some(&ClusterBarrierModeAttr::ArriveAligned)
-                }
-                GeneratedClusterBarrierMode::ArriveRelaxed => {
-                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
-                        == Some(&ClusterBarrierModeAttr::ArriveRelaxed)
-                }
-                GeneratedClusterBarrierMode::ArriveRelaxedAligned => {
-                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
-                        == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned)
-                }
-                GeneratedClusterBarrierMode::Wait => {
-                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
-                        == Some(&ClusterBarrierModeAttr::Wait)
-                }
-                GeneratedClusterBarrierMode::WaitAligned => {
-                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
-                        == Some(&ClusterBarrierModeAttr::WaitAligned)
-                }
-            }
-        }
-        GeneratedIntrinsicVariant::WgmmaControl { mode } => match mode {
-            GeneratedWgmmaControlMode::Fence => {
-                Operation::get_op::<WgmmaFenceSyncAlignedOp>(operation, ctx).is_some()
-            }
-            GeneratedWgmmaControlMode::CommitGroup => {
-                Operation::get_op::<WgmmaCommitGroupSyncAlignedOp>(operation, ctx).is_some()
-            }
-            GeneratedWgmmaControlMode::WaitGroup => {
-                Operation::get_op::<WgmmaWaitGroupSyncAlignedOp>(operation, ctx).is_some()
-            }
-        },
-        GeneratedIntrinsicVariant::ScalarConversion {
-            rounding,
-            saturation,
-        } => {
-            let Some(op) = Operation::get_op::<ScalarConversionOp>(operation, ctx) else {
-                return false;
-            };
-            let rounding_matches = match rounding {
-                GeneratedScalarConversionRounding::NearestAway => {
-                    op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref()
-                        == Some(&ScalarConversionRoundingAttr::NearestAway)
-                }
-                GeneratedScalarConversionRounding::NearestEven => {
-                    op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref()
-                        == Some(&ScalarConversionRoundingAttr::NearestEven)
-                }
-                GeneratedScalarConversionRounding::TowardZero => {
-                    op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref()
-                        == Some(&ScalarConversionRoundingAttr::TowardZero)
-                }
-            };
-            let saturation_matches = match saturation {
-                GeneratedScalarConversionSaturation::None => {
-                    op.get_attr_nvvm_scalar_conversion_saturation(ctx)
-                        .as_deref()
-                        == Some(&ScalarConversionSaturationAttr::None)
-                }
-                GeneratedScalarConversionSaturation::Relu => {
-                    op.get_attr_nvvm_scalar_conversion_saturation(ctx)
-                        .as_deref()
-                        == Some(&ScalarConversionSaturationAttr::Relu)
-                }
-                GeneratedScalarConversionSaturation::Satfinite => {
-                    op.get_attr_nvvm_scalar_conversion_saturation(ctx)
-                        .as_deref()
-                        == Some(&ScalarConversionSaturationAttr::Satfinite)
-                }
-                GeneratedScalarConversionSaturation::ReluSatfinite => {
-                    op.get_attr_nvvm_scalar_conversion_saturation(ctx)
-                        .as_deref()
-                        == Some(&ScalarConversionSaturationAttr::ReluSatfinite)
-                }
-            };
-            rounding_matches && saturation_matches
-        }
-        GeneratedIntrinsicVariant::ScalarArithmetic {
-            format,
-            operation: arithmetic_operation,
-            rounding,
-            subnormal,
-            saturation,
-        } => {
-            let Some(op) = Operation::get_op::<ScalarArithmeticOp>(operation, ctx) else {
-                return false;
-            };
-            let format_matches = match format {
-                GeneratedScalarArithmeticFormat::F32 => {
-                    op.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref()
-                        == Some(&ScalarArithmeticFormatAttr::F32)
-                }
-                GeneratedScalarArithmeticFormat::F64 => {
-                    op.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref()
-                        == Some(&ScalarArithmeticFormatAttr::F64)
-                }
-            };
-            let operation_matches = match arithmetic_operation {
-                GeneratedScalarArithmeticOperation::Mul => {
-                    op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref()
-                        == Some(&ScalarArithmeticOperationAttr::Mul)
-                }
-                GeneratedScalarArithmeticOperation::Div => {
-                    op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref()
-                        == Some(&ScalarArithmeticOperationAttr::Div)
-                }
-                GeneratedScalarArithmeticOperation::Fma => {
-                    op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref()
-                        == Some(&ScalarArithmeticOperationAttr::Fma)
-                }
-                GeneratedScalarArithmeticOperation::Add => {
-                    op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref()
-                        == Some(&ScalarArithmeticOperationAttr::Add)
-                }
-            };
-            let rounding_matches = match rounding {
-                GeneratedScalarArithmeticRounding::Rn => {
-                    op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref()
-                        == Some(&ScalarArithmeticRoundingAttr::Rn)
-                }
-                GeneratedScalarArithmeticRounding::Rz => {
-                    op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref()
-                        == Some(&ScalarArithmeticRoundingAttr::Rz)
-                }
-                GeneratedScalarArithmeticRounding::Rm => {
-                    op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref()
-                        == Some(&ScalarArithmeticRoundingAttr::Rm)
-                }
-                GeneratedScalarArithmeticRounding::Rp => {
-                    op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref()
-                        == Some(&ScalarArithmeticRoundingAttr::Rp)
-                }
-            };
-            let subnormal_matches = match subnormal {
-                GeneratedScalarArithmeticSubnormal::Preserve => {
-                    op.get_attr_nvvm_scalar_arithmetic_subnormal(ctx).as_deref()
-                        == Some(&ScalarArithmeticSubnormalAttr::Preserve)
-                }
-                GeneratedScalarArithmeticSubnormal::Ftz => {
-                    op.get_attr_nvvm_scalar_arithmetic_subnormal(ctx).as_deref()
-                        == Some(&ScalarArithmeticSubnormalAttr::Ftz)
-                }
-            };
-            let saturation_matches = match saturation {
-                GeneratedScalarArithmeticSaturation::None => {
-                    op.get_attr_nvvm_scalar_arithmetic_saturation(ctx)
-                        .as_deref()
-                        == Some(&ScalarArithmeticSaturationAttr::None)
-                }
-                GeneratedScalarArithmeticSaturation::Sat => {
-                    op.get_attr_nvvm_scalar_arithmetic_saturation(ctx)
-                        .as_deref()
-                        == Some(&ScalarArithmeticSaturationAttr::Sat)
-                }
-            };
-            format_matches
-                && operation_matches
-                && rounding_matches
-                && subnormal_matches
-                && saturation_matches
-        }
-        GeneratedIntrinsicVariant::ExtendedMinMax {
-            format,
-            operation: minmax_operation,
-            subnormal,
-            nan,
-            xorsign_abs,
-        } => {
-            let Some(op) = Operation::get_op::<ExtendedMinMaxOp>(operation, ctx) else {
-                return false;
-            };
-            let format_matches = match format {
-                GeneratedExtendedMinMaxFormat::F32 => {
-                    op.get_attr_nvvm_extended_minmax_format(ctx).as_deref()
-                        == Some(&ExtendedMinMaxFormatAttr::F32)
-                }
-                GeneratedExtendedMinMaxFormat::F16 => {
-                    op.get_attr_nvvm_extended_minmax_format(ctx).as_deref()
-                        == Some(&ExtendedMinMaxFormatAttr::F16)
-                }
-                GeneratedExtendedMinMaxFormat::Bf16 => {
-                    op.get_attr_nvvm_extended_minmax_format(ctx).as_deref()
-                        == Some(&ExtendedMinMaxFormatAttr::Bf16)
-                }
-                GeneratedExtendedMinMaxFormat::F16x2 => {
-                    op.get_attr_nvvm_extended_minmax_format(ctx).as_deref()
-                        == Some(&ExtendedMinMaxFormatAttr::F16x2)
-                }
-                GeneratedExtendedMinMaxFormat::Bf16x2 => {
-                    op.get_attr_nvvm_extended_minmax_format(ctx).as_deref()
-                        == Some(&ExtendedMinMaxFormatAttr::Bf16x2)
-                }
-            };
-            let operation_matches = match minmax_operation {
-                GeneratedExtendedMinMaxOperation::Min => {
-                    op.get_attr_nvvm_extended_minmax_operation(ctx).as_deref()
-                        == Some(&ExtendedMinMaxOperationAttr::Min)
-                }
-                GeneratedExtendedMinMaxOperation::Max => {
-                    op.get_attr_nvvm_extended_minmax_operation(ctx).as_deref()
-                        == Some(&ExtendedMinMaxOperationAttr::Max)
-                }
-            };
-            let subnormal_matches = match subnormal {
-                GeneratedExtendedMinMaxSubnormal::Preserve => {
-                    op.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref()
-                        == Some(&ExtendedMinMaxSubnormalAttr::Preserve)
-                }
-                GeneratedExtendedMinMaxSubnormal::Ftz => {
-                    op.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref()
-                        == Some(&ExtendedMinMaxSubnormalAttr::Ftz)
-                }
-            };
-            let nan_matches = match nan {
-                GeneratedExtendedMinMaxNan::Number => {
-                    op.get_attr_nvvm_extended_minmax_nan(ctx).as_deref()
-                        == Some(&ExtendedMinMaxNanAttr::Number)
-                }
-                GeneratedExtendedMinMaxNan::Nan => {
-                    op.get_attr_nvvm_extended_minmax_nan(ctx).as_deref()
-                        == Some(&ExtendedMinMaxNanAttr::Nan)
-                }
-            };
-            let xorsign_abs_matches = match xorsign_abs {
-                false => {
-                    op.get_attr_nvvm_extended_minmax_xorsign_abs(ctx).as_deref()
-                        == Some(&ExtendedMinMaxXorSignAbsAttr::Disabled)
-                }
-                true => {
-                    op.get_attr_nvvm_extended_minmax_xorsign_abs(ctx).as_deref()
-                        == Some(&ExtendedMinMaxXorSignAbsAttr::Enabled)
-                }
-            };
-            format_matches
-                && operation_matches
-                && subnormal_matches
-                && nan_matches
-                && xorsign_abs_matches
-        }
-    }
-}
-
-use dialect_nvvm::ops::{
-    ClusterBarrierModeAttr, ClusterBarrierOp, ExtendedMinMaxFormatAttr, ExtendedMinMaxNanAttr,
-    ExtendedMinMaxOp, ExtendedMinMaxOperationAttr, ExtendedMinMaxSubnormalAttr,
-    ExtendedMinMaxXorSignAbsAttr, LdmatrixElementAttr, LdmatrixLayoutAttr,
-    LdmatrixMultiplicityAttr, LdmatrixOp, LdmatrixShapeAttr, LdmatrixStateSpaceAttr,
-    PackedAtomicAddOp, PackedAtomicAtomicityAttr, PackedAtomicFormatAttr, PackedAtomicOrderingAttr,
-    PackedAtomicRoundingAttr, PackedAtomicScopeAttr, PackedAtomicStateSpaceAttr,
-    PackedAtomicSubnormalAttr, PrmtModeAttr, PrmtOp, RegisterMmaAccumulatorAttr,
-    RegisterMmaElementAttr, RegisterMmaKindAttr, RegisterMmaLayoutAttr, RegisterMmaOp,
-    RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr,
-    ScalarArithmeticFormatAttr, ScalarArithmeticOp, ScalarArithmeticOperationAttr,
-    ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr,
-    ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr,
-    SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr,
-    SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr,
-    Tcgen05MmaBBufferAttr, Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr,
-    Tcgen05MmaFormAttr, Tcgen05MmaKindAttr, Tcgen05MmaOp, WgmmaCommitGroupSyncAlignedOp,
-    WgmmaFenceSyncAlignedOp, WgmmaWaitGroupSyncAlignedOp,
-};
-use pliron::{
-    context::{Context, Ptr},
-    operation::Operation,
-};
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use std::collections::BTreeSet;
-
-    #[test]
-    fn generated_target_table_is_unique_and_lookup_is_complete() {
-        let mut ids = BTreeSet::new();
-        let mut markers = BTreeSet::new();
-        let mut previous_abi_id = None;
-        for target in GENERATED_INTRINSIC_TARGETS {
-            if let Some(previous) = previous_abi_id {
-                assert!(
-                    previous < target.abi_id,
-                    "generated ABI IDs are not strictly increasing: {previous} then {}",
-                    target.abi_id
-                );
-            }
-            previous_abi_id = Some(target.abi_id);
-            assert!(
-                ids.insert(target.id),
-                "duplicate generated intrinsic ID {}",
-                target.id
-            );
-            assert!(
-                markers.insert(target.marker),
-                "duplicate generated marker {}",
-                target.marker
-            );
-            assert_eq!(
-                generated_intrinsic_target_by_marker(target.marker),
-                Some(target)
-            );
-            assert!(
-                generated_intrinsic_targets_by_op_name(target.dialect_op)
-                    .any(|candidate| candidate == target)
-            );
-        }
-        let target = generated_intrinsic_target_by_marker("v1:i0001").unwrap();
-        assert_eq!(target.id, "thread_idx_x");
-        assert_eq!(target.abi_id, "i0001");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_tid_x");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_TID_x",
-                asm: "mov.u32 \t$d, %tid.x;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,1024>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0002").unwrap();
-        assert_eq!(target.id, "block_idx_x");
-        assert_eq!(target.abi_id, "i0002");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ctaid_x");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CTAID_x",
-                asm: "mov.u32 \t$d, %ctaid.x;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,2147483647>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0003").unwrap();
-        assert_eq!(target.id, "block_dim_x");
-        assert_eq!(target.abi_id, "i0003");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ntid_x");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_NTID_x",
-                asm: "mov.u32 \t$d, %ntid.x;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,1025>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0004").unwrap();
-        assert_eq!(target.id, "grid_dim_x");
-        assert_eq!(target.abi_id, "i0004");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nctaid_x");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_NCTAID_x",
-                asm: "mov.u32 \t$d, %nctaid.x;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,2147483648>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0005").unwrap();
-        assert_eq!(target.id, "thread_idx_y");
-        assert_eq!(target.abi_id, "i0005");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_tid_y");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_TID_y",
-                asm: "mov.u32 \t$d, %tid.y;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,1024>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0006").unwrap();
-        assert_eq!(target.id, "block_idx_y");
-        assert_eq!(target.abi_id, "i0006");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ctaid_y");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CTAID_y",
-                asm: "mov.u32 \t$d, %ctaid.y;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0007").unwrap();
-        assert_eq!(target.id, "block_dim_y");
-        assert_eq!(target.abi_id, "i0007");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ntid_y");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_NTID_y",
-                asm: "mov.u32 \t$d, %ntid.y;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,1025>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0008").unwrap();
-        assert_eq!(target.id, "grid_dim_y");
-        assert_eq!(target.abi_id, "i0008");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nctaid_y");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_NCTAID_y",
-                asm: "mov.u32 \t$d, %nctaid.y;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0009").unwrap();
-        assert_eq!(target.id, "thread_idx_z");
-        assert_eq!(target.abi_id, "i0009");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_tid_z");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_TID_z",
-                asm: "mov.u32 \t$d, %tid.z;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,64>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0010").unwrap();
-        assert_eq!(target.id, "block_idx_z");
-        assert_eq!(target.abi_id, "i0010");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ctaid_z");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CTAID_z",
-                asm: "mov.u32 \t$d, %ctaid.z;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0011").unwrap();
-        assert_eq!(target.id, "block_dim_z");
-        assert_eq!(target.abi_id, "i0011");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ntid_z");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_NTID_z",
-                asm: "mov.u32 \t$d, %ntid.z;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0012").unwrap();
-        assert_eq!(target.id, "grid_dim_z");
-        assert_eq!(target.abi_id, "i0012");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nctaid_z");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_NCTAID_z",
-                asm: "mov.u32 \t$d, %nctaid.z;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0013").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n8_x4_b16");
-        assert_eq!(target.abi_id, "i0013");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n8,
-                multiplicity: GeneratedLdmatrixMultiplicity::X4,
-                layout: GeneratedLdmatrixLayout::Normal,
-                element: GeneratedLdmatrixElement::B16
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20697",
-                asm: "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0014").unwrap();
-        assert_eq!(target.id, "packed_atomic_add_f16x2");
-        assert_eq!(target.abi_id, "i0014");
-        assert_eq!(target.dialect_op, "nvvm.packed_atomic_add");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::PackedAtomic {
-                format: GeneratedPackedAtomicFormat::F16x2
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 62);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(62),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(62),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0015").unwrap();
-        assert_eq!(target.id, "packed_atomic_add_bf16x2");
-        assert_eq!(target.abi_id, "i0015");
-        assert_eq!(target.dialect_op, "nvvm.packed_atomic_add");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::PackedAtomic {
-                format: GeneratedPackedAtomicFormat::Bf16x2
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0016").unwrap();
-        assert_eq!(target.id, "lane_id");
-        assert_eq!(target.abi_id, "i0016");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_laneid");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 13);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "SREG_LANEID",
-                asm: "mov.u32 \t$d, %laneid;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,32>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0017").unwrap();
-        assert_eq!(target.id, "redux_sync_add");
-        assert_eq!(target.abi_id, "i0017");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_add");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15029",
-                asm: "redux.sync.add.s32 \t$dst, $src, $mask;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0018").unwrap();
-        assert_eq!(target.id, "redux_sync_min_u32");
-        assert_eq!(target.abi_id, "i0018");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_umin");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15027",
-                asm: "redux.sync.min.u32 \t$dst, $src, $mask;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0019").unwrap();
-        assert_eq!(target.id, "redux_sync_min_i32");
-        assert_eq!(target.abi_id, "i0019");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_min");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15030",
-                asm: "redux.sync.min.s32 \t$dst, $src, $mask;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0020").unwrap();
-        assert_eq!(target.id, "redux_sync_max_u32");
-        assert_eq!(target.abi_id, "i0020");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_umax");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15028",
-                asm: "redux.sync.max.u32 \t$dst, $src, $mask;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0021").unwrap();
-        assert_eq!(target.id, "redux_sync_max_i32");
-        assert_eq!(target.abi_id, "i0021");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_max");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15031",
-                asm: "redux.sync.max.s32 \t$dst, $src, $mask;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0022").unwrap();
-        assert_eq!(target.id, "redux_sync_and");
-        assert_eq!(target.abi_id, "i0022");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_and");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15032",
-                asm: "redux.sync.and.b32 \t$dst, $src, $mask;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0023").unwrap();
-        assert_eq!(target.id, "redux_sync_or");
-        assert_eq!(target.abi_id, "i0023");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_or");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15034",
-                asm: "redux.sync.or.b32 \t$dst, $src, $mask;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0024").unwrap();
-        assert_eq!(target.id, "redux_sync_xor");
-        assert_eq!(target.abi_id, "i0024");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_xor");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15033",
-                asm: "redux.sync.xor.b32 \t$dst, $src, $mask;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0025").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n8_x1_b16");
-        assert_eq!(target.abi_id, "i0025");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n8,
-                multiplicity: GeneratedLdmatrixMultiplicity::X1,
-                layout: GeneratedLdmatrixLayout::Normal,
-                element: GeneratedLdmatrixElement::B16
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20675",
-                asm: "ldmatrix.sync.aligned.m8n8.x1.shared.b16 {{$rx10}}, [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0026").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n8_x1_trans_b16");
-        assert_eq!(target.abi_id, "i0026");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n8,
-                multiplicity: GeneratedLdmatrixMultiplicity::X1,
-                layout: GeneratedLdmatrixLayout::Transposed,
-                element: GeneratedLdmatrixElement::B16
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20758",
-                asm: "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16 {{$rx10}}, [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0027").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n8_x2_b16");
-        assert_eq!(target.abi_id, "i0027");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n8,
-                multiplicity: GeneratedLdmatrixMultiplicity::X2,
-                layout: GeneratedLdmatrixLayout::Normal,
-                element: GeneratedLdmatrixElement::B16
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20687",
-                asm: "ldmatrix.sync.aligned.m8n8.x2.shared.b16 {{$rx20, $rx21}}, [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0028").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n8_x2_trans_b16");
-        assert_eq!(target.abi_id, "i0028");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n8,
-                multiplicity: GeneratedLdmatrixMultiplicity::X2,
-                layout: GeneratedLdmatrixLayout::Transposed,
-                element: GeneratedLdmatrixElement::B16
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20762",
-                asm: "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16 {{$rx20, $rx21}}, [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0029").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n8_x4_trans_b16");
-        assert_eq!(target.abi_id, "i0029");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n8,
-                multiplicity: GeneratedLdmatrixMultiplicity::X4,
-                layout: GeneratedLdmatrixLayout::Transposed,
-                element: GeneratedLdmatrixElement::B16
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20766",
-                asm: "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0030").unwrap();
-        assert_eq!(target.id, "dp4a_s32");
-        assert_eq!(target.abi_id, "i0030");
-        assert_eq!(target.dialect_op, "nvvm.dp4a_s32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 50);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(61)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(61),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "DOT4_ss",
-                asm: "dp4a.s32.s32 \t$dst, $a, $b, $c;",
-                predicates: &["hasDotInstructions"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0031").unwrap();
-        assert_eq!(target.id, "dp4a_u32");
-        assert_eq!(target.abi_id, "i0031");
-        assert_eq!(target.dialect_op, "nvvm.dp4a_u32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 50);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(61)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(61),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "DOT4_uu",
-                asm: "dp4a.u32.u32 \t$dst, $a, $b, $c;",
-                predicates: &["hasDotInstructions"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0032").unwrap();
-        assert_eq!(target.id, "dp2a_s32");
-        assert_eq!(target.abi_id, "i0032");
-        assert_eq!(target.dialect_op, "nvvm.dp2a_s32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 50);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(61)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(61),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "DOT2_lo_ss",
-                asm: "dp2a.lo.s32.s32 \t$dst, $a, $b, $c;",
-                predicates: &["hasDotInstructions"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 2,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0033").unwrap();
-        assert_eq!(target.id, "dp2a_u32");
-        assert_eq!(target.abi_id, "i0033");
-        assert_eq!(target.dialect_op, "nvvm.dp2a_u32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 50);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(61)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(61),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "DOT2_lo_uu",
-                asm: "dp2a.lo.u32.u32 \t$dst, $a, $b, $c;",
-                predicates: &["hasDotInstructions"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 2,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0034").unwrap();
-        assert_eq!(target.id, "sync_threads");
-        assert_eq!(target.abi_id, "i0034");
-        assert_eq!(target.dialect_op, "nvvm.barrier0");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "BARRIER_CTA_SYNC_ALIGNED_ALL_i",
-                asm: "bar.sync \t$i;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0035").unwrap();
-        assert_eq!(target.id, "lanemask_lt");
-        assert_eq!(target.abi_id, "i0035");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_lanemask_lt");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_LANEMASK_LT",
-                asm: "mov.u32 \t$d, %lanemask_lt;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0036").unwrap();
-        assert_eq!(target.id, "lanemask_le");
-        assert_eq!(target.abi_id, "i0036");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_lanemask_le");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_LANEMASK_LE",
-                asm: "mov.u32 \t$d, %lanemask_le;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0037").unwrap();
-        assert_eq!(target.id, "lanemask_eq");
-        assert_eq!(target.abi_id, "i0037");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_lanemask_eq");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_LANEMASK_EQ",
-                asm: "mov.u32 \t$d, %lanemask_eq;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0038").unwrap();
-        assert_eq!(target.id, "lanemask_ge");
-        assert_eq!(target.abi_id, "i0038");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_lanemask_ge");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_LANEMASK_GE",
-                asm: "mov.u32 \t$d, %lanemask_ge;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0039").unwrap();
-        assert_eq!(target.id, "lanemask_gt");
-        assert_eq!(target.abi_id, "i0039");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_lanemask_gt");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_LANEMASK_GT",
-                asm: "mov.u32 \t$d, %lanemask_gt;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0040").unwrap();
-        assert_eq!(target.id, "all_sync");
-        assert_eq!(target.abi_id, "i0040");
-        assert_eq!(target.dialect_op, "nvvm.vote_sync_all");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "VOTE_SYNC_ALLi",
-                    asm: "vote.sync.all.pred \t$dest, $pred, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "VOTE_SYNC_ALLr",
-                    asm: "vote.sync.all.pred \t$dest, $pred, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0041").unwrap();
-        assert_eq!(target.id, "any_sync");
-        assert_eq!(target.abi_id, "i0041");
-        assert_eq!(target.dialect_op, "nvvm.vote_sync_any");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "VOTE_SYNC_ANYi",
-                    asm: "vote.sync.any.pred \t$dest, $pred, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "VOTE_SYNC_ANYr",
-                    asm: "vote.sync.any.pred \t$dest, $pred, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0042").unwrap();
-        assert_eq!(target.id, "ballot_sync");
-        assert_eq!(target.abi_id, "i0042");
-        assert_eq!(target.dialect_op, "nvvm.vote_sync_ballot");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "VOTE_SYNC_BALLOTi",
-                    asm: "vote.sync.ballot.b32 \t$dest, $pred, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "VOTE_SYNC_BALLOTr",
-                    asm: "vote.sync.ballot.b32 \t$dest, $pred, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0043").unwrap();
-        assert_eq!(target.id, "uni_sync");
-        assert_eq!(target.abi_id, "i0043");
-        assert_eq!(target.dialect_op, "nvvm.vote_sync_uni");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "VOTE_SYNC_UNIi",
-                    asm: "vote.sync.uni.pred \t$dest, $pred, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "VOTE_SYNC_UNIr",
-                    asm: "vote.sync.uni.pred \t$dest, $pred, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0044").unwrap();
-        assert_eq!(target.id, "active_mask");
-        assert_eq!(target.abi_id, "i0044");
-        assert_eq!(target.dialect_op, "nvvm.activemask");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 62);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(62),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(62),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "ACTIVEMASK",
-                asm: "activemask.b32 \t$dest;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 30",
-                    "Subtarget->getPTXVersion() >= 62"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrHasSideEffects",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0045").unwrap();
-        assert_eq!(target.id, "match_any_sync");
-        assert_eq!(target.abi_id, "i0045");
-        assert_eq!(target.dialect_op, "nvvm.match_any_sync_i32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ANY_SYNC_32ii",
-                    asm: "match.any.sync.b32 \t$dest, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ANY_SYNC_32ir",
-                    asm: "match.any.sync.b32 \t$dest, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ANY_SYNC_32ri",
-                    asm: "match.any.sync.b32 \t$dest, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ANY_SYNC_32rr",
-                    asm: "match.any.sync.b32 \t$dest, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0046").unwrap();
-        assert_eq!(target.id, "match_any_i64_sync");
-        assert_eq!(target.abi_id, "i0046");
-        assert_eq!(target.dialect_op, "nvvm.match_any_sync_i64");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ANY_SYNC_64ii",
-                    asm: "match.any.sync.b64 \t$dest, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ANY_SYNC_64ir",
-                    asm: "match.any.sync.b64 \t$dest, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ANY_SYNC_64ri",
-                    asm: "match.any.sync.b64 \t$dest, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ANY_SYNC_64rr",
-                    asm: "match.any.sync.b64 \t$dest, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0047").unwrap();
-        assert_eq!(target.id, "match_all_sync");
-        assert_eq!(target.abi_id, "i0047");
-        assert_eq!(target.dialect_op, "nvvm.match_all_sync_i32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ALLP_SYNC_32ii",
-                    asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ALLP_SYNC_32ir",
-                    asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ALLP_SYNC_32ri",
-                    asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ALLP_SYNC_32rr",
-                    asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0048").unwrap();
-        assert_eq!(target.id, "match_all_i64_sync");
-        assert_eq!(target.abi_id, "i0048");
-        assert_eq!(target.dialect_op, "nvvm.match_all_sync_i64");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ALLP_SYNC_64ii",
-                    asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ALLP_SYNC_64ir",
-                    asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ALLP_SYNC_64ri",
-                    asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "MATCH_ALLP_SYNC_64rr",
-                    asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0049").unwrap();
-        assert_eq!(target.id, "sync_mask");
-        assert_eq!(target.abi_id, "i0049");
-        assert_eq!(target.dialect_op, "nvvm.bar_warp_sync");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "INT_BAR_WARP_SYNC_I",
-                    asm: "bar.warp.sync \t$i;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "INT_BAR_WARP_SYNC_R",
-                    asm: "bar.warp.sync \t$i;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0050").unwrap();
-        assert_eq!(target.id, "shuffle_sync");
-        assert_eq!(target.abi_id, "i0050");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_idx_i32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14989",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14990",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14991",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14992",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14993",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14994",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14995",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14996",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0051").unwrap();
-        assert_eq!(target.id, "shuffle_xor_sync");
-        assert_eq!(target.abi_id, "i0051");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_bfly_i32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14957",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14958",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14959",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14960",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14961",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14962",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14963",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14964",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0052").unwrap();
-        assert_eq!(target.id, "shuffle_down_sync");
-        assert_eq!(target.abi_id, "i0052");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_down_i32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14925",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14926",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14927",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14928",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14929",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14930",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14931",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14932",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0053").unwrap();
-        assert_eq!(target.id, "shuffle_up_sync");
-        assert_eq!(target.abi_id, "i0053");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_up_i32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14893",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14894",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14895",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14896",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14897",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14898",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14899",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14900",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0054").unwrap();
-        assert_eq!(target.id, "shuffle_f32_sync");
-        assert_eq!(target.abi_id, "i0054");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_idx_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_15005",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_15006",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_15007",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_15008",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_15009",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_15010",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_15011",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_15012",
-                    asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0055").unwrap();
-        assert_eq!(target.id, "shuffle_xor_f32_sync");
-        assert_eq!(target.abi_id, "i0055");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_bfly_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14973",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14974",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14975",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14976",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14977",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14978",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14979",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14980",
-                    asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0056").unwrap();
-        assert_eq!(target.id, "shuffle_down_f32_sync");
-        assert_eq!(target.abi_id, "i0056");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_down_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14941",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14942",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14943",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14944",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14945",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14946",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14947",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14948",
-                    asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0057").unwrap();
-        assert_eq!(target.id, "shuffle_up_f32_sync");
-        assert_eq!(target.abi_id, "i0057");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_up_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14909",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14910",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14911",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14912",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14913",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14914",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14915",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_14916",
-                    asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 60",
-                        "Subtarget->getSmVersion() >= 30"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0058").unwrap();
-        assert_eq!(target.id, "shuffle_u64_sync");
-        assert_eq!(target.abi_id, "i0058");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_idx_i64");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0059").unwrap();
-        assert_eq!(target.id, "shuffle_xor_u64_sync");
-        assert_eq!(target.abi_id, "i0059");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_bfly_i64");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0060").unwrap();
-        assert_eq!(target.id, "shuffle_down_u64_sync");
-        assert_eq!(target.abi_id, "i0060");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_down_i64");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0061").unwrap();
-        assert_eq!(target.id, "shuffle_up_u64_sync");
-        assert_eq!(target.abi_id, "i0061");
-        assert_eq!(target.dialect_op, "nvvm.shfl_sync_up_i64");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0062").unwrap();
-        assert_eq!(target.id, "fma_bf16x2");
-        assert_eq!(target.abi_id, "i0062");
-        assert_eq!(target.dialect_op, "nvvm.fma_bf16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_bf16x2",
-                asm: "fma.rn.bf16x2 \t$dst, $src0, $src1, $src2;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0063").unwrap();
-        assert_eq!(target.id, "fma_relu_bf16x2");
-        assert_eq!(target.abi_id, "i0063");
-        assert_eq!(target.dialect_op, "nvvm.fma_relu_bf16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_relu_bf16x2",
-                asm: "fma.rn.relu.bf16x2 \t$dst, $src0, $src1, $src2;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0064").unwrap();
-        assert_eq!(target.id, "add_bf16x2");
-        assert_eq!(target.abi_id, "i0064");
-        assert_eq!(target.dialect_op, "nvvm.add_bf16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0065").unwrap();
-        assert_eq!(target.id, "sub_bf16x2");
-        assert_eq!(target.abi_id, "i0065");
-        assert_eq!(target.dialect_op, "nvvm.sub_bf16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0066").unwrap();
-        assert_eq!(target.id, "mul_bf16x2");
-        assert_eq!(target.abi_id, "i0066");
-        assert_eq!(target.dialect_op, "nvvm.mul_bf16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0067").unwrap();
-        assert_eq!(target.id, "min_bf16x2");
-        assert_eq!(target.abi_id, "i0067");
-        assert_eq!(target.dialect_op, "nvvm.min_bf16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_bf16x2",
-                asm: "min.bf16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0068").unwrap();
-        assert_eq!(target.id, "max_bf16x2");
-        assert_eq!(target.abi_id, "i0068");
-        assert_eq!(target.dialect_op, "nvvm.max_bf16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_bf16x2",
-                asm: "max.bf16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0069").unwrap();
-        assert_eq!(target.id, "neg_bf16x2");
-        assert_eq!(target.abi_id, "i0069");
-        assert_eq!(target.dialect_op, "nvvm.neg_bf16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_NEG_BF16X2",
-                asm: "neg.bf16x2 \t$dst, $src0;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0070").unwrap();
-        assert_eq!(target.id, "abs_bf16x2");
-        assert_eq!(target.abi_id, "i0070");
-        assert_eq!(target.dialect_op, "nvvm.abs_bf16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "ABS_BF16X2",
-                asm: "abs.bf16x2 \t$dst, $src0;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0071").unwrap();
-        assert_eq!(target.id, "cvt_f32x2_bf16x2");
-        assert_eq!(target.abi_id, "i0071");
-        assert_eq!(target.dialect_op, "nvvm.cvt_f32x2_bf16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0072").unwrap();
-        assert_eq!(target.id, "fma_f16x2");
-        assert_eq!(target.abi_id, "i0072");
-        assert_eq!(target.dialect_op, "nvvm.fma_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_f16x2",
-                asm: "fma.rn.f16x2 \t$dst, $src0, $src1, $src2;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 53",
-                    "Subtarget->getPTXVersion() >= 42"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0073").unwrap();
-        assert_eq!(target.id, "fma_relu_f16x2");
-        assert_eq!(target.abi_id, "i0073");
-        assert_eq!(target.dialect_op, "nvvm.fma_relu_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_relu_f16x2",
-                asm: "fma.rn.relu.f16x2 \t$dst, $src0, $src1, $src2;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0074").unwrap();
-        assert_eq!(target.id, "add_f16x2");
-        assert_eq!(target.abi_id, "i0074");
-        assert_eq!(target.dialect_op, "nvvm.add_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0075").unwrap();
-        assert_eq!(target.id, "sub_f16x2");
-        assert_eq!(target.abi_id, "i0075");
-        assert_eq!(target.dialect_op, "nvvm.sub_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0076").unwrap();
-        assert_eq!(target.id, "mul_f16x2");
-        assert_eq!(target.abi_id, "i0076");
-        assert_eq!(target.dialect_op, "nvvm.mul_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0077").unwrap();
-        assert_eq!(target.id, "min_f16x2");
-        assert_eq!(target.abi_id, "i0077");
-        assert_eq!(target.dialect_op, "nvvm.min_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_f16x2",
-                asm: "min.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0078").unwrap();
-        assert_eq!(target.id, "max_f16x2");
-        assert_eq!(target.abi_id, "i0078");
-        assert_eq!(target.dialect_op, "nvvm.max_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_f16x2",
-                asm: "max.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0079").unwrap();
-        assert_eq!(target.id, "neg_f16x2");
-        assert_eq!(target.abi_id, "i0079");
-        assert_eq!(target.dialect_op, "nvvm.neg_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0080").unwrap();
-        assert_eq!(target.id, "abs_f16x2");
-        assert_eq!(target.abi_id, "i0080");
-        assert_eq!(target.dialect_op, "nvvm.abs_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "ABS_F16X2",
-                asm: "abs.f16x2 \t$dst, $src0;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 53",
-                    "Subtarget->getPTXVersion() >= 65"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0081").unwrap();
-        assert_eq!(target.id, "cvt_f16x2_f32");
-        assert_eq!(target.abi_id, "i0081");
-        assert_eq!(target.dialect_op, "nvvm.cvt_f16x2_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0082").unwrap();
-        assert_eq!(target.id, "cvt_rz_f16x2_f32");
-        assert_eq!(target.abi_id, "i0082");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rz_f16x2_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0083").unwrap();
-        assert_eq!(target.id, "cvt_rn_relu_f16x2_f32");
-        assert_eq!(target.abi_id, "i0083");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_relu_f16x2_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0084").unwrap();
-        assert_eq!(target.id, "cvt_rn_relu_bf16x2_f32");
-        assert_eq!(target.abi_id, "i0084");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_relu_bf16x2_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0085").unwrap();
-        assert_eq!(target.id, "cvt_rz_bf16x2_f32");
-        assert_eq!(target.abi_id, "i0085");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rz_bf16x2_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0086").unwrap();
-        assert_eq!(target.id, "cp_async_ca_4");
-        assert_eq!(target.abi_id, "i0086");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_ca_4");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4",
-                asm: "cp.async.ca.shared.global [$dst], [$src], 4;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0087").unwrap();
-        assert_eq!(target.id, "cp_async_ca_zfill_4");
-        assert_eq!(target.abi_id, "i0087");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_ca_zfill_4");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4_s",
-                    asm: "cp.async.ca.shared.global [$dst], [$src], 4, $src_size;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 80",
-                        "Subtarget->getPTXVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4_si",
-                    asm: "cp.async.ca.shared.global [$dst], [$src], 4, $src_size;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 80",
-                        "Subtarget->getPTXVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0088").unwrap();
-        assert_eq!(target.id, "cp_async_ca_8");
-        assert_eq!(target.abi_id, "i0088");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_ca_8");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8",
-                asm: "cp.async.ca.shared.global [$dst], [$src], 8;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0089").unwrap();
-        assert_eq!(target.id, "cp_async_ca_zfill_8");
-        assert_eq!(target.abi_id, "i0089");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_ca_zfill_8");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8_s",
-                    asm: "cp.async.ca.shared.global [$dst], [$src], 8, $src_size;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 80",
-                        "Subtarget->getPTXVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8_si",
-                    asm: "cp.async.ca.shared.global [$dst], [$src], 8, $src_size;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 80",
-                        "Subtarget->getPTXVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0090").unwrap();
-        assert_eq!(target.id, "cp_async_ca_16");
-        assert_eq!(target.abi_id, "i0090");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_ca_16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16",
-                asm: "cp.async.ca.shared.global [$dst], [$src], 16;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0091").unwrap();
-        assert_eq!(target.id, "cp_async_ca_zfill_16");
-        assert_eq!(target.abi_id, "i0091");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_ca_zfill_16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16_s",
-                    asm: "cp.async.ca.shared.global [$dst], [$src], 16, $src_size;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 80",
-                        "Subtarget->getPTXVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16_si",
-                    asm: "cp.async.ca.shared.global [$dst], [$src], 16, $src_size;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 80",
-                        "Subtarget->getPTXVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0092").unwrap();
-        assert_eq!(target.id, "cp_async_cg_16");
-        assert_eq!(target.abi_id, "i0092");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_cg_16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16",
-                asm: "cp.async.cg.shared.global [$dst], [$src], 16;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0093").unwrap();
-        assert_eq!(target.id, "cp_async_cg_zfill_16");
-        assert_eq!(target.abi_id, "i0093");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_cg_zfill_16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16_s",
-                    asm: "cp.async.cg.shared.global [$dst], [$src], 16, $src_size;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 80",
-                        "Subtarget->getPTXVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16_si",
-                    asm: "cp.async.cg.shared.global [$dst], [$src], 16, $src_size;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 80",
-                        "Subtarget->getPTXVersion() >= 70"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "NoAlias<arg0>",
-                "NoAlias<arg1>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0094").unwrap();
-        assert_eq!(target.id, "cp_async_commit_group");
-        assert_eq!(target.abi_id, "i0094");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_commit_group");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_COMMIT_GROUP",
-                asm: "cp.async.commit_group;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &[] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0095").unwrap();
-        assert_eq!(target.id, "cp_async_wait_all");
-        assert_eq!(target.abi_id, "i0095");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_wait_all");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_WAIT_ALL",
-                asm: "cp.async.wait_all;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &[] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0096").unwrap();
-        assert_eq!(target.id, "cp_async_wait_group");
-        assert_eq!(target.abi_id, "i0096");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_wait_group");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_WAIT_GROUP",
-                asm: "cp.async.wait_group \t$n;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0097").unwrap();
-        assert_eq!(target.id, "mbarrier_init");
-        assert_eq!(target.abi_id, "i0097");
-        assert_eq!(target.dialect_op, "nvvm.mbarrier_init_shared");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "MBARRIER_INIT_SHARED",
-                asm: "mbarrier.init.shared.b64 \t[$addr], $count;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0098").unwrap();
-        assert_eq!(target.id, "mbarrier_arrive");
-        assert_eq!(target.abi_id, "i0098");
-        assert_eq!(target.dialect_op, "nvvm.mbarrier_arrive_shared");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "MBARRIER_ARRIVE_SHARED",
-                asm: "mbarrier.arrive.shared.b64 \t$state, [$addr];",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0099").unwrap();
-        assert_eq!(target.id, "mbarrier_test_wait");
-        assert_eq!(target.abi_id, "i0099");
-        assert_eq!(target.dialect_op, "nvvm.mbarrier_test_wait_shared");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "MBARRIER_TEST_WAIT_SHARED",
-                asm: "mbarrier.test_wait.shared.b64 \t$res, [$addr], $state;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0100").unwrap();
-        assert_eq!(target.id, "mbarrier_inval");
-        assert_eq!(target.abi_id, "i0100");
-        assert_eq!(target.dialect_op, "nvvm.mbarrier_inval_shared");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "MBARRIER_INVAL_SHARED",
-                asm: "mbarrier.inval.shared.b64 \t[$addr];",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0101").unwrap();
-        assert_eq!(target.id, "cp_async_mbarrier_arrive");
-        assert_eq!(target.abi_id, "i0101");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_mbarrier_arrive");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_MBARRIER_ARRIVE",
-                asm: "cp.async.mbarrier.arrive.b64 \t[$addr];",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0102").unwrap();
-        assert_eq!(target.id, "cp_async_mbarrier_arrive_shared");
-        assert_eq!(target.abi_id, "i0102");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_mbarrier_arrive_shared");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_MBARRIER_ARRIVE_SHARED",
-                asm: "cp.async.mbarrier.arrive.shared.b64 \t[$addr];",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0103").unwrap();
-        assert_eq!(target.id, "cp_async_mbarrier_arrive_noinc");
-        assert_eq!(target.abi_id, "i0103");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_mbarrier_arrive_noinc");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_MBARRIER_ARRIVE_NOINC",
-                asm: "cp.async.mbarrier.arrive.noinc.b64 \t[$addr];",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0104").unwrap();
-        assert_eq!(target.id, "cp_async_mbarrier_arrive_noinc_shared");
-        assert_eq!(target.abi_id, "i0104");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_mbarrier_arrive_noinc_shared"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_MBARRIER_ARRIVE_NOINC_SHARED",
-                asm: "cp.async.mbarrier.arrive.noinc.shared.b64 \t[$addr];",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0105").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_f32_bf16");
-        assert_eq!(target.abi_id, "i0105");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::Bf16,
-                b_element: GeneratedRegisterMmaElement::Bf16,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_18973",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0106").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_f32_f16");
-        assert_eq!(target.abi_id, "i0106");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::F16,
-                b_element: GeneratedRegisterMmaElement::F16,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19051",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0107").unwrap();
-        assert_eq!(target.id, "mma_m16n8k8_f32_tf32");
-        assert_eq!(target.abi_id, "i0107");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k8,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::Tf32,
-                b_element: GeneratedRegisterMmaElement::Tf32,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_18964",
-                asm: "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0108").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_s8");
-        assert_eq!(target.abi_id, "i0108");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19407",
-                asm: "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0109").unwrap();
-        assert_eq!(target.id, "mma_m8n8k4_f64");
-        assert_eq!(target.abi_id, "i0109");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k4,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F64,
-                a_element: GeneratedRegisterMmaElement::F64,
-                b_element: GeneratedRegisterMmaElement::F64,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_18989",
-                asm: "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0110").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_s32_s8");
-        assert_eq!(target.abi_id, "i0110");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19383",
-                asm: "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0111").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_s32_s8_u8");
-        assert_eq!(target.abi_id, "i0111");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19388",
-                asm: "mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0112").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_s32_u8");
-        assert_eq!(target.abi_id, "i0112");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19398",
-                asm: "mma.sync.aligned.m16n8k16.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0113").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_s32_u8_s8");
-        assert_eq!(target.abi_id, "i0113");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19394",
-                asm: "mma.sync.aligned.m16n8k16.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0114").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_s8_u8");
-        assert_eq!(target.abi_id, "i0114");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19412",
-                asm: "mma.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0115").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_u8");
-        assert_eq!(target.abi_id, "i0115");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19422",
-                asm: "mma.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0116").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_u8_s8");
-        assert_eq!(target.abi_id, "i0116");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19418",
-                asm: "mma.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0117").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_s32_s8_satfinite");
-        assert_eq!(target.abi_id, "i0117");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19546",
-                asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0118").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_s32_s8_u8_satfinite");
-        assert_eq!(target.abi_id, "i0118");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19549",
-                asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0119").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_s32_u8_satfinite");
-        assert_eq!(target.abi_id, "i0119");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19555",
-                asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0120").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_s32_u8_s8_satfinite");
-        assert_eq!(target.abi_id, "i0120");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19552",
-                asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0121").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_s8_satfinite");
-        assert_eq!(target.abi_id, "i0121");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19558",
-                asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0122").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_s8_u8_satfinite");
-        assert_eq!(target.abi_id, "i0122");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19561",
-                asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0123").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_u8_satfinite");
-        assert_eq!(target.abi_id, "i0123");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19567",
-                asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0124").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_u8_s8_satfinite");
-        assert_eq!(target.abi_id, "i0124");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19564",
-                asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0125").unwrap();
-        assert_eq!(target.id, "mma_m8n8k16_s32_s8");
-        assert_eq!(target.abi_id, "i0125");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19359",
-                asm: "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0126").unwrap();
-        assert_eq!(target.id, "mma_m8n8k16_s32_s8_u8");
-        assert_eq!(target.abi_id, "i0126");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19364",
-                asm: "mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0127").unwrap();
-        assert_eq!(target.id, "mma_m8n8k16_s32_u8");
-        assert_eq!(target.abi_id, "i0127");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19374",
-                asm: "mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0128").unwrap();
-        assert_eq!(target.id, "mma_m8n8k16_s32_u8_s8");
-        assert_eq!(target.abi_id, "i0128");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19370",
-                asm: "mma.sync.aligned.m8n8k16.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0129").unwrap();
-        assert_eq!(target.id, "mma_m8n8k16_s32_s8_satfinite");
-        assert_eq!(target.abi_id, "i0129");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19534",
-                asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0130").unwrap();
-        assert_eq!(target.id, "mma_m8n8k16_s32_s8_u8_satfinite");
-        assert_eq!(target.abi_id, "i0130");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19537",
-                asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0131").unwrap();
-        assert_eq!(target.id, "mma_m8n8k16_s32_u8_satfinite");
-        assert_eq!(target.abi_id, "i0131");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::U8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19543",
-                asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0132").unwrap();
-        assert_eq!(target.id, "mma_m8n8k16_s32_u8_s8_satfinite");
-        assert_eq!(target.abi_id, "i0132");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U8,
-                b_element: GeneratedRegisterMmaElement::S8,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19540",
-                asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0133").unwrap();
-        assert_eq!(target.id, "mma_m8n8k32_s32_s4");
-        assert_eq!(target.abi_id, "i0133");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19431",
-                asm: "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0134").unwrap();
-        assert_eq!(target.id, "mma_m8n8k32_s32_s4_u4");
-        assert_eq!(target.abi_id, "i0134");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19436",
-                asm: "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0135").unwrap();
-        assert_eq!(target.id, "mma_m8n8k32_s32_u4");
-        assert_eq!(target.abi_id, "i0135");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19446",
-                asm: "mma.sync.aligned.m8n8k32.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0136").unwrap();
-        assert_eq!(target.id, "mma_m8n8k32_s32_u4_s4");
-        assert_eq!(target.abi_id, "i0136");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19442",
-                asm: "mma.sync.aligned.m8n8k32.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0137").unwrap();
-        assert_eq!(target.id, "mma_m8n8k32_s32_s4_satfinite");
-        assert_eq!(target.abi_id, "i0137");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19570",
-                asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0138").unwrap();
-        assert_eq!(target.id, "mma_m8n8k32_s32_s4_u4_satfinite");
-        assert_eq!(target.abi_id, "i0138");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19573",
-                asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0139").unwrap();
-        assert_eq!(target.id, "mma_m8n8k32_s32_u4_satfinite");
-        assert_eq!(target.abi_id, "i0139");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19579",
-                asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0140").unwrap();
-        assert_eq!(target.id, "mma_m8n8k32_s32_u4_s4_satfinite");
-        assert_eq!(target.abi_id, "i0140");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19576",
-                asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0141").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_s4");
-        assert_eq!(target.abi_id, "i0141");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19453",
-                asm: "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0142").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_s4_u4");
-        assert_eq!(target.abi_id, "i0142");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19458",
-                asm: "mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0143").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_u4");
-        assert_eq!(target.abi_id, "i0143");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19468",
-                asm: "mma.sync.aligned.m16n8k32.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0144").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_u4_s4");
-        assert_eq!(target.abi_id, "i0144");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19464",
-                asm: "mma.sync.aligned.m16n8k32.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0145").unwrap();
-        assert_eq!(target.id, "mma_m16n8k64_s32_s4");
-        assert_eq!(target.abi_id, "i0145");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k64,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19477",
-                asm: "mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0146").unwrap();
-        assert_eq!(target.id, "mma_m16n8k64_s32_s4_u4");
-        assert_eq!(target.abi_id, "i0146");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k64,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19482",
-                asm: "mma.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0147").unwrap();
-        assert_eq!(target.id, "mma_m16n8k64_s32_u4");
-        assert_eq!(target.abi_id, "i0147");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k64,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19492",
-                asm: "mma.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0148").unwrap();
-        assert_eq!(target.id, "mma_m16n8k64_s32_u4_s4");
-        assert_eq!(target.abi_id, "i0148");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k64,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19488",
-                asm: "mma.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0149").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_s4_satfinite");
-        assert_eq!(target.abi_id, "i0149");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19582",
-                asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0150").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_s4_u4_satfinite");
-        assert_eq!(target.abi_id, "i0150");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19585",
-                asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0151").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_u4_satfinite");
-        assert_eq!(target.abi_id, "i0151");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19591",
-                asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0152").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_s32_u4_s4_satfinite");
-        assert_eq!(target.abi_id, "i0152");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19588",
-                asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0153").unwrap();
-        assert_eq!(target.id, "mma_m16n8k64_s32_s4_satfinite");
-        assert_eq!(target.abi_id, "i0153");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k64,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19594",
-                asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0154").unwrap();
-        assert_eq!(target.id, "mma_m16n8k64_s32_s4_u4_satfinite");
-        assert_eq!(target.abi_id, "i0154");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k64,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::S4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19597",
-                asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0155").unwrap();
-        assert_eq!(target.id, "mma_m16n8k64_s32_u4_satfinite");
-        assert_eq!(target.abi_id, "i0155");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k64,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::U4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19603",
-                asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0156").unwrap();
-        assert_eq!(target.id, "mma_m16n8k64_s32_u4_s4_satfinite");
-        assert_eq!(target.abi_id, "i0156");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k64,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::U4,
-                b_element: GeneratedRegisterMmaElement::S4,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19600",
-                asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0157").unwrap();
-        assert_eq!(target.id, "mma_m8n8k128_s32_b1_xor_popc");
-        assert_eq!(target.abi_id, "i0157");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k128,
-                operation: GeneratedRegisterMmaOperation::XorPopc,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::B1,
-                b_element: GeneratedRegisterMmaElement::B1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19501",
-                asm: "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0158").unwrap();
-        assert_eq!(target.id, "mma_m16n8k128_s32_b1_xor_popc");
-        assert_eq!(target.abi_id, "i0158");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k128,
-                operation: GeneratedRegisterMmaOperation::XorPopc,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::B1,
-                b_element: GeneratedRegisterMmaElement::B1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19514",
-                asm: "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0159").unwrap();
-        assert_eq!(target.id, "mma_m16n8k256_s32_b1_xor_popc");
-        assert_eq!(target.abi_id, "i0159");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k256,
-                operation: GeneratedRegisterMmaOperation::XorPopc,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::B1,
-                b_element: GeneratedRegisterMmaElement::B1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19527",
-                asm: "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0160").unwrap();
-        assert_eq!(target.id, "mma_m8n8k128_s32_b1_and_popc");
-        assert_eq!(target.abi_id, "i0160");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M8n8k128,
-                operation: GeneratedRegisterMmaOperation::AndPopc,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::B1,
-                b_element: GeneratedRegisterMmaElement::B1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19505",
-                asm: "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0161").unwrap();
-        assert_eq!(target.id, "mma_m16n8k128_s32_b1_and_popc");
-        assert_eq!(target.abi_id, "i0161");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k128,
-                operation: GeneratedRegisterMmaOperation::AndPopc,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::B1,
-                b_element: GeneratedRegisterMmaElement::B1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19518",
-                asm: "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0162").unwrap();
-        assert_eq!(target.id, "mma_m16n8k256_s32_b1_and_popc");
-        assert_eq!(target.abi_id, "i0162");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k256,
-                operation: GeneratedRegisterMmaOperation::AndPopc,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::S32,
-                a_element: GeneratedRegisterMmaElement::B1,
-                b_element: GeneratedRegisterMmaElement::B1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::Wrapping
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19531",
-                asm: "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0163").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k32_s32_s8");
-        assert_eq!(target.abi_id, "i0163");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19958",
-                asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0164").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k32_s32_s8_u8");
-        assert_eq!(target.abi_id, "i0164");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19963",
-                asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0165").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k32_s32_u8");
-        assert_eq!(target.abi_id, "i0165");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19972",
-                asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0166").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k32_s32_u8_s8");
-        assert_eq!(target.abi_id, "i0166");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19968",
-                asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0167").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k32_s32_s8_satfinite");
-        assert_eq!(target.abi_id, "i0167");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20019",
-                asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0168").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k32_s32_s8_u8_satfinite");
-        assert_eq!(target.abi_id, "i0168");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20022",
-                asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0169").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k32_s32_u8_satfinite");
-        assert_eq!(target.abi_id, "i0169");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20028",
-                asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0170").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k32_s32_u8_s8_satfinite");
-        assert_eq!(target.abi_id, "i0170");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20025",
-                asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0171").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_s32_s8");
-        assert_eq!(target.abi_id, "i0171");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20168",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0172").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8");
-        assert_eq!(target.abi_id, "i0172");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20173",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0173").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_s32_u8");
-        assert_eq!(target.abi_id, "i0173");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20182",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0174").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8");
-        assert_eq!(target.abi_id, "i0174");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20178",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0175").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0175");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20229",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0176").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0176");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20232",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0177").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0177");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20238",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0178").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0178");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k32,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20235",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0179").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_s8");
-        assert_eq!(target.abi_id, "i0179");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20188",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0180").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8");
-        assert_eq!(target.abi_id, "i0180");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20193",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0181").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_u8");
-        assert_eq!(target.abi_id, "i0181");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20202",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0182").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8");
-        assert_eq!(target.abi_id, "i0182");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20198",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0183").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0183");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20241",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0184").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0184");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20244",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0185").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0185");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20250",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0186").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0186");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20247",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0187").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_s8");
-        assert_eq!(target.abi_id, "i0187");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19978",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0188").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_s8_u8");
-        assert_eq!(target.abi_id, "i0188");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19983",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0189").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_u8");
-        assert_eq!(target.abi_id, "i0189");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19992",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0190").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_u8_s8");
-        assert_eq!(target.abi_id, "i0190");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19988",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0191").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_s8_satfinite");
-        assert_eq!(target.abi_id, "i0191");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20031",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0192").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_s8_u8_satfinite");
-        assert_eq!(target.abi_id, "i0192");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20034",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0193").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_u8_satfinite");
-        assert_eq!(target.abi_id, "i0193");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::U8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20040",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0194").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_u8_s8_satfinite");
-        assert_eq!(target.abi_id, "i0194");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U8,
-                b_element: GeneratedSparseMmaElement::S8,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20037",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0195").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_s4");
-        assert_eq!(target.abi_id, "i0195");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20124",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0196").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4");
-        assert_eq!(target.abi_id, "i0196");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20129",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0197").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_u4");
-        assert_eq!(target.abi_id, "i0197");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20138",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0198").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4");
-        assert_eq!(target.abi_id, "i0198");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20134",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0199").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0199");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20205",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0200").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0200");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20208",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0201").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0201");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20214",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0202").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0202");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20211",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0203").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k128_s32_s4");
-        assert_eq!(target.abi_id, "i0203");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20146",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0204").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4");
-        assert_eq!(target.abi_id, "i0204");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20151",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0205").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k128_s32_u4");
-        assert_eq!(target.abi_id, "i0205");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20160",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0206").unwrap();
-        assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4");
-        assert_eq!(target.abi_id, "i0206");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20156",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0207").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0207");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20217",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0208").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0208");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20220",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0209").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0209");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20226",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0210").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
-        );
-        assert_eq!(target.abi_id, "i0210");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20223",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 85"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0211").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_s4");
-        assert_eq!(target.abi_id, "i0211");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19914",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0212").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_s4_u4");
-        assert_eq!(target.abi_id, "i0212");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19919",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0213").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_u4");
-        assert_eq!(target.abi_id, "i0213");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19928",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0214").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_u4_s4");
-        assert_eq!(target.abi_id, "i0214");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19924",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0215").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_s4_satfinite");
-        assert_eq!(target.abi_id, "i0215");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19995",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0216").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_s4_u4_satfinite");
-        assert_eq!(target.abi_id, "i0216");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19998",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0217").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_u4_satfinite");
-        assert_eq!(target.abi_id, "i0217");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20004",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0218").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k64_s32_u4_s4_satfinite");
-        assert_eq!(target.abi_id, "i0218");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20001",
-                asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg9>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg9,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0219").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k128_s32_s4");
-        assert_eq!(target.abi_id, "i0219");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19936",
-                asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0220").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k128_s32_s4_u4");
-        assert_eq!(target.abi_id, "i0220");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19941",
-                asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0221").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k128_s32_u4");
-        assert_eq!(target.abi_id, "i0221");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19950",
-                asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0222").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k128_s32_u4_s4");
-        assert_eq!(target.abi_id, "i0222");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Wrapping,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19946",
-                asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0223").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k128_s32_s4_satfinite");
-        assert_eq!(target.abi_id, "i0223");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20007",
-                asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0224").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k128_s32_s4_u4_satfinite");
-        assert_eq!(target.abi_id, "i0224");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::S4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20010",
-                asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0225").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k128_s32_u4_satfinite");
-        assert_eq!(target.abi_id, "i0225");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::U4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20016",
-                asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0226").unwrap();
-        assert_eq!(target.id, "mma_sp_m16n8k128_s32_u4_s4_satfinite");
-        assert_eq!(target.abi_id, "i0226");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k128,
-                accumulator: GeneratedSparseMmaAccumulator::S32,
-                a_element: GeneratedSparseMmaElement::U4,
-                b_element: GeneratedSparseMmaElement::S4,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::Satfinite,
-                metadata: GeneratedSparseMmaMetadata::Standard,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20013",
-                asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 71"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0227").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
-        );
-        assert_eq!(target.abi_id, "i0227");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E2m1,
-                b_element: GeneratedSparseMmaElement::E2m1,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20464",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0228").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
-        );
-        assert_eq!(target.abi_id, "i0228");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E2m1,
-                b_element: GeneratedSparseMmaElement::E2m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20456",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0229").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
-        );
-        assert_eq!(target.abi_id, "i0229");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E2m1,
-                b_element: GeneratedSparseMmaElement::E3m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20448",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0230").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
-        );
-        assert_eq!(target.abi_id, "i0230");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E2m1,
-                b_element: GeneratedSparseMmaElement::E4m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20432",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0231").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
-        );
-        assert_eq!(target.abi_id, "i0231");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E2m1,
-                b_element: GeneratedSparseMmaElement::E5m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20440",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0232").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
-        );
-        assert_eq!(target.abi_id, "i0232");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E2m3,
-                b_element: GeneratedSparseMmaElement::E2m1,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20423",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0233").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
-        );
-        assert_eq!(target.abi_id, "i0233");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E2m3,
-                b_element: GeneratedSparseMmaElement::E2m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20415",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0234").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
-        );
-        assert_eq!(target.abi_id, "i0234");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E2m3,
-                b_element: GeneratedSparseMmaElement::E3m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20407",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0235").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
-        );
-        assert_eq!(target.abi_id, "i0235");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E2m3,
-                b_element: GeneratedSparseMmaElement::E4m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20391",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0236").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
-        );
-        assert_eq!(target.abi_id, "i0236");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E2m3,
-                b_element: GeneratedSparseMmaElement::E5m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20399",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0237").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
-        );
-        assert_eq!(target.abi_id, "i0237");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E3m2,
-                b_element: GeneratedSparseMmaElement::E2m1,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20382",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0238").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
-        );
-        assert_eq!(target.abi_id, "i0238");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E3m2,
-                b_element: GeneratedSparseMmaElement::E2m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20374",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0239").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
-        );
-        assert_eq!(target.abi_id, "i0239");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E3m2,
-                b_element: GeneratedSparseMmaElement::E3m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20366",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0240").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
-        );
-        assert_eq!(target.abi_id, "i0240");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E3m2,
-                b_element: GeneratedSparseMmaElement::E4m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20350",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0241").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
-        );
-        assert_eq!(target.abi_id, "i0241");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E3m2,
-                b_element: GeneratedSparseMmaElement::E5m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20358",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0242").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
-        );
-        assert_eq!(target.abi_id, "i0242");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E4m3,
-                b_element: GeneratedSparseMmaElement::E2m1,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20300",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0243").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
-        );
-        assert_eq!(target.abi_id, "i0243");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E4m3,
-                b_element: GeneratedSparseMmaElement::E2m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20291",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0244").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
-        );
-        assert_eq!(target.abi_id, "i0244");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E4m3,
-                b_element: GeneratedSparseMmaElement::E3m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20282",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0245").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
-        );
-        assert_eq!(target.abi_id, "i0245");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E4m3,
-                b_element: GeneratedSparseMmaElement::E4m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20264",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0246").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
-        );
-        assert_eq!(target.abi_id, "i0246");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E4m3,
-                b_element: GeneratedSparseMmaElement::E5m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20273",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0247").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
-        );
-        assert_eq!(target.abi_id, "i0247");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E5m2,
-                b_element: GeneratedSparseMmaElement::E2m1,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20341",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0248").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
-        );
-        assert_eq!(target.abi_id, "i0248");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E5m2,
-                b_element: GeneratedSparseMmaElement::E2m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20333",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0249").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
-        );
-        assert_eq!(target.abi_id, "i0249");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E5m2,
-                b_element: GeneratedSparseMmaElement::E3m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20325",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0250").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
-        );
-        assert_eq!(target.abi_id, "i0250");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E5m2,
-                b_element: GeneratedSparseMmaElement::E4m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20309",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0251").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
-        );
-        assert_eq!(target.abi_id, "i0251");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F32,
-                a_element: GeneratedSparseMmaElement::E5m2,
-                b_element: GeneratedSparseMmaElement::E5m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20317",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg13>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg13,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0252").unwrap();
-        assert_eq!(target.id, "prmt");
-        assert_eq!(target.abi_id, "i0252");
-        assert_eq!(target.dialect_op, "nvvm.prmt");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Prmt {
-                mode: GeneratedPrmtMode::Generic
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0253").unwrap();
-        assert_eq!(target.id, "prmt_f4e");
-        assert_eq!(target.abi_id, "i0253");
-        assert_eq!(target.dialect_op, "nvvm.prmt");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Prmt {
-                mode: GeneratedPrmtMode::F4e
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0254").unwrap();
-        assert_eq!(target.id, "prmt_b4e");
-        assert_eq!(target.abi_id, "i0254");
-        assert_eq!(target.dialect_op, "nvvm.prmt");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Prmt {
-                mode: GeneratedPrmtMode::B4e
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0255").unwrap();
-        assert_eq!(target.id, "prmt_rc8");
-        assert_eq!(target.abi_id, "i0255");
-        assert_eq!(target.dialect_op, "nvvm.prmt");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Prmt {
-                mode: GeneratedPrmtMode::Rc8
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0256").unwrap();
-        assert_eq!(target.id, "prmt_ecl");
-        assert_eq!(target.abi_id, "i0256");
-        assert_eq!(target.dialect_op, "nvvm.prmt");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Prmt {
-                mode: GeneratedPrmtMode::Ecl
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0257").unwrap();
-        assert_eq!(target.id, "prmt_ecr");
-        assert_eq!(target.abi_id, "i0257");
-        assert_eq!(target.dialect_op, "nvvm.prmt");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Prmt {
-                mode: GeneratedPrmtMode::Ecr
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0258").unwrap();
-        assert_eq!(target.id, "prmt_rc16");
-        assert_eq!(target.abi_id, "i0258");
-        assert_eq!(target.dialect_op, "nvvm.prmt");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Prmt {
-                mode: GeneratedPrmtMode::Rc16
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0259").unwrap();
-        assert_eq!(target.id, "cvt_rn_satfinite_e4m3x2_f32");
-        assert_eq!(target.abi_id, "i0259");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_e4m3x2_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0260").unwrap();
-        assert_eq!(target.id, "cvt_rn_satfinite_relu_e4m3x2_f32");
-        assert_eq!(target.abi_id, "i0260");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_relu_e4m3x2_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0261").unwrap();
-        assert_eq!(target.id, "cvt_rn_satfinite_e5m2x2_f32");
-        assert_eq!(target.abi_id, "i0261");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_e5m2x2_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0262").unwrap();
-        assert_eq!(target.id, "cvt_rn_satfinite_relu_e5m2x2_f32");
-        assert_eq!(target.abi_id, "i0262");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_relu_e5m2x2_f32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0263").unwrap();
-        assert_eq!(target.id, "cluster_block_idx_x");
-        assert_eq!(target.abi_id, "i0263");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_ctaid_x");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTER_CTAID_x",
-                asm: "mov.u32 \t$d, %cluster_ctaid.x;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,2147483647>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0264").unwrap();
-        assert_eq!(target.id, "cluster_block_idx_y");
-        assert_eq!(target.abi_id, "i0264");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_ctaid_y");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTER_CTAID_y",
-                asm: "mov.u32 \t$d, %cluster_ctaid.y;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0265").unwrap();
-        assert_eq!(target.id, "cluster_block_idx_z");
-        assert_eq!(target.abi_id, "i0265");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_ctaid_z");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTER_CTAID_z",
-                asm: "mov.u32 \t$d, %cluster_ctaid.z;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0266").unwrap();
-        assert_eq!(target.id, "cluster_dim_x");
-        assert_eq!(target.abi_id, "i0266");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_nctaid_x");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTER_NCTAID_x",
-                asm: "mov.u32 \t$d, %cluster_nctaid.x;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,2147483648>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0267").unwrap();
-        assert_eq!(target.id, "cluster_dim_y");
-        assert_eq!(target.abi_id, "i0267");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_nctaid_y");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTER_NCTAID_y",
-                asm: "mov.u32 \t$d, %cluster_nctaid.y;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0268").unwrap();
-        assert_eq!(target.id, "cluster_dim_z");
-        assert_eq!(target.abi_id, "i0268");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_nctaid_z");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTER_NCTAID_z",
-                asm: "mov.u32 \t$d, %cluster_nctaid.z;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0269").unwrap();
-        assert_eq!(target.id, "cluster_idx_x");
-        assert_eq!(target.abi_id, "i0269");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_clusterid_x");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTERID_x",
-                asm: "mov.u32 \t$d, %clusterid.x;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,2147483647>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0270").unwrap();
-        assert_eq!(target.id, "cluster_idx_y");
-        assert_eq!(target.abi_id, "i0270");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_clusterid_y");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTERID_y",
-                asm: "mov.u32 \t$d, %clusterid.y;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0271").unwrap();
-        assert_eq!(target.id, "cluster_idx_z");
-        assert_eq!(target.abi_id, "i0271");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_clusterid_z");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTERID_z",
-                asm: "mov.u32 \t$d, %clusterid.z;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,0,65535>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0272").unwrap();
-        assert_eq!(target.id, "cluster_grid_dim_x");
-        assert_eq!(target.abi_id, "i0272");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nclusterid_x");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_NCLUSTERID_x",
-                asm: "mov.u32 \t$d, %nclusterid.x;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,2147483648>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0273").unwrap();
-        assert_eq!(target.id, "cluster_grid_dim_y");
-        assert_eq!(target.abi_id, "i0273");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nclusterid_y");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_NCLUSTERID_y",
-                asm: "mov.u32 \t$d, %nclusterid.y;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0274").unwrap();
-        assert_eq!(target.id, "cluster_grid_dim_z");
-        assert_eq!(target.abi_id, "i0274");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nclusterid_z");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_NCLUSTERID_z",
-                asm: "mov.u32 \t$d, %nclusterid.z;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrNoMem",
-                "IntrSpeculatable",
-                "NoUndef<ret>",
-                "Range<ret,1,65536>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0275").unwrap();
-        assert_eq!(target.id, "cluster_block_rank");
-        assert_eq!(target.abi_id, "i0275");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_ctarank");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTER_CTARANK",
-                asm: "mov.u32 \t$d, %cluster_ctarank;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0276").unwrap();
-        assert_eq!(target.id, "cluster_block_count");
-        assert_eq!(target.abi_id, "i0276");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_nctarank");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_CLUSTER_NCTARANK",
-                asm: "mov.u32 \t$d, %cluster_nctarank;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0277").unwrap();
-        assert_eq!(target.id, "barrier_cluster_arrive");
-        assert_eq!(target.abi_id, "i0277");
-        assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ClusterBarrier {
-                mode: GeneratedClusterBarrierMode::Arrive
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "barrier_cluster_arrive",
-                asm: "barrier.cluster.arrive;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0278").unwrap();
-        assert_eq!(target.id, "barrier_cluster_arrive_aligned");
-        assert_eq!(target.abi_id, "i0278");
-        assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ClusterBarrier {
-                mode: GeneratedClusterBarrierMode::ArriveAligned
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "barrier_cluster_arrive_aligned",
-                asm: "barrier.cluster.arrive.aligned;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0279").unwrap();
-        assert_eq!(target.id, "barrier_cluster_arrive_relaxed");
-        assert_eq!(target.abi_id, "i0279");
-        assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ClusterBarrier {
-                mode: GeneratedClusterBarrierMode::ArriveRelaxed
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "barrier_cluster_arrive_relaxed",
-                asm: "barrier.cluster.arrive.relaxed;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0280").unwrap();
-        assert_eq!(target.id, "barrier_cluster_arrive_relaxed_aligned");
-        assert_eq!(target.abi_id, "i0280");
-        assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ClusterBarrier {
-                mode: GeneratedClusterBarrierMode::ArriveRelaxedAligned
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "barrier_cluster_arrive_relaxed_aligned",
-                asm: "barrier.cluster.arrive.relaxed.aligned;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0281").unwrap();
-        assert_eq!(target.id, "barrier_cluster_wait");
-        assert_eq!(target.abi_id, "i0281");
-        assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ClusterBarrier {
-                mode: GeneratedClusterBarrierMode::Wait
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "barrier_cluster_wait",
-                asm: "barrier.cluster.wait;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0282").unwrap();
-        assert_eq!(target.id, "barrier_cluster_wait_aligned");
-        assert_eq!(target.abi_id, "i0282");
-        assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ClusterBarrier {
-                mode: GeneratedClusterBarrierMode::WaitAligned
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "barrier_cluster_wait_aligned",
-                asm: "barrier.cluster.wait.aligned;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0283").unwrap();
-        assert_eq!(target.id, "clock");
-        assert_eq!(target.abi_id, "i0283");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_clock");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "SREG_CLOCK",
-                asm: "mov.u32 \t$d, %clock;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-                "IntrNoFree",
-                "IntrWillReturn",
-                "NoUndef<ret>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0284").unwrap();
-        assert_eq!(target.id, "clock64");
-        assert_eq!(target.abi_id, "i0284");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_clock64");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "SREG_CLOCK64",
-                asm: "mov.u64 \t$d, %clock64;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-                "IntrNoFree",
-                "IntrWillReturn",
-                "NoUndef<ret>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0285").unwrap();
-        assert_eq!(target.id, "globaltimer");
-        assert_eq!(target.abi_id, "i0285");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_globaltimer");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 31);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(31),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "SREG_GLOBALTIMER",
-                asm: "mov.u64 \t$d, %globaltimer;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback",
-                "IntrNoFree",
-                "IntrWillReturn",
-                "NoUndef<ret>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0286").unwrap();
-        assert_eq!(target.id, "envreg1");
-        assert_eq!(target.abi_id, "i0286");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_envreg1");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 21);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(21),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0287").unwrap();
-        assert_eq!(target.id, "envreg2");
-        assert_eq!(target.abi_id, "i0287");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_envreg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 21);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(21),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0288").unwrap();
-        assert_eq!(target.id, "smid");
-        assert_eq!(target.abi_id, "i0288");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_smid");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 13);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(13),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "SREG_SMID",
-                asm: "mov.u32 \t$d, %smid;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0289").unwrap();
-        assert_eq!(target.id, "nsmid");
-        assert_eq!(target.abi_id, "i0289");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nsmid");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "SREG_NSMID",
-                asm: "mov.u32 \t$d, %nsmid;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0290").unwrap();
-        assert_eq!(target.id, "gridid");
-        assert_eq!(target.abi_id, "i0290");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_gridid");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 30);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(30),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0291").unwrap();
-        assert_eq!(target.id, "warpid");
-        assert_eq!(target.abi_id, "i0291");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_warpid");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 13);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(13),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "SREG_WARPID",
-                asm: "mov.u32 \t$d, %warpid;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0292").unwrap();
-        assert_eq!(target.id, "nwarpid");
-        assert_eq!(target.abi_id, "i0292");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nwarpid");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "SREG_NWARPID",
-                asm: "mov.u32 \t$d, %nwarpid;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0293").unwrap();
-        assert_eq!(target.id, "dynamic_smem_size");
-        assert_eq!(target.abi_id, "i0293");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_dynamic_smem_size");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 41);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(41),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(41),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_DYNAMIC_SMEM_SIZE",
-                asm: "mov.u32 \t$d, %dynamic_smem_size;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0294").unwrap();
-        assert_eq!(target.id, "total_smem_size");
-        assert_eq!(target.abi_id, "i0294");
-        assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_total_smem_size");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 41);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(41),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(41),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_PTX_SREG_TOTAL_SMEM_SIZE",
-                asm: "mov.u32 \t$d, %total_smem_size;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0295").unwrap();
-        assert_eq!(target.id, "trap");
-        assert_eq!(target.abi_id, "i0295");
-        assert_eq!(target.dialect_op, "nvvm.trap");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0296").unwrap();
-        assert_eq!(target.id, "breakpoint");
-        assert_eq!(target.abi_id, "i0296");
-        assert_eq!(target.dialect_op, "nvvm.brkpt");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(11)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0297").unwrap();
-        assert_eq!(target.id, "pmevent");
-        assert_eq!(target.abi_id, "i0297");
-        assert_eq!(target.dialect_op, "nvvm.pmevent");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 14);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0298").unwrap();
-        assert_eq!(target.id, "threadfence_block");
-        assert_eq!(target.abi_id, "i0298");
-        assert_eq!(target.dialect_op, "nvvm.threadfence_block");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 14);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_MEMBAR_CTA",
-                asm: "membar.cta;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0299").unwrap();
-        assert_eq!(target.id, "threadfence");
-        assert_eq!(target.abi_id, "i0299");
-        assert_eq!(target.dialect_op, "nvvm.threadfence");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 14);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_MEMBAR_GL",
-                asm: "membar.gl;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0300").unwrap();
-        assert_eq!(target.id, "threadfence_system");
-        assert_eq!(target.abi_id, "i0300");
-        assert_eq!(target.dialect_op, "nvvm.threadfence_system");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_MEMBAR_SYS",
-                asm: "membar.sys;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0301").unwrap();
-        assert_eq!(target.id, "stmatrix_m8n8_x2_b16");
-        assert_eq!(target.abi_id, "i0301");
-        assert_eq!(target.dialect_op, "nvvm.stmatrix_m8n8_x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0302").unwrap();
-        assert_eq!(target.id, "stmatrix_m8n8_x2_trans_b16");
-        assert_eq!(target.abi_id, "i0302");
-        assert_eq!(target.dialect_op, "nvvm.stmatrix_m8n8_x2_trans");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0303").unwrap();
-        assert_eq!(target.id, "stmatrix_m8n8_x4_b16");
-        assert_eq!(target.abi_id, "i0303");
-        assert_eq!(target.dialect_op, "nvvm.stmatrix_m8n8_x4");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0304").unwrap();
-        assert_eq!(target.id, "stmatrix_m8n8_x4_trans_b16");
-        assert_eq!(target.abi_id, "i0304");
-        assert_eq!(target.dialect_op, "nvvm.stmatrix_m8n8_x4_trans");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0305").unwrap();
-        assert_eq!(target.id, "movmatrix_trans_b16");
-        assert_eq!(target.abi_id, "i0305");
-        assert_eq!(target.dialect_op, "nvvm.movmatrix_trans_b16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0306").unwrap();
-        assert_eq!(target.id, "mbarrier_arrive_expect_tx");
-        assert_eq!(target.abi_id, "i0306");
-        assert_eq!(target.dialect_op, "nvvm.mbarrier_arrive_expect_tx_shared");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0307").unwrap();
-        assert_eq!(target.id, "mbarrier_arrive_expect_tx_cluster");
-        assert_eq!(target.abi_id, "i0307");
-        assert_eq!(target.dialect_op, "nvvm.mbarrier_arrive_expect_tx_cluster");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrArgMemOnly", "IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0308").unwrap();
-        assert_eq!(target.id, "mbarrier_arrive_cluster");
-        assert_eq!(target.abi_id, "i0308");
-        assert_eq!(target.dialect_op, "nvvm.mbarrier_arrive_cluster");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0309").unwrap();
-        assert_eq!(target.id, "mbarrier_try_wait");
-        assert_eq!(target.abi_id, "i0309");
-        assert_eq!(target.dialect_op, "nvvm.mbarrier_try_wait_shared");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "mbar_try_wait_scope_cta_acquire_STATE",
-                asm: "mbarrier.try_wait.shared.b64 $res, [$addr], $state;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0310").unwrap();
-        assert_eq!(target.id, "mbarrier_try_wait_parity");
-        assert_eq!(target.abi_id, "i0310");
-        assert_eq!(target.dialect_op, "nvvm.mbarrier_try_wait_parity_shared");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0311").unwrap();
-        assert_eq!(target.id, "mbarrier_try_wait_parity_cluster");
-        assert_eq!(target.abi_id, "i0311");
-        assert_eq!(target.dialect_op, "nvvm.mbarrier_try_wait_parity_cluster");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0312").unwrap();
-        assert_eq!(target.id, "fence_proxy_async_shared_cta");
-        assert_eq!(target.abi_id, "i0312");
-        assert_eq!(target.dialect_op, "nvvm.fence_proxy_async_shared_cta");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15048",
-                asm: "fence.proxy.async.shared::cta;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0313").unwrap();
-        assert_eq!(target.id, "fence_mbarrier_init_release_cluster");
-        assert_eq!(target.abi_id, "i0313");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_mbarrier_init_release_cluster"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_FENCE_MBARRIER_INIT_RELEASE_CLUSTER",
-                asm: "fence.mbarrier_init.release.cluster;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0314").unwrap();
-        assert_eq!(
-            target.id,
-            "fence_proxy_async_generic_release_shared_cta_cluster"
-        );
-        assert_eq!(target.abi_id, "i0314");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_proxy_async_generic_release_shared_cta_cluster"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FENCE_PROXY_ASYNC_GENERIC_RELEASE_SYNC_RESTRICT_SPACE_CTA_SCOPE_CLUSTER",
-                asm: "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0315").unwrap();
-        assert_eq!(
-            target.id,
-            "fence_proxy_async_generic_acquire_shared_cluster_cluster"
-        );
-        assert_eq!(target.abi_id, "i0315");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_proxy_async_generic_acquire_shared_cluster_cluster"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FENCE_PROXY_ASYNC_GENERIC_ACQUIRE_SYNC_RESTRICT_SPACE_CLUSTER_SCOPE_CLUSTER",
-                asm: "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0316").unwrap();
-        assert_eq!(target.id, "nanosleep");
-        assert_eq!(target.abi_id, "i0316");
-        assert_eq!(target.dialect_op, "nvvm.nanosleep");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 63);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(63),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(63),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "INT_NVVM_NANOSLEEP_I",
-                    asm: "nanosleep.u32 \t$i;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 70",
-                        "Subtarget->getPTXVersion() >= 63"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "INT_NVVM_NANOSLEEP_R",
-                    asm: "nanosleep.u32 \t$i;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 70",
-                        "Subtarget->getPTXVersion() >= 63"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrHasSideEffects", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0317").unwrap();
-        assert_eq!(target.id, "wgmma_fence");
-        assert_eq!(target.abi_id, "i0317");
-        assert_eq!(target.dialect_op, "nvvm.wgmma_fence_sync_aligned");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::WgmmaControl {
-                mode: GeneratedWgmmaControlMode::Fence
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(
-                    90,
-                )])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "WGMMA_FENCE_SYNC_ALIGNED",
-                asm: "wgmma.fence.sync.aligned;",
-                predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0318").unwrap();
-        assert_eq!(target.id, "wgmma_commit_group");
-        assert_eq!(target.abi_id, "i0318");
-        assert_eq!(target.dialect_op, "nvvm.wgmma_commit_group_sync_aligned");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::WgmmaControl {
-                mode: GeneratedWgmmaControlMode::CommitGroup
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(
-                    90,
-                )])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "WGMMA_COMMIT_GROUP_SYNC_ALIGNED",
-                asm: "wgmma.commit_group.sync.aligned;",
-                predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0319").unwrap();
-        assert_eq!(target.id, "wgmma_wait_group");
-        assert_eq!(target.abi_id, "i0319");
-        assert_eq!(target.dialect_op, "nvvm.wgmma_wait_group_sync_aligned");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::WgmmaControl {
-                mode: GeneratedWgmmaControlMode::WaitGroup
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(
-                    90,
-                )])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "WGMMA_WAIT_GROUP_SYNC_ALIGNED",
-                asm: "wgmma.wait_group.sync.aligned \t$n;",
-                predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg0>", "IntrConvergent"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0320").unwrap();
-        assert_eq!(target.id, "map_shared_rank");
-        assert_eq!(target.abi_id, "i0320");
-        assert_eq!(target.dialect_op, "nvvm.mapa_shared_cluster");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "mapa_shared_cluster_64",
-                    asm: "mapa.shared::cluster.u64 \t$d, $a, $b;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 90",
-                        "Subtarget->getPTXVersion() >= 78"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "mapa_shared_cluster_64i",
-                    asm: "mapa.shared::cluster.u64 \t$d, $a, $b;",
-                    predicates: &[
-                        "Subtarget->getSmVersion() >= 90",
-                        "Subtarget->getPTXVersion() >= 78"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable", "NoCapture<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0321").unwrap();
-        assert_eq!(target.id, "dsmem_read_u32");
-        assert_eq!(target.abi_id, "i0321");
-        assert_eq!(target.dialect_op, "nvvm.dsmem_read_u32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0322").unwrap();
-        assert_eq!(target.id, "clc_try_cancel");
-        assert_eq!(target.abi_id, "i0322");
-        assert_eq!(target.dialect_op, "nvvm.clc_try_cancel");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CLUSTERLAUNCHCONTRL_TRY_CANCEL",
-                asm: "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 \t[$addr], [$mbar];",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 100",
-                    "Subtarget->getPTXVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrArgMemOnly", "IntrHasSideEffects"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0323").unwrap();
-        assert_eq!(target.id, "clc_try_cancel_multicast");
-        assert_eq!(target.abi_id, "i0323");
-        assert_eq!(target.dialect_op, "nvvm.clc_try_cancel_multicast");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CLUSTERLAUNCHCONTRL_TRY_CANCEL_MULTICAST",
-                asm: "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 \t[$addr], [$mbar];",
-                predicates: &["Subtarget->hasClusterLaunchControlTryCancelMulticastSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrArgMemOnly", "IntrHasSideEffects"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0324").unwrap();
-        assert_eq!(target.id, "clc_query_is_canceled");
-        assert_eq!(target.abi_id, "i0324");
-        assert_eq!(target.dialect_op, "nvvm.clc_query_is_canceled");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0325").unwrap();
-        assert_eq!(target.id, "clc_query_get_first_ctaid_x");
-        assert_eq!(target.abi_id, "i0325");
-        assert_eq!(target.dialect_op, "nvvm.clc_query_get_first_ctaid_x");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0326").unwrap();
-        assert_eq!(target.id, "clc_query_get_first_ctaid_y");
-        assert_eq!(target.abi_id, "i0326");
-        assert_eq!(target.dialect_op, "nvvm.clc_query_get_first_ctaid_y");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0327").unwrap();
-        assert_eq!(target.id, "clc_query_get_first_ctaid_z");
-        assert_eq!(target.abi_id, "i0327");
-        assert_eq!(target.dialect_op, "nvvm.clc_query_get_first_ctaid_z");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0328").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_1d_g2s");
-        assert_eq!(target.abi_id, "i0328");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_g2s_tile_1d");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_G2S_TILE_CG0_1D",
-                asm: "cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0}}], [$mbar];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[
-                        GeneratedImmediateBinding {
-                            argument_index: 6,
-                            value: 0
-                        },
-                        GeneratedImmediateBinding {
-                            argument_index: 7,
-                            value: 0
-                        }
-                    ]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "Range<arg8,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0329").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_2d_g2s");
-        assert_eq!(target.abi_id, "i0329");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_g2s_tile_2d");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_G2S_TILE_CG0_2D",
-                asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[
-                        GeneratedImmediateBinding {
-                            argument_index: 7,
-                            value: 0
-                        },
-                        GeneratedImmediateBinding {
-                            argument_index: 8,
-                            value: 0
-                        }
-                    ]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrConvergent",
-                "Range<arg9,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0330").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_2d_g2s_multicast");
-        assert_eq!(target.abi_id, "i0330");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_G2S_TILE_CG0_2D_MC",
-                asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[
-                        GeneratedImmediateBinding {
-                            argument_index: 7,
-                            value: -1
-                        },
-                        GeneratedImmediateBinding {
-                            argument_index: 8,
-                            value: 0
-                        }
-                    ]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrConvergent",
-                "Range<arg9,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0331").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_2d_g2s_multicast_cg2");
-        assert_eq!(target.abi_id, "i0331");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast_cg2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_G2S_TILE_2D_MC",
-                asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
-                predicates: &["Subtarget->hasTMABlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[
-                        GeneratedImmediateBinding {
-                            argument_index: 7,
-                            value: -1
-                        },
-                        GeneratedImmediateBinding {
-                            argument_index: 8,
-                            value: 0
-                        }
-                    ]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrConvergent",
-                "Range<arg9,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0332").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_3d_g2s");
-        assert_eq!(target.abi_id, "i0332");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_g2s_tile_3d");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_G2S_TILE_CG0_3D",
-                asm: "cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2}}], [$mbar];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[
-                        GeneratedImmediateBinding {
-                            argument_index: 8,
-                            value: 0
-                        },
-                        GeneratedImmediateBinding {
-                            argument_index: 9,
-                            value: 0
-                        }
-                    ]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg10>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrConvergent",
-                "Range<arg10,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0333").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_4d_g2s");
-        assert_eq!(target.abi_id, "i0333");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_g2s_tile_4d");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_G2S_TILE_CG0_4D",
-                asm: "cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3}}], [$mbar];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[
-                        GeneratedImmediateBinding {
-                            argument_index: 9,
-                            value: 0
-                        },
-                        GeneratedImmediateBinding {
-                            argument_index: 10,
-                            value: 0
-                        }
-                    ]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg10>",
-                "ImmArg<arg11>",
-                "ImmArg<arg9>",
-                "IntrConvergent",
-                "Range<arg11,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0334").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_5d_g2s");
-        assert_eq!(target.abi_id, "i0334");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_g2s_tile_5d");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_G2S_TILE_CG0_5D",
-                asm: "cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$mbar];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[
-                        GeneratedImmediateBinding {
-                            argument_index: 10,
-                            value: 0
-                        },
-                        GeneratedImmediateBinding {
-                            argument_index: 11,
-                            value: 0
-                        }
-                    ]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg10>",
-                "ImmArg<arg11>",
-                "ImmArg<arg12>",
-                "IntrConvergent",
-                "Range<arg12,0,3>",
-                "ReadOnly<arg2>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0335").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_1d_s2g");
-        assert_eq!(target.abi_id, "i0335");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_s2g_tile_1d");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_S2G_TILE_1D",
-                asm: "cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [$tmap, {{$d0}}], [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 4,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0336").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_2d_s2g");
-        assert_eq!(target.abi_id, "i0336");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_s2g_tile_2d");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_S2G_TILE_2D",
-                asm: "cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1}}], [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 5,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0337").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_3d_s2g");
-        assert_eq!(target.abi_id, "i0337");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_s2g_tile_3d");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_S2G_TILE_3D",
-                asm: "cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2}}], [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 6,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0338").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_4d_s2g");
-        assert_eq!(target.abi_id, "i0338");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_s2g_tile_4d");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_S2G_TILE_4D",
-                asm: "cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3}}], [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 7,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0339").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_5d_s2g");
-        assert_eq!(target.abi_id, "i0339");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_s2g_tile_5d");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_S2G_TILE_5D",
-                asm: "cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$src];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 8,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0340").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_commit_group");
-        assert_eq!(target.abi_id, "i0340");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_commit_group");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_BULK_COMMIT_GROUP",
-                asm: "cp.async.bulk.commit_group;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &[] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0341").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_wait_group");
-        assert_eq!(target.abi_id, "i0341");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_wait_group");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_BULK_WAIT_GROUP",
-                asm: "cp.async.bulk.wait_group \t$n;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0342").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_wait_group_read");
-        assert_eq!(target.abi_id, "i0342");
-        assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_wait_group_read");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CP_ASYNC_BULK_WAIT_GROUP_READ",
-                asm: "cp.async.bulk.wait_group.read \t$n;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0343").unwrap();
-        assert_eq!(target.id, "tcgen05_alloc");
-        assert_eq!(target.abi_id, "i0343");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_alloc");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_ALLOC_S64_CG1",
-                asm: "tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 \t[$dst], $ncols;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0344").unwrap();
-        assert_eq!(target.id, "tcgen05_dealloc");
-        assert_eq!(target.abi_id, "i0344");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_dealloc");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_DEALLOC_CG1",
-                asm: "tcgen05.dealloc.cta_group::1.sync.aligned.b32 \t$tmem_addr, $ncols;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0345").unwrap();
-        assert_eq!(target.id, "tcgen05_relinquish_alloc_permit");
-        assert_eq!(target.abi_id, "i0345");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_relinquish_alloc_permit");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_RELINQ_CG1",
-                asm: "tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrInaccessibleMemOnly"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0346").unwrap();
-        assert_eq!(target.id, "tcgen05_fence_before_thread_sync");
-        assert_eq!(target.abi_id, "i0346");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_fence_before_thread_sync");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "tcgen05_fence_before_thread_sync",
-                asm: "tcgen05.fence::before_thread_sync;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrHasSideEffects", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0347").unwrap();
-        assert_eq!(target.id, "tcgen05_fence_after_thread_sync");
-        assert_eq!(target.abi_id, "i0347");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_fence_after_thread_sync");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "tcgen05_fence_after_thread_sync",
-                asm: "tcgen05.fence::after_thread_sync;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrHasSideEffects", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0348").unwrap();
-        assert_eq!(target.id, "tcgen05_commit");
-        assert_eq!(target.abi_id, "i0348");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_commit");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0349").unwrap();
-        assert_eq!(target.id, "tcgen05_commit_shared_cluster");
-        assert_eq!(target.abi_id, "i0349");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_commit_shared_cluster");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_COMMIT_S64_CG1",
-                asm: "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0350").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_f16");
-        assert_eq!(target.abi_id, "i0350");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma_ws_f16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0351").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_f16");
-        assert_eq!(target.abi_id, "i0351");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma_f16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0352").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_bf16");
-        assert_eq!(target.abi_id, "i0352");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma_ws_bf16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0353").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_tf32");
-        assert_eq!(target.abi_id, "i0353");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma_ws_tf32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0354").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_smem_to_tmem");
-        assert_eq!(target.abi_id, "i0354");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_smem_to_tmem");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x256b_cg1",
-                asm: "tcgen05.cp.cta_group::1.128x256b \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0355").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x8_pure");
-        assert_eq!(target.abi_id, "i0355");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x8_pure");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0356").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_pure");
-        assert_eq!(target.abi_id, "i0356");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_pure");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0357").unwrap();
-        assert_eq!(target.id, "tcgen05_load_wait");
-        assert_eq!(target.abi_id, "i0357");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_load_wait");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "tcgen05_wait_ld",
-                asm: "tcgen05.wait::ld.sync.aligned;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrInaccessibleMemOnly"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0358").unwrap();
-        assert_eq!(target.id, "tcgen05_store_wait");
-        assert_eq!(target.abi_id, "i0358");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_store_wait");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "tcgen05_wait_st",
-                asm: "tcgen05.wait::st.sync.aligned;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrInaccessibleMemOnly"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0359").unwrap();
-        assert_eq!(target.id, "tcgen05_alloc_cg2");
-        assert_eq!(target.abi_id, "i0359");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_alloc_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_ALLOC_S64_CG2",
-                asm: "tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 \t[$dst], $ncols;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0360").unwrap();
-        assert_eq!(target.id, "tcgen05_dealloc_cg2");
-        assert_eq!(target.abi_id, "i0360");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_dealloc_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_DEALLOC_CG2",
-                asm: "tcgen05.dealloc.cta_group::2.sync.aligned.b32 \t$tmem_addr, $ncols;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0361").unwrap();
-        assert_eq!(target.id, "tcgen05_relinquish_alloc_permit_cg2");
-        assert_eq!(target.abi_id, "i0361");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_relinquish_alloc_permit_cg2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_RELINQ_CG2",
-                asm: "tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrInaccessibleMemOnly"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0362").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_f16_cg2");
-        assert_eq!(target.abi_id, "i0362");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma_f16_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0363").unwrap();
-        assert_eq!(target.id, "tcgen05_commit_cg2");
-        assert_eq!(target.abi_id, "i0363");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_commit_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0364").unwrap();
-        assert_eq!(target.id, "tcgen05_commit_shared_cluster_cg2");
-        assert_eq!(target.abi_id, "i0364");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_commit_shared_cluster_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_COMMIT_S64_CG2",
-                asm: "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0365").unwrap();
-        assert_eq!(target.id, "tcgen05_commit_multicast_cg2");
-        assert_eq!(target.abi_id, "i0365");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_commit_multicast_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_COMMIT_S64_CG2_MC",
-                asm: "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0366").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_smem_to_tmem_cg2");
-        assert_eq!(target.abi_id, "i0366");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_smem_to_tmem_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x256b_cg2",
-                asm: "tcgen05.cp.cta_group::2.128x256b \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0367").unwrap();
-        assert_eq!(target.id, "elect_sync");
-        assert_eq!(target.abi_id, "i0367");
-        assert_eq!(target.dialect_op, "nvvm.elect_sync");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "INT_ELECT_SYNC_I",
-                    asm: "elect.sync \t$dest|$pred, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 80",
-                        "Subtarget->getSmVersion() >= 90"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "INT_ELECT_SYNC_R",
-                    asm: "elect.sync \t$dest|$pred, $mask;",
-                    predicates: &[
-                        "Subtarget->getPTXVersion() >= 80",
-                        "Subtarget->getSmVersion() >= 90"
-                    ],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrInaccessibleMemOnly"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0368").unwrap();
-        assert_eq!(target.id, "cvt_rna_tf32_f32");
-        assert_eq!(target.abi_id, "i0368");
-        assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarConversion {
-                rounding: GeneratedScalarConversionRounding::NearestAway,
-                saturation: GeneratedScalarConversionSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CVT_to_tf32_rna",
-                asm: "cvt.rna.tf32.f32 \t$dst, $src;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0369").unwrap();
-        assert_eq!(target.id, "cvt_rna_satfinite_tf32_f32");
-        assert_eq!(target.abi_id, "i0369");
-        assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarConversion {
-                rounding: GeneratedScalarConversionRounding::NearestAway,
-                saturation: GeneratedScalarConversionSaturation::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CVT_to_tf32_rna_satf",
-                asm: "cvt.rna.satfinite.tf32.f32 \t$dst, $src;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 81"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0370").unwrap();
-        assert_eq!(target.id, "cvt_rn_tf32_f32");
-        assert_eq!(target.abi_id, "i0370");
-        assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarConversion {
-                rounding: GeneratedScalarConversionRounding::NearestEven,
-                saturation: GeneratedScalarConversionSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CVT_to_tf32_rn",
-                asm: "cvt.rn.tf32.f32 \t$dst, $src;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0371").unwrap();
-        assert_eq!(target.id, "cvt_rn_relu_tf32_f32");
-        assert_eq!(target.abi_id, "i0371");
-        assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarConversion {
-                rounding: GeneratedScalarConversionRounding::NearestEven,
-                saturation: GeneratedScalarConversionSaturation::Relu
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CVT_to_tf32_rn_relu",
-                asm: "cvt.rn.relu.tf32.f32 \t$dst, $src;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0372").unwrap();
-        assert_eq!(target.id, "cvt_rn_satfinite_tf32_f32");
-        assert_eq!(target.abi_id, "i0372");
-        assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarConversion {
-                rounding: GeneratedScalarConversionRounding::NearestEven,
-                saturation: GeneratedScalarConversionSaturation::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CVT_to_tf32_rn_satf",
-                asm: "cvt.rn.satfinite.tf32.f32 \t$dst, $src;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 100",
-                    "Subtarget->getPTXVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0373").unwrap();
-        assert_eq!(target.id, "cvt_rn_relu_satfinite_tf32_f32");
-        assert_eq!(target.abi_id, "i0373");
-        assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarConversion {
-                rounding: GeneratedScalarConversionRounding::NearestEven,
-                saturation: GeneratedScalarConversionSaturation::ReluSatfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CVT_to_tf32_rn_relu_satf",
-                asm: "cvt.rn.relu.satfinite.tf32.f32 \t$dst, $src;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 100",
-                    "Subtarget->getPTXVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0374").unwrap();
-        assert_eq!(target.id, "cvt_rz_tf32_f32");
-        assert_eq!(target.abi_id, "i0374");
-        assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarConversion {
-                rounding: GeneratedScalarConversionRounding::TowardZero,
-                saturation: GeneratedScalarConversionSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CVT_to_tf32_rz",
-                asm: "cvt.rz.tf32.f32 \t$dst, $src;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0375").unwrap();
-        assert_eq!(target.id, "cvt_rz_relu_tf32_f32");
-        assert_eq!(target.abi_id, "i0375");
-        assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarConversion {
-                rounding: GeneratedScalarConversionRounding::TowardZero,
-                saturation: GeneratedScalarConversionSaturation::Relu
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CVT_to_tf32_rz_relu",
-                asm: "cvt.rz.relu.tf32.f32 \t$dst, $src;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0376").unwrap();
-        assert_eq!(target.id, "cvt_rz_satfinite_tf32_f32");
-        assert_eq!(target.abi_id, "i0376");
-        assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarConversion {
-                rounding: GeneratedScalarConversionRounding::TowardZero,
-                saturation: GeneratedScalarConversionSaturation::Satfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CVT_to_tf32_rz_satf",
-                asm: "cvt.rz.satfinite.tf32.f32 \t$dst, $src;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 100",
-                    "Subtarget->getPTXVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0377").unwrap();
-        assert_eq!(target.id, "cvt_rz_relu_satfinite_tf32_f32");
-        assert_eq!(target.abi_id, "i0377");
-        assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarConversion {
-                rounding: GeneratedScalarConversionRounding::TowardZero,
-                saturation: GeneratedScalarConversionSaturation::ReluSatfinite
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "CVT_to_tf32_rz_relu_satf",
-                asm: "cvt.rz.relu.satfinite.tf32.f32 \t$dst, $src;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 100",
-                    "Subtarget->getPTXVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0378").unwrap();
-        assert_eq!(target.id, "ldmatrix_m16n16_x1_trans_b8");
-        assert_eq!(target.abi_id, "i0378");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M16n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X1,
-                layout: GeneratedLdmatrixLayout::Transposed,
-                element: GeneratedLdmatrixElement::B8
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20772",
-                asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {{$rx10, $rx11}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0379").unwrap();
-        assert_eq!(target.id, "ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64");
-        assert_eq!(target.abi_id, "i0379");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M16n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X1,
-                layout: GeneratedLdmatrixLayout::Transposed,
-                element: GeneratedLdmatrixElement::B8x16B4x16P64
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20782",
-                asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b4x16_p64 {{$rx10, $rx11}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0380").unwrap();
-        assert_eq!(target.id, "ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32");
-        assert_eq!(target.abi_id, "i0380");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M16n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X1,
-                layout: GeneratedLdmatrixLayout::Transposed,
-                element: GeneratedLdmatrixElement::B8x16B6x16P32
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20777",
-                asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b6x16_p32 {{$rx10, $rx11}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0381").unwrap();
-        assert_eq!(target.id, "ldmatrix_m16n16_x2_trans_b8");
-        assert_eq!(target.abi_id, "i0381");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M16n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X2,
-                layout: GeneratedLdmatrixLayout::Transposed,
-                element: GeneratedLdmatrixElement::B8
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20789",
-                asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0382").unwrap();
-        assert_eq!(target.id, "ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64");
-        assert_eq!(target.abi_id, "i0382");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M16n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X2,
-                layout: GeneratedLdmatrixLayout::Transposed,
-                element: GeneratedLdmatrixElement::B8x16B4x16P64
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20799",
-                asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b4x16_p64 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0383").unwrap();
-        assert_eq!(target.id, "ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32");
-        assert_eq!(target.abi_id, "i0383");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M16n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X2,
-                layout: GeneratedLdmatrixLayout::Transposed,
-                element: GeneratedLdmatrixElement::B8x16B6x16P32
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20794",
-                asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b6x16_p32 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0384").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n16_x1_b8x16_b4x16_p64");
-        assert_eq!(target.abi_id, "i0384");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X1,
-                layout: GeneratedLdmatrixLayout::Normal,
-                element: GeneratedLdmatrixElement::B8x16B4x16P64
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20707",
-                asm: "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b4x16_p64 {{$rx10}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0385").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n16_x1_b8x16_b6x16_p32");
-        assert_eq!(target.abi_id, "i0385");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X1,
-                layout: GeneratedLdmatrixLayout::Normal,
-                element: GeneratedLdmatrixElement::B8x16B6x16P32
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20702",
-                asm: "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b6x16_p32 {{$rx10}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0386").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n16_x2_b8x16_b4x16_p64");
-        assert_eq!(target.abi_id, "i0386");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X2,
-                layout: GeneratedLdmatrixLayout::Normal,
-                element: GeneratedLdmatrixElement::B8x16B4x16P64
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20717",
-                asm: "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b4x16_p64 {{$rx20, $rx21}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0387").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n16_x2_b8x16_b6x16_p32");
-        assert_eq!(target.abi_id, "i0387");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X2,
-                layout: GeneratedLdmatrixLayout::Normal,
-                element: GeneratedLdmatrixElement::B8x16B6x16P32
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20712",
-                asm: "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b6x16_p32 {{$rx20, $rx21}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0388").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n16_x4_b8x16_b4x16_p64");
-        assert_eq!(target.abi_id, "i0388");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X4,
-                layout: GeneratedLdmatrixLayout::Normal,
-                element: GeneratedLdmatrixElement::B8x16B4x16P64
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20727",
-                asm: "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b4x16_p64 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0389").unwrap();
-        assert_eq!(target.id, "ldmatrix_m8n16_x4_b8x16_b6x16_p32");
-        assert_eq!(target.abi_id, "i0389");
-        assert_eq!(target.dialect_op, "nvvm.ldmatrix");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Ldmatrix {
-                shape: GeneratedLdmatrixShape::M8n16,
-                multiplicity: GeneratedLdmatrixMultiplicity::X4,
-                layout: GeneratedLdmatrixLayout::Normal,
-                element: GeneratedLdmatrixElement::B8x16B6x16P32
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20722",
-                asm: "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b6x16_p32 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
-                predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: Some(GeneratedSelectionAddressSpace::Shared),
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "IntrNoCallback",
-                "IntrReadMem",
-                "NoCapture<arg0>",
-                "ReadOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0390").unwrap();
-        assert_eq!(target.id, "mul_rn_f64");
-        assert_eq!(target.abi_id, "i0390");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RN_D",
-                asm: "mul.rn.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0391").unwrap();
-        assert_eq!(target.id, "mul_rz_f64");
-        assert_eq!(target.abi_id, "i0391");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RZ_D",
-                asm: "mul.rz.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0392").unwrap();
-        assert_eq!(target.id, "mul_rm_f64");
-        assert_eq!(target.abi_id, "i0392");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RM_D",
-                asm: "mul.rm.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0393").unwrap();
-        assert_eq!(target.id, "mul_rp_f64");
-        assert_eq!(target.abi_id, "i0393");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RP_D",
-                asm: "mul.rp.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0394").unwrap();
-        assert_eq!(target.id, "div_rn_f64");
-        assert_eq!(target.abi_id, "i0394");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RN_D",
-                asm: "div.rn.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0395").unwrap();
-        assert_eq!(target.id, "div_rz_f64");
-        assert_eq!(target.abi_id, "i0395");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RZ_D",
-                asm: "div.rz.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0396").unwrap();
-        assert_eq!(target.id, "div_rm_f64");
-        assert_eq!(target.abi_id, "i0396");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RM_D",
-                asm: "div.rm.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0397").unwrap();
-        assert_eq!(target.id, "div_rp_f64");
-        assert_eq!(target.abi_id, "i0397");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RP_D",
-                asm: "div.rp.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0398").unwrap();
-        assert_eq!(target.id, "fma_rn_f64");
-        assert_eq!(target.abi_id, "i0398");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_f64",
-                asm: "fma.rn.f64 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0399").unwrap();
-        assert_eq!(target.id, "fma_rz_f64");
-        assert_eq!(target.abi_id, "i0399");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rz_f64",
-                asm: "fma.rz.f64 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0400").unwrap();
-        assert_eq!(target.id, "fma_rm_f64");
-        assert_eq!(target.abi_id, "i0400");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rm_f64",
-                asm: "fma.rm.f64 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0401").unwrap();
-        assert_eq!(target.id, "fma_rp_f64");
-        assert_eq!(target.abi_id, "i0401");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rp_f64",
-                asm: "fma.rp.f64 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0402").unwrap();
-        assert_eq!(target.id, "mul_rn_f32");
-        assert_eq!(target.abi_id, "i0402");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RN_F",
-                asm: "mul.rn.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0403").unwrap();
-        assert_eq!(target.id, "mul_rn_ftz_f32");
-        assert_eq!(target.abi_id, "i0403");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RN_FTZ_F",
-                asm: "mul.rn.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0404").unwrap();
-        assert_eq!(target.id, "mul_rz_f32");
-        assert_eq!(target.abi_id, "i0404");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RZ_F",
-                asm: "mul.rz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0405").unwrap();
-        assert_eq!(target.id, "mul_rz_ftz_f32");
-        assert_eq!(target.abi_id, "i0405");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RZ_FTZ_F",
-                asm: "mul.rz.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0406").unwrap();
-        assert_eq!(target.id, "mul_rm_f32");
-        assert_eq!(target.abi_id, "i0406");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RM_F",
-                asm: "mul.rm.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0407").unwrap();
-        assert_eq!(target.id, "mul_rm_ftz_f32");
-        assert_eq!(target.abi_id, "i0407");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RM_FTZ_F",
-                asm: "mul.rm.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0408").unwrap();
-        assert_eq!(target.id, "mul_rp_f32");
-        assert_eq!(target.abi_id, "i0408");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RP_F",
-                asm: "mul.rp.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0409").unwrap();
-        assert_eq!(target.id, "mul_rp_ftz_f32");
-        assert_eq!(target.abi_id, "i0409");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Mul,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_MUL_RP_FTZ_F",
-                asm: "mul.rp.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0410").unwrap();
-        assert_eq!(target.id, "div_rn_f32");
-        assert_eq!(target.abi_id, "i0410");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RN_F",
-                asm: "div.rn.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0411").unwrap();
-        assert_eq!(target.id, "div_rn_ftz_f32");
-        assert_eq!(target.abi_id, "i0411");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RN_FTZ_F",
-                asm: "div.rn.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0412").unwrap();
-        assert_eq!(target.id, "div_rz_f32");
-        assert_eq!(target.abi_id, "i0412");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RZ_F",
-                asm: "div.rz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0413").unwrap();
-        assert_eq!(target.id, "div_rz_ftz_f32");
-        assert_eq!(target.abi_id, "i0413");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RZ_FTZ_F",
-                asm: "div.rz.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0414").unwrap();
-        assert_eq!(target.id, "div_rm_f32");
-        assert_eq!(target.abi_id, "i0414");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RM_F",
-                asm: "div.rm.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0415").unwrap();
-        assert_eq!(target.id, "div_rm_ftz_f32");
-        assert_eq!(target.abi_id, "i0415");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RM_FTZ_F",
-                asm: "div.rm.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0416").unwrap();
-        assert_eq!(target.id, "div_rp_f32");
-        assert_eq!(target.abi_id, "i0416");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RP_F",
-                asm: "div.rp.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0417").unwrap();
-        assert_eq!(target.id, "div_rp_ftz_f32");
-        assert_eq!(target.abi_id, "i0417");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Div,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_DIV_RP_FTZ_F",
-                asm: "div.rp.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0418").unwrap();
-        assert_eq!(target.id, "fma_rn_f32");
-        assert_eq!(target.abi_id, "i0418");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_f32",
-                asm: "fma.rn.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0419").unwrap();
-        assert_eq!(target.id, "fma_rn_ftz_f32");
-        assert_eq!(target.abi_id, "i0419");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_ftz_f32",
-                asm: "fma.rn.ftz.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0420").unwrap();
-        assert_eq!(target.id, "fma_rn_sat_f32");
-        assert_eq!(target.abi_id, "i0420");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_sat_f32",
-                asm: "fma.rn.sat.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0421").unwrap();
-        assert_eq!(target.id, "fma_rn_ftz_sat_f32");
-        assert_eq!(target.abi_id, "i0421");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_ftz_sat_f32",
-                asm: "fma.rn.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0422").unwrap();
-        assert_eq!(target.id, "fma_rz_f32");
-        assert_eq!(target.abi_id, "i0422");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rz_f32",
-                asm: "fma.rz.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0423").unwrap();
-        assert_eq!(target.id, "fma_rz_ftz_f32");
-        assert_eq!(target.abi_id, "i0423");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rz_ftz_f32",
-                asm: "fma.rz.ftz.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0424").unwrap();
-        assert_eq!(target.id, "fma_rz_sat_f32");
-        assert_eq!(target.abi_id, "i0424");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rz_sat_f32",
-                asm: "fma.rz.sat.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0425").unwrap();
-        assert_eq!(target.id, "fma_rz_ftz_sat_f32");
-        assert_eq!(target.abi_id, "i0425");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rz_ftz_sat_f32",
-                asm: "fma.rz.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0426").unwrap();
-        assert_eq!(target.id, "fma_rm_f32");
-        assert_eq!(target.abi_id, "i0426");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rm_f32",
-                asm: "fma.rm.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0427").unwrap();
-        assert_eq!(target.id, "fma_rm_ftz_f32");
-        assert_eq!(target.abi_id, "i0427");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rm_ftz_f32",
-                asm: "fma.rm.ftz.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0428").unwrap();
-        assert_eq!(target.id, "fma_rm_sat_f32");
-        assert_eq!(target.abi_id, "i0428");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rm_sat_f32",
-                asm: "fma.rm.sat.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0429").unwrap();
-        assert_eq!(target.id, "fma_rm_ftz_sat_f32");
-        assert_eq!(target.abi_id, "i0429");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rm_ftz_sat_f32",
-                asm: "fma.rm.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0430").unwrap();
-        assert_eq!(target.id, "fma_rp_f32");
-        assert_eq!(target.abi_id, "i0430");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rp_f32",
-                asm: "fma.rp.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0431").unwrap();
-        assert_eq!(target.id, "fma_rp_ftz_f32");
-        assert_eq!(target.abi_id, "i0431");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rp_ftz_f32",
-                asm: "fma.rp.ftz.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0432").unwrap();
-        assert_eq!(target.id, "fma_rp_sat_f32");
-        assert_eq!(target.abi_id, "i0432");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rp_sat_f32",
-                asm: "fma.rp.sat.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0433").unwrap();
-        assert_eq!(target.id, "fma_rp_ftz_sat_f32");
-        assert_eq!(target.abi_id, "i0433");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Fma,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rp_ftz_sat_f32",
-                asm: "fma.rp.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0434").unwrap();
-        assert_eq!(target.id, "add_rn_f64");
-        assert_eq!(target.abi_id, "i0434");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RN_D",
-                asm: "add.rn.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0435").unwrap();
-        assert_eq!(target.id, "add_rz_f64");
-        assert_eq!(target.abi_id, "i0435");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RZ_D",
-                asm: "add.rz.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0436").unwrap();
-        assert_eq!(target.id, "add_rm_f64");
-        assert_eq!(target.abi_id, "i0436");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RM_D",
-                asm: "add.rm.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0437").unwrap();
-        assert_eq!(target.id, "add_rp_f64");
-        assert_eq!(target.abi_id, "i0437");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F64,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RP_D",
-                asm: "add.rp.f64 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0438").unwrap();
-        assert_eq!(target.id, "add_rn_f32");
-        assert_eq!(target.abi_id, "i0438");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RN_F",
-                asm: "add.rn.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0439").unwrap();
-        assert_eq!(target.id, "add_rn_ftz_f32");
-        assert_eq!(target.abi_id, "i0439");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RN_FTZ_F",
-                asm: "add.rn.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0440").unwrap();
-        assert_eq!(target.id, "add_rn_sat_f32");
-        assert_eq!(target.abi_id, "i0440");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RN_SAT_F",
-                asm: "add.rn.sat.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0441").unwrap();
-        assert_eq!(target.id, "add_rn_ftz_sat_f32");
-        assert_eq!(target.abi_id, "i0441");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rn,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RN_SAT_FTZ_F",
-                asm: "add.rn.sat.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0442").unwrap();
-        assert_eq!(target.id, "add_rz_f32");
-        assert_eq!(target.abi_id, "i0442");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RZ_F",
-                asm: "add.rz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0443").unwrap();
-        assert_eq!(target.id, "add_rz_ftz_f32");
-        assert_eq!(target.abi_id, "i0443");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RZ_FTZ_F",
-                asm: "add.rz.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0444").unwrap();
-        assert_eq!(target.id, "add_rz_sat_f32");
-        assert_eq!(target.abi_id, "i0444");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RZ_SAT_F",
-                asm: "add.rz.sat.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0445").unwrap();
-        assert_eq!(target.id, "add_rz_ftz_sat_f32");
-        assert_eq!(target.abi_id, "i0445");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rz,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RZ_SAT_FTZ_F",
-                asm: "add.rz.sat.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0446").unwrap();
-        assert_eq!(target.id, "add_rm_f32");
-        assert_eq!(target.abi_id, "i0446");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RM_F",
-                asm: "add.rm.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0447").unwrap();
-        assert_eq!(target.id, "add_rm_ftz_f32");
-        assert_eq!(target.abi_id, "i0447");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RM_FTZ_F",
-                asm: "add.rm.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0448").unwrap();
-        assert_eq!(target.id, "add_rm_sat_f32");
-        assert_eq!(target.abi_id, "i0448");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RM_SAT_F",
-                asm: "add.rm.sat.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0449").unwrap();
-        assert_eq!(target.id, "add_rm_ftz_sat_f32");
-        assert_eq!(target.abi_id, "i0449");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rm,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RM_SAT_FTZ_F",
-                asm: "add.rm.sat.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0450").unwrap();
-        assert_eq!(target.id, "add_rp_f32");
-        assert_eq!(target.abi_id, "i0450");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RP_F",
-                asm: "add.rp.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0451").unwrap();
-        assert_eq!(target.id, "add_rp_ftz_f32");
-        assert_eq!(target.abi_id, "i0451");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::None
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RP_FTZ_F",
-                asm: "add.rp.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0452").unwrap();
-        assert_eq!(target.id, "add_rp_sat_f32");
-        assert_eq!(target.abi_id, "i0452");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RP_SAT_F",
-                asm: "add.rp.sat.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0453").unwrap();
-        assert_eq!(target.id, "add_rp_ftz_sat_f32");
-        assert_eq!(target.abi_id, "i0453");
-        assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ScalarArithmetic {
-                format: GeneratedScalarArithmeticFormat::F32,
-                operation: GeneratedScalarArithmeticOperation::Add,
-                rounding: GeneratedScalarArithmeticRounding::Rp,
-                subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
-                saturation: GeneratedScalarArithmeticSaturation::Sat
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_ADD_RP_SAT_FTZ_F",
-                asm: "add.rp.sat.ftz.f32 \t$dst, $src0, $src1;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0454").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e2m1_e2m1");
-        assert_eq!(target.abi_id, "i0454");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19350",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0455").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e2m1_e2m3");
-        assert_eq!(target.abi_id, "i0455");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19342",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0456").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e2m1_e3m2");
-        assert_eq!(target.abi_id, "i0456");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19334",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0457").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e2m1_e4m3");
-        assert_eq!(target.abi_id, "i0457");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19318",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0458").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e2m1_e5m2");
-        assert_eq!(target.abi_id, "i0458");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19326",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0459").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e2m3_e2m1");
-        assert_eq!(target.abi_id, "i0459");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19308",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0460").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e2m3_e2m3");
-        assert_eq!(target.abi_id, "i0460");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19300",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0461").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e2m3_e3m2");
-        assert_eq!(target.abi_id, "i0461");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19292",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0462").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e2m3_e4m3");
-        assert_eq!(target.abi_id, "i0462");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19276",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0463").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e2m3_e5m2");
-        assert_eq!(target.abi_id, "i0463");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19284",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0464").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e3m2_e2m1");
-        assert_eq!(target.abi_id, "i0464");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19266",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0465").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e3m2_e2m3");
-        assert_eq!(target.abi_id, "i0465");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19258",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0466").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e3m2_e3m2");
-        assert_eq!(target.abi_id, "i0466");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19250",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0467").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e3m2_e4m3");
-        assert_eq!(target.abi_id, "i0467");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19234",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0468").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e3m2_e5m2");
-        assert_eq!(target.abi_id, "i0468");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19242",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0469").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e4m3_e2m1");
-        assert_eq!(target.abi_id, "i0469");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19164",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0470").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e4m3_e2m3");
-        assert_eq!(target.abi_id, "i0470");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19155",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0471").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e4m3_e3m2");
-        assert_eq!(target.abi_id, "i0471");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19146",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0472").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e4m3_e4m3");
-        assert_eq!(target.abi_id, "i0472");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19119",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0473").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e4m3_e5m2");
-        assert_eq!(target.abi_id, "i0473");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19137",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0474").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e5m2_e2m1");
-        assert_eq!(target.abi_id, "i0474");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19224",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0475").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e5m2_e2m3");
-        assert_eq!(target.abi_id, "i0475");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19216",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0476").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e5m2_e3m2");
-        assert_eq!(target.abi_id, "i0476");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19208",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0477").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e5m2_e4m3");
-        assert_eq!(target.abi_id, "i0477");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19184",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0478").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f32_e5m2_e5m2");
-        assert_eq!(target.abi_id, "i0478");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19200",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0479").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e2m1_e2m1");
-        assert_eq!(target.abi_id, "i0479");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19346",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0480").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e2m1_e2m3");
-        assert_eq!(target.abi_id, "i0480");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19338",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0481").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e2m1_e3m2");
-        assert_eq!(target.abi_id, "i0481");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19330",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0482").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e2m1_e4m3");
-        assert_eq!(target.abi_id, "i0482");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19314",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0483").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e2m1_e5m2");
-        assert_eq!(target.abi_id, "i0483");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19322",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0484").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e2m3_e2m1");
-        assert_eq!(target.abi_id, "i0484");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19304",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0485").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e2m3_e2m3");
-        assert_eq!(target.abi_id, "i0485");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19296",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0486").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e2m3_e3m2");
-        assert_eq!(target.abi_id, "i0486");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19288",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0487").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e2m3_e4m3");
-        assert_eq!(target.abi_id, "i0487");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19272",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0488").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e2m3_e5m2");
-        assert_eq!(target.abi_id, "i0488");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19280",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0489").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e3m2_e2m1");
-        assert_eq!(target.abi_id, "i0489");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19262",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0490").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e3m2_e2m3");
-        assert_eq!(target.abi_id, "i0490");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19254",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0491").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e3m2_e3m2");
-        assert_eq!(target.abi_id, "i0491");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19246",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0492").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e3m2_e4m3");
-        assert_eq!(target.abi_id, "i0492");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19230",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0493").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e3m2_e5m2");
-        assert_eq!(target.abi_id, "i0493");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19238",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0494").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e4m3_e2m1");
-        assert_eq!(target.abi_id, "i0494");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19160",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0495").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e4m3_e2m3");
-        assert_eq!(target.abi_id, "i0495");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19151",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0496").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e4m3_e3m2");
-        assert_eq!(target.abi_id, "i0496");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19142",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0497").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e4m3_e4m3");
-        assert_eq!(target.abi_id, "i0497");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19107",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0498").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e4m3_e5m2");
-        assert_eq!(target.abi_id, "i0498");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19129",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0499").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e5m2_e2m1");
-        assert_eq!(target.abi_id, "i0499");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19220",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0500").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e5m2_e2m3");
-        assert_eq!(target.abi_id, "i0500");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19212",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0501").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e5m2_e3m2");
-        assert_eq!(target.abi_id, "i0501");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19204",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0502").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e5m2_e4m3");
-        assert_eq!(target.abi_id, "i0502");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19176",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0503").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_f16_e5m2_e5m2");
-        assert_eq!(target.abi_id, "i0503");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::F8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19192",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0504").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_fp8_f16_e4m3_e4m3");
-        assert_eq!(target.abi_id, "i0504");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19058",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 87"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0505").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_fp8_f16_e4m3_e5m2");
-        assert_eq!(target.abi_id, "i0505");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19067",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 87"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0506").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_fp8_f16_e5m2_e4m3");
-        assert_eq!(target.abi_id, "i0506");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19077",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 87"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0507").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_fp8_f16_e5m2_e5m2");
-        assert_eq!(target.abi_id, "i0507");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19085",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 87"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0508").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_fp8_f32_e4m3_e4m3");
-        assert_eq!(target.abi_id, "i0508");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19062",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 87"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0509").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_fp8_f32_e4m3_e5m2");
-        assert_eq!(target.abi_id, "i0509");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19071",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 87"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0510").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_fp8_f32_e5m2_e4m3");
-        assert_eq!(target.abi_id, "i0510");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19081",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 87"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0511").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_fp8_f32_e5m2_e5m2");
-        assert_eq!(target.abi_id, "i0511");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19089",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 87"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0512").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_fp8_f16_e4m3_e4m3");
-        assert_eq!(target.abi_id, "i0512");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19098",
-                asm: "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 84"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0513").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_fp8_f16_e4m3_e5m2");
-        assert_eq!(target.abi_id, "i0513");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19124",
-                asm: "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 84"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0514").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_fp8_f16_e5m2_e4m3");
-        assert_eq!(target.abi_id, "i0514");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19170",
-                asm: "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 84"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0515").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_fp8_f16_e5m2_e5m2");
-        assert_eq!(target.abi_id, "i0515");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19188",
-                asm: "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 84"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0516").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_fp8_f32_e4m3_e4m3");
-        assert_eq!(target.abi_id, "i0516");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 84);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19113",
-                asm: "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 84"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0517").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_fp8_f32_e4m3_e5m2");
-        assert_eq!(target.abi_id, "i0517");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 84);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19133",
-                asm: "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 84"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0518").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_fp8_f32_e5m2_e4m3");
-        assert_eq!(target.abi_id, "i0518");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 84);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19180",
-                asm: "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 84"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0519").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_fp8_f32_e5m2_e5m2");
-        assert_eq!(target.abi_id, "i0519");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 84);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19196",
-                asm: "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 89",
-                    "Subtarget->getPTXVersion() >= 84"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0520").unwrap();
-        assert_eq!(target.id, "mma_m16n8k4_f32_tf32");
-        assert_eq!(target.abi_id, "i0520");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k4,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::Tf32,
-                b_element: GeneratedRegisterMmaElement::Tf32,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_18955",
-                asm: "mma.sync.aligned.m16n8k4.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0521").unwrap();
-        assert_eq!(target.id, "mma_m16n8k8_f16_f16");
-        assert_eq!(target.abi_id, "i0521");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k8,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::F16,
-                b_element: GeneratedRegisterMmaElement::F16,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19034",
-                asm: "mma.sync.aligned.m16n8k8.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0522").unwrap();
-        assert_eq!(target.id, "mma_m16n8k8_f32_bf16");
-        assert_eq!(target.abi_id, "i0522");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k8,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::Bf16,
-                b_element: GeneratedRegisterMmaElement::Bf16,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_18980",
-                asm: "mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0523").unwrap();
-        assert_eq!(target.id, "mma_m16n8k8_f32_f16");
-        assert_eq!(target.abi_id, "i0523");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k8,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::F16,
-                b_element: GeneratedRegisterMmaElement::F16,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19038",
-                asm: "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 65",
-                    "Subtarget->getSmVersion() >= 75"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0524").unwrap();
-        assert_eq!(target.id, "mma_m16n8k16_f16_f16");
-        assert_eq!(target.abi_id, "i0524");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k16,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Standard,
-                accumulator: GeneratedRegisterMmaAccumulator::F16,
-                a_element: GeneratedRegisterMmaElement::F16,
-                b_element: GeneratedRegisterMmaElement::F16,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19047",
-                asm: "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0525").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
-        );
-        assert_eq!(target.abi_id, "i0525");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E2m1,
-                b_element: GeneratedSparseMmaElement::E2m1,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20460",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0526").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
-        );
-        assert_eq!(target.abi_id, "i0526");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E2m1,
-                b_element: GeneratedSparseMmaElement::E2m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20452",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0527").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
-        );
-        assert_eq!(target.abi_id, "i0527");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E2m1,
-                b_element: GeneratedSparseMmaElement::E3m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20444",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0528").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
-        );
-        assert_eq!(target.abi_id, "i0528");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E2m1,
-                b_element: GeneratedSparseMmaElement::E4m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20428",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0529").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
-        );
-        assert_eq!(target.abi_id, "i0529");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E2m1,
-                b_element: GeneratedSparseMmaElement::E5m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20436",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0530").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
-        );
-        assert_eq!(target.abi_id, "i0530");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E2m3,
-                b_element: GeneratedSparseMmaElement::E2m1,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20419",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0531").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
-        );
-        assert_eq!(target.abi_id, "i0531");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E2m3,
-                b_element: GeneratedSparseMmaElement::E2m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20411",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0532").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
-        );
-        assert_eq!(target.abi_id, "i0532");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E2m3,
-                b_element: GeneratedSparseMmaElement::E3m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20403",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0533").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
-        );
-        assert_eq!(target.abi_id, "i0533");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E2m3,
-                b_element: GeneratedSparseMmaElement::E4m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20387",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0534").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
-        );
-        assert_eq!(target.abi_id, "i0534");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E2m3,
-                b_element: GeneratedSparseMmaElement::E5m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20395",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0535").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
-        );
-        assert_eq!(target.abi_id, "i0535");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E3m2,
-                b_element: GeneratedSparseMmaElement::E2m1,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20378",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0536").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
-        );
-        assert_eq!(target.abi_id, "i0536");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E3m2,
-                b_element: GeneratedSparseMmaElement::E2m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20370",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0537").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
-        );
-        assert_eq!(target.abi_id, "i0537");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E3m2,
-                b_element: GeneratedSparseMmaElement::E3m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20362",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0538").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
-        );
-        assert_eq!(target.abi_id, "i0538");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E3m2,
-                b_element: GeneratedSparseMmaElement::E4m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20346",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0539").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
-        );
-        assert_eq!(target.abi_id, "i0539");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E3m2,
-                b_element: GeneratedSparseMmaElement::E5m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20354",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0540").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
-        );
-        assert_eq!(target.abi_id, "i0540");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E4m3,
-                b_element: GeneratedSparseMmaElement::E2m1,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20296",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0541").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
-        );
-        assert_eq!(target.abi_id, "i0541");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E4m3,
-                b_element: GeneratedSparseMmaElement::E2m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20287",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0542").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
-        );
-        assert_eq!(target.abi_id, "i0542");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E4m3,
-                b_element: GeneratedSparseMmaElement::E3m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20278",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0543").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
-        );
-        assert_eq!(target.abi_id, "i0543");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E4m3,
-                b_element: GeneratedSparseMmaElement::E4m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20258",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0544").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
-        );
-        assert_eq!(target.abi_id, "i0544");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E4m3,
-                b_element: GeneratedSparseMmaElement::E5m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20269",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0545").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
-        );
-        assert_eq!(target.abi_id, "i0545");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E5m2,
-                b_element: GeneratedSparseMmaElement::E2m1,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20337",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0546").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
-        );
-        assert_eq!(target.abi_id, "i0546");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E5m2,
-                b_element: GeneratedSparseMmaElement::E2m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20329",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0547").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
-        );
-        assert_eq!(target.abi_id, "i0547");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E5m2,
-                b_element: GeneratedSparseMmaElement::E3m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20321",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0548").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
-        );
-        assert_eq!(target.abi_id, "i0548");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E5m2,
-                b_element: GeneratedSparseMmaElement::E4m3,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20305",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0549").unwrap();
-        assert_eq!(
-            target.id,
-            "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
-        );
-        assert_eq!(target.abi_id, "i0549");
-        assert_eq!(target.dialect_op, "nvvm.sparse_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::SparseMma {
-                shape: GeneratedSparseMmaShape::M16n8k64,
-                accumulator: GeneratedSparseMmaAccumulator::F16,
-                a_element: GeneratedSparseMmaElement::E5m2,
-                b_element: GeneratedSparseMmaElement::E5m2,
-                a_layout: GeneratedSparseMmaLayout::Row,
-                b_layout: GeneratedSparseMmaLayout::Col,
-                overflow: GeneratedSparseMmaOverflow::NotApplicable,
-                metadata: GeneratedSparseMmaMetadata::Ordered,
-                selector: GeneratedSparseMmaSelector::ImmediateZero
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_20313",
-                asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg11>",
-                "IntrNoCallback",
-                "IntrNoMem",
-                "Range<arg11,0,1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0550").unwrap();
-        assert_eq!(target.id, "min_ftz_f16x2");
-        assert_eq!(target.abi_id, "i0550");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_ftz_f16x2",
-                asm: "min.ftz.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0551").unwrap();
-        assert_eq!(target.id, "min_ftz_nan_f16x2");
-        assert_eq!(target.abi_id, "i0551");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_ftz_NaN_f16x2",
-                asm: "min.ftz.NaN.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0552").unwrap();
-        assert_eq!(target.id, "min_ftz_nan_xorsign_abs_f32");
-        assert_eq!(target.abi_id, "i0552");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F32,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_FTZ_NAN_XORSIGN_ABS_F",
-                asm: "min.ftz.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0553").unwrap();
-        assert_eq!(target.id, "min_ftz_nan_xorsign_abs_f16x2");
-        assert_eq!(target.abi_id, "i0553");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_ftz_NaN_xorsign_abs_f16x2",
-                asm: "min.ftz.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0554").unwrap();
-        assert_eq!(target.id, "min_ftz_xorsign_abs_f32");
-        assert_eq!(target.abi_id, "i0554");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F32,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_FTZ_XORSIGN_ABS_F",
-                asm: "min.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0555").unwrap();
-        assert_eq!(target.id, "min_ftz_xorsign_abs_f16x2");
-        assert_eq!(target.abi_id, "i0555");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_ftz_xorsign_abs_f16x2",
-                asm: "min.ftz.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0556").unwrap();
-        assert_eq!(target.id, "min_nan_bf16x2");
-        assert_eq!(target.abi_id, "i0556");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16x2,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_NaN_bf16x2",
-                asm: "min.NaN.bf16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0557").unwrap();
-        assert_eq!(target.id, "min_nan_f16x2");
-        assert_eq!(target.abi_id, "i0557");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_NaN_f16x2",
-                asm: "min.NaN.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0558").unwrap();
-        assert_eq!(target.id, "min_nan_xorsign_abs_bf16x2");
-        assert_eq!(target.abi_id, "i0558");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16x2,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_bf16x2",
-                asm: "min.NaN.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0559").unwrap();
-        assert_eq!(target.id, "min_nan_xorsign_abs_f32");
-        assert_eq!(target.abi_id, "i0559");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F32,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_NAN_XORSIGN_ABS_F",
-                asm: "min.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0560").unwrap();
-        assert_eq!(target.id, "min_nan_xorsign_abs_f16x2");
-        assert_eq!(target.abi_id, "i0560");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_f16x2",
-                asm: "min.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0561").unwrap();
-        assert_eq!(target.id, "min_xorsign_abs_bf16x2");
-        assert_eq!(target.abi_id, "i0561");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16x2,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_xorsign_abs_bf16x2",
-                asm: "min.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0562").unwrap();
-        assert_eq!(target.id, "min_xorsign_abs_f32");
-        assert_eq!(target.abi_id, "i0562");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F32,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_XORSIGN_ABS_F",
-                asm: "min.xorsign.abs.f32 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0563").unwrap();
-        assert_eq!(target.id, "min_xorsign_abs_f16x2");
-        assert_eq!(target.abi_id, "i0563");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_xorsign_abs_f16x2",
-                asm: "min.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0564").unwrap();
-        assert_eq!(target.id, "max_ftz_f16x2");
-        assert_eq!(target.abi_id, "i0564");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_ftz_f16x2",
-                asm: "max.ftz.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0565").unwrap();
-        assert_eq!(target.id, "max_ftz_nan_f16x2");
-        assert_eq!(target.abi_id, "i0565");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_ftz_NaN_f16x2",
-                asm: "max.ftz.NaN.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0566").unwrap();
-        assert_eq!(target.id, "max_ftz_nan_xorsign_abs_f32");
-        assert_eq!(target.abi_id, "i0566");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F32,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAX_FTZ_NAN_XORSIGN_ABS_F",
-                asm: "max.ftz.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0567").unwrap();
-        assert_eq!(target.id, "max_ftz_nan_xorsign_abs_f16x2");
-        assert_eq!(target.abi_id, "i0567");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_ftz_NaN_xorsign_abs_f16x2",
-                asm: "max.ftz.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0568").unwrap();
-        assert_eq!(target.id, "max_ftz_xorsign_abs_f32");
-        assert_eq!(target.abi_id, "i0568");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F32,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAX_FTZ_XORSIGN_ABS_F",
-                asm: "max.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0569").unwrap();
-        assert_eq!(target.id, "max_ftz_xorsign_abs_f16x2");
-        assert_eq!(target.abi_id, "i0569");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_ftz_xorsign_abs_f16x2",
-                asm: "max.ftz.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0570").unwrap();
-        assert_eq!(target.id, "max_nan_bf16x2");
-        assert_eq!(target.abi_id, "i0570");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16x2,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_NaN_bf16x2",
-                asm: "max.NaN.bf16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0571").unwrap();
-        assert_eq!(target.id, "max_nan_f16x2");
-        assert_eq!(target.abi_id, "i0571");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_NaN_f16x2",
-                asm: "max.NaN.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0572").unwrap();
-        assert_eq!(target.id, "max_nan_xorsign_abs_bf16x2");
-        assert_eq!(target.abi_id, "i0572");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16x2,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_bf16x2",
-                asm: "max.NaN.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0573").unwrap();
-        assert_eq!(target.id, "max_nan_xorsign_abs_f32");
-        assert_eq!(target.abi_id, "i0573");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F32,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAX_NAN_XORSIGN_ABS_F",
-                asm: "max.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0574").unwrap();
-        assert_eq!(target.id, "max_nan_xorsign_abs_f16x2");
-        assert_eq!(target.abi_id, "i0574");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_f16x2",
-                asm: "max.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0575").unwrap();
-        assert_eq!(target.id, "max_xorsign_abs_bf16x2");
-        assert_eq!(target.abi_id, "i0575");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16x2,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_xorsign_abs_bf16x2",
-                asm: "max.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0576").unwrap();
-        assert_eq!(target.id, "max_xorsign_abs_f32");
-        assert_eq!(target.abi_id, "i0576");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F32,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAX_XORSIGN_ABS_F",
-                asm: "max.xorsign.abs.f32 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0577").unwrap();
-        assert_eq!(target.id, "max_xorsign_abs_f16x2");
-        assert_eq!(target.abi_id, "i0577");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16x2,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_xorsign_abs_f16x2",
-                asm: "max.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0578").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_128x128b_b4x16_p64");
-        assert_eq!(target.abi_id, "i0578");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b_b4x16_p64");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x128bb4x16_p64_cg1",
-                asm: "tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0579").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_128x128b_b4x16_p64_cg2");
-        assert_eq!(target.abi_id, "i0579");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b_b4x16_p64_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x128bb4x16_p64_cg2",
-                asm: "tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0580").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_128x128b_b6x16_p32");
-        assert_eq!(target.abi_id, "i0580");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b_b6x16_p32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x128bb6x16_p32_cg1",
-                asm: "tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0581").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_128x128b_b6x16_p32_cg2");
-        assert_eq!(target.abi_id, "i0581");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b_b6x16_p32_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x128bb6x16_p32_cg2",
-                asm: "tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0582").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_128x128b");
-        assert_eq!(target.abi_id, "i0582");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x128b_cg1",
-                asm: "tcgen05.cp.cta_group::1.128x128b \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0583").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_128x128b_cg2");
-        assert_eq!(target.abi_id, "i0583");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x128b_cg2",
-                asm: "tcgen05.cp.cta_group::2.128x128b \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0584").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_128x256b_b4x16_p64");
-        assert_eq!(target.abi_id, "i0584");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x256b_b4x16_p64");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x256bb4x16_p64_cg1",
-                asm: "tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0585").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_128x256b_b4x16_p64_cg2");
-        assert_eq!(target.abi_id, "i0585");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x256b_b4x16_p64_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x256bb4x16_p64_cg2",
-                asm: "tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0586").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_128x256b_b6x16_p32");
-        assert_eq!(target.abi_id, "i0586");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x256b_b6x16_p32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x256bb6x16_p32_cg1",
-                asm: "tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0587").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_128x256b_b6x16_p32_cg2");
-        assert_eq!(target.abi_id, "i0587");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x256b_b6x16_p32_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_128x256bb6x16_p32_cg2",
-                asm: "tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0588").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4_b4x16_p64");
-        assert_eq!(target.abi_id, "i0588");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_32x128b_warpx4_b4x16_p64"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_32x128b4x16_p64_cg1",
-                asm: "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0589").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2");
-        assert_eq!(target.abi_id, "i0589");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_32x128b4x16_p64_cg2",
-                asm: "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0590").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4_b6x16_p32");
-        assert_eq!(target.abi_id, "i0590");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_32x128b_warpx4_b6x16_p32"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_32x128b6x16_p32_cg1",
-                asm: "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0591").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2");
-        assert_eq!(target.abi_id, "i0591");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_32x128b6x16_p32_cg2",
-                asm: "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0592").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4");
-        assert_eq!(target.abi_id, "i0592");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_32x128b_warpx4");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_32x128_cg1",
-                asm: "tcgen05.cp.cta_group::1.32x128b.warpx4 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0593").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4_cg2");
-        assert_eq!(target.abi_id, "i0593");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_32x128b_warpx4_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_32x128_cg2",
-                asm: "tcgen05.cp.cta_group::2.32x128b.warpx4 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0594").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_4x256b_b4x16_p64");
-        assert_eq!(target.abi_id, "i0594");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b_b4x16_p64");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_4x256bb4x16_p64_cg1",
-                asm: "tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0595").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_4x256b_b4x16_p64_cg2");
-        assert_eq!(target.abi_id, "i0595");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b_b4x16_p64_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_4x256bb4x16_p64_cg2",
-                asm: "tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0596").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_4x256b_b6x16_p32");
-        assert_eq!(target.abi_id, "i0596");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b_b6x16_p32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_4x256bb6x16_p32_cg1",
-                asm: "tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0597").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_4x256b_b6x16_p32_cg2");
-        assert_eq!(target.abi_id, "i0597");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b_b6x16_p32_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_4x256bb6x16_p32_cg2",
-                asm: "tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0598").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_4x256b");
-        assert_eq!(target.abi_id, "i0598");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_4x256b_cg1",
-                asm: "tcgen05.cp.cta_group::1.4x256b \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0599").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_4x256b_cg2");
-        assert_eq!(target.abi_id, "i0599");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_4x256b_cg2",
-                asm: "tcgen05.cp.cta_group::2.4x256b \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0600").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64");
-        assert_eq!(target.abi_id, "i0600");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_2b4x16_p64_cg1",
-                asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0601").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2");
-        assert_eq!(target.abi_id, "i0601");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_2b4x16_p64_cg2",
-                asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0602").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32");
-        assert_eq!(target.abi_id, "i0602");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_2b6x16_p32_cg1",
-                asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0603").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2");
-        assert_eq!(target.abi_id, "i0603");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_2b6x16_p32_cg2",
-                asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0604").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23");
-        assert_eq!(target.abi_id, "i0604");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_64x128b_warpx2_01_23");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_2_cg1",
-                asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0605").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23_cg2");
-        assert_eq!(target.abi_id, "i0605");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_64x128b_warpx2_01_23_cg2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_2_cg2",
-                asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0606").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64");
-        assert_eq!(target.abi_id, "i0606");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_1b4x16_p64_cg1",
-                asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0607").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2");
-        assert_eq!(target.abi_id, "i0607");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_1b4x16_p64_cg2",
-                asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0608").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32");
-        assert_eq!(target.abi_id, "i0608");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_1b6x16_p32_cg1",
-                asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0609").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2");
-        assert_eq!(target.abi_id, "i0609");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_1b6x16_p32_cg2",
-                asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0610").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13");
-        assert_eq!(target.abi_id, "i0610");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_64x128b_warpx2_02_13");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_1_cg1",
-                asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0611").unwrap();
-        assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13_cg2");
-        assert_eq!(target.abi_id, "i0611");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tcgen05_cp_64x128b_warpx2_02_13_cg2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_CP_64x128_1_cg2",
-                asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 \t[$tmem_addr], $sdesc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0612").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x1_raw");
-        assert_eq!(target.abi_id, "i0612");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x1_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0613").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x1_pack16");
-        assert_eq!(target.abi_id, "i0613");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x1_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0614").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x2_raw");
-        assert_eq!(target.abi_id, "i0614");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x2_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0615").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x2_pack16");
-        assert_eq!(target.abi_id, "i0615");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x2_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0616").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x4_raw");
-        assert_eq!(target.abi_id, "i0616");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x4_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0617").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x4_pack16");
-        assert_eq!(target.abi_id, "i0617");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x4_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0618").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x8_raw");
-        assert_eq!(target.abi_id, "i0618");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x8_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0619").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x8_pack16");
-        assert_eq!(target.abi_id, "i0619");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x8_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0620").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x16_raw");
-        assert_eq!(target.abi_id, "i0620");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x16_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0621").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x16_pack16");
-        assert_eq!(target.abi_id, "i0621");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x16_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0622").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x32_raw");
-        assert_eq!(target.abi_id, "i0622");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x32_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0623").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x32_pack16");
-        assert_eq!(target.abi_id, "i0623");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x32_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0624").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x64_raw");
-        assert_eq!(target.abi_id, "i0624");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x64_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0625").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x64_pack16");
-        assert_eq!(target.abi_id, "i0625");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x64_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0626").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x128_raw");
-        assert_eq!(target.abi_id, "i0626");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x128_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0627").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x64b_x128_pack16");
-        assert_eq!(target.abi_id, "i0627");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x128_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0628").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x1_raw");
-        assert_eq!(target.abi_id, "i0628");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x1_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0629").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x1_pack16");
-        assert_eq!(target.abi_id, "i0629");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x1_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0630").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x2_raw");
-        assert_eq!(target.abi_id, "i0630");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x2_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0631").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x2_pack16");
-        assert_eq!(target.abi_id, "i0631");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x2_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0632").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x4_raw");
-        assert_eq!(target.abi_id, "i0632");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x4_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0633").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x4_pack16");
-        assert_eq!(target.abi_id, "i0633");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x4_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0634").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x8_raw");
-        assert_eq!(target.abi_id, "i0634");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x8_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0635").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x8_pack16");
-        assert_eq!(target.abi_id, "i0635");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x8_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0636").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x16_raw");
-        assert_eq!(target.abi_id, "i0636");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x16_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0637").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x16_pack16");
-        assert_eq!(target.abi_id, "i0637");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x16_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0638").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x32_raw");
-        assert_eq!(target.abi_id, "i0638");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x32_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0639").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x32_pack16");
-        assert_eq!(target.abi_id, "i0639");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x32_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0640").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x64_raw");
-        assert_eq!(target.abi_id, "i0640");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x64_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0641").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x128b_x64_pack16");
-        assert_eq!(target.abi_id, "i0641");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x64_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0642").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x1_raw");
-        assert_eq!(target.abi_id, "i0642");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x1_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0643").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x1_pack16");
-        assert_eq!(target.abi_id, "i0643");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x1_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0644").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x2_raw");
-        assert_eq!(target.abi_id, "i0644");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x2_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0645").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x2_pack16");
-        assert_eq!(target.abi_id, "i0645");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x2_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0646").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x4_raw");
-        assert_eq!(target.abi_id, "i0646");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x4_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0647").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x4_pack16");
-        assert_eq!(target.abi_id, "i0647");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x4_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0648").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x8_raw");
-        assert_eq!(target.abi_id, "i0648");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x8_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0649").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x8_pack16");
-        assert_eq!(target.abi_id, "i0649");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x8_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0650").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x16_raw");
-        assert_eq!(target.abi_id, "i0650");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x16_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0651").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x16_pack16");
-        assert_eq!(target.abi_id, "i0651");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x16_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0652").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x32_raw");
-        assert_eq!(target.abi_id, "i0652");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x32_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0653").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x256b_x32_pack16");
-        assert_eq!(target.abi_id, "i0653");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x32_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0654").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x1_raw");
-        assert_eq!(target.abi_id, "i0654");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x1_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0655").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x1_pack16");
-        assert_eq!(target.abi_id, "i0655");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x1_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0656").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x2_raw");
-        assert_eq!(target.abi_id, "i0656");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x2_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0657").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x2_pack16");
-        assert_eq!(target.abi_id, "i0657");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x2_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0658").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x4_raw");
-        assert_eq!(target.abi_id, "i0658");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x4_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0659").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x4_pack16");
-        assert_eq!(target.abi_id, "i0659");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x4_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0660").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x8_raw");
-        assert_eq!(target.abi_id, "i0660");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x8_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0661").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x8_pack16");
-        assert_eq!(target.abi_id, "i0661");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x8_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0662").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x16_raw");
-        assert_eq!(target.abi_id, "i0662");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x16_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0663").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x16_pack16");
-        assert_eq!(target.abi_id, "i0663");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x16_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0664").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x32_raw");
-        assert_eq!(target.abi_id, "i0664");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x32_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0665").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x32_pack16");
-        assert_eq!(target.abi_id, "i0665");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x32_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0666").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x64_raw");
-        assert_eq!(target.abi_id, "i0666");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x64_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0667").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x64_pack16");
-        assert_eq!(target.abi_id, "i0667");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x64_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0668").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x128_raw");
-        assert_eq!(target.abi_id, "i0668");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x128_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0669").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_32x32b_x128_pack16");
-        assert_eq!(target.abi_id, "i0669");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x128_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0670").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x1_raw");
-        assert_eq!(target.abi_id, "i0670");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x1_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0671").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x1_unpack16");
-        assert_eq!(target.abi_id, "i0671");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x1_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0672").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x2_raw");
-        assert_eq!(target.abi_id, "i0672");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x2_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0673").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x2_unpack16");
-        assert_eq!(target.abi_id, "i0673");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x2_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0674").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x4_raw");
-        assert_eq!(target.abi_id, "i0674");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x4_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0675").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x4_unpack16");
-        assert_eq!(target.abi_id, "i0675");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x4_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0676").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x8_raw");
-        assert_eq!(target.abi_id, "i0676");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x8_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0677").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x8_unpack16");
-        assert_eq!(target.abi_id, "i0677");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x8_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0678").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x16_raw");
-        assert_eq!(target.abi_id, "i0678");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x16_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0679").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x16_unpack16");
-        assert_eq!(target.abi_id, "i0679");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x16_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0680").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x32_raw");
-        assert_eq!(target.abi_id, "i0680");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x32_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0681").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x32_unpack16");
-        assert_eq!(target.abi_id, "i0681");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x32_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0682").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x64_raw");
-        assert_eq!(target.abi_id, "i0682");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x64_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0683").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x64_unpack16");
-        assert_eq!(target.abi_id, "i0683");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x64_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0684").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x128_raw");
-        assert_eq!(target.abi_id, "i0684");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x128_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0685").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x64b_x128_unpack16");
-        assert_eq!(target.abi_id, "i0685");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x128_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0686").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x1_raw");
-        assert_eq!(target.abi_id, "i0686");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x1_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0687").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x1_unpack16");
-        assert_eq!(target.abi_id, "i0687");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x1_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0688").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x2_raw");
-        assert_eq!(target.abi_id, "i0688");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x2_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0689").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x2_unpack16");
-        assert_eq!(target.abi_id, "i0689");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x2_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0690").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x4_raw");
-        assert_eq!(target.abi_id, "i0690");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x4_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0691").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x4_unpack16");
-        assert_eq!(target.abi_id, "i0691");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x4_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0692").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x8_raw");
-        assert_eq!(target.abi_id, "i0692");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x8_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0693").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x8_unpack16");
-        assert_eq!(target.abi_id, "i0693");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x8_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0694").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x16_raw");
-        assert_eq!(target.abi_id, "i0694");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x16_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0695").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x16_unpack16");
-        assert_eq!(target.abi_id, "i0695");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x16_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0696").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x32_raw");
-        assert_eq!(target.abi_id, "i0696");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x32_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0697").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x32_unpack16");
-        assert_eq!(target.abi_id, "i0697");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x32_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0698").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x64_raw");
-        assert_eq!(target.abi_id, "i0698");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x64_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0699").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x128b_x64_unpack16");
-        assert_eq!(target.abi_id, "i0699");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x64_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0700").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x1_raw");
-        assert_eq!(target.abi_id, "i0700");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x1_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0701").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x1_unpack16");
-        assert_eq!(target.abi_id, "i0701");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x1_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0702").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x2_raw");
-        assert_eq!(target.abi_id, "i0702");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x2_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0703").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x2_unpack16");
-        assert_eq!(target.abi_id, "i0703");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x2_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0704").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x4_raw");
-        assert_eq!(target.abi_id, "i0704");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x4_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0705").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x4_unpack16");
-        assert_eq!(target.abi_id, "i0705");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x4_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0706").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x8_raw");
-        assert_eq!(target.abi_id, "i0706");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x8_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0707").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x8_unpack16");
-        assert_eq!(target.abi_id, "i0707");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x8_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0708").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x16_raw");
-        assert_eq!(target.abi_id, "i0708");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x16_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0709").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x16_unpack16");
-        assert_eq!(target.abi_id, "i0709");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x16_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0710").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x32_raw");
-        assert_eq!(target.abi_id, "i0710");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x32_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0711").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x256b_x32_unpack16");
-        assert_eq!(target.abi_id, "i0711");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x32_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0712").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x1_raw");
-        assert_eq!(target.abi_id, "i0712");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x1_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0713").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x1_unpack16");
-        assert_eq!(target.abi_id, "i0713");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x1_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0714").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x2_raw");
-        assert_eq!(target.abi_id, "i0714");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x2_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0715").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x2_unpack16");
-        assert_eq!(target.abi_id, "i0715");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x2_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0716").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x4_raw");
-        assert_eq!(target.abi_id, "i0716");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x4_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0717").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x4_unpack16");
-        assert_eq!(target.abi_id, "i0717");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x4_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0718").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x8_raw");
-        assert_eq!(target.abi_id, "i0718");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x8_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0719").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x8_unpack16");
-        assert_eq!(target.abi_id, "i0719");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x8_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0720").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x16_raw");
-        assert_eq!(target.abi_id, "i0720");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x16_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0721").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x16_unpack16");
-        assert_eq!(target.abi_id, "i0721");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x16_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0722").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x32_raw");
-        assert_eq!(target.abi_id, "i0722");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x32_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0723").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x32_unpack16");
-        assert_eq!(target.abi_id, "i0723");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x32_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0724").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x64_raw");
-        assert_eq!(target.abi_id, "i0724");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x64_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0725").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x64_unpack16");
-        assert_eq!(target.abi_id, "i0725");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x64_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0726").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x128_raw");
-        assert_eq!(target.abi_id, "i0726");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x128_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0727").unwrap();
-        assert_eq!(target.id, "tcgen05_st_32x32b_x128_unpack16");
-        assert_eq!(target.abi_id, "i0727");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x128_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0728").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x1_raw");
-        assert_eq!(target.abi_id, "i0728");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x1_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0729").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x1_pack16");
-        assert_eq!(target.abi_id, "i0729");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x1_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0730").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x2_raw");
-        assert_eq!(target.abi_id, "i0730");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x2_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0731").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x2_pack16");
-        assert_eq!(target.abi_id, "i0731");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x2_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0732").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x4_raw");
-        assert_eq!(target.abi_id, "i0732");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x4_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0733").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x4_pack16");
-        assert_eq!(target.abi_id, "i0733");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x4_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0734").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x8_raw");
-        assert_eq!(target.abi_id, "i0734");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x8_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0735").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x8_pack16");
-        assert_eq!(target.abi_id, "i0735");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x8_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0736").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x16_raw");
-        assert_eq!(target.abi_id, "i0736");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x16_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0737").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x16_pack16");
-        assert_eq!(target.abi_id, "i0737");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x16_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0738").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x32_raw");
-        assert_eq!(target.abi_id, "i0738");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x32_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0739").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x32_pack16");
-        assert_eq!(target.abi_id, "i0739");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x32_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0740").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x64_raw");
-        assert_eq!(target.abi_id, "i0740");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x64_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0741").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x64_pack16");
-        assert_eq!(target.abi_id, "i0741");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x64_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0742").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x128_raw");
-        assert_eq!(target.abi_id, "i0742");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x128_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0743").unwrap();
-        assert_eq!(target.id, "tcgen05_ld_16x32bx2_x128_pack16");
-        assert_eq!(target.abi_id, "i0743");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x128_pack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg2>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0744").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x1_raw");
-        assert_eq!(target.abi_id, "i0744");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x1_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0745").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x1_unpack16");
-        assert_eq!(target.abi_id, "i0745");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x1_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0746").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x2_raw");
-        assert_eq!(target.abi_id, "i0746");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x2_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0747").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x2_unpack16");
-        assert_eq!(target.abi_id, "i0747");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x2_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0748").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x4_raw");
-        assert_eq!(target.abi_id, "i0748");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x4_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0749").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x4_unpack16");
-        assert_eq!(target.abi_id, "i0749");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x4_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0750").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x8_raw");
-        assert_eq!(target.abi_id, "i0750");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x8_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0751").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x8_unpack16");
-        assert_eq!(target.abi_id, "i0751");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x8_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0752").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x16_raw");
-        assert_eq!(target.abi_id, "i0752");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x16_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0753").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x16_unpack16");
-        assert_eq!(target.abi_id, "i0753");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x16_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0754").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x32_raw");
-        assert_eq!(target.abi_id, "i0754");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x32_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0755").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x32_unpack16");
-        assert_eq!(target.abi_id, "i0755");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x32_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0756").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x64_raw");
-        assert_eq!(target.abi_id, "i0756");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x64_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0757").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x64_unpack16");
-        assert_eq!(target.abi_id, "i0757");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x64_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0758").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x128_raw");
-        assert_eq!(target.abi_id, "i0758");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x128_raw");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0759").unwrap();
-        assert_eq!(target.id, "tcgen05_st_16x32bx2_x128_unpack16");
-        assert_eq!(target.abi_id, "i0759");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x128_unpack16");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "ImmArg<arg3>",
-                "IntrArgMemOnly",
-                "IntrConvergent",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0760").unwrap();
-        assert_eq!(target.id, "tcgen05_commit_multicast");
-        assert_eq!(target.abi_id, "i0760");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_commit_multicast");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_COMMIT_S64_CG1_MC",
-                asm: "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOrArgMemOnly",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0761").unwrap();
-        assert_eq!(target.id, "tcgen05_shift_down");
-        assert_eq!(target.abi_id, "i0761");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_shift_down");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_SHIFT_CG1",
-                asm: "tcgen05.shift.cta_group::1.down \t[$tmem_addr];",
-                predicates: &["Subtarget->hasTcgen05ShiftSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0762").unwrap();
-        assert_eq!(target.id, "tcgen05_shift_down_cg2");
-        assert_eq!(target.abi_id, "i0762");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_shift_down_cg2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TCGEN05_SHIFT_CG2",
-                asm: "tcgen05.shift.cta_group::2.down \t[$tmem_addr];",
-                predicates: &["Subtarget->hasTcgen05ShiftSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0763").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_shared");
-        assert_eq!(target.abi_id, "i0763");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::Shared,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22502",
-                    asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22504",
-                    asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22506",
-                    asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22508",
-                    asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22510",
-                    asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22512",
-                    asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22514",
-                    asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22516",
-                    asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22518",
-                    asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22520",
-                    asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22522",
-                    asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22524",
-                    asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22526",
-                    asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22528",
-                    asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22530",
-                    asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22532",
-                    asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22534",
-                    asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22535",
-                    asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22536",
-                    asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22537",
-                    asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22538",
-                    asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22539",
-                    asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22540",
-                    asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22541",
-                    asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22542",
-                    asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22543",
-                    asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22544",
-                    asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22545",
-                    asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22546",
-                    asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22547",
-                    asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22548",
-                    asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22549",
-                    asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0764").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_tensor");
-        assert_eq!(target.abi_id, "i0764");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::Tensor,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22406",
-                    asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22410",
-                    asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22414",
-                    asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22418",
-                    asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22422",
-                    asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22426",
-                    asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22430",
-                    asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22434",
-                    asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22438",
-                    asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22442",
-                    asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22446",
-                    asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22450",
-                    asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22454",
-                    asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22458",
-                    asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22462",
-                    asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22466",
-                    asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22470",
-                    asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22472",
-                    asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22474",
-                    asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22476",
-                    asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22478",
-                    asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22480",
-                    asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22482",
-                    asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22484",
-                    asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22486",
-                    asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22488",
-                    asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22490",
-                    asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22492",
-                    asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22494",
-                    asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22496",
-                    asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22498",
-                    asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22500",
-                    asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ArgInfo<arg5>",
-                "ArgInfo<arg6>",
-                "ArgInfo<arg7>",
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0765").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_tensor_ashift");
-        assert_eq!(target.abi_id, "i0765");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::TensorAshift,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22407",
-                    asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22411",
-                    asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22423",
-                    asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22427",
-                    asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22439",
-                    asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22443",
-                    asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22455",
-                    asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22459",
-                    asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22471",
-                    asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22473",
-                    asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22479",
-                    asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22481",
-                    asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22487",
-                    asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22489",
-                    asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22495",
-                    asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22497",
-                    asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,2>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0766").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_sp_shared");
-        assert_eq!(target.abi_id, "i0766");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::SpShared,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22646",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22648",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22650",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22652",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22654",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22656",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22658",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22660",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22662",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22664",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22666",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22668",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22670",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22672",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22674",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22676",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22678",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22679",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22680",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22681",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22682",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22683",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22684",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22685",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22686",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22687",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22688",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22689",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22690",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22691",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22692",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22693",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,1,3>",
-                "Range<arg8,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0767").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_sp_tensor");
-        assert_eq!(target.abi_id, "i0767");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::SpTensor,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22550",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22554",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22558",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22562",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22566",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22570",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22574",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22578",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22582",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22586",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22590",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22594",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22598",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22602",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22606",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22610",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22614",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22616",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22618",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22620",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22622",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22624",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22626",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22628",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22630",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22632",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22634",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22636",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22638",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22640",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22642",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22644",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,1,3>",
-                "Range<arg8,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0768").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_sp_tensor_ashift");
-        assert_eq!(target.abi_id, "i0768");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::SpTensorAshift,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22551",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22555",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22567",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22571",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22583",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22587",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22599",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22603",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22615",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22617",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22623",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22625",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22631",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22633",
-                    asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22639",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_22641",
-                    asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,1,3>",
-                "Range<arg8,0,2>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0769").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_shared");
-        assert_eq!(target.abi_id, "i0769");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsShared,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23232",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23234",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23236",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23238",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23240",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23242",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23244",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23246",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23248",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23250",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23252",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23254",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23256",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23258",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23260",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23262",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23264",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23266",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23268",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23270",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23272",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23274",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23276",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23278",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23280",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23282",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23284",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23286",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23288",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23290",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23292",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23294",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23296",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23298",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23300",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23302",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23304",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23306",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23308",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23310",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23312",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23314",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23316",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23318",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23320",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23322",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23324",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23326",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23328",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23330",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23332",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23334",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23336",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23338",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23340",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23342",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23344",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23346",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23348",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23350",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23352",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23354",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23356",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23358",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0770").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_shared_zero_col_mask");
-        assert_eq!(target.abi_id, "i0770");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsSharedZeroColMask,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23233",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23235",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23237",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23239",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23241",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23243",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23245",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23247",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23249",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23251",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23253",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23255",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23257",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23259",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23261",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23263",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23265",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23267",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23269",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23271",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23273",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23275",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23277",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23279",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23281",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23283",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23285",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23287",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23289",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23291",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23293",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23295",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23297",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23299",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23301",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23303",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23305",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23307",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23309",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23311",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23313",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23315",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23317",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23319",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23321",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23323",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23325",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23327",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23329",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23331",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23333",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23335",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23337",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23339",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23341",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23343",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23345",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23347",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23349",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23351",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23353",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23355",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23357",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23359",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0771").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_sp_shared");
-        assert_eq!(target.abi_id, "i0771");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsSpShared,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23488",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23490",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23492",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23494",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23496",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23498",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23500",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23502",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23504",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23506",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23508",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23510",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23512",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23514",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23516",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23518",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23520",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23522",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23524",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23526",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23528",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23530",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23532",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23534",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23536",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23538",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23540",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23542",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23544",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23546",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23548",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23550",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23552",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23554",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23556",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23558",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23560",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23562",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23564",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23566",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23568",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23570",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23572",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23574",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23576",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23578",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23580",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23582",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23584",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23586",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23588",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23590",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23592",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23594",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23596",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23598",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23600",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23602",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23604",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23606",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23608",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23610",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23612",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23614",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0772").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_sp_shared_zero_col_mask");
-        assert_eq!(target.abi_id, "i0772");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsSpSharedZeroColMask,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23489",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23491",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23493",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23495",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23497",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23499",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23501",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23503",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23505",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23507",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23509",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23511",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23513",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23515",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23517",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23519",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23521",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23523",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23525",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23527",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23529",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23531",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23533",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23535",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23537",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23539",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23541",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23543",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23545",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23547",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23549",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23551",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23553",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23555",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23557",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23559",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23561",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23563",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23565",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23567",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23569",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23571",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23573",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23575",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23577",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23579",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23581",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23583",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23585",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23587",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23589",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23591",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23593",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23595",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23597",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23599",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23601",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23603",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23605",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23607",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23609",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23611",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23613",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23615",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrArgMemOnly",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "Range<arg9,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0773").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_sp_tensor");
-        assert_eq!(target.abi_id, "i0773");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsSpTensor,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23616",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23618",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23620",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23622",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23624",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23626",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23628",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23630",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23632",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23634",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23636",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23638",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23640",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23642",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23644",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23646",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23648",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23650",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23652",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23654",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23656",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23658",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23660",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23662",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23664",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23666",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23668",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23670",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23672",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23674",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23676",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23678",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23680",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23682",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23684",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23686",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23688",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23690",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23692",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23694",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23696",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23698",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23700",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23702",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23704",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23706",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23708",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23710",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23712",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23714",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23716",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23718",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23720",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23722",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23724",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23726",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23728",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23730",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23732",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23734",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23736",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23738",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23740",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23742",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0774").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_sp_tensor_zero_col_mask");
-        assert_eq!(target.abi_id, "i0774");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsSpTensorZeroColMask,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23617",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23619",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23621",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23623",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23625",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23627",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23629",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23631",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23633",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23635",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23637",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23639",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23641",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23643",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23645",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23647",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23649",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23651",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23653",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23655",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23657",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23659",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23661",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23663",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23665",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23667",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23669",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23671",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23673",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23675",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23677",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23679",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23681",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23683",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23685",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23687",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23689",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23691",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23693",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23695",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23697",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23699",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23701",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23703",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23705",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23707",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23709",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23711",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23713",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23715",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23717",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23719",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23721",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23723",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23725",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23727",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23729",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23731",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23733",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23735",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23737",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23739",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23741",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23743",
-                    asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "ImmArg<arg9>",
-                "IntrArgMemOnly",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "Range<arg9,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0775").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_tensor");
-        assert_eq!(target.abi_id, "i0775");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsTensor,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23360",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23362",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23364",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23366",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23368",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23370",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23372",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23374",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23376",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23378",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23380",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23382",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23384",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23386",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23388",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23390",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23392",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23394",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23396",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23398",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23400",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23402",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23404",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23406",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23408",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23410",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23412",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23414",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23416",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23418",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23420",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23422",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23424",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23426",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23428",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23430",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23432",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23434",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23436",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23438",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23440",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23442",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23444",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23446",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23448",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23450",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23452",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23454",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23456",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23458",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23460",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23462",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23464",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23466",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23468",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23470",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23472",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23474",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23476",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23478",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23480",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23482",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23484",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23486",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0776").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_tensor_zero_col_mask");
-        assert_eq!(target.abi_id, "i0776");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsTensorZeroColMask,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f16",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "f8f6f4",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "i8",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                            ],
-                        },
-                        GeneratedTargetContract {
-                            selectors: &[GeneratedTargetSelectorBinding {
-                                name: "kind",
-                                value: "tf32",
-                            }],
-                            alternatives: &[
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                                },
-                                GeneratedTargetAlternative {
-                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                                },
-                            ],
-                        },
-                    ],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        101,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(101),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f16",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "f8f6f4",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "i8",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                        ],
-                                    },
-                                    GeneratedTargetContract {
-                                        selectors: &[GeneratedTargetSelectorBinding {
-                                            name: "kind",
-                                            value: "tf32",
-                                        }],
-                                        alternatives: &[
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        100,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(100),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        103,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(103),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::ExactArchitecture(
-                                                        110,
-                                                    ),
-                                            },
-                                            GeneratedTargetAlternative {
-                                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                                hardware:
-                                                    GeneratedHardwareAlternative::FamilyTarget(110),
-                                            },
-                                        ],
-                                    },
-                                ],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23361",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23363",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23365",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23367",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23369",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23371",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23373",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23375",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23377",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23379",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23381",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23383",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23385",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23387",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23389",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23391",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23393",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23395",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23397",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23399",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23401",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23403",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23405",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23407",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23409",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23411",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23413",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23415",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23417",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23419",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23421",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23423",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23425",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23427",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23429",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23431",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23433",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23435",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23437",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23439",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23441",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23443",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23445",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23447",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23449",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23451",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23453",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23455",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23457",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23459",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23461",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23463",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23465",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23467",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23469",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23471",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23473",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23475",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23477",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23479",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23481",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23483",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23485",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "anonymous_23487",
-                    asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
-                    predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "ImmArg<arg8>",
-                "IntrArgMemOnly",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "Range<arg8,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0777").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_e4m3");
-        assert_eq!(target.abi_id, "i0777");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsTensor,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    }],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                101,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_23424",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0778").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_e5m2");
-        assert_eq!(target.abi_id, "i0778");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsTensor,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    }],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                101,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_23424",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0779").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_e2m3");
-        assert_eq!(target.abi_id, "i0779");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsTensor,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    }],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                101,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_23424",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0780").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_e3m2");
-        assert_eq!(target.abi_id, "i0780");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsTensor,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    }],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                101,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_23424",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0781").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_ws_e2m1");
-        assert_eq!(target.abi_id, "i0781");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::WsTensor,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    }],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                101,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_23424",
-                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,0,4>",
-                "Range<arg7,0,4>",
-                "ReadOnly<arg1>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0782").unwrap();
-        assert_eq!(target.id, "sin_approx_f32");
-        assert_eq!(target.abi_id, "i0782");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0783").unwrap();
-        assert_eq!(target.id, "sin_approx_ftz_f32");
-        assert_eq!(target.abi_id, "i0783");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0784").unwrap();
-        assert_eq!(target.id, "cos_approx_f32");
-        assert_eq!(target.abi_id, "i0784");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0785").unwrap();
-        assert_eq!(target.id, "cos_approx_ftz_f32");
-        assert_eq!(target.abi_id, "i0785");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0786").unwrap();
-        assert_eq!(target.id, "lg2_approx_f32");
-        assert_eq!(target.abi_id, "i0786");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0787").unwrap();
-        assert_eq!(target.id, "lg2_approx_ftz_f32");
-        assert_eq!(target.abi_id, "i0787");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0788").unwrap();
-        assert_eq!(target.id, "rcp_approx_ftz_f32");
-        assert_eq!(target.abi_id, "i0788");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_APPROX_FTZ_F",
-                asm: "rcp.approx.ftz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0789").unwrap();
-        assert_eq!(target.id, "rcp_rn_f32");
-        assert_eq!(target.abi_id, "i0789");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RN_F",
-                asm: "rcp.rn.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0790").unwrap();
-        assert_eq!(target.id, "rcp_rn_ftz_f32");
-        assert_eq!(target.abi_id, "i0790");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RN_FTZ_F",
-                asm: "rcp.rn.ftz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0791").unwrap();
-        assert_eq!(target.id, "rcp_rz_f32");
-        assert_eq!(target.abi_id, "i0791");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RZ_F",
-                asm: "rcp.rz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0792").unwrap();
-        assert_eq!(target.id, "rcp_rz_ftz_f32");
-        assert_eq!(target.abi_id, "i0792");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RZ_FTZ_F",
-                asm: "rcp.rz.ftz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0793").unwrap();
-        assert_eq!(target.id, "rcp_rm_f32");
-        assert_eq!(target.abi_id, "i0793");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RM_F",
-                asm: "rcp.rm.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0794").unwrap();
-        assert_eq!(target.id, "rcp_rm_ftz_f32");
-        assert_eq!(target.abi_id, "i0794");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RM_FTZ_F",
-                asm: "rcp.rm.ftz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0795").unwrap();
-        assert_eq!(target.id, "rcp_rp_f32");
-        assert_eq!(target.abi_id, "i0795");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RP_F",
-                asm: "rcp.rp.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0796").unwrap();
-        assert_eq!(target.id, "rcp_rp_ftz_f32");
-        assert_eq!(target.abi_id, "i0796");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RP_FTZ_F",
-                asm: "rcp.rp.ftz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0797").unwrap();
-        assert_eq!(target.id, "rcp_approx_ftz_f64");
-        assert_eq!(target.abi_id, "i0797");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_APPROX_FTZ_D",
-                asm: "rcp.approx.ftz.f64 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0798").unwrap();
-        assert_eq!(target.id, "rcp_rn_f64");
-        assert_eq!(target.abi_id, "i0798");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RN_D",
-                asm: "rcp.rn.f64 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0799").unwrap();
-        assert_eq!(target.id, "rcp_rz_f64");
-        assert_eq!(target.abi_id, "i0799");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RZ_D",
-                asm: "rcp.rz.f64 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0800").unwrap();
-        assert_eq!(target.id, "rcp_rm_f64");
-        assert_eq!(target.abi_id, "i0800");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RM_D",
-                asm: "rcp.rm.f64 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0801").unwrap();
-        assert_eq!(target.id, "rcp_rp_f64");
-        assert_eq!(target.abi_id, "i0801");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_RCP_RP_D",
-                asm: "rcp.rp.f64 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0802").unwrap();
-        assert_eq!(target.id, "rsqrt_approx_f32");
-        assert_eq!(target.abi_id, "i0802");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0803").unwrap();
-        assert_eq!(target.id, "rsqrt_approx_ftz_f32");
-        assert_eq!(target.abi_id, "i0803");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0804").unwrap();
-        assert_eq!(target.id, "rsqrt_approx_f64");
-        assert_eq!(target.abi_id, "i0804");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0805").unwrap();
-        assert_eq!(target.id, "sqrt_approx_f32");
-        assert_eq!(target.abi_id, "i0805");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_APPROX_F",
-                asm: "sqrt.approx.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0806").unwrap();
-        assert_eq!(target.id, "sqrt_approx_ftz_f32");
-        assert_eq!(target.abi_id, "i0806");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_APPROX_FTZ_F",
-                asm: "sqrt.approx.ftz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0807").unwrap();
-        assert_eq!(target.id, "sqrt_rn_f32");
-        assert_eq!(target.abi_id, "i0807");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RN_F",
-                asm: "sqrt.rn.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0808").unwrap();
-        assert_eq!(target.id, "sqrt_rn_ftz_f32");
-        assert_eq!(target.abi_id, "i0808");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RN_FTZ_F",
-                asm: "sqrt.rn.ftz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0809").unwrap();
-        assert_eq!(target.id, "sqrt_rz_f32");
-        assert_eq!(target.abi_id, "i0809");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RZ_F",
-                asm: "sqrt.rz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0810").unwrap();
-        assert_eq!(target.id, "sqrt_rz_ftz_f32");
-        assert_eq!(target.abi_id, "i0810");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RZ_FTZ_F",
-                asm: "sqrt.rz.ftz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0811").unwrap();
-        assert_eq!(target.id, "sqrt_rm_f32");
-        assert_eq!(target.abi_id, "i0811");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RM_F",
-                asm: "sqrt.rm.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0812").unwrap();
-        assert_eq!(target.id, "sqrt_rm_ftz_f32");
-        assert_eq!(target.abi_id, "i0812");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RM_FTZ_F",
-                asm: "sqrt.rm.ftz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0813").unwrap();
-        assert_eq!(target.id, "sqrt_rp_f32");
-        assert_eq!(target.abi_id, "i0813");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RP_F",
-                asm: "sqrt.rp.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0814").unwrap();
-        assert_eq!(target.id, "sqrt_rp_ftz_f32");
-        assert_eq!(target.abi_id, "i0814");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RP_FTZ_F",
-                asm: "sqrt.rp.ftz.f32 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0815").unwrap();
-        assert_eq!(target.id, "sqrt_rn_f64");
-        assert_eq!(target.abi_id, "i0815");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RN_D",
-                asm: "sqrt.rn.f64 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0816").unwrap();
-        assert_eq!(target.id, "sqrt_rz_f64");
-        assert_eq!(target.abi_id, "i0816");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RZ_D",
-                asm: "sqrt.rz.f64 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0817").unwrap();
-        assert_eq!(target.id, "sqrt_rm_f64");
-        assert_eq!(target.abi_id, "i0817");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RM_D",
-                asm: "sqrt.rm.f64 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0818").unwrap();
-        assert_eq!(target.id, "sqrt_rp_f64");
-        assert_eq!(target.abi_id, "i0818");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_SQRT_RP_D",
-                asm: "sqrt.rp.f64 \t$dst, $src0;",
-                predicates: &[],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0819").unwrap();
-        assert_eq!(target.id, "ex2_approx_f32");
-        assert_eq!(target.abi_id, "i0819");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0820").unwrap();
-        assert_eq!(target.id, "ex2_approx_ftz_f32");
-        assert_eq!(target.abi_id, "i0820");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        let target = generated_intrinsic_target_by_marker("v1:i0821").unwrap();
-        assert_eq!(target.id, "tanh_approx_f32");
-        assert_eq!(target.abi_id, "i0821");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0822").unwrap();
-        assert_eq!(target.id, "cvt_rn_satfinite_e4m3x2_f16x2");
-        assert_eq!(target.abi_id, "i0822");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_e4m3x2_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0823").unwrap();
-        assert_eq!(target.id, "cvt_rn_satfinite_relu_e4m3x2_f16x2");
-        assert_eq!(target.abi_id, "i0823");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_relu_e4m3x2_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0824").unwrap();
-        assert_eq!(target.id, "cvt_rn_satfinite_e5m2x2_f16x2");
-        assert_eq!(target.abi_id, "i0824");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_e5m2x2_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0825").unwrap();
-        assert_eq!(target.id, "cvt_rn_satfinite_relu_e5m2x2_f16x2");
-        assert_eq!(target.abi_id, "i0825");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_relu_e5m2x2_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0826").unwrap();
-        assert_eq!(target.id, "cvt_rn_f16x2_e4m3x2");
-        assert_eq!(target.abi_id, "i0826");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_f16x2_e4m3x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0827").unwrap();
-        assert_eq!(target.id, "cvt_rn_relu_f16x2_e4m3x2");
-        assert_eq!(target.abi_id, "i0827");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_relu_f16x2_e4m3x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0828").unwrap();
-        assert_eq!(target.id, "cvt_rn_f16x2_e5m2x2");
-        assert_eq!(target.abi_id, "i0828");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_f16x2_e5m2x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0829").unwrap();
-        assert_eq!(target.id, "cvt_rn_relu_f16x2_e5m2x2");
-        assert_eq!(target.abi_id, "i0829");
-        assert_eq!(target.dialect_op, "nvvm.cvt_rn_relu_f16x2_e5m2x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(89),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0830").unwrap();
-        assert_eq!(target.id, "min_f16");
-        assert_eq!(target.abi_id, "i0830");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_f16",
-                asm: "min.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0831").unwrap();
-        assert_eq!(target.id, "min_ftz_f16");
-        assert_eq!(target.abi_id, "i0831");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_ftz_f16",
-                asm: "min.ftz.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0832").unwrap();
-        assert_eq!(target.id, "min_nan_f16");
-        assert_eq!(target.abi_id, "i0832");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_NaN_f16",
-                asm: "min.NaN.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0833").unwrap();
-        assert_eq!(target.id, "min_ftz_nan_f16");
-        assert_eq!(target.abi_id, "i0833");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_ftz_NaN_f16",
-                asm: "min.ftz.NaN.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0834").unwrap();
-        assert_eq!(target.id, "min_xorsign_abs_f16");
-        assert_eq!(target.abi_id, "i0834");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_xorsign_abs_f16",
-                asm: "min.xorsign.abs.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0835").unwrap();
-        assert_eq!(target.id, "min_ftz_xorsign_abs_f16");
-        assert_eq!(target.abi_id, "i0835");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_ftz_xorsign_abs_f16",
-                asm: "min.ftz.xorsign.abs.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0836").unwrap();
-        assert_eq!(target.id, "min_nan_xorsign_abs_f16");
-        assert_eq!(target.abi_id, "i0836");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_f16",
-                asm: "min.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0837").unwrap();
-        assert_eq!(target.id, "min_ftz_nan_xorsign_abs_f16");
-        assert_eq!(target.abi_id, "i0837");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_ftz_NaN_xorsign_abs_f16",
-                asm: "min.ftz.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0838").unwrap();
-        assert_eq!(target.id, "min_bf16");
-        assert_eq!(target.abi_id, "i0838");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_bf16",
-                asm: "min.bf16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0839").unwrap();
-        assert_eq!(target.id, "min_nan_bf16");
-        assert_eq!(target.abi_id, "i0839");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_NaN_bf16",
-                asm: "min.NaN.bf16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0840").unwrap();
-        assert_eq!(target.id, "min_xorsign_abs_bf16");
-        assert_eq!(target.abi_id, "i0840");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_xorsign_abs_bf16",
-                asm: "min.xorsign.abs.bf16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0841").unwrap();
-        assert_eq!(target.id, "min_nan_xorsign_abs_bf16");
-        assert_eq!(target.abi_id, "i0841");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16,
-                operation: GeneratedExtendedMinMaxOperation::Min,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_bf16",
-                asm: "min.NaN.xorsign.abs.bf16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0842").unwrap();
-        assert_eq!(target.id, "max_f16");
-        assert_eq!(target.abi_id, "i0842");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_f16",
-                asm: "max.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0843").unwrap();
-        assert_eq!(target.id, "max_ftz_f16");
-        assert_eq!(target.abi_id, "i0843");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_ftz_f16",
-                asm: "max.ftz.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0844").unwrap();
-        assert_eq!(target.id, "max_nan_f16");
-        assert_eq!(target.abi_id, "i0844");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_NaN_f16",
-                asm: "max.NaN.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0845").unwrap();
-        assert_eq!(target.id, "max_ftz_nan_f16");
-        assert_eq!(target.abi_id, "i0845");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_ftz_NaN_f16",
-                asm: "max.ftz.NaN.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0846").unwrap();
-        assert_eq!(target.id, "max_xorsign_abs_f16");
-        assert_eq!(target.abi_id, "i0846");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_xorsign_abs_f16",
-                asm: "max.xorsign.abs.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0847").unwrap();
-        assert_eq!(target.id, "max_ftz_xorsign_abs_f16");
-        assert_eq!(target.abi_id, "i0847");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_ftz_xorsign_abs_f16",
-                asm: "max.ftz.xorsign.abs.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0848").unwrap();
-        assert_eq!(target.id, "max_nan_xorsign_abs_f16");
-        assert_eq!(target.abi_id, "i0848");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_f16",
-                asm: "max.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0849").unwrap();
-        assert_eq!(target.id, "max_ftz_nan_xorsign_abs_f16");
-        assert_eq!(target.abi_id, "i0849");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::F16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_ftz_NaN_xorsign_abs_f16",
-                asm: "max.ftz.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0850").unwrap();
-        assert_eq!(target.id, "max_bf16");
-        assert_eq!(target.abi_id, "i0850");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_bf16",
-                asm: "max.bf16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0851").unwrap();
-        assert_eq!(target.id, "max_nan_bf16");
-        assert_eq!(target.abi_id, "i0851");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: false
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_NaN_bf16",
-                asm: "max.NaN.bf16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0852").unwrap();
-        assert_eq!(target.id, "max_xorsign_abs_bf16");
-        assert_eq!(target.abi_id, "i0852");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Number,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_xorsign_abs_bf16",
-                asm: "max.xorsign.abs.bf16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0853").unwrap();
-        assert_eq!(target.id, "max_nan_xorsign_abs_bf16");
-        assert_eq!(target.abi_id, "i0853");
-        assert_eq!(target.dialect_op, "nvvm.extended_minmax");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::ExtendedMinMax {
-                format: GeneratedExtendedMinMaxFormat::Bf16,
-                operation: GeneratedExtendedMinMaxOperation::Max,
-                subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
-                nan: GeneratedExtendedMinMaxNan::Nan,
-                xorsign_abs: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(86),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_bf16",
-                asm: "max.NaN.xorsign.abs.bf16 \t$dst, $src0, $src1;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 72",
-                    "Subtarget->getSmVersion() >= 86"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0854").unwrap();
-        assert_eq!(target.id, "fma_ftz_f16x2");
-        assert_eq!(target.abi_id, "i0854");
-        assert_eq!(target.dialect_op, "nvvm.fma_ftz_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_ftz_f16x2",
-                asm: "fma.rn.ftz.f16x2 \t$dst, $src0, $src1, $src2;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 53",
-                    "Subtarget->getPTXVersion() >= 42"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0855").unwrap();
-        assert_eq!(target.id, "fma_sat_f16x2");
-        assert_eq!(target.abi_id, "i0855");
-        assert_eq!(target.dialect_op, "nvvm.fma_sat_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_sat_f16x2",
-                asm: "fma.rn.sat.f16x2 \t$dst, $src0, $src1, $src2;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 53",
-                    "Subtarget->getPTXVersion() >= 42"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0856").unwrap();
-        assert_eq!(target.id, "fma_ftz_sat_f16x2");
-        assert_eq!(target.abi_id, "i0856");
-        assert_eq!(target.dialect_op, "nvvm.fma_ftz_sat_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(70),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_ftz_sat_f16x2",
-                asm: "fma.rn.ftz.sat.f16x2 \t$dst, $src0, $src1, $src2;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 53",
-                    "Subtarget->getPTXVersion() >= 42"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0857").unwrap();
-        assert_eq!(target.id, "fma_ftz_relu_f16x2");
-        assert_eq!(target.abi_id, "i0857");
-        assert_eq!(target.dialect_op, "nvvm.fma_ftz_relu_f16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(80),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_NVVM_FMA_rn_ftz_relu_f16x2",
-                asm: "fma.rn.ftz.relu.f16x2 \t$dst, $src0, $src1, $src2;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 80",
-                    "Subtarget->getPTXVersion() >= 70"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoMem", "IntrSpeculatable"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0858").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1");
-        assert_eq!(target.abi_id, "i0858");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19651",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0859").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3");
-        assert_eq!(target.abi_id, "i0859");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19656",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0860").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2");
-        assert_eq!(target.abi_id, "i0860");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19661",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0861").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3");
-        assert_eq!(target.abi_id, "i0861");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19671",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0862").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2");
-        assert_eq!(target.abi_id, "i0862");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m1,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19666",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0863").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1");
-        assert_eq!(target.abi_id, "i0863");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19676",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0864").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3");
-        assert_eq!(target.abi_id, "i0864");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19680",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0865").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2");
-        assert_eq!(target.abi_id, "i0865");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19684",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0866").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3");
-        assert_eq!(target.abi_id, "i0866");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19692",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0867").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2");
-        assert_eq!(target.abi_id, "i0867");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E2m3,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19688",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0868").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1");
-        assert_eq!(target.abi_id, "i0868");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19697",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0869").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3");
-        assert_eq!(target.abi_id, "i0869");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19701",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0870").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2");
-        assert_eq!(target.abi_id, "i0870");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19705",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0871").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3");
-        assert_eq!(target.abi_id, "i0871");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19713",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0872").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2");
-        assert_eq!(target.abi_id, "i0872");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E3m2,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19709",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0873").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1");
-        assert_eq!(target.abi_id, "i0873");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19739",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0874").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3");
-        assert_eq!(target.abi_id, "i0874");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19743",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0875").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2");
-        assert_eq!(target.abi_id, "i0875");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19747",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0876").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3");
-        assert_eq!(target.abi_id, "i0876");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19755",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0877").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2");
-        assert_eq!(target.abi_id, "i0877");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E4m3,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19751",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0878").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1");
-        assert_eq!(target.abi_id, "i0878");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E2m1,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19718",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0879").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3");
-        assert_eq!(target.abi_id, "i0879");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E2m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19722",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0880").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2");
-        assert_eq!(target.abi_id, "i0880");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E3m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19726",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0881").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3");
-        assert_eq!(target.abi_id, "i0881");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E4m3,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19734",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0882").unwrap();
-        assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2");
-        assert_eq!(target.abi_id, "i0882");
-        assert_eq!(target.dialect_op, "nvvm.register_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::RegisterMma {
-                shape: GeneratedRegisterMmaShape::M16n8k32,
-                operation: GeneratedRegisterMmaOperation::Multiply,
-                kind: GeneratedRegisterMmaKind::Mxf8f6f4,
-                accumulator: GeneratedRegisterMmaAccumulator::F32,
-                a_element: GeneratedRegisterMmaElement::E5m2,
-                b_element: GeneratedRegisterMmaElement::E5m2,
-                a_layout: GeneratedRegisterMmaLayout::Row,
-                b_layout: GeneratedRegisterMmaLayout::Col,
-                overflow: GeneratedRegisterMmaOverflow::NotApplicable
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_19730",
-                asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
-                predicates: &["Subtarget->hasMMABlockScale()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0883").unwrap();
-        assert_eq!(target.id, "barrier_cta_sync");
-        assert_eq!(target.abi_id, "i0883");
-        assert_eq!(target.dialect_op, "nvvm.barrier_cta_sync_count");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_SYNC_ii",
-                    asm: "barrier.sync \t$i, $j;",
-                    predicates: &["Subtarget->getPTXVersion() >= 60"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_SYNC_ir",
-                    asm: "barrier.sync \t$i, $j;",
-                    predicates: &["Subtarget->getPTXVersion() >= 60"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_SYNC_ri",
-                    asm: "barrier.sync \t$i, $j;",
-                    predicates: &["Subtarget->getPTXVersion() >= 60"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_SYNC_rr",
-                    asm: "barrier.sync \t$i, $j;",
-                    predicates: &["Subtarget->getPTXVersion() >= 60"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0884").unwrap();
-        assert_eq!(target.id, "barrier_cta_sync_aligned");
-        assert_eq!(target.abi_id, "i0884");
-        assert_eq!(target.dialect_op, "nvvm.barrier_cta_sync_aligned_count");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_SYNC_ALIGNED_ii",
-                    asm: "bar.sync \t$i, $j;",
-                    predicates: &[],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_SYNC_ALIGNED_ir",
-                    asm: "bar.sync \t$i, $j;",
-                    predicates: &[],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_SYNC_ALIGNED_ri",
-                    asm: "bar.sync \t$i, $j;",
-                    predicates: &[],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_SYNC_ALIGNED_rr",
-                    asm: "bar.sync \t$i, $j;",
-                    predicates: &[],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0885").unwrap();
-        assert_eq!(target.id, "barrier_cta_arrive");
-        assert_eq!(target.abi_id, "i0885");
-        assert_eq!(target.dialect_op, "nvvm.barrier_cta_arrive_count");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(30),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_ARRIVE_ii",
-                    asm: "barrier.arrive \t$i, $j;",
-                    predicates: &["Subtarget->getPTXVersion() >= 60"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_ARRIVE_ir",
-                    asm: "barrier.arrive \t$i, $j;",
-                    predicates: &["Subtarget->getPTXVersion() >= 60"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_ARRIVE_ri",
-                    asm: "barrier.arrive \t$i, $j;",
-                    predicates: &["Subtarget->getPTXVersion() >= 60"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_ARRIVE_rr",
-                    asm: "barrier.arrive \t$i, $j;",
-                    predicates: &["Subtarget->getPTXVersion() >= 60"],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0886").unwrap();
-        assert_eq!(target.id, "barrier_cta_arrive_aligned");
-        assert_eq!(target.abi_id, "i0886");
-        assert_eq!(target.dialect_op, "nvvm.barrier_cta_arrive_aligned_count");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::All }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(32),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(20),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ii",
-                    asm: "bar.arrive \t$i, $j;",
-                    predicates: &[],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ir",
-                    asm: "bar.arrive \t$i, $j;",
-                    predicates: &[],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ri",
-                    asm: "bar.arrive \t$i, $j;",
-                    predicates: &[],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-                GeneratedSelectionAlternative {
-                    source_record: "BARRIER_CTA_ARRIVE_ALIGNED_rr",
-                    asm: "bar.arrive \t$i, $j;",
-                    predicates: &[],
-                    constraints: GeneratedSelectionConstraints {
-                        address_space: None,
-                        immediate_bindings: &[]
-                    }
-                },
-            ]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrConvergent", "IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0887").unwrap();
-        assert_eq!(target.id, "prefetch_tma_descriptor");
-        assert_eq!(target.abi_id, "i0887");
-        assert_eq!(target.dialect_op, "nvvm.prefetch_tensormap");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrArgMemOnly", "NoCapture<arg0>", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0888").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_1d_l2");
-        assert_eq!(target.abi_id, "i0888");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_1d_l2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_1D",
-                asm: "cp.async.bulk.prefetch.tensor.1d.L2.global.tile [$tmap, {{$d0}}];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 3,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg3>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0889").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_2d_l2");
-        assert_eq!(target.abi_id, "i0889");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_2d_l2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_2D",
-                asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile [$tmap, {{$d0, $d1}}];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 4,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg4>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0890").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_3d_l2");
-        assert_eq!(target.abi_id, "i0890");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_3d_l2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_3D",
-                asm: "cp.async.bulk.prefetch.tensor.3d.L2.global.tile [$tmap, {{$d0, $d1, $d2}}];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 5,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg5>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0891").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_4d_l2");
-        assert_eq!(target.abi_id, "i0891");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_4d_l2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_4D",
-                asm: "cp.async.bulk.prefetch.tensor.4d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3}}];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 6,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg6>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0892").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_5d_l2");
-        assert_eq!(target.abi_id, "i0892");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_5d_l2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_5D",
-                asm: "cp.async.bulk.prefetch.tensor.5d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 7,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0893").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_gather4_2d_l2");
-        assert_eq!(target.abi_id, "i0893");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_GATHER4_2D",
-                asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4 [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
-                predicates: &["Subtarget->hasTMABlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 7,
-                        value: 0
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0894").unwrap();
-        assert_eq!(target.id, "tensormap_replace_box_dim");
-        assert_eq!(target.abi_id, "i0894");
-        assert_eq!(target.dialect_op, "nvvm.tensormap_replace_box_dim");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0895").unwrap();
-        assert_eq!(target.id, "tensormap_replace_element_stride");
-        assert_eq!(target.abi_id, "i0895");
-        assert_eq!(target.dialect_op, "nvvm.tensormap_replace_element_stride");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0896").unwrap();
-        assert_eq!(target.id, "tensormap_replace_element_type");
-        assert_eq!(target.abi_id, "i0896");
-        assert_eq!(target.dialect_op, "nvvm.tensormap_replace_element_type");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ArgInfo<arg1>",
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "Range<arg1,0,16>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0897").unwrap();
-        assert_eq!(target.id, "tensormap_replace_fill_mode");
-        assert_eq!(target.abi_id, "i0897");
-        assert_eq!(target.dialect_op, "nvvm.tensormap_replace_fill_mode");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ArgInfo<arg1>",
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "Range<arg1,0,2>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0898").unwrap();
-        assert_eq!(target.id, "tensormap_replace_global_address");
-        assert_eq!(target.abi_id, "i0898");
-        assert_eq!(target.dialect_op, "nvvm.tensormap_replace_global_address");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrArgMemOnly", "IntrWriteMem", "NoCapture<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0899").unwrap();
-        assert_eq!(target.id, "tensormap_replace_global_dim");
-        assert_eq!(target.abi_id, "i0899");
-        assert_eq!(target.dialect_op, "nvvm.tensormap_replace_global_dim");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0900").unwrap();
-        assert_eq!(target.id, "tensormap_replace_global_stride");
-        assert_eq!(target.abi_id, "i0900");
-        assert_eq!(target.dialect_op, "nvvm.tensormap_replace_global_stride");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0901").unwrap();
-        assert_eq!(target.id, "tensormap_replace_interleave_layout");
-        assert_eq!(target.abi_id, "i0901");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tensormap_replace_interleave_layout"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ArgInfo<arg1>",
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "Range<arg1,0,3>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0902").unwrap();
-        assert_eq!(target.id, "tensormap_replace_rank");
-        assert_eq!(target.abi_id, "i0902");
-        assert_eq!(target.dialect_op, "nvvm.tensormap_replace_rank");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrArgMemOnly", "IntrWriteMem", "NoCapture<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0903").unwrap();
-        assert_eq!(target.id, "tensormap_replace_swizzle_atomicity");
-        assert_eq!(target.abi_id, "i0903");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.tensormap_replace_swizzle_atomicity"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ArgInfo<arg1>",
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "Range<arg1,0,4>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0904").unwrap();
-        assert_eq!(target.id, "tensormap_replace_swizzle_mode");
-        assert_eq!(target.abi_id, "i0904");
-        assert_eq!(target.dialect_op, "nvvm.tensormap_replace_swizzle_mode");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ArgInfo<arg1>",
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrWriteMem",
-                "NoCapture<arg0>",
-                "Range<arg1,0,5>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0905").unwrap();
-        assert_eq!(target.id, "fence_proxy_tensormap_generic_acquire_cluster");
-        assert_eq!(target.abi_id, "i0905");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_proxy_tensormap_generic_acquire_cluster"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CLUSTER",
-                asm: "fence.proxy.tensormap::generic.acquire.cluster [$addr], 128;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 83"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "Range<arg1,128,129>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0906").unwrap();
-        assert_eq!(target.id, "fence_proxy_tensormap_generic_acquire_cta");
-        assert_eq!(target.abi_id, "i0906");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_proxy_tensormap_generic_acquire_cta"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CTA",
-                asm: "fence.proxy.tensormap::generic.acquire.cta [$addr], 128;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 83"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "Range<arg1,128,129>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0907").unwrap();
-        assert_eq!(target.id, "fence_proxy_tensormap_generic_acquire_gpu");
-        assert_eq!(target.abi_id, "i0907");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_proxy_tensormap_generic_acquire_gpu"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_GPU",
-                asm: "fence.proxy.tensormap::generic.acquire.gpu [$addr], 128;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 83"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "Range<arg1,128,129>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0908").unwrap();
-        assert_eq!(target.id, "fence_proxy_tensormap_generic_acquire_system");
-        assert_eq!(target.abi_id, "i0908");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_proxy_tensormap_generic_acquire_system"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_SYS",
-                asm: "fence.proxy.tensormap::generic.acquire.sys [$addr], 128;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 83"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg1>",
-                "IntrArgMemOnly",
-                "IntrNoCallback",
-                "Range<arg1,128,129>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0909").unwrap();
-        assert_eq!(target.id, "fence_proxy_tensormap_generic_release_cluster");
-        assert_eq!(target.abi_id, "i0909");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_proxy_tensormap_generic_release_cluster"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CLUSTER",
-                asm: "fence.proxy.tensormap::generic.release.cluster;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 83"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0910").unwrap();
-        assert_eq!(target.id, "fence_proxy_tensormap_generic_release_cta");
-        assert_eq!(target.abi_id, "i0910");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_proxy_tensormap_generic_release_cta"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CTA",
-                asm: "fence.proxy.tensormap::generic.release.cta;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 83"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0911").unwrap();
-        assert_eq!(target.id, "fence_proxy_tensormap_generic_release_gpu");
-        assert_eq!(target.abi_id, "i0911");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_proxy_tensormap_generic_release_gpu"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_GPU",
-                asm: "fence.proxy.tensormap::generic.release.gpu;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 83"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0912").unwrap();
-        assert_eq!(target.id, "fence_proxy_tensormap_generic_release_system");
-        assert_eq!(target.abi_id, "i0912");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.fence_proxy_tensormap_generic_release_system"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_SYS",
-                asm: "fence.proxy.tensormap::generic.release.sys;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 83"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrNoCallback"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0913").unwrap();
-        assert_eq!(target.id, "grid_dependency_launch_dependents");
-        assert_eq!(target.abi_id, "i0913");
-        assert_eq!(target.dialect_op, "nvvm.grid_dependency_launch_dependents");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "GRIDDEPCONTROL_LAUNCH_DEPENDENTS",
-                asm: "griddepcontrol.launch_dependents;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrHasSideEffects", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0914").unwrap();
-        assert_eq!(target.id, "grid_dependency_wait");
-        assert_eq!(target.abi_id, "i0914");
-        assert_eq!(target.dialect_op, "nvvm.grid_dependency_wait");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "GRIDDEPCONTROL_WAIT",
-                asm: "griddepcontrol.wait;",
-                predicates: &[
-                    "Subtarget->getSmVersion() >= 90",
-                    "Subtarget->getPTXVersion() >= 78"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["IntrHasSideEffects", "IntrNoMem"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0915").unwrap();
-        assert_eq!(target.id, "setmaxnreg_inc");
-        assert_eq!(target.abi_id, "i0915");
-        assert_eq!(target.dialect_op, "nvvm.setmaxnreg_inc");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_22212",
-                asm: "setmaxnreg.inc.sync.aligned.u32 \t$reg_count;",
-                predicates: &["Subtarget->hasSetMaxNRegSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg0>",
-                "IntrConvergent",
-                "IntrHasSideEffects",
-                "IntrNoMem",
-                "Range<arg0,24,257>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0916").unwrap();
-        assert_eq!(target.id, "setmaxnreg_dec");
-        assert_eq!(target.abi_id, "i0916");
-        assert_eq!(target.dialect_op, "nvvm.setmaxnreg_dec");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                    GeneratedHardwareAlternative::FamilyTarget(110),
-                    GeneratedHardwareAlternative::ExactArchitecture(120),
-                    GeneratedHardwareAlternative::FamilyTarget(120),
-                    GeneratedHardwareAlternative::ExactArchitecture(121),
-                    GeneratedHardwareAlternative::FamilyTarget(121),
-                    GeneratedHardwareAlternative::ExactArchitecture(90),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::FamilyTarget(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::FamilyTarget(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                GeneratedHardwareAlternative::FamilyTarget(110),
-                                GeneratedHardwareAlternative::ExactArchitecture(120),
-                                GeneratedHardwareAlternative::FamilyTarget(120),
-                                GeneratedHardwareAlternative::ExactArchitecture(121),
-                                GeneratedHardwareAlternative::FamilyTarget(121),
-                                GeneratedHardwareAlternative::ExactArchitecture(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_22214",
-                asm: "setmaxnreg.dec.sync.aligned.u32 \t$reg_count;",
-                predicates: &["Subtarget->hasSetMaxNRegSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg0>",
-                "IntrConvergent",
-                "IntrHasSideEffects",
-                "IntrNoMem",
-                "Range<arg0,24,257>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0917").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_1d_l2_cache_hint");
-        assert_eq!(target.abi_id, "i0917");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_1D_CH",
-                asm: "cp.async.bulk.prefetch.tensor.1d.L2.global.tile.L2::cache_hint [$tmap, {{$d0}}], $ch;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 3,
-                        value: -1
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg3>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0918").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_2d_l2_cache_hint");
-        assert_eq!(target.abi_id, "i0918");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_2D_CH",
-                asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1}}], $ch;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 4,
-                        value: -1
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg4>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0919").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_3d_l2_cache_hint");
-        assert_eq!(target.abi_id, "i0919");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_3D_CH",
-                asm: "cp.async.bulk.prefetch.tensor.3d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2}}], $ch;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 5,
-                        value: -1
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg5>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0920").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_4d_l2_cache_hint");
-        assert_eq!(target.abi_id, "i0920");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_4D_CH",
-                asm: "cp.async.bulk.prefetch.tensor.4d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3}}], $ch;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 6,
-                        value: -1
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg6>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0921").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_5d_l2_cache_hint");
-        assert_eq!(target.abi_id, "i0921");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_5D_CH",
-                asm: "cp.async.bulk.prefetch.tensor.5d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
-                predicates: &[
-                    "Subtarget->getPTXVersion() >= 80",
-                    "Subtarget->getSmVersion() >= 90"
-                ],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 7,
-                        value: -1
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0922").unwrap();
-        assert_eq!(
-            target.id,
-            "cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
-        );
-        assert_eq!(target.abi_id, "i0922");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(101),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::ExactArchitecture(110),
-                ])
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "TMA_TENSOR_PF_TILE_GATHER4_2D_CH",
-                asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
-                predicates: &["Subtarget->hasTMABlackwellSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[GeneratedImmediateBinding {
-                        argument_index: 7,
-                        value: -1
-                    }]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0923").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_tile_1d");
-        assert_eq!(target.abi_id, "i0923");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_add_tile_1d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0924").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_tile_2d");
-        assert_eq!(target.abi_id, "i0924");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_add_tile_2d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0925").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_tile_3d");
-        assert_eq!(target.abi_id, "i0925");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_add_tile_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0926").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_tile_4d");
-        assert_eq!(target.abi_id, "i0926");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_add_tile_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0927").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_tile_5d");
-        assert_eq!(target.abi_id, "i0927");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_add_tile_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0928").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_im2col_3d");
-        assert_eq!(target.abi_id, "i0928");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_add_im2col_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0929").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_im2col_4d");
-        assert_eq!(target.abi_id, "i0929");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_add_im2col_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0930").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_im2col_5d");
-        assert_eq!(target.abi_id, "i0930");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_add_im2col_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0931").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_tile_1d");
-        assert_eq!(target.abi_id, "i0931");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_and_tile_1d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0932").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_tile_2d");
-        assert_eq!(target.abi_id, "i0932");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_and_tile_2d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0933").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_tile_3d");
-        assert_eq!(target.abi_id, "i0933");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_and_tile_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0934").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_tile_4d");
-        assert_eq!(target.abi_id, "i0934");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_and_tile_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0935").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_tile_5d");
-        assert_eq!(target.abi_id, "i0935");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_and_tile_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0936").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_im2col_3d");
-        assert_eq!(target.abi_id, "i0936");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_and_im2col_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0937").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_im2col_4d");
-        assert_eq!(target.abi_id, "i0937");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_and_im2col_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0938").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_im2col_5d");
-        assert_eq!(target.abi_id, "i0938");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_and_im2col_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0939").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_tile_1d");
-        assert_eq!(target.abi_id, "i0939");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_dec_tile_1d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0940").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_tile_2d");
-        assert_eq!(target.abi_id, "i0940");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_dec_tile_2d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0941").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_tile_3d");
-        assert_eq!(target.abi_id, "i0941");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_dec_tile_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0942").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_tile_4d");
-        assert_eq!(target.abi_id, "i0942");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_dec_tile_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0943").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_tile_5d");
-        assert_eq!(target.abi_id, "i0943");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_dec_tile_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0944").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_im2col_3d");
-        assert_eq!(target.abi_id, "i0944");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0945").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_im2col_4d");
-        assert_eq!(target.abi_id, "i0945");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0946").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_im2col_5d");
-        assert_eq!(target.abi_id, "i0946");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0947").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_tile_1d");
-        assert_eq!(target.abi_id, "i0947");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_inc_tile_1d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0948").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_tile_2d");
-        assert_eq!(target.abi_id, "i0948");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_inc_tile_2d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0949").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_tile_3d");
-        assert_eq!(target.abi_id, "i0949");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_inc_tile_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0950").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_tile_4d");
-        assert_eq!(target.abi_id, "i0950");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_inc_tile_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0951").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_tile_5d");
-        assert_eq!(target.abi_id, "i0951");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_inc_tile_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0952").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_im2col_3d");
-        assert_eq!(target.abi_id, "i0952");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0953").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_im2col_4d");
-        assert_eq!(target.abi_id, "i0953");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0954").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_im2col_5d");
-        assert_eq!(target.abi_id, "i0954");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0955").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_tile_1d");
-        assert_eq!(target.abi_id, "i0955");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_max_tile_1d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0956").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_tile_2d");
-        assert_eq!(target.abi_id, "i0956");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_max_tile_2d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0957").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_tile_3d");
-        assert_eq!(target.abi_id, "i0957");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_max_tile_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0958").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_tile_4d");
-        assert_eq!(target.abi_id, "i0958");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_max_tile_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0959").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_tile_5d");
-        assert_eq!(target.abi_id, "i0959");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_max_tile_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0960").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_im2col_3d");
-        assert_eq!(target.abi_id, "i0960");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_max_im2col_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0961").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_im2col_4d");
-        assert_eq!(target.abi_id, "i0961");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_max_im2col_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0962").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_im2col_5d");
-        assert_eq!(target.abi_id, "i0962");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_max_im2col_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0963").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_tile_1d");
-        assert_eq!(target.abi_id, "i0963");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_min_tile_1d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0964").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_tile_2d");
-        assert_eq!(target.abi_id, "i0964");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_min_tile_2d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0965").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_tile_3d");
-        assert_eq!(target.abi_id, "i0965");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_min_tile_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0966").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_tile_4d");
-        assert_eq!(target.abi_id, "i0966");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_min_tile_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0967").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_tile_5d");
-        assert_eq!(target.abi_id, "i0967");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_min_tile_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0968").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_im2col_3d");
-        assert_eq!(target.abi_id, "i0968");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_min_im2col_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0969").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_im2col_4d");
-        assert_eq!(target.abi_id, "i0969");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_min_im2col_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0970").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_im2col_5d");
-        assert_eq!(target.abi_id, "i0970");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_min_im2col_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0971").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_tile_1d");
-        assert_eq!(target.abi_id, "i0971");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_or_tile_1d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0972").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_tile_2d");
-        assert_eq!(target.abi_id, "i0972");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_or_tile_2d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0973").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_tile_3d");
-        assert_eq!(target.abi_id, "i0973");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_or_tile_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0974").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_tile_4d");
-        assert_eq!(target.abi_id, "i0974");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_or_tile_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0975").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_tile_5d");
-        assert_eq!(target.abi_id, "i0975");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_or_tile_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0976").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_im2col_3d");
-        assert_eq!(target.abi_id, "i0976");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_or_im2col_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0977").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_im2col_4d");
-        assert_eq!(target.abi_id, "i0977");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_or_im2col_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0978").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_im2col_5d");
-        assert_eq!(target.abi_id, "i0978");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_or_im2col_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0979").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_tile_1d");
-        assert_eq!(target.abi_id, "i0979");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_xor_tile_1d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg4>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0980").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_tile_2d");
-        assert_eq!(target.abi_id, "i0980");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_xor_tile_2d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0981").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_tile_3d");
-        assert_eq!(target.abi_id, "i0981");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_xor_tile_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0982").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_tile_4d");
-        assert_eq!(target.abi_id, "i0982");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_xor_tile_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0983").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_tile_5d");
-        assert_eq!(target.abi_id, "i0983");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_xor_tile_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0984").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_im2col_3d");
-        assert_eq!(target.abi_id, "i0984");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_3d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg6>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0985").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_im2col_4d");
-        assert_eq!(target.abi_id, "i0985");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_4d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg7>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0986").unwrap();
-        assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_im2col_5d");
-        assert_eq!(target.abi_id, "i0986");
-        assert_eq!(
-            target.dialect_op,
-            "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_5d"
-        );
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(90),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg8>",
-                "IntrConvergent",
-                "ReadOnly<arg0>",
-                "ReadOnly<arg1>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i0987").unwrap();
-        assert_eq!(target.id, "min_relu_s32");
-        assert_eq!(target.abi_id, "i0987");
-        assert_eq!(target.dialect_op, "nvvm.min_relu_s32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[GeneratedBackendRequirement {
-                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                    requirement: GeneratedTargetRequirement {
-                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                        hardware: GeneratedHardwareTarget::AnyOf(&[
-                            GeneratedHardwareAlternative::MinimumSm(90),
-                        ]),
-                    },
-                }]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0988").unwrap();
-        assert_eq!(target.id, "max_relu_s32");
-        assert_eq!(target.abi_id, "i0988");
-        assert_eq!(target.dialect_op, "nvvm.max_relu_s32");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[GeneratedBackendRequirement {
-                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                    requirement: GeneratedTargetRequirement {
-                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                        hardware: GeneratedHardwareTarget::AnyOf(&[
-                            GeneratedHardwareAlternative::MinimumSm(90),
-                        ]),
-                    },
-                }]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0989").unwrap();
-        assert_eq!(target.id, "min_s16x2");
-        assert_eq!(target.abi_id, "i0989");
-        assert_eq!(target.dialect_op, "nvvm.min_s16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[GeneratedBackendRequirement {
-                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                    requirement: GeneratedTargetRequirement {
-                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                        hardware: GeneratedHardwareTarget::AnyOf(&[
-                            GeneratedHardwareAlternative::MinimumSm(90),
-                        ]),
-                    },
-                }]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0990").unwrap();
-        assert_eq!(target.id, "max_s16x2");
-        assert_eq!(target.abi_id, "i0990");
-        assert_eq!(target.dialect_op, "nvvm.max_s16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[GeneratedBackendRequirement {
-                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                    requirement: GeneratedTargetRequirement {
-                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                        hardware: GeneratedHardwareTarget::AnyOf(&[
-                            GeneratedHardwareAlternative::MinimumSm(90),
-                        ]),
-                    },
-                }]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0991").unwrap();
-        assert_eq!(target.id, "min_u16x2");
-        assert_eq!(target.abi_id, "i0991");
-        assert_eq!(target.dialect_op, "nvvm.min_u16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[GeneratedBackendRequirement {
-                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                    requirement: GeneratedTargetRequirement {
-                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                        hardware: GeneratedHardwareTarget::AnyOf(&[
-                            GeneratedHardwareAlternative::MinimumSm(90),
-                        ]),
-                    },
-                }]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0992").unwrap();
-        assert_eq!(target.id, "max_u16x2");
-        assert_eq!(target.abi_id, "i0992");
-        assert_eq!(target.dialect_op, "nvvm.max_u16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[GeneratedBackendRequirement {
-                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                    requirement: GeneratedTargetRequirement {
-                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                        hardware: GeneratedHardwareTarget::AnyOf(&[
-                            GeneratedHardwareAlternative::MinimumSm(90),
-                        ]),
-                    },
-                }]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0993").unwrap();
-        assert_eq!(target.id, "min_relu_s16x2");
-        assert_eq!(target.abi_id, "i0993");
-        assert_eq!(target.dialect_op, "nvvm.min_relu_s16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[GeneratedBackendRequirement {
-                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                    requirement: GeneratedTargetRequirement {
-                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                        hardware: GeneratedHardwareTarget::AnyOf(&[
-                            GeneratedHardwareAlternative::MinimumSm(90),
-                        ]),
-                    },
-                }]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0994").unwrap();
-        assert_eq!(target.id, "max_relu_s16x2");
-        assert_eq!(target.abi_id, "i0994");
-        assert_eq!(target.dialect_op, "nvvm.max_relu_s16x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[GeneratedBackendRequirement {
-                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                    requirement: GeneratedTargetRequirement {
-                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
-                        hardware: GeneratedHardwareTarget::AnyOf(&[
-                            GeneratedHardwareAlternative::MinimumSm(90),
-                        ]),
-                    },
-                }]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0995").unwrap();
-        assert_eq!(target.id, "add_f32x2");
-        assert_eq!(target.abi_id, "i0995");
-        assert_eq!(target.dialect_op, "nvvm.add_f32x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0996").unwrap();
-        assert_eq!(target.id, "add_ftz_f32x2");
-        assert_eq!(target.abi_id, "i0996");
-        assert_eq!(target.dialect_op, "nvvm.add_ftz_f32x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0997").unwrap();
-        assert_eq!(target.id, "sub_f32x2");
-        assert_eq!(target.abi_id, "i0997");
-        assert_eq!(target.dialect_op, "nvvm.sub_f32x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0998").unwrap();
-        assert_eq!(target.id, "sub_ftz_f32x2");
-        assert_eq!(target.abi_id, "i0998");
-        assert_eq!(target.dialect_op, "nvvm.sub_ftz_f32x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i0999").unwrap();
-        assert_eq!(target.id, "mul_f32x2");
-        assert_eq!(target.abi_id, "i0999");
-        assert_eq!(target.dialect_op, "nvvm.mul_f32x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i1000").unwrap();
-        assert_eq!(target.id, "mul_ftz_f32x2");
-        assert_eq!(target.abi_id, "i1000");
-        assert_eq!(target.dialect_op, "nvvm.mul_ftz_f32x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i1001").unwrap();
-        assert_eq!(target.id, "fma_f32x2");
-        assert_eq!(target.abi_id, "i1001");
-        assert_eq!(target.dialect_op, "nvvm.fma_f32x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i1002").unwrap();
-        assert_eq!(target.id, "fma_ftz_f32x2");
-        assert_eq!(target.abi_id, "i1002");
-        assert_eq!(target.dialect_op, "nvvm.fma_ftz_f32x2");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(100),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert!(target.llvm.is_none());
-        let target = generated_intrinsic_target_by_marker("v1:i1003").unwrap();
-        assert_eq!(target.id, "redux_sync_min_f32");
-        assert_eq!(target.abi_id, "i1003");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_fmin");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                ])
-            }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15035",
-                asm: "redux.sync.min.f32 \t$dst, $src, $mask;",
-                predicates: &["Subtarget->hasReduxSyncF32()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1004").unwrap();
-        assert_eq!(target.id, "redux_sync_min_nan_f32");
-        assert_eq!(target.abi_id, "i1004");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_fmin_nan");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                ])
-            }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15038",
-                asm: "redux.sync.min.NaN.f32 \t$dst, $src, $mask;",
-                predicates: &["Subtarget->hasReduxSyncF32()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1005").unwrap();
-        assert_eq!(target.id, "redux_sync_min_abs_f32");
-        assert_eq!(target.abi_id, "i1005");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_fmin_abs");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                ])
-            }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15037",
-                asm: "redux.sync.min.abs.f32 \t$dst, $src, $mask;",
-                predicates: &["Subtarget->hasReduxSyncF32()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1006").unwrap();
-        assert_eq!(target.id, "redux_sync_min_abs_nan_f32");
-        assert_eq!(target.abi_id, "i1006");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_fmin_abs_nan");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                ])
-            }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15039",
-                asm: "redux.sync.min.abs.NaN.f32 \t$dst, $src, $mask;",
-                predicates: &["Subtarget->hasReduxSyncF32()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1007").unwrap();
-        assert_eq!(target.id, "redux_sync_max_f32");
-        assert_eq!(target.abi_id, "i1007");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_fmax");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                ])
-            }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15040",
-                asm: "redux.sync.max.f32 \t$dst, $src, $mask;",
-                predicates: &["Subtarget->hasReduxSyncF32()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1008").unwrap();
-        assert_eq!(target.id, "redux_sync_max_nan_f32");
-        assert_eq!(target.abi_id, "i1008");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_fmax_nan");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                ])
-            }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15042",
-                asm: "redux.sync.max.NaN.f32 \t$dst, $src, $mask;",
-                predicates: &["Subtarget->hasReduxSyncF32()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1009").unwrap();
-        assert_eq!(target.id, "redux_sync_max_abs_f32");
-        assert_eq!(target.abi_id, "i1009");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_fmax_abs");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                ])
-            }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15041",
-                asm: "redux.sync.max.abs.f32 \t$dst, $src, $mask;",
-                predicates: &["Subtarget->hasReduxSyncF32()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1010").unwrap();
-        assert_eq!(target.id, "redux_sync_max_abs_nan_f32");
-        assert_eq!(target.abi_id, "i1010");
-        assert_eq!(target.dialect_op, "nvvm.redux_sync_fmax_abs_nan");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::AnyOf(&[
-                    GeneratedHardwareAlternative::ExactArchitecture(100),
-                    GeneratedHardwareAlternative::FamilyTarget(100),
-                    GeneratedHardwareAlternative::ExactArchitecture(103),
-                    GeneratedHardwareAlternative::FamilyTarget(103),
-                ])
-            }
-        );
-        assert_eq!(target.backend_requirements, const { &[] });
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_15043",
-                asm: "redux.sync.max.abs.NaN.f32 \t$dst, $src, $mask;",
-                predicates: &["Subtarget->hasReduxSyncF32()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "IntrConvergent",
-                "IntrInaccessibleMemOnly",
-                "IntrNoCallback"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1011").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_e4m3");
-        assert_eq!(target.abi_id, "i1011");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::Shared,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    }],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                101,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_22534",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1012").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_e5m2");
-        assert_eq!(target.abi_id, "i1012");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::Shared,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    }],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                101,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_22534",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1013").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_e2m3");
-        assert_eq!(target.abi_id, "i1013");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::Shared,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    }],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                101,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_22534",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1014").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_e3m2");
-        assert_eq!(target.abi_id, "i1014");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::Shared,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    }],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                101,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_22534",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1015").unwrap();
-        assert_eq!(target.id, "tcgen05_mma_e2m1");
-        assert_eq!(target.abi_id, "i1015");
-        assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
-        assert_eq!(
-            target.variant,
-            GeneratedIntrinsicVariant::Tcgen05Mma {
-                form: GeneratedTcgen05MmaForm::Shared,
-                target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
-                compatibility_alias: true
-            }
-        );
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
-        assert_eq!(
-            target.requirement.hardware,
-            const {
-                GeneratedHardwareTarget::TargetMatrix {
-                    contracts: &[GeneratedTargetContract {
-                        selectors: &[GeneratedTargetSelectorBinding {
-                            name: "kind",
-                            value: "f8f6f4",
-                        }],
-                        alternatives: &[
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-                            },
-                            GeneratedTargetAlternative {
-                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-                            },
-                        ],
-                    }],
-                }
-            }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(101),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                101,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                            hardware: GeneratedHardwareTarget::TargetMatrix {
-                                contracts: &[GeneratedTargetContract {
-                                    selectors: &[GeneratedTargetSelectorBinding {
-                                        name: "kind",
-                                        value: "f8f6f4",
-                                    }],
-                                    alternatives: &[
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(100),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                100,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(103),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                103,
-                                            ),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware:
-                                                GeneratedHardwareAlternative::ExactArchitecture(110),
-                                        },
-                                        GeneratedTargetAlternative {
-                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
-                                                110,
-                                            ),
-                                        },
-                                    ],
-                                }],
-                            },
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(
-            target.selections,
-            &[GeneratedSelectionAlternative {
-                source_record: "anonymous_22534",
-                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
-                predicates: &["Subtarget->hasTcgen05InstSupport()"],
-                constraints: GeneratedSelectionConstraints {
-                    address_space: None,
-                    immediate_bindings: &[]
-                }
-            },]
-        );
-        assert_eq!(
-            target.llvm.unwrap().properties,
-            &[
-                "ImmArg<arg5>",
-                "ImmArg<arg6>",
-                "ImmArg<arg7>",
-                "IntrArgMemOnly",
-                "Range<arg5,0,4>",
-                "Range<arg6,1,3>",
-                "Range<arg7,0,4>",
-                "WriteOnly<arg0>"
-            ] as &[&str]
-        );
-        let target = generated_intrinsic_target_by_marker("v1:i1016").unwrap();
-        assert_eq!(target.id, "ex2_approx_f16");
-        assert_eq!(target.abi_id, "i1016");
-        assert_eq!(target.dialect_op, "nvvm.scalar_math");
-        assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
-        assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
-        assert_eq!(
-            target.requirement.hardware,
-            const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
-        );
-        assert_eq!(
-            target.backend_requirements,
-            const {
-                &[
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LlvmNvptx,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                    GeneratedBackendRequirement {
-                        backend: GeneratedIntrinsicBackend::LibNvvm,
-                        requirement: GeneratedTargetRequirement {
-                            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
-                            hardware: GeneratedHardwareTarget::AnyOf(&[
-                                GeneratedHardwareAlternative::MinimumSm(75),
-                            ]),
-                        },
-                    },
-                ]
-            }
-        );
-        assert_eq!(target.selections, &[]);
-        assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
-        assert!(generated_intrinsic_target_by_marker("v1:i9999").is_none());
-    }
-}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs
new file mode 100644
index 0000000000..6a462e4da7
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs
@@ -0,0 +1,71 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `active_mask` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[GeneratedIntrinsicTarget {
+    marker: "v1:i0044",
+    id: "active_mask",
+    abi_id: "i0044",
+    dialect_op: "nvvm.activemask",
+    variant: GeneratedIntrinsicVariant::Scalar,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(62),
+        hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]),
+    },
+    backend_requirements: &[
+        GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(62),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(30),
+                ]),
+            },
+        },
+        GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LibNvvm,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(62),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(75),
+                ]),
+            },
+        },
+    ],
+    selections: &[GeneratedSelectionAlternative {
+        source_record: "ACTIVEMASK",
+        asm: "activemask.b32 \t$dest;",
+        predicates: &[
+            "Subtarget->getSmVersion() >= 30",
+            "Subtarget->getPTXVersion() >= 62",
+        ],
+        constraints: GeneratedSelectionConstraints {
+            address_space: None,
+            immediate_bindings: &[],
+        },
+    }],
+    llvm: Some(GeneratedLlvmFacts {
+        properties: &[
+            "IntrConvergent",
+            "IntrHasSideEffects",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback",
+        ],
+        result_no_undef: false,
+        result_range: None,
+    }),
+}];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs
new file mode 100644
index 0000000000..43114a153f
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs
@@ -0,0 +1,288 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `clc` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0322",
+        id: "clc_try_cancel",
+        abi_id: "i0322",
+        dialect_op: "nvvm.clc_try_cancel",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CLUSTERLAUNCHCONTRL_TRY_CANCEL",
+            asm: "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 \t[$addr], [$mbar];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 100",
+                "Subtarget->getPTXVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrArgMemOnly", "IntrHasSideEffects"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0323",
+        id: "clc_try_cancel_multicast",
+        abi_id: "i0323",
+        dialect_op: "nvvm.clc_try_cancel_multicast",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CLUSTERLAUNCHCONTRL_TRY_CANCEL_MULTICAST",
+            asm: "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 \t[$addr], [$mbar];",
+            predicates: &["Subtarget->hasClusterLaunchControlTryCancelMulticastSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrArgMemOnly", "IntrHasSideEffects"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0324",
+        id: "clc_query_is_canceled",
+        abi_id: "i0324",
+        dialect_op: "nvvm.clc_query_is_canceled",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0325",
+        id: "clc_query_get_first_ctaid_x",
+        abi_id: "i0325",
+        dialect_op: "nvvm.clc_query_get_first_ctaid_x",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0326",
+        id: "clc_query_get_first_ctaid_y",
+        abi_id: "i0326",
+        dialect_op: "nvvm.clc_query_get_first_ctaid_y",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0327",
+        id: "clc_query_get_first_ctaid_z",
+        abi_id: "i0327",
+        dialect_op: "nvvm.clc_query_get_first_ctaid_z",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs
new file mode 100644
index 0000000000..4e054c70b4
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs
@@ -0,0 +1,332 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `cluster_barrier` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedClusterBarrierMode, GeneratedHardwareAlternative,
+    GeneratedHardwareTarget, GeneratedIntrinsicBackend, GeneratedIntrinsicTarget,
+    GeneratedIntrinsicVariant, GeneratedLlvmFacts, GeneratedPtxVersion,
+    GeneratedSelectionAlternative, GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0277",
+        id: "barrier_cluster_arrive",
+        abi_id: "i0277",
+        dialect_op: "nvvm.cluster_barrier",
+        variant: GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::Arrive,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_arrive",
+            asm: "barrier.cluster.arrive;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0278",
+        id: "barrier_cluster_arrive_aligned",
+        abi_id: "i0278",
+        dialect_op: "nvvm.cluster_barrier",
+        variant: GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::ArriveAligned,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_arrive_aligned",
+            asm: "barrier.cluster.arrive.aligned;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0279",
+        id: "barrier_cluster_arrive_relaxed",
+        abi_id: "i0279",
+        dialect_op: "nvvm.cluster_barrier",
+        variant: GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::ArriveRelaxed,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_arrive_relaxed",
+            asm: "barrier.cluster.arrive.relaxed;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0280",
+        id: "barrier_cluster_arrive_relaxed_aligned",
+        abi_id: "i0280",
+        dialect_op: "nvvm.cluster_barrier",
+        variant: GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::ArriveRelaxedAligned,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_arrive_relaxed_aligned",
+            asm: "barrier.cluster.arrive.relaxed.aligned;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0281",
+        id: "barrier_cluster_wait",
+        abi_id: "i0281",
+        dialect_op: "nvvm.cluster_barrier",
+        variant: GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::Wait,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_wait",
+            asm: "barrier.cluster.wait;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0282",
+        id: "barrier_cluster_wait_aligned",
+        abi_id: "i0282",
+        dialect_op: "nvvm.cluster_barrier",
+        variant: GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::WaitAligned,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_wait_aligned",
+            asm: "barrier.cluster.wait.aligned;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs
new file mode 100644
index 0000000000..1eac7d4ca5
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs
@@ -0,0 +1,119 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `cluster_memory` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0320",
+        id: "map_shared_rank",
+        abi_id: "i0320",
+        dialect_op: "nvvm.mapa_shared_cluster",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "mapa_shared_cluster_64",
+                asm: "mapa.shared::cluster.u64 \t$d, $a, $b;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 90",
+                    "Subtarget->getPTXVersion() >= 78",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "mapa_shared_cluster_64i",
+                asm: "mapa.shared::cluster.u64 \t$d, $a, $b;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 90",
+                    "Subtarget->getPTXVersion() >= 78",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoCapture<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0321",
+        id: "dsmem_read_u32",
+        abi_id: "i0321",
+        dialect_op: "nvvm.dsmem_read_u32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs
new file mode 100644
index 0000000000..297b52d270
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs
@@ -0,0 +1,882 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `cp_async` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0086",
+        id: "cp_async_ca_4",
+        abi_id: "i0086",
+        dialect_op: "nvvm.cp_async_ca_4",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4",
+            asm: "cp.async.ca.shared.global [$dst], [$src], 4;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "NoAlias<arg0>",
+                "NoAlias<arg1>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0087",
+        id: "cp_async_ca_zfill_4",
+        abi_id: "i0087",
+        dialect_op: "nvvm.cp_async_ca_zfill_4",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4_s",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 4, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4_si",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 4, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "NoAlias<arg0>",
+                "NoAlias<arg1>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0088",
+        id: "cp_async_ca_8",
+        abi_id: "i0088",
+        dialect_op: "nvvm.cp_async_ca_8",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8",
+            asm: "cp.async.ca.shared.global [$dst], [$src], 8;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "NoAlias<arg0>",
+                "NoAlias<arg1>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0089",
+        id: "cp_async_ca_zfill_8",
+        abi_id: "i0089",
+        dialect_op: "nvvm.cp_async_ca_zfill_8",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8_s",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 8, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8_si",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 8, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "NoAlias<arg0>",
+                "NoAlias<arg1>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0090",
+        id: "cp_async_ca_16",
+        abi_id: "i0090",
+        dialect_op: "nvvm.cp_async_ca_16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16",
+            asm: "cp.async.ca.shared.global [$dst], [$src], 16;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "NoAlias<arg0>",
+                "NoAlias<arg1>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0091",
+        id: "cp_async_ca_zfill_16",
+        abi_id: "i0091",
+        dialect_op: "nvvm.cp_async_ca_zfill_16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16_s",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 16, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16_si",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 16, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "NoAlias<arg0>",
+                "NoAlias<arg1>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0092",
+        id: "cp_async_cg_16",
+        abi_id: "i0092",
+        dialect_op: "nvvm.cp_async_cg_16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16",
+            asm: "cp.async.cg.shared.global [$dst], [$src], 16;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "NoAlias<arg0>",
+                "NoAlias<arg1>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0093",
+        id: "cp_async_cg_zfill_16",
+        abi_id: "i0093",
+        dialect_op: "nvvm.cp_async_cg_zfill_16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16_s",
+                asm: "cp.async.cg.shared.global [$dst], [$src], 16, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16_si",
+                asm: "cp.async.cg.shared.global [$dst], [$src], 16, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "NoAlias<arg0>",
+                "NoAlias<arg1>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0094",
+        id: "cp_async_commit_group",
+        abi_id: "i0094",
+        dialect_op: "nvvm.cp_async_commit_group",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_COMMIT_GROUP",
+            asm: "cp.async.commit_group;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0095",
+        id: "cp_async_wait_all",
+        abi_id: "i0095",
+        dialect_op: "nvvm.cp_async_wait_all",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_WAIT_ALL",
+            asm: "cp.async.wait_all;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0096",
+        id: "cp_async_wait_group",
+        abi_id: "i0096",
+        dialect_op: "nvvm.cp_async_wait_group",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_WAIT_GROUP",
+            asm: "cp.async.wait_group \t$n;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0101",
+        id: "cp_async_mbarrier_arrive",
+        abi_id: "i0101",
+        dialect_op: "nvvm.cp_async_mbarrier_arrive",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_MBARRIER_ARRIVE",
+            asm: "cp.async.mbarrier.arrive.b64 \t[$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0102",
+        id: "cp_async_mbarrier_arrive_shared",
+        abi_id: "i0102",
+        dialect_op: "nvvm.cp_async_mbarrier_arrive_shared",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_MBARRIER_ARRIVE_SHARED",
+            asm: "cp.async.mbarrier.arrive.shared.b64 \t[$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0103",
+        id: "cp_async_mbarrier_arrive_noinc",
+        abi_id: "i0103",
+        dialect_op: "nvvm.cp_async_mbarrier_arrive_noinc",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_MBARRIER_ARRIVE_NOINC",
+            asm: "cp.async.mbarrier.arrive.noinc.b64 \t[$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0104",
+        id: "cp_async_mbarrier_arrive_noinc_shared",
+        abi_id: "i0104",
+        dialect_op: "nvvm.cp_async_mbarrier_arrive_noinc_shared",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_MBARRIER_ARRIVE_NOINC_SHARED",
+            asm: "cp.async.mbarrier.arrive.noinc.shared.b64 \t[$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs
new file mode 100644
index 0000000000..ac8d3af258
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs
@@ -0,0 +1,120 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `debug_control` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedPtxVersion, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0295",
+        id: "trap",
+        abi_id: "i0295",
+        dialect_op: "nvvm.trap",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0296",
+        id: "breakpoint",
+        abi_id: "i0296",
+        dialect_op: "nvvm.brkpt",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                11,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0297",
+        id: "pmevent",
+        abi_id: "i0297",
+        dialect_op: "nvvm.pmevent",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(14),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs
new file mode 100644
index 0000000000..b0d1ffe2f9
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs
@@ -0,0 +1,214 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `dotprod` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedImmediateBinding, GeneratedIntrinsicBackend, GeneratedIntrinsicTarget,
+    GeneratedIntrinsicVariant, GeneratedLlvmFacts, GeneratedPtxVersion,
+    GeneratedSelectionAlternative, GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0030",
+        id: "dp4a_s32",
+        abi_id: "i0030",
+        dialect_op: "nvvm.dp4a_s32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                61,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(61),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "DOT4_ss",
+            asm: "dp4a.s32.s32 \t$dst, $a, $b, $c;",
+            predicates: &["hasDotInstructions"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0031",
+        id: "dp4a_u32",
+        abi_id: "i0031",
+        dialect_op: "nvvm.dp4a_u32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                61,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(61),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "DOT4_uu",
+            asm: "dp4a.u32.u32 \t$dst, $a, $b, $c;",
+            predicates: &["hasDotInstructions"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0032",
+        id: "dp2a_s32",
+        abi_id: "i0032",
+        dialect_op: "nvvm.dp2a_s32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                61,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(61),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "DOT2_lo_ss",
+            asm: "dp2a.lo.s32.s32 \t$dst, $a, $b, $c;",
+            predicates: &["hasDotInstructions"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 2,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0033",
+        id: "dp2a_u32",
+        abi_id: "i0033",
+        dialect_op: "nvvm.dp2a_u32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                61,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(61),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "DOT2_lo_uu",
+            asm: "dp2a.lo.u32.u32 \t$dst, $a, $b, $c;",
+            predicates: &["hasDotInstructions"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 2,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs
new file mode 100644
index 0000000000..f908a24fb0
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs
@@ -0,0 +1,80 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `elect` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[GeneratedIntrinsicTarget {
+    marker: "v1:i0367",
+    id: "elect_sync",
+    abi_id: "i0367",
+    dialect_op: "nvvm.elect_sync",
+    variant: GeneratedIntrinsicVariant::Scalar,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+        hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]),
+    },
+    backend_requirements: &[
+        GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(90),
+                ]),
+            },
+        },
+        GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LibNvvm,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(90),
+                ]),
+            },
+        },
+    ],
+    selections: &[
+        GeneratedSelectionAlternative {
+            source_record: "INT_ELECT_SYNC_I",
+            asm: "elect.sync \t$dest|$pred, $mask;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        },
+        GeneratedSelectionAlternative {
+            source_record: "INT_ELECT_SYNC_R",
+            asm: "elect.sync \t$dest|$pred, $mask;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        },
+    ],
+    llvm: Some(GeneratedLlvmFacts {
+        properties: &["IntrConvergent", "IntrInaccessibleMemOnly"],
+        result_no_undef: false,
+        result_range: None,
+    }),
+}];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs
new file mode 100644
index 0000000000..c226548d9f
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs
@@ -0,0 +1,586 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `execution_control` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0883",
+        id: "barrier_cta_sync",
+        abi_id: "i0883",
+        dialect_op: "nvvm.barrier_cta_sync_count",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ii",
+                asm: "barrier.sync \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ir",
+                asm: "barrier.sync \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ri",
+                asm: "barrier.sync \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_rr",
+                asm: "barrier.sync \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0884",
+        id: "barrier_cta_sync_aligned",
+        abi_id: "i0884",
+        dialect_op: "nvvm.barrier_cta_sync_aligned_count",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ALIGNED_ii",
+                asm: "bar.sync \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ALIGNED_ir",
+                asm: "bar.sync \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ALIGNED_ri",
+                asm: "bar.sync \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ALIGNED_rr",
+                asm: "bar.sync \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0885",
+        id: "barrier_cta_arrive",
+        abi_id: "i0885",
+        dialect_op: "nvvm.barrier_cta_arrive_count",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ii",
+                asm: "barrier.arrive \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ir",
+                asm: "barrier.arrive \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ri",
+                asm: "barrier.arrive \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_rr",
+                asm: "barrier.arrive \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0886",
+        id: "barrier_cta_arrive_aligned",
+        abi_id: "i0886",
+        dialect_op: "nvvm.barrier_cta_arrive_aligned_count",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ii",
+                asm: "bar.arrive \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ir",
+                asm: "bar.arrive \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ri",
+                asm: "bar.arrive \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_rr",
+                asm: "bar.arrive \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0913",
+        id: "grid_dependency_launch_dependents",
+        abi_id: "i0913",
+        dialect_op: "nvvm.grid_dependency_launch_dependents",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "GRIDDEPCONTROL_LAUNCH_DEPENDENTS",
+            asm: "griddepcontrol.launch_dependents;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrHasSideEffects", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0914",
+        id: "grid_dependency_wait",
+        abi_id: "i0914",
+        dialect_op: "nvvm.grid_dependency_wait",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "GRIDDEPCONTROL_WAIT",
+            asm: "griddepcontrol.wait;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrHasSideEffects", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0915",
+        id: "setmaxnreg_inc",
+        abi_id: "i0915",
+        dialect_op: "nvvm.setmaxnreg_inc",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22212",
+            asm: "setmaxnreg.inc.sync.aligned.u32 \t$reg_count;",
+            predicates: &["Subtarget->hasSetMaxNRegSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg0>",
+                "IntrConvergent",
+                "IntrHasSideEffects",
+                "IntrNoMem",
+                "Range<arg0,24,257>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0916",
+        id: "setmaxnreg_dec",
+        abi_id: "i0916",
+        dialect_op: "nvvm.setmaxnreg_dec",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22214",
+            asm: "setmaxnreg.dec.sync.aligned.u32 \t$reg_count;",
+            predicates: &["Subtarget->hasSetMaxNRegSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg0>",
+                "IntrConvergent",
+                "IntrHasSideEffects",
+                "IntrNoMem",
+                "Range<arg0,24,257>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs
new file mode 100644
index 0000000000..0c45fe264c
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs
@@ -0,0 +1,2933 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `extended_minmax` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedExtendedMinMaxFormat, GeneratedExtendedMinMaxNan,
+    GeneratedExtendedMinMaxOperation, GeneratedExtendedMinMaxSubnormal,
+    GeneratedHardwareAlternative, GeneratedHardwareTarget, GeneratedIntrinsicBackend,
+    GeneratedIntrinsicTarget, GeneratedIntrinsicVariant, GeneratedLlvmFacts, GeneratedPtxVersion,
+    GeneratedSelectionAlternative, GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0550",
+        id: "min_ftz_f16x2",
+        abi_id: "i0550",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_f16x2",
+            asm: "min.ftz.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0551",
+        id: "min_ftz_nan_f16x2",
+        abi_id: "i0551",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_NaN_f16x2",
+            asm: "min.ftz.NaN.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0552",
+        id: "min_ftz_nan_xorsign_abs_f32",
+        abi_id: "i0552",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_FTZ_NAN_XORSIGN_ABS_F",
+            asm: "min.ftz.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0553",
+        id: "min_ftz_nan_xorsign_abs_f16x2",
+        abi_id: "i0553",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_NaN_xorsign_abs_f16x2",
+            asm: "min.ftz.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0554",
+        id: "min_ftz_xorsign_abs_f32",
+        abi_id: "i0554",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_FTZ_XORSIGN_ABS_F",
+            asm: "min.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0555",
+        id: "min_ftz_xorsign_abs_f16x2",
+        abi_id: "i0555",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_xorsign_abs_f16x2",
+            asm: "min.ftz.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0556",
+        id: "min_nan_bf16x2",
+        abi_id: "i0556",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_bf16x2",
+            asm: "min.NaN.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0557",
+        id: "min_nan_f16x2",
+        abi_id: "i0557",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_f16x2",
+            asm: "min.NaN.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0558",
+        id: "min_nan_xorsign_abs_bf16x2",
+        abi_id: "i0558",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_bf16x2",
+            asm: "min.NaN.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0559",
+        id: "min_nan_xorsign_abs_f32",
+        abi_id: "i0559",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NAN_XORSIGN_ABS_F",
+            asm: "min.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0560",
+        id: "min_nan_xorsign_abs_f16x2",
+        abi_id: "i0560",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_f16x2",
+            asm: "min.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0561",
+        id: "min_xorsign_abs_bf16x2",
+        abi_id: "i0561",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_xorsign_abs_bf16x2",
+            asm: "min.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0562",
+        id: "min_xorsign_abs_f32",
+        abi_id: "i0562",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_XORSIGN_ABS_F",
+            asm: "min.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0563",
+        id: "min_xorsign_abs_f16x2",
+        abi_id: "i0563",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_xorsign_abs_f16x2",
+            asm: "min.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0564",
+        id: "max_ftz_f16x2",
+        abi_id: "i0564",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_f16x2",
+            asm: "max.ftz.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0565",
+        id: "max_ftz_nan_f16x2",
+        abi_id: "i0565",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_NaN_f16x2",
+            asm: "max.ftz.NaN.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0566",
+        id: "max_ftz_nan_xorsign_abs_f32",
+        abi_id: "i0566",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAX_FTZ_NAN_XORSIGN_ABS_F",
+            asm: "max.ftz.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0567",
+        id: "max_ftz_nan_xorsign_abs_f16x2",
+        abi_id: "i0567",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_NaN_xorsign_abs_f16x2",
+            asm: "max.ftz.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0568",
+        id: "max_ftz_xorsign_abs_f32",
+        abi_id: "i0568",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAX_FTZ_XORSIGN_ABS_F",
+            asm: "max.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0569",
+        id: "max_ftz_xorsign_abs_f16x2",
+        abi_id: "i0569",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_xorsign_abs_f16x2",
+            asm: "max.ftz.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0570",
+        id: "max_nan_bf16x2",
+        abi_id: "i0570",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_bf16x2",
+            asm: "max.NaN.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0571",
+        id: "max_nan_f16x2",
+        abi_id: "i0571",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_f16x2",
+            asm: "max.NaN.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0572",
+        id: "max_nan_xorsign_abs_bf16x2",
+        abi_id: "i0572",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_bf16x2",
+            asm: "max.NaN.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0573",
+        id: "max_nan_xorsign_abs_f32",
+        abi_id: "i0573",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAX_NAN_XORSIGN_ABS_F",
+            asm: "max.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0574",
+        id: "max_nan_xorsign_abs_f16x2",
+        abi_id: "i0574",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_f16x2",
+            asm: "max.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0575",
+        id: "max_xorsign_abs_bf16x2",
+        abi_id: "i0575",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_xorsign_abs_bf16x2",
+            asm: "max.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0576",
+        id: "max_xorsign_abs_f32",
+        abi_id: "i0576",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAX_XORSIGN_ABS_F",
+            asm: "max.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0577",
+        id: "max_xorsign_abs_f16x2",
+        abi_id: "i0577",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_xorsign_abs_f16x2",
+            asm: "max.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0830",
+        id: "min_f16",
+        abi_id: "i0830",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_f16",
+            asm: "min.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0831",
+        id: "min_ftz_f16",
+        abi_id: "i0831",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_f16",
+            asm: "min.ftz.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0832",
+        id: "min_nan_f16",
+        abi_id: "i0832",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_f16",
+            asm: "min.NaN.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0833",
+        id: "min_ftz_nan_f16",
+        abi_id: "i0833",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_NaN_f16",
+            asm: "min.ftz.NaN.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0834",
+        id: "min_xorsign_abs_f16",
+        abi_id: "i0834",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_xorsign_abs_f16",
+            asm: "min.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0835",
+        id: "min_ftz_xorsign_abs_f16",
+        abi_id: "i0835",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_xorsign_abs_f16",
+            asm: "min.ftz.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0836",
+        id: "min_nan_xorsign_abs_f16",
+        abi_id: "i0836",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_f16",
+            asm: "min.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0837",
+        id: "min_ftz_nan_xorsign_abs_f16",
+        abi_id: "i0837",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_NaN_xorsign_abs_f16",
+            asm: "min.ftz.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0838",
+        id: "min_bf16",
+        abi_id: "i0838",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_bf16",
+            asm: "min.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0839",
+        id: "min_nan_bf16",
+        abi_id: "i0839",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_bf16",
+            asm: "min.NaN.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0840",
+        id: "min_xorsign_abs_bf16",
+        abi_id: "i0840",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_xorsign_abs_bf16",
+            asm: "min.xorsign.abs.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0841",
+        id: "min_nan_xorsign_abs_bf16",
+        abi_id: "i0841",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_bf16",
+            asm: "min.NaN.xorsign.abs.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0842",
+        id: "max_f16",
+        abi_id: "i0842",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_f16",
+            asm: "max.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0843",
+        id: "max_ftz_f16",
+        abi_id: "i0843",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_f16",
+            asm: "max.ftz.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0844",
+        id: "max_nan_f16",
+        abi_id: "i0844",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_f16",
+            asm: "max.NaN.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0845",
+        id: "max_ftz_nan_f16",
+        abi_id: "i0845",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_NaN_f16",
+            asm: "max.ftz.NaN.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0846",
+        id: "max_xorsign_abs_f16",
+        abi_id: "i0846",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_xorsign_abs_f16",
+            asm: "max.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0847",
+        id: "max_ftz_xorsign_abs_f16",
+        abi_id: "i0847",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_xorsign_abs_f16",
+            asm: "max.ftz.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0848",
+        id: "max_nan_xorsign_abs_f16",
+        abi_id: "i0848",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_f16",
+            asm: "max.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0849",
+        id: "max_ftz_nan_xorsign_abs_f16",
+        abi_id: "i0849",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_NaN_xorsign_abs_f16",
+            asm: "max.ftz.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0850",
+        id: "max_bf16",
+        abi_id: "i0850",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_bf16",
+            asm: "max.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0851",
+        id: "max_nan_bf16",
+        abi_id: "i0851",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_bf16",
+            asm: "max.NaN.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0852",
+        id: "max_xorsign_abs_bf16",
+        abi_id: "i0852",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_xorsign_abs_bf16",
+            asm: "max.xorsign.abs.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0853",
+        id: "max_nan_xorsign_abs_bf16",
+        abi_id: "i0853",
+        dialect_op: "nvvm.extended_minmax",
+        variant: GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                86,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(86),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_bf16",
+            asm: "max.NaN.xorsign.abs.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs
new file mode 100644
index 0000000000..d2245265b1
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs
@@ -0,0 +1,211 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `integer_minmax` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedPtxVersion, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0987",
+        id: "min_relu_s32",
+        abi_id: "i0987",
+        dialect_op: "nvvm.min_relu_s32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(90),
+                ]),
+            },
+        }],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0988",
+        id: "max_relu_s32",
+        abi_id: "i0988",
+        dialect_op: "nvvm.max_relu_s32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(90),
+                ]),
+            },
+        }],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0989",
+        id: "min_s16x2",
+        abi_id: "i0989",
+        dialect_op: "nvvm.min_s16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(90),
+                ]),
+            },
+        }],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0990",
+        id: "max_s16x2",
+        abi_id: "i0990",
+        dialect_op: "nvvm.max_s16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(90),
+                ]),
+            },
+        }],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0991",
+        id: "min_u16x2",
+        abi_id: "i0991",
+        dialect_op: "nvvm.min_u16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(90),
+                ]),
+            },
+        }],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0992",
+        id: "max_u16x2",
+        abi_id: "i0992",
+        dialect_op: "nvvm.max_u16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(90),
+                ]),
+            },
+        }],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0993",
+        id: "min_relu_s16x2",
+        abi_id: "i0993",
+        dialect_op: "nvvm.min_relu_s16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(90),
+                ]),
+            },
+        }],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0994",
+        id: "max_relu_s16x2",
+        abi_id: "i0994",
+        dialect_op: "nvvm.max_relu_s16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(90),
+                ]),
+            },
+        }],
+        selections: &[],
+        llvm: None,
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs
new file mode 100644
index 0000000000..84a0791b03
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs
@@ -0,0 +1,1426 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `ldmatrix` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLdmatrixElement, GeneratedLdmatrixLayout, GeneratedLdmatrixMultiplicity,
+    GeneratedLdmatrixShape, GeneratedLlvmFacts, GeneratedPtxVersion,
+    GeneratedSelectionAddressSpace, GeneratedSelectionAlternative, GeneratedSelectionConstraints,
+    GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0013",
+        id: "ldmatrix_m8n8_x4_b16",
+        abi_id: "i0013",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X4,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B16,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20697",
+            asm: "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0025",
+        id: "ldmatrix_m8n8_x1_b16",
+        abi_id: "i0025",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B16,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20675",
+            asm: "ldmatrix.sync.aligned.m8n8.x1.shared.b16 {{$rx10}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0026",
+        id: "ldmatrix_m8n8_x1_trans_b16",
+        abi_id: "i0026",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B16,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20758",
+            asm: "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16 {{$rx10}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0027",
+        id: "ldmatrix_m8n8_x2_b16",
+        abi_id: "i0027",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B16,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20687",
+            asm: "ldmatrix.sync.aligned.m8n8.x2.shared.b16 {{$rx20, $rx21}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0028",
+        id: "ldmatrix_m8n8_x2_trans_b16",
+        abi_id: "i0028",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B16,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20762",
+            asm: "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16 {{$rx20, $rx21}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0029",
+        id: "ldmatrix_m8n8_x4_trans_b16",
+        abi_id: "i0029",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X4,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B16,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20766",
+            asm: "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0378",
+        id: "ldmatrix_m16n16_x1_trans_b8",
+        abi_id: "i0378",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20772",
+            asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {{$rx10, $rx11}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0379",
+        id: "ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64",
+        abi_id: "i0379",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8x16B4x16P64,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20782",
+            asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b4x16_p64 {{$rx10, $rx11}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0380",
+        id: "ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32",
+        abi_id: "i0380",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8x16B6x16P32,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20777",
+            asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b6x16_p32 {{$rx10, $rx11}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0381",
+        id: "ldmatrix_m16n16_x2_trans_b8",
+        abi_id: "i0381",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20789",
+            asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0382",
+        id: "ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64",
+        abi_id: "i0382",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8x16B4x16P64,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20799",
+            asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b4x16_p64 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0383",
+        id: "ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32",
+        abi_id: "i0383",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8x16B6x16P32,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20794",
+            asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b6x16_p32 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0384",
+        id: "ldmatrix_m8n16_x1_b8x16_b4x16_p64",
+        abi_id: "i0384",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B4x16P64,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20707",
+            asm: "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b4x16_p64 {{$rx10}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0385",
+        id: "ldmatrix_m8n16_x1_b8x16_b6x16_p32",
+        abi_id: "i0385",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B6x16P32,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20702",
+            asm: "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b6x16_p32 {{$rx10}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0386",
+        id: "ldmatrix_m8n16_x2_b8x16_b4x16_p64",
+        abi_id: "i0386",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B4x16P64,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20717",
+            asm: "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b4x16_p64 {{$rx20, $rx21}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0387",
+        id: "ldmatrix_m8n16_x2_b8x16_b6x16_p32",
+        abi_id: "i0387",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B6x16P32,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20712",
+            asm: "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b6x16_p32 {{$rx20, $rx21}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0388",
+        id: "ldmatrix_m8n16_x4_b8x16_b4x16_p64",
+        abi_id: "i0388",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X4,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B4x16P64,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20727",
+            asm: "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b4x16_p64 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0389",
+        id: "ldmatrix_m8n16_x4_b8x16_b6x16_p32",
+        abi_id: "i0389",
+        dialect_op: "nvvm.ldmatrix",
+        variant: GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X4,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B6x16P32,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20722",
+            asm: "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b6x16_p32 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrReadMem",
+                "NoCapture<arg0>",
+                "ReadOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs
new file mode 100644
index 0000000000..756eaa45a2
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs
@@ -0,0 +1,227 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `mbarrier_basic` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0097",
+        id: "mbarrier_init",
+        abi_id: "i0097",
+        dialect_op: "nvvm.mbarrier_init_shared",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "MBARRIER_INIT_SHARED",
+            asm: "mbarrier.init.shared.b64 \t[$addr], $count;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0098",
+        id: "mbarrier_arrive",
+        abi_id: "i0098",
+        dialect_op: "nvvm.mbarrier_arrive_shared",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "MBARRIER_ARRIVE_SHARED",
+            asm: "mbarrier.arrive.shared.b64 \t$state, [$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0099",
+        id: "mbarrier_test_wait",
+        abi_id: "i0099",
+        dialect_op: "nvvm.mbarrier_test_wait_shared",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "MBARRIER_TEST_WAIT_SHARED",
+            asm: "mbarrier.test_wait.shared.b64 \t$res, [$addr], $state;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0100",
+        id: "mbarrier_inval",
+        abi_id: "i0100",
+        dialect_op: "nvvm.mbarrier_inval_shared",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "MBARRIER_INVAL_SHARED",
+            asm: "mbarrier.inval.shared.b64 \t[$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs
new file mode 100644
index 0000000000..85e99673fe
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs
@@ -0,0 +1,525 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `mbarrier_extended` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0306",
+        id: "mbarrier_arrive_expect_tx",
+        abi_id: "i0306",
+        dialect_op: "nvvm.mbarrier_arrive_expect_tx_shared",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0307",
+        id: "mbarrier_arrive_expect_tx_cluster",
+        abi_id: "i0307",
+        dialect_op: "nvvm.mbarrier_arrive_expect_tx_cluster",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrArgMemOnly", "IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0308",
+        id: "mbarrier_arrive_cluster",
+        abi_id: "i0308",
+        dialect_op: "nvvm.mbarrier_arrive_cluster",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0309",
+        id: "mbarrier_try_wait",
+        abi_id: "i0309",
+        dialect_op: "nvvm.mbarrier_try_wait_shared",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "mbar_try_wait_scope_cta_acquire_STATE",
+            asm: "mbarrier.try_wait.shared.b64 $res, [$addr], $state;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0310",
+        id: "mbarrier_try_wait_parity",
+        abi_id: "i0310",
+        dialect_op: "nvvm.mbarrier_try_wait_parity_shared",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0311",
+        id: "mbarrier_try_wait_parity_cluster",
+        abi_id: "i0311",
+        dialect_op: "nvvm.mbarrier_try_wait_parity_cluster",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0312",
+        id: "fence_proxy_async_shared_cta",
+        abi_id: "i0312",
+        dialect_op: "nvvm.fence_proxy_async_shared_cta",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15048",
+            asm: "fence.proxy.async.shared::cta;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0313",
+        id: "fence_mbarrier_init_release_cluster",
+        abi_id: "i0313",
+        dialect_op: "nvvm.fence_mbarrier_init_release_cluster",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_MBARRIER_INIT_RELEASE_CLUSTER",
+            asm: "fence.mbarrier_init.release.cluster;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0314",
+        id: "fence_proxy_async_generic_release_shared_cta_cluster",
+        abi_id: "i0314",
+        dialect_op: "nvvm.fence_proxy_async_generic_release_shared_cta_cluster",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FENCE_PROXY_ASYNC_GENERIC_RELEASE_SYNC_RESTRICT_SPACE_CTA_SCOPE_CLUSTER",
+            asm: "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0315",
+        id: "fence_proxy_async_generic_acquire_shared_cluster_cluster",
+        abi_id: "i0315",
+        dialect_op: "nvvm.fence_proxy_async_generic_acquire_shared_cluster_cluster",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FENCE_PROXY_ASYNC_GENERIC_ACQUIRE_SYNC_RESTRICT_SPACE_CLUSTER_SCOPE_CLUSTER",
+            asm: "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0316",
+        id: "nanosleep",
+        abi_id: "i0316",
+        dialect_op: "nvvm.nanosleep",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(63),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(63),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(63),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "INT_NVVM_NANOSLEEP_I",
+                asm: "nanosleep.u32 \t$i;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 70",
+                    "Subtarget->getPTXVersion() >= 63",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "INT_NVVM_NANOSLEEP_R",
+                asm: "nanosleep.u32 \t$i;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 70",
+                    "Subtarget->getPTXVersion() >= 63",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrHasSideEffects", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs
new file mode 100644
index 0000000000..e629cc76b0
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs
@@ -0,0 +1,1398 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated target requirements and separately imported LLVM/selection facts.
+
+pub const GENERATED_INTRINSIC_MARKER_ATTR: &str = "cuda_oxide_intrinsic_marker";
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+pub struct GeneratedPtxVersion(u16);
+impl GeneratedPtxVersion {
+    pub const fn from_encoded(encoded: u16) -> Self {
+        Self(encoded)
+    }
+    pub const fn encoded(self) -> u16 {
+        self.0
+    }
+    pub const fn major(self) -> u16 {
+        self.0 / 10
+    }
+    pub const fn minor(self) -> u16 {
+        self.0 % 10
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedHardwareAlternative {
+    MinimumSm(u16),
+    ExactArchitecture(u16),
+    FamilyTarget(u16),
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedTargetSelectorBinding {
+    pub name: &'static str,
+    pub value: &'static str,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedTargetAlternative {
+    pub minimum_ptx: GeneratedPtxVersion,
+    pub hardware: GeneratedHardwareAlternative,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedTargetContract {
+    pub selectors: &'static [GeneratedTargetSelectorBinding],
+    pub alternatives: &'static [GeneratedTargetAlternative],
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedHardwareTarget {
+    All,
+    AnyOf(&'static [GeneratedHardwareAlternative]),
+    TargetMatrix {
+        contracts: &'static [GeneratedTargetContract],
+    },
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedTargetRequirement {
+    pub minimum_ptx: GeneratedPtxVersion,
+    pub hardware: GeneratedHardwareTarget,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedIntrinsicBackend {
+    LlvmNvptx,
+    LibNvvm,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedBackendRequirement {
+    pub backend: GeneratedIntrinsicBackend,
+    pub requirement: GeneratedTargetRequirement,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedSelectionAddressSpace {
+    Generic,
+    Shared,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedImmediateBinding {
+    pub argument_index: usize,
+    pub value: i64,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedSelectionConstraints {
+    pub address_space: Option<GeneratedSelectionAddressSpace>,
+    pub immediate_bindings: &'static [GeneratedImmediateBinding],
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedSelectionAlternative {
+    pub source_record: &'static str,
+    pub asm: &'static str,
+    pub predicates: &'static [&'static str],
+    pub constraints: GeneratedSelectionConstraints,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedIntrinsicRange {
+    pub lower: &'static str,
+    pub upper_exclusive: &'static str,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedLlvmFacts {
+    pub properties: &'static [&'static str],
+    pub result_no_undef: bool,
+    pub result_range: Option<GeneratedIntrinsicRange>,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedLdmatrixShape {
+    M8n8,
+    M8n16,
+    M16n16,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedLdmatrixMultiplicity {
+    X1,
+    X2,
+    X4,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedLdmatrixLayout {
+    Normal,
+    Transposed,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedLdmatrixElement {
+    B16,
+    B8,
+    B8x16B4x16P64,
+    B8x16B6x16P32,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedPackedAtomicFormat {
+    F16x2,
+    Bf16x2,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedRegisterMmaShape {
+    M8n8k4,
+    M8n8k16,
+    M8n8k32,
+    M8n8k128,
+    M16n8k4,
+    M16n8k8,
+    M16n8k16,
+    M16n8k32,
+    M16n8k64,
+    M16n8k128,
+    M16n8k256,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedRegisterMmaOperation {
+    Multiply,
+    AndPopc,
+    XorPopc,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedRegisterMmaKind {
+    Standard,
+    F8f6f4,
+    Mxf8f6f4,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedRegisterMmaAccumulator {
+    F16,
+    F32,
+    F64,
+    S32,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedRegisterMmaElement {
+    Bf16,
+    E2m1,
+    E2m3,
+    E3m2,
+    E4m3,
+    E5m2,
+    F16,
+    Tf32,
+    F64,
+    B1,
+    S4,
+    U4,
+    S8,
+    U8,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedRegisterMmaLayout {
+    Row,
+    Col,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedRegisterMmaOverflow {
+    NotApplicable,
+    Wrapping,
+    Satfinite,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedSparseMmaShape {
+    M16n8k32,
+    M16n8k64,
+    M16n8k128,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedSparseMmaAccumulator {
+    F16,
+    F32,
+    S32,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedSparseMmaElement {
+    E2m1,
+    E2m3,
+    E3m2,
+    E4m3,
+    E5m2,
+    S4,
+    U4,
+    S8,
+    U8,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedSparseMmaLayout {
+    Row,
+    Col,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedSparseMmaOverflow {
+    NotApplicable,
+    Wrapping,
+    Satfinite,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedSparseMmaMetadata {
+    Standard,
+    Ordered,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedSparseMmaSelector {
+    ImmediateZeroOrOne,
+    ImmediateZero,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedPrmtMode {
+    Generic,
+    F4e,
+    B4e,
+    Rc8,
+    Ecl,
+    Ecr,
+    Rc16,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedClusterBarrierMode {
+    Arrive,
+    ArriveAligned,
+    ArriveRelaxed,
+    ArriveRelaxedAligned,
+    Wait,
+    WaitAligned,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedScalarConversionRounding {
+    NearestAway,
+    NearestEven,
+    TowardZero,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedScalarConversionSaturation {
+    None,
+    Relu,
+    Satfinite,
+    ReluSatfinite,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedWgmmaControlMode {
+    Fence,
+    CommitGroup,
+    WaitGroup,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedScalarArithmeticFormat {
+    F32,
+    F64,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedScalarArithmeticOperation {
+    Mul,
+    Div,
+    Fma,
+    Add,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedScalarArithmeticRounding {
+    Rn,
+    Rz,
+    Rm,
+    Rp,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedScalarArithmeticSubnormal {
+    Preserve,
+    Ftz,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedScalarArithmeticSaturation {
+    None,
+    Sat,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedExtendedMinMaxFormat {
+    F32,
+    F16,
+    Bf16,
+    F16x2,
+    Bf16x2,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedExtendedMinMaxOperation {
+    Min,
+    Max,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedExtendedMinMaxSubnormal {
+    Preserve,
+    Ftz,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedExtendedMinMaxNan {
+    Number,
+    Nan,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedTcgen05MmaForm {
+    Shared,
+    Tensor,
+    TensorAshift,
+    SpShared,
+    SpTensor,
+    SpTensorAshift,
+    WsShared,
+    WsSharedZeroColMask,
+    WsSpShared,
+    WsSpSharedZeroColMask,
+    WsSpTensor,
+    WsSpTensorZeroColMask,
+    WsTensor,
+    WsTensorZeroColMask,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedTcgen05MmaTargetSelector {
+    Kind,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum GeneratedIntrinsicVariant {
+    Scalar,
+    Ldmatrix {
+        shape: GeneratedLdmatrixShape,
+        multiplicity: GeneratedLdmatrixMultiplicity,
+        layout: GeneratedLdmatrixLayout,
+        element: GeneratedLdmatrixElement,
+    },
+    PackedAtomic {
+        format: GeneratedPackedAtomicFormat,
+    },
+    RegisterMma {
+        shape: GeneratedRegisterMmaShape,
+        operation: GeneratedRegisterMmaOperation,
+        kind: GeneratedRegisterMmaKind,
+        accumulator: GeneratedRegisterMmaAccumulator,
+        a_element: GeneratedRegisterMmaElement,
+        b_element: GeneratedRegisterMmaElement,
+        a_layout: GeneratedRegisterMmaLayout,
+        b_layout: GeneratedRegisterMmaLayout,
+        overflow: GeneratedRegisterMmaOverflow,
+    },
+    SparseMma {
+        shape: GeneratedSparseMmaShape,
+        accumulator: GeneratedSparseMmaAccumulator,
+        a_element: GeneratedSparseMmaElement,
+        b_element: GeneratedSparseMmaElement,
+        a_layout: GeneratedSparseMmaLayout,
+        b_layout: GeneratedSparseMmaLayout,
+        overflow: GeneratedSparseMmaOverflow,
+        metadata: GeneratedSparseMmaMetadata,
+        selector: GeneratedSparseMmaSelector,
+    },
+    Prmt {
+        mode: GeneratedPrmtMode,
+    },
+    ClusterBarrier {
+        mode: GeneratedClusterBarrierMode,
+    },
+    ScalarConversion {
+        rounding: GeneratedScalarConversionRounding,
+        saturation: GeneratedScalarConversionSaturation,
+    },
+    WgmmaControl {
+        mode: GeneratedWgmmaControlMode,
+    },
+    ScalarArithmetic {
+        format: GeneratedScalarArithmeticFormat,
+        operation: GeneratedScalarArithmeticOperation,
+        rounding: GeneratedScalarArithmeticRounding,
+        subnormal: GeneratedScalarArithmeticSubnormal,
+        saturation: GeneratedScalarArithmeticSaturation,
+    },
+    ExtendedMinMax {
+        format: GeneratedExtendedMinMaxFormat,
+        operation: GeneratedExtendedMinMaxOperation,
+        subnormal: GeneratedExtendedMinMaxSubnormal,
+        nan: GeneratedExtendedMinMaxNan,
+        xorsign_abs: bool,
+    },
+    Tcgen05Mma {
+        form: GeneratedTcgen05MmaForm,
+        target_selector: GeneratedTcgen05MmaTargetSelector,
+        compatibility_alias: bool,
+    },
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct GeneratedIntrinsicTarget {
+    pub marker: &'static str,
+    pub id: &'static str,
+    pub abi_id: &'static str,
+    pub dialect_op: &'static str,
+    pub variant: GeneratedIntrinsicVariant,
+    pub requirement: GeneratedTargetRequirement,
+    pub backend_requirements: &'static [GeneratedBackendRequirement],
+    pub selections: &'static [GeneratedSelectionAlternative],
+    pub llvm: Option<GeneratedLlvmFacts>,
+}
+
+impl GeneratedHardwareTarget {
+    pub fn contract_for_selector(
+        self,
+        name: &str,
+        value: &str,
+    ) -> Option<&'static GeneratedTargetContract> {
+        let Self::TargetMatrix { contracts } = self else {
+            return None;
+        };
+        let mut matching = contracts.iter().filter(|contract| {
+            matches!(contract.selectors, [binding] if binding.name == name && binding.value == value)
+        });
+        let contract = matching.next()?;
+        if matching.next().is_some() {
+            None
+        } else {
+            Some(contract)
+        }
+    }
+}
+
+impl GeneratedIntrinsicTarget {
+    pub fn requirement_for_backend(
+        &self,
+        backend: GeneratedIntrinsicBackend,
+    ) -> GeneratedTargetRequirement {
+        self.backend_requirements
+            .iter()
+            .find(|entry| entry.backend == backend)
+            .map(|entry| entry.requirement)
+            .unwrap_or(self.requirement)
+    }
+
+    pub fn target_contract_for_backend_selector(
+        &self,
+        backend: GeneratedIntrinsicBackend,
+        name: &str,
+        value: &str,
+    ) -> Option<&'static GeneratedTargetContract> {
+        self.requirement_for_backend(backend)
+            .hardware
+            .contract_for_selector(name, value)
+    }
+}
+pub const GENERATED_INTRINSIC_TARGET_GROUPS: &[&[GeneratedIntrinsicTarget]] = &[
+    sreg::TARGETS,
+    ldmatrix::TARGETS,
+    packed_atomic::TARGETS,
+    redux::TARGETS,
+    dotprod::TARGETS,
+    sync::TARGETS,
+    vote::TARGETS,
+    active_mask::TARGETS,
+    warp_match::TARGETS,
+    warp_barrier::TARGETS,
+    warp_shuffle::TARGETS,
+    packed_alu::TARGETS,
+    packed_conversion::TARGETS,
+    cp_async::TARGETS,
+    mbarrier_basic::TARGETS,
+    register_mma::TARGETS,
+    sparse_mma::TARGETS,
+    prmt::TARGETS,
+    cluster_barrier::TARGETS,
+    debug_control::TARGETS,
+    stmatrix::TARGETS,
+    movmatrix::TARGETS,
+    mbarrier_extended::TARGETS,
+    wgmma_control::TARGETS,
+    cluster_memory::TARGETS,
+    clc::TARGETS,
+    tma::TARGETS,
+    tcgen05_other::TARGETS,
+    elect::TARGETS,
+    scalar_conversion::TARGETS,
+    scalar_arithmetic::TARGETS,
+    extended_minmax::TARGETS,
+    tcgen05_cp::TARGETS,
+    tcgen05_ld::TARGETS,
+    tcgen05_st::TARGETS,
+    tcgen05_mma::TARGETS,
+    tcgen05_mma_ws::TARGETS,
+    scalar_math::TARGETS,
+    execution_control::TARGETS,
+    integer_minmax::TARGETS,
+];
+
+pub fn generated_intrinsic_targets() -> impl Iterator<Item = &'static GeneratedIntrinsicTarget> {
+    GENERATED_INTRINSIC_TARGET_GROUPS
+        .iter()
+        .flat_map(|group| group.iter())
+}
+
+fn generated_intrinsic_compatibility_marker_by_op_name(op_name: &str) -> Option<&'static str> {
+    match op_name {
+        "nvvm.ldmatrix_x1" => Some("v1:i0025"),
+        "nvvm.ldmatrix_x1_trans" => Some("v1:i0026"),
+        "nvvm.ldmatrix_x2" => Some("v1:i0027"),
+        "nvvm.ldmatrix_x2_trans" => Some("v1:i0028"),
+        "nvvm.ldmatrix_x4" => Some("v1:i0013"),
+        "nvvm.ldmatrix_x4_trans" => Some("v1:i0029"),
+        _ => None,
+    }
+}
+
+pub fn generated_intrinsic_target_by_marker(
+    marker: &str,
+) -> Option<&'static GeneratedIntrinsicTarget> {
+    generated_intrinsic_targets().find(|target| target.marker == marker)
+}
+
+pub fn generated_intrinsic_targets_by_op_name(
+    op_name: &str,
+) -> impl Iterator<Item = &'static GeneratedIntrinsicTarget> + '_ {
+    let compatibility_marker = generated_intrinsic_compatibility_marker_by_op_name(op_name);
+    generated_intrinsic_targets().filter(move |target| {
+        target.dialect_op == op_name || compatibility_marker == Some(target.marker)
+    })
+}
+
+pub fn generated_intrinsic_target_by_op_name(
+    op_name: &str,
+) -> Option<&'static GeneratedIntrinsicTarget> {
+    generated_intrinsic_targets_by_op_name(op_name).next()
+}
+
+pub fn generated_intrinsic_target(op_name: &str) -> Option<&'static GeneratedIntrinsicTarget> {
+    generated_intrinsic_target_by_op_name(op_name)
+}
+
+pub fn generated_intrinsic_target_is_direct_dialect_candidate(
+    target: &GeneratedIntrinsicTarget,
+) -> bool {
+    !matches!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            compatibility_alias: true,
+            ..
+        }
+    )
+}
+
+pub fn generated_intrinsic_operation_matches(
+    ctx: &Context,
+    target: &GeneratedIntrinsicTarget,
+    operation: Ptr<Operation>,
+) -> bool {
+    match target.variant {
+        GeneratedIntrinsicVariant::Scalar => true,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form,
+            target_selector,
+            compatibility_alias,
+        } => {
+            let Some(op) = Operation::get_op::<Tcgen05MmaOp>(operation, ctx) else {
+                return false;
+            };
+            let form_matches = match form {
+                GeneratedTcgen05MmaForm::Shared => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::Shared)
+                }
+                GeneratedTcgen05MmaForm::Tensor => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::Tensor)
+                }
+                GeneratedTcgen05MmaForm::TensorAshift => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::TensorAshift)
+                }
+                GeneratedTcgen05MmaForm::SpShared => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::SpShared)
+                }
+                GeneratedTcgen05MmaForm::SpTensor => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::SpTensor)
+                }
+                GeneratedTcgen05MmaForm::SpTensorAshift => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::SpTensorAshift)
+                }
+                GeneratedTcgen05MmaForm::WsShared => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::WsShared)
+                }
+                GeneratedTcgen05MmaForm::WsSharedZeroColMask => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::WsSharedZeroColMask)
+                }
+                GeneratedTcgen05MmaForm::WsSpShared => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::WsSpShared)
+                }
+                GeneratedTcgen05MmaForm::WsSpSharedZeroColMask => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::WsSpSharedZeroColMask)
+                }
+                GeneratedTcgen05MmaForm::WsSpTensor => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::WsSpTensor)
+                }
+                GeneratedTcgen05MmaForm::WsSpTensorZeroColMask => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::WsSpTensorZeroColMask)
+                }
+                GeneratedTcgen05MmaForm::WsTensor => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::WsTensor)
+                }
+                GeneratedTcgen05MmaForm::WsTensorZeroColMask => {
+                    op.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref()
+                        == Some(&Tcgen05MmaFormAttr::WsTensorZeroColMask)
+                }
+            };
+            let selector_matches =
+                matches!(target_selector, GeneratedTcgen05MmaTargetSelector::Kind)
+                    && op.get_attr_nvvm_tcgen05_mma_kind(ctx).is_some();
+            let alias_matches = !compatibility_alias
+                || (op.get_attr_nvvm_tcgen05_mma_kind(ctx).as_deref()
+                    == Some(&Tcgen05MmaKindAttr::F8f6f4)
+                    && match form {
+                        GeneratedTcgen05MmaForm::Shared => {
+                            op.get_attr_nvvm_tcgen05_mma_cta_group(ctx).as_deref()
+                                == Some(&Tcgen05MmaCtaGroupAttr::Cg1)
+                                && op.get_attr_nvvm_tcgen05_mma_collector_a(ctx).as_deref()
+                                    == Some(&Tcgen05MmaCollectorAAttr::Discard)
+                        }
+                        GeneratedTcgen05MmaForm::WsTensor => {
+                            op.get_attr_nvvm_tcgen05_mma_b_buffer(ctx).as_deref()
+                                == Some(&Tcgen05MmaBBufferAttr::B0)
+                                && op.get_attr_nvvm_tcgen05_mma_b_usage(ctx).as_deref()
+                                    == Some(&Tcgen05MmaBUsageAttr::Discard)
+                        }
+                        _ => false,
+                    });
+            form_matches && selector_matches && alias_matches
+        }
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape,
+            multiplicity,
+            layout,
+            element,
+        } => {
+            let operation_name = Operation::get_opid(operation, ctx).to_string();
+            if let Some(marker) =
+                generated_intrinsic_compatibility_marker_by_op_name(&operation_name)
+            {
+                return marker == target.marker;
+            }
+            let Some(op) = Operation::get_op::<LdmatrixOp>(operation, ctx) else {
+                return false;
+            };
+            let shape_matches = match shape {
+                GeneratedLdmatrixShape::M8n8 => {
+                    op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref()
+                        == Some(&LdmatrixShapeAttr::M8n8)
+                }
+                GeneratedLdmatrixShape::M8n16 => {
+                    op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref()
+                        == Some(&LdmatrixShapeAttr::M8n16)
+                }
+                GeneratedLdmatrixShape::M16n16 => {
+                    op.get_attr_nvvm_ldmatrix_shape(ctx).as_deref()
+                        == Some(&LdmatrixShapeAttr::M16n16)
+                }
+            };
+            let multiplicity_matches = match multiplicity {
+                GeneratedLdmatrixMultiplicity::X1 => {
+                    op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref()
+                        == Some(&LdmatrixMultiplicityAttr::X1)
+                }
+                GeneratedLdmatrixMultiplicity::X2 => {
+                    op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref()
+                        == Some(&LdmatrixMultiplicityAttr::X2)
+                }
+                GeneratedLdmatrixMultiplicity::X4 => {
+                    op.get_attr_nvvm_ldmatrix_multiplicity(ctx).as_deref()
+                        == Some(&LdmatrixMultiplicityAttr::X4)
+                }
+            };
+            let layout_matches = match layout {
+                GeneratedLdmatrixLayout::Normal => {
+                    op.get_attr_nvvm_ldmatrix_layout(ctx).as_deref()
+                        == Some(&LdmatrixLayoutAttr::Normal)
+                }
+                GeneratedLdmatrixLayout::Transposed => {
+                    op.get_attr_nvvm_ldmatrix_layout(ctx).as_deref()
+                        == Some(&LdmatrixLayoutAttr::Transposed)
+                }
+            };
+            let element_matches = match element {
+                GeneratedLdmatrixElement::B16 => {
+                    op.get_attr_nvvm_ldmatrix_element(ctx).as_deref()
+                        == Some(&LdmatrixElementAttr::B16)
+                }
+                GeneratedLdmatrixElement::B8 => {
+                    op.get_attr_nvvm_ldmatrix_element(ctx).as_deref()
+                        == Some(&LdmatrixElementAttr::B8)
+                }
+                GeneratedLdmatrixElement::B8x16B4x16P64 => {
+                    op.get_attr_nvvm_ldmatrix_element(ctx).as_deref()
+                        == Some(&LdmatrixElementAttr::B8x16B4x16P64)
+                }
+                GeneratedLdmatrixElement::B8x16B6x16P32 => {
+                    op.get_attr_nvvm_ldmatrix_element(ctx).as_deref()
+                        == Some(&LdmatrixElementAttr::B8x16B6x16P32)
+                }
+            };
+            shape_matches
+                && multiplicity_matches
+                && layout_matches
+                && element_matches
+                && op.get_attr_nvvm_ldmatrix_state_space(ctx).as_deref()
+                    == Some(&LdmatrixStateSpaceAttr::Shared)
+        }
+        GeneratedIntrinsicVariant::PackedAtomic { format } => {
+            let Some(op) = Operation::get_op::<PackedAtomicAddOp>(operation, ctx) else {
+                return false;
+            };
+            let format_matches = match format {
+                GeneratedPackedAtomicFormat::F16x2 => {
+                    op.get_attr_nvvm_packed_atomic_format(ctx).as_deref()
+                        == Some(&PackedAtomicFormatAttr::F16x2)
+                }
+                GeneratedPackedAtomicFormat::Bf16x2 => {
+                    op.get_attr_nvvm_packed_atomic_format(ctx).as_deref()
+                        == Some(&PackedAtomicFormatAttr::Bf16x2)
+                }
+            };
+            format_matches
+                && op.get_attr_nvvm_packed_atomic_state_space(ctx).as_deref()
+                    == Some(&PackedAtomicStateSpaceAttr::Global)
+                && op.get_attr_nvvm_packed_atomic_ordering(ctx).as_deref()
+                    == Some(&PackedAtomicOrderingAttr::Relaxed)
+                && op.get_attr_nvvm_packed_atomic_scope(ctx).as_deref()
+                    == Some(&PackedAtomicScopeAttr::Gpu)
+                && op.get_attr_nvvm_packed_atomic_rounding(ctx).as_deref()
+                    == Some(&PackedAtomicRoundingAttr::Rn)
+                && op.get_attr_nvvm_packed_atomic_subnormal(ctx).as_deref()
+                    == Some(&PackedAtomicSubnormalAttr::NoFtz)
+                && op.get_attr_nvvm_packed_atomic_atomicity(ctx).as_deref()
+                    == Some(&PackedAtomicAtomicityAttr::PerElement)
+        }
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape,
+            operation: mma_operation,
+            kind,
+            accumulator,
+            a_element,
+            b_element,
+            a_layout,
+            b_layout,
+            overflow,
+        } => {
+            let Some(op) = Operation::get_op::<RegisterMmaOp>(operation, ctx) else {
+                return false;
+            };
+            let shape_matches = match shape {
+                GeneratedRegisterMmaShape::M8n8k4 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M8n8k4)
+                }
+                GeneratedRegisterMmaShape::M8n8k16 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M8n8k16)
+                }
+                GeneratedRegisterMmaShape::M8n8k32 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M8n8k32)
+                }
+                GeneratedRegisterMmaShape::M8n8k128 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M8n8k128)
+                }
+                GeneratedRegisterMmaShape::M16n8k4 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M16n8k4)
+                }
+                GeneratedRegisterMmaShape::M16n8k8 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M16n8k8)
+                }
+                GeneratedRegisterMmaShape::M16n8k16 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M16n8k16)
+                }
+                GeneratedRegisterMmaShape::M16n8k32 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M16n8k32)
+                }
+                GeneratedRegisterMmaShape::M16n8k64 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M16n8k64)
+                }
+                GeneratedRegisterMmaShape::M16n8k128 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M16n8k128)
+                }
+                GeneratedRegisterMmaShape::M16n8k256 => {
+                    op.get_attr_nvvm_register_mma_shape(ctx).as_deref()
+                        == Some(&RegisterMmaShapeAttr::M16n8k256)
+                }
+            };
+            let operation_matches = match mma_operation {
+                GeneratedRegisterMmaOperation::Multiply => {
+                    op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::Multiply
+                }
+                GeneratedRegisterMmaOperation::AndPopc => {
+                    op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::AndPopc
+                }
+                GeneratedRegisterMmaOperation::XorPopc => {
+                    op.operation_or_multiply(ctx) == RegisterMmaOperationAttr::XorPopc
+                }
+            };
+            let kind_matches = match kind {
+                GeneratedRegisterMmaKind::Standard => {
+                    op.kind_or_inferred(ctx) == RegisterMmaKindAttr::Standard
+                }
+                GeneratedRegisterMmaKind::F8f6f4 => {
+                    op.kind_or_inferred(ctx) == RegisterMmaKindAttr::F8f6f4
+                }
+                GeneratedRegisterMmaKind::Mxf8f6f4 => {
+                    op.kind_or_inferred(ctx) == RegisterMmaKindAttr::Mxf8f6f4
+                }
+            };
+            let accumulator_matches = match accumulator {
+                GeneratedRegisterMmaAccumulator::F16 => {
+                    op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref()
+                        == Some(&RegisterMmaAccumulatorAttr::F16)
+                }
+                GeneratedRegisterMmaAccumulator::F32 => {
+                    op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref()
+                        == Some(&RegisterMmaAccumulatorAttr::F32)
+                }
+                GeneratedRegisterMmaAccumulator::F64 => {
+                    op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref()
+                        == Some(&RegisterMmaAccumulatorAttr::F64)
+                }
+                GeneratedRegisterMmaAccumulator::S32 => {
+                    op.get_attr_nvvm_register_mma_accumulator(ctx).as_deref()
+                        == Some(&RegisterMmaAccumulatorAttr::S32)
+                }
+            };
+            let element_matches = |expected, actual: Option<&RegisterMmaElementAttr>| match expected
+            {
+                GeneratedRegisterMmaElement::Bf16 => actual == Some(&RegisterMmaElementAttr::Bf16),
+                GeneratedRegisterMmaElement::F16 => actual == Some(&RegisterMmaElementAttr::F16),
+                GeneratedRegisterMmaElement::Tf32 => actual == Some(&RegisterMmaElementAttr::Tf32),
+                GeneratedRegisterMmaElement::F64 => actual == Some(&RegisterMmaElementAttr::F64),
+                GeneratedRegisterMmaElement::E2m1 => actual == Some(&RegisterMmaElementAttr::E2m1),
+                GeneratedRegisterMmaElement::E2m3 => actual == Some(&RegisterMmaElementAttr::E2m3),
+                GeneratedRegisterMmaElement::E3m2 => actual == Some(&RegisterMmaElementAttr::E3m2),
+                GeneratedRegisterMmaElement::E4m3 => actual == Some(&RegisterMmaElementAttr::E4m3),
+                GeneratedRegisterMmaElement::E5m2 => actual == Some(&RegisterMmaElementAttr::E5m2),
+                GeneratedRegisterMmaElement::B1 => actual == Some(&RegisterMmaElementAttr::B1),
+                GeneratedRegisterMmaElement::S4 => actual == Some(&RegisterMmaElementAttr::S4),
+                GeneratedRegisterMmaElement::U4 => actual == Some(&RegisterMmaElementAttr::U4),
+                GeneratedRegisterMmaElement::S8 => actual == Some(&RegisterMmaElementAttr::S8),
+                GeneratedRegisterMmaElement::U8 => actual == Some(&RegisterMmaElementAttr::U8),
+            };
+            let layout_matches = |expected, actual: Option<&RegisterMmaLayoutAttr>| match expected {
+                GeneratedRegisterMmaLayout::Row => actual == Some(&RegisterMmaLayoutAttr::Row),
+                GeneratedRegisterMmaLayout::Col => actual == Some(&RegisterMmaLayoutAttr::Col),
+            };
+            let overflow_matches = match overflow {
+                GeneratedRegisterMmaOverflow::NotApplicable => {
+                    op.get_attr_nvvm_register_mma_overflow(ctx).as_deref()
+                        == Some(&RegisterMmaOverflowAttr::NotApplicable)
+                }
+                GeneratedRegisterMmaOverflow::Wrapping => {
+                    op.get_attr_nvvm_register_mma_overflow(ctx).as_deref()
+                        == Some(&RegisterMmaOverflowAttr::Wrapping)
+                }
+                GeneratedRegisterMmaOverflow::Satfinite => {
+                    op.get_attr_nvvm_register_mma_overflow(ctx).as_deref()
+                        == Some(&RegisterMmaOverflowAttr::Satfinite)
+                }
+            };
+            shape_matches
+                && operation_matches
+                && kind_matches
+                && accumulator_matches
+                && element_matches(
+                    a_element,
+                    op.get_attr_nvvm_register_mma_a_element(ctx).as_deref(),
+                )
+                && element_matches(
+                    b_element,
+                    op.get_attr_nvvm_register_mma_b_element(ctx).as_deref(),
+                )
+                && layout_matches(
+                    a_layout,
+                    op.get_attr_nvvm_register_mma_a_layout(ctx).as_deref(),
+                )
+                && layout_matches(
+                    b_layout,
+                    op.get_attr_nvvm_register_mma_b_layout(ctx).as_deref(),
+                )
+                && overflow_matches
+        }
+        GeneratedIntrinsicVariant::SparseMma {
+            shape,
+            accumulator,
+            a_element,
+            b_element,
+            a_layout,
+            b_layout,
+            overflow,
+            metadata,
+            selector,
+        } => {
+            let Some(op) = Operation::get_op::<SparseMmaOp>(operation, ctx) else {
+                return false;
+            };
+            let element_matches = |expected, actual: Option<&SparseMmaElementAttr>| match expected {
+                GeneratedSparseMmaElement::E2m1 => actual == Some(&SparseMmaElementAttr::E2m1),
+                GeneratedSparseMmaElement::E2m3 => actual == Some(&SparseMmaElementAttr::E2m3),
+                GeneratedSparseMmaElement::E3m2 => actual == Some(&SparseMmaElementAttr::E3m2),
+                GeneratedSparseMmaElement::E4m3 => actual == Some(&SparseMmaElementAttr::E4m3),
+                GeneratedSparseMmaElement::E5m2 => actual == Some(&SparseMmaElementAttr::E5m2),
+                GeneratedSparseMmaElement::S4 => actual == Some(&SparseMmaElementAttr::S4),
+                GeneratedSparseMmaElement::U4 => actual == Some(&SparseMmaElementAttr::U4),
+                GeneratedSparseMmaElement::S8 => actual == Some(&SparseMmaElementAttr::S8),
+                GeneratedSparseMmaElement::U8 => actual == Some(&SparseMmaElementAttr::U8),
+            };
+            let layout_matches = |expected, actual: Option<&SparseMmaLayoutAttr>| match expected {
+                GeneratedSparseMmaLayout::Row => actual == Some(&SparseMmaLayoutAttr::Row),
+                GeneratedSparseMmaLayout::Col => actual == Some(&SparseMmaLayoutAttr::Col),
+            };
+            let overflow_matches = match overflow {
+                GeneratedSparseMmaOverflow::NotApplicable => {
+                    op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref()
+                        == Some(&SparseMmaOverflowAttr::NotApplicable)
+                }
+                GeneratedSparseMmaOverflow::Wrapping => {
+                    op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref()
+                        == Some(&SparseMmaOverflowAttr::Wrapping)
+                }
+                GeneratedSparseMmaOverflow::Satfinite => {
+                    op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref()
+                        == Some(&SparseMmaOverflowAttr::Satfinite)
+                }
+            };
+            let metadata_matches = match metadata {
+                GeneratedSparseMmaMetadata::Standard => {
+                    op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref()
+                        == Some(&SparseMmaMetadataAttr::Standard)
+                }
+                GeneratedSparseMmaMetadata::Ordered => {
+                    op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref()
+                        == Some(&SparseMmaMetadataAttr::Ordered)
+                }
+            };
+            let shape_matches = match shape {
+                GeneratedSparseMmaShape::M16n8k32 => {
+                    op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref()
+                        == Some(&SparseMmaShapeAttr::M16n8k32)
+                }
+                GeneratedSparseMmaShape::M16n8k64 => {
+                    op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref()
+                        == Some(&SparseMmaShapeAttr::M16n8k64)
+                }
+                GeneratedSparseMmaShape::M16n8k128 => {
+                    op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref()
+                        == Some(&SparseMmaShapeAttr::M16n8k128)
+                }
+            };
+            let accumulator_matches = match accumulator {
+                GeneratedSparseMmaAccumulator::F16 => {
+                    op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref()
+                        == Some(&SparseMmaAccumulatorAttr::F16)
+                }
+                GeneratedSparseMmaAccumulator::F32 => {
+                    op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref()
+                        == Some(&SparseMmaAccumulatorAttr::F32)
+                }
+                GeneratedSparseMmaAccumulator::S32 => {
+                    op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref()
+                        == Some(&SparseMmaAccumulatorAttr::S32)
+                }
+            };
+            let selector_matches = match selector {
+                GeneratedSparseMmaSelector::ImmediateZeroOrOne => {
+                    op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref()
+                        == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne)
+                }
+                GeneratedSparseMmaSelector::ImmediateZero => {
+                    op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref()
+                        == Some(&SparseMmaSelectorAttr::ImmediateZero)
+                }
+            };
+            shape_matches
+                && accumulator_matches
+                && element_matches(
+                    a_element,
+                    op.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref(),
+                )
+                && element_matches(
+                    b_element,
+                    op.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref(),
+                )
+                && layout_matches(
+                    a_layout,
+                    op.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref(),
+                )
+                && layout_matches(
+                    b_layout,
+                    op.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref(),
+                )
+                && overflow_matches
+                && metadata_matches
+                && selector_matches
+        }
+        GeneratedIntrinsicVariant::Prmt { mode } => {
+            let Some(op) = Operation::get_op::<PrmtOp>(operation, ctx) else {
+                return false;
+            };
+            match mode {
+                GeneratedPrmtMode::Generic => {
+                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Generic)
+                }
+                GeneratedPrmtMode::F4e => {
+                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::F4e)
+                }
+                GeneratedPrmtMode::B4e => {
+                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::B4e)
+                }
+                GeneratedPrmtMode::Rc8 => {
+                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Rc8)
+                }
+                GeneratedPrmtMode::Ecl => {
+                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Ecl)
+                }
+                GeneratedPrmtMode::Ecr => {
+                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Ecr)
+                }
+                GeneratedPrmtMode::Rc16 => {
+                    op.get_attr_nvvm_prmt_mode(ctx).as_deref() == Some(&PrmtModeAttr::Rc16)
+                }
+            }
+        }
+        GeneratedIntrinsicVariant::ClusterBarrier { mode } => {
+            let Some(op) = Operation::get_op::<ClusterBarrierOp>(operation, ctx) else {
+                return false;
+            };
+            match mode {
+                GeneratedClusterBarrierMode::Arrive => {
+                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
+                        == Some(&ClusterBarrierModeAttr::Arrive)
+                }
+                GeneratedClusterBarrierMode::ArriveAligned => {
+                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
+                        == Some(&ClusterBarrierModeAttr::ArriveAligned)
+                }
+                GeneratedClusterBarrierMode::ArriveRelaxed => {
+                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
+                        == Some(&ClusterBarrierModeAttr::ArriveRelaxed)
+                }
+                GeneratedClusterBarrierMode::ArriveRelaxedAligned => {
+                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
+                        == Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned)
+                }
+                GeneratedClusterBarrierMode::Wait => {
+                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
+                        == Some(&ClusterBarrierModeAttr::Wait)
+                }
+                GeneratedClusterBarrierMode::WaitAligned => {
+                    op.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref()
+                        == Some(&ClusterBarrierModeAttr::WaitAligned)
+                }
+            }
+        }
+        GeneratedIntrinsicVariant::WgmmaControl { mode } => match mode {
+            GeneratedWgmmaControlMode::Fence => {
+                Operation::get_op::<WgmmaFenceSyncAlignedOp>(operation, ctx).is_some()
+            }
+            GeneratedWgmmaControlMode::CommitGroup => {
+                Operation::get_op::<WgmmaCommitGroupSyncAlignedOp>(operation, ctx).is_some()
+            }
+            GeneratedWgmmaControlMode::WaitGroup => {
+                Operation::get_op::<WgmmaWaitGroupSyncAlignedOp>(operation, ctx).is_some()
+            }
+        },
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding,
+            saturation,
+        } => {
+            let Some(op) = Operation::get_op::<ScalarConversionOp>(operation, ctx) else {
+                return false;
+            };
+            let rounding_matches = match rounding {
+                GeneratedScalarConversionRounding::NearestAway => {
+                    op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref()
+                        == Some(&ScalarConversionRoundingAttr::NearestAway)
+                }
+                GeneratedScalarConversionRounding::NearestEven => {
+                    op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref()
+                        == Some(&ScalarConversionRoundingAttr::NearestEven)
+                }
+                GeneratedScalarConversionRounding::TowardZero => {
+                    op.get_attr_nvvm_scalar_conversion_rounding(ctx).as_deref()
+                        == Some(&ScalarConversionRoundingAttr::TowardZero)
+                }
+            };
+            let saturation_matches = match saturation {
+                GeneratedScalarConversionSaturation::None => {
+                    op.get_attr_nvvm_scalar_conversion_saturation(ctx)
+                        .as_deref()
+                        == Some(&ScalarConversionSaturationAttr::None)
+                }
+                GeneratedScalarConversionSaturation::Relu => {
+                    op.get_attr_nvvm_scalar_conversion_saturation(ctx)
+                        .as_deref()
+                        == Some(&ScalarConversionSaturationAttr::Relu)
+                }
+                GeneratedScalarConversionSaturation::Satfinite => {
+                    op.get_attr_nvvm_scalar_conversion_saturation(ctx)
+                        .as_deref()
+                        == Some(&ScalarConversionSaturationAttr::Satfinite)
+                }
+                GeneratedScalarConversionSaturation::ReluSatfinite => {
+                    op.get_attr_nvvm_scalar_conversion_saturation(ctx)
+                        .as_deref()
+                        == Some(&ScalarConversionSaturationAttr::ReluSatfinite)
+                }
+            };
+            rounding_matches && saturation_matches
+        }
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format,
+            operation: arithmetic_operation,
+            rounding,
+            subnormal,
+            saturation,
+        } => {
+            let Some(op) = Operation::get_op::<ScalarArithmeticOp>(operation, ctx) else {
+                return false;
+            };
+            let format_matches = match format {
+                GeneratedScalarArithmeticFormat::F32 => {
+                    op.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref()
+                        == Some(&ScalarArithmeticFormatAttr::F32)
+                }
+                GeneratedScalarArithmeticFormat::F64 => {
+                    op.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref()
+                        == Some(&ScalarArithmeticFormatAttr::F64)
+                }
+            };
+            let operation_matches = match arithmetic_operation {
+                GeneratedScalarArithmeticOperation::Mul => {
+                    op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref()
+                        == Some(&ScalarArithmeticOperationAttr::Mul)
+                }
+                GeneratedScalarArithmeticOperation::Div => {
+                    op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref()
+                        == Some(&ScalarArithmeticOperationAttr::Div)
+                }
+                GeneratedScalarArithmeticOperation::Fma => {
+                    op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref()
+                        == Some(&ScalarArithmeticOperationAttr::Fma)
+                }
+                GeneratedScalarArithmeticOperation::Add => {
+                    op.get_attr_nvvm_scalar_arithmetic_operation(ctx).as_deref()
+                        == Some(&ScalarArithmeticOperationAttr::Add)
+                }
+            };
+            let rounding_matches = match rounding {
+                GeneratedScalarArithmeticRounding::Rn => {
+                    op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref()
+                        == Some(&ScalarArithmeticRoundingAttr::Rn)
+                }
+                GeneratedScalarArithmeticRounding::Rz => {
+                    op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref()
+                        == Some(&ScalarArithmeticRoundingAttr::Rz)
+                }
+                GeneratedScalarArithmeticRounding::Rm => {
+                    op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref()
+                        == Some(&ScalarArithmeticRoundingAttr::Rm)
+                }
+                GeneratedScalarArithmeticRounding::Rp => {
+                    op.get_attr_nvvm_scalar_arithmetic_rounding(ctx).as_deref()
+                        == Some(&ScalarArithmeticRoundingAttr::Rp)
+                }
+            };
+            let subnormal_matches = match subnormal {
+                GeneratedScalarArithmeticSubnormal::Preserve => {
+                    op.get_attr_nvvm_scalar_arithmetic_subnormal(ctx).as_deref()
+                        == Some(&ScalarArithmeticSubnormalAttr::Preserve)
+                }
+                GeneratedScalarArithmeticSubnormal::Ftz => {
+                    op.get_attr_nvvm_scalar_arithmetic_subnormal(ctx).as_deref()
+                        == Some(&ScalarArithmeticSubnormalAttr::Ftz)
+                }
+            };
+            let saturation_matches = match saturation {
+                GeneratedScalarArithmeticSaturation::None => {
+                    op.get_attr_nvvm_scalar_arithmetic_saturation(ctx)
+                        .as_deref()
+                        == Some(&ScalarArithmeticSaturationAttr::None)
+                }
+                GeneratedScalarArithmeticSaturation::Sat => {
+                    op.get_attr_nvvm_scalar_arithmetic_saturation(ctx)
+                        .as_deref()
+                        == Some(&ScalarArithmeticSaturationAttr::Sat)
+                }
+            };
+            format_matches
+                && operation_matches
+                && rounding_matches
+                && subnormal_matches
+                && saturation_matches
+        }
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format,
+            operation: minmax_operation,
+            subnormal,
+            nan,
+            xorsign_abs,
+        } => {
+            let Some(op) = Operation::get_op::<ExtendedMinMaxOp>(operation, ctx) else {
+                return false;
+            };
+            let format_matches = match format {
+                GeneratedExtendedMinMaxFormat::F32 => {
+                    op.get_attr_nvvm_extended_minmax_format(ctx).as_deref()
+                        == Some(&ExtendedMinMaxFormatAttr::F32)
+                }
+                GeneratedExtendedMinMaxFormat::F16 => {
+                    op.get_attr_nvvm_extended_minmax_format(ctx).as_deref()
+                        == Some(&ExtendedMinMaxFormatAttr::F16)
+                }
+                GeneratedExtendedMinMaxFormat::Bf16 => {
+                    op.get_attr_nvvm_extended_minmax_format(ctx).as_deref()
+                        == Some(&ExtendedMinMaxFormatAttr::Bf16)
+                }
+                GeneratedExtendedMinMaxFormat::F16x2 => {
+                    op.get_attr_nvvm_extended_minmax_format(ctx).as_deref()
+                        == Some(&ExtendedMinMaxFormatAttr::F16x2)
+                }
+                GeneratedExtendedMinMaxFormat::Bf16x2 => {
+                    op.get_attr_nvvm_extended_minmax_format(ctx).as_deref()
+                        == Some(&ExtendedMinMaxFormatAttr::Bf16x2)
+                }
+            };
+            let operation_matches = match minmax_operation {
+                GeneratedExtendedMinMaxOperation::Min => {
+                    op.get_attr_nvvm_extended_minmax_operation(ctx).as_deref()
+                        == Some(&ExtendedMinMaxOperationAttr::Min)
+                }
+                GeneratedExtendedMinMaxOperation::Max => {
+                    op.get_attr_nvvm_extended_minmax_operation(ctx).as_deref()
+                        == Some(&ExtendedMinMaxOperationAttr::Max)
+                }
+            };
+            let subnormal_matches = match subnormal {
+                GeneratedExtendedMinMaxSubnormal::Preserve => {
+                    op.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref()
+                        == Some(&ExtendedMinMaxSubnormalAttr::Preserve)
+                }
+                GeneratedExtendedMinMaxSubnormal::Ftz => {
+                    op.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref()
+                        == Some(&ExtendedMinMaxSubnormalAttr::Ftz)
+                }
+            };
+            let nan_matches = match nan {
+                GeneratedExtendedMinMaxNan::Number => {
+                    op.get_attr_nvvm_extended_minmax_nan(ctx).as_deref()
+                        == Some(&ExtendedMinMaxNanAttr::Number)
+                }
+                GeneratedExtendedMinMaxNan::Nan => {
+                    op.get_attr_nvvm_extended_minmax_nan(ctx).as_deref()
+                        == Some(&ExtendedMinMaxNanAttr::Nan)
+                }
+            };
+            let xorsign_abs_matches = match xorsign_abs {
+                false => {
+                    op.get_attr_nvvm_extended_minmax_xorsign_abs(ctx).as_deref()
+                        == Some(&ExtendedMinMaxXorSignAbsAttr::Disabled)
+                }
+                true => {
+                    op.get_attr_nvvm_extended_minmax_xorsign_abs(ctx).as_deref()
+                        == Some(&ExtendedMinMaxXorSignAbsAttr::Enabled)
+                }
+            };
+            format_matches
+                && operation_matches
+                && subnormal_matches
+                && nan_matches
+                && xorsign_abs_matches
+        }
+    }
+}
+
+use dialect_nvvm::ops::{
+    ClusterBarrierModeAttr, ClusterBarrierOp, ExtendedMinMaxFormatAttr, ExtendedMinMaxNanAttr,
+    ExtendedMinMaxOp, ExtendedMinMaxOperationAttr, ExtendedMinMaxSubnormalAttr,
+    ExtendedMinMaxXorSignAbsAttr, LdmatrixElementAttr, LdmatrixLayoutAttr,
+    LdmatrixMultiplicityAttr, LdmatrixOp, LdmatrixShapeAttr, LdmatrixStateSpaceAttr,
+    PackedAtomicAddOp, PackedAtomicAtomicityAttr, PackedAtomicFormatAttr, PackedAtomicOrderingAttr,
+    PackedAtomicRoundingAttr, PackedAtomicScopeAttr, PackedAtomicStateSpaceAttr,
+    PackedAtomicSubnormalAttr, PrmtModeAttr, PrmtOp, RegisterMmaAccumulatorAttr,
+    RegisterMmaElementAttr, RegisterMmaKindAttr, RegisterMmaLayoutAttr, RegisterMmaOp,
+    RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr,
+    ScalarArithmeticFormatAttr, ScalarArithmeticOp, ScalarArithmeticOperationAttr,
+    ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr,
+    ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr,
+    SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr,
+    SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr,
+    Tcgen05MmaBBufferAttr, Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr,
+    Tcgen05MmaFormAttr, Tcgen05MmaKindAttr, Tcgen05MmaOp, WgmmaCommitGroupSyncAlignedOp,
+    WgmmaFenceSyncAlignedOp, WgmmaWaitGroupSyncAlignedOp,
+};
+use pliron::{
+    context::{Context, Ptr},
+    operation::Operation,
+};
+
+mod active_mask;
+mod clc;
+mod cluster_barrier;
+mod cluster_memory;
+mod cp_async;
+mod debug_control;
+mod dotprod;
+mod elect;
+mod execution_control;
+mod extended_minmax;
+mod integer_minmax;
+mod ldmatrix;
+mod mbarrier_basic;
+mod mbarrier_extended;
+mod movmatrix;
+mod packed_alu;
+mod packed_atomic;
+mod packed_conversion;
+mod prmt;
+mod redux;
+mod register_mma;
+mod scalar_arithmetic;
+mod scalar_conversion;
+mod scalar_math;
+mod sparse_mma;
+mod sreg;
+mod stmatrix;
+mod sync;
+mod tcgen05_cp;
+mod tcgen05_ld;
+mod tcgen05_mma;
+mod tcgen05_mma_ws;
+mod tcgen05_other;
+mod tcgen05_st;
+mod tma;
+mod vote;
+mod warp_barrier;
+mod warp_match;
+mod warp_shuffle;
+mod wgmma_control;
+
+#[cfg(test)]
+mod tests;
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs
new file mode 100644
index 0000000000..eb1aa984b8
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs
@@ -0,0 +1,50 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `movmatrix` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedPtxVersion, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[GeneratedIntrinsicTarget {
+    marker: "v1:i0305",
+    id: "movmatrix_trans_b16",
+    abi_id: "i0305",
+    dialect_op: "nvvm.movmatrix_trans_b16",
+    variant: GeneratedIntrinsicVariant::Scalar,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+        hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]),
+    },
+    backend_requirements: &[
+        GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(75),
+                ]),
+            },
+        },
+        GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LibNvvm,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(75),
+                ]),
+            },
+        },
+    ],
+    selections: &[],
+    llvm: None,
+}];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs
new file mode 100644
index 0000000000..eab8d54094
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs
@@ -0,0 +1,1295 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `packed_alu` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0062",
+        id: "fma_bf16x2",
+        abi_id: "i0062",
+        dialect_op: "nvvm.fma_bf16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_bf16x2",
+            asm: "fma.rn.bf16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0063",
+        id: "fma_relu_bf16x2",
+        abi_id: "i0063",
+        dialect_op: "nvvm.fma_relu_bf16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_relu_bf16x2",
+            asm: "fma.rn.relu.bf16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0064",
+        id: "add_bf16x2",
+        abi_id: "i0064",
+        dialect_op: "nvvm.add_bf16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0065",
+        id: "sub_bf16x2",
+        abi_id: "i0065",
+        dialect_op: "nvvm.sub_bf16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0066",
+        id: "mul_bf16x2",
+        abi_id: "i0066",
+        dialect_op: "nvvm.mul_bf16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0067",
+        id: "min_bf16x2",
+        abi_id: "i0067",
+        dialect_op: "nvvm.min_bf16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_bf16x2",
+            asm: "min.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0068",
+        id: "max_bf16x2",
+        abi_id: "i0068",
+        dialect_op: "nvvm.max_bf16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_bf16x2",
+            asm: "max.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0069",
+        id: "neg_bf16x2",
+        abi_id: "i0069",
+        dialect_op: "nvvm.neg_bf16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_NEG_BF16X2",
+            asm: "neg.bf16x2 \t$dst, $src0;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0070",
+        id: "abs_bf16x2",
+        abi_id: "i0070",
+        dialect_op: "nvvm.abs_bf16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "ABS_BF16X2",
+            asm: "abs.bf16x2 \t$dst, $src0;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0072",
+        id: "fma_f16x2",
+        abi_id: "i0072",
+        dialect_op: "nvvm.fma_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_f16x2",
+            asm: "fma.rn.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 53",
+                "Subtarget->getPTXVersion() >= 42",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0073",
+        id: "fma_relu_f16x2",
+        abi_id: "i0073",
+        dialect_op: "nvvm.fma_relu_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_relu_f16x2",
+            asm: "fma.rn.relu.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0074",
+        id: "add_f16x2",
+        abi_id: "i0074",
+        dialect_op: "nvvm.add_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0075",
+        id: "sub_f16x2",
+        abi_id: "i0075",
+        dialect_op: "nvvm.sub_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0076",
+        id: "mul_f16x2",
+        abi_id: "i0076",
+        dialect_op: "nvvm.mul_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0077",
+        id: "min_f16x2",
+        abi_id: "i0077",
+        dialect_op: "nvvm.min_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_f16x2",
+            asm: "min.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0078",
+        id: "max_f16x2",
+        abi_id: "i0078",
+        dialect_op: "nvvm.max_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_f16x2",
+            asm: "max.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0079",
+        id: "neg_f16x2",
+        abi_id: "i0079",
+        dialect_op: "nvvm.neg_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0080",
+        id: "abs_f16x2",
+        abi_id: "i0080",
+        dialect_op: "nvvm.abs_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "ABS_F16X2",
+            asm: "abs.f16x2 \t$dst, $src0;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 53",
+                "Subtarget->getPTXVersion() >= 65",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0854",
+        id: "fma_ftz_f16x2",
+        abi_id: "i0854",
+        dialect_op: "nvvm.fma_ftz_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_ftz_f16x2",
+            asm: "fma.rn.ftz.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 53",
+                "Subtarget->getPTXVersion() >= 42",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0855",
+        id: "fma_sat_f16x2",
+        abi_id: "i0855",
+        dialect_op: "nvvm.fma_sat_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_sat_f16x2",
+            asm: "fma.rn.sat.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 53",
+                "Subtarget->getPTXVersion() >= 42",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0856",
+        id: "fma_ftz_sat_f16x2",
+        abi_id: "i0856",
+        dialect_op: "nvvm.fma_ftz_sat_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_ftz_sat_f16x2",
+            asm: "fma.rn.ftz.sat.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 53",
+                "Subtarget->getPTXVersion() >= 42",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0857",
+        id: "fma_ftz_relu_f16x2",
+        abi_id: "i0857",
+        dialect_op: "nvvm.fma_ftz_relu_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_ftz_relu_f16x2",
+            asm: "fma.rn.ftz.relu.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0995",
+        id: "add_f32x2",
+        abi_id: "i0995",
+        dialect_op: "nvvm.add_f32x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0996",
+        id: "add_ftz_f32x2",
+        abi_id: "i0996",
+        dialect_op: "nvvm.add_ftz_f32x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0997",
+        id: "sub_f32x2",
+        abi_id: "i0997",
+        dialect_op: "nvvm.sub_f32x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0998",
+        id: "sub_ftz_f32x2",
+        abi_id: "i0998",
+        dialect_op: "nvvm.sub_ftz_f32x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0999",
+        id: "mul_f32x2",
+        abi_id: "i0999",
+        dialect_op: "nvvm.mul_f32x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1000",
+        id: "mul_ftz_f32x2",
+        abi_id: "i1000",
+        dialect_op: "nvvm.mul_ftz_f32x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1001",
+        id: "fma_f32x2",
+        abi_id: "i1001",
+        dialect_op: "nvvm.fma_f32x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1002",
+        id: "fma_ftz_f32x2",
+        abi_id: "i1002",
+        dialect_op: "nvvm.fma_ftz_f32x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs
new file mode 100644
index 0000000000..7c046da09a
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs
@@ -0,0 +1,93 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `packed_atomic` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedPackedAtomicFormat, GeneratedPtxVersion, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0014",
+        id: "packed_atomic_add_f16x2",
+        abi_id: "i0014",
+        dialect_op: "nvvm.packed_atomic_add",
+        variant: GeneratedIntrinsicVariant::PackedAtomic {
+            format: GeneratedPackedAtomicFormat::F16x2,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(62),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(62),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(70),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(62),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0015",
+        id: "packed_atomic_add_bf16x2",
+        abi_id: "i0015",
+        dialect_op: "nvvm.packed_atomic_add",
+        variant: GeneratedIntrinsicVariant::PackedAtomic {
+            format: GeneratedPackedAtomicFormat::Bf16x2,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs
new file mode 100644
index 0000000000..14c480e670
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs
@@ -0,0 +1,721 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `packed_conversion` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0071",
+        id: "cvt_f32x2_bf16x2",
+        abi_id: "i0071",
+        dialect_op: "nvvm.cvt_f32x2_bf16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0081",
+        id: "cvt_f16x2_f32",
+        abi_id: "i0081",
+        dialect_op: "nvvm.cvt_f16x2_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0082",
+        id: "cvt_rz_f16x2_f32",
+        abi_id: "i0082",
+        dialect_op: "nvvm.cvt_rz_f16x2_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0083",
+        id: "cvt_rn_relu_f16x2_f32",
+        abi_id: "i0083",
+        dialect_op: "nvvm.cvt_rn_relu_f16x2_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0084",
+        id: "cvt_rn_relu_bf16x2_f32",
+        abi_id: "i0084",
+        dialect_op: "nvvm.cvt_rn_relu_bf16x2_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0085",
+        id: "cvt_rz_bf16x2_f32",
+        abi_id: "i0085",
+        dialect_op: "nvvm.cvt_rz_bf16x2_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0259",
+        id: "cvt_rn_satfinite_e4m3x2_f32",
+        abi_id: "i0259",
+        dialect_op: "nvvm.cvt_rn_satfinite_e4m3x2_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0260",
+        id: "cvt_rn_satfinite_relu_e4m3x2_f32",
+        abi_id: "i0260",
+        dialect_op: "nvvm.cvt_rn_satfinite_relu_e4m3x2_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0261",
+        id: "cvt_rn_satfinite_e5m2x2_f32",
+        abi_id: "i0261",
+        dialect_op: "nvvm.cvt_rn_satfinite_e5m2x2_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0262",
+        id: "cvt_rn_satfinite_relu_e5m2x2_f32",
+        abi_id: "i0262",
+        dialect_op: "nvvm.cvt_rn_satfinite_relu_e5m2x2_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0822",
+        id: "cvt_rn_satfinite_e4m3x2_f16x2",
+        abi_id: "i0822",
+        dialect_op: "nvvm.cvt_rn_satfinite_e4m3x2_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0823",
+        id: "cvt_rn_satfinite_relu_e4m3x2_f16x2",
+        abi_id: "i0823",
+        dialect_op: "nvvm.cvt_rn_satfinite_relu_e4m3x2_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0824",
+        id: "cvt_rn_satfinite_e5m2x2_f16x2",
+        abi_id: "i0824",
+        dialect_op: "nvvm.cvt_rn_satfinite_e5m2x2_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0825",
+        id: "cvt_rn_satfinite_relu_e5m2x2_f16x2",
+        abi_id: "i0825",
+        dialect_op: "nvvm.cvt_rn_satfinite_relu_e5m2x2_f16x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0826",
+        id: "cvt_rn_f16x2_e4m3x2",
+        abi_id: "i0826",
+        dialect_op: "nvvm.cvt_rn_f16x2_e4m3x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0827",
+        id: "cvt_rn_relu_f16x2_e4m3x2",
+        abi_id: "i0827",
+        dialect_op: "nvvm.cvt_rn_relu_f16x2_e4m3x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0828",
+        id: "cvt_rn_f16x2_e5m2x2",
+        abi_id: "i0828",
+        dialect_op: "nvvm.cvt_rn_f16x2_e5m2x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0829",
+        id: "cvt_rn_relu_f16x2_e5m2x2",
+        abi_id: "i0829",
+        dialect_op: "nvvm.cvt_rn_relu_f16x2_e5m2x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs
new file mode 100644
index 0000000000..f5e87f6682
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs
@@ -0,0 +1,306 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `prmt` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPrmtMode, GeneratedPtxVersion, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0252",
+        id: "prmt",
+        abi_id: "i0252",
+        dialect_op: "nvvm.prmt",
+        variant: GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::Generic,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0253",
+        id: "prmt_f4e",
+        abi_id: "i0253",
+        dialect_op: "nvvm.prmt",
+        variant: GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::F4e,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0254",
+        id: "prmt_b4e",
+        abi_id: "i0254",
+        dialect_op: "nvvm.prmt",
+        variant: GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::B4e,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0255",
+        id: "prmt_rc8",
+        abi_id: "i0255",
+        dialect_op: "nvvm.prmt",
+        variant: GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::Rc8,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0256",
+        id: "prmt_ecl",
+        abi_id: "i0256",
+        dialect_op: "nvvm.prmt",
+        variant: GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::Ecl,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0257",
+        id: "prmt_ecr",
+        abi_id: "i0257",
+        dialect_op: "nvvm.prmt",
+        variant: GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::Ecr,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0258",
+        id: "prmt_rc16",
+        abi_id: "i0258",
+        dialect_op: "nvvm.prmt",
+        variant: GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::Rc16,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs
new file mode 100644
index 0000000000..d03abc9a63
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs
@@ -0,0 +1,579 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `redux` intrinsics.
+
+use super::{
+    GeneratedHardwareAlternative, GeneratedHardwareTarget, GeneratedIntrinsicTarget,
+    GeneratedIntrinsicVariant, GeneratedLlvmFacts, GeneratedPtxVersion,
+    GeneratedSelectionAlternative, GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0017",
+        id: "redux_sync_add",
+        abi_id: "i0017",
+        dialect_op: "nvvm.redux_sync_add",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15029",
+            asm: "redux.sync.add.s32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0018",
+        id: "redux_sync_min_u32",
+        abi_id: "i0018",
+        dialect_op: "nvvm.redux_sync_umin",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15027",
+            asm: "redux.sync.min.u32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0019",
+        id: "redux_sync_min_i32",
+        abi_id: "i0019",
+        dialect_op: "nvvm.redux_sync_min",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15030",
+            asm: "redux.sync.min.s32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0020",
+        id: "redux_sync_max_u32",
+        abi_id: "i0020",
+        dialect_op: "nvvm.redux_sync_umax",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15028",
+            asm: "redux.sync.max.u32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0021",
+        id: "redux_sync_max_i32",
+        abi_id: "i0021",
+        dialect_op: "nvvm.redux_sync_max",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15031",
+            asm: "redux.sync.max.s32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0022",
+        id: "redux_sync_and",
+        abi_id: "i0022",
+        dialect_op: "nvvm.redux_sync_and",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15032",
+            asm: "redux.sync.and.b32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0023",
+        id: "redux_sync_or",
+        abi_id: "i0023",
+        dialect_op: "nvvm.redux_sync_or",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15034",
+            asm: "redux.sync.or.b32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0024",
+        id: "redux_sync_xor",
+        abi_id: "i0024",
+        dialect_op: "nvvm.redux_sync_xor",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15033",
+            asm: "redux.sync.xor.b32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1003",
+        id: "redux_sync_min_f32",
+        abi_id: "i1003",
+        dialect_op: "nvvm.redux_sync_fmin",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15035",
+            asm: "redux.sync.min.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1004",
+        id: "redux_sync_min_nan_f32",
+        abi_id: "i1004",
+        dialect_op: "nvvm.redux_sync_fmin_nan",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15038",
+            asm: "redux.sync.min.NaN.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1005",
+        id: "redux_sync_min_abs_f32",
+        abi_id: "i1005",
+        dialect_op: "nvvm.redux_sync_fmin_abs",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15037",
+            asm: "redux.sync.min.abs.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1006",
+        id: "redux_sync_min_abs_nan_f32",
+        abi_id: "i1006",
+        dialect_op: "nvvm.redux_sync_fmin_abs_nan",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15039",
+            asm: "redux.sync.min.abs.NaN.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1007",
+        id: "redux_sync_max_f32",
+        abi_id: "i1007",
+        dialect_op: "nvvm.redux_sync_fmax",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15040",
+            asm: "redux.sync.max.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1008",
+        id: "redux_sync_max_nan_f32",
+        abi_id: "i1008",
+        dialect_op: "nvvm.redux_sync_fmax_nan",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15042",
+            asm: "redux.sync.max.NaN.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1009",
+        id: "redux_sync_max_abs_f32",
+        abi_id: "i1009",
+        dialect_op: "nvvm.redux_sync_fmax_abs",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15041",
+            asm: "redux.sync.max.abs.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1010",
+        id: "redux_sync_max_abs_nan_f32",
+        abi_id: "i1010",
+        dialect_op: "nvvm.redux_sync_fmax_abs_nan",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15043",
+            asm: "redux.sync.max.abs.NaN.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs
new file mode 100644
index 0000000000..e33f861d67
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs
@@ -0,0 +1,9715 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `register_mma` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedRegisterMmaAccumulator,
+    GeneratedRegisterMmaElement, GeneratedRegisterMmaKind, GeneratedRegisterMmaLayout,
+    GeneratedRegisterMmaOperation, GeneratedRegisterMmaOverflow, GeneratedRegisterMmaShape,
+    GeneratedSelectionAlternative, GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0105",
+        id: "mma_m16n8k16_f32_bf16",
+        abi_id: "i0105",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::Bf16,
+            b_element: GeneratedRegisterMmaElement::Bf16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_18973",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0106",
+        id: "mma_m16n8k16_f32_f16",
+        abi_id: "i0106",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::F16,
+            b_element: GeneratedRegisterMmaElement::F16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19051",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0107",
+        id: "mma_m16n8k8_f32_tf32",
+        abi_id: "i0107",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k8,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::Tf32,
+            b_element: GeneratedRegisterMmaElement::Tf32,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_18964",
+            asm: "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0108",
+        id: "mma_m16n8k32_s32_s8",
+        abi_id: "i0108",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19407",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0109",
+        id: "mma_m8n8k4_f64",
+        abi_id: "i0109",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k4,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F64,
+            a_element: GeneratedRegisterMmaElement::F64,
+            b_element: GeneratedRegisterMmaElement::F64,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_18989",
+            asm: "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0110",
+        id: "mma_m16n8k16_s32_s8",
+        abi_id: "i0110",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19383",
+            asm: "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0111",
+        id: "mma_m16n8k16_s32_s8_u8",
+        abi_id: "i0111",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19388",
+            asm: "mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0112",
+        id: "mma_m16n8k16_s32_u8",
+        abi_id: "i0112",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19398",
+            asm: "mma.sync.aligned.m16n8k16.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0113",
+        id: "mma_m16n8k16_s32_u8_s8",
+        abi_id: "i0113",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19394",
+            asm: "mma.sync.aligned.m16n8k16.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0114",
+        id: "mma_m16n8k32_s32_s8_u8",
+        abi_id: "i0114",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19412",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0115",
+        id: "mma_m16n8k32_s32_u8",
+        abi_id: "i0115",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19422",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0116",
+        id: "mma_m16n8k32_s32_u8_s8",
+        abi_id: "i0116",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19418",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0117",
+        id: "mma_m16n8k16_s32_s8_satfinite",
+        abi_id: "i0117",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19546",
+            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0118",
+        id: "mma_m16n8k16_s32_s8_u8_satfinite",
+        abi_id: "i0118",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19549",
+            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0119",
+        id: "mma_m16n8k16_s32_u8_satfinite",
+        abi_id: "i0119",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19555",
+            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0120",
+        id: "mma_m16n8k16_s32_u8_s8_satfinite",
+        abi_id: "i0120",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19552",
+            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0121",
+        id: "mma_m16n8k32_s32_s8_satfinite",
+        abi_id: "i0121",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19558",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0122",
+        id: "mma_m16n8k32_s32_s8_u8_satfinite",
+        abi_id: "i0122",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19561",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0123",
+        id: "mma_m16n8k32_s32_u8_satfinite",
+        abi_id: "i0123",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19567",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0124",
+        id: "mma_m16n8k32_s32_u8_s8_satfinite",
+        abi_id: "i0124",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19564",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0125",
+        id: "mma_m8n8k16_s32_s8",
+        abi_id: "i0125",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19359",
+            asm: "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0126",
+        id: "mma_m8n8k16_s32_s8_u8",
+        abi_id: "i0126",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19364",
+            asm: "mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0127",
+        id: "mma_m8n8k16_s32_u8",
+        abi_id: "i0127",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19374",
+            asm: "mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0128",
+        id: "mma_m8n8k16_s32_u8_s8",
+        abi_id: "i0128",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19370",
+            asm: "mma.sync.aligned.m8n8k16.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0129",
+        id: "mma_m8n8k16_s32_s8_satfinite",
+        abi_id: "i0129",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19534",
+            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0130",
+        id: "mma_m8n8k16_s32_s8_u8_satfinite",
+        abi_id: "i0130",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19537",
+            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0131",
+        id: "mma_m8n8k16_s32_u8_satfinite",
+        abi_id: "i0131",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19543",
+            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0132",
+        id: "mma_m8n8k16_s32_u8_s8_satfinite",
+        abi_id: "i0132",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19540",
+            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0133",
+        id: "mma_m8n8k32_s32_s4",
+        abi_id: "i0133",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19431",
+            asm: "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0134",
+        id: "mma_m8n8k32_s32_s4_u4",
+        abi_id: "i0134",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19436",
+            asm: "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0135",
+        id: "mma_m8n8k32_s32_u4",
+        abi_id: "i0135",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19446",
+            asm: "mma.sync.aligned.m8n8k32.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0136",
+        id: "mma_m8n8k32_s32_u4_s4",
+        abi_id: "i0136",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19442",
+            asm: "mma.sync.aligned.m8n8k32.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0137",
+        id: "mma_m8n8k32_s32_s4_satfinite",
+        abi_id: "i0137",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19570",
+            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0138",
+        id: "mma_m8n8k32_s32_s4_u4_satfinite",
+        abi_id: "i0138",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19573",
+            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0139",
+        id: "mma_m8n8k32_s32_u4_satfinite",
+        abi_id: "i0139",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19579",
+            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0140",
+        id: "mma_m8n8k32_s32_u4_s4_satfinite",
+        abi_id: "i0140",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19576",
+            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0141",
+        id: "mma_m16n8k32_s32_s4",
+        abi_id: "i0141",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19453",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0142",
+        id: "mma_m16n8k32_s32_s4_u4",
+        abi_id: "i0142",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19458",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0143",
+        id: "mma_m16n8k32_s32_u4",
+        abi_id: "i0143",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19468",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0144",
+        id: "mma_m16n8k32_s32_u4_s4",
+        abi_id: "i0144",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19464",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0145",
+        id: "mma_m16n8k64_s32_s4",
+        abi_id: "i0145",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19477",
+            asm: "mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0146",
+        id: "mma_m16n8k64_s32_s4_u4",
+        abi_id: "i0146",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19482",
+            asm: "mma.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0147",
+        id: "mma_m16n8k64_s32_u4",
+        abi_id: "i0147",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19492",
+            asm: "mma.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0148",
+        id: "mma_m16n8k64_s32_u4_s4",
+        abi_id: "i0148",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19488",
+            asm: "mma.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0149",
+        id: "mma_m16n8k32_s32_s4_satfinite",
+        abi_id: "i0149",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19582",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0150",
+        id: "mma_m16n8k32_s32_s4_u4_satfinite",
+        abi_id: "i0150",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19585",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0151",
+        id: "mma_m16n8k32_s32_u4_satfinite",
+        abi_id: "i0151",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19591",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0152",
+        id: "mma_m16n8k32_s32_u4_s4_satfinite",
+        abi_id: "i0152",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19588",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0153",
+        id: "mma_m16n8k64_s32_s4_satfinite",
+        abi_id: "i0153",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19594",
+            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0154",
+        id: "mma_m16n8k64_s32_s4_u4_satfinite",
+        abi_id: "i0154",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19597",
+            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0155",
+        id: "mma_m16n8k64_s32_u4_satfinite",
+        abi_id: "i0155",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19603",
+            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0156",
+        id: "mma_m16n8k64_s32_u4_s4_satfinite",
+        abi_id: "i0156",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19600",
+            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0157",
+        id: "mma_m8n8k128_s32_b1_xor_popc",
+        abi_id: "i0157",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k128,
+            operation: GeneratedRegisterMmaOperation::XorPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19501",
+            asm: "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0158",
+        id: "mma_m16n8k128_s32_b1_xor_popc",
+        abi_id: "i0158",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k128,
+            operation: GeneratedRegisterMmaOperation::XorPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19514",
+            asm: "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0159",
+        id: "mma_m16n8k256_s32_b1_xor_popc",
+        abi_id: "i0159",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k256,
+            operation: GeneratedRegisterMmaOperation::XorPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19527",
+            asm: "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0160",
+        id: "mma_m8n8k128_s32_b1_and_popc",
+        abi_id: "i0160",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k128,
+            operation: GeneratedRegisterMmaOperation::AndPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19505",
+            asm: "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0161",
+        id: "mma_m16n8k128_s32_b1_and_popc",
+        abi_id: "i0161",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k128,
+            operation: GeneratedRegisterMmaOperation::AndPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19518",
+            asm: "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0162",
+        id: "mma_m16n8k256_s32_b1_and_popc",
+        abi_id: "i0162",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k256,
+            operation: GeneratedRegisterMmaOperation::AndPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19531",
+            asm: "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0454",
+        id: "mma_m16n8k32_f32_e2m1_e2m1",
+        abi_id: "i0454",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19350",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0455",
+        id: "mma_m16n8k32_f32_e2m1_e2m3",
+        abi_id: "i0455",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19342",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0456",
+        id: "mma_m16n8k32_f32_e2m1_e3m2",
+        abi_id: "i0456",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19334",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0457",
+        id: "mma_m16n8k32_f32_e2m1_e4m3",
+        abi_id: "i0457",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19318",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0458",
+        id: "mma_m16n8k32_f32_e2m1_e5m2",
+        abi_id: "i0458",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19326",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0459",
+        id: "mma_m16n8k32_f32_e2m3_e2m1",
+        abi_id: "i0459",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19308",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0460",
+        id: "mma_m16n8k32_f32_e2m3_e2m3",
+        abi_id: "i0460",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19300",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0461",
+        id: "mma_m16n8k32_f32_e2m3_e3m2",
+        abi_id: "i0461",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19292",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0462",
+        id: "mma_m16n8k32_f32_e2m3_e4m3",
+        abi_id: "i0462",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19276",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0463",
+        id: "mma_m16n8k32_f32_e2m3_e5m2",
+        abi_id: "i0463",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19284",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0464",
+        id: "mma_m16n8k32_f32_e3m2_e2m1",
+        abi_id: "i0464",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19266",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0465",
+        id: "mma_m16n8k32_f32_e3m2_e2m3",
+        abi_id: "i0465",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19258",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0466",
+        id: "mma_m16n8k32_f32_e3m2_e3m2",
+        abi_id: "i0466",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19250",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0467",
+        id: "mma_m16n8k32_f32_e3m2_e4m3",
+        abi_id: "i0467",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19234",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0468",
+        id: "mma_m16n8k32_f32_e3m2_e5m2",
+        abi_id: "i0468",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19242",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0469",
+        id: "mma_m16n8k32_f32_e4m3_e2m1",
+        abi_id: "i0469",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19164",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0470",
+        id: "mma_m16n8k32_f32_e4m3_e2m3",
+        abi_id: "i0470",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19155",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0471",
+        id: "mma_m16n8k32_f32_e4m3_e3m2",
+        abi_id: "i0471",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19146",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0472",
+        id: "mma_m16n8k32_f32_e4m3_e4m3",
+        abi_id: "i0472",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19119",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0473",
+        id: "mma_m16n8k32_f32_e4m3_e5m2",
+        abi_id: "i0473",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19137",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0474",
+        id: "mma_m16n8k32_f32_e5m2_e2m1",
+        abi_id: "i0474",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19224",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0475",
+        id: "mma_m16n8k32_f32_e5m2_e2m3",
+        abi_id: "i0475",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19216",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0476",
+        id: "mma_m16n8k32_f32_e5m2_e3m2",
+        abi_id: "i0476",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19208",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0477",
+        id: "mma_m16n8k32_f32_e5m2_e4m3",
+        abi_id: "i0477",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19184",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0478",
+        id: "mma_m16n8k32_f32_e5m2_e5m2",
+        abi_id: "i0478",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19200",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0479",
+        id: "mma_m16n8k32_f16_e2m1_e2m1",
+        abi_id: "i0479",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19346",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0480",
+        id: "mma_m16n8k32_f16_e2m1_e2m3",
+        abi_id: "i0480",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19338",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0481",
+        id: "mma_m16n8k32_f16_e2m1_e3m2",
+        abi_id: "i0481",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19330",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0482",
+        id: "mma_m16n8k32_f16_e2m1_e4m3",
+        abi_id: "i0482",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19314",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0483",
+        id: "mma_m16n8k32_f16_e2m1_e5m2",
+        abi_id: "i0483",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19322",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0484",
+        id: "mma_m16n8k32_f16_e2m3_e2m1",
+        abi_id: "i0484",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19304",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0485",
+        id: "mma_m16n8k32_f16_e2m3_e2m3",
+        abi_id: "i0485",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19296",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0486",
+        id: "mma_m16n8k32_f16_e2m3_e3m2",
+        abi_id: "i0486",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19288",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0487",
+        id: "mma_m16n8k32_f16_e2m3_e4m3",
+        abi_id: "i0487",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19272",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0488",
+        id: "mma_m16n8k32_f16_e2m3_e5m2",
+        abi_id: "i0488",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19280",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0489",
+        id: "mma_m16n8k32_f16_e3m2_e2m1",
+        abi_id: "i0489",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19262",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0490",
+        id: "mma_m16n8k32_f16_e3m2_e2m3",
+        abi_id: "i0490",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19254",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0491",
+        id: "mma_m16n8k32_f16_e3m2_e3m2",
+        abi_id: "i0491",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19246",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0492",
+        id: "mma_m16n8k32_f16_e3m2_e4m3",
+        abi_id: "i0492",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19230",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0493",
+        id: "mma_m16n8k32_f16_e3m2_e5m2",
+        abi_id: "i0493",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19238",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0494",
+        id: "mma_m16n8k32_f16_e4m3_e2m1",
+        abi_id: "i0494",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19160",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0495",
+        id: "mma_m16n8k32_f16_e4m3_e2m3",
+        abi_id: "i0495",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19151",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0496",
+        id: "mma_m16n8k32_f16_e4m3_e3m2",
+        abi_id: "i0496",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19142",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0497",
+        id: "mma_m16n8k32_f16_e4m3_e4m3",
+        abi_id: "i0497",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19107",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0498",
+        id: "mma_m16n8k32_f16_e4m3_e5m2",
+        abi_id: "i0498",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19129",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0499",
+        id: "mma_m16n8k32_f16_e5m2_e2m1",
+        abi_id: "i0499",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19220",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0500",
+        id: "mma_m16n8k32_f16_e5m2_e2m3",
+        abi_id: "i0500",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19212",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0501",
+        id: "mma_m16n8k32_f16_e5m2_e3m2",
+        abi_id: "i0501",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19204",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0502",
+        id: "mma_m16n8k32_f16_e5m2_e4m3",
+        abi_id: "i0502",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19176",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0503",
+        id: "mma_m16n8k32_f16_e5m2_e5m2",
+        abi_id: "i0503",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19192",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0504",
+        id: "mma_m16n8k16_fp8_f16_e4m3_e4m3",
+        abi_id: "i0504",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19058",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0505",
+        id: "mma_m16n8k16_fp8_f16_e4m3_e5m2",
+        abi_id: "i0505",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19067",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0506",
+        id: "mma_m16n8k16_fp8_f16_e5m2_e4m3",
+        abi_id: "i0506",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19077",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0507",
+        id: "mma_m16n8k16_fp8_f16_e5m2_e5m2",
+        abi_id: "i0507",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19085",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0508",
+        id: "mma_m16n8k16_fp8_f32_e4m3_e4m3",
+        abi_id: "i0508",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19062",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0509",
+        id: "mma_m16n8k16_fp8_f32_e4m3_e5m2",
+        abi_id: "i0509",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19071",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0510",
+        id: "mma_m16n8k16_fp8_f32_e5m2_e4m3",
+        abi_id: "i0510",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19081",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0511",
+        id: "mma_m16n8k16_fp8_f32_e5m2_e5m2",
+        abi_id: "i0511",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19089",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0512",
+        id: "mma_m16n8k32_fp8_f16_e4m3_e4m3",
+        abi_id: "i0512",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19098",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0513",
+        id: "mma_m16n8k32_fp8_f16_e4m3_e5m2",
+        abi_id: "i0513",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19124",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0514",
+        id: "mma_m16n8k32_fp8_f16_e5m2_e4m3",
+        abi_id: "i0514",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19170",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0515",
+        id: "mma_m16n8k32_fp8_f16_e5m2_e5m2",
+        abi_id: "i0515",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19188",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0516",
+        id: "mma_m16n8k32_fp8_f32_e4m3_e4m3",
+        abi_id: "i0516",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19113",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0517",
+        id: "mma_m16n8k32_fp8_f32_e4m3_e5m2",
+        abi_id: "i0517",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19133",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0518",
+        id: "mma_m16n8k32_fp8_f32_e5m2_e4m3",
+        abi_id: "i0518",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19180",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0519",
+        id: "mma_m16n8k32_fp8_f32_e5m2_e5m2",
+        abi_id: "i0519",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                89,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(89),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19196",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0520",
+        id: "mma_m16n8k4_f32_tf32",
+        abi_id: "i0520",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k4,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::Tf32,
+            b_element: GeneratedRegisterMmaElement::Tf32,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_18955",
+            asm: "mma.sync.aligned.m16n8k4.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0521",
+        id: "mma_m16n8k8_f16_f16",
+        abi_id: "i0521",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k8,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::F16,
+            b_element: GeneratedRegisterMmaElement::F16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19034",
+            asm: "mma.sync.aligned.m16n8k8.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0522",
+        id: "mma_m16n8k8_f32_bf16",
+        abi_id: "i0522",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k8,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::Bf16,
+            b_element: GeneratedRegisterMmaElement::Bf16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_18980",
+            asm: "mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0523",
+        id: "mma_m16n8k8_f32_f16",
+        abi_id: "i0523",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k8,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::F16,
+            b_element: GeneratedRegisterMmaElement::F16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19038",
+            asm: "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0524",
+        id: "mma_m16n8k16_f16_f16",
+        abi_id: "i0524",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::F16,
+            b_element: GeneratedRegisterMmaElement::F16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19047",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0858",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1",
+        abi_id: "i0858",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19651",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0859",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3",
+        abi_id: "i0859",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19656",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0860",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2",
+        abi_id: "i0860",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19661",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0861",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3",
+        abi_id: "i0861",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19671",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0862",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2",
+        abi_id: "i0862",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19666",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0863",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1",
+        abi_id: "i0863",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19676",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0864",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3",
+        abi_id: "i0864",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19680",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0865",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2",
+        abi_id: "i0865",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19684",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0866",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3",
+        abi_id: "i0866",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19692",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0867",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2",
+        abi_id: "i0867",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19688",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0868",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1",
+        abi_id: "i0868",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19697",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0869",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3",
+        abi_id: "i0869",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19701",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0870",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2",
+        abi_id: "i0870",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19705",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0871",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3",
+        abi_id: "i0871",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19713",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0872",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2",
+        abi_id: "i0872",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19709",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0873",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1",
+        abi_id: "i0873",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19739",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0874",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3",
+        abi_id: "i0874",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19743",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0875",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2",
+        abi_id: "i0875",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19747",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0876",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3",
+        abi_id: "i0876",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19755",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0877",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2",
+        abi_id: "i0877",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19751",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0878",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1",
+        abi_id: "i0878",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19718",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0879",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3",
+        abi_id: "i0879",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19722",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0880",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2",
+        abi_id: "i0880",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19726",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0881",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3",
+        abi_id: "i0881",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19734",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0882",
+        id: "mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2",
+        abi_id: "i0882",
+        dialect_op: "nvvm.register_mma",
+        variant: GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19730",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs
new file mode 100644
index 0000000000..8dba2636d7
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs
@@ -0,0 +1,3414 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `scalar_arithmetic` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedScalarArithmeticFormat,
+    GeneratedScalarArithmeticOperation, GeneratedScalarArithmeticRounding,
+    GeneratedScalarArithmeticSaturation, GeneratedScalarArithmeticSubnormal,
+    GeneratedSelectionAlternative, GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0390",
+        id: "mul_rn_f64",
+        abi_id: "i0390",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RN_D",
+            asm: "mul.rn.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0391",
+        id: "mul_rz_f64",
+        abi_id: "i0391",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RZ_D",
+            asm: "mul.rz.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0392",
+        id: "mul_rm_f64",
+        abi_id: "i0392",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RM_D",
+            asm: "mul.rm.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0393",
+        id: "mul_rp_f64",
+        abi_id: "i0393",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RP_D",
+            asm: "mul.rp.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0394",
+        id: "div_rn_f64",
+        abi_id: "i0394",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RN_D",
+            asm: "div.rn.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0395",
+        id: "div_rz_f64",
+        abi_id: "i0395",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RZ_D",
+            asm: "div.rz.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0396",
+        id: "div_rm_f64",
+        abi_id: "i0396",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RM_D",
+            asm: "div.rm.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0397",
+        id: "div_rp_f64",
+        abi_id: "i0397",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RP_D",
+            asm: "div.rp.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0398",
+        id: "fma_rn_f64",
+        abi_id: "i0398",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_f64",
+            asm: "fma.rn.f64 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0399",
+        id: "fma_rz_f64",
+        abi_id: "i0399",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rz_f64",
+            asm: "fma.rz.f64 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0400",
+        id: "fma_rm_f64",
+        abi_id: "i0400",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rm_f64",
+            asm: "fma.rm.f64 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0401",
+        id: "fma_rp_f64",
+        abi_id: "i0401",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rp_f64",
+            asm: "fma.rp.f64 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0402",
+        id: "mul_rn_f32",
+        abi_id: "i0402",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RN_F",
+            asm: "mul.rn.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0403",
+        id: "mul_rn_ftz_f32",
+        abi_id: "i0403",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RN_FTZ_F",
+            asm: "mul.rn.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0404",
+        id: "mul_rz_f32",
+        abi_id: "i0404",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RZ_F",
+            asm: "mul.rz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0405",
+        id: "mul_rz_ftz_f32",
+        abi_id: "i0405",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RZ_FTZ_F",
+            asm: "mul.rz.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0406",
+        id: "mul_rm_f32",
+        abi_id: "i0406",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RM_F",
+            asm: "mul.rm.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0407",
+        id: "mul_rm_ftz_f32",
+        abi_id: "i0407",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RM_FTZ_F",
+            asm: "mul.rm.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0408",
+        id: "mul_rp_f32",
+        abi_id: "i0408",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RP_F",
+            asm: "mul.rp.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0409",
+        id: "mul_rp_ftz_f32",
+        abi_id: "i0409",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RP_FTZ_F",
+            asm: "mul.rp.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0410",
+        id: "div_rn_f32",
+        abi_id: "i0410",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RN_F",
+            asm: "div.rn.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0411",
+        id: "div_rn_ftz_f32",
+        abi_id: "i0411",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RN_FTZ_F",
+            asm: "div.rn.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0412",
+        id: "div_rz_f32",
+        abi_id: "i0412",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RZ_F",
+            asm: "div.rz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0413",
+        id: "div_rz_ftz_f32",
+        abi_id: "i0413",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RZ_FTZ_F",
+            asm: "div.rz.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0414",
+        id: "div_rm_f32",
+        abi_id: "i0414",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RM_F",
+            asm: "div.rm.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0415",
+        id: "div_rm_ftz_f32",
+        abi_id: "i0415",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RM_FTZ_F",
+            asm: "div.rm.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0416",
+        id: "div_rp_f32",
+        abi_id: "i0416",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RP_F",
+            asm: "div.rp.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0417",
+        id: "div_rp_ftz_f32",
+        abi_id: "i0417",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RP_FTZ_F",
+            asm: "div.rp.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0418",
+        id: "fma_rn_f32",
+        abi_id: "i0418",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_f32",
+            asm: "fma.rn.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0419",
+        id: "fma_rn_ftz_f32",
+        abi_id: "i0419",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_ftz_f32",
+            asm: "fma.rn.ftz.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0420",
+        id: "fma_rn_sat_f32",
+        abi_id: "i0420",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_sat_f32",
+            asm: "fma.rn.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0421",
+        id: "fma_rn_ftz_sat_f32",
+        abi_id: "i0421",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_ftz_sat_f32",
+            asm: "fma.rn.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0422",
+        id: "fma_rz_f32",
+        abi_id: "i0422",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rz_f32",
+            asm: "fma.rz.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0423",
+        id: "fma_rz_ftz_f32",
+        abi_id: "i0423",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rz_ftz_f32",
+            asm: "fma.rz.ftz.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0424",
+        id: "fma_rz_sat_f32",
+        abi_id: "i0424",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rz_sat_f32",
+            asm: "fma.rz.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0425",
+        id: "fma_rz_ftz_sat_f32",
+        abi_id: "i0425",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rz_ftz_sat_f32",
+            asm: "fma.rz.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0426",
+        id: "fma_rm_f32",
+        abi_id: "i0426",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rm_f32",
+            asm: "fma.rm.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0427",
+        id: "fma_rm_ftz_f32",
+        abi_id: "i0427",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rm_ftz_f32",
+            asm: "fma.rm.ftz.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0428",
+        id: "fma_rm_sat_f32",
+        abi_id: "i0428",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rm_sat_f32",
+            asm: "fma.rm.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0429",
+        id: "fma_rm_ftz_sat_f32",
+        abi_id: "i0429",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rm_ftz_sat_f32",
+            asm: "fma.rm.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0430",
+        id: "fma_rp_f32",
+        abi_id: "i0430",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rp_f32",
+            asm: "fma.rp.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0431",
+        id: "fma_rp_ftz_f32",
+        abi_id: "i0431",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rp_ftz_f32",
+            asm: "fma.rp.ftz.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0432",
+        id: "fma_rp_sat_f32",
+        abi_id: "i0432",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rp_sat_f32",
+            asm: "fma.rp.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0433",
+        id: "fma_rp_ftz_sat_f32",
+        abi_id: "i0433",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rp_ftz_sat_f32",
+            asm: "fma.rp.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0434",
+        id: "add_rn_f64",
+        abi_id: "i0434",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RN_D",
+            asm: "add.rn.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0435",
+        id: "add_rz_f64",
+        abi_id: "i0435",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RZ_D",
+            asm: "add.rz.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0436",
+        id: "add_rm_f64",
+        abi_id: "i0436",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RM_D",
+            asm: "add.rm.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0437",
+        id: "add_rp_f64",
+        abi_id: "i0437",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RP_D",
+            asm: "add.rp.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0438",
+        id: "add_rn_f32",
+        abi_id: "i0438",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RN_F",
+            asm: "add.rn.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0439",
+        id: "add_rn_ftz_f32",
+        abi_id: "i0439",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RN_FTZ_F",
+            asm: "add.rn.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0440",
+        id: "add_rn_sat_f32",
+        abi_id: "i0440",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RN_SAT_F",
+            asm: "add.rn.sat.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0441",
+        id: "add_rn_ftz_sat_f32",
+        abi_id: "i0441",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RN_SAT_FTZ_F",
+            asm: "add.rn.sat.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0442",
+        id: "add_rz_f32",
+        abi_id: "i0442",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RZ_F",
+            asm: "add.rz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0443",
+        id: "add_rz_ftz_f32",
+        abi_id: "i0443",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RZ_FTZ_F",
+            asm: "add.rz.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0444",
+        id: "add_rz_sat_f32",
+        abi_id: "i0444",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RZ_SAT_F",
+            asm: "add.rz.sat.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0445",
+        id: "add_rz_ftz_sat_f32",
+        abi_id: "i0445",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RZ_SAT_FTZ_F",
+            asm: "add.rz.sat.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0446",
+        id: "add_rm_f32",
+        abi_id: "i0446",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RM_F",
+            asm: "add.rm.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0447",
+        id: "add_rm_ftz_f32",
+        abi_id: "i0447",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RM_FTZ_F",
+            asm: "add.rm.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0448",
+        id: "add_rm_sat_f32",
+        abi_id: "i0448",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RM_SAT_F",
+            asm: "add.rm.sat.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0449",
+        id: "add_rm_ftz_sat_f32",
+        abi_id: "i0449",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RM_SAT_FTZ_F",
+            asm: "add.rm.sat.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0450",
+        id: "add_rp_f32",
+        abi_id: "i0450",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RP_F",
+            asm: "add.rp.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0451",
+        id: "add_rp_ftz_f32",
+        abi_id: "i0451",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RP_FTZ_F",
+            asm: "add.rp.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0452",
+        id: "add_rp_sat_f32",
+        abi_id: "i0452",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RP_SAT_F",
+            asm: "add.rp.sat.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0453",
+        id: "add_rp_ftz_sat_f32",
+        abi_id: "i0453",
+        dialect_op: "nvvm.scalar_arithmetic",
+        variant: GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RP_SAT_FTZ_F",
+            asm: "add.rp.sat.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["Commutative", "IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs
new file mode 100644
index 0000000000..1d9732b865
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs
@@ -0,0 +1,551 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `scalar_conversion` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedScalarConversionRounding,
+    GeneratedScalarConversionSaturation, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0368",
+        id: "cvt_rna_tf32_f32",
+        abi_id: "i0368",
+        dialect_op: "nvvm.scalar_conversion",
+        variant: GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestAway,
+            saturation: GeneratedScalarConversionSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rna",
+            asm: "cvt.rna.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0369",
+        id: "cvt_rna_satfinite_tf32_f32",
+        abi_id: "i0369",
+        dialect_op: "nvvm.scalar_conversion",
+        variant: GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestAway,
+            saturation: GeneratedScalarConversionSaturation::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rna_satf",
+            asm: "cvt.rna.satfinite.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 81",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0370",
+        id: "cvt_rn_tf32_f32",
+        abi_id: "i0370",
+        dialect_op: "nvvm.scalar_conversion",
+        variant: GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestEven,
+            saturation: GeneratedScalarConversionSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rn",
+            asm: "cvt.rn.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0371",
+        id: "cvt_rn_relu_tf32_f32",
+        abi_id: "i0371",
+        dialect_op: "nvvm.scalar_conversion",
+        variant: GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestEven,
+            saturation: GeneratedScalarConversionSaturation::Relu,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rn_relu",
+            asm: "cvt.rn.relu.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0372",
+        id: "cvt_rn_satfinite_tf32_f32",
+        abi_id: "i0372",
+        dialect_op: "nvvm.scalar_conversion",
+        variant: GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestEven,
+            saturation: GeneratedScalarConversionSaturation::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rn_satf",
+            asm: "cvt.rn.satfinite.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 100",
+                "Subtarget->getPTXVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0373",
+        id: "cvt_rn_relu_satfinite_tf32_f32",
+        abi_id: "i0373",
+        dialect_op: "nvvm.scalar_conversion",
+        variant: GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestEven,
+            saturation: GeneratedScalarConversionSaturation::ReluSatfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rn_relu_satf",
+            asm: "cvt.rn.relu.satfinite.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 100",
+                "Subtarget->getPTXVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0374",
+        id: "cvt_rz_tf32_f32",
+        abi_id: "i0374",
+        dialect_op: "nvvm.scalar_conversion",
+        variant: GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::TowardZero,
+            saturation: GeneratedScalarConversionSaturation::None,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rz",
+            asm: "cvt.rz.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0375",
+        id: "cvt_rz_relu_tf32_f32",
+        abi_id: "i0375",
+        dialect_op: "nvvm.scalar_conversion",
+        variant: GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::TowardZero,
+            saturation: GeneratedScalarConversionSaturation::Relu,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rz_relu",
+            asm: "cvt.rz.relu.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0376",
+        id: "cvt_rz_satfinite_tf32_f32",
+        abi_id: "i0376",
+        dialect_op: "nvvm.scalar_conversion",
+        variant: GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::TowardZero,
+            saturation: GeneratedScalarConversionSaturation::Satfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rz_satf",
+            asm: "cvt.rz.satfinite.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 100",
+                "Subtarget->getPTXVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0377",
+        id: "cvt_rz_relu_satfinite_tf32_f32",
+        abi_id: "i0377",
+        dialect_op: "nvvm.scalar_conversion",
+        variant: GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::TowardZero,
+            saturation: GeneratedScalarConversionSaturation::ReluSatfinite,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                100,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(100),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rz_relu_satf",
+            asm: "cvt.rz.relu.satfinite.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 100",
+                "Subtarget->getPTXVersion() >= 86",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs
new file mode 100644
index 0000000000..69a0ee3261
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs
@@ -0,0 +1,1839 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `scalar_math` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0782",
+        id: "sin_approx_f32",
+        abi_id: "i0782",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0783",
+        id: "sin_approx_ftz_f32",
+        abi_id: "i0783",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0784",
+        id: "cos_approx_f32",
+        abi_id: "i0784",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0785",
+        id: "cos_approx_ftz_f32",
+        abi_id: "i0785",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0786",
+        id: "lg2_approx_f32",
+        abi_id: "i0786",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0787",
+        id: "lg2_approx_ftz_f32",
+        abi_id: "i0787",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0788",
+        id: "rcp_approx_ftz_f32",
+        abi_id: "i0788",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_APPROX_FTZ_F",
+            asm: "rcp.approx.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0789",
+        id: "rcp_rn_f32",
+        abi_id: "i0789",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RN_F",
+            asm: "rcp.rn.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0790",
+        id: "rcp_rn_ftz_f32",
+        abi_id: "i0790",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RN_FTZ_F",
+            asm: "rcp.rn.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0791",
+        id: "rcp_rz_f32",
+        abi_id: "i0791",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RZ_F",
+            asm: "rcp.rz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0792",
+        id: "rcp_rz_ftz_f32",
+        abi_id: "i0792",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RZ_FTZ_F",
+            asm: "rcp.rz.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0793",
+        id: "rcp_rm_f32",
+        abi_id: "i0793",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RM_F",
+            asm: "rcp.rm.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0794",
+        id: "rcp_rm_ftz_f32",
+        abi_id: "i0794",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RM_FTZ_F",
+            asm: "rcp.rm.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0795",
+        id: "rcp_rp_f32",
+        abi_id: "i0795",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RP_F",
+            asm: "rcp.rp.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0796",
+        id: "rcp_rp_ftz_f32",
+        abi_id: "i0796",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RP_FTZ_F",
+            asm: "rcp.rp.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0797",
+        id: "rcp_approx_ftz_f64",
+        abi_id: "i0797",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_APPROX_FTZ_D",
+            asm: "rcp.approx.ftz.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0798",
+        id: "rcp_rn_f64",
+        abi_id: "i0798",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RN_D",
+            asm: "rcp.rn.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0799",
+        id: "rcp_rz_f64",
+        abi_id: "i0799",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RZ_D",
+            asm: "rcp.rz.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0800",
+        id: "rcp_rm_f64",
+        abi_id: "i0800",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RM_D",
+            asm: "rcp.rm.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0801",
+        id: "rcp_rp_f64",
+        abi_id: "i0801",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RP_D",
+            asm: "rcp.rp.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0802",
+        id: "rsqrt_approx_f32",
+        abi_id: "i0802",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0803",
+        id: "rsqrt_approx_ftz_f32",
+        abi_id: "i0803",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0804",
+        id: "rsqrt_approx_f64",
+        abi_id: "i0804",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0805",
+        id: "sqrt_approx_f32",
+        abi_id: "i0805",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_APPROX_F",
+            asm: "sqrt.approx.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0806",
+        id: "sqrt_approx_ftz_f32",
+        abi_id: "i0806",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_APPROX_FTZ_F",
+            asm: "sqrt.approx.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0807",
+        id: "sqrt_rn_f32",
+        abi_id: "i0807",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RN_F",
+            asm: "sqrt.rn.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0808",
+        id: "sqrt_rn_ftz_f32",
+        abi_id: "i0808",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RN_FTZ_F",
+            asm: "sqrt.rn.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0809",
+        id: "sqrt_rz_f32",
+        abi_id: "i0809",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RZ_F",
+            asm: "sqrt.rz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0810",
+        id: "sqrt_rz_ftz_f32",
+        abi_id: "i0810",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RZ_FTZ_F",
+            asm: "sqrt.rz.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0811",
+        id: "sqrt_rm_f32",
+        abi_id: "i0811",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RM_F",
+            asm: "sqrt.rm.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0812",
+        id: "sqrt_rm_ftz_f32",
+        abi_id: "i0812",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RM_FTZ_F",
+            asm: "sqrt.rm.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0813",
+        id: "sqrt_rp_f32",
+        abi_id: "i0813",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RP_F",
+            asm: "sqrt.rp.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0814",
+        id: "sqrt_rp_ftz_f32",
+        abi_id: "i0814",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RP_FTZ_F",
+            asm: "sqrt.rp.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0815",
+        id: "sqrt_rn_f64",
+        abi_id: "i0815",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RN_D",
+            asm: "sqrt.rn.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0816",
+        id: "sqrt_rz_f64",
+        abi_id: "i0816",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RZ_D",
+            asm: "sqrt.rz.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0817",
+        id: "sqrt_rm_f64",
+        abi_id: "i0817",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RM_D",
+            asm: "sqrt.rm.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0818",
+        id: "sqrt_rp_f64",
+        abi_id: "i0818",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RP_D",
+            asm: "sqrt.rp.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0819",
+        id: "ex2_approx_f32",
+        abi_id: "i0819",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0820",
+        id: "ex2_approx_ftz_f32",
+        abi_id: "i0820",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0821",
+        id: "tanh_approx_f32",
+        abi_id: "i0821",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1016",
+        id: "ex2_approx_f16",
+        abi_id: "i1016",
+        dialect_op: "nvvm.scalar_math",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                75,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs
new file mode 100644
index 0000000000..a4b70a031c
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs
@@ -0,0 +1,7732 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `sparse_mma` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedSparseMmaAccumulator, GeneratedSparseMmaElement,
+    GeneratedSparseMmaLayout, GeneratedSparseMmaMetadata, GeneratedSparseMmaOverflow,
+    GeneratedSparseMmaSelector, GeneratedSparseMmaShape, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0163",
+        id: "mma_sp_m16n8k32_s32_s8",
+        abi_id: "i0163",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19958",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0164",
+        id: "mma_sp_m16n8k32_s32_s8_u8",
+        abi_id: "i0164",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19963",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0165",
+        id: "mma_sp_m16n8k32_s32_u8",
+        abi_id: "i0165",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19972",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0166",
+        id: "mma_sp_m16n8k32_s32_u8_s8",
+        abi_id: "i0166",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19968",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0167",
+        id: "mma_sp_m16n8k32_s32_s8_satfinite",
+        abi_id: "i0167",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20019",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0168",
+        id: "mma_sp_m16n8k32_s32_s8_u8_satfinite",
+        abi_id: "i0168",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20022",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0169",
+        id: "mma_sp_m16n8k32_s32_u8_satfinite",
+        abi_id: "i0169",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20028",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0170",
+        id: "mma_sp_m16n8k32_s32_u8_s8_satfinite",
+        abi_id: "i0170",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20025",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0171",
+        id: "mma_sp_ordered_metadata_m16n8k32_s32_s8",
+        abi_id: "i0171",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20168",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0172",
+        id: "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8",
+        abi_id: "i0172",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20173",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0173",
+        id: "mma_sp_ordered_metadata_m16n8k32_s32_u8",
+        abi_id: "i0173",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20182",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0174",
+        id: "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8",
+        abi_id: "i0174",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20178",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0175",
+        id: "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite",
+        abi_id: "i0175",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20229",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0176",
+        id: "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite",
+        abi_id: "i0176",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20232",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0177",
+        id: "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite",
+        abi_id: "i0177",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20238",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0178",
+        id: "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite",
+        abi_id: "i0178",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20235",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0179",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_s8",
+        abi_id: "i0179",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20188",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0180",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8",
+        abi_id: "i0180",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20193",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0181",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_u8",
+        abi_id: "i0181",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20202",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0182",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8",
+        abi_id: "i0182",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20198",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0183",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite",
+        abi_id: "i0183",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20241",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0184",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite",
+        abi_id: "i0184",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20244",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0185",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite",
+        abi_id: "i0185",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20250",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0186",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite",
+        abi_id: "i0186",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20247",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0187",
+        id: "mma_sp_m16n8k64_s32_s8",
+        abi_id: "i0187",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19978",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0188",
+        id: "mma_sp_m16n8k64_s32_s8_u8",
+        abi_id: "i0188",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19983",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0189",
+        id: "mma_sp_m16n8k64_s32_u8",
+        abi_id: "i0189",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19992",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0190",
+        id: "mma_sp_m16n8k64_s32_u8_s8",
+        abi_id: "i0190",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19988",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0191",
+        id: "mma_sp_m16n8k64_s32_s8_satfinite",
+        abi_id: "i0191",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20031",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0192",
+        id: "mma_sp_m16n8k64_s32_s8_u8_satfinite",
+        abi_id: "i0192",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20034",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0193",
+        id: "mma_sp_m16n8k64_s32_u8_satfinite",
+        abi_id: "i0193",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20040",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0194",
+        id: "mma_sp_m16n8k64_s32_u8_s8_satfinite",
+        abi_id: "i0194",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20037",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0195",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_s4",
+        abi_id: "i0195",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20124",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0196",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4",
+        abi_id: "i0196",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20129",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0197",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_u4",
+        abi_id: "i0197",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20138",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0198",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4",
+        abi_id: "i0198",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20134",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0199",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite",
+        abi_id: "i0199",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20205",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0200",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite",
+        abi_id: "i0200",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20208",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0201",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite",
+        abi_id: "i0201",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20214",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0202",
+        id: "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite",
+        abi_id: "i0202",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20211",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0203",
+        id: "mma_sp_ordered_metadata_m16n8k128_s32_s4",
+        abi_id: "i0203",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20146",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0204",
+        id: "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4",
+        abi_id: "i0204",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20151",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0205",
+        id: "mma_sp_ordered_metadata_m16n8k128_s32_u4",
+        abi_id: "i0205",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20160",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0206",
+        id: "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4",
+        abi_id: "i0206",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20156",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0207",
+        id: "mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite",
+        abi_id: "i0207",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20217",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0208",
+        id: "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite",
+        abi_id: "i0208",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20220",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0209",
+        id: "mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite",
+        abi_id: "i0209",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20226",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0210",
+        id: "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite",
+        abi_id: "i0210",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20223",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0211",
+        id: "mma_sp_m16n8k64_s32_s4",
+        abi_id: "i0211",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19914",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0212",
+        id: "mma_sp_m16n8k64_s32_s4_u4",
+        abi_id: "i0212",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19919",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0213",
+        id: "mma_sp_m16n8k64_s32_u4",
+        abi_id: "i0213",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19928",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0214",
+        id: "mma_sp_m16n8k64_s32_u4_s4",
+        abi_id: "i0214",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19924",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0215",
+        id: "mma_sp_m16n8k64_s32_s4_satfinite",
+        abi_id: "i0215",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19995",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0216",
+        id: "mma_sp_m16n8k64_s32_s4_u4_satfinite",
+        abi_id: "i0216",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19998",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0217",
+        id: "mma_sp_m16n8k64_s32_u4_satfinite",
+        abi_id: "i0217",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20004",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0218",
+        id: "mma_sp_m16n8k64_s32_u4_s4_satfinite",
+        abi_id: "i0218",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20001",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg9>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg9,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0219",
+        id: "mma_sp_m16n8k128_s32_s4",
+        abi_id: "i0219",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19936",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0220",
+        id: "mma_sp_m16n8k128_s32_s4_u4",
+        abi_id: "i0220",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19941",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0221",
+        id: "mma_sp_m16n8k128_s32_u4",
+        abi_id: "i0221",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19950",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0222",
+        id: "mma_sp_m16n8k128_s32_u4_s4",
+        abi_id: "i0222",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19946",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0223",
+        id: "mma_sp_m16n8k128_s32_s4_satfinite",
+        abi_id: "i0223",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20007",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0224",
+        id: "mma_sp_m16n8k128_s32_s4_u4_satfinite",
+        abi_id: "i0224",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20010",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0225",
+        id: "mma_sp_m16n8k128_s32_u4_satfinite",
+        abi_id: "i0225",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20016",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0226",
+        id: "mma_sp_m16n8k128_s32_u4_s4_satfinite",
+        abi_id: "i0226",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                80,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20013",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0227",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32",
+        abi_id: "i0227",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20464",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0228",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32",
+        abi_id: "i0228",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20456",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0229",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32",
+        abi_id: "i0229",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20448",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0230",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32",
+        abi_id: "i0230",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20432",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0231",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32",
+        abi_id: "i0231",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20440",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0232",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32",
+        abi_id: "i0232",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20423",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0233",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32",
+        abi_id: "i0233",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20415",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0234",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32",
+        abi_id: "i0234",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20407",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0235",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32",
+        abi_id: "i0235",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20391",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0236",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32",
+        abi_id: "i0236",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20399",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0237",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32",
+        abi_id: "i0237",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20382",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0238",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32",
+        abi_id: "i0238",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20374",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0239",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32",
+        abi_id: "i0239",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20366",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0240",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32",
+        abi_id: "i0240",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20350",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0241",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32",
+        abi_id: "i0241",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20358",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0242",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32",
+        abi_id: "i0242",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20300",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0243",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32",
+        abi_id: "i0243",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20291",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0244",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32",
+        abi_id: "i0244",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20282",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0245",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32",
+        abi_id: "i0245",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20264",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0246",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32",
+        abi_id: "i0246",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20273",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0247",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32",
+        abi_id: "i0247",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20341",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0248",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32",
+        abi_id: "i0248",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20333",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0249",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32",
+        abi_id: "i0249",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20325",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0250",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32",
+        abi_id: "i0250",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20309",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0251",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32",
+        abi_id: "i0251",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20317",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg13>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg13,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0525",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16",
+        abi_id: "i0525",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20460",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0526",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16",
+        abi_id: "i0526",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20452",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0527",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16",
+        abi_id: "i0527",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20444",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0528",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16",
+        abi_id: "i0528",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20428",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0529",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16",
+        abi_id: "i0529",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20436",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0530",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16",
+        abi_id: "i0530",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20419",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0531",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16",
+        abi_id: "i0531",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20411",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0532",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16",
+        abi_id: "i0532",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20403",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0533",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16",
+        abi_id: "i0533",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20387",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0534",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16",
+        abi_id: "i0534",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20395",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0535",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16",
+        abi_id: "i0535",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20378",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0536",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16",
+        abi_id: "i0536",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20370",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0537",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16",
+        abi_id: "i0537",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20362",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0538",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16",
+        abi_id: "i0538",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20346",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0539",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16",
+        abi_id: "i0539",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20354",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0540",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16",
+        abi_id: "i0540",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20296",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0541",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16",
+        abi_id: "i0541",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20287",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0542",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16",
+        abi_id: "i0542",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20278",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0543",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16",
+        abi_id: "i0543",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20258",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0544",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16",
+        abi_id: "i0544",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20269",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0545",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16",
+        abi_id: "i0545",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20337",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0546",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16",
+        abi_id: "i0546",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20329",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0547",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16",
+        abi_id: "i0547",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20321",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0548",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16",
+        abi_id: "i0548",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20305",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0549",
+        id: "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16",
+        abi_id: "i0549",
+        dialect_op: "nvvm.sparse_mma",
+        variant: GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20313",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg11>",
+                "IntrNoCallback",
+                "IntrNoMem",
+                "Range<arg11,0,1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs
new file mode 100644
index 0000000000..cc2ee26a18
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs
@@ -0,0 +1,1676 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `sreg` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicRange, GeneratedIntrinsicTarget,
+    GeneratedIntrinsicVariant, GeneratedLlvmFacts, GeneratedPtxVersion,
+    GeneratedSelectionAlternative, GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0001",
+        id: "thread_idx_x",
+        abi_id: "i0001",
+        dialect_op: "nvvm.read_ptx_sreg_tid_x",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_TID_x",
+            asm: "mov.u32 \t$d, %tid.x;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,1024>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "1024",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0002",
+        id: "block_idx_x",
+        abi_id: "i0002",
+        dialect_op: "nvvm.read_ptx_sreg_ctaid_x",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CTAID_x",
+            asm: "mov.u32 \t$d, %ctaid.x;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,2147483647>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "2147483647",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0003",
+        id: "block_dim_x",
+        abi_id: "i0003",
+        dialect_op: "nvvm.read_ptx_sreg_ntid_x",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NTID_x",
+            asm: "mov.u32 \t$d, %ntid.x;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,1025>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "1025",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0004",
+        id: "grid_dim_x",
+        abi_id: "i0004",
+        dialect_op: "nvvm.read_ptx_sreg_nctaid_x",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCTAID_x",
+            asm: "mov.u32 \t$d, %nctaid.x;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,2147483648>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "2147483648",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0005",
+        id: "thread_idx_y",
+        abi_id: "i0005",
+        dialect_op: "nvvm.read_ptx_sreg_tid_y",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_TID_y",
+            asm: "mov.u32 \t$d, %tid.y;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,1024>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "1024",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0006",
+        id: "block_idx_y",
+        abi_id: "i0006",
+        dialect_op: "nvvm.read_ptx_sreg_ctaid_y",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CTAID_y",
+            asm: "mov.u32 \t$d, %ctaid.y;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,65535>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "65535",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0007",
+        id: "block_dim_y",
+        abi_id: "i0007",
+        dialect_op: "nvvm.read_ptx_sreg_ntid_y",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NTID_y",
+            asm: "mov.u32 \t$d, %ntid.y;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,1025>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "1025",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0008",
+        id: "grid_dim_y",
+        abi_id: "i0008",
+        dialect_op: "nvvm.read_ptx_sreg_nctaid_y",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCTAID_y",
+            asm: "mov.u32 \t$d, %nctaid.y;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,65536>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "65536",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0009",
+        id: "thread_idx_z",
+        abi_id: "i0009",
+        dialect_op: "nvvm.read_ptx_sreg_tid_z",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_TID_z",
+            asm: "mov.u32 \t$d, %tid.z;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,64>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "64",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0010",
+        id: "block_idx_z",
+        abi_id: "i0010",
+        dialect_op: "nvvm.read_ptx_sreg_ctaid_z",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CTAID_z",
+            asm: "mov.u32 \t$d, %ctaid.z;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,65535>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "65535",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0011",
+        id: "block_dim_z",
+        abi_id: "i0011",
+        dialect_op: "nvvm.read_ptx_sreg_ntid_z",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NTID_z",
+            asm: "mov.u32 \t$d, %ntid.z;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,65>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "65",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0012",
+        id: "grid_dim_z",
+        abi_id: "i0012",
+        dialect_op: "nvvm.read_ptx_sreg_nctaid_z",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCTAID_z",
+            asm: "mov.u32 \t$d, %nctaid.z;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,65536>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "65536",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0016",
+        id: "lane_id",
+        abi_id: "i0016",
+        dialect_op: "nvvm.read_ptx_sreg_laneid",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(13),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "SREG_LANEID",
+            asm: "mov.u32 \t$d, %laneid;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,32>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "32",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0035",
+        id: "lanemask_lt",
+        abi_id: "i0035",
+        dialect_op: "nvvm.read_ptx_sreg_lanemask_lt",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_LANEMASK_LT",
+            asm: "mov.u32 \t$d, %lanemask_lt;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0036",
+        id: "lanemask_le",
+        abi_id: "i0036",
+        dialect_op: "nvvm.read_ptx_sreg_lanemask_le",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_LANEMASK_LE",
+            asm: "mov.u32 \t$d, %lanemask_le;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0037",
+        id: "lanemask_eq",
+        abi_id: "i0037",
+        dialect_op: "nvvm.read_ptx_sreg_lanemask_eq",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_LANEMASK_EQ",
+            asm: "mov.u32 \t$d, %lanemask_eq;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0038",
+        id: "lanemask_ge",
+        abi_id: "i0038",
+        dialect_op: "nvvm.read_ptx_sreg_lanemask_ge",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_LANEMASK_GE",
+            asm: "mov.u32 \t$d, %lanemask_ge;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0039",
+        id: "lanemask_gt",
+        abi_id: "i0039",
+        dialect_op: "nvvm.read_ptx_sreg_lanemask_gt",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_LANEMASK_GT",
+            asm: "mov.u32 \t$d, %lanemask_gt;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0263",
+        id: "cluster_block_idx_x",
+        abi_id: "i0263",
+        dialect_op: "nvvm.read_ptx_sreg_cluster_ctaid_x",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_CTAID_x",
+            asm: "mov.u32 \t$d, %cluster_ctaid.x;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,2147483647>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "2147483647",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0264",
+        id: "cluster_block_idx_y",
+        abi_id: "i0264",
+        dialect_op: "nvvm.read_ptx_sreg_cluster_ctaid_y",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_CTAID_y",
+            asm: "mov.u32 \t$d, %cluster_ctaid.y;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,65535>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "65535",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0265",
+        id: "cluster_block_idx_z",
+        abi_id: "i0265",
+        dialect_op: "nvvm.read_ptx_sreg_cluster_ctaid_z",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_CTAID_z",
+            asm: "mov.u32 \t$d, %cluster_ctaid.z;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,65535>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "65535",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0266",
+        id: "cluster_dim_x",
+        abi_id: "i0266",
+        dialect_op: "nvvm.read_ptx_sreg_cluster_nctaid_x",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_NCTAID_x",
+            asm: "mov.u32 \t$d, %cluster_nctaid.x;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,2147483648>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "2147483648",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0267",
+        id: "cluster_dim_y",
+        abi_id: "i0267",
+        dialect_op: "nvvm.read_ptx_sreg_cluster_nctaid_y",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_NCTAID_y",
+            asm: "mov.u32 \t$d, %cluster_nctaid.y;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,65536>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "65536",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0268",
+        id: "cluster_dim_z",
+        abi_id: "i0268",
+        dialect_op: "nvvm.read_ptx_sreg_cluster_nctaid_z",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_NCTAID_z",
+            asm: "mov.u32 \t$d, %cluster_nctaid.z;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,65536>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "65536",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0269",
+        id: "cluster_idx_x",
+        abi_id: "i0269",
+        dialect_op: "nvvm.read_ptx_sreg_clusterid_x",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTERID_x",
+            asm: "mov.u32 \t$d, %clusterid.x;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,2147483647>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "2147483647",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0270",
+        id: "cluster_idx_y",
+        abi_id: "i0270",
+        dialect_op: "nvvm.read_ptx_sreg_clusterid_y",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTERID_y",
+            asm: "mov.u32 \t$d, %clusterid.y;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,65535>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "65535",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0271",
+        id: "cluster_idx_z",
+        abi_id: "i0271",
+        dialect_op: "nvvm.read_ptx_sreg_clusterid_z",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTERID_z",
+            asm: "mov.u32 \t$d, %clusterid.z;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,0,65535>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "0",
+                upper_exclusive: "65535",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0272",
+        id: "cluster_grid_dim_x",
+        abi_id: "i0272",
+        dialect_op: "nvvm.read_ptx_sreg_nclusterid_x",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCLUSTERID_x",
+            asm: "mov.u32 \t$d, %nclusterid.x;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,2147483648>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "2147483648",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0273",
+        id: "cluster_grid_dim_y",
+        abi_id: "i0273",
+        dialect_op: "nvvm.read_ptx_sreg_nclusterid_y",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCLUSTERID_y",
+            asm: "mov.u32 \t$d, %nclusterid.y;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,65536>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "65536",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0274",
+        id: "cluster_grid_dim_z",
+        abi_id: "i0274",
+        dialect_op: "nvvm.read_ptx_sreg_nclusterid_z",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCLUSTERID_z",
+            asm: "mov.u32 \t$d, %nclusterid.z;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrNoMem",
+                "IntrSpeculatable",
+                "NoUndef<ret>",
+                "Range<ret,1,65536>",
+            ],
+            result_no_undef: true,
+            result_range: Some(GeneratedIntrinsicRange {
+                lower: "1",
+                upper_exclusive: "65536",
+            }),
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0275",
+        id: "cluster_block_rank",
+        abi_id: "i0275",
+        dialect_op: "nvvm.read_ptx_sreg_cluster_ctarank",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_CTARANK",
+            asm: "mov.u32 \t$d, %cluster_ctarank;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0276",
+        id: "cluster_block_count",
+        abi_id: "i0276",
+        dialect_op: "nvvm.read_ptx_sreg_cluster_nctarank",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_NCTARANK",
+            asm: "mov.u32 \t$d, %cluster_nctarank;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0283",
+        id: "clock",
+        abi_id: "i0283",
+        dialect_op: "nvvm.read_ptx_sreg_clock",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "SREG_CLOCK",
+            asm: "mov.u32 \t$d, %clock;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+                "IntrNoFree",
+                "IntrWillReturn",
+                "NoUndef<ret>",
+            ],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0284",
+        id: "clock64",
+        abi_id: "i0284",
+        dialect_op: "nvvm.read_ptx_sreg_clock64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "SREG_CLOCK64",
+            asm: "mov.u64 \t$d, %clock64;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+                "IntrNoFree",
+                "IntrWillReturn",
+                "NoUndef<ret>",
+            ],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0285",
+        id: "globaltimer",
+        abi_id: "i0285",
+        dialect_op: "nvvm.read_ptx_sreg_globaltimer",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(31),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(31),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "SREG_GLOBALTIMER",
+            asm: "mov.u64 \t$d, %globaltimer;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+                "IntrNoFree",
+                "IntrWillReturn",
+                "NoUndef<ret>",
+            ],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0286",
+        id: "envreg1",
+        abi_id: "i0286",
+        dialect_op: "nvvm.read_ptx_sreg_envreg1",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(21),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(21),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0287",
+        id: "envreg2",
+        abi_id: "i0287",
+        dialect_op: "nvvm.read_ptx_sreg_envreg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(21),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(21),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0288",
+        id: "smid",
+        abi_id: "i0288",
+        dialect_op: "nvvm.read_ptx_sreg_smid",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(13),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(13),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "SREG_SMID",
+            asm: "mov.u32 \t$d, %smid;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0289",
+        id: "nsmid",
+        abi_id: "i0289",
+        dialect_op: "nvvm.read_ptx_sreg_nsmid",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "SREG_NSMID",
+            asm: "mov.u32 \t$d, %nsmid;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0290",
+        id: "gridid",
+        abi_id: "i0290",
+        dialect_op: "nvvm.read_ptx_sreg_gridid",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(30),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(30),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0291",
+        id: "warpid",
+        abi_id: "i0291",
+        dialect_op: "nvvm.read_ptx_sreg_warpid",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(13),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(13),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "SREG_WARPID",
+            asm: "mov.u32 \t$d, %warpid;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0292",
+        id: "nwarpid",
+        abi_id: "i0292",
+        dialect_op: "nvvm.read_ptx_sreg_nwarpid",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "SREG_NWARPID",
+            asm: "mov.u32 \t$d, %nwarpid;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0293",
+        id: "dynamic_smem_size",
+        abi_id: "i0293",
+        dialect_op: "nvvm.read_ptx_sreg_dynamic_smem_size",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(41),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(41),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(41),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_DYNAMIC_SMEM_SIZE",
+            asm: "mov.u32 \t$d, %dynamic_smem_size;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0294",
+        id: "total_smem_size",
+        abi_id: "i0294",
+        dialect_op: "nvvm.read_ptx_sreg_total_smem_size",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(41),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(41),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(41),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_TOTAL_SMEM_SIZE",
+            asm: "mov.u32 \t$d, %total_smem_size;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"],
+            result_no_undef: true,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs
new file mode 100644
index 0000000000..840591a31a
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs
@@ -0,0 +1,203 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `stmatrix` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0301",
+        id: "stmatrix_m8n8_x2_b16",
+        abi_id: "i0301",
+        dialect_op: "nvvm.stmatrix_m8n8_x2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0302",
+        id: "stmatrix_m8n8_x2_trans_b16",
+        abi_id: "i0302",
+        dialect_op: "nvvm.stmatrix_m8n8_x2_trans",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0303",
+        id: "stmatrix_m8n8_x4_b16",
+        abi_id: "i0303",
+        dialect_op: "nvvm.stmatrix_m8n8_x4",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0304",
+        id: "stmatrix_m8n8_x4_trans_b16",
+        abi_id: "i0304",
+        dialect_op: "nvvm.stmatrix_m8n8_x4_trans",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "IntrNoCallback",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs
new file mode 100644
index 0000000000..81f42254c0
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs
@@ -0,0 +1,202 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `sync` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0034",
+        id: "sync_threads",
+        abi_id: "i0034",
+        dialect_op: "nvvm.barrier0",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "BARRIER_CTA_SYNC_ALIGNED_ALL_i",
+            asm: "bar.sync \t$i;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0298",
+        id: "threadfence_block",
+        abi_id: "i0298",
+        dialect_op: "nvvm.threadfence_block",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(14),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_MEMBAR_CTA",
+            asm: "membar.cta;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0299",
+        id: "threadfence",
+        abi_id: "i0299",
+        dialect_op: "nvvm.threadfence",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(14),
+            hardware: GeneratedHardwareTarget::All,
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_MEMBAR_GL",
+            asm: "membar.gl;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0300",
+        id: "threadfence_system",
+        abi_id: "i0300",
+        dialect_op: "nvvm.threadfence_system",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                20,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(20),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(80),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_MEMBAR_SYS",
+            asm: "membar.sys;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs
new file mode 100644
index 0000000000..e667484f33
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs
@@ -0,0 +1,2026 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `tcgen05_cp` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0578",
+        id: "tcgen05_cp_128x128b_b4x16_p64",
+        abi_id: "i0578",
+        dialect_op: "nvvm.tcgen05_cp_128x128b_b4x16_p64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128bb4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0579",
+        id: "tcgen05_cp_128x128b_b4x16_p64_cg2",
+        abi_id: "i0579",
+        dialect_op: "nvvm.tcgen05_cp_128x128b_b4x16_p64_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128bb4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0580",
+        id: "tcgen05_cp_128x128b_b6x16_p32",
+        abi_id: "i0580",
+        dialect_op: "nvvm.tcgen05_cp_128x128b_b6x16_p32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128bb6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0581",
+        id: "tcgen05_cp_128x128b_b6x16_p32_cg2",
+        abi_id: "i0581",
+        dialect_op: "nvvm.tcgen05_cp_128x128b_b6x16_p32_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128bb6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0582",
+        id: "tcgen05_cp_128x128b",
+        abi_id: "i0582",
+        dialect_op: "nvvm.tcgen05_cp_128x128b",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128b_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x128b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0583",
+        id: "tcgen05_cp_128x128b_cg2",
+        abi_id: "i0583",
+        dialect_op: "nvvm.tcgen05_cp_128x128b_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128b_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x128b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0584",
+        id: "tcgen05_cp_128x256b_b4x16_p64",
+        abi_id: "i0584",
+        dialect_op: "nvvm.tcgen05_cp_128x256b_b4x16_p64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256bb4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0585",
+        id: "tcgen05_cp_128x256b_b4x16_p64_cg2",
+        abi_id: "i0585",
+        dialect_op: "nvvm.tcgen05_cp_128x256b_b4x16_p64_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256bb4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0586",
+        id: "tcgen05_cp_128x256b_b6x16_p32",
+        abi_id: "i0586",
+        dialect_op: "nvvm.tcgen05_cp_128x256b_b6x16_p32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256bb6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0587",
+        id: "tcgen05_cp_128x256b_b6x16_p32_cg2",
+        abi_id: "i0587",
+        dialect_op: "nvvm.tcgen05_cp_128x256b_b6x16_p32_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256bb6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0588",
+        id: "tcgen05_cp_32x128b_warpx4_b4x16_p64",
+        abi_id: "i0588",
+        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4_b4x16_p64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128b4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0589",
+        id: "tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2",
+        abi_id: "i0589",
+        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128b4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0590",
+        id: "tcgen05_cp_32x128b_warpx4_b6x16_p32",
+        abi_id: "i0590",
+        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4_b6x16_p32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128b6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0591",
+        id: "tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2",
+        abi_id: "i0591",
+        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128b6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0592",
+        id: "tcgen05_cp_32x128b_warpx4",
+        abi_id: "i0592",
+        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128_cg1",
+            asm: "tcgen05.cp.cta_group::1.32x128b.warpx4 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0593",
+        id: "tcgen05_cp_32x128b_warpx4_cg2",
+        abi_id: "i0593",
+        dialect_op: "nvvm.tcgen05_cp_32x128b_warpx4_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128_cg2",
+            asm: "tcgen05.cp.cta_group::2.32x128b.warpx4 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0594",
+        id: "tcgen05_cp_4x256b_b4x16_p64",
+        abi_id: "i0594",
+        dialect_op: "nvvm.tcgen05_cp_4x256b_b4x16_p64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256bb4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0595",
+        id: "tcgen05_cp_4x256b_b4x16_p64_cg2",
+        abi_id: "i0595",
+        dialect_op: "nvvm.tcgen05_cp_4x256b_b4x16_p64_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256bb4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0596",
+        id: "tcgen05_cp_4x256b_b6x16_p32",
+        abi_id: "i0596",
+        dialect_op: "nvvm.tcgen05_cp_4x256b_b6x16_p32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256bb6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0597",
+        id: "tcgen05_cp_4x256b_b6x16_p32_cg2",
+        abi_id: "i0597",
+        dialect_op: "nvvm.tcgen05_cp_4x256b_b6x16_p32_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256bb6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0598",
+        id: "tcgen05_cp_4x256b",
+        abi_id: "i0598",
+        dialect_op: "nvvm.tcgen05_cp_4x256b",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256b_cg1",
+            asm: "tcgen05.cp.cta_group::1.4x256b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0599",
+        id: "tcgen05_cp_4x256b_cg2",
+        abi_id: "i0599",
+        dialect_op: "nvvm.tcgen05_cp_4x256b_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256b_cg2",
+            asm: "tcgen05.cp.cta_group::2.4x256b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0600",
+        id: "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64",
+        abi_id: "i0600",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2b4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0601",
+        id: "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2",
+        abi_id: "i0601",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2b4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0602",
+        id: "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32",
+        abi_id: "i0602",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2b6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0603",
+        id: "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2",
+        abi_id: "i0603",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2b6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0604",
+        id: "tcgen05_cp_64x128b_warpx2_01_23",
+        abi_id: "i0604",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0605",
+        id: "tcgen05_cp_64x128b_warpx2_01_23_cg2",
+        abi_id: "i0605",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_01_23_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0606",
+        id: "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64",
+        abi_id: "i0606",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1b4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0607",
+        id: "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2",
+        abi_id: "i0607",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1b4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0608",
+        id: "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32",
+        abi_id: "i0608",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1b6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0609",
+        id: "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2",
+        abi_id: "i0609",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1b6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0610",
+        id: "tcgen05_cp_64x128b_warpx2_02_13",
+        abi_id: "i0610",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0611",
+        id: "tcgen05_cp_64x128b_warpx2_02_13_cg2",
+        abi_id: "i0611",
+        dialect_op: "nvvm.tcgen05_cp_64x128b_warpx2_02_13_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs
new file mode 100644
index 0000000000..d4c917bc18
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs
@@ -0,0 +1,3883 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `tcgen05_ld` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0612",
+        id: "tcgen05_ld_16x64b_x1_raw",
+        abi_id: "i0612",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x1_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0613",
+        id: "tcgen05_ld_16x64b_x1_pack16",
+        abi_id: "i0613",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x1_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0614",
+        id: "tcgen05_ld_16x64b_x2_raw",
+        abi_id: "i0614",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x2_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0615",
+        id: "tcgen05_ld_16x64b_x2_pack16",
+        abi_id: "i0615",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x2_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0616",
+        id: "tcgen05_ld_16x64b_x4_raw",
+        abi_id: "i0616",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x4_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0617",
+        id: "tcgen05_ld_16x64b_x4_pack16",
+        abi_id: "i0617",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x4_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0618",
+        id: "tcgen05_ld_16x64b_x8_raw",
+        abi_id: "i0618",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x8_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0619",
+        id: "tcgen05_ld_16x64b_x8_pack16",
+        abi_id: "i0619",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x8_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0620",
+        id: "tcgen05_ld_16x64b_x16_raw",
+        abi_id: "i0620",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x16_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0621",
+        id: "tcgen05_ld_16x64b_x16_pack16",
+        abi_id: "i0621",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x16_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0622",
+        id: "tcgen05_ld_16x64b_x32_raw",
+        abi_id: "i0622",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x32_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0623",
+        id: "tcgen05_ld_16x64b_x32_pack16",
+        abi_id: "i0623",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x32_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0624",
+        id: "tcgen05_ld_16x64b_x64_raw",
+        abi_id: "i0624",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x64_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0625",
+        id: "tcgen05_ld_16x64b_x64_pack16",
+        abi_id: "i0625",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x64_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0626",
+        id: "tcgen05_ld_16x64b_x128_raw",
+        abi_id: "i0626",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x128_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0627",
+        id: "tcgen05_ld_16x64b_x128_pack16",
+        abi_id: "i0627",
+        dialect_op: "nvvm.tcgen05_ld_16x64b_x128_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0628",
+        id: "tcgen05_ld_16x128b_x1_raw",
+        abi_id: "i0628",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x1_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0629",
+        id: "tcgen05_ld_16x128b_x1_pack16",
+        abi_id: "i0629",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x1_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0630",
+        id: "tcgen05_ld_16x128b_x2_raw",
+        abi_id: "i0630",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x2_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0631",
+        id: "tcgen05_ld_16x128b_x2_pack16",
+        abi_id: "i0631",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x2_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0632",
+        id: "tcgen05_ld_16x128b_x4_raw",
+        abi_id: "i0632",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x4_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0633",
+        id: "tcgen05_ld_16x128b_x4_pack16",
+        abi_id: "i0633",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x4_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0634",
+        id: "tcgen05_ld_16x128b_x8_raw",
+        abi_id: "i0634",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x8_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0635",
+        id: "tcgen05_ld_16x128b_x8_pack16",
+        abi_id: "i0635",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x8_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0636",
+        id: "tcgen05_ld_16x128b_x16_raw",
+        abi_id: "i0636",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x16_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0637",
+        id: "tcgen05_ld_16x128b_x16_pack16",
+        abi_id: "i0637",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x16_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0638",
+        id: "tcgen05_ld_16x128b_x32_raw",
+        abi_id: "i0638",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x32_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0639",
+        id: "tcgen05_ld_16x128b_x32_pack16",
+        abi_id: "i0639",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x32_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0640",
+        id: "tcgen05_ld_16x128b_x64_raw",
+        abi_id: "i0640",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x64_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0641",
+        id: "tcgen05_ld_16x128b_x64_pack16",
+        abi_id: "i0641",
+        dialect_op: "nvvm.tcgen05_ld_16x128b_x64_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0642",
+        id: "tcgen05_ld_16x256b_x1_raw",
+        abi_id: "i0642",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x1_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0643",
+        id: "tcgen05_ld_16x256b_x1_pack16",
+        abi_id: "i0643",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x1_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0644",
+        id: "tcgen05_ld_16x256b_x2_raw",
+        abi_id: "i0644",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x2_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0645",
+        id: "tcgen05_ld_16x256b_x2_pack16",
+        abi_id: "i0645",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x2_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0646",
+        id: "tcgen05_ld_16x256b_x4_raw",
+        abi_id: "i0646",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x4_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0647",
+        id: "tcgen05_ld_16x256b_x4_pack16",
+        abi_id: "i0647",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x4_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0648",
+        id: "tcgen05_ld_16x256b_x8_raw",
+        abi_id: "i0648",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x8_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0649",
+        id: "tcgen05_ld_16x256b_x8_pack16",
+        abi_id: "i0649",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x8_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0650",
+        id: "tcgen05_ld_16x256b_x16_raw",
+        abi_id: "i0650",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x16_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0651",
+        id: "tcgen05_ld_16x256b_x16_pack16",
+        abi_id: "i0651",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x16_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0652",
+        id: "tcgen05_ld_16x256b_x32_raw",
+        abi_id: "i0652",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x32_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0653",
+        id: "tcgen05_ld_16x256b_x32_pack16",
+        abi_id: "i0653",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x32_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0654",
+        id: "tcgen05_ld_32x32b_x1_raw",
+        abi_id: "i0654",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x1_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0655",
+        id: "tcgen05_ld_32x32b_x1_pack16",
+        abi_id: "i0655",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x1_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0656",
+        id: "tcgen05_ld_32x32b_x2_raw",
+        abi_id: "i0656",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x2_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0657",
+        id: "tcgen05_ld_32x32b_x2_pack16",
+        abi_id: "i0657",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x2_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0658",
+        id: "tcgen05_ld_32x32b_x4_raw",
+        abi_id: "i0658",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x4_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0659",
+        id: "tcgen05_ld_32x32b_x4_pack16",
+        abi_id: "i0659",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x4_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0660",
+        id: "tcgen05_ld_32x32b_x8_raw",
+        abi_id: "i0660",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x8_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0661",
+        id: "tcgen05_ld_32x32b_x8_pack16",
+        abi_id: "i0661",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x8_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0662",
+        id: "tcgen05_ld_32x32b_x16_raw",
+        abi_id: "i0662",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x16_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0663",
+        id: "tcgen05_ld_32x32b_x16_pack16",
+        abi_id: "i0663",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x16_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0664",
+        id: "tcgen05_ld_32x32b_x32_raw",
+        abi_id: "i0664",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x32_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0665",
+        id: "tcgen05_ld_32x32b_x32_pack16",
+        abi_id: "i0665",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x32_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0666",
+        id: "tcgen05_ld_32x32b_x64_raw",
+        abi_id: "i0666",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x64_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0667",
+        id: "tcgen05_ld_32x32b_x64_pack16",
+        abi_id: "i0667",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x64_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0668",
+        id: "tcgen05_ld_32x32b_x128_raw",
+        abi_id: "i0668",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x128_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0669",
+        id: "tcgen05_ld_32x32b_x128_pack16",
+        abi_id: "i0669",
+        dialect_op: "nvvm.tcgen05_ld_32x32b_x128_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0728",
+        id: "tcgen05_ld_16x32bx2_x1_raw",
+        abi_id: "i0728",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x1_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0729",
+        id: "tcgen05_ld_16x32bx2_x1_pack16",
+        abi_id: "i0729",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x1_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0730",
+        id: "tcgen05_ld_16x32bx2_x2_raw",
+        abi_id: "i0730",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x2_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0731",
+        id: "tcgen05_ld_16x32bx2_x2_pack16",
+        abi_id: "i0731",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x2_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0732",
+        id: "tcgen05_ld_16x32bx2_x4_raw",
+        abi_id: "i0732",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x4_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0733",
+        id: "tcgen05_ld_16x32bx2_x4_pack16",
+        abi_id: "i0733",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x4_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0734",
+        id: "tcgen05_ld_16x32bx2_x8_raw",
+        abi_id: "i0734",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x8_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0735",
+        id: "tcgen05_ld_16x32bx2_x8_pack16",
+        abi_id: "i0735",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x8_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0736",
+        id: "tcgen05_ld_16x32bx2_x16_raw",
+        abi_id: "i0736",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x16_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0737",
+        id: "tcgen05_ld_16x32bx2_x16_pack16",
+        abi_id: "i0737",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x16_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0738",
+        id: "tcgen05_ld_16x32bx2_x32_raw",
+        abi_id: "i0738",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x32_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0739",
+        id: "tcgen05_ld_16x32bx2_x32_pack16",
+        abi_id: "i0739",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x32_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0740",
+        id: "tcgen05_ld_16x32bx2_x64_raw",
+        abi_id: "i0740",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x64_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0741",
+        id: "tcgen05_ld_16x32bx2_x64_pack16",
+        abi_id: "i0741",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x64_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0742",
+        id: "tcgen05_ld_16x32bx2_x128_raw",
+        abi_id: "i0742",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x128_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0743",
+        id: "tcgen05_ld_16x32bx2_x128_pack16",
+        abi_id: "i0743",
+        dialect_op: "nvvm.tcgen05_ld_16x32bx2_x128_pack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs
new file mode 100644
index 0000000000..33e82ddf80
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs
@@ -0,0 +1,5314 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `tcgen05_mma` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetAlternative, GeneratedTargetContract,
+    GeneratedTargetRequirement, GeneratedTargetSelectorBinding, GeneratedTcgen05MmaForm,
+    GeneratedTcgen05MmaTargetSelector,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0763",
+        id: "tcgen05_mma_shared",
+        abi_id: "i0763",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22502",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22504",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22506",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22508",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22510",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22512",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22514",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22516",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22518",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22520",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22522",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22524",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22526",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22528",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22530",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22532",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22534",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22535",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22536",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22537",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22538",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22539",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22540",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22541",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22542",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22543",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22544",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22545",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22546",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22547",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22548",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22549",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,1,3>",
+                "Range<arg7,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0764",
+        id: "tcgen05_mma_tensor",
+        abi_id: "i0764",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Tensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22406",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22410",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22414",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22418",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22422",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22426",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22430",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22434",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22438",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22442",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22446",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22450",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22454",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22458",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22462",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22466",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22470",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22472",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22474",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22476",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22478",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22480",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22482",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22484",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22486",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22488",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22490",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22492",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22494",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22496",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22498",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22500",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ArgInfo<arg5>",
+                "ArgInfo<arg6>",
+                "ArgInfo<arg7>",
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,1,3>",
+                "Range<arg7,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0765",
+        id: "tcgen05_mma_tensor_ashift",
+        abi_id: "i0765",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::TensorAshift,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22407",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22411",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22423",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22427",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22439",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22443",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22455",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22459",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22471",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22473",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22479",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22481",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22487",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22489",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22495",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22497",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,1,3>",
+                "Range<arg7,0,2>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0766",
+        id: "tcgen05_mma_sp_shared",
+        abi_id: "i0766",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::SpShared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22646",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22648",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22650",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22652",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22654",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22656",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22658",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22660",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22662",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22664",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22666",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22668",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22670",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22672",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22674",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22676",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22678",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22679",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22680",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22681",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22682",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22683",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22684",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22685",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22686",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22687",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22688",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22689",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22690",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22691",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22692",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22693",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "IntrArgMemOnly",
+                "Range<arg6,0,4>",
+                "Range<arg7,1,3>",
+                "Range<arg8,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0767",
+        id: "tcgen05_mma_sp_tensor",
+        abi_id: "i0767",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::SpTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22550",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22554",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22558",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22562",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22566",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22570",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22574",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22578",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22582",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22586",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22590",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22594",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22598",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22602",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22606",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22610",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22614",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22616",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22618",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22620",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22622",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22624",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22626",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22628",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22630",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22632",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22634",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22636",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22638",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22640",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22642",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22644",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "IntrArgMemOnly",
+                "Range<arg6,0,4>",
+                "Range<arg7,1,3>",
+                "Range<arg8,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0768",
+        id: "tcgen05_mma_sp_tensor_ashift",
+        abi_id: "i0768",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::SpTensorAshift,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22551",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22555",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22567",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22571",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22583",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22587",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22599",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22603",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22615",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22617",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22623",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22625",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22631",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22633",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22639",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22641",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "IntrArgMemOnly",
+                "Range<arg6,0,4>",
+                "Range<arg7,1,3>",
+                "Range<arg8,0,2>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1011",
+        id: "tcgen05_mma_e4m3",
+        abi_id: "i1011",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22534",
+            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,1,3>",
+                "Range<arg7,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1012",
+        id: "tcgen05_mma_e5m2",
+        abi_id: "i1012",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22534",
+            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,1,3>",
+                "Range<arg7,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1013",
+        id: "tcgen05_mma_e2m3",
+        abi_id: "i1013",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22534",
+            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,1,3>",
+                "Range<arg7,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1014",
+        id: "tcgen05_mma_e3m2",
+        abi_id: "i1014",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22534",
+            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,1,3>",
+                "Range<arg7,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i1015",
+        id: "tcgen05_mma_e2m1",
+        abi_id: "i1015",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22534",
+            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,1,3>",
+                "Range<arg7,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs
new file mode 100644
index 0000000000..686787fd06
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs
@@ -0,0 +1,9484 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `tcgen05_mma_ws` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetAlternative, GeneratedTargetContract,
+    GeneratedTargetRequirement, GeneratedTargetSelectorBinding, GeneratedTcgen05MmaForm,
+    GeneratedTcgen05MmaTargetSelector,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0769",
+        id: "tcgen05_mma_ws_shared",
+        abi_id: "i0769",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsShared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23232",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23234",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23236",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23238",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23240",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23242",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23244",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23246",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23248",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23250",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23252",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23254",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23256",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23258",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23260",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23262",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23264",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23266",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23268",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23270",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23272",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23274",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23276",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23278",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23280",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23282",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23284",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23286",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23288",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23290",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23292",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23294",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23296",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23298",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23300",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23302",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23304",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23306",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23308",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23310",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23312",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23314",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23316",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23318",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23320",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23322",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23324",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23326",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23328",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23330",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23332",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23334",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23336",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23338",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23340",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23342",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23344",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23346",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23348",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23350",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23352",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23354",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23356",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23358",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0770",
+        id: "tcgen05_mma_ws_shared_zero_col_mask",
+        abi_id: "i0770",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsSharedZeroColMask,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23233",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23235",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23237",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23239",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23241",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23243",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23245",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23247",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23249",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23251",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23253",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23255",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23257",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23259",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23261",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23263",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23265",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23267",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23269",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23271",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23273",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23275",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23277",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23279",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23281",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23283",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23285",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23287",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23289",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23291",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23293",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23295",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23297",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23299",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23301",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23303",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23305",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23307",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23309",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23311",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23313",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23315",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23317",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23319",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23321",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23323",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23325",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23327",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23329",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23331",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23333",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23335",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23337",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23339",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23341",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23343",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23345",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23347",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23349",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23351",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23353",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23355",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23357",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23359",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "IntrArgMemOnly",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "Range<arg8,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0771",
+        id: "tcgen05_mma_ws_sp_shared",
+        abi_id: "i0771",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsSpShared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23488",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23490",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23492",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23494",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23496",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23498",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23500",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23502",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23504",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23506",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23508",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23510",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23512",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23514",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23516",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23518",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23520",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23522",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23524",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23526",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23528",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23530",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23532",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23534",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23536",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23538",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23540",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23542",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23544",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23546",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23548",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23550",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23552",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23554",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23556",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23558",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23560",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23562",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23564",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23566",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23568",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23570",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23572",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23574",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23576",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23578",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23580",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23582",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23584",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23586",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23588",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23590",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23592",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23594",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23596",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23598",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23600",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23602",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23604",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23606",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23608",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23610",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23612",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23614",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "IntrArgMemOnly",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "Range<arg8,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0772",
+        id: "tcgen05_mma_ws_sp_shared_zero_col_mask",
+        abi_id: "i0772",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsSpSharedZeroColMask,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23489",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23491",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23493",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23495",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23497",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23499",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23501",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23503",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23505",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23507",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23509",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23511",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23513",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23515",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23517",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23519",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23521",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23523",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23525",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23527",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23529",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23531",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23533",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23535",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23537",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23539",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23541",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23543",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23545",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23547",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23549",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23551",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23553",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23555",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23557",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23559",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23561",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23563",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23565",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23567",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23569",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23571",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23573",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23575",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23577",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23579",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23581",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23583",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23585",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23587",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23589",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23591",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23593",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23595",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23597",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23599",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23601",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23603",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23605",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23607",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23609",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23611",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23613",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23615",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "ImmArg<arg9>",
+                "IntrArgMemOnly",
+                "Range<arg7,0,4>",
+                "Range<arg8,0,4>",
+                "Range<arg9,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0773",
+        id: "tcgen05_mma_ws_sp_tensor",
+        abi_id: "i0773",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsSpTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23616",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23618",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23620",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23622",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23624",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23626",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23628",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23630",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23632",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23634",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23636",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23638",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23640",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23642",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23644",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23646",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23648",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23650",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23652",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23654",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23656",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23658",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23660",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23662",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23664",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23666",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23668",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23670",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23672",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23674",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23676",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23678",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23680",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23682",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23684",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23686",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23688",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23690",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23692",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23694",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23696",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23698",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23700",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23702",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23704",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23706",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23708",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23710",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23712",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23714",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23716",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23718",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23720",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23722",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23724",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23726",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23728",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23730",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23732",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23734",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23736",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23738",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23740",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23742",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "IntrArgMemOnly",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "Range<arg8,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0774",
+        id: "tcgen05_mma_ws_sp_tensor_zero_col_mask",
+        abi_id: "i0774",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsSpTensorZeroColMask,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23617",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23619",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23621",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23623",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23625",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23627",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23629",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23631",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23633",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23635",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23637",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23639",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23641",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23643",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23645",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23647",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23649",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23651",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23653",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23655",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23657",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23659",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23661",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23663",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23665",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23667",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23669",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23671",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23673",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23675",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23677",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23679",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23681",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23683",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23685",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23687",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23689",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23691",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23693",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23695",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23697",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23699",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23701",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23703",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23705",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23707",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23709",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23711",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23713",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23715",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23717",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23719",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23721",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23723",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23725",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23727",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23729",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23731",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23733",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23735",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23737",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23739",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23741",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23743",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "ImmArg<arg9>",
+                "IntrArgMemOnly",
+                "Range<arg7,0,4>",
+                "Range<arg8,0,4>",
+                "Range<arg9,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0775",
+        id: "tcgen05_mma_ws_tensor",
+        abi_id: "i0775",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23360",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23362",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23364",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23366",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23368",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23370",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23372",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23374",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23376",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23378",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23380",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23382",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23384",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23386",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23388",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23390",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23392",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23394",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23396",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23398",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23400",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23402",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23404",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23406",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23408",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23410",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23412",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23414",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23416",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23418",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23420",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23422",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23424",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23426",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23428",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23430",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23432",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23434",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23436",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23438",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23440",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23442",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23444",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23446",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23448",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23450",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23452",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23454",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23456",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23458",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23460",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23462",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23464",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23466",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23468",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23470",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23472",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23474",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23476",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23478",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23480",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23482",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23484",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23486",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0776",
+        id: "tcgen05_mma_ws_tensor_zero_col_mask",
+        abi_id: "i0776",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensorZeroColMask,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f16",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "i8",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                ],
+                            },
+                            GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "tf32",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            },
+                        ],
+                    },
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23361",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23363",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23365",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23367",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23369",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23371",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23373",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23375",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23377",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23379",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23381",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23383",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23385",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23387",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23389",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23391",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23393",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23395",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23397",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23399",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23401",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23403",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23405",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23407",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23409",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23411",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23413",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23415",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23417",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23419",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23421",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23423",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23425",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23427",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23429",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23431",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23433",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23435",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23437",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23439",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23441",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23443",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23445",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23447",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23449",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23451",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23453",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23455",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23457",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23459",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23461",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23463",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23465",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23467",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23469",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23471",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23473",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23475",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23477",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23479",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23481",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23483",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23485",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23487",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "IntrArgMemOnly",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "Range<arg8,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0777",
+        id: "tcgen05_mma_ws_e4m3",
+        abi_id: "i0777",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_23424",
+            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0778",
+        id: "tcgen05_mma_ws_e5m2",
+        abi_id: "i0778",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_23424",
+            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0779",
+        id: "tcgen05_mma_ws_e2m3",
+        abi_id: "i0779",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_23424",
+            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0780",
+        id: "tcgen05_mma_ws_e3m2",
+        abi_id: "i0780",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_23424",
+            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0781",
+        id: "tcgen05_mma_ws_e2m1",
+        abi_id: "i0781",
+        dialect_op: "nvvm.tcgen05_mma",
+        variant: GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            },
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::TargetMatrix {
+                        contracts: &[GeneratedTargetContract {
+                            selectors: &[GeneratedTargetSelectorBinding {
+                                name: "kind",
+                                value: "f8f6f4",
+                            }],
+                            alternatives: &[
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                                },
+                                GeneratedTargetAlternative {
+                                    minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                    hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                },
+                            ],
+                        }],
+                    },
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "anonymous_23424",
+            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs
new file mode 100644
index 0000000000..c7ebd4f922
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs
@@ -0,0 +1,1529 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `tcgen05_other` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0343",
+        id: "tcgen05_alloc",
+        abi_id: "i0343",
+        dialect_op: "nvvm.tcgen05_alloc",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_ALLOC_S64_CG1",
+            asm: "tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 \t[$dst], $ncols;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0344",
+        id: "tcgen05_dealloc",
+        abi_id: "i0344",
+        dialect_op: "nvvm.tcgen05_dealloc",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_DEALLOC_CG1",
+            asm: "tcgen05.dealloc.cta_group::1.sync.aligned.b32 \t$tmem_addr, $ncols;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0345",
+        id: "tcgen05_relinquish_alloc_permit",
+        abi_id: "i0345",
+        dialect_op: "nvvm.tcgen05_relinquish_alloc_permit",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_RELINQ_CG1",
+            asm: "tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrInaccessibleMemOnly"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0346",
+        id: "tcgen05_fence_before_thread_sync",
+        abi_id: "i0346",
+        dialect_op: "nvvm.tcgen05_fence_before_thread_sync",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "tcgen05_fence_before_thread_sync",
+            asm: "tcgen05.fence::before_thread_sync;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrHasSideEffects", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0347",
+        id: "tcgen05_fence_after_thread_sync",
+        abi_id: "i0347",
+        dialect_op: "nvvm.tcgen05_fence_after_thread_sync",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "tcgen05_fence_after_thread_sync",
+            asm: "tcgen05.fence::after_thread_sync;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrHasSideEffects", "IntrNoMem"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0348",
+        id: "tcgen05_commit",
+        abi_id: "i0348",
+        dialect_op: "nvvm.tcgen05_commit",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0349",
+        id: "tcgen05_commit_shared_cluster",
+        abi_id: "i0349",
+        dialect_op: "nvvm.tcgen05_commit_shared_cluster",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_COMMIT_S64_CG1",
+            asm: "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0350",
+        id: "tcgen05_mma_ws_f16",
+        abi_id: "i0350",
+        dialect_op: "nvvm.tcgen05_mma_ws_f16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0351",
+        id: "tcgen05_mma_f16",
+        abi_id: "i0351",
+        dialect_op: "nvvm.tcgen05_mma_f16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0352",
+        id: "tcgen05_mma_ws_bf16",
+        abi_id: "i0352",
+        dialect_op: "nvvm.tcgen05_mma_ws_bf16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0353",
+        id: "tcgen05_mma_ws_tf32",
+        abi_id: "i0353",
+        dialect_op: "nvvm.tcgen05_mma_ws_tf32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg5,0,4>",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "ReadOnly<arg1>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0354",
+        id: "tcgen05_cp_smem_to_tmem",
+        abi_id: "i0354",
+        dialect_op: "nvvm.tcgen05_cp_smem_to_tmem",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256b_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x256b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0355",
+        id: "tcgen05_ld_16x256b_x8_pure",
+        abi_id: "i0355",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_x8_pure",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0356",
+        id: "tcgen05_ld_16x256b_pure",
+        abi_id: "i0356",
+        dialect_op: "nvvm.tcgen05_ld_16x256b_pure",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0357",
+        id: "tcgen05_load_wait",
+        abi_id: "i0357",
+        dialect_op: "nvvm.tcgen05_load_wait",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "tcgen05_wait_ld",
+            asm: "tcgen05.wait::ld.sync.aligned;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrInaccessibleMemOnly"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0358",
+        id: "tcgen05_store_wait",
+        abi_id: "i0358",
+        dialect_op: "nvvm.tcgen05_store_wait",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "tcgen05_wait_st",
+            asm: "tcgen05.wait::st.sync.aligned;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrInaccessibleMemOnly"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0359",
+        id: "tcgen05_alloc_cg2",
+        abi_id: "i0359",
+        dialect_op: "nvvm.tcgen05_alloc_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_ALLOC_S64_CG2",
+            asm: "tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 \t[$dst], $ncols;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0360",
+        id: "tcgen05_dealloc_cg2",
+        abi_id: "i0360",
+        dialect_op: "nvvm.tcgen05_dealloc_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_DEALLOC_CG2",
+            asm: "tcgen05.dealloc.cta_group::2.sync.aligned.b32 \t$tmem_addr, $ncols;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0361",
+        id: "tcgen05_relinquish_alloc_permit_cg2",
+        abi_id: "i0361",
+        dialect_op: "nvvm.tcgen05_relinquish_alloc_permit_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_RELINQ_CG2",
+            asm: "tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent", "IntrInaccessibleMemOnly"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0362",
+        id: "tcgen05_mma_f16_cg2",
+        abi_id: "i0362",
+        dialect_op: "nvvm.tcgen05_mma_f16_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "IntrArgMemOnly",
+                "Range<arg6,0,4>",
+                "Range<arg7,0,4>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0363",
+        id: "tcgen05_commit_cg2",
+        abi_id: "i0363",
+        dialect_op: "nvvm.tcgen05_commit_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0364",
+        id: "tcgen05_commit_shared_cluster_cg2",
+        abi_id: "i0364",
+        dialect_op: "nvvm.tcgen05_commit_shared_cluster_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_COMMIT_S64_CG2",
+            asm: "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0365",
+        id: "tcgen05_commit_multicast_cg2",
+        abi_id: "i0365",
+        dialect_op: "nvvm.tcgen05_commit_multicast_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_COMMIT_S64_CG2_MC",
+            asm: "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0366",
+        id: "tcgen05_cp_smem_to_tmem_cg2",
+        abi_id: "i0366",
+        dialect_op: "nvvm.tcgen05_cp_smem_to_tmem_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256b_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x256b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0760",
+        id: "tcgen05_commit_multicast",
+        abi_id: "i0760",
+        dialect_op: "nvvm.tcgen05_commit_multicast",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_COMMIT_S64_CG1_MC",
+            asm: "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOrArgMemOnly",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0761",
+        id: "tcgen05_shift_down",
+        abi_id: "i0761",
+        dialect_op: "nvvm.tcgen05_shift_down",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_SHIFT_CG1",
+            asm: "tcgen05.shift.cta_group::1.down \t[$tmem_addr];",
+            predicates: &["Subtarget->hasTcgen05ShiftSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0762",
+        id: "tcgen05_shift_down_cg2",
+        abi_id: "i0762",
+        dialect_op: "nvvm.tcgen05_shift_down_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_SHIFT_CG2",
+            asm: "tcgen05.shift.cta_group::2.down \t[$tmem_addr];",
+            predicates: &["Subtarget->hasTcgen05ShiftSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs
new file mode 100644
index 0000000000..fe4e38e913
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs
@@ -0,0 +1,3883 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `tcgen05_st` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0670",
+        id: "tcgen05_st_16x64b_x1_raw",
+        abi_id: "i0670",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x1_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0671",
+        id: "tcgen05_st_16x64b_x1_unpack16",
+        abi_id: "i0671",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x1_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0672",
+        id: "tcgen05_st_16x64b_x2_raw",
+        abi_id: "i0672",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x2_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0673",
+        id: "tcgen05_st_16x64b_x2_unpack16",
+        abi_id: "i0673",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x2_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0674",
+        id: "tcgen05_st_16x64b_x4_raw",
+        abi_id: "i0674",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x4_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0675",
+        id: "tcgen05_st_16x64b_x4_unpack16",
+        abi_id: "i0675",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x4_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0676",
+        id: "tcgen05_st_16x64b_x8_raw",
+        abi_id: "i0676",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x8_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0677",
+        id: "tcgen05_st_16x64b_x8_unpack16",
+        abi_id: "i0677",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x8_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0678",
+        id: "tcgen05_st_16x64b_x16_raw",
+        abi_id: "i0678",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x16_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0679",
+        id: "tcgen05_st_16x64b_x16_unpack16",
+        abi_id: "i0679",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x16_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0680",
+        id: "tcgen05_st_16x64b_x32_raw",
+        abi_id: "i0680",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x32_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0681",
+        id: "tcgen05_st_16x64b_x32_unpack16",
+        abi_id: "i0681",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x32_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0682",
+        id: "tcgen05_st_16x64b_x64_raw",
+        abi_id: "i0682",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x64_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0683",
+        id: "tcgen05_st_16x64b_x64_unpack16",
+        abi_id: "i0683",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x64_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0684",
+        id: "tcgen05_st_16x64b_x128_raw",
+        abi_id: "i0684",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x128_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0685",
+        id: "tcgen05_st_16x64b_x128_unpack16",
+        abi_id: "i0685",
+        dialect_op: "nvvm.tcgen05_st_16x64b_x128_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0686",
+        id: "tcgen05_st_16x128b_x1_raw",
+        abi_id: "i0686",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x1_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0687",
+        id: "tcgen05_st_16x128b_x1_unpack16",
+        abi_id: "i0687",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x1_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0688",
+        id: "tcgen05_st_16x128b_x2_raw",
+        abi_id: "i0688",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x2_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0689",
+        id: "tcgen05_st_16x128b_x2_unpack16",
+        abi_id: "i0689",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x2_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0690",
+        id: "tcgen05_st_16x128b_x4_raw",
+        abi_id: "i0690",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x4_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0691",
+        id: "tcgen05_st_16x128b_x4_unpack16",
+        abi_id: "i0691",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x4_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0692",
+        id: "tcgen05_st_16x128b_x8_raw",
+        abi_id: "i0692",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x8_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0693",
+        id: "tcgen05_st_16x128b_x8_unpack16",
+        abi_id: "i0693",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x8_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0694",
+        id: "tcgen05_st_16x128b_x16_raw",
+        abi_id: "i0694",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x16_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0695",
+        id: "tcgen05_st_16x128b_x16_unpack16",
+        abi_id: "i0695",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x16_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0696",
+        id: "tcgen05_st_16x128b_x32_raw",
+        abi_id: "i0696",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x32_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0697",
+        id: "tcgen05_st_16x128b_x32_unpack16",
+        abi_id: "i0697",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x32_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0698",
+        id: "tcgen05_st_16x128b_x64_raw",
+        abi_id: "i0698",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x64_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0699",
+        id: "tcgen05_st_16x128b_x64_unpack16",
+        abi_id: "i0699",
+        dialect_op: "nvvm.tcgen05_st_16x128b_x64_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0700",
+        id: "tcgen05_st_16x256b_x1_raw",
+        abi_id: "i0700",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x1_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0701",
+        id: "tcgen05_st_16x256b_x1_unpack16",
+        abi_id: "i0701",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x1_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0702",
+        id: "tcgen05_st_16x256b_x2_raw",
+        abi_id: "i0702",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x2_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0703",
+        id: "tcgen05_st_16x256b_x2_unpack16",
+        abi_id: "i0703",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x2_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0704",
+        id: "tcgen05_st_16x256b_x4_raw",
+        abi_id: "i0704",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x4_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0705",
+        id: "tcgen05_st_16x256b_x4_unpack16",
+        abi_id: "i0705",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x4_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0706",
+        id: "tcgen05_st_16x256b_x8_raw",
+        abi_id: "i0706",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x8_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0707",
+        id: "tcgen05_st_16x256b_x8_unpack16",
+        abi_id: "i0707",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x8_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0708",
+        id: "tcgen05_st_16x256b_x16_raw",
+        abi_id: "i0708",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x16_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0709",
+        id: "tcgen05_st_16x256b_x16_unpack16",
+        abi_id: "i0709",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x16_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0710",
+        id: "tcgen05_st_16x256b_x32_raw",
+        abi_id: "i0710",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x32_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0711",
+        id: "tcgen05_st_16x256b_x32_unpack16",
+        abi_id: "i0711",
+        dialect_op: "nvvm.tcgen05_st_16x256b_x32_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0712",
+        id: "tcgen05_st_32x32b_x1_raw",
+        abi_id: "i0712",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x1_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0713",
+        id: "tcgen05_st_32x32b_x1_unpack16",
+        abi_id: "i0713",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x1_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0714",
+        id: "tcgen05_st_32x32b_x2_raw",
+        abi_id: "i0714",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x2_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0715",
+        id: "tcgen05_st_32x32b_x2_unpack16",
+        abi_id: "i0715",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x2_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0716",
+        id: "tcgen05_st_32x32b_x4_raw",
+        abi_id: "i0716",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x4_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0717",
+        id: "tcgen05_st_32x32b_x4_unpack16",
+        abi_id: "i0717",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x4_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0718",
+        id: "tcgen05_st_32x32b_x8_raw",
+        abi_id: "i0718",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x8_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0719",
+        id: "tcgen05_st_32x32b_x8_unpack16",
+        abi_id: "i0719",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x8_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0720",
+        id: "tcgen05_st_32x32b_x16_raw",
+        abi_id: "i0720",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x16_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0721",
+        id: "tcgen05_st_32x32b_x16_unpack16",
+        abi_id: "i0721",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x16_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0722",
+        id: "tcgen05_st_32x32b_x32_raw",
+        abi_id: "i0722",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x32_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0723",
+        id: "tcgen05_st_32x32b_x32_unpack16",
+        abi_id: "i0723",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x32_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0724",
+        id: "tcgen05_st_32x32b_x64_raw",
+        abi_id: "i0724",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x64_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0725",
+        id: "tcgen05_st_32x32b_x64_unpack16",
+        abi_id: "i0725",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x64_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0726",
+        id: "tcgen05_st_32x32b_x128_raw",
+        abi_id: "i0726",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x128_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0727",
+        id: "tcgen05_st_32x32b_x128_unpack16",
+        abi_id: "i0727",
+        dialect_op: "nvvm.tcgen05_st_32x32b_x128_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg2>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0744",
+        id: "tcgen05_st_16x32bx2_x1_raw",
+        abi_id: "i0744",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x1_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0745",
+        id: "tcgen05_st_16x32bx2_x1_unpack16",
+        abi_id: "i0745",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x1_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0746",
+        id: "tcgen05_st_16x32bx2_x2_raw",
+        abi_id: "i0746",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x2_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0747",
+        id: "tcgen05_st_16x32bx2_x2_unpack16",
+        abi_id: "i0747",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x2_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0748",
+        id: "tcgen05_st_16x32bx2_x4_raw",
+        abi_id: "i0748",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x4_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0749",
+        id: "tcgen05_st_16x32bx2_x4_unpack16",
+        abi_id: "i0749",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x4_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0750",
+        id: "tcgen05_st_16x32bx2_x8_raw",
+        abi_id: "i0750",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x8_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0751",
+        id: "tcgen05_st_16x32bx2_x8_unpack16",
+        abi_id: "i0751",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x8_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0752",
+        id: "tcgen05_st_16x32bx2_x16_raw",
+        abi_id: "i0752",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x16_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0753",
+        id: "tcgen05_st_16x32bx2_x16_unpack16",
+        abi_id: "i0753",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x16_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0754",
+        id: "tcgen05_st_16x32bx2_x32_raw",
+        abi_id: "i0754",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x32_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0755",
+        id: "tcgen05_st_16x32bx2_x32_unpack16",
+        abi_id: "i0755",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x32_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0756",
+        id: "tcgen05_st_16x32bx2_x64_raw",
+        abi_id: "i0756",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x64_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0757",
+        id: "tcgen05_st_16x32bx2_x64_unpack16",
+        abi_id: "i0757",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x64_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0758",
+        id: "tcgen05_st_16x32bx2_x128_raw",
+        abi_id: "i0758",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x128_raw",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0759",
+        id: "tcgen05_st_16x32bx2_x128_unpack16",
+        abi_id: "i0759",
+        dialect_op: "nvvm.tcgen05_st_16x32bx2_x128_unpack16",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "ImmArg<arg3>",
+                "IntrArgMemOnly",
+                "IntrConvergent",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs
new file mode 100644
index 0000000000..3ae5d84fb5
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs
@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `active_mask` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn active_mask_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0044").unwrap();
+    assert_eq!(target.id, "active_mask");
+    assert_eq!(target.abi_id, "i0044");
+    assert_eq!(target.dialect_op, "nvvm.activemask");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 62);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(62),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(62),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "ACTIVEMASK",
+            asm: "activemask.b32 \t$dest;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 30",
+                "Subtarget->getPTXVersion() >= 62"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrHasSideEffects",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs
new file mode 100644
index 0000000000..6648da25a6
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs
@@ -0,0 +1,320 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `clc` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn clc_try_cancel_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0322").unwrap();
+    assert_eq!(target.id, "clc_try_cancel");
+    assert_eq!(target.abi_id, "i0322");
+    assert_eq!(target.dialect_op, "nvvm.clc_try_cancel");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CLUSTERLAUNCHCONTRL_TRY_CANCEL",
+            asm: "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 \t[$addr], [$mbar];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 100",
+                "Subtarget->getPTXVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrArgMemOnly", "IntrHasSideEffects"] as &[&str]
+    );
+}
+
+#[test]
+fn clc_try_cancel_multicast_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0323").unwrap();
+    assert_eq!(target.id, "clc_try_cancel_multicast");
+    assert_eq!(target.abi_id, "i0323");
+    assert_eq!(target.dialect_op, "nvvm.clc_try_cancel_multicast");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CLUSTERLAUNCHCONTRL_TRY_CANCEL_MULTICAST",
+            asm: "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 \t[$addr], [$mbar];",
+            predicates: &["Subtarget->hasClusterLaunchControlTryCancelMulticastSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrArgMemOnly", "IntrHasSideEffects"] as &[&str]
+    );
+}
+
+#[test]
+fn clc_query_is_canceled_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0324").unwrap();
+    assert_eq!(target.id, "clc_query_is_canceled");
+    assert_eq!(target.abi_id, "i0324");
+    assert_eq!(target.dialect_op, "nvvm.clc_query_is_canceled");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn clc_query_get_first_ctaid_x_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0325").unwrap();
+    assert_eq!(target.id, "clc_query_get_first_ctaid_x");
+    assert_eq!(target.abi_id, "i0325");
+    assert_eq!(target.dialect_op, "nvvm.clc_query_get_first_ctaid_x");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn clc_query_get_first_ctaid_y_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0326").unwrap();
+    assert_eq!(target.id, "clc_query_get_first_ctaid_y");
+    assert_eq!(target.abi_id, "i0326");
+    assert_eq!(target.dialect_op, "nvvm.clc_query_get_first_ctaid_y");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn clc_query_get_first_ctaid_z_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0327").unwrap();
+    assert_eq!(target.id, "clc_query_get_first_ctaid_z");
+    assert_eq!(target.abi_id, "i0327");
+    assert_eq!(target.dialect_op, "nvvm.clc_query_get_first_ctaid_z");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs
new file mode 100644
index 0000000000..3b7e3335eb
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs
@@ -0,0 +1,390 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `cluster_barrier` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn barrier_cluster_arrive_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0277").unwrap();
+    assert_eq!(target.id, "barrier_cluster_arrive");
+    assert_eq!(target.abi_id, "i0277");
+    assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::Arrive
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_arrive",
+            asm: "barrier.cluster.arrive;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn barrier_cluster_arrive_aligned_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0278").unwrap();
+    assert_eq!(target.id, "barrier_cluster_arrive_aligned");
+    assert_eq!(target.abi_id, "i0278");
+    assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::ArriveAligned
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_arrive_aligned",
+            asm: "barrier.cluster.arrive.aligned;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn barrier_cluster_arrive_relaxed_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0279").unwrap();
+    assert_eq!(target.id, "barrier_cluster_arrive_relaxed");
+    assert_eq!(target.abi_id, "i0279");
+    assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::ArriveRelaxed
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_arrive_relaxed",
+            asm: "barrier.cluster.arrive.relaxed;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn barrier_cluster_arrive_relaxed_aligned_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0280").unwrap();
+    assert_eq!(target.id, "barrier_cluster_arrive_relaxed_aligned");
+    assert_eq!(target.abi_id, "i0280");
+    assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::ArriveRelaxedAligned
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_arrive_relaxed_aligned",
+            asm: "barrier.cluster.arrive.relaxed.aligned;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn barrier_cluster_wait_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0281").unwrap();
+    assert_eq!(target.id, "barrier_cluster_wait");
+    assert_eq!(target.abi_id, "i0281");
+    assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::Wait
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_wait",
+            asm: "barrier.cluster.wait;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn barrier_cluster_wait_aligned_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0282").unwrap();
+    assert_eq!(target.id, "barrier_cluster_wait_aligned");
+    assert_eq!(target.abi_id, "i0282");
+    assert_eq!(target.dialect_op, "nvvm.cluster_barrier");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ClusterBarrier {
+            mode: GeneratedClusterBarrierMode::WaitAligned
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "barrier_cluster_wait_aligned",
+            asm: "barrier.cluster.wait.aligned;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs
new file mode 100644
index 0000000000..3d3307ff17
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs
@@ -0,0 +1,125 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `cluster_memory` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn map_shared_rank_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0320").unwrap();
+    assert_eq!(target.id, "map_shared_rank");
+    assert_eq!(target.abi_id, "i0320");
+    assert_eq!(target.dialect_op, "nvvm.mapa_shared_cluster");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "mapa_shared_cluster_64",
+                asm: "mapa.shared::cluster.u64 \t$d, $a, $b;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 90",
+                    "Subtarget->getPTXVersion() >= 78"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "mapa_shared_cluster_64i",
+                asm: "mapa.shared::cluster.u64 \t$d, $a, $b;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 90",
+                    "Subtarget->getPTXVersion() >= 78"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoCapture<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn dsmem_read_u32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0321").unwrap();
+    assert_eq!(target.id, "dsmem_read_u32");
+    assert_eq!(target.abi_id, "i0321");
+    assert_eq!(target.dialect_op, "nvvm.dsmem_read_u32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs
new file mode 100644
index 0000000000..88fdd0b3b6
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs
@@ -0,0 +1,991 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `cp_async` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn cp_async_ca_4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0086").unwrap();
+    assert_eq!(target.id, "cp_async_ca_4");
+    assert_eq!(target.abi_id, "i0086");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_ca_4");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4",
+            asm: "cp.async.ca.shared.global [$dst], [$src], 4;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "NoAlias<arg0>",
+            "NoAlias<arg1>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_ca_zfill_4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0087").unwrap();
+    assert_eq!(target.id, "cp_async_ca_zfill_4");
+    assert_eq!(target.abi_id, "i0087");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_ca_zfill_4");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4_s",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 4, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_4_si",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 4, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "NoAlias<arg0>",
+            "NoAlias<arg1>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_ca_8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0088").unwrap();
+    assert_eq!(target.id, "cp_async_ca_8");
+    assert_eq!(target.abi_id, "i0088");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_ca_8");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8",
+            asm: "cp.async.ca.shared.global [$dst], [$src], 8;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "NoAlias<arg0>",
+            "NoAlias<arg1>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_ca_zfill_8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0089").unwrap();
+    assert_eq!(target.id, "cp_async_ca_zfill_8");
+    assert_eq!(target.abi_id, "i0089");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_ca_zfill_8");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8_s",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 8, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_8_si",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 8, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "NoAlias<arg0>",
+            "NoAlias<arg1>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_ca_16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0090").unwrap();
+    assert_eq!(target.id, "cp_async_ca_16");
+    assert_eq!(target.abi_id, "i0090");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_ca_16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16",
+            asm: "cp.async.ca.shared.global [$dst], [$src], 16;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "NoAlias<arg0>",
+            "NoAlias<arg1>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_ca_zfill_16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0091").unwrap();
+    assert_eq!(target.id, "cp_async_ca_zfill_16");
+    assert_eq!(target.abi_id, "i0091");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_ca_zfill_16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16_s",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 16, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CA_SHARED_GLOBAL_16_si",
+                asm: "cp.async.ca.shared.global [$dst], [$src], 16, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "NoAlias<arg0>",
+            "NoAlias<arg1>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_cg_16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0092").unwrap();
+    assert_eq!(target.id, "cp_async_cg_16");
+    assert_eq!(target.abi_id, "i0092");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_cg_16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16",
+            asm: "cp.async.cg.shared.global [$dst], [$src], 16;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "NoAlias<arg0>",
+            "NoAlias<arg1>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_cg_zfill_16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0093").unwrap();
+    assert_eq!(target.id, "cp_async_cg_zfill_16");
+    assert_eq!(target.abi_id, "i0093");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_cg_zfill_16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16_s",
+                asm: "cp.async.cg.shared.global [$dst], [$src], 16, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "CP_ASYNC_CG_SHARED_GLOBAL_16_si",
+                asm: "cp.async.cg.shared.global [$dst], [$src], 16, $src_size;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 80",
+                    "Subtarget->getPTXVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "NoAlias<arg0>",
+            "NoAlias<arg1>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_commit_group_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0094").unwrap();
+    assert_eq!(target.id, "cp_async_commit_group");
+    assert_eq!(target.abi_id, "i0094");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_commit_group");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_COMMIT_GROUP",
+            asm: "cp.async.commit_group;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &[] as &[&str]);
+}
+
+#[test]
+fn cp_async_wait_all_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0095").unwrap();
+    assert_eq!(target.id, "cp_async_wait_all");
+    assert_eq!(target.abi_id, "i0095");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_wait_all");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_WAIT_ALL",
+            asm: "cp.async.wait_all;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &[] as &[&str]);
+}
+
+#[test]
+fn cp_async_wait_group_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0096").unwrap();
+    assert_eq!(target.id, "cp_async_wait_group");
+    assert_eq!(target.abi_id, "i0096");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_wait_group");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_WAIT_GROUP",
+            asm: "cp.async.wait_group \t$n;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_mbarrier_arrive_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0101").unwrap();
+    assert_eq!(target.id, "cp_async_mbarrier_arrive");
+    assert_eq!(target.abi_id, "i0101");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_mbarrier_arrive");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_MBARRIER_ARRIVE",
+            asm: "cp.async.mbarrier.arrive.b64 \t[$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_mbarrier_arrive_shared_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0102").unwrap();
+    assert_eq!(target.id, "cp_async_mbarrier_arrive_shared");
+    assert_eq!(target.abi_id, "i0102");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_mbarrier_arrive_shared");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_MBARRIER_ARRIVE_SHARED",
+            asm: "cp.async.mbarrier.arrive.shared.b64 \t[$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_mbarrier_arrive_noinc_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0103").unwrap();
+    assert_eq!(target.id, "cp_async_mbarrier_arrive_noinc");
+    assert_eq!(target.abi_id, "i0103");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_mbarrier_arrive_noinc");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_MBARRIER_ARRIVE_NOINC",
+            asm: "cp.async.mbarrier.arrive.noinc.b64 \t[$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_mbarrier_arrive_noinc_shared_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0104").unwrap();
+    assert_eq!(target.id, "cp_async_mbarrier_arrive_noinc_shared");
+    assert_eq!(target.abi_id, "i0104");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_mbarrier_arrive_noinc_shared"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_MBARRIER_ARRIVE_NOINC_SHARED",
+            asm: "cp.async.mbarrier.arrive.noinc.shared.b64 \t[$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs
new file mode 100644
index 0000000000..e244ed05f6
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs
@@ -0,0 +1,135 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `debug_control` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn trap_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0295").unwrap();
+    assert_eq!(target.id, "trap");
+    assert_eq!(target.abi_id, "i0295");
+    assert_eq!(target.dialect_op, "nvvm.trap");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn breakpoint_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0296").unwrap();
+    assert_eq!(target.id, "breakpoint");
+    assert_eq!(target.abi_id, "i0296");
+    assert_eq!(target.dialect_op, "nvvm.brkpt");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(11)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn pmevent_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0297").unwrap();
+    assert_eq!(target.id, "pmevent");
+    assert_eq!(target.abi_id, "i0297");
+    assert_eq!(target.dialect_op, "nvvm.pmevent");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 14);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs
new file mode 100644
index 0000000000..5fecb7b62b
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs
@@ -0,0 +1,238 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `dotprod` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn dp4a_s32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0030").unwrap();
+    assert_eq!(target.id, "dp4a_s32");
+    assert_eq!(target.abi_id, "i0030");
+    assert_eq!(target.dialect_op, "nvvm.dp4a_s32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 50);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(61)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(61),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "DOT4_ss",
+            asm: "dp4a.s32.s32 \t$dst, $a, $b, $c;",
+            predicates: &["hasDotInstructions"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn dp4a_u32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0031").unwrap();
+    assert_eq!(target.id, "dp4a_u32");
+    assert_eq!(target.abi_id, "i0031");
+    assert_eq!(target.dialect_op, "nvvm.dp4a_u32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 50);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(61)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(61),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "DOT4_uu",
+            asm: "dp4a.u32.u32 \t$dst, $a, $b, $c;",
+            predicates: &["hasDotInstructions"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn dp2a_s32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0032").unwrap();
+    assert_eq!(target.id, "dp2a_s32");
+    assert_eq!(target.abi_id, "i0032");
+    assert_eq!(target.dialect_op, "nvvm.dp2a_s32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 50);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(61)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(61),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "DOT2_lo_ss",
+            asm: "dp2a.lo.s32.s32 \t$dst, $a, $b, $c;",
+            predicates: &["hasDotInstructions"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 2,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn dp2a_u32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0033").unwrap();
+    assert_eq!(target.id, "dp2a_u32");
+    assert_eq!(target.abi_id, "i0033");
+    assert_eq!(target.dialect_op, "nvvm.dp2a_u32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 50);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(61)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(61),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(50),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "DOT2_lo_uu",
+            asm: "dp2a.lo.u32.u32 \t$dst, $a, $b, $c;",
+            predicates: &["hasDotInstructions"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 2,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg2>", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs
new file mode 100644
index 0000000000..9d41eafebd
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs
@@ -0,0 +1,84 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `elect` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn elect_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0367").unwrap();
+    assert_eq!(target.id, "elect_sync");
+    assert_eq!(target.abi_id, "i0367");
+    assert_eq!(target.dialect_op, "nvvm.elect_sync");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "INT_ELECT_SYNC_I",
+                asm: "elect.sync \t$dest|$pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 80",
+                    "Subtarget->getSmVersion() >= 90"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "INT_ELECT_SYNC_R",
+                asm: "elect.sync \t$dest|$pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 80",
+                    "Subtarget->getSmVersion() >= 90"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrInaccessibleMemOnly"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs
new file mode 100644
index 0000000000..86ad413285
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs
@@ -0,0 +1,654 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `execution_control` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn barrier_cta_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0883").unwrap();
+    assert_eq!(target.id, "barrier_cta_sync");
+    assert_eq!(target.abi_id, "i0883");
+    assert_eq!(target.dialect_op, "nvvm.barrier_cta_sync_count");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ii",
+                asm: "barrier.sync \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ir",
+                asm: "barrier.sync \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ri",
+                asm: "barrier.sync \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_rr",
+                asm: "barrier.sync \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn barrier_cta_sync_aligned_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0884").unwrap();
+    assert_eq!(target.id, "barrier_cta_sync_aligned");
+    assert_eq!(target.abi_id, "i0884");
+    assert_eq!(target.dialect_op, "nvvm.barrier_cta_sync_aligned_count");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ALIGNED_ii",
+                asm: "bar.sync \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ALIGNED_ir",
+                asm: "bar.sync \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ALIGNED_ri",
+                asm: "bar.sync \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_SYNC_ALIGNED_rr",
+                asm: "bar.sync \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn barrier_cta_arrive_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0885").unwrap();
+    assert_eq!(target.id, "barrier_cta_arrive");
+    assert_eq!(target.abi_id, "i0885");
+    assert_eq!(target.dialect_op, "nvvm.barrier_cta_arrive_count");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ii",
+                asm: "barrier.arrive \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ir",
+                asm: "barrier.arrive \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ri",
+                asm: "barrier.arrive \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_rr",
+                asm: "barrier.arrive \t$i, $j;",
+                predicates: &["Subtarget->getPTXVersion() >= 60"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn barrier_cta_arrive_aligned_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0886").unwrap();
+    assert_eq!(target.id, "barrier_cta_arrive_aligned");
+    assert_eq!(target.abi_id, "i0886");
+    assert_eq!(target.dialect_op, "nvvm.barrier_cta_arrive_aligned_count");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ii",
+                asm: "bar.arrive \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ir",
+                asm: "bar.arrive \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_ri",
+                asm: "bar.arrive \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "BARRIER_CTA_ARRIVE_ALIGNED_rr",
+                asm: "bar.arrive \t$i, $j;",
+                predicates: &[],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn grid_dependency_launch_dependents_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0913").unwrap();
+    assert_eq!(target.id, "grid_dependency_launch_dependents");
+    assert_eq!(target.abi_id, "i0913");
+    assert_eq!(target.dialect_op, "nvvm.grid_dependency_launch_dependents");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "GRIDDEPCONTROL_LAUNCH_DEPENDENTS",
+            asm: "griddepcontrol.launch_dependents;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrHasSideEffects", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn grid_dependency_wait_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0914").unwrap();
+    assert_eq!(target.id, "grid_dependency_wait");
+    assert_eq!(target.abi_id, "i0914");
+    assert_eq!(target.dialect_op, "nvvm.grid_dependency_wait");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "GRIDDEPCONTROL_WAIT",
+            asm: "griddepcontrol.wait;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrHasSideEffects", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn setmaxnreg_inc_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0915").unwrap();
+    assert_eq!(target.id, "setmaxnreg_inc");
+    assert_eq!(target.abi_id, "i0915");
+    assert_eq!(target.dialect_op, "nvvm.setmaxnreg_inc");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22212",
+            asm: "setmaxnreg.inc.sync.aligned.u32 \t$reg_count;",
+            predicates: &["Subtarget->hasSetMaxNRegSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg0>",
+            "IntrConvergent",
+            "IntrHasSideEffects",
+            "IntrNoMem",
+            "Range<arg0,24,257>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn setmaxnreg_dec_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0916").unwrap();
+    assert_eq!(target.id, "setmaxnreg_dec");
+    assert_eq!(target.abi_id, "i0916");
+    assert_eq!(target.dialect_op, "nvvm.setmaxnreg_dec");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22214",
+            asm: "setmaxnreg.dec.sync.aligned.u32 \t$reg_count;",
+            predicates: &["Subtarget->hasSetMaxNRegSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg0>",
+            "IntrConvergent",
+            "IntrHasSideEffects",
+            "IntrNoMem",
+            "Range<arg0,24,257>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs
new file mode 100644
index 0000000000..21aba61bb1
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs
@@ -0,0 +1,3496 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `extended_minmax` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn min_ftz_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0550").unwrap();
+    assert_eq!(target.id, "min_ftz_f16x2");
+    assert_eq!(target.abi_id, "i0550");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_f16x2",
+            asm: "min.ftz.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_ftz_nan_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0551").unwrap();
+    assert_eq!(target.id, "min_ftz_nan_f16x2");
+    assert_eq!(target.abi_id, "i0551");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_NaN_f16x2",
+            asm: "min.ftz.NaN.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_ftz_nan_xorsign_abs_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0552").unwrap();
+    assert_eq!(target.id, "min_ftz_nan_xorsign_abs_f32");
+    assert_eq!(target.abi_id, "i0552");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_FTZ_NAN_XORSIGN_ABS_F",
+            asm: "min.ftz.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_ftz_nan_xorsign_abs_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0553").unwrap();
+    assert_eq!(target.id, "min_ftz_nan_xorsign_abs_f16x2");
+    assert_eq!(target.abi_id, "i0553");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_NaN_xorsign_abs_f16x2",
+            asm: "min.ftz.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_ftz_xorsign_abs_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0554").unwrap();
+    assert_eq!(target.id, "min_ftz_xorsign_abs_f32");
+    assert_eq!(target.abi_id, "i0554");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_FTZ_XORSIGN_ABS_F",
+            asm: "min.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_ftz_xorsign_abs_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0555").unwrap();
+    assert_eq!(target.id, "min_ftz_xorsign_abs_f16x2");
+    assert_eq!(target.abi_id, "i0555");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_xorsign_abs_f16x2",
+            asm: "min.ftz.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_nan_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0556").unwrap();
+    assert_eq!(target.id, "min_nan_bf16x2");
+    assert_eq!(target.abi_id, "i0556");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_bf16x2",
+            asm: "min.NaN.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_nan_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0557").unwrap();
+    assert_eq!(target.id, "min_nan_f16x2");
+    assert_eq!(target.abi_id, "i0557");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_f16x2",
+            asm: "min.NaN.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_nan_xorsign_abs_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0558").unwrap();
+    assert_eq!(target.id, "min_nan_xorsign_abs_bf16x2");
+    assert_eq!(target.abi_id, "i0558");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_bf16x2",
+            asm: "min.NaN.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_nan_xorsign_abs_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0559").unwrap();
+    assert_eq!(target.id, "min_nan_xorsign_abs_f32");
+    assert_eq!(target.abi_id, "i0559");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NAN_XORSIGN_ABS_F",
+            asm: "min.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_nan_xorsign_abs_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0560").unwrap();
+    assert_eq!(target.id, "min_nan_xorsign_abs_f16x2");
+    assert_eq!(target.abi_id, "i0560");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_f16x2",
+            asm: "min.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_xorsign_abs_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0561").unwrap();
+    assert_eq!(target.id, "min_xorsign_abs_bf16x2");
+    assert_eq!(target.abi_id, "i0561");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_xorsign_abs_bf16x2",
+            asm: "min.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_xorsign_abs_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0562").unwrap();
+    assert_eq!(target.id, "min_xorsign_abs_f32");
+    assert_eq!(target.abi_id, "i0562");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_XORSIGN_ABS_F",
+            asm: "min.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_xorsign_abs_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0563").unwrap();
+    assert_eq!(target.id, "min_xorsign_abs_f16x2");
+    assert_eq!(target.abi_id, "i0563");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_xorsign_abs_f16x2",
+            asm: "min.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_ftz_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0564").unwrap();
+    assert_eq!(target.id, "max_ftz_f16x2");
+    assert_eq!(target.abi_id, "i0564");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_f16x2",
+            asm: "max.ftz.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_ftz_nan_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0565").unwrap();
+    assert_eq!(target.id, "max_ftz_nan_f16x2");
+    assert_eq!(target.abi_id, "i0565");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_NaN_f16x2",
+            asm: "max.ftz.NaN.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_ftz_nan_xorsign_abs_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0566").unwrap();
+    assert_eq!(target.id, "max_ftz_nan_xorsign_abs_f32");
+    assert_eq!(target.abi_id, "i0566");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAX_FTZ_NAN_XORSIGN_ABS_F",
+            asm: "max.ftz.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_ftz_nan_xorsign_abs_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0567").unwrap();
+    assert_eq!(target.id, "max_ftz_nan_xorsign_abs_f16x2");
+    assert_eq!(target.abi_id, "i0567");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_NaN_xorsign_abs_f16x2",
+            asm: "max.ftz.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_ftz_xorsign_abs_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0568").unwrap();
+    assert_eq!(target.id, "max_ftz_xorsign_abs_f32");
+    assert_eq!(target.abi_id, "i0568");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAX_FTZ_XORSIGN_ABS_F",
+            asm: "max.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_ftz_xorsign_abs_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0569").unwrap();
+    assert_eq!(target.id, "max_ftz_xorsign_abs_f16x2");
+    assert_eq!(target.abi_id, "i0569");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_xorsign_abs_f16x2",
+            asm: "max.ftz.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_nan_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0570").unwrap();
+    assert_eq!(target.id, "max_nan_bf16x2");
+    assert_eq!(target.abi_id, "i0570");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_bf16x2",
+            asm: "max.NaN.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_nan_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0571").unwrap();
+    assert_eq!(target.id, "max_nan_f16x2");
+    assert_eq!(target.abi_id, "i0571");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_f16x2",
+            asm: "max.NaN.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_nan_xorsign_abs_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0572").unwrap();
+    assert_eq!(target.id, "max_nan_xorsign_abs_bf16x2");
+    assert_eq!(target.abi_id, "i0572");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_bf16x2",
+            asm: "max.NaN.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_nan_xorsign_abs_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0573").unwrap();
+    assert_eq!(target.id, "max_nan_xorsign_abs_f32");
+    assert_eq!(target.abi_id, "i0573");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAX_NAN_XORSIGN_ABS_F",
+            asm: "max.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_nan_xorsign_abs_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0574").unwrap();
+    assert_eq!(target.id, "max_nan_xorsign_abs_f16x2");
+    assert_eq!(target.abi_id, "i0574");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_f16x2",
+            asm: "max.NaN.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_xorsign_abs_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0575").unwrap();
+    assert_eq!(target.id, "max_xorsign_abs_bf16x2");
+    assert_eq!(target.abi_id, "i0575");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_xorsign_abs_bf16x2",
+            asm: "max.xorsign.abs.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_xorsign_abs_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0576").unwrap();
+    assert_eq!(target.id, "max_xorsign_abs_f32");
+    assert_eq!(target.abi_id, "i0576");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F32,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAX_XORSIGN_ABS_F",
+            asm: "max.xorsign.abs.f32 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_xorsign_abs_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0577").unwrap();
+    assert_eq!(target.id, "max_xorsign_abs_f16x2");
+    assert_eq!(target.abi_id, "i0577");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16x2,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_xorsign_abs_f16x2",
+            asm: "max.xorsign.abs.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0830").unwrap();
+    assert_eq!(target.id, "min_f16");
+    assert_eq!(target.abi_id, "i0830");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_f16",
+            asm: "min.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_ftz_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0831").unwrap();
+    assert_eq!(target.id, "min_ftz_f16");
+    assert_eq!(target.abi_id, "i0831");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_f16",
+            asm: "min.ftz.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_nan_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0832").unwrap();
+    assert_eq!(target.id, "min_nan_f16");
+    assert_eq!(target.abi_id, "i0832");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_f16",
+            asm: "min.NaN.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_ftz_nan_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0833").unwrap();
+    assert_eq!(target.id, "min_ftz_nan_f16");
+    assert_eq!(target.abi_id, "i0833");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_NaN_f16",
+            asm: "min.ftz.NaN.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_xorsign_abs_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0834").unwrap();
+    assert_eq!(target.id, "min_xorsign_abs_f16");
+    assert_eq!(target.abi_id, "i0834");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_xorsign_abs_f16",
+            asm: "min.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_ftz_xorsign_abs_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0835").unwrap();
+    assert_eq!(target.id, "min_ftz_xorsign_abs_f16");
+    assert_eq!(target.abi_id, "i0835");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_xorsign_abs_f16",
+            asm: "min.ftz.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_nan_xorsign_abs_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0836").unwrap();
+    assert_eq!(target.id, "min_nan_xorsign_abs_f16");
+    assert_eq!(target.abi_id, "i0836");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_f16",
+            asm: "min.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_ftz_nan_xorsign_abs_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0837").unwrap();
+    assert_eq!(target.id, "min_ftz_nan_xorsign_abs_f16");
+    assert_eq!(target.abi_id, "i0837");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_ftz_NaN_xorsign_abs_f16",
+            asm: "min.ftz.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0838").unwrap();
+    assert_eq!(target.id, "min_bf16");
+    assert_eq!(target.abi_id, "i0838");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_bf16",
+            asm: "min.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_nan_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0839").unwrap();
+    assert_eq!(target.id, "min_nan_bf16");
+    assert_eq!(target.abi_id, "i0839");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_bf16",
+            asm: "min.NaN.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_xorsign_abs_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0840").unwrap();
+    assert_eq!(target.id, "min_xorsign_abs_bf16");
+    assert_eq!(target.abi_id, "i0840");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_xorsign_abs_bf16",
+            asm: "min.xorsign.abs.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn min_nan_xorsign_abs_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0841").unwrap();
+    assert_eq!(target.id, "min_nan_xorsign_abs_bf16");
+    assert_eq!(target.abi_id, "i0841");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Min,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_NaN_xorsign_abs_bf16",
+            asm: "min.NaN.xorsign.abs.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0842").unwrap();
+    assert_eq!(target.id, "max_f16");
+    assert_eq!(target.abi_id, "i0842");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_f16",
+            asm: "max.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_ftz_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0843").unwrap();
+    assert_eq!(target.id, "max_ftz_f16");
+    assert_eq!(target.abi_id, "i0843");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_f16",
+            asm: "max.ftz.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_nan_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0844").unwrap();
+    assert_eq!(target.id, "max_nan_f16");
+    assert_eq!(target.abi_id, "i0844");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_f16",
+            asm: "max.NaN.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_ftz_nan_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0845").unwrap();
+    assert_eq!(target.id, "max_ftz_nan_f16");
+    assert_eq!(target.abi_id, "i0845");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_NaN_f16",
+            asm: "max.ftz.NaN.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_xorsign_abs_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0846").unwrap();
+    assert_eq!(target.id, "max_xorsign_abs_f16");
+    assert_eq!(target.abi_id, "i0846");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_xorsign_abs_f16",
+            asm: "max.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_ftz_xorsign_abs_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0847").unwrap();
+    assert_eq!(target.id, "max_ftz_xorsign_abs_f16");
+    assert_eq!(target.abi_id, "i0847");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_xorsign_abs_f16",
+            asm: "max.ftz.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_nan_xorsign_abs_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0848").unwrap();
+    assert_eq!(target.id, "max_nan_xorsign_abs_f16");
+    assert_eq!(target.abi_id, "i0848");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_f16",
+            asm: "max.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_ftz_nan_xorsign_abs_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0849").unwrap();
+    assert_eq!(target.id, "max_ftz_nan_xorsign_abs_f16");
+    assert_eq!(target.abi_id, "i0849");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::F16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Ftz,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_ftz_NaN_xorsign_abs_f16",
+            asm: "max.ftz.NaN.xorsign.abs.f16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0850").unwrap();
+    assert_eq!(target.id, "max_bf16");
+    assert_eq!(target.abi_id, "i0850");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_bf16",
+            asm: "max.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_nan_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0851").unwrap();
+    assert_eq!(target.id, "max_nan_bf16");
+    assert_eq!(target.abi_id, "i0851");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_bf16",
+            asm: "max.NaN.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_xorsign_abs_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0852").unwrap();
+    assert_eq!(target.id, "max_xorsign_abs_bf16");
+    assert_eq!(target.abi_id, "i0852");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Number,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_xorsign_abs_bf16",
+            asm: "max.xorsign.abs.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_nan_xorsign_abs_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0853").unwrap();
+    assert_eq!(target.id, "max_nan_xorsign_abs_bf16");
+    assert_eq!(target.abi_id, "i0853");
+    assert_eq!(target.dialect_op, "nvvm.extended_minmax");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ExtendedMinMax {
+            format: GeneratedExtendedMinMaxFormat::Bf16,
+            operation: GeneratedExtendedMinMaxOperation::Max,
+            subnormal: GeneratedExtendedMinMaxSubnormal::Preserve,
+            nan: GeneratedExtendedMinMaxNan::Nan,
+            xorsign_abs: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 72);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(86)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(72),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(86),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_NaN_xorsign_abs_bf16",
+            asm: "max.NaN.xorsign.abs.bf16 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 72",
+                "Subtarget->getSmVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs
new file mode 100644
index 0000000000..d07000b37f
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs
@@ -0,0 +1,252 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `integer_minmax` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn min_relu_s32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0987").unwrap();
+    assert_eq!(target.id, "min_relu_s32");
+    assert_eq!(target.abi_id, "i0987");
+    assert_eq!(target.dialect_op, "nvvm.min_relu_s32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            }]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn max_relu_s32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0988").unwrap();
+    assert_eq!(target.id, "max_relu_s32");
+    assert_eq!(target.abi_id, "i0988");
+    assert_eq!(target.dialect_op, "nvvm.max_relu_s32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            }]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn min_s16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0989").unwrap();
+    assert_eq!(target.id, "min_s16x2");
+    assert_eq!(target.abi_id, "i0989");
+    assert_eq!(target.dialect_op, "nvvm.min_s16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            }]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn max_s16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0990").unwrap();
+    assert_eq!(target.id, "max_s16x2");
+    assert_eq!(target.abi_id, "i0990");
+    assert_eq!(target.dialect_op, "nvvm.max_s16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            }]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn min_u16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0991").unwrap();
+    assert_eq!(target.id, "min_u16x2");
+    assert_eq!(target.abi_id, "i0991");
+    assert_eq!(target.dialect_op, "nvvm.min_u16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            }]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn max_u16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0992").unwrap();
+    assert_eq!(target.id, "max_u16x2");
+    assert_eq!(target.abi_id, "i0992");
+    assert_eq!(target.dialect_op, "nvvm.max_u16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            }]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn min_relu_s16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0993").unwrap();
+    assert_eq!(target.id, "min_relu_s16x2");
+    assert_eq!(target.abi_id, "i0993");
+    assert_eq!(target.dialect_op, "nvvm.min_relu_s16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            }]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn max_relu_s16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0994").unwrap();
+    assert_eq!(target.id, "max_relu_s16x2");
+    assert_eq!(target.abi_id, "i0994");
+    assert_eq!(target.dialect_op, "nvvm.max_relu_s16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            }]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs
new file mode 100644
index 0000000000..8c2b6db6e5
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs
@@ -0,0 +1,1662 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `ldmatrix` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn ldmatrix_m8n8_x4_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0013").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n8_x4_b16");
+    assert_eq!(target.abi_id, "i0013");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X4,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B16
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20697",
+            asm: "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n8_x1_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0025").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n8_x1_b16");
+    assert_eq!(target.abi_id, "i0025");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B16
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20675",
+            asm: "ldmatrix.sync.aligned.m8n8.x1.shared.b16 {{$rx10}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n8_x1_trans_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0026").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n8_x1_trans_b16");
+    assert_eq!(target.abi_id, "i0026");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B16
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20758",
+            asm: "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16 {{$rx10}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n8_x2_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0027").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n8_x2_b16");
+    assert_eq!(target.abi_id, "i0027");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B16
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20687",
+            asm: "ldmatrix.sync.aligned.m8n8.x2.shared.b16 {{$rx20, $rx21}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n8_x2_trans_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0028").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n8_x2_trans_b16");
+    assert_eq!(target.abi_id, "i0028");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B16
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20762",
+            asm: "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16 {{$rx20, $rx21}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n8_x4_trans_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0029").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n8_x4_trans_b16");
+    assert_eq!(target.abi_id, "i0029");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n8,
+            multiplicity: GeneratedLdmatrixMultiplicity::X4,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B16
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20766",
+            asm: "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m16n16_x1_trans_b8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0378").unwrap();
+    assert_eq!(target.id, "ldmatrix_m16n16_x1_trans_b8");
+    assert_eq!(target.abi_id, "i0378");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20772",
+            asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {{$rx10, $rx11}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0379").unwrap();
+    assert_eq!(target.id, "ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64");
+    assert_eq!(target.abi_id, "i0379");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8x16B4x16P64
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20782",
+            asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b4x16_p64 {{$rx10, $rx11}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0380").unwrap();
+    assert_eq!(target.id, "ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32");
+    assert_eq!(target.abi_id, "i0380");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8x16B6x16P32
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20777",
+            asm: "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b6x16_p32 {{$rx10, $rx11}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m16n16_x2_trans_b8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0381").unwrap();
+    assert_eq!(target.id, "ldmatrix_m16n16_x2_trans_b8");
+    assert_eq!(target.abi_id, "i0381");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20789",
+            asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0382").unwrap();
+    assert_eq!(target.id, "ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64");
+    assert_eq!(target.abi_id, "i0382");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8x16B4x16P64
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20799",
+            asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b4x16_p64 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0383").unwrap();
+    assert_eq!(target.id, "ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32");
+    assert_eq!(target.abi_id, "i0383");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M16n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Transposed,
+            element: GeneratedLdmatrixElement::B8x16B6x16P32
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20794",
+            asm: "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b6x16_p32 {{$rx20, $rx21, $rx22, $rx23}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n16_x1_b8x16_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0384").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n16_x1_b8x16_b4x16_p64");
+    assert_eq!(target.abi_id, "i0384");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B4x16P64
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20707",
+            asm: "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b4x16_p64 {{$rx10}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n16_x1_b8x16_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0385").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n16_x1_b8x16_b6x16_p32");
+    assert_eq!(target.abi_id, "i0385");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X1,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B6x16P32
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20702",
+            asm: "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b6x16_p32 {{$rx10}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n16_x2_b8x16_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0386").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n16_x2_b8x16_b4x16_p64");
+    assert_eq!(target.abi_id, "i0386");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B4x16P64
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20717",
+            asm: "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b4x16_p64 {{$rx20, $rx21}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n16_x2_b8x16_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0387").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n16_x2_b8x16_b6x16_p32");
+    assert_eq!(target.abi_id, "i0387");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X2,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B6x16P32
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20712",
+            asm: "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b6x16_p32 {{$rx20, $rx21}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n16_x4_b8x16_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0388").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n16_x4_b8x16_b4x16_p64");
+    assert_eq!(target.abi_id, "i0388");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X4,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B4x16P64
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20727",
+            asm: "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b4x16_p64 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ldmatrix_m8n16_x4_b8x16_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0389").unwrap();
+    assert_eq!(target.id, "ldmatrix_m8n16_x4_b8x16_b6x16_p32");
+    assert_eq!(target.abi_id, "i0389");
+    assert_eq!(target.dialect_op, "nvvm.ldmatrix");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Ldmatrix {
+            shape: GeneratedLdmatrixShape::M8n16,
+            multiplicity: GeneratedLdmatrixMultiplicity::X4,
+            layout: GeneratedLdmatrixLayout::Normal,
+            element: GeneratedLdmatrixElement::B8x16B6x16P32
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20722",
+            asm: "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b6x16_p32 {{$rx40, $rx41, $rx42, $rx43}}, [$src];",
+            predicates: &["Subtarget->hasLdStmatrixBlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: Some(GeneratedSelectionAddressSpace::Shared),
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrReadMem",
+            "NoCapture<arg0>",
+            "ReadOnly<arg0>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs
new file mode 100644
index 0000000000..cae00add20
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs
@@ -0,0 +1,251 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `mbarrier_basic` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn mbarrier_init_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0097").unwrap();
+    assert_eq!(target.id, "mbarrier_init");
+    assert_eq!(target.abi_id, "i0097");
+    assert_eq!(target.dialect_op, "nvvm.mbarrier_init_shared");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "MBARRIER_INIT_SHARED",
+            asm: "mbarrier.init.shared.b64 \t[$addr], $count;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn mbarrier_arrive_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0098").unwrap();
+    assert_eq!(target.id, "mbarrier_arrive");
+    assert_eq!(target.abi_id, "i0098");
+    assert_eq!(target.dialect_op, "nvvm.mbarrier_arrive_shared");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "MBARRIER_ARRIVE_SHARED",
+            asm: "mbarrier.arrive.shared.b64 \t$state, [$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn mbarrier_test_wait_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0099").unwrap();
+    assert_eq!(target.id, "mbarrier_test_wait");
+    assert_eq!(target.abi_id, "i0099");
+    assert_eq!(target.dialect_op, "nvvm.mbarrier_test_wait_shared");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "MBARRIER_TEST_WAIT_SHARED",
+            asm: "mbarrier.test_wait.shared.b64 \t$res, [$addr], $state;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn mbarrier_inval_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0100").unwrap();
+    assert_eq!(target.id, "mbarrier_inval");
+    assert_eq!(target.abi_id, "i0100");
+    assert_eq!(target.dialect_op, "nvvm.mbarrier_inval_shared");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "MBARRIER_INVAL_SHARED",
+            asm: "mbarrier.inval.shared.b64 \t[$addr];",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrWriteMem",
+            "NoCapture<arg0>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs
new file mode 100644
index 0000000000..c47d8d0a76
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs
@@ -0,0 +1,606 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `mbarrier_extended` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn mbarrier_arrive_expect_tx_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0306").unwrap();
+    assert_eq!(target.id, "mbarrier_arrive_expect_tx");
+    assert_eq!(target.abi_id, "i0306");
+    assert_eq!(target.dialect_op, "nvvm.mbarrier_arrive_expect_tx_shared");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn mbarrier_arrive_expect_tx_cluster_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0307").unwrap();
+    assert_eq!(target.id, "mbarrier_arrive_expect_tx_cluster");
+    assert_eq!(target.abi_id, "i0307");
+    assert_eq!(target.dialect_op, "nvvm.mbarrier_arrive_expect_tx_cluster");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrArgMemOnly", "IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn mbarrier_arrive_cluster_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0308").unwrap();
+    assert_eq!(target.id, "mbarrier_arrive_cluster");
+    assert_eq!(target.abi_id, "i0308");
+    assert_eq!(target.dialect_op, "nvvm.mbarrier_arrive_cluster");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn mbarrier_try_wait_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0309").unwrap();
+    assert_eq!(target.id, "mbarrier_try_wait");
+    assert_eq!(target.abi_id, "i0309");
+    assert_eq!(target.dialect_op, "nvvm.mbarrier_try_wait_shared");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "mbar_try_wait_scope_cta_acquire_STATE",
+            asm: "mbarrier.try_wait.shared.b64 $res, [$addr], $state;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn mbarrier_try_wait_parity_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0310").unwrap();
+    assert_eq!(target.id, "mbarrier_try_wait_parity");
+    assert_eq!(target.abi_id, "i0310");
+    assert_eq!(target.dialect_op, "nvvm.mbarrier_try_wait_parity_shared");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn mbarrier_try_wait_parity_cluster_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0311").unwrap();
+    assert_eq!(target.id, "mbarrier_try_wait_parity_cluster");
+    assert_eq!(target.abi_id, "i0311");
+    assert_eq!(target.dialect_op, "nvvm.mbarrier_try_wait_parity_cluster");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback", "NoCapture<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_async_shared_cta_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0312").unwrap();
+    assert_eq!(target.id, "fence_proxy_async_shared_cta");
+    assert_eq!(target.abi_id, "i0312");
+    assert_eq!(target.dialect_op, "nvvm.fence_proxy_async_shared_cta");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15048",
+            asm: "fence.proxy.async.shared::cta;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn fence_mbarrier_init_release_cluster_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0313").unwrap();
+    assert_eq!(target.id, "fence_mbarrier_init_release_cluster");
+    assert_eq!(target.abi_id, "i0313");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_mbarrier_init_release_cluster"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_MBARRIER_INIT_RELEASE_CLUSTER",
+            asm: "fence.mbarrier_init.release.cluster;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_async_generic_release_shared_cta_cluster_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0314").unwrap();
+    assert_eq!(
+        target.id,
+        "fence_proxy_async_generic_release_shared_cta_cluster"
+    );
+    assert_eq!(target.abi_id, "i0314");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_proxy_async_generic_release_shared_cta_cluster"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FENCE_PROXY_ASYNC_GENERIC_RELEASE_SYNC_RESTRICT_SPACE_CTA_SCOPE_CLUSTER",
+            asm: "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_async_generic_acquire_shared_cluster_cluster_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0315").unwrap();
+    assert_eq!(
+        target.id,
+        "fence_proxy_async_generic_acquire_shared_cluster_cluster"
+    );
+    assert_eq!(target.abi_id, "i0315");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_proxy_async_generic_acquire_shared_cluster_cluster"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FENCE_PROXY_ASYNC_GENERIC_ACQUIRE_SYNC_RESTRICT_SPACE_CLUSTER_SCOPE_CLUSTER",
+            asm: "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn nanosleep_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0316").unwrap();
+    assert_eq!(target.id, "nanosleep");
+    assert_eq!(target.abi_id, "i0316");
+    assert_eq!(target.dialect_op, "nvvm.nanosleep");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 63);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(63),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(63),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "INT_NVVM_NANOSLEEP_I",
+                asm: "nanosleep.u32 \t$i;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 70",
+                    "Subtarget->getPTXVersion() >= 63"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "INT_NVVM_NANOSLEEP_R",
+                asm: "nanosleep.u32 \t$i;",
+                predicates: &[
+                    "Subtarget->getSmVersion() >= 70",
+                    "Subtarget->getPTXVersion() >= 63"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrHasSideEffects", "IntrNoMem"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs
new file mode 100644
index 0000000000..a37c0e0743
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs
@@ -0,0 +1,99 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests, grouped per family shard.
+
+use super::*;
+use std::collections::BTreeSet;
+
+mod active_mask;
+mod clc;
+mod cluster_barrier;
+mod cluster_memory;
+mod cp_async;
+mod debug_control;
+mod dotprod;
+mod elect;
+mod execution_control;
+mod extended_minmax;
+mod integer_minmax;
+mod ldmatrix;
+mod mbarrier_basic;
+mod mbarrier_extended;
+mod movmatrix;
+mod packed_alu;
+mod packed_atomic;
+mod packed_conversion;
+mod prmt;
+mod redux;
+mod register_mma_float;
+mod register_mma_s32;
+mod scalar_arithmetic;
+mod scalar_conversion;
+mod scalar_math;
+mod sparse_mma;
+mod sreg;
+mod stmatrix;
+mod sync;
+mod tcgen05_cp;
+mod tcgen05_ld;
+mod tcgen05_mma;
+mod tcgen05_mma_ws;
+mod tcgen05_other;
+mod tcgen05_st;
+mod tma;
+mod vote;
+mod warp_barrier;
+mod warp_match;
+mod warp_shuffle;
+mod wgmma_control;
+
+#[test]
+fn generated_target_table_is_unique_and_lookup_is_complete() {
+    let mut ids = BTreeSet::new();
+    let mut markers = BTreeSet::new();
+    let mut abi_ids = BTreeSet::new();
+    for group in GENERATED_INTRINSIC_TARGET_GROUPS {
+        let mut previous_abi_id = None;
+        for target in *group {
+            if let Some(previous) = previous_abi_id {
+                assert!(
+                    previous < target.abi_id,
+                    "generated ABI IDs are not strictly increasing: {previous} then {}",
+                    target.abi_id
+                );
+            }
+            previous_abi_id = Some(target.abi_id);
+            assert!(
+                abi_ids.insert(target.abi_id),
+                "duplicate generated ABI ID {}",
+                target.abi_id
+            );
+            assert!(
+                ids.insert(target.id),
+                "duplicate generated intrinsic ID {}",
+                target.id
+            );
+            assert!(
+                markers.insert(target.marker),
+                "duplicate generated marker {}",
+                target.marker
+            );
+            assert_eq!(
+                generated_intrinsic_target_by_marker(target.marker),
+                Some(target)
+            );
+            assert!(
+                generated_intrinsic_targets_by_op_name(target.dialect_op)
+                    .any(|candidate| candidate == target)
+            );
+        }
+    }
+    assert!(generated_intrinsic_target_by_marker("v1:i9999").is_none());
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs
new file mode 100644
index 0000000000..cb5ae5eb56
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs
@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `movmatrix` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn movmatrix_trans_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0305").unwrap();
+    assert_eq!(target.id, "movmatrix_trans_b16");
+    assert_eq!(target.abi_id, "i0305");
+    assert_eq!(target.dialect_op, "nvvm.movmatrix_trans_b16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs
new file mode 100644
index 0000000000..6468240dd9
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs
@@ -0,0 +1,1497 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `packed_alu` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn fma_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0062").unwrap();
+    assert_eq!(target.id, "fma_bf16x2");
+    assert_eq!(target.abi_id, "i0062");
+    assert_eq!(target.dialect_op, "nvvm.fma_bf16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_bf16x2",
+            asm: "fma.rn.bf16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_relu_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0063").unwrap();
+    assert_eq!(target.id, "fma_relu_bf16x2");
+    assert_eq!(target.abi_id, "i0063");
+    assert_eq!(target.dialect_op, "nvvm.fma_relu_bf16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_relu_bf16x2",
+            asm: "fma.rn.relu.bf16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0064").unwrap();
+    assert_eq!(target.id, "add_bf16x2");
+    assert_eq!(target.abi_id, "i0064");
+    assert_eq!(target.dialect_op, "nvvm.add_bf16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn sub_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0065").unwrap();
+    assert_eq!(target.id, "sub_bf16x2");
+    assert_eq!(target.abi_id, "i0065");
+    assert_eq!(target.dialect_op, "nvvm.sub_bf16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn mul_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0066").unwrap();
+    assert_eq!(target.id, "mul_bf16x2");
+    assert_eq!(target.abi_id, "i0066");
+    assert_eq!(target.dialect_op, "nvvm.mul_bf16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn min_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0067").unwrap();
+    assert_eq!(target.id, "min_bf16x2");
+    assert_eq!(target.abi_id, "i0067");
+    assert_eq!(target.dialect_op, "nvvm.min_bf16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_bf16x2",
+            asm: "min.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0068").unwrap();
+    assert_eq!(target.id, "max_bf16x2");
+    assert_eq!(target.abi_id, "i0068");
+    assert_eq!(target.dialect_op, "nvvm.max_bf16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_bf16x2",
+            asm: "max.bf16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn neg_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0069").unwrap();
+    assert_eq!(target.id, "neg_bf16x2");
+    assert_eq!(target.abi_id, "i0069");
+    assert_eq!(target.dialect_op, "nvvm.neg_bf16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_NEG_BF16X2",
+            asm: "neg.bf16x2 \t$dst, $src0;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn abs_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0070").unwrap();
+    assert_eq!(target.id, "abs_bf16x2");
+    assert_eq!(target.abi_id, "i0070");
+    assert_eq!(target.dialect_op, "nvvm.abs_bf16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "ABS_BF16X2",
+            asm: "abs.bf16x2 \t$dst, $src0;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0072").unwrap();
+    assert_eq!(target.id, "fma_f16x2");
+    assert_eq!(target.abi_id, "i0072");
+    assert_eq!(target.dialect_op, "nvvm.fma_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_f16x2",
+            asm: "fma.rn.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 53",
+                "Subtarget->getPTXVersion() >= 42"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_relu_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0073").unwrap();
+    assert_eq!(target.id, "fma_relu_f16x2");
+    assert_eq!(target.abi_id, "i0073");
+    assert_eq!(target.dialect_op, "nvvm.fma_relu_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_relu_f16x2",
+            asm: "fma.rn.relu.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0074").unwrap();
+    assert_eq!(target.id, "add_f16x2");
+    assert_eq!(target.abi_id, "i0074");
+    assert_eq!(target.dialect_op, "nvvm.add_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn sub_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0075").unwrap();
+    assert_eq!(target.id, "sub_f16x2");
+    assert_eq!(target.abi_id, "i0075");
+    assert_eq!(target.dialect_op, "nvvm.sub_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn mul_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0076").unwrap();
+    assert_eq!(target.id, "mul_f16x2");
+    assert_eq!(target.abi_id, "i0076");
+    assert_eq!(target.dialect_op, "nvvm.mul_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn min_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0077").unwrap();
+    assert_eq!(target.id, "min_f16x2");
+    assert_eq!(target.abi_id, "i0077");
+    assert_eq!(target.dialect_op, "nvvm.min_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMIN_f16x2",
+            asm: "min.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn max_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0078").unwrap();
+    assert_eq!(target.id, "max_f16x2");
+    assert_eq!(target.abi_id, "i0078");
+    assert_eq!(target.dialect_op, "nvvm.max_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMAN_f16x2",
+            asm: "max.f16x2 \t$dst, $src0, $src1;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn neg_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0079").unwrap();
+    assert_eq!(target.id, "neg_f16x2");
+    assert_eq!(target.abi_id, "i0079");
+    assert_eq!(target.dialect_op, "nvvm.neg_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn abs_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0080").unwrap();
+    assert_eq!(target.id, "abs_f16x2");
+    assert_eq!(target.abi_id, "i0080");
+    assert_eq!(target.dialect_op, "nvvm.abs_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "ABS_F16X2",
+            asm: "abs.f16x2 \t$dst, $src0;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 53",
+                "Subtarget->getPTXVersion() >= 65"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_ftz_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0854").unwrap();
+    assert_eq!(target.id, "fma_ftz_f16x2");
+    assert_eq!(target.abi_id, "i0854");
+    assert_eq!(target.dialect_op, "nvvm.fma_ftz_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_ftz_f16x2",
+            asm: "fma.rn.ftz.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 53",
+                "Subtarget->getPTXVersion() >= 42"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_sat_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0855").unwrap();
+    assert_eq!(target.id, "fma_sat_f16x2");
+    assert_eq!(target.abi_id, "i0855");
+    assert_eq!(target.dialect_op, "nvvm.fma_sat_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_sat_f16x2",
+            asm: "fma.rn.sat.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 53",
+                "Subtarget->getPTXVersion() >= 42"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_ftz_sat_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0856").unwrap();
+    assert_eq!(target.id, "fma_ftz_sat_f16x2");
+    assert_eq!(target.abi_id, "i0856");
+    assert_eq!(target.dialect_op, "nvvm.fma_ftz_sat_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 42);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(42),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_ftz_sat_f16x2",
+            asm: "fma.rn.ftz.sat.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 53",
+                "Subtarget->getPTXVersion() >= 42"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_ftz_relu_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0857").unwrap();
+    assert_eq!(target.id, "fma_ftz_relu_f16x2");
+    assert_eq!(target.abi_id, "i0857");
+    assert_eq!(target.dialect_op, "nvvm.fma_ftz_relu_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_ftz_relu_f16x2",
+            asm: "fma.rn.ftz.relu.f16x2 \t$dst, $src0, $src1, $src2;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_f32x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0995").unwrap();
+    assert_eq!(target.id, "add_f32x2");
+    assert_eq!(target.abi_id, "i0995");
+    assert_eq!(target.dialect_op, "nvvm.add_f32x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn add_ftz_f32x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0996").unwrap();
+    assert_eq!(target.id, "add_ftz_f32x2");
+    assert_eq!(target.abi_id, "i0996");
+    assert_eq!(target.dialect_op, "nvvm.add_ftz_f32x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn sub_f32x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0997").unwrap();
+    assert_eq!(target.id, "sub_f32x2");
+    assert_eq!(target.abi_id, "i0997");
+    assert_eq!(target.dialect_op, "nvvm.sub_f32x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn sub_ftz_f32x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0998").unwrap();
+    assert_eq!(target.id, "sub_ftz_f32x2");
+    assert_eq!(target.abi_id, "i0998");
+    assert_eq!(target.dialect_op, "nvvm.sub_ftz_f32x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn mul_f32x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0999").unwrap();
+    assert_eq!(target.id, "mul_f32x2");
+    assert_eq!(target.abi_id, "i0999");
+    assert_eq!(target.dialect_op, "nvvm.mul_f32x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn mul_ftz_f32x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1000").unwrap();
+    assert_eq!(target.id, "mul_ftz_f32x2");
+    assert_eq!(target.abi_id, "i1000");
+    assert_eq!(target.dialect_op, "nvvm.mul_ftz_f32x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn fma_f32x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1001").unwrap();
+    assert_eq!(target.id, "fma_f32x2");
+    assert_eq!(target.abi_id, "i1001");
+    assert_eq!(target.dialect_op, "nvvm.fma_f32x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn fma_ftz_f32x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1002").unwrap();
+    assert_eq!(target.id, "fma_ftz_f32x2");
+    assert_eq!(target.abi_id, "i1002");
+    assert_eq!(target.dialect_op, "nvvm.fma_ftz_f32x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs
new file mode 100644
index 0000000000..737163f85b
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs
@@ -0,0 +1,104 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `packed_atomic` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn packed_atomic_add_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0014").unwrap();
+    assert_eq!(target.id, "packed_atomic_add_f16x2");
+    assert_eq!(target.abi_id, "i0014");
+    assert_eq!(target.dialect_op, "nvvm.packed_atomic_add");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::PackedAtomic {
+            format: GeneratedPackedAtomicFormat::F16x2
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 62);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(62),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(70),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(62),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn packed_atomic_add_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0015").unwrap();
+    assert_eq!(target.id, "packed_atomic_add_bf16x2");
+    assert_eq!(target.abi_id, "i0015");
+    assert_eq!(target.dialect_op, "nvvm.packed_atomic_add");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::PackedAtomic {
+            format: GeneratedPackedAtomicFormat::Bf16x2
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs
new file mode 100644
index 0000000000..71e9f3eaee
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs
@@ -0,0 +1,804 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `packed_conversion` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn cvt_f32x2_bf16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0071").unwrap();
+    assert_eq!(target.id, "cvt_f32x2_bf16x2");
+    assert_eq!(target.abi_id, "i0071");
+    assert_eq!(target.dialect_op, "nvvm.cvt_f32x2_bf16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_f16x2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0081").unwrap();
+    assert_eq!(target.id, "cvt_f16x2_f32");
+    assert_eq!(target.abi_id, "i0081");
+    assert_eq!(target.dialect_op, "nvvm.cvt_f16x2_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rz_f16x2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0082").unwrap();
+    assert_eq!(target.id, "cvt_rz_f16x2_f32");
+    assert_eq!(target.abi_id, "i0082");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rz_f16x2_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_relu_f16x2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0083").unwrap();
+    assert_eq!(target.id, "cvt_rn_relu_f16x2_f32");
+    assert_eq!(target.abi_id, "i0083");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_relu_f16x2_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_relu_bf16x2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0084").unwrap();
+    assert_eq!(target.id, "cvt_rn_relu_bf16x2_f32");
+    assert_eq!(target.abi_id, "i0084");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_relu_bf16x2_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rz_bf16x2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0085").unwrap();
+    assert_eq!(target.id, "cvt_rz_bf16x2_f32");
+    assert_eq!(target.abi_id, "i0085");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rz_bf16x2_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_satfinite_e4m3x2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0259").unwrap();
+    assert_eq!(target.id, "cvt_rn_satfinite_e4m3x2_f32");
+    assert_eq!(target.abi_id, "i0259");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_e4m3x2_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_satfinite_relu_e4m3x2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0260").unwrap();
+    assert_eq!(target.id, "cvt_rn_satfinite_relu_e4m3x2_f32");
+    assert_eq!(target.abi_id, "i0260");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_relu_e4m3x2_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_satfinite_e5m2x2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0261").unwrap();
+    assert_eq!(target.id, "cvt_rn_satfinite_e5m2x2_f32");
+    assert_eq!(target.abi_id, "i0261");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_e5m2x2_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_satfinite_relu_e5m2x2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0262").unwrap();
+    assert_eq!(target.id, "cvt_rn_satfinite_relu_e5m2x2_f32");
+    assert_eq!(target.abi_id, "i0262");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_relu_e5m2x2_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_satfinite_e4m3x2_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0822").unwrap();
+    assert_eq!(target.id, "cvt_rn_satfinite_e4m3x2_f16x2");
+    assert_eq!(target.abi_id, "i0822");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_e4m3x2_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_satfinite_relu_e4m3x2_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0823").unwrap();
+    assert_eq!(target.id, "cvt_rn_satfinite_relu_e4m3x2_f16x2");
+    assert_eq!(target.abi_id, "i0823");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_relu_e4m3x2_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_satfinite_e5m2x2_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0824").unwrap();
+    assert_eq!(target.id, "cvt_rn_satfinite_e5m2x2_f16x2");
+    assert_eq!(target.abi_id, "i0824");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_e5m2x2_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_satfinite_relu_e5m2x2_f16x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0825").unwrap();
+    assert_eq!(target.id, "cvt_rn_satfinite_relu_e5m2x2_f16x2");
+    assert_eq!(target.abi_id, "i0825");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_satfinite_relu_e5m2x2_f16x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_f16x2_e4m3x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0826").unwrap();
+    assert_eq!(target.id, "cvt_rn_f16x2_e4m3x2");
+    assert_eq!(target.abi_id, "i0826");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_f16x2_e4m3x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_relu_f16x2_e4m3x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0827").unwrap();
+    assert_eq!(target.id, "cvt_rn_relu_f16x2_e4m3x2");
+    assert_eq!(target.abi_id, "i0827");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_relu_f16x2_e4m3x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_f16x2_e5m2x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0828").unwrap();
+    assert_eq!(target.id, "cvt_rn_f16x2_e5m2x2");
+    assert_eq!(target.abi_id, "i0828");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_f16x2_e5m2x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_relu_f16x2_e5m2x2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0829").unwrap();
+    assert_eq!(target.id, "cvt_rn_relu_f16x2_e5m2x2");
+    assert_eq!(target.abi_id, "i0829");
+    assert_eq!(target.dialect_op, "nvvm.cvt_rn_relu_f16x2_e5m2x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs
new file mode 100644
index 0000000000..6ed9313c59
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs
@@ -0,0 +1,355 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `prmt` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn prmt_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0252").unwrap();
+    assert_eq!(target.id, "prmt");
+    assert_eq!(target.abi_id, "i0252");
+    assert_eq!(target.dialect_op, "nvvm.prmt");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::Generic
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn prmt_f4e_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0253").unwrap();
+    assert_eq!(target.id, "prmt_f4e");
+    assert_eq!(target.abi_id, "i0253");
+    assert_eq!(target.dialect_op, "nvvm.prmt");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::F4e
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn prmt_b4e_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0254").unwrap();
+    assert_eq!(target.id, "prmt_b4e");
+    assert_eq!(target.abi_id, "i0254");
+    assert_eq!(target.dialect_op, "nvvm.prmt");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::B4e
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn prmt_rc8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0255").unwrap();
+    assert_eq!(target.id, "prmt_rc8");
+    assert_eq!(target.abi_id, "i0255");
+    assert_eq!(target.dialect_op, "nvvm.prmt");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::Rc8
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn prmt_ecl_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0256").unwrap();
+    assert_eq!(target.id, "prmt_ecl");
+    assert_eq!(target.abi_id, "i0256");
+    assert_eq!(target.dialect_op, "nvvm.prmt");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::Ecl
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn prmt_ecr_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0257").unwrap();
+    assert_eq!(target.id, "prmt_ecr");
+    assert_eq!(target.abi_id, "i0257");
+    assert_eq!(target.dialect_op, "nvvm.prmt");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::Ecr
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn prmt_rc16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0258").unwrap();
+    assert_eq!(target.id, "prmt_rc16");
+    assert_eq!(target.abi_id, "i0258");
+    assert_eq!(target.dialect_op, "nvvm.prmt");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Prmt {
+            mode: GeneratedPrmtMode::Rc16
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs
new file mode 100644
index 0000000000..d67176b7fd
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs
@@ -0,0 +1,652 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `redux` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn redux_sync_add_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0017").unwrap();
+    assert_eq!(target.id, "redux_sync_add");
+    assert_eq!(target.abi_id, "i0017");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_add");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15029",
+            asm: "redux.sync.add.s32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_min_u32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0018").unwrap();
+    assert_eq!(target.id, "redux_sync_min_u32");
+    assert_eq!(target.abi_id, "i0018");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_umin");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15027",
+            asm: "redux.sync.min.u32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_min_i32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0019").unwrap();
+    assert_eq!(target.id, "redux_sync_min_i32");
+    assert_eq!(target.abi_id, "i0019");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_min");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15030",
+            asm: "redux.sync.min.s32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_max_u32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0020").unwrap();
+    assert_eq!(target.id, "redux_sync_max_u32");
+    assert_eq!(target.abi_id, "i0020");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_umax");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15028",
+            asm: "redux.sync.max.u32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_max_i32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0021").unwrap();
+    assert_eq!(target.id, "redux_sync_max_i32");
+    assert_eq!(target.abi_id, "i0021");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_max");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15031",
+            asm: "redux.sync.max.s32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_and_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0022").unwrap();
+    assert_eq!(target.id, "redux_sync_and");
+    assert_eq!(target.abi_id, "i0022");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_and");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15032",
+            asm: "redux.sync.and.b32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_or_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0023").unwrap();
+    assert_eq!(target.id, "redux_sync_or");
+    assert_eq!(target.abi_id, "i0023");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_or");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15034",
+            asm: "redux.sync.or.b32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_xor_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0024").unwrap();
+    assert_eq!(target.id, "redux_sync_xor");
+    assert_eq!(target.abi_id, "i0024");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_xor");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15033",
+            asm: "redux.sync.xor.b32 \t$dst, $src, $mask;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_min_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1003").unwrap();
+    assert_eq!(target.id, "redux_sync_min_f32");
+    assert_eq!(target.abi_id, "i1003");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_fmin");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ])
+        }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15035",
+            asm: "redux.sync.min.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_min_nan_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1004").unwrap();
+    assert_eq!(target.id, "redux_sync_min_nan_f32");
+    assert_eq!(target.abi_id, "i1004");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_fmin_nan");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ])
+        }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15038",
+            asm: "redux.sync.min.NaN.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_min_abs_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1005").unwrap();
+    assert_eq!(target.id, "redux_sync_min_abs_f32");
+    assert_eq!(target.abi_id, "i1005");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_fmin_abs");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ])
+        }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15037",
+            asm: "redux.sync.min.abs.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_min_abs_nan_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1006").unwrap();
+    assert_eq!(target.id, "redux_sync_min_abs_nan_f32");
+    assert_eq!(target.abi_id, "i1006");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_fmin_abs_nan");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ])
+        }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15039",
+            asm: "redux.sync.min.abs.NaN.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_max_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1007").unwrap();
+    assert_eq!(target.id, "redux_sync_max_f32");
+    assert_eq!(target.abi_id, "i1007");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_fmax");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ])
+        }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15040",
+            asm: "redux.sync.max.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_max_nan_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1008").unwrap();
+    assert_eq!(target.id, "redux_sync_max_nan_f32");
+    assert_eq!(target.abi_id, "i1008");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_fmax_nan");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ])
+        }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15042",
+            asm: "redux.sync.max.NaN.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_max_abs_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1009").unwrap();
+    assert_eq!(target.id, "redux_sync_max_abs_f32");
+    assert_eq!(target.abi_id, "i1009");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_fmax_abs");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ])
+        }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15041",
+            asm: "redux.sync.max.abs.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn redux_sync_max_abs_nan_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1010").unwrap();
+    assert_eq!(target.id, "redux_sync_max_abs_nan_f32");
+    assert_eq!(target.abi_id, "i1010");
+    assert_eq!(target.dialect_op, "nvvm.redux_sync_fmax_abs_nan");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+            ])
+        }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_15043",
+            asm: "redux.sync.max.abs.NaN.f32 \t$dst, $src, $mask;",
+            predicates: &["Subtarget->hasReduxSyncF32()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs
new file mode 100644
index 0000000000..bc65467a9c
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs
@@ -0,0 +1,7862 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `register_mma_float` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn mma_m16n8k16_f32_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0105").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_f32_bf16");
+    assert_eq!(target.abi_id, "i0105");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::Bf16,
+            b_element: GeneratedRegisterMmaElement::Bf16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_18973",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_f32_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0106").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_f32_f16");
+    assert_eq!(target.abi_id, "i0106");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::F16,
+            b_element: GeneratedRegisterMmaElement::F16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19051",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k8_f32_tf32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0107").unwrap();
+    assert_eq!(target.id, "mma_m16n8k8_f32_tf32");
+    assert_eq!(target.abi_id, "i0107");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k8,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::Tf32,
+            b_element: GeneratedRegisterMmaElement::Tf32,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_18964",
+            asm: "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k4_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0109").unwrap();
+    assert_eq!(target.id, "mma_m8n8k4_f64");
+    assert_eq!(target.abi_id, "i0109");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k4,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F64,
+            a_element: GeneratedRegisterMmaElement::F64,
+            b_element: GeneratedRegisterMmaElement::F64,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_18989",
+            asm: "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e2m1_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0454").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e2m1_e2m1");
+    assert_eq!(target.abi_id, "i0454");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19350",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e2m1_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0455").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e2m1_e2m3");
+    assert_eq!(target.abi_id, "i0455");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19342",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e2m1_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0456").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e2m1_e3m2");
+    assert_eq!(target.abi_id, "i0456");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19334",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e2m1_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0457").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e2m1_e4m3");
+    assert_eq!(target.abi_id, "i0457");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19318",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e2m1_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0458").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e2m1_e5m2");
+    assert_eq!(target.abi_id, "i0458");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19326",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e2m3_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0459").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e2m3_e2m1");
+    assert_eq!(target.abi_id, "i0459");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19308",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e2m3_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0460").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e2m3_e2m3");
+    assert_eq!(target.abi_id, "i0460");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19300",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e2m3_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0461").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e2m3_e3m2");
+    assert_eq!(target.abi_id, "i0461");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19292",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e2m3_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0462").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e2m3_e4m3");
+    assert_eq!(target.abi_id, "i0462");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19276",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e2m3_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0463").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e2m3_e5m2");
+    assert_eq!(target.abi_id, "i0463");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19284",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e3m2_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0464").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e3m2_e2m1");
+    assert_eq!(target.abi_id, "i0464");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19266",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e3m2_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0465").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e3m2_e2m3");
+    assert_eq!(target.abi_id, "i0465");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19258",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e3m2_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0466").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e3m2_e3m2");
+    assert_eq!(target.abi_id, "i0466");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19250",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e3m2_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0467").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e3m2_e4m3");
+    assert_eq!(target.abi_id, "i0467");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19234",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e3m2_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0468").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e3m2_e5m2");
+    assert_eq!(target.abi_id, "i0468");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19242",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e4m3_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0469").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e4m3_e2m1");
+    assert_eq!(target.abi_id, "i0469");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19164",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e4m3_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0470").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e4m3_e2m3");
+    assert_eq!(target.abi_id, "i0470");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19155",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e4m3_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0471").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e4m3_e3m2");
+    assert_eq!(target.abi_id, "i0471");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19146",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e4m3_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0472").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e4m3_e4m3");
+    assert_eq!(target.abi_id, "i0472");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19119",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e4m3_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0473").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e4m3_e5m2");
+    assert_eq!(target.abi_id, "i0473");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19137",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e5m2_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0474").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e5m2_e2m1");
+    assert_eq!(target.abi_id, "i0474");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19224",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e5m2_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0475").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e5m2_e2m3");
+    assert_eq!(target.abi_id, "i0475");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19216",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e5m2_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0476").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e5m2_e3m2");
+    assert_eq!(target.abi_id, "i0476");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19208",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e5m2_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0477").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e5m2_e4m3");
+    assert_eq!(target.abi_id, "i0477");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19184",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f32_e5m2_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0478").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f32_e5m2_e5m2");
+    assert_eq!(target.abi_id, "i0478");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19200",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e2m1_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0479").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e2m1_e2m1");
+    assert_eq!(target.abi_id, "i0479");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19346",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e2m1_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0480").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e2m1_e2m3");
+    assert_eq!(target.abi_id, "i0480");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19338",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e2m1_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0481").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e2m1_e3m2");
+    assert_eq!(target.abi_id, "i0481");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19330",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e2m1_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0482").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e2m1_e4m3");
+    assert_eq!(target.abi_id, "i0482");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19314",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e2m1_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0483").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e2m1_e5m2");
+    assert_eq!(target.abi_id, "i0483");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19322",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e2m3_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0484").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e2m3_e2m1");
+    assert_eq!(target.abi_id, "i0484");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19304",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e2m3_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0485").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e2m3_e2m3");
+    assert_eq!(target.abi_id, "i0485");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19296",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e2m3_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0486").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e2m3_e3m2");
+    assert_eq!(target.abi_id, "i0486");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19288",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e2m3_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0487").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e2m3_e4m3");
+    assert_eq!(target.abi_id, "i0487");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19272",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e2m3_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0488").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e2m3_e5m2");
+    assert_eq!(target.abi_id, "i0488");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19280",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e3m2_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0489").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e3m2_e2m1");
+    assert_eq!(target.abi_id, "i0489");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19262",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e3m2_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0490").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e3m2_e2m3");
+    assert_eq!(target.abi_id, "i0490");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19254",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e3m2_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0491").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e3m2_e3m2");
+    assert_eq!(target.abi_id, "i0491");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19246",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e3m2_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0492").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e3m2_e4m3");
+    assert_eq!(target.abi_id, "i0492");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19230",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e3m2_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0493").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e3m2_e5m2");
+    assert_eq!(target.abi_id, "i0493");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19238",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e4m3_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0494").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e4m3_e2m1");
+    assert_eq!(target.abi_id, "i0494");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19160",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e4m3_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0495").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e4m3_e2m3");
+    assert_eq!(target.abi_id, "i0495");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19151",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e4m3_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0496").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e4m3_e3m2");
+    assert_eq!(target.abi_id, "i0496");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19142",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e4m3_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0497").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e4m3_e4m3");
+    assert_eq!(target.abi_id, "i0497");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19107",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e4m3_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0498").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e4m3_e5m2");
+    assert_eq!(target.abi_id, "i0498");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19129",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e5m2_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0499").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e5m2_e2m1");
+    assert_eq!(target.abi_id, "i0499");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19220",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e5m2_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0500").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e5m2_e2m3");
+    assert_eq!(target.abi_id, "i0500");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19212",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e5m2_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0501").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e5m2_e3m2");
+    assert_eq!(target.abi_id, "i0501");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19204",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e5m2_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0502").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e5m2_e4m3");
+    assert_eq!(target.abi_id, "i0502");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19176",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_f16_e5m2_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0503").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_f16_e5m2_e5m2");
+    assert_eq!(target.abi_id, "i0503");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::F8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19192",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_fp8_f16_e4m3_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0504").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_fp8_f16_e4m3_e4m3");
+    assert_eq!(target.abi_id, "i0504");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19058",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_fp8_f16_e4m3_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0505").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_fp8_f16_e4m3_e5m2");
+    assert_eq!(target.abi_id, "i0505");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19067",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_fp8_f16_e5m2_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0506").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_fp8_f16_e5m2_e4m3");
+    assert_eq!(target.abi_id, "i0506");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19077",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_fp8_f16_e5m2_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0507").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_fp8_f16_e5m2_e5m2");
+    assert_eq!(target.abi_id, "i0507");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19085",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_fp8_f32_e4m3_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0508").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_fp8_f32_e4m3_e4m3");
+    assert_eq!(target.abi_id, "i0508");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19062",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_fp8_f32_e4m3_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0509").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_fp8_f32_e4m3_e5m2");
+    assert_eq!(target.abi_id, "i0509");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19071",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_fp8_f32_e5m2_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0510").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_fp8_f32_e5m2_e4m3");
+    assert_eq!(target.abi_id, "i0510");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19081",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_fp8_f32_e5m2_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0511").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_fp8_f32_e5m2_e5m2");
+    assert_eq!(target.abi_id, "i0511");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19089",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 87"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_fp8_f16_e4m3_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0512").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_fp8_f16_e4m3_e4m3");
+    assert_eq!(target.abi_id, "i0512");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19098",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_fp8_f16_e4m3_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0513").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_fp8_f16_e4m3_e5m2");
+    assert_eq!(target.abi_id, "i0513");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19124",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_fp8_f16_e5m2_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0514").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_fp8_f16_e5m2_e4m3");
+    assert_eq!(target.abi_id, "i0514");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19170",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_fp8_f16_e5m2_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0515").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_fp8_f16_e5m2_e5m2");
+    assert_eq!(target.abi_id, "i0515");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19188",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_fp8_f32_e4m3_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0516").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_fp8_f32_e4m3_e4m3");
+    assert_eq!(target.abi_id, "i0516");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 84);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19113",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_fp8_f32_e4m3_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0517").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_fp8_f32_e4m3_e5m2");
+    assert_eq!(target.abi_id, "i0517");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 84);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19133",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_fp8_f32_e5m2_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0518").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_fp8_f32_e5m2_e4m3");
+    assert_eq!(target.abi_id, "i0518");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 84);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19180",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_fp8_f32_e5m2_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0519").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_fp8_f32_e5m2_e5m2");
+    assert_eq!(target.abi_id, "i0519");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 84);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(89)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(84),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(89),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19196",
+            asm: "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 89",
+                "Subtarget->getPTXVersion() >= 84"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k4_f32_tf32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0520").unwrap();
+    assert_eq!(target.id, "mma_m16n8k4_f32_tf32");
+    assert_eq!(target.abi_id, "i0520");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k4,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::Tf32,
+            b_element: GeneratedRegisterMmaElement::Tf32,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_18955",
+            asm: "mma.sync.aligned.m16n8k4.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k8_f16_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0521").unwrap();
+    assert_eq!(target.id, "mma_m16n8k8_f16_f16");
+    assert_eq!(target.abi_id, "i0521");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k8,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::F16,
+            b_element: GeneratedRegisterMmaElement::F16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19034",
+            asm: "mma.sync.aligned.m16n8k8.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k8_f32_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0522").unwrap();
+    assert_eq!(target.id, "mma_m16n8k8_f32_bf16");
+    assert_eq!(target.abi_id, "i0522");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k8,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::Bf16,
+            b_element: GeneratedRegisterMmaElement::Bf16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_18980",
+            asm: "mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k8_f32_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0523").unwrap();
+    assert_eq!(target.id, "mma_m16n8k8_f32_f16");
+    assert_eq!(target.abi_id, "i0523");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k8,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::F16,
+            b_element: GeneratedRegisterMmaElement::F16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19038",
+            asm: "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_f16_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0524").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_f16_f16");
+    assert_eq!(target.abi_id, "i0524");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::F16,
+            a_element: GeneratedRegisterMmaElement::F16,
+            b_element: GeneratedRegisterMmaElement::F16,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19047",
+            asm: "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0858").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1");
+    assert_eq!(target.abi_id, "i0858");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19651",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0859").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3");
+    assert_eq!(target.abi_id, "i0859");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19656",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0860").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2");
+    assert_eq!(target.abi_id, "i0860");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19661",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0861").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3");
+    assert_eq!(target.abi_id, "i0861");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19671",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0862").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2");
+    assert_eq!(target.abi_id, "i0862");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m1,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19666",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0863").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1");
+    assert_eq!(target.abi_id, "i0863");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19676",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0864").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3");
+    assert_eq!(target.abi_id, "i0864");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19680",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0865").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2");
+    assert_eq!(target.abi_id, "i0865");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19684",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0866").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3");
+    assert_eq!(target.abi_id, "i0866");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19692",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0867").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2");
+    assert_eq!(target.abi_id, "i0867");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E2m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19688",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0868").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1");
+    assert_eq!(target.abi_id, "i0868");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19697",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0869").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3");
+    assert_eq!(target.abi_id, "i0869");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19701",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0870").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2");
+    assert_eq!(target.abi_id, "i0870");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19705",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0871").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3");
+    assert_eq!(target.abi_id, "i0871");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19713",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0872").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2");
+    assert_eq!(target.abi_id, "i0872");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E3m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19709",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0873").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1");
+    assert_eq!(target.abi_id, "i0873");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19739",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0874").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3");
+    assert_eq!(target.abi_id, "i0874");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19743",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0875").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2");
+    assert_eq!(target.abi_id, "i0875");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19747",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0876").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3");
+    assert_eq!(target.abi_id, "i0876");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19755",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0877").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2");
+    assert_eq!(target.abi_id, "i0877");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E4m3,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19751",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0878").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1");
+    assert_eq!(target.abi_id, "i0878");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19718",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m1.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0879").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3");
+    assert_eq!(target.abi_id, "i0879");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E2m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19722",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0880").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2");
+    assert_eq!(target.abi_id, "i0880");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E3m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19726",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e3m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0881").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3");
+    assert_eq!(target.abi_id, "i0881");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E4m3,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19734",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e4m3.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0882").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2");
+    assert_eq!(target.abi_id, "i0882");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Mxf8f6f4,
+            accumulator: GeneratedRegisterMmaAccumulator::F32,
+            a_element: GeneratedRegisterMmaElement::E5m2,
+            b_element: GeneratedRegisterMmaElement::E5m2,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::NotApplicable
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19730",
+            asm: "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e5m2.f32.ue8m0 \n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$scale_a, {{$byte_id_a, $thread_id_a}},\n\t\t$scale_b, {{$byte_id_b, $thread_id_b}};",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs
new file mode 100644
index 0000000000..89a03b0876
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs
@@ -0,0 +1,3849 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `register_mma_s32` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn mma_m16n8k32_s32_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0108").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_s8");
+    assert_eq!(target.abi_id, "i0108");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19407",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_s32_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0110").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_s32_s8");
+    assert_eq!(target.abi_id, "i0110");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19383",
+            asm: "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_s32_s8_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0111").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_s32_s8_u8");
+    assert_eq!(target.abi_id, "i0111");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19388",
+            asm: "mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_s32_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0112").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_s32_u8");
+    assert_eq!(target.abi_id, "i0112");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19398",
+            asm: "mma.sync.aligned.m16n8k16.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_s32_u8_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0113").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_s32_u8_s8");
+    assert_eq!(target.abi_id, "i0113");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19394",
+            asm: "mma.sync.aligned.m16n8k16.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_s8_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0114").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_s8_u8");
+    assert_eq!(target.abi_id, "i0114");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19412",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0115").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_u8");
+    assert_eq!(target.abi_id, "i0115");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19422",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_u8_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0116").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_u8_s8");
+    assert_eq!(target.abi_id, "i0116");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19418",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_s32_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0117").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_s32_s8_satfinite");
+    assert_eq!(target.abi_id, "i0117");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19546",
+            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_s32_s8_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0118").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_s32_s8_u8_satfinite");
+    assert_eq!(target.abi_id, "i0118");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19549",
+            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_s32_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0119").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_s32_u8_satfinite");
+    assert_eq!(target.abi_id, "i0119");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19555",
+            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k16_s32_u8_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0120").unwrap();
+    assert_eq!(target.id, "mma_m16n8k16_s32_u8_s8_satfinite");
+    assert_eq!(target.abi_id, "i0120");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19552",
+            asm: "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0121").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_s8_satfinite");
+    assert_eq!(target.abi_id, "i0121");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19558",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_s8_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0122").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_s8_u8_satfinite");
+    assert_eq!(target.abi_id, "i0122");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19561",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0123").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_u8_satfinite");
+    assert_eq!(target.abi_id, "i0123");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19567",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_u8_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0124").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_u8_s8_satfinite");
+    assert_eq!(target.abi_id, "i0124");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19564",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k16_s32_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0125").unwrap();
+    assert_eq!(target.id, "mma_m8n8k16_s32_s8");
+    assert_eq!(target.abi_id, "i0125");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19359",
+            asm: "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k16_s32_s8_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0126").unwrap();
+    assert_eq!(target.id, "mma_m8n8k16_s32_s8_u8");
+    assert_eq!(target.abi_id, "i0126");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19364",
+            asm: "mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k16_s32_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0127").unwrap();
+    assert_eq!(target.id, "mma_m8n8k16_s32_u8");
+    assert_eq!(target.abi_id, "i0127");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19374",
+            asm: "mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k16_s32_u8_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0128").unwrap();
+    assert_eq!(target.id, "mma_m8n8k16_s32_u8_s8");
+    assert_eq!(target.abi_id, "i0128");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19370",
+            asm: "mma.sync.aligned.m8n8k16.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k16_s32_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0129").unwrap();
+    assert_eq!(target.id, "mma_m8n8k16_s32_s8_satfinite");
+    assert_eq!(target.abi_id, "i0129");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19534",
+            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k16_s32_s8_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0130").unwrap();
+    assert_eq!(target.id, "mma_m8n8k16_s32_s8_u8_satfinite");
+    assert_eq!(target.abi_id, "i0130");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19537",
+            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k16_s32_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0131").unwrap();
+    assert_eq!(target.id, "mma_m8n8k16_s32_u8_satfinite");
+    assert_eq!(target.abi_id, "i0131");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::U8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19543",
+            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k16_s32_u8_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0132").unwrap();
+    assert_eq!(target.id, "mma_m8n8k16_s32_u8_s8_satfinite");
+    assert_eq!(target.abi_id, "i0132");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k16,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U8,
+            b_element: GeneratedRegisterMmaElement::S8,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19540",
+            asm: "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k32_s32_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0133").unwrap();
+    assert_eq!(target.id, "mma_m8n8k32_s32_s4");
+    assert_eq!(target.abi_id, "i0133");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19431",
+            asm: "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k32_s32_s4_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0134").unwrap();
+    assert_eq!(target.id, "mma_m8n8k32_s32_s4_u4");
+    assert_eq!(target.abi_id, "i0134");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19436",
+            asm: "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k32_s32_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0135").unwrap();
+    assert_eq!(target.id, "mma_m8n8k32_s32_u4");
+    assert_eq!(target.abi_id, "i0135");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19446",
+            asm: "mma.sync.aligned.m8n8k32.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k32_s32_u4_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0136").unwrap();
+    assert_eq!(target.id, "mma_m8n8k32_s32_u4_s4");
+    assert_eq!(target.abi_id, "i0136");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19442",
+            asm: "mma.sync.aligned.m8n8k32.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k32_s32_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0137").unwrap();
+    assert_eq!(target.id, "mma_m8n8k32_s32_s4_satfinite");
+    assert_eq!(target.abi_id, "i0137");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19570",
+            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k32_s32_s4_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0138").unwrap();
+    assert_eq!(target.id, "mma_m8n8k32_s32_s4_u4_satfinite");
+    assert_eq!(target.abi_id, "i0138");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19573",
+            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k32_s32_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0139").unwrap();
+    assert_eq!(target.id, "mma_m8n8k32_s32_u4_satfinite");
+    assert_eq!(target.abi_id, "i0139");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19579",
+            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k32_s32_u4_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0140").unwrap();
+    assert_eq!(target.id, "mma_m8n8k32_s32_u4_s4_satfinite");
+    assert_eq!(target.abi_id, "i0140");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 65);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(65),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19576",
+            asm: "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 65",
+                "Subtarget->getSmVersion() >= 75"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0141").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_s4");
+    assert_eq!(target.abi_id, "i0141");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19453",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_s4_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0142").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_s4_u4");
+    assert_eq!(target.abi_id, "i0142");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19458",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0143").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_u4");
+    assert_eq!(target.abi_id, "i0143");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19468",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_u4_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0144").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_u4_s4");
+    assert_eq!(target.abi_id, "i0144");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19464",
+            asm: "mma.sync.aligned.m16n8k32.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k64_s32_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0145").unwrap();
+    assert_eq!(target.id, "mma_m16n8k64_s32_s4");
+    assert_eq!(target.abi_id, "i0145");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19477",
+            asm: "mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k64_s32_s4_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0146").unwrap();
+    assert_eq!(target.id, "mma_m16n8k64_s32_s4_u4");
+    assert_eq!(target.abi_id, "i0146");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19482",
+            asm: "mma.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k64_s32_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0147").unwrap();
+    assert_eq!(target.id, "mma_m16n8k64_s32_u4");
+    assert_eq!(target.abi_id, "i0147");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19492",
+            asm: "mma.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k64_s32_u4_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0148").unwrap();
+    assert_eq!(target.id, "mma_m16n8k64_s32_u4_s4");
+    assert_eq!(target.abi_id, "i0148");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19488",
+            asm: "mma.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0149").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_s4_satfinite");
+    assert_eq!(target.abi_id, "i0149");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19582",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_s4_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0150").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_s4_u4_satfinite");
+    assert_eq!(target.abi_id, "i0150");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19585",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0151").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_u4_satfinite");
+    assert_eq!(target.abi_id, "i0151");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19591",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k32_s32_u4_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0152").unwrap();
+    assert_eq!(target.id, "mma_m16n8k32_s32_u4_s4_satfinite");
+    assert_eq!(target.abi_id, "i0152");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k32,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19588",
+            asm: "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k64_s32_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0153").unwrap();
+    assert_eq!(target.id, "mma_m16n8k64_s32_s4_satfinite");
+    assert_eq!(target.abi_id, "i0153");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19594",
+            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k64_s32_s4_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0154").unwrap();
+    assert_eq!(target.id, "mma_m16n8k64_s32_s4_u4_satfinite");
+    assert_eq!(target.abi_id, "i0154");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::S4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19597",
+            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k64_s32_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0155").unwrap();
+    assert_eq!(target.id, "mma_m16n8k64_s32_u4_satfinite");
+    assert_eq!(target.abi_id, "i0155");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::U4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19603",
+            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k64_s32_u4_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0156").unwrap();
+    assert_eq!(target.id, "mma_m16n8k64_s32_u4_s4_satfinite");
+    assert_eq!(target.abi_id, "i0156");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k64,
+            operation: GeneratedRegisterMmaOperation::Multiply,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::U4,
+            b_element: GeneratedRegisterMmaElement::S4,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19600",
+            asm: "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k128_s32_b1_xor_popc_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0157").unwrap();
+    assert_eq!(target.id, "mma_m8n8k128_s32_b1_xor_popc");
+    assert_eq!(target.abi_id, "i0157");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k128,
+            operation: GeneratedRegisterMmaOperation::XorPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19501",
+            asm: "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k128_s32_b1_xor_popc_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0158").unwrap();
+    assert_eq!(target.id, "mma_m16n8k128_s32_b1_xor_popc");
+    assert_eq!(target.abi_id, "i0158");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k128,
+            operation: GeneratedRegisterMmaOperation::XorPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19514",
+            asm: "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k256_s32_b1_xor_popc_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0159").unwrap();
+    assert_eq!(target.id, "mma_m16n8k256_s32_b1_xor_popc");
+    assert_eq!(target.abi_id, "i0159");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k256,
+            operation: GeneratedRegisterMmaOperation::XorPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19527",
+            asm: "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m8n8k128_s32_b1_and_popc_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0160").unwrap();
+    assert_eq!(target.id, "mma_m8n8k128_s32_b1_and_popc");
+    assert_eq!(target.abi_id, "i0160");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M8n8k128,
+            operation: GeneratedRegisterMmaOperation::AndPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19505",
+            asm: "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k128_s32_b1_and_popc_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0161").unwrap();
+    assert_eq!(target.id, "mma_m16n8k128_s32_b1_and_popc");
+    assert_eq!(target.abi_id, "i0161");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k128,
+            operation: GeneratedRegisterMmaOperation::AndPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19518",
+            asm: "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn mma_m16n8k256_s32_b1_and_popc_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0162").unwrap();
+    assert_eq!(target.id, "mma_m16n8k256_s32_b1_and_popc");
+    assert_eq!(target.abi_id, "i0162");
+    assert_eq!(target.dialect_op, "nvvm.register_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::RegisterMma {
+            shape: GeneratedRegisterMmaShape::M16n8k256,
+            operation: GeneratedRegisterMmaOperation::AndPopc,
+            kind: GeneratedRegisterMmaKind::Standard,
+            accumulator: GeneratedRegisterMmaAccumulator::S32,
+            a_element: GeneratedRegisterMmaElement::B1,
+            b_element: GeneratedRegisterMmaElement::B1,
+            a_layout: GeneratedRegisterMmaLayout::Row,
+            b_layout: GeneratedRegisterMmaLayout::Col,
+            overflow: GeneratedRegisterMmaOverflow::Wrapping
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19531",
+            asm: "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}};",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback", "IntrNoMem"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs
new file mode 100644
index 0000000000..54f6b9dd4c
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs
@@ -0,0 +1,4072 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `scalar_arithmetic` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn mul_rn_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0390").unwrap();
+    assert_eq!(target.id, "mul_rn_f64");
+    assert_eq!(target.abi_id, "i0390");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RN_D",
+            asm: "mul.rn.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rz_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0391").unwrap();
+    assert_eq!(target.id, "mul_rz_f64");
+    assert_eq!(target.abi_id, "i0391");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RZ_D",
+            asm: "mul.rz.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rm_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0392").unwrap();
+    assert_eq!(target.id, "mul_rm_f64");
+    assert_eq!(target.abi_id, "i0392");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RM_D",
+            asm: "mul.rm.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rp_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0393").unwrap();
+    assert_eq!(target.id, "mul_rp_f64");
+    assert_eq!(target.abi_id, "i0393");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RP_D",
+            asm: "mul.rp.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn div_rn_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0394").unwrap();
+    assert_eq!(target.id, "div_rn_f64");
+    assert_eq!(target.abi_id, "i0394");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RN_D",
+            asm: "div.rn.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn div_rz_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0395").unwrap();
+    assert_eq!(target.id, "div_rz_f64");
+    assert_eq!(target.abi_id, "i0395");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RZ_D",
+            asm: "div.rz.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn div_rm_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0396").unwrap();
+    assert_eq!(target.id, "div_rm_f64");
+    assert_eq!(target.abi_id, "i0396");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RM_D",
+            asm: "div.rm.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn div_rp_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0397").unwrap();
+    assert_eq!(target.id, "div_rp_f64");
+    assert_eq!(target.abi_id, "i0397");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RP_D",
+            asm: "div.rp.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn fma_rn_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0398").unwrap();
+    assert_eq!(target.id, "fma_rn_f64");
+    assert_eq!(target.abi_id, "i0398");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_f64",
+            asm: "fma.rn.f64 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rz_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0399").unwrap();
+    assert_eq!(target.id, "fma_rz_f64");
+    assert_eq!(target.abi_id, "i0399");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rz_f64",
+            asm: "fma.rz.f64 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rm_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0400").unwrap();
+    assert_eq!(target.id, "fma_rm_f64");
+    assert_eq!(target.abi_id, "i0400");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rm_f64",
+            asm: "fma.rm.f64 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rp_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0401").unwrap();
+    assert_eq!(target.id, "fma_rp_f64");
+    assert_eq!(target.abi_id, "i0401");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rp_f64",
+            asm: "fma.rp.f64 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCreateUndefOrPoison", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rn_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0402").unwrap();
+    assert_eq!(target.id, "mul_rn_f32");
+    assert_eq!(target.abi_id, "i0402");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RN_F",
+            asm: "mul.rn.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rn_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0403").unwrap();
+    assert_eq!(target.id, "mul_rn_ftz_f32");
+    assert_eq!(target.abi_id, "i0403");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RN_FTZ_F",
+            asm: "mul.rn.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0404").unwrap();
+    assert_eq!(target.id, "mul_rz_f32");
+    assert_eq!(target.abi_id, "i0404");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RZ_F",
+            asm: "mul.rz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rz_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0405").unwrap();
+    assert_eq!(target.id, "mul_rz_ftz_f32");
+    assert_eq!(target.abi_id, "i0405");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RZ_FTZ_F",
+            asm: "mul.rz.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rm_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0406").unwrap();
+    assert_eq!(target.id, "mul_rm_f32");
+    assert_eq!(target.abi_id, "i0406");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RM_F",
+            asm: "mul.rm.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rm_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0407").unwrap();
+    assert_eq!(target.id, "mul_rm_ftz_f32");
+    assert_eq!(target.abi_id, "i0407");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RM_FTZ_F",
+            asm: "mul.rm.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rp_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0408").unwrap();
+    assert_eq!(target.id, "mul_rp_f32");
+    assert_eq!(target.abi_id, "i0408");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RP_F",
+            asm: "mul.rp.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn mul_rp_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0409").unwrap();
+    assert_eq!(target.id, "mul_rp_ftz_f32");
+    assert_eq!(target.abi_id, "i0409");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Mul,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_MUL_RP_FTZ_F",
+            asm: "mul.rp.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn div_rn_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0410").unwrap();
+    assert_eq!(target.id, "div_rn_f32");
+    assert_eq!(target.abi_id, "i0410");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RN_F",
+            asm: "div.rn.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn div_rn_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0411").unwrap();
+    assert_eq!(target.id, "div_rn_ftz_f32");
+    assert_eq!(target.abi_id, "i0411");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RN_FTZ_F",
+            asm: "div.rn.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn div_rz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0412").unwrap();
+    assert_eq!(target.id, "div_rz_f32");
+    assert_eq!(target.abi_id, "i0412");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RZ_F",
+            asm: "div.rz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn div_rz_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0413").unwrap();
+    assert_eq!(target.id, "div_rz_ftz_f32");
+    assert_eq!(target.abi_id, "i0413");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RZ_FTZ_F",
+            asm: "div.rz.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn div_rm_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0414").unwrap();
+    assert_eq!(target.id, "div_rm_f32");
+    assert_eq!(target.abi_id, "i0414");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RM_F",
+            asm: "div.rm.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn div_rm_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0415").unwrap();
+    assert_eq!(target.id, "div_rm_ftz_f32");
+    assert_eq!(target.abi_id, "i0415");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RM_FTZ_F",
+            asm: "div.rm.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn div_rp_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0416").unwrap();
+    assert_eq!(target.id, "div_rp_f32");
+    assert_eq!(target.abi_id, "i0416");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RP_F",
+            asm: "div.rp.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn div_rp_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0417").unwrap();
+    assert_eq!(target.id, "div_rp_ftz_f32");
+    assert_eq!(target.abi_id, "i0417");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Div,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_DIV_RP_FTZ_F",
+            asm: "div.rp.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn fma_rn_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0418").unwrap();
+    assert_eq!(target.id, "fma_rn_f32");
+    assert_eq!(target.abi_id, "i0418");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_f32",
+            asm: "fma.rn.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rn_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0419").unwrap();
+    assert_eq!(target.id, "fma_rn_ftz_f32");
+    assert_eq!(target.abi_id, "i0419");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_ftz_f32",
+            asm: "fma.rn.ftz.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rn_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0420").unwrap();
+    assert_eq!(target.id, "fma_rn_sat_f32");
+    assert_eq!(target.abi_id, "i0420");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_sat_f32",
+            asm: "fma.rn.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rn_ftz_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0421").unwrap();
+    assert_eq!(target.id, "fma_rn_ftz_sat_f32");
+    assert_eq!(target.abi_id, "i0421");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rn_ftz_sat_f32",
+            asm: "fma.rn.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0422").unwrap();
+    assert_eq!(target.id, "fma_rz_f32");
+    assert_eq!(target.abi_id, "i0422");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rz_f32",
+            asm: "fma.rz.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rz_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0423").unwrap();
+    assert_eq!(target.id, "fma_rz_ftz_f32");
+    assert_eq!(target.abi_id, "i0423");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rz_ftz_f32",
+            asm: "fma.rz.ftz.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rz_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0424").unwrap();
+    assert_eq!(target.id, "fma_rz_sat_f32");
+    assert_eq!(target.abi_id, "i0424");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rz_sat_f32",
+            asm: "fma.rz.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rz_ftz_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0425").unwrap();
+    assert_eq!(target.id, "fma_rz_ftz_sat_f32");
+    assert_eq!(target.abi_id, "i0425");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rz_ftz_sat_f32",
+            asm: "fma.rz.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rm_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0426").unwrap();
+    assert_eq!(target.id, "fma_rm_f32");
+    assert_eq!(target.abi_id, "i0426");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rm_f32",
+            asm: "fma.rm.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rm_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0427").unwrap();
+    assert_eq!(target.id, "fma_rm_ftz_f32");
+    assert_eq!(target.abi_id, "i0427");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rm_ftz_f32",
+            asm: "fma.rm.ftz.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rm_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0428").unwrap();
+    assert_eq!(target.id, "fma_rm_sat_f32");
+    assert_eq!(target.abi_id, "i0428");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rm_sat_f32",
+            asm: "fma.rm.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rm_ftz_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0429").unwrap();
+    assert_eq!(target.id, "fma_rm_ftz_sat_f32");
+    assert_eq!(target.abi_id, "i0429");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rm_ftz_sat_f32",
+            asm: "fma.rm.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rp_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0430").unwrap();
+    assert_eq!(target.id, "fma_rp_f32");
+    assert_eq!(target.abi_id, "i0430");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rp_f32",
+            asm: "fma.rp.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rp_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0431").unwrap();
+    assert_eq!(target.id, "fma_rp_ftz_f32");
+    assert_eq!(target.abi_id, "i0431");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rp_ftz_f32",
+            asm: "fma.rp.ftz.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rp_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0432").unwrap();
+    assert_eq!(target.id, "fma_rp_sat_f32");
+    assert_eq!(target.abi_id, "i0432");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rp_sat_f32",
+            asm: "fma.rp.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn fma_rp_ftz_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0433").unwrap();
+    assert_eq!(target.id, "fma_rp_ftz_sat_f32");
+    assert_eq!(target.abi_id, "i0433");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Fma,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_FMA_rp_ftz_sat_f32",
+            asm: "fma.rp.ftz.sat.f32 \t$dst, $src0, $src1, $src2;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rn_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0434").unwrap();
+    assert_eq!(target.id, "add_rn_f64");
+    assert_eq!(target.abi_id, "i0434");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RN_D",
+            asm: "add.rn.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rz_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0435").unwrap();
+    assert_eq!(target.id, "add_rz_f64");
+    assert_eq!(target.abi_id, "i0435");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RZ_D",
+            asm: "add.rz.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rm_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0436").unwrap();
+    assert_eq!(target.id, "add_rm_f64");
+    assert_eq!(target.abi_id, "i0436");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RM_D",
+            asm: "add.rm.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rp_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0437").unwrap();
+    assert_eq!(target.id, "add_rp_f64");
+    assert_eq!(target.abi_id, "i0437");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F64,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RP_D",
+            asm: "add.rp.f64 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rn_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0438").unwrap();
+    assert_eq!(target.id, "add_rn_f32");
+    assert_eq!(target.abi_id, "i0438");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RN_F",
+            asm: "add.rn.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rn_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0439").unwrap();
+    assert_eq!(target.id, "add_rn_ftz_f32");
+    assert_eq!(target.abi_id, "i0439");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RN_FTZ_F",
+            asm: "add.rn.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rn_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0440").unwrap();
+    assert_eq!(target.id, "add_rn_sat_f32");
+    assert_eq!(target.abi_id, "i0440");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RN_SAT_F",
+            asm: "add.rn.sat.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rn_ftz_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0441").unwrap();
+    assert_eq!(target.id, "add_rn_ftz_sat_f32");
+    assert_eq!(target.abi_id, "i0441");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rn,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RN_SAT_FTZ_F",
+            asm: "add.rn.sat.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0442").unwrap();
+    assert_eq!(target.id, "add_rz_f32");
+    assert_eq!(target.abi_id, "i0442");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RZ_F",
+            asm: "add.rz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rz_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0443").unwrap();
+    assert_eq!(target.id, "add_rz_ftz_f32");
+    assert_eq!(target.abi_id, "i0443");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RZ_FTZ_F",
+            asm: "add.rz.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rz_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0444").unwrap();
+    assert_eq!(target.id, "add_rz_sat_f32");
+    assert_eq!(target.abi_id, "i0444");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RZ_SAT_F",
+            asm: "add.rz.sat.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rz_ftz_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0445").unwrap();
+    assert_eq!(target.id, "add_rz_ftz_sat_f32");
+    assert_eq!(target.abi_id, "i0445");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rz,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RZ_SAT_FTZ_F",
+            asm: "add.rz.sat.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rm_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0446").unwrap();
+    assert_eq!(target.id, "add_rm_f32");
+    assert_eq!(target.abi_id, "i0446");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RM_F",
+            asm: "add.rm.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rm_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0447").unwrap();
+    assert_eq!(target.id, "add_rm_ftz_f32");
+    assert_eq!(target.abi_id, "i0447");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RM_FTZ_F",
+            asm: "add.rm.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rm_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0448").unwrap();
+    assert_eq!(target.id, "add_rm_sat_f32");
+    assert_eq!(target.abi_id, "i0448");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RM_SAT_F",
+            asm: "add.rm.sat.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rm_ftz_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0449").unwrap();
+    assert_eq!(target.id, "add_rm_ftz_sat_f32");
+    assert_eq!(target.abi_id, "i0449");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rm,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RM_SAT_FTZ_F",
+            asm: "add.rm.sat.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rp_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0450").unwrap();
+    assert_eq!(target.id, "add_rp_f32");
+    assert_eq!(target.abi_id, "i0450");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RP_F",
+            asm: "add.rp.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rp_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0451").unwrap();
+    assert_eq!(target.id, "add_rp_ftz_f32");
+    assert_eq!(target.abi_id, "i0451");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RP_FTZ_F",
+            asm: "add.rp.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rp_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0452").unwrap();
+    assert_eq!(target.id, "add_rp_sat_f32");
+    assert_eq!(target.abi_id, "i0452");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Preserve,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RP_SAT_F",
+            asm: "add.rp.sat.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn add_rp_ftz_sat_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0453").unwrap();
+    assert_eq!(target.id, "add_rp_ftz_sat_f32");
+    assert_eq!(target.abi_id, "i0453");
+    assert_eq!(target.dialect_op, "nvvm.scalar_arithmetic");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarArithmetic {
+            format: GeneratedScalarArithmeticFormat::F32,
+            operation: GeneratedScalarArithmeticOperation::Add,
+            rounding: GeneratedScalarArithmeticRounding::Rp,
+            subnormal: GeneratedScalarArithmeticSubnormal::Ftz,
+            saturation: GeneratedScalarArithmeticSaturation::Sat
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_ADD_RP_SAT_FTZ_F",
+            asm: "add.rp.sat.ftz.f32 \t$dst, $src0, $src1;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["Commutative", "IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs
new file mode 100644
index 0000000000..47ab6cb5a0
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs
@@ -0,0 +1,652 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `scalar_conversion` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn cvt_rna_tf32_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0368").unwrap();
+    assert_eq!(target.id, "cvt_rna_tf32_f32");
+    assert_eq!(target.abi_id, "i0368");
+    assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestAway,
+            saturation: GeneratedScalarConversionSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rna",
+            asm: "cvt.rna.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 70"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rna_satfinite_tf32_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0369").unwrap();
+    assert_eq!(target.id, "cvt_rna_satfinite_tf32_f32");
+    assert_eq!(target.abi_id, "i0369");
+    assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestAway,
+            saturation: GeneratedScalarConversionSaturation::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 81);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(81),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rna_satf",
+            asm: "cvt.rna.satfinite.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 81"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_tf32_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0370").unwrap();
+    assert_eq!(target.id, "cvt_rn_tf32_f32");
+    assert_eq!(target.abi_id, "i0370");
+    assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestEven,
+            saturation: GeneratedScalarConversionSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rn",
+            asm: "cvt.rn.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_relu_tf32_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0371").unwrap();
+    assert_eq!(target.id, "cvt_rn_relu_tf32_f32");
+    assert_eq!(target.abi_id, "i0371");
+    assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestEven,
+            saturation: GeneratedScalarConversionSaturation::Relu
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rn_relu",
+            asm: "cvt.rn.relu.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_satfinite_tf32_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0372").unwrap();
+    assert_eq!(target.id, "cvt_rn_satfinite_tf32_f32");
+    assert_eq!(target.abi_id, "i0372");
+    assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestEven,
+            saturation: GeneratedScalarConversionSaturation::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rn_satf",
+            asm: "cvt.rn.satfinite.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 100",
+                "Subtarget->getPTXVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rn_relu_satfinite_tf32_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0373").unwrap();
+    assert_eq!(target.id, "cvt_rn_relu_satfinite_tf32_f32");
+    assert_eq!(target.abi_id, "i0373");
+    assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::NearestEven,
+            saturation: GeneratedScalarConversionSaturation::ReluSatfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rn_relu_satf",
+            asm: "cvt.rn.relu.satfinite.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 100",
+                "Subtarget->getPTXVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rz_tf32_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0374").unwrap();
+    assert_eq!(target.id, "cvt_rz_tf32_f32");
+    assert_eq!(target.abi_id, "i0374");
+    assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::TowardZero,
+            saturation: GeneratedScalarConversionSaturation::None
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rz",
+            asm: "cvt.rz.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rz_relu_tf32_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0375").unwrap();
+    assert_eq!(target.id, "cvt_rz_relu_tf32_f32");
+    assert_eq!(target.abi_id, "i0375");
+    assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::TowardZero,
+            saturation: GeneratedScalarConversionSaturation::Relu
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rz_relu",
+            asm: "cvt.rz.relu.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rz_satfinite_tf32_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0376").unwrap();
+    assert_eq!(target.id, "cvt_rz_satfinite_tf32_f32");
+    assert_eq!(target.abi_id, "i0376");
+    assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::TowardZero,
+            saturation: GeneratedScalarConversionSaturation::Satfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rz_satf",
+            asm: "cvt.rz.satfinite.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 100",
+                "Subtarget->getPTXVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
+
+#[test]
+fn cvt_rz_relu_satfinite_tf32_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0377").unwrap();
+    assert_eq!(target.id, "cvt_rz_relu_satfinite_tf32_f32");
+    assert_eq!(target.abi_id, "i0377");
+    assert_eq!(target.dialect_op, "nvvm.scalar_conversion");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::ScalarConversion {
+            rounding: GeneratedScalarConversionRounding::TowardZero,
+            saturation: GeneratedScalarConversionSaturation::ReluSatfinite
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(100)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(100),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CVT_to_tf32_rz_relu_satf",
+            asm: "cvt.rz.relu.satfinite.tf32.f32 \t$dst, $src;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 100",
+                "Subtarget->getPTXVersion() >= 86"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs
new file mode 100644
index 0000000000..48b947462b
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs
@@ -0,0 +1,2001 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `scalar_math` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn sin_approx_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0782").unwrap();
+    assert_eq!(target.id, "sin_approx_f32");
+    assert_eq!(target.abi_id, "i0782");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sin_approx_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0783").unwrap();
+    assert_eq!(target.id, "sin_approx_ftz_f32");
+    assert_eq!(target.abi_id, "i0783");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn cos_approx_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0784").unwrap();
+    assert_eq!(target.id, "cos_approx_f32");
+    assert_eq!(target.abi_id, "i0784");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn cos_approx_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0785").unwrap();
+    assert_eq!(target.id, "cos_approx_ftz_f32");
+    assert_eq!(target.abi_id, "i0785");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn lg2_approx_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0786").unwrap();
+    assert_eq!(target.id, "lg2_approx_f32");
+    assert_eq!(target.abi_id, "i0786");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn lg2_approx_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0787").unwrap();
+    assert_eq!(target.id, "lg2_approx_ftz_f32");
+    assert_eq!(target.abi_id, "i0787");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_approx_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0788").unwrap();
+    assert_eq!(target.id, "rcp_approx_ftz_f32");
+    assert_eq!(target.abi_id, "i0788");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_APPROX_FTZ_F",
+            asm: "rcp.approx.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rn_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0789").unwrap();
+    assert_eq!(target.id, "rcp_rn_f32");
+    assert_eq!(target.abi_id, "i0789");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RN_F",
+            asm: "rcp.rn.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rn_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0790").unwrap();
+    assert_eq!(target.id, "rcp_rn_ftz_f32");
+    assert_eq!(target.abi_id, "i0790");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RN_FTZ_F",
+            asm: "rcp.rn.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0791").unwrap();
+    assert_eq!(target.id, "rcp_rz_f32");
+    assert_eq!(target.abi_id, "i0791");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RZ_F",
+            asm: "rcp.rz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rz_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0792").unwrap();
+    assert_eq!(target.id, "rcp_rz_ftz_f32");
+    assert_eq!(target.abi_id, "i0792");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RZ_FTZ_F",
+            asm: "rcp.rz.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rm_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0793").unwrap();
+    assert_eq!(target.id, "rcp_rm_f32");
+    assert_eq!(target.abi_id, "i0793");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RM_F",
+            asm: "rcp.rm.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rm_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0794").unwrap();
+    assert_eq!(target.id, "rcp_rm_ftz_f32");
+    assert_eq!(target.abi_id, "i0794");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RM_FTZ_F",
+            asm: "rcp.rm.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rp_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0795").unwrap();
+    assert_eq!(target.id, "rcp_rp_f32");
+    assert_eq!(target.abi_id, "i0795");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RP_F",
+            asm: "rcp.rp.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rp_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0796").unwrap();
+    assert_eq!(target.id, "rcp_rp_ftz_f32");
+    assert_eq!(target.abi_id, "i0796");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RP_FTZ_F",
+            asm: "rcp.rp.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_approx_ftz_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0797").unwrap();
+    assert_eq!(target.id, "rcp_approx_ftz_f64");
+    assert_eq!(target.abi_id, "i0797");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_APPROX_FTZ_D",
+            asm: "rcp.approx.ftz.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rn_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0798").unwrap();
+    assert_eq!(target.id, "rcp_rn_f64");
+    assert_eq!(target.abi_id, "i0798");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RN_D",
+            asm: "rcp.rn.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rz_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0799").unwrap();
+    assert_eq!(target.id, "rcp_rz_f64");
+    assert_eq!(target.abi_id, "i0799");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RZ_D",
+            asm: "rcp.rz.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rm_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0800").unwrap();
+    assert_eq!(target.id, "rcp_rm_f64");
+    assert_eq!(target.abi_id, "i0800");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RM_D",
+            asm: "rcp.rm.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rcp_rp_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0801").unwrap();
+    assert_eq!(target.id, "rcp_rp_f64");
+    assert_eq!(target.abi_id, "i0801");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_RCP_RP_D",
+            asm: "rcp.rp.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rsqrt_approx_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0802").unwrap();
+    assert_eq!(target.id, "rsqrt_approx_f32");
+    assert_eq!(target.abi_id, "i0802");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rsqrt_approx_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0803").unwrap();
+    assert_eq!(target.id, "rsqrt_approx_ftz_f32");
+    assert_eq!(target.abi_id, "i0803");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn rsqrt_approx_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0804").unwrap();
+    assert_eq!(target.id, "rsqrt_approx_f64");
+    assert_eq!(target.abi_id, "i0804");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_approx_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0805").unwrap();
+    assert_eq!(target.id, "sqrt_approx_f32");
+    assert_eq!(target.abi_id, "i0805");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_APPROX_F",
+            asm: "sqrt.approx.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_approx_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0806").unwrap();
+    assert_eq!(target.id, "sqrt_approx_ftz_f32");
+    assert_eq!(target.abi_id, "i0806");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_APPROX_FTZ_F",
+            asm: "sqrt.approx.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rn_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0807").unwrap();
+    assert_eq!(target.id, "sqrt_rn_f32");
+    assert_eq!(target.abi_id, "i0807");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RN_F",
+            asm: "sqrt.rn.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rn_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0808").unwrap();
+    assert_eq!(target.id, "sqrt_rn_ftz_f32");
+    assert_eq!(target.abi_id, "i0808");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RN_FTZ_F",
+            asm: "sqrt.rn.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0809").unwrap();
+    assert_eq!(target.id, "sqrt_rz_f32");
+    assert_eq!(target.abi_id, "i0809");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RZ_F",
+            asm: "sqrt.rz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rz_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0810").unwrap();
+    assert_eq!(target.id, "sqrt_rz_ftz_f32");
+    assert_eq!(target.abi_id, "i0810");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RZ_FTZ_F",
+            asm: "sqrt.rz.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rm_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0811").unwrap();
+    assert_eq!(target.id, "sqrt_rm_f32");
+    assert_eq!(target.abi_id, "i0811");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RM_F",
+            asm: "sqrt.rm.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rm_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0812").unwrap();
+    assert_eq!(target.id, "sqrt_rm_ftz_f32");
+    assert_eq!(target.abi_id, "i0812");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RM_FTZ_F",
+            asm: "sqrt.rm.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rp_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0813").unwrap();
+    assert_eq!(target.id, "sqrt_rp_f32");
+    assert_eq!(target.abi_id, "i0813");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RP_F",
+            asm: "sqrt.rp.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rp_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0814").unwrap();
+    assert_eq!(target.id, "sqrt_rp_ftz_f32");
+    assert_eq!(target.abi_id, "i0814");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RP_FTZ_F",
+            asm: "sqrt.rp.ftz.f32 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rn_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0815").unwrap();
+    assert_eq!(target.id, "sqrt_rn_f64");
+    assert_eq!(target.abi_id, "i0815");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RN_D",
+            asm: "sqrt.rn.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rz_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0816").unwrap();
+    assert_eq!(target.id, "sqrt_rz_f64");
+    assert_eq!(target.abi_id, "i0816");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RZ_D",
+            asm: "sqrt.rz.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rm_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0817").unwrap();
+    assert_eq!(target.id, "sqrt_rm_f64");
+    assert_eq!(target.abi_id, "i0817");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RM_D",
+            asm: "sqrt.rm.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn sqrt_rp_f64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0818").unwrap();
+    assert_eq!(target.id, "sqrt_rp_f64");
+    assert_eq!(target.abi_id, "i0818");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_NVVM_SQRT_RP_D",
+            asm: "sqrt.rp.f64 \t$dst, $src0;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn ex2_approx_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0819").unwrap();
+    assert_eq!(target.id, "ex2_approx_f32");
+    assert_eq!(target.abi_id, "i0819");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn ex2_approx_ftz_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0820").unwrap();
+    assert_eq!(target.id, "ex2_approx_ftz_f32");
+    assert_eq!(target.abi_id, "i0820");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
+
+#[test]
+fn tanh_approx_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0821").unwrap();
+    assert_eq!(target.id, "tanh_approx_f32");
+    assert_eq!(target.abi_id, "i0821");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn ex2_approx_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1016").unwrap();
+    assert_eq!(target.id, "ex2_approx_f16");
+    assert_eq!(target.abi_id, "i1016");
+    assert_eq!(target.dialect_op, "nvvm.scalar_math");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 70);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(75)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(target.llvm.unwrap().properties, &["IntrNoMem"] as &[&str]);
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs
new file mode 100644
index 0000000000..11e67d007b
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs
@@ -0,0 +1,9374 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `sparse_mma` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn mma_sp_m16n8k32_s32_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0163").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k32_s32_s8");
+    assert_eq!(target.abi_id, "i0163");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19958",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k32_s32_s8_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0164").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k32_s32_s8_u8");
+    assert_eq!(target.abi_id, "i0164");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19963",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k32_s32_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0165").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k32_s32_u8");
+    assert_eq!(target.abi_id, "i0165");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19972",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k32_s32_u8_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0166").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k32_s32_u8_s8");
+    assert_eq!(target.abi_id, "i0166");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19968",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k32_s32_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0167").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k32_s32_s8_satfinite");
+    assert_eq!(target.abi_id, "i0167");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20019",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k32_s32_s8_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0168").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k32_s32_s8_u8_satfinite");
+    assert_eq!(target.abi_id, "i0168");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20022",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k32_s32_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0169").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k32_s32_u8_satfinite");
+    assert_eq!(target.abi_id, "i0169");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20028",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k32_s32_u8_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0170").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k32_s32_u8_s8_satfinite");
+    assert_eq!(target.abi_id, "i0170");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20025",
+            asm: "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0171").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_s32_s8");
+    assert_eq!(target.abi_id, "i0171");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20168",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0172").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8");
+    assert_eq!(target.abi_id, "i0172");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20173",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0173").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_s32_u8");
+    assert_eq!(target.abi_id, "i0173");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20182",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0174").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8");
+    assert_eq!(target.abi_id, "i0174");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20178",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0175").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0175");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20229",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0176").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0176");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20232",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0177").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0177");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20238",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0178").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0178");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k32,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20235",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0179").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_s8");
+    assert_eq!(target.abi_id, "i0179");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20188",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0180").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8");
+    assert_eq!(target.abi_id, "i0180");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20193",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0181").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_u8");
+    assert_eq!(target.abi_id, "i0181");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20202",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0182").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8");
+    assert_eq!(target.abi_id, "i0182");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20198",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0183").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0183");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20241",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0184").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0184");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20244",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0185").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0185");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20250",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0186").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0186");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20247",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0187").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_s8");
+    assert_eq!(target.abi_id, "i0187");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19978",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_s8_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0188").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_s8_u8");
+    assert_eq!(target.abi_id, "i0188");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19983",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_u8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0189").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_u8");
+    assert_eq!(target.abi_id, "i0189");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19992",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_u8_s8_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0190").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_u8_s8");
+    assert_eq!(target.abi_id, "i0190");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19988",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0191").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_s8_satfinite");
+    assert_eq!(target.abi_id, "i0191");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20031",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_s8_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0192").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_s8_u8_satfinite");
+    assert_eq!(target.abi_id, "i0192");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20034",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_u8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0193").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_u8_satfinite");
+    assert_eq!(target.abi_id, "i0193");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::U8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20040",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_u8_s8_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0194").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_u8_s8_satfinite");
+    assert_eq!(target.abi_id, "i0194");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U8,
+            b_element: GeneratedSparseMmaElement::S8,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20037",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0195").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_s4");
+    assert_eq!(target.abi_id, "i0195");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20124",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0196").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4");
+    assert_eq!(target.abi_id, "i0196");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20129",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0197").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_u4");
+    assert_eq!(target.abi_id, "i0197");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20138",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0198").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4");
+    assert_eq!(target.abi_id, "i0198");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20134",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0199").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0199");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20205",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0200").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0200");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20208",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0201").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0201");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20214",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0202").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0202");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20211",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0203").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k128_s32_s4");
+    assert_eq!(target.abi_id, "i0203");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20146",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0204").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4");
+    assert_eq!(target.abi_id, "i0204");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20151",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0205").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k128_s32_u4");
+    assert_eq!(target.abi_id, "i0205");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20160",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0206").unwrap();
+    assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4");
+    assert_eq!(target.abi_id, "i0206");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20156",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0207").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0207");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20217",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0208").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0208");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20220",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0209").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0209");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20226",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0210").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
+    );
+    assert_eq!(target.abi_id, "i0210");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 85);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(85),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20223",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 85"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0211").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_s4");
+    assert_eq!(target.abi_id, "i0211");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19914",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_s4_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0212").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_s4_u4");
+    assert_eq!(target.abi_id, "i0212");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19919",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0213").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_u4");
+    assert_eq!(target.abi_id, "i0213");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19928",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_u4_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0214").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_u4_s4");
+    assert_eq!(target.abi_id, "i0214");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19924",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0215").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_s4_satfinite");
+    assert_eq!(target.abi_id, "i0215");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19995",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_s4_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0216").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_s4_u4_satfinite");
+    assert_eq!(target.abi_id, "i0216");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19998",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0217").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_u4_satfinite");
+    assert_eq!(target.abi_id, "i0217");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20004",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k64_s32_u4_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0218").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k64_s32_u4_s4_satfinite");
+    assert_eq!(target.abi_id, "i0218");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20001",
+            asm: "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg9>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg9,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k128_s32_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0219").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k128_s32_s4");
+    assert_eq!(target.abi_id, "i0219");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19936",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k128_s32_s4_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0220").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k128_s32_s4_u4");
+    assert_eq!(target.abi_id, "i0220");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19941",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k128_s32_u4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0221").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k128_s32_u4");
+    assert_eq!(target.abi_id, "i0221");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19950",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k128_s32_u4_s4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0222").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k128_s32_u4_s4");
+    assert_eq!(target.abi_id, "i0222");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Wrapping,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_19946",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k128_s32_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0223").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k128_s32_s4_satfinite");
+    assert_eq!(target.abi_id, "i0223");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20007",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k128_s32_s4_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0224").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k128_s32_s4_u4_satfinite");
+    assert_eq!(target.abi_id, "i0224");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::S4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20010",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k128_s32_u4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0225").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k128_s32_u4_satfinite");
+    assert_eq!(target.abi_id, "i0225");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::U4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20016",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_m16n8k128_s32_u4_s4_satfinite_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0226").unwrap();
+    assert_eq!(target.id, "mma_sp_m16n8k128_s32_u4_s4_satfinite");
+    assert_eq!(target.abi_id, "i0226");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k128,
+            accumulator: GeneratedSparseMmaAccumulator::S32,
+            a_element: GeneratedSparseMmaElement::U4,
+            b_element: GeneratedSparseMmaElement::S4,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::Satfinite,
+            metadata: GeneratedSparseMmaMetadata::Standard,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 71);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(71),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20013",
+            asm: "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 80",
+                "Subtarget->getPTXVersion() >= 71"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0227").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
+    );
+    assert_eq!(target.abi_id, "i0227");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20464",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0228").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
+    );
+    assert_eq!(target.abi_id, "i0228");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20456",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0229").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
+    );
+    assert_eq!(target.abi_id, "i0229");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20448",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0230").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
+    );
+    assert_eq!(target.abi_id, "i0230");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20432",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0231").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
+    );
+    assert_eq!(target.abi_id, "i0231");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20440",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0232").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
+    );
+    assert_eq!(target.abi_id, "i0232");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20423",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0233").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
+    );
+    assert_eq!(target.abi_id, "i0233");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20415",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0234").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
+    );
+    assert_eq!(target.abi_id, "i0234");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20407",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0235").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
+    );
+    assert_eq!(target.abi_id, "i0235");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20391",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0236").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
+    );
+    assert_eq!(target.abi_id, "i0236");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20399",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0237").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
+    );
+    assert_eq!(target.abi_id, "i0237");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20382",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0238").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
+    );
+    assert_eq!(target.abi_id, "i0238");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20374",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0239").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
+    );
+    assert_eq!(target.abi_id, "i0239");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20366",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0240").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
+    );
+    assert_eq!(target.abi_id, "i0240");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20350",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0241").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
+    );
+    assert_eq!(target.abi_id, "i0241");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20358",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0242").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
+    );
+    assert_eq!(target.abi_id, "i0242");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20300",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0243").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
+    );
+    assert_eq!(target.abi_id, "i0243");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20291",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0244").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
+    );
+    assert_eq!(target.abi_id, "i0244");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20282",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0245").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
+    );
+    assert_eq!(target.abi_id, "i0245");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20264",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0246").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
+    );
+    assert_eq!(target.abi_id, "i0246");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20273",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0247").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
+    );
+    assert_eq!(target.abi_id, "i0247");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20341",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0248").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
+    );
+    assert_eq!(target.abi_id, "i0248");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20333",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0249").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
+    );
+    assert_eq!(target.abi_id, "i0249");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20325",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0250").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
+    );
+    assert_eq!(target.abi_id, "i0250");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20309",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0251").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
+    );
+    assert_eq!(target.abi_id, "i0251");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F32,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20317",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg13>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg13,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0525").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
+    );
+    assert_eq!(target.abi_id, "i0525");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20460",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0526").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
+    );
+    assert_eq!(target.abi_id, "i0526");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20452",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0527").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
+    );
+    assert_eq!(target.abi_id, "i0527");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20444",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0528").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
+    );
+    assert_eq!(target.abi_id, "i0528");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20428",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0529").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
+    );
+    assert_eq!(target.abi_id, "i0529");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m1,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20436",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0530").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
+    );
+    assert_eq!(target.abi_id, "i0530");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20419",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0531").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
+    );
+    assert_eq!(target.abi_id, "i0531");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20411",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0532").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
+    );
+    assert_eq!(target.abi_id, "i0532");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20403",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0533").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
+    );
+    assert_eq!(target.abi_id, "i0533");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20387",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0534").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
+    );
+    assert_eq!(target.abi_id, "i0534");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E2m3,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20395",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0535").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
+    );
+    assert_eq!(target.abi_id, "i0535");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20378",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0536").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
+    );
+    assert_eq!(target.abi_id, "i0536");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20370",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0537").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
+    );
+    assert_eq!(target.abi_id, "i0537");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20362",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0538").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
+    );
+    assert_eq!(target.abi_id, "i0538");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20346",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0539").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
+    );
+    assert_eq!(target.abi_id, "i0539");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E3m2,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20354",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0540").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
+    );
+    assert_eq!(target.abi_id, "i0540");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20296",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0541").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
+    );
+    assert_eq!(target.abi_id, "i0541");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20287",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0542").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
+    );
+    assert_eq!(target.abi_id, "i0542");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20278",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0543").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
+    );
+    assert_eq!(target.abi_id, "i0543");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20258",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0544").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
+    );
+    assert_eq!(target.abi_id, "i0544");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E4m3,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20269",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0545").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
+    );
+    assert_eq!(target.abi_id, "i0545");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E2m1,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20337",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0546").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
+    );
+    assert_eq!(target.abi_id, "i0546");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E2m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20329",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0547").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
+    );
+    assert_eq!(target.abi_id, "i0547");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E3m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20321",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0548").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
+    );
+    assert_eq!(target.abi_id, "i0548");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E4m3,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20305",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0549").unwrap();
+    assert_eq!(
+        target.id,
+        "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
+    );
+    assert_eq!(target.abi_id, "i0549");
+    assert_eq!(target.dialect_op, "nvvm.sparse_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::SparseMma {
+            shape: GeneratedSparseMmaShape::M16n8k64,
+            accumulator: GeneratedSparseMmaAccumulator::F16,
+            a_element: GeneratedSparseMmaElement::E5m2,
+            b_element: GeneratedSparseMmaElement::E5m2,
+            a_layout: GeneratedSparseMmaLayout::Row,
+            b_layout: GeneratedSparseMmaLayout::Col,
+            overflow: GeneratedSparseMmaOverflow::NotApplicable,
+            metadata: GeneratedSparseMmaMetadata::Ordered,
+            selector: GeneratedSparseMmaSelector::ImmediateZero
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 87);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_20313",
+            asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;",
+            predicates: &["Subtarget->hasMMABlockScale()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg11>",
+            "IntrNoCallback",
+            "IntrNoMem",
+            "Range<arg11,0,1>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs
new file mode 100644
index 0000000000..d1a2ae2d05
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs
@@ -0,0 +1,1813 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `sreg` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn thread_idx_x_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0001").unwrap();
+    assert_eq!(target.id, "thread_idx_x");
+    assert_eq!(target.abi_id, "i0001");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_tid_x");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_TID_x",
+            asm: "mov.u32 \t$d, %tid.x;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,1024>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn block_idx_x_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0002").unwrap();
+    assert_eq!(target.id, "block_idx_x");
+    assert_eq!(target.abi_id, "i0002");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ctaid_x");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CTAID_x",
+            asm: "mov.u32 \t$d, %ctaid.x;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,2147483647>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn block_dim_x_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0003").unwrap();
+    assert_eq!(target.id, "block_dim_x");
+    assert_eq!(target.abi_id, "i0003");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ntid_x");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NTID_x",
+            asm: "mov.u32 \t$d, %ntid.x;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,1025>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn grid_dim_x_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0004").unwrap();
+    assert_eq!(target.id, "grid_dim_x");
+    assert_eq!(target.abi_id, "i0004");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nctaid_x");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCTAID_x",
+            asm: "mov.u32 \t$d, %nctaid.x;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,2147483648>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn thread_idx_y_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0005").unwrap();
+    assert_eq!(target.id, "thread_idx_y");
+    assert_eq!(target.abi_id, "i0005");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_tid_y");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_TID_y",
+            asm: "mov.u32 \t$d, %tid.y;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,1024>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn block_idx_y_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0006").unwrap();
+    assert_eq!(target.id, "block_idx_y");
+    assert_eq!(target.abi_id, "i0006");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ctaid_y");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CTAID_y",
+            asm: "mov.u32 \t$d, %ctaid.y;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,65535>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn block_dim_y_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0007").unwrap();
+    assert_eq!(target.id, "block_dim_y");
+    assert_eq!(target.abi_id, "i0007");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ntid_y");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NTID_y",
+            asm: "mov.u32 \t$d, %ntid.y;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,1025>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn grid_dim_y_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0008").unwrap();
+    assert_eq!(target.id, "grid_dim_y");
+    assert_eq!(target.abi_id, "i0008");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nctaid_y");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCTAID_y",
+            asm: "mov.u32 \t$d, %nctaid.y;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,65536>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn thread_idx_z_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0009").unwrap();
+    assert_eq!(target.id, "thread_idx_z");
+    assert_eq!(target.abi_id, "i0009");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_tid_z");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_TID_z",
+            asm: "mov.u32 \t$d, %tid.z;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,64>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn block_idx_z_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0010").unwrap();
+    assert_eq!(target.id, "block_idx_z");
+    assert_eq!(target.abi_id, "i0010");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ctaid_z");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CTAID_z",
+            asm: "mov.u32 \t$d, %ctaid.z;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,65535>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn block_dim_z_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0011").unwrap();
+    assert_eq!(target.id, "block_dim_z");
+    assert_eq!(target.abi_id, "i0011");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_ntid_z");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NTID_z",
+            asm: "mov.u32 \t$d, %ntid.z;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,65>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn grid_dim_z_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0012").unwrap();
+    assert_eq!(target.id, "grid_dim_z");
+    assert_eq!(target.abi_id, "i0012");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nctaid_z");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCTAID_z",
+            asm: "mov.u32 \t$d, %nctaid.z;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,65536>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn lane_id_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0016").unwrap();
+    assert_eq!(target.id, "lane_id");
+    assert_eq!(target.abi_id, "i0016");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_laneid");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 13);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "SREG_LANEID",
+            asm: "mov.u32 \t$d, %laneid;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,32>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn lanemask_lt_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0035").unwrap();
+    assert_eq!(target.id, "lanemask_lt");
+    assert_eq!(target.abi_id, "i0035");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_lanemask_lt");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_LANEMASK_LT",
+            asm: "mov.u32 \t$d, %lanemask_lt;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn lanemask_le_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0036").unwrap();
+    assert_eq!(target.id, "lanemask_le");
+    assert_eq!(target.abi_id, "i0036");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_lanemask_le");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_LANEMASK_LE",
+            asm: "mov.u32 \t$d, %lanemask_le;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn lanemask_eq_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0037").unwrap();
+    assert_eq!(target.id, "lanemask_eq");
+    assert_eq!(target.abi_id, "i0037");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_lanemask_eq");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_LANEMASK_EQ",
+            asm: "mov.u32 \t$d, %lanemask_eq;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn lanemask_ge_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0038").unwrap();
+    assert_eq!(target.id, "lanemask_ge");
+    assert_eq!(target.abi_id, "i0038");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_lanemask_ge");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_LANEMASK_GE",
+            asm: "mov.u32 \t$d, %lanemask_ge;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn lanemask_gt_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0039").unwrap();
+    assert_eq!(target.id, "lanemask_gt");
+    assert_eq!(target.abi_id, "i0039");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_lanemask_gt");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_LANEMASK_GT",
+            asm: "mov.u32 \t$d, %lanemask_gt;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_block_idx_x_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0263").unwrap();
+    assert_eq!(target.id, "cluster_block_idx_x");
+    assert_eq!(target.abi_id, "i0263");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_ctaid_x");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_CTAID_x",
+            asm: "mov.u32 \t$d, %cluster_ctaid.x;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,2147483647>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_block_idx_y_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0264").unwrap();
+    assert_eq!(target.id, "cluster_block_idx_y");
+    assert_eq!(target.abi_id, "i0264");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_ctaid_y");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_CTAID_y",
+            asm: "mov.u32 \t$d, %cluster_ctaid.y;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,65535>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_block_idx_z_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0265").unwrap();
+    assert_eq!(target.id, "cluster_block_idx_z");
+    assert_eq!(target.abi_id, "i0265");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_ctaid_z");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_CTAID_z",
+            asm: "mov.u32 \t$d, %cluster_ctaid.z;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,65535>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_dim_x_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0266").unwrap();
+    assert_eq!(target.id, "cluster_dim_x");
+    assert_eq!(target.abi_id, "i0266");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_nctaid_x");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_NCTAID_x",
+            asm: "mov.u32 \t$d, %cluster_nctaid.x;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,2147483648>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_dim_y_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0267").unwrap();
+    assert_eq!(target.id, "cluster_dim_y");
+    assert_eq!(target.abi_id, "i0267");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_nctaid_y");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_NCTAID_y",
+            asm: "mov.u32 \t$d, %cluster_nctaid.y;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,65536>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_dim_z_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0268").unwrap();
+    assert_eq!(target.id, "cluster_dim_z");
+    assert_eq!(target.abi_id, "i0268");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_nctaid_z");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_NCTAID_z",
+            asm: "mov.u32 \t$d, %cluster_nctaid.z;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,65536>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_idx_x_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0269").unwrap();
+    assert_eq!(target.id, "cluster_idx_x");
+    assert_eq!(target.abi_id, "i0269");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_clusterid_x");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTERID_x",
+            asm: "mov.u32 \t$d, %clusterid.x;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,2147483647>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_idx_y_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0270").unwrap();
+    assert_eq!(target.id, "cluster_idx_y");
+    assert_eq!(target.abi_id, "i0270");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_clusterid_y");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTERID_y",
+            asm: "mov.u32 \t$d, %clusterid.y;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,65535>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_idx_z_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0271").unwrap();
+    assert_eq!(target.id, "cluster_idx_z");
+    assert_eq!(target.abi_id, "i0271");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_clusterid_z");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTERID_z",
+            asm: "mov.u32 \t$d, %clusterid.z;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,0,65535>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_grid_dim_x_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0272").unwrap();
+    assert_eq!(target.id, "cluster_grid_dim_x");
+    assert_eq!(target.abi_id, "i0272");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nclusterid_x");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCLUSTERID_x",
+            asm: "mov.u32 \t$d, %nclusterid.x;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,2147483648>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_grid_dim_y_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0273").unwrap();
+    assert_eq!(target.id, "cluster_grid_dim_y");
+    assert_eq!(target.abi_id, "i0273");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nclusterid_y");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCLUSTERID_y",
+            asm: "mov.u32 \t$d, %nclusterid.y;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,65536>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_grid_dim_z_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0274").unwrap();
+    assert_eq!(target.id, "cluster_grid_dim_z");
+    assert_eq!(target.abi_id, "i0274");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nclusterid_z");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_NCLUSTERID_z",
+            asm: "mov.u32 \t$d, %nclusterid.z;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrNoMem",
+            "IntrSpeculatable",
+            "NoUndef<ret>",
+            "Range<ret,1,65536>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_block_rank_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0275").unwrap();
+    assert_eq!(target.id, "cluster_block_rank");
+    assert_eq!(target.abi_id, "i0275");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_ctarank");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_CTARANK",
+            asm: "mov.u32 \t$d, %cluster_ctarank;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn cluster_block_count_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0276").unwrap();
+    assert_eq!(target.id, "cluster_block_count");
+    assert_eq!(target.abi_id, "i0276");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_cluster_nctarank");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_CLUSTER_NCTARANK",
+            asm: "mov.u32 \t$d, %cluster_nctarank;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 78"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn clock_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0283").unwrap();
+    assert_eq!(target.id, "clock");
+    assert_eq!(target.abi_id, "i0283");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_clock");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "SREG_CLOCK",
+            asm: "mov.u32 \t$d, %clock;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback",
+            "IntrNoFree",
+            "IntrWillReturn",
+            "NoUndef<ret>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn clock64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0284").unwrap();
+    assert_eq!(target.id, "clock64");
+    assert_eq!(target.abi_id, "i0284");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_clock64");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "SREG_CLOCK64",
+            asm: "mov.u64 \t$d, %clock64;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback",
+            "IntrNoFree",
+            "IntrWillReturn",
+            "NoUndef<ret>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn globaltimer_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0285").unwrap();
+    assert_eq!(target.id, "globaltimer");
+    assert_eq!(target.abi_id, "i0285");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_globaltimer");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 31);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(31),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "SREG_GLOBALTIMER",
+            asm: "mov.u64 \t$d, %globaltimer;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback",
+            "IntrNoFree",
+            "IntrWillReturn",
+            "NoUndef<ret>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn envreg1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0286").unwrap();
+    assert_eq!(target.id, "envreg1");
+    assert_eq!(target.abi_id, "i0286");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_envreg1");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 21);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(21),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn envreg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0287").unwrap();
+    assert_eq!(target.id, "envreg2");
+    assert_eq!(target.abi_id, "i0287");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_envreg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 21);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(21),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn smid_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0288").unwrap();
+    assert_eq!(target.id, "smid");
+    assert_eq!(target.abi_id, "i0288");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_smid");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 13);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(13),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "SREG_SMID",
+            asm: "mov.u32 \t$d, %smid;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn nsmid_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0289").unwrap();
+    assert_eq!(target.id, "nsmid");
+    assert_eq!(target.abi_id, "i0289");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nsmid");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "SREG_NSMID",
+            asm: "mov.u32 \t$d, %nsmid;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn gridid_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0290").unwrap();
+    assert_eq!(target.id, "gridid");
+    assert_eq!(target.abi_id, "i0290");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_gridid");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 30);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(30),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn warpid_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0291").unwrap();
+    assert_eq!(target.id, "warpid");
+    assert_eq!(target.abi_id, "i0291");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_warpid");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 13);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(13),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "SREG_WARPID",
+            asm: "mov.u32 \t$d, %warpid;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn nwarpid_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0292").unwrap();
+    assert_eq!(target.id, "nwarpid");
+    assert_eq!(target.abi_id, "i0292");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_nwarpid");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(20),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "SREG_NWARPID",
+            asm: "mov.u32 \t$d, %nwarpid;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn dynamic_smem_size_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0293").unwrap();
+    assert_eq!(target.id, "dynamic_smem_size");
+    assert_eq!(target.abi_id, "i0293");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_dynamic_smem_size");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 41);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(41),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(41),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_DYNAMIC_SMEM_SIZE",
+            asm: "mov.u32 \t$d, %dynamic_smem_size;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
+
+#[test]
+fn total_smem_size_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0294").unwrap();
+    assert_eq!(target.id, "total_smem_size");
+    assert_eq!(target.abi_id, "i0294");
+    assert_eq!(target.dialect_op, "nvvm.read_ptx_sreg_total_smem_size");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 41);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(41),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(41),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_PTX_SREG_TOTAL_SMEM_SIZE",
+            asm: "mov.u32 \t$d, %total_smem_size;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoMem", "IntrSpeculatable", "NoUndef<ret>"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs
new file mode 100644
index 0000000000..e0b9d2e962
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs
@@ -0,0 +1,216 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `stmatrix` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn stmatrix_m8n8_x2_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0301").unwrap();
+    assert_eq!(target.id, "stmatrix_m8n8_x2_b16");
+    assert_eq!(target.abi_id, "i0301");
+    assert_eq!(target.dialect_op, "nvvm.stmatrix_m8n8_x2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrWriteMem",
+            "NoCapture<arg0>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn stmatrix_m8n8_x2_trans_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0302").unwrap();
+    assert_eq!(target.id, "stmatrix_m8n8_x2_trans_b16");
+    assert_eq!(target.abi_id, "i0302");
+    assert_eq!(target.dialect_op, "nvvm.stmatrix_m8n8_x2_trans");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrWriteMem",
+            "NoCapture<arg0>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn stmatrix_m8n8_x4_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0303").unwrap();
+    assert_eq!(target.id, "stmatrix_m8n8_x4_b16");
+    assert_eq!(target.abi_id, "i0303");
+    assert_eq!(target.dialect_op, "nvvm.stmatrix_m8n8_x4");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrWriteMem",
+            "NoCapture<arg0>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn stmatrix_m8n8_x4_trans_b16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0304").unwrap();
+    assert_eq!(target.id, "stmatrix_m8n8_x4_trans_b16");
+    assert_eq!(target.abi_id, "i0304");
+    assert_eq!(target.dialect_op, "nvvm.stmatrix_m8n8_x4_trans");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 78);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(78),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "IntrNoCallback",
+            "IntrWriteMem",
+            "NoCapture<arg0>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs
new file mode 100644
index 0000000000..87ea83763d
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs
@@ -0,0 +1,232 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `sync` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn sync_threads_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0034").unwrap();
+    assert_eq!(target.id, "sync_threads");
+    assert_eq!(target.abi_id, "i0034");
+    assert_eq!(target.dialect_op, "nvvm.barrier0");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 10);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(10),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "BARRIER_CTA_SYNC_ALIGNED_ALL_i",
+            asm: "bar.sync \t$i;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn threadfence_block_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0298").unwrap();
+    assert_eq!(target.id, "threadfence_block");
+    assert_eq!(target.abi_id, "i0298");
+    assert_eq!(target.dialect_op, "nvvm.threadfence_block");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 14);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_MEMBAR_CTA",
+            asm: "membar.cta;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn threadfence_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0299").unwrap();
+    assert_eq!(target.id, "threadfence");
+    assert_eq!(target.abi_id, "i0299");
+    assert_eq!(target.dialect_op, "nvvm.threadfence");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 14);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::All }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_MEMBAR_GL",
+            asm: "membar.gl;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn threadfence_system_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0300").unwrap();
+    assert_eq!(target.id, "threadfence_system");
+    assert_eq!(target.abi_id, "i0300");
+    assert_eq!(target.dialect_op, "nvvm.threadfence_system");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 20);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(20)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(32),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(20),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(70),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(80),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_MEMBAR_SYS",
+            asm: "membar.sys;",
+            predicates: &[],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs
new file mode 100644
index 0000000000..f372d0b161
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs
@@ -0,0 +1,2468 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `tcgen05_cp` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn tcgen05_cp_128x128b_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0578").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_128x128b_b4x16_p64");
+    assert_eq!(target.abi_id, "i0578");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b_b4x16_p64");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128bb4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_128x128b_b4x16_p64_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0579").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_128x128b_b4x16_p64_cg2");
+    assert_eq!(target.abi_id, "i0579");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b_b4x16_p64_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128bb4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_128x128b_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0580").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_128x128b_b6x16_p32");
+    assert_eq!(target.abi_id, "i0580");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b_b6x16_p32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128bb6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_128x128b_b6x16_p32_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0581").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_128x128b_b6x16_p32_cg2");
+    assert_eq!(target.abi_id, "i0581");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b_b6x16_p32_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128bb6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_128x128b_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0582").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_128x128b");
+    assert_eq!(target.abi_id, "i0582");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128b_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x128b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_128x128b_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0583").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_128x128b_cg2");
+    assert_eq!(target.abi_id, "i0583");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x128b_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x128b_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x128b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_128x256b_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0584").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_128x256b_b4x16_p64");
+    assert_eq!(target.abi_id, "i0584");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x256b_b4x16_p64");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256bb4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_128x256b_b4x16_p64_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0585").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_128x256b_b4x16_p64_cg2");
+    assert_eq!(target.abi_id, "i0585");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x256b_b4x16_p64_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256bb4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_128x256b_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0586").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_128x256b_b6x16_p32");
+    assert_eq!(target.abi_id, "i0586");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x256b_b6x16_p32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256bb6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_128x256b_b6x16_p32_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0587").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_128x256b_b6x16_p32_cg2");
+    assert_eq!(target.abi_id, "i0587");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_128x256b_b6x16_p32_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256bb6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_32x128b_warpx4_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0588").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4_b4x16_p64");
+    assert_eq!(target.abi_id, "i0588");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_32x128b_warpx4_b4x16_p64"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128b4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0589").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2");
+    assert_eq!(target.abi_id, "i0589");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128b4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_32x128b_warpx4_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0590").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4_b6x16_p32");
+    assert_eq!(target.abi_id, "i0590");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_32x128b_warpx4_b6x16_p32"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128b6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0591").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2");
+    assert_eq!(target.abi_id, "i0591");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128b6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_32x128b_warpx4_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0592").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4");
+    assert_eq!(target.abi_id, "i0592");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_32x128b_warpx4");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128_cg1",
+            asm: "tcgen05.cp.cta_group::1.32x128b.warpx4 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_32x128b_warpx4_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0593").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_32x128b_warpx4_cg2");
+    assert_eq!(target.abi_id, "i0593");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_32x128b_warpx4_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_32x128_cg2",
+            asm: "tcgen05.cp.cta_group::2.32x128b.warpx4 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_4x256b_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0594").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_4x256b_b4x16_p64");
+    assert_eq!(target.abi_id, "i0594");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b_b4x16_p64");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256bb4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_4x256b_b4x16_p64_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0595").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_4x256b_b4x16_p64_cg2");
+    assert_eq!(target.abi_id, "i0595");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b_b4x16_p64_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256bb4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_4x256b_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0596").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_4x256b_b6x16_p32");
+    assert_eq!(target.abi_id, "i0596");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b_b6x16_p32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256bb6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_4x256b_b6x16_p32_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0597").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_4x256b_b6x16_p32_cg2");
+    assert_eq!(target.abi_id, "i0597");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b_b6x16_p32_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256bb6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_4x256b_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0598").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_4x256b");
+    assert_eq!(target.abi_id, "i0598");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256b_cg1",
+            asm: "tcgen05.cp.cta_group::1.4x256b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_4x256b_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0599").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_4x256b_cg2");
+    assert_eq!(target.abi_id, "i0599");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_4x256b_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_4x256b_cg2",
+            asm: "tcgen05.cp.cta_group::2.4x256b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0600").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64");
+    assert_eq!(target.abi_id, "i0600");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2b4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0601").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2");
+    assert_eq!(target.abi_id, "i0601");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2b4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0602").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32");
+    assert_eq!(target.abi_id, "i0602");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2b6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0603").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2");
+    assert_eq!(target.abi_id, "i0603");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2b6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0604").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23");
+    assert_eq!(target.abi_id, "i0604");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_64x128b_warpx2_01_23");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0605").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_01_23_cg2");
+    assert_eq!(target.abi_id, "i0605");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_64x128b_warpx2_01_23_cg2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_2_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0606").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64");
+    assert_eq!(target.abi_id, "i0606");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1b4x16_p64_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0607").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2");
+    assert_eq!(target.abi_id, "i0607");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1b4x16_p64_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0608").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32");
+    assert_eq!(target.abi_id, "i0608");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1b6x16_p32_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0609").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2");
+    assert_eq!(target.abi_id, "i0609");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1b6x16_p32_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0610").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13");
+    assert_eq!(target.abi_id, "i0610");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_64x128b_warpx2_02_13");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1_cg1",
+            asm: "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0611").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_64x128b_warpx2_02_13_cg2");
+    assert_eq!(target.abi_id, "i0611");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_cp_64x128b_warpx2_02_13_cg2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_64x128_1_cg2",
+            asm: "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs
new file mode 100644
index 0000000000..f5e3550a03
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs
@@ -0,0 +1,4542 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `tcgen05_ld` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn tcgen05_ld_16x64b_x1_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0612").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x1_raw");
+    assert_eq!(target.abi_id, "i0612");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x1_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x1_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0613").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x1_pack16");
+    assert_eq!(target.abi_id, "i0613");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x1_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x2_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0614").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x2_raw");
+    assert_eq!(target.abi_id, "i0614");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x2_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x2_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0615").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x2_pack16");
+    assert_eq!(target.abi_id, "i0615");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x2_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x4_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0616").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x4_raw");
+    assert_eq!(target.abi_id, "i0616");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x4_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x4_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0617").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x4_pack16");
+    assert_eq!(target.abi_id, "i0617");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x4_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x8_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0618").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x8_raw");
+    assert_eq!(target.abi_id, "i0618");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x8_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x8_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0619").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x8_pack16");
+    assert_eq!(target.abi_id, "i0619");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x8_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x16_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0620").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x16_raw");
+    assert_eq!(target.abi_id, "i0620");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x16_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x16_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0621").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x16_pack16");
+    assert_eq!(target.abi_id, "i0621");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x16_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x32_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0622").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x32_raw");
+    assert_eq!(target.abi_id, "i0622");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x32_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x32_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0623").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x32_pack16");
+    assert_eq!(target.abi_id, "i0623");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x32_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x64_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0624").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x64_raw");
+    assert_eq!(target.abi_id, "i0624");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x64_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x64_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0625").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x64_pack16");
+    assert_eq!(target.abi_id, "i0625");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x64_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x128_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0626").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x128_raw");
+    assert_eq!(target.abi_id, "i0626");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x128_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x64b_x128_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0627").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x64b_x128_pack16");
+    assert_eq!(target.abi_id, "i0627");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x64b_x128_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x1_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0628").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x1_raw");
+    assert_eq!(target.abi_id, "i0628");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x1_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x1_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0629").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x1_pack16");
+    assert_eq!(target.abi_id, "i0629");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x1_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x2_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0630").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x2_raw");
+    assert_eq!(target.abi_id, "i0630");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x2_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x2_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0631").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x2_pack16");
+    assert_eq!(target.abi_id, "i0631");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x2_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x4_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0632").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x4_raw");
+    assert_eq!(target.abi_id, "i0632");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x4_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x4_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0633").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x4_pack16");
+    assert_eq!(target.abi_id, "i0633");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x4_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x8_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0634").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x8_raw");
+    assert_eq!(target.abi_id, "i0634");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x8_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x8_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0635").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x8_pack16");
+    assert_eq!(target.abi_id, "i0635");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x8_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x16_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0636").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x16_raw");
+    assert_eq!(target.abi_id, "i0636");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x16_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x16_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0637").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x16_pack16");
+    assert_eq!(target.abi_id, "i0637");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x16_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x32_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0638").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x32_raw");
+    assert_eq!(target.abi_id, "i0638");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x32_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x32_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0639").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x32_pack16");
+    assert_eq!(target.abi_id, "i0639");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x32_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x64_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0640").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x64_raw");
+    assert_eq!(target.abi_id, "i0640");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x64_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x128b_x64_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0641").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x128b_x64_pack16");
+    assert_eq!(target.abi_id, "i0641");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x128b_x64_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x1_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0642").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x1_raw");
+    assert_eq!(target.abi_id, "i0642");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x1_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x1_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0643").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x1_pack16");
+    assert_eq!(target.abi_id, "i0643");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x1_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x2_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0644").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x2_raw");
+    assert_eq!(target.abi_id, "i0644");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x2_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x2_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0645").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x2_pack16");
+    assert_eq!(target.abi_id, "i0645");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x2_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x4_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0646").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x4_raw");
+    assert_eq!(target.abi_id, "i0646");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x4_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x4_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0647").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x4_pack16");
+    assert_eq!(target.abi_id, "i0647");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x4_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x8_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0648").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x8_raw");
+    assert_eq!(target.abi_id, "i0648");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x8_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x8_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0649").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x8_pack16");
+    assert_eq!(target.abi_id, "i0649");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x8_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x16_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0650").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x16_raw");
+    assert_eq!(target.abi_id, "i0650");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x16_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x16_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0651").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x16_pack16");
+    assert_eq!(target.abi_id, "i0651");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x16_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x32_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0652").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x32_raw");
+    assert_eq!(target.abi_id, "i0652");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x32_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x32_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0653").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x32_pack16");
+    assert_eq!(target.abi_id, "i0653");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x32_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x1_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0654").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x1_raw");
+    assert_eq!(target.abi_id, "i0654");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x1_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x1_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0655").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x1_pack16");
+    assert_eq!(target.abi_id, "i0655");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x1_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x2_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0656").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x2_raw");
+    assert_eq!(target.abi_id, "i0656");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x2_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x2_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0657").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x2_pack16");
+    assert_eq!(target.abi_id, "i0657");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x2_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x4_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0658").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x4_raw");
+    assert_eq!(target.abi_id, "i0658");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x4_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x4_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0659").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x4_pack16");
+    assert_eq!(target.abi_id, "i0659");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x4_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x8_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0660").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x8_raw");
+    assert_eq!(target.abi_id, "i0660");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x8_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x8_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0661").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x8_pack16");
+    assert_eq!(target.abi_id, "i0661");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x8_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x16_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0662").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x16_raw");
+    assert_eq!(target.abi_id, "i0662");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x16_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x16_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0663").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x16_pack16");
+    assert_eq!(target.abi_id, "i0663");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x16_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x32_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0664").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x32_raw");
+    assert_eq!(target.abi_id, "i0664");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x32_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x32_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0665").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x32_pack16");
+    assert_eq!(target.abi_id, "i0665");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x32_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x64_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0666").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x64_raw");
+    assert_eq!(target.abi_id, "i0666");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x64_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x64_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0667").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x64_pack16");
+    assert_eq!(target.abi_id, "i0667");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x64_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x128_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0668").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x128_raw");
+    assert_eq!(target.abi_id, "i0668");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x128_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_32x32b_x128_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0669").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_32x32b_x128_pack16");
+    assert_eq!(target.abi_id, "i0669");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_32x32b_x128_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x1_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0728").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x1_raw");
+    assert_eq!(target.abi_id, "i0728");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x1_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x1_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0729").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x1_pack16");
+    assert_eq!(target.abi_id, "i0729");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x1_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x2_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0730").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x2_raw");
+    assert_eq!(target.abi_id, "i0730");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x2_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x2_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0731").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x2_pack16");
+    assert_eq!(target.abi_id, "i0731");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x2_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x4_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0732").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x4_raw");
+    assert_eq!(target.abi_id, "i0732");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x4_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x4_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0733").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x4_pack16");
+    assert_eq!(target.abi_id, "i0733");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x4_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x8_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0734").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x8_raw");
+    assert_eq!(target.abi_id, "i0734");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x8_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x8_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0735").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x8_pack16");
+    assert_eq!(target.abi_id, "i0735");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x8_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x16_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0736").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x16_raw");
+    assert_eq!(target.abi_id, "i0736");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x16_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x16_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0737").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x16_pack16");
+    assert_eq!(target.abi_id, "i0737");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x16_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x32_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0738").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x32_raw");
+    assert_eq!(target.abi_id, "i0738");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x32_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x32_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0739").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x32_pack16");
+    assert_eq!(target.abi_id, "i0739");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x32_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x64_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0740").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x64_raw");
+    assert_eq!(target.abi_id, "i0740");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x64_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x64_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0741").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x64_pack16");
+    assert_eq!(target.abi_id, "i0741");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x64_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x128_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0742").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x128_raw");
+    assert_eq!(target.abi_id, "i0742");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x128_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x32bx2_x128_pack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0743").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x32bx2_x128_pack16");
+    assert_eq!(target.abi_id, "i0743");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x32bx2_x128_pack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs
new file mode 100644
index 0000000000..02ca7d0505
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs
@@ -0,0 +1,5635 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `tcgen05_mma` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn tcgen05_mma_shared_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0763").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_shared");
+    assert_eq!(target.abi_id, "i0763");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22502",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22504",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22506",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22508",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22510",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22512",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22514",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22516",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22518",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22520",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22522",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22524",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22526",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22528",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22530",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22532",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22534",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22535",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22536",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22537",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22538",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22539",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22540",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22541",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22542",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22543",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22544",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22545",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22546",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22547",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22548",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22549",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,1,3>",
+            "Range<arg7,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_tensor_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0764").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_tensor");
+    assert_eq!(target.abi_id, "i0764");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Tensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22406",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22410",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22414",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22418",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22422",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22426",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22430",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22434",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22438",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22442",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22446",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22450",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22454",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22458",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22462",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22466",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22470",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22472",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22474",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22476",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22478",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22480",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22482",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22484",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22486",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22488",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22490",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22492",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22494",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22496",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22498",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22500",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ArgInfo<arg5>",
+            "ArgInfo<arg6>",
+            "ArgInfo<arg7>",
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,1,3>",
+            "Range<arg7,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_tensor_ashift_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0765").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_tensor_ashift");
+    assert_eq!(target.abi_id, "i0765");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::TensorAshift,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22407",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22411",
+                asm: "tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22423",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22427",
+                asm: "tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22439",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22443",
+                asm: "tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22455",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22459",
+                asm: "tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22471",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22473",
+                asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22479",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22481",
+                asm: "tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22487",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22489",
+                asm: "tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22495",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22497",
+                asm: "tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,1,3>",
+            "Range<arg7,0,2>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_sp_shared_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0766").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_sp_shared");
+    assert_eq!(target.abi_id, "i0766");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::SpShared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22646",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22648",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22650",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22652",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22654",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22656",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22658",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22660",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22662",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22664",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22666",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22668",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22670",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22672",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22674",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22676",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22678",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22679",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22680",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22681",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22682",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22683",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22684",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22685",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22686",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22687",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22688",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22689",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22690",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22691",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22692",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22693",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "IntrArgMemOnly",
+            "Range<arg6,0,4>",
+            "Range<arg7,1,3>",
+            "Range<arg8,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_sp_tensor_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0767").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_sp_tensor");
+    assert_eq!(target.abi_id, "i0767");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::SpTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22550",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22554",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22558",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22562",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22566",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22570",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22574",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22578",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22582",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22586",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22590",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22594",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22598",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22602",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22606",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22610",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22614",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22616",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22618",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22620",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22622",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22624",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22626",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22628",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22630",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22632",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22634",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22636",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22638",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22640",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22642",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22644",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "IntrArgMemOnly",
+            "Range<arg6,0,4>",
+            "Range<arg7,1,3>",
+            "Range<arg8,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_sp_tensor_ashift_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0768").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_sp_tensor_ashift");
+    assert_eq!(target.abi_id, "i0768");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::SpTensorAshift,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22551",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22555",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22567",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22571",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22583",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22587",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22599",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22603",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22615",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22617",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22623",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22625",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22631",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22633",
+                asm: "tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22639",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_22641",
+                asm: "tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse.ashift [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "IntrArgMemOnly",
+            "Range<arg6,0,4>",
+            "Range<arg7,1,3>",
+            "Range<arg8,0,2>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1011").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_e4m3");
+    assert_eq!(target.abi_id, "i1011");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22534",
+            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,1,3>",
+            "Range<arg7,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1012").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_e5m2");
+    assert_eq!(target.abi_id, "i1012");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22534",
+            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,1,3>",
+            "Range<arg7,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1013").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_e2m3");
+    assert_eq!(target.abi_id, "i1013");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22534",
+            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,1,3>",
+            "Range<arg7,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1014").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_e3m2");
+    assert_eq!(target.abi_id, "i1014");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22534",
+            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,1,3>",
+            "Range<arg7,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i1015").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_e2m1");
+    assert_eq!(target.abi_id, "i1015");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::Shared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_22534",
+            asm: "tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,1,3>",
+            "Range<arg7,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs
new file mode 100644
index 0000000000..983f77aae4
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs
@@ -0,0 +1,9867 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `tcgen05_mma_ws` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn tcgen05_mma_ws_shared_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0769").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_shared");
+    assert_eq!(target.abi_id, "i0769");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsShared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23232",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23234",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23236",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23238",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23240",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23242",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23244",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23246",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23248",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23250",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23252",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23254",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23256",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23258",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23260",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23262",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23264",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23266",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23268",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23270",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23272",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23274",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23276",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23278",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23280",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23282",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23284",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23286",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23288",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23290",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23292",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23294",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23296",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23298",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23300",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23302",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23304",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23306",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23308",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23310",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23312",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23314",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23316",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23318",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23320",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23322",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23324",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23326",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23328",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23330",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23332",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23334",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23336",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23338",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23340",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23342",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23344",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23346",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23348",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23350",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23352",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23354",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23356",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23358",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_shared_zero_col_mask_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0770").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_shared_zero_col_mask");
+    assert_eq!(target.abi_id, "i0770");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsSharedZeroColMask,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23233",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23235",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23237",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23239",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23241",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23243",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23245",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23247",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23249",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23251",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23253",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23255",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23257",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23259",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23261",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23263",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23265",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23267",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23269",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23271",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23273",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23275",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23277",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23279",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23281",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23283",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23285",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23287",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23289",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23291",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23293",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23295",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23297",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23299",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23301",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23303",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23305",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23307",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23309",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23311",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23313",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23315",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23317",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23319",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23321",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23323",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23325",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23327",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23329",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23331",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23333",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23335",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23337",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23339",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23341",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23343",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23345",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23347",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23349",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23351",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23353",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23355",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23357",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23359",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "IntrArgMemOnly",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "Range<arg8,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_sp_shared_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0771").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_sp_shared");
+    assert_eq!(target.abi_id, "i0771");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsSpShared,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23488",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23490",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23492",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23494",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23496",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23498",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23500",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23502",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23504",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23506",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23508",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23510",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23512",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23514",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23516",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23518",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23520",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23522",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23524",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23526",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23528",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23530",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23532",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23534",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23536",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23538",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23540",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23542",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23544",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23546",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23548",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23550",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23552",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23554",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23556",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23558",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23560",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23562",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23564",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23566",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23568",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23570",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23572",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23574",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23576",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23578",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23580",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23582",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23584",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23586",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23588",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23590",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23592",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23594",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23596",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23598",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23600",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23602",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23604",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23606",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23608",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23610",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23612",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23614",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "IntrArgMemOnly",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "Range<arg8,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_sp_shared_zero_col_mask_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0772").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_sp_shared_zero_col_mask");
+    assert_eq!(target.abi_id, "i0772");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsSpSharedZeroColMask,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23489",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23491",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23493",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23495",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23497",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23499",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23501",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23503",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23505",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23507",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23509",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23511",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23513",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23515",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23517",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23519",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23521",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23523",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23525",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23527",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23529",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23531",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23533",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23535",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23537",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23539",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23541",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23543",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23545",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23547",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23549",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23551",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23553",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23555",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23557",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23559",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23561",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23563",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23565",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23567",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23569",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23571",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23573",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23575",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23577",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23579",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23581",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23583",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23585",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23587",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23589",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23591",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23593",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23595",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23597",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23599",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23601",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23603",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23605",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23607",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23609",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23611",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23613",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23615",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], $a, $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "ImmArg<arg9>",
+            "IntrArgMemOnly",
+            "Range<arg7,0,4>",
+            "Range<arg8,0,4>",
+            "Range<arg9,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_sp_tensor_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0773").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_sp_tensor");
+    assert_eq!(target.abi_id, "i0773");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsSpTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23616",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23618",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23620",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23622",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23624",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23626",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23628",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23630",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23632",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23634",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23636",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23638",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23640",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23642",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23644",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23646",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23648",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23650",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23652",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23654",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23656",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23658",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23660",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23662",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23664",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23666",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23668",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23670",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23672",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23674",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23676",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23678",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23680",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23682",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23684",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23686",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23688",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23690",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23692",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23694",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23696",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23698",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23700",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23702",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23704",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23706",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23708",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23710",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23712",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23714",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23716",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23718",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23720",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23722",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23724",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23726",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23728",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23730",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23732",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23734",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23736",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23738",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23740",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23742",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "IntrArgMemOnly",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "Range<arg8,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_sp_tensor_zero_col_mask_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0774").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_sp_tensor_zero_col_mask");
+    assert_eq!(target.abi_id, "i0774");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsSpTensorZeroColMask,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23617",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23619",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23621",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23623",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23625",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23627",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23629",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23631",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23633",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23635",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23637",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23639",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23641",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23643",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23645",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23647",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23649",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23651",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23653",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23655",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23657",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23659",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23661",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23663",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23665",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23667",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23669",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23671",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23673",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23675",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23677",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23679",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23681",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23683",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23685",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23687",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23689",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23691",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23693",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23695",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23697",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23699",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23701",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23703",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23705",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23707",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23709",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23711",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23713",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23715",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23717",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23719",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23721",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23723",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23725",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23727",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23729",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23731",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23733",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23735",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23737",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23739",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23741",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23743",
+                asm: "tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, [$spmetadata], $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "ImmArg<arg9>",
+            "IntrArgMemOnly",
+            "Range<arg7,0,4>",
+            "Range<arg8,0,4>",
+            "Range<arg9,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_tensor_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0775").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_tensor");
+    assert_eq!(target.abi_id, "i0775");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23360",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23362",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23364",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23366",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23368",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23370",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23372",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23374",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23376",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23378",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23380",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23382",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23384",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23386",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23388",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23390",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23392",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23394",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23396",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23398",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23400",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23402",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23404",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23406",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23408",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23410",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23412",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23414",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23416",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23418",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23420",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23422",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23424",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23426",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23428",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23430",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23432",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23434",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23436",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23438",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23440",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23442",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23444",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23446",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23448",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23450",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23452",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23454",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23456",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23458",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23460",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23462",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23464",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23466",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23468",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23470",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23472",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23474",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23476",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23478",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23480",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23482",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23484",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23486",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_tensor_zero_col_mask_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0776").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_tensor_zero_col_mask");
+    assert_eq!(target.abi_id, "i0776");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensorZeroColMask,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: false
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f16",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "f8f6f4",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "i8",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                        ],
+                    },
+                    GeneratedTargetContract {
+                        selectors: &[GeneratedTargetSelectorBinding {
+                            name: "kind",
+                            value: "tf32",
+                        }],
+                        alternatives: &[
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                            },
+                            GeneratedTargetAlternative {
+                                minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                            },
+                        ],
+                    },
+                ],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(101),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                101,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f16",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "f8f6f4",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "i8",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                    ],
+                                },
+                                GeneratedTargetContract {
+                                    selectors: &[GeneratedTargetSelectorBinding {
+                                        name: "kind",
+                                        value: "tf32",
+                                    }],
+                                    alternatives: &[
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(100),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                100,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(103),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                103,
+                                            ),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware:
+                                                GeneratedHardwareAlternative::ExactArchitecture(110),
+                                        },
+                                        GeneratedTargetAlternative {
+                                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                            hardware: GeneratedHardwareAlternative::FamilyTarget(
+                                                110,
+                                            ),
+                                        },
+                                    ],
+                                },
+                            ],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23361",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23363",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23365",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23367",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23369",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23371",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23373",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23375",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23377",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23379",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23381",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23383",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23385",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23387",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23389",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23391",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23393",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23395",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23397",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23399",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23401",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23403",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23405",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23407",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23409",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23411",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23413",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23415",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23417",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23419",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23421",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23423",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23425",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23427",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23429",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23431",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23433",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23435",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23437",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23439",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23441",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23443",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23445",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23447",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23449",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23451",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23453",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23455",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05InstSupport()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23457",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23459",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23461",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23463",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23465",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23467",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23469",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23471",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23473",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23475",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23477",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23479",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23481",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23483",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23485",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_23487",
+                asm: "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [$dtmem], [$a], $b, $idesc, $enable_inp_d, $zero_col_mask;",
+                predicates: &["Subtarget->hasTcgen05MMAI8Kind()"],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "IntrArgMemOnly",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "Range<arg8,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_e4m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0777").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_e4m3");
+    assert_eq!(target.abi_id, "i0777");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_23424",
+            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_e5m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0778").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_e5m2");
+    assert_eq!(target.abi_id, "i0778");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_23424",
+            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_e2m3_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0779").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_e2m3");
+    assert_eq!(target.abi_id, "i0779");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_23424",
+            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_e3m2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0780").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_e3m2");
+    assert_eq!(target.abi_id, "i0780");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_23424",
+            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_e2m1_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0781").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_e2m1");
+    assert_eq!(target.abi_id, "i0781");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::Tcgen05Mma {
+            form: GeneratedTcgen05MmaForm::WsTensor,
+            target_selector: GeneratedTcgen05MmaTargetSelector::Kind,
+            compatibility_alias: true
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::TargetMatrix {
+                contracts: &[GeneratedTargetContract {
+                    selectors: &[GeneratedTargetSelectorBinding {
+                        name: "kind",
+                        value: "f8f6f4",
+                    }],
+                    alternatives: &[
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+                        },
+                        GeneratedTargetAlternative {
+                            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                        },
+                    ],
+                }],
+            }
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            101,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::TargetMatrix {
+                            contracts: &[GeneratedTargetContract {
+                                selectors: &[GeneratedTargetSelectorBinding {
+                                    name: "kind",
+                                    value: "f8f6f4",
+                                }],
+                                alternatives: &[
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            100,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            103,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::ExactArchitecture(
+                                            110,
+                                        ),
+                                    },
+                                    GeneratedTargetAlternative {
+                                        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+                                        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+                                    },
+                                ],
+                            }],
+                        },
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "anonymous_23424",
+            asm: "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [$dtmem], [$a], $b, $idesc, $enable_inp_d;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs
new file mode 100644
index 0000000000..f33b300988
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs
@@ -0,0 +1,1821 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `tcgen05_other` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn tcgen05_alloc_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0343").unwrap();
+    assert_eq!(target.id, "tcgen05_alloc");
+    assert_eq!(target.abi_id, "i0343");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_alloc");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_ALLOC_S64_CG1",
+            asm: "tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 \t[$dst], $ncols;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_dealloc_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0344").unwrap();
+    assert_eq!(target.id, "tcgen05_dealloc");
+    assert_eq!(target.abi_id, "i0344");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_dealloc");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_DEALLOC_CG1",
+            asm: "tcgen05.dealloc.cta_group::1.sync.aligned.b32 \t$tmem_addr, $ncols;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_relinquish_alloc_permit_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0345").unwrap();
+    assert_eq!(target.id, "tcgen05_relinquish_alloc_permit");
+    assert_eq!(target.abi_id, "i0345");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_relinquish_alloc_permit");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_RELINQ_CG1",
+            asm: "tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrInaccessibleMemOnly"] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_fence_before_thread_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0346").unwrap();
+    assert_eq!(target.id, "tcgen05_fence_before_thread_sync");
+    assert_eq!(target.abi_id, "i0346");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_fence_before_thread_sync");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "tcgen05_fence_before_thread_sync",
+            asm: "tcgen05.fence::before_thread_sync;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrHasSideEffects", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_fence_after_thread_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0347").unwrap();
+    assert_eq!(target.id, "tcgen05_fence_after_thread_sync");
+    assert_eq!(target.abi_id, "i0347");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_fence_after_thread_sync");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "tcgen05_fence_after_thread_sync",
+            asm: "tcgen05.fence::after_thread_sync;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrHasSideEffects", "IntrNoMem"] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_commit_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0348").unwrap();
+    assert_eq!(target.id, "tcgen05_commit");
+    assert_eq!(target.abi_id, "i0348");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_commit");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_commit_shared_cluster_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0349").unwrap();
+    assert_eq!(target.id, "tcgen05_commit_shared_cluster");
+    assert_eq!(target.abi_id, "i0349");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_commit_shared_cluster");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_COMMIT_S64_CG1",
+            asm: "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0350").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_f16");
+    assert_eq!(target.abi_id, "i0350");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma_ws_f16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_f16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0351").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_f16");
+    assert_eq!(target.abi_id, "i0351");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma_f16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_bf16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0352").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_bf16");
+    assert_eq!(target.abi_id, "i0352");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma_ws_bf16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_ws_tf32_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0353").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_ws_tf32");
+    assert_eq!(target.abi_id, "i0353");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma_ws_tf32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg5,0,4>",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "ReadOnly<arg1>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_smem_to_tmem_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0354").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_smem_to_tmem");
+    assert_eq!(target.abi_id, "i0354");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_smem_to_tmem");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256b_cg1",
+            asm: "tcgen05.cp.cta_group::1.128x256b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_x8_pure_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0355").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_x8_pure");
+    assert_eq!(target.abi_id, "i0355");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_x8_pure");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_ld_16x256b_pure_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0356").unwrap();
+    assert_eq!(target.id, "tcgen05_ld_16x256b_pure");
+    assert_eq!(target.abi_id, "i0356");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_ld_16x256b_pure");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_load_wait_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0357").unwrap();
+    assert_eq!(target.id, "tcgen05_load_wait");
+    assert_eq!(target.abi_id, "i0357");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_load_wait");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "tcgen05_wait_ld",
+            asm: "tcgen05.wait::ld.sync.aligned;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrInaccessibleMemOnly"] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_store_wait_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0358").unwrap();
+    assert_eq!(target.id, "tcgen05_store_wait");
+    assert_eq!(target.abi_id, "i0358");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_store_wait");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "tcgen05_wait_st",
+            asm: "tcgen05.wait::st.sync.aligned;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrInaccessibleMemOnly"] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_alloc_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0359").unwrap();
+    assert_eq!(target.id, "tcgen05_alloc_cg2");
+    assert_eq!(target.abi_id, "i0359");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_alloc_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_ALLOC_S64_CG2",
+            asm: "tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 \t[$dst], $ncols;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_dealloc_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0360").unwrap();
+    assert_eq!(target.id, "tcgen05_dealloc_cg2");
+    assert_eq!(target.abi_id, "i0360");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_dealloc_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_DEALLOC_CG2",
+            asm: "tcgen05.dealloc.cta_group::2.sync.aligned.b32 \t$tmem_addr, $ncols;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_relinquish_alloc_permit_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0361").unwrap();
+    assert_eq!(target.id, "tcgen05_relinquish_alloc_permit_cg2");
+    assert_eq!(target.abi_id, "i0361");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tcgen05_relinquish_alloc_permit_cg2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_RELINQ_CG2",
+            asm: "tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrInaccessibleMemOnly"] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_mma_f16_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0362").unwrap();
+    assert_eq!(target.id, "tcgen05_mma_f16_cg2");
+    assert_eq!(target.abi_id, "i0362");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_mma_f16_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "IntrArgMemOnly",
+            "Range<arg6,0,4>",
+            "Range<arg7,0,4>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_commit_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0363").unwrap();
+    assert_eq!(target.id, "tcgen05_commit_cg2");
+    assert_eq!(target.abi_id, "i0363");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_commit_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_commit_shared_cluster_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0364").unwrap();
+    assert_eq!(target.id, "tcgen05_commit_shared_cluster_cg2");
+    assert_eq!(target.abi_id, "i0364");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_commit_shared_cluster_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_COMMIT_S64_CG2",
+            asm: "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 \t[$mbar];",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_commit_multicast_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0365").unwrap();
+    assert_eq!(target.id, "tcgen05_commit_multicast_cg2");
+    assert_eq!(target.abi_id, "i0365");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_commit_multicast_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_COMMIT_S64_CG2_MC",
+            asm: "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_cp_smem_to_tmem_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0366").unwrap();
+    assert_eq!(target.id, "tcgen05_cp_smem_to_tmem_cg2");
+    assert_eq!(target.abi_id, "i0366");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_cp_smem_to_tmem_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_CP_128x256b_cg2",
+            asm: "tcgen05.cp.cta_group::2.128x256b \t[$tmem_addr], $sdesc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_commit_multicast_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0760").unwrap();
+    assert_eq!(target.id, "tcgen05_commit_multicast");
+    assert_eq!(target.abi_id, "i0760");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_commit_multicast");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_COMMIT_S64_CG1_MC",
+            asm: "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 \t[$mbar], $mc;",
+            predicates: &["Subtarget->hasTcgen05InstSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOrArgMemOnly",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_shift_down_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0761").unwrap();
+    assert_eq!(target.id, "tcgen05_shift_down");
+    assert_eq!(target.abi_id, "i0761");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_shift_down");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_SHIFT_CG1",
+            asm: "tcgen05.shift.cta_group::1.down \t[$tmem_addr];",
+            predicates: &["Subtarget->hasTcgen05ShiftSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_shift_down_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0762").unwrap();
+    assert_eq!(target.id, "tcgen05_shift_down_cg2");
+    assert_eq!(target.abi_id, "i0762");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_shift_down_cg2");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TCGEN05_SHIFT_CG2",
+            asm: "tcgen05.shift.cta_group::2.down \t[$tmem_addr];",
+            predicates: &["Subtarget->hasTcgen05ShiftSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrArgMemOnly", "IntrConvergent", "NoCapture<arg0>"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs
new file mode 100644
index 0000000000..6b63b1c1d0
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs
@@ -0,0 +1,4542 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `tcgen05_st` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn tcgen05_st_16x64b_x1_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0670").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x1_raw");
+    assert_eq!(target.abi_id, "i0670");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x1_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x1_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0671").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x1_unpack16");
+    assert_eq!(target.abi_id, "i0671");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x1_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x2_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0672").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x2_raw");
+    assert_eq!(target.abi_id, "i0672");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x2_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x2_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0673").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x2_unpack16");
+    assert_eq!(target.abi_id, "i0673");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x2_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x4_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0674").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x4_raw");
+    assert_eq!(target.abi_id, "i0674");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x4_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x4_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0675").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x4_unpack16");
+    assert_eq!(target.abi_id, "i0675");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x4_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x8_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0676").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x8_raw");
+    assert_eq!(target.abi_id, "i0676");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x8_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x8_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0677").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x8_unpack16");
+    assert_eq!(target.abi_id, "i0677");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x8_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x16_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0678").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x16_raw");
+    assert_eq!(target.abi_id, "i0678");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x16_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x16_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0679").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x16_unpack16");
+    assert_eq!(target.abi_id, "i0679");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x16_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x32_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0680").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x32_raw");
+    assert_eq!(target.abi_id, "i0680");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x32_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x32_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0681").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x32_unpack16");
+    assert_eq!(target.abi_id, "i0681");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x32_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x64_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0682").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x64_raw");
+    assert_eq!(target.abi_id, "i0682");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x64_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x64_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0683").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x64_unpack16");
+    assert_eq!(target.abi_id, "i0683");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x64_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x128_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0684").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x128_raw");
+    assert_eq!(target.abi_id, "i0684");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x128_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x64b_x128_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0685").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x64b_x128_unpack16");
+    assert_eq!(target.abi_id, "i0685");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x64b_x128_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x1_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0686").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x1_raw");
+    assert_eq!(target.abi_id, "i0686");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x1_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x1_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0687").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x1_unpack16");
+    assert_eq!(target.abi_id, "i0687");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x1_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x2_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0688").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x2_raw");
+    assert_eq!(target.abi_id, "i0688");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x2_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x2_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0689").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x2_unpack16");
+    assert_eq!(target.abi_id, "i0689");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x2_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x4_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0690").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x4_raw");
+    assert_eq!(target.abi_id, "i0690");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x4_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x4_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0691").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x4_unpack16");
+    assert_eq!(target.abi_id, "i0691");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x4_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x8_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0692").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x8_raw");
+    assert_eq!(target.abi_id, "i0692");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x8_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x8_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0693").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x8_unpack16");
+    assert_eq!(target.abi_id, "i0693");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x8_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x16_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0694").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x16_raw");
+    assert_eq!(target.abi_id, "i0694");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x16_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x16_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0695").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x16_unpack16");
+    assert_eq!(target.abi_id, "i0695");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x16_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x32_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0696").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x32_raw");
+    assert_eq!(target.abi_id, "i0696");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x32_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x32_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0697").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x32_unpack16");
+    assert_eq!(target.abi_id, "i0697");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x32_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x64_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0698").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x64_raw");
+    assert_eq!(target.abi_id, "i0698");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x64_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x128b_x64_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0699").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x128b_x64_unpack16");
+    assert_eq!(target.abi_id, "i0699");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x128b_x64_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x1_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0700").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x1_raw");
+    assert_eq!(target.abi_id, "i0700");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x1_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x1_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0701").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x1_unpack16");
+    assert_eq!(target.abi_id, "i0701");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x1_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x2_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0702").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x2_raw");
+    assert_eq!(target.abi_id, "i0702");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x2_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x2_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0703").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x2_unpack16");
+    assert_eq!(target.abi_id, "i0703");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x2_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x4_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0704").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x4_raw");
+    assert_eq!(target.abi_id, "i0704");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x4_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x4_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0705").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x4_unpack16");
+    assert_eq!(target.abi_id, "i0705");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x4_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x8_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0706").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x8_raw");
+    assert_eq!(target.abi_id, "i0706");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x8_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x8_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0707").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x8_unpack16");
+    assert_eq!(target.abi_id, "i0707");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x8_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x16_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0708").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x16_raw");
+    assert_eq!(target.abi_id, "i0708");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x16_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x16_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0709").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x16_unpack16");
+    assert_eq!(target.abi_id, "i0709");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x16_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x32_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0710").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x32_raw");
+    assert_eq!(target.abi_id, "i0710");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x32_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x256b_x32_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0711").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x256b_x32_unpack16");
+    assert_eq!(target.abi_id, "i0711");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x256b_x32_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x1_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0712").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x1_raw");
+    assert_eq!(target.abi_id, "i0712");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x1_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x1_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0713").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x1_unpack16");
+    assert_eq!(target.abi_id, "i0713");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x1_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x2_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0714").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x2_raw");
+    assert_eq!(target.abi_id, "i0714");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x2_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x2_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0715").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x2_unpack16");
+    assert_eq!(target.abi_id, "i0715");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x2_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x4_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0716").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x4_raw");
+    assert_eq!(target.abi_id, "i0716");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x4_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x4_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0717").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x4_unpack16");
+    assert_eq!(target.abi_id, "i0717");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x4_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x8_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0718").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x8_raw");
+    assert_eq!(target.abi_id, "i0718");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x8_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x8_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0719").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x8_unpack16");
+    assert_eq!(target.abi_id, "i0719");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x8_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x16_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0720").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x16_raw");
+    assert_eq!(target.abi_id, "i0720");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x16_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x16_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0721").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x16_unpack16");
+    assert_eq!(target.abi_id, "i0721");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x16_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x32_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0722").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x32_raw");
+    assert_eq!(target.abi_id, "i0722");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x32_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x32_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0723").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x32_unpack16");
+    assert_eq!(target.abi_id, "i0723");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x32_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x64_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0724").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x64_raw");
+    assert_eq!(target.abi_id, "i0724");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x64_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x64_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0725").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x64_unpack16");
+    assert_eq!(target.abi_id, "i0725");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x64_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x128_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0726").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x128_raw");
+    assert_eq!(target.abi_id, "i0726");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x128_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_32x32b_x128_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0727").unwrap();
+    assert_eq!(target.id, "tcgen05_st_32x32b_x128_unpack16");
+    assert_eq!(target.abi_id, "i0727");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_32x32b_x128_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg2>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x1_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0744").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x1_raw");
+    assert_eq!(target.abi_id, "i0744");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x1_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x1_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0745").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x1_unpack16");
+    assert_eq!(target.abi_id, "i0745");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x1_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x2_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0746").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x2_raw");
+    assert_eq!(target.abi_id, "i0746");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x2_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x2_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0747").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x2_unpack16");
+    assert_eq!(target.abi_id, "i0747");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x2_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x4_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0748").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x4_raw");
+    assert_eq!(target.abi_id, "i0748");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x4_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x4_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0749").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x4_unpack16");
+    assert_eq!(target.abi_id, "i0749");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x4_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x8_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0750").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x8_raw");
+    assert_eq!(target.abi_id, "i0750");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x8_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x8_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0751").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x8_unpack16");
+    assert_eq!(target.abi_id, "i0751");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x8_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x16_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0752").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x16_raw");
+    assert_eq!(target.abi_id, "i0752");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x16_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x16_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0753").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x16_unpack16");
+    assert_eq!(target.abi_id, "i0753");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x16_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x32_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0754").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x32_raw");
+    assert_eq!(target.abi_id, "i0754");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x32_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x32_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0755").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x32_unpack16");
+    assert_eq!(target.abi_id, "i0755");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x32_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x64_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0756").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x64_raw");
+    assert_eq!(target.abi_id, "i0756");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x64_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x64_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0757").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x64_unpack16");
+    assert_eq!(target.abi_id, "i0757");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x64_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x128_raw_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0758").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x128_raw");
+    assert_eq!(target.abi_id, "i0758");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x128_raw");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tcgen05_st_16x32bx2_x128_unpack16_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0759").unwrap();
+    assert_eq!(target.id, "tcgen05_st_16x32bx2_x128_unpack16");
+    assert_eq!(target.abi_id, "i0759");
+    assert_eq!(target.dialect_op, "nvvm.tcgen05_st_16x32bx2_x128_unpack16");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "ImmArg<arg3>",
+            "IntrArgMemOnly",
+            "IntrConvergent",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs
new file mode 100644
index 0000000000..60a840fddd
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs
@@ -0,0 +1,6641 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `tma` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn cp_async_bulk_tensor_1d_g2s_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0328").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_1d_g2s");
+    assert_eq!(target.abi_id, "i0328");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_g2s_tile_1d");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_1D",
+            asm: "cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0}}], [$mbar];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 6,
+                        value: 0
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 7,
+                        value: 0
+                    }
+                ]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "Range<arg8,0,3>",
+            "ReadOnly<arg2>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_2d_g2s_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0329").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_2d_g2s");
+    assert_eq!(target.abi_id, "i0329");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_g2s_tile_2d");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_2D",
+            asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 7,
+                        value: 0
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 8,
+                        value: 0
+                    }
+                ]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "ImmArg<arg9>",
+            "IntrConvergent",
+            "Range<arg9,0,3>",
+            "ReadOnly<arg2>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_2d_g2s_multicast_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0330").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_2d_g2s_multicast");
+    assert_eq!(target.abi_id, "i0330");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_2D_MC",
+            asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 7,
+                        value: -1
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 8,
+                        value: 0
+                    }
+                ]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "ImmArg<arg9>",
+            "IntrConvergent",
+            "Range<arg9,0,3>",
+            "ReadOnly<arg2>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_2d_g2s_multicast_cg2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0331").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_2d_g2s_multicast_cg2");
+    assert_eq!(target.abi_id, "i0331");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast_cg2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_2D_MC",
+            asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
+            predicates: &["Subtarget->hasTMABlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 7,
+                        value: -1
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 8,
+                        value: 0
+                    }
+                ]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "ImmArg<arg8>",
+            "ImmArg<arg9>",
+            "IntrConvergent",
+            "Range<arg9,0,3>",
+            "ReadOnly<arg2>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_3d_g2s_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0332").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_3d_g2s");
+    assert_eq!(target.abi_id, "i0332");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_g2s_tile_3d");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_3D",
+            asm: "cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2}}], [$mbar];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 8,
+                        value: 0
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 9,
+                        value: 0
+                    }
+                ]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg10>",
+            "ImmArg<arg8>",
+            "ImmArg<arg9>",
+            "IntrConvergent",
+            "Range<arg10,0,3>",
+            "ReadOnly<arg2>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_4d_g2s_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0333").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_4d_g2s");
+    assert_eq!(target.abi_id, "i0333");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_g2s_tile_4d");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_4D",
+            asm: "cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3}}], [$mbar];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 9,
+                        value: 0
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 10,
+                        value: 0
+                    }
+                ]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg10>",
+            "ImmArg<arg11>",
+            "ImmArg<arg9>",
+            "IntrConvergent",
+            "Range<arg11,0,3>",
+            "ReadOnly<arg2>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_5d_g2s_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0334").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_5d_g2s");
+    assert_eq!(target.abi_id, "i0334");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_g2s_tile_5d");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_5D",
+            asm: "cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$mbar];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 10,
+                        value: 0
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 11,
+                        value: 0
+                    }
+                ]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg10>",
+            "ImmArg<arg11>",
+            "ImmArg<arg12>",
+            "IntrConvergent",
+            "Range<arg12,0,3>",
+            "ReadOnly<arg2>",
+            "WriteOnly<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_1d_s2g_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0335").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_1d_s2g");
+    assert_eq!(target.abi_id, "i0335");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_s2g_tile_1d");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_S2G_TILE_1D",
+            asm: "cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [$tmap, {{$d0}}], [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 4,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg4>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_2d_s2g_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0336").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_2d_s2g");
+    assert_eq!(target.abi_id, "i0336");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_s2g_tile_2d");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_S2G_TILE_2D",
+            asm: "cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1}}], [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 5,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_3d_s2g_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0337").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_3d_s2g");
+    assert_eq!(target.abi_id, "i0337");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_s2g_tile_3d");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_S2G_TILE_3D",
+            asm: "cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2}}], [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 6,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_4d_s2g_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0338").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_4d_s2g");
+    assert_eq!(target.abi_id, "i0338");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_s2g_tile_4d");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_S2G_TILE_4D",
+            asm: "cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3}}], [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 7,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_5d_s2g_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0339").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_5d_s2g");
+    assert_eq!(target.abi_id, "i0339");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_tensor_s2g_tile_5d");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_S2G_TILE_5D",
+            asm: "cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 8,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_commit_group_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0340").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_commit_group");
+    assert_eq!(target.abi_id, "i0340");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_commit_group");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_BULK_COMMIT_GROUP",
+            asm: "cp.async.bulk.commit_group;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(target.llvm.unwrap().properties, &[] as &[&str]);
+}
+
+#[test]
+fn cp_async_bulk_wait_group_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0341").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_wait_group");
+    assert_eq!(target.abi_id, "i0341");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_wait_group");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_BULK_WAIT_GROUP",
+            asm: "cp.async.bulk.wait_group \t$n;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_wait_group_read_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0342").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_wait_group_read");
+    assert_eq!(target.abi_id, "i0342");
+    assert_eq!(target.dialect_op, "nvvm.cp_async_bulk_wait_group_read");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_BULK_WAIT_GROUP_READ",
+            asm: "cp.async.bulk.wait_group.read \t$n;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn prefetch_tma_descriptor_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0887").unwrap();
+    assert_eq!(target.id, "prefetch_tma_descriptor");
+    assert_eq!(target.abi_id, "i0887");
+    assert_eq!(target.dialect_op, "nvvm.prefetch_tensormap");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrArgMemOnly", "NoCapture<arg0>", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_1d_l2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0888").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_1d_l2");
+    assert_eq!(target.abi_id, "i0888");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_1d_l2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_1D",
+            asm: "cp.async.bulk.prefetch.tensor.1d.L2.global.tile [$tmap, {{$d0}}];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 3,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg3>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_2d_l2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0889").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_2d_l2");
+    assert_eq!(target.abi_id, "i0889");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_2d_l2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_2D",
+            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile [$tmap, {{$d0, $d1}}];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 4,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg4>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_3d_l2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0890").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_3d_l2");
+    assert_eq!(target.abi_id, "i0890");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_3d_l2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_3D",
+            asm: "cp.async.bulk.prefetch.tensor.3d.L2.global.tile [$tmap, {{$d0, $d1, $d2}}];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 5,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg5>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_4d_l2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0891").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_4d_l2");
+    assert_eq!(target.abi_id, "i0891");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_4d_l2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_4D",
+            asm: "cp.async.bulk.prefetch.tensor.4d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3}}];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 6,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg6>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_5d_l2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0892").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_5d_l2");
+    assert_eq!(target.abi_id, "i0892");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_5d_l2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_5D",
+            asm: "cp.async.bulk.prefetch.tensor.5d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 7,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_gather4_2d_l2_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0893").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_gather4_2d_l2");
+    assert_eq!(target.abi_id, "i0893");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_GATHER4_2D",
+            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4 [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
+            predicates: &["Subtarget->hasTMABlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 7,
+                    value: 0
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_box_dim_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0894").unwrap();
+    assert_eq!(target.id, "tensormap_replace_box_dim");
+    assert_eq!(target.abi_id, "i0894");
+    assert_eq!(target.dialect_op, "nvvm.tensormap_replace_box_dim");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrWriteMem",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_element_stride_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0895").unwrap();
+    assert_eq!(target.id, "tensormap_replace_element_stride");
+    assert_eq!(target.abi_id, "i0895");
+    assert_eq!(target.dialect_op, "nvvm.tensormap_replace_element_stride");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrWriteMem",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_element_type_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0896").unwrap();
+    assert_eq!(target.id, "tensormap_replace_element_type");
+    assert_eq!(target.abi_id, "i0896");
+    assert_eq!(target.dialect_op, "nvvm.tensormap_replace_element_type");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ArgInfo<arg1>",
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrWriteMem",
+            "NoCapture<arg0>",
+            "Range<arg1,0,16>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_fill_mode_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0897").unwrap();
+    assert_eq!(target.id, "tensormap_replace_fill_mode");
+    assert_eq!(target.abi_id, "i0897");
+    assert_eq!(target.dialect_op, "nvvm.tensormap_replace_fill_mode");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ArgInfo<arg1>",
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrWriteMem",
+            "NoCapture<arg0>",
+            "Range<arg1,0,2>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_global_address_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0898").unwrap();
+    assert_eq!(target.id, "tensormap_replace_global_address");
+    assert_eq!(target.abi_id, "i0898");
+    assert_eq!(target.dialect_op, "nvvm.tensormap_replace_global_address");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrArgMemOnly", "IntrWriteMem", "NoCapture<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_global_dim_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0899").unwrap();
+    assert_eq!(target.id, "tensormap_replace_global_dim");
+    assert_eq!(target.abi_id, "i0899");
+    assert_eq!(target.dialect_op, "nvvm.tensormap_replace_global_dim");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrWriteMem",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_global_stride_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0900").unwrap();
+    assert_eq!(target.id, "tensormap_replace_global_stride");
+    assert_eq!(target.abi_id, "i0900");
+    assert_eq!(target.dialect_op, "nvvm.tensormap_replace_global_stride");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrWriteMem",
+            "NoCapture<arg0>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_interleave_layout_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0901").unwrap();
+    assert_eq!(target.id, "tensormap_replace_interleave_layout");
+    assert_eq!(target.abi_id, "i0901");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tensormap_replace_interleave_layout"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ArgInfo<arg1>",
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrWriteMem",
+            "NoCapture<arg0>",
+            "Range<arg1,0,3>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_rank_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0902").unwrap();
+    assert_eq!(target.id, "tensormap_replace_rank");
+    assert_eq!(target.abi_id, "i0902");
+    assert_eq!(target.dialect_op, "nvvm.tensormap_replace_rank");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrArgMemOnly", "IntrWriteMem", "NoCapture<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_swizzle_atomicity_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0903").unwrap();
+    assert_eq!(target.id, "tensormap_replace_swizzle_atomicity");
+    assert_eq!(target.abi_id, "i0903");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.tensormap_replace_swizzle_atomicity"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ArgInfo<arg1>",
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrWriteMem",
+            "NoCapture<arg0>",
+            "Range<arg1,0,4>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn tensormap_replace_swizzle_mode_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0904").unwrap();
+    assert_eq!(target.id, "tensormap_replace_swizzle_mode");
+    assert_eq!(target.abi_id, "i0904");
+    assert_eq!(target.dialect_op, "nvvm.tensormap_replace_swizzle_mode");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::FamilyTarget(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::FamilyTarget(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                            GeneratedHardwareAlternative::FamilyTarget(110),
+                            GeneratedHardwareAlternative::ExactArchitecture(120),
+                            GeneratedHardwareAlternative::FamilyTarget(120),
+                            GeneratedHardwareAlternative::ExactArchitecture(121),
+                            GeneratedHardwareAlternative::FamilyTarget(121),
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ArgInfo<arg1>",
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrWriteMem",
+            "NoCapture<arg0>",
+            "Range<arg1,0,5>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_tensormap_generic_acquire_cluster_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0905").unwrap();
+    assert_eq!(target.id, "fence_proxy_tensormap_generic_acquire_cluster");
+    assert_eq!(target.abi_id, "i0905");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_proxy_tensormap_generic_acquire_cluster"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CLUSTER",
+            asm: "fence.proxy.tensormap::generic.acquire.cluster [$addr], 128;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "Range<arg1,128,129>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_tensormap_generic_acquire_cta_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0906").unwrap();
+    assert_eq!(target.id, "fence_proxy_tensormap_generic_acquire_cta");
+    assert_eq!(target.abi_id, "i0906");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_proxy_tensormap_generic_acquire_cta"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CTA",
+            asm: "fence.proxy.tensormap::generic.acquire.cta [$addr], 128;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "Range<arg1,128,129>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_tensormap_generic_acquire_gpu_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0907").unwrap();
+    assert_eq!(target.id, "fence_proxy_tensormap_generic_acquire_gpu");
+    assert_eq!(target.abi_id, "i0907");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_proxy_tensormap_generic_acquire_gpu"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_GPU",
+            asm: "fence.proxy.tensormap::generic.acquire.gpu [$addr], 128;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "Range<arg1,128,129>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_tensormap_generic_acquire_system_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0908").unwrap();
+    assert_eq!(target.id, "fence_proxy_tensormap_generic_acquire_system");
+    assert_eq!(target.abi_id, "i0908");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_proxy_tensormap_generic_acquire_system"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_SYS",
+            asm: "fence.proxy.tensormap::generic.acquire.sys [$addr], 128;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg1>",
+            "IntrArgMemOnly",
+            "IntrNoCallback",
+            "Range<arg1,128,129>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_tensormap_generic_release_cluster_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0909").unwrap();
+    assert_eq!(target.id, "fence_proxy_tensormap_generic_release_cluster");
+    assert_eq!(target.abi_id, "i0909");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_proxy_tensormap_generic_release_cluster"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CLUSTER",
+            asm: "fence.proxy.tensormap::generic.release.cluster;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_tensormap_generic_release_cta_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0910").unwrap();
+    assert_eq!(target.id, "fence_proxy_tensormap_generic_release_cta");
+    assert_eq!(target.abi_id, "i0910");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_proxy_tensormap_generic_release_cta"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CTA",
+            asm: "fence.proxy.tensormap::generic.release.cta;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_tensormap_generic_release_gpu_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0911").unwrap();
+    assert_eq!(target.id, "fence_proxy_tensormap_generic_release_gpu");
+    assert_eq!(target.abi_id, "i0911");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_proxy_tensormap_generic_release_gpu"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_GPU",
+            asm: "fence.proxy.tensormap::generic.release.gpu;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn fence_proxy_tensormap_generic_release_system_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0912").unwrap();
+    assert_eq!(target.id, "fence_proxy_tensormap_generic_release_system");
+    assert_eq!(target.abi_id, "i0912");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.fence_proxy_tensormap_generic_release_system"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 83);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_SYS",
+            asm: "fence.proxy.tensormap::generic.release.sys;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrNoCallback"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_1d_l2_cache_hint_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0917").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_1d_l2_cache_hint");
+    assert_eq!(target.abi_id, "i0917");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_1D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.1d.L2.global.tile.L2::cache_hint [$tmap, {{$d0}}], $ch;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 3,
+                    value: -1
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg3>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_2d_l2_cache_hint_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0918").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_2d_l2_cache_hint");
+    assert_eq!(target.abi_id, "i0918");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_2D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1}}], $ch;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 4,
+                    value: -1
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg4>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_3d_l2_cache_hint_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0919").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_3d_l2_cache_hint");
+    assert_eq!(target.abi_id, "i0919");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_3D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.3d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2}}], $ch;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 5,
+                    value: -1
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg5>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_4d_l2_cache_hint_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0920").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_4d_l2_cache_hint");
+    assert_eq!(target.abi_id, "i0920");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_4D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.4d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3}}], $ch;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 6,
+                    value: -1
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg6>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_5d_l2_cache_hint_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0921").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_prefetch_tensor_5d_l2_cache_hint");
+    assert_eq!(target.abi_id, "i0921");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_5D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.5d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90"
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 7,
+                    value: -1
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0922").unwrap();
+    assert_eq!(
+        target.id,
+        "cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
+    );
+    assert_eq!(target.abi_id, "i0922");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 86);
+    assert_eq!(
+        target.requirement.hardware,
+        const {
+            GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ])
+        }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(100),
+                            GeneratedHardwareAlternative::ExactArchitecture(101),
+                            GeneratedHardwareAlternative::ExactArchitecture(103),
+                            GeneratedHardwareAlternative::ExactArchitecture(110),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_GATHER4_2D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
+            predicates: &["Subtarget->hasTMABlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 7,
+                    value: -1
+                }]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_add_tile_1d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0923").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_tile_1d");
+    assert_eq!(target.abi_id, "i0923");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_add_tile_1d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg4>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_add_tile_2d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0924").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_tile_2d");
+    assert_eq!(target.abi_id, "i0924");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_add_tile_2d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_add_tile_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0925").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_tile_3d");
+    assert_eq!(target.abi_id, "i0925");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_add_tile_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_add_tile_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0926").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_tile_4d");
+    assert_eq!(target.abi_id, "i0926");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_add_tile_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_add_tile_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0927").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_tile_5d");
+    assert_eq!(target.abi_id, "i0927");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_add_tile_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_add_im2col_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0928").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_im2col_3d");
+    assert_eq!(target.abi_id, "i0928");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_add_im2col_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_add_im2col_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0929").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_im2col_4d");
+    assert_eq!(target.abi_id, "i0929");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_add_im2col_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_add_im2col_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0930").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_add_im2col_5d");
+    assert_eq!(target.abi_id, "i0930");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_add_im2col_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_and_tile_1d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0931").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_tile_1d");
+    assert_eq!(target.abi_id, "i0931");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_and_tile_1d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg4>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_and_tile_2d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0932").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_tile_2d");
+    assert_eq!(target.abi_id, "i0932");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_and_tile_2d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_and_tile_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0933").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_tile_3d");
+    assert_eq!(target.abi_id, "i0933");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_and_tile_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_and_tile_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0934").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_tile_4d");
+    assert_eq!(target.abi_id, "i0934");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_and_tile_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_and_tile_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0935").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_tile_5d");
+    assert_eq!(target.abi_id, "i0935");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_and_tile_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_and_im2col_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0936").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_im2col_3d");
+    assert_eq!(target.abi_id, "i0936");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_and_im2col_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_and_im2col_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0937").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_im2col_4d");
+    assert_eq!(target.abi_id, "i0937");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_and_im2col_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_and_im2col_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0938").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_and_im2col_5d");
+    assert_eq!(target.abi_id, "i0938");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_and_im2col_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_tile_1d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0939").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_tile_1d");
+    assert_eq!(target.abi_id, "i0939");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_dec_tile_1d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg4>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_tile_2d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0940").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_tile_2d");
+    assert_eq!(target.abi_id, "i0940");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_dec_tile_2d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_tile_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0941").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_tile_3d");
+    assert_eq!(target.abi_id, "i0941");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_dec_tile_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_tile_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0942").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_tile_4d");
+    assert_eq!(target.abi_id, "i0942");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_dec_tile_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_tile_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0943").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_tile_5d");
+    assert_eq!(target.abi_id, "i0943");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_dec_tile_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_im2col_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0944").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_im2col_3d");
+    assert_eq!(target.abi_id, "i0944");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_im2col_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0945").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_im2col_4d");
+    assert_eq!(target.abi_id, "i0945");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_im2col_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0946").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_dec_im2col_5d");
+    assert_eq!(target.abi_id, "i0946");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_tile_1d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0947").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_tile_1d");
+    assert_eq!(target.abi_id, "i0947");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_inc_tile_1d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg4>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_tile_2d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0948").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_tile_2d");
+    assert_eq!(target.abi_id, "i0948");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_inc_tile_2d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_tile_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0949").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_tile_3d");
+    assert_eq!(target.abi_id, "i0949");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_inc_tile_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_tile_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0950").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_tile_4d");
+    assert_eq!(target.abi_id, "i0950");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_inc_tile_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_tile_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0951").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_tile_5d");
+    assert_eq!(target.abi_id, "i0951");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_inc_tile_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_im2col_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0952").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_im2col_3d");
+    assert_eq!(target.abi_id, "i0952");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_im2col_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0953").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_im2col_4d");
+    assert_eq!(target.abi_id, "i0953");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_im2col_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0954").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_inc_im2col_5d");
+    assert_eq!(target.abi_id, "i0954");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_max_tile_1d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0955").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_tile_1d");
+    assert_eq!(target.abi_id, "i0955");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_max_tile_1d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg4>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_max_tile_2d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0956").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_tile_2d");
+    assert_eq!(target.abi_id, "i0956");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_max_tile_2d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_max_tile_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0957").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_tile_3d");
+    assert_eq!(target.abi_id, "i0957");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_max_tile_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_max_tile_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0958").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_tile_4d");
+    assert_eq!(target.abi_id, "i0958");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_max_tile_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_max_tile_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0959").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_tile_5d");
+    assert_eq!(target.abi_id, "i0959");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_max_tile_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_max_im2col_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0960").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_im2col_3d");
+    assert_eq!(target.abi_id, "i0960");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_max_im2col_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_max_im2col_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0961").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_im2col_4d");
+    assert_eq!(target.abi_id, "i0961");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_max_im2col_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_max_im2col_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0962").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_max_im2col_5d");
+    assert_eq!(target.abi_id, "i0962");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_max_im2col_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_min_tile_1d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0963").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_tile_1d");
+    assert_eq!(target.abi_id, "i0963");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_min_tile_1d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg4>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_min_tile_2d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0964").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_tile_2d");
+    assert_eq!(target.abi_id, "i0964");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_min_tile_2d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_min_tile_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0965").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_tile_3d");
+    assert_eq!(target.abi_id, "i0965");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_min_tile_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_min_tile_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0966").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_tile_4d");
+    assert_eq!(target.abi_id, "i0966");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_min_tile_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_min_tile_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0967").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_tile_5d");
+    assert_eq!(target.abi_id, "i0967");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_min_tile_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_min_im2col_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0968").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_im2col_3d");
+    assert_eq!(target.abi_id, "i0968");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_min_im2col_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_min_im2col_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0969").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_im2col_4d");
+    assert_eq!(target.abi_id, "i0969");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_min_im2col_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_min_im2col_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0970").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_min_im2col_5d");
+    assert_eq!(target.abi_id, "i0970");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_min_im2col_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_or_tile_1d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0971").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_tile_1d");
+    assert_eq!(target.abi_id, "i0971");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_or_tile_1d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg4>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_or_tile_2d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0972").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_tile_2d");
+    assert_eq!(target.abi_id, "i0972");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_or_tile_2d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_or_tile_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0973").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_tile_3d");
+    assert_eq!(target.abi_id, "i0973");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_or_tile_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_or_tile_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0974").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_tile_4d");
+    assert_eq!(target.abi_id, "i0974");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_or_tile_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_or_tile_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0975").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_tile_5d");
+    assert_eq!(target.abi_id, "i0975");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_or_tile_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_or_im2col_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0976").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_im2col_3d");
+    assert_eq!(target.abi_id, "i0976");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_or_im2col_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_or_im2col_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0977").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_im2col_4d");
+    assert_eq!(target.abi_id, "i0977");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_or_im2col_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_or_im2col_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0978").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_or_im2col_5d");
+    assert_eq!(target.abi_id, "i0978");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_or_im2col_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_tile_1d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0979").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_tile_1d");
+    assert_eq!(target.abi_id, "i0979");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_xor_tile_1d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg4>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_tile_2d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0980").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_tile_2d");
+    assert_eq!(target.abi_id, "i0980");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_xor_tile_2d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg5>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_tile_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0981").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_tile_3d");
+    assert_eq!(target.abi_id, "i0981");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_xor_tile_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_tile_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0982").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_tile_4d");
+    assert_eq!(target.abi_id, "i0982");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_xor_tile_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_tile_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0983").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_tile_5d");
+    assert_eq!(target.abi_id, "i0983");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_xor_tile_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_im2col_3d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0984").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_im2col_3d");
+    assert_eq!(target.abi_id, "i0984");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_3d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg6>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_im2col_4d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0985").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_im2col_4d");
+    assert_eq!(target.abi_id, "i0985");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_4d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg7>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_im2col_5d_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0986").unwrap();
+    assert_eq!(target.id, "cp_async_bulk_tensor_reduce_xor_im2col_5d");
+    assert_eq!(target.abi_id, "i0986");
+    assert_eq!(
+        target.dialect_op,
+        "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_5d"
+    );
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "ImmArg<arg8>",
+            "IntrConvergent",
+            "ReadOnly<arg0>",
+            "ReadOnly<arg1>"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs
new file mode 100644
index 0000000000..7508a794ff
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs
@@ -0,0 +1,220 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `vote` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn all_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0040").unwrap();
+    assert_eq!(target.id, "all_sync");
+    assert_eq!(target.abi_id, "i0040");
+    assert_eq!(target.dialect_op, "nvvm.vote_sync_all");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_ALLi",
+                asm: "vote.sync.all.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_ALLr",
+                asm: "vote.sync.all.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn any_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0041").unwrap();
+    assert_eq!(target.id, "any_sync");
+    assert_eq!(target.abi_id, "i0041");
+    assert_eq!(target.dialect_op, "nvvm.vote_sync_any");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_ANYi",
+                asm: "vote.sync.any.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_ANYr",
+                asm: "vote.sync.any.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn ballot_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0042").unwrap();
+    assert_eq!(target.id, "ballot_sync");
+    assert_eq!(target.abi_id, "i0042");
+    assert_eq!(target.dialect_op, "nvvm.vote_sync_ballot");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_BALLOTi",
+                asm: "vote.sync.ballot.b32 \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_BALLOTr",
+                asm: "vote.sync.ballot.b32 \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn uni_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0043").unwrap();
+    assert_eq!(target.id, "uni_sync");
+    assert_eq!(target.abi_id, "i0043");
+    assert_eq!(target.dialect_op, "nvvm.vote_sync_uni");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_UNIi",
+                asm: "vote.sync.uni.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_UNIr",
+                asm: "vote.sync.uni.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs
new file mode 100644
index 0000000000..15ae933d00
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs
@@ -0,0 +1,84 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `warp_barrier` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn sync_mask_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0049").unwrap();
+    assert_eq!(target.id, "sync_mask");
+    assert_eq!(target.abi_id, "i0049");
+    assert_eq!(target.dialect_op, "nvvm.bar_warp_sync");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "INT_BAR_WARP_SYNC_I",
+                asm: "bar.warp.sync \t$i;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "INT_BAR_WARP_SYNC_R",
+                asm: "bar.warp.sync \t$i;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent", "IntrNoCallback"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs
new file mode 100644
index 0000000000..19061fd4b6
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs
@@ -0,0 +1,316 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `warp_match` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn match_any_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0045").unwrap();
+    assert_eq!(target.id, "match_any_sync");
+    assert_eq!(target.abi_id, "i0045");
+    assert_eq!(target.dialect_op, "nvvm.match_any_sync_i32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_32ii",
+                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_32ir",
+                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_32ri",
+                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_32rr",
+                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn match_any_i64_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0046").unwrap();
+    assert_eq!(target.id, "match_any_i64_sync");
+    assert_eq!(target.abi_id, "i0046");
+    assert_eq!(target.dialect_op, "nvvm.match_any_sync_i64");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_64ii",
+                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_64ir",
+                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_64ri",
+                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_64rr",
+                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn match_all_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0047").unwrap();
+    assert_eq!(target.id, "match_all_sync");
+    assert_eq!(target.abi_id, "i0047");
+    assert_eq!(target.dialect_op, "nvvm.match_all_sync_i32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_32ii",
+                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_32ir",
+                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_32ri",
+                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_32rr",
+                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn match_all_i64_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0048").unwrap();
+    assert_eq!(target.id, "match_all_i64_sync");
+    assert_eq!(target.abi_id, "i0048");
+    assert_eq!(target.dialect_op, "nvvm.match_all_sync_i64");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(70)]) }
+    );
+    assert_eq!(target.backend_requirements, const { &[] });
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_64ii",
+                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_64ir",
+                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_64ri",
+                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_64rr",
+                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs
new file mode 100644
index 0000000000..d79fefe9cd
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs
@@ -0,0 +1,1360 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `warp_shuffle` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn shuffle_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0050").unwrap();
+    assert_eq!(target.id, "shuffle_sync");
+    assert_eq!(target.abi_id, "i0050");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_idx_i32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14989",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14990",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14991",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14992",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14993",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14994",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14995",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14996",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn shuffle_xor_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0051").unwrap();
+    assert_eq!(target.id, "shuffle_xor_sync");
+    assert_eq!(target.abi_id, "i0051");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_bfly_i32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14957",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14958",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14959",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14960",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14961",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14962",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14963",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14964",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn shuffle_down_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0052").unwrap();
+    assert_eq!(target.id, "shuffle_down_sync");
+    assert_eq!(target.abi_id, "i0052");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_down_i32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14925",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14926",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14927",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14928",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14929",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14930",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14931",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14932",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn shuffle_up_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0053").unwrap();
+    assert_eq!(target.id, "shuffle_up_sync");
+    assert_eq!(target.abi_id, "i0053");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_up_i32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14893",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14894",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14895",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14896",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14897",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14898",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14899",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14900",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn shuffle_f32_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0054").unwrap();
+    assert_eq!(target.id, "shuffle_f32_sync");
+    assert_eq!(target.abi_id, "i0054");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_idx_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15005",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15006",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15007",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15008",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15009",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15010",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15011",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15012",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn shuffle_xor_f32_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0055").unwrap();
+    assert_eq!(target.id, "shuffle_xor_f32_sync");
+    assert_eq!(target.abi_id, "i0055");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_bfly_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14973",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14974",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14975",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14976",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14977",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14978",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14979",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14980",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn shuffle_down_f32_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0056").unwrap();
+    assert_eq!(target.id, "shuffle_down_f32_sync");
+    assert_eq!(target.abi_id, "i0056");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_down_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14941",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14942",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14943",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14944",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14945",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14946",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14947",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14948",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn shuffle_up_f32_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0057").unwrap();
+    assert_eq!(target.id, "shuffle_up_f32_sync");
+    assert_eq!(target.abi_id, "i0057");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_up_f32");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14909",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14910",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14911",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14912",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14913",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14914",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14915",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14916",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30"
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[]
+                }
+            },
+        ]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &[
+            "IntrConvergent",
+            "IntrInaccessibleMemOnly",
+            "IntrNoCallback"
+        ] as &[&str]
+    );
+}
+
+#[test]
+fn shuffle_u64_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0058").unwrap();
+    assert_eq!(target.id, "shuffle_u64_sync");
+    assert_eq!(target.abi_id, "i0058");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_idx_i64");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn shuffle_xor_u64_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0059").unwrap();
+    assert_eq!(target.id, "shuffle_xor_u64_sync");
+    assert_eq!(target.abi_id, "i0059");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_bfly_i64");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn shuffle_down_u64_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0060").unwrap();
+    assert_eq!(target.id, "shuffle_down_u64_sync");
+    assert_eq!(target.abi_id, "i0060");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_down_i64");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
+
+#[test]
+fn shuffle_up_u64_sync_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0061").unwrap();
+    assert_eq!(target.id, "shuffle_up_u64_sync");
+    assert_eq!(target.abi_id, "i0061");
+    assert_eq!(target.dialect_op, "nvvm.shfl_sync_up_i64");
+    assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar);
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 60);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(30),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::MinimumSm(75),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(target.selections, &[]);
+    assert!(target.llvm.is_none());
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs
new file mode 100644
index 0000000000..410912ef19
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs
@@ -0,0 +1,192 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target tests: `wgmma_control` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn wgmma_fence_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0317").unwrap();
+    assert_eq!(target.id, "wgmma_fence");
+    assert_eq!(target.abi_id, "i0317");
+    assert_eq!(target.dialect_op, "nvvm.wgmma_fence_sync_aligned");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::WgmmaControl {
+            mode: GeneratedWgmmaControlMode::Fence
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "WGMMA_FENCE_SYNC_ALIGNED",
+            asm: "wgmma.fence.sync.aligned;",
+            predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent"] as &[&str]
+    );
+}
+
+#[test]
+fn wgmma_commit_group_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0318").unwrap();
+    assert_eq!(target.id, "wgmma_commit_group");
+    assert_eq!(target.abi_id, "i0318");
+    assert_eq!(target.dialect_op, "nvvm.wgmma_commit_group_sync_aligned");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::WgmmaControl {
+            mode: GeneratedWgmmaControlMode::CommitGroup
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "WGMMA_COMMIT_GROUP_SYNC_ALIGNED",
+            asm: "wgmma.commit_group.sync.aligned;",
+            predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["IntrConvergent"] as &[&str]
+    );
+}
+
+#[test]
+fn wgmma_wait_group_target_matches_the_catalog() {
+    let target = generated_intrinsic_target_by_marker("v1:i0319").unwrap();
+    assert_eq!(target.id, "wgmma_wait_group");
+    assert_eq!(target.abi_id, "i0319");
+    assert_eq!(target.dialect_op, "nvvm.wgmma_wait_group_sync_aligned");
+    assert_eq!(
+        target.variant,
+        GeneratedIntrinsicVariant::WgmmaControl {
+            mode: GeneratedWgmmaControlMode::WaitGroup
+        }
+    );
+    assert_eq!(target.requirement.minimum_ptx.encoded(), 80);
+    assert_eq!(
+        target.requirement.hardware,
+        const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::ExactArchitecture(90)]) }
+    );
+    assert_eq!(
+        target.backend_requirements,
+        const {
+            &[
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+                GeneratedBackendRequirement {
+                    backend: GeneratedIntrinsicBackend::LibNvvm,
+                    requirement: GeneratedTargetRequirement {
+                        minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                        hardware: GeneratedHardwareTarget::AnyOf(&[
+                            GeneratedHardwareAlternative::ExactArchitecture(90),
+                        ]),
+                    },
+                },
+            ]
+        }
+    );
+    assert_eq!(
+        target.selections,
+        &[GeneratedSelectionAlternative {
+            source_record: "WGMMA_WAIT_GROUP_SYNC_ALIGNED",
+            asm: "wgmma.wait_group.sync.aligned \t$n;",
+            predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[]
+            }
+        },]
+    );
+    assert_eq!(
+        target.llvm.unwrap().properties,
+        &["ImmArg<arg0>", "IntrConvergent"] as &[&str]
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs
new file mode 100644
index 0000000000..c82e29de95
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs
@@ -0,0 +1,5669 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `tma` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedImmediateBinding, GeneratedIntrinsicBackend, GeneratedIntrinsicTarget,
+    GeneratedIntrinsicVariant, GeneratedLlvmFacts, GeneratedPtxVersion,
+    GeneratedSelectionAlternative, GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0328",
+        id: "cp_async_bulk_tensor_1d_g2s",
+        abi_id: "i0328",
+        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_1d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_1D",
+            asm: "cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0}}], [$mbar];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 6,
+                        value: 0,
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 7,
+                        value: 0,
+                    },
+                ],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "Range<arg8,0,3>",
+                "ReadOnly<arg2>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0329",
+        id: "cp_async_bulk_tensor_2d_g2s",
+        abi_id: "i0329",
+        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_2d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_2D",
+            asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 7,
+                        value: 0,
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 8,
+                        value: 0,
+                    },
+                ],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "ImmArg<arg9>",
+                "IntrConvergent",
+                "Range<arg9,0,3>",
+                "ReadOnly<arg2>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0330",
+        id: "cp_async_bulk_tensor_2d_g2s_multicast",
+        abi_id: "i0330",
+        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_2D_MC",
+            asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 7,
+                        value: -1,
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 8,
+                        value: 0,
+                    },
+                ],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "ImmArg<arg9>",
+                "IntrConvergent",
+                "Range<arg9,0,3>",
+                "ReadOnly<arg2>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0331",
+        id: "cp_async_bulk_tensor_2d_g2s_multicast_cg2",
+        abi_id: "i0331",
+        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_2d_multicast_cg2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_2D_MC",
+            asm: "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster$cg [$dst], [$tmap, {{$d0, $d1}}], [$mbar], $mc;",
+            predicates: &["Subtarget->hasTMABlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 7,
+                        value: -1,
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 8,
+                        value: 0,
+                    },
+                ],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "ImmArg<arg8>",
+                "ImmArg<arg9>",
+                "IntrConvergent",
+                "Range<arg9,0,3>",
+                "ReadOnly<arg2>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0332",
+        id: "cp_async_bulk_tensor_3d_g2s",
+        abi_id: "i0332",
+        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_3D",
+            asm: "cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2}}], [$mbar];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 8,
+                        value: 0,
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 9,
+                        value: 0,
+                    },
+                ],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg10>",
+                "ImmArg<arg8>",
+                "ImmArg<arg9>",
+                "IntrConvergent",
+                "Range<arg10,0,3>",
+                "ReadOnly<arg2>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0333",
+        id: "cp_async_bulk_tensor_4d_g2s",
+        abi_id: "i0333",
+        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_4D",
+            asm: "cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3}}], [$mbar];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 9,
+                        value: 0,
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 10,
+                        value: 0,
+                    },
+                ],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg10>",
+                "ImmArg<arg11>",
+                "ImmArg<arg9>",
+                "IntrConvergent",
+                "Range<arg11,0,3>",
+                "ReadOnly<arg2>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0334",
+        id: "cp_async_bulk_tensor_5d_g2s",
+        abi_id: "i0334",
+        dialect_op: "nvvm.cp_async_bulk_tensor_g2s_tile_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_G2S_TILE_CG0_5D",
+            asm: "cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes$cg [$dst], [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$mbar];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[
+                    GeneratedImmediateBinding {
+                        argument_index: 10,
+                        value: 0,
+                    },
+                    GeneratedImmediateBinding {
+                        argument_index: 11,
+                        value: 0,
+                    },
+                ],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg10>",
+                "ImmArg<arg11>",
+                "ImmArg<arg12>",
+                "IntrConvergent",
+                "Range<arg12,0,3>",
+                "ReadOnly<arg2>",
+                "WriteOnly<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0335",
+        id: "cp_async_bulk_tensor_1d_s2g",
+        abi_id: "i0335",
+        dialect_op: "nvvm.cp_async_bulk_tensor_s2g_tile_1d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_S2G_TILE_1D",
+            asm: "cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [$tmap, {{$d0}}], [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 4,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg4>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0336",
+        id: "cp_async_bulk_tensor_2d_s2g",
+        abi_id: "i0336",
+        dialect_op: "nvvm.cp_async_bulk_tensor_s2g_tile_2d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_S2G_TILE_2D",
+            asm: "cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1}}], [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 5,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0337",
+        id: "cp_async_bulk_tensor_3d_s2g",
+        abi_id: "i0337",
+        dialect_op: "nvvm.cp_async_bulk_tensor_s2g_tile_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_S2G_TILE_3D",
+            asm: "cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2}}], [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 6,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0338",
+        id: "cp_async_bulk_tensor_4d_s2g",
+        abi_id: "i0338",
+        dialect_op: "nvvm.cp_async_bulk_tensor_s2g_tile_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_S2G_TILE_4D",
+            asm: "cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3}}], [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 7,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0339",
+        id: "cp_async_bulk_tensor_5d_s2g",
+        abi_id: "i0339",
+        dialect_op: "nvvm.cp_async_bulk_tensor_s2g_tile_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_S2G_TILE_5D",
+            asm: "cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], [$src];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 8,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0340",
+        id: "cp_async_bulk_commit_group",
+        abi_id: "i0340",
+        dialect_op: "nvvm.cp_async_bulk_commit_group",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_BULK_COMMIT_GROUP",
+            asm: "cp.async.bulk.commit_group;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0341",
+        id: "cp_async_bulk_wait_group",
+        abi_id: "i0341",
+        dialect_op: "nvvm.cp_async_bulk_wait_group",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_BULK_WAIT_GROUP",
+            asm: "cp.async.bulk.wait_group \t$n;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0342",
+        id: "cp_async_bulk_wait_group_read",
+        abi_id: "i0342",
+        dialect_op: "nvvm.cp_async_bulk_wait_group_read",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "CP_ASYNC_BULK_WAIT_GROUP_READ",
+            asm: "cp.async.bulk.wait_group.read \t$n;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0887",
+        id: "prefetch_tma_descriptor",
+        abi_id: "i0887",
+        dialect_op: "nvvm.prefetch_tensormap",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrArgMemOnly", "NoCapture<arg0>", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0888",
+        id: "cp_async_bulk_prefetch_tensor_1d_l2",
+        abi_id: "i0888",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_1d_l2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_1D",
+            asm: "cp.async.bulk.prefetch.tensor.1d.L2.global.tile [$tmap, {{$d0}}];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 3,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg3>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0889",
+        id: "cp_async_bulk_prefetch_tensor_2d_l2",
+        abi_id: "i0889",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_2d_l2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_2D",
+            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile [$tmap, {{$d0, $d1}}];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 4,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg4>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0890",
+        id: "cp_async_bulk_prefetch_tensor_3d_l2",
+        abi_id: "i0890",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_3d_l2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_3D",
+            asm: "cp.async.bulk.prefetch.tensor.3d.L2.global.tile [$tmap, {{$d0, $d1, $d2}}];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 5,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg5>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0891",
+        id: "cp_async_bulk_prefetch_tensor_4d_l2",
+        abi_id: "i0891",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_4d_l2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_4D",
+            asm: "cp.async.bulk.prefetch.tensor.4d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3}}];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 6,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg6>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0892",
+        id: "cp_async_bulk_prefetch_tensor_5d_l2",
+        abi_id: "i0892",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_5d_l2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_5D",
+            asm: "cp.async.bulk.prefetch.tensor.5d.L2.global.tile [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 7,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0893",
+        id: "cp_async_bulk_prefetch_tensor_gather4_2d_l2",
+        abi_id: "i0893",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_GATHER4_2D",
+            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4 [$tmap, {{$d0, $d1, $d2, $d3, $d4}}];",
+            predicates: &["Subtarget->hasTMABlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 7,
+                    value: 0,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0894",
+        id: "tensormap_replace_box_dim",
+        abi_id: "i0894",
+        dialect_op: "nvvm.tensormap_replace_box_dim",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0895",
+        id: "tensormap_replace_element_stride",
+        abi_id: "i0895",
+        dialect_op: "nvvm.tensormap_replace_element_stride",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0896",
+        id: "tensormap_replace_element_type",
+        abi_id: "i0896",
+        dialect_op: "nvvm.tensormap_replace_element_type",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ArgInfo<arg1>",
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "Range<arg1,0,16>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0897",
+        id: "tensormap_replace_fill_mode",
+        abi_id: "i0897",
+        dialect_op: "nvvm.tensormap_replace_fill_mode",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ArgInfo<arg1>",
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "Range<arg1,0,2>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0898",
+        id: "tensormap_replace_global_address",
+        abi_id: "i0898",
+        dialect_op: "nvvm.tensormap_replace_global_address",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrArgMemOnly", "IntrWriteMem", "NoCapture<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0899",
+        id: "tensormap_replace_global_dim",
+        abi_id: "i0899",
+        dialect_op: "nvvm.tensormap_replace_global_dim",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0900",
+        id: "tensormap_replace_global_stride",
+        abi_id: "i0900",
+        dialect_op: "nvvm.tensormap_replace_global_stride",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0901",
+        id: "tensormap_replace_interleave_layout",
+        abi_id: "i0901",
+        dialect_op: "nvvm.tensormap_replace_interleave_layout",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ArgInfo<arg1>",
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "Range<arg1,0,3>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0902",
+        id: "tensormap_replace_rank",
+        abi_id: "i0902",
+        dialect_op: "nvvm.tensormap_replace_rank",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrArgMemOnly", "IntrWriteMem", "NoCapture<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0903",
+        id: "tensormap_replace_swizzle_atomicity",
+        abi_id: "i0903",
+        dialect_op: "nvvm.tensormap_replace_swizzle_atomicity",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ArgInfo<arg1>",
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "Range<arg1,0,4>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0904",
+        id: "tensormap_replace_swizzle_mode",
+        abi_id: "i0904",
+        dialect_op: "nvvm.tensormap_replace_swizzle_mode",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::FamilyTarget(100),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::FamilyTarget(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+                GeneratedHardwareAlternative::FamilyTarget(110),
+                GeneratedHardwareAlternative::ExactArchitecture(120),
+                GeneratedHardwareAlternative::FamilyTarget(120),
+                GeneratedHardwareAlternative::ExactArchitecture(121),
+                GeneratedHardwareAlternative::FamilyTarget(121),
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::FamilyTarget(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::FamilyTarget(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                        GeneratedHardwareAlternative::FamilyTarget(110),
+                        GeneratedHardwareAlternative::ExactArchitecture(120),
+                        GeneratedHardwareAlternative::FamilyTarget(120),
+                        GeneratedHardwareAlternative::ExactArchitecture(121),
+                        GeneratedHardwareAlternative::FamilyTarget(121),
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ArgInfo<arg1>",
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrWriteMem",
+                "NoCapture<arg0>",
+                "Range<arg1,0,5>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0905",
+        id: "fence_proxy_tensormap_generic_acquire_cluster",
+        abi_id: "i0905",
+        dialect_op: "nvvm.fence_proxy_tensormap_generic_acquire_cluster",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CLUSTER",
+            asm: "fence.proxy.tensormap::generic.acquire.cluster [$addr], 128;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "Range<arg1,128,129>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0906",
+        id: "fence_proxy_tensormap_generic_acquire_cta",
+        abi_id: "i0906",
+        dialect_op: "nvvm.fence_proxy_tensormap_generic_acquire_cta",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CTA",
+            asm: "fence.proxy.tensormap::generic.acquire.cta [$addr], 128;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "Range<arg1,128,129>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0907",
+        id: "fence_proxy_tensormap_generic_acquire_gpu",
+        abi_id: "i0907",
+        dialect_op: "nvvm.fence_proxy_tensormap_generic_acquire_gpu",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_GPU",
+            asm: "fence.proxy.tensormap::generic.acquire.gpu [$addr], 128;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "Range<arg1,128,129>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0908",
+        id: "fence_proxy_tensormap_generic_acquire_system",
+        abi_id: "i0908",
+        dialect_op: "nvvm.fence_proxy_tensormap_generic_acquire_system",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_SYS",
+            asm: "fence.proxy.tensormap::generic.acquire.sys [$addr], 128;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg1>",
+                "IntrArgMemOnly",
+                "IntrNoCallback",
+                "Range<arg1,128,129>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0909",
+        id: "fence_proxy_tensormap_generic_release_cluster",
+        abi_id: "i0909",
+        dialect_op: "nvvm.fence_proxy_tensormap_generic_release_cluster",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CLUSTER",
+            asm: "fence.proxy.tensormap::generic.release.cluster;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0910",
+        id: "fence_proxy_tensormap_generic_release_cta",
+        abi_id: "i0910",
+        dialect_op: "nvvm.fence_proxy_tensormap_generic_release_cta",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CTA",
+            asm: "fence.proxy.tensormap::generic.release.cta;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0911",
+        id: "fence_proxy_tensormap_generic_release_gpu",
+        abi_id: "i0911",
+        dialect_op: "nvvm.fence_proxy_tensormap_generic_release_gpu",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_GPU",
+            asm: "fence.proxy.tensormap::generic.release.gpu;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0912",
+        id: "fence_proxy_tensormap_generic_release_system",
+        abi_id: "i0912",
+        dialect_op: "nvvm.fence_proxy_tensormap_generic_release_system",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(83),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_SYS",
+            asm: "fence.proxy.tensormap::generic.release.sys;",
+            predicates: &[
+                "Subtarget->getSmVersion() >= 90",
+                "Subtarget->getPTXVersion() >= 83",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrNoCallback"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0917",
+        id: "cp_async_bulk_prefetch_tensor_1d_l2_cache_hint",
+        abi_id: "i0917",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_1d_l2_cache_hint",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_1D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.1d.L2.global.tile.L2::cache_hint [$tmap, {{$d0}}], $ch;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 3,
+                    value: -1,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg3>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0918",
+        id: "cp_async_bulk_prefetch_tensor_2d_l2_cache_hint",
+        abi_id: "i0918",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_2d_l2_cache_hint",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_2D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1}}], $ch;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 4,
+                    value: -1,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg4>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0919",
+        id: "cp_async_bulk_prefetch_tensor_3d_l2_cache_hint",
+        abi_id: "i0919",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_3d_l2_cache_hint",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_3D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.3d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2}}], $ch;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 5,
+                    value: -1,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg5>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0920",
+        id: "cp_async_bulk_prefetch_tensor_4d_l2_cache_hint",
+        abi_id: "i0920",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_4d_l2_cache_hint",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_4D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.4d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3}}], $ch;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 6,
+                    value: -1,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg6>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0921",
+        id: "cp_async_bulk_prefetch_tensor_5d_l2_cache_hint",
+        abi_id: "i0921",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_5d_l2_cache_hint",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_5D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.5d.L2.global.tile.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 80",
+                "Subtarget->getSmVersion() >= 90",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 7,
+                    value: -1,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0922",
+        id: "cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint",
+        abi_id: "i0922",
+        dialect_op: "nvvm.cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(100),
+                GeneratedHardwareAlternative::ExactArchitecture(101),
+                GeneratedHardwareAlternative::ExactArchitecture(103),
+                GeneratedHardwareAlternative::ExactArchitecture(110),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(100),
+                        GeneratedHardwareAlternative::ExactArchitecture(101),
+                        GeneratedHardwareAlternative::ExactArchitecture(103),
+                        GeneratedHardwareAlternative::ExactArchitecture(110),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "TMA_TENSOR_PF_TILE_GATHER4_2D_CH",
+            asm: "cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4.L2::cache_hint [$tmap, {{$d0, $d1, $d2, $d3, $d4}}], $ch;",
+            predicates: &["Subtarget->hasTMABlackwellSupport()"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[GeneratedImmediateBinding {
+                    argument_index: 7,
+                    value: -1,
+                }],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg7>", "IntrConvergent", "ReadOnly<arg0>"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0923",
+        id: "cp_async_bulk_tensor_reduce_add_tile_1d",
+        abi_id: "i0923",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_tile_1d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg4>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0924",
+        id: "cp_async_bulk_tensor_reduce_add_tile_2d",
+        abi_id: "i0924",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_tile_2d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0925",
+        id: "cp_async_bulk_tensor_reduce_add_tile_3d",
+        abi_id: "i0925",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_tile_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0926",
+        id: "cp_async_bulk_tensor_reduce_add_tile_4d",
+        abi_id: "i0926",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_tile_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0927",
+        id: "cp_async_bulk_tensor_reduce_add_tile_5d",
+        abi_id: "i0927",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_tile_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0928",
+        id: "cp_async_bulk_tensor_reduce_add_im2col_3d",
+        abi_id: "i0928",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_im2col_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0929",
+        id: "cp_async_bulk_tensor_reduce_add_im2col_4d",
+        abi_id: "i0929",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_im2col_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0930",
+        id: "cp_async_bulk_tensor_reduce_add_im2col_5d",
+        abi_id: "i0930",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_add_im2col_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0931",
+        id: "cp_async_bulk_tensor_reduce_and_tile_1d",
+        abi_id: "i0931",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_tile_1d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg4>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0932",
+        id: "cp_async_bulk_tensor_reduce_and_tile_2d",
+        abi_id: "i0932",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_tile_2d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0933",
+        id: "cp_async_bulk_tensor_reduce_and_tile_3d",
+        abi_id: "i0933",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_tile_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0934",
+        id: "cp_async_bulk_tensor_reduce_and_tile_4d",
+        abi_id: "i0934",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_tile_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0935",
+        id: "cp_async_bulk_tensor_reduce_and_tile_5d",
+        abi_id: "i0935",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_tile_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0936",
+        id: "cp_async_bulk_tensor_reduce_and_im2col_3d",
+        abi_id: "i0936",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_im2col_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0937",
+        id: "cp_async_bulk_tensor_reduce_and_im2col_4d",
+        abi_id: "i0937",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_im2col_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0938",
+        id: "cp_async_bulk_tensor_reduce_and_im2col_5d",
+        abi_id: "i0938",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_and_im2col_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0939",
+        id: "cp_async_bulk_tensor_reduce_dec_tile_1d",
+        abi_id: "i0939",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_tile_1d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg4>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0940",
+        id: "cp_async_bulk_tensor_reduce_dec_tile_2d",
+        abi_id: "i0940",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_tile_2d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0941",
+        id: "cp_async_bulk_tensor_reduce_dec_tile_3d",
+        abi_id: "i0941",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_tile_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0942",
+        id: "cp_async_bulk_tensor_reduce_dec_tile_4d",
+        abi_id: "i0942",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_tile_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0943",
+        id: "cp_async_bulk_tensor_reduce_dec_tile_5d",
+        abi_id: "i0943",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_tile_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0944",
+        id: "cp_async_bulk_tensor_reduce_dec_im2col_3d",
+        abi_id: "i0944",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0945",
+        id: "cp_async_bulk_tensor_reduce_dec_im2col_4d",
+        abi_id: "i0945",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0946",
+        id: "cp_async_bulk_tensor_reduce_dec_im2col_5d",
+        abi_id: "i0946",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_dec_im2col_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0947",
+        id: "cp_async_bulk_tensor_reduce_inc_tile_1d",
+        abi_id: "i0947",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_tile_1d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg4>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0948",
+        id: "cp_async_bulk_tensor_reduce_inc_tile_2d",
+        abi_id: "i0948",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_tile_2d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0949",
+        id: "cp_async_bulk_tensor_reduce_inc_tile_3d",
+        abi_id: "i0949",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_tile_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0950",
+        id: "cp_async_bulk_tensor_reduce_inc_tile_4d",
+        abi_id: "i0950",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_tile_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0951",
+        id: "cp_async_bulk_tensor_reduce_inc_tile_5d",
+        abi_id: "i0951",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_tile_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0952",
+        id: "cp_async_bulk_tensor_reduce_inc_im2col_3d",
+        abi_id: "i0952",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0953",
+        id: "cp_async_bulk_tensor_reduce_inc_im2col_4d",
+        abi_id: "i0953",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0954",
+        id: "cp_async_bulk_tensor_reduce_inc_im2col_5d",
+        abi_id: "i0954",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_inc_im2col_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0955",
+        id: "cp_async_bulk_tensor_reduce_max_tile_1d",
+        abi_id: "i0955",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_tile_1d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg4>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0956",
+        id: "cp_async_bulk_tensor_reduce_max_tile_2d",
+        abi_id: "i0956",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_tile_2d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0957",
+        id: "cp_async_bulk_tensor_reduce_max_tile_3d",
+        abi_id: "i0957",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_tile_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0958",
+        id: "cp_async_bulk_tensor_reduce_max_tile_4d",
+        abi_id: "i0958",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_tile_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0959",
+        id: "cp_async_bulk_tensor_reduce_max_tile_5d",
+        abi_id: "i0959",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_tile_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0960",
+        id: "cp_async_bulk_tensor_reduce_max_im2col_3d",
+        abi_id: "i0960",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_im2col_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0961",
+        id: "cp_async_bulk_tensor_reduce_max_im2col_4d",
+        abi_id: "i0961",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_im2col_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0962",
+        id: "cp_async_bulk_tensor_reduce_max_im2col_5d",
+        abi_id: "i0962",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_max_im2col_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0963",
+        id: "cp_async_bulk_tensor_reduce_min_tile_1d",
+        abi_id: "i0963",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_tile_1d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg4>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0964",
+        id: "cp_async_bulk_tensor_reduce_min_tile_2d",
+        abi_id: "i0964",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_tile_2d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0965",
+        id: "cp_async_bulk_tensor_reduce_min_tile_3d",
+        abi_id: "i0965",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_tile_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0966",
+        id: "cp_async_bulk_tensor_reduce_min_tile_4d",
+        abi_id: "i0966",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_tile_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0967",
+        id: "cp_async_bulk_tensor_reduce_min_tile_5d",
+        abi_id: "i0967",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_tile_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0968",
+        id: "cp_async_bulk_tensor_reduce_min_im2col_3d",
+        abi_id: "i0968",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_im2col_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0969",
+        id: "cp_async_bulk_tensor_reduce_min_im2col_4d",
+        abi_id: "i0969",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_im2col_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0970",
+        id: "cp_async_bulk_tensor_reduce_min_im2col_5d",
+        abi_id: "i0970",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_min_im2col_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0971",
+        id: "cp_async_bulk_tensor_reduce_or_tile_1d",
+        abi_id: "i0971",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_tile_1d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg4>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0972",
+        id: "cp_async_bulk_tensor_reduce_or_tile_2d",
+        abi_id: "i0972",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_tile_2d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0973",
+        id: "cp_async_bulk_tensor_reduce_or_tile_3d",
+        abi_id: "i0973",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_tile_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0974",
+        id: "cp_async_bulk_tensor_reduce_or_tile_4d",
+        abi_id: "i0974",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_tile_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0975",
+        id: "cp_async_bulk_tensor_reduce_or_tile_5d",
+        abi_id: "i0975",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_tile_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0976",
+        id: "cp_async_bulk_tensor_reduce_or_im2col_3d",
+        abi_id: "i0976",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_im2col_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0977",
+        id: "cp_async_bulk_tensor_reduce_or_im2col_4d",
+        abi_id: "i0977",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_im2col_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0978",
+        id: "cp_async_bulk_tensor_reduce_or_im2col_5d",
+        abi_id: "i0978",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_or_im2col_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0979",
+        id: "cp_async_bulk_tensor_reduce_xor_tile_1d",
+        abi_id: "i0979",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_tile_1d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg4>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0980",
+        id: "cp_async_bulk_tensor_reduce_xor_tile_2d",
+        abi_id: "i0980",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_tile_2d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg5>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0981",
+        id: "cp_async_bulk_tensor_reduce_xor_tile_3d",
+        abi_id: "i0981",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_tile_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0982",
+        id: "cp_async_bulk_tensor_reduce_xor_tile_4d",
+        abi_id: "i0982",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_tile_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0983",
+        id: "cp_async_bulk_tensor_reduce_xor_tile_5d",
+        abi_id: "i0983",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_tile_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0984",
+        id: "cp_async_bulk_tensor_reduce_xor_im2col_3d",
+        abi_id: "i0984",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_3d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg6>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0985",
+        id: "cp_async_bulk_tensor_reduce_xor_im2col_4d",
+        abi_id: "i0985",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_4d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg7>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0986",
+        id: "cp_async_bulk_tensor_reduce_xor_im2col_5d",
+        abi_id: "i0986",
+        dialect_op: "nvvm.cp_async_bulk_tensor_reduce_xor_im2col_5d",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                90,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "ImmArg<arg8>",
+                "IntrConvergent",
+                "ReadOnly<arg0>",
+                "ReadOnly<arg1>",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs
new file mode 100644
index 0000000000..f666040e4e
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs
@@ -0,0 +1,215 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `vote` intrinsics.
+
+use super::{
+    GeneratedHardwareAlternative, GeneratedHardwareTarget, GeneratedIntrinsicTarget,
+    GeneratedIntrinsicVariant, GeneratedLlvmFacts, GeneratedPtxVersion,
+    GeneratedSelectionAlternative, GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0040",
+        id: "all_sync",
+        abi_id: "i0040",
+        dialect_op: "nvvm.vote_sync_all",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_ALLi",
+                asm: "vote.sync.all.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_ALLr",
+                asm: "vote.sync.all.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0041",
+        id: "any_sync",
+        abi_id: "i0041",
+        dialect_op: "nvvm.vote_sync_any",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_ANYi",
+                asm: "vote.sync.any.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_ANYr",
+                asm: "vote.sync.any.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0042",
+        id: "ballot_sync",
+        abi_id: "i0042",
+        dialect_op: "nvvm.vote_sync_ballot",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_BALLOTi",
+                asm: "vote.sync.ballot.b32 \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_BALLOTr",
+                asm: "vote.sync.ballot.b32 \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0043",
+        id: "uni_sync",
+        abi_id: "i0043",
+        dialect_op: "nvvm.vote_sync_uni",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_UNIi",
+                asm: "vote.sync.uni.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "VOTE_SYNC_UNIr",
+                asm: "vote.sync.uni.pred \t$dest, $pred, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs
new file mode 100644
index 0000000000..820b012719
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs
@@ -0,0 +1,80 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `warp_barrier` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[GeneratedIntrinsicTarget {
+    marker: "v1:i0049",
+    id: "sync_mask",
+    abi_id: "i0049",
+    dialect_op: "nvvm.bar_warp_sync",
+    variant: GeneratedIntrinsicVariant::Scalar,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+        hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]),
+    },
+    backend_requirements: &[
+        GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LlvmNvptx,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(30),
+                ]),
+            },
+        },
+        GeneratedBackendRequirement {
+            backend: GeneratedIntrinsicBackend::LibNvvm,
+            requirement: GeneratedTargetRequirement {
+                minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                hardware: GeneratedHardwareTarget::AnyOf(&[
+                    GeneratedHardwareAlternative::MinimumSm(75),
+                ]),
+            },
+        },
+    ],
+    selections: &[
+        GeneratedSelectionAlternative {
+            source_record: "INT_BAR_WARP_SYNC_I",
+            asm: "bar.warp.sync \t$i;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 60",
+                "Subtarget->getSmVersion() >= 30",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        },
+        GeneratedSelectionAlternative {
+            source_record: "INT_BAR_WARP_SYNC_R",
+            asm: "bar.warp.sync \t$i;",
+            predicates: &[
+                "Subtarget->getPTXVersion() >= 60",
+                "Subtarget->getSmVersion() >= 30",
+            ],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        },
+    ],
+    llvm: Some(GeneratedLlvmFacts {
+        properties: &["IntrConvergent", "IntrNoCallback"],
+        result_no_undef: false,
+        result_range: None,
+    }),
+}];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs
new file mode 100644
index 0000000000..4e768ef9f2
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs
@@ -0,0 +1,311 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `warp_match` intrinsics.
+
+use super::{
+    GeneratedHardwareAlternative, GeneratedHardwareTarget, GeneratedIntrinsicTarget,
+    GeneratedIntrinsicVariant, GeneratedLlvmFacts, GeneratedPtxVersion,
+    GeneratedSelectionAlternative, GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0045",
+        id: "match_any_sync",
+        abi_id: "i0045",
+        dialect_op: "nvvm.match_any_sync_i32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_32ii",
+                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_32ir",
+                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_32ri",
+                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_32rr",
+                asm: "match.any.sync.b32 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0046",
+        id: "match_any_i64_sync",
+        abi_id: "i0046",
+        dialect_op: "nvvm.match_any_sync_i64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_64ii",
+                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_64ir",
+                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_64ri",
+                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ANY_SYNC_64rr",
+                asm: "match.any.sync.b64 \t$dest, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0047",
+        id: "match_all_sync",
+        abi_id: "i0047",
+        dialect_op: "nvvm.match_all_sync_i32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_32ii",
+                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_32ir",
+                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_32ri",
+                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_32rr",
+                asm: "match.all.sync.b32 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0048",
+        id: "match_all_i64_sync",
+        abi_id: "i0048",
+        dialect_op: "nvvm.match_all_sync_i64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                70,
+            )]),
+        },
+        backend_requirements: &[],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_64ii",
+                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_64ir",
+                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_64ri",
+                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "MATCH_ALLP_SYNC_64rr",
+                asm: "match.all.sync.b64 \t$dest|$pred, $value, $mask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 70",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs
new file mode 100644
index 0000000000..3d37afaa88
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs
@@ -0,0 +1,1280 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `warp_shuffle` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0050",
+        id: "shuffle_sync",
+        abi_id: "i0050",
+        dialect_op: "nvvm.shfl_sync_idx_i32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14989",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14990",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14991",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14992",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14993",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14994",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14995",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14996",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0051",
+        id: "shuffle_xor_sync",
+        abi_id: "i0051",
+        dialect_op: "nvvm.shfl_sync_bfly_i32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14957",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14958",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14959",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14960",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14961",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14962",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14963",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14964",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0052",
+        id: "shuffle_down_sync",
+        abi_id: "i0052",
+        dialect_op: "nvvm.shfl_sync_down_i32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14925",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14926",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14927",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14928",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14929",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14930",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14931",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14932",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0053",
+        id: "shuffle_up_sync",
+        abi_id: "i0053",
+        dialect_op: "nvvm.shfl_sync_up_i32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14893",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14894",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14895",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14896",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14897",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14898",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14899",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14900",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0054",
+        id: "shuffle_f32_sync",
+        abi_id: "i0054",
+        dialect_op: "nvvm.shfl_sync_idx_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15005",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15006",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15007",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15008",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15009",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15010",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15011",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_15012",
+                asm: "shfl.sync.idx.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0055",
+        id: "shuffle_xor_f32_sync",
+        abi_id: "i0055",
+        dialect_op: "nvvm.shfl_sync_bfly_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14973",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14974",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14975",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14976",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14977",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14978",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14979",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14980",
+                asm: "shfl.sync.bfly.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0056",
+        id: "shuffle_down_f32_sync",
+        abi_id: "i0056",
+        dialect_op: "nvvm.shfl_sync_down_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14941",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14942",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14943",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14944",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14945",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14946",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14947",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14948",
+                asm: "shfl.sync.down.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0057",
+        id: "shuffle_up_f32_sync",
+        abi_id: "i0057",
+        dialect_op: "nvvm.shfl_sync_up_f32",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14909",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14910",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14911",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14912",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14913",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14914",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14915",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+            GeneratedSelectionAlternative {
+                source_record: "anonymous_14916",
+                asm: "shfl.sync.up.b32 \t$dst, $src, $offset, $mask, $threadmask;",
+                predicates: &[
+                    "Subtarget->getPTXVersion() >= 60",
+                    "Subtarget->getSmVersion() >= 30",
+                ],
+                constraints: GeneratedSelectionConstraints {
+                    address_space: None,
+                    immediate_bindings: &[],
+                },
+            },
+        ],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &[
+                "IntrConvergent",
+                "IntrInaccessibleMemOnly",
+                "IntrNoCallback",
+            ],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0058",
+        id: "shuffle_u64_sync",
+        abi_id: "i0058",
+        dialect_op: "nvvm.shfl_sync_idx_i64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0059",
+        id: "shuffle_xor_u64_sync",
+        abi_id: "i0059",
+        dialect_op: "nvvm.shfl_sync_bfly_i64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0060",
+        id: "shuffle_down_u64_sync",
+        abi_id: "i0060",
+        dialect_op: "nvvm.shfl_sync_down_i64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0061",
+        id: "shuffle_up_u64_sync",
+        abi_id: "i0061",
+        dialect_op: "nvvm.shfl_sync_up_i64",
+        variant: GeneratedIntrinsicVariant::Scalar,
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+            hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(
+                30,
+            )]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(30),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(60),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::MinimumSm(75),
+                    ]),
+                },
+            },
+        ],
+        selections: &[],
+        llvm: None,
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs
new file mode 100644
index 0000000000..5ff9ec0dd2
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs
@@ -0,0 +1,167 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated intrinsic target records: `wgmma_control` intrinsics.
+
+use super::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedLlvmFacts, GeneratedPtxVersion, GeneratedSelectionAlternative,
+    GeneratedSelectionConstraints, GeneratedTargetRequirement, GeneratedWgmmaControlMode,
+};
+
+pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0317",
+        id: "wgmma_fence",
+        abi_id: "i0317",
+        dialect_op: "nvvm.wgmma_fence_sync_aligned",
+        variant: GeneratedIntrinsicVariant::WgmmaControl {
+            mode: GeneratedWgmmaControlMode::Fence,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "WGMMA_FENCE_SYNC_ALIGNED",
+            asm: "wgmma.fence.sync.aligned;",
+            predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0318",
+        id: "wgmma_commit_group",
+        abi_id: "i0318",
+        dialect_op: "nvvm.wgmma_commit_group_sync_aligned",
+        variant: GeneratedIntrinsicVariant::WgmmaControl {
+            mode: GeneratedWgmmaControlMode::CommitGroup,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "WGMMA_COMMIT_GROUP_SYNC_ALIGNED",
+            asm: "wgmma.commit_group.sync.aligned;",
+            predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["IntrConvergent"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+    GeneratedIntrinsicTarget {
+        marker: "v1:i0319",
+        id: "wgmma_wait_group",
+        abi_id: "i0319",
+        dialect_op: "nvvm.wgmma_wait_group_sync_aligned",
+        variant: GeneratedIntrinsicVariant::WgmmaControl {
+            mode: GeneratedWgmmaControlMode::WaitGroup,
+        },
+        requirement: GeneratedTargetRequirement {
+            minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+            hardware: GeneratedHardwareTarget::AnyOf(&[
+                GeneratedHardwareAlternative::ExactArchitecture(90),
+            ]),
+        },
+        backend_requirements: &[
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LlvmNvptx,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+            GeneratedBackendRequirement {
+                backend: GeneratedIntrinsicBackend::LibNvvm,
+                requirement: GeneratedTargetRequirement {
+                    minimum_ptx: GeneratedPtxVersion::from_encoded(80),
+                    hardware: GeneratedHardwareTarget::AnyOf(&[
+                        GeneratedHardwareAlternative::ExactArchitecture(90),
+                    ]),
+                },
+            },
+        ],
+        selections: &[GeneratedSelectionAlternative {
+            source_record: "WGMMA_WAIT_GROUP_SYNC_ALIGNED",
+            asm: "wgmma.wait_group.sync.aligned \t$n;",
+            predicates: &["Subtarget->getPTXVersion() >= 80", "hasSM90a"],
+            constraints: GeneratedSelectionConstraints {
+                address_space: None,
+                immediate_bindings: &[],
+            },
+        }],
+        llvm: Some(GeneratedLlvmFacts {
+            properties: &["ImmArg<arg0>", "IntrConvergent"],
+            result_no_undef: false,
+            result_range: None,
+        }),
+    },
+];
diff --git a/crates/cuda-oxide-codegen/src/target.rs b/crates/cuda-oxide-codegen/src/target.rs
deleted file mode 100644
index 329eb45aa3..0000000000
--- a/crates/cuda-oxide-codegen/src/target.rs
+++ /dev/null
@@ -1,5209 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-//! Architecture feature detection and PTX target selection.
-//!
-//! Detects the architecture and PTX-ISA requirements of exported LLVM IR and
-//! selects the minimum `sm_XX` that can lower them. The backend owns this so an
-//! experimental frontend gets the same target selection as the Rust MIR path
-//! in `mir-importer`.
-
-use crate::error::PipelineError;
-use crate::generated::{
-    GeneratedModuleRequirements, GeneratedResolvedRequirement, GeneratedResolvedTarget,
-};
-use crate::generated_intrinsic_targets::{
-    GeneratedHardwareAlternative, GeneratedHardwareTarget, GeneratedTargetContract,
-    GeneratedTargetRequirement,
-};
-#[cfg(test)]
-use cuda_target_spec::RECORDED_PTX_FLOORS;
-use cuda_target_spec::{PTX_ISA_SPELLINGS, recorded_ptx_floor, spelling_at_least};
-use libnvvm_sys::CudaArch;
-use std::path::Path;
-
-fn contains_wgmma_features(contents: &str) -> bool {
-    contents.contains("wgmma.fence")
-        || contents.contains("wgmma.commit_group")
-        || contents.contains("wgmma.wait_group")
-        || contents.contains("wgmma.mma_async")
-}
-
-/// Checks for Thread Block Cluster instructions (sm_90+).
-///
-/// Cluster features require Hopper (sm_90) or newer:
-/// - Cluster special registers (%cluster_ctaid, %cluster_nctaid)
-/// - Cluster synchronization (cluster.sync)
-/// - Distributed shared memory (mapa.shared::cluster)
-fn contains_cluster_features(contents: &str) -> bool {
-    // Cluster special registers
-    contents.contains("cluster_ctaid")
-        || contents.contains("cluster_nctaid")
-        || contents.contains("cluster_ctarank")
-        || contents.contains("cluster_nctarank")
-        || contents.contains("%clusterid")
-        || contents.contains("%nclusterid")
-        || contents.contains("%is_explicit_cluster")
-        || contents.contains("!\"cluster_dim_x\"")
-        || contents.contains("!\"cluster_dim_y\"")
-        || contents.contains("!\"cluster_dim_z\"")
-        // Cluster synchronization
-        || contents.contains("cluster.sync")
-        || contents.contains("barrier.cluster.")
-        // Distributed shared memory
-        || contents.contains("mapa.shared::cluster")
-        || contents.contains(".shared::cluster")
-        || contains_cluster_fence_features(contents)
-        || contains_cluster_scoped_memory_features(contents)
-}
-
-fn contains_cluster_fence_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        statement.contains("fence.sc.cluster")
-            || statement.contains("fence.acq_rel.cluster")
-            || statement.contains("fence.acquire.cluster")
-            || statement.contains("fence.release.cluster")
-    })
-}
-
-fn contains_cluster_scoped_memory_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        !statement.contains("multimem.")
-            && statement.contains(".cluster.")
-            && ["ld.", "st.", "atom.", "red."]
-                .iter()
-                .any(|mnemonic| statement.contains(mnemonic))
-    })
-}
-
-/// Checks the one-way fence semantics added in PTX 8.6.
-///
-/// Unlike the older `.sc` / `.acq_rel` forms, `.acquire` and `.release`
-/// require sm_90 for every scope, not just `.cluster`.
-fn contains_fence_acquire_release_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        statement.contains("fence.acquire.") || statement.contains("fence.release.")
-    })
-}
-
-/// Checks the multimem instruction family introduced for sm_90.
-///
-/// Base forms need PTX 8.1. The pipeline currently has no 8.1 feature switch,
-/// so PTX 8.6 is the nearest conservative version supported by LLVM.
-fn contains_multimem_features(contents: &str) -> bool {
-    contents.split(';').any(is_multimem_instruction)
-}
-
-fn is_multimem_instruction(statement: &str) -> bool {
-    ["multimem.ld_reduce", "multimem.st", "multimem.red"]
-        .iter()
-        .any(|instruction| statement.contains(instruction))
-}
-
-/// Checks PTX 8.6 multimem formats that require a Blackwell family target.
-fn contains_multimem_blackwell_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        is_multimem_instruction(statement)
-            && [".e4m3", ".e5m2", ".acc::f16"]
-                .iter()
-                .any(|qualifier| statement.contains(qualifier))
-    })
-}
-
-/// Checks the PTX 8.6 floating-point extension to `redux.sync`.
-fn contains_redux_f32_features(contents: &str) -> bool {
-    contents
-        .split(';')
-        .any(|statement| statement.contains("redux.sync") && statement.contains(".f32"))
-}
-
-/// Checks for forward-compatible instructions whose minimum target is sm_90.
-///
-/// Keep this category architecture-neutral: unlike WGMMA, these instructions
-/// are not Hopper-specific and remain available on newer architectures.
-fn contains_sm90_features(contents: &str) -> bool {
-    ["add.rn.bf16x2", "sub.rn.bf16x2", "mul.rn.bf16x2"]
-        .iter()
-        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
-        || contains_packed_bf16_atomic_features(contents)
-        || contains_stmatrix_features(contents)
-        || contains_elect_features(contents)
-        || contains_fence_acquire_release_features(contents)
-        || contains_multimem_features(contents)
-}
-
-/// Native two-lane f32 arithmetic requires PTX 8.6 and sm_100+.
-///
-/// Match the instruction family rather than cuda-oxide's currently emitted
-/// spelling. External LLVM IR can contain any valid rounding/FTZ modifier
-/// combination and must receive the same target floor.
-fn contains_f32x2_features(contents: &str) -> bool {
-    contains_instruction_family_modifier(contents, &["add", "sub", "mul", "fma"], "f32x2")
-}
-
-/// Native packed bf16 atomic add was added in PTX 7.8 for sm_90.
-fn contains_packed_bf16_atomic_features(contents: &str) -> bool {
-    contains_instruction_mnemonic(contents, "atom.global.add.noftz.bf16x2")
-}
-
-/// Packed f16 atomic add needs PTX 6.2. Its hardware floor predates
-/// cuda-oxide's Volta floor, so only the independent PTX ISA requirement must
-/// be raised.
-fn contains_packed_f16_atomic_features(contents: &str) -> bool {
-    contains_instruction_mnemonic(contents, "atom.global.add.noftz.f16x2")
-}
-
-fn contains_elect_features(contents: &str) -> bool {
-    contents.contains("elect.sync")
-}
-
-/// Checks for the register-only 8x8 matrix transpose (PTX 7.8, sm_75+).
-fn contains_movmatrix_features(contents: &str) -> bool {
-    contains_instruction_mnemonic(contents, "movmatrix.sync.aligned.m8n8.trans.b16")
-}
-
-/// Checks the dense BF16 MMA form added by the typed device intrinsic.
-///
-/// MMA shapes and types have different architecture and PTX ISA floors, so
-/// this intentionally matches the complete operation-specific mnemonic.
-fn contains_mma_m16n8k16_f32_bf16_features(contents: &str) -> bool {
-    contains_instruction_mnemonic(
-        contents,
-        "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32",
-    )
-}
-
-/// Checks for the Ampere TF32 MMA operation (PTX 7.0, sm_80+).
-fn contains_mma_m16n8k8_f32_tf32_features(contents: &str) -> bool {
-    contains_instruction_mnemonic(
-        contents,
-        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32",
-    )
-}
-
-/// Checks the dense Ampere INT8 MMA forms (PTX 7.0, sm_80+).
-fn contains_dense_int8_mma_features(contents: &str) -> bool {
-    const MNEMONICS: &[&str] = &[
-        "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32",
-        "mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32",
-        "mma.sync.aligned.m16n8k16.row.col.s32.u8.s8.s32",
-        "mma.sync.aligned.m16n8k16.row.col.s32.u8.u8.s32",
-        "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.s8.s32",
-        "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32",
-        "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.s8.s32",
-        "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.u8.s32",
-        "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32",
-        "mma.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32",
-        "mma.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32",
-        "mma.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32",
-        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32",
-        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32",
-        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32",
-        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32",
-    ];
-
-    MNEMONICS
-        .iter()
-        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
-}
-
-/// Checks the m8n8k16 INT8 MMA forms (PTX 6.5, sm_75+).
-fn contains_mma_m8n8k16_int8_features(contents: &str) -> bool {
-    const MNEMONICS: &[&str] = &[
-        "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32",
-        "mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32",
-        "mma.sync.aligned.m8n8k16.row.col.s32.u8.s8.s32",
-        "mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32",
-        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s8.s32",
-        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32",
-        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32",
-        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.u8.s32",
-    ];
-
-    MNEMONICS
-        .iter()
-        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
-}
-
-/// Checks the m8n8k32 INT4 MMA forms (PTX 6.5, sm_75+).
-fn contains_mma_m8n8k32_int4_features(contents: &str) -> bool {
-    const MNEMONICS: &[&str] = &[
-        "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32",
-        "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32",
-        "mma.sync.aligned.m8n8k32.row.col.s32.u4.s4.s32",
-        "mma.sync.aligned.m8n8k32.row.col.s32.u4.u4.s32",
-        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.s4.s32",
-        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32",
-        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32",
-        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32",
-    ];
-
-    MNEMONICS
-        .iter()
-        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
-}
-
-/// Checks the dense Ampere INT4 MMA forms (PTX 7.0, sm_80+).
-fn contains_dense_int4_mma_features(contents: &str) -> bool {
-    const MNEMONICS: &[&str] = &[
-        "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32",
-        "mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32",
-        "mma.sync.aligned.m16n8k32.row.col.s32.u4.s4.s32",
-        "mma.sync.aligned.m16n8k32.row.col.s32.u4.u4.s32",
-        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.s4.s32",
-        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.u4.s32",
-        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32",
-        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.u4.s32",
-        "mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32",
-        "mma.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32",
-        "mma.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32",
-        "mma.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32",
-        "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32",
-        "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32",
-        "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32",
-        "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32",
-    ];
-
-    MNEMONICS
-        .iter()
-        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
-}
-
-const B1_XOR_MMA_MNEMONICS: &[&str] = &[
-    "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc",
-    "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc",
-    "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc",
-];
-
-const B1_AND_MMA_MNEMONICS: &[&str] = &[
-    "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc",
-    "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc",
-    "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc",
-];
-
-/// Checks the three dense binary XOR/POPC MMA forms (PTX 7.0).
-fn contains_b1_xor_mma_features(contents: &str) -> bool {
-    B1_XOR_MMA_MNEMONICS
-        .iter()
-        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
-}
-
-/// Checks the three dense binary AND/POPC MMA forms (PTX 7.1, sm_80+).
-fn contains_b1_and_mma_features(contents: &str) -> bool {
-    B1_AND_MMA_MNEMONICS
-        .iter()
-        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
-}
-
-/// Checks the only dense binary MMA form that can run below sm_80.
-fn contains_mma_m8n8k128_b1_xor_features(contents: &str) -> bool {
-    contains_instruction_mnemonic(contents, B1_XOR_MMA_MNEMONICS[0])
-}
-
-fn contains_sm80_b1_mma_features(contents: &str) -> bool {
-    contains_b1_and_mma_features(contents)
-        || B1_XOR_MMA_MNEMONICS[1..]
-            .iter()
-            .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
-}
-
-/// Checks for the Ampere FP64 tensor-core MMA operation (PTX 7.0, sm_80+).
-fn contains_mma_m8n8k4_f64_features(contents: &str) -> bool {
-    contains_instruction_mnemonic(contents, "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64")
-}
-
-/// Checks the dense F16 MMA form added by the typed device intrinsic.
-///
-/// MMA shapes and types have different architecture and PTX ISA floors, so
-/// this intentionally matches the complete operation-specific mnemonic.
-fn contains_mma_m16n8k16_f32_f16_features(contents: &str) -> bool {
-    contains_instruction_mnemonic(
-        contents,
-        "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32",
-    )
-}
-
-fn contains_instruction_mnemonic(contents: &str, mnemonic: &str) -> bool {
-    contents.match_indices(mnemonic).any(|(index, _)| {
-        let preceding = &contents[..index];
-        let following = &contents[index + mnemonic.len()..];
-        let escapes = ["\\09", "\\0A", "\\0B", "\\0C", "\\0D"];
-        // Use PTX token delimiters rather than treating arbitrary punctuation
-        // as a boundary. In particular, `$` and `%` participate in PTX
-        // identifiers, and guarded opcodes have whitespace after `@{!}p`.
-        let begins_at_instruction_boundary = preceding.is_empty()
-            || preceding
-                .chars()
-                .next_back()
-                .is_some_and(|ch| ch.is_whitespace() || matches!(ch, '"' | ';' | ':' | '{' | '}'))
-            || escapes.iter().any(|escape| preceding.ends_with(escape))
-            || preceding.ends_with("*/");
-        let ends_at_instruction_boundary =
-            following.chars().next().is_some_and(char::is_whitespace)
-                || escapes.iter().any(|escape| following.starts_with(escape));
-        begins_at_instruction_boundary && ends_at_instruction_boundary
-    })
-}
-
-fn contains_instruction_family_modifier(
-    contents: &str,
-    operations: &[&str],
-    required_modifier: &str,
-) -> bool {
-    const ESCAPED_WHITESPACE: [&str; 5] = ["\\09", "\\0A", "\\0B", "\\0C", "\\0D"];
-    operations.iter().any(|operation| {
-        contents.match_indices(operation).any(|(index, _)| {
-            let preceding = &contents[..index];
-            let following = &contents[index + operation.len()..];
-            let begins_at_instruction_boundary = preceding.is_empty()
-                || preceding.chars().next_back().is_some_and(|ch| {
-                    ch.is_whitespace() || matches!(ch, '"' | ';' | ':' | '{' | '}')
-                })
-                || ESCAPED_WHITESPACE
-                    .iter()
-                    .any(|escape| preceding.ends_with(escape))
-                || preceding.ends_with("*/");
-            if !begins_at_instruction_boundary || !following.starts_with('.') {
-                return false;
-            }
-
-            let token_end = following
-                .char_indices()
-                .find_map(|(offset, ch)| {
-                    (ch.is_whitespace() || matches!(ch, '"' | ';')).then_some(offset)
-                })
-                .into_iter()
-                .chain(
-                    ESCAPED_WHITESPACE
-                        .iter()
-                        .filter_map(|escape| following.find(escape)),
-                )
-                .min()
-                .unwrap_or(following.len());
-            following[..token_end]
-                .split('.')
-                .any(|modifier| modifier == required_modifier)
-        })
-    })
-}
-
-/// Checks the full PTX instruction families, including inline `ptx_asm!`
-/// forms that cuda-oxide does not yet expose as typed wrappers.
-///
-/// Broad family matching is intentional. Missing a valid spelling can
-/// silently select an architecture or PTX ISA that is too old; an invalid
-/// spelling still reaches ptxas and fails there after conservative targeting.
-fn contains_ldmatrix_features(contents: &str) -> bool {
-    contents.contains("ldmatrix.sync.aligned.")
-}
-
-fn contains_stmatrix_features(contents: &str) -> bool {
-    contents.contains("stmatrix.sync.aligned.")
-}
-
-/// PTX 8.6 matrix shapes/types have a Blackwell architecture-family floor.
-fn contains_blackwell_matrix_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        let newer_ldmatrix = statement.contains("ldmatrix.sync.aligned.")
-            && [".m16n16.", ".m8n16.", ".b8", ".src_fmt", ".dst_fmt"]
-                .iter()
-                .any(|token| statement.contains(token));
-        let newer_stmatrix = statement.contains("stmatrix.sync.aligned.")
-            && [".m16n8.", ".b8"]
-                .iter()
-                .any(|token| statement.contains(token));
-        newer_ldmatrix || newer_stmatrix
-    })
-}
-
-fn contains_ldmatrix_cta_state_space(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        statement.contains("ldmatrix.sync.aligned.") && statement.contains(".shared::cta.")
-    })
-}
-
-/// Checks for features whose minimum target is sm_80.
-///
-/// This category includes packed bf16 operations introduced on Ampere and
-/// non-bulk asynchronous copies. Match both the PTX spellings used in inline
-/// assembly and the dotted LLVM NVVM intrinsic names for `cp.async`. Bulk and
-/// tensor-copy forms have stronger requirements and are classified first.
-fn contains_sm80_features(contents: &str) -> bool {
-    [
-        "fma.rn.bf16x2",
-        "fma.rn.relu.bf16x2",
-        "min.bf16x2",
-        "max.bf16x2",
-        "neg.bf16x2",
-        "abs.bf16x2",
-    ]
-    .iter()
-    .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
-        || contains_mma_m8n8k4_f64_features(contents)
-        || contents
-            .split(';')
-            .any(|statement| statement.contains("cvt.") && statement.contains(".bf16x2.f32"))
-        || contains_mbarrier_features(contents)
-        || contents.contains("redux.sync")
-        || contents.contains("cp.async.ca.shared")
-        || contents.contains("cp.async.cg.shared")
-        || contents.contains("cp.async.commit_group")
-        || contents.contains("cp.async.commit.group")
-        || contents.contains("cp.async.wait_group")
-        || contents.contains("cp.async.wait.group")
-        || contents.contains("cp.async.wait_all")
-        || contents.contains("cp.async.wait.all")
-        || contains_mma_m16n8k16_f32_bf16_features(contents)
-        || contains_mma_m16n8k16_f32_f16_features(contents)
-        || contains_mma_m16n8k8_f32_tf32_features(contents)
-        || contains_dense_int8_mma_features(contents)
-        || contains_dense_int4_mma_features(contents)
-        || contains_sm80_b1_mma_features(contents)
-}
-
-/// Checks for TMA/mbarrier instructions (Hopper+ compatible with Blackwell).
-///
-/// These instructions work on BOTH Hopper and Blackwell:
-/// - TMA: Tensor Memory Accelerator bulk copies
-/// - mbarrier: Async hardware barriers with transaction tracking
-///
-/// The architecture floor is generic sm_90; automatic cross-compilation keeps
-/// the existing sm_100 default for forward-compatible Blackwell PTX.
-fn contains_tma_features(contents: &str) -> bool {
-    // TMA tensor copies and their commit/wait group controls.
-    contains_cp_async_bulk_features(contents)
-        || contains_mbarrier_sm90_features(contents)
-        || contents.contains("fence.mbarrier_init")
-        // Proxy fence for async operations
-        || contents.contains("fence.proxy.async")
-        || contents.contains(".sync_restrict")
-}
-
-fn contains_cp_async_bulk_features(contents: &str) -> bool {
-    contents.contains("cp.async.bulk.")
-}
-
-fn contains_mbarrier_features(contents: &str) -> bool {
-    contents.contains("mbarrier.") || contents.contains("llvm.nvvm.mbarrier")
-}
-
-fn contains_mbarrier_sm90_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        (statement.contains("mbarrier.") || statement.contains("llvm.nvvm.mbarrier"))
-            && [
-                "try_wait",
-                "expect_tx",
-                "complete_tx",
-                "shared::cluster",
-                ".acquire.",
-                ".release.",
-                ".relaxed",
-            ]
-            .iter()
-            .any(|feature| statement.contains(feature))
-    })
-}
-
-fn contains_mbarrier_ptx71_features(contents: &str) -> bool {
-    contents
-        .split(';')
-        .any(|statement| statement.contains("mbarrier.test_wait") && statement.contains(".parity"))
-}
-
-fn contains_mbarrier_ptx78_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        statement.contains("mbarrier.")
-            && (statement.contains("try_wait") || statement.contains("shared::cta"))
-    })
-}
-
-fn contains_mbarrier_ptx80_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        statement.contains("mbarrier.")
-            && [
-                "expect_tx",
-                "complete_tx",
-                "shared::cluster",
-                ".acquire.",
-                ".release.",
-            ]
-            .iter()
-            .any(|feature| statement.contains(feature))
-    })
-}
-
-/// Checks for Blackwell tcgen05 instructions (sm_100a+).
-///
-/// These instructions require a datacenter-Blackwell `a`/`f` target; consumer
-/// sm_120 does not provide Tensor Memory:
-/// - tcgen05: Tensor Core Gen 5 (TMEM allocation, MMA, sync primitives)
-///
-/// Key differences from Hopper:
-/// - tcgen05 MMA is single-thread (vs WGMMA's 128 threads)
-/// - Uses Tensor Memory (TMEM) instead of registers
-/// - Different synchronization model (mbarrier-based)
-fn contains_blackwell_features(contents: &str) -> bool {
-    // Keep the instruction-family match broad enough for inline PTX and LLVM
-    // intrinsic names, but do not treat debug filenames such as `tcgen05.rs`
-    // as an instruction.
-    [
-        "tcgen05.alloc",
-        "tcgen05.dealloc",
-        "tcgen05.relinquish_alloc_permit",
-        "tcgen05.fence",
-        "tcgen05.commit",
-        "tcgen05.mma",
-        "tcgen05.cp",
-        "tcgen05.shift",
-        "tcgen05.ld",
-        "tcgen05.st",
-        "tcgen05.wait",
-    ]
-    .iter()
-    .any(|instruction| contents.contains(instruction))
-}
-
-/// Checks for base TMA multicast in LLVM IR or inline PTX.
-///
-/// TMA multicast (`cp.async.bulk.tensor...multicast::cluster`) is an optional
-/// qualifier that broadcasts a tile to all CTAs in a cluster. It is legal on
-/// sm_90+, although NVIDIA advises an `a`/`f` target
-/// for performance. In the LLVM intrinsic this is controlled by the trailing
-/// `use_cta_mask` i1 argument being set to true.
-fn contains_tma_multicast(contents: &str) -> bool {
-    contents.lines().any(|line| {
-        line.contains("g2s.tile") && (line.contains(", i1 1, i1") || line.contains(", i1 true, i1"))
-    }) || contents.split(';').any(|statement| {
-        statement.contains("cp.async.bulk.tensor") && statement.contains(".multicast::cluster")
-    })
-}
-
-/// Checks Blackwell-only TMA forms with an explicit CTA-group qualifier.
-fn contains_tma_cta_group_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        statement.contains("cp.async.bulk.tensor")
-            && (statement.contains(".cta_group::1") || statement.contains(".cta_group::2"))
-    }) || contents.lines().any(|line| {
-        line.contains("g2s.tile") && (line.contains(", i32 1)") || line.contains(", i32 2)"))
-    })
-}
-
-/// Checks TMA copies whose destination is CTA-local shared memory.
-///
-/// `.shared::cta` already existed as a source state space for shared-to-global
-/// copies, so the following `.global` source qualifier is part of the match.
-/// The destination form was introduced in PTX 8.6 but is valid on sm_90.
-fn contains_tma_shared_cta_destination(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        statement.contains("cp.async.bulk.") && statement.contains(".shared::cta.global")
-    })
-}
-
-/// Checks PTX 8.6 TMA modifiers with a generic sm_100 architecture floor.
-fn contains_tma_sm100_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        if !statement.contains("cp.async.bulk.") {
-            return false;
-        }
-        statement.contains(".cp_mask")
-            || (contains_tma_gather_or_im2col(statement)
-                && statement.contains(".shared::cta.global"))
-    })
-}
-
-/// Checks PTX 8.6 TMA modes restricted to datacenter Blackwell targets.
-fn contains_tma_blackwell_accelerated_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        if !statement.contains("cp.async.bulk.") {
-            return false;
-        }
-        statement.contains(".tile::scatter4")
-            || statement.contains(".im2col::w::128")
-            || (contains_tma_gather_or_im2col(statement)
-                && !statement.contains(".shared::cta.global"))
-    })
-}
-
-fn contains_tma_gather_or_im2col(statement: &str) -> bool {
-    statement.contains(".tile::gather4")
-        || (statement.contains(".im2col::w") && !statement.contains(".im2col::w::128"))
-}
-
-fn contains_tma_ptx86_features(contents: &str) -> bool {
-    contains_tma_sm100_features(contents)
-        || contains_tma_blackwell_accelerated_features(contents)
-        || contents.contains(".sync_restrict")
-        || contents
-            .split(';')
-            .any(|statement| statement.contains("mbarrier.") && statement.contains(".relaxed"))
-}
-
-fn contains_clc_features(contents: &str) -> bool {
-    contents.contains("clusterlaunchcontrol.")
-}
-
-fn contains_clc_multicast_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        statement.contains("clusterlaunchcontrol.")
-            && statement.contains(".multicast::cluster::all")
-    })
-}
-
-fn contains_cluster_ptx80_features(contents: &str) -> bool {
-    contents.split(';').any(|statement| {
-        statement.contains("barrier.cluster.")
-            && [".release", ".relaxed", ".acquire"]
-                .iter()
-                .any(|qualifier| statement.contains(qualifier))
-    })
-}
-
-/// Detect a direct LLVM intrinsic call, including its opaque-pointer overload.
-///
-/// Opaque-pointer LLVM IR spells the dynamic-stack intrinsics as
-/// `llvm.stacksave.p0` and `llvm.stackrestore.p0`, while typed-pointer IR can
-/// use the unsuffixed names. Keep the boundary strict so similarly named user
-/// functions do not raise the module's target requirements. Only call
-/// instructions count: declarations, comments, and quoted metadata or string
-/// contents do not reach the backend.
-fn contains_llvm_pointer_intrinsic_call(contents: &str, intrinsic: &str) -> bool {
-    contents.lines().any(|line| {
-        if !line.contains(intrinsic) {
-            return false;
-        }
-        let code = llvm_code_without_comments_or_strings(line);
-        code.match_indices(intrinsic).any(|(start, _)| {
-            if !contains_llvm_keyword(&code[..start], "call") {
-                return false;
-            }
-
-            let suffix = &code[start + intrinsic.len()..];
-            if suffix.starts_with('(') {
-                return true;
-            }
-            let Some(overload) = suffix.strip_prefix(".p") else {
-                return false;
-            };
-            let digits = overload.bytes().take_while(u8::is_ascii_digit).count();
-            digits != 0 && overload[digits..].starts_with('(')
-        })
-    })
-}
-
-fn llvm_code_without_comments_or_strings(line: &str) -> String {
-    let mut code = String::with_capacity(line.len());
-    let mut chars = line.chars();
-    let mut in_string = false;
-
-    while let Some(character) = chars.next() {
-        if in_string {
-            match character {
-                '\\' => {
-                    code.push(' ');
-                    if chars.next().is_some() {
-                        code.push(' ');
-                    }
-                }
-                '"' => {
-                    code.push(' ');
-                    in_string = false;
-                }
-                _ => code.push(' '),
-            }
-        } else {
-            match character {
-                ';' => break,
-                '"' => {
-                    code.push(' ');
-                    in_string = true;
-                }
-                _ => code.push(character),
-            }
-        }
-    }
-
-    code
-}
-
-fn contains_llvm_keyword(contents: &str, keyword: &str) -> bool {
-    contents.match_indices(keyword).any(|(start, _)| {
-        let before = contents[..start].bytes().next_back();
-        let after = contents[start + keyword.len()..].bytes().next();
-        before.is_none_or(|byte| !is_llvm_identifier_byte(byte))
-            && after.is_none_or(|byte| !is_llvm_identifier_byte(byte))
-    })
-}
-
-fn is_llvm_identifier_byte(byte: u8) -> bool {
-    byte.is_ascii_alphanumeric() || matches!(byte, b'-' | b'$' | b'.' | b'_')
-}
-
-fn contains_dynamic_stack_features(contents: &str) -> bool {
-    contains_llvm_pointer_intrinsic_call(contents, "@llvm.stacksave")
-        || contains_llvm_pointer_intrinsic_call(contents, "@llvm.stackrestore")
-}
-
-/// GPU feature requirements detected in one LLVM module.
-///
-/// This is a set rather than a single "strongest" feature: architecture
-/// families are not totally ordered. For example, WGMMA requires Hopper
-/// `sm_90a`, while PTX 8.6 matrix forms require Blackwell. Keeping every bit
-/// lets target validation enforce the intersection instead of silently
-/// choosing whichever instruction happened to have higher detector priority.
-#[derive(Clone, Copy, PartialEq, Eq)]
-pub struct DetectedFeatures(u32);
-
-#[allow(non_upper_case_globals)]
-impl DetectedFeatures {
-    /// tcgen05/TMEM (Blackwell datacenter, sm_100a).
-    pub(crate) const Blackwell: Self = Self(1 << 0);
-    /// Base TMA multicast (sm_90+, with architecture/family targets preferred).
-    pub(crate) const TmaMulticast: Self = Self(1 << 1);
-    /// Explicit CTA-group TMA forms (Blackwell datacenter family).
-    pub(crate) const TmaCtaGroup: Self = Self(1 << 2);
-    /// PTX 8.6 ldmatrix/stmatrix shapes supported on Blackwell family targets.
-    pub(crate) const MatrixBlackwell: Self = Self(1 << 3);
-    /// WGMMA (Hopper only, sm_90a - NOT forward-compatible).
-    pub(crate) const Wgmma: Self = Self(1 << 4);
-    /// TMA/mbarrier (Hopper+ compatible).
-    pub(crate) const Tma: Self = Self(1 << 5);
-    /// Thread Block Clusters (sm_90+, forward-compatible).
-    pub(crate) const Cluster: Self = Self(1 << 6);
-    /// Forward-compatible instructions with an sm_90 floor.
-    pub(crate) const Sm90: Self = Self(1 << 7);
-    /// Forward-compatible instructions with an sm_80 floor.
-    pub(crate) const Sm80: Self = Self(1 << 8);
-    /// Forward-compatible instructions with an sm_75 floor.
-    pub(crate) const Sm75: Self = Self(1 << 17);
-    /// Warp matrix register transpose introduced in PTX 7.8 on sm_75.
-    pub(crate) const Movmatrix: Self = Self(1 << 9);
-    /// Warp matrix shared-memory load introduced in PTX 6.5 on sm_75.
-    pub(crate) const Ldmatrix: Self = Self(1 << 10);
-    /// No special features (Volta+, with an sm_80 cross-compile default).
-    pub(crate) const Basic: Self = Self(1 << 11);
-    /// Generic Blackwell-or-newer operations such as base CLC and TMA cp_mask.
-    pub(crate) const Sm100: Self = Self(1 << 12);
-    /// Architecture/family-specific Blackwell features also available on consumers.
-    pub(crate) const BlackwellFamily: Self = Self(1 << 13);
-    /// Architecture/family-specific datacenter Blackwell TMA modes.
-    pub(crate) const BlackwellAccelerated: Self = Self(1 << 14);
-    /// Floating-point `redux.sync` (the sm_100/sm_103 architecture family).
-    pub(crate) const ReduxF32: Self = Self(1 << 15);
-    /// FP8 / f16-accumulator multimem forms on supported Blackwell families.
-    pub(crate) const MultimemFp8: Self = Self(1 << 16);
-    /// Dynamic stack save/restore, supported by LLVM NVPTX on sm_52+.
-    pub(crate) const DynamicStack: Self = Self(1 << 18);
-
-    const ALL: [Self; 19] = [
-        Self::Blackwell,
-        Self::TmaCtaGroup,
-        Self::BlackwellAccelerated,
-        Self::BlackwellFamily,
-        Self::ReduxF32,
-        Self::MultimemFp8,
-        Self::TmaMulticast,
-        Self::MatrixBlackwell,
-        Self::Wgmma,
-        Self::Tma,
-        Self::Cluster,
-        Self::Sm90,
-        Self::Sm80,
-        Self::Sm75,
-        Self::Movmatrix,
-        Self::Ldmatrix,
-        Self::Sm100,
-        Self::DynamicStack,
-        Self::Basic,
-    ];
-
-    const fn empty() -> Self {
-        Self(0)
-    }
-
-    const fn contains(self, feature: Self) -> bool {
-        self.0 & feature.0 != 0
-    }
-
-    fn insert(&mut self, feature: Self) {
-        self.0 |= feature.0;
-    }
-
-    fn iter(self) -> impl Iterator<Item = Self> {
-        Self::ALL
-            .into_iter()
-            .filter(move |feature| self.contains(*feature))
-    }
-
-    fn name(self) -> &'static str {
-        match self {
-            Self::Blackwell => "Blackwell",
-            Self::TmaMulticast => "TmaMulticast",
-            Self::TmaCtaGroup => "TmaCtaGroup",
-            Self::MatrixBlackwell => "MatrixBlackwell",
-            Self::Wgmma => "Wgmma",
-            Self::Tma => "Tma",
-            Self::Cluster => "Cluster",
-            Self::Sm90 => "Sm90",
-            Self::Sm80 => "Sm80",
-            Self::Sm75 => "Sm75",
-            Self::Movmatrix => "Movmatrix",
-            Self::Ldmatrix => "Ldmatrix",
-            Self::Sm100 => "Sm100",
-            Self::BlackwellFamily => "BlackwellFamily",
-            Self::BlackwellAccelerated => "BlackwellAccelerated",
-            Self::ReduxF32 => "ReduxF32",
-            Self::MultimemFp8 => "MultimemFp8",
-            Self::DynamicStack => "DynamicStack",
-            Self::Basic => "Basic",
-            _ => "Unknown",
-        }
-    }
-}
-
-impl std::fmt::Debug for DetectedFeatures {
-    fn fmt(&self, formatter: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
-        let mut first = true;
-        for feature in self.iter() {
-            if !first {
-                formatter.write_str(" + ")?;
-            }
-            formatter.write_str(feature.name())?;
-            first = false;
-        }
-        Ok(())
-    }
-}
-
-impl std::ops::BitOr for DetectedFeatures {
-    type Output = Self;
-
-    fn bitor(self, rhs: Self) -> Self::Output {
-        Self(self.0 | rhs.0)
-    }
-}
-
-/// PTX ISA requirements are independent of the GPU architecture floor.
-///
-/// For example, a module may need sm_80 because it uses `cp.async` and still
-/// need PTX 7.8 because it also uses `movmatrix`.
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
-pub enum PtxIsaRequirement {
-    Default,
-    Ptx62,
-    Ptx65,
-    Ptx70,
-    Ptx71,
-    Ptx73,
-    Ptx78,
-    Ptx80,
-    Ptx86,
-    Ptx87,
-    Ptx88,
-    Ptx90,
-}
-
-impl PtxIsaRequirement {
-    fn from_spelling(spelling: u16) -> Option<Self> {
-        Some(match spelling {
-            62 => Self::Ptx62,
-            65 => Self::Ptx65,
-            70 => Self::Ptx70,
-            71 => Self::Ptx71,
-            73 => Self::Ptx73,
-            78 => Self::Ptx78,
-            80 => Self::Ptx80,
-            86 => Self::Ptx86,
-            87 => Self::Ptx87,
-            88 => Self::Ptx88,
-            90 => Self::Ptx90,
-            _ => return None,
-        })
-    }
-
-    fn spelling(self) -> Option<u16> {
-        match self {
-            Self::Default => None,
-            requirement => PTX_ISA_SPELLINGS
-                .iter()
-                .copied()
-                .find(|spelling| Self::from_spelling(*spelling) == Some(requirement)),
-        }
-    }
-
-    fn feature(self) -> Option<&'static str> {
-        self.spelling().and_then(cuda_target_spec::spelling_feature)
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct ModuleRequirements {
-    pub features: DetectedFeatures,
-    pub ptx_isa: PtxIsaRequirement,
-}
-
-/// Convert catalog PTX floors to the discrete `llc` feature spellings this
-/// compiler supports. A floor between two spellings rounds upward; a future
-/// floor beyond the newest supported spelling is rejected instead of ignored.
-pub(crate) fn generated_ptx_isa_requirement(
-    generated: &GeneratedModuleRequirements,
-) -> Result<PtxIsaRequirement, String> {
-    let mut requirement = PtxIsaRequirement::Default;
-    for resolved in generated.resolved_targets() {
-        let target_requirement = resolved_requirement(generated, resolved)?;
-        let minimum_ptx =
-            resolved_requirement_minimum_ptx(target_requirement).ok_or_else(|| {
-                format!(
-                    "generated intrinsic `{}` (`{}`) has an empty resolved target contract",
-                    resolved.target.id, resolved.target.marker
-                )
-            })?;
-        requirement = requirement.max(ptx_isa_requirement_for_floor(
-            minimum_ptx,
-            resolved.target.id,
-            resolved.target.marker,
-        )?);
-    }
-    Ok(requirement)
-}
-
-/// Resolve the PTX floor for the selected hardware alternative.
-pub(crate) fn generated_ptx_isa_requirement_for_target(
-    generated: &GeneratedModuleRequirements,
-    arch: &str,
-) -> Result<PtxIsaRequirement, String> {
-    let mut requirement = PtxIsaRequirement::Default;
-    for resolved in generated.resolved_targets() {
-        let target_requirement = resolved_requirement(generated, resolved)?;
-        let floor = resolved_requirement_ptx_floor(arch, target_requirement).ok_or_else(|| {
-            format!(
-                "CUDA target {arch} cannot lower generated intrinsic `{}` (`{}`); requires {}",
-                resolved.target.id,
-                resolved.target.marker,
-                describe_resolved_requirement(target_requirement)
-            )
-        })?;
-        requirement = requirement.max(ptx_isa_requirement_for_floor(
-            floor,
-            resolved.target.id,
-            resolved.target.marker,
-        )?);
-    }
-    validate_sm101_ptx_pair(arch, requirement)?;
-    Ok(requirement)
-}
-
-fn resolved_requirement(
-    generated: &GeneratedModuleRequirements,
-    resolved: &GeneratedResolvedTarget,
-) -> Result<GeneratedResolvedRequirement, String> {
-    generated.resolved_requirement(resolved).ok_or_else(|| {
-        let selector = resolved
-            .selector
-            .map(|selector| format!("{}={}", selector.name, selector.value))
-            .unwrap_or_else(|| "<none>".to_string());
-        format!(
-            "generated intrinsic `{}` (`{}`) has no unique target contract for {selector}",
-            resolved.target.id, resolved.target.marker
-        )
-    })
-}
-
-fn resolved_requirement_minimum_ptx(requirement: GeneratedResolvedRequirement) -> Option<u16> {
-    match requirement {
-        GeneratedResolvedRequirement::Target(requirement) => {
-            Some(requirement.minimum_ptx.encoded())
-        }
-        GeneratedResolvedRequirement::Contract(contract) => contract
-            .alternatives
-            .iter()
-            .map(|alternative| alternative.minimum_ptx.encoded())
-            .min(),
-    }
-}
-
-fn ptx_isa_requirement_for_floor(
-    encoded: u16,
-    id: &str,
-    marker: &str,
-) -> Result<PtxIsaRequirement, String> {
-    if encoded <= 60 {
-        return Ok(PtxIsaRequirement::Default);
-    }
-    spelling_at_least(encoded)
-        .and_then(PtxIsaRequirement::from_spelling)
-        .ok_or_else(|| format!(
-            "generated intrinsic `{id}` (`{marker}`) requires PTX {}.{}, newer than cuda-oxide can request",
-            encoded / 10,
-            encoded % 10
-        ))
-}
-
-pub(crate) fn merge_generated_module_requirements(
-    mut text: ModuleRequirements,
-    generated: &GeneratedModuleRequirements,
-) -> Result<ModuleRequirements, String> {
-    text.ptx_isa = text.ptx_isa.max(generated_ptx_isa_requirement(generated)?);
-    Ok(text)
-}
-
-pub(crate) fn merge_generated_module_requirements_for_target(
-    mut text: ModuleRequirements,
-    generated: &GeneratedModuleRequirements,
-    arch: &str,
-) -> Result<ModuleRequirements, String> {
-    text.ptx_isa = text
-        .ptx_isa
-        .max(generated_ptx_isa_requirement_for_target(generated, arch)?);
-    validate_sm101_ptx_pair(arch, text.ptx_isa)?;
-    Ok(text)
-}
-
-/// Reject LLVM target names whose meaning changes at a newer PTX ISA.
-fn validate_sm101_ptx_pair(arch: &str, requirement: PtxIsaRequirement) -> Result<(), String> {
-    let Some((capability, suffix)) = arch_compute_capability_and_suffix(arch) else {
-        return Ok(());
-    };
-    if capability == 101
-        && matches!(suffix, Some('a' | 'f'))
-        && requirement >= PtxIsaRequirement::Ptx90
-    {
-        return Err(format!(
-            "CUDA target {arch} cannot be combined with PTX 9.0 or newer; LLVM renamed the sm_101 target to sm_110 at that PTX level"
-        ));
-    }
-    Ok(())
-}
-
-/// Detect every architecture requirement in exported LLVM text.
-///
-/// Both the ordinary PTX path and automatic libdevice mode use this exact
-/// detector. The latter renders an in-memory preview before choosing the NVVM
-/// pointer dialect.
-pub fn detect_features_in_llvm_text(contents: &str) -> DetectedFeatures {
-    let mut features = DetectedFeatures::empty();
-    for (present, feature) in [
-        (
-            contains_blackwell_features(contents),
-            DetectedFeatures::Blackwell,
-        ),
-        (
-            contains_tma_cta_group_features(contents),
-            DetectedFeatures::TmaCtaGroup,
-        ),
-        (
-            contains_tma_blackwell_accelerated_features(contents),
-            DetectedFeatures::BlackwellAccelerated,
-        ),
-        (
-            contains_clc_multicast_features(contents),
-            DetectedFeatures::BlackwellFamily,
-        ),
-        (
-            contains_redux_f32_features(contents),
-            DetectedFeatures::ReduxF32,
-        ),
-        (
-            contains_multimem_blackwell_features(contents),
-            DetectedFeatures::MultimemFp8,
-        ),
-        (
-            contains_tma_multicast(contents),
-            DetectedFeatures::TmaMulticast,
-        ),
-        (
-            contains_blackwell_matrix_features(contents),
-            DetectedFeatures::MatrixBlackwell,
-        ),
-        (contains_wgmma_features(contents), DetectedFeatures::Wgmma),
-        (contains_tma_features(contents), DetectedFeatures::Tma),
-        (
-            contains_cluster_features(contents),
-            DetectedFeatures::Cluster,
-        ),
-        (contains_sm90_features(contents), DetectedFeatures::Sm90),
-        (contains_sm80_features(contents), DetectedFeatures::Sm80),
-        (
-            contains_mma_m8n8k16_int8_features(contents)
-                || contains_mma_m8n8k32_int4_features(contents)
-                || contains_mma_m8n8k128_b1_xor_features(contents),
-            DetectedFeatures::Sm75,
-        ),
-        (
-            contains_movmatrix_features(contents),
-            DetectedFeatures::Movmatrix,
-        ),
-        (
-            contains_ldmatrix_features(contents),
-            DetectedFeatures::Ldmatrix,
-        ),
-        (
-            contains_tma_sm100_features(contents)
-                || contains_clc_features(contents)
-                || contains_f32x2_features(contents),
-            DetectedFeatures::Sm100,
-        ),
-        (
-            contains_dynamic_stack_features(contents),
-            DetectedFeatures::DynamicStack,
-        ),
-    ] {
-        if present {
-            features.insert(feature);
-        }
-    }
-    if features == DetectedFeatures::empty() {
-        features.insert(DetectedFeatures::Basic);
-    }
-    features
-}
-
-fn detect_module_requirements_in_llvm_text(contents: &str) -> ModuleRequirements {
-    let mut ptx_isa = PtxIsaRequirement::Default;
-    if contains_packed_f16_atomic_features(contents) {
-        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx62);
-    }
-    if contains_ldmatrix_features(contents)
-        || contains_mma_m8n8k16_int8_features(contents)
-        || contains_mma_m8n8k32_int4_features(contents)
-    {
-        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx65);
-    }
-    if contains_mbarrier_features(contents)
-        || contents.contains("redux.sync")
-        || contains_mma_m16n8k16_f32_bf16_features(contents)
-        || contains_mma_m16n8k16_f32_f16_features(contents)
-        || contains_mma_m16n8k8_f32_tf32_features(contents)
-        || contains_dense_int8_mma_features(contents)
-        || contains_dense_int4_mma_features(contents)
-        || contains_b1_xor_mma_features(contents)
-        || contains_mma_m8n8k4_f64_features(contents)
-    {
-        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx70);
-    }
-    if contains_mbarrier_ptx71_features(contents) {
-        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx71);
-    }
-    if contains_b1_and_mma_features(contents) {
-        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx71);
-    }
-    if contains_dynamic_stack_features(contents) {
-        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx73);
-    }
-    if contains_movmatrix_features(contents)
-        || contains_stmatrix_features(contents)
-        || contains_ldmatrix_cta_state_space(contents)
-        || contains_cluster_features(contents)
-        || contains_mbarrier_ptx78_features(contents)
-        || contains_packed_bf16_atomic_features(contents)
-    {
-        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx78);
-    }
-    if contains_cp_async_bulk_features(contents)
-        || contains_wgmma_features(contents)
-        || contains_cluster_ptx80_features(contents)
-        || contains_elect_features(contents)
-        || contains_mbarrier_ptx80_features(contents)
-        || contents.contains("fence.mbarrier_init")
-        || contents.contains("fence.proxy.async")
-    {
-        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx80);
-    }
-    if contains_blackwell_matrix_features(contents)
-        || contains_tma_cta_group_features(contents)
-        || contains_tma_shared_cta_destination(contents)
-        || contains_tma_ptx86_features(contents)
-        || contains_clc_features(contents)
-        || contains_blackwell_features(contents)
-        || contains_fence_acquire_release_features(contents)
-        || contains_multimem_features(contents)
-        || contains_redux_f32_features(contents)
-        || contains_f32x2_features(contents)
-    {
-        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx86);
-    }
-
-    ModuleRequirements {
-        features: detect_features_in_llvm_text(contents),
-        ptx_isa,
-    }
-}
-
-pub fn detect_module_requirements_in_llvm_file(
-    ll_path: &Path,
-) -> Result<ModuleRequirements, PipelineError> {
-    let contents = std::fs::read_to_string(ll_path).map_err(|error| {
-        PipelineError::PtxGeneration(format!(
-            "failed to inspect generated LLVM IR {}: {error}",
-            ll_path.display()
-        ))
-    })?;
-    Ok(detect_module_requirements_in_llvm_text(&contents))
-}
-
-/// Select a concrete architecture that satisfies every detected feature.
-///
-/// The first candidate preserves the established default for a module's most
-/// restrictive-looking feature. The remaining candidates handle intersections
-/// such as WGMMA + TMA multicast, whose only common target is `sm_90a`.
-pub fn select_target(features: DetectedFeatures) -> Result<&'static str, String> {
-    let preferred = if features.contains(DetectedFeatures::Blackwell)
-        || features.contains(DetectedFeatures::TmaCtaGroup)
-        || features.contains(DetectedFeatures::BlackwellAccelerated)
-        || features.contains(DetectedFeatures::BlackwellFamily)
-        || features.contains(DetectedFeatures::ReduxF32)
-        || features.contains(DetectedFeatures::MultimemFp8)
-        || features.contains(DetectedFeatures::TmaMulticast)
-        || features.contains(DetectedFeatures::MatrixBlackwell)
-    {
-        "sm_100a"
-    } else if features.contains(DetectedFeatures::Wgmma) {
-        "sm_90a"
-    } else if features.contains(DetectedFeatures::Sm100) {
-        "sm_100"
-    } else if features.contains(DetectedFeatures::Tma) {
-        // Plain TMA is compatible with Hopper, but sm_100 is the existing
-        // cross-compilation default because it produces forward-compatible
-        // PTX for generic Blackwell devices.
-        "sm_100"
-    } else if features.contains(DetectedFeatures::Cluster)
-        || features.contains(DetectedFeatures::Sm90)
-    {
-        "sm_90"
-    } else if features.contains(DetectedFeatures::Sm80) {
-        "sm_80"
-    } else if features.contains(DetectedFeatures::Sm75)
-        || features.contains(DetectedFeatures::Movmatrix)
-        || features.contains(DetectedFeatures::Ldmatrix)
-    {
-        "sm_75"
-    } else {
-        "sm_80"
-    };
-
-    for candidate in [
-        preferred, "sm_100a", "sm_90a", "sm_100", "sm_90", "sm_80", "sm_75",
-    ] {
-        if arch_satisfies(candidate, features) {
-            return Ok(candidate);
-        }
-    }
-
-    Err(format!(
-        "detected CUDA features {features:?} do not share a compatible GPU architecture"
-    ))
-}
-
-/// Select one concrete target satisfying both text-detected features and every
-/// generated intrinsic used by the module.
-///
-/// Generated hardware requirements are a module-wide AND. Each intrinsic's
-/// `AnyOf` list remains an OR, so the search finds one architecture in the
-/// intersection rather than selecting a separate target per call.
-pub(crate) fn select_target_with_generated(
-    features: DetectedFeatures,
-    generated: &GeneratedModuleRequirements,
-) -> Result<String, String> {
-    let preferred = select_target(features)?;
-    if generated.is_empty() {
-        return Ok(preferred.to_string());
-    }
-
-    let mut candidates = vec![preferred.to_string()];
-    let mut push_candidate = |candidate: String| {
-        if !candidates.contains(&candidate) {
-            candidates.push(candidate);
-        }
-    };
-
-    // Try each catalog spelling before the exhaustive known-target list. This
-    // preserves catalog alternative order while still finding intersections
-    // such as `minimum sm_80` AND `sm_90a exactly`.
-    for resolved in generated.resolved_targets() {
-        let requirement = resolved_requirement(generated, resolved)?;
-        for_each_resolved_hardware_alternative(requirement, |alternative| {
-            push_candidate(generated_hardware_candidate(alternative));
-        });
-    }
-
-    // This is the reviewed set accepted by `is_known_cuda_target`. Family and
-    // architecture spellings are included because a generated requirement may
-    // need to intersect with an existing text-detected feature.
-    for candidate in KNOWN_CUDA_TARGET_CANDIDATES {
-        push_candidate(candidate.to_string());
-    }
-
-    if let Some(candidate) = candidates.into_iter().find(|candidate| {
-        arch_satisfies(candidate, features) && generated_target_satisfied(candidate, generated)
-    }) {
-        return Ok(candidate);
-    }
-
-    let generated_ids = generated
-        .resolved_targets()
-        .iter()
-        .map(|resolved| {
-            let selector = resolved
-                .selector
-                .map(|selector| format!(" for {}={}", selector.name, selector.value))
-                .unwrap_or_default();
-            format!(
-                "{} ({}){selector}",
-                resolved.target.id, resolved.target.marker
-            )
-        })
-        .collect::<Vec<_>>()
-        .join(", ");
-    Err(format!(
-        "detected CUDA features {features:?} and generated intrinsics [{generated_ids}] do not share a compatible GPU architecture"
-    ))
-}
-
-const KNOWN_CUDA_TARGET_CANDIDATES: &[&str] = &[
-    "sm_70", "sm_72", "sm_75", "sm_80", "sm_86", "sm_87", "sm_88", "sm_89", "sm_90", "sm_100",
-    "sm_101", "sm_103", "sm_110", "sm_120", "sm_121", "sm_90a", "sm_100a", "sm_101a", "sm_103a",
-    "sm_110a", "sm_120a", "sm_121a", "sm_100f", "sm_101f", "sm_103f", "sm_110f", "sm_120f",
-    "sm_121f",
-];
-
-pub(crate) fn generated_target_satisfied(
-    arch: &str,
-    generated: &GeneratedModuleRequirements,
-) -> bool {
-    generated.resolved_targets().iter().all(|resolved| {
-        let Ok(requirement) = resolved_requirement(generated, resolved) else {
-            return false;
-        };
-        resolved_hardware_satisfied(arch, requirement)
-            && resolved_requirement_ptx_floor(arch, requirement).is_some_and(|floor| {
-                ptx_isa_requirement_for_floor(floor, resolved.target.id, resolved.target.marker)
-                    .is_ok()
-            })
-    })
-}
-
-fn resolved_hardware_satisfied(arch: &str, requirement: GeneratedResolvedRequirement) -> bool {
-    match requirement {
-        GeneratedResolvedRequirement::Target(requirement) => {
-            generated_hardware_satisfied(arch, requirement.hardware)
-        }
-        GeneratedResolvedRequirement::Contract(contract) => {
-            generated_contract_satisfied(arch, contract)
-        }
-    }
-}
-
-fn generated_hardware_satisfied(arch: &str, hardware: GeneratedHardwareTarget) -> bool {
-    let Some((capability, suffix)) = arch_compute_capability_and_suffix(arch) else {
-        return false;
-    };
-    if !is_known_cuda_target(capability, suffix) {
-        return false;
-    }
-
-    match hardware {
-        GeneratedHardwareTarget::All => true,
-        GeneratedHardwareTarget::AnyOf(alternatives) => alternatives.iter().any(|alternative| {
-            generated_hardware_alternative_satisfied(capability, suffix, *alternative)
-        }),
-        GeneratedHardwareTarget::TargetMatrix { contracts } => contracts.iter().any(|contract| {
-            contract.alternatives.iter().any(|alternative| {
-                generated_hardware_alternative_satisfied(capability, suffix, alternative.hardware)
-            })
-        }),
-    }
-}
-
-fn generated_contract_satisfied(arch: &str, contract: &GeneratedTargetContract) -> bool {
-    let Some((capability, suffix)) = arch_compute_capability_and_suffix(arch) else {
-        return false;
-    };
-    is_known_cuda_target(capability, suffix)
-        && contract.alternatives.iter().any(|alternative| {
-            generated_hardware_alternative_satisfied(capability, suffix, alternative.hardware)
-        })
-}
-
-fn for_each_resolved_hardware_alternative(
-    requirement: GeneratedResolvedRequirement,
-    mut visit: impl FnMut(GeneratedHardwareAlternative),
-) {
-    match requirement {
-        GeneratedResolvedRequirement::Target(requirement) => match requirement.hardware {
-            GeneratedHardwareTarget::All => {}
-            GeneratedHardwareTarget::AnyOf(alternatives) => {
-                for alternative in alternatives {
-                    visit(*alternative);
-                }
-            }
-            GeneratedHardwareTarget::TargetMatrix { contracts } => {
-                for contract in contracts {
-                    for alternative in contract.alternatives {
-                        visit(alternative.hardware);
-                    }
-                }
-            }
-        },
-        GeneratedResolvedRequirement::Contract(contract) => {
-            for alternative in contract.alternatives {
-                visit(alternative.hardware);
-            }
-        }
-    }
-}
-
-fn generated_hardware_candidate(alternative: GeneratedHardwareAlternative) -> String {
-    match alternative {
-        GeneratedHardwareAlternative::MinimumSm(capability) => format!("sm_{capability}"),
-        GeneratedHardwareAlternative::ExactArchitecture(capability) => {
-            format!("sm_{capability}a")
-        }
-        GeneratedHardwareAlternative::FamilyTarget(capability) => format!("sm_{capability}f"),
-    }
-}
-
-fn generated_hardware_requirement_label(alternative: GeneratedHardwareAlternative) -> String {
-    match alternative {
-        GeneratedHardwareAlternative::MinimumSm(capability) => {
-            format!("sm_{capability} or newer")
-        }
-        GeneratedHardwareAlternative::ExactArchitecture(capability) => {
-            format!("sm_{capability}a exactly")
-        }
-        GeneratedHardwareAlternative::FamilyTarget(capability) => {
-            format!("sm_{capability}f exactly")
-        }
-    }
-}
-
-fn generated_hardware_alternative_satisfied(
-    capability: u32,
-    suffix: Option<char>,
-    alternative: GeneratedHardwareAlternative,
-) -> bool {
-    match alternative {
-        GeneratedHardwareAlternative::MinimumSm(minimum) => capability >= u32::from(minimum),
-        GeneratedHardwareAlternative::ExactArchitecture(exact) => {
-            capability == u32::from(exact) && suffix == Some('a')
-        }
-        // Family targets match only the named `sm_Nf` spelling.
-        GeneratedHardwareAlternative::FamilyTarget(family) => {
-            capability == u32::from(family) && suffix == Some('f')
-        }
-    }
-}
-
-fn generated_requirement_ptx_floor(
-    arch: &str,
-    requirement: GeneratedTargetRequirement,
-) -> Option<u16> {
-    let (capability, suffix) = arch_compute_capability_and_suffix(arch)?;
-    if !is_known_cuda_target(capability, suffix) {
-        return None;
-    }
-    match requirement.hardware {
-        GeneratedHardwareTarget::All => Some(requirement.minimum_ptx.encoded()),
-        GeneratedHardwareTarget::AnyOf(alternatives) => alternatives
-            .iter()
-            .any(|alternative| {
-                generated_hardware_alternative_satisfied(capability, suffix, *alternative)
-            })
-            .then(|| requirement.minimum_ptx.encoded()),
-        GeneratedHardwareTarget::TargetMatrix { contracts } => contracts
-            .iter()
-            .flat_map(|contract| contract.alternatives.iter())
-            .filter(|alternative| {
-                generated_hardware_alternative_satisfied(capability, suffix, alternative.hardware)
-            })
-            .map(|alternative| alternative.minimum_ptx.encoded())
-            .min(),
-    }
-}
-
-fn resolved_requirement_ptx_floor(
-    arch: &str,
-    requirement: GeneratedResolvedRequirement,
-) -> Option<u16> {
-    match requirement {
-        GeneratedResolvedRequirement::Target(requirement) => {
-            generated_requirement_ptx_floor(arch, requirement)
-        }
-        GeneratedResolvedRequirement::Contract(contract) => {
-            let (capability, suffix) = arch_compute_capability_and_suffix(arch)?;
-            is_known_cuda_target(capability, suffix).then_some(())?;
-            contract
-                .alternatives
-                .iter()
-                .filter(|alternative| {
-                    generated_hardware_alternative_satisfied(
-                        capability,
-                        suffix,
-                        alternative.hardware,
-                    )
-                })
-                .map(|alternative| alternative.minimum_ptx.encoded())
-                .min()
-        }
-    }
-}
-
-pub(crate) fn validate_generated_target(
-    arch: &str,
-    generated: &GeneratedModuleRequirements,
-) -> Result<(), String> {
-    for resolved in generated.resolved_targets() {
-        let requirement = resolved_requirement(generated, resolved)?;
-        if !resolved_hardware_satisfied(arch, requirement) {
-            return Err(format!(
-                "CUDA target {arch} cannot lower generated intrinsic `{}` (`{}`); requires {}",
-                resolved.target.id,
-                resolved.target.marker,
-                describe_resolved_requirement(requirement)
-            ));
-        }
-        ptx_isa_requirement_for_floor(
-            resolved_requirement_ptx_floor(arch, requirement).unwrap(),
-            resolved.target.id,
-            resolved.target.marker,
-        )?;
-    }
-    Ok(())
-}
-
-fn describe_generated_hardware(hardware: GeneratedHardwareTarget) -> String {
-    match hardware {
-        GeneratedHardwareTarget::All => "any supported CUDA target".to_string(),
-        GeneratedHardwareTarget::AnyOf(alternatives) => alternatives
-            .iter()
-            .map(|alternative| generated_hardware_requirement_label(*alternative))
-            .collect::<Vec<_>>()
-            .join(" or "),
-        GeneratedHardwareTarget::TargetMatrix { contracts } => contracts
-            .iter()
-            .map(describe_generated_contract)
-            .collect::<Vec<_>>()
-            .join(" or "),
-    }
-}
-
-fn describe_resolved_requirement(requirement: GeneratedResolvedRequirement) -> String {
-    match requirement {
-        GeneratedResolvedRequirement::Target(requirement) => {
-            describe_generated_hardware(requirement.hardware)
-        }
-        GeneratedResolvedRequirement::Contract(contract) => describe_generated_contract(contract),
-    }
-}
-
-fn describe_generated_contract(contract: &GeneratedTargetContract) -> String {
-    let alternatives = contract
-        .alternatives
-        .iter()
-        .map(|alternative| {
-            format!(
-                "{} at PTX {}.{}",
-                generated_hardware_requirement_label(alternative.hardware),
-                alternative.minimum_ptx.major(),
-                alternative.minimum_ptx.minor()
-            )
-        })
-        .collect::<Vec<_>>()
-        .join(" or ");
-    if contract.selectors.is_empty() {
-        alternatives
-    } else {
-        let selectors = contract
-            .selectors
-            .iter()
-            .map(|selector| format!("{}={}", selector.name, selector.value))
-            .collect::<Vec<_>>()
-            .join(", ");
-        format!("{alternatives} for {selectors}")
-    }
-}
-
-/// Does `arch` (e.g. `"sm_120a"`, `"sm_90"`) support the kernel's detected
-/// features?
-///
-/// tcgen05/TMEM and explicit `cta_group` TMA forms exist only in the sm_100
-/// datacenter-Blackwell family: consumer Blackwell (sm_120) and Hopper (sm_90)
-/// lack them, so an sm_120 GPU cannot run an sm_100 tcgen05 kernel even though
-/// 120 > 100. WGMMA is Hopper-only. The remaining features are forward
-/// compatible from their floor (TMA / cluster / sm_90 features need sm_90+,
-/// sm_80 features need sm_80+, sm_75 features need sm_75+, and basic needs
-/// sm_70+).
-///
-/// Used to decide whether the GPU in this machine (the `CUDA_OXIDE_DEVICE_ARCH`
-/// hint) can actually run the kernel, or whether we must build for the arch the
-/// IR requires instead.
-pub fn arch_satisfies(arch: &str, features: DetectedFeatures) -> bool {
-    let Some((capability, suffix)) = arch_compute_capability_and_suffix(arch) else {
-        return false;
-    };
-    if !is_known_cuda_target(capability, suffix) {
-        return false;
-    }
-    features
-        .iter()
-        .all(|feature| arch_satisfies_feature(capability, suffix, feature))
-}
-
-fn arch_satisfies_feature(
-    capability: u32,
-    suffix: Option<char>,
-    feature: DetectedFeatures,
-) -> bool {
-    let major = capability / 10;
-    match feature {
-        DetectedFeatures::Blackwell | DetectedFeatures::TmaCtaGroup => {
-            supports_tcgen_target(capability, suffix)
-        }
-        DetectedFeatures::BlackwellAccelerated => {
-            supports_blackwell_accelerated_target(capability, suffix)
-        }
-        DetectedFeatures::BlackwellFamily => supports_blackwell_family_target(capability, suffix),
-        DetectedFeatures::MatrixBlackwell => supports_blackwell_matrix_target(capability, suffix),
-        DetectedFeatures::ReduxF32 => supports_redux_f32_target(capability, suffix),
-        DetectedFeatures::MultimemFp8 => supports_multimem_fp8_target(capability, suffix),
-        // The PTX ISA requires only sm_90+. The suffixed targets are advised
-        // for performance, so target selection still prefers sm_100a.
-        DetectedFeatures::TmaMulticast => major >= 9,
-        DetectedFeatures::Wgmma => capability == 90 && suffix == Some('a'),
-        DetectedFeatures::Sm100 => is_known_blackwell_capability(capability),
-        DetectedFeatures::Tma | DetectedFeatures::Cluster | DetectedFeatures::Sm90 => major >= 9,
-        DetectedFeatures::Sm80 => major >= 8,
-        DetectedFeatures::Sm75 | DetectedFeatures::Movmatrix | DetectedFeatures::Ldmatrix => {
-            capability >= 75
-        }
-        DetectedFeatures::DynamicStack => capability >= 52,
-        // Basic kernels are supported on the project's Volta+ floor. The
-        // cross-compilation default remains sm_80, but a detected sm_70/sm_75
-        // GPU is a valid and more useful target for `cargo oxide run`.
-        DetectedFeatures::Basic => major >= 7,
-        // `iter` only yields the single-bit constants above.
-        _ => false,
-    }
-}
-
-/// tcgen05/TMEM exists only on the datacenter Blackwell architecture or
-/// family targets. Consumer sm_120 and generic targets without an `a`/`f`
-/// suffix do not provide Tensor Memory.
-fn supports_tcgen_target(capability: u32, suffix: Option<char>) -> bool {
-    match suffix {
-        // Architecture-specific targets are exact, not numerically forward
-        // compatible. `sm_101a` is the PTX 8.x spelling later renamed to
-        // `sm_110a`; accept both spellings plus the distinct sm_103 target.
-        Some('a') => matches!(capability, 100 | 101 | 103 | 110),
-        Some('f') => matches!(capability, 100 | 101 | 103 | 110),
-        _ => false,
-    }
-}
-
-fn supports_blackwell_accelerated_target(capability: u32, suffix: Option<char>) -> bool {
-    match suffix {
-        Some('a') => matches!(capability, 100 | 101 | 103 | 110),
-        Some('f') => matches!(capability, 100 | 101 | 103 | 110),
-        _ => false,
-    }
-}
-
-fn supports_blackwell_family_target(capability: u32, suffix: Option<char>) -> bool {
-    match suffix {
-        Some('a') => matches!(capability, 100 | 101 | 110 | 120),
-        Some('f') => matches!(capability, 100 | 101 | 103 | 110 | 120 | 121),
-        _ => false,
-    }
-}
-
-fn supports_blackwell_matrix_target(capability: u32, suffix: Option<char>) -> bool {
-    // LLVM's sm_101 aliases stop selecting these instructions at PTX 9.0.
-    match suffix {
-        Some('a' | 'f') => matches!(capability, 100 | 103 | 110 | 120 | 121),
-        _ => false,
-    }
-}
-
-/// Floating-point `redux.sync` is scoped to the sm_100/sm_103 family.
-fn supports_redux_f32_target(capability: u32, suffix: Option<char>) -> bool {
-    matches!(suffix, Some('a' | 'f')) && matches!(capability, 100 | 103)
-}
-
-/// FP8 / f16-accumulator multimem forms span several Blackwell architecture
-/// targets, but consumer family (`f`) targets do not support the sm_120 line.
-fn supports_multimem_fp8_target(capability: u32, suffix: Option<char>) -> bool {
-    match suffix {
-        Some('a') => matches!(capability, 100 | 101 | 103 | 110 | 120 | 121),
-        Some('f') => matches!(capability, 100 | 101 | 103 | 110),
-        _ => false,
-    }
-}
-
-fn is_known_blackwell_capability(capability: u32) -> bool {
-    matches!(capability, 100 | 101 | 103 | 110 | 120 | 121)
-}
-
-fn is_known_cuda_target(capability: u32, suffix: Option<char>) -> bool {
-    CudaArch::new(capability, suffix).is_ok_and(|arch| recorded_ptx_floor(&arch).is_ok())
-}
-
-pub fn validate_target_features(
-    target: &CudaArch,
-    features: DetectedFeatures,
-) -> Result<(), String> {
-    let compatible_default = select_target(features)?;
-    if arch_satisfies(&target.sm(), features) {
-        return Ok(());
-    }
-
-    Err(format!(
-        "CUDA target {} cannot lower detected feature {features:?}; \
-         cuda-oxide requires a target compatible with {} for this module",
-        target.sm(),
-        compatible_default
-    ))
-}
-
-#[cfg(test)]
-pub fn resolve_ptx_target(
-    explicit_override: Option<&str>,
-    explicit_override_source: &'static str,
-    device_hint: Option<&str>,
-    detected: DetectedFeatures,
-) -> Result<(String, &'static str), PipelineError> {
-    resolve_ptx_target_with_generated(
-        explicit_override,
-        explicit_override_source,
-        device_hint,
-        detected,
-        &GeneratedModuleRequirements::default(),
-    )
-}
-
-pub(crate) fn resolve_ptx_target_with_generated(
-    explicit_override: Option<&str>,
-    explicit_override_source: &'static str,
-    device_hint: Option<&str>,
-    detected: DetectedFeatures,
-    generated: &GeneratedModuleRequirements,
-) -> Result<(String, &'static str), PipelineError> {
-    if let Some(target) = explicit_override {
-        let parsed =
-            target
-                .parse::<CudaArch>()
-                .map_err(|error| PipelineError::TargetSelection {
-                    target: target.to_string(),
-                    // `error` already reads "invalid CUDA target `x`: ...";
-                    // only the provenance needs to be added here.
-                    reason: format!("{error} (target from {explicit_override_source})"),
-                })?;
-        validate_target_features(&parsed, detected).map_err(|reason| {
-            PipelineError::TargetSelection {
-                target: parsed.sm(),
-                reason: format!("{reason} (target from {explicit_override_source})"),
-            }
-        })?;
-        validate_generated_target(&parsed.sm(), generated).map_err(|reason| {
-            PipelineError::TargetSelection {
-                target: parsed.sm(),
-                reason: format!("{reason} (target from {explicit_override_source})"),
-            }
-        })?;
-        return Ok((parsed.sm(), explicit_override_source));
-    }
-
-    if let Some(device) = device_hint.filter(|target| {
-        arch_satisfies(target, detected) && generated_target_satisfied(target, generated)
-    }) {
-        return Ok((device.to_string(), "detected GPU"));
-    }
-
-    let target =
-        select_target_with_generated(detected, generated).map_err(PipelineError::PtxGeneration)?;
-    Ok((target, "feature requirement"))
-}
-
-/// Select the PTX ISA independently from the GPU architecture.
-///
-/// LLVM GPU CPUs select a default PTX ISA independently from the hardware
-/// feature floor. Raise that ISA only when the selected CPU's default is too
-/// old; never force a newer target back to an older PTX version.
-pub fn required_ptx_feature(
-    target: &str,
-    requirement: PtxIsaRequirement,
-) -> Result<Option<&'static str>, String> {
-    if !target.starts_with("sm_") {
-        return Err(format!("invalid CUDA target `{target}`: expected `sm_XX`"));
-    }
-    let arch = target
-        .parse::<CudaArch>()
-        .map_err(|error| error.to_string())?;
-    let minimum = recorded_ptx_floor(&arch).map_err(|error| error.to_string())?;
-    let Some(requested) = requirement.spelling() else {
-        return Ok(None);
-    };
-    if requested <= minimum {
-        return Ok(None);
-    }
-    Ok(requirement.feature())
-}
-
-/// Reject targets that the supported LLVM 21 backend silently mishandles.
-///
-/// A recorded floor of PTX 9.0 identifies the targets LLVM 21 cannot emit
-/// reliably: it accepts their `-mcpu` spellings but only prints a warning and
-/// emits PTX 6.0, which ptxas then rejects. LLVM 22 is the first backend in
-/// cuda-oxide's supported toolchain set that emits valid PTX for them. An
-/// unknown backend version is rejected because it cannot prove support, while
-/// unknown targets remain the responsibility of the normal target validators.
-pub fn validate_target_for_llvm_major(target: &str, llc_major: Option<u32>) -> Result<(), String> {
-    let requires_llvm_22 = target.starts_with("sm_")
-        && target
-            .parse::<CudaArch>()
-            .ok()
-            .and_then(|arch| recorded_ptx_floor(&arch).ok())
-            .is_some_and(|floor| floor >= 90);
-    if requires_llvm_22 && llc_major.is_none_or(|major| major < 22) {
-        let backend = llc_major.map_or_else(
-            || "an LLVM backend with an unknown version".to_string(),
-            |major| format!("LLVM {major}"),
-        );
-        return Err(format!(
-            "CUDA target {target} requires LLVM 22 or newer; {backend} does not reliably emit valid PTX for this PTX 9.0 target"
-        ));
-    }
-    Ok(())
-}
-
-pub(crate) fn validate_ptx_isa_for_llvm_major(
-    requirement: PtxIsaRequirement,
-    llc_major: Option<u32>,
-) -> Result<(), String> {
-    if requirement >= PtxIsaRequirement::Ptx90 && llc_major.is_none_or(|major| major < 22) {
-        let backend = llc_major.map_or_else(
-            || "an LLVM backend with an unknown version".to_string(),
-            |major| format!("LLVM {major}"),
-        );
-        return Err(format!(
-            "PTX 9.0 or newer requires LLVM 22 or newer; {backend} does not support the required PTX feature"
-        ));
-    }
-    Ok(())
-}
-
-/// Extract the compute-capability *major* version from an `sm_…` target string.
-///
-/// CUDA concatenates major+minor without a separator, so `"sm_120a"` is cc 12.0
-/// (major 12), `"sm_90"` is cc 9.0, `"sm_103a"` is cc 10.3. We read the digit
-/// run after `sm_` and divide by ten. Returns `None` when there are no digits.
-#[cfg(test)]
-fn arch_major(arch: &str) -> Option<u32> {
-    arch_compute_capability(arch).map(|capability| capability / 10)
-}
-
-/// Extract the numeric compute capability from an `sm_…` target.
-#[cfg(test)]
-fn arch_compute_capability(arch: &str) -> Option<u32> {
-    arch_compute_capability_and_suffix(arch).map(|(capability, _)| capability)
-}
-
-fn arch_compute_capability_and_suffix(arch: &str) -> Option<(u32, Option<char>)> {
-    if !arch.starts_with("sm_") {
-        return None;
-    }
-    let target = arch.parse::<CudaArch>().ok()?;
-    Some((target.capability(), target.suffix()))
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use crate::generated_intrinsic_targets::{
-        GeneratedBackendRequirement, GeneratedIntrinsicBackend, GeneratedIntrinsicTarget,
-        GeneratedIntrinsicVariant, GeneratedPtxVersion, GeneratedTargetAlternative,
-        GeneratedTargetRequirement, GeneratedTargetSelectorBinding,
-    };
-
-    static EXACT_SM120A: &[GeneratedHardwareAlternative] =
-        &[GeneratedHardwareAlternative::ExactArchitecture(120)];
-    static PTX87_EXACT_SM120A: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
-        marker: "test:ptx87",
-        id: "ptx87_exact_sm120a",
-        abi_id: "test",
-        dialect_op: "test.ptx87",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(87),
-            hardware: GeneratedHardwareTarget::AnyOf(EXACT_SM120A),
-        },
-        backend_requirements: &[],
-        selections: &[],
-        llvm: None,
-    };
-    static PTX88: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
-        marker: "test:ptx88",
-        id: "ptx88",
-        abi_id: "test",
-        dialect_op: "test.ptx88",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[],
-        llvm: None,
-    };
-    static PTX90: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
-        marker: "test:ptx90",
-        id: "ptx90",
-        abi_id: "test",
-        dialect_op: "test.ptx90",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[],
-        llvm: None,
-    };
-    static PTX91_FUTURE: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
-        marker: "test:ptx91",
-        id: "ptx91_future",
-        abi_id: "test",
-        dialect_op: "test.ptx91",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(91),
-            hardware: GeneratedHardwareTarget::All,
-        },
-        backend_requirements: &[],
-        selections: &[],
-        llvm: None,
-    };
-    static TCGEN_F16_SELECTORS: &[GeneratedTargetSelectorBinding] =
-        &[GeneratedTargetSelectorBinding {
-            name: "kind",
-            value: "f16",
-        }];
-    static TCGEN_F16_TARGETS: &[GeneratedTargetAlternative] = &[
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-        },
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-        },
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-            hardware: GeneratedHardwareAlternative::FamilyTarget(100),
-        },
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-            hardware: GeneratedHardwareAlternative::FamilyTarget(101),
-        },
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-            hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
-        },
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-            hardware: GeneratedHardwareAlternative::FamilyTarget(103),
-        },
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-        },
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-            hardware: GeneratedHardwareAlternative::FamilyTarget(110),
-        },
-    ];
-    static TCGEN_F16_CONTRACTS: &[GeneratedTargetContract] = &[GeneratedTargetContract {
-        selectors: TCGEN_F16_SELECTORS,
-        alternatives: TCGEN_F16_TARGETS,
-    }];
-    static TCGEN_F16: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
-        marker: "test:tcgen_f16",
-        id: "tcgen_f16",
-        abi_id: "test",
-        dialect_op: "test.tcgen_f16",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: TCGEN_F16_CONTRACTS,
-            },
-        },
-        backend_requirements: &[],
-        selections: &[],
-        llvm: None,
-    };
-    static TCGEN_I8_SELECTORS: &[GeneratedTargetSelectorBinding] =
-        &[GeneratedTargetSelectorBinding {
-            name: "kind",
-            value: "i8",
-        }];
-    static TCGEN_I8_TARGETS: &[GeneratedTargetAlternative] = &[
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-        },
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
-        },
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-        },
-    ];
-    static TCGEN_I8_LIBNVVM_TARGETS: &[GeneratedTargetAlternative] = &[
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
-        },
-        GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(90),
-            hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
-        },
-    ];
-    static TCGEN_I8_CONTRACTS: &[GeneratedTargetContract] = &[GeneratedTargetContract {
-        selectors: TCGEN_I8_SELECTORS,
-        alternatives: TCGEN_I8_TARGETS,
-    }];
-    static TCGEN_I8_LIBNVVM_CONTRACTS: &[GeneratedTargetContract] = &[GeneratedTargetContract {
-        selectors: TCGEN_I8_SELECTORS,
-        alternatives: TCGEN_I8_LIBNVVM_TARGETS,
-    }];
-    static TCGEN_I8_BACKENDS: &[GeneratedBackendRequirement] = &[GeneratedBackendRequirement {
-        backend: GeneratedIntrinsicBackend::LibNvvm,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: TCGEN_I8_LIBNVVM_CONTRACTS,
-            },
-        },
-    }];
-    static TCGEN_I8: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
-        marker: "test:tcgen_i8",
-        id: "tcgen_i8",
-        abi_id: "test",
-        dialect_op: "test.tcgen_i8",
-        variant: GeneratedIntrinsicVariant::Scalar,
-        requirement: GeneratedTargetRequirement {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(86),
-            hardware: GeneratedHardwareTarget::TargetMatrix {
-                contracts: TCGEN_I8_CONTRACTS,
-            },
-        },
-        backend_requirements: TCGEN_I8_BACKENDS,
-        selections: &[],
-        llvm: None,
-    };
-
-    #[test]
-    fn paired_target_floors_compose_with_target_cpu_minima() {
-        let generated = GeneratedModuleRequirements::from_targets(vec![&TCGEN_F16]);
-
-        assert_eq!(
-            generated_ptx_isa_requirement(&generated).unwrap(),
-            PtxIsaRequirement::Ptx86
-        );
-        for target in ["sm_100a", "sm_101a", "sm_103a", "sm_110a"] {
-            assert!(generated_target_satisfied(target, &generated), "{target}");
-        }
-        for (target, requirement) in [
-            ("sm_100a", PtxIsaRequirement::Ptx86),
-            ("sm_101a", PtxIsaRequirement::Ptx86),
-            ("sm_103a", PtxIsaRequirement::Ptx88),
-            ("sm_110a", PtxIsaRequirement::Ptx90),
-        ] {
-            assert_eq!(
-                generated_ptx_isa_requirement_for_target(&generated, target).unwrap(),
-                requirement
-            );
-            assert_eq!(required_ptx_feature(target, requirement).unwrap(), None);
-        }
-        assert_eq!(
-            generated_requirement_ptx_floor("sm_103a", TCGEN_F16.requirement),
-            Some(88)
-        );
-        assert_eq!(
-            generated_requirement_ptx_floor("sm_110a", TCGEN_F16.requirement),
-            Some(90)
-        );
-        for target in ["sm_120a", "sm_121a"] {
-            assert!(!generated_target_satisfied(target, &generated), "{target}");
-        }
-        for target in ["sm_100f", "sm_101f", "sm_103f", "sm_110f"] {
-            assert!(generated_target_satisfied(target, &generated), "{target}");
-        }
-        assert_eq!(
-            select_target_with_generated(DetectedFeatures::Basic, &generated).unwrap(),
-            "sm_100a"
-        );
-
-        let generated = GeneratedModuleRequirements::from_targets(vec![&TCGEN_I8]);
-        assert_eq!(
-            generated_ptx_isa_requirement(&generated).unwrap(),
-            PtxIsaRequirement::Ptx86
-        );
-        assert_eq!(
-            generated_ptx_isa_requirement_for_target(&generated, "sm_100a").unwrap(),
-            PtxIsaRequirement::Ptx86
-        );
-        assert_eq!(
-            required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx86).unwrap(),
-            None
-        );
-        for (target, requirement) in [
-            ("sm_101a", PtxIsaRequirement::Ptx86),
-            ("sm_110a", PtxIsaRequirement::Ptx90),
-        ] {
-            assert_eq!(
-                generated_ptx_isa_requirement_for_target(&generated, target).unwrap(),
-                requirement
-            );
-            assert_eq!(required_ptx_feature(target, requirement).unwrap(), None);
-        }
-        assert!(!generated_target_satisfied("sm_103a", &generated));
-        assert!(!generated_target_satisfied("sm_100f", &generated));
-    }
-
-    #[test]
-    fn sm101_aliases_reject_an_aggregate_ptx90_requirement() {
-        let generated = GeneratedModuleRequirements::from_targets(vec![&TCGEN_F16, &PTX90]);
-
-        for target in ["sm_101a", "sm_101f"] {
-            let error = generated_ptx_isa_requirement_for_target(&generated, target).unwrap_err();
-            assert!(
-                error.contains("renamed the sm_101 target to sm_110"),
-                "{error}"
-            );
-
-            let f16 = GeneratedModuleRequirements::from_targets(vec![&TCGEN_F16]);
-            let text = ModuleRequirements {
-                features: DetectedFeatures::Basic,
-                ptx_isa: PtxIsaRequirement::Ptx90,
-            };
-            let error =
-                merge_generated_module_requirements_for_target(text, &f16, target).unwrap_err();
-            assert!(
-                error.contains("renamed the sm_101 target to sm_110"),
-                "{error}"
-            );
-        }
-    }
-
-    #[test]
-    fn dynamic_stack_calls_require_ptx73_and_sm52() {
-        for llvm in [
-            "%saved = call ptr @llvm.stacksave.p0()\n",
-            "%saved = tail call ptr addrspace(12) @llvm.stacksave.p12()\n",
-            "call void @llvm.stackrestore.p3(ptr addrspace(3) %saved)\n",
-            "%saved = call i8* @llvm.stacksave()\n",
-            "call void @llvm.stackrestore(i8* %saved)\n",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(llvm);
-            assert!(
-                requirements
-                    .features
-                    .contains(DetectedFeatures::DynamicStack),
-                "{llvm}"
-            );
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx73, "{llvm}");
-        }
-
-        for near_match in [
-            "%saved = call ptr @llvm.stacksavex.p0()\n",
-            "%saved = call ptr @llvm.stacksave_extra.p0()\n",
-            "%saved = call ptr @llvm.stacksave.p()\n",
-            "%saved = call ptr @llvm.stacksave.p0x()\n",
-            "%saved = call ptr @llvm.stacksave.p0.extra()\n",
-            "call void @llvm.stackrestorex.p0(ptr %saved)\n",
-            "call void @llvm.stackrestore.p0_extra(ptr %saved)\n",
-            "%saved = call ptr @llvm.stacksave.p0\n",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(near_match);
-            assert_eq!(
-                requirements.features,
-                DetectedFeatures::Basic,
-                "{near_match}"
-            );
-            assert_eq!(
-                requirements.ptx_isa,
-                PtxIsaRequirement::Default,
-                "{near_match}"
-            );
-        }
-
-        assert!(!arch_satisfies_feature(
-            50,
-            None,
-            DetectedFeatures::DynamicStack
-        ));
-        assert!(arch_satisfies_feature(
-            52,
-            None,
-            DetectedFeatures::DynamicStack
-        ));
-        for target in ["sm_70", "sm_86"] {
-            let parsed = target.parse::<CudaArch>().unwrap();
-            assert!(
-                validate_target_features(&parsed, DetectedFeatures::DynamicStack).is_ok(),
-                "{target}"
-            );
-        }
-        let sm_50 = "sm_50".parse::<CudaArch>().unwrap();
-        let error = validate_target_features(&sm_50, DetectedFeatures::DynamicStack).unwrap_err();
-        assert!(error.contains("DynamicStack"), "{error}");
-    }
-
-    #[test]
-    fn dynamic_stack_mentions_without_calls_do_not_raise_requirements() {
-        let non_calls = [
-            "declare ptr @llvm.stacksave.p0()\n",
-            "declare void @llvm.stackrestore.p0(ptr)\n",
-            "; %saved = call ptr @llvm.stacksave.p0()\n",
-            "!0 = !{!\"call ptr @llvm.stacksave.p0()\"}\n",
-            "@message = private constant [39 x i8] c\"call ptr @llvm.stacksave.p0()\\00\"\n",
-            "!1 = !{ptr @llvm.stacksave.p0}\n",
-            "declare ptr @llvm.stacksave.p0 ; call ptr @llvm.stacksave.p0()\n",
-        ];
-
-        for llvm in non_calls {
-            let requirements = detect_module_requirements_in_llvm_text(llvm);
-            assert_eq!(requirements.features, DetectedFeatures::Basic, "{llvm}");
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Default, "{llvm}");
-        }
-
-        let call_after_quoted_semicolon = concat!(
-            "@message = private constant [2 x i8] c\";\\00\"\n",
-            "%saved = call ptr @llvm.stacksave.p0() ; ignored comment\n",
-        );
-        assert!(
-            detect_module_requirements_in_llvm_text(call_after_quoted_semicolon)
-                .features
-                .contains(DetectedFeatures::DynamicStack)
-        );
-    }
-
-    #[test]
-    fn ptx73_feature_is_requested_only_when_the_target_default_is_older() {
-        assert_eq!(
-            ptx_isa_requirement_for_floor(72, "test", "test").unwrap(),
-            PtxIsaRequirement::Ptx73
-        );
-        assert_eq!(
-            ptx_isa_requirement_for_floor(73, "test", "test").unwrap(),
-            PtxIsaRequirement::Ptx73
-        );
-        assert_eq!(
-            ptx_isa_requirement_for_floor(74, "test", "test").unwrap(),
-            PtxIsaRequirement::Ptx78
-        );
-        for target in ["sm_70", "sm_80", "sm_86"] {
-            assert_eq!(
-                required_ptx_feature(target, PtxIsaRequirement::Ptx73).unwrap(),
-                Some("+ptx73"),
-                "{target}"
-            );
-        }
-        assert_eq!(
-            required_ptx_feature("sm_87", PtxIsaRequirement::Ptx73).unwrap(),
-            None
-        );
-    }
-
-    #[test]
-    fn every_shared_ptx_spelling_round_trips() {
-        for spelling in PTX_ISA_SPELLINGS {
-            let requirement = PtxIsaRequirement::from_spelling(*spelling).unwrap();
-            assert_eq!(requirement.spelling(), Some(*spelling));
-            assert!(requirement.feature().is_some());
-        }
-    }
-
-    #[test]
-    fn selection_candidates_cover_exactly_the_recorded_target_set() {
-        let candidates = KNOWN_CUDA_TARGET_CANDIDATES
-            .iter()
-            .copied()
-            .collect::<std::collections::BTreeSet<_>>();
-        let recorded = RECORDED_PTX_FLOORS
-            .iter()
-            .map(|entry| match entry.suffix {
-                Some(suffix) => format!("sm_{}{suffix}", entry.capability),
-                None => format!("sm_{}", entry.capability),
-            })
-            .collect::<std::collections::BTreeSet<_>>();
-        assert_eq!(
-            candidates,
-            recorded.iter().map(String::as_str).collect(),
-            "selection preference list and shared recorded-floor keys drifted"
-        );
-    }
-
-    #[test]
-    fn unrecorded_target_fails_closed_for_explicit_ptx() {
-        let error = required_ptx_feature("sm_89a", PtxIsaRequirement::Ptx80).unwrap_err();
-        assert!(error.contains("no recorded PTX ISA floor"));
-        let error = required_ptx_feature("sm_999a", PtxIsaRequirement::Default).unwrap_err();
-        assert!(error.contains("no recorded PTX ISA floor"));
-    }
-
-    #[test]
-    fn paired_minimum_target_diagnostic_preserves_range_meaning() {
-        static TARGETS: &[GeneratedTargetAlternative] = &[GeneratedTargetAlternative {
-            minimum_ptx: GeneratedPtxVersion::from_encoded(88),
-            hardware: GeneratedHardwareAlternative::MinimumSm(100),
-        }];
-        static CONTRACTS: &[GeneratedTargetContract] = &[GeneratedTargetContract {
-            selectors: &[],
-            alternatives: TARGETS,
-        }];
-
-        assert_eq!(
-            describe_generated_hardware(GeneratedHardwareTarget::TargetMatrix {
-                contracts: CONTRACTS,
-            }),
-            "sm_100 or newer at PTX 8.8"
-        );
-    }
-
-    #[test]
-    fn paired_target_matrix_flows_through_backend_target_resolution() {
-        let llvm = GeneratedModuleRequirements::from_targets(vec![&TCGEN_I8])
-            .for_backend(GeneratedIntrinsicBackend::LlvmNvptx);
-        let libnvvm = GeneratedModuleRequirements::from_targets(vec![&TCGEN_I8])
-            .for_backend(GeneratedIntrinsicBackend::LibNvvm);
-
-        assert!(generated_target_satisfied("sm_101a", &llvm));
-        assert!(!generated_target_satisfied("sm_101a", &libnvvm));
-        assert!(!generated_target_satisfied("sm_103a", &llvm));
-        assert!(generated_target_satisfied("sm_110a", &libnvvm));
-
-        assert_eq!(
-            resolve_ptx_target_with_generated(
-                Some("sm_101a"),
-                "CUDA_OXIDE_TARGET",
-                None,
-                DetectedFeatures::Basic,
-                &llvm,
-            )
-            .unwrap(),
-            ("sm_101a".into(), "CUDA_OXIDE_TARGET")
-        );
-        assert!(
-            resolve_ptx_target_with_generated(
-                Some("sm_103a"),
-                "CUDA_OXIDE_TARGET",
-                None,
-                DetectedFeatures::Basic,
-                &llvm,
-            )
-            .is_err()
-        );
-        assert_eq!(
-            resolve_ptx_target_with_generated(
-                None,
-                "CUDA_OXIDE_TARGET",
-                Some("sm_101a"),
-                DetectedFeatures::Basic,
-                &llvm,
-            )
-            .unwrap(),
-            ("sm_101a".into(), "detected GPU")
-        );
-        assert_eq!(
-            resolve_ptx_target_with_generated(
-                None,
-                "CUDA_OXIDE_TARGET",
-                Some("sm_101a"),
-                DetectedFeatures::Basic,
-                &libnvvm,
-            )
-            .unwrap(),
-            ("sm_100a".into(), "feature requirement")
-        );
-        assert_eq!(
-            resolve_ptx_target_with_generated(
-                None,
-                "CUDA_OXIDE_TARGET",
-                None,
-                DetectedFeatures::Basic,
-                &llvm
-            )
-            .unwrap(),
-            ("sm_100a".into(), "feature requirement")
-        );
-
-        let base = ModuleRequirements {
-            features: DetectedFeatures::Basic,
-            ptx_isa: PtxIsaRequirement::Default,
-        };
-        assert_eq!(
-            merge_generated_module_requirements_for_target(base, &llvm, "sm_101a")
-                .unwrap()
-                .ptx_isa,
-            PtxIsaRequirement::Ptx86
-        );
-        assert_eq!(
-            merge_generated_module_requirements_for_target(base, &llvm, "sm_110a")
-                .unwrap()
-                .ptx_isa,
-            PtxIsaRequirement::Ptx90
-        );
-
-        let error = crate::export::resolve_nvvm_target_with_generated(
-            Some("sm_103a"),
-            None,
-            None,
-            &libnvvm,
-        )
-        .unwrap_err()
-        .to_string();
-        assert!(error.contains("tcgen_i8"), "{error}");
-        assert_eq!(
-            crate::export::resolve_nvvm_target_with_generated(
-                Some("sm_110a"),
-                None,
-                None,
-                &libnvvm,
-            )
-            .unwrap()
-            .sm(),
-            "sm_110a"
-        );
-        assert_eq!(
-            crate::export::resolve_nvvm_target_with_generated(
-                None,
-                Some("sm_103a"),
-                None,
-                &libnvvm,
-            )
-            .unwrap()
-            .sm(),
-            "sm_100a"
-        );
-    }
-
-    #[test]
-    fn generated_ptx87_exact_sm120a_requirement_is_preserved() {
-        let generated = GeneratedModuleRequirements::from_targets(vec![&PTX87_EXACT_SM120A]);
-
-        assert_eq!(
-            generated_ptx_isa_requirement(&generated).unwrap(),
-            PtxIsaRequirement::Ptx87
-        );
-        assert!(PtxIsaRequirement::Ptx86 < PtxIsaRequirement::Ptx87);
-        assert_eq!(
-            required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx87).unwrap(),
-            Some("+ptx87")
-        );
-        assert_eq!(
-            required_ptx_feature("sm_120a", PtxIsaRequirement::Ptx87).unwrap(),
-            None
-        );
-        assert_eq!(
-            required_ptx_feature("sm_100f", PtxIsaRequirement::Ptx87).unwrap(),
-            None
-        );
-        assert_eq!(
-            required_ptx_feature("sm_120f", PtxIsaRequirement::Ptx87).unwrap(),
-            None
-        );
-        assert_eq!(
-            select_target_with_generated(DetectedFeatures::Basic, &generated).unwrap(),
-            "sm_120a"
-        );
-        assert!(generated_target_satisfied("sm_120a", &generated));
-        for incompatible in ["sm_120", "sm_120f", "sm_121a"] {
-            assert!(
-                !generated_target_satisfied(incompatible, &generated),
-                "{incompatible}"
-            );
-        }
-    }
-
-    #[test]
-    fn generated_ptx88_and_ptx90_floors_are_preserved() {
-        let generated = GeneratedModuleRequirements::from_targets(vec![&PTX88]);
-        assert_eq!(
-            generated_ptx_isa_requirement(&generated).unwrap(),
-            PtxIsaRequirement::Ptx88
-        );
-        assert_eq!(
-            required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx88).unwrap(),
-            Some("+ptx88")
-        );
-        assert_eq!(
-            required_ptx_feature("sm_103a", PtxIsaRequirement::Ptx88).unwrap(),
-            None
-        );
-        assert_eq!(
-            ptx_isa_requirement_for_floor(89, "test", "test").unwrap(),
-            PtxIsaRequirement::Ptx90
-        );
-        assert_eq!(
-            required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx90).unwrap(),
-            Some("+ptx90")
-        );
-        assert_eq!(
-            required_ptx_feature("sm_110a", PtxIsaRequirement::Ptx90).unwrap(),
-            None
-        );
-        validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx87, Some(21)).unwrap();
-        validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx88, None).unwrap();
-        validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx88, Some(21)).unwrap();
-        validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx88, Some(22)).unwrap();
-        assert!(validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx90, None).is_err());
-        assert!(validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx90, Some(21)).is_err());
-        validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx90, Some(22)).unwrap();
-
-        let generated = GeneratedModuleRequirements::from_targets(vec![&PTX91_FUTURE]);
-        let error = generated_ptx_isa_requirement(&generated).unwrap_err();
-
-        assert!(error.contains("requires PTX 9.1"), "{error}");
-        assert!(
-            error.contains("newer than cuda-oxide can request"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn generated_redux_floor_matches_the_lowered_ptx_detector() {
-        use crate::generated_intrinsic_targets::generated_intrinsic_target_by_marker;
-
-        let target = generated_intrinsic_target_by_marker("v1:i0017").unwrap();
-        let generated = GeneratedModuleRequirements::from_targets(vec![target]);
-        let detected = detect_module_requirements_in_llvm_text("redux.sync.add.s32 $0, $1, $2;");
-
-        assert_eq!(
-            generated_ptx_isa_requirement(&generated).unwrap(),
-            detected.ptx_isa
-        );
-        assert_eq!(detected.ptx_isa, PtxIsaRequirement::Ptx70);
-        assert!(detected.features.contains(DetectedFeatures::Sm80));
-        for arch in ["sm_75", "sm_80", "sm_90"] {
-            assert_eq!(
-                generated_target_satisfied(arch, &generated),
-                arch_satisfies(arch, detected.features),
-                "{arch}"
-            );
-        }
-    }
-
-    #[test]
-    fn generated_packed_atomic_floors_are_backend_specific() {
-        use crate::generated_intrinsic_targets::{
-            GeneratedIntrinsicBackend, generated_intrinsic_target_by_marker,
-        };
-
-        let f16 = generated_intrinsic_target_by_marker("v1:i0014").unwrap();
-        let llvm = GeneratedModuleRequirements::from_targets(vec![f16])
-            .for_backend(GeneratedIntrinsicBackend::LlvmNvptx);
-        assert!(generated_target_satisfied("sm_70", &llvm));
-        assert_eq!(
-            generated_ptx_isa_requirement(&llvm).unwrap(),
-            PtxIsaRequirement::Ptx62
-        );
-
-        let libnvvm = GeneratedModuleRequirements::from_targets(vec![f16])
-            .for_backend(GeneratedIntrinsicBackend::LibNvvm);
-        assert!(!generated_target_satisfied("sm_70", &libnvvm));
-        assert!(generated_target_satisfied("sm_75", &libnvvm));
-
-        let bf16 = generated_intrinsic_target_by_marker("v1:i0015").unwrap();
-        let bf16 = GeneratedModuleRequirements::from_targets(vec![bf16]);
-        assert!(!generated_target_satisfied("sm_89", &bf16));
-        assert!(generated_target_satisfied("sm_90", &bf16));
-        let error = resolve_ptx_target_with_generated(
-            Some("sm_89"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            DetectedFeatures::Basic,
-            &bf16,
-        )
-        .unwrap_err()
-        .to_string();
-        assert!(error.contains("packed_atomic_add_bf16x2"), "{error}");
-        assert!(error.contains("sm_90 or newer"), "{error}");
-    }
-
-    #[test]
-    fn generated_non_mma_tcgen05_targets_preserve_the_backend_split() {
-        use crate::generated_intrinsic_targets::{
-            GENERATED_INTRINSIC_TARGETS, GeneratedIntrinsicBackend, GeneratedIntrinsicVariant,
-        };
-
-        let targets = GENERATED_INTRINSIC_TARGETS
-            .iter()
-            .filter(|target| {
-                target.id.starts_with("tcgen05_")
-                    && !matches!(target.variant, GeneratedIntrinsicVariant::Tcgen05Mma { .. })
-            })
-            .collect::<Vec<_>>();
-        assert_eq!(targets.len(), 209);
-
-        for target in targets {
-            let llvm = GeneratedModuleRequirements::from_targets(vec![target])
-                .for_backend(GeneratedIntrinsicBackend::LlvmNvptx);
-            let libnvvm = GeneratedModuleRequirements::from_targets(vec![target])
-                .for_backend(GeneratedIntrinsicBackend::LibNvvm);
-
-            assert_eq!(
-                generated_ptx_isa_requirement(&llvm).unwrap(),
-                PtxIsaRequirement::Ptx86,
-                "{}",
-                target.id
-            );
-            assert_eq!(
-                generated_ptx_isa_requirement(&libnvvm).unwrap(),
-                PtxIsaRequirement::Ptx86,
-                "{}",
-                target.id
-            );
-            for arch in ["sm_100a", "sm_103a", "sm_110a"] {
-                assert!(
-                    generated_target_satisfied(arch, &llvm),
-                    "{} {arch}",
-                    target.id
-                );
-                assert!(
-                    generated_target_satisfied(arch, &libnvvm),
-                    "{} {arch}",
-                    target.id
-                );
-            }
-            assert!(
-                generated_target_satisfied("sm_101a", &llvm),
-                "{}",
-                target.id
-            );
-            assert!(
-                !generated_target_satisfied("sm_101a", &libnvvm),
-                "{}",
-                target.id
-            );
-            assert!(
-                !generated_target_satisfied("sm_120a", &llvm),
-                "{}",
-                target.id
-            );
-            assert!(
-                !generated_target_satisfied("sm_120a", &libnvvm),
-                "{}",
-                target.id
-            );
-        }
-    }
-
-    #[test]
-    fn generated_packed_conversion_floors_require_ampere() {
-        use crate::generated_intrinsic_targets::{
-            GeneratedIntrinsicBackend, generated_intrinsic_target_by_marker,
-        };
-
-        for marker in [
-            "v1:i0071", "v1:i0081", "v1:i0082", "v1:i0083", "v1:i0084", "v1:i0085",
-        ] {
-            let target = generated_intrinsic_target_by_marker(marker).unwrap();
-            for backend in [
-                GeneratedIntrinsicBackend::LlvmNvptx,
-                GeneratedIntrinsicBackend::LibNvvm,
-            ] {
-                let generated =
-                    GeneratedModuleRequirements::from_targets(vec![target]).for_backend(backend);
-                assert_eq!(
-                    generated_ptx_isa_requirement(&generated).unwrap(),
-                    PtxIsaRequirement::Ptx70,
-                    "{marker} {backend:?}"
-                );
-                assert!(!generated_target_satisfied("sm_75", &generated), "{marker}");
-                assert!(generated_target_satisfied("sm_80", &generated), "{marker}");
-                let error = validate_generated_target("sm_75", &generated).unwrap_err();
-                assert!(error.contains(target.id), "{error}");
-                assert!(error.contains("sm_80 or newer"), "{error}");
-            }
-        }
-    }
-
-    #[test]
-    fn generated_cp_async_floors_require_ampere() {
-        use crate::generated_intrinsic_targets::{
-            GeneratedIntrinsicBackend, generated_intrinsic_target_by_marker,
-        };
-
-        for marker in [
-            "v1:i0086", "v1:i0087", "v1:i0088", "v1:i0089", "v1:i0090", "v1:i0091", "v1:i0092",
-            "v1:i0093", "v1:i0094", "v1:i0095", "v1:i0096", "v1:i0101", "v1:i0102", "v1:i0103",
-            "v1:i0104",
-        ] {
-            let target = generated_intrinsic_target_by_marker(marker).unwrap();
-            for backend in [
-                GeneratedIntrinsicBackend::LlvmNvptx,
-                GeneratedIntrinsicBackend::LibNvvm,
-            ] {
-                let generated =
-                    GeneratedModuleRequirements::from_targets(vec![target]).for_backend(backend);
-                assert_eq!(
-                    generated_ptx_isa_requirement(&generated).unwrap(),
-                    PtxIsaRequirement::Ptx70,
-                    "{marker} {backend:?}"
-                );
-                assert!(!generated_target_satisfied("sm_75", &generated), "{marker}");
-                assert!(generated_target_satisfied("sm_80", &generated), "{marker}");
-                let error = validate_generated_target("sm_75", &generated).unwrap_err();
-                assert!(error.contains(target.id), "{error}");
-                assert!(error.contains("sm_80 or newer"), "{error}");
-            }
-        }
-    }
-
-    #[test]
-    fn generated_dot_product_floors_record_sm61_and_split_backend_support() {
-        use crate::generated_intrinsic_targets::{
-            GeneratedIntrinsicBackend, generated_intrinsic_target_by_marker,
-        };
-
-        for marker in ["v1:i0030", "v1:i0031", "v1:i0032", "v1:i0033"] {
-            let target = generated_intrinsic_target_by_marker(marker).unwrap();
-            let llvm = GeneratedModuleRequirements::from_targets(vec![target])
-                .for_backend(GeneratedIntrinsicBackend::LlvmNvptx);
-            assert!(matches!(
-                llvm.requirement(target).hardware,
-                GeneratedHardwareTarget::AnyOf(alternatives)
-                    if alternatives == [GeneratedHardwareAlternative::MinimumSm(61)]
-            ));
-            assert!(!generated_target_satisfied("sm_60", &llvm), "{marker}");
-            assert!(generated_target_satisfied("sm_70", &llvm), "{marker}");
-            assert_eq!(
-                generated_ptx_isa_requirement(&llvm).unwrap(),
-                PtxIsaRequirement::Default
-            );
-
-            let error = validate_generated_target("sm_60", &llvm)
-                .unwrap_err()
-                .to_string();
-            assert!(error.contains(target.id), "{error}");
-            assert!(error.contains("sm_61 or newer"), "{error}");
-
-            let libnvvm = GeneratedModuleRequirements::from_targets(vec![target])
-                .for_backend(GeneratedIntrinsicBackend::LibNvvm);
-            assert!(!generated_target_satisfied("sm_74", &libnvvm));
-            assert!(generated_target_satisfied("sm_75", &libnvvm));
-        }
-    }
-
-    #[test]
-    fn test_feature_detection_reads_llvm_ir_snippets() {
-        let llvm = r#"
-            call void asm sideeffect "wgmma.fence.sync.aligned", ""()
-            call void @llvm.nvvm.tcgen05.alloc()
-            call void asm sideeffect "cluster.sync.aligned", ""()
-            call void asm sideeffect "cp.async.bulk.tensor.2d.shared::cluster.global", ""()
-            call void asm sideeffect "cp.async.ca.shared.global", ""()
-        "#;
-
-        assert!(contains_wgmma_features(llvm));
-        assert!(contains_blackwell_features(llvm));
-        assert!(contains_cluster_features(llvm));
-        assert!(contains_tma_features(llvm));
-        assert!(contains_sm80_features(llvm));
-        let detected = detect_features_in_llvm_text(llvm);
-        for feature in [
-            DetectedFeatures::Blackwell,
-            DetectedFeatures::Wgmma,
-            DetectedFeatures::Cluster,
-            DetectedFeatures::Tma,
-            DetectedFeatures::Sm80,
-        ] {
-            assert!(detected.contains(feature), "missing {feature:?}");
-        }
-        assert!(
-            select_target(detected).is_err(),
-            "Hopper-only WGMMA and Blackwell-only tcgen05 are incompatible"
-        );
-    }
-
-    #[test]
-    fn test_sm80_detection_accepts_inline_ptx_and_nvvm_intrinsics() {
-        for llvm in [
-            r#"call void asm sideeffect "cp.async.ca.shared.global [%0], [%1], 4;", "l,l"()"#,
-            "call void @llvm.nvvm.cp.async.ca.shared.global.8(ptr addrspace(3) %dst, ptr addrspace(1) %src)",
-            r#"call void asm sideeffect "cp.async.commit_group;", ""()"#,
-            "call void @llvm.nvvm.cp.async.wait.all()",
-        ] {
-            assert!(contains_sm80_features(llvm), "missed cp.async in {llvm}");
-            assert_eq!(detect_features_in_llvm_text(llvm), DetectedFeatures::Sm80);
-        }
-    }
-
-    #[test]
-    fn test_bf16x2_detection_matches_exact_architecture_floors() {
-        for mnemonic in [
-            "add.rn.bf16x2 $0, $1, $2;",
-            "sub.rn.bf16x2 $0, $1, $2;",
-            "mul.rn.bf16x2 $0, $1, $2;",
-        ] {
-            assert!(contains_sm90_features(mnemonic));
-            assert!(!contains_sm80_features(mnemonic));
-            assert_eq!(
-                detect_features_in_llvm_text(mnemonic),
-                DetectedFeatures::Sm90
-            );
-        }
-
-        for mnemonic in ["add.rn.bf16x2\t$0, $1, $2;", "sub.rn.bf16x2\\09$0, $1, $2;"] {
-            assert_eq!(
-                detect_features_in_llvm_text(mnemonic),
-                DetectedFeatures::Sm90,
-                "{mnemonic:?}"
-            );
-        }
-
-        for mnemonic in [
-            "fma.rn.bf16x2 $0, $1, $2, $3;",
-            "fma.rn.relu.bf16x2 $0, $1, $2, $3;",
-            "min.bf16x2 $0, $1, $2;",
-            "max.bf16x2 $0, $1, $2;",
-            "neg.bf16x2 $0, $1;",
-            "abs.bf16x2 $0, $1;",
-        ] {
-            assert!(!contains_sm90_features(mnemonic));
-            assert!(contains_sm80_features(mnemonic));
-            assert_eq!(
-                detect_features_in_llvm_text(mnemonic),
-                DetectedFeatures::Sm80
-            );
-        }
-
-        for near_miss in [
-            "add.rn.bf16x2x $0, $1, $2;",
-            "fma.rn.bf16x2x $0, $1, $2, $3;",
-            "add.rn.bf16x2\\5C09$0, $1, $2;",
-        ] {
-            assert!(!contains_sm90_features(near_miss));
-            assert!(!contains_sm80_features(near_miss));
-            assert_eq!(
-                detect_features_in_llvm_text(near_miss),
-                DetectedFeatures::Basic
-            );
-        }
-    }
-
-    #[test]
-    fn f32x2_family_detection_requires_sm100_and_ptx86() {
-        for mnemonic in [
-            "add.f32x2 $0, $1, $2;",
-            "add.rz.f32x2 $0, $1, $2;",
-            "sub.rm.f32x2 $0, $1, $2;",
-            "mul.rp.ftz.f32x2 $0, $1, $2;",
-            "fma.rn.f32x2 $0, $1, $2, $3;",
-            "fma.rz.ftz.f32x2\\09$0, $1, $2, $3;",
-        ] {
-            assert!(contains_f32x2_features(mnemonic));
-            let requirements = detect_module_requirements_in_llvm_text(mnemonic);
-            assert_eq!(requirements.features, DetectedFeatures::Sm100);
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86);
-            assert!(!arch_satisfies("sm_90", requirements.features));
-            assert!(arch_satisfies("sm_100", requirements.features));
-            assert!(arch_satisfies("sm_120", requirements.features));
-        }
-
-        for near_miss in [
-            "add.rn.f32x2x $0, $1, $2;",
-            "fmax.rn.f32x2 $0, $1, $2;",
-            "myadd.rn.f32x2 $0, $1, $2;",
-            "add.rn.f32 $0, $1, $2;",
-        ] {
-            assert!(!contains_f32x2_features(near_miss));
-        }
-    }
-
-    #[test]
-    fn dense_bf16_mma_detection_applies_exact_sm80_and_ptx70_floors() {
-        let mnemonic =
-            "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};";
-        for spelling in [
-            mnemonic,
-            "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\t{$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\\09{$0}, {$1}, {$2}, {$3};",
-            ";mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "prefix\\0Amma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "\"mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "{mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "$L:mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "/* comment */mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "@p mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "@!%p\\09mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                contains_mma_m16n8k16_f32_bf16_features(spelling),
-                "missed {spelling:?}"
-            );
-        }
-
-        let requirements = detect_module_requirements_in_llvm_text(mnemonic);
-        assert_eq!(
-            requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Ptx70,
-            }
-        );
-        assert_eq!(select_target(requirements.features).unwrap(), "sm_80");
-
-        let lower_target = resolve_ptx_target(
-            Some("sm_75"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            requirements.features,
-        )
-        .unwrap_err();
-        assert!(
-            lower_target
-                .to_string()
-                .contains("cannot lower detected feature Sm80"),
-            "{lower_target}"
-        );
-        let (target, _) = resolve_ptx_target(
-            Some("sm_80"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            requirements.features,
-        )
-        .unwrap();
-        assert_eq!(target, "sm_80");
-
-        for near_miss in [
-            "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sp.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32x {$0}, {$1}, {$2}, {$3};",
-            "not_mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "$mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "%mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "@mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "!mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "@!mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "not$mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "/mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            ")mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                !contains_mma_m16n8k16_f32_bf16_features(near_miss),
-                "matched {near_miss:?}"
-            );
-        }
-
-        let combined = format!(
-            "{mnemonic}\n{}",
-            "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;"
-        );
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&combined),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-    }
-
-    #[test]
-    fn packed_atomic_detection_enforces_native_architecture_and_ptx_floors() {
-        for f16 in [
-            "atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "atom.global.add.noftz.f16x2\t$0, [$1], $2;",
-            "atom.global.add.noftz.f16x2\\09$0, [$1], $2;",
-            ";atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "prefix\\0Aatom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "\"atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "{atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "$L:atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "/* comment */atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "@p atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "@!%p\\09atom.global.add.noftz.f16x2 $0, [$1], $2;",
-        ] {
-            assert!(contains_packed_f16_atomic_features(f16), "{f16:?}");
-            assert!(!contains_packed_bf16_atomic_features(f16), "{f16:?}");
-            assert_eq!(detect_features_in_llvm_text(f16), DetectedFeatures::Basic);
-            assert_eq!(
-                detect_module_requirements_in_llvm_text(f16).ptx_isa,
-                PtxIsaRequirement::Ptx62
-            );
-        }
-        assert_eq!(
-            required_ptx_feature("sm_70", PtxIsaRequirement::Ptx62).unwrap(),
-            Some("+ptx62")
-        );
-        assert_eq!(
-            resolve_ptx_target(
-                Some("sm_70"),
-                "CUDA_OXIDE_TARGET",
-                None,
-                DetectedFeatures::Basic
-            )
-            .unwrap()
-            .0,
-            "sm_70"
-        );
-
-        for bf16 in [
-            "atom.global.add.noftz.bf16x2 $0, [$1], $2;",
-            "atom.global.add.noftz.bf16x2\t$0, [$1], $2;",
-            "atom.global.add.noftz.bf16x2\\0A$0, [$1], $2;",
-        ] {
-            assert!(contains_packed_bf16_atomic_features(bf16), "{bf16:?}");
-            assert!(!contains_packed_f16_atomic_features(bf16), "{bf16:?}");
-            assert_eq!(detect_features_in_llvm_text(bf16), DetectedFeatures::Sm90);
-            assert_eq!(
-                detect_module_requirements_in_llvm_text(bf16).ptx_isa,
-                PtxIsaRequirement::Ptx78
-            );
-        }
-        assert_eq!(select_target(DetectedFeatures::Sm90).unwrap(), "sm_90");
-        let rejected = resolve_ptx_target(
-            Some("sm_80"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            DetectedFeatures::Sm90,
-        )
-        .expect_err("native bf16x2 atomic add must reject sm_80")
-        .to_string();
-        assert!(rejected.contains("cannot lower detected feature Sm90"));
-        let near_miss = resolve_ptx_target(
-            Some("sm_89"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            DetectedFeatures::Sm90,
-        )
-        .expect_err("the architecture immediately below sm_90 must be rejected")
-        .to_string();
-        assert!(near_miss.contains("cannot lower detected feature Sm90"));
-
-        let both = "atom.global.add.noftz.f16x2 $0, [$1], $2; \
-                    atom.global.add.noftz.bf16x2 $0, [$1], $2;";
-        let requirements = detect_module_requirements_in_llvm_text(both);
-        assert_eq!(requirements.features, DetectedFeatures::Sm90);
-        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx78);
-
-        let dense_bf16_mma =
-            "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};";
-        let mma_f16_requirements = detect_module_requirements_in_llvm_text(&format!(
-            "{dense_bf16_mma}\natom.global.add.noftz.f16x2 $0, [$1], $2;"
-        ));
-        assert_eq!(
-            mma_f16_requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Ptx70,
-            }
-        );
-        assert_eq!(
-            select_target(mma_f16_requirements.features).unwrap(),
-            "sm_80"
-        );
-
-        let mma_bf16_requirements = detect_module_requirements_in_llvm_text(&format!(
-            "{dense_bf16_mma}\natom.global.add.noftz.bf16x2 $0, [$1], $2;"
-        ));
-        assert_eq!(
-            mma_bf16_requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm90 | DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-        assert_eq!(
-            select_target(mma_bf16_requirements.features).unwrap(),
-            "sm_90"
-        );
-
-        for near_miss in [
-            "atom.global.add.noftz.f16x2x $0, [$1], $2;",
-            "atom.global.add.noftz.bf16x2x $0, [$1], $2;",
-            "not_atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "not_atom.global.add.noftz.bf16x2 $0, [$1], $2;",
-            "not.atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "not.atom.global.add.noftz.bf16x2 $0, [$1], $2;",
-            "$atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "%atom.global.add.noftz.bf16x2 $0, [$1], $2;",
-            "@atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "!atom.global.add.noftz.bf16x2 $0, [$1], $2;",
-            "@!atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "not$atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "/atom.global.add.noftz.bf16x2 $0, [$1], $2;",
-            ")atom.global.add.noftz.f16x2 $0, [$1], $2;",
-            "atom.shared.add.noftz.f16x2 $0, [$1], $2;",
-            "atom.global.add.bf16x2 $0, [$1], $2;",
-            "red.global.add.noftz.bf16x2 [$0], $1;",
-            "atom.global.add.noftz.f16x2\\5C09$0, [$1], $2;",
-        ] {
-            assert!(!contains_packed_f16_atomic_features(near_miss));
-            assert!(!contains_packed_bf16_atomic_features(near_miss));
-            assert_eq!(
-                detect_module_requirements_in_llvm_text(near_miss),
-                ModuleRequirements {
-                    features: DetectedFeatures::Basic,
-                    ptx_isa: PtxIsaRequirement::Default,
-                },
-                "{near_miss:?}"
-            );
-        }
-    }
-
-    #[test]
-    fn fp64_mma_and_packed_atomics_take_the_strongest_target_floor() {
-        let dense_bf16_mma =
-            "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};";
-        let dense_fp64_mma =
-            "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};";
-
-        let fp64_f16_requirements = detect_module_requirements_in_llvm_text(&format!(
-            "{dense_fp64_mma}\natom.global.add.noftz.f16x2 $0, [$1], $2;"
-        ));
-        assert_eq!(
-            fp64_f16_requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Ptx70,
-            }
-        );
-        assert_eq!(
-            select_target(fp64_f16_requirements.features).unwrap(),
-            "sm_80"
-        );
-
-        let fp64_bf16_requirements = detect_module_requirements_in_llvm_text(&format!(
-            "{dense_fp64_mma}\natom.global.add.noftz.bf16x2 $0, [$1], $2;"
-        ));
-        assert_eq!(
-            fp64_bf16_requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm90 | DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-        assert_eq!(
-            select_target(fp64_bf16_requirements.features).unwrap(),
-            "sm_90"
-        );
-
-        let all_four = format!(
-            "{dense_bf16_mma}\n{dense_fp64_mma}\n\
-             atom.global.add.noftz.f16x2 $0, [$1], $2;\n\
-             atom.global.add.noftz.bf16x2 $0, [$1], $2;"
-        );
-        let all_four_requirements = detect_module_requirements_in_llvm_text(&all_four);
-        assert_eq!(
-            all_four_requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm90 | DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-        assert_eq!(
-            select_target(all_four_requirements.features).unwrap(),
-            "sm_90"
-        );
-    }
-
-    #[test]
-    fn dense_f16_mma_detection_applies_exact_sm80_and_ptx70_floors() {
-        let mnemonic = "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};";
-        for spelling in [
-            mnemonic,
-            "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\t{$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\\09{$0}, {$1}, {$2}, {$3};",
-            ";mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "prefix\\0Amma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "\"mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "{mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "$L:mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "/* comment */mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "@p mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "@!%p\\09mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                contains_mma_m16n8k16_f32_f16_features(spelling),
-                "missed {spelling:?}"
-            );
-        }
-
-        let requirements = detect_module_requirements_in_llvm_text(mnemonic);
-        assert_eq!(
-            requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Ptx70,
-            }
-        );
-        assert_eq!(select_target(requirements.features).unwrap(), "sm_80");
-
-        let lower_target = resolve_ptx_target(
-            Some("sm_75"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            requirements.features,
-        )
-        .unwrap_err();
-        assert!(
-            lower_target
-                .to_string()
-                .contains("cannot lower detected feature Sm80"),
-            "{lower_target}"
-        );
-        let (target, _) = resolve_ptx_target(
-            Some("sm_80"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            requirements.features,
-        )
-        .unwrap();
-        assert_eq!(target, "sm_80");
-
-        for near_miss in [
-            "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sp.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32x {$0}, {$1}, {$2}, {$3};",
-            "not_mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "$mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "%mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "@mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "!mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "@!mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "not$mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "/mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            ")mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                !contains_mma_m16n8k16_f32_f16_features(near_miss),
-                "matched {near_miss:?}"
-            );
-        }
-
-        let combined = format!(
-            "{mnemonic}\n{}",
-            "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;"
-        );
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&combined),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-    }
-
-    #[test]
-    fn tf32_mma_detection_applies_exact_sm80_and_ptx70_floors() {
-        let mnemonic = concat!(
-            "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 ",
-            "{$0, $1, $2, $3}, {$4, $5, $6, $7}, {$8, $9}, {$10, $11, $12, $13};"
-        );
-        for spelling in [
-            mnemonic,
-            "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\t{$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\\09{$0}, {$1}, {$2}, {$3};",
-            ";mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "prefix\\0Amma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "\"mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "{mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "$L:mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "/* comment */mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "@p mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "@!%p\\09mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                contains_mma_m16n8k8_f32_tf32_features(spelling),
-                "missed {spelling:?}"
-            );
-        }
-
-        let requirements = detect_module_requirements_in_llvm_text(mnemonic);
-        assert_eq!(requirements.features, DetectedFeatures::Sm80);
-        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx70);
-        let (target, _) =
-            resolve_ptx_target(None, "CUDA_OXIDE_TARGET", None, requirements.features)
-                .expect("auto-resolve");
-        assert_eq!(target, "sm_80");
-
-        for near_miss in [
-            "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sp.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32x {$0}, {$1}, {$2}, {$3};",
-            "not_mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "$mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "%mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "@mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "!mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "@!mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "not$mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            "/mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-            ")mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                !contains_mma_m16n8k8_f32_tf32_features(near_miss),
-                "matched {near_miss:?}"
-            );
-        }
-
-        let sm_75: CudaArch = "sm_75".parse().unwrap();
-        let sm_80: CudaArch = "sm_80".parse().unwrap();
-        assert!(validate_target_features(&sm_75, requirements.features).is_err());
-        assert!(validate_target_features(&sm_80, requirements.features).is_ok());
-        let error = resolve_ptx_target(
-            Some("sm_75"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            requirements.features,
-        )
-        .expect_err("sm_75 must not accept TF32 tensor-core MMA")
-        .to_string();
-        assert!(
-            error.contains("cannot lower detected feature Sm80"),
-            "{error}"
-        );
-
-        let combined = format!("{mnemonic}\nmovmatrix.sync.aligned.m8n8.trans.b16 $0, $1;");
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&combined),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-    }
-
-    #[test]
-    fn int8_mma_detection_applies_exact_sm80_and_ptx70_floors() {
-        let mut forms = 0;
-        for shape in ["m16n8k16", "m16n8k32"] {
-            for a_type in ["s8", "u8"] {
-                for b_type in ["s8", "u8"] {
-                    for satfinite in [false, true] {
-                        let overflow = if satfinite { ".satfinite" } else { "" };
-                        let spelling = format!(
-                            "mma.sync.aligned.{shape}.row.col{overflow}.s32.{a_type}.{b_type}.s32 {{$0}}, {{$1}}, {{$2}}, {{$3}};"
-                        );
-                        assert!(
-                            contains_dense_int8_mma_features(&spelling),
-                            "missed {spelling:?}"
-                        );
-                        assert_eq!(
-                            detect_module_requirements_in_llvm_text(&spelling),
-                            ModuleRequirements {
-                                features: DetectedFeatures::Sm80,
-                                ptx_isa: PtxIsaRequirement::Ptx70,
-                            },
-                            "{spelling}"
-                        );
-                        forms += 1;
-                    }
-                }
-            }
-        }
-        assert_eq!(forms, 16);
-
-        for spelling in [
-            "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32\t{$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\\09{$0}, {$1}, {$2}, {$3};",
-            ";mma.sync.aligned.m16n8k16.row.col.s32.u8.u8.s32 {$0}, {$1}, {$2}, {$3};",
-            "prefix\\0Amma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32 {$0}, {$1}, {$2}, {$3};",
-            "@p mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32 {$0}, {$1}, {$2}, {$3};",
-            "@!%p\\09mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                contains_dense_int8_mma_features(spelling),
-                "missed {spelling:?}"
-            );
-        }
-
-        let representative = concat!(
-            "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32 ",
-            "{$0, $1, $2, $3}, {$4, $5}, {$6}, {$7, $8, $9, $10};"
-        );
-        let requirements = detect_module_requirements_in_llvm_text(representative);
-        let (target, _) =
-            resolve_ptx_target(None, "CUDA_OXIDE_TARGET", None, requirements.features)
-                .expect("auto-resolve");
-        assert_eq!(target, "sm_80");
-
-        for near_miss in [
-            "mma.sync.aligned.m16n8k8.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.col.row.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32x {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32.satfinite {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.satfiniteX.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32x {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.u32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k16.row.col.s32.s4.u8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k16.row.col.s32.u8.f16.s32 {$0}, {$1}, {$2}, {$3};",
-            "not_mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "$mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "$mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "%mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "@mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "!mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "@!mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "not$mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "/mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            ")mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                !contains_dense_int8_mma_features(near_miss),
-                "matched {near_miss:?}"
-            );
-        }
-
-        let sm_75: CudaArch = "sm_75".parse().unwrap();
-        let sm_80: CudaArch = "sm_80".parse().unwrap();
-        assert!(validate_target_features(&sm_75, requirements.features).is_err());
-        assert!(validate_target_features(&sm_80, requirements.features).is_ok());
-        let error = resolve_ptx_target(
-            Some("sm_75"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            requirements.features,
-        )
-        .expect_err("sm_75 must not accept INT8 tensor-core MMA")
-        .to_string();
-        assert!(
-            error.contains("cannot lower detected feature Sm80"),
-            "{error}"
-        );
-
-        let combined = format!("{representative}\nmovmatrix.sync.aligned.m8n8.trans.b16 $0, $1;");
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&combined),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-    }
-
-    #[test]
-    fn dense_int4_mma_detection_applies_exact_sm80_and_ptx70_floors() {
-        let mut forms = 0;
-        for shape in ["m16n8k32", "m16n8k64"] {
-            for a_type in ["s4", "u4"] {
-                for b_type in ["s4", "u4"] {
-                    for satfinite in [false, true] {
-                        let overflow = if satfinite { ".satfinite" } else { "" };
-                        let spelling = format!(
-                            "mma.sync.aligned.{shape}.row.col{overflow}.s32.{a_type}.{b_type}.s32 {{$0}}, {{$1}}, {{$2}}, {{$3}};"
-                        );
-                        assert!(
-                            contains_dense_int4_mma_features(&spelling),
-                            "missed {spelling:?}"
-                        );
-                        assert!(
-                            !contains_mma_m8n8k32_int4_features(&spelling),
-                            "m16 form entered the m8 INT4 detector: {spelling:?}"
-                        );
-                        assert!(
-                            !contains_dense_int8_mma_features(&spelling),
-                            "INT4 form entered the dense INT8 detector: {spelling:?}"
-                        );
-                        assert_eq!(
-                            detect_module_requirements_in_llvm_text(&spelling),
-                            ModuleRequirements {
-                                features: DetectedFeatures::Sm80,
-                                ptx_isa: PtxIsaRequirement::Ptx70,
-                            },
-                            "{spelling}"
-                        );
-                        forms += 1;
-                    }
-                }
-            }
-        }
-        assert_eq!(forms, 16);
-
-        for spelling in [
-            "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.u4.s32\t{$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\\09{$0}, {$1}, {$2}, {$3};",
-            ";mma.sync.aligned.m16n8k32.row.col.s32.u4.u4.s32 {$0}, {$1}, {$2}, {$3};",
-            "prefix\\0Amma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32 {$0}, {$1}, {$2}, {$3};",
-            "@p mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32 {$0}, {$1}, {$2}, {$3};",
-            "@!%p\\09mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                contains_dense_int4_mma_features(spelling),
-                "missed {spelling:?}"
-            );
-        }
-
-        let representative = concat!(
-            "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32 ",
-            "{$0, $1, $2, $3}, {$4, $5, $6, $7}, {$8, $9}, {$10, $11, $12, $13};"
-        );
-        let requirements = detect_module_requirements_in_llvm_text(representative);
-        assert_eq!(
-            requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Ptx70,
-            }
-        );
-        assert_eq!(select_target(requirements.features).unwrap(), "sm_80");
-        assert_eq!(
-            required_ptx_feature("sm_75", requirements.ptx_isa).unwrap(),
-            Some("+ptx70")
-        );
-        assert_eq!(
-            required_ptx_feature("sm_80", requirements.ptx_isa).unwrap(),
-            None
-        );
-
-        let sm_75: CudaArch = "sm_75".parse().unwrap();
-        let sm_80: CudaArch = "sm_80".parse().unwrap();
-        assert!(validate_target_features(&sm_75, requirements.features).is_err());
-        assert!(validate_target_features(&sm_80, requirements.features).is_ok());
-        let error = resolve_ptx_target(
-            Some("sm_75"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            requirements.features,
-        )
-        .expect_err("sm_75 must not accept dense m16 INT4 MMA")
-        .to_string();
-        assert!(
-            error.contains("cannot lower detected feature Sm80"),
-            "{error}"
-        );
-
-        for target in [
-            "sm_80", "sm_86", "sm_89", "sm_90", "sm_90a", "sm_100", "sm_100a", "sm_120", "sm_120a",
-        ] {
-            assert!(
-                arch_satisfies(target, requirements.features),
-                "rejected {target}"
-            );
-        }
-
-        let m8_int4 = concat!(
-            "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32 ",
-            "{$0, $1}, {$4}, {$5}, {$2, $3};"
-        );
-        let mixed = format!("{representative}\n{m8_int4}");
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&mixed),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Sm75,
-                ptx_isa: PtxIsaRequirement::Ptx70,
-            }
-        );
-
-        let newer_ptx = format!("{representative}\nmovmatrix.sync.aligned.m8n8.trans.b16 $0, $1;");
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&newer_ptx),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-    }
-
-    #[test]
-    fn dense_int4_mma_detection_rejects_other_mma_families_and_near_misses() {
-        for near_miss in [
-            "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k16.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k64.row.col.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
-            "mma.sp.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "wmma.mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.col.row.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k64.row.row.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32.satfinite {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k64.row.col.s32.satfinite.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.satfiniteX.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.u32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.s32.s4.u8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32x {$0}, {$1}, {$2}, {$3};",
-            "not_mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "$mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "%mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "@mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "!mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            ")mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                !contains_dense_int4_mma_features(near_miss),
-                "matched {near_miss:?}"
-            );
-        }
-    }
-
-    #[test]
-    fn dense_b1_mma_detection_applies_exact_operation_floors() {
-        let cases = [
-            (
-                "m8n8k128",
-                "xor",
-                DetectedFeatures::Sm75,
-                PtxIsaRequirement::Ptx70,
-            ),
-            (
-                "m16n8k128",
-                "xor",
-                DetectedFeatures::Sm80,
-                PtxIsaRequirement::Ptx70,
-            ),
-            (
-                "m16n8k256",
-                "xor",
-                DetectedFeatures::Sm80,
-                PtxIsaRequirement::Ptx70,
-            ),
-            (
-                "m8n8k128",
-                "and",
-                DetectedFeatures::Sm80,
-                PtxIsaRequirement::Ptx71,
-            ),
-            (
-                "m16n8k128",
-                "and",
-                DetectedFeatures::Sm80,
-                PtxIsaRequirement::Ptx71,
-            ),
-            (
-                "m16n8k256",
-                "and",
-                DetectedFeatures::Sm80,
-                PtxIsaRequirement::Ptx71,
-            ),
-        ];
-
-        for (shape, operation, features, ptx_isa) in cases {
-            let spelling = format!(
-                "mma.sync.aligned.{shape}.row.col.s32.b1.b1.s32.{operation}.popc {{$0}}, {{$1}}, {{$2}}, {{$3}};"
-            );
-            assert_eq!(contains_b1_xor_mma_features(&spelling), operation == "xor");
-            assert_eq!(contains_b1_and_mma_features(&spelling), operation == "and");
-            assert_eq!(
-                contains_mma_m8n8k128_b1_xor_features(&spelling),
-                shape == "m8n8k128" && operation == "xor"
-            );
-            assert_eq!(
-                detect_module_requirements_in_llvm_text(&spelling),
-                ModuleRequirements { features, ptx_isa },
-                "{spelling}"
-            );
-        }
-
-        let m8_xor = concat!(
-            "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc ",
-            "{$0, $1}, {$4}, {$5}, {$2, $3};"
-        );
-        let m8_requirements = detect_module_requirements_in_llvm_text(m8_xor);
-        assert_eq!(select_target(m8_requirements.features).unwrap(), "sm_75");
-        assert_eq!(
-            required_ptx_feature("sm_75", m8_requirements.ptx_isa).unwrap(),
-            Some("+ptx70")
-        );
-
-        let m16_and = concat!(
-            "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc ",
-            "{$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};"
-        );
-        let and_requirements = detect_module_requirements_in_llvm_text(m16_and);
-        assert_eq!(select_target(and_requirements.features).unwrap(), "sm_80");
-        assert_eq!(
-            required_ptx_feature("sm_80", and_requirements.ptx_isa).unwrap(),
-            Some("+ptx71")
-        );
-        let sm_75: CudaArch = "sm_75".parse().unwrap();
-        let sm_80: CudaArch = "sm_80".parse().unwrap();
-        assert!(validate_target_features(&sm_75, and_requirements.features).is_err());
-        assert!(validate_target_features(&sm_80, and_requirements.features).is_ok());
-
-        let combined = format!("{m8_xor}\n{m16_and}");
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&combined),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Sm75,
-                ptx_isa: PtxIsaRequirement::Ptx71,
-            }
-        );
-    }
-
-    #[test]
-    fn dense_b1_mma_detection_rejects_other_families_and_near_misses() {
-        for near_miss in [
-            "wmma.mma.xor.popc.sync.aligned.row.col.m8n8k128.s32.b1.b1.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k64.row.col.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k128.col.row.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.or.popc {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.popc.xor {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popcx {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc.satfinite {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.u32.xor.popc {$0}, {$1}, {$2}, {$3};",
-            "not_mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
-            "$mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
-            "%mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                !contains_b1_xor_mma_features(near_miss),
-                "matched {near_miss:?}"
-            );
-            assert!(
-                !contains_b1_and_mma_features(near_miss),
-                "matched {near_miss:?}"
-            );
-        }
-    }
-
-    #[test]
-    fn generated_b1_floors_match_text_detection_on_both_backends() {
-        use crate::generated_intrinsic_targets::{
-            GeneratedIntrinsicBackend, generated_intrinsic_target_by_marker,
-        };
-
-        for (marker, mnemonic) in [
-            ("v1:i0157", B1_XOR_MMA_MNEMONICS[0]),
-            ("v1:i0158", B1_XOR_MMA_MNEMONICS[1]),
-            ("v1:i0159", B1_XOR_MMA_MNEMONICS[2]),
-            ("v1:i0160", B1_AND_MMA_MNEMONICS[0]),
-            ("v1:i0161", B1_AND_MMA_MNEMONICS[1]),
-            ("v1:i0162", B1_AND_MMA_MNEMONICS[2]),
-        ] {
-            let instruction = format!("{mnemonic} {{$0}}, {{$1}}, {{$2}}, {{$3}};");
-            let detected = detect_module_requirements_in_llvm_text(&instruction);
-            let target = generated_intrinsic_target_by_marker(marker).unwrap();
-            for backend in [
-                GeneratedIntrinsicBackend::LlvmNvptx,
-                GeneratedIntrinsicBackend::LibNvvm,
-            ] {
-                let generated =
-                    GeneratedModuleRequirements::from_targets(vec![target]).for_backend(backend);
-                assert_eq!(
-                    generated_ptx_isa_requirement(&generated).unwrap(),
-                    detected.ptx_isa,
-                    "{marker} {backend:?}"
-                );
-                for arch in ["sm_70", "sm_75", "sm_80", "sm_90"] {
-                    assert_eq!(
-                        generated_target_satisfied(arch, &generated),
-                        arch_satisfies(arch, detected.features),
-                        "{marker} {backend:?} {arch}"
-                    );
-                }
-            }
-        }
-    }
-
-    #[test]
-    fn m8n8k16_int8_mma_detection_applies_exact_sm75_and_ptx65_floors() {
-        let mut forms = 0;
-        for a_type in ["s8", "u8"] {
-            for b_type in ["s8", "u8"] {
-                for satfinite in [false, true] {
-                    let overflow = if satfinite { ".satfinite" } else { "" };
-                    let spelling = format!(
-                        "mma.sync.aligned.m8n8k16.row.col{overflow}.s32.{a_type}.{b_type}.s32 {{$0, $1}}, {{$2}}, {{$3}}, {{$4, $5}};"
-                    );
-                    assert!(
-                        contains_mma_m8n8k16_int8_features(&spelling),
-                        "missed {spelling:?}"
-                    );
-                    assert!(
-                        !contains_dense_int8_mma_features(&spelling),
-                        "m8 form entered the m16 detector: {spelling:?}"
-                    );
-                    assert_eq!(
-                        detect_module_requirements_in_llvm_text(&spelling),
-                        ModuleRequirements {
-                            features: DetectedFeatures::Sm75,
-                            ptx_isa: PtxIsaRequirement::Ptx65,
-                        },
-                        "{spelling}"
-                    );
-                    forms += 1;
-                }
-            }
-        }
-        assert_eq!(forms, 8);
-
-        for spelling in [
-            "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32\t{$0, $1}, {$2}, {$3}, {$4, $5};",
-            "mma.sync.aligned.m8n8k16.row.col.s32.u8.s8.s32\\09{$0, $1}, {$2}, {$3}, {$4, $5};",
-            ";mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "prefix\\0Amma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.u8.s32 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "@p mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "@!%p\\09mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32 {$0, $1}, {$2}, {$3}, {$4, $5};",
-        ] {
-            assert!(
-                contains_mma_m8n8k16_int8_features(spelling),
-                "missed {spelling:?}"
-            );
-        }
-
-        let representative = concat!(
-            "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32 ",
-            "{$0, $1}, {$4}, {$5}, {$2, $3};"
-        );
-        let requirements = detect_module_requirements_in_llvm_text(representative);
-        let (target, _) =
-            resolve_ptx_target(None, "CUDA_OXIDE_TARGET", None, requirements.features)
-                .expect("auto-resolve");
-        assert_eq!(target, "sm_75");
-        assert_eq!(
-            required_ptx_feature("sm_75", requirements.ptx_isa).unwrap(),
-            Some("+ptx65")
-        );
-        assert_eq!(
-            required_ptx_feature("sm_80", requirements.ptx_isa).unwrap(),
-            None
-        );
-
-        let sm_70: CudaArch = "sm_70".parse().unwrap();
-        let sm_75: CudaArch = "sm_75".parse().unwrap();
-        let sm_80: CudaArch = "sm_80".parse().unwrap();
-        assert!(validate_target_features(&sm_70, requirements.features).is_err());
-        assert!(validate_target_features(&sm_75, requirements.features).is_ok());
-        assert!(validate_target_features(&sm_80, requirements.features).is_ok());
-        let error = resolve_ptx_target(
-            Some("sm_70"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            requirements.features,
-        )
-        .expect_err("sm_70 must not accept m8n8k16 INT8 MMA")
-        .to_string();
-        assert!(
-            error.contains("cannot lower detected feature Sm75"),
-            "{error}"
-        );
-
-        for near_miss in [
-            "mma.sync.aligned.m8n8k8.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k16.col.row.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sp.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32x {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32.satfinite {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k16.row.col.satfiniteX.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s8.u32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k16.row.col.s32.s4.u8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k16.row.col.s32.u8.f16.s32 {$0}, {$1}, {$2}, {$3};",
-            "not_mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "$mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "%mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "@mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "!mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            ")mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                !contains_mma_m8n8k16_int8_features(near_miss),
-                "matched {near_miss:?}"
-            );
-        }
-
-        let m16 = concat!(
-            "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32 ",
-            "{$0, $1, $2, $3}, {$4, $5}, {$6}, {$7, $8, $9, $10};"
-        );
-        assert!(!contains_mma_m8n8k16_int8_features(m16));
-        assert!(contains_dense_int8_mma_features(m16));
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(m16),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Ptx70,
-            }
-        );
-
-        let combined = format!("{representative}\n{m16}");
-        let combined_requirements = detect_module_requirements_in_llvm_text(&combined);
-        assert_eq!(
-            combined_requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Sm75,
-                ptx_isa: PtxIsaRequirement::Ptx70,
-            }
-        );
-        let (target, _) = resolve_ptx_target(
-            None,
-            "CUDA_OXIDE_TARGET",
-            None,
-            combined_requirements.features,
-        )
-        .expect("combined m8 and m16 MMA should auto-resolve");
-        assert_eq!(target, "sm_80");
-    }
-
-    #[test]
-    fn m8n8k32_int4_mma_detection_applies_exact_sm75_and_ptx65_floors() {
-        let mut forms = 0;
-        for a_type in ["s4", "u4"] {
-            for b_type in ["s4", "u4"] {
-                for satfinite in [false, true] {
-                    let overflow = if satfinite { ".satfinite" } else { "" };
-                    let spelling = format!(
-                        "mma.sync.aligned.m8n8k32.row.col{overflow}.s32.{a_type}.{b_type}.s32 {{$0, $1}}, {{$4}}, {{$5}}, {{$2, $3}};"
-                    );
-                    assert!(
-                        contains_mma_m8n8k32_int4_features(&spelling),
-                        "missed {spelling:?}"
-                    );
-                    assert!(
-                        !contains_mma_m8n8k16_int8_features(&spelling),
-                        "INT4 form entered the m8n8k16 detector: {spelling:?}"
-                    );
-                    assert!(
-                        !contains_dense_int8_mma_features(&spelling),
-                        "INT4 form entered the dense INT8 detector: {spelling:?}"
-                    );
-                    assert_eq!(
-                        detect_module_requirements_in_llvm_text(&spelling),
-                        ModuleRequirements {
-                            features: DetectedFeatures::Sm75,
-                            ptx_isa: PtxIsaRequirement::Ptx65,
-                        },
-                        "{spelling}"
-                    );
-                    forms += 1;
-                }
-            }
-        }
-        assert_eq!(forms, 8);
-
-        for spelling in [
-            "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32\t{$0, $1}, {$4}, {$5}, {$2, $3};",
-            "mma.sync.aligned.m8n8k32.row.col.s32.u4.s4.s32\\09{$0, $1}, {$4}, {$5}, {$2, $3};",
-            ";mma.sync.aligned.m8n8k32.row.col.s32.u4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-            "prefix\\0Amma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-            "@p mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-            "@!%p\\09mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-        ] {
-            assert!(
-                contains_mma_m8n8k32_int4_features(spelling),
-                "missed {spelling:?}"
-            );
-        }
-
-        let representative = concat!(
-            "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32 ",
-            "{$0, $1}, {$4}, {$5}, {$2, $3};"
-        );
-        let requirements = detect_module_requirements_in_llvm_text(representative);
-        assert_eq!(
-            requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm75,
-                ptx_isa: PtxIsaRequirement::Ptx65,
-            }
-        );
-        assert_eq!(select_target(requirements.features).unwrap(), "sm_75");
-        assert_eq!(
-            required_ptx_feature("sm_75", requirements.ptx_isa).unwrap(),
-            Some("+ptx65")
-        );
-        assert_eq!(
-            required_ptx_feature("sm_80", requirements.ptx_isa).unwrap(),
-            None
-        );
-
-        let sm_72: CudaArch = "sm_72".parse().unwrap();
-        let sm_75: CudaArch = "sm_75".parse().unwrap();
-        let sm_80: CudaArch = "sm_80".parse().unwrap();
-        assert!(validate_target_features(&sm_72, requirements.features).is_err());
-        assert!(validate_target_features(&sm_75, requirements.features).is_ok());
-        assert!(validate_target_features(&sm_80, requirements.features).is_ok());
-        let error = resolve_ptx_target(
-            Some("sm_72"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            requirements.features,
-        )
-        .expect_err("sm_72 must not accept m8n8k32 INT4 MMA")
-        .to_string();
-        assert!(
-            error.contains("cannot lower detected feature Sm75"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn m8n8k32_int4_mma_detection_rejects_near_misses() {
-        for near_miss in [
-            "mma.sync.aligned.m8n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k32.row.col.s32.b1.b1.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sp.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k32.col.row.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k32.row.row.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32.satfinite {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k32.row.col.s32.satfinite.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k32.row.col.satfiniteX.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.s4.u32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k32.row.col.s32.s4.u8.s32 {$0}, {$1}, {$2}, {$3};",
-            "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32x {$0}, {$1}, {$2}, {$3};",
-            "not_mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "$mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "%mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "@mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            "!mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-            ")mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
-        ] {
-            assert!(
-                !contains_mma_m8n8k32_int4_features(near_miss),
-                "matched {near_miss:?}"
-            );
-        }
-    }
-
-    #[test]
-    fn m8n8k32_int4_mma_requirements_compose_and_are_forward_compatible() {
-        let int4 = concat!(
-            "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32 ",
-            "{$0, $1}, {$4}, {$5}, {$2, $3};"
-        );
-        let features = detect_features_in_llvm_text(int4);
-        for target in [
-            "sm_75", "sm_80", "sm_86", "sm_89", "sm_90", "sm_90a", "sm_100", "sm_100a", "sm_120",
-            "sm_120a",
-        ] {
-            assert!(arch_satisfies(target, features), "rejected {target}");
-        }
-        assert!(!arch_satisfies("sm_72", features));
-        assert_eq!(
-            resolve_ptx_target(None, "CUDA_OXIDE_TARGET", Some("sm_120"), features).unwrap(),
-            ("sm_120".to_string(), "detected GPU")
-        );
-
-        let m16_int8 = concat!(
-            "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 ",
-            "{$0, $1, $2, $3}, {$4, $5, $6, $7}, {$8, $9}, {$10, $11, $12, $13};"
-        );
-        let mixed = format!("{int4}\n{m16_int8}");
-        let mixed_requirements = detect_module_requirements_in_llvm_text(&mixed);
-        assert_eq!(
-            mixed_requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Sm75,
-                ptx_isa: PtxIsaRequirement::Ptx70,
-            }
-        );
-        assert_eq!(select_target(mixed_requirements.features).unwrap(), "sm_80");
-
-        let newer_ptx = format!("{int4}\nmovmatrix.sync.aligned.m8n8.trans.b16 $0, $1;");
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&newer_ptx),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm75 | DetectedFeatures::Movmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-    }
-
-    #[test]
-    fn mma_m8n8k4_f64_detection_enforces_sm80_and_ptx70() {
-        let mnemonic = concat!(
-            "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 ",
-            "{$0, $1}, {$2}, {$3}, {$4, $5};"
-        );
-        for spelling in [
-            mnemonic,
-            "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\t{$0, $1}, {$2}, {$3}, {$4, $5};",
-            "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\n{$0, $1}, {$2}, {$3}, {$4, $5};",
-            "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\\09{$0, $1}, {$2}, {$3}, {$4, $5};",
-            "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\\0A{$0, $1}, {$2}, {$3}, {$4, $5};",
-            ";mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "prefix\\0Amma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "\"mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "{mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "$L:mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "/* comment */mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "@p mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "@!%p\\09mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-        ] {
-            assert!(contains_mma_m8n8k4_f64_features(spelling), "{spelling:?}");
-        }
-
-        let requirements = detect_module_requirements_in_llvm_text(mnemonic);
-        assert_eq!(
-            requirements,
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Ptx70,
-            }
-        );
-        assert_eq!(select_target(requirements.features).unwrap(), "sm_80");
-
-        for near_miss in [
-            "mma.sync.aligned.m16n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "mma.sync.aligned.m8n8k4.col.row.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "mma.sync.aligned.m8n8k4.row.col.f32.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64x2 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\\5C09{$0, $1}, {$2}, {$3}, {$4, $5};",
-            "not_mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "$mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "%mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "@mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "!mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "@!mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "not$mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            "/mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-            ")mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
-        ] {
-            assert!(!contains_mma_m8n8k4_f64_features(near_miss));
-            assert_eq!(
-                detect_module_requirements_in_llvm_text(near_miss),
-                ModuleRequirements {
-                    features: DetectedFeatures::Basic,
-                    ptx_isa: PtxIsaRequirement::Default,
-                },
-                "matched near-miss {near_miss}"
-            );
-        }
-
-        let sm_75: CudaArch = "sm_75".parse().unwrap();
-        let sm_80: CudaArch = "sm_80".parse().unwrap();
-        assert!(validate_target_features(&sm_75, requirements.features).is_err());
-        assert!(validate_target_features(&sm_80, requirements.features).is_ok());
-        let error = resolve_ptx_target(
-            Some("sm_75"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            requirements.features,
-        )
-        .expect_err("sm_75 must not accept FP64 tensor-core MMA")
-        .to_string();
-        assert!(
-            error.contains("cannot lower detected feature Sm80"),
-            "{error}"
-        );
-
-        let combined = format!("{mnemonic}\nmovmatrix.sync.aligned.m8n8.trans.b16 $0, $1;");
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&combined),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-    }
-
-    #[test]
-    fn test_movmatrix_detection_separates_sm75_from_the_ptx78_floor() {
-        let mnemonic = "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;";
-        for spelling in [
-            mnemonic,
-            "movmatrix.sync.aligned.m8n8.trans.b16\t$0, $1;",
-            "movmatrix.sync.aligned.m8n8.trans.b16\n$0, $1;",
-            "movmatrix.sync.aligned.m8n8.trans.b16\\09$0, $1;",
-            "movmatrix.sync.aligned.m8n8.trans.b16\\0A$0, $1;",
-            "movmatrix.sync.aligned.m8n8.trans.b16\\0D\\0A$0, $1;",
-        ] {
-            assert!(contains_movmatrix_features(spelling), "{spelling:?}");
-        }
-        assert_eq!(
-            detect_features_in_llvm_text(mnemonic),
-            DetectedFeatures::Movmatrix
-        );
-        assert_eq!(select_target(DetectedFeatures::Movmatrix).unwrap(), "sm_75");
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(mnemonic).ptx_isa,
-            PtxIsaRequirement::Ptx78
-        );
-
-        for near_miss in [
-            "movmatrix.sync.aligned.m8n8.b16 $0, $1;",
-            "movmatrix.sync.aligned.m16n8.trans.b16 $0, $1;",
-            "movmatrix.sync.aligned.m8n8.trans.b32 $0, $1;",
-            "movmatrix.sync.aligned.m8n8.trans.b16x2 $0, $1;",
-            "movmatrix.sync.aligned.m8n8.trans.b16\\5C09$0, $1;",
-        ] {
-            assert!(
-                !contains_movmatrix_features(near_miss),
-                "matched {near_miss}"
-            );
-            assert_eq!(
-                detect_module_requirements_in_llvm_text(near_miss),
-                ModuleRequirements {
-                    features: DetectedFeatures::Basic,
-                    ptx_isa: PtxIsaRequirement::Default,
-                }
-            );
-        }
-
-        let combined = format!("{mnemonic}\ncp.async.ca.shared.global [$0], [$1], 4;");
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&combined),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            },
-            "the architecture and PTX ISA floors must compose independently"
-        );
-
-        let sm_70: CudaArch = "sm_70".parse().unwrap();
-        let sm_75: CudaArch = "sm_75".parse().unwrap();
-        let sm_80: CudaArch = "sm_80".parse().unwrap();
-        assert!(validate_target_features(&sm_70, DetectedFeatures::Movmatrix).is_err());
-        assert!(validate_target_features(&sm_75, DetectedFeatures::Movmatrix).is_ok());
-        assert!(validate_target_features(&sm_80, DetectedFeatures::Movmatrix).is_ok());
-
-        for target in ["sm_75", "sm_80", "sm_86", "sm_87"] {
-            assert_eq!(
-                required_ptx_feature(target, PtxIsaRequirement::Ptx78).unwrap(),
-                Some("+ptx78"),
-                "{target} needs an explicit PTX 7.8 floor"
-            );
-        }
-        assert_eq!(
-            required_ptx_feature("sm_90", PtxIsaRequirement::Ptx78).unwrap(),
-            None
-        );
-        for target in ["sm_88", "sm_89"] {
-            assert_eq!(
-                required_ptx_feature(target, PtxIsaRequirement::Ptx78).unwrap(),
-                None,
-                "{target} already requires PTX 7.8 or newer"
-            );
-        }
-        assert_eq!(
-            required_ptx_feature("sm_75", PtxIsaRequirement::Default).unwrap(),
-            None
-        );
-    }
-
-    #[test]
-    fn matrix_memory_detection_composes_architecture_and_ptx_isa_floors() {
-        let base_ldmatrix = "ldmatrix.sync.aligned.m8n8.x4.b16 {$0, $1, $2, $3}, [$4];";
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(base_ldmatrix),
-            ModuleRequirements {
-                features: DetectedFeatures::Ldmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx65,
-            }
-        );
-
-        let cta_ldmatrix = "ldmatrix.sync.aligned.m8n8.x1.shared::cta.b16 {$0}, [$1];";
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(cta_ldmatrix),
-            ModuleRequirements {
-                features: DetectedFeatures::Ldmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-
-        for stmatrix in [
-            "stmatrix.sync.aligned.m8n8.x1.b16 [$0], {$1};",
-            "stmatrix.sync.aligned.m8n8.x4.trans.shared::cta.b16 [$0], {$1, $2, $3, $4};",
-        ] {
-            assert_eq!(
-                detect_module_requirements_in_llvm_text(stmatrix),
-                ModuleRequirements {
-                    features: DetectedFeatures::Sm90,
-                    ptx_isa: PtxIsaRequirement::Ptx78,
-                }
-            );
-        }
-
-        for newer in [
-            "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {$0, $1}, [$2];",
-            "ldmatrix.sync.aligned.m8n16.x2.shared::cta.b8x16.b6x16_p32 {$0, $1}, [$2];",
-            "stmatrix.sync.aligned.m16n8.x1.trans.shared.b8 [$0], {$1};",
-        ] {
-            assert_eq!(
-                detect_module_requirements_in_llvm_text(newer),
-                ModuleRequirements {
-                    features: DetectedFeatures::MatrixBlackwell
-                        | if newer.starts_with("ldmatrix") {
-                            DetectedFeatures::Ldmatrix
-                        } else {
-                            DetectedFeatures::Sm90
-                        },
-                    ptx_isa: PtxIsaRequirement::Ptx86,
-                },
-                "{newer}"
-            );
-        }
-
-        let mixed = format!(
-            "{base_ldmatrix}\n{}",
-            "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;"
-        );
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(&mixed),
-            ModuleRequirements {
-                features: DetectedFeatures::Movmatrix | DetectedFeatures::Ldmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            },
-            "the strongest PTX ISA floor must survive equal sm_75 feature families"
-        );
-
-        assert_eq!(
-            required_ptx_feature("sm_75", PtxIsaRequirement::Ptx65).unwrap(),
-            Some("+ptx65")
-        );
-        assert_eq!(
-            required_ptx_feature("sm_80", PtxIsaRequirement::Ptx65).unwrap(),
-            None
-        );
-        assert_eq!(
-            required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx86).unwrap(),
-            None
-        );
-
-        let adjacent_unrelated_b8 = concat!(
-            "ldmatrix.sync.aligned.m8n8.x1.shared.b16 {$0}, [$1]; ",
-            "mov.b8 $2, $3;"
-        );
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(adjacent_unrelated_b8),
-            ModuleRequirements {
-                features: DetectedFeatures::Ldmatrix,
-                ptx_isa: PtxIsaRequirement::Ptx65,
-            },
-            "an unrelated b8 instruction must not raise the ldmatrix family"
-        );
-    }
-
-    #[test]
-    fn tma_and_wgmma_raise_their_independent_ptx_floors() {
-        for tma in [
-            "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes;",
-            "cp.async.bulk.commit_group;",
-            "cp.async.bulk.wait_group 0;",
-            "cp.async.bulk.wait_group.read 0;",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(tma);
-            assert!(
-                requirements.features.contains(DetectedFeatures::Tma),
-                "{tma}"
-            );
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx80, "{tma}");
-        }
-
-        let non_bulk = "cp.async.commit_group;";
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(non_bulk),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm80,
-                ptx_isa: PtxIsaRequirement::Default,
-            }
-        );
-
-        let tma_and_movmatrix = concat!(
-            "cp.async.bulk.commit_group; ",
-            "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;"
-        );
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(tma_and_movmatrix).ptx_isa,
-            PtxIsaRequirement::Ptx80
-        );
-
-        let wgmma = "wgmma.fence.sync.aligned;";
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(wgmma),
-            ModuleRequirements {
-                features: DetectedFeatures::Wgmma,
-                ptx_isa: PtxIsaRequirement::Ptx80,
-            }
-        );
-
-        let shared_cta =
-            "cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes;";
-        assert!(contains_tma_shared_cta_destination(shared_cta));
-        let shared_cta_requirements = detect_module_requirements_in_llvm_text(shared_cta);
-        assert_eq!(shared_cta_requirements.features, DetectedFeatures::Tma);
-        assert_eq!(shared_cta_requirements.ptx_isa, PtxIsaRequirement::Ptx86);
-
-        let shared_source = "cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group;";
-        assert!(!contains_tma_shared_cta_destination(shared_source));
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(shared_source).ptx_isa,
-            PtxIsaRequirement::Ptx80
-        );
-
-        let cta_group = "cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1;";
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(cta_group).ptx_isa,
-            PtxIsaRequirement::Ptx86
-        );
-
-        assert_eq!(
-            required_ptx_feature("sm_90", PtxIsaRequirement::Ptx80).unwrap(),
-            Some("+ptx80")
-        );
-        assert_eq!(
-            required_ptx_feature("sm_90a", PtxIsaRequirement::Ptx86).unwrap(),
-            Some("+ptx86")
-        );
-        assert_eq!(
-            required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx80).unwrap(),
-            None
-        );
-    }
-
-    #[test]
-    fn related_cluster_mbarrier_and_clc_requirements_are_detected() {
-        for ptx in [
-            "mbarrier.arrive.release.cluster.shared::cluster.b64 _, [$0];",
-            "fence.mbarrier_init.release.cluster;",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(ptx);
-            assert!(
-                requirements.features.contains(DetectedFeatures::Tma),
-                "{ptx}"
-            );
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx80, "{ptx}");
-            assert!(arch_satisfies("sm_90", requirements.features));
-        }
-
-        for (ptx, expected_isa) in [
-            (
-                "mbarrier.init.shared.b64 [$0], 1;",
-                PtxIsaRequirement::Ptx70,
-            ),
-            (
-                "mbarrier.test_wait.parity.shared.b64 $0, [$1], $2;",
-                PtxIsaRequirement::Ptx71,
-            ),
-            (
-                "mbarrier.try_wait.parity.shared::cta.b64 $0, [$1], $2;",
-                PtxIsaRequirement::Ptx78,
-            ),
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(ptx);
-            assert!(
-                requirements.features.contains(DetectedFeatures::Sm80),
-                "{ptx}"
-            );
-            assert_eq!(requirements.ptx_isa, expected_isa, "{ptx}");
-            if ptx.contains("try_wait") {
-                assert!(requirements.features.contains(DetectedFeatures::Tma));
-                assert!(!arch_satisfies("sm_80", requirements.features));
-            } else {
-                assert!(arch_satisfies("sm_80", requirements.features));
-                assert!(!arch_satisfies("sm_75", requirements.features));
-            }
-        }
-
-        for ptx in [
-            "redux.sync.add.u32 $0, $1, $2;",
-            "cvt.rn.bf16x2.f32 $0, $1, $2;",
-            "cvt.rn.relu.bf16x2.f32 $0, $1, $2;",
-            "cvt.rz.bf16x2.f32 $0, $1, $2;",
-        ] {
-            assert!(
-                detect_features_in_llvm_text(ptx).contains(DetectedFeatures::Sm80),
-                "{ptx}"
-            );
-        }
-        assert_eq!(
-            required_ptx_feature("sm_80", PtxIsaRequirement::Ptx70).unwrap(),
-            None
-        );
-        assert_eq!(
-            required_ptx_feature("sm_80", PtxIsaRequirement::Ptx71).unwrap(),
-            Some("+ptx71")
-        );
-        for target in ["sm_86", "sm_87", "sm_88", "sm_89"] {
-            assert_eq!(
-                required_ptx_feature(target, PtxIsaRequirement::Ptx71).unwrap(),
-                None,
-                "{target} cannot be downgraded below its minimum PTX ISA"
-            );
-        }
-
-        for ptx in [
-            "mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 $0, [$1], $2;",
-            "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
-            "fence.acquire.sync_restrict::shared::cluster.cluster;",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(ptx);
-            assert!(
-                requirements.features.contains(DetectedFeatures::Tma),
-                "{ptx}"
-            );
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86, "{ptx}");
-            assert!(!arch_satisfies("sm_80", requirements.features));
-        }
-
-        for ptx in [
-            "mbarrier.test_wait.acquire.cta.shared::cta.b64 $0, [$1], $2;",
-            "mbarrier.arrive.release.cta.shared::cta.b64 $0, [$1];",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(ptx);
-            assert!(requirements.features.contains(DetectedFeatures::Tma));
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx80);
-            assert!(!arch_satisfies("sm_80", requirements.features));
-        }
-
-        let cluster_sync = "barrier.cluster.arrive.aligned; barrier.cluster.wait.aligned;";
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(cluster_sync),
-            ModuleRequirements {
-                features: DetectedFeatures::Cluster,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-        assert_eq!(select_target(DetectedFeatures::Cluster).unwrap(), "sm_90");
-
-        let cluster_release = "barrier.cluster.arrive.release;";
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(cluster_release).ptx_isa,
-            PtxIsaRequirement::Ptx80
-        );
-
-        for ptx in [
-            "fence.sc.cluster;",
-            "fence.acq_rel.cluster;",
-            "ld.shared::cluster.u32 $0, [$1];",
-            "ld.acquire.cluster.global.u32 $0, [$1];",
-            "getctarank.shared::cluster.u32 $0, $1;",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(ptx);
-            assert!(requirements.features.contains(DetectedFeatures::Cluster));
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx78);
-            assert!(!arch_satisfies("sm_80", requirements.features));
-        }
-
-        for ptx in [
-            "fence.acquire.cta;",
-            "fence.release.gpu;",
-            "fence.acquire.cluster;",
-            "fence.release.sys;",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(ptx);
-            assert!(
-                requirements.features.contains(DetectedFeatures::Sm90),
-                "{ptx}"
-            );
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86, "{ptx}");
-            assert_eq!(
-                requirements.features.contains(DetectedFeatures::Cluster),
-                ptx.contains(".cluster"),
-                "{ptx}"
-            );
-            assert!(!arch_satisfies("sm_80", requirements.features));
-        }
-
-        let multimem = "multimem.red.relaxed.cluster.global.add.u32 [$0], $1;";
-        let requirements = detect_module_requirements_in_llvm_text(multimem);
-        assert_eq!(requirements.features, DetectedFeatures::Sm90);
-        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86);
-        assert_eq!(select_target(requirements.features).unwrap(), "sm_90");
-        let multimem_debug_filename = r#"!9 = !DIFile(filename: "multimem.rs", directory: "/tmp")"#;
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(multimem_debug_filename),
-            ModuleRequirements {
-                features: DetectedFeatures::Basic,
-                ptx_isa: PtxIsaRequirement::Default,
-            }
-        );
-
-        for multimem in [
-            "multimem.ld_reduce.relaxed.cta.add.v4.e4m3 {$0, $1, $2, $3}, [$4];",
-            "multimem.st.relaxed.gpu.e5m2 [$0], $1;",
-            "multimem.ld_reduce.add.acc::f16.v4.e5m2 {$0, $1, $2, $3}, [$4];",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(multimem);
-            assert_eq!(
-                requirements.features,
-                DetectedFeatures::MultimemFp8 | DetectedFeatures::Sm90,
-                "{multimem}"
-            );
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86, "{multimem}");
-            assert_eq!(select_target(requirements.features).unwrap(), "sm_100a");
-            for target in [
-                "sm_100a", "sm_103a", "sm_110a", "sm_120a", "sm_121a", "sm_100f", "sm_103f",
-                "sm_110f",
-            ] {
-                assert!(arch_satisfies(target, requirements.features), "{target}");
-            }
-            for target in ["sm_100", "sm_90a", "sm_120f", "sm_121f"] {
-                assert!(!arch_satisfies(target, requirements.features), "{target}");
-            }
-        }
-
-        let redux_f32 = "redux.sync.min.abs.NaN.f32 $0, $1, $2;";
-        let requirements = detect_module_requirements_in_llvm_text(redux_f32);
-        assert_eq!(
-            requirements.features,
-            DetectedFeatures::ReduxF32 | DetectedFeatures::Sm80
-        );
-        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86);
-        assert_eq!(select_target(requirements.features).unwrap(), "sm_100a");
-        for target in ["sm_100a", "sm_103a", "sm_100f", "sm_103f"] {
-            assert!(arch_satisfies(target, requirements.features), "{target}");
-        }
-        for target in ["sm_100", "sm_110a", "sm_120a", "sm_121f"] {
-            assert!(!arch_satisfies(target, requirements.features), "{target}");
-        }
-
-        for sreg in [
-            "mov.u32 $0, %clusterid.x;",
-            "mov.u32 $0, %nclusterid.z;",
-            "mov.u32 $0, %cluster_ctarank;",
-            "mov.u32 $0, %cluster_nctarank;",
-            "mov.pred $0, %is_explicit_cluster;",
-        ] {
-            assert_eq!(
-                detect_module_requirements_in_llvm_text(sreg),
-                ModuleRequirements {
-                    features: DetectedFeatures::Cluster,
-                    ptx_isa: PtxIsaRequirement::Ptx78,
-                },
-                "{sreg}"
-            );
-        }
-
-        let cluster_metadata = r#"!0 = !{!"cluster_dim_x", i32 2}
-            !1 = !{!"cluster_dim_y", i32 1}
-            !2 = !{!"cluster_dim_z", i32 1}"#;
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(cluster_metadata),
-            ModuleRequirements {
-                features: DetectedFeatures::Cluster,
-                ptx_isa: PtxIsaRequirement::Ptx78,
-            }
-        );
-        let cluster_debug_local =
-            r#"!8 = !DILocalVariable(name: "cluster_dim_x", scope: !1, file: !2, line: 3)"#;
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(cluster_debug_local),
-            ModuleRequirements {
-                features: DetectedFeatures::Basic,
-                ptx_isa: PtxIsaRequirement::Default,
-            }
-        );
-
-        let elect = "elect.sync $0|p, $1;";
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(elect),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm90,
-                ptx_isa: PtxIsaRequirement::Ptx80,
-            }
-        );
-
-        let tcgen_wait = "tcgen05.wait::ld.sync.aligned;";
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(tcgen_wait),
-            ModuleRequirements {
-                features: DetectedFeatures::Blackwell,
-                ptx_isa: PtxIsaRequirement::Ptx86,
-            }
-        );
-
-        let tcgen_debug_filename = r#"!7 = !DIFile(filename: "tcgen05.rs", directory: "/tmp")"#;
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(tcgen_debug_filename),
-            ModuleRequirements {
-                features: DetectedFeatures::Basic,
-                ptx_isa: PtxIsaRequirement::Default,
-            }
-        );
-
-        let clc = "clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 $0, $1;";
-        assert_eq!(
-            detect_module_requirements_in_llvm_text(clc),
-            ModuleRequirements {
-                features: DetectedFeatures::Sm100,
-                ptx_isa: PtxIsaRequirement::Ptx86,
-            }
-        );
-        assert_eq!(select_target(DetectedFeatures::Sm100).unwrap(), "sm_100");
-        assert!(!arch_satisfies("sm_90", DetectedFeatures::Sm100));
-        assert!(arch_satisfies("sm_120", DetectedFeatures::Sm100));
-
-        let clc_multicast = "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 [$0], [$1];";
-        let requirements = detect_module_requirements_in_llvm_text(clc_multicast);
-        assert_eq!(
-            requirements.features,
-            DetectedFeatures::Sm100 | DetectedFeatures::BlackwellFamily
-        );
-        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86);
-        assert_eq!(select_target(requirements.features).unwrap(), "sm_100a");
-        assert!(!arch_satisfies("sm_100", requirements.features));
-        assert!(arch_satisfies("sm_120a", requirements.features));
-        for arch in ["sm_100f", "sm_101f", "sm_110f", "sm_121f"] {
-            assert!(arch_satisfies(arch, requirements.features), "{arch}");
-        }
-        for arch in ["sm_103a", "sm_121a"] {
-            assert!(!arch_satisfies(arch, requirements.features), "{arch}");
-        }
-    }
-
-    #[test]
-    fn ptx86_tma_modes_enforce_their_architecture_families() {
-        for ptx in [
-            "cp.async.bulk.global.shared::cta.bulk_group.cp_mask [$0], [$1], 16, $2;",
-            "cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes;",
-            "cp.async.bulk.tensor.3d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes;",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(ptx);
-            assert!(
-                requirements.features.contains(DetectedFeatures::Tma),
-                "{ptx}"
-            );
-            assert!(
-                requirements.features.contains(DetectedFeatures::Sm100),
-                "{ptx}"
-            );
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86, "{ptx}");
-            assert!(!arch_satisfies("sm_90", requirements.features));
-            assert!(arch_satisfies("sm_100", requirements.features));
-        }
-
-        for ptx in [
-            "cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes;",
-            "cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group;",
-            "cp.async.bulk.tensor.3d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes;",
-            "cp.async.bulk.prefetch.tensor.3d.L2.global.im2col::w::128;",
-        ] {
-            let requirements = detect_module_requirements_in_llvm_text(ptx);
-            assert!(
-                requirements.features.contains(DetectedFeatures::Tma),
-                "{ptx}"
-            );
-            assert!(
-                requirements
-                    .features
-                    .contains(DetectedFeatures::BlackwellAccelerated),
-                "{ptx}"
-            );
-            assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86, "{ptx}");
-            assert_eq!(select_target(requirements.features).unwrap(), "sm_100a");
-            assert!(!arch_satisfies("sm_100", requirements.features));
-            assert!(!arch_satisfies("sm_120a", requirements.features));
-            assert!(arch_satisfies("sm_103f", requirements.features));
-        }
-
-        assert!(!contains_tma_sm100_features("custom.op.cp_mask $0;"));
-        assert!(!contains_tma_blackwell_accelerated_features(
-            "custom.tile::scatter4 $0;"
-        ));
-    }
-
-    #[test]
-    fn test_sm90_floor_wins_when_sm80_features_are_also_present() {
-        let llvm = r#"
-            call i32 asm pure "add.rn.bf16x2 $0, $1, $2;", "=r,r,r"(i32 %a, i32 %b)
-            call void asm sideeffect "cp.async.ca.shared.global [%0], [%1], 4;", "l,l"()
-        "#;
-
-        assert!(contains_sm90_features(llvm));
-        assert!(contains_sm80_features(llvm));
-        assert_eq!(
-            detect_features_in_llvm_text(llvm),
-            DetectedFeatures::Sm90 | DetectedFeatures::Sm80
-        );
-    }
-
-    #[test]
-    fn test_tma_multicast_detection_requires_cta_mask() {
-        let multicast = "call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile(i32 0, i1 1, i1 false)";
-        let unicast = "call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile(i32 0, i1 0, i1 false)";
-        let literal_multicast = "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster";
-        let cg1 = "cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1";
-        let cg2 = "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2";
-        let cg1_intrinsic = "call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d(ptr addrspace(7) %dst, i1 0, i1 false, i32 1)";
-        let cg2_intrinsic = "call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d(ptr addrspace(7) %dst, i1 1, i1 false, i32 2)";
-        let unrelated_i32 = "call void @unrelated(i32 2)";
-
-        assert!(contains_tma_multicast(multicast));
-        assert!(contains_tma_multicast(literal_multicast));
-        assert!(!contains_tma_multicast(unicast));
-        assert_eq!(
-            detect_features_in_llvm_text(multicast),
-            DetectedFeatures::TmaMulticast | DetectedFeatures::Tma
-        );
-        assert_eq!(
-            detect_features_in_llvm_text(literal_multicast),
-            DetectedFeatures::TmaMulticast | DetectedFeatures::Tma | DetectedFeatures::Cluster
-        );
-        assert_eq!(detect_features_in_llvm_text(unicast), DetectedFeatures::Tma);
-        assert_eq!(
-            detect_features_in_llvm_text(cg1),
-            DetectedFeatures::TmaCtaGroup | DetectedFeatures::Tma
-        );
-        assert_eq!(
-            detect_features_in_llvm_text(cg1_intrinsic),
-            DetectedFeatures::TmaCtaGroup | DetectedFeatures::Tma
-        );
-        assert_eq!(
-            detect_features_in_llvm_text(cg2),
-            DetectedFeatures::TmaCtaGroup
-                | DetectedFeatures::TmaMulticast
-                | DetectedFeatures::Tma
-                | DetectedFeatures::Cluster
-        );
-        assert_eq!(
-            detect_features_in_llvm_text(cg2_intrinsic),
-            DetectedFeatures::TmaCtaGroup | DetectedFeatures::TmaMulticast | DetectedFeatures::Tma
-        );
-        assert!(!contains_tma_cta_group_features(unrelated_i32));
-    }
-
-    #[test]
-    fn test_select_target_prefers_required_architecture() {
-        for (features, expected) in [
-            (DetectedFeatures::Blackwell, "sm_100a"),
-            (DetectedFeatures::TmaCtaGroup, "sm_100a"),
-            (DetectedFeatures::BlackwellAccelerated, "sm_100a"),
-            (DetectedFeatures::BlackwellFamily, "sm_100a"),
-            (DetectedFeatures::ReduxF32, "sm_100a"),
-            (DetectedFeatures::MultimemFp8, "sm_100a"),
-            (DetectedFeatures::TmaMulticast, "sm_100a"),
-            (DetectedFeatures::MatrixBlackwell, "sm_100a"),
-            (DetectedFeatures::Wgmma, "sm_90a"),
-            (DetectedFeatures::Sm100, "sm_100"),
-            (DetectedFeatures::Tma, "sm_100"),
-            (DetectedFeatures::Cluster, "sm_90"),
-            (DetectedFeatures::Sm90, "sm_90"),
-            (DetectedFeatures::Sm80, "sm_80"),
-            (DetectedFeatures::Movmatrix, "sm_75"),
-            (DetectedFeatures::Ldmatrix, "sm_75"),
-            (DetectedFeatures::Basic, "sm_80"),
-        ] {
-            assert_eq!(select_target(features).unwrap(), expected, "{features:?}");
-        }
-    }
-
-    #[test]
-    fn target_selection_enforces_feature_intersections() {
-        let multicast = "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster";
-        let hopper_pair = format!("{multicast};\nwgmma.fence.sync.aligned;");
-        let hopper_requirements = detect_features_in_llvm_text(&hopper_pair);
-        assert!(hopper_requirements.contains(DetectedFeatures::TmaMulticast));
-        assert!(hopper_requirements.contains(DetectedFeatures::Wgmma));
-        assert_eq!(select_target(hopper_requirements).unwrap(), "sm_90a");
-        assert!(arch_satisfies("sm_90a", hopper_requirements));
-        assert!(!arch_satisfies("sm_100a", hopper_requirements));
-
-        let blackwell_pair = format!(
-            "{multicast};\n{}",
-            "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {$0, $1}, [$2];"
-        );
-        let blackwell_requirements = detect_features_in_llvm_text(&blackwell_pair);
-        assert!(blackwell_requirements.contains(DetectedFeatures::TmaMulticast));
-        assert!(blackwell_requirements.contains(DetectedFeatures::MatrixBlackwell));
-        assert_eq!(select_target(blackwell_requirements).unwrap(), "sm_100a");
-        assert!(arch_satisfies("sm_100a", blackwell_requirements));
-        assert!(!arch_satisfies("sm_90a", blackwell_requirements));
-
-        let impossible = DetectedFeatures::Wgmma | DetectedFeatures::MatrixBlackwell;
-        let error = select_target(impossible).expect_err("families have no common target");
-        assert!(error.contains("do not share a compatible GPU architecture"));
-        assert!(resolve_ptx_target(Some("sm_90a"), "CUDA_OXIDE_TARGET", None, impossible).is_err());
-        assert!(
-            resolve_ptx_target(Some("sm_100a"), "CUDA_OXIDE_TARGET", None, impossible).is_err()
-        );
-    }
-
-    #[test]
-    fn rejected_explicit_targets_name_the_source_that_chose_them() {
-        let parse_failure = resolve_ptx_target(
-            Some("not-a-target"),
-            "PipelineConfig::target_arch",
-            None,
-            DetectedFeatures::Sm80,
-        )
-        .unwrap_err()
-        .to_string();
-        assert!(
-            parse_failure.contains("invalid CUDA target `not-a-target`"),
-            "{parse_failure}"
-        );
-        assert!(
-            parse_failure.contains("(target from PipelineConfig::target_arch)"),
-            "{parse_failure}"
-        );
-        assert_eq!(
-            parse_failure.matches("invalid CUDA target").count(),
-            1,
-            "parse errors must not double-wrap the parser's own prefix: {parse_failure}"
-        );
-
-        let floor_rejection = resolve_ptx_target(
-            Some("sm_75"),
-            "CUDA_OXIDE_TARGET",
-            None,
-            DetectedFeatures::Sm80,
-        )
-        .unwrap_err()
-        .to_string();
-        assert!(
-            floor_rejection.contains("cannot lower detected feature Sm80"),
-            "{floor_rejection}"
-        );
-        assert!(
-            floor_rejection.contains("(target from CUDA_OXIDE_TARGET)"),
-            "{floor_rejection}"
-        );
-    }
-
-    #[test]
-    fn test_arch_major_parses_cuda_spelling() {
-        assert_eq!(arch_compute_capability("sm_75"), Some(75));
-        assert_eq!(arch_compute_capability("sm_100a"), Some(100));
-        assert_eq!(arch_major("sm_75"), Some(7));
-        assert_eq!(arch_major("sm_80"), Some(8));
-        assert_eq!(arch_major("sm_90a"), Some(9));
-        assert_eq!(arch_major("sm_100a"), Some(10));
-        assert_eq!(arch_major("sm_103a"), Some(10));
-        assert_eq!(arch_major("sm_120a"), Some(12));
-        assert_eq!(arch_major("nvvm-ir"), None);
-        assert_eq!(arch_major("sm_"), None);
-    }
-
-    #[test]
-    fn ptx9_targets_require_an_llvm22_backend() {
-        for target in ["sm_88", "sm_110", "sm_110a", "sm_110f"] {
-            assert!(
-                validate_target_for_llvm_major(target, Some(21)).is_err(),
-                "{target}"
-            );
-            assert!(
-                validate_target_for_llvm_major(target, None).is_err(),
-                "{target}"
-            );
-            assert!(
-                validate_target_for_llvm_major(target, Some(22)).is_ok(),
-                "{target}"
-            );
-            assert!(
-                validate_target_for_llvm_major(target, Some(23)).is_ok(),
-                "{target}"
-            );
-        }
-        for target in ["sm_87", "sm_103a", "sm_120a", "sm_121f"] {
-            assert!(
-                validate_target_for_llvm_major(target, Some(21)).is_ok(),
-                "{target}"
-            );
-        }
-        for target in ["sm_999a", "not-a-target", "compute_88"] {
-            assert!(
-                validate_target_for_llvm_major(target, Some(21)).is_ok(),
-                "unknown or non-sm target {target} must remain owned by other validators"
-            );
-        }
-        for (target, floor) in [
-            ("sm_90a", 80),
-            ("sm_100a", 86),
-            ("sm_100f", 88),
-            ("sm_120a", 87),
-            ("sm_120f", 88),
-            ("sm_121a", 88),
-        ] {
-            assert_eq!(recorded_ptx_floor(&target.parse().unwrap()), Ok(floor));
-        }
-    }
-
-    #[test]
-    fn test_arch_satisfies_sm100_only_features() {
-        // tcgen05 and explicit cta_group TMA are datacenter-Blackwell only:
-        // consumer Blackwell (sm_120) and Hopper (sm_90) cannot run them, even
-        // though 120 > 100. This is the gemm_sol regression guard.
-        for f in [DetectedFeatures::Blackwell, DetectedFeatures::TmaCtaGroup] {
-            assert!(arch_satisfies("sm_100a", f), "sm_100a must satisfy {f:?}");
-            assert!(arch_satisfies("sm_103a", f), "sm_103a must satisfy {f:?}");
-            assert!(arch_satisfies("sm_103f", f), "sm_103f must satisfy {f:?}");
-            assert!(
-                !arch_satisfies("sm_100", f),
-                "generic sm_100 must NOT satisfy {f:?}"
-            );
-            assert!(
-                !arch_satisfies("sm_120a", f),
-                "sm_120a must NOT satisfy {f:?}"
-            );
-            assert!(
-                !arch_satisfies("sm_90a", f),
-                "sm_90a must NOT satisfy {f:?}"
-            );
-            assert!(
-                !arch_satisfies("sm_102a", f),
-                "unknown architecture-specific targets must not be accepted"
-            );
-            assert!(
-                !arch_satisfies("sm_102f", f),
-                "unknown family-specific targets must not be accepted"
-            );
-        }
-    }
-
-    #[test]
-    fn test_arch_satisfies_base_tma_multicast_targets() {
-        for arch in [
-            "sm_90", "sm_90a", "sm_100", "sm_100a", "sm_103f", "sm_110a", "sm_120", "sm_120a",
-        ] {
-            assert!(
-                arch_satisfies(arch, DetectedFeatures::TmaMulticast),
-                "{arch}"
-            );
-        }
-        for arch in ["sm_80", "sm_89", "sm_102a", "sm_102f"] {
-            assert!(
-                !arch_satisfies(arch, DetectedFeatures::TmaMulticast),
-                "{arch}"
-            );
-        }
-    }
-
-    #[test]
-    fn test_arch_satisfies_wgmma_is_hopper_only() {
-        assert!(arch_satisfies("sm_90a", DetectedFeatures::Wgmma));
-        assert!(!arch_satisfies("sm_90", DetectedFeatures::Wgmma));
-        assert!(!arch_satisfies("sm_100a", DetectedFeatures::Wgmma));
-        assert!(!arch_satisfies("sm_120a", DetectedFeatures::Wgmma));
-    }
-
-    #[test]
-    fn test_arch_satisfies_blackwell_matrix_family_targets() {
-        for arch in [
-            "sm_100a", "sm_103a", "sm_110a", "sm_120a", "sm_121a", "sm_100f", "sm_103f", "sm_110f",
-            "sm_120f", "sm_121f",
-        ] {
-            assert!(
-                arch_satisfies(arch, DetectedFeatures::MatrixBlackwell),
-                "{arch}"
-            );
-        }
-        for arch in [
-            "sm_100a", "sm_101a", "sm_110a", "sm_120a", "sm_100f", "sm_101f", "sm_103f", "sm_110f",
-            "sm_120f", "sm_121f",
-        ] {
-            assert!(
-                arch_satisfies(arch, DetectedFeatures::BlackwellFamily),
-                "{arch}"
-            );
-        }
-        for arch in ["sm_101a", "sm_101f"] {
-            assert!(!arch_satisfies(arch, DetectedFeatures::MatrixBlackwell));
-        }
-        for arch in ["sm_103a", "sm_121a"] {
-            assert!(!arch_satisfies(arch, DetectedFeatures::BlackwellFamily));
-        }
-        for arch in [
-            "sm_100a", "sm_101a", "sm_103a", "sm_110a", "sm_100f", "sm_103f", "sm_110f",
-        ] {
-            assert!(
-                arch_satisfies(arch, DetectedFeatures::BlackwellAccelerated),
-                "{arch}"
-            );
-        }
-        for arch in ["sm_100", "sm_120a", "sm_120f", "sm_102f"] {
-            assert!(
-                !arch_satisfies(arch, DetectedFeatures::BlackwellAccelerated),
-                "{arch}"
-            );
-        }
-        for arch in ["sm_100", "sm_103", "sm_110", "sm_120", "sm_121a"] {
-            assert!(arch_satisfies(arch, DetectedFeatures::Sm100), "{arch}");
-        }
-        for arch in ["sm_90a", "sm_102", "sm_102a"] {
-            assert!(!arch_satisfies(arch, DetectedFeatures::Sm100), "{arch}");
-        }
-        for arch in ["sm_90a", "sm_100", "sm_102f", "sm_120"] {
-            assert!(
-                !arch_satisfies(arch, DetectedFeatures::MatrixBlackwell),
-                "{arch}"
-            );
-            assert!(
-                !arch_satisfies(arch, DetectedFeatures::BlackwellFamily),
-                "{arch}"
-            );
-        }
-    }
-
-    #[test]
-    fn test_arch_satisfies_forward_compatible_features() {
-        // Plain TMA / cluster / sm_90-floor instructions lower on any sm_90+
-        // device, sm_80-floor instructions on any sm_80+ device, movmatrix and
-        // base ldmatrix on sm_75+, and basic kernels on Volta+.
-        // So a consumer sm_120 GPU is a valid target for these (it runs locally
-        // instead of being downgraded to the feature floor).
-        for arch in ["sm_90a", "sm_100a", "sm_120a"] {
-            assert!(arch_satisfies(arch, DetectedFeatures::Tma));
-            assert!(arch_satisfies(arch, DetectedFeatures::Cluster));
-            assert!(arch_satisfies(arch, DetectedFeatures::Sm90));
-            assert!(arch_satisfies(arch, DetectedFeatures::Sm80));
-            assert!(arch_satisfies(arch, DetectedFeatures::Movmatrix));
-            assert!(arch_satisfies(arch, DetectedFeatures::Ldmatrix));
-            assert!(arch_satisfies(arch, DetectedFeatures::Basic));
-        }
-        assert!(arch_satisfies("sm_80", DetectedFeatures::Sm80));
-        assert!(!arch_satisfies("sm_75", DetectedFeatures::Sm80));
-        assert!(arch_satisfies("sm_75", DetectedFeatures::Movmatrix));
-        assert!(arch_satisfies("sm_80", DetectedFeatures::Movmatrix));
-        assert!(!arch_satisfies("sm_70", DetectedFeatures::Movmatrix));
-        assert!(arch_satisfies("sm_75", DetectedFeatures::Ldmatrix));
-        assert!(!arch_satisfies("sm_70", DetectedFeatures::Ldmatrix));
-        assert!(arch_satisfies("sm_80", DetectedFeatures::Basic));
-        assert!(arch_satisfies("sm_75", DetectedFeatures::Basic));
-        assert!(arch_satisfies("sm_70", DetectedFeatures::Basic));
-        assert!(!arch_satisfies("sm_80", DetectedFeatures::Tma));
-        assert!(!arch_satisfies("sm_80", DetectedFeatures::Sm90));
-        assert!(!arch_satisfies("sm_80a", DetectedFeatures::Basic));
-        assert!(!arch_satisfies("sm_90f", DetectedFeatures::Tma));
-    }
-
-    #[test]
-    fn resolve_ptx_target_threads_a_caller_supplied_source_label() {
-        let (target, source) = resolve_ptx_target(
-            Some("sm_80"),
-            "the requested Target",
-            None,
-            DetectedFeatures::Basic,
-        )
-        .unwrap();
-        assert_eq!(target, "sm_80");
-        assert_eq!(source, "the requested Target");
-    }
-
-    #[test]
-    fn resolve_ptx_target_failure_does_not_assume_an_env_var_source() {
-        let error = resolve_ptx_target(
-            Some("sm_75"),
-            "the requested Target",
-            None,
-            DetectedFeatures::Wgmma,
-        )
-        .unwrap_err();
-        assert!(matches!(error, PipelineError::TargetSelection { .. }));
-        assert!(
-            !error.to_string().contains("CUDA_OXIDE_TARGET"),
-            "a standalone caller that never set CUDA_OXIDE_TARGET should not see it blamed: {error}"
-        );
-
-        let parse_error = resolve_ptx_target(
-            Some("not-a-target"),
-            "the requested Target",
-            None,
-            DetectedFeatures::Basic,
-        )
-        .unwrap_err();
-        assert!(matches!(parse_error, PipelineError::TargetSelection { .. }));
-        assert!(
-            !parse_error.to_string().contains("CUDA_OXIDE_TARGET"),
-            "{parse_error}"
-        );
-    }
-}
diff --git a/crates/cuda-oxide-codegen/src/target/arch.rs b/crates/cuda-oxide-codegen/src/target/arch.rs
new file mode 100644
index 0000000000..8d63993301
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/arch.rs
@@ -0,0 +1,156 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::features::DetectedFeatures;
+use cuda_target_spec::recorded_ptx_floor;
+use libnvvm_sys::CudaArch;
+
+/// Does `arch` (e.g. `"sm_120a"`, `"sm_90"`) support the kernel's detected
+/// features?
+///
+/// tcgen05/TMEM and explicit `cta_group` TMA forms exist only in the sm_100
+/// datacenter-Blackwell family: consumer Blackwell (sm_120) and Hopper (sm_90)
+/// lack them, so an sm_120 GPU cannot run an sm_100 tcgen05 kernel even though
+/// 120 > 100. WGMMA is Hopper-only. The remaining features are forward
+/// compatible from their floor (TMA / cluster / sm_90 features need sm_90+,
+/// sm_80 features need sm_80+, sm_75 features need sm_75+, and basic needs
+/// sm_70+).
+///
+/// Used to decide whether the GPU in this machine (the `CUDA_OXIDE_DEVICE_ARCH`
+/// hint) can actually run the kernel, or whether we must build for the arch the
+/// IR requires instead.
+pub fn arch_satisfies(arch: &str, features: DetectedFeatures) -> bool {
+    let Some((capability, suffix)) = arch_compute_capability_and_suffix(arch) else {
+        return false;
+    };
+    if !is_known_cuda_target(capability, suffix) {
+        return false;
+    }
+    features
+        .iter()
+        .all(|feature| arch_satisfies_feature(capability, suffix, feature))
+}
+
+pub(super) fn arch_satisfies_feature(
+    capability: u32,
+    suffix: Option<char>,
+    feature: DetectedFeatures,
+) -> bool {
+    let major = capability / 10;
+    match feature {
+        DetectedFeatures::Blackwell | DetectedFeatures::TmaCtaGroup => {
+            supports_tcgen_target(capability, suffix)
+        }
+        DetectedFeatures::BlackwellAccelerated => {
+            supports_blackwell_accelerated_target(capability, suffix)
+        }
+        DetectedFeatures::BlackwellFamily => supports_blackwell_family_target(capability, suffix),
+        DetectedFeatures::MatrixBlackwell => supports_blackwell_matrix_target(capability, suffix),
+        DetectedFeatures::ReduxF32 => supports_redux_f32_target(capability, suffix),
+        DetectedFeatures::MultimemFp8 => supports_multimem_fp8_target(capability, suffix),
+        // The PTX ISA requires only sm_90+. The suffixed targets are advised
+        // for performance, so target selection still prefers sm_100a.
+        DetectedFeatures::TmaMulticast => major >= 9,
+        DetectedFeatures::Wgmma => capability == 90 && suffix == Some('a'),
+        DetectedFeatures::Sm100 => is_known_blackwell_capability(capability),
+        DetectedFeatures::Tma | DetectedFeatures::Cluster | DetectedFeatures::Sm90 => major >= 9,
+        DetectedFeatures::Sm80 => major >= 8,
+        DetectedFeatures::Sm75 | DetectedFeatures::Movmatrix | DetectedFeatures::Ldmatrix => {
+            capability >= 75
+        }
+        DetectedFeatures::DynamicStack => capability >= 52,
+        // Basic kernels are supported on the project's Volta+ floor. The
+        // cross-compilation default remains sm_80, but a detected sm_70/sm_75
+        // GPU is a valid and more useful target for `cargo oxide run`.
+        DetectedFeatures::Basic => major >= 7,
+        // `iter` only yields the single-bit constants above.
+        _ => false,
+    }
+}
+
+/// tcgen05/TMEM exists only on the datacenter Blackwell architecture or
+/// family targets. Consumer sm_120 and generic targets without an `a`/`f`
+/// suffix do not provide Tensor Memory.
+fn supports_tcgen_target(capability: u32, suffix: Option<char>) -> bool {
+    match suffix {
+        // Architecture-specific targets are exact, not numerically forward
+        // compatible. `sm_101a` is the PTX 8.x spelling later renamed to
+        // `sm_110a`; accept both spellings plus the distinct sm_103 target.
+        Some('a') => matches!(capability, 100 | 101 | 103 | 110),
+        Some('f') => matches!(capability, 100 | 101 | 103 | 110),
+        _ => false,
+    }
+}
+
+fn supports_blackwell_accelerated_target(capability: u32, suffix: Option<char>) -> bool {
+    match suffix {
+        Some('a') => matches!(capability, 100 | 101 | 103 | 110),
+        Some('f') => matches!(capability, 100 | 101 | 103 | 110),
+        _ => false,
+    }
+}
+
+fn supports_blackwell_family_target(capability: u32, suffix: Option<char>) -> bool {
+    match suffix {
+        Some('a') => matches!(capability, 100 | 101 | 110 | 120),
+        Some('f') => matches!(capability, 100 | 101 | 103 | 110 | 120 | 121),
+        _ => false,
+    }
+}
+
+fn supports_blackwell_matrix_target(capability: u32, suffix: Option<char>) -> bool {
+    // LLVM's sm_101 aliases stop selecting these instructions at PTX 9.0.
+    match suffix {
+        Some('a' | 'f') => matches!(capability, 100 | 103 | 110 | 120 | 121),
+        _ => false,
+    }
+}
+
+/// Floating-point `redux.sync` is scoped to the sm_100/sm_103 family.
+fn supports_redux_f32_target(capability: u32, suffix: Option<char>) -> bool {
+    matches!(suffix, Some('a' | 'f')) && matches!(capability, 100 | 103)
+}
+
+/// FP8 / f16-accumulator multimem forms span several Blackwell architecture
+/// targets, but consumer family (`f`) targets do not support the sm_120 line.
+fn supports_multimem_fp8_target(capability: u32, suffix: Option<char>) -> bool {
+    match suffix {
+        Some('a') => matches!(capability, 100 | 101 | 103 | 110 | 120 | 121),
+        Some('f') => matches!(capability, 100 | 101 | 103 | 110),
+        _ => false,
+    }
+}
+
+fn is_known_blackwell_capability(capability: u32) -> bool {
+    matches!(capability, 100 | 101 | 103 | 110 | 120 | 121)
+}
+
+pub(super) fn is_known_cuda_target(capability: u32, suffix: Option<char>) -> bool {
+    CudaArch::new(capability, suffix).is_ok_and(|arch| recorded_ptx_floor(&arch).is_ok())
+}
+
+/// Extract the compute-capability *major* version from an `sm_…` target string.
+///
+/// CUDA concatenates major+minor without a separator, so `"sm_120a"` is cc 12.0
+/// (major 12), `"sm_90"` is cc 9.0, `"sm_103a"` is cc 10.3. We read the digit
+/// run after `sm_` and divide by ten. Returns `None` when there are no digits.
+#[cfg(test)]
+pub(super) fn arch_major(arch: &str) -> Option<u32> {
+    arch_compute_capability(arch).map(|capability| capability / 10)
+}
+
+/// Extract the numeric compute capability from an `sm_…` target.
+#[cfg(test)]
+pub(super) fn arch_compute_capability(arch: &str) -> Option<u32> {
+    arch_compute_capability_and_suffix(arch).map(|(capability, _)| capability)
+}
+
+pub(super) fn arch_compute_capability_and_suffix(arch: &str) -> Option<(u32, Option<char>)> {
+    if !arch.starts_with("sm_") {
+        return None;
+    }
+    let target = arch.parse::<CudaArch>().ok()?;
+    Some((target.capability(), target.suffix()))
+}
diff --git a/crates/cuda-oxide-codegen/src/target/detect.rs b/crates/cuda-oxide-codegen/src/target/detect.rs
new file mode 100644
index 0000000000..1f1d963578
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/detect.rs
@@ -0,0 +1,895 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::features::{DetectedFeatures, ModuleRequirements, PtxIsaRequirement};
+use crate::error::PipelineError;
+use std::path::Path;
+
+pub(super) fn contains_wgmma_features(contents: &str) -> bool {
+    contents.contains("wgmma.fence")
+        || contents.contains("wgmma.commit_group")
+        || contents.contains("wgmma.wait_group")
+        || contents.contains("wgmma.mma_async")
+}
+
+/// Checks for Thread Block Cluster instructions (sm_90+).
+///
+/// Cluster features require Hopper (sm_90) or newer:
+/// - Cluster special registers (%cluster_ctaid, %cluster_nctaid)
+/// - Cluster synchronization (cluster.sync)
+/// - Distributed shared memory (mapa.shared::cluster)
+pub(super) fn contains_cluster_features(contents: &str) -> bool {
+    // Cluster special registers
+    contents.contains("cluster_ctaid")
+        || contents.contains("cluster_nctaid")
+        || contents.contains("cluster_ctarank")
+        || contents.contains("cluster_nctarank")
+        || contents.contains("%clusterid")
+        || contents.contains("%nclusterid")
+        || contents.contains("%is_explicit_cluster")
+        || contents.contains("!\"cluster_dim_x\"")
+        || contents.contains("!\"cluster_dim_y\"")
+        || contents.contains("!\"cluster_dim_z\"")
+        // Cluster synchronization
+        || contents.contains("cluster.sync")
+        || contents.contains("barrier.cluster.")
+        // Distributed shared memory
+        || contents.contains("mapa.shared::cluster")
+        || contents.contains(".shared::cluster")
+        || contains_cluster_fence_features(contents)
+        || contains_cluster_scoped_memory_features(contents)
+}
+
+fn contains_cluster_fence_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        statement.contains("fence.sc.cluster")
+            || statement.contains("fence.acq_rel.cluster")
+            || statement.contains("fence.acquire.cluster")
+            || statement.contains("fence.release.cluster")
+    })
+}
+
+fn contains_cluster_scoped_memory_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        !statement.contains("multimem.")
+            && statement.contains(".cluster.")
+            && ["ld.", "st.", "atom.", "red."]
+                .iter()
+                .any(|mnemonic| statement.contains(mnemonic))
+    })
+}
+
+/// Checks the one-way fence semantics added in PTX 8.6.
+///
+/// Unlike the older `.sc` / `.acq_rel` forms, `.acquire` and `.release`
+/// require sm_90 for every scope, not just `.cluster`.
+fn contains_fence_acquire_release_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        statement.contains("fence.acquire.") || statement.contains("fence.release.")
+    })
+}
+
+/// Checks the multimem instruction family introduced for sm_90.
+///
+/// Base forms need PTX 8.1. The pipeline currently has no 8.1 feature switch,
+/// so PTX 8.6 is the nearest conservative version supported by LLVM.
+fn contains_multimem_features(contents: &str) -> bool {
+    contents.split(';').any(is_multimem_instruction)
+}
+
+fn is_multimem_instruction(statement: &str) -> bool {
+    ["multimem.ld_reduce", "multimem.st", "multimem.red"]
+        .iter()
+        .any(|instruction| statement.contains(instruction))
+}
+
+/// Checks PTX 8.6 multimem formats that require a Blackwell family target.
+fn contains_multimem_blackwell_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        is_multimem_instruction(statement)
+            && [".e4m3", ".e5m2", ".acc::f16"]
+                .iter()
+                .any(|qualifier| statement.contains(qualifier))
+    })
+}
+
+/// Checks the PTX 8.6 floating-point extension to `redux.sync`.
+fn contains_redux_f32_features(contents: &str) -> bool {
+    contents
+        .split(';')
+        .any(|statement| statement.contains("redux.sync") && statement.contains(".f32"))
+}
+
+/// Checks for forward-compatible instructions whose minimum target is sm_90.
+///
+/// Keep this category architecture-neutral: unlike WGMMA, these instructions
+/// are not Hopper-specific and remain available on newer architectures.
+pub(super) fn contains_sm90_features(contents: &str) -> bool {
+    ["add.rn.bf16x2", "sub.rn.bf16x2", "mul.rn.bf16x2"]
+        .iter()
+        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
+        || contains_packed_bf16_atomic_features(contents)
+        || contains_stmatrix_features(contents)
+        || contains_elect_features(contents)
+        || contains_fence_acquire_release_features(contents)
+        || contains_multimem_features(contents)
+}
+
+/// Native two-lane f32 arithmetic requires PTX 8.6 and sm_100+.
+///
+/// Match the instruction family rather than cuda-oxide's currently emitted
+/// spelling. External LLVM IR can contain any valid rounding/FTZ modifier
+/// combination and must receive the same target floor.
+pub(super) fn contains_f32x2_features(contents: &str) -> bool {
+    contains_instruction_family_modifier(contents, &["add", "sub", "mul", "fma"], "f32x2")
+}
+
+/// Native packed bf16 atomic add was added in PTX 7.8 for sm_90.
+pub(super) fn contains_packed_bf16_atomic_features(contents: &str) -> bool {
+    contains_instruction_mnemonic(contents, "atom.global.add.noftz.bf16x2")
+}
+
+/// Packed f16 atomic add needs PTX 6.2. Its hardware floor predates
+/// cuda-oxide's Volta floor, so only the independent PTX ISA requirement must
+/// be raised.
+pub(super) fn contains_packed_f16_atomic_features(contents: &str) -> bool {
+    contains_instruction_mnemonic(contents, "atom.global.add.noftz.f16x2")
+}
+
+fn contains_elect_features(contents: &str) -> bool {
+    contents.contains("elect.sync")
+}
+
+/// Checks for the register-only 8x8 matrix transpose (PTX 7.8, sm_75+).
+pub(super) fn contains_movmatrix_features(contents: &str) -> bool {
+    contains_instruction_mnemonic(contents, "movmatrix.sync.aligned.m8n8.trans.b16")
+}
+
+/// Checks the dense BF16 MMA form added by the typed device intrinsic.
+///
+/// MMA shapes and types have different architecture and PTX ISA floors, so
+/// this intentionally matches the complete operation-specific mnemonic.
+pub(super) fn contains_mma_m16n8k16_f32_bf16_features(contents: &str) -> bool {
+    contains_instruction_mnemonic(
+        contents,
+        "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32",
+    )
+}
+
+/// Checks for the Ampere TF32 MMA operation (PTX 7.0, sm_80+).
+pub(super) fn contains_mma_m16n8k8_f32_tf32_features(contents: &str) -> bool {
+    contains_instruction_mnemonic(
+        contents,
+        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32",
+    )
+}
+
+/// Checks the dense Ampere INT8 MMA forms (PTX 7.0, sm_80+).
+pub(super) fn contains_dense_int8_mma_features(contents: &str) -> bool {
+    const MNEMONICS: &[&str] = &[
+        "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32",
+        "mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32",
+        "mma.sync.aligned.m16n8k16.row.col.s32.u8.s8.s32",
+        "mma.sync.aligned.m16n8k16.row.col.s32.u8.u8.s32",
+        "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.s8.s32",
+        "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32",
+        "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.s8.s32",
+        "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.u8.s32",
+        "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32",
+        "mma.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32",
+        "mma.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32",
+        "mma.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32",
+    ];
+
+    MNEMONICS
+        .iter()
+        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
+}
+
+/// Checks the m8n8k16 INT8 MMA forms (PTX 6.5, sm_75+).
+pub(super) fn contains_mma_m8n8k16_int8_features(contents: &str) -> bool {
+    const MNEMONICS: &[&str] = &[
+        "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32",
+        "mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32",
+        "mma.sync.aligned.m8n8k16.row.col.s32.u8.s8.s32",
+        "mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32",
+        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s8.s32",
+        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32",
+        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32",
+        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.u8.s32",
+    ];
+
+    MNEMONICS
+        .iter()
+        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
+}
+
+/// Checks the m8n8k32 INT4 MMA forms (PTX 6.5, sm_75+).
+pub(super) fn contains_mma_m8n8k32_int4_features(contents: &str) -> bool {
+    const MNEMONICS: &[&str] = &[
+        "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32",
+        "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32",
+        "mma.sync.aligned.m8n8k32.row.col.s32.u4.s4.s32",
+        "mma.sync.aligned.m8n8k32.row.col.s32.u4.u4.s32",
+        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.s4.s32",
+        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32",
+        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32",
+        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32",
+    ];
+
+    MNEMONICS
+        .iter()
+        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
+}
+
+/// Checks the dense Ampere INT4 MMA forms (PTX 7.0, sm_80+).
+pub(super) fn contains_dense_int4_mma_features(contents: &str) -> bool {
+    const MNEMONICS: &[&str] = &[
+        "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32",
+        "mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32",
+        "mma.sync.aligned.m16n8k32.row.col.s32.u4.s4.s32",
+        "mma.sync.aligned.m16n8k32.row.col.s32.u4.u4.s32",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.s4.s32",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.u4.s32",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.u4.s32",
+        "mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32",
+        "mma.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32",
+        "mma.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32",
+        "mma.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32",
+        "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32",
+        "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32",
+        "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32",
+        "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32",
+    ];
+
+    MNEMONICS
+        .iter()
+        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
+}
+
+pub(super) const B1_XOR_MMA_MNEMONICS: &[&str] = &[
+    "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc",
+    "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc",
+    "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc",
+];
+
+pub(super) const B1_AND_MMA_MNEMONICS: &[&str] = &[
+    "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc",
+    "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc",
+    "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc",
+];
+
+/// Checks the three dense binary XOR/POPC MMA forms (PTX 7.0).
+pub(super) fn contains_b1_xor_mma_features(contents: &str) -> bool {
+    B1_XOR_MMA_MNEMONICS
+        .iter()
+        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
+}
+
+/// Checks the three dense binary AND/POPC MMA forms (PTX 7.1, sm_80+).
+pub(super) fn contains_b1_and_mma_features(contents: &str) -> bool {
+    B1_AND_MMA_MNEMONICS
+        .iter()
+        .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
+}
+
+/// Checks the only dense binary MMA form that can run below sm_80.
+pub(super) fn contains_mma_m8n8k128_b1_xor_features(contents: &str) -> bool {
+    contains_instruction_mnemonic(contents, B1_XOR_MMA_MNEMONICS[0])
+}
+
+fn contains_sm80_b1_mma_features(contents: &str) -> bool {
+    contains_b1_and_mma_features(contents)
+        || B1_XOR_MMA_MNEMONICS[1..]
+            .iter()
+            .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
+}
+
+/// Checks for the Ampere FP64 tensor-core MMA operation (PTX 7.0, sm_80+).
+pub(super) fn contains_mma_m8n8k4_f64_features(contents: &str) -> bool {
+    contains_instruction_mnemonic(contents, "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64")
+}
+
+/// Checks the dense F16 MMA form added by the typed device intrinsic.
+///
+/// MMA shapes and types have different architecture and PTX ISA floors, so
+/// this intentionally matches the complete operation-specific mnemonic.
+pub(super) fn contains_mma_m16n8k16_f32_f16_features(contents: &str) -> bool {
+    contains_instruction_mnemonic(
+        contents,
+        "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32",
+    )
+}
+
+fn contains_instruction_mnemonic(contents: &str, mnemonic: &str) -> bool {
+    contents.match_indices(mnemonic).any(|(index, _)| {
+        let preceding = &contents[..index];
+        let following = &contents[index + mnemonic.len()..];
+        let escapes = ["\\09", "\\0A", "\\0B", "\\0C", "\\0D"];
+        // Use PTX token delimiters rather than treating arbitrary punctuation
+        // as a boundary. In particular, `$` and `%` participate in PTX
+        // identifiers, and guarded opcodes have whitespace after `@{!}p`.
+        let begins_at_instruction_boundary = preceding.is_empty()
+            || preceding
+                .chars()
+                .next_back()
+                .is_some_and(|ch| ch.is_whitespace() || matches!(ch, '"' | ';' | ':' | '{' | '}'))
+            || escapes.iter().any(|escape| preceding.ends_with(escape))
+            || preceding.ends_with("*/");
+        let ends_at_instruction_boundary =
+            following.chars().next().is_some_and(char::is_whitespace)
+                || escapes.iter().any(|escape| following.starts_with(escape));
+        begins_at_instruction_boundary && ends_at_instruction_boundary
+    })
+}
+
+fn contains_instruction_family_modifier(
+    contents: &str,
+    operations: &[&str],
+    required_modifier: &str,
+) -> bool {
+    const ESCAPED_WHITESPACE: [&str; 5] = ["\\09", "\\0A", "\\0B", "\\0C", "\\0D"];
+    operations.iter().any(|operation| {
+        contents.match_indices(operation).any(|(index, _)| {
+            let preceding = &contents[..index];
+            let following = &contents[index + operation.len()..];
+            let begins_at_instruction_boundary = preceding.is_empty()
+                || preceding.chars().next_back().is_some_and(|ch| {
+                    ch.is_whitespace() || matches!(ch, '"' | ';' | ':' | '{' | '}')
+                })
+                || ESCAPED_WHITESPACE
+                    .iter()
+                    .any(|escape| preceding.ends_with(escape))
+                || preceding.ends_with("*/");
+            if !begins_at_instruction_boundary || !following.starts_with('.') {
+                return false;
+            }
+
+            let token_end = following
+                .char_indices()
+                .find_map(|(offset, ch)| {
+                    (ch.is_whitespace() || matches!(ch, '"' | ';')).then_some(offset)
+                })
+                .into_iter()
+                .chain(
+                    ESCAPED_WHITESPACE
+                        .iter()
+                        .filter_map(|escape| following.find(escape)),
+                )
+                .min()
+                .unwrap_or(following.len());
+            following[..token_end]
+                .split('.')
+                .any(|modifier| modifier == required_modifier)
+        })
+    })
+}
+
+/// Checks the full PTX instruction families, including inline `ptx_asm!`
+/// forms that cuda-oxide does not yet expose as typed wrappers.
+///
+/// Broad family matching is intentional. Missing a valid spelling can
+/// silently select an architecture or PTX ISA that is too old; an invalid
+/// spelling still reaches ptxas and fails there after conservative targeting.
+fn contains_ldmatrix_features(contents: &str) -> bool {
+    contents.contains("ldmatrix.sync.aligned.")
+}
+
+fn contains_stmatrix_features(contents: &str) -> bool {
+    contents.contains("stmatrix.sync.aligned.")
+}
+
+/// PTX 8.6 matrix shapes/types have a Blackwell architecture-family floor.
+fn contains_blackwell_matrix_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        let newer_ldmatrix = statement.contains("ldmatrix.sync.aligned.")
+            && [".m16n16.", ".m8n16.", ".b8", ".src_fmt", ".dst_fmt"]
+                .iter()
+                .any(|token| statement.contains(token));
+        let newer_stmatrix = statement.contains("stmatrix.sync.aligned.")
+            && [".m16n8.", ".b8"]
+                .iter()
+                .any(|token| statement.contains(token));
+        newer_ldmatrix || newer_stmatrix
+    })
+}
+
+fn contains_ldmatrix_cta_state_space(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        statement.contains("ldmatrix.sync.aligned.") && statement.contains(".shared::cta.")
+    })
+}
+
+/// Checks for features whose minimum target is sm_80.
+///
+/// This category includes packed bf16 operations introduced on Ampere and
+/// non-bulk asynchronous copies. Match both the PTX spellings used in inline
+/// assembly and the dotted LLVM NVVM intrinsic names for `cp.async`. Bulk and
+/// tensor-copy forms have stronger requirements and are classified first.
+pub(super) fn contains_sm80_features(contents: &str) -> bool {
+    [
+        "fma.rn.bf16x2",
+        "fma.rn.relu.bf16x2",
+        "min.bf16x2",
+        "max.bf16x2",
+        "neg.bf16x2",
+        "abs.bf16x2",
+    ]
+    .iter()
+    .any(|mnemonic| contains_instruction_mnemonic(contents, mnemonic))
+        || contains_mma_m8n8k4_f64_features(contents)
+        || contents
+            .split(';')
+            .any(|statement| statement.contains("cvt.") && statement.contains(".bf16x2.f32"))
+        || contains_mbarrier_features(contents)
+        || contents.contains("redux.sync")
+        || contents.contains("cp.async.ca.shared")
+        || contents.contains("cp.async.cg.shared")
+        || contents.contains("cp.async.commit_group")
+        || contents.contains("cp.async.commit.group")
+        || contents.contains("cp.async.wait_group")
+        || contents.contains("cp.async.wait.group")
+        || contents.contains("cp.async.wait_all")
+        || contents.contains("cp.async.wait.all")
+        || contains_mma_m16n8k16_f32_bf16_features(contents)
+        || contains_mma_m16n8k16_f32_f16_features(contents)
+        || contains_mma_m16n8k8_f32_tf32_features(contents)
+        || contains_dense_int8_mma_features(contents)
+        || contains_dense_int4_mma_features(contents)
+        || contains_sm80_b1_mma_features(contents)
+}
+
+/// Checks for TMA/mbarrier instructions (Hopper+ compatible with Blackwell).
+///
+/// These instructions work on BOTH Hopper and Blackwell:
+/// - TMA: Tensor Memory Accelerator bulk copies
+/// - mbarrier: Async hardware barriers with transaction tracking
+///
+/// The architecture floor is generic sm_90; automatic cross-compilation keeps
+/// the existing sm_100 default for forward-compatible Blackwell PTX.
+pub(super) fn contains_tma_features(contents: &str) -> bool {
+    // TMA tensor copies and their commit/wait group controls.
+    contains_cp_async_bulk_features(contents)
+        || contains_mbarrier_sm90_features(contents)
+        || contents.contains("fence.mbarrier_init")
+        // Proxy fence for async operations
+        || contents.contains("fence.proxy.async")
+        || contents.contains(".sync_restrict")
+}
+
+fn contains_cp_async_bulk_features(contents: &str) -> bool {
+    contents.contains("cp.async.bulk.")
+}
+
+fn contains_mbarrier_features(contents: &str) -> bool {
+    contents.contains("mbarrier.") || contents.contains("llvm.nvvm.mbarrier")
+}
+
+fn contains_mbarrier_sm90_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        (statement.contains("mbarrier.") || statement.contains("llvm.nvvm.mbarrier"))
+            && [
+                "try_wait",
+                "expect_tx",
+                "complete_tx",
+                "shared::cluster",
+                ".acquire.",
+                ".release.",
+                ".relaxed",
+            ]
+            .iter()
+            .any(|feature| statement.contains(feature))
+    })
+}
+
+fn contains_mbarrier_ptx71_features(contents: &str) -> bool {
+    contents
+        .split(';')
+        .any(|statement| statement.contains("mbarrier.test_wait") && statement.contains(".parity"))
+}
+
+fn contains_mbarrier_ptx78_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        statement.contains("mbarrier.")
+            && (statement.contains("try_wait") || statement.contains("shared::cta"))
+    })
+}
+
+fn contains_mbarrier_ptx80_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        statement.contains("mbarrier.")
+            && [
+                "expect_tx",
+                "complete_tx",
+                "shared::cluster",
+                ".acquire.",
+                ".release.",
+            ]
+            .iter()
+            .any(|feature| statement.contains(feature))
+    })
+}
+
+/// Checks for Blackwell tcgen05 instructions (sm_100a+).
+///
+/// These instructions require a datacenter-Blackwell `a`/`f` target; consumer
+/// sm_120 does not provide Tensor Memory:
+/// - tcgen05: Tensor Core Gen 5 (TMEM allocation, MMA, sync primitives)
+///
+/// Key differences from Hopper:
+/// - tcgen05 MMA is single-thread (vs WGMMA's 128 threads)
+/// - Uses Tensor Memory (TMEM) instead of registers
+/// - Different synchronization model (mbarrier-based)
+pub(super) fn contains_blackwell_features(contents: &str) -> bool {
+    // Keep the instruction-family match broad enough for inline PTX and LLVM
+    // intrinsic names, but do not treat debug filenames such as `tcgen05.rs`
+    // as an instruction.
+    [
+        "tcgen05.alloc",
+        "tcgen05.dealloc",
+        "tcgen05.relinquish_alloc_permit",
+        "tcgen05.fence",
+        "tcgen05.commit",
+        "tcgen05.mma",
+        "tcgen05.cp",
+        "tcgen05.shift",
+        "tcgen05.ld",
+        "tcgen05.st",
+        "tcgen05.wait",
+    ]
+    .iter()
+    .any(|instruction| contents.contains(instruction))
+}
+
+/// Checks for base TMA multicast in LLVM IR or inline PTX.
+///
+/// TMA multicast (`cp.async.bulk.tensor...multicast::cluster`) is an optional
+/// qualifier that broadcasts a tile to all CTAs in a cluster. It is legal on
+/// sm_90+, although NVIDIA advises an `a`/`f` target
+/// for performance. In the LLVM intrinsic this is controlled by the trailing
+/// `use_cta_mask` i1 argument being set to true.
+pub(super) fn contains_tma_multicast(contents: &str) -> bool {
+    contents.lines().any(|line| {
+        line.contains("g2s.tile") && (line.contains(", i1 1, i1") || line.contains(", i1 true, i1"))
+    }) || contents.split(';').any(|statement| {
+        statement.contains("cp.async.bulk.tensor") && statement.contains(".multicast::cluster")
+    })
+}
+
+/// Checks Blackwell-only TMA forms with an explicit CTA-group qualifier.
+pub(super) fn contains_tma_cta_group_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        statement.contains("cp.async.bulk.tensor")
+            && (statement.contains(".cta_group::1") || statement.contains(".cta_group::2"))
+    }) || contents.lines().any(|line| {
+        line.contains("g2s.tile") && (line.contains(", i32 1)") || line.contains(", i32 2)"))
+    })
+}
+
+/// Checks TMA copies whose destination is CTA-local shared memory.
+///
+/// `.shared::cta` already existed as a source state space for shared-to-global
+/// copies, so the following `.global` source qualifier is part of the match.
+/// The destination form was introduced in PTX 8.6 but is valid on sm_90.
+pub(super) fn contains_tma_shared_cta_destination(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        statement.contains("cp.async.bulk.") && statement.contains(".shared::cta.global")
+    })
+}
+
+/// Checks PTX 8.6 TMA modifiers with a generic sm_100 architecture floor.
+pub(super) fn contains_tma_sm100_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        if !statement.contains("cp.async.bulk.") {
+            return false;
+        }
+        statement.contains(".cp_mask")
+            || (contains_tma_gather_or_im2col(statement)
+                && statement.contains(".shared::cta.global"))
+    })
+}
+
+/// Checks PTX 8.6 TMA modes restricted to datacenter Blackwell targets.
+pub(super) fn contains_tma_blackwell_accelerated_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        if !statement.contains("cp.async.bulk.") {
+            return false;
+        }
+        statement.contains(".tile::scatter4")
+            || statement.contains(".im2col::w::128")
+            || (contains_tma_gather_or_im2col(statement)
+                && !statement.contains(".shared::cta.global"))
+    })
+}
+
+fn contains_tma_gather_or_im2col(statement: &str) -> bool {
+    statement.contains(".tile::gather4")
+        || (statement.contains(".im2col::w") && !statement.contains(".im2col::w::128"))
+}
+
+fn contains_tma_ptx86_features(contents: &str) -> bool {
+    contains_tma_sm100_features(contents)
+        || contains_tma_blackwell_accelerated_features(contents)
+        || contents.contains(".sync_restrict")
+        || contents
+            .split(';')
+            .any(|statement| statement.contains("mbarrier.") && statement.contains(".relaxed"))
+}
+
+fn contains_clc_features(contents: &str) -> bool {
+    contents.contains("clusterlaunchcontrol.")
+}
+
+fn contains_clc_multicast_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        statement.contains("clusterlaunchcontrol.")
+            && statement.contains(".multicast::cluster::all")
+    })
+}
+
+fn contains_cluster_ptx80_features(contents: &str) -> bool {
+    contents.split(';').any(|statement| {
+        statement.contains("barrier.cluster.")
+            && [".release", ".relaxed", ".acquire"]
+                .iter()
+                .any(|qualifier| statement.contains(qualifier))
+    })
+}
+
+/// Detect a direct LLVM intrinsic call, including its opaque-pointer overload.
+///
+/// Opaque-pointer LLVM IR spells the dynamic-stack intrinsics as
+/// `llvm.stacksave.p0` and `llvm.stackrestore.p0`, while typed-pointer IR can
+/// use the unsuffixed names. Keep the boundary strict so similarly named user
+/// functions do not raise the module's target requirements. Only call
+/// instructions count: declarations, comments, and quoted metadata or string
+/// contents do not reach the backend.
+fn contains_llvm_pointer_intrinsic_call(contents: &str, intrinsic: &str) -> bool {
+    contents.lines().any(|line| {
+        if !line.contains(intrinsic) {
+            return false;
+        }
+        let code = llvm_code_without_comments_or_strings(line);
+        code.match_indices(intrinsic).any(|(start, _)| {
+            if !contains_llvm_keyword(&code[..start], "call") {
+                return false;
+            }
+
+            let suffix = &code[start + intrinsic.len()..];
+            if suffix.starts_with('(') {
+                return true;
+            }
+            let Some(overload) = suffix.strip_prefix(".p") else {
+                return false;
+            };
+            let digits = overload.bytes().take_while(u8::is_ascii_digit).count();
+            digits != 0 && overload[digits..].starts_with('(')
+        })
+    })
+}
+
+fn llvm_code_without_comments_or_strings(line: &str) -> String {
+    let mut code = String::with_capacity(line.len());
+    let mut chars = line.chars();
+    let mut in_string = false;
+
+    while let Some(character) = chars.next() {
+        if in_string {
+            match character {
+                '\\' => {
+                    code.push(' ');
+                    if chars.next().is_some() {
+                        code.push(' ');
+                    }
+                }
+                '"' => {
+                    code.push(' ');
+                    in_string = false;
+                }
+                _ => code.push(' '),
+            }
+        } else {
+            match character {
+                ';' => break,
+                '"' => {
+                    code.push(' ');
+                    in_string = true;
+                }
+                _ => code.push(character),
+            }
+        }
+    }
+
+    code
+}
+
+fn contains_llvm_keyword(contents: &str, keyword: &str) -> bool {
+    contents.match_indices(keyword).any(|(start, _)| {
+        let before = contents[..start].bytes().next_back();
+        let after = contents[start + keyword.len()..].bytes().next();
+        before.is_none_or(|byte| !is_llvm_identifier_byte(byte))
+            && after.is_none_or(|byte| !is_llvm_identifier_byte(byte))
+    })
+}
+
+fn is_llvm_identifier_byte(byte: u8) -> bool {
+    byte.is_ascii_alphanumeric() || matches!(byte, b'-' | b'$' | b'.' | b'_')
+}
+
+fn contains_dynamic_stack_features(contents: &str) -> bool {
+    contains_llvm_pointer_intrinsic_call(contents, "@llvm.stacksave")
+        || contains_llvm_pointer_intrinsic_call(contents, "@llvm.stackrestore")
+}
+
+/// Detect every architecture requirement in exported LLVM text.
+///
+/// Both the ordinary PTX path and automatic libdevice mode use this exact
+/// detector. The latter renders an in-memory preview before choosing the NVVM
+/// pointer dialect.
+pub fn detect_features_in_llvm_text(contents: &str) -> DetectedFeatures {
+    let mut features = DetectedFeatures::empty();
+    for (present, feature) in [
+        (
+            contains_blackwell_features(contents),
+            DetectedFeatures::Blackwell,
+        ),
+        (
+            contains_tma_cta_group_features(contents),
+            DetectedFeatures::TmaCtaGroup,
+        ),
+        (
+            contains_tma_blackwell_accelerated_features(contents),
+            DetectedFeatures::BlackwellAccelerated,
+        ),
+        (
+            contains_clc_multicast_features(contents),
+            DetectedFeatures::BlackwellFamily,
+        ),
+        (
+            contains_redux_f32_features(contents),
+            DetectedFeatures::ReduxF32,
+        ),
+        (
+            contains_multimem_blackwell_features(contents),
+            DetectedFeatures::MultimemFp8,
+        ),
+        (
+            contains_tma_multicast(contents),
+            DetectedFeatures::TmaMulticast,
+        ),
+        (
+            contains_blackwell_matrix_features(contents),
+            DetectedFeatures::MatrixBlackwell,
+        ),
+        (contains_wgmma_features(contents), DetectedFeatures::Wgmma),
+        (contains_tma_features(contents), DetectedFeatures::Tma),
+        (
+            contains_cluster_features(contents),
+            DetectedFeatures::Cluster,
+        ),
+        (contains_sm90_features(contents), DetectedFeatures::Sm90),
+        (contains_sm80_features(contents), DetectedFeatures::Sm80),
+        (
+            contains_mma_m8n8k16_int8_features(contents)
+                || contains_mma_m8n8k32_int4_features(contents)
+                || contains_mma_m8n8k128_b1_xor_features(contents),
+            DetectedFeatures::Sm75,
+        ),
+        (
+            contains_movmatrix_features(contents),
+            DetectedFeatures::Movmatrix,
+        ),
+        (
+            contains_ldmatrix_features(contents),
+            DetectedFeatures::Ldmatrix,
+        ),
+        (
+            contains_tma_sm100_features(contents)
+                || contains_clc_features(contents)
+                || contains_f32x2_features(contents),
+            DetectedFeatures::Sm100,
+        ),
+        (
+            contains_dynamic_stack_features(contents),
+            DetectedFeatures::DynamicStack,
+        ),
+    ] {
+        if present {
+            features.insert(feature);
+        }
+    }
+    if features == DetectedFeatures::empty() {
+        features.insert(DetectedFeatures::Basic);
+    }
+    features
+}
+
+pub(super) fn detect_module_requirements_in_llvm_text(contents: &str) -> ModuleRequirements {
+    let mut ptx_isa = PtxIsaRequirement::Default;
+    if contains_packed_f16_atomic_features(contents) {
+        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx62);
+    }
+    if contains_ldmatrix_features(contents)
+        || contains_mma_m8n8k16_int8_features(contents)
+        || contains_mma_m8n8k32_int4_features(contents)
+    {
+        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx65);
+    }
+    if contains_mbarrier_features(contents)
+        || contents.contains("redux.sync")
+        || contains_mma_m16n8k16_f32_bf16_features(contents)
+        || contains_mma_m16n8k16_f32_f16_features(contents)
+        || contains_mma_m16n8k8_f32_tf32_features(contents)
+        || contains_dense_int8_mma_features(contents)
+        || contains_dense_int4_mma_features(contents)
+        || contains_b1_xor_mma_features(contents)
+        || contains_mma_m8n8k4_f64_features(contents)
+    {
+        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx70);
+    }
+    if contains_mbarrier_ptx71_features(contents) {
+        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx71);
+    }
+    if contains_b1_and_mma_features(contents) {
+        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx71);
+    }
+    if contains_dynamic_stack_features(contents) {
+        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx73);
+    }
+    if contains_movmatrix_features(contents)
+        || contains_stmatrix_features(contents)
+        || contains_ldmatrix_cta_state_space(contents)
+        || contains_cluster_features(contents)
+        || contains_mbarrier_ptx78_features(contents)
+        || contains_packed_bf16_atomic_features(contents)
+    {
+        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx78);
+    }
+    if contains_cp_async_bulk_features(contents)
+        || contains_wgmma_features(contents)
+        || contains_cluster_ptx80_features(contents)
+        || contains_elect_features(contents)
+        || contains_mbarrier_ptx80_features(contents)
+        || contents.contains("fence.mbarrier_init")
+        || contents.contains("fence.proxy.async")
+    {
+        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx80);
+    }
+    if contains_blackwell_matrix_features(contents)
+        || contains_tma_cta_group_features(contents)
+        || contains_tma_shared_cta_destination(contents)
+        || contains_tma_ptx86_features(contents)
+        || contains_clc_features(contents)
+        || contains_blackwell_features(contents)
+        || contains_fence_acquire_release_features(contents)
+        || contains_multimem_features(contents)
+        || contains_redux_f32_features(contents)
+        || contains_f32x2_features(contents)
+    {
+        ptx_isa = ptx_isa.max(PtxIsaRequirement::Ptx86);
+    }
+
+    ModuleRequirements {
+        features: detect_features_in_llvm_text(contents),
+        ptx_isa,
+    }
+}
+
+pub fn detect_module_requirements_in_llvm_file(
+    ll_path: &Path,
+) -> Result<ModuleRequirements, PipelineError> {
+    let contents = std::fs::read_to_string(ll_path).map_err(|error| {
+        PipelineError::PtxGeneration(format!(
+            "failed to inspect generated LLVM IR {}: {error}",
+            ll_path.display()
+        ))
+    })?;
+    Ok(detect_module_requirements_in_llvm_text(&contents))
+}
diff --git a/crates/cuda-oxide-codegen/src/target/features.rs b/crates/cuda-oxide-codegen/src/target/features.rs
new file mode 100644
index 0000000000..93da3083c5
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/features.rs
@@ -0,0 +1,204 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use cuda_target_spec::PTX_ISA_SPELLINGS;
+
+/// GPU feature requirements detected in one LLVM module.
+///
+/// This is a set rather than a single "strongest" feature: architecture
+/// families are not totally ordered. For example, WGMMA requires Hopper
+/// `sm_90a`, while PTX 8.6 matrix forms require Blackwell. Keeping every bit
+/// lets target validation enforce the intersection instead of silently
+/// choosing whichever instruction happened to have higher detector priority.
+#[derive(Clone, Copy, PartialEq, Eq)]
+pub struct DetectedFeatures(u32);
+
+#[allow(non_upper_case_globals)]
+impl DetectedFeatures {
+    /// tcgen05/TMEM (Blackwell datacenter, sm_100a).
+    pub(crate) const Blackwell: Self = Self(1 << 0);
+    /// Base TMA multicast (sm_90+, with architecture/family targets preferred).
+    pub(crate) const TmaMulticast: Self = Self(1 << 1);
+    /// Explicit CTA-group TMA forms (Blackwell datacenter family).
+    pub(crate) const TmaCtaGroup: Self = Self(1 << 2);
+    /// PTX 8.6 ldmatrix/stmatrix shapes supported on Blackwell family targets.
+    pub(crate) const MatrixBlackwell: Self = Self(1 << 3);
+    /// WGMMA (Hopper only, sm_90a - NOT forward-compatible).
+    pub(crate) const Wgmma: Self = Self(1 << 4);
+    /// TMA/mbarrier (Hopper+ compatible).
+    pub(crate) const Tma: Self = Self(1 << 5);
+    /// Thread Block Clusters (sm_90+, forward-compatible).
+    pub(crate) const Cluster: Self = Self(1 << 6);
+    /// Forward-compatible instructions with an sm_90 floor.
+    pub(crate) const Sm90: Self = Self(1 << 7);
+    /// Forward-compatible instructions with an sm_80 floor.
+    pub(crate) const Sm80: Self = Self(1 << 8);
+    /// Forward-compatible instructions with an sm_75 floor.
+    pub(crate) const Sm75: Self = Self(1 << 17);
+    /// Warp matrix register transpose introduced in PTX 7.8 on sm_75.
+    pub(crate) const Movmatrix: Self = Self(1 << 9);
+    /// Warp matrix shared-memory load introduced in PTX 6.5 on sm_75.
+    pub(crate) const Ldmatrix: Self = Self(1 << 10);
+    /// No special features (Volta+, with an sm_80 cross-compile default).
+    pub(crate) const Basic: Self = Self(1 << 11);
+    /// Generic Blackwell-or-newer operations such as base CLC and TMA cp_mask.
+    pub(crate) const Sm100: Self = Self(1 << 12);
+    /// Architecture/family-specific Blackwell features also available on consumers.
+    pub(crate) const BlackwellFamily: Self = Self(1 << 13);
+    /// Architecture/family-specific datacenter Blackwell TMA modes.
+    pub(crate) const BlackwellAccelerated: Self = Self(1 << 14);
+    /// Floating-point `redux.sync` (the sm_100/sm_103 architecture family).
+    pub(crate) const ReduxF32: Self = Self(1 << 15);
+    /// FP8 / f16-accumulator multimem forms on supported Blackwell families.
+    pub(crate) const MultimemFp8: Self = Self(1 << 16);
+    /// Dynamic stack save/restore, supported by LLVM NVPTX on sm_52+.
+    pub(crate) const DynamicStack: Self = Self(1 << 18);
+
+    const ALL: [Self; 19] = [
+        Self::Blackwell,
+        Self::TmaCtaGroup,
+        Self::BlackwellAccelerated,
+        Self::BlackwellFamily,
+        Self::ReduxF32,
+        Self::MultimemFp8,
+        Self::TmaMulticast,
+        Self::MatrixBlackwell,
+        Self::Wgmma,
+        Self::Tma,
+        Self::Cluster,
+        Self::Sm90,
+        Self::Sm80,
+        Self::Sm75,
+        Self::Movmatrix,
+        Self::Ldmatrix,
+        Self::Sm100,
+        Self::DynamicStack,
+        Self::Basic,
+    ];
+
+    pub(super) const fn empty() -> Self {
+        Self(0)
+    }
+
+    pub(super) const fn contains(self, feature: Self) -> bool {
+        self.0 & feature.0 != 0
+    }
+
+    pub(super) fn insert(&mut self, feature: Self) {
+        self.0 |= feature.0;
+    }
+
+    pub(super) fn iter(self) -> impl Iterator<Item = Self> {
+        Self::ALL
+            .into_iter()
+            .filter(move |feature| self.contains(*feature))
+    }
+
+    fn name(self) -> &'static str {
+        match self {
+            Self::Blackwell => "Blackwell",
+            Self::TmaMulticast => "TmaMulticast",
+            Self::TmaCtaGroup => "TmaCtaGroup",
+            Self::MatrixBlackwell => "MatrixBlackwell",
+            Self::Wgmma => "Wgmma",
+            Self::Tma => "Tma",
+            Self::Cluster => "Cluster",
+            Self::Sm90 => "Sm90",
+            Self::Sm80 => "Sm80",
+            Self::Sm75 => "Sm75",
+            Self::Movmatrix => "Movmatrix",
+            Self::Ldmatrix => "Ldmatrix",
+            Self::Sm100 => "Sm100",
+            Self::BlackwellFamily => "BlackwellFamily",
+            Self::BlackwellAccelerated => "BlackwellAccelerated",
+            Self::ReduxF32 => "ReduxF32",
+            Self::MultimemFp8 => "MultimemFp8",
+            Self::DynamicStack => "DynamicStack",
+            Self::Basic => "Basic",
+            _ => "Unknown",
+        }
+    }
+}
+
+impl std::fmt::Debug for DetectedFeatures {
+    fn fmt(&self, formatter: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        let mut first = true;
+        for feature in self.iter() {
+            if !first {
+                formatter.write_str(" + ")?;
+            }
+            formatter.write_str(feature.name())?;
+            first = false;
+        }
+        Ok(())
+    }
+}
+
+impl std::ops::BitOr for DetectedFeatures {
+    type Output = Self;
+
+    fn bitor(self, rhs: Self) -> Self::Output {
+        Self(self.0 | rhs.0)
+    }
+}
+
+/// PTX ISA requirements are independent of the GPU architecture floor.
+///
+/// For example, a module may need sm_80 because it uses `cp.async` and still
+/// need PTX 7.8 because it also uses `movmatrix`.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+pub enum PtxIsaRequirement {
+    Default,
+    Ptx62,
+    Ptx65,
+    Ptx70,
+    Ptx71,
+    Ptx73,
+    Ptx78,
+    Ptx80,
+    Ptx86,
+    Ptx87,
+    Ptx88,
+    Ptx90,
+}
+
+impl PtxIsaRequirement {
+    pub(super) fn from_spelling(spelling: u16) -> Option<Self> {
+        Some(match spelling {
+            62 => Self::Ptx62,
+            65 => Self::Ptx65,
+            70 => Self::Ptx70,
+            71 => Self::Ptx71,
+            73 => Self::Ptx73,
+            78 => Self::Ptx78,
+            80 => Self::Ptx80,
+            86 => Self::Ptx86,
+            87 => Self::Ptx87,
+            88 => Self::Ptx88,
+            90 => Self::Ptx90,
+            _ => return None,
+        })
+    }
+
+    pub(super) fn spelling(self) -> Option<u16> {
+        match self {
+            Self::Default => None,
+            requirement => PTX_ISA_SPELLINGS
+                .iter()
+                .copied()
+                .find(|spelling| Self::from_spelling(*spelling) == Some(requirement)),
+        }
+    }
+
+    pub(super) fn feature(self) -> Option<&'static str> {
+        self.spelling().and_then(cuda_target_spec::spelling_feature)
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct ModuleRequirements {
+    pub features: DetectedFeatures,
+    pub ptx_isa: PtxIsaRequirement,
+}
diff --git a/crates/cuda-oxide-codegen/src/target/generated_requirements.rs b/crates/cuda-oxide-codegen/src/target/generated_requirements.rs
new file mode 100644
index 0000000000..ea2921222a
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/generated_requirements.rs
@@ -0,0 +1,404 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::arch::{arch_compute_capability_and_suffix, is_known_cuda_target};
+use super::features::{ModuleRequirements, PtxIsaRequirement};
+use crate::generated::{
+    GeneratedModuleRequirements, GeneratedResolvedRequirement, GeneratedResolvedTarget,
+};
+use crate::generated_intrinsic_targets::{
+    GeneratedHardwareAlternative, GeneratedHardwareTarget, GeneratedTargetContract,
+    GeneratedTargetRequirement,
+};
+use cuda_target_spec::spelling_at_least;
+
+/// Convert catalog PTX floors to the discrete `llc` feature spellings this
+/// compiler supports. A floor between two spellings rounds upward; a future
+/// floor beyond the newest supported spelling is rejected instead of ignored.
+pub(crate) fn generated_ptx_isa_requirement(
+    generated: &GeneratedModuleRequirements,
+) -> Result<PtxIsaRequirement, String> {
+    let mut requirement = PtxIsaRequirement::Default;
+    for resolved in generated.resolved_targets() {
+        let target_requirement = resolved_requirement(generated, resolved)?;
+        let minimum_ptx =
+            resolved_requirement_minimum_ptx(target_requirement).ok_or_else(|| {
+                format!(
+                    "generated intrinsic `{}` (`{}`) has an empty resolved target contract",
+                    resolved.target.id, resolved.target.marker
+                )
+            })?;
+        requirement = requirement.max(ptx_isa_requirement_for_floor(
+            minimum_ptx,
+            resolved.target.id,
+            resolved.target.marker,
+        )?);
+    }
+    Ok(requirement)
+}
+
+/// Resolve the PTX floor for the selected hardware alternative.
+pub(crate) fn generated_ptx_isa_requirement_for_target(
+    generated: &GeneratedModuleRequirements,
+    arch: &str,
+) -> Result<PtxIsaRequirement, String> {
+    let mut requirement = PtxIsaRequirement::Default;
+    for resolved in generated.resolved_targets() {
+        let target_requirement = resolved_requirement(generated, resolved)?;
+        let floor = resolved_requirement_ptx_floor(arch, target_requirement).ok_or_else(|| {
+            format!(
+                "CUDA target {arch} cannot lower generated intrinsic `{}` (`{}`); requires {}",
+                resolved.target.id,
+                resolved.target.marker,
+                describe_resolved_requirement(target_requirement)
+            )
+        })?;
+        requirement = requirement.max(ptx_isa_requirement_for_floor(
+            floor,
+            resolved.target.id,
+            resolved.target.marker,
+        )?);
+    }
+    validate_sm101_ptx_pair(arch, requirement)?;
+    Ok(requirement)
+}
+
+pub(super) fn resolved_requirement(
+    generated: &GeneratedModuleRequirements,
+    resolved: &GeneratedResolvedTarget,
+) -> Result<GeneratedResolvedRequirement, String> {
+    generated.resolved_requirement(resolved).ok_or_else(|| {
+        let selector = resolved
+            .selector
+            .map(|selector| format!("{}={}", selector.name, selector.value))
+            .unwrap_or_else(|| "<none>".to_string());
+        format!(
+            "generated intrinsic `{}` (`{}`) has no unique target contract for {selector}",
+            resolved.target.id, resolved.target.marker
+        )
+    })
+}
+
+fn resolved_requirement_minimum_ptx(requirement: GeneratedResolvedRequirement) -> Option<u16> {
+    match requirement {
+        GeneratedResolvedRequirement::Target(requirement) => {
+            Some(requirement.minimum_ptx.encoded())
+        }
+        GeneratedResolvedRequirement::Contract(contract) => contract
+            .alternatives
+            .iter()
+            .map(|alternative| alternative.minimum_ptx.encoded())
+            .min(),
+    }
+}
+
+pub(super) fn ptx_isa_requirement_for_floor(
+    encoded: u16,
+    id: &str,
+    marker: &str,
+) -> Result<PtxIsaRequirement, String> {
+    if encoded <= 60 {
+        return Ok(PtxIsaRequirement::Default);
+    }
+    spelling_at_least(encoded)
+        .and_then(PtxIsaRequirement::from_spelling)
+        .ok_or_else(|| format!(
+            "generated intrinsic `{id}` (`{marker}`) requires PTX {}.{}, newer than cuda-oxide can request",
+            encoded / 10,
+            encoded % 10
+        ))
+}
+
+pub(crate) fn merge_generated_module_requirements(
+    mut text: ModuleRequirements,
+    generated: &GeneratedModuleRequirements,
+) -> Result<ModuleRequirements, String> {
+    text.ptx_isa = text.ptx_isa.max(generated_ptx_isa_requirement(generated)?);
+    Ok(text)
+}
+
+pub(crate) fn merge_generated_module_requirements_for_target(
+    mut text: ModuleRequirements,
+    generated: &GeneratedModuleRequirements,
+    arch: &str,
+) -> Result<ModuleRequirements, String> {
+    text.ptx_isa = text
+        .ptx_isa
+        .max(generated_ptx_isa_requirement_for_target(generated, arch)?);
+    validate_sm101_ptx_pair(arch, text.ptx_isa)?;
+    Ok(text)
+}
+
+/// Reject LLVM target names whose meaning changes at a newer PTX ISA.
+fn validate_sm101_ptx_pair(arch: &str, requirement: PtxIsaRequirement) -> Result<(), String> {
+    let Some((capability, suffix)) = arch_compute_capability_and_suffix(arch) else {
+        return Ok(());
+    };
+    if capability == 101
+        && matches!(suffix, Some('a' | 'f'))
+        && requirement >= PtxIsaRequirement::Ptx90
+    {
+        return Err(format!(
+            "CUDA target {arch} cannot be combined with PTX 9.0 or newer; LLVM renamed the sm_101 target to sm_110 at that PTX level"
+        ));
+    }
+    Ok(())
+}
+
+pub(crate) fn generated_target_satisfied(
+    arch: &str,
+    generated: &GeneratedModuleRequirements,
+) -> bool {
+    generated.resolved_targets().iter().all(|resolved| {
+        let Ok(requirement) = resolved_requirement(generated, resolved) else {
+            return false;
+        };
+        resolved_hardware_satisfied(arch, requirement)
+            && resolved_requirement_ptx_floor(arch, requirement).is_some_and(|floor| {
+                ptx_isa_requirement_for_floor(floor, resolved.target.id, resolved.target.marker)
+                    .is_ok()
+            })
+    })
+}
+
+fn resolved_hardware_satisfied(arch: &str, requirement: GeneratedResolvedRequirement) -> bool {
+    match requirement {
+        GeneratedResolvedRequirement::Target(requirement) => {
+            generated_hardware_satisfied(arch, requirement.hardware)
+        }
+        GeneratedResolvedRequirement::Contract(contract) => {
+            generated_contract_satisfied(arch, contract)
+        }
+    }
+}
+
+fn generated_hardware_satisfied(arch: &str, hardware: GeneratedHardwareTarget) -> bool {
+    let Some((capability, suffix)) = arch_compute_capability_and_suffix(arch) else {
+        return false;
+    };
+    if !is_known_cuda_target(capability, suffix) {
+        return false;
+    }
+
+    match hardware {
+        GeneratedHardwareTarget::All => true,
+        GeneratedHardwareTarget::AnyOf(alternatives) => alternatives.iter().any(|alternative| {
+            generated_hardware_alternative_satisfied(capability, suffix, *alternative)
+        }),
+        GeneratedHardwareTarget::TargetMatrix { contracts } => contracts.iter().any(|contract| {
+            contract.alternatives.iter().any(|alternative| {
+                generated_hardware_alternative_satisfied(capability, suffix, alternative.hardware)
+            })
+        }),
+    }
+}
+
+fn generated_contract_satisfied(arch: &str, contract: &GeneratedTargetContract) -> bool {
+    let Some((capability, suffix)) = arch_compute_capability_and_suffix(arch) else {
+        return false;
+    };
+    is_known_cuda_target(capability, suffix)
+        && contract.alternatives.iter().any(|alternative| {
+            generated_hardware_alternative_satisfied(capability, suffix, alternative.hardware)
+        })
+}
+
+pub(super) fn for_each_resolved_hardware_alternative(
+    requirement: GeneratedResolvedRequirement,
+    mut visit: impl FnMut(GeneratedHardwareAlternative),
+) {
+    match requirement {
+        GeneratedResolvedRequirement::Target(requirement) => match requirement.hardware {
+            GeneratedHardwareTarget::All => {}
+            GeneratedHardwareTarget::AnyOf(alternatives) => {
+                for alternative in alternatives {
+                    visit(*alternative);
+                }
+            }
+            GeneratedHardwareTarget::TargetMatrix { contracts } => {
+                for contract in contracts {
+                    for alternative in contract.alternatives {
+                        visit(alternative.hardware);
+                    }
+                }
+            }
+        },
+        GeneratedResolvedRequirement::Contract(contract) => {
+            for alternative in contract.alternatives {
+                visit(alternative.hardware);
+            }
+        }
+    }
+}
+
+pub(super) fn generated_hardware_candidate(alternative: GeneratedHardwareAlternative) -> String {
+    match alternative {
+        GeneratedHardwareAlternative::MinimumSm(capability) => format!("sm_{capability}"),
+        GeneratedHardwareAlternative::ExactArchitecture(capability) => {
+            format!("sm_{capability}a")
+        }
+        GeneratedHardwareAlternative::FamilyTarget(capability) => format!("sm_{capability}f"),
+    }
+}
+
+fn generated_hardware_requirement_label(alternative: GeneratedHardwareAlternative) -> String {
+    match alternative {
+        GeneratedHardwareAlternative::MinimumSm(capability) => {
+            format!("sm_{capability} or newer")
+        }
+        GeneratedHardwareAlternative::ExactArchitecture(capability) => {
+            format!("sm_{capability}a exactly")
+        }
+        GeneratedHardwareAlternative::FamilyTarget(capability) => {
+            format!("sm_{capability}f exactly")
+        }
+    }
+}
+
+fn generated_hardware_alternative_satisfied(
+    capability: u32,
+    suffix: Option<char>,
+    alternative: GeneratedHardwareAlternative,
+) -> bool {
+    match alternative {
+        GeneratedHardwareAlternative::MinimumSm(minimum) => capability >= u32::from(minimum),
+        GeneratedHardwareAlternative::ExactArchitecture(exact) => {
+            capability == u32::from(exact) && suffix == Some('a')
+        }
+        // Family targets match only the named `sm_Nf` spelling.
+        GeneratedHardwareAlternative::FamilyTarget(family) => {
+            capability == u32::from(family) && suffix == Some('f')
+        }
+    }
+}
+
+pub(super) fn generated_requirement_ptx_floor(
+    arch: &str,
+    requirement: GeneratedTargetRequirement,
+) -> Option<u16> {
+    let (capability, suffix) = arch_compute_capability_and_suffix(arch)?;
+    if !is_known_cuda_target(capability, suffix) {
+        return None;
+    }
+    match requirement.hardware {
+        GeneratedHardwareTarget::All => Some(requirement.minimum_ptx.encoded()),
+        GeneratedHardwareTarget::AnyOf(alternatives) => alternatives
+            .iter()
+            .any(|alternative| {
+                generated_hardware_alternative_satisfied(capability, suffix, *alternative)
+            })
+            .then(|| requirement.minimum_ptx.encoded()),
+        GeneratedHardwareTarget::TargetMatrix { contracts } => contracts
+            .iter()
+            .flat_map(|contract| contract.alternatives.iter())
+            .filter(|alternative| {
+                generated_hardware_alternative_satisfied(capability, suffix, alternative.hardware)
+            })
+            .map(|alternative| alternative.minimum_ptx.encoded())
+            .min(),
+    }
+}
+
+fn resolved_requirement_ptx_floor(
+    arch: &str,
+    requirement: GeneratedResolvedRequirement,
+) -> Option<u16> {
+    match requirement {
+        GeneratedResolvedRequirement::Target(requirement) => {
+            generated_requirement_ptx_floor(arch, requirement)
+        }
+        GeneratedResolvedRequirement::Contract(contract) => {
+            let (capability, suffix) = arch_compute_capability_and_suffix(arch)?;
+            is_known_cuda_target(capability, suffix).then_some(())?;
+            contract
+                .alternatives
+                .iter()
+                .filter(|alternative| {
+                    generated_hardware_alternative_satisfied(
+                        capability,
+                        suffix,
+                        alternative.hardware,
+                    )
+                })
+                .map(|alternative| alternative.minimum_ptx.encoded())
+                .min()
+        }
+    }
+}
+
+pub(crate) fn validate_generated_target(
+    arch: &str,
+    generated: &GeneratedModuleRequirements,
+) -> Result<(), String> {
+    for resolved in generated.resolved_targets() {
+        let requirement = resolved_requirement(generated, resolved)?;
+        if !resolved_hardware_satisfied(arch, requirement) {
+            return Err(format!(
+                "CUDA target {arch} cannot lower generated intrinsic `{}` (`{}`); requires {}",
+                resolved.target.id,
+                resolved.target.marker,
+                describe_resolved_requirement(requirement)
+            ));
+        }
+        ptx_isa_requirement_for_floor(
+            resolved_requirement_ptx_floor(arch, requirement).unwrap(),
+            resolved.target.id,
+            resolved.target.marker,
+        )?;
+    }
+    Ok(())
+}
+
+pub(super) fn describe_generated_hardware(hardware: GeneratedHardwareTarget) -> String {
+    match hardware {
+        GeneratedHardwareTarget::All => "any supported CUDA target".to_string(),
+        GeneratedHardwareTarget::AnyOf(alternatives) => alternatives
+            .iter()
+            .map(|alternative| generated_hardware_requirement_label(*alternative))
+            .collect::<Vec<_>>()
+            .join(" or "),
+        GeneratedHardwareTarget::TargetMatrix { contracts } => contracts
+            .iter()
+            .map(describe_generated_contract)
+            .collect::<Vec<_>>()
+            .join(" or "),
+    }
+}
+
+fn describe_resolved_requirement(requirement: GeneratedResolvedRequirement) -> String {
+    match requirement {
+        GeneratedResolvedRequirement::Target(requirement) => {
+            describe_generated_hardware(requirement.hardware)
+        }
+        GeneratedResolvedRequirement::Contract(contract) => describe_generated_contract(contract),
+    }
+}
+
+fn describe_generated_contract(contract: &GeneratedTargetContract) -> String {
+    let alternatives = contract
+        .alternatives
+        .iter()
+        .map(|alternative| {
+            format!(
+                "{} at PTX {}.{}",
+                generated_hardware_requirement_label(alternative.hardware),
+                alternative.minimum_ptx.major(),
+                alternative.minimum_ptx.minor()
+            )
+        })
+        .collect::<Vec<_>>()
+        .join(" or ");
+    if contract.selectors.is_empty() {
+        alternatives
+    } else {
+        let selectors = contract
+            .selectors
+            .iter()
+            .map(|selector| format!("{}={}", selector.name, selector.value))
+            .collect::<Vec<_>>()
+            .join(", ");
+        format!("{alternatives} for {selectors}")
+    }
+}
diff --git a/crates/cuda-oxide-codegen/src/target/mod.rs b/crates/cuda-oxide-codegen/src/target/mod.rs
new file mode 100644
index 0000000000..e243a3e115
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/mod.rs
@@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Architecture feature detection and PTX target selection.
+//!
+//! Detects the architecture and PTX-ISA requirements of exported LLVM IR and
+//! selects the minimum `sm_XX` that can lower them. The backend owns this so an
+//! experimental frontend gets the same target selection as the Rust MIR path
+//! in `mir-importer`.
+
+mod arch;
+mod detect;
+mod features;
+mod generated_requirements;
+mod select;
+#[cfg(test)]
+mod tests;
+
+pub use arch::arch_satisfies;
+pub use detect::{detect_features_in_llvm_text, detect_module_requirements_in_llvm_file};
+pub use features::{DetectedFeatures, ModuleRequirements};
+pub(crate) use generated_requirements::{
+    generated_ptx_isa_requirement, generated_target_satisfied, merge_generated_module_requirements,
+    merge_generated_module_requirements_for_target, validate_generated_target,
+};
+pub use select::{required_ptx_feature, validate_target_features, validate_target_for_llvm_major};
+pub(crate) use select::{
+    resolve_ptx_target_with_generated, select_target_with_generated,
+    validate_ptx_isa_for_llvm_major,
+};
+
+// The re-exports below preserve the module's pre-split surface. In-crate
+// consumers currently reach these names only from test code (or straight
+// through the submodules), so without the `allow` the compiler flags them
+// as unused imports in non-test builds.
+#[allow(unused_imports)]
+pub use features::PtxIsaRequirement;
+#[allow(unused_imports)]
+pub(crate) use generated_requirements::generated_ptx_isa_requirement_for_target;
+#[cfg(test)]
+#[allow(unused_imports)]
+pub use select::resolve_ptx_target;
+#[allow(unused_imports)]
+pub use select::select_target;
diff --git a/crates/cuda-oxide-codegen/src/target/select.rs b/crates/cuda-oxide-codegen/src/target/select.rs
new file mode 100644
index 0000000000..faa84f3c3d
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/select.rs
@@ -0,0 +1,284 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::arch::arch_satisfies;
+use super::features::{DetectedFeatures, PtxIsaRequirement};
+use super::generated_requirements::{
+    for_each_resolved_hardware_alternative, generated_hardware_candidate,
+    generated_target_satisfied, resolved_requirement, validate_generated_target,
+};
+use crate::error::PipelineError;
+use crate::generated::GeneratedModuleRequirements;
+use cuda_target_spec::recorded_ptx_floor;
+use libnvvm_sys::CudaArch;
+
+/// Select a concrete architecture that satisfies every detected feature.
+///
+/// The first candidate preserves the established default for a module's most
+/// restrictive-looking feature. The remaining candidates handle intersections
+/// such as WGMMA + TMA multicast, whose only common target is `sm_90a`.
+pub fn select_target(features: DetectedFeatures) -> Result<&'static str, String> {
+    let preferred = if features.contains(DetectedFeatures::Blackwell)
+        || features.contains(DetectedFeatures::TmaCtaGroup)
+        || features.contains(DetectedFeatures::BlackwellAccelerated)
+        || features.contains(DetectedFeatures::BlackwellFamily)
+        || features.contains(DetectedFeatures::ReduxF32)
+        || features.contains(DetectedFeatures::MultimemFp8)
+        || features.contains(DetectedFeatures::TmaMulticast)
+        || features.contains(DetectedFeatures::MatrixBlackwell)
+    {
+        "sm_100a"
+    } else if features.contains(DetectedFeatures::Wgmma) {
+        "sm_90a"
+    } else if features.contains(DetectedFeatures::Sm100) {
+        "sm_100"
+    } else if features.contains(DetectedFeatures::Tma) {
+        // Plain TMA is compatible with Hopper, but sm_100 is the existing
+        // cross-compilation default because it produces forward-compatible
+        // PTX for generic Blackwell devices.
+        "sm_100"
+    } else if features.contains(DetectedFeatures::Cluster)
+        || features.contains(DetectedFeatures::Sm90)
+    {
+        "sm_90"
+    } else if features.contains(DetectedFeatures::Sm80) {
+        "sm_80"
+    } else if features.contains(DetectedFeatures::Sm75)
+        || features.contains(DetectedFeatures::Movmatrix)
+        || features.contains(DetectedFeatures::Ldmatrix)
+    {
+        "sm_75"
+    } else {
+        "sm_80"
+    };
+
+    for candidate in [
+        preferred, "sm_100a", "sm_90a", "sm_100", "sm_90", "sm_80", "sm_75",
+    ] {
+        if arch_satisfies(candidate, features) {
+            return Ok(candidate);
+        }
+    }
+
+    Err(format!(
+        "detected CUDA features {features:?} do not share a compatible GPU architecture"
+    ))
+}
+
+/// Select one concrete target satisfying both text-detected features and every
+/// generated intrinsic used by the module.
+///
+/// Generated hardware requirements are a module-wide AND. Each intrinsic's
+/// `AnyOf` list remains an OR, so the search finds one architecture in the
+/// intersection rather than selecting a separate target per call.
+pub(crate) fn select_target_with_generated(
+    features: DetectedFeatures,
+    generated: &GeneratedModuleRequirements,
+) -> Result<String, String> {
+    let preferred = select_target(features)?;
+    if generated.is_empty() {
+        return Ok(preferred.to_string());
+    }
+
+    let mut candidates = vec![preferred.to_string()];
+    let mut push_candidate = |candidate: String| {
+        if !candidates.contains(&candidate) {
+            candidates.push(candidate);
+        }
+    };
+
+    // Try each catalog spelling before the exhaustive known-target list. This
+    // preserves catalog alternative order while still finding intersections
+    // such as `minimum sm_80` AND `sm_90a exactly`.
+    for resolved in generated.resolved_targets() {
+        let requirement = resolved_requirement(generated, resolved)?;
+        for_each_resolved_hardware_alternative(requirement, |alternative| {
+            push_candidate(generated_hardware_candidate(alternative));
+        });
+    }
+
+    // This is the reviewed set accepted by `is_known_cuda_target`. Family and
+    // architecture spellings are included because a generated requirement may
+    // need to intersect with an existing text-detected feature.
+    for candidate in KNOWN_CUDA_TARGET_CANDIDATES {
+        push_candidate(candidate.to_string());
+    }
+
+    if let Some(candidate) = candidates.into_iter().find(|candidate| {
+        arch_satisfies(candidate, features) && generated_target_satisfied(candidate, generated)
+    }) {
+        return Ok(candidate);
+    }
+
+    let generated_ids = generated
+        .resolved_targets()
+        .iter()
+        .map(|resolved| {
+            let selector = resolved
+                .selector
+                .map(|selector| format!(" for {}={}", selector.name, selector.value))
+                .unwrap_or_default();
+            format!(
+                "{} ({}){selector}",
+                resolved.target.id, resolved.target.marker
+            )
+        })
+        .collect::<Vec<_>>()
+        .join(", ");
+    Err(format!(
+        "detected CUDA features {features:?} and generated intrinsics [{generated_ids}] do not share a compatible GPU architecture"
+    ))
+}
+
+pub(super) const KNOWN_CUDA_TARGET_CANDIDATES: &[&str] = &[
+    "sm_70", "sm_72", "sm_75", "sm_80", "sm_86", "sm_87", "sm_88", "sm_89", "sm_90", "sm_100",
+    "sm_101", "sm_103", "sm_110", "sm_120", "sm_121", "sm_90a", "sm_100a", "sm_101a", "sm_103a",
+    "sm_110a", "sm_120a", "sm_121a", "sm_100f", "sm_101f", "sm_103f", "sm_110f", "sm_120f",
+    "sm_121f",
+];
+
+pub fn validate_target_features(
+    target: &CudaArch,
+    features: DetectedFeatures,
+) -> Result<(), String> {
+    let compatible_default = select_target(features)?;
+    if arch_satisfies(&target.sm(), features) {
+        return Ok(());
+    }
+
+    Err(format!(
+        "CUDA target {} cannot lower detected feature {features:?}; \
+         cuda-oxide requires a target compatible with {} for this module",
+        target.sm(),
+        compatible_default
+    ))
+}
+
+#[cfg(test)]
+pub fn resolve_ptx_target(
+    explicit_override: Option<&str>,
+    explicit_override_source: &'static str,
+    device_hint: Option<&str>,
+    detected: DetectedFeatures,
+) -> Result<(String, &'static str), PipelineError> {
+    resolve_ptx_target_with_generated(
+        explicit_override,
+        explicit_override_source,
+        device_hint,
+        detected,
+        &GeneratedModuleRequirements::default(),
+    )
+}
+
+pub(crate) fn resolve_ptx_target_with_generated(
+    explicit_override: Option<&str>,
+    explicit_override_source: &'static str,
+    device_hint: Option<&str>,
+    detected: DetectedFeatures,
+    generated: &GeneratedModuleRequirements,
+) -> Result<(String, &'static str), PipelineError> {
+    if let Some(target) = explicit_override {
+        let parsed =
+            target
+                .parse::<CudaArch>()
+                .map_err(|error| PipelineError::TargetSelection {
+                    target: target.to_string(),
+                    // `error` already reads "invalid CUDA target `x`: ...";
+                    // only the provenance needs to be added here.
+                    reason: format!("{error} (target from {explicit_override_source})"),
+                })?;
+        validate_target_features(&parsed, detected).map_err(|reason| {
+            PipelineError::TargetSelection {
+                target: parsed.sm(),
+                reason: format!("{reason} (target from {explicit_override_source})"),
+            }
+        })?;
+        validate_generated_target(&parsed.sm(), generated).map_err(|reason| {
+            PipelineError::TargetSelection {
+                target: parsed.sm(),
+                reason: format!("{reason} (target from {explicit_override_source})"),
+            }
+        })?;
+        return Ok((parsed.sm(), explicit_override_source));
+    }
+
+    if let Some(device) = device_hint.filter(|target| {
+        arch_satisfies(target, detected) && generated_target_satisfied(target, generated)
+    }) {
+        return Ok((device.to_string(), "detected GPU"));
+    }
+
+    let target =
+        select_target_with_generated(detected, generated).map_err(PipelineError::PtxGeneration)?;
+    Ok((target, "feature requirement"))
+}
+
+/// Select the PTX ISA independently from the GPU architecture.
+///
+/// LLVM GPU CPUs select a default PTX ISA independently from the hardware
+/// feature floor. Raise that ISA only when the selected CPU's default is too
+/// old; never force a newer target back to an older PTX version.
+pub fn required_ptx_feature(
+    target: &str,
+    requirement: PtxIsaRequirement,
+) -> Result<Option<&'static str>, String> {
+    if !target.starts_with("sm_") {
+        return Err(format!("invalid CUDA target `{target}`: expected `sm_XX`"));
+    }
+    let arch = target
+        .parse::<CudaArch>()
+        .map_err(|error| error.to_string())?;
+    let minimum = recorded_ptx_floor(&arch).map_err(|error| error.to_string())?;
+    let Some(requested) = requirement.spelling() else {
+        return Ok(None);
+    };
+    if requested <= minimum {
+        return Ok(None);
+    }
+    Ok(requirement.feature())
+}
+
+/// Reject targets that the supported LLVM 21 backend silently mishandles.
+///
+/// A recorded floor of PTX 9.0 identifies the targets LLVM 21 cannot emit
+/// reliably: it accepts their `-mcpu` spellings but only prints a warning and
+/// emits PTX 6.0, which ptxas then rejects. LLVM 22 is the first backend in
+/// cuda-oxide's supported toolchain set that emits valid PTX for them. An
+/// unknown backend version is rejected because it cannot prove support, while
+/// unknown targets remain the responsibility of the normal target validators.
+pub fn validate_target_for_llvm_major(target: &str, llc_major: Option<u32>) -> Result<(), String> {
+    let requires_llvm_22 = target.starts_with("sm_")
+        && target
+            .parse::<CudaArch>()
+            .ok()
+            .and_then(|arch| recorded_ptx_floor(&arch).ok())
+            .is_some_and(|floor| floor >= 90);
+    if requires_llvm_22 && llc_major.is_none_or(|major| major < 22) {
+        let backend = llc_major.map_or_else(
+            || "an LLVM backend with an unknown version".to_string(),
+            |major| format!("LLVM {major}"),
+        );
+        return Err(format!(
+            "CUDA target {target} requires LLVM 22 or newer; {backend} does not reliably emit valid PTX for this PTX 9.0 target"
+        ));
+    }
+    Ok(())
+}
+
+pub(crate) fn validate_ptx_isa_for_llvm_major(
+    requirement: PtxIsaRequirement,
+    llc_major: Option<u32>,
+) -> Result<(), String> {
+    if requirement >= PtxIsaRequirement::Ptx90 && llc_major.is_none_or(|major| major < 22) {
+        let backend = llc_major.map_or_else(
+            || "an LLVM backend with an unknown version".to_string(),
+            |major| format!("LLVM {major}"),
+        );
+        return Err(format!(
+            "PTX 9.0 or newer requires LLVM 22 or newer; {backend} does not support the required PTX feature"
+        ));
+    }
+    Ok(())
+}
diff --git a/crates/cuda-oxide-codegen/src/target/tests/detection_async_memory.rs b/crates/cuda-oxide-codegen/src/target/tests/detection_async_memory.rs
new file mode 100644
index 0000000000..84df4a2eef
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/tests/detection_async_memory.rs
@@ -0,0 +1,488 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::target::arch::*;
+use crate::target::detect::*;
+use crate::target::features::*;
+use crate::target::select::*;
+
+#[test]
+fn tma_and_wgmma_raise_their_independent_ptx_floors() {
+    for tma in [
+        "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes;",
+        "cp.async.bulk.commit_group;",
+        "cp.async.bulk.wait_group 0;",
+        "cp.async.bulk.wait_group.read 0;",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(tma);
+        assert!(
+            requirements.features.contains(DetectedFeatures::Tma),
+            "{tma}"
+        );
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx80, "{tma}");
+    }
+
+    let non_bulk = "cp.async.commit_group;";
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(non_bulk),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Default,
+        }
+    );
+
+    let tma_and_movmatrix = concat!(
+        "cp.async.bulk.commit_group; ",
+        "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;"
+    );
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(tma_and_movmatrix).ptx_isa,
+        PtxIsaRequirement::Ptx80
+    );
+
+    let wgmma = "wgmma.fence.sync.aligned;";
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(wgmma),
+        ModuleRequirements {
+            features: DetectedFeatures::Wgmma,
+            ptx_isa: PtxIsaRequirement::Ptx80,
+        }
+    );
+
+    let shared_cta =
+        "cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes;";
+    assert!(contains_tma_shared_cta_destination(shared_cta));
+    let shared_cta_requirements = detect_module_requirements_in_llvm_text(shared_cta);
+    assert_eq!(shared_cta_requirements.features, DetectedFeatures::Tma);
+    assert_eq!(shared_cta_requirements.ptx_isa, PtxIsaRequirement::Ptx86);
+
+    let shared_source = "cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group;";
+    assert!(!contains_tma_shared_cta_destination(shared_source));
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(shared_source).ptx_isa,
+        PtxIsaRequirement::Ptx80
+    );
+
+    let cta_group = "cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1;";
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(cta_group).ptx_isa,
+        PtxIsaRequirement::Ptx86
+    );
+
+    assert_eq!(
+        required_ptx_feature("sm_90", PtxIsaRequirement::Ptx80).unwrap(),
+        Some("+ptx80")
+    );
+    assert_eq!(
+        required_ptx_feature("sm_90a", PtxIsaRequirement::Ptx86).unwrap(),
+        Some("+ptx86")
+    );
+    assert_eq!(
+        required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx80).unwrap(),
+        None
+    );
+}
+
+#[test]
+fn related_cluster_mbarrier_and_clc_requirements_are_detected() {
+    for ptx in [
+        "mbarrier.arrive.release.cluster.shared::cluster.b64 _, [$0];",
+        "fence.mbarrier_init.release.cluster;",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(ptx);
+        assert!(
+            requirements.features.contains(DetectedFeatures::Tma),
+            "{ptx}"
+        );
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx80, "{ptx}");
+        assert!(arch_satisfies("sm_90", requirements.features));
+    }
+
+    for (ptx, expected_isa) in [
+        (
+            "mbarrier.init.shared.b64 [$0], 1;",
+            PtxIsaRequirement::Ptx70,
+        ),
+        (
+            "mbarrier.test_wait.parity.shared.b64 $0, [$1], $2;",
+            PtxIsaRequirement::Ptx71,
+        ),
+        (
+            "mbarrier.try_wait.parity.shared::cta.b64 $0, [$1], $2;",
+            PtxIsaRequirement::Ptx78,
+        ),
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(ptx);
+        assert!(
+            requirements.features.contains(DetectedFeatures::Sm80),
+            "{ptx}"
+        );
+        assert_eq!(requirements.ptx_isa, expected_isa, "{ptx}");
+        if ptx.contains("try_wait") {
+            assert!(requirements.features.contains(DetectedFeatures::Tma));
+            assert!(!arch_satisfies("sm_80", requirements.features));
+        } else {
+            assert!(arch_satisfies("sm_80", requirements.features));
+            assert!(!arch_satisfies("sm_75", requirements.features));
+        }
+    }
+
+    for ptx in [
+        "redux.sync.add.u32 $0, $1, $2;",
+        "cvt.rn.bf16x2.f32 $0, $1, $2;",
+        "cvt.rn.relu.bf16x2.f32 $0, $1, $2;",
+        "cvt.rz.bf16x2.f32 $0, $1, $2;",
+    ] {
+        assert!(
+            detect_features_in_llvm_text(ptx).contains(DetectedFeatures::Sm80),
+            "{ptx}"
+        );
+    }
+    assert_eq!(
+        required_ptx_feature("sm_80", PtxIsaRequirement::Ptx70).unwrap(),
+        None
+    );
+    assert_eq!(
+        required_ptx_feature("sm_80", PtxIsaRequirement::Ptx71).unwrap(),
+        Some("+ptx71")
+    );
+    for target in ["sm_86", "sm_87", "sm_88", "sm_89"] {
+        assert_eq!(
+            required_ptx_feature(target, PtxIsaRequirement::Ptx71).unwrap(),
+            None,
+            "{target} cannot be downgraded below its minimum PTX ISA"
+        );
+    }
+
+    for ptx in [
+        "mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 $0, [$1], $2;",
+        "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
+        "fence.acquire.sync_restrict::shared::cluster.cluster;",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(ptx);
+        assert!(
+            requirements.features.contains(DetectedFeatures::Tma),
+            "{ptx}"
+        );
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86, "{ptx}");
+        assert!(!arch_satisfies("sm_80", requirements.features));
+    }
+
+    for ptx in [
+        "mbarrier.test_wait.acquire.cta.shared::cta.b64 $0, [$1], $2;",
+        "mbarrier.arrive.release.cta.shared::cta.b64 $0, [$1];",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(ptx);
+        assert!(requirements.features.contains(DetectedFeatures::Tma));
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx80);
+        assert!(!arch_satisfies("sm_80", requirements.features));
+    }
+
+    let cluster_sync = "barrier.cluster.arrive.aligned; barrier.cluster.wait.aligned;";
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(cluster_sync),
+        ModuleRequirements {
+            features: DetectedFeatures::Cluster,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+    assert_eq!(select_target(DetectedFeatures::Cluster).unwrap(), "sm_90");
+
+    let cluster_release = "barrier.cluster.arrive.release;";
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(cluster_release).ptx_isa,
+        PtxIsaRequirement::Ptx80
+    );
+
+    for ptx in [
+        "fence.sc.cluster;",
+        "fence.acq_rel.cluster;",
+        "ld.shared::cluster.u32 $0, [$1];",
+        "ld.acquire.cluster.global.u32 $0, [$1];",
+        "getctarank.shared::cluster.u32 $0, $1;",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(ptx);
+        assert!(requirements.features.contains(DetectedFeatures::Cluster));
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx78);
+        assert!(!arch_satisfies("sm_80", requirements.features));
+    }
+
+    for ptx in [
+        "fence.acquire.cta;",
+        "fence.release.gpu;",
+        "fence.acquire.cluster;",
+        "fence.release.sys;",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(ptx);
+        assert!(
+            requirements.features.contains(DetectedFeatures::Sm90),
+            "{ptx}"
+        );
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86, "{ptx}");
+        assert_eq!(
+            requirements.features.contains(DetectedFeatures::Cluster),
+            ptx.contains(".cluster"),
+            "{ptx}"
+        );
+        assert!(!arch_satisfies("sm_80", requirements.features));
+    }
+
+    let multimem = "multimem.red.relaxed.cluster.global.add.u32 [$0], $1;";
+    let requirements = detect_module_requirements_in_llvm_text(multimem);
+    assert_eq!(requirements.features, DetectedFeatures::Sm90);
+    assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86);
+    assert_eq!(select_target(requirements.features).unwrap(), "sm_90");
+    let multimem_debug_filename = r#"!9 = !DIFile(filename: "multimem.rs", directory: "/tmp")"#;
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(multimem_debug_filename),
+        ModuleRequirements {
+            features: DetectedFeatures::Basic,
+            ptx_isa: PtxIsaRequirement::Default,
+        }
+    );
+
+    for multimem in [
+        "multimem.ld_reduce.relaxed.cta.add.v4.e4m3 {$0, $1, $2, $3}, [$4];",
+        "multimem.st.relaxed.gpu.e5m2 [$0], $1;",
+        "multimem.ld_reduce.add.acc::f16.v4.e5m2 {$0, $1, $2, $3}, [$4];",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(multimem);
+        assert_eq!(
+            requirements.features,
+            DetectedFeatures::MultimemFp8 | DetectedFeatures::Sm90,
+            "{multimem}"
+        );
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86, "{multimem}");
+        assert_eq!(select_target(requirements.features).unwrap(), "sm_100a");
+        for target in [
+            "sm_100a", "sm_103a", "sm_110a", "sm_120a", "sm_121a", "sm_100f", "sm_103f", "sm_110f",
+        ] {
+            assert!(arch_satisfies(target, requirements.features), "{target}");
+        }
+        for target in ["sm_100", "sm_90a", "sm_120f", "sm_121f"] {
+            assert!(!arch_satisfies(target, requirements.features), "{target}");
+        }
+    }
+
+    let redux_f32 = "redux.sync.min.abs.NaN.f32 $0, $1, $2;";
+    let requirements = detect_module_requirements_in_llvm_text(redux_f32);
+    assert_eq!(
+        requirements.features,
+        DetectedFeatures::ReduxF32 | DetectedFeatures::Sm80
+    );
+    assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86);
+    assert_eq!(select_target(requirements.features).unwrap(), "sm_100a");
+    for target in ["sm_100a", "sm_103a", "sm_100f", "sm_103f"] {
+        assert!(arch_satisfies(target, requirements.features), "{target}");
+    }
+    for target in ["sm_100", "sm_110a", "sm_120a", "sm_121f"] {
+        assert!(!arch_satisfies(target, requirements.features), "{target}");
+    }
+
+    for sreg in [
+        "mov.u32 $0, %clusterid.x;",
+        "mov.u32 $0, %nclusterid.z;",
+        "mov.u32 $0, %cluster_ctarank;",
+        "mov.u32 $0, %cluster_nctarank;",
+        "mov.pred $0, %is_explicit_cluster;",
+    ] {
+        assert_eq!(
+            detect_module_requirements_in_llvm_text(sreg),
+            ModuleRequirements {
+                features: DetectedFeatures::Cluster,
+                ptx_isa: PtxIsaRequirement::Ptx78,
+            },
+            "{sreg}"
+        );
+    }
+
+    let cluster_metadata = r#"!0 = !{!"cluster_dim_x", i32 2}
+            !1 = !{!"cluster_dim_y", i32 1}
+            !2 = !{!"cluster_dim_z", i32 1}"#;
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(cluster_metadata),
+        ModuleRequirements {
+            features: DetectedFeatures::Cluster,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+    let cluster_debug_local =
+        r#"!8 = !DILocalVariable(name: "cluster_dim_x", scope: !1, file: !2, line: 3)"#;
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(cluster_debug_local),
+        ModuleRequirements {
+            features: DetectedFeatures::Basic,
+            ptx_isa: PtxIsaRequirement::Default,
+        }
+    );
+
+    let elect = "elect.sync $0|p, $1;";
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(elect),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm90,
+            ptx_isa: PtxIsaRequirement::Ptx80,
+        }
+    );
+
+    let tcgen_wait = "tcgen05.wait::ld.sync.aligned;";
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(tcgen_wait),
+        ModuleRequirements {
+            features: DetectedFeatures::Blackwell,
+            ptx_isa: PtxIsaRequirement::Ptx86,
+        }
+    );
+
+    let tcgen_debug_filename = r#"!7 = !DIFile(filename: "tcgen05.rs", directory: "/tmp")"#;
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(tcgen_debug_filename),
+        ModuleRequirements {
+            features: DetectedFeatures::Basic,
+            ptx_isa: PtxIsaRequirement::Default,
+        }
+    );
+
+    let clc = "clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 $0, $1;";
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(clc),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm100,
+            ptx_isa: PtxIsaRequirement::Ptx86,
+        }
+    );
+    assert_eq!(select_target(DetectedFeatures::Sm100).unwrap(), "sm_100");
+    assert!(!arch_satisfies("sm_90", DetectedFeatures::Sm100));
+    assert!(arch_satisfies("sm_120", DetectedFeatures::Sm100));
+
+    let clc_multicast = "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 [$0], [$1];";
+    let requirements = detect_module_requirements_in_llvm_text(clc_multicast);
+    assert_eq!(
+        requirements.features,
+        DetectedFeatures::Sm100 | DetectedFeatures::BlackwellFamily
+    );
+    assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86);
+    assert_eq!(select_target(requirements.features).unwrap(), "sm_100a");
+    assert!(!arch_satisfies("sm_100", requirements.features));
+    assert!(arch_satisfies("sm_120a", requirements.features));
+    for arch in ["sm_100f", "sm_101f", "sm_110f", "sm_121f"] {
+        assert!(arch_satisfies(arch, requirements.features), "{arch}");
+    }
+    for arch in ["sm_103a", "sm_121a"] {
+        assert!(!arch_satisfies(arch, requirements.features), "{arch}");
+    }
+}
+
+#[test]
+fn ptx86_tma_modes_enforce_their_architecture_families() {
+    for ptx in [
+        "cp.async.bulk.global.shared::cta.bulk_group.cp_mask [$0], [$1], 16, $2;",
+        "cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes;",
+        "cp.async.bulk.tensor.3d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes;",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(ptx);
+        assert!(
+            requirements.features.contains(DetectedFeatures::Tma),
+            "{ptx}"
+        );
+        assert!(
+            requirements.features.contains(DetectedFeatures::Sm100),
+            "{ptx}"
+        );
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86, "{ptx}");
+        assert!(!arch_satisfies("sm_90", requirements.features));
+        assert!(arch_satisfies("sm_100", requirements.features));
+    }
+
+    for ptx in [
+        "cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes;",
+        "cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group;",
+        "cp.async.bulk.tensor.3d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes;",
+        "cp.async.bulk.prefetch.tensor.3d.L2.global.im2col::w::128;",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(ptx);
+        assert!(
+            requirements.features.contains(DetectedFeatures::Tma),
+            "{ptx}"
+        );
+        assert!(
+            requirements
+                .features
+                .contains(DetectedFeatures::BlackwellAccelerated),
+            "{ptx}"
+        );
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86, "{ptx}");
+        assert_eq!(select_target(requirements.features).unwrap(), "sm_100a");
+        assert!(!arch_satisfies("sm_100", requirements.features));
+        assert!(!arch_satisfies("sm_120a", requirements.features));
+        assert!(arch_satisfies("sm_103f", requirements.features));
+    }
+
+    assert!(!contains_tma_sm100_features("custom.op.cp_mask $0;"));
+    assert!(!contains_tma_blackwell_accelerated_features(
+        "custom.tile::scatter4 $0;"
+    ));
+}
+
+#[test]
+fn test_sm90_floor_wins_when_sm80_features_are_also_present() {
+    let llvm = r#"
+            call i32 asm pure "add.rn.bf16x2 $0, $1, $2;", "=r,r,r"(i32 %a, i32 %b)
+            call void asm sideeffect "cp.async.ca.shared.global [%0], [%1], 4;", "l,l"()
+        "#;
+
+    assert!(contains_sm90_features(llvm));
+    assert!(contains_sm80_features(llvm));
+    assert_eq!(
+        detect_features_in_llvm_text(llvm),
+        DetectedFeatures::Sm90 | DetectedFeatures::Sm80
+    );
+}
+
+#[test]
+fn test_tma_multicast_detection_requires_cta_mask() {
+    let multicast = "call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile(i32 0, i1 1, i1 false)";
+    let unicast = "call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile(i32 0, i1 0, i1 false)";
+    let literal_multicast = "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster";
+    let cg1 =
+        "cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1";
+    let cg2 = "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2";
+    let cg1_intrinsic = "call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d(ptr addrspace(7) %dst, i1 0, i1 false, i32 1)";
+    let cg2_intrinsic = "call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d(ptr addrspace(7) %dst, i1 1, i1 false, i32 2)";
+    let unrelated_i32 = "call void @unrelated(i32 2)";
+
+    assert!(contains_tma_multicast(multicast));
+    assert!(contains_tma_multicast(literal_multicast));
+    assert!(!contains_tma_multicast(unicast));
+    assert_eq!(
+        detect_features_in_llvm_text(multicast),
+        DetectedFeatures::TmaMulticast | DetectedFeatures::Tma
+    );
+    assert_eq!(
+        detect_features_in_llvm_text(literal_multicast),
+        DetectedFeatures::TmaMulticast | DetectedFeatures::Tma | DetectedFeatures::Cluster
+    );
+    assert_eq!(detect_features_in_llvm_text(unicast), DetectedFeatures::Tma);
+    assert_eq!(
+        detect_features_in_llvm_text(cg1),
+        DetectedFeatures::TmaCtaGroup | DetectedFeatures::Tma
+    );
+    assert_eq!(
+        detect_features_in_llvm_text(cg1_intrinsic),
+        DetectedFeatures::TmaCtaGroup | DetectedFeatures::Tma
+    );
+    assert_eq!(
+        detect_features_in_llvm_text(cg2),
+        DetectedFeatures::TmaCtaGroup
+            | DetectedFeatures::TmaMulticast
+            | DetectedFeatures::Tma
+            | DetectedFeatures::Cluster
+    );
+    assert_eq!(
+        detect_features_in_llvm_text(cg2_intrinsic),
+        DetectedFeatures::TmaCtaGroup | DetectedFeatures::TmaMulticast | DetectedFeatures::Tma
+    );
+    assert!(!contains_tma_cta_group_features(unrelated_i32));
+}
diff --git a/crates/cuda-oxide-codegen/src/target/tests/detection_matrix.rs b/crates/cuda-oxide-codegen/src/target/tests/detection_matrix.rs
new file mode 100644
index 0000000000..e98cfc1505
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/tests/detection_matrix.rs
@@ -0,0 +1,1591 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::generated::GeneratedModuleRequirements;
+use crate::target::arch::*;
+use crate::target::detect::*;
+use crate::target::features::*;
+use crate::target::generated_requirements::*;
+use crate::target::select::*;
+use libnvvm_sys::CudaArch;
+
+#[test]
+fn test_feature_detection_reads_llvm_ir_snippets() {
+    let llvm = r#"
+            call void asm sideeffect "wgmma.fence.sync.aligned", ""()
+            call void @llvm.nvvm.tcgen05.alloc()
+            call void asm sideeffect "cluster.sync.aligned", ""()
+            call void asm sideeffect "cp.async.bulk.tensor.2d.shared::cluster.global", ""()
+            call void asm sideeffect "cp.async.ca.shared.global", ""()
+        "#;
+
+    assert!(contains_wgmma_features(llvm));
+    assert!(contains_blackwell_features(llvm));
+    assert!(contains_cluster_features(llvm));
+    assert!(contains_tma_features(llvm));
+    assert!(contains_sm80_features(llvm));
+    let detected = detect_features_in_llvm_text(llvm);
+    for feature in [
+        DetectedFeatures::Blackwell,
+        DetectedFeatures::Wgmma,
+        DetectedFeatures::Cluster,
+        DetectedFeatures::Tma,
+        DetectedFeatures::Sm80,
+    ] {
+        assert!(detected.contains(feature), "missing {feature:?}");
+    }
+    assert!(
+        select_target(detected).is_err(),
+        "Hopper-only WGMMA and Blackwell-only tcgen05 are incompatible"
+    );
+}
+
+#[test]
+fn test_sm80_detection_accepts_inline_ptx_and_nvvm_intrinsics() {
+    for llvm in [
+        r#"call void asm sideeffect "cp.async.ca.shared.global [%0], [%1], 4;", "l,l"()"#,
+        "call void @llvm.nvvm.cp.async.ca.shared.global.8(ptr addrspace(3) %dst, ptr addrspace(1) %src)",
+        r#"call void asm sideeffect "cp.async.commit_group;", ""()"#,
+        "call void @llvm.nvvm.cp.async.wait.all()",
+    ] {
+        assert!(contains_sm80_features(llvm), "missed cp.async in {llvm}");
+        assert_eq!(detect_features_in_llvm_text(llvm), DetectedFeatures::Sm80);
+    }
+}
+
+#[test]
+fn test_bf16x2_detection_matches_exact_architecture_floors() {
+    for mnemonic in [
+        "add.rn.bf16x2 $0, $1, $2;",
+        "sub.rn.bf16x2 $0, $1, $2;",
+        "mul.rn.bf16x2 $0, $1, $2;",
+    ] {
+        assert!(contains_sm90_features(mnemonic));
+        assert!(!contains_sm80_features(mnemonic));
+        assert_eq!(
+            detect_features_in_llvm_text(mnemonic),
+            DetectedFeatures::Sm90
+        );
+    }
+
+    for mnemonic in ["add.rn.bf16x2\t$0, $1, $2;", "sub.rn.bf16x2\\09$0, $1, $2;"] {
+        assert_eq!(
+            detect_features_in_llvm_text(mnemonic),
+            DetectedFeatures::Sm90,
+            "{mnemonic:?}"
+        );
+    }
+
+    for mnemonic in [
+        "fma.rn.bf16x2 $0, $1, $2, $3;",
+        "fma.rn.relu.bf16x2 $0, $1, $2, $3;",
+        "min.bf16x2 $0, $1, $2;",
+        "max.bf16x2 $0, $1, $2;",
+        "neg.bf16x2 $0, $1;",
+        "abs.bf16x2 $0, $1;",
+    ] {
+        assert!(!contains_sm90_features(mnemonic));
+        assert!(contains_sm80_features(mnemonic));
+        assert_eq!(
+            detect_features_in_llvm_text(mnemonic),
+            DetectedFeatures::Sm80
+        );
+    }
+
+    for near_miss in [
+        "add.rn.bf16x2x $0, $1, $2;",
+        "fma.rn.bf16x2x $0, $1, $2, $3;",
+        "add.rn.bf16x2\\5C09$0, $1, $2;",
+    ] {
+        assert!(!contains_sm90_features(near_miss));
+        assert!(!contains_sm80_features(near_miss));
+        assert_eq!(
+            detect_features_in_llvm_text(near_miss),
+            DetectedFeatures::Basic
+        );
+    }
+}
+
+#[test]
+fn f32x2_family_detection_requires_sm100_and_ptx86() {
+    for mnemonic in [
+        "add.f32x2 $0, $1, $2;",
+        "add.rz.f32x2 $0, $1, $2;",
+        "sub.rm.f32x2 $0, $1, $2;",
+        "mul.rp.ftz.f32x2 $0, $1, $2;",
+        "fma.rn.f32x2 $0, $1, $2, $3;",
+        "fma.rz.ftz.f32x2\\09$0, $1, $2, $3;",
+    ] {
+        assert!(contains_f32x2_features(mnemonic));
+        let requirements = detect_module_requirements_in_llvm_text(mnemonic);
+        assert_eq!(requirements.features, DetectedFeatures::Sm100);
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx86);
+        assert!(!arch_satisfies("sm_90", requirements.features));
+        assert!(arch_satisfies("sm_100", requirements.features));
+        assert!(arch_satisfies("sm_120", requirements.features));
+    }
+
+    for near_miss in [
+        "add.rn.f32x2x $0, $1, $2;",
+        "fmax.rn.f32x2 $0, $1, $2;",
+        "myadd.rn.f32x2 $0, $1, $2;",
+        "add.rn.f32 $0, $1, $2;",
+    ] {
+        assert!(!contains_f32x2_features(near_miss));
+    }
+}
+
+#[test]
+fn dense_bf16_mma_detection_applies_exact_sm80_and_ptx70_floors() {
+    let mnemonic = "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};";
+    for spelling in [
+        mnemonic,
+        "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\t{$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\\09{$0}, {$1}, {$2}, {$3};",
+        ";mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "prefix\\0Amma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "\"mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "{mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "$L:mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "/* comment */mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "@p mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "@!%p\\09mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            contains_mma_m16n8k16_f32_bf16_features(spelling),
+            "missed {spelling:?}"
+        );
+    }
+
+    let requirements = detect_module_requirements_in_llvm_text(mnemonic);
+    assert_eq!(
+        requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Ptx70,
+        }
+    );
+    assert_eq!(select_target(requirements.features).unwrap(), "sm_80");
+
+    let lower_target = resolve_ptx_target(
+        Some("sm_75"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        requirements.features,
+    )
+    .unwrap_err();
+    assert!(
+        lower_target
+            .to_string()
+            .contains("cannot lower detected feature Sm80"),
+        "{lower_target}"
+    );
+    let (target, _) = resolve_ptx_target(
+        Some("sm_80"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        requirements.features,
+    )
+    .unwrap();
+    assert_eq!(target, "sm_80");
+
+    for near_miss in [
+        "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sp.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32x {$0}, {$1}, {$2}, {$3};",
+        "not_mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "$mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "%mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "@mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "!mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "@!mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "not$mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "/mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        ")mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            !contains_mma_m16n8k16_f32_bf16_features(near_miss),
+            "matched {near_miss:?}"
+        );
+    }
+
+    let combined = format!(
+        "{mnemonic}\n{}",
+        "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;"
+    );
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&combined),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+}
+
+#[test]
+fn packed_atomic_detection_enforces_native_architecture_and_ptx_floors() {
+    for f16 in [
+        "atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "atom.global.add.noftz.f16x2\t$0, [$1], $2;",
+        "atom.global.add.noftz.f16x2\\09$0, [$1], $2;",
+        ";atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "prefix\\0Aatom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "\"atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "{atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "$L:atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "/* comment */atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "@p atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "@!%p\\09atom.global.add.noftz.f16x2 $0, [$1], $2;",
+    ] {
+        assert!(contains_packed_f16_atomic_features(f16), "{f16:?}");
+        assert!(!contains_packed_bf16_atomic_features(f16), "{f16:?}");
+        assert_eq!(detect_features_in_llvm_text(f16), DetectedFeatures::Basic);
+        assert_eq!(
+            detect_module_requirements_in_llvm_text(f16).ptx_isa,
+            PtxIsaRequirement::Ptx62
+        );
+    }
+    assert_eq!(
+        required_ptx_feature("sm_70", PtxIsaRequirement::Ptx62).unwrap(),
+        Some("+ptx62")
+    );
+    assert_eq!(
+        resolve_ptx_target(
+            Some("sm_70"),
+            "CUDA_OXIDE_TARGET",
+            None,
+            DetectedFeatures::Basic
+        )
+        .unwrap()
+        .0,
+        "sm_70"
+    );
+
+    for bf16 in [
+        "atom.global.add.noftz.bf16x2 $0, [$1], $2;",
+        "atom.global.add.noftz.bf16x2\t$0, [$1], $2;",
+        "atom.global.add.noftz.bf16x2\\0A$0, [$1], $2;",
+    ] {
+        assert!(contains_packed_bf16_atomic_features(bf16), "{bf16:?}");
+        assert!(!contains_packed_f16_atomic_features(bf16), "{bf16:?}");
+        assert_eq!(detect_features_in_llvm_text(bf16), DetectedFeatures::Sm90);
+        assert_eq!(
+            detect_module_requirements_in_llvm_text(bf16).ptx_isa,
+            PtxIsaRequirement::Ptx78
+        );
+    }
+    assert_eq!(select_target(DetectedFeatures::Sm90).unwrap(), "sm_90");
+    let rejected = resolve_ptx_target(
+        Some("sm_80"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        DetectedFeatures::Sm90,
+    )
+    .expect_err("native bf16x2 atomic add must reject sm_80")
+    .to_string();
+    assert!(rejected.contains("cannot lower detected feature Sm90"));
+    let near_miss = resolve_ptx_target(
+        Some("sm_89"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        DetectedFeatures::Sm90,
+    )
+    .expect_err("the architecture immediately below sm_90 must be rejected")
+    .to_string();
+    assert!(near_miss.contains("cannot lower detected feature Sm90"));
+
+    let both = "atom.global.add.noftz.f16x2 $0, [$1], $2; \
+                    atom.global.add.noftz.bf16x2 $0, [$1], $2;";
+    let requirements = detect_module_requirements_in_llvm_text(both);
+    assert_eq!(requirements.features, DetectedFeatures::Sm90);
+    assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx78);
+
+    let dense_bf16_mma =
+        "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};";
+    let mma_f16_requirements = detect_module_requirements_in_llvm_text(&format!(
+        "{dense_bf16_mma}\natom.global.add.noftz.f16x2 $0, [$1], $2;"
+    ));
+    assert_eq!(
+        mma_f16_requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Ptx70,
+        }
+    );
+    assert_eq!(
+        select_target(mma_f16_requirements.features).unwrap(),
+        "sm_80"
+    );
+
+    let mma_bf16_requirements = detect_module_requirements_in_llvm_text(&format!(
+        "{dense_bf16_mma}\natom.global.add.noftz.bf16x2 $0, [$1], $2;"
+    ));
+    assert_eq!(
+        mma_bf16_requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm90 | DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+    assert_eq!(
+        select_target(mma_bf16_requirements.features).unwrap(),
+        "sm_90"
+    );
+
+    for near_miss in [
+        "atom.global.add.noftz.f16x2x $0, [$1], $2;",
+        "atom.global.add.noftz.bf16x2x $0, [$1], $2;",
+        "not_atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "not_atom.global.add.noftz.bf16x2 $0, [$1], $2;",
+        "not.atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "not.atom.global.add.noftz.bf16x2 $0, [$1], $2;",
+        "$atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "%atom.global.add.noftz.bf16x2 $0, [$1], $2;",
+        "@atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "!atom.global.add.noftz.bf16x2 $0, [$1], $2;",
+        "@!atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "not$atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "/atom.global.add.noftz.bf16x2 $0, [$1], $2;",
+        ")atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "atom.shared.add.noftz.f16x2 $0, [$1], $2;",
+        "atom.global.add.bf16x2 $0, [$1], $2;",
+        "red.global.add.noftz.bf16x2 [$0], $1;",
+        "atom.global.add.noftz.f16x2\\5C09$0, [$1], $2;",
+    ] {
+        assert!(!contains_packed_f16_atomic_features(near_miss));
+        assert!(!contains_packed_bf16_atomic_features(near_miss));
+        assert_eq!(
+            detect_module_requirements_in_llvm_text(near_miss),
+            ModuleRequirements {
+                features: DetectedFeatures::Basic,
+                ptx_isa: PtxIsaRequirement::Default,
+            },
+            "{near_miss:?}"
+        );
+    }
+}
+
+#[test]
+fn fp64_mma_and_packed_atomics_take_the_strongest_target_floor() {
+    let dense_bf16_mma =
+        "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};";
+    let dense_fp64_mma =
+        "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};";
+
+    let fp64_f16_requirements = detect_module_requirements_in_llvm_text(&format!(
+        "{dense_fp64_mma}\natom.global.add.noftz.f16x2 $0, [$1], $2;"
+    ));
+    assert_eq!(
+        fp64_f16_requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Ptx70,
+        }
+    );
+    assert_eq!(
+        select_target(fp64_f16_requirements.features).unwrap(),
+        "sm_80"
+    );
+
+    let fp64_bf16_requirements = detect_module_requirements_in_llvm_text(&format!(
+        "{dense_fp64_mma}\natom.global.add.noftz.bf16x2 $0, [$1], $2;"
+    ));
+    assert_eq!(
+        fp64_bf16_requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm90 | DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+    assert_eq!(
+        select_target(fp64_bf16_requirements.features).unwrap(),
+        "sm_90"
+    );
+
+    let all_four = format!(
+        "{dense_bf16_mma}\n{dense_fp64_mma}\n\
+             atom.global.add.noftz.f16x2 $0, [$1], $2;\n\
+             atom.global.add.noftz.bf16x2 $0, [$1], $2;"
+    );
+    let all_four_requirements = detect_module_requirements_in_llvm_text(&all_four);
+    assert_eq!(
+        all_four_requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm90 | DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+    assert_eq!(
+        select_target(all_four_requirements.features).unwrap(),
+        "sm_90"
+    );
+}
+
+#[test]
+fn dense_f16_mma_detection_applies_exact_sm80_and_ptx70_floors() {
+    let mnemonic = "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};";
+    for spelling in [
+        mnemonic,
+        "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\t{$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\\09{$0}, {$1}, {$2}, {$3};",
+        ";mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "prefix\\0Amma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "\"mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "{mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "$L:mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "/* comment */mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "@p mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "@!%p\\09mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            contains_mma_m16n8k16_f32_f16_features(spelling),
+            "missed {spelling:?}"
+        );
+    }
+
+    let requirements = detect_module_requirements_in_llvm_text(mnemonic);
+    assert_eq!(
+        requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Ptx70,
+        }
+    );
+    assert_eq!(select_target(requirements.features).unwrap(), "sm_80");
+
+    let lower_target = resolve_ptx_target(
+        Some("sm_75"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        requirements.features,
+    )
+    .unwrap_err();
+    assert!(
+        lower_target
+            .to_string()
+            .contains("cannot lower detected feature Sm80"),
+        "{lower_target}"
+    );
+    let (target, _) = resolve_ptx_target(
+        Some("sm_80"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        requirements.features,
+    )
+    .unwrap();
+    assert_eq!(target, "sm_80");
+
+    for near_miss in [
+        "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sp.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32x {$0}, {$1}, {$2}, {$3};",
+        "not_mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "$mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "%mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "@mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "!mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "@!mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "not$mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "/mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        ")mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            !contains_mma_m16n8k16_f32_f16_features(near_miss),
+            "matched {near_miss:?}"
+        );
+    }
+
+    let combined = format!(
+        "{mnemonic}\n{}",
+        "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;"
+    );
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&combined),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+}
+
+#[test]
+fn tf32_mma_detection_applies_exact_sm80_and_ptx70_floors() {
+    let mnemonic = concat!(
+        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 ",
+        "{$0, $1, $2, $3}, {$4, $5, $6, $7}, {$8, $9}, {$10, $11, $12, $13};"
+    );
+    for spelling in [
+        mnemonic,
+        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\t{$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\\09{$0}, {$1}, {$2}, {$3};",
+        ";mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "prefix\\0Amma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "\"mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "{mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "$L:mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "/* comment */mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "@p mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "@!%p\\09mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            contains_mma_m16n8k8_f32_tf32_features(spelling),
+            "missed {spelling:?}"
+        );
+    }
+
+    let requirements = detect_module_requirements_in_llvm_text(mnemonic);
+    assert_eq!(requirements.features, DetectedFeatures::Sm80);
+    assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx70);
+    let (target, _) = resolve_ptx_target(None, "CUDA_OXIDE_TARGET", None, requirements.features)
+        .expect("auto-resolve");
+    assert_eq!(target, "sm_80");
+
+    for near_miss in [
+        "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sp.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32x {$0}, {$1}, {$2}, {$3};",
+        "not_mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "$mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "%mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "@mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "!mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "@!mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "not$mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        "/mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+        ")mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            !contains_mma_m16n8k8_f32_tf32_features(near_miss),
+            "matched {near_miss:?}"
+        );
+    }
+
+    let sm_75: CudaArch = "sm_75".parse().unwrap();
+    let sm_80: CudaArch = "sm_80".parse().unwrap();
+    assert!(validate_target_features(&sm_75, requirements.features).is_err());
+    assert!(validate_target_features(&sm_80, requirements.features).is_ok());
+    let error = resolve_ptx_target(
+        Some("sm_75"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        requirements.features,
+    )
+    .expect_err("sm_75 must not accept TF32 tensor-core MMA")
+    .to_string();
+    assert!(
+        error.contains("cannot lower detected feature Sm80"),
+        "{error}"
+    );
+
+    let combined = format!("{mnemonic}\nmovmatrix.sync.aligned.m8n8.trans.b16 $0, $1;");
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&combined),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+}
+
+#[test]
+fn int8_mma_detection_applies_exact_sm80_and_ptx70_floors() {
+    let mut forms = 0;
+    for shape in ["m16n8k16", "m16n8k32"] {
+        for a_type in ["s8", "u8"] {
+            for b_type in ["s8", "u8"] {
+                for satfinite in [false, true] {
+                    let overflow = if satfinite { ".satfinite" } else { "" };
+                    let spelling = format!(
+                        "mma.sync.aligned.{shape}.row.col{overflow}.s32.{a_type}.{b_type}.s32 {{$0}}, {{$1}}, {{$2}}, {{$3}};"
+                    );
+                    assert!(
+                        contains_dense_int8_mma_features(&spelling),
+                        "missed {spelling:?}"
+                    );
+                    assert_eq!(
+                        detect_module_requirements_in_llvm_text(&spelling),
+                        ModuleRequirements {
+                            features: DetectedFeatures::Sm80,
+                            ptx_isa: PtxIsaRequirement::Ptx70,
+                        },
+                        "{spelling}"
+                    );
+                    forms += 1;
+                }
+            }
+        }
+    }
+    assert_eq!(forms, 16);
+
+    for spelling in [
+        "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32\t{$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\\09{$0}, {$1}, {$2}, {$3};",
+        ";mma.sync.aligned.m16n8k16.row.col.s32.u8.u8.s32 {$0}, {$1}, {$2}, {$3};",
+        "prefix\\0Amma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32 {$0}, {$1}, {$2}, {$3};",
+        "@p mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32 {$0}, {$1}, {$2}, {$3};",
+        "@!%p\\09mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            contains_dense_int8_mma_features(spelling),
+            "missed {spelling:?}"
+        );
+    }
+
+    let representative = concat!(
+        "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32 ",
+        "{$0, $1, $2, $3}, {$4, $5}, {$6}, {$7, $8, $9, $10};"
+    );
+    let requirements = detect_module_requirements_in_llvm_text(representative);
+    let (target, _) = resolve_ptx_target(None, "CUDA_OXIDE_TARGET", None, requirements.features)
+        .expect("auto-resolve");
+    assert_eq!(target, "sm_80");
+
+    for near_miss in [
+        "mma.sync.aligned.m16n8k8.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.col.row.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32x {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32.satfinite {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.satfiniteX.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32x {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.u32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k16.row.col.s32.s4.u8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k16.row.col.s32.u8.f16.s32 {$0}, {$1}, {$2}, {$3};",
+        "not_mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "$mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "$mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "%mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "@mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "!mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "@!mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "not$mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "/mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        ")mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            !contains_dense_int8_mma_features(near_miss),
+            "matched {near_miss:?}"
+        );
+    }
+
+    let sm_75: CudaArch = "sm_75".parse().unwrap();
+    let sm_80: CudaArch = "sm_80".parse().unwrap();
+    assert!(validate_target_features(&sm_75, requirements.features).is_err());
+    assert!(validate_target_features(&sm_80, requirements.features).is_ok());
+    let error = resolve_ptx_target(
+        Some("sm_75"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        requirements.features,
+    )
+    .expect_err("sm_75 must not accept INT8 tensor-core MMA")
+    .to_string();
+    assert!(
+        error.contains("cannot lower detected feature Sm80"),
+        "{error}"
+    );
+
+    let combined = format!("{representative}\nmovmatrix.sync.aligned.m8n8.trans.b16 $0, $1;");
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&combined),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+}
+
+#[test]
+fn dense_int4_mma_detection_applies_exact_sm80_and_ptx70_floors() {
+    let mut forms = 0;
+    for shape in ["m16n8k32", "m16n8k64"] {
+        for a_type in ["s4", "u4"] {
+            for b_type in ["s4", "u4"] {
+                for satfinite in [false, true] {
+                    let overflow = if satfinite { ".satfinite" } else { "" };
+                    let spelling = format!(
+                        "mma.sync.aligned.{shape}.row.col{overflow}.s32.{a_type}.{b_type}.s32 {{$0}}, {{$1}}, {{$2}}, {{$3}};"
+                    );
+                    assert!(
+                        contains_dense_int4_mma_features(&spelling),
+                        "missed {spelling:?}"
+                    );
+                    assert!(
+                        !contains_mma_m8n8k32_int4_features(&spelling),
+                        "m16 form entered the m8 INT4 detector: {spelling:?}"
+                    );
+                    assert!(
+                        !contains_dense_int8_mma_features(&spelling),
+                        "INT4 form entered the dense INT8 detector: {spelling:?}"
+                    );
+                    assert_eq!(
+                        detect_module_requirements_in_llvm_text(&spelling),
+                        ModuleRequirements {
+                            features: DetectedFeatures::Sm80,
+                            ptx_isa: PtxIsaRequirement::Ptx70,
+                        },
+                        "{spelling}"
+                    );
+                    forms += 1;
+                }
+            }
+        }
+    }
+    assert_eq!(forms, 16);
+
+    for spelling in [
+        "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.u4.s32\t{$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\\09{$0}, {$1}, {$2}, {$3};",
+        ";mma.sync.aligned.m16n8k32.row.col.s32.u4.u4.s32 {$0}, {$1}, {$2}, {$3};",
+        "prefix\\0Amma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32 {$0}, {$1}, {$2}, {$3};",
+        "@p mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32 {$0}, {$1}, {$2}, {$3};",
+        "@!%p\\09mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            contains_dense_int4_mma_features(spelling),
+            "missed {spelling:?}"
+        );
+    }
+
+    let representative = concat!(
+        "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32 ",
+        "{$0, $1, $2, $3}, {$4, $5, $6, $7}, {$8, $9}, {$10, $11, $12, $13};"
+    );
+    let requirements = detect_module_requirements_in_llvm_text(representative);
+    assert_eq!(
+        requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Ptx70,
+        }
+    );
+    assert_eq!(select_target(requirements.features).unwrap(), "sm_80");
+    assert_eq!(
+        required_ptx_feature("sm_75", requirements.ptx_isa).unwrap(),
+        Some("+ptx70")
+    );
+    assert_eq!(
+        required_ptx_feature("sm_80", requirements.ptx_isa).unwrap(),
+        None
+    );
+
+    let sm_75: CudaArch = "sm_75".parse().unwrap();
+    let sm_80: CudaArch = "sm_80".parse().unwrap();
+    assert!(validate_target_features(&sm_75, requirements.features).is_err());
+    assert!(validate_target_features(&sm_80, requirements.features).is_ok());
+    let error = resolve_ptx_target(
+        Some("sm_75"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        requirements.features,
+    )
+    .expect_err("sm_75 must not accept dense m16 INT4 MMA")
+    .to_string();
+    assert!(
+        error.contains("cannot lower detected feature Sm80"),
+        "{error}"
+    );
+
+    for target in [
+        "sm_80", "sm_86", "sm_89", "sm_90", "sm_90a", "sm_100", "sm_100a", "sm_120", "sm_120a",
+    ] {
+        assert!(
+            arch_satisfies(target, requirements.features),
+            "rejected {target}"
+        );
+    }
+
+    let m8_int4 = concat!(
+        "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32 ",
+        "{$0, $1}, {$4}, {$5}, {$2, $3};"
+    );
+    let mixed = format!("{representative}\n{m8_int4}");
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&mixed),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Sm75,
+            ptx_isa: PtxIsaRequirement::Ptx70,
+        }
+    );
+
+    let newer_ptx = format!("{representative}\nmovmatrix.sync.aligned.m8n8.trans.b16 $0, $1;");
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&newer_ptx),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+}
+
+#[test]
+fn dense_int4_mma_detection_rejects_other_mma_families_and_near_misses() {
+    for near_miss in [
+        "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k16.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k64.row.col.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
+        "mma.sp.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "wmma.mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.col.row.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k64.row.row.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32.satfinite {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k64.row.col.s32.satfinite.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.satfiniteX.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.u32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.s32.s4.u8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32x {$0}, {$1}, {$2}, {$3};",
+        "not_mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "$mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "%mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "@mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "!mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        ")mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            !contains_dense_int4_mma_features(near_miss),
+            "matched {near_miss:?}"
+        );
+    }
+}
+
+#[test]
+fn dense_b1_mma_detection_applies_exact_operation_floors() {
+    let cases = [
+        (
+            "m8n8k128",
+            "xor",
+            DetectedFeatures::Sm75,
+            PtxIsaRequirement::Ptx70,
+        ),
+        (
+            "m16n8k128",
+            "xor",
+            DetectedFeatures::Sm80,
+            PtxIsaRequirement::Ptx70,
+        ),
+        (
+            "m16n8k256",
+            "xor",
+            DetectedFeatures::Sm80,
+            PtxIsaRequirement::Ptx70,
+        ),
+        (
+            "m8n8k128",
+            "and",
+            DetectedFeatures::Sm80,
+            PtxIsaRequirement::Ptx71,
+        ),
+        (
+            "m16n8k128",
+            "and",
+            DetectedFeatures::Sm80,
+            PtxIsaRequirement::Ptx71,
+        ),
+        (
+            "m16n8k256",
+            "and",
+            DetectedFeatures::Sm80,
+            PtxIsaRequirement::Ptx71,
+        ),
+    ];
+
+    for (shape, operation, features, ptx_isa) in cases {
+        let spelling = format!(
+            "mma.sync.aligned.{shape}.row.col.s32.b1.b1.s32.{operation}.popc {{$0}}, {{$1}}, {{$2}}, {{$3}};"
+        );
+        assert_eq!(contains_b1_xor_mma_features(&spelling), operation == "xor");
+        assert_eq!(contains_b1_and_mma_features(&spelling), operation == "and");
+        assert_eq!(
+            contains_mma_m8n8k128_b1_xor_features(&spelling),
+            shape == "m8n8k128" && operation == "xor"
+        );
+        assert_eq!(
+            detect_module_requirements_in_llvm_text(&spelling),
+            ModuleRequirements { features, ptx_isa },
+            "{spelling}"
+        );
+    }
+
+    let m8_xor = concat!(
+        "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc ",
+        "{$0, $1}, {$4}, {$5}, {$2, $3};"
+    );
+    let m8_requirements = detect_module_requirements_in_llvm_text(m8_xor);
+    assert_eq!(select_target(m8_requirements.features).unwrap(), "sm_75");
+    assert_eq!(
+        required_ptx_feature("sm_75", m8_requirements.ptx_isa).unwrap(),
+        Some("+ptx70")
+    );
+
+    let m16_and = concat!(
+        "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc ",
+        "{$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};"
+    );
+    let and_requirements = detect_module_requirements_in_llvm_text(m16_and);
+    assert_eq!(select_target(and_requirements.features).unwrap(), "sm_80");
+    assert_eq!(
+        required_ptx_feature("sm_80", and_requirements.ptx_isa).unwrap(),
+        Some("+ptx71")
+    );
+    let sm_75: CudaArch = "sm_75".parse().unwrap();
+    let sm_80: CudaArch = "sm_80".parse().unwrap();
+    assert!(validate_target_features(&sm_75, and_requirements.features).is_err());
+    assert!(validate_target_features(&sm_80, and_requirements.features).is_ok());
+
+    let combined = format!("{m8_xor}\n{m16_and}");
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&combined),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Sm75,
+            ptx_isa: PtxIsaRequirement::Ptx71,
+        }
+    );
+}
+
+#[test]
+fn dense_b1_mma_detection_rejects_other_families_and_near_misses() {
+    for near_miss in [
+        "wmma.mma.xor.popc.sync.aligned.row.col.m8n8k128.s32.b1.b1.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k64.row.col.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k128.col.row.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.or.popc {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.popc.xor {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popcx {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc.satfinite {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.u32.xor.popc {$0}, {$1}, {$2}, {$3};",
+        "not_mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
+        "$mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
+        "%mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            !contains_b1_xor_mma_features(near_miss),
+            "matched {near_miss:?}"
+        );
+        assert!(
+            !contains_b1_and_mma_features(near_miss),
+            "matched {near_miss:?}"
+        );
+    }
+}
+
+#[test]
+fn generated_b1_floors_match_text_detection_on_both_backends() {
+    use crate::generated_intrinsic_targets::{
+        GeneratedIntrinsicBackend, generated_intrinsic_target_by_marker,
+    };
+
+    for (marker, mnemonic) in [
+        ("v1:i0157", B1_XOR_MMA_MNEMONICS[0]),
+        ("v1:i0158", B1_XOR_MMA_MNEMONICS[1]),
+        ("v1:i0159", B1_XOR_MMA_MNEMONICS[2]),
+        ("v1:i0160", B1_AND_MMA_MNEMONICS[0]),
+        ("v1:i0161", B1_AND_MMA_MNEMONICS[1]),
+        ("v1:i0162", B1_AND_MMA_MNEMONICS[2]),
+    ] {
+        let instruction = format!("{mnemonic} {{$0}}, {{$1}}, {{$2}}, {{$3}};");
+        let detected = detect_module_requirements_in_llvm_text(&instruction);
+        let target = generated_intrinsic_target_by_marker(marker).unwrap();
+        for backend in [
+            GeneratedIntrinsicBackend::LlvmNvptx,
+            GeneratedIntrinsicBackend::LibNvvm,
+        ] {
+            let generated =
+                GeneratedModuleRequirements::from_targets(vec![target]).for_backend(backend);
+            assert_eq!(
+                generated_ptx_isa_requirement(&generated).unwrap(),
+                detected.ptx_isa,
+                "{marker} {backend:?}"
+            );
+            for arch in ["sm_70", "sm_75", "sm_80", "sm_90"] {
+                assert_eq!(
+                    generated_target_satisfied(arch, &generated),
+                    arch_satisfies(arch, detected.features),
+                    "{marker} {backend:?} {arch}"
+                );
+            }
+        }
+    }
+}
+
+#[test]
+fn m8n8k16_int8_mma_detection_applies_exact_sm75_and_ptx65_floors() {
+    let mut forms = 0;
+    for a_type in ["s8", "u8"] {
+        for b_type in ["s8", "u8"] {
+            for satfinite in [false, true] {
+                let overflow = if satfinite { ".satfinite" } else { "" };
+                let spelling = format!(
+                    "mma.sync.aligned.m8n8k16.row.col{overflow}.s32.{a_type}.{b_type}.s32 {{$0, $1}}, {{$2}}, {{$3}}, {{$4, $5}};"
+                );
+                assert!(
+                    contains_mma_m8n8k16_int8_features(&spelling),
+                    "missed {spelling:?}"
+                );
+                assert!(
+                    !contains_dense_int8_mma_features(&spelling),
+                    "m8 form entered the m16 detector: {spelling:?}"
+                );
+                assert_eq!(
+                    detect_module_requirements_in_llvm_text(&spelling),
+                    ModuleRequirements {
+                        features: DetectedFeatures::Sm75,
+                        ptx_isa: PtxIsaRequirement::Ptx65,
+                    },
+                    "{spelling}"
+                );
+                forms += 1;
+            }
+        }
+    }
+    assert_eq!(forms, 8);
+
+    for spelling in [
+        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32\t{$0, $1}, {$2}, {$3}, {$4, $5};",
+        "mma.sync.aligned.m8n8k16.row.col.s32.u8.s8.s32\\09{$0, $1}, {$2}, {$3}, {$4, $5};",
+        ";mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "prefix\\0Amma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.u8.s32 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "@p mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "@!%p\\09mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32 {$0, $1}, {$2}, {$3}, {$4, $5};",
+    ] {
+        assert!(
+            contains_mma_m8n8k16_int8_features(spelling),
+            "missed {spelling:?}"
+        );
+    }
+
+    let representative = concat!(
+        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32 ",
+        "{$0, $1}, {$4}, {$5}, {$2, $3};"
+    );
+    let requirements = detect_module_requirements_in_llvm_text(representative);
+    let (target, _) = resolve_ptx_target(None, "CUDA_OXIDE_TARGET", None, requirements.features)
+        .expect("auto-resolve");
+    assert_eq!(target, "sm_75");
+    assert_eq!(
+        required_ptx_feature("sm_75", requirements.ptx_isa).unwrap(),
+        Some("+ptx65")
+    );
+    assert_eq!(
+        required_ptx_feature("sm_80", requirements.ptx_isa).unwrap(),
+        None
+    );
+
+    let sm_70: CudaArch = "sm_70".parse().unwrap();
+    let sm_75: CudaArch = "sm_75".parse().unwrap();
+    let sm_80: CudaArch = "sm_80".parse().unwrap();
+    assert!(validate_target_features(&sm_70, requirements.features).is_err());
+    assert!(validate_target_features(&sm_75, requirements.features).is_ok());
+    assert!(validate_target_features(&sm_80, requirements.features).is_ok());
+    let error = resolve_ptx_target(
+        Some("sm_70"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        requirements.features,
+    )
+    .expect_err("sm_70 must not accept m8n8k16 INT8 MMA")
+    .to_string();
+    assert!(
+        error.contains("cannot lower detected feature Sm75"),
+        "{error}"
+    );
+
+    for near_miss in [
+        "mma.sync.aligned.m8n8k8.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k16.col.row.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sp.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32x {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32.satfinite {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k16.row.col.satfiniteX.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s8.u32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k16.row.col.s32.s4.u8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k16.row.col.s32.u8.f16.s32 {$0}, {$1}, {$2}, {$3};",
+        "not_mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "$mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "%mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "@mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "!mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        ")mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            !contains_mma_m8n8k16_int8_features(near_miss),
+            "matched {near_miss:?}"
+        );
+    }
+
+    let m16 = concat!(
+        "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32 ",
+        "{$0, $1, $2, $3}, {$4, $5}, {$6}, {$7, $8, $9, $10};"
+    );
+    assert!(!contains_mma_m8n8k16_int8_features(m16));
+    assert!(contains_dense_int8_mma_features(m16));
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(m16),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Ptx70,
+        }
+    );
+
+    let combined = format!("{representative}\n{m16}");
+    let combined_requirements = detect_module_requirements_in_llvm_text(&combined);
+    assert_eq!(
+        combined_requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Sm75,
+            ptx_isa: PtxIsaRequirement::Ptx70,
+        }
+    );
+    let (target, _) = resolve_ptx_target(
+        None,
+        "CUDA_OXIDE_TARGET",
+        None,
+        combined_requirements.features,
+    )
+    .expect("combined m8 and m16 MMA should auto-resolve");
+    assert_eq!(target, "sm_80");
+}
+
+#[test]
+fn m8n8k32_int4_mma_detection_applies_exact_sm75_and_ptx65_floors() {
+    let mut forms = 0;
+    for a_type in ["s4", "u4"] {
+        for b_type in ["s4", "u4"] {
+            for satfinite in [false, true] {
+                let overflow = if satfinite { ".satfinite" } else { "" };
+                let spelling = format!(
+                    "mma.sync.aligned.m8n8k32.row.col{overflow}.s32.{a_type}.{b_type}.s32 {{$0, $1}}, {{$4}}, {{$5}}, {{$2, $3}};"
+                );
+                assert!(
+                    contains_mma_m8n8k32_int4_features(&spelling),
+                    "missed {spelling:?}"
+                );
+                assert!(
+                    !contains_mma_m8n8k16_int8_features(&spelling),
+                    "INT4 form entered the m8n8k16 detector: {spelling:?}"
+                );
+                assert!(
+                    !contains_dense_int8_mma_features(&spelling),
+                    "INT4 form entered the dense INT8 detector: {spelling:?}"
+                );
+                assert_eq!(
+                    detect_module_requirements_in_llvm_text(&spelling),
+                    ModuleRequirements {
+                        features: DetectedFeatures::Sm75,
+                        ptx_isa: PtxIsaRequirement::Ptx65,
+                    },
+                    "{spelling}"
+                );
+                forms += 1;
+            }
+        }
+    }
+    assert_eq!(forms, 8);
+
+    for spelling in [
+        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32\t{$0, $1}, {$4}, {$5}, {$2, $3};",
+        "mma.sync.aligned.m8n8k32.row.col.s32.u4.s4.s32\\09{$0, $1}, {$4}, {$5}, {$2, $3};",
+        ";mma.sync.aligned.m8n8k32.row.col.s32.u4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+        "prefix\\0Amma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+        "@p mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+        "@!%p\\09mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+    ] {
+        assert!(
+            contains_mma_m8n8k32_int4_features(spelling),
+            "missed {spelling:?}"
+        );
+    }
+
+    let representative = concat!(
+        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32 ",
+        "{$0, $1}, {$4}, {$5}, {$2, $3};"
+    );
+    let requirements = detect_module_requirements_in_llvm_text(representative);
+    assert_eq!(
+        requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm75,
+            ptx_isa: PtxIsaRequirement::Ptx65,
+        }
+    );
+    assert_eq!(select_target(requirements.features).unwrap(), "sm_75");
+    assert_eq!(
+        required_ptx_feature("sm_75", requirements.ptx_isa).unwrap(),
+        Some("+ptx65")
+    );
+    assert_eq!(
+        required_ptx_feature("sm_80", requirements.ptx_isa).unwrap(),
+        None
+    );
+
+    let sm_72: CudaArch = "sm_72".parse().unwrap();
+    let sm_75: CudaArch = "sm_75".parse().unwrap();
+    let sm_80: CudaArch = "sm_80".parse().unwrap();
+    assert!(validate_target_features(&sm_72, requirements.features).is_err());
+    assert!(validate_target_features(&sm_75, requirements.features).is_ok());
+    assert!(validate_target_features(&sm_80, requirements.features).is_ok());
+    let error = resolve_ptx_target(
+        Some("sm_72"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        requirements.features,
+    )
+    .expect_err("sm_72 must not accept m8n8k32 INT4 MMA")
+    .to_string();
+    assert!(
+        error.contains("cannot lower detected feature Sm75"),
+        "{error}"
+    );
+}
+
+#[test]
+fn m8n8k32_int4_mma_detection_rejects_near_misses() {
+    for near_miss in [
+        "mma.sync.aligned.m8n8k32.row.col.s32.s8.s8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k32.row.col.s32.b1.b1.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sp.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k32.col.row.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k32.row.row.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32.satfinite {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k32.row.col.s32.satfinite.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k32.row.col.satfiniteX.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.s4.u32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k32.row.col.s32.s4.u8.s32 {$0}, {$1}, {$2}, {$3};",
+        "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32x {$0}, {$1}, {$2}, {$3};",
+        "not_mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "$mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "%mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "@mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        "!mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+        ")mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0}, {$1}, {$2}, {$3};",
+    ] {
+        assert!(
+            !contains_mma_m8n8k32_int4_features(near_miss),
+            "matched {near_miss:?}"
+        );
+    }
+}
+
+#[test]
+fn m8n8k32_int4_mma_requirements_compose_and_are_forward_compatible() {
+    let int4 = concat!(
+        "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32 ",
+        "{$0, $1}, {$4}, {$5}, {$2, $3};"
+    );
+    let features = detect_features_in_llvm_text(int4);
+    for target in [
+        "sm_75", "sm_80", "sm_86", "sm_89", "sm_90", "sm_90a", "sm_100", "sm_100a", "sm_120",
+        "sm_120a",
+    ] {
+        assert!(arch_satisfies(target, features), "rejected {target}");
+    }
+    assert!(!arch_satisfies("sm_72", features));
+    assert_eq!(
+        resolve_ptx_target(None, "CUDA_OXIDE_TARGET", Some("sm_120"), features).unwrap(),
+        ("sm_120".to_string(), "detected GPU")
+    );
+
+    let m16_int8 = concat!(
+        "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 ",
+        "{$0, $1, $2, $3}, {$4, $5, $6, $7}, {$8, $9}, {$10, $11, $12, $13};"
+    );
+    let mixed = format!("{int4}\n{m16_int8}");
+    let mixed_requirements = detect_module_requirements_in_llvm_text(&mixed);
+    assert_eq!(
+        mixed_requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Sm75,
+            ptx_isa: PtxIsaRequirement::Ptx70,
+        }
+    );
+    assert_eq!(select_target(mixed_requirements.features).unwrap(), "sm_80");
+
+    let newer_ptx = format!("{int4}\nmovmatrix.sync.aligned.m8n8.trans.b16 $0, $1;");
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&newer_ptx),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm75 | DetectedFeatures::Movmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+}
+
+#[test]
+fn mma_m8n8k4_f64_detection_enforces_sm80_and_ptx70() {
+    let mnemonic = concat!(
+        "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 ",
+        "{$0, $1}, {$2}, {$3}, {$4, $5};"
+    );
+    for spelling in [
+        mnemonic,
+        "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\t{$0, $1}, {$2}, {$3}, {$4, $5};",
+        "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\n{$0, $1}, {$2}, {$3}, {$4, $5};",
+        "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\\09{$0, $1}, {$2}, {$3}, {$4, $5};",
+        "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\\0A{$0, $1}, {$2}, {$3}, {$4, $5};",
+        ";mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "prefix\\0Amma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "\"mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "{mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "$L:mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "/* comment */mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "@p mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "@!%p\\09mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+    ] {
+        assert!(contains_mma_m8n8k4_f64_features(spelling), "{spelling:?}");
+    }
+
+    let requirements = detect_module_requirements_in_llvm_text(mnemonic);
+    assert_eq!(
+        requirements,
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80,
+            ptx_isa: PtxIsaRequirement::Ptx70,
+        }
+    );
+    assert_eq!(select_target(requirements.features).unwrap(), "sm_80");
+
+    for near_miss in [
+        "mma.sync.aligned.m16n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "mma.sync.aligned.m8n8k4.col.row.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "mma.sync.aligned.m8n8k4.row.col.f32.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64x2 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64\\5C09{$0, $1}, {$2}, {$3}, {$4, $5};",
+        "not_mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "$mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "%mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "@mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "!mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "@!mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "not$mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        "/mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+        ")mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$2}, {$3}, {$4, $5};",
+    ] {
+        assert!(!contains_mma_m8n8k4_f64_features(near_miss));
+        assert_eq!(
+            detect_module_requirements_in_llvm_text(near_miss),
+            ModuleRequirements {
+                features: DetectedFeatures::Basic,
+                ptx_isa: PtxIsaRequirement::Default,
+            },
+            "matched near-miss {near_miss}"
+        );
+    }
+
+    let sm_75: CudaArch = "sm_75".parse().unwrap();
+    let sm_80: CudaArch = "sm_80".parse().unwrap();
+    assert!(validate_target_features(&sm_75, requirements.features).is_err());
+    assert!(validate_target_features(&sm_80, requirements.features).is_ok());
+    let error = resolve_ptx_target(
+        Some("sm_75"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        requirements.features,
+    )
+    .expect_err("sm_75 must not accept FP64 tensor-core MMA")
+    .to_string();
+    assert!(
+        error.contains("cannot lower detected feature Sm80"),
+        "{error}"
+    );
+
+    let combined = format!("{mnemonic}\nmovmatrix.sync.aligned.m8n8.trans.b16 $0, $1;");
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&combined),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+}
+
+#[test]
+fn test_movmatrix_detection_separates_sm75_from_the_ptx78_floor() {
+    let mnemonic = "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;";
+    for spelling in [
+        mnemonic,
+        "movmatrix.sync.aligned.m8n8.trans.b16\t$0, $1;",
+        "movmatrix.sync.aligned.m8n8.trans.b16\n$0, $1;",
+        "movmatrix.sync.aligned.m8n8.trans.b16\\09$0, $1;",
+        "movmatrix.sync.aligned.m8n8.trans.b16\\0A$0, $1;",
+        "movmatrix.sync.aligned.m8n8.trans.b16\\0D\\0A$0, $1;",
+    ] {
+        assert!(contains_movmatrix_features(spelling), "{spelling:?}");
+    }
+    assert_eq!(
+        detect_features_in_llvm_text(mnemonic),
+        DetectedFeatures::Movmatrix
+    );
+    assert_eq!(select_target(DetectedFeatures::Movmatrix).unwrap(), "sm_75");
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(mnemonic).ptx_isa,
+        PtxIsaRequirement::Ptx78
+    );
+
+    for near_miss in [
+        "movmatrix.sync.aligned.m8n8.b16 $0, $1;",
+        "movmatrix.sync.aligned.m16n8.trans.b16 $0, $1;",
+        "movmatrix.sync.aligned.m8n8.trans.b32 $0, $1;",
+        "movmatrix.sync.aligned.m8n8.trans.b16x2 $0, $1;",
+        "movmatrix.sync.aligned.m8n8.trans.b16\\5C09$0, $1;",
+    ] {
+        assert!(
+            !contains_movmatrix_features(near_miss),
+            "matched {near_miss}"
+        );
+        assert_eq!(
+            detect_module_requirements_in_llvm_text(near_miss),
+            ModuleRequirements {
+                features: DetectedFeatures::Basic,
+                ptx_isa: PtxIsaRequirement::Default,
+            }
+        );
+    }
+
+    let combined = format!("{mnemonic}\ncp.async.ca.shared.global [$0], [$1], 4;");
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&combined),
+        ModuleRequirements {
+            features: DetectedFeatures::Sm80 | DetectedFeatures::Movmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        },
+        "the architecture and PTX ISA floors must compose independently"
+    );
+
+    let sm_70: CudaArch = "sm_70".parse().unwrap();
+    let sm_75: CudaArch = "sm_75".parse().unwrap();
+    let sm_80: CudaArch = "sm_80".parse().unwrap();
+    assert!(validate_target_features(&sm_70, DetectedFeatures::Movmatrix).is_err());
+    assert!(validate_target_features(&sm_75, DetectedFeatures::Movmatrix).is_ok());
+    assert!(validate_target_features(&sm_80, DetectedFeatures::Movmatrix).is_ok());
+
+    for target in ["sm_75", "sm_80", "sm_86", "sm_87"] {
+        assert_eq!(
+            required_ptx_feature(target, PtxIsaRequirement::Ptx78).unwrap(),
+            Some("+ptx78"),
+            "{target} needs an explicit PTX 7.8 floor"
+        );
+    }
+    assert_eq!(
+        required_ptx_feature("sm_90", PtxIsaRequirement::Ptx78).unwrap(),
+        None
+    );
+    for target in ["sm_88", "sm_89"] {
+        assert_eq!(
+            required_ptx_feature(target, PtxIsaRequirement::Ptx78).unwrap(),
+            None,
+            "{target} already requires PTX 7.8 or newer"
+        );
+    }
+    assert_eq!(
+        required_ptx_feature("sm_75", PtxIsaRequirement::Default).unwrap(),
+        None
+    );
+}
+
+#[test]
+fn matrix_memory_detection_composes_architecture_and_ptx_isa_floors() {
+    let base_ldmatrix = "ldmatrix.sync.aligned.m8n8.x4.b16 {$0, $1, $2, $3}, [$4];";
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(base_ldmatrix),
+        ModuleRequirements {
+            features: DetectedFeatures::Ldmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx65,
+        }
+    );
+
+    let cta_ldmatrix = "ldmatrix.sync.aligned.m8n8.x1.shared::cta.b16 {$0}, [$1];";
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(cta_ldmatrix),
+        ModuleRequirements {
+            features: DetectedFeatures::Ldmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        }
+    );
+
+    for stmatrix in [
+        "stmatrix.sync.aligned.m8n8.x1.b16 [$0], {$1};",
+        "stmatrix.sync.aligned.m8n8.x4.trans.shared::cta.b16 [$0], {$1, $2, $3, $4};",
+    ] {
+        assert_eq!(
+            detect_module_requirements_in_llvm_text(stmatrix),
+            ModuleRequirements {
+                features: DetectedFeatures::Sm90,
+                ptx_isa: PtxIsaRequirement::Ptx78,
+            }
+        );
+    }
+
+    for newer in [
+        "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {$0, $1}, [$2];",
+        "ldmatrix.sync.aligned.m8n16.x2.shared::cta.b8x16.b6x16_p32 {$0, $1}, [$2];",
+        "stmatrix.sync.aligned.m16n8.x1.trans.shared.b8 [$0], {$1};",
+    ] {
+        assert_eq!(
+            detect_module_requirements_in_llvm_text(newer),
+            ModuleRequirements {
+                features: DetectedFeatures::MatrixBlackwell
+                    | if newer.starts_with("ldmatrix") {
+                        DetectedFeatures::Ldmatrix
+                    } else {
+                        DetectedFeatures::Sm90
+                    },
+                ptx_isa: PtxIsaRequirement::Ptx86,
+            },
+            "{newer}"
+        );
+    }
+
+    let mixed = format!(
+        "{base_ldmatrix}\n{}",
+        "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;"
+    );
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(&mixed),
+        ModuleRequirements {
+            features: DetectedFeatures::Movmatrix | DetectedFeatures::Ldmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx78,
+        },
+        "the strongest PTX ISA floor must survive equal sm_75 feature families"
+    );
+
+    assert_eq!(
+        required_ptx_feature("sm_75", PtxIsaRequirement::Ptx65).unwrap(),
+        Some("+ptx65")
+    );
+    assert_eq!(
+        required_ptx_feature("sm_80", PtxIsaRequirement::Ptx65).unwrap(),
+        None
+    );
+    assert_eq!(
+        required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx86).unwrap(),
+        None
+    );
+
+    let adjacent_unrelated_b8 = concat!(
+        "ldmatrix.sync.aligned.m8n8.x1.shared.b16 {$0}, [$1]; ",
+        "mov.b8 $2, $3;"
+    );
+    assert_eq!(
+        detect_module_requirements_in_llvm_text(adjacent_unrelated_b8),
+        ModuleRequirements {
+            features: DetectedFeatures::Ldmatrix,
+            ptx_isa: PtxIsaRequirement::Ptx65,
+        },
+        "an unrelated b8 instruction must not raise the ldmatrix family"
+    );
+}
diff --git a/crates/cuda-oxide-codegen/src/target/tests/fixtures.rs b/crates/cuda-oxide-codegen/src/target/tests/fixtures.rs
new file mode 100644
index 0000000000..e06a2abce7
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/tests/fixtures.rs
@@ -0,0 +1,189 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::generated_intrinsic_targets::{
+    GeneratedBackendRequirement, GeneratedHardwareAlternative, GeneratedHardwareTarget,
+    GeneratedIntrinsicBackend, GeneratedIntrinsicTarget, GeneratedIntrinsicVariant,
+    GeneratedPtxVersion, GeneratedTargetAlternative, GeneratedTargetContract,
+    GeneratedTargetRequirement, GeneratedTargetSelectorBinding,
+};
+
+static EXACT_SM120A: &[GeneratedHardwareAlternative] =
+    &[GeneratedHardwareAlternative::ExactArchitecture(120)];
+pub(super) static PTX87_EXACT_SM120A: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
+    marker: "test:ptx87",
+    id: "ptx87_exact_sm120a",
+    abi_id: "test",
+    dialect_op: "test.ptx87",
+    variant: GeneratedIntrinsicVariant::Scalar,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(87),
+        hardware: GeneratedHardwareTarget::AnyOf(EXACT_SM120A),
+    },
+    backend_requirements: &[],
+    selections: &[],
+    llvm: None,
+};
+pub(super) static PTX88: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
+    marker: "test:ptx88",
+    id: "ptx88",
+    abi_id: "test",
+    dialect_op: "test.ptx88",
+    variant: GeneratedIntrinsicVariant::Scalar,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+        hardware: GeneratedHardwareTarget::All,
+    },
+    backend_requirements: &[],
+    selections: &[],
+    llvm: None,
+};
+pub(super) static PTX90: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
+    marker: "test:ptx90",
+    id: "ptx90",
+    abi_id: "test",
+    dialect_op: "test.ptx90",
+    variant: GeneratedIntrinsicVariant::Scalar,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+        hardware: GeneratedHardwareTarget::All,
+    },
+    backend_requirements: &[],
+    selections: &[],
+    llvm: None,
+};
+pub(super) static PTX91_FUTURE: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
+    marker: "test:ptx91",
+    id: "ptx91_future",
+    abi_id: "test",
+    dialect_op: "test.ptx91",
+    variant: GeneratedIntrinsicVariant::Scalar,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(91),
+        hardware: GeneratedHardwareTarget::All,
+    },
+    backend_requirements: &[],
+    selections: &[],
+    llvm: None,
+};
+static TCGEN_F16_SELECTORS: &[GeneratedTargetSelectorBinding] = &[GeneratedTargetSelectorBinding {
+    name: "kind",
+    value: "f16",
+}];
+static TCGEN_F16_TARGETS: &[GeneratedTargetAlternative] = &[
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+        hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+    },
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+        hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+    },
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+        hardware: GeneratedHardwareAlternative::FamilyTarget(100),
+    },
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+        hardware: GeneratedHardwareAlternative::FamilyTarget(101),
+    },
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+        hardware: GeneratedHardwareAlternative::ExactArchitecture(103),
+    },
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+        hardware: GeneratedHardwareAlternative::FamilyTarget(103),
+    },
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+        hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+    },
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+        hardware: GeneratedHardwareAlternative::FamilyTarget(110),
+    },
+];
+static TCGEN_F16_CONTRACTS: &[GeneratedTargetContract] = &[GeneratedTargetContract {
+    selectors: TCGEN_F16_SELECTORS,
+    alternatives: TCGEN_F16_TARGETS,
+}];
+pub(super) static TCGEN_F16: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
+    marker: "test:tcgen_f16",
+    id: "tcgen_f16",
+    abi_id: "test",
+    dialect_op: "test.tcgen_f16",
+    variant: GeneratedIntrinsicVariant::Scalar,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+        hardware: GeneratedHardwareTarget::TargetMatrix {
+            contracts: TCGEN_F16_CONTRACTS,
+        },
+    },
+    backend_requirements: &[],
+    selections: &[],
+    llvm: None,
+};
+static TCGEN_I8_SELECTORS: &[GeneratedTargetSelectorBinding] = &[GeneratedTargetSelectorBinding {
+    name: "kind",
+    value: "i8",
+}];
+static TCGEN_I8_TARGETS: &[GeneratedTargetAlternative] = &[
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+        hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+    },
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+        hardware: GeneratedHardwareAlternative::ExactArchitecture(101),
+    },
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+        hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+    },
+];
+static TCGEN_I8_LIBNVVM_TARGETS: &[GeneratedTargetAlternative] = &[
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+        hardware: GeneratedHardwareAlternative::ExactArchitecture(100),
+    },
+    GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(90),
+        hardware: GeneratedHardwareAlternative::ExactArchitecture(110),
+    },
+];
+static TCGEN_I8_CONTRACTS: &[GeneratedTargetContract] = &[GeneratedTargetContract {
+    selectors: TCGEN_I8_SELECTORS,
+    alternatives: TCGEN_I8_TARGETS,
+}];
+static TCGEN_I8_LIBNVVM_CONTRACTS: &[GeneratedTargetContract] = &[GeneratedTargetContract {
+    selectors: TCGEN_I8_SELECTORS,
+    alternatives: TCGEN_I8_LIBNVVM_TARGETS,
+}];
+static TCGEN_I8_BACKENDS: &[GeneratedBackendRequirement] = &[GeneratedBackendRequirement {
+    backend: GeneratedIntrinsicBackend::LibNvvm,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+        hardware: GeneratedHardwareTarget::TargetMatrix {
+            contracts: TCGEN_I8_LIBNVVM_CONTRACTS,
+        },
+    },
+}];
+pub(super) static TCGEN_I8: GeneratedIntrinsicTarget = GeneratedIntrinsicTarget {
+    marker: "test:tcgen_i8",
+    id: "tcgen_i8",
+    abi_id: "test",
+    dialect_op: "test.tcgen_i8",
+    variant: GeneratedIntrinsicVariant::Scalar,
+    requirement: GeneratedTargetRequirement {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(86),
+        hardware: GeneratedHardwareTarget::TargetMatrix {
+            contracts: TCGEN_I8_CONTRACTS,
+        },
+    },
+    backend_requirements: TCGEN_I8_BACKENDS,
+    selections: &[],
+    llvm: None,
+};
diff --git a/crates/cuda-oxide-codegen/src/target/tests/generated_floors.rs b/crates/cuda-oxide-codegen/src/target/tests/generated_floors.rs
new file mode 100644
index 0000000000..8e1fe3c1ca
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/tests/generated_floors.rs
@@ -0,0 +1,697 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::fixtures::{PTX87_EXACT_SM120A, PTX88, PTX90, PTX91_FUTURE, TCGEN_F16, TCGEN_I8};
+use crate::generated::GeneratedModuleRequirements;
+use crate::generated_intrinsic_targets::{
+    GeneratedHardwareAlternative, GeneratedHardwareTarget, GeneratedIntrinsicBackend,
+    GeneratedPtxVersion, GeneratedTargetAlternative, GeneratedTargetContract,
+};
+use crate::target::arch::*;
+use crate::target::detect::*;
+use crate::target::features::*;
+use crate::target::generated_requirements::*;
+use crate::target::select::*;
+use cuda_target_spec::{PTX_ISA_SPELLINGS, RECORDED_PTX_FLOORS};
+use libnvvm_sys::CudaArch;
+
+#[test]
+fn paired_target_floors_compose_with_target_cpu_minima() {
+    let generated = GeneratedModuleRequirements::from_targets(vec![&TCGEN_F16]);
+
+    assert_eq!(
+        generated_ptx_isa_requirement(&generated).unwrap(),
+        PtxIsaRequirement::Ptx86
+    );
+    for target in ["sm_100a", "sm_101a", "sm_103a", "sm_110a"] {
+        assert!(generated_target_satisfied(target, &generated), "{target}");
+    }
+    for (target, requirement) in [
+        ("sm_100a", PtxIsaRequirement::Ptx86),
+        ("sm_101a", PtxIsaRequirement::Ptx86),
+        ("sm_103a", PtxIsaRequirement::Ptx88),
+        ("sm_110a", PtxIsaRequirement::Ptx90),
+    ] {
+        assert_eq!(
+            generated_ptx_isa_requirement_for_target(&generated, target).unwrap(),
+            requirement
+        );
+        assert_eq!(required_ptx_feature(target, requirement).unwrap(), None);
+    }
+    assert_eq!(
+        generated_requirement_ptx_floor("sm_103a", TCGEN_F16.requirement),
+        Some(88)
+    );
+    assert_eq!(
+        generated_requirement_ptx_floor("sm_110a", TCGEN_F16.requirement),
+        Some(90)
+    );
+    for target in ["sm_120a", "sm_121a"] {
+        assert!(!generated_target_satisfied(target, &generated), "{target}");
+    }
+    for target in ["sm_100f", "sm_101f", "sm_103f", "sm_110f"] {
+        assert!(generated_target_satisfied(target, &generated), "{target}");
+    }
+    assert_eq!(
+        select_target_with_generated(DetectedFeatures::Basic, &generated).unwrap(),
+        "sm_100a"
+    );
+
+    let generated = GeneratedModuleRequirements::from_targets(vec![&TCGEN_I8]);
+    assert_eq!(
+        generated_ptx_isa_requirement(&generated).unwrap(),
+        PtxIsaRequirement::Ptx86
+    );
+    assert_eq!(
+        generated_ptx_isa_requirement_for_target(&generated, "sm_100a").unwrap(),
+        PtxIsaRequirement::Ptx86
+    );
+    assert_eq!(
+        required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx86).unwrap(),
+        None
+    );
+    for (target, requirement) in [
+        ("sm_101a", PtxIsaRequirement::Ptx86),
+        ("sm_110a", PtxIsaRequirement::Ptx90),
+    ] {
+        assert_eq!(
+            generated_ptx_isa_requirement_for_target(&generated, target).unwrap(),
+            requirement
+        );
+        assert_eq!(required_ptx_feature(target, requirement).unwrap(), None);
+    }
+    assert!(!generated_target_satisfied("sm_103a", &generated));
+    assert!(!generated_target_satisfied("sm_100f", &generated));
+}
+
+#[test]
+fn sm101_aliases_reject_an_aggregate_ptx90_requirement() {
+    let generated = GeneratedModuleRequirements::from_targets(vec![&TCGEN_F16, &PTX90]);
+
+    for target in ["sm_101a", "sm_101f"] {
+        let error = generated_ptx_isa_requirement_for_target(&generated, target).unwrap_err();
+        assert!(
+            error.contains("renamed the sm_101 target to sm_110"),
+            "{error}"
+        );
+
+        let f16 = GeneratedModuleRequirements::from_targets(vec![&TCGEN_F16]);
+        let text = ModuleRequirements {
+            features: DetectedFeatures::Basic,
+            ptx_isa: PtxIsaRequirement::Ptx90,
+        };
+        let error = merge_generated_module_requirements_for_target(text, &f16, target).unwrap_err();
+        assert!(
+            error.contains("renamed the sm_101 target to sm_110"),
+            "{error}"
+        );
+    }
+}
+
+#[test]
+fn dynamic_stack_calls_require_ptx73_and_sm52() {
+    for llvm in [
+        "%saved = call ptr @llvm.stacksave.p0()\n",
+        "%saved = tail call ptr addrspace(12) @llvm.stacksave.p12()\n",
+        "call void @llvm.stackrestore.p3(ptr addrspace(3) %saved)\n",
+        "%saved = call i8* @llvm.stacksave()\n",
+        "call void @llvm.stackrestore(i8* %saved)\n",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(llvm);
+        assert!(
+            requirements
+                .features
+                .contains(DetectedFeatures::DynamicStack),
+            "{llvm}"
+        );
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Ptx73, "{llvm}");
+    }
+
+    for near_match in [
+        "%saved = call ptr @llvm.stacksavex.p0()\n",
+        "%saved = call ptr @llvm.stacksave_extra.p0()\n",
+        "%saved = call ptr @llvm.stacksave.p()\n",
+        "%saved = call ptr @llvm.stacksave.p0x()\n",
+        "%saved = call ptr @llvm.stacksave.p0.extra()\n",
+        "call void @llvm.stackrestorex.p0(ptr %saved)\n",
+        "call void @llvm.stackrestore.p0_extra(ptr %saved)\n",
+        "%saved = call ptr @llvm.stacksave.p0\n",
+    ] {
+        let requirements = detect_module_requirements_in_llvm_text(near_match);
+        assert_eq!(
+            requirements.features,
+            DetectedFeatures::Basic,
+            "{near_match}"
+        );
+        assert_eq!(
+            requirements.ptx_isa,
+            PtxIsaRequirement::Default,
+            "{near_match}"
+        );
+    }
+
+    assert!(!arch_satisfies_feature(
+        50,
+        None,
+        DetectedFeatures::DynamicStack
+    ));
+    assert!(arch_satisfies_feature(
+        52,
+        None,
+        DetectedFeatures::DynamicStack
+    ));
+    for target in ["sm_70", "sm_86"] {
+        let parsed = target.parse::<CudaArch>().unwrap();
+        assert!(
+            validate_target_features(&parsed, DetectedFeatures::DynamicStack).is_ok(),
+            "{target}"
+        );
+    }
+    let sm_50 = "sm_50".parse::<CudaArch>().unwrap();
+    let error = validate_target_features(&sm_50, DetectedFeatures::DynamicStack).unwrap_err();
+    assert!(error.contains("DynamicStack"), "{error}");
+}
+
+#[test]
+fn dynamic_stack_mentions_without_calls_do_not_raise_requirements() {
+    let non_calls = [
+        "declare ptr @llvm.stacksave.p0()\n",
+        "declare void @llvm.stackrestore.p0(ptr)\n",
+        "; %saved = call ptr @llvm.stacksave.p0()\n",
+        "!0 = !{!\"call ptr @llvm.stacksave.p0()\"}\n",
+        "@message = private constant [39 x i8] c\"call ptr @llvm.stacksave.p0()\\00\"\n",
+        "!1 = !{ptr @llvm.stacksave.p0}\n",
+        "declare ptr @llvm.stacksave.p0 ; call ptr @llvm.stacksave.p0()\n",
+    ];
+
+    for llvm in non_calls {
+        let requirements = detect_module_requirements_in_llvm_text(llvm);
+        assert_eq!(requirements.features, DetectedFeatures::Basic, "{llvm}");
+        assert_eq!(requirements.ptx_isa, PtxIsaRequirement::Default, "{llvm}");
+    }
+
+    let call_after_quoted_semicolon = concat!(
+        "@message = private constant [2 x i8] c\";\\00\"\n",
+        "%saved = call ptr @llvm.stacksave.p0() ; ignored comment\n",
+    );
+    assert!(
+        detect_module_requirements_in_llvm_text(call_after_quoted_semicolon)
+            .features
+            .contains(DetectedFeatures::DynamicStack)
+    );
+}
+
+#[test]
+fn ptx73_feature_is_requested_only_when_the_target_default_is_older() {
+    assert_eq!(
+        ptx_isa_requirement_for_floor(72, "test", "test").unwrap(),
+        PtxIsaRequirement::Ptx73
+    );
+    assert_eq!(
+        ptx_isa_requirement_for_floor(73, "test", "test").unwrap(),
+        PtxIsaRequirement::Ptx73
+    );
+    assert_eq!(
+        ptx_isa_requirement_for_floor(74, "test", "test").unwrap(),
+        PtxIsaRequirement::Ptx78
+    );
+    for target in ["sm_70", "sm_80", "sm_86"] {
+        assert_eq!(
+            required_ptx_feature(target, PtxIsaRequirement::Ptx73).unwrap(),
+            Some("+ptx73"),
+            "{target}"
+        );
+    }
+    assert_eq!(
+        required_ptx_feature("sm_87", PtxIsaRequirement::Ptx73).unwrap(),
+        None
+    );
+}
+
+#[test]
+fn every_shared_ptx_spelling_round_trips() {
+    for spelling in PTX_ISA_SPELLINGS {
+        let requirement = PtxIsaRequirement::from_spelling(*spelling).unwrap();
+        assert_eq!(requirement.spelling(), Some(*spelling));
+        assert!(requirement.feature().is_some());
+    }
+}
+
+#[test]
+fn selection_candidates_cover_exactly_the_recorded_target_set() {
+    let candidates = KNOWN_CUDA_TARGET_CANDIDATES
+        .iter()
+        .copied()
+        .collect::<std::collections::BTreeSet<_>>();
+    let recorded = RECORDED_PTX_FLOORS
+        .iter()
+        .map(|entry| match entry.suffix {
+            Some(suffix) => format!("sm_{}{suffix}", entry.capability),
+            None => format!("sm_{}", entry.capability),
+        })
+        .collect::<std::collections::BTreeSet<_>>();
+    assert_eq!(
+        candidates,
+        recorded.iter().map(String::as_str).collect(),
+        "selection preference list and shared recorded-floor keys drifted"
+    );
+}
+
+#[test]
+fn unrecorded_target_fails_closed_for_explicit_ptx() {
+    let error = required_ptx_feature("sm_89a", PtxIsaRequirement::Ptx80).unwrap_err();
+    assert!(error.contains("no recorded PTX ISA floor"));
+    let error = required_ptx_feature("sm_999a", PtxIsaRequirement::Default).unwrap_err();
+    assert!(error.contains("no recorded PTX ISA floor"));
+}
+
+#[test]
+fn paired_minimum_target_diagnostic_preserves_range_meaning() {
+    static TARGETS: &[GeneratedTargetAlternative] = &[GeneratedTargetAlternative {
+        minimum_ptx: GeneratedPtxVersion::from_encoded(88),
+        hardware: GeneratedHardwareAlternative::MinimumSm(100),
+    }];
+    static CONTRACTS: &[GeneratedTargetContract] = &[GeneratedTargetContract {
+        selectors: &[],
+        alternatives: TARGETS,
+    }];
+
+    assert_eq!(
+        describe_generated_hardware(GeneratedHardwareTarget::TargetMatrix {
+            contracts: CONTRACTS,
+        }),
+        "sm_100 or newer at PTX 8.8"
+    );
+}
+
+#[test]
+fn paired_target_matrix_flows_through_backend_target_resolution() {
+    let llvm = GeneratedModuleRequirements::from_targets(vec![&TCGEN_I8])
+        .for_backend(GeneratedIntrinsicBackend::LlvmNvptx);
+    let libnvvm = GeneratedModuleRequirements::from_targets(vec![&TCGEN_I8])
+        .for_backend(GeneratedIntrinsicBackend::LibNvvm);
+
+    assert!(generated_target_satisfied("sm_101a", &llvm));
+    assert!(!generated_target_satisfied("sm_101a", &libnvvm));
+    assert!(!generated_target_satisfied("sm_103a", &llvm));
+    assert!(generated_target_satisfied("sm_110a", &libnvvm));
+
+    assert_eq!(
+        resolve_ptx_target_with_generated(
+            Some("sm_101a"),
+            "CUDA_OXIDE_TARGET",
+            None,
+            DetectedFeatures::Basic,
+            &llvm,
+        )
+        .unwrap(),
+        ("sm_101a".into(), "CUDA_OXIDE_TARGET")
+    );
+    assert!(
+        resolve_ptx_target_with_generated(
+            Some("sm_103a"),
+            "CUDA_OXIDE_TARGET",
+            None,
+            DetectedFeatures::Basic,
+            &llvm,
+        )
+        .is_err()
+    );
+    assert_eq!(
+        resolve_ptx_target_with_generated(
+            None,
+            "CUDA_OXIDE_TARGET",
+            Some("sm_101a"),
+            DetectedFeatures::Basic,
+            &llvm,
+        )
+        .unwrap(),
+        ("sm_101a".into(), "detected GPU")
+    );
+    assert_eq!(
+        resolve_ptx_target_with_generated(
+            None,
+            "CUDA_OXIDE_TARGET",
+            Some("sm_101a"),
+            DetectedFeatures::Basic,
+            &libnvvm,
+        )
+        .unwrap(),
+        ("sm_100a".into(), "feature requirement")
+    );
+    assert_eq!(
+        resolve_ptx_target_with_generated(
+            None,
+            "CUDA_OXIDE_TARGET",
+            None,
+            DetectedFeatures::Basic,
+            &llvm
+        )
+        .unwrap(),
+        ("sm_100a".into(), "feature requirement")
+    );
+
+    let base = ModuleRequirements {
+        features: DetectedFeatures::Basic,
+        ptx_isa: PtxIsaRequirement::Default,
+    };
+    assert_eq!(
+        merge_generated_module_requirements_for_target(base, &llvm, "sm_101a")
+            .unwrap()
+            .ptx_isa,
+        PtxIsaRequirement::Ptx86
+    );
+    assert_eq!(
+        merge_generated_module_requirements_for_target(base, &llvm, "sm_110a")
+            .unwrap()
+            .ptx_isa,
+        PtxIsaRequirement::Ptx90
+    );
+
+    let error =
+        crate::export::resolve_nvvm_target_with_generated(Some("sm_103a"), None, None, &libnvvm)
+            .unwrap_err()
+            .to_string();
+    assert!(error.contains("tcgen_i8"), "{error}");
+    assert_eq!(
+        crate::export::resolve_nvvm_target_with_generated(Some("sm_110a"), None, None, &libnvvm,)
+            .unwrap()
+            .sm(),
+        "sm_110a"
+    );
+    assert_eq!(
+        crate::export::resolve_nvvm_target_with_generated(None, Some("sm_103a"), None, &libnvvm,)
+            .unwrap()
+            .sm(),
+        "sm_100a"
+    );
+}
+
+#[test]
+fn generated_ptx87_exact_sm120a_requirement_is_preserved() {
+    let generated = GeneratedModuleRequirements::from_targets(vec![&PTX87_EXACT_SM120A]);
+
+    assert_eq!(
+        generated_ptx_isa_requirement(&generated).unwrap(),
+        PtxIsaRequirement::Ptx87
+    );
+    assert!(PtxIsaRequirement::Ptx86 < PtxIsaRequirement::Ptx87);
+    assert_eq!(
+        required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx87).unwrap(),
+        Some("+ptx87")
+    );
+    assert_eq!(
+        required_ptx_feature("sm_120a", PtxIsaRequirement::Ptx87).unwrap(),
+        None
+    );
+    assert_eq!(
+        required_ptx_feature("sm_100f", PtxIsaRequirement::Ptx87).unwrap(),
+        None
+    );
+    assert_eq!(
+        required_ptx_feature("sm_120f", PtxIsaRequirement::Ptx87).unwrap(),
+        None
+    );
+    assert_eq!(
+        select_target_with_generated(DetectedFeatures::Basic, &generated).unwrap(),
+        "sm_120a"
+    );
+    assert!(generated_target_satisfied("sm_120a", &generated));
+    for incompatible in ["sm_120", "sm_120f", "sm_121a"] {
+        assert!(
+            !generated_target_satisfied(incompatible, &generated),
+            "{incompatible}"
+        );
+    }
+}
+
+#[test]
+fn generated_ptx88_and_ptx90_floors_are_preserved() {
+    let generated = GeneratedModuleRequirements::from_targets(vec![&PTX88]);
+    assert_eq!(
+        generated_ptx_isa_requirement(&generated).unwrap(),
+        PtxIsaRequirement::Ptx88
+    );
+    assert_eq!(
+        required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx88).unwrap(),
+        Some("+ptx88")
+    );
+    assert_eq!(
+        required_ptx_feature("sm_103a", PtxIsaRequirement::Ptx88).unwrap(),
+        None
+    );
+    assert_eq!(
+        ptx_isa_requirement_for_floor(89, "test", "test").unwrap(),
+        PtxIsaRequirement::Ptx90
+    );
+    assert_eq!(
+        required_ptx_feature("sm_100a", PtxIsaRequirement::Ptx90).unwrap(),
+        Some("+ptx90")
+    );
+    assert_eq!(
+        required_ptx_feature("sm_110a", PtxIsaRequirement::Ptx90).unwrap(),
+        None
+    );
+    validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx87, Some(21)).unwrap();
+    validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx88, None).unwrap();
+    validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx88, Some(21)).unwrap();
+    validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx88, Some(22)).unwrap();
+    assert!(validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx90, None).is_err());
+    assert!(validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx90, Some(21)).is_err());
+    validate_ptx_isa_for_llvm_major(PtxIsaRequirement::Ptx90, Some(22)).unwrap();
+
+    let generated = GeneratedModuleRequirements::from_targets(vec![&PTX91_FUTURE]);
+    let error = generated_ptx_isa_requirement(&generated).unwrap_err();
+
+    assert!(error.contains("requires PTX 9.1"), "{error}");
+    assert!(
+        error.contains("newer than cuda-oxide can request"),
+        "{error}"
+    );
+}
+
+#[test]
+fn generated_redux_floor_matches_the_lowered_ptx_detector() {
+    use crate::generated_intrinsic_targets::generated_intrinsic_target_by_marker;
+
+    let target = generated_intrinsic_target_by_marker("v1:i0017").unwrap();
+    let generated = GeneratedModuleRequirements::from_targets(vec![target]);
+    let detected = detect_module_requirements_in_llvm_text("redux.sync.add.s32 $0, $1, $2;");
+
+    assert_eq!(
+        generated_ptx_isa_requirement(&generated).unwrap(),
+        detected.ptx_isa
+    );
+    assert_eq!(detected.ptx_isa, PtxIsaRequirement::Ptx70);
+    assert!(detected.features.contains(DetectedFeatures::Sm80));
+    for arch in ["sm_75", "sm_80", "sm_90"] {
+        assert_eq!(
+            generated_target_satisfied(arch, &generated),
+            arch_satisfies(arch, detected.features),
+            "{arch}"
+        );
+    }
+}
+
+#[test]
+fn generated_packed_atomic_floors_are_backend_specific() {
+    use crate::generated_intrinsic_targets::{
+        GeneratedIntrinsicBackend, generated_intrinsic_target_by_marker,
+    };
+
+    let f16 = generated_intrinsic_target_by_marker("v1:i0014").unwrap();
+    let llvm = GeneratedModuleRequirements::from_targets(vec![f16])
+        .for_backend(GeneratedIntrinsicBackend::LlvmNvptx);
+    assert!(generated_target_satisfied("sm_70", &llvm));
+    assert_eq!(
+        generated_ptx_isa_requirement(&llvm).unwrap(),
+        PtxIsaRequirement::Ptx62
+    );
+
+    let libnvvm = GeneratedModuleRequirements::from_targets(vec![f16])
+        .for_backend(GeneratedIntrinsicBackend::LibNvvm);
+    assert!(!generated_target_satisfied("sm_70", &libnvvm));
+    assert!(generated_target_satisfied("sm_75", &libnvvm));
+
+    let bf16 = generated_intrinsic_target_by_marker("v1:i0015").unwrap();
+    let bf16 = GeneratedModuleRequirements::from_targets(vec![bf16]);
+    assert!(!generated_target_satisfied("sm_89", &bf16));
+    assert!(generated_target_satisfied("sm_90", &bf16));
+    let error = resolve_ptx_target_with_generated(
+        Some("sm_89"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        DetectedFeatures::Basic,
+        &bf16,
+    )
+    .unwrap_err()
+    .to_string();
+    assert!(error.contains("packed_atomic_add_bf16x2"), "{error}");
+    assert!(error.contains("sm_90 or newer"), "{error}");
+}
+
+#[test]
+fn generated_non_mma_tcgen05_targets_preserve_the_backend_split() {
+    use crate::generated_intrinsic_targets::{
+        GeneratedIntrinsicBackend, GeneratedIntrinsicVariant, generated_intrinsic_targets,
+    };
+
+    let targets = generated_intrinsic_targets()
+        .filter(|target| {
+            target.id.starts_with("tcgen05_")
+                && !matches!(target.variant, GeneratedIntrinsicVariant::Tcgen05Mma { .. })
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(targets.len(), 209);
+
+    for target in targets {
+        let llvm = GeneratedModuleRequirements::from_targets(vec![target])
+            .for_backend(GeneratedIntrinsicBackend::LlvmNvptx);
+        let libnvvm = GeneratedModuleRequirements::from_targets(vec![target])
+            .for_backend(GeneratedIntrinsicBackend::LibNvvm);
+
+        assert_eq!(
+            generated_ptx_isa_requirement(&llvm).unwrap(),
+            PtxIsaRequirement::Ptx86,
+            "{}",
+            target.id
+        );
+        assert_eq!(
+            generated_ptx_isa_requirement(&libnvvm).unwrap(),
+            PtxIsaRequirement::Ptx86,
+            "{}",
+            target.id
+        );
+        for arch in ["sm_100a", "sm_103a", "sm_110a"] {
+            assert!(
+                generated_target_satisfied(arch, &llvm),
+                "{} {arch}",
+                target.id
+            );
+            assert!(
+                generated_target_satisfied(arch, &libnvvm),
+                "{} {arch}",
+                target.id
+            );
+        }
+        assert!(
+            generated_target_satisfied("sm_101a", &llvm),
+            "{}",
+            target.id
+        );
+        assert!(
+            !generated_target_satisfied("sm_101a", &libnvvm),
+            "{}",
+            target.id
+        );
+        assert!(
+            !generated_target_satisfied("sm_120a", &llvm),
+            "{}",
+            target.id
+        );
+        assert!(
+            !generated_target_satisfied("sm_120a", &libnvvm),
+            "{}",
+            target.id
+        );
+    }
+}
+
+#[test]
+fn generated_packed_conversion_floors_require_ampere() {
+    use crate::generated_intrinsic_targets::{
+        GeneratedIntrinsicBackend, generated_intrinsic_target_by_marker,
+    };
+
+    for marker in [
+        "v1:i0071", "v1:i0081", "v1:i0082", "v1:i0083", "v1:i0084", "v1:i0085",
+    ] {
+        let target = generated_intrinsic_target_by_marker(marker).unwrap();
+        for backend in [
+            GeneratedIntrinsicBackend::LlvmNvptx,
+            GeneratedIntrinsicBackend::LibNvvm,
+        ] {
+            let generated =
+                GeneratedModuleRequirements::from_targets(vec![target]).for_backend(backend);
+            assert_eq!(
+                generated_ptx_isa_requirement(&generated).unwrap(),
+                PtxIsaRequirement::Ptx70,
+                "{marker} {backend:?}"
+            );
+            assert!(!generated_target_satisfied("sm_75", &generated), "{marker}");
+            assert!(generated_target_satisfied("sm_80", &generated), "{marker}");
+            let error = validate_generated_target("sm_75", &generated).unwrap_err();
+            assert!(error.contains(target.id), "{error}");
+            assert!(error.contains("sm_80 or newer"), "{error}");
+        }
+    }
+}
+
+#[test]
+fn generated_cp_async_floors_require_ampere() {
+    use crate::generated_intrinsic_targets::{
+        GeneratedIntrinsicBackend, generated_intrinsic_target_by_marker,
+    };
+
+    for marker in [
+        "v1:i0086", "v1:i0087", "v1:i0088", "v1:i0089", "v1:i0090", "v1:i0091", "v1:i0092",
+        "v1:i0093", "v1:i0094", "v1:i0095", "v1:i0096", "v1:i0101", "v1:i0102", "v1:i0103",
+        "v1:i0104",
+    ] {
+        let target = generated_intrinsic_target_by_marker(marker).unwrap();
+        for backend in [
+            GeneratedIntrinsicBackend::LlvmNvptx,
+            GeneratedIntrinsicBackend::LibNvvm,
+        ] {
+            let generated =
+                GeneratedModuleRequirements::from_targets(vec![target]).for_backend(backend);
+            assert_eq!(
+                generated_ptx_isa_requirement(&generated).unwrap(),
+                PtxIsaRequirement::Ptx70,
+                "{marker} {backend:?}"
+            );
+            assert!(!generated_target_satisfied("sm_75", &generated), "{marker}");
+            assert!(generated_target_satisfied("sm_80", &generated), "{marker}");
+            let error = validate_generated_target("sm_75", &generated).unwrap_err();
+            assert!(error.contains(target.id), "{error}");
+            assert!(error.contains("sm_80 or newer"), "{error}");
+        }
+    }
+}
+
+#[test]
+fn generated_dot_product_floors_record_sm61_and_split_backend_support() {
+    use crate::generated_intrinsic_targets::{
+        GeneratedIntrinsicBackend, generated_intrinsic_target_by_marker,
+    };
+
+    for marker in ["v1:i0030", "v1:i0031", "v1:i0032", "v1:i0033"] {
+        let target = generated_intrinsic_target_by_marker(marker).unwrap();
+        let llvm = GeneratedModuleRequirements::from_targets(vec![target])
+            .for_backend(GeneratedIntrinsicBackend::LlvmNvptx);
+        assert!(matches!(
+            llvm.requirement(target).hardware,
+            GeneratedHardwareTarget::AnyOf(alternatives)
+                if alternatives == [GeneratedHardwareAlternative::MinimumSm(61)]
+        ));
+        assert!(!generated_target_satisfied("sm_60", &llvm), "{marker}");
+        assert!(generated_target_satisfied("sm_70", &llvm), "{marker}");
+        assert_eq!(
+            generated_ptx_isa_requirement(&llvm).unwrap(),
+            PtxIsaRequirement::Default
+        );
+
+        let error = validate_generated_target("sm_60", &llvm)
+            .unwrap_err()
+            .to_string();
+        assert!(error.contains(target.id), "{error}");
+        assert!(error.contains("sm_61 or newer"), "{error}");
+
+        let libnvvm = GeneratedModuleRequirements::from_targets(vec![target])
+            .for_backend(GeneratedIntrinsicBackend::LibNvvm);
+        assert!(!generated_target_satisfied("sm_74", &libnvvm));
+        assert!(generated_target_satisfied("sm_75", &libnvvm));
+    }
+}
diff --git a/crates/cuda-oxide-codegen/src/target/tests/mod.rs b/crates/cuda-oxide-codegen/src/target/tests/mod.rs
new file mode 100644
index 0000000000..b2700da279
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/tests/mod.rs
@@ -0,0 +1,10 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+mod detection_async_memory;
+mod detection_matrix;
+mod fixtures;
+mod generated_floors;
+mod selection;
diff --git a/crates/cuda-oxide-codegen/src/target/tests/selection.rs b/crates/cuda-oxide-codegen/src/target/tests/selection.rs
new file mode 100644
index 0000000000..70218faf49
--- /dev/null
+++ b/crates/cuda-oxide-codegen/src/target/tests/selection.rs
@@ -0,0 +1,355 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use crate::error::PipelineError;
+use crate::target::arch::*;
+use crate::target::detect::*;
+use crate::target::features::*;
+use crate::target::select::*;
+use cuda_target_spec::recorded_ptx_floor;
+
+#[test]
+fn test_select_target_prefers_required_architecture() {
+    for (features, expected) in [
+        (DetectedFeatures::Blackwell, "sm_100a"),
+        (DetectedFeatures::TmaCtaGroup, "sm_100a"),
+        (DetectedFeatures::BlackwellAccelerated, "sm_100a"),
+        (DetectedFeatures::BlackwellFamily, "sm_100a"),
+        (DetectedFeatures::ReduxF32, "sm_100a"),
+        (DetectedFeatures::MultimemFp8, "sm_100a"),
+        (DetectedFeatures::TmaMulticast, "sm_100a"),
+        (DetectedFeatures::MatrixBlackwell, "sm_100a"),
+        (DetectedFeatures::Wgmma, "sm_90a"),
+        (DetectedFeatures::Sm100, "sm_100"),
+        (DetectedFeatures::Tma, "sm_100"),
+        (DetectedFeatures::Cluster, "sm_90"),
+        (DetectedFeatures::Sm90, "sm_90"),
+        (DetectedFeatures::Sm80, "sm_80"),
+        (DetectedFeatures::Movmatrix, "sm_75"),
+        (DetectedFeatures::Ldmatrix, "sm_75"),
+        (DetectedFeatures::Basic, "sm_80"),
+    ] {
+        assert_eq!(select_target(features).unwrap(), expected, "{features:?}");
+    }
+}
+
+#[test]
+fn target_selection_enforces_feature_intersections() {
+    let multicast = "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster";
+    let hopper_pair = format!("{multicast};\nwgmma.fence.sync.aligned;");
+    let hopper_requirements = detect_features_in_llvm_text(&hopper_pair);
+    assert!(hopper_requirements.contains(DetectedFeatures::TmaMulticast));
+    assert!(hopper_requirements.contains(DetectedFeatures::Wgmma));
+    assert_eq!(select_target(hopper_requirements).unwrap(), "sm_90a");
+    assert!(arch_satisfies("sm_90a", hopper_requirements));
+    assert!(!arch_satisfies("sm_100a", hopper_requirements));
+
+    let blackwell_pair = format!(
+        "{multicast};\n{}",
+        "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {$0, $1}, [$2];"
+    );
+    let blackwell_requirements = detect_features_in_llvm_text(&blackwell_pair);
+    assert!(blackwell_requirements.contains(DetectedFeatures::TmaMulticast));
+    assert!(blackwell_requirements.contains(DetectedFeatures::MatrixBlackwell));
+    assert_eq!(select_target(blackwell_requirements).unwrap(), "sm_100a");
+    assert!(arch_satisfies("sm_100a", blackwell_requirements));
+    assert!(!arch_satisfies("sm_90a", blackwell_requirements));
+
+    let impossible = DetectedFeatures::Wgmma | DetectedFeatures::MatrixBlackwell;
+    let error = select_target(impossible).expect_err("families have no common target");
+    assert!(error.contains("do not share a compatible GPU architecture"));
+    assert!(resolve_ptx_target(Some("sm_90a"), "CUDA_OXIDE_TARGET", None, impossible).is_err());
+    assert!(resolve_ptx_target(Some("sm_100a"), "CUDA_OXIDE_TARGET", None, impossible).is_err());
+}
+
+#[test]
+fn rejected_explicit_targets_name_the_source_that_chose_them() {
+    let parse_failure = resolve_ptx_target(
+        Some("not-a-target"),
+        "PipelineConfig::target_arch",
+        None,
+        DetectedFeatures::Sm80,
+    )
+    .unwrap_err()
+    .to_string();
+    assert!(
+        parse_failure.contains("invalid CUDA target `not-a-target`"),
+        "{parse_failure}"
+    );
+    assert!(
+        parse_failure.contains("(target from PipelineConfig::target_arch)"),
+        "{parse_failure}"
+    );
+    assert_eq!(
+        parse_failure.matches("invalid CUDA target").count(),
+        1,
+        "parse errors must not double-wrap the parser's own prefix: {parse_failure}"
+    );
+
+    let floor_rejection = resolve_ptx_target(
+        Some("sm_75"),
+        "CUDA_OXIDE_TARGET",
+        None,
+        DetectedFeatures::Sm80,
+    )
+    .unwrap_err()
+    .to_string();
+    assert!(
+        floor_rejection.contains("cannot lower detected feature Sm80"),
+        "{floor_rejection}"
+    );
+    assert!(
+        floor_rejection.contains("(target from CUDA_OXIDE_TARGET)"),
+        "{floor_rejection}"
+    );
+}
+
+#[test]
+fn test_arch_major_parses_cuda_spelling() {
+    assert_eq!(arch_compute_capability("sm_75"), Some(75));
+    assert_eq!(arch_compute_capability("sm_100a"), Some(100));
+    assert_eq!(arch_major("sm_75"), Some(7));
+    assert_eq!(arch_major("sm_80"), Some(8));
+    assert_eq!(arch_major("sm_90a"), Some(9));
+    assert_eq!(arch_major("sm_100a"), Some(10));
+    assert_eq!(arch_major("sm_103a"), Some(10));
+    assert_eq!(arch_major("sm_120a"), Some(12));
+    assert_eq!(arch_major("nvvm-ir"), None);
+    assert_eq!(arch_major("sm_"), None);
+}
+
+#[test]
+fn ptx9_targets_require_an_llvm22_backend() {
+    for target in ["sm_88", "sm_110", "sm_110a", "sm_110f"] {
+        assert!(
+            validate_target_for_llvm_major(target, Some(21)).is_err(),
+            "{target}"
+        );
+        assert!(
+            validate_target_for_llvm_major(target, None).is_err(),
+            "{target}"
+        );
+        assert!(
+            validate_target_for_llvm_major(target, Some(22)).is_ok(),
+            "{target}"
+        );
+        assert!(
+            validate_target_for_llvm_major(target, Some(23)).is_ok(),
+            "{target}"
+        );
+    }
+    for target in ["sm_87", "sm_103a", "sm_120a", "sm_121f"] {
+        assert!(
+            validate_target_for_llvm_major(target, Some(21)).is_ok(),
+            "{target}"
+        );
+    }
+    for target in ["sm_999a", "not-a-target", "compute_88"] {
+        assert!(
+            validate_target_for_llvm_major(target, Some(21)).is_ok(),
+            "unknown or non-sm target {target} must remain owned by other validators"
+        );
+    }
+    for (target, floor) in [
+        ("sm_90a", 80),
+        ("sm_100a", 86),
+        ("sm_100f", 88),
+        ("sm_120a", 87),
+        ("sm_120f", 88),
+        ("sm_121a", 88),
+    ] {
+        assert_eq!(recorded_ptx_floor(&target.parse().unwrap()), Ok(floor));
+    }
+}
+
+#[test]
+fn test_arch_satisfies_sm100_only_features() {
+    // tcgen05 and explicit cta_group TMA are datacenter-Blackwell only:
+    // consumer Blackwell (sm_120) and Hopper (sm_90) cannot run them, even
+    // though 120 > 100. This is the gemm_sol regression guard.
+    for f in [DetectedFeatures::Blackwell, DetectedFeatures::TmaCtaGroup] {
+        assert!(arch_satisfies("sm_100a", f), "sm_100a must satisfy {f:?}");
+        assert!(arch_satisfies("sm_103a", f), "sm_103a must satisfy {f:?}");
+        assert!(arch_satisfies("sm_103f", f), "sm_103f must satisfy {f:?}");
+        assert!(
+            !arch_satisfies("sm_100", f),
+            "generic sm_100 must NOT satisfy {f:?}"
+        );
+        assert!(
+            !arch_satisfies("sm_120a", f),
+            "sm_120a must NOT satisfy {f:?}"
+        );
+        assert!(
+            !arch_satisfies("sm_90a", f),
+            "sm_90a must NOT satisfy {f:?}"
+        );
+        assert!(
+            !arch_satisfies("sm_102a", f),
+            "unknown architecture-specific targets must not be accepted"
+        );
+        assert!(
+            !arch_satisfies("sm_102f", f),
+            "unknown family-specific targets must not be accepted"
+        );
+    }
+}
+
+#[test]
+fn test_arch_satisfies_base_tma_multicast_targets() {
+    for arch in [
+        "sm_90", "sm_90a", "sm_100", "sm_100a", "sm_103f", "sm_110a", "sm_120", "sm_120a",
+    ] {
+        assert!(
+            arch_satisfies(arch, DetectedFeatures::TmaMulticast),
+            "{arch}"
+        );
+    }
+    for arch in ["sm_80", "sm_89", "sm_102a", "sm_102f"] {
+        assert!(
+            !arch_satisfies(arch, DetectedFeatures::TmaMulticast),
+            "{arch}"
+        );
+    }
+}
+
+#[test]
+fn test_arch_satisfies_wgmma_is_hopper_only() {
+    assert!(arch_satisfies("sm_90a", DetectedFeatures::Wgmma));
+    assert!(!arch_satisfies("sm_90", DetectedFeatures::Wgmma));
+    assert!(!arch_satisfies("sm_100a", DetectedFeatures::Wgmma));
+    assert!(!arch_satisfies("sm_120a", DetectedFeatures::Wgmma));
+}
+
+#[test]
+fn test_arch_satisfies_blackwell_matrix_family_targets() {
+    for arch in [
+        "sm_100a", "sm_103a", "sm_110a", "sm_120a", "sm_121a", "sm_100f", "sm_103f", "sm_110f",
+        "sm_120f", "sm_121f",
+    ] {
+        assert!(
+            arch_satisfies(arch, DetectedFeatures::MatrixBlackwell),
+            "{arch}"
+        );
+    }
+    for arch in [
+        "sm_100a", "sm_101a", "sm_110a", "sm_120a", "sm_100f", "sm_101f", "sm_103f", "sm_110f",
+        "sm_120f", "sm_121f",
+    ] {
+        assert!(
+            arch_satisfies(arch, DetectedFeatures::BlackwellFamily),
+            "{arch}"
+        );
+    }
+    for arch in ["sm_101a", "sm_101f"] {
+        assert!(!arch_satisfies(arch, DetectedFeatures::MatrixBlackwell));
+    }
+    for arch in ["sm_103a", "sm_121a"] {
+        assert!(!arch_satisfies(arch, DetectedFeatures::BlackwellFamily));
+    }
+    for arch in [
+        "sm_100a", "sm_101a", "sm_103a", "sm_110a", "sm_100f", "sm_103f", "sm_110f",
+    ] {
+        assert!(
+            arch_satisfies(arch, DetectedFeatures::BlackwellAccelerated),
+            "{arch}"
+        );
+    }
+    for arch in ["sm_100", "sm_120a", "sm_120f", "sm_102f"] {
+        assert!(
+            !arch_satisfies(arch, DetectedFeatures::BlackwellAccelerated),
+            "{arch}"
+        );
+    }
+    for arch in ["sm_100", "sm_103", "sm_110", "sm_120", "sm_121a"] {
+        assert!(arch_satisfies(arch, DetectedFeatures::Sm100), "{arch}");
+    }
+    for arch in ["sm_90a", "sm_102", "sm_102a"] {
+        assert!(!arch_satisfies(arch, DetectedFeatures::Sm100), "{arch}");
+    }
+    for arch in ["sm_90a", "sm_100", "sm_102f", "sm_120"] {
+        assert!(
+            !arch_satisfies(arch, DetectedFeatures::MatrixBlackwell),
+            "{arch}"
+        );
+        assert!(
+            !arch_satisfies(arch, DetectedFeatures::BlackwellFamily),
+            "{arch}"
+        );
+    }
+}
+
+#[test]
+fn test_arch_satisfies_forward_compatible_features() {
+    // Plain TMA / cluster / sm_90-floor instructions lower on any sm_90+
+    // device, sm_80-floor instructions on any sm_80+ device, movmatrix and
+    // base ldmatrix on sm_75+, and basic kernels on Volta+.
+    // So a consumer sm_120 GPU is a valid target for these (it runs locally
+    // instead of being downgraded to the feature floor).
+    for arch in ["sm_90a", "sm_100a", "sm_120a"] {
+        assert!(arch_satisfies(arch, DetectedFeatures::Tma));
+        assert!(arch_satisfies(arch, DetectedFeatures::Cluster));
+        assert!(arch_satisfies(arch, DetectedFeatures::Sm90));
+        assert!(arch_satisfies(arch, DetectedFeatures::Sm80));
+        assert!(arch_satisfies(arch, DetectedFeatures::Movmatrix));
+        assert!(arch_satisfies(arch, DetectedFeatures::Ldmatrix));
+        assert!(arch_satisfies(arch, DetectedFeatures::Basic));
+    }
+    assert!(arch_satisfies("sm_80", DetectedFeatures::Sm80));
+    assert!(!arch_satisfies("sm_75", DetectedFeatures::Sm80));
+    assert!(arch_satisfies("sm_75", DetectedFeatures::Movmatrix));
+    assert!(arch_satisfies("sm_80", DetectedFeatures::Movmatrix));
+    assert!(!arch_satisfies("sm_70", DetectedFeatures::Movmatrix));
+    assert!(arch_satisfies("sm_75", DetectedFeatures::Ldmatrix));
+    assert!(!arch_satisfies("sm_70", DetectedFeatures::Ldmatrix));
+    assert!(arch_satisfies("sm_80", DetectedFeatures::Basic));
+    assert!(arch_satisfies("sm_75", DetectedFeatures::Basic));
+    assert!(arch_satisfies("sm_70", DetectedFeatures::Basic));
+    assert!(!arch_satisfies("sm_80", DetectedFeatures::Tma));
+    assert!(!arch_satisfies("sm_80", DetectedFeatures::Sm90));
+    assert!(!arch_satisfies("sm_80a", DetectedFeatures::Basic));
+    assert!(!arch_satisfies("sm_90f", DetectedFeatures::Tma));
+}
+
+#[test]
+fn resolve_ptx_target_threads_a_caller_supplied_source_label() {
+    let (target, source) = resolve_ptx_target(
+        Some("sm_80"),
+        "the requested Target",
+        None,
+        DetectedFeatures::Basic,
+    )
+    .unwrap();
+    assert_eq!(target, "sm_80");
+    assert_eq!(source, "the requested Target");
+}
+
+#[test]
+fn resolve_ptx_target_failure_does_not_assume_an_env_var_source() {
+    let error = resolve_ptx_target(
+        Some("sm_75"),
+        "the requested Target",
+        None,
+        DetectedFeatures::Wgmma,
+    )
+    .unwrap_err();
+    assert!(matches!(error, PipelineError::TargetSelection { .. }));
+    assert!(
+        !error.to_string().contains("CUDA_OXIDE_TARGET"),
+        "a standalone caller that never set CUDA_OXIDE_TARGET should not see it blamed: {error}"
+    );
+
+    let parse_error = resolve_ptx_target(
+        Some("not-a-target"),
+        "the requested Target",
+        None,
+        DetectedFeatures::Basic,
+    )
+    .unwrap_err();
+    assert!(matches!(parse_error, PipelineError::TargetSelection { .. }));
+    assert!(
+        !parse_error.to_string().contains("CUDA_OXIDE_TARGET"),
+        "{parse_error}"
+    );
+}
diff --git a/crates/dialect-mir/tests/ops_test.rs b/crates/dialect-mir/tests/ops_test.rs
deleted file mode 100644
index b235dd9c09..0000000000
--- a/crates/dialect-mir/tests/ops_test.rs
+++ /dev/null
@@ -1,4251 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// Tests build kinded fixture types directly; production minting lives in
-// mir-importer's facts.rs (see the workspace clippy.toml disallowed-methods).
-#![allow(clippy::disallowed_methods)]
-
-use dialect_mir::{
-    attributes::{FieldIndexAttr, MirCastKindAttr, MirPointerKindAuthorityAttr, VariantIndexAttr},
-    ops::{
-        MirAddOp, MirAllocaOp, MirArrayElementAddrOp, MirAssertOp, MirAssignOp, MirCallOp,
-        MirCastOp, MirCheckedAddOp, MirCmpOp, MirCondBranchOp, MirConstantOp,
-        MirConstructDisjointSliceOp, MirConstructEnumOp, MirConstructSliceOp, MirDivOp,
-        MirEnumPayloadOp, MirEqOp, MirExtractFieldOp, MirFieldAddrOp, MirFuncOp, MirGeOp,
-        MirGetDiscriminantOp, MirGlobalAllocOp, MirGotoOp, MirGtOp, MirLeOp, MirLoadOp, MirLtOp,
-        MirMulOp, MirNeOp, MirNegOp, MirNotOp, MirPtrOffsetOp, MirRefOp, MirRemOp, MirReturnOp,
-        MirSetDiscriminantOp, MirSharedAllocOp, MirStoreOp, MirSubOp,
-    },
-    types::{
-        EnumVariant, MirArrayType, MirDisjointSliceType, MirEnumType, MirPointerKind, MirPtrType,
-        MirSliceType, MirStructType, MirTupleType, MirUnionType,
-    },
-};
-use pliron::{
-    basic_block::BasicBlock,
-    builtin::{
-        attributes::{IntegerAttr, StringAttr, TypeAttr},
-        op_interfaces::OperandSegmentInterface,
-        types::{FP32Type, FunctionType, IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::Context,
-    op::Op,
-    operation::Operation,
-    opts::mem2reg::{AllocInfo, PromotableOpInterface, PromotableOpKind},
-    r#type::TypeHandle,
-    utils::apint::APInt,
-};
-use std::num::NonZeroUsize;
-
-#[test]
-fn test_mir_control_flow_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-
-    // 1. MirGotoOp
-    let target_block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let src_block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let arg_val = src_block.deref(&ctx).get_argument(0);
-
-    let op = Operation::new(
-        &mut ctx,
-        MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![arg_val],
-        vec![target_block],
-        0,
-    );
-    let goto_op = MirGotoOp::new(op);
-    assert!(goto_op.verify(&ctx).is_ok(), "Valid Goto");
-
-    let op_bad = Operation::new(
-        &mut ctx,
-        MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![target_block],
-        0,
-    );
-    assert!(
-        MirGotoOp::new(op_bad).verify(&ctx).is_err(),
-        "Goto missing operand"
-    );
-
-    // 2. MirCondBranchOp
-    let true_block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let false_block = BasicBlock::new(&mut ctx, None, vec![]);
-    let cond_block = BasicBlock::new(&mut ctx, None, vec![i1_ty.into(), i32_ty.into()]);
-    let cond_val = cond_block.deref(&ctx).get_argument(0);
-    let val = cond_block.deref(&ctx).get_argument(1);
-
-    let (cond_flat, cond_sizes) =
-        MirCondBranchOp::compute_segment_sizes(vec![vec![cond_val], vec![val], vec![]]);
-    let op_cond = Operation::new(
-        &mut ctx,
-        MirCondBranchOp::get_concrete_op_info(),
-        vec![],
-        cond_flat,
-        vec![true_block, false_block],
-        0,
-    );
-    MirCondBranchOp::new(op_cond).set_operand_segment_sizes(&ctx, cond_sizes);
-    let cond_br = MirCondBranchOp::new(op_cond);
-    assert!(cond_br.verify(&ctx).is_ok(), "Valid CondBranch");
-
-    let (cond_bad_flat, cond_bad_sizes) =
-        MirCondBranchOp::compute_segment_sizes(vec![vec![cond_val], vec![], vec![]]);
-    let op_cond_bad = Operation::new(
-        &mut ctx,
-        MirCondBranchOp::get_concrete_op_info(),
-        vec![],
-        cond_bad_flat,
-        vec![true_block, false_block],
-        0,
-    );
-    MirCondBranchOp::new(op_cond_bad).set_operand_segment_sizes(&ctx, cond_bad_sizes);
-    assert!(
-        MirCondBranchOp::new(op_cond_bad).verify(&ctx).is_err(),
-        "CondBranch missing operand"
-    );
-
-    // 3. MirReturnOp
-    let func_ty = FunctionType::get(&ctx, vec![], vec![i32_ty.into()]);
-    let func_ty_attr = TypeAttr::new(func_ty.into());
-
-    let func_op_ptr = Operation::new(
-        &mut ctx,
-        MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let mir_func = MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
-    let entry_block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let ret_val = entry_block.deref(&ctx).get_argument(0);
-
-    let region = mir_func.get_operation().deref(&ctx).get_region(0);
-    entry_block.insert_at_front(region, &ctx);
-
-    let ret_op = Operation::new(
-        &mut ctx,
-        MirReturnOp::get_concrete_op_info(),
-        vec![],
-        vec![ret_val],
-        vec![],
-        0,
-    );
-    ret_op.insert_at_back(entry_block, &ctx);
-
-    let mir_ret = MirReturnOp::new(ret_op);
-    assert!(mir_ret.verify(&ctx).is_ok(), "Valid Return");
-
-    let f32_ty = FP32Type::get(&ctx);
-    let f32_block = BasicBlock::new(&mut ctx, None, vec![f32_ty.into()]);
-    let f32_val = f32_block.deref(&ctx).get_argument(0);
-
-    let ret_op_bad = Operation::new(
-        &mut ctx,
-        MirReturnOp::get_concrete_op_info(),
-        vec![],
-        vec![f32_val],
-        vec![],
-        0,
-    );
-    ret_op_bad.insert_at_back(entry_block, &ctx);
-
-    let mir_ret_bad = MirReturnOp::new(ret_op_bad);
-    assert!(mir_ret_bad.verify(&ctx).is_err(), "Return type mismatch");
-
-    // 4. MirAssertOp
-    let assert_succ = BasicBlock::new(&mut ctx, None, vec![]);
-
-    let (assert_flat, assert_sizes) =
-        MirAssertOp::compute_segment_sizes(vec![vec![cond_val], vec![]]);
-    let op_assert = Operation::new(
-        &mut ctx,
-        MirAssertOp::get_concrete_op_info(),
-        vec![],
-        assert_flat,
-        vec![assert_succ],
-        0,
-    );
-    MirAssertOp::new(op_assert).set_operand_segment_sizes(&ctx, assert_sizes);
-    let assert_op = MirAssertOp::new(op_assert);
-    assert!(assert_op.verify(&ctx).is_ok(), "Valid Assert");
-
-    let (assert_bad_flat, assert_bad_sizes) =
-        MirAssertOp::compute_segment_sizes(vec![vec![val], vec![]]);
-    let op_assert_bad = Operation::new(
-        &mut ctx,
-        MirAssertOp::get_concrete_op_info(),
-        vec![],
-        assert_bad_flat,
-        vec![assert_succ],
-        0,
-    );
-    MirAssertOp::new(op_assert_bad).set_operand_segment_sizes(&ctx, assert_bad_sizes);
-    assert!(
-        MirAssertOp::new(op_assert_bad).verify(&ctx).is_err(),
-        "Assert cond type mismatch"
-    );
-}
-
-#[test]
-fn test_mir_pointer_kind_distinguishes_references_from_raw_pointers() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let pointee: pliron::r#type::TypeHandle = i32_ty.into();
-
-    let shared_ref =
-        MirPtrType::get_generic_with_kind(&mut ctx, pointee, false, MirPointerKind::SharedRef);
-    let raw_const =
-        MirPtrType::get_generic_with_kind(&mut ctx, pointee, false, MirPointerKind::RawConst);
-    let unique_ref =
-        MirPtrType::get_generic_with_kind(&mut ctx, pointee, true, MirPointerKind::UniqueRef);
-    let raw_mut =
-        MirPtrType::get_generic_with_kind(&mut ctx, pointee, true, MirPointerKind::RawMut);
-
-    assert_ne!(
-        shared_ref, raw_const,
-        "&T must remain distinct from *const T"
-    );
-    assert_ne!(
-        unique_ref, raw_mut,
-        "&mut T must remain distinct from *mut T"
-    );
-    assert_ne!(
-        shared_ref, unique_ref,
-        "&T must remain distinct from &mut T"
-    );
-    assert_ne!(
-        raw_const, raw_mut,
-        "*const T must remain distinct from *mut T"
-    );
-
-    assert_eq!(
-        shared_ref.deref(&ctx).pointer_kind(),
-        MirPointerKind::SharedRef
-    );
-    assert_eq!(
-        unique_ref.deref(&ctx).pointer_kind(),
-        MirPointerKind::UniqueRef
-    );
-    assert_eq!(
-        raw_const.deref(&ctx).pointer_kind(),
-        MirPointerKind::RawConst
-    );
-    assert_eq!(raw_mut.deref(&ctx).pointer_kind(), MirPointerKind::RawMut);
-}
-
-#[test]
-fn test_mir_slice_preserves_pointer_kind() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let element: pliron::r#type::TypeHandle = u8_ty.into();
-
-    let shared = MirSliceType::get_with_kind(&mut ctx, element, MirPointerKind::SharedRef);
-    let raw = MirSliceType::get_with_kind(&mut ctx, element, MirPointerKind::RawConst);
-
-    assert_ne!(shared, raw, "&[T] must remain distinct from *const [T]");
-    assert_eq!(shared.deref(&ctx).pointer_kind(), MirPointerKind::SharedRef);
-    assert_eq!(raw.deref(&ctx).pointer_kind(), MirPointerKind::RawConst);
-}
-
-#[test]
-fn test_mir_pointer_kind_mutability_consistency_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let invalid_shared = MirPtrType {
-        pointee: i32_ty.into(),
-        is_mutable: true,
-        address_space: 0,
-        kind: MirPointerKind::SharedRef,
-    };
-    let invalid_raw_mut = MirPtrType {
-        pointee: i32_ty.into(),
-        is_mutable: false,
-        address_space: 0,
-        kind: MirPointerKind::RawMut,
-    };
-
-    assert!(invalid_shared.verify(&ctx).is_err());
-    assert!(invalid_raw_mut.verify(&ctx).is_err());
-
-    let invalid_shared_slice = MirSliceType {
-        element_ty: i32_ty.into(),
-        is_mutable: true,
-        kind: MirPointerKind::SharedRef,
-    };
-    let valid_erased_mut_slice = MirSliceType {
-        element_ty: i32_ty.into(),
-        is_mutable: true,
-        kind: MirPointerKind::Erased,
-    };
-    assert!(invalid_shared_slice.verify(&ctx).is_err());
-    assert!(valid_erased_mut_slice.verify(&ctx).is_ok());
-}
-
-#[test]
-fn test_alloca_cannot_claim_a_rust_pointer_kind() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let erased = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let erased_alloca = Operation::new(
-        &mut ctx,
-        MirAllocaOp::get_concrete_op_info(),
-        vec![erased.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(MirAllocaOp::new(erased_alloca).verify(&ctx).is_ok());
-
-    let immutable_erased = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let immutable_alloca = Operation::new(
-        &mut ctx,
-        MirAllocaOp::get_concrete_op_info(),
-        vec![immutable_erased.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(
-        MirAllocaOp::new(immutable_alloca).verify(&ctx).is_err(),
-        "an alloca cannot masquerade as the immutable canonical function-pointer carrier"
-    );
-
-    let shared_erased = MirPtrType::get_shared(&mut ctx, i32_ty.into(), true);
-    let shared_alloca = Operation::new(
-        &mut ctx,
-        MirAllocaOp::get_concrete_op_info(),
-        vec![shared_erased.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(
-        MirAllocaOp::new(shared_alloca).verify(&ctx).is_err(),
-        "a stack allocation must remain in generic address space"
-    );
-
-    let unique =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
-    let unique_alloca = Operation::new(
-        &mut ctx,
-        MirAllocaOp::get_concrete_op_info(),
-        vec![unique.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(
-        MirAllocaOp::new(unique_alloca).verify(&ctx).is_err(),
-        "compiler storage must not manufacture UniqueRef"
-    );
-}
-
-#[test]
-fn test_shared_alloc_result_pointee_must_match_element_type() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
-    let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
-    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let mismatched_result = MirPtrType::get_shared(&mut ctx, i64_ty, true);
-    let op = Operation::new(
-        &mut ctx,
-        MirSharedAllocOp::get_concrete_op_info(),
-        vec![mismatched_result.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let alloc = MirSharedAllocOp::new(op);
-    alloc.set_attr_elem_type(&ctx, TypeAttr::new(i8_ty));
-    alloc.set_attr_size(
-        &ctx,
-        IntegerAttr::new(usize_ty, APInt::from_u64(1, NonZeroUsize::new(64).unwrap())),
-    );
-    alloc.set_attr_alloc_key(&ctx, StringAttr::new("mismatched-shared".to_string()));
-
-    let error = alloc
-        .verify(&ctx)
-        .expect_err("shared storage cannot claim an unrelated result pointee type");
-    assert!(
-        error
-            .to_string()
-            .contains("pointee type must match elem_type"),
-        "{error}"
-    );
-}
-
-#[test]
-fn test_mir_load_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-
-    let block = BasicBlock::new(&mut ctx, None, vec![ptr_ty.into()]);
-    let ptr_val = block.deref(&ctx).get_argument(0);
-
-    let op = Operation::new(
-        &mut ctx,
-        MirLoadOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![ptr_val],
-        vec![],
-        0,
-    );
-    let mir_load = MirLoadOp::new(op);
-    assert!(mir_load.verify(&ctx).is_ok(), "Valid MirLoadOp");
-
-    let block_i32 = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let i32_val = block_i32.deref(&ctx).get_argument(0);
-
-    let op_fail_operand = Operation::new(
-        &mut ctx,
-        MirLoadOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![i32_val],
-        vec![],
-        0,
-    );
-    let mir_load_fail_operand = MirLoadOp::new(op_fail_operand);
-    assert!(
-        mir_load_fail_operand.verify(&ctx).is_err(),
-        "MirLoadOp non-ptr operand"
-    );
-
-    let f32_ty = FP32Type::get(&ctx);
-    let op_fail_res = Operation::new(
-        &mut ctx,
-        MirLoadOp::get_concrete_op_info(),
-        vec![f32_ty.into()],
-        vec![ptr_val],
-        vec![],
-        0,
-    );
-    let mir_load_fail_res = MirLoadOp::new(op_fail_res);
-    assert!(
-        mir_load_fail_res.verify(&ctx).is_err(),
-        "MirLoadOp result mismatch"
-    );
-}
-
-#[test]
-fn test_mir_load_volatile_is_not_promotable() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let block = BasicBlock::new(&mut ctx, None, vec![ptr_ty.into()]);
-    let ptr_val = block.deref(&ctx).get_argument(0);
-
-    let op = Operation::new(
-        &mut ctx,
-        MirLoadOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![ptr_val],
-        vec![],
-        0,
-    );
-    let mir_load = MirLoadOp::new(op);
-    let alloc_info = AllocInfo {
-        ptr: ptr_val,
-        ty: i32_ty.into(),
-    };
-
-    assert!(!mir_load.is_volatile(&ctx));
-    assert!(matches!(
-        mir_load.promotion_kind(&ctx, &alloc_info),
-        PromotableOpKind::Load
-    ));
-
-    mir_load.set_volatile(&mut ctx, true);
-
-    assert!(mir_load.is_volatile(&ctx));
-    assert!(matches!(
-        mir_load.promotion_kind(&ctx, &alloc_info),
-        PromotableOpKind::NonPromotableUse
-    ));
-}
-
-#[test]
-fn test_mir_ptr_offset_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-
-    let block = BasicBlock::new(&mut ctx, None, vec![ptr_ty.into(), usize_ty.into()]);
-    let ptr_val = block.deref(&ctx).get_argument(0);
-    let idx_val = block.deref(&ctx).get_argument(1);
-
-    let op = Operation::new(
-        &mut ctx,
-        MirPtrOffsetOp::get_concrete_op_info(),
-        vec![ptr_ty.into()],
-        vec![ptr_val, idx_val],
-        vec![],
-        0,
-    );
-    let offset_op = MirPtrOffsetOp::new(op);
-    assert!(offset_op.verify(&ctx).is_ok(), "Valid MirPtrOffsetOp");
-    assert!(
-        offset_op.is_inbounds(&ctx),
-        "ordinary pointer offsets default to inbounds"
-    );
-    offset_op.set_inbounds(&mut ctx, false);
-    assert!(
-        !offset_op.is_inbounds(&ctx),
-        "wrapping pointer offsets retain their explicit semantics"
-    );
-
-    let block2 = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), usize_ty.into()]);
-    let i32_val = block2.deref(&ctx).get_argument(0);
-    let idx_val2 = block2.deref(&ctx).get_argument(1);
-
-    let op_bad_base = Operation::new(
-        &mut ctx,
-        MirPtrOffsetOp::get_concrete_op_info(),
-        vec![ptr_ty.into()],
-        vec![i32_val, idx_val2],
-        vec![],
-        0,
-    );
-    assert!(MirPtrOffsetOp::new(op_bad_base).verify(&ctx).is_err());
-
-    let f32_ty = FP32Type::get(&ctx);
-    let ptr_f32_ty = MirPtrType::get_generic(&mut ctx, f32_ty.into(), false);
-    let op_bad_res = Operation::new(
-        &mut ctx,
-        MirPtrOffsetOp::get_concrete_op_info(),
-        vec![ptr_f32_ty.into()],
-        vec![ptr_val, idx_val],
-        vec![],
-        0,
-    );
-    assert!(MirPtrOffsetOp::new(op_bad_res).verify(&ctx).is_err());
-}
-
-#[test]
-fn test_pointer_kind_laundering_requires_explicit_authority() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let raw_mut_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
-    let erased_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let erased_read_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let unique_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
-    let shared_ty = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        i32_ty.into(),
-        false,
-        MirPointerKind::SharedRef,
-    );
-    let raw_const_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), false, MirPointerKind::RawConst);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            raw_mut_ty.into(),
-            erased_ty.into(),
-            usize_ty.into(),
-            shared_ty.into(),
-            raw_const_ty.into(),
-            erased_read_ty.into(),
-        ],
-    );
-    let raw_mut = block.deref(&ctx).get_argument(0);
-    let erased = block.deref(&ctx).get_argument(1);
-    let offset = block.deref(&ctx).get_argument(2);
-    let shared = block.deref(&ctx).get_argument(3);
-    let raw_const = block.deref(&ctx).get_argument(4);
-    let erased_read = block.deref(&ctx).get_argument(5);
-
-    // The concrete laundering example: pointer arithmetic is not a Rust
-    // reborrow and cannot manufacture `&mut T` from `*mut T`.
-    let raw_offset_to_unique = Operation::new(
-        &mut ctx,
-        MirPtrOffsetOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![raw_mut, offset],
-        vec![],
-        0,
-    );
-    assert!(
-        MirPtrOffsetOp::new(raw_offset_to_unique)
-            .verify(&ctx)
-            .is_err(),
-        "ptr_offset must not invent UniqueRef from RawMut"
-    );
-
-    let erased_offset_to_unique = Operation::new(
-        &mut ctx,
-        MirPtrOffsetOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![erased, offset],
-        vec![],
-        0,
-    );
-    assert!(
-        MirPtrOffsetOp::new(erased_offset_to_unique)
-            .verify(&ctx)
-            .is_err(),
-        "ptr_offset must not recover UniqueRef from Erased"
-    );
-
-    let preserving_offset = Operation::new(
-        &mut ctx,
-        MirPtrOffsetOp::get_concrete_op_info(),
-        vec![raw_mut_ty.into()],
-        vec![raw_mut, offset],
-        vec![],
-        0,
-    );
-    assert!(MirPtrOffsetOp::new(preserving_offset).verify(&ctx).is_ok());
-
-    let erasing_offset = Operation::new(
-        &mut ctx,
-        MirPtrOffsetOp::get_concrete_op_info(),
-        vec![erased_ty.into()],
-        vec![raw_mut, offset],
-        vec![],
-        0,
-    );
-    assert!(MirPtrOffsetOp::new(erasing_offset).verify(&ctx).is_ok());
-
-    let mutability_launder = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![erased_ty.into()],
-        vec![erased_read],
-        vec![],
-        0,
-    );
-    let mutability_launder_cast = MirCastOp::new(mutability_launder);
-    mutability_launder_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    assert!(
-        mutability_launder_cast.verify(&ctx).is_err(),
-        "an unmarked cast cannot manufacture writable Erased evidence"
-    );
-
-    let reborrow = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![raw_mut],
-        vec![],
-        0,
-    );
-    let reborrow_cast = MirCastOp::new(reborrow);
-    reborrow_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    assert!(
-        reborrow_cast.verify(&ctx).is_err(),
-        "an unmarked cast must not manufacture UniqueRef"
-    );
-    reborrow_cast.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    assert!(
-        reborrow_cast.verify(&ctx).is_ok(),
-        "a rustc-declared reborrow is the explicit authority"
-    );
-
-    for (target, authority) in [
-        (unique_ty.into(), MirPointerKindAuthorityAttr::Reborrow),
-        (raw_mut_ty.into(), MirPointerKindAuthorityAttr::RawAddress),
-    ] {
-        let mutable_storage_boundary = Operation::new(
-            &mut ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![target],
-            vec![erased],
-            vec![],
-            0,
-        );
-        let mutable_storage_boundary_cast = MirCastOp::new(mutable_storage_boundary);
-        mutable_storage_boundary_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-        mutable_storage_boundary_cast.set_pointer_kind_authority(&mut ctx, authority);
-        assert!(
-            mutable_storage_boundary_cast.verify(&ctx).is_ok(),
-            "mutable compiler storage is a valid source for a mutable Rust boundary"
-        );
-    }
-
-    let raw_to_shared_static = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![shared_ty.into()],
-        vec![raw_const],
-        vec![],
-        0,
-    );
-    let raw_to_shared_static_cast = MirCastOp::new(raw_to_shared_static);
-    raw_to_shared_static_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    raw_to_shared_static_cast
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    assert!(
-        raw_to_shared_static_cast.verify(&ctx).is_err(),
-        "StaticAddress may establish a typed static value only from Erased storage, not relabel an arbitrary raw pointer as SharedRef"
-    );
-
-    let raw_to_erased = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![erased_read_ty.into()],
-        vec![raw_const],
-        vec![],
-        0,
-    );
-    let raw_to_erased_cast = MirCastOp::new(raw_to_erased);
-    raw_to_erased_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    assert!(raw_to_erased_cast.verify(&ctx).is_ok());
-    let erased_from_raw = raw_to_erased.deref(&ctx).get_result(0);
-    let laundered_static = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![shared_ty.into()],
-        vec![erased_from_raw],
-        vec![],
-        0,
-    );
-    let laundered_static_cast = MirCastOp::new(laundered_static);
-    laundered_static_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    laundered_static_cast
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    assert!(
-        laundered_static_cast.verify(&ctx).is_err(),
-        "erasing RawConst must not make it valid StaticAddress storage"
-    );
-
-    let raw_mut_to_erased = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![erased_ty.into()],
-        vec![raw_mut],
-        vec![],
-        0,
-    );
-    let raw_mut_to_erased_cast = MirCastOp::new(raw_mut_to_erased);
-    raw_mut_to_erased_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    assert!(raw_mut_to_erased_cast.verify(&ctx).is_ok());
-    let erased_from_raw_mut = raw_mut_to_erased.deref(&ctx).get_result(0);
-    let laundered_abi = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![erased_from_raw_mut],
-        vec![],
-        0,
-    );
-    let laundered_abi_cast = MirCastOp::new(laundered_abi);
-    laundered_abi_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    laundered_abi_cast
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::AbiBoundary);
-    assert!(
-        laundered_abi_cast.verify(&ctx).is_err(),
-        "erasing RawMut must not let AbiBoundary manufacture UniqueRef"
-    );
-
-    let global_erased_ty = MirPtrType::get_with_kind(
-        &mut ctx,
-        i32_ty.into(),
-        false,
-        dialect_mir::types::address_space::GLOBAL,
-        MirPointerKind::Erased,
-    );
-    let global_op = Operation::new(
-        &mut ctx,
-        MirGlobalAllocOp::get_concrete_op_info(),
-        vec![global_erased_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let global = MirGlobalAllocOp::new(global_op);
-    global.set_attr_global_type(&ctx, TypeAttr::new(i32_ty.into()));
-    global.set_attr_global_key(&ctx, StringAttr::new("lineage-global".to_string()));
-    assert!(global.verify(&ctx).is_ok());
-    let global_storage = global_op.deref(&ctx).get_result(0);
-    let typed_global = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![shared_ty.into()],
-        vec![global_storage],
-        vec![],
-        0,
-    );
-    let typed_global_cast = MirCastOp::new(typed_global);
-    typed_global_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    typed_global_cast
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    assert!(
-        typed_global_cast.verify(&ctx).is_ok(),
-        "StaticAddress accepts a verified global-allocation root"
-    );
-
-    let shared_erased_ty = MirPtrType::get_shared(&mut ctx, i32_ty.into(), true);
-    let shared_op = Operation::new(
-        &mut ctx,
-        MirSharedAllocOp::get_concrete_op_info(),
-        vec![shared_erased_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let shared_alloc = MirSharedAllocOp::new(shared_op);
-    shared_alloc.set_attr_elem_type(&ctx, TypeAttr::new(i32_ty.into()));
-    shared_alloc.set_attr_size(
-        &ctx,
-        IntegerAttr::new(usize_ty, APInt::from_u64(1, NonZeroUsize::new(64).unwrap())),
-    );
-    shared_alloc.set_attr_alloc_key(&ctx, StringAttr::new("lineage-shared".to_string()));
-    assert!(shared_alloc.verify(&ctx).is_ok());
-    let shared_storage = shared_op.deref(&ctx).get_result(0);
-    let typed_shared = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![raw_mut_ty.into()],
-        vec![shared_storage],
-        vec![],
-        0,
-    );
-    let typed_shared_cast = MirCastOp::new(typed_shared);
-    typed_shared_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    typed_shared_cast
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    assert!(
-        typed_shared_cast.verify(&ctx).is_ok(),
-        "StaticAddress accepts a verified shared-allocation root"
-    );
-
-    let alloca_op = Operation::new(
-        &mut ctx,
-        MirAllocaOp::get_concrete_op_info(),
-        vec![erased_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let alloca = MirAllocaOp::new(alloca_op);
-    assert!(alloca.verify(&ctx).is_ok());
-    let compiler_storage = alloca_op.deref(&ctx).get_result(0);
-    let typed_abi = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![raw_mut_ty.into()],
-        vec![compiler_storage],
-        vec![],
-        0,
-    );
-    let typed_abi_cast = MirCastOp::new(typed_abi);
-    typed_abi_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    typed_abi_cast.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::AbiBoundary);
-    assert!(
-        typed_abi_cast.verify(&ctx).is_ok(),
-        "AbiBoundary accepts verified compiler-owned alloca storage"
-    );
-
-    for (target, authority) in [
-        (unique_ty.into(), MirPointerKindAuthorityAttr::Reborrow),
-        (raw_mut_ty.into(), MirPointerKindAuthorityAttr::RawAddress),
-        (
-            raw_mut_ty.into(),
-            MirPointerKindAuthorityAttr::StaticAddress,
-        ),
-        (raw_mut_ty.into(), MirPointerKindAuthorityAttr::AbiBoundary),
-    ] {
-        let immutable_storage_boundary = Operation::new(
-            &mut ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![target],
-            vec![erased_read],
-            vec![],
-            0,
-        );
-        let immutable_storage_boundary_cast = MirCastOp::new(immutable_storage_boundary);
-        immutable_storage_boundary_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-        immutable_storage_boundary_cast.set_pointer_kind_authority(&mut ctx, authority);
-        assert!(
-            immutable_storage_boundary_cast.verify(&ctx).is_err(),
-            "an immutable Erased thin pointer cannot establish a mutable Rust pointer kind"
-        );
-    }
-
-    let wrong_authority = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![erased],
-        vec![],
-        0,
-    );
-    let wrong_authority_cast = MirCastOp::new(wrong_authority);
-    wrong_authority_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    wrong_authority_cast
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RawAddress);
-    assert!(
-        wrong_authority_cast.verify(&ctx).is_err(),
-        "RawAddress authority cannot establish a reference kind"
-    );
-
-    let inline_asm_authority = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![erased],
-        vec![],
-        0,
-    );
-    let inline_asm_authority_cast = MirCastOp::new(inline_asm_authority);
-    inline_asm_authority_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    inline_asm_authority_cast
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::InlineAsm);
-    assert!(
-        inline_asm_authority_cast.verify(&ctx).is_err(),
-        "InlineAsm is a producer authority and must never authorize a cast"
-    );
-
-    let integer_reborrow = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![offset],
-        vec![],
-        0,
-    );
-    let integer_reborrow_cast = MirCastOp::new(integer_reborrow);
-    integer_reborrow_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    integer_reborrow_cast
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    assert!(
-        integer_reborrow_cast.verify(&ctx).is_err(),
-        "Reborrow authority cannot reinterpret an integer as a Rust reference"
-    );
-    integer_reborrow_cast
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RustCast);
-    assert!(
-        integer_reborrow_cast.verify(&ctx).is_err(),
-        "RustCast authority cannot make an integer a PtrToPtr operand"
-    );
-    integer_reborrow_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::FnPtrToPtr);
-    assert!(
-        integer_reborrow_cast.verify(&ctx).is_err(),
-        "FnPtrToPtr also requires a real pointer carrier"
-    );
-
-    let f32_ty = FP32Type::get(&ctx);
-    let wrong_pointee_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, f32_ty.into(), true, MirPointerKind::RawMut);
-    let wrong_pointee_block = BasicBlock::new(&mut ctx, None, vec![wrong_pointee_ty.into()]);
-    let wrong_pointee = wrong_pointee_block.deref(&ctx).get_argument(0);
-    let wrong_pointee_reborrow = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![wrong_pointee],
-        vec![],
-        0,
-    );
-    let wrong_pointee_reborrow_cast = MirCastOp::new(wrong_pointee_reborrow);
-    wrong_pointee_reborrow_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    wrong_pointee_reborrow_cast
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    assert!(
-        wrong_pointee_reborrow_cast.verify(&ctx).is_err(),
-        "Reborrow authority must retain the pointee type"
-    );
-
-    for immutable_source in [shared, raw_const] {
-        let invalid_unique = Operation::new(
-            &mut ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![unique_ty.into()],
-            vec![immutable_source],
-            vec![],
-            0,
-        );
-        let invalid_unique_cast = MirCastOp::new(invalid_unique);
-        invalid_unique_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-        invalid_unique_cast
-            .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-        assert!(
-            invalid_unique_cast.verify(&ctx).is_err(),
-            "an immutable source cannot be relabelled as UniqueRef by Reborrow authority"
-        );
-
-        let invalid_raw_mut = Operation::new(
-            &mut ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![raw_mut_ty.into()],
-            vec![immutable_source],
-            vec![],
-            0,
-        );
-        let invalid_raw_mut_cast = MirCastOp::new(invalid_raw_mut);
-        invalid_raw_mut_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-        invalid_raw_mut_cast
-            .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RawAddress);
-        assert!(
-            invalid_raw_mut_cast.verify(&ctx).is_err(),
-            "an immutable source cannot be relabelled as RawMut by RawAddress authority"
-        );
-    }
-}
-
-#[test]
-fn test_promoted_empty_mutable_reference_is_a_narrow_static_exception() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let empty_array_ty = MirArrayType::get(&mut ctx, i32_ty.into(), 0);
-    let nonempty_array_ty = MirArrayType::get(&mut ctx, i32_ty.into(), 1);
-
-    let empty_storage_ty = MirPtrType::get_with_kind(
-        &mut ctx,
-        empty_array_ty.into(),
-        false,
-        dialect_mir::types::address_space::GLOBAL,
-        MirPointerKind::Erased,
-    );
-    let empty_unique_ty = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        empty_array_ty.into(),
-        true,
-        MirPointerKind::UniqueRef,
-    );
-    let empty_global_op = Operation::new(
-        &mut ctx,
-        MirGlobalAllocOp::get_concrete_op_info(),
-        vec![empty_storage_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let empty_global = MirGlobalAllocOp::new(empty_global_op);
-    empty_global.set_attr_global_type(&ctx, TypeAttr::new(empty_array_ty.into()));
-    empty_global.set_attr_global_key(
-        &ctx,
-        StringAttr::new("promoted-empty-mutable-reference".to_string()),
-    );
-    empty_global.set_alignment_value(&mut ctx, 4);
-    empty_global_op.deref_mut(&ctx).attributes.set(
-        "global_initializer_hex".try_into().unwrap(),
-        StringAttr::new(String::new()),
-    );
-    empty_global.mark_immutable(&mut ctx);
-    assert!(empty_global.verify(&ctx).is_ok());
-
-    let empty_global_storage = empty_global_op.deref(&ctx).get_result(0);
-    let empty_static_borrow_op = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![empty_unique_ty.into()],
-        vec![empty_global_storage],
-        vec![],
-        0,
-    );
-    let empty_static_borrow = MirCastOp::new(empty_static_borrow_op);
-    empty_static_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    empty_static_borrow
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-
-    empty_global.set_alignment_value(&mut ctx, 1);
-    assert!(
-        empty_static_borrow.verify(&ctx).is_err(),
-        "even [i32; 0] must retain i32's natural four-byte alignment"
-    );
-    empty_global.set_alignment_value(&mut ctx, 4);
-    assert!(
-        empty_static_borrow.verify(&ctx).is_ok(),
-        "an immutable promoted [T; 0] global may back rustc's vacuous &mut []"
-    );
-
-    empty_global_op.deref_mut(&ctx).attributes.set(
-        "global_initializer_hex".try_into().unwrap(),
-        StringAttr::new("00".to_string()),
-    );
-    assert!(
-        empty_static_borrow.verify(&ctx).is_err(),
-        "the exception requires an actually empty initializer, not merely the attribute"
-    );
-    empty_global_op.deref_mut(&ctx).attributes.set(
-        "global_initializer_hex".try_into().unwrap(),
-        StringAttr::new(String::new()),
-    );
-    empty_global_op.deref_mut(&ctx).attributes.set(
-        "global_initializer_relocations".try_into().unwrap(),
-        StringAttr::new("unexpected-relocation".to_string()),
-    );
-    assert!(
-        empty_static_borrow.verify(&ctx).is_err(),
-        "zero-byte promoted storage cannot carry a relocation"
-    );
-
-    let mutable_empty_global_op = Operation::new(
-        &mut ctx,
-        MirGlobalAllocOp::get_concrete_op_info(),
-        vec![empty_storage_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let mutable_empty_global = MirGlobalAllocOp::new(mutable_empty_global_op);
-    mutable_empty_global.set_attr_global_type(&ctx, TypeAttr::new(empty_array_ty.into()));
-    mutable_empty_global.set_attr_global_key(
-        &ctx,
-        StringAttr::new("non-promoted-empty-global".to_string()),
-    );
-    assert!(mutable_empty_global.verify(&ctx).is_ok());
-    let mutable_empty_storage = mutable_empty_global_op.deref(&ctx).get_result(0);
-    let mutable_empty_borrow_op = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![empty_unique_ty.into()],
-        vec![mutable_empty_storage],
-        vec![],
-        0,
-    );
-    let mutable_empty_borrow = MirCastOp::new(mutable_empty_borrow_op);
-    mutable_empty_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    mutable_empty_borrow
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    assert!(
-        mutable_empty_borrow.verify(&ctx).is_err(),
-        "the [T; 0] exception requires compiler-promoted immutable storage"
-    );
-
-    let aligned_element_ty: TypeHandle = MirStructType::get_with_full_layout(
-        &mut ctx,
-        "Align16".to_string(),
-        vec!["value".to_string()],
-        vec![i32_ty.into()],
-        vec![],
-        vec![0],
-        16,
-        16,
-    )
-    .into();
-    let aligned_empty_array_ty = MirArrayType::get(&mut ctx, aligned_element_ty, 0);
-    let underaligned_storage_ty = MirPtrType::get_with_kind(
-        &mut ctx,
-        aligned_empty_array_ty.into(),
-        false,
-        dialect_mir::types::address_space::GLOBAL,
-        MirPointerKind::Erased,
-    );
-    let aligned_empty_unique_ty = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        aligned_empty_array_ty.into(),
-        true,
-        MirPointerKind::UniqueRef,
-    );
-    let underaligned_global_op = Operation::new(
-        &mut ctx,
-        MirGlobalAllocOp::get_concrete_op_info(),
-        vec![underaligned_storage_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let underaligned_global = MirGlobalAllocOp::new(underaligned_global_op);
-    underaligned_global.set_attr_global_type(&ctx, TypeAttr::new(aligned_empty_array_ty.into()));
-    underaligned_global.set_attr_global_key(
-        &ctx,
-        StringAttr::new("underaligned-empty-reference".to_string()),
-    );
-    underaligned_global.set_alignment_value(&mut ctx, 1);
-    underaligned_global_op.deref_mut(&ctx).attributes.set(
-        "global_initializer_hex".try_into().unwrap(),
-        StringAttr::new(String::new()),
-    );
-    underaligned_global.mark_immutable(&mut ctx);
-    assert!(underaligned_global.verify(&ctx).is_ok());
-    let underaligned_storage = underaligned_global_op.deref(&ctx).get_result(0);
-    let underaligned_borrow_op = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![aligned_empty_unique_ty.into()],
-        vec![underaligned_storage],
-        vec![],
-        0,
-    );
-    let underaligned_borrow = MirCastOp::new(underaligned_borrow_op);
-    underaligned_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    underaligned_borrow
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    assert!(
-        underaligned_borrow.verify(&ctx).is_err(),
-        "promoted &mut [Align16; 0] requires at least 16-byte global alignment"
-    );
-
-    let nonempty_storage_ty = MirPtrType::get_with_kind(
-        &mut ctx,
-        nonempty_array_ty.into(),
-        false,
-        dialect_mir::types::address_space::GLOBAL,
-        MirPointerKind::Erased,
-    );
-    let nonempty_unique_ty = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        nonempty_array_ty.into(),
-        true,
-        MirPointerKind::UniqueRef,
-    );
-    let nonempty_global_op = Operation::new(
-        &mut ctx,
-        MirGlobalAllocOp::get_concrete_op_info(),
-        vec![nonempty_storage_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let nonempty_global = MirGlobalAllocOp::new(nonempty_global_op);
-    nonempty_global.set_attr_global_type(&ctx, TypeAttr::new(nonempty_array_ty.into()));
-    nonempty_global.set_attr_global_key(
-        &ctx,
-        StringAttr::new("promoted-nonempty-mutable-reference".to_string()),
-    );
-    nonempty_global.mark_immutable(&mut ctx);
-    assert!(nonempty_global.verify(&ctx).is_ok());
-    let nonempty_global_storage = nonempty_global_op.deref(&ctx).get_result(0);
-    let nonempty_static_borrow_op = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![nonempty_unique_ty.into()],
-        vec![nonempty_global_storage],
-        vec![],
-        0,
-    );
-    let nonempty_static_borrow = MirCastOp::new(nonempty_static_borrow_op);
-    nonempty_static_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    nonempty_static_borrow
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    assert!(
-        nonempty_static_borrow.verify(&ctx).is_err(),
-        "StaticAddress must never manufacture UniqueRef for non-empty promoted storage"
-    );
-
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![empty_storage_ty.into(), empty_unique_ty.into()],
-    );
-    let erased_block_argument = block.deref(&ctx).get_argument(0);
-    let block_argument_borrow_op = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![empty_unique_ty.into()],
-        vec![erased_block_argument],
-        vec![],
-        0,
-    );
-    let block_argument_borrow = MirCastOp::new(block_argument_borrow_op);
-    block_argument_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    block_argument_borrow
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    assert!(
-        block_argument_borrow.verify(&ctx).is_err(),
-        "an Erased [T; 0] block argument has no proven promoted-global lineage"
-    );
-
-    let raw_empty_ty = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        empty_array_ty.into(),
-        false,
-        MirPointerKind::RawConst,
-    );
-    let raw_block = BasicBlock::new(&mut ctx, None, vec![raw_empty_ty.into()]);
-    let raw_empty = raw_block.deref(&ctx).get_argument(0);
-    let erase_raw_op = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![empty_storage_ty.into()],
-        vec![raw_empty],
-        vec![],
-        0,
-    );
-    let erase_raw = MirCastOp::new(erase_raw_op);
-    erase_raw.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    assert!(erase_raw.verify(&ctx).is_ok());
-    let erased_from_raw = erase_raw_op.deref(&ctx).get_result(0);
-    let laundered_borrow_op = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![empty_unique_ty.into()],
-        vec![erased_from_raw],
-        vec![],
-        0,
-    );
-    let laundered_borrow = MirCastOp::new(laundered_borrow_op);
-    laundered_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    laundered_borrow
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    assert!(
-        laundered_borrow.verify(&ctx).is_err(),
-        "RawConst -> Erased must not launder a zero-length pointer into UniqueRef"
-    );
-
-    let byte_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let byte_storage_ty = MirPtrType::get_with_kind(
-        &mut ctx,
-        byte_ty.into(),
-        false,
-        dialect_mir::types::address_space::GLOBAL,
-        MirPointerKind::Erased,
-    );
-    let byte_global_op = Operation::new(
-        &mut ctx,
-        MirGlobalAllocOp::get_concrete_op_info(),
-        vec![byte_storage_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let byte_global = MirGlobalAllocOp::new(byte_global_op);
-    byte_global.set_attr_global_type(&ctx, TypeAttr::new(byte_ty.into()));
-    byte_global.set_attr_global_key(
-        &ctx,
-        StringAttr::new("misaligned-empty-reference-root".to_string()),
-    );
-    byte_global.mark_immutable(&mut ctx);
-    assert!(byte_global.verify(&ctx).is_ok());
-    let byte_storage = byte_global_op.deref(&ctx).get_result(0);
-    let retype_root_op = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![empty_storage_ty.into()],
-        vec![byte_storage],
-        vec![],
-        0,
-    );
-    let retype_root = MirCastOp::new(retype_root_op);
-    retype_root.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    assert!(retype_root.verify(&ctx).is_ok());
-    let retyped_storage = retype_root_op.deref(&ctx).get_result(0);
-    let misaligned_borrow_op = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![empty_unique_ty.into()],
-        vec![retyped_storage],
-        vec![],
-        0,
-    );
-    let misaligned_borrow = MirCastOp::new(misaligned_borrow_op);
-    misaligned_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    misaligned_borrow
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    assert!(
-        misaligned_borrow.verify(&ctx).is_err(),
-        "an immutable byte global cannot be retyped into an aligned &mut [i32; 0] capability"
-    );
-}
-
-fn promoted_empty_unique_ref_verifies(
-    ctx: &mut Context,
-    element_ty: TypeHandle,
-    alignment: u64,
-) -> bool {
-    let empty_array_ty: TypeHandle = MirArrayType::get(ctx, element_ty, 0).into();
-    let storage_ty = MirPtrType::get_with_kind(
-        ctx,
-        empty_array_ty,
-        false,
-        dialect_mir::types::address_space::GLOBAL,
-        MirPointerKind::Erased,
-    );
-    let unique_ty =
-        MirPtrType::get_generic_with_kind(ctx, empty_array_ty, true, MirPointerKind::UniqueRef);
-    let global_op = Operation::new(
-        ctx,
-        MirGlobalAllocOp::get_concrete_op_info(),
-        vec![storage_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let global = MirGlobalAllocOp::new(global_op);
-    global.set_attr_global_type(ctx, TypeAttr::new(empty_array_ty));
-    global.set_attr_global_key(ctx, StringAttr::new("promoted-empty-shape".to_string()));
-    global.set_alignment_value(ctx, alignment);
-    global_op.deref_mut(ctx).attributes.set(
-        "global_initializer_hex".try_into().unwrap(),
-        StringAttr::new(String::new()),
-    );
-    global.mark_immutable(ctx);
-
-    let storage = global_op.deref(ctx).get_result(0);
-    let cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![storage],
-        vec![],
-        0,
-    );
-    let cast = MirCastOp::new(cast_op);
-    cast.set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-    cast.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    cast.verify(ctx).is_ok()
-}
-
-#[test]
-fn test_promoted_empty_alignment_covers_supported_fat_and_unit_elements() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let byte: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-    let word: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-    let unit: TypeHandle = MirTupleType::get(&mut ctx, vec![]).into();
-    let slice: TypeHandle =
-        MirSliceType::get_with_kind(&mut ctx, byte, MirPointerKind::SharedRef).into();
-    let disjoint: TypeHandle = MirDisjointSliceType::get(&mut ctx, byte).into();
-
-    assert!(promoted_empty_unique_ref_verifies(&mut ctx, unit, 1));
-    assert!(promoted_empty_unique_ref_verifies(&mut ctx, slice, 8));
-    assert!(promoted_empty_unique_ref_verifies(&mut ctx, disjoint, 8));
-    assert!(promoted_empty_unique_ref_verifies(&mut ctx, word, 8));
-    assert!(
-        !promoted_empty_unique_ref_verifies(&mut ctx, word, 12),
-        "a non-power-of-two numeric value is not a valid alignment guarantee"
-    );
-    assert!(
-        !promoted_empty_unique_ref_verifies(&mut ctx, slice, 4),
-        "a stored slice value still requires pointer-word alignment"
-    );
-}
-
-#[test]
-fn test_mir_ref_requires_exact_pointer_kind_authority() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let shared_ty = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        i32_ty.into(),
-        false,
-        MirPointerKind::SharedRef,
-    );
-    let unique_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
-    let raw_const_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), false, MirPointerKind::RawConst);
-    let raw_mut_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
-    let erased_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let global_shared_ty = MirPtrType::get_with_kind(
-        &mut ctx,
-        i32_ty.into(),
-        false,
-        dialect_mir::types::address_space::GLOBAL,
-        MirPointerKind::SharedRef,
-    );
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let value = block.deref(&ctx).get_argument(0);
-
-    let build =
-        |ctx: &mut Context, result_ty, mutable, authority: Option<MirPointerKindAuthorityAttr>| {
-            let op = Operation::new(
-                ctx,
-                MirRefOp::get_concrete_op_info(),
-                vec![result_ty],
-                vec![value],
-                vec![],
-                0,
-            );
-            let reference = MirRefOp::new(op);
-            reference.set_mutable(ctx, mutable);
-            if let Some(authority) = authority {
-                reference.set_pointer_kind_authority(ctx, authority);
-            }
-            op
-        };
-
-    for (result_ty, mutable, authority) in [
-        (
-            shared_ty.into(),
-            false,
-            MirPointerKindAuthorityAttr::Reborrow,
-        ),
-        (
-            unique_ty.into(),
-            true,
-            MirPointerKindAuthorityAttr::Reborrow,
-        ),
-        (
-            raw_const_ty.into(),
-            false,
-            MirPointerKindAuthorityAttr::RawAddress,
-        ),
-        (
-            raw_mut_ty.into(),
-            true,
-            MirPointerKindAuthorityAttr::RawAddress,
-        ),
-        (
-            shared_ty.into(),
-            false,
-            MirPointerKindAuthorityAttr::StaticAddress,
-        ),
-    ] {
-        assert!(
-            MirRefOp::new(build(&mut ctx, result_ty, mutable, Some(authority)))
-                .verify(&ctx)
-                .is_ok()
-        );
-    }
-
-    assert!(
-        MirRefOp::new(build(&mut ctx, shared_ty.into(), false, None))
-            .verify(&ctx)
-            .is_err(),
-        "mir.ref must visibly identify its Rust semantic origin"
-    );
-    assert!(
-        MirRefOp::new(build(&mut ctx, erased_ty.into(), false, None))
-            .verify(&ctx)
-            .is_err(),
-        "mir.ref is an explicit pointer-creation boundary, not generic Erased storage"
-    );
-    assert!(
-        MirRefOp::new(build(
-            &mut ctx,
-            shared_ty.into(),
-            false,
-            Some(MirPointerKindAuthorityAttr::RawAddress),
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "RawAddress cannot manufacture SharedRef"
-    );
-    assert!(
-        MirRefOp::new(build(
-            &mut ctx,
-            unique_ty.into(),
-            true,
-            Some(MirPointerKindAuthorityAttr::StaticAddress),
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "constant/static materialization cannot manufacture uniqueness"
-    );
-    assert!(
-        MirRefOp::new(build(
-            &mut ctx,
-            unique_ty.into(),
-            false,
-            Some(MirPointerKindAuthorityAttr::Reborrow),
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "reference kind must agree with the operation's mutability"
-    );
-    assert!(
-        MirRefOp::new(build(
-            &mut ctx,
-            global_shared_ty.into(),
-            false,
-            Some(MirPointerKindAuthorityAttr::Reborrow),
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "mir.ref materializes generic stack storage"
-    );
-}
-
-#[test]
-fn test_aggregate_cast_cannot_hide_pointer_kind_laundering() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let raw_mut_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
-    let unique_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
-    let raw_tuple_ty = MirTupleType::get(&mut ctx, vec![raw_mut_ty.into()]);
-    let unique_tuple_ty = MirTupleType::get(&mut ctx, vec![unique_ty.into()]);
-    let block = BasicBlock::new(&mut ctx, None, vec![raw_tuple_ty.into()]);
-    let raw_tuple = block.deref(&ctx).get_argument(0);
-
-    let build = |ctx: &mut Context, authority: Option<MirPointerKindAuthorityAttr>| {
-        let op = Operation::new(
-            ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![unique_tuple_ty.into()],
-            vec![raw_tuple],
-            vec![],
-            0,
-        );
-        let cast = MirCastOp::new(op);
-        cast.set_attr_cast_kind(ctx, MirCastKindAttr::Transmute);
-        if let Some(authority) = authority {
-            cast.set_pointer_kind_authority(ctx, authority);
-        }
-        op
-    };
-
-    assert!(
-        MirCastOp::new(build(&mut ctx, None)).verify(&ctx).is_err(),
-        "nested RawMut -> UniqueRef laundering must be rejected"
-    );
-    assert!(
-        MirCastOp::new(build(&mut ctx, Some(MirPointerKindAuthorityAttr::Reborrow),))
-            .verify(&ctx)
-            .is_err(),
-        "Rvalue::Ref cannot authorize a nested aggregate transition"
-    );
-    assert!(
-        MirCastOp::new(build(&mut ctx, Some(MirPointerKindAuthorityAttr::RustCast),))
-            .verify(&ctx)
-            .is_ok(),
-        "an explicit rustc aggregate transmute is visible and authorized"
-    );
-}
-
-#[test]
-fn test_aggregate_reinterpretation_requires_rust_cast_authority() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let shared_ty = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        i64_ty.into(),
-        false,
-        MirPointerKind::SharedRef,
-    );
-    // Both tuple declarations list the same pointer at field 0, but its byte
-    // offset changes from 0 to 8. Pairing by declaration index alone would
-    // therefore mistake an integer's old bytes for a preserved reference.
-    let source_ty = MirTupleType::get_with_layout(
-        &mut ctx,
-        vec![shared_ty.into(), i64_ty.into()],
-        vec![0, 1],
-        vec![0, 8],
-        16,
-        8,
-    );
-    let target_ty = MirTupleType::get_with_layout(
-        &mut ctx,
-        vec![shared_ty.into(), i64_ty.into()],
-        vec![1, 0],
-        vec![8, 0],
-        16,
-        8,
-    );
-    let block = BasicBlock::new(&mut ctx, None, vec![source_ty.into()]);
-    let source = block.deref(&ctx).get_argument(0);
-
-    let build = |ctx: &mut Context, authority: Option<MirPointerKindAuthorityAttr>| {
-        let op = Operation::new(
-            ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![target_ty.into()],
-            vec![source],
-            vec![],
-            0,
-        );
-        let cast = MirCastOp::new(op);
-        cast.set_attr_cast_kind(ctx, MirCastKindAttr::Transmute);
-        if let Some(authority) = authority {
-            cast.set_pointer_kind_authority(ctx, authority);
-        }
-        op
-    };
-
-    assert!(
-        MirCastOp::new(build(&mut ctx, None)).verify(&ctx).is_err(),
-        "layout-changing aggregate casts must not infer pointer preservation by field index"
-    );
-    assert!(
-        MirCastOp::new(build(&mut ctx, Some(MirPointerKindAuthorityAttr::RustCast),))
-            .verify(&ctx)
-            .is_ok(),
-        "an explicit rustc transmute makes the representation reinterpretation auditable"
-    );
-}
-
-#[test]
-fn test_generic_aggregate_cast_cannot_invent_erased_pointer_carriers() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let word_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let erased_mut = MirPtrType::get_generic(&mut ctx, word_ty.into(), true);
-    let source_ty = MirTupleType::get_with_layout(
-        &mut ctx,
-        vec![erased_mut.into(), word_ty.into()],
-        vec![0, 1],
-        vec![0, 8],
-        16,
-        8,
-    );
-    let extra_pointer_ty = MirTupleType::get_with_layout(
-        &mut ctx,
-        vec![erased_mut.into(), erased_mut.into()],
-        vec![0, 1],
-        vec![0, 8],
-        16,
-        8,
-    );
-    let moved_pointer_ty = MirTupleType::get_with_layout(
-        &mut ctx,
-        vec![erased_mut.into(), word_ty.into()],
-        vec![1, 0],
-        vec![8, 0],
-        16,
-        8,
-    );
-    let one_pointer = MirArrayType::get(&mut ctx, erased_mut.into(), 1);
-    let two_pointers = MirArrayType::get(&mut ctx, erased_mut.into(), 2);
-
-    let source_block = BasicBlock::new(&mut ctx, None, vec![source_ty.into()]);
-    let source = source_block.deref(&ctx).get_argument(0);
-    let array_block = BasicBlock::new(&mut ctx, None, vec![one_pointer.into()]);
-    let array_source = array_block.deref(&ctx).get_argument(0);
-    let build = |ctx: &mut Context, source, target| {
-        let op = Operation::new(
-            ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![target],
-            vec![source],
-            vec![],
-            0,
-        );
-        MirCastOp::new(op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-        op
-    };
-
-    assert!(
-        MirCastOp::new(build(&mut ctx, source, extra_pointer_ty.into()))
-            .verify(&ctx)
-            .is_err(),
-        "PtrToPtr cannot reinterpret an integer field as writable Erased pointer evidence"
-    );
-    assert!(
-        MirCastOp::new(build(&mut ctx, source, moved_pointer_ty.into()))
-            .verify(&ctx)
-            .is_err(),
-        "field-index equality cannot hide an Erased pointer moving onto integer bytes"
-    );
-    assert!(
-        MirCastOp::new(build(&mut ctx, array_source, two_pointers.into()))
-            .verify(&ctx)
-            .is_err(),
-        "homogeneous array traversal must retain pointer-carrier cardinality"
-    );
-}
-
-#[test]
-fn test_rust_cast_authority_obeys_cast_kind_semantics() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let array_ty = MirArrayType::get(&mut ctx, u8_ty.into(), 4);
-    let raw_mut =
-        MirPtrType::get_generic_with_kind(&mut ctx, u8_ty.into(), true, MirPointerKind::RawMut);
-    let raw_const =
-        MirPtrType::get_generic_with_kind(&mut ctx, u8_ty.into(), false, MirPointerKind::RawConst);
-    let unique =
-        MirPtrType::get_generic_with_kind(&mut ctx, u8_ty.into(), true, MirPointerKind::UniqueRef);
-    let fn_target = MirStructType::get_with_full_layout(
-        &mut ctx,
-        "FnPtrTarget".into(),
-        vec![],
-        vec![],
-        vec![],
-        vec![],
-        0,
-        0,
-    );
-    let fn_target_ty: pliron::r#type::TypeHandle = fn_target.into();
-    let fn_carrier = MirPtrType::get_generic(&mut ctx, fn_target_ty, false);
-    let raw_mut_array =
-        MirPtrType::get_generic_with_kind(&mut ctx, array_ty.into(), true, MirPointerKind::RawMut);
-    let raw_const_array = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        array_ty.into(),
-        false,
-        MirPointerKind::RawConst,
-    );
-    let erased_array = MirPtrType::get_generic(&mut ctx, array_ty.into(), false);
-    let erased_slice = MirSliceType::get(&mut ctx, u8_ty.into());
-    let erased_mut_slice = MirSliceType::get_with_mutability(&mut ctx, u8_ty.into(), true);
-    let raw_const_slice =
-        MirSliceType::get_with_kind(&mut ctx, u8_ty.into(), MirPointerKind::RawConst);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            raw_mut.into(),
-            raw_const.into(),
-            fn_carrier.into(),
-            raw_mut_array.into(),
-            raw_const_array.into(),
-            erased_array.into(),
-            usize_ty.into(),
-        ],
-    );
-    let raw_mut_value = block.deref(&ctx).get_argument(0);
-    let raw_const_value = block.deref(&ctx).get_argument(1);
-    let fn_value = block.deref(&ctx).get_argument(2);
-    let raw_mut_array_value = block.deref(&ctx).get_argument(3);
-    let raw_const_array_value = block.deref(&ctx).get_argument(4);
-    let erased_array_value = block.deref(&ctx).get_argument(5);
-    let integer_value = block.deref(&ctx).get_argument(6);
-
-    let build = |ctx: &mut Context,
-                 source,
-                 target,
-                 kind,
-                 authority: Option<MirPointerKindAuthorityAttr>| {
-        let op = Operation::new(
-            ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![target],
-            vec![source],
-            vec![],
-            0,
-        );
-        let cast = MirCastOp::new(op);
-        cast.set_attr_cast_kind(ctx, kind);
-        if let Some(authority) = authority {
-            cast.set_pointer_kind_authority(ctx, authority);
-        }
-        op
-    };
-    let rust_cast = Some(MirPointerKindAuthorityAttr::RustCast);
-
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            raw_mut_value,
-            unique.into(),
-            MirCastKindAttr::PtrToPtr,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "PtrToPtr cannot use RustCast to invent a reference"
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            raw_mut_value,
-            raw_const.into(),
-            MirCastKindAttr::PtrToPtr,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_ok(),
-        "PtrToPtr may perform an explicit raw-to-raw cast"
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            fn_value,
-            raw_const.into(),
-            MirCastKindAttr::FnPtrToPtr,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_ok(),
-        "FnPtrToPtr may expose an opaque function pointer as a raw pointer"
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            erased_array_value,
-            raw_const.into(),
-            MirCastKindAttr::FnPtrToPtr,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "FnPtrToPtr cannot relabel arbitrary Erased storage as a function pointer"
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            fn_value,
-            unique.into(),
-            MirCastKindAttr::FnPtrToPtr,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_err()
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            raw_mut_value,
-            raw_const.into(),
-            MirCastKindAttr::PointerCoercionMutToConst,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_ok()
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            raw_const_value,
-            raw_mut.into(),
-            MirCastKindAttr::PointerCoercionMutToConst,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_err()
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            raw_mut_value,
-            raw_mut.into(),
-            MirCastKindAttr::PointerCoercionMutToConst,
-            None,
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "MutToConst cannot masquerade as a same-category pointer cast"
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            raw_const_array_value,
-            raw_const_slice.into(),
-            MirCastKindAttr::PointerCoercionUnsize,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_ok(),
-        "Unsize may change thin/fat shape while preserving its carrier"
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            erased_array_value,
-            erased_slice.into(),
-            MirCastKindAttr::PointerCoercionUnsize,
-            None,
-        ))
-        .verify(&ctx)
-        .is_ok(),
-        "an all-Erased unsize still preserves read-only carrier state"
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            erased_array_value,
-            erased_mut_slice.into(),
-            MirCastKindAttr::PointerCoercionUnsize,
-            None,
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "Unsize cannot turn an immutable Erased thin pointer into writable fat evidence"
-    );
-
-    let prefix_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let sized_tail = MirStructType::get_with_full_layout(
-        &mut ctx,
-        "TailCarrier".into(),
-        vec!["prefix".into(), "tail".into()],
-        vec![prefix_ty.into(), array_ty.into()],
-        vec![0, 1],
-        vec![0, 8],
-        16,
-        8,
-    );
-    let shifted_unsized_tail = MirStructType::get_with_full_layout(
-        &mut ctx,
-        "TailCarrier".into(),
-        vec!["prefix".into(), "tail".into()],
-        vec![prefix_ty.into(), u8_ty.into()],
-        vec![0, 1],
-        vec![0, 16],
-        24,
-        8,
-    );
-    let sized_tail_ptr = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        sized_tail.into(),
-        false,
-        MirPointerKind::RawConst,
-    );
-    let shifted_tail_slice = MirSliceType::get_with_kind(
-        &mut ctx,
-        shifted_unsized_tail.into(),
-        MirPointerKind::RawConst,
-    );
-    let tail_block = BasicBlock::new(&mut ctx, None, vec![sized_tail_ptr.into()]);
-    let tail_value = tail_block.deref(&ctx).get_argument(0);
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            tail_value,
-            shifted_tail_slice.into(),
-            MirCastKindAttr::PointerCoercionUnsize,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "Unsize cannot move the trailing data behind a changed struct-field offset"
-    );
-
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            raw_const_array_value,
-            raw_mut.into(),
-            MirCastKindAttr::PointerCoercionArrayToPointer,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "ArrayToPointer cannot strengthen const raw storage to mutable"
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            raw_mut_value,
-            raw_const.into(),
-            MirCastKindAttr::PointerCoercionArrayToPointer,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "ArrayToPointer requires a raw pointer to an array, not an arbitrary pointer"
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            raw_mut_value,
-            raw_mut.into(),
-            MirCastKindAttr::PointerCoercionArrayToPointer,
-            None,
-        ))
-        .verify(&ctx)
-        .is_err(),
-        "an unmarked same-kind ArrayToPointer still requires an array source"
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            raw_mut_array_value,
-            raw_const.into(),
-            MirCastKindAttr::PointerCoercionArrayToPointer,
-            rust_cast.clone(),
-        ))
-        .verify(&ctx)
-        .is_ok()
-    );
-    assert!(
-        MirCastOp::new(build(
-            &mut ctx,
-            integer_value,
-            unique.into(),
-            MirCastKindAttr::Transmute,
-            rust_cast,
-        ))
-        .verify(&ctx)
-        .is_ok(),
-        "only an explicit Transmute may establish an arbitrary pointer category"
-    );
-
-    let word_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let source_wrapper = MirStructType::get_with_full_layout(
-        &mut ctx,
-        "CarrierWrapper".into(),
-        vec!["pointer".into(), "word".into()],
-        vec![unique.into(), word_ty.into()],
-        vec![0, 1],
-        vec![0, 8],
-        16,
-        8,
-    );
-    let moved_wrapper = MirStructType::get_with_full_layout(
-        &mut ctx,
-        "CarrierWrapper".into(),
-        vec!["word".into(), "pointer".into()],
-        vec![word_ty.into(), unique.into()],
-        vec![0, 1],
-        vec![0, 8],
-        16,
-        8,
-    );
-    let wrapper_block = BasicBlock::new(&mut ctx, None, vec![source_wrapper.into()]);
-    let wrapper_value = wrapper_block.deref(&ctx).get_argument(0);
-    for kind in [
-        MirCastKindAttr::PointerCoercionUnsize,
-        MirCastKindAttr::Subtype,
-    ] {
-        assert!(
-            MirCastOp::new(build(
-                &mut ctx,
-                wrapper_value,
-                moved_wrapper.into(),
-                kind,
-                Some(MirPointerKindAuthorityAttr::RustCast),
-            ))
-            .verify(&ctx)
-            .is_err(),
-            "Unsize/Subtype cannot bless a pointer carrier moved onto integer bytes"
-        );
-    }
-}
-
-#[test]
-fn test_pointer_projections_preserve_or_erase_kind_only() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let tuple_ty = MirTupleType::get(&mut ctx, vec![i32_ty.into()]);
-    let array_ty = MirArrayType::get(&mut ctx, i32_ty.into(), 4);
-    let raw_tuple_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, tuple_ty.into(), true, MirPointerKind::RawMut);
-    let raw_array_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, array_ty.into(), true, MirPointerKind::RawMut);
-    let raw_field_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
-    let erased_field_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let erased_read_field_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let unique_field_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![raw_tuple_ty.into(), raw_array_ty.into(), usize_ty.into()],
-    );
-    let tuple = block.deref(&ctx).get_argument(0);
-    let array = block.deref(&ctx).get_argument(1);
-    let index = block.deref(&ctx).get_argument(2);
-
-    let field = |ctx: &mut Context, result_ty| {
-        let op = Operation::new(
-            ctx,
-            MirFieldAddrOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![tuple],
-            vec![],
-            0,
-        );
-        MirFieldAddrOp::new(op).set_attr_field_index(ctx, FieldIndexAttr(0));
-        MirFieldAddrOp::new(op).set_attr_aggregate_ty(ctx, TypeAttr::new(tuple_ty.into()));
-        op
-    };
-    assert!(
-        MirFieldAddrOp::new(field(&mut ctx, raw_field_ty.into()))
-            .verify(&ctx)
-            .is_ok()
-    );
-    assert!(
-        MirFieldAddrOp::new(field(&mut ctx, erased_field_ty.into()))
-            .verify(&ctx)
-            .is_ok()
-    );
-    assert!(
-        MirFieldAddrOp::new(field(&mut ctx, unique_field_ty.into()))
-            .verify(&ctx)
-            .is_err()
-    );
-    assert!(
-        MirFieldAddrOp::new(field(&mut ctx, erased_read_field_ty.into()))
-            .verify(&ctx)
-            .is_err(),
-        "field projection cannot flip an Erased address from writable to read-only"
-    );
-
-    let array_launder = Operation::new(
-        &mut ctx,
-        MirArrayElementAddrOp::get_concrete_op_info(),
-        vec![unique_field_ty.into()],
-        vec![array, index],
-        vec![],
-        0,
-    );
-    assert!(
-        MirArrayElementAddrOp::new(array_launder)
-            .verify(&ctx)
-            .is_err()
-    );
-    let array_erase = Operation::new(
-        &mut ctx,
-        MirArrayElementAddrOp::get_concrete_op_info(),
-        vec![erased_field_ty.into()],
-        vec![array, index],
-        vec![],
-        0,
-    );
-    assert!(
-        MirArrayElementAddrOp::new(array_erase).verify(&ctx).is_ok(),
-        "projection may erase kind while preserving machine mutability"
-    );
-    let array_mutability_flip = Operation::new(
-        &mut ctx,
-        MirArrayElementAddrOp::get_concrete_op_info(),
-        vec![erased_read_field_ty.into()],
-        vec![array, index],
-        vec![],
-        0,
-    );
-    assert!(
-        MirArrayElementAddrOp::new(array_mutability_flip)
-            .verify(&ctx)
-            .is_err(),
-        "array projection cannot change machine mutability"
-    );
-}
-
-#[test]
-fn test_pointer_with_exposed_provenance_only_creates_raw_or_erased_pointer() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let fn_target = MirStructType::get_with_full_layout(
-        &mut ctx,
-        "FnPtrTarget".into(),
-        vec![],
-        vec![],
-        vec![],
-        vec![],
-        0,
-        0,
-    );
-    let fn_target_ty: pliron::r#type::TypeHandle = fn_target.into();
-    let raw_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
-    let opaque_fn_ty = MirPtrType::get_generic(&mut ctx, fn_target_ty, false);
-    let arbitrary_erased_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let writable_erased_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let unique_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
-    let block = BasicBlock::new(&mut ctx, None, vec![usize_ty.into()]);
-    let address = block.deref(&ctx).get_argument(0);
-
-    let build = |ctx: &mut Context, result_ty| {
-        let op = Operation::new(
-            ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![address],
-            vec![],
-            0,
-        );
-        let cast = MirCastOp::new(op);
-        cast.set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
-        cast.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::RustCast);
-        op
-    };
-
-    assert!(
-        MirCastOp::new(build(&mut ctx, raw_ty.into()))
-            .verify(&ctx)
-            .is_ok()
-    );
-    assert!(
-        MirCastOp::new(build(&mut ctx, unique_ty.into()))
-            .verify(&ctx)
-            .is_err(),
-        "integer provenance cannot directly materialize a Rust reference"
-    );
-
-    let build_unmarked = |ctx: &mut Context, result_ty| {
-        let op = Operation::new(
-            ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![address],
-            vec![],
-            0,
-        );
-        MirCastOp::new(op).set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
-        op
-    };
-    assert!(
-        MirCastOp::new(build_unmarked(&mut ctx, opaque_fn_ty.into()))
-            .verify(&ctx)
-            .is_ok(),
-        "function-pointer tokens may materialize only the canonical immutable Erased carrier"
-    );
-    assert!(
-        MirCastOp::new(build_unmarked(&mut ctx, arbitrary_erased_ty.into()))
-            .verify(&ctx)
-            .is_err(),
-        "an integer cannot manufacture arbitrary Erased pointer evidence"
-    );
-    assert!(
-        MirCastOp::new(build_unmarked(&mut ctx, writable_erased_ty.into()))
-            .verify(&ctx)
-            .is_err(),
-        "an integer cannot manufacture writable Erased evidence and then reborrow it as UniqueRef"
-    );
-
-    let fn_block = BasicBlock::new(&mut ctx, None, vec![opaque_fn_ty.into()]);
-    let opaque_fn = fn_block.deref(&ctx).get_argument(0);
-    let disguised_data_pointer = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![arbitrary_erased_ty.into()],
-        vec![opaque_fn],
-        vec![],
-        0,
-    );
-    MirCastOp::new(disguised_data_pointer)
-        .set_attr_cast_kind(&ctx, MirCastKindAttr::PointerCoercionArrayToPointer);
-    assert!(
-        MirCastOp::new(disguised_data_pointer).verify(&ctx).is_err(),
-        "an unrelated coercion cannot turn the opaque function token into Erased data storage"
-    );
-
-    let shared_fn_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, fn_target_ty, false, MirPointerKind::SharedRef);
-    let fake_reborrow = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![shared_fn_ty.into()],
-        vec![opaque_fn],
-        vec![],
-        0,
-    );
-    let fake_reborrow = MirCastOp::new(fake_reborrow);
-    fake_reborrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    fake_reborrow.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    assert!(
-        fake_reborrow.verify(&ctx).is_err(),
-        "an opaque function-pointer value is not compiler storage that may be reborrowed"
-    );
-
-    // Keeping only kind+mutability while recursively pairing aggregate fields
-    // is insufficient: the canonical function token is also identified by
-    // its pointee. Otherwise a tuple cast can disguise data storage as a
-    // function pointer (or vice versa), after which individually legal casts
-    // can manufacture a reference.
-    let data_tuple_ty = MirTupleType::get(&mut ctx, vec![arbitrary_erased_ty.into()]);
-    let fn_tuple_ty = MirTupleType::get(&mut ctx, vec![opaque_fn_ty.into()]);
-    let nested_block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![data_tuple_ty.into(), fn_tuple_ty.into()],
-    );
-    let data_tuple = nested_block.deref(&ctx).get_argument(0);
-    let fn_tuple = nested_block.deref(&ctx).get_argument(1);
-    let nested_cast = |ctx: &mut Context, source, target| {
-        let op = Operation::new(
-            ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![target],
-            vec![source],
-            vec![],
-            0,
-        );
-        MirCastOp::new(op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-        op
-    };
-    let data_to_fn = nested_cast(&mut ctx, data_tuple, fn_tuple_ty.into());
-    assert!(
-        MirCastOp::new(data_to_fn).verify(&ctx).is_err(),
-        "an aggregate cast cannot manufacture a nested canonical function token"
-    );
-    assert!(
-        MirCastOp::new(nested_cast(&mut ctx, fn_tuple, data_tuple_ty.into(),))
-            .verify(&ctx)
-            .is_err(),
-        "an aggregate cast cannot disguise a nested function token as Erased data"
-    );
-
-    let forged_fn_tuple = data_to_fn.deref(&ctx).get_result(0);
-    let extract_forged_fn = Operation::new(
-        &mut ctx,
-        MirExtractFieldOp::get_concrete_op_info(),
-        vec![opaque_fn_ty.into()],
-        vec![forged_fn_tuple],
-        vec![],
-        0,
-    );
-    let extract_forged_fn = MirExtractFieldOp::new(extract_forged_fn);
-    extract_forged_fn.set_attr_index(&ctx, FieldIndexAttr(0));
-    assert!(extract_forged_fn.verify(&ctx).is_ok());
-
-    let forged_fn = extract_forged_fn.get_operation().deref(&ctx).get_result(0);
-    let expose_forged_fn = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![raw_ty.into()],
-        vec![forged_fn],
-        vec![],
-        0,
-    );
-    let expose_forged_fn = MirCastOp::new(expose_forged_fn);
-    expose_forged_fn.set_attr_cast_kind(&ctx, MirCastKindAttr::FnPtrToPtr);
-    expose_forged_fn.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RustCast);
-    assert!(expose_forged_fn.verify(&ctx).is_ok());
-
-    let forged_raw = expose_forged_fn.get_operation().deref(&ctx).get_result(0);
-    let reborrow_forged_fn = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![forged_raw],
-        vec![],
-        0,
-    );
-    let reborrow_forged_fn = MirCastOp::new(reborrow_forged_fn);
-    reborrow_forged_fn.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    reborrow_forged_fn.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    assert!(
-        reborrow_forged_fn.verify(&ctx).is_ok(),
-        "the laundering chain must be rejected at its aggregate reinterpretation"
-    );
-
-    let shared_marker_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, fn_target_ty, false, MirPointerKind::SharedRef);
-    let marker_tuple_ty = MirTupleType::get(&mut ctx, vec![fn_target_ty]);
-    let shared_marker_tuple_ty = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        marker_tuple_ty.into(),
-        false,
-        MirPointerKind::SharedRef,
-    );
-    let marker_array_ty = MirArrayType::get(&mut ctx, fn_target_ty, 1);
-    let shared_marker_array_ty = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        marker_array_ty.into(),
-        false,
-        MirPointerKind::SharedRef,
-    );
-    let shared_marker_slice_ty =
-        MirSliceType::get_with_kind(&mut ctx, fn_target_ty, MirPointerKind::SharedRef);
-    let projection_block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            shared_marker_ty.into(),
-            shared_marker_tuple_ty.into(),
-            shared_marker_array_ty.into(),
-            shared_marker_slice_ty.into(),
-            usize_ty.into(),
-        ],
-    );
-    let marker_address = projection_block.deref(&ctx).get_argument(0);
-    let marker_tuple_address = projection_block.deref(&ctx).get_argument(1);
-    let marker_array_address = projection_block.deref(&ctx).get_argument(2);
-    let marker_slice = projection_block.deref(&ctx).get_argument(3);
-    let zero = projection_block.deref(&ctx).get_argument(4);
-
-    let offset_to_token = Operation::new(
-        &mut ctx,
-        MirPtrOffsetOp::get_concrete_op_info(),
-        vec![opaque_fn_ty.into()],
-        vec![marker_address, zero],
-        vec![],
-        0,
-    );
-    assert!(
-        MirPtrOffsetOp::new(offset_to_token).verify(&ctx).is_err(),
-        "pointer arithmetic produces a data address, never a function token"
-    );
-
-    let field_address_to_token = Operation::new(
-        &mut ctx,
-        MirFieldAddrOp::get_concrete_op_info(),
-        vec![opaque_fn_ty.into()],
-        vec![marker_tuple_address],
-        vec![],
-        0,
-    );
-    let field_address_to_token = MirFieldAddrOp::new(field_address_to_token);
-    field_address_to_token.set_attr_field_index(&ctx, FieldIndexAttr(0));
-    assert!(
-        field_address_to_token.verify(&ctx).is_err(),
-        "a field address cannot masquerade as a function token"
-    );
-
-    let array_address_to_token = Operation::new(
-        &mut ctx,
-        MirArrayElementAddrOp::get_concrete_op_info(),
-        vec![opaque_fn_ty.into()],
-        vec![marker_array_address, zero],
-        vec![],
-        0,
-    );
-    assert!(
-        MirArrayElementAddrOp::new(array_address_to_token)
-            .verify(&ctx)
-            .is_err(),
-        "an array element address cannot masquerade as a function token"
-    );
-
-    let slice_data_to_token = Operation::new(
-        &mut ctx,
-        MirExtractFieldOp::get_concrete_op_info(),
-        vec![opaque_fn_ty.into()],
-        vec![marker_slice],
-        vec![],
-        0,
-    );
-    let slice_data_to_token = MirExtractFieldOp::new(slice_data_to_token);
-    slice_data_to_token.set_attr_index(&ctx, FieldIndexAttr(0));
-    assert!(
-        slice_data_to_token.verify(&ctx).is_err(),
-        "a slice data address cannot masquerade as a function token"
-    );
-
-    // A ClosureFnPointer cast must not extract captured reference bits as a
-    // function pointer, expose them as RawMut, and then reborrow them as
-    // UniqueRef. Only a genuinely non-capturing, zero-sized closure may enter
-    // the opaque function-pointer path.
-    let captured_ref = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        i32_ty.into(),
-        false,
-        MirPointerKind::SharedRef,
-    );
-    let captured_closure = MirStructType::get_with_full_layout(
-        &mut ctx,
-        "CapturedClosure".into(),
-        vec!["capture_0".into()],
-        vec![captured_ref.into()],
-        vec![0],
-        vec![0],
-        8,
-        8,
-    );
-    let empty_closure = MirStructType::get_with_full_layout(
-        &mut ctx,
-        "NonCapturingClosure".into(),
-        vec![],
-        vec![],
-        vec![],
-        vec![],
-        0,
-        1,
-    );
-    let closure_block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![captured_closure.into(), empty_closure.into()],
-    );
-    let captured_value = closure_block.deref(&ctx).get_argument(0);
-    let empty_value = closure_block.deref(&ctx).get_argument(1);
-    let closure_cast = |ctx: &mut Context, source| {
-        let op = Operation::new(
-            ctx,
-            MirCastOp::get_concrete_op_info(),
-            vec![opaque_fn_ty.into()],
-            vec![source],
-            vec![],
-            0,
-        );
-        MirCastOp::new(op)
-            .set_attr_cast_kind(ctx, MirCastKindAttr::PointerCoercionClosureFnPointer);
-        op
-    };
-    let captured_to_fn = closure_cast(&mut ctx, captured_value);
-    assert!(
-        MirCastOp::new(captured_to_fn).verify(&ctx).is_err(),
-        "a closure carrying SharedRef bytes cannot become an opaque function pointer"
-    );
-    assert!(
-        MirCastOp::new(closure_cast(&mut ctx, empty_value))
-            .verify(&ctx)
-            .is_err(),
-        "the importer materializes a closure function token directly; the legacy cast is not lowerable"
-    );
-
-    let captured_fn_value = captured_to_fn.deref(&ctx).get_result(0);
-    let exposed_capture = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![raw_ty.into()],
-        vec![captured_fn_value],
-        vec![],
-        0,
-    );
-    let exposed_capture = MirCastOp::new(exposed_capture);
-    exposed_capture.set_attr_cast_kind(&ctx, MirCastKindAttr::FnPtrToPtr);
-    exposed_capture.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RustCast);
-    assert!(exposed_capture.verify(&ctx).is_ok());
-
-    let exposed_capture_value = exposed_capture.get_operation().deref(&ctx).get_result(0);
-    let unique_capture = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_ty.into()],
-        vec![exposed_capture_value],
-        vec![],
-        0,
-    );
-    let unique_capture = MirCastOp::new(unique_capture);
-    unique_capture.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    unique_capture.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    assert!(
-        unique_capture.verify(&ctx).is_ok(),
-        "the chain must be stopped at ClosureFnPointer before later individually legal boundaries"
-    );
-}
-
-#[test]
-fn test_mir_extract_field_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let tuple_ty = MirTupleType::get(&mut ctx, vec![i32_ty.into(), i32_ty.into()]);
-
-    let block = BasicBlock::new(&mut ctx, None, vec![tuple_ty.into()]);
-    let tuple_val = block.deref(&ctx).get_argument(0);
-
-    let op = Operation::new(
-        &mut ctx,
-        MirExtractFieldOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![tuple_val],
-        vec![],
-        0,
-    );
-    let extract_op = MirExtractFieldOp::new(op);
-    extract_op.set_attr_index(&ctx, dialect_mir::attributes::FieldIndexAttr(0));
-    assert!(extract_op.verify(&ctx).is_ok(), "Valid Tuple Extract");
-
-    let op_oob = Operation::new(
-        &mut ctx,
-        MirExtractFieldOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![tuple_val],
-        vec![],
-        0,
-    );
-    let extract_op_oob = MirExtractFieldOp::new(op_oob);
-    extract_op_oob.set_attr_index(&ctx, dialect_mir::attributes::FieldIndexAttr(2));
-    assert!(extract_op_oob.verify(&ctx).is_err(), "OOB Index");
-
-    let union_ty = MirUnionType::get(
-        &mut ctx,
-        "Bits".into(),
-        vec!["word".into(), "alias".into()],
-        vec![i32_ty.into(), i32_ty.into()],
-        4,
-        4,
-    );
-    let union_block = BasicBlock::new(&mut ctx, None, vec![union_ty.into()]);
-    let union_val = union_block.deref(&ctx).get_argument(0);
-    let union_extract = Operation::new(
-        &mut ctx,
-        MirExtractFieldOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![union_val],
-        vec![],
-        0,
-    );
-    let union_extract = MirExtractFieldOp::new(union_extract);
-    union_extract.set_attr_index(&ctx, dialect_mir::attributes::FieldIndexAttr(1));
-    assert!(union_extract.verify(&ctx).is_ok(), "Valid union extract");
-}
-
-#[test]
-fn test_mir_construct_disjoint_slice_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let f32_ty = FP32Type::get(&ctx);
-    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let width_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let f32_ptr_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, f32_ty.into(), true, MirPointerKind::RawMut);
-    let plain_ty = MirDisjointSliceType::get(&mut ctx, f32_ty.into());
-    let width_ty_handle: pliron::r#type::TypeHandle = width_ty.into();
-    let row_width_ty =
-        MirDisjointSliceType::get_with_space(&mut ctx, f32_ty.into(), vec![width_ty_handle]);
-
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![f32_ptr_ty.into(), usize_ty.into(), width_ty.into()],
-    );
-    let ptr_val = block.deref(&ctx).get_argument(0);
-    let len_val = block.deref(&ctx).get_argument(1);
-    let width_val = block.deref(&ctx).get_argument(2);
-
-    // Valid: an index space with no runtime layout takes two operands.
-    let op = Operation::new(
-        &mut ctx,
-        MirConstructDisjointSliceOp::get_concrete_op_info(),
-        vec![plain_ty.into()],
-        vec![ptr_val, len_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructDisjointSliceOp::new(op).verify(&ctx).is_ok(),
-        "Valid space-free disjoint slice construction"
-    );
-
-    // Valid: a runtime row width takes a third operand.
-    let op_width = Operation::new(
-        &mut ctx,
-        MirConstructDisjointSliceOp::get_concrete_op_info(),
-        vec![row_width_ty.into()],
-        vec![ptr_val, len_val, width_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructDisjointSliceOp::new(op_width)
-            .verify(&ctx)
-            .is_ok(),
-        "Valid row-width disjoint slice construction"
-    );
-
-    let erased_ptr_ty = MirPtrType::get_generic(&mut ctx, f32_ty.into(), true);
-    let erased_block = BasicBlock::new(&mut ctx, None, vec![erased_ptr_ty.into()]);
-    let erased_ptr = erased_block.deref(&ctx).get_argument(0);
-    let op_erased_data = Operation::new(
-        &mut ctx,
-        MirConstructDisjointSliceOp::get_concrete_op_info(),
-        vec![plain_ty.into()],
-        vec![erased_ptr, len_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructDisjointSliceOp::new(op_erased_data)
-            .verify(&ctx)
-            .is_err(),
-        "DisjointSlice's fixed RawMut field cannot be reconstructed from Erased"
-    );
-
-    // Invalid: the row width is missing, so the slice would carry whatever
-    // slot 2 held.
-    let op_missing_width = Operation::new(
-        &mut ctx,
-        MirConstructDisjointSliceOp::get_concrete_op_info(),
-        vec![row_width_ty.into()],
-        vec![ptr_val, len_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructDisjointSliceOp::new(op_missing_width)
-            .verify(&ctx)
-            .is_err(),
-        "Missing index-space operand"
-    );
-
-    // Invalid: a space-free slice given a third operand.
-    let op_extra = Operation::new(
-        &mut ctx,
-        MirConstructDisjointSliceOp::get_concrete_op_info(),
-        vec![plain_ty.into()],
-        vec![ptr_val, len_val, width_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructDisjointSliceOp::new(op_extra)
-            .verify(&ctx)
-            .is_err(),
-        "Index-space operand for a space-free slice"
-    );
-
-    // Invalid: the row width operand has the wrong width, which would write a
-    // 64-bit value into the 32-bit row width slot.
-    let op_wrong_width_ty = Operation::new(
-        &mut ctx,
-        MirConstructDisjointSliceOp::get_concrete_op_info(),
-        vec![row_width_ty.into()],
-        vec![ptr_val, len_val, len_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructDisjointSliceOp::new(op_wrong_width_ty)
-            .verify(&ctx)
-            .is_err(),
-        "Index-space operand type mismatch"
-    );
-
-    // Invalid: result is a plain slice, which `mir.construct_slice` owns.
-    let plain_slice_ty = MirSliceType::get(&mut ctx, f32_ty.into());
-    let op_bad_res = Operation::new(
-        &mut ctx,
-        MirConstructDisjointSliceOp::get_concrete_op_info(),
-        vec![plain_slice_ty.into()],
-        vec![ptr_val, len_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructDisjointSliceOp::new(op_bad_res)
-            .verify(&ctx)
-            .is_err(),
-        "Result must be a disjoint slice type"
-    );
-}
-
-#[test]
-fn test_mir_construct_slice_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let u8_ptr_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
-    let u8_slice_ty = MirSliceType::get(&mut ctx, u8_ty.into());
-    let i32_slice_ty = MirSliceType::get(&mut ctx, i32_ty.into());
-
-    let block = BasicBlock::new(&mut ctx, None, vec![u8_ptr_ty.into(), usize_ty.into()]);
-    let ptr_val = block.deref(&ctx).get_argument(0);
-    let len_val = block.deref(&ctx).get_argument(1);
-
-    // Valid: (ptr to u8, usize len) -> slice of u8
-    let op = Operation::new(
-        &mut ctx,
-        MirConstructSliceOp::get_concrete_op_info(),
-        vec![u8_slice_ty.into()],
-        vec![ptr_val, len_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructSliceOp::new(op).verify(&ctx).is_ok(),
-        "Valid slice construction"
-    );
-
-    // Invalid: data pointer pointee does not match slice element type
-    let op_bad_elem = Operation::new(
-        &mut ctx,
-        MirConstructSliceOp::get_concrete_op_info(),
-        vec![i32_slice_ty.into()],
-        vec![ptr_val, len_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructSliceOp::new(op_bad_elem).verify(&ctx).is_err(),
-        "Pointee/element mismatch"
-    );
-
-    // Invalid: operands swapped (length where the pointer should be)
-    let op_swapped = Operation::new(
-        &mut ctx,
-        MirConstructSliceOp::get_concrete_op_info(),
-        vec![u8_slice_ty.into()],
-        vec![len_val, ptr_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructSliceOp::new(op_swapped).verify(&ctx).is_err(),
-        "Swapped operands"
-    );
-
-    // Invalid: result is not a slice type
-    let op_bad_res = Operation::new(
-        &mut ctx,
-        MirConstructSliceOp::get_concrete_op_info(),
-        vec![u8_ptr_ty.into()],
-        vec![ptr_val, len_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirConstructSliceOp::new(op_bad_res).verify(&ctx).is_err(),
-        "Non-slice result type"
-    );
-}
-
-#[test]
-fn test_slice_carrier_cannot_launder_pointer_kind() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let raw_mut_ptr =
-        MirPtrType::get_generic_with_kind(&mut ctx, u8_ty.into(), true, MirPointerKind::RawMut);
-    let erased_ptr = MirPtrType::get_generic(&mut ctx, u8_ty.into(), true);
-    let erased_const_ptr = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
-    let global_raw_mut_ptr = MirPtrType::get_with_kind(
-        &mut ctx,
-        u8_ty.into(),
-        true,
-        dialect_mir::types::address_space::GLOBAL,
-        MirPointerKind::RawMut,
-    );
-    let unique_ptr =
-        MirPtrType::get_generic_with_kind(&mut ctx, u8_ty.into(), true, MirPointerKind::UniqueRef);
-    let raw_mut_slice = MirSliceType::get_with_kind(&mut ctx, u8_ty.into(), MirPointerKind::RawMut);
-    let unique_slice =
-        MirSliceType::get_with_kind(&mut ctx, u8_ty.into(), MirPointerKind::UniqueRef);
-    let erased_slice = MirSliceType::get(&mut ctx, u8_ty.into());
-    let erased_mut_slice = MirSliceType::get_with_mutability(&mut ctx, u8_ty.into(), true);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            raw_mut_ptr.into(),
-            erased_ptr.into(),
-            erased_const_ptr.into(),
-            global_raw_mut_ptr.into(),
-            usize_ty.into(),
-            raw_mut_slice.into(),
-            erased_slice.into(),
-            erased_mut_slice.into(),
-        ],
-    );
-    let raw_mut = block.deref(&ctx).get_argument(0);
-    let erased = block.deref(&ctx).get_argument(1);
-    let erased_const = block.deref(&ctx).get_argument(2);
-    let global_raw_mut = block.deref(&ctx).get_argument(3);
-    let len = block.deref(&ctx).get_argument(4);
-    let raw_slice = block.deref(&ctx).get_argument(5);
-    let erased_slice_value = block.deref(&ctx).get_argument(6);
-    let erased_mut_slice_value = block.deref(&ctx).get_argument(7);
-
-    let construct = |ctx: &mut Context, data, result_ty| {
-        Operation::new(
-            ctx,
-            MirConstructSliceOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![data, len],
-            vec![],
-            0,
-        )
-    };
-    assert!(
-        MirConstructSliceOp::new(construct(&mut ctx, raw_mut, raw_mut_slice.into()))
-            .verify(&ctx)
-            .is_ok()
-    );
-    assert!(
-        MirConstructSliceOp::new(construct(&mut ctx, raw_mut, unique_slice.into()))
-            .verify(&ctx)
-            .is_err(),
-        "construct_slice must not turn RawMut into UniqueRef"
-    );
-    assert!(
-        MirConstructSliceOp::new(construct(&mut ctx, erased, raw_mut_slice.into()))
-            .verify(&ctx)
-            .is_err(),
-        "construct_slice must not recover RawMut from Erased"
-    );
-    assert!(
-        MirConstructSliceOp::new(construct(&mut ctx, global_raw_mut, raw_mut_slice.into()))
-            .verify(&ctx)
-            .is_err(),
-        "ordinary slice carriers always use generic address space"
-    );
-    assert!(
-        MirConstructSliceOp::new(construct(&mut ctx, erased_const, erased_slice.into()))
-            .verify(&ctx)
-            .is_ok(),
-        "an immutable Erased data pointer constructs an immutable Erased slice"
-    );
-
-    let extract = |ctx: &mut Context, result_ty| {
-        let op = Operation::new(
-            ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![raw_slice],
-            vec![],
-            0,
-        );
-        MirExtractFieldOp::new(op).set_attr_index(ctx, FieldIndexAttr(0));
-        op
-    };
-    assert!(
-        MirExtractFieldOp::new(extract(&mut ctx, raw_mut_ptr.into()))
-            .verify(&ctx)
-            .is_ok()
-    );
-    assert!(
-        MirExtractFieldOp::new(extract(&mut ctx, erased_ptr.into()))
-            .verify(&ctx)
-            .is_ok(),
-        "slice extraction may deliberately erase a concrete kind"
-    );
-    assert!(
-        MirExtractFieldOp::new(extract(&mut ctx, unique_ptr.into()))
-            .verify(&ctx)
-            .is_err(),
-        "slice extraction must not change RawMut into UniqueRef"
-    );
-    assert!(
-        MirExtractFieldOp::new(extract(&mut ctx, global_raw_mut_ptr.into()))
-            .verify(&ctx)
-            .is_err(),
-        "ordinary slice extraction cannot invent a non-generic address space"
-    );
-    assert!(
-        MirExtractFieldOp::new(extract(&mut ctx, erased_const_ptr.into()))
-            .verify(&ctx)
-            .is_err(),
-        "erasing a concrete slice kind must preserve machine mutability"
-    );
-
-    let extract_erased = |ctx: &mut Context, result_ty| {
-        let op = Operation::new(
-            ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![erased_slice_value],
-            vec![],
-            0,
-        );
-        MirExtractFieldOp::new(op).set_attr_index(ctx, FieldIndexAttr(0));
-        op
-    };
-    assert!(
-        MirExtractFieldOp::new(extract_erased(&mut ctx, erased_const_ptr.into()))
-            .verify(&ctx)
-            .is_ok(),
-        "an immutable Erased slice extracts an immutable Erased data pointer"
-    );
-    assert!(
-        MirExtractFieldOp::new(extract_erased(&mut ctx, erased_ptr.into()))
-            .verify(&ctx)
-            .is_err(),
-        "an immutable Erased slice cannot manufacture writable data-pointer evidence"
-    );
-
-    let extract_erased_mut = |ctx: &mut Context, result_ty| {
-        let op = Operation::new(
-            ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![erased_mut_slice_value],
-            vec![],
-            0,
-        );
-        MirExtractFieldOp::new(op).set_attr_index(ctx, FieldIndexAttr(0));
-        op
-    };
-    assert!(
-        MirExtractFieldOp::new(extract_erased_mut(&mut ctx, erased_ptr.into()))
-            .verify(&ctx)
-            .is_ok(),
-        "a mutable Erased slice retains writable data-pointer evidence"
-    );
-
-    let immutable_slice_reborrow = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_slice.into()],
-        vec![erased_slice_value],
-        vec![],
-        0,
-    );
-    let immutable_slice_reborrow = MirCastOp::new(immutable_slice_reborrow);
-    immutable_slice_reborrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    immutable_slice_reborrow
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    assert!(
-        immutable_slice_reborrow.verify(&ctx).is_err(),
-        "an immutable Erased slice cannot be reborrowed as UniqueRef"
-    );
-
-    let mutable_slice_reborrow = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![unique_slice.into()],
-        vec![erased_mut_slice_value],
-        vec![],
-        0,
-    );
-    let mutable_slice_reborrow = MirCastOp::new(mutable_slice_reborrow);
-    mutable_slice_reborrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    mutable_slice_reborrow
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    assert!(
-        mutable_slice_reborrow.verify(&ctx).is_ok(),
-        "a mutable Erased slice may establish UniqueRef at a real reborrow boundary"
-    );
-}
-
-#[test]
-fn test_mir_arithmetic_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), i32_ty.into()]);
-    let lhs = block.deref(&ctx).get_argument(0);
-
-    let check_bin_op = |opid: (
-        fn(pliron::context::Ptr<pliron::operation::Operation>) -> pliron::op::OpObj,
-        std::any::TypeId,
-    ),
-                        name: &str| {
-        let mut context = Context::new();
-        dialect_mir::register(&mut context);
-        let ty = IntegerType::get(&context, 32, Signedness::Signed);
-        let blk = BasicBlock::new(&mut context, None, vec![ty.into(), ty.into()]);
-        let l = blk.deref(&context).get_argument(0);
-        let r = blk.deref(&context).get_argument(1);
-
-        let op = Operation::new(&mut context, opid, vec![ty.into()], vec![l, r], vec![], 0);
-        assert!(op.verify(&context).is_ok(), "Valid {}", name);
-
-        let f32_t = FP32Type::get(&context);
-        let blk2 = BasicBlock::new(&mut context, None, vec![f32_t.into()]);
-        let f32_val = blk2.deref(&context).get_argument(0);
-
-        let op_bad = Operation::new(
-            &mut context,
-            opid,
-            vec![ty.into()],
-            vec![l, f32_val],
-            vec![],
-            0,
-        );
-        assert!(op_bad.verify(&context).is_err(), "Type mismatch {}", name);
-    };
-
-    check_bin_op(MirAddOp::get_concrete_op_info(), "Add");
-    check_bin_op(MirSubOp::get_concrete_op_info(), "Sub");
-    check_bin_op(MirMulOp::get_concrete_op_info(), "Mul");
-    check_bin_op(MirDivOp::get_concrete_op_info(), "Div");
-    check_bin_op(MirRemOp::get_concrete_op_info(), "Rem");
-
-    let op_neg = Operation::new(
-        &mut ctx,
-        MirNegOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![lhs],
-        vec![],
-        0,
-    );
-    assert!(op_neg.verify(&ctx).is_ok(), "Valid Neg");
-
-    let f32_ty = FP32Type::get(&ctx);
-    let op_neg_bad = Operation::new(
-        &mut ctx,
-        MirNegOp::get_concrete_op_info(),
-        vec![f32_ty.into()],
-        vec![lhs],
-        vec![],
-        0,
-    );
-    assert!(op_neg_bad.verify(&ctx).is_err(), "Neg type mismatch");
-
-    let op_not = Operation::new(
-        &mut ctx,
-        MirNotOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![lhs],
-        vec![],
-        0,
-    );
-    assert!(op_not.verify(&ctx).is_ok(), "Valid Not");
-}
-
-#[test]
-fn test_mir_misc_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signed);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-
-    // 1. MirConstantOp
-    let i32_signless = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let width = NonZeroUsize::new(32).unwrap();
-    let apint = APInt::from_u32(42, width);
-    let int_attr = IntegerAttr::new(i32_signless, apint);
-
-    let const_op_ptr = Operation::new(
-        &mut ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![i32_signless.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let const_op = MirConstantOp::new(const_op_ptr);
-    const_op.set_attr_value(&ctx, int_attr);
-    assert!(const_op.verify(&ctx).is_ok(), "Valid Constant");
-
-    // Mismatch type
-    let i64_signless = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let i64_width = NonZeroUsize::new(64).unwrap();
-    let i64_attr = IntegerAttr::new(i64_signless, APInt::from_u64(42, i64_width));
-    const_op.set_attr_value(&ctx, i64_attr);
-    assert!(const_op.verify(&ctx).is_err(), "Constant type mismatch");
-
-    // 2. MirCastOp
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let arg = block.deref(&ctx).get_argument(0);
-
-    let cast_op = Operation::new(
-        &mut ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![arg],
-        vec![],
-        0,
-    );
-    MirCastOp::new(cast_op).set_attr_cast_kind(&ctx, MirCastKindAttr::IntToInt);
-    assert!(MirCastOp::new(cast_op).verify(&ctx).is_ok(), "Valid Cast");
-
-    // 3. MirCheckedAddOp
-    let tuple_ty = MirTupleType::get(&mut ctx, vec![i32_ty.into(), i1_ty.into()]);
-    let block2 = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), i32_ty.into()]);
-    let lhs = block2.deref(&ctx).get_argument(0);
-    let rhs = block2.deref(&ctx).get_argument(1);
-
-    let checked_add = Operation::new(
-        &mut ctx,
-        MirCheckedAddOp::get_concrete_op_info(),
-        vec![tuple_ty.into()],
-        vec![lhs, rhs],
-        vec![],
-        0,
-    );
-    assert!(
-        MirCheckedAddOp::new(checked_add).verify(&ctx).is_ok(),
-        "Valid CheckedAdd"
-    );
-
-    // Invalid result type (not tuple)
-    let checked_add_bad = Operation::new(
-        &mut ctx,
-        MirCheckedAddOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![lhs, rhs],
-        vec![],
-        0,
-    );
-    assert!(
-        MirCheckedAddOp::new(checked_add_bad).verify(&ctx).is_err(),
-        "CheckedAdd bad result"
-    );
-}
-
-#[test]
-fn test_mir_comparison_verify() {
-    let check_cmp = |opid: (
-        fn(pliron::context::Ptr<pliron::operation::Operation>) -> pliron::op::OpObj,
-        std::any::TypeId,
-    ),
-                     name: &str| {
-        let mut context = Context::new();
-        dialect_mir::register(&mut context);
-        let ty = IntegerType::get(&context, 32, Signedness::Signed);
-        let res_ty = IntegerType::get(&context, 1, Signedness::Signless);
-        let blk = BasicBlock::new(&mut context, None, vec![ty.into(), ty.into()]);
-        let l = blk.deref(&context).get_argument(0);
-        let r = blk.deref(&context).get_argument(1);
-
-        let op = Operation::new(
-            &mut context,
-            opid,
-            vec![res_ty.into()],
-            vec![l, r],
-            vec![],
-            0,
-        );
-        assert!(op.verify(&context).is_ok(), "Valid {}", name);
-
-        // Invalid operand types
-        let f32_ty = FP32Type::get(&context);
-        let blk2 = BasicBlock::new(&mut context, None, vec![f32_ty.into()]);
-        let f32_val = blk2.deref(&context).get_argument(0);
-        let op_bad = Operation::new(
-            &mut context,
-            opid,
-            vec![res_ty.into()],
-            vec![l, f32_val],
-            vec![],
-            0,
-        );
-        assert!(op_bad.verify(&context).is_err(), "Type mismatch {}", name);
-
-        // Invalid result type
-        let op_bad_res = Operation::new(
-            &mut context,
-            opid,
-            vec![ty.into()], // i32 result instead of i1
-            vec![l, r],
-            vec![],
-            0,
-        );
-        assert!(
-            op_bad_res.verify(&context).is_err(),
-            "Result type mismatch {}",
-            name
-        );
-    };
-
-    check_cmp(MirEqOp::get_concrete_op_info(), "Eq");
-    check_cmp(MirNeOp::get_concrete_op_info(), "Ne");
-    check_cmp(MirLtOp::get_concrete_op_info(), "Lt");
-    check_cmp(MirLeOp::get_concrete_op_info(), "Le");
-    check_cmp(MirGtOp::get_concrete_op_info(), "Gt");
-    check_cmp(MirGeOp::get_concrete_op_info(), "Ge");
-
-    let mut context = Context::new();
-    dialect_mir::register(&mut context);
-    let i8_ty = IntegerType::get(&context, 8, Signedness::Signed);
-    let i32_ty = IntegerType::get(&context, 32, Signedness::Signed);
-    let unit = |name: &str| EnumVariant::unit(name.to_string());
-    let ordering_ty = MirEnumType::get(
-        &mut context,
-        "Ordering".to_string(),
-        i8_ty.into(),
-        vec![255, 0, 1],
-        vec![unit("Less"), unit("Equal"), unit("Greater")],
-    );
-    let blk = BasicBlock::new(&mut context, None, vec![i32_ty.into(), i32_ty.into()]);
-    let lhs = blk.deref(&context).get_argument(0);
-    let rhs = blk.deref(&context).get_argument(1);
-    let two_variant_ty = MirEnumType::get(
-        &mut context,
-        "Two".to_string(),
-        i8_ty.into(),
-        vec![0, 1],
-        vec![unit("A"), unit("B")],
-    );
-    // Payload variants disqualify the Ordering shape.
-    let payload_ty = MirEnumType::get(
-        &mut context,
-        "ThreeWithPayload".to_string(),
-        i8_ty.into(),
-        vec![0, 1, 2],
-        vec![
-            unit("A"),
-            EnumVariant::new("B".to_string(), vec![i32_ty.into()]),
-            unit("C"),
-        ],
-    );
-    let mut check_cmp_result = |result_ty, valid| {
-        let op = Operation::new(
-            &mut context,
-            MirCmpOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![lhs, rhs],
-            vec![],
-            0,
-        );
-        assert_eq!(op.verify(&context).is_ok(), valid);
-    };
-    check_cmp_result(ordering_ty.into(), true);
-    check_cmp_result(i32_ty.into(), false);
-    check_cmp_result(two_variant_ty.into(), false);
-    check_cmp_result(payload_ty.into(), false);
-
-    // Float operands are rejected: rustc never emits BinOp::Cmp on floats.
-    let f32_ty = FP32Type::get(&context);
-    let fblk = BasicBlock::new(&mut context, None, vec![f32_ty.into(), f32_ty.into()]);
-    let flhs = fblk.deref(&context).get_argument(0);
-    let frhs = fblk.deref(&context).get_argument(1);
-    let float_cmp = Operation::new(
-        &mut context,
-        MirCmpOp::get_concrete_op_info(),
-        vec![ordering_ty.into()],
-        vec![flhs, frhs],
-        vec![],
-        0,
-    );
-    assert!(
-        float_cmp.verify(&context).is_err(),
-        "float mir.cmp must be rejected"
-    );
-}
-
-#[test]
-fn test_mir_func_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let func_ty = FunctionType::get(&ctx, vec![i32_ty.into()], vec![]);
-    let func_ty_attr = TypeAttr::new(func_ty.into());
-
-    // Valid Function
-    let op_ptr = Operation::new(
-        &mut ctx,
-        MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let mir_func = MirFuncOp::new(&mut ctx, op_ptr, func_ty_attr.clone());
-
-    // Add entry block with correct argument
-    let region = mir_func.get_operation().deref(&ctx).get_region(0);
-    let entry_block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    entry_block.insert_at_front(region, &ctx);
-
-    assert!(mir_func.verify(&ctx).is_ok(), "Valid MirFuncOp");
-
-    // Invalid: Argument count mismatch
-    let op_ptr2 = Operation::new(
-        &mut ctx,
-        MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let mir_func2 = MirFuncOp::new(&mut ctx, op_ptr2, func_ty_attr.clone());
-    let region2 = mir_func2.get_operation().deref(&ctx).get_region(0);
-    // Block with 0 args
-    let entry_block2 = BasicBlock::new(&mut ctx, None, vec![]);
-    entry_block2.insert_at_front(region2, &ctx);
-
-    assert!(
-        mir_func2.verify(&ctx).is_err(),
-        "MirFuncOp argument count mismatch"
-    );
-
-    // Invalid: Argument type mismatch
-    let op_ptr3 = Operation::new(
-        &mut ctx,
-        MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let mir_func3 = MirFuncOp::new(&mut ctx, op_ptr3, func_ty_attr);
-    let region3 = mir_func3.get_operation().deref(&ctx).get_region(0);
-    let f32_ty = FP32Type::get(&ctx);
-    let entry_block3 = BasicBlock::new(&mut ctx, None, vec![f32_ty.into()]);
-    entry_block3.insert_at_front(region3, &ctx);
-
-    assert!(
-        mir_func3.verify(&ctx).is_err(),
-        "MirFuncOp argument type mismatch"
-    );
-}
-
-#[test]
-fn test_mir_assign_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let val = block.deref(&ctx).get_argument(0);
-
-    let op = Operation::new(
-        &mut ctx,
-        MirAssignOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirAssignOp::new(op).verify(&ctx).is_ok(),
-        "Valid MirAssignOp"
-    );
-
-    let f32_ty = FP32Type::get(&ctx);
-    let op_bad = Operation::new(
-        &mut ctx,
-        MirAssignOp::get_concrete_op_info(),
-        vec![f32_ty.into()],
-        vec![val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirAssignOp::new(op_bad).verify(&ctx).is_err(),
-        "MirAssignOp type mismatch"
-    );
-}
-
-#[test]
-fn test_mir_call_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let op = Operation::new(
-        &mut ctx,
-        MirCallOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    let call_op = MirCallOp::new(op);
-
-    // Missing attribute
-    assert!(call_op.verify(&ctx).is_err(), "MirCallOp missing attribute");
-
-    // With attribute
-    let name = StringAttr::new("my_func".to_string());
-    call_op.set_attr_callee(&ctx, name);
-    assert!(call_op.verify(&ctx).is_ok(), "Valid MirCallOp");
-}
-
-#[test]
-fn test_mir_store_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let block = BasicBlock::new(&mut ctx, None, vec![ptr_ty.into(), i32_ty.into()]);
-    let ptr_val = block.deref(&ctx).get_argument(0);
-    let val = block.deref(&ctx).get_argument(1);
-
-    let op = Operation::new(
-        &mut ctx,
-        MirStoreOp::get_concrete_op_info(),
-        vec![],
-        vec![ptr_val, val],
-        vec![],
-        0,
-    );
-    assert!(MirStoreOp::new(op).verify(&ctx).is_ok(), "Valid MirStoreOp");
-
-    // Invalid: store to non-ptr
-    let op_bad_ptr = Operation::new(
-        &mut ctx,
-        MirStoreOp::get_concrete_op_info(),
-        vec![],
-        vec![val, val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirStoreOp::new(op_bad_ptr).verify(&ctx).is_err(),
-        "MirStoreOp non-ptr dest"
-    );
-
-    // Invalid: type mismatch
-    let f32_ty = FP32Type::get(&ctx);
-    let block2 = BasicBlock::new(&mut ctx, None, vec![f32_ty.into()]);
-    let f32_val = block2.deref(&ctx).get_argument(0);
-    let op_bad_type = Operation::new(
-        &mut ctx,
-        MirStoreOp::get_concrete_op_info(),
-        vec![],
-        vec![ptr_val, f32_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirStoreOp::new(op_bad_type).verify(&ctx).is_err(),
-        "MirStoreOp type mismatch"
-    );
-}
-
-#[test]
-fn test_mir_store_volatile_is_not_promotable() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let block = BasicBlock::new(&mut ctx, None, vec![ptr_ty.into(), i32_ty.into()]);
-    let ptr_val = block.deref(&ctx).get_argument(0);
-    let val = block.deref(&ctx).get_argument(1);
-
-    let op = Operation::new(
-        &mut ctx,
-        MirStoreOp::get_concrete_op_info(),
-        vec![],
-        vec![ptr_val, val],
-        vec![],
-        0,
-    );
-    let mir_store = MirStoreOp::new(op);
-    let alloc_info = AllocInfo {
-        ptr: ptr_val,
-        ty: i32_ty.into(),
-    };
-
-    assert!(!mir_store.is_volatile(&ctx));
-    match mir_store.promotion_kind(&ctx, &alloc_info) {
-        PromotableOpKind::Store(stored) => assert!(stored == val),
-        _ => panic!("non-volatile store should be promotable"),
-    }
-
-    mir_store.set_volatile(&mut ctx, true);
-
-    assert!(mir_store.is_volatile(&ctx));
-    assert!(matches!(
-        mir_store.promotion_kind(&ctx, &alloc_info),
-        PromotableOpKind::NonPromotableUse
-    ));
-}
-
-#[test]
-fn test_mir_global_alloc_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let f32_ty = FP32Type::get(&ctx);
-
-    // Helper: build a MirGlobalAllocOp whose result pointer is in `ptr_ty`
-    // address space, with valid attributes.
-    let build = |ctx: &mut Context, ptr_ty: pliron::r#type::TypedHandle<MirPtrType>| {
-        let op = Operation::new(
-            ctx,
-            MirGlobalAllocOp::get_concrete_op_info(),
-            vec![ptr_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        let alloc = MirGlobalAllocOp::new(op);
-        alloc.set_attr_global_type(ctx, TypeAttr::new(f32_ty.into()));
-        alloc.set_attr_global_key(ctx, StringAttr::new("k".to_string()));
-        alloc
-    };
-
-    // Global memory (addrspace 1) — the original allowed space.
-    let ptr_global = MirPtrType::get_global(&mut ctx, f32_ty.into(), true);
-    assert!(
-        build(&mut ctx, ptr_global).verify(&ctx).is_ok(),
-        "global addrspace accepted"
-    );
-
-    // Constant memory (addrspace 4) — added for `#[constant]` support.
-    let ptr_const = MirPtrType::get_constant(&mut ctx, f32_ty.into(), true);
-    assert!(
-        build(&mut ctx, ptr_const).verify(&ctx).is_ok(),
-        "constant addrspace accepted"
-    );
-
-    // Shared memory (addrspace 3) — must be rejected.
-    let ptr_shared = MirPtrType::get_shared(&mut ctx, f32_ty.into(), true);
-    assert!(
-        build(&mut ctx, ptr_shared).verify(&ctx).is_err(),
-        "shared addrspace rejected"
-    );
-
-    let ptr_unique_global = MirPtrType::get_with_kind(
-        &mut ctx,
-        f32_ty.into(),
-        true,
-        dialect_mir::types::address_space::GLOBAL,
-        MirPointerKind::UniqueRef,
-    );
-    assert!(
-        build(&mut ctx, ptr_unique_global).verify(&ctx).is_err(),
-        "a storage allocation cannot directly claim UniqueRef"
-    );
-
-    // Missing required attributes.
-    let no_attrs = Operation::new(
-        &mut ctx,
-        MirGlobalAllocOp::get_concrete_op_info(),
-        vec![ptr_global.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(
-        MirGlobalAllocOp::new(no_attrs).verify(&ctx).is_err(),
-        "missing attributes rejected"
-    );
-}
-
-#[test]
-fn test_mir_set_discriminant_verify() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signed);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let unit = |name: &str| EnumVariant::unit(name.to_string());
-
-    let enum_ty = MirEnumType::get(
-        &mut ctx,
-        "DeviceState".to_string(),
-        i8_ty.into(),
-        vec![0, 1],
-        vec![
-            unit("Empty"),
-            EnumVariant::new("Full".to_string(), vec![i32_ty.into()]),
-        ],
-    );
-
-    let enum_ptr_ty = MirPtrType::get_generic(&mut ctx, enum_ty.into(), true);
-    let blk = BasicBlock::new(&mut ctx, None, vec![enum_ptr_ty.into(), i8_ty.into()]);
-    let enum_ptr = blk.deref(&ctx).get_argument(0);
-    let discr_val = blk.deref(&ctx).get_argument(1);
-
-    // Malformed IR must be diagnosed without panicking, regardless of whether
-    // the generated operand-count interface happens to run first.
-    let op_no_operands = Operation::new(
-        &mut ctx,
-        MirSetDiscriminantOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    let no_operands = MirSetDiscriminantOp::new(op_no_operands);
-    no_operands.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(0));
-    assert!(no_operands.verify(&ctx).is_err(), "zero operands rejected");
-
-    let op_extra_operand = Operation::new(
-        &mut ctx,
-        MirSetDiscriminantOp::get_concrete_op_info(),
-        vec![],
-        vec![enum_ptr, discr_val],
-        vec![],
-        0,
-    );
-    let extra_operand = MirSetDiscriminantOp::new(op_extra_operand);
-    extra_operand.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(0));
-    assert!(
-        extra_operand.verify(&ctx).is_err(),
-        "extra operand rejected"
-    );
-
-    // Valid: pointer to enum plus the semantic target variant attribute.
-    let op_valid = Operation::new(
-        &mut ctx,
-        MirSetDiscriminantOp::get_concrete_op_info(),
-        vec![],
-        vec![enum_ptr],
-        vec![],
-        0,
-    );
-    let valid = MirSetDiscriminantOp::new(op_valid);
-    valid.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(1));
-    valid.set_attr_set_discriminant_enum_ty(&ctx, TypeAttr::new(enum_ty.into()));
-    assert!(valid.verify(&ctx).is_ok(), "Valid set_discriminant");
-
-    // Invalid: first operand is not a pointer.
-    let op_bad_ptr = Operation::new(
-        &mut ctx,
-        MirSetDiscriminantOp::get_concrete_op_info(),
-        vec![],
-        vec![discr_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirSetDiscriminantOp::new(op_bad_ptr).verify(&ctx).is_err(),
-        "Non-pointer enum operand rejected"
-    );
-
-    // Invalid: SetDiscriminant writes memory and therefore cannot accept an
-    // immutable pointer even when the pointee is the right enum.
-    let immutable_ptr_ty = MirPtrType::get_generic(&mut ctx, enum_ty.into(), false);
-    let immutable_block = BasicBlock::new(&mut ctx, None, vec![immutable_ptr_ty.into()]);
-    let immutable_ptr = immutable_block.deref(&ctx).get_argument(0);
-    let op_immutable = Operation::new(
-        &mut ctx,
-        MirSetDiscriminantOp::get_concrete_op_info(),
-        vec![],
-        vec![immutable_ptr],
-        vec![],
-        0,
-    );
-    let immutable = MirSetDiscriminantOp::new(op_immutable);
-    immutable.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(0));
-    assert!(
-        immutable.verify(&ctx).is_err(),
-        "immutable pointer rejected"
-    );
-
-    // Invalid: pointer does not point to an enum.
-    let i32_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let blk_i32 = BasicBlock::new(&mut ctx, None, vec![i32_ptr_ty.into(), i8_ty.into()]);
-    let i32_ptr = blk_i32.deref(&ctx).get_argument(0);
-    let op_bad_pointee = Operation::new(
-        &mut ctx,
-        MirSetDiscriminantOp::get_concrete_op_info(),
-        vec![],
-        vec![i32_ptr],
-        vec![],
-        0,
-    );
-    let bad_pointee = MirSetDiscriminantOp::new(op_bad_pointee);
-    bad_pointee.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(0));
-    assert!(
-        bad_pointee.verify(&ctx).is_err(),
-        "Non-enum pointee rejected"
-    );
-
-    // Invalid: target attribute is required.
-    let op_missing_target = Operation::new(
-        &mut ctx,
-        MirSetDiscriminantOp::get_concrete_op_info(),
-        vec![],
-        vec![enum_ptr],
-        vec![],
-        0,
-    );
-    assert!(
-        MirSetDiscriminantOp::new(op_missing_target)
-            .verify(&ctx)
-            .is_err(),
-        "Missing target rejected"
-    );
-
-    // Invalid: target index is out of bounds.
-    let op_oob = Operation::new(
-        &mut ctx,
-        MirSetDiscriminantOp::get_concrete_op_info(),
-        vec![],
-        vec![enum_ptr],
-        vec![],
-        0,
-    );
-    let oob = MirSetDiscriminantOp::new(op_oob);
-    oob.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(2));
-    assert!(oob.verify(&ctx).is_err(), "Out-of-bounds target rejected");
-}
-
-#[test]
-fn test_mir_enum_ops_malformed_arity_is_diagnostic() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let unit_enum = MirEnumType::get(
-        &mut ctx,
-        "Unit".into(),
-        i8_ty.into(),
-        vec![0],
-        vec![EnumVariant::unit("Only".into())],
-    );
-    let payload_enum = MirEnumType::get(
-        &mut ctx,
-        "Payload".into(),
-        i8_ty.into(),
-        vec![0],
-        vec![EnumVariant::new("Only".into(), vec![i32_ty.into()])],
-    );
-    let block = BasicBlock::new(&mut ctx, None, vec![unit_enum.into(), payload_enum.into()]);
-    let unit_value = block.deref(&ctx).get_argument(0);
-    let payload_value = block.deref(&ctx).get_argument(1);
-
-    let construct_no_result = Operation::new(
-        &mut ctx,
-        MirConstructEnumOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    let construct_no_result = MirConstructEnumOp::new(construct_no_result);
-    construct_no_result.set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
-    assert!(construct_no_result.verify(&ctx).is_err());
-
-    let construct_extra_result = Operation::new(
-        &mut ctx,
-        MirConstructEnumOp::get_concrete_op_info(),
-        vec![unit_enum.into(), unit_enum.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let construct_extra_result = MirConstructEnumOp::new(construct_extra_result);
-    construct_extra_result.set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
-    assert!(construct_extra_result.verify(&ctx).is_err());
-
-    let get_empty = Operation::new(
-        &mut ctx,
-        MirGetDiscriminantOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(MirGetDiscriminantOp::new(get_empty).verify(&ctx).is_err());
-    let get_extra = Operation::new(
-        &mut ctx,
-        MirGetDiscriminantOp::get_concrete_op_info(),
-        vec![i8_ty.into(), i8_ty.into()],
-        vec![unit_value, unit_value],
-        vec![],
-        0,
-    );
-    assert!(MirGetDiscriminantOp::new(get_extra).verify(&ctx).is_err());
-
-    let payload_empty = Operation::new(
-        &mut ctx,
-        MirEnumPayloadOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    let payload_empty = MirEnumPayloadOp::new(payload_empty);
-    payload_empty.set_attr_payload_variant_index(&ctx, VariantIndexAttr(0));
-    payload_empty.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
-    assert!(payload_empty.verify(&ctx).is_err());
-
-    let payload_extra = Operation::new(
-        &mut ctx,
-        MirEnumPayloadOp::get_concrete_op_info(),
-        vec![i32_ty.into(), i32_ty.into()],
-        vec![payload_value, payload_value],
-        vec![],
-        0,
-    );
-    let payload_extra = MirEnumPayloadOp::new(payload_extra);
-    payload_extra.set_attr_payload_variant_index(&ctx, VariantIndexAttr(0));
-    payload_extra.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
-    assert!(payload_extra.verify(&ctx).is_err());
-}
-
-#[test]
-fn test_mir_enum_payload_rejects_uninhabited_variant() {
-    use dialect_mir::types::{EnumCarrierKind, EnumEncoding, EnumLayoutKind};
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let enum_ty = MirEnumType::get_with_encoding(
-        &mut ctx,
-        "HasImpossibleField".into(),
-        i8_ty.into(),
-        vec![0, 1],
-        vec![
-            EnumVariant::unit("Live".into()),
-            // An uninhabited variant's unused physical offsets need not fit
-            // the object. The verifier must stop them reaching lowering.
-            EnumVariant::new_with_layout(
-                "Impossible".into(),
-                vec![i32_ty.into()],
-                vec![64],
-                vec![4],
-            ),
-        ],
-        EnumEncoding {
-            tag_offset: 0,
-            total_size: 1,
-            abi_align: 1,
-            layout_kind: EnumLayoutKind::Direct,
-            carrier_kind: EnumCarrierKind::Integer,
-            carrier_width: 8,
-            variant_inhabited: vec![1, 0],
-            ..EnumEncoding::default()
-        },
-    );
-    assert!(enum_ty.verify(&ctx).is_ok());
-
-    let block = BasicBlock::new(&mut ctx, None, vec![enum_ty.into()]);
-    let value = block.deref(&ctx).get_argument(0);
-    let op = Operation::new(
-        &mut ctx,
-        MirEnumPayloadOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![value],
-        vec![],
-        0,
-    );
-    let payload = MirEnumPayloadOp::new(op);
-    payload.set_attr_payload_variant_index(&ctx, VariantIndexAttr(1));
-    payload.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
-    assert!(payload.verify(&ctx).is_err());
-}
-
-/// Reachable-but-dead MIR (e.g. the residual arms of `array::try_from_fn`)
-/// can name uninhabited variants. The importer must lower such reads and
-/// constructions to typed undefs; if it ever emits the real ops again, these
-/// verifiers are the loud stop.
-#[test]
-fn test_uninhabited_enum_construct_and_discriminant_fail_verification() {
-    use dialect_mir::types::{EnumCarrierKind, EnumEncoding, EnumLayoutKind};
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-
-    // Constructing an uninhabited variant must fail verification.
-    let partial = MirEnumType::get_with_encoding(
-        &mut ctx,
-        "HasImpossibleVariant".into(),
-        i8_ty.into(),
-        vec![0, 1],
-        vec![
-            EnumVariant::unit("Live".into()),
-            EnumVariant::new_with_layout(
-                "Impossible".into(),
-                vec![i32_ty.into()],
-                vec![0],
-                vec![4],
-            ),
-        ],
-        EnumEncoding {
-            tag_offset: 0,
-            total_size: 8,
-            abi_align: 4,
-            layout_kind: EnumLayoutKind::Direct,
-            carrier_kind: EnumCarrierKind::Integer,
-            carrier_width: 8,
-            variant_inhabited: vec![1, 0],
-            ..EnumEncoding::default()
-        },
-    );
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let field = block.deref(&ctx).get_argument(0);
-    let construct = Operation::new(
-        &mut ctx,
-        MirConstructEnumOp::get_concrete_op_info(),
-        vec![partial.into()],
-        vec![field],
-        vec![],
-        0,
-    );
-    let construct = MirConstructEnumOp::new(construct);
-    construct.set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
-    assert!(construct.verify(&ctx).is_err());
-
-    // Reading the discriminant of a fully uninhabited enum must fail
-    // verification.
-    let never = MirEnumType::get_with_encoding(
-        &mut ctx,
-        "Never".into(),
-        i8_ty.into(),
-        vec![],
-        vec![],
-        EnumEncoding {
-            tag_offset: 0,
-            total_size: 0,
-            abi_align: 1,
-            layout_kind: EnumLayoutKind::Empty,
-            carrier_kind: EnumCarrierKind::None,
-            carrier_width: 0,
-            variant_inhabited: vec![],
-            ..EnumEncoding::default()
-        },
-    );
-    assert!(never.verify(&ctx).is_ok());
-    let never_block = BasicBlock::new(&mut ctx, None, vec![never.into()]);
-    let never_value = never_block.deref(&ctx).get_argument(0);
-    let get_discriminant = Operation::new(
-        &mut ctx,
-        MirGetDiscriminantOp::get_concrete_op_info(),
-        vec![i8_ty.into()],
-        vec![never_value],
-        vec![],
-        0,
-    );
-    let get_discriminant = MirGetDiscriminantOp::new(get_discriminant);
-    assert!(get_discriminant.verify(&ctx).is_err());
-}
-
-#[test]
-fn test_mir_field_addr_tuple_pointee_verify() {
-    // `(u8, u32)` laid out the way rustc actually places it: the u32 field
-    // first in memory for alignment, so declaration index 0 (`u8`) lands at
-    // byte offset 4 and declaration index 1 (`u32`) lands at byte offset 0.
-    // `field_addr`'s `field_index` attribute is a DECLARATION index (it names
-    // `.0`/`.1` as written), so this test only passes if the op resolves the
-    // field's type through `MirTupleType::get_types()` (declaration order)
-    // rather than assuming identity with memory order.
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-
-    let tuple_ty = MirTupleType::get_with_layout(
-        &mut ctx,
-        vec![u8_ty.into(), u32_ty.into()],
-        vec![1, 0],
-        vec![4, 0],
-        8,
-        4,
-    );
-
-    let tuple_ptr_ty = MirPtrType::get_generic(&mut ctx, tuple_ty.into(), false);
-    let blk = BasicBlock::new(&mut ctx, None, vec![tuple_ptr_ty.into()]);
-    let tuple_ptr = blk.deref(&ctx).get_argument(0);
-
-    let u8_ptr_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
-    let op_field0 = Operation::new(
-        &mut ctx,
-        MirFieldAddrOp::get_concrete_op_info(),
-        vec![u8_ptr_ty.into()],
-        vec![tuple_ptr],
-        vec![],
-        0,
-    );
-    let field0 = MirFieldAddrOp::new(op_field0);
-    field0.set_attr_field_index(&ctx, FieldIndexAttr(0));
-    field0.set_attr_aggregate_ty(&ctx, TypeAttr::new(tuple_ty.into()));
-    assert!(
-        field0.verify(&ctx).is_ok(),
-        "tuple field 0 (u8) address accepted"
-    );
-
-    let u32_ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
-    let op_field1 = Operation::new(
-        &mut ctx,
-        MirFieldAddrOp::get_concrete_op_info(),
-        vec![u32_ptr_ty.into()],
-        vec![tuple_ptr],
-        vec![],
-        0,
-    );
-    let field1 = MirFieldAddrOp::new(op_field1);
-    field1.set_attr_field_index(&ctx, FieldIndexAttr(1));
-    field1.set_attr_aggregate_ty(&ctx, TypeAttr::new(tuple_ty.into()));
-    assert!(
-        field1.verify(&ctx).is_ok(),
-        "tuple field 1 (u32) address accepted"
-    );
-
-    // Result pointee type must match the DECLARED field type, not whatever
-    // sits at that byte offset: pointing field 0's result at u32 (field 1's
-    // type) must be rejected even though both are in-bounds indices.
-    let op_wrong_result_ty = Operation::new(
-        &mut ctx,
-        MirFieldAddrOp::get_concrete_op_info(),
-        vec![u32_ptr_ty.into()],
-        vec![tuple_ptr],
-        vec![],
-        0,
-    );
-    let wrong_result_ty = MirFieldAddrOp::new(op_wrong_result_ty);
-    wrong_result_ty.set_attr_field_index(&ctx, FieldIndexAttr(0));
-    wrong_result_ty.set_attr_aggregate_ty(&ctx, TypeAttr::new(tuple_ty.into()));
-    assert!(
-        wrong_result_ty.verify(&ctx).is_err(),
-        "result pointee type mismatch rejected"
-    );
-
-    let op_out_of_bounds = Operation::new(
-        &mut ctx,
-        MirFieldAddrOp::get_concrete_op_info(),
-        vec![u8_ptr_ty.into()],
-        vec![tuple_ptr],
-        vec![],
-        0,
-    );
-    let out_of_bounds = MirFieldAddrOp::new(op_out_of_bounds);
-    out_of_bounds.set_attr_field_index(&ctx, FieldIndexAttr(2));
-    out_of_bounds.set_attr_aggregate_ty(&ctx, TypeAttr::new(tuple_ty.into()));
-    assert!(
-        out_of_bounds.verify(&ctx).is_err(),
-        "out-of-bounds tuple field index rejected"
-    );
-}
-
-#[test]
-fn test_mir_field_addr_tuple_pointee_store_verify() {
-    // The WRITE side of the tuple-pointee unlock: `t.1 = x` / `arr[i].1 = x`
-    // lower to `mir.field_addr` + `mir.store` through the field's address, so
-    // a tuple-pointee field address used as a store destination must pass
-    // verification too. Same reordered `(u8, u32)` layout as above (the u32
-    // field first in memory), so the store type-checks against the DECLARED
-    // field type, not whatever occupies that memory slot.
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-
-    let tuple_ty = MirTupleType::get_with_layout(
-        &mut ctx,
-        vec![u8_ty.into(), u32_ty.into()],
-        vec![1, 0],
-        vec![4, 0],
-        8,
-        4,
-    );
-
-    let tuple_ptr_ty = MirPtrType::get_generic(&mut ctx, tuple_ty.into(), false);
-    let blk = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![tuple_ptr_ty.into(), u32_ty.into(), u8_ty.into()],
-    );
-    let tuple_ptr = blk.deref(&ctx).get_argument(0);
-    let u32_val = blk.deref(&ctx).get_argument(1);
-    let u8_val = blk.deref(&ctx).get_argument(2);
-
-    // `.1 = x`: address declaration field 1 (u32, memory slot 0) and store a
-    // u32 through it.
-    let u32_ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
-    let op_field1 = Operation::new(
-        &mut ctx,
-        MirFieldAddrOp::get_concrete_op_info(),
-        vec![u32_ptr_ty.into()],
-        vec![tuple_ptr],
-        vec![],
-        0,
-    );
-    let field1 = MirFieldAddrOp::new(op_field1);
-    field1.set_attr_field_index(&ctx, FieldIndexAttr(1));
-    field1.set_attr_aggregate_ty(&ctx, TypeAttr::new(tuple_ty.into()));
-    assert!(
-        field1.verify(&ctx).is_ok(),
-        "tuple field 1 (u32) address accepted as a store destination"
-    );
-    let field1_ptr = op_field1.deref(&ctx).get_result(0);
-
-    let op_store = Operation::new(
-        &mut ctx,
-        MirStoreOp::get_concrete_op_info(),
-        vec![],
-        vec![field1_ptr, u32_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirStoreOp::new(op_store).verify(&ctx).is_ok(),
-        "store through a tuple field address verifies"
-    );
-
-    // The stored value must match the DECLARED field type (`u32` for `.1`),
-    // not the type of the field sharing the tuple: a u8 store through the
-    // `.1` pointer is a type mismatch.
-    let op_store_wrong_ty = Operation::new(
-        &mut ctx,
-        MirStoreOp::get_concrete_op_info(),
-        vec![],
-        vec![field1_ptr, u8_val],
-        vec![],
-        0,
-    );
-    assert!(
-        MirStoreOp::new(op_store_wrong_ty).verify(&ctx).is_err(),
-        "store of a mismatched value type through a tuple field address rejected"
-    );
-}
diff --git a/crates/dialect-mir/tests/ops_test/aggregates.rs b/crates/dialect-mir/tests/ops_test/aggregates.rs
new file mode 100644
index 0000000000..545f81addc
--- /dev/null
+++ b/crates/dialect-mir/tests/ops_test/aggregates.rs
@@ -0,0 +1,687 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::{
+    attributes::{FieldIndexAttr, MirCastKindAttr, MirPointerKindAuthorityAttr},
+    ops::{
+        MirCastOp, MirConstructDisjointSliceOp, MirConstructSliceOp, MirExtractFieldOp,
+        MirFieldAddrOp, MirStoreOp,
+    },
+    types::{
+        MirDisjointSliceType, MirPointerKind, MirPtrType, MirSliceType, MirTupleType, MirUnionType,
+    },
+};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::{
+        attributes::TypeAttr,
+        types::{FP32Type, IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::Context,
+    op::Op,
+    operation::Operation,
+};
+
+#[test]
+fn test_mir_extract_field_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let tuple_ty = MirTupleType::get(&mut ctx, vec![i32_ty.into(), i32_ty.into()]);
+
+    let block = BasicBlock::new(&mut ctx, None, vec![tuple_ty.into()]);
+    let tuple_val = block.deref(&ctx).get_argument(0);
+
+    let op = Operation::new(
+        &mut ctx,
+        MirExtractFieldOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![tuple_val],
+        vec![],
+        0,
+    );
+    let extract_op = MirExtractFieldOp::new(op);
+    extract_op.set_attr_index(&ctx, dialect_mir::attributes::FieldIndexAttr(0));
+    assert!(extract_op.verify(&ctx).is_ok(), "Valid Tuple Extract");
+
+    let op_oob = Operation::new(
+        &mut ctx,
+        MirExtractFieldOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![tuple_val],
+        vec![],
+        0,
+    );
+    let extract_op_oob = MirExtractFieldOp::new(op_oob);
+    extract_op_oob.set_attr_index(&ctx, dialect_mir::attributes::FieldIndexAttr(2));
+    assert!(extract_op_oob.verify(&ctx).is_err(), "OOB Index");
+
+    let union_ty = MirUnionType::get(
+        &mut ctx,
+        "Bits".into(),
+        vec!["word".into(), "alias".into()],
+        vec![i32_ty.into(), i32_ty.into()],
+        4,
+        4,
+    );
+    let union_block = BasicBlock::new(&mut ctx, None, vec![union_ty.into()]);
+    let union_val = union_block.deref(&ctx).get_argument(0);
+    let union_extract = Operation::new(
+        &mut ctx,
+        MirExtractFieldOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![union_val],
+        vec![],
+        0,
+    );
+    let union_extract = MirExtractFieldOp::new(union_extract);
+    union_extract.set_attr_index(&ctx, dialect_mir::attributes::FieldIndexAttr(1));
+    assert!(union_extract.verify(&ctx).is_ok(), "Valid union extract");
+}
+
+#[test]
+fn test_mir_construct_disjoint_slice_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let f32_ty = FP32Type::get(&ctx);
+    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let width_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let f32_ptr_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, f32_ty.into(), true, MirPointerKind::RawMut);
+    let plain_ty = MirDisjointSliceType::get(&mut ctx, f32_ty.into());
+    let width_ty_handle: pliron::r#type::TypeHandle = width_ty.into();
+    let row_width_ty =
+        MirDisjointSliceType::get_with_space(&mut ctx, f32_ty.into(), vec![width_ty_handle]);
+
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![f32_ptr_ty.into(), usize_ty.into(), width_ty.into()],
+    );
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let len_val = block.deref(&ctx).get_argument(1);
+    let width_val = block.deref(&ctx).get_argument(2);
+
+    // Valid: an index space with no runtime layout takes two operands.
+    let op = Operation::new(
+        &mut ctx,
+        MirConstructDisjointSliceOp::get_concrete_op_info(),
+        vec![plain_ty.into()],
+        vec![ptr_val, len_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructDisjointSliceOp::new(op).verify(&ctx).is_ok(),
+        "Valid space-free disjoint slice construction"
+    );
+
+    // Valid: a runtime row width takes a third operand.
+    let op_width = Operation::new(
+        &mut ctx,
+        MirConstructDisjointSliceOp::get_concrete_op_info(),
+        vec![row_width_ty.into()],
+        vec![ptr_val, len_val, width_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructDisjointSliceOp::new(op_width)
+            .verify(&ctx)
+            .is_ok(),
+        "Valid row-width disjoint slice construction"
+    );
+
+    let erased_ptr_ty = MirPtrType::get_generic(&mut ctx, f32_ty.into(), true);
+    let erased_block = BasicBlock::new(&mut ctx, None, vec![erased_ptr_ty.into()]);
+    let erased_ptr = erased_block.deref(&ctx).get_argument(0);
+    let op_erased_data = Operation::new(
+        &mut ctx,
+        MirConstructDisjointSliceOp::get_concrete_op_info(),
+        vec![plain_ty.into()],
+        vec![erased_ptr, len_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructDisjointSliceOp::new(op_erased_data)
+            .verify(&ctx)
+            .is_err(),
+        "DisjointSlice's fixed RawMut field cannot be reconstructed from Erased"
+    );
+
+    // Invalid: the row width is missing, so the slice would carry whatever
+    // slot 2 held.
+    let op_missing_width = Operation::new(
+        &mut ctx,
+        MirConstructDisjointSliceOp::get_concrete_op_info(),
+        vec![row_width_ty.into()],
+        vec![ptr_val, len_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructDisjointSliceOp::new(op_missing_width)
+            .verify(&ctx)
+            .is_err(),
+        "Missing index-space operand"
+    );
+
+    // Invalid: a space-free slice given a third operand.
+    let op_extra = Operation::new(
+        &mut ctx,
+        MirConstructDisjointSliceOp::get_concrete_op_info(),
+        vec![plain_ty.into()],
+        vec![ptr_val, len_val, width_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructDisjointSliceOp::new(op_extra)
+            .verify(&ctx)
+            .is_err(),
+        "Index-space operand for a space-free slice"
+    );
+
+    // Invalid: the row width operand has the wrong width, which would write a
+    // 64-bit value into the 32-bit row width slot.
+    let op_wrong_width_ty = Operation::new(
+        &mut ctx,
+        MirConstructDisjointSliceOp::get_concrete_op_info(),
+        vec![row_width_ty.into()],
+        vec![ptr_val, len_val, len_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructDisjointSliceOp::new(op_wrong_width_ty)
+            .verify(&ctx)
+            .is_err(),
+        "Index-space operand type mismatch"
+    );
+
+    // Invalid: result is a plain slice, which `mir.construct_slice` owns.
+    let plain_slice_ty = MirSliceType::get(&mut ctx, f32_ty.into());
+    let op_bad_res = Operation::new(
+        &mut ctx,
+        MirConstructDisjointSliceOp::get_concrete_op_info(),
+        vec![plain_slice_ty.into()],
+        vec![ptr_val, len_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructDisjointSliceOp::new(op_bad_res)
+            .verify(&ctx)
+            .is_err(),
+        "Result must be a disjoint slice type"
+    );
+}
+
+#[test]
+fn test_mir_construct_slice_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let u8_ptr_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
+    let u8_slice_ty = MirSliceType::get(&mut ctx, u8_ty.into());
+    let i32_slice_ty = MirSliceType::get(&mut ctx, i32_ty.into());
+
+    let block = BasicBlock::new(&mut ctx, None, vec![u8_ptr_ty.into(), usize_ty.into()]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let len_val = block.deref(&ctx).get_argument(1);
+
+    // Valid: (ptr to u8, usize len) -> slice of u8
+    let op = Operation::new(
+        &mut ctx,
+        MirConstructSliceOp::get_concrete_op_info(),
+        vec![u8_slice_ty.into()],
+        vec![ptr_val, len_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructSliceOp::new(op).verify(&ctx).is_ok(),
+        "Valid slice construction"
+    );
+
+    // Invalid: data pointer pointee does not match slice element type
+    let op_bad_elem = Operation::new(
+        &mut ctx,
+        MirConstructSliceOp::get_concrete_op_info(),
+        vec![i32_slice_ty.into()],
+        vec![ptr_val, len_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructSliceOp::new(op_bad_elem).verify(&ctx).is_err(),
+        "Pointee/element mismatch"
+    );
+
+    // Invalid: operands swapped (length where the pointer should be)
+    let op_swapped = Operation::new(
+        &mut ctx,
+        MirConstructSliceOp::get_concrete_op_info(),
+        vec![u8_slice_ty.into()],
+        vec![len_val, ptr_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructSliceOp::new(op_swapped).verify(&ctx).is_err(),
+        "Swapped operands"
+    );
+
+    // Invalid: result is not a slice type
+    let op_bad_res = Operation::new(
+        &mut ctx,
+        MirConstructSliceOp::get_concrete_op_info(),
+        vec![u8_ptr_ty.into()],
+        vec![ptr_val, len_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirConstructSliceOp::new(op_bad_res).verify(&ctx).is_err(),
+        "Non-slice result type"
+    );
+}
+
+#[test]
+fn test_slice_carrier_cannot_launder_pointer_kind() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let raw_mut_ptr =
+        MirPtrType::get_generic_with_kind(&mut ctx, u8_ty.into(), true, MirPointerKind::RawMut);
+    let erased_ptr = MirPtrType::get_generic(&mut ctx, u8_ty.into(), true);
+    let erased_const_ptr = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
+    let global_raw_mut_ptr = MirPtrType::get_with_kind(
+        &mut ctx,
+        u8_ty.into(),
+        true,
+        dialect_mir::types::address_space::GLOBAL,
+        MirPointerKind::RawMut,
+    );
+    let unique_ptr =
+        MirPtrType::get_generic_with_kind(&mut ctx, u8_ty.into(), true, MirPointerKind::UniqueRef);
+    let raw_mut_slice = MirSliceType::get_with_kind(&mut ctx, u8_ty.into(), MirPointerKind::RawMut);
+    let unique_slice =
+        MirSliceType::get_with_kind(&mut ctx, u8_ty.into(), MirPointerKind::UniqueRef);
+    let erased_slice = MirSliceType::get(&mut ctx, u8_ty.into());
+    let erased_mut_slice = MirSliceType::get_with_mutability(&mut ctx, u8_ty.into(), true);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            raw_mut_ptr.into(),
+            erased_ptr.into(),
+            erased_const_ptr.into(),
+            global_raw_mut_ptr.into(),
+            usize_ty.into(),
+            raw_mut_slice.into(),
+            erased_slice.into(),
+            erased_mut_slice.into(),
+        ],
+    );
+    let raw_mut = block.deref(&ctx).get_argument(0);
+    let erased = block.deref(&ctx).get_argument(1);
+    let erased_const = block.deref(&ctx).get_argument(2);
+    let global_raw_mut = block.deref(&ctx).get_argument(3);
+    let len = block.deref(&ctx).get_argument(4);
+    let raw_slice = block.deref(&ctx).get_argument(5);
+    let erased_slice_value = block.deref(&ctx).get_argument(6);
+    let erased_mut_slice_value = block.deref(&ctx).get_argument(7);
+
+    let construct = |ctx: &mut Context, data, result_ty| {
+        Operation::new(
+            ctx,
+            MirConstructSliceOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![data, len],
+            vec![],
+            0,
+        )
+    };
+    assert!(
+        MirConstructSliceOp::new(construct(&mut ctx, raw_mut, raw_mut_slice.into()))
+            .verify(&ctx)
+            .is_ok()
+    );
+    assert!(
+        MirConstructSliceOp::new(construct(&mut ctx, raw_mut, unique_slice.into()))
+            .verify(&ctx)
+            .is_err(),
+        "construct_slice must not turn RawMut into UniqueRef"
+    );
+    assert!(
+        MirConstructSliceOp::new(construct(&mut ctx, erased, raw_mut_slice.into()))
+            .verify(&ctx)
+            .is_err(),
+        "construct_slice must not recover RawMut from Erased"
+    );
+    assert!(
+        MirConstructSliceOp::new(construct(&mut ctx, global_raw_mut, raw_mut_slice.into()))
+            .verify(&ctx)
+            .is_err(),
+        "ordinary slice carriers always use generic address space"
+    );
+    assert!(
+        MirConstructSliceOp::new(construct(&mut ctx, erased_const, erased_slice.into()))
+            .verify(&ctx)
+            .is_ok(),
+        "an immutable Erased data pointer constructs an immutable Erased slice"
+    );
+
+    let extract = |ctx: &mut Context, result_ty| {
+        let op = Operation::new(
+            ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![raw_slice],
+            vec![],
+            0,
+        );
+        MirExtractFieldOp::new(op).set_attr_index(ctx, FieldIndexAttr(0));
+        op
+    };
+    assert!(
+        MirExtractFieldOp::new(extract(&mut ctx, raw_mut_ptr.into()))
+            .verify(&ctx)
+            .is_ok()
+    );
+    assert!(
+        MirExtractFieldOp::new(extract(&mut ctx, erased_ptr.into()))
+            .verify(&ctx)
+            .is_ok(),
+        "slice extraction may deliberately erase a concrete kind"
+    );
+    assert!(
+        MirExtractFieldOp::new(extract(&mut ctx, unique_ptr.into()))
+            .verify(&ctx)
+            .is_err(),
+        "slice extraction must not change RawMut into UniqueRef"
+    );
+    assert!(
+        MirExtractFieldOp::new(extract(&mut ctx, global_raw_mut_ptr.into()))
+            .verify(&ctx)
+            .is_err(),
+        "ordinary slice extraction cannot invent a non-generic address space"
+    );
+    assert!(
+        MirExtractFieldOp::new(extract(&mut ctx, erased_const_ptr.into()))
+            .verify(&ctx)
+            .is_err(),
+        "erasing a concrete slice kind must preserve machine mutability"
+    );
+
+    let extract_erased = |ctx: &mut Context, result_ty| {
+        let op = Operation::new(
+            ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![erased_slice_value],
+            vec![],
+            0,
+        );
+        MirExtractFieldOp::new(op).set_attr_index(ctx, FieldIndexAttr(0));
+        op
+    };
+    assert!(
+        MirExtractFieldOp::new(extract_erased(&mut ctx, erased_const_ptr.into()))
+            .verify(&ctx)
+            .is_ok(),
+        "an immutable Erased slice extracts an immutable Erased data pointer"
+    );
+    assert!(
+        MirExtractFieldOp::new(extract_erased(&mut ctx, erased_ptr.into()))
+            .verify(&ctx)
+            .is_err(),
+        "an immutable Erased slice cannot manufacture writable data-pointer evidence"
+    );
+
+    let extract_erased_mut = |ctx: &mut Context, result_ty| {
+        let op = Operation::new(
+            ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![erased_mut_slice_value],
+            vec![],
+            0,
+        );
+        MirExtractFieldOp::new(op).set_attr_index(ctx, FieldIndexAttr(0));
+        op
+    };
+    assert!(
+        MirExtractFieldOp::new(extract_erased_mut(&mut ctx, erased_ptr.into()))
+            .verify(&ctx)
+            .is_ok(),
+        "a mutable Erased slice retains writable data-pointer evidence"
+    );
+
+    let immutable_slice_reborrow = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_slice.into()],
+        vec![erased_slice_value],
+        vec![],
+        0,
+    );
+    let immutable_slice_reborrow = MirCastOp::new(immutable_slice_reborrow);
+    immutable_slice_reborrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    immutable_slice_reborrow
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    assert!(
+        immutable_slice_reborrow.verify(&ctx).is_err(),
+        "an immutable Erased slice cannot be reborrowed as UniqueRef"
+    );
+
+    let mutable_slice_reborrow = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_slice.into()],
+        vec![erased_mut_slice_value],
+        vec![],
+        0,
+    );
+    let mutable_slice_reborrow = MirCastOp::new(mutable_slice_reborrow);
+    mutable_slice_reborrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    mutable_slice_reborrow
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    assert!(
+        mutable_slice_reborrow.verify(&ctx).is_ok(),
+        "a mutable Erased slice may establish UniqueRef at a real reborrow boundary"
+    );
+}
+
+#[test]
+fn test_mir_field_addr_tuple_pointee_verify() {
+    // `(u8, u32)` laid out the way rustc actually places it: the u32 field
+    // first in memory for alignment, so declaration index 0 (`u8`) lands at
+    // byte offset 4 and declaration index 1 (`u32`) lands at byte offset 0.
+    // `field_addr`'s `field_index` attribute is a DECLARATION index (it names
+    // `.0`/`.1` as written), so this test only passes if the op resolves the
+    // field's type through `MirTupleType::get_types()` (declaration order)
+    // rather than assuming identity with memory order.
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+
+    let tuple_ty = MirTupleType::get_with_layout(
+        &mut ctx,
+        vec![u8_ty.into(), u32_ty.into()],
+        vec![1, 0],
+        vec![4, 0],
+        8,
+        4,
+    );
+
+    let tuple_ptr_ty = MirPtrType::get_generic(&mut ctx, tuple_ty.into(), false);
+    let blk = BasicBlock::new(&mut ctx, None, vec![tuple_ptr_ty.into()]);
+    let tuple_ptr = blk.deref(&ctx).get_argument(0);
+
+    let u8_ptr_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
+    let op_field0 = Operation::new(
+        &mut ctx,
+        MirFieldAddrOp::get_concrete_op_info(),
+        vec![u8_ptr_ty.into()],
+        vec![tuple_ptr],
+        vec![],
+        0,
+    );
+    let field0 = MirFieldAddrOp::new(op_field0);
+    field0.set_attr_field_index(&ctx, FieldIndexAttr(0));
+    field0.set_attr_aggregate_ty(&ctx, TypeAttr::new(tuple_ty.into()));
+    assert!(
+        field0.verify(&ctx).is_ok(),
+        "tuple field 0 (u8) address accepted"
+    );
+
+    let u32_ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
+    let op_field1 = Operation::new(
+        &mut ctx,
+        MirFieldAddrOp::get_concrete_op_info(),
+        vec![u32_ptr_ty.into()],
+        vec![tuple_ptr],
+        vec![],
+        0,
+    );
+    let field1 = MirFieldAddrOp::new(op_field1);
+    field1.set_attr_field_index(&ctx, FieldIndexAttr(1));
+    field1.set_attr_aggregate_ty(&ctx, TypeAttr::new(tuple_ty.into()));
+    assert!(
+        field1.verify(&ctx).is_ok(),
+        "tuple field 1 (u32) address accepted"
+    );
+
+    // Result pointee type must match the DECLARED field type, not whatever
+    // sits at that byte offset: pointing field 0's result at u32 (field 1's
+    // type) must be rejected even though both are in-bounds indices.
+    let op_wrong_result_ty = Operation::new(
+        &mut ctx,
+        MirFieldAddrOp::get_concrete_op_info(),
+        vec![u32_ptr_ty.into()],
+        vec![tuple_ptr],
+        vec![],
+        0,
+    );
+    let wrong_result_ty = MirFieldAddrOp::new(op_wrong_result_ty);
+    wrong_result_ty.set_attr_field_index(&ctx, FieldIndexAttr(0));
+    wrong_result_ty.set_attr_aggregate_ty(&ctx, TypeAttr::new(tuple_ty.into()));
+    assert!(
+        wrong_result_ty.verify(&ctx).is_err(),
+        "result pointee type mismatch rejected"
+    );
+
+    let op_out_of_bounds = Operation::new(
+        &mut ctx,
+        MirFieldAddrOp::get_concrete_op_info(),
+        vec![u8_ptr_ty.into()],
+        vec![tuple_ptr],
+        vec![],
+        0,
+    );
+    let out_of_bounds = MirFieldAddrOp::new(op_out_of_bounds);
+    out_of_bounds.set_attr_field_index(&ctx, FieldIndexAttr(2));
+    out_of_bounds.set_attr_aggregate_ty(&ctx, TypeAttr::new(tuple_ty.into()));
+    assert!(
+        out_of_bounds.verify(&ctx).is_err(),
+        "out-of-bounds tuple field index rejected"
+    );
+}
+
+#[test]
+fn test_mir_field_addr_tuple_pointee_store_verify() {
+    // The WRITE side of the tuple-pointee unlock: `t.1 = x` / `arr[i].1 = x`
+    // lower to `mir.field_addr` + `mir.store` through the field's address, so
+    // a tuple-pointee field address used as a store destination must pass
+    // verification too. Same reordered `(u8, u32)` layout as above (the u32
+    // field first in memory), so the store type-checks against the DECLARED
+    // field type, not whatever occupies that memory slot.
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+
+    let tuple_ty = MirTupleType::get_with_layout(
+        &mut ctx,
+        vec![u8_ty.into(), u32_ty.into()],
+        vec![1, 0],
+        vec![4, 0],
+        8,
+        4,
+    );
+
+    let tuple_ptr_ty = MirPtrType::get_generic(&mut ctx, tuple_ty.into(), false);
+    let blk = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![tuple_ptr_ty.into(), u32_ty.into(), u8_ty.into()],
+    );
+    let tuple_ptr = blk.deref(&ctx).get_argument(0);
+    let u32_val = blk.deref(&ctx).get_argument(1);
+    let u8_val = blk.deref(&ctx).get_argument(2);
+
+    // `.1 = x`: address declaration field 1 (u32, memory slot 0) and store a
+    // u32 through it.
+    let u32_ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
+    let op_field1 = Operation::new(
+        &mut ctx,
+        MirFieldAddrOp::get_concrete_op_info(),
+        vec![u32_ptr_ty.into()],
+        vec![tuple_ptr],
+        vec![],
+        0,
+    );
+    let field1 = MirFieldAddrOp::new(op_field1);
+    field1.set_attr_field_index(&ctx, FieldIndexAttr(1));
+    field1.set_attr_aggregate_ty(&ctx, TypeAttr::new(tuple_ty.into()));
+    assert!(
+        field1.verify(&ctx).is_ok(),
+        "tuple field 1 (u32) address accepted as a store destination"
+    );
+    let field1_ptr = op_field1.deref(&ctx).get_result(0);
+
+    let op_store = Operation::new(
+        &mut ctx,
+        MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![field1_ptr, u32_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirStoreOp::new(op_store).verify(&ctx).is_ok(),
+        "store through a tuple field address verifies"
+    );
+
+    // The stored value must match the DECLARED field type (`u32` for `.1`),
+    // not the type of the field sharing the tuple: a u8 store through the
+    // `.1` pointer is a type mismatch.
+    let op_store_wrong_ty = Operation::new(
+        &mut ctx,
+        MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![field1_ptr, u8_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirStoreOp::new(op_store_wrong_ty).verify(&ctx).is_err(),
+        "store of a mismatched value type through a tuple field address rejected"
+    );
+}
diff --git a/crates/dialect-mir/tests/ops_test/cast_authority.rs b/crates/dialect-mir/tests/ops_test/cast_authority.rs
new file mode 100644
index 0000000000..b3dc7a8b47
--- /dev/null
+++ b/crates/dialect-mir/tests/ops_test/cast_authority.rs
@@ -0,0 +1,1060 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::{
+    attributes::{FieldIndexAttr, MirCastKindAttr, MirPointerKindAuthorityAttr},
+    ops::{MirArrayElementAddrOp, MirCastOp, MirExtractFieldOp, MirFieldAddrOp, MirPtrOffsetOp},
+    types::{MirArrayType, MirPointerKind, MirPtrType, MirSliceType, MirStructType, MirTupleType},
+};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::{
+        attributes::TypeAttr,
+        types::{IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::Context,
+    op::Op,
+    operation::Operation,
+};
+
+#[test]
+fn test_aggregate_cast_cannot_hide_pointer_kind_laundering() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let raw_mut_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
+    let unique_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
+    let raw_tuple_ty = MirTupleType::get(&mut ctx, vec![raw_mut_ty.into()]);
+    let unique_tuple_ty = MirTupleType::get(&mut ctx, vec![unique_ty.into()]);
+    let block = BasicBlock::new(&mut ctx, None, vec![raw_tuple_ty.into()]);
+    let raw_tuple = block.deref(&ctx).get_argument(0);
+
+    let build = |ctx: &mut Context, authority: Option<MirPointerKindAuthorityAttr>| {
+        let op = Operation::new(
+            ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![unique_tuple_ty.into()],
+            vec![raw_tuple],
+            vec![],
+            0,
+        );
+        let cast = MirCastOp::new(op);
+        cast.set_attr_cast_kind(ctx, MirCastKindAttr::Transmute);
+        if let Some(authority) = authority {
+            cast.set_pointer_kind_authority(ctx, authority);
+        }
+        op
+    };
+
+    assert!(
+        MirCastOp::new(build(&mut ctx, None)).verify(&ctx).is_err(),
+        "nested RawMut -> UniqueRef laundering must be rejected"
+    );
+    assert!(
+        MirCastOp::new(build(&mut ctx, Some(MirPointerKindAuthorityAttr::Reborrow),))
+            .verify(&ctx)
+            .is_err(),
+        "Rvalue::Ref cannot authorize a nested aggregate transition"
+    );
+    assert!(
+        MirCastOp::new(build(&mut ctx, Some(MirPointerKindAuthorityAttr::RustCast),))
+            .verify(&ctx)
+            .is_ok(),
+        "an explicit rustc aggregate transmute is visible and authorized"
+    );
+}
+
+#[test]
+fn test_aggregate_reinterpretation_requires_rust_cast_authority() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let shared_ty = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        i64_ty.into(),
+        false,
+        MirPointerKind::SharedRef,
+    );
+    // Both tuple declarations list the same pointer at field 0, but its byte
+    // offset changes from 0 to 8. Pairing by declaration index alone would
+    // therefore mistake an integer's old bytes for a preserved reference.
+    let source_ty = MirTupleType::get_with_layout(
+        &mut ctx,
+        vec![shared_ty.into(), i64_ty.into()],
+        vec![0, 1],
+        vec![0, 8],
+        16,
+        8,
+    );
+    let target_ty = MirTupleType::get_with_layout(
+        &mut ctx,
+        vec![shared_ty.into(), i64_ty.into()],
+        vec![1, 0],
+        vec![8, 0],
+        16,
+        8,
+    );
+    let block = BasicBlock::new(&mut ctx, None, vec![source_ty.into()]);
+    let source = block.deref(&ctx).get_argument(0);
+
+    let build = |ctx: &mut Context, authority: Option<MirPointerKindAuthorityAttr>| {
+        let op = Operation::new(
+            ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![target_ty.into()],
+            vec![source],
+            vec![],
+            0,
+        );
+        let cast = MirCastOp::new(op);
+        cast.set_attr_cast_kind(ctx, MirCastKindAttr::Transmute);
+        if let Some(authority) = authority {
+            cast.set_pointer_kind_authority(ctx, authority);
+        }
+        op
+    };
+
+    assert!(
+        MirCastOp::new(build(&mut ctx, None)).verify(&ctx).is_err(),
+        "layout-changing aggregate casts must not infer pointer preservation by field index"
+    );
+    assert!(
+        MirCastOp::new(build(&mut ctx, Some(MirPointerKindAuthorityAttr::RustCast),))
+            .verify(&ctx)
+            .is_ok(),
+        "an explicit rustc transmute makes the representation reinterpretation auditable"
+    );
+}
+
+#[test]
+fn test_generic_aggregate_cast_cannot_invent_erased_pointer_carriers() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let word_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let erased_mut = MirPtrType::get_generic(&mut ctx, word_ty.into(), true);
+    let source_ty = MirTupleType::get_with_layout(
+        &mut ctx,
+        vec![erased_mut.into(), word_ty.into()],
+        vec![0, 1],
+        vec![0, 8],
+        16,
+        8,
+    );
+    let extra_pointer_ty = MirTupleType::get_with_layout(
+        &mut ctx,
+        vec![erased_mut.into(), erased_mut.into()],
+        vec![0, 1],
+        vec![0, 8],
+        16,
+        8,
+    );
+    let moved_pointer_ty = MirTupleType::get_with_layout(
+        &mut ctx,
+        vec![erased_mut.into(), word_ty.into()],
+        vec![1, 0],
+        vec![8, 0],
+        16,
+        8,
+    );
+    let one_pointer = MirArrayType::get(&mut ctx, erased_mut.into(), 1);
+    let two_pointers = MirArrayType::get(&mut ctx, erased_mut.into(), 2);
+
+    let source_block = BasicBlock::new(&mut ctx, None, vec![source_ty.into()]);
+    let source = source_block.deref(&ctx).get_argument(0);
+    let array_block = BasicBlock::new(&mut ctx, None, vec![one_pointer.into()]);
+    let array_source = array_block.deref(&ctx).get_argument(0);
+    let build = |ctx: &mut Context, source, target| {
+        let op = Operation::new(
+            ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![target],
+            vec![source],
+            vec![],
+            0,
+        );
+        MirCastOp::new(op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+        op
+    };
+
+    assert!(
+        MirCastOp::new(build(&mut ctx, source, extra_pointer_ty.into()))
+            .verify(&ctx)
+            .is_err(),
+        "PtrToPtr cannot reinterpret an integer field as writable Erased pointer evidence"
+    );
+    assert!(
+        MirCastOp::new(build(&mut ctx, source, moved_pointer_ty.into()))
+            .verify(&ctx)
+            .is_err(),
+        "field-index equality cannot hide an Erased pointer moving onto integer bytes"
+    );
+    assert!(
+        MirCastOp::new(build(&mut ctx, array_source, two_pointers.into()))
+            .verify(&ctx)
+            .is_err(),
+        "homogeneous array traversal must retain pointer-carrier cardinality"
+    );
+}
+
+#[test]
+fn test_rust_cast_authority_obeys_cast_kind_semantics() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let array_ty = MirArrayType::get(&mut ctx, u8_ty.into(), 4);
+    let raw_mut =
+        MirPtrType::get_generic_with_kind(&mut ctx, u8_ty.into(), true, MirPointerKind::RawMut);
+    let raw_const =
+        MirPtrType::get_generic_with_kind(&mut ctx, u8_ty.into(), false, MirPointerKind::RawConst);
+    let unique =
+        MirPtrType::get_generic_with_kind(&mut ctx, u8_ty.into(), true, MirPointerKind::UniqueRef);
+    let fn_target = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "FnPtrTarget".into(),
+        vec![],
+        vec![],
+        vec![],
+        vec![],
+        0,
+        0,
+    );
+    let fn_target_ty: pliron::r#type::TypeHandle = fn_target.into();
+    let fn_carrier = MirPtrType::get_generic(&mut ctx, fn_target_ty, false);
+    let raw_mut_array =
+        MirPtrType::get_generic_with_kind(&mut ctx, array_ty.into(), true, MirPointerKind::RawMut);
+    let raw_const_array = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        array_ty.into(),
+        false,
+        MirPointerKind::RawConst,
+    );
+    let erased_array = MirPtrType::get_generic(&mut ctx, array_ty.into(), false);
+    let erased_slice = MirSliceType::get(&mut ctx, u8_ty.into());
+    let erased_mut_slice = MirSliceType::get_with_mutability(&mut ctx, u8_ty.into(), true);
+    let raw_const_slice =
+        MirSliceType::get_with_kind(&mut ctx, u8_ty.into(), MirPointerKind::RawConst);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            raw_mut.into(),
+            raw_const.into(),
+            fn_carrier.into(),
+            raw_mut_array.into(),
+            raw_const_array.into(),
+            erased_array.into(),
+            usize_ty.into(),
+        ],
+    );
+    let raw_mut_value = block.deref(&ctx).get_argument(0);
+    let raw_const_value = block.deref(&ctx).get_argument(1);
+    let fn_value = block.deref(&ctx).get_argument(2);
+    let raw_mut_array_value = block.deref(&ctx).get_argument(3);
+    let raw_const_array_value = block.deref(&ctx).get_argument(4);
+    let erased_array_value = block.deref(&ctx).get_argument(5);
+    let integer_value = block.deref(&ctx).get_argument(6);
+
+    let build = |ctx: &mut Context,
+                 source,
+                 target,
+                 kind,
+                 authority: Option<MirPointerKindAuthorityAttr>| {
+        let op = Operation::new(
+            ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![target],
+            vec![source],
+            vec![],
+            0,
+        );
+        let cast = MirCastOp::new(op);
+        cast.set_attr_cast_kind(ctx, kind);
+        if let Some(authority) = authority {
+            cast.set_pointer_kind_authority(ctx, authority);
+        }
+        op
+    };
+    let rust_cast = Some(MirPointerKindAuthorityAttr::RustCast);
+
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            raw_mut_value,
+            unique.into(),
+            MirCastKindAttr::PtrToPtr,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "PtrToPtr cannot use RustCast to invent a reference"
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            raw_mut_value,
+            raw_const.into(),
+            MirCastKindAttr::PtrToPtr,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_ok(),
+        "PtrToPtr may perform an explicit raw-to-raw cast"
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            fn_value,
+            raw_const.into(),
+            MirCastKindAttr::FnPtrToPtr,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_ok(),
+        "FnPtrToPtr may expose an opaque function pointer as a raw pointer"
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            erased_array_value,
+            raw_const.into(),
+            MirCastKindAttr::FnPtrToPtr,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "FnPtrToPtr cannot relabel arbitrary Erased storage as a function pointer"
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            fn_value,
+            unique.into(),
+            MirCastKindAttr::FnPtrToPtr,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_err()
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            raw_mut_value,
+            raw_const.into(),
+            MirCastKindAttr::PointerCoercionMutToConst,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_ok()
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            raw_const_value,
+            raw_mut.into(),
+            MirCastKindAttr::PointerCoercionMutToConst,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_err()
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            raw_mut_value,
+            raw_mut.into(),
+            MirCastKindAttr::PointerCoercionMutToConst,
+            None,
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "MutToConst cannot masquerade as a same-category pointer cast"
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            raw_const_array_value,
+            raw_const_slice.into(),
+            MirCastKindAttr::PointerCoercionUnsize,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_ok(),
+        "Unsize may change thin/fat shape while preserving its carrier"
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            erased_array_value,
+            erased_slice.into(),
+            MirCastKindAttr::PointerCoercionUnsize,
+            None,
+        ))
+        .verify(&ctx)
+        .is_ok(),
+        "an all-Erased unsize still preserves read-only carrier state"
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            erased_array_value,
+            erased_mut_slice.into(),
+            MirCastKindAttr::PointerCoercionUnsize,
+            None,
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "Unsize cannot turn an immutable Erased thin pointer into writable fat evidence"
+    );
+
+    let prefix_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let sized_tail = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "TailCarrier".into(),
+        vec!["prefix".into(), "tail".into()],
+        vec![prefix_ty.into(), array_ty.into()],
+        vec![0, 1],
+        vec![0, 8],
+        16,
+        8,
+    );
+    let shifted_unsized_tail = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "TailCarrier".into(),
+        vec!["prefix".into(), "tail".into()],
+        vec![prefix_ty.into(), u8_ty.into()],
+        vec![0, 1],
+        vec![0, 16],
+        24,
+        8,
+    );
+    let sized_tail_ptr = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        sized_tail.into(),
+        false,
+        MirPointerKind::RawConst,
+    );
+    let shifted_tail_slice = MirSliceType::get_with_kind(
+        &mut ctx,
+        shifted_unsized_tail.into(),
+        MirPointerKind::RawConst,
+    );
+    let tail_block = BasicBlock::new(&mut ctx, None, vec![sized_tail_ptr.into()]);
+    let tail_value = tail_block.deref(&ctx).get_argument(0);
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            tail_value,
+            shifted_tail_slice.into(),
+            MirCastKindAttr::PointerCoercionUnsize,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "Unsize cannot move the trailing data behind a changed struct-field offset"
+    );
+
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            raw_const_array_value,
+            raw_mut.into(),
+            MirCastKindAttr::PointerCoercionArrayToPointer,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "ArrayToPointer cannot strengthen const raw storage to mutable"
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            raw_mut_value,
+            raw_const.into(),
+            MirCastKindAttr::PointerCoercionArrayToPointer,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "ArrayToPointer requires a raw pointer to an array, not an arbitrary pointer"
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            raw_mut_value,
+            raw_mut.into(),
+            MirCastKindAttr::PointerCoercionArrayToPointer,
+            None,
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "an unmarked same-kind ArrayToPointer still requires an array source"
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            raw_mut_array_value,
+            raw_const.into(),
+            MirCastKindAttr::PointerCoercionArrayToPointer,
+            rust_cast.clone(),
+        ))
+        .verify(&ctx)
+        .is_ok()
+    );
+    assert!(
+        MirCastOp::new(build(
+            &mut ctx,
+            integer_value,
+            unique.into(),
+            MirCastKindAttr::Transmute,
+            rust_cast,
+        ))
+        .verify(&ctx)
+        .is_ok(),
+        "only an explicit Transmute may establish an arbitrary pointer category"
+    );
+
+    let word_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let source_wrapper = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "CarrierWrapper".into(),
+        vec!["pointer".into(), "word".into()],
+        vec![unique.into(), word_ty.into()],
+        vec![0, 1],
+        vec![0, 8],
+        16,
+        8,
+    );
+    let moved_wrapper = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "CarrierWrapper".into(),
+        vec!["word".into(), "pointer".into()],
+        vec![word_ty.into(), unique.into()],
+        vec![0, 1],
+        vec![0, 8],
+        16,
+        8,
+    );
+    let wrapper_block = BasicBlock::new(&mut ctx, None, vec![source_wrapper.into()]);
+    let wrapper_value = wrapper_block.deref(&ctx).get_argument(0);
+    for kind in [
+        MirCastKindAttr::PointerCoercionUnsize,
+        MirCastKindAttr::Subtype,
+    ] {
+        assert!(
+            MirCastOp::new(build(
+                &mut ctx,
+                wrapper_value,
+                moved_wrapper.into(),
+                kind,
+                Some(MirPointerKindAuthorityAttr::RustCast),
+            ))
+            .verify(&ctx)
+            .is_err(),
+            "Unsize/Subtype cannot bless a pointer carrier moved onto integer bytes"
+        );
+    }
+}
+
+#[test]
+fn test_pointer_projections_preserve_or_erase_kind_only() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let tuple_ty = MirTupleType::get(&mut ctx, vec![i32_ty.into()]);
+    let array_ty = MirArrayType::get(&mut ctx, i32_ty.into(), 4);
+    let raw_tuple_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, tuple_ty.into(), true, MirPointerKind::RawMut);
+    let raw_array_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, array_ty.into(), true, MirPointerKind::RawMut);
+    let raw_field_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
+    let erased_field_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let erased_read_field_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let unique_field_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![raw_tuple_ty.into(), raw_array_ty.into(), usize_ty.into()],
+    );
+    let tuple = block.deref(&ctx).get_argument(0);
+    let array = block.deref(&ctx).get_argument(1);
+    let index = block.deref(&ctx).get_argument(2);
+
+    let field = |ctx: &mut Context, result_ty| {
+        let op = Operation::new(
+            ctx,
+            MirFieldAddrOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![tuple],
+            vec![],
+            0,
+        );
+        MirFieldAddrOp::new(op).set_attr_field_index(ctx, FieldIndexAttr(0));
+        MirFieldAddrOp::new(op).set_attr_aggregate_ty(ctx, TypeAttr::new(tuple_ty.into()));
+        op
+    };
+    assert!(
+        MirFieldAddrOp::new(field(&mut ctx, raw_field_ty.into()))
+            .verify(&ctx)
+            .is_ok()
+    );
+    assert!(
+        MirFieldAddrOp::new(field(&mut ctx, erased_field_ty.into()))
+            .verify(&ctx)
+            .is_ok()
+    );
+    assert!(
+        MirFieldAddrOp::new(field(&mut ctx, unique_field_ty.into()))
+            .verify(&ctx)
+            .is_err()
+    );
+    assert!(
+        MirFieldAddrOp::new(field(&mut ctx, erased_read_field_ty.into()))
+            .verify(&ctx)
+            .is_err(),
+        "field projection cannot flip an Erased address from writable to read-only"
+    );
+
+    let array_launder = Operation::new(
+        &mut ctx,
+        MirArrayElementAddrOp::get_concrete_op_info(),
+        vec![unique_field_ty.into()],
+        vec![array, index],
+        vec![],
+        0,
+    );
+    assert!(
+        MirArrayElementAddrOp::new(array_launder)
+            .verify(&ctx)
+            .is_err()
+    );
+    let array_erase = Operation::new(
+        &mut ctx,
+        MirArrayElementAddrOp::get_concrete_op_info(),
+        vec![erased_field_ty.into()],
+        vec![array, index],
+        vec![],
+        0,
+    );
+    assert!(
+        MirArrayElementAddrOp::new(array_erase).verify(&ctx).is_ok(),
+        "projection may erase kind while preserving machine mutability"
+    );
+    let array_mutability_flip = Operation::new(
+        &mut ctx,
+        MirArrayElementAddrOp::get_concrete_op_info(),
+        vec![erased_read_field_ty.into()],
+        vec![array, index],
+        vec![],
+        0,
+    );
+    assert!(
+        MirArrayElementAddrOp::new(array_mutability_flip)
+            .verify(&ctx)
+            .is_err(),
+        "array projection cannot change machine mutability"
+    );
+}
+
+#[test]
+fn test_pointer_with_exposed_provenance_only_creates_raw_or_erased_pointer() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let fn_target = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "FnPtrTarget".into(),
+        vec![],
+        vec![],
+        vec![],
+        vec![],
+        0,
+        0,
+    );
+    let fn_target_ty: pliron::r#type::TypeHandle = fn_target.into();
+    let raw_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
+    let opaque_fn_ty = MirPtrType::get_generic(&mut ctx, fn_target_ty, false);
+    let arbitrary_erased_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let writable_erased_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let unique_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
+    let block = BasicBlock::new(&mut ctx, None, vec![usize_ty.into()]);
+    let address = block.deref(&ctx).get_argument(0);
+
+    let build = |ctx: &mut Context, result_ty| {
+        let op = Operation::new(
+            ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![address],
+            vec![],
+            0,
+        );
+        let cast = MirCastOp::new(op);
+        cast.set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
+        cast.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::RustCast);
+        op
+    };
+
+    assert!(
+        MirCastOp::new(build(&mut ctx, raw_ty.into()))
+            .verify(&ctx)
+            .is_ok()
+    );
+    assert!(
+        MirCastOp::new(build(&mut ctx, unique_ty.into()))
+            .verify(&ctx)
+            .is_err(),
+        "integer provenance cannot directly materialize a Rust reference"
+    );
+
+    let build_unmarked = |ctx: &mut Context, result_ty| {
+        let op = Operation::new(
+            ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![address],
+            vec![],
+            0,
+        );
+        MirCastOp::new(op).set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
+        op
+    };
+    assert!(
+        MirCastOp::new(build_unmarked(&mut ctx, opaque_fn_ty.into()))
+            .verify(&ctx)
+            .is_ok(),
+        "function-pointer tokens may materialize only the canonical immutable Erased carrier"
+    );
+    assert!(
+        MirCastOp::new(build_unmarked(&mut ctx, arbitrary_erased_ty.into()))
+            .verify(&ctx)
+            .is_err(),
+        "an integer cannot manufacture arbitrary Erased pointer evidence"
+    );
+    assert!(
+        MirCastOp::new(build_unmarked(&mut ctx, writable_erased_ty.into()))
+            .verify(&ctx)
+            .is_err(),
+        "an integer cannot manufacture writable Erased evidence and then reborrow it as UniqueRef"
+    );
+
+    let fn_block = BasicBlock::new(&mut ctx, None, vec![opaque_fn_ty.into()]);
+    let opaque_fn = fn_block.deref(&ctx).get_argument(0);
+    let disguised_data_pointer = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![arbitrary_erased_ty.into()],
+        vec![opaque_fn],
+        vec![],
+        0,
+    );
+    MirCastOp::new(disguised_data_pointer)
+        .set_attr_cast_kind(&ctx, MirCastKindAttr::PointerCoercionArrayToPointer);
+    assert!(
+        MirCastOp::new(disguised_data_pointer).verify(&ctx).is_err(),
+        "an unrelated coercion cannot turn the opaque function token into Erased data storage"
+    );
+
+    let shared_fn_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, fn_target_ty, false, MirPointerKind::SharedRef);
+    let fake_reborrow = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![shared_fn_ty.into()],
+        vec![opaque_fn],
+        vec![],
+        0,
+    );
+    let fake_reborrow = MirCastOp::new(fake_reborrow);
+    fake_reborrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    fake_reborrow.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    assert!(
+        fake_reborrow.verify(&ctx).is_err(),
+        "an opaque function-pointer value is not compiler storage that may be reborrowed"
+    );
+
+    // Keeping only kind+mutability while recursively pairing aggregate fields
+    // is insufficient: the canonical function token is also identified by
+    // its pointee. Otherwise a tuple cast can disguise data storage as a
+    // function pointer (or vice versa), after which individually legal casts
+    // can manufacture a reference.
+    let data_tuple_ty = MirTupleType::get(&mut ctx, vec![arbitrary_erased_ty.into()]);
+    let fn_tuple_ty = MirTupleType::get(&mut ctx, vec![opaque_fn_ty.into()]);
+    let nested_block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![data_tuple_ty.into(), fn_tuple_ty.into()],
+    );
+    let data_tuple = nested_block.deref(&ctx).get_argument(0);
+    let fn_tuple = nested_block.deref(&ctx).get_argument(1);
+    let nested_cast = |ctx: &mut Context, source, target| {
+        let op = Operation::new(
+            ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![target],
+            vec![source],
+            vec![],
+            0,
+        );
+        MirCastOp::new(op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+        op
+    };
+    let data_to_fn = nested_cast(&mut ctx, data_tuple, fn_tuple_ty.into());
+    assert!(
+        MirCastOp::new(data_to_fn).verify(&ctx).is_err(),
+        "an aggregate cast cannot manufacture a nested canonical function token"
+    );
+    assert!(
+        MirCastOp::new(nested_cast(&mut ctx, fn_tuple, data_tuple_ty.into(),))
+            .verify(&ctx)
+            .is_err(),
+        "an aggregate cast cannot disguise a nested function token as Erased data"
+    );
+
+    let forged_fn_tuple = data_to_fn.deref(&ctx).get_result(0);
+    let extract_forged_fn = Operation::new(
+        &mut ctx,
+        MirExtractFieldOp::get_concrete_op_info(),
+        vec![opaque_fn_ty.into()],
+        vec![forged_fn_tuple],
+        vec![],
+        0,
+    );
+    let extract_forged_fn = MirExtractFieldOp::new(extract_forged_fn);
+    extract_forged_fn.set_attr_index(&ctx, FieldIndexAttr(0));
+    assert!(extract_forged_fn.verify(&ctx).is_ok());
+
+    let forged_fn = extract_forged_fn.get_operation().deref(&ctx).get_result(0);
+    let expose_forged_fn = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![raw_ty.into()],
+        vec![forged_fn],
+        vec![],
+        0,
+    );
+    let expose_forged_fn = MirCastOp::new(expose_forged_fn);
+    expose_forged_fn.set_attr_cast_kind(&ctx, MirCastKindAttr::FnPtrToPtr);
+    expose_forged_fn.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RustCast);
+    assert!(expose_forged_fn.verify(&ctx).is_ok());
+
+    let forged_raw = expose_forged_fn.get_operation().deref(&ctx).get_result(0);
+    let reborrow_forged_fn = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![forged_raw],
+        vec![],
+        0,
+    );
+    let reborrow_forged_fn = MirCastOp::new(reborrow_forged_fn);
+    reborrow_forged_fn.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    reborrow_forged_fn.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    assert!(
+        reborrow_forged_fn.verify(&ctx).is_ok(),
+        "the laundering chain must be rejected at its aggregate reinterpretation"
+    );
+
+    let shared_marker_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, fn_target_ty, false, MirPointerKind::SharedRef);
+    let marker_tuple_ty = MirTupleType::get(&mut ctx, vec![fn_target_ty]);
+    let shared_marker_tuple_ty = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        marker_tuple_ty.into(),
+        false,
+        MirPointerKind::SharedRef,
+    );
+    let marker_array_ty = MirArrayType::get(&mut ctx, fn_target_ty, 1);
+    let shared_marker_array_ty = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        marker_array_ty.into(),
+        false,
+        MirPointerKind::SharedRef,
+    );
+    let shared_marker_slice_ty =
+        MirSliceType::get_with_kind(&mut ctx, fn_target_ty, MirPointerKind::SharedRef);
+    let projection_block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            shared_marker_ty.into(),
+            shared_marker_tuple_ty.into(),
+            shared_marker_array_ty.into(),
+            shared_marker_slice_ty.into(),
+            usize_ty.into(),
+        ],
+    );
+    let marker_address = projection_block.deref(&ctx).get_argument(0);
+    let marker_tuple_address = projection_block.deref(&ctx).get_argument(1);
+    let marker_array_address = projection_block.deref(&ctx).get_argument(2);
+    let marker_slice = projection_block.deref(&ctx).get_argument(3);
+    let zero = projection_block.deref(&ctx).get_argument(4);
+
+    let offset_to_token = Operation::new(
+        &mut ctx,
+        MirPtrOffsetOp::get_concrete_op_info(),
+        vec![opaque_fn_ty.into()],
+        vec![marker_address, zero],
+        vec![],
+        0,
+    );
+    assert!(
+        MirPtrOffsetOp::new(offset_to_token).verify(&ctx).is_err(),
+        "pointer arithmetic produces a data address, never a function token"
+    );
+
+    let field_address_to_token = Operation::new(
+        &mut ctx,
+        MirFieldAddrOp::get_concrete_op_info(),
+        vec![opaque_fn_ty.into()],
+        vec![marker_tuple_address],
+        vec![],
+        0,
+    );
+    let field_address_to_token = MirFieldAddrOp::new(field_address_to_token);
+    field_address_to_token.set_attr_field_index(&ctx, FieldIndexAttr(0));
+    assert!(
+        field_address_to_token.verify(&ctx).is_err(),
+        "a field address cannot masquerade as a function token"
+    );
+
+    let array_address_to_token = Operation::new(
+        &mut ctx,
+        MirArrayElementAddrOp::get_concrete_op_info(),
+        vec![opaque_fn_ty.into()],
+        vec![marker_array_address, zero],
+        vec![],
+        0,
+    );
+    assert!(
+        MirArrayElementAddrOp::new(array_address_to_token)
+            .verify(&ctx)
+            .is_err(),
+        "an array element address cannot masquerade as a function token"
+    );
+
+    let slice_data_to_token = Operation::new(
+        &mut ctx,
+        MirExtractFieldOp::get_concrete_op_info(),
+        vec![opaque_fn_ty.into()],
+        vec![marker_slice],
+        vec![],
+        0,
+    );
+    let slice_data_to_token = MirExtractFieldOp::new(slice_data_to_token);
+    slice_data_to_token.set_attr_index(&ctx, FieldIndexAttr(0));
+    assert!(
+        slice_data_to_token.verify(&ctx).is_err(),
+        "a slice data address cannot masquerade as a function token"
+    );
+
+    // A ClosureFnPointer cast must not extract captured reference bits as a
+    // function pointer, expose them as RawMut, and then reborrow them as
+    // UniqueRef. Only a genuinely non-capturing, zero-sized closure may enter
+    // the opaque function-pointer path.
+    let captured_ref = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        i32_ty.into(),
+        false,
+        MirPointerKind::SharedRef,
+    );
+    let captured_closure = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "CapturedClosure".into(),
+        vec!["capture_0".into()],
+        vec![captured_ref.into()],
+        vec![0],
+        vec![0],
+        8,
+        8,
+    );
+    let empty_closure = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "NonCapturingClosure".into(),
+        vec![],
+        vec![],
+        vec![],
+        vec![],
+        0,
+        1,
+    );
+    let closure_block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![captured_closure.into(), empty_closure.into()],
+    );
+    let captured_value = closure_block.deref(&ctx).get_argument(0);
+    let empty_value = closure_block.deref(&ctx).get_argument(1);
+    let closure_cast = |ctx: &mut Context, source| {
+        let op = Operation::new(
+            ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![opaque_fn_ty.into()],
+            vec![source],
+            vec![],
+            0,
+        );
+        MirCastOp::new(op)
+            .set_attr_cast_kind(ctx, MirCastKindAttr::PointerCoercionClosureFnPointer);
+        op
+    };
+    let captured_to_fn = closure_cast(&mut ctx, captured_value);
+    assert!(
+        MirCastOp::new(captured_to_fn).verify(&ctx).is_err(),
+        "a closure carrying SharedRef bytes cannot become an opaque function pointer"
+    );
+    assert!(
+        MirCastOp::new(closure_cast(&mut ctx, empty_value))
+            .verify(&ctx)
+            .is_err(),
+        "the importer materializes a closure function token directly; the legacy cast is not lowerable"
+    );
+
+    let captured_fn_value = captured_to_fn.deref(&ctx).get_result(0);
+    let exposed_capture = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![raw_ty.into()],
+        vec![captured_fn_value],
+        vec![],
+        0,
+    );
+    let exposed_capture = MirCastOp::new(exposed_capture);
+    exposed_capture.set_attr_cast_kind(&ctx, MirCastKindAttr::FnPtrToPtr);
+    exposed_capture.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RustCast);
+    assert!(exposed_capture.verify(&ctx).is_ok());
+
+    let exposed_capture_value = exposed_capture.get_operation().deref(&ctx).get_result(0);
+    let unique_capture = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![exposed_capture_value],
+        vec![],
+        0,
+    );
+    let unique_capture = MirCastOp::new(unique_capture);
+    unique_capture.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    unique_capture.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    assert!(
+        unique_capture.verify(&ctx).is_ok(),
+        "the chain must be stopped at ClosureFnPointer before later individually legal boundaries"
+    );
+}
diff --git a/crates/dialect-mir/tests/ops_test/control_flow.rs b/crates/dialect-mir/tests/ops_test/control_flow.rs
new file mode 100644
index 0000000000..5f2664f0b8
--- /dev/null
+++ b/crates/dialect-mir/tests/ops_test/control_flow.rs
@@ -0,0 +1,175 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::ops::{MirAssertOp, MirCondBranchOp, MirFuncOp, MirGotoOp, MirReturnOp};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::{
+        attributes::TypeAttr,
+        op_interfaces::OperandSegmentInterface,
+        types::{FP32Type, FunctionType, IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::Context,
+    op::Op,
+    operation::Operation,
+};
+
+#[test]
+fn test_mir_control_flow_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+
+    // 1. MirGotoOp
+    let target_block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let src_block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let arg_val = src_block.deref(&ctx).get_argument(0);
+
+    let op = Operation::new(
+        &mut ctx,
+        MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![arg_val],
+        vec![target_block],
+        0,
+    );
+    let goto_op = MirGotoOp::new(op);
+    assert!(goto_op.verify(&ctx).is_ok(), "Valid Goto");
+
+    let op_bad = Operation::new(
+        &mut ctx,
+        MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![target_block],
+        0,
+    );
+    assert!(
+        MirGotoOp::new(op_bad).verify(&ctx).is_err(),
+        "Goto missing operand"
+    );
+
+    // 2. MirCondBranchOp
+    let true_block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let false_block = BasicBlock::new(&mut ctx, None, vec![]);
+    let cond_block = BasicBlock::new(&mut ctx, None, vec![i1_ty.into(), i32_ty.into()]);
+    let cond_val = cond_block.deref(&ctx).get_argument(0);
+    let val = cond_block.deref(&ctx).get_argument(1);
+
+    let (cond_flat, cond_sizes) =
+        MirCondBranchOp::compute_segment_sizes(vec![vec![cond_val], vec![val], vec![]]);
+    let op_cond = Operation::new(
+        &mut ctx,
+        MirCondBranchOp::get_concrete_op_info(),
+        vec![],
+        cond_flat,
+        vec![true_block, false_block],
+        0,
+    );
+    MirCondBranchOp::new(op_cond).set_operand_segment_sizes(&ctx, cond_sizes);
+    let cond_br = MirCondBranchOp::new(op_cond);
+    assert!(cond_br.verify(&ctx).is_ok(), "Valid CondBranch");
+
+    let (cond_bad_flat, cond_bad_sizes) =
+        MirCondBranchOp::compute_segment_sizes(vec![vec![cond_val], vec![], vec![]]);
+    let op_cond_bad = Operation::new(
+        &mut ctx,
+        MirCondBranchOp::get_concrete_op_info(),
+        vec![],
+        cond_bad_flat,
+        vec![true_block, false_block],
+        0,
+    );
+    MirCondBranchOp::new(op_cond_bad).set_operand_segment_sizes(&ctx, cond_bad_sizes);
+    assert!(
+        MirCondBranchOp::new(op_cond_bad).verify(&ctx).is_err(),
+        "CondBranch missing operand"
+    );
+
+    // 3. MirReturnOp
+    let func_ty = FunctionType::get(&ctx, vec![], vec![i32_ty.into()]);
+    let func_ty_attr = TypeAttr::new(func_ty.into());
+
+    let func_op_ptr = Operation::new(
+        &mut ctx,
+        MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let mir_func = MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
+    let entry_block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let ret_val = entry_block.deref(&ctx).get_argument(0);
+
+    let region = mir_func.get_operation().deref(&ctx).get_region(0);
+    entry_block.insert_at_front(region, &ctx);
+
+    let ret_op = Operation::new(
+        &mut ctx,
+        MirReturnOp::get_concrete_op_info(),
+        vec![],
+        vec![ret_val],
+        vec![],
+        0,
+    );
+    ret_op.insert_at_back(entry_block, &ctx);
+
+    let mir_ret = MirReturnOp::new(ret_op);
+    assert!(mir_ret.verify(&ctx).is_ok(), "Valid Return");
+
+    let f32_ty = FP32Type::get(&ctx);
+    let f32_block = BasicBlock::new(&mut ctx, None, vec![f32_ty.into()]);
+    let f32_val = f32_block.deref(&ctx).get_argument(0);
+
+    let ret_op_bad = Operation::new(
+        &mut ctx,
+        MirReturnOp::get_concrete_op_info(),
+        vec![],
+        vec![f32_val],
+        vec![],
+        0,
+    );
+    ret_op_bad.insert_at_back(entry_block, &ctx);
+
+    let mir_ret_bad = MirReturnOp::new(ret_op_bad);
+    assert!(mir_ret_bad.verify(&ctx).is_err(), "Return type mismatch");
+
+    // 4. MirAssertOp
+    let assert_succ = BasicBlock::new(&mut ctx, None, vec![]);
+
+    let (assert_flat, assert_sizes) =
+        MirAssertOp::compute_segment_sizes(vec![vec![cond_val], vec![]]);
+    let op_assert = Operation::new(
+        &mut ctx,
+        MirAssertOp::get_concrete_op_info(),
+        vec![],
+        assert_flat,
+        vec![assert_succ],
+        0,
+    );
+    MirAssertOp::new(op_assert).set_operand_segment_sizes(&ctx, assert_sizes);
+    let assert_op = MirAssertOp::new(op_assert);
+    assert!(assert_op.verify(&ctx).is_ok(), "Valid Assert");
+
+    let (assert_bad_flat, assert_bad_sizes) =
+        MirAssertOp::compute_segment_sizes(vec![vec![val], vec![]]);
+    let op_assert_bad = Operation::new(
+        &mut ctx,
+        MirAssertOp::get_concrete_op_info(),
+        vec![],
+        assert_bad_flat,
+        vec![assert_succ],
+        0,
+    );
+    MirAssertOp::new(op_assert_bad).set_operand_segment_sizes(&ctx, assert_bad_sizes);
+    assert!(
+        MirAssertOp::new(op_assert_bad).verify(&ctx).is_err(),
+        "Assert cond type mismatch"
+    );
+}
diff --git a/crates/dialect-mir/tests/ops_test/enums.rs b/crates/dialect-mir/tests/ops_test/enums.rs
new file mode 100644
index 0000000000..09213860fd
--- /dev/null
+++ b/crates/dialect-mir/tests/ops_test/enums.rs
@@ -0,0 +1,406 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::{
+    attributes::{FieldIndexAttr, VariantIndexAttr},
+    ops::{MirConstructEnumOp, MirEnumPayloadOp, MirGetDiscriminantOp, MirSetDiscriminantOp},
+    types::{EnumVariant, MirEnumType, MirPtrType},
+};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::{
+        attributes::TypeAttr,
+        types::{IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::Context,
+    op::Op,
+    operation::Operation,
+};
+
+#[test]
+fn test_mir_set_discriminant_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signed);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let unit = |name: &str| EnumVariant::unit(name.to_string());
+
+    let enum_ty = MirEnumType::get(
+        &mut ctx,
+        "DeviceState".to_string(),
+        i8_ty.into(),
+        vec![0, 1],
+        vec![
+            unit("Empty"),
+            EnumVariant::new("Full".to_string(), vec![i32_ty.into()]),
+        ],
+    );
+
+    let enum_ptr_ty = MirPtrType::get_generic(&mut ctx, enum_ty.into(), true);
+    let blk = BasicBlock::new(&mut ctx, None, vec![enum_ptr_ty.into(), i8_ty.into()]);
+    let enum_ptr = blk.deref(&ctx).get_argument(0);
+    let discr_val = blk.deref(&ctx).get_argument(1);
+
+    // Malformed IR must be diagnosed without panicking, regardless of whether
+    // the generated operand-count interface happens to run first.
+    let op_no_operands = Operation::new(
+        &mut ctx,
+        MirSetDiscriminantOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    let no_operands = MirSetDiscriminantOp::new(op_no_operands);
+    no_operands.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(0));
+    assert!(no_operands.verify(&ctx).is_err(), "zero operands rejected");
+
+    let op_extra_operand = Operation::new(
+        &mut ctx,
+        MirSetDiscriminantOp::get_concrete_op_info(),
+        vec![],
+        vec![enum_ptr, discr_val],
+        vec![],
+        0,
+    );
+    let extra_operand = MirSetDiscriminantOp::new(op_extra_operand);
+    extra_operand.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(0));
+    assert!(
+        extra_operand.verify(&ctx).is_err(),
+        "extra operand rejected"
+    );
+
+    // Valid: pointer to enum plus the semantic target variant attribute.
+    let op_valid = Operation::new(
+        &mut ctx,
+        MirSetDiscriminantOp::get_concrete_op_info(),
+        vec![],
+        vec![enum_ptr],
+        vec![],
+        0,
+    );
+    let valid = MirSetDiscriminantOp::new(op_valid);
+    valid.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(1));
+    valid.set_attr_set_discriminant_enum_ty(&ctx, TypeAttr::new(enum_ty.into()));
+    assert!(valid.verify(&ctx).is_ok(), "Valid set_discriminant");
+
+    // Invalid: first operand is not a pointer.
+    let op_bad_ptr = Operation::new(
+        &mut ctx,
+        MirSetDiscriminantOp::get_concrete_op_info(),
+        vec![],
+        vec![discr_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirSetDiscriminantOp::new(op_bad_ptr).verify(&ctx).is_err(),
+        "Non-pointer enum operand rejected"
+    );
+
+    // Invalid: SetDiscriminant writes memory and therefore cannot accept an
+    // immutable pointer even when the pointee is the right enum.
+    let immutable_ptr_ty = MirPtrType::get_generic(&mut ctx, enum_ty.into(), false);
+    let immutable_block = BasicBlock::new(&mut ctx, None, vec![immutable_ptr_ty.into()]);
+    let immutable_ptr = immutable_block.deref(&ctx).get_argument(0);
+    let op_immutable = Operation::new(
+        &mut ctx,
+        MirSetDiscriminantOp::get_concrete_op_info(),
+        vec![],
+        vec![immutable_ptr],
+        vec![],
+        0,
+    );
+    let immutable = MirSetDiscriminantOp::new(op_immutable);
+    immutable.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(0));
+    assert!(
+        immutable.verify(&ctx).is_err(),
+        "immutable pointer rejected"
+    );
+
+    // Invalid: pointer does not point to an enum.
+    let i32_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let blk_i32 = BasicBlock::new(&mut ctx, None, vec![i32_ptr_ty.into(), i8_ty.into()]);
+    let i32_ptr = blk_i32.deref(&ctx).get_argument(0);
+    let op_bad_pointee = Operation::new(
+        &mut ctx,
+        MirSetDiscriminantOp::get_concrete_op_info(),
+        vec![],
+        vec![i32_ptr],
+        vec![],
+        0,
+    );
+    let bad_pointee = MirSetDiscriminantOp::new(op_bad_pointee);
+    bad_pointee.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(0));
+    assert!(
+        bad_pointee.verify(&ctx).is_err(),
+        "Non-enum pointee rejected"
+    );
+
+    // Invalid: target attribute is required.
+    let op_missing_target = Operation::new(
+        &mut ctx,
+        MirSetDiscriminantOp::get_concrete_op_info(),
+        vec![],
+        vec![enum_ptr],
+        vec![],
+        0,
+    );
+    assert!(
+        MirSetDiscriminantOp::new(op_missing_target)
+            .verify(&ctx)
+            .is_err(),
+        "Missing target rejected"
+    );
+
+    // Invalid: target index is out of bounds.
+    let op_oob = Operation::new(
+        &mut ctx,
+        MirSetDiscriminantOp::get_concrete_op_info(),
+        vec![],
+        vec![enum_ptr],
+        vec![],
+        0,
+    );
+    let oob = MirSetDiscriminantOp::new(op_oob);
+    oob.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(2));
+    assert!(oob.verify(&ctx).is_err(), "Out-of-bounds target rejected");
+}
+
+#[test]
+fn test_mir_enum_ops_malformed_arity_is_diagnostic() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let unit_enum = MirEnumType::get(
+        &mut ctx,
+        "Unit".into(),
+        i8_ty.into(),
+        vec![0],
+        vec![EnumVariant::unit("Only".into())],
+    );
+    let payload_enum = MirEnumType::get(
+        &mut ctx,
+        "Payload".into(),
+        i8_ty.into(),
+        vec![0],
+        vec![EnumVariant::new("Only".into(), vec![i32_ty.into()])],
+    );
+    let block = BasicBlock::new(&mut ctx, None, vec![unit_enum.into(), payload_enum.into()]);
+    let unit_value = block.deref(&ctx).get_argument(0);
+    let payload_value = block.deref(&ctx).get_argument(1);
+
+    let construct_no_result = Operation::new(
+        &mut ctx,
+        MirConstructEnumOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    let construct_no_result = MirConstructEnumOp::new(construct_no_result);
+    construct_no_result.set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
+    assert!(construct_no_result.verify(&ctx).is_err());
+
+    let construct_extra_result = Operation::new(
+        &mut ctx,
+        MirConstructEnumOp::get_concrete_op_info(),
+        vec![unit_enum.into(), unit_enum.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let construct_extra_result = MirConstructEnumOp::new(construct_extra_result);
+    construct_extra_result.set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
+    assert!(construct_extra_result.verify(&ctx).is_err());
+
+    let get_empty = Operation::new(
+        &mut ctx,
+        MirGetDiscriminantOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(MirGetDiscriminantOp::new(get_empty).verify(&ctx).is_err());
+    let get_extra = Operation::new(
+        &mut ctx,
+        MirGetDiscriminantOp::get_concrete_op_info(),
+        vec![i8_ty.into(), i8_ty.into()],
+        vec![unit_value, unit_value],
+        vec![],
+        0,
+    );
+    assert!(MirGetDiscriminantOp::new(get_extra).verify(&ctx).is_err());
+
+    let payload_empty = Operation::new(
+        &mut ctx,
+        MirEnumPayloadOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    let payload_empty = MirEnumPayloadOp::new(payload_empty);
+    payload_empty.set_attr_payload_variant_index(&ctx, VariantIndexAttr(0));
+    payload_empty.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
+    assert!(payload_empty.verify(&ctx).is_err());
+
+    let payload_extra = Operation::new(
+        &mut ctx,
+        MirEnumPayloadOp::get_concrete_op_info(),
+        vec![i32_ty.into(), i32_ty.into()],
+        vec![payload_value, payload_value],
+        vec![],
+        0,
+    );
+    let payload_extra = MirEnumPayloadOp::new(payload_extra);
+    payload_extra.set_attr_payload_variant_index(&ctx, VariantIndexAttr(0));
+    payload_extra.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
+    assert!(payload_extra.verify(&ctx).is_err());
+}
+
+#[test]
+fn test_mir_enum_payload_rejects_uninhabited_variant() {
+    use dialect_mir::types::{EnumCarrierKind, EnumEncoding, EnumLayoutKind};
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let enum_ty = MirEnumType::get_with_encoding(
+        &mut ctx,
+        "HasImpossibleField".into(),
+        i8_ty.into(),
+        vec![0, 1],
+        vec![
+            EnumVariant::unit("Live".into()),
+            // An uninhabited variant's unused physical offsets need not fit
+            // the object. The verifier must stop them reaching lowering.
+            EnumVariant::new_with_layout(
+                "Impossible".into(),
+                vec![i32_ty.into()],
+                vec![64],
+                vec![4],
+            ),
+        ],
+        EnumEncoding {
+            tag_offset: 0,
+            total_size: 1,
+            abi_align: 1,
+            layout_kind: EnumLayoutKind::Direct,
+            carrier_kind: EnumCarrierKind::Integer,
+            carrier_width: 8,
+            variant_inhabited: vec![1, 0],
+            ..EnumEncoding::default()
+        },
+    );
+    assert!(enum_ty.verify(&ctx).is_ok());
+
+    let block = BasicBlock::new(&mut ctx, None, vec![enum_ty.into()]);
+    let value = block.deref(&ctx).get_argument(0);
+    let op = Operation::new(
+        &mut ctx,
+        MirEnumPayloadOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![value],
+        vec![],
+        0,
+    );
+    let payload = MirEnumPayloadOp::new(op);
+    payload.set_attr_payload_variant_index(&ctx, VariantIndexAttr(1));
+    payload.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
+    assert!(payload.verify(&ctx).is_err());
+}
+
+/// Reachable-but-dead MIR (e.g. the residual arms of `array::try_from_fn`)
+/// can name uninhabited variants. The importer must lower such reads and
+/// constructions to typed undefs; if it ever emits the real ops again, these
+/// verifiers are the loud stop.
+#[test]
+fn test_uninhabited_enum_construct_and_discriminant_fail_verification() {
+    use dialect_mir::types::{EnumCarrierKind, EnumEncoding, EnumLayoutKind};
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+
+    // Constructing an uninhabited variant must fail verification.
+    let partial = MirEnumType::get_with_encoding(
+        &mut ctx,
+        "HasImpossibleVariant".into(),
+        i8_ty.into(),
+        vec![0, 1],
+        vec![
+            EnumVariant::unit("Live".into()),
+            EnumVariant::new_with_layout(
+                "Impossible".into(),
+                vec![i32_ty.into()],
+                vec![0],
+                vec![4],
+            ),
+        ],
+        EnumEncoding {
+            tag_offset: 0,
+            total_size: 8,
+            abi_align: 4,
+            layout_kind: EnumLayoutKind::Direct,
+            carrier_kind: EnumCarrierKind::Integer,
+            carrier_width: 8,
+            variant_inhabited: vec![1, 0],
+            ..EnumEncoding::default()
+        },
+    );
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let field = block.deref(&ctx).get_argument(0);
+    let construct = Operation::new(
+        &mut ctx,
+        MirConstructEnumOp::get_concrete_op_info(),
+        vec![partial.into()],
+        vec![field],
+        vec![],
+        0,
+    );
+    let construct = MirConstructEnumOp::new(construct);
+    construct.set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
+    assert!(construct.verify(&ctx).is_err());
+
+    // Reading the discriminant of a fully uninhabited enum must fail
+    // verification.
+    let never = MirEnumType::get_with_encoding(
+        &mut ctx,
+        "Never".into(),
+        i8_ty.into(),
+        vec![],
+        vec![],
+        EnumEncoding {
+            tag_offset: 0,
+            total_size: 0,
+            abi_align: 1,
+            layout_kind: EnumLayoutKind::Empty,
+            carrier_kind: EnumCarrierKind::None,
+            carrier_width: 0,
+            variant_inhabited: vec![],
+            ..EnumEncoding::default()
+        },
+    );
+    assert!(never.verify(&ctx).is_ok());
+    let never_block = BasicBlock::new(&mut ctx, None, vec![never.into()]);
+    let never_value = never_block.deref(&ctx).get_argument(0);
+    let get_discriminant = Operation::new(
+        &mut ctx,
+        MirGetDiscriminantOp::get_concrete_op_info(),
+        vec![i8_ty.into()],
+        vec![never_value],
+        vec![],
+        0,
+    );
+    let get_discriminant = MirGetDiscriminantOp::new(get_discriminant);
+    assert!(get_discriminant.verify(&ctx).is_err());
+}
diff --git a/crates/dialect-mir/tests/ops_test/main.rs b/crates/dialect-mir/tests/ops_test/main.rs
new file mode 100644
index 0000000000..a7d126d046
--- /dev/null
+++ b/crates/dialect-mir/tests/ops_test/main.rs
@@ -0,0 +1,16 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Tests build kinded fixture types directly; production minting lives in
+// mir-importer's facts.rs (see the workspace clippy.toml disallowed-methods).
+#![allow(clippy::disallowed_methods)]
+
+mod aggregates;
+mod cast_authority;
+mod control_flow;
+mod enums;
+mod memory;
+mod pointer_kinds;
+mod scalars_and_funcs;
diff --git a/crates/dialect-mir/tests/ops_test/memory.rs b/crates/dialect-mir/tests/ops_test/memory.rs
new file mode 100644
index 0000000000..ac740b48e2
--- /dev/null
+++ b/crates/dialect-mir/tests/ops_test/memory.rs
@@ -0,0 +1,340 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::{
+    ops::{MirGlobalAllocOp, MirLoadOp, MirPtrOffsetOp, MirStoreOp},
+    types::{MirPointerKind, MirPtrType},
+};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::{
+        attributes::{StringAttr, TypeAttr},
+        types::{FP32Type, IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::Context,
+    op::Op,
+    operation::Operation,
+    opts::mem2reg::{AllocInfo, PromotableOpInterface, PromotableOpKind},
+};
+
+#[test]
+fn test_mir_load_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+
+    let block = BasicBlock::new(&mut ctx, None, vec![ptr_ty.into()]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+
+    let op = Operation::new(
+        &mut ctx,
+        MirLoadOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![ptr_val],
+        vec![],
+        0,
+    );
+    let mir_load = MirLoadOp::new(op);
+    assert!(mir_load.verify(&ctx).is_ok(), "Valid MirLoadOp");
+
+    let block_i32 = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let i32_val = block_i32.deref(&ctx).get_argument(0);
+
+    let op_fail_operand = Operation::new(
+        &mut ctx,
+        MirLoadOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![i32_val],
+        vec![],
+        0,
+    );
+    let mir_load_fail_operand = MirLoadOp::new(op_fail_operand);
+    assert!(
+        mir_load_fail_operand.verify(&ctx).is_err(),
+        "MirLoadOp non-ptr operand"
+    );
+
+    let f32_ty = FP32Type::get(&ctx);
+    let op_fail_res = Operation::new(
+        &mut ctx,
+        MirLoadOp::get_concrete_op_info(),
+        vec![f32_ty.into()],
+        vec![ptr_val],
+        vec![],
+        0,
+    );
+    let mir_load_fail_res = MirLoadOp::new(op_fail_res);
+    assert!(
+        mir_load_fail_res.verify(&ctx).is_err(),
+        "MirLoadOp result mismatch"
+    );
+}
+
+#[test]
+fn test_mir_load_volatile_is_not_promotable() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let block = BasicBlock::new(&mut ctx, None, vec![ptr_ty.into()]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+
+    let op = Operation::new(
+        &mut ctx,
+        MirLoadOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![ptr_val],
+        vec![],
+        0,
+    );
+    let mir_load = MirLoadOp::new(op);
+    let alloc_info = AllocInfo {
+        ptr: ptr_val,
+        ty: i32_ty.into(),
+    };
+
+    assert!(!mir_load.is_volatile(&ctx));
+    assert!(matches!(
+        mir_load.promotion_kind(&ctx, &alloc_info),
+        PromotableOpKind::Load
+    ));
+
+    mir_load.set_volatile(&mut ctx, true);
+
+    assert!(mir_load.is_volatile(&ctx));
+    assert!(matches!(
+        mir_load.promotion_kind(&ctx, &alloc_info),
+        PromotableOpKind::NonPromotableUse
+    ));
+}
+
+#[test]
+fn test_mir_ptr_offset_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+
+    let block = BasicBlock::new(&mut ctx, None, vec![ptr_ty.into(), usize_ty.into()]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let idx_val = block.deref(&ctx).get_argument(1);
+
+    let op = Operation::new(
+        &mut ctx,
+        MirPtrOffsetOp::get_concrete_op_info(),
+        vec![ptr_ty.into()],
+        vec![ptr_val, idx_val],
+        vec![],
+        0,
+    );
+    let offset_op = MirPtrOffsetOp::new(op);
+    assert!(offset_op.verify(&ctx).is_ok(), "Valid MirPtrOffsetOp");
+    assert!(
+        offset_op.is_inbounds(&ctx),
+        "ordinary pointer offsets default to inbounds"
+    );
+    offset_op.set_inbounds(&mut ctx, false);
+    assert!(
+        !offset_op.is_inbounds(&ctx),
+        "wrapping pointer offsets retain their explicit semantics"
+    );
+
+    let block2 = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), usize_ty.into()]);
+    let i32_val = block2.deref(&ctx).get_argument(0);
+    let idx_val2 = block2.deref(&ctx).get_argument(1);
+
+    let op_bad_base = Operation::new(
+        &mut ctx,
+        MirPtrOffsetOp::get_concrete_op_info(),
+        vec![ptr_ty.into()],
+        vec![i32_val, idx_val2],
+        vec![],
+        0,
+    );
+    assert!(MirPtrOffsetOp::new(op_bad_base).verify(&ctx).is_err());
+
+    let f32_ty = FP32Type::get(&ctx);
+    let ptr_f32_ty = MirPtrType::get_generic(&mut ctx, f32_ty.into(), false);
+    let op_bad_res = Operation::new(
+        &mut ctx,
+        MirPtrOffsetOp::get_concrete_op_info(),
+        vec![ptr_f32_ty.into()],
+        vec![ptr_val, idx_val],
+        vec![],
+        0,
+    );
+    assert!(MirPtrOffsetOp::new(op_bad_res).verify(&ctx).is_err());
+}
+
+#[test]
+fn test_mir_store_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let block = BasicBlock::new(&mut ctx, None, vec![ptr_ty.into(), i32_ty.into()]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let val = block.deref(&ctx).get_argument(1);
+
+    let op = Operation::new(
+        &mut ctx,
+        MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![ptr_val, val],
+        vec![],
+        0,
+    );
+    assert!(MirStoreOp::new(op).verify(&ctx).is_ok(), "Valid MirStoreOp");
+
+    // Invalid: store to non-ptr
+    let op_bad_ptr = Operation::new(
+        &mut ctx,
+        MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![val, val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirStoreOp::new(op_bad_ptr).verify(&ctx).is_err(),
+        "MirStoreOp non-ptr dest"
+    );
+
+    // Invalid: type mismatch
+    let f32_ty = FP32Type::get(&ctx);
+    let block2 = BasicBlock::new(&mut ctx, None, vec![f32_ty.into()]);
+    let f32_val = block2.deref(&ctx).get_argument(0);
+    let op_bad_type = Operation::new(
+        &mut ctx,
+        MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![ptr_val, f32_val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirStoreOp::new(op_bad_type).verify(&ctx).is_err(),
+        "MirStoreOp type mismatch"
+    );
+}
+
+#[test]
+fn test_mir_store_volatile_is_not_promotable() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let block = BasicBlock::new(&mut ctx, None, vec![ptr_ty.into(), i32_ty.into()]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let val = block.deref(&ctx).get_argument(1);
+
+    let op = Operation::new(
+        &mut ctx,
+        MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![ptr_val, val],
+        vec![],
+        0,
+    );
+    let mir_store = MirStoreOp::new(op);
+    let alloc_info = AllocInfo {
+        ptr: ptr_val,
+        ty: i32_ty.into(),
+    };
+
+    assert!(!mir_store.is_volatile(&ctx));
+    match mir_store.promotion_kind(&ctx, &alloc_info) {
+        PromotableOpKind::Store(stored) => assert!(stored == val),
+        _ => panic!("non-volatile store should be promotable"),
+    }
+
+    mir_store.set_volatile(&mut ctx, true);
+
+    assert!(mir_store.is_volatile(&ctx));
+    assert!(matches!(
+        mir_store.promotion_kind(&ctx, &alloc_info),
+        PromotableOpKind::NonPromotableUse
+    ));
+}
+
+#[test]
+fn test_mir_global_alloc_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let f32_ty = FP32Type::get(&ctx);
+
+    // Helper: build a MirGlobalAllocOp whose result pointer is in `ptr_ty`
+    // address space, with valid attributes.
+    let build = |ctx: &mut Context, ptr_ty: pliron::r#type::TypedHandle<MirPtrType>| {
+        let op = Operation::new(
+            ctx,
+            MirGlobalAllocOp::get_concrete_op_info(),
+            vec![ptr_ty.into()],
+            vec![],
+            vec![],
+            0,
+        );
+        let alloc = MirGlobalAllocOp::new(op);
+        alloc.set_attr_global_type(ctx, TypeAttr::new(f32_ty.into()));
+        alloc.set_attr_global_key(ctx, StringAttr::new("k".to_string()));
+        alloc
+    };
+
+    // Global memory (addrspace 1) — the original allowed space.
+    let ptr_global = MirPtrType::get_global(&mut ctx, f32_ty.into(), true);
+    assert!(
+        build(&mut ctx, ptr_global).verify(&ctx).is_ok(),
+        "global addrspace accepted"
+    );
+
+    // Constant memory (addrspace 4) — added for `#[constant]` support.
+    let ptr_const = MirPtrType::get_constant(&mut ctx, f32_ty.into(), true);
+    assert!(
+        build(&mut ctx, ptr_const).verify(&ctx).is_ok(),
+        "constant addrspace accepted"
+    );
+
+    // Shared memory (addrspace 3) — must be rejected.
+    let ptr_shared = MirPtrType::get_shared(&mut ctx, f32_ty.into(), true);
+    assert!(
+        build(&mut ctx, ptr_shared).verify(&ctx).is_err(),
+        "shared addrspace rejected"
+    );
+
+    let ptr_unique_global = MirPtrType::get_with_kind(
+        &mut ctx,
+        f32_ty.into(),
+        true,
+        dialect_mir::types::address_space::GLOBAL,
+        MirPointerKind::UniqueRef,
+    );
+    assert!(
+        build(&mut ctx, ptr_unique_global).verify(&ctx).is_err(),
+        "a storage allocation cannot directly claim UniqueRef"
+    );
+
+    // Missing required attributes.
+    let no_attrs = Operation::new(
+        &mut ctx,
+        MirGlobalAllocOp::get_concrete_op_info(),
+        vec![ptr_global.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(
+        MirGlobalAllocOp::new(no_attrs).verify(&ctx).is_err(),
+        "missing attributes rejected"
+    );
+}
diff --git a/crates/dialect-mir/tests/ops_test/pointer_kinds.rs b/crates/dialect-mir/tests/ops_test/pointer_kinds.rs
new file mode 100644
index 0000000000..608b51ba56
--- /dev/null
+++ b/crates/dialect-mir/tests/ops_test/pointer_kinds.rs
@@ -0,0 +1,1256 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::{
+    attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr},
+    ops::{MirAllocaOp, MirCastOp, MirGlobalAllocOp, MirPtrOffsetOp, MirRefOp, MirSharedAllocOp},
+    types::{
+        MirArrayType, MirDisjointSliceType, MirPointerKind, MirPtrType, MirSliceType,
+        MirStructType, MirTupleType,
+    },
+};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::{
+        attributes::{IntegerAttr, StringAttr, TypeAttr},
+        types::{FP32Type, IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::Context,
+    op::Op,
+    operation::Operation,
+    r#type::TypeHandle,
+    utils::apint::APInt,
+};
+use std::num::NonZeroUsize;
+
+#[test]
+fn test_mir_pointer_kind_distinguishes_references_from_raw_pointers() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let pointee: pliron::r#type::TypeHandle = i32_ty.into();
+
+    let shared_ref =
+        MirPtrType::get_generic_with_kind(&mut ctx, pointee, false, MirPointerKind::SharedRef);
+    let raw_const =
+        MirPtrType::get_generic_with_kind(&mut ctx, pointee, false, MirPointerKind::RawConst);
+    let unique_ref =
+        MirPtrType::get_generic_with_kind(&mut ctx, pointee, true, MirPointerKind::UniqueRef);
+    let raw_mut =
+        MirPtrType::get_generic_with_kind(&mut ctx, pointee, true, MirPointerKind::RawMut);
+
+    assert_ne!(
+        shared_ref, raw_const,
+        "&T must remain distinct from *const T"
+    );
+    assert_ne!(
+        unique_ref, raw_mut,
+        "&mut T must remain distinct from *mut T"
+    );
+    assert_ne!(
+        shared_ref, unique_ref,
+        "&T must remain distinct from &mut T"
+    );
+    assert_ne!(
+        raw_const, raw_mut,
+        "*const T must remain distinct from *mut T"
+    );
+
+    assert_eq!(
+        shared_ref.deref(&ctx).pointer_kind(),
+        MirPointerKind::SharedRef
+    );
+    assert_eq!(
+        unique_ref.deref(&ctx).pointer_kind(),
+        MirPointerKind::UniqueRef
+    );
+    assert_eq!(
+        raw_const.deref(&ctx).pointer_kind(),
+        MirPointerKind::RawConst
+    );
+    assert_eq!(raw_mut.deref(&ctx).pointer_kind(), MirPointerKind::RawMut);
+}
+
+#[test]
+fn test_mir_slice_preserves_pointer_kind() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let element: pliron::r#type::TypeHandle = u8_ty.into();
+
+    let shared = MirSliceType::get_with_kind(&mut ctx, element, MirPointerKind::SharedRef);
+    let raw = MirSliceType::get_with_kind(&mut ctx, element, MirPointerKind::RawConst);
+
+    assert_ne!(shared, raw, "&[T] must remain distinct from *const [T]");
+    assert_eq!(shared.deref(&ctx).pointer_kind(), MirPointerKind::SharedRef);
+    assert_eq!(raw.deref(&ctx).pointer_kind(), MirPointerKind::RawConst);
+}
+
+#[test]
+fn test_mir_pointer_kind_mutability_consistency_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let invalid_shared = MirPtrType {
+        pointee: i32_ty.into(),
+        is_mutable: true,
+        address_space: 0,
+        kind: MirPointerKind::SharedRef,
+    };
+    let invalid_raw_mut = MirPtrType {
+        pointee: i32_ty.into(),
+        is_mutable: false,
+        address_space: 0,
+        kind: MirPointerKind::RawMut,
+    };
+
+    assert!(invalid_shared.verify(&ctx).is_err());
+    assert!(invalid_raw_mut.verify(&ctx).is_err());
+
+    let invalid_shared_slice = MirSliceType {
+        element_ty: i32_ty.into(),
+        is_mutable: true,
+        kind: MirPointerKind::SharedRef,
+    };
+    let valid_erased_mut_slice = MirSliceType {
+        element_ty: i32_ty.into(),
+        is_mutable: true,
+        kind: MirPointerKind::Erased,
+    };
+    assert!(invalid_shared_slice.verify(&ctx).is_err());
+    assert!(valid_erased_mut_slice.verify(&ctx).is_ok());
+}
+
+#[test]
+fn test_alloca_cannot_claim_a_rust_pointer_kind() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let erased = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let erased_alloca = Operation::new(
+        &mut ctx,
+        MirAllocaOp::get_concrete_op_info(),
+        vec![erased.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(MirAllocaOp::new(erased_alloca).verify(&ctx).is_ok());
+
+    let immutable_erased = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let immutable_alloca = Operation::new(
+        &mut ctx,
+        MirAllocaOp::get_concrete_op_info(),
+        vec![immutable_erased.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(
+        MirAllocaOp::new(immutable_alloca).verify(&ctx).is_err(),
+        "an alloca cannot masquerade as the immutable canonical function-pointer carrier"
+    );
+
+    let shared_erased = MirPtrType::get_shared(&mut ctx, i32_ty.into(), true);
+    let shared_alloca = Operation::new(
+        &mut ctx,
+        MirAllocaOp::get_concrete_op_info(),
+        vec![shared_erased.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(
+        MirAllocaOp::new(shared_alloca).verify(&ctx).is_err(),
+        "a stack allocation must remain in generic address space"
+    );
+
+    let unique =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
+    let unique_alloca = Operation::new(
+        &mut ctx,
+        MirAllocaOp::get_concrete_op_info(),
+        vec![unique.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(
+        MirAllocaOp::new(unique_alloca).verify(&ctx).is_err(),
+        "compiler storage must not manufacture UniqueRef"
+    );
+}
+
+#[test]
+fn test_shared_alloc_result_pointee_must_match_element_type() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
+    let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
+    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let mismatched_result = MirPtrType::get_shared(&mut ctx, i64_ty, true);
+    let op = Operation::new(
+        &mut ctx,
+        MirSharedAllocOp::get_concrete_op_info(),
+        vec![mismatched_result.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let alloc = MirSharedAllocOp::new(op);
+    alloc.set_attr_elem_type(&ctx, TypeAttr::new(i8_ty));
+    alloc.set_attr_size(
+        &ctx,
+        IntegerAttr::new(usize_ty, APInt::from_u64(1, NonZeroUsize::new(64).unwrap())),
+    );
+    alloc.set_attr_alloc_key(&ctx, StringAttr::new("mismatched-shared".to_string()));
+
+    let error = alloc
+        .verify(&ctx)
+        .expect_err("shared storage cannot claim an unrelated result pointee type");
+    assert!(
+        error
+            .to_string()
+            .contains("pointee type must match elem_type"),
+        "{error}"
+    );
+}
+
+#[test]
+fn test_pointer_kind_laundering_requires_explicit_authority() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let usize_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let raw_mut_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
+    let erased_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let erased_read_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let unique_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
+    let shared_ty = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        i32_ty.into(),
+        false,
+        MirPointerKind::SharedRef,
+    );
+    let raw_const_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), false, MirPointerKind::RawConst);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            raw_mut_ty.into(),
+            erased_ty.into(),
+            usize_ty.into(),
+            shared_ty.into(),
+            raw_const_ty.into(),
+            erased_read_ty.into(),
+        ],
+    );
+    let raw_mut = block.deref(&ctx).get_argument(0);
+    let erased = block.deref(&ctx).get_argument(1);
+    let offset = block.deref(&ctx).get_argument(2);
+    let shared = block.deref(&ctx).get_argument(3);
+    let raw_const = block.deref(&ctx).get_argument(4);
+    let erased_read = block.deref(&ctx).get_argument(5);
+
+    // The concrete laundering example: pointer arithmetic is not a Rust
+    // reborrow and cannot manufacture `&mut T` from `*mut T`.
+    let raw_offset_to_unique = Operation::new(
+        &mut ctx,
+        MirPtrOffsetOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![raw_mut, offset],
+        vec![],
+        0,
+    );
+    assert!(
+        MirPtrOffsetOp::new(raw_offset_to_unique)
+            .verify(&ctx)
+            .is_err(),
+        "ptr_offset must not invent UniqueRef from RawMut"
+    );
+
+    let erased_offset_to_unique = Operation::new(
+        &mut ctx,
+        MirPtrOffsetOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![erased, offset],
+        vec![],
+        0,
+    );
+    assert!(
+        MirPtrOffsetOp::new(erased_offset_to_unique)
+            .verify(&ctx)
+            .is_err(),
+        "ptr_offset must not recover UniqueRef from Erased"
+    );
+
+    let preserving_offset = Operation::new(
+        &mut ctx,
+        MirPtrOffsetOp::get_concrete_op_info(),
+        vec![raw_mut_ty.into()],
+        vec![raw_mut, offset],
+        vec![],
+        0,
+    );
+    assert!(MirPtrOffsetOp::new(preserving_offset).verify(&ctx).is_ok());
+
+    let erasing_offset = Operation::new(
+        &mut ctx,
+        MirPtrOffsetOp::get_concrete_op_info(),
+        vec![erased_ty.into()],
+        vec![raw_mut, offset],
+        vec![],
+        0,
+    );
+    assert!(MirPtrOffsetOp::new(erasing_offset).verify(&ctx).is_ok());
+
+    let mutability_launder = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![erased_ty.into()],
+        vec![erased_read],
+        vec![],
+        0,
+    );
+    let mutability_launder_cast = MirCastOp::new(mutability_launder);
+    mutability_launder_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    assert!(
+        mutability_launder_cast.verify(&ctx).is_err(),
+        "an unmarked cast cannot manufacture writable Erased evidence"
+    );
+
+    let reborrow = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![raw_mut],
+        vec![],
+        0,
+    );
+    let reborrow_cast = MirCastOp::new(reborrow);
+    reborrow_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    assert!(
+        reborrow_cast.verify(&ctx).is_err(),
+        "an unmarked cast must not manufacture UniqueRef"
+    );
+    reborrow_cast.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    assert!(
+        reborrow_cast.verify(&ctx).is_ok(),
+        "a rustc-declared reborrow is the explicit authority"
+    );
+
+    for (target, authority) in [
+        (unique_ty.into(), MirPointerKindAuthorityAttr::Reborrow),
+        (raw_mut_ty.into(), MirPointerKindAuthorityAttr::RawAddress),
+    ] {
+        let mutable_storage_boundary = Operation::new(
+            &mut ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![target],
+            vec![erased],
+            vec![],
+            0,
+        );
+        let mutable_storage_boundary_cast = MirCastOp::new(mutable_storage_boundary);
+        mutable_storage_boundary_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+        mutable_storage_boundary_cast.set_pointer_kind_authority(&mut ctx, authority);
+        assert!(
+            mutable_storage_boundary_cast.verify(&ctx).is_ok(),
+            "mutable compiler storage is a valid source for a mutable Rust boundary"
+        );
+    }
+
+    let raw_to_shared_static = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![shared_ty.into()],
+        vec![raw_const],
+        vec![],
+        0,
+    );
+    let raw_to_shared_static_cast = MirCastOp::new(raw_to_shared_static);
+    raw_to_shared_static_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    raw_to_shared_static_cast
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    assert!(
+        raw_to_shared_static_cast.verify(&ctx).is_err(),
+        "StaticAddress may establish a typed static value only from Erased storage, not relabel an arbitrary raw pointer as SharedRef"
+    );
+
+    let raw_to_erased = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![erased_read_ty.into()],
+        vec![raw_const],
+        vec![],
+        0,
+    );
+    let raw_to_erased_cast = MirCastOp::new(raw_to_erased);
+    raw_to_erased_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    assert!(raw_to_erased_cast.verify(&ctx).is_ok());
+    let erased_from_raw = raw_to_erased.deref(&ctx).get_result(0);
+    let laundered_static = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![shared_ty.into()],
+        vec![erased_from_raw],
+        vec![],
+        0,
+    );
+    let laundered_static_cast = MirCastOp::new(laundered_static);
+    laundered_static_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    laundered_static_cast
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    assert!(
+        laundered_static_cast.verify(&ctx).is_err(),
+        "erasing RawConst must not make it valid StaticAddress storage"
+    );
+
+    let raw_mut_to_erased = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![erased_ty.into()],
+        vec![raw_mut],
+        vec![],
+        0,
+    );
+    let raw_mut_to_erased_cast = MirCastOp::new(raw_mut_to_erased);
+    raw_mut_to_erased_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    assert!(raw_mut_to_erased_cast.verify(&ctx).is_ok());
+    let erased_from_raw_mut = raw_mut_to_erased.deref(&ctx).get_result(0);
+    let laundered_abi = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![erased_from_raw_mut],
+        vec![],
+        0,
+    );
+    let laundered_abi_cast = MirCastOp::new(laundered_abi);
+    laundered_abi_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    laundered_abi_cast
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::AbiBoundary);
+    assert!(
+        laundered_abi_cast.verify(&ctx).is_err(),
+        "erasing RawMut must not let AbiBoundary manufacture UniqueRef"
+    );
+
+    let global_erased_ty = MirPtrType::get_with_kind(
+        &mut ctx,
+        i32_ty.into(),
+        false,
+        dialect_mir::types::address_space::GLOBAL,
+        MirPointerKind::Erased,
+    );
+    let global_op = Operation::new(
+        &mut ctx,
+        MirGlobalAllocOp::get_concrete_op_info(),
+        vec![global_erased_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let global = MirGlobalAllocOp::new(global_op);
+    global.set_attr_global_type(&ctx, TypeAttr::new(i32_ty.into()));
+    global.set_attr_global_key(&ctx, StringAttr::new("lineage-global".to_string()));
+    assert!(global.verify(&ctx).is_ok());
+    let global_storage = global_op.deref(&ctx).get_result(0);
+    let typed_global = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![shared_ty.into()],
+        vec![global_storage],
+        vec![],
+        0,
+    );
+    let typed_global_cast = MirCastOp::new(typed_global);
+    typed_global_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    typed_global_cast
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    assert!(
+        typed_global_cast.verify(&ctx).is_ok(),
+        "StaticAddress accepts a verified global-allocation root"
+    );
+
+    let shared_erased_ty = MirPtrType::get_shared(&mut ctx, i32_ty.into(), true);
+    let shared_op = Operation::new(
+        &mut ctx,
+        MirSharedAllocOp::get_concrete_op_info(),
+        vec![shared_erased_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let shared_alloc = MirSharedAllocOp::new(shared_op);
+    shared_alloc.set_attr_elem_type(&ctx, TypeAttr::new(i32_ty.into()));
+    shared_alloc.set_attr_size(
+        &ctx,
+        IntegerAttr::new(usize_ty, APInt::from_u64(1, NonZeroUsize::new(64).unwrap())),
+    );
+    shared_alloc.set_attr_alloc_key(&ctx, StringAttr::new("lineage-shared".to_string()));
+    assert!(shared_alloc.verify(&ctx).is_ok());
+    let shared_storage = shared_op.deref(&ctx).get_result(0);
+    let typed_shared = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![raw_mut_ty.into()],
+        vec![shared_storage],
+        vec![],
+        0,
+    );
+    let typed_shared_cast = MirCastOp::new(typed_shared);
+    typed_shared_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    typed_shared_cast
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    assert!(
+        typed_shared_cast.verify(&ctx).is_ok(),
+        "StaticAddress accepts a verified shared-allocation root"
+    );
+
+    let alloca_op = Operation::new(
+        &mut ctx,
+        MirAllocaOp::get_concrete_op_info(),
+        vec![erased_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let alloca = MirAllocaOp::new(alloca_op);
+    assert!(alloca.verify(&ctx).is_ok());
+    let compiler_storage = alloca_op.deref(&ctx).get_result(0);
+    let typed_abi = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![raw_mut_ty.into()],
+        vec![compiler_storage],
+        vec![],
+        0,
+    );
+    let typed_abi_cast = MirCastOp::new(typed_abi);
+    typed_abi_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    typed_abi_cast.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::AbiBoundary);
+    assert!(
+        typed_abi_cast.verify(&ctx).is_ok(),
+        "AbiBoundary accepts verified compiler-owned alloca storage"
+    );
+
+    for (target, authority) in [
+        (unique_ty.into(), MirPointerKindAuthorityAttr::Reborrow),
+        (raw_mut_ty.into(), MirPointerKindAuthorityAttr::RawAddress),
+        (
+            raw_mut_ty.into(),
+            MirPointerKindAuthorityAttr::StaticAddress,
+        ),
+        (raw_mut_ty.into(), MirPointerKindAuthorityAttr::AbiBoundary),
+    ] {
+        let immutable_storage_boundary = Operation::new(
+            &mut ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![target],
+            vec![erased_read],
+            vec![],
+            0,
+        );
+        let immutable_storage_boundary_cast = MirCastOp::new(immutable_storage_boundary);
+        immutable_storage_boundary_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+        immutable_storage_boundary_cast.set_pointer_kind_authority(&mut ctx, authority);
+        assert!(
+            immutable_storage_boundary_cast.verify(&ctx).is_err(),
+            "an immutable Erased thin pointer cannot establish a mutable Rust pointer kind"
+        );
+    }
+
+    let wrong_authority = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![erased],
+        vec![],
+        0,
+    );
+    let wrong_authority_cast = MirCastOp::new(wrong_authority);
+    wrong_authority_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    wrong_authority_cast
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RawAddress);
+    assert!(
+        wrong_authority_cast.verify(&ctx).is_err(),
+        "RawAddress authority cannot establish a reference kind"
+    );
+
+    let inline_asm_authority = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![erased],
+        vec![],
+        0,
+    );
+    let inline_asm_authority_cast = MirCastOp::new(inline_asm_authority);
+    inline_asm_authority_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    inline_asm_authority_cast
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::InlineAsm);
+    assert!(
+        inline_asm_authority_cast.verify(&ctx).is_err(),
+        "InlineAsm is a producer authority and must never authorize a cast"
+    );
+
+    let integer_reborrow = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![offset],
+        vec![],
+        0,
+    );
+    let integer_reborrow_cast = MirCastOp::new(integer_reborrow);
+    integer_reborrow_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    integer_reborrow_cast
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    assert!(
+        integer_reborrow_cast.verify(&ctx).is_err(),
+        "Reborrow authority cannot reinterpret an integer as a Rust reference"
+    );
+    integer_reborrow_cast
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RustCast);
+    assert!(
+        integer_reborrow_cast.verify(&ctx).is_err(),
+        "RustCast authority cannot make an integer a PtrToPtr operand"
+    );
+    integer_reborrow_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::FnPtrToPtr);
+    assert!(
+        integer_reborrow_cast.verify(&ctx).is_err(),
+        "FnPtrToPtr also requires a real pointer carrier"
+    );
+
+    let f32_ty = FP32Type::get(&ctx);
+    let wrong_pointee_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, f32_ty.into(), true, MirPointerKind::RawMut);
+    let wrong_pointee_block = BasicBlock::new(&mut ctx, None, vec![wrong_pointee_ty.into()]);
+    let wrong_pointee = wrong_pointee_block.deref(&ctx).get_argument(0);
+    let wrong_pointee_reborrow = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![wrong_pointee],
+        vec![],
+        0,
+    );
+    let wrong_pointee_reborrow_cast = MirCastOp::new(wrong_pointee_reborrow);
+    wrong_pointee_reborrow_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    wrong_pointee_reborrow_cast
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    assert!(
+        wrong_pointee_reborrow_cast.verify(&ctx).is_err(),
+        "Reborrow authority must retain the pointee type"
+    );
+
+    for immutable_source in [shared, raw_const] {
+        let invalid_unique = Operation::new(
+            &mut ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![unique_ty.into()],
+            vec![immutable_source],
+            vec![],
+            0,
+        );
+        let invalid_unique_cast = MirCastOp::new(invalid_unique);
+        invalid_unique_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+        invalid_unique_cast
+            .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+        assert!(
+            invalid_unique_cast.verify(&ctx).is_err(),
+            "an immutable source cannot be relabelled as UniqueRef by Reborrow authority"
+        );
+
+        let invalid_raw_mut = Operation::new(
+            &mut ctx,
+            MirCastOp::get_concrete_op_info(),
+            vec![raw_mut_ty.into()],
+            vec![immutable_source],
+            vec![],
+            0,
+        );
+        let invalid_raw_mut_cast = MirCastOp::new(invalid_raw_mut);
+        invalid_raw_mut_cast.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+        invalid_raw_mut_cast
+            .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RawAddress);
+        assert!(
+            invalid_raw_mut_cast.verify(&ctx).is_err(),
+            "an immutable source cannot be relabelled as RawMut by RawAddress authority"
+        );
+    }
+}
+
+#[test]
+fn test_promoted_empty_mutable_reference_is_a_narrow_static_exception() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let empty_array_ty = MirArrayType::get(&mut ctx, i32_ty.into(), 0);
+    let nonempty_array_ty = MirArrayType::get(&mut ctx, i32_ty.into(), 1);
+
+    let empty_storage_ty = MirPtrType::get_with_kind(
+        &mut ctx,
+        empty_array_ty.into(),
+        false,
+        dialect_mir::types::address_space::GLOBAL,
+        MirPointerKind::Erased,
+    );
+    let empty_unique_ty = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        empty_array_ty.into(),
+        true,
+        MirPointerKind::UniqueRef,
+    );
+    let empty_global_op = Operation::new(
+        &mut ctx,
+        MirGlobalAllocOp::get_concrete_op_info(),
+        vec![empty_storage_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let empty_global = MirGlobalAllocOp::new(empty_global_op);
+    empty_global.set_attr_global_type(&ctx, TypeAttr::new(empty_array_ty.into()));
+    empty_global.set_attr_global_key(
+        &ctx,
+        StringAttr::new("promoted-empty-mutable-reference".to_string()),
+    );
+    empty_global.set_alignment_value(&mut ctx, 4);
+    empty_global_op.deref_mut(&ctx).attributes.set(
+        "global_initializer_hex".try_into().unwrap(),
+        StringAttr::new(String::new()),
+    );
+    empty_global.mark_immutable(&mut ctx);
+    assert!(empty_global.verify(&ctx).is_ok());
+
+    let empty_global_storage = empty_global_op.deref(&ctx).get_result(0);
+    let empty_static_borrow_op = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![empty_unique_ty.into()],
+        vec![empty_global_storage],
+        vec![],
+        0,
+    );
+    let empty_static_borrow = MirCastOp::new(empty_static_borrow_op);
+    empty_static_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    empty_static_borrow
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+
+    empty_global.set_alignment_value(&mut ctx, 1);
+    assert!(
+        empty_static_borrow.verify(&ctx).is_err(),
+        "even [i32; 0] must retain i32's natural four-byte alignment"
+    );
+    empty_global.set_alignment_value(&mut ctx, 4);
+    assert!(
+        empty_static_borrow.verify(&ctx).is_ok(),
+        "an immutable promoted [T; 0] global may back rustc's vacuous &mut []"
+    );
+
+    empty_global_op.deref_mut(&ctx).attributes.set(
+        "global_initializer_hex".try_into().unwrap(),
+        StringAttr::new("00".to_string()),
+    );
+    assert!(
+        empty_static_borrow.verify(&ctx).is_err(),
+        "the exception requires an actually empty initializer, not merely the attribute"
+    );
+    empty_global_op.deref_mut(&ctx).attributes.set(
+        "global_initializer_hex".try_into().unwrap(),
+        StringAttr::new(String::new()),
+    );
+    empty_global_op.deref_mut(&ctx).attributes.set(
+        "global_initializer_relocations".try_into().unwrap(),
+        StringAttr::new("unexpected-relocation".to_string()),
+    );
+    assert!(
+        empty_static_borrow.verify(&ctx).is_err(),
+        "zero-byte promoted storage cannot carry a relocation"
+    );
+
+    let mutable_empty_global_op = Operation::new(
+        &mut ctx,
+        MirGlobalAllocOp::get_concrete_op_info(),
+        vec![empty_storage_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let mutable_empty_global = MirGlobalAllocOp::new(mutable_empty_global_op);
+    mutable_empty_global.set_attr_global_type(&ctx, TypeAttr::new(empty_array_ty.into()));
+    mutable_empty_global.set_attr_global_key(
+        &ctx,
+        StringAttr::new("non-promoted-empty-global".to_string()),
+    );
+    assert!(mutable_empty_global.verify(&ctx).is_ok());
+    let mutable_empty_storage = mutable_empty_global_op.deref(&ctx).get_result(0);
+    let mutable_empty_borrow_op = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![empty_unique_ty.into()],
+        vec![mutable_empty_storage],
+        vec![],
+        0,
+    );
+    let mutable_empty_borrow = MirCastOp::new(mutable_empty_borrow_op);
+    mutable_empty_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    mutable_empty_borrow
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    assert!(
+        mutable_empty_borrow.verify(&ctx).is_err(),
+        "the [T; 0] exception requires compiler-promoted immutable storage"
+    );
+
+    let aligned_element_ty: TypeHandle = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "Align16".to_string(),
+        vec!["value".to_string()],
+        vec![i32_ty.into()],
+        vec![],
+        vec![0],
+        16,
+        16,
+    )
+    .into();
+    let aligned_empty_array_ty = MirArrayType::get(&mut ctx, aligned_element_ty, 0);
+    let underaligned_storage_ty = MirPtrType::get_with_kind(
+        &mut ctx,
+        aligned_empty_array_ty.into(),
+        false,
+        dialect_mir::types::address_space::GLOBAL,
+        MirPointerKind::Erased,
+    );
+    let aligned_empty_unique_ty = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        aligned_empty_array_ty.into(),
+        true,
+        MirPointerKind::UniqueRef,
+    );
+    let underaligned_global_op = Operation::new(
+        &mut ctx,
+        MirGlobalAllocOp::get_concrete_op_info(),
+        vec![underaligned_storage_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let underaligned_global = MirGlobalAllocOp::new(underaligned_global_op);
+    underaligned_global.set_attr_global_type(&ctx, TypeAttr::new(aligned_empty_array_ty.into()));
+    underaligned_global.set_attr_global_key(
+        &ctx,
+        StringAttr::new("underaligned-empty-reference".to_string()),
+    );
+    underaligned_global.set_alignment_value(&mut ctx, 1);
+    underaligned_global_op.deref_mut(&ctx).attributes.set(
+        "global_initializer_hex".try_into().unwrap(),
+        StringAttr::new(String::new()),
+    );
+    underaligned_global.mark_immutable(&mut ctx);
+    assert!(underaligned_global.verify(&ctx).is_ok());
+    let underaligned_storage = underaligned_global_op.deref(&ctx).get_result(0);
+    let underaligned_borrow_op = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![aligned_empty_unique_ty.into()],
+        vec![underaligned_storage],
+        vec![],
+        0,
+    );
+    let underaligned_borrow = MirCastOp::new(underaligned_borrow_op);
+    underaligned_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    underaligned_borrow
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    assert!(
+        underaligned_borrow.verify(&ctx).is_err(),
+        "promoted &mut [Align16; 0] requires at least 16-byte global alignment"
+    );
+
+    let nonempty_storage_ty = MirPtrType::get_with_kind(
+        &mut ctx,
+        nonempty_array_ty.into(),
+        false,
+        dialect_mir::types::address_space::GLOBAL,
+        MirPointerKind::Erased,
+    );
+    let nonempty_unique_ty = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        nonempty_array_ty.into(),
+        true,
+        MirPointerKind::UniqueRef,
+    );
+    let nonempty_global_op = Operation::new(
+        &mut ctx,
+        MirGlobalAllocOp::get_concrete_op_info(),
+        vec![nonempty_storage_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let nonempty_global = MirGlobalAllocOp::new(nonempty_global_op);
+    nonempty_global.set_attr_global_type(&ctx, TypeAttr::new(nonempty_array_ty.into()));
+    nonempty_global.set_attr_global_key(
+        &ctx,
+        StringAttr::new("promoted-nonempty-mutable-reference".to_string()),
+    );
+    nonempty_global.mark_immutable(&mut ctx);
+    assert!(nonempty_global.verify(&ctx).is_ok());
+    let nonempty_global_storage = nonempty_global_op.deref(&ctx).get_result(0);
+    let nonempty_static_borrow_op = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![nonempty_unique_ty.into()],
+        vec![nonempty_global_storage],
+        vec![],
+        0,
+    );
+    let nonempty_static_borrow = MirCastOp::new(nonempty_static_borrow_op);
+    nonempty_static_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    nonempty_static_borrow
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    assert!(
+        nonempty_static_borrow.verify(&ctx).is_err(),
+        "StaticAddress must never manufacture UniqueRef for non-empty promoted storage"
+    );
+
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![empty_storage_ty.into(), empty_unique_ty.into()],
+    );
+    let erased_block_argument = block.deref(&ctx).get_argument(0);
+    let block_argument_borrow_op = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![empty_unique_ty.into()],
+        vec![erased_block_argument],
+        vec![],
+        0,
+    );
+    let block_argument_borrow = MirCastOp::new(block_argument_borrow_op);
+    block_argument_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    block_argument_borrow
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    assert!(
+        block_argument_borrow.verify(&ctx).is_err(),
+        "an Erased [T; 0] block argument has no proven promoted-global lineage"
+    );
+
+    let raw_empty_ty = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        empty_array_ty.into(),
+        false,
+        MirPointerKind::RawConst,
+    );
+    let raw_block = BasicBlock::new(&mut ctx, None, vec![raw_empty_ty.into()]);
+    let raw_empty = raw_block.deref(&ctx).get_argument(0);
+    let erase_raw_op = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![empty_storage_ty.into()],
+        vec![raw_empty],
+        vec![],
+        0,
+    );
+    let erase_raw = MirCastOp::new(erase_raw_op);
+    erase_raw.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    assert!(erase_raw.verify(&ctx).is_ok());
+    let erased_from_raw = erase_raw_op.deref(&ctx).get_result(0);
+    let laundered_borrow_op = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![empty_unique_ty.into()],
+        vec![erased_from_raw],
+        vec![],
+        0,
+    );
+    let laundered_borrow = MirCastOp::new(laundered_borrow_op);
+    laundered_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    laundered_borrow
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    assert!(
+        laundered_borrow.verify(&ctx).is_err(),
+        "RawConst -> Erased must not launder a zero-length pointer into UniqueRef"
+    );
+
+    let byte_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let byte_storage_ty = MirPtrType::get_with_kind(
+        &mut ctx,
+        byte_ty.into(),
+        false,
+        dialect_mir::types::address_space::GLOBAL,
+        MirPointerKind::Erased,
+    );
+    let byte_global_op = Operation::new(
+        &mut ctx,
+        MirGlobalAllocOp::get_concrete_op_info(),
+        vec![byte_storage_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let byte_global = MirGlobalAllocOp::new(byte_global_op);
+    byte_global.set_attr_global_type(&ctx, TypeAttr::new(byte_ty.into()));
+    byte_global.set_attr_global_key(
+        &ctx,
+        StringAttr::new("misaligned-empty-reference-root".to_string()),
+    );
+    byte_global.mark_immutable(&mut ctx);
+    assert!(byte_global.verify(&ctx).is_ok());
+    let byte_storage = byte_global_op.deref(&ctx).get_result(0);
+    let retype_root_op = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![empty_storage_ty.into()],
+        vec![byte_storage],
+        vec![],
+        0,
+    );
+    let retype_root = MirCastOp::new(retype_root_op);
+    retype_root.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    assert!(retype_root.verify(&ctx).is_ok());
+    let retyped_storage = retype_root_op.deref(&ctx).get_result(0);
+    let misaligned_borrow_op = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![empty_unique_ty.into()],
+        vec![retyped_storage],
+        vec![],
+        0,
+    );
+    let misaligned_borrow = MirCastOp::new(misaligned_borrow_op);
+    misaligned_borrow.set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    misaligned_borrow
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    assert!(
+        misaligned_borrow.verify(&ctx).is_err(),
+        "an immutable byte global cannot be retyped into an aligned &mut [i32; 0] capability"
+    );
+}
+
+fn promoted_empty_unique_ref_verifies(
+    ctx: &mut Context,
+    element_ty: TypeHandle,
+    alignment: u64,
+) -> bool {
+    let empty_array_ty: TypeHandle = MirArrayType::get(ctx, element_ty, 0).into();
+    let storage_ty = MirPtrType::get_with_kind(
+        ctx,
+        empty_array_ty,
+        false,
+        dialect_mir::types::address_space::GLOBAL,
+        MirPointerKind::Erased,
+    );
+    let unique_ty =
+        MirPtrType::get_generic_with_kind(ctx, empty_array_ty, true, MirPointerKind::UniqueRef);
+    let global_op = Operation::new(
+        ctx,
+        MirGlobalAllocOp::get_concrete_op_info(),
+        vec![storage_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let global = MirGlobalAllocOp::new(global_op);
+    global.set_attr_global_type(ctx, TypeAttr::new(empty_array_ty));
+    global.set_attr_global_key(ctx, StringAttr::new("promoted-empty-shape".to_string()));
+    global.set_alignment_value(ctx, alignment);
+    global_op.deref_mut(ctx).attributes.set(
+        "global_initializer_hex".try_into().unwrap(),
+        StringAttr::new(String::new()),
+    );
+    global.mark_immutable(ctx);
+
+    let storage = global_op.deref(ctx).get_result(0);
+    let cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![unique_ty.into()],
+        vec![storage],
+        vec![],
+        0,
+    );
+    let cast = MirCastOp::new(cast_op);
+    cast.set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+    cast.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    cast.verify(ctx).is_ok()
+}
+
+#[test]
+fn test_promoted_empty_alignment_covers_supported_fat_and_unit_elements() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let byte: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+    let word: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+    let unit: TypeHandle = MirTupleType::get(&mut ctx, vec![]).into();
+    let slice: TypeHandle =
+        MirSliceType::get_with_kind(&mut ctx, byte, MirPointerKind::SharedRef).into();
+    let disjoint: TypeHandle = MirDisjointSliceType::get(&mut ctx, byte).into();
+
+    assert!(promoted_empty_unique_ref_verifies(&mut ctx, unit, 1));
+    assert!(promoted_empty_unique_ref_verifies(&mut ctx, slice, 8));
+    assert!(promoted_empty_unique_ref_verifies(&mut ctx, disjoint, 8));
+    assert!(promoted_empty_unique_ref_verifies(&mut ctx, word, 8));
+    assert!(
+        !promoted_empty_unique_ref_verifies(&mut ctx, word, 12),
+        "a non-power-of-two numeric value is not a valid alignment guarantee"
+    );
+    assert!(
+        !promoted_empty_unique_ref_verifies(&mut ctx, slice, 4),
+        "a stored slice value still requires pointer-word alignment"
+    );
+}
+
+#[test]
+fn test_mir_ref_requires_exact_pointer_kind_authority() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let shared_ty = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        i32_ty.into(),
+        false,
+        MirPointerKind::SharedRef,
+    );
+    let unique_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
+    let raw_const_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), false, MirPointerKind::RawConst);
+    let raw_mut_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
+    let erased_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let global_shared_ty = MirPtrType::get_with_kind(
+        &mut ctx,
+        i32_ty.into(),
+        false,
+        dialect_mir::types::address_space::GLOBAL,
+        MirPointerKind::SharedRef,
+    );
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let value = block.deref(&ctx).get_argument(0);
+
+    let build =
+        |ctx: &mut Context, result_ty, mutable, authority: Option<MirPointerKindAuthorityAttr>| {
+            let op = Operation::new(
+                ctx,
+                MirRefOp::get_concrete_op_info(),
+                vec![result_ty],
+                vec![value],
+                vec![],
+                0,
+            );
+            let reference = MirRefOp::new(op);
+            reference.set_mutable(ctx, mutable);
+            if let Some(authority) = authority {
+                reference.set_pointer_kind_authority(ctx, authority);
+            }
+            op
+        };
+
+    for (result_ty, mutable, authority) in [
+        (
+            shared_ty.into(),
+            false,
+            MirPointerKindAuthorityAttr::Reborrow,
+        ),
+        (
+            unique_ty.into(),
+            true,
+            MirPointerKindAuthorityAttr::Reborrow,
+        ),
+        (
+            raw_const_ty.into(),
+            false,
+            MirPointerKindAuthorityAttr::RawAddress,
+        ),
+        (
+            raw_mut_ty.into(),
+            true,
+            MirPointerKindAuthorityAttr::RawAddress,
+        ),
+        (
+            shared_ty.into(),
+            false,
+            MirPointerKindAuthorityAttr::StaticAddress,
+        ),
+    ] {
+        assert!(
+            MirRefOp::new(build(&mut ctx, result_ty, mutable, Some(authority)))
+                .verify(&ctx)
+                .is_ok()
+        );
+    }
+
+    assert!(
+        MirRefOp::new(build(&mut ctx, shared_ty.into(), false, None))
+            .verify(&ctx)
+            .is_err(),
+        "mir.ref must visibly identify its Rust semantic origin"
+    );
+    assert!(
+        MirRefOp::new(build(&mut ctx, erased_ty.into(), false, None))
+            .verify(&ctx)
+            .is_err(),
+        "mir.ref is an explicit pointer-creation boundary, not generic Erased storage"
+    );
+    assert!(
+        MirRefOp::new(build(
+            &mut ctx,
+            shared_ty.into(),
+            false,
+            Some(MirPointerKindAuthorityAttr::RawAddress),
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "RawAddress cannot manufacture SharedRef"
+    );
+    assert!(
+        MirRefOp::new(build(
+            &mut ctx,
+            unique_ty.into(),
+            true,
+            Some(MirPointerKindAuthorityAttr::StaticAddress),
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "constant/static materialization cannot manufacture uniqueness"
+    );
+    assert!(
+        MirRefOp::new(build(
+            &mut ctx,
+            unique_ty.into(),
+            false,
+            Some(MirPointerKindAuthorityAttr::Reborrow),
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "reference kind must agree with the operation's mutability"
+    );
+    assert!(
+        MirRefOp::new(build(
+            &mut ctx,
+            global_shared_ty.into(),
+            false,
+            Some(MirPointerKindAuthorityAttr::Reborrow),
+        ))
+        .verify(&ctx)
+        .is_err(),
+        "mir.ref materializes generic stack storage"
+    );
+}
diff --git a/crates/dialect-mir/tests/ops_test/scalars_and_funcs.rs b/crates/dialect-mir/tests/ops_test/scalars_and_funcs.rs
new file mode 100644
index 0000000000..15be9832ef
--- /dev/null
+++ b/crates/dialect-mir/tests/ops_test/scalars_and_funcs.rs
@@ -0,0 +1,447 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::{
+    attributes::MirCastKindAttr,
+    ops::{
+        MirAddOp, MirAssignOp, MirCallOp, MirCastOp, MirCheckedAddOp, MirCmpOp, MirConstantOp,
+        MirDivOp, MirEqOp, MirFuncOp, MirGeOp, MirGtOp, MirLeOp, MirLtOp, MirMulOp, MirNeOp,
+        MirNegOp, MirNotOp, MirRemOp, MirSubOp,
+    },
+    types::{EnumVariant, MirEnumType, MirTupleType},
+};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::{
+        attributes::{IntegerAttr, StringAttr, TypeAttr},
+        types::{FP32Type, FunctionType, IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::Context,
+    op::Op,
+    operation::Operation,
+    utils::apint::APInt,
+};
+use std::num::NonZeroUsize;
+
+#[test]
+fn test_mir_arithmetic_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), i32_ty.into()]);
+    let lhs = block.deref(&ctx).get_argument(0);
+
+    let check_bin_op = |opid: (
+        fn(pliron::context::Ptr<pliron::operation::Operation>) -> pliron::op::OpObj,
+        std::any::TypeId,
+    ),
+                        name: &str| {
+        let mut context = Context::new();
+        dialect_mir::register(&mut context);
+        let ty = IntegerType::get(&context, 32, Signedness::Signed);
+        let blk = BasicBlock::new(&mut context, None, vec![ty.into(), ty.into()]);
+        let l = blk.deref(&context).get_argument(0);
+        let r = blk.deref(&context).get_argument(1);
+
+        let op = Operation::new(&mut context, opid, vec![ty.into()], vec![l, r], vec![], 0);
+        assert!(op.verify(&context).is_ok(), "Valid {}", name);
+
+        let f32_t = FP32Type::get(&context);
+        let blk2 = BasicBlock::new(&mut context, None, vec![f32_t.into()]);
+        let f32_val = blk2.deref(&context).get_argument(0);
+
+        let op_bad = Operation::new(
+            &mut context,
+            opid,
+            vec![ty.into()],
+            vec![l, f32_val],
+            vec![],
+            0,
+        );
+        assert!(op_bad.verify(&context).is_err(), "Type mismatch {}", name);
+    };
+
+    check_bin_op(MirAddOp::get_concrete_op_info(), "Add");
+    check_bin_op(MirSubOp::get_concrete_op_info(), "Sub");
+    check_bin_op(MirMulOp::get_concrete_op_info(), "Mul");
+    check_bin_op(MirDivOp::get_concrete_op_info(), "Div");
+    check_bin_op(MirRemOp::get_concrete_op_info(), "Rem");
+
+    let op_neg = Operation::new(
+        &mut ctx,
+        MirNegOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![lhs],
+        vec![],
+        0,
+    );
+    assert!(op_neg.verify(&ctx).is_ok(), "Valid Neg");
+
+    let f32_ty = FP32Type::get(&ctx);
+    let op_neg_bad = Operation::new(
+        &mut ctx,
+        MirNegOp::get_concrete_op_info(),
+        vec![f32_ty.into()],
+        vec![lhs],
+        vec![],
+        0,
+    );
+    assert!(op_neg_bad.verify(&ctx).is_err(), "Neg type mismatch");
+
+    let op_not = Operation::new(
+        &mut ctx,
+        MirNotOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![lhs],
+        vec![],
+        0,
+    );
+    assert!(op_not.verify(&ctx).is_ok(), "Valid Not");
+}
+
+#[test]
+fn test_mir_misc_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signed);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+
+    // 1. MirConstantOp
+    let i32_signless = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let width = NonZeroUsize::new(32).unwrap();
+    let apint = APInt::from_u32(42, width);
+    let int_attr = IntegerAttr::new(i32_signless, apint);
+
+    let const_op_ptr = Operation::new(
+        &mut ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![i32_signless.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let const_op = MirConstantOp::new(const_op_ptr);
+    const_op.set_attr_value(&ctx, int_attr);
+    assert!(const_op.verify(&ctx).is_ok(), "Valid Constant");
+
+    // Mismatch type
+    let i64_signless = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let i64_width = NonZeroUsize::new(64).unwrap();
+    let i64_attr = IntegerAttr::new(i64_signless, APInt::from_u64(42, i64_width));
+    const_op.set_attr_value(&ctx, i64_attr);
+    assert!(const_op.verify(&ctx).is_err(), "Constant type mismatch");
+
+    // 2. MirCastOp
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let arg = block.deref(&ctx).get_argument(0);
+
+    let cast_op = Operation::new(
+        &mut ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![arg],
+        vec![],
+        0,
+    );
+    MirCastOp::new(cast_op).set_attr_cast_kind(&ctx, MirCastKindAttr::IntToInt);
+    assert!(MirCastOp::new(cast_op).verify(&ctx).is_ok(), "Valid Cast");
+
+    // 3. MirCheckedAddOp
+    let tuple_ty = MirTupleType::get(&mut ctx, vec![i32_ty.into(), i1_ty.into()]);
+    let block2 = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), i32_ty.into()]);
+    let lhs = block2.deref(&ctx).get_argument(0);
+    let rhs = block2.deref(&ctx).get_argument(1);
+
+    let checked_add = Operation::new(
+        &mut ctx,
+        MirCheckedAddOp::get_concrete_op_info(),
+        vec![tuple_ty.into()],
+        vec![lhs, rhs],
+        vec![],
+        0,
+    );
+    assert!(
+        MirCheckedAddOp::new(checked_add).verify(&ctx).is_ok(),
+        "Valid CheckedAdd"
+    );
+
+    // Invalid result type (not tuple)
+    let checked_add_bad = Operation::new(
+        &mut ctx,
+        MirCheckedAddOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![lhs, rhs],
+        vec![],
+        0,
+    );
+    assert!(
+        MirCheckedAddOp::new(checked_add_bad).verify(&ctx).is_err(),
+        "CheckedAdd bad result"
+    );
+}
+
+#[test]
+fn test_mir_comparison_verify() {
+    let check_cmp = |opid: (
+        fn(pliron::context::Ptr<pliron::operation::Operation>) -> pliron::op::OpObj,
+        std::any::TypeId,
+    ),
+                     name: &str| {
+        let mut context = Context::new();
+        dialect_mir::register(&mut context);
+        let ty = IntegerType::get(&context, 32, Signedness::Signed);
+        let res_ty = IntegerType::get(&context, 1, Signedness::Signless);
+        let blk = BasicBlock::new(&mut context, None, vec![ty.into(), ty.into()]);
+        let l = blk.deref(&context).get_argument(0);
+        let r = blk.deref(&context).get_argument(1);
+
+        let op = Operation::new(
+            &mut context,
+            opid,
+            vec![res_ty.into()],
+            vec![l, r],
+            vec![],
+            0,
+        );
+        assert!(op.verify(&context).is_ok(), "Valid {}", name);
+
+        // Invalid operand types
+        let f32_ty = FP32Type::get(&context);
+        let blk2 = BasicBlock::new(&mut context, None, vec![f32_ty.into()]);
+        let f32_val = blk2.deref(&context).get_argument(0);
+        let op_bad = Operation::new(
+            &mut context,
+            opid,
+            vec![res_ty.into()],
+            vec![l, f32_val],
+            vec![],
+            0,
+        );
+        assert!(op_bad.verify(&context).is_err(), "Type mismatch {}", name);
+
+        // Invalid result type
+        let op_bad_res = Operation::new(
+            &mut context,
+            opid,
+            vec![ty.into()], // i32 result instead of i1
+            vec![l, r],
+            vec![],
+            0,
+        );
+        assert!(
+            op_bad_res.verify(&context).is_err(),
+            "Result type mismatch {}",
+            name
+        );
+    };
+
+    check_cmp(MirEqOp::get_concrete_op_info(), "Eq");
+    check_cmp(MirNeOp::get_concrete_op_info(), "Ne");
+    check_cmp(MirLtOp::get_concrete_op_info(), "Lt");
+    check_cmp(MirLeOp::get_concrete_op_info(), "Le");
+    check_cmp(MirGtOp::get_concrete_op_info(), "Gt");
+    check_cmp(MirGeOp::get_concrete_op_info(), "Ge");
+
+    let mut context = Context::new();
+    dialect_mir::register(&mut context);
+    let i8_ty = IntegerType::get(&context, 8, Signedness::Signed);
+    let i32_ty = IntegerType::get(&context, 32, Signedness::Signed);
+    let unit = |name: &str| EnumVariant::unit(name.to_string());
+    let ordering_ty = MirEnumType::get(
+        &mut context,
+        "Ordering".to_string(),
+        i8_ty.into(),
+        vec![255, 0, 1],
+        vec![unit("Less"), unit("Equal"), unit("Greater")],
+    );
+    let blk = BasicBlock::new(&mut context, None, vec![i32_ty.into(), i32_ty.into()]);
+    let lhs = blk.deref(&context).get_argument(0);
+    let rhs = blk.deref(&context).get_argument(1);
+    let two_variant_ty = MirEnumType::get(
+        &mut context,
+        "Two".to_string(),
+        i8_ty.into(),
+        vec![0, 1],
+        vec![unit("A"), unit("B")],
+    );
+    // Payload variants disqualify the Ordering shape.
+    let payload_ty = MirEnumType::get(
+        &mut context,
+        "ThreeWithPayload".to_string(),
+        i8_ty.into(),
+        vec![0, 1, 2],
+        vec![
+            unit("A"),
+            EnumVariant::new("B".to_string(), vec![i32_ty.into()]),
+            unit("C"),
+        ],
+    );
+    let mut check_cmp_result = |result_ty, valid| {
+        let op = Operation::new(
+            &mut context,
+            MirCmpOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![lhs, rhs],
+            vec![],
+            0,
+        );
+        assert_eq!(op.verify(&context).is_ok(), valid);
+    };
+    check_cmp_result(ordering_ty.into(), true);
+    check_cmp_result(i32_ty.into(), false);
+    check_cmp_result(two_variant_ty.into(), false);
+    check_cmp_result(payload_ty.into(), false);
+
+    // Float operands are rejected: rustc never emits BinOp::Cmp on floats.
+    let f32_ty = FP32Type::get(&context);
+    let fblk = BasicBlock::new(&mut context, None, vec![f32_ty.into(), f32_ty.into()]);
+    let flhs = fblk.deref(&context).get_argument(0);
+    let frhs = fblk.deref(&context).get_argument(1);
+    let float_cmp = Operation::new(
+        &mut context,
+        MirCmpOp::get_concrete_op_info(),
+        vec![ordering_ty.into()],
+        vec![flhs, frhs],
+        vec![],
+        0,
+    );
+    assert!(
+        float_cmp.verify(&context).is_err(),
+        "float mir.cmp must be rejected"
+    );
+}
+
+#[test]
+fn test_mir_func_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let func_ty = FunctionType::get(&ctx, vec![i32_ty.into()], vec![]);
+    let func_ty_attr = TypeAttr::new(func_ty.into());
+
+    // Valid Function
+    let op_ptr = Operation::new(
+        &mut ctx,
+        MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let mir_func = MirFuncOp::new(&mut ctx, op_ptr, func_ty_attr.clone());
+
+    // Add entry block with correct argument
+    let region = mir_func.get_operation().deref(&ctx).get_region(0);
+    let entry_block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    entry_block.insert_at_front(region, &ctx);
+
+    assert!(mir_func.verify(&ctx).is_ok(), "Valid MirFuncOp");
+
+    // Invalid: Argument count mismatch
+    let op_ptr2 = Operation::new(
+        &mut ctx,
+        MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let mir_func2 = MirFuncOp::new(&mut ctx, op_ptr2, func_ty_attr.clone());
+    let region2 = mir_func2.get_operation().deref(&ctx).get_region(0);
+    // Block with 0 args
+    let entry_block2 = BasicBlock::new(&mut ctx, None, vec![]);
+    entry_block2.insert_at_front(region2, &ctx);
+
+    assert!(
+        mir_func2.verify(&ctx).is_err(),
+        "MirFuncOp argument count mismatch"
+    );
+
+    // Invalid: Argument type mismatch
+    let op_ptr3 = Operation::new(
+        &mut ctx,
+        MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let mir_func3 = MirFuncOp::new(&mut ctx, op_ptr3, func_ty_attr);
+    let region3 = mir_func3.get_operation().deref(&ctx).get_region(0);
+    let f32_ty = FP32Type::get(&ctx);
+    let entry_block3 = BasicBlock::new(&mut ctx, None, vec![f32_ty.into()]);
+    entry_block3.insert_at_front(region3, &ctx);
+
+    assert!(
+        mir_func3.verify(&ctx).is_err(),
+        "MirFuncOp argument type mismatch"
+    );
+}
+
+#[test]
+fn test_mir_assign_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let val = block.deref(&ctx).get_argument(0);
+
+    let op = Operation::new(
+        &mut ctx,
+        MirAssignOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirAssignOp::new(op).verify(&ctx).is_ok(),
+        "Valid MirAssignOp"
+    );
+
+    let f32_ty = FP32Type::get(&ctx);
+    let op_bad = Operation::new(
+        &mut ctx,
+        MirAssignOp::get_concrete_op_info(),
+        vec![f32_ty.into()],
+        vec![val],
+        vec![],
+        0,
+    );
+    assert!(
+        MirAssignOp::new(op_bad).verify(&ctx).is_err(),
+        "MirAssignOp type mismatch"
+    );
+}
+
+#[test]
+fn test_mir_call_verify() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+
+    let op = Operation::new(
+        &mut ctx,
+        MirCallOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    let call_op = MirCallOp::new(op);
+
+    // Missing attribute
+    assert!(call_op.verify(&ctx).is_err(), "MirCallOp missing attribute");
+
+    // With attribute
+    let name = StringAttr::new("my_func".to_string());
+    call_op.set_attr_callee(&ctx, name);
+    assert!(call_op.verify(&ctx).is_ok(), "Valid MirCallOp");
+}
diff --git a/crates/dialect-nvvm/tests/ops_test.rs b/crates/dialect-nvvm/tests/ops_test.rs
deleted file mode 100644
index d8a7099fcf..0000000000
--- a/crates/dialect-nvvm/tests/ops_test.rs
+++ /dev/null
@@ -1,5575 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// Tests build kinded fixture types directly; production minting lives in
-// mir-importer's facts.rs (see the workspace clippy.toml disallowed-methods).
-#![allow(clippy::disallowed_methods)]
-
-use dialect_mir::{
-    attributes::MirPointerKindAuthorityAttr,
-    types::{MirPointerKind, MirPtrType, MirTupleType, address_space},
-};
-use dialect_nvvm::ops::{
-    ActiveMaskOp, AssertFailOp, AtomicOrdering, AtomicRmwKind, AtomicScope, BarWarpSyncOp,
-    Barrier0Op, ClcQueryIsCanceledOp, ClusterBarrierModeAttr, ClusterBarrierOp, CpAsyncCa4Op,
-    CpAsyncCaZfill4Op, CpAsyncMbarrierArriveNoIncOp, CpAsyncMbarrierArriveNoIncSharedOp,
-    CpAsyncMbarrierArriveOp, CpAsyncMbarrierArriveSharedOp, CpAsyncWaitGroupOp,
-    CvtaGenericToSharedOffsetOp, Dp2aS32Op, Dp2aU32Op, Dp4aS32Op, Dp4aU32Op, ElectSyncOp,
-    FmaBf16x2Op, InlinePtxOp, LdmatrixElementAttr, LdmatrixLayoutAttr, LdmatrixMultiplicityAttr,
-    LdmatrixOp, LdmatrixShapeAttr, LdmatrixStateSpaceAttr, LdmatrixX1Op, LdmatrixX1TransOp,
-    LdmatrixX2Op, LdmatrixX2TransOp, LdmatrixX4Op, LdmatrixX4TransOp, MatchAllSyncI32Op,
-    MatchAllSyncI64Op, MatchAnySyncI32Op, MatchAnySyncI64Op, MbarrierArriveSharedOp,
-    MbarrierInitSharedOp, MbarrierInvalSharedOp, MbarrierTestWaitSharedOp, MmaM8N8K4F64Op,
-    MmaM16N8K8F32Tf32Op, MmaM16N8K16F32Bf16Op, MmaM16N8K16F32F16Op, MmaM16N8K32S32S8Op,
-    MovmatrixTransB16Op, NvvmAtomAddBf16x2Op, NvvmAtomAddF16x2Op, NvvmAtomicCmpxchgOp,
-    NvvmAtomicLoadOp, NvvmAtomicRmwOp, NvvmAtomicStoreOp, PackedAtomicAddOp,
-    PackedAtomicAtomicityAttr, PackedAtomicFormatAttr, PackedAtomicOrderingAttr,
-    PackedAtomicRoundingAttr, PackedAtomicScopeAttr, PackedAtomicStateSpaceAttr,
-    PackedAtomicSubnormalAttr, ReadPtxSregClusterIdxOp, ReadPtxSregDynamicSmemSizeOp,
-    ReadPtxSregGridIdOp, ReadPtxSregLaneIdOp, ReadPtxSregLanemaskEqOp, ReadPtxSregLanemaskGeOp,
-    ReadPtxSregLanemaskGtOp, ReadPtxSregLanemaskLeOp, ReadPtxSregLanemaskLtOp,
-    ReadPtxSregNclusterIdOp, ReadPtxSregNsmIdOp, ReadPtxSregNwarpIdOp, ReadPtxSregSmIdOp,
-    ReadPtxSregTidXOp, ReadPtxSregTotalSmemSizeOp, ReadPtxSregWarpIdOp, ReduxSyncAddOp,
-    ReduxSyncAndOp, ReduxSyncFmaxAbsNanOp, ReduxSyncFmaxAbsOp, ReduxSyncFmaxNanOp, ReduxSyncFmaxOp,
-    ReduxSyncFminAbsNanOp, ReduxSyncFminAbsOp, ReduxSyncFminNanOp, ReduxSyncFminOp, ReduxSyncMaxOp,
-    ReduxSyncMinOp, ReduxSyncOrOp, ReduxSyncUmaxOp, ReduxSyncUminOp, ReduxSyncXorOp,
-    RegisterMmaAccumulatorAttr, RegisterMmaElementAttr, RegisterMmaLayoutAttr, RegisterMmaOp,
-    RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr,
-    ScalarArithmeticFormatAttr, ScalarArithmeticOp, ScalarArithmeticOperationAttr,
-    ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr,
-    ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr,
-    ShflSyncBflyI64Op, ShflSyncDownI64Op, ShflSyncIdxI64Op, ShflSyncUpI64Op,
-    SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr,
-    SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr,
-    StmatrixM8n8X4Op, Tcgen05AllocOp, Tcgen05CommitMulticastCg2Op, Tcgen05Ld16x32bx2X1RawOp,
-    Tcgen05Ld16x256bPureOp, Tcgen05MmaF16Op, ThreadfenceBlockOp, ThreadfenceOp,
-    ThreadfenceSystemOp, VoteSyncAllOp, VoteSyncAnyOp, VoteSyncBallotOp, VoteSyncUniOp, VprintfOp,
-    WgmmaMakeSmemDescOp, WgmmaMaxPendingAttr, WgmmaMmaGroupM64N64K16F32Bf16Op,
-    WgmmaMmaGroupValuesM64N64K8F32Tf32Op, WgmmaMmaGroupValuesM64N64K16F32Bf16Op,
-    WgmmaMmaGroupValuesM64N64K16F32F16Op, WgmmaMmaGroupValuesM64N128K16F32Bf16Op,
-    WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op, WgmmaMmaLoopValuesM64N64K16F32Bf16Op,
-    WgmmaMmaLoopValuesM64N64K16F32F16Op, WgmmaMmaM64N64K8F32Tf32Op, WgmmaMmaM64N64K16F32Bf16Op,
-    WgmmaMmaM64N64K16F32F16Op, WgmmaMmaM64N128K16F32Bf16Op,
-    WgmmaMmaPipelineValuesM64N64K16F32Bf16Op,
-};
-
-#[test]
-fn handwritten_ops_match_reviewed_allowlist() {
-    use std::{fs, path::Path};
-
-    let ops_dir = Path::new(env!("CARGO_MANIFEST_DIR")).join("src/ops");
-    let mut found = Vec::new();
-
-    for entry in fs::read_dir(&ops_dir).expect("read top-level NVVM ops directory") {
-        let path = entry.expect("read NVVM ops entry").path();
-        if path.extension().and_then(|extension| extension.to_str()) != Some("rs") {
-            continue;
-        }
-
-        let source = fs::read_to_string(&path).expect("read handwritten NVVM ops source");
-        let file = path
-            .file_name()
-            .and_then(|name| name.to_str())
-            .expect("NVVM ops file name");
-
-        for (marker, _) in source.match_indices("#[pliron_op(") {
-            let declaration = source[marker..]
-                .lines()
-                .find_map(|line| line.trim().strip_prefix("pub struct "))
-                .expect("pliron_op must be followed by a public struct");
-            let name = declaration
-                .split(|character: char| !character.is_ascii_alphanumeric() && character != '_')
-                .next()
-                .expect("NVVM op struct name");
-            found.push((file.to_owned(), name.to_owned()));
-        }
-    }
-
-    let mut expected = [
-        ("asm.rs", "InlinePtxOp"),
-        ("atomic.rs", "NvvmAtomicLoadOp"),
-        ("atomic.rs", "NvvmAtomicStoreOp"),
-        ("atomic.rs", "NvvmAtomicFenceOp"),
-        ("atomic.rs", "NvvmAtomicRmwOp"),
-        ("atomic.rs", "NvvmAtomicCmpxchgOp"),
-        ("cluster.rs", "ReadPtxSregClusterIdxOp"),
-        ("cluster.rs", "ReadPtxSregNclusterIdOp"),
-        ("debug.rs", "AssertFailOp"),
-        ("debug.rs", "VprintfOp"),
-        ("grid.rs", "GridSyncOp"),
-        ("memory.rs", "CvtaGenericToSharedOffsetOp"),
-        ("wgmma.rs", "WgmmaMakeSmemDescOp"),
-        ("wgmma.rs", "WgmmaMmaM64N64K16F32Bf16Op"),
-        ("wgmma.rs", "WgmmaMmaM64N128K16F32Bf16Op"),
-        ("wgmma.rs", "WgmmaMmaM64N64K16F32F16Op"),
-        ("wgmma.rs", "WgmmaMmaM64N64K8F32Tf32Op"),
-        ("wgmma.rs", "WgmmaMmaGroupM64N64K16F32Bf16Op"),
-        ("wgmma.rs", "WgmmaMmaGroupValuesM64N64K16F32Bf16Op"),
-        ("wgmma.rs", "WgmmaMmaGroupValuesM64N128K16F32Bf16Op"),
-        ("wgmma.rs", "WgmmaMmaGroupValuesM64N64K16F32F16Op"),
-        ("wgmma.rs", "WgmmaMmaGroupValuesM64N64K8F32Tf32Op"),
-        ("wgmma.rs", "WgmmaMmaLoopValuesM64N64K16F32Bf16Op"),
-        ("wgmma.rs", "WgmmaMmaLoopValuesM64N64K16F32F16Op"),
-        ("wgmma.rs", "WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op"),
-        ("wgmma.rs", "WgmmaMmaPipelineValuesM64N64K16F32Bf16Op"),
-    ];
-    expected.sort_unstable();
-    found.sort_unstable();
-
-    assert_eq!(
-        found,
-        expected.map(|(file, op)| (file.to_owned(), op.to_owned())),
-        "top-level handwritten NVVM ops changed; generate leaf ops or review this allowlist"
-    );
-}
-
-#[test]
-fn cluster_grid_compatibility_ops_keep_names_and_i32_shape() {
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::common_traits::Verify;
-    use pliron::context::Context;
-    use pliron::op::Op;
-    use pliron::operation::Operation;
-
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-    assert_eq!(
-        ReadPtxSregClusterIdxOp::get_opid_static().to_string(),
-        "nvvm.read_ptx_sreg_cluster_idx"
-    );
-    assert_eq!(
-        ReadPtxSregNclusterIdOp::get_opid_static().to_string(),
-        "nvvm.read_ptx_sreg_nclusterid"
-    );
-
-    let i32_type = IntegerType::get(&ctx, 32, Signedness::Signless);
-    for op_info in [
-        ReadPtxSregClusterIdxOp::get_concrete_op_info(),
-        ReadPtxSregNclusterIdOp::get_concrete_op_info(),
-    ] {
-        let op = Operation::new(&mut ctx, op_info, vec![i32_type.into()], vec![], vec![], 0);
-        assert!(op.deref(&ctx).verify(&ctx).is_ok());
-    }
-}
-
-#[test]
-fn mapa_shared_cluster_requires_and_preserves_raw_pointer_kind() {
-    use dialect_mir::types::{MirPointerKind, MirPtrType, address_space};
-    use dialect_nvvm::ops::MapaSharedClusterOp;
-    use pliron::{
-        basic_block::BasicBlock,
-        builtin::types::{IntegerType, Signedness},
-        common_traits::Verify,
-        context::Context,
-        op::Op,
-        operation::Operation,
-    };
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let raw_const_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), false, MirPointerKind::RawConst);
-    let raw_mut_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
-    let erased_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            raw_const_ty.into(),
-            raw_mut_ty.into(),
-            erased_ty.into(),
-            i32_ty.into(),
-        ],
-    );
-    let raw_const = block.deref(&ctx).get_argument(0);
-    let raw_mut = block.deref(&ctx).get_argument(1);
-    let erased = block.deref(&ctx).get_argument(2);
-    let rank = block.deref(&ctx).get_argument(3);
-
-    for (source, expected_kind) in [
-        (raw_const, MirPointerKind::RawConst),
-        (raw_mut, MirPointerKind::RawMut),
-    ] {
-        let operation = MapaSharedClusterOp::build(&mut ctx, source, rank);
-        let result_ty = operation.deref(&ctx).get_result(0).get_type(&ctx);
-        let result_ty = result_ty.deref(&ctx);
-        let result_ptr = result_ty
-            .downcast_ref::<MirPtrType>()
-            .expect("mapa result must be a MIR pointer");
-        assert_eq!(result_ptr.pointer_kind(), expected_kind);
-        assert_eq!(result_ptr.address_space(), address_space::CLUSTER_SHARED);
-        assert!(MapaSharedClusterOp::new(operation).verify(&ctx).is_ok());
-    }
-
-    let erased_result = MirPtrType::get_with_kind(
-        &mut ctx,
-        i32_ty.into(),
-        true,
-        address_space::CLUSTER_SHARED,
-        MirPointerKind::Erased,
-    );
-    let erasing = Operation::new(
-        &mut ctx,
-        MapaSharedClusterOp::get_concrete_op_info(),
-        vec![erased_result.into()],
-        vec![raw_mut, rank],
-        vec![],
-        0,
-    );
-    assert!(
-        MapaSharedClusterOp::new(erasing).verify(&ctx).is_err(),
-        "cluster address mapping must preserve the source raw-pointer kind"
-    );
-
-    let erased_source = MapaSharedClusterOp::build(&mut ctx, erased, rank);
-    assert!(
-        MapaSharedClusterOp::new(erased_source)
-            .verify(&ctx)
-            .is_err(),
-        "an Erased data/function carrier cannot enter the raw-pointer intrinsic ABI"
-    );
-
-    let invented_unique = MirPtrType::get_with_kind(
-        &mut ctx,
-        i32_ty.into(),
-        true,
-        address_space::CLUSTER_SHARED,
-        MirPointerKind::UniqueRef,
-    );
-    let laundering = Operation::new(
-        &mut ctx,
-        MapaSharedClusterOp::get_concrete_op_info(),
-        vec![invented_unique.into()],
-        vec![raw_mut, rank],
-        vec![],
-        0,
-    );
-    assert!(
-        MapaSharedClusterOp::new(laundering).verify(&ctx).is_err(),
-        "cluster address mapping must not turn RawMut into UniqueRef"
-    );
-
-    let invented_shared = MirPtrType::get_with_kind(
-        &mut ctx,
-        i32_ty.into(),
-        false,
-        address_space::CLUSTER_SHARED,
-        MirPointerKind::SharedRef,
-    );
-    let laundering = Operation::new(
-        &mut ctx,
-        MapaSharedClusterOp::get_concrete_op_info(),
-        vec![invented_shared.into()],
-        vec![raw_const, rank],
-        vec![],
-        0,
-    );
-    assert!(
-        MapaSharedClusterOp::new(laundering).verify(&ctx).is_err(),
-        "cluster address mapping must not turn RawConst into SharedRef"
-    );
-}
-
-#[test]
-fn generated_cluster_barrier_requires_one_closed_mode_and_no_values() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    for mode in [
-        ClusterBarrierModeAttr::Arrive,
-        ClusterBarrierModeAttr::ArriveAligned,
-        ClusterBarrierModeAttr::ArriveRelaxed,
-        ClusterBarrierModeAttr::ArriveRelaxedAligned,
-        ClusterBarrierModeAttr::Wait,
-        ClusterBarrierModeAttr::WaitAligned,
-    ] {
-        let op = ClusterBarrierOp::build(&mut ctx, mode);
-        assert!(verify_op(&ClusterBarrierOp::new(op), &ctx).is_ok());
-    }
-
-    let missing_mode = Operation::new(
-        &mut ctx,
-        ClusterBarrierOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ClusterBarrierOp::new(missing_mode), &ctx).is_err());
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let wrong_shape = Operation::new(
-        &mut ctx,
-        ClusterBarrierOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    ClusterBarrierOp::new(wrong_shape)
-        .set_attr_nvvm_cluster_barrier_mode(&ctx, ClusterBarrierModeAttr::Wait);
-    assert!(verify_op(&ClusterBarrierOp::new(wrong_shape), &ctx).is_err());
-}
-
-#[test]
-fn generated_scalar_conversion_accepts_only_reviewed_f32_to_i32_variants() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let f32_ty = FP32Type::get(&ctx);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let block = BasicBlock::new(&mut ctx, None, vec![f32_ty.into(), i32_ty.into()]);
-    let f32_value = block.deref(&ctx).get_argument(0);
-    let i32_value = block.deref(&ctx).get_argument(1);
-
-    for (rounding, saturation) in [
-        (
-            ScalarConversionRoundingAttr::NearestAway,
-            ScalarConversionSaturationAttr::None,
-        ),
-        (
-            ScalarConversionRoundingAttr::NearestAway,
-            ScalarConversionSaturationAttr::Satfinite,
-        ),
-        (
-            ScalarConversionRoundingAttr::NearestEven,
-            ScalarConversionSaturationAttr::None,
-        ),
-        (
-            ScalarConversionRoundingAttr::NearestEven,
-            ScalarConversionSaturationAttr::Relu,
-        ),
-        (
-            ScalarConversionRoundingAttr::NearestEven,
-            ScalarConversionSaturationAttr::Satfinite,
-        ),
-        (
-            ScalarConversionRoundingAttr::NearestEven,
-            ScalarConversionSaturationAttr::ReluSatfinite,
-        ),
-        (
-            ScalarConversionRoundingAttr::TowardZero,
-            ScalarConversionSaturationAttr::None,
-        ),
-        (
-            ScalarConversionRoundingAttr::TowardZero,
-            ScalarConversionSaturationAttr::Relu,
-        ),
-        (
-            ScalarConversionRoundingAttr::TowardZero,
-            ScalarConversionSaturationAttr::Satfinite,
-        ),
-        (
-            ScalarConversionRoundingAttr::TowardZero,
-            ScalarConversionSaturationAttr::ReluSatfinite,
-        ),
-    ] {
-        let op = ScalarConversionOp::build(&mut ctx, f32_value, rounding, saturation);
-        assert!(verify_op(&ScalarConversionOp::new(op), &ctx).is_ok());
-    }
-
-    let invalid_variant = ScalarConversionOp::build(
-        &mut ctx,
-        f32_value,
-        ScalarConversionRoundingAttr::NearestAway,
-        ScalarConversionSaturationAttr::Relu,
-    );
-    assert!(verify_op(&ScalarConversionOp::new(invalid_variant), &ctx).is_err());
-
-    let wrong_operand = Operation::new(
-        &mut ctx,
-        ScalarConversionOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![i32_value],
-        vec![],
-        0,
-    );
-    let wrong_operand = ScalarConversionOp::new(wrong_operand);
-    wrong_operand
-        .set_attr_nvvm_scalar_conversion_rounding(&ctx, ScalarConversionRoundingAttr::NearestEven);
-    wrong_operand
-        .set_attr_nvvm_scalar_conversion_saturation(&ctx, ScalarConversionSaturationAttr::None);
-    assert!(verify_op(&wrong_operand, &ctx).is_err());
-
-    let wrong_result = Operation::new(
-        &mut ctx,
-        ScalarConversionOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![f32_value],
-        vec![],
-        0,
-    );
-    let wrong_result = ScalarConversionOp::new(wrong_result);
-    wrong_result
-        .set_attr_nvvm_scalar_conversion_rounding(&ctx, ScalarConversionRoundingAttr::TowardZero);
-    wrong_result
-        .set_attr_nvvm_scalar_conversion_saturation(&ctx, ScalarConversionSaturationAttr::None);
-    assert!(verify_op(&wrong_result, &ctx).is_err());
-}
-
-#[test]
-fn generated_scalar_arithmetic_accepts_only_admitted_shapes_and_types() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let f32_ty = FP32Type::get(&ctx);
-    let f64_ty = FP64Type::get(&ctx);
-    let block = BasicBlock::new(&mut ctx, None, vec![f32_ty.into(), f64_ty.into()]);
-    let f32_value = block.deref(&ctx).get_argument(0);
-    let f64_value = block.deref(&ctx).get_argument(1);
-
-    let valid_f32 = ScalarArithmeticOp::build(
-        &mut ctx,
-        vec![f32_value, f32_value],
-        ScalarArithmeticFormatAttr::F32,
-        ScalarArithmeticOperationAttr::Mul,
-        ScalarArithmeticRoundingAttr::Rn,
-        ScalarArithmeticSubnormalAttr::Preserve,
-        ScalarArithmeticSaturationAttr::None,
-    );
-    assert!(verify_op(&ScalarArithmeticOp::new(valid_f32), &ctx).is_ok());
-
-    let valid_f64 = ScalarArithmeticOp::build(
-        &mut ctx,
-        vec![f64_value, f64_value, f64_value],
-        ScalarArithmeticFormatAttr::F64,
-        ScalarArithmeticOperationAttr::Fma,
-        ScalarArithmeticRoundingAttr::Rz,
-        ScalarArithmeticSubnormalAttr::Preserve,
-        ScalarArithmeticSaturationAttr::None,
-    );
-    assert!(verify_op(&ScalarArithmeticOp::new(valid_f64), &ctx).is_ok());
-
-    let valid_add = ScalarArithmeticOp::build(
-        &mut ctx,
-        vec![f32_value, f32_value],
-        ScalarArithmeticFormatAttr::F32,
-        ScalarArithmeticOperationAttr::Add,
-        ScalarArithmeticRoundingAttr::Rp,
-        ScalarArithmeticSubnormalAttr::Ftz,
-        ScalarArithmeticSaturationAttr::Sat,
-    );
-    assert!(verify_op(&ScalarArithmeticOp::new(valid_add), &ctx).is_ok());
-
-    let f64_ftz = ScalarArithmeticOp::build(
-        &mut ctx,
-        vec![f64_value, f64_value],
-        ScalarArithmeticFormatAttr::F64,
-        ScalarArithmeticOperationAttr::Mul,
-        ScalarArithmeticRoundingAttr::Rn,
-        ScalarArithmeticSubnormalAttr::Ftz,
-        ScalarArithmeticSaturationAttr::None,
-    );
-    assert!(verify_op(&ScalarArithmeticOp::new(f64_ftz), &ctx).is_err());
-
-    let wrong_arity = ScalarArithmeticOp::build(
-        &mut ctx,
-        vec![f32_value, f32_value],
-        ScalarArithmeticFormatAttr::F32,
-        ScalarArithmeticOperationAttr::Fma,
-        ScalarArithmeticRoundingAttr::Rn,
-        ScalarArithmeticSubnormalAttr::Preserve,
-        ScalarArithmeticSaturationAttr::None,
-    );
-    assert!(verify_op(&ScalarArithmeticOp::new(wrong_arity), &ctx).is_err());
-
-    let wrong_type = ScalarArithmeticOp::build(
-        &mut ctx,
-        vec![f32_value, f64_value],
-        ScalarArithmeticFormatAttr::F32,
-        ScalarArithmeticOperationAttr::Mul,
-        ScalarArithmeticRoundingAttr::Rn,
-        ScalarArithmeticSubnormalAttr::Preserve,
-        ScalarArithmeticSaturationAttr::None,
-    );
-    assert!(verify_op(&ScalarArithmeticOp::new(wrong_type), &ctx).is_err());
-
-    let missing_attrs = Operation::new(
-        &mut ctx,
-        ScalarArithmeticOp::get_concrete_op_info(),
-        vec![f32_ty.into()],
-        vec![f32_value, f32_value],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ScalarArithmeticOp::new(missing_attrs), &ctx).is_err());
-}
-
-#[test]
-fn test_generated_cp_async_accepts_pointer_shapes_and_both_constant_kinds() {
-    use dialect_mir::ops::MirConstantOp;
-    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let dst_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
-    let src_ty = MirPtrType::get(&mut ctx, u8_ty.into(), true, address_space::GLOBAL);
-    let wrong_dst_ty = MirPtrType::get(&mut ctx, u8_ty.into(), true, address_space::GLOBAL);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            dst_ty.into(),
-            src_ty.into(),
-            wrong_dst_ty.into(),
-            u32_ty.into(),
-        ],
-    );
-    let dst = block.deref(&ctx).get_argument(0);
-    let src = block.deref(&ctx).get_argument(1);
-    let wrong_dst = block.deref(&ctx).get_argument(2);
-    let dynamic = block.deref(&ctx).get_argument(3);
-
-    let copy = CpAsyncCa4Op::build(&mut ctx, dst, src);
-    assert!(verify_op(&CpAsyncCa4Op::new(copy), &ctx).is_ok());
-    let zfill = CpAsyncCaZfill4Op::build(&mut ctx, dst, src, dynamic);
-    assert!(verify_op(&CpAsyncCaZfill4Op::new(zfill), &ctx).is_ok());
-    let wrong_space = CpAsyncCa4Op::build(&mut ctx, wrong_dst, src);
-    assert!(verify_op(&CpAsyncCa4Op::new(wrong_space), &ctx).is_err());
-
-    let value = IntegerAttr::new(u32_ty, APInt::from_u32(0, NonZeroUsize::new(32).unwrap()));
-    let builtin = ConstantOp::new(&mut ctx, value.clone().into());
-    let builtin_value = builtin.get_operation().deref(&ctx).get_result(0);
-    let builtin_wait = CpAsyncWaitGroupOp::build(&mut ctx, builtin_value);
-    assert!(verify_op(&CpAsyncWaitGroupOp::new(builtin_wait), &ctx).is_ok());
-
-    let mir_constant = Operation::new(
-        &mut ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    MirConstantOp::new(mir_constant).set_attr_value(&ctx, value);
-    let mir_value = mir_constant.deref(&ctx).get_result(0);
-    let mir_wait = CpAsyncWaitGroupOp::build(&mut ctx, mir_value);
-    assert!(verify_op(&CpAsyncWaitGroupOp::new(mir_wait), &ctx).is_ok());
-
-    let dynamic_wait = CpAsyncWaitGroupOp::build(&mut ctx, dynamic);
-    assert!(verify_op(&CpAsyncWaitGroupOp::new(dynamic_wait), &ctx).is_err());
-}
-
-#[test]
-fn generated_tcgen05_verifies_carriers_and_half_split_constants() {
-    use dialect_mir::ops::MirConstantOp;
-    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let i16_ty = IntegerType::get(&ctx, 16, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let f32_ty = FP32Type::get(&ctx);
-    let pointer_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            pointer_ty.into(),
-            i1_ty.into(),
-            i16_ty.into(),
-            i32_ty.into(),
-            i64_ty.into(),
-            f32_ty.into(),
-        ],
-    );
-    let pointer = block.deref(&ctx).get_argument(0);
-    let predicate = block.deref(&ctx).get_argument(1);
-    let mask = block.deref(&ctx).get_argument(2);
-    let address = block.deref(&ctx).get_argument(3);
-    let dynamic_offset = block.deref(&ctx).get_argument(4);
-
-    let offset_attr = IntegerAttr::new(i64_ty, APInt::from_i64(16, NonZeroUsize::new(64).unwrap()));
-    let builtin_offset = ConstantOp::new(&mut ctx, offset_attr.clone().into())
-        .get_operation()
-        .deref(&ctx)
-        .get_result(0);
-    let mir_constant = Operation::new(
-        &mut ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    MirConstantOp::new(mir_constant).set_attr_value(&ctx, offset_attr);
-    let mir_offset = mir_constant.deref(&ctx).get_result(0);
-
-    for offset in [builtin_offset, mir_offset] {
-        let load = Operation::new(
-            &mut ctx,
-            Tcgen05Ld16x32bx2X1RawOp::get_concrete_op_info(),
-            vec![i32_ty.into()],
-            vec![address, offset],
-            vec![],
-            0,
-        );
-        assert!(verify_op(&Tcgen05Ld16x32bx2X1RawOp::new(load), &ctx).is_ok());
-    }
-
-    let dynamic = Operation::new(
-        &mut ctx,
-        Tcgen05Ld16x32bx2X1RawOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![address, dynamic_offset],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&Tcgen05Ld16x32bx2X1RawOp::new(dynamic), &ctx).is_err());
-
-    let wrong_offset_type = Operation::new(
-        &mut ctx,
-        Tcgen05Ld16x32bx2X1RawOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![address, address],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&Tcgen05Ld16x32bx2X1RawOp::new(wrong_offset_type), &ctx).is_err());
-
-    let wrong_result_type = Operation::new(
-        &mut ctx,
-        Tcgen05Ld16x32bx2X1RawOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![address, builtin_offset],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&Tcgen05Ld16x32bx2X1RawOp::new(wrong_result_type), &ctx).is_err());
-
-    let alloc = Operation::new(
-        &mut ctx,
-        Tcgen05AllocOp::get_concrete_op_info(),
-        vec![],
-        vec![pointer, address],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&Tcgen05AllocOp::new(alloc), &ctx).is_ok());
-
-    let multicast = Operation::new(
-        &mut ctx,
-        Tcgen05CommitMulticastCg2Op::get_concrete_op_info(),
-        vec![],
-        vec![pointer, mask],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&Tcgen05CommitMulticastCg2Op::new(multicast), &ctx).is_ok());
-
-    let mma = Operation::new(
-        &mut ctx,
-        Tcgen05MmaF16Op::get_concrete_op_info(),
-        vec![],
-        vec![address, dynamic_offset, dynamic_offset, address, predicate],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&Tcgen05MmaF16Op::new(mma), &ctx).is_ok());
-
-    let pure_load = Operation::new(
-        &mut ctx,
-        Tcgen05Ld16x256bPureOp::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        vec![address],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&Tcgen05Ld16x256bPureOp::new(pure_load), &ctx).is_ok());
-}
-
-#[test]
-fn generated_cp_async_mbarrier_requires_mutable_generic_or_shared_u64() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let generic_u64 = MirPtrType::get_generic(&mut ctx, u64_ty.into(), true);
-    let shared_u64 = MirPtrType::get_shared(&mut ctx, u64_ty.into(), true);
-    let global_u64 = MirPtrType::get_global(&mut ctx, u64_ty.into(), true);
-    let immutable_u64 = MirPtrType::get_generic(&mut ctx, u64_ty.into(), false);
-    let generic_u32 = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            generic_u64.into(),
-            shared_u64.into(),
-            global_u64.into(),
-            immutable_u64.into(),
-            generic_u32.into(),
-            u64_ty.into(),
-        ],
-    );
-    let generic = block.deref(&ctx).get_argument(0);
-    let shared = block.deref(&ctx).get_argument(1);
-    let global = block.deref(&ctx).get_argument(2);
-    let immutable = block.deref(&ctx).get_argument(3);
-    let wrong_pointee = block.deref(&ctx).get_argument(4);
-    let scalar = block.deref(&ctx).get_argument(5);
-
-    macro_rules! check_bridge {
-        ($op:ty) => {{
-            for barrier in [generic, shared] {
-                let valid = <$op>::build(&mut ctx, barrier);
-                assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
-            }
-            for barrier in [global, immutable, wrong_pointee, scalar] {
-                let invalid = <$op>::build(&mut ctx, barrier);
-                assert!(verify_op(&<$op>::new(invalid), &ctx).is_err());
-            }
-            let wrong_shape = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![u64_ty.into()],
-                vec![generic],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(wrong_shape), &ctx).is_err());
-        }};
-    }
-
-    check_bridge!(CpAsyncMbarrierArriveOp);
-    check_bridge!(CpAsyncMbarrierArriveSharedOp);
-    check_bridge!(CpAsyncMbarrierArriveNoIncOp);
-    check_bridge!(CpAsyncMbarrierArriveNoIncSharedOp);
-}
-
-#[test]
-fn generated_mbarrier_builders_and_verifiers_are_closed_over_their_shapes() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let u1_ty = IntegerType::get(&ctx, 1, Signedness::Unsigned);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let generic_ptr = MirPtrType::get_generic(&mut ctx, u64_ty.into(), false);
-    let shared_ptr = MirPtrType::get_shared(&mut ctx, u64_ty.into(), false);
-    let global_ptr = MirPtrType::get_global(&mut ctx, u64_ty.into(), false);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            generic_ptr.into(),
-            shared_ptr.into(),
-            global_ptr.into(),
-            i32_ty.into(),
-            u32_ty.into(),
-            u64_ty.into(),
-        ],
-    );
-    let generic = block.deref(&ctx).get_argument(0);
-    let shared = block.deref(&ctx).get_argument(1);
-    let global = block.deref(&ctx).get_argument(2);
-    let signless_i32 = block.deref(&ctx).get_argument(3);
-    let count = block.deref(&ctx).get_argument(4);
-    let token = block.deref(&ctx).get_argument(5);
-
-    for barrier in [generic, shared] {
-        let init = MbarrierInitSharedOp::build(&mut ctx, barrier, count);
-        assert!(MbarrierInitSharedOp::new(init).verify(&ctx).is_ok());
-        let arrive = MbarrierArriveSharedOp::build(&mut ctx, barrier);
-        assert!(MbarrierArriveSharedOp::new(arrive).verify(&ctx).is_ok());
-        let test_wait = MbarrierTestWaitSharedOp::build(&mut ctx, barrier, token);
-        assert!(
-            MbarrierTestWaitSharedOp::new(test_wait)
-                .verify(&ctx)
-                .is_ok()
-        );
-        let inval = MbarrierInvalSharedOp::build(&mut ctx, barrier);
-        assert!(MbarrierInvalSharedOp::new(inval).verify(&ctx).is_ok());
-    }
-
-    for barrier in [token, global] {
-        let inval = MbarrierInvalSharedOp::build(&mut ctx, barrier);
-        assert!(MbarrierInvalSharedOp::new(inval).verify(&ctx).is_err());
-    }
-
-    let bad_count = MbarrierInitSharedOp::build(&mut ctx, shared, signless_i32);
-    assert!(MbarrierInitSharedOp::new(bad_count).verify(&ctx).is_err());
-    let bad_arrive_result = Operation::new(
-        &mut ctx,
-        MbarrierArriveSharedOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![shared],
-        vec![],
-        0,
-    );
-    assert!(
-        MbarrierArriveSharedOp::new(bad_arrive_result)
-            .verify(&ctx)
-            .is_err()
-    );
-    let bad_token = MbarrierTestWaitSharedOp::build(&mut ctx, shared, count);
-    assert!(
-        MbarrierTestWaitSharedOp::new(bad_token)
-            .verify(&ctx)
-            .is_err()
-    );
-    let bad_predicate = Operation::new(
-        &mut ctx,
-        MbarrierTestWaitSharedOp::get_concrete_op_info(),
-        vec![u1_ty.into()],
-        vec![shared, token],
-        vec![],
-        0,
-    );
-    assert!(
-        MbarrierTestWaitSharedOp::new(bad_predicate)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let missing_operands = Operation::new(
-        &mut ctx,
-        MbarrierInitSharedOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(
-        MbarrierInitSharedOp::new(missing_operands)
-            .verify(&ctx)
-            .is_err()
-    );
-}
-use pliron::{
-    basic_block::BasicBlock,
-    builtin::types::{FP32Type, FP64Type, IntegerType, Signedness},
-    common_traits::Verify,
-    context::Context,
-    op::{Op, verify_op},
-    operation::Operation,
-    r#type::Typed,
-};
-
-#[test]
-fn test_mma_m8n8k4_f64_requires_four_f64_operands_and_two_f64_results() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let f64_ty = FP64Type::get(&ctx);
-    let f32_ty = FP32Type::get(&ctx);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            f64_ty.into(),
-            f64_ty.into(),
-            f64_ty.into(),
-            f64_ty.into(),
-            f32_ty.into(),
-        ],
-    );
-    let f64_operands = (0..4)
-        .map(|index| block.deref(&ctx).get_argument(index))
-        .collect::<Vec<_>>();
-    let f32_value = block.deref(&ctx).get_argument(4);
-
-    let valid = Operation::new(
-        &mut ctx,
-        MmaM8N8K4F64Op::get_concrete_op_info(),
-        vec![f64_ty.into(), f64_ty.into()],
-        f64_operands.clone(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM8N8K4F64Op::new(valid), &ctx).is_ok());
-
-    let mut bad_operands = f64_operands.clone();
-    bad_operands[2] = f32_value;
-    let invalid_operand = Operation::new(
-        &mut ctx,
-        MmaM8N8K4F64Op::get_concrete_op_info(),
-        vec![f64_ty.into(), f64_ty.into()],
-        bad_operands,
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM8N8K4F64Op::new(invalid_operand), &ctx).is_err());
-
-    let invalid_result = Operation::new(
-        &mut ctx,
-        MmaM8N8K4F64Op::get_concrete_op_info(),
-        vec![f64_ty.into(), f32_ty.into()],
-        f64_operands,
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM8N8K4F64Op::new(invalid_result), &ctx).is_err());
-}
-
-#[test]
-fn test_movmatrix_requires_one_i32_operand_and_result() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let f32_ty = FP32Type::get(&ctx);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![i32_ty.into(), i64_ty.into(), f32_ty.into()],
-    );
-    let i32_value = block.deref(&ctx).get_argument(0);
-    let i64_value = block.deref(&ctx).get_argument(1);
-    let f32_value = block.deref(&ctx).get_argument(2);
-
-    let valid = Operation::new(
-        &mut ctx,
-        MovmatrixTransB16Op::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![i32_value],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MovmatrixTransB16Op::new(valid), &ctx).is_ok());
-
-    for (operand, result_type) in [
-        (i64_value, i32_ty.into()),
-        (f32_value, i32_ty.into()),
-        (i32_value, i64_ty.into()),
-        (i32_value, f32_ty.into()),
-    ] {
-        let invalid = Operation::new(
-            &mut ctx,
-            MovmatrixTransB16Op::get_concrete_op_info(),
-            vec![result_type],
-            vec![operand],
-            vec![],
-            0,
-        );
-        assert!(
-            verify_op(&MovmatrixTransB16Op::new(invalid), &ctx).is_err(),
-            "movmatrix must reject non-i32 carriers"
-        );
-    }
-}
-
-fn make_ldmatrix_x2(
-    ctx: &mut Context,
-    pointer: pliron::value::Value,
-    result_types: Vec<pliron::r#type::TypeHandle>,
-) -> LdmatrixOp {
-    let operation = Operation::new(
-        ctx,
-        LdmatrixOp::get_concrete_op_info(),
-        result_types,
-        vec![pointer],
-        vec![],
-        0,
-    );
-    let ldmatrix = LdmatrixOp::new(operation);
-    ldmatrix.set_attr_nvvm_ldmatrix_shape(ctx, LdmatrixShapeAttr::M8n8);
-    ldmatrix.set_attr_nvvm_ldmatrix_multiplicity(ctx, LdmatrixMultiplicityAttr::X2);
-    ldmatrix.set_attr_nvvm_ldmatrix_layout(ctx, LdmatrixLayoutAttr::Normal);
-    ldmatrix.set_attr_nvvm_ldmatrix_element(ctx, LdmatrixElementAttr::B16);
-    ldmatrix.set_attr_nvvm_ldmatrix_state_space(ctx, LdmatrixStateSpaceAttr::Shared);
-    ldmatrix
-}
-
-#[test]
-fn test_ldmatrix_accepts_only_generic_or_shared_u32_pointers() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let u16_ty = IntegerType::get(&ctx, 16, Signedness::Unsigned);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let pointer_types = [
-        MirPtrType::get_generic(&mut ctx, u32_ty.into(), false),
-        MirPtrType::get_shared(&mut ctx, u32_ty.into(), false),
-        MirPtrType::get_global(&mut ctx, u32_ty.into(), false),
-        MirPtrType::get_constant(&mut ctx, u32_ty.into(), false),
-        MirPtrType::get(&mut ctx, u32_ty.into(), false, address_space::LOCAL),
-        MirPtrType::get_generic(&mut ctx, u16_ty.into(), false),
-    ];
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        pointer_types
-            .iter()
-            .map(|pointer| (*pointer).into())
-            .collect(),
-    );
-
-    for index in 0..pointer_types.len() {
-        let pointer = block.deref(&ctx).get_argument(index);
-        let operation = make_ldmatrix_x2(&mut ctx, pointer, vec![u32_ty.into(), u32_ty.into()]);
-        let verified = verify_op(&operation, &ctx);
-        if index < 2 {
-            assert!(verified.is_ok(), "pointer case {index} should be accepted");
-        } else {
-            assert!(verified.is_err(), "pointer case {index} should be rejected");
-        }
-    }
-}
-
-#[test]
-fn generated_ldmatrix_verifier_rejects_zero_or_two_operands_without_panicking() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let pointer_ty = MirPtrType::get_shared(&mut ctx, u32_ty.into(), false);
-    let block = BasicBlock::new(&mut ctx, None, vec![pointer_ty.into(), pointer_ty.into()]);
-    let pointer0 = block.deref(&ctx).get_argument(0);
-    let pointer1 = block.deref(&ctx).get_argument(1);
-
-    let zero = Operation::new(
-        &mut ctx,
-        LdmatrixOp::get_concrete_op_info(),
-        vec![u32_ty.into(); 4],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(LdmatrixOp::new(zero).verify(&ctx).is_err());
-
-    let two = Operation::new(
-        &mut ctx,
-        LdmatrixOp::get_concrete_op_info(),
-        vec![u32_ty.into(); 4],
-        vec![pointer0, pointer1],
-        vec![],
-        0,
-    );
-    assert!(LdmatrixOp::new(two).verify(&ctx).is_err());
-
-    let valid = LdmatrixOp::build(
-        &mut ctx,
-        pointer0,
-        LdmatrixShapeAttr::M8n8,
-        LdmatrixMultiplicityAttr::X4,
-        LdmatrixLayoutAttr::Normal,
-        LdmatrixElementAttr::B16,
-        LdmatrixStateSpaceAttr::Shared,
-    );
-    assert!(LdmatrixOp::new(valid).verify(&ctx).is_ok());
-}
-
-#[test]
-fn blackwell_ldmatrix_verifier_accepts_only_reviewed_shapes() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let shared_u8 = MirPtrType::get_shared(&mut ctx, u8_ty.into(), false);
-    let generic_u8 = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
-    let global_u8 = MirPtrType::get_global(&mut ctx, u8_ty.into(), false);
-    let shared_u32 = MirPtrType::get_shared(&mut ctx, u32_ty.into(), false);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            shared_u8.into(),
-            generic_u8.into(),
-            global_u8.into(),
-            shared_u32.into(),
-        ],
-    );
-    let shared_pointer = block.deref(&ctx).get_argument(0);
-
-    for pointer_index in [0, 1] {
-        let pointer = block.deref(&ctx).get_argument(pointer_index);
-        for (shape, multiplicity, layout, element, result_count) in [
-            (
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8,
-                2,
-            ),
-            (
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8x16B4x16P64,
-                2,
-            ),
-            (
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8x16B6x16P32,
-                2,
-            ),
-            (
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8,
-                4,
-            ),
-            (
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8x16B4x16P64,
-                4,
-            ),
-            (
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8x16B6x16P32,
-                4,
-            ),
-            (
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B4x16P64,
-                1,
-            ),
-            (
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B6x16P32,
-                1,
-            ),
-            (
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B4x16P64,
-                2,
-            ),
-            (
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B6x16P32,
-                2,
-            ),
-            (
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X4,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B4x16P64,
-                4,
-            ),
-            (
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X4,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B6x16P32,
-                4,
-            ),
-        ] {
-            let op = LdmatrixOp::build(
-                &mut ctx,
-                pointer,
-                shape,
-                multiplicity,
-                layout,
-                element,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            assert_eq!(op.deref(&ctx).get_num_results(), result_count);
-            assert!(LdmatrixOp::new(op).verify(&ctx).is_ok());
-        }
-    }
-
-    for (shape, multiplicity, layout, element) in [
-        (
-            LdmatrixShapeAttr::M16n16,
-            LdmatrixMultiplicityAttr::X4,
-            LdmatrixLayoutAttr::Transposed,
-            LdmatrixElementAttr::B8,
-        ),
-        (
-            LdmatrixShapeAttr::M16n16,
-            LdmatrixMultiplicityAttr::X1,
-            LdmatrixLayoutAttr::Normal,
-            LdmatrixElementAttr::B8,
-        ),
-        (
-            LdmatrixShapeAttr::M8n16,
-            LdmatrixMultiplicityAttr::X1,
-            LdmatrixLayoutAttr::Transposed,
-            LdmatrixElementAttr::B8x16B4x16P64,
-        ),
-        (
-            LdmatrixShapeAttr::M8n16,
-            LdmatrixMultiplicityAttr::X1,
-            LdmatrixLayoutAttr::Normal,
-            LdmatrixElementAttr::B8,
-        ),
-    ] {
-        let op = LdmatrixOp::build(
-            &mut ctx,
-            shared_pointer,
-            shape,
-            multiplicity,
-            layout,
-            element,
-            LdmatrixStateSpaceAttr::Shared,
-        );
-        assert!(LdmatrixOp::new(op).verify(&ctx).is_err());
-    }
-
-    for pointer_index in [2, 3] {
-        let pointer = block.deref(&ctx).get_argument(pointer_index);
-        let op = LdmatrixOp::build(
-            &mut ctx,
-            pointer,
-            LdmatrixShapeAttr::M16n16,
-            LdmatrixMultiplicityAttr::X1,
-            LdmatrixLayoutAttr::Transposed,
-            LdmatrixElementAttr::B8,
-            LdmatrixStateSpaceAttr::Shared,
-        );
-        assert!(LdmatrixOp::new(op).verify(&ctx).is_err());
-    }
-}
-
-#[test]
-fn classic_ldmatrix_compatibility_ops_keep_names_and_register_shapes() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let pointer_ty = MirPtrType::get_shared(&mut ctx, u32_ty.into(), false);
-    let block = BasicBlock::new(&mut ctx, None, vec![pointer_ty.into()]);
-    let pointer = block.deref(&ctx).get_argument(0);
-
-    macro_rules! check_compat {
-        ($op:ty, $name:literal, $results:literal) => {{
-            assert_eq!(<$op>::get_opid_static().to_string(), $name);
-            let valid = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![u32_ty.into(); $results],
-                vec![pointer],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
-
-            let wrong_shape = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![u32_ty.into(); $results + 1],
-                vec![pointer],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(wrong_shape), &ctx).is_err());
-        }};
-    }
-
-    check_compat!(LdmatrixX1Op, "nvvm.ldmatrix_x1", 1);
-    check_compat!(LdmatrixX1TransOp, "nvvm.ldmatrix_x1_trans", 1);
-    check_compat!(LdmatrixX2Op, "nvvm.ldmatrix_x2", 2);
-    check_compat!(LdmatrixX2TransOp, "nvvm.ldmatrix_x2_trans", 2);
-    check_compat!(LdmatrixX4Op, "nvvm.ldmatrix_x4", 4);
-    check_compat!(LdmatrixX4TransOp, "nvvm.ldmatrix_x4_trans", 4);
-}
-
-#[test]
-fn test_mma_m16n8k16_bf16_verifies_exact_register_signature() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let f32_ty = FP32Type::get(&ctx);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![f32_ty.into(), i32_ty.into(), i64_ty.into()],
-    );
-    let f32_value = block.deref(&ctx).get_argument(0);
-    let i32_value = block.deref(&ctx).get_argument(1);
-    let i64_value = block.deref(&ctx).get_argument(2);
-
-    let valid_operands = (0..4)
-        .map(|_| f32_value)
-        .chain((0..6).map(|_| i32_value))
-        .collect();
-    let valid = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        valid_operands,
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32Bf16Op::new(valid), &ctx).is_ok());
-
-    let bad_c_operands = (0..4)
-        .map(|index| if index == 0 { i32_value } else { f32_value })
-        .chain((0..6).map(|_| i32_value))
-        .collect();
-    let bad_c = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        bad_c_operands,
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32Bf16Op::new(bad_c), &ctx).is_err());
-
-    let bad_a_operands = (0..4)
-        .map(|_| f32_value)
-        .chain((0..6).map(|index| if index == 0 { i64_value } else { i32_value }))
-        .collect();
-    let bad_a = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        bad_a_operands,
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32Bf16Op::new(bad_a), &ctx).is_err());
-
-    let bad_result = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(), f32_ty.into(), f32_ty.into(), i32_ty.into()],
-        (0..4)
-            .map(|_| f32_value)
-            .chain((0..6).map(|_| i32_value))
-            .collect(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32Bf16Op::new(bad_result), &ctx).is_err());
-
-    let bad_arity = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        (0..4)
-            .map(|_| f32_value)
-            .chain((0..5).map(|_| i32_value))
-            .collect(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32Bf16Op::new(bad_arity), &ctx).is_err());
-}
-
-#[test]
-fn test_mma_m16n8k16_f16_verifies_exact_register_signature() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let f32_ty = FP32Type::get(&ctx);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![f32_ty.into(), i32_ty.into(), i64_ty.into()],
-    );
-    let f32_value = block.deref(&ctx).get_argument(0);
-    let i32_value = block.deref(&ctx).get_argument(1);
-    let i64_value = block.deref(&ctx).get_argument(2);
-
-    let operands = || {
-        (0..4)
-            .map(|_| f32_value)
-            .chain((0..6).map(|_| i32_value))
-            .collect()
-    };
-    let valid = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32F16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        operands(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32F16Op::new(valid), &ctx).is_ok());
-
-    let bad_c_operands = (0..4)
-        .map(|index| if index == 0 { i32_value } else { f32_value })
-        .chain((0..6).map(|_| i32_value))
-        .collect();
-    let bad_c = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32F16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        bad_c_operands,
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32F16Op::new(bad_c), &ctx).is_err());
-
-    let bad_packed_operands = (0..4)
-        .map(|_| f32_value)
-        .chain((0..6).map(|index| if index == 0 { i64_value } else { i32_value }))
-        .collect();
-    let bad_packed = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32F16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        bad_packed_operands,
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32F16Op::new(bad_packed), &ctx).is_err());
-
-    let bad_result_type = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32F16Op::get_concrete_op_info(),
-        vec![f32_ty.into(), f32_ty.into(), f32_ty.into(), i32_ty.into()],
-        operands(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32F16Op::new(bad_result_type), &ctx).is_err());
-
-    let bad_operand_arity = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32F16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        (0..4)
-            .map(|_| f32_value)
-            .chain((0..5).map(|_| i32_value))
-            .collect(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32F16Op::new(bad_operand_arity), &ctx).is_err());
-
-    let bad_result_arity = Operation::new(
-        &mut ctx,
-        MmaM16N8K16F32F16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 3],
-        operands(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K16F32F16Op::new(bad_result_arity), &ctx).is_err());
-}
-
-#[test]
-fn test_mma_m16n8k8_tf32_verifies_exact_register_signature() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let f32_ty = FP32Type::get(&ctx);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![f32_ty.into(), i32_ty.into(), i64_ty.into()],
-    );
-    let f32_value = block.deref(&ctx).get_argument(0);
-    let i32_value = block.deref(&ctx).get_argument(1);
-    let i64_value = block.deref(&ctx).get_argument(2);
-
-    let operands = || {
-        (0..4)
-            .map(|_| f32_value)
-            .chain((0..6).map(|_| i32_value))
-            .collect()
-    };
-    let valid = Operation::new(
-        &mut ctx,
-        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        operands(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(valid), &ctx).is_ok());
-
-    let bad_c_operands = (0..4)
-        .map(|index| if index == 0 { i32_value } else { f32_value })
-        .chain((0..6).map(|_| i32_value))
-        .collect();
-    let bad_c = Operation::new(
-        &mut ctx,
-        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        bad_c_operands,
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(bad_c), &ctx).is_err());
-
-    let bad_packed_operands = (0..4)
-        .map(|_| f32_value)
-        .chain((0..6).map(|index| if index == 0 { i64_value } else { i32_value }))
-        .collect();
-    let bad_packed = Operation::new(
-        &mut ctx,
-        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        bad_packed_operands,
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(bad_packed), &ctx).is_err());
-
-    let bad_result_type = Operation::new(
-        &mut ctx,
-        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
-        vec![f32_ty.into(), f32_ty.into(), f32_ty.into(), i32_ty.into()],
-        operands(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(bad_result_type), &ctx).is_err());
-
-    let bad_operand_arity = Operation::new(
-        &mut ctx,
-        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        (0..4)
-            .map(|_| f32_value)
-            .chain((0..5).map(|_| i32_value))
-            .collect(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(bad_operand_arity), &ctx).is_err());
-
-    let bad_result_arity = Operation::new(
-        &mut ctx,
-        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 3],
-        operands(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(bad_result_arity), &ctx).is_err());
-}
-
-#[test]
-fn test_mma_m16n8k32_s8_verifies_exact_register_signature() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let f32_ty = FP32Type::get(&ctx);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![i32_ty.into(), i64_ty.into(), f32_ty.into()],
-    );
-    let i32_value = block.deref(&ctx).get_argument(0);
-    let i64_value = block.deref(&ctx).get_argument(1);
-    let f32_value = block.deref(&ctx).get_argument(2);
-    let valid_operands = vec![i32_value; 10];
-
-    let valid = Operation::new(
-        &mut ctx,
-        MmaM16N8K32S32S8Op::get_concrete_op_info(),
-        vec![i32_ty.into(); 4],
-        valid_operands.clone(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K32S32S8Op::new(valid), &ctx).is_ok());
-
-    for bad_value in [i64_value, f32_value] {
-        let mut bad_operands = valid_operands.clone();
-        bad_operands[4] = bad_value;
-        let invalid = Operation::new(
-            &mut ctx,
-            MmaM16N8K32S32S8Op::get_concrete_op_info(),
-            vec![i32_ty.into(); 4],
-            bad_operands,
-            vec![],
-            0,
-        );
-        assert!(
-            verify_op(&MmaM16N8K32S32S8Op::new(invalid), &ctx).is_err(),
-            "MMA must reject non-i32 register operands"
-        );
-    }
-
-    for bad_results in [
-        vec![i32_ty.into(), i32_ty.into(), i32_ty.into(), i64_ty.into()],
-        vec![i32_ty.into(), i32_ty.into(), i32_ty.into(), f32_ty.into()],
-        vec![i32_ty.into(); 3],
-    ] {
-        let invalid = Operation::new(
-            &mut ctx,
-            MmaM16N8K32S32S8Op::get_concrete_op_info(),
-            bad_results,
-            valid_operands.clone(),
-            vec![],
-            0,
-        );
-        assert!(
-            verify_op(&MmaM16N8K32S32S8Op::new(invalid), &ctx).is_err(),
-            "MMA must reject the wrong result register signature"
-        );
-    }
-
-    let invalid_arity = Operation::new(
-        &mut ctx,
-        MmaM16N8K32S32S8Op::get_concrete_op_info(),
-        vec![i32_ty.into(); 4],
-        vec![i32_value; 9],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&MmaM16N8K32S32S8Op::new(invalid_arity), &ctx).is_err());
-}
-
-#[test]
-fn generated_register_mma_verifier_rejects_crossed_variants_and_carriers() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    macro_rules! set_variant {
-        ($op:expr, $shape:expr, $acc:expr, $a:expr, $b:expr, $overflow:expr) => {{
-            $op.set_attr_nvvm_register_mma_shape(&ctx, $shape);
-            $op.set_attr_nvvm_register_mma_accumulator(&ctx, $acc);
-            $op.set_attr_nvvm_register_mma_a_element(&ctx, $a);
-            $op.set_attr_nvvm_register_mma_b_element(&ctx, $b);
-            $op.set_attr_nvvm_register_mma_a_layout(&ctx, RegisterMmaLayoutAttr::Row);
-            $op.set_attr_nvvm_register_mma_b_layout(&ctx, RegisterMmaLayoutAttr::Col);
-            $op.set_attr_nvvm_register_mma_overflow(&ctx, $overflow);
-        }};
-    }
-
-    let f32_ty = FP32Type::get(&ctx);
-    let f64_ty = FP64Type::get(&ctx);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![f32_ty.into(), f64_ty.into(), i32_ty.into(), u32_ty.into()],
-    );
-    let f32_value = block.deref(&ctx).get_argument(0);
-    let f64_value = block.deref(&ctx).get_argument(1);
-    let i32_value = block.deref(&ctx).get_argument(2);
-    let u32_value = block.deref(&ctx).get_argument(3);
-
-    let bf16_operation = Operation::new(
-        &mut ctx,
-        RegisterMmaOp::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        [vec![f32_value; 4], vec![u32_value; 6]].concat(),
-        vec![],
-        0,
-    );
-    let bf16 = RegisterMmaOp::new(bf16_operation);
-    set_variant!(
-        bf16,
-        RegisterMmaShapeAttr::M16n8k16,
-        RegisterMmaAccumulatorAttr::F32,
-        RegisterMmaElementAttr::Bf16,
-        RegisterMmaElementAttr::Bf16,
-        RegisterMmaOverflowAttr::NotApplicable
-    );
-    assert!(bf16.get_attr_nvvm_register_mma_operation(&ctx).is_none());
-    assert!(verify_op(&bf16, &ctx).is_ok());
-    bf16.set_attr_nvvm_register_mma_b_element(&ctx, RegisterMmaElementAttr::F16);
-    assert!(verify_op(&bf16, &ctx).is_err());
-
-    let f64_operation = Operation::new(
-        &mut ctx,
-        RegisterMmaOp::get_concrete_op_info(),
-        vec![f64_ty.into(); 2],
-        vec![f64_value; 4],
-        vec![],
-        0,
-    );
-    let f64_mma = RegisterMmaOp::new(f64_operation);
-    set_variant!(
-        f64_mma,
-        RegisterMmaShapeAttr::M8n8k4,
-        RegisterMmaAccumulatorAttr::F64,
-        RegisterMmaElementAttr::F64,
-        RegisterMmaElementAttr::F64,
-        RegisterMmaOverflowAttr::NotApplicable
-    );
-    assert!(verify_op(&f64_mma, &ctx).is_ok());
-
-    let int_operands = [vec![i32_value; 4], vec![u32_value; 6]].concat();
-    let int_operation = Operation::new(
-        &mut ctx,
-        RegisterMmaOp::get_concrete_op_info(),
-        vec![i32_ty.into(); 4],
-        int_operands.clone(),
-        vec![],
-        0,
-    );
-    let int_mma = RegisterMmaOp::new(int_operation);
-    set_variant!(
-        int_mma,
-        RegisterMmaShapeAttr::M16n8k32,
-        RegisterMmaAccumulatorAttr::S32,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaOverflowAttr::Wrapping
-    );
-    assert!(verify_op(&int_mma, &ctx).is_ok());
-
-    let wrong_signedness = Operation::new(
-        &mut ctx,
-        RegisterMmaOp::get_concrete_op_info(),
-        vec![signless_i32_ty.into(); 4],
-        int_operands,
-        vec![],
-        0,
-    );
-    let wrong_signedness = RegisterMmaOp::new(wrong_signedness);
-    set_variant!(
-        wrong_signedness,
-        RegisterMmaShapeAttr::M16n8k32,
-        RegisterMmaAccumulatorAttr::S32,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaOverflowAttr::Wrapping
-    );
-    assert!(verify_op(&wrong_signedness, &ctx).is_err());
-
-    let missing_attributes = Operation::new(
-        &mut ctx,
-        RegisterMmaOp::get_concrete_op_info(),
-        vec![f64_ty.into(); 2],
-        vec![f64_value; 4],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&RegisterMmaOp::new(missing_attributes), &ctx).is_err());
-}
-
-#[test]
-fn generated_register_mma_verifies_dense_integer_families() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![i32_ty.into(), u32_ty.into(), signless_i32_ty.into()],
-    );
-    let i32_value = block.deref(&ctx).get_argument(0);
-    let u32_value = block.deref(&ctx).get_argument(1);
-
-    macro_rules! int_mma {
-        ($shape:expr, $a:expr, $b:expr, $overflow:expr, $operands:expr, $results:expr) => {{
-            let operation = Operation::new(
-                &mut ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                $results,
-                $operands,
-                vec![],
-                0,
-            );
-            let mma = RegisterMmaOp::new(operation);
-            mma.set_attr_nvvm_register_mma_shape(&ctx, $shape);
-            mma.set_attr_nvvm_register_mma_operation(&ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_accumulator(&ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(&ctx, $a);
-            mma.set_attr_nvvm_register_mma_b_element(&ctx, $b);
-            mma.set_attr_nvvm_register_mma_a_layout(&ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(&ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(&ctx, $overflow);
-            mma
-        }};
-    }
-
-    let mut accepted = 0;
-    for (shape, accumulator_count, operand_count, result_count) in [
-        (RegisterMmaShapeAttr::M8n8k16, 2, 4, 2),
-        (RegisterMmaShapeAttr::M16n8k16, 4, 7, 4),
-        (RegisterMmaShapeAttr::M16n8k32, 4, 10, 4),
-    ] {
-        for (a_element, b_element) in [
-            (RegisterMmaElementAttr::S8, RegisterMmaElementAttr::S8),
-            (RegisterMmaElementAttr::S8, RegisterMmaElementAttr::U8),
-            (RegisterMmaElementAttr::U8, RegisterMmaElementAttr::S8),
-            (RegisterMmaElementAttr::U8, RegisterMmaElementAttr::U8),
-        ] {
-            for overflow in [
-                RegisterMmaOverflowAttr::Wrapping,
-                RegisterMmaOverflowAttr::Satfinite,
-            ] {
-                let operands = [
-                    vec![i32_value; accumulator_count],
-                    vec![u32_value; operand_count - accumulator_count],
-                ]
-                .concat();
-                let mma = int_mma!(
-                    shape.clone(),
-                    a_element.clone(),
-                    b_element.clone(),
-                    overflow.clone(),
-                    operands,
-                    vec![i32_ty.into(); result_count]
-                );
-                assert_eq!(
-                    mma.get_operation().deref(&ctx).get_num_operands(),
-                    operand_count
-                );
-                assert_eq!(
-                    mma.get_operation().deref(&ctx).get_num_results(),
-                    result_count
-                );
-                assert!(
-                    verify_op(&mma, &ctx).is_ok(),
-                    "rejected {shape:?} {a_element:?}x{b_element:?} {overflow:?}"
-                );
-                accepted += 1;
-            }
-        }
-    }
-    assert_eq!(accepted, 24);
-
-    let mut int4_accepted = 0;
-    for (shape, accumulator_count, a_count, b_count, result_count) in [
-        (RegisterMmaShapeAttr::M8n8k32, 2, 1, 1, 2),
-        (RegisterMmaShapeAttr::M16n8k32, 4, 2, 1, 4),
-        (RegisterMmaShapeAttr::M16n8k64, 4, 4, 2, 4),
-    ] {
-        for (a_element, b_element) in [
-            (RegisterMmaElementAttr::S4, RegisterMmaElementAttr::S4),
-            (RegisterMmaElementAttr::S4, RegisterMmaElementAttr::U4),
-            (RegisterMmaElementAttr::U4, RegisterMmaElementAttr::S4),
-            (RegisterMmaElementAttr::U4, RegisterMmaElementAttr::U4),
-        ] {
-            for overflow in [
-                RegisterMmaOverflowAttr::Wrapping,
-                RegisterMmaOverflowAttr::Satfinite,
-            ] {
-                let operands = [
-                    vec![i32_value; accumulator_count],
-                    vec![u32_value; a_count],
-                    vec![u32_value; b_count],
-                ]
-                .concat();
-                let expected_operand_types = [
-                    vec![i32_ty.into(); accumulator_count],
-                    vec![u32_ty.into(); a_count],
-                    vec![u32_ty.into(); b_count],
-                ]
-                .concat();
-                let mma = int_mma!(
-                    shape.clone(),
-                    a_element.clone(),
-                    b_element.clone(),
-                    overflow.clone(),
-                    operands,
-                    vec![i32_ty.into(); result_count]
-                );
-                let operation = mma.get_operation().deref(&ctx);
-                assert_eq!(
-                    operation.get_num_operands(),
-                    accumulator_count + a_count + b_count
-                );
-                assert_eq!(operation.get_num_results(), result_count);
-                assert_eq!(
-                    operation
-                        .operands()
-                        .map(|operand| operand.get_type(&ctx))
-                        .collect::<Vec<_>>(),
-                    expected_operand_types
-                );
-                assert_eq!(
-                    (0..operation.get_num_results())
-                        .map(|index| operation.get_result(index).get_type(&ctx))
-                        .collect::<Vec<_>>(),
-                    vec![i32_ty.into(); result_count]
-                );
-                assert_eq!(
-                    mma.get_attr_nvvm_register_mma_shape(&ctx).as_deref(),
-                    Some(&shape)
-                );
-                assert_eq!(
-                    mma.get_attr_nvvm_register_mma_accumulator(&ctx).as_deref(),
-                    Some(&RegisterMmaAccumulatorAttr::S32)
-                );
-                assert_eq!(
-                    mma.get_attr_nvvm_register_mma_a_element(&ctx).as_deref(),
-                    Some(&a_element)
-                );
-                assert_eq!(
-                    mma.get_attr_nvvm_register_mma_b_element(&ctx).as_deref(),
-                    Some(&b_element)
-                );
-                assert_eq!(
-                    mma.get_attr_nvvm_register_mma_a_layout(&ctx).as_deref(),
-                    Some(&RegisterMmaLayoutAttr::Row)
-                );
-                assert_eq!(
-                    mma.get_attr_nvvm_register_mma_b_layout(&ctx).as_deref(),
-                    Some(&RegisterMmaLayoutAttr::Col)
-                );
-                assert_eq!(
-                    mma.get_attr_nvvm_register_mma_overflow(&ctx).as_deref(),
-                    Some(&overflow)
-                );
-                assert!(
-                    verify_op(&mma, &ctx).is_ok(),
-                    "rejected {shape:?} {a_element:?}x{b_element:?} {overflow:?}"
-                );
-                int4_accepted += 1;
-            }
-        }
-    }
-    assert_eq!(int4_accepted, 24);
-
-    for (shape, accumulator_count, operand_count, result_count) in [
-        (RegisterMmaShapeAttr::M8n8k32, 2, 4, 2),
-        (RegisterMmaShapeAttr::M16n8k32, 4, 7, 4),
-        (RegisterMmaShapeAttr::M16n8k64, 4, 10, 4),
-    ] {
-        for wrong_operand_count in [operand_count - 1, operand_count + 1] {
-            let mma = int_mma!(
-                shape.clone(),
-                RegisterMmaElementAttr::S4,
-                RegisterMmaElementAttr::U4,
-                RegisterMmaOverflowAttr::Wrapping,
-                [
-                    vec![i32_value; accumulator_count],
-                    vec![u32_value; wrong_operand_count - accumulator_count],
-                ]
-                .concat(),
-                vec![i32_ty.into(); result_count]
-            );
-            assert!(verify_op(&mma, &ctx).is_err());
-        }
-
-        for wrong_result_count in [result_count - 1, result_count + 1] {
-            let mma = int_mma!(
-                shape.clone(),
-                RegisterMmaElementAttr::U4,
-                RegisterMmaElementAttr::S4,
-                RegisterMmaOverflowAttr::Satfinite,
-                [
-                    vec![i32_value; accumulator_count],
-                    vec![u32_value; operand_count - accumulator_count],
-                ]
-                .concat(),
-                vec![i32_ty.into(); wrong_result_count]
-            );
-            assert!(verify_op(&mma, &ctx).is_err());
-        }
-    }
-
-    let int4_on_int8_shape = int_mma!(
-        RegisterMmaShapeAttr::M8n8k16,
-        RegisterMmaElementAttr::S4,
-        RegisterMmaElementAttr::U4,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
-        vec![i32_ty.into(); 2]
-    );
-    assert!(verify_op(&int4_on_int8_shape, &ctx).is_err());
-
-    let int8_on_int4_shape = int_mma!(
-        RegisterMmaShapeAttr::M8n8k32,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
-        vec![i32_ty.into(); 2]
-    );
-    assert!(verify_op(&int8_on_int4_shape, &ctx).is_err());
-
-    let crossed_integer_width = int_mma!(
-        RegisterMmaShapeAttr::M16n8k32,
-        RegisterMmaElementAttr::S4,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaOverflowAttr::Satfinite,
-        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&crossed_integer_width, &ctx).is_err());
-
-    let m16k32_int4_with_int8_carriers = int_mma!(
-        RegisterMmaShapeAttr::M16n8k32,
-        RegisterMmaElementAttr::U4,
-        RegisterMmaElementAttr::S4,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 4], vec![u32_value; 6]].concat(),
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&m16k32_int4_with_int8_carriers, &ctx).is_err());
-
-    let m16k32_int8_with_int4_carriers = int_mma!(
-        RegisterMmaShapeAttr::M16n8k32,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaOverflowAttr::Satfinite,
-        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&m16k32_int8_with_int4_carriers, &ctx).is_err());
-
-    let m16k64_int4_with_k32_carriers = int_mma!(
-        RegisterMmaShapeAttr::M16n8k64,
-        RegisterMmaElementAttr::S4,
-        RegisterMmaElementAttr::U4,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&m16k64_int4_with_k32_carriers, &ctx).is_err());
-
-    let m16k32_int4_with_k64_carriers = int_mma!(
-        RegisterMmaShapeAttr::M16n8k32,
-        RegisterMmaElementAttr::U4,
-        RegisterMmaElementAttr::S4,
-        RegisterMmaOverflowAttr::Satfinite,
-        [vec![i32_value; 4], vec![u32_value; 6]].concat(),
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&m16k32_int4_with_k64_carriers, &ctx).is_err());
-
-    let int8_on_m16k64_shape = int_mma!(
-        RegisterMmaShapeAttr::M16n8k64,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 4], vec![u32_value; 6]].concat(),
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&int8_on_m16k64_shape, &ctx).is_err());
-
-    for (shape, accumulator_count, operand_count, result_count) in [
-        (RegisterMmaShapeAttr::M8n8k16, 2, 4, 2),
-        (RegisterMmaShapeAttr::M16n8k16, 4, 7, 4),
-        (RegisterMmaShapeAttr::M16n8k32, 4, 10, 4),
-    ] {
-        for wrong_count in [operand_count - 1, operand_count + 1] {
-            let operands = [
-                vec![i32_value; accumulator_count],
-                vec![u32_value; wrong_count - accumulator_count],
-            ]
-            .concat();
-            let mma = int_mma!(
-                shape.clone(),
-                RegisterMmaElementAttr::S8,
-                RegisterMmaElementAttr::U8,
-                RegisterMmaOverflowAttr::Wrapping,
-                operands,
-                vec![i32_ty.into(); result_count]
-            );
-            assert!(verify_op(&mma, &ctx).is_err());
-        }
-    }
-
-    let m8_wrong_result_signedness = int_mma!(
-        RegisterMmaShapeAttr::M8n8k16,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
-        vec![signless_i32_ty.into(); 2]
-    );
-    assert!(verify_op(&m8_wrong_result_signedness, &ctx).is_err());
-
-    let m8_wrong_accumulator_signedness = int_mma!(
-        RegisterMmaShapeAttr::M8n8k16,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaOverflowAttr::Wrapping,
-        vec![u32_value; 4],
-        vec![i32_ty.into(); 2]
-    );
-    assert!(verify_op(&m8_wrong_accumulator_signedness, &ctx).is_err());
-
-    let m8_wrong_fragment_signedness = int_mma!(
-        RegisterMmaShapeAttr::M8n8k16,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaOverflowAttr::Satfinite,
-        vec![i32_value; 4],
-        vec![i32_ty.into(); 2]
-    );
-    assert!(verify_op(&m8_wrong_fragment_signedness, &ctx).is_err());
-
-    let m8_crossed_element = int_mma!(
-        RegisterMmaShapeAttr::M8n8k16,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::F16,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
-        vec![i32_ty.into(); 2]
-    );
-    assert!(verify_op(&m8_crossed_element, &ctx).is_err());
-
-    let m8_crossed_overflow = int_mma!(
-        RegisterMmaShapeAttr::M8n8k16,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaOverflowAttr::NotApplicable,
-        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
-        vec![i32_ty.into(); 2]
-    );
-    assert!(verify_op(&m8_crossed_overflow, &ctx).is_err());
-
-    let m8_crossed_carrier_shape = int_mma!(
-        RegisterMmaShapeAttr::M8n8k16,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&m8_crossed_carrier_shape, &ctx).is_err());
-
-    let m8_crossed_shape = int_mma!(
-        RegisterMmaShapeAttr::M8n8k4,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
-        vec![i32_ty.into(); 2]
-    );
-    assert!(verify_op(&m8_crossed_shape, &ctx).is_err());
-
-    let wrong_result_signedness = int_mma!(
-        RegisterMmaShapeAttr::M16n8k16,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
-        vec![signless_i32_ty.into(); 4]
-    );
-    assert!(verify_op(&wrong_result_signedness, &ctx).is_err());
-
-    let wrong_accumulator_signedness = int_mma!(
-        RegisterMmaShapeAttr::M16n8k16,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaOverflowAttr::Wrapping,
-        vec![u32_value; 7],
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&wrong_accumulator_signedness, &ctx).is_err());
-
-    let wrong_fragment_signedness = int_mma!(
-        RegisterMmaShapeAttr::M16n8k32,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaOverflowAttr::Satfinite,
-        vec![i32_value; 10],
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&wrong_fragment_signedness, &ctx).is_err());
-
-    let crossed_element = int_mma!(
-        RegisterMmaShapeAttr::M16n8k16,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::F16,
-        RegisterMmaOverflowAttr::Wrapping,
-        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&crossed_element, &ctx).is_err());
-
-    let crossed_overflow = int_mma!(
-        RegisterMmaShapeAttr::M16n8k32,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaElementAttr::U8,
-        RegisterMmaOverflowAttr::NotApplicable,
-        [vec![i32_value; 4], vec![u32_value; 6]].concat(),
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&crossed_overflow, &ctx).is_err());
-
-    let crossed_shape = int_mma!(
-        RegisterMmaShapeAttr::M16n8k8,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaElementAttr::S8,
-        RegisterMmaOverflowAttr::Satfinite,
-        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
-        vec![i32_ty.into(); 4]
-    );
-    assert!(verify_op(&crossed_shape, &ctx).is_err());
-}
-
-#[test]
-fn generated_register_mma_verifies_dense_b1_families() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    fn b1_mma(
-        ctx: &mut Context,
-        shape: RegisterMmaShapeAttr,
-        operation: Option<RegisterMmaOperationAttr>,
-    ) -> RegisterMmaOp {
-        let (accumulator_count, a_count, b_count, result_count) = match shape {
-            RegisterMmaShapeAttr::M8n8k128 => (2, 1, 1, 2),
-            RegisterMmaShapeAttr::M16n8k128 => (4, 2, 1, 4),
-            RegisterMmaShapeAttr::M16n8k256 => (4, 4, 2, 4),
-            _ => panic!("unsupported B1 MMA shape"),
-        };
-        let i32_ty = IntegerType::get(ctx, 32, Signedness::Signed);
-        let u32_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
-        let argument_types = (0..accumulator_count)
-            .map(|_| i32_ty.into())
-            .chain((0..a_count + b_count).map(|_| u32_ty.into()))
-            .collect();
-        let block = BasicBlock::new(ctx, None, argument_types);
-        let operands = (0..accumulator_count + a_count + b_count)
-            .map(|index| block.deref(ctx).get_argument(index))
-            .collect();
-        let op = Operation::new(
-            ctx,
-            RegisterMmaOp::get_concrete_op_info(),
-            vec![i32_ty.into(); result_count],
-            operands,
-            vec![],
-            0,
-        );
-        let mma = RegisterMmaOp::new(op);
-        mma.set_attr_nvvm_register_mma_shape(ctx, shape);
-        if let Some(operation) = operation {
-            mma.set_attr_nvvm_register_mma_operation(ctx, operation);
-        }
-        mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-        mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
-        mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
-        mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-        mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-        mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-        mma
-    }
-
-    let mut accepted = 0;
-    for shape in [
-        RegisterMmaShapeAttr::M8n8k128,
-        RegisterMmaShapeAttr::M16n8k128,
-        RegisterMmaShapeAttr::M16n8k256,
-    ] {
-        for operation in [
-            RegisterMmaOperationAttr::XorPopc,
-            RegisterMmaOperationAttr::AndPopc,
-        ] {
-            let mma = b1_mma(&mut ctx, shape.clone(), Some(operation));
-            assert!(verify_op(&mma, &ctx).is_ok(), "rejected {shape:?}");
-            accepted += 1;
-        }
-    }
-    assert_eq!(accepted, 6);
-
-    let multiply = b1_mma(
-        &mut ctx,
-        RegisterMmaShapeAttr::M8n8k128,
-        Some(RegisterMmaOperationAttr::Multiply),
-    );
-    assert!(verify_op(&multiply, &ctx).is_err());
-
-    let wrong_shape = b1_mma(
-        &mut ctx,
-        RegisterMmaShapeAttr::M16n8k128,
-        Some(RegisterMmaOperationAttr::XorPopc),
-    );
-    wrong_shape.set_attr_nvvm_register_mma_shape(&ctx, RegisterMmaShapeAttr::M16n8k64);
-    assert!(verify_op(&wrong_shape, &ctx).is_err());
-
-    let missing_operation = b1_mma(&mut ctx, RegisterMmaShapeAttr::M8n8k128, None);
-    assert!(verify_op(&missing_operation, &ctx).is_err());
-}
-
-#[test]
-fn generated_sparse_mma_verifies_all_int8_variants_and_metadata_modes() {
-    use dialect_mir::ops::MirConstantOp;
-    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![i32_ty.into(), u32_ty.into(), signless_i32_ty.into()],
-    );
-    let i32_value = block.deref(&ctx).get_argument(0);
-    let u32_value = block.deref(&ctx).get_argument(1);
-    let signless_i32_value = block.deref(&ctx).get_argument(2);
-
-    let integer = |value| {
-        IntegerAttr::new(
-            u32_ty,
-            APInt::from_u32(value, NonZeroUsize::new(32).unwrap()),
-        )
-    };
-    let builtin_zero = ConstantOp::new(&mut ctx, integer(0).into());
-    let builtin_zero = builtin_zero.get_operation().deref(&ctx).get_result(0);
-    let builtin_two = ConstantOp::new(&mut ctx, integer(2).into());
-    let builtin_two = builtin_two.get_operation().deref(&ctx).get_result(0);
-    let mir_one = Operation::new(
-        &mut ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    MirConstantOp::new(mir_one).set_attr_value(&ctx, integer(1));
-    let mir_one = mir_one.deref(&ctx).get_result(0);
-
-    macro_rules! sparse_mma {
-        ($operands:expr, $results:expr, $a:expr, $b:expr, $overflow:expr, $metadata:expr) => {{
-            let operation = Operation::new(
-                &mut ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                $results,
-                $operands,
-                vec![],
-                0,
-            );
-            let mma = SparseMmaOp::new(operation);
-            mma.set_attr_nvvm_sparse_mma_shape(&ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(&ctx, $a);
-            mma.set_attr_nvvm_sparse_mma_b_element(&ctx, $b);
-            mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(&ctx, $overflow);
-            mma.set_attr_nvvm_sparse_mma_metadata(&ctx, $metadata);
-            mma.set_attr_nvvm_sparse_mma_selector(&ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            mma
-        }};
-    }
-
-    let variants = [
-        (
-            SparseMmaElementAttr::S8,
-            SparseMmaElementAttr::S8,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::S8,
-            SparseMmaElementAttr::U8,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::U8,
-            SparseMmaElementAttr::U8,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::U8,
-            SparseMmaElementAttr::S8,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::S8,
-            SparseMmaElementAttr::S8,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            SparseMmaElementAttr::S8,
-            SparseMmaElementAttr::U8,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            SparseMmaElementAttr::U8,
-            SparseMmaElementAttr::U8,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            SparseMmaElementAttr::U8,
-            SparseMmaElementAttr::S8,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-    ];
-    for metadata in [
-        SparseMmaMetadataAttr::Standard,
-        SparseMmaMetadataAttr::Ordered,
-    ] {
-        for (index, (a_element, b_element, overflow)) in variants.iter().enumerate() {
-            let selector = if index % 2 == 0 {
-                builtin_zero
-            } else {
-                mir_one
-            };
-            let operands = [vec![i32_value; 4], vec![u32_value; 5], vec![selector]].concat();
-            let mma = sparse_mma!(
-                operands,
-                vec![i32_ty.into(); 4],
-                a_element.clone(),
-                b_element.clone(),
-                overflow.clone(),
-                metadata.clone()
-            );
-            assert_eq!(
-                mma.get_attr_nvvm_sparse_mma_a_element(&ctx).as_deref(),
-                Some(a_element)
-            );
-            assert_eq!(
-                mma.get_attr_nvvm_sparse_mma_b_element(&ctx).as_deref(),
-                Some(b_element)
-            );
-            assert_eq!(
-                mma.get_attr_nvvm_sparse_mma_overflow(&ctx).as_deref(),
-                Some(overflow)
-            );
-            assert_eq!(
-                mma.get_attr_nvvm_sparse_mma_metadata(&ctx).as_deref(),
-                Some(&metadata)
-            );
-            assert!(
-                verify_op(&mma, &ctx).is_ok(),
-                "rejected sparse {metadata:?} {a_element:?}x{b_element:?} {overflow:?}"
-            );
-        }
-    }
-
-    for metadata in [
-        SparseMmaMetadataAttr::Standard,
-        SparseMmaMetadataAttr::Ordered,
-    ] {
-        for selector in [u32_value, builtin_two] {
-            let invalid = sparse_mma!(
-                [vec![i32_value; 4], vec![u32_value; 5], vec![selector],].concat(),
-                vec![i32_ty.into(); 4],
-                SparseMmaElementAttr::S8,
-                SparseMmaElementAttr::U8,
-                SparseMmaOverflowAttr::Wrapping,
-                metadata.clone()
-            );
-            assert!(verify_op(&invalid, &ctx).is_err());
-        }
-    }
-
-    let wrong_accumulator_type = sparse_mma!(
-        [
-            vec![signless_i32_value; 4],
-            vec![u32_value; 5],
-            vec![builtin_zero],
-        ]
-        .concat(),
-        vec![i32_ty.into(); 4],
-        SparseMmaElementAttr::U8,
-        SparseMmaElementAttr::S8,
-        SparseMmaOverflowAttr::Satfinite,
-        SparseMmaMetadataAttr::Standard
-    );
-    assert!(verify_op(&wrong_accumulator_type, &ctx).is_err());
-
-    let wrong_count = sparse_mma!(
-        [vec![i32_value; 4], vec![u32_value; 4], vec![builtin_zero],].concat(),
-        vec![i32_ty.into(); 4],
-        SparseMmaElementAttr::S8,
-        SparseMmaElementAttr::S8,
-        SparseMmaOverflowAttr::Wrapping,
-        SparseMmaMetadataAttr::Standard
-    );
-    assert!(verify_op(&wrong_count, &ctx).is_err());
-
-    let wrong_results = sparse_mma!(
-        [vec![i32_value; 4], vec![u32_value; 5], vec![mir_one],].concat(),
-        vec![signless_i32_ty.into(); 4],
-        SparseMmaElementAttr::U8,
-        SparseMmaElementAttr::U8,
-        SparseMmaOverflowAttr::Wrapping,
-        SparseMmaMetadataAttr::Standard
-    );
-    assert!(verify_op(&wrong_results, &ctx).is_err());
-
-    let wrong_layout = sparse_mma!(
-        [vec![i32_value; 4], vec![u32_value; 5], vec![builtin_zero],].concat(),
-        vec![i32_ty.into(); 4],
-        SparseMmaElementAttr::S8,
-        SparseMmaElementAttr::U8,
-        SparseMmaOverflowAttr::Satfinite,
-        SparseMmaMetadataAttr::Standard
-    );
-    wrong_layout.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Row);
-    assert!(verify_op(&wrong_layout, &ctx).is_err());
-}
-
-#[test]
-fn generated_sparse_mma_m16n8k64_verifies_selector_and_carriers() {
-    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![i32_ty.into(), u32_ty.into(), signless_i32_ty.into()],
-    );
-    let i32_value = block.deref(&ctx).get_argument(0);
-    let u32_value = block.deref(&ctx).get_argument(1);
-    let signless_i32_value = block.deref(&ctx).get_argument(2);
-    let integer = |value| {
-        IntegerAttr::new(
-            u32_ty,
-            APInt::from_u32(value, NonZeroUsize::new(32).unwrap()),
-        )
-    };
-    let zero = ConstantOp::new(&mut ctx, integer(0).into())
-        .get_operation()
-        .deref(&ctx)
-        .get_result(0);
-    let one = ConstantOp::new(&mut ctx, integer(1).into())
-        .get_operation()
-        .deref(&ctx)
-        .get_result(0);
-    let two = ConstantOp::new(&mut ctx, integer(2).into())
-        .get_operation()
-        .deref(&ctx)
-        .get_result(0);
-
-    macro_rules! k64_mma {
-        ($operands:expr, $metadata:expr) => {{
-            let operation = Operation::new(
-                &mut ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![i32_ty.into(); 4],
-                $operands,
-                vec![],
-                0,
-            );
-            let mma = SparseMmaOp::new(operation);
-            mma.set_attr_nvvm_sparse_mma_shape(&ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(&ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(&ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(&ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(&ctx, $metadata);
-            mma.set_attr_nvvm_sparse_mma_selector(&ctx, SparseMmaSelectorAttr::ImmediateZero);
-            mma
-        }};
-    }
-
-    let operands = |selector| [vec![i32_value; 4], vec![u32_value; 9], vec![selector]].concat();
-    assert!(
-        verify_op(
-            &k64_mma!(operands(zero), SparseMmaMetadataAttr::Standard),
-            &ctx
-        )
-        .is_ok()
-    );
-    assert!(
-        verify_op(
-            &k64_mma!(operands(zero), SparseMmaMetadataAttr::Ordered),
-            &ctx
-        )
-        .is_ok()
-    );
-    assert!(
-        verify_op(
-            &k64_mma!(operands(one), SparseMmaMetadataAttr::Standard),
-            &ctx
-        )
-        .is_err()
-    );
-    assert!(
-        verify_op(
-            &k64_mma!(operands(one), SparseMmaMetadataAttr::Ordered),
-            &ctx
-        )
-        .is_err()
-    );
-    assert!(
-        verify_op(
-            &k64_mma!(operands(u32_value), SparseMmaMetadataAttr::Standard),
-            &ctx
-        )
-        .is_err()
-    );
-    assert!(
-        verify_op(
-            &k64_mma!(operands(u32_value), SparseMmaMetadataAttr::Ordered),
-            &ctx
-        )
-        .is_err()
-    );
-
-    let wrong_count = [vec![i32_value; 4], vec![u32_value; 8], vec![zero]].concat();
-    assert!(
-        verify_op(
-            &k64_mma!(wrong_count, SparseMmaMetadataAttr::Standard),
-            &ctx
-        )
-        .is_err()
-    );
-
-    let mut wrong_type = operands(zero);
-    wrong_type[4] = signless_i32_value;
-    assert!(verify_op(&k64_mma!(wrong_type, SparseMmaMetadataAttr::Standard), &ctx).is_err());
-
-    macro_rules! int4_mma {
-        ($operands:expr, $a:expr, $b:expr, $overflow:expr, $metadata:expr) => {{
-            let operation = Operation::new(
-                &mut ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![i32_ty.into(); 4],
-                $operands,
-                vec![],
-                0,
-            );
-            let mma = SparseMmaOp::new(operation);
-            mma.set_attr_nvvm_sparse_mma_shape(&ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(&ctx, $a);
-            mma.set_attr_nvvm_sparse_mma_b_element(&ctx, $b);
-            mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(&ctx, $overflow);
-            mma.set_attr_nvvm_sparse_mma_metadata(&ctx, $metadata);
-            mma.set_attr_nvvm_sparse_mma_selector(&ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            mma
-        }};
-    }
-
-    let int4_variants = [
-        (
-            SparseMmaElementAttr::S4,
-            SparseMmaElementAttr::S4,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::S4,
-            SparseMmaElementAttr::U4,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::U4,
-            SparseMmaElementAttr::U4,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::U4,
-            SparseMmaElementAttr::S4,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::S4,
-            SparseMmaElementAttr::S4,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            SparseMmaElementAttr::S4,
-            SparseMmaElementAttr::U4,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            SparseMmaElementAttr::U4,
-            SparseMmaElementAttr::U4,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            SparseMmaElementAttr::U4,
-            SparseMmaElementAttr::S4,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-    ];
-    let int4_operands =
-        |selector| [vec![i32_value; 4], vec![u32_value; 5], vec![selector]].concat();
-    for metadata in [
-        SparseMmaMetadataAttr::Standard,
-        SparseMmaMetadataAttr::Ordered,
-    ] {
-        for (index, (a, b, overflow)) in int4_variants.iter().enumerate() {
-            let selector = if index % 2 == 0 { zero } else { one };
-            assert!(
-                verify_op(
-                    &int4_mma!(
-                        int4_operands(selector),
-                        a.clone(),
-                        b.clone(),
-                        overflow.clone(),
-                        metadata.clone()
-                    ),
-                    &ctx,
-                )
-                .is_ok()
-            );
-        }
-    }
-
-    assert!(
-        verify_op(
-            &int4_mma!(
-                int4_operands(zero),
-                SparseMmaElementAttr::S4,
-                SparseMmaElementAttr::U8,
-                SparseMmaOverflowAttr::Wrapping,
-                SparseMmaMetadataAttr::Standard
-            ),
-            &ctx,
-        )
-        .is_err()
-    );
-    for metadata in [
-        SparseMmaMetadataAttr::Standard,
-        SparseMmaMetadataAttr::Ordered,
-    ] {
-        for selector in [two, u32_value] {
-            assert!(
-                verify_op(
-                    &int4_mma!(
-                        int4_operands(selector),
-                        SparseMmaElementAttr::S4,
-                        SparseMmaElementAttr::U4,
-                        SparseMmaOverflowAttr::Wrapping,
-                        metadata.clone()
-                    ),
-                    &ctx,
-                )
-                .is_err()
-            );
-        }
-    }
-}
-
-#[test]
-fn generated_sparse_mma_m16n8k128_int4_verifies_metadata_selector_and_widths() {
-    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), u32_ty.into()]);
-    let i32_value = block.deref(&ctx).get_argument(0);
-    let u32_value = block.deref(&ctx).get_argument(1);
-    let integer = |value| {
-        IntegerAttr::new(
-            u32_ty,
-            APInt::from_u32(value, NonZeroUsize::new(32).unwrap()),
-        )
-    };
-    let zero = ConstantOp::new(&mut ctx, integer(0).into())
-        .get_operation()
-        .deref(&ctx)
-        .get_result(0);
-    let one = ConstantOp::new(&mut ctx, integer(1).into())
-        .get_operation()
-        .deref(&ctx)
-        .get_result(0);
-
-    macro_rules! k128_mma {
-        ($operands:expr, $a:expr, $b:expr, $overflow:expr, $metadata:expr) => {{
-            let operation = Operation::new(
-                &mut ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![i32_ty.into(); 4],
-                $operands,
-                vec![],
-                0,
-            );
-            let mma = SparseMmaOp::new(operation);
-            mma.set_attr_nvvm_sparse_mma_shape(&ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(&ctx, $a);
-            mma.set_attr_nvvm_sparse_mma_b_element(&ctx, $b);
-            mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(&ctx, $overflow);
-            mma.set_attr_nvvm_sparse_mma_metadata(&ctx, $metadata);
-            mma.set_attr_nvvm_sparse_mma_selector(&ctx, SparseMmaSelectorAttr::ImmediateZero);
-            mma
-        }};
-    }
-
-    let variants = [
-        (
-            SparseMmaElementAttr::S4,
-            SparseMmaElementAttr::S4,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::S4,
-            SparseMmaElementAttr::U4,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::U4,
-            SparseMmaElementAttr::U4,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::U4,
-            SparseMmaElementAttr::S4,
-            SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            SparseMmaElementAttr::S4,
-            SparseMmaElementAttr::S4,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            SparseMmaElementAttr::S4,
-            SparseMmaElementAttr::U4,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            SparseMmaElementAttr::U4,
-            SparseMmaElementAttr::U4,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            SparseMmaElementAttr::U4,
-            SparseMmaElementAttr::S4,
-            SparseMmaOverflowAttr::Satfinite,
-        ),
-    ];
-    let operands = |selector| [vec![i32_value; 4], vec![u32_value; 9], vec![selector]].concat();
-    for metadata in [
-        SparseMmaMetadataAttr::Standard,
-        SparseMmaMetadataAttr::Ordered,
-    ] {
-        for (a, b, overflow) in &variants {
-            assert!(
-                verify_op(
-                    &k128_mma!(
-                        operands(zero),
-                        a.clone(),
-                        b.clone(),
-                        overflow.clone(),
-                        metadata.clone()
-                    ),
-                    &ctx,
-                )
-                .is_ok()
-            );
-        }
-    }
-
-    for metadata in [
-        SparseMmaMetadataAttr::Standard,
-        SparseMmaMetadataAttr::Ordered,
-    ] {
-        for selector in [one, u32_value] {
-            assert!(
-                verify_op(
-                    &k128_mma!(
-                        operands(selector),
-                        SparseMmaElementAttr::S4,
-                        SparseMmaElementAttr::U4,
-                        SparseMmaOverflowAttr::Wrapping,
-                        metadata.clone()
-                    ),
-                    &ctx,
-                )
-                .is_err()
-            );
-        }
-    }
-    assert!(
-        verify_op(
-            &k128_mma!(
-                operands(zero),
-                SparseMmaElementAttr::S4,
-                SparseMmaElementAttr::U8,
-                SparseMmaOverflowAttr::Wrapping,
-                SparseMmaMetadataAttr::Standard
-            ),
-            &ctx,
-        )
-        .is_err()
-    );
-    assert!(
-        verify_op(
-            &k128_mma!(
-                [vec![i32_value; 4], vec![u32_value; 8], vec![zero]].concat(),
-                SparseMmaElementAttr::S4,
-                SparseMmaElementAttr::S4,
-                SparseMmaOverflowAttr::Wrapping,
-                SparseMmaMetadataAttr::Standard
-            ),
-            &ctx,
-        )
-        .is_err()
-    );
-}
-
-#[test]
-fn generated_sparse_mma_f8f6f4_verifies_all_formats_and_closed_shape() {
-    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let f32_ty = FP32Type::get(&ctx);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let block = BasicBlock::new(&mut ctx, None, vec![f32_ty.into(), u32_ty.into()]);
-    let f32_value = block.deref(&ctx).get_argument(0);
-    let u32_value = block.deref(&ctx).get_argument(1);
-    let integer = |value| {
-        IntegerAttr::new(
-            u32_ty,
-            APInt::from_u32(value, NonZeroUsize::new(32).unwrap()),
-        )
-    };
-    let zero = ConstantOp::new(&mut ctx, integer(0).into())
-        .get_operation()
-        .deref(&ctx)
-        .get_result(0);
-    let one = ConstantOp::new(&mut ctx, integer(1).into())
-        .get_operation()
-        .deref(&ctx)
-        .get_result(0);
-
-    macro_rules! f8f6f4_mma {
-        ($operands:expr, $results:expr, $a:expr, $b:expr, $overflow:expr, $metadata:expr) => {{
-            let operation = Operation::new(
-                &mut ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                $results,
-                $operands,
-                vec![],
-                0,
-            );
-            let mma = SparseMmaOp::new(operation);
-            mma.set_attr_nvvm_sparse_mma_shape(&ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(&ctx, $a);
-            mma.set_attr_nvvm_sparse_mma_b_element(&ctx, $b);
-            mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(&ctx, $overflow);
-            mma.set_attr_nvvm_sparse_mma_metadata(&ctx, $metadata);
-            mma.set_attr_nvvm_sparse_mma_selector(&ctx, SparseMmaSelectorAttr::ImmediateZero);
-            mma
-        }};
-    }
-
-    let elements = [
-        SparseMmaElementAttr::E2m1,
-        SparseMmaElementAttr::E2m3,
-        SparseMmaElementAttr::E3m2,
-        SparseMmaElementAttr::E4m3,
-        SparseMmaElementAttr::E5m2,
-    ];
-    let operands = |selector| [vec![f32_value; 4], vec![u32_value; 9], vec![selector]].concat();
-    for a in &elements {
-        for b in &elements {
-            let mma = f8f6f4_mma!(
-                operands(zero),
-                vec![f32_ty.into(); 4],
-                a.clone(),
-                b.clone(),
-                SparseMmaOverflowAttr::NotApplicable,
-                SparseMmaMetadataAttr::Ordered
-            );
-            assert!(verify_op(&mma, &ctx).is_ok(), "rejected {a:?}x{b:?}");
-        }
-    }
-
-    for invalid in [
-        f8f6f4_mma!(
-            operands(one),
-            vec![f32_ty.into(); 4],
-            SparseMmaElementAttr::E2m1,
-            SparseMmaElementAttr::E2m1,
-            SparseMmaOverflowAttr::NotApplicable,
-            SparseMmaMetadataAttr::Ordered
-        ),
-        f8f6f4_mma!(
-            operands(zero),
-            vec![f32_ty.into(); 4],
-            SparseMmaElementAttr::E2m1,
-            SparseMmaElementAttr::E2m1,
-            SparseMmaOverflowAttr::Wrapping,
-            SparseMmaMetadataAttr::Ordered
-        ),
-        f8f6f4_mma!(
-            operands(zero),
-            vec![f32_ty.into(); 4],
-            SparseMmaElementAttr::E2m1,
-            SparseMmaElementAttr::E2m1,
-            SparseMmaOverflowAttr::NotApplicable,
-            SparseMmaMetadataAttr::Standard
-        ),
-        f8f6f4_mma!(
-            operands(zero),
-            vec![u32_ty.into(); 4],
-            SparseMmaElementAttr::E2m1,
-            SparseMmaElementAttr::E2m1,
-            SparseMmaOverflowAttr::NotApplicable,
-            SparseMmaMetadataAttr::Ordered
-        ),
-    ] {
-        assert!(verify_op(&invalid, &ctx).is_err());
-    }
-}
-
-#[test]
-fn test_matrix_memory_ops_verify_pointer_and_packed_register_types() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let f32_ty = FP32Type::get(&ctx);
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let load_ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
-
-    let load_block = BasicBlock::new(&mut ctx, None, vec![load_ptr_ty.into()]);
-    let load_pointer = load_block.deref(&ctx).get_argument(0);
-    let load = make_ldmatrix_x2(&mut ctx, load_pointer, vec![u32_ty.into(), u32_ty.into()]);
-    assert!(load.verify(&ctx).is_ok());
-
-    let bad_load_pointer_block = BasicBlock::new(&mut ctx, None, vec![i64_ty.into()]);
-    let bad_pointer = bad_load_pointer_block.deref(&ctx).get_argument(0);
-    let bad_load_pointer =
-        make_ldmatrix_x2(&mut ctx, bad_pointer, vec![u32_ty.into(), u32_ty.into()]);
-    assert!(bad_load_pointer.verify(&ctx).is_err());
-
-    let bad_load_result =
-        make_ldmatrix_x2(&mut ctx, load_pointer, vec![u32_ty.into(), f32_ty.into()]);
-    assert!(bad_load_result.verify(&ctx).is_err());
-
-    let store_block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            ptr_ty.into(),
-            i32_ty.into(),
-            i32_ty.into(),
-            i32_ty.into(),
-            i32_ty.into(),
-        ],
-    );
-    let store_operands = (0..5)
-        .map(|index| store_block.deref(&ctx).get_argument(index))
-        .collect();
-    let store = Operation::new(
-        &mut ctx,
-        StmatrixM8n8X4Op::get_concrete_op_info(),
-        vec![],
-        store_operands,
-        vec![],
-        0,
-    );
-    assert!(StmatrixM8n8X4Op::new(store).verify(&ctx).is_ok());
-
-    let bad_store_block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            ptr_ty.into(),
-            f32_ty.into(),
-            i32_ty.into(),
-            i32_ty.into(),
-            i32_ty.into(),
-        ],
-    );
-    let bad_store_operands = (0..5)
-        .map(|index| bad_store_block.deref(&ctx).get_argument(index))
-        .collect();
-    let bad_store = Operation::new(
-        &mut ctx,
-        StmatrixM8n8X4Op::get_concrete_op_info(),
-        vec![],
-        bad_store_operands,
-        vec![],
-        0,
-    );
-    assert!(StmatrixM8n8X4Op::new(bad_store).verify(&ctx).is_err());
-}
-
-#[test]
-fn test_packed_atomic_add_verifies_exact_raw_u32_shape() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let generic_u32_ptr = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
-    let global_u32_ptr = MirPtrType::get_global(&mut ctx, u32_ty.into(), true);
-    let immutable_u32_ptr = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
-    let shared_u32_ptr = MirPtrType::get_shared(&mut ctx, u32_ty.into(), true);
-    let generic_u64_ptr = MirPtrType::get_generic(&mut ctx, u64_ty.into(), true);
-
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            generic_u32_ptr.into(),
-            global_u32_ptr.into(),
-            immutable_u32_ptr.into(),
-            shared_u32_ptr.into(),
-            generic_u64_ptr.into(),
-            u32_ty.into(),
-            signless_i32_ty.into(),
-        ],
-    );
-    let generic_ptr = block.deref(&ctx).get_argument(0);
-    let global_ptr = block.deref(&ctx).get_argument(1);
-    let immutable_ptr = block.deref(&ctx).get_argument(2);
-    let shared_ptr = block.deref(&ctx).get_argument(3);
-    let wrong_pointee_ptr = block.deref(&ctx).get_argument(4);
-    let addend = block.deref(&ctx).get_argument(5);
-    let signless_addend = block.deref(&ctx).get_argument(6);
-
-    macro_rules! check_variant {
-        ($op:ty) => {{
-            for pointer in [generic_ptr, global_ptr] {
-                let valid = Operation::new(
-                    &mut ctx,
-                    <$op>::get_concrete_op_info(),
-                    vec![u32_ty.into()],
-                    vec![pointer, addend],
-                    vec![],
-                    0,
-                );
-                assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
-            }
-
-            for pointer in [immutable_ptr, shared_ptr, wrong_pointee_ptr] {
-                let invalid = Operation::new(
-                    &mut ctx,
-                    <$op>::get_concrete_op_info(),
-                    vec![u32_ty.into()],
-                    vec![pointer, addend],
-                    vec![],
-                    0,
-                );
-                assert!(verify_op(&<$op>::new(invalid), &ctx).is_err());
-            }
-
-            let bad_address = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![u32_ty.into()],
-                vec![addend, addend],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(bad_address), &ctx).is_err());
-
-            let bad_addend = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![u32_ty.into()],
-                vec![generic_ptr, signless_addend],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(bad_addend), &ctx).is_err());
-
-            let bad_result = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![signless_i32_ty.into()],
-                vec![generic_ptr, addend],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(bad_result), &ctx).is_err());
-
-            let bad_counts = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![],
-                vec![generic_ptr],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(bad_counts), &ctx).is_err());
-        }};
-    }
-
-    check_variant!(NvvmAtomAddF16x2Op);
-    check_variant!(NvvmAtomAddBf16x2Op);
-}
-
-#[test]
-fn test_generated_packed_atomic_add_requires_closed_attributes_and_raw_u32_shape() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let signed_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let global_u32_ptr = MirPtrType::get_global(&mut ctx, u32_ty.into(), true);
-    let immutable_u32_ptr = MirPtrType::get_global(&mut ctx, u32_ty.into(), false);
-    let shared_u32_ptr = MirPtrType::get_shared(&mut ctx, u32_ty.into(), true);
-    let local_u32_ptr = MirPtrType::get(&mut ctx, u32_ty.into(), true, address_space::LOCAL);
-    let constant_u32_ptr = MirPtrType::get_constant(&mut ctx, u32_ty.into(), true);
-    let global_u64_ptr = MirPtrType::get_global(&mut ctx, u64_ty.into(), true);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            global_u32_ptr.into(),
-            immutable_u32_ptr.into(),
-            shared_u32_ptr.into(),
-            local_u32_ptr.into(),
-            constant_u32_ptr.into(),
-            global_u64_ptr.into(),
-            u32_ty.into(),
-            signless_i32_ty.into(),
-        ],
-    );
-    let global = block.deref(&ctx).get_argument(0);
-    let immutable = block.deref(&ctx).get_argument(1);
-    let shared = block.deref(&ctx).get_argument(2);
-    let local = block.deref(&ctx).get_argument(3);
-    let constant = block.deref(&ctx).get_argument(4);
-    let wrong_pointee = block.deref(&ctx).get_argument(5);
-    let addend = block.deref(&ctx).get_argument(6);
-    let signless = block.deref(&ctx).get_argument(7);
-
-    for format in [
-        PackedAtomicFormatAttr::F16x2,
-        PackedAtomicFormatAttr::Bf16x2,
-    ] {
-        let valid = PackedAtomicAddOp::build(&mut ctx, global, addend, format);
-        assert!(verify_op(&PackedAtomicAddOp::new(valid), &ctx).is_ok());
-    }
-
-    for pointer in [immutable, shared, local, constant, wrong_pointee, addend] {
-        let invalid =
-            PackedAtomicAddOp::build(&mut ctx, pointer, addend, PackedAtomicFormatAttr::F16x2);
-        assert!(verify_op(&PackedAtomicAddOp::new(invalid), &ctx).is_err());
-    }
-    let bad_addend = Operation::new(
-        &mut ctx,
-        PackedAtomicAddOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![global, signless],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&PackedAtomicAddOp::new(bad_addend), &ctx).is_err());
-
-    fn set_closed_attributes(ctx: &Context, op: pliron::context::Ptr<Operation>) {
-        let packed = PackedAtomicAddOp::new(op);
-        packed.set_attr_nvvm_packed_atomic_format(ctx, PackedAtomicFormatAttr::F16x2);
-        packed.set_attr_nvvm_packed_atomic_state_space(ctx, PackedAtomicStateSpaceAttr::Global);
-        packed.set_attr_nvvm_packed_atomic_ordering(ctx, PackedAtomicOrderingAttr::Relaxed);
-        packed.set_attr_nvvm_packed_atomic_scope(ctx, PackedAtomicScopeAttr::Gpu);
-        packed.set_attr_nvvm_packed_atomic_rounding(ctx, PackedAtomicRoundingAttr::Rn);
-        packed.set_attr_nvvm_packed_atomic_subnormal(ctx, PackedAtomicSubnormalAttr::NoFtz);
-        packed.set_attr_nvvm_packed_atomic_atomicity(ctx, PackedAtomicAtomicityAttr::PerElement);
-    }
-
-    for result_ty in [signless_i32_ty.into(), signed_i32_ty.into(), u64_ty.into()] {
-        let bad_result = Operation::new(
-            &mut ctx,
-            PackedAtomicAddOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![global, addend],
-            vec![],
-            0,
-        );
-        set_closed_attributes(&ctx, bad_result);
-        assert!(verify_op(&PackedAtomicAddOp::new(bad_result), &ctx).is_err());
-    }
-
-    for (results, operands) in [
-        (vec![], vec![global, addend]),
-        (vec![u32_ty.into(), u32_ty.into()], vec![global, addend]),
-        (vec![u32_ty.into()], vec![global]),
-        (vec![u32_ty.into()], vec![global, addend, addend]),
-    ] {
-        let bad_counts = Operation::new(
-            &mut ctx,
-            PackedAtomicAddOp::get_concrete_op_info(),
-            results,
-            operands,
-            vec![],
-            0,
-        );
-        set_closed_attributes(&ctx, bad_counts);
-        assert!(verify_op(&PackedAtomicAddOp::new(bad_counts), &ctx).is_err());
-    }
-
-    // A structurally correct operation without the closed semantic attributes
-    // must fail instead of inheriting implicit defaults.
-    let missing_attributes = Operation::new(
-        &mut ctx,
-        PackedAtomicAddOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![global, addend],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&PackedAtomicAddOp::new(missing_attributes), &ctx).is_err());
-}
-
-#[test]
-fn test_thread_register_ops_verify_i32_results() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-
-    let tid_x = Operation::new(
-        &mut ctx,
-        ReadPtxSregTidXOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ReadPtxSregTidXOp::new(tid_x).verify(&ctx).is_ok());
-
-    let lane_id = Operation::new(
-        &mut ctx,
-        ReadPtxSregLaneIdOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ReadPtxSregLaneIdOp::new(lane_id).verify(&ctx).is_ok());
-}
-
-#[test]
-fn test_thread_register_ops_reject_non_i32_results() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let op = Operation::new(
-        &mut ctx,
-        ReadPtxSregTidXOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-
-    assert!(ReadPtxSregTidXOp::new(op).verify(&ctx).is_err());
-}
-
-#[test]
-fn test_lanemask_ops_verify_i32_results() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-
-    // Each lane-position mask is a zero-operand, single-i32-result sreg read.
-    let lt = Operation::new(
-        &mut ctx,
-        ReadPtxSregLanemaskLtOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ReadPtxSregLanemaskLtOp::new(lt).verify(&ctx).is_ok());
-
-    let le = Operation::new(
-        &mut ctx,
-        ReadPtxSregLanemaskLeOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ReadPtxSregLanemaskLeOp::new(le).verify(&ctx).is_ok());
-
-    let eq = Operation::new(
-        &mut ctx,
-        ReadPtxSregLanemaskEqOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ReadPtxSregLanemaskEqOp::new(eq).verify(&ctx).is_ok());
-
-    let ge = Operation::new(
-        &mut ctx,
-        ReadPtxSregLanemaskGeOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ReadPtxSregLanemaskGeOp::new(ge).verify(&ctx).is_ok());
-
-    let gt = Operation::new(
-        &mut ctx,
-        ReadPtxSregLanemaskGtOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ReadPtxSregLanemaskGtOp::new(gt).verify(&ctx).is_ok());
-}
-
-#[test]
-fn test_lanemask_op_rejects_non_i32_result() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    // A 64-bit result must fail the shared lane-position mask verifier.
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let op = Operation::new(
-        &mut ctx,
-        ReadPtxSregLanemaskLtOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ReadPtxSregLanemaskLtOp::new(op).verify(&ctx).is_err());
-}
-
-#[test]
-fn test_generated_vote_sync_family_requires_exact_mask_predicate_and_result_types() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![i32_ty.into(), i1_ty.into(), i64_ty.into()],
-    );
-    let mask = block.deref(&ctx).get_argument(0);
-    let predicate = block.deref(&ctx).get_argument(1);
-    let wide_mask = block.deref(&ctx).get_argument(2);
-
-    macro_rules! check_vote {
-        ($op:ty, $result_ty:expr, $wrong_result_ty:expr) => {{
-            let valid = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![$result_ty.into()],
-                vec![mask, predicate],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
-
-            for operands in [vec![], vec![mask], vec![mask, predicate, predicate]] {
-                let wrong_arity = Operation::new(
-                    &mut ctx,
-                    <$op>::get_concrete_op_info(),
-                    vec![$result_ty.into()],
-                    operands,
-                    vec![],
-                    0,
-                );
-                assert!(verify_op(&<$op>::new(wrong_arity), &ctx).is_err());
-            }
-
-            for results in [vec![], vec![$result_ty.into(), $result_ty.into()]] {
-                let wrong_arity = Operation::new(
-                    &mut ctx,
-                    <$op>::get_concrete_op_info(),
-                    results,
-                    vec![mask, predicate],
-                    vec![],
-                    0,
-                );
-                assert!(verify_op(&<$op>::new(wrong_arity), &ctx).is_err());
-            }
-
-            let wrong_mask = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![$result_ty.into()],
-                vec![wide_mask, predicate],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(wrong_mask), &ctx).is_err());
-
-            let wrong_predicate = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![$result_ty.into()],
-                vec![mask, mask],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(wrong_predicate), &ctx).is_err());
-
-            let wrong_result = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![$wrong_result_ty.into()],
-                vec![mask, predicate],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(wrong_result), &ctx).is_err());
-        }};
-    }
-
-    check_vote!(VoteSyncAllOp, i1_ty, u32_ty);
-    check_vote!(VoteSyncAnyOp, i1_ty, u32_ty);
-    check_vote!(VoteSyncBallotOp, u32_ty, i1_ty);
-    check_vote!(VoteSyncUniOp, i1_ty, u32_ty);
-}
-
-#[test]
-fn test_generated_active_mask_requires_no_operands_and_i32_result() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let unexpected_operand = block.deref(&ctx).get_argument(0);
-
-    let valid = Operation::new(
-        &mut ctx,
-        ActiveMaskOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ActiveMaskOp::new(valid), &ctx).is_ok());
-
-    let wrong_operand_count = Operation::new(
-        &mut ctx,
-        ActiveMaskOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![unexpected_operand],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ActiveMaskOp::new(wrong_operand_count), &ctx).is_err());
-
-    for results in [vec![], vec![i32_ty.into(), i32_ty.into()]] {
-        let wrong_result_count = Operation::new(
-            &mut ctx,
-            ActiveMaskOp::get_concrete_op_info(),
-            results,
-            vec![],
-            vec![],
-            0,
-        );
-        assert!(verify_op(&ActiveMaskOp::new(wrong_result_count), &ctx).is_err());
-    }
-
-    let wrong_result_width = Operation::new(
-        &mut ctx,
-        ActiveMaskOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ActiveMaskOp::new(wrong_result_width), &ctx).is_err());
-}
-
-#[test]
-fn test_generated_match_family_requires_exact_mask_value_and_result_widths() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![i32_ty.into(), i32_ty.into(), i64_ty.into()],
-    );
-    let mask = block.deref(&ctx).get_argument(0);
-    let value32 = block.deref(&ctx).get_argument(1);
-    let value64 = block.deref(&ctx).get_argument(2);
-
-    macro_rules! check_match {
-        ($op:ty, $value:expr, $wrong_value:expr) => {{
-            let valid = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![i32_ty.into()],
-                vec![mask, $value],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
-
-            for operands in [vec![], vec![mask], vec![mask, $value, $value]] {
-                let wrong_operand_count = Operation::new(
-                    &mut ctx,
-                    <$op>::get_concrete_op_info(),
-                    vec![i32_ty.into()],
-                    operands,
-                    vec![],
-                    0,
-                );
-                assert!(verify_op(&<$op>::new(wrong_operand_count), &ctx).is_err());
-            }
-
-            for results in [vec![], vec![i32_ty.into(), i32_ty.into()]] {
-                let wrong_result_count = Operation::new(
-                    &mut ctx,
-                    <$op>::get_concrete_op_info(),
-                    results,
-                    vec![mask, $value],
-                    vec![],
-                    0,
-                );
-                assert!(verify_op(&<$op>::new(wrong_result_count), &ctx).is_err());
-            }
-
-            let wrong_mask_width = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![i32_ty.into()],
-                vec![value64, $value],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(wrong_mask_width), &ctx).is_err());
-
-            let wrong_value_width = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![i32_ty.into()],
-                vec![mask, $wrong_value],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(wrong_value_width), &ctx).is_err());
-
-            let wrong_result_width = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![i64_ty.into()],
-                vec![mask, $value],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(wrong_result_width), &ctx).is_err());
-        }};
-    }
-
-    check_match!(MatchAnySyncI32Op, value32, value64);
-    check_match!(MatchAllSyncI32Op, value32, value64);
-    check_match!(MatchAnySyncI64Op, value64, value32);
-    check_match!(MatchAllSyncI64Op, value64, value32);
-}
-
-#[test]
-fn test_special_register_ops_verify_authoritative_widths() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-
-    macro_rules! check_width {
-        ($op:ty, $good:expr, $bad:expr) => {{
-            let good = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![$good.into()],
-                vec![],
-                vec![],
-                0,
-            );
-            assert!(
-                verify_op(&<$op>::new(good), &ctx).is_ok(),
-                "{} must accept its PTX register width",
-                stringify!($op)
-            );
-
-            let bad = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![$bad.into()],
-                vec![],
-                vec![],
-                0,
-            );
-            assert!(
-                verify_op(&<$op>::new(bad), &ctx).is_err(),
-                "{} must reject the other integer width",
-                stringify!($op)
-            );
-        }};
-    }
-
-    check_width!(ReadPtxSregWarpIdOp, i32_ty, i64_ty);
-    check_width!(ReadPtxSregNwarpIdOp, i32_ty, i64_ty);
-    check_width!(ReadPtxSregSmIdOp, i32_ty, i64_ty);
-    check_width!(ReadPtxSregNsmIdOp, i32_ty, i64_ty);
-    check_width!(ReadPtxSregDynamicSmemSizeOp, i32_ty, i64_ty);
-    check_width!(ReadPtxSregTotalSmemSizeOp, i32_ty, i64_ty);
-    check_width!(ReadPtxSregGridIdOp, i64_ty, i32_ty);
-}
-
-#[test]
-fn test_sync_ops_construct_and_verify() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let barrier = Operation::new(
-        &mut ctx,
-        Barrier0Op::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(Barrier0Op::new(barrier).verify(&ctx).is_ok());
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let unexpected_operand = block.deref(&ctx).get_argument(0);
-    let bad_operand = Operation::new(
-        &mut ctx,
-        Barrier0Op::get_concrete_op_info(),
-        vec![],
-        vec![unexpected_operand],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&Barrier0Op::new(bad_operand), &ctx).is_err());
-
-    let bad_result = Operation::new(
-        &mut ctx,
-        Barrier0Op::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&Barrier0Op::new(bad_result), &ctx).is_err());
-
-    let block_fence = Operation::new(
-        &mut ctx,
-        ThreadfenceBlockOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ThreadfenceBlockOp::new(block_fence).verify(&ctx).is_ok());
-
-    let device_fence = Operation::new(
-        &mut ctx,
-        ThreadfenceOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ThreadfenceOp::new(device_fence).verify(&ctx).is_ok());
-
-    let system_fence = Operation::new(
-        &mut ctx,
-        ThreadfenceSystemOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(ThreadfenceSystemOp::new(system_fence).verify(&ctx).is_ok());
-}
-
-#[test]
-fn test_bf16x2_fma_constructs_and_verifies_three_operands() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-
-    let a = Operation::new(
-        &mut ctx,
-        ReadPtxSregTidXOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let b = Operation::new(
-        &mut ctx,
-        ReadPtxSregTidXOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let c = Operation::new(
-        &mut ctx,
-        ReadPtxSregTidXOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-
-    let operands = vec![
-        a.deref(&ctx).get_result(0),
-        b.deref(&ctx).get_result(0),
-        c.deref(&ctx).get_result(0),
-    ];
-
-    let fma = Operation::new(
-        &mut ctx,
-        FmaBf16x2Op::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        operands,
-        vec![],
-        0,
-    );
-
-    assert!(FmaBf16x2Op::new(fma).verify(&ctx).is_ok());
-}
-
-#[test]
-fn test_generated_dot_products_require_three_i32_operands_and_one_i32_result() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![i32_ty.into(), i32_ty.into(), i32_ty.into(), i64_ty.into()],
-    );
-    let a = block.deref(&ctx).get_argument(0);
-    let b = block.deref(&ctx).get_argument(1);
-    let c = block.deref(&ctx).get_argument(2);
-    let wide = block.deref(&ctx).get_argument(3);
-
-    macro_rules! check_variant {
-        ($op:ty) => {{
-            let valid = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![i32_ty.into()],
-                vec![a, b, c],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
-
-            let wrong_width = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![i32_ty.into()],
-                vec![a, b, wide],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(wrong_width), &ctx).is_err());
-
-            for (results, operands) in [
-                (vec![], vec![a, b, c]),
-                (vec![i32_ty.into(), i32_ty.into()], vec![a, b, c]),
-                (vec![i32_ty.into()], vec![a, b]),
-                (vec![i32_ty.into()], vec![a, b, c, c]),
-            ] {
-                let wrong_count = Operation::new(
-                    &mut ctx,
-                    <$op>::get_concrete_op_info(),
-                    results,
-                    operands,
-                    vec![],
-                    0,
-                );
-                assert!(verify_op(&<$op>::new(wrong_count), &ctx).is_err());
-            }
-        }};
-    }
-
-    check_variant!(Dp4aS32Op);
-    check_variant!(Dp4aU32Op);
-    check_variant!(Dp2aS32Op);
-    check_variant!(Dp2aU32Op);
-}
-
-#[test]
-fn test_redux_sync_add_construct_and_verify() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-
-    // A block supplies the two operands [mask, value].
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), i32_ty.into()]);
-    let mask = block.deref(&ctx).get_argument(0);
-    let value = block.deref(&ctx).get_argument(1);
-
-    // Valid: 2 operands, 1 result (matches NOpdsInterface<2>/NResultsInterface<1>).
-    let op = Operation::new(
-        &mut ctx,
-        ReduxSyncAddOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![mask, value],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ReduxSyncAddOp::new(op), &ctx).is_ok());
-
-    // Invalid: wrong operand count (1 instead of 2) must fail verification.
-    let bad_opnds = Operation::new(
-        &mut ctx,
-        ReduxSyncAddOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![mask],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ReduxSyncAddOp::new(bad_opnds), &ctx).is_err());
-
-    // Invalid: wrong result count (0 instead of 1) must fail verification.
-    let bad_results = Operation::new(
-        &mut ctx,
-        ReduxSyncAddOp::get_concrete_op_info(),
-        vec![],
-        vec![mask, value],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ReduxSyncAddOp::new(bad_results), &ctx).is_err());
-}
-
-#[test]
-fn test_redux_sync_integer_family_construct_and_verify() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), i32_ty.into()]);
-    let mask = block.deref(&ctx).get_argument(0);
-    let value = block.deref(&ctx).get_argument(1);
-
-    // Every integer-family variant has the same 2-operand/1-result shape. A
-    // valid build of each must verify; a wrong operand count must not. The
-    // `new` wrapper is invoked so each concrete op type is exercised.
-    macro_rules! check_variant {
-        ($op:ty) => {{
-            let good = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![i32_ty.into()],
-                vec![mask, value],
-                vec![],
-                0,
-            );
-            assert!(
-                verify_op(&<$op>::new(good), &ctx).is_ok(),
-                "{} should verify with [mask, value] -> i32",
-                stringify!($op)
-            );
-
-            let bad = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![i32_ty.into()],
-                vec![mask],
-                vec![],
-                0,
-            );
-            assert!(
-                verify_op(&<$op>::new(bad), &ctx).is_err(),
-                "{} must reject a single operand",
-                stringify!($op)
-            );
-        }};
-    }
-
-    check_variant!(ReduxSyncUminOp);
-    check_variant!(ReduxSyncMinOp);
-    check_variant!(ReduxSyncUmaxOp);
-    check_variant!(ReduxSyncMaxOp);
-    check_variant!(ReduxSyncAndOp);
-    check_variant!(ReduxSyncOrOp);
-    check_variant!(ReduxSyncXorOp);
-}
-
-#[test]
-fn test_redux_sync_f32_family_construct_and_verify() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let f32_ty = FP32Type::get(&ctx);
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), f32_ty.into()]);
-    let mask = block.deref(&ctx).get_argument(0);
-    let value = block.deref(&ctx).get_argument(1);
-
-    // The good case goes through the generated `build()` so its f32 result
-    // construction is exercised; the bad case's i32 value and result must
-    // fail the `is_f32` verifier path.
-    macro_rules! check_variant {
-        ($op:ty) => {{
-            let good = <$op>::build(&mut ctx, mask, value);
-            assert!(
-                verify_op(&<$op>::new(good), &ctx).is_ok(),
-                "{} should verify with [mask, value] -> f32",
-                stringify!($op)
-            );
-
-            let bad = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![i32_ty.into()],
-                vec![mask, mask],
-                vec![],
-                0,
-            );
-            assert!(
-                verify_op(&<$op>::new(bad), &ctx).is_err(),
-                "{} must reject an i32 value and result",
-                stringify!($op)
-            );
-        }};
-    }
-
-    check_variant!(ReduxSyncFminOp);
-    check_variant!(ReduxSyncFminNanOp);
-    check_variant!(ReduxSyncFminAbsOp);
-    check_variant!(ReduxSyncFminAbsNanOp);
-    check_variant!(ReduxSyncFmaxOp);
-    check_variant!(ReduxSyncFmaxNanOp);
-    check_variant!(ReduxSyncFmaxAbsOp);
-    check_variant!(ReduxSyncFmaxAbsNanOp);
-}
-
-#[test]
-fn test_bar_warp_sync_construct_and_verify() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), i64_ty.into()]);
-    let mask = block.deref(&ctx).get_argument(0);
-    let wrong_mask = block.deref(&ctx).get_argument(1);
-
-    let valid = BarWarpSyncOp::build(&mut ctx, mask);
-    assert!(verify_op(&BarWarpSyncOp::new(valid), &ctx).is_ok());
-
-    let wrong_type = BarWarpSyncOp::build(&mut ctx, wrong_mask);
-    assert!(verify_op(&BarWarpSyncOp::new(wrong_type), &ctx).is_err());
-
-    let wrong_arity = Operation::new(
-        &mut ctx,
-        BarWarpSyncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&BarWarpSyncOp::new(wrong_arity), &ctx).is_err());
-}
-
-#[test]
-fn test_elect_sync_construct_and_verify() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-
-    // A block supplies the single `mask` operand.
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let mask = block.deref(&ctx).get_argument(0);
-
-    // Valid: 1 operand [mask], 2 results [leader (i32), is_elected (i1)]
-    // (matches NOpdsInterface<1>/NResultsInterface<2>).
-    let op = Operation::new(
-        &mut ctx,
-        ElectSyncOp::get_concrete_op_info(),
-        vec![i32_ty.into(), i1_ty.into()],
-        vec![mask],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ElectSyncOp::new(op), &ctx).is_ok());
-
-    // Invalid: wrong operand count (0 instead of 1) must fail verification.
-    let bad_opnds = Operation::new(
-        &mut ctx,
-        ElectSyncOp::get_concrete_op_info(),
-        vec![i32_ty.into(), i1_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ElectSyncOp::new(bad_opnds), &ctx).is_err());
-
-    // Invalid: wrong result count (1 instead of 2) must fail verification.
-    let bad_results = Operation::new(
-        &mut ctx,
-        ElectSyncOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![mask],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ElectSyncOp::new(bad_results), &ctx).is_err());
-
-    // Invalid: a correctly-sized result list still cannot use a pointer as
-    // either result and thereby manufacture a MIR pointer kind.
-    let pointer_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
-    let bad_result_type = Operation::new(
-        &mut ctx,
-        ElectSyncOp::get_concrete_op_info(),
-        vec![i32_ty.into(), pointer_ty.into()],
-        vec![mask],
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ElectSyncOp::new(bad_result_type), &ctx).is_err());
-}
-
-#[test]
-fn test_clc_query_rejects_pointer_results() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let block = BasicBlock::new(&mut ctx, None, vec![u64_ty.into(), u64_ty.into()]);
-    let operands = vec![
-        block.deref(&ctx).get_argument(0),
-        block.deref(&ctx).get_argument(1),
-    ];
-
-    let valid = Operation::new(
-        &mut ctx,
-        ClcQueryIsCanceledOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        operands.clone(),
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ClcQueryIsCanceledOp::new(valid), &ctx).is_ok());
-
-    let pointer_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, u32_ty.into(), true, MirPointerKind::UniqueRef);
-    let bad = Operation::new(
-        &mut ctx,
-        ClcQueryIsCanceledOp::get_concrete_op_info(),
-        vec![pointer_ty.into()],
-        operands,
-        vec![],
-        0,
-    );
-    assert!(verify_op(&ClcQueryIsCanceledOp::new(bad), &ctx).is_err());
-}
-
-#[test]
-fn test_shfl_sync_i64_construct_and_verify() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![i32_ty.into(), i64_ty.into(), i32_ty.into()],
-    );
-    let mask = block.deref(&ctx).get_argument(0);
-    let value = block.deref(&ctx).get_argument(1);
-    let lane = block.deref(&ctx).get_argument(2);
-
-    macro_rules! check_mode {
-        ($op:ty) => {{
-            let valid = <$op>::build(&mut ctx, mask, value, lane);
-            assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
-
-            for (operands, result_ty) in [
-                (vec![mask, value], i64_ty.into()),
-                (vec![value, value, lane], i64_ty.into()),
-                (vec![mask, mask, lane], i64_ty.into()),
-                (vec![mask, value, value], i64_ty.into()),
-                (vec![mask, value, lane], i32_ty.into()),
-            ] {
-                let invalid = Operation::new(
-                    &mut ctx,
-                    <$op>::get_concrete_op_info(),
-                    vec![result_ty],
-                    operands,
-                    vec![],
-                    0,
-                );
-                assert!(verify_op(&<$op>::new(invalid), &ctx).is_err());
-            }
-
-            let no_result = Operation::new(
-                &mut ctx,
-                <$op>::get_concrete_op_info(),
-                vec![],
-                vec![mask, value, lane],
-                vec![],
-                0,
-            );
-            assert!(verify_op(&<$op>::new(no_result), &ctx).is_err());
-        }};
-    }
-
-    check_mode!(ShflSyncIdxI64Op);
-    check_mode!(ShflSyncBflyI64Op);
-    check_mode!(ShflSyncDownI64Op);
-    check_mode!(ShflSyncUpI64Op);
-}
-
-#[test]
-fn handwritten_atomic_carriers_reject_malformed_ir() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let f32_ty = FP32Type::get(&ctx);
-    let generic_ptr = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            generic_ptr.into(),
-            u32_ty.into(),
-            i32_ty.into(),
-            f32_ty.into(),
-        ],
-    );
-    let pointer = block.deref(&ctx).get_argument(0);
-    let u32_value = block.deref(&ctx).get_argument(1);
-    let i32_value = block.deref(&ctx).get_argument(2);
-    let f32_value = block.deref(&ctx).get_argument(3);
-
-    assert!(
-        NvvmAtomicLoadOp::build(
-            &mut ctx,
-            pointer,
-            u32_ty.into(),
-            AtomicOrdering::Acquire,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_ok()
-    );
-    assert!(
-        NvvmAtomicStoreOp::build(
-            &mut ctx,
-            u32_value,
-            pointer,
-            AtomicOrdering::Release,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_ok()
-    );
-    assert!(
-        NvvmAtomicRmwOp::build(
-            &mut ctx,
-            pointer,
-            u32_value,
-            u32_ty.into(),
-            AtomicRmwKind::Add,
-            AtomicOrdering::AcqRel,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_ok()
-    );
-    assert!(
-        NvvmAtomicRmwOp::build(
-            &mut ctx,
-            pointer,
-            f32_value,
-            f32_ty.into(),
-            AtomicRmwKind::FAdd,
-            AtomicOrdering::Relaxed,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_ok()
-    );
-    assert!(
-        NvvmAtomicCmpxchgOp::build(
-            &mut ctx,
-            pointer,
-            u32_value,
-            u32_value,
-            u32_ty.into(),
-            AtomicOrdering::Relaxed,
-            AtomicOrdering::Acquire,
-            AtomicScope::System,
-        )
-        .verify(&ctx)
-        .is_ok()
-    );
-
-    for invalid in [
-        NvvmAtomicLoadOp::build(
-            &mut ctx,
-            pointer,
-            u32_ty.into(),
-            AtomicOrdering::Release,
-            AtomicScope::Device,
-        ),
-        NvvmAtomicLoadOp::build(
-            &mut ctx,
-            u32_value,
-            u32_ty.into(),
-            AtomicOrdering::Relaxed,
-            AtomicScope::Device,
-        ),
-    ] {
-        assert!(invalid.verify(&ctx).is_err());
-    }
-    assert!(
-        NvvmAtomicStoreOp::build(
-            &mut ctx,
-            u32_value,
-            pointer,
-            AtomicOrdering::Acquire,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_err()
-    );
-    assert!(
-        NvvmAtomicRmwOp::build(
-            &mut ctx,
-            pointer,
-            u32_value,
-            u64_ty.into(),
-            AtomicRmwKind::Add,
-            AtomicOrdering::Relaxed,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_err()
-    );
-    assert!(
-        NvvmAtomicRmwOp::build(
-            &mut ctx,
-            pointer,
-            u32_value,
-            u32_ty.into(),
-            AtomicRmwKind::FAdd,
-            AtomicOrdering::Relaxed,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_err()
-    );
-    assert!(
-        NvvmAtomicRmwOp::build(
-            &mut ctx,
-            pointer,
-            i32_value,
-            i32_ty.into(),
-            AtomicRmwKind::UMin,
-            AtomicOrdering::Relaxed,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_err()
-    );
-    assert!(
-        NvvmAtomicCmpxchgOp::build(
-            &mut ctx,
-            pointer,
-            f32_value,
-            f32_value,
-            f32_ty.into(),
-            AtomicOrdering::SeqCst,
-            AtomicOrdering::Relaxed,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_err()
-    );
-    assert!(
-        NvvmAtomicCmpxchgOp::build(
-            &mut ctx,
-            pointer,
-            u32_value,
-            i32_value,
-            u32_ty.into(),
-            AtomicOrdering::SeqCst,
-            AtomicOrdering::Relaxed,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_err()
-    );
-    assert!(
-        NvvmAtomicCmpxchgOp::build(
-            &mut ctx,
-            pointer,
-            u32_value,
-            u32_value,
-            u32_ty.into(),
-            AtomicOrdering::SeqCst,
-            AtomicOrdering::Release,
-            AtomicScope::Device,
-        )
-        .verify(&ctx)
-        .is_err()
-    );
-
-    let missing_attributes = Operation::new(
-        &mut ctx,
-        NvvmAtomicRmwOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![pointer, u32_value],
-        vec![],
-        0,
-    );
-    assert!(
-        NvvmAtomicRmwOp::new(missing_attributes)
-            .verify(&ctx)
-            .is_err()
-    );
-    let bad_count = Operation::new(
-        &mut ctx,
-        NvvmAtomicCmpxchgOp::get_concrete_op_info(),
-        vec![],
-        vec![pointer, u32_value],
-        vec![],
-        0,
-    );
-    assert!(NvvmAtomicCmpxchgOp::new(bad_count).verify(&ctx).is_err());
-}
-
-#[test]
-fn atomic_cmpxchg_accepts_exactly_llvm_ordering_pairs() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let pointer_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
-    let block = BasicBlock::new(&mut ctx, None, vec![pointer_ty.into(), u32_ty.into()]);
-    let pointer = block.deref(&ctx).get_argument(0);
-    let value = block.deref(&ctx).get_argument(1);
-
-    let orderings = [
-        AtomicOrdering::Relaxed,
-        AtomicOrdering::Acquire,
-        AtomicOrdering::Release,
-        AtomicOrdering::AcqRel,
-        AtomicOrdering::SeqCst,
-    ];
-    for success in &orderings {
-        for failure in &orderings {
-            let expected = matches!(
-                failure,
-                AtomicOrdering::Relaxed | AtomicOrdering::Acquire | AtomicOrdering::SeqCst
-            );
-            let actual = NvvmAtomicCmpxchgOp::build(
-                &mut ctx,
-                pointer,
-                value,
-                value,
-                u32_ty.into(),
-                success.clone(),
-                failure.clone(),
-                AtomicScope::Device,
-            )
-            .verify(&ctx)
-            .is_ok();
-            assert_eq!(
-                actual, expected,
-                "unexpected cmpxchg ordering result for success={success:?}, failure={failure:?}"
-            );
-        }
-    }
-}
-
-#[test]
-fn handwritten_ffi_and_wgmma_carriers_verify_exact_shapes() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let f32_ty = FP32Type::get(&ctx);
-    let pointer_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
-    let accumulator_pointer_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), true);
-    let global_pointer_ty = MirPtrType::get_global(&mut ctx, u8_ty.into(), false);
-    let mutable_global_pointer_ty = MirPtrType::get_global(&mut ctx, u8_ty.into(), true);
-    let block = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            pointer_ty.into(),
-            accumulator_pointer_ty.into(),
-            global_pointer_ty.into(),
-            mutable_global_pointer_ty.into(),
-            u32_ty.into(),
-            u64_ty.into(),
-            f32_ty.into(),
-        ],
-    );
-    let pointer = block.deref(&ctx).get_argument(0);
-    let accumulator_pointer = block.deref(&ctx).get_argument(1);
-    let global_pointer = block.deref(&ctx).get_argument(2);
-    let mutable_global_pointer = block.deref(&ctx).get_argument(3);
-    let u32_value = block.deref(&ctx).get_argument(4);
-    let u64_value = block.deref(&ctx).get_argument(5);
-    let f32_value = block.deref(&ctx).get_argument(6);
-
-    let vprintf = VprintfOp::build(&mut ctx, pointer, pointer);
-    assert!(VprintfOp::new(vprintf).verify(&ctx).is_ok());
-
-    let i64_signless_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let assertfail = AssertFailOp::build(&mut ctx, pointer, pointer, u32_value, pointer, u64_value);
-    assert!(AssertFailOp::new(assertfail).verify(&ctx).is_ok());
-    for (operands, results) in [
-        // message must be a MIR pointer
-        (
-            vec![u32_value, pointer, u32_value, pointer, u64_value],
-            vec![],
-        ),
-        // line must be a 32-bit integer
-        (
-            vec![pointer, pointer, u64_value, pointer, u64_value],
-            vec![],
-        ),
-        // char size must be a 64-bit integer
-        (
-            vec![pointer, pointer, u32_value, pointer, u32_value],
-            vec![],
-        ),
-        // wrong operand count
-        (vec![pointer, pointer, u32_value], vec![]),
-        // must have no results
-        (
-            vec![pointer, pointer, u32_value, pointer, u64_value],
-            vec![i64_signless_ty.into()],
-        ),
-    ] {
-        let invalid = Operation::new(
-            &mut ctx,
-            AssertFailOp::get_concrete_op_info(),
-            results,
-            operands,
-            vec![],
-            0,
-        );
-        assert!(AssertFailOp::new(invalid).verify(&ctx).is_err());
-    }
-    let bad_vprintf = Operation::new(
-        &mut ctx,
-        VprintfOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![pointer, u32_value],
-        vec![],
-        0,
-    );
-    assert!(VprintfOp::new(bad_vprintf).verify(&ctx).is_err());
-
-    let descriptor = Operation::new(
-        &mut ctx,
-        WgmmaMakeSmemDescOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![pointer],
-        vec![],
-        0,
-    );
-    assert!(WgmmaMakeSmemDescOp::new(descriptor).verify(&ctx).is_ok());
-    for (operands, results) in [
-        (vec![u32_value], vec![u64_ty.into()]),
-        (vec![global_pointer], vec![u64_ty.into()]),
-        (vec![pointer], vec![u32_ty.into()]),
-        (vec![], vec![u64_ty.into()]),
-    ] {
-        let invalid = Operation::new(
-            &mut ctx,
-            WgmmaMakeSmemDescOp::get_concrete_op_info(),
-            results,
-            operands,
-            vec![],
-            0,
-        );
-        assert!(WgmmaMakeSmemDescOp::new(invalid).verify(&ctx).is_err());
-    }
-
-    let cvta = Operation::new(
-        &mut ctx,
-        CvtaGenericToSharedOffsetOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![pointer],
-        vec![],
-        0,
-    );
-    assert!(CvtaGenericToSharedOffsetOp::new(cvta).verify(&ctx).is_ok());
-    for (operands, results) in [
-        // Operand must be a MIR pointer.
-        (vec![u32_value], vec![u64_ty.into()]),
-        // Operand must point to generic or shared memory.
-        (vec![global_pointer], vec![u64_ty.into()]),
-        // Result must be u64.
-        (vec![pointer], vec![u32_ty.into()]),
-        // Exact arity is required.
-        (vec![], vec![u64_ty.into()]),
-    ] {
-        let invalid = Operation::new(
-            &mut ctx,
-            CvtaGenericToSharedOffsetOp::get_concrete_op_info(),
-            results,
-            operands,
-            vec![],
-            0,
-        );
-        assert!(
-            CvtaGenericToSharedOffsetOp::new(invalid)
-                .verify(&ctx)
-                .is_err()
-        );
-    }
-
-    let mma = Operation::new(
-        &mut ctx,
-        WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![],
-        vec![accumulator_pointer, u64_value, u64_value],
-        vec![],
-        0,
-    );
-    assert!(WgmmaMmaM64N64K16F32Bf16Op::new(mma).verify(&ctx).is_ok());
-    for (operands, results) in [
-        // Accumulator must be mutable.
-        (vec![pointer, u64_value, u64_value], vec![]),
-        // Accumulator must use generic address space.
-        (vec![mutable_global_pointer, u64_value, u64_value], vec![]),
-        // Accumulator must be a MIR pointer.
-        (vec![u32_value, u64_value, u64_value], vec![]),
-        // Descriptors must be u64.
-        (vec![accumulator_pointer, u32_value, u64_value], vec![]),
-        // Exact arity is required.
-        (vec![accumulator_pointer, u64_value], vec![]),
-        // No results are permitted.
-        (
-            vec![accumulator_pointer, u64_value, u64_value],
-            vec![u32_ty.into()],
-        ),
-    ] {
-        let invalid = Operation::new(
-            &mut ctx,
-            WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
-            results,
-            operands,
-            vec![],
-            0,
-        );
-        assert!(
-            WgmmaMmaM64N64K16F32Bf16Op::new(invalid)
-                .verify(&ctx)
-                .is_err()
-        );
-    }
-
-    let group = WgmmaMmaGroupM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        accumulator_pointer,
-        vec![u64_value, u64_value, u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupM64N64K16F32Bf16Op::new(group)
-            .verify(&ctx)
-            .is_ok()
-    );
-    for (operands, results) in [
-        // Missing descriptor.
-        (vec![accumulator_pointer, u64_value], vec![]),
-        // Incomplete descriptor pair.
-        (
-            vec![accumulator_pointer, u64_value, u64_value, u64_value],
-            vec![],
-        ),
-        // Accumulator must be mutable.
-        (vec![pointer, u64_value, u64_value], vec![]),
-        // Accumulator must use generic address space.
-        (vec![mutable_global_pointer, u64_value, u64_value], vec![]),
-        // Accumulator must be a MIR pointer.
-        (vec![u32_value, u64_value, u64_value], vec![]),
-        // Descriptors must be u64.
-        (vec![accumulator_pointer, u64_value, u32_value], vec![]),
-        // No results are permitted.
-        (
-            vec![accumulator_pointer, u64_value, u64_value],
-            vec![u32_ty.into()],
-        ),
-    ] {
-        let invalid = Operation::new(
-            &mut ctx,
-            WgmmaMmaGroupM64N64K16F32Bf16Op::get_concrete_op_info(),
-            results,
-            operands,
-            vec![],
-            0,
-        );
-        assert!(
-            WgmmaMmaGroupM64N64K16F32Bf16Op::new(invalid)
-                .verify(&ctx)
-                .is_err()
-        );
-    }
-
-    let value_group = WgmmaMmaGroupValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        vec![u64_value, u64_value, u64_value, u64_value],
-    );
-    {
-        let value_group_ref = value_group.deref(&ctx);
-        assert_eq!(value_group_ref.get_num_operands(), 36);
-        assert_eq!(value_group_ref.get_num_results(), 32);
-    }
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(value_group)
-            .verify(&ctx)
-            .is_ok()
-    );
-
-    let too_few_accumulators = WgmmaMmaGroupValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 31],
-        vec![u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(too_few_accumulators)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let missing_descriptors =
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::build(&mut ctx, vec![f32_value; 32], vec![]);
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(missing_descriptors)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let incomplete_descriptor_pair = WgmmaMmaGroupValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        vec![u64_value, u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(incomplete_descriptor_pair)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let mut wrong_accumulator_operands = vec![f32_value; 32];
-    wrong_accumulator_operands[0] = u32_value;
-    wrong_accumulator_operands.extend([u64_value, u64_value]);
-    let wrong_accumulator = Operation::new(
-        &mut ctx,
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 32],
-        wrong_accumulator_operands,
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(wrong_accumulator)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let mut wrong_descriptor_operands = vec![f32_value; 32];
-    wrong_descriptor_operands.extend([u32_value, u64_value]);
-    let wrong_descriptor = Operation::new(
-        &mut ctx,
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 32],
-        wrong_descriptor_operands,
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(wrong_descriptor)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let mut valid_value_operands = vec![f32_value; 32];
-    valid_value_operands.extend([u64_value, u64_value]);
-
-    let wrong_result_count = Operation::new(
-        &mut ctx,
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 31],
-        valid_value_operands.clone(),
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(wrong_result_count)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let mut wrong_result_types = vec![f32_ty.into(); 32];
-    wrong_result_types[0] = u32_ty.into();
-    let wrong_result_type = Operation::new(
-        &mut ctx,
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
-        wrong_result_types,
-        valid_value_operands,
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(wrong_result_type)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let wide_mma = Operation::new(
-        &mut ctx,
-        WgmmaMmaM64N128K16F32Bf16Op::get_concrete_op_info(),
-        vec![],
-        vec![accumulator_pointer, u64_value, u64_value],
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaM64N128K16F32Bf16Op::new(wide_mma)
-            .verify(&ctx)
-            .is_ok()
-    );
-
-    let wide_value_group = WgmmaMmaGroupValuesM64N128K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 64],
-        vec![u64_value, u64_value],
-    );
-    {
-        let group_ref = wide_value_group.deref(&ctx);
-        assert_eq!(group_ref.get_num_operands(), 66);
-        assert_eq!(group_ref.get_num_results(), 64);
-    }
-    assert!(
-        WgmmaMmaGroupValuesM64N128K16F32Bf16Op::new(wide_value_group)
-            .verify(&ctx)
-            .is_ok()
-    );
-
-    let wide_too_few = WgmmaMmaGroupValuesM64N128K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 63],
-        vec![u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N128K16F32Bf16Op::new(wide_too_few)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let wide_incomplete_pair = WgmmaMmaGroupValuesM64N128K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 64],
-        vec![u64_value, u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N128K16F32Bf16Op::new(wide_incomplete_pair)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let f16_mma = Operation::new(
-        &mut ctx,
-        WgmmaMmaM64N64K16F32F16Op::get_concrete_op_info(),
-        vec![],
-        vec![accumulator_pointer, u64_value, u64_value],
-        vec![],
-        0,
-    );
-    assert!(WgmmaMmaM64N64K16F32F16Op::new(f16_mma).verify(&ctx).is_ok());
-    for operands in [
-        vec![pointer, u64_value, u64_value],
-        vec![mutable_global_pointer, u64_value, u64_value],
-        vec![accumulator_pointer, u32_value, u64_value],
-    ] {
-        let invalid = Operation::new(
-            &mut ctx,
-            WgmmaMmaM64N64K16F32F16Op::get_concrete_op_info(),
-            vec![],
-            operands,
-            vec![],
-            0,
-        );
-        assert!(
-            WgmmaMmaM64N64K16F32F16Op::new(invalid)
-                .verify(&ctx)
-                .is_err()
-        );
-    }
-
-    let f16_value_group = WgmmaMmaGroupValuesM64N64K16F32F16Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        vec![u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32F16Op::new(f16_value_group)
-            .verify(&ctx)
-            .is_ok()
-    );
-
-    let f16_too_few_accumulators = WgmmaMmaGroupValuesM64N64K16F32F16Op::build(
-        &mut ctx,
-        vec![f32_value; 31],
-        vec![u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32F16Op::new(f16_too_few_accumulators)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let f16_incomplete_descriptor_pair = WgmmaMmaGroupValuesM64N64K16F32F16Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        vec![u64_value, u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32F16Op::new(f16_incomplete_descriptor_pair)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let mut f16_wrong_accumulator_operands = vec![f32_value; 32];
-    f16_wrong_accumulator_operands[0] = u32_value;
-    f16_wrong_accumulator_operands.extend([u64_value, u64_value]);
-    let f16_wrong_accumulator = Operation::new(
-        &mut ctx,
-        WgmmaMmaGroupValuesM64N64K16F32F16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 32],
-        f16_wrong_accumulator_operands,
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K16F32F16Op::new(f16_wrong_accumulator)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let tf32_mma = Operation::new(
-        &mut ctx,
-        WgmmaMmaM64N64K8F32Tf32Op::get_concrete_op_info(),
-        vec![],
-        vec![accumulator_pointer, u64_value, u64_value],
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaM64N64K8F32Tf32Op::new(tf32_mma)
-            .verify(&ctx)
-            .is_ok()
-    );
-    for operands in [
-        vec![pointer, u64_value, u64_value],
-        vec![mutable_global_pointer, u64_value, u64_value],
-        vec![accumulator_pointer, u32_value, u64_value],
-    ] {
-        let invalid = Operation::new(
-            &mut ctx,
-            WgmmaMmaM64N64K8F32Tf32Op::get_concrete_op_info(),
-            vec![],
-            operands,
-            vec![],
-            0,
-        );
-        assert!(
-            WgmmaMmaM64N64K8F32Tf32Op::new(invalid)
-                .verify(&ctx)
-                .is_err()
-        );
-    }
-
-    let tf32_value_group = WgmmaMmaGroupValuesM64N64K8F32Tf32Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        vec![u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K8F32Tf32Op::new(tf32_value_group)
-            .verify(&ctx)
-            .is_ok()
-    );
-
-    let tf32_too_few_accumulators = WgmmaMmaGroupValuesM64N64K8F32Tf32Op::build(
-        &mut ctx,
-        vec![f32_value; 31],
-        vec![u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K8F32Tf32Op::new(tf32_too_few_accumulators)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let tf32_incomplete_descriptor_pair = WgmmaMmaGroupValuesM64N64K8F32Tf32Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        vec![u64_value, u64_value, u64_value],
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K8F32Tf32Op::new(tf32_incomplete_descriptor_pair)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let mut tf32_wrong_accumulator_operands = vec![f32_value; 32];
-    tf32_wrong_accumulator_operands[0] = u32_value;
-    tf32_wrong_accumulator_operands.extend([u64_value, u64_value]);
-    let tf32_wrong_accumulator = Operation::new(
-        &mut ctx,
-        WgmmaMmaGroupValuesM64N64K8F32Tf32Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 32],
-        tf32_wrong_accumulator_operands,
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaGroupValuesM64N64K8F32Tf32Op::new(tf32_wrong_accumulator)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let loop_group = WgmmaMmaLoopValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        u64_value,
-        u64_value,
-        u64_value,
-        u64_value,
-        u64_value,
-    );
-    {
-        let loop_group_ref = loop_group.deref(&ctx);
-        assert_eq!(loop_group_ref.get_num_operands(), 37);
-        assert_eq!(loop_group_ref.get_num_results(), 32);
-    }
-    assert!(
-        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::new(loop_group)
-            .verify(&ctx)
-            .is_ok()
-    );
-
-    let f16_loop_group = WgmmaMmaLoopValuesM64N64K16F32F16Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        u64_value,
-        u64_value,
-        u64_value,
-        u64_value,
-        u64_value,
-    );
-    {
-        let loop_group_ref = f16_loop_group.deref(&ctx);
-        assert_eq!(loop_group_ref.get_num_operands(), 37);
-        assert_eq!(loop_group_ref.get_num_results(), 32);
-    }
-    assert!(
-        WgmmaMmaLoopValuesM64N64K16F32F16Op::new(f16_loop_group)
-            .verify(&ctx)
-            .is_ok()
-    );
-
-    let mut f16_wrong_loop_control_operands = vec![f32_value; 32];
-    f16_wrong_loop_control_operands.extend([u64_value, u64_value, u32_value, u64_value, u64_value]);
-    let f16_wrong_loop_control = Operation::new(
-        &mut ctx,
-        WgmmaMmaLoopValuesM64N64K16F32F16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 32],
-        f16_wrong_loop_control_operands,
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaLoopValuesM64N64K16F32F16Op::new(f16_wrong_loop_control)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let too_few_loop_accumulators = WgmmaMmaLoopValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 31],
-        u64_value,
-        u64_value,
-        u64_value,
-        u64_value,
-        u64_value,
-    );
-    assert!(
-        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::new(too_few_loop_accumulators)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let mut wrong_loop_control_operands = vec![f32_value; 32];
-    wrong_loop_control_operands.extend([u64_value, u64_value, u32_value, u64_value, u64_value]);
-    let wrong_loop_control = Operation::new(
-        &mut ctx,
-        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 32],
-        wrong_loop_control_operands,
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::new(wrong_loop_control)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let mut valid_loop_operands = vec![f32_value; 32];
-    valid_loop_operands.extend([u64_value; 5]);
-
-    let wrong_loop_result_count = Operation::new(
-        &mut ctx,
-        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 31],
-        valid_loop_operands.clone(),
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::new(wrong_loop_result_count)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let mut wrong_loop_result_types = vec![f32_ty.into(); 32];
-    wrong_loop_result_types[0] = u32_ty.into();
-    let wrong_loop_result_type = Operation::new(
-        &mut ctx,
-        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
-        wrong_loop_result_types,
-        valid_loop_operands,
-        vec![],
-        0,
-    );
-    assert!(
-        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::new(wrong_loop_result_type)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let counted_pipeline_group = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 64],
-        vec![u64_value; 4],
-        vec![u64_value; 4],
-        u64_value,
-        1,
-    );
-    {
-        let counted_pipeline_ref = counted_pipeline_group.deref(&ctx);
-        assert_eq!(counted_pipeline_ref.get_num_operands(), 73);
-        assert_eq!(counted_pipeline_ref.get_num_results(), 64);
-    }
-    let counted_pipeline =
-        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(counted_pipeline_group);
-    assert_eq!(counted_pipeline.max_pending_groups(&ctx), Some(1));
-    assert!(counted_pipeline.verify(&ctx).is_ok());
-
-    let three_slot_counted_pipeline = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 96],
-        vec![u64_value; 6],
-        vec![u64_value; 6],
-        u64_value,
-        2,
-    );
-    {
-        let counted_pipeline_ref = three_slot_counted_pipeline.deref(&ctx);
-        assert_eq!(counted_pipeline_ref.get_num_operands(), 109);
-        assert_eq!(counted_pipeline_ref.get_num_results(), 96);
-    }
-    let three_slot_counted_pipeline =
-        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(three_slot_counted_pipeline);
-    assert_eq!(
-        three_slot_counted_pipeline.max_pending_groups(&ctx),
-        Some(2)
-    );
-    assert!(three_slot_counted_pipeline.verify(&ctx).is_ok());
-
-    let too_many_accumulators_for_wait_one = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 96],
-        vec![u64_value; 4],
-        vec![u64_value; 4],
-        u64_value,
-        1,
-    );
-    assert!(
-        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(too_many_accumulators_for_wait_one)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let too_few_accumulators_for_wait_two = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 64],
-        vec![u64_value; 6],
-        vec![u64_value; 6],
-        u64_value,
-        2,
-    );
-    assert!(
-        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(too_few_accumulators_for_wait_two)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let unsupported_wait_three = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 128],
-        vec![u64_value; 8],
-        vec![u64_value; 8],
-        u64_value,
-        3,
-    );
-    assert!(
-        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(unsupported_wait_three)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let wrong_counted_pipeline_control = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 64],
-        vec![u64_value; 4],
-        vec![u64_value, u64_value, u32_value, u64_value],
-        u64_value,
-        1,
-    );
-    assert!(
-        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(wrong_counted_pipeline_control)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    let mut valid_counted_pipeline_operands = vec![f32_value; 64];
-    valid_counted_pipeline_operands.extend([u64_value; 9]);
-    let wrong_counted_pipeline_result_count = Operation::new(
-        &mut ctx,
-        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 63],
-        valid_counted_pipeline_operands.clone(),
-        vec![],
-        0,
-    );
-    let wrong_counted_pipeline_result_count =
-        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(wrong_counted_pipeline_result_count);
-    wrong_counted_pipeline_result_count
-        .set_attr_counted_max_pending_groups(&ctx, WgmmaMaxPendingAttr(1));
-    assert!(wrong_counted_pipeline_result_count.verify(&ctx).is_err());
-
-    let mut wrong_counted_pipeline_result_types = vec![f32_ty.into(); 64];
-    wrong_counted_pipeline_result_types[0] = u32_ty.into();
-    let wrong_counted_pipeline_result_type = Operation::new(
-        &mut ctx,
-        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
-        wrong_counted_pipeline_result_types,
-        valid_counted_pipeline_operands,
-        vec![],
-        0,
-    );
-    let wrong_counted_pipeline_result_type =
-        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(wrong_counted_pipeline_result_type);
-    wrong_counted_pipeline_result_type
-        .set_attr_counted_max_pending_groups(&ctx, WgmmaMaxPendingAttr(1));
-    assert!(wrong_counted_pipeline_result_type.verify(&ctx).is_err());
-
-    let pipeline_group = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 64],
-        vec![u64_value; 8],
-        1,
-    );
-    {
-        let pipeline_ref = pipeline_group.deref(&ctx);
-        assert_eq!(pipeline_ref.get_num_operands(), 72);
-        assert_eq!(pipeline_ref.get_num_results(), 64);
-    }
-    let pipeline = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::new(pipeline_group);
-    assert_eq!(pipeline.max_pending_groups(&ctx), Some(1));
-    assert!(pipeline.verify(&ctx).is_ok());
-
-    let too_few_pipeline_slots = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        vec![u64_value; 4],
-        1,
-    );
-    assert!(
-        WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::new(too_few_pipeline_slots)
-            .verify(&ctx)
-            .is_err()
-    );
-
-    assert!(WgmmaMaxPendingAttr(1).verify(&ctx).is_ok());
-    assert!(WgmmaMaxPendingAttr(7).verify(&ctx).is_ok());
-    assert!(WgmmaMaxPendingAttr(0).verify(&ctx).is_err());
-    assert!(WgmmaMaxPendingAttr(8).verify(&ctx).is_err());
-
-    let zero_pending_pipeline = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        vec![u64_value; 2],
-        0,
-    );
-    let zero_pending_error = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::new(zero_pending_pipeline)
-        .verify(&ctx)
-        .unwrap_err();
-    assert!(
-        zero_pending_error
-            .err
-            .to_string()
-            .contains("nvvm.wgmma_max_pending_groups must be in 1..=7, got 0"),
-        "unexpected zero-pending error: {}",
-        zero_pending_error.err
-    );
-
-    let excess_pending_pipeline = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::build(
-        &mut ctx,
-        vec![f32_value; 32],
-        vec![u64_value; 2],
-        8,
-    );
-    let excess_pending_error =
-        WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::new(excess_pending_pipeline)
-            .verify(&ctx)
-            .unwrap_err();
-    assert!(
-        excess_pending_error
-            .err
-            .to_string()
-            .contains("nvvm.wgmma_max_pending_groups must be in 1..=7, got 8"),
-        "unexpected excess-pending error: {}",
-        excess_pending_error.err
-    );
-
-    let mut missing_attr_operands = vec![f32_value; 64];
-    missing_attr_operands.extend([u64_value; 8]);
-    let missing_attr_pipeline = Operation::new(
-        &mut ctx,
-        WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 64],
-        missing_attr_operands,
-        vec![],
-        0,
-    );
-    let missing_attr_error = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::new(missing_attr_pipeline)
-        .verify(&ctx)
-        .unwrap_err();
-    assert!(
-        missing_attr_error
-            .err
-            .to_string()
-            .contains("requires an nvvm.wgmma_max_pending_groups attribute"),
-        "unexpected missing-attribute error: {}",
-        missing_attr_error.err
-    );
-}
-
-#[test]
-fn test_inline_ptx_results_must_match_output_constraints() {
-    let mut ctx = Context::new();
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    let input = block.deref(&ctx).get_argument(0);
-
-    let void = InlinePtxOp::build(&mut ctx, vec![], vec![], "membar.gl;", "", true, false);
-    assert!(verify_op(&InlinePtxOp::new(void), &ctx).is_ok());
-
-    let single = InlinePtxOp::build(
-        &mut ctx,
-        vec![i32_ty.into()],
-        vec![input],
-        "add.u32 $0, $1, $1;",
-        "=r,r",
-        false,
-        false,
-    );
-    assert!(verify_op(&InlinePtxOp::new(single), &ctx).is_ok());
-
-    let multi = InlinePtxOp::build(
-        &mut ctx,
-        vec![i32_ty.into(), i32_ty.into()],
-        vec![input],
-        "add.u32 $0, $2, $2; mul.lo.u32 $1, $2, $2;",
-        "=r,=r,r",
-        false,
-        false,
-    );
-    assert!(verify_op(&InlinePtxOp::new(multi), &ctx).is_ok());
-
-    let missing_result = InlinePtxOp::build(
-        &mut ctx,
-        vec![i32_ty.into()],
-        vec![input],
-        "add.u32 $0, $2, $2; mul.lo.u32 $1, $2, $2;",
-        "=r,=r,r",
-        false,
-        false,
-    );
-    assert!(verify_op(&InlinePtxOp::new(missing_result), &ctx).is_err());
-
-    let extra_result = InlinePtxOp::build(
-        &mut ctx,
-        vec![i32_ty.into()],
-        vec![input],
-        "prefetch.global.L1 [$0];",
-        "r",
-        true,
-        false,
-    );
-    assert!(verify_op(&InlinePtxOp::new(extra_result), &ctx).is_err());
-}
-
-#[test]
-fn test_inline_ptx_pointer_results_require_exact_inline_asm_authority() {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let unique_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
-    let erased_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::Erased);
-    let nested_erased_ty = MirTupleType::get(&mut ctx, vec![erased_ty.into()]);
-
-    let build = |ctx: &mut Context, result_ty| {
-        InlinePtxOp::build(
-            ctx,
-            vec![result_ty],
-            vec![],
-            "mov.u64 $0, 0;",
-            "=l",
-            false,
-            false,
-        )
-    };
-
-    for (name, result_ty) in [
-        ("UniqueRef", unique_ty.into()),
-        ("Erased", erased_ty.into()),
-        ("nested Erased", nested_erased_ty.into()),
-    ] {
-        let unmarked = InlinePtxOp::new(build(&mut ctx, result_ty));
-        let error = verify_op(&unmarked, &ctx).unwrap_err();
-        assert!(
-            error
-                .err
-                .to_string()
-                .contains("pointer-carrying results require InlineAsm pointer-kind authority"),
-            "unexpected unmarked {name} error: {}",
-            error.err
-        );
-
-        let marked = InlinePtxOp::new(build(&mut ctx, result_ty));
-        marked.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::InlineAsm);
-        assert!(
-            verify_op(&marked, &ctx).is_ok(),
-            "marked {name} pointer result should verify"
-        );
-    }
-
-    let wrong_authority = InlinePtxOp::new(build(&mut ctx, unique_ty.into()));
-    wrong_authority.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RustCast);
-    let wrong_error = verify_op(&wrong_authority, &ctx).unwrap_err();
-    assert!(
-        wrong_error.err.to_string().contains("found RustCast"),
-        "unexpected wrong-authority error: {}",
-        wrong_error.err
-    );
-
-    let spurious = InlinePtxOp::new(build(&mut ctx, i32_ty.into()));
-    spurious.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::InlineAsm);
-    let spurious_error = verify_op(&spurious, &ctx).unwrap_err();
-    assert!(
-        spurious_error
-            .err
-            .to_string()
-            .contains("spurious for pointer-free results"),
-        "unexpected spurious-authority error: {}",
-        spurious_error.err
-    );
-}
-
-#[test]
-fn test_inline_ptx_count_output_constraints() {
-    assert_eq!(InlinePtxOp::count_output_constraints("=r,r,r"), 1);
-    assert_eq!(InlinePtxOp::count_output_constraints("=r,=r,=f,=d,r,l"), 4);
-    assert_eq!(InlinePtxOp::count_output_constraints("r,l,~{memory}"), 0);
-    assert_eq!(InlinePtxOp::count_output_constraints(""), 0);
-    // `=` only counts as an output marker at the start of a token.
-    assert_eq!(InlinePtxOp::count_output_constraints("r,r=f"), 0);
-}
diff --git a/crates/dialect-nvvm/tests/ops_test/allowlist.rs b/crates/dialect-nvvm/tests/ops_test/allowlist.rs
new file mode 100644
index 0000000000..bc48d66501
--- /dev/null
+++ b/crates/dialect-nvvm/tests/ops_test/allowlist.rs
@@ -0,0 +1,74 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#[test]
+fn handwritten_ops_match_reviewed_allowlist() {
+    use std::{fs, path::Path};
+
+    let ops_dir = Path::new(env!("CARGO_MANIFEST_DIR")).join("src/ops");
+    let mut found = Vec::new();
+
+    for entry in fs::read_dir(&ops_dir).expect("read top-level NVVM ops directory") {
+        let path = entry.expect("read NVVM ops entry").path();
+        if path.extension().and_then(|extension| extension.to_str()) != Some("rs") {
+            continue;
+        }
+
+        let source = fs::read_to_string(&path).expect("read handwritten NVVM ops source");
+        let file = path
+            .file_name()
+            .and_then(|name| name.to_str())
+            .expect("NVVM ops file name");
+
+        for (marker, _) in source.match_indices("#[pliron_op(") {
+            let declaration = source[marker..]
+                .lines()
+                .find_map(|line| line.trim().strip_prefix("pub struct "))
+                .expect("pliron_op must be followed by a public struct");
+            let name = declaration
+                .split(|character: char| !character.is_ascii_alphanumeric() && character != '_')
+                .next()
+                .expect("NVVM op struct name");
+            found.push((file.to_owned(), name.to_owned()));
+        }
+    }
+
+    let mut expected = [
+        ("asm.rs", "InlinePtxOp"),
+        ("atomic.rs", "NvvmAtomicLoadOp"),
+        ("atomic.rs", "NvvmAtomicStoreOp"),
+        ("atomic.rs", "NvvmAtomicFenceOp"),
+        ("atomic.rs", "NvvmAtomicRmwOp"),
+        ("atomic.rs", "NvvmAtomicCmpxchgOp"),
+        ("cluster.rs", "ReadPtxSregClusterIdxOp"),
+        ("cluster.rs", "ReadPtxSregNclusterIdOp"),
+        ("debug.rs", "AssertFailOp"),
+        ("debug.rs", "VprintfOp"),
+        ("grid.rs", "GridSyncOp"),
+        ("memory.rs", "CvtaGenericToSharedOffsetOp"),
+        ("wgmma.rs", "WgmmaMakeSmemDescOp"),
+        ("wgmma.rs", "WgmmaMmaM64N64K16F32Bf16Op"),
+        ("wgmma.rs", "WgmmaMmaM64N128K16F32Bf16Op"),
+        ("wgmma.rs", "WgmmaMmaM64N64K16F32F16Op"),
+        ("wgmma.rs", "WgmmaMmaM64N64K8F32Tf32Op"),
+        ("wgmma.rs", "WgmmaMmaGroupM64N64K16F32Bf16Op"),
+        ("wgmma.rs", "WgmmaMmaGroupValuesM64N64K16F32Bf16Op"),
+        ("wgmma.rs", "WgmmaMmaGroupValuesM64N128K16F32Bf16Op"),
+        ("wgmma.rs", "WgmmaMmaGroupValuesM64N64K16F32F16Op"),
+        ("wgmma.rs", "WgmmaMmaGroupValuesM64N64K8F32Tf32Op"),
+        ("wgmma.rs", "WgmmaMmaLoopValuesM64N64K16F32Bf16Op"),
+        ("wgmma.rs", "WgmmaMmaLoopValuesM64N64K16F32F16Op"),
+        ("wgmma.rs", "WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op"),
+        ("wgmma.rs", "WgmmaMmaPipelineValuesM64N64K16F32Bf16Op"),
+    ];
+    expected.sort_unstable();
+    found.sort_unstable();
+
+    assert_eq!(
+        found,
+        expected.map(|(file, op)| (file.to_owned(), op.to_owned())),
+        "top-level handwritten NVVM ops changed; generate leaf ops or review this allowlist"
+    );
+}
diff --git a/crates/dialect-nvvm/tests/ops_test/atomics.rs b/crates/dialect-nvvm/tests/ops_test/atomics.rs
new file mode 100644
index 0000000000..5680a27e9f
--- /dev/null
+++ b/crates/dialect-nvvm/tests/ops_test/atomics.rs
@@ -0,0 +1,516 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::types::{MirPtrType, address_space};
+use dialect_nvvm::ops::{
+    AtomicOrdering, AtomicRmwKind, AtomicScope, NvvmAtomAddBf16x2Op, NvvmAtomAddF16x2Op,
+    NvvmAtomicCmpxchgOp, NvvmAtomicLoadOp, NvvmAtomicRmwOp, NvvmAtomicStoreOp, PackedAtomicAddOp,
+    PackedAtomicAtomicityAttr, PackedAtomicFormatAttr, PackedAtomicOrderingAttr,
+    PackedAtomicRoundingAttr, PackedAtomicScopeAttr, PackedAtomicStateSpaceAttr,
+    PackedAtomicSubnormalAttr,
+};
+
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::types::{FP32Type, IntegerType, Signedness},
+    common_traits::Verify,
+    context::Context,
+    op::{Op, verify_op},
+    operation::Operation,
+};
+
+#[test]
+fn test_packed_atomic_add_verifies_exact_raw_u32_shape() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let generic_u32_ptr = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
+    let global_u32_ptr = MirPtrType::get_global(&mut ctx, u32_ty.into(), true);
+    let immutable_u32_ptr = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
+    let shared_u32_ptr = MirPtrType::get_shared(&mut ctx, u32_ty.into(), true);
+    let generic_u64_ptr = MirPtrType::get_generic(&mut ctx, u64_ty.into(), true);
+
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            generic_u32_ptr.into(),
+            global_u32_ptr.into(),
+            immutable_u32_ptr.into(),
+            shared_u32_ptr.into(),
+            generic_u64_ptr.into(),
+            u32_ty.into(),
+            signless_i32_ty.into(),
+        ],
+    );
+    let generic_ptr = block.deref(&ctx).get_argument(0);
+    let global_ptr = block.deref(&ctx).get_argument(1);
+    let immutable_ptr = block.deref(&ctx).get_argument(2);
+    let shared_ptr = block.deref(&ctx).get_argument(3);
+    let wrong_pointee_ptr = block.deref(&ctx).get_argument(4);
+    let addend = block.deref(&ctx).get_argument(5);
+    let signless_addend = block.deref(&ctx).get_argument(6);
+
+    macro_rules! check_variant {
+        ($op:ty) => {{
+            for pointer in [generic_ptr, global_ptr] {
+                let valid = Operation::new(
+                    &mut ctx,
+                    <$op>::get_concrete_op_info(),
+                    vec![u32_ty.into()],
+                    vec![pointer, addend],
+                    vec![],
+                    0,
+                );
+                assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
+            }
+
+            for pointer in [immutable_ptr, shared_ptr, wrong_pointee_ptr] {
+                let invalid = Operation::new(
+                    &mut ctx,
+                    <$op>::get_concrete_op_info(),
+                    vec![u32_ty.into()],
+                    vec![pointer, addend],
+                    vec![],
+                    0,
+                );
+                assert!(verify_op(&<$op>::new(invalid), &ctx).is_err());
+            }
+
+            let bad_address = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![u32_ty.into()],
+                vec![addend, addend],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(bad_address), &ctx).is_err());
+
+            let bad_addend = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![u32_ty.into()],
+                vec![generic_ptr, signless_addend],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(bad_addend), &ctx).is_err());
+
+            let bad_result = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![signless_i32_ty.into()],
+                vec![generic_ptr, addend],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(bad_result), &ctx).is_err());
+
+            let bad_counts = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![],
+                vec![generic_ptr],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(bad_counts), &ctx).is_err());
+        }};
+    }
+
+    check_variant!(NvvmAtomAddF16x2Op);
+    check_variant!(NvvmAtomAddBf16x2Op);
+}
+
+#[test]
+fn test_generated_packed_atomic_add_requires_closed_attributes_and_raw_u32_shape() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let signed_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let global_u32_ptr = MirPtrType::get_global(&mut ctx, u32_ty.into(), true);
+    let immutable_u32_ptr = MirPtrType::get_global(&mut ctx, u32_ty.into(), false);
+    let shared_u32_ptr = MirPtrType::get_shared(&mut ctx, u32_ty.into(), true);
+    let local_u32_ptr = MirPtrType::get(&mut ctx, u32_ty.into(), true, address_space::LOCAL);
+    let constant_u32_ptr = MirPtrType::get_constant(&mut ctx, u32_ty.into(), true);
+    let global_u64_ptr = MirPtrType::get_global(&mut ctx, u64_ty.into(), true);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            global_u32_ptr.into(),
+            immutable_u32_ptr.into(),
+            shared_u32_ptr.into(),
+            local_u32_ptr.into(),
+            constant_u32_ptr.into(),
+            global_u64_ptr.into(),
+            u32_ty.into(),
+            signless_i32_ty.into(),
+        ],
+    );
+    let global = block.deref(&ctx).get_argument(0);
+    let immutable = block.deref(&ctx).get_argument(1);
+    let shared = block.deref(&ctx).get_argument(2);
+    let local = block.deref(&ctx).get_argument(3);
+    let constant = block.deref(&ctx).get_argument(4);
+    let wrong_pointee = block.deref(&ctx).get_argument(5);
+    let addend = block.deref(&ctx).get_argument(6);
+    let signless = block.deref(&ctx).get_argument(7);
+
+    for format in [
+        PackedAtomicFormatAttr::F16x2,
+        PackedAtomicFormatAttr::Bf16x2,
+    ] {
+        let valid = PackedAtomicAddOp::build(&mut ctx, global, addend, format);
+        assert!(verify_op(&PackedAtomicAddOp::new(valid), &ctx).is_ok());
+    }
+
+    for pointer in [immutable, shared, local, constant, wrong_pointee, addend] {
+        let invalid =
+            PackedAtomicAddOp::build(&mut ctx, pointer, addend, PackedAtomicFormatAttr::F16x2);
+        assert!(verify_op(&PackedAtomicAddOp::new(invalid), &ctx).is_err());
+    }
+    let bad_addend = Operation::new(
+        &mut ctx,
+        PackedAtomicAddOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![global, signless],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&PackedAtomicAddOp::new(bad_addend), &ctx).is_err());
+
+    fn set_closed_attributes(ctx: &Context, op: pliron::context::Ptr<Operation>) {
+        let packed = PackedAtomicAddOp::new(op);
+        packed.set_attr_nvvm_packed_atomic_format(ctx, PackedAtomicFormatAttr::F16x2);
+        packed.set_attr_nvvm_packed_atomic_state_space(ctx, PackedAtomicStateSpaceAttr::Global);
+        packed.set_attr_nvvm_packed_atomic_ordering(ctx, PackedAtomicOrderingAttr::Relaxed);
+        packed.set_attr_nvvm_packed_atomic_scope(ctx, PackedAtomicScopeAttr::Gpu);
+        packed.set_attr_nvvm_packed_atomic_rounding(ctx, PackedAtomicRoundingAttr::Rn);
+        packed.set_attr_nvvm_packed_atomic_subnormal(ctx, PackedAtomicSubnormalAttr::NoFtz);
+        packed.set_attr_nvvm_packed_atomic_atomicity(ctx, PackedAtomicAtomicityAttr::PerElement);
+    }
+
+    for result_ty in [signless_i32_ty.into(), signed_i32_ty.into(), u64_ty.into()] {
+        let bad_result = Operation::new(
+            &mut ctx,
+            PackedAtomicAddOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![global, addend],
+            vec![],
+            0,
+        );
+        set_closed_attributes(&ctx, bad_result);
+        assert!(verify_op(&PackedAtomicAddOp::new(bad_result), &ctx).is_err());
+    }
+
+    for (results, operands) in [
+        (vec![], vec![global, addend]),
+        (vec![u32_ty.into(), u32_ty.into()], vec![global, addend]),
+        (vec![u32_ty.into()], vec![global]),
+        (vec![u32_ty.into()], vec![global, addend, addend]),
+    ] {
+        let bad_counts = Operation::new(
+            &mut ctx,
+            PackedAtomicAddOp::get_concrete_op_info(),
+            results,
+            operands,
+            vec![],
+            0,
+        );
+        set_closed_attributes(&ctx, bad_counts);
+        assert!(verify_op(&PackedAtomicAddOp::new(bad_counts), &ctx).is_err());
+    }
+
+    // A structurally correct operation without the closed semantic attributes
+    // must fail instead of inheriting implicit defaults.
+    let missing_attributes = Operation::new(
+        &mut ctx,
+        PackedAtomicAddOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![global, addend],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&PackedAtomicAddOp::new(missing_attributes), &ctx).is_err());
+}
+
+#[test]
+fn handwritten_atomic_carriers_reject_malformed_ir() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let f32_ty = FP32Type::get(&ctx);
+    let generic_ptr = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            generic_ptr.into(),
+            u32_ty.into(),
+            i32_ty.into(),
+            f32_ty.into(),
+        ],
+    );
+    let pointer = block.deref(&ctx).get_argument(0);
+    let u32_value = block.deref(&ctx).get_argument(1);
+    let i32_value = block.deref(&ctx).get_argument(2);
+    let f32_value = block.deref(&ctx).get_argument(3);
+
+    assert!(
+        NvvmAtomicLoadOp::build(
+            &mut ctx,
+            pointer,
+            u32_ty.into(),
+            AtomicOrdering::Acquire,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_ok()
+    );
+    assert!(
+        NvvmAtomicStoreOp::build(
+            &mut ctx,
+            u32_value,
+            pointer,
+            AtomicOrdering::Release,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_ok()
+    );
+    assert!(
+        NvvmAtomicRmwOp::build(
+            &mut ctx,
+            pointer,
+            u32_value,
+            u32_ty.into(),
+            AtomicRmwKind::Add,
+            AtomicOrdering::AcqRel,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_ok()
+    );
+    assert!(
+        NvvmAtomicRmwOp::build(
+            &mut ctx,
+            pointer,
+            f32_value,
+            f32_ty.into(),
+            AtomicRmwKind::FAdd,
+            AtomicOrdering::Relaxed,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_ok()
+    );
+    assert!(
+        NvvmAtomicCmpxchgOp::build(
+            &mut ctx,
+            pointer,
+            u32_value,
+            u32_value,
+            u32_ty.into(),
+            AtomicOrdering::Relaxed,
+            AtomicOrdering::Acquire,
+            AtomicScope::System,
+        )
+        .verify(&ctx)
+        .is_ok()
+    );
+
+    for invalid in [
+        NvvmAtomicLoadOp::build(
+            &mut ctx,
+            pointer,
+            u32_ty.into(),
+            AtomicOrdering::Release,
+            AtomicScope::Device,
+        ),
+        NvvmAtomicLoadOp::build(
+            &mut ctx,
+            u32_value,
+            u32_ty.into(),
+            AtomicOrdering::Relaxed,
+            AtomicScope::Device,
+        ),
+    ] {
+        assert!(invalid.verify(&ctx).is_err());
+    }
+    assert!(
+        NvvmAtomicStoreOp::build(
+            &mut ctx,
+            u32_value,
+            pointer,
+            AtomicOrdering::Acquire,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_err()
+    );
+    assert!(
+        NvvmAtomicRmwOp::build(
+            &mut ctx,
+            pointer,
+            u32_value,
+            u64_ty.into(),
+            AtomicRmwKind::Add,
+            AtomicOrdering::Relaxed,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_err()
+    );
+    assert!(
+        NvvmAtomicRmwOp::build(
+            &mut ctx,
+            pointer,
+            u32_value,
+            u32_ty.into(),
+            AtomicRmwKind::FAdd,
+            AtomicOrdering::Relaxed,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_err()
+    );
+    assert!(
+        NvvmAtomicRmwOp::build(
+            &mut ctx,
+            pointer,
+            i32_value,
+            i32_ty.into(),
+            AtomicRmwKind::UMin,
+            AtomicOrdering::Relaxed,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_err()
+    );
+    assert!(
+        NvvmAtomicCmpxchgOp::build(
+            &mut ctx,
+            pointer,
+            f32_value,
+            f32_value,
+            f32_ty.into(),
+            AtomicOrdering::SeqCst,
+            AtomicOrdering::Relaxed,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_err()
+    );
+    assert!(
+        NvvmAtomicCmpxchgOp::build(
+            &mut ctx,
+            pointer,
+            u32_value,
+            i32_value,
+            u32_ty.into(),
+            AtomicOrdering::SeqCst,
+            AtomicOrdering::Relaxed,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_err()
+    );
+    assert!(
+        NvvmAtomicCmpxchgOp::build(
+            &mut ctx,
+            pointer,
+            u32_value,
+            u32_value,
+            u32_ty.into(),
+            AtomicOrdering::SeqCst,
+            AtomicOrdering::Release,
+            AtomicScope::Device,
+        )
+        .verify(&ctx)
+        .is_err()
+    );
+
+    let missing_attributes = Operation::new(
+        &mut ctx,
+        NvvmAtomicRmwOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![pointer, u32_value],
+        vec![],
+        0,
+    );
+    assert!(
+        NvvmAtomicRmwOp::new(missing_attributes)
+            .verify(&ctx)
+            .is_err()
+    );
+    let bad_count = Operation::new(
+        &mut ctx,
+        NvvmAtomicCmpxchgOp::get_concrete_op_info(),
+        vec![],
+        vec![pointer, u32_value],
+        vec![],
+        0,
+    );
+    assert!(NvvmAtomicCmpxchgOp::new(bad_count).verify(&ctx).is_err());
+}
+
+#[test]
+fn atomic_cmpxchg_accepts_exactly_llvm_ordering_pairs() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let pointer_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
+    let block = BasicBlock::new(&mut ctx, None, vec![pointer_ty.into(), u32_ty.into()]);
+    let pointer = block.deref(&ctx).get_argument(0);
+    let value = block.deref(&ctx).get_argument(1);
+
+    let orderings = [
+        AtomicOrdering::Relaxed,
+        AtomicOrdering::Acquire,
+        AtomicOrdering::Release,
+        AtomicOrdering::AcqRel,
+        AtomicOrdering::SeqCst,
+    ];
+    for success in &orderings {
+        for failure in &orderings {
+            let expected = matches!(
+                failure,
+                AtomicOrdering::Relaxed | AtomicOrdering::Acquire | AtomicOrdering::SeqCst
+            );
+            let actual = NvvmAtomicCmpxchgOp::build(
+                &mut ctx,
+                pointer,
+                value,
+                value,
+                u32_ty.into(),
+                success.clone(),
+                failure.clone(),
+                AtomicScope::Device,
+            )
+            .verify(&ctx)
+            .is_ok();
+            assert_eq!(
+                actual, expected,
+                "unexpected cmpxchg ordering result for success={success:?}, failure={failure:?}"
+            );
+        }
+    }
+}
diff --git a/crates/dialect-nvvm/tests/ops_test/carriers.rs b/crates/dialect-nvvm/tests/ops_test/carriers.rs
new file mode 100644
index 0000000000..9555f85cab
--- /dev/null
+++ b/crates/dialect-nvvm/tests/ops_test/carriers.rs
@@ -0,0 +1,923 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::types::MirPtrType;
+use dialect_nvvm::ops::{
+    AssertFailOp, CvtaGenericToSharedOffsetOp, VprintfOp, WgmmaMakeSmemDescOp, WgmmaMaxPendingAttr,
+    WgmmaMmaGroupM64N64K16F32Bf16Op, WgmmaMmaGroupValuesM64N64K8F32Tf32Op,
+    WgmmaMmaGroupValuesM64N64K16F32Bf16Op, WgmmaMmaGroupValuesM64N64K16F32F16Op,
+    WgmmaMmaGroupValuesM64N128K16F32Bf16Op, WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op,
+    WgmmaMmaLoopValuesM64N64K16F32Bf16Op, WgmmaMmaLoopValuesM64N64K16F32F16Op,
+    WgmmaMmaM64N64K8F32Tf32Op, WgmmaMmaM64N64K16F32Bf16Op, WgmmaMmaM64N64K16F32F16Op,
+    WgmmaMmaM64N128K16F32Bf16Op, WgmmaMmaPipelineValuesM64N64K16F32Bf16Op,
+};
+
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::types::{FP32Type, IntegerType, Signedness},
+    common_traits::Verify,
+    context::Context,
+    op::Op,
+    operation::Operation,
+};
+
+#[test]
+fn handwritten_ffi_and_wgmma_carriers_verify_exact_shapes() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let f32_ty = FP32Type::get(&ctx);
+    let pointer_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
+    let accumulator_pointer_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), true);
+    let global_pointer_ty = MirPtrType::get_global(&mut ctx, u8_ty.into(), false);
+    let mutable_global_pointer_ty = MirPtrType::get_global(&mut ctx, u8_ty.into(), true);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            pointer_ty.into(),
+            accumulator_pointer_ty.into(),
+            global_pointer_ty.into(),
+            mutable_global_pointer_ty.into(),
+            u32_ty.into(),
+            u64_ty.into(),
+            f32_ty.into(),
+        ],
+    );
+    let pointer = block.deref(&ctx).get_argument(0);
+    let accumulator_pointer = block.deref(&ctx).get_argument(1);
+    let global_pointer = block.deref(&ctx).get_argument(2);
+    let mutable_global_pointer = block.deref(&ctx).get_argument(3);
+    let u32_value = block.deref(&ctx).get_argument(4);
+    let u64_value = block.deref(&ctx).get_argument(5);
+    let f32_value = block.deref(&ctx).get_argument(6);
+
+    let vprintf = VprintfOp::build(&mut ctx, pointer, pointer);
+    assert!(VprintfOp::new(vprintf).verify(&ctx).is_ok());
+
+    let i64_signless_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let assertfail = AssertFailOp::build(&mut ctx, pointer, pointer, u32_value, pointer, u64_value);
+    assert!(AssertFailOp::new(assertfail).verify(&ctx).is_ok());
+    for (operands, results) in [
+        // message must be a MIR pointer
+        (
+            vec![u32_value, pointer, u32_value, pointer, u64_value],
+            vec![],
+        ),
+        // line must be a 32-bit integer
+        (
+            vec![pointer, pointer, u64_value, pointer, u64_value],
+            vec![],
+        ),
+        // char size must be a 64-bit integer
+        (
+            vec![pointer, pointer, u32_value, pointer, u32_value],
+            vec![],
+        ),
+        // wrong operand count
+        (vec![pointer, pointer, u32_value], vec![]),
+        // must have no results
+        (
+            vec![pointer, pointer, u32_value, pointer, u64_value],
+            vec![i64_signless_ty.into()],
+        ),
+    ] {
+        let invalid = Operation::new(
+            &mut ctx,
+            AssertFailOp::get_concrete_op_info(),
+            results,
+            operands,
+            vec![],
+            0,
+        );
+        assert!(AssertFailOp::new(invalid).verify(&ctx).is_err());
+    }
+    let bad_vprintf = Operation::new(
+        &mut ctx,
+        VprintfOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![pointer, u32_value],
+        vec![],
+        0,
+    );
+    assert!(VprintfOp::new(bad_vprintf).verify(&ctx).is_err());
+
+    let descriptor = Operation::new(
+        &mut ctx,
+        WgmmaMakeSmemDescOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![pointer],
+        vec![],
+        0,
+    );
+    assert!(WgmmaMakeSmemDescOp::new(descriptor).verify(&ctx).is_ok());
+    for (operands, results) in [
+        (vec![u32_value], vec![u64_ty.into()]),
+        (vec![global_pointer], vec![u64_ty.into()]),
+        (vec![pointer], vec![u32_ty.into()]),
+        (vec![], vec![u64_ty.into()]),
+    ] {
+        let invalid = Operation::new(
+            &mut ctx,
+            WgmmaMakeSmemDescOp::get_concrete_op_info(),
+            results,
+            operands,
+            vec![],
+            0,
+        );
+        assert!(WgmmaMakeSmemDescOp::new(invalid).verify(&ctx).is_err());
+    }
+
+    let cvta = Operation::new(
+        &mut ctx,
+        CvtaGenericToSharedOffsetOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![pointer],
+        vec![],
+        0,
+    );
+    assert!(CvtaGenericToSharedOffsetOp::new(cvta).verify(&ctx).is_ok());
+    for (operands, results) in [
+        // Operand must be a MIR pointer.
+        (vec![u32_value], vec![u64_ty.into()]),
+        // Operand must point to generic or shared memory.
+        (vec![global_pointer], vec![u64_ty.into()]),
+        // Result must be u64.
+        (vec![pointer], vec![u32_ty.into()]),
+        // Exact arity is required.
+        (vec![], vec![u64_ty.into()]),
+    ] {
+        let invalid = Operation::new(
+            &mut ctx,
+            CvtaGenericToSharedOffsetOp::get_concrete_op_info(),
+            results,
+            operands,
+            vec![],
+            0,
+        );
+        assert!(
+            CvtaGenericToSharedOffsetOp::new(invalid)
+                .verify(&ctx)
+                .is_err()
+        );
+    }
+
+    let mma = Operation::new(
+        &mut ctx,
+        WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![],
+        vec![accumulator_pointer, u64_value, u64_value],
+        vec![],
+        0,
+    );
+    assert!(WgmmaMmaM64N64K16F32Bf16Op::new(mma).verify(&ctx).is_ok());
+    for (operands, results) in [
+        // Accumulator must be mutable.
+        (vec![pointer, u64_value, u64_value], vec![]),
+        // Accumulator must use generic address space.
+        (vec![mutable_global_pointer, u64_value, u64_value], vec![]),
+        // Accumulator must be a MIR pointer.
+        (vec![u32_value, u64_value, u64_value], vec![]),
+        // Descriptors must be u64.
+        (vec![accumulator_pointer, u32_value, u64_value], vec![]),
+        // Exact arity is required.
+        (vec![accumulator_pointer, u64_value], vec![]),
+        // No results are permitted.
+        (
+            vec![accumulator_pointer, u64_value, u64_value],
+            vec![u32_ty.into()],
+        ),
+    ] {
+        let invalid = Operation::new(
+            &mut ctx,
+            WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
+            results,
+            operands,
+            vec![],
+            0,
+        );
+        assert!(
+            WgmmaMmaM64N64K16F32Bf16Op::new(invalid)
+                .verify(&ctx)
+                .is_err()
+        );
+    }
+
+    let group = WgmmaMmaGroupM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        accumulator_pointer,
+        vec![u64_value, u64_value, u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupM64N64K16F32Bf16Op::new(group)
+            .verify(&ctx)
+            .is_ok()
+    );
+    for (operands, results) in [
+        // Missing descriptor.
+        (vec![accumulator_pointer, u64_value], vec![]),
+        // Incomplete descriptor pair.
+        (
+            vec![accumulator_pointer, u64_value, u64_value, u64_value],
+            vec![],
+        ),
+        // Accumulator must be mutable.
+        (vec![pointer, u64_value, u64_value], vec![]),
+        // Accumulator must use generic address space.
+        (vec![mutable_global_pointer, u64_value, u64_value], vec![]),
+        // Accumulator must be a MIR pointer.
+        (vec![u32_value, u64_value, u64_value], vec![]),
+        // Descriptors must be u64.
+        (vec![accumulator_pointer, u64_value, u32_value], vec![]),
+        // No results are permitted.
+        (
+            vec![accumulator_pointer, u64_value, u64_value],
+            vec![u32_ty.into()],
+        ),
+    ] {
+        let invalid = Operation::new(
+            &mut ctx,
+            WgmmaMmaGroupM64N64K16F32Bf16Op::get_concrete_op_info(),
+            results,
+            operands,
+            vec![],
+            0,
+        );
+        assert!(
+            WgmmaMmaGroupM64N64K16F32Bf16Op::new(invalid)
+                .verify(&ctx)
+                .is_err()
+        );
+    }
+
+    let value_group = WgmmaMmaGroupValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        vec![u64_value, u64_value, u64_value, u64_value],
+    );
+    {
+        let value_group_ref = value_group.deref(&ctx);
+        assert_eq!(value_group_ref.get_num_operands(), 36);
+        assert_eq!(value_group_ref.get_num_results(), 32);
+    }
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(value_group)
+            .verify(&ctx)
+            .is_ok()
+    );
+
+    let too_few_accumulators = WgmmaMmaGroupValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 31],
+        vec![u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(too_few_accumulators)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let missing_descriptors =
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::build(&mut ctx, vec![f32_value; 32], vec![]);
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(missing_descriptors)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let incomplete_descriptor_pair = WgmmaMmaGroupValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        vec![u64_value, u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(incomplete_descriptor_pair)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let mut wrong_accumulator_operands = vec![f32_value; 32];
+    wrong_accumulator_operands[0] = u32_value;
+    wrong_accumulator_operands.extend([u64_value, u64_value]);
+    let wrong_accumulator = Operation::new(
+        &mut ctx,
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 32],
+        wrong_accumulator_operands,
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(wrong_accumulator)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let mut wrong_descriptor_operands = vec![f32_value; 32];
+    wrong_descriptor_operands.extend([u32_value, u64_value]);
+    let wrong_descriptor = Operation::new(
+        &mut ctx,
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 32],
+        wrong_descriptor_operands,
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(wrong_descriptor)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let mut valid_value_operands = vec![f32_value; 32];
+    valid_value_operands.extend([u64_value, u64_value]);
+
+    let wrong_result_count = Operation::new(
+        &mut ctx,
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 31],
+        valid_value_operands.clone(),
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(wrong_result_count)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let mut wrong_result_types = vec![f32_ty.into(); 32];
+    wrong_result_types[0] = u32_ty.into();
+    let wrong_result_type = Operation::new(
+        &mut ctx,
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
+        wrong_result_types,
+        valid_value_operands,
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32Bf16Op::new(wrong_result_type)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let wide_mma = Operation::new(
+        &mut ctx,
+        WgmmaMmaM64N128K16F32Bf16Op::get_concrete_op_info(),
+        vec![],
+        vec![accumulator_pointer, u64_value, u64_value],
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaM64N128K16F32Bf16Op::new(wide_mma)
+            .verify(&ctx)
+            .is_ok()
+    );
+
+    let wide_value_group = WgmmaMmaGroupValuesM64N128K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 64],
+        vec![u64_value, u64_value],
+    );
+    {
+        let group_ref = wide_value_group.deref(&ctx);
+        assert_eq!(group_ref.get_num_operands(), 66);
+        assert_eq!(group_ref.get_num_results(), 64);
+    }
+    assert!(
+        WgmmaMmaGroupValuesM64N128K16F32Bf16Op::new(wide_value_group)
+            .verify(&ctx)
+            .is_ok()
+    );
+
+    let wide_too_few = WgmmaMmaGroupValuesM64N128K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 63],
+        vec![u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N128K16F32Bf16Op::new(wide_too_few)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let wide_incomplete_pair = WgmmaMmaGroupValuesM64N128K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 64],
+        vec![u64_value, u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N128K16F32Bf16Op::new(wide_incomplete_pair)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let f16_mma = Operation::new(
+        &mut ctx,
+        WgmmaMmaM64N64K16F32F16Op::get_concrete_op_info(),
+        vec![],
+        vec![accumulator_pointer, u64_value, u64_value],
+        vec![],
+        0,
+    );
+    assert!(WgmmaMmaM64N64K16F32F16Op::new(f16_mma).verify(&ctx).is_ok());
+    for operands in [
+        vec![pointer, u64_value, u64_value],
+        vec![mutable_global_pointer, u64_value, u64_value],
+        vec![accumulator_pointer, u32_value, u64_value],
+    ] {
+        let invalid = Operation::new(
+            &mut ctx,
+            WgmmaMmaM64N64K16F32F16Op::get_concrete_op_info(),
+            vec![],
+            operands,
+            vec![],
+            0,
+        );
+        assert!(
+            WgmmaMmaM64N64K16F32F16Op::new(invalid)
+                .verify(&ctx)
+                .is_err()
+        );
+    }
+
+    let f16_value_group = WgmmaMmaGroupValuesM64N64K16F32F16Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        vec![u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32F16Op::new(f16_value_group)
+            .verify(&ctx)
+            .is_ok()
+    );
+
+    let f16_too_few_accumulators = WgmmaMmaGroupValuesM64N64K16F32F16Op::build(
+        &mut ctx,
+        vec![f32_value; 31],
+        vec![u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32F16Op::new(f16_too_few_accumulators)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let f16_incomplete_descriptor_pair = WgmmaMmaGroupValuesM64N64K16F32F16Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        vec![u64_value, u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32F16Op::new(f16_incomplete_descriptor_pair)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let mut f16_wrong_accumulator_operands = vec![f32_value; 32];
+    f16_wrong_accumulator_operands[0] = u32_value;
+    f16_wrong_accumulator_operands.extend([u64_value, u64_value]);
+    let f16_wrong_accumulator = Operation::new(
+        &mut ctx,
+        WgmmaMmaGroupValuesM64N64K16F32F16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 32],
+        f16_wrong_accumulator_operands,
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K16F32F16Op::new(f16_wrong_accumulator)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let tf32_mma = Operation::new(
+        &mut ctx,
+        WgmmaMmaM64N64K8F32Tf32Op::get_concrete_op_info(),
+        vec![],
+        vec![accumulator_pointer, u64_value, u64_value],
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaM64N64K8F32Tf32Op::new(tf32_mma)
+            .verify(&ctx)
+            .is_ok()
+    );
+    for operands in [
+        vec![pointer, u64_value, u64_value],
+        vec![mutable_global_pointer, u64_value, u64_value],
+        vec![accumulator_pointer, u32_value, u64_value],
+    ] {
+        let invalid = Operation::new(
+            &mut ctx,
+            WgmmaMmaM64N64K8F32Tf32Op::get_concrete_op_info(),
+            vec![],
+            operands,
+            vec![],
+            0,
+        );
+        assert!(
+            WgmmaMmaM64N64K8F32Tf32Op::new(invalid)
+                .verify(&ctx)
+                .is_err()
+        );
+    }
+
+    let tf32_value_group = WgmmaMmaGroupValuesM64N64K8F32Tf32Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        vec![u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K8F32Tf32Op::new(tf32_value_group)
+            .verify(&ctx)
+            .is_ok()
+    );
+
+    let tf32_too_few_accumulators = WgmmaMmaGroupValuesM64N64K8F32Tf32Op::build(
+        &mut ctx,
+        vec![f32_value; 31],
+        vec![u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K8F32Tf32Op::new(tf32_too_few_accumulators)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let tf32_incomplete_descriptor_pair = WgmmaMmaGroupValuesM64N64K8F32Tf32Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        vec![u64_value, u64_value, u64_value],
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K8F32Tf32Op::new(tf32_incomplete_descriptor_pair)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let mut tf32_wrong_accumulator_operands = vec![f32_value; 32];
+    tf32_wrong_accumulator_operands[0] = u32_value;
+    tf32_wrong_accumulator_operands.extend([u64_value, u64_value]);
+    let tf32_wrong_accumulator = Operation::new(
+        &mut ctx,
+        WgmmaMmaGroupValuesM64N64K8F32Tf32Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 32],
+        tf32_wrong_accumulator_operands,
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaGroupValuesM64N64K8F32Tf32Op::new(tf32_wrong_accumulator)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let loop_group = WgmmaMmaLoopValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        u64_value,
+        u64_value,
+        u64_value,
+        u64_value,
+        u64_value,
+    );
+    {
+        let loop_group_ref = loop_group.deref(&ctx);
+        assert_eq!(loop_group_ref.get_num_operands(), 37);
+        assert_eq!(loop_group_ref.get_num_results(), 32);
+    }
+    assert!(
+        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::new(loop_group)
+            .verify(&ctx)
+            .is_ok()
+    );
+
+    let f16_loop_group = WgmmaMmaLoopValuesM64N64K16F32F16Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        u64_value,
+        u64_value,
+        u64_value,
+        u64_value,
+        u64_value,
+    );
+    {
+        let loop_group_ref = f16_loop_group.deref(&ctx);
+        assert_eq!(loop_group_ref.get_num_operands(), 37);
+        assert_eq!(loop_group_ref.get_num_results(), 32);
+    }
+    assert!(
+        WgmmaMmaLoopValuesM64N64K16F32F16Op::new(f16_loop_group)
+            .verify(&ctx)
+            .is_ok()
+    );
+
+    let mut f16_wrong_loop_control_operands = vec![f32_value; 32];
+    f16_wrong_loop_control_operands.extend([u64_value, u64_value, u32_value, u64_value, u64_value]);
+    let f16_wrong_loop_control = Operation::new(
+        &mut ctx,
+        WgmmaMmaLoopValuesM64N64K16F32F16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 32],
+        f16_wrong_loop_control_operands,
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaLoopValuesM64N64K16F32F16Op::new(f16_wrong_loop_control)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let too_few_loop_accumulators = WgmmaMmaLoopValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 31],
+        u64_value,
+        u64_value,
+        u64_value,
+        u64_value,
+        u64_value,
+    );
+    assert!(
+        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::new(too_few_loop_accumulators)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let mut wrong_loop_control_operands = vec![f32_value; 32];
+    wrong_loop_control_operands.extend([u64_value, u64_value, u32_value, u64_value, u64_value]);
+    let wrong_loop_control = Operation::new(
+        &mut ctx,
+        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 32],
+        wrong_loop_control_operands,
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::new(wrong_loop_control)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let mut valid_loop_operands = vec![f32_value; 32];
+    valid_loop_operands.extend([u64_value; 5]);
+
+    let wrong_loop_result_count = Operation::new(
+        &mut ctx,
+        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 31],
+        valid_loop_operands.clone(),
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::new(wrong_loop_result_count)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let mut wrong_loop_result_types = vec![f32_ty.into(); 32];
+    wrong_loop_result_types[0] = u32_ty.into();
+    let wrong_loop_result_type = Operation::new(
+        &mut ctx,
+        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
+        wrong_loop_result_types,
+        valid_loop_operands,
+        vec![],
+        0,
+    );
+    assert!(
+        WgmmaMmaLoopValuesM64N64K16F32Bf16Op::new(wrong_loop_result_type)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let counted_pipeline_group = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 64],
+        vec![u64_value; 4],
+        vec![u64_value; 4],
+        u64_value,
+        1,
+    );
+    {
+        let counted_pipeline_ref = counted_pipeline_group.deref(&ctx);
+        assert_eq!(counted_pipeline_ref.get_num_operands(), 73);
+        assert_eq!(counted_pipeline_ref.get_num_results(), 64);
+    }
+    let counted_pipeline =
+        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(counted_pipeline_group);
+    assert_eq!(counted_pipeline.max_pending_groups(&ctx), Some(1));
+    assert!(counted_pipeline.verify(&ctx).is_ok());
+
+    let three_slot_counted_pipeline = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 96],
+        vec![u64_value; 6],
+        vec![u64_value; 6],
+        u64_value,
+        2,
+    );
+    {
+        let counted_pipeline_ref = three_slot_counted_pipeline.deref(&ctx);
+        assert_eq!(counted_pipeline_ref.get_num_operands(), 109);
+        assert_eq!(counted_pipeline_ref.get_num_results(), 96);
+    }
+    let three_slot_counted_pipeline =
+        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(three_slot_counted_pipeline);
+    assert_eq!(
+        three_slot_counted_pipeline.max_pending_groups(&ctx),
+        Some(2)
+    );
+    assert!(three_slot_counted_pipeline.verify(&ctx).is_ok());
+
+    let too_many_accumulators_for_wait_one = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 96],
+        vec![u64_value; 4],
+        vec![u64_value; 4],
+        u64_value,
+        1,
+    );
+    assert!(
+        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(too_many_accumulators_for_wait_one)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let too_few_accumulators_for_wait_two = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 64],
+        vec![u64_value; 6],
+        vec![u64_value; 6],
+        u64_value,
+        2,
+    );
+    assert!(
+        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(too_few_accumulators_for_wait_two)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let unsupported_wait_three = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 128],
+        vec![u64_value; 8],
+        vec![u64_value; 8],
+        u64_value,
+        3,
+    );
+    assert!(
+        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(unsupported_wait_three)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let wrong_counted_pipeline_control = WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 64],
+        vec![u64_value; 4],
+        vec![u64_value, u64_value, u32_value, u64_value],
+        u64_value,
+        1,
+    );
+    assert!(
+        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(wrong_counted_pipeline_control)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let mut valid_counted_pipeline_operands = vec![f32_value; 64];
+    valid_counted_pipeline_operands.extend([u64_value; 9]);
+    let wrong_counted_pipeline_result_count = Operation::new(
+        &mut ctx,
+        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 63],
+        valid_counted_pipeline_operands.clone(),
+        vec![],
+        0,
+    );
+    let wrong_counted_pipeline_result_count =
+        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(wrong_counted_pipeline_result_count);
+    wrong_counted_pipeline_result_count
+        .set_attr_counted_max_pending_groups(&ctx, WgmmaMaxPendingAttr(1));
+    assert!(wrong_counted_pipeline_result_count.verify(&ctx).is_err());
+
+    let mut wrong_counted_pipeline_result_types = vec![f32_ty.into(); 64];
+    wrong_counted_pipeline_result_types[0] = u32_ty.into();
+    let wrong_counted_pipeline_result_type = Operation::new(
+        &mut ctx,
+        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
+        wrong_counted_pipeline_result_types,
+        valid_counted_pipeline_operands,
+        vec![],
+        0,
+    );
+    let wrong_counted_pipeline_result_type =
+        WgmmaMmaLoopPipelineValuesM64N64K16F32Bf16Op::new(wrong_counted_pipeline_result_type);
+    wrong_counted_pipeline_result_type
+        .set_attr_counted_max_pending_groups(&ctx, WgmmaMaxPendingAttr(1));
+    assert!(wrong_counted_pipeline_result_type.verify(&ctx).is_err());
+
+    let pipeline_group = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 64],
+        vec![u64_value; 8],
+        1,
+    );
+    {
+        let pipeline_ref = pipeline_group.deref(&ctx);
+        assert_eq!(pipeline_ref.get_num_operands(), 72);
+        assert_eq!(pipeline_ref.get_num_results(), 64);
+    }
+    let pipeline = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::new(pipeline_group);
+    assert_eq!(pipeline.max_pending_groups(&ctx), Some(1));
+    assert!(pipeline.verify(&ctx).is_ok());
+
+    let too_few_pipeline_slots = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        vec![u64_value; 4],
+        1,
+    );
+    assert!(
+        WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::new(too_few_pipeline_slots)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    assert!(WgmmaMaxPendingAttr(1).verify(&ctx).is_ok());
+    assert!(WgmmaMaxPendingAttr(7).verify(&ctx).is_ok());
+    assert!(WgmmaMaxPendingAttr(0).verify(&ctx).is_err());
+    assert!(WgmmaMaxPendingAttr(8).verify(&ctx).is_err());
+
+    let zero_pending_pipeline = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        vec![u64_value; 2],
+        0,
+    );
+    let zero_pending_error = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::new(zero_pending_pipeline)
+        .verify(&ctx)
+        .unwrap_err();
+    assert!(
+        zero_pending_error
+            .err
+            .to_string()
+            .contains("nvvm.wgmma_max_pending_groups must be in 1..=7, got 0"),
+        "unexpected zero-pending error: {}",
+        zero_pending_error.err
+    );
+
+    let excess_pending_pipeline = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::build(
+        &mut ctx,
+        vec![f32_value; 32],
+        vec![u64_value; 2],
+        8,
+    );
+    let excess_pending_error =
+        WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::new(excess_pending_pipeline)
+            .verify(&ctx)
+            .unwrap_err();
+    assert!(
+        excess_pending_error
+            .err
+            .to_string()
+            .contains("nvvm.wgmma_max_pending_groups must be in 1..=7, got 8"),
+        "unexpected excess-pending error: {}",
+        excess_pending_error.err
+    );
+
+    let mut missing_attr_operands = vec![f32_value; 64];
+    missing_attr_operands.extend([u64_value; 8]);
+    let missing_attr_pipeline = Operation::new(
+        &mut ctx,
+        WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 64],
+        missing_attr_operands,
+        vec![],
+        0,
+    );
+    let missing_attr_error = WgmmaMmaPipelineValuesM64N64K16F32Bf16Op::new(missing_attr_pipeline)
+        .verify(&ctx)
+        .unwrap_err();
+    assert!(
+        missing_attr_error
+            .err
+            .to_string()
+            .contains("requires an nvvm.wgmma_max_pending_groups attribute"),
+        "unexpected missing-attribute error: {}",
+        missing_attr_error.err
+    );
+}
diff --git a/crates/dialect-nvvm/tests/ops_test/cluster_and_memory.rs b/crates/dialect-nvvm/tests/ops_test/cluster_and_memory.rs
new file mode 100644
index 0000000000..db490524aa
--- /dev/null
+++ b/crates/dialect-nvvm/tests/ops_test/cluster_and_memory.rs
@@ -0,0 +1,761 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::types::{MirPtrType, address_space};
+use dialect_nvvm::ops::{
+    ClusterBarrierModeAttr, ClusterBarrierOp, CpAsyncCa4Op, CpAsyncCaZfill4Op,
+    CpAsyncMbarrierArriveNoIncOp, CpAsyncMbarrierArriveNoIncSharedOp, CpAsyncMbarrierArriveOp,
+    CpAsyncMbarrierArriveSharedOp, CpAsyncWaitGroupOp, MbarrierArriveSharedOp,
+    MbarrierInitSharedOp, MbarrierInvalSharedOp, MbarrierTestWaitSharedOp, ReadPtxSregClusterIdxOp,
+    ReadPtxSregNclusterIdOp, ScalarArithmeticFormatAttr, ScalarArithmeticOp,
+    ScalarArithmeticOperationAttr, ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr,
+    ScalarArithmeticSubnormalAttr, ScalarConversionOp, ScalarConversionRoundingAttr,
+    ScalarConversionSaturationAttr, Tcgen05AllocOp, Tcgen05CommitMulticastCg2Op,
+    Tcgen05Ld16x32bx2X1RawOp, Tcgen05Ld16x256bPureOp, Tcgen05MmaF16Op,
+};
+
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::types::{FP32Type, FP64Type, IntegerType, Signedness},
+    common_traits::Verify,
+    context::Context,
+    op::{Op, verify_op},
+    operation::Operation,
+    r#type::Typed,
+};
+
+#[test]
+fn cluster_grid_compatibility_ops_keep_names_and_i32_shape() {
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::common_traits::Verify;
+    use pliron::context::Context;
+    use pliron::op::Op;
+    use pliron::operation::Operation;
+
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+    assert_eq!(
+        ReadPtxSregClusterIdxOp::get_opid_static().to_string(),
+        "nvvm.read_ptx_sreg_cluster_idx"
+    );
+    assert_eq!(
+        ReadPtxSregNclusterIdOp::get_opid_static().to_string(),
+        "nvvm.read_ptx_sreg_nclusterid"
+    );
+
+    let i32_type = IntegerType::get(&ctx, 32, Signedness::Signless);
+    for op_info in [
+        ReadPtxSregClusterIdxOp::get_concrete_op_info(),
+        ReadPtxSregNclusterIdOp::get_concrete_op_info(),
+    ] {
+        let op = Operation::new(&mut ctx, op_info, vec![i32_type.into()], vec![], vec![], 0);
+        assert!(op.deref(&ctx).verify(&ctx).is_ok());
+    }
+}
+
+#[test]
+fn mapa_shared_cluster_requires_and_preserves_raw_pointer_kind() {
+    use dialect_mir::types::{MirPointerKind, MirPtrType, address_space};
+    use dialect_nvvm::ops::MapaSharedClusterOp;
+    use pliron::{
+        basic_block::BasicBlock,
+        builtin::types::{IntegerType, Signedness},
+        common_traits::Verify,
+        context::Context,
+        op::Op,
+        operation::Operation,
+    };
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let raw_const_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), false, MirPointerKind::RawConst);
+    let raw_mut_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::RawMut);
+    let erased_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            raw_const_ty.into(),
+            raw_mut_ty.into(),
+            erased_ty.into(),
+            i32_ty.into(),
+        ],
+    );
+    let raw_const = block.deref(&ctx).get_argument(0);
+    let raw_mut = block.deref(&ctx).get_argument(1);
+    let erased = block.deref(&ctx).get_argument(2);
+    let rank = block.deref(&ctx).get_argument(3);
+
+    for (source, expected_kind) in [
+        (raw_const, MirPointerKind::RawConst),
+        (raw_mut, MirPointerKind::RawMut),
+    ] {
+        let operation = MapaSharedClusterOp::build(&mut ctx, source, rank);
+        let result_ty = operation.deref(&ctx).get_result(0).get_type(&ctx);
+        let result_ty = result_ty.deref(&ctx);
+        let result_ptr = result_ty
+            .downcast_ref::<MirPtrType>()
+            .expect("mapa result must be a MIR pointer");
+        assert_eq!(result_ptr.pointer_kind(), expected_kind);
+        assert_eq!(result_ptr.address_space(), address_space::CLUSTER_SHARED);
+        assert!(MapaSharedClusterOp::new(operation).verify(&ctx).is_ok());
+    }
+
+    let erased_result = MirPtrType::get_with_kind(
+        &mut ctx,
+        i32_ty.into(),
+        true,
+        address_space::CLUSTER_SHARED,
+        MirPointerKind::Erased,
+    );
+    let erasing = Operation::new(
+        &mut ctx,
+        MapaSharedClusterOp::get_concrete_op_info(),
+        vec![erased_result.into()],
+        vec![raw_mut, rank],
+        vec![],
+        0,
+    );
+    assert!(
+        MapaSharedClusterOp::new(erasing).verify(&ctx).is_err(),
+        "cluster address mapping must preserve the source raw-pointer kind"
+    );
+
+    let erased_source = MapaSharedClusterOp::build(&mut ctx, erased, rank);
+    assert!(
+        MapaSharedClusterOp::new(erased_source)
+            .verify(&ctx)
+            .is_err(),
+        "an Erased data/function carrier cannot enter the raw-pointer intrinsic ABI"
+    );
+
+    let invented_unique = MirPtrType::get_with_kind(
+        &mut ctx,
+        i32_ty.into(),
+        true,
+        address_space::CLUSTER_SHARED,
+        MirPointerKind::UniqueRef,
+    );
+    let laundering = Operation::new(
+        &mut ctx,
+        MapaSharedClusterOp::get_concrete_op_info(),
+        vec![invented_unique.into()],
+        vec![raw_mut, rank],
+        vec![],
+        0,
+    );
+    assert!(
+        MapaSharedClusterOp::new(laundering).verify(&ctx).is_err(),
+        "cluster address mapping must not turn RawMut into UniqueRef"
+    );
+
+    let invented_shared = MirPtrType::get_with_kind(
+        &mut ctx,
+        i32_ty.into(),
+        false,
+        address_space::CLUSTER_SHARED,
+        MirPointerKind::SharedRef,
+    );
+    let laundering = Operation::new(
+        &mut ctx,
+        MapaSharedClusterOp::get_concrete_op_info(),
+        vec![invented_shared.into()],
+        vec![raw_const, rank],
+        vec![],
+        0,
+    );
+    assert!(
+        MapaSharedClusterOp::new(laundering).verify(&ctx).is_err(),
+        "cluster address mapping must not turn RawConst into SharedRef"
+    );
+}
+
+#[test]
+fn generated_cluster_barrier_requires_one_closed_mode_and_no_values() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    for mode in [
+        ClusterBarrierModeAttr::Arrive,
+        ClusterBarrierModeAttr::ArriveAligned,
+        ClusterBarrierModeAttr::ArriveRelaxed,
+        ClusterBarrierModeAttr::ArriveRelaxedAligned,
+        ClusterBarrierModeAttr::Wait,
+        ClusterBarrierModeAttr::WaitAligned,
+    ] {
+        let op = ClusterBarrierOp::build(&mut ctx, mode);
+        assert!(verify_op(&ClusterBarrierOp::new(op), &ctx).is_ok());
+    }
+
+    let missing_mode = Operation::new(
+        &mut ctx,
+        ClusterBarrierOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ClusterBarrierOp::new(missing_mode), &ctx).is_err());
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let wrong_shape = Operation::new(
+        &mut ctx,
+        ClusterBarrierOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    ClusterBarrierOp::new(wrong_shape)
+        .set_attr_nvvm_cluster_barrier_mode(&ctx, ClusterBarrierModeAttr::Wait);
+    assert!(verify_op(&ClusterBarrierOp::new(wrong_shape), &ctx).is_err());
+}
+
+#[test]
+fn generated_scalar_conversion_accepts_only_reviewed_f32_to_i32_variants() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let f32_ty = FP32Type::get(&ctx);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let block = BasicBlock::new(&mut ctx, None, vec![f32_ty.into(), i32_ty.into()]);
+    let f32_value = block.deref(&ctx).get_argument(0);
+    let i32_value = block.deref(&ctx).get_argument(1);
+
+    for (rounding, saturation) in [
+        (
+            ScalarConversionRoundingAttr::NearestAway,
+            ScalarConversionSaturationAttr::None,
+        ),
+        (
+            ScalarConversionRoundingAttr::NearestAway,
+            ScalarConversionSaturationAttr::Satfinite,
+        ),
+        (
+            ScalarConversionRoundingAttr::NearestEven,
+            ScalarConversionSaturationAttr::None,
+        ),
+        (
+            ScalarConversionRoundingAttr::NearestEven,
+            ScalarConversionSaturationAttr::Relu,
+        ),
+        (
+            ScalarConversionRoundingAttr::NearestEven,
+            ScalarConversionSaturationAttr::Satfinite,
+        ),
+        (
+            ScalarConversionRoundingAttr::NearestEven,
+            ScalarConversionSaturationAttr::ReluSatfinite,
+        ),
+        (
+            ScalarConversionRoundingAttr::TowardZero,
+            ScalarConversionSaturationAttr::None,
+        ),
+        (
+            ScalarConversionRoundingAttr::TowardZero,
+            ScalarConversionSaturationAttr::Relu,
+        ),
+        (
+            ScalarConversionRoundingAttr::TowardZero,
+            ScalarConversionSaturationAttr::Satfinite,
+        ),
+        (
+            ScalarConversionRoundingAttr::TowardZero,
+            ScalarConversionSaturationAttr::ReluSatfinite,
+        ),
+    ] {
+        let op = ScalarConversionOp::build(&mut ctx, f32_value, rounding, saturation);
+        assert!(verify_op(&ScalarConversionOp::new(op), &ctx).is_ok());
+    }
+
+    let invalid_variant = ScalarConversionOp::build(
+        &mut ctx,
+        f32_value,
+        ScalarConversionRoundingAttr::NearestAway,
+        ScalarConversionSaturationAttr::Relu,
+    );
+    assert!(verify_op(&ScalarConversionOp::new(invalid_variant), &ctx).is_err());
+
+    let wrong_operand = Operation::new(
+        &mut ctx,
+        ScalarConversionOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![i32_value],
+        vec![],
+        0,
+    );
+    let wrong_operand = ScalarConversionOp::new(wrong_operand);
+    wrong_operand
+        .set_attr_nvvm_scalar_conversion_rounding(&ctx, ScalarConversionRoundingAttr::NearestEven);
+    wrong_operand
+        .set_attr_nvvm_scalar_conversion_saturation(&ctx, ScalarConversionSaturationAttr::None);
+    assert!(verify_op(&wrong_operand, &ctx).is_err());
+
+    let wrong_result = Operation::new(
+        &mut ctx,
+        ScalarConversionOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![f32_value],
+        vec![],
+        0,
+    );
+    let wrong_result = ScalarConversionOp::new(wrong_result);
+    wrong_result
+        .set_attr_nvvm_scalar_conversion_rounding(&ctx, ScalarConversionRoundingAttr::TowardZero);
+    wrong_result
+        .set_attr_nvvm_scalar_conversion_saturation(&ctx, ScalarConversionSaturationAttr::None);
+    assert!(verify_op(&wrong_result, &ctx).is_err());
+}
+
+#[test]
+fn generated_scalar_arithmetic_accepts_only_admitted_shapes_and_types() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let f32_ty = FP32Type::get(&ctx);
+    let f64_ty = FP64Type::get(&ctx);
+    let block = BasicBlock::new(&mut ctx, None, vec![f32_ty.into(), f64_ty.into()]);
+    let f32_value = block.deref(&ctx).get_argument(0);
+    let f64_value = block.deref(&ctx).get_argument(1);
+
+    let valid_f32 = ScalarArithmeticOp::build(
+        &mut ctx,
+        vec![f32_value, f32_value],
+        ScalarArithmeticFormatAttr::F32,
+        ScalarArithmeticOperationAttr::Mul,
+        ScalarArithmeticRoundingAttr::Rn,
+        ScalarArithmeticSubnormalAttr::Preserve,
+        ScalarArithmeticSaturationAttr::None,
+    );
+    assert!(verify_op(&ScalarArithmeticOp::new(valid_f32), &ctx).is_ok());
+
+    let valid_f64 = ScalarArithmeticOp::build(
+        &mut ctx,
+        vec![f64_value, f64_value, f64_value],
+        ScalarArithmeticFormatAttr::F64,
+        ScalarArithmeticOperationAttr::Fma,
+        ScalarArithmeticRoundingAttr::Rz,
+        ScalarArithmeticSubnormalAttr::Preserve,
+        ScalarArithmeticSaturationAttr::None,
+    );
+    assert!(verify_op(&ScalarArithmeticOp::new(valid_f64), &ctx).is_ok());
+
+    let valid_add = ScalarArithmeticOp::build(
+        &mut ctx,
+        vec![f32_value, f32_value],
+        ScalarArithmeticFormatAttr::F32,
+        ScalarArithmeticOperationAttr::Add,
+        ScalarArithmeticRoundingAttr::Rp,
+        ScalarArithmeticSubnormalAttr::Ftz,
+        ScalarArithmeticSaturationAttr::Sat,
+    );
+    assert!(verify_op(&ScalarArithmeticOp::new(valid_add), &ctx).is_ok());
+
+    let f64_ftz = ScalarArithmeticOp::build(
+        &mut ctx,
+        vec![f64_value, f64_value],
+        ScalarArithmeticFormatAttr::F64,
+        ScalarArithmeticOperationAttr::Mul,
+        ScalarArithmeticRoundingAttr::Rn,
+        ScalarArithmeticSubnormalAttr::Ftz,
+        ScalarArithmeticSaturationAttr::None,
+    );
+    assert!(verify_op(&ScalarArithmeticOp::new(f64_ftz), &ctx).is_err());
+
+    let wrong_arity = ScalarArithmeticOp::build(
+        &mut ctx,
+        vec![f32_value, f32_value],
+        ScalarArithmeticFormatAttr::F32,
+        ScalarArithmeticOperationAttr::Fma,
+        ScalarArithmeticRoundingAttr::Rn,
+        ScalarArithmeticSubnormalAttr::Preserve,
+        ScalarArithmeticSaturationAttr::None,
+    );
+    assert!(verify_op(&ScalarArithmeticOp::new(wrong_arity), &ctx).is_err());
+
+    let wrong_type = ScalarArithmeticOp::build(
+        &mut ctx,
+        vec![f32_value, f64_value],
+        ScalarArithmeticFormatAttr::F32,
+        ScalarArithmeticOperationAttr::Mul,
+        ScalarArithmeticRoundingAttr::Rn,
+        ScalarArithmeticSubnormalAttr::Preserve,
+        ScalarArithmeticSaturationAttr::None,
+    );
+    assert!(verify_op(&ScalarArithmeticOp::new(wrong_type), &ctx).is_err());
+
+    let missing_attrs = Operation::new(
+        &mut ctx,
+        ScalarArithmeticOp::get_concrete_op_info(),
+        vec![f32_ty.into()],
+        vec![f32_value, f32_value],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ScalarArithmeticOp::new(missing_attrs), &ctx).is_err());
+}
+
+#[test]
+fn test_generated_cp_async_accepts_pointer_shapes_and_both_constant_kinds() {
+    use dialect_mir::ops::MirConstantOp;
+    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let dst_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
+    let src_ty = MirPtrType::get(&mut ctx, u8_ty.into(), true, address_space::GLOBAL);
+    let wrong_dst_ty = MirPtrType::get(&mut ctx, u8_ty.into(), true, address_space::GLOBAL);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            dst_ty.into(),
+            src_ty.into(),
+            wrong_dst_ty.into(),
+            u32_ty.into(),
+        ],
+    );
+    let dst = block.deref(&ctx).get_argument(0);
+    let src = block.deref(&ctx).get_argument(1);
+    let wrong_dst = block.deref(&ctx).get_argument(2);
+    let dynamic = block.deref(&ctx).get_argument(3);
+
+    let copy = CpAsyncCa4Op::build(&mut ctx, dst, src);
+    assert!(verify_op(&CpAsyncCa4Op::new(copy), &ctx).is_ok());
+    let zfill = CpAsyncCaZfill4Op::build(&mut ctx, dst, src, dynamic);
+    assert!(verify_op(&CpAsyncCaZfill4Op::new(zfill), &ctx).is_ok());
+    let wrong_space = CpAsyncCa4Op::build(&mut ctx, wrong_dst, src);
+    assert!(verify_op(&CpAsyncCa4Op::new(wrong_space), &ctx).is_err());
+
+    let value = IntegerAttr::new(u32_ty, APInt::from_u32(0, NonZeroUsize::new(32).unwrap()));
+    let builtin = ConstantOp::new(&mut ctx, value.clone().into());
+    let builtin_value = builtin.get_operation().deref(&ctx).get_result(0);
+    let builtin_wait = CpAsyncWaitGroupOp::build(&mut ctx, builtin_value);
+    assert!(verify_op(&CpAsyncWaitGroupOp::new(builtin_wait), &ctx).is_ok());
+
+    let mir_constant = Operation::new(
+        &mut ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    MirConstantOp::new(mir_constant).set_attr_value(&ctx, value);
+    let mir_value = mir_constant.deref(&ctx).get_result(0);
+    let mir_wait = CpAsyncWaitGroupOp::build(&mut ctx, mir_value);
+    assert!(verify_op(&CpAsyncWaitGroupOp::new(mir_wait), &ctx).is_ok());
+
+    let dynamic_wait = CpAsyncWaitGroupOp::build(&mut ctx, dynamic);
+    assert!(verify_op(&CpAsyncWaitGroupOp::new(dynamic_wait), &ctx).is_err());
+}
+
+#[test]
+fn generated_tcgen05_verifies_carriers_and_half_split_constants() {
+    use dialect_mir::ops::MirConstantOp;
+    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let i16_ty = IntegerType::get(&ctx, 16, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let f32_ty = FP32Type::get(&ctx);
+    let pointer_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            pointer_ty.into(),
+            i1_ty.into(),
+            i16_ty.into(),
+            i32_ty.into(),
+            i64_ty.into(),
+            f32_ty.into(),
+        ],
+    );
+    let pointer = block.deref(&ctx).get_argument(0);
+    let predicate = block.deref(&ctx).get_argument(1);
+    let mask = block.deref(&ctx).get_argument(2);
+    let address = block.deref(&ctx).get_argument(3);
+    let dynamic_offset = block.deref(&ctx).get_argument(4);
+
+    let offset_attr = IntegerAttr::new(i64_ty, APInt::from_i64(16, NonZeroUsize::new(64).unwrap()));
+    let builtin_offset = ConstantOp::new(&mut ctx, offset_attr.clone().into())
+        .get_operation()
+        .deref(&ctx)
+        .get_result(0);
+    let mir_constant = Operation::new(
+        &mut ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    MirConstantOp::new(mir_constant).set_attr_value(&ctx, offset_attr);
+    let mir_offset = mir_constant.deref(&ctx).get_result(0);
+
+    for offset in [builtin_offset, mir_offset] {
+        let load = Operation::new(
+            &mut ctx,
+            Tcgen05Ld16x32bx2X1RawOp::get_concrete_op_info(),
+            vec![i32_ty.into()],
+            vec![address, offset],
+            vec![],
+            0,
+        );
+        assert!(verify_op(&Tcgen05Ld16x32bx2X1RawOp::new(load), &ctx).is_ok());
+    }
+
+    let dynamic = Operation::new(
+        &mut ctx,
+        Tcgen05Ld16x32bx2X1RawOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![address, dynamic_offset],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&Tcgen05Ld16x32bx2X1RawOp::new(dynamic), &ctx).is_err());
+
+    let wrong_offset_type = Operation::new(
+        &mut ctx,
+        Tcgen05Ld16x32bx2X1RawOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![address, address],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&Tcgen05Ld16x32bx2X1RawOp::new(wrong_offset_type), &ctx).is_err());
+
+    let wrong_result_type = Operation::new(
+        &mut ctx,
+        Tcgen05Ld16x32bx2X1RawOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![address, builtin_offset],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&Tcgen05Ld16x32bx2X1RawOp::new(wrong_result_type), &ctx).is_err());
+
+    let alloc = Operation::new(
+        &mut ctx,
+        Tcgen05AllocOp::get_concrete_op_info(),
+        vec![],
+        vec![pointer, address],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&Tcgen05AllocOp::new(alloc), &ctx).is_ok());
+
+    let multicast = Operation::new(
+        &mut ctx,
+        Tcgen05CommitMulticastCg2Op::get_concrete_op_info(),
+        vec![],
+        vec![pointer, mask],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&Tcgen05CommitMulticastCg2Op::new(multicast), &ctx).is_ok());
+
+    let mma = Operation::new(
+        &mut ctx,
+        Tcgen05MmaF16Op::get_concrete_op_info(),
+        vec![],
+        vec![address, dynamic_offset, dynamic_offset, address, predicate],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&Tcgen05MmaF16Op::new(mma), &ctx).is_ok());
+
+    let pure_load = Operation::new(
+        &mut ctx,
+        Tcgen05Ld16x256bPureOp::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        vec![address],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&Tcgen05Ld16x256bPureOp::new(pure_load), &ctx).is_ok());
+}
+
+#[test]
+fn generated_cp_async_mbarrier_requires_mutable_generic_or_shared_u64() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let generic_u64 = MirPtrType::get_generic(&mut ctx, u64_ty.into(), true);
+    let shared_u64 = MirPtrType::get_shared(&mut ctx, u64_ty.into(), true);
+    let global_u64 = MirPtrType::get_global(&mut ctx, u64_ty.into(), true);
+    let immutable_u64 = MirPtrType::get_generic(&mut ctx, u64_ty.into(), false);
+    let generic_u32 = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            generic_u64.into(),
+            shared_u64.into(),
+            global_u64.into(),
+            immutable_u64.into(),
+            generic_u32.into(),
+            u64_ty.into(),
+        ],
+    );
+    let generic = block.deref(&ctx).get_argument(0);
+    let shared = block.deref(&ctx).get_argument(1);
+    let global = block.deref(&ctx).get_argument(2);
+    let immutable = block.deref(&ctx).get_argument(3);
+    let wrong_pointee = block.deref(&ctx).get_argument(4);
+    let scalar = block.deref(&ctx).get_argument(5);
+
+    macro_rules! check_bridge {
+        ($op:ty) => {{
+            for barrier in [generic, shared] {
+                let valid = <$op>::build(&mut ctx, barrier);
+                assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
+            }
+            for barrier in [global, immutable, wrong_pointee, scalar] {
+                let invalid = <$op>::build(&mut ctx, barrier);
+                assert!(verify_op(&<$op>::new(invalid), &ctx).is_err());
+            }
+            let wrong_shape = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![u64_ty.into()],
+                vec![generic],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(wrong_shape), &ctx).is_err());
+        }};
+    }
+
+    check_bridge!(CpAsyncMbarrierArriveOp);
+    check_bridge!(CpAsyncMbarrierArriveSharedOp);
+    check_bridge!(CpAsyncMbarrierArriveNoIncOp);
+    check_bridge!(CpAsyncMbarrierArriveNoIncSharedOp);
+}
+
+#[test]
+fn generated_mbarrier_builders_and_verifiers_are_closed_over_their_shapes() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let u1_ty = IntegerType::get(&ctx, 1, Signedness::Unsigned);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let generic_ptr = MirPtrType::get_generic(&mut ctx, u64_ty.into(), false);
+    let shared_ptr = MirPtrType::get_shared(&mut ctx, u64_ty.into(), false);
+    let global_ptr = MirPtrType::get_global(&mut ctx, u64_ty.into(), false);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            generic_ptr.into(),
+            shared_ptr.into(),
+            global_ptr.into(),
+            i32_ty.into(),
+            u32_ty.into(),
+            u64_ty.into(),
+        ],
+    );
+    let generic = block.deref(&ctx).get_argument(0);
+    let shared = block.deref(&ctx).get_argument(1);
+    let global = block.deref(&ctx).get_argument(2);
+    let signless_i32 = block.deref(&ctx).get_argument(3);
+    let count = block.deref(&ctx).get_argument(4);
+    let token = block.deref(&ctx).get_argument(5);
+
+    for barrier in [generic, shared] {
+        let init = MbarrierInitSharedOp::build(&mut ctx, barrier, count);
+        assert!(MbarrierInitSharedOp::new(init).verify(&ctx).is_ok());
+        let arrive = MbarrierArriveSharedOp::build(&mut ctx, barrier);
+        assert!(MbarrierArriveSharedOp::new(arrive).verify(&ctx).is_ok());
+        let test_wait = MbarrierTestWaitSharedOp::build(&mut ctx, barrier, token);
+        assert!(
+            MbarrierTestWaitSharedOp::new(test_wait)
+                .verify(&ctx)
+                .is_ok()
+        );
+        let inval = MbarrierInvalSharedOp::build(&mut ctx, barrier);
+        assert!(MbarrierInvalSharedOp::new(inval).verify(&ctx).is_ok());
+    }
+
+    for barrier in [token, global] {
+        let inval = MbarrierInvalSharedOp::build(&mut ctx, barrier);
+        assert!(MbarrierInvalSharedOp::new(inval).verify(&ctx).is_err());
+    }
+
+    let bad_count = MbarrierInitSharedOp::build(&mut ctx, shared, signless_i32);
+    assert!(MbarrierInitSharedOp::new(bad_count).verify(&ctx).is_err());
+    let bad_arrive_result = Operation::new(
+        &mut ctx,
+        MbarrierArriveSharedOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![shared],
+        vec![],
+        0,
+    );
+    assert!(
+        MbarrierArriveSharedOp::new(bad_arrive_result)
+            .verify(&ctx)
+            .is_err()
+    );
+    let bad_token = MbarrierTestWaitSharedOp::build(&mut ctx, shared, count);
+    assert!(
+        MbarrierTestWaitSharedOp::new(bad_token)
+            .verify(&ctx)
+            .is_err()
+    );
+    let bad_predicate = Operation::new(
+        &mut ctx,
+        MbarrierTestWaitSharedOp::get_concrete_op_info(),
+        vec![u1_ty.into()],
+        vec![shared, token],
+        vec![],
+        0,
+    );
+    assert!(
+        MbarrierTestWaitSharedOp::new(bad_predicate)
+            .verify(&ctx)
+            .is_err()
+    );
+
+    let missing_operands = Operation::new(
+        &mut ctx,
+        MbarrierInitSharedOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(
+        MbarrierInitSharedOp::new(missing_operands)
+            .verify(&ctx)
+            .is_err()
+    );
+}
diff --git a/crates/dialect-nvvm/tests/ops_test/inline_ptx.rs b/crates/dialect-nvvm/tests/ops_test/inline_ptx.rs
new file mode 100644
index 0000000000..b11bf9866b
--- /dev/null
+++ b/crates/dialect-nvvm/tests/ops_test/inline_ptx.rs
@@ -0,0 +1,155 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::{
+    attributes::MirPointerKindAuthorityAttr,
+    types::{MirPointerKind, MirPtrType, MirTupleType},
+};
+use dialect_nvvm::ops::InlinePtxOp;
+
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::types::{IntegerType, Signedness},
+    context::Context,
+    op::verify_op,
+};
+
+#[test]
+fn test_inline_ptx_results_must_match_output_constraints() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let input = block.deref(&ctx).get_argument(0);
+
+    let void = InlinePtxOp::build(&mut ctx, vec![], vec![], "membar.gl;", "", true, false);
+    assert!(verify_op(&InlinePtxOp::new(void), &ctx).is_ok());
+
+    let single = InlinePtxOp::build(
+        &mut ctx,
+        vec![i32_ty.into()],
+        vec![input],
+        "add.u32 $0, $1, $1;",
+        "=r,r",
+        false,
+        false,
+    );
+    assert!(verify_op(&InlinePtxOp::new(single), &ctx).is_ok());
+
+    let multi = InlinePtxOp::build(
+        &mut ctx,
+        vec![i32_ty.into(), i32_ty.into()],
+        vec![input],
+        "add.u32 $0, $2, $2; mul.lo.u32 $1, $2, $2;",
+        "=r,=r,r",
+        false,
+        false,
+    );
+    assert!(verify_op(&InlinePtxOp::new(multi), &ctx).is_ok());
+
+    let missing_result = InlinePtxOp::build(
+        &mut ctx,
+        vec![i32_ty.into()],
+        vec![input],
+        "add.u32 $0, $2, $2; mul.lo.u32 $1, $2, $2;",
+        "=r,=r,r",
+        false,
+        false,
+    );
+    assert!(verify_op(&InlinePtxOp::new(missing_result), &ctx).is_err());
+
+    let extra_result = InlinePtxOp::build(
+        &mut ctx,
+        vec![i32_ty.into()],
+        vec![input],
+        "prefetch.global.L1 [$0];",
+        "r",
+        true,
+        false,
+    );
+    assert!(verify_op(&InlinePtxOp::new(extra_result), &ctx).is_err());
+}
+
+#[test]
+fn test_inline_ptx_pointer_results_require_exact_inline_asm_authority() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let unique_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
+    let erased_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::Erased);
+    let nested_erased_ty = MirTupleType::get(&mut ctx, vec![erased_ty.into()]);
+
+    let build = |ctx: &mut Context, result_ty| {
+        InlinePtxOp::build(
+            ctx,
+            vec![result_ty],
+            vec![],
+            "mov.u64 $0, 0;",
+            "=l",
+            false,
+            false,
+        )
+    };
+
+    for (name, result_ty) in [
+        ("UniqueRef", unique_ty.into()),
+        ("Erased", erased_ty.into()),
+        ("nested Erased", nested_erased_ty.into()),
+    ] {
+        let unmarked = InlinePtxOp::new(build(&mut ctx, result_ty));
+        let error = verify_op(&unmarked, &ctx).unwrap_err();
+        assert!(
+            error
+                .err
+                .to_string()
+                .contains("pointer-carrying results require InlineAsm pointer-kind authority"),
+            "unexpected unmarked {name} error: {}",
+            error.err
+        );
+
+        let marked = InlinePtxOp::new(build(&mut ctx, result_ty));
+        marked.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::InlineAsm);
+        assert!(
+            verify_op(&marked, &ctx).is_ok(),
+            "marked {name} pointer result should verify"
+        );
+    }
+
+    let wrong_authority = InlinePtxOp::new(build(&mut ctx, unique_ty.into()));
+    wrong_authority.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::RustCast);
+    let wrong_error = verify_op(&wrong_authority, &ctx).unwrap_err();
+    assert!(
+        wrong_error.err.to_string().contains("found RustCast"),
+        "unexpected wrong-authority error: {}",
+        wrong_error.err
+    );
+
+    let spurious = InlinePtxOp::new(build(&mut ctx, i32_ty.into()));
+    spurious.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::InlineAsm);
+    let spurious_error = verify_op(&spurious, &ctx).unwrap_err();
+    assert!(
+        spurious_error
+            .err
+            .to_string()
+            .contains("spurious for pointer-free results"),
+        "unexpected spurious-authority error: {}",
+        spurious_error.err
+    );
+}
+
+#[test]
+fn test_inline_ptx_count_output_constraints() {
+    assert_eq!(InlinePtxOp::count_output_constraints("=r,r,r"), 1);
+    assert_eq!(InlinePtxOp::count_output_constraints("=r,=r,=f,=d,r,l"), 4);
+    assert_eq!(InlinePtxOp::count_output_constraints("r,l,~{memory}"), 0);
+    assert_eq!(InlinePtxOp::count_output_constraints(""), 0);
+    // `=` only counts as an output marker at the start of a token.
+    assert_eq!(InlinePtxOp::count_output_constraints("r,r=f"), 0);
+}
diff --git a/crates/dialect-nvvm/tests/ops_test/main.rs b/crates/dialect-nvvm/tests/ops_test/main.rs
new file mode 100644
index 0000000000..2645507245
--- /dev/null
+++ b/crates/dialect-nvvm/tests/ops_test/main.rs
@@ -0,0 +1,16 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Tests build kinded fixture types directly; production minting lives in
+// mir-importer's facts.rs (see the workspace clippy.toml disallowed-methods).
+#![allow(clippy::disallowed_methods)]
+
+mod allowlist;
+mod atomics;
+mod carriers;
+mod cluster_and_memory;
+mod inline_ptx;
+mod matrix;
+mod thread_and_warp;
diff --git a/crates/dialect-nvvm/tests/ops_test/matrix.rs b/crates/dialect-nvvm/tests/ops_test/matrix.rs
new file mode 100644
index 0000000000..13aee19a73
--- /dev/null
+++ b/crates/dialect-nvvm/tests/ops_test/matrix.rs
@@ -0,0 +1,2278 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::types::{MirPtrType, address_space};
+use dialect_nvvm::ops::{
+    LdmatrixElementAttr, LdmatrixLayoutAttr, LdmatrixMultiplicityAttr, LdmatrixOp,
+    LdmatrixShapeAttr, LdmatrixStateSpaceAttr, LdmatrixX1Op, LdmatrixX1TransOp, LdmatrixX2Op,
+    LdmatrixX2TransOp, LdmatrixX4Op, LdmatrixX4TransOp, MmaM8N8K4F64Op, MmaM16N8K8F32Tf32Op,
+    MmaM16N8K16F32Bf16Op, MmaM16N8K16F32F16Op, MmaM16N8K32S32S8Op, MovmatrixTransB16Op,
+    RegisterMmaAccumulatorAttr, RegisterMmaElementAttr, RegisterMmaLayoutAttr, RegisterMmaOp,
+    RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr,
+    SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr,
+    SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr,
+    StmatrixM8n8X4Op,
+};
+
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::types::{FP32Type, FP64Type, IntegerType, Signedness},
+    common_traits::Verify,
+    context::Context,
+    op::{Op, verify_op},
+    operation::Operation,
+    r#type::Typed,
+};
+
+#[test]
+fn test_mma_m8n8k4_f64_requires_four_f64_operands_and_two_f64_results() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let f64_ty = FP64Type::get(&ctx);
+    let f32_ty = FP32Type::get(&ctx);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            f64_ty.into(),
+            f64_ty.into(),
+            f64_ty.into(),
+            f64_ty.into(),
+            f32_ty.into(),
+        ],
+    );
+    let f64_operands = (0..4)
+        .map(|index| block.deref(&ctx).get_argument(index))
+        .collect::<Vec<_>>();
+    let f32_value = block.deref(&ctx).get_argument(4);
+
+    let valid = Operation::new(
+        &mut ctx,
+        MmaM8N8K4F64Op::get_concrete_op_info(),
+        vec![f64_ty.into(), f64_ty.into()],
+        f64_operands.clone(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM8N8K4F64Op::new(valid), &ctx).is_ok());
+
+    let mut bad_operands = f64_operands.clone();
+    bad_operands[2] = f32_value;
+    let invalid_operand = Operation::new(
+        &mut ctx,
+        MmaM8N8K4F64Op::get_concrete_op_info(),
+        vec![f64_ty.into(), f64_ty.into()],
+        bad_operands,
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM8N8K4F64Op::new(invalid_operand), &ctx).is_err());
+
+    let invalid_result = Operation::new(
+        &mut ctx,
+        MmaM8N8K4F64Op::get_concrete_op_info(),
+        vec![f64_ty.into(), f32_ty.into()],
+        f64_operands,
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM8N8K4F64Op::new(invalid_result), &ctx).is_err());
+}
+
+#[test]
+fn test_movmatrix_requires_one_i32_operand_and_result() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let f32_ty = FP32Type::get(&ctx);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![i32_ty.into(), i64_ty.into(), f32_ty.into()],
+    );
+    let i32_value = block.deref(&ctx).get_argument(0);
+    let i64_value = block.deref(&ctx).get_argument(1);
+    let f32_value = block.deref(&ctx).get_argument(2);
+
+    let valid = Operation::new(
+        &mut ctx,
+        MovmatrixTransB16Op::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![i32_value],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MovmatrixTransB16Op::new(valid), &ctx).is_ok());
+
+    for (operand, result_type) in [
+        (i64_value, i32_ty.into()),
+        (f32_value, i32_ty.into()),
+        (i32_value, i64_ty.into()),
+        (i32_value, f32_ty.into()),
+    ] {
+        let invalid = Operation::new(
+            &mut ctx,
+            MovmatrixTransB16Op::get_concrete_op_info(),
+            vec![result_type],
+            vec![operand],
+            vec![],
+            0,
+        );
+        assert!(
+            verify_op(&MovmatrixTransB16Op::new(invalid), &ctx).is_err(),
+            "movmatrix must reject non-i32 carriers"
+        );
+    }
+}
+
+fn make_ldmatrix_x2(
+    ctx: &mut Context,
+    pointer: pliron::value::Value,
+    result_types: Vec<pliron::r#type::TypeHandle>,
+) -> LdmatrixOp {
+    let operation = Operation::new(
+        ctx,
+        LdmatrixOp::get_concrete_op_info(),
+        result_types,
+        vec![pointer],
+        vec![],
+        0,
+    );
+    let ldmatrix = LdmatrixOp::new(operation);
+    ldmatrix.set_attr_nvvm_ldmatrix_shape(ctx, LdmatrixShapeAttr::M8n8);
+    ldmatrix.set_attr_nvvm_ldmatrix_multiplicity(ctx, LdmatrixMultiplicityAttr::X2);
+    ldmatrix.set_attr_nvvm_ldmatrix_layout(ctx, LdmatrixLayoutAttr::Normal);
+    ldmatrix.set_attr_nvvm_ldmatrix_element(ctx, LdmatrixElementAttr::B16);
+    ldmatrix.set_attr_nvvm_ldmatrix_state_space(ctx, LdmatrixStateSpaceAttr::Shared);
+    ldmatrix
+}
+
+#[test]
+fn test_ldmatrix_accepts_only_generic_or_shared_u32_pointers() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let u16_ty = IntegerType::get(&ctx, 16, Signedness::Unsigned);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let pointer_types = [
+        MirPtrType::get_generic(&mut ctx, u32_ty.into(), false),
+        MirPtrType::get_shared(&mut ctx, u32_ty.into(), false),
+        MirPtrType::get_global(&mut ctx, u32_ty.into(), false),
+        MirPtrType::get_constant(&mut ctx, u32_ty.into(), false),
+        MirPtrType::get(&mut ctx, u32_ty.into(), false, address_space::LOCAL),
+        MirPtrType::get_generic(&mut ctx, u16_ty.into(), false),
+    ];
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        pointer_types
+            .iter()
+            .map(|pointer| (*pointer).into())
+            .collect(),
+    );
+
+    for index in 0..pointer_types.len() {
+        let pointer = block.deref(&ctx).get_argument(index);
+        let operation = make_ldmatrix_x2(&mut ctx, pointer, vec![u32_ty.into(), u32_ty.into()]);
+        let verified = verify_op(&operation, &ctx);
+        if index < 2 {
+            assert!(verified.is_ok(), "pointer case {index} should be accepted");
+        } else {
+            assert!(verified.is_err(), "pointer case {index} should be rejected");
+        }
+    }
+}
+
+#[test]
+fn generated_ldmatrix_verifier_rejects_zero_or_two_operands_without_panicking() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let pointer_ty = MirPtrType::get_shared(&mut ctx, u32_ty.into(), false);
+    let block = BasicBlock::new(&mut ctx, None, vec![pointer_ty.into(), pointer_ty.into()]);
+    let pointer0 = block.deref(&ctx).get_argument(0);
+    let pointer1 = block.deref(&ctx).get_argument(1);
+
+    let zero = Operation::new(
+        &mut ctx,
+        LdmatrixOp::get_concrete_op_info(),
+        vec![u32_ty.into(); 4],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(LdmatrixOp::new(zero).verify(&ctx).is_err());
+
+    let two = Operation::new(
+        &mut ctx,
+        LdmatrixOp::get_concrete_op_info(),
+        vec![u32_ty.into(); 4],
+        vec![pointer0, pointer1],
+        vec![],
+        0,
+    );
+    assert!(LdmatrixOp::new(two).verify(&ctx).is_err());
+
+    let valid = LdmatrixOp::build(
+        &mut ctx,
+        pointer0,
+        LdmatrixShapeAttr::M8n8,
+        LdmatrixMultiplicityAttr::X4,
+        LdmatrixLayoutAttr::Normal,
+        LdmatrixElementAttr::B16,
+        LdmatrixStateSpaceAttr::Shared,
+    );
+    assert!(LdmatrixOp::new(valid).verify(&ctx).is_ok());
+}
+
+#[test]
+fn blackwell_ldmatrix_verifier_accepts_only_reviewed_shapes() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let shared_u8 = MirPtrType::get_shared(&mut ctx, u8_ty.into(), false);
+    let generic_u8 = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
+    let global_u8 = MirPtrType::get_global(&mut ctx, u8_ty.into(), false);
+    let shared_u32 = MirPtrType::get_shared(&mut ctx, u32_ty.into(), false);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            shared_u8.into(),
+            generic_u8.into(),
+            global_u8.into(),
+            shared_u32.into(),
+        ],
+    );
+    let shared_pointer = block.deref(&ctx).get_argument(0);
+
+    for pointer_index in [0, 1] {
+        let pointer = block.deref(&ctx).get_argument(pointer_index);
+        for (shape, multiplicity, layout, element, result_count) in [
+            (
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8,
+                2,
+            ),
+            (
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8x16B4x16P64,
+                2,
+            ),
+            (
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8x16B6x16P32,
+                2,
+            ),
+            (
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8,
+                4,
+            ),
+            (
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8x16B4x16P64,
+                4,
+            ),
+            (
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8x16B6x16P32,
+                4,
+            ),
+            (
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B4x16P64,
+                1,
+            ),
+            (
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B6x16P32,
+                1,
+            ),
+            (
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B4x16P64,
+                2,
+            ),
+            (
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B6x16P32,
+                2,
+            ),
+            (
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X4,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B4x16P64,
+                4,
+            ),
+            (
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X4,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B6x16P32,
+                4,
+            ),
+        ] {
+            let op = LdmatrixOp::build(
+                &mut ctx,
+                pointer,
+                shape,
+                multiplicity,
+                layout,
+                element,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            assert_eq!(op.deref(&ctx).get_num_results(), result_count);
+            assert!(LdmatrixOp::new(op).verify(&ctx).is_ok());
+        }
+    }
+
+    for (shape, multiplicity, layout, element) in [
+        (
+            LdmatrixShapeAttr::M16n16,
+            LdmatrixMultiplicityAttr::X4,
+            LdmatrixLayoutAttr::Transposed,
+            LdmatrixElementAttr::B8,
+        ),
+        (
+            LdmatrixShapeAttr::M16n16,
+            LdmatrixMultiplicityAttr::X1,
+            LdmatrixLayoutAttr::Normal,
+            LdmatrixElementAttr::B8,
+        ),
+        (
+            LdmatrixShapeAttr::M8n16,
+            LdmatrixMultiplicityAttr::X1,
+            LdmatrixLayoutAttr::Transposed,
+            LdmatrixElementAttr::B8x16B4x16P64,
+        ),
+        (
+            LdmatrixShapeAttr::M8n16,
+            LdmatrixMultiplicityAttr::X1,
+            LdmatrixLayoutAttr::Normal,
+            LdmatrixElementAttr::B8,
+        ),
+    ] {
+        let op = LdmatrixOp::build(
+            &mut ctx,
+            shared_pointer,
+            shape,
+            multiplicity,
+            layout,
+            element,
+            LdmatrixStateSpaceAttr::Shared,
+        );
+        assert!(LdmatrixOp::new(op).verify(&ctx).is_err());
+    }
+
+    for pointer_index in [2, 3] {
+        let pointer = block.deref(&ctx).get_argument(pointer_index);
+        let op = LdmatrixOp::build(
+            &mut ctx,
+            pointer,
+            LdmatrixShapeAttr::M16n16,
+            LdmatrixMultiplicityAttr::X1,
+            LdmatrixLayoutAttr::Transposed,
+            LdmatrixElementAttr::B8,
+            LdmatrixStateSpaceAttr::Shared,
+        );
+        assert!(LdmatrixOp::new(op).verify(&ctx).is_err());
+    }
+}
+
+#[test]
+fn classic_ldmatrix_compatibility_ops_keep_names_and_register_shapes() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let pointer_ty = MirPtrType::get_shared(&mut ctx, u32_ty.into(), false);
+    let block = BasicBlock::new(&mut ctx, None, vec![pointer_ty.into()]);
+    let pointer = block.deref(&ctx).get_argument(0);
+
+    macro_rules! check_compat {
+        ($op:ty, $name:literal, $results:literal) => {{
+            assert_eq!(<$op>::get_opid_static().to_string(), $name);
+            let valid = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![u32_ty.into(); $results],
+                vec![pointer],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
+
+            let wrong_shape = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![u32_ty.into(); $results + 1],
+                vec![pointer],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(wrong_shape), &ctx).is_err());
+        }};
+    }
+
+    check_compat!(LdmatrixX1Op, "nvvm.ldmatrix_x1", 1);
+    check_compat!(LdmatrixX1TransOp, "nvvm.ldmatrix_x1_trans", 1);
+    check_compat!(LdmatrixX2Op, "nvvm.ldmatrix_x2", 2);
+    check_compat!(LdmatrixX2TransOp, "nvvm.ldmatrix_x2_trans", 2);
+    check_compat!(LdmatrixX4Op, "nvvm.ldmatrix_x4", 4);
+    check_compat!(LdmatrixX4TransOp, "nvvm.ldmatrix_x4_trans", 4);
+}
+
+#[test]
+fn test_mma_m16n8k16_bf16_verifies_exact_register_signature() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let f32_ty = FP32Type::get(&ctx);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![f32_ty.into(), i32_ty.into(), i64_ty.into()],
+    );
+    let f32_value = block.deref(&ctx).get_argument(0);
+    let i32_value = block.deref(&ctx).get_argument(1);
+    let i64_value = block.deref(&ctx).get_argument(2);
+
+    let valid_operands = (0..4)
+        .map(|_| f32_value)
+        .chain((0..6).map(|_| i32_value))
+        .collect();
+    let valid = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        valid_operands,
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32Bf16Op::new(valid), &ctx).is_ok());
+
+    let bad_c_operands = (0..4)
+        .map(|index| if index == 0 { i32_value } else { f32_value })
+        .chain((0..6).map(|_| i32_value))
+        .collect();
+    let bad_c = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        bad_c_operands,
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32Bf16Op::new(bad_c), &ctx).is_err());
+
+    let bad_a_operands = (0..4)
+        .map(|_| f32_value)
+        .chain((0..6).map(|index| if index == 0 { i64_value } else { i32_value }))
+        .collect();
+    let bad_a = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        bad_a_operands,
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32Bf16Op::new(bad_a), &ctx).is_err());
+
+    let bad_result = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(), f32_ty.into(), f32_ty.into(), i32_ty.into()],
+        (0..4)
+            .map(|_| f32_value)
+            .chain((0..6).map(|_| i32_value))
+            .collect(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32Bf16Op::new(bad_result), &ctx).is_err());
+
+    let bad_arity = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        (0..4)
+            .map(|_| f32_value)
+            .chain((0..5).map(|_| i32_value))
+            .collect(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32Bf16Op::new(bad_arity), &ctx).is_err());
+}
+
+#[test]
+fn test_mma_m16n8k16_f16_verifies_exact_register_signature() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let f32_ty = FP32Type::get(&ctx);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![f32_ty.into(), i32_ty.into(), i64_ty.into()],
+    );
+    let f32_value = block.deref(&ctx).get_argument(0);
+    let i32_value = block.deref(&ctx).get_argument(1);
+    let i64_value = block.deref(&ctx).get_argument(2);
+
+    let operands = || {
+        (0..4)
+            .map(|_| f32_value)
+            .chain((0..6).map(|_| i32_value))
+            .collect()
+    };
+    let valid = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32F16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        operands(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32F16Op::new(valid), &ctx).is_ok());
+
+    let bad_c_operands = (0..4)
+        .map(|index| if index == 0 { i32_value } else { f32_value })
+        .chain((0..6).map(|_| i32_value))
+        .collect();
+    let bad_c = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32F16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        bad_c_operands,
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32F16Op::new(bad_c), &ctx).is_err());
+
+    let bad_packed_operands = (0..4)
+        .map(|_| f32_value)
+        .chain((0..6).map(|index| if index == 0 { i64_value } else { i32_value }))
+        .collect();
+    let bad_packed = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32F16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        bad_packed_operands,
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32F16Op::new(bad_packed), &ctx).is_err());
+
+    let bad_result_type = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32F16Op::get_concrete_op_info(),
+        vec![f32_ty.into(), f32_ty.into(), f32_ty.into(), i32_ty.into()],
+        operands(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32F16Op::new(bad_result_type), &ctx).is_err());
+
+    let bad_operand_arity = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32F16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        (0..4)
+            .map(|_| f32_value)
+            .chain((0..5).map(|_| i32_value))
+            .collect(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32F16Op::new(bad_operand_arity), &ctx).is_err());
+
+    let bad_result_arity = Operation::new(
+        &mut ctx,
+        MmaM16N8K16F32F16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 3],
+        operands(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K16F32F16Op::new(bad_result_arity), &ctx).is_err());
+}
+
+#[test]
+fn test_mma_m16n8k8_tf32_verifies_exact_register_signature() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let f32_ty = FP32Type::get(&ctx);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![f32_ty.into(), i32_ty.into(), i64_ty.into()],
+    );
+    let f32_value = block.deref(&ctx).get_argument(0);
+    let i32_value = block.deref(&ctx).get_argument(1);
+    let i64_value = block.deref(&ctx).get_argument(2);
+
+    let operands = || {
+        (0..4)
+            .map(|_| f32_value)
+            .chain((0..6).map(|_| i32_value))
+            .collect()
+    };
+    let valid = Operation::new(
+        &mut ctx,
+        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        operands(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(valid), &ctx).is_ok());
+
+    let bad_c_operands = (0..4)
+        .map(|index| if index == 0 { i32_value } else { f32_value })
+        .chain((0..6).map(|_| i32_value))
+        .collect();
+    let bad_c = Operation::new(
+        &mut ctx,
+        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        bad_c_operands,
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(bad_c), &ctx).is_err());
+
+    let bad_packed_operands = (0..4)
+        .map(|_| f32_value)
+        .chain((0..6).map(|index| if index == 0 { i64_value } else { i32_value }))
+        .collect();
+    let bad_packed = Operation::new(
+        &mut ctx,
+        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        bad_packed_operands,
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(bad_packed), &ctx).is_err());
+
+    let bad_result_type = Operation::new(
+        &mut ctx,
+        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
+        vec![f32_ty.into(), f32_ty.into(), f32_ty.into(), i32_ty.into()],
+        operands(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(bad_result_type), &ctx).is_err());
+
+    let bad_operand_arity = Operation::new(
+        &mut ctx,
+        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        (0..4)
+            .map(|_| f32_value)
+            .chain((0..5).map(|_| i32_value))
+            .collect(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(bad_operand_arity), &ctx).is_err());
+
+    let bad_result_arity = Operation::new(
+        &mut ctx,
+        MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 3],
+        operands(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K8F32Tf32Op::new(bad_result_arity), &ctx).is_err());
+}
+
+#[test]
+fn test_mma_m16n8k32_s8_verifies_exact_register_signature() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let f32_ty = FP32Type::get(&ctx);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![i32_ty.into(), i64_ty.into(), f32_ty.into()],
+    );
+    let i32_value = block.deref(&ctx).get_argument(0);
+    let i64_value = block.deref(&ctx).get_argument(1);
+    let f32_value = block.deref(&ctx).get_argument(2);
+    let valid_operands = vec![i32_value; 10];
+
+    let valid = Operation::new(
+        &mut ctx,
+        MmaM16N8K32S32S8Op::get_concrete_op_info(),
+        vec![i32_ty.into(); 4],
+        valid_operands.clone(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K32S32S8Op::new(valid), &ctx).is_ok());
+
+    for bad_value in [i64_value, f32_value] {
+        let mut bad_operands = valid_operands.clone();
+        bad_operands[4] = bad_value;
+        let invalid = Operation::new(
+            &mut ctx,
+            MmaM16N8K32S32S8Op::get_concrete_op_info(),
+            vec![i32_ty.into(); 4],
+            bad_operands,
+            vec![],
+            0,
+        );
+        assert!(
+            verify_op(&MmaM16N8K32S32S8Op::new(invalid), &ctx).is_err(),
+            "MMA must reject non-i32 register operands"
+        );
+    }
+
+    for bad_results in [
+        vec![i32_ty.into(), i32_ty.into(), i32_ty.into(), i64_ty.into()],
+        vec![i32_ty.into(), i32_ty.into(), i32_ty.into(), f32_ty.into()],
+        vec![i32_ty.into(); 3],
+    ] {
+        let invalid = Operation::new(
+            &mut ctx,
+            MmaM16N8K32S32S8Op::get_concrete_op_info(),
+            bad_results,
+            valid_operands.clone(),
+            vec![],
+            0,
+        );
+        assert!(
+            verify_op(&MmaM16N8K32S32S8Op::new(invalid), &ctx).is_err(),
+            "MMA must reject the wrong result register signature"
+        );
+    }
+
+    let invalid_arity = Operation::new(
+        &mut ctx,
+        MmaM16N8K32S32S8Op::get_concrete_op_info(),
+        vec![i32_ty.into(); 4],
+        vec![i32_value; 9],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&MmaM16N8K32S32S8Op::new(invalid_arity), &ctx).is_err());
+}
+
+#[test]
+fn generated_register_mma_verifier_rejects_crossed_variants_and_carriers() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    macro_rules! set_variant {
+        ($op:expr, $shape:expr, $acc:expr, $a:expr, $b:expr, $overflow:expr) => {{
+            $op.set_attr_nvvm_register_mma_shape(&ctx, $shape);
+            $op.set_attr_nvvm_register_mma_accumulator(&ctx, $acc);
+            $op.set_attr_nvvm_register_mma_a_element(&ctx, $a);
+            $op.set_attr_nvvm_register_mma_b_element(&ctx, $b);
+            $op.set_attr_nvvm_register_mma_a_layout(&ctx, RegisterMmaLayoutAttr::Row);
+            $op.set_attr_nvvm_register_mma_b_layout(&ctx, RegisterMmaLayoutAttr::Col);
+            $op.set_attr_nvvm_register_mma_overflow(&ctx, $overflow);
+        }};
+    }
+
+    let f32_ty = FP32Type::get(&ctx);
+    let f64_ty = FP64Type::get(&ctx);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![f32_ty.into(), f64_ty.into(), i32_ty.into(), u32_ty.into()],
+    );
+    let f32_value = block.deref(&ctx).get_argument(0);
+    let f64_value = block.deref(&ctx).get_argument(1);
+    let i32_value = block.deref(&ctx).get_argument(2);
+    let u32_value = block.deref(&ctx).get_argument(3);
+
+    let bf16_operation = Operation::new(
+        &mut ctx,
+        RegisterMmaOp::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        [vec![f32_value; 4], vec![u32_value; 6]].concat(),
+        vec![],
+        0,
+    );
+    let bf16 = RegisterMmaOp::new(bf16_operation);
+    set_variant!(
+        bf16,
+        RegisterMmaShapeAttr::M16n8k16,
+        RegisterMmaAccumulatorAttr::F32,
+        RegisterMmaElementAttr::Bf16,
+        RegisterMmaElementAttr::Bf16,
+        RegisterMmaOverflowAttr::NotApplicable
+    );
+    assert!(bf16.get_attr_nvvm_register_mma_operation(&ctx).is_none());
+    assert!(verify_op(&bf16, &ctx).is_ok());
+    bf16.set_attr_nvvm_register_mma_b_element(&ctx, RegisterMmaElementAttr::F16);
+    assert!(verify_op(&bf16, &ctx).is_err());
+
+    let f64_operation = Operation::new(
+        &mut ctx,
+        RegisterMmaOp::get_concrete_op_info(),
+        vec![f64_ty.into(); 2],
+        vec![f64_value; 4],
+        vec![],
+        0,
+    );
+    let f64_mma = RegisterMmaOp::new(f64_operation);
+    set_variant!(
+        f64_mma,
+        RegisterMmaShapeAttr::M8n8k4,
+        RegisterMmaAccumulatorAttr::F64,
+        RegisterMmaElementAttr::F64,
+        RegisterMmaElementAttr::F64,
+        RegisterMmaOverflowAttr::NotApplicable
+    );
+    assert!(verify_op(&f64_mma, &ctx).is_ok());
+
+    let int_operands = [vec![i32_value; 4], vec![u32_value; 6]].concat();
+    let int_operation = Operation::new(
+        &mut ctx,
+        RegisterMmaOp::get_concrete_op_info(),
+        vec![i32_ty.into(); 4],
+        int_operands.clone(),
+        vec![],
+        0,
+    );
+    let int_mma = RegisterMmaOp::new(int_operation);
+    set_variant!(
+        int_mma,
+        RegisterMmaShapeAttr::M16n8k32,
+        RegisterMmaAccumulatorAttr::S32,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaOverflowAttr::Wrapping
+    );
+    assert!(verify_op(&int_mma, &ctx).is_ok());
+
+    let wrong_signedness = Operation::new(
+        &mut ctx,
+        RegisterMmaOp::get_concrete_op_info(),
+        vec![signless_i32_ty.into(); 4],
+        int_operands,
+        vec![],
+        0,
+    );
+    let wrong_signedness = RegisterMmaOp::new(wrong_signedness);
+    set_variant!(
+        wrong_signedness,
+        RegisterMmaShapeAttr::M16n8k32,
+        RegisterMmaAccumulatorAttr::S32,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaOverflowAttr::Wrapping
+    );
+    assert!(verify_op(&wrong_signedness, &ctx).is_err());
+
+    let missing_attributes = Operation::new(
+        &mut ctx,
+        RegisterMmaOp::get_concrete_op_info(),
+        vec![f64_ty.into(); 2],
+        vec![f64_value; 4],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&RegisterMmaOp::new(missing_attributes), &ctx).is_err());
+}
+
+#[test]
+fn generated_register_mma_verifies_dense_integer_families() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![i32_ty.into(), u32_ty.into(), signless_i32_ty.into()],
+    );
+    let i32_value = block.deref(&ctx).get_argument(0);
+    let u32_value = block.deref(&ctx).get_argument(1);
+
+    macro_rules! int_mma {
+        ($shape:expr, $a:expr, $b:expr, $overflow:expr, $operands:expr, $results:expr) => {{
+            let operation = Operation::new(
+                &mut ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                $results,
+                $operands,
+                vec![],
+                0,
+            );
+            let mma = RegisterMmaOp::new(operation);
+            mma.set_attr_nvvm_register_mma_shape(&ctx, $shape);
+            mma.set_attr_nvvm_register_mma_operation(&ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_accumulator(&ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(&ctx, $a);
+            mma.set_attr_nvvm_register_mma_b_element(&ctx, $b);
+            mma.set_attr_nvvm_register_mma_a_layout(&ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(&ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(&ctx, $overflow);
+            mma
+        }};
+    }
+
+    let mut accepted = 0;
+    for (shape, accumulator_count, operand_count, result_count) in [
+        (RegisterMmaShapeAttr::M8n8k16, 2, 4, 2),
+        (RegisterMmaShapeAttr::M16n8k16, 4, 7, 4),
+        (RegisterMmaShapeAttr::M16n8k32, 4, 10, 4),
+    ] {
+        for (a_element, b_element) in [
+            (RegisterMmaElementAttr::S8, RegisterMmaElementAttr::S8),
+            (RegisterMmaElementAttr::S8, RegisterMmaElementAttr::U8),
+            (RegisterMmaElementAttr::U8, RegisterMmaElementAttr::S8),
+            (RegisterMmaElementAttr::U8, RegisterMmaElementAttr::U8),
+        ] {
+            for overflow in [
+                RegisterMmaOverflowAttr::Wrapping,
+                RegisterMmaOverflowAttr::Satfinite,
+            ] {
+                let operands = [
+                    vec![i32_value; accumulator_count],
+                    vec![u32_value; operand_count - accumulator_count],
+                ]
+                .concat();
+                let mma = int_mma!(
+                    shape.clone(),
+                    a_element.clone(),
+                    b_element.clone(),
+                    overflow.clone(),
+                    operands,
+                    vec![i32_ty.into(); result_count]
+                );
+                assert_eq!(
+                    mma.get_operation().deref(&ctx).get_num_operands(),
+                    operand_count
+                );
+                assert_eq!(
+                    mma.get_operation().deref(&ctx).get_num_results(),
+                    result_count
+                );
+                assert!(
+                    verify_op(&mma, &ctx).is_ok(),
+                    "rejected {shape:?} {a_element:?}x{b_element:?} {overflow:?}"
+                );
+                accepted += 1;
+            }
+        }
+    }
+    assert_eq!(accepted, 24);
+
+    let mut int4_accepted = 0;
+    for (shape, accumulator_count, a_count, b_count, result_count) in [
+        (RegisterMmaShapeAttr::M8n8k32, 2, 1, 1, 2),
+        (RegisterMmaShapeAttr::M16n8k32, 4, 2, 1, 4),
+        (RegisterMmaShapeAttr::M16n8k64, 4, 4, 2, 4),
+    ] {
+        for (a_element, b_element) in [
+            (RegisterMmaElementAttr::S4, RegisterMmaElementAttr::S4),
+            (RegisterMmaElementAttr::S4, RegisterMmaElementAttr::U4),
+            (RegisterMmaElementAttr::U4, RegisterMmaElementAttr::S4),
+            (RegisterMmaElementAttr::U4, RegisterMmaElementAttr::U4),
+        ] {
+            for overflow in [
+                RegisterMmaOverflowAttr::Wrapping,
+                RegisterMmaOverflowAttr::Satfinite,
+            ] {
+                let operands = [
+                    vec![i32_value; accumulator_count],
+                    vec![u32_value; a_count],
+                    vec![u32_value; b_count],
+                ]
+                .concat();
+                let expected_operand_types = [
+                    vec![i32_ty.into(); accumulator_count],
+                    vec![u32_ty.into(); a_count],
+                    vec![u32_ty.into(); b_count],
+                ]
+                .concat();
+                let mma = int_mma!(
+                    shape.clone(),
+                    a_element.clone(),
+                    b_element.clone(),
+                    overflow.clone(),
+                    operands,
+                    vec![i32_ty.into(); result_count]
+                );
+                let operation = mma.get_operation().deref(&ctx);
+                assert_eq!(
+                    operation.get_num_operands(),
+                    accumulator_count + a_count + b_count
+                );
+                assert_eq!(operation.get_num_results(), result_count);
+                assert_eq!(
+                    operation
+                        .operands()
+                        .map(|operand| operand.get_type(&ctx))
+                        .collect::<Vec<_>>(),
+                    expected_operand_types
+                );
+                assert_eq!(
+                    (0..operation.get_num_results())
+                        .map(|index| operation.get_result(index).get_type(&ctx))
+                        .collect::<Vec<_>>(),
+                    vec![i32_ty.into(); result_count]
+                );
+                assert_eq!(
+                    mma.get_attr_nvvm_register_mma_shape(&ctx).as_deref(),
+                    Some(&shape)
+                );
+                assert_eq!(
+                    mma.get_attr_nvvm_register_mma_accumulator(&ctx).as_deref(),
+                    Some(&RegisterMmaAccumulatorAttr::S32)
+                );
+                assert_eq!(
+                    mma.get_attr_nvvm_register_mma_a_element(&ctx).as_deref(),
+                    Some(&a_element)
+                );
+                assert_eq!(
+                    mma.get_attr_nvvm_register_mma_b_element(&ctx).as_deref(),
+                    Some(&b_element)
+                );
+                assert_eq!(
+                    mma.get_attr_nvvm_register_mma_a_layout(&ctx).as_deref(),
+                    Some(&RegisterMmaLayoutAttr::Row)
+                );
+                assert_eq!(
+                    mma.get_attr_nvvm_register_mma_b_layout(&ctx).as_deref(),
+                    Some(&RegisterMmaLayoutAttr::Col)
+                );
+                assert_eq!(
+                    mma.get_attr_nvvm_register_mma_overflow(&ctx).as_deref(),
+                    Some(&overflow)
+                );
+                assert!(
+                    verify_op(&mma, &ctx).is_ok(),
+                    "rejected {shape:?} {a_element:?}x{b_element:?} {overflow:?}"
+                );
+                int4_accepted += 1;
+            }
+        }
+    }
+    assert_eq!(int4_accepted, 24);
+
+    for (shape, accumulator_count, operand_count, result_count) in [
+        (RegisterMmaShapeAttr::M8n8k32, 2, 4, 2),
+        (RegisterMmaShapeAttr::M16n8k32, 4, 7, 4),
+        (RegisterMmaShapeAttr::M16n8k64, 4, 10, 4),
+    ] {
+        for wrong_operand_count in [operand_count - 1, operand_count + 1] {
+            let mma = int_mma!(
+                shape.clone(),
+                RegisterMmaElementAttr::S4,
+                RegisterMmaElementAttr::U4,
+                RegisterMmaOverflowAttr::Wrapping,
+                [
+                    vec![i32_value; accumulator_count],
+                    vec![u32_value; wrong_operand_count - accumulator_count],
+                ]
+                .concat(),
+                vec![i32_ty.into(); result_count]
+            );
+            assert!(verify_op(&mma, &ctx).is_err());
+        }
+
+        for wrong_result_count in [result_count - 1, result_count + 1] {
+            let mma = int_mma!(
+                shape.clone(),
+                RegisterMmaElementAttr::U4,
+                RegisterMmaElementAttr::S4,
+                RegisterMmaOverflowAttr::Satfinite,
+                [
+                    vec![i32_value; accumulator_count],
+                    vec![u32_value; operand_count - accumulator_count],
+                ]
+                .concat(),
+                vec![i32_ty.into(); wrong_result_count]
+            );
+            assert!(verify_op(&mma, &ctx).is_err());
+        }
+    }
+
+    let int4_on_int8_shape = int_mma!(
+        RegisterMmaShapeAttr::M8n8k16,
+        RegisterMmaElementAttr::S4,
+        RegisterMmaElementAttr::U4,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
+        vec![i32_ty.into(); 2]
+    );
+    assert!(verify_op(&int4_on_int8_shape, &ctx).is_err());
+
+    let int8_on_int4_shape = int_mma!(
+        RegisterMmaShapeAttr::M8n8k32,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
+        vec![i32_ty.into(); 2]
+    );
+    assert!(verify_op(&int8_on_int4_shape, &ctx).is_err());
+
+    let crossed_integer_width = int_mma!(
+        RegisterMmaShapeAttr::M16n8k32,
+        RegisterMmaElementAttr::S4,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaOverflowAttr::Satfinite,
+        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&crossed_integer_width, &ctx).is_err());
+
+    let m16k32_int4_with_int8_carriers = int_mma!(
+        RegisterMmaShapeAttr::M16n8k32,
+        RegisterMmaElementAttr::U4,
+        RegisterMmaElementAttr::S4,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 4], vec![u32_value; 6]].concat(),
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&m16k32_int4_with_int8_carriers, &ctx).is_err());
+
+    let m16k32_int8_with_int4_carriers = int_mma!(
+        RegisterMmaShapeAttr::M16n8k32,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaOverflowAttr::Satfinite,
+        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&m16k32_int8_with_int4_carriers, &ctx).is_err());
+
+    let m16k64_int4_with_k32_carriers = int_mma!(
+        RegisterMmaShapeAttr::M16n8k64,
+        RegisterMmaElementAttr::S4,
+        RegisterMmaElementAttr::U4,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&m16k64_int4_with_k32_carriers, &ctx).is_err());
+
+    let m16k32_int4_with_k64_carriers = int_mma!(
+        RegisterMmaShapeAttr::M16n8k32,
+        RegisterMmaElementAttr::U4,
+        RegisterMmaElementAttr::S4,
+        RegisterMmaOverflowAttr::Satfinite,
+        [vec![i32_value; 4], vec![u32_value; 6]].concat(),
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&m16k32_int4_with_k64_carriers, &ctx).is_err());
+
+    let int8_on_m16k64_shape = int_mma!(
+        RegisterMmaShapeAttr::M16n8k64,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 4], vec![u32_value; 6]].concat(),
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&int8_on_m16k64_shape, &ctx).is_err());
+
+    for (shape, accumulator_count, operand_count, result_count) in [
+        (RegisterMmaShapeAttr::M8n8k16, 2, 4, 2),
+        (RegisterMmaShapeAttr::M16n8k16, 4, 7, 4),
+        (RegisterMmaShapeAttr::M16n8k32, 4, 10, 4),
+    ] {
+        for wrong_count in [operand_count - 1, operand_count + 1] {
+            let operands = [
+                vec![i32_value; accumulator_count],
+                vec![u32_value; wrong_count - accumulator_count],
+            ]
+            .concat();
+            let mma = int_mma!(
+                shape.clone(),
+                RegisterMmaElementAttr::S8,
+                RegisterMmaElementAttr::U8,
+                RegisterMmaOverflowAttr::Wrapping,
+                operands,
+                vec![i32_ty.into(); result_count]
+            );
+            assert!(verify_op(&mma, &ctx).is_err());
+        }
+    }
+
+    let m8_wrong_result_signedness = int_mma!(
+        RegisterMmaShapeAttr::M8n8k16,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
+        vec![signless_i32_ty.into(); 2]
+    );
+    assert!(verify_op(&m8_wrong_result_signedness, &ctx).is_err());
+
+    let m8_wrong_accumulator_signedness = int_mma!(
+        RegisterMmaShapeAttr::M8n8k16,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaOverflowAttr::Wrapping,
+        vec![u32_value; 4],
+        vec![i32_ty.into(); 2]
+    );
+    assert!(verify_op(&m8_wrong_accumulator_signedness, &ctx).is_err());
+
+    let m8_wrong_fragment_signedness = int_mma!(
+        RegisterMmaShapeAttr::M8n8k16,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaOverflowAttr::Satfinite,
+        vec![i32_value; 4],
+        vec![i32_ty.into(); 2]
+    );
+    assert!(verify_op(&m8_wrong_fragment_signedness, &ctx).is_err());
+
+    let m8_crossed_element = int_mma!(
+        RegisterMmaShapeAttr::M8n8k16,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::F16,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
+        vec![i32_ty.into(); 2]
+    );
+    assert!(verify_op(&m8_crossed_element, &ctx).is_err());
+
+    let m8_crossed_overflow = int_mma!(
+        RegisterMmaShapeAttr::M8n8k16,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaOverflowAttr::NotApplicable,
+        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
+        vec![i32_ty.into(); 2]
+    );
+    assert!(verify_op(&m8_crossed_overflow, &ctx).is_err());
+
+    let m8_crossed_carrier_shape = int_mma!(
+        RegisterMmaShapeAttr::M8n8k16,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&m8_crossed_carrier_shape, &ctx).is_err());
+
+    let m8_crossed_shape = int_mma!(
+        RegisterMmaShapeAttr::M8n8k4,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 2], vec![u32_value; 2]].concat(),
+        vec![i32_ty.into(); 2]
+    );
+    assert!(verify_op(&m8_crossed_shape, &ctx).is_err());
+
+    let wrong_result_signedness = int_mma!(
+        RegisterMmaShapeAttr::M16n8k16,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
+        vec![signless_i32_ty.into(); 4]
+    );
+    assert!(verify_op(&wrong_result_signedness, &ctx).is_err());
+
+    let wrong_accumulator_signedness = int_mma!(
+        RegisterMmaShapeAttr::M16n8k16,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaOverflowAttr::Wrapping,
+        vec![u32_value; 7],
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&wrong_accumulator_signedness, &ctx).is_err());
+
+    let wrong_fragment_signedness = int_mma!(
+        RegisterMmaShapeAttr::M16n8k32,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaOverflowAttr::Satfinite,
+        vec![i32_value; 10],
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&wrong_fragment_signedness, &ctx).is_err());
+
+    let crossed_element = int_mma!(
+        RegisterMmaShapeAttr::M16n8k16,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::F16,
+        RegisterMmaOverflowAttr::Wrapping,
+        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&crossed_element, &ctx).is_err());
+
+    let crossed_overflow = int_mma!(
+        RegisterMmaShapeAttr::M16n8k32,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaElementAttr::U8,
+        RegisterMmaOverflowAttr::NotApplicable,
+        [vec![i32_value; 4], vec![u32_value; 6]].concat(),
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&crossed_overflow, &ctx).is_err());
+
+    let crossed_shape = int_mma!(
+        RegisterMmaShapeAttr::M16n8k8,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaElementAttr::S8,
+        RegisterMmaOverflowAttr::Satfinite,
+        [vec![i32_value; 4], vec![u32_value; 3]].concat(),
+        vec![i32_ty.into(); 4]
+    );
+    assert!(verify_op(&crossed_shape, &ctx).is_err());
+}
+
+#[test]
+fn generated_register_mma_verifies_dense_b1_families() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    fn b1_mma(
+        ctx: &mut Context,
+        shape: RegisterMmaShapeAttr,
+        operation: Option<RegisterMmaOperationAttr>,
+    ) -> RegisterMmaOp {
+        let (accumulator_count, a_count, b_count, result_count) = match shape {
+            RegisterMmaShapeAttr::M8n8k128 => (2, 1, 1, 2),
+            RegisterMmaShapeAttr::M16n8k128 => (4, 2, 1, 4),
+            RegisterMmaShapeAttr::M16n8k256 => (4, 4, 2, 4),
+            _ => panic!("unsupported B1 MMA shape"),
+        };
+        let i32_ty = IntegerType::get(ctx, 32, Signedness::Signed);
+        let u32_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
+        let argument_types = (0..accumulator_count)
+            .map(|_| i32_ty.into())
+            .chain((0..a_count + b_count).map(|_| u32_ty.into()))
+            .collect();
+        let block = BasicBlock::new(ctx, None, argument_types);
+        let operands = (0..accumulator_count + a_count + b_count)
+            .map(|index| block.deref(ctx).get_argument(index))
+            .collect();
+        let op = Operation::new(
+            ctx,
+            RegisterMmaOp::get_concrete_op_info(),
+            vec![i32_ty.into(); result_count],
+            operands,
+            vec![],
+            0,
+        );
+        let mma = RegisterMmaOp::new(op);
+        mma.set_attr_nvvm_register_mma_shape(ctx, shape);
+        if let Some(operation) = operation {
+            mma.set_attr_nvvm_register_mma_operation(ctx, operation);
+        }
+        mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+        mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
+        mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
+        mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+        mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+        mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+        mma
+    }
+
+    let mut accepted = 0;
+    for shape in [
+        RegisterMmaShapeAttr::M8n8k128,
+        RegisterMmaShapeAttr::M16n8k128,
+        RegisterMmaShapeAttr::M16n8k256,
+    ] {
+        for operation in [
+            RegisterMmaOperationAttr::XorPopc,
+            RegisterMmaOperationAttr::AndPopc,
+        ] {
+            let mma = b1_mma(&mut ctx, shape.clone(), Some(operation));
+            assert!(verify_op(&mma, &ctx).is_ok(), "rejected {shape:?}");
+            accepted += 1;
+        }
+    }
+    assert_eq!(accepted, 6);
+
+    let multiply = b1_mma(
+        &mut ctx,
+        RegisterMmaShapeAttr::M8n8k128,
+        Some(RegisterMmaOperationAttr::Multiply),
+    );
+    assert!(verify_op(&multiply, &ctx).is_err());
+
+    let wrong_shape = b1_mma(
+        &mut ctx,
+        RegisterMmaShapeAttr::M16n8k128,
+        Some(RegisterMmaOperationAttr::XorPopc),
+    );
+    wrong_shape.set_attr_nvvm_register_mma_shape(&ctx, RegisterMmaShapeAttr::M16n8k64);
+    assert!(verify_op(&wrong_shape, &ctx).is_err());
+
+    let missing_operation = b1_mma(&mut ctx, RegisterMmaShapeAttr::M8n8k128, None);
+    assert!(verify_op(&missing_operation, &ctx).is_err());
+}
+
+#[test]
+fn generated_sparse_mma_verifies_all_int8_variants_and_metadata_modes() {
+    use dialect_mir::ops::MirConstantOp;
+    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![i32_ty.into(), u32_ty.into(), signless_i32_ty.into()],
+    );
+    let i32_value = block.deref(&ctx).get_argument(0);
+    let u32_value = block.deref(&ctx).get_argument(1);
+    let signless_i32_value = block.deref(&ctx).get_argument(2);
+
+    let integer = |value| {
+        IntegerAttr::new(
+            u32_ty,
+            APInt::from_u32(value, NonZeroUsize::new(32).unwrap()),
+        )
+    };
+    let builtin_zero = ConstantOp::new(&mut ctx, integer(0).into());
+    let builtin_zero = builtin_zero.get_operation().deref(&ctx).get_result(0);
+    let builtin_two = ConstantOp::new(&mut ctx, integer(2).into());
+    let builtin_two = builtin_two.get_operation().deref(&ctx).get_result(0);
+    let mir_one = Operation::new(
+        &mut ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    MirConstantOp::new(mir_one).set_attr_value(&ctx, integer(1));
+    let mir_one = mir_one.deref(&ctx).get_result(0);
+
+    macro_rules! sparse_mma {
+        ($operands:expr, $results:expr, $a:expr, $b:expr, $overflow:expr, $metadata:expr) => {{
+            let operation = Operation::new(
+                &mut ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                $results,
+                $operands,
+                vec![],
+                0,
+            );
+            let mma = SparseMmaOp::new(operation);
+            mma.set_attr_nvvm_sparse_mma_shape(&ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(&ctx, $a);
+            mma.set_attr_nvvm_sparse_mma_b_element(&ctx, $b);
+            mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(&ctx, $overflow);
+            mma.set_attr_nvvm_sparse_mma_metadata(&ctx, $metadata);
+            mma.set_attr_nvvm_sparse_mma_selector(&ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            mma
+        }};
+    }
+
+    let variants = [
+        (
+            SparseMmaElementAttr::S8,
+            SparseMmaElementAttr::S8,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::S8,
+            SparseMmaElementAttr::U8,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::U8,
+            SparseMmaElementAttr::U8,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::U8,
+            SparseMmaElementAttr::S8,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::S8,
+            SparseMmaElementAttr::S8,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            SparseMmaElementAttr::S8,
+            SparseMmaElementAttr::U8,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            SparseMmaElementAttr::U8,
+            SparseMmaElementAttr::U8,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            SparseMmaElementAttr::U8,
+            SparseMmaElementAttr::S8,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+    ];
+    for metadata in [
+        SparseMmaMetadataAttr::Standard,
+        SparseMmaMetadataAttr::Ordered,
+    ] {
+        for (index, (a_element, b_element, overflow)) in variants.iter().enumerate() {
+            let selector = if index % 2 == 0 {
+                builtin_zero
+            } else {
+                mir_one
+            };
+            let operands = [vec![i32_value; 4], vec![u32_value; 5], vec![selector]].concat();
+            let mma = sparse_mma!(
+                operands,
+                vec![i32_ty.into(); 4],
+                a_element.clone(),
+                b_element.clone(),
+                overflow.clone(),
+                metadata.clone()
+            );
+            assert_eq!(
+                mma.get_attr_nvvm_sparse_mma_a_element(&ctx).as_deref(),
+                Some(a_element)
+            );
+            assert_eq!(
+                mma.get_attr_nvvm_sparse_mma_b_element(&ctx).as_deref(),
+                Some(b_element)
+            );
+            assert_eq!(
+                mma.get_attr_nvvm_sparse_mma_overflow(&ctx).as_deref(),
+                Some(overflow)
+            );
+            assert_eq!(
+                mma.get_attr_nvvm_sparse_mma_metadata(&ctx).as_deref(),
+                Some(&metadata)
+            );
+            assert!(
+                verify_op(&mma, &ctx).is_ok(),
+                "rejected sparse {metadata:?} {a_element:?}x{b_element:?} {overflow:?}"
+            );
+        }
+    }
+
+    for metadata in [
+        SparseMmaMetadataAttr::Standard,
+        SparseMmaMetadataAttr::Ordered,
+    ] {
+        for selector in [u32_value, builtin_two] {
+            let invalid = sparse_mma!(
+                [vec![i32_value; 4], vec![u32_value; 5], vec![selector],].concat(),
+                vec![i32_ty.into(); 4],
+                SparseMmaElementAttr::S8,
+                SparseMmaElementAttr::U8,
+                SparseMmaOverflowAttr::Wrapping,
+                metadata.clone()
+            );
+            assert!(verify_op(&invalid, &ctx).is_err());
+        }
+    }
+
+    let wrong_accumulator_type = sparse_mma!(
+        [
+            vec![signless_i32_value; 4],
+            vec![u32_value; 5],
+            vec![builtin_zero],
+        ]
+        .concat(),
+        vec![i32_ty.into(); 4],
+        SparseMmaElementAttr::U8,
+        SparseMmaElementAttr::S8,
+        SparseMmaOverflowAttr::Satfinite,
+        SparseMmaMetadataAttr::Standard
+    );
+    assert!(verify_op(&wrong_accumulator_type, &ctx).is_err());
+
+    let wrong_count = sparse_mma!(
+        [vec![i32_value; 4], vec![u32_value; 4], vec![builtin_zero],].concat(),
+        vec![i32_ty.into(); 4],
+        SparseMmaElementAttr::S8,
+        SparseMmaElementAttr::S8,
+        SparseMmaOverflowAttr::Wrapping,
+        SparseMmaMetadataAttr::Standard
+    );
+    assert!(verify_op(&wrong_count, &ctx).is_err());
+
+    let wrong_results = sparse_mma!(
+        [vec![i32_value; 4], vec![u32_value; 5], vec![mir_one],].concat(),
+        vec![signless_i32_ty.into(); 4],
+        SparseMmaElementAttr::U8,
+        SparseMmaElementAttr::U8,
+        SparseMmaOverflowAttr::Wrapping,
+        SparseMmaMetadataAttr::Standard
+    );
+    assert!(verify_op(&wrong_results, &ctx).is_err());
+
+    let wrong_layout = sparse_mma!(
+        [vec![i32_value; 4], vec![u32_value; 5], vec![builtin_zero],].concat(),
+        vec![i32_ty.into(); 4],
+        SparseMmaElementAttr::S8,
+        SparseMmaElementAttr::U8,
+        SparseMmaOverflowAttr::Satfinite,
+        SparseMmaMetadataAttr::Standard
+    );
+    wrong_layout.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Row);
+    assert!(verify_op(&wrong_layout, &ctx).is_err());
+}
+
+#[test]
+fn generated_sparse_mma_m16n8k64_verifies_selector_and_carriers() {
+    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let signless_i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![i32_ty.into(), u32_ty.into(), signless_i32_ty.into()],
+    );
+    let i32_value = block.deref(&ctx).get_argument(0);
+    let u32_value = block.deref(&ctx).get_argument(1);
+    let signless_i32_value = block.deref(&ctx).get_argument(2);
+    let integer = |value| {
+        IntegerAttr::new(
+            u32_ty,
+            APInt::from_u32(value, NonZeroUsize::new(32).unwrap()),
+        )
+    };
+    let zero = ConstantOp::new(&mut ctx, integer(0).into())
+        .get_operation()
+        .deref(&ctx)
+        .get_result(0);
+    let one = ConstantOp::new(&mut ctx, integer(1).into())
+        .get_operation()
+        .deref(&ctx)
+        .get_result(0);
+    let two = ConstantOp::new(&mut ctx, integer(2).into())
+        .get_operation()
+        .deref(&ctx)
+        .get_result(0);
+
+    macro_rules! k64_mma {
+        ($operands:expr, $metadata:expr) => {{
+            let operation = Operation::new(
+                &mut ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![i32_ty.into(); 4],
+                $operands,
+                vec![],
+                0,
+            );
+            let mma = SparseMmaOp::new(operation);
+            mma.set_attr_nvvm_sparse_mma_shape(&ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(&ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(&ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(&ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(&ctx, $metadata);
+            mma.set_attr_nvvm_sparse_mma_selector(&ctx, SparseMmaSelectorAttr::ImmediateZero);
+            mma
+        }};
+    }
+
+    let operands = |selector| [vec![i32_value; 4], vec![u32_value; 9], vec![selector]].concat();
+    assert!(
+        verify_op(
+            &k64_mma!(operands(zero), SparseMmaMetadataAttr::Standard),
+            &ctx
+        )
+        .is_ok()
+    );
+    assert!(
+        verify_op(
+            &k64_mma!(operands(zero), SparseMmaMetadataAttr::Ordered),
+            &ctx
+        )
+        .is_ok()
+    );
+    assert!(
+        verify_op(
+            &k64_mma!(operands(one), SparseMmaMetadataAttr::Standard),
+            &ctx
+        )
+        .is_err()
+    );
+    assert!(
+        verify_op(
+            &k64_mma!(operands(one), SparseMmaMetadataAttr::Ordered),
+            &ctx
+        )
+        .is_err()
+    );
+    assert!(
+        verify_op(
+            &k64_mma!(operands(u32_value), SparseMmaMetadataAttr::Standard),
+            &ctx
+        )
+        .is_err()
+    );
+    assert!(
+        verify_op(
+            &k64_mma!(operands(u32_value), SparseMmaMetadataAttr::Ordered),
+            &ctx
+        )
+        .is_err()
+    );
+
+    let wrong_count = [vec![i32_value; 4], vec![u32_value; 8], vec![zero]].concat();
+    assert!(
+        verify_op(
+            &k64_mma!(wrong_count, SparseMmaMetadataAttr::Standard),
+            &ctx
+        )
+        .is_err()
+    );
+
+    let mut wrong_type = operands(zero);
+    wrong_type[4] = signless_i32_value;
+    assert!(verify_op(&k64_mma!(wrong_type, SparseMmaMetadataAttr::Standard), &ctx).is_err());
+
+    macro_rules! int4_mma {
+        ($operands:expr, $a:expr, $b:expr, $overflow:expr, $metadata:expr) => {{
+            let operation = Operation::new(
+                &mut ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![i32_ty.into(); 4],
+                $operands,
+                vec![],
+                0,
+            );
+            let mma = SparseMmaOp::new(operation);
+            mma.set_attr_nvvm_sparse_mma_shape(&ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(&ctx, $a);
+            mma.set_attr_nvvm_sparse_mma_b_element(&ctx, $b);
+            mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(&ctx, $overflow);
+            mma.set_attr_nvvm_sparse_mma_metadata(&ctx, $metadata);
+            mma.set_attr_nvvm_sparse_mma_selector(&ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            mma
+        }};
+    }
+
+    let int4_variants = [
+        (
+            SparseMmaElementAttr::S4,
+            SparseMmaElementAttr::S4,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::S4,
+            SparseMmaElementAttr::U4,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::U4,
+            SparseMmaElementAttr::U4,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::U4,
+            SparseMmaElementAttr::S4,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::S4,
+            SparseMmaElementAttr::S4,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            SparseMmaElementAttr::S4,
+            SparseMmaElementAttr::U4,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            SparseMmaElementAttr::U4,
+            SparseMmaElementAttr::U4,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            SparseMmaElementAttr::U4,
+            SparseMmaElementAttr::S4,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+    ];
+    let int4_operands =
+        |selector| [vec![i32_value; 4], vec![u32_value; 5], vec![selector]].concat();
+    for metadata in [
+        SparseMmaMetadataAttr::Standard,
+        SparseMmaMetadataAttr::Ordered,
+    ] {
+        for (index, (a, b, overflow)) in int4_variants.iter().enumerate() {
+            let selector = if index % 2 == 0 { zero } else { one };
+            assert!(
+                verify_op(
+                    &int4_mma!(
+                        int4_operands(selector),
+                        a.clone(),
+                        b.clone(),
+                        overflow.clone(),
+                        metadata.clone()
+                    ),
+                    &ctx,
+                )
+                .is_ok()
+            );
+        }
+    }
+
+    assert!(
+        verify_op(
+            &int4_mma!(
+                int4_operands(zero),
+                SparseMmaElementAttr::S4,
+                SparseMmaElementAttr::U8,
+                SparseMmaOverflowAttr::Wrapping,
+                SparseMmaMetadataAttr::Standard
+            ),
+            &ctx,
+        )
+        .is_err()
+    );
+    for metadata in [
+        SparseMmaMetadataAttr::Standard,
+        SparseMmaMetadataAttr::Ordered,
+    ] {
+        for selector in [two, u32_value] {
+            assert!(
+                verify_op(
+                    &int4_mma!(
+                        int4_operands(selector),
+                        SparseMmaElementAttr::S4,
+                        SparseMmaElementAttr::U4,
+                        SparseMmaOverflowAttr::Wrapping,
+                        metadata.clone()
+                    ),
+                    &ctx,
+                )
+                .is_err()
+            );
+        }
+    }
+}
+
+#[test]
+fn generated_sparse_mma_m16n8k128_int4_verifies_metadata_selector_and_widths() {
+    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), u32_ty.into()]);
+    let i32_value = block.deref(&ctx).get_argument(0);
+    let u32_value = block.deref(&ctx).get_argument(1);
+    let integer = |value| {
+        IntegerAttr::new(
+            u32_ty,
+            APInt::from_u32(value, NonZeroUsize::new(32).unwrap()),
+        )
+    };
+    let zero = ConstantOp::new(&mut ctx, integer(0).into())
+        .get_operation()
+        .deref(&ctx)
+        .get_result(0);
+    let one = ConstantOp::new(&mut ctx, integer(1).into())
+        .get_operation()
+        .deref(&ctx)
+        .get_result(0);
+
+    macro_rules! k128_mma {
+        ($operands:expr, $a:expr, $b:expr, $overflow:expr, $metadata:expr) => {{
+            let operation = Operation::new(
+                &mut ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![i32_ty.into(); 4],
+                $operands,
+                vec![],
+                0,
+            );
+            let mma = SparseMmaOp::new(operation);
+            mma.set_attr_nvvm_sparse_mma_shape(&ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(&ctx, $a);
+            mma.set_attr_nvvm_sparse_mma_b_element(&ctx, $b);
+            mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(&ctx, $overflow);
+            mma.set_attr_nvvm_sparse_mma_metadata(&ctx, $metadata);
+            mma.set_attr_nvvm_sparse_mma_selector(&ctx, SparseMmaSelectorAttr::ImmediateZero);
+            mma
+        }};
+    }
+
+    let variants = [
+        (
+            SparseMmaElementAttr::S4,
+            SparseMmaElementAttr::S4,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::S4,
+            SparseMmaElementAttr::U4,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::U4,
+            SparseMmaElementAttr::U4,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::U4,
+            SparseMmaElementAttr::S4,
+            SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            SparseMmaElementAttr::S4,
+            SparseMmaElementAttr::S4,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            SparseMmaElementAttr::S4,
+            SparseMmaElementAttr::U4,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            SparseMmaElementAttr::U4,
+            SparseMmaElementAttr::U4,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            SparseMmaElementAttr::U4,
+            SparseMmaElementAttr::S4,
+            SparseMmaOverflowAttr::Satfinite,
+        ),
+    ];
+    let operands = |selector| [vec![i32_value; 4], vec![u32_value; 9], vec![selector]].concat();
+    for metadata in [
+        SparseMmaMetadataAttr::Standard,
+        SparseMmaMetadataAttr::Ordered,
+    ] {
+        for (a, b, overflow) in &variants {
+            assert!(
+                verify_op(
+                    &k128_mma!(
+                        operands(zero),
+                        a.clone(),
+                        b.clone(),
+                        overflow.clone(),
+                        metadata.clone()
+                    ),
+                    &ctx,
+                )
+                .is_ok()
+            );
+        }
+    }
+
+    for metadata in [
+        SparseMmaMetadataAttr::Standard,
+        SparseMmaMetadataAttr::Ordered,
+    ] {
+        for selector in [one, u32_value] {
+            assert!(
+                verify_op(
+                    &k128_mma!(
+                        operands(selector),
+                        SparseMmaElementAttr::S4,
+                        SparseMmaElementAttr::U4,
+                        SparseMmaOverflowAttr::Wrapping,
+                        metadata.clone()
+                    ),
+                    &ctx,
+                )
+                .is_err()
+            );
+        }
+    }
+    assert!(
+        verify_op(
+            &k128_mma!(
+                operands(zero),
+                SparseMmaElementAttr::S4,
+                SparseMmaElementAttr::U8,
+                SparseMmaOverflowAttr::Wrapping,
+                SparseMmaMetadataAttr::Standard
+            ),
+            &ctx,
+        )
+        .is_err()
+    );
+    assert!(
+        verify_op(
+            &k128_mma!(
+                [vec![i32_value; 4], vec![u32_value; 8], vec![zero]].concat(),
+                SparseMmaElementAttr::S4,
+                SparseMmaElementAttr::S4,
+                SparseMmaOverflowAttr::Wrapping,
+                SparseMmaMetadataAttr::Standard
+            ),
+            &ctx,
+        )
+        .is_err()
+    );
+}
+
+#[test]
+fn generated_sparse_mma_f8f6f4_verifies_all_formats_and_closed_shape() {
+    use pliron::builtin::{attributes::IntegerAttr, ops::ConstantOp};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let f32_ty = FP32Type::get(&ctx);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let block = BasicBlock::new(&mut ctx, None, vec![f32_ty.into(), u32_ty.into()]);
+    let f32_value = block.deref(&ctx).get_argument(0);
+    let u32_value = block.deref(&ctx).get_argument(1);
+    let integer = |value| {
+        IntegerAttr::new(
+            u32_ty,
+            APInt::from_u32(value, NonZeroUsize::new(32).unwrap()),
+        )
+    };
+    let zero = ConstantOp::new(&mut ctx, integer(0).into())
+        .get_operation()
+        .deref(&ctx)
+        .get_result(0);
+    let one = ConstantOp::new(&mut ctx, integer(1).into())
+        .get_operation()
+        .deref(&ctx)
+        .get_result(0);
+
+    macro_rules! f8f6f4_mma {
+        ($operands:expr, $results:expr, $a:expr, $b:expr, $overflow:expr, $metadata:expr) => {{
+            let operation = Operation::new(
+                &mut ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                $results,
+                $operands,
+                vec![],
+                0,
+            );
+            let mma = SparseMmaOp::new(operation);
+            mma.set_attr_nvvm_sparse_mma_shape(&ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(&ctx, $a);
+            mma.set_attr_nvvm_sparse_mma_b_element(&ctx, $b);
+            mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(&ctx, $overflow);
+            mma.set_attr_nvvm_sparse_mma_metadata(&ctx, $metadata);
+            mma.set_attr_nvvm_sparse_mma_selector(&ctx, SparseMmaSelectorAttr::ImmediateZero);
+            mma
+        }};
+    }
+
+    let elements = [
+        SparseMmaElementAttr::E2m1,
+        SparseMmaElementAttr::E2m3,
+        SparseMmaElementAttr::E3m2,
+        SparseMmaElementAttr::E4m3,
+        SparseMmaElementAttr::E5m2,
+    ];
+    let operands = |selector| [vec![f32_value; 4], vec![u32_value; 9], vec![selector]].concat();
+    for a in &elements {
+        for b in &elements {
+            let mma = f8f6f4_mma!(
+                operands(zero),
+                vec![f32_ty.into(); 4],
+                a.clone(),
+                b.clone(),
+                SparseMmaOverflowAttr::NotApplicable,
+                SparseMmaMetadataAttr::Ordered
+            );
+            assert!(verify_op(&mma, &ctx).is_ok(), "rejected {a:?}x{b:?}");
+        }
+    }
+
+    for invalid in [
+        f8f6f4_mma!(
+            operands(one),
+            vec![f32_ty.into(); 4],
+            SparseMmaElementAttr::E2m1,
+            SparseMmaElementAttr::E2m1,
+            SparseMmaOverflowAttr::NotApplicable,
+            SparseMmaMetadataAttr::Ordered
+        ),
+        f8f6f4_mma!(
+            operands(zero),
+            vec![f32_ty.into(); 4],
+            SparseMmaElementAttr::E2m1,
+            SparseMmaElementAttr::E2m1,
+            SparseMmaOverflowAttr::Wrapping,
+            SparseMmaMetadataAttr::Ordered
+        ),
+        f8f6f4_mma!(
+            operands(zero),
+            vec![f32_ty.into(); 4],
+            SparseMmaElementAttr::E2m1,
+            SparseMmaElementAttr::E2m1,
+            SparseMmaOverflowAttr::NotApplicable,
+            SparseMmaMetadataAttr::Standard
+        ),
+        f8f6f4_mma!(
+            operands(zero),
+            vec![u32_ty.into(); 4],
+            SparseMmaElementAttr::E2m1,
+            SparseMmaElementAttr::E2m1,
+            SparseMmaOverflowAttr::NotApplicable,
+            SparseMmaMetadataAttr::Ordered
+        ),
+    ] {
+        assert!(verify_op(&invalid, &ctx).is_err());
+    }
+}
+
+#[test]
+fn test_matrix_memory_ops_verify_pointer_and_packed_register_types() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let f32_ty = FP32Type::get(&ctx);
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let load_ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
+
+    let load_block = BasicBlock::new(&mut ctx, None, vec![load_ptr_ty.into()]);
+    let load_pointer = load_block.deref(&ctx).get_argument(0);
+    let load = make_ldmatrix_x2(&mut ctx, load_pointer, vec![u32_ty.into(), u32_ty.into()]);
+    assert!(load.verify(&ctx).is_ok());
+
+    let bad_load_pointer_block = BasicBlock::new(&mut ctx, None, vec![i64_ty.into()]);
+    let bad_pointer = bad_load_pointer_block.deref(&ctx).get_argument(0);
+    let bad_load_pointer =
+        make_ldmatrix_x2(&mut ctx, bad_pointer, vec![u32_ty.into(), u32_ty.into()]);
+    assert!(bad_load_pointer.verify(&ctx).is_err());
+
+    let bad_load_result =
+        make_ldmatrix_x2(&mut ctx, load_pointer, vec![u32_ty.into(), f32_ty.into()]);
+    assert!(bad_load_result.verify(&ctx).is_err());
+
+    let store_block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            ptr_ty.into(),
+            i32_ty.into(),
+            i32_ty.into(),
+            i32_ty.into(),
+            i32_ty.into(),
+        ],
+    );
+    let store_operands = (0..5)
+        .map(|index| store_block.deref(&ctx).get_argument(index))
+        .collect();
+    let store = Operation::new(
+        &mut ctx,
+        StmatrixM8n8X4Op::get_concrete_op_info(),
+        vec![],
+        store_operands,
+        vec![],
+        0,
+    );
+    assert!(StmatrixM8n8X4Op::new(store).verify(&ctx).is_ok());
+
+    let bad_store_block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            ptr_ty.into(),
+            f32_ty.into(),
+            i32_ty.into(),
+            i32_ty.into(),
+            i32_ty.into(),
+        ],
+    );
+    let bad_store_operands = (0..5)
+        .map(|index| bad_store_block.deref(&ctx).get_argument(index))
+        .collect();
+    let bad_store = Operation::new(
+        &mut ctx,
+        StmatrixM8n8X4Op::get_concrete_op_info(),
+        vec![],
+        bad_store_operands,
+        vec![],
+        0,
+    );
+    assert!(StmatrixM8n8X4Op::new(bad_store).verify(&ctx).is_err());
+}
diff --git a/crates/dialect-nvvm/tests/ops_test/thread_and_warp.rs b/crates/dialect-nvvm/tests/ops_test/thread_and_warp.rs
new file mode 100644
index 0000000000..4b37d837ff
--- /dev/null
+++ b/crates/dialect-nvvm/tests/ops_test/thread_and_warp.rs
@@ -0,0 +1,953 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::types::{MirPointerKind, MirPtrType};
+use dialect_nvvm::ops::{
+    ActiveMaskOp, BarWarpSyncOp, Barrier0Op, ClcQueryIsCanceledOp, Dp2aS32Op, Dp2aU32Op, Dp4aS32Op,
+    Dp4aU32Op, ElectSyncOp, FmaBf16x2Op, MatchAllSyncI32Op, MatchAllSyncI64Op, MatchAnySyncI32Op,
+    MatchAnySyncI64Op, ReadPtxSregDynamicSmemSizeOp, ReadPtxSregGridIdOp, ReadPtxSregLaneIdOp,
+    ReadPtxSregLanemaskEqOp, ReadPtxSregLanemaskGeOp, ReadPtxSregLanemaskGtOp,
+    ReadPtxSregLanemaskLeOp, ReadPtxSregLanemaskLtOp, ReadPtxSregNsmIdOp, ReadPtxSregNwarpIdOp,
+    ReadPtxSregSmIdOp, ReadPtxSregTidXOp, ReadPtxSregTotalSmemSizeOp, ReadPtxSregWarpIdOp,
+    ReduxSyncAddOp, ReduxSyncAndOp, ReduxSyncFmaxAbsNanOp, ReduxSyncFmaxAbsOp, ReduxSyncFmaxNanOp,
+    ReduxSyncFmaxOp, ReduxSyncFminAbsNanOp, ReduxSyncFminAbsOp, ReduxSyncFminNanOp,
+    ReduxSyncFminOp, ReduxSyncMaxOp, ReduxSyncMinOp, ReduxSyncOrOp, ReduxSyncUmaxOp,
+    ReduxSyncUminOp, ReduxSyncXorOp, ShflSyncBflyI64Op, ShflSyncDownI64Op, ShflSyncIdxI64Op,
+    ShflSyncUpI64Op, ThreadfenceBlockOp, ThreadfenceOp, ThreadfenceSystemOp, VoteSyncAllOp,
+    VoteSyncAnyOp, VoteSyncBallotOp, VoteSyncUniOp,
+};
+
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::types::{FP32Type, IntegerType, Signedness},
+    common_traits::Verify,
+    context::Context,
+    op::{Op, verify_op},
+    operation::Operation,
+};
+
+#[test]
+fn test_thread_register_ops_verify_i32_results() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+
+    let tid_x = Operation::new(
+        &mut ctx,
+        ReadPtxSregTidXOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ReadPtxSregTidXOp::new(tid_x).verify(&ctx).is_ok());
+
+    let lane_id = Operation::new(
+        &mut ctx,
+        ReadPtxSregLaneIdOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ReadPtxSregLaneIdOp::new(lane_id).verify(&ctx).is_ok());
+}
+
+#[test]
+fn test_thread_register_ops_reject_non_i32_results() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let op = Operation::new(
+        &mut ctx,
+        ReadPtxSregTidXOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+
+    assert!(ReadPtxSregTidXOp::new(op).verify(&ctx).is_err());
+}
+
+#[test]
+fn test_lanemask_ops_verify_i32_results() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+
+    // Each lane-position mask is a zero-operand, single-i32-result sreg read.
+    let lt = Operation::new(
+        &mut ctx,
+        ReadPtxSregLanemaskLtOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ReadPtxSregLanemaskLtOp::new(lt).verify(&ctx).is_ok());
+
+    let le = Operation::new(
+        &mut ctx,
+        ReadPtxSregLanemaskLeOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ReadPtxSregLanemaskLeOp::new(le).verify(&ctx).is_ok());
+
+    let eq = Operation::new(
+        &mut ctx,
+        ReadPtxSregLanemaskEqOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ReadPtxSregLanemaskEqOp::new(eq).verify(&ctx).is_ok());
+
+    let ge = Operation::new(
+        &mut ctx,
+        ReadPtxSregLanemaskGeOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ReadPtxSregLanemaskGeOp::new(ge).verify(&ctx).is_ok());
+
+    let gt = Operation::new(
+        &mut ctx,
+        ReadPtxSregLanemaskGtOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ReadPtxSregLanemaskGtOp::new(gt).verify(&ctx).is_ok());
+}
+
+#[test]
+fn test_lanemask_op_rejects_non_i32_result() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    // A 64-bit result must fail the shared lane-position mask verifier.
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let op = Operation::new(
+        &mut ctx,
+        ReadPtxSregLanemaskLtOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ReadPtxSregLanemaskLtOp::new(op).verify(&ctx).is_err());
+}
+
+#[test]
+fn test_generated_vote_sync_family_requires_exact_mask_predicate_and_result_types() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![i32_ty.into(), i1_ty.into(), i64_ty.into()],
+    );
+    let mask = block.deref(&ctx).get_argument(0);
+    let predicate = block.deref(&ctx).get_argument(1);
+    let wide_mask = block.deref(&ctx).get_argument(2);
+
+    macro_rules! check_vote {
+        ($op:ty, $result_ty:expr, $wrong_result_ty:expr) => {{
+            let valid = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![$result_ty.into()],
+                vec![mask, predicate],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
+
+            for operands in [vec![], vec![mask], vec![mask, predicate, predicate]] {
+                let wrong_arity = Operation::new(
+                    &mut ctx,
+                    <$op>::get_concrete_op_info(),
+                    vec![$result_ty.into()],
+                    operands,
+                    vec![],
+                    0,
+                );
+                assert!(verify_op(&<$op>::new(wrong_arity), &ctx).is_err());
+            }
+
+            for results in [vec![], vec![$result_ty.into(), $result_ty.into()]] {
+                let wrong_arity = Operation::new(
+                    &mut ctx,
+                    <$op>::get_concrete_op_info(),
+                    results,
+                    vec![mask, predicate],
+                    vec![],
+                    0,
+                );
+                assert!(verify_op(&<$op>::new(wrong_arity), &ctx).is_err());
+            }
+
+            let wrong_mask = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![$result_ty.into()],
+                vec![wide_mask, predicate],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(wrong_mask), &ctx).is_err());
+
+            let wrong_predicate = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![$result_ty.into()],
+                vec![mask, mask],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(wrong_predicate), &ctx).is_err());
+
+            let wrong_result = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![$wrong_result_ty.into()],
+                vec![mask, predicate],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(wrong_result), &ctx).is_err());
+        }};
+    }
+
+    check_vote!(VoteSyncAllOp, i1_ty, u32_ty);
+    check_vote!(VoteSyncAnyOp, i1_ty, u32_ty);
+    check_vote!(VoteSyncBallotOp, u32_ty, i1_ty);
+    check_vote!(VoteSyncUniOp, i1_ty, u32_ty);
+}
+
+#[test]
+fn test_generated_active_mask_requires_no_operands_and_i32_result() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let unexpected_operand = block.deref(&ctx).get_argument(0);
+
+    let valid = Operation::new(
+        &mut ctx,
+        ActiveMaskOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ActiveMaskOp::new(valid), &ctx).is_ok());
+
+    let wrong_operand_count = Operation::new(
+        &mut ctx,
+        ActiveMaskOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![unexpected_operand],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ActiveMaskOp::new(wrong_operand_count), &ctx).is_err());
+
+    for results in [vec![], vec![i32_ty.into(), i32_ty.into()]] {
+        let wrong_result_count = Operation::new(
+            &mut ctx,
+            ActiveMaskOp::get_concrete_op_info(),
+            results,
+            vec![],
+            vec![],
+            0,
+        );
+        assert!(verify_op(&ActiveMaskOp::new(wrong_result_count), &ctx).is_err());
+    }
+
+    let wrong_result_width = Operation::new(
+        &mut ctx,
+        ActiveMaskOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ActiveMaskOp::new(wrong_result_width), &ctx).is_err());
+}
+
+#[test]
+fn test_generated_match_family_requires_exact_mask_value_and_result_widths() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![i32_ty.into(), i32_ty.into(), i64_ty.into()],
+    );
+    let mask = block.deref(&ctx).get_argument(0);
+    let value32 = block.deref(&ctx).get_argument(1);
+    let value64 = block.deref(&ctx).get_argument(2);
+
+    macro_rules! check_match {
+        ($op:ty, $value:expr, $wrong_value:expr) => {{
+            let valid = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![i32_ty.into()],
+                vec![mask, $value],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
+
+            for operands in [vec![], vec![mask], vec![mask, $value, $value]] {
+                let wrong_operand_count = Operation::new(
+                    &mut ctx,
+                    <$op>::get_concrete_op_info(),
+                    vec![i32_ty.into()],
+                    operands,
+                    vec![],
+                    0,
+                );
+                assert!(verify_op(&<$op>::new(wrong_operand_count), &ctx).is_err());
+            }
+
+            for results in [vec![], vec![i32_ty.into(), i32_ty.into()]] {
+                let wrong_result_count = Operation::new(
+                    &mut ctx,
+                    <$op>::get_concrete_op_info(),
+                    results,
+                    vec![mask, $value],
+                    vec![],
+                    0,
+                );
+                assert!(verify_op(&<$op>::new(wrong_result_count), &ctx).is_err());
+            }
+
+            let wrong_mask_width = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![i32_ty.into()],
+                vec![value64, $value],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(wrong_mask_width), &ctx).is_err());
+
+            let wrong_value_width = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![i32_ty.into()],
+                vec![mask, $wrong_value],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(wrong_value_width), &ctx).is_err());
+
+            let wrong_result_width = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![i64_ty.into()],
+                vec![mask, $value],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(wrong_result_width), &ctx).is_err());
+        }};
+    }
+
+    check_match!(MatchAnySyncI32Op, value32, value64);
+    check_match!(MatchAllSyncI32Op, value32, value64);
+    check_match!(MatchAnySyncI64Op, value64, value32);
+    check_match!(MatchAllSyncI64Op, value64, value32);
+}
+
+#[test]
+fn test_special_register_ops_verify_authoritative_widths() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+
+    macro_rules! check_width {
+        ($op:ty, $good:expr, $bad:expr) => {{
+            let good = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![$good.into()],
+                vec![],
+                vec![],
+                0,
+            );
+            assert!(
+                verify_op(&<$op>::new(good), &ctx).is_ok(),
+                "{} must accept its PTX register width",
+                stringify!($op)
+            );
+
+            let bad = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![$bad.into()],
+                vec![],
+                vec![],
+                0,
+            );
+            assert!(
+                verify_op(&<$op>::new(bad), &ctx).is_err(),
+                "{} must reject the other integer width",
+                stringify!($op)
+            );
+        }};
+    }
+
+    check_width!(ReadPtxSregWarpIdOp, i32_ty, i64_ty);
+    check_width!(ReadPtxSregNwarpIdOp, i32_ty, i64_ty);
+    check_width!(ReadPtxSregSmIdOp, i32_ty, i64_ty);
+    check_width!(ReadPtxSregNsmIdOp, i32_ty, i64_ty);
+    check_width!(ReadPtxSregDynamicSmemSizeOp, i32_ty, i64_ty);
+    check_width!(ReadPtxSregTotalSmemSizeOp, i32_ty, i64_ty);
+    check_width!(ReadPtxSregGridIdOp, i64_ty, i32_ty);
+}
+
+#[test]
+fn test_sync_ops_construct_and_verify() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let barrier = Operation::new(
+        &mut ctx,
+        Barrier0Op::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(Barrier0Op::new(barrier).verify(&ctx).is_ok());
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let unexpected_operand = block.deref(&ctx).get_argument(0);
+    let bad_operand = Operation::new(
+        &mut ctx,
+        Barrier0Op::get_concrete_op_info(),
+        vec![],
+        vec![unexpected_operand],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&Barrier0Op::new(bad_operand), &ctx).is_err());
+
+    let bad_result = Operation::new(
+        &mut ctx,
+        Barrier0Op::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&Barrier0Op::new(bad_result), &ctx).is_err());
+
+    let block_fence = Operation::new(
+        &mut ctx,
+        ThreadfenceBlockOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ThreadfenceBlockOp::new(block_fence).verify(&ctx).is_ok());
+
+    let device_fence = Operation::new(
+        &mut ctx,
+        ThreadfenceOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ThreadfenceOp::new(device_fence).verify(&ctx).is_ok());
+
+    let system_fence = Operation::new(
+        &mut ctx,
+        ThreadfenceSystemOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(ThreadfenceSystemOp::new(system_fence).verify(&ctx).is_ok());
+}
+
+#[test]
+fn test_bf16x2_fma_constructs_and_verifies_three_operands() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+
+    let a = Operation::new(
+        &mut ctx,
+        ReadPtxSregTidXOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let b = Operation::new(
+        &mut ctx,
+        ReadPtxSregTidXOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let c = Operation::new(
+        &mut ctx,
+        ReadPtxSregTidXOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+
+    let operands = vec![
+        a.deref(&ctx).get_result(0),
+        b.deref(&ctx).get_result(0),
+        c.deref(&ctx).get_result(0),
+    ];
+
+    let fma = Operation::new(
+        &mut ctx,
+        FmaBf16x2Op::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        operands,
+        vec![],
+        0,
+    );
+
+    assert!(FmaBf16x2Op::new(fma).verify(&ctx).is_ok());
+}
+
+#[test]
+fn test_generated_dot_products_require_three_i32_operands_and_one_i32_result() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![i32_ty.into(), i32_ty.into(), i32_ty.into(), i64_ty.into()],
+    );
+    let a = block.deref(&ctx).get_argument(0);
+    let b = block.deref(&ctx).get_argument(1);
+    let c = block.deref(&ctx).get_argument(2);
+    let wide = block.deref(&ctx).get_argument(3);
+
+    macro_rules! check_variant {
+        ($op:ty) => {{
+            let valid = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![i32_ty.into()],
+                vec![a, b, c],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
+
+            let wrong_width = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![i32_ty.into()],
+                vec![a, b, wide],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(wrong_width), &ctx).is_err());
+
+            for (results, operands) in [
+                (vec![], vec![a, b, c]),
+                (vec![i32_ty.into(), i32_ty.into()], vec![a, b, c]),
+                (vec![i32_ty.into()], vec![a, b]),
+                (vec![i32_ty.into()], vec![a, b, c, c]),
+            ] {
+                let wrong_count = Operation::new(
+                    &mut ctx,
+                    <$op>::get_concrete_op_info(),
+                    results,
+                    operands,
+                    vec![],
+                    0,
+                );
+                assert!(verify_op(&<$op>::new(wrong_count), &ctx).is_err());
+            }
+        }};
+    }
+
+    check_variant!(Dp4aS32Op);
+    check_variant!(Dp4aU32Op);
+    check_variant!(Dp2aS32Op);
+    check_variant!(Dp2aU32Op);
+}
+
+#[test]
+fn test_redux_sync_add_construct_and_verify() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+
+    // A block supplies the two operands [mask, value].
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), i32_ty.into()]);
+    let mask = block.deref(&ctx).get_argument(0);
+    let value = block.deref(&ctx).get_argument(1);
+
+    // Valid: 2 operands, 1 result (matches NOpdsInterface<2>/NResultsInterface<1>).
+    let op = Operation::new(
+        &mut ctx,
+        ReduxSyncAddOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![mask, value],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ReduxSyncAddOp::new(op), &ctx).is_ok());
+
+    // Invalid: wrong operand count (1 instead of 2) must fail verification.
+    let bad_opnds = Operation::new(
+        &mut ctx,
+        ReduxSyncAddOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![mask],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ReduxSyncAddOp::new(bad_opnds), &ctx).is_err());
+
+    // Invalid: wrong result count (0 instead of 1) must fail verification.
+    let bad_results = Operation::new(
+        &mut ctx,
+        ReduxSyncAddOp::get_concrete_op_info(),
+        vec![],
+        vec![mask, value],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ReduxSyncAddOp::new(bad_results), &ctx).is_err());
+}
+
+#[test]
+fn test_redux_sync_integer_family_construct_and_verify() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), i32_ty.into()]);
+    let mask = block.deref(&ctx).get_argument(0);
+    let value = block.deref(&ctx).get_argument(1);
+
+    // Every integer-family variant has the same 2-operand/1-result shape. A
+    // valid build of each must verify; a wrong operand count must not. The
+    // `new` wrapper is invoked so each concrete op type is exercised.
+    macro_rules! check_variant {
+        ($op:ty) => {{
+            let good = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![i32_ty.into()],
+                vec![mask, value],
+                vec![],
+                0,
+            );
+            assert!(
+                verify_op(&<$op>::new(good), &ctx).is_ok(),
+                "{} should verify with [mask, value] -> i32",
+                stringify!($op)
+            );
+
+            let bad = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![i32_ty.into()],
+                vec![mask],
+                vec![],
+                0,
+            );
+            assert!(
+                verify_op(&<$op>::new(bad), &ctx).is_err(),
+                "{} must reject a single operand",
+                stringify!($op)
+            );
+        }};
+    }
+
+    check_variant!(ReduxSyncUminOp);
+    check_variant!(ReduxSyncMinOp);
+    check_variant!(ReduxSyncUmaxOp);
+    check_variant!(ReduxSyncMaxOp);
+    check_variant!(ReduxSyncAndOp);
+    check_variant!(ReduxSyncOrOp);
+    check_variant!(ReduxSyncXorOp);
+}
+
+#[test]
+fn test_redux_sync_f32_family_construct_and_verify() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let f32_ty = FP32Type::get(&ctx);
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), f32_ty.into()]);
+    let mask = block.deref(&ctx).get_argument(0);
+    let value = block.deref(&ctx).get_argument(1);
+
+    // The good case goes through the generated `build()` so its f32 result
+    // construction is exercised; the bad case's i32 value and result must
+    // fail the `is_f32` verifier path.
+    macro_rules! check_variant {
+        ($op:ty) => {{
+            let good = <$op>::build(&mut ctx, mask, value);
+            assert!(
+                verify_op(&<$op>::new(good), &ctx).is_ok(),
+                "{} should verify with [mask, value] -> f32",
+                stringify!($op)
+            );
+
+            let bad = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![i32_ty.into()],
+                vec![mask, mask],
+                vec![],
+                0,
+            );
+            assert!(
+                verify_op(&<$op>::new(bad), &ctx).is_err(),
+                "{} must reject an i32 value and result",
+                stringify!($op)
+            );
+        }};
+    }
+
+    check_variant!(ReduxSyncFminOp);
+    check_variant!(ReduxSyncFminNanOp);
+    check_variant!(ReduxSyncFminAbsOp);
+    check_variant!(ReduxSyncFminAbsNanOp);
+    check_variant!(ReduxSyncFmaxOp);
+    check_variant!(ReduxSyncFmaxNanOp);
+    check_variant!(ReduxSyncFmaxAbsOp);
+    check_variant!(ReduxSyncFmaxAbsNanOp);
+}
+
+#[test]
+fn test_bar_warp_sync_construct_and_verify() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into(), i64_ty.into()]);
+    let mask = block.deref(&ctx).get_argument(0);
+    let wrong_mask = block.deref(&ctx).get_argument(1);
+
+    let valid = BarWarpSyncOp::build(&mut ctx, mask);
+    assert!(verify_op(&BarWarpSyncOp::new(valid), &ctx).is_ok());
+
+    let wrong_type = BarWarpSyncOp::build(&mut ctx, wrong_mask);
+    assert!(verify_op(&BarWarpSyncOp::new(wrong_type), &ctx).is_err());
+
+    let wrong_arity = Operation::new(
+        &mut ctx,
+        BarWarpSyncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&BarWarpSyncOp::new(wrong_arity), &ctx).is_err());
+}
+
+#[test]
+fn test_elect_sync_construct_and_verify() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+
+    // A block supplies the single `mask` operand.
+    let block = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    let mask = block.deref(&ctx).get_argument(0);
+
+    // Valid: 1 operand [mask], 2 results [leader (i32), is_elected (i1)]
+    // (matches NOpdsInterface<1>/NResultsInterface<2>).
+    let op = Operation::new(
+        &mut ctx,
+        ElectSyncOp::get_concrete_op_info(),
+        vec![i32_ty.into(), i1_ty.into()],
+        vec![mask],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ElectSyncOp::new(op), &ctx).is_ok());
+
+    // Invalid: wrong operand count (0 instead of 1) must fail verification.
+    let bad_opnds = Operation::new(
+        &mut ctx,
+        ElectSyncOp::get_concrete_op_info(),
+        vec![i32_ty.into(), i1_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ElectSyncOp::new(bad_opnds), &ctx).is_err());
+
+    // Invalid: wrong result count (1 instead of 2) must fail verification.
+    let bad_results = Operation::new(
+        &mut ctx,
+        ElectSyncOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![mask],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ElectSyncOp::new(bad_results), &ctx).is_err());
+
+    // Invalid: a correctly-sized result list still cannot use a pointer as
+    // either result and thereby manufacture a MIR pointer kind.
+    let pointer_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty.into(), true, MirPointerKind::UniqueRef);
+    let bad_result_type = Operation::new(
+        &mut ctx,
+        ElectSyncOp::get_concrete_op_info(),
+        vec![i32_ty.into(), pointer_ty.into()],
+        vec![mask],
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ElectSyncOp::new(bad_result_type), &ctx).is_err());
+}
+
+#[test]
+fn test_clc_query_rejects_pointer_results() {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let block = BasicBlock::new(&mut ctx, None, vec![u64_ty.into(), u64_ty.into()]);
+    let operands = vec![
+        block.deref(&ctx).get_argument(0),
+        block.deref(&ctx).get_argument(1),
+    ];
+
+    let valid = Operation::new(
+        &mut ctx,
+        ClcQueryIsCanceledOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        operands.clone(),
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ClcQueryIsCanceledOp::new(valid), &ctx).is_ok());
+
+    let pointer_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, u32_ty.into(), true, MirPointerKind::UniqueRef);
+    let bad = Operation::new(
+        &mut ctx,
+        ClcQueryIsCanceledOp::get_concrete_op_info(),
+        vec![pointer_ty.into()],
+        operands,
+        vec![],
+        0,
+    );
+    assert!(verify_op(&ClcQueryIsCanceledOp::new(bad), &ctx).is_err());
+}
+
+#[test]
+fn test_shfl_sync_i64_construct_and_verify() {
+    let mut ctx = Context::new();
+    dialect_nvvm::register(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+
+    let block = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![i32_ty.into(), i64_ty.into(), i32_ty.into()],
+    );
+    let mask = block.deref(&ctx).get_argument(0);
+    let value = block.deref(&ctx).get_argument(1);
+    let lane = block.deref(&ctx).get_argument(2);
+
+    macro_rules! check_mode {
+        ($op:ty) => {{
+            let valid = <$op>::build(&mut ctx, mask, value, lane);
+            assert!(verify_op(&<$op>::new(valid), &ctx).is_ok());
+
+            for (operands, result_ty) in [
+                (vec![mask, value], i64_ty.into()),
+                (vec![value, value, lane], i64_ty.into()),
+                (vec![mask, mask, lane], i64_ty.into()),
+                (vec![mask, value, value], i64_ty.into()),
+                (vec![mask, value, lane], i32_ty.into()),
+            ] {
+                let invalid = Operation::new(
+                    &mut ctx,
+                    <$op>::get_concrete_op_info(),
+                    vec![result_ty],
+                    operands,
+                    vec![],
+                    0,
+                );
+                assert!(verify_op(&<$op>::new(invalid), &ctx).is_err());
+            }
+
+            let no_result = Operation::new(
+                &mut ctx,
+                <$op>::get_concrete_op_info(),
+                vec![],
+                vec![mask, value, lane],
+                vec![],
+                0,
+            );
+            assert!(verify_op(&<$op>::new(no_result), &ctx).is_err());
+        }};
+    }
+
+    check_mode!(ShflSyncIdxI64Op);
+    check_mode!(ShflSyncBflyI64Op);
+    check_mode!(ShflSyncDownI64Op);
+    check_mode!(ShflSyncUpI64Op);
+}
diff --git a/crates/llvm-export/tests/export_test.rs b/crates/llvm-export/tests/export_test.rs
deleted file mode 100644
index 2ae0d00273..0000000000
--- a/crates/llvm-export/tests/export_test.rs
+++ /dev/null
@@ -1,5373 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-use combine::stream::position::SourcePosition;
-use llvm_export::{
-    export::{
-        DebugKind, DeviceExternAttrs, DeviceExternDecl, DeviceExternType, ExportBackendConfig,
-        NvvmExportConfig, NvvmIrDialect, PtxExportConfig, export_module_to_string,
-        export_module_to_string_with_config, export_module_with_externs,
-        export_module_with_externs_and_roots,
-    },
-    op_interfaces::CastOpInterface,
-    ops::{
-        AddrSpaceCastOp, AddressOfOp, AllocaOp, BitcastOp, BrOp, CallOp, CondBrOp, ConstantOp,
-        DebugEnumDiscriminant, DebugEnumVariant, DebugFragment, DebugFragmentVariableInfo,
-        DebugGlobalVariableInfo, DebugLocalTypeKind, DebugLocalVariableInfo,
-        DebugProjectedVariableInfo, DebugSourcePosition, DebugSourceScope,
-        DebugSourceScopeLocation, DebugSourceScopeMap, DebugValueExpression,
-        DebugValueExpressionOp, DebugValueListOp, DebugValueOp, FuncOp, GepIndex, GetElementPtrOp,
-        GlobalInitializerRelocation, GlobalOp, GlobalOpExt, InlineAsmOp, LoadOp, ReturnOp,
-        SelectOp, StoreOp, UndefOp, encode_global_initializer_relocations,
-    },
-    types::{ArrayType, FuncType, HalfType, PointerType, StructLayout, StructType, VoidType},
-};
-use pliron::{
-    basic_block::BasicBlock,
-    builtin::{
-        attributes::{IntegerAttr, StringAttr},
-        op_interfaces::CallOpCallable,
-        ops::ModuleOp,
-        types::{FP32Type, IntegerType, Signedness},
-    },
-    common_traits::Verify,
-    context::{Context, Ptr},
-    identifier::Identifier,
-    linked_list::ContainsLinkedList,
-    location::{Located, Location, Source},
-    op::Op,
-    utils::apint::APInt,
-};
-use std::{num::NonZero, path::PathBuf};
-
-struct DebugConfig<C> {
-    inner: C,
-    debug_kind: DebugKind,
-}
-
-impl<C: ExportBackendConfig> ExportBackendConfig for DebugConfig<C> {
-    fn datalayout(&self) -> &str {
-        self.inner.datalayout()
-    }
-
-    fn emit_llvm_used(&self) -> bool {
-        self.inner.emit_llvm_used()
-    }
-
-    fn emit_nvvmir_version(&self) -> bool {
-        self.inner.emit_nvvmir_version()
-    }
-
-    fn nvvmir_version(&self) -> [i32; 4] {
-        self.inner.nvvmir_version()
-    }
-
-    fn emit_all_kernel_annotations(&self) -> bool {
-        self.inner.emit_all_kernel_annotations()
-    }
-
-    fn emit_ptx_kernel_keyword(&self) -> bool {
-        self.inner.emit_ptx_kernel_keyword()
-    }
-
-    fn nvvm_ir_dialect(&self) -> Option<llvm_export::export::NvvmIrDialect> {
-        self.inner.nvvm_ir_dialect()
-    }
-
-    fn debug_kind(&self) -> DebugKind {
-        self.debug_kind
-    }
-}
-
-fn src_location(ctx: &mut Context, file: &str, line: i32, column: i32) -> Location {
-    Location::SrcPos {
-        src: Source::new_from_file(ctx, PathBuf::from(file)),
-        pos: SourcePosition { line, column },
-    }
-}
-
-fn module_top_block(ctx: &mut Context, module: &ModuleOp) -> Ptr<BasicBlock> {
-    let module_region = module.get_operation().deref(ctx).get_region(0);
-    {
-        let region = module_region.deref(ctx);
-        if let Some(block) = region.iter(ctx).next() {
-            return block;
-        }
-    }
-
-    let block = BasicBlock::new(ctx, None, vec![]);
-    block.insert_at_back(module_region, ctx);
-    block
-}
-
-fn metadata_id<'a>(ir: &'a str, needle: &str) -> &'a str {
-    ir.lines()
-        .find(|line| line.contains(needle))
-        .and_then(|line| line.split_once(" = ").map(|(id, _)| id))
-        .unwrap_or_else(|| panic!("missing metadata node containing {needle:?}:\n{ir}"))
-}
-
-#[test]
-fn export_volatile_load_prints_keyword() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let ptr_ty = PointerType::get(&ctx, 0);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![ptr_ty.to_handle()], false);
-    let func = FuncOp::new(&mut ctx, "volatile_load_test".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let ptr = entry.deref(&ctx).get_argument(0);
-
-    let load = LoadOp::new(&mut ctx, ptr, i32_ty.to_handle());
-    llvm_export::ops::set_op_volatile(&mut ctx, load.get_operation(), true);
-    load.get_operation().insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
-    let line = ir
-        .lines()
-        .find(|line| line.contains("load volatile"))
-        .expect("volatile load line");
-
-    assert!(
-        line.trim_start().contains(" = load volatile i32, ptr "),
-        "volatile load keyword must appear immediately after load:\n{ir}"
-    );
-}
-
-#[test]
-fn export_volatile_store_prints_keyword() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let ptr_ty = PointerType::get(&ctx, 0);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(
-        &ctx,
-        void_ty.to_handle(),
-        vec![ptr_ty.to_handle(), i32_ty.to_handle()],
-        false,
-    );
-    let func = FuncOp::new(&mut ctx, "volatile_store_test".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let ptr = entry.deref(&ctx).get_argument(0);
-    let val = entry.deref(&ctx).get_argument(1);
-
-    let store = StoreOp::new(&mut ctx, val, ptr);
-    llvm_export::ops::set_op_volatile(&mut ctx, store.get_operation(), true);
-    store.get_operation().insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
-    let line = ir
-        .lines()
-        .find(|line| line.contains("store volatile"))
-        .expect("volatile store line");
-
-    assert!(
-        line.trim_start().starts_with("store volatile i32 "),
-        "volatile store keyword must appear immediately after store:\n{ir}"
-    );
-}
-
-#[test]
-fn legacy_export_uses_one_canonical_pointer_with_multiple_typed_views() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "legacy_views".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let ptr_ty = PointerType::get(&ctx, 0);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let f32_ty = FP32Type::get(&ctx);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
-    let func = FuncOp::new(&mut ctx, "multiple_views".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let pointer = entry.deref(&ctx).get_argument(0);
-
-    LoadOp::new(&mut ctx, pointer, i32_ty.into())
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    LoadOp::new(&mut ctx, pointer, f32_ty.into())
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    LoadOp::new(&mut ctx, pointer, i8_ty.into())
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7);
-    let ir = export_module_to_string_with_config(&ctx, &module, &config)
-        .expect("legacy export succeeds");
-
-    assert!(ir.contains("define void @multiple_views(i8* %v0)"), "{ir}");
-    assert!(ir.contains("bitcast i8* %v0 to i32*"), "{ir}");
-    assert!(ir.contains("load i32, i32*"), "{ir}");
-    assert!(ir.contains("bitcast i8* %v0 to float*"), "{ir}");
-    assert!(ir.contains("load float, float*"), "{ir}");
-    assert!(ir.contains("load i8, i8* %v0"), "{ir}");
-    assert!(!ir.contains("bitcast i8* %v0 to i8*"), "{ir}");
-    assert!(
-        !ir.split(|c: char| !c.is_ascii_alphanumeric())
-            .any(|t| t == "ptr")
-    );
-}
-
-#[test]
-fn legacy_alloca_rejects_a_non_default_result_address_space() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "invalid_alloca_as".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "invalid_alloca".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-
-    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
-    let one = ConstantOp::new(&mut ctx, one_attr.into());
-    let one_value = one.get_operation().deref(&ctx).get_result(0);
-    one.get_operation().insert_at_back(entry, &ctx);
-    let alloca = AllocaOp::new(&mut ctx, i32_ty.into(), one_value);
-    let alloca_result = alloca.get_operation().deref(&ctx).get_result(0);
-    let shared_pointer = PointerType::get(&ctx, 3);
-    alloca_result.set_type(&ctx, shared_pointer.into());
-    alloca.get_operation().insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    module
-        .get_operation()
-        .deref(&ctx)
-        .verify(&ctx)
-        .expect("upstream verification currently does not enforce alloca result AS0");
-    let error = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("legacy export must reject an alloca address-space mismatch");
-    assert!(
-        error.contains("alloca result uses address space 3"),
-        "{error}"
-    );
-}
-
-#[test]
-fn legacy_gep_rejects_a_result_address_space_different_from_its_base() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "invalid_gep_as".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let global_pointer = PointerType::get(&ctx, 1);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![global_pointer.into()], false);
-    let func = FuncOp::new(&mut ctx, "invalid_gep".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let base = entry.deref(&ctx).get_argument(0);
-    let gep = GetElementPtrOp::new(&mut ctx, base, vec![GepIndex::Constant(0)], i32_ty.into());
-    let gep_result = gep.get_operation().deref(&ctx).get_result(0);
-    let shared_pointer = PointerType::get(&ctx, 3);
-    gep_result.set_type(&ctx, shared_pointer.into());
-    gep.get_operation().insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    module
-        .get_operation()
-        .deref(&ctx)
-        .verify(&ctx)
-        .expect("upstream verification currently does not enforce GEP result/base AS equality");
-    let error = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("legacy export must reject a GEP address-space mismatch");
-    assert!(
-        error.contains("GEP result address-space mismatch: base is 1, result is 3"),
-        "{error}"
-    );
-}
-
-#[test]
-fn gep_inbounds_marker_controls_exported_pointer_semantics() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "gep_semantics".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let pointer = PointerType::get(&ctx, 0);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![pointer.into()], false);
-    let func = FuncOp::new(&mut ctx, "offsets".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let base = entry.deref(&ctx).get_argument(0);
-
-    let ordinary = GetElementPtrOp::new(&mut ctx, base, vec![GepIndex::Constant(1)], i32_ty.into());
-    ordinary.get_operation().insert_at_back(entry, &ctx);
-
-    let wrapping = GetElementPtrOp::new(&mut ctx, base, vec![GepIndex::Constant(2)], i32_ty.into());
-    llvm_export::ops::set_gep_inbounds(&mut ctx, wrapping.get_operation(), false);
-    wrapping.get_operation().insert_at_back(entry, &ctx);
-
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string(&ctx, &module).expect("GEP export succeeds");
-    let gep_lines: Vec<_> = ir
-        .lines()
-        .filter(|line| line.contains("getelementptr"))
-        .collect();
-    assert_eq!(gep_lines.len(), 2, "{ir}");
-    assert!(gep_lines[0].contains("getelementptr inbounds"), "{ir}");
-    assert!(
-        gep_lines[1].contains("getelementptr i32")
-            && !gep_lines[1].contains("getelementptr inbounds"),
-        "{ir}"
-    );
-}
-
-#[test]
-fn legacy_pointer_select_keeps_one_canonical_type() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "legacy_pointer_select".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let ptr_ty = PointerType::get(&ctx, 0);
-    let func_ty = FuncType::get(
-        &ctx,
-        ptr_ty.into(),
-        vec![i1_ty.into(), ptr_ty.into(), ptr_ty.into()],
-        false,
-    );
-    let func = FuncOp::new(&mut ctx, "choose_pointer".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let condition = entry.deref(&ctx).get_argument(0);
-    let if_true = entry.deref(&ctx).get_argument(1);
-    let if_false = entry.deref(&ctx).get_argument(2);
-    let select = SelectOp::new(&mut ctx, condition, if_true, if_false);
-    let selected = select.get_operation().deref(&ctx).get_result(0);
-    select.get_operation().insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, Some(selected))
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect("legacy pointer select export succeeds");
-    assert!(
-        ir.contains("select i1 %v0, i8* %v1, i8* %v2"),
-        "pointer select must use the canonical byte-pointer type:\n{ir}"
-    );
-    assert!(ir.contains("ret i8*"), "{ir}");
-}
-
-#[test]
-fn exporter_rejects_extra_predecessor_values_before_emitting_phis() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "invalid_branch_arity".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "invalid_branch".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let region = func.get_operation().deref(&ctx).get_region(0);
-    let destination = BasicBlock::new(&mut ctx, None, vec![]);
-    destination.insert_at_back(region, &ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
-    let one = ConstantOp::new(&mut ctx, one_attr.into());
-    let one_value = one.get_operation().deref(&ctx).get_result(0);
-    one.get_operation().insert_at_back(entry, &ctx);
-    BrOp::new(&mut ctx, destination, vec![one_value])
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(destination, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let error = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("extra predecessor values must be rejected");
-    assert!(
-        error.contains("supplies 1 values") && error.contains("expects 0 block arguments"),
-        "{error}"
-    );
-}
-
-#[test]
-fn exporter_rejects_distinct_values_on_duplicate_conditional_edges() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "duplicate_conditional_edge".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let func_ty = FuncType::get(
-        &ctx,
-        i32_ty.into(),
-        vec![i1_ty.into(), i32_ty.into(), i32_ty.into()],
-        false,
-    );
-    let func = FuncOp::new(&mut ctx, "duplicate_edge".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let condition = entry.deref(&ctx).get_argument(0);
-    let if_true = entry.deref(&ctx).get_argument(1);
-    let if_false = entry.deref(&ctx).get_argument(2);
-    let region = func.get_operation().deref(&ctx).get_region(0);
-    let destination = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    destination.insert_at_back(region, &ctx);
-    CondBrOp::new(
-        &mut ctx,
-        condition,
-        destination,
-        vec![if_true],
-        destination,
-        vec![if_false],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    let result = destination.deref(&ctx).get_argument(0);
-    ReturnOp::new(&mut ctx, Some(result))
-        .get_operation()
-        .insert_at_back(destination, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    module
-        .get_operation()
-        .deref(&ctx)
-        .verify(&ctx)
-        .expect("pliron permits same-destination conditional edges with distinct values");
-    let error = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("LLVM PHIs cannot distinguish duplicate predecessor edges");
-    assert!(
-        error.contains("both edges with different forwarded values"),
-        "{error}"
-    );
-}
-
-#[test]
-fn exporter_deduplicates_identical_values_on_duplicate_conditional_edges() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "identical_conditional_edge".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let func_ty = FuncType::get(
-        &ctx,
-        i32_ty.into(),
-        vec![i1_ty.into(), i32_ty.into()],
-        false,
-    );
-    let func = FuncOp::new(&mut ctx, "identical_edge".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let condition = entry.deref(&ctx).get_argument(0);
-    let value = entry.deref(&ctx).get_argument(1);
-    let region = func.get_operation().deref(&ctx).get_region(0);
-    let destination = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    destination.insert_at_back(region, &ctx);
-    CondBrOp::new(
-        &mut ctx,
-        condition,
-        destination,
-        vec![value],
-        destination,
-        vec![value],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    let result = destination.deref(&ctx).get_argument(0);
-    ReturnOp::new(&mut ctx, Some(result))
-        .get_operation()
-        .insert_at_back(destination, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect("identical duplicate-edge values can use one PHI predecessor");
-    let phi = ir
-        .lines()
-        .find(|line| line.contains(" = phi i32 "))
-        .expect("destination block must contain a PHI");
-    assert_eq!(phi.matches("%entry").count(), 1, "{phi}");
-}
-
-#[test]
-fn phi_can_reference_undef_from_a_later_block() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "later_undef_phi".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let func_ty = FuncType::get(
-        &ctx,
-        i32_ty.into(),
-        vec![i1_ty.into(), i32_ty.into()],
-        false,
-    );
-    let func = FuncOp::new(&mut ctx, "choose_undef".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let condition = entry.deref(&ctx).get_argument(0);
-    let fallback = entry.deref(&ctx).get_argument(1);
-    let region = func.get_operation().deref(&ctx).get_region(0);
-
-    // The join precedes both predecessors in print order, so its PHI depends
-    // on the exporter's whole-function value-name pre-pass.
-    let join = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
-    join.insert_at_back(region, &ctx);
-    let undef_block = BasicBlock::new(&mut ctx, None, vec![]);
-    undef_block.insert_at_back(region, &ctx);
-    let value_block = BasicBlock::new(&mut ctx, None, vec![]);
-    value_block.insert_at_back(region, &ctx);
-
-    CondBrOp::new(
-        &mut ctx,
-        condition,
-        undef_block,
-        vec![],
-        value_block,
-        vec![],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-
-    let undef = UndefOp::new(&mut ctx, i32_ty.into());
-    let undef_value = undef.get_operation().deref(&ctx).get_result(0);
-    undef.get_operation().insert_at_back(undef_block, &ctx);
-    BrOp::new(&mut ctx, join, vec![undef_value])
-        .get_operation()
-        .insert_at_back(undef_block, &ctx);
-    BrOp::new(&mut ctx, join, vec![fallback])
-        .get_operation()
-        .insert_at_back(value_block, &ctx);
-
-    let result = join.deref(&ctx).get_argument(0);
-    ReturnOp::new(&mut ctx, Some(result))
-        .get_operation()
-        .insert_at_back(join, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect("later-block undef must be available while exporting an earlier PHI");
-    assert!(
-        ir.lines()
-            .any(|line| line.contains(" = phi i32 ") && line.contains("[ undef,")),
-        "{ir}"
-    );
-}
-
-#[test]
-fn indirect_call_rejects_non_program_address_space() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "invalid_indirect_callee".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let shared_ptr_ty = PointerType::get(&ctx, 3);
-    let void_ty = VoidType::get(&ctx);
-    let callee_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
-    let caller_ty = FuncType::get(&ctx, void_ty.into(), vec![shared_ptr_ty.into()], false);
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), caller_ty);
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    let callee = entry.deref(&ctx).get_argument(0);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Indirect(callee),
-        callee_ty,
-        vec![],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    for dialect in [NvvmIrDialect::LegacyLlvm7, NvvmIrDialect::Modern] {
-        let error =
-            export_module_to_string_with_config(&ctx, &module, &NvvmExportConfig::new(dialect))
-                .expect_err("NVPTX must reject a shared-memory function pointer");
-        assert!(error.contains("address space 3"), "{error}");
-        assert!(error.contains("function pointers"), "{error}");
-    }
-}
-
-#[test]
-fn intrinsic_export_preserves_legacy_dots_and_literal_underscores() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "intrinsic_names".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let void_ty = VoidType::get(&ctx);
-    let function_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
-    let legacy = "llvm_nvvm_wgmma_fence_sync_aligned";
-    let escaped = "llvm__nvvm_dwgmma_dcommit_ugroup_dsync_daligned";
-
-    for name in [legacy, escaped] {
-        FuncOp::new(&mut ctx, name.try_into().unwrap(), function_ty)
-            .get_operation()
-            .insert_at_back(module_block, &ctx);
-    }
-
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), function_ty);
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    for name in [legacy, escaped] {
-        CallOp::new(
-            &mut ctx,
-            CallOpCallable::Direct(name.try_into().unwrap()),
-            function_ty,
-            vec![],
-        )
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    }
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string(&ctx, &module).expect("intrinsic export succeeds");
-    assert!(ir.contains("@llvm.nvvm.wgmma.fence.sync.aligned"), "{ir}");
-    assert!(
-        ir.contains("@llvm.nvvm.wgmma.commit_group.sync.aligned"),
-        "{ir}"
-    );
-    assert!(!ir.contains("@llvm.nvvm.wgmma.commit.group"), "{ir}");
-}
-
-#[test]
-fn pointer_bitcast_cannot_cross_address_spaces_in_either_nvvm_dialect() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "invalid_pointer_bitcast".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let global_pointer = PointerType::get(&ctx, 1);
-    let shared_pointer = PointerType::get(&ctx, 3);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![global_pointer.into()], false);
-    let func = FuncOp::new(&mut ctx, "invalid_cast".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let input = entry.deref(&ctx).get_argument(0);
-    BitcastOp::new(&mut ctx, input, shared_pointer.into())
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    module
-        .get_operation()
-        .deref(&ctx)
-        .verify(&ctx)
-        .expect("upstream bitcast verification currently does not enforce pointer AS equality");
-    for dialect in [NvvmIrDialect::LegacyLlvm7, NvvmIrDialect::Modern] {
-        let error =
-            export_module_to_string_with_config(&ctx, &module, &NvvmExportConfig::new(dialect))
-                .expect_err("a cross-address-space pointer bitcast must be rejected");
-        assert!(
-            error.contains("pointer bitcast cannot cross address spaces 1 -> 3"),
-            "{dialect:?}: {error}"
-        );
-    }
-}
-
-#[test]
-fn addrspacecast_must_change_address_spaces_in_either_nvvm_dialect() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "invalid_addrspacecast".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let shared_pointer = PointerType::get(&ctx, 3);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![shared_pointer.into()], false);
-    let func = FuncOp::new(&mut ctx, "invalid_cast".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let input = entry.deref(&ctx).get_argument(0);
-    AddrSpaceCastOp::new(&mut ctx, input, shared_pointer.into())
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    module
-        .get_operation()
-        .deref(&ctx)
-        .verify(&ctx)
-        .expect("upstream addrspacecast verification currently permits equal address spaces");
-    for dialect in [NvvmIrDialect::LegacyLlvm7, NvvmIrDialect::Modern] {
-        let error =
-            export_module_to_string_with_config(&ctx, &module, &NvvmExportConfig::new(dialect))
-                .expect_err("addrspacecast must not encode a no-op address-space conversion");
-        assert!(
-            error.contains(
-                "addrspacecast must change address spaces; source and result are both address space 3"
-            ),
-            "{dialect:?}: {error}"
-        );
-    }
-}
-
-#[test]
-fn legacy_function_address_defined_later_round_trips_through_indirect_call() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "function_address".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let void_ty = VoidType::get(&ctx);
-    let callee_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
-
-    // Print the caller first to prove symbol typing is a module pre-pass, not
-    // an accidental dependency on textual definition order.
-    let caller = FuncOp::new(
-        &mut ctx,
-        "call_function_pointer".try_into().unwrap(),
-        callee_ty,
-    );
-    let caller_entry = caller.get_or_create_entry_block(&mut ctx);
-    let address = AddressOfOp::new(&mut ctx, "target".try_into().unwrap(), 0);
-    let address_value = address.get_operation().deref(&ctx).get_result(0);
-    address.get_operation().insert_at_back(caller_entry, &ctx);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Indirect(address_value),
-        callee_ty,
-        vec![],
-    )
-    .get_operation()
-    .insert_at_back(caller_entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(caller_entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let target = FuncOp::new(&mut ctx, "target".try_into().unwrap(), callee_ty);
-    let target_entry = target.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(target_entry, &ctx);
-    target.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect("legacy function-address export succeeds");
-    assert!(
-        ir.contains("bitcast void ()* @target to i8*"),
-        "function address must normalize to the canonical byte pointer:\n{ir}"
-    );
-    assert!(
-        ir.contains("bitcast i8*") && ir.contains("to void ()*"),
-        "indirect call must restore the exact function pointer type:\n{ir}"
-    );
-    assert!(ir.contains("call void %"), "{ir}");
-}
-
-#[test]
-fn modern_function_address_uses_the_normalized_definition_name() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "modern_function_address".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let void_ty = VoidType::get(&ctx);
-    let callee_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
-    let prefixed_name = reserved_oxide_symbols::device_symbol("target");
-
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), callee_ty);
-    let caller_entry = caller.get_or_create_entry_block(&mut ctx);
-    let address = AddressOfOp::new(&mut ctx, prefixed_name.as_str().try_into().unwrap(), 0);
-    let address_value = address.get_operation().deref(&ctx).get_result(0);
-    address.get_operation().insert_at_back(caller_entry, &ctx);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Indirect(address_value),
-        callee_ty,
-        vec![],
-    )
-    .get_operation()
-    .insert_at_back(caller_entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(caller_entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let target = FuncOp::new(
-        &mut ctx,
-        prefixed_name.as_str().try_into().unwrap(),
-        callee_ty,
-    );
-    let target_entry = target.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(target_entry, &ctx);
-    target.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect("modern function-address export succeeds");
-    assert!(ir.contains("define void @target()"), "{ir}");
-    assert!(ir.contains("call void @target()"), "{ir}");
-    assert!(!ir.contains(&prefixed_name), "{ir}");
-}
-
-#[test]
-fn modern_addressof_rejects_global_and_function_address_space_mismatches() {
-    let mut ctx = Context::new();
-    let void_ty = VoidType::get(&ctx);
-    let no_args = FuncType::get(&ctx, void_ty.into(), vec![], false);
-
-    let global_module = ModuleOp::new(&mut ctx, "bad_global_address".try_into().unwrap());
-    let global_module_block = module_top_block(&mut ctx, &global_module);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let global = GlobalOp::new(&mut ctx, "shared_value".try_into().unwrap(), i32_ty.into());
-    global.set_address_space(&mut ctx, 3);
-    global
-        .get_operation()
-        .insert_at_back(global_module_block, &ctx);
-    let global_user = FuncOp::new(&mut ctx, "global_user".try_into().unwrap(), no_args);
-    let global_entry = global_user.get_or_create_entry_block(&mut ctx);
-    AddressOfOp::new(&mut ctx, "shared_value".try_into().unwrap(), 0)
-        .get_operation()
-        .insert_at_back(global_entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(global_entry, &ctx);
-    global_user
-        .get_operation()
-        .insert_at_back(global_module_block, &ctx);
-    let error = export_module_to_string_with_config(
-        &ctx,
-        &global_module,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect_err("modern global addressof must preserve address spaces");
-    assert!(
-        error.contains("result is 0, global is 3"),
-        "unexpected global error: {error}"
-    );
-
-    let function_module = ModuleOp::new(&mut ctx, "bad_function_address".try_into().unwrap());
-    let function_module_block = module_top_block(&mut ctx, &function_module);
-    FuncOp::new(&mut ctx, "target".try_into().unwrap(), no_args)
-        .get_operation()
-        .insert_at_back(function_module_block, &ctx);
-    let function_user = FuncOp::new(&mut ctx, "function_user".try_into().unwrap(), no_args);
-    let function_entry = function_user.get_or_create_entry_block(&mut ctx);
-    AddressOfOp::new(&mut ctx, "target".try_into().unwrap(), 3)
-        .get_operation()
-        .insert_at_back(function_entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(function_entry, &ctx);
-    function_user
-        .get_operation()
-        .insert_at_back(function_module_block, &ctx);
-    let error = export_module_to_string_with_config(
-        &ctx,
-        &function_module,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect_err("modern function addressof must use program address space");
-    assert!(error.contains("program-address-space (0)"), "{error}");
-}
-
-#[test]
-fn legacy_device_extern_adapts_exact_pointer_arguments_and_results() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "legacy_extern".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let ptr_ty = PointerType::get(&ctx, 0);
-    let external_ty = FuncType::get(&ctx, ptr_ty.into(), vec![ptr_ty.into()], false);
-    FuncOp::new(&mut ctx, "float_roundtrip".try_into().unwrap(), external_ty)
-        .get_operation()
-        .insert_at_back(module_block, &ctx);
-
-    let void_ty = VoidType::get(&ctx);
-    let caller_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), caller_ty);
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    let pointer = entry.deref(&ctx).get_argument(0);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Direct("float_roundtrip".try_into().unwrap()),
-        external_ty,
-        vec![pointer],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let externs = [DeviceExternDecl {
-        export_name: "float_roundtrip".to_string(),
-        param_types: vec![DeviceExternType::pointer_to(DeviceExternType::Float32, 0)],
-        return_type: DeviceExternType::pointer_to(DeviceExternType::Float32, 0),
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let ir = export_module_with_externs(
-        &ctx,
-        &module,
-        &externs,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect("legacy extern export succeeds");
-
-    assert!(
-        ir.contains("declare float* @float_roundtrip(float*)"),
-        "{ir}"
-    );
-    assert!(ir.contains("bitcast i8* %v0 to float*"), "{ir}");
-    assert!(ir.contains("call float* @float_roundtrip(float*"), "{ir}");
-    assert!(
-        ir.contains(" = bitcast float* ") && ir.contains(" to i8*"),
-        "{ir}"
-    );
-    assert!(
-        !ir.split(|c: char| !c.is_ascii_alphanumeric())
-            .any(|token| token == "ptr"),
-        "{ir}"
-    );
-}
-
-#[test]
-fn legacy_device_extern_preserves_pointer_address_spaces() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "legacy_extern_as".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let ptr_ty = PointerType::get(&ctx, 3);
-    let void_ty = VoidType::get(&ctx);
-    let external_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
-    FuncOp::new(&mut ctx, "shared_float".try_into().unwrap(), external_ty)
-        .get_operation()
-        .insert_at_back(module_block, &ctx);
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), external_ty);
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    let pointer = entry.deref(&ctx).get_argument(0);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Direct("shared_float".try_into().unwrap()),
-        external_ty,
-        vec![pointer],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let externs = [DeviceExternDecl {
-        export_name: "shared_float".to_string(),
-        param_types: vec![DeviceExternType::pointer_to(DeviceExternType::Float32, 3)],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let ir = export_module_with_externs(
-        &ctx,
-        &module,
-        &externs,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect("legacy extern export succeeds");
-    assert!(
-        ir.contains("declare void @shared_float(float addrspace(3)*)"),
-        "{ir}"
-    );
-    assert!(
-        ir.contains("bitcast i8 addrspace(3)* %v0 to float addrspace(3)*"),
-        "{ir}"
-    );
-}
-
-#[test]
-fn modern_device_extern_erases_pointee_without_boundary_casts() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "modern_extern".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let ptr_ty = PointerType::get(&ctx, 0);
-    let void_ty = VoidType::get(&ctx);
-    let external_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
-    FuncOp::new(&mut ctx, "takes_float".try_into().unwrap(), external_ty)
-        .get_operation()
-        .insert_at_back(module_block, &ctx);
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), external_ty);
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    let pointer = entry.deref(&ctx).get_argument(0);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Direct("takes_float".try_into().unwrap()),
-        external_ty,
-        vec![pointer],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let externs = [DeviceExternDecl {
-        export_name: "takes_float".to_string(),
-        param_types: vec![DeviceExternType::pointer_to(DeviceExternType::Float32, 0)],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let ir = export_module_with_externs(
-        &ctx,
-        &module,
-        &externs,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect("modern extern export succeeds");
-    assert!(ir.contains("declare void @takes_float(ptr)"), "{ir}");
-    assert!(ir.contains("call void @takes_float(ptr %v0)"), "{ir}");
-    assert!(!ir.contains("bitcast"), "{ir}");
-}
-
-#[test]
-fn device_extern_rejects_invalid_symbol_and_address_space_mismatch() {
-    let mut ctx = Context::new();
-    let empty = ModuleOp::new(&mut ctx, "empty".try_into().unwrap());
-    let invalid = [DeviceExternDecl {
-        export_name: "bad.name".to_string(),
-        param_types: vec![],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let err = export_module_with_externs(
-        &ctx,
-        &empty,
-        &invalid,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("invalid NVVM symbol must fail");
-    assert!(err.contains("global-identifier subset"), "{err}");
-
-    let reserved_intrinsic_prefix = [DeviceExternDecl {
-        export_name: "llvm_external".to_string(),
-        param_types: vec![],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let err = export_module_with_externs(
-        &ctx,
-        &empty,
-        &reserved_intrinsic_prefix,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("the reserved intrinsic namespace must not be ambiguous");
-    assert!(err.contains("reserves for LLVM intrinsics"), "{err}");
-
-    let by_value_array = [DeviceExternDecl {
-        export_name: "array_by_value".to_string(),
-        param_types: vec![DeviceExternType::Array {
-            element: Box::new(DeviceExternType::Float32),
-            len: 4,
-        }],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let err = export_module_with_externs(
-        &ctx,
-        &empty,
-        &by_value_array,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("by-value aggregate externs must be rejected");
-    assert!(err.contains("passes an array by value"), "{err}");
-
-    let nested_half = [DeviceExternDecl {
-        export_name: "half_buffer".to_string(),
-        param_types: vec![DeviceExternType::pointer_to(
-            DeviceExternType::Array {
-                element: Box::new(DeviceExternType::Float16),
-                len: 4,
-            },
-            0,
-        )],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let err = export_module_with_externs(
-        &ctx,
-        &empty,
-        &nested_half,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("legacy half nested in a pointer must fail");
-    assert!(
-        err.contains("CUDA 12 legacy") && err.contains("half"),
-        "{err}"
-    );
-    let modern = export_module_with_externs(
-        &ctx,
-        &empty,
-        &nested_half,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect("modern opaque-pointer extern may use half pointees");
-    assert!(
-        modern.contains("declare void @half_buffer(ptr)"),
-        "{modern}"
-    );
-
-    let module = ModuleOp::new(&mut ctx, "mismatch".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let ptr0 = PointerType::get(&ctx, 0);
-    let void_ty = VoidType::get(&ctx);
-    let external_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr0.into()], false);
-    FuncOp::new(&mut ctx, "shared_only".try_into().unwrap(), external_ty)
-        .get_operation()
-        .insert_at_back(module_block, &ctx);
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), external_ty);
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    let pointer = entry.deref(&ctx).get_argument(0);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Direct("shared_only".try_into().unwrap()),
-        external_ty,
-        vec![pointer],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-    let mismatch = [DeviceExternDecl {
-        export_name: "shared_only".to_string(),
-        param_types: vec![DeviceExternType::pointer_to(DeviceExternType::Float32, 3)],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let err = export_module_with_externs(
-        &ctx,
-        &module,
-        &mismatch,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("address-space mismatch must fail");
-    assert!(
-        err.contains("parameter, result, or pointer address-space types"),
-        "{err}"
-    );
-}
-
-#[test]
-fn device_extern_rejects_same_name_declaration_shape_without_a_call() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "extern_decl_conflict".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let void_ty = VoidType::get(&ctx);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let lowered_type = FuncType::get(&ctx, void_ty.into(), vec![i32_ty.into()], false);
-    FuncOp::new(
-        &mut ctx,
-        "conflicting_decl".try_into().unwrap(),
-        lowered_type,
-    )
-    .get_operation()
-    .insert_at_back(module_block, &ctx);
-
-    let externs = [DeviceExternDecl {
-        export_name: "conflicting_decl".to_string(),
-        param_types: vec![DeviceExternType::Float32],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let error = export_module_with_externs(
-        &ctx,
-        &module,
-        &externs,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("the exporter must independently reject a conflicting declaration");
-    assert!(
-        error.contains("parameter, result, or pointer address-space types"),
-        "{error}"
-    );
-}
-
-#[test]
-fn device_extern_rejects_definition_and_address_taken_shape_conflicts() {
-    let mut ctx = Context::new();
-    let void_ty = VoidType::get(&ctx);
-
-    let definition_module = ModuleOp::new(&mut ctx, "extern_definition".try_into().unwrap());
-    let definition_block = module_top_block(&mut ctx, &definition_module);
-    let no_args = FuncType::get(&ctx, void_ty.into(), vec![], false);
-    let definition = FuncOp::new(&mut ctx, "defined_external".try_into().unwrap(), no_args);
-    let definition_entry = definition.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(definition_entry, &ctx);
-    definition
-        .get_operation()
-        .insert_at_back(definition_block, &ctx);
-    let definition_extern = [DeviceExternDecl {
-        export_name: "defined_external".to_string(),
-        param_types: vec![],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let error = export_module_with_externs(
-        &ctx,
-        &definition_module,
-        &definition_extern,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("a side-table extern must not collide with a definition");
-    assert!(error.contains("function definition"), "{error}");
-
-    let address_module = ModuleOp::new(&mut ctx, "extern_address".try_into().unwrap());
-    let address_block = module_top_block(&mut ctx, &address_module);
-    let generic_pointer = PointerType::get(&ctx, 0);
-    let lowered_type = FuncType::get(&ctx, void_ty.into(), vec![generic_pointer.into()], false);
-    FuncOp::new(
-        &mut ctx,
-        "addressed_external".try_into().unwrap(),
-        lowered_type,
-    )
-    .get_operation()
-    .insert_at_back(address_block, &ctx);
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), lowered_type);
-    let caller_entry = caller.get_or_create_entry_block(&mut ctx);
-    let argument = caller_entry.deref(&ctx).get_argument(0);
-    let address = AddressOfOp::new(&mut ctx, "addressed_external".try_into().unwrap(), 0);
-    let address_value = address.get_operation().deref(&ctx).get_result(0);
-    address.get_operation().insert_at_back(caller_entry, &ctx);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Indirect(address_value),
-        lowered_type,
-        vec![argument],
-    )
-    .get_operation()
-    .insert_at_back(caller_entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(caller_entry, &ctx);
-    caller.get_operation().insert_at_back(address_block, &ctx);
-    let address_extern = [DeviceExternDecl {
-        export_name: "addressed_external".to_string(),
-        param_types: vec![DeviceExternType::pointer_to(DeviceExternType::Float32, 3)],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let error = export_module_with_externs(
-        &ctx,
-        &address_module,
-        &address_extern,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("address-taking must not bypass exact extern shape validation");
-    assert!(
-        error.contains("parameter, result, or pointer address-space types"),
-        "{error}"
-    );
-}
-
-#[test]
-fn legacy_kernel_metadata_uses_typed_function_references() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "legacy_metadata".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let ptr_ty = PointerType::get(&ctx, 0);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
-    let func = FuncOp::new(&mut ctx, "metadata_kernel".try_into().unwrap(), func_ty);
-    func.get_operation().deref_mut(&ctx).attributes.set(
-        "gpu_kernel".try_into().unwrap(),
-        StringAttr::new("true".into()),
-    );
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7);
-    let ir = export_module_to_string_with_config(&ctx, &module, &config)
-        .expect("legacy metadata export succeeds");
-    assert!(
-        ir.contains(
-            "@llvm.used = appending global [1 x i8*] [i8* bitcast (void (i8*)* @metadata_kernel to i8*)]"
-        ),
-        "{ir}"
-    );
-    assert!(
-        ir.contains("!{void (i8*)* @metadata_kernel, !\"kernel\", i32 1}"),
-        "{ir}"
-    );
-}
-
-#[test]
-fn llvm_used_roots_only_explicitly_retained_globals() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "retained_globals".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-
-    let retained = GlobalOp::new(&mut ctx, "IKET_META".try_into().unwrap(), i32_ty.into());
-    retained.set_address_space(&mut ctx, 1);
-    retained.mark_retained(&mut ctx);
-    retained.get_operation().insert_at_back(module_block, &ctx);
-
-    let ordinary = GlobalOp::new(&mut ctx, "ORDINARY".try_into().unwrap(), i32_ty.into());
-    ordinary.set_address_space(&mut ctx, 1);
-    ordinary.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string_with_config(&ctx, &module, &PtxExportConfig)
-        .expect("retained global export succeeds");
-    assert!(
-        ir.contains(
-            "@llvm.used = appending global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @IKET_META to ptr)], section \"llvm.metadata\""
-        ),
-        "{ir}"
-    );
-    assert!(!ir.contains("@ORDINARY to ptr"), "{ir}");
-}
-
-#[test]
-fn legacy_llvm_used_roots_retained_address_space_global() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "legacy_retained_global".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let retained = GlobalOp::new(&mut ctx, "IKET_META".try_into().unwrap(), i32_ty.into());
-    retained.set_address_space(&mut ctx, 1);
-    retained.mark_retained(&mut ctx);
-    retained.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7);
-    let ir = export_module_to_string_with_config(&ctx, &module, &config)
-        .expect("legacy retained global export succeeds");
-    assert!(
-        ir.contains(
-            "@llvm.used = appending global [1 x i8*] [i8* addrspacecast (i32 addrspace(1)* @IKET_META to i8*)], section \"llvm.metadata\""
-        ),
-        "{ir}"
-    );
-}
-
-#[test]
-fn ptx_export_records_kernel_roots_for_internalization() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "ptx_roots".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let global = GlobalOp::new(&mut ctx, "COEFFS".try_into().unwrap(), i32_ty.into());
-    global.set_address_space(&mut ctx, 4);
-    global.get_operation().insert_at_back(module_block, &ctx);
-    let func_ty = FuncType::get(&ctx, VoidType::get(&ctx).into(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "entry_kernel".try_into().unwrap(), func_ty);
-    func.get_operation().deref_mut(&ctx).attributes.set(
-        "gpu_kernel".try_into().unwrap(),
-        StringAttr::new("true".into()),
-    );
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let exported = export_module_with_externs_and_roots::<DeviceExternDecl>(
-        &ctx,
-        &module,
-        &[],
-        &PtxExportConfig,
-    )
-    .expect("PTX export succeeds");
-    let ir = exported.llvm_ir;
-    assert!(
-        ir.contains(
-            "@llvm.used = appending global [1 x ptr] [ptr @entry_kernel], section \"llvm.metadata\""
-        ),
-        "{ir}"
-    );
-    assert_eq!(exported.public_symbols, ["COEFFS", "entry_kernel"]);
-}
-
-#[test]
-fn ptx_export_records_standalone_device_function_roots_for_internalization() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "ptx_device_root".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let func_ty = FuncType::get(&ctx, VoidType::get(&ctx).into(), vec![], false);
-    let prefixed_name = format!(
-        "{}standalone_export",
-        reserved_oxide_symbols::LEGACY_DEVICE_PREFIX
-    );
-    let func = FuncOp::new(
-        &mut ctx,
-        prefixed_name.as_str().try_into().unwrap(),
-        func_ty,
-    );
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let exported = export_module_with_externs_and_roots::<DeviceExternDecl>(
-        &ctx,
-        &module,
-        &[],
-        &PtxExportConfig,
-    )
-    .expect("standalone PTX export succeeds");
-    assert_eq!(exported.public_symbols, ["standalone_export"]);
-    assert!(
-        exported.llvm_ir.contains(
-            "@llvm.used = appending global [1 x ptr] [ptr @standalone_export], section \"llvm.metadata\""
-        ),
-        "{}",
-        exported.llvm_ir
-    );
-}
-
-#[test]
-fn legacy_export_rejects_debug_metadata() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "legacy_debug".try_into().unwrap());
-    let config = DebugConfig {
-        inner: NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-        debug_kind: DebugKind::LineTables,
-    };
-
-    let error = export_module_to_string_with_config(&ctx, &module, &config)
-        .expect_err("legacy debug output must be rejected");
-    assert!(error.contains("legacy LLVM 7"), "{error}");
-    assert!(error.contains("debug"), "{error}");
-}
-
-#[test]
-fn legacy_pointer_slot_is_recursively_canonical() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "legacy_pointer_slot".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let ptr_ty = PointerType::get(&ctx, 0);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
-    let func = FuncOp::new(&mut ctx, "pointer_slot".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let incoming = entry.deref(&ctx).get_argument(0);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
-    let one = ConstantOp::new(&mut ctx, one_attr.into());
-    let one_value = one.get_operation().deref(&ctx).get_result(0);
-    one.get_operation().insert_at_back(entry, &ctx);
-
-    let slot = AllocaOp::new(&mut ctx, ptr_ty.into(), one_value);
-    let slot_value = slot.get_operation().deref(&ctx).get_result(0);
-    slot.get_operation().insert_at_back(entry, &ctx);
-    StoreOp::new(&mut ctx, incoming, slot_value)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    LoadOp::new(&mut ctx, slot_value, ptr_ty.into())
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect("legacy pointer-slot export succeeds");
-    assert!(ir.contains("alloca i8*"), "{ir}");
-    assert!(ir.contains("bitcast i8**"), "{ir}");
-    assert!(ir.matches("to i8**").count() >= 2, "{ir}");
-    assert!(ir.contains("store i8* %v0, i8**"), "{ir}");
-    assert!(ir.contains("load i8*, i8**"), "{ir}");
-}
-
-#[test]
-fn export_addressof_uses_symbol_when_definition_block_prints_later() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let existing = {
-            let region = module_region.deref(&ctx);
-            region.iter(&ctx).next()
-        };
-        if let Some(block) = existing {
-            block
-        } else {
-            let block = BasicBlock::new(&mut ctx, None, vec![]);
-            block.insert_at_back(module_region, &ctx);
-            block
-        }
-    };
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let global = GlobalOp::new(
-        &mut ctx,
-        "__shared_mem_20".try_into().unwrap(),
-        i32_ty.to_handle(),
-    );
-    global.set_address_space(&mut ctx, 3);
-    global.get_operation().insert_at_back(module_block, &ctx);
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "uses_late_addressof".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let func_region = func.get_operation().deref(&ctx).get_region(0);
-    let use_block = BasicBlock::new(&mut ctx, None, vec![]);
-    use_block.insert_at_back(func_region, &ctx);
-    let address_block = BasicBlock::new(&mut ctx, None, vec![]);
-    address_block.insert_at_back(func_region, &ctx);
-
-    BrOp::new(&mut ctx, address_block, vec![])
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-
-    let address = AddressOfOp::new(&mut ctx, "__shared_mem_20".try_into().unwrap(), 3);
-    let address_value = address.get_operation().deref(&ctx).get_result(0);
-    address.get_operation().insert_at_back(address_block, &ctx);
-    BrOp::new(&mut ctx, use_block, vec![])
-        .get_operation()
-        .insert_at_back(address_block, &ctx);
-
-    let gep = GetElementPtrOp::new(
-        &mut ctx,
-        address_value,
-        vec![GepIndex::Constant(0)],
-        i32_ty.to_handle(),
-    );
-    gep.get_operation().insert_at_back(use_block, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(use_block, &ctx);
-
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
-
-    // The shared global must be declared at module scope.
-    assert!(
-        ir.contains("@__shared_mem_20 = addrspace(3) global"),
-        "module must declare the shared global:\n{ir}"
-    );
-
-    // The GEP base operand must be the global symbol, not a stale `%vN`.
-    let gep_line = ir
-        .lines()
-        .find(|line| line.contains("getelementptr inbounds"))
-        .expect("exported GEP line");
-    assert!(
-        gep_line.contains("@__shared_mem_20"),
-        "GEP must use the global symbol, not a stale temporary:\n{ir}"
-    );
-
-    // Bug class from issue #54: every `%vN` reference in the IR must have a
-    // matching `%vN = ...` definition. With the bug present the addressof
-    // result was named `%v1` but never defined; this catches that and any
-    // future regression that re-introduces a dangling SSA reference.
-    assert_no_undefined_temporaries(&ir);
-
-    let legacy = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect("legacy addressof export succeeds");
-    assert!(
-        legacy.contains("@__shared_mem_20 = addrspace(3) global i32 undef"),
-        "NVVM shared globals must be uninitialized:\n{legacy}"
-    );
-    assert!(
-        legacy.contains("bitcast i32 addrspace(3)* @__shared_mem_20 to i8 addrspace(3)*"),
-        "legacy addressof must normalize the global pointer:\n{legacy}"
-    );
-    assert!(
-        legacy.contains("bitcast i8 addrspace(3)*") && legacy.contains("to i32 addrspace(3)*"),
-        "legacy GEP must repair its canonical base pointer:\n{legacy}"
-    );
-    assert_no_undefined_temporaries(&legacy);
-}
-
-/// Export a module holding one shared global, optionally labelled with the
-/// Rust path of the `static` it came from.
-fn export_shared_global_with_source_name(source_name: Option<&str>) -> String {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let array_ty = ArrayType::get(&ctx, i32_ty.to_handle(), 64);
-    let global = GlobalOp::new(
-        &mut ctx,
-        "__shared_mem_7".try_into().unwrap(),
-        array_ty.to_handle(),
-    );
-    global.set_address_space(&mut ctx, 3);
-    if let Some(source_name) = source_name {
-        global.set_shared_source_name(&mut ctx, source_name);
-    }
-    global.get_operation().insert_at_back(module_block, &ctx);
-
-    export_module_to_string(&ctx, &module).expect("export succeeds")
-}
-
-#[test]
-fn shared_global_source_name_is_exported_as_a_comment_above_the_definition() {
-    let ir = export_shared_global_with_source_name(Some("my_kernel::TILE"));
-
-    let definition_index = ir
-        .find("@__shared_mem_7 = addrspace(3) global")
-        .expect("module must declare the shared global");
-    let comment_index = ir
-        .find("; shared source: my_kernel::TILE")
-        .unwrap_or_else(|| panic!("shared global must name its Rust source:\n{ir}"));
-    assert!(
-        comment_index < definition_index,
-        "the source comment must precede the definition it describes:\n{ir}"
-    );
-}
-
-#[test]
-fn shared_global_without_a_source_name_exports_no_comment() {
-    let ir = export_shared_global_with_source_name(None);
-
-    assert!(
-        ir.contains("@__shared_mem_7 = addrspace(3) global"),
-        "module must declare the shared global:\n{ir}"
-    );
-    assert!(
-        !ir.contains("; shared source:"),
-        "an unlabelled global must not gain a comment:\n{ir}"
-    );
-}
-
-#[test]
-fn shared_global_source_name_cannot_escape_its_comment_line() {
-    // A newline in the label would end the comment and leave the remainder to
-    // be parsed as IR. Nothing in the current pipeline produces such a name,
-    // so this pins the exporter's own guarantee rather than a live bug.
-    let ir = export_shared_global_with_source_name(Some("EVIL\n@injected = addrspace(3) global"));
-
-    assert!(
-        ir.lines().all(|line| !line.starts_with("@injected")),
-        "a control character in the label must not open a new IR line:\n{ir}"
-    );
-    assert!(
-        ir.contains("; shared source: EVIL @injected = addrspace(3) global"),
-        "the label must survive on one line with controls flattened:\n{ir}"
-    );
-}
-
-#[test]
-fn nvvm_export_rejects_invalid_global_address_spaces() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let global = GlobalOp::new(
-        &mut ctx,
-        "thread_local_global".try_into().unwrap(),
-        i32_ty.to_handle(),
-    );
-    global.set_address_space(&mut ctx, 5);
-    global.get_operation().insert_at_back(module_block, &ctx);
-
-    let error = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("NVVM module-scope local-memory global must be rejected");
-    assert!(error.contains("unsupported address space 5"), "{error}");
-
-    // The ordinary LLVM/PTX exporter retains its prior behavior; this
-    // restriction is specifically part of the NVVM IR contract.
-    assert!(export_module_to_string(&ctx, &module).is_ok());
-}
-
-#[test]
-fn initialized_globals_export_exact_bytes() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "exact_global_bytes".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-
-    // 0x7fc01234 is a quiet f32 NaN with a non-canonical payload. Treating
-    // these bytes as an f32 before printing would collapse it to 0x7fc00000.
-    let nan_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
-    let nan = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "nan_payload".try_into().unwrap(),
-        nan_ty.into(),
-        4,
-    );
-    nan.set_address_space(&mut ctx, 1);
-    nan.set_initializer_hex(&mut ctx, "3412c07f");
-    nan.get_operation().insert_at_back(module_block, &ctx);
-
-    // Byte 0 is a u8, bytes 1..4 are zeroed repr(C) padding, and bytes 4..8
-    // are a little-endian u32. The exporter must not recompute those offsets.
-    let padded_ty = ArrayType::get(&ctx, i8_ty.into(), 8);
-    let padded = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "padded_struct".try_into().unwrap(),
-        padded_ty.into(),
-        4,
-    );
-    padded.set_address_space(&mut ctx, 1);
-    padded.set_initializer_hex(&mut ctx, "ab00000078563412");
-    padded.get_operation().insert_at_back(module_block, &ctx);
-
-    for config in [
-        NvvmExportConfig::new(NvvmIrDialect::Modern),
-        NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    ] {
-        let ir = export_module_to_string_with_config(&ctx, &module, &config)
-            .expect("byte-exact global export succeeds");
-        assert!(
-            ir.contains(r#"@nan_payload = addrspace(1) global [4 x i8] c"\34\12\C0\7F", align 4"#),
-            "NaN payload bytes changed:\n{ir}"
-        );
-        assert!(
-            ir.contains(
-                r#"@padded_struct = addrspace(1) global [8 x i8] c"\AB\00\00\00\78\56\34\12", align 4"#
-            ),
-            "repr(C) layout bytes changed:\n{ir}"
-        );
-    }
-}
-
-#[test]
-fn immutable_globals_export_the_constant_keyword() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "constant_keyword".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let table_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
-
-    // The compiler's own promoted table: marked never-written, so it must
-    // export as `constant`. That keyword is the whole point of the marker:
-    // it is what lets `opt` treat reads as invariant (deleting a copy into a
-    // stack slot) and what makes `llc` select `ld.global.nc`.
-    let promoted = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "promoted_table".try_into().unwrap(),
-        table_ty.into(),
-        4,
-    );
-    promoted.set_address_space(&mut ctx, 1);
-    promoted.set_initializer_hex(&mut ctx, "01020304");
-    promoted.mark_immutable(&mut ctx);
-    promoted.get_operation().insert_at_back(module_block, &ctx);
-
-    // An identically shaped global without the marker: the host may still
-    // write such storage by symbol, so it must keep `global`. Immutability is
-    // opt-in per global, never inferred from the shape of the initializer.
-    let plain = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "plain_static".try_into().unwrap(),
-        table_ty.into(),
-        4,
-    );
-    plain.set_address_space(&mut ctx, 1);
-    plain.set_initializer_hex(&mut ctx, "01020304");
-    plain.get_operation().insert_at_back(module_block, &ctx);
-
-    for config in [
-        NvvmExportConfig::new(NvvmIrDialect::Modern),
-        NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    ] {
-        let ir = export_module_to_string_with_config(&ctx, &module, &config)
-            .expect("immutable global export succeeds");
-        assert!(
-            ir.contains(
-                r#"@promoted_table = addrspace(1) constant [4 x i8] c"\01\02\03\04", align 4"#
-            ),
-            "promoted global lost the constant keyword:\n{ir}"
-        );
-        assert!(
-            ir.contains(r#"@plain_static = addrspace(1) global [4 x i8] c"\01\02\03\04", align 4"#),
-            "unmarked global must not become constant:\n{ir}"
-        );
-    }
-}
-
-#[test]
-fn initialized_global_exports_static_pointer_relocation() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "static_relocation".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-
-    // Insert the reference first. Module symbol indexing must make relocation
-    // resolution independent of textual global order.
-    let reference_ty = StructType::get_unnamed(&ctx, (vec![i64_ty.into()], StructLayout::Unpacked));
-    let reference = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "reference".try_into().unwrap(),
-        reference_ty.into(),
-        8,
-    );
-    reference.set_address_space(&mut ctx, 1);
-    reference.set_source_global_key(&mut ctx, "REFERENCE");
-    reference.set_initializer_hex(&mut ctx, "0000000000000000");
-    let encoded = encode_global_initializer_relocations(&[GlobalInitializerRelocation {
-        source_offset: 0,
-        width_bytes: 8,
-        target_address_space: 1,
-        target_addend: 0,
-        target_key: "TARGET".to_string(),
-    }]);
-    reference.set_initializer_relocations(&mut ctx, &encoded);
-    reference.get_operation().insert_at_back(module_block, &ctx);
-
-    let target_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
-    let target =
-        GlobalOp::new_with_alignment(&mut ctx, "target".try_into().unwrap(), target_ty.into(), 4);
-    target.set_address_space(&mut ctx, 1);
-    target.set_source_global_key(&mut ctx, "TARGET");
-    target.set_initializer_hex(&mut ctx, "78563412");
-    target.get_operation().insert_at_back(module_block, &ctx);
-
-    let modern = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect("modern relocated initializer export succeeds");
-    assert!(
-        modern.contains(
-            "@reference = addrspace(1) global { i64 } { i64 ptrtoint (ptr addrspacecast (ptr addrspace(1) @target to ptr) to i64) }, align 8"
-        ),
-        "{modern}"
-    );
-
-    let legacy = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect("legacy relocated initializer export succeeds");
-    assert!(
-        legacy.contains(
-            "@reference = addrspace(1) global { i64 } { i64 ptrtoint (i8* addrspacecast (i8 addrspace(1)* bitcast ([4 x i8] addrspace(1)* @target to i8 addrspace(1)*) to i8*) to i64) }, align 8"
-        ),
-        "{legacy}"
-    );
-}
-
-#[test]
-fn initialized_global_exports_unaligned_pointer_relocation_as_packed_storage() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "packed_static_relocation".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-
-    let literal_ty = ArrayType::get(&ctx, i8_ty.into(), 1);
-    let reference_ty = StructType::get_unnamed(
-        &ctx,
-        (vec![literal_ty.into(), i64_ty.into()], StructLayout::Packed),
-    );
-    let reference = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "packed_reference".try_into().unwrap(),
-        reference_ty.into(),
-        1,
-    );
-    reference.set_address_space(&mut ctx, 1);
-    reference.set_source_global_key(&mut ctx, "PACKED_REFERENCE");
-    reference.set_initializer_hex(&mut ctx, "7b0000000000000000");
-    let encoded = encode_global_initializer_relocations(&[GlobalInitializerRelocation {
-        source_offset: 1,
-        width_bytes: 8,
-        target_address_space: 1,
-        target_addend: 0,
-        target_key: "TARGET".to_string(),
-    }]);
-    reference.set_initializer_relocations(&mut ctx, &encoded);
-    reference.get_operation().insert_at_back(module_block, &ctx);
-
-    let target_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
-    let target =
-        GlobalOp::new_with_alignment(&mut ctx, "target".try_into().unwrap(), target_ty.into(), 4);
-    target.set_address_space(&mut ctx, 1);
-    target.set_source_global_key(&mut ctx, "TARGET");
-    target.set_initializer_hex(&mut ctx, "78563412");
-    target.get_operation().insert_at_back(module_block, &ctx);
-
-    let modern = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect("modern packed relocated initializer export succeeds");
-    assert!(
-        modern.contains(
-            r#"@packed_reference = addrspace(1) global <{ [1 x i8], i64 }> <{ [1 x i8] c"\7B", i64 ptrtoint (ptr addrspacecast (ptr addrspace(1) @target to ptr) to i64) }>, align 1"#
-        ),
-        "{modern}"
-    );
-
-    let legacy = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect("legacy packed relocated initializer export succeeds");
-    assert!(
-        legacy.contains(
-            r#"@packed_reference = addrspace(1) global <{ [1 x i8], i64 }> <{ [1 x i8] c"\7B", i64 ptrtoint (i8* addrspacecast (i8 addrspace(1)* bitcast ([4 x i8] addrspace(1)* @target to i8 addrspace(1)*) to i8*) to i64) }>, align 1"#
-        ),
-        "{legacy}"
-    );
-}
-
-#[test]
-fn initialized_global_exports_multiple_relocations_and_addends() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "multiple_static_relocations".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-
-    let target_a_ty = ArrayType::get(&ctx, i8_ty.into(), 16);
-    let target_a = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "target_a".try_into().unwrap(),
-        target_a_ty.into(),
-        8,
-    );
-    target_a.set_address_space(&mut ctx, 1);
-    target_a.set_source_global_key(&mut ctx, "TARGET_A");
-    target_a.set_initializer_hex(&mut ctx, "000102030405060708090a0b0c0d0e0f");
-    target_a.get_operation().insert_at_back(module_block, &ctx);
-
-    let target_b_ty = ArrayType::get(&ctx, i8_ty.into(), 8);
-    let target_b = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "target_b".try_into().unwrap(),
-        target_b_ty.into(),
-        8,
-    );
-    target_b.set_address_space(&mut ctx, 4);
-    target_b.set_source_global_key(&mut ctx, "TARGET_B");
-    target_b.set_initializer_hex(&mut ctx, "1011121314151617");
-    target_b.get_operation().insert_at_back(module_block, &ctx);
-
-    let table_ty = StructType::get_unnamed(
-        &ctx,
-        (vec![i64_ty.into(), i64_ty.into()], StructLayout::Unpacked),
-    );
-    let table = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "reference_table".try_into().unwrap(),
-        table_ty.into(),
-        8,
-    );
-    table.set_address_space(&mut ctx, 1);
-    table.set_source_global_key(&mut ctx, "REFERENCE_TABLE");
-    table.set_initializer_hex(&mut ctx, "00000000000000000000000000000000");
-    let encoded = encode_global_initializer_relocations(&[
-        GlobalInitializerRelocation {
-            source_offset: 0,
-            width_bytes: 8,
-            target_address_space: 1,
-            target_addend: 4,
-            target_key: "TARGET_A".to_string(),
-        },
-        GlobalInitializerRelocation {
-            source_offset: 8,
-            width_bytes: 8,
-            target_address_space: 4,
-            target_addend: 0,
-            target_key: "TARGET_B".to_string(),
-        },
-    ]);
-    table.set_initializer_relocations(&mut ctx, &encoded);
-    table.get_operation().insert_at_back(module_block, &ctx);
-
-    for dialect in [NvvmIrDialect::Modern, NvvmIrDialect::LegacyLlvm7] {
-        let ir =
-            export_module_to_string_with_config(&ctx, &module, &NvvmExportConfig::new(dialect))
-                .expect("relocated initializer export succeeds");
-        assert!(
-            ir.contains("@reference_table = addrspace(1) global { i64, i64 }"),
-            "{ir}"
-        );
-        assert!(ir.contains("getelementptr (i8"), "{ir}");
-        assert!(ir.contains("@target_a"), "{ir}");
-        assert!(ir.contains("@target_b"), "{ir}");
-        assert!(!ir.contains("inttoptr"), "{ir}");
-    }
-}
-
-#[test]
-fn initialized_global_relocation_rejects_unknown_target_key() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "unknown_relocation_target".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let reference_ty = StructType::get_unnamed(&ctx, (vec![i64_ty.into()], StructLayout::Unpacked));
-    let reference = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "reference".try_into().unwrap(),
-        reference_ty.into(),
-        8,
-    );
-    reference.set_address_space(&mut ctx, 1);
-    reference.set_source_global_key(&mut ctx, "REFERENCE");
-    reference.set_initializer_hex(&mut ctx, "0000000000000000");
-    let encoded = encode_global_initializer_relocations(&[GlobalInitializerRelocation {
-        source_offset: 0,
-        width_bytes: 8,
-        target_address_space: 1,
-        target_addend: 0,
-        target_key: "MISSING".to_string(),
-    }]);
-    reference.set_initializer_relocations(&mut ctx, &encoded);
-    reference.get_operation().insert_at_back(module_block, &ctx);
-
-    let error = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect_err("unknown relocation target must fail");
-    assert!(
-        error.contains("unknown rustc global key `MISSING`"),
-        "{error}"
-    );
-}
-
-#[test]
-fn export_inline_asm_respects_sideeffect_marker() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "has_inline_asm".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-
-    let default_asm = InlineAsmOp::new(&mut ctx, void_ty.into(), vec![], "bar.sync 0;", "", false);
-    default_asm.get_operation().insert_at_back(entry, &ctx);
-
-    let register_only_asm = InlineAsmOp::new(&mut ctx, void_ty.into(), vec![], "nop;", "", true);
-    llvm_export::ops::set_inline_asm_sideeffect(&mut ctx, register_only_asm.get_operation(), false);
-    register_only_asm
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
-
-    assert!(
-        ir.contains("call void asm sideeffect \"bar.sync 0;\", \"\"()"),
-        "inline asm without an explicit marker should remain conservative:\n{ir}"
-    );
-    assert!(
-        ir.contains("call void asm \"nop;\", \"\"() #0"),
-        "inline asm marked sideeffect=false should omit the keyword while preserving convergent:\n{ir}"
-    );
-    assert!(
-        ir.contains("attributes #0 = { convergent }"),
-        "convergent inline asm must emit the convergent attr group:\n{ir}"
-    );
-}
-
-#[test]
-fn export_inline_asm_escapes_llvm_string_literals() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(
-        &mut ctx,
-        "has_escaped_inline_asm".try_into().unwrap(),
-        func_ty,
-    );
-    let entry = func.get_or_create_entry_block(&mut ctx);
-
-    let asm = InlineAsmOp::new(
-        &mut ctx,
-        void_ty.into(),
-        vec![],
-        "mov.u32 $0, %laneid;\n// \"quoted\" \\22",
-        "~{memory}\\raw",
-        false,
-    );
-    asm.get_operation().insert_at_back(entry, &ctx);
-
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
-
-    assert!(
-        ir.contains(
-            "call void asm sideeffect \"mov.u32 $0, %laneid;\\0A// \\22quoted\\22 \\5C22\", \"~{memory}\\5Craw\"()"
-        ),
-        "inline asm template and constraints must be escaped as LLVM string literals:\n{ir}"
-    );
-}
-
-#[test]
-fn nvvm_metadata_version_uses_next_allocated_metadata_id() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "bounded_kernel".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let width = NonZero::new(32).unwrap();
-    let max_threads = IntegerAttr::new(u32_ty, APInt::from_u32(256, width));
-    let min_blocks = IntegerAttr::new(u32_ty, APInt::from_u32(2, width));
-
-    {
-        let attrs = &mut func.get_operation().deref_mut(&ctx).attributes;
-        attrs.set(
-            Identifier::try_from("gpu_kernel").unwrap(),
-            StringAttr::new("true".into()),
-        );
-        attrs.set(Identifier::try_from("maxntid").unwrap(), max_threads);
-        attrs.set(Identifier::try_from("minctasm").unwrap(), min_blocks);
-    }
-
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string_with_config(&ctx, &module, &NvvmExportConfig::default())
-        .expect("NVVM export succeeds");
-
-    assert!(
-        ir.contains("!0 = !{ptr @bounded_kernel, !\"kernel\", i32 1}"),
-        "a launch-bounded kernel still needs its kernel annotation:\n{ir}"
-    );
-    assert!(
-        ir.contains("!nvvm.annotations = !{!0, !1, !2, !3, !4}"),
-        "kernel identity plus launch-bounds annotations should occupy !0..!4:\n{ir}"
-    );
-    assert!(
-        ir.contains("!nvvmir.version = !{!5}\n!5 = !{i32 2, i32 0, i32 3, i32 2}"),
-        "version metadata should use the next allocated ID:\n{ir}"
-    );
-}
-
-#[test]
-fn line_table_debug_metadata_emits_function_scope_and_instruction_locations() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
-    llvm_export::ops::set_debug_function_name(
-        &mut ctx,
-        func.get_operation(),
-        "source_crate::debug_kernel",
-    );
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 7, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let ret = ReturnOp::new(&mut ctx, None);
-    let ret_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 8, 5);
-    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
-    ret.get_operation().insert_at_back(entry, &ctx);
-
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::LineTables,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    let define_line = ir
-        .lines()
-        .find(|line| line.starts_with("define "))
-        .expect("function definition");
-    assert!(
-        define_line.contains("!dbg !"),
-        "function definition should reference its DISubprogram:\n{ir}"
-    );
-
-    let ret_line = ir
-        .lines()
-        .find(|line| line.trim_start().starts_with("ret void"))
-        .expect("return instruction");
-    assert!(
-        ret_line.contains(", !dbg !"),
-        "real instructions should carry DILocation attachments:\n{ir}"
-    );
-
-    assert!(
-        ir.contains("!llvm.dbg.cu = !{!"),
-        "module should reference a compile unit:\n{ir}"
-    );
-    assert!(
-        ir.contains("!llvm.module.flags = !{!"),
-        "module should declare debug-info flags:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DIFile(filename: \"kernel.rs\", directory: \"/tmp/cuda-oxide/tests\")"),
-        "source path should be split into DIFile filename and directory:\n{ir}"
-    );
-    assert!(
-        ir.contains("distinct !DICompileUnit(language: DW_LANG_Rust"),
-        "debug export should describe the Rust compile unit:\n{ir}"
-    );
-    assert!(
-        ir.contains(
-            "distinct !DISubprogram(name: \"source_crate::debug_kernel\", linkageName: \"debug_kernel\""
-        ),
-        "function definition should separate its source name from its physical linkage name:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocation(line: 8, column: 5, scope: !"),
-        "instruction location should preserve the source line and column:\n{ir}"
-    );
-}
-
-#[test]
-fn full_debug_metadata_keeps_generic_source_name_separate_from_mangled_symbol() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let linkage_name = "_RNvMCexampleINtCsource7WrapperjE7get_mut";
-    let func = FuncOp::new(&mut ctx, linkage_name.try_into().unwrap(), func_ty);
-    llvm_export::ops::set_debug_function_name(
-        &mut ctx,
-        func.get_operation(),
-        "source_crate::Wrapper::<u16>::get_mut",
-    );
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/generic.rs", 19, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::Full,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    assert!(
-        ir.contains(&format!("define void @{linkage_name}()")),
-        "debug naming must not change the physical function symbol:\n{ir}"
-    );
-    assert!(
-        ir.contains(&format!(
-            "distinct !DISubprogram(name: \"source_crate::Wrapper::<u16>::get_mut\", linkageName: \"{linkage_name}\""
-        )),
-        "generic debug metadata must carry both source and linkage spellings:\n{ir}"
-    );
-}
-
-#[test]
-fn export_alwaysinline_function_attribute_uses_llvm_define_syntax() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "inline_helper".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-
-    let key: pliron::identifier::Identifier = "alwaysinline".try_into().unwrap();
-    func.get_operation()
-        .deref_mut(&ctx)
-        .attributes
-        .set(key, StringAttr::new("true".to_string()));
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
-    let define_line = ir
-        .lines()
-        .find(|line| line.starts_with("define void @inline_helper("))
-        .expect("inline helper definition");
-    assert_eq!(
-        define_line, "define void @inline_helper() alwaysinline #0 {",
-        "`alwaysinline` must be emitted after the parameter list, before attr group #0:\n{ir}"
-    );
-    assert!(
-        ir.contains("attributes #0 = { convergent }"),
-        "convergent attribute group must still be emitted:\n{ir}"
-    );
-}
-
-#[test]
-fn export_alwaysinline_coexists_with_debug_scope() {
-    // alwaysinline and the !dbg scope are emitted on the same define line and
-    // must not crowd each other out. This guards the 4-way emission: a future
-    // change that drops either one when both are present fails here.
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "inline_helper".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 7, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let ret = ReturnOp::new(&mut ctx, None);
-    let ret_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 8, 5);
-    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
-    ret.get_operation().insert_at_back(entry, &ctx);
-
-    let key: pliron::identifier::Identifier = "alwaysinline".try_into().unwrap();
-    func.get_operation()
-        .deref_mut(&ctx)
-        .attributes
-        .set(key, StringAttr::new("true".to_string()));
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::LineTables,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-    let define_line = ir
-        .lines()
-        .find(|line| line.starts_with("define void @inline_helper("))
-        .expect("inline helper definition");
-    assert!(
-        define_line.contains("alwaysinline"),
-        "alwaysinline must survive when debug info is on:\n{ir}"
-    );
-    assert!(
-        define_line.contains("!dbg !"),
-        "!dbg scope must survive when alwaysinline is present:\n{ir}"
-    );
-}
-
-#[test]
-fn line_table_debug_metadata_uses_file_scope_for_cross_file_locations() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 38, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let ret = ReturnOp::new(&mut ctx, None);
-    let ret_loc = src_location(
-        &mut ctx,
-        "/tmp/cuda-oxide/crates/cuda-device/src/thread.rs",
-        292,
-        19,
-    );
-    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
-    ret.get_operation().insert_at_back(entry, &ctx);
-
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::LineTables,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    let ret_line = ir
-        .lines()
-        .find(|line| line.trim_start().starts_with("ret void"))
-        .expect("return instruction");
-    assert!(
-        ret_line.contains(", !dbg !"),
-        "cross-file instructions should keep source locations:\n{ir}"
-    );
-    assert!(
-        ir.contains(
-            "!DIFile(filename: \"thread.rs\", directory: \"/tmp/cuda-oxide/crates/cuda-device/src\")"
-        ),
-        "cross-file locations should get their own DIFile:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILexicalBlockFile(scope: !"),
-        "cross-file locations should use a file-specific debug scope:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocation(line: 292, column: 19, scope: !"),
-        "cross-file locations should preserve their real source line:\n{ir}"
-    );
-}
-
-#[test]
-fn line_table_debug_metadata_emits_inlined_at_for_callsite_locations() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 38, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let ret = ReturnOp::new(&mut ctx, None);
-    let callee = src_location(
-        &mut ctx,
-        "/tmp/cuda-oxide/crates/cuda-device/src/thread.rs",
-        292,
-        19,
-    );
-    let caller = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 39, 13);
-    ret.get_operation()
-        .deref_mut(&ctx)
-        .set_loc(Location::CallSite {
-            callee: Box::new(callee),
-            caller: Box::new(caller),
-        });
-    ret.get_operation().insert_at_back(entry, &ctx);
-
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::LineTables,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    assert!(
-        ir.contains("!DILocation(line: 39, column: 13, scope: !"),
-        "callsite metadata should preserve the caller location:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocation(line: 292, column: 19, scope: !") && ir.contains(", inlinedAt: !"),
-        "callsite metadata should describe the callee location as inlined at the caller:\n{ir}"
-    );
-}
-
-#[test]
-fn debug_metadata_shares_allocator_with_nvvm_metadata() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 10, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-
-    {
-        let attrs = &mut func.get_operation().deref_mut(&ctx).attributes;
-        attrs.set(
-            Identifier::try_from("gpu_kernel").unwrap(),
-            StringAttr::new("true".into()),
-        );
-    }
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let ret = ReturnOp::new(&mut ctx, None);
-    let ret_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 11, 5);
-    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
-    ret.get_operation().insert_at_back(entry, &ctx);
-
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: NvvmExportConfig::default(),
-        debug_kind: DebugKind::LineTables,
-    };
-    let ir = export_module_to_string_with_config(&ctx, &module, &config)
-        .expect("debug NVVM export succeeds");
-
-    assert!(
-        ir.contains("!0 = !DIFile(filename: \"kernel.rs\", directory: \"/tmp/cuda-oxide/tests\")"),
-        "debug file node should take the first metadata ID:\n{ir}"
-    );
-    assert!(
-        ir.contains("!4 = !DILocation(line: 11, column: 5, scope: !3)"),
-        "instruction location should be allocated before NVVM metadata:\n{ir}"
-    );
-    assert!(
-        ir.contains("!5 = !{ptr @debug_kernel, !\"kernel\", i32 1}"),
-        "NVVM annotations should continue after debug metadata:\n{ir}"
-    );
-    assert!(
-        ir.contains("!nvvm.annotations = !{!5}"),
-        "named NVVM metadata should reference its allocated node:\n{ir}"
-    );
-    assert!(
-        ir.contains("!nvvmir.version = !{!6}\n!6 = !{i32 2, i32 0, i32 3, i32 2}"),
-        "NVVM version should use the next free metadata ID:\n{ir}"
-    );
-    assert!(
-        ir.contains("!llvm.module.flags = !{!7, !8}"),
-        "debug module flags should also use the shared allocator:\n{ir}"
-    );
-}
-
-#[test]
-fn debug_locations_use_rustc_source_scope_positions() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 10, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-    llvm_export::ops::set_debug_source_scope_map(
-        &mut ctx,
-        func.get_operation(),
-        &DebugSourceScopeMap {
-            scopes: vec![
-                DebugSourceScope {
-                    id: 0,
-                    parent: None,
-                    span: Some(DebugSourcePosition {
-                        file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
-                        line: 10,
-                        column: 1,
-                    }),
-                    inlined: None,
-                },
-                DebugSourceScope {
-                    id: 1,
-                    parent: Some(0),
-                    span: Some(DebugSourcePosition {
-                        file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
-                        line: 12,
-                        column: 9,
-                    }),
-                    inlined: None,
-                },
-            ],
-            locations: vec![DebugSourceScopeLocation {
-                pos: DebugSourcePosition {
-                    file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
-                    line: 12,
-                    column: 9,
-                },
-                scope: 1,
-            }],
-        },
-    );
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let ret = ReturnOp::new(&mut ctx, None);
-    let ret_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 12, 9);
-    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
-    ret.get_operation().insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::LineTables,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    let block_id = ir
-        .lines()
-        .find_map(|line| {
-            if line.contains("!DILexicalBlock(scope: !") && line.contains("line: 12, column: 9") {
-                line.split_once(" = ")
-                    .map(|(id, _)| id.trim_start_matches('!').to_string())
-            } else {
-                None
-            }
-        })
-        .expect("nested lexical block should be emitted");
-
-    assert!(
-        ir.contains(&format!(
-            "!DILocation(line: 12, column: 9, scope: !{block_id})"
-        )),
-        "instruction location should use the exact rustc source scope, not the function scope:\n{ir}"
-    );
-}
-
-#[test]
-fn full_debug_metadata_emits_dbg_declare_for_tagged_allocas() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 30, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
-    let one = ConstantOp::new(&mut ctx, one_attr.into());
-    one.get_operation().insert_at_back(entry, &ctx);
-    let one_val = one.get_operation().deref(&ctx).get_result(0);
-
-    let tid = AllocaOp::new(&mut ctx, i32_ty.into(), one_val);
-    let tid_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 31, 9);
-    tid.get_operation().deref_mut(&ctx).set_loc(tid_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        tid.get_operation(),
-        DebugLocalVariableInfo {
-            name: "tid".to_string(),
-            argument_index: Some(1),
-            ty: DebugLocalTypeKind::Basic {
-                name: "u32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_unsigned",
-            },
-        },
-    );
-    tid.get_operation().insert_at_back(entry, &ctx);
-
-    let ptr_ty = PointerType::get(&ctx, 0);
-    let ptr = AllocaOp::new(&mut ctx, ptr_ty.into(), one_val);
-    let ptr_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 32, 9);
-    ptr.get_operation().deref_mut(&ctx).set_loc(ptr_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        ptr.get_operation(),
-        DebugLocalVariableInfo {
-            name: "ptr".to_string(),
-            argument_index: None,
-            ty: DebugLocalTypeKind::TypedPointer {
-                name: "*mut f32".to_string(),
-                size_bits: 64,
-                pointee: Box::new(DebugLocalTypeKind::Basic {
-                    name: "f32".to_string(),
-                    size_bits: 32,
-                    encoding: "DW_ATE_float",
-                }),
-            },
-        },
-    );
-    ptr.get_operation().insert_at_back(entry, &ctx);
-
-    let nested_ptr = AllocaOp::new(&mut ctx, ptr_ty.into(), one_val);
-    let nested_ptr_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 33, 9);
-    nested_ptr
-        .get_operation()
-        .deref_mut(&ctx)
-        .set_loc(nested_ptr_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        nested_ptr.get_operation(),
-        DebugLocalVariableInfo {
-            name: "nested_ptr".to_string(),
-            argument_index: None,
-            ty: DebugLocalTypeKind::TypedPointer {
-                name: "*const *mut i32".to_string(),
-                size_bits: 64,
-                pointee: Box::new(DebugLocalTypeKind::TypedPointer {
-                    name: "*mut i32".to_string(),
-                    size_bits: 64,
-                    pointee: Box::new(DebugLocalTypeKind::Basic {
-                        name: "i32".to_string(),
-                        size_bits: 32,
-                        encoding: "DW_ATE_signed",
-                    }),
-                }),
-            },
-        },
-    );
-    nested_ptr.get_operation().insert_at_back(entry, &ctx);
-
-    let array_ptr = AllocaOp::new(&mut ctx, ptr_ty.into(), one_val);
-    let array_ptr_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 34, 9);
-    array_ptr
-        .get_operation()
-        .deref_mut(&ctx)
-        .set_loc(array_ptr_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        array_ptr.get_operation(),
-        DebugLocalVariableInfo {
-            name: "array_ptr".to_string(),
-            argument_index: None,
-            ty: DebugLocalTypeKind::TypedPointer {
-                name: "*const [u16; 4]".to_string(),
-                size_bits: 64,
-                pointee: Box::new(DebugLocalTypeKind::Array {
-                    name: "[u16; 4]".to_string(),
-                    size_bits: 64,
-                    element: Box::new(DebugLocalTypeKind::Basic {
-                        name: "u16".to_string(),
-                        size_bits: 16,
-                        encoding: "DW_ATE_unsigned",
-                    }),
-                    count: 4,
-                }),
-            },
-        },
-    );
-    array_ptr.get_operation().insert_at_back(entry, &ctx);
-
-    let opaque_ptr = AllocaOp::new(&mut ctx, ptr_ty.into(), one_val);
-    let opaque_ptr_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 35, 9);
-    opaque_ptr
-        .get_operation()
-        .deref_mut(&ctx)
-        .set_loc(opaque_ptr_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        opaque_ptr.get_operation(),
-        DebugLocalVariableInfo {
-            name: "opaque_ptr".to_string(),
-            argument_index: None,
-            ty: DebugLocalTypeKind::Pointer {
-                name: "*const _".to_string(),
-                size_bits: 64,
-            },
-        },
-    );
-    opaque_ptr.get_operation().insert_at_back(entry, &ctx);
-
-    let ret = ReturnOp::new(&mut ctx, None);
-    let ret_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 36, 1);
-    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
-    ret.get_operation().insert_at_back(entry, &ctx);
-
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::Full,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    assert!(
-        ir.contains("emissionKind: FullDebug"),
-        "full debug should request full DWARF metadata:\n{ir}"
-    );
-    assert!(
-        ir.contains("isOptimized: false"),
-        "full debug export should describe the unoptimized debug path:\n{ir}"
-    );
-    assert!(
-        ir.contains("declare void @llvm.dbg.declare(metadata, metadata, metadata)"),
-        "full debug should declare the debug intrinsic it calls:\n{ir}"
-    );
-    assert!(
-        ir.contains("call void @llvm.dbg.declare(metadata ptr %"),
-        "tagged allocas should be bound to variables with dbg.declare:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocalVariable(name: \"tid\", arg: 1, scope: !"),
-        "argument debug metadata should preserve the argument number:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocalVariable(name: \"ptr\", scope: !"),
-        "local debug metadata should omit the arg field:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DIBasicType(name: \"u32\", size: 32, encoding: DW_ATE_unsigned)"),
-        "basic integer variables should get DIBasicType metadata:\n{ir}"
-    );
-    let f32_id = metadata_id(
-        &ir,
-        "!DIBasicType(name: \"f32\", size: 32, encoding: DW_ATE_float)",
-    );
-    assert!(
-        ir.contains(&format!(
-            "!DIDerivedType(tag: DW_TAG_pointer_type, name: \"*mut f32\", baseType: {f32_id}, size: 64)"
-        )),
-        "pointer variables should reference their pointee DIType:\n{ir}"
-    );
-    let i32_id = metadata_id(
-        &ir,
-        "!DIBasicType(name: \"i32\", size: 32, encoding: DW_ATE_signed)",
-    );
-    let inner_pointer = format!(
-        "!DIDerivedType(tag: DW_TAG_pointer_type, name: \"*mut i32\", baseType: {i32_id}, size: 64)"
-    );
-    let inner_pointer_id = metadata_id(&ir, &inner_pointer);
-    assert!(
-        ir.contains(&format!(
-            "!DIDerivedType(tag: DW_TAG_pointer_type, name: \"*const *mut i32\", baseType: {inner_pointer_id}, size: 64)"
-        )),
-        "nested pointer metadata must preserve the complete base-type chain:\n{ir}"
-    );
-
-    let u16_id = metadata_id(
-        &ir,
-        "!DIBasicType(name: \"u16\", size: 16, encoding: DW_ATE_unsigned)",
-    );
-    let subrange_id = metadata_id(&ir, "!DISubrange(count: 4)");
-    let subrange_tuple_id = metadata_id(&ir, &format!("!{{{subrange_id}}}"));
-    let array_type = format!(
-        "!DICompositeType(tag: DW_TAG_array_type, baseType: {u16_id}, size: 64, elements: {subrange_tuple_id})"
-    );
-    let array_type_id = metadata_id(&ir, &array_type);
-    assert!(
-        ir.contains(&format!(
-            "!DIDerivedType(tag: DW_TAG_pointer_type, name: \"*const [u16; 4]\", baseType: {array_type_id}, size: 64)"
-        )),
-        "array pointer metadata must reference the exact element/subrange graph:\n{ir}"
-    );
-
-    assert!(
-        ir.contains("!DILocalVariable(name: \"opaque_ptr\", scope: !"),
-        "unsupported pointers must remain visible as source variables:\n{ir}"
-    );
-    assert!(
-        ir.contains(
-            "!DIDerivedType(tag: DW_TAG_pointer_type, name: \"*const _\", baseType: null, size: 64)"
-        ),
-        "the compatibility pointer must retain its legacy null-base metadata:\n{ir}"
-    );
-    let null_base_pointer_count = ir
-        .lines()
-        .filter(|line| line.contains("DW_TAG_pointer_type") && line.contains("baseType: null"))
-        .count();
-    assert!(
-        null_base_pointer_count == 1,
-        "only the explicit opaque compatibility pointer may have a null baseType:\n{ir}"
-    );
-
-    let Some(llvm_as) = ["llvm-as-22", "llvm-as-21", "llvm-as"]
-        .into_iter()
-        .find(|tool| {
-            std::process::Command::new(tool)
-                .arg("--version")
-                .output()
-                .is_ok_and(|out| out.status.success())
-        })
-    else {
-        eprintln!("skipping pointer-debug llvm-as parse gate: no supported llvm-as on PATH");
-        return;
-    };
-    let ll_path = std::env::temp_dir().join(format!(
-        "cuda_oxide_pointer_debug_parse_gate_{}.ll",
-        std::process::id()
-    ));
-    std::fs::write(&ll_path, &ir).expect("write pointer-debug temp .ll");
-    let output = std::process::Command::new(llvm_as)
-        .arg("-o")
-        .arg("/dev/null")
-        .arg(&ll_path)
-        .output()
-        .expect("run llvm-as for pointer debug metadata");
-    let stderr = String::from_utf8_lossy(&output.stderr).into_owned();
-    let _ = std::fs::remove_file(&ll_path);
-    assert!(
-        output.status.success(),
-        "{llvm_as} rejected pointer debug metadata:\n{stderr}\n--- module ---\n{ir}"
-    );
-}
-
-#[test]
-fn full_debug_metadata_describes_as1_global_with_semantic_rust_type() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let storage_ty = ArrayType::get(&ctx, i8_ty.into(), 8);
-    let global = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "__device_global_7".try_into().unwrap(),
-        storage_ty.into(),
-        8,
-    );
-    global.set_address_space(&mut ctx, llvm_export::types::address_space::GLOBAL);
-    global.set_initializer_hex(&mut ctx, "0000000000000000");
-    llvm_export::ops::set_debug_global_variable(
-        &mut ctx,
-        global.get_operation(),
-        &DebugGlobalVariableInfo {
-            name: "GLOBAL_COUNTER".to_string(),
-            namespace: vec!["debuginfo".to_string(), "state".to_string()],
-            ty: DebugLocalTypeKind::Basic {
-                name: "u64".to_string(),
-                size_bits: 64,
-                encoding: "DW_ATE_unsigned",
-            },
-            declaration: DebugSourcePosition {
-                file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
-                line: 90,
-                column: 1,
-            },
-            is_local_to_unit: true,
-            is_function_local: false,
-        },
-    );
-    global.get_operation().insert_at_back(module_block, &ctx);
-
-    let full = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &DebugConfig {
-            inner: PtxExportConfig,
-            debug_kind: DebugKind::Full,
-        },
-    )
-    .expect("full debug export succeeds");
-
-    let definition = full
-        .lines()
-        .find(|line| line.starts_with("@__device_global_7 = "))
-        .expect("device-global definition");
-    assert!(
-        definition.contains("addrspace(1) global [8 x i8] c\"\\00\\00\\00\\00\\00\\00\\00\\00\"")
-            && definition.contains(", align 8, !dbg !"),
-        "the physical byte storage should retain a global debug attachment:\n{full}"
-    );
-    assert!(
-        full.contains(
-            "distinct !DIGlobalVariable(name: \"GLOBAL_COUNTER\", linkageName: \"__device_global_7\""
-        ),
-        "DWARF should separate the source name from the generated linkage name:\n{full}"
-    );
-    assert!(
-        full.contains("!DINamespace(name: \"debuginfo\", scope: null)")
-            && full.contains("!DINamespace(name: \"state\", scope: !")
-            && full.contains("scope: !"),
-        "the source crate/module hierarchy should scope the leaf name:\n{full}"
-    );
-    assert!(
-        full.contains("isLocal: true, isDefinition: true"),
-        "private Rust statics should remain local to the compile unit:\n{full}"
-    );
-    assert!(
-        full.contains("file: !")
-            && full.contains("line: 90, type: !")
-            && full.contains("align: 64)"),
-        "the declaration location and source alignment should be retained:\n{full}"
-    );
-    assert!(
-        full.contains("!DIBasicType(name: \"u64\", size: 64, encoding: DW_ATE_unsigned)"),
-        "the debug type must be semantic u64, not the physical [8 x i8] storage:\n{full}"
-    );
-    assert!(
-        full.contains("!DIGlobalVariableExpression(var: !")
-            && full.contains("expr: !DIExpression())")
-            && full.contains("emissionKind: FullDebug, globals: !"),
-        "the global expression should be retained by the compile unit:\n{full}"
-    );
-
-    let off = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &DebugConfig {
-            inner: PtxExportConfig,
-            debug_kind: DebugKind::Off,
-        },
-    )
-    .expect("non-debug export succeeds");
-    let line_tables = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &DebugConfig {
-            inner: PtxExportConfig,
-            debug_kind: DebugKind::LineTables,
-        },
-    )
-    .expect("line-table export succeeds");
-    assert_eq!(
-        line_tables, off,
-        "a global-only module must not gain variable metadata outside full debug"
-    );
-}
-
-#[test]
-fn full_debug_metadata_describes_function_local_as3_array_with_shared_address_class() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "shared_debug".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let raw_owner = reserved_oxide_symbols::device_symbol("shared_kernel");
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let storage_ty = ArrayType::get(&ctx, i32_ty.into(), 32);
-    let global = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "__shared_mem_0".try_into().unwrap(),
-        storage_ty.into(),
-        4,
-    );
-    global.set_address_space(&mut ctx, llvm_export::types::address_space::SHARED);
-    let info = DebugGlobalVariableInfo {
-        name: "TILE".to_string(),
-        namespace: vec![
-            "debuginfo".to_string(),
-            "kernels".to_string(),
-            "shared_kernel".to_string(),
-        ],
-        ty: DebugLocalTypeKind::Array {
-            name: "[i32; 32]".to_string(),
-            size_bits: 1024,
-            element: Box::new(DebugLocalTypeKind::Basic {
-                name: "i32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_signed",
-            }),
-            count: 32,
-        },
-        declaration: DebugSourcePosition {
-            file: PathBuf::from("/tmp/cuda-oxide/tests/shared.rs"),
-            line: 40,
-            column: 9,
-        },
-        is_local_to_unit: true,
-        is_function_local: true,
-    };
-    llvm_export::ops::set_debug_global_variable(&mut ctx, global.get_operation(), &info);
-    llvm_export::ops::set_debug_global_owner_function(&mut ctx, global.get_operation(), &raw_owner);
-    global.get_operation().insert_at_back(module_block, &ctx);
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let function = FuncOp::new(&mut ctx, raw_owner.as_str().try_into().unwrap(), func_ty);
-    let function_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/shared.rs", 35, 1);
-    function
-        .get_operation()
-        .deref_mut(&ctx)
-        .set_loc(function_loc);
-    let entry = function.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    function.get_operation().insert_at_back(module_block, &ctx);
-
-    let full = export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &DebugConfig {
-            inner: PtxExportConfig,
-            debug_kind: DebugKind::Full,
-        },
-    )
-    .expect("full shared debug export succeeds");
-
-    let definition = full
-        .lines()
-        .find(|line| line.starts_with("@__shared_mem_0 = "))
-        .expect("shared definition");
-    assert!(
-        definition.contains("addrspace(3) global [32 x i32]")
-            && definition.contains(", align 4, !dbg !"),
-        "physical AS3 array must retain the debug attachment:\n{full}"
-    );
-    assert!(
-        full.contains("!DIExpression(DW_OP_constu, 8, DW_OP_swap, DW_OP_xderef)"),
-        "AS3 must carry CUDA DWARF shared address class 8:\n{full}"
-    );
-    assert!(
-        full.contains("!DINamespace(name: \"debuginfo\", scope: null)")
-            && full.contains("!DINamespace(name: \"kernels\", scope: !")
-            && full.contains(
-                "distinct !DISubprogram(name: \"shared_kernel\", \
-                 linkageName: \"shared_kernel\", scope: !"
-            ),
-        "the owning subprogram must be nested under the structured namespace:\n{full}"
-    );
-    assert_eq!(
-        full.matches("distinct !DISubprogram(name: \"shared_kernel\"")
-            .count(),
-        1,
-        "pre-reservation and function export must reuse one DISubprogram:\n{full}"
-    );
-    assert!(
-        full.contains("distinct !DIGlobalVariable(name: \"TILE\", linkageName: \"__shared_mem_0\"")
-            && full.contains("!DISubrange(count: 32)")
-            && full.contains("!DICompositeType(tag: DW_TAG_array_type, baseType: !")
-            && full.contains("size: 1024, elements: !"),
-        "the DIE must keep leaf/linkage and the logical array type:\n{full}"
-    );
-    assert!(
-        full.contains("emissionKind: FullDebug, globals: !"),
-        "the CU must retain the one shared expression:\n{full}"
-    );
-}
-
-fn export_mixed_shared_owner_order(malformed_first: bool) -> String {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "shared_owner_validation".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let raw_owner = reserved_oxide_symbols::device_symbol("shared_kernel");
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let storage_ty = ArrayType::get(&ctx, i32_ty.into(), 4);
-
-    let valid = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "__shared_mem_valid".try_into().unwrap(),
-        storage_ty.into(),
-        4,
-    );
-    valid.set_address_space(&mut ctx, llvm_export::types::address_space::SHARED);
-    llvm_export::ops::set_debug_global_variable(
-        &mut ctx,
-        valid.get_operation(),
-        &DebugGlobalVariableInfo {
-            name: "VALID".to_string(),
-            namespace: vec!["owner_fixture".to_string(), "shared_kernel".to_string()],
-            ty: DebugLocalTypeKind::Array {
-                name: "[i32; 4]".to_string(),
-                size_bits: 128,
-                element: Box::new(DebugLocalTypeKind::Basic {
-                    name: "i32".to_string(),
-                    size_bits: 32,
-                    encoding: "DW_ATE_signed",
-                }),
-                count: 4,
-            },
-            declaration: DebugSourcePosition {
-                file: PathBuf::from("/tmp/cuda-oxide/tests/shared-owner.rs"),
-                line: 20,
-                column: 5,
-            },
-            is_local_to_unit: true,
-            is_function_local: true,
-        },
-    );
-    llvm_export::ops::set_debug_global_owner_function(&mut ctx, valid.get_operation(), &raw_owner);
-
-    let malformed = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "__shared_mem_malformed".try_into().unwrap(),
-        storage_ty.into(),
-        4,
-    );
-    malformed.set_address_space(&mut ctx, llvm_export::types::address_space::SHARED);
-    llvm_export::ops::set_debug_global_variable(
-        &mut ctx,
-        malformed.get_operation(),
-        &DebugGlobalVariableInfo {
-            name: "MALFORMED".to_string(),
-            namespace: vec!["owner_fixture".to_string(), "shared_kernel".to_string()],
-            ty: DebugLocalTypeKind::Array {
-                name: "[i32; 4]".to_string(),
-                size_bits: 128,
-                element: Box::new(DebugLocalTypeKind::Basic {
-                    name: "i32".to_string(),
-                    size_bits: 32,
-                    encoding: "DW_ATE_signed",
-                }),
-                count: 4,
-            },
-            declaration: DebugSourcePosition {
-                file: PathBuf::from("/tmp/cuda-oxide/tests/shared-owner.rs"),
-                line: 24,
-                column: 5,
-            },
-            is_local_to_unit: true,
-            is_function_local: true,
-        },
-    );
-    // This raw spelling normalizes to `shared_kernel`, but it is not the raw
-    // symbol indexed for that function definition. It must not borrow the
-    // valid sibling's pre-reserved DISubprogram.
-    llvm_export::ops::set_debug_global_owner_function(
-        &mut ctx,
-        malformed.get_operation(),
-        "shared_kernel",
-    );
-
-    if malformed_first {
-        malformed.get_operation().insert_at_back(module_block, &ctx);
-        valid.get_operation().insert_at_back(module_block, &ctx);
-    } else {
-        valid.get_operation().insert_at_back(module_block, &ctx);
-        malformed.get_operation().insert_at_back(module_block, &ctx);
-    }
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let function = FuncOp::new(&mut ctx, raw_owner.as_str().try_into().unwrap(), func_ty);
-    let function_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/shared-owner.rs", 16, 1);
-    function
-        .get_operation()
-        .deref_mut(&ctx)
-        .set_loc(function_loc);
-    let entry = function.get_or_create_entry_block(&mut ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    function.get_operation().insert_at_back(module_block, &ctx);
-
-    export_module_to_string_with_config(
-        &ctx,
-        &module,
-        &DebugConfig {
-            inner: PtxExportConfig,
-            debug_kind: DebugKind::Full,
-        },
-    )
-    .expect("a malformed shared owner must not break its valid sibling")
-}
-
-fn assert_malformed_shared_owner_fails_closed(full: &str) {
-    let valid_definition = full
-        .lines()
-        .find(|line| line.starts_with("@__shared_mem_valid = "))
-        .expect("valid shared definition");
-    let malformed_definition = full
-        .lines()
-        .find(|line| line.starts_with("@__shared_mem_malformed = "))
-        .expect("malformed-owner shared definition");
-    assert!(
-        valid_definition.contains(", !dbg !"),
-        "the valid sibling must retain its debug attachment:\n{full}"
-    );
-    assert!(
-        !malformed_definition.contains(", !dbg !"),
-        "the malformed owner must not borrow the valid sibling's scope:\n{full}"
-    );
-    assert!(
-        full.contains("distinct !DIGlobalVariable(name: \"VALID\"")
-            && !full.contains("distinct !DIGlobalVariable(name: \"MALFORMED\""),
-        "only the valid shared source identity may become a DIE:\n{full}"
-    );
-    assert_eq!(
-        full.matches("!DIGlobalVariableExpression(var:").count(),
-        1,
-        "only the valid sibling may be retained by the compile unit:\n{full}"
-    );
-    assert_eq!(
-        full.matches("distinct !DISubprogram(name: \"shared_kernel\"")
-            .count(),
-        1,
-        "the valid owner must still reuse exactly one DISubprogram:\n{full}"
-    );
-}
-
-#[test]
-fn malformed_shared_owner_before_valid_sibling_cannot_borrow_its_scope() {
-    assert_malformed_shared_owner_fails_closed(&export_mixed_shared_owner_order(true));
-}
-
-#[test]
-fn malformed_shared_owner_after_valid_sibling_cannot_borrow_its_scope() {
-    assert_malformed_shared_owner_fails_closed(&export_mixed_shared_owner_order(false));
-}
-
-#[test]
-fn full_debug_globals_preserve_qualified_identity_visibility_and_relocations() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "global_debug_adversarial".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-
-    let left_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
-    let left = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "__device_global_20".try_into().unwrap(),
-        left_ty.into(),
-        4,
-    );
-    left.set_address_space(&mut ctx, llvm_export::types::address_space::GLOBAL);
-    left.set_initializer_hex(&mut ctx, "01000000");
-    llvm_export::ops::set_debug_global_variable(
-        &mut ctx,
-        left.get_operation(),
-        &DebugGlobalVariableInfo {
-            name: "SAME_LEAF".to_string(),
-            namespace: vec!["qualified_fixture".to_string(), "left".to_string()],
-            ty: DebugLocalTypeKind::Basic {
-                name: "u32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_unsigned",
-            },
-            declaration: DebugSourcePosition {
-                file: PathBuf::from("/tmp/cuda-oxide/tests/qualified.rs"),
-                line: 20,
-                column: 5,
-            },
-            is_local_to_unit: true,
-            is_function_local: false,
-        },
-    );
-    left.get_operation().insert_at_back(module_block, &ctx);
-
-    let right_ty = ArrayType::get(&ctx, i8_ty.into(), 8);
-    let right = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "__device_global_21".try_into().unwrap(),
-        right_ty.into(),
-        8,
-    );
-    right.set_address_space(&mut ctx, llvm_export::types::address_space::GLOBAL);
-    right.set_initializer_hex(&mut ctx, "0200000000000000");
-    llvm_export::ops::set_debug_global_variable(
-        &mut ctx,
-        right.get_operation(),
-        &DebugGlobalVariableInfo {
-            name: "SAME_LEAF".to_string(),
-            namespace: vec!["qualified_fixture".to_string(), "right".to_string()],
-            ty: DebugLocalTypeKind::Basic {
-                name: "u64".to_string(),
-                size_bits: 64,
-                encoding: "DW_ATE_unsigned",
-            },
-            declaration: DebugSourcePosition {
-                file: PathBuf::from("/tmp/cuda-oxide/tests/qualified.rs"),
-                line: 24,
-                column: 5,
-            },
-            is_local_to_unit: false,
-            is_function_local: false,
-        },
-    );
-    right.get_operation().insert_at_back(module_block, &ctx);
-
-    let target_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
-    let target = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "__device_global_22".try_into().unwrap(),
-        target_ty.into(),
-        4,
-    );
-    target.set_address_space(&mut ctx, llvm_export::types::address_space::GLOBAL);
-    target.set_source_global_key(&mut ctx, "qualified_fixture::RELOCATION_TARGET");
-    target.set_initializer_hex(&mut ctx, "78563412");
-    llvm_export::ops::set_debug_global_variable(
-        &mut ctx,
-        target.get_operation(),
-        &DebugGlobalVariableInfo {
-            name: "RELOCATION_TARGET".to_string(),
-            namespace: vec!["qualified_fixture".to_string()],
-            ty: DebugLocalTypeKind::Basic {
-                name: "u32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_unsigned",
-            },
-            declaration: DebugSourcePosition {
-                file: PathBuf::from("/tmp/cuda-oxide/tests/qualified.rs"),
-                line: 30,
-                column: 1,
-            },
-            is_local_to_unit: true,
-            is_function_local: false,
-        },
-    );
-    target.get_operation().insert_at_back(module_block, &ctx);
-
-    let references_ty = StructType::get_unnamed(
-        &ctx,
-        (vec![i64_ty.into(), i64_ty.into()], StructLayout::Unpacked),
-    );
-    let references = GlobalOp::new_with_alignment(
-        &mut ctx,
-        "__device_global_23".try_into().unwrap(),
-        references_ty.into(),
-        8,
-    );
-    references.set_address_space(&mut ctx, llvm_export::types::address_space::GLOBAL);
-    references.set_source_global_key(&mut ctx, "qualified_fixture::REFERENCES");
-    references.set_initializer_hex(&mut ctx, "00000000000000000000000000000000");
-    references.set_initializer_relocations(
-        &mut ctx,
-        &encode_global_initializer_relocations(&[
-            GlobalInitializerRelocation {
-                source_offset: 0,
-                width_bytes: 8,
-                target_address_space: llvm_export::types::address_space::GLOBAL,
-                target_addend: 0,
-                target_key: "qualified_fixture::RELOCATION_TARGET".to_string(),
-            },
-            GlobalInitializerRelocation {
-                source_offset: 8,
-                width_bytes: 8,
-                target_address_space: llvm_export::types::address_space::GLOBAL,
-                target_addend: 0,
-                target_key: "qualified_fixture::RELOCATION_TARGET".to_string(),
-            },
-        ]),
-    );
-    llvm_export::ops::set_debug_global_variable(
-        &mut ctx,
-        references.get_operation(),
-        &DebugGlobalVariableInfo {
-            name: "REFERENCES".to_string(),
-            namespace: vec!["qualified_fixture".to_string()],
-            ty: DebugLocalTypeKind::Array {
-                name: "[&u32; 2]".to_string(),
-                size_bits: 128,
-                element: Box::new(DebugLocalTypeKind::Pointer {
-                    name: "&u32".to_string(),
-                    size_bits: 64,
-                }),
-                count: 2,
-            },
-            declaration: DebugSourcePosition {
-                file: PathBuf::from("/tmp/cuda-oxide/tests/qualified.rs"),
-                line: 31,
-                column: 1,
-            },
-            is_local_to_unit: true,
-            is_function_local: false,
-        },
-    );
-    references
-        .get_operation()
-        .insert_at_back(module_block, &ctx);
-
-    let export = |debug_kind| {
-        export_module_to_string_with_config(
-            &ctx,
-            &module,
-            &DebugConfig {
-                inner: PtxExportConfig,
-                debug_kind,
-            },
-        )
-        .expect("global debug export succeeds")
-    };
-    let full = export(DebugKind::Full);
-
-    let metadata_id = |needle: &str| {
-        full.lines()
-            .find(|line| line.contains(needle))
-            .unwrap_or_else(|| panic!("missing `{needle}` in:\n{full}"))
-            .split_once(" = ")
-            .expect("metadata definition")
-            .0
-            .trim_start_matches('!')
-            .to_string()
-    };
-    let left_scope = metadata_id("!DINamespace(name: \"left\"");
-    let right_scope = metadata_id("!DINamespace(name: \"right\"");
-    let left_variable = full
-        .lines()
-        .find(|line| {
-            line.contains("!DIGlobalVariable(name: \"SAME_LEAF\"")
-                && line.contains("linkageName: \"__device_global_20\"")
-        })
-        .expect("left source global");
-    let right_variable = full
-        .lines()
-        .find(|line| {
-            line.contains("!DIGlobalVariable(name: \"SAME_LEAF\"")
-                && line.contains("linkageName: \"__device_global_21\"")
-        })
-        .expect("right source global");
-    assert!(left_variable.contains(&format!("scope: !{left_scope}")));
-    assert!(left_variable.contains("line: 20") && left_variable.contains("isLocal: true"));
-    assert!(right_variable.contains(&format!("scope: !{right_scope}")));
-    assert!(right_variable.contains("line: 24") && right_variable.contains("isLocal: false"));
-
-    let target_definition = full
-        .lines()
-        .find(|line| line.starts_with("@__device_global_22 = "))
-        .expect("relocation-only target definition");
-    assert!(target_definition.contains("[4 x i8]") && target_definition.contains("!dbg !"));
-    let target_variable = full
-        .lines()
-        .find(|line| line.contains("!DIGlobalVariable(name: \"RELOCATION_TARGET\""))
-        .expect("relocation-only target source identity");
-    assert!(
-        target_variable.contains("linkageName: \"__device_global_22\"")
-            && target_variable.contains("line: 30")
-    );
-
-    let reference_definition = full
-        .lines()
-        .find(|line| line.starts_with("@__device_global_23 = "))
-        .expect("relocation-backed definition");
-    assert_eq!(
-        reference_definition.matches("@__device_global_22").count(),
-        2,
-        "both initializer references must target the same one physical global"
-    );
-    assert!(
-        full.contains("!DICompositeType(tag: DW_TAG_array_type, baseType: !")
-            && full.contains("size: 128, elements: !")
-            && full.contains("!DIDerivedType(tag: DW_TAG_pointer_type, name: \"&u32\"")
-    );
-
-    assert_eq!(
-        full.matches("!DIGlobalVariableExpression(var:").count(),
-        4,
-        "one expression per physical source global, despite repeated relocations"
-    );
-    let compile_unit = full
-        .lines()
-        .find(|line| line.contains("!DICompileUnit("))
-        .expect("debug compile unit");
-    let globals_id = compile_unit
-        .split("globals: !")
-        .nth(1)
-        .and_then(|tail| tail.strip_suffix(')'))
-        .expect("compile-unit globals tuple");
-    let globals_tuple = full
-        .lines()
-        .find(|line| line.starts_with(&format!("!{globals_id} = !{{")))
-        .expect("compile-unit globals tuple definition");
-    assert_eq!(globals_tuple.matches('!').count() - 2, 4, "{globals_tuple}");
-
-    assert_eq!(
-        export(DebugKind::LineTables),
-        export(DebugKind::Off),
-        "initialized and relocation-backed globals must not gain metadata outside Full debug"
-    );
-
-    let Some(llvm_as) = ["llvm-as-22", "llvm-as-21", "llvm-as"]
-        .into_iter()
-        .find(|tool| {
-            std::process::Command::new(tool)
-                .arg("--version")
-                .output()
-                .is_ok_and(|out| out.status.success())
-        })
-    else {
-        eprintln!("skipping global-debug parse gate: no llvm-as on PATH");
-        return;
-    };
-    let ll_path = std::env::temp_dir().join(format!(
-        "cuda_oxide_global_debug_parse_gate_{}.ll",
-        std::process::id()
-    ));
-    std::fs::write(&ll_path, &full).expect("write temp .ll");
-    let output = std::process::Command::new(llvm_as)
-        .arg("-o")
-        .arg("/dev/null")
-        .arg(&ll_path)
-        .output()
-        .expect("run llvm-as");
-    let stderr = String::from_utf8_lossy(&output.stderr).into_owned();
-    let _ = std::fs::remove_file(&ll_path);
-    assert!(
-        output.status.success(),
-        "{llvm_as} rejected global debug metadata:\n{stderr}\n--- module ---\n{full}"
-    );
-}
-
-#[test]
-fn full_debug_metadata_emits_rust_enum_variant_parts() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "enum_debug".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "enum_debug_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/enum.rs", 10, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
-    let one = ConstantOp::new(&mut ctx, one_attr.into());
-    one.get_operation().insert_at_back(entry, &ctx);
-    let one_val = one.get_operation().deref(&ctx).get_result(0);
-
-    let direct = AllocaOp::new(&mut ctx, i64_ty.into(), one_val);
-    let direct_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/enum.rs", 11, 9);
-    direct.get_operation().deref_mut(&ctx).set_loc(direct_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        direct.get_operation(),
-        DebugLocalVariableInfo {
-            name: "direct".to_string(),
-            argument_index: None,
-            ty: DebugLocalTypeKind::Enum {
-                name: "Direct".to_string(),
-                size_bits: 64,
-                discriminant: Some(DebugEnumDiscriminant {
-                    offset_bits: 0,
-                    ty: Box::new(DebugLocalTypeKind::Basic {
-                        name: "u8".to_string(),
-                        size_bits: 8,
-                        encoding: "DW_ATE_unsigned",
-                    }),
-                }),
-                variants: vec![
-                    DebugEnumVariant {
-                        name: "Small".to_string(),
-                        discriminant: Some(3),
-                        members: vec![llvm_export::ops::DebugTypeMember {
-                            name: "0".to_string(),
-                            offset_bits: 32,
-                            ty: DebugLocalTypeKind::Basic {
-                                name: "u32".to_string(),
-                                size_bits: 32,
-                                encoding: "DW_ATE_unsigned",
-                            },
-                        }],
-                    },
-                    DebugEnumVariant {
-                        name: "Empty".to_string(),
-                        discriminant: Some(9),
-                        members: vec![],
-                    },
-                ],
-            },
-        },
-    );
-    direct.get_operation().insert_at_back(entry, &ctx);
-
-    let niche = AllocaOp::new(&mut ctx, i64_ty.into(), one_val);
-    let niche_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/enum.rs", 12, 9);
-    niche.get_operation().deref_mut(&ctx).set_loc(niche_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        niche.get_operation(),
-        DebugLocalVariableInfo {
-            name: "niche".to_string(),
-            argument_index: None,
-            ty: DebugLocalTypeKind::Enum {
-                name: "OptionRef".to_string(),
-                size_bits: 64,
-                discriminant: Some(DebugEnumDiscriminant {
-                    offset_bits: 0,
-                    ty: Box::new(DebugLocalTypeKind::Basic {
-                        name: "usize".to_string(),
-                        size_bits: 64,
-                        encoding: "DW_ATE_unsigned",
-                    }),
-                }),
-                variants: vec![
-                    DebugEnumVariant {
-                        name: "None".to_string(),
-                        discriminant: Some(0),
-                        members: vec![],
-                    },
-                    DebugEnumVariant {
-                        name: "Some".to_string(),
-                        discriminant: None,
-                        members: vec![llvm_export::ops::DebugTypeMember {
-                            name: "0".to_string(),
-                            offset_bits: 0,
-                            ty: DebugLocalTypeKind::TypedPointer {
-                                name: "&u32".to_string(),
-                                size_bits: 64,
-                                pointee: Box::new(DebugLocalTypeKind::Basic {
-                                    name: "u32".to_string(),
-                                    size_bits: 32,
-                                    encoding: "DW_ATE_unsigned",
-                                }),
-                            },
-                        }],
-                    },
-                ],
-            },
-        },
-    );
-    niche.get_operation().insert_at_back(entry, &ctx);
-
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::Full,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("enum debug export");
-
-    assert!(
-        ir.contains("!DICompositeType(tag: DW_TAG_variant_part"),
-        "Rust enums must contain a DW_TAG_variant_part:\n{ir}"
-    );
-    assert!(
-        ir.contains("flags: DIFlagArtificial"),
-        "the physical enum carrier must be marked artificial:\n{ir}"
-    );
-    let discriminator_member = ir
-        .lines()
-        .find(|line| {
-            line.contains("!DIDerivedType(tag: DW_TAG_member")
-                && line.contains("flags: DIFlagArtificial")
-        })
-        .expect("enum discriminator member");
-    assert!(
-        discriminator_member.contains("scope: !"),
-        "the physical enum carrier must be scoped to its enum object:\n{discriminator_member}\n{ir}"
-    );
-    let variant_part = ir
-        .lines()
-        .find(|line| line.contains("!DICompositeType(tag: DW_TAG_variant_part"))
-        .expect("enum variant part");
-    assert!(
-        variant_part.contains("scope: !"),
-        "the variant part must be scoped to its enum object:\n{variant_part}\n{ir}"
-    );
-    let direct_variant_member = ir
-        .lines()
-        .find(|line| {
-            line.contains("!DIDerivedType(tag: DW_TAG_member, name: \"Small\"")
-                && line.contains("extraData: i8 3")
-        })
-        .expect("direct enum variant member");
-    assert!(
-        direct_variant_member.contains("scope: !"),
-        "variant members must be scoped to their DW_TAG_variant_part:\n{direct_variant_member}\n{ir}"
-    );
-    assert!(
-        ir.contains("extraData: i8 3") && ir.contains("extraData: i8 9"),
-        "direct-tag variants must carry their physical discriminant values:\n{ir}"
-    );
-    assert!(
-        ir.contains("extraData: i64 0"),
-        "the tagged niche variant must carry the niche value:\n{ir}"
-    );
-
-    let some_variant_member = ir
-        .lines()
-        .find(|line| {
-            line.contains("!DIDerivedType(tag: DW_TAG_member, name: \"Some\"")
-                && line.contains("baseType:")
-        })
-        .expect("Some variant member");
-    assert!(
-        !some_variant_member.contains("extraData:"),
-        "the untagged niche variant must be the default branch:\n{some_variant_member}\n{ir}"
-    );
-}
-
-#[test]
-fn full_debug_metadata_uses_file_scope_for_cross_file_local_variables() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 30, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
-    let one = ConstantOp::new(&mut ctx, one_attr.into());
-    one.get_operation().insert_at_back(entry, &ctx);
-    let one_val = one.get_operation().deref(&ctx).get_result(0);
-
-    let tid = AllocaOp::new(&mut ctx, i32_ty.into(), one_val);
-    let tid_loc = src_location(
-        &mut ctx,
-        "/tmp/cuda-oxide/crates/cuda-device/src/thread.rs",
-        292,
-        19,
-    );
-    tid.get_operation().deref_mut(&ctx).set_loc(tid_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        tid.get_operation(),
-        DebugLocalVariableInfo {
-            name: "tid".to_string(),
-            argument_index: None,
-            ty: DebugLocalTypeKind::Basic {
-                name: "u32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_unsigned",
-            },
-        },
-    );
-    tid.get_operation().insert_at_back(entry, &ctx);
-
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::Full,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    assert!(
-        ir.contains("!DILexicalBlockFile(scope: !"),
-        "cross-file local variables should get a file-specific debug scope:\n{ir}"
-    );
-    assert!(
-        ir.contains(
-            "!DIFile(filename: \"thread.rs\", directory: \"/tmp/cuda-oxide/crates/cuda-device/src\")"
-        ),
-        "cross-file local variables should reference their source file:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocalVariable(name: \"tid\", scope: !") && ir.contains("line: 292"),
-        "cross-file local variables should preserve the variable file scope and line:\n{ir}"
-    );
-    assert!(
-        ir.contains("call void @llvm.dbg.declare"),
-        "cross-file local variables should still get dbg.declare bindings:\n{ir}"
-    );
-}
-
-#[test]
-fn full_debug_metadata_emits_dbg_value_for_promoted_locals() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![i32_ty.into()], false);
-    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 30, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let arg = entry.deref(&ctx).get_argument(0);
-    let dbg_value = DebugValueOp::new(&mut ctx, arg);
-    let dbg_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 31, 13);
-    dbg_value.get_operation().deref_mut(&ctx).set_loc(dbg_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        dbg_value.get_operation(),
-        DebugLocalVariableInfo {
-            name: "x".to_string(),
-            argument_index: Some(1),
-            ty: DebugLocalTypeKind::Basic {
-                name: "i32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_signed",
-            },
-        },
-    );
-    llvm_export::ops::set_debug_local_declaration_location(
-        &mut ctx,
-        dbg_value.get_operation(),
-        PathBuf::from("/tmp/cuda-oxide/tests/declarations.rs"),
-        12,
-        5,
-    );
-    llvm_export::ops::set_debug_fragment_variables(
-        &mut ctx,
-        dbg_value.get_operation(),
-        &[DebugFragmentVariableInfo {
-            variable: DebugLocalVariableInfo {
-                name: "pair".to_string(),
-                argument_index: None,
-                ty: DebugLocalTypeKind::Array {
-                    name: "[u32; 2]".to_string(),
-                    size_bits: 64,
-                    element: Box::new(DebugLocalTypeKind::Basic {
-                        name: "u32".to_string(),
-                        size_bits: 32,
-                        encoding: "DW_ATE_unsigned",
-                    }),
-                    count: 2,
-                },
-            },
-            fragment: DebugFragment {
-                offset_bits: 32,
-                size_bits: 32,
-            },
-            source_scope: None,
-            declaration: Some(DebugSourcePosition {
-                file: PathBuf::from("/tmp/cuda-oxide/tests/declarations.rs"),
-                line: 13,
-                column: 5,
-            }),
-        }],
-    );
-    dbg_value.get_operation().insert_at_back(entry, &ctx);
-
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::Full,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    assert!(
-        ir.contains("declare void @llvm.dbg.value(metadata, metadata, metadata)"),
-        "full debug should declare dbg.value when it emits one:\n{ir}"
-    );
-    assert!(
-        ir.contains("call void @llvm.dbg.value(metadata i32 %v0, metadata !"),
-        "dbg.value should describe the local as the current SSA value:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocalVariable(name: \"x\", arg: 1, scope: !"),
-        "dbg.value should preserve formal-argument metadata when the source local is an argument:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocalVariable(name: \"x\", arg: 1, scope: !")
-            && ir.contains("file: !")
-            && ir.contains("line: 12"),
-        "DILocalVariable should use the source declaration line, not the dbg.value line:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocation(line: 31, column: 13, scope: !"),
-        "dbg.value should still be located at the value's current source point:\n{ir}"
-    );
-    assert!(
-        ir.contains("DW_OP_LLVM_fragment, 32, 32"),
-        "dbg.value should preserve scalarized source-variable fragments:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocalVariable(name: \"pair\", scope: !") && ir.contains("line: 13"),
-        "fragment dbg.value should describe the complete source variable:\n{ir}"
-    );
-    assert!(
-        !ir.contains("llvm.dbg.declare"),
-        "a value-only debug record should not force dbg.declare:\n{ir}"
-    );
-}
-
-#[test]
-fn full_debug_metadata_emits_diarglist_for_multi_value_locations() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let ptr_ty = PointerType::get(&ctx, 0);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(
-        &ctx,
-        void_ty.to_handle(),
-        vec![ptr_ty.into(), i64_ty.into()],
-        false,
-    );
-    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 40, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let base = entry.deref(&ctx).get_argument(0);
-    let index = entry.deref(&ctx).get_argument(1);
-    let dbg_value = DebugValueListOp::new(&mut ctx, vec![base, index]);
-    let dbg_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 41, 17);
-    dbg_value.get_operation().deref_mut(&ctx).set_loc(dbg_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        dbg_value.get_operation(),
-        DebugLocalVariableInfo {
-            name: "item".to_string(),
-            argument_index: None,
-            ty: DebugLocalTypeKind::Basic {
-                name: "u32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_unsigned",
-            },
-        },
-    );
-    llvm_export::ops::set_debug_value_expression(
-        &mut ctx,
-        dbg_value.get_operation(),
-        &DebugValueExpression::new(vec![
-            DebugValueExpressionOp::Arg(0),
-            DebugValueExpressionOp::Arg(1),
-            DebugValueExpressionOp::ConstU(4),
-            DebugValueExpressionOp::Mul,
-            DebugValueExpressionOp::Plus,
-            DebugValueExpressionOp::Deref,
-        ]),
-    );
-    dbg_value.get_operation().insert_at_back(entry, &ctx);
-
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::Full,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    assert!(
-        ir.contains("call void @llvm.dbg.value(metadata !DIArgList(ptr %v0, i64 %v1), metadata !"),
-        "multi-value debug records should emit an inline DIArgList:\n{ir}"
-    );
-    assert!(
-        ir.contains(
-            "!DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_deref)"
-        ),
-        "multi-value debug records should emit the typed location recipe:\n{ir}"
-    );
-    assert!(
-        ir.contains("declare void @llvm.dbg.value(metadata, metadata, metadata)"),
-        "multi-value records should reuse the ordinary dbg.value intrinsic declaration:\n{ir}"
-    );
-
-    let Some(llvm_as) = ["llvm-as-22", "llvm-as-21", "llvm-as"]
-        .into_iter()
-        .find(|tool| {
-            std::process::Command::new(tool)
-                .arg("--version")
-                .output()
-                .is_ok_and(|out| out.status.success())
-        })
-    else {
-        eprintln!("skipping llvm-as parse gate: no llvm-as-22/llvm-as-21/llvm-as on PATH");
-        return;
-    };
-
-    let ll_path = std::env::temp_dir().join(format!(
-        "cuda_oxide_diarglist_parse_gate_{}.ll",
-        std::process::id()
-    ));
-    std::fs::write(&ll_path, &ir).expect("write temp .ll");
-    let output = std::process::Command::new(llvm_as)
-        .arg("-o")
-        .arg("/dev/null")
-        .arg(&ll_path)
-        .output()
-        .expect("run llvm-as");
-    let stderr = String::from_utf8_lossy(&output.stderr).into_owned();
-    let _ = std::fs::remove_file(&ll_path);
-    assert!(
-        output.status.success(),
-        "{llvm_as} rejected the emitted multi-value debug module:\n{stderr}\n--- module ---\n{ir}"
-    );
-}
-
-#[test]
-fn full_debug_metadata_uses_inlined_callee_scope_for_inlined_arguments() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![i32_ty.into()], false);
-    let func = FuncOp::new(&mut ctx, "caller_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 30, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-    llvm_export::ops::set_debug_source_scope_map(
-        &mut ctx,
-        func.get_operation(),
-        &DebugSourceScopeMap {
-            scopes: vec![
-                DebugSourceScope {
-                    id: 0,
-                    parent: None,
-                    span: Some(DebugSourcePosition {
-                        file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
-                        line: 30,
-                        column: 1,
-                    }),
-                    inlined: None,
-                },
-                DebugSourceScope {
-                    id: 1,
-                    parent: Some(0),
-                    span: Some(DebugSourcePosition {
-                        file: PathBuf::from("/tmp/cuda-oxide/tests/helper.rs"),
-                        line: 7,
-                        column: 1,
-                    }),
-                    inlined: Some(llvm_export::ops::DebugInlinedScope {
-                        callee_name: "helper::next".to_string(),
-                        callsite: Some(DebugSourcePosition {
-                            file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
-                            line: 41,
-                            column: 13,
-                        }),
-                    }),
-                },
-            ],
-            locations: vec![],
-        },
-    );
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let arg = entry.deref(&ctx).get_argument(0);
-
-    let caller_value = DebugValueOp::new(&mut ctx, arg);
-    let caller_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 31, 9);
-    caller_value
-        .get_operation()
-        .deref_mut(&ctx)
-        .set_loc(caller_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        caller_value.get_operation(),
-        DebugLocalVariableInfo {
-            name: "data".to_string(),
-            argument_index: Some(1),
-            ty: DebugLocalTypeKind::Basic {
-                name: "i32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_signed",
-            },
-        },
-    );
-    llvm_export::ops::set_debug_local_source_scope(&mut ctx, caller_value.get_operation(), 0);
-    caller_value.get_operation().insert_at_back(entry, &ctx);
-
-    let inlined_value = DebugValueOp::new(&mut ctx, arg);
-    let inlined_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/helper.rs", 8, 17);
-    inlined_value
-        .get_operation()
-        .deref_mut(&ctx)
-        .set_loc(inlined_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        inlined_value.get_operation(),
-        DebugLocalVariableInfo {
-            name: "self".to_string(),
-            argument_index: Some(1),
-            ty: DebugLocalTypeKind::Basic {
-                name: "i32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_signed",
-            },
-        },
-    );
-    llvm_export::ops::set_debug_local_source_scope(&mut ctx, inlined_value.get_operation(), 1);
-    inlined_value.get_operation().insert_at_back(entry, &ctx);
-
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::Full,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    assert!(
-        ir.contains("distinct !DISubprogram(name: \"caller_kernel\""),
-        "caller should keep its own function debug scope:\n{ir}"
-    );
-    assert!(
-        ir.contains("distinct !DISubprogram(name: \"helper::next\""),
-        "inlined callee should get its own DISubprogram scope:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocalVariable(name: \"data\", arg: 1, scope: !"),
-        "caller argument should remain arg #1 in the caller scope:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocalVariable(name: \"self\", arg: 1, scope: !"),
-        "inlined callee argument should remain arg #1 in the callee scope:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocation(line: 8, column: 17, scope: !") && ir.contains("inlinedAt: !"),
-        "inlined dbg.value location should point at the callee line and caller callsite:\n{ir}"
-    );
-}
-
-#[test]
-fn line_table_debug_metadata_ignores_tagged_alloca_variables() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 40, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
-    let one = ConstantOp::new(&mut ctx, one_attr.into());
-    one.get_operation().insert_at_back(entry, &ctx);
-    let one_val = one.get_operation().deref(&ctx).get_result(0);
-
-    let local = AllocaOp::new(&mut ctx, i32_ty.into(), one_val);
-    let local_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 41, 9);
-    local.get_operation().deref_mut(&ctx).set_loc(local_loc);
-    llvm_export::ops::set_debug_local_variable(
-        &mut ctx,
-        local.get_operation(),
-        DebugLocalVariableInfo {
-            name: "x".to_string(),
-            argument_index: None,
-            ty: DebugLocalTypeKind::Basic {
-                name: "i32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_signed",
-            },
-        },
-    );
-    local.get_operation().insert_at_back(entry, &ctx);
-
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::LineTables,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    assert!(
-        ir.contains("emissionKind: LineTablesOnly"),
-        "line-table mode should stay line-table-only:\n{ir}"
-    );
-    assert!(
-        !ir.contains("llvm.dbg.declare"),
-        "line-table mode should not emit variable bindings:\n{ir}"
-    );
-    assert!(
-        !ir.contains("DILocalVariable"),
-        "line-table mode should not emit local-variable metadata:\n{ir}"
-    );
-}
-
-#[test]
-fn line_table_debug_metadata_adds_fallback_locations_to_calls() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let void_ty = VoidType::get(&ctx);
-    let helper_ty = FuncType::get(&ctx, i32_ty.to_handle(), vec![], false);
-    let helper = FuncOp::new(&mut ctx, "helper".try_into().unwrap(), helper_ty);
-    helper.get_operation().insert_at_back(module_block, &ctx);
-
-    let caller_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let caller = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), caller_ty);
-    let caller_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 20, 3);
-    caller.get_operation().deref_mut(&ctx).set_loc(caller_loc);
-
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    let call = CallOp::new(
-        &mut ctx,
-        CallOpCallable::Direct("helper".try_into().unwrap()),
-        helper_ty,
-        vec![],
-    );
-    call.get_operation().insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::LineTables,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    let call_line = ir
-        .lines()
-        .find(|line| line.contains("call i32 @helper()"))
-        .expect("call instruction");
-    assert!(
-        call_line.contains(", !dbg !"),
-        "calls without their own source span should use the function fallback location:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocation(line: 20, column: 3, scope: !"),
-        "fallback call location should point at the caller's function line:\n{ir}"
-    );
-}
-
-#[test]
-fn line_table_debug_metadata_emits_explicit_artificial_calls_at_line_zero() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = {
-        let region = module_region.deref(&ctx);
-        region.iter(&ctx).next().unwrap()
-    };
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let void_ty = VoidType::get(&ctx);
-    let helper_ty = FuncType::get(&ctx, i32_ty.to_handle(), vec![], false);
-    let helper = FuncOp::new(&mut ctx, "helper".try_into().unwrap(), helper_ty);
-    helper.get_operation().insert_at_back(module_block, &ctx);
-
-    let caller_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
-    let caller = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), caller_ty);
-    let caller_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 20, 3);
-    caller.get_operation().deref_mut(&ctx).set_loc(caller_loc);
-
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    let call = CallOp::new(
-        &mut ctx,
-        CallOpCallable::Direct("helper".try_into().unwrap()),
-        helper_ty,
-        vec![],
-    );
-    call.get_operation()
-        .deref_mut(&ctx)
-        .set_loc(llvm_export::artificial_debug_location());
-    call.get_operation().insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::LineTables,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    let call_line = ir
-        .lines()
-        .find(|line| line.contains("call i32 @helper()"))
-        .expect("call instruction");
-    assert!(
-        call_line.contains(", !dbg !"),
-        "LLVM still requires an artificial call location:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DILocation(line: 0, column: 0, scope: !"),
-        "artificial setup must not reuse the caller's user line:\n{ir}"
-    );
-}
-
-/// Scans the textual LLVM IR and asserts that every `%vN` token appearing in
-/// an operand position has a corresponding `%vN = ...` definition somewhere
-/// in the module. Operates on `%v` temporaries only because that's the
-/// exporter's naming scheme; named values like `%entry` (block labels) are
-/// ignored by construction.
-fn assert_no_undefined_temporaries(ir: &str) {
-    use std::collections::HashSet;
-
-    let mut defined: HashSet<String> = HashSet::new();
-    for line in ir.lines() {
-        let trimmed = line.trim_start();
-        if !trimmed.starts_with("%v") {
-            continue;
-        }
-        let Some((lhs, _)) = trimmed.split_once('=') else {
-            continue;
-        };
-        defined.insert(lhs.trim().to_string());
-    }
-
-    let mut referenced: HashSet<String> = HashSet::new();
-    for line in ir.lines() {
-        let trimmed = line.trim_start();
-        // Skip the lhs of a definition; only operand positions can be stale.
-        let body = if trimmed.starts_with("%v")
-            && let Some(eq) = trimmed.find('=')
-        {
-            &trimmed[eq + 1..]
-        } else {
-            trimmed
-        };
-        for tok in body.split(|c: char| !c.is_alphanumeric() && c != '%' && c != '_') {
-            if let Some(num) = tok.strip_prefix("%v")
-                && !num.is_empty()
-                && num.chars().all(|c| c.is_ascii_digit())
-            {
-                referenced.insert(format!("%v{num}"));
-            }
-        }
-    }
-
-    let mut undefined: Vec<&String> = referenced.difference(&defined).collect();
-    undefined.sort();
-    assert!(
-        undefined.is_empty(),
-        "IR references undefined SSA temporaries: {undefined:?}\nIR:\n{ir}"
-    );
-}
-
-/// A float binop carrying `FastmathFlags` must export with the matching LLVM
-/// fast-math keyword (`fast` for the all-bits set), while a float binop with no
-/// flags must export with none. Regression guard: the textual exporter
-/// previously dropped fast-math flags entirely, making the `f*_fast` intrinsic
-/// lowering inert end to end.
-#[test]
-fn export_emits_fast_math_flags_only_on_flagged_float_ops() {
-    use llvm_export::attributes::FastmathFlags;
-    use llvm_export::op_interfaces::{BinArithOp, FloatBinArithOpWithFastMathFlags};
-    use llvm_export::ops::{FAddOp, FMulOp};
-    use pliron::builtin::types::FP32Type;
-
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-
-    let f32_ty = FP32Type::get(&ctx);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(
-        &ctx,
-        void_ty.to_handle(),
-        vec![f32_ty.into(), f32_ty.into()],
-        false,
-    );
-    let func = FuncOp::new(&mut ctx, "fast_math".try_into().unwrap(), func_ty);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-    let a = entry.deref(&ctx).get_argument(0);
-    let b = entry.deref(&ctx).get_argument(1);
-
-    // fadd with the full fast-math set.
-    let fadd = FAddOp::new_with_fast_math_flags(&mut ctx, a, b, FastmathFlags::FAST.into());
-    fadd.get_operation().insert_at_back(entry, &ctx);
-    // fmul with no flags: must stay flag-free.
-    let fmul = FMulOp::new(&mut ctx, a, b);
-    fmul.get_operation().insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
-
-    assert!(
-        ir.contains("fadd fast float"),
-        "fast-math fadd must export the `fast` keyword:\n{ir}"
-    );
-    let fmul_line = ir
-        .lines()
-        .find(|line| line.contains("fmul"))
-        .expect("exported fmul line");
-    assert!(
-        !fmul_line.contains("fast"),
-        "a float binop with no fast-math flags must not gain them:\n{ir}"
-    );
-}
-
-#[test]
-fn modern_device_extern_emits_signext_zeroext_for_small_integer_params() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "small_types_extern".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    // The extern takes (i8 signext, i16 zeroext, i1 zeroext, half) and
-    // returns void. The declared IR types stay NARROW (matching cuda-oxide's
-    // own i8/i16/i1 SSA values and the clang-compiled LTOIR definition); the
-    // ABI extension attributes live only in the DeviceExternType metadata.
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let i16_ty = IntegerType::get(&ctx, 16, Signedness::Signless);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let half_ty = HalfType::get(&ctx);
-    let void_ty = VoidType::get(&ctx);
-
-    let external_ty = FuncType::get(
-        &ctx,
-        void_ty.into(),
-        vec![i8_ty.into(), i16_ty.into(), i1_ty.into(), half_ty.into()],
-        false,
-    );
-    FuncOp::new(&mut ctx, "small_types_fn".try_into().unwrap(), external_ty)
-        .get_operation()
-        .insert_at_back(module_block, &ctx);
-
-    // Caller that forwards its own narrow parameters to the extern with no
-    // value conversions.
-    let caller_ty = FuncType::get(
-        &ctx,
-        void_ty.into(),
-        vec![i8_ty.into(), i16_ty.into(), i1_ty.into(), half_ty.into()],
-        false,
-    );
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), caller_ty);
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    let arg0 = entry.deref(&ctx).get_argument(0);
-    let arg1 = entry.deref(&ctx).get_argument(1);
-    let arg2 = entry.deref(&ctx).get_argument(2);
-    let arg3 = entry.deref(&ctx).get_argument(3);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Direct("small_types_fn".try_into().unwrap()),
-        external_ty,
-        vec![arg0, arg1, arg2, arg3],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let externs = [DeviceExternDecl {
-        export_name: "small_types_fn".to_string(),
-        param_types: vec![
-            DeviceExternType::SignExtInteger(8), // i8, sign-extended by NVPTX
-            DeviceExternType::ZeroExtInteger(16), // u16, zero-extended by NVPTX
-            DeviceExternType::ZeroExtInteger(1), // bool
-            DeviceExternType::Float16,           // f16 as native half
-        ],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-
-    let ir = export_module_with_externs(
-        &ctx,
-        &module,
-        &externs,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect("modern extern with small types export succeeds");
-
-    // Declaration: narrow types with parameter-position attributes.
-    assert!(
-        ir.contains("declare void @small_types_fn(i8 signext, i16 zeroext, i1 zeroext, half)"),
-        "declaration should keep narrow types with signext/zeroext attributes:\n{ir}"
-    );
-
-    // Call site keeps the narrow types and attributes too.
-    assert!(
-        ir.contains("i8 signext %v0"),
-        "call should use signext on first arg:\n{ir}"
-    );
-    assert!(
-        ir.contains("i16 zeroext %v1"),
-        "call should use zeroext on second arg:\n{ir}"
-    );
-    assert!(
-        ir.contains("i1 zeroext %v2"),
-        "call should use zeroext on the bool arg:\n{ir}"
-    );
-    assert!(
-        ir.contains("half %v3"),
-        "call should use half for the f16 arg:\n{ir}"
-    );
-}
-
-#[test]
-fn modern_device_extern_signext_return_type() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "signext_return".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let void_ty = VoidType::get(&ctx);
-
-    // Extern returns i8 with signext. The declared type stays i8; only the
-    // attribute marks the NVPTX widening, and in return position LLVM's
-    // grammar requires the attribute BEFORE the type.
-    let external_ty = FuncType::get(&ctx, i8_ty.into(), vec![], false);
-    FuncOp::new(&mut ctx, "get_small_val".try_into().unwrap(), external_ty)
-        .get_operation()
-        .insert_at_back(module_block, &ctx);
-
-    // Caller that calls the extern and discards the result.
-    let caller_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), caller_ty);
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Direct("get_small_val".try_into().unwrap()),
-        external_ty,
-        vec![],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let externs = [DeviceExternDecl {
-        export_name: "get_small_val".to_string(),
-        param_types: vec![],
-        return_type: DeviceExternType::SignExtInteger(8),
-        attrs: DeviceExternAttrs::default(),
-    }];
-
-    let ir = export_module_with_externs(
-        &ctx,
-        &module,
-        &externs,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect("modern extern with signext return export succeeds");
-
-    // Declaration: attribute precedes the narrow return type.
-    assert!(
-        ir.contains("declare signext i8 @get_small_val()"),
-        "declaration should have signext BEFORE the return type:\n{ir}"
-    );
-
-    // Call site uses the same return-position placement.
-    assert!(
-        ir.contains("call signext i8 @get_small_val()"),
-        "call should have signext BEFORE the return type:\n{ir}"
-    );
-}
-
-#[test]
-fn plain_integer_device_extern_has_no_extension_attributes() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "plain_int".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let void_ty = VoidType::get(&ctx);
-
-    let external_ty = FuncType::get(&ctx, void_ty.into(), vec![i32_ty.into()], false);
-    FuncOp::new(&mut ctx, "plain_int_fn".try_into().unwrap(), external_ty)
-        .get_operation()
-        .insert_at_back(module_block, &ctx);
-
-    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), external_ty);
-    let entry = caller.get_or_create_entry_block(&mut ctx);
-    let arg0 = entry.deref(&ctx).get_argument(0);
-    CallOp::new(
-        &mut ctx,
-        CallOpCallable::Direct("plain_int_fn".try_into().unwrap()),
-        external_ty,
-        vec![arg0],
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    let externs = [DeviceExternDecl {
-        export_name: "plain_int_fn".to_string(),
-        param_types: vec![DeviceExternType::Integer(32)],
-        return_type: DeviceExternType::Void,
-        attrs: DeviceExternAttrs::default(),
-    }];
-
-    let ir = export_module_with_externs(
-        &ctx,
-        &module,
-        &externs,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect("plain int extern export succeeds");
-
-    // Plain i32 should have no signext/zeroext.
-    assert!(
-        ir.contains("declare void @plain_int_fn(i32)"),
-        "declaration should have plain i32 without attributes:\n{ir}"
-    );
-    assert!(
-        !ir.contains("signext") && !ir.contains("zeroext"),
-        "plain i32 should have no extension attributes:\n{ir}"
-    );
-}
-
-#[test]
-fn legacy_device_extern_rejects_small_integers_by_value() {
-    let mut ctx = Context::new();
-    let empty = ModuleOp::new(&mut ctx, "empty".try_into().unwrap());
-    let externs = [DeviceExternDecl {
-        export_name: "takes_small".to_string(),
-        param_types: vec![DeviceExternType::SignExtInteger(8)],
-        return_type: DeviceExternType::ZeroExtInteger(16),
-        attrs: DeviceExternAttrs::default(),
-    }];
-    let err = export_module_with_externs(
-        &ctx,
-        &empty,
-        &externs,
-        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
-    )
-    .expect_err("legacy sub-32-bit by-value externs must fail cleanly");
-    assert!(
-        err.contains("CUDA 12 legacy") && err.contains("sub-32-bit"),
-        "{err}"
-    );
-}
-
-/// Build a module whose externs carry small params AND a small return, in
-/// both declare and call positions, so the emitted attribute placement can
-/// be checked against a real LLVM parser.
-fn small_type_extern_module(ctx: &mut Context) -> (ModuleOp, Vec<DeviceExternDecl>) {
-    let module = ModuleOp::new(ctx, "small_types_parse_gate".try_into().unwrap());
-    let module_block = module_top_block(ctx, &module);
-
-    let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
-    let i16_ty = IntegerType::get(ctx, 16, Signedness::Signless);
-    let i1_ty = IntegerType::get(ctx, 1, Signedness::Signless);
-    let half_ty = HalfType::get(ctx);
-    let void_ty = VoidType::get(ctx);
-
-    let take_small_ty = FuncType::get(
-        ctx,
-        void_ty.into(),
-        vec![i8_ty.into(), i16_ty.into(), i1_ty.into(), half_ty.into()],
-        false,
-    );
-    FuncOp::new(ctx, "take_small".try_into().unwrap(), take_small_ty)
-        .get_operation()
-        .insert_at_back(module_block, &*ctx);
-
-    let give_small_ty = FuncType::get(ctx, i8_ty.into(), vec![], false);
-    FuncOp::new(ctx, "give_small".try_into().unwrap(), give_small_ty)
-        .get_operation()
-        .insert_at_back(module_block, &*ctx);
-
-    let caller_ty = FuncType::get(
-        ctx,
-        void_ty.into(),
-        vec![i8_ty.into(), i16_ty.into(), i1_ty.into(), half_ty.into()],
-        false,
-    );
-    let caller = FuncOp::new(ctx, "caller".try_into().unwrap(), caller_ty);
-    let entry = caller.get_or_create_entry_block(ctx);
-    let arg0 = entry.deref(ctx).get_argument(0);
-    let arg1 = entry.deref(ctx).get_argument(1);
-    let arg2 = entry.deref(ctx).get_argument(2);
-    let arg3 = entry.deref(ctx).get_argument(3);
-    CallOp::new(
-        ctx,
-        CallOpCallable::Direct("take_small".try_into().unwrap()),
-        take_small_ty,
-        vec![arg0, arg1, arg2, arg3],
-    )
-    .get_operation()
-    .insert_at_back(entry, &*ctx);
-    CallOp::new(
-        ctx,
-        CallOpCallable::Direct("give_small".try_into().unwrap()),
-        give_small_ty,
-        vec![],
-    )
-    .get_operation()
-    .insert_at_back(entry, &*ctx);
-    ReturnOp::new(ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &*ctx);
-    caller.get_operation().insert_at_back(module_block, &*ctx);
-
-    let externs = vec![
-        DeviceExternDecl {
-            export_name: "take_small".to_string(),
-            param_types: vec![
-                DeviceExternType::SignExtInteger(8),
-                DeviceExternType::ZeroExtInteger(16),
-                DeviceExternType::ZeroExtInteger(1),
-                DeviceExternType::Float16,
-            ],
-            return_type: DeviceExternType::Void,
-            attrs: DeviceExternAttrs::default(),
-        },
-        DeviceExternDecl {
-            export_name: "give_small".to_string(),
-            param_types: vec![],
-            return_type: DeviceExternType::SignExtInteger(8),
-            attrs: DeviceExternAttrs::default(),
-        },
-    ];
-    (module, externs)
-}
-
-/// Parse gate: the emitted attribute placement (`i8 signext` in parameter
-/// position, `signext i8` in return position, for both `declare` and `call`)
-/// must be accepted by a real LLVM parser, not just string-matched.
-#[test]
-fn small_type_extern_module_parses_with_llvm_as() {
-    let mut ctx = Context::new();
-    let (module, externs) = small_type_extern_module(&mut ctx);
-    let ir = export_module_with_externs(
-        &ctx,
-        &module,
-        &externs,
-        &NvvmExportConfig::new(NvvmIrDialect::Modern),
-    )
-    .expect("modern small-type extern export succeeds");
-
-    // Belt-and-braces string checks before the external parse.
-    assert!(
-        ir.contains("declare void @take_small(i8 signext, i16 zeroext, i1 zeroext, half)"),
-        "{ir}"
-    );
-    assert!(ir.contains("declare signext i8 @give_small()"), "{ir}");
-    assert!(ir.contains("call signext i8 @give_small()"), "{ir}");
-
-    let Some(llvm_as) = ["llvm-as-22", "llvm-as-21", "llvm-as"]
-        .into_iter()
-        .find(|tool| {
-            std::process::Command::new(tool)
-                .arg("--version")
-                .output()
-                .is_ok_and(|out| out.status.success())
-        })
-    else {
-        eprintln!("skipping llvm-as parse gate: no llvm-as-22/llvm-as-21/llvm-as on PATH");
-        return;
-    };
-
-    let ll_path = std::env::temp_dir().join(format!(
-        "cuda_oxide_small_type_parse_gate_{}.ll",
-        std::process::id()
-    ));
-    std::fs::write(&ll_path, &ir).expect("write temp .ll");
-    let output = std::process::Command::new(llvm_as)
-        .arg("-o")
-        .arg("/dev/null")
-        .arg(&ll_path)
-        .output()
-        .expect("run llvm-as");
-    let stderr = String::from_utf8_lossy(&output.stderr).into_owned();
-    let _ = std::fs::remove_file(&ll_path);
-    assert!(
-        output.status.success(),
-        "{llvm_as} rejected the emitted module:\n{stderr}\n--- module ---\n{ir}"
-    );
-}
-
-/// Builds a `void` function taking pointer parameters in the given address
-/// spaces, with an empty body, optionally carrying the `gpu_kernel` marker
-/// the exporter uses to distinguish an entry from a device function.
-fn pointer_param_function(
-    ctx: &mut Context,
-    module_block: Ptr<BasicBlock>,
-    name: &str,
-    address_spaces: &[u32],
-    is_kernel: bool,
-) {
-    let params: Vec<_> = address_spaces
-        .iter()
-        .map(|space| PointerType::get(ctx, *space).into())
-        .collect();
-    let void_ty = VoidType::get(ctx);
-    let func_ty = FuncType::get(ctx, void_ty.into(), params, false);
-    let func = FuncOp::new(ctx, name.try_into().unwrap(), func_ty);
-    if is_kernel {
-        let kernel_key: Identifier = "gpu_kernel".try_into().unwrap();
-        func.get_operation()
-            .deref_mut(ctx)
-            .attributes
-            .set(kernel_key, StringAttr::new("true".to_string()));
-    }
-    let entry = func.get_or_create_entry_block(ctx);
-    ReturnOp::new(ctx, None)
-        .get_operation()
-        .insert_at_back(entry, ctx);
-    func.get_operation().insert_at_back(module_block, ctx);
-}
-
-/// A kernel receives its parameters in `.param` space from the host, which
-/// holds no shared-memory address to pass. The exporter must refuse the
-/// signature instead of emitting `.ptr .shared`, which ptxas accepts but the
-/// driver rejects at module load, taking every kernel in the module down.
-#[test]
-fn kernel_rejects_a_shared_memory_pointer_parameter() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "kernel_shared_param".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    pointer_param_function(&mut ctx, module_block, "shared_param", &[0, 3], true);
-
-    let error = export_module_to_string(&ctx, &module)
-        .expect_err("export must refuse a kernel parameter in shared memory");
-    assert!(
-        error.contains(
-            "kernel `@shared_param` parameter 1 is a pointer into shared memory (address space 3)"
-        ),
-        "{error}"
-    );
-}
-
-/// Local memory is per-thread, so the host has no address in it to pass
-/// either; the exporter refuses it on the same grounds as shared.
-#[test]
-fn kernel_rejects_a_local_memory_pointer_parameter() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "kernel_local_param".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    pointer_param_function(&mut ctx, module_block, "local_param", &[5], true);
-
-    let error = export_module_to_string(&ctx, &module)
-        .expect_err("export must refuse a kernel parameter in local memory");
-    assert!(
-        error.contains(
-            "kernel `@local_param` parameter 0 is a pointer into local memory (address space 5)"
-        ),
-        "{error}"
-    );
-}
-
-/// The refusal is scoped to what the host cannot supply. Generic, global,
-/// and constant pointer parameters are host-addressable and stay accepted on
-/// kernels, and a device (non-kernel) function may carry any state space on
-/// its parameters, shared included.
-#[test]
-fn kernel_keeps_host_addressable_pointer_parameters_and_device_functions_keep_shared() {
-    let mut ctx = Context::new();
-    let module = ModuleOp::new(&mut ctx, "kernel_allowed_params".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    pointer_param_function(&mut ctx, module_block, "allowed_param", &[0, 1, 4], true);
-    pointer_param_function(&mut ctx, module_block, "device_shared", &[3], false);
-
-    let ir = export_module_to_string(&ctx, &module)
-        .expect("generic/global/constant kernel parameters and device shared must export");
-    assert!(
-        ir.contains(
-            "define ptx_kernel void @allowed_param(ptr %v0, ptr addrspace(1) %v1, ptr addrspace(4) %v2)"
-        ),
-        "{ir}"
-    );
-    assert!(
-        ir.contains("define void @device_shared(ptr addrspace(3) %v0)"),
-        "{ir}"
-    );
-}
-
-#[test]
-fn full_debug_metadata_emits_scalarized_fragment_dbg_declares() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "fragment_debug".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
-    let func = FuncOp::new(
-        &mut ctx,
-        "fragment_debug_kernel".try_into().unwrap(),
-        func_ty,
-    );
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/fragments.rs", 10, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
-    let one = ConstantOp::new(&mut ctx, one_attr.into());
-    let one_value = one.get_operation().deref(&ctx).get_result(0);
-    one.get_operation().insert_at_back(entry, &ctx);
-
-    let whole_ty = DebugLocalTypeKind::Array {
-        name: "[u32; 2]".to_string(),
-        size_bits: 64,
-        element: Box::new(DebugLocalTypeKind::Basic {
-            name: "u32".to_string(),
-            size_bits: 32,
-            encoding: "DW_ATE_unsigned",
-        }),
-        count: 2,
-    };
-    for (index, offset_bits) in [0u64, 32].into_iter().enumerate() {
-        let alloca = AllocaOp::new(&mut ctx, i32_ty.into(), one_value);
-        llvm_export::ops::set_debug_fragment_variables(
-            &mut ctx,
-            alloca.get_operation(),
-            &[DebugFragmentVariableInfo {
-                variable: DebugLocalVariableInfo {
-                    name: "pair".to_string(),
-                    argument_index: None,
-                    ty: whole_ty.clone(),
-                },
-                fragment: DebugFragment {
-                    offset_bits,
-                    size_bits: 32,
-                },
-                source_scope: None,
-                declaration: Some(DebugSourcePosition {
-                    file: PathBuf::from("/tmp/cuda-oxide/tests/fragments.rs"),
-                    line: 11,
-                    column: 9,
-                }),
-            }],
-        );
-        let loc = src_location(
-            &mut ctx,
-            "/tmp/cuda-oxide/tests/fragments.rs",
-            12 + index as i32,
-            9,
-        );
-        alloca.get_operation().deref_mut(&ctx).set_loc(loc);
-        alloca.get_operation().insert_at_back(entry, &ctx);
-    }
-
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::Full,
-    };
-    let ir =
-        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
-
-    assert!(
-        ir.contains("DW_OP_LLVM_fragment, 0, 32"),
-        "first scalarized piece should describe the low fragment:\n{ir}"
-    );
-    assert!(
-        ir.contains("DW_OP_LLVM_fragment, 32, 32"),
-        "second scalarized piece should describe the high fragment:\n{ir}"
-    );
-    assert_eq!(
-        ir.matches("!DILocalVariable(name: \"pair\"").count(),
-        1,
-        "all pieces must share one DILocalVariable identity:\n{ir}"
-    );
-    assert_eq!(
-        ir.matches("call void @llvm.dbg.declare").count(),
-        2,
-        "each scalarized storage piece should emit one dbg.declare:\n{ir}"
-    );
-
-    let Some(llvm_as) = ["llvm-as-22", "llvm-as-21", "llvm-as"]
-        .into_iter()
-        .find(|tool| {
-            std::process::Command::new(tool)
-                .arg("--version")
-                .output()
-                .is_ok_and(|out| out.status.success())
-        })
-    else {
-        eprintln!("skipping fragment llvm-as parse gate: no llvm-as on PATH");
-        return;
-    };
-    let ll_path = std::env::temp_dir().join(format!(
-        "cuda_oxide_fragment_parse_gate_{}.ll",
-        std::process::id()
-    ));
-    std::fs::write(&ll_path, &ir).expect("write fragment temp .ll");
-    let output = std::process::Command::new(llvm_as)
-        .arg("-o")
-        .arg("/dev/null")
-        .arg(&ll_path)
-        .output()
-        .expect("run llvm-as for fragments");
-    let stderr = String::from_utf8_lossy(&output.stderr).into_owned();
-    let _ = std::fs::remove_file(&ll_path);
-    assert!(
-        output.status.success(),
-        "{llvm_as} rejected scalarized fragment debug metadata:\n{stderr}\n--- module ---\n{ir}"
-    );
-}
-
-#[test]
-fn full_debug_metadata_emits_projected_dbg_declares() {
-    let mut ctx = Context::new();
-
-    let module = ModuleOp::new(&mut ctx, "projected_debug".try_into().unwrap());
-    let module_block = module_top_block(&mut ctx, &module);
-    let void_ty = VoidType::get(&ctx);
-    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
-    let func = FuncOp::new(
-        &mut ctx,
-        "projected_debug_kernel".try_into().unwrap(),
-        func_ty,
-    );
-    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/projected.rs", 10, 1);
-    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
-    let entry = func.get_or_create_entry_block(&mut ctx);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
-    let one = ConstantOp::new(&mut ctx, one_attr.into());
-    let one_value = one.get_operation().deref(&ctx).get_result(0);
-    one.get_operation().insert_at_back(entry, &ctx);
-
-    let storage_ty = ArrayType::get(&ctx, i32_ty.into(), 8);
-    let alloca = AllocaOp::new(&mut ctx, storage_ty.into(), one_value);
-    llvm_export::ops::set_debug_projected_variables(
-        &mut ctx,
-        alloca.get_operation(),
-        &[
-            DebugProjectedVariableInfo {
-                variable: DebugLocalVariableInfo {
-                    name: "field_value".to_string(),
-                    argument_index: None,
-                    ty: DebugLocalTypeKind::Basic {
-                        name: "u32".to_string(),
-                        size_bits: 32,
-                        encoding: "DW_ATE_unsigned",
-                    },
-                },
-                dereference_base: false,
-                offset_bytes: 8,
-                source_scope: None,
-                declaration: Some(DebugSourcePosition {
-                    file: PathBuf::from("/tmp/cuda-oxide/tests/projected.rs"),
-                    line: 11,
-                    column: 9,
-                }),
-            },
-            DebugProjectedVariableInfo {
-                variable: DebugLocalVariableInfo {
-                    name: "tuple_value".to_string(),
-                    argument_index: None,
-                    ty: DebugLocalTypeKind::Basic {
-                        name: "u64".to_string(),
-                        size_bits: 64,
-                        encoding: "DW_ATE_unsigned",
-                    },
-                },
-                dereference_base: false,
-                offset_bytes: 16,
-                source_scope: None,
-                declaration: Some(DebugSourcePosition {
-                    file: PathBuf::from("/tmp/cuda-oxide/tests/projected.rs"),
-                    line: 12,
-                    column: 9,
-                }),
-            },
-            DebugProjectedVariableInfo {
-                variable: DebugLocalVariableInfo {
-                    name: "array_value".to_string(),
-                    argument_index: None,
-                    ty: DebugLocalTypeKind::Basic {
-                        name: "u32".to_string(),
-                        size_bits: 32,
-                        encoding: "DW_ATE_unsigned",
-                    },
-                },
-                dereference_base: false,
-                offset_bytes: 24,
-                source_scope: None,
-                declaration: Some(DebugSourcePosition {
-                    file: PathBuf::from("/tmp/cuda-oxide/tests/projected.rs"),
-                    line: 13,
-                    column: 9,
-                }),
-            },
-            DebugProjectedVariableInfo {
-                variable: DebugLocalVariableInfo {
-                    name: "deref_value".to_string(),
-                    argument_index: None,
-                    ty: DebugLocalTypeKind::Basic {
-                        name: "u32".to_string(),
-                        size_bits: 32,
-                        encoding: "DW_ATE_unsigned",
-                    },
-                },
-                dereference_base: true,
-                offset_bytes: 0,
-                source_scope: None,
-                declaration: Some(DebugSourcePosition {
-                    file: PathBuf::from("/tmp/cuda-oxide/tests/projected.rs"),
-                    line: 14,
-                    column: 9,
-                }),
-            },
-            DebugProjectedVariableInfo {
-                variable: DebugLocalVariableInfo {
-                    name: "deref_field_value".to_string(),
-                    argument_index: None,
-                    ty: DebugLocalTypeKind::Basic {
-                        name: "u64".to_string(),
-                        size_bits: 64,
-                        encoding: "DW_ATE_unsigned",
-                    },
-                },
-                dereference_base: true,
-                offset_bytes: 32,
-                source_scope: None,
-                declaration: Some(DebugSourcePosition {
-                    file: PathBuf::from("/tmp/cuda-oxide/tests/projected.rs"),
-                    line: 15,
-                    column: 9,
-                }),
-            },
-        ],
-    );
-    alloca.get_operation().insert_at_back(entry, &ctx);
-    ReturnOp::new(&mut ctx, None)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    let config = DebugConfig {
-        inner: PtxExportConfig,
-        debug_kind: DebugKind::Full,
-    };
-    let ir = export_module_to_string_with_config(&ctx, &module, &config)
-        .expect("projected debug export succeeds");
-
-    assert_eq!(
-        ir.matches("call void @llvm.dbg.declare").count(),
-        5,
-        "each projected source variable should get its own dbg.declare:\n{ir}"
-    );
-    for name in [
-        "field_value",
-        "tuple_value",
-        "array_value",
-        "deref_value",
-        "deref_field_value",
-    ] {
-        assert!(
-            ir.contains(&format!("!DILocalVariable(name: \"{name}\"")),
-            "missing projected variable {name}:\n{ir}"
-        );
-    }
-    for offset in [8u64, 16, 24] {
-        assert!(
-            ir.contains(&format!("!DIExpression(DW_OP_plus_uconst, {offset})")),
-            "missing static projection offset {offset}:\n{ir}"
-        );
-    }
-    assert!(
-        ir.contains("!DIExpression(DW_OP_deref)"),
-        "missing dereference-only debug expression:\n{ir}"
-    );
-    assert!(
-        ir.contains("!DIExpression(DW_OP_deref, DW_OP_plus_uconst, 32)"),
-        "missing dereference-plus-field debug expression:\n{ir}"
-    );
-}
diff --git a/crates/llvm-export/tests/export_test/calls_and_addresses.rs b/crates/llvm-export/tests/export_test/calls_and_addresses.rs
new file mode 100644
index 0000000000..7535b36f12
--- /dev/null
+++ b/crates/llvm-export/tests/export_test/calls_and_addresses.rs
@@ -0,0 +1,377 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use llvm_export::{
+    export::{
+        NvvmExportConfig, NvvmIrDialect, export_module_to_string,
+        export_module_to_string_with_config,
+    },
+    ops::{AddressOfOp, BrOp, CallOp, FuncOp, GepIndex, GetElementPtrOp, GlobalOp, ReturnOp},
+    types::{FuncType, PointerType, VoidType},
+};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::{
+        op_interfaces::CallOpCallable,
+        ops::ModuleOp,
+        types::{IntegerType, Signedness},
+    },
+    context::Context,
+    linked_list::ContainsLinkedList,
+    op::Op,
+};
+
+use crate::common::{assert_no_undefined_temporaries, module_top_block};
+
+#[test]
+fn indirect_call_rejects_non_program_address_space() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "invalid_indirect_callee".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let shared_ptr_ty = PointerType::get(&ctx, 3);
+    let void_ty = VoidType::get(&ctx);
+    let callee_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
+    let caller_ty = FuncType::get(&ctx, void_ty.into(), vec![shared_ptr_ty.into()], false);
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), caller_ty);
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    let callee = entry.deref(&ctx).get_argument(0);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Indirect(callee),
+        callee_ty,
+        vec![],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    for dialect in [NvvmIrDialect::LegacyLlvm7, NvvmIrDialect::Modern] {
+        let error =
+            export_module_to_string_with_config(&ctx, &module, &NvvmExportConfig::new(dialect))
+                .expect_err("NVPTX must reject a shared-memory function pointer");
+        assert!(error.contains("address space 3"), "{error}");
+        assert!(error.contains("function pointers"), "{error}");
+    }
+}
+
+#[test]
+fn intrinsic_export_preserves_legacy_dots_and_literal_underscores() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "intrinsic_names".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let void_ty = VoidType::get(&ctx);
+    let function_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
+    let legacy = "llvm_nvvm_wgmma_fence_sync_aligned";
+    let escaped = "llvm__nvvm_dwgmma_dcommit_ugroup_dsync_daligned";
+
+    for name in [legacy, escaped] {
+        FuncOp::new(&mut ctx, name.try_into().unwrap(), function_ty)
+            .get_operation()
+            .insert_at_back(module_block, &ctx);
+    }
+
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), function_ty);
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    for name in [legacy, escaped] {
+        CallOp::new(
+            &mut ctx,
+            CallOpCallable::Direct(name.try_into().unwrap()),
+            function_ty,
+            vec![],
+        )
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    }
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string(&ctx, &module).expect("intrinsic export succeeds");
+    assert!(ir.contains("@llvm.nvvm.wgmma.fence.sync.aligned"), "{ir}");
+    assert!(
+        ir.contains("@llvm.nvvm.wgmma.commit_group.sync.aligned"),
+        "{ir}"
+    );
+    assert!(!ir.contains("@llvm.nvvm.wgmma.commit.group"), "{ir}");
+}
+
+#[test]
+fn legacy_function_address_defined_later_round_trips_through_indirect_call() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "function_address".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let void_ty = VoidType::get(&ctx);
+    let callee_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
+
+    // Print the caller first to prove symbol typing is a module pre-pass, not
+    // an accidental dependency on textual definition order.
+    let caller = FuncOp::new(
+        &mut ctx,
+        "call_function_pointer".try_into().unwrap(),
+        callee_ty,
+    );
+    let caller_entry = caller.get_or_create_entry_block(&mut ctx);
+    let address = AddressOfOp::new(&mut ctx, "target".try_into().unwrap(), 0);
+    let address_value = address.get_operation().deref(&ctx).get_result(0);
+    address.get_operation().insert_at_back(caller_entry, &ctx);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Indirect(address_value),
+        callee_ty,
+        vec![],
+    )
+    .get_operation()
+    .insert_at_back(caller_entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(caller_entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let target = FuncOp::new(&mut ctx, "target".try_into().unwrap(), callee_ty);
+    let target_entry = target.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(target_entry, &ctx);
+    target.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect("legacy function-address export succeeds");
+    assert!(
+        ir.contains("bitcast void ()* @target to i8*"),
+        "function address must normalize to the canonical byte pointer:\n{ir}"
+    );
+    assert!(
+        ir.contains("bitcast i8*") && ir.contains("to void ()*"),
+        "indirect call must restore the exact function pointer type:\n{ir}"
+    );
+    assert!(ir.contains("call void %"), "{ir}");
+}
+
+#[test]
+fn modern_function_address_uses_the_normalized_definition_name() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "modern_function_address".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let void_ty = VoidType::get(&ctx);
+    let callee_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
+    let prefixed_name = reserved_oxide_symbols::device_symbol("target");
+
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), callee_ty);
+    let caller_entry = caller.get_or_create_entry_block(&mut ctx);
+    let address = AddressOfOp::new(&mut ctx, prefixed_name.as_str().try_into().unwrap(), 0);
+    let address_value = address.get_operation().deref(&ctx).get_result(0);
+    address.get_operation().insert_at_back(caller_entry, &ctx);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Indirect(address_value),
+        callee_ty,
+        vec![],
+    )
+    .get_operation()
+    .insert_at_back(caller_entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(caller_entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let target = FuncOp::new(
+        &mut ctx,
+        prefixed_name.as_str().try_into().unwrap(),
+        callee_ty,
+    );
+    let target_entry = target.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(target_entry, &ctx);
+    target.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect("modern function-address export succeeds");
+    assert!(ir.contains("define void @target()"), "{ir}");
+    assert!(ir.contains("call void @target()"), "{ir}");
+    assert!(!ir.contains(&prefixed_name), "{ir}");
+}
+
+#[test]
+fn modern_addressof_rejects_global_and_function_address_space_mismatches() {
+    let mut ctx = Context::new();
+    let void_ty = VoidType::get(&ctx);
+    let no_args = FuncType::get(&ctx, void_ty.into(), vec![], false);
+
+    let global_module = ModuleOp::new(&mut ctx, "bad_global_address".try_into().unwrap());
+    let global_module_block = module_top_block(&mut ctx, &global_module);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let global = GlobalOp::new(&mut ctx, "shared_value".try_into().unwrap(), i32_ty.into());
+    global.set_address_space(&mut ctx, 3);
+    global
+        .get_operation()
+        .insert_at_back(global_module_block, &ctx);
+    let global_user = FuncOp::new(&mut ctx, "global_user".try_into().unwrap(), no_args);
+    let global_entry = global_user.get_or_create_entry_block(&mut ctx);
+    AddressOfOp::new(&mut ctx, "shared_value".try_into().unwrap(), 0)
+        .get_operation()
+        .insert_at_back(global_entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(global_entry, &ctx);
+    global_user
+        .get_operation()
+        .insert_at_back(global_module_block, &ctx);
+    let error = export_module_to_string_with_config(
+        &ctx,
+        &global_module,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect_err("modern global addressof must preserve address spaces");
+    assert!(
+        error.contains("result is 0, global is 3"),
+        "unexpected global error: {error}"
+    );
+
+    let function_module = ModuleOp::new(&mut ctx, "bad_function_address".try_into().unwrap());
+    let function_module_block = module_top_block(&mut ctx, &function_module);
+    FuncOp::new(&mut ctx, "target".try_into().unwrap(), no_args)
+        .get_operation()
+        .insert_at_back(function_module_block, &ctx);
+    let function_user = FuncOp::new(&mut ctx, "function_user".try_into().unwrap(), no_args);
+    let function_entry = function_user.get_or_create_entry_block(&mut ctx);
+    AddressOfOp::new(&mut ctx, "target".try_into().unwrap(), 3)
+        .get_operation()
+        .insert_at_back(function_entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(function_entry, &ctx);
+    function_user
+        .get_operation()
+        .insert_at_back(function_module_block, &ctx);
+    let error = export_module_to_string_with_config(
+        &ctx,
+        &function_module,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect_err("modern function addressof must use program address space");
+    assert!(error.contains("program-address-space (0)"), "{error}");
+}
+
+#[test]
+fn export_addressof_uses_symbol_when_definition_block_prints_later() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let existing = {
+            let region = module_region.deref(&ctx);
+            region.iter(&ctx).next()
+        };
+        if let Some(block) = existing {
+            block
+        } else {
+            let block = BasicBlock::new(&mut ctx, None, vec![]);
+            block.insert_at_back(module_region, &ctx);
+            block
+        }
+    };
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let global = GlobalOp::new(
+        &mut ctx,
+        "__shared_mem_20".try_into().unwrap(),
+        i32_ty.to_handle(),
+    );
+    global.set_address_space(&mut ctx, 3);
+    global.get_operation().insert_at_back(module_block, &ctx);
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "uses_late_addressof".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let func_region = func.get_operation().deref(&ctx).get_region(0);
+    let use_block = BasicBlock::new(&mut ctx, None, vec![]);
+    use_block.insert_at_back(func_region, &ctx);
+    let address_block = BasicBlock::new(&mut ctx, None, vec![]);
+    address_block.insert_at_back(func_region, &ctx);
+
+    BrOp::new(&mut ctx, address_block, vec![])
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+
+    let address = AddressOfOp::new(&mut ctx, "__shared_mem_20".try_into().unwrap(), 3);
+    let address_value = address.get_operation().deref(&ctx).get_result(0);
+    address.get_operation().insert_at_back(address_block, &ctx);
+    BrOp::new(&mut ctx, use_block, vec![])
+        .get_operation()
+        .insert_at_back(address_block, &ctx);
+
+    let gep = GetElementPtrOp::new(
+        &mut ctx,
+        address_value,
+        vec![GepIndex::Constant(0)],
+        i32_ty.to_handle(),
+    );
+    gep.get_operation().insert_at_back(use_block, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(use_block, &ctx);
+
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
+
+    // The shared global must be declared at module scope.
+    assert!(
+        ir.contains("@__shared_mem_20 = addrspace(3) global"),
+        "module must declare the shared global:\n{ir}"
+    );
+
+    // The GEP base operand must be the global symbol, not a stale `%vN`.
+    let gep_line = ir
+        .lines()
+        .find(|line| line.contains("getelementptr inbounds"))
+        .expect("exported GEP line");
+    assert!(
+        gep_line.contains("@__shared_mem_20"),
+        "GEP must use the global symbol, not a stale temporary:\n{ir}"
+    );
+
+    // Bug class from issue #54: every `%vN` reference in the IR must have a
+    // matching `%vN = ...` definition. With the bug present the addressof
+    // result was named `%v1` but never defined; this catches that and any
+    // future regression that re-introduces a dangling SSA reference.
+    assert_no_undefined_temporaries(&ir);
+
+    let legacy = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect("legacy addressof export succeeds");
+    assert!(
+        legacy.contains("@__shared_mem_20 = addrspace(3) global i32 undef"),
+        "NVVM shared globals must be uninitialized:\n{legacy}"
+    );
+    assert!(
+        legacy.contains("bitcast i32 addrspace(3)* @__shared_mem_20 to i8 addrspace(3)*"),
+        "legacy addressof must normalize the global pointer:\n{legacy}"
+    );
+    assert!(
+        legacy.contains("bitcast i8 addrspace(3)*") && legacy.contains("to i32 addrspace(3)*"),
+        "legacy GEP must repair its canonical base pointer:\n{legacy}"
+    );
+    assert_no_undefined_temporaries(&legacy);
+}
diff --git a/crates/llvm-export/tests/export_test/common.rs b/crates/llvm-export/tests/export_test/common.rs
new file mode 100644
index 0000000000..40583f911b
--- /dev/null
+++ b/crates/llvm-export/tests/export_test/common.rs
@@ -0,0 +1,132 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use combine::stream::position::SourcePosition;
+use llvm_export::export::{DebugKind, ExportBackendConfig};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::ops::ModuleOp,
+    context::{Context, Ptr},
+    linked_list::ContainsLinkedList,
+    location::{Location, Source},
+    op::Op,
+};
+use std::path::PathBuf;
+
+pub(super) struct DebugConfig<C> {
+    pub(super) inner: C,
+    pub(super) debug_kind: DebugKind,
+}
+
+impl<C: ExportBackendConfig> ExportBackendConfig for DebugConfig<C> {
+    fn datalayout(&self) -> &str {
+        self.inner.datalayout()
+    }
+
+    fn emit_llvm_used(&self) -> bool {
+        self.inner.emit_llvm_used()
+    }
+
+    fn emit_nvvmir_version(&self) -> bool {
+        self.inner.emit_nvvmir_version()
+    }
+
+    fn nvvmir_version(&self) -> [i32; 4] {
+        self.inner.nvvmir_version()
+    }
+
+    fn emit_all_kernel_annotations(&self) -> bool {
+        self.inner.emit_all_kernel_annotations()
+    }
+
+    fn emit_ptx_kernel_keyword(&self) -> bool {
+        self.inner.emit_ptx_kernel_keyword()
+    }
+
+    fn nvvm_ir_dialect(&self) -> Option<llvm_export::export::NvvmIrDialect> {
+        self.inner.nvvm_ir_dialect()
+    }
+
+    fn debug_kind(&self) -> DebugKind {
+        self.debug_kind
+    }
+}
+
+pub(super) fn src_location(ctx: &mut Context, file: &str, line: i32, column: i32) -> Location {
+    Location::SrcPos {
+        src: Source::new_from_file(ctx, PathBuf::from(file)),
+        pos: SourcePosition { line, column },
+    }
+}
+
+pub(super) fn module_top_block(ctx: &mut Context, module: &ModuleOp) -> Ptr<BasicBlock> {
+    let module_region = module.get_operation().deref(ctx).get_region(0);
+    {
+        let region = module_region.deref(ctx);
+        if let Some(block) = region.iter(ctx).next() {
+            return block;
+        }
+    }
+
+    let block = BasicBlock::new(ctx, None, vec![]);
+    block.insert_at_back(module_region, ctx);
+    block
+}
+
+pub(super) fn metadata_id<'a>(ir: &'a str, needle: &str) -> &'a str {
+    ir.lines()
+        .find(|line| line.contains(needle))
+        .and_then(|line| line.split_once(" = ").map(|(id, _)| id))
+        .unwrap_or_else(|| panic!("missing metadata node containing {needle:?}:\n{ir}"))
+}
+
+/// Scans the textual LLVM IR and asserts that every `%vN` token appearing in
+/// an operand position has a corresponding `%vN = ...` definition somewhere
+/// in the module. Operates on `%v` temporaries only because that's the
+/// exporter's naming scheme; named values like `%entry` (block labels) are
+/// ignored by construction.
+pub(super) fn assert_no_undefined_temporaries(ir: &str) {
+    use std::collections::HashSet;
+
+    let mut defined: HashSet<String> = HashSet::new();
+    for line in ir.lines() {
+        let trimmed = line.trim_start();
+        if !trimmed.starts_with("%v") {
+            continue;
+        }
+        let Some((lhs, _)) = trimmed.split_once('=') else {
+            continue;
+        };
+        defined.insert(lhs.trim().to_string());
+    }
+
+    let mut referenced: HashSet<String> = HashSet::new();
+    for line in ir.lines() {
+        let trimmed = line.trim_start();
+        // Skip the lhs of a definition; only operand positions can be stale.
+        let body = if trimmed.starts_with("%v")
+            && let Some(eq) = trimmed.find('=')
+        {
+            &trimmed[eq + 1..]
+        } else {
+            trimmed
+        };
+        for tok in body.split(|c: char| !c.is_alphanumeric() && c != '%' && c != '_') {
+            if let Some(num) = tok.strip_prefix("%v")
+                && !num.is_empty()
+                && num.chars().all(|c| c.is_ascii_digit())
+            {
+                referenced.insert(format!("%v{num}"));
+            }
+        }
+    }
+
+    let mut undefined: Vec<&String> = referenced.difference(&defined).collect();
+    undefined.sort();
+    assert!(
+        undefined.is_empty(),
+        "IR references undefined SSA temporaries: {undefined:?}\nIR:\n{ir}"
+    );
+}
diff --git a/crates/llvm-export/tests/export_test/control_flow.rs b/crates/llvm-export/tests/export_test/control_flow.rs
new file mode 100644
index 0000000000..ceb24956ce
--- /dev/null
+++ b/crates/llvm-export/tests/export_test/control_flow.rs
@@ -0,0 +1,234 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use llvm_export::{
+    export::{NvvmExportConfig, NvvmIrDialect, export_module_to_string_with_config},
+    ops::{BrOp, CondBrOp, ConstantOp, FuncOp, ReturnOp, UndefOp},
+    types::{FuncType, VoidType},
+};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::{
+        attributes::IntegerAttr,
+        ops::ModuleOp,
+        types::{IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::Context,
+    op::Op,
+    utils::apint::APInt,
+};
+use std::num::NonZero;
+
+use crate::common::module_top_block;
+
+#[test]
+fn exporter_rejects_extra_predecessor_values_before_emitting_phis() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "invalid_branch_arity".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "invalid_branch".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let region = func.get_operation().deref(&ctx).get_region(0);
+    let destination = BasicBlock::new(&mut ctx, None, vec![]);
+    destination.insert_at_back(region, &ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
+    let one = ConstantOp::new(&mut ctx, one_attr.into());
+    let one_value = one.get_operation().deref(&ctx).get_result(0);
+    one.get_operation().insert_at_back(entry, &ctx);
+    BrOp::new(&mut ctx, destination, vec![one_value])
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(destination, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let error = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("extra predecessor values must be rejected");
+    assert!(
+        error.contains("supplies 1 values") && error.contains("expects 0 block arguments"),
+        "{error}"
+    );
+}
+
+#[test]
+fn exporter_rejects_distinct_values_on_duplicate_conditional_edges() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "duplicate_conditional_edge".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let func_ty = FuncType::get(
+        &ctx,
+        i32_ty.into(),
+        vec![i1_ty.into(), i32_ty.into(), i32_ty.into()],
+        false,
+    );
+    let func = FuncOp::new(&mut ctx, "duplicate_edge".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let condition = entry.deref(&ctx).get_argument(0);
+    let if_true = entry.deref(&ctx).get_argument(1);
+    let if_false = entry.deref(&ctx).get_argument(2);
+    let region = func.get_operation().deref(&ctx).get_region(0);
+    let destination = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    destination.insert_at_back(region, &ctx);
+    CondBrOp::new(
+        &mut ctx,
+        condition,
+        destination,
+        vec![if_true],
+        destination,
+        vec![if_false],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    let result = destination.deref(&ctx).get_argument(0);
+    ReturnOp::new(&mut ctx, Some(result))
+        .get_operation()
+        .insert_at_back(destination, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    module
+        .get_operation()
+        .deref(&ctx)
+        .verify(&ctx)
+        .expect("pliron permits same-destination conditional edges with distinct values");
+    let error = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("LLVM PHIs cannot distinguish duplicate predecessor edges");
+    assert!(
+        error.contains("both edges with different forwarded values"),
+        "{error}"
+    );
+}
+
+#[test]
+fn exporter_deduplicates_identical_values_on_duplicate_conditional_edges() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "identical_conditional_edge".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let func_ty = FuncType::get(
+        &ctx,
+        i32_ty.into(),
+        vec![i1_ty.into(), i32_ty.into()],
+        false,
+    );
+    let func = FuncOp::new(&mut ctx, "identical_edge".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let condition = entry.deref(&ctx).get_argument(0);
+    let value = entry.deref(&ctx).get_argument(1);
+    let region = func.get_operation().deref(&ctx).get_region(0);
+    let destination = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    destination.insert_at_back(region, &ctx);
+    CondBrOp::new(
+        &mut ctx,
+        condition,
+        destination,
+        vec![value],
+        destination,
+        vec![value],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    let result = destination.deref(&ctx).get_argument(0);
+    ReturnOp::new(&mut ctx, Some(result))
+        .get_operation()
+        .insert_at_back(destination, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect("identical duplicate-edge values can use one PHI predecessor");
+    let phi = ir
+        .lines()
+        .find(|line| line.contains(" = phi i32 "))
+        .expect("destination block must contain a PHI");
+    assert_eq!(phi.matches("%entry").count(), 1, "{phi}");
+}
+
+#[test]
+fn phi_can_reference_undef_from_a_later_block() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "later_undef_phi".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let func_ty = FuncType::get(
+        &ctx,
+        i32_ty.into(),
+        vec![i1_ty.into(), i32_ty.into()],
+        false,
+    );
+    let func = FuncOp::new(&mut ctx, "choose_undef".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let condition = entry.deref(&ctx).get_argument(0);
+    let fallback = entry.deref(&ctx).get_argument(1);
+    let region = func.get_operation().deref(&ctx).get_region(0);
+
+    // The join precedes both predecessors in print order, so its PHI depends
+    // on the exporter's whole-function value-name pre-pass.
+    let join = BasicBlock::new(&mut ctx, None, vec![i32_ty.into()]);
+    join.insert_at_back(region, &ctx);
+    let undef_block = BasicBlock::new(&mut ctx, None, vec![]);
+    undef_block.insert_at_back(region, &ctx);
+    let value_block = BasicBlock::new(&mut ctx, None, vec![]);
+    value_block.insert_at_back(region, &ctx);
+
+    CondBrOp::new(
+        &mut ctx,
+        condition,
+        undef_block,
+        vec![],
+        value_block,
+        vec![],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+
+    let undef = UndefOp::new(&mut ctx, i32_ty.into());
+    let undef_value = undef.get_operation().deref(&ctx).get_result(0);
+    undef.get_operation().insert_at_back(undef_block, &ctx);
+    BrOp::new(&mut ctx, join, vec![undef_value])
+        .get_operation()
+        .insert_at_back(undef_block, &ctx);
+    BrOp::new(&mut ctx, join, vec![fallback])
+        .get_operation()
+        .insert_at_back(value_block, &ctx);
+
+    let result = join.deref(&ctx).get_argument(0);
+    ReturnOp::new(&mut ctx, Some(result))
+        .get_operation()
+        .insert_at_back(join, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect("later-block undef must be available while exporting an earlier PHI");
+    assert!(
+        ir.lines()
+            .any(|line| line.contains(" = phi i32 ") && line.contains("[ undef,")),
+        "{ir}"
+    );
+}
diff --git a/crates/llvm-export/tests/export_test/debug_info.rs b/crates/llvm-export/tests/export_test/debug_info.rs
new file mode 100644
index 0000000000..6b941ff8c7
--- /dev/null
+++ b/crates/llvm-export/tests/export_test/debug_info.rs
@@ -0,0 +1,2458 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use llvm_export::{
+    export::{
+        DebugKind, NvvmExportConfig, NvvmIrDialect, PtxExportConfig,
+        export_module_to_string_with_config,
+    },
+    ops::{
+        AllocaOp, CallOp, ConstantOp, DebugEnumDiscriminant, DebugEnumVariant, DebugFragment,
+        DebugFragmentVariableInfo, DebugGlobalVariableInfo, DebugLocalTypeKind,
+        DebugLocalVariableInfo, DebugProjectedVariableInfo, DebugSourcePosition, DebugSourceScope,
+        DebugSourceScopeLocation, DebugSourceScopeMap, DebugValueExpression,
+        DebugValueExpressionOp, DebugValueListOp, DebugValueOp, FuncOp,
+        GlobalInitializerRelocation, GlobalOp, GlobalOpExt, ReturnOp,
+        encode_global_initializer_relocations,
+    },
+    types::{ArrayType, FuncType, PointerType, StructLayout, StructType, VoidType},
+};
+use pliron::{
+    builtin::{
+        attributes::IntegerAttr,
+        op_interfaces::CallOpCallable,
+        ops::ModuleOp,
+        types::{IntegerType, Signedness},
+    },
+    context::Context,
+    linked_list::ContainsLinkedList,
+    location::{Located, Location},
+    op::Op,
+    utils::apint::APInt,
+};
+use std::{num::NonZero, path::PathBuf};
+
+use crate::common::{DebugConfig, metadata_id, module_top_block, src_location};
+
+#[test]
+fn legacy_export_rejects_debug_metadata() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "legacy_debug".try_into().unwrap());
+    let config = DebugConfig {
+        inner: NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+        debug_kind: DebugKind::LineTables,
+    };
+
+    let error = export_module_to_string_with_config(&ctx, &module, &config)
+        .expect_err("legacy debug output must be rejected");
+    assert!(error.contains("legacy LLVM 7"), "{error}");
+    assert!(error.contains("debug"), "{error}");
+}
+
+#[test]
+fn line_table_debug_metadata_emits_function_scope_and_instruction_locations() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
+    llvm_export::ops::set_debug_function_name(
+        &mut ctx,
+        func.get_operation(),
+        "source_crate::debug_kernel",
+    );
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 7, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let ret = ReturnOp::new(&mut ctx, None);
+    let ret_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 8, 5);
+    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
+    ret.get_operation().insert_at_back(entry, &ctx);
+
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::LineTables,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    let define_line = ir
+        .lines()
+        .find(|line| line.starts_with("define "))
+        .expect("function definition");
+    assert!(
+        define_line.contains("!dbg !"),
+        "function definition should reference its DISubprogram:\n{ir}"
+    );
+
+    let ret_line = ir
+        .lines()
+        .find(|line| line.trim_start().starts_with("ret void"))
+        .expect("return instruction");
+    assert!(
+        ret_line.contains(", !dbg !"),
+        "real instructions should carry DILocation attachments:\n{ir}"
+    );
+
+    assert!(
+        ir.contains("!llvm.dbg.cu = !{!"),
+        "module should reference a compile unit:\n{ir}"
+    );
+    assert!(
+        ir.contains("!llvm.module.flags = !{!"),
+        "module should declare debug-info flags:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DIFile(filename: \"kernel.rs\", directory: \"/tmp/cuda-oxide/tests\")"),
+        "source path should be split into DIFile filename and directory:\n{ir}"
+    );
+    assert!(
+        ir.contains("distinct !DICompileUnit(language: DW_LANG_Rust"),
+        "debug export should describe the Rust compile unit:\n{ir}"
+    );
+    assert!(
+        ir.contains(
+            "distinct !DISubprogram(name: \"source_crate::debug_kernel\", linkageName: \"debug_kernel\""
+        ),
+        "function definition should separate its source name from its physical linkage name:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocation(line: 8, column: 5, scope: !"),
+        "instruction location should preserve the source line and column:\n{ir}"
+    );
+}
+
+#[test]
+fn full_debug_metadata_keeps_generic_source_name_separate_from_mangled_symbol() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let linkage_name = "_RNvMCexampleINtCsource7WrapperjE7get_mut";
+    let func = FuncOp::new(&mut ctx, linkage_name.try_into().unwrap(), func_ty);
+    llvm_export::ops::set_debug_function_name(
+        &mut ctx,
+        func.get_operation(),
+        "source_crate::Wrapper::<u16>::get_mut",
+    );
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/generic.rs", 19, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::Full,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    assert!(
+        ir.contains(&format!("define void @{linkage_name}()")),
+        "debug naming must not change the physical function symbol:\n{ir}"
+    );
+    assert!(
+        ir.contains(&format!(
+            "distinct !DISubprogram(name: \"source_crate::Wrapper::<u16>::get_mut\", linkageName: \"{linkage_name}\""
+        )),
+        "generic debug metadata must carry both source and linkage spellings:\n{ir}"
+    );
+}
+
+#[test]
+fn line_table_debug_metadata_uses_file_scope_for_cross_file_locations() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 38, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let ret = ReturnOp::new(&mut ctx, None);
+    let ret_loc = src_location(
+        &mut ctx,
+        "/tmp/cuda-oxide/crates/cuda-device/src/thread.rs",
+        292,
+        19,
+    );
+    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
+    ret.get_operation().insert_at_back(entry, &ctx);
+
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::LineTables,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    let ret_line = ir
+        .lines()
+        .find(|line| line.trim_start().starts_with("ret void"))
+        .expect("return instruction");
+    assert!(
+        ret_line.contains(", !dbg !"),
+        "cross-file instructions should keep source locations:\n{ir}"
+    );
+    assert!(
+        ir.contains(
+            "!DIFile(filename: \"thread.rs\", directory: \"/tmp/cuda-oxide/crates/cuda-device/src\")"
+        ),
+        "cross-file locations should get their own DIFile:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILexicalBlockFile(scope: !"),
+        "cross-file locations should use a file-specific debug scope:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocation(line: 292, column: 19, scope: !"),
+        "cross-file locations should preserve their real source line:\n{ir}"
+    );
+}
+
+#[test]
+fn line_table_debug_metadata_emits_inlined_at_for_callsite_locations() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 38, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let ret = ReturnOp::new(&mut ctx, None);
+    let callee = src_location(
+        &mut ctx,
+        "/tmp/cuda-oxide/crates/cuda-device/src/thread.rs",
+        292,
+        19,
+    );
+    let caller = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 39, 13);
+    ret.get_operation()
+        .deref_mut(&ctx)
+        .set_loc(Location::CallSite {
+            callee: Box::new(callee),
+            caller: Box::new(caller),
+        });
+    ret.get_operation().insert_at_back(entry, &ctx);
+
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::LineTables,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    assert!(
+        ir.contains("!DILocation(line: 39, column: 13, scope: !"),
+        "callsite metadata should preserve the caller location:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocation(line: 292, column: 19, scope: !") && ir.contains(", inlinedAt: !"),
+        "callsite metadata should describe the callee location as inlined at the caller:\n{ir}"
+    );
+}
+
+#[test]
+fn debug_locations_use_rustc_source_scope_positions() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 10, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+    llvm_export::ops::set_debug_source_scope_map(
+        &mut ctx,
+        func.get_operation(),
+        &DebugSourceScopeMap {
+            scopes: vec![
+                DebugSourceScope {
+                    id: 0,
+                    parent: None,
+                    span: Some(DebugSourcePosition {
+                        file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
+                        line: 10,
+                        column: 1,
+                    }),
+                    inlined: None,
+                },
+                DebugSourceScope {
+                    id: 1,
+                    parent: Some(0),
+                    span: Some(DebugSourcePosition {
+                        file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
+                        line: 12,
+                        column: 9,
+                    }),
+                    inlined: None,
+                },
+            ],
+            locations: vec![DebugSourceScopeLocation {
+                pos: DebugSourcePosition {
+                    file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
+                    line: 12,
+                    column: 9,
+                },
+                scope: 1,
+            }],
+        },
+    );
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let ret = ReturnOp::new(&mut ctx, None);
+    let ret_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 12, 9);
+    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
+    ret.get_operation().insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::LineTables,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    let block_id = ir
+        .lines()
+        .find_map(|line| {
+            if line.contains("!DILexicalBlock(scope: !") && line.contains("line: 12, column: 9") {
+                line.split_once(" = ")
+                    .map(|(id, _)| id.trim_start_matches('!').to_string())
+            } else {
+                None
+            }
+        })
+        .expect("nested lexical block should be emitted");
+
+    assert!(
+        ir.contains(&format!(
+            "!DILocation(line: 12, column: 9, scope: !{block_id})"
+        )),
+        "instruction location should use the exact rustc source scope, not the function scope:\n{ir}"
+    );
+}
+
+#[test]
+fn full_debug_metadata_emits_dbg_declare_for_tagged_allocas() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 30, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
+    let one = ConstantOp::new(&mut ctx, one_attr.into());
+    one.get_operation().insert_at_back(entry, &ctx);
+    let one_val = one.get_operation().deref(&ctx).get_result(0);
+
+    let tid = AllocaOp::new(&mut ctx, i32_ty.into(), one_val);
+    let tid_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 31, 9);
+    tid.get_operation().deref_mut(&ctx).set_loc(tid_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        tid.get_operation(),
+        DebugLocalVariableInfo {
+            name: "tid".to_string(),
+            argument_index: Some(1),
+            ty: DebugLocalTypeKind::Basic {
+                name: "u32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_unsigned",
+            },
+        },
+    );
+    tid.get_operation().insert_at_back(entry, &ctx);
+
+    let ptr_ty = PointerType::get(&ctx, 0);
+    let ptr = AllocaOp::new(&mut ctx, ptr_ty.into(), one_val);
+    let ptr_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 32, 9);
+    ptr.get_operation().deref_mut(&ctx).set_loc(ptr_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        ptr.get_operation(),
+        DebugLocalVariableInfo {
+            name: "ptr".to_string(),
+            argument_index: None,
+            ty: DebugLocalTypeKind::TypedPointer {
+                name: "*mut f32".to_string(),
+                size_bits: 64,
+                pointee: Box::new(DebugLocalTypeKind::Basic {
+                    name: "f32".to_string(),
+                    size_bits: 32,
+                    encoding: "DW_ATE_float",
+                }),
+            },
+        },
+    );
+    ptr.get_operation().insert_at_back(entry, &ctx);
+
+    let nested_ptr = AllocaOp::new(&mut ctx, ptr_ty.into(), one_val);
+    let nested_ptr_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 33, 9);
+    nested_ptr
+        .get_operation()
+        .deref_mut(&ctx)
+        .set_loc(nested_ptr_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        nested_ptr.get_operation(),
+        DebugLocalVariableInfo {
+            name: "nested_ptr".to_string(),
+            argument_index: None,
+            ty: DebugLocalTypeKind::TypedPointer {
+                name: "*const *mut i32".to_string(),
+                size_bits: 64,
+                pointee: Box::new(DebugLocalTypeKind::TypedPointer {
+                    name: "*mut i32".to_string(),
+                    size_bits: 64,
+                    pointee: Box::new(DebugLocalTypeKind::Basic {
+                        name: "i32".to_string(),
+                        size_bits: 32,
+                        encoding: "DW_ATE_signed",
+                    }),
+                }),
+            },
+        },
+    );
+    nested_ptr.get_operation().insert_at_back(entry, &ctx);
+
+    let array_ptr = AllocaOp::new(&mut ctx, ptr_ty.into(), one_val);
+    let array_ptr_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 34, 9);
+    array_ptr
+        .get_operation()
+        .deref_mut(&ctx)
+        .set_loc(array_ptr_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        array_ptr.get_operation(),
+        DebugLocalVariableInfo {
+            name: "array_ptr".to_string(),
+            argument_index: None,
+            ty: DebugLocalTypeKind::TypedPointer {
+                name: "*const [u16; 4]".to_string(),
+                size_bits: 64,
+                pointee: Box::new(DebugLocalTypeKind::Array {
+                    name: "[u16; 4]".to_string(),
+                    size_bits: 64,
+                    element: Box::new(DebugLocalTypeKind::Basic {
+                        name: "u16".to_string(),
+                        size_bits: 16,
+                        encoding: "DW_ATE_unsigned",
+                    }),
+                    count: 4,
+                }),
+            },
+        },
+    );
+    array_ptr.get_operation().insert_at_back(entry, &ctx);
+
+    let opaque_ptr = AllocaOp::new(&mut ctx, ptr_ty.into(), one_val);
+    let opaque_ptr_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 35, 9);
+    opaque_ptr
+        .get_operation()
+        .deref_mut(&ctx)
+        .set_loc(opaque_ptr_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        opaque_ptr.get_operation(),
+        DebugLocalVariableInfo {
+            name: "opaque_ptr".to_string(),
+            argument_index: None,
+            ty: DebugLocalTypeKind::Pointer {
+                name: "*const _".to_string(),
+                size_bits: 64,
+            },
+        },
+    );
+    opaque_ptr.get_operation().insert_at_back(entry, &ctx);
+
+    let ret = ReturnOp::new(&mut ctx, None);
+    let ret_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 36, 1);
+    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
+    ret.get_operation().insert_at_back(entry, &ctx);
+
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::Full,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    assert!(
+        ir.contains("emissionKind: FullDebug"),
+        "full debug should request full DWARF metadata:\n{ir}"
+    );
+    assert!(
+        ir.contains("isOptimized: false"),
+        "full debug export should describe the unoptimized debug path:\n{ir}"
+    );
+    assert!(
+        ir.contains("declare void @llvm.dbg.declare(metadata, metadata, metadata)"),
+        "full debug should declare the debug intrinsic it calls:\n{ir}"
+    );
+    assert!(
+        ir.contains("call void @llvm.dbg.declare(metadata ptr %"),
+        "tagged allocas should be bound to variables with dbg.declare:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocalVariable(name: \"tid\", arg: 1, scope: !"),
+        "argument debug metadata should preserve the argument number:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocalVariable(name: \"ptr\", scope: !"),
+        "local debug metadata should omit the arg field:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DIBasicType(name: \"u32\", size: 32, encoding: DW_ATE_unsigned)"),
+        "basic integer variables should get DIBasicType metadata:\n{ir}"
+    );
+    let f32_id = metadata_id(
+        &ir,
+        "!DIBasicType(name: \"f32\", size: 32, encoding: DW_ATE_float)",
+    );
+    assert!(
+        ir.contains(&format!(
+            "!DIDerivedType(tag: DW_TAG_pointer_type, name: \"*mut f32\", baseType: {f32_id}, size: 64)"
+        )),
+        "pointer variables should reference their pointee DIType:\n{ir}"
+    );
+    let i32_id = metadata_id(
+        &ir,
+        "!DIBasicType(name: \"i32\", size: 32, encoding: DW_ATE_signed)",
+    );
+    let inner_pointer = format!(
+        "!DIDerivedType(tag: DW_TAG_pointer_type, name: \"*mut i32\", baseType: {i32_id}, size: 64)"
+    );
+    let inner_pointer_id = metadata_id(&ir, &inner_pointer);
+    assert!(
+        ir.contains(&format!(
+            "!DIDerivedType(tag: DW_TAG_pointer_type, name: \"*const *mut i32\", baseType: {inner_pointer_id}, size: 64)"
+        )),
+        "nested pointer metadata must preserve the complete base-type chain:\n{ir}"
+    );
+
+    let u16_id = metadata_id(
+        &ir,
+        "!DIBasicType(name: \"u16\", size: 16, encoding: DW_ATE_unsigned)",
+    );
+    let subrange_id = metadata_id(&ir, "!DISubrange(count: 4)");
+    let subrange_tuple_id = metadata_id(&ir, &format!("!{{{subrange_id}}}"));
+    let array_type = format!(
+        "!DICompositeType(tag: DW_TAG_array_type, baseType: {u16_id}, size: 64, elements: {subrange_tuple_id})"
+    );
+    let array_type_id = metadata_id(&ir, &array_type);
+    assert!(
+        ir.contains(&format!(
+            "!DIDerivedType(tag: DW_TAG_pointer_type, name: \"*const [u16; 4]\", baseType: {array_type_id}, size: 64)"
+        )),
+        "array pointer metadata must reference the exact element/subrange graph:\n{ir}"
+    );
+
+    assert!(
+        ir.contains("!DILocalVariable(name: \"opaque_ptr\", scope: !"),
+        "unsupported pointers must remain visible as source variables:\n{ir}"
+    );
+    assert!(
+        ir.contains(
+            "!DIDerivedType(tag: DW_TAG_pointer_type, name: \"*const _\", baseType: null, size: 64)"
+        ),
+        "the compatibility pointer must retain its legacy null-base metadata:\n{ir}"
+    );
+    let null_base_pointer_count = ir
+        .lines()
+        .filter(|line| line.contains("DW_TAG_pointer_type") && line.contains("baseType: null"))
+        .count();
+    assert!(
+        null_base_pointer_count == 1,
+        "only the explicit opaque compatibility pointer may have a null baseType:\n{ir}"
+    );
+
+    let Some(llvm_as) = ["llvm-as-22", "llvm-as-21", "llvm-as"]
+        .into_iter()
+        .find(|tool| {
+            std::process::Command::new(tool)
+                .arg("--version")
+                .output()
+                .is_ok_and(|out| out.status.success())
+        })
+    else {
+        eprintln!("skipping pointer-debug llvm-as parse gate: no supported llvm-as on PATH");
+        return;
+    };
+    let ll_path = std::env::temp_dir().join(format!(
+        "cuda_oxide_pointer_debug_parse_gate_{}.ll",
+        std::process::id()
+    ));
+    std::fs::write(&ll_path, &ir).expect("write pointer-debug temp .ll");
+    let output = std::process::Command::new(llvm_as)
+        .arg("-o")
+        .arg("/dev/null")
+        .arg(&ll_path)
+        .output()
+        .expect("run llvm-as for pointer debug metadata");
+    let stderr = String::from_utf8_lossy(&output.stderr).into_owned();
+    let _ = std::fs::remove_file(&ll_path);
+    assert!(
+        output.status.success(),
+        "{llvm_as} rejected pointer debug metadata:\n{stderr}\n--- module ---\n{ir}"
+    );
+}
+
+#[test]
+fn full_debug_metadata_describes_as1_global_with_semantic_rust_type() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let storage_ty = ArrayType::get(&ctx, i8_ty.into(), 8);
+    let global = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "__device_global_7".try_into().unwrap(),
+        storage_ty.into(),
+        8,
+    );
+    global.set_address_space(&mut ctx, llvm_export::types::address_space::GLOBAL);
+    global.set_initializer_hex(&mut ctx, "0000000000000000");
+    llvm_export::ops::set_debug_global_variable(
+        &mut ctx,
+        global.get_operation(),
+        &DebugGlobalVariableInfo {
+            name: "GLOBAL_COUNTER".to_string(),
+            namespace: vec!["debuginfo".to_string(), "state".to_string()],
+            ty: DebugLocalTypeKind::Basic {
+                name: "u64".to_string(),
+                size_bits: 64,
+                encoding: "DW_ATE_unsigned",
+            },
+            declaration: DebugSourcePosition {
+                file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
+                line: 90,
+                column: 1,
+            },
+            is_local_to_unit: true,
+            is_function_local: false,
+        },
+    );
+    global.get_operation().insert_at_back(module_block, &ctx);
+
+    let full = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &DebugConfig {
+            inner: PtxExportConfig,
+            debug_kind: DebugKind::Full,
+        },
+    )
+    .expect("full debug export succeeds");
+
+    let definition = full
+        .lines()
+        .find(|line| line.starts_with("@__device_global_7 = "))
+        .expect("device-global definition");
+    assert!(
+        definition.contains("addrspace(1) global [8 x i8] c\"\\00\\00\\00\\00\\00\\00\\00\\00\"")
+            && definition.contains(", align 8, !dbg !"),
+        "the physical byte storage should retain a global debug attachment:\n{full}"
+    );
+    assert!(
+        full.contains(
+            "distinct !DIGlobalVariable(name: \"GLOBAL_COUNTER\", linkageName: \"__device_global_7\""
+        ),
+        "DWARF should separate the source name from the generated linkage name:\n{full}"
+    );
+    assert!(
+        full.contains("!DINamespace(name: \"debuginfo\", scope: null)")
+            && full.contains("!DINamespace(name: \"state\", scope: !")
+            && full.contains("scope: !"),
+        "the source crate/module hierarchy should scope the leaf name:\n{full}"
+    );
+    assert!(
+        full.contains("isLocal: true, isDefinition: true"),
+        "private Rust statics should remain local to the compile unit:\n{full}"
+    );
+    assert!(
+        full.contains("file: !")
+            && full.contains("line: 90, type: !")
+            && full.contains("align: 64)"),
+        "the declaration location and source alignment should be retained:\n{full}"
+    );
+    assert!(
+        full.contains("!DIBasicType(name: \"u64\", size: 64, encoding: DW_ATE_unsigned)"),
+        "the debug type must be semantic u64, not the physical [8 x i8] storage:\n{full}"
+    );
+    assert!(
+        full.contains("!DIGlobalVariableExpression(var: !")
+            && full.contains("expr: !DIExpression())")
+            && full.contains("emissionKind: FullDebug, globals: !"),
+        "the global expression should be retained by the compile unit:\n{full}"
+    );
+
+    let off = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &DebugConfig {
+            inner: PtxExportConfig,
+            debug_kind: DebugKind::Off,
+        },
+    )
+    .expect("non-debug export succeeds");
+    let line_tables = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &DebugConfig {
+            inner: PtxExportConfig,
+            debug_kind: DebugKind::LineTables,
+        },
+    )
+    .expect("line-table export succeeds");
+    assert_eq!(
+        line_tables, off,
+        "a global-only module must not gain variable metadata outside full debug"
+    );
+}
+
+#[test]
+fn full_debug_metadata_describes_function_local_as3_array_with_shared_address_class() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "shared_debug".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let raw_owner = reserved_oxide_symbols::device_symbol("shared_kernel");
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let storage_ty = ArrayType::get(&ctx, i32_ty.into(), 32);
+    let global = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "__shared_mem_0".try_into().unwrap(),
+        storage_ty.into(),
+        4,
+    );
+    global.set_address_space(&mut ctx, llvm_export::types::address_space::SHARED);
+    let info = DebugGlobalVariableInfo {
+        name: "TILE".to_string(),
+        namespace: vec![
+            "debuginfo".to_string(),
+            "kernels".to_string(),
+            "shared_kernel".to_string(),
+        ],
+        ty: DebugLocalTypeKind::Array {
+            name: "[i32; 32]".to_string(),
+            size_bits: 1024,
+            element: Box::new(DebugLocalTypeKind::Basic {
+                name: "i32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_signed",
+            }),
+            count: 32,
+        },
+        declaration: DebugSourcePosition {
+            file: PathBuf::from("/tmp/cuda-oxide/tests/shared.rs"),
+            line: 40,
+            column: 9,
+        },
+        is_local_to_unit: true,
+        is_function_local: true,
+    };
+    llvm_export::ops::set_debug_global_variable(&mut ctx, global.get_operation(), &info);
+    llvm_export::ops::set_debug_global_owner_function(&mut ctx, global.get_operation(), &raw_owner);
+    global.get_operation().insert_at_back(module_block, &ctx);
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let function = FuncOp::new(&mut ctx, raw_owner.as_str().try_into().unwrap(), func_ty);
+    let function_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/shared.rs", 35, 1);
+    function
+        .get_operation()
+        .deref_mut(&ctx)
+        .set_loc(function_loc);
+    let entry = function.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    function.get_operation().insert_at_back(module_block, &ctx);
+
+    let full = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &DebugConfig {
+            inner: PtxExportConfig,
+            debug_kind: DebugKind::Full,
+        },
+    )
+    .expect("full shared debug export succeeds");
+
+    let definition = full
+        .lines()
+        .find(|line| line.starts_with("@__shared_mem_0 = "))
+        .expect("shared definition");
+    assert!(
+        definition.contains("addrspace(3) global [32 x i32]")
+            && definition.contains(", align 4, !dbg !"),
+        "physical AS3 array must retain the debug attachment:\n{full}"
+    );
+    assert!(
+        full.contains("!DIExpression(DW_OP_constu, 8, DW_OP_swap, DW_OP_xderef)"),
+        "AS3 must carry CUDA DWARF shared address class 8:\n{full}"
+    );
+    assert!(
+        full.contains("!DINamespace(name: \"debuginfo\", scope: null)")
+            && full.contains("!DINamespace(name: \"kernels\", scope: !")
+            && full.contains(
+                "distinct !DISubprogram(name: \"shared_kernel\", \
+                 linkageName: \"shared_kernel\", scope: !"
+            ),
+        "the owning subprogram must be nested under the structured namespace:\n{full}"
+    );
+    assert_eq!(
+        full.matches("distinct !DISubprogram(name: \"shared_kernel\"")
+            .count(),
+        1,
+        "pre-reservation and function export must reuse one DISubprogram:\n{full}"
+    );
+    assert!(
+        full.contains("distinct !DIGlobalVariable(name: \"TILE\", linkageName: \"__shared_mem_0\"")
+            && full.contains("!DISubrange(count: 32)")
+            && full.contains("!DICompositeType(tag: DW_TAG_array_type, baseType: !")
+            && full.contains("size: 1024, elements: !"),
+        "the DIE must keep leaf/linkage and the logical array type:\n{full}"
+    );
+    assert!(
+        full.contains("emissionKind: FullDebug, globals: !"),
+        "the CU must retain the one shared expression:\n{full}"
+    );
+}
+
+fn export_mixed_shared_owner_order(malformed_first: bool) -> String {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "shared_owner_validation".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let raw_owner = reserved_oxide_symbols::device_symbol("shared_kernel");
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let storage_ty = ArrayType::get(&ctx, i32_ty.into(), 4);
+
+    let valid = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "__shared_mem_valid".try_into().unwrap(),
+        storage_ty.into(),
+        4,
+    );
+    valid.set_address_space(&mut ctx, llvm_export::types::address_space::SHARED);
+    llvm_export::ops::set_debug_global_variable(
+        &mut ctx,
+        valid.get_operation(),
+        &DebugGlobalVariableInfo {
+            name: "VALID".to_string(),
+            namespace: vec!["owner_fixture".to_string(), "shared_kernel".to_string()],
+            ty: DebugLocalTypeKind::Array {
+                name: "[i32; 4]".to_string(),
+                size_bits: 128,
+                element: Box::new(DebugLocalTypeKind::Basic {
+                    name: "i32".to_string(),
+                    size_bits: 32,
+                    encoding: "DW_ATE_signed",
+                }),
+                count: 4,
+            },
+            declaration: DebugSourcePosition {
+                file: PathBuf::from("/tmp/cuda-oxide/tests/shared-owner.rs"),
+                line: 20,
+                column: 5,
+            },
+            is_local_to_unit: true,
+            is_function_local: true,
+        },
+    );
+    llvm_export::ops::set_debug_global_owner_function(&mut ctx, valid.get_operation(), &raw_owner);
+
+    let malformed = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "__shared_mem_malformed".try_into().unwrap(),
+        storage_ty.into(),
+        4,
+    );
+    malformed.set_address_space(&mut ctx, llvm_export::types::address_space::SHARED);
+    llvm_export::ops::set_debug_global_variable(
+        &mut ctx,
+        malformed.get_operation(),
+        &DebugGlobalVariableInfo {
+            name: "MALFORMED".to_string(),
+            namespace: vec!["owner_fixture".to_string(), "shared_kernel".to_string()],
+            ty: DebugLocalTypeKind::Array {
+                name: "[i32; 4]".to_string(),
+                size_bits: 128,
+                element: Box::new(DebugLocalTypeKind::Basic {
+                    name: "i32".to_string(),
+                    size_bits: 32,
+                    encoding: "DW_ATE_signed",
+                }),
+                count: 4,
+            },
+            declaration: DebugSourcePosition {
+                file: PathBuf::from("/tmp/cuda-oxide/tests/shared-owner.rs"),
+                line: 24,
+                column: 5,
+            },
+            is_local_to_unit: true,
+            is_function_local: true,
+        },
+    );
+    // This raw spelling normalizes to `shared_kernel`, but it is not the raw
+    // symbol indexed for that function definition. It must not borrow the
+    // valid sibling's pre-reserved DISubprogram.
+    llvm_export::ops::set_debug_global_owner_function(
+        &mut ctx,
+        malformed.get_operation(),
+        "shared_kernel",
+    );
+
+    if malformed_first {
+        malformed.get_operation().insert_at_back(module_block, &ctx);
+        valid.get_operation().insert_at_back(module_block, &ctx);
+    } else {
+        valid.get_operation().insert_at_back(module_block, &ctx);
+        malformed.get_operation().insert_at_back(module_block, &ctx);
+    }
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let function = FuncOp::new(&mut ctx, raw_owner.as_str().try_into().unwrap(), func_ty);
+    let function_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/shared-owner.rs", 16, 1);
+    function
+        .get_operation()
+        .deref_mut(&ctx)
+        .set_loc(function_loc);
+    let entry = function.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    function.get_operation().insert_at_back(module_block, &ctx);
+
+    export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &DebugConfig {
+            inner: PtxExportConfig,
+            debug_kind: DebugKind::Full,
+        },
+    )
+    .expect("a malformed shared owner must not break its valid sibling")
+}
+
+fn assert_malformed_shared_owner_fails_closed(full: &str) {
+    let valid_definition = full
+        .lines()
+        .find(|line| line.starts_with("@__shared_mem_valid = "))
+        .expect("valid shared definition");
+    let malformed_definition = full
+        .lines()
+        .find(|line| line.starts_with("@__shared_mem_malformed = "))
+        .expect("malformed-owner shared definition");
+    assert!(
+        valid_definition.contains(", !dbg !"),
+        "the valid sibling must retain its debug attachment:\n{full}"
+    );
+    assert!(
+        !malformed_definition.contains(", !dbg !"),
+        "the malformed owner must not borrow the valid sibling's scope:\n{full}"
+    );
+    assert!(
+        full.contains("distinct !DIGlobalVariable(name: \"VALID\"")
+            && !full.contains("distinct !DIGlobalVariable(name: \"MALFORMED\""),
+        "only the valid shared source identity may become a DIE:\n{full}"
+    );
+    assert_eq!(
+        full.matches("!DIGlobalVariableExpression(var:").count(),
+        1,
+        "only the valid sibling may be retained by the compile unit:\n{full}"
+    );
+    assert_eq!(
+        full.matches("distinct !DISubprogram(name: \"shared_kernel\"")
+            .count(),
+        1,
+        "the valid owner must still reuse exactly one DISubprogram:\n{full}"
+    );
+}
+
+#[test]
+fn malformed_shared_owner_before_valid_sibling_cannot_borrow_its_scope() {
+    assert_malformed_shared_owner_fails_closed(&export_mixed_shared_owner_order(true));
+}
+
+#[test]
+fn malformed_shared_owner_after_valid_sibling_cannot_borrow_its_scope() {
+    assert_malformed_shared_owner_fails_closed(&export_mixed_shared_owner_order(false));
+}
+
+#[test]
+fn full_debug_globals_preserve_qualified_identity_visibility_and_relocations() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "global_debug_adversarial".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+
+    let left_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
+    let left = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "__device_global_20".try_into().unwrap(),
+        left_ty.into(),
+        4,
+    );
+    left.set_address_space(&mut ctx, llvm_export::types::address_space::GLOBAL);
+    left.set_initializer_hex(&mut ctx, "01000000");
+    llvm_export::ops::set_debug_global_variable(
+        &mut ctx,
+        left.get_operation(),
+        &DebugGlobalVariableInfo {
+            name: "SAME_LEAF".to_string(),
+            namespace: vec!["qualified_fixture".to_string(), "left".to_string()],
+            ty: DebugLocalTypeKind::Basic {
+                name: "u32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_unsigned",
+            },
+            declaration: DebugSourcePosition {
+                file: PathBuf::from("/tmp/cuda-oxide/tests/qualified.rs"),
+                line: 20,
+                column: 5,
+            },
+            is_local_to_unit: true,
+            is_function_local: false,
+        },
+    );
+    left.get_operation().insert_at_back(module_block, &ctx);
+
+    let right_ty = ArrayType::get(&ctx, i8_ty.into(), 8);
+    let right = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "__device_global_21".try_into().unwrap(),
+        right_ty.into(),
+        8,
+    );
+    right.set_address_space(&mut ctx, llvm_export::types::address_space::GLOBAL);
+    right.set_initializer_hex(&mut ctx, "0200000000000000");
+    llvm_export::ops::set_debug_global_variable(
+        &mut ctx,
+        right.get_operation(),
+        &DebugGlobalVariableInfo {
+            name: "SAME_LEAF".to_string(),
+            namespace: vec!["qualified_fixture".to_string(), "right".to_string()],
+            ty: DebugLocalTypeKind::Basic {
+                name: "u64".to_string(),
+                size_bits: 64,
+                encoding: "DW_ATE_unsigned",
+            },
+            declaration: DebugSourcePosition {
+                file: PathBuf::from("/tmp/cuda-oxide/tests/qualified.rs"),
+                line: 24,
+                column: 5,
+            },
+            is_local_to_unit: false,
+            is_function_local: false,
+        },
+    );
+    right.get_operation().insert_at_back(module_block, &ctx);
+
+    let target_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
+    let target = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "__device_global_22".try_into().unwrap(),
+        target_ty.into(),
+        4,
+    );
+    target.set_address_space(&mut ctx, llvm_export::types::address_space::GLOBAL);
+    target.set_source_global_key(&mut ctx, "qualified_fixture::RELOCATION_TARGET");
+    target.set_initializer_hex(&mut ctx, "78563412");
+    llvm_export::ops::set_debug_global_variable(
+        &mut ctx,
+        target.get_operation(),
+        &DebugGlobalVariableInfo {
+            name: "RELOCATION_TARGET".to_string(),
+            namespace: vec!["qualified_fixture".to_string()],
+            ty: DebugLocalTypeKind::Basic {
+                name: "u32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_unsigned",
+            },
+            declaration: DebugSourcePosition {
+                file: PathBuf::from("/tmp/cuda-oxide/tests/qualified.rs"),
+                line: 30,
+                column: 1,
+            },
+            is_local_to_unit: true,
+            is_function_local: false,
+        },
+    );
+    target.get_operation().insert_at_back(module_block, &ctx);
+
+    let references_ty = StructType::get_unnamed(
+        &ctx,
+        (vec![i64_ty.into(), i64_ty.into()], StructLayout::Unpacked),
+    );
+    let references = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "__device_global_23".try_into().unwrap(),
+        references_ty.into(),
+        8,
+    );
+    references.set_address_space(&mut ctx, llvm_export::types::address_space::GLOBAL);
+    references.set_source_global_key(&mut ctx, "qualified_fixture::REFERENCES");
+    references.set_initializer_hex(&mut ctx, "00000000000000000000000000000000");
+    references.set_initializer_relocations(
+        &mut ctx,
+        &encode_global_initializer_relocations(&[
+            GlobalInitializerRelocation {
+                source_offset: 0,
+                width_bytes: 8,
+                target_address_space: llvm_export::types::address_space::GLOBAL,
+                target_addend: 0,
+                target_key: "qualified_fixture::RELOCATION_TARGET".to_string(),
+            },
+            GlobalInitializerRelocation {
+                source_offset: 8,
+                width_bytes: 8,
+                target_address_space: llvm_export::types::address_space::GLOBAL,
+                target_addend: 0,
+                target_key: "qualified_fixture::RELOCATION_TARGET".to_string(),
+            },
+        ]),
+    );
+    llvm_export::ops::set_debug_global_variable(
+        &mut ctx,
+        references.get_operation(),
+        &DebugGlobalVariableInfo {
+            name: "REFERENCES".to_string(),
+            namespace: vec!["qualified_fixture".to_string()],
+            ty: DebugLocalTypeKind::Array {
+                name: "[&u32; 2]".to_string(),
+                size_bits: 128,
+                element: Box::new(DebugLocalTypeKind::Pointer {
+                    name: "&u32".to_string(),
+                    size_bits: 64,
+                }),
+                count: 2,
+            },
+            declaration: DebugSourcePosition {
+                file: PathBuf::from("/tmp/cuda-oxide/tests/qualified.rs"),
+                line: 31,
+                column: 1,
+            },
+            is_local_to_unit: true,
+            is_function_local: false,
+        },
+    );
+    references
+        .get_operation()
+        .insert_at_back(module_block, &ctx);
+
+    let export = |debug_kind| {
+        export_module_to_string_with_config(
+            &ctx,
+            &module,
+            &DebugConfig {
+                inner: PtxExportConfig,
+                debug_kind,
+            },
+        )
+        .expect("global debug export succeeds")
+    };
+    let full = export(DebugKind::Full);
+
+    let metadata_id = |needle: &str| {
+        full.lines()
+            .find(|line| line.contains(needle))
+            .unwrap_or_else(|| panic!("missing `{needle}` in:\n{full}"))
+            .split_once(" = ")
+            .expect("metadata definition")
+            .0
+            .trim_start_matches('!')
+            .to_string()
+    };
+    let left_scope = metadata_id("!DINamespace(name: \"left\"");
+    let right_scope = metadata_id("!DINamespace(name: \"right\"");
+    let left_variable = full
+        .lines()
+        .find(|line| {
+            line.contains("!DIGlobalVariable(name: \"SAME_LEAF\"")
+                && line.contains("linkageName: \"__device_global_20\"")
+        })
+        .expect("left source global");
+    let right_variable = full
+        .lines()
+        .find(|line| {
+            line.contains("!DIGlobalVariable(name: \"SAME_LEAF\"")
+                && line.contains("linkageName: \"__device_global_21\"")
+        })
+        .expect("right source global");
+    assert!(left_variable.contains(&format!("scope: !{left_scope}")));
+    assert!(left_variable.contains("line: 20") && left_variable.contains("isLocal: true"));
+    assert!(right_variable.contains(&format!("scope: !{right_scope}")));
+    assert!(right_variable.contains("line: 24") && right_variable.contains("isLocal: false"));
+
+    let target_definition = full
+        .lines()
+        .find(|line| line.starts_with("@__device_global_22 = "))
+        .expect("relocation-only target definition");
+    assert!(target_definition.contains("[4 x i8]") && target_definition.contains("!dbg !"));
+    let target_variable = full
+        .lines()
+        .find(|line| line.contains("!DIGlobalVariable(name: \"RELOCATION_TARGET\""))
+        .expect("relocation-only target source identity");
+    assert!(
+        target_variable.contains("linkageName: \"__device_global_22\"")
+            && target_variable.contains("line: 30")
+    );
+
+    let reference_definition = full
+        .lines()
+        .find(|line| line.starts_with("@__device_global_23 = "))
+        .expect("relocation-backed definition");
+    assert_eq!(
+        reference_definition.matches("@__device_global_22").count(),
+        2,
+        "both initializer references must target the same one physical global"
+    );
+    assert!(
+        full.contains("!DICompositeType(tag: DW_TAG_array_type, baseType: !")
+            && full.contains("size: 128, elements: !")
+            && full.contains("!DIDerivedType(tag: DW_TAG_pointer_type, name: \"&u32\"")
+    );
+
+    assert_eq!(
+        full.matches("!DIGlobalVariableExpression(var:").count(),
+        4,
+        "one expression per physical source global, despite repeated relocations"
+    );
+    let compile_unit = full
+        .lines()
+        .find(|line| line.contains("!DICompileUnit("))
+        .expect("debug compile unit");
+    let globals_id = compile_unit
+        .split("globals: !")
+        .nth(1)
+        .and_then(|tail| tail.strip_suffix(')'))
+        .expect("compile-unit globals tuple");
+    let globals_tuple = full
+        .lines()
+        .find(|line| line.starts_with(&format!("!{globals_id} = !{{")))
+        .expect("compile-unit globals tuple definition");
+    assert_eq!(globals_tuple.matches('!').count() - 2, 4, "{globals_tuple}");
+
+    assert_eq!(
+        export(DebugKind::LineTables),
+        export(DebugKind::Off),
+        "initialized and relocation-backed globals must not gain metadata outside Full debug"
+    );
+
+    let Some(llvm_as) = ["llvm-as-22", "llvm-as-21", "llvm-as"]
+        .into_iter()
+        .find(|tool| {
+            std::process::Command::new(tool)
+                .arg("--version")
+                .output()
+                .is_ok_and(|out| out.status.success())
+        })
+    else {
+        eprintln!("skipping global-debug parse gate: no llvm-as on PATH");
+        return;
+    };
+    let ll_path = std::env::temp_dir().join(format!(
+        "cuda_oxide_global_debug_parse_gate_{}.ll",
+        std::process::id()
+    ));
+    std::fs::write(&ll_path, &full).expect("write temp .ll");
+    let output = std::process::Command::new(llvm_as)
+        .arg("-o")
+        .arg("/dev/null")
+        .arg(&ll_path)
+        .output()
+        .expect("run llvm-as");
+    let stderr = String::from_utf8_lossy(&output.stderr).into_owned();
+    let _ = std::fs::remove_file(&ll_path);
+    assert!(
+        output.status.success(),
+        "{llvm_as} rejected global debug metadata:\n{stderr}\n--- module ---\n{full}"
+    );
+}
+
+#[test]
+fn full_debug_metadata_emits_rust_enum_variant_parts() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "enum_debug".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "enum_debug_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/enum.rs", 10, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
+    let one = ConstantOp::new(&mut ctx, one_attr.into());
+    one.get_operation().insert_at_back(entry, &ctx);
+    let one_val = one.get_operation().deref(&ctx).get_result(0);
+
+    let direct = AllocaOp::new(&mut ctx, i64_ty.into(), one_val);
+    let direct_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/enum.rs", 11, 9);
+    direct.get_operation().deref_mut(&ctx).set_loc(direct_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        direct.get_operation(),
+        DebugLocalVariableInfo {
+            name: "direct".to_string(),
+            argument_index: None,
+            ty: DebugLocalTypeKind::Enum {
+                name: "Direct".to_string(),
+                size_bits: 64,
+                discriminant: Some(DebugEnumDiscriminant {
+                    offset_bits: 0,
+                    ty: Box::new(DebugLocalTypeKind::Basic {
+                        name: "u8".to_string(),
+                        size_bits: 8,
+                        encoding: "DW_ATE_unsigned",
+                    }),
+                }),
+                variants: vec![
+                    DebugEnumVariant {
+                        name: "Small".to_string(),
+                        discriminant: Some(3),
+                        members: vec![llvm_export::ops::DebugTypeMember {
+                            name: "0".to_string(),
+                            offset_bits: 32,
+                            ty: DebugLocalTypeKind::Basic {
+                                name: "u32".to_string(),
+                                size_bits: 32,
+                                encoding: "DW_ATE_unsigned",
+                            },
+                        }],
+                    },
+                    DebugEnumVariant {
+                        name: "Empty".to_string(),
+                        discriminant: Some(9),
+                        members: vec![],
+                    },
+                ],
+            },
+        },
+    );
+    direct.get_operation().insert_at_back(entry, &ctx);
+
+    let niche = AllocaOp::new(&mut ctx, i64_ty.into(), one_val);
+    let niche_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/enum.rs", 12, 9);
+    niche.get_operation().deref_mut(&ctx).set_loc(niche_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        niche.get_operation(),
+        DebugLocalVariableInfo {
+            name: "niche".to_string(),
+            argument_index: None,
+            ty: DebugLocalTypeKind::Enum {
+                name: "OptionRef".to_string(),
+                size_bits: 64,
+                discriminant: Some(DebugEnumDiscriminant {
+                    offset_bits: 0,
+                    ty: Box::new(DebugLocalTypeKind::Basic {
+                        name: "usize".to_string(),
+                        size_bits: 64,
+                        encoding: "DW_ATE_unsigned",
+                    }),
+                }),
+                variants: vec![
+                    DebugEnumVariant {
+                        name: "None".to_string(),
+                        discriminant: Some(0),
+                        members: vec![],
+                    },
+                    DebugEnumVariant {
+                        name: "Some".to_string(),
+                        discriminant: None,
+                        members: vec![llvm_export::ops::DebugTypeMember {
+                            name: "0".to_string(),
+                            offset_bits: 0,
+                            ty: DebugLocalTypeKind::TypedPointer {
+                                name: "&u32".to_string(),
+                                size_bits: 64,
+                                pointee: Box::new(DebugLocalTypeKind::Basic {
+                                    name: "u32".to_string(),
+                                    size_bits: 32,
+                                    encoding: "DW_ATE_unsigned",
+                                }),
+                            },
+                        }],
+                    },
+                ],
+            },
+        },
+    );
+    niche.get_operation().insert_at_back(entry, &ctx);
+
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::Full,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("enum debug export");
+
+    assert!(
+        ir.contains("!DICompositeType(tag: DW_TAG_variant_part"),
+        "Rust enums must contain a DW_TAG_variant_part:\n{ir}"
+    );
+    assert!(
+        ir.contains("flags: DIFlagArtificial"),
+        "the physical enum carrier must be marked artificial:\n{ir}"
+    );
+    let discriminator_member = ir
+        .lines()
+        .find(|line| {
+            line.contains("!DIDerivedType(tag: DW_TAG_member")
+                && line.contains("flags: DIFlagArtificial")
+        })
+        .expect("enum discriminator member");
+    assert!(
+        discriminator_member.contains("scope: !"),
+        "the physical enum carrier must be scoped to its enum object:\n{discriminator_member}\n{ir}"
+    );
+    let variant_part = ir
+        .lines()
+        .find(|line| line.contains("!DICompositeType(tag: DW_TAG_variant_part"))
+        .expect("enum variant part");
+    assert!(
+        variant_part.contains("scope: !"),
+        "the variant part must be scoped to its enum object:\n{variant_part}\n{ir}"
+    );
+    let direct_variant_member = ir
+        .lines()
+        .find(|line| {
+            line.contains("!DIDerivedType(tag: DW_TAG_member, name: \"Small\"")
+                && line.contains("extraData: i8 3")
+        })
+        .expect("direct enum variant member");
+    assert!(
+        direct_variant_member.contains("scope: !"),
+        "variant members must be scoped to their DW_TAG_variant_part:\n{direct_variant_member}\n{ir}"
+    );
+    assert!(
+        ir.contains("extraData: i8 3") && ir.contains("extraData: i8 9"),
+        "direct-tag variants must carry their physical discriminant values:\n{ir}"
+    );
+    assert!(
+        ir.contains("extraData: i64 0"),
+        "the tagged niche variant must carry the niche value:\n{ir}"
+    );
+
+    let some_variant_member = ir
+        .lines()
+        .find(|line| {
+            line.contains("!DIDerivedType(tag: DW_TAG_member, name: \"Some\"")
+                && line.contains("baseType:")
+        })
+        .expect("Some variant member");
+    assert!(
+        !some_variant_member.contains("extraData:"),
+        "the untagged niche variant must be the default branch:\n{some_variant_member}\n{ir}"
+    );
+}
+
+#[test]
+fn full_debug_metadata_uses_file_scope_for_cross_file_local_variables() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 30, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
+    let one = ConstantOp::new(&mut ctx, one_attr.into());
+    one.get_operation().insert_at_back(entry, &ctx);
+    let one_val = one.get_operation().deref(&ctx).get_result(0);
+
+    let tid = AllocaOp::new(&mut ctx, i32_ty.into(), one_val);
+    let tid_loc = src_location(
+        &mut ctx,
+        "/tmp/cuda-oxide/crates/cuda-device/src/thread.rs",
+        292,
+        19,
+    );
+    tid.get_operation().deref_mut(&ctx).set_loc(tid_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        tid.get_operation(),
+        DebugLocalVariableInfo {
+            name: "tid".to_string(),
+            argument_index: None,
+            ty: DebugLocalTypeKind::Basic {
+                name: "u32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_unsigned",
+            },
+        },
+    );
+    tid.get_operation().insert_at_back(entry, &ctx);
+
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::Full,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    assert!(
+        ir.contains("!DILexicalBlockFile(scope: !"),
+        "cross-file local variables should get a file-specific debug scope:\n{ir}"
+    );
+    assert!(
+        ir.contains(
+            "!DIFile(filename: \"thread.rs\", directory: \"/tmp/cuda-oxide/crates/cuda-device/src\")"
+        ),
+        "cross-file local variables should reference their source file:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocalVariable(name: \"tid\", scope: !") && ir.contains("line: 292"),
+        "cross-file local variables should preserve the variable file scope and line:\n{ir}"
+    );
+    assert!(
+        ir.contains("call void @llvm.dbg.declare"),
+        "cross-file local variables should still get dbg.declare bindings:\n{ir}"
+    );
+}
+
+#[test]
+fn full_debug_metadata_emits_dbg_value_for_promoted_locals() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![i32_ty.into()], false);
+    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 30, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let arg = entry.deref(&ctx).get_argument(0);
+    let dbg_value = DebugValueOp::new(&mut ctx, arg);
+    let dbg_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 31, 13);
+    dbg_value.get_operation().deref_mut(&ctx).set_loc(dbg_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        dbg_value.get_operation(),
+        DebugLocalVariableInfo {
+            name: "x".to_string(),
+            argument_index: Some(1),
+            ty: DebugLocalTypeKind::Basic {
+                name: "i32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_signed",
+            },
+        },
+    );
+    llvm_export::ops::set_debug_local_declaration_location(
+        &mut ctx,
+        dbg_value.get_operation(),
+        PathBuf::from("/tmp/cuda-oxide/tests/declarations.rs"),
+        12,
+        5,
+    );
+    llvm_export::ops::set_debug_fragment_variables(
+        &mut ctx,
+        dbg_value.get_operation(),
+        &[DebugFragmentVariableInfo {
+            variable: DebugLocalVariableInfo {
+                name: "pair".to_string(),
+                argument_index: None,
+                ty: DebugLocalTypeKind::Array {
+                    name: "[u32; 2]".to_string(),
+                    size_bits: 64,
+                    element: Box::new(DebugLocalTypeKind::Basic {
+                        name: "u32".to_string(),
+                        size_bits: 32,
+                        encoding: "DW_ATE_unsigned",
+                    }),
+                    count: 2,
+                },
+            },
+            fragment: DebugFragment {
+                offset_bits: 32,
+                size_bits: 32,
+            },
+            source_scope: None,
+            declaration: Some(DebugSourcePosition {
+                file: PathBuf::from("/tmp/cuda-oxide/tests/declarations.rs"),
+                line: 13,
+                column: 5,
+            }),
+        }],
+    );
+    dbg_value.get_operation().insert_at_back(entry, &ctx);
+
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::Full,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    assert!(
+        ir.contains("declare void @llvm.dbg.value(metadata, metadata, metadata)"),
+        "full debug should declare dbg.value when it emits one:\n{ir}"
+    );
+    assert!(
+        ir.contains("call void @llvm.dbg.value(metadata i32 %v0, metadata !"),
+        "dbg.value should describe the local as the current SSA value:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocalVariable(name: \"x\", arg: 1, scope: !"),
+        "dbg.value should preserve formal-argument metadata when the source local is an argument:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocalVariable(name: \"x\", arg: 1, scope: !")
+            && ir.contains("file: !")
+            && ir.contains("line: 12"),
+        "DILocalVariable should use the source declaration line, not the dbg.value line:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocation(line: 31, column: 13, scope: !"),
+        "dbg.value should still be located at the value's current source point:\n{ir}"
+    );
+    assert!(
+        ir.contains("DW_OP_LLVM_fragment, 32, 32"),
+        "dbg.value should preserve scalarized source-variable fragments:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocalVariable(name: \"pair\", scope: !") && ir.contains("line: 13"),
+        "fragment dbg.value should describe the complete source variable:\n{ir}"
+    );
+    assert!(
+        !ir.contains("llvm.dbg.declare"),
+        "a value-only debug record should not force dbg.declare:\n{ir}"
+    );
+}
+
+#[test]
+fn full_debug_metadata_emits_diarglist_for_multi_value_locations() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let ptr_ty = PointerType::get(&ctx, 0);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(
+        &ctx,
+        void_ty.to_handle(),
+        vec![ptr_ty.into(), i64_ty.into()],
+        false,
+    );
+    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 40, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let base = entry.deref(&ctx).get_argument(0);
+    let index = entry.deref(&ctx).get_argument(1);
+    let dbg_value = DebugValueListOp::new(&mut ctx, vec![base, index]);
+    let dbg_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 41, 17);
+    dbg_value.get_operation().deref_mut(&ctx).set_loc(dbg_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        dbg_value.get_operation(),
+        DebugLocalVariableInfo {
+            name: "item".to_string(),
+            argument_index: None,
+            ty: DebugLocalTypeKind::Basic {
+                name: "u32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_unsigned",
+            },
+        },
+    );
+    llvm_export::ops::set_debug_value_expression(
+        &mut ctx,
+        dbg_value.get_operation(),
+        &DebugValueExpression::new(vec![
+            DebugValueExpressionOp::Arg(0),
+            DebugValueExpressionOp::Arg(1),
+            DebugValueExpressionOp::ConstU(4),
+            DebugValueExpressionOp::Mul,
+            DebugValueExpressionOp::Plus,
+            DebugValueExpressionOp::Deref,
+        ]),
+    );
+    dbg_value.get_operation().insert_at_back(entry, &ctx);
+
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::Full,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    assert!(
+        ir.contains("call void @llvm.dbg.value(metadata !DIArgList(ptr %v0, i64 %v1), metadata !"),
+        "multi-value debug records should emit an inline DIArgList:\n{ir}"
+    );
+    assert!(
+        ir.contains(
+            "!DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_deref)"
+        ),
+        "multi-value debug records should emit the typed location recipe:\n{ir}"
+    );
+    assert!(
+        ir.contains("declare void @llvm.dbg.value(metadata, metadata, metadata)"),
+        "multi-value records should reuse the ordinary dbg.value intrinsic declaration:\n{ir}"
+    );
+
+    let Some(llvm_as) = ["llvm-as-22", "llvm-as-21", "llvm-as"]
+        .into_iter()
+        .find(|tool| {
+            std::process::Command::new(tool)
+                .arg("--version")
+                .output()
+                .is_ok_and(|out| out.status.success())
+        })
+    else {
+        eprintln!("skipping llvm-as parse gate: no llvm-as-22/llvm-as-21/llvm-as on PATH");
+        return;
+    };
+
+    let ll_path = std::env::temp_dir().join(format!(
+        "cuda_oxide_diarglist_parse_gate_{}.ll",
+        std::process::id()
+    ));
+    std::fs::write(&ll_path, &ir).expect("write temp .ll");
+    let output = std::process::Command::new(llvm_as)
+        .arg("-o")
+        .arg("/dev/null")
+        .arg(&ll_path)
+        .output()
+        .expect("run llvm-as");
+    let stderr = String::from_utf8_lossy(&output.stderr).into_owned();
+    let _ = std::fs::remove_file(&ll_path);
+    assert!(
+        output.status.success(),
+        "{llvm_as} rejected the emitted multi-value debug module:\n{stderr}\n--- module ---\n{ir}"
+    );
+}
+
+#[test]
+fn full_debug_metadata_uses_inlined_callee_scope_for_inlined_arguments() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![i32_ty.into()], false);
+    let func = FuncOp::new(&mut ctx, "caller_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 30, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+    llvm_export::ops::set_debug_source_scope_map(
+        &mut ctx,
+        func.get_operation(),
+        &DebugSourceScopeMap {
+            scopes: vec![
+                DebugSourceScope {
+                    id: 0,
+                    parent: None,
+                    span: Some(DebugSourcePosition {
+                        file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
+                        line: 30,
+                        column: 1,
+                    }),
+                    inlined: None,
+                },
+                DebugSourceScope {
+                    id: 1,
+                    parent: Some(0),
+                    span: Some(DebugSourcePosition {
+                        file: PathBuf::from("/tmp/cuda-oxide/tests/helper.rs"),
+                        line: 7,
+                        column: 1,
+                    }),
+                    inlined: Some(llvm_export::ops::DebugInlinedScope {
+                        callee_name: "helper::next".to_string(),
+                        callsite: Some(DebugSourcePosition {
+                            file: PathBuf::from("/tmp/cuda-oxide/tests/kernel.rs"),
+                            line: 41,
+                            column: 13,
+                        }),
+                    }),
+                },
+            ],
+            locations: vec![],
+        },
+    );
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let arg = entry.deref(&ctx).get_argument(0);
+
+    let caller_value = DebugValueOp::new(&mut ctx, arg);
+    let caller_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 31, 9);
+    caller_value
+        .get_operation()
+        .deref_mut(&ctx)
+        .set_loc(caller_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        caller_value.get_operation(),
+        DebugLocalVariableInfo {
+            name: "data".to_string(),
+            argument_index: Some(1),
+            ty: DebugLocalTypeKind::Basic {
+                name: "i32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_signed",
+            },
+        },
+    );
+    llvm_export::ops::set_debug_local_source_scope(&mut ctx, caller_value.get_operation(), 0);
+    caller_value.get_operation().insert_at_back(entry, &ctx);
+
+    let inlined_value = DebugValueOp::new(&mut ctx, arg);
+    let inlined_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/helper.rs", 8, 17);
+    inlined_value
+        .get_operation()
+        .deref_mut(&ctx)
+        .set_loc(inlined_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        inlined_value.get_operation(),
+        DebugLocalVariableInfo {
+            name: "self".to_string(),
+            argument_index: Some(1),
+            ty: DebugLocalTypeKind::Basic {
+                name: "i32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_signed",
+            },
+        },
+    );
+    llvm_export::ops::set_debug_local_source_scope(&mut ctx, inlined_value.get_operation(), 1);
+    inlined_value.get_operation().insert_at_back(entry, &ctx);
+
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::Full,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    assert!(
+        ir.contains("distinct !DISubprogram(name: \"caller_kernel\""),
+        "caller should keep its own function debug scope:\n{ir}"
+    );
+    assert!(
+        ir.contains("distinct !DISubprogram(name: \"helper::next\""),
+        "inlined callee should get its own DISubprogram scope:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocalVariable(name: \"data\", arg: 1, scope: !"),
+        "caller argument should remain arg #1 in the caller scope:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocalVariable(name: \"self\", arg: 1, scope: !"),
+        "inlined callee argument should remain arg #1 in the callee scope:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocation(line: 8, column: 17, scope: !") && ir.contains("inlinedAt: !"),
+        "inlined dbg.value location should point at the callee line and caller callsite:\n{ir}"
+    );
+}
+
+#[test]
+fn line_table_debug_metadata_ignores_tagged_alloca_variables() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 40, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
+    let one = ConstantOp::new(&mut ctx, one_attr.into());
+    one.get_operation().insert_at_back(entry, &ctx);
+    let one_val = one.get_operation().deref(&ctx).get_result(0);
+
+    let local = AllocaOp::new(&mut ctx, i32_ty.into(), one_val);
+    let local_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 41, 9);
+    local.get_operation().deref_mut(&ctx).set_loc(local_loc);
+    llvm_export::ops::set_debug_local_variable(
+        &mut ctx,
+        local.get_operation(),
+        DebugLocalVariableInfo {
+            name: "x".to_string(),
+            argument_index: None,
+            ty: DebugLocalTypeKind::Basic {
+                name: "i32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_signed",
+            },
+        },
+    );
+    local.get_operation().insert_at_back(entry, &ctx);
+
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::LineTables,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    assert!(
+        ir.contains("emissionKind: LineTablesOnly"),
+        "line-table mode should stay line-table-only:\n{ir}"
+    );
+    assert!(
+        !ir.contains("llvm.dbg.declare"),
+        "line-table mode should not emit variable bindings:\n{ir}"
+    );
+    assert!(
+        !ir.contains("DILocalVariable"),
+        "line-table mode should not emit local-variable metadata:\n{ir}"
+    );
+}
+
+#[test]
+fn line_table_debug_metadata_adds_fallback_locations_to_calls() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let void_ty = VoidType::get(&ctx);
+    let helper_ty = FuncType::get(&ctx, i32_ty.to_handle(), vec![], false);
+    let helper = FuncOp::new(&mut ctx, "helper".try_into().unwrap(), helper_ty);
+    helper.get_operation().insert_at_back(module_block, &ctx);
+
+    let caller_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let caller = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), caller_ty);
+    let caller_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 20, 3);
+    caller.get_operation().deref_mut(&ctx).set_loc(caller_loc);
+
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    let call = CallOp::new(
+        &mut ctx,
+        CallOpCallable::Direct("helper".try_into().unwrap()),
+        helper_ty,
+        vec![],
+    );
+    call.get_operation().insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::LineTables,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    let call_line = ir
+        .lines()
+        .find(|line| line.contains("call i32 @helper()"))
+        .expect("call instruction");
+    assert!(
+        call_line.contains(", !dbg !"),
+        "calls without their own source span should use the function fallback location:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocation(line: 20, column: 3, scope: !"),
+        "fallback call location should point at the caller's function line:\n{ir}"
+    );
+}
+
+#[test]
+fn line_table_debug_metadata_emits_explicit_artificial_calls_at_line_zero() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let void_ty = VoidType::get(&ctx);
+    let helper_ty = FuncType::get(&ctx, i32_ty.to_handle(), vec![], false);
+    let helper = FuncOp::new(&mut ctx, "helper".try_into().unwrap(), helper_ty);
+    helper.get_operation().insert_at_back(module_block, &ctx);
+
+    let caller_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let caller = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), caller_ty);
+    let caller_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 20, 3);
+    caller.get_operation().deref_mut(&ctx).set_loc(caller_loc);
+
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    let call = CallOp::new(
+        &mut ctx,
+        CallOpCallable::Direct("helper".try_into().unwrap()),
+        helper_ty,
+        vec![],
+    );
+    call.get_operation()
+        .deref_mut(&ctx)
+        .set_loc(llvm_export::artificial_debug_location());
+    call.get_operation().insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::LineTables,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    let call_line = ir
+        .lines()
+        .find(|line| line.contains("call i32 @helper()"))
+        .expect("call instruction");
+    assert!(
+        call_line.contains(", !dbg !"),
+        "LLVM still requires an artificial call location:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DILocation(line: 0, column: 0, scope: !"),
+        "artificial setup must not reuse the caller's user line:\n{ir}"
+    );
+}
+
+#[test]
+fn full_debug_metadata_emits_scalarized_fragment_dbg_declares() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "fragment_debug".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
+    let func = FuncOp::new(
+        &mut ctx,
+        "fragment_debug_kernel".try_into().unwrap(),
+        func_ty,
+    );
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/fragments.rs", 10, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
+    let one = ConstantOp::new(&mut ctx, one_attr.into());
+    let one_value = one.get_operation().deref(&ctx).get_result(0);
+    one.get_operation().insert_at_back(entry, &ctx);
+
+    let whole_ty = DebugLocalTypeKind::Array {
+        name: "[u32; 2]".to_string(),
+        size_bits: 64,
+        element: Box::new(DebugLocalTypeKind::Basic {
+            name: "u32".to_string(),
+            size_bits: 32,
+            encoding: "DW_ATE_unsigned",
+        }),
+        count: 2,
+    };
+    for (index, offset_bits) in [0u64, 32].into_iter().enumerate() {
+        let alloca = AllocaOp::new(&mut ctx, i32_ty.into(), one_value);
+        llvm_export::ops::set_debug_fragment_variables(
+            &mut ctx,
+            alloca.get_operation(),
+            &[DebugFragmentVariableInfo {
+                variable: DebugLocalVariableInfo {
+                    name: "pair".to_string(),
+                    argument_index: None,
+                    ty: whole_ty.clone(),
+                },
+                fragment: DebugFragment {
+                    offset_bits,
+                    size_bits: 32,
+                },
+                source_scope: None,
+                declaration: Some(DebugSourcePosition {
+                    file: PathBuf::from("/tmp/cuda-oxide/tests/fragments.rs"),
+                    line: 11,
+                    column: 9,
+                }),
+            }],
+        );
+        let loc = src_location(
+            &mut ctx,
+            "/tmp/cuda-oxide/tests/fragments.rs",
+            12 + index as i32,
+            9,
+        );
+        alloca.get_operation().deref_mut(&ctx).set_loc(loc);
+        alloca.get_operation().insert_at_back(entry, &ctx);
+    }
+
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::Full,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+
+    assert!(
+        ir.contains("DW_OP_LLVM_fragment, 0, 32"),
+        "first scalarized piece should describe the low fragment:\n{ir}"
+    );
+    assert!(
+        ir.contains("DW_OP_LLVM_fragment, 32, 32"),
+        "second scalarized piece should describe the high fragment:\n{ir}"
+    );
+    assert_eq!(
+        ir.matches("!DILocalVariable(name: \"pair\"").count(),
+        1,
+        "all pieces must share one DILocalVariable identity:\n{ir}"
+    );
+    assert_eq!(
+        ir.matches("call void @llvm.dbg.declare").count(),
+        2,
+        "each scalarized storage piece should emit one dbg.declare:\n{ir}"
+    );
+
+    let Some(llvm_as) = ["llvm-as-22", "llvm-as-21", "llvm-as"]
+        .into_iter()
+        .find(|tool| {
+            std::process::Command::new(tool)
+                .arg("--version")
+                .output()
+                .is_ok_and(|out| out.status.success())
+        })
+    else {
+        eprintln!("skipping fragment llvm-as parse gate: no llvm-as on PATH");
+        return;
+    };
+    let ll_path = std::env::temp_dir().join(format!(
+        "cuda_oxide_fragment_parse_gate_{}.ll",
+        std::process::id()
+    ));
+    std::fs::write(&ll_path, &ir).expect("write fragment temp .ll");
+    let output = std::process::Command::new(llvm_as)
+        .arg("-o")
+        .arg("/dev/null")
+        .arg(&ll_path)
+        .output()
+        .expect("run llvm-as for fragments");
+    let stderr = String::from_utf8_lossy(&output.stderr).into_owned();
+    let _ = std::fs::remove_file(&ll_path);
+    assert!(
+        output.status.success(),
+        "{llvm_as} rejected scalarized fragment debug metadata:\n{stderr}\n--- module ---\n{ir}"
+    );
+}
+
+#[test]
+fn full_debug_metadata_emits_projected_dbg_declares() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "projected_debug".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
+    let func = FuncOp::new(
+        &mut ctx,
+        "projected_debug_kernel".try_into().unwrap(),
+        func_ty,
+    );
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/projected.rs", 10, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
+    let one = ConstantOp::new(&mut ctx, one_attr.into());
+    let one_value = one.get_operation().deref(&ctx).get_result(0);
+    one.get_operation().insert_at_back(entry, &ctx);
+
+    let storage_ty = ArrayType::get(&ctx, i32_ty.into(), 8);
+    let alloca = AllocaOp::new(&mut ctx, storage_ty.into(), one_value);
+    llvm_export::ops::set_debug_projected_variables(
+        &mut ctx,
+        alloca.get_operation(),
+        &[
+            DebugProjectedVariableInfo {
+                variable: DebugLocalVariableInfo {
+                    name: "field_value".to_string(),
+                    argument_index: None,
+                    ty: DebugLocalTypeKind::Basic {
+                        name: "u32".to_string(),
+                        size_bits: 32,
+                        encoding: "DW_ATE_unsigned",
+                    },
+                },
+                dereference_base: false,
+                offset_bytes: 8,
+                source_scope: None,
+                declaration: Some(DebugSourcePosition {
+                    file: PathBuf::from("/tmp/cuda-oxide/tests/projected.rs"),
+                    line: 11,
+                    column: 9,
+                }),
+            },
+            DebugProjectedVariableInfo {
+                variable: DebugLocalVariableInfo {
+                    name: "tuple_value".to_string(),
+                    argument_index: None,
+                    ty: DebugLocalTypeKind::Basic {
+                        name: "u64".to_string(),
+                        size_bits: 64,
+                        encoding: "DW_ATE_unsigned",
+                    },
+                },
+                dereference_base: false,
+                offset_bytes: 16,
+                source_scope: None,
+                declaration: Some(DebugSourcePosition {
+                    file: PathBuf::from("/tmp/cuda-oxide/tests/projected.rs"),
+                    line: 12,
+                    column: 9,
+                }),
+            },
+            DebugProjectedVariableInfo {
+                variable: DebugLocalVariableInfo {
+                    name: "array_value".to_string(),
+                    argument_index: None,
+                    ty: DebugLocalTypeKind::Basic {
+                        name: "u32".to_string(),
+                        size_bits: 32,
+                        encoding: "DW_ATE_unsigned",
+                    },
+                },
+                dereference_base: false,
+                offset_bytes: 24,
+                source_scope: None,
+                declaration: Some(DebugSourcePosition {
+                    file: PathBuf::from("/tmp/cuda-oxide/tests/projected.rs"),
+                    line: 13,
+                    column: 9,
+                }),
+            },
+            DebugProjectedVariableInfo {
+                variable: DebugLocalVariableInfo {
+                    name: "deref_value".to_string(),
+                    argument_index: None,
+                    ty: DebugLocalTypeKind::Basic {
+                        name: "u32".to_string(),
+                        size_bits: 32,
+                        encoding: "DW_ATE_unsigned",
+                    },
+                },
+                dereference_base: true,
+                offset_bytes: 0,
+                source_scope: None,
+                declaration: Some(DebugSourcePosition {
+                    file: PathBuf::from("/tmp/cuda-oxide/tests/projected.rs"),
+                    line: 14,
+                    column: 9,
+                }),
+            },
+            DebugProjectedVariableInfo {
+                variable: DebugLocalVariableInfo {
+                    name: "deref_field_value".to_string(),
+                    argument_index: None,
+                    ty: DebugLocalTypeKind::Basic {
+                        name: "u64".to_string(),
+                        size_bits: 64,
+                        encoding: "DW_ATE_unsigned",
+                    },
+                },
+                dereference_base: true,
+                offset_bytes: 32,
+                source_scope: None,
+                declaration: Some(DebugSourcePosition {
+                    file: PathBuf::from("/tmp/cuda-oxide/tests/projected.rs"),
+                    line: 15,
+                    column: 9,
+                }),
+            },
+        ],
+    );
+    alloca.get_operation().insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::Full,
+    };
+    let ir = export_module_to_string_with_config(&ctx, &module, &config)
+        .expect("projected debug export succeeds");
+
+    assert_eq!(
+        ir.matches("call void @llvm.dbg.declare").count(),
+        5,
+        "each projected source variable should get its own dbg.declare:\n{ir}"
+    );
+    for name in [
+        "field_value",
+        "tuple_value",
+        "array_value",
+        "deref_value",
+        "deref_field_value",
+    ] {
+        assert!(
+            ir.contains(&format!("!DILocalVariable(name: \"{name}\"")),
+            "missing projected variable {name}:\n{ir}"
+        );
+    }
+    for offset in [8u64, 16, 24] {
+        assert!(
+            ir.contains(&format!("!DIExpression(DW_OP_plus_uconst, {offset})")),
+            "missing static projection offset {offset}:\n{ir}"
+        );
+    }
+    assert!(
+        ir.contains("!DIExpression(DW_OP_deref)"),
+        "missing dereference-only debug expression:\n{ir}"
+    );
+    assert!(
+        ir.contains("!DIExpression(DW_OP_deref, DW_OP_plus_uconst, 32)"),
+        "missing dereference-plus-field debug expression:\n{ir}"
+    );
+}
diff --git a/crates/llvm-export/tests/export_test/device_externs.rs b/crates/llvm-export/tests/export_test/device_externs.rs
new file mode 100644
index 0000000000..ee928c3819
--- /dev/null
+++ b/crates/llvm-export/tests/export_test/device_externs.rs
@@ -0,0 +1,800 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use llvm_export::{
+    export::{
+        DeviceExternAttrs, DeviceExternDecl, DeviceExternType, NvvmExportConfig, NvvmIrDialect,
+        export_module_with_externs,
+    },
+    ops::{AddressOfOp, CallOp, FuncOp, ReturnOp},
+    types::{FuncType, HalfType, PointerType, VoidType},
+};
+use pliron::{
+    builtin::{
+        op_interfaces::CallOpCallable,
+        ops::ModuleOp,
+        types::{IntegerType, Signedness},
+    },
+    context::Context,
+    op::Op,
+};
+
+use crate::common::module_top_block;
+
+#[test]
+fn legacy_device_extern_adapts_exact_pointer_arguments_and_results() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "legacy_extern".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let ptr_ty = PointerType::get(&ctx, 0);
+    let external_ty = FuncType::get(&ctx, ptr_ty.into(), vec![ptr_ty.into()], false);
+    FuncOp::new(&mut ctx, "float_roundtrip".try_into().unwrap(), external_ty)
+        .get_operation()
+        .insert_at_back(module_block, &ctx);
+
+    let void_ty = VoidType::get(&ctx);
+    let caller_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), caller_ty);
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    let pointer = entry.deref(&ctx).get_argument(0);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Direct("float_roundtrip".try_into().unwrap()),
+        external_ty,
+        vec![pointer],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let externs = [DeviceExternDecl {
+        export_name: "float_roundtrip".to_string(),
+        param_types: vec![DeviceExternType::pointer_to(DeviceExternType::Float32, 0)],
+        return_type: DeviceExternType::pointer_to(DeviceExternType::Float32, 0),
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let ir = export_module_with_externs(
+        &ctx,
+        &module,
+        &externs,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect("legacy extern export succeeds");
+
+    assert!(
+        ir.contains("declare float* @float_roundtrip(float*)"),
+        "{ir}"
+    );
+    assert!(ir.contains("bitcast i8* %v0 to float*"), "{ir}");
+    assert!(ir.contains("call float* @float_roundtrip(float*"), "{ir}");
+    assert!(
+        ir.contains(" = bitcast float* ") && ir.contains(" to i8*"),
+        "{ir}"
+    );
+    assert!(
+        !ir.split(|c: char| !c.is_ascii_alphanumeric())
+            .any(|token| token == "ptr"),
+        "{ir}"
+    );
+}
+
+#[test]
+fn legacy_device_extern_preserves_pointer_address_spaces() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "legacy_extern_as".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let ptr_ty = PointerType::get(&ctx, 3);
+    let void_ty = VoidType::get(&ctx);
+    let external_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
+    FuncOp::new(&mut ctx, "shared_float".try_into().unwrap(), external_ty)
+        .get_operation()
+        .insert_at_back(module_block, &ctx);
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), external_ty);
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    let pointer = entry.deref(&ctx).get_argument(0);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Direct("shared_float".try_into().unwrap()),
+        external_ty,
+        vec![pointer],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let externs = [DeviceExternDecl {
+        export_name: "shared_float".to_string(),
+        param_types: vec![DeviceExternType::pointer_to(DeviceExternType::Float32, 3)],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let ir = export_module_with_externs(
+        &ctx,
+        &module,
+        &externs,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect("legacy extern export succeeds");
+    assert!(
+        ir.contains("declare void @shared_float(float addrspace(3)*)"),
+        "{ir}"
+    );
+    assert!(
+        ir.contains("bitcast i8 addrspace(3)* %v0 to float addrspace(3)*"),
+        "{ir}"
+    );
+}
+
+#[test]
+fn modern_device_extern_erases_pointee_without_boundary_casts() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "modern_extern".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let ptr_ty = PointerType::get(&ctx, 0);
+    let void_ty = VoidType::get(&ctx);
+    let external_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
+    FuncOp::new(&mut ctx, "takes_float".try_into().unwrap(), external_ty)
+        .get_operation()
+        .insert_at_back(module_block, &ctx);
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), external_ty);
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    let pointer = entry.deref(&ctx).get_argument(0);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Direct("takes_float".try_into().unwrap()),
+        external_ty,
+        vec![pointer],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let externs = [DeviceExternDecl {
+        export_name: "takes_float".to_string(),
+        param_types: vec![DeviceExternType::pointer_to(DeviceExternType::Float32, 0)],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let ir = export_module_with_externs(
+        &ctx,
+        &module,
+        &externs,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect("modern extern export succeeds");
+    assert!(ir.contains("declare void @takes_float(ptr)"), "{ir}");
+    assert!(ir.contains("call void @takes_float(ptr %v0)"), "{ir}");
+    assert!(!ir.contains("bitcast"), "{ir}");
+}
+
+#[test]
+fn device_extern_rejects_invalid_symbol_and_address_space_mismatch() {
+    let mut ctx = Context::new();
+    let empty = ModuleOp::new(&mut ctx, "empty".try_into().unwrap());
+    let invalid = [DeviceExternDecl {
+        export_name: "bad.name".to_string(),
+        param_types: vec![],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let err = export_module_with_externs(
+        &ctx,
+        &empty,
+        &invalid,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("invalid NVVM symbol must fail");
+    assert!(err.contains("global-identifier subset"), "{err}");
+
+    let reserved_intrinsic_prefix = [DeviceExternDecl {
+        export_name: "llvm_external".to_string(),
+        param_types: vec![],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let err = export_module_with_externs(
+        &ctx,
+        &empty,
+        &reserved_intrinsic_prefix,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("the reserved intrinsic namespace must not be ambiguous");
+    assert!(err.contains("reserves for LLVM intrinsics"), "{err}");
+
+    let by_value_array = [DeviceExternDecl {
+        export_name: "array_by_value".to_string(),
+        param_types: vec![DeviceExternType::Array {
+            element: Box::new(DeviceExternType::Float32),
+            len: 4,
+        }],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let err = export_module_with_externs(
+        &ctx,
+        &empty,
+        &by_value_array,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("by-value aggregate externs must be rejected");
+    assert!(err.contains("passes an array by value"), "{err}");
+
+    let nested_half = [DeviceExternDecl {
+        export_name: "half_buffer".to_string(),
+        param_types: vec![DeviceExternType::pointer_to(
+            DeviceExternType::Array {
+                element: Box::new(DeviceExternType::Float16),
+                len: 4,
+            },
+            0,
+        )],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let err = export_module_with_externs(
+        &ctx,
+        &empty,
+        &nested_half,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("legacy half nested in a pointer must fail");
+    assert!(
+        err.contains("CUDA 12 legacy") && err.contains("half"),
+        "{err}"
+    );
+    let modern = export_module_with_externs(
+        &ctx,
+        &empty,
+        &nested_half,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect("modern opaque-pointer extern may use half pointees");
+    assert!(
+        modern.contains("declare void @half_buffer(ptr)"),
+        "{modern}"
+    );
+
+    let module = ModuleOp::new(&mut ctx, "mismatch".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let ptr0 = PointerType::get(&ctx, 0);
+    let void_ty = VoidType::get(&ctx);
+    let external_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr0.into()], false);
+    FuncOp::new(&mut ctx, "shared_only".try_into().unwrap(), external_ty)
+        .get_operation()
+        .insert_at_back(module_block, &ctx);
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), external_ty);
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    let pointer = entry.deref(&ctx).get_argument(0);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Direct("shared_only".try_into().unwrap()),
+        external_ty,
+        vec![pointer],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+    let mismatch = [DeviceExternDecl {
+        export_name: "shared_only".to_string(),
+        param_types: vec![DeviceExternType::pointer_to(DeviceExternType::Float32, 3)],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let err = export_module_with_externs(
+        &ctx,
+        &module,
+        &mismatch,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("address-space mismatch must fail");
+    assert!(
+        err.contains("parameter, result, or pointer address-space types"),
+        "{err}"
+    );
+}
+
+#[test]
+fn device_extern_rejects_same_name_declaration_shape_without_a_call() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "extern_decl_conflict".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let void_ty = VoidType::get(&ctx);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let lowered_type = FuncType::get(&ctx, void_ty.into(), vec![i32_ty.into()], false);
+    FuncOp::new(
+        &mut ctx,
+        "conflicting_decl".try_into().unwrap(),
+        lowered_type,
+    )
+    .get_operation()
+    .insert_at_back(module_block, &ctx);
+
+    let externs = [DeviceExternDecl {
+        export_name: "conflicting_decl".to_string(),
+        param_types: vec![DeviceExternType::Float32],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let error = export_module_with_externs(
+        &ctx,
+        &module,
+        &externs,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("the exporter must independently reject a conflicting declaration");
+    assert!(
+        error.contains("parameter, result, or pointer address-space types"),
+        "{error}"
+    );
+}
+
+#[test]
+fn device_extern_rejects_definition_and_address_taken_shape_conflicts() {
+    let mut ctx = Context::new();
+    let void_ty = VoidType::get(&ctx);
+
+    let definition_module = ModuleOp::new(&mut ctx, "extern_definition".try_into().unwrap());
+    let definition_block = module_top_block(&mut ctx, &definition_module);
+    let no_args = FuncType::get(&ctx, void_ty.into(), vec![], false);
+    let definition = FuncOp::new(&mut ctx, "defined_external".try_into().unwrap(), no_args);
+    let definition_entry = definition.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(definition_entry, &ctx);
+    definition
+        .get_operation()
+        .insert_at_back(definition_block, &ctx);
+    let definition_extern = [DeviceExternDecl {
+        export_name: "defined_external".to_string(),
+        param_types: vec![],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let error = export_module_with_externs(
+        &ctx,
+        &definition_module,
+        &definition_extern,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("a side-table extern must not collide with a definition");
+    assert!(error.contains("function definition"), "{error}");
+
+    let address_module = ModuleOp::new(&mut ctx, "extern_address".try_into().unwrap());
+    let address_block = module_top_block(&mut ctx, &address_module);
+    let generic_pointer = PointerType::get(&ctx, 0);
+    let lowered_type = FuncType::get(&ctx, void_ty.into(), vec![generic_pointer.into()], false);
+    FuncOp::new(
+        &mut ctx,
+        "addressed_external".try_into().unwrap(),
+        lowered_type,
+    )
+    .get_operation()
+    .insert_at_back(address_block, &ctx);
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), lowered_type);
+    let caller_entry = caller.get_or_create_entry_block(&mut ctx);
+    let argument = caller_entry.deref(&ctx).get_argument(0);
+    let address = AddressOfOp::new(&mut ctx, "addressed_external".try_into().unwrap(), 0);
+    let address_value = address.get_operation().deref(&ctx).get_result(0);
+    address.get_operation().insert_at_back(caller_entry, &ctx);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Indirect(address_value),
+        lowered_type,
+        vec![argument],
+    )
+    .get_operation()
+    .insert_at_back(caller_entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(caller_entry, &ctx);
+    caller.get_operation().insert_at_back(address_block, &ctx);
+    let address_extern = [DeviceExternDecl {
+        export_name: "addressed_external".to_string(),
+        param_types: vec![DeviceExternType::pointer_to(DeviceExternType::Float32, 3)],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let error = export_module_with_externs(
+        &ctx,
+        &address_module,
+        &address_extern,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("address-taking must not bypass exact extern shape validation");
+    assert!(
+        error.contains("parameter, result, or pointer address-space types"),
+        "{error}"
+    );
+}
+
+#[test]
+fn modern_device_extern_emits_signext_zeroext_for_small_integer_params() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "small_types_extern".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    // The extern takes (i8 signext, i16 zeroext, i1 zeroext, half) and
+    // returns void. The declared IR types stay NARROW (matching cuda-oxide's
+    // own i8/i16/i1 SSA values and the clang-compiled LTOIR definition); the
+    // ABI extension attributes live only in the DeviceExternType metadata.
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let i16_ty = IntegerType::get(&ctx, 16, Signedness::Signless);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let half_ty = HalfType::get(&ctx);
+    let void_ty = VoidType::get(&ctx);
+
+    let external_ty = FuncType::get(
+        &ctx,
+        void_ty.into(),
+        vec![i8_ty.into(), i16_ty.into(), i1_ty.into(), half_ty.into()],
+        false,
+    );
+    FuncOp::new(&mut ctx, "small_types_fn".try_into().unwrap(), external_ty)
+        .get_operation()
+        .insert_at_back(module_block, &ctx);
+
+    // Caller that forwards its own narrow parameters to the extern with no
+    // value conversions.
+    let caller_ty = FuncType::get(
+        &ctx,
+        void_ty.into(),
+        vec![i8_ty.into(), i16_ty.into(), i1_ty.into(), half_ty.into()],
+        false,
+    );
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), caller_ty);
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    let arg0 = entry.deref(&ctx).get_argument(0);
+    let arg1 = entry.deref(&ctx).get_argument(1);
+    let arg2 = entry.deref(&ctx).get_argument(2);
+    let arg3 = entry.deref(&ctx).get_argument(3);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Direct("small_types_fn".try_into().unwrap()),
+        external_ty,
+        vec![arg0, arg1, arg2, arg3],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let externs = [DeviceExternDecl {
+        export_name: "small_types_fn".to_string(),
+        param_types: vec![
+            DeviceExternType::SignExtInteger(8), // i8, sign-extended by NVPTX
+            DeviceExternType::ZeroExtInteger(16), // u16, zero-extended by NVPTX
+            DeviceExternType::ZeroExtInteger(1), // bool
+            DeviceExternType::Float16,           // f16 as native half
+        ],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+
+    let ir = export_module_with_externs(
+        &ctx,
+        &module,
+        &externs,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect("modern extern with small types export succeeds");
+
+    // Declaration: narrow types with parameter-position attributes.
+    assert!(
+        ir.contains("declare void @small_types_fn(i8 signext, i16 zeroext, i1 zeroext, half)"),
+        "declaration should keep narrow types with signext/zeroext attributes:\n{ir}"
+    );
+
+    // Call site keeps the narrow types and attributes too.
+    assert!(
+        ir.contains("i8 signext %v0"),
+        "call should use signext on first arg:\n{ir}"
+    );
+    assert!(
+        ir.contains("i16 zeroext %v1"),
+        "call should use zeroext on second arg:\n{ir}"
+    );
+    assert!(
+        ir.contains("i1 zeroext %v2"),
+        "call should use zeroext on the bool arg:\n{ir}"
+    );
+    assert!(
+        ir.contains("half %v3"),
+        "call should use half for the f16 arg:\n{ir}"
+    );
+}
+
+#[test]
+fn modern_device_extern_signext_return_type() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "signext_return".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let void_ty = VoidType::get(&ctx);
+
+    // Extern returns i8 with signext. The declared type stays i8; only the
+    // attribute marks the NVPTX widening, and in return position LLVM's
+    // grammar requires the attribute BEFORE the type.
+    let external_ty = FuncType::get(&ctx, i8_ty.into(), vec![], false);
+    FuncOp::new(&mut ctx, "get_small_val".try_into().unwrap(), external_ty)
+        .get_operation()
+        .insert_at_back(module_block, &ctx);
+
+    // Caller that calls the extern and discards the result.
+    let caller_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), caller_ty);
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Direct("get_small_val".try_into().unwrap()),
+        external_ty,
+        vec![],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let externs = [DeviceExternDecl {
+        export_name: "get_small_val".to_string(),
+        param_types: vec![],
+        return_type: DeviceExternType::SignExtInteger(8),
+        attrs: DeviceExternAttrs::default(),
+    }];
+
+    let ir = export_module_with_externs(
+        &ctx,
+        &module,
+        &externs,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect("modern extern with signext return export succeeds");
+
+    // Declaration: attribute precedes the narrow return type.
+    assert!(
+        ir.contains("declare signext i8 @get_small_val()"),
+        "declaration should have signext BEFORE the return type:\n{ir}"
+    );
+
+    // Call site uses the same return-position placement.
+    assert!(
+        ir.contains("call signext i8 @get_small_val()"),
+        "call should have signext BEFORE the return type:\n{ir}"
+    );
+}
+
+#[test]
+fn plain_integer_device_extern_has_no_extension_attributes() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "plain_int".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let void_ty = VoidType::get(&ctx);
+
+    let external_ty = FuncType::get(&ctx, void_ty.into(), vec![i32_ty.into()], false);
+    FuncOp::new(&mut ctx, "plain_int_fn".try_into().unwrap(), external_ty)
+        .get_operation()
+        .insert_at_back(module_block, &ctx);
+
+    let caller = FuncOp::new(&mut ctx, "caller".try_into().unwrap(), external_ty);
+    let entry = caller.get_or_create_entry_block(&mut ctx);
+    let arg0 = entry.deref(&ctx).get_argument(0);
+    CallOp::new(
+        &mut ctx,
+        CallOpCallable::Direct("plain_int_fn".try_into().unwrap()),
+        external_ty,
+        vec![arg0],
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    let externs = [DeviceExternDecl {
+        export_name: "plain_int_fn".to_string(),
+        param_types: vec![DeviceExternType::Integer(32)],
+        return_type: DeviceExternType::Void,
+        attrs: DeviceExternAttrs::default(),
+    }];
+
+    let ir = export_module_with_externs(
+        &ctx,
+        &module,
+        &externs,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect("plain int extern export succeeds");
+
+    // Plain i32 should have no signext/zeroext.
+    assert!(
+        ir.contains("declare void @plain_int_fn(i32)"),
+        "declaration should have plain i32 without attributes:\n{ir}"
+    );
+    assert!(
+        !ir.contains("signext") && !ir.contains("zeroext"),
+        "plain i32 should have no extension attributes:\n{ir}"
+    );
+}
+
+#[test]
+fn legacy_device_extern_rejects_small_integers_by_value() {
+    let mut ctx = Context::new();
+    let empty = ModuleOp::new(&mut ctx, "empty".try_into().unwrap());
+    let externs = [DeviceExternDecl {
+        export_name: "takes_small".to_string(),
+        param_types: vec![DeviceExternType::SignExtInteger(8)],
+        return_type: DeviceExternType::ZeroExtInteger(16),
+        attrs: DeviceExternAttrs::default(),
+    }];
+    let err = export_module_with_externs(
+        &ctx,
+        &empty,
+        &externs,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("legacy sub-32-bit by-value externs must fail cleanly");
+    assert!(
+        err.contains("CUDA 12 legacy") && err.contains("sub-32-bit"),
+        "{err}"
+    );
+}
+
+/// Build a module whose externs carry small params AND a small return, in
+/// both declare and call positions, so the emitted attribute placement can
+/// be checked against a real LLVM parser.
+fn small_type_extern_module(ctx: &mut Context) -> (ModuleOp, Vec<DeviceExternDecl>) {
+    let module = ModuleOp::new(ctx, "small_types_parse_gate".try_into().unwrap());
+    let module_block = module_top_block(ctx, &module);
+
+    let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
+    let i16_ty = IntegerType::get(ctx, 16, Signedness::Signless);
+    let i1_ty = IntegerType::get(ctx, 1, Signedness::Signless);
+    let half_ty = HalfType::get(ctx);
+    let void_ty = VoidType::get(ctx);
+
+    let take_small_ty = FuncType::get(
+        ctx,
+        void_ty.into(),
+        vec![i8_ty.into(), i16_ty.into(), i1_ty.into(), half_ty.into()],
+        false,
+    );
+    FuncOp::new(ctx, "take_small".try_into().unwrap(), take_small_ty)
+        .get_operation()
+        .insert_at_back(module_block, &*ctx);
+
+    let give_small_ty = FuncType::get(ctx, i8_ty.into(), vec![], false);
+    FuncOp::new(ctx, "give_small".try_into().unwrap(), give_small_ty)
+        .get_operation()
+        .insert_at_back(module_block, &*ctx);
+
+    let caller_ty = FuncType::get(
+        ctx,
+        void_ty.into(),
+        vec![i8_ty.into(), i16_ty.into(), i1_ty.into(), half_ty.into()],
+        false,
+    );
+    let caller = FuncOp::new(ctx, "caller".try_into().unwrap(), caller_ty);
+    let entry = caller.get_or_create_entry_block(ctx);
+    let arg0 = entry.deref(ctx).get_argument(0);
+    let arg1 = entry.deref(ctx).get_argument(1);
+    let arg2 = entry.deref(ctx).get_argument(2);
+    let arg3 = entry.deref(ctx).get_argument(3);
+    CallOp::new(
+        ctx,
+        CallOpCallable::Direct("take_small".try_into().unwrap()),
+        take_small_ty,
+        vec![arg0, arg1, arg2, arg3],
+    )
+    .get_operation()
+    .insert_at_back(entry, &*ctx);
+    CallOp::new(
+        ctx,
+        CallOpCallable::Direct("give_small".try_into().unwrap()),
+        give_small_ty,
+        vec![],
+    )
+    .get_operation()
+    .insert_at_back(entry, &*ctx);
+    ReturnOp::new(ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &*ctx);
+    caller.get_operation().insert_at_back(module_block, &*ctx);
+
+    let externs = vec![
+        DeviceExternDecl {
+            export_name: "take_small".to_string(),
+            param_types: vec![
+                DeviceExternType::SignExtInteger(8),
+                DeviceExternType::ZeroExtInteger(16),
+                DeviceExternType::ZeroExtInteger(1),
+                DeviceExternType::Float16,
+            ],
+            return_type: DeviceExternType::Void,
+            attrs: DeviceExternAttrs::default(),
+        },
+        DeviceExternDecl {
+            export_name: "give_small".to_string(),
+            param_types: vec![],
+            return_type: DeviceExternType::SignExtInteger(8),
+            attrs: DeviceExternAttrs::default(),
+        },
+    ];
+    (module, externs)
+}
+
+/// Parse gate: the emitted attribute placement (`i8 signext` in parameter
+/// position, `signext i8` in return position, for both `declare` and `call`)
+/// must be accepted by a real LLVM parser, not just string-matched.
+#[test]
+fn small_type_extern_module_parses_with_llvm_as() {
+    let mut ctx = Context::new();
+    let (module, externs) = small_type_extern_module(&mut ctx);
+    let ir = export_module_with_externs(
+        &ctx,
+        &module,
+        &externs,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect("modern small-type extern export succeeds");
+
+    // Belt-and-braces string checks before the external parse.
+    assert!(
+        ir.contains("declare void @take_small(i8 signext, i16 zeroext, i1 zeroext, half)"),
+        "{ir}"
+    );
+    assert!(ir.contains("declare signext i8 @give_small()"), "{ir}");
+    assert!(ir.contains("call signext i8 @give_small()"), "{ir}");
+
+    let Some(llvm_as) = ["llvm-as-22", "llvm-as-21", "llvm-as"]
+        .into_iter()
+        .find(|tool| {
+            std::process::Command::new(tool)
+                .arg("--version")
+                .output()
+                .is_ok_and(|out| out.status.success())
+        })
+    else {
+        eprintln!("skipping llvm-as parse gate: no llvm-as-22/llvm-as-21/llvm-as on PATH");
+        return;
+    };
+
+    let ll_path = std::env::temp_dir().join(format!(
+        "cuda_oxide_small_type_parse_gate_{}.ll",
+        std::process::id()
+    ));
+    std::fs::write(&ll_path, &ir).expect("write temp .ll");
+    let output = std::process::Command::new(llvm_as)
+        .arg("-o")
+        .arg("/dev/null")
+        .arg(&ll_path)
+        .output()
+        .expect("run llvm-as");
+    let stderr = String::from_utf8_lossy(&output.stderr).into_owned();
+    let _ = std::fs::remove_file(&ll_path);
+    assert!(
+        output.status.success(),
+        "{llvm_as} rejected the emitted module:\n{stderr}\n--- module ---\n{ir}"
+    );
+}
diff --git a/crates/llvm-export/tests/export_test/globals.rs b/crates/llvm-export/tests/export_test/globals.rs
new file mode 100644
index 0000000000..f79923cbcf
--- /dev/null
+++ b/crates/llvm-export/tests/export_test/globals.rs
@@ -0,0 +1,478 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use llvm_export::{
+    export::{
+        NvvmExportConfig, NvvmIrDialect, export_module_to_string,
+        export_module_to_string_with_config,
+    },
+    ops::{
+        GlobalInitializerRelocation, GlobalOp, GlobalOpExt, encode_global_initializer_relocations,
+    },
+    types::{ArrayType, StructLayout, StructType},
+};
+use pliron::{
+    builtin::{
+        ops::ModuleOp,
+        types::{IntegerType, Signedness},
+    },
+    context::Context,
+    op::Op,
+};
+
+use crate::common::module_top_block;
+
+/// Export a module holding one shared global, optionally labelled with the
+/// Rust path of the `static` it came from.
+fn export_shared_global_with_source_name(source_name: Option<&str>) -> String {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let array_ty = ArrayType::get(&ctx, i32_ty.to_handle(), 64);
+    let global = GlobalOp::new(
+        &mut ctx,
+        "__shared_mem_7".try_into().unwrap(),
+        array_ty.to_handle(),
+    );
+    global.set_address_space(&mut ctx, 3);
+    if let Some(source_name) = source_name {
+        global.set_shared_source_name(&mut ctx, source_name);
+    }
+    global.get_operation().insert_at_back(module_block, &ctx);
+
+    export_module_to_string(&ctx, &module).expect("export succeeds")
+}
+
+#[test]
+fn shared_global_source_name_is_exported_as_a_comment_above_the_definition() {
+    let ir = export_shared_global_with_source_name(Some("my_kernel::TILE"));
+
+    let definition_index = ir
+        .find("@__shared_mem_7 = addrspace(3) global")
+        .expect("module must declare the shared global");
+    let comment_index = ir
+        .find("; shared source: my_kernel::TILE")
+        .unwrap_or_else(|| panic!("shared global must name its Rust source:\n{ir}"));
+    assert!(
+        comment_index < definition_index,
+        "the source comment must precede the definition it describes:\n{ir}"
+    );
+}
+
+#[test]
+fn shared_global_without_a_source_name_exports_no_comment() {
+    let ir = export_shared_global_with_source_name(None);
+
+    assert!(
+        ir.contains("@__shared_mem_7 = addrspace(3) global"),
+        "module must declare the shared global:\n{ir}"
+    );
+    assert!(
+        !ir.contains("; shared source:"),
+        "an unlabelled global must not gain a comment:\n{ir}"
+    );
+}
+
+#[test]
+fn shared_global_source_name_cannot_escape_its_comment_line() {
+    // A newline in the label would end the comment and leave the remainder to
+    // be parsed as IR. Nothing in the current pipeline produces such a name,
+    // so this pins the exporter's own guarantee rather than a live bug.
+    let ir = export_shared_global_with_source_name(Some("EVIL\n@injected = addrspace(3) global"));
+
+    assert!(
+        ir.lines().all(|line| !line.starts_with("@injected")),
+        "a control character in the label must not open a new IR line:\n{ir}"
+    );
+    assert!(
+        ir.contains("; shared source: EVIL @injected = addrspace(3) global"),
+        "the label must survive on one line with controls flattened:\n{ir}"
+    );
+}
+
+#[test]
+fn nvvm_export_rejects_invalid_global_address_spaces() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let global = GlobalOp::new(
+        &mut ctx,
+        "thread_local_global".try_into().unwrap(),
+        i32_ty.to_handle(),
+    );
+    global.set_address_space(&mut ctx, 5);
+    global.get_operation().insert_at_back(module_block, &ctx);
+
+    let error = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("NVVM module-scope local-memory global must be rejected");
+    assert!(error.contains("unsupported address space 5"), "{error}");
+
+    // The ordinary LLVM/PTX exporter retains its prior behavior; this
+    // restriction is specifically part of the NVVM IR contract.
+    assert!(export_module_to_string(&ctx, &module).is_ok());
+}
+
+#[test]
+fn initialized_globals_export_exact_bytes() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "exact_global_bytes".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+
+    // 0x7fc01234 is a quiet f32 NaN with a non-canonical payload. Treating
+    // these bytes as an f32 before printing would collapse it to 0x7fc00000.
+    let nan_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
+    let nan = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "nan_payload".try_into().unwrap(),
+        nan_ty.into(),
+        4,
+    );
+    nan.set_address_space(&mut ctx, 1);
+    nan.set_initializer_hex(&mut ctx, "3412c07f");
+    nan.get_operation().insert_at_back(module_block, &ctx);
+
+    // Byte 0 is a u8, bytes 1..4 are zeroed repr(C) padding, and bytes 4..8
+    // are a little-endian u32. The exporter must not recompute those offsets.
+    let padded_ty = ArrayType::get(&ctx, i8_ty.into(), 8);
+    let padded = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "padded_struct".try_into().unwrap(),
+        padded_ty.into(),
+        4,
+    );
+    padded.set_address_space(&mut ctx, 1);
+    padded.set_initializer_hex(&mut ctx, "ab00000078563412");
+    padded.get_operation().insert_at_back(module_block, &ctx);
+
+    for config in [
+        NvvmExportConfig::new(NvvmIrDialect::Modern),
+        NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    ] {
+        let ir = export_module_to_string_with_config(&ctx, &module, &config)
+            .expect("byte-exact global export succeeds");
+        assert!(
+            ir.contains(r#"@nan_payload = addrspace(1) global [4 x i8] c"\34\12\C0\7F", align 4"#),
+            "NaN payload bytes changed:\n{ir}"
+        );
+        assert!(
+            ir.contains(
+                r#"@padded_struct = addrspace(1) global [8 x i8] c"\AB\00\00\00\78\56\34\12", align 4"#
+            ),
+            "repr(C) layout bytes changed:\n{ir}"
+        );
+    }
+}
+
+#[test]
+fn immutable_globals_export_the_constant_keyword() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "constant_keyword".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let table_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
+
+    // The compiler's own promoted table: marked never-written, so it must
+    // export as `constant`. That keyword is the whole point of the marker:
+    // it is what lets `opt` treat reads as invariant (deleting a copy into a
+    // stack slot) and what makes `llc` select `ld.global.nc`.
+    let promoted = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "promoted_table".try_into().unwrap(),
+        table_ty.into(),
+        4,
+    );
+    promoted.set_address_space(&mut ctx, 1);
+    promoted.set_initializer_hex(&mut ctx, "01020304");
+    promoted.mark_immutable(&mut ctx);
+    promoted.get_operation().insert_at_back(module_block, &ctx);
+
+    // An identically shaped global without the marker: the host may still
+    // write such storage by symbol, so it must keep `global`. Immutability is
+    // opt-in per global, never inferred from the shape of the initializer.
+    let plain = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "plain_static".try_into().unwrap(),
+        table_ty.into(),
+        4,
+    );
+    plain.set_address_space(&mut ctx, 1);
+    plain.set_initializer_hex(&mut ctx, "01020304");
+    plain.get_operation().insert_at_back(module_block, &ctx);
+
+    for config in [
+        NvvmExportConfig::new(NvvmIrDialect::Modern),
+        NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    ] {
+        let ir = export_module_to_string_with_config(&ctx, &module, &config)
+            .expect("immutable global export succeeds");
+        assert!(
+            ir.contains(
+                r#"@promoted_table = addrspace(1) constant [4 x i8] c"\01\02\03\04", align 4"#
+            ),
+            "promoted global lost the constant keyword:\n{ir}"
+        );
+        assert!(
+            ir.contains(r#"@plain_static = addrspace(1) global [4 x i8] c"\01\02\03\04", align 4"#),
+            "unmarked global must not become constant:\n{ir}"
+        );
+    }
+}
+
+#[test]
+fn initialized_global_exports_static_pointer_relocation() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "static_relocation".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+
+    // Insert the reference first. Module symbol indexing must make relocation
+    // resolution independent of textual global order.
+    let reference_ty = StructType::get_unnamed(&ctx, (vec![i64_ty.into()], StructLayout::Unpacked));
+    let reference = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "reference".try_into().unwrap(),
+        reference_ty.into(),
+        8,
+    );
+    reference.set_address_space(&mut ctx, 1);
+    reference.set_source_global_key(&mut ctx, "REFERENCE");
+    reference.set_initializer_hex(&mut ctx, "0000000000000000");
+    let encoded = encode_global_initializer_relocations(&[GlobalInitializerRelocation {
+        source_offset: 0,
+        width_bytes: 8,
+        target_address_space: 1,
+        target_addend: 0,
+        target_key: "TARGET".to_string(),
+    }]);
+    reference.set_initializer_relocations(&mut ctx, &encoded);
+    reference.get_operation().insert_at_back(module_block, &ctx);
+
+    let target_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
+    let target =
+        GlobalOp::new_with_alignment(&mut ctx, "target".try_into().unwrap(), target_ty.into(), 4);
+    target.set_address_space(&mut ctx, 1);
+    target.set_source_global_key(&mut ctx, "TARGET");
+    target.set_initializer_hex(&mut ctx, "78563412");
+    target.get_operation().insert_at_back(module_block, &ctx);
+
+    let modern = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect("modern relocated initializer export succeeds");
+    assert!(
+        modern.contains(
+            "@reference = addrspace(1) global { i64 } { i64 ptrtoint (ptr addrspacecast (ptr addrspace(1) @target to ptr) to i64) }, align 8"
+        ),
+        "{modern}"
+    );
+
+    let legacy = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect("legacy relocated initializer export succeeds");
+    assert!(
+        legacy.contains(
+            "@reference = addrspace(1) global { i64 } { i64 ptrtoint (i8* addrspacecast (i8 addrspace(1)* bitcast ([4 x i8] addrspace(1)* @target to i8 addrspace(1)*) to i8*) to i64) }, align 8"
+        ),
+        "{legacy}"
+    );
+}
+
+#[test]
+fn initialized_global_exports_unaligned_pointer_relocation_as_packed_storage() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "packed_static_relocation".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+
+    let literal_ty = ArrayType::get(&ctx, i8_ty.into(), 1);
+    let reference_ty = StructType::get_unnamed(
+        &ctx,
+        (vec![literal_ty.into(), i64_ty.into()], StructLayout::Packed),
+    );
+    let reference = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "packed_reference".try_into().unwrap(),
+        reference_ty.into(),
+        1,
+    );
+    reference.set_address_space(&mut ctx, 1);
+    reference.set_source_global_key(&mut ctx, "PACKED_REFERENCE");
+    reference.set_initializer_hex(&mut ctx, "7b0000000000000000");
+    let encoded = encode_global_initializer_relocations(&[GlobalInitializerRelocation {
+        source_offset: 1,
+        width_bytes: 8,
+        target_address_space: 1,
+        target_addend: 0,
+        target_key: "TARGET".to_string(),
+    }]);
+    reference.set_initializer_relocations(&mut ctx, &encoded);
+    reference.get_operation().insert_at_back(module_block, &ctx);
+
+    let target_ty = ArrayType::get(&ctx, i8_ty.into(), 4);
+    let target =
+        GlobalOp::new_with_alignment(&mut ctx, "target".try_into().unwrap(), target_ty.into(), 4);
+    target.set_address_space(&mut ctx, 1);
+    target.set_source_global_key(&mut ctx, "TARGET");
+    target.set_initializer_hex(&mut ctx, "78563412");
+    target.get_operation().insert_at_back(module_block, &ctx);
+
+    let modern = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect("modern packed relocated initializer export succeeds");
+    assert!(
+        modern.contains(
+            r#"@packed_reference = addrspace(1) global <{ [1 x i8], i64 }> <{ [1 x i8] c"\7B", i64 ptrtoint (ptr addrspacecast (ptr addrspace(1) @target to ptr) to i64) }>, align 1"#
+        ),
+        "{modern}"
+    );
+
+    let legacy = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect("legacy packed relocated initializer export succeeds");
+    assert!(
+        legacy.contains(
+            r#"@packed_reference = addrspace(1) global <{ [1 x i8], i64 }> <{ [1 x i8] c"\7B", i64 ptrtoint (i8* addrspacecast (i8 addrspace(1)* bitcast ([4 x i8] addrspace(1)* @target to i8 addrspace(1)*) to i8*) to i64) }>, align 1"#
+        ),
+        "{legacy}"
+    );
+}
+
+#[test]
+fn initialized_global_exports_multiple_relocations_and_addends() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "multiple_static_relocations".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+
+    let target_a_ty = ArrayType::get(&ctx, i8_ty.into(), 16);
+    let target_a = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "target_a".try_into().unwrap(),
+        target_a_ty.into(),
+        8,
+    );
+    target_a.set_address_space(&mut ctx, 1);
+    target_a.set_source_global_key(&mut ctx, "TARGET_A");
+    target_a.set_initializer_hex(&mut ctx, "000102030405060708090a0b0c0d0e0f");
+    target_a.get_operation().insert_at_back(module_block, &ctx);
+
+    let target_b_ty = ArrayType::get(&ctx, i8_ty.into(), 8);
+    let target_b = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "target_b".try_into().unwrap(),
+        target_b_ty.into(),
+        8,
+    );
+    target_b.set_address_space(&mut ctx, 4);
+    target_b.set_source_global_key(&mut ctx, "TARGET_B");
+    target_b.set_initializer_hex(&mut ctx, "1011121314151617");
+    target_b.get_operation().insert_at_back(module_block, &ctx);
+
+    let table_ty = StructType::get_unnamed(
+        &ctx,
+        (vec![i64_ty.into(), i64_ty.into()], StructLayout::Unpacked),
+    );
+    let table = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "reference_table".try_into().unwrap(),
+        table_ty.into(),
+        8,
+    );
+    table.set_address_space(&mut ctx, 1);
+    table.set_source_global_key(&mut ctx, "REFERENCE_TABLE");
+    table.set_initializer_hex(&mut ctx, "00000000000000000000000000000000");
+    let encoded = encode_global_initializer_relocations(&[
+        GlobalInitializerRelocation {
+            source_offset: 0,
+            width_bytes: 8,
+            target_address_space: 1,
+            target_addend: 4,
+            target_key: "TARGET_A".to_string(),
+        },
+        GlobalInitializerRelocation {
+            source_offset: 8,
+            width_bytes: 8,
+            target_address_space: 4,
+            target_addend: 0,
+            target_key: "TARGET_B".to_string(),
+        },
+    ]);
+    table.set_initializer_relocations(&mut ctx, &encoded);
+    table.get_operation().insert_at_back(module_block, &ctx);
+
+    for dialect in [NvvmIrDialect::Modern, NvvmIrDialect::LegacyLlvm7] {
+        let ir =
+            export_module_to_string_with_config(&ctx, &module, &NvvmExportConfig::new(dialect))
+                .expect("relocated initializer export succeeds");
+        assert!(
+            ir.contains("@reference_table = addrspace(1) global { i64, i64 }"),
+            "{ir}"
+        );
+        assert!(ir.contains("getelementptr (i8"), "{ir}");
+        assert!(ir.contains("@target_a"), "{ir}");
+        assert!(ir.contains("@target_b"), "{ir}");
+        assert!(!ir.contains("inttoptr"), "{ir}");
+    }
+}
+
+#[test]
+fn initialized_global_relocation_rejects_unknown_target_key() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "unknown_relocation_target".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let reference_ty = StructType::get_unnamed(&ctx, (vec![i64_ty.into()], StructLayout::Unpacked));
+    let reference = GlobalOp::new_with_alignment(
+        &mut ctx,
+        "reference".try_into().unwrap(),
+        reference_ty.into(),
+        8,
+    );
+    reference.set_address_space(&mut ctx, 1);
+    reference.set_source_global_key(&mut ctx, "REFERENCE");
+    reference.set_initializer_hex(&mut ctx, "0000000000000000");
+    let encoded = encode_global_initializer_relocations(&[GlobalInitializerRelocation {
+        source_offset: 0,
+        width_bytes: 8,
+        target_address_space: 1,
+        target_addend: 0,
+        target_key: "MISSING".to_string(),
+    }]);
+    reference.set_initializer_relocations(&mut ctx, &encoded);
+    reference.get_operation().insert_at_back(module_block, &ctx);
+
+    let error = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::Modern),
+    )
+    .expect_err("unknown relocation target must fail");
+    assert!(
+        error.contains("unknown rustc global key `MISSING`"),
+        "{error}"
+    );
+}
diff --git a/crates/llvm-export/tests/export_test/instructions.rs b/crates/llvm-export/tests/export_test/instructions.rs
new file mode 100644
index 0000000000..021ddd5364
--- /dev/null
+++ b/crates/llvm-export/tests/export_test/instructions.rs
@@ -0,0 +1,578 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use llvm_export::{
+    export::{
+        NvvmExportConfig, NvvmIrDialect, export_module_to_string,
+        export_module_to_string_with_config,
+    },
+    op_interfaces::CastOpInterface,
+    ops::{
+        AddrSpaceCastOp, AllocaOp, BitcastOp, ConstantOp, FuncOp, GepIndex, GetElementPtrOp,
+        InlineAsmOp, LoadOp, ReturnOp, SelectOp, StoreOp,
+    },
+    types::{FuncType, PointerType, VoidType},
+};
+use pliron::{
+    builtin::{
+        attributes::IntegerAttr,
+        ops::ModuleOp,
+        types::{FP32Type, IntegerType, Signedness},
+    },
+    common_traits::Verify,
+    context::Context,
+    linked_list::ContainsLinkedList,
+    op::Op,
+    utils::apint::APInt,
+};
+use std::num::NonZero;
+
+use crate::common::module_top_block;
+
+#[test]
+fn export_volatile_load_prints_keyword() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let ptr_ty = PointerType::get(&ctx, 0);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![ptr_ty.to_handle()], false);
+    let func = FuncOp::new(&mut ctx, "volatile_load_test".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let ptr = entry.deref(&ctx).get_argument(0);
+
+    let load = LoadOp::new(&mut ctx, ptr, i32_ty.to_handle());
+    llvm_export::ops::set_op_volatile(&mut ctx, load.get_operation(), true);
+    load.get_operation().insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
+    let line = ir
+        .lines()
+        .find(|line| line.contains("load volatile"))
+        .expect("volatile load line");
+
+    assert!(
+        line.trim_start().contains(" = load volatile i32, ptr "),
+        "volatile load keyword must appear immediately after load:\n{ir}"
+    );
+}
+
+#[test]
+fn export_volatile_store_prints_keyword() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let ptr_ty = PointerType::get(&ctx, 0);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(
+        &ctx,
+        void_ty.to_handle(),
+        vec![ptr_ty.to_handle(), i32_ty.to_handle()],
+        false,
+    );
+    let func = FuncOp::new(&mut ctx, "volatile_store_test".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let ptr = entry.deref(&ctx).get_argument(0);
+    let val = entry.deref(&ctx).get_argument(1);
+
+    let store = StoreOp::new(&mut ctx, val, ptr);
+    llvm_export::ops::set_op_volatile(&mut ctx, store.get_operation(), true);
+    store.get_operation().insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
+    let line = ir
+        .lines()
+        .find(|line| line.contains("store volatile"))
+        .expect("volatile store line");
+
+    assert!(
+        line.trim_start().starts_with("store volatile i32 "),
+        "volatile store keyword must appear immediately after store:\n{ir}"
+    );
+}
+
+#[test]
+fn legacy_export_uses_one_canonical_pointer_with_multiple_typed_views() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "legacy_views".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let ptr_ty = PointerType::get(&ctx, 0);
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let f32_ty = FP32Type::get(&ctx);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
+    let func = FuncOp::new(&mut ctx, "multiple_views".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let pointer = entry.deref(&ctx).get_argument(0);
+
+    LoadOp::new(&mut ctx, pointer, i32_ty.into())
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    LoadOp::new(&mut ctx, pointer, f32_ty.into())
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    LoadOp::new(&mut ctx, pointer, i8_ty.into())
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7);
+    let ir = export_module_to_string_with_config(&ctx, &module, &config)
+        .expect("legacy export succeeds");
+
+    assert!(ir.contains("define void @multiple_views(i8* %v0)"), "{ir}");
+    assert!(ir.contains("bitcast i8* %v0 to i32*"), "{ir}");
+    assert!(ir.contains("load i32, i32*"), "{ir}");
+    assert!(ir.contains("bitcast i8* %v0 to float*"), "{ir}");
+    assert!(ir.contains("load float, float*"), "{ir}");
+    assert!(ir.contains("load i8, i8* %v0"), "{ir}");
+    assert!(!ir.contains("bitcast i8* %v0 to i8*"), "{ir}");
+    assert!(
+        !ir.split(|c: char| !c.is_ascii_alphanumeric())
+            .any(|t| t == "ptr")
+    );
+}
+
+#[test]
+fn legacy_alloca_rejects_a_non_default_result_address_space() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "invalid_alloca_as".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "invalid_alloca".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+
+    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
+    let one = ConstantOp::new(&mut ctx, one_attr.into());
+    let one_value = one.get_operation().deref(&ctx).get_result(0);
+    one.get_operation().insert_at_back(entry, &ctx);
+    let alloca = AllocaOp::new(&mut ctx, i32_ty.into(), one_value);
+    let alloca_result = alloca.get_operation().deref(&ctx).get_result(0);
+    let shared_pointer = PointerType::get(&ctx, 3);
+    alloca_result.set_type(&ctx, shared_pointer.into());
+    alloca.get_operation().insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    module
+        .get_operation()
+        .deref(&ctx)
+        .verify(&ctx)
+        .expect("upstream verification currently does not enforce alloca result AS0");
+    let error = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("legacy export must reject an alloca address-space mismatch");
+    assert!(
+        error.contains("alloca result uses address space 3"),
+        "{error}"
+    );
+}
+
+#[test]
+fn legacy_gep_rejects_a_result_address_space_different_from_its_base() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "invalid_gep_as".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let global_pointer = PointerType::get(&ctx, 1);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![global_pointer.into()], false);
+    let func = FuncOp::new(&mut ctx, "invalid_gep".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let base = entry.deref(&ctx).get_argument(0);
+    let gep = GetElementPtrOp::new(&mut ctx, base, vec![GepIndex::Constant(0)], i32_ty.into());
+    let gep_result = gep.get_operation().deref(&ctx).get_result(0);
+    let shared_pointer = PointerType::get(&ctx, 3);
+    gep_result.set_type(&ctx, shared_pointer.into());
+    gep.get_operation().insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    module
+        .get_operation()
+        .deref(&ctx)
+        .verify(&ctx)
+        .expect("upstream verification currently does not enforce GEP result/base AS equality");
+    let error = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect_err("legacy export must reject a GEP address-space mismatch");
+    assert!(
+        error.contains("GEP result address-space mismatch: base is 1, result is 3"),
+        "{error}"
+    );
+}
+
+#[test]
+fn gep_inbounds_marker_controls_exported_pointer_semantics() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "gep_semantics".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let pointer = PointerType::get(&ctx, 0);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![pointer.into()], false);
+    let func = FuncOp::new(&mut ctx, "offsets".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let base = entry.deref(&ctx).get_argument(0);
+
+    let ordinary = GetElementPtrOp::new(&mut ctx, base, vec![GepIndex::Constant(1)], i32_ty.into());
+    ordinary.get_operation().insert_at_back(entry, &ctx);
+
+    let wrapping = GetElementPtrOp::new(&mut ctx, base, vec![GepIndex::Constant(2)], i32_ty.into());
+    llvm_export::ops::set_gep_inbounds(&mut ctx, wrapping.get_operation(), false);
+    wrapping.get_operation().insert_at_back(entry, &ctx);
+
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string(&ctx, &module).expect("GEP export succeeds");
+    let gep_lines: Vec<_> = ir
+        .lines()
+        .filter(|line| line.contains("getelementptr"))
+        .collect();
+    assert_eq!(gep_lines.len(), 2, "{ir}");
+    assert!(gep_lines[0].contains("getelementptr inbounds"), "{ir}");
+    assert!(
+        gep_lines[1].contains("getelementptr i32")
+            && !gep_lines[1].contains("getelementptr inbounds"),
+        "{ir}"
+    );
+}
+
+#[test]
+fn legacy_pointer_select_keeps_one_canonical_type() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "legacy_pointer_select".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let ptr_ty = PointerType::get(&ctx, 0);
+    let func_ty = FuncType::get(
+        &ctx,
+        ptr_ty.into(),
+        vec![i1_ty.into(), ptr_ty.into(), ptr_ty.into()],
+        false,
+    );
+    let func = FuncOp::new(&mut ctx, "choose_pointer".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let condition = entry.deref(&ctx).get_argument(0);
+    let if_true = entry.deref(&ctx).get_argument(1);
+    let if_false = entry.deref(&ctx).get_argument(2);
+    let select = SelectOp::new(&mut ctx, condition, if_true, if_false);
+    let selected = select.get_operation().deref(&ctx).get_result(0);
+    select.get_operation().insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, Some(selected))
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect("legacy pointer select export succeeds");
+    assert!(
+        ir.contains("select i1 %v0, i8* %v1, i8* %v2"),
+        "pointer select must use the canonical byte-pointer type:\n{ir}"
+    );
+    assert!(ir.contains("ret i8*"), "{ir}");
+}
+
+#[test]
+fn pointer_bitcast_cannot_cross_address_spaces_in_either_nvvm_dialect() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "invalid_pointer_bitcast".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let global_pointer = PointerType::get(&ctx, 1);
+    let shared_pointer = PointerType::get(&ctx, 3);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![global_pointer.into()], false);
+    let func = FuncOp::new(&mut ctx, "invalid_cast".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let input = entry.deref(&ctx).get_argument(0);
+    BitcastOp::new(&mut ctx, input, shared_pointer.into())
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    module
+        .get_operation()
+        .deref(&ctx)
+        .verify(&ctx)
+        .expect("upstream bitcast verification currently does not enforce pointer AS equality");
+    for dialect in [NvvmIrDialect::LegacyLlvm7, NvvmIrDialect::Modern] {
+        let error =
+            export_module_to_string_with_config(&ctx, &module, &NvvmExportConfig::new(dialect))
+                .expect_err("a cross-address-space pointer bitcast must be rejected");
+        assert!(
+            error.contains("pointer bitcast cannot cross address spaces 1 -> 3"),
+            "{dialect:?}: {error}"
+        );
+    }
+}
+
+#[test]
+fn addrspacecast_must_change_address_spaces_in_either_nvvm_dialect() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "invalid_addrspacecast".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let shared_pointer = PointerType::get(&ctx, 3);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![shared_pointer.into()], false);
+    let func = FuncOp::new(&mut ctx, "invalid_cast".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let input = entry.deref(&ctx).get_argument(0);
+    AddrSpaceCastOp::new(&mut ctx, input, shared_pointer.into())
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    module
+        .get_operation()
+        .deref(&ctx)
+        .verify(&ctx)
+        .expect("upstream addrspacecast verification currently permits equal address spaces");
+    for dialect in [NvvmIrDialect::LegacyLlvm7, NvvmIrDialect::Modern] {
+        let error =
+            export_module_to_string_with_config(&ctx, &module, &NvvmExportConfig::new(dialect))
+                .expect_err("addrspacecast must not encode a no-op address-space conversion");
+        assert!(
+            error.contains(
+                "addrspacecast must change address spaces; source and result are both address space 3"
+            ),
+            "{dialect:?}: {error}"
+        );
+    }
+}
+
+#[test]
+fn legacy_pointer_slot_is_recursively_canonical() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "legacy_pointer_slot".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let ptr_ty = PointerType::get(&ctx, 0);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
+    let func = FuncOp::new(&mut ctx, "pointer_slot".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let incoming = entry.deref(&ctx).get_argument(0);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let one_attr = IntegerAttr::new(i32_ty, APInt::from_u32(1, NonZero::new(32).unwrap()));
+    let one = ConstantOp::new(&mut ctx, one_attr.into());
+    let one_value = one.get_operation().deref(&ctx).get_result(0);
+    one.get_operation().insert_at_back(entry, &ctx);
+
+    let slot = AllocaOp::new(&mut ctx, ptr_ty.into(), one_value);
+    let slot_value = slot.get_operation().deref(&ctx).get_result(0);
+    slot.get_operation().insert_at_back(entry, &ctx);
+    StoreOp::new(&mut ctx, incoming, slot_value)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    LoadOp::new(&mut ctx, slot_value, ptr_ty.into())
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string_with_config(
+        &ctx,
+        &module,
+        &NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7),
+    )
+    .expect("legacy pointer-slot export succeeds");
+    assert!(ir.contains("alloca i8*"), "{ir}");
+    assert!(ir.contains("bitcast i8**"), "{ir}");
+    assert!(ir.matches("to i8**").count() >= 2, "{ir}");
+    assert!(ir.contains("store i8* %v0, i8**"), "{ir}");
+    assert!(ir.contains("load i8*, i8**"), "{ir}");
+}
+
+#[test]
+fn export_inline_asm_respects_sideeffect_marker() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "has_inline_asm".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+
+    let default_asm = InlineAsmOp::new(&mut ctx, void_ty.into(), vec![], "bar.sync 0;", "", false);
+    default_asm.get_operation().insert_at_back(entry, &ctx);
+
+    let register_only_asm = InlineAsmOp::new(&mut ctx, void_ty.into(), vec![], "nop;", "", true);
+    llvm_export::ops::set_inline_asm_sideeffect(&mut ctx, register_only_asm.get_operation(), false);
+    register_only_asm
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
+
+    assert!(
+        ir.contains("call void asm sideeffect \"bar.sync 0;\", \"\"()"),
+        "inline asm without an explicit marker should remain conservative:\n{ir}"
+    );
+    assert!(
+        ir.contains("call void asm \"nop;\", \"\"() #0"),
+        "inline asm marked sideeffect=false should omit the keyword while preserving convergent:\n{ir}"
+    );
+    assert!(
+        ir.contains("attributes #0 = { convergent }"),
+        "convergent inline asm must emit the convergent attr group:\n{ir}"
+    );
+}
+
+#[test]
+fn export_inline_asm_escapes_llvm_string_literals() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(
+        &mut ctx,
+        "has_escaped_inline_asm".try_into().unwrap(),
+        func_ty,
+    );
+    let entry = func.get_or_create_entry_block(&mut ctx);
+
+    let asm = InlineAsmOp::new(
+        &mut ctx,
+        void_ty.into(),
+        vec![],
+        "mov.u32 $0, %laneid;\n// \"quoted\" \\22",
+        "~{memory}\\raw",
+        false,
+    );
+    asm.get_operation().insert_at_back(entry, &ctx);
+
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
+
+    assert!(
+        ir.contains(
+            "call void asm sideeffect \"mov.u32 $0, %laneid;\\0A// \\22quoted\\22 \\5C22\", \"~{memory}\\5Craw\"()"
+        ),
+        "inline asm template and constraints must be escaped as LLVM string literals:\n{ir}"
+    );
+}
+
+/// A float binop carrying `FastmathFlags` must export with the matching LLVM
+/// fast-math keyword (`fast` for the all-bits set), while a float binop with no
+/// flags must export with none. Regression guard: the textual exporter
+/// previously dropped fast-math flags entirely, making the `f*_fast` intrinsic
+/// lowering inert end to end.
+#[test]
+fn export_emits_fast_math_flags_only_on_flagged_float_ops() {
+    use llvm_export::attributes::FastmathFlags;
+    use llvm_export::op_interfaces::{BinArithOp, FloatBinArithOpWithFastMathFlags};
+    use llvm_export::ops::{FAddOp, FMulOp};
+    use pliron::builtin::types::FP32Type;
+
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+
+    let f32_ty = FP32Type::get(&ctx);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(
+        &ctx,
+        void_ty.to_handle(),
+        vec![f32_ty.into(), f32_ty.into()],
+        false,
+    );
+    let func = FuncOp::new(&mut ctx, "fast_math".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let a = entry.deref(&ctx).get_argument(0);
+    let b = entry.deref(&ctx).get_argument(1);
+
+    // fadd with the full fast-math set.
+    let fadd = FAddOp::new_with_fast_math_flags(&mut ctx, a, b, FastmathFlags::FAST.into());
+    fadd.get_operation().insert_at_back(entry, &ctx);
+    // fmul with no flags: must stay flag-free.
+    let fmul = FMulOp::new(&mut ctx, a, b);
+    fmul.get_operation().insert_at_back(entry, &ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
+
+    assert!(
+        ir.contains("fadd fast float"),
+        "fast-math fadd must export the `fast` keyword:\n{ir}"
+    );
+    let fmul_line = ir
+        .lines()
+        .find(|line| line.contains("fmul"))
+        .expect("exported fmul line");
+    assert!(
+        !fmul_line.contains("fast"),
+        "a float binop with no fast-math flags must not gain them:\n{ir}"
+    );
+}
diff --git a/crates/llvm-export/tests/export_test/kernels_and_roots.rs b/crates/llvm-export/tests/export_test/kernels_and_roots.rs
new file mode 100644
index 0000000000..e6490122cf
--- /dev/null
+++ b/crates/llvm-export/tests/export_test/kernels_and_roots.rs
@@ -0,0 +1,283 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use llvm_export::{
+    export::{
+        DeviceExternDecl, NvvmExportConfig, NvvmIrDialect, PtxExportConfig,
+        export_module_to_string, export_module_to_string_with_config,
+        export_module_with_externs_and_roots,
+    },
+    ops::{FuncOp, GlobalOp, GlobalOpExt, ReturnOp},
+    types::{FuncType, PointerType, VoidType},
+};
+use pliron::{
+    basic_block::BasicBlock,
+    builtin::{
+        attributes::StringAttr,
+        ops::ModuleOp,
+        types::{IntegerType, Signedness},
+    },
+    context::{Context, Ptr},
+    identifier::Identifier,
+    op::Op,
+};
+
+use crate::common::module_top_block;
+
+#[test]
+fn legacy_kernel_metadata_uses_typed_function_references() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "legacy_metadata".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let ptr_ty = PointerType::get(&ctx, 0);
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.into(), vec![ptr_ty.into()], false);
+    let func = FuncOp::new(&mut ctx, "metadata_kernel".try_into().unwrap(), func_ty);
+    func.get_operation().deref_mut(&ctx).attributes.set(
+        "gpu_kernel".try_into().unwrap(),
+        StringAttr::new("true".into()),
+    );
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7);
+    let ir = export_module_to_string_with_config(&ctx, &module, &config)
+        .expect("legacy metadata export succeeds");
+    assert!(
+        ir.contains(
+            "@llvm.used = appending global [1 x i8*] [i8* bitcast (void (i8*)* @metadata_kernel to i8*)]"
+        ),
+        "{ir}"
+    );
+    assert!(
+        ir.contains("!{void (i8*)* @metadata_kernel, !\"kernel\", i32 1}"),
+        "{ir}"
+    );
+}
+
+#[test]
+fn llvm_used_roots_only_explicitly_retained_globals() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "retained_globals".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+
+    let retained = GlobalOp::new(&mut ctx, "IKET_META".try_into().unwrap(), i32_ty.into());
+    retained.set_address_space(&mut ctx, 1);
+    retained.mark_retained(&mut ctx);
+    retained.get_operation().insert_at_back(module_block, &ctx);
+
+    let ordinary = GlobalOp::new(&mut ctx, "ORDINARY".try_into().unwrap(), i32_ty.into());
+    ordinary.set_address_space(&mut ctx, 1);
+    ordinary.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string_with_config(&ctx, &module, &PtxExportConfig)
+        .expect("retained global export succeeds");
+    assert!(
+        ir.contains(
+            "@llvm.used = appending global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @IKET_META to ptr)], section \"llvm.metadata\""
+        ),
+        "{ir}"
+    );
+    assert!(!ir.contains("@ORDINARY to ptr"), "{ir}");
+}
+
+#[test]
+fn legacy_llvm_used_roots_retained_address_space_global() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "legacy_retained_global".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let retained = GlobalOp::new(&mut ctx, "IKET_META".try_into().unwrap(), i32_ty.into());
+    retained.set_address_space(&mut ctx, 1);
+    retained.mark_retained(&mut ctx);
+    retained.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = NvvmExportConfig::new(NvvmIrDialect::LegacyLlvm7);
+    let ir = export_module_to_string_with_config(&ctx, &module, &config)
+        .expect("legacy retained global export succeeds");
+    assert!(
+        ir.contains(
+            "@llvm.used = appending global [1 x i8*] [i8* addrspacecast (i32 addrspace(1)* @IKET_META to i8*)], section \"llvm.metadata\""
+        ),
+        "{ir}"
+    );
+}
+
+#[test]
+fn ptx_export_records_kernel_roots_for_internalization() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "ptx_roots".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let global = GlobalOp::new(&mut ctx, "COEFFS".try_into().unwrap(), i32_ty.into());
+    global.set_address_space(&mut ctx, 4);
+    global.get_operation().insert_at_back(module_block, &ctx);
+    let func_ty = FuncType::get(&ctx, VoidType::get(&ctx).into(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "entry_kernel".try_into().unwrap(), func_ty);
+    func.get_operation().deref_mut(&ctx).attributes.set(
+        "gpu_kernel".try_into().unwrap(),
+        StringAttr::new("true".into()),
+    );
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let exported = export_module_with_externs_and_roots::<DeviceExternDecl>(
+        &ctx,
+        &module,
+        &[],
+        &PtxExportConfig,
+    )
+    .expect("PTX export succeeds");
+    let ir = exported.llvm_ir;
+    assert!(
+        ir.contains(
+            "@llvm.used = appending global [1 x ptr] [ptr @entry_kernel], section \"llvm.metadata\""
+        ),
+        "{ir}"
+    );
+    assert_eq!(exported.public_symbols, ["COEFFS", "entry_kernel"]);
+}
+
+#[test]
+fn ptx_export_records_standalone_device_function_roots_for_internalization() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "ptx_device_root".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    let func_ty = FuncType::get(&ctx, VoidType::get(&ctx).into(), vec![], false);
+    let prefixed_name = format!(
+        "{}standalone_export",
+        reserved_oxide_symbols::LEGACY_DEVICE_PREFIX
+    );
+    let func = FuncOp::new(
+        &mut ctx,
+        prefixed_name.as_str().try_into().unwrap(),
+        func_ty,
+    );
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let exported = export_module_with_externs_and_roots::<DeviceExternDecl>(
+        &ctx,
+        &module,
+        &[],
+        &PtxExportConfig,
+    )
+    .expect("standalone PTX export succeeds");
+    assert_eq!(exported.public_symbols, ["standalone_export"]);
+    assert!(
+        exported.llvm_ir.contains(
+            "@llvm.used = appending global [1 x ptr] [ptr @standalone_export], section \"llvm.metadata\""
+        ),
+        "{}",
+        exported.llvm_ir
+    );
+}
+
+/// Builds a `void` function taking pointer parameters in the given address
+/// spaces, with an empty body, optionally carrying the `gpu_kernel` marker
+/// the exporter uses to distinguish an entry from a device function.
+fn pointer_param_function(
+    ctx: &mut Context,
+    module_block: Ptr<BasicBlock>,
+    name: &str,
+    address_spaces: &[u32],
+    is_kernel: bool,
+) {
+    let params: Vec<_> = address_spaces
+        .iter()
+        .map(|space| PointerType::get(ctx, *space).into())
+        .collect();
+    let void_ty = VoidType::get(ctx);
+    let func_ty = FuncType::get(ctx, void_ty.into(), params, false);
+    let func = FuncOp::new(ctx, name.try_into().unwrap(), func_ty);
+    if is_kernel {
+        let kernel_key: Identifier = "gpu_kernel".try_into().unwrap();
+        func.get_operation()
+            .deref_mut(ctx)
+            .attributes
+            .set(kernel_key, StringAttr::new("true".to_string()));
+    }
+    let entry = func.get_or_create_entry_block(ctx);
+    ReturnOp::new(ctx, None)
+        .get_operation()
+        .insert_at_back(entry, ctx);
+    func.get_operation().insert_at_back(module_block, ctx);
+}
+
+/// A kernel receives its parameters in `.param` space from the host, which
+/// holds no shared-memory address to pass. The exporter must refuse the
+/// signature instead of emitting `.ptr .shared`, which ptxas accepts but the
+/// driver rejects at module load, taking every kernel in the module down.
+#[test]
+fn kernel_rejects_a_shared_memory_pointer_parameter() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "kernel_shared_param".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    pointer_param_function(&mut ctx, module_block, "shared_param", &[0, 3], true);
+
+    let error = export_module_to_string(&ctx, &module)
+        .expect_err("export must refuse a kernel parameter in shared memory");
+    assert!(
+        error.contains(
+            "kernel `@shared_param` parameter 1 is a pointer into shared memory (address space 3)"
+        ),
+        "{error}"
+    );
+}
+
+/// Local memory is per-thread, so the host has no address in it to pass
+/// either; the exporter refuses it on the same grounds as shared.
+#[test]
+fn kernel_rejects_a_local_memory_pointer_parameter() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "kernel_local_param".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    pointer_param_function(&mut ctx, module_block, "local_param", &[5], true);
+
+    let error = export_module_to_string(&ctx, &module)
+        .expect_err("export must refuse a kernel parameter in local memory");
+    assert!(
+        error.contains(
+            "kernel `@local_param` parameter 0 is a pointer into local memory (address space 5)"
+        ),
+        "{error}"
+    );
+}
+
+/// The refusal is scoped to what the host cannot supply. Generic, global,
+/// and constant pointer parameters are host-addressable and stay accepted on
+/// kernels, and a device (non-kernel) function may carry any state space on
+/// its parameters, shared included.
+#[test]
+fn kernel_keeps_host_addressable_pointer_parameters_and_device_functions_keep_shared() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "kernel_allowed_params".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+    pointer_param_function(&mut ctx, module_block, "allowed_param", &[0, 1, 4], true);
+    pointer_param_function(&mut ctx, module_block, "device_shared", &[3], false);
+
+    let ir = export_module_to_string(&ctx, &module)
+        .expect("generic/global/constant kernel parameters and device shared must export");
+    assert!(
+        ir.contains(
+            "define ptx_kernel void @allowed_param(ptr %v0, ptr addrspace(1) %v1, ptr addrspace(4) %v2)"
+        ),
+        "{ir}"
+    );
+    assert!(
+        ir.contains("define void @device_shared(ptr addrspace(3) %v0)"),
+        "{ir}"
+    );
+}
diff --git a/crates/llvm-export/tests/export_test/main.rs b/crates/llvm-export/tests/export_test/main.rs
new file mode 100644
index 0000000000..9b77233528
--- /dev/null
+++ b/crates/llvm-export/tests/export_test/main.rs
@@ -0,0 +1,14 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+mod calls_and_addresses;
+mod common;
+mod control_flow;
+mod debug_info;
+mod device_externs;
+mod globals;
+mod instructions;
+mod kernels_and_roots;
+mod metadata;
diff --git a/crates/llvm-export/tests/export_test/metadata.rs b/crates/llvm-export/tests/export_test/metadata.rs
new file mode 100644
index 0000000000..0330a9f420
--- /dev/null
+++ b/crates/llvm-export/tests/export_test/metadata.rs
@@ -0,0 +1,231 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use llvm_export::{
+    export::{
+        DebugKind, NvvmExportConfig, PtxExportConfig, export_module_to_string,
+        export_module_to_string_with_config,
+    },
+    ops::{FuncOp, ReturnOp},
+    types::{FuncType, VoidType},
+};
+use pliron::{
+    builtin::{
+        attributes::{IntegerAttr, StringAttr},
+        ops::ModuleOp,
+        types::{IntegerType, Signedness},
+    },
+    context::Context,
+    identifier::Identifier,
+    linked_list::ContainsLinkedList,
+    location::Located,
+    op::Op,
+    utils::apint::APInt,
+};
+use std::num::NonZero;
+
+use crate::common::{DebugConfig, module_top_block, src_location};
+
+#[test]
+fn nvvm_metadata_version_uses_next_allocated_metadata_id() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "bounded_kernel".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let width = NonZero::new(32).unwrap();
+    let max_threads = IntegerAttr::new(u32_ty, APInt::from_u32(256, width));
+    let min_blocks = IntegerAttr::new(u32_ty, APInt::from_u32(2, width));
+
+    {
+        let attrs = &mut func.get_operation().deref_mut(&ctx).attributes;
+        attrs.set(
+            Identifier::try_from("gpu_kernel").unwrap(),
+            StringAttr::new("true".into()),
+        );
+        attrs.set(Identifier::try_from("maxntid").unwrap(), max_threads);
+        attrs.set(Identifier::try_from("minctasm").unwrap(), min_blocks);
+    }
+
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string_with_config(&ctx, &module, &NvvmExportConfig::default())
+        .expect("NVVM export succeeds");
+
+    assert!(
+        ir.contains("!0 = !{ptr @bounded_kernel, !\"kernel\", i32 1}"),
+        "a launch-bounded kernel still needs its kernel annotation:\n{ir}"
+    );
+    assert!(
+        ir.contains("!nvvm.annotations = !{!0, !1, !2, !3, !4}"),
+        "kernel identity plus launch-bounds annotations should occupy !0..!4:\n{ir}"
+    );
+    assert!(
+        ir.contains("!nvvmir.version = !{!5}\n!5 = !{i32 2, i32 0, i32 3, i32 2}"),
+        "version metadata should use the next allocated ID:\n{ir}"
+    );
+}
+
+#[test]
+fn export_alwaysinline_function_attribute_uses_llvm_define_syntax() {
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "inline_helper".try_into().unwrap(), func_ty);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    ReturnOp::new(&mut ctx, None)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+
+    let key: pliron::identifier::Identifier = "alwaysinline".try_into().unwrap();
+    func.get_operation()
+        .deref_mut(&ctx)
+        .attributes
+        .set(key, StringAttr::new("true".to_string()));
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let ir = export_module_to_string(&ctx, &module).expect("export succeeds");
+    let define_line = ir
+        .lines()
+        .find(|line| line.starts_with("define void @inline_helper("))
+        .expect("inline helper definition");
+    assert_eq!(
+        define_line, "define void @inline_helper() alwaysinline #0 {",
+        "`alwaysinline` must be emitted after the parameter list, before attr group #0:\n{ir}"
+    );
+    assert!(
+        ir.contains("attributes #0 = { convergent }"),
+        "convergent attribute group must still be emitted:\n{ir}"
+    );
+}
+
+#[test]
+fn export_alwaysinline_coexists_with_debug_scope() {
+    // alwaysinline and the !dbg scope are emitted on the same define line and
+    // must not crowd each other out. This guards the 4-way emission: a future
+    // change that drops either one when both are present fails here.
+    let mut ctx = Context::new();
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_block = module_top_block(&mut ctx, &module);
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "inline_helper".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 7, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let ret = ReturnOp::new(&mut ctx, None);
+    let ret_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 8, 5);
+    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
+    ret.get_operation().insert_at_back(entry, &ctx);
+
+    let key: pliron::identifier::Identifier = "alwaysinline".try_into().unwrap();
+    func.get_operation()
+        .deref_mut(&ctx)
+        .attributes
+        .set(key, StringAttr::new("true".to_string()));
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: PtxExportConfig,
+        debug_kind: DebugKind::LineTables,
+    };
+    let ir =
+        export_module_to_string_with_config(&ctx, &module, &config).expect("debug export succeeds");
+    let define_line = ir
+        .lines()
+        .find(|line| line.starts_with("define void @inline_helper("))
+        .expect("inline helper definition");
+    assert!(
+        define_line.contains("alwaysinline"),
+        "alwaysinline must survive when debug info is on:\n{ir}"
+    );
+    assert!(
+        define_line.contains("!dbg !"),
+        "!dbg scope must survive when alwaysinline is present:\n{ir}"
+    );
+}
+
+#[test]
+fn debug_metadata_shares_allocator_with_nvvm_metadata() {
+    let mut ctx = Context::new();
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = {
+        let region = module_region.deref(&ctx);
+        region.iter(&ctx).next().unwrap()
+    };
+
+    let void_ty = VoidType::get(&ctx);
+    let func_ty = FuncType::get(&ctx, void_ty.to_handle(), vec![], false);
+    let func = FuncOp::new(&mut ctx, "debug_kernel".try_into().unwrap(), func_ty);
+    let func_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 10, 1);
+    func.get_operation().deref_mut(&ctx).set_loc(func_loc);
+
+    {
+        let attrs = &mut func.get_operation().deref_mut(&ctx).attributes;
+        attrs.set(
+            Identifier::try_from("gpu_kernel").unwrap(),
+            StringAttr::new("true".into()),
+        );
+    }
+
+    let entry = func.get_or_create_entry_block(&mut ctx);
+    let ret = ReturnOp::new(&mut ctx, None);
+    let ret_loc = src_location(&mut ctx, "/tmp/cuda-oxide/tests/kernel.rs", 11, 5);
+    ret.get_operation().deref_mut(&ctx).set_loc(ret_loc);
+    ret.get_operation().insert_at_back(entry, &ctx);
+
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    let config = DebugConfig {
+        inner: NvvmExportConfig::default(),
+        debug_kind: DebugKind::LineTables,
+    };
+    let ir = export_module_to_string_with_config(&ctx, &module, &config)
+        .expect("debug NVVM export succeeds");
+
+    assert!(
+        ir.contains("!0 = !DIFile(filename: \"kernel.rs\", directory: \"/tmp/cuda-oxide/tests\")"),
+        "debug file node should take the first metadata ID:\n{ir}"
+    );
+    assert!(
+        ir.contains("!4 = !DILocation(line: 11, column: 5, scope: !3)"),
+        "instruction location should be allocated before NVVM metadata:\n{ir}"
+    );
+    assert!(
+        ir.contains("!5 = !{ptr @debug_kernel, !\"kernel\", i32 1}"),
+        "NVVM annotations should continue after debug metadata:\n{ir}"
+    );
+    assert!(
+        ir.contains("!nvvm.annotations = !{!5}"),
+        "named NVVM metadata should reference its allocated node:\n{ir}"
+    );
+    assert!(
+        ir.contains("!nvvmir.version = !{!6}\n!6 = !{i32 2, i32 0, i32 3, i32 2}"),
+        "NVVM version should use the next free metadata ID:\n{ir}"
+    );
+    assert!(
+        ir.contains("!llvm.module.flags = !{!7, !8}"),
+        "debug module flags should also use the shared allocator:\n{ir}"
+    );
+}
diff --git a/crates/mir-importer/src/translator/rvalue.rs b/crates/mir-importer/src/translator/rvalue.rs
deleted file mode 100644
index 6cd6feb596..0000000000
--- a/crates/mir-importer/src/translator/rvalue.rs
+++ /dev/null
@@ -1,15707 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-//! Rvalue translation: MIR expressions → `dialect-mir` operations.
-//!
-//! Translates the right-hand side of MIR assignments into `dialect-mir` ops.
-//!
-//! # Supported Rvalues
-//!
-//! | MIR Rvalue          | `dialect-mir` Op                                      |
-//! |---------------------|-------------------------------------------------------|
-//! | `BinaryOp(+,-,*,/)` | `mir.add`, `mir.sub`, `mir.mul`, `mir.div`            |
-//! | `BinaryOp(<,<=,>)`  | `mir.lt`, `mir.le`, `mir.gt`, etc.                    |
-//! | `CheckedBinaryOp`   | `mir.checked_add`, etc. (returns tuple)               |
-//! | `UnaryOp(Not,Neg)`  | `mir.not`, `mir.neg`                                  |
-//! | `Cast`              | `mir.cast`                                            |
-//! | `Ref`               | Slot pointer for locals; `mir.ref` for SSA values     |
-//! | `Use(operand)`      | `mir.load` of the source slot (no op for constants)   |
-//! | `Aggregate`         | `mir.construct_tuple/struct/enum/array`               |
-//! | `Repeat`            | `mir.construct_array` (array repeat syntax)           |
-//! | `CopyForDeref`      | Same place-read lowering as `Copy`/`Move`             |
-//!
-//! # Key Functions
-//!
-//! - [`translate_rvalue`]: Main entry point for rvalue translation
-//! - [`translate_operand`]: Translates operands (Copy/Move/Constant/RuntimeChecks)
-//! - [`translate_place`]: Translates places to their SSA values (handles ghost locals)
-//! - `translate_constant`: Translates MIR constants to `dialect-mir`
-//! - `create_ghost_enum_default`: Synthesises a placeholder for never-assigned enum locals
-
-use super::facts;
-use super::types;
-use crate::error::{TranslationErr, TranslationResult};
-use crate::translator::values::{ValueMap, generic_pointer_kind_retype_allowed};
-use dialect_iket::{ops::IketSentinelTokenOp, types::IketRangeTokenType};
-use dialect_mir::attributes::MirFP16Attr;
-use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
-use dialect_mir::ops::{
-    MirAddOp, MirBitAndOp, MirBitOrOp, MirBitXorOp, MirCastOp, MirCheckedAddOp, MirCheckedMulOp,
-    MirCheckedSubOp, MirCmpOp, MirConstantOp, MirConstructArrayOp, MirConstructEnumOp,
-    MirConstructStructOp, MirDivOp, MirEqOp, MirExtractFieldOp, MirGeOp, MirGlobalAllocOp, MirGtOp,
-    MirInsertFieldOp, MirLeOp, MirLoadOp, MirLtOp, MirMulOp, MirNeOp, MirNegOp, MirNotOp,
-    MirPtrOffsetOp, MirRefOp, MirRemOp, MirShlOp, MirShrOp, MirSubOp, MirUndefOp,
-};
-use dialect_mir::types::{MirFP16Type, MirPointerKind};
-use pliron::basic_block::BasicBlock;
-use pliron::builtin::types::{FP32Type, FP64Type, IntegerType, Signedness};
-use pliron::context::{Context, Ptr};
-use pliron::location::{Located, Location};
-use pliron::op::Op;
-use pliron::operation::Operation;
-use pliron::printable::Printable;
-use pliron::r#type::{TypeHandle, Typed};
-use pliron::utils::apint::APInt;
-use pliron::value::Value;
-use pliron::{input_err, input_err_noloc, input_error, input_error_noloc};
-use rustc_public::CrateDef;
-use rustc_public::mir;
-use rustc_public::mir::ProjectionElem;
-use rustc_public::ty::{AdtKind, ConstantKind};
-use rustc_public_bridge::IndexedVal;
-use std::num::NonZeroUsize;
-
-/// Normalize a pointer-like value without creating new Rust pointer semantics.
-///
-/// This helper is for representation adjustments such as address-space
-/// normalization and aggregate/local type reconciliation. Thin pointers must
-/// have the same pointee and fat slices the same element type. A concrete kind
-/// may be preserved or deliberately erased, but `Erased` cannot regain a
-/// concrete Rust kind and two distinct concrete kinds cannot be interconverted.
-fn cast_to_expected_pointer_type_if_needed(
-    ctx: &mut Context,
-    value: Value,
-    expected_type: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> (Value, Option<Ptr<Operation>>) {
-    let value_type = value.get_type(ctx);
-    if value_type == expected_type {
-        return (value, prev_op);
-    }
-
-    let compatible = {
-        let value_ref = value_type.deref(ctx);
-        let expected_ref = expected_type.deref(ctx);
-
-        match (
-            value_ref.downcast_ref::<dialect_mir::types::MirPtrType>(),
-            expected_ref.downcast_ref::<dialect_mir::types::MirPtrType>(),
-        ) {
-            (Some(value_ptr), Some(expected_ptr)) => {
-                value_ptr.pointee == expected_ptr.pointee
-                    && value_ptr.is_mutable == expected_ptr.is_mutable
-                    && generic_pointer_kind_retype_allowed(value_ptr.kind, expected_ptr.kind)
-            }
-            _ => match (
-                value_ref.downcast_ref::<dialect_mir::types::MirSliceType>(),
-                expected_ref.downcast_ref::<dialect_mir::types::MirSliceType>(),
-            ) {
-                (Some(value_slice), Some(expected_slice)) => {
-                    value_slice.element_ty == expected_slice.element_ty
-                        && value_slice.is_mutable == expected_slice.is_mutable
-                        && generic_pointer_kind_retype_allowed(
-                            value_slice.kind,
-                            expected_slice.kind,
-                        )
-                }
-                _ => false,
-            },
-        }
-    };
-
-    if !compatible {
-        return (value, prev_op);
-    }
-
-    let cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![expected_type],
-        vec![value],
-        vec![],
-        0,
-    );
-    cast_op.deref_mut(ctx).set_loc(loc);
-    MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-
-    match prev_op {
-        Some(prev) => cast_op.insert_after(ctx, prev),
-        None => cast_op.insert_at_front(block_ptr, ctx),
-    }
-
-    (cast_op.deref(ctx).get_result(0), Some(cast_op))
-}
-
-/// Establish the exact pointer/reference type declared by rustc at a semantic boundary.
-///
-/// `Rvalue::Ref` and `Rvalue::AddressOf` are not representation-only
-/// normalizations: they create a new Rust pointer/reference value. The result
-/// type supplied by rustc is therefore authoritative, including legitimate
-/// transitions such as `RawMut -> UniqueRef` for `unsafe { &mut *raw }`. This
-/// helper still requires the same thin-pointee or fat-slice element shape so it
-/// cannot hide an unrelated representation mismatch.
-fn cast_to_declared_rust_pointer_type_if_needed(
-    ctx: &mut Context,
-    value: Value,
-    expected_type: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-    authority: MirPointerKindAuthorityAttr,
-) -> (Value, Option<Ptr<Operation>>) {
-    let value_type = value.get_type(ctx);
-    if value_type == expected_type {
-        return (value, prev_op);
-    }
-
-    let compatible = {
-        let value_ref = value_type.deref(ctx);
-        let expected_ref = expected_type.deref(ctx);
-
-        match (
-            value_ref.downcast_ref::<dialect_mir::types::MirPtrType>(),
-            expected_ref.downcast_ref::<dialect_mir::types::MirPtrType>(),
-        ) {
-            (Some(value_ptr), Some(expected_ptr)) => value_ptr.pointee == expected_ptr.pointee,
-            _ => match (
-                value_ref.downcast_ref::<dialect_mir::types::MirSliceType>(),
-                expected_ref.downcast_ref::<dialect_mir::types::MirSliceType>(),
-            ) {
-                (Some(value_slice), Some(expected_slice)) => {
-                    value_slice.element_ty == expected_slice.element_ty
-                }
-                _ => false,
-            },
-        }
-    };
-
-    if !compatible {
-        return (value, prev_op);
-    }
-
-    let cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![expected_type],
-        vec![value],
-        vec![],
-        0,
-    );
-    cast_op.deref_mut(ctx).set_loc(loc);
-    let cast = MirCastOp::new(cast_op);
-    cast.set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-    cast.set_pointer_kind_authority(ctx, authority);
-
-    match prev_op {
-        Some(prev) => cast_op.insert_after(ctx, prev),
-        None => cast_op.insert_at_front(block_ptr, ctx),
-    }
-
-    (cast_op.deref(ctx).get_result(0), Some(cast_op))
-}
-
-/// Return the physical-storage form of a thin pointer type.
-///
-/// Allocation operations create addresses, not Rust borrows/raw-pointer
-/// values, so their results stay `Erased`. The translated Rust constant type
-/// is established by a separately marked boundary cast.
-fn erase_thin_pointer_kind(ctx: &mut Context, pointer_ty: TypeHandle) -> Option<TypeHandle> {
-    let (pointee, is_mutable, address_space) = {
-        let pointer_ty = pointer_ty.deref(ctx);
-        let pointer_ty = pointer_ty.downcast_ref::<dialect_mir::types::MirPtrType>()?;
-        (
-            pointer_ty.pointee,
-            pointer_ty.is_mutable,
-            pointer_ty.address_space,
-        )
-    };
-    Some(dialect_mir::types::MirPtrType::get(ctx, pointee, is_mutable, address_space).into())
-}
-
-/// Coerce a raw data pointer so it points to `element_type` in the generic
-/// address space.
-///
-/// `from_raw_parts`/`from_raw_parts_mut` build a `[T]` slice from a thin data
-/// pointer, but a reinterpret cast at the call site (e.g. `p as *mut (u64, u64)`
-/// feeding a `[(u64, u64)]` slice) can leave the data operand typed to the
-/// pre-cast pointee. The fat pointer's data slot must be a generic-address-space
-/// pointer to the slice element type, so when the pointee differs, emit a
-/// `PtrToPtr` cast to that type. The data carrier retains its existing pointer
-/// kind; otherwise constructing the fat pointer could launder an Erased carrier
-/// back into a concrete slice kind.
-fn coerce_slice_data_pointee(
-    ctx: &mut Context,
-    value: Value,
-    element_type: TypeHandle,
-    _is_mutable: bool,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> (Value, Option<Ptr<Operation>>) {
-    let (pointee_matches, origin) = {
-        let value_type = value.get_type(ctx);
-        let ty_ref = value_type.deref(ctx);
-        match ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>() {
-            Some(pt) => (
-                pt.pointee == element_type,
-                facts::pointer_origin_of_ptr_carrier(pt),
-            ),
-            None => return (value, prev_op),
-        }
-    };
-    if pointee_matches {
-        return (value, prev_op);
-    }
-    let target_ptr_ty: TypeHandle = facts::mint_generic_ptr_type(ctx, element_type, origin).into();
-    let cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![target_ptr_ty],
-        vec![value],
-        vec![],
-        0,
-    );
-    cast_op.deref_mut(ctx).set_loc(loc);
-    MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-    match prev_op {
-        Some(p) => cast_op.insert_after(ctx, p),
-        None => cast_op.insert_at_front(block_ptr, ctx),
-    }
-    (cast_op.deref(ctx).get_result(0), Some(cast_op))
-}
-
-/// Cast struct field values to match expected field types (address space normalization).
-///
-/// When constructing a struct, field values may have specific address spaces (e.g., addrspace:3)
-/// but the struct type's field definitions use generic address space (addrspace:0).
-/// This function casts each field value to match its expected type.
-fn cast_struct_fields_to_expected_types(
-    ctx: &mut Context,
-    field_values: Vec<Value>,
-    struct_type: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> (Vec<Value>, Option<Ptr<Operation>>) {
-    // Get field types from the struct type
-    let field_types: Vec<TypeHandle> = {
-        let ty_ref = struct_type.deref(ctx);
-        if let Some(st) = ty_ref.downcast_ref::<dialect_mir::types::MirStructType>() {
-            st.field_types.clone()
-        } else {
-            // Not a struct type, return as-is
-            return (field_values, prev_op);
-        }
-    };
-
-    let mut result_values = Vec::with_capacity(field_values.len());
-    let mut current_prev_op = prev_op;
-
-    for (i, value) in field_values.into_iter().enumerate() {
-        if let Some(expected_type) = field_types.get(i) {
-            let (casted_value, new_prev_op) = cast_to_expected_pointer_type_if_needed(
-                ctx,
-                value,
-                *expected_type,
-                block_ptr,
-                current_prev_op,
-                loc.clone(),
-            );
-            result_values.push(casted_value);
-            current_prev_op = new_prev_op;
-        } else {
-            result_values.push(value);
-        }
-    }
-
-    (result_values, current_prev_op)
-}
-
-/// Cast enum variant field values to match expected field types (address space normalization).
-///
-/// Similar to cast_struct_fields_to_expected_types, but for enum variants.
-/// Gets the field types for the specific variant and casts each field value.
-fn cast_enum_fields_to_expected_types(
-    ctx: &mut Context,
-    field_values: Vec<Value>,
-    enum_type: TypeHandle,
-    variant_idx: usize,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> (Vec<Value>, Option<Ptr<Operation>>) {
-    // Get the field types for this variant from the enum type
-    let variant_field_types: Vec<TypeHandle> = {
-        let ty_ref = enum_type.deref(ctx);
-        if let Some(et) = ty_ref.downcast_ref::<dialect_mir::types::MirEnumType>() {
-            // Calculate the field offset for this variant
-            let field_offset: usize = et.variant_field_counts[..variant_idx]
-                .iter()
-                .map(|&x| x as usize)
-                .sum();
-            let field_count = et.variant_field_counts[variant_idx] as usize;
-
-            // Get the field types for this variant
-            et.all_field_types[field_offset..field_offset + field_count].to_vec()
-        } else {
-            // Not an enum type, return as-is
-            return (field_values, prev_op);
-        }
-    };
-
-    let mut result_values = Vec::with_capacity(field_values.len());
-    let mut current_prev_op = prev_op;
-
-    for (i, value) in field_values.into_iter().enumerate() {
-        if let Some(expected_type) = variant_field_types.get(i) {
-            let (casted_value, new_prev_op) = cast_to_expected_pointer_type_if_needed(
-                ctx,
-                value,
-                *expected_type,
-                block_ptr,
-                current_prev_op,
-                loc.clone(),
-            );
-            result_values.push(casted_value);
-            current_prev_op = new_prev_op;
-        } else {
-            result_values.push(value);
-        }
-    }
-
-    (result_values, current_prev_op)
-}
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-enum CheckedBinaryOpKind {
-    Add,
-    Sub,
-    Mul,
-}
-
-fn classify_checked_binary_op(bin_op: &mir::BinOp) -> Result<CheckedBinaryOpKind, String> {
-    match bin_op {
-        mir::BinOp::Add => Ok(CheckedBinaryOpKind::Add),
-        mir::BinOp::Sub => Ok(CheckedBinaryOpKind::Sub),
-        mir::BinOp::Mul => Ok(CheckedBinaryOpKind::Mul),
-        _ => Err(format!("CheckedBinaryOp {:?} not yet implemented", bin_op)),
-    }
-}
-
-/// Translates a MIR rvalue to pliron IR operation(s).
-///
-/// # Returns
-///
-/// Tuple of `(Option<op>, result_value, last_inserted)`:
-/// - `op`: The main operation (None for `Rvalue::Use`)
-/// - `result_value`: The SSA value produced
-/// - `last_inserted`: Last inserted helper op (for operation ordering)
-///
-/// The operation is created but **not inserted** - caller must insert it.
-pub fn translate_rvalue(
-    ctx: &mut Context,
-    body: &mir::Body,
-    rvalue: &mir::Rvalue,
-    value_map: &mut ValueMap,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
-    match rvalue {
-        mir::Rvalue::BinaryOp(bin_op, left, right) => {
-            let (left_val, prev_op_after_left) =
-                translate_operand(ctx, body, left, value_map, block_ptr, prev_op, loc.clone())?;
-            let (right_val, prev_op_after_right) = translate_operand(
-                ctx,
-                body,
-                right,
-                value_map,
-                block_ptr,
-                prev_op_after_left,
-                loc.clone(),
-            )?;
-
-            // Check if this is a comparison operation that may need type coercion
-            let is_comparison = matches!(
-                bin_op,
-                mir::BinOp::Eq
-                    | mir::BinOp::Ne
-                    | mir::BinOp::Lt
-                    | mir::BinOp::Le
-                    | mir::BinOp::Gt
-                    | mir::BinOp::Ge
-            );
-
-            // For comparison operations, handle type mismatches by casting the right operand
-            // to match the left operand's type. This commonly occurs when comparing enum
-            // discriminants (u8) against isize constants in Rust's MIR.
-            let (final_right_val, final_prev_op) = if is_comparison {
-                let left_type = left_val.get_type(ctx);
-                let right_type = right_val.get_type(ctx);
-
-                if left_type != right_type {
-                    // Insert a cast operation to coerce right to match left's type
-                    let cast_op = Operation::new(
-                        ctx,
-                        MirCastOp::get_concrete_op_info(),
-                        vec![left_type],
-                        vec![right_val],
-                        vec![],
-                        0,
-                    );
-                    cast_op.deref_mut(ctx).set_loc(loc.clone());
-                    let coercion_kind = {
-                        let l = left_type.deref(ctx);
-                        let r = right_type.deref(ctx);
-                        if l.downcast_ref::<IntegerType>().is_some()
-                            && r.downcast_ref::<IntegerType>().is_some()
-                        {
-                            MirCastKindAttr::IntToInt
-                        } else if l.downcast_ref::<FP32Type>().is_some()
-                            || l.downcast_ref::<FP64Type>().is_some()
-                        {
-                            if r.downcast_ref::<FP32Type>().is_some()
-                                || r.downcast_ref::<FP64Type>().is_some()
-                            {
-                                MirCastKindAttr::FloatToFloat
-                            } else {
-                                MirCastKindAttr::Transmute
-                            }
-                        } else if l.downcast_ref::<dialect_mir::types::MirPtrType>().is_some()
-                            && r.downcast_ref::<dialect_mir::types::MirPtrType>().is_some()
-                        {
-                            MirCastKindAttr::PtrToPtr
-                        } else {
-                            MirCastKindAttr::Transmute
-                        }
-                    };
-                    MirCastOp::new(cast_op).set_attr_cast_kind(ctx, coercion_kind);
-
-                    // Insert the cast op after the right operand was processed
-                    if let Some(prev) = prev_op_after_right {
-                        cast_op.insert_after(ctx, prev);
-                    } else {
-                        cast_op.insert_at_front(block_ptr, ctx);
-                    }
-
-                    let casted_right = cast_op.deref(ctx).get_result(0);
-                    (casted_right, Some(cast_op))
-                } else {
-                    (right_val, prev_op_after_right)
-                }
-            } else {
-                (right_val, prev_op_after_right)
-            };
-
-            // Determine result type and operation
-            // Comparison operations return bool (i1), arithmetic ops return operand type
-            let (op_id, result_type) = match bin_op {
-                // Arithmetic operations - return same type as operands
-                // Unchecked variants are identical - overflow check is elided at MIR level
-                mir::BinOp::Add | mir::BinOp::AddUnchecked => {
-                    (MirAddOp::get_concrete_op_info(), left_val.get_type(ctx))
-                }
-                mir::BinOp::Sub | mir::BinOp::SubUnchecked => {
-                    (MirSubOp::get_concrete_op_info(), left_val.get_type(ctx))
-                }
-                mir::BinOp::Mul | mir::BinOp::MulUnchecked => {
-                    (MirMulOp::get_concrete_op_info(), left_val.get_type(ctx))
-                }
-                mir::BinOp::Div => (MirDivOp::get_concrete_op_info(), left_val.get_type(ctx)),
-                mir::BinOp::Rem => (MirRemOp::get_concrete_op_info(), left_val.get_type(ctx)),
-
-                // Comparison operations - return bool (i1)
-                mir::BinOp::Lt => (
-                    MirLtOp::get_concrete_op_info(),
-                    types::get_bool_type(ctx).to_handle(),
-                ),
-                mir::BinOp::Le => (
-                    MirLeOp::get_concrete_op_info(),
-                    types::get_bool_type(ctx).to_handle(),
-                ),
-                mir::BinOp::Gt => (
-                    MirGtOp::get_concrete_op_info(),
-                    types::get_bool_type(ctx).to_handle(),
-                ),
-                mir::BinOp::Ge => (
-                    MirGeOp::get_concrete_op_info(),
-                    types::get_bool_type(ctx).to_handle(),
-                ),
-                mir::BinOp::Eq => (
-                    MirEqOp::get_concrete_op_info(),
-                    types::get_bool_type(ctx).to_handle(),
-                ),
-                mir::BinOp::Ne => (
-                    MirNeOp::get_concrete_op_info(),
-                    types::get_bool_type(ctx).to_handle(),
-                ),
-                // Three-way comparison (`Ord::cmp`) - returns
-                // `core::cmp::Ordering`. rustc's `BinOp::ty` knows the
-                // result type of every binop (including `Cmp`, for which it
-                // returns the `Ordering` enum), so derive it locally from
-                // the operand types instead of threading the assignment
-                // destination type through every translate_rvalue caller.
-                mir::BinOp::Cmp => {
-                    let left_ty = left.ty(body.locals()).map_err(|e| {
-                        pliron::input_error!(
-                            loc.clone(),
-                            TranslationErr::unsupported(format!(
-                                "Failed to resolve BinOp::Cmp lhs type: {:?}",
-                                e
-                            ))
-                        )
-                    })?;
-                    let right_ty = right.ty(body.locals()).map_err(|e| {
-                        pliron::input_error!(
-                            loc.clone(),
-                            TranslationErr::unsupported(format!(
-                                "Failed to resolve BinOp::Cmp rhs type: {:?}",
-                                e
-                            ))
-                        )
-                    })?;
-                    let ordering_ty = bin_op.ty(left_ty, right_ty);
-                    (
-                        MirCmpOp::get_concrete_op_info(),
-                        types::translate_type(ctx, &ordering_ty)?,
-                    )
-                }
-
-                // Pointer offset - ptr.add(n) returns ptr + n * sizeof(element)
-                mir::BinOp::Offset => (
-                    MirPtrOffsetOp::get_concrete_op_info(),
-                    left_val.get_type(ctx), // Result is same pointer type
-                ),
-
-                // Shift operations - result is same as left operand type
-                // Unchecked variants are identical - overflow check is elided at MIR level
-                mir::BinOp::Shr | mir::BinOp::ShrUnchecked => {
-                    (MirShrOp::get_concrete_op_info(), left_val.get_type(ctx))
-                }
-                mir::BinOp::Shl | mir::BinOp::ShlUnchecked => {
-                    (MirShlOp::get_concrete_op_info(), left_val.get_type(ctx))
-                }
-
-                // Bitwise operations - result is same as operand type
-                mir::BinOp::BitAnd => (MirBitAndOp::get_concrete_op_info(), left_val.get_type(ctx)),
-                mir::BinOp::BitOr => (MirBitOrOp::get_concrete_op_info(), left_val.get_type(ctx)),
-                mir::BinOp::BitXor => (MirBitXorOp::get_concrete_op_info(), left_val.get_type(ctx)),
-            };
-
-            let op = Operation::new(
-                ctx,
-                op_id,
-                vec![result_type],
-                vec![left_val, final_right_val],
-                vec![],
-                0,
-            );
-            op.deref_mut(ctx).set_loc(loc);
-
-            let result = op.deref(ctx).get_result(0);
-
-            Ok((Some(op), result, final_prev_op))
-        }
-        mir::Rvalue::UnaryOp(un_op, operand) => {
-            match un_op {
-                mir::UnOp::PtrMetadata => {
-                    // PtrMetadata extracts the length from a slice (fat pointer)
-                    // For a slice &[T], this is field 1 (field 0 is the pointer, field 1 is length)
-                    let (operand_val, prev_op_after_operand) = translate_operand(
-                        ctx,
-                        body,
-                        operand,
-                        value_map,
-                        block_ptr,
-                        prev_op,
-                        loc.clone(),
-                    )?;
-
-                    // Result type is usize (the length)
-                    let result_type = types::get_usize_type(ctx);
-
-                    // Create an extract field operation to get field 1 (length)
-                    let op = Operation::new(
-                        ctx,
-                        MirExtractFieldOp::get_concrete_op_info(),
-                        vec![result_type.to_handle()],
-                        vec![operand_val],
-                        vec![],
-                        0,
-                    );
-                    op.deref_mut(ctx).set_loc(loc.clone());
-
-                    let extract_op = MirExtractFieldOp::new(op);
-                    extract_op.set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(1));
-
-                    let result = extract_op.get_operation().deref(ctx).get_result(0);
-
-                    Ok((
-                        Some(extract_op.get_operation()),
-                        result,
-                        prev_op_after_operand,
-                    ))
-                }
-                mir::UnOp::Not | mir::UnOp::Neg => {
-                    let (operand_val, prev_op_after_operand) = translate_operand(
-                        ctx,
-                        body,
-                        operand,
-                        value_map,
-                        block_ptr,
-                        prev_op,
-                        loc.clone(),
-                    )?;
-                    let result_type = operand_val.get_type(ctx);
-
-                    let op_id = match un_op {
-                        mir::UnOp::Not => MirNotOp::get_concrete_op_info(),
-                        mir::UnOp::Neg => MirNegOp::get_concrete_op_info(),
-                        _ => unreachable!(),
-                    };
-
-                    let op =
-                        Operation::new(ctx, op_id, vec![result_type], vec![operand_val], vec![], 0);
-                    op.deref_mut(ctx).set_loc(loc);
-
-                    let result = op.deref(ctx).get_result(0);
-
-                    Ok((Some(op), result, prev_op_after_operand))
-                }
-            }
-        }
-        mir::Rvalue::Cast(kind, operand, ty) => {
-            // `let f: fn(u32) -> u32 = inc;` compiles to a ReifyFnPointer
-            // cast. It is not a value conversion: the fn item `inc` is
-            // zero-sized, so there is nothing to convert. What the program
-            // needs is some address-like value identifying the function.
-            // Real code addresses do not exist on the device (the function
-            // may not even be compiled), so we make a stable stand-in: a
-            // hash of the function's mangled name, cast int -> ptr. With
-            // that, `f == f` is true and two different functions compare
-            // unequal (Rust permits, but does not promise, distinct fn
-            // addresses, so a hash stand-in is within contract). CALLING
-            // through the pointer is still unsupported and fails loudly at
-            // the call site. Handled before translate_operand because the
-            // zero-sized fn-item operand itself never becomes a value.
-            if let mir::CastKind::PointerCoercion(mir::PointerCoercion::ReifyFnPointer(_)) = kind {
-                return translate_reify_fn_pointer(ctx, body, operand, ty, block_ptr, prev_op, loc);
-            }
-            if let mir::CastKind::PointerCoercion(mir::PointerCoercion::ClosureFnPointer(_)) = kind
-            {
-                return translate_closure_fn_pointer(
-                    ctx, body, operand, ty, block_ptr, prev_op, loc,
-                );
-            }
-
-            let (operand_val, prev_op_after_operand) = translate_operand(
-                ctx,
-                body,
-                operand,
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-
-            let result_type = types::translate_type(ctx, ty)?;
-
-            let op = Operation::new(
-                ctx,
-                MirCastOp::get_concrete_op_info(),
-                vec![result_type],
-                vec![operand_val],
-                vec![],
-                0,
-            );
-            op.deref_mut(ctx).set_loc(loc);
-
-            let cast_kind_attr = match kind {
-                mir::CastKind::IntToInt => MirCastKindAttr::IntToInt,
-                mir::CastKind::IntToFloat => MirCastKindAttr::IntToFloat,
-                mir::CastKind::FloatToInt => MirCastKindAttr::FloatToInt,
-                mir::CastKind::FloatToFloat => MirCastKindAttr::FloatToFloat,
-                mir::CastKind::PtrToPtr => MirCastKindAttr::PtrToPtr,
-                mir::CastKind::FnPtrToPtr => MirCastKindAttr::FnPtrToPtr,
-                mir::CastKind::PointerExposeAddress => MirCastKindAttr::PointerExposeAddress,
-                mir::CastKind::PointerWithExposedProvenance => {
-                    MirCastKindAttr::PointerWithExposedProvenance
-                }
-                mir::CastKind::Transmute => MirCastKindAttr::Transmute,
-                mir::CastKind::PointerCoercion(coercion) => match coercion {
-                    mir::PointerCoercion::Unsize => MirCastKindAttr::PointerCoercionUnsize,
-                    mir::PointerCoercion::MutToConstPointer => {
-                        MirCastKindAttr::PointerCoercionMutToConst
-                    }
-                    mir::PointerCoercion::ArrayToPointer => {
-                        MirCastKindAttr::PointerCoercionArrayToPointer
-                    }
-                    mir::PointerCoercion::ReifyFnPointer(_) => {
-                        MirCastKindAttr::PointerCoercionReifyFnPointer
-                    }
-                    mir::PointerCoercion::UnsafeFnPointer => {
-                        MirCastKindAttr::PointerCoercionUnsafeFnPointer
-                    }
-                    mir::PointerCoercion::ClosureFnPointer(_safety) => {
-                        MirCastKindAttr::PointerCoercionClosureFnPointer
-                    }
-                },
-                mir::CastKind::Subtype => MirCastKindAttr::Subtype,
-            };
-            let cast_op = MirCastOp::new(op);
-            cast_op.set_attr_cast_kind(ctx, cast_kind_attr.clone());
-            if dialect_mir::types::type_contains_concrete_pointer_kind(ctx, result_type)
-                || (cast_kind_attr == MirCastKindAttr::Transmute
-                    && !dialect_mir::types::pointer_kinds_in_type(ctx, result_type).is_empty())
-            {
-                // This operation comes directly from a rustc MIR CastKind, so
-                // any concrete result category, including one nested in an
-                // aggregate transmute, is an explicit Rust semantic boundary
-                // rather than a generic representation adjustment.
-                cast_op.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::RustCast);
-            }
-
-            let result = op.deref(ctx).get_result(0);
-
-            Ok((Some(op), result, prev_op_after_operand))
-        }
-        mir::Rvalue::CheckedBinaryOp(bin_op, left, right) => {
-            let checked_kind = classify_checked_binary_op(bin_op).map_err(|message| {
-                input_error!(loc.clone(), TranslationErr::unsupported(message))
-            })?;
-
-            let (left_val, prev_op_after_left) =
-                translate_operand(ctx, body, left, value_map, block_ptr, prev_op, loc.clone())?;
-            let (right_val, prev_op_after_right) = translate_operand(
-                ctx,
-                body,
-                right,
-                value_map,
-                block_ptr,
-                prev_op_after_left,
-                loc.clone(),
-            )?;
-
-            // The result type is the MIR-level `(T, bool)` tuple.
-            // Translate it from the rvalue's rustc type so it is the
-            // same uniqued, layout-carrying tuple type the rest of
-            // the body (locals, places) uses.
-            let rust_tuple_ty = rvalue.ty(body.locals()).map_err(|e| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Failed to query checked-arithmetic result type: {:?}",
-                    e
-                )))
-            })?;
-            let result_type = types::translate_type(ctx, &rust_tuple_ty)?;
-
-            let op_id = match checked_kind {
-                CheckedBinaryOpKind::Add => MirCheckedAddOp::get_concrete_op_info(),
-                CheckedBinaryOpKind::Sub => MirCheckedSubOp::get_concrete_op_info(),
-                CheckedBinaryOpKind::Mul => MirCheckedMulOp::get_concrete_op_info(),
-            };
-            let op = Operation::new(
-                ctx,
-                op_id,
-                vec![result_type],
-                vec![left_val, right_val],
-                vec![],
-                0,
-            );
-            op.deref_mut(ctx).set_loc(loc);
-
-            let result = op.deref(ctx).get_result(0);
-            Ok((Some(op), result, prev_op_after_right))
-        }
-        mir::Rvalue::Use(operand) => {
-            // Use just copies/moves a value - no operation needed, just pass through
-            // The operand translation may insert field extraction operations
-            let (val, last_inserted) =
-                translate_operand(ctx, body, operand, value_map, block_ptr, prev_op, loc)?;
-
-            // Return None for operation - Use doesn't create an operation
-            // Any field extractions are already inserted and tracked in last_inserted
-            Ok((None, val, last_inserted))
-        }
-        mir::Rvalue::Ref(_region, borrow_kind, place) => {
-            // Ref creates a reference to a place: &place or &mut place.
-            //
-            // Strategy:
-            //
-            // 1. `&local` / `&mut local` -- return the local's alloca slot
-            //    pointer directly (ZST locals get a synthesised pointer).
-            // 2. Any projected place -- compute the real in-memory address
-            //    by walking the FULL projection list from the base local's
-            //    slot via `translate_place_address`: `&(*ptr)` loads the
-            //    pointer, `&(*ptr).field` adds a `mir.field_addr`,
-            //    `&x.arr[i]` adds a `mir.array_element_addr`, and arbitrary
-            //    combinations compose. Borrows produced this way ALIAS the
-            //    original storage, which is what Rust requires: e.g.
-            //    `Enumerate::next` takes `&mut (*_1).0` and `Iter::next`
-            //    must advance the ORIGINAL Iter in place -- a `mir.ref` of
-            //    an extracted field VALUE would mutate a copy and loop
-            //    forever.
-            // 3. Only when no address can be computed (slot-less computed
-            //    value, or a projection the walker cannot lower, e.g.
-            //    Downcast) do we fall back to materialising the VALUE and
-            //    wrapping it in `mir.ref` (fresh slot + store of a COPY).
-            //    That is sound for shared borrows (reads through a copy)
-            //    and a silent miscompile for mutable ones (writes land in
-            //    the copy), so mutable borrows hard-error instead.
-
-            // Case 1: bare local reference `&local` / `&mut local`.
-            //
-            // Alloca + load/store model: every non-ZST MIR local is backed by
-            // a stack slot emitted at the top of the entry block. Taking the
-            // address of the local therefore just returns that slot pointer --
-            // no extra allocation is needed. `mem2reg` folds this back into
-            // SSA when the borrow doesn't escape.
-            //
-            // Slots are always allocated mutable because the importer writes
-            // locals through them. They are compiler storage, not `&mut T`.
-            // The normalization below retypes the physical slot address to the
-            // exact Rust reference kind without treating slot mutability as
-            // evidence of uniqueness.
-            let origin = facts::pointer_origin_of_borrow(*borrow_kind);
-            let is_mutable = origin.is_mutable();
-            if place.projection.is_empty() {
-                if let Some(slot) = value_map.get_slot(place.local) {
-                    // The slot is compiler storage (`Erased`) and is always
-                    // mutable. Taking a Rust borrow is the semantic boundary
-                    // where that physical address acquires the exact `&T` /
-                    // `&mut T` type recorded by rustc.
-                    let rust_result_type = rvalue.ty(body.locals()).map_err(|error| {
-                        input_error_noloc!(TranslationErr::unsupported(format!(
-                            "failed to determine reference rvalue type: {error:?}"
-                        )))
-                    })?;
-                    let expected_ptr_type = types::translate_type(ctx, &rust_result_type)?;
-                    let (result, last_inserted) = cast_to_declared_rust_pointer_type_if_needed(
-                        ctx,
-                        slot,
-                        expected_ptr_type,
-                        block_ptr,
-                        prev_op,
-                        loc.clone(),
-                        MirPointerKindAuthorityAttr::Reborrow,
-                    );
-                    return Ok((None, result, last_inserted));
-                }
-                // ZST local (no slot). Synthesise a pointer-to-ZST via
-                // MirRefOp as a fallback so callers still get a well-typed
-                // pointer value.
-                let local_decl = &body.locals()[place.local];
-                let ty_ptr = super::types::translate_type(ctx, &local_decl.ty)?;
-                let (zst_val, last_inserted) =
-                    if ty_ptr.deref(ctx).is::<dialect_mir::types::MirEnumType>() {
-                        let op = create_ghost_enum_default(ctx, ty_ptr, loc.clone());
-                        match prev_op {
-                            Some(p) => op.insert_after(ctx, p),
-                            None => op.insert_at_front(block_ptr, ctx),
-                        }
-                        (op.deref(ctx).get_result(0), Some(op))
-                    } else {
-                        translate_zero_sized_constant_value(
-                            ctx,
-                            ty_ptr,
-                            block_ptr,
-                            prev_op,
-                            loc.clone(),
-                        )?
-                    };
-                let ptr_ty = facts::mint_generic_ptr_type(ctx, ty_ptr, origin);
-                let ref_op = Operation::new(
-                    ctx,
-                    MirRefOp::get_concrete_op_info(),
-                    vec![ptr_ty.into()],
-                    vec![zst_val],
-                    vec![],
-                    0,
-                );
-                ref_op.deref_mut(ctx).set_loc(loc);
-                let mir_ref = MirRefOp::new(ref_op);
-                mir_ref.set_mutable(ctx, is_mutable);
-                mir_ref.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::Reborrow);
-                match last_inserted {
-                    Some(p) => ref_op.insert_after(ctx, p),
-                    None => ref_op.insert_at_front(block_ptr, ctx),
-                }
-                let result_val = ref_op.deref(ctx).get_result(0);
-                return Ok((None, result_val, Some(ref_op)));
-            }
-
-            // Case 2: unified address path -- walk the full projection list
-            // (`Deref`, `Field`, `Index`, `ConstantIndex`) from the base
-            // local's alloca slot. This is the "correct-refs" path: the
-            // resulting pointer addresses the ORIGINAL storage, so writes
-            // through the borrow mutate the borrowed place.
-            if let Some((result_val, last_inserted)) = translate_place_address(
-                ctx,
-                body,
-                value_map,
-                place,
-                is_mutable,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )? {
-                // Address arithmetic remains in the physical address space, but the
-                // resulting Rust reference must have its exact translated Rust type.
-                let rust_result_type = rvalue.ty(body.locals()).map_err(|error| {
-                    input_error_noloc!(TranslationErr::unsupported(format!(
-                        "failed to determine reference rvalue type: {error:?}"
-                    )))
-                })?;
-                let expected_ptr_type = types::translate_type(ctx, &rust_result_type)?;
-
-                let (result_val, last_inserted) = cast_to_declared_rust_pointer_type_if_needed(
-                    ctx,
-                    result_val,
-                    expected_ptr_type,
-                    block_ptr,
-                    last_inserted,
-                    loc.clone(),
-                    MirPointerKindAuthorityAttr::Reborrow,
-                );
-
-                return Ok((None, result_val, last_inserted));
-            }
-
-            // No address could be computed. The only remaining strategy is
-            // the value-copy fallback below, which is a silent miscompile
-            // for mutable borrows: writes through the borrow would land in
-            // the copy and the original place would never change. Refuse
-            // loudly instead of emitting wrong code.
-            if is_mutable {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Rvalue::Ref: cannot compute an in-memory address for the mutable \
-                         borrow of place {:?} (projection {:?}); the value-copy fallback \
-                         would silently discard writes through the borrow",
-                        place, place.projection
-                    ))
-                );
-            }
-
-            // Case 3: shared-borrow fallback -- reference to a computed
-            // value that has no backing slot (e.g. the result of an rvalue
-            // expression) or whose projection the address walker cannot
-            // lower (e.g. enum Downcast, issues #131/#146). Emit `mir.ref`
-            // which allocates a fresh slot, stores a COPY of the value, and
-            // returns the pointer. Sound for shared borrows only (reads);
-            // mutable borrows were rejected above.
-            let (val, last_inserted) =
-                translate_place(ctx, body, place, value_map, block_ptr, prev_op, loc.clone())?;
-
-            let val_ty = val.get_type(ctx);
-            let ptr_ty = facts::mint_generic_ptr_type(ctx, val_ty, origin);
-
-            let ref_op = Operation::new(
-                ctx,
-                MirRefOp::get_concrete_op_info(),
-                vec![ptr_ty.into()],
-                vec![val],
-                vec![],
-                0,
-            );
-            ref_op.deref_mut(ctx).set_loc(loc);
-            let mir_ref = MirRefOp::new(ref_op);
-            mir_ref.set_mutable(ctx, is_mutable);
-            mir_ref.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::Reborrow);
-
-            let result_val = ref_op.deref(ctx).get_result(0);
-            Ok((Some(ref_op), result_val, last_inserted))
-        }
-        mir::Rvalue::AddressOf(mutability, place) => {
-            // AddressOf creates a raw pointer to a place: `&raw const place`
-            // / `&raw mut place` (also `core::ptr::addr_of!`). Raw pointers
-            // have the same aliasing requirement as references: the pointer
-            // must address the ORIGINAL place, so this routes through the
-            // same unified address walker as `Rvalue::Ref` (which also gives
-            // raw pointers the runtime-Index / ConstantIndex handling).
-            let origin = facts::pointer_origin_of_raw_ptr(*mutability);
-            let is_mutable = origin.is_mutable();
-
-            // Bare local: the alloca slot is the physical address, but the
-            // result must carry the exact raw-pointer kind rather than the
-            // slot's compiler-only `Erased` provenance.
-            if place.projection.is_empty()
-                && let Some(slot) = value_map.get_slot(place.local)
-            {
-                let rust_result_type = rvalue.ty(body.locals()).map_err(|error| {
-                    input_error_noloc!(TranslationErr::unsupported(format!(
-                        "failed to determine address-of rvalue type: {error:?}"
-                    )))
-                })?;
-                let expected_ptr_type = types::translate_type(ctx, &rust_result_type)?;
-                let (result, last_inserted) = cast_to_declared_rust_pointer_type_if_needed(
-                    ctx,
-                    slot,
-                    expected_ptr_type,
-                    block_ptr,
-                    prev_op,
-                    loc.clone(),
-                    MirPointerKindAuthorityAttr::RawAddress,
-                );
-                return Ok((None, result, last_inserted));
-            }
-
-            // Unified address path: full projection walk from the slot
-            // (`&raw (*ptr)` loads the pointer, `&raw (*ptr).field[i]`
-            // composes field + element addresses, ...).
-            if let Some((result_val, last_inserted)) = translate_place_address(
-                ctx,
-                body,
-                value_map,
-                place,
-                is_mutable,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )? {
-                // Preserve physical address spaces while walking the place, then restore
-                // the exact raw-pointer type required by the Rust rvalue.
-                let rust_result_type = rvalue.ty(body.locals()).map_err(|error| {
-                    input_error_noloc!(TranslationErr::unsupported(format!(
-                        "failed to determine address-of rvalue type: {error:?}"
-                    )))
-                })?;
-                let expected_ptr_type = types::translate_type(ctx, &rust_result_type)?;
-
-                let (result_val, last_inserted) = cast_to_declared_rust_pointer_type_if_needed(
-                    ctx,
-                    result_val,
-                    expected_ptr_type,
-                    block_ptr,
-                    last_inserted,
-                    loc.clone(),
-                    MirPointerKindAuthorityAttr::RawAddress,
-                );
-
-                return Ok((None, result_val, last_inserted));
-            }
-
-            // No address could be computed. The value-copy fallback below
-            // returns a pointer to a COPY, so writes through a `&raw mut`
-            // would be silently lost -- refuse loudly. Exception: a bare
-            // slot-less local is a ZST (no bytes), so a copy cannot lose
-            // writes; let it use the fallback for both mutabilities, the
-            // same way `Rvalue::Ref` synthesises ZST borrows.
-            if is_mutable && !place.projection.is_empty() {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Rvalue::AddressOf: cannot compute an in-memory address for \
-                         `&raw mut` of place {:?} (projection {:?}); the value-copy \
-                         fallback would silently discard writes through the pointer",
-                        place, place.projection
-                    ))
-                );
-            }
-
-            // Shared (or bare-ZST) fallback: translate to a value and
-            // materialize an address of a copy.
-            let (val, last_inserted) =
-                translate_place(ctx, body, place, value_map, block_ptr, prev_op, loc.clone())?;
-
-            let val_ty = val.get_type(ctx);
-            let ptr_ty = facts::mint_generic_ptr_type(ctx, val_ty, origin);
-
-            use dialect_mir::ops::MirRefOp;
-            let ref_op = Operation::new(
-                ctx,
-                MirRefOp::get_concrete_op_info(),
-                vec![ptr_ty.into()],
-                vec![val],
-                vec![],
-                0,
-            );
-            ref_op.deref_mut(ctx).set_loc(loc);
-
-            let mir_ref_op = MirRefOp::new(ref_op);
-            mir_ref_op.set_mutable(ctx, is_mutable);
-            mir_ref_op.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::RawAddress);
-
-            let result_val = ref_op.deref(ctx).get_result(0);
-
-            Ok((Some(ref_op), result_val, last_inserted))
-        }
-        mir::Rvalue::Aggregate(aggregate_kind, operands) => {
-            // Aggregate constructs a compound type from individual values.
-            // This is used for:
-            // - Tuple construction: (a, b, c)
-            // - Struct construction: MyStruct { field1: a, field2: b }
-            // - Array construction: [a, b, c]
-
-            match aggregate_kind {
-                mir::AggregateKind::Adt(adt_def, variant_idx, substs, _, active_field_idx) => {
-                    let adt_kind = adt_def.kind();
-
-                    // Get the type using adt_def.ty_with_args()
-                    let adt_ty_rust = adt_def.ty_with_args(substs);
-                    let adt_ty = types::translate_type(ctx, &adt_ty_rust)?;
-                    let translated_field_values = if matches!(adt_kind, AdtKind::Union) {
-                        None
-                    } else {
-                        Some(translate_adt_aggregate_field_values(
-                            ctx,
-                            body,
-                            *adt_def,
-                            *variant_idx,
-                            substs,
-                            operands,
-                            value_map,
-                            block_ptr,
-                            prev_op,
-                            loc.clone(),
-                        )?)
-                    };
-
-                    match adt_kind {
-                        AdtKind::Struct => {
-                            let (field_values, current_prev_op) = translated_field_values
-                                .expect("non-union ADT fields should have been translated");
-                            // Check if the translated type is a struct type.
-                            // Scalar-lowered newtypes like ThreadIndex are translated to
-                            // their single runtime field type. They may still have ZST
-                            // marker fields in MIR, so select the one field whose
-                            // translated value matches the scalar result type.
-                            let is_struct_type = {
-                                let ty_obj = adt_ty.deref(ctx);
-                                ty_obj.is::<dialect_mir::types::MirStructType>()
-                                    || ty_obj.is::<dialect_mir::types::MirTupleType>()
-                            };
-
-                            // A `DisjointSlice` literal, which
-                            // `DisjointSlice::from_raw_parts` builds. The type
-                            // translator gives the ADT its own slice type rather
-                            // than a struct, so without this arm the shape falls
-                            // into the scalar-lowered path below, where no field
-                            // carries the slice type and the search reports zero
-                            // runtime fields (issue #667).
-                            if adt_ty
-                                .deref(ctx)
-                                .is::<dialect_mir::types::MirDisjointSliceType>()
-                            {
-                                return construct_disjoint_slice_aggregate(
-                                    ctx,
-                                    adt_ty,
-                                    &field_values,
-                                    block_ptr,
-                                    current_prev_op,
-                                    loc,
-                                );
-                            }
-
-                            if !is_struct_type {
-                                // Scalar-lowered ADT: layout collapsed to a single runtime
-                                // value. The MIR Aggregate may still list ZST fields
-                                // (PhantomData, etc.) -- those translate to types other
-                                // than `adt_ty`, so filtering by "type matches the
-                                // collapsed scalar" reliably picks the one runtime field.
-                                //
-                                // This works for shapes like
-                                //     ThreadIndex { raw: usize, _kernel: PhantomData<...>, ... }
-                                // where exactly one field shares the scalar type. If a
-                                // future scalar-lowered ADT has two runtime fields with
-                                // the same type, the filter returns >1 match and we bail
-                                // -- the assumption is wrong and the translator needs an
-                                // explicit story for that shape.
-                                let runtime_fields: Vec<Value> = field_values
-                                    .iter()
-                                    .copied()
-                                    .filter(|value| value.get_type(ctx) == adt_ty)
-                                    .collect();
-
-                                if runtime_fields.len() == 1 {
-                                    Ok((None, runtime_fields[0], current_prev_op))
-                                } else {
-                                    input_err!(
-                                        loc,
-                                        TranslationErr::unsupported(format!(
-                                            "Scalar-lowered ADT expected exactly one runtime field, found {}",
-                                            runtime_fields.len()
-                                        ))
-                                    )
-                                }
-                            } else {
-                                // Cast field values to expected types (address space normalization)
-                                // This handles cases where field values have specific address spaces
-                                // (e.g., addrspace:3 for shared memory) but the struct type expects
-                                // generic address space (addrspace:0)
-                                let (casted_field_values, prev_after_casts) =
-                                    cast_struct_fields_to_expected_types(
-                                        ctx,
-                                        field_values,
-                                        adt_ty,
-                                        block_ptr,
-                                        current_prev_op,
-                                        loc.clone(),
-                                    );
-
-                                // Create the construct_struct operation
-                                let op = Operation::new(
-                                    ctx,
-                                    MirConstructStructOp::get_concrete_op_info(),
-                                    vec![adt_ty],
-                                    casted_field_values,
-                                    vec![],
-                                    0,
-                                );
-                                op.deref_mut(ctx).set_loc(loc);
-
-                                let result = op.deref(ctx).get_result(0);
-
-                                Ok((Some(op), result, prev_after_casts))
-                            }
-                        }
-                        AdtKind::Enum => {
-                            let (field_values, current_prev_op) = translated_field_values
-                                .expect("non-union ADT fields should have been translated");
-                            // Get the variant index for the enum
-                            // NOTE: variant_idx IS the index (0, 1, 2, ...), NOT the discriminant!
-                            // discriminant_for_variant returns the discriminant VALUE which may differ
-                            // (e.g., enum Foo { A = 0, B = 2, C = 6 } has indices 0,1,2 but discriminants 0,2,6)
-                            let variant_index_val: usize = variant_idx.to_index();
-
-                            // A value inhabiting this variant cannot exist,
-                            // so this construction sits on a dynamically dead
-                            // path rustc keeps in MIR (e.g. building
-                            // `ControlFlow::Break(NeverShortCircuitResidual)`
-                            // inside `array::try_from_fn`).
-                            // `mir.construct_enum` refuses uninhabited
-                            // variants by verification, so keep the dead path
-                            // representable with a typed undef instead.
-                            let variant_is_uninhabited = adt_ty
-                                .deref(ctx)
-                                .downcast_ref::<dialect_mir::types::MirEnumType>()
-                                .and_then(|enum_ty| enum_ty.variant_is_inhabited(variant_index_val))
-                                .is_some_and(|inhabited| !inhabited);
-                            if variant_is_uninhabited {
-                                let undef = MirUndefOp::new(ctx, adt_ty).get_operation();
-                                undef.deref_mut(ctx).set_loc(loc);
-                                let result = undef.deref(ctx).get_result(0);
-                                return Ok((Some(undef), result, current_prev_op));
-                            }
-
-                            // Cast field values to expected types (address space normalization)
-                            // This handles cases where field values have specific address spaces
-                            // (e.g., addrspace:3 for shared memory) but the enum type expects
-                            // generic address space (addrspace:0)
-                            let (casted_field_values, prev_after_casts) =
-                                cast_enum_fields_to_expected_types(
-                                    ctx,
-                                    field_values,
-                                    adt_ty,
-                                    variant_index_val,
-                                    block_ptr,
-                                    current_prev_op,
-                                    loc.clone(),
-                                );
-
-                            // Create the construct_enum operation with variant_index attribute
-                            let op = Operation::new(
-                                ctx,
-                                MirConstructEnumOp::get_concrete_op_info(),
-                                vec![adt_ty],
-                                casted_field_values,
-                                vec![],
-                                0,
-                            );
-                            op.deref_mut(ctx).set_loc(loc.clone());
-
-                            let enum_op = MirConstructEnumOp::new(op);
-                            enum_op.set_attr_construct_enum_variant_index(
-                                ctx,
-                                dialect_mir::attributes::VariantIndexAttr(variant_index_val as u32),
-                            );
-
-                            let result = op.deref(ctx).get_result(0);
-
-                            Ok((Some(op), result, prev_after_casts))
-                        }
-                        AdtKind::Union => translate_union_aggregate(
-                            ctx,
-                            body,
-                            *adt_def,
-                            adt_ty,
-                            *active_field_idx,
-                            operands,
-                            value_map,
-                            block_ptr,
-                            prev_op,
-                            loc,
-                        ),
-                    }
-                }
-                mir::AggregateKind::Tuple => {
-                    // Tuple construction: (a, b, c)
-                    // Similar to struct construction but with positional fields
-
-                    // Translate all element operands
-                    let mut element_values = Vec::with_capacity(operands.len());
-                    let mut current_prev_op = prev_op;
-
-                    for operand in operands {
-                        let (val, new_prev_op) = translate_operand(
-                            ctx,
-                            body,
-                            operand,
-                            value_map,
-                            block_ptr,
-                            current_prev_op,
-                            loc.clone(),
-                        )?;
-                        element_values.push(val);
-                        current_prev_op = new_prev_op;
-                    }
-
-                    // Translate the tuple type from the rvalue's rustc type
-                    // so it carries rustc's layout and uniques with the
-                    // tuple type of the destination place.
-                    let rust_tuple_ty = rvalue.ty(body.locals()).map_err(|e| {
-                        input_error_noloc!(TranslationErr::unsupported(format!(
-                            "Failed to query tuple aggregate type: {:?}",
-                            e
-                        )))
-                    })?;
-                    let tuple_ty = types::translate_type(ctx, &rust_tuple_ty)?;
-
-                    // Create mir.construct_tuple operation
-                    use dialect_mir::ops::MirConstructTupleOp;
-
-                    let op = Operation::new(
-                        ctx,
-                        MirConstructTupleOp::get_concrete_op_info(),
-                        vec![tuple_ty],
-                        element_values,
-                        vec![],
-                        0,
-                    );
-                    op.deref_mut(ctx).set_loc(loc);
-
-                    let result = op.deref(ctx).get_result(0);
-
-                    Ok((Some(op), result, current_prev_op))
-                }
-                mir::AggregateKind::Array(elem_ty) => {
-                    // Array construction: [e0, e1, e2, ...] -> mir.construct_array
-                    // Translate the element type
-                    let element_type = types::translate_type(ctx, elem_ty)?;
-                    let array_size = operands.len() as u64;
-
-                    // Translate all element operands
-                    let mut element_values = Vec::with_capacity(operands.len());
-                    let mut current_prev_op = prev_op;
-
-                    for operand in operands {
-                        let (val, new_prev_op) = translate_operand(
-                            ctx,
-                            body,
-                            operand,
-                            value_map,
-                            block_ptr,
-                            current_prev_op,
-                            loc.clone(),
-                        )?;
-                        let (val, new_prev_op) = cast_to_expected_pointer_type_if_needed(
-                            ctx,
-                            val,
-                            element_type,
-                            block_ptr,
-                            new_prev_op,
-                            loc.clone(),
-                        );
-                        element_values.push(val);
-                        current_prev_op = new_prev_op;
-                    }
-
-                    // Create the array type
-                    let array_ty =
-                        dialect_mir::types::MirArrayType::get(ctx, element_type, array_size);
-
-                    // Create mir.construct_array operation
-                    let op = Operation::new(
-                        ctx,
-                        MirConstructArrayOp::get_concrete_op_info(),
-                        vec![array_ty.into()],
-                        element_values,
-                        vec![],
-                        0,
-                    );
-                    op.deref_mut(ctx).set_loc(loc);
-
-                    let result = op.deref(ctx).get_result(0);
-
-                    Ok((Some(op), result, current_prev_op))
-                }
-                mir::AggregateKind::Closure(closure_def, substs) => {
-                    // Closure construction with captures
-                    // The operands are the captured values that form the closure environment
-                    //
-                    // MIR: _N = Aggregate(Closure(...), [captured_val1, captured_val2, ...])
-                    // We construct a struct with the captured values as fields
-
-                    // Translate all captured operands
-                    let mut capture_values = Vec::with_capacity(operands.len());
-                    let mut current_prev_op = prev_op;
-
-                    for operand in operands {
-                        let (val, new_prev_op) = translate_operand(
-                            ctx,
-                            body,
-                            operand,
-                            value_map,
-                            block_ptr,
-                            current_prev_op,
-                            loc.clone(),
-                        )?;
-                        capture_values.push(val);
-                        current_prev_op = new_prev_op;
-                    }
-
-                    // Get the closure type
-                    let closure_ty_rust =
-                        rustc_public::ty::Ty::new_closure(*closure_def, substs.clone());
-                    let closure_ty = types::translate_type(ctx, &closure_ty_rust)?;
-
-                    if capture_values.is_empty() {
-                        // ZST closure (no captures) - create empty struct
-                        let op = Operation::new(
-                            ctx,
-                            MirConstructStructOp::get_concrete_op_info(),
-                            vec![closure_ty],
-                            vec![],
-                            vec![],
-                            0,
-                        );
-                        op.deref_mut(ctx).set_loc(loc);
-                        let result = op.deref(ctx).get_result(0);
-                        Ok((Some(op), result, current_prev_op))
-                    } else {
-                        // Closure with captures - create struct with captured values
-                        // Cast captured values to expected types (address space normalization)
-                        let (casted_capture_values, prev_after_casts) =
-                            cast_struct_fields_to_expected_types(
-                                ctx,
-                                capture_values,
-                                closure_ty,
-                                block_ptr,
-                                current_prev_op,
-                                loc.clone(),
-                            );
-
-                        let op = Operation::new(
-                            ctx,
-                            MirConstructStructOp::get_concrete_op_info(),
-                            vec![closure_ty],
-                            casted_capture_values,
-                            vec![],
-                            0,
-                        );
-                        op.deref_mut(ctx).set_loc(loc);
-                        let result = op.deref(ctx).get_result(0);
-                        Ok((Some(op), result, prev_after_casts))
-                    }
-                }
-                mir::AggregateKind::RawPtr(pointee_ty, mutability) => {
-                    // Raw pointer construction from parts: rustc lowers the
-                    // `aggregate_raw_ptr` intrinsic to this aggregate kind.
-                    // It is reached by re-slicing (`&bytes[2..]` goes through
-                    // `slice::index::get_offset_len_noubcheck`) and by
-                    // `ptr::slice_from_raw_parts` / `ptr::from_raw_parts`.
-                    // The two operands are (data_pointer, metadata).
-                    use rustc_public::ty::{RigidTy, TyKind};
-
-                    if operands.len() != 2 {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "RawPtr aggregate expected 2 operands (data, metadata), found {}",
-                                operands.len()
-                            ))
-                        );
-                    }
-
-                    let origin = facts::pointer_origin_of_raw_mutability(*mutability);
-                    let is_mutable = origin.is_mutable();
-
-                    match pointee_ty.kind() {
-                        TyKind::RigidTy(RigidTy::Slice(elem_ty)) => {
-                            // `*const [T]` / `*mut [T]`: the metadata operand is
-                            // the element count. `*const [T]` translates to
-                            // `MirSliceType` (same runtime layout as `&[T]`), so
-                            // build the fat pointer with `mir.construct_slice`.
-                            let element_type = types::translate_type(ctx, &elem_ty)?;
-
-                            let (data_val, prev_after_data) = translate_operand(
-                                ctx,
-                                body,
-                                &operands[0],
-                                value_map,
-                                block_ptr,
-                                prev_op,
-                                loc.clone(),
-                            )?;
-                            let (len_val, prev_after_len) = translate_operand(
-                                ctx,
-                                body,
-                                &operands[1],
-                                value_map,
-                                block_ptr,
-                                prev_after_data,
-                                loc.clone(),
-                            )?;
-
-                            // The fat pointer's data slot is a generic-addrspace
-                            // pointer. Values coming from shared memory carry
-                            // addrspace(3); normalize them like the struct/array
-                            // arms do.
-                            let expected_ptr_ty: TypeHandle =
-                                facts::mint_generic_ptr_type(ctx, element_type, origin).into();
-                            let (data_val, current_prev_op) =
-                                cast_to_expected_pointer_type_if_needed(
-                                    ctx,
-                                    data_val,
-                                    expected_ptr_ty,
-                                    block_ptr,
-                                    prev_after_len,
-                                    loc.clone(),
-                                );
-
-                            // Coerce the data pointer to the slice element type: a
-                            // reinterpret cast feeding `from_raw_parts` can leave it
-                            // typed to the pre-cast pointee (e.g. `*mut u64` for a
-                            // `[(u64, u64)]` slice), which the fat pointer rejects.
-                            let (data_val, current_prev_op) = coerce_slice_data_pointee(
-                                ctx,
-                                data_val,
-                                element_type,
-                                is_mutable,
-                                block_ptr,
-                                current_prev_op,
-                                loc.clone(),
-                            );
-
-                            let slice_ty = facts::mint_slice_type(ctx, element_type, origin);
-
-                            use dialect_mir::ops::MirConstructSliceOp;
-                            let op = Operation::new(
-                                ctx,
-                                MirConstructSliceOp::get_concrete_op_info(),
-                                vec![slice_ty.into()],
-                                vec![data_val, len_val],
-                                vec![],
-                                0,
-                            );
-                            op.deref_mut(ctx).set_loc(loc);
-
-                            let result = op.deref(ctx).get_result(0);
-
-                            Ok((Some(op), result, current_prev_op))
-                        }
-                        TyKind::RigidTy(RigidTy::Str) => {
-                            // Blocked on `str` having a device-side type
-                            // translation (issue #76).
-                            input_err!(
-                                loc,
-                                TranslationErr::unsupported(
-                                    "RawPtr aggregate with `str` pointee not yet supported \
-                                     (no `str` type translation on device)"
-                                        .to_string()
-                                )
-                            )
-                        }
-                        TyKind::RigidTy(RigidTy::Dynamic(..)) => {
-                            // Trait objects need a vtable, which has no
-                            // device-side story.
-                            input_err!(
-                                loc,
-                                TranslationErr::unsupported(
-                                    "RawPtr aggregate with `dyn Trait` pointee not supported \
-                                     (no vtable support on device)"
-                                        .to_string()
-                                )
-                            )
-                        }
-                        _ => {
-                            // `Sized` pointee: the metadata operand is `()`, so
-                            // the aggregate is just the data pointer re-typed as
-                            // `*const P` / `*mut P`. Confirm the metadata really
-                            // is unit before dropping it; an unsized-tail struct
-                            // pointee would carry real metadata here.
-                            let metadata_ty = operands[1].ty(body.locals()).map_err(|e| {
-                                input_error!(
-                                    loc.clone(),
-                                    TranslationErr::unsupported(format!(
-                                        "Cannot get RawPtr aggregate metadata type: {e}"
-                                    ))
-                                )
-                            })?;
-                            let metadata_is_unit = matches!(
-                                metadata_ty.kind(),
-                                TyKind::RigidTy(RigidTy::Tuple(tys)) if tys.is_empty()
-                            );
-                            if !metadata_is_unit {
-                                return input_err!(
-                                    loc,
-                                    TranslationErr::unsupported(format!(
-                                        "RawPtr aggregate with non-unit metadata of type {:?} \
-                                         not yet supported",
-                                        metadata_ty
-                                    ))
-                                );
-                            }
-
-                            // Translate the target pointer type through the same
-                            // path as the destination local, so the two agree
-                            // (including SharedArray/Barrier special cases).
-                            let raw_ptr_ty_rust =
-                                rustc_public::ty::Ty::new_ptr(*pointee_ty, *mutability);
-                            let target_ty = types::translate_type(ctx, &raw_ptr_ty_rust)?;
-
-                            let (data_val, current_prev_op) = translate_operand(
-                                ctx,
-                                body,
-                                &operands[0],
-                                value_map,
-                                block_ptr,
-                                prev_op,
-                                loc.clone(),
-                            )?;
-
-                            if data_val.get_type(ctx) == target_ty {
-                                // Already the right pointer type: pass through.
-                                Ok((None, data_val, current_prev_op))
-                            } else {
-                                // Pointer re-typing, e.g. `*const ()` data
-                                // pointer becoming `*const P`.
-                                let cast_op = Operation::new(
-                                    ctx,
-                                    MirCastOp::get_concrete_op_info(),
-                                    vec![target_ty],
-                                    vec![data_val],
-                                    vec![],
-                                    0,
-                                );
-                                cast_op.deref_mut(ctx).set_loc(loc);
-                                MirCastOp::new(cast_op)
-                                    .set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-
-                                let result = cast_op.deref(ctx).get_result(0);
-
-                                Ok((Some(cast_op), result, current_prev_op))
-                            }
-                        }
-                    }
-                }
-                _ => {
-                    input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "Aggregate kind {:?} not yet supported",
-                            aggregate_kind
-                        ))
-                    )
-                }
-            }
-        }
-        mir::Rvalue::Discriminant(place) => {
-            // Get the discriminant (tag) from an enum value.
-            //
-            // Two discriminant types can be in play:
-            //   - `native_tag_ty`: the logical result type produced by our
-            //     enum operation. For Direct layouts this is the physical tag
-            //     type; for Niche/Single layouts the operation decodes or
-            //     materializes the logical discriminant directly.
-            //   - `mir_discr_ty`: the type stable-MIR declares for the
-            //     `Rvalue::Discriminant(place)` value itself, via
-            //     `Ty::kind().discriminant_ty()`. This is what rustc uses
-            //     to type the destination local (often `i64`).
-            //
-            // When the two types disagree (normally a narrow Direct tag versus
-            // stable MIR's wider declared type), widen via `mir.cast IntToInt`
-            // so the rvalue matches what stable MIR promised. Without this,
-            // storing the result into its destination slot would fail
-            // verification.
-            use dialect_mir::ops::MirGetDiscriminantOp;
-            use dialect_mir::types::MirEnumType;
-            use pliron::builtin::types::IntegerType;
-            use pliron::printable::Printable;
-
-            let (enum_val, prev_op_after) =
-                translate_place(ctx, body, place, value_map, block_ptr, prev_op, loc.clone())?;
-
-            let enum_ty = enum_val.get_type(ctx);
-            let (native_tag_ty, enum_is_uninhabited) = {
-                let enum_ty_obj = enum_ty.deref(ctx);
-                if let Some(enum_type) = enum_ty_obj.downcast_ref::<MirEnumType>() {
-                    let uninhabited = !enum_type
-                        .variant_inhabited
-                        .iter()
-                        .any(|inhabited| *inhabited != 0);
-                    (enum_type.discriminant_type(), uninhabited)
-                } else {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "Discriminant on non-enum type: {}",
-                            enum_ty.disp(ctx)
-                        ))
-                    );
-                }
-            };
-
-            // No value of an uninhabited enum can exist, so this read sits
-            // on a dynamically dead path rustc keeps in MIR (e.g. matching
-            // the residual `ControlFlow<Infallible, NeverShortCircuitResidual>`
-            // inside `array::try_from_fn`). `mir.get_discriminant` refuses
-            // uninhabited enums by verification, so keep the dead path
-            // representable with a typed undef of the declared discriminant
-            // type instead.
-            if enum_is_uninhabited {
-                let declared_discr_ty = place
-                    .ty(body.locals())
-                    .ok()
-                    .and_then(|place_ty| place_ty.kind().discriminant_ty());
-                let undef_ty = match declared_discr_ty {
-                    Some(ty) => super::types::translate_type(ctx, &ty)?,
-                    None => native_tag_ty,
-                };
-                let undef = MirUndefOp::new(ctx, undef_ty).get_operation();
-                undef.deref_mut(ctx).set_loc(loc);
-                let result = undef.deref(ctx).get_result(0);
-                return Ok((Some(undef), result, prev_op_after));
-            }
-
-            let get_disc_op = Operation::new(
-                ctx,
-                MirGetDiscriminantOp::get_concrete_op_info(),
-                vec![native_tag_ty],
-                vec![enum_val],
-                vec![],
-                0,
-            );
-            get_disc_op.deref_mut(ctx).set_loc(loc.clone());
-            let native_result = get_disc_op.deref(ctx).get_result(0);
-
-            // Ask stable-MIR what the declared discriminant type of this
-            // place is. For well-formed MIR on an enum place this should
-            // always succeed; if we can't compute it, fall back to the
-            // native tag (no cast). In the fallback path we preserve the
-            // original contract: the caller inserts `get_disc_op`.
-            let place_ty = place.ty(body.locals()).map_err(|e| {
-                input_error!(
-                    loc.clone(),
-                    TranslationErr::unsupported(format!(
-                        "Failed to resolve place type for Discriminant: {:?}",
-                        e
-                    ))
-                )
-            })?;
-            let declared_discr_ty = place_ty.kind().discriminant_ty();
-
-            let mir_discr_ty = match declared_discr_ty {
-                Some(ty) => super::types::translate_type(ctx, &ty)?,
-                None => {
-                    return Ok((Some(get_disc_op), native_result, prev_op_after));
-                }
-            };
-
-            // Only widen when both sides are integers and differ. Anything
-            // else is either already matched or a dialect-level mismatch
-            // that deserves its own verifier error upstream.
-            let needs_cast = mir_discr_ty != native_tag_ty && {
-                let src = native_tag_ty.deref(ctx);
-                let dst = mir_discr_ty.deref(ctx);
-                src.is::<IntegerType>() && dst.is::<IntegerType>()
-            };
-
-            if !needs_cast {
-                return Ok((Some(get_disc_op), native_result, prev_op_after));
-            }
-
-            // Widening path: we emit two ops (get_discriminant + cast) and
-            // the caller only inserts a single "main" op. Insert both here
-            // and return `None` as the main op so the caller does not try
-            // to re-insert.
-            if let Some(prev) = prev_op_after {
-                get_disc_op.insert_after(ctx, prev);
-            } else {
-                get_disc_op.insert_at_front(block_ptr, ctx);
-            }
-
-            let cast_op = Operation::new(
-                ctx,
-                MirCastOp::get_concrete_op_info(),
-                vec![mir_discr_ty],
-                vec![native_result],
-                vec![],
-                0,
-            );
-            cast_op.deref_mut(ctx).set_loc(loc);
-            MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::IntToInt);
-            cast_op.insert_after(ctx, get_disc_op);
-
-            let result = cast_op.deref(ctx).get_result(0);
-            Ok((None, result, Some(cast_op)))
-        }
-        mir::Rvalue::Repeat(operand, count) => {
-            // Array repeat: [value; N] -> mir.construct_array with N copies of value
-            //
-            // MIR: _1 = Repeat(Constant(0.0f32), 16)
-            // Produces: [0.0, 0.0, 0.0, ...] (16 elements)
-
-            // Extract the count from TyConst
-            let array_size = count.eval_target_usize().map_err(|e| {
-                input_error!(
-                    loc.clone(),
-                    TranslationErr::unsupported(format!(
-                        "Failed to evaluate Repeat count: {:?}",
-                        e
-                    ))
-                )
-            })?;
-
-            // Translate the operand to get the element value
-            let (element_val, prev_op_after_operand) = translate_operand(
-                ctx,
-                body,
-                operand,
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-
-            // Get the element type from the value
-            let element_type = element_val.get_type(ctx);
-
-            // Create element values by repeating the single value
-            let element_values: Vec<Value> =
-                std::iter::repeat_n(element_val, array_size as usize).collect();
-
-            // Create the array type
-            let array_ty = dialect_mir::types::MirArrayType::get(ctx, element_type, array_size);
-
-            // Create mir.construct_array operation
-            let op = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                element_values,
-                vec![],
-                0,
-            );
-            op.deref_mut(ctx).set_loc(loc);
-
-            let result = op.deref(ctx).get_result(0);
-
-            Ok((Some(op), result, prev_op_after_operand))
-        }
-        mir::Rvalue::CopyForDeref(place) => {
-            // CopyForDeref is semantically a place read. Any load or projection
-            // operations emitted by translate_place are already inserted and tracked.
-            //
-            // Note: on the pinned toolchain the MIR optimization pipeline
-            // (copy-prop/GVN) eliminates every CopyForDeref before the
-            // optimized MIR reaches this importer; nested-deref kernels
-            // (`**rr`, including through raw pointers) were probed and none
-            // produce one here today. This arm is defensive coverage so a
-            // future toolchain bump or lower mir-opt-level cannot regress
-            // valid nested-deref kernels into an "unsupported construct"
-            // failure.
-            let (value, last_inserted) =
-                translate_place(ctx, body, place, value_map, block_ptr, prev_op, loc)?;
-
-            Ok((None, value, last_inserted))
-        }
-        mir::Rvalue::Len(place) => input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Rvalue::Len for place {:?} not yet implemented",
-                place
-            ))
-        ),
-        mir::Rvalue::ThreadLocalRef(item) => input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Rvalue::ThreadLocalRef {:?} is not supported in device code",
-                item
-            ))
-        ),
-    }
-}
-
-fn read_float_constant_bits(
-    constant: &mir::ConstOperand,
-    kind_name: &str,
-    byte_width: usize,
-    loc: Location,
-) -> TranslationResult<u128> {
-    let bytes = constant_bytes(constant, kind_name, loc.clone())?;
-
-    if bytes.len() < byte_width {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "{kind_name} constant needs {byte_width} bytes, found {}",
-                bytes.len()
-            ))
-        );
-    }
-
-    Ok(read_uint_from_bytes(&bytes[..byte_width]))
-}
-
-fn translate_float_constant(
-    ctx: &mut Context,
-    constant: &mir::ConstOperand,
-    const_ty: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    use dialect_mir::ops::MirFloatConstantOp;
-    use pliron::builtin::attributes::{FPDoubleAttr, FPSingleAttr};
-
-    /// Bit pattern decoded from the MIR constant, tagged by float width.
-    enum FloatBits {
-        F16(u16),
-        F32(u32),
-        F64(u64),
-    }
-
-    // Decode the constant bytes before allocating the op, so a decode
-    // error cannot leave an orphan operation behind in the context.
-    let bits = if const_ty.deref(ctx).is::<MirFP16Type>() {
-        FloatBits::F16(read_float_constant_bits(constant, "f16", 2, loc.clone())? as u16)
-    } else if const_ty.deref(ctx).is::<FP32Type>() {
-        FloatBits::F32(read_float_constant_bits(constant, "f32", 4, loc.clone())? as u32)
-    } else if const_ty.deref(ctx).is::<FP64Type>() {
-        FloatBits::F64(read_float_constant_bits(constant, "f64", 8, loc.clone())? as u64)
-    } else {
-        unreachable!("translate_float_constant called with a non-float type");
-    };
-
-    let op = Operation::new(
-        ctx,
-        MirFloatConstantOp::get_concrete_op_info(),
-        vec![const_ty],
-        vec![],
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc.clone());
-
-    let float_op = MirFloatConstantOp::new(op);
-
-    match bits {
-        FloatBits::F16(bits) => {
-            float_op.set_attr_float_value_f16(ctx, MirFP16Attr::from_bits(bits));
-        }
-        FloatBits::F32(bits) => {
-            float_op.set_attr_float_value(ctx, FPSingleAttr::from(f32::from_bits(bits)));
-        }
-        FloatBits::F64(bits) => {
-            float_op.set_attr_float_value_f64(ctx, FPDoubleAttr::from(f64::from_bits(bits)));
-        }
-    }
-
-    if let Some(prev) = prev_op {
-        float_op.get_operation().insert_after(ctx, prev);
-    } else {
-        float_op.get_operation().insert_at_front(block_ptr, ctx);
-    }
-
-    let value = float_op.get_operation().deref(ctx).get_result(0);
-    Ok((value, Some(float_op.get_operation())))
-}
-
-/// Translate a MIR Operand to a pliron IR [`Value`].
-/// Returns the value and the last inserted operation (for proper ordering).
-///
-/// Handles Copy, Move (via translate_place) and Constant operands.
-pub fn translate_operand(
-    ctx: &mut Context,
-    body: &mir::Body,
-    operand: &mir::Operand,
-    value_map: &mut ValueMap,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    match operand {
-        mir::Operand::Copy(place) | mir::Operand::Move(place) => {
-            // Get the value from the place
-            translate_place(ctx, body, place, value_map, block_ptr, prev_op, loc)
-        }
-        mir::Operand::Constant(constant) => {
-            // Get the Rust type of this constant
-            let rust_ty = constant.ty();
-
-            // Check if this is a pointer to SharedArray (static shared memory)
-            if is_shared_array_pointer(&rust_ty) {
-                // Extract element type, size, and alignment from SharedArray<T, N, ALIGN>
-                let (elem_ty, array_size, alignment) = extract_shared_array_info(ctx, &rust_ty)?;
-
-                // Allocation creates physical storage with Erased provenance.
-                // The Rust constant's exact reference/raw-pointer kind is
-                // established explicitly after the producer.
-                let declared_ptr_ty = types::translate_type(ctx, &rust_ty)?;
-                let storage_ptr_ty =
-                    erase_thin_pointer_kind(ctx, declared_ptr_ty).ok_or_else(|| {
-                        input_error_noloc!(TranslationErr::unsupported(
-                            "SharedArray constant did not translate to a thin pointer type"
-                        ))
-                    })?;
-
-                // Create a MirSharedAllocOp to represent the shared memory allocation
-                // This will be lowered to an LLVM global with addrspace(3)
-                //
-                // NOTE: We include the alloc key in the operation so the LLVM lowering
-                // phase can deduplicate multiple references to the same static.
-                use dialect_mir::ops::MirSharedAllocOp;
-                let op = Operation::new(
-                    ctx,
-                    MirSharedAllocOp::get_concrete_op_info(),
-                    vec![storage_ptr_ty],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                op.deref_mut(ctx).set_loc(loc.clone());
-
-                let shared_alloc = MirSharedAllocOp::new(op);
-
-                // Set the element type, size, and alloc key attributes
-                use pliron::builtin::attributes::{IntegerAttr, StringAttr, TypeAttr};
-                shared_alloc.set_attr_elem_type(ctx, TypeAttr::new(elem_ty));
-                let size_attr = IntegerAttr::new(
-                    pliron::builtin::types::IntegerType::get(
-                        ctx,
-                        64,
-                        pliron::builtin::types::Signedness::Signless,
-                    ),
-                    pliron::utils::apint::APInt::from_u64(
-                        array_size as u64,
-                        std::num::NonZeroUsize::new(64).unwrap(),
-                    ),
-                );
-                shared_alloc.set_attr_size(ctx, size_attr);
-
-                // Full debug resolves an injective static key.  Off and line
-                // tables deliberately retain the historical allocation key and
-                // avoid the extra stable-MIR identity work entirely.
-                let source_identity = value_map
-                    .debug_variables()
-                    .then(|| shared_static_source_identity(constant))
-                    .flatten();
-                let alloc_key = if let Some(identity) = &source_identity {
-                    identity.key.clone()
-                } else {
-                    format!("{:?}", constant.const_)
-                };
-                shared_alloc.set_attr_alloc_key(ctx, StringAttr::new(alloc_key));
-
-                // Record which Rust `static` this is. The alloc key above is
-                // opaque and lowering mints an anonymous `__shared_mem_N`
-                // symbol, so without this the generated shared-memory blocks
-                // cannot be attributed back to source.
-                if let Some(identity) = source_identity {
-                    shared_alloc.set_attr_source_name(ctx, StringAttr::new(identity.name));
-                    shared_alloc.set_attr_source_key(ctx, StringAttr::new(identity.key));
-                } else if let Some(source_name) = shared_static_source_name(constant) {
-                    shared_alloc.set_attr_source_name(ctx, StringAttr::new(source_name));
-                }
-
-                // Set alignment if specified (non-zero)
-                if alignment > 0 {
-                    shared_alloc.set_alignment_value(ctx, alignment as u64);
-                }
-
-                if let Some(prev) = prev_op {
-                    shared_alloc.get_operation().insert_after(ctx, prev);
-                } else {
-                    shared_alloc.get_operation().insert_at_front(block_ptr, ctx);
-                }
-
-                let storage = shared_alloc.get_operation().deref(ctx).get_result(0);
-                let (value, last_op) = cast_to_declared_rust_pointer_type_if_needed(
-                    ctx,
-                    storage,
-                    declared_ptr_ty,
-                    block_ptr,
-                    Some(shared_alloc.get_operation()),
-                    loc.clone(),
-                    MirPointerKindAuthorityAttr::StaticAddress,
-                );
-
-                return Ok((value, last_op));
-            }
-
-            // Check if this is a pointer to Barrier (static barrier in shared memory)
-            if is_barrier_pointer(&rust_ty) {
-                // Barrier is a single 64-bit value in shared memory (mbarrier state)
-                let elem_ty = pliron::builtin::types::IntegerType::get(
-                    ctx,
-                    64,
-                    pliron::builtin::types::Signedness::Unsigned,
-                )
-                .into();
-
-                // Keep the allocation itself Erased, then establish the Rust
-                // constant's declared pointer category at a visible boundary.
-                let declared_ptr_ty = types::translate_type(ctx, &rust_ty)?;
-                let storage_ptr_ty =
-                    erase_thin_pointer_kind(ctx, declared_ptr_ty).ok_or_else(|| {
-                        input_error_noloc!(TranslationErr::unsupported(
-                            "Barrier constant did not translate to a thin pointer type"
-                        ))
-                    })?;
-
-                // Create a MirSharedAllocOp for the barrier
-                use dialect_mir::ops::MirSharedAllocOp;
-                let op = Operation::new(
-                    ctx,
-                    MirSharedAllocOp::get_concrete_op_info(),
-                    vec![storage_ptr_ty],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                op.deref_mut(ctx).set_loc(loc.clone());
-
-                let shared_alloc = MirSharedAllocOp::new(op);
-
-                // Set attributes: element type (i64), size (1 element)
-                use pliron::builtin::attributes::{IntegerAttr, StringAttr, TypeAttr};
-                shared_alloc.set_attr_elem_type(ctx, TypeAttr::new(elem_ty));
-                let size_attr = IntegerAttr::new(
-                    pliron::builtin::types::IntegerType::get(
-                        ctx,
-                        64,
-                        pliron::builtin::types::Signedness::Signless,
-                    ),
-                    pliron::utils::apint::APInt::from_u64(
-                        1, // Single barrier element
-                        std::num::NonZeroUsize::new(64).unwrap(),
-                    ),
-                );
-                shared_alloc.set_attr_size(ctx, size_attr);
-
-                let source_identity = value_map
-                    .debug_variables()
-                    .then(|| shared_static_source_identity(constant))
-                    .flatten();
-                let alloc_key = if let Some(identity) = &source_identity {
-                    identity.key.clone()
-                } else {
-                    format!("{:?}", constant.const_)
-                };
-                shared_alloc.set_attr_alloc_key(ctx, StringAttr::new(alloc_key));
-
-                // A `Barrier` static occupies shared memory too, so name it
-                // for the same attribution reason as `SharedArray` above.
-                if let Some(identity) = source_identity {
-                    shared_alloc.set_attr_source_name(ctx, StringAttr::new(identity.name));
-                    shared_alloc.set_attr_source_key(ctx, StringAttr::new(identity.key));
-                } else if let Some(source_name) = shared_static_source_name(constant) {
-                    shared_alloc.set_attr_source_name(ctx, StringAttr::new(source_name));
-                }
-
-                if let Some(prev) = prev_op {
-                    shared_alloc.get_operation().insert_after(ctx, prev);
-                } else {
-                    shared_alloc.get_operation().insert_at_front(block_ptr, ctx);
-                }
-
-                let storage = shared_alloc.get_operation().deref(ctx).get_result(0);
-                let (value, last_op) = cast_to_declared_rust_pointer_type_if_needed(
-                    ctx,
-                    storage,
-                    declared_ptr_ty,
-                    block_ptr,
-                    Some(shared_alloc.get_operation()),
-                    loc.clone(),
-                    MirPointerKindAuthorityAttr::StaticAddress,
-                );
-
-                return Ok((value, last_op));
-            }
-
-            // Ordinary Rust `static` / `static mut` values in device code live in
-            // CUDA global memory (addrspace 1) by default. SharedArray/Barrier
-            // statics have already been intercepted above and remain addrspace 3.
-            // Statics tagged `#[constant]` (detected by the mangled symbol
-            // prefix) instead lower into constant memory (addrspace 4).
-            if let Some((pointee_ty, origin)) = get_static_pointer_info(&rust_ty)
-                && let Some(static_target) = static_target_from_constant(constant, loc.clone())?
-            {
-                let is_mutable = origin.is_mutable();
-                let static_ty = static_target.static_def.ty();
-                let pointee_mir_ty = types::translate_type(ctx, &pointee_ty)?;
-                let static_mir_ty = types::translate_type(ctx, &static_ty)?;
-
-                // A zero addend may name either the whole static or a subobject
-                // at byte zero (for example `&ARRAY[0]` or `&STRUCT.first`).
-                // Array→slice unsize remains special because it needs a fat
-                // pointer carrying the evaluated metadata word. Other sized
-                // pointees continue through byte-address normalization below.
-                if static_target.byte_offset == 0
-                    && pointee_mir_ty != static_mir_ty
-                    && let Some((elem_ty, array_len)) =
-                        array_to_slice_unsize_info(&static_ty, &pointee_ty, loc.clone())?
-                {
-                    // The emitted length is the constant's own metadata
-                    // word, not the array's N: a zero-addend prefix
-                    // subslice (`split_at(k).0` over the static) stores
-                    // k there. The array length only bounds it.
-                    let len = slice_len_from_constant(constant, loc.clone())?;
-                    if len > array_len {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "constant slice over device static {} stores length {}, \
-                                 which exceeds the static array's length {}",
-                                static_target.static_def.name(),
-                                len,
-                                array_len
-                            ))
-                        );
-                    }
-                    return translate_static_array_as_slice(
-                        ctx,
-                        &static_target.static_def,
-                        elem_ty,
-                        len,
-                        origin,
-                        0,
-                        block_ptr,
-                        prev_op,
-                        loc.clone(),
-                    );
-                }
-
-                if static_target.byte_offset != 0
-                    && let Some((elem_ty, remaining_len)) = interior_array_to_slice_unsize_info(
-                        &static_ty,
-                        &pointee_ty,
-                        static_target.byte_offset,
-                        loc.clone(),
-                    )?
-                {
-                    let len = slice_len_from_constant(constant, loc.clone())?;
-
-                    if len > remaining_len {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "constant slice over device static {} stores length {}, \
-                                 which exceeds the selected array region's remaining length {}",
-                                static_target.static_def.name(),
-                                len,
-                                remaining_len,
-                            ))
-                        );
-                    }
-
-                    return translate_static_array_as_slice(
-                        ctx,
-                        &static_target.static_def,
-                        elem_ty,
-                        len,
-                        origin,
-                        static_target.byte_offset,
-                        block_ptr,
-                        prev_op,
-                        loc.clone(),
-                    );
-                }
-
-                // Every remaining path emits a thin pointer, including a
-                // zero-addend pointer to a first field/element. A slice, str,
-                // trait object, or another DST requires metadata and cannot be
-                // represented here. Note that `layout()` succeeds for DSTs
-                // such as `[f32]`, so check the returned shape explicitly.
-                let pointee_layout = pointee_ty.layout().map_err(|e| {
-                    input_error!(
-                        loc.clone(),
-                        TranslationErr::unsupported(format!(
-                            "constant pointer into device static {} has byte offset {}, \
-                             but pointee type {:?} does not have a sized layout: {:?}",
-                            static_target.static_def.name(),
-                            static_target.byte_offset,
-                            pointee_ty,
-                            e
-                        ))
-                    )
-                })?;
-                if !pointee_layout.shape().is_sized() {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "constant pointer into device static {} has byte offset {}, \
-                             but pointee type {:?} is unsized; cuda-oxide does not yet \
-                             preserve the fat-pointer metadata this slice or DST pointer needs",
-                            static_target.static_def.name(),
-                            static_target.byte_offset,
-                            pointee_ty
-                        ))
-                    );
-                }
-
-                // The materialized constant pointer must carry the exact
-                // translated Rust operand type. Slot stores and mem2reg are
-                // type-strict, so shapes like `_1 = const &STATIC;
-                // &(*_1).field` need the operand normalized here rather
-                // than leaving the physical-address-space pointer type
-                // exposed to the rest of the function body.
-                let result_ptr_ty = types::translate_type(ctx, &rust_ty)?;
-
-                return translate_static_global_pointer(
-                    ctx,
-                    &static_target.static_def,
-                    pointee_mir_ty,
-                    result_ptr_ty,
-                    is_mutable,
-                    static_target.byte_offset,
-                    block_ptr,
-                    prev_op,
-                    loc.clone(),
-                );
-            }
-
-            let const_ty_ptr = types::translate_type(ctx, &rust_ty)?;
-
-            // `RangeToken<R>` is intentionally a Rust ZST. Optimized MIR can
-            // therefore materialize a token operand as an independent ZST
-            // constant instead of preserving the call-result SSA edge. Keep a
-            // well-typed semantic placeholder here; the frontend-provided
-            // static range key pairs range_start/range_end during lowering.
-            if const_ty_ptr.deref(ctx).is::<IketRangeTokenType>() {
-                let op = IketSentinelTokenOp::new(ctx).get_operation();
-                op.deref_mut(ctx).set_loc(loc);
-                if let Some(prev) = prev_op {
-                    op.insert_after(ctx, prev);
-                } else {
-                    op.insert_at_front(block_ptr, ctx);
-                }
-                return Ok((op.deref(ctx).get_result(0), Some(op)));
-            }
-
-            // ZSTs have no runtime bytes, but they still need a value with the
-            // exact translated type. This is critical for marker structs,
-            // unit, and zero-sized unions.
-            if types::is_zst_type(ctx, const_ty_ptr) {
-                return translate_zero_sized_constant_value(
-                    ctx,
-                    const_ty_ptr,
-                    block_ptr,
-                    prev_op,
-                    loc,
-                );
-            }
-
-            // A fully-uninitialized constant allocation (`MaybeUninit::uninit()`
-            // and similar: every byte uninit, no provenance) has no defined
-            // bytes to materialize for any type; its value is `undef`.
-            if let ConstantKind::Allocated(alloc) = constant.const_.kind()
-                && !alloc.bytes.is_empty()
-                && alloc.bytes.iter().all(|b| b.is_none())
-                && alloc.provenance.ptrs.is_empty()
-            {
-                use dialect_mir::ops::MirUndefOp;
-                let op = MirUndefOp::new(ctx, const_ty_ptr).get_operation();
-                op.deref_mut(ctx).set_loc(loc);
-                if let Some(prev) = prev_op {
-                    op.insert_after(ctx, prev);
-                } else {
-                    op.insert_at_front(block_ptr, ctx);
-                }
-                return Ok((op.deref(ctx).get_result(0), Some(op)));
-            }
-
-            // Check if this is a struct type (non-ZST)
-            // For struct constants, we need to construct the struct from its field values.
-            let is_struct = const_ty_ptr
-                .deref(ctx)
-                .is::<dialect_mir::types::MirStructType>();
-            let is_tuple = const_ty_ptr
-                .deref(ctx)
-                .is::<dialect_mir::types::MirTupleType>();
-
-            // Check if this is a float type (f16, f32, or f64)
-            let is_float_16 = const_ty_ptr.deref(ctx).is::<MirFP16Type>();
-            let is_float_32 = const_ty_ptr.deref(ctx).is::<FP32Type>();
-            let is_float_64 = const_ty_ptr.deref(ctx).is::<FP64Type>();
-            let is_float = is_float_16 || is_float_32 || is_float_64;
-
-            // Check if this is an enum type
-            let is_enum = const_ty_ptr
-                .deref(ctx)
-                .is::<dialect_mir::types::MirEnumType>();
-            let is_union = const_ty_ptr
-                .deref(ctx)
-                .is::<dialect_mir::types::MirUnionType>();
-
-            // Check if this is a pointer to an array (byte strings, or typed arrays like [f64; 3])
-            let is_ptr_to_array = const_ty_ptr
-                .deref(ctx)
-                .downcast_ref::<dialect_mir::types::MirPtrType>()
-                .map(|ptr_ty| {
-                    ptr_ty
-                        .pointee
-                        .deref(ctx)
-                        .is::<dialect_mir::types::MirArrayType>()
-                })
-                .unwrap_or(false);
-
-            // Check if this is a bare array value constant (e.g. `const TABLE: [f32; N]`
-            // referenced as `TABLE[runtime_idx]`, which materialises the whole array
-            // as an operand rather than a pointer to it).
-            let is_array_value = const_ty_ptr
-                .deref(ctx)
-                .is::<dialect_mir::types::MirArrayType>();
-
-            if is_float {
-                return translate_float_constant(
-                    ctx,
-                    constant,
-                    const_ty_ptr,
-                    block_ptr,
-                    prev_op,
-                    loc,
-                );
-            }
-
-            // Debug repr kept for diagnostics only (CUDA_OXIDE_DEBUG_CONST and
-            // the unsupported-constant error at the bottom); constant VALUES
-            // are read through typed rustc_public APIs, never parsed from it.
-            let const_str = format!("{:?}", constant.const_);
-
-            // Handle pointer-to-array constants (byte strings, typed arrays like [f64; 3], etc.)
-            if is_ptr_to_array {
-                return translate_ptr_to_array_constant(
-                    ctx,
-                    constant,
-                    const_ty_ptr,
-                    block_ptr,
-                    prev_op,
-                    loc,
-                );
-            }
-
-            // Handle bare array value constants (e.g. `TABLE[runtime_idx]` where
-            // `TABLE: [f32; N]` materialises the whole array by value).
-            if is_array_value {
-                return translate_array_value_constant(
-                    ctx,
-                    constant,
-                    const_ty_ptr,
-                    block_ptr,
-                    prev_op,
-                    loc,
-                );
-            }
-
-            if is_struct {
-                // Non-ZST struct constant - extract field values and construct the struct
-                translate_struct_constant(
-                    ctx,
-                    constant,
-                    &rust_ty,
-                    const_ty_ptr,
-                    block_ptr,
-                    prev_op,
-                    loc,
-                )
-            } else if is_tuple {
-                translate_tuple_constant(
-                    ctx,
-                    constant,
-                    &rust_ty,
-                    const_ty_ptr,
-                    block_ptr,
-                    prev_op,
-                    loc,
-                )
-            } else if is_enum {
-                translate_enum_constant(
-                    ctx,
-                    constant,
-                    &rust_ty,
-                    const_ty_ptr,
-                    block_ptr,
-                    prev_op,
-                    loc,
-                )
-            } else if is_union {
-                translate_union_constant(
-                    ctx,
-                    constant,
-                    &rust_ty,
-                    const_ty_ptr,
-                    block_ptr,
-                    prev_op,
-                    loc,
-                )
-            } else if const_ty_ptr
-                .deref(ctx)
-                .is::<dialect_mir::types::MirPtrType>()
-            {
-                // Pointer type constant - could be:
-                // 1. A raw pointer constant (like core::ptr::null()) - just bytes,
-                //    no provenance
-                // 2. A reference to a constant struct (like &(8..16)) - need
-                //    struct + mir.ref
-                // 3. A reference to any other promoted constant (like the `&77`
-                //    that -O const-folds out of `Option<&u32>::unwrap_or(&77)`,
-                //    issue #132) - follow the allocation provenance, materialize
-                //    the pointee constant, then mir.ref
-                //
-                // Only constants WITHOUT provenance may take the raw-pointer
-                // path; a provenance entry always names a real allocation, and
-                // ignoring it would lower the reference to `inttoptr 0` (a null
-                // pointer).
-
-                // Extract pointer type info before further borrows
-                let (pointee_ty, is_mutable, pointee_is_struct) = {
-                    let ty_ref = const_ty_ptr.deref(ctx);
-                    let ptr_ty = ty_ref
-                        .downcast_ref::<dialect_mir::types::MirPtrType>()
-                        .unwrap();
-                    let pointee = ptr_ty.pointee;
-                    let mutable = ptr_ty.is_mutable;
-                    let is_struct = pointee.deref(ctx).is::<dialect_mir::types::MirStructType>();
-                    (pointee, mutable, is_struct)
-                };
-
-                // Check if the constant has actual struct data (not all zeros)
-                // Handle both Allocated constants and promoted constants (Ty variant)
-                //
-                // Debug: print constant info for reference-to-struct types
-                if pointee_is_struct && std::env::var("CUDA_OXIDE_DEBUG_CONST").is_ok() {
-                    eprintln!(
-                        "[DEBUG] Ptr-to-struct constant: kind={:?}, str={:?}",
-                        constant.const_.kind(),
-                        const_str
-                    );
-                }
-
-                let has_struct_data = if pointee_is_struct {
-                    match constant.const_.kind() {
-                        ConstantKind::Allocated(alloc) => {
-                            // For promoted constants like &(8..16), the bytes are zeros
-                            // (pointer placeholder) but provenance indicates a real allocation.
-                            // Check for provenance OR non-zero bytes.
-                            let has_provenance = !alloc.provenance.ptrs.is_empty();
-                            let has_nonzero_bytes = alloc
-                                .raw_bytes()
-                                .ok()
-                                .map(|bytes| bytes.iter().any(|&b| b != 0))
-                                .unwrap_or(false);
-                            has_provenance || has_nonzero_bytes
-                        }
-                        ConstantKind::Ty(_) => {
-                            // Promoted constants (like &(8..16)) are Ty variants
-                            // These contain the actual struct data
-                            true
-                        }
-                        _ => false,
-                    }
-                } else {
-                    false
-                };
-
-                if has_struct_data {
-                    // This is a reference to a constant struct (like &(8..16))
-
-                    // Create the struct constant, then use mir.ref to get a pointer
-                    let (struct_val, last_op) = translate_struct_constant(
-                        ctx,
-                        constant,
-                        &rust_ty,
-                        pointee_ty,
-                        block_ptr,
-                        prev_op,
-                        loc.clone(),
-                    )?;
-
-                    // Now create mir.ref to get a pointer to the struct
-                    use dialect_mir::ops::MirRefOp;
-                    let ref_op = Operation::new(
-                        ctx,
-                        MirRefOp::get_concrete_op_info(),
-                        vec![const_ty_ptr], // Result is pointer to struct
-                        vec![struct_val],   // Operand is the struct value
-                        vec![],
-                        0,
-                    );
-                    ref_op.deref_mut(ctx).set_loc(loc);
-
-                    let mir_ref = MirRefOp::new(ref_op);
-
-                    mir_ref
-                        .set_attr_mutable(ctx, dialect_mir::attributes::MutabilityAttr(is_mutable));
-                    mir_ref.set_pointer_kind_authority(
-                        ctx,
-                        MirPointerKindAuthorityAttr::StaticAddress,
-                    );
-
-                    if let Some(prev) = last_op {
-                        mir_ref.get_operation().insert_after(ctx, prev);
-                    } else {
-                        mir_ref.get_operation().insert_at_front(block_ptr, ctx);
-                    }
-
-                    let ptr_val = mir_ref.get_operation().deref(ctx).get_result(0);
-                    return Ok((ptr_val, Some(mir_ref.get_operation())));
-                }
-
-                // Reference to a non-struct promoted constant (issue #132).
-                //
-                // Under -O, MIR const-folds e.g. the `None` arm of
-                // `Option<&u32>::unwrap_or(&77)` into a constant of type `&u32`
-                // whose data bytes are a pointer placeholder and whose
-                // provenance entry names the allocation holding the literal
-                // `77`. Struct pointees were already handled above; follow the
-                // provenance for every other pointee type too, materialize the
-                // pointee through the shared constant-from-bytes path, and take
-                // its address with mir.ref (mem2reg/lowering turn that into an
-                // alloca + store + address; sound because promoted constants
-                // are immutable).
-                let backing_alloc: Option<&rustc_public::ty::Allocation> =
-                    match constant.const_.kind() {
-                        ConstantKind::Allocated(alloc) => Some(alloc),
-                        ConstantKind::Ty(ty_const) => match ty_const.kind() {
-                            rustc_public::ty::TyConstKind::Value(_, alloc) => Some(alloc),
-                            _ => None,
-                        },
-                        _ => None,
-                    };
-
-                if let Some(alloc) = backing_alloc
-                    && let Some(&(prov_pos, prov)) = alloc.provenance.ptrs.first()
-                {
-                    use rustc_public::mir::alloc::GlobalAlloc;
-                    let alloc_id = prov.0;
-
-                    // The pointer's own data bytes encode the byte offset into
-                    // the target allocation (zero for plain promoted literals
-                    // like `&77`). The struct/array provenance branches assume
-                    // offset zero; here the slice below honors a non-zero
-                    // offset, and an unreadable offset is a hard error rather
-                    // than a silently wrong address.
-                    let ptr_width =
-                        rustc_public::target::MachineInfo::target_pointer_width().bytes();
-                    let target_offset = alloc
-                        .read_partial_uint(prov_pos..prov_pos + ptr_width)
-                        .map_err(|e| {
-                            input_error_noloc!(TranslationErr::unsupported(format!(
-                                "Failed to read pointer constant provenance offset: {:?}",
-                                e
-                            )))
-                        })? as usize;
-
-                    // The pointee is decoded from raw bytes below, with no
-                    // provenance map to resolve pointers nested inside it, so
-                    // a pointee that itself contains relocations must fail
-                    // loudly before its placeholder bytes decode as addresses.
-                    let reject_pointee_relocations = |relocations: usize| -> TranslationResult<()> {
-                        if relocations != 0 {
-                            return input_err!(
-                                loc.clone(),
-                                TranslationErr::unsupported(format!(
-                                    "Promoted constant's pointee contains {relocations} pointer \
-                                         relocation(s); cuda-oxide cannot yet preserve nested \
-                                         pointer provenance"
-                                ))
-                            );
-                        }
-                        Ok(())
-                    };
-                    let target_bytes: Vec<u8> = match GlobalAlloc::from(alloc_id) {
-                        GlobalAlloc::Memory(target_alloc) => {
-                            reject_pointee_relocations(target_alloc.provenance.ptrs.len())?;
-                            target_alloc.raw_bytes().ok().unwrap_or_else(|| {
-                                target_alloc
-                                    .bytes
-                                    .iter()
-                                    .map(|opt: &Option<u8>| opt.unwrap_or(0))
-                                    .collect::<Vec<u8>>()
-                            })
-                        }
-                        GlobalAlloc::Static(static_def) => {
-                            let target_alloc = static_def.eval_initializer().map_err(|e| {
-                                input_error_noloc!(TranslationErr::unsupported(format!(
-                                    "Failed to evaluate static initializer for pointer constant: {:?}",
-                                    e
-                                )))
-                            })?;
-                            reject_pointee_relocations(target_alloc.provenance.ptrs.len())?;
-                            target_alloc.raw_bytes().ok().unwrap_or_else(|| {
-                                target_alloc
-                                    .bytes
-                                    .iter()
-                                    .map(|opt: &Option<u8>| opt.unwrap_or(0))
-                                    .collect::<Vec<u8>>()
-                            })
-                        }
-                        other => {
-                            return input_err!(
-                                loc,
-                                TranslationErr::unsupported(format!(
-                                    "Pointer constant provenance points to non-memory allocation: {:?}",
-                                    other
-                                ))
-                            );
-                        }
-                    };
-
-                    if target_offset > target_bytes.len() {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "Pointer constant provenance offset {} exceeds target allocation size {}",
-                                target_offset,
-                                target_bytes.len()
-                            ))
-                        );
-                    }
-
-                    // The shared materializer needs the pointee's Rust type for
-                    // enum-layout queries and ZST detection.
-                    let Some((pointee_rust_ty, _)) = get_static_pointer_info(&rust_ty) else {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "Pointer constant with provenance has unsupported Rust type: {:?}",
-                                rust_ty
-                            ))
-                        );
-                    };
-
-                    let (pointee_val, last_op) = translate_constant_value_from_bytes(
-                        ctx,
-                        &pointee_rust_ty,
-                        pointee_ty,
-                        &target_bytes[target_offset..],
-                        block_ptr,
-                        prev_op,
-                        loc.clone(),
-                    )?;
-
-                    // Take the address of the materialized value, exactly like
-                    // the struct branch above.
-                    let ref_op = Operation::new(
-                        ctx,
-                        MirRefOp::get_concrete_op_info(),
-                        vec![const_ty_ptr], // Result is pointer to the pointee
-                        vec![pointee_val],  // Operand is the materialized value
-                        vec![],
-                        0,
-                    );
-                    ref_op.deref_mut(ctx).set_loc(loc);
-
-                    let mir_ref = MirRefOp::new(ref_op);
-                    mir_ref
-                        .set_attr_mutable(ctx, dialect_mir::attributes::MutabilityAttr(is_mutable));
-                    mir_ref.set_pointer_kind_authority(
-                        ctx,
-                        MirPointerKindAuthorityAttr::StaticAddress,
-                    );
-
-                    if let Some(prev) = last_op {
-                        mir_ref.get_operation().insert_after(ctx, prev);
-                    } else {
-                        mir_ref.get_operation().insert_at_front(block_ptr, ctx);
-                    }
-
-                    let ptr_val = mir_ref.get_operation().deref(ctx).get_result(0);
-                    return Ok((ptr_val, Some(mir_ref.get_operation())));
-                }
-
-                // Raw pointer constant (like core::ptr::null()).
-                //
-                // Only reachable for constants WITHOUT provenance (true null or
-                // int-to-ptr values); provenance-carrying constants returned
-                // above. Create an integer constant with the pointer value
-                // (0 for null), then convert it to a pointer type using
-                // MirCastOp
-                use dialect_mir::ops::MirCastOp;
-
-                // No provenance, so the data bytes ARE the address. Read the
-                // first pointer-width bytes as a target-endian uint:
-                //
-                //   bytes: [00 00 00 00 00 00 00 00] -> 0x00 (null)
-                //   bytes: [2a 00 00 00 00 00 00 00] -> 0x2a (without_provenance(42))
-                //
-                // A constant with no backing allocation, too few bytes, or an
-                // uninit byte in the range has no readable address; post-mono
-                // MIR should never produce that here, so fail loudly instead
-                // of defaulting to null.
-                let Some(alloc) = backing_alloc else {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "raw pointer constant has no backing allocation to read an \
-                             address from (constant kind: {:?})",
-                            constant.const_.kind()
-                        ))
-                    );
-                };
-                debug_assert!(
-                    alloc.provenance.ptrs.is_empty(),
-                    "provenance-carrying pointer constants must return earlier"
-                );
-                let ptr_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-                let ptr_val = alloc.read_partial_uint(0..ptr_width).map_err(|e| {
-                    input_error_noloc!(TranslationErr::unsupported(format!(
-                        "raw pointer constant needs {ptr_width} initialized address \
-                         bytes, but reading them failed: {e:?}"
-                    )))
-                })? as u64;
-
-                // Create integer constant (i64) for the pointer value
-                let i64_ty = pliron::builtin::types::IntegerType::get(
-                    ctx,
-                    64,
-                    pliron::builtin::types::Signedness::Signless,
-                );
-                let apint = APInt::from_u64(ptr_val, NonZeroUsize::new(64).unwrap());
-                let int_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, apint);
-
-                use dialect_mir::ops::MirConstantOp;
-                let int_op = Operation::new(
-                    ctx,
-                    MirConstantOp::get_concrete_op_info(),
-                    vec![i64_ty.into()],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                int_op.deref_mut(ctx).set_loc(loc.clone());
-
-                let const_op = MirConstantOp::new(int_op);
-                const_op.set_attr_value(ctx, int_attr);
-
-                if let Some(prev) = prev_op {
-                    const_op.get_operation().insert_after(ctx, prev);
-                } else {
-                    const_op.get_operation().insert_at_front(block_ptr, ctx);
-                }
-
-                let int_val = const_op.get_operation().deref(ctx).get_result(0);
-
-                // Cast integer to pointer type using MirCastOp
-                let cast_op = Operation::new(
-                    ctx,
-                    MirCastOp::get_concrete_op_info(),
-                    vec![const_ty_ptr], // Result is the pointer type
-                    vec![int_val],      // Operand is the integer value
-                    vec![],
-                    0,
-                );
-                cast_op.deref_mut(ctx).set_loc(loc);
-                let cast = MirCastOp::new(cast_op);
-                cast.set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
-                if dialect_mir::types::type_contains_concrete_pointer_kind(ctx, const_ty_ptr) {
-                    cast.set_pointer_kind_authority(
-                        ctx,
-                        MirPointerKindAuthorityAttr::StaticAddress,
-                    );
-                }
-
-                cast_op.insert_after(ctx, const_op.get_operation());
-
-                let ptr_val_result = cast_op.deref(ctx).get_result(0);
-
-                Ok((ptr_val_result, Some(cast_op)))
-            } else if const_ty_ptr.deref(ctx).is::<IntegerType>() {
-                // Integer constant
-                let (width_val, signedness) = {
-                    let const_ty_obj = const_ty_ptr.deref(ctx);
-                    let int_ty = const_ty_obj
-                        .downcast_ref::<IntegerType>()
-                        .expect("already checked is::<IntegerType>()");
-                    (int_ty.width(), int_ty.signedness())
-                };
-
-                let byte_size = (width_val as usize).div_ceil(8);
-
-                // Walk to the backing allocation directly instead of going
-                // through `constant_bytes`: that helper zero-fills uninit
-                // bytes, and an integer's value bytes must all be present.
-                //
-                //   bytes: [ff 7f] -> 0x7fff  (fine)
-                //   bytes: [-- 7f] -> error   (uninit byte, not 0x7f00)
-                //
-                // No fallback: a constant we cannot read here is a compiler
-                // bug, never a zero.
-                let alloc = match constant.const_.kind() {
-                    ConstantKind::Allocated(alloc) => alloc,
-                    ConstantKind::Ty(ty_const) => match ty_const.kind() {
-                        rustc_public::ty::TyConstKind::Value(_, alloc) => alloc,
-                        other => {
-                            return input_err!(
-                                loc,
-                                TranslationErr::unsupported(format!(
-                                    "integer constant is not an evaluated value \
-                                     (TyConstKind::{other:?}), so its bytes cannot be read"
-                                ))
-                            );
-                        }
-                    },
-                    other => {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "integer constant has no byte-backed allocation \
-                                 (constant kind: {other:?})"
-                            ))
-                        );
-                    }
-                };
-                if !alloc.provenance.ptrs.is_empty() {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(
-                            "integer constant carries pointer provenance; its bytes are \
-                             a relocation placeholder, not a number",
-                        )
-                    );
-                }
-                if alloc.bytes.len() < byte_size {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "integer constant has {} data bytes, expected at least \
-                             {byte_size} for i{width_val}",
-                            alloc.bytes.len()
-                        ))
-                    );
-                }
-                let int_val = alloc.read_partial_uint(0..byte_size).map_err(|e| {
-                    input_error_noloc!(TranslationErr::unsupported(format!(
-                        "integer constant has uninitialized bytes in its value range: {e:?}"
-                    )))
-                })?;
-
-                let width = NonZeroUsize::new(width_val as usize).unwrap();
-                let apint = APInt::from_u128(int_val, width);
-
-                let int_attr = pliron::builtin::attributes::IntegerAttr::new(
-                    pliron::builtin::types::IntegerType::get(ctx, width_val, signedness),
-                    apint,
-                );
-
-                use dialect_mir::ops::MirConstantOp;
-                let op = Operation::new(
-                    ctx,
-                    MirConstantOp::get_concrete_op_info(),
-                    vec![const_ty_ptr],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                op.deref_mut(ctx).set_loc(loc);
-
-                let const_op = MirConstantOp::new(op);
-                const_op.set_attr_value(ctx, int_attr);
-
-                if let Some(prev) = prev_op {
-                    const_op.get_operation().insert_after(ctx, prev);
-                } else {
-                    const_op.get_operation().insert_at_front(block_ptr, ctx);
-                }
-
-                let val = const_op.get_operation().deref(ctx).get_result(0);
-
-                Ok((val, Some(const_op.get_operation())))
-            } else {
-                // No matching type handler — report what we got so it's clear what needs support.
-                let pliron_ty_dbg = format!("{:?}", const_ty_ptr.deref(ctx));
-                Err(input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Unsupported constant type in translate_constant.\n\
-                     \n  Rust type : {:?}\
-                     \n  pliron type: {}\
-                     \n  const repr : {}\
-                     \n\
-                     \nThe type dispatch (ZST -> ptr_to_array -> array -> struct -> tuple -> enum -> union -> float -> pointer -> integer)\n\
-                     did not match this constant. A new handler may need to be added.",
-                    rust_ty, pliron_ty_dbg, const_str
-                ))))
-            }
-        }
-        mir::Operand::RuntimeChecks(_) => {
-            // RuntimeChecks variants (UbChecks, ContractChecks, OverflowChecks)
-            // evaluate to `false` on GPU -- runtime safety checks are disabled.
-            //
-            // Emits a `mir.constant false : i1` and inserts it into the current
-            // block. The op *must* be linked before returning; callers use the
-            // returned `last_op` as the insertion point for subsequent ops.
-            use dialect_mir::ops::MirConstantOp;
-            use pliron::builtin::attributes::IntegerAttr;
-            use pliron::builtin::types::{IntegerType, Signedness};
-            use pliron::utils::apint::APInt;
-
-            let bool_ty: TypeHandle = IntegerType::get(ctx, 1, Signedness::Signless).into();
-            let value = APInt::from_u64(
-                u64::from(crate::DEVICE_RUNTIME_CHECKS_VALUE),
-                std::num::NonZeroUsize::new(1).unwrap(),
-            );
-            let const_attr =
-                IntegerAttr::new(IntegerType::get(ctx, 1, Signedness::Signless), value);
-
-            let op = Operation::new(
-                ctx,
-                MirConstantOp::get_concrete_op_info(),
-                vec![bool_ty],
-                vec![],
-                vec![],
-                0,
-            );
-            op.deref_mut(ctx).set_loc(loc);
-
-            let const_op = MirConstantOp::new(op);
-            const_op.set_attr_value(ctx, const_attr);
-
-            match prev_op {
-                Some(p) => op.insert_after(ctx, p),
-                None => op.insert_at_front(block_ptr, ctx),
-            }
-
-            let val = const_op.get_operation().deref(ctx).get_result(0);
-
-            Ok((val, Some(const_op.get_operation())))
-        }
-    }
-}
-
-/// Translate MIR [`Place`](mir::Place) reads to pliron IR SSA [`Value`]s.
-///
-/// Reads for `Copy(place)` and `Move(place)` first ask a side-effect-free
-/// classifier whether the place has a real final load address. Addressable
-/// reads use the same
-/// `translate_place_address` walker as refs, raw addresses, and writes, then
-/// emit one `mir.load` at the end.
-///
-/// Places that are not representable as one final load address use the explicit
-/// value fallback below. The fallback handles value-only projections such as
-/// enum payload extraction, tuple field extraction, ZST reads, and no-slot
-/// locals.
-///
-/// A bare slot-backed local is the trivial addressable case: it reads by
-/// loading the local's alloca slot once. Projected reads compose address
-/// operations for `field`, `index`, and `deref` when the whole projection
-/// chain stays addressable.
-///
-/// # Value fallback and ghost locals
-///
-/// A local may have no backing slot in `value_map` if rustc optimised away its
-/// assignment, or if the local is ZST and has no runtime footprint.
-///
-/// When such a local is still *used* within a block (e.g. `discriminant(_6)`)
-/// and happens to be an enum, we synthesise a variant-0 default via
-/// `create_ghost_enum_default`. Non-enum ghost locals currently produce an
-/// error -- extend this match if new patterns appear in future toolchains.
-///
-/// This is the SSA equivalent of rustc's codegen reading an uninitialized
-/// alloca, which produces LLVM `undef`.
-///
-/// # Returns
-///
-/// `(value, last_inserted_op)` -- the pliron IR value for the place and the last
-/// operation inserted into the block (for op-ordering bookkeeping).
-pub fn translate_place(
-    ctx: &mut Context,
-    body: &mir::Body,
-    place: &mir::Place,
-    value_map: &ValueMap,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    match classify_place_read_strategy(ctx, place, value_map)? {
-        PlaceReadStrategy::Address => {
-            if let Some((value, last_op)) = translate_place_load_from_address(
-                ctx,
-                body,
-                place,
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )? {
-                return Ok((value, last_op));
-            }
-
-            input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "place read {:?} was classified as addressable but did not lower to a \
-                     final load address",
-                    place.projection
-                ))
-            )
-        }
-        PlaceReadStrategy::ValueFallback => {
-            translate_place_value_fallback(ctx, body, place, value_map, block_ptr, prev_op, loc)
-        }
-    }
-}
-
-// ============================================================================
-// Place Read Strategy and Address Path
-// ============================================================================
-
-enum PlaceReadStrategy {
-    /// Read the place by walking to its in-memory address and loading once.
-    Address,
-    /// Read the place through value projection because it is not representable
-    /// as one final load address.
-    ValueFallback,
-}
-
-/// Choose how to lower MIR place reads.
-///
-/// This deliberately does not emit IR. The address walker may create several
-/// operations before discovering an unsupported projection, so read lowering
-/// must not call it speculatively and then fall back to value projections.
-///
-/// Conservative fallback is part of the design. Enum payload addressing,
-/// unsupported slice forms, ZST results, and computed/no-slot values remain on
-/// the value path until they have dedicated address-lowering support.
-fn classify_place_read_strategy(
-    ctx: &mut Context,
-    place: &mir::Place,
-    value_map: &ValueMap,
-) -> TranslationResult<PlaceReadStrategy> {
-    let Some(slot) = value_map.get_slot(place.local) else {
-        return Ok(PlaceReadStrategy::ValueFallback);
-    };
-
-    if place.projection.is_empty() {
-        let Some(final_pointee) = mir_ptr_pointee(ctx, slot.get_type(ctx)) else {
-            return Ok(PlaceReadStrategy::ValueFallback);
-        };
-        if types::is_zst_type(ctx, final_pointee) {
-            return Ok(PlaceReadStrategy::ValueFallback);
-        }
-        return Ok(PlaceReadStrategy::Address);
-    };
-
-    let mut current_ptr_ty = slot.get_type(ctx);
-    let mut current_is_slice_data = false;
-
-    for (proj_idx, elem) in place.projection.iter().enumerate() {
-        let entered_as_slice_data = current_is_slice_data;
-        current_is_slice_data = false;
-
-        match elem {
-            mir::ProjectionElem::Deref => {
-                let Some(place_ty) = mir_ptr_pointee(ctx, current_ptr_ty) else {
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                };
-
-                if is_empty_tuple_type(ctx, place_ty) {
-                    continue;
-                }
-
-                if let Some(elem_ty) = slice_like_element_type(ctx, place_ty) {
-                    let is_last = proj_idx + 1 == place.projection.len();
-                    if is_last {
-                        // The address walker returns a loaded fat value for a
-                        // trailing slice-shaped deref. This helper handles only
-                        // paths whose final result is an address to load from.
-                        return Ok(PlaceReadStrategy::ValueFallback);
-                    }
-
-                    match &place.projection[proj_idx + 1] {
-                        mir::ProjectionElem::Field(_, field_rust_ty) => {
-                            if rust_ty_is_slice(field_rust_ty)
-                                || types::slice_tail_element_ty(field_rust_ty).is_some()
-                            {
-                                // A direct slice tail or a nested slice-tailed DST needs
-                                // fat-pointer metadata that the address read path does not carry
-                                // across fields. Keep it on the value path.
-                                return Ok(PlaceReadStrategy::ValueFallback);
-                            }
-
-                            current_ptr_ty = dialect_mir::types::MirPtrType::get_generic(
-                                ctx, elem_ty, /* is_mutable */ false,
-                            )
-                            .into();
-                        }
-                        mir::ProjectionElem::Index(_)
-                        | mir::ProjectionElem::ConstantIndex { .. } => {
-                            current_ptr_ty = dialect_mir::types::MirPtrType::get_generic(
-                                ctx, elem_ty, /* is_mutable */ false,
-                            )
-                            .into();
-                            current_is_slice_data = true;
-                        }
-                        _ => return Ok(PlaceReadStrategy::ValueFallback),
-                    }
-                } else if place_ty.deref(ctx).is::<dialect_mir::types::MirPtrType>() {
-                    current_ptr_ty = place_ty;
-                } else {
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                }
-            }
-
-            mir::ProjectionElem::Field(_, field_ty) => {
-                let Some(pointee) = mir_ptr_pointee(ctx, current_ptr_ty) else {
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                };
-                let is_struct_or_tuple =
-                    pointee.deref(ctx).is::<dialect_mir::types::MirStructType>()
-                        || pointee.deref(ctx).is::<dialect_mir::types::MirTupleType>();
-                if !is_struct_or_tuple {
-                    // `mir.field_addr` verifies struct, tuple, union and enum
-                    // pointees; anything else stays on the value path, where
-                    // `mir.extract_field` supports it instead.
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                }
-                if tuple_has_over_aligned_zst_field(ctx, pointee) {
-                    // Code-shape guard: the address path's final load states
-                    // natural alignment only, while a zero-byte
-                    // `repr(align(N))` field raises the tuple's ABI alignment
-                    // without appearing in its LLVM storage type. Keep such
-                    // tuples on the value path, which moves the whole
-                    // aggregate at its recorded alignment. Gate shape from
-                    // PR #715 (vyncint), with the byte-size gap closed.
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                }
-
-                let field_type = types::translate_type(ctx, field_ty)?;
-                let Some(projected_ptr_ty) = projected_pointer_type(
-                    ctx,
-                    current_ptr_ty,
-                    field_type,
-                    /* is_mutable */ false,
-                ) else {
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                };
-
-                current_ptr_ty = projected_ptr_ty;
-            }
-
-            mir::ProjectionElem::Index(_) => {
-                let Some((mut pointee_kind, addr_space)) =
-                    pointer_type_pointee_kind(ctx, current_ptr_ty)
-                else {
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                };
-                if entered_as_slice_data {
-                    pointee_kind = PointeeKind::Direct;
-                }
-                current_ptr_ty = indexed_element_ptr_type(
-                    ctx,
-                    current_ptr_ty,
-                    pointee_kind,
-                    addr_space,
-                    /* is_mutable */ false,
-                );
-            }
-
-            mir::ProjectionElem::ConstantIndex { from_end, .. } => {
-                // rustc emits from-end ConstantIndex only for runtime-length
-                // slices. Require the immediately preceding fat-slice deref;
-                // arrays never reach stable MIR with `from_end=true`.
-                if *from_end && !entered_as_slice_data {
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                }
-                let Some((mut pointee_kind, addr_space)) =
-                    pointer_type_pointee_kind(ctx, current_ptr_ty)
-                else {
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                };
-                if entered_as_slice_data {
-                    pointee_kind = PointeeKind::Direct;
-                }
-                current_ptr_ty = indexed_element_ptr_type(
-                    ctx,
-                    current_ptr_ty,
-                    pointee_kind,
-                    addr_space,
-                    /* is_mutable */ false,
-                );
-            }
-
-            mir::ProjectionElem::Subslice { from, to, from_end } => {
-                // PlaceElem::Subslice uses from_end=false for arrays and
-                // from_end=true for slices. A slice subslice is unsized and
-                // therefore is not a final load address; references/raw
-                // pointers to it are handled by the address walker directly.
-                if *from_end {
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                }
-
-                let (element_ty, array_len, addr_space) = {
-                    let ptr_ty = current_ptr_ty.deref(ctx);
-                    let Some(ptr_ty) = ptr_ty.downcast_ref::<dialect_mir::types::MirPtrType>()
-                    else {
-                        return Ok(PlaceReadStrategy::ValueFallback);
-                    };
-                    let array_ty = ptr_ty.pointee.deref(ctx);
-                    let Some(array_ty) =
-                        array_ty.downcast_ref::<dialect_mir::types::MirArrayType>()
-                    else {
-                        return Ok(PlaceReadStrategy::ValueFallback);
-                    };
-                    (
-                        array_ty.element_type(),
-                        array_ty.size(),
-                        ptr_ty.address_space,
-                    )
-                };
-                let Some(projected_len) = to.checked_sub(*from) else {
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                };
-                if *to > array_len {
-                    return Ok(PlaceReadStrategy::ValueFallback);
-                }
-
-                let projected_array_ty: TypeHandle =
-                    dialect_mir::types::MirArrayType::get(ctx, element_ty, projected_len).into();
-                current_ptr_ty = dialect_mir::types::MirPtrType::get(
-                    ctx,
-                    projected_array_ty,
-                    /* is_mutable */ false,
-                    addr_space,
-                )
-                .into();
-            }
-
-            // Enum payload addressing is a value projection, not a final load
-            // address. Other unknown projections stay on the conservative path.
-            mir::ProjectionElem::Downcast(_) => return Ok(PlaceReadStrategy::ValueFallback),
-            _ => return Ok(PlaceReadStrategy::ValueFallback),
-        }
-    }
-
-    let Some(final_pointee) = mir_ptr_pointee(ctx, current_ptr_ty) else {
-        return Ok(PlaceReadStrategy::ValueFallback);
-    };
-    if types::is_zst_type(ctx, final_pointee) {
-        return Ok(PlaceReadStrategy::ValueFallback);
-    }
-
-    Ok(PlaceReadStrategy::Address)
-}
-
-/// Lower an addressable place read by computing its in-memory address, then
-/// emitting one final `mir.load` from that address.
-///
-/// Returning `None` means the address walker did not produce a final load
-/// address. `translate_place` treats that as a checker/walker divergence when
-/// the classifier selected the address path.
-#[allow(clippy::too_many_arguments)]
-fn translate_place_load_from_address(
-    ctx: &mut Context,
-    body: &mir::Body,
-    place: &mir::Place,
-    value_map: &ValueMap,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<Option<(Value, Option<Ptr<Operation>>)>> {
-    let Some((addr, addr_prev_op)) = translate_place_address(
-        ctx,
-        body,
-        value_map,
-        place,
-        /* is_mutable */ false,
-        block_ptr,
-        prev_op,
-        loc.clone(),
-    )?
-    else {
-        return Ok(None);
-    };
-
-    let Some(pointee) = mir_ptr_pointee(ctx, addr.get_type(ctx)) else {
-        return Ok(None);
-    };
-    if types::is_zst_type(ctx, pointee) {
-        return Ok(None);
-    }
-
-    let load_op = Operation::new(
-        ctx,
-        MirLoadOp::get_concrete_op_info(),
-        vec![pointee],
-        vec![addr],
-        vec![],
-        0,
-    );
-    load_op.deref_mut(ctx).set_loc(loc);
-    match addr_prev_op.or(prev_op) {
-        Some(prev) => load_op.insert_after(ctx, prev),
-        None => load_op.insert_at_front(block_ptr, ctx),
-    }
-
-    let value = load_op.deref(ctx).get_result(0);
-    Ok(Some((value, Some(load_op))))
-}
-
-// ============================================================================
-// Place Read Value Fallback
-// ============================================================================
-
-/// Explicit value-projection fallback for place reads that are not addressable.
-///
-/// Handles value-only reads, including enum downcast/payload extraction, tuple
-/// field extraction, no-slot ghost locals, and ZST synthesis.
-fn translate_place_value_fallback(
-    ctx: &mut Context,
-    body: &mir::Body,
-    place: &mir::Place,
-    value_map: &ValueMap,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    if place.projection.is_empty() {
-        let local = place.local;
-        // Alloca + load/store model: emit `mir.load slot`. Every non-ZST local
-        // has a slot allocated in the entry block, so the loaded value is the
-        // local's current contents. `mem2reg` promotes these loads back into
-        // SSA form when the slot's address doesn't escape.
-        if let Some((load_op, val)) = value_map.load_local(ctx, local, block_ptr, prev_op) {
-            return Ok((val, Some(load_op)));
-        }
-        // ZST or unsupported local -- synthesise a value for it so callers
-        // can uniformly consume a `Value`. An enum gets its variant-0 default
-        // (ghost-enum), a struct/tuple ZST gets an empty aggregate. Loads of
-        // these are otherwise meaningless.
-        let local_decl = &body.locals()[local];
-        let ty_ptr = types::translate_type(ctx, &local_decl.ty)?;
-        if ty_ptr.deref(ctx).is::<dialect_mir::types::MirEnumType>() {
-            let op = create_ghost_enum_default(ctx, ty_ptr, loc.clone());
-            match prev_op {
-                Some(p) => op.insert_after(ctx, p),
-                None => op.insert_at_front(block_ptr, ctx),
-            }
-            let val = op.deref(ctx).get_result(0);
-            return Ok((val, Some(op)));
-        }
-        if types::is_zst_type(ctx, ty_ptr) {
-            return translate_zero_sized_constant_value(ctx, ty_ptr, block_ptr, prev_op, loc);
-        }
-        input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Local {} has no alloca slot and is not a ZST",
-                Into::<usize>::into(local)
-            ))
-        )
-    } else {
-        // Handle projections (place.field, place[index], etc.)
-        // For now, handle tuple field projections (_3.0, _3.1, etc.)
-        if place.projection.len() == 1 {
-            // Check if this is a tuple field projection
-            match &place.projection[0] {
-                ProjectionElem::Deref => {
-                    // Dereference: *ptr
-                    // The base value must be a pointer
-                    let base_place = mir::Place {
-                        local: place.local,
-                        projection: vec![],
-                    };
-                    let (base_value, prev_op_after_base) = translate_place(
-                        ctx,
-                        body,
-                        &base_place,
-                        value_map,
-                        block_ptr,
-                        prev_op,
-                        loc.clone(),
-                    )?;
-
-                    // Get the result type from the pointer's element type
-                    let base_ty = base_value.get_type(ctx);
-
-                    // Extract pointee info while holding the borrow, then release before fallback
-                    let pointee_info: Option<(pliron::r#type::TypeHandle, bool)> = {
-                        let base_ty_ref = base_ty.deref(ctx);
-                        base_ty_ref
-                            .downcast_ref::<dialect_mir::types::MirPtrType>()
-                            .map(|ptr_ty| {
-                                let pointee = ptr_ty.pointee;
-                                let pointee_ref = pointee.deref(ctx);
-
-                                // Check if pointee is a ZST (empty tuple) - this happens for SharedArray
-                                // which is a zero-sized type. For ZSTs, dereferencing just returns the
-                                // same pointer (there's nothing to load).
-                                let is_empty_tuple = pointee_ref
-                                    .downcast_ref::<dialect_mir::types::MirTupleType>()
-                                    .is_some_and(|tt| tt.get_types().is_empty());
-
-                                (pointee, is_empty_tuple)
-                            })
-                    };
-
-                    let (res_ty, is_zst) = pointee_info.unwrap_or_else(|| {
-                        // Fallback: assume i32 if we can't determine the type
-                        (types::get_i32_type(ctx).to_handle(), false)
-                    });
-
-                    // For ZST pointees (like SharedArray), don't create a load op.
-                    // Instead, just return the pointer itself - dereferencing a pointer
-                    // to a ZST and taking a reference back gives the same pointer.
-                    // NOTE: We still load from shared memory pointers (addrspace:3) -
-                    // the ZST check only applies to SharedArray itself, not to data
-                    // stored in shared memory.
-                    if is_zst {
-                        return Ok((base_value, prev_op_after_base));
-                    }
-
-                    let op = Operation::new(
-                        ctx,
-                        MirLoadOp::get_concrete_op_info(),
-                        vec![res_ty],
-                        vec![base_value],
-                        vec![],
-                        0,
-                    );
-                    op.deref_mut(ctx).set_loc(loc);
-
-                    let load_op = MirLoadOp::new(op);
-
-                    if let Some(prev) = prev_op_after_base {
-                        load_op.get_operation().insert_after(ctx, prev);
-                    } else {
-                        load_op.get_operation().insert_at_front(block_ptr, ctx);
-                    }
-
-                    let loaded_val = load_op.get_operation().deref(ctx).get_result(0);
-
-                    Ok((loaded_val, Some(load_op.get_operation())))
-                }
-                ProjectionElem::Field(field_idx, ty) => {
-                    // Get the base value (the tuple/struct).
-                    //
-                    // In the alloca model the recursive call may emit a
-                    // `mir.load <slot>` into the block to materialise the
-                    // aggregate value; we must anchor our `mir.extract_field`
-                    // **after** that load, otherwise the extract ends up
-                    // before the load (and subsequent ops keep pushing the
-                    // load past the block's terminator).
-                    let base_place = mir::Place {
-                        local: place.local,
-                        projection: vec![],
-                    };
-                    let (base_value, prev_op_after_base) = translate_place(
-                        ctx,
-                        body,
-                        &base_place,
-                        value_map,
-                        block_ptr,
-                        prev_op,
-                        loc.clone(),
-                    )?;
-                    let anchor = prev_op_after_base.or(prev_op);
-
-                    let field_type = types::translate_type(ctx, ty)?;
-
-                    let op = Operation::new(
-                        ctx,
-                        MirExtractFieldOp::get_concrete_op_info(),
-                        vec![field_type],
-                        vec![base_value],
-                        vec![],
-                        0,
-                    );
-                    op.deref_mut(ctx).set_loc(loc);
-
-                    let extract_op = MirExtractFieldOp::new(op);
-                    extract_op.set_attr_index(
-                        ctx,
-                        dialect_mir::attributes::FieldIndexAttr(*field_idx as u32),
-                    );
-
-                    if let Some(prev) = anchor {
-                        extract_op.get_operation().insert_after(ctx, prev);
-                    } else {
-                        extract_op.get_operation().insert_at_front(block_ptr, ctx);
-                    }
-
-                    let field_value = extract_op.get_operation().deref(ctx).get_result(0);
-                    Ok((field_value, Some(extract_op.get_operation())))
-                }
-                ProjectionElem::Downcast(_variant_idx) => {
-                    // Downcast by itself is a no-op - it just narrows the type.
-                    // The actual field extraction happens with the following Field projection.
-                    // For now, just return the base value unchanged.
-                    let base_place = mir::Place {
-                        local: place.local,
-                        projection: vec![],
-                    };
-                    translate_place(ctx, body, &base_place, value_map, block_ptr, prev_op, loc)
-                }
-                ProjectionElem::Index(index_local) => {
-                    // Array indexing with a runtime index: array[index]
-                    //
-                    // Alloca model: `array` is backed by a stack slot whose
-                    // pointee is `MirArrayType`, so we compute the element
-                    // address from that slot directly (no MirRefOp needed)
-                    // and load the element.
-
-                    let mut current_prev = prev_op;
-
-                    let Some(arr_ptr) = value_map.get_slot(place.local) else {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "Array local {} has no alloca slot; cannot index",
-                                Into::<usize>::into(place.local)
-                            ))
-                        );
-                    };
-
-                    // Get the index value
-                    let index_place = mir::Place {
-                        local: *index_local,
-                        projection: vec![],
-                    };
-                    let (index_value, prev_op_after_index) = translate_place(
-                        ctx,
-                        body,
-                        &index_place,
-                        value_map,
-                        block_ptr,
-                        current_prev,
-                        loc.clone(),
-                    )?;
-                    current_prev = prev_op_after_index;
-
-                    // Get element type from pointer type
-                    let arr_ptr_ty = arr_ptr.get_type(ctx);
-                    let element_ty = {
-                        let arr_ptr_ty_ref = arr_ptr_ty.deref(ctx);
-                        let mir_ptr_ty = arr_ptr_ty_ref
-                            .downcast_ref::<dialect_mir::types::MirPtrType>()
-                            .expect("Memory array pointer should be MirPtrType");
-                        let array_ty = mir_ptr_ty.pointee;
-                        let array_ty_ref = array_ty.deref(ctx);
-                        array_ty_ref
-                            .downcast_ref::<dialect_mir::types::MirArrayType>()
-                            .expect("Pointee should be MirArrayType")
-                            .element_type()
-                    };
-
-                    // Projection keeps the slot address's machine mutability,
-                    // address space, and pointer kind (or explicitly erases
-                    // only the kind). A read does not require manufacturing
-                    // an immutable address type.
-                    let elem_ptr_ty = projected_pointer_type(
-                        ctx, arr_ptr_ty, element_ty,
-                        /* legacy requested mutability, ignored */ false,
-                    )
-                    .expect("array slot must be a MirPtrType");
-
-                    // Create MirArrayElementAddrOp to get element pointer
-                    use dialect_mir::ops::MirArrayElementAddrOp;
-                    let addr_op = Operation::new(
-                        ctx,
-                        MirArrayElementAddrOp::get_concrete_op_info(),
-                        vec![elem_ptr_ty],
-                        vec![arr_ptr, index_value],
-                        vec![],
-                        0,
-                    );
-                    addr_op.deref_mut(ctx).set_loc(loc.clone());
-
-                    if let Some(prev) = current_prev {
-                        addr_op.insert_after(ctx, prev);
-                    } else {
-                        addr_op.insert_at_front(block_ptr, ctx);
-                    }
-                    current_prev = Some(addr_op);
-
-                    let elem_ptr = addr_op.deref(ctx).get_result(0);
-
-                    // Load the element value
-                    use dialect_mir::ops::MirLoadOp;
-                    let load_op = Operation::new(
-                        ctx,
-                        MirLoadOp::get_concrete_op_info(),
-                        vec![element_ty],
-                        vec![elem_ptr],
-                        vec![],
-                        0,
-                    );
-                    load_op.deref_mut(ctx).set_loc(loc);
-
-                    if let Some(prev) = current_prev {
-                        load_op.insert_after(ctx, prev);
-                    } else {
-                        load_op.insert_at_front(block_ptr, ctx);
-                    }
-
-                    let result = load_op.deref(ctx).get_result(0);
-                    Ok((result, Some(load_op)))
-                }
-                ProjectionElem::ConstantIndex {
-                    offset,
-                    min_length: _,
-                    from_end,
-                } => {
-                    // Array indexing with a compile-time constant index.
-                    //
-                    // Alloca model: the array local already has a `*mut [T; N]`
-                    // slot, so compute the element address via
-                    // `MirConstantOp` + `MirArrayElementAddrOp` and load.
-                    // `mem2reg` collapses the resulting load-after-store pairs
-                    // back into SSA extracts for promotable arrays.
-
-                    let index = if *from_end {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(
-                                "ConstantIndex with from_end=true not yet supported"
-                            )
-                        );
-                    } else {
-                        *offset as usize
-                    };
-
-                    // Load the current array value if we don't have a slot (ZST/edge case)
-                    // so that we fall back to the SSA extract-field behaviour.
-                    let Some(arr_ptr) = value_map.get_slot(place.local) else {
-                        // ZST / no-slot fallback: materialise the whole
-                        // aggregate and extract. Anchor the extract after
-                        // whatever the base-place materialiser inserted.
-                        let base_place = mir::Place {
-                            local: place.local,
-                            projection: vec![],
-                        };
-                        let (array_value, prev_op_after_base) = translate_place(
-                            ctx,
-                            body,
-                            &base_place,
-                            value_map,
-                            block_ptr,
-                            prev_op,
-                            loc.clone(),
-                        )?;
-                        let anchor = prev_op_after_base.or(prev_op);
-
-                        let array_ty = array_value.get_type(ctx);
-                        let element_ty = {
-                            let array_ty_ref = array_ty.deref(ctx);
-                            if let Some(arr_ty) =
-                                array_ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>()
-                            {
-                                arr_ty.element_type()
-                            } else {
-                                return input_err!(
-                                    loc,
-                                    TranslationErr::unsupported(format!(
-                                        "ConstantIndex projection on non-array type: {}",
-                                        array_ty.disp(ctx)
-                                    ))
-                                );
-                            }
-                        };
-
-                        let op = Operation::new(
-                            ctx,
-                            MirExtractFieldOp::get_concrete_op_info(),
-                            vec![element_ty],
-                            vec![array_value],
-                            vec![],
-                            0,
-                        );
-                        op.deref_mut(ctx).set_loc(loc);
-
-                        let extract_op = MirExtractFieldOp::new(op);
-                        extract_op.set_attr_index(
-                            ctx,
-                            dialect_mir::attributes::FieldIndexAttr(index as u32),
-                        );
-
-                        if let Some(prev) = anchor {
-                            extract_op.get_operation().insert_after(ctx, prev);
-                        } else {
-                            extract_op.get_operation().insert_at_front(block_ptr, ctx);
-                        }
-
-                        let result = extract_op.get_operation().deref(ctx).get_result(0);
-                        return Ok((result, Some(extract_op.get_operation())));
-                    };
-
-                    // Slot-backed path: GEP + load from the slot.
-                    let mut current_prev = prev_op;
-
-                    let (element_ty, arr_ptr_ty) = {
-                        let arr_ptr_ty = arr_ptr.get_type(ctx);
-                        let arr_ptr_ty_ref = arr_ptr_ty.deref(ctx);
-                        let mir_ptr_ty = arr_ptr_ty_ref
-                            .downcast_ref::<dialect_mir::types::MirPtrType>()
-                            .ok_or_else(|| {
-                                input_error!(
-                                    loc.clone(),
-                                    TranslationErr::unsupported(format!(
-                                        "ConstantIndex base slot is not a pointer: {}",
-                                        arr_ptr_ty.disp(ctx)
-                                    ))
-                                )
-                            })?;
-                        let array_ty_ref = mir_ptr_ty.pointee.deref(ctx);
-                        let elem_ty = array_ty_ref
-                            .downcast_ref::<dialect_mir::types::MirArrayType>()
-                            .ok_or_else(|| {
-                                input_error_noloc!(TranslationErr::unsupported(
-                                    "ConstantIndex base slot pointee is not MirArrayType"
-                                ))
-                            })?
-                            .element_type();
-                        (elem_ty, arr_ptr_ty)
-                    };
-
-                    use dialect_mir::ops::MirConstantOp;
-                    use pliron::builtin::attributes::IntegerAttr;
-
-                    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signed);
-                    let index_apint = APInt::from_i64(index as i64, NonZeroUsize::new(64).unwrap());
-                    let index_attr = IntegerAttr::new(i64_ty, index_apint);
-
-                    let const_op_ptr = Operation::new(
-                        ctx,
-                        MirConstantOp::get_concrete_op_info(),
-                        vec![i64_ty.into()],
-                        vec![],
-                        vec![],
-                        0,
-                    );
-                    const_op_ptr.deref_mut(ctx).set_loc(loc.clone());
-                    MirConstantOp::new(const_op_ptr).set_attr_value(ctx, index_attr);
-                    if let Some(prev) = current_prev {
-                        const_op_ptr.insert_after(ctx, prev);
-                    } else {
-                        const_op_ptr.insert_at_front(block_ptr, ctx);
-                    }
-                    current_prev = Some(const_op_ptr);
-                    let index_value = const_op_ptr.deref(ctx).get_result(0);
-
-                    let elem_ptr_ty = projected_pointer_type(
-                        ctx, arr_ptr_ty, element_ty,
-                        /* legacy requested mutability, ignored */ false,
-                    )
-                    .expect("array slot must be a MirPtrType");
-
-                    use dialect_mir::ops::MirArrayElementAddrOp;
-                    let addr_op = Operation::new(
-                        ctx,
-                        MirArrayElementAddrOp::get_concrete_op_info(),
-                        vec![elem_ptr_ty],
-                        vec![arr_ptr, index_value],
-                        vec![],
-                        0,
-                    );
-                    addr_op.deref_mut(ctx).set_loc(loc.clone());
-                    if let Some(prev) = current_prev {
-                        addr_op.insert_after(ctx, prev);
-                    } else {
-                        addr_op.insert_at_front(block_ptr, ctx);
-                    }
-                    current_prev = Some(addr_op);
-                    let elem_ptr = addr_op.deref(ctx).get_result(0);
-
-                    let load_op = Operation::new(
-                        ctx,
-                        MirLoadOp::get_concrete_op_info(),
-                        vec![element_ty],
-                        vec![elem_ptr],
-                        vec![],
-                        0,
-                    );
-                    load_op.deref_mut(ctx).set_loc(loc);
-                    if let Some(prev) = current_prev {
-                        load_op.insert_after(ctx, prev);
-                    } else {
-                        load_op.insert_at_front(block_ptr, ctx);
-                    }
-
-                    let result = load_op.deref(ctx).get_result(0);
-                    Ok((result, Some(load_op)))
-                }
-                _ => input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Projection element {:?} not yet implemented",
-                        place.projection[0]
-                    ))
-                ),
-            }
-        } else {
-            // Multi-level projections (2+): use iterative processing.
-            // The iterative path handles Deref on slices (extracts data pointer),
-            // Index/ConstantIndex on both arrays and pointers, Field, Downcast, etc.
-            translate_place_iterative(ctx, body, place, value_map, block_ptr, prev_op, loc)
-        }
-    }
-}
-
-// ============================================================================
-// Iterative Projection Helpers
-// ============================================================================
-// These functions support the iterative processing of MIR projections.
-// Each projection element is handled independently, allowing arbitrary depth.
-
-/// Apply a Deref projection: load from pointer.
-fn apply_deref_projection(
-    ctx: &mut Context,
-    ptr_value: Value,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let ptr_ty = ptr_value.get_type(ctx);
-
-    enum DerefKind {
-        Ptr {
-            pointee: pliron::r#type::TypeHandle,
-            is_zst: bool,
-        },
-        Slice {
-            element_ty: pliron::r#type::TypeHandle,
-        },
-    }
-
-    let deref_kind = {
-        let ptr_ty_ref = ptr_ty.deref(ctx);
-        if let Some(mir_ptr_ty) = ptr_ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>() {
-            let pointee = mir_ptr_ty.pointee;
-            let is_zst = pointee
-                .deref(ctx)
-                .downcast_ref::<dialect_mir::types::MirTupleType>()
-                .is_some_and(|tt| tt.get_types().is_empty());
-            Some(DerefKind::Ptr { pointee, is_zst })
-        } else {
-            ptr_ty_ref
-                .downcast_ref::<dialect_mir::types::MirSliceType>()
-                .map(|slice_ty| DerefKind::Slice {
-                    element_ty: slice_ty.element_type(),
-                })
-        }
-    };
-
-    let deref_kind = deref_kind.ok_or_else(|| {
-        let ty_dbg = format!("{:?}", ptr_ty.deref(ctx));
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "Deref projection on unsupported type in apply_deref_projection.\n\
-             \n  pliron type: {}\n\
-             \n  display    : {}\n\
-             \n\
-             \nDeref currently handles MirPtrType (thin pointer load) and MirSliceType\n\
-             (fat pointer → extract data pointer). The type above matched neither.\n\
-             A new handler may need to be added.",
-            ty_dbg,
-            ptr_ty.disp(ctx)
-        )))
-    })?;
-
-    match deref_kind {
-        DerefKind::Ptr { pointee, is_zst } => {
-            if is_zst {
-                return Ok((ptr_value, prev_op));
-            }
-
-            let op = Operation::new(
-                ctx,
-                MirLoadOp::get_concrete_op_info(),
-                vec![pointee],
-                vec![ptr_value],
-                vec![],
-                0,
-            );
-            op.deref_mut(ctx).set_loc(loc);
-            let load_op = MirLoadOp::new(op);
-
-            if let Some(prev) = prev_op {
-                load_op.get_operation().insert_after(ctx, prev);
-            } else {
-                load_op.get_operation().insert_at_front(block_ptr, ctx);
-            }
-
-            Ok((
-                load_op.get_operation().deref(ctx).get_result(0),
-                Some(load_op.get_operation()),
-            ))
-        }
-
-        DerefKind::Slice { element_ty } => {
-            // Slices are unsized — we can't load `[T]` into an SSA value.
-            // Extract the data pointer (field 0 of the fat pointer {ptr, len}).
-            // Subsequent Index/ConstantIndex projections will do ptr arithmetic + load.
-            let origin = ptr_value
-                .get_type(ctx)
-                .deref(ctx)
-                .downcast_ref::<dialect_mir::types::MirSliceType>()
-                .map(facts::pointer_origin_of_slice_carrier);
-            let ptr_ty: TypeHandle = match origin {
-                Some(origin) => facts::mint_generic_ptr_type(ctx, element_ty, origin).into(),
-                None => dialect_mir::types::MirPtrType::get_generic(ctx, element_ty, false).into(),
-            };
-
-            let extract_op = Operation::new(
-                ctx,
-                MirExtractFieldOp::get_concrete_op_info(),
-                vec![ptr_ty],
-                vec![ptr_value],
-                vec![],
-                0,
-            );
-            extract_op.deref_mut(ctx).set_loc(loc);
-
-            let extract = MirExtractFieldOp::new(extract_op);
-            extract.set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
-
-            if let Some(prev) = prev_op {
-                extract.get_operation().insert_after(ctx, prev);
-            } else {
-                extract.get_operation().insert_at_front(block_ptr, ctx);
-            }
-
-            Ok((
-                extract.get_operation().deref(ctx).get_result(0),
-                Some(extract.get_operation()),
-            ))
-        }
-    }
-}
-
-/// Apply a Field projection against a POINTER to the aggregate: compute the
-/// field's address with `mir.field_addr` and load the field value.
-///
-/// Used when the projection walk holds an address rather than an aggregate
-/// value, which happens after dereferencing a fat pointer (the unsized
-/// pointee cannot be loaded whole, so the deref hands back the data
-/// pointer; see `apply_deref_projection`).
-fn apply_field_addr_and_load(
-    ctx: &mut Context,
-    aggregate_ptr: Value,
-    field_idx: mir::FieldIdx,
-    field_ty: &rustc_public::ty::Ty,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let field_type = types::translate_type(ctx, field_ty)?;
-    let field_ptr_ty = projected_pointer_type(
-        ctx,
-        aggregate_ptr.get_type(ctx),
-        field_type,
-        /* legacy requested mutability, ignored */ false,
-    )
-    .ok_or_else(|| {
-        input_error!(
-            loc.clone(),
-            TranslationErr::unsupported("field-address base is not a MIR pointer".to_string())
-        )
-    })?;
-
-    let addr_op = dialect_mir::ops::MirFieldAddrOp::build(
-        ctx,
-        aggregate_ptr,
-        field_ptr_ty,
-        field_idx as u32,
-    )?;
-    addr_op.deref_mut(ctx).set_loc(loc.clone());
-    match prev_op {
-        Some(p) => addr_op.insert_after(ctx, p),
-        None => addr_op.insert_at_front(block_ptr, ctx),
-    }
-    let field_ptr = addr_op.deref(ctx).get_result(0);
-
-    let load_op = Operation::new(
-        ctx,
-        MirLoadOp::get_concrete_op_info(),
-        vec![field_type],
-        vec![field_ptr],
-        vec![],
-        0,
-    );
-    load_op.deref_mut(ctx).set_loc(loc);
-    load_op.insert_after(ctx, addr_op);
-
-    Ok((load_op.deref(ctx).get_result(0), Some(load_op)))
-}
-
-/// Apply a Field projection: extract field from struct/tuple.
-fn apply_field_projection(
-    ctx: &mut Context,
-    aggregate_value: Value,
-    field_idx: mir::FieldIdx,
-    field_ty: &rustc_public::ty::Ty,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let field_type = types::translate_type(ctx, field_ty)?;
-
-    let op = Operation::new(
-        ctx,
-        MirExtractFieldOp::get_concrete_op_info(),
-        vec![field_type],
-        vec![aggregate_value],
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc.clone());
-
-    let extract_op = MirExtractFieldOp::new(op);
-    extract_op.set_attr_index(
-        ctx,
-        dialect_mir::attributes::FieldIndexAttr(field_idx as u32),
-    );
-
-    if let Some(prev) = prev_op {
-        extract_op.get_operation().insert_after(ctx, prev);
-    } else {
-        extract_op.get_operation().insert_at_front(block_ptr, ctx);
-    }
-
-    let field_value = extract_op.get_operation().deref(ctx).get_result(0);
-
-    Ok((field_value, Some(extract_op.get_operation())))
-}
-
-/// Apply a Field projection on an enum variant (after Downcast).
-#[allow(clippy::too_many_arguments)]
-pub(crate) fn apply_enum_field_projection_pub(
-    ctx: &mut Context,
-    enum_value: Value,
-    enum_rust_ty: &rustc_public::ty::Ty,
-    variant_idx: rustc_public::ty::VariantIdx,
-    field_idx: mir::FieldIdx,
-    field_ty: &rustc_public::ty::Ty,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    apply_enum_field_projection(
-        ctx,
-        enum_value,
-        enum_rust_ty,
-        variant_idx,
-        field_idx,
-        field_ty,
-        block_ptr,
-        prev_op,
-        loc,
-    )
-}
-
-fn apply_enum_field_projection(
-    ctx: &mut Context,
-    enum_value: Value,
-    enum_rust_ty: &rustc_public::ty::Ty,
-    variant_idx: rustc_public::ty::VariantIdx,
-    field_idx: mir::FieldIdx,
-    field_ty: &rustc_public::ty::Ty,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    use dialect_mir::ops::MirEnumPayloadOp;
-
-    let field_type = types::translate_type(ctx, field_ty)?;
-
-    // Get the variant index
-    // NOTE: variant_idx IS the index (0, 1, 2, ...), NOT the discriminant!
-    // We just need to validate it's an ADT type, then use the index directly.
-    let variant_idx_val: usize = match enum_rust_ty.kind() {
-        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Adt(_adt_def, _)) => {
-            variant_idx.to_index()
-        }
-        _ => {
-            return input_err!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Downcast on non-ADT type: {:?}",
-                    enum_rust_ty
-                ))
-            );
-        }
-    };
-
-    // A value inhabiting this variant cannot exist, so the read sits on a
-    // dynamically dead path that rustc nevertheless keeps in MIR (e.g. the
-    // `ControlFlow::Break(NeverShortCircuitResidual)` arm inside
-    // `array::try_from_fn`). `mir.enum_payload` refuses uninhabited
-    // variants by verification, so keep the dead path representable with a
-    // typed undef instead — the same treatment `[T; 0]` extraction gets.
-    let variant_is_uninhabited = {
-        let enum_ty = enum_value.get_type(ctx);
-        enum_ty
-            .deref(ctx)
-            .downcast_ref::<dialect_mir::types::MirEnumType>()
-            .and_then(|enum_ty| enum_ty.variant_is_inhabited(variant_idx_val))
-            .is_some_and(|inhabited| !inhabited)
-    };
-    if variant_is_uninhabited {
-        let undef = MirUndefOp::new(ctx, field_type).get_operation();
-        undef.deref_mut(ctx).set_loc(loc);
-        match prev_op {
-            Some(prev) => undef.insert_after(ctx, prev),
-            None => undef.insert_at_front(block_ptr, ctx),
-        }
-        return Ok((undef.deref(ctx).get_result(0), Some(undef)));
-    }
-
-    let op = Operation::new(
-        ctx,
-        MirEnumPayloadOp::get_concrete_op_info(),
-        vec![field_type],
-        vec![enum_value],
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc.clone());
-
-    let payload_op = MirEnumPayloadOp::new(op);
-
-    payload_op.set_attr_payload_variant_index(
-        ctx,
-        dialect_mir::attributes::VariantIndexAttr(variant_idx_val as u32),
-    );
-    payload_op.set_attr_payload_field_index(
-        ctx,
-        dialect_mir::attributes::FieldIndexAttr(field_idx as u32),
-    );
-
-    if let Some(prev) = prev_op {
-        payload_op.get_operation().insert_after(ctx, prev);
-    } else {
-        payload_op.get_operation().insert_at_front(block_ptr, ctx);
-    }
-
-    let payload_value = payload_op.get_operation().deref(ctx).get_result(0);
-
-    Ok((payload_value, Some(payload_op.get_operation())))
-}
-
-/// Compute the in-memory address of `place` by walking its FULL projection
-/// list starting from `place.local`'s alloca slot.
-///
-/// Single entry point for `Rvalue::Ref` / `Rvalue::AddressOf` address
-/// materialisation: `&(*ptr)` loads the pointer, `&(*ptr).field` adds a
-/// field address, `&x.arr[i]` adds an element address, and arbitrary
-/// combinations compose.
-///
-/// Returns `Ok(None)` when the local has no slot (ZST / ghost locals) or
-/// when the projection chain contains an element
-/// [`translate_place_addr_from_slot`] cannot lower. The caller decides
-/// whether a value-copy fallback is sound (shared borrows: reads through a
-/// copy are fine) or the construct must be rejected (mutable borrows / raw
-/// mut pointers: writes through a copy are silently lost).
-///
-/// Also used by statement translation to compute the destination address
-/// of projected assignments (indexed `(*ptr)[i]` writes and 3+ element
-/// projection chains), where the same "walk the chain, then act through
-/// the address" logic applies with a store instead of a borrow.
-#[allow(clippy::too_many_arguments)]
-pub(crate) fn translate_place_address(
-    ctx: &mut Context,
-    body: &mir::Body,
-    value_map: &ValueMap,
-    place: &mir::Place,
-    is_mutable: bool,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<Option<(Value, Option<Ptr<Operation>>)>> {
-    let Some(slot) = value_map.get_slot(place.local) else {
-        return Ok(None);
-    };
-    translate_place_addr_from_slot(
-        ctx,
-        body,
-        value_map,
-        slot,
-        &place.projection,
-        is_mutable,
-        block_ptr,
-        prev_op,
-        loc,
-    )
-}
-
-/// Whether an enum payload's SEMANTIC type needs canonical-storage coercion
-/// when its bytes live inside enum storage.
-///
-/// Mirrors what mir-lower's `enum_payload_storage_type` rewrites: `bool`
-/// leaves are stored as canonical `i8` bytes and shared-memory pointer
-/// leaves are stored as CUDA generic pointers, recursively through
-/// struct/tuple/array nesting. An address of such a payload cannot carry
-/// that coercion (the address escapes, and loads and stores through it are
-/// typed with the SEMANTIC type), so the address walker uses this predicate
-/// to punt SHARED borrows back to the sound value-copy fallback.
-///
-/// Layering: this predicate is allowed to be conservative. A nested enum
-/// payload, for example, is treated as needing coercion whenever any of its
-/// own payload fields does, without proving the leaf survives into the
-/// nested enum's converted storage. Over-punting only costs a copy for a
-/// shared borrow and stays sound. mir-lower's canonical-storage gate on
-/// `mir.field_addr` remains the fail-closed authority, so a miss here still
-/// errors loudly instead of miscompiling.
-pub(crate) fn enum_payload_needs_storage_coercion_pub(ctx: &Context, ty: TypeHandle) -> bool {
-    enum_payload_needs_storage_coercion(ctx, ty)
-}
-
-fn enum_payload_needs_storage_coercion(ctx: &Context, ty: TypeHandle) -> bool {
-    // Bool leaf: semantic i1, canonical i8 byte in enum storage.
-    if let Some(integer) = ty.deref(ctx).downcast_ref::<IntegerType>() {
-        return integer.width() == 1;
-    }
-    // Pointer leaf: shared-memory pointers are stored as generic pointers
-    // because their physical width is target-mode dependent.
-    if let Some(pointer) = ty
-        .deref(ctx)
-        .downcast_ref::<dialect_mir::types::MirPtrType>()
-    {
-        return pointer.address_space() == dialect_mir::types::address_space::SHARED;
-    }
-    // Aggregates: recurse through every leaf position the storage rewrite
-    // visits. Collect the children first so the type `Ref` is dropped
-    // before recursing.
-    let children: Vec<TypeHandle> = {
-        let ty_ref = ty.deref(ctx);
-        if let Some(tuple) = ty_ref.downcast_ref::<dialect_mir::types::MirTupleType>() {
-            tuple.types.clone()
-        } else if let Some(struct_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirStructType>() {
-            struct_ty.field_types.clone()
-        } else if let Some(array) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
-            vec![array.element_ty]
-        } else if let Some(enum_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirEnumType>() {
-            enum_ty.all_field_types.clone()
-        } else {
-            return false;
-        }
-    };
-    children
-        .into_iter()
-        .any(|child| enum_payload_needs_storage_coercion(ctx, child))
-}
-
-/// Extract the runtime element count from a slice-shaped fat value.
-///
-/// CUDA Oxide models slices as `(data_ptr, len)`, with the length in field 1.
-/// The extraction must use the fat value itself: inferring a length from the
-/// data pointer's pointee type is wrong for slices whose elements are arrays.
-fn emit_slice_len_extract(
-    ctx: &mut Context,
-    slice_value: Value,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> (Value, Ptr<Operation>) {
-    let usize_ty = types::get_usize_type(ctx);
-    let op = Operation::new(
-        ctx,
-        MirExtractFieldOp::get_concrete_op_info(),
-        vec![usize_ty.to_handle()],
-        vec![slice_value],
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc);
-    MirExtractFieldOp::new(op).set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(1));
-    match prev_op {
-        Some(prev) => op.insert_after(ctx, prev),
-        None => op.insert_at_front(block_ptr, ctx),
-    }
-    (op.deref(ctx).get_result(0), op)
-}
-
-/// Materialize the zero-based index for
-/// `ConstantIndex { offset, from_end: true }` on a runtime-length slice.
-///
-/// rustc defines the offset as 1-based from the end, so the index is
-/// `slice_len - offset`. The MIR pattern-length test dominates this place,
-/// therefore the subtraction cannot underflow on an executed path.
-fn emit_from_end_slice_index(
-    ctx: &mut Context,
-    slice_len: Value,
-    offset: u64,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Ptr<Operation>)> {
-    let usize_ty = types::get_usize_type(ctx);
-    let usize_handle = usize_ty.to_handle();
-    if slice_len.get_type(ctx) != usize_handle {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "from-end ConstantIndex expected slice length of type {}, got {}",
-                usize_handle.disp(ctx),
-                slice_len.get_type(ctx).disp(ctx)
-            ))
-        );
-    }
-
-    let width = NonZeroUsize::new(
-        usize::try_from(usize_ty.deref(ctx).width()).expect("usize width must fit usize"),
-    )
-    .expect("usize integer width must be non-zero");
-    let offset_attr =
-        pliron::builtin::attributes::IntegerAttr::new(usize_ty, APInt::from_u64(offset, width));
-    let offset_op = Operation::new(
-        ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![usize_handle],
-        vec![],
-        vec![],
-        0,
-    );
-    offset_op.deref_mut(ctx).set_loc(loc.clone());
-    MirConstantOp::new(offset_op).set_attr_value(ctx, offset_attr);
-    match prev_op {
-        Some(prev) => offset_op.insert_after(ctx, prev),
-        None => offset_op.insert_at_front(block_ptr, ctx),
-    }
-    let offset_value = offset_op.deref(ctx).get_result(0);
-
-    let sub_op = Operation::new(
-        ctx,
-        MirSubOp::get_concrete_op_info(),
-        vec![usize_handle],
-        vec![slice_len, offset_value],
-        vec![],
-        0,
-    );
-    sub_op.deref_mut(ctx).set_loc(loc);
-    sub_op.insert_after(ctx, offset_op);
-
-    Ok((sub_op.deref(ctx).get_result(0), sub_op))
-}
-
-/// Emit a `usize` constant and insert it after `prev_op`.
-fn emit_usize_constant(
-    ctx: &mut Context,
-    value: u64,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> (Value, Ptr<Operation>) {
-    use pliron::builtin::attributes::IntegerAttr;
-
-    let usize_ty = types::get_usize_type(ctx);
-    let attr = IntegerAttr::new(
-        IntegerType::get(ctx, 64, Signedness::Unsigned),
-        APInt::from_u64(value, NonZeroUsize::new(64).unwrap()),
-    );
-    let op = Operation::new(
-        ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![usize_ty.to_handle()],
-        vec![],
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc);
-    MirConstantOp::new(op).set_attr_value(ctx, attr);
-    match prev_op {
-        Some(prev) => op.insert_after(ctx, prev),
-        None => op.insert_at_front(block_ptr, ctx),
-    }
-    (op.deref(ctx).get_result(0), op)
-}
-
-/// Compute the address of a sized array subslice.
-///
-/// For `Subslice { from, to, from_end: false }`, rustc codegen takes the
-/// address of element `from` and re-types that address as `[T; to - from]`.
-#[allow(clippy::too_many_arguments)]
-fn emit_array_subslice_address(
-    ctx: &mut Context,
-    array_ptr: Value,
-    from: u64,
-    to: u64,
-    is_mutable: bool,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Ptr<Operation>)> {
-    use dialect_mir::ops::MirArrayElementAddrOp;
-
-    let (element_ty, array_len) = {
-        let ptr_ty = array_ptr.get_type(ctx);
-        let ptr_ty = ptr_ty.deref(ctx);
-        let Some(ptr_ty) = ptr_ty.downcast_ref::<dialect_mir::types::MirPtrType>() else {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported("Subslice base is not a pointer".to_string())
-            );
-        };
-        let array_ty = ptr_ty.pointee.deref(ctx);
-        let Some(array_ty) = array_ty.downcast_ref::<dialect_mir::types::MirArrayType>() else {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(
-                    "array Subslice base pointer does not point to MirArrayType".to_string()
-                )
-            );
-        };
-        (array_ty.element_type(), array_ty.size())
-    };
-
-    let Some(projected_len) = to.checked_sub(from) else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "array Subslice has inverted bounds: from={from}, to={to}"
-            ))
-        );
-    };
-    if to > array_len {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "array Subslice end {to} exceeds array length {array_len}"
-            ))
-        );
-    }
-
-    let (from_value, from_op) = emit_usize_constant(ctx, from, block_ptr, prev_op, loc.clone());
-    let elem_ptr_ty = projected_pointer_type(
-        ctx,
-        array_ptr.get_type(ctx),
-        element_ty,
-        /* legacy requested mutability, ignored */ is_mutable,
-    )
-    .expect("array subslice base must be a MirPtrType");
-    let addr_op = Operation::new(
-        ctx,
-        MirArrayElementAddrOp::get_concrete_op_info(),
-        vec![elem_ptr_ty],
-        vec![array_ptr, from_value],
-        vec![],
-        0,
-    );
-    addr_op.deref_mut(ctx).set_loc(loc.clone());
-    addr_op.insert_after(ctx, from_op);
-    let elem_ptr = addr_op.deref(ctx).get_result(0);
-
-    let projected_array_ty: TypeHandle =
-        dialect_mir::types::MirArrayType::get(ctx, element_ty, projected_len).into();
-    let projected_ptr_ty = projected_pointer_type(
-        ctx,
-        elem_ptr.get_type(ctx),
-        projected_array_ty,
-        /* legacy requested mutability, ignored */ is_mutable,
-    )
-    .expect("array subslice element address must be a MirPtrType");
-    let cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![projected_ptr_ty],
-        vec![elem_ptr],
-        vec![],
-        0,
-    );
-    cast_op.deref_mut(ctx).set_loc(loc);
-    MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-    cast_op.insert_after(ctx, addr_op);
-
-    Ok((cast_op.deref(ctx).get_result(0), cast_op))
-}
-
-/// Build the fat value for a slice subslice from the original fat slice.
-///
-/// rustc's semantics for `from_end=true` are
-/// `slice[from..slice.len() - to]`: advance the data pointer by `from` and
-/// replace the metadata with `len - (from + to)`.
-#[allow(clippy::too_many_arguments)]
-fn emit_slice_subslice_value(
-    ctx: &mut Context,
-    slice_value: Value,
-    element_ty: TypeHandle,
-    is_mutable: bool,
-    from: u64,
-    to: u64,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Ptr<Operation>)> {
-    // Subslice is a projection of an existing fat pointer, not a new borrow.
-    // Preserve the source pointer category; callers that explicitly form a
-    // reborrow/raw address normalize the terminal result to their new Rust
-    // type afterwards. A non-slice carrier keeps the caller's mutability with
-    // Erased provenance.
-    let origin = slice_value
-        .get_type(ctx)
-        .deref(ctx)
-        .downcast_ref::<dialect_mir::types::MirSliceType>()
-        .map(facts::pointer_origin_of_slice_carrier);
-
-    use dialect_mir::ops::MirConstructSliceOp;
-
-    let Some(trim) = from.checked_add(to) else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported("Subslice bounds overflow usize metadata".to_string())
-        );
-    };
-
-    let data_ptr_ty: TypeHandle = match origin {
-        Some(origin) => facts::mint_generic_ptr_type(ctx, element_ty, origin).into(),
-        None => dialect_mir::types::MirPtrType::get_generic(ctx, element_ty, is_mutable).into(),
-    };
-    let extract_ptr = Operation::new(
-        ctx,
-        MirExtractFieldOp::get_concrete_op_info(),
-        vec![data_ptr_ty],
-        vec![slice_value],
-        vec![],
-        0,
-    );
-    extract_ptr.deref_mut(ctx).set_loc(loc.clone());
-    MirExtractFieldOp::new(extract_ptr)
-        .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
-    match prev_op {
-        Some(prev) => extract_ptr.insert_after(ctx, prev),
-        None => extract_ptr.insert_at_front(block_ptr, ctx),
-    }
-    let data_ptr = extract_ptr.deref(ctx).get_result(0);
-
-    let usize_ty = types::get_usize_type(ctx);
-    let extract_len = Operation::new(
-        ctx,
-        MirExtractFieldOp::get_concrete_op_info(),
-        vec![usize_ty.to_handle()],
-        vec![slice_value],
-        vec![],
-        0,
-    );
-    extract_len.deref_mut(ctx).set_loc(loc.clone());
-    MirExtractFieldOp::new(extract_len)
-        .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(1));
-    extract_len.insert_after(ctx, extract_ptr);
-    let len = extract_len.deref(ctx).get_result(0);
-
-    let (from_value, from_op) =
-        emit_usize_constant(ctx, from, block_ptr, Some(extract_len), loc.clone());
-    let offset_op = Operation::new(
-        ctx,
-        MirPtrOffsetOp::get_concrete_op_info(),
-        vec![data_ptr_ty],
-        vec![data_ptr, from_value],
-        vec![],
-        0,
-    );
-    offset_op.deref_mut(ctx).set_loc(loc.clone());
-    offset_op.insert_after(ctx, from_op);
-    let new_data = offset_op.deref(ctx).get_result(0);
-
-    let (trim_value, trim_op) =
-        emit_usize_constant(ctx, trim, block_ptr, Some(offset_op), loc.clone());
-    let sub_op = Operation::new(
-        ctx,
-        MirSubOp::get_concrete_op_info(),
-        vec![usize_ty.to_handle()],
-        vec![len, trim_value],
-        vec![],
-        0,
-    );
-    sub_op.deref_mut(ctx).set_loc(loc.clone());
-    sub_op.insert_after(ctx, trim_op);
-    let new_len = sub_op.deref(ctx).get_result(0);
-
-    let slice_ty = match origin {
-        Some(origin) => facts::mint_slice_type(ctx, element_ty, origin),
-        None => dialect_mir::types::MirSliceType::get_with_mutability(ctx, element_ty, is_mutable),
-    };
-    let construct = Operation::new(
-        ctx,
-        MirConstructSliceOp::get_concrete_op_info(),
-        vec![slice_ty.into()],
-        vec![new_data, new_len],
-        vec![],
-        0,
-    );
-    construct.deref_mut(ctx).set_loc(loc);
-    construct.insert_after(ctx, sub_op);
-
-    Ok((construct.deref(ctx).get_result(0), construct))
-}
-
-/// Materialize a sized array subslice from an SSA array value.
-fn emit_array_subslice_value(
-    ctx: &mut Context,
-    array_value: Value,
-    from: u64,
-    to: u64,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let (element_ty, array_len) = {
-        let array_ty = array_value.get_type(ctx);
-        let array_ty = array_ty.deref(ctx);
-        let Some(array_ty) = array_ty.downcast_ref::<dialect_mir::types::MirArrayType>() else {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported("Subslice value base is not MirArrayType".to_string())
-            );
-        };
-        (array_ty.element_type(), array_ty.size())
-    };
-
-    let Some(projected_len) = to.checked_sub(from) else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "array Subslice has inverted bounds: from={from}, to={to}"
-            ))
-        );
-    };
-    if to > array_len {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "array Subslice end {to} exceeds array length {array_len}"
-            ))
-        );
-    }
-
-    let mut elements = Vec::with_capacity(projected_len as usize);
-    let mut current_prev = prev_op;
-    for index in from..to {
-        let field_index = u32::try_from(index).map_err(|_| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "array Subslice index {index} exceeds dialect field-index range"
-            )))
-        })?;
-        let extract = Operation::new(
-            ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![element_ty],
-            vec![array_value],
-            vec![],
-            0,
-        );
-        extract.deref_mut(ctx).set_loc(loc.clone());
-        MirExtractFieldOp::new(extract)
-            .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(field_index));
-        match current_prev {
-            Some(prev) => extract.insert_after(ctx, prev),
-            None => extract.insert_at_front(block_ptr, ctx),
-        }
-        elements.push(extract.deref(ctx).get_result(0));
-        current_prev = Some(extract);
-    }
-
-    let projected_array_ty: TypeHandle =
-        dialect_mir::types::MirArrayType::get(ctx, element_ty, projected_len).into();
-    let construct = Operation::new(
-        ctx,
-        MirConstructArrayOp::get_concrete_op_info(),
-        vec![projected_array_ty],
-        elements,
-        vec![],
-        0,
-    );
-    construct.deref_mut(ctx).set_loc(loc);
-    match current_prev {
-        Some(prev) => construct.insert_after(ctx, prev),
-        None => construct.insert_at_front(block_ptr, ctx),
-    }
-
-    Ok((construct.deref(ctx).get_result(0), Some(construct)))
-}
-
-/// Compute the in-memory address of `place` starting from its alloca `slot`.
-///
-/// Walks the projection chain and emits the correct pliron ops for each
-/// element:
-///
-/// - `Field(idx, _)`   → [`MirFieldAddrOp`]
-/// - `ConstantIndex {offset, from_end, ..}` → an element address. Forward
-///   indexes materialize `offset` directly; from-end indexes on slices extract
-///   the fat-pointer length and materialize `len - offset` at runtime.
-/// - `Index(local)`    → `load_local(local)` + [`MirArrayElementAddrOp`]
-///   (array pointee) or `load_local(local)` + [`MirPtrOffsetOp`] (slice data pointer)
-/// - `Deref`           → `MirLoadOp` of the pointer (the loaded pointer IS
-///   the pointee's address); subsequent projections apply to the pointee.
-///   ZST pointees skip the load (SharedArray exception). Fat (slice-shaped)
-///   pointees scalarize to a (data ptr, len) pair: a mid-chain fat deref
-///   loads the whole fat value and extracts the thin data pointer (field 0)
-///   so the walk continues against the ORIGINAL elements, while a trailing
-///   fat deref (`&*s` reborrow) is just a load of the fat value.
-///
-/// `Downcast` records the variant for the `Field` immediately after it (the
-/// pair addresses an enum payload through the flattened `all_field_types`
-/// index); rustc guarantees that pairing, and any other continuation punts.
-/// A SHARED borrow of a payload whose enum storage is canonical rather than
-/// semantic (see [`enum_payload_needs_storage_coercion`]) also punts, so the
-/// caller's value-copy fallback handles the read soundly instead of handing
-/// out an address that cannot honor the storage coercion.
-/// `Subslice` is handled for both sized arrays and slice fat pointers. Array
-/// subslices keep an in-memory address; slice subslices advance the data
-/// pointer and rebuild metadata as `len - (from + to)`, and can continue into
-/// element Index/forward-ConstantIndex projections. From-end `ConstantIndex`
-/// is accepted only when the immediately preceding fat-slice deref supplied
-/// runtime length metadata; other bases (including a from-end index after a
-/// Subslice) punt instead of guessing a length.
-///
-/// Returns `Ok(Some((addr, last_op)))` on success, `Ok(None)` if the
-/// projection chain contains an element this helper doesn't know how to
-/// turn into an address (the caller decides whether a value fallback is
-/// sound or the construct must be rejected), or `Err` if something
-/// structurally invalid happens (wrong pointee kind, unsupported type).
-///
-/// `is_mutable` governs the mutability of intermediate pointer types; the
-/// final result pointer also carries this mutability.
-fn translate_place_addr_from_slot(
-    ctx: &mut Context,
-    body: &mir::Body,
-    value_map: &ValueMap,
-    slot: Value,
-    projection: &[mir::ProjectionElem],
-    is_mutable: bool,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<Option<(Value, Option<Ptr<Operation>>)>> {
-    use dialect_mir::ops::MirConstantOp;
-
-    let mut current = slot;
-    let mut current_prev_op = prev_op;
-    let mut current_is_slice_data = false;
-    // A fat-slice Deref may lower the immediately following Subslice while its
-    // length metadata is still available. The next loop iteration then skips
-    // that already-consumed projection and preserves slice-data provenance for
-    // a following Index/ConstantIndex.
-    let mut consumed_slice_subslice = false;
-    // A fat DST Deref can consume the immediately following slice-tail Field
-    // while rebuilding the `(data_ptr, len)` value needed for an indexed
-    // element address. The next loop iteration skips that already-lowered
-    // Field and preserves slice-data provenance for Index/ConstantIndex.
-    let mut consumed_slice_tail_field = false;
-    let mut current_slice_len: Option<Value> = None;
-    // A fat reference to a slice-tailed struct carries the runtime length of
-    // its final slice field. Preserve that metadata while walking nested
-    // slice-tailed struct fields until the actual `[T]` field is reached.
-    let mut carried_slice_tail_len: Option<Value> = None;
-    // Set by a `Downcast` and consumed by the `Field` that follows it, which
-    // is the only projection pair that can name an enum payload.
-    let mut pending_variant: Option<usize> = None;
-
-    for (proj_idx, elem) in projection.iter().enumerate() {
-        // The slice-data provenance bit only describes the pointer produced by
-        // the immediately-preceding `Deref` of a fat slice (index it by
-        // element, not as a pointer to one array object). Capture it for this
-        // iteration and clear it up front, so the invariant stays local: it is
-        // true only when the previous step handed us a slice DATA pointer, and
-        // no later projection arm can accidentally leak it forward.
-        let entered_as_slice_data = current_is_slice_data;
-        let entered_slice_len = current_slice_len.take();
-        current_is_slice_data = false;
-
-        // The preceding fat-DST Deref already lowered this slice-tail Field
-        // so it could preserve the metadata before continuing to an element
-        // index. Skip the syntactic Field here and carry the normalized
-        // slice-data state into the following Index/ConstantIndex.
-        if consumed_slice_tail_field {
-            if !matches!(elem, mir::ProjectionElem::Field(_, _)) {
-                return Ok(None);
-            }
-            consumed_slice_tail_field = false;
-            current_is_slice_data = entered_as_slice_data;
-            current_slice_len = entered_slice_len;
-            continue;
-        }
-
-        // A `Downcast` names a variant only for the `Field` IMMEDIATELY
-        // after it (rustc's MIR validator enforces the pairing). Any other
-        // continuation is not a shape valid MIR produces; punt rather than
-        // let a stale variant leak into a later `Field` arm.
-        if pending_variant.is_some() && !matches!(elem, mir::ProjectionElem::Field(_, _)) {
-            return Ok(None);
-        }
-
-        match elem {
-            // `*place` -- the place walked so far holds a pointer; the
-            // address of the dereferenced place is that pointer VALUE, so a
-            // single `mir.load` of `current` yields it. Subsequent
-            // projections then apply to the pointee.
-            mir::ProjectionElem::Deref => {
-                // Type of the place being dereferenced (= pointee of the
-                // `current` address).
-                let Some(place_ty) = mir_ptr_pointee(ctx, current.get_type(ctx)) else {
-                    // `current` is not a pointer-typed address; punt to the
-                    // caller.
-                    return Ok(None);
-                };
-                let pointee_is_zst_tuple = is_empty_tuple_type(ctx, place_ty);
-                let pointee_is_thin_ptr =
-                    place_ty.deref(ctx).is::<dialect_mir::types::MirPtrType>();
-                // Slice-shaped (fat) pointees carry their element type.
-                let fat_elem_ty = slice_like_element_type(ctx, place_ty);
-
-                if pointee_is_zst_tuple {
-                    // ZST-pointee no-load exception (mirrors the Deref
-                    // handling in `translate_place`, where it covers
-                    // SharedArray): a pointer to a ZST *is* the runtime
-                    // representation of the ZST place, so the deref adds no
-                    // indirection. Keep `current` unchanged instead of
-                    // emitting a meaningless load.
-                    continue;
-                }
-
-                let is_last = proj_idx + 1 == projection.len();
-                if let Some(elem_ty) = fat_elem_ty {
-                    // Fat values (`&[T]`, `DisjointSlice<T>`, fat references
-                    // to slice-tailed structs) are a (data pointer, element
-                    // count) pair; dereferencing THROUGH them with a single
-                    // `mir.load` would treat the pair as a thin address, a
-                    // silent miscompile, so we never do that. What we CAN do:
-                    //
-                    // - Trailing `&*s` reborrow (the deref is the last
-                    //   projection): the borrow result IS the fat value,
-                    //   which lives whole in the slot, so the plain load
-                    //   below is exactly right.
-                    //
-                    // - When the next projection is one we understand,
-                    //   continue the walk by hand: load the fat PAIR,
-                    //   extract its data pointer (field 0), and process the
-                    //   following projection against that pointer. The data
-                    //   pointer addresses the ORIGINAL elements, so both
-                    //   shared and mutable borrows stay sound. This covers
-                    //   field access through a fat reference to a
-                    //   slice-tailed struct (the `(*iter).alive.start`
-                    //   accesses inside `core::array::IntoIter::next`,
-                    //   issue #138) and element access through a slice
-                    //   reference (`(*slice)[i]`, including the inlined
-                    //   body of `slice::get_mut`, issue #58).
-                    //
-                    // - Anything else keeps the loud failure (mutable) or
-                    //   the value-copy fallback (shared).
-                    if is_last {
-                        // Fall through to the load below.
-                    } else {
-                        // Load the fat (ptr, len) pair from the slot.
-                        let fat_load = Operation::new(
-                            ctx,
-                            MirLoadOp::get_concrete_op_info(),
-                            vec![place_ty],
-                            vec![current],
-                            vec![],
-                            0,
-                        );
-                        fat_load.deref_mut(ctx).set_loc(loc.clone());
-                        match current_prev_op {
-                            Some(p) => fat_load.insert_after(ctx, p),
-                            None => fat_load.insert_at_front(block_ptr, ctx),
-                        }
-                        let fat_val = fat_load.deref(ctx).get_result(0);
-
-                        if let mir::ProjectionElem::Subslice { from, to, from_end } =
-                            &projection[proj_idx + 1]
-                        {
-                            // Slice Subslice needs both halves of the fat value,
-                            // so lower it here before Deref would discard length
-                            // metadata. Optimized MIR can continue with an
-                            // Index/ConstantIndex, e.g. `(*s)[1:-1][0 of 1]`.
-                            if !*from_end {
-                                return Ok(None);
-                            }
-                            let (subslice, last_op) = emit_slice_subslice_value(
-                                ctx,
-                                fat_val,
-                                elem_ty,
-                                is_mutable,
-                                *from,
-                                *to,
-                                block_ptr,
-                                Some(fat_load),
-                                loc.clone(),
-                            )?;
-
-                            if proj_idx + 2 == projection.len() {
-                                return Ok(Some((subslice, Some(last_op))));
-                            }
-
-                            match &projection[proj_idx + 2] {
-                                mir::ProjectionElem::Index(_)
-                                | mir::ProjectionElem::ConstantIndex {
-                                    from_end: false, ..
-                                } => {
-                                    let Some(data_ptr_ty) =
-                                        erased_slice_data_pointer_type(ctx, subslice, elem_ty)
-                                    else {
-                                        return Ok(None);
-                                    };
-                                    let extract_ptr = Operation::new(
-                                        ctx,
-                                        MirExtractFieldOp::get_concrete_op_info(),
-                                        vec![data_ptr_ty],
-                                        vec![subslice],
-                                        vec![],
-                                        0,
-                                    );
-                                    extract_ptr.deref_mut(ctx).set_loc(loc.clone());
-                                    MirExtractFieldOp::new(extract_ptr).set_attr_index(
-                                        ctx,
-                                        dialect_mir::attributes::FieldIndexAttr(0),
-                                    );
-                                    extract_ptr.insert_after(ctx, last_op);
-                                    current = extract_ptr.deref(ctx).get_result(0);
-                                    current_prev_op = Some(extract_ptr);
-                                    current_is_slice_data = true;
-                                    consumed_slice_subslice = true;
-                                    continue;
-                                }
-                                _ => return Ok(None),
-                            }
-                        }
-
-                        // Extract the data pointer (field 0 of the pair).
-                        // Its pointee is the slice's element type: the
-                        // struct itself for a fat struct reference, or the
-                        // element for an ordinary `&[T]` / `DisjointSlice`.
-                        let Some(data_ptr_ty) =
-                            erased_slice_data_pointer_type(ctx, fat_val, elem_ty)
-                        else {
-                            return Ok(None);
-                        };
-                        let extract_ptr = Operation::new(
-                            ctx,
-                            MirExtractFieldOp::get_concrete_op_info(),
-                            vec![data_ptr_ty],
-                            vec![fat_val],
-                            vec![],
-                            0,
-                        );
-                        extract_ptr.deref_mut(ctx).set_loc(loc.clone());
-                        MirExtractFieldOp::new(extract_ptr)
-                            .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
-                        extract_ptr.insert_after(ctx, fat_load);
-                        let data_ptr = extract_ptr.deref(ctx).get_result(0);
-                        current_prev_op = Some(extract_ptr);
-
-                        // Borrow or index of the struct's unsized slice tail,
-                        // e.g. `&(*iter).data` or `&(*p).tail[k]`. No thin
-                        // pointer can represent the whole tail: rebuild the
-                        // `(tail pointer, len)` pair while the fat reference's
-                        // metadata is still available.
-                        if let mir::ProjectionElem::Field(field_idx, field_rust_ty) =
-                            &projection[proj_idx + 1]
-                            && let rustc_public::ty::TyKind::RigidTy(
-                                rustc_public::ty::RigidTy::Slice(tail_elem_rust_ty),
-                            ) = field_rust_ty.kind()
-                        {
-                            let tail_continuation = projection.get(proj_idx + 2);
-                            if !matches!(
-                                tail_continuation,
-                                None | Some(&mir::ProjectionElem::Index(_))
-                                    | Some(&mir::ProjectionElem::ConstantIndex { .. })
-                            ) {
-                                return Ok(None);
-                            }
-
-                            let tail_elem_ty = types::translate_type(ctx, &tail_elem_rust_ty)?;
-
-                            // Address of the first tail element. The struct
-                            // model stores the tail field with the ELEMENT
-                            // type (see `translate_type`'s ADT arm), so the
-                            // field-addr result is a pointer to the element
-                            // and the dialect verifier agrees.
-                            let tail_ptr_ty = projected_pointer_type(
-                                ctx,
-                                data_ptr.get_type(ctx),
-                                tail_elem_ty,
-                                /* legacy requested mutability, ignored */ is_mutable,
-                            )
-                            .expect("fat-pointer data extraction must yield a MirPtrType");
-                            let tail_addr = dialect_mir::ops::MirFieldAddrOp::build(
-                                ctx,
-                                data_ptr,
-                                tail_ptr_ty,
-                                *field_idx as u32,
-                            )?;
-                            tail_addr.deref_mut(ctx).set_loc(loc.clone());
-                            tail_addr.insert_after(ctx, extract_ptr);
-                            let tail_ptr = tail_addr.deref(ctx).get_result(0);
-
-                            // The element count (field 1 of the fat pair).
-                            let (len_val, extract_len) = emit_slice_len_extract(
-                                ctx,
-                                fat_val,
-                                block_ptr,
-                                Some(tail_addr),
-                                loc.clone(),
-                            );
-
-                            // Erased kind on purpose: this fat value is a projection-internal
-                            // reconstruction of the DST tail. A Rust kind is established only
-                            // when the value crosses an `Rvalue::Ref`/`AddressOf` boundary,
-                            // which retypes it to the declared kind.
-                            let tail_is_mutable = tail_ptr_ty
-                                .deref(ctx)
-                                .downcast_ref::<dialect_mir::types::MirPtrType>()
-                                .expect("slice-tail projection must produce a MirPtrType")
-                                .is_mutable;
-                            let slice_ty = dialect_mir::types::MirSliceType::get_with_mutability(
-                                ctx,
-                                tail_elem_ty,
-                                tail_is_mutable,
-                            );
-                            use dialect_mir::ops::MirConstructSliceOp;
-                            let construct = Operation::new(
-                                ctx,
-                                MirConstructSliceOp::get_concrete_op_info(),
-                                vec![slice_ty.into()],
-                                vec![tail_ptr, len_val],
-                                vec![],
-                                0,
-                            );
-                            construct.deref_mut(ctx).set_loc(loc.clone());
-                            construct.insert_after(ctx, extract_len);
-                            let tail_slice = construct.deref(ctx).get_result(0);
-
-                            // Whole-tail borrow/reborrow: return the fat value.
-                            if tail_continuation.is_none() {
-                                return Ok(Some((tail_slice, Some(construct))));
-                            }
-
-                            // Element borrow/write: normalize the rebuilt tail
-                            // to its data pointer, then let the existing
-                            // Index/ConstantIndex arms perform the element
-                            // offset and return the real address.
-                            let Some(indexed_data_ptr_ty) =
-                                erased_slice_data_pointer_type(ctx, tail_slice, tail_elem_ty)
-                            else {
-                                return Ok(None);
-                            };
-                            let indexed_extract = Operation::new(
-                                ctx,
-                                MirExtractFieldOp::get_concrete_op_info(),
-                                vec![indexed_data_ptr_ty],
-                                vec![tail_slice],
-                                vec![],
-                                0,
-                            );
-                            indexed_extract.deref_mut(ctx).set_loc(loc.clone());
-                            MirExtractFieldOp::new(indexed_extract)
-                                .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
-                            indexed_extract.insert_after(ctx, construct);
-
-                            current = indexed_extract.deref(ctx).get_result(0);
-                            current_prev_op = Some(indexed_extract);
-                            current_is_slice_data = true;
-                            current_slice_len = if matches!(
-                                tail_continuation,
-                                Some(&mir::ProjectionElem::ConstantIndex { from_end: true, .. })
-                            ) {
-                                Some(len_val)
-                            } else {
-                                None
-                            };
-                            consumed_slice_tail_field = true;
-                            continue;
-                        }
-
-                        match &projection[proj_idx + 1] {
-                            // Sized field access: hand the data pointer to
-                            // the field arm below. If the field is itself a
-                            // slice-tailed DST, preserve the fat reference's
-                            // metadata until the walk reaches the actual `[T]`
-                            // tail field.
-                            mir::ProjectionElem::Field(_, field_rust_ty) => {
-                                if types::slice_tail_element_ty(field_rust_ty).is_some() {
-                                    let (len, len_op) = emit_slice_len_extract(
-                                        ctx,
-                                        fat_val,
-                                        block_ptr,
-                                        current_prev_op,
-                                        loc.clone(),
-                                    );
-                                    current_prev_op = Some(len_op);
-                                    carried_slice_tail_len = Some(len);
-                                }
-                                current = data_ptr;
-                                continue;
-                            }
-                            // Element access through a slice data pointer is
-                            // pointer arithmetic over the slice element type.
-                            // That remains true when the element type is
-                            // itself an array (`&[[T; N]][i]`), where a
-                            // type-only check would otherwise mistake the
-                            // data pointer for a pointer to one array object
-                            // and index inside row 0.
-                            mir::ProjectionElem::Index(_) => {
-                                current = data_ptr;
-                                current_is_slice_data = true;
-                                continue;
-                            }
-                            mir::ProjectionElem::ConstantIndex { from_end, .. } => {
-                                current = data_ptr;
-                                current_is_slice_data = true;
-                                if *from_end {
-                                    let (len, len_op) = emit_slice_len_extract(
-                                        ctx,
-                                        fat_val,
-                                        block_ptr,
-                                        current_prev_op,
-                                        loc.clone(),
-                                    );
-                                    current_prev_op = Some(len_op);
-                                    current_slice_len = Some(len);
-                                }
-                                continue;
-                            }
-                            // Unknown continuation: keep the conservative
-                            // behaviour (loud failure for mutable borrows,
-                            // value-copy fallback for shared ones).
-                            _ => {
-                                if is_mutable {
-                                    return input_err!(
-                                        loc,
-                                        TranslationErr::unsupported(format!(
-                                            "cannot compute a mutable in-memory address through \
-                                             fat-pointer deref (projection {:?})",
-                                            projection
-                                        ))
-                                    );
-                                }
-                                return Ok(None);
-                            }
-                        }
-                    }
-                } else if !pointee_is_thin_ptr {
-                    // Deref of a non-pointer-typed place (a type the
-                    // importer models by value); punt to the caller.
-                    return Ok(None);
-                }
-
-                let load_op = Operation::new(
-                    ctx,
-                    MirLoadOp::get_concrete_op_info(),
-                    vec![place_ty],
-                    vec![current],
-                    vec![],
-                    0,
-                );
-                load_op.deref_mut(ctx).set_loc(loc.clone());
-                match current_prev_op {
-                    Some(p) => load_op.insert_after(ctx, p),
-                    None => load_op.insert_at_front(block_ptr, ctx),
-                }
-                current = load_op.deref(ctx).get_result(0);
-                current_prev_op = Some(load_op);
-            }
-
-            mir::ProjectionElem::Field(field_idx, field_ty) => {
-                let tail_elem_rust_ty = match field_ty.kind() {
-                    rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Slice(elem)) => {
-                        Some(elem)
-                    }
-                    _ => None,
-                };
-
-                if let Some(tail_len) = carried_slice_tail_len.take() {
-                    if let Some(tail_elem_rust_ty) = tail_elem_rust_ty {
-                        // Element-address traversal through an unsized tail is
-                        // intentionally left to #881. For #880 the address path
-                        // only needs to materialize the whole nested slice tail.
-                        if proj_idx + 1 != projection.len() || pending_variant.is_some() {
-                            return Ok(None);
-                        }
-
-                        let tail_elem_ty = types::translate_type(ctx, &tail_elem_rust_ty)?;
-                        let Some(tail_ptr_ty) = projected_pointer_type(
-                            ctx,
-                            current.get_type(ctx),
-                            tail_elem_ty,
-                            is_mutable,
-                        ) else {
-                            return Ok(None);
-                        };
-
-                        // The physical struct stores an unsized slice tail as
-                        // its element type, so the field address must be `*T`,
-                        // not `*[T]`.
-                        let tail_addr = dialect_mir::ops::MirFieldAddrOp::build(
-                            ctx,
-                            current,
-                            tail_ptr_ty,
-                            *field_idx as u32,
-                        )?;
-                        tail_addr.deref_mut(ctx).set_loc(loc.clone());
-                        match current_prev_op {
-                            Some(previous) => tail_addr.insert_after(ctx, previous),
-                            None => tail_addr.insert_at_front(block_ptr, ctx),
-                        }
-                        let tail_ptr = tail_addr.deref(ctx).get_result(0);
-
-                        // Erased kind on purpose: this fat value is a projection-internal
-                        // reconstruction of the DST tail. A Rust kind is established only
-                        // when the value crosses an `Rvalue::Ref`/`AddressOf` boundary,
-                        // which retypes it to the declared kind.
-                        let tail_is_mutable = tail_ptr_ty
-                            .deref(ctx)
-                            .downcast_ref::<dialect_mir::types::MirPtrType>()
-                            .expect("slice-tail projection must produce a MirPtrType")
-                            .is_mutable;
-                        let slice_ty = dialect_mir::types::MirSliceType::get_with_mutability(
-                            ctx,
-                            tail_elem_ty,
-                            tail_is_mutable,
-                        );
-                        use dialect_mir::ops::MirConstructSliceOp;
-                        let construct = Operation::new(
-                            ctx,
-                            MirConstructSliceOp::get_concrete_op_info(),
-                            vec![slice_ty.into()],
-                            vec![tail_ptr, tail_len],
-                            vec![],
-                            0,
-                        );
-                        construct.deref_mut(ctx).set_loc(loc.clone());
-                        construct.insert_after(ctx, tail_addr);
-                        return Ok(Some((construct.deref(ctx).get_result(0), Some(construct))));
-                    }
-
-                    // Metadata remains relevant only while descending through
-                    // another slice-tailed DST field. A sized field projects
-                    // away from the unsized tail, so discard it there.
-                    if types::slice_tail_element_ty(field_ty).is_some() {
-                        carried_slice_tail_len = Some(tail_len);
-                    }
-                }
-
-                let field_type = types::translate_type(ctx, field_ty)?;
-
-                // After a `Downcast`, the field belongs to that variant, and an
-                // enum names its payload fields by position in the flattened
-                // `all_field_types`. Translate the per-variant index into that
-                // flat one; a non-enum pointee keeps the index as written.
-                let pointee = current
-                    .get_type(ctx)
-                    .deref(ctx)
-                    .downcast_ref::<dialect_mir::types::MirPtrType>()
-                    .map(|ptr| ptr.pointee);
-                let pointee_is_enum = pointee.is_some_and(|pointee| {
-                    pointee.deref(ctx).is::<dialect_mir::types::MirEnumType>()
-                });
-                let flat_field_index = match pending_variant.take() {
-                    Some(variant) => {
-                        let flat = pointee.and_then(|pointee| {
-                            pointee
-                                .deref(ctx)
-                                .downcast_ref::<dialect_mir::types::MirEnumType>()
-                                .and_then(|enum_ty| enum_ty.flat_field_index(variant, *field_idx))
-                        });
-                        match flat {
-                            Some(flat) => {
-                                // A payload whose bytes use canonical storage
-                                // that differs from its semantic type (bool
-                                // leaves are i8 bytes, shared-memory pointer
-                                // leaves are generic pointers) has no honest
-                                // raw address: reads and writes through one
-                                // are typed with the SEMANTIC type. For a
-                                // SHARED borrow the value-copy fallback is
-                                // sound and matches what the importer did
-                                // before payload addressing existed, so punt.
-                                // Mutable borrows and assignment stores keep
-                                // the address path, where mir-lower's
-                                // canonical-storage gate stays the loud,
-                                // fail-closed authority (so a conservative
-                                // miss here errors instead of miscompiling).
-                                if !is_mutable
-                                    && enum_payload_needs_storage_coercion(ctx, field_type)
-                                {
-                                    return Ok(None);
-                                }
-                                flat as u32
-                            }
-                            // A downcast over something this walker cannot
-                            // resolve to an enum payload position. Punt rather
-                            // than address the wrong bytes.
-                            None => return Ok(None),
-                        }
-                    }
-                    // Valid MIR never applies `Field` to an enum place without
-                    // a `Downcast` naming the variant first (rustc's own place
-                    // typing has no answer for it). `MirFieldAddrOp` reads an
-                    // enum-pointee index as a FLATTENED (variant, field)
-                    // position, so passing this raw per-variant index through
-                    // could silently address another variant's payload. Only an
-                    // importer bug or invalid MIR reaches here; fail loudly.
-                    None if pointee_is_enum => {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "Field projection on an enum place without a preceding \
-                                 Downcast (projection {:?})",
-                                projection
-                            ))
-                        );
-                    }
-                    None => *field_idx as u32,
-                };
-
-                // Field address computation must remain in the address space of the
-                // aggregate pointer. LLVM GEP cannot change address spaces.
-                let Some(result_ptr_ty) =
-                    projected_pointer_type(ctx, current.get_type(ctx), field_type, is_mutable)
-                else {
-                    return Ok(None);
-                };
-
-                let op = dialect_mir::ops::MirFieldAddrOp::build(
-                    ctx,
-                    current,
-                    result_ptr_ty,
-                    flat_field_index,
-                )?;
-                op.deref_mut(ctx).set_loc(loc.clone());
-
-                match current_prev_op {
-                    Some(previous) => op.insert_after(ctx, previous),
-                    None => op.insert_at_front(block_ptr, ctx),
-                }
-
-                current = op.deref(ctx).get_result(0);
-                current_prev_op = Some(op);
-            }
-
-            mir::ProjectionElem::ConstantIndex {
-                offset,
-                min_length: _,
-                from_end,
-            } => {
-                let (mut pointee_kind, addr_space) = match pointer_pointee_kind(ctx, current) {
-                    Some(kind) => kind,
-                    None => return Ok(None),
-                };
-                if entered_as_slice_data {
-                    pointee_kind = PointeeKind::Direct;
-                }
-
-                let index_val = if *from_end {
-                    // Never derive this from the pointee type. For
-                    // `&[[T; N]]`, the pointee array length N is the row
-                    // width, while this index selects a row from the outer
-                    // runtime-length slice.
-                    if !entered_as_slice_data {
-                        return Ok(None);
-                    }
-                    let Some(slice_len) = entered_slice_len else {
-                        return Ok(None);
-                    };
-                    let (index, sub_op) = emit_from_end_slice_index(
-                        ctx,
-                        slice_len,
-                        *offset,
-                        block_ptr,
-                        current_prev_op,
-                        loc.clone(),
-                    )?;
-                    current_prev_op = Some(sub_op);
-                    index
-                } else {
-                    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signed);
-                    let index_apint =
-                        APInt::from_i64(*offset as i64, NonZeroUsize::new(64).unwrap());
-                    let const_attr =
-                        pliron::builtin::attributes::IntegerAttr::new(i64_ty, index_apint);
-                    let const_op_ptr = Operation::new(
-                        ctx,
-                        MirConstantOp::get_concrete_op_info(),
-                        vec![i64_ty.into()],
-                        vec![],
-                        vec![],
-                        0,
-                    );
-                    const_op_ptr.deref_mut(ctx).set_loc(loc.clone());
-                    MirConstantOp::new(const_op_ptr).set_attr_value(ctx, const_attr);
-                    match current_prev_op {
-                        Some(p) => const_op_ptr.insert_after(ctx, p),
-                        None => const_op_ptr.insert_at_front(block_ptr, ctx),
-                    }
-                    current_prev_op = Some(const_op_ptr);
-                    const_op_ptr.deref(ctx).get_result(0)
-                };
-
-                let (addr_op, next_current) = emit_indexed_element_addr(
-                    ctx,
-                    current,
-                    index_val,
-                    pointee_kind,
-                    addr_space,
-                    is_mutable,
-                    block_ptr,
-                    current_prev_op,
-                    loc.clone(),
-                );
-                current = next_current;
-                current_prev_op = Some(addr_op);
-            }
-
-            // Runtime `arr[i]` indexing. Without this arm, a place like
-            // `&(*ptr).field[i]` would silently drop the `Index` projection
-            // and return a pointer to the array's first slot, miscompiling
-            // every load through the reference into a load of element 0.
-            mir::ProjectionElem::Index(index_local) => {
-                let (mut pointee_kind, addr_space) = match pointer_pointee_kind(ctx, current) {
-                    Some(kind) => kind,
-                    None => return Ok(None),
-                };
-                if entered_as_slice_data {
-                    pointee_kind = PointeeKind::Direct;
-                }
-
-                let index_place = mir::Place {
-                    local: *index_local,
-                    projection: vec![],
-                };
-                let (index_val, next_prev_op) = translate_place(
-                    ctx,
-                    body,
-                    &index_place,
-                    value_map,
-                    block_ptr,
-                    current_prev_op,
-                    loc.clone(),
-                )?;
-                current_prev_op = next_prev_op;
-
-                let (addr_op, next_current) = emit_indexed_element_addr(
-                    ctx,
-                    current,
-                    index_val,
-                    pointee_kind,
-                    addr_space,
-                    is_mutable,
-                    block_ptr,
-                    current_prev_op,
-                    loc.clone(),
-                );
-                current = next_current;
-                current_prev_op = Some(addr_op);
-            }
-
-            mir::ProjectionElem::Subslice { from, to, from_end } => {
-                if *from_end && consumed_slice_subslice {
-                    consumed_slice_subslice = false;
-                    current_is_slice_data = true;
-                    continue;
-                }
-                // A slice Subslice must be lowered while the fat-pointer
-                // metadata is available in the preceding Deref arm.
-                if *from_end {
-                    return Ok(None);
-                }
-                let (subslice_ptr, last_op) = emit_array_subslice_address(
-                    ctx,
-                    current,
-                    *from,
-                    *to,
-                    is_mutable,
-                    block_ptr,
-                    current_prev_op,
-                    loc.clone(),
-                )?;
-                current = subslice_ptr;
-                current_prev_op = Some(last_op);
-            }
-
-            // Enum-variant downcast (`(x as Variant).field`). The downcast
-            // itself moves no address: a payload shares the enum's storage, so
-            // the variant only decides which field the next `Field` names.
-            // Record it and let that arm resolve the flattened payload
-            // position; lowering maps it to a slot or a byte offset through
-            // the enum slot map.
-            mir::ProjectionElem::Downcast(variant_idx) => {
-                pending_variant = Some(variant_idx.to_index());
-            }
-
-            // Remaining projection kinds (OpaqueCast, Subtype) aren't lowered
-            // to addresses here yet. Punt to the caller,
-            // which decides between a value fallback (shared borrows) and a
-            // hard error (mutable borrows).
-            _ => return Ok(None),
-        }
-    }
-
-    // A chain that ENDS on a `Downcast` never occurs in valid MIR (the
-    // validator requires a `Field` after it). Punt rather than hand back the
-    // enum's own address as if it were the variant's payload place.
-    if pending_variant.is_some() || carried_slice_tail_len.is_some() {
-        return Ok(None);
-    }
-
-    Ok(Some((current, current_prev_op)))
-}
-
-/// Describes what a pointer points to (array vs. anything else) for
-/// address-computation dispatch.
-enum PointeeKind {
-    /// Pointee is `[T; N]` (carries `T`). Element addressing GEPs through
-    /// the array type via `mir.array_element_addr`.
-    Array(TypeHandle),
-    /// Pointee is any other type. When an `Index` / `ConstantIndex`
-    /// projection meets such a pointer, MIR typing guarantees the indexed
-    /// place is a slice whose data pointer (produced by the fat-pointer
-    /// `Deref` arm) points directly at the elements, so element addressing
-    /// is a plain `mir.ptr_offset` keeping the pointer's own type.
-    Direct,
-}
-
-fn indexed_element_ptr_type(
-    ctx: &mut Context,
-    current_ptr_ty: TypeHandle,
-    pointee_kind: PointeeKind,
-    _addr_space: u32,
-    _is_mutable: bool,
-) -> TypeHandle {
-    match pointee_kind {
-        PointeeKind::Array(element_ty) => projected_pointer_type(
-            ctx,
-            current_ptr_ty,
-            element_ty,
-            /* legacy requested mutability, ignored */ false,
-        )
-        .expect("indexed array base must be a MirPtrType"),
-        PointeeKind::Direct => current_ptr_ty,
-    }
-}
-
-/// Emit the address of element `index_val` behind `current`, which is either
-/// a pointer to a whole array (`&arr[i]`: `mir.array_element_addr`) or a
-/// pointer to a single ELEMENT, i.e. the data pointer of a fat slice value
-/// extracted by the Deref arm above (`(*slice)[i]`: element-size pointer
-/// arithmetic via `mir.ptr_offset`). Returns the emitted op and the element
-/// address it produces.
-#[allow(clippy::too_many_arguments)]
-fn emit_indexed_element_addr(
-    ctx: &mut Context,
-    current: Value,
-    index_val: Value,
-    pointee_kind: PointeeKind,
-    _addr_space: u32,
-    is_mutable: bool,
-    block_ptr: Ptr<BasicBlock>,
-    current_prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> (Ptr<Operation>, Value) {
-    use dialect_mir::ops::MirArrayElementAddrOp;
-
-    let addr_op = match pointee_kind {
-        PointeeKind::Array(element_ty) => {
-            let elem_ptr_ty =
-                projected_pointer_type(ctx, current.get_type(ctx), element_ty, is_mutable)
-                    .expect("indexed array base must be a MirPtrType");
-            Operation::new(
-                ctx,
-                MirArrayElementAddrOp::get_concrete_op_info(),
-                vec![elem_ptr_ty],
-                vec![current, index_val],
-                vec![],
-                0,
-            )
-        }
-        PointeeKind::Direct => {
-            // The pointee IS the element type, so indexing is plain
-            // element-size pointer arithmetic and the result keeps the
-            // pointer's own type.
-            let ptr_ty = current.get_type(ctx);
-            Operation::new(
-                ctx,
-                MirPtrOffsetOp::get_concrete_op_info(),
-                vec![ptr_ty],
-                vec![current, index_val],
-                vec![],
-                0,
-            )
-        }
-    };
-    addr_op.deref_mut(ctx).set_loc(loc);
-    match current_prev_op {
-        Some(p) => addr_op.insert_after(ctx, p),
-        None => addr_op.insert_at_front(block_ptr, ctx),
-    }
-    let result = addr_op.deref(ctx).get_result(0);
-    (addr_op, result)
-}
-
-/// Inspect a pointer value and return its pointee kind + address space, or
-/// `None` if the value's type isn't a `MirPtrType`.
-fn pointer_pointee_kind(ctx: &Context, ptr_value: Value) -> Option<(PointeeKind, u32)> {
-    pointer_type_pointee_kind(ctx, ptr_value.get_type(ctx))
-}
-
-/// Inspect a pointer type and return its pointee kind + address space, or
-/// `None` if the type isn't a `MirPtrType`.
-fn pointer_type_pointee_kind(ctx: &Context, ptr_ty: TypeHandle) -> Option<(PointeeKind, u32)> {
-    let ty_ref = ptr_ty.deref(ctx);
-    let mir_ptr_ty = ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>()?;
-    let pointee = mir_ptr_ty.pointee;
-    let addr_space = mir_ptr_ty.address_space;
-    let pointee_ref = pointee.deref(ctx);
-    let kind = if let Some(arr_ty) = pointee_ref.downcast_ref::<dialect_mir::types::MirArrayType>()
-    {
-        PointeeKind::Array(arr_ty.element_type())
-    } else {
-        PointeeKind::Direct
-    };
-    Some((kind, addr_space))
-}
-
-fn mir_ptr_pointee(ctx: &Context, ptr_ty: TypeHandle) -> Option<TypeHandle> {
-    ptr_ty
-        .deref(ctx)
-        .downcast_ref::<dialect_mir::types::MirPtrType>()
-        .map(|ptr_ty| ptr_ty.pointee)
-}
-
-/// Build a pointer to `pointee` while preserving the address space of
-/// `base_ptr_ty`.
-///
-/// Address-producing projections such as field access are LLVM GEPs, and a
-/// GEP cannot change the address space of its base pointer.
-fn projected_pointer_type(
-    ctx: &mut Context,
-    base_ptr_ty: TypeHandle,
-    pointee: TypeHandle,
-    _is_mutable: bool,
-) -> Option<TypeHandle> {
-    let (origin, address_space) = {
-        let base_ptr_ty = base_ptr_ty.deref(ctx);
-        let base_ptr_ty = base_ptr_ty.downcast_ref::<dialect_mir::types::MirPtrType>()?;
-        (
-            facts::pointer_origin_of_ptr_carrier(base_ptr_ty),
-            base_ptr_ty.address_space,
-        )
-    };
-
-    Some(facts::mint_ptr_type(ctx, pointee, address_space, origin).into())
-}
-
-/// Build a `DisjointSlice` value from the fields of its MIR aggregate.
-///
-/// The literal lists `ptr`, `len`, the index space's runtime layout, and the
-/// marker fields; the markers are zero-sized and carry nothing, so dropping
-/// them leaves the operands `mir.construct_disjoint_slice` takes, in the same
-/// order. An index space with no runtime layout (`Index1D`, `Index2D<S>`)
-/// stores `()` there, which drops with the markers and leaves the two-word
-/// slice.
-///
-/// Field selection is positional, which the op's verifier then checks against
-/// the result type: the data pointer must point to the element type, the
-/// length must be an integer, and each remaining operand must match the index
-/// space's layout types in order. A reordered or retyped field therefore
-/// fails at verification rather than silently writing a row width into the
-/// length slot.
-fn construct_disjoint_slice_aggregate(
-    ctx: &mut Context,
-    adt_ty: TypeHandle,
-    field_values: &[Value],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
-    let (element_type, space_tys) = {
-        let ty_obj = adt_ty.deref(ctx);
-        let slice_ty = ty_obj
-            .downcast_ref::<dialect_mir::types::MirDisjointSliceType>()
-            .expect("caller checked the disjoint slice type");
-        (slice_ty.element_type(), slice_ty.space_types().to_vec())
-    };
-
-    let runtime_fields: Vec<Value> = field_values
-        .iter()
-        .copied()
-        .filter(|value| !types::is_zst_type(ctx, value.get_type(ctx)))
-        .collect();
-
-    let expected = 2 + space_tys.len();
-    if runtime_fields.len() != expected {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "DisjointSlice aggregate expected {} runtime fields for {}, found {}",
-                expected,
-                adt_ty.disp(ctx),
-                runtime_fields.len()
-            ))
-        );
-    }
-
-    // The data pointer reaches the slice through the generic address space,
-    // as the fat-pointer arm does for `*mut [T]`: a value coming from shared
-    // memory carries addrspace(3) and would not match the element pointer the
-    // verifier expects.
-    let expected_ptr_ty: TypeHandle =
-        facts::mint_generic_ptr_type(ctx, element_type, facts::abi_disjoint_slice_data_ptr())
-            .into();
-    let (data_val, current_prev_op) = cast_to_expected_pointer_type_if_needed(
-        ctx,
-        runtime_fields[0],
-        expected_ptr_ty,
-        block_ptr,
-        prev_op,
-        loc.clone(),
-    );
-
-    let mut operands = vec![data_val];
-    operands.extend_from_slice(&runtime_fields[1..]);
-
-    let op = Operation::new(
-        ctx,
-        dialect_mir::ops::MirConstructDisjointSliceOp::get_concrete_op_info(),
-        vec![adt_ty],
-        operands,
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc);
-
-    let result = op.deref(ctx).get_result(0);
-    Ok((Some(op), result, current_prev_op))
-}
-
-fn is_empty_tuple_type(ctx: &Context, ty: TypeHandle) -> bool {
-    ty.deref(ctx)
-        .downcast_ref::<dialect_mir::types::MirTupleType>()
-        .is_some_and(|tt| tt.get_types().is_empty())
-}
-
-/// Whether `ty` is a tuple carrying a field that owns zero bytes while
-/// demanding ABI alignment above 1, at any array nesting depth.
-///
-/// Code-shape guard for the read classifier: the address path's final
-/// `mir.load` states the loaded field's natural alignment only, so a tuple
-/// whose recorded ABI alignment comes from a zero-sized `repr(align(N))`
-/// field must keep the value path, which moves the whole aggregate at its
-/// recorded alignment. Gate shape from PR #715 (vyncint), with the byte-size
-/// gap closed: detection compares byte sizes, not element counts, so
-/// `[Align32; 2]` still reads as zero bytes.
-fn tuple_has_over_aligned_zst_field(ctx: &Context, ty: TypeHandle) -> bool {
-    ty.deref(ctx)
-        .downcast_ref::<dialect_mir::types::MirTupleType>()
-        .is_some_and(|tuple_ty| {
-            tuple_ty
-                .get_types()
-                .iter()
-                .any(|field| is_over_aligned_zst_type(ctx, *field))
-        })
-}
-
-/// Whether `ty` occupies zero bytes while its recorded ABI alignment exceeds
-/// 1: a `repr(align(N))` ZST, possibly wrapped in arrays.
-fn is_over_aligned_zst_type(ctx: &Context, ty: TypeHandle) -> bool {
-    recorded_byte_size_and_abi_align(ctx, ty)
-        .is_some_and(|(byte_size, abi_align)| byte_size == 0 && abi_align > 1)
-}
-
-/// Byte size and ABI alignment of `ty`, when the dialect records them.
-///
-/// Aggregates carry rustc's `total_size` and `abi_align` directly. Arrays
-/// multiply the element's byte size by the element count
-/// (`MirArrayType::size()` is a count, not a byte size) and align like their
-/// element. Scalars and pointers return `None`: they always occupy at least
-/// one byte, so they can never be a zero-sized alignment carrier.
-fn recorded_byte_size_and_abi_align(ctx: &Context, ty: TypeHandle) -> Option<(u64, u64)> {
-    use dialect_mir::types::{
-        MirArrayType, MirEnumType, MirStructType, MirTupleType, MirUnionType,
-    };
-
-    let ty_ref = ty.deref(ctx);
-    if let Some(array_ty) = ty_ref.downcast_ref::<MirArrayType>() {
-        let element_ty = array_ty.element_type();
-        let element_count = array_ty.size();
-        return recorded_byte_size_and_abi_align(ctx, element_ty).map(
-            |(element_size, element_align)| {
-                (element_size.saturating_mul(element_count), element_align)
-            },
-        );
-    }
-    if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
-        return Some((tuple_ty.total_size(), tuple_ty.abi_align()));
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
-        return Some((struct_ty.total_size(), struct_ty.abi_align));
-    }
-    if let Some(enum_ty) = ty_ref.downcast_ref::<MirEnumType>() {
-        return Some((enum_ty.total_size(), enum_ty.abi_align()));
-    }
-    if let Some(union_ty) = ty_ref.downcast_ref::<MirUnionType>() {
-        return Some((union_ty.total_size(), union_ty.abi_align()));
-    }
-    None
-}
-
-fn slice_like_element_type(ctx: &Context, ty: TypeHandle) -> Option<TypeHandle> {
-    let ty_ref = ty.deref(ctx);
-    ty_ref
-        .downcast_ref::<dialect_mir::types::MirSliceType>()
-        .map(|slice_ty| slice_ty.element_type())
-        .or_else(|| {
-            ty_ref
-                .downcast_ref::<dialect_mir::types::MirDisjointSliceType>()
-                .map(|slice_ty| slice_ty.element_type())
-        })
-}
-
-/// Return the projection-internal data-pointer type for a fat slice value.
-///
-/// Ordinary slices deliberately erase their Rust pointer kind while retaining
-/// the carrier's exact machine mutability. `DisjointSlice` instead has a fixed
-/// `RawMut` field contract. In both cases extraction is representation-only:
-/// it cannot invent writable evidence or a stronger Rust category.
-fn erased_slice_data_pointer_type(
-    ctx: &mut Context,
-    slice_value: Value,
-    element_ty: TypeHandle,
-) -> Option<TypeHandle> {
-    let slice_ty = slice_value.get_type(ctx);
-    let ordinary_mutability = slice_ty
-        .deref(ctx)
-        .downcast_ref::<dialect_mir::types::MirSliceType>()
-        .map(|slice| slice.is_mutable);
-    if let Some(is_mutable) = ordinary_mutability {
-        return Some(
-            dialect_mir::types::MirPtrType::get_generic(ctx, element_ty, is_mutable).into(),
-        );
-    }
-    if slice_ty
-        .deref(ctx)
-        .downcast_ref::<dialect_mir::types::MirDisjointSliceType>()
-        .is_some()
-    {
-        return Some(
-            facts::mint_generic_ptr_type(ctx, element_ty, facts::abi_disjoint_slice_data_ptr())
-                .into(),
-        );
-    }
-    None
-}
-
-fn rust_ty_is_slice(ty: &rustc_public::ty::Ty) -> bool {
-    matches!(
-        ty.kind(),
-        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Slice(_))
-    )
-}
-
-fn normalize_slice_value_to_data_ptr(
-    ctx: &mut Context,
-    value: Value,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> (Value, Option<Ptr<Operation>>) {
-    let slice_element_ty = {
-        let value_ty = value.get_type(ctx);
-        let value_ty_ref = value_ty.deref(ctx);
-        value_ty_ref
-            .downcast_ref::<dialect_mir::types::MirSliceType>()
-            .map(|slice_ty| slice_ty.element_type())
-    };
-    let Some(element_ty) = slice_element_ty else {
-        return (value, prev_op);
-    };
-
-    let Some(data_ptr_ty) = erased_slice_data_pointer_type(ctx, value, element_ty) else {
-        return (value, prev_op);
-    };
-    let extract_ptr = Operation::new(
-        ctx,
-        MirExtractFieldOp::get_concrete_op_info(),
-        vec![data_ptr_ty],
-        vec![value],
-        vec![],
-        0,
-    );
-    extract_ptr.deref_mut(ctx).set_loc(loc);
-    MirExtractFieldOp::new(extract_ptr)
-        .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
-    match prev_op {
-        Some(prev) => extract_ptr.insert_after(ctx, prev),
-        None => extract_ptr.insert_at_front(block_ptr, ctx),
-    }
-
-    (extract_ptr.deref(ctx).get_result(0), Some(extract_ptr))
-}
-
-/// Translate a MIR Place using iterative projection processing.
-/// This handles arbitrary depth projections by processing each element in sequence.
-pub fn translate_place_iterative(
-    ctx: &mut Context,
-    body: &mir::Body,
-    place: &mir::Place,
-    value_map: &ValueMap,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    // Start with the base local's current value. In the alloca model every
-    // non-ZST local has a stack slot, so we emit `mir.load` once here and
-    // then layer projections on top of the loaded SSA value; `mem2reg` folds
-    // the load back into a direct SSA use when the slot is promotable. ZST /
-    // unsupported locals fall back to the same ghost-enum / empty-aggregate
-    // synthesis as [`translate_place`].
-    let local = place.local;
-    let (mut current_value, mut current_prev_op) = match value_map
-        .load_local(ctx, local, block_ptr, prev_op)
-    {
-        Some((load_op, val)) => (val, Some(load_op)),
-        None => {
-            let local_decl = &body.locals()[local];
-            let ty_ptr = types::translate_type(ctx, &local_decl.ty)?;
-            if ty_ptr.deref(ctx).is::<dialect_mir::types::MirEnumType>() {
-                let synth_op = create_ghost_enum_default(ctx, ty_ptr, loc.clone());
-                match prev_op {
-                    Some(p) => synth_op.insert_after(ctx, p),
-                    None => synth_op.insert_at_front(block_ptr, ctx),
-                }
-                let val = synth_op.deref(ctx).get_result(0);
-                (val, Some(synth_op))
-            } else if types::is_zst_type(ctx, ty_ptr) {
-                translate_zero_sized_constant_value(ctx, ty_ptr, block_ptr, prev_op, loc.clone())?
-            } else {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Local {} has no alloca slot and is not a ZST",
-                        Into::<usize>::into(local)
-                    ))
-                );
-            }
-        }
-    };
-
-    // Track the Rust type of `current_value` alongside the pliron value.
-    // Each iteration below advances it through rustc_public's own projection
-    // typing (`ProjectionElem::ty`) AFTER the arm has processed the element,
-    // so every arm observes the type *before* its own projection applies and
-    // the next iteration sees the narrowed type. `Downcast` deliberately
-    // leaves the type unchanged (still the enum ADT), which is exactly what
-    // `apply_enum_field_projection` expects when the following `Field` fires.
-    //
-    // This single fold is the only place `current_rust_ty` is updated;
-    // individual arms must not update it themselves. Per-arm updates were
-    // the cause of issue #131: only `Field` advanced the type, so chains
-    // like `[Index, Downcast, Field]` (from `match xs[i]` over an array of
-    // enums) handed the stale Array type to the Downcast/Field handler,
-    // which bailed with "Downcast on non-ADT type: Array". The same
-    // staleness affected `Deref` and `ConstantIndex`.
-    let mut current_rust_ty = body.locals()[local].ty;
-
-    // Track pending downcast (Downcast is a no-op, but we need variant info for Field on enums)
-    // Type inferred from ProjectionElem::Downcast pattern
-    let mut pending_downcast = None;
-
-    // When Deref of a slice is immediately followed by Subslice, keep the fat
-    // value intact for one iteration so Subslice can update both data and len.
-    // The ordinary Deref helper intentionally drops len and returns only the
-    // data pointer because Index/ConstantIndex do not need metadata.
-    let mut preserved_slice_deref_mutability: Option<bool> = None;
-
-    // A fat reference to a slice-tailed struct carries the runtime length of
-    // that tail in field 1. Keep the metadata alongside the projected address
-    // until the walk reaches the actual slice field. This mirrors rustc's
-    // `llextra` model and lets metadata survive through nested slice-tailed
-    // struct fields such as `outer.inner.tail[k]`.
-    let mut carried_slice_tail_len: Option<Value> = None;
-
-    // Process each projection element iteratively
-    for (proj_idx, projection) in place.projection.iter().enumerate() {
-        match projection {
-            ProjectionElem::Deref => {
-                let next_is_slice_subslice = matches!(
-                    place.projection.get(proj_idx + 1),
-                    Some(ProjectionElem::Subslice { from_end: true, .. })
-                );
-                let current_is_fat_slice = current_value
-                    .get_type(ctx)
-                    .deref(ctx)
-                    .is::<dialect_mir::types::MirSliceType>();
-                let pointer_info = get_static_pointer_info(&current_rust_ty);
-                let slice_deref_mutability = pointer_info.as_ref().and_then(|(pointee, origin)| {
-                    rust_ty_is_slice(pointee).then_some(origin.is_mutable())
-                });
-                let current_is_slice_tail_ref = pointer_info
-                    .as_ref()
-                    .is_some_and(|(pointee, _)| types::slice_tail_element_ty(pointee).is_some());
-
-                if next_is_slice_subslice
-                    && current_is_fat_slice
-                    && slice_deref_mutability.is_some()
-                {
-                    // Preserve the fat pair. The following Subslice consumes
-                    // both data and len and advances `current_rust_ty` normally.
-                    preserved_slice_deref_mutability = slice_deref_mutability;
-                    carried_slice_tail_len = None;
-                } else {
-                    // `&S<[T]>` uses the same fat-pair carrier as a slice, but
-                    // field 0 points at the struct prefix while field 1 is the
-                    // trailing slice length. Extract that metadata before Deref
-                    // reduces the value to the struct data pointer. Unlike the
-                    // old one-step handoff, keep it alive across any nested
-                    // slice-tailed struct fields until the real `[T]` field is
-                    // reached.
-                    carried_slice_tail_len = if current_is_fat_slice && current_is_slice_tail_ref {
-                        let (len, len_op) = emit_slice_len_extract(
-                            ctx,
-                            current_value,
-                            block_ptr,
-                            current_prev_op,
-                            loc.clone(),
-                        );
-                        current_prev_op = Some(len_op);
-                        Some(len)
-                    } else {
-                        None
-                    };
-
-                    (current_value, current_prev_op) = apply_deref_projection(
-                        ctx,
-                        current_value,
-                        block_ptr,
-                        current_prev_op,
-                        loc.clone(),
-                    )?;
-                    preserved_slice_deref_mutability = None;
-                }
-                pending_downcast = None;
-            }
-
-            ProjectionElem::Field(field_idx, field_ty) => {
-                // Check if this is a field access on an enum (preceded by Downcast).
-                if let Some(variant_idx) = pending_downcast.take() {
-                    if carried_slice_tail_len.is_some() {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(
-                                "slice-tail metadata cannot cross an enum Downcast/Field projection"
-                                    .to_string()
-                            )
-                        );
-                    }
-
-                    // Enum variant field access - use MirEnumPayloadOp.
-                    (current_value, current_prev_op) = apply_enum_field_projection(
-                        ctx,
-                        current_value,
-                        &current_rust_ty,
-                        variant_idx,
-                        *field_idx,
-                        field_ty,
-                        block_ptr,
-                        current_prev_op,
-                        loc.clone(),
-                    )?;
-                } else {
-                    let tail_elem_rust_ty = match field_ty.kind() {
-                        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Slice(
-                            elem,
-                        )) => Some(elem),
-                        _ => None,
-                    };
-                    let field_is_slice_tailed_adt =
-                        types::slice_tail_element_ty(field_ty).is_some();
-
-                    if let Some(tail_elem_rust_ty) = tail_elem_rust_ty
-                        && let Some(tail_len) = carried_slice_tail_len.take()
-                    {
-                        let tail_elem_ty = types::translate_type(ctx, &tail_elem_rust_ty)?;
-
-                        // The struct model stores an unsized `[T]` tail as the
-                        // element type `T`, because the elements live inline after
-                        // the sized prefix. Address the field as `*T`, not `*[T]`.
-                        use dialect_mir::ops::MirConstructSliceOp;
-                        let tail_ptr_ty = projected_pointer_type(
-                            ctx,
-                            current_value.get_type(ctx),
-                            tail_elem_ty,
-                            /* legacy requested mutability, ignored */ false,
-                        )
-                        .expect("slice-tail field base must be a MirPtrType");
-                        let tail_addr = dialect_mir::ops::MirFieldAddrOp::build(
-                            ctx,
-                            current_value,
-                            tail_ptr_ty,
-                            *field_idx as u32,
-                        )?;
-                        tail_addr.deref_mut(ctx).set_loc(loc.clone());
-                        match current_prev_op {
-                            Some(prev) => tail_addr.insert_after(ctx, prev),
-                            None => tail_addr.insert_at_front(block_ptr, ctx),
-                        }
-                        let tail_ptr = tail_addr.deref(ctx).get_result(0);
-
-                        // Reconstruct the semantic `[T]` value from the inline tail
-                        // address plus the metadata carried from the outer fat reference,
-                        // with an intentionally Erased pointer kind: a Rust kind is
-                        // established only at the `Rvalue::Ref`/`AddressOf` boundary.
-                        // A following Index or ConstantIndex can scalarize this
-                        // MirSliceType to field 0 and reuse the existing pointer-offset
-                        // + load path.
-                        let tail_is_mutable = tail_ptr_ty
-                            .deref(ctx)
-                            .downcast_ref::<dialect_mir::types::MirPtrType>()
-                            .expect("slice-tail projection must produce a MirPtrType")
-                            .is_mutable;
-                        let tail_slice_ty = dialect_mir::types::MirSliceType::get_with_mutability(
-                            ctx,
-                            tail_elem_ty,
-                            tail_is_mutable,
-                        );
-                        let construct_tail = Operation::new(
-                            ctx,
-                            MirConstructSliceOp::get_concrete_op_info(),
-                            vec![tail_slice_ty.into()],
-                            vec![tail_ptr, tail_len],
-                            vec![],
-                            0,
-                        );
-                        construct_tail.deref_mut(ctx).set_loc(loc.clone());
-                        construct_tail.insert_after(ctx, tail_addr);
-                        current_value = construct_tail.deref(ctx).get_result(0);
-                        current_prev_op = Some(construct_tail);
-                    } else if carried_slice_tail_len.is_some() && field_is_slice_tailed_adt {
-                        // The selected field is itself an unsized struct whose final
-                        // field eventually contains the same slice tail. Such a field
-                        // cannot be loaded as an SSA aggregate. Advance only the
-                        // address and keep the metadata riding alongside it for the
-                        // next projection step.
-                        if !current_value
-                            .get_type(ctx)
-                            .deref(ctx)
-                            .is::<dialect_mir::types::MirPtrType>()
-                        {
-                            return input_err!(
-                                loc,
-                                TranslationErr::unsupported(format!(
-                                    "slice-tail metadata reached nested DST field {:?}, but the current value is not an address",
-                                    field_ty
-                                ))
-                            );
-                        }
-
-                        let field_type = types::translate_type(ctx, field_ty)?;
-                        let field_ptr_ty = projected_pointer_type(
-                            ctx,
-                            current_value.get_type(ctx),
-                            field_type,
-                            /* legacy requested mutability, ignored */ false,
-                        )
-                        .expect("nested DST field base must be a MirPtrType");
-                        let field_addr = dialect_mir::ops::MirFieldAddrOp::build(
-                            ctx,
-                            current_value,
-                            field_ptr_ty,
-                            *field_idx as u32,
-                        )?;
-                        field_addr.deref_mut(ctx).set_loc(loc.clone());
-                        match current_prev_op {
-                            Some(prev) => field_addr.insert_after(ctx, prev),
-                            None => field_addr.insert_at_front(block_ptr, ctx),
-                        }
-                        current_value = field_addr.deref(ctx).get_result(0);
-                        current_prev_op = Some(field_addr);
-                    } else {
-                        // A sized field does not inherit DST metadata. Once the
-                        // projection leaves the unsized-tail path, drop the
-                        // metadata and lower the field normally.
-                        carried_slice_tail_len = None;
-
-                        let current_is_ptr = current_value
-                            .get_type(ctx)
-                            .deref(ctx)
-                            .is::<dialect_mir::types::MirPtrType>();
-                        if current_is_ptr {
-                            // `current_value` is an ADDRESS, not an aggregate
-                            // value. This happens after dereferencing a fat
-                            // pointer: `apply_deref_projection` cannot load an
-                            // unsized pointee, so it hands back the data
-                            // pointer instead (e.g. reading
-                            // `(*iter).alive.start` through the fat
-                            // `&mut PolymorphicIter<[MaybeUninit<T>]>` inside
-                            // `core::array::IntoIter::next`, issue #138).
-                            // Compute the field's address and load the field.
-                            (current_value, current_prev_op) = apply_field_addr_and_load(
-                                ctx,
-                                current_value,
-                                *field_idx,
-                                field_ty,
-                                block_ptr,
-                                current_prev_op,
-                                loc.clone(),
-                            )?;
-                        } else {
-                            // Regular struct/tuple field access.
-                            (current_value, current_prev_op) = apply_field_projection(
-                                ctx,
-                                current_value,
-                                *field_idx,
-                                field_ty,
-                                block_ptr,
-                                current_prev_op,
-                                loc.clone(),
-                            )?;
-                        }
-                    }
-                }
-            }
-
-            ProjectionElem::Downcast(variant_idx) => {
-                if carried_slice_tail_len.is_some() {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(
-                            "slice-tail metadata reached Downcast before the unsized slice field"
-                                .to_string()
-                        )
-                    );
-                }
-                // Downcast is a no-op - it just narrows the type for the next Field access
-                // Store the variant index for use by the next Field projection
-                pending_downcast = Some(*variant_idx);
-                // Don't change current_value
-            }
-
-            ProjectionElem::Index(index_local) => {
-                if carried_slice_tail_len.is_some() {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(
-                            "slice-tail metadata reached Index before the unsized slice field"
-                                .to_string()
-                        )
-                    );
-                }
-                let index_place = mir::Place {
-                    local: *index_local,
-                    projection: vec![],
-                };
-                let (index_value, next_prev_op) = translate_place(
-                    ctx,
-                    body,
-                    &index_place,
-                    value_map,
-                    block_ptr,
-                    current_prev_op,
-                    loc.clone(),
-                )?;
-                current_prev_op = next_prev_op;
-
-                // A projected unsized slice tail is represented as a fat
-                // `MirSliceType` value. Runtime Index only needs the data
-                // pointer, so normalize it before reusing the pointer path.
-                (current_value, current_prev_op) = normalize_slice_value_to_data_ptr(
-                    ctx,
-                    current_value,
-                    block_ptr,
-                    current_prev_op,
-                    loc.clone(),
-                );
-
-                // Determine indexable kind upfront so we drop the immutable borrow
-                // before creating operations (which need &mut ctx).
-                enum IndexableKind {
-                    Array {
-                        element_ty: TypeHandle,
-                    },
-                    Ptr {
-                        element_ty: TypeHandle,
-                        ptr_ty: TypeHandle,
-                    },
-                }
-
-                let cur_ty = current_value.get_type(ctx);
-                let kind = {
-                    let cur_ty_ref = cur_ty.deref(ctx);
-                    if let Some(arr_ty) =
-                        cur_ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>()
-                    {
-                        Ok(IndexableKind::Array {
-                            element_ty: arr_ty.element_type(),
-                        })
-                    } else if let Some(ptr_ty) =
-                        cur_ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>()
-                    {
-                        Ok(IndexableKind::Ptr {
-                            element_ty: ptr_ty.pointee,
-                            ptr_ty: cur_ty,
-                        })
-                    } else {
-                        let ty_dbg = format!("{:?}", cur_ty_ref);
-                        Err(ty_dbg)
-                    }
-                };
-
-                match kind {
-                    Ok(IndexableKind::Array { element_ty }) => {
-                        use dialect_mir::ops::MirExtractArrayElementOp;
-                        let op = Operation::new(
-                            ctx,
-                            MirExtractArrayElementOp::get_concrete_op_info(),
-                            vec![element_ty],
-                            vec![current_value, index_value],
-                            vec![],
-                            0,
-                        );
-                        op.deref_mut(ctx).set_loc(loc.clone());
-
-                        if let Some(prev) = current_prev_op {
-                            op.insert_after(ctx, prev);
-                        } else {
-                            op.insert_at_front(block_ptr, ctx);
-                        }
-
-                        current_value = op.deref(ctx).get_result(0);
-                        current_prev_op = Some(op);
-                    }
-                    Ok(IndexableKind::Ptr { element_ty, ptr_ty }) => {
-                        let offset_op = Operation::new(
-                            ctx,
-                            MirPtrOffsetOp::get_concrete_op_info(),
-                            vec![ptr_ty],
-                            vec![current_value, index_value],
-                            vec![],
-                            0,
-                        );
-                        offset_op.deref_mut(ctx).set_loc(loc.clone());
-                        if let Some(prev) = current_prev_op {
-                            offset_op.insert_after(ctx, prev);
-                        } else {
-                            offset_op.insert_at_front(block_ptr, ctx);
-                        }
-                        current_prev_op = Some(offset_op);
-                        let offset_ptr = offset_op.deref(ctx).get_result(0);
-
-                        let load_op = Operation::new(
-                            ctx,
-                            MirLoadOp::get_concrete_op_info(),
-                            vec![element_ty],
-                            vec![offset_ptr],
-                            vec![],
-                            0,
-                        );
-                        load_op.deref_mut(ctx).set_loc(loc.clone());
-                        let load = MirLoadOp::new(load_op);
-                        if let Some(prev) = current_prev_op {
-                            load.get_operation().insert_after(ctx, prev);
-                        } else {
-                            load.get_operation().insert_at_front(block_ptr, ctx);
-                        }
-
-                        current_value = load.get_operation().deref(ctx).get_result(0);
-                        current_prev_op = Some(load.get_operation());
-                    }
-                    Err(ty_dbg) => {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "Index projection on unsupported type.\n\
-                                 \n  pliron type: {}\n\
-                                 \n  display    : {}\n\
-                                 \n\
-                                 \nIndex handles MirArrayType (extract_array_element) and MirPtrType\n\
-                                 (pointer offset + load, e.g. after Deref on a slice). The type above\n\
-                                 matched neither. A new handler may need to be added.",
-                                ty_dbg,
-                                cur_ty.disp(ctx)
-                            ))
-                        );
-                    }
-                }
-                pending_downcast = None;
-            }
-
-            ProjectionElem::ConstantIndex {
-                offset,
-                min_length: _,
-                from_end,
-            } => {
-                if carried_slice_tail_len.is_some() {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(
-                            "slice-tail metadata reached ConstantIndex before the unsized slice field"
-                                .to_string()
-                        )
-                    );
-                }
-                if *from_end {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(
-                            "ConstantIndex with from_end=true not yet supported"
-                        )
-                    );
-                }
-                let index = *offset as usize;
-
-                // A projected unsized slice tail is represented as a fat
-                // `MirSliceType` value. ConstantIndex only needs the data
-                // pointer, so normalize it before reusing the pointer path.
-                (current_value, current_prev_op) = normalize_slice_value_to_data_ptr(
-                    ctx,
-                    current_value,
-                    block_ptr,
-                    current_prev_op,
-                    loc.clone(),
-                );
-
-                // Determine indexable kind upfront so we drop the immutable borrow
-                // before creating operations (which need &mut ctx).
-                enum ConstIndexKind {
-                    Array {
-                        element_ty: TypeHandle,
-                    },
-                    Ptr {
-                        element_ty: TypeHandle,
-                        ptr_ty: TypeHandle,
-                    },
-                }
-
-                let cur_ty = current_value.get_type(ctx);
-                let kind = {
-                    let cur_ty_ref = cur_ty.deref(ctx);
-                    if let Some(arr_ty) =
-                        cur_ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>()
-                    {
-                        Ok(ConstIndexKind::Array {
-                            element_ty: arr_ty.element_type(),
-                        })
-                    } else if let Some(ptr_ty) =
-                        cur_ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>()
-                    {
-                        Ok(ConstIndexKind::Ptr {
-                            element_ty: ptr_ty.pointee,
-                            ptr_ty: cur_ty,
-                        })
-                    } else {
-                        let ty_dbg = format!("{:?}", cur_ty_ref);
-                        Err(ty_dbg)
-                    }
-                };
-
-                match kind {
-                    Ok(ConstIndexKind::Array { element_ty }) => {
-                        let op = Operation::new(
-                            ctx,
-                            MirExtractFieldOp::get_concrete_op_info(),
-                            vec![element_ty],
-                            vec![current_value],
-                            vec![],
-                            0,
-                        );
-                        op.deref_mut(ctx).set_loc(loc.clone());
-                        let extract_op = MirExtractFieldOp::new(op);
-                        extract_op.set_attr_index(
-                            ctx,
-                            dialect_mir::attributes::FieldIndexAttr(index as u32),
-                        );
-
-                        if let Some(prev) = current_prev_op {
-                            extract_op.get_operation().insert_after(ctx, prev);
-                        } else {
-                            extract_op.get_operation().insert_at_front(block_ptr, ctx);
-                        }
-
-                        current_value = extract_op.get_operation().deref(ctx).get_result(0);
-                        current_prev_op = Some(extract_op.get_operation());
-                    }
-                    Ok(ConstIndexKind::Ptr { element_ty, ptr_ty }) => {
-                        // Create constant index value
-                        let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-                        let apint = APInt::from_u32(index as u32, NonZeroUsize::new(32).unwrap());
-                        let index_attr =
-                            pliron::builtin::attributes::IntegerAttr::new(i32_ty, apint);
-                        use dialect_mir::ops::MirConstantOp;
-                        let const_op = Operation::new(
-                            ctx,
-                            MirConstantOp::get_concrete_op_info(),
-                            vec![i32_ty.into()],
-                            vec![],
-                            vec![],
-                            0,
-                        );
-                        const_op.deref_mut(ctx).set_loc(loc.clone());
-                        let const_mir = MirConstantOp::new(const_op);
-                        const_mir.set_attr_value(ctx, index_attr);
-                        if let Some(prev) = current_prev_op {
-                            const_mir.get_operation().insert_after(ctx, prev);
-                        } else {
-                            const_mir.get_operation().insert_at_front(block_ptr, ctx);
-                        }
-                        current_prev_op = Some(const_mir.get_operation());
-                        let index_value = const_mir.get_operation().deref(ctx).get_result(0);
-
-                        // Pointer offset
-                        let offset_op = Operation::new(
-                            ctx,
-                            MirPtrOffsetOp::get_concrete_op_info(),
-                            vec![ptr_ty],
-                            vec![current_value, index_value],
-                            vec![],
-                            0,
-                        );
-                        offset_op.deref_mut(ctx).set_loc(loc.clone());
-                        if let Some(prev) = current_prev_op {
-                            offset_op.insert_after(ctx, prev);
-                        } else {
-                            offset_op.insert_at_front(block_ptr, ctx);
-                        }
-                        current_prev_op = Some(offset_op);
-                        let offset_ptr = offset_op.deref(ctx).get_result(0);
-
-                        // Load element
-                        let load_op = Operation::new(
-                            ctx,
-                            MirLoadOp::get_concrete_op_info(),
-                            vec![element_ty],
-                            vec![offset_ptr],
-                            vec![],
-                            0,
-                        );
-                        load_op.deref_mut(ctx).set_loc(loc.clone());
-                        let load = MirLoadOp::new(load_op);
-                        if let Some(prev) = current_prev_op {
-                            load.get_operation().insert_after(ctx, prev);
-                        } else {
-                            load.get_operation().insert_at_front(block_ptr, ctx);
-                        }
-
-                        current_value = load.get_operation().deref(ctx).get_result(0);
-                        current_prev_op = Some(load.get_operation());
-                    }
-                    Err(ty_dbg) => {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "ConstantIndex projection on unsupported type.\n\
-                                 \n  pliron type: {}\n\
-                                 \n  display    : {}\n\
-                                 \n  index      : {}\n\
-                                 \n\
-                                 \nConstantIndex handles MirArrayType (extractvalue) and MirPtrType\n\
-                                 (pointer offset + load, e.g. after Deref on a slice). The type above\n\
-                                 matched neither. A new handler may need to be added.",
-                                ty_dbg,
-                                cur_ty.disp(ctx),
-                                index
-                            ))
-                        );
-                    }
-                }
-                pending_downcast = None;
-            }
-
-            ProjectionElem::Subslice { from, to, from_end } => {
-                if carried_slice_tail_len.is_some() {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(
-                            "slice-tail metadata reached Subslice before the unsized slice field"
-                                .to_string()
-                        )
-                    );
-                }
-                if *from_end {
-                    let Some(is_mutable) = preserved_slice_deref_mutability.take() else {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(
-                                "slice Subslice reached iterative lowering without preserved fat-pointer metadata"
-                                    .to_string()
-                            )
-                        );
-                    };
-                    let element_ty = {
-                        let current_ty = current_value.get_type(ctx);
-                        let current_ty = current_ty.deref(ctx);
-                        let Some(slice_ty) =
-                            current_ty.downcast_ref::<dialect_mir::types::MirSliceType>()
-                        else {
-                            return input_err!(
-                                loc,
-                                TranslationErr::unsupported(
-                                    "slice Subslice preserved value is not MirSliceType"
-                                        .to_string()
-                                )
-                            );
-                        };
-                        slice_ty.element_type()
-                    };
-
-                    let (subslice, last_op) = emit_slice_subslice_value(
-                        ctx,
-                        current_value,
-                        element_ty,
-                        is_mutable,
-                        *from,
-                        *to,
-                        block_ptr,
-                        current_prev_op,
-                        loc.clone(),
-                    )?;
-                    current_value = subslice;
-                    current_prev_op = Some(last_op);
-
-                    // A subsequent element projection needs only the adjusted
-                    // data pointer. Keep a terminal Subslice as a fat value so
-                    // PtrMetadata/borrow users can observe the rebuilt length.
-                    if matches!(
-                        place.projection.get(proj_idx + 1),
-                        Some(ProjectionElem::Index(_))
-                            | Some(ProjectionElem::ConstantIndex {
-                                from_end: false,
-                                ..
-                            })
-                    ) {
-                        let data_ptr_ty: TypeHandle = dialect_mir::types::MirPtrType::get_generic(
-                            ctx, element_ty, is_mutable,
-                        )
-                        .into();
-                        let extract_ptr = Operation::new(
-                            ctx,
-                            MirExtractFieldOp::get_concrete_op_info(),
-                            vec![data_ptr_ty],
-                            vec![current_value],
-                            vec![],
-                            0,
-                        );
-                        extract_ptr.deref_mut(ctx).set_loc(loc.clone());
-                        MirExtractFieldOp::new(extract_ptr)
-                            .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
-                        extract_ptr.insert_after(ctx, last_op);
-                        current_value = extract_ptr.deref(ctx).get_result(0);
-                        current_prev_op = Some(extract_ptr);
-                    }
-                } else {
-                    (current_value, current_prev_op) = emit_array_subslice_value(
-                        ctx,
-                        current_value,
-                        *from,
-                        *to,
-                        block_ptr,
-                        current_prev_op,
-                        loc.clone(),
-                    )?;
-                    preserved_slice_deref_mutability = None;
-                }
-                pending_downcast = None;
-            }
-
-            // Unsupported projection types
-            other => {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Projection element {:?} not yet implemented in iterative mode",
-                        other
-                    ))
-                );
-            }
-        }
-
-        // Advance the running Rust type with rustc_public's own projection
-        // typing (single source of truth; see the comment on
-        // `current_rust_ty` above). For well-formed MIR this never fails;
-        // if it does, surface the projection element and the type it was
-        // applied to so the bail-out is actionable.
-        current_rust_ty = projection.ty(current_rust_ty).map_err(|e| {
-            input_error!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Failed to type projection {:?} applied to {:?}: {:?}",
-                    projection, current_rust_ty, e
-                ))
-            )
-        })?;
-    }
-
-    if carried_slice_tail_len.is_some() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(
-                "place projection ended on a slice-tailed DST before its metadata was attached to the slice field"
-                    .to_string()
-            )
-        );
-    }
-
-    Ok((current_value, current_prev_op))
-}
-
-/// Translate a pointer-to-array constant to MIR operations.
-///
-/// Handles both byte string literals (`&[u8; N]`, e.g. `b"hello\0"`) and typed
-/// array constants (`&[f64; 3]`, `&[u32; 4]`, etc.). The function:
-/// 1. Extracts raw bytes from the constant's allocation
-/// 2. Groups bytes into element-sized chunks based on the array element type
-/// 3. Creates typed constants for each element (u8, u32, f32, f64, etc.)
-/// 4. Returns a pointer to the constructed array
-fn translate_ptr_to_array_constant(
-    ctx: &mut Context,
-    constant: &mir::ConstOperand,
-    const_ty_ptr: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    // Extract array type from the pointer type. A pointer-to-array constant can
-    // outlive this function, so lowering it as `array value + mir.ref` would
-    // return a pointer to function-local stack storage. Materialize it as an
-    // immutable device global instead.
-    let array_ty = {
-        let ty_obj = const_ty_ptr.deref(ctx);
-        let ptr_ty = ty_obj
-            .downcast_ref::<dialect_mir::types::MirPtrType>()
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(
-                    "translate_ptr_to_array_constant: expected pointer type"
-                ))
-            })?;
-
-        let arr_ty_obj = ptr_ty.pointee.deref(ctx);
-        if arr_ty_obj
-            .downcast_ref::<dialect_mir::types::MirArrayType>()
-            .is_none()
-        {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(
-                    "translate_ptr_to_array_constant: expected array pointee"
-                )
-            );
-        }
-        ptr_ty.pointee
-    };
-
-    let rust_array_ty = match constant.const_.ty().kind() {
-        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::RawPtr(pointee, _))
-        | rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Ref(_, pointee, _)) => {
-            pointee
-        }
-        _ => constant.const_.ty(),
-    };
-    let expected_size = rust_type_layout_size(rust_array_ty, loc.clone())?;
-    if expected_size != 0
-        && let Some(union_name) = stored_type_union_name(rust_array_ty, &mut Vec::new())
-    {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "promoted array initializer contains union `{union_name}`; initialized union storage is not yet supported"
-            ))
-        );
-    }
-
-    validate_ptr_to_array_constant_type(ctx, array_ty, loc.clone())?;
-    // The same byte-size agreement the bare-array promotion demands: the
-    // global's declared type is the converted dialect type while its
-    // initializer bytes come from rustc's evaluated allocation, so the two
-    // layouts must agree before the byte image is trusted. Unlike that path
-    // there is no element-wise lowering to fall back to here, so disagreement
-    // is an error rather than a bail-out. Zero size stays exempt because
-    // `dialect_stored_size` cannot tell a genuine zero from an unrecorded
-    // layout, and an empty initializer has no bytes to misplace.
-    let stored_size = dialect_stored_size(ctx, array_ty);
-    if expected_size > 0 && stored_size != Some(expected_size as u64) {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "translate_ptr_to_array_constant: converted array storage size {stored_size:?} disagrees with rustc layout size {expected_size}"
-            ))
-        );
-    }
-    let initializer = promoted_array_initializer(constant, expected_size, "array", loc.clone())?;
-    let promoted_anchor = materialize_promoted_initializer_targets(
-        ctx,
-        &initializer.relocations,
-        block_ptr,
-        prev_op,
-        loc.clone(),
-    )?;
-
-    let global_alloc = emit_promoted_immutable_global(
-        ctx,
-        array_ty,
-        &initializer,
-        block_ptr,
-        promoted_anchor,
-        loc.clone(),
-    );
-
-    let global_ptr = global_alloc.get_operation().deref(ctx).get_result(0);
-    let (ptr_val, last_op) = cast_to_declared_rust_pointer_type_if_needed(
-        ctx,
-        global_ptr,
-        const_ty_ptr,
-        block_ptr,
-        Some(global_alloc.get_operation()),
-        loc,
-        MirPointerKindAuthorityAttr::StaticAddress,
-    );
-    Ok((ptr_val, last_op))
-}
-
-/// Materialize an evaluated constant allocation as an immutable device global.
-///
-/// Deduplicated by type, bytes, allocation alignment, and relocation identity.
-/// Pointer placeholder bytes alone are not enough: two constants can have
-/// identical byte images and addends while their rustc provenance targets
-/// different statics or their backing allocations require different alignment.
-///
-/// The global is marked immutable, which is what makes it useful beyond simply
-/// having an address: the exporter writes LLVM `constant`, so `opt` may treat
-/// reads of it as invariant. Pointer slots remain symbolic relocation metadata
-/// all the way to the exporter instead of being reconstructed from placeholder
-/// integer bytes.
-pub(crate) fn emit_promoted_immutable_global(
-    ctx: &mut Context,
-    value_ty: TypeHandle,
-    initializer: &GlobalInitializerData,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> MirGlobalAllocOp {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::attributes::{StringAttr, TypeAttr};
-
-    let initializer_hex = bytes_to_hex(&initializer.bytes);
-    let global_key = promoted_constant_dedup_key(ctx, value_ty, initializer);
-    let global_ptr_ty = MirPtrType::get_global(ctx, value_ty, false);
-    let validation_ty = promoted_global_validation_type(ctx, value_ty, initializer.bytes.len());
-    let global_op = Operation::new(
-        ctx,
-        MirGlobalAllocOp::get_concrete_op_info(),
-        vec![global_ptr_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    global_op.deref_mut(ctx).set_loc(loc);
-
-    let global_alloc = MirGlobalAllocOp::new(global_op);
-    global_alloc.set_attr_global_type(ctx, TypeAttr::new(validation_ty));
-    global_alloc.set_attr_global_key(ctx, StringAttr::new(global_key));
-    set_global_initializer_hex_attr(ctx, global_alloc.get_operation(), &initializer_hex);
-    if !initializer.relocations.is_empty() {
-        let encoded = encode_global_initializer_relocations(&initializer.relocations);
-        set_global_initializer_relocations_attr(ctx, global_alloc.get_operation(), &encoded);
-    }
-    if initializer.alignment > 0 {
-        global_alloc.set_alignment_value(ctx, initializer.alignment);
-    }
-    global_alloc.mark_immutable(ctx);
-
-    if let Some(prev) = prev_op {
-        global_alloc.get_operation().insert_after(ctx, prev);
-    } else {
-        global_alloc.get_operation().insert_at_front(block_ptr, ctx);
-    }
-
-    global_alloc
-}
-
-/// Ensure every Rust static referenced by a promoted initializer exists as a
-/// MIR global before the promoted table is emitted.
-///
-/// Without this step the old element-wise pointer decoder used to materialize
-/// the targets as a side effect. Once the entire table stays in one global, the
-/// relocation metadata is the only reference and the targets must be made
-/// explicit here.
-fn materialize_promoted_initializer_targets(
-    ctx: &mut Context,
-    relocations: &[GlobalInitializerRelocation],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<Option<Ptr<Operation>>> {
-    let mut state = StaticGlobalMaterializationState {
-        globals: std::collections::HashMap::new(),
-        last_op: prev_op,
-    };
-    ensure_initializer_relocation_targets(
-        ctx,
-        relocations,
-        "promoted constant table",
-        block_ptr,
-        loc,
-        &mut state,
-    )?;
-    Ok(state.last_op)
-}
-
-/// Whether an array's elements are cheap enough to be worth promoting the whole
-/// array to an immutable global and copying it in.
-///
-/// This is the element gate for the immutable-global promotion optimization
-/// used by bare array values ([`translate_array_constant_into_alloca`]) and for
-/// the pointer-to-array form ([`translate_ptr_to_array_constant`], via
-/// [`validate_ptr_to_array_constant_type`]). It is deliberately narrower than
-/// bare-array value admission: an unpromotable bare value can fall back to
-/// element-wise materialization, while a pointer-to-array constant cannot.
-///
-/// Admits primitive scalars, thin pointers, enums carrying no payload, tuples
-/// and structs whose every field is itself admissible, and nested arrays of any
-/// of those. Pointer admission is still relocation-gated later: only provenance
-/// that can be represented by [`GlobalInitializerRelocation`] reaches promotion.
-/// `ty` is
-/// the array type, and nesting is walked so an unsupported leaf cannot hide
-/// inside it. A zero-length array passes for any element type: its initializer
-/// is empty and nothing can ever be read through it, which is what admits a
-/// promoted empty-slice constant such as `&[]` (rustc promotes it to `&[T; 0]`)
-/// regardless of `T`.
-///
-/// Tuples are admitted when every field is itself promotable. That only became
-/// worth doing once a tuple field read stopped going through a copy of the whole
-/// array: while that copy stood it dominated, so promoting such a table changed
-/// nothing measurable and merely added a global to the module image. With the
-/// read addressed in place, the promotion is what removes the depot — the two
-/// only pay off together.
-///
-/// Structs are admitted recursively, including thin pointer fields. Unions,
-/// fat-pointer storage, payload-carrying enums, and any other unsupported leaf
-/// remain outside this path. A payload-carrying enum stays out because reading
-/// one back still
-/// round-trips the payload through memory: the address walker resolves enum
-/// payload fields for writes, not for reads.
-///
-/// A struct's recorded rustc layout must be byte-faithful in the LLVM storage
-/// selected by lowering. Ordinary layouts use the natural struct path; layouts
-/// such as `repr(C, packed)` may use the packed struct path when the recorded
-/// field ranges are non-overlapping and the packed representation can reproduce
-/// every offset and the final size exactly. Layouts that neither representation
-/// can express remain on the fallback path. See
-/// [`struct_layout_matches_llvm_storage`].
-fn promotable_array_element(ctx: &Context, ty: TypeHandle) -> bool {
-    use dialect_mir::types::{MirArrayType, MirEnumType, MirStructType, MirTupleType};
-
-    let obj = ty.deref(ctx);
-    if let Some(array) = obj.downcast_ref::<MirArrayType>() {
-        // No element values exist, so the element restriction is vacuous.
-        if array.size() == 0 {
-            return true;
-        }
-        return promotable_array_element(ctx, array.element_type());
-    }
-    if let Some(tuple) = obj.downcast_ref::<MirTupleType>() {
-        let fields = tuple.get_types().to_vec();
-        drop(obj);
-        return fields
-            .into_iter()
-            .all(|field| promotable_array_element(ctx, field));
-    }
-    if let Some(structure) = obj.downcast_ref::<MirStructType>() {
-        let fields = structure.field_types().to_vec();
-        let field_offsets = structure.field_offsets().to_vec();
-        let mem_to_decl = structure.mem_to_decl.clone();
-        let total_size = structure.total_size;
-        let has_zero_byte_over_alignment = total_size == 0 && structure.abi_align > 1;
-        drop(obj);
-
-        // A zero-byte `repr(align(N))` struct can raise the alignment of an
-        // enclosing tuple without contributing storage to its LLVM shape. Keep
-        // that established alignment-sensitive path out of immutable-global
-        // promotion; ordinary stored structs still recurse through their fields.
-        if has_zero_byte_over_alignment {
-            return false;
-        }
-
-        // Immutable promotion copies rustc's evaluated byte image into the
-        // exact storage type selected by lowering. Accept either the ordinary
-        // natural representation or the exact packed representation introduced
-        // for layout-divergent structs. Overlapping or otherwise unrepresentable
-        // field maps still fail closed.
-        if !struct_layout_matches_llvm_storage(
-            ctx,
-            &fields,
-            &field_offsets,
-            &mem_to_decl,
-            total_size,
-        ) {
-            return false;
-        }
-
-        return fields
-            .into_iter()
-            .all(|field| promotable_array_element(ctx, field));
-    }
-    if let Some(enumeration) = obj.downcast_ref::<MirEnumType>() {
-        // No variant carries a field, so the whole element *is* its discriminant
-        // and reading one is a single load.
-        return enumeration.total_size() > 0
-            && enumeration
-                .variant_field_counts
-                .iter()
-                .all(|&count| count == 0);
-    }
-    obj.is::<dialect_mir::types::MirPtrType>()
-        || obj.is::<IntegerType>()
-        || obj.is::<MirFP16Type>()
-        || obj.is::<FP32Type>()
-        || obj.is::<FP64Type>()
-}
-
-/// Whether rustc's recorded struct layout is byte-faithful in one of the LLVM
-/// struct representations available to lowering.
-///
-/// The natural representation remains preferred. When it cannot reproduce the
-/// recorded offsets, lowering can use a packed LLVM struct with explicit byte
-/// padding between stored fields. Such a representation is exact iff the stored
-/// fields are non-overlapping in rustc memory order and every field range plus
-/// the tail fits inside `total_size`. Alignment is intentionally not part of the
-/// packed check: LLVM packed structs permit an otherwise naturally aligned field
-/// at an unaligned byte offset, while the enclosing allocation keeps rustc's ABI
-/// alignment separately.
-///
-/// Unknown layouts retain the previous optimistic answer here; the promotion
-/// path's stored-size agreement check rejects a non-empty initializer whose
-/// concrete size cannot be established.
-fn struct_layout_matches_llvm_storage(
-    ctx: &Context,
-    field_types: &[TypeHandle],
-    field_offsets: &[u64],
-    mem_to_decl: &[usize],
-    total_size: u64,
-) -> bool {
-    if field_offsets.is_empty() || total_size == 0 {
-        return true;
-    }
-    if field_offsets.len() != field_types.len() {
-        return false;
-    }
-
-    if struct_layout_matches_llvm_natural(ctx, field_types, field_offsets, mem_to_decl, total_size)
-    {
-        return true;
-    }
-
-    // Empty `mem_to_decl` means identity (declaration order = memory order).
-    let identity: Vec<usize>;
-    let memory_order: &[usize] = if mem_to_decl.is_empty() {
-        identity = (0..field_types.len()).collect();
-        &identity
-    } else {
-        mem_to_decl
-    };
-
-    let mut end = 0u64;
-    for &decl_idx in memory_order {
-        if decl_idx >= field_types.len() {
-            return false;
-        }
-
-        let Some((size, _)) = llvm_natural_size_align(ctx, field_types[decl_idx]) else {
-            return false;
-        };
-        if size == 0 {
-            continue;
-        }
-
-        let offset = field_offsets[decl_idx];
-        if offset < end {
-            return false;
-        }
-        let Some(field_end) = offset.checked_add(size) else {
-            return false;
-        };
-        if field_end > total_size {
-            return false;
-        }
-        end = field_end;
-    }
-
-    end <= total_size
-}
-
-/// Type used by initialized-global validation for a promoted constant.
-///
-/// `mir.global_alloc` keeps the semantic result pointer separately from its
-/// `global_type` storage metadata. Pointer-free initializers are emitted as an
-/// exact `[N x i8]` allocation by lowering. For a semantic type that contains a
-/// byte-faithful packed struct, use that physical byte view for global-layout
-/// validation while retaining the semantic result pointer. Later typed GEPs and
-/// loads still use `value_ty`, whose packed representation is selected by #941.
-/// Ordinary layouts keep their semantic validation unchanged.
-fn promoted_global_validation_type(
-    ctx: &mut Context,
-    value_ty: TypeHandle,
-    byte_len: usize,
-) -> TypeHandle {
-    use dialect_mir::types::MirArrayType;
-
-    // A zero-byte allocation has no field bytes whose physical placement
-    // needs the packed-storage fallback. Retain the semantic type so the
-    // immutable-global root remains an exact authority for rustc-promoted
-    // `&mut [T; 0]`; lowering still checks its zero size and required
-    // alignment before emitting `[0 x i8]` storage.
-    if byte_len == 0 {
-        return value_ty;
-    }
-
-    if !type_contains_packed_struct_storage(ctx, value_ty) {
-        return value_ty;
-    }
-
-    let byte_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Unsigned).into();
-    MirArrayType::get(ctx, byte_ty, byte_len as u64).into()
-}
-
-/// Whether `ty` contains a struct whose exact LLVM storage must be packed.
-fn type_contains_packed_struct_storage(ctx: &Context, ty: TypeHandle) -> bool {
-    use dialect_mir::types::{MirArrayType, MirStructType, MirTupleType};
-
-    let obj = ty.deref(ctx);
-    if let Some(array) = obj.downcast_ref::<MirArrayType>() {
-        let element_ty = array.element_type();
-        drop(obj);
-        return type_contains_packed_struct_storage(ctx, element_ty);
-    }
-    if let Some(tuple) = obj.downcast_ref::<MirTupleType>() {
-        let fields = tuple.get_types().to_vec();
-        drop(obj);
-        return fields
-            .into_iter()
-            .any(|field| type_contains_packed_struct_storage(ctx, field));
-    }
-    if let Some(structure) = obj.downcast_ref::<MirStructType>() {
-        let fields = structure.field_types().to_vec();
-        let field_offsets = structure.field_offsets().to_vec();
-        let mem_to_decl = structure.mem_to_decl.clone();
-        let total_size = structure.total_size;
-        drop(obj);
-
-        let uses_packed_storage = !struct_layout_matches_llvm_natural(
-            ctx,
-            &fields,
-            &field_offsets,
-            &mem_to_decl,
-            total_size,
-        ) && struct_layout_matches_llvm_storage(
-            ctx,
-            &fields,
-            &field_offsets,
-            &mem_to_decl,
-            total_size,
-        );
-        return uses_packed_storage
-            || fields
-                .into_iter()
-                .any(|field| type_contains_packed_struct_storage(ctx, field));
-    }
-
-    false
-}
-
-/// Whether rustc's recorded struct layout is one the lowering's non-packed
-/// LLVM struct actually reproduces at the byte level.
-///
-/// The lowering places fields at their recorded offsets by inserting explicit
-/// `[N x i8]` padding slots, which can only ADD bytes: a field can never land
-/// below its natural LLVM alignment, and LLVM still rounds the struct's size
-/// up to its natural alignment. So the built type agrees with rustc's byte
-/// image exactly when every stored field's offset is naturally aligned and
-/// non-overlapping in memory order, and `total_size` is a multiple of the
-/// struct's natural alignment. `repr(packed)` breaks the former (a `u32` at
-/// offset 1) and usually the latter (a 5-byte total), and either divergence
-/// makes a byte-image copy land fields at the wrong bytes.
-///
-/// A struct with no recorded layout (`field_offsets` empty or `total_size`
-/// zero) answers `true`: the lowering builds no padded layout to diverge
-/// from, and the promotion path's stored-size agreement check already fails
-/// closed on the unknown size. Any field whose natural size or alignment
-/// cannot be established answers `false`: no verdict means no promotion.
-fn struct_layout_matches_llvm_natural(
-    ctx: &Context,
-    field_types: &[TypeHandle],
-    field_offsets: &[u64],
-    mem_to_decl: &[usize],
-    total_size: u64,
-) -> bool {
-    if field_offsets.is_empty() || total_size == 0 {
-        return true;
-    }
-    if field_offsets.len() != field_types.len() {
-        return false;
-    }
-    // Empty `mem_to_decl` means identity (declaration order = memory order).
-    let identity: Vec<usize>;
-    let memory_order: &[usize] = if mem_to_decl.is_empty() {
-        identity = (0..field_types.len()).collect();
-        &identity
-    } else {
-        mem_to_decl
-    };
-
-    let mut end: u64 = 0;
-    let mut max_align: u64 = 1;
-    for &decl_idx in memory_order {
-        if decl_idx >= field_types.len() {
-            return false;
-        }
-        let Some((size, align)) = llvm_natural_size_align(ctx, field_types[decl_idx]) else {
-            return false;
-        };
-        // Zero-sized fields are stripped from the LLVM struct: no slot, no
-        // bytes, no alignment contribution (over-aligned ZSTs are refused
-        // before this walk runs).
-        if size == 0 {
-            continue;
-        }
-        let offset = field_offsets[decl_idx];
-        if !offset.is_multiple_of(align) || offset < end {
-            return false;
-        }
-        end = offset + size;
-        max_align = max_align.max(align);
-    }
-    total_size >= end && total_size.is_multiple_of(max_align)
-}
-
-/// Natural size and alignment of the LLVM storage a dialect type converts to,
-/// or `None` when the walk cannot establish them.
-///
-/// "Natural" means what LLVM's datalayout assigns the converted type with no
-/// packing: leaves are their own width and self-aligned, arrays inherit their
-/// element's alignment, and aggregates align to their most-aligned stored
-/// field because the padding slots between fields are `[N x i8]` with
-/// alignment one. Aggregates answer with rustc's `total_size` for their size;
-/// that matches the built LLVM type only when their own layout is natural,
-/// which [`struct_layout_matches_llvm_storage`] validates recursively (via
-/// [`promotable_array_element`]) before the answer is trusted. A field-less
-/// enum stores only its discriminant, so it aligns as that integer does.
-fn llvm_natural_size_align(ctx: &Context, ty: TypeHandle) -> Option<(u64, u64)> {
-    use dialect_mir::types::{MirArrayType, MirEnumType, MirPtrType, MirStructType, MirTupleType};
-
-    let obj = ty.deref(ctx);
-    if let Some(array) = obj.downcast_ref::<MirArrayType>() {
-        let element_ty = array.element_type();
-        let count = array.size();
-        drop(obj);
-        let (element_size, element_align) = llvm_natural_size_align(ctx, element_ty)?;
-        return Some((element_size.checked_mul(count)?, element_align));
-    }
-    if let Some(tuple) = obj.downcast_ref::<MirTupleType>() {
-        let fields = tuple.get_types().to_vec();
-        let total_size = tuple.total_size();
-        drop(obj);
-        let align = aggregate_natural_align(ctx, &fields)?;
-        return Some((total_size, align));
-    }
-    if let Some(structure) = obj.downcast_ref::<MirStructType>() {
-        let fields = structure.field_types().to_vec();
-        let total_size = structure.total_size;
-        drop(obj);
-        let align = aggregate_natural_align(ctx, &fields)?;
-        return Some((total_size, align));
-    }
-    if let Some(enumeration) = obj.downcast_ref::<MirEnumType>() {
-        let discriminant_ty = enumeration.discriminant_ty;
-        let total_size = enumeration.total_size();
-        drop(obj);
-        let (_, align) = llvm_natural_size_align(ctx, discriminant_ty)?;
-        return Some((total_size, align));
-    }
-    let size = if obj.is::<MirPtrType>() {
-        // cuda-oxide lowers device code for 64-bit NVPTX. Keep this helper
-        // independent of rustc's session TLS so it remains unit-testable.
-        8
-    } else if let Some(integer) = obj.downcast_ref::<IntegerType>() {
-        // `bool` arrives as `i1` and occupies a byte.
-        u64::from(integer.width().div_ceil(8)).max(1)
-    } else if obj.is::<MirFP16Type>() {
-        2
-    } else if obj.is::<FP32Type>() {
-        4
-    } else if obj.is::<FP64Type>() {
-        8
-    } else {
-        return None;
-    };
-    // Every scalar Rust hands this path is self-aligned at a power-of-two
-    // width; anything else has no natural alignment to report.
-    size.is_power_of_two().then_some((size, size))
-}
-
-/// Natural alignment of the LLVM struct built for an aggregate's fields:
-/// the maximum over the stored (non-zero-sized) fields, one when nothing is
-/// stored. `None` when some field's alignment cannot be established.
-fn aggregate_natural_align(ctx: &Context, fields: &[TypeHandle]) -> Option<u64> {
-    let mut align: u64 = 1;
-    for &field in fields {
-        let (field_size, field_align) = llvm_natural_size_align(ctx, field)?;
-        if field_size > 0 {
-            align = align.max(field_align);
-        }
-    }
-    Some(align)
-}
-
-/// Bytes a dialect type occupies, as the converted LLVM storage will lay it out,
-/// or `None` when that cannot be established from the type alone.
-///
-/// Aggregates answer with the `total_size` rustc gave them, which is exactly what
-/// the storage builders reproduce: they pad to reach each field's recorded offset
-/// and pad the tail to reach `total_size`. Leaves answer with their own width, and
-/// `i1` counts as the one byte Rust gives a `bool` rather than an eighth of one.
-///
-/// A zero answer is reported as `None`: the dialect uses `total_size() == 0` both
-/// for a genuine zero-sized type and for a size it does not know, and only the
-/// caller's own size comparison could tell them apart.
-fn dialect_stored_size(ctx: &Context, ty: TypeHandle) -> Option<u64> {
-    use dialect_mir::types::{MirArrayType, MirEnumType, MirPtrType, MirStructType, MirTupleType};
-
-    let obj = ty.deref(ctx);
-    let size = if let Some(array) = obj.downcast_ref::<MirArrayType>() {
-        let element = dialect_stored_size(ctx, array.element_type())?;
-        element.checked_mul(array.size())?
-    } else if let Some(tuple) = obj.downcast_ref::<MirTupleType>() {
-        tuple.total_size()
-    } else if let Some(structure) = obj.downcast_ref::<MirStructType>() {
-        structure.total_size()
-    } else if let Some(enumeration) = obj.downcast_ref::<MirEnumType>() {
-        enumeration.total_size()
-    } else if obj.is::<MirPtrType>() {
-        // cuda-oxide lowers device code for 64-bit NVPTX. Keep this helper
-        // independent of rustc's session TLS so it remains unit-testable.
-        8
-    } else if let Some(integer) = obj.downcast_ref::<IntegerType>() {
-        // `bool` arrives as `i1` and occupies a byte.
-        u64::from(integer.width().div_ceil(8)).max(1)
-    } else if obj.is::<MirFP16Type>() {
-        2
-    } else if obj.is::<FP32Type>() {
-        4
-    } else if obj.is::<FP64Type>() {
-        8
-    } else {
-        return None;
-    };
-    (size > 0).then_some(size)
-}
-
-/// Whether `local` is written exactly once — by the assignment being translated
-/// — and never has an address handed out.
-///
-/// This chooses *which of two correct lowerings* to use, never correctness: both
-/// give the local a private copy of the constant, and whether that copy is later
-/// deleted is `opt`'s own sound decision. So an unrecognised write form here only
-/// costs performance, which is why the statement match ends in a catch-all rather
-/// than an error.
-///
-/// It has to exist because the two lowerings fail in opposite directions. When
-/// the local really is read-only the copy disappears; when it is written the
-/// copy survives, and NVPTX expands a surviving `memcpy` into a *byte* loop —
-/// measurably worse than the element-wise stores it replaced. Rejecting every
-/// borrow, not just mutable ones, keeps this on the shape that motivates it
-/// (`TABLE[i]`, which projects a place and borrows nothing).
-fn constant_local_is_written_once(body: &mir::Body, local: mir::Local) -> bool {
-    let mut assignments = 0usize;
-    for block in body.blocks.iter() {
-        for statement in block.statements.iter() {
-            match &statement.kind {
-                mir::StatementKind::Assign(place, rvalue) => {
-                    if place.local == local {
-                        // A projected write is a write to part of the local.
-                        if !place.projection.is_empty() {
-                            return false;
-                        }
-                        assignments += 1;
-                    }
-                    // Any borrow or raw pointer, of either mutability, is a
-                    // path this scan cannot follow.
-                    match rvalue {
-                        mir::Rvalue::Ref(_, _, source) if source.local == local => return false,
-                        mir::Rvalue::AddressOf(_, source) if source.local == local => return false,
-                        _ => {}
-                    }
-                }
-                mir::StatementKind::SetDiscriminant { place, .. } if place.local == local => {
-                    return false;
-                }
-                _ => {}
-            }
-        }
-        // A call writes its destination.
-        if let mir::TerminatorKind::Call { destination, .. } = &block.terminator.kind
-            && destination.local == local
-        {
-            return false;
-        }
-    }
-    assignments == 1
-}
-
-/// Fill an addressable local from a fully-constant array by copying an immutable
-/// device global into it, instead of building the array in registers first.
-///
-/// `Ok(None)` means "not this shape" and the caller keeps the ordinary path.
-///
-/// # Why a copy and not just the global's address
-///
-/// The local is ordinary mutable storage — `let mut t = TABLE; t[0] = x;` is
-/// legal — so handing out the global's address would be wrong in general. A
-/// `memcpy` from `constant` storage is unconditionally correct instead, and
-/// `opt` supplies the proof that removes it: `isOnlyCopiedFromConstantMemory`
-/// deletes the copy and rewrites the reads to the global wherever the local is
-/// never written.
-///
-/// [`constant_local_is_written_once`] gates the path on the same property, so
-/// the two agree. It is not redundant: a copy that survives is *worse* than what
-/// it replaced, because NVPTX expands a surviving `memcpy` into a byte loop.
-///
-/// # Why this is worth doing at all
-///
-/// The value form cannot reach the global no matter how it is spelled: LLVM
-/// splits every first-class-aggregate load, so a whole-array load from the
-/// global is folded straight back into one store per element. Only a `memcpy`
-/// survives to the point where the proof can run.
-///
-/// What this replaces, for `TABLE[i]` with a runtime `i`, is one `st.local` per
-/// element in *every thread* — a per-thread copy of data the module image
-/// already carries — followed by `ld.local` reads of thread-private memory.
-pub(crate) fn translate_array_constant_into_alloca(
-    ctx: &mut Context,
-    body: &mir::Body,
-    dest_place: &mir::Place,
-    constant: &mir::ConstOperand,
-    value_map: &ValueMap,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<Option<Ptr<Operation>>> {
-    use pliron::builtin::attributes::IntegerAttr;
-
-    // Whole-local assignment only. With a projection the copy would have to land
-    // at an offset, which the ordinary element-wise path already handles.
-    if !dest_place.projection.is_empty() {
-        return Ok(None);
-    }
-    let Some(dest_addr) = value_map.get_slot(dest_place.local) else {
-        return Ok(None);
-    };
-    if !constant_local_is_written_once(body, dest_place.local) {
-        return Ok(None);
-    }
-
-    let rust_ty = constant.const_.ty();
-    let Ok(value_ty) = types::translate_type(ctx, &rust_ty) else {
-        return Ok(None);
-    };
-    if !value_ty.deref(ctx).is::<dialect_mir::types::MirArrayType>() {
-        return Ok(None);
-    }
-    // Elements whose whole-element read is a single scalar-like load, or whose
-    // fields are each addressed in place: primitive scalars, field-less enums,
-    // recursively promotable tuples and structs, and nested arrays of those.
-    if !promotable_array_element(ctx, value_ty) {
-        return Ok(None);
-    }
-    let Ok(expected_size) = rust_type_layout_size(rust_ty, loc.clone()) else {
-        return Ok(None);
-    };
-    // The copy is sized from the destination's *converted* type, while the bytes
-    // come from rustc's evaluated allocation. Require the two to agree before
-    // trusting a byte image: a padded tuple or an enum reaches its layout through
-    // `build_struct_slot_map` / `build_enum_slot_map`, and if either ever stopped
-    // reproducing rustc's size, this is the check that keeps a byte image from
-    // being copied over a differently-sized local.
-    if dialect_stored_size(ctx, value_ty) != Some(expected_size as u64) {
-        return Ok(None);
-    }
-    // Preserve both the evaluated byte image and any supported pointer
-    // relocations. Unsupported relocation targets keep the existing element-wise
-    // fallback rather than partially promoting the table.
-    let Ok(initializer) = promoted_array_initializer(constant, expected_size, "array", loc.clone())
-    else {
-        return Ok(None);
-    };
-    let promoted_anchor = materialize_promoted_initializer_targets(
-        ctx,
-        &initializer.relocations,
-        block_ptr,
-        prev_op,
-        loc.clone(),
-    )?;
-
-    // Past every promotion bail-out: emit one immutable global and copy it into the local.
-    let global_alloc = emit_promoted_immutable_global(
-        ctx,
-        value_ty,
-        &initializer,
-        block_ptr,
-        promoted_anchor,
-        loc.clone(),
-    );
-    let src = global_alloc.get_operation().deref(ctx).get_result(0);
-
-    // `mir.memcpy`'s count is in destination-pointee elements, and the
-    // destination slot points at the whole array, so one element is the whole
-    // table.
-    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signed);
-    let count_attr = IntegerAttr::new(i64_ty, APInt::from_i64(1, NonZeroUsize::new(64).unwrap()));
-    let count_op = Operation::new(
-        ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    count_op.deref_mut(ctx).set_loc(loc.clone());
-    MirConstantOp::new(count_op).set_attr_value(ctx, count_attr);
-    count_op.insert_after(ctx, global_alloc.get_operation());
-    let count = count_op.deref(ctx).get_result(0);
-
-    // Typed builder: stamps the elem_type fact from dest_addr (the whole
-    // promoted aggregate type; count is 1), read back by lowering.
-    let memcpy_op = dialect_mir::ops::MirMemcpyOp::build(ctx, dest_addr, src, count)?;
-    memcpy_op.deref_mut(ctx).set_loc(loc);
-    memcpy_op.insert_after(ctx, count_op);
-
-    Ok(Some(memcpy_op))
-}
-
-/// Enforce the pointer-to-array constant element boundary, as a hard error.
-///
-/// The admission question is [`promotable_array_element`], the same predicate
-/// used by the bare array value path's immutable-global optimization. A bare
-/// array that fails this gate can still fall back to element-wise materialization;
-/// a pointer-to-array constant has no such fallback, so failure here is an input
-/// error. Structs pass only when every field is recursively promotable.
-fn validate_ptr_to_array_constant_type(
-    ctx: &Context,
-    ty: TypeHandle,
-    loc: Location,
-) -> TranslationResult<()> {
-    if promotable_array_element(ctx, ty) {
-        return Ok(());
-    }
-
-    input_err!(
-        loc,
-        TranslationErr::unsupported(format!(
-            "Array constant element type is not supported: {:?}. Supported promoted array constants are primitive scalars (integers, f16, f32, f64), thin pointers/references with supported static relocations, field-less enums, tuples and structs recursively composed of supported fields, or nested arrays of those.",
-            ty.deref(ctx)
-        ))
-    )
-}
-
-fn constant_allocation(constant: &mir::ConstOperand) -> Option<&rustc_public::ty::Allocation> {
-    match constant.const_.kind() {
-        ConstantKind::Allocated(alloc) => Some(alloc),
-        ConstantKind::Ty(ty_const) => match ty_const.kind() {
-            rustc_public::ty::TyConstKind::Value(_, alloc) => Some(alloc),
-            _ => None,
-        },
-        _ => None,
-    }
-}
-
-/// Lower a bare `MirArrayType` value constant (e.g. `const TABLE: [f32; N] =
-/// [..]` indexed by runtime value) to a `MirConstructArrayOp`. Element stride
-/// and aggregate field offsets come from rustc layout. Thin pointer fields
-/// inside elements that relocate to device statics are materialized via
-/// [`MirGlobalAllocOp`] per field.
-fn translate_array_value_constant(
-    ctx: &mut Context,
-    constant: &mir::ConstOperand,
-    const_ty_ptr: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let element_ty = {
-        let ty_obj = const_ty_ptr.deref(ctx);
-        let Some(array_ty) = ty_obj.downcast_ref::<dialect_mir::types::MirArrayType>() else {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported("translate_array_value_constant: expected array type")
-            );
-        };
-        array_ty.element_type()
-    };
-
-    // Bare array values support primitive scalars, enums, initialized unions,
-    // tuples, structs, and nested arrays of those. Struct elements are decoded
-    // through the existing layout-aware aggregate path while pointer-to-array
-    // promotion remains intentionally unchanged; arrays nested inside struct
-    // constants have their own layout-aware entry point.
-    validate_array_value_element_type(ctx, element_ty, &loc)?;
-
-    let rust_array_ty = constant.const_.ty();
-    let alloc = match constant.const_.kind() {
-        ConstantKind::Allocated(alloc) => alloc.clone(),
-        ConstantKind::Ty(ty_const) => match ty_const.kind() {
-            rustc_public::ty::TyConstKind::Value(_, alloc) => alloc.clone(),
-            other => {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Array value constant must be backed by bytes, found TyConstKind::{other:?}"
-                    ))
-                );
-            }
-        },
-        ConstantKind::ZeroSized => {
-            return translate_array_value_constant_inner(
-                ctx,
-                constant,
-                const_ty_ptr,
-                rust_array_ty,
-                block_ptr,
-                prev_op,
-                loc,
-            );
-        }
-        other => {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Array value constant must be Allocated or Ty::Value, got {other:?}"
-                ))
-            );
-        }
-    };
-
-    translate_array_constant_from_alloc(
-        ctx,
-        &alloc,
-        0,
-        &rust_array_ty,
-        const_ty_ptr,
-        block_ptr,
-        prev_op,
-        loc,
-    )
-}
-
-fn rust_type_layout_size(ty: rustc_public::ty::Ty, loc: Location) -> TranslationResult<usize> {
-    ty.layout()
-        .map(|layout| layout.shape().size.bytes())
-        .map_err(|error| {
-            input_error!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Failed to query rustc layout for constant type {ty:?}: {error:?}"
-                ))
-            )
-        })
-}
-
-fn rust_array_type_info(
-    ty: rustc_public::ty::Ty,
-    loc: Location,
-) -> TranslationResult<(rustc_public::ty::Ty, u64)> {
-    match ty.kind() {
-        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Array(element_ty, count)) => {
-            let count = count.eval_target_usize().map_err(|error| {
-                input_error!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Failed to evaluate array constant length: {error:?}"
-                    ))
-                )
-            })?;
-            Ok((element_ty, count))
-        }
-        other => input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Array constant expected a Rust array type, got {other:?}"
-            ))
-        ),
-    }
-}
-
-/// Build a `MirConstructArrayOp` (and the necessary scalar / nested-array
-/// element ops) from a slice of raw bytes for an `array_ty`. Recurses on
-/// `MirArrayType` element types so multi-dimensional arrays (`[[T; M]; N]`,
-/// etc.) are handled by repeated decomposition.
-fn build_array_op_from_bytes(
-    ctx: &mut Context,
-    array_ty: TypeHandle,
-    rust_array_ty: rustc_public::ty::Ty,
-    bytes: &[u8],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    use pliron::builtin::types::{FP32Type, FP64Type, IntegerType};
-
-    // Element type + count.
-    let (element_ty_ptr, element_count) = {
-        let arr_ty_obj = array_ty.deref(ctx);
-        let arr_ty = arr_ty_obj
-            .downcast_ref::<dialect_mir::types::MirArrayType>()
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(
-                    "build_array_op_from_bytes: expected array type"
-                ))
-            })?;
-        (arr_ty.element_type(), arr_ty.size())
-    };
-
-    let (rust_element_ty, rust_element_count) = rust_array_type_info(rust_array_ty, loc.clone())?;
-    if rust_element_count != element_count {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Array constant length mismatch: Rust type has {rust_element_count} elements, dialect type has {element_count}"
-            ))
-        );
-    }
-    let element_byte_size = rust_type_layout_size(rust_element_ty, loc.clone())?;
-
-    let element_count_usize = usize::try_from(element_count).map_err(|_| {
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "Array constant element count {element_count} does not fit usize"
-        )))
-    })?;
-    let expected_bytes = element_count_usize
-        .checked_mul(element_byte_size)
-        .ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Array constant byte size overflowed: {} elements x {} bytes each",
-                element_count, element_byte_size
-            )))
-        })?;
-    if bytes.len() != expected_bytes {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Array constant has {} bytes but requires exactly {} ({} elements x {} bytes each)",
-                bytes.len(),
-                expected_bytes,
-                element_count,
-                element_byte_size
-            ))
-        );
-    }
-
-    #[derive(Clone, Copy)]
-    enum ElemKind {
-        F64,
-        F32,
-        F16,
-        Int { width: u32, signedness: Signedness },
-        Array,
-        Tuple,
-        Struct,
-    }
-    let elem_kind = {
-        let elem_obj = element_ty_ptr.deref(ctx);
-        if elem_obj.is::<FP64Type>() {
-            ElemKind::F64
-        } else if elem_obj.is::<FP32Type>() {
-            ElemKind::F32
-        } else if elem_obj.is::<MirFP16Type>() {
-            ElemKind::F16
-        } else if let Some(int_ty) = elem_obj.downcast_ref::<IntegerType>() {
-            ElemKind::Int {
-                width: int_ty.width(),
-                signedness: int_ty.signedness(),
-            }
-        } else if elem_obj.is::<dialect_mir::types::MirArrayType>() {
-            ElemKind::Array
-        } else if elem_obj.is::<dialect_mir::types::MirTupleType>() {
-            ElemKind::Tuple
-        } else if elem_obj.is::<dialect_mir::types::MirStructType>() {
-            ElemKind::Struct
-        } else {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Array constant element type is not supported by byte lowering: {:?}. \
-                     Byte lowering handles primitive scalars, tuples, structs, or nested \
-                     arrays of those. Enum elements decode from a constant \
-                     allocation instead, so an enum array that reaches byte lowering (e.g. \
-                     one with a zero-sized element) cannot be materialized here.",
-                    elem_obj
-                ))
-            );
-        }
-    };
-
-    let mut element_values = Vec::with_capacity(element_count_usize);
-    let mut last_op = prev_op;
-
-    for i in 0..element_count_usize {
-        let chunk = &bytes[i * element_byte_size..(i + 1) * element_byte_size];
-
-        let (elem_val, elem_last_op) = match elem_kind {
-            ElemKind::F64 => {
-                let mut buf = [0u8; 8];
-                buf.copy_from_slice(chunk);
-                let float_val = match rustc_public::target::MachineInfo::target_endianness() {
-                    rustc_public::target::Endian::Little => f64::from_le_bytes(buf),
-                    rustc_public::target::Endian::Big => f64::from_be_bytes(buf),
-                };
-                let float_attr = pliron::builtin::attributes::FPDoubleAttr::from(float_val);
-
-                use dialect_mir::ops::MirFloatConstantOp;
-                let op = Operation::new(
-                    ctx,
-                    MirFloatConstantOp::get_concrete_op_info(),
-                    vec![element_ty_ptr],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                op.deref_mut(ctx).set_loc(loc.clone());
-                let float_op = MirFloatConstantOp::new(op);
-                float_op.set_attr_float_value_f64(ctx, float_attr);
-
-                if let Some(prev) = last_op {
-                    float_op.get_operation().insert_after(ctx, prev);
-                } else {
-                    float_op.get_operation().insert_at_front(block_ptr, ctx);
-                }
-                (
-                    float_op.get_operation().deref(ctx).get_result(0),
-                    Some(float_op.get_operation()),
-                )
-            }
-            ElemKind::F32 => {
-                let mut buf = [0u8; 4];
-                buf.copy_from_slice(chunk);
-                let float_val = match rustc_public::target::MachineInfo::target_endianness() {
-                    rustc_public::target::Endian::Little => f32::from_le_bytes(buf),
-                    rustc_public::target::Endian::Big => f32::from_be_bytes(buf),
-                };
-                let float_attr = pliron::builtin::attributes::FPSingleAttr::from(float_val);
-
-                use dialect_mir::ops::MirFloatConstantOp;
-                let op = Operation::new(
-                    ctx,
-                    MirFloatConstantOp::get_concrete_op_info(),
-                    vec![element_ty_ptr],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                op.deref_mut(ctx).set_loc(loc.clone());
-                let float_op = MirFloatConstantOp::new(op);
-                float_op.set_attr_float_value(ctx, float_attr);
-
-                if let Some(prev) = last_op {
-                    float_op.get_operation().insert_after(ctx, prev);
-                } else {
-                    float_op.get_operation().insert_at_front(block_ptr, ctx);
-                }
-                (
-                    float_op.get_operation().deref(ctx).get_result(0),
-                    Some(float_op.get_operation()),
-                )
-            }
-            ElemKind::F16 => {
-                let bits = read_uint_from_bytes(chunk) as u16;
-                let float_attr = MirFP16Attr::from_bits(bits);
-
-                use dialect_mir::ops::MirFloatConstantOp;
-                let op = Operation::new(
-                    ctx,
-                    MirFloatConstantOp::get_concrete_op_info(),
-                    vec![element_ty_ptr],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                op.deref_mut(ctx).set_loc(loc.clone());
-                let float_op = MirFloatConstantOp::new(op);
-                float_op.set_attr_float_value_f16(ctx, float_attr);
-
-                if let Some(prev) = last_op {
-                    float_op.get_operation().insert_after(ctx, prev);
-                } else {
-                    float_op.get_operation().insert_at_front(block_ptr, ctx);
-                }
-                (
-                    float_op.get_operation().deref(ctx).get_result(0),
-                    Some(float_op.get_operation()),
-                )
-            }
-            ElemKind::Int { width, signedness } => {
-                let val = read_uint_from_bytes(chunk);
-                let apint = APInt::from_u128(val, NonZeroUsize::new(width as usize).unwrap());
-                let int_attr = pliron::builtin::attributes::IntegerAttr::new(
-                    IntegerType::get(ctx, width, signedness),
-                    apint,
-                );
-
-                use dialect_mir::ops::MirConstantOp;
-                let op = Operation::new(
-                    ctx,
-                    MirConstantOp::get_concrete_op_info(),
-                    vec![element_ty_ptr],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                op.deref_mut(ctx).set_loc(loc.clone());
-                let const_op = MirConstantOp::new(op);
-                const_op.set_attr_value(ctx, int_attr);
-
-                if let Some(prev) = last_op {
-                    const_op.get_operation().insert_after(ctx, prev);
-                } else {
-                    const_op.get_operation().insert_at_front(block_ptr, ctx);
-                }
-                (
-                    const_op.get_operation().deref(ctx).get_result(0),
-                    Some(const_op.get_operation()),
-                )
-            }
-            ElemKind::Array => build_array_op_from_bytes(
-                ctx,
-                element_ty_ptr,
-                rust_element_ty,
-                chunk,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?,
-            ElemKind::Tuple | ElemKind::Struct => translate_constant_value_from_bytes(
-                ctx,
-                &rust_element_ty,
-                element_ty_ptr,
-                chunk,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?,
-        };
-
-        element_values.push(elem_val);
-        last_op = elem_last_op;
-    }
-
-    use dialect_mir::ops::MirConstructArrayOp;
-    let construct_op = Operation::new(
-        ctx,
-        MirConstructArrayOp::get_concrete_op_info(),
-        vec![array_ty],
-        element_values,
-        vec![],
-        0,
-    );
-    construct_op.deref_mut(ctx).set_loc(loc.clone());
-
-    if let Some(prev) = last_op {
-        construct_op.insert_after(ctx, prev);
-    } else {
-        construct_op.insert_at_front(block_ptr, ctx);
-    }
-    last_op = Some(construct_op);
-
-    let array_val = construct_op.deref(ctx).get_result(0);
-    Ok((array_val, last_op))
-}
-
-/// Extract the raw allocation bytes for a bare array value, then recursively
-/// build the corresponding `MirConstructArrayOp`.
-fn translate_array_value_constant_inner(
-    ctx: &mut Context,
-    constant: &mir::ConstOperand,
-    array_ty: TypeHandle,
-    rust_array_ty: rustc_public::ty::Ty,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let bytes = constant_bytes(constant, "Array", loc.clone())?;
-
-    build_array_op_from_bytes(
-        ctx,
-        array_ty,
-        rust_array_ty,
-        &bytes,
-        block_ptr,
-        prev_op,
-        loc,
-    )
-}
-
-/// ## How it works
-///
-/// 1. Resolve the struct's own allocation (following by-ref provenance when the
-///    constant is a promoted `&Struct`)
-/// 2. Decode each field at its rustc layout offset from that allocation
-/// 3. Thin pointer fields that relocate to device statics become
-///    [`MirGlobalAllocOp`] results; other fields use the byte decoder
-/// 4. Create MirConstructStructOp with those operands
-///
-/// Each field is read at the byte offset rustc's layout records for it, so
-/// padding between fields and any reordering rustc applies are both accounted
-/// for. A field's size comes from the same layout, which is why a padded struct
-/// nested inside another is sliced at its true width rather than at the sum of
-/// its fields.
-///
-/// Aggregate **const** values with thin pointers to device statics are
-/// materialized per field; device-global initializers use a separate
-/// allocation-level relocation path instead of this value reconstruction.
-fn translate_struct_constant(
-    ctx: &mut Context,
-    constant: &mir::ConstOperand,
-    rust_ty: &rustc_public::ty::Ty,
-    const_ty_ptr: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    // Confirm the MIR type is a struct before touching the allocation.
-    {
-        let ty_obj = const_ty_ptr.deref(ctx);
-        if ty_obj
-            .downcast_ref::<dialect_mir::types::MirStructType>()
-            .is_none()
-        {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported("translate_struct_constant called on non-struct type")
-            );
-        }
-    }
-
-    // The constant's Rust type decides how to read the allocation. A
-    // reference or raw pointer means stable_mir handed over a promoted
-    // constant indirectly (`&(8..16)`): the allocation is a thin pointer whose
-    // provenance names the allocation with the actual struct data, and the
-    // layout query must run on the pointee. An aggregate type means the
-    // allocation IS the struct's memory image. Deciding by "has provenance"
-    // conflated the two: a by-value struct with a pointer field would have had
-    // its own bytes silently replaced by the first pointee's.
-    let by_ref_pointee = match rust_ty.kind() {
-        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Ref(_, pointee, _))
-        | rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::RawPtr(pointee, _)) => {
-            Some(pointee)
-        }
-        _ => None,
-    };
-    let struct_rust_ty = by_ref_pointee.unwrap_or(*rust_ty);
-
-    let alloc = match constant.const_.kind() {
-        ConstantKind::Allocated(alloc) => {
-            if by_ref_pointee.is_some() {
-                use rustc_public::mir::alloc::GlobalAlloc;
-                let Some(&(prov_pos, prov)) = alloc.provenance.ptrs.first() else {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(
-                            "Reference-to-struct constant has no provenance to follow".to_string()
-                        )
-                    );
-                };
-                // The pointer's data bytes encode the byte offset into the
-                // target allocation. Field decoding below starts at byte zero
-                // of that target, so an interior reference must fail loudly.
-                let ptr_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-                let ref_offset = alloc
-                    .read_partial_uint(prov_pos..prov_pos + ptr_width)
-                    .map_err(|e| {
-                        input_error_noloc!(TranslationErr::unsupported(format!(
-                            "Failed to read struct constant provenance offset: {:?}",
-                            e
-                        )))
-                    })?;
-                if ref_offset != 0 {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "Reference-to-struct constant points at interior offset {ref_offset}; \
-                             cuda-oxide cannot yet decode interior references to constants"
-                        ))
-                    );
-                }
-                let alloc_id = prov.0;
-                match GlobalAlloc::from(alloc_id) {
-                    GlobalAlloc::Memory(target_alloc) => target_alloc,
-                    GlobalAlloc::Static(static_def) => {
-                        static_def.eval_initializer().map_err(|e| {
-                            input_error_noloc!(TranslationErr::unsupported(format!(
-                                "Failed to evaluate static initializer for struct constant: {:?}",
-                                e
-                            )))
-                        })?
-                    }
-                    other => {
-                        return input_err!(
-                            loc,
-                            TranslationErr::unsupported(format!(
-                                "Struct constant provenance points to non-memory allocation: {:?}",
-                                other
-                            ))
-                        );
-                    }
-                }
-            } else {
-                // The allocation is the struct's own memory image (may contain
-                // thin-pointer relocations to device statics).
-                alloc.clone()
-            }
-        }
-        ConstantKind::ZeroSized => {
-            return translate_struct_constant_from_bytes(
-                ctx,
-                &struct_rust_ty,
-                const_ty_ptr,
-                &[],
-                block_ptr,
-                prev_op,
-                loc,
-            );
-        }
-        _ => {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Struct constant must be Allocated, got: {:?}. \
-                     Consider using inline construction: `let s = MyStruct {{ field: value }};`",
-                    constant.const_.kind()
-                ))
-            );
-        }
-    };
-
-    translate_struct_constant_from_alloc(
-        ctx,
-        &alloc,
-        0,
-        &struct_rust_ty,
-        const_ty_ptr,
-        block_ptr,
-        prev_op,
-        loc,
-    )
-}
-
-/// Byte image for a tuple constant, or `None` when a sized tuple has no
-/// backing allocation.
-///
-/// Undefined bytes in an allocation are padding; they are zeroed
-/// deterministically while the provenance map stays available separately for
-/// pointer-field reconstruction. `ConstantKind::ZeroSized`-style constants
-/// (e.g. `((), ())`) carry no allocation at all; a zero-byte layout is
-/// reproduced exactly by an empty image.
-fn tuple_constant_byte_image(
-    allocation: Option<&rustc_public::ty::Allocation>,
-    layout_size: usize,
-) -> Option<Vec<u8>> {
-    match allocation {
-        Some(allocation) => Some(
-            allocation
-                .bytes
-                .iter()
-                .map(|byte| byte.unwrap_or(0))
-                .collect(),
-        ),
-        None if layout_size == 0 => Some(Vec::new()),
-        None => None,
-    }
-}
-
-/// Translate a non-empty tuple constant from its own allocation image.
-///
-/// Unlike `constant_bytes`, this must not follow the first provenance entry:
-/// for a by-value tuple, that entry names one pointer field's target, while the
-/// allocation itself still contains the tuple's scalar fields and padding.
-/// Pointer fields consume their relocation entries through the
-/// allocation-aware decoder below.
-fn translate_tuple_constant(
-    ctx: &mut Context,
-    constant: &mir::ConstOperand,
-    rust_ty: &rustc_public::ty::Ty,
-    const_ty_ptr: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let layout_size = rust_ty
-        .layout()
-        .map_err(|error| {
-            input_error!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Failed to query layout for tuple constant: {error:?}"
-                ))
-            )
-        })?
-        .shape()
-        .size
-        .bytes();
-
-    let Some(allocation) = constant_allocation(constant) else {
-        let bytes = tuple_constant_byte_image(None, layout_size).ok_or_else(|| {
-            input_error!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Tuple constant of {layout_size} byte(s) must be backed by an allocation, \
-                     found {:?}",
-                    constant.const_.kind()
-                ))
-            )
-        })?;
-        return translate_tuple_constant_from_bytes(
-            ctx,
-            rust_ty,
-            const_ty_ptr,
-            &bytes,
-            block_ptr,
-            prev_op,
-            loc,
-        );
-    };
-
-    translate_tuple_constant_from_alloc(
-        ctx,
-        allocation,
-        0,
-        rust_ty,
-        const_ty_ptr,
-        block_ptr,
-        prev_op,
-        loc,
-    )
-}
-
-/// Translate a tuple constant from bytes using rustc's field offsets.
-fn translate_tuple_constant_from_bytes(
-    ctx: &mut Context,
-    rust_ty: &rustc_public::ty::Ty,
-    const_ty_ptr: TypeHandle,
-    bytes: &[u8],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let (field_types, mir_field_offsets, mir_memory_order, mir_total_size, mir_abi_align) = {
-        let ty_ref = const_ty_ptr.deref(ctx);
-        let tuple_ty = ty_ref
-            .downcast_ref::<dialect_mir::types::MirTupleType>()
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(
-                    "translate_tuple_constant called on non-tuple type"
-                ))
-            })?;
-        (
-            tuple_ty.get_types().to_vec(),
-            tuple_ty.field_offsets().to_vec(),
-            tuple_ty.memory_order(),
-            tuple_ty.total_size(),
-            tuple_ty.abi_align(),
-        )
-    };
-
-    let rust_field_types = match rust_ty.kind() {
-        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Tuple(fields)) => {
-            fields.to_vec()
-        }
-        other => {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Tuple constant expected Rust tuple type, got {:?}",
-                    other
-                ))
-            );
-        }
-    };
-
-    if field_types.len() != rust_field_types.len() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Tuple constant type mismatch: MIR has {} fields, Rust type has {}",
-                field_types.len(),
-                rust_field_types.len()
-            ))
-        );
-    }
-
-    let layout = rust_ty.layout().map_err(|error| {
-        input_error!(
-            loc.clone(),
-            TranslationErr::unsupported(format!(
-                "Failed to query layout for tuple constant: {error:?}"
-            ))
-        )
-    })?;
-    let shape = layout.shape();
-    let tuple_size = shape.size.bytes();
-    if bytes.len() != tuple_size {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Tuple constant has {} bytes but rustc layout requires exactly {tuple_size}",
-                bytes.len()
-            ))
-        );
-    }
-
-    let field_offsets = match &shape.fields {
-        rustc_public::abi::FieldsShape::Primitive if field_types.is_empty() => vec![],
-        rustc_public::abi::FieldsShape::Arbitrary { offsets } => offsets
-            .iter()
-            .map(|offset| offset.bytes())
-            .collect::<Vec<_>>(),
-        fields => {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Tuple constant fields use unsupported layout shape {fields:?}"
-                ))
-            );
-        }
-    };
-    if field_offsets.len() != field_types.len() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Tuple constant layout has {} offsets for {} fields",
-                field_offsets.len(),
-                field_types.len()
-            ))
-        );
-    }
-    if !field_types.is_empty() {
-        let rust_field_offsets = field_offsets
-            .iter()
-            .map(|offset| *offset as u64)
-            .collect::<Vec<_>>();
-        let rust_memory_order = shape.fields.fields_by_offset_order();
-        if mir_field_offsets != rust_field_offsets
-            || mir_memory_order != rust_memory_order
-            || mir_total_size != tuple_size as u64
-            || mir_abi_align != shape.abi_align
-        {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Tuple constant layout disagrees between rustc and dialect-mir: rustc offsets/order/size/alignment {:?}/{:?}/{}/{}, dialect {:?}/{:?}/{}/{}",
-                    rust_field_offsets,
-                    rust_memory_order,
-                    tuple_size,
-                    shape.abi_align,
-                    mir_field_offsets,
-                    mir_memory_order,
-                    mir_total_size,
-                    mir_abi_align
-                ))
-            );
-        }
-    }
-
-    let mut values = Vec::with_capacity(field_types.len());
-    let mut current_prev_op = prev_op;
-
-    for (field_idx, (field_ty, rust_field_ty)) in field_types
-        .iter()
-        .copied()
-        .zip(rust_field_types.iter())
-        .enumerate()
-    {
-        let byte_offset = field_offsets[field_idx];
-        let byte_size = rust_type_layout_size(*rust_field_ty, loc.clone())?;
-
-        let field_end = byte_offset.checked_add(byte_size).ok_or_else(|| {
-            input_error!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Tuple constant field {field_idx} overflowed offset computation"
-                ))
-            )
-        })?;
-        let field_bytes = if byte_size == 0 {
-            &[][..]
-        } else if field_end <= bytes.len() {
-            &bytes[byte_offset..field_end]
-        } else {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Tuple constant has insufficient bytes for field {} (need {} bytes at offset {}, have {})",
-                    field_idx,
-                    byte_size,
-                    byte_offset,
-                    bytes.len()
-                ))
-            );
-        };
-
-        let (value, new_prev_op) = translate_constant_value_from_bytes(
-            ctx,
-            rust_field_ty,
-            field_ty,
-            field_bytes,
-            block_ptr,
-            current_prev_op,
-            loc.clone(),
-        )?;
-        values.push(value);
-        current_prev_op = new_prev_op;
-    }
-
-    use dialect_mir::ops::MirConstructTupleOp;
-    let op = Operation::new(
-        ctx,
-        MirConstructTupleOp::get_concrete_op_info(),
-        vec![const_ty_ptr],
-        values,
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc);
-
-    if let Some(prev) = current_prev_op {
-        op.insert_after(ctx, prev);
-    } else {
-        op.insert_at_front(block_ptr, ctx);
-    }
-
-    Ok((op.deref(ctx).get_result(0), Some(op)))
-}
-
-/// Storage size of a struct constant from its recorded layout, or `None` when
-/// that layout is missing.
-///
-/// rustc's size counts the padding between and after fields, so it is what a
-/// reader must stride by. Summing the field sizes would under-report any padded
-/// struct and hand a short byte slice to whoever reads it.
-///
-/// Recorded offsets are what separates a known layout from a failed query:
-/// `translator/types.rs` stores empty offsets and a zero size when `Ty::layout()`
-/// fails. A zero size on its own does not imply a failure, since a struct whose
-/// fields are all zero-sized is genuinely zero bytes wide. `is_zst_type` does not
-/// cover those, because it calls a struct zero-sized only when it has no fields
-/// at all, so a `PhantomData` newtype reaches here with one field and a size of
-/// zero.
-fn struct_storage_size(field_count: usize, offset_count: usize, total_size: u64) -> Option<usize> {
-    if offset_count == 0 && field_count > 0 {
-        None
-    } else {
-        Some(total_size as usize)
-    }
-}
-
-fn constant_storage_size(ctx: &Context, ty_ptr: TypeHandle) -> Option<usize> {
-    let ty_ref = ty_ptr.deref(ctx);
-    if types::is_zst_type(ctx, ty_ptr) {
-        Some(0)
-    } else if let Some(int_ty) = ty_ref.downcast_ref::<IntegerType>() {
-        Some((int_ty.width() as usize).div_ceil(8))
-    } else if ty_ref.is::<MirFP16Type>() {
-        Some(2)
-    } else if ty_ref.is::<FP32Type>() {
-        Some(4)
-    } else if ty_ref.is::<FP64Type>() {
-        Some(8)
-    } else if ty_ref.is::<dialect_mir::types::MirPtrType>() {
-        Some(rustc_public::target::MachineInfo::target_pointer_width().bytes())
-    } else if let Some(st) = ty_ref.downcast_ref::<dialect_mir::types::MirStructType>() {
-        struct_storage_size(
-            st.field_types().len(),
-            st.field_offsets().len(),
-            st.total_size(),
-        )
-    } else if let Some(union_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirUnionType>() {
-        usize::try_from(union_ty.total_size()).ok()
-    } else if let Some(at) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
-        let elem = at.element_type();
-        let n = at.size() as usize;
-        Some(constant_storage_size(ctx, elem)? * n)
-    } else {
-        None
-    }
-}
-
-/// Whether a constant-storage type contains a pointer-bearing leaf.
-///
-/// Raw-byte constant materialization is only sound when this returns false.
-/// Provenance-aware aggregate paths use the same predicate to decide whether
-/// they need typed reconstruction instead.
-fn constant_type_contains_pointer(ctx: &Context, ty: TypeHandle) -> bool {
-    let ty_ref = ty.deref(ctx);
-    if ty_ref.is::<dialect_mir::types::MirPtrType>()
-        || ty_ref.is::<dialect_mir::types::MirSliceType>()
-        || ty_ref.is::<dialect_mir::types::MirDisjointSliceType>()
-    {
-        return true;
-    }
-    if let Some(array) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
-        let element = array.element_type();
-        drop(ty_ref);
-        return constant_type_contains_pointer(ctx, element);
-    }
-    let children: Vec<TypeHandle> =
-        if let Some(tuple) = ty_ref.downcast_ref::<dialect_mir::types::MirTupleType>() {
-            tuple.get_types().to_vec()
-        } else if let Some(structure) = ty_ref.downcast_ref::<dialect_mir::types::MirStructType>() {
-            structure.field_types().to_vec()
-        } else if let Some(enumeration) = ty_ref.downcast_ref::<dialect_mir::types::MirEnumType>() {
-            enumeration.all_field_types.clone()
-        } else if let Some(union_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirUnionType>() {
-            union_ty.field_types().to_vec()
-        } else {
-            return false;
-        };
-    drop(ty_ref);
-    children
-        .into_iter()
-        .any(|child| constant_type_contains_pointer(ctx, child))
-}
-
-/// Physical representation strategy for an initialized union constant.
-///
-/// rustc does not retain the source-level active field in an evaluated union
-/// allocation. Pointer-free unions can therefore use the exact byte image,
-/// while a provenance-bearing union is only reconstructible without guessing
-/// an active field when every non-ZST alternative is the same class of thin
-/// pointer storage.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-enum UnionConstantStorageKind {
-    ByteImage,
-    ThinPointer {
-        field_index: usize,
-        field_ty: TypeHandle,
-    },
-}
-
-/// How a classified union constant is consumed by its caller.
-///
-/// SSA reconstruction materializes the carrier field's own reference type, so
-/// a reference minted for the wrong alternative could claim validity for a
-/// pointee the program never wrote. Device-static physical storage emits the
-/// exact evaluated bytes plus one integer-width relocation slot and never
-/// mints a typed reference, so same-kind reference alternatives may keep
-/// different pointee views there; device code reads the storage through its
-/// own field types.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-enum UnionConstantUse {
-    SsaReconstruction,
-    PhysicalStorage,
-}
-
-fn classify_union_constant_storage(
-    ctx: &Context,
-    union_ty: TypeHandle,
-    usage: UnionConstantUse,
-) -> Result<UnionConstantStorageKind, String> {
-    let (name, field_types) = {
-        let ty_ref = union_ty.deref(ctx);
-        let union_ty = ty_ref
-            .downcast_ref::<dialect_mir::types::MirUnionType>()
-            .ok_or_else(|| {
-                "classify_union_constant_storage called on non-union type".to_string()
-            })?;
-        (union_ty.name().to_string(), union_ty.field_types().to_vec())
-    };
-
-    if !field_types
-        .iter()
-        .copied()
-        .any(|field| constant_type_contains_pointer(ctx, field))
-    {
-        return Ok(UnionConstantStorageKind::ByteImage);
-    }
-
-    let mut carrier: Option<(usize, TypeHandle, u32, MirPointerKind, bool)> = None;
-    for (field_index, field_ty) in field_types.into_iter().enumerate() {
-        if types::is_zst_type(ctx, field_ty) {
-            continue;
-        }
-
-        let pointer_semantics = {
-            let field_ref = field_ty.deref(ctx);
-            field_ref
-                .downcast_ref::<dialect_mir::types::MirPtrType>()
-                .map(|ptr| (ptr.address_space, ptr.kind, ptr.is_mutable))
-        };
-
-        let Some((address_space, pointer_kind, is_mutable)) = pointer_semantics else {
-            if constant_type_contains_pointer(ctx, field_ty) {
-                return Err(format!(
-                    "Initialized union constant `{name}` contains pointer-bearing field \
-                     {field_index} that is not a thin pointer; fat or nested pointer storage \
-                     in union constants is not supported"
-                ));
-            }
-            return Err(format!(
-                "Initialized union constant `{name}` overlaps thin-pointer storage with \
-                 non-pointer field {field_index}; pointer/integer union constants cannot \
-                 preserve both provenance and exact integer bits"
-            ));
-        };
-
-        if dialect_mir::types::is_opaque_fn_pointer_type(ctx, field_ty) {
-            return Err(format!(
-                "Initialized union constant `{name}` contains canonical function-pointer \
-                 field {field_index}; function tokens cannot serve as data-pointer union storage"
-            ));
-        }
-        if pointer_kind == MirPointerKind::UniqueRef {
-            return Err(format!(
-                "Initialized union constant `{name}` contains UniqueRef field {field_index}; \
-                 constant reconstruction cannot establish uniqueness"
-            ));
-        }
-
-        match carrier {
-            None => {
-                carrier = Some((
-                    field_index,
-                    field_ty,
-                    address_space,
-                    pointer_kind,
-                    is_mutable,
-                ));
-            }
-            Some((
-                _,
-                carrier_field_ty,
-                carrier_address_space,
-                carrier_kind,
-                carrier_mutability,
-            )) if carrier_address_space == address_space
-                && carrier_kind == pointer_kind
-                && carrier_mutability == is_mutable =>
-            {
-                if usage == UnionConstantUse::SsaReconstruction
-                    && pointer_kind == MirPointerKind::SharedRef
-                    && carrier_field_ty != field_ty
-                {
-                    return Err(format!(
-                        "Initialized union constant `{name}` mixes reference pointee types; \
-                         rustc's evaluated allocation does not retain the active union field, \
-                         so reconstructing either reference view could invent pointee validity"
-                    ));
-                }
-            }
-            Some((_, _, carrier_address_space, carrier_kind, carrier_mutability)) => {
-                return Err(format!(
-                    "Initialized union constant `{name}` mixes pointer storage semantics \
-                     (address space/kind/mutability {carrier_address_space}/{carrier_kind:?}/{carrier_mutability} \
-                     and {address_space}/{pointer_kind:?}/{is_mutable}); one union carrier cannot \
-                     preserve both representations and Rust pointer categories"
-                ));
-            }
-        }
-    }
-
-    let Some((field_index, field_ty, _, _, _)) = carrier else {
-        return Err(format!(
-            "Initialized union constant `{name}` is pointer-bearing but has no non-ZST \
-             thin-pointer field"
-        ));
-    };
-
-    Ok(UnionConstantStorageKind::ThinPointer {
-        field_index,
-        field_ty,
-    })
-}
-
-/// Return the full-width integer field through which a relocation-free mixed
-/// raw-pointer/integer union can be reconstructed without producing a pointer.
-///
-/// Keep this deliberately narrower than [`classify_union_constant_storage`]:
-/// the ordinary classifier remains the provenance-preserving authority used by
-/// pointer-bearing constants and device-static union initializers. This helper
-/// only admits one naturally aligned pointer word whose non-ZST alternatives
-/// are semantically compatible generic raw pointers or full-width integers.
-fn relocation_free_pointer_integer_union_storage_field(
-    ctx: &Context,
-    union_ty: TypeHandle,
-    pointer_width: usize,
-) -> Option<(usize, TypeHandle)> {
-    let (union_size, union_align, field_types) = {
-        let ty_ref = union_ty.deref(ctx);
-        let union_ty = ty_ref.downcast_ref::<dialect_mir::types::MirUnionType>()?;
-        (
-            union_ty.total_size(),
-            union_ty.abi_align(),
-            union_ty.field_types().to_vec(),
-        )
-    };
-
-    let pointer_width_u64 = pointer_width as u64;
-    if union_size != pointer_width_u64 || union_align != pointer_width_u64 {
-        return None;
-    }
-
-    let integer_width = (pointer_width * 8) as u32;
-    let mut pointer_semantics = None;
-    let mut saw_pointer = false;
-    let mut integer_field = None;
-
-    for (field_index, field_ty) in field_types.into_iter().enumerate() {
-        if types::is_zst_type(ctx, field_ty) {
-            continue;
-        }
-
-        let field_ref = field_ty.deref(ctx);
-        if let Some(pointer) = field_ref.downcast_ref::<dialect_mir::types::MirPtrType>() {
-            if !matches!(
-                pointer.kind,
-                MirPointerKind::RawConst | MirPointerKind::RawMut
-            ) || pointer.address_space != dialect_mir::types::address_space::GENERIC
-            {
-                return None;
-            }
-            let semantics = (pointer.address_space, pointer.kind, pointer.is_mutable);
-            match pointer_semantics {
-                None => pointer_semantics = Some(semantics),
-                Some(existing) if existing == semantics => {}
-                Some(_) => return None,
-            }
-            saw_pointer = true;
-            continue;
-        }
-
-        if field_ref
-            .downcast_ref::<IntegerType>()
-            .is_some_and(|integer| integer.width() == integer_width)
-        {
-            integer_field.get_or_insert((field_index, field_ty));
-            continue;
-        }
-
-        // Fat pointers, nested pointer aggregates, partial-width integers, and
-        // unrelated scalar/aggregate alternatives keep the existing fail-closed
-        // path. The byte-image exception is intentionally pointer-word exact.
-        return None;
-    }
-
-    saw_pointer.then_some(())?;
-    integer_field
-}
-
-/// Admit only the device-static union shape whose complete storage can be
-/// represented by one provenance-preserving thin-pointer relocation.
-///
-/// Device-global initializers do not retain a source-level active union field,
-/// so this path must prove the physical storage without guessing one. Keep the
-/// scope deliberately narrower than ordinary union SSA lowering: one top-level
-/// pointer-sized union, naturally aligned, one relocation at byte zero, and
-/// every non-ZST alternative a representation-compatible thin pointer.
-fn validate_device_static_union_initializer(
-    ctx: &Context,
-    static_def: &rustc_public::mir::mono::StaticDef,
-    union_ty: TypeHandle,
-    initializer: &GlobalInitializerData,
-    loc: Location,
-) -> TranslationResult<()> {
-    let relocation_slots: Vec<(u64, u32)> = initializer
-        .relocations
-        .iter()
-        .map(|relocation| (relocation.source_offset, relocation.width_bytes))
-        .collect();
-    validate_device_static_union_storage(
-        ctx,
-        union_ty,
-        rustc_public::target::MachineInfo::target_pointer_width().bytes(),
-        initializer.bytes.len() as u64,
-        initializer.alignment,
-        &relocation_slots,
-    )
-    .map_err(|message| {
-        input_error!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "device static {} contains {message}",
-                static_def.name()
-            ))
-        )
-    })
-}
-
-/// Pure storage gate behind [`validate_device_static_union_initializer`]:
-/// accept only a union that is one naturally aligned pointer word whose
-/// evaluated initializer is exactly one full-width relocation at byte zero.
-/// The caller attaches the static's name and source location to rejections.
-fn validate_device_static_union_storage(
-    ctx: &Context,
-    union_ty: TypeHandle,
-    pointer_width: usize,
-    initializer_len: u64,
-    initializer_align: u64,
-    relocation_slots: &[(u64, u32)],
-) -> Result<(), String> {
-    let (union_name, union_size, union_align) = {
-        let ty_ref = union_ty.deref(ctx);
-        let union_ty = ty_ref
-            .downcast_ref::<dialect_mir::types::MirUnionType>()
-            .ok_or_else(|| {
-                "a non-union type in the device-static union initializer gate".to_string()
-            })?;
-        (
-            union_ty.name().to_string(),
-            union_ty.total_size(),
-            union_ty.abi_align(),
-        )
-    };
-
-    let storage_kind =
-        classify_union_constant_storage(ctx, union_ty, UnionConstantUse::PhysicalStorage).map_err(
-            |message| {
-                format!(
-                    "union `{union_name}` whose initializer cannot preserve pointer provenance: \
-                 {message}"
-                )
-            },
-        )?;
-    if !matches!(storage_kind, UnionConstantStorageKind::ThinPointer { .. }) {
-        return Err(format!(
-            "union `{union_name}` without thin-pointer storage; device-global union \
-             initializers are supported only when every non-ZST alternative is a \
-             representation-compatible thin pointer"
-        ));
-    }
-
-    if pointer_width != 8 {
-        return Err(format!(
-            "union `{union_name}`, but cuda-oxide currently supports device-global union \
-             relocations only for 8-byte NVPTX pointers"
-        ));
-    }
-    let pointer_width_u64 = pointer_width as u64;
-
-    if union_size != pointer_width_u64 || union_align != pointer_width_u64 {
-        return Err(format!(
-            "union `{union_name}` with size/alignment {union_size}/{union_align}; \
-             device-global union relocations require exactly one naturally aligned \
-             {pointer_width}-byte pointer word"
-        ));
-    }
-    if initializer_len != pointer_width_u64 || initializer_align != pointer_width_u64 {
-        return Err(format!(
-            "union `{union_name}` with evaluated initializer size/alignment \
-             {initializer_len}/{initializer_align}, expected {pointer_width}/{pointer_width}"
-        ));
-    }
-
-    let [(source_offset, width_bytes)] = relocation_slots else {
-        return Err(format!(
-            "union `{union_name}` with {} initializer relocations; exactly one \
-             thin-pointer relocation is required",
-            relocation_slots.len()
-        ));
-    };
-    if *source_offset != 0 || u64::from(*width_bytes) != pointer_width_u64 {
-        return Err(format!(
-            "union `{union_name}` whose relocation occupies byte {source_offset} with \
-             width {width_bytes}, expected one {pointer_width}-byte slot at byte zero"
-        ));
-    }
-
-    Ok(())
-}
-
-/// Verify that rustc and the MIR union agree on the exact stored size.
-fn union_constant_storage_size(
-    ctx: &Context,
-    rust_ty: &rustc_public::ty::Ty,
-    union_ty: TypeHandle,
-    loc: &Location,
-) -> TranslationResult<usize> {
-    let rust_size = rust_type_layout_size(*rust_ty, loc.clone())?;
-    let (name, mir_size) = {
-        let ty_ref = union_ty.deref(ctx);
-        let union_ty = ty_ref
-            .downcast_ref::<dialect_mir::types::MirUnionType>()
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(
-                    "union_constant_storage_size called on non-union type"
-                ))
-            })?;
-        let size = usize::try_from(union_ty.total_size()).map_err(|_| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Union constant `{}` size {} does not fit usize",
-                union_ty.name(),
-                union_ty.total_size()
-            )))
-        })?;
-        (union_ty.name().to_string(), size)
-    };
-
-    if rust_size != mir_size {
-        return input_err!(
-            loc.clone(),
-            TranslationErr::unsupported(format!(
-                "Union constant `{name}` has rustc size {rust_size}, but MirUnionType records {mir_size}"
-            ))
-        );
-    }
-    Ok(rust_size)
-}
-
-/// Materialize a non-ZST union constant without guessing an active field.
-///
-/// rustc constant evaluation gives us the physical storage image and its
-/// initialization mask, but not a source-level active-field identity. Pointer-free
-/// unions therefore keep the exact byte image. Pointer-only unions use a typed
-/// carrier selected from representation-compatible fields so relocation provenance
-/// survives without claiming which source field initialized the allocation.
-fn translate_union_constant(
-    ctx: &mut Context,
-    constant: &mir::ConstOperand,
-    rust_ty: &rustc_public::ty::Ty,
-    union_ty: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let size = union_constant_storage_size(ctx, rust_ty, union_ty, &loc)?;
-    if size == 0 {
-        return translate_zero_sized_constant_value(ctx, union_ty, block_ptr, prev_op, loc);
-    }
-
-    let Some(alloc) = constant_allocation(constant) else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Initialized union constant of {size} byte(s) must be backed by an allocation, found {:?}",
-                constant.const_.kind()
-            ))
-        );
-    };
-
-    translate_union_constant_from_alloc(ctx, alloc, 0, rust_ty, union_ty, block_ptr, prev_op, loc)
-}
-
-/// Materialize one union value from an allocation while preserving its storage semantics.
-///
-/// Pointer-free unions retain the existing byte-image path and exact initialization
-/// mask. A union whose every non-ZST alternative is a compatible thin pointer
-/// instead uses one typed pointer carrier so rustc relocation provenance never
-/// becomes integer bytes. A naturally aligned pointer-word union that overlaps
-/// compatible thin pointers with full-width integers may also use the byte image,
-/// but only when no relocation overlaps its storage. Relocation-bearing mixed
-/// unions, fat pointers, nested pointer aggregates, and ambiguous layouts remain
-/// fail-closed.
-#[allow(clippy::too_many_arguments)]
-fn translate_union_constant_from_alloc(
-    ctx: &mut Context,
-    alloc: &rustc_public::ty::Allocation,
-    base_offset: usize,
-    rust_ty: &rustc_public::ty::Ty,
-    union_ty: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let size = union_constant_storage_size(ctx, rust_ty, union_ty, &loc)?;
-    if size == 0 {
-        return translate_zero_sized_constant_value(ctx, union_ty, block_ptr, prev_op, loc);
-    }
-
-    let end = base_offset.checked_add(size).ok_or_else(|| {
-        input_error!(
-            loc.clone(),
-            TranslationErr::unsupported(format!(
-                "Union constant byte range overflows: offset {base_offset} + size {size}"
-            ))
-        )
-    })?;
-    if end > alloc.bytes.len() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Union constant needs bytes [{base_offset}..{end}), but allocation is only {} bytes",
-                alloc.bytes.len()
-            ))
-        );
-    }
-
-    let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-    let relocations = relocation_offsets_overlapping_range(
-        &alloc.provenance.ptrs,
-        base_offset,
-        end,
-        pointer_width,
-    );
-    let storage = &alloc.bytes[base_offset..end];
-
-    // A mixed pointer/integer union initialized through the integer view carries
-    // no relocation provenance. When every byte is initialized, the evaluated
-    // byte image is the complete storage truth. Reconstruct it through the
-    // full-width integer field so no inactive pointer alternative is produced.
-    // Keep this no-relocation exception separate: #984's device-static gate and
-    // relocation-bearing union constants use the stricter pointer classifier.
-    if relocations.is_empty()
-        && storage.iter().all(Option::is_some)
-        && let Some((integer_field_index, integer_field_ty)) =
-            relocation_free_pointer_integer_union_storage_field(ctx, union_ty, pointer_width)
-    {
-        return translate_pointer_integer_union_constant_from_storage(
-            ctx,
-            union_ty,
-            integer_field_index,
-            integer_field_ty,
-            storage,
-            block_ptr,
-            prev_op,
-            loc,
-        );
-    }
-
-    let storage_kind =
-        classify_union_constant_storage(ctx, union_ty, UnionConstantUse::SsaReconstruction)
-            .map_err(|message| input_error!(loc.clone(), TranslationErr::unsupported(message)))?;
-
-    match storage_kind {
-        UnionConstantStorageKind::ByteImage => {
-            if !relocations.is_empty() {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Pointer-free union constant has relocation(s) overlapping byte offset(s) \
-                         {relocations:?}; the union type does not contain storage that can \
-                         preserve that provenance"
-                    ))
-                );
-            }
-
-            translate_union_constant_from_storage(ctx, union_ty, storage, block_ptr, prev_op, loc)
-        }
-        UnionConstantStorageKind::ThinPointer {
-            field_index,
-            field_ty,
-        } => {
-            if size != pointer_width {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Thin-pointer union constant has size {size}, but the target pointer width \
-                         is {pointer_width}; over-aligned or padded pointer-union constants are \
-                         not yet supported because their non-pointer bytes would need a separate \
-                         initialization-mask representation"
-                    ))
-                );
-            }
-
-            if relocations.iter().any(|offset| *offset != base_offset) || relocations.len() > 1 {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Thin-pointer union constant expects at most one relocation anchored at \
-                         byte {base_offset}, found overlapping relocation start(s) {relocations:?}"
-                    ))
-                );
-            }
-
-            let pointer_end = base_offset + pointer_width;
-            if alloc.bytes[base_offset..pointer_end]
-                .iter()
-                .any(|byte| byte.is_none())
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "Thin-pointer union constant contains uninitialized bytes in its pointer \
-                         carrier; partially initialized pointer storage cannot be reconstructed"
-                            .to_string()
-                    )
-                );
-            }
-
-            let (pointer, current_prev_op) = translate_thin_pointer_at_alloc_offset(
-                ctx,
-                alloc,
-                base_offset,
-                field_ty,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-
-            let undef_op = MirUndefOp::new(ctx, union_ty).get_operation();
-            undef_op.deref_mut(ctx).set_loc(loc.clone());
-            match current_prev_op {
-                Some(prev) => undef_op.insert_after(ctx, prev),
-                None => undef_op.insert_at_front(block_ptr, ctx),
-            }
-            let undef_value = undef_op.deref(ctx).get_result(0);
-
-            let insert_op = Operation::new(
-                ctx,
-                MirInsertFieldOp::get_concrete_op_info(),
-                vec![union_ty],
-                vec![undef_value, pointer],
-                vec![],
-                0,
-            );
-            insert_op.deref_mut(ctx).set_loc(loc);
-            MirInsertFieldOp::new(insert_op).set_attr_insert_index(
-                ctx,
-                dialect_mir::attributes::FieldIndexAttr(field_index as u32),
-            );
-            insert_op.insert_after(ctx, undef_op);
-
-            Ok((insert_op.deref(ctx).get_result(0), Some(insert_op)))
-        }
-    }
-}
-
-/// Build `[u8; size]` with one SSA value per physical byte and transmute it to
-/// the union type. `None` bytes become `mir.undef`; no inactive byte is invented.
-fn translate_union_constant_from_storage(
-    ctx: &mut Context,
-    union_ty: TypeHandle,
-    storage: &[Option<u8>],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    if storage.is_empty() {
-        return translate_zero_sized_constant_value(ctx, union_ty, block_ptr, prev_op, loc);
-    }
-
-    let (byte_array, array_op) =
-        translate_constant_storage_byte_array(ctx, storage, block_ptr, prev_op, loc.clone());
-
-    let cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![union_ty],
-        vec![byte_array],
-        vec![],
-        0,
-    );
-    cast_op.deref_mut(ctx).set_loc(loc);
-    MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::Transmute);
-    cast_op.insert_after(ctx, array_op);
-
-    Ok((cast_op.deref(ctx).get_result(0), Some(cast_op)))
-}
-
-/// Reconstruct a relocation-free pointer/integer union through its integer
-/// field, exactly as an ordinary Rust union aggregate is constructed.
-///
-/// The byte-array-to-integer transmute is representation-only and produces no
-/// pointer carrier. Inserting that integer into an undefined union therefore
-/// keeps the pointer alternatives inactive instead of asking a synthetic
-/// transmute to establish their raw-pointer kinds.
-#[allow(clippy::too_many_arguments)]
-fn translate_pointer_integer_union_constant_from_storage(
-    ctx: &mut Context,
-    union_ty: TypeHandle,
-    integer_field_index: usize,
-    integer_field_ty: TypeHandle,
-    storage: &[Option<u8>],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    debug_assert!(!storage.is_empty());
-
-    let (byte_array, array_op) =
-        translate_constant_storage_byte_array(ctx, storage, block_ptr, prev_op, loc.clone());
-
-    let integer_cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![integer_field_ty],
-        vec![byte_array],
-        vec![],
-        0,
-    );
-    integer_cast_op.deref_mut(ctx).set_loc(loc.clone());
-    MirCastOp::new(integer_cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::Transmute);
-    integer_cast_op.insert_after(ctx, array_op);
-    let integer_value = integer_cast_op.deref(ctx).get_result(0);
-
-    let undef_op = MirUndefOp::new(ctx, union_ty).get_operation();
-    undef_op.deref_mut(ctx).set_loc(loc.clone());
-    undef_op.insert_after(ctx, integer_cast_op);
-    let undef_value = undef_op.deref(ctx).get_result(0);
-
-    let insert_op = Operation::new(
-        ctx,
-        MirInsertFieldOp::get_concrete_op_info(),
-        vec![union_ty],
-        vec![undef_value, integer_value],
-        vec![],
-        0,
-    );
-    insert_op.deref_mut(ctx).set_loc(loc);
-    MirInsertFieldOp::new(insert_op).set_attr_insert_index(
-        ctx,
-        dialect_mir::attributes::FieldIndexAttr(integer_field_index as u32),
-    );
-    insert_op.insert_after(ctx, undef_op);
-
-    Ok((insert_op.deref(ctx).get_result(0), Some(insert_op)))
-}
-
-/// Build the exact `[u8; size]` SSA image used by constant-storage
-/// reconstruction. `None` bytes remain `mir.undef`.
-fn translate_constant_storage_byte_array(
-    ctx: &mut Context,
-    storage: &[Option<u8>],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> (Value, Ptr<Operation>) {
-    debug_assert!(!storage.is_empty());
-
-    let byte_ty = IntegerType::get(ctx, 8, Signedness::Unsigned);
-    let byte_ty_handle: TypeHandle = byte_ty.into();
-    let mut bytes = Vec::with_capacity(storage.len());
-    let mut current_prev_op = prev_op;
-
-    for byte in storage {
-        let op = match byte {
-            Some(value) => {
-                let attr = pliron::builtin::attributes::IntegerAttr::new(
-                    byte_ty,
-                    APInt::from_u64(
-                        u64::from(*value),
-                        NonZeroUsize::new(8).expect("u8 width is non-zero"),
-                    ),
-                );
-                let op = Operation::new(
-                    ctx,
-                    MirConstantOp::get_concrete_op_info(),
-                    vec![byte_ty_handle],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                MirConstantOp::new(op).set_attr_value(ctx, attr);
-                op
-            }
-            None => MirUndefOp::new(ctx, byte_ty_handle).get_operation(),
-        };
-        op.deref_mut(ctx).set_loc(loc.clone());
-        match current_prev_op {
-            Some(prev) => op.insert_after(ctx, prev),
-            None => op.insert_at_front(block_ptr, ctx),
-        }
-        bytes.push(op.deref(ctx).get_result(0));
-        current_prev_op = Some(op);
-    }
-
-    let byte_array_ty: TypeHandle =
-        dialect_mir::types::MirArrayType::get(ctx, byte_ty_handle, storage.len() as u64).into();
-    let array_op = Operation::new(
-        ctx,
-        MirConstructArrayOp::get_concrete_op_info(),
-        vec![byte_array_ty],
-        bytes,
-        vec![],
-        0,
-    );
-    array_op.deref_mut(ctx).set_loc(loc.clone());
-    match current_prev_op {
-        Some(prev) => array_op.insert_after(ctx, prev),
-        None => array_op.insert_at_front(block_ptr, ctx),
-    }
-    (array_op.deref(ctx).get_result(0), array_op)
-}
-
-/// Translate an enum constant by reconstructing both its active variant and any
-/// payload operands from the constant's allocation.
-///
-/// Pointer-bearing enums must retain the outer allocation: the bytes stored in a
-/// rustc relocation slot are only an addend, while the provenance map identifies
-/// the target allocation. Following the first relocation here would replace the
-/// enum's storage image with its pointee and lose both the tag and other fields.
-fn translate_enum_constant(
-    ctx: &mut Context,
-    constant: &mir::ConstOperand,
-    rust_ty: &rustc_public::ty::Ty,
-    const_ty_ptr: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    if let Some(allocation) = constant_allocation(constant) {
-        return translate_enum_constant_from_alloc(
-            ctx,
-            allocation,
-            0,
-            rust_ty,
-            const_ty_ptr,
-            block_ptr,
-            prev_op,
-            loc,
-        );
-    }
-
-    let enum_size = rust_type_layout_size(*rust_ty, loc.clone())?;
-    if enum_size != 0 {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Enum constant of {enum_size} byte(s) must be backed by an allocation, found {:?}",
-                constant.const_.kind()
-            ))
-        );
-    }
-
-    translate_enum_constant_from_bytes(ctx, rust_ty, const_ty_ptr, &[], block_ptr, prev_op, loc)
-}
-
-/// Translate an enum constant while retaining rustc's provenance map.
-fn translate_enum_constant_from_alloc(
-    ctx: &mut Context,
-    alloc: &rustc_public::ty::Allocation,
-    base_offset: usize,
-    rust_ty: &rustc_public::ty::Ty,
-    const_ty_ptr: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let enum_size = rust_type_layout_size(*rust_ty, loc.clone())?;
-    let enum_bytes =
-        alloc_slice_bytes_zeroing_uninit(alloc, base_offset, enum_size, "Enum constant", &loc)?;
-
-    translate_enum_constant_from_storage(
-        ctx,
-        rust_ty,
-        const_ty_ptr,
-        &enum_bytes,
-        Some((alloc, base_offset)),
-        block_ptr,
-        prev_op,
-        loc,
-    )
-}
-
-/// Translate an enum value from raw bytes plus the Rust type/layout metadata.
-fn translate_enum_constant_from_bytes(
-    ctx: &mut Context,
-    rust_ty: &rustc_public::ty::Ty,
-    const_ty_ptr: TypeHandle,
-    enum_bytes: &[u8],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    translate_enum_constant_from_storage(
-        ctx,
-        rust_ty,
-        const_ty_ptr,
-        enum_bytes,
-        None,
-        block_ptr,
-        prev_op,
-        loc,
-    )
-}
-
-/// Shared enum decoder. When `allocation` is present, direct thin-pointer
-/// fields are reconstructed from rustc relocations and niche selection can
-/// distinguish a relocated pointer from the all-zero placeholder bytes.
-#[allow(clippy::too_many_arguments)]
-fn translate_enum_constant_from_storage(
-    ctx: &mut Context,
-    rust_ty: &rustc_public::ty::Ty,
-    const_ty_ptr: TypeHandle,
-    enum_bytes: &[u8],
-    allocation: Option<(&rustc_public::ty::Allocation, usize)>,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let enum_variant = {
-        let ty_obj = const_ty_ptr.deref(ctx);
-        let enum_ty = ty_obj
-            .downcast_ref::<dialect_mir::types::MirEnumType>()
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(
-                    "translate_enum_constant_from_storage called on non-enum type"
-                ))
-            })?;
-
-        let variant_index = match allocation {
-            Some((alloc, base_offset)) => {
-                enum_variant_index_from_alloc(rust_ty, enum_bytes, alloc, base_offset, loc.clone())?
-            }
-            None => enum_variant_index_from_bytes(rust_ty, enum_bytes, loc.clone())?,
-        };
-        let variant = enum_ty.get_variant(variant_index).ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Enum constant resolved to variant index {} outside translated MIR enum '{}'",
-                variant_index,
-                enum_ty.name()
-            )))
-        })?;
-        (variant_index, variant)
-    };
-    let variant_index = enum_variant.0;
-    let variant = enum_variant.1;
-
-    let mut field_values = Vec::with_capacity(variant.field_types.len());
-    let mut field_ranges = Vec::with_capacity(variant.field_types.len());
-    let mut current_prev_op = prev_op;
-
-    if !variant.field_types.is_empty() {
-        use rustc_public::ty::{RigidTy, TyKind};
-
-        let layout = rust_ty.layout().map_err(|e| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Failed to query layout for enum constant: {:?}",
-                e
-            )))
-        })?;
-        let field_offsets =
-            enum_variant_field_offsets(&layout.shape(), variant_index, loc.clone())?;
-
-        let (adt_def, substs) = match rust_ty.kind() {
-            TyKind::RigidTy(RigidTy::Adt(adt_def, substs)) => (adt_def, substs),
-            other => {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Expected ADT Rust type for enum constant, got {:?}",
-                        other
-                    ))
-                );
-            }
-        };
-        let rust_variant = &adt_def.variants()[variant_index];
-
-        for (field_idx, field_ty_ptr) in variant.field_types.iter().copied().enumerate() {
-            let rust_field_ty = rust_variant.fields()[field_idx].ty_with_args(&substs);
-            let field_layout = rust_field_ty.layout().map_err(|e| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Failed to query layout for enum field {} of variant '{}': {:?}",
-                    field_idx,
-                    rust_variant.name(),
-                    e
-                )))
-            })?;
-            let field_offset = *field_offsets.get(field_idx).ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Missing layout offset for enum field {} of variant '{}'",
-                    field_idx,
-                    rust_variant.name()
-                )))
-            })?;
-            let field_size = field_layout.shape().size.bytes() as usize;
-            let field_end = field_offset.checked_add(field_size).ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Enum field {} of variant '{}' overflowed offset computation",
-                    field_idx,
-                    rust_variant.name()
-                )))
-            })?;
-
-            if field_end > enum_bytes.len() {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Enum constant for variant '{}' has {} bytes, but field {} needs [{}..{})",
-                        rust_variant.name(),
-                        enum_bytes.len(),
-                        field_idx,
-                        field_offset,
-                        field_end
-                    ))
-                );
-            }
-
-            let (field_val, new_prev_op) = match allocation {
-                Some((alloc, base_offset)) => {
-                    let absolute_field_offset =
-                        base_offset.checked_add(field_offset).ok_or_else(|| {
-                            input_error_noloc!(TranslationErr::unsupported(format!(
-                                "Enum field {} of variant '{}' overflowed absolute offset computation",
-                                field_idx,
-                                rust_variant.name()
-                            )))
-                        })?;
-                    field_ranges.push((absolute_field_offset, field_size));
-                    translate_constant_value_from_alloc(
-                        ctx,
-                        alloc,
-                        absolute_field_offset,
-                        &rust_field_ty,
-                        field_ty_ptr,
-                        block_ptr,
-                        current_prev_op,
-                        loc.clone(),
-                    )?
-                }
-                None => {
-                    let field_bytes = &enum_bytes[field_offset..field_end];
-                    translate_constant_value_from_bytes(
-                        ctx,
-                        &rust_field_ty,
-                        field_ty_ptr,
-                        field_bytes,
-                        block_ptr,
-                        current_prev_op,
-                        loc.clone(),
-                    )?
-                }
-            };
-            field_values.push(field_val);
-            current_prev_op = new_prev_op;
-        }
-
-        let (casted_field_values, prev_after_casts) = cast_enum_fields_to_expected_types(
-            ctx,
-            field_values,
-            const_ty_ptr,
-            variant_index,
-            block_ptr,
-            current_prev_op,
-            loc.clone(),
-        );
-        field_values = casted_field_values;
-        current_prev_op = prev_after_casts;
-    }
-
-    if let Some((alloc, base_offset)) = allocation {
-        let enum_size = rust_type_layout_size(*rust_ty, loc.clone())?;
-        audit_aggregate_relocations(alloc, base_offset, enum_size, &field_ranges, "Enum", &loc)?;
-    }
-
-    let op = Operation::new(
-        ctx,
-        MirConstructEnumOp::get_concrete_op_info(),
-        vec![const_ty_ptr],
-        field_values,
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc.clone());
-
-    let enum_op = MirConstructEnumOp::new(op);
-    enum_op.set_attr_construct_enum_variant_index(
-        ctx,
-        dialect_mir::attributes::VariantIndexAttr(variant_index as u32),
-    );
-
-    if let Some(prev) = current_prev_op {
-        enum_op.get_operation().insert_after(ctx, prev);
-    } else {
-        enum_op.get_operation().insert_at_front(block_ptr, ctx);
-    }
-
-    let val = enum_op.get_operation().deref(ctx).get_result(0);
-
-    Ok((val, Some(enum_op.get_operation())))
-}
-
-/// Translate a struct value from raw bytes plus the Rust type/layout metadata.
-///
-/// This is the byte-slice counterpart to [`translate_struct_constant`] and is
-/// used whenever a constant field has a struct type (e.g. `NonZero<T>` wrappers
-/// inside enum payloads). Each field is parsed recursively so nested newtypes
-/// are handled automatically.
-fn translate_struct_constant_from_bytes(
-    ctx: &mut Context,
-    rust_ty: &rustc_public::ty::Ty,
-    const_ty_ptr: TypeHandle,
-    struct_bytes: &[u8],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    use rustc_public::ty::{RigidTy, TyKind};
-
-    let field_types: Vec<TypeHandle> = {
-        let ty_obj = const_ty_ptr.deref(ctx);
-        let struct_ty = ty_obj
-            .downcast_ref::<dialect_mir::types::MirStructType>()
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(
-                    "translate_struct_constant_from_bytes called on non-struct type"
-                ))
-            })?;
-        struct_ty.field_types().to_vec()
-    };
-
-    let layout = rust_ty.layout().map_err(|e| {
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "Failed to query layout for struct constant: {:?}",
-            e
-        )))
-    })?;
-    let shape = layout.shape();
-
-    // A zero-sized struct span holds no bytes and cannot carry relocations,
-    // and not every type that lands here as a MirStructType is an ADT:
-    // function items and non-capturing closures have no ADT metadata to
-    // consult. Synthesize such values from the dialect type alone.
-    if shape.size.bytes() == 0 {
-        return translate_zero_sized_constant_value(ctx, const_ty_ptr, block_ptr, prev_op, loc);
-    }
-
-    let field_offsets: Vec<usize> = match &shape.fields {
-        rustc_public::abi::FieldsShape::Arbitrary { offsets } => {
-            offsets.iter().map(|offset| offset.bytes()).collect()
-        }
-        rustc_public::abi::FieldsShape::Primitive => vec![0; field_types.len()],
-        rustc_public::abi::FieldsShape::Union { .. } => vec![0; field_types.len()],
-        other => {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Struct constant fields use unsupported shape {:?}",
-                    other
-                ))
-            );
-        }
-    };
-
-    let (adt_def, substs) = match rust_ty.kind() {
-        TyKind::RigidTy(RigidTy::Adt(adt_def, substs)) => (adt_def, substs),
-        other => {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Expected ADT Rust type for struct constant, got {:?}",
-                    other
-                ))
-            );
-        }
-    };
-
-    // Structs have a single variant in the ADT metadata.
-    let variants = adt_def.variants();
-    let struct_variant = variants.first().ok_or_else(|| {
-        input_error_noloc!(TranslationErr::unsupported(
-            "Struct ADT has no variants in metadata"
-        ))
-    })?;
-
-    let mut field_values = Vec::with_capacity(field_types.len());
-    let mut current_prev_op = prev_op;
-
-    for (field_idx, field_ty_ptr) in field_types.iter().copied().enumerate() {
-        let fields = struct_variant.fields();
-        let rust_field = fields.get(field_idx).ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Struct constant field {} is missing in rustc ADT metadata ({} field(s) recorded)",
-                field_idx,
-                fields.len()
-            )))
-        })?;
-        let rust_field_ty = rust_field.ty_with_args(&substs);
-        let field_layout = rust_field_ty.layout().map_err(|e| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Failed to query layout for struct field {}: {:?}",
-                field_idx, e
-            )))
-        })?;
-        let field_size = field_layout.shape().size.bytes();
-        let field_offset = *field_offsets.get(field_idx).ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Missing layout offset for struct field {}",
-                field_idx
-            )))
-        })?;
-
-        if field_size == 0 {
-            let (zst_val, new_prev_op) = translate_zero_sized_constant_value(
-                ctx,
-                field_ty_ptr,
-                block_ptr,
-                current_prev_op,
-                loc.clone(),
-            )?;
-            field_values.push(zst_val);
-            current_prev_op = new_prev_op;
-            continue;
-        }
-
-        let field_end = field_offset.checked_add(field_size).ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Struct field {} offset {} + size {} overflowed",
-                field_idx, field_offset, field_size
-            )))
-        })?;
-        if field_end > struct_bytes.len() {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Struct constant has {} bytes, but field {} needs [{}..{})",
-                    struct_bytes.len(),
-                    field_idx,
-                    field_offset,
-                    field_end
-                ))
-            );
-        }
-
-        let field_bytes = &struct_bytes[field_offset..field_end];
-        let (field_val, new_prev_op) = translate_constant_value_from_bytes(
-            ctx,
-            &rust_field_ty,
-            field_ty_ptr,
-            field_bytes,
-            block_ptr,
-            current_prev_op,
-            loc.clone(),
-        )?;
-        field_values.push(field_val);
-        current_prev_op = new_prev_op;
-    }
-
-    let (casted_field_values, prev_after_casts) = cast_struct_fields_to_expected_types(
-        ctx,
-        field_values,
-        const_ty_ptr,
-        block_ptr,
-        current_prev_op,
-        loc.clone(),
-    );
-
-    let op = Operation::new(
-        ctx,
-        MirConstructStructOp::get_concrete_op_info(),
-        vec![const_ty_ptr],
-        casted_field_values,
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc.clone());
-
-    if let Some(prev) = prev_after_casts {
-        op.insert_after(ctx, prev);
-    } else {
-        op.insert_at_front(block_ptr, ctx);
-    }
-
-    Ok((op.deref(ctx).get_result(0), Some(op)))
-}
-
-/// Translate one field-sized byte slice into a constant value.
-fn translate_constant_value_from_bytes(
-    ctx: &mut Context,
-    rust_ty: &rustc_public::ty::Ty,
-    ty_ptr: TypeHandle,
-    bytes: &[u8],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let is_enum = {
-        let ty_ref = ty_ptr.deref(ctx);
-        ty_ref.is::<dialect_mir::types::MirEnumType>()
-    };
-    if is_enum {
-        return translate_enum_constant_from_bytes(
-            ctx, rust_ty, ty_ptr, bytes, block_ptr, prev_op, loc,
-        );
-    }
-
-    // Aggregate decoders own their complete field model, including non-empty
-    // aggregates whose every field is zero-sized. Dispatch them before the
-    // generic ZST synthesizer, which only has the translated type and cannot
-    // recover a Rust aggregate's active variant or field metadata.
-    if ty_ptr.deref(ctx).is::<dialect_mir::types::MirTupleType>() {
-        return translate_tuple_constant_from_bytes(
-            ctx, rust_ty, ty_ptr, bytes, block_ptr, prev_op, loc,
-        );
-    }
-
-    // Struct-typed constants (e.g. `NonZero<T>` wrappers inside enum payloads)
-    // need per-field construction rather than a single scalar constant.
-    let is_struct = {
-        let ty_ref = ty_ptr.deref(ctx);
-        ty_ref.is::<dialect_mir::types::MirStructType>()
-    };
-    if is_struct {
-        return translate_struct_constant_from_bytes(
-            ctx, rust_ty, ty_ptr, bytes, block_ptr, prev_op, loc,
-        );
-    }
-
-    let is_zst = rust_ty
-        .layout()
-        .map(|layout| layout.shape().is_1zst())
-        .map_err(|error| {
-            input_error!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Failed to query layout for aggregate constant field {rust_ty:?}: {error:?}"
-                ))
-            )
-        })?;
-    if is_zst || types::is_zst_type(ctx, ty_ptr) {
-        return translate_zero_sized_constant_value(ctx, ty_ptr, block_ptr, prev_op, loc);
-    }
-
-    if ty_ptr.deref(ctx).is::<dialect_mir::types::MirUnionType>() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(
-                "Initialized union constants require their rustc allocation so the initialization mask is preserved; byte-only union decoding is not supported"
-                    .to_string()
-            )
-        );
-    }
-
-    enum ValueKind {
-        Integer { width: u32, signedness: Signedness },
-        Float16,
-        Float32,
-        Float64,
-        Pointer,
-        Unsupported(String),
-    }
-
-    let value_kind = {
-        let ty_ref = ty_ptr.deref(ctx);
-        if let Some(int_ty) = ty_ref.downcast_ref::<IntegerType>() {
-            ValueKind::Integer {
-                width: int_ty.width(),
-                signedness: int_ty.signedness(),
-            }
-        } else if ty_ref.is::<MirFP16Type>() {
-            ValueKind::Float16
-        } else if ty_ref.is::<FP32Type>() {
-            ValueKind::Float32
-        } else if ty_ref.is::<FP64Type>() {
-            ValueKind::Float64
-        } else if ty_ref.is::<dialect_mir::types::MirPtrType>() {
-            ValueKind::Pointer
-        } else {
-            ValueKind::Unsupported(format!("{:?}", ty_ref))
-        }
-    };
-
-    match value_kind {
-        ValueKind::Integer { width, signedness } => {
-            let byte_size = (width as usize).div_ceil(8);
-            if bytes.len() < byte_size {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Integer constant needs {} bytes, found {}",
-                        byte_size,
-                        bytes.len()
-                    ))
-                );
-            }
-
-            let int_val = read_uint_from_bytes(&bytes[..byte_size]);
-            let width_nz = NonZeroUsize::new(width as usize).unwrap();
-            let apint = APInt::from_u128(int_val, width_nz);
-            let int_attr = pliron::builtin::attributes::IntegerAttr::new(
-                IntegerType::get(ctx, width, signedness),
-                apint,
-            );
-
-            use dialect_mir::ops::MirConstantOp;
-            let op = Operation::new(
-                ctx,
-                MirConstantOp::get_concrete_op_info(),
-                vec![ty_ptr],
-                vec![],
-                vec![],
-                0,
-            );
-            op.deref_mut(ctx).set_loc(loc.clone());
-            let const_op = MirConstantOp::new(op);
-            const_op.set_attr_value(ctx, int_attr);
-
-            if let Some(prev) = prev_op {
-                const_op.get_operation().insert_after(ctx, prev);
-            } else {
-                const_op.get_operation().insert_at_front(block_ptr, ctx);
-            }
-
-            Ok((
-                const_op.get_operation().deref(ctx).get_result(0),
-                Some(const_op.get_operation()),
-            ))
-        }
-        ValueKind::Float16 => {
-            if bytes.len() < 2 {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "f16 constant needs 2 bytes, found {}",
-                        bytes.len()
-                    ))
-                );
-            }
-
-            let bits = read_uint_from_bytes(&bytes[..2]) as u16;
-            let float_attr = MirFP16Attr::from_bits(bits);
-
-            use dialect_mir::ops::MirFloatConstantOp;
-            let op = Operation::new(
-                ctx,
-                MirFloatConstantOp::get_concrete_op_info(),
-                vec![ty_ptr],
-                vec![],
-                vec![],
-                0,
-            );
-            op.deref_mut(ctx).set_loc(loc.clone());
-            let float_op = MirFloatConstantOp::new(op);
-            float_op.set_attr_float_value_f16(ctx, float_attr);
-
-            if let Some(prev) = prev_op {
-                float_op.get_operation().insert_after(ctx, prev);
-            } else {
-                float_op.get_operation().insert_at_front(block_ptr, ctx);
-            }
-
-            Ok((
-                float_op.get_operation().deref(ctx).get_result(0),
-                Some(float_op.get_operation()),
-            ))
-        }
-        ValueKind::Float32 => {
-            if bytes.len() < 4 {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "f32 constant needs 4 bytes, found {}",
-                        bytes.len()
-                    ))
-                );
-            }
-
-            let mut field_bytes = [0u8; 4];
-            field_bytes.copy_from_slice(&bytes[..4]);
-            let float_val = match rustc_public::target::MachineInfo::target_endianness() {
-                rustc_public::target::Endian::Little => f32::from_le_bytes(field_bytes),
-                rustc_public::target::Endian::Big => f32::from_be_bytes(field_bytes),
-            };
-            let float_attr = pliron::builtin::attributes::FPSingleAttr::from(float_val);
-
-            use dialect_mir::ops::MirFloatConstantOp;
-            let op = Operation::new(
-                ctx,
-                MirFloatConstantOp::get_concrete_op_info(),
-                vec![ty_ptr],
-                vec![],
-                vec![],
-                0,
-            );
-            op.deref_mut(ctx).set_loc(loc.clone());
-            let float_op = MirFloatConstantOp::new(op);
-            float_op.set_attr_float_value(ctx, float_attr);
-
-            if let Some(prev) = prev_op {
-                float_op.get_operation().insert_after(ctx, prev);
-            } else {
-                float_op.get_operation().insert_at_front(block_ptr, ctx);
-            }
-
-            Ok((
-                float_op.get_operation().deref(ctx).get_result(0),
-                Some(float_op.get_operation()),
-            ))
-        }
-        ValueKind::Float64 => {
-            if bytes.len() < 8 {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "f64 constant needs 8 bytes, found {}",
-                        bytes.len()
-                    ))
-                );
-            }
-
-            let mut field_bytes = [0u8; 8];
-            field_bytes.copy_from_slice(&bytes[..8]);
-            let float_val = match rustc_public::target::MachineInfo::target_endianness() {
-                rustc_public::target::Endian::Little => f64::from_le_bytes(field_bytes),
-                rustc_public::target::Endian::Big => f64::from_be_bytes(field_bytes),
-            };
-            let float_attr = pliron::builtin::attributes::FPDoubleAttr::from(float_val);
-
-            use dialect_mir::ops::MirFloatConstantOp;
-            let op = Operation::new(
-                ctx,
-                MirFloatConstantOp::get_concrete_op_info(),
-                vec![ty_ptr],
-                vec![],
-                vec![],
-                0,
-            );
-            op.deref_mut(ctx).set_loc(loc.clone());
-            let float_op = MirFloatConstantOp::new(op);
-            float_op.set_attr_float_value_f64(ctx, float_attr);
-
-            if let Some(prev) = prev_op {
-                float_op.get_operation().insert_after(ctx, prev);
-            } else {
-                float_op.get_operation().insert_at_front(block_ptr, ctx);
-            }
-
-            Ok((
-                float_op.get_operation().deref(ctx).get_result(0),
-                Some(float_op.get_operation()),
-            ))
-        }
-        ValueKind::Pointer => {
-            let pointer_bytes = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-            if bytes.len() < pointer_bytes {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Pointer constant needs {} bytes, found {}",
-                        pointer_bytes,
-                        bytes.len()
-                    ))
-                );
-            }
-
-            let ptr_val = read_uint_from_bytes(&bytes[..pointer_bytes]) as u64;
-            let i64_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);
-            let apint = APInt::from_u64(ptr_val, NonZeroUsize::new(64).unwrap());
-            let int_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, apint);
-
-            use dialect_mir::ops::MirConstantOp;
-            let int_op = Operation::new(
-                ctx,
-                MirConstantOp::get_concrete_op_info(),
-                vec![i64_ty.into()],
-                vec![],
-                vec![],
-                0,
-            );
-            int_op.deref_mut(ctx).set_loc(loc.clone());
-            let const_op = MirConstantOp::new(int_op);
-            const_op.set_attr_value(ctx, int_attr);
-
-            if let Some(prev) = prev_op {
-                const_op.get_operation().insert_after(ctx, prev);
-            } else {
-                const_op.get_operation().insert_at_front(block_ptr, ctx);
-            }
-
-            let const_value = const_op.get_operation().deref(ctx).get_result(0);
-            let cast_op = Operation::new(
-                ctx,
-                MirCastOp::get_concrete_op_info(),
-                vec![ty_ptr],
-                vec![const_value],
-                vec![],
-                0,
-            );
-            cast_op.deref_mut(ctx).set_loc(loc.clone());
-            let cast = MirCastOp::new(cast_op);
-            cast.set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
-            if dialect_mir::types::type_contains_concrete_pointer_kind(ctx, ty_ptr) {
-                cast.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::StaticAddress);
-            }
-            cast_op.insert_after(ctx, const_op.get_operation());
-
-            Ok((cast_op.deref(ctx).get_result(0), Some(cast_op)))
-        }
-        ValueKind::Unsupported(ty_name) => input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Aggregate constant field type is not yet supported: {}",
-                ty_name
-            ))
-        ),
-    }
-}
-
-/// Build a zero-sized value while preserving its exact translated type.
-fn translate_zero_sized_constant_value(
-    ctx: &mut Context,
-    ty_ptr: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    enum ZeroSizedKind {
-        Struct,
-        EmptyTuple,
-        Union,
-        Unsupported(String),
-    }
-
-    let zero_sized_kind = {
-        let ty_ref = ty_ptr.deref(ctx);
-        if ty_ref.is::<dialect_mir::types::MirStructType>() {
-            ZeroSizedKind::Struct
-        } else if ty_ref.is::<dialect_mir::types::MirUnionType>() {
-            ZeroSizedKind::Union
-        } else if let Some(tuple_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirTupleType>() {
-            if tuple_ty.get_types().is_empty() {
-                ZeroSizedKind::EmptyTuple
-            } else {
-                ZeroSizedKind::Unsupported(
-                    "Only empty tuple constants can be synthesized as zero-sized values"
-                        .to_string(),
-                )
-            }
-        } else {
-            ZeroSizedKind::Unsupported(format!(
-                "Zero-sized constant synthesis does not support type {:?}",
-                ty_ref
-            ))
-        }
-    };
-
-    // A zero-sized struct can still carry (zero-sized) fields in its type, and
-    // `MirConstructStructOp` requires one operand per field. Recursively
-    // synthesize a ZST value for each field type (e.g. `TryFromIntError(())`,
-    // which surfaces when building `core` for nvptx via `-Zbuild-std`).
-    if matches!(zero_sized_kind, ZeroSizedKind::Struct) {
-        let field_types: Vec<TypeHandle> = {
-            let ty_ref = ty_ptr.deref(ctx);
-            ty_ref
-                .downcast_ref::<dialect_mir::types::MirStructType>()
-                .map(|st| st.field_types.clone())
-                .unwrap_or_default()
-        };
-        let mut operands = Vec::with_capacity(field_types.len());
-        let mut cur_prev = prev_op;
-        for fty in field_types {
-            let (v, np) =
-                translate_zero_sized_constant_value(ctx, fty, block_ptr, cur_prev, loc.clone())?;
-            operands.push(v);
-            cur_prev = np;
-        }
-        let op = Operation::new(
-            ctx,
-            MirConstructStructOp::get_concrete_op_info(),
-            vec![ty_ptr],
-            operands,
-            vec![],
-            0,
-        );
-        op.deref_mut(ctx).set_loc(loc);
-        if let Some(prev) = cur_prev {
-            op.insert_after(ctx, prev);
-        } else {
-            op.insert_at_front(block_ptr, ctx);
-        }
-        return Ok((op.deref(ctx).get_result(0), Some(op)));
-    }
-
-    let op = match zero_sized_kind {
-        ZeroSizedKind::Struct => unreachable!("handled above"),
-        ZeroSizedKind::EmptyTuple => {
-            use dialect_mir::ops::MirConstructTupleOp;
-            Operation::new(
-                ctx,
-                MirConstructTupleOp::get_concrete_op_info(),
-                vec![ty_ptr],
-                vec![],
-                vec![],
-                0,
-            )
-        }
-        ZeroSizedKind::Union => MirUndefOp::new(ctx, ty_ptr).get_operation(),
-        ZeroSizedKind::Unsupported(message) => {
-            return input_err!(loc, TranslationErr::unsupported(message));
-        }
-    };
-    op.deref_mut(ctx).set_loc(loc);
-
-    if let Some(prev) = prev_op {
-        op.insert_after(ctx, prev);
-    } else {
-        op.insert_at_front(block_ptr, ctx);
-    }
-
-    Ok((op.deref(ctx).get_result(0), Some(op)))
-}
-
-/// Translate ADT aggregate operands, synthesizing omitted runtime-ZST fields when
-/// MIR carries only the non-ZST runtime operands.
-fn translate_adt_aggregate_field_values(
-    ctx: &mut Context,
-    body: &mir::Body,
-    adt_def: rustc_public::ty::AdtDef,
-    variant_idx: rustc_public::ty::VariantIdx,
-    substs: &rustc_public::ty::GenericArgs,
-    operands: &[mir::Operand],
-    value_map: &mut ValueMap,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Vec<Value>, Option<Ptr<Operation>>)> {
-    let variant_index = variant_idx.to_index();
-    let variant = &adt_def.variants()[variant_index];
-
-    let mut field_infos = Vec::with_capacity(variant.fields().len());
-    for field in variant.fields() {
-        let field_rust_ty = field.ty_with_args(substs);
-        let translated_ty = types::translate_type(ctx, &field_rust_ty)?;
-        let is_runtime_zst = field_rust_ty
-            .layout()
-            .map(|layout| layout.shape().is_1zst())
-            .unwrap_or(false);
-        field_infos.push((field_rust_ty, translated_ty, is_runtime_zst));
-    }
-
-    let total_field_count = field_infos.len();
-    let non_zst_count = field_infos
-        .iter()
-        .filter(|(_, _, is_runtime_zst)| !*is_runtime_zst)
-        .count();
-
-    let synthesize_runtime_zsts = if operands.len() == total_field_count {
-        false
-    } else if operands.len() == non_zst_count {
-        true
-    } else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "ADT aggregate '{}' variant '{}' has {} translated fields, {} non-ZST runtime fields, but MIR provided {} operands",
-                adt_def.trimmed_name(),
-                variant.name(),
-                total_field_count,
-                non_zst_count,
-                operands.len()
-            ))
-        );
-    };
-
-    let mut field_values = Vec::with_capacity(total_field_count);
-    let mut current_prev_op = prev_op;
-    let mut operand_iter = operands.iter();
-
-    for (field_rust_ty, translated_ty, is_runtime_zst) in field_infos {
-        if synthesize_runtime_zsts && is_runtime_zst {
-            let (value, new_prev_op) = translate_constant_value_from_bytes(
-                ctx,
-                &field_rust_ty,
-                translated_ty,
-                &[],
-                block_ptr,
-                current_prev_op,
-                loc.clone(),
-            )?;
-            field_values.push(value);
-            current_prev_op = new_prev_op;
-            continue;
-        }
-
-        let operand = operand_iter.next().ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "ADT aggregate '{}' variant '{}' ran out of MIR operands while translating fields",
-                adt_def.trimmed_name(),
-                variant.name()
-            )))
-        })?;
-        let (value, new_prev_op) = translate_operand(
-            ctx,
-            body,
-            operand,
-            value_map,
-            block_ptr,
-            current_prev_op,
-            loc.clone(),
-        )?;
-        field_values.push(value);
-        current_prev_op = new_prev_op;
-    }
-
-    if operand_iter.next().is_some() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "ADT aggregate '{}' variant '{}' left unused MIR operands after field translation",
-                adt_def.trimmed_name(),
-                variant.name()
-            ))
-        );
-    }
-
-    Ok((field_values, current_prev_op))
-}
-
-/// Construct a union by writing the one active field into shared storage.
-///
-/// MIR supplies exactly one operand plus the declaration index of its active
-/// field. Start with undefined union storage and use `mir.insert_field` to
-/// write that typed view at byte zero. The union-specific lowering preserves
-/// every other byte as undefined; it never invents one independent slot per
-/// field.
-#[allow(clippy::too_many_arguments)]
-fn translate_union_aggregate(
-    ctx: &mut Context,
-    body: &mir::Body,
-    adt_def: rustc_public::ty::AdtDef,
-    union_ty: TypeHandle,
-    active_field_idx: Option<usize>,
-    operands: &[mir::Operand],
-    value_map: &mut ValueMap,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
-    let active_field_idx = active_field_idx.ok_or_else(|| {
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "Union aggregate '{}' did not identify an active field",
-            adt_def.trimmed_name()
-        )))
-    })?;
-
-    if operands.len() != 1 {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Union aggregate '{}' expected exactly one operand for active field {}, found {}",
-                adt_def.trimmed_name(),
-                active_field_idx,
-                operands.len()
-            ))
-        );
-    }
-
-    let (field_count, expected_field_ty) = {
-        let ty_ref = union_ty.deref(ctx);
-        let union = ty_ref
-            .downcast_ref::<dialect_mir::types::MirUnionType>()
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Union aggregate '{}' did not translate to MirUnionType",
-                    adt_def.trimmed_name()
-                )))
-            })?;
-        (union.field_count(), union.get_field_type(active_field_idx))
-    };
-    if active_field_idx >= field_count {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Union aggregate '{}' active field {} is out of bounds for {} fields",
-                adt_def.trimmed_name(),
-                active_field_idx,
-                field_count
-            ))
-        );
-    }
-    let expected_field_ty = expected_field_ty.expect("active union field was bounds-checked");
-
-    let (active_value, current_prev_op) = translate_operand(
-        ctx,
-        body,
-        &operands[0],
-        value_map,
-        block_ptr,
-        prev_op,
-        loc.clone(),
-    )?;
-    let (active_value, current_prev_op) = cast_to_expected_pointer_type_if_needed(
-        ctx,
-        active_value,
-        expected_field_ty,
-        block_ptr,
-        current_prev_op,
-        loc.clone(),
-    );
-
-    let undef_op = MirUndefOp::new(ctx, union_ty).get_operation();
-    undef_op.deref_mut(ctx).set_loc(loc.clone());
-    if let Some(prev) = current_prev_op {
-        undef_op.insert_after(ctx, prev);
-    } else {
-        undef_op.insert_at_front(block_ptr, ctx);
-    }
-    let undef_value = undef_op.deref(ctx).get_result(0);
-
-    let insert_op = Operation::new(
-        ctx,
-        MirInsertFieldOp::get_concrete_op_info(),
-        vec![union_ty],
-        vec![undef_value, active_value],
-        vec![],
-        0,
-    );
-    insert_op.deref_mut(ctx).set_loc(loc);
-    MirInsertFieldOp::new(insert_op).set_attr_insert_index(
-        ctx,
-        dialect_mir::attributes::FieldIndexAttr(active_field_idx as u32),
-    );
-    let result = insert_op.deref(ctx).get_result(0);
-
-    Ok((Some(insert_op), result, Some(undef_op)))
-}
-
-/// Fetch the raw bytes backing a constant, following provenance for promoted
-/// aggregate constants when necessary.
-pub(crate) fn constant_bytes(
-    constant: &mir::ConstOperand,
-    kind_name: &str,
-    loc: Location,
-) -> TranslationResult<Vec<u8>> {
-    use rustc_public::ty::TyConstKind;
-
-    fn allocation_bytes_zeroing_uninit(alloc: &rustc_public::ty::Allocation) -> Vec<u8> {
-        alloc.raw_bytes().ok().unwrap_or_else(|| {
-            alloc
-                .bytes
-                .iter()
-                .map(|opt: &Option<u8>| opt.unwrap_or(0))
-                .collect::<Vec<u8>>()
-        })
-    }
-
-    fn allocation_bytes(
-        alloc: &rustc_public::ty::Allocation,
-        kind_name: &str,
-        loc: Location,
-    ) -> TranslationResult<Vec<u8>> {
-        use rustc_public::mir::alloc::GlobalAlloc;
-
-        if let Some((_, prov)) = alloc.provenance.ptrs.first() {
-            let alloc_id = prov.0;
-            match GlobalAlloc::from(alloc_id) {
-                GlobalAlloc::Memory(target_alloc) => {
-                    Ok(allocation_bytes_zeroing_uninit(&target_alloc))
-                }
-                GlobalAlloc::Static(static_def) => {
-                    let target_alloc = static_def.eval_initializer().map_err(|e| {
-                        input_error_noloc!(TranslationErr::unsupported(format!(
-                            "Failed to evaluate static initializer for {} constant: {:?}",
-                            kind_name, e
-                        )))
-                    })?;
-                    Ok(allocation_bytes_zeroing_uninit(&target_alloc))
-                }
-                other => input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "{} constant provenance points to non-memory allocation: {:?}",
-                        kind_name, other
-                    ))
-                ),
-            }
-        } else {
-            Ok(allocation_bytes_zeroing_uninit(alloc))
-        }
-    }
-
-    match constant.const_.kind() {
-        ConstantKind::Allocated(alloc) => allocation_bytes(alloc, kind_name, loc),
-        ConstantKind::Ty(ty_const) => match ty_const.kind() {
-            TyConstKind::Value(_, alloc) => allocation_bytes(alloc, kind_name, loc),
-            TyConstKind::ZSTValue(_) => Ok(vec![]),
-            other => input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "{} constant must be backed by bytes, found TyConstKind::{:?}",
-                    kind_name, other
-                ))
-            ),
-        },
-        ConstantKind::ZeroSized => Ok(vec![]),
-        other => input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "{} constant must be Allocated or Ty::Value, got {:?}",
-                kind_name, other
-            ))
-        ),
-    }
-}
-
-/// Determine the active enum variant from layout metadata plus raw bytes.
-fn decode_niche_variant_index(
-    tag_value: u128,
-    carrier_mask: u128,
-    niche_start: u128,
-    niche_variant_start: usize,
-    niche_variant_end: usize,
-    untagged_variant: usize,
-) -> usize {
-    let relative = tag_value.wrapping_sub(niche_start) & carrier_mask;
-    let span = (niche_variant_end - niche_variant_start) as u128;
-
-    // Compare at the full physical carrier width. Converting `relative` to
-    // host usize before this check can turn 2^64 into zero on a 64-bit host
-    // and select the wrong variant for an i128 carrier.
-    if relative <= span {
-        niche_variant_start + relative as usize
-    } else {
-        untagged_variant
-    }
-}
-
-fn enum_variant_index_from_bytes(
-    rust_ty: &rustc_public::ty::Ty,
-    enum_bytes: &[u8],
-    loc: Location,
-) -> TranslationResult<usize> {
-    enum_variant_index_from_storage(rust_ty, enum_bytes, None, loc)
-}
-
-fn enum_variant_index_from_alloc(
-    rust_ty: &rustc_public::ty::Ty,
-    enum_bytes: &[u8],
-    alloc: &rustc_public::ty::Allocation,
-    base_offset: usize,
-    loc: Location,
-) -> TranslationResult<usize> {
-    enum_variant_index_from_storage(rust_ty, enum_bytes, Some((alloc, base_offset)), loc)
-}
-
-/// Determine the active enum variant from layout metadata, raw bytes, and
-/// optionally the provenance map of the enclosing allocation.
-///
-/// A niche-encoded pointer enum such as `Option<&T>` stores its carrier in the
-/// pointer word itself. rustc leaves addend bytes in that word and records the
-/// target separately as a relocation, so all-zero bytes do not mean the niche
-/// variant when a full-width relocation covers the carrier.
-fn enum_variant_index_from_storage(
-    rust_ty: &rustc_public::ty::Ty,
-    enum_bytes: &[u8],
-    allocation: Option<(&rustc_public::ty::Allocation, usize)>,
-    loc: Location,
-) -> TranslationResult<usize> {
-    let layout = rust_ty.layout().map_err(|e| {
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "Failed to query enum layout: {:?}",
-            e
-        )))
-    })?;
-    let shape = layout.shape();
-
-    match &shape.variants {
-        rustc_public::abi::VariantsShape::Single { index } => Ok(index.to_index()),
-        rustc_public::abi::VariantsShape::Empty => input_err!(
-            loc,
-            TranslationErr::unsupported("Cannot materialize a constant for an uninhabited enum")
-        ),
-        rustc_public::abi::VariantsShape::Multiple {
-            tag,
-            tag_encoding,
-            tag_field,
-            ..
-        } => {
-            let primitive = match tag {
-                rustc_public::abi::Scalar::Initialized { value, .. }
-                | rustc_public::abi::Scalar::Union { value } => *value,
-            };
-            let scalar_size = primitive.size(&rustc_public::target::MachineInfo::target());
-            let mask = scalar_size.unsigned_int_max().ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Enum tag width {} exceeds 128 bits",
-                    scalar_size.bits()
-                )))
-            })?;
-
-            if let Some((alloc, base_offset)) = allocation {
-                let (relative_tag_offset, tag_size) =
-                    enum_tag_byte_range(&shape.fields, *tag_field, *tag, loc.clone())?;
-                let absolute_tag_offset =
-                    base_offset
-                        .checked_add(relative_tag_offset)
-                        .ok_or_else(|| {
-                            input_error_noloc!(TranslationErr::unsupported(
-                                "Enum tag absolute offset overflowed"
-                            ))
-                        })?;
-                let absolute_tag_end =
-                    absolute_tag_offset.checked_add(tag_size).ok_or_else(|| {
-                        input_error_noloc!(TranslationErr::unsupported(
-                            "Enum tag absolute range overflowed"
-                        ))
-                    })?;
-                let pointer_width =
-                    rustc_public::target::MachineInfo::target_pointer_width().bytes();
-                let overlaps = relocation_offsets_overlapping_range(
-                    &alloc.provenance.ptrs,
-                    absolute_tag_offset,
-                    absolute_tag_end,
-                    pointer_width,
-                );
-
-                if !overlaps.is_empty() {
-                    if let rustc_public::abi::TagEncoding::Niche {
-                        untagged_variant, ..
-                    } = tag_encoding
-                        && tag_size == pointer_width
-                        && overlaps.len() == 1
-                        && overlaps[0] == absolute_tag_offset
-                    {
-                        return Ok(untagged_variant.to_index());
-                    }
-
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "Enum tag bytes [{absolute_tag_offset}..{absolute_tag_end}) overlap \
-                             pointer relocation(s) at {overlaps:?}; only one full-width \
-                             relocation exactly covering a niche pointer carrier is supported"
-                        ))
-                    );
-                }
-            }
-
-            let tag_value =
-                read_enum_tag_value(enum_bytes, &shape.fields, *tag_field, *tag, loc.clone())?;
-
-            match tag_encoding {
-                rustc_public::abi::TagEncoding::Direct => {
-                    // The tag bytes hold a declared discriminant VALUE
-                    // truncated to the PHYSICAL tag width; the caller wants
-                    // a variant INDEX. `discriminant_for_variant().val` is
-                    // at the declared discriminant type's width (isize for
-                    // default-repr enums), so the comparison must mask both
-                    // sides to the tag width (`Neg::N = -5` is byte 0xFB in
-                    // an i8 tag but 0xFFFF_FFFF_FFFF_FFFB as isize). A tag
-                    // that matches no declared discriminant means we
-                    // misread the constant; falling back to
-                    // "value == index" would silently conflate the two
-                    // semantics (the issue #146 bug class).
-                    discriminant_to_variant_index(rust_ty, tag_value, mask).ok_or_else(|| {
-                        input_error!(
-                            loc.clone(),
-                            TranslationErr::unsupported(format!(
-                                "Enum constant tag value {} matches no declared discriminant",
-                                tag_value
-                            ))
-                        )
-                    })
-                }
-                rustc_public::abi::TagEncoding::Niche {
-                    untagged_variant,
-                    niche_variants,
-                    niche_start,
-                } => {
-                    let niche_start_idx = niche_variants.start().to_index();
-                    let niche_end_idx = niche_variants.end().to_index();
-                    Ok(decode_niche_variant_index(
-                        tag_value,
-                        mask,
-                        *niche_start,
-                        niche_start_idx,
-                        niche_end_idx,
-                        untagged_variant.to_index(),
-                    ))
-                }
-            }
-        }
-    }
-}
-
-/// Lower a `fn item -> fn pointer` coercion (`ReifyFnPointer`).
-///
-/// Emits a stable per-function token (hash of the function's mangled
-/// name, never 0 so it cannot look like a null pointer) and casts it
-/// int -> ptr. See the comment at the `Rvalue::Cast` arm for why a token
-/// stands in for a code address on the device.
-fn translate_reify_fn_pointer(
-    ctx: &mut Context,
-    body: &mir::Body,
-    operand: &mir::Operand,
-    dest_ty: &rustc_public::ty::Ty,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
-    use rustc_public::mir::mono::Instance;
-    use std::hash::{Hash, Hasher};
-
-    // The operand's type names the function being reified.
-    let operand_ty = operand.ty(body.locals()).map_err(|e| {
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "ReifyFnPointer: cannot read operand type: {e:?}"
-        )))
-    })?;
-    let rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::FnDef(fn_def, substs)) =
-        operand_ty.kind()
-    else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "ReifyFnPointer on a non-fn-item operand of type {operand_ty:?}"
-            ))
-        );
-    };
-    let raw_intrinsic =
-        crate::translator::terminator::intrinsics::generated::require_supported_raw_intrinsic(
-            fn_def, &loc,
-        )?;
-    let compatibility_path = fn_def.name().as_str().to_string();
-    if let Some(path) = raw_intrinsic.or_else(|| {
-        crate::translator::terminator::intrinsics::generated::is_generated_intrinsic_path(
-            &compatibility_path,
-        )
-        .then_some(compatibility_path)
-    }) {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "generated CUDA intrinsic `{path}` must be called directly and cannot be converted to a function pointer"
-            ))
-        );
-    }
-    let mangled = Instance::resolve(fn_def, &substs)
-        .map_err(|e| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "ReifyFnPointer: cannot resolve fn item: {e:?}"
-            )))
-        })?
-        .mangled_name();
-    let token = {
-        let mut h = std::collections::hash_map::DefaultHasher::new();
-        mangled.hash(&mut h);
-        h.finish() | 1
-    };
-
-    materialize_function_pointer_token(ctx, dest_ty, token, block_ptr, prev_op, loc)
-}
-
-/// Lower a non-capturing `closure -> fn pointer` coercion.
-///
-/// Like named function items, a closure value is zero-sized and contains no
-/// code address to extract. Resolve rustc's `FnOnce` closure shim and use its
-/// mangled identity to create the same non-null comparison token used by
-/// `translate_reify_fn_pointer`.
-fn translate_closure_fn_pointer(
-    ctx: &mut Context,
-    body: &mir::Body,
-    operand: &mir::Operand,
-    dest_ty: &rustc_public::ty::Ty,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
-    use rustc_public::{
-        mir::mono::Instance,
-        ty::{ClosureKind, RigidTy, TyKind},
-    };
-    use std::hash::{Hash, Hasher};
-
-    let operand_ty = operand.ty(body.locals()).map_err(|error| {
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "ClosureFnPointer: cannot read operand type: {error:?}"
-        )))
-    })?;
-    let TyKind::RigidTy(RigidTy::Closure(closure_def, substs)) = operand_ty.kind() else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "ClosureFnPointer on a non-closure operand of type {operand_ty:?}"
-            ))
-        );
-    };
-    let mangled = Instance::resolve_closure(closure_def, &substs, ClosureKind::FnOnce)
-        .map_err(|error| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "ClosureFnPointer: cannot resolve closure shim: {error:?}"
-            )))
-        })?
-        .mangled_name();
-    let token = {
-        let mut hasher = std::collections::hash_map::DefaultHasher::new();
-        mangled.hash(&mut hasher);
-        hasher.finish() | 1
-    };
-
-    materialize_function_pointer_token(ctx, dest_ty, token, block_ptr, prev_op, loc)
-}
-
-fn materialize_function_pointer_token(
-    ctx: &mut Context,
-    dest_ty: &rustc_public::ty::Ty,
-    token: u64,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
-    use dialect_mir::ops::MirConstantOp;
-
-    // Materialize the token and cast it to the fn-pointer type, the same
-    // two-op shape used for provenance-carrying pointer constants.
-    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-    let apint = APInt::from_u64(token, NonZeroUsize::new(64).unwrap());
-    let int_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, apint);
-    let int_op = Operation::new(
-        ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    int_op.deref_mut(ctx).set_loc(loc.clone());
-    MirConstantOp::new(int_op).set_attr_value(ctx, int_attr);
-    match prev_op {
-        Some(prev) => int_op.insert_after(ctx, prev),
-        None => int_op.insert_at_front(block_ptr, ctx),
-    }
-    let int_val = int_op.deref(ctx).get_result(0);
-
-    let result_type = types::translate_type(ctx, dest_ty)?;
-    let cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![result_type],
-        vec![int_val],
-        vec![],
-        0,
-    );
-    cast_op.deref_mut(ctx).set_loc(loc);
-    let cast = MirCastOp::new(cast_op);
-    cast.set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
-
-    let result = cast_op.deref(ctx).get_result(0);
-    Ok((Some(cast_op), result, Some(int_op)))
-}
-
-// Byte-offset lookups over rustc enum layout live in the shared
-// `translator::layout` module so type import and constant decoding cannot
-// drift on how an offset is derived.
-use crate::translator::layout::{enum_tag_offset, enum_variant_field_offsets};
-
-/// Return the byte range occupied by an enum's direct tag or niche carrier.
-fn enum_tag_byte_range(
-    fields: &rustc_public::abi::FieldsShape,
-    tag_field: usize,
-    tag: rustc_public::abi::Scalar,
-    loc: Location,
-) -> TranslationResult<(usize, usize)> {
-    let primitive = match tag {
-        rustc_public::abi::Scalar::Initialized { value, .. }
-        | rustc_public::abi::Scalar::Union { value } => value,
-    };
-    let byte_size = primitive
-        .size(&rustc_public::target::MachineInfo::target())
-        .bytes();
-    let offset = enum_tag_offset(fields, tag_field, loc)?;
-    Ok((offset, byte_size))
-}
-
-/// Read an enum tag scalar from raw bytes using the stable layout metadata.
-fn read_enum_tag_value(
-    enum_bytes: &[u8],
-    fields: &rustc_public::abi::FieldsShape,
-    tag_field: usize,
-    tag: rustc_public::abi::Scalar,
-    loc: Location,
-) -> TranslationResult<u128> {
-    let (offset, byte_size) = enum_tag_byte_range(fields, tag_field, tag, loc.clone())?;
-
-    let end = offset.checked_add(byte_size).ok_or_else(|| {
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "Enum tag overflowed offset computation: offset={}, size={}",
-            offset, byte_size
-        )))
-    })?;
-    if end > enum_bytes.len() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Enum tag needs bytes [{}..{}), but constant only has {} bytes",
-                offset,
-                end,
-                enum_bytes.len()
-            ))
-        );
-    }
-
-    Ok(read_uint_from_bytes(&enum_bytes[offset..end]))
-}
-
-/// Decode an integer from raw bytes using the current target endianness.
-fn read_uint_from_bytes(bytes: &[u8]) -> u128 {
-    match rustc_public::target::MachineInfo::target_endianness() {
-        rustc_public::target::Endian::Little => {
-            bytes.iter().enumerate().fold(0u128, |acc, (idx, byte)| {
-                acc | ((*byte as u128) << (idx * 8))
-            })
-        }
-        rustc_public::target::Endian::Big => bytes
-            .iter()
-            .fold(0u128, |acc, byte| (acc << 8) | (*byte as u128)),
-    }
-}
-
-/// Convert a discriminant value to a variant index.
-///
-/// For enums with explicit discriminants (e.g., `enum { A = 0, B = 2, C = 6 }`),
-/// the discriminant value differs from the variant index:
-/// - Variant index: position in the enum (0, 1, 2, ...)
-/// - Discriminant: the explicit or implicit value assigned to each variant
-///
-/// `tag_value` is the raw tag read from memory, i.e. the discriminant
-/// truncated to the PHYSICAL tag width, while `discriminant_for_variant`
-/// reports values at the declared discriminant type's width (isize for
-/// default-repr enums). `mask` is the tag width's unsigned max; both
-/// sides are masked to it so negative discriminants compare correctly
-/// (`-5` is `0xFB` in an i8 tag but `0xFFFF_FFFF_FFFF_FFFB` as isize).
-///
-/// This function iterates through variants to find which one has the given discriminant.
-fn discriminant_to_variant_index(
-    rust_ty: &rustc_public::ty::Ty,
-    tag_value: u128,
-    mask: u128,
-) -> Option<usize> {
-    use rustc_public::ty::{RigidTy, TyKind};
-
-    match rust_ty.kind() {
-        TyKind::RigidTy(RigidTy::Adt(adt_def, _)) => {
-            for (idx, _variant_def) in adt_def.variants().iter().enumerate() {
-                let variant_idx = rustc_public::ty::VariantIdx::to_val(idx);
-                let discr = adt_def.discriminant_for_variant(variant_idx);
-                if discr.val & mask == tag_value & mask {
-                    return Some(idx);
-                }
-            }
-            None
-        }
-        _ => None,
-    }
-}
-
-/// Check if a type is a pointer to cuda-device's SharedArray.
-fn is_shared_array_pointer(ty: &rustc_public::ty::Ty) -> bool {
-    use rustc_public::ty::{RigidTy, TyKind};
-
-    match ty.kind() {
-        TyKind::RigidTy(RigidTy::RawPtr(pointee_ty, _)) => {
-            // Check if the pointee is SharedArray
-            match pointee_ty.kind() {
-                TyKind::RigidTy(RigidTy::Adt(adt_def, _)) => {
-                    types::is_cuda_device_adt(&adt_def, "SharedArray")
-                }
-                _ => false,
-            }
-        }
-        _ => false,
-    }
-}
-
-/// Check if a type is a pointer to cuda-device's Barrier (mbarrier state in
-/// shared memory).
-fn is_barrier_pointer(ty: &rustc_public::ty::Ty) -> bool {
-    use rustc_public::ty::{RigidTy, TyKind};
-
-    match ty.kind() {
-        TyKind::RigidTy(RigidTy::RawPtr(pointee_ty, _)) => {
-            // Check if the pointee is Barrier
-            match pointee_ty.kind() {
-                TyKind::RigidTy(RigidTy::Adt(adt_def, _)) => {
-                    types::is_cuda_device_adt(&adt_def, "Barrier")
-                }
-                _ => false,
-            }
-        }
-        _ => false,
-    }
-}
-
-struct SharedStaticSourceIdentity {
-    name: String,
-    key: String,
-}
-
-/// Resolve a whole-static shared allocation to both its display path and its
-/// injective compiler identity.
-///
-/// `StaticDef::name()` deliberately omits DefPath disambiguators, so distinct
-/// same-leaf nested statics can have the same display path. The mangled static
-/// instance remains unique and is used for both deduplication and the full-debug
-/// side-table join. Interior pointers are rejected: a `SharedArray` or
-/// `Barrier` allocation always represents the entire static.
-fn shared_static_source_identity(
-    constant: &mir::ConstOperand,
-) -> Option<SharedStaticSourceIdentity> {
-    let ConstantKind::Allocated(allocation) = constant.const_.kind() else {
-        return None;
-    };
-    if allocation.provenance.ptrs.len() != 1 {
-        return None;
-    }
-    let &(relocation_offset, _) = allocation.provenance.ptrs.first()?;
-    let target = static_target_from_allocation_at(allocation, relocation_offset)
-        .ok()
-        .flatten()?;
-    if target.byte_offset != 0 {
-        return None;
-    }
-    let name = target.static_def.name();
-    let key = crate::device_static_global_key(&target.static_def);
-    Some(SharedStaticSourceIdentity { name, key })
-}
-
-/// Historical best-effort source label used by non-Full builds.
-///
-/// This intentionally performs no strict validation: the comment label must
-/// never turn an otherwise valid translation into an error.
-fn shared_static_source_name(constant: &mir::ConstOperand) -> Option<String> {
-    use rustc_public::mir::alloc::GlobalAlloc;
-
-    let ConstantKind::Allocated(allocation) = constant.const_.kind() else {
-        return None;
-    };
-    let &(_, provenance) = allocation.provenance.ptrs.first()?;
-    match GlobalAlloc::from(provenance.0) {
-        GlobalAlloc::Static(static_def) => Some(static_def.name()),
-        _ => None,
-    }
-}
-
-/// Resolve a constant pointer/reference to the Rust static it points at, if any.
-///
-/// The source allocation stores the pointer's byte addend at the relocation
-/// offset, while the provenance entry identifies the target allocation. Keeping
-/// both pieces together prevents interior pointers from silently degrading to
-/// the static's base address. Anonymous allocations return `None`.
-struct StaticPointerTarget {
-    static_def: rustc_public::mir::mono::StaticDef,
-    byte_offset: u64,
-}
-
-fn static_target_from_constant(
-    constant: &mir::ConstOperand,
-    loc: Location,
-) -> TranslationResult<Option<StaticPointerTarget>> {
-    let ConstantKind::Allocated(allocation) = constant.const_.kind() else {
-        return Ok(None);
-    };
-
-    if allocation.is_null().unwrap_or(false) {
-        return Ok(None);
-    }
-
-    let Some(&(relocation_offset, _)) = allocation.provenance.ptrs.first() else {
-        return Ok(None);
-    };
-
-    if allocation.provenance.ptrs.len() != 1 {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "constant pointer contains {} provenance entries; expected one static target",
-                allocation.provenance.ptrs.len()
-            ))
-        );
-    }
-    static_target_from_allocation_at(allocation, relocation_offset)
-}
-
-/// Resolve the pointer relocation beginning at `relocation_offset` to a static.
-///
-/// Unlike `static_target_from_constant`, this operates on an aggregate's own
-/// allocation and therefore does not require that the allocation contain only
-/// one relocation.
-fn static_target_from_allocation_at(
-    allocation: &rustc_public::ty::Allocation,
-    relocation_offset: usize,
-) -> TranslationResult<Option<StaticPointerTarget>> {
-    use rustc_public::mir::alloc::GlobalAlloc;
-
-    let Some(&(provenance_offset, provenance)) = allocation
-        .provenance
-        .ptrs
-        .iter()
-        .find(|(offset, _)| *offset == relocation_offset)
-    else {
-        return Ok(None);
-    };
-
-    let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-    let pointer_end = provenance_offset
-        .checked_add(pointer_width)
-        .ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "constant static-pointer relocation at byte {provenance_offset} overflowed"
-            )))
-        })?;
-    let byte_offset = allocation
-        .read_partial_uint(provenance_offset..pointer_end)
-        .map_err(|error| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Failed to read constant static-pointer addend at byte {provenance_offset}: \
-                 {error:?}"
-            )))
-        })? as u64;
-
-    match GlobalAlloc::from(provenance.0) {
-        GlobalAlloc::Static(static_def) => Ok(Some(StaticPointerTarget {
-            static_def,
-            byte_offset,
-        })),
-        _ => Ok(None),
-    }
-}
-
-/// One pointer-width relocation inside an evaluated Rust static initializer.
-///
-/// The source and target offsets are byte offsets. `target_key` is the same
-/// domain-tagged rustc identity stored on the target `MirGlobalAllocOp`.
-struct GlobalInitializerRelocation {
-    source_offset: u64,
-    width_bytes: u32,
-    target_address_space: u32,
-    target_addend: u64,
-    target_key: String,
-    target_static: rustc_public::mir::mono::StaticDef,
-}
-
-/// The byte image, ABI alignment, and pointer relocations of a global initializer.
-///
-/// Literal bytes remain byte-exact. Pointer slots are carried separately so
-/// lowering can replace their placeholder addend bytes with LLVM relocation
-/// expressions without changing padding, NaN payloads, or field offsets.
-pub(crate) struct GlobalInitializerData {
-    bytes: Vec<u8>,
-    alignment: u64,
-    relocations: Vec<GlobalInitializerRelocation>,
-}
-
-fn static_global_key(static_def: &rustc_public::mir::mono::StaticDef) -> String {
-    crate::device_static_global_key(static_def)
-}
-
-fn static_global_address_space(static_def: &rustc_public::mir::mono::StaticDef) -> u32 {
-    if is_constant_wrapper_type(&static_def.ty()) {
-        4
-    } else {
-        1
-    }
-}
-
-/// Encode initializer relocations using the versioned, length-prefixed format
-/// consumed by `mir-lower` and `llvm-export`.
-fn encode_global_initializer_relocations(relocations: &[GlobalInitializerRelocation]) -> String {
-    fn put_u64(out: &mut String, value: u64) {
-        out.push_str(&value.to_string());
-        out.push(' ');
-    }
-
-    fn put_str(out: &mut String, value: &str) {
-        put_u64(out, value.len() as u64);
-        out.push_str(value);
-        out.push(' ');
-    }
-
-    let mut encoded = String::from("v1 ");
-    put_u64(&mut encoded, relocations.len() as u64);
-    for relocation in relocations {
-        put_u64(&mut encoded, relocation.source_offset);
-        put_u64(&mut encoded, u64::from(relocation.width_bytes));
-        put_u64(&mut encoded, u64::from(relocation.target_address_space));
-        put_u64(&mut encoded, relocation.target_addend);
-        put_str(&mut encoded, &relocation.target_key);
-    }
-    encoded
-}
-
-/// Copy one evaluated allocation into a byte-exact global initializer.
-///
-/// Undefined bytes are Rust padding and become deterministic zeros. Each
-/// provenance entry is preserved as a static-to-static pointer relocation.
-/// Anonymous memory, functions, vtables, and malformed source ranges remain
-/// diagnosed rather than being flattened to integer bytes.
-fn allocation_initializer_data(
-    alloc: &rustc_public::ty::Allocation,
-    description: &str,
-    loc: Location,
-) -> TranslationResult<GlobalInitializerData> {
-    use rustc_public::mir::alloc::GlobalAlloc;
-
-    let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-    let width_bytes = u32::try_from(pointer_width).map_err(|_| {
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "{description} uses a target pointer width that does not fit u32"
-        )))
-    })?;
-
-    if !alloc.provenance.ptrs.is_empty() && pointer_width != 8 {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "{description} contains pointer relocations, but cuda-oxide currently supports only 8-byte NVPTX pointers"
-            ))
-        );
-    }
-
-    let mut entries: Vec<_> = alloc.provenance.ptrs.to_vec();
-    entries.sort_by_key(|(source_offset, _)| *source_offset);
-
-    let mut relocations = Vec::with_capacity(entries.len());
-    let mut previous_end = 0usize;
-
-    for (index, (source_offset, provenance)) in entries.into_iter().enumerate() {
-        if source_offset < previous_end {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "{description} pointer relocation {index} overlaps the previous relocation"
-                ))
-            );
-        }
-
-        let end = source_offset.checked_add(pointer_width).ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "{description} pointer relocation {index} source range overflows"
-            )))
-        })?;
-        if end > alloc.bytes.len() {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "{description} pointer relocation {index} occupies bytes {source_offset}..{end}, but the allocation is only {} bytes",
-                    alloc.bytes.len()
-                ))
-            );
-        }
-
-        let target_addend = alloc
-            .read_partial_uint(source_offset..end)
-            .map_err(|error| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Failed to read {description} pointer relocation {index} addend: {error:?}"
-                )))
-            })? as u64;
-
-        let target_static = match GlobalAlloc::from(provenance.0) {
-            GlobalAlloc::Static(static_def) => static_def,
-            other => {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "{description} pointer relocation {index} targets unsupported allocation {other:?}; only Rust statics in CUDA global or constant memory are supported"
-                    ))
-                );
-            }
-        };
-
-        relocations.push(GlobalInitializerRelocation {
-            source_offset: u64::try_from(source_offset).map_err(|_| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "{description} pointer relocation {index} source offset does not fit u64"
-                )))
-            })?,
-            width_bytes,
-            target_address_space: static_global_address_space(&target_static),
-            target_addend,
-            target_key: static_global_key(&target_static),
-            target_static,
-        });
-        previous_end = end;
-    }
-
-    Ok(GlobalInitializerData {
-        bytes: alloc.bytes.iter().map(|byte| byte.unwrap_or(0)).collect(),
-        alignment: alloc.align,
-        relocations,
-    })
-}
-
-/// Build the byte-exact, relocation-aware initializer used by array promotion.
-///
-/// Bare `[T; N]` constants own their allocation directly, so provenance entries
-/// inside that allocation belong to pointer fields in the table. Pointer-to-array
-/// constants (`&[T; N]` / `*const [T; N]`) instead contain one outer relocation
-/// to the backing allocation; that relocation is followed once and any
-/// relocations inside the selected table range are preserved and rebased.
-fn promoted_array_initializer(
-    constant: &mir::ConstOperand,
-    expected_size: usize,
-    kind_name: &str,
-    loc: Location,
-) -> TranslationResult<GlobalInitializerData> {
-    use rustc_public::mir::alloc::GlobalAlloc;
-    use rustc_public::ty::{RigidTy, TyConstKind, TyKind};
-
-    fn direct_initializer(
-        alloc: &rustc_public::ty::Allocation,
-        expected_size: usize,
-        kind_name: &str,
-        loc: Location,
-    ) -> TranslationResult<GlobalInitializerData> {
-        let data = allocation_initializer_data(
-            alloc,
-            &format!("promoted {kind_name} initializer"),
-            loc.clone(),
-        )?;
-        if data.bytes.len() != expected_size {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "promoted {kind_name} initializer is {} bytes, expected {expected_size}",
-                    data.bytes.len()
-                ))
-            );
-        }
-        Ok(data)
-    }
-
-    fn project_initializer_range(
-        data: GlobalInitializerData,
-        target_offset: usize,
-        expected_size: usize,
-        kind_name: &str,
-        loc: Location,
-    ) -> TranslationResult<GlobalInitializerData> {
-        let end = target_offset.checked_add(expected_size).ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "promoted {kind_name} initializer offset overflows its allocation"
-            )))
-        })?;
-        let bytes = data
-            .bytes
-            .get(target_offset..end)
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "promoted {kind_name} initializer needs bytes {target_offset}..{end}, but its backing allocation is only {} bytes",
-                    data.bytes.len()
-                )))
-            })?
-            .to_vec();
-        let alignment = data.alignment;
-
-        let mut relocations = Vec::new();
-        for relocation in data.relocations {
-            let source_start = usize::try_from(relocation.source_offset).map_err(|_| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "promoted {kind_name} relocation source offset {} does not fit usize",
-                    relocation.source_offset
-                )))
-            })?;
-            let width = usize::try_from(relocation.width_bytes).map_err(|_| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "promoted {kind_name} relocation width {} does not fit usize",
-                    relocation.width_bytes
-                )))
-            })?;
-            let source_end = source_start.checked_add(width).ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "promoted {kind_name} relocation at byte {source_start} overflows"
-                )))
-            })?;
-            let overlaps = source_start < end && source_end > target_offset;
-            if !overlaps {
-                continue;
-            }
-            if source_start < target_offset || source_end > end {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "promoted {kind_name} relocation bytes {source_start}..{source_end} cross selected initializer range {target_offset}..{end}"
-                    ))
-                );
-            }
-
-            relocations.push(GlobalInitializerRelocation {
-                source_offset: u64::try_from(source_start - target_offset).map_err(|_| {
-                    input_error_noloc!(TranslationErr::unsupported(format!(
-                        "promoted {kind_name} rebased relocation offset does not fit u64"
-                    )))
-                })?,
-                width_bytes: relocation.width_bytes,
-                target_address_space: relocation.target_address_space,
-                target_addend: relocation.target_addend,
-                target_key: relocation.target_key,
-                target_static: relocation.target_static,
-            });
-        }
-
-        Ok(GlobalInitializerData {
-            bytes,
-            alignment,
-            relocations,
-        })
-    }
-
-    fn pointer_initializer(
-        alloc: &rustc_public::ty::Allocation,
-        expected_size: usize,
-        kind_name: &str,
-        loc: Location,
-    ) -> TranslationResult<GlobalInitializerData> {
-        if alloc.provenance.ptrs.len() != 1 {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "promoted {kind_name} pointer contains {} provenance entries; expected exactly one backing allocation",
-                    alloc.provenance.ptrs.len()
-                ))
-            );
-        }
-        let &(provenance_offset, provenance) =
-            alloc.provenance.ptrs.first().expect("length checked above");
-
-        let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-        let pointer_end = provenance_offset
-            .checked_add(pointer_width)
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "promoted {kind_name} outer pointer range overflows"
-                )))
-            })?;
-        let target_offset = alloc
-            .read_partial_uint(provenance_offset..pointer_end)
-            .map_err(|e| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Failed to read promoted {kind_name} pointer offset: {e:?}"
-                )))
-            })? as usize;
-
-        let target_alloc = match GlobalAlloc::from(provenance.0) {
-            GlobalAlloc::Memory(target_alloc) => target_alloc,
-            GlobalAlloc::Static(static_def) => static_def.eval_initializer().map_err(|e| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Failed to evaluate promoted {kind_name} backing static {}: {e:?}",
-                    static_def.name()
-                )))
-            })?,
-            other => {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "promoted {kind_name} provenance points to unsupported allocation {other:?}"
-                    ))
-                );
-            }
-        };
-
-        let data = allocation_initializer_data(
-            &target_alloc,
-            &format!("promoted {kind_name} backing allocation"),
-            loc.clone(),
-        )?;
-        project_initializer_range(data, target_offset, expected_size, kind_name, loc)
-    }
-
-    let pointer_form = matches!(
-        constant.const_.ty().kind(),
-        TyKind::RigidTy(RigidTy::RawPtr(_, _)) | TyKind::RigidTy(RigidTy::Ref(_, _, _))
-    );
-
-    match constant.const_.kind() {
-        ConstantKind::Allocated(alloc) => {
-            if pointer_form {
-                pointer_initializer(alloc, expected_size, kind_name, loc)
-            } else {
-                direct_initializer(alloc, expected_size, kind_name, loc)
-            }
-        }
-        ConstantKind::Ty(ty_const) => match ty_const.kind() {
-            TyConstKind::Value(_, alloc) => {
-                if pointer_form {
-                    pointer_initializer(alloc, expected_size, kind_name, loc)
-                } else {
-                    direct_initializer(alloc, expected_size, kind_name, loc)
-                }
-            }
-            TyConstKind::ZSTValue(_) if expected_size == 0 => Ok(GlobalInitializerData {
-                bytes: Vec::new(),
-                alignment: 1,
-                relocations: Vec::new(),
-            }),
-            other => input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "promoted {kind_name} initializer must be backed by bytes, found TyConstKind::{other:?}"
-                ))
-            ),
-        },
-        ConstantKind::ZeroSized if expected_size == 0 => Ok(GlobalInitializerData {
-            bytes: Vec::new(),
-            alignment: 1,
-            relocations: Vec::new(),
-        }),
-        other => input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "promoted {kind_name} initializer must be allocated, found {other:?}"
-            ))
-        ),
-    }
-}
-
-/// Return rustc's evaluated static initializer bytes, alignment, and relocations.
-fn static_initializer_data(
-    static_def: &rustc_public::mir::mono::StaticDef,
-    loc: Location,
-) -> TranslationResult<GlobalInitializerData> {
-    let alloc = static_def.eval_initializer().map_err(|e| {
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "Failed to evaluate initializer for device static {}: {:?}",
-            static_def.name(),
-            e
-        )))
-    })?;
-    allocation_initializer_data(&alloc, &format!("device static {}", static_def.name()), loc)
-}
-
-fn bytes_to_hex(bytes: &[u8]) -> String {
-    let mut hex = String::with_capacity(bytes.len() * 2);
-    for byte in bytes {
-        use std::fmt::Write as _;
-        write!(&mut hex, "{byte:02x}").expect("writing to String cannot fail");
-    }
-    hex
-}
-
-fn promoted_constant_dedup_key(
-    ctx: &Context,
-    ty: TypeHandle,
-    initializer: &GlobalInitializerData,
-) -> String {
-    let relocations = encode_global_initializer_relocations(&initializer.relocations);
-    promoted_constant_dedup_key_from_parts(
-        ctx,
-        ty,
-        &initializer.bytes,
-        initializer.alignment,
-        &relocations,
-    )
-}
-
-fn promoted_constant_dedup_key_from_parts(
-    ctx: &Context,
-    ty: TypeHandle,
-    bytes: &[u8],
-    alignment: u64,
-    relocations: &str,
-) -> String {
-    // This string is only an in-pass map key; it never becomes the emitted
-    // symbol name. Keep the full type, byte image, allocation alignment, and
-    // relocation encoding so constants with identical bytes but different
-    // storage requirements or provenance targets cannot alias.
-    let ty = ty.deref(ctx).disp(ctx).to_string();
-    let bytes = bytes_to_hex(bytes);
-    let fingerprint = format!(
-        "__cuda_oxide_promoted_type{}:{ty}:bytes{}:{bytes}:align{alignment}:relocs{}:{relocations}",
-        ty.len(),
-        bytes.len() / 2,
-        relocations.len()
-    );
-    dialect_mir::ops::encode_promoted_global_key(&fingerprint)
-}
-
-/// Detect zero-addend array→slice unsize: static `[T; N]` viewed as `[T]`.
-///
-/// Returns `(element_ty, N)` when the pointee is a slice of the same element
-/// type as the static array. Other pointee mismatches stay unsupported.
-/// `N` is an upper bound for validation only; the emitted slice length comes
-/// from the constant's own fat-pointer metadata word, which is what makes
-/// zero-addend prefix subslices (e.g. `split_at(2).0` over the static) carry
-/// their true length instead of the whole array's.
-///
-/// The `static_elem == slice_elem` restriction is deliberate: a zero-addend
-/// *flattening* view (e.g. `&NESTED[0]` over `[[f32; 2]; 3]` typed as
-/// `&[f32]`) is valid Rust but stays a diagnosed support gap; accepting it
-/// would need element-count arithmetic across the reinterpreted shape, not
-/// just the stored metadata word.
-fn array_to_slice_unsize_info(
-    static_ty: &rustc_public::ty::Ty,
-    pointee_ty: &rustc_public::ty::Ty,
-    loc: Location,
-) -> TranslationResult<Option<(rustc_public::ty::Ty, u64)>> {
-    use rustc_public::ty::{RigidTy, TyKind};
-
-    match (static_ty.kind(), pointee_ty.kind()) {
-        (
-            TyKind::RigidTy(RigidTy::Array(static_elem, len_const)),
-            TyKind::RigidTy(RigidTy::Slice(slice_elem)),
-        ) if static_elem == slice_elem => {
-            let len = len_const.eval_target_usize().map_err(|error| {
-                input_error!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Failed to evaluate array length for static slice unsize: {error:?}"
-                    ))
-                )
-            })?;
-            Ok(Some((static_elem, len)))
-        }
-        _ => Ok(None),
-    }
-}
-
-/// Detect an interior array→slice unsize within a device static.
-///
-/// The walk is intentionally limited to arrays. At each nesting level, the
-/// byte addend selects one array element; when that array's element type
-/// matches the slice element type, the remaining element count is returned.
-/// This supports both an offset into a flat `[T; N]` and a slice over an array
-/// nested inside outer arrays, while keeping structs, tuples, enums, and other
-/// DST reinterpretations outside this lowering path.
-fn interior_array_to_slice_unsize_info(
-    static_ty: &rustc_public::ty::Ty,
-    pointee_ty: &rustc_public::ty::Ty,
-    byte_offset: u64,
-    loc: Location,
-) -> TranslationResult<Option<(rustc_public::ty::Ty, u64)>> {
-    use rustc_public::ty::{RigidTy, Ty, TyKind};
-
-    let TyKind::RigidTy(RigidTy::Slice(slice_elem)) = pointee_ty.kind() else {
-        return Ok(None);
-    };
-
-    fn find_region(
-        array_ty: Ty,
-        slice_elem: Ty,
-        byte_offset: u64,
-        loc: &Location,
-    ) -> TranslationResult<Option<u64>> {
-        let TyKind::RigidTy(RigidTy::Array(array_elem, len_const)) = array_ty.kind() else {
-            return Ok(None);
-        };
-
-        let len = len_const.eval_target_usize().map_err(|error| {
-            input_error!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Failed to evaluate array length for interior static slice unsize: {error:?}"
-                ))
-            )
-        })?;
-        let elem_size = rust_type_layout_size(array_elem, loc.clone())? as u64;
-        let array_size = elem_size.checked_mul(len).ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Array byte size overflowed while resolving an interior static slice: \
-                 {len} elements x {elem_size} bytes"
-            )))
-        })?;
-
-        if byte_offset > array_size {
-            return Ok(None);
-        }
-
-        if array_elem == slice_elem {
-            // A non-zero byte addend cannot distinguish positions between
-            // zero-sized elements. Keep that case outside this path rather
-            // than manufacturing an arbitrary element index.
-            if elem_size == 0 || !byte_offset.is_multiple_of(elem_size) {
-                return Ok(None);
-            }
-
-            let start = byte_offset / elem_size;
-            if start > len {
-                return Ok(None);
-            }
-            return Ok(Some(len - start));
-        }
-
-        // Descend only through the concrete outer element containing the
-        // addend. An offset one-past this array has no child array region to
-        // inspect, even though it may be valid for an empty slice at this
-        // array's own element type (handled by the matching arm above).
-        if elem_size == 0 || byte_offset >= array_size {
-            return Ok(None);
-        }
-
-        let element_index = byte_offset / elem_size;
-        if element_index >= len {
-            return Ok(None);
-        }
-
-        find_region(array_elem, slice_elem, byte_offset % elem_size, loc)
-    }
-
-    Ok(find_region(*static_ty, slice_elem, byte_offset, &loc)?
-        .map(|remaining_len| (slice_elem, remaining_len)))
-}
-
-/// Validate the relocation shape of one slice fat pointer stored inside an
-/// allocation.
-///
-/// A slice occupies two pointer-width words. Exactly one relocation must back
-/// the data word at `fat_ptr_offset`; the metadata word is a literal `usize`
-/// and therefore must not overlap another relocation. Sibling relocations that
-/// end exactly at the field start or begin exactly at the field end are fine.
-///
-/// Returns `(metadata_offset, fat_pointer_end)` on success. Generic over the
-/// provenance payload so the boundary rules are unit testable without a rustc
-/// session.
-fn validate_slice_relocation_shape<P>(
-    ptrs: &[(usize, P)],
-    fat_ptr_offset: usize,
-    pointer_width: usize,
-) -> Result<(usize, usize), String> {
-    if pointer_width == 0 {
-        return Err("slice fat pointer has zero-width target pointers".to_string());
-    }
-
-    let metadata_offset = fat_ptr_offset
-        .checked_add(pointer_width)
-        .ok_or_else(|| "slice fat-pointer data-word end overflowed".to_string())?;
-    let fat_pointer_end = metadata_offset
-        .checked_add(pointer_width)
-        .ok_or_else(|| "slice fat-pointer metadata-word end overflowed".to_string())?;
-
-    let anchored = ptrs
-        .iter()
-        .filter(|(offset, _)| *offset == fat_ptr_offset)
-        .count();
-    if anchored != 1 {
-        return Err(format!(
-            "Slice fat pointer at byte {fat_ptr_offset} has {anchored} provenance entries at its \
-             data-word start; expected exactly one"
-        ));
-    }
-
-    let overlapping =
-        relocation_offsets_overlapping_range(ptrs, fat_ptr_offset, fat_pointer_end, pointer_width);
-    if let Some(other_offset) = overlapping
-        .into_iter()
-        .find(|offset| *offset != fat_ptr_offset)
-    {
-        return Err(format!(
-            "Slice fat pointer at byte {fat_ptr_offset} has an additional relocation at byte \
-             {other_offset}; the metadata word must remain literal usize bytes"
-        ));
-    }
-
-    Ok((metadata_offset, fat_pointer_end))
-}
-
-/// Read the slice length from a fat-pointer image stored at an arbitrary
-/// allocation offset.
-fn slice_len_from_alloc_at(
-    alloc: &rustc_public::ty::Allocation,
-    fat_ptr_offset: usize,
-    loc: Location,
-) -> TranslationResult<u64> {
-    let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-    let (metadata_offset, fat_pointer_end) =
-        validate_slice_relocation_shape(&alloc.provenance.ptrs, fat_ptr_offset, pointer_width)
-            .map_err(|message| input_error!(loc.clone(), TranslationErr::unsupported(message)))?;
-
-    if fat_pointer_end > alloc.bytes.len() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Slice fat pointer at byte {fat_ptr_offset} needs bytes through \
-                 {fat_pointer_end}, but the allocation is only {} bytes",
-                alloc.bytes.len()
-            ))
-        );
-    }
-
-    alloc
-        .read_partial_uint(metadata_offset..fat_pointer_end)
-        .map(|len| len as u64)
-        .map_err(|error| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Failed to read slice length metadata at byte {metadata_offset}: {error:?}"
-            )))
-        })
-}
-
-/// Read the slice length from a standalone fat-pointer constant's metadata
-/// word.
-///
-/// A `&[T]` / `*const [T]` constant is a two-word image: the data word (which
-/// carries the provenance to the static, read by `static_target_from_constant`)
-/// followed by the `usize` length. The length word is the source of truth for
-/// the emitted slice: a const like `split_at(2).0` over a `[f32; 4]` static is
-/// a zero-addend pointer whose stored length is 2, not the array's 4.
-fn slice_len_from_constant(constant: &mir::ConstOperand, loc: Location) -> TranslationResult<u64> {
-    let ConstantKind::Allocated(alloc) = constant.const_.kind() else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(
-                "static slice unsize constant is not an allocated constant".to_string()
-            )
-        );
-    };
-
-    let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-    let expected_size = pointer_width.checked_mul(2).ok_or_else(|| {
-        input_error_noloc!(TranslationErr::unsupported(
-            "static slice unsize constant pointer width overflowed".to_string()
-        ))
-    })?;
-    if alloc.bytes.len() != expected_size {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "static slice unsize constant has {} bytes; expected exactly two \
-                 pointer-width words ({expected_size} bytes)",
-                alloc.bytes.len()
-            ))
-        );
-    }
-
-    slice_len_from_alloc_at(alloc, 0, loc)
-}
-
-/// Materialize a region of a device static as a fat `&[T]` / `*const [T]`.
-///
-/// A zero addend preserves the established whole-array path. A non-zero
-/// addend reuses the byte-addressed static-pointer lowering to produce the
-/// interior `*T` data pointer before pairing it with the length stored in the
-/// constant's metadata word.
-fn translate_static_array_as_slice(
-    ctx: &mut Context,
-    static_def: &rustc_public::mir::mono::StaticDef,
-    elem_ty: rustc_public::ty::Ty,
-    len: u64,
-    origin: facts::PointerOrigin,
-    byte_offset: u64,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    use dialect_mir::ops::MirConstructSliceOp;
-
-    let elem_mir_ty = types::translate_type(ctx, &elem_ty)?;
-    let is_mutable = origin.is_mutable();
-
-    let (data_ptr, prev_after_data) = if byte_offset == 0 {
-        let static_ty = static_def.ty();
-        let array_mir_ty = types::translate_type(ctx, &static_ty)?;
-
-        // Thin pointer to the full array object (exact Rust `&[T; N]` shape).
-        let thin_array_ptr_ty: TypeHandle =
-            facts::mint_generic_ptr_type(ctx, array_mir_ty, origin).into();
-
-        let (array_ptr, prev_after_array) = translate_static_global_pointer(
-            ctx,
-            static_def,
-            array_mir_ty,
-            thin_array_ptr_ty,
-            is_mutable,
-            0,
-            block_ptr,
-            prev_op,
-            loc.clone(),
-        )?;
-
-        // Fat-pointer data slot is a generic `*T` / `*mut T`.
-        coerce_slice_data_pointee(
-            ctx,
-            array_ptr,
-            elem_mir_ty,
-            is_mutable,
-            block_ptr,
-            prev_after_array,
-            loc.clone(),
-        )
-    } else {
-        let data_ptr_ty: TypeHandle = facts::mint_generic_ptr_type(ctx, elem_mir_ty, origin).into();
-
-        translate_static_global_pointer(
-            ctx,
-            static_def,
-            elem_mir_ty,
-            data_ptr_ty,
-            is_mutable,
-            byte_offset,
-            block_ptr,
-            prev_op,
-            loc.clone(),
-        )?
-    };
-
-    let usize_ty = types::get_usize_type(ctx);
-    let len_attr = pliron::builtin::attributes::IntegerAttr::new(
-        usize_ty,
-        APInt::from_u64(len, NonZeroUsize::new(64).unwrap()),
-    );
-    let len_op = Operation::new(
-        ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![usize_ty.to_handle()],
-        vec![],
-        vec![],
-        0,
-    );
-    len_op.deref_mut(ctx).set_loc(loc.clone());
-    MirConstantOp::new(len_op).set_attr_value(ctx, len_attr);
-    match prev_after_data {
-        Some(prev) => len_op.insert_after(ctx, prev),
-        None => len_op.insert_at_front(block_ptr, ctx),
-    };
-    let len_val = len_op.deref(ctx).get_result(0);
-
-    let slice_ty = facts::mint_slice_type(ctx, elem_mir_ty, origin);
-    let construct = Operation::new(
-        ctx,
-        MirConstructSliceOp::get_concrete_op_info(),
-        vec![slice_ty.into()],
-        vec![data_ptr, len_val],
-        vec![],
-        0,
-    );
-    construct.deref_mut(ctx).set_loc(loc);
-    construct.insert_after(ctx, len_op);
-
-    Ok((construct.deref(ctx).get_result(0), Some(construct)))
-}
-
-/// Return relocation starts whose pointer-width storage overlaps
-/// `range_start..range_end`.
-///
-/// Unlike a simple "starts in range" check, this catches a relocation that
-/// begins before the enum tag carrier but extends into it.
-fn relocation_offsets_overlapping_range<P>(
-    ptrs: &[(usize, P)],
-    range_start: usize,
-    range_end: usize,
-    pointer_width: usize,
-) -> Vec<usize> {
-    ptrs.iter()
-        .map(|(pos, _)| *pos)
-        .filter(|pos| {
-            let relocation_end = pos.saturating_add(pointer_width);
-            *pos < range_end && relocation_end > range_start
-        })
-        .collect()
-}
-
-/// Match the provenance entries of a thin-pointer field spanning
-/// `pointer_offset..field_end`.
-///
-/// Returns the payload of the single relocation anchored at the field's base
-/// offset, or `None` when no entry starts inside the field (null or exposed
-/// provenance bytes). More than one entry anchored at the base, or an entry
-/// starting strictly inside the field (fat or multi-word pointer bits), is a
-/// hard error. Generic over the payload so the matching rules are unit
-/// testable without a rustc session (`Prov` wraps an unconstructible
-/// `AllocId`).
-fn match_thin_pointer_relocation<P: Copy>(
-    ptrs: &[(usize, P)],
-    pointer_offset: usize,
-    field_end: usize,
-) -> Result<Option<P>, String> {
-    let matches: Vec<P> = ptrs
-        .iter()
-        .filter(|(pos, _)| *pos == pointer_offset)
-        .map(|&(_, prov)| prov)
-        .collect();
-    if matches.len() > 1 {
-        return Err(format!(
-            "Thin pointer field at offset {pointer_offset} has {} provenance entries; \
-             expected at most one",
-            matches.len()
-        ));
-    }
-
-    // A thin pointer occupies one pointer-sized word; reject any additional
-    // provenance that lands inside this field's byte range.
-    if let Some(&(interior_pos, _)) = ptrs
-        .iter()
-        .find(|(pos, _)| *pos > pointer_offset && *pos < field_end)
-    {
-        return Err(format!(
-            "Pointer field at offset {pointer_offset} has interior provenance at byte \
-             {interior_pos}; fat or multi-word pointer provenance in aggregate constants \
-             is not supported"
-        ));
-    }
-
-    Ok(matches.first().copied())
-}
-
-/// Decode the byte addend stored under a thin-pointer relocation at
-/// `pointer_offset..pointer_offset + ptr_width`.
-///
-/// The bytes under a relocation encode the offset into the target allocation
-/// and are always initialized by rustc, so an uninitialized byte is a hard
-/// error rather than a zero. Endianness is a parameter so the decoding is
-/// unit testable without a rustc session.
-fn decode_relocation_addend(
-    bytes: &[Option<u8>],
-    pointer_offset: usize,
-    ptr_width: usize,
-    endianness: rustc_public::target::Endian,
-) -> Result<u128, String> {
-    if ptr_width > 16 {
-        return Err(format!(
-            "relocation addend width {ptr_width} exceeds the 16-byte decode limit"
-        ));
-    }
-    let field_end = pointer_offset
-        .checked_add(ptr_width)
-        .filter(|end| *end <= bytes.len())
-        .ok_or_else(|| {
-            format!(
-                "relocation addend at offset {pointer_offset} needs {ptr_width} bytes, \
-                 but the allocation holds {}",
-                bytes.len()
-            )
-        })?;
-    let raw = bytes[pointer_offset..field_end]
-        .iter()
-        .copied()
-        .collect::<Option<Vec<u8>>>()
-        .ok_or_else(|| {
-            format!("relocation addend at offset {pointer_offset} contains uninitialized bytes")
-        })?;
-    Ok(match endianness {
-        rustc_public::target::Endian::Little => {
-            raw.iter().enumerate().fold(0u128, |acc, (idx, byte)| {
-                acc | ((*byte as u128) << (idx * 8))
-            })
-        }
-        rustc_public::target::Endian::Big => raw
-            .iter()
-            .fold(0u128, |acc, byte| (acc << 8) | (*byte as u128)),
-    })
-}
-
-/// Materialize a thin pointer field from an aggregate constant's allocation.
-///
-/// Aggregate **const** values with thin pointers to device statics are
-/// materialized via [`MirGlobalAllocOp`] per field (addend taken from the
-/// relocation's stored bytes). This does **not** mean device-static
-/// *initializers* that themselves contain pointer relocations are supported —
-/// those remain rejected by [`allocation_initializer_data`].
-///
-/// When the field has no provenance entry, falls back to the existing
-/// inttoptr-of-bytes path (null / exposed provenance).
-fn translate_thin_pointer_at_alloc_offset(
-    ctx: &mut Context,
-    alloc: &rustc_public::ty::Allocation,
-    pointer_offset: usize,
-    result_ptr_ty: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    use rustc_public::mir::alloc::GlobalAlloc;
-
-    let ptr_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-    let field_end = pointer_offset.checked_add(ptr_width).ok_or_else(|| {
-        input_error!(
-            loc.clone(),
-            TranslationErr::unsupported(format!(
-                "Thin pointer field offset {pointer_offset} + width {ptr_width} overflowed"
-            ))
-        )
-    })?;
-    if field_end > alloc.bytes.len() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Thin pointer field at offset {pointer_offset} needs {ptr_width} bytes, \
-                 but allocation is only {} bytes",
-                alloc.bytes.len()
-            ))
-        );
-    }
-
-    let relocation =
-        match_thin_pointer_relocation(&alloc.provenance.ptrs, pointer_offset, field_end)
-            .map_err(|message| input_error!(loc.clone(), TranslationErr::unsupported(message)))?;
-
-    if let Some(prov) = relocation {
-        let addend = decode_relocation_addend(
-            &alloc.bytes,
-            pointer_offset,
-            ptr_width,
-            rustc_public::target::MachineInfo::target_endianness(),
-        )
-        .map_err(|message| {
-            input_error!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Failed to read thin-pointer addend at offset {pointer_offset}: {message}"
-                ))
-            )
-        })?;
-
-        let (pointee_ty, is_mutable) = {
-            let ty_ref = result_ptr_ty.deref(ctx);
-            let ptr_ty = ty_ref
-                .downcast_ref::<dialect_mir::types::MirPtrType>()
-                .ok_or_else(|| {
-                    input_error_noloc!(TranslationErr::unsupported(
-                        "translate_thin_pointer_at_alloc_offset: expected MirPtrType"
-                    ))
-                })?;
-            (ptr_ty.pointee, ptr_ty.is_mutable)
-        };
-
-        match GlobalAlloc::from(prov.0) {
-            GlobalAlloc::Static(static_def) => {
-                let byte_offset = u64::try_from(addend).map_err(|_| {
-                    input_error_noloc!(TranslationErr::unsupported(format!(
-                        "Device-static pointer addend {addend} does not fit u64"
-                    )))
-                })?;
-                return translate_static_global_pointer(
-                    ctx,
-                    &static_def,
-                    pointee_ty,
-                    result_ptr_ty,
-                    is_mutable,
-                    byte_offset,
-                    block_ptr,
-                    prev_op,
-                    loc,
-                );
-            }
-            GlobalAlloc::Memory(_) => {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Aggregate constant thin pointer at offset {pointer_offset} points at \
-                        an anonymous promoted allocation; promoted aggregate pointer constants \
-                        are not yet supported"
-                    ))
-                );
-            }
-            other => {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(format!(
-                        "Aggregate constant thin pointer at offset {pointer_offset} points at \
-                         unsupported allocation kind: {other:?}"
-                    ))
-                );
-            }
-        }
-    }
-
-    // No provenance: keep the existing inttoptr-of-bytes behavior (null / exposed).
-    let field_bytes: Vec<u8> = alloc.bytes[pointer_offset..field_end]
-        .iter()
-        .map(|opt| opt.unwrap_or(0))
-        .collect();
-    let ptr_val = read_uint_from_bytes(&field_bytes) as u64;
-    let i64_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);
-    let apint = APInt::from_u64(ptr_val, NonZeroUsize::new(64).unwrap());
-    let int_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, apint);
-
-    let int_op = Operation::new(
-        ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    int_op.deref_mut(ctx).set_loc(loc.clone());
-    let const_op = MirConstantOp::new(int_op);
-    const_op.set_attr_value(ctx, int_attr);
-    if let Some(prev) = prev_op {
-        const_op.get_operation().insert_after(ctx, prev);
-    } else {
-        const_op.get_operation().insert_at_front(block_ptr, ctx);
-    }
-
-    let const_value = const_op.get_operation().deref(ctx).get_result(0);
-    let cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![result_ptr_ty],
-        vec![const_value],
-        vec![],
-        0,
-    );
-    cast_op.deref_mut(ctx).set_loc(loc);
-    let cast = MirCastOp::new(cast_op);
-    cast.set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
-    if dialect_mir::types::type_contains_concrete_pointer_kind(ctx, result_ptr_ty) {
-        cast.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    }
-    cast_op.insert_after(ctx, const_op.get_operation());
-    Ok((cast_op.deref(ctx).get_result(0), Some(cast_op)))
-}
-
-/// Materialize a slice fat-pointer field from an aggregate constant allocation.
-///
-/// The data word keeps rustc provenance and may carry a non-zero byte addend
-/// into a device static. The metadata word is decoded independently as the
-/// stored slice length. This deliberately supports only same-element
-/// array-to-slice views over Rust statics, matching the standalone constant
-/// path; anonymous promoted allocations and other DST metadata remain
-/// fail-closed.
-#[allow(clippy::too_many_arguments)]
-fn translate_slice_at_alloc_offset(
-    ctx: &mut Context,
-    alloc: &rustc_public::ty::Allocation,
-    fat_ptr_offset: usize,
-    rust_ty: &rustc_public::ty::Ty,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let Some((pointee_ty, origin)) = get_static_pointer_info(rust_ty) else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Aggregate slice constant at byte {fat_ptr_offset} has unexpected Rust type \
-                 {rust_ty:?}; expected a reference or raw pointer to a slice"
-            ))
-        );
-    };
-
-    let len = slice_len_from_alloc_at(alloc, fat_ptr_offset, loc.clone())?;
-    let Some(static_target) = static_target_from_allocation_at(alloc, fat_ptr_offset)? else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Aggregate slice constant at byte {fat_ptr_offset} points at an anonymous or \
-                 unsupported allocation; slice provenance currently requires a Rust device static"
-            ))
-        );
-    };
-
-    let static_ty = static_target.static_def.ty();
-    let slice_region = if static_target.byte_offset == 0 {
-        array_to_slice_unsize_info(&static_ty, &pointee_ty, loc.clone())?
-    } else {
-        interior_array_to_slice_unsize_info(
-            &static_ty,
-            &pointee_ty,
-            static_target.byte_offset,
-            loc.clone(),
-        )?
-    };
-
-    let Some((elem_ty, available_len)) = slice_region else {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Aggregate slice constant at byte {fat_ptr_offset} points into device static {} \
-                 at byte addend {}, but its pointee type {pointee_ty:?} is not a supported \
-                 same-element array-to-slice view of static type {static_ty:?}",
-                static_target.static_def.name(),
-                static_target.byte_offset
-            ))
-        );
-    };
-
-    if len > available_len {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Aggregate slice constant at byte {fat_ptr_offset} stores length {len}, which \
-                 exceeds the selected region's remaining length {available_len} in device \
-                 static {}",
-                static_target.static_def.name()
-            ))
-        );
-    }
-
-    translate_static_array_as_slice(
-        ctx,
-        &static_target.static_def,
-        elem_ty,
-        len,
-        origin,
-        static_target.byte_offset,
-        block_ptr,
-        prev_op,
-        loc,
-    )
-}
-
-/// Slice `size` bytes from `alloc` at `offset`, treating uninit as zero.
-fn alloc_slice_bytes_zeroing_uninit(
-    alloc: &rustc_public::ty::Allocation,
-    offset: usize,
-    size: usize,
-    what: &str,
-    loc: &Location,
-) -> TranslationResult<Vec<u8>> {
-    let end = offset.checked_add(size).ok_or_else(|| {
-        input_error!(
-            loc.clone(),
-            TranslationErr::unsupported(format!(
-                "{what}: offset {offset} + size {size} overflowed"
-            ))
-        )
-    })?;
-    if end > alloc.bytes.len() {
-        return input_err!(
-            loc.clone(),
-            TranslationErr::unsupported(format!(
-                "{what}: need [{offset}..{end}), but allocation is only {} bytes",
-                alloc.bytes.len()
-            ))
-        );
-    }
-    Ok(alloc.bytes[offset..end]
-        .iter()
-        .map(|opt| opt.unwrap_or(0))
-        .collect())
-}
-
-/// Whether any provenance entry starts inside `offset..offset + size`.
-/// Generic over the payload so the predicate is unit testable without a
-/// rustc session.
-fn provenance_starts_in_range<P>(ptrs: &[(usize, P)], offset: usize, size: usize) -> bool {
-    let end = offset.saturating_add(size);
-    ptrs.iter().any(|(pos, _)| *pos >= offset && *pos < end)
-}
-
-fn alloc_has_provenance_in_range(
-    alloc: &rustc_public::ty::Allocation,
-    offset: usize,
-    size: usize,
-) -> bool {
-    provenance_starts_in_range(&alloc.provenance.ptrs, offset, size)
-}
-
-/// Return the start offset of the first provenance entry that lies inside
-/// the aggregate's byte range but inside none of its fields.
-///
-/// Field translation consumes (thin pointer) or rejects (every other kind)
-/// the relocations under the bytes it decodes, so a survivor here sits in
-/// padding: no field would ever consume it, and dropping it would silently
-/// strip a pointer from the constant. Generic over the payload so the audit
-/// is unit testable without a rustc session.
-fn find_unconsumed_relocation<P>(
-    ptrs: &[(usize, P)],
-    aggregate_start: usize,
-    aggregate_size: usize,
-    field_ranges: &[(usize, usize)],
-) -> Option<usize> {
-    let aggregate_end = aggregate_start.saturating_add(aggregate_size);
-    ptrs.iter().map(|(pos, _)| *pos).find(|&pos| {
-        pos >= aggregate_start
-            && pos < aggregate_end
-            && !field_ranges
-                .iter()
-                .any(|&(start, size)| pos >= start && pos < start.saturating_add(size))
-    })
-}
-
-/// Fail-closed audit run after all of an aggregate's fields have been
-/// translated: any relocation inside the aggregate's byte range that no
-/// field consumed is a hard error.
-fn audit_aggregate_relocations(
-    alloc: &rustc_public::ty::Allocation,
-    aggregate_start: usize,
-    aggregate_size: usize,
-    field_ranges: &[(usize, usize)],
-    what: &str,
-    loc: &Location,
-) -> TranslationResult<()> {
-    if let Some(pos) = find_unconsumed_relocation(
-        &alloc.provenance.ptrs,
-        aggregate_start,
-        aggregate_size,
-        field_ranges,
-    ) {
-        return input_err!(
-            loc.clone(),
-            TranslationErr::unsupported(format!(
-                "{what} constant has a pointer relocation at byte {pos} that no field \
-                 consumes; provenance in padding bytes cannot be preserved"
-            ))
-        );
-    }
-    Ok(())
-}
-
-/// Byte width of a constant field: rustc layout when available, the dialect
-/// type's storage size as a fallback. Shared by the scalar decode path and
-/// the per-aggregate relocation audit so both see the same field extents.
-fn constant_field_byte_size(
-    ctx: &Context,
-    rust_ty: &rustc_public::ty::Ty,
-    ty_ptr: TypeHandle,
-    loc: &Location,
-) -> TranslationResult<usize> {
-    rust_type_layout_size(*rust_ty, loc.clone()).or_else(|_| {
-        constant_storage_size(ctx, ty_ptr).ok_or_else(|| {
-            input_error!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Cannot determine storage size for constant field of type {rust_ty:?}"
-                ))
-            )
-        })
-    })
-}
-
-/// Decode one typed value from an allocation at an absolute byte offset,
-/// preserving supported pointer provenance. Thin pointer fields resolve through
-/// [`translate_thin_pointer_at_alloc_offset`]; slice fields pair the relocated
-/// data word with their literal length metadata.
-fn translate_constant_value_from_alloc(
-    ctx: &mut Context,
-    alloc: &rustc_public::ty::Allocation,
-    absolute_byte_offset: usize,
-    rust_ty: &rustc_public::ty::Ty,
-    ty_ptr: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    use rustc_public::ty::{RigidTy, TyKind};
-
-    let is_ptr = ty_ptr.deref(ctx).is::<dialect_mir::types::MirPtrType>();
-    if is_ptr {
-        return translate_thin_pointer_at_alloc_offset(
-            ctx,
-            alloc,
-            absolute_byte_offset,
-            ty_ptr,
-            block_ptr,
-            prev_op,
-            loc,
-        );
-    }
-
-    let is_slice = ty_ptr.deref(ctx).is::<dialect_mir::types::MirSliceType>();
-    if is_slice {
-        let size = rust_type_layout_size(*rust_ty, loc.clone())?;
-        let field_end = absolute_byte_offset.checked_add(size).ok_or_else(|| {
-            input_error!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Slice field at byte {absolute_byte_offset} with size {size} overflowed"
-                ))
-            )
-        })?;
-        let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
-        let overlaps = relocation_offsets_overlapping_range(
-            &alloc.provenance.ptrs,
-            absolute_byte_offset,
-            field_end,
-            pointer_width,
-        );
-        if !overlaps.is_empty() {
-            return translate_slice_at_alloc_offset(
-                ctx,
-                alloc,
-                absolute_byte_offset,
-                rust_ty,
-                block_ptr,
-                prev_op,
-                loc,
-            );
-        }
-        let bytes = alloc_slice_bytes_zeroing_uninit(
-            alloc,
-            absolute_byte_offset,
-            size,
-            "Slice field",
-            &loc,
-        )?;
-        return translate_constant_value_from_bytes(
-            ctx, rust_ty, ty_ptr, &bytes, block_ptr, prev_op, loc,
-        );
-    }
-
-    let is_tuple = ty_ptr.deref(ctx).is::<dialect_mir::types::MirTupleType>();
-    if is_tuple {
-        return translate_tuple_constant_from_alloc(
-            ctx,
-            alloc,
-            absolute_byte_offset,
-            rust_ty,
-            ty_ptr,
-            block_ptr,
-            prev_op,
-            loc,
-        );
-    }
-
-    let is_struct = ty_ptr.deref(ctx).is::<dialect_mir::types::MirStructType>();
-    if is_struct {
-        return translate_struct_constant_from_alloc(
-            ctx,
-            alloc,
-            absolute_byte_offset,
-            rust_ty,
-            ty_ptr,
-            block_ptr,
-            prev_op,
-            loc,
-        );
-    }
-
-    let is_union = ty_ptr.deref(ctx).is::<dialect_mir::types::MirUnionType>();
-    if is_union {
-        return translate_union_constant_from_alloc(
-            ctx,
-            alloc,
-            absolute_byte_offset,
-            rust_ty,
-            ty_ptr,
-            block_ptr,
-            prev_op,
-            loc,
-        );
-    }
-
-    let is_array = ty_ptr.deref(ctx).is::<dialect_mir::types::MirArrayType>();
-    if is_array {
-        return translate_array_constant_from_alloc(
-            ctx,
-            alloc,
-            absolute_byte_offset,
-            rust_ty,
-            ty_ptr,
-            block_ptr,
-            prev_op,
-            loc,
-        );
-    }
-
-    let is_enum = ty_ptr.deref(ctx).is::<dialect_mir::types::MirEnumType>();
-    if is_enum {
-        let size = rust_type_layout_size(*rust_ty, loc.clone())?;
-        if alloc_has_provenance_in_range(alloc, absolute_byte_offset, size) {
-            return translate_enum_constant_from_alloc(
-                ctx,
-                alloc,
-                absolute_byte_offset,
-                rust_ty,
-                ty_ptr,
-                block_ptr,
-                prev_op,
-                loc,
-            );
-        }
-    }
-
-    let size = constant_field_byte_size(ctx, rust_ty, ty_ptr, &loc)?;
-    // Fail closed: the bytes under a relocation are an addend into the target
-    // allocation, not literal data. Decoding them as a non-pointer value
-    // would silently strip the pointer they represent.
-    if alloc_has_provenance_in_range(alloc, absolute_byte_offset, size) {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Constant field of type {rust_ty:?} at byte offset {absolute_byte_offset} \
-                 overlaps a pointer relocation; only supported pointer or slice fields can \
-                 carry provenance in aggregate constants"
-            ))
-        );
-    }
-    // ZSTs: layout size 0.
-    if size == 0 || types::is_zst_type(ctx, ty_ptr) {
-        // Still need Rust ADT metadata for empty aggregates.
-        if matches!(
-            rust_ty.kind(),
-            TyKind::RigidTy(RigidTy::Tuple(_)) | TyKind::RigidTy(RigidTy::Adt(_, _))
-        ) {
-            let bytes = alloc_slice_bytes_zeroing_uninit(
-                alloc,
-                absolute_byte_offset,
-                size,
-                "ZST field",
-                &loc,
-            )?;
-            return translate_constant_value_from_bytes(
-                ctx, rust_ty, ty_ptr, &bytes, block_ptr, prev_op, loc,
-            );
-        }
-        return translate_zero_sized_constant_value(ctx, ty_ptr, block_ptr, prev_op, loc);
-    }
-
-    let bytes = alloc_slice_bytes_zeroing_uninit(
-        alloc,
-        absolute_byte_offset,
-        size,
-        "Constant field",
-        &loc,
-    )?;
-    translate_constant_value_from_bytes(ctx, rust_ty, ty_ptr, &bytes, block_ptr, prev_op, loc)
-}
-
-fn translate_tuple_constant_from_alloc(
-    ctx: &mut Context,
-    alloc: &rustc_public::ty::Allocation,
-    base_offset: usize,
-    rust_ty: &rustc_public::ty::Ty,
-    const_ty_ptr: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let field_types: Vec<TypeHandle> = {
-        let ty_ref = const_ty_ptr.deref(ctx);
-        let tuple_ty = ty_ref
-            .downcast_ref::<dialect_mir::types::MirTupleType>()
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(
-                    "translate_tuple_constant_from_alloc called on non-tuple type"
-                ))
-            })?;
-        tuple_ty.get_types().to_vec()
-    };
-
-    let rust_field_types = match rust_ty.kind() {
-        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Tuple(fields)) => {
-            fields.to_vec()
-        }
-        other => {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Tuple constant expected Rust tuple type, got {other:?}"
-                ))
-            );
-        }
-    };
-    if field_types.len() != rust_field_types.len() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Tuple constant type mismatch: MIR has {} fields, Rust type has {}",
-                field_types.len(),
-                rust_field_types.len()
-            ))
-        );
-    }
-
-    let field_offsets = super::layout::aggregate_field_offsets(rust_ty, "Tuple", &loc)?;
-    if field_offsets.len() != field_types.len() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Tuple constant layout has {} offsets for {} fields",
-                field_offsets.len(),
-                field_types.len()
-            ))
-        );
-    }
-
-    let mut values = Vec::with_capacity(field_types.len());
-    let mut field_ranges = Vec::with_capacity(field_types.len());
-    let mut current_prev_op = prev_op;
-    for (field_idx, (field_ty, rust_field_ty)) in field_types
-        .iter()
-        .copied()
-        .zip(rust_field_types.iter())
-        .enumerate()
-    {
-        let abs = base_offset
-            .checked_add(field_offsets[field_idx])
-            .ok_or_else(|| {
-                input_error!(
-                    loc.clone(),
-                    TranslationErr::unsupported(format!(
-                        "Tuple constant field {field_idx} offset overflowed"
-                    ))
-                )
-            })?;
-        let field_size = constant_field_byte_size(ctx, rust_field_ty, field_ty, &loc)?;
-        field_ranges.push((abs, field_size));
-        let (value, new_prev_op) = translate_constant_value_from_alloc(
-            ctx,
-            alloc,
-            abs,
-            rust_field_ty,
-            field_ty,
-            block_ptr,
-            current_prev_op,
-            loc.clone(),
-        )?;
-        values.push(value);
-        current_prev_op = new_prev_op;
-    }
-
-    let tuple_size = rust_type_layout_size(*rust_ty, loc.clone())?;
-    audit_aggregate_relocations(alloc, base_offset, tuple_size, &field_ranges, "Tuple", &loc)?;
-
-    use dialect_mir::ops::MirConstructTupleOp;
-    let op = Operation::new(
-        ctx,
-        MirConstructTupleOp::get_concrete_op_info(),
-        vec![const_ty_ptr],
-        values,
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc);
-    if let Some(prev) = current_prev_op {
-        op.insert_after(ctx, prev);
-    } else {
-        op.insert_at_front(block_ptr, ctx);
-    }
-    Ok((op.deref(ctx).get_result(0), Some(op)))
-}
-
-fn translate_struct_constant_from_alloc(
-    ctx: &mut Context,
-    alloc: &rustc_public::ty::Allocation,
-    base_offset: usize,
-    rust_ty: &rustc_public::ty::Ty,
-    const_ty_ptr: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    use rustc_public::ty::{RigidTy, TyKind};
-
-    let field_types: Vec<TypeHandle> = {
-        let ty_obj = const_ty_ptr.deref(ctx);
-        let struct_ty = ty_obj
-            .downcast_ref::<dialect_mir::types::MirStructType>()
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(
-                    "translate_struct_constant_from_alloc called on non-struct type"
-                ))
-            })?;
-        struct_ty.field_types().to_vec()
-    };
-
-    // A zero-sized struct span holds no bytes and cannot carry relocations,
-    // and not every type that lands here as a MirStructType is an ADT:
-    // function items and non-capturing closures have no ADT metadata to
-    // consult. Synthesize such values from the dialect type alone.
-    let struct_size = rust_ty
-        .layout()
-        .map_err(|e| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Failed to query layout for struct constant: {:?}",
-                e
-            )))
-        })?
-        .shape()
-        .size
-        .bytes();
-    if struct_size == 0 {
-        return translate_zero_sized_constant_value(ctx, const_ty_ptr, block_ptr, prev_op, loc);
-    }
-
-    let field_offsets = super::layout::aggregate_field_offsets(rust_ty, "Struct", &loc)?;
-    if field_offsets.len() != field_types.len() {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Struct constant layout has {} field offsets, type has {} fields",
-                field_offsets.len(),
-                field_types.len()
-            ))
-        );
-    }
-
-    let (adt_def, substs) = match rust_ty.kind() {
-        TyKind::RigidTy(RigidTy::Adt(adt_def, substs)) => (adt_def, substs),
-        other => {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "Expected ADT Rust type for struct constant, got {other:?}"
-                ))
-            );
-        }
-    };
-    let variants = adt_def.variants();
-    let struct_variant = variants.first().ok_or_else(|| {
-        input_error_noloc!(TranslationErr::unsupported(
-            "Struct ADT has no variants in metadata"
-        ))
-    })?;
-
-    let mut field_values = Vec::with_capacity(field_types.len());
-    let mut field_ranges = Vec::with_capacity(field_types.len());
-    let mut current_prev_op = prev_op;
-    for (field_idx, field_ty_ptr) in field_types.iter().copied().enumerate() {
-        let fields = struct_variant.fields();
-        let rust_field = fields.get(field_idx).ok_or_else(|| {
-            input_error_noloc!(TranslationErr::unsupported(format!(
-                "Struct constant field {field_idx} is missing in rustc ADT metadata ({} field(s) recorded)",
-                fields.len()
-            )))
-        })?;
-        let rust_field_ty = rust_field.ty_with_args(&substs);
-        let abs = base_offset
-            .checked_add(field_offsets[field_idx])
-            .ok_or_else(|| {
-                input_error!(
-                    loc.clone(),
-                    TranslationErr::unsupported(format!(
-                        "Struct constant field {field_idx} offset overflowed"
-                    ))
-                )
-            })?;
-        let field_size = constant_field_byte_size(ctx, &rust_field_ty, field_ty_ptr, &loc)?;
-        field_ranges.push((abs, field_size));
-        let (field_val, new_prev_op) = translate_constant_value_from_alloc(
-            ctx,
-            alloc,
-            abs,
-            &rust_field_ty,
-            field_ty_ptr,
-            block_ptr,
-            current_prev_op,
-            loc.clone(),
-        )?;
-        field_values.push(field_val);
-        current_prev_op = new_prev_op;
-    }
-
-    let struct_size = rust_type_layout_size(*rust_ty, loc.clone())?;
-    audit_aggregate_relocations(
-        alloc,
-        base_offset,
-        struct_size,
-        &field_ranges,
-        "Struct",
-        &loc,
-    )?;
-
-    let (casted_field_values, prev_after_casts) = cast_struct_fields_to_expected_types(
-        ctx,
-        field_values,
-        const_ty_ptr,
-        block_ptr,
-        current_prev_op,
-        loc.clone(),
-    );
-
-    let op = Operation::new(
-        ctx,
-        MirConstructStructOp::get_concrete_op_info(),
-        vec![const_ty_ptr],
-        casted_field_values,
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc);
-    if let Some(prev) = prev_after_casts {
-        op.insert_after(ctx, prev);
-    } else {
-        op.insert_at_front(block_ptr, ctx);
-    }
-    Ok((op.deref(ctx).get_result(0), Some(op)))
-}
-
-/// Element kinds admitted by a bare array value constant
-/// (`translate_array_value_constant`).
-///
-/// Primitive scalars, enums, initialized unions, tuples, structs, and nested
-/// arrays are supported at this entry point. Nested arrays are walked
-/// recursively so an unsupported leaf cannot hide behind nesting. Struct
-/// elements reuse the same layout-aware aggregate decoders used when structs
-/// appear inside other constants. Arrays inside struct or tuple constants are
-/// dispatched through [`translate_constant_value_from_alloc`] and are not
-/// governed by this gate.
-fn validate_array_value_element_type(
-    ctx: &Context,
-    element_ty: TypeHandle,
-    loc: &Location,
-) -> TranslationResult<()> {
-    let nested_element_ty = {
-        let elem_obj = element_ty.deref(ctx);
-        if elem_obj.is::<IntegerType>()
-            || elem_obj.is::<MirFP16Type>()
-            || elem_obj.is::<FP32Type>()
-            || elem_obj.is::<FP64Type>()
-            || elem_obj.is::<dialect_mir::types::MirTupleType>()
-            || elem_obj.is::<dialect_mir::types::MirStructType>()
-            || elem_obj.is::<dialect_mir::types::MirEnumType>()
-            || elem_obj.is::<dialect_mir::types::MirUnionType>()
-        {
-            return Ok(());
-        }
-        let Some(array_ty) = elem_obj.downcast_ref::<dialect_mir::types::MirArrayType>() else {
-            return input_err!(
-                loc.clone(),
-                TranslationErr::unsupported(format!(
-                    "Array constant element type is not supported: {:?}. Supported array \
-                     constants are primitive scalars, enums, initialized unions, tuples, \
-                     structs, or nested arrays of those.",
-                    elem_obj
-                ))
-            );
-        };
-        array_ty.element_type()
-    };
-    validate_array_value_element_type(ctx, nested_element_ty, loc)
-}
-
-fn translate_array_constant_from_alloc(
-    ctx: &mut Context,
-    alloc: &rustc_public::ty::Allocation,
-    base_offset: usize,
-    rust_array_ty: &rustc_public::ty::Ty,
-    array_ty: TypeHandle,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let (element_ty_ptr, element_count) = {
-        let arr_ty_obj = array_ty.deref(ctx);
-        let arr_ty = arr_ty_obj
-            .downcast_ref::<dialect_mir::types::MirArrayType>()
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(
-                    "translate_array_constant_from_alloc: expected array type"
-                ))
-            })?;
-        (arr_ty.element_type(), arr_ty.size())
-    };
-
-    let (rust_element_ty, rust_element_count) = rust_array_type_info(*rust_array_ty, loc.clone())?;
-    if rust_element_count != element_count {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "Array constant length mismatch: Rust type has {rust_element_count} elements, \
-                 dialect type has {element_count}"
-            ))
-        );
-    }
-    let element_byte_size = rust_type_layout_size(rust_element_ty, loc.clone())?;
-    let element_count_usize = usize::try_from(element_count).map_err(|_| {
-        input_error_noloc!(TranslationErr::unsupported(format!(
-            "Array constant element count {element_count} does not fit usize"
-        )))
-    })?;
-
-    let mut element_values = Vec::with_capacity(element_count_usize);
-    let mut element_ranges = Vec::with_capacity(element_count_usize);
-    let mut last_op = prev_op;
-    for i in 0..element_count_usize {
-        let abs = base_offset
-            .checked_add(i.checked_mul(element_byte_size).ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Array constant element {i} stride overflowed"
-                )))
-            })?)
-            .ok_or_else(|| {
-                input_error_noloc!(TranslationErr::unsupported(format!(
-                    "Array constant element {i} absolute offset overflowed"
-                )))
-            })?;
-        element_ranges.push((abs, element_byte_size));
-        let (elem_val, elem_last_op) = translate_constant_value_from_alloc(
-            ctx,
-            alloc,
-            abs,
-            &rust_element_ty,
-            element_ty_ptr,
-            block_ptr,
-            last_op,
-            loc.clone(),
-        )?;
-        element_values.push(elem_val);
-        last_op = elem_last_op;
-    }
-
-    let array_size = rust_type_layout_size(*rust_array_ty, loc.clone())?;
-    audit_aggregate_relocations(
-        alloc,
-        base_offset,
-        array_size,
-        &element_ranges,
-        "Array",
-        &loc,
-    )?;
-
-    let op = Operation::new(
-        ctx,
-        MirConstructArrayOp::get_concrete_op_info(),
-        vec![array_ty],
-        element_values,
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc);
-    if let Some(prev) = last_op {
-        op.insert_after(ctx, prev);
-    } else {
-        op.insert_at_front(block_ptr, ctx);
-    }
-    Ok((op.deref(ctx).get_result(0), Some(op)))
-}
-
-#[derive(Clone, Copy)]
-struct MaterializedStaticGlobal {
-    base_ptr: Value,
-    global_op: Ptr<Operation>,
-    allocation_size: u64,
-}
-
-struct StaticGlobalMaterializationState {
-    globals: std::collections::HashMap<String, MaterializedStaticGlobal>,
-    last_op: Option<Ptr<Operation>>,
-}
-
-/// Materialize one device static and every static reachable from its initializer.
-///
-/// The current global is registered before traversing its relocations. That
-/// makes self-references and mutually recursive static graphs finite while the
-/// lowering pass still performs module-wide deduplication by `global_key`.
-fn ensure_static_global_alloc(
-    ctx: &mut Context,
-    static_def: &rustc_public::mir::mono::StaticDef,
-    is_mutable: bool,
-    block_ptr: Ptr<BasicBlock>,
-    loc: Location,
-    state: &mut StaticGlobalMaterializationState,
-) -> TranslationResult<MaterializedStaticGlobal> {
-    let global_key = static_global_key(static_def);
-    if let Some(existing) = state.globals.get(&global_key) {
-        return Ok(*existing);
-    }
-
-    let initializer = static_initializer_data(static_def, loc.clone())?;
-    let allocation_size = initializer.bytes.len() as u64;
-    let initializer_hex = bytes_to_hex(&initializer.bytes);
-    let static_ty = static_def.ty();
-    let is_constant = is_constant_wrapper_type(&static_ty);
-    let global_ty = types::translate_type(ctx, &static_ty)?;
-
-    if let Some(union_name) = stored_type_union_name(static_ty, &mut Vec::new()) {
-        if global_ty
-            .deref(ctx)
-            .is::<dialect_mir::types::MirUnionType>()
-        {
-            validate_device_static_union_initializer(
-                ctx,
-                static_def,
-                global_ty,
-                &initializer,
-                loc.clone(),
-            )?;
-        } else {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "device static {} contains nested union `{union_name}`; device-global \
-                     union initializer relocations are supported only for a top-level \
-                     thin-pointer union",
-                    static_def.name()
-                ))
-            );
-        }
-    }
-    let global_ptr_ty: TypeHandle = if is_constant {
-        dialect_mir::types::MirPtrType::get_constant(ctx, global_ty, is_mutable).into()
-    } else {
-        dialect_mir::types::MirPtrType::get_global(ctx, global_ty, is_mutable).into()
-    };
-
-    let global_op = Operation::new(
-        ctx,
-        MirGlobalAllocOp::get_concrete_op_info(),
-        vec![global_ptr_ty],
-        vec![],
-        vec![],
-        0,
-    );
-    global_op.deref_mut(ctx).set_loc(loc.clone());
-
-    let global_alloc = MirGlobalAllocOp::new(global_op);
-
-    use pliron::builtin::attributes::{StringAttr, TypeAttr};
-
-    global_alloc.set_attr_global_type(ctx, TypeAttr::new(global_ty));
-    global_alloc.set_attr_global_key(ctx, StringAttr::new(global_key.clone()));
-    set_global_initializer_hex_attr(ctx, global_alloc.get_operation(), &initializer_hex);
-    if !initializer.relocations.is_empty() {
-        let encoded = encode_global_initializer_relocations(&initializer.relocations);
-        set_global_initializer_relocations_attr(ctx, global_alloc.get_operation(), &encoded);
-    }
-
-    if initializer.alignment > 0 {
-        global_alloc.set_alignment_value(ctx, initializer.alignment);
-    }
-
-    match state.last_op {
-        Some(previous) => global_alloc.get_operation().insert_after(ctx, previous),
-        None => global_alloc.get_operation().insert_at_front(block_ptr, ctx),
-    }
-    state.last_op = Some(global_alloc.get_operation());
-
-    let materialized = MaterializedStaticGlobal {
-        base_ptr: global_alloc.get_operation().deref(ctx).get_result(0),
-        global_op: global_alloc.get_operation(),
-        allocation_size,
-    };
-    state.globals.insert(global_key, materialized);
-
-    let owner_description = format!("device static {}", static_def.name());
-    ensure_initializer_relocation_targets(
-        ctx,
-        &initializer.relocations,
-        &owner_description,
-        block_ptr,
-        loc,
-        state,
-    )?;
-
-    Ok(materialized)
-}
-
-/// Materialize and validate every static referenced by an initializer.
-///
-/// The owner is already registered by [`ensure_static_global_alloc`] before
-/// recursion reaches this helper, so self-references and mutually recursive
-/// static graphs remain finite.
-fn ensure_initializer_relocation_targets(
-    ctx: &mut Context,
-    relocations: &[GlobalInitializerRelocation],
-    owner_description: &str,
-    block_ptr: Ptr<BasicBlock>,
-    loc: Location,
-    state: &mut StaticGlobalMaterializationState,
-) -> TranslationResult<()> {
-    for relocation in relocations {
-        let target = ensure_static_global_alloc(
-            ctx,
-            &relocation.target_static,
-            false,
-            block_ptr,
-            loc.clone(),
-            state,
-        )?;
-        if relocation.target_addend > target.allocation_size {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "{owner_description} relocation at byte {} points {} bytes into {}, but the target allocation is only {} bytes",
-                    relocation.source_offset,
-                    relocation.target_addend,
-                    relocation.target_static.name(),
-                    target.allocation_size
-                ))
-            );
-        }
-    }
-    Ok(())
-}
-
-fn translate_static_global_pointer(
-    ctx: &mut Context,
-    static_def: &rustc_public::mir::mono::StaticDef,
-    result_pointee_ty: TypeHandle,
-    result_ptr_ty: TypeHandle,
-    is_mutable: bool,
-    byte_offset: u64,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
-    let mut state = StaticGlobalMaterializationState {
-        globals: std::collections::HashMap::new(),
-        last_op: prev_op,
-    };
-    let materialized = ensure_static_global_alloc(
-        ctx,
-        static_def,
-        is_mutable,
-        block_ptr,
-        loc.clone(),
-        &mut state,
-    )?;
-
-    // Rust const evaluation permits forming a pointer one past the end of
-    // an allocation (offset == allocation size); only offsets strictly
-    // beyond the allocation are impossible for rustc to have produced.
-    // Forming the pointer is what is translated here, so the check must
-    // not add a pointee-size term.
-    if byte_offset > materialized.allocation_size {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "constant pointer to device static {} has byte offset {}, \
-                 but the static allocation is only {} bytes",
-                static_def.name(),
-                byte_offset,
-                materialized.allocation_size
-            ))
-        );
-    }
-
-    let base_ptr = materialized.base_ptr;
-    let insert_after = state.last_op.unwrap_or(materialized.global_op);
-
-    let (base_pointee_ty, address_space) = {
-        let base_ty = base_ptr.get_type(ctx);
-        let base_ty = base_ty.deref(ctx);
-        let base_ptr_ty = base_ty
-            .downcast_ref::<dialect_mir::types::MirPtrType>()
-            .expect("MirGlobalAllocOp must return MirPtrType");
-        (base_ptr_ty.pointee, base_ptr_ty.address_space)
-    };
-
-    // Preserve the existing direct path. It avoids generating unnecessary
-    // casts and pointer arithmetic for ordinary references to whole statics.
-    // The result is still normalized to the exact translated Rust operand
-    // type: slot stores and mem2reg are type-strict, so the physical
-    // address-space pointer must not leak into the function body. A zero-addend
-    // relocation may still name the first element of an array static (or an
-    // equivalent differently typed view). Keep those on the byte-addressed
-    // path below so `StaticAddress` establishes only the final kind/address
-    // space after generic Erased casts have normalized the pointee shape.
-    if byte_offset == 0 && base_pointee_ty == result_pointee_ty {
-        let (result, last_op) =
-            retype_static_pointer_result(ctx, base_ptr, result_ptr_ty, insert_after, loc);
-        return Ok((result, Some(last_op)));
-    }
-
-    // mir.ptr_offset scales by sizeof(pointee). Cast to u8 first so the
-    // rustc addend is interpreted as bytes rather than static elements.
-    let byte_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Unsigned).into();
-
-    let byte_ptr_ty: TypeHandle =
-        dialect_mir::types::MirPtrType::get(ctx, byte_ty, is_mutable, address_space).into();
-
-    // The address arithmetic stays in the static's physical address space
-    // (LLVM GEPs cannot change address spaces); the exact-Rust-type
-    // normalization happens once, at the end.
-    let interior_ptr_ty: TypeHandle =
-        dialect_mir::types::MirPtrType::get(ctx, result_pointee_ty, is_mutable, address_space)
-            .into();
-
-    // 1. *StaticType addrspace(N) -> *u8 addrspace(N)
-    let to_byte_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![byte_ptr_ty],
-        vec![base_ptr],
-        vec![],
-        0,
-    );
-    to_byte_op.deref_mut(ctx).set_loc(loc.clone());
-
-    let to_byte_cast = MirCastOp::new(to_byte_op);
-    to_byte_cast.set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-    to_byte_cast.get_operation().insert_after(ctx, insert_after);
-
-    let byte_ptr = to_byte_cast.get_operation().deref(ctx).get_result(0);
-
-    // 2. Materialize the rustc byte addend as usize.
-    let offset_ty = types::get_usize_type(ctx);
-    let offset_attr = pliron::builtin::attributes::IntegerAttr::new(
-        offset_ty,
-        APInt::from_u64(
-            byte_offset,
-            NonZeroUsize::new(64).expect("usize must have non-zero width"),
-        ),
-    );
-
-    let offset_const_op = Operation::new(
-        ctx,
-        MirConstantOp::get_concrete_op_info(),
-        vec![offset_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    offset_const_op.deref_mut(ctx).set_loc(loc.clone());
-
-    let offset_const = MirConstantOp::new(offset_const_op);
-    offset_const.set_attr_value(ctx, offset_attr);
-    offset_const
-        .get_operation()
-        .insert_after(ctx, to_byte_cast.get_operation());
-
-    let offset_value = offset_const.get_operation().deref(ctx).get_result(0);
-
-    // 3. Apply the addend. Since the pointer now points to u8, one element
-    // equals exactly one byte.
-    let ptr_offset_op = Operation::new(
-        ctx,
-        MirPtrOffsetOp::get_concrete_op_info(),
-        vec![byte_ptr_ty],
-        vec![byte_ptr, offset_value],
-        vec![],
-        0,
-    );
-    ptr_offset_op.deref_mut(ctx).set_loc(loc.clone());
-    ptr_offset_op.insert_after(ctx, offset_const.get_operation());
-
-    let offset_byte_ptr = ptr_offset_op.deref(ctx).get_result(0);
-
-    // 4. *u8 addrspace(N) -> *ResultPointee addrspace(N)
-    let result_cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![interior_ptr_ty],
-        vec![offset_byte_ptr],
-        vec![],
-        0,
-    );
-    result_cast_op.deref_mut(ctx).set_loc(loc.clone());
-
-    let result_cast = MirCastOp::new(result_cast_op);
-    result_cast.set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-    result_cast.get_operation().insert_after(ctx, ptr_offset_op);
-
-    // 5. Normalize to the exact translated Rust operand type (lowering
-    // emits an `addrspacecast` when the address spaces differ).
-    let result = result_cast.get_operation().deref(ctx).get_result(0);
-    let (result, last_op) =
-        retype_static_pointer_result(ctx, result, result_ptr_ty, result_cast.get_operation(), loc);
-    Ok((result, Some(last_op)))
-}
-
-/// Retype a materialized static-pointer `value` to the exact translated Rust
-/// operand type.
-///
-/// `MirGlobalAllocOp` results (and interior-pointer arithmetic built on
-/// them) carry the static's physical address space, but slot stores and
-/// mem2reg are type-strict: the constant operand must have the exact
-/// translated Rust type. Lowering turns this `PtrToPtr` cast into an
-/// `addrspacecast` when the address spaces differ, which
-/// `InferAddressSpaces` later folds back through for direct loads.
-fn retype_static_pointer_result(
-    ctx: &mut Context,
-    value: Value,
-    result_ptr_ty: TypeHandle,
-    insert_after: Ptr<Operation>,
-    loc: Location,
-) -> (Value, Ptr<Operation>) {
-    if value.get_type(ctx) == result_ptr_ty {
-        return (value, insert_after);
-    }
-
-    let cast_op = Operation::new(
-        ctx,
-        MirCastOp::get_concrete_op_info(),
-        vec![result_ptr_ty],
-        vec![value],
-        vec![],
-        0,
-    );
-    cast_op.deref_mut(ctx).set_loc(loc);
-    let cast = MirCastOp::new(cast_op);
-    cast.set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
-    if result_ptr_ty
-        .deref(ctx)
-        .downcast_ref::<dialect_mir::types::MirPtrType>()
-        .is_some_and(|pointer| pointer.kind != MirPointerKind::Erased)
-    {
-        cast.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::StaticAddress);
-    }
-    cast_op.insert_after(ctx, insert_after);
-
-    (cast_op.deref(ctx).get_result(0), cast_op)
-}
-
-/// Return the first union stored inline in `ty`.
-///
-/// Pointer pointees are deliberately not followed: their bytes are not part of
-/// the containing allocation, and initializer relocations are collected through
-/// rustc provenance separately. Arrays, tuples, structs, and enum payloads are
-/// inline and must be searched recursively.
-fn stored_type_union_name(
-    ty: rustc_public::ty::Ty,
-    visited: &mut Vec<rustc_public::ty::Ty>,
-) -> Option<String> {
-    use rustc_public::ty::{AdtKind, RigidTy, TyKind};
-
-    if visited.contains(&ty) {
-        return None;
-    }
-    visited.push(ty);
-
-    match ty.kind() {
-        TyKind::RigidTy(RigidTy::Adt(adt_def, substs)) => {
-            if matches!(adt_def.kind(), AdtKind::Union) {
-                return Some(adt_def.trimmed_name());
-            }
-            for variant in adt_def.variants() {
-                for field in variant.fields() {
-                    if let Some(name) = stored_type_union_name(field.ty_with_args(&substs), visited)
-                    {
-                        return Some(name);
-                    }
-                }
-            }
-            None
-        }
-        TyKind::RigidTy(RigidTy::Array(element, _)) | TyKind::RigidTy(RigidTy::Slice(element)) => {
-            stored_type_union_name(element, visited)
-        }
-        TyKind::RigidTy(RigidTy::Tuple(elements)) => {
-            for element in elements.iter() {
-                if let Some(name) = stored_type_union_name(*element, visited) {
-                    return Some(name);
-                }
-            }
-            None
-        }
-        _ => None,
-    }
-}
-
-fn set_global_initializer_hex_attr(ctx: &mut Context, op: Ptr<Operation>, initializer_hex: &str) {
-    use pliron::builtin::attributes::StringAttr;
-    use pliron::identifier::Identifier;
-
-    let key = Identifier::try_new("global_initializer_hex".to_string()).expect("valid identifier");
-    op.deref_mut(ctx)
-        .attributes
-        .set(key, StringAttr::new(initializer_hex.to_string()));
-}
-
-fn set_global_initializer_relocations_attr(
-    ctx: &mut Context,
-    op: Ptr<Operation>,
-    relocations: &str,
-) {
-    use pliron::builtin::attributes::StringAttr;
-    use pliron::identifier::Identifier;
-
-    let key = Identifier::try_new("global_initializer_relocations".to_string())
-        .expect("valid identifier");
-    op.deref_mut(ctx)
-        .attributes
-        .set(key, StringAttr::new(relocations.to_string()));
-}
-
-/// Check if a type is a pointer/reference to a static allocation.
-/// Returns `(pointee_ty, origin)` when the type can carry a static address.
-/// Keeping the origin here prevents constant materialization from collapsing
-/// `&T`/`&mut T` and raw pointers before they enter `dialect-mir`.
-use super::values::is_constant_wrapper_type;
-
-fn get_static_pointer_info(
-    ty: &rustc_public::ty::Ty,
-) -> Option<(rustc_public::ty::Ty, facts::PointerOrigin)> {
-    facts::pointer_origin_of_ty(ty)
-}
-
-/// Extract element type, size, and alignment from a pointer to SharedArray<T, N, ALIGN>.
-/// Returns (element_type, size, alignment) where alignment is 0 for natural alignment.
-fn extract_shared_array_info(
-    ctx: &mut Context,
-    ty: &rustc_public::ty::Ty,
-) -> TranslationResult<(pliron::r#type::TypeHandle, usize, usize)> {
-    use rustc_public::ty::{GenericArgKind, RigidTy, TyKind};
-
-    match ty.kind() {
-        TyKind::RigidTy(RigidTy::RawPtr(pointee_ty, _)) => {
-            match pointee_ty.kind() {
-                TyKind::RigidTy(RigidTy::Adt(adt_def, substs)) => {
-                    if !types::is_cuda_device_adt(&adt_def, "SharedArray") {
-                        return input_err_noloc!(TranslationErr::unsupported(format!(
-                            "Expected cuda_device::SharedArray, got {}",
-                            adt_def.trimmed_name()
-                        )));
-                    }
-
-                    let generic_args = &substs.0;
-
-                    // SharedArray substs arrive in declaration order, with
-                    // the ALIGN default already materialized by rustc:
-                    //
-                    //   SharedArray<T, N, ALIGN = 0>
-                    //     [0] T      type
-                    //     [1] N      const usize (element count)
-                    //     [2] ALIGN  const usize (0 = natural alignment)
-                    //
-                    // Reads are positional on purpose: if N fails to
-                    // evaluate that's an error, never "slide over and read
-                    // ALIGN as N". If cuda-device ever reorders these
-                    // generics, this read must change in the same commit.
-                    debug_assert!(
-                        generic_args.len() == 2 || generic_args.len() == 3,
-                        "SharedArray is declared <T, const N, const ALIGN = 0>; \
-                         got {} generic args",
-                        generic_args.len()
-                    );
-
-                    let Some(GenericArgKind::Type(elem_ty)) = generic_args.first() else {
-                        return input_err_noloc!(TranslationErr::unsupported(
-                            "SharedArray substs missing the element type at position 0"
-                        ));
-                    };
-
-                    let Some(GenericArgKind::Const(n_const)) = generic_args.get(1) else {
-                        return input_err_noloc!(TranslationErr::unsupported(
-                            "SharedArray substs missing the N const generic at position 1"
-                        ));
-                    };
-                    let size = facts::eval_usize_const(n_const, "SharedArray N", None)? as usize;
-
-                    // ALIGN = 0 means natural alignment (the declaration
-                    // default). Only a genuinely two-generic SharedArray may
-                    // omit it; a present-but-unreadable position 2 is an
-                    // error, silently dropping a user-requested
-                    // over-alignment would miscompile.
-                    let alignment = match generic_args.get(2) {
-                        Some(GenericArgKind::Const(align_const)) => {
-                            facts::eval_usize_const(align_const, "SharedArray ALIGN", None)?
-                                as usize
-                        }
-                        Some(_) => {
-                            return input_err_noloc!(TranslationErr::unsupported(
-                                "SharedArray substs position 2 is not the ALIGN const generic"
-                            ));
-                        }
-                        None => 0,
-                    };
-
-                    let translated_elem_ty = types::translate_type(ctx, elem_ty)?;
-                    Ok((translated_elem_ty, size, alignment))
-                }
-                _ => input_err_noloc!(TranslationErr::unsupported(
-                    "Expected ADT type for SharedArray"
-                )),
-            }
-        }
-        _ => input_err_noloc!(TranslationErr::unsupported("Expected raw pointer type")),
-    }
-}
-
-/// Create a placeholder `MirConstructEnumOp` for a ghost local.
-///
-/// Ghost locals are MIR locals that are referenced but never assigned — e.g.
-/// rustc optimised away their definition. When translation encounters one we
-/// synthesise a variant-0 enum value with no fields -- the moral equivalent
-/// of LLVM `undef` for an enum.
-///
-/// Typical trigger: `Option<Infallible>` which is always `None` (variant 0,
-/// no payload) after MIR optimisations.
-///
-/// The returned operation is **not** inserted into any block; the caller must
-/// link it via `insert_after` / `insert_at_front`.
-fn create_ghost_enum_default(
-    ctx: &mut Context,
-    ty_ptr: pliron::r#type::TypeHandle,
-    loc: Location,
-) -> Ptr<Operation> {
-    use dialect_mir::ops::MirConstructEnumOp;
-    let op = Operation::new(
-        ctx,
-        MirConstructEnumOp::get_concrete_op_info(),
-        vec![ty_ptr],
-        vec![],
-        vec![],
-        0,
-    );
-    op.deref_mut(ctx).set_loc(loc);
-    MirConstructEnumOp::new(op)
-        .set_attr_construct_enum_variant_index(ctx, dialect_mir::attributes::VariantIndexAttr(0));
-    op
-}
-
-#[cfg(test)]
-mod enum_niche_decode_tests {
-    use super::decode_niche_variant_index;
-
-    #[test]
-    fn i128_relative_value_is_checked_before_usize_conversion() {
-        assert_eq!(
-            decode_niche_variant_index(1u128 << 64, u128::MAX, 0, 0, 1, 2),
-            2,
-            "2^64 must not truncate to relative variant zero on a 64-bit host"
-        );
-    }
-
-    #[test]
-    fn niche_decode_wraps_at_the_carrier_width() {
-        assert_eq!(
-            decode_niche_variant_index(0, u8::MAX.into(), u8::MAX.into(), 3, 4, 1),
-            4,
-            "u8 carrier value 0 is one step after niche_start 255"
-        );
-    }
-}
-
-#[cfg(test)]
-mod tuple_constant_byte_image_tests {
-    use super::tuple_constant_byte_image;
-    use rustc_public::mir::Mutability;
-    use rustc_public::ty::{Allocation, ProvenanceMap};
-
-    #[test]
-    fn zst_tuple_constant_without_allocation_is_an_empty_image() {
-        // `ConstantKind::ZeroSized`-style tuple constants such as `((), ())`
-        // carry no allocation; a zero-byte layout translates as empty bytes.
-        assert_eq!(tuple_constant_byte_image(None, 0), Some(Vec::new()));
-    }
-
-    #[test]
-    fn sized_tuple_constant_without_allocation_is_rejected() {
-        assert_eq!(tuple_constant_byte_image(None, 16), None);
-    }
-
-    #[test]
-    fn allocation_padding_bytes_are_zeroed_deterministically() {
-        let allocation = Allocation {
-            bytes: vec![Some(0xAB), None, None, Some(0xCD)],
-            provenance: ProvenanceMap { ptrs: Vec::new() },
-            align: 4,
-            mutability: Mutability::Not,
-        };
-        assert_eq!(
-            tuple_constant_byte_image(Some(&allocation), 4),
-            Some(vec![0xAB, 0, 0, 0xCD])
-        );
-    }
-}
-
-#[cfg(test)]
-mod pointer_array_constant_type_tests {
-    use super::validate_ptr_to_array_constant_type;
-    use dialect_mir::types::{
-        EnumVariant, MirArrayType, MirEnumType, MirPtrType, MirStructType, MirTupleType,
-    };
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::context::Context;
-    use pliron::location::Location;
-    use pliron::r#type::TypeHandle;
-
-    #[test]
-    fn pointer_array_constant_boundary_admits_recursive_promotable_aggregates() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let primitive_array: TypeHandle = MirArrayType::get(&mut ctx, u32_ty, 3).into();
-        let nested_primitive_array: TypeHandle =
-            MirArrayType::get(&mut ctx, primitive_array, 2).into();
-        assert!(
-            validate_ptr_to_array_constant_type(&ctx, nested_primitive_array, Location::Unknown)
-                .is_ok(),
-            "recursively nested primitive arrays remain supported"
-        );
-
-        let struct_ty: TypeHandle = MirStructType::get(
-            &mut ctx,
-            "PointerArrayElement".into(),
-            vec!["value".into()],
-            vec![u32_ty],
-        )
-        .into();
-        let struct_array: TypeHandle = MirArrayType::get(&mut ctx, struct_ty, 2).into();
-        assert!(
-            validate_ptr_to_array_constant_type(&ctx, struct_array, Location::Unknown).is_ok(),
-            "pointer-to-array constants admit structs whose fields are promotable"
-        );
-
-        // The reference form shares the immutable-promotion gate. A packed
-        // struct whose selected packed LLVM storage reproduces rustc exactly
-        // must therefore be accepted here as well.
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let packed_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedPointerArrayElement".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![],
-            vec![0, 1],
-            5,
-            1,
-        )
-        .into();
-        let packed_struct_array: TypeHandle =
-            MirArrayType::get(&mut ctx, packed_struct_ty, 2).into();
-        assert!(
-            validate_ptr_to_array_constant_type(&ctx, packed_struct_array, Location::Unknown,)
-                .is_ok(),
-            "const R: &[Packed; N] = &TABLE must share the packed immutable global"
-        );
-
-        let nested_struct_array: TypeHandle = MirArrayType::get(&mut ctx, struct_array, 2).into();
-        assert!(
-            validate_ptr_to_array_constant_type(&ctx, nested_struct_array, Location::Unknown)
-                .is_ok(),
-            "nesting preserves a promotable struct leaf"
-        );
-
-        // The shared predicate gates both bare-value promotion and this
-        // reference form. The initializer is rustc's evaluated byte image and
-        // the size-agreement check rejects any layout the dialect reproduces
-        // differently, so recursive tuples and structs travel this path without
-        // rebuilding fields here.
-        let tuple_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![u32_ty]).into();
-        let tuple_array: TypeHandle = MirArrayType::get(&mut ctx, tuple_ty, 2).into();
-        assert!(
-            validate_ptr_to_array_constant_type(&ctx, tuple_array, Location::Unknown).is_ok(),
-            "const R: &[(u32,); N] = &TABLE must pass the same gate the bare table passes"
-        );
-
-        // A tuple containing a promotable struct is recursively admissible too.
-        let tuple_with_struct_ty: TypeHandle =
-            MirTupleType::get(&mut ctx, vec![u32_ty, struct_ty]).into();
-        let tuple_with_struct_array: TypeHandle =
-            MirArrayType::get(&mut ctx, tuple_with_struct_ty, 2).into();
-        assert!(
-            validate_ptr_to_array_constant_type(&ctx, tuple_with_struct_array, Location::Unknown)
-                .is_ok(),
-            "a promotable struct field keeps its tuple in the reference form"
-        );
-
-        // Pointer-bearing structs are promotable now that immutable globals
-        // preserve rustc relocation metadata instead of flattening pointer
-        // placeholder bytes.
-        let pointer_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let pointer_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PointerBearingElement".into(),
-            vec!["pointer".into()],
-            vec![pointer_ty],
-            vec![],
-            vec![0],
-            8,
-            8,
-        )
-        .into();
-        let pointer_struct_array: TypeHandle =
-            MirArrayType::get(&mut ctx, pointer_struct_ty, 2).into();
-        assert!(
-            validate_ptr_to_array_constant_type(&ctx, pointer_struct_array, Location::Unknown)
-                .is_ok(),
-            "pointer-bearing structs are admitted by relocation-aware promotion"
-        );
-    }
-
-    #[test]
-    fn pointer_array_constant_boundary_matches_the_bare_array_gate_for_enums() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let fieldless_variants = vec!["Add", "Sub"]
-            .into_iter()
-            .map(|name| EnumVariant {
-                name: name.into(),
-                field_types: vec![],
-                field_offsets: vec![],
-                field_sizes: vec![],
-            })
-            .collect();
-        let op_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "Op".into(),
-            u32_ty,
-            vec![0, 1],
-            fieldless_variants,
-            0,
-            4,
-            4,
-        )
-        .into();
-        let op_array: TypeHandle = MirArrayType::get(&mut ctx, op_ty, 8).into();
-        assert!(
-            validate_ptr_to_array_constant_type(&ctx, op_array, Location::Unknown).is_ok(),
-            "const R: &[Op; N] = &OPS must pass the same gate the bare table passes"
-        );
-
-        let payload_variants = vec![
-            EnumVariant {
-                name: "None".into(),
-                field_types: vec![],
-                field_offsets: vec![],
-                field_sizes: vec![],
-            },
-            EnumVariant {
-                name: "Some".into(),
-                field_types: vec![u32_ty],
-                field_offsets: vec![4],
-                field_sizes: vec![4],
-            },
-        ];
-        let maybe_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "Maybe".into(),
-            u32_ty,
-            vec![0, 1],
-            payload_variants,
-            0,
-            8,
-            4,
-        )
-        .into();
-        let maybe_array: TypeHandle = MirArrayType::get(&mut ctx, maybe_ty, 4).into();
-        assert!(
-            validate_ptr_to_array_constant_type(&ctx, maybe_array, Location::Unknown).is_err(),
-            "a payload-carrying enum stays out of the reference form too"
-        );
-
-        // The `&[]` shape: a promoted empty-slice constant keeps its
-        // any-element admission now that the check routes through the shared
-        // predicate.
-        let struct_ty: TypeHandle = MirStructType::get(
-            &mut ctx,
-            "EmptySliceElement".into(),
-            vec!["value".into()],
-            vec![u32_ty],
-        )
-        .into();
-        let empty_struct_array: TypeHandle = MirArrayType::get(&mut ctx, struct_ty, 0).into();
-        assert!(
-            validate_ptr_to_array_constant_type(&ctx, empty_struct_array, Location::Unknown)
-                .is_ok(),
-            "a zero-length array has nothing readable, whatever its element type"
-        );
-    }
-}
-
-#[cfg(test)]
-mod promotable_array_element_tests {
-    use super::{
-        dialect_stored_size, promotable_array_element, promoted_global_validation_type,
-        validate_array_value_element_type,
-    };
-    use dialect_mir::types::{
-        EnumVariant, MirArrayType, MirEnumType, MirPtrType, MirStructType, MirTupleType,
-    };
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::context::Context;
-    use pliron::location::Location;
-    use pliron::r#type::TypeHandle;
-
-    /// A field-less enum with a recorded layout, as rustc gives a `#[repr(u32)]`
-    /// C-like enum.
-    fn fieldless_enum(ctx: &mut Context, u32_ty: TypeHandle) -> TypeHandle {
-        let variants = vec!["Add", "Sub"]
-            .into_iter()
-            .map(|name| EnumVariant {
-                name: name.into(),
-                field_types: vec![],
-                field_offsets: vec![],
-                field_sizes: vec![],
-            })
-            .collect();
-        MirEnumType::get_with_layout(ctx, "Op".into(), u32_ty, vec![0, 1], variants, 0, 4, 4).into()
-    }
-
-    /// The same shape, except one variant carries a payload.
-    fn payload_enum(ctx: &mut Context, u32_ty: TypeHandle) -> TypeHandle {
-        let variants = vec![
-            EnumVariant {
-                name: "None".into(),
-                field_types: vec![],
-                field_offsets: vec![],
-                field_sizes: vec![],
-            },
-            EnumVariant {
-                name: "Some".into(),
-                field_types: vec![u32_ty],
-                field_offsets: vec![4],
-                field_sizes: vec![4],
-            },
-        ];
-        MirEnumType::get_with_layout(ctx, "Maybe".into(), u32_ty, vec![0, 1], variants, 0, 8, 4)
-            .into()
-    }
-
-    #[test]
-    fn promotion_admits_recursive_promotable_aggregates() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-
-        let scalars: TypeHandle = MirArrayType::get(&mut ctx, u32_ty, 4).into();
-        assert!(
-            promotable_array_element(&ctx, scalars),
-            "a scalar array is the shape this already promoted"
-        );
-        let nested: TypeHandle = MirArrayType::get(&mut ctx, scalars, 2).into();
-        assert!(
-            promotable_array_element(&ctx, nested),
-            "nesting must not lose a promotable leaf"
-        );
-
-        let op_ty = fieldless_enum(&mut ctx, u32_ty);
-        let op_array: TypeHandle = MirArrayType::get(&mut ctx, op_ty, 8).into();
-        assert!(
-            promotable_array_element(&ctx, op_array),
-            "a field-less enum element is its discriminant, so one load reads it"
-        );
-        let nested_ops: TypeHandle = MirArrayType::get(&mut ctx, op_array, 2).into();
-        assert!(
-            promotable_array_element(&ctx, nested_ops),
-            "nested field-less enum arrays stay promotable"
-        );
-
-        // Payload-carrying enums still use a value path that round-trips their
-        // payload through memory, so they remain outside immutable-global promotion.
-        let maybe_ty = payload_enum(&mut ctx, u32_ty);
-        let maybe_array: TypeHandle = MirArrayType::get(&mut ctx, maybe_ty, 4).into();
-        assert!(
-            !promotable_array_element(&ctx, maybe_array),
-            "a payload-carrying enum round-trips its payload through memory"
-        );
-
-        let tuple_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![u32_ty, u32_ty]).into();
-        let tuple_array: TypeHandle = MirArrayType::get(&mut ctx, tuple_ty, 4).into();
-        assert!(
-            promotable_array_element(&ctx, tuple_array),
-            "a tuple of promotable fields is promotable now that a field read \
-             addresses in place instead of copying the array"
-        );
-        let nested_tuple_arrays: TypeHandle = MirArrayType::get(&mut ctx, tuple_array, 2).into();
-        assert!(
-            promotable_array_element(&ctx, nested_tuple_arrays),
-            "nesting must not lose a promotable tuple leaf"
-        );
-
-        let struct_ty: TypeHandle = MirStructType::get(
-            &mut ctx,
-            "Element".into(),
-            vec!["value".into()],
-            vec![u32_ty],
-        )
-        .into();
-        let struct_array: TypeHandle = MirArrayType::get(&mut ctx, struct_ty, 4).into();
-        assert!(
-            promotable_array_element(&ctx, struct_array),
-            "a struct of promotable fields is promotable"
-        );
-
-        // Recursive aggregates remain promotable when every leaf is promotable.
-        let tuple_with_struct: TypeHandle =
-            MirTupleType::get(&mut ctx, vec![u32_ty, struct_ty]).into();
-        let tuple_with_struct_array: TypeHandle =
-            MirArrayType::get(&mut ctx, tuple_with_struct, 4).into();
-        assert!(
-            promotable_array_element(&ctx, tuple_with_struct_array),
-            "a promotable struct field keeps its tuple promotable"
-        );
-        let nested_struct_arrays: TypeHandle =
-            MirArrayType::get(&mut ctx, tuple_with_struct_array, 2).into();
-        assert!(
-            promotable_array_element(&ctx, nested_struct_arrays),
-            "nesting preserves recursive promotability"
-        );
-
-        // A zero-byte over-aligned struct carries an ABI constraint that is not
-        // visible in the lowered storage shape. Preserve the established
-        // alignment-sensitive value path for aggregates containing such a leaf.
-        let over_aligned_zst_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "OverAlignedZst".into(),
-            vec![],
-            vec![],
-            vec![],
-            vec![],
-            0,
-            32,
-        )
-        .into();
-        let tuple_with_over_aligned_zst: TypeHandle =
-            MirTupleType::get(&mut ctx, vec![over_aligned_zst_ty, u32_ty]).into();
-        let over_aligned_zst_array: TypeHandle =
-            MirArrayType::get(&mut ctx, tuple_with_over_aligned_zst, 2).into();
-        assert!(
-            !promotable_array_element(&ctx, over_aligned_zst_array),
-            "a zero-byte over-aligned struct must keep its containing aggregate on the alignment-sensitive path"
-        );
-
-        // Thin pointers are scalar load leaves once their initializer
-        // provenance is preserved as relocation metadata. Pin their concrete
-        // storage size too, so admission cannot later fail the byte-size gate.
-        let pointer_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let pointer_array: TypeHandle = MirArrayType::get(&mut ctx, pointer_ty, 4).into();
-        assert!(
-            promotable_array_element(&ctx, pointer_array),
-            "a thin pointer is itself a promotable scalar load leaf"
-        );
-        assert_eq!(
-            dialect_stored_size(&ctx, pointer_array),
-            Some(32),
-            "four NVPTX64 pointers occupy 32 bytes"
-        );
-
-        // Use a full rustc-style layout so this assertion exercises
-        // struct_layout_matches_llvm_natural instead of its unknown-layout
-        // early return.
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let pointer_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PointerBearingElement".into(),
-            vec!["pointer".into(), "tag".into()],
-            vec![pointer_ty, u8_ty],
-            vec![],
-            vec![0, 8],
-            16,
-            8,
-        )
-        .into();
-        let pointer_struct_array: TypeHandle =
-            MirArrayType::get(&mut ctx, pointer_struct_ty, 4).into();
-        assert!(
-            promotable_array_element(&ctx, pointer_struct_array),
-            "a naturally laid out struct containing a thin pointer is promotable"
-        );
-
-        let struct_with_payload_enum: TypeHandle = MirStructType::get(
-            &mut ctx,
-            "PayloadEnumElement".into(),
-            vec!["value".into()],
-            vec![maybe_ty],
-        )
-        .into();
-        let payload_struct_array: TypeHandle =
-            MirArrayType::get(&mut ctx, struct_with_payload_enum, 4).into();
-        assert!(
-            !promotable_array_element(&ctx, payload_struct_array),
-            "a payload-enum leaf must keep its containing struct out of promotion"
-        );
-    }
-
-    #[test]
-    fn packed_struct_promotion_requires_byte_faithful_storage() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-
-        // `#[repr(C, packed)] struct Packed { tag: u8, value: u32 }`: rustc
-        // records `value` at offset 1 and a five-byte total. The natural LLVM
-        // struct diverges, but the packed LLVM representation is exactly
-        // `<{ i8, i32 }>` and therefore preserves both offsets and stride.
-        let packed_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Packed".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![],
-            vec![0, 1],
-            5,
-            1,
-        )
-        .into();
-        let packed_struct_array: TypeHandle =
-            MirArrayType::get(&mut ctx, packed_struct_ty, 4).into();
-        assert!(
-            promotable_array_element(&ctx, packed_struct_array),
-            "a byte-faithful packed struct must use immutable-global promotion"
-        );
-        assert_eq!(
-            dialect_stored_size(&ctx, packed_struct_array),
-            Some(20),
-            "four packed five-byte elements must retain rustc's stride"
-        );
-
-        let empty_packed_array: TypeHandle =
-            MirArrayType::get(&mut ctx, packed_struct_ty, 0).into();
-        assert!(
-            promotable_array_element(&ctx, empty_packed_array),
-            "a zero-length packed array remains vacuously promotable"
-        );
-        assert_eq!(
-            promoted_global_validation_type(&mut ctx, empty_packed_array, 0),
-            empty_packed_array,
-            "zero-byte promotion must retain the semantic [Packed; 0] type"
-        );
-        let packed_byte_len = dialect_stored_size(&ctx, packed_struct_array).unwrap() as usize;
-        let packed_validation =
-            promoted_global_validation_type(&mut ctx, packed_struct_array, packed_byte_len);
-        let packed_validation_ref = packed_validation.deref(&ctx);
-        let packed_validation_array = packed_validation_ref
-            .downcast_ref::<MirArrayType>()
-            .expect("packed validation storage must be an array");
-        assert_eq!(packed_validation_array.size, 20);
-        assert_eq!(packed_validation_array.element_ty, u8_ty);
-        drop(packed_validation_ref);
-        // `repr(C, packed(2))` keeps one explicit byte between the fields and
-        // a six-byte stride. Natural LLVM still cannot place the u32 at offset
-        // two, while a packed struct plus one byte padding slot can.
-        let packed2_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Packed2".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![],
-            vec![0, 2],
-            6,
-            2,
-        )
-        .into();
-        let packed2_array: TypeHandle = MirArrayType::get(&mut ctx, packed2_struct_ty, 3).into();
-        assert!(
-            promotable_array_element(&ctx, packed2_array),
-            "packed(2) must be admitted when explicit padding reproduces rustc exactly"
-        );
-        assert_eq!(
-            dialect_stored_size(&ctx, packed2_array),
-            Some(18),
-            "packed(2) array promotion must preserve the six-byte element stride"
-        );
-
-        // A naturally laid-out outer struct may contain a packed child. The
-        // child's selected storage is already byte-faithful, so recursive
-        // promotion must not re-impose the child's natural alignment.
-        let outer_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "OuterWithPacked".into(),
-            vec!["head".into(), "inner".into()],
-            vec![u32_ty, packed_struct_ty],
-            vec![],
-            vec![0, 4],
-            12,
-            4,
-        )
-        .into();
-        let outer_array: TypeHandle = MirArrayType::get(&mut ctx, outer_ty, 2).into();
-        assert!(
-            promotable_array_element(&ctx, outer_array),
-            "a recursively byte-faithful packed child must remain promotable"
-        );
-
-        // Synthetic overlapping field ranges model layouts that no sequential
-        // natural or packed LLVM struct can express. Keep this fail-closed even
-        // though the individual leaves are promotable.
-        let overlapping_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Overlapping".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![],
-            vec![0, 0],
-            4,
-            1,
-        )
-        .into();
-        let overlapping_array: TypeHandle = MirArrayType::get(&mut ctx, overlapping_ty, 2).into();
-        assert!(
-            !promotable_array_element(&ctx, overlapping_array),
-            "overlapping storage must remain outside immutable-global promotion"
-        );
-
-        // Bare-array admission stays broader than promotion, so a layout that
-        // fails the promotion gate still has its existing element-wise fallback.
-        assert!(
-            validate_array_value_element_type(&ctx, overlapping_ty, &Location::Unknown).is_ok(),
-            "the bare-array fallback must remain available for an unpromotable struct"
-        );
-
-        let natural_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Natural".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![],
-            vec![0, 4],
-            8,
-            4,
-        )
-        .into();
-        let natural_struct_array: TypeHandle =
-            MirArrayType::get(&mut ctx, natural_struct_ty, 4).into();
-        assert!(
-            promotable_array_element(&ctx, natural_struct_array),
-            "natural-layout struct promotion must remain unchanged"
-        );
-    }
-
-    /// Coupling oracle: every struct layout the promotion gate admits must be
-    /// one mir-lower actually lowers byte-faithfully (natural, or packed with
-    /// explicit padding). The promotion gate swaps the global's validation
-    /// type to a byte view, so this agreement is the only thing standing
-    /// between an admitted layout and typed reads through a divergent
-    /// natural-layout fallback. If this test fails after changing either
-    /// side's layout walk, the two predicates have drifted.
-    #[test]
-    fn promoted_struct_layouts_agree_with_the_mir_lower_storage_selection() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-
-        // (name, offsets, total_size, align) for each struct shape the
-        // promotion test admits; every one must be byte-faithful downstream.
-        let admitted = [
-            ("Packed", vec![0u64, 1], 5u64, 1u64),
-            ("Packed2", vec![0, 2], 6, 2),
-            ("Natural", vec![0, 4], 8, 4),
-        ];
-        for (name, offsets, total_size, align) in admitted {
-            let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-                &mut ctx,
-                name.into(),
-                vec!["tag".into(), "value".into()],
-                vec![u8_ty, u32_ty],
-                vec![],
-                offsets,
-                total_size,
-                align,
-            )
-            .into();
-            let array_ty: TypeHandle = MirArrayType::get(&mut ctx, struct_ty, 2).into();
-            assert!(
-                promotable_array_element(&ctx, array_ty),
-                "`{name}` must stay in the promotion corpus this test guards"
-            );
-            assert!(
-                mir_lower::convert::types::struct_value_lowering_is_byte_faithful(
-                    &mut ctx, struct_ty
-                )
-                .expect("slot map must build for an admitted layout"),
-                "`{name}` is admitted for promotion but mir-lower would fall \
-                 back to a divergent natural layout; the two layout walks have \
-                 drifted"
-            );
-        }
-
-        // The known-unfaithful shape must stay rejected on BOTH sides.
-        let overlapping_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Overlapping".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![],
-            vec![0, 0],
-            4,
-            1,
-        )
-        .into();
-        let overlapping_array: TypeHandle = MirArrayType::get(&mut ctx, overlapping_ty, 2).into();
-        assert!(
-            !promotable_array_element(&ctx, overlapping_array),
-            "overlapping storage must remain outside promotion"
-        );
-        assert!(
-            !mir_lower::convert::types::struct_value_lowering_is_byte_faithful(
-                &mut ctx,
-                overlapping_ty
-            )
-            .expect("slot map must still build for the overlapping layout"),
-            "mir-lower must agree that overlapping storage is not byte-faithful"
-        );
-    }
-
-    #[test]
-    fn an_enum_without_a_recorded_layout_is_not_promoted() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        // `total_size` 0 means the layout was never recorded, so the byte image
-        // has nothing to be checked against.
-        let variants = vec![EnumVariant {
-            name: "Only".into(),
-            field_types: vec![],
-            field_offsets: vec![],
-            field_sizes: vec![],
-        }];
-        let unsized_enum: TypeHandle =
-            MirEnumType::get(&mut ctx, "Unknown".into(), u32_ty, vec![0], variants).into();
-        let array: TypeHandle = MirArrayType::get(&mut ctx, unsized_enum, 4).into();
-        assert!(
-            !promotable_array_element(&ctx, array),
-            "an enum with no recorded size must not be promoted"
-        );
-    }
-}
-
-#[cfg(test)]
-// Tests build kinded fixture types directly; production code mints via facts::PointerOrigin.
-#[allow(clippy::disallowed_methods)]
-mod aggregate_relocation_tests {
-    use super::{
-        UnionConstantStorageKind, UnionConstantUse, classify_union_constant_storage,
-        constant_type_contains_pointer, decode_relocation_addend, find_unconsumed_relocation,
-        match_thin_pointer_relocation, provenance_starts_in_range,
-        relocation_free_pointer_integer_union_storage_field, relocation_offsets_overlapping_range,
-        translate_pointer_integer_union_constant_from_storage, validate_array_value_element_type,
-        validate_device_static_union_storage, validate_slice_relocation_shape,
-    };
-    use dialect_mir::ops::{MirCastOp, MirInsertFieldOp};
-    use dialect_mir::types::{
-        EnumVariant, MirArrayType, MirEnumType, MirPointerKind, MirPtrType, MirStructType,
-        MirTupleType, MirUnionType, pointer_carriers_in_type,
-    };
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::common_traits::Verify;
-    use pliron::context::Context;
-    use pliron::linked_list::ContainsLinkedList;
-    use pliron::location::Location;
-    use pliron::op::Op;
-    use pliron::operation::Operation;
-    use pliron::r#type::TypeHandle;
-    use pliron::r#type::Typed;
-    use rustc_public::target::Endian;
-
-    #[test]
-    fn relocation_overlap_detects_exact_and_left_crossing_pointer_words() {
-        let ptrs = [(0usize, ()), (8, ()), (24, ())];
-        assert_eq!(
-            relocation_offsets_overlapping_range(&ptrs, 8, 16, 8),
-            vec![8],
-            "an exact full-width relocation covers the carrier"
-        );
-        assert_eq!(
-            relocation_offsets_overlapping_range(&ptrs, 4, 12, 8),
-            vec![0, 8],
-            "overlap detection must include relocations starting before the carrier"
-        );
-        assert!(
-            relocation_offsets_overlapping_range(&ptrs, 16, 24, 8).is_empty(),
-            "touching a range boundary is not an overlap"
-        );
-    }
-
-    #[test]
-    fn aggregate_slice_relocation_accepts_nonzero_field_offset_with_siblings() {
-        let ptrs = [(0usize, ()), (8, ()), (24, ())];
-        assert_eq!(
-            validate_slice_relocation_shape(&ptrs, 8, 8),
-            Ok((16, 24)),
-            "sibling relocations outside the fat-pointer bytes must not interfere"
-        );
-    }
-
-    #[test]
-    fn aggregate_slice_relocation_rejects_metadata_provenance() {
-        let ptrs = [(8usize, ()), (16, ())];
-        let error = validate_slice_relocation_shape(&ptrs, 8, 8)
-            .expect_err("the metadata word must remain literal usize bytes");
-        assert!(
-            error.contains("additional relocation at byte 16"),
-            "diagnostic must identify metadata provenance: {error}"
-        );
-    }
-
-    #[test]
-    fn aggregate_slice_relocation_requires_data_word_provenance_at_field_start() {
-        let ptrs = [(12usize, ())];
-        let error = validate_slice_relocation_shape(&ptrs, 8, 8)
-            .expect_err("interior provenance cannot stand in for the slice data word");
-        assert!(
-            error.contains("0 provenance entries at its data-word start"),
-            "diagnostic must require an anchored data relocation: {error}"
-        );
-
-        let duplicate = [(8usize, 1u8), (8, 2u8)];
-        let error = validate_slice_relocation_shape(&duplicate, 8, 8)
-            .expect_err("two data-word provenance entries are ambiguous");
-        assert!(
-            error.contains("2 provenance entries at its data-word start"),
-            "diagnostic must count duplicate anchored relocations: {error}"
-        );
-    }
-
-    #[test]
-    fn aggregate_slice_relocation_rejects_left_crossing_pointer_storage() {
-        let ptrs = [(4usize, ()), (8, ())];
-        let error = validate_slice_relocation_shape(&ptrs, 8, 8)
-            .expect_err("a relocation from the preceding bytes must not overlap the slice");
-        assert!(
-            error.contains("additional relocation at byte 4"),
-            "diagnostic must identify the crossing relocation: {error}"
-        );
-    }
-
-    #[test]
-    fn relocation_matching_is_anchored_to_the_field_base() {
-        let ptrs = [(0usize, 1u32), (16, 2)];
-        assert_eq!(
-            match_thin_pointer_relocation(&ptrs, 16, 24),
-            Ok(Some(2)),
-            "the entry at the field base must be matched"
-        );
-        assert_eq!(
-            match_thin_pointer_relocation(&ptrs, 8, 16),
-            Ok(None),
-            "entries outside the field belong to sibling fields, not this one"
-        );
-    }
-
-    #[test]
-    fn relocation_matching_rejects_duplicate_entries_at_the_base() {
-        let ptrs = [(8usize, 1u32), (8, 2)];
-        let error = match_thin_pointer_relocation(&ptrs, 8, 16)
-            .expect_err("two provenance entries at one offset must fail closed");
-        assert!(
-            error.contains("2 provenance entries"),
-            "diagnostic must count the entries: {error}"
-        );
-    }
-
-    #[test]
-    fn relocation_matching_rejects_interior_provenance() {
-        let ptrs = [(12usize, 7u32)];
-        let error = match_thin_pointer_relocation(&ptrs, 8, 16)
-            .expect_err("provenance strictly inside a thin field is fat-pointer bits");
-        assert!(
-            error.contains("interior provenance at byte 12"),
-            "diagnostic must name the interior byte: {error}"
-        );
-    }
-
-    #[test]
-    fn relocation_addend_decodes_with_the_given_endianness() {
-        let mut bytes = vec![Some(0u8); 16];
-        bytes[8] = Some(0x28);
-        assert_eq!(
-            decode_relocation_addend(&bytes, 8, 8, Endian::Little),
-            Ok(0x28),
-            "little-endian addend must read the low byte first"
-        );
-        assert_eq!(
-            decode_relocation_addend(&bytes, 8, 8, Endian::Big),
-            Ok(0x28u128 << 56),
-            "big-endian addend must read the high byte first"
-        );
-    }
-
-    #[test]
-    fn relocation_addend_rejects_uninitialized_and_out_of_bounds_bytes() {
-        let mut bytes = vec![Some(0u8); 16];
-        bytes[10] = None;
-        let error = decode_relocation_addend(&bytes, 8, 8, Endian::Little)
-            .expect_err("addend bytes under a relocation are always initialized");
-        assert!(
-            error.contains("uninitialized"),
-            "diagnostic must name the failure: {error}"
-        );
-
-        let error = decode_relocation_addend(&bytes, 12, 8, Endian::Little)
-            .expect_err("an addend past the allocation end must fail closed");
-        assert!(
-            error.contains("needs 8 bytes"),
-            "diagnostic must name the missing width: {error}"
-        );
-    }
-
-    #[test]
-    fn non_pointer_fields_detect_overlapping_relocations() {
-        let ptrs = [(4usize, ())];
-        assert!(
-            provenance_starts_in_range(&ptrs, 4, 4),
-            "a relocation at the field base overlaps the field"
-        );
-        assert!(
-            provenance_starts_in_range(&ptrs, 0, 8),
-            "a relocation inside the field range overlaps the field"
-        );
-        assert!(
-            !provenance_starts_in_range(&ptrs, 8, 8),
-            "a relocation before the field does not start inside it"
-        );
-        assert!(
-            !provenance_starts_in_range(&ptrs, 4, 0),
-            "a zero-sized field cannot overlap any relocation"
-        );
-    }
-
-    #[test]
-    fn unconsumed_relocation_audit_flags_padding_only() {
-        let padding_relocation = [(12usize, ())];
-        assert_eq!(
-            find_unconsumed_relocation(&padding_relocation, 0, 16, &[(0, 8), (8, 4)]),
-            Some(12),
-            "a relocation in padding is consumed by no field and must be reported"
-        );
-        assert_eq!(
-            find_unconsumed_relocation(&padding_relocation, 0, 16, &[(0, 8), (8, 8)]),
-            None,
-            "a relocation covered by a field is that field's responsibility"
-        );
-        assert_eq!(
-            find_unconsumed_relocation(&padding_relocation, 16, 16, &[(16, 8)]),
-            None,
-            "relocations outside the aggregate's range belong to its siblings"
-        );
-        assert_eq!(
-            find_unconsumed_relocation(&padding_relocation, 0, 16, &[(0, 12), (12, 0)]),
-            Some(12),
-            "a zero-sized field consumes nothing"
-        );
-    }
-
-    #[test]
-    fn bare_array_elements_follow_the_documented_contract() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        assert!(
-            validate_array_value_element_type(&ctx, u32_ty, &Location::Unknown).is_ok(),
-            "primitive scalar elements remain supported"
-        );
-
-        let tuple_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![u32_ty]).into();
-        assert!(
-            validate_array_value_element_type(&ctx, tuple_ty, &Location::Unknown).is_ok(),
-            "tuple elements remain supported"
-        );
-        let nested_array_ty: TypeHandle = MirArrayType::get(&mut ctx, u32_ty, 4).into();
-        assert!(
-            validate_array_value_element_type(&ctx, nested_array_ty, &Location::Unknown).is_ok(),
-            "nested array elements remain supported"
-        );
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "Side".into(),
-            u8_ty,
-            vec![2, 5],
-            vec![
-                EnumVariant::unit("Low".into()),
-                EnumVariant::unit("High".into()),
-            ],
-            0,
-            1,
-            1,
-        )
-        .into();
-        assert!(
-            validate_array_value_element_type(&ctx, enum_ty, &Location::Unknown).is_ok(),
-            "bare enum-array elements are supported"
-        );
-        let nested_enum_array: TypeHandle = MirArrayType::get(&mut ctx, enum_ty, 2).into();
-        assert!(
-            validate_array_value_element_type(&ctx, nested_enum_array, &Location::Unknown).is_ok(),
-            "nesting preserves supported enum leaves"
-        );
-
-        let bytes_ty: TypeHandle = MirArrayType::get(&mut ctx, u8_ty, 4).into();
-        let union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "Bits".into(),
-            vec!["word".into(), "bytes".into()],
-            vec![u32_ty, bytes_ty],
-            4,
-            4,
-        )
-        .into();
-        assert!(
-            validate_array_value_element_type(&ctx, union_ty, &Location::Unknown).is_ok(),
-            "initialized union elements are supported"
-        );
-        let nested_union_array: TypeHandle = MirArrayType::get(&mut ctx, union_ty, 2).into();
-        assert!(
-            validate_array_value_element_type(&ctx, nested_union_array, &Location::Unknown).is_ok(),
-            "nesting preserves supported union leaves"
-        );
-        assert!(
-            !constant_type_contains_pointer(&ctx, union_ty),
-            "the byte-materialized Bits shape is pointer-free"
-        );
-
-        let pointer_field_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let u8_pointer_field_ty: TypeHandle =
-            MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
-        let pointer_only_union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "PointerOnly".into(),
-            vec!["word".into(), "bytes".into()],
-            vec![pointer_field_ty, u8_pointer_field_ty],
-            8,
-            8,
-        )
-        .into();
-        assert!(
-            constant_type_contains_pointer(&ctx, pointer_only_union_ty),
-            "pointer-only union constants must use typed reconstruction"
-        );
-        assert_eq!(
-            classify_union_constant_storage(
-                &ctx,
-                pointer_only_union_ty,
-                UnionConstantUse::SsaReconstruction
-            ),
-            Ok(UnionConstantStorageKind::ThinPointer {
-                field_index: 0,
-                field_ty: pointer_field_ty,
-            }),
-            "compatible thin-pointer alternatives can share one provenance-bearing carrier"
-        );
-
-        assert!(
-            validate_array_value_element_type(&ctx, pointer_only_union_ty, &Location::Unknown)
-                .is_ok(),
-            "bare arrays of pointer-only unions must reach the provenance-aware union decoder"
-        );
-
-        let u64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let raw_const_pointer_field_ty: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::RawConst)
-                .into();
-        let pointer_integer_union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "PointerBits".into(),
-            vec!["ptr".into(), "bits".into()],
-            vec![raw_const_pointer_field_ty, u64_ty],
-            8,
-            8,
-        )
-        .into();
-        let pointer_integer_error = classify_union_constant_storage(
-            &ctx,
-            pointer_integer_union_ty,
-            UnionConstantUse::SsaReconstruction,
-        )
-        .expect_err("the provenance-aware classifier must keep pointer/integer overlap closed");
-        assert!(
-            pointer_integer_error.contains("pointer/integer union constants"),
-            "diagnostic must explain the provenance-vs-bits conflict: {pointer_integer_error}"
-        );
-        assert_eq!(
-            relocation_free_pointer_integer_union_storage_field(&ctx, pointer_integer_union_ty, 8),
-            Some((1, u64_ty)),
-            "a pointer-word ptr/u64 union is byte-image eligible when the allocation has no relocation"
-        );
-        assert_eq!(
-            relocation_free_pointer_integer_union_storage_field(&ctx, pointer_integer_union_ty, 4),
-            None,
-            "the exception must not cross a target pointer-width mismatch"
-        );
-
-        let u32_pointer_integer_union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "PointerNarrowBits".into(),
-            vec!["ptr".into(), "bits".into()],
-            vec![raw_const_pointer_field_ty, u32_ty],
-            8,
-            8,
-        )
-        .into();
-        assert_eq!(
-            relocation_free_pointer_integer_union_storage_field(
-                &ctx,
-                u32_pointer_integer_union_ty,
-                8
-            ),
-            None,
-            "partial-width integer alternatives stay outside the initial pointer-word exception"
-        );
-
-        let slice_ty: TypeHandle = dialect_mir::types::MirSliceType::get(&mut ctx, u32_ty).into();
-        let fat_pointer_union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "FatPointer".into(),
-            vec!["slice".into(), "ptr".into()],
-            vec![slice_ty, pointer_field_ty],
-            16,
-            8,
-        )
-        .into();
-        let fat_pointer_error = classify_union_constant_storage(
-            &ctx,
-            fat_pointer_union_ty,
-            UnionConstantUse::SsaReconstruction,
-        )
-        .expect_err("fat-pointer union storage must remain fail-closed");
-        assert!(
-            fat_pointer_error.contains("not a thin pointer"),
-            "diagnostic must identify unsupported fat/nested storage: {fat_pointer_error}"
-        );
-
-        let struct_ty: TypeHandle = MirStructType::get(
-            &mut ctx,
-            "ArrayValueElement".into(),
-            vec!["value".into()],
-            vec![u32_ty],
-        )
-        .into();
-        assert!(
-            validate_array_value_element_type(&ctx, struct_ty, &Location::Unknown).is_ok(),
-            "bare struct arrays are materialized by the layout-aware aggregate decoder"
-        );
-
-        let struct_array_ty: TypeHandle = MirArrayType::get(&mut ctx, struct_ty, 2).into();
-        assert!(
-            validate_array_value_element_type(&ctx, struct_array_ty, &Location::Unknown).is_ok(),
-            "nesting preserves supported struct leaves"
-        );
-
-        let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        assert!(
-            validate_array_value_element_type(&ctx, ptr_ty, &Location::Unknown).is_err(),
-            "direct pointer elements were never part of the bare array contract"
-        );
-    }
-
-    #[test]
-    fn relocation_free_pointer_integer_union_gate_is_raw_only() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let u64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let raw_mut_ty: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, true, MirPointerKind::RawMut)
-                .into();
-        let raw_mut_union: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "RawMutBits".into(),
-            vec!["ptr".into(), "bits".into()],
-            vec![raw_mut_ty, u64_ty],
-            8,
-            8,
-        )
-        .into();
-        assert_eq!(
-            relocation_free_pointer_integer_union_storage_field(&ctx, raw_mut_union, 8),
-            Some((1, u64_ty)),
-            "RawMut carries no uniqueness claim and may use the integer storage view"
-        );
-
-        let erased_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let shared_ty: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::SharedRef)
-                .into();
-        let unique_ty: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, true, MirPointerKind::UniqueRef)
-                .into();
-        let global_raw_ty: TypeHandle = MirPtrType::get_with_kind(
-            &mut ctx,
-            u32_ty,
-            false,
-            dialect_mir::types::address_space::GLOBAL,
-            MirPointerKind::RawConst,
-        )
-        .into();
-        let fn_marker: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "FnPtrTarget".into(),
-            vec![],
-            vec![],
-            vec![],
-            vec![],
-            0,
-            0,
-        )
-        .into();
-        let fn_token_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, fn_marker, false).into();
-
-        for (name, pointer_ty) in [
-            ("Erased", erased_ty),
-            ("SharedRef", shared_ty),
-            ("UniqueRef", unique_ty),
-            ("non-generic raw", global_raw_ty),
-            ("function token", fn_token_ty),
-        ] {
-            let union_ty: TypeHandle = MirUnionType::get(
-                &mut ctx,
-                format!("{name}Bits"),
-                vec!["ptr".into(), "bits".into()],
-                vec![pointer_ty, u64_ty],
-                8,
-                8,
-            )
-            .into();
-            assert_eq!(
-                relocation_free_pointer_integer_union_storage_field(&ctx, union_ty, 8),
-                None,
-                "{name} must not acquire a pointer category from integer-initialized union storage"
-            );
-        }
-    }
-
-    #[test]
-    fn pointer_only_union_classifier_preserves_reference_semantics() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let shared_u32: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::SharedRef)
-                .into();
-        let shared_u8: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u8_ty, false, MirPointerKind::SharedRef)
-                .into();
-        let raw_u32: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::RawConst)
-                .into();
-        let raw_u8: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u8_ty, false, MirPointerKind::RawConst)
-                .into();
-        let raw_mut_u32: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, true, MirPointerKind::RawMut)
-                .into();
-        let unique_u32: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, true, MirPointerKind::UniqueRef)
-                .into();
-
-        let raw_views: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "RawViews".into(),
-            vec!["word".into(), "byte".into()],
-            vec![raw_u32, raw_u8],
-            8,
-            8,
-        )
-        .into();
-        assert!(
-            classify_union_constant_storage(&ctx, raw_views, UnionConstantUse::SsaReconstruction)
-                .is_ok(),
-            "same-kind raw pointers may safely use different pointee views"
-        );
-
-        for (name, fields, expected) in [
-            (
-                "MixedReferencePointees",
-                vec![shared_u32, shared_u8],
-                "reference pointee types",
-            ),
-            (
-                "MixedRawKinds",
-                vec![raw_u32, raw_mut_u32],
-                "pointer storage semantics",
-            ),
-            ("UniqueReference", vec![unique_u32, unique_u32], "UniqueRef"),
-        ] {
-            let union_ty: TypeHandle = MirUnionType::get(
-                &mut ctx,
-                name.into(),
-                vec!["first".into(), "second".into()],
-                fields,
-                8,
-                8,
-            )
-            .into();
-            let error = classify_union_constant_storage(
-                &ctx,
-                union_ty,
-                UnionConstantUse::SsaReconstruction,
-            )
-            .expect_err("ambiguous pointer semantics must fail closed");
-            assert!(
-                error.contains(expected),
-                "{name} diagnostic must identify {expected}: {error}"
-            );
-        }
-
-        // Physical device-static storage emits exact bytes plus one
-        // integer-width relocation slot and never mints a typed reference, so
-        // same-kind reference alternatives with different pointee views stay
-        // supported there (e.g. `union { word: &'static u32, byte: &'static u8 }`).
-        let mixed_reference_pointees: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "MixedReferencePointees".into(),
-            vec!["first".into(), "second".into()],
-            vec![shared_u32, shared_u8],
-            8,
-            8,
-        )
-        .into();
-        assert!(
-            classify_union_constant_storage(
-                &ctx,
-                mixed_reference_pointees,
-                UnionConstantUse::PhysicalStorage
-            )
-            .is_ok(),
-            "physical initializer storage must keep mixed-pointee reference unions supported"
-        );
-    }
-
-    #[test]
-    fn pointer_integer_union_materialization_never_transmutes_to_a_pointer_carrier() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let u64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let raw_ty: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::RawConst)
-                .into();
-        let union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "PointerOrBits".into(),
-            vec!["pointer".into(), "bits".into()],
-            vec![raw_ty, u64_ty],
-            8,
-            8,
-        )
-        .into();
-        let block = BasicBlock::new(&mut ctx, None, vec![]);
-
-        let (value, last_op) = translate_pointer_integer_union_constant_from_storage(
-            &mut ctx,
-            union_ty,
-            1,
-            u64_ty,
-            &[
-                Some(0x88),
-                Some(0x77),
-                Some(0x66),
-                Some(0x55),
-                Some(0x44),
-                Some(0x33),
-                Some(0x22),
-                Some(0x11),
-            ],
-            block,
-            None,
-            Location::Unknown,
-        )
-        .expect("the exact raw-pointer/integer storage shape must materialize");
-        assert_eq!(value.get_type(&ctx), union_ty);
-
-        let last_op = last_op.expect("non-empty storage must emit an insert operation");
-        let insert = Operation::get_op::<MirInsertFieldOp>(last_op, &ctx)
-            .expect("the final operation must insert the integer union field");
-        assert_eq!(
-            insert.get_attr_insert_index(&ctx).map(|index| index.0),
-            Some(1)
-        );
-        assert!(insert.verify(&ctx).is_ok());
-
-        for operation in block.deref(&ctx).iter(&ctx) {
-            if let Some(cast) = Operation::get_op::<MirCastOp>(operation, &ctx) {
-                assert!(cast.verify(&ctx).is_ok());
-                let result_ty = cast
-                    .get_operation()
-                    .deref(&ctx)
-                    .get_result(0)
-                    .get_type(&ctx);
-                assert!(
-                    pointer_carriers_in_type(&ctx, result_ty).is_empty(),
-                    "constant storage may transmute bytes to the integer field, never to a pointer-bearing union"
-                );
-            }
-        }
-    }
-
-    #[test]
-    fn device_static_union_storage_gate_admits_only_one_anchored_pointer_word() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let word_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let byte_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
-        let thin_pointer_union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "ThinPointerWord".into(),
-            vec!["word".into(), "bytes".into()],
-            vec![word_ptr_ty, byte_ptr_ty],
-            8,
-            8,
-        )
-        .into();
-
-        assert_eq!(
-            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 8, 8, 8, &[(0, 8)]),
-            Ok(()),
-            "one naturally aligned pointer word with one anchored relocation is the \
-             accepted shape"
-        );
-
-        // The example shape `union { word: &'static u32, byte: &'static u8 }`:
-        // same-kind references with different pointee views. The storage gate
-        // emits bytes plus one relocation slot and never mints a typed
-        // reference, so this stays supported even though SSA reconstruction
-        // of the same union fails closed.
-        let shared_word_ty: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::SharedRef)
-                .into();
-        let shared_byte_ty: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, u8_ty, false, MirPointerKind::SharedRef)
-                .into();
-        let mixed_reference_union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "MixedReferenceWord".into(),
-            vec!["word".into(), "byte".into()],
-            vec![shared_word_ty, shared_byte_ty],
-            8,
-            8,
-        )
-        .into();
-        assert_eq!(
-            validate_device_static_union_storage(
-                &ctx,
-                mixed_reference_union_ty,
-                8,
-                8,
-                8,
-                &[(0, 8)]
-            ),
-            Ok(()),
-            "mixed-pointee reference unions remain valid device-static storage"
-        );
-
-        let byte_image_error =
-            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 4, 8, 8, &[(0, 8)])
-                .expect_err("a 32-bit pointer target must remain fail-closed");
-        assert!(
-            byte_image_error.contains("8-byte NVPTX pointers"),
-            "diagnostic must name the pointer-width restriction: {byte_image_error}"
-        );
-
-        let bytes_ty: TypeHandle = MirArrayType::get(&mut ctx, u8_ty, 4).into();
-        let pointer_free_union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "Bits".into(),
-            vec!["word".into(), "bytes".into()],
-            vec![u32_ty, bytes_ty],
-            4,
-            4,
-        )
-        .into();
-        let storage_error =
-            validate_device_static_union_storage(&ctx, pointer_free_union_ty, 8, 4, 4, &[(0, 8)])
-                .expect_err("byte-image unions take the literal-bytes path, not this gate");
-        assert!(
-            storage_error.contains("without thin-pointer storage"),
-            "diagnostic must explain the thin-pointer requirement: {storage_error}"
-        );
-
-        let wide_union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "TwoWords".into(),
-            vec!["first".into(), "second".into()],
-            vec![word_ptr_ty, byte_ptr_ty],
-            16,
-            8,
-        )
-        .into();
-        let size_error =
-            validate_device_static_union_storage(&ctx, wide_union_ty, 8, 16, 8, &[(0, 8)])
-                .expect_err("a union wider than one pointer word must remain fail-closed");
-        assert!(
-            size_error.contains("size/alignment 16/8"),
-            "diagnostic must report the rejected layout: {size_error}"
-        );
-
-        let initializer_error =
-            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 8, 16, 8, &[(0, 8)])
-                .expect_err("an over-sized evaluated initializer must remain fail-closed");
-        assert!(
-            initializer_error.contains("initializer size/alignment 16/8"),
-            "diagnostic must report the evaluated-initializer mismatch: {initializer_error}"
-        );
-
-        let uninit_error =
-            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 8, 8, 8, &[])
-                .expect_err("zero relocations (e.g. a ZST-field initializer) must fail closed");
-        assert!(
-            uninit_error.contains("0 initializer relocations"),
-            "diagnostic must count the missing relocation: {uninit_error}"
-        );
-
-        let multi_error = validate_device_static_union_storage(
-            &ctx,
-            thin_pointer_union_ty,
-            8,
-            8,
-            8,
-            &[(0, 4), (4, 4)],
-        )
-        .expect_err("two relocations cannot describe one pointer word");
-        assert!(
-            multi_error.contains("2 initializer relocations"),
-            "diagnostic must count the extra relocations: {multi_error}"
-        );
-
-        let offset_error =
-            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 8, 8, 8, &[(4, 8)])
-                .expect_err("a relocation off the word base must remain fail-closed");
-        assert!(
-            offset_error.contains("occupies byte 4"),
-            "diagnostic must locate the misplaced relocation: {offset_error}"
-        );
-
-        let width_error =
-            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 8, 8, 8, &[(0, 4)])
-                .expect_err("a narrow relocation cannot carry full pointer provenance");
-        assert!(
-            width_error.contains("width 4"),
-            "diagnostic must report the short relocation: {width_error}"
-        );
-    }
-}
-
-#[cfg(test)]
-// Tests build kinded fixture types directly; production code mints via facts::PointerOrigin.
-#[allow(clippy::disallowed_methods)]
-mod tests {
-    use super::*;
-    use dialect_mir::types::{MirArrayType, MirPtrType, MirStructType, MirTupleType};
-
-    #[test]
-    fn over_aligned_zst_tuple_fields_force_the_value_fallback_gate() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-
-        // `#[repr(align(32))] struct Align32;`: zero bytes, ABI alignment 32.
-        let align32_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Align32".into(),
-            vec![],
-            vec![],
-            vec![],
-            vec![],
-            0,
-            32,
-        )
-        .into();
-
-        // `(Align32, u8)` as rustc lays it out: one payload byte padded out
-        // to a 32-byte, align-32 allocation.
-        let pair_ty: TypeHandle = MirTupleType::get_with_layout(
-            &mut ctx,
-            vec![align32_ty, u8_ty],
-            vec![],
-            vec![0, 0],
-            32,
-            32,
-        )
-        .into();
-        assert!(
-            tuple_has_over_aligned_zst_field(&ctx, pair_ty),
-            "a zero-byte repr(align(32)) field must force the value path"
-        );
-
-        // The byte-size gap in PR #715's gate: `[Align32; 2]` has element
-        // count 2 but still owns zero bytes and still demands align 32, at
-        // any array nesting depth.
-        let align32_x2_ty: TypeHandle = MirArrayType::get(&mut ctx, align32_ty, 2).into();
-        let align32_x2x3_ty: TypeHandle = MirArrayType::get(&mut ctx, align32_x2_ty, 3).into();
-        for wrapped_ty in [align32_x2_ty, align32_x2x3_ty] {
-            let tuple_ty: TypeHandle = MirTupleType::get_with_layout(
-                &mut ctx,
-                vec![wrapped_ty, u8_ty],
-                vec![],
-                vec![0, 0],
-                32,
-                32,
-            )
-            .into();
-            assert!(
-                tuple_has_over_aligned_zst_field(&ctx, tuple_ty),
-                "a zero-byte array of over-aligned ZSTs must not slip through on element count"
-            );
-        }
-
-        // Ordinary tuples keep the address path: rustc's reordered
-        // `(u8, u32)` layout (u8 at offset 4, u32 at offset 0).
-        let plain_ty: TypeHandle = MirTupleType::get_with_layout(
-            &mut ctx,
-            vec![u8_ty, u32_ty],
-            vec![1, 0],
-            vec![4, 0],
-            8,
-            4,
-        )
-        .into();
-        assert!(
-            !tuple_has_over_aligned_zst_field(&ctx, plain_ty),
-            "tuples without over-aligned ZST fields must stay on the address path"
-        );
-
-        // An align-1 ZST field, the unit tuple, does not trip the gate:
-        // zero bytes alone raise nothing.
-        let unit_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![]).into();
-        let with_unit_ty: TypeHandle = MirTupleType::get_with_layout(
-            &mut ctx,
-            vec![unit_ty, u32_ty],
-            vec![],
-            vec![0, 0],
-            4,
-            4,
-        )
-        .into();
-        assert!(
-            !tuple_has_over_aligned_zst_field(&ctx, with_unit_ty),
-            "plain ZST fields raise no alignment and must not force the fallback"
-        );
-    }
-
-    #[test]
-    fn struct_storage_size_reads_layout_presence_not_size() {
-        // Ordinary padded struct: size is the padded width, not the field sum.
-        assert_eq!(struct_storage_size(2, 2, 16), Some(16));
-
-        // A struct with fields that is genuinely zero-sized, such as a
-        // `PhantomData` newtype. rustc recorded an offset for the field, so the
-        // size of zero is the answer rather than a missing one.
-        assert_eq!(struct_storage_size(1, 1, 0), Some(0));
-
-        // Field-less struct. `is_zst_type` takes these before the struct arm is
-        // reached, but the predicate agrees with it.
-        assert_eq!(struct_storage_size(0, 0, 0), Some(0));
-
-        // `Ty::layout()` failed when the type was imported, which
-        // `translator/types.rs` records as no offsets and a zero size.
-        assert_eq!(struct_storage_size(2, 0, 0), None);
-
-        // Same failure on a type whose size was recorded before the query failed.
-        assert_eq!(struct_storage_size(1, 0, 8), None);
-    }
-
-    #[test]
-    fn projected_pointer_type_preserves_base_address_space() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let field_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-
-        let aggregate_ty: TypeHandle = MirStructType::get(
-            &mut ctx,
-            "ProjectedAddressSpaceTest".into(),
-            vec!["field".into()],
-            vec![field_ty],
-        )
-        .into();
-
-        for address_space in [1, 4] {
-            let base_ptr_ty: TypeHandle =
-                MirPtrType::get(&mut ctx, aggregate_ty, false, address_space).into();
-
-            let projected_ty = projected_pointer_type(&mut ctx, base_ptr_ty, field_ty, false)
-                .expect("base type must be a MIR pointer");
-
-            let (projected_pointee, projected_mutability, projected_address_space) = {
-                let projected_ty = projected_ty.deref(&ctx);
-                let projected_ptr = projected_ty
-                    .downcast_ref::<MirPtrType>()
-                    .expect("projected type must remain a MIR pointer");
-
-                (
-                    projected_ptr.pointee,
-                    projected_ptr.is_mutable,
-                    projected_ptr.address_space,
-                )
-            };
-
-            assert_eq!(
-                projected_pointee, field_ty,
-                "field projection must change the pointee type"
-            );
-            assert!(
-                !projected_mutability,
-                "field projection must preserve the requested mutability"
-            );
-            assert_eq!(
-                projected_address_space, address_space,
-                "field projection must preserve the base pointer address space"
-            );
-        }
-    }
-
-    /// The shared-borrow punt predicate must flag exactly the payload shapes
-    /// whose enum storage differs from their semantic type: bool leaves and
-    /// shared-memory pointer leaves, at any nesting depth. Canonical scalars
-    /// and generic pointers must stay on the address path so shared reads of
-    /// ordinary payloads keep compiling without a copy.
-    #[test]
-    fn payload_storage_coercion_predicate_flags_bool_and_shared_pointer_leaves() {
-        use dialect_mir::types::{MirArrayType, MirTupleType};
-
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let bool_ty: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let f32_ty: TypeHandle = FP32Type::get(&ctx).into();
-        let shared_ptr: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
-        let generic_ptr: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-
-        // Leaves.
-        assert!(enum_payload_needs_storage_coercion(&ctx, bool_ty));
-        assert!(enum_payload_needs_storage_coercion(&ctx, shared_ptr));
-        assert!(!enum_payload_needs_storage_coercion(&ctx, u32_ty));
-        assert!(!enum_payload_needs_storage_coercion(&ctx, f32_ty));
-        assert!(!enum_payload_needs_storage_coercion(&ctx, generic_ptr));
-
-        // Nesting: one flagged leaf taints the aggregate, and a clean
-        // aggregate stays clean.
-        let mixed_tuple: TypeHandle = MirTupleType::get(&mut ctx, vec![u32_ty, bool_ty]).into();
-        let clean_tuple: TypeHandle = MirTupleType::get(&mut ctx, vec![u32_ty, f32_ty]).into();
-        assert!(enum_payload_needs_storage_coercion(&ctx, mixed_tuple));
-        assert!(!enum_payload_needs_storage_coercion(&ctx, clean_tuple));
-
-        let bool_struct: TypeHandle = MirStructType::get(
-            &mut ctx,
-            "HasBool".into(),
-            vec!["a".into(), "b".into()],
-            vec![u32_ty, bool_ty],
-        )
-        .into();
-        assert!(enum_payload_needs_storage_coercion(&ctx, bool_struct));
-
-        let bool_array: TypeHandle = MirArrayType::get(&mut ctx, bool_ty, 4).into();
-        let f32_array: TypeHandle = MirArrayType::get(&mut ctx, f32_ty, 4).into();
-        assert!(enum_payload_needs_storage_coercion(&ctx, bool_array));
-        assert!(!enum_payload_needs_storage_coercion(&ctx, f32_array));
-
-        // Deep nesting: struct-of-tuple-of-shared-pointer.
-        let inner: TypeHandle = MirTupleType::get(&mut ctx, vec![f32_ty, shared_ptr]).into();
-        let deep: TypeHandle =
-            MirStructType::get(&mut ctx, "Deep".into(), vec!["inner".into()], vec![inner]).into();
-        assert!(enum_payload_needs_storage_coercion(&ctx, deep));
-    }
-
-    #[test]
-    fn expected_pointer_normalization_rejects_concrete_kind_change() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let pointee_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let source_ty: TypeHandle = MirPtrType::get_generic_with_kind(
-            &mut ctx,
-            pointee_ty,
-            false,
-            MirPointerKind::SharedRef,
-        )
-        .into();
-        let target_ty: TypeHandle = MirPtrType::get_generic_with_kind(
-            &mut ctx,
-            pointee_ty,
-            true,
-            MirPointerKind::UniqueRef,
-        )
-        .into();
-        let block = BasicBlock::new(&mut ctx, None, vec![source_ty]);
-        let source = block.deref(&ctx).get_argument(0);
-
-        let (normalized, last_op) = cast_to_expected_pointer_type_if_needed(
-            &mut ctx,
-            source,
-            target_ty,
-            block,
-            None,
-            Location::Unknown,
-        );
-
-        assert_eq!(normalized.get_type(&ctx), source_ty);
-        assert!(
-            last_op.is_none(),
-            "generic normalization must not strengthen SharedRef into UniqueRef"
-        );
-
-        let erased_read: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee_ty, false).into();
-        let erased_write: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee_ty, true).into();
-        let erased_block = BasicBlock::new(&mut ctx, None, vec![erased_read]);
-        let erased_value = erased_block.deref(&ctx).get_argument(0);
-        let (normalized, last_op) = cast_to_expected_pointer_type_if_needed(
-            &mut ctx,
-            erased_value,
-            erased_write,
-            erased_block,
-            None,
-            Location::Unknown,
-        );
-        assert_eq!(normalized.get_type(&ctx), erased_read);
-        assert!(
-            last_op.is_none(),
-            "generic normalization must not manufacture writable Erased evidence"
-        );
-    }
-
-    #[test]
-    fn rust_pointer_boundary_allows_raw_mut_reborrow_to_unique_ref() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let pointee_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let raw_mut_ty: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, pointee_ty, true, MirPointerKind::RawMut)
-                .into();
-        let unique_ref_ty: TypeHandle = MirPtrType::get_generic_with_kind(
-            &mut ctx,
-            pointee_ty,
-            true,
-            MirPointerKind::UniqueRef,
-        )
-        .into();
-        let block = BasicBlock::new(&mut ctx, None, vec![raw_mut_ty]);
-        let raw_mut = block.deref(&ctx).get_argument(0);
-
-        let (reborrow, last_op) = cast_to_declared_rust_pointer_type_if_needed(
-            &mut ctx,
-            raw_mut,
-            unique_ref_ty,
-            block,
-            None,
-            Location::Unknown,
-            MirPointerKindAuthorityAttr::Reborrow,
-        );
-
-        assert_eq!(reborrow.get_type(&ctx), unique_ref_ty);
-        assert!(
-            last_op.is_some(),
-            "Rvalue::Ref must trust rustc's declared reborrow result kind"
-        );
-    }
-
-    #[test]
-    fn projected_address_normalization_matches_expected_pointer_type() {
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let pointee_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-
-        let physical_ptr_ty: TypeHandle = MirPtrType::get(&mut ctx, pointee_ty, false, 1).into();
-
-        let expected_rust_ptr_ty: TypeHandle = MirPtrType::get_generic_with_kind(
-            &mut ctx,
-            pointee_ty,
-            false,
-            MirPointerKind::SharedRef,
-        )
-        .into();
-
-        let block = BasicBlock::new(&mut ctx, None, vec![physical_ptr_ty]);
-        let physical_pointer = block.deref(&ctx).get_argument(0);
-
-        // Rvalue::Ref and Rvalue::AddressOf both use this normalization after
-        // computing a projected address in its physical address space.
-        let (normalized_pointer, last_op) = cast_to_declared_rust_pointer_type_if_needed(
-            &mut ctx,
-            physical_pointer,
-            expected_rust_ptr_ty,
-            block,
-            None,
-            Location::Unknown,
-            MirPointerKindAuthorityAttr::Reborrow,
-        );
-
-        assert_eq!(
-            normalized_pointer.get_type(&ctx),
-            expected_rust_ptr_ty,
-            "projected addresses must be normalized to the exact Rust pointer type and kind"
-        );
-
-        let cast_op = last_op.expect(
-            "normalizing addrspace(1) to the Rust generic address space must insert a cast",
-        );
-
-        assert!(
-            Operation::get_op::<MirCastOp>(cast_op, &ctx).is_some(),
-            "normalization must insert mir.cast"
-        );
-    }
-}
-
-#[cfg(test)]
-mod checked_binary_op_tests {
-    use super::*;
-
-    #[test]
-    fn checked_binary_op_accepts_supported_operators() {
-        assert_eq!(
-            classify_checked_binary_op(&mir::BinOp::Add),
-            Ok(CheckedBinaryOpKind::Add)
-        );
-        assert_eq!(
-            classify_checked_binary_op(&mir::BinOp::Sub),
-            Ok(CheckedBinaryOpKind::Sub)
-        );
-        assert_eq!(
-            classify_checked_binary_op(&mir::BinOp::Mul),
-            Ok(CheckedBinaryOpKind::Mul)
-        );
-    }
-
-    #[test]
-    fn checked_binary_op_rejects_unsupported_operator() {
-        let error = classify_checked_binary_op(&mir::BinOp::Div)
-            .expect_err("Div must remain unsupported as CheckedBinaryOp");
-
-        assert_eq!(error, "CheckedBinaryOp Div not yet implemented");
-    }
-
-    #[test]
-    fn promoted_immutable_globals_are_marked_and_dedup_by_type_and_initializer() {
-        use dialect_mir::types::MirArrayType;
-        use pliron::builtin::ops::ModuleOp;
-        use pliron::linked_list::ContainsLinkedList;
-
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let module = ModuleOp::new(&mut ctx, "promoted_globals".try_into().unwrap());
-        let module_region = module.get_operation().deref(&ctx).get_region(0);
-        let block = {
-            let existing = module_region.deref(&ctx).iter(&ctx).next();
-            match existing {
-                Some(block) => block,
-                None => {
-                    let block = BasicBlock::new(&mut ctx, None, vec![]);
-                    block.insert_at_back(module_region, &ctx);
-                    block
-                }
-            }
-        };
-
-        let f32_ty: TypeHandle = FP32Type::get(&ctx).into();
-        let table_ty: TypeHandle = MirArrayType::get(&mut ctx, f32_ty, 2).into();
-        let bytes = vec![0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x00, 0x40]; // [1.0f32, 2.0f32]
-        let initializer = GlobalInitializerData {
-            bytes,
-            alignment: 4,
-            relocations: Vec::new(),
-        };
-
-        let first = emit_promoted_immutable_global(
-            &mut ctx,
-            table_ty,
-            &initializer,
-            block,
-            None,
-            Location::Unknown,
-        );
-
-        // The marker is the point: without it the exporter writes `global` and
-        // `opt` may not delete the per-thread copy this path exists to remove.
-        assert!(
-            first.is_immutable(&ctx),
-            "promoted global must be immutable"
-        );
-        let first_key = String::from(first.get_attr_global_key(&ctx).expect("dedup key").clone());
-
-        // The same table reached again, through another function or spelling,
-        // must produce the same key.
-        let again = emit_promoted_immutable_global(
-            &mut ctx,
-            table_ty,
-            &initializer,
-            block,
-            None,
-            Location::Unknown,
-        );
-        let again_key = String::from(again.get_attr_global_key(&ctx).expect("dedup key").clone());
-        assert_eq!(
-            first_key, again_key,
-            "same type, bytes, and relocations must share a key"
-        );
-
-        // A different byte image must not alias.
-        let other_initializer = GlobalInitializerData {
-            bytes: vec![0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x80, 0x3f],
-            alignment: 4,
-            relocations: Vec::new(),
-        };
-        let other = emit_promoted_immutable_global(
-            &mut ctx,
-            table_ty,
-            &other_initializer,
-            block,
-            None,
-            Location::Unknown,
-        );
-        let other_key = String::from(other.get_attr_global_key(&ctx).expect("dedup key").clone());
-        assert_ne!(first_key, other_key, "distinct bytes must not share a key");
-    }
-
-    #[test]
-    fn promoted_dedup_key_distinguishes_relocation_identity() {
-        use dialect_mir::types::MirArrayType;
-
-        let mut ctx = Context::new();
-        crate::translator::register_dialects(&mut ctx);
-
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let table_ty: TypeHandle = MirArrayType::get(&mut ctx, i64_ty, 1).into();
-        let bytes = [0u8; 8];
-
-        // Pointer placeholder bytes and addends may be identical. The target key
-        // is rustc's provenance identity and must therefore participate in the
-        // promoted-global dedup key.
-        let target_a = "v1 1 0 8 1 0 8 target_a ";
-        let target_b = "v1 1 0 8 1 0 8 target_b ";
-
-        let key_a = promoted_constant_dedup_key_from_parts(&ctx, table_ty, &bytes, 8, target_a);
-        let key_b = promoted_constant_dedup_key_from_parts(&ctx, table_ty, &bytes, 8, target_b);
-        assert_ne!(
-            key_a, key_b,
-            "identical bytes with different relocation targets must not alias"
-        );
-
-        let differently_aligned =
-            promoted_constant_dedup_key_from_parts(&ctx, table_ty, &bytes, 16, target_a);
-        assert_ne!(
-            key_a, differently_aligned,
-            "identical type, bytes, and relocations with different allocation alignment must not alias"
-        );
-    }
-}
diff --git a/crates/mir-importer/src/translator/rvalue/aggregate.rs b/crates/mir-importer/src/translator/rvalue/aggregate.rs
new file mode 100644
index 0000000000..9f9a9a7fdd
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/aggregate.rs
@@ -0,0 +1,924 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Aggregate construction and field-value helpers.
+
+use super::coerce::cast_to_expected_pointer_type_if_needed;
+use super::coerce::{
+    cast_enum_fields_to_expected_types, cast_struct_fields_to_expected_types,
+    coerce_slice_data_pointee,
+};
+use super::const_bytes::translate_constant_value_from_bytes;
+use super::operand::translate_operand;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::facts;
+use crate::translator::types;
+use crate::translator::values::ValueMap;
+use dialect_mir::attributes::MirCastKindAttr;
+use dialect_mir::ops::{MirCastOp, MirConstructArrayOp, MirConstructEnumOp, MirConstructStructOp};
+use dialect_mir::ops::{MirInsertFieldOp, MirUndefOp};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_error;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::printable::Printable;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+use pliron::{input_err, input_error_noloc};
+use rustc_public::CrateDef;
+use rustc_public::mir;
+use rustc_public::ty::AdtKind;
+use rustc_public_bridge::IndexedVal;
+
+/// Build a `DisjointSlice` value from the fields of its MIR aggregate.
+///
+/// The literal lists `ptr`, `len`, the index space's runtime layout, and the
+/// marker fields; the markers are zero-sized and carry nothing, so dropping
+/// them leaves the operands `mir.construct_disjoint_slice` takes, in the same
+/// order. An index space with no runtime layout (`Index1D`, `Index2D<S>`)
+/// stores `()` there, which drops with the markers and leaves the two-word
+/// slice.
+///
+/// Field selection is positional, which the op's verifier then checks against
+/// the result type: the data pointer must point to the element type, the
+/// length must be an integer, and each remaining operand must match the index
+/// space's layout types in order. A reordered or retyped field therefore
+/// fails at verification rather than silently writing a row width into the
+/// length slot.
+pub(super) fn construct_disjoint_slice_aggregate(
+    ctx: &mut Context,
+    adt_ty: TypeHandle,
+    field_values: &[Value],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
+    let (element_type, space_tys) = {
+        let ty_obj = adt_ty.deref(ctx);
+        let slice_ty = ty_obj
+            .downcast_ref::<dialect_mir::types::MirDisjointSliceType>()
+            .expect("caller checked the disjoint slice type");
+        (slice_ty.element_type(), slice_ty.space_types().to_vec())
+    };
+
+    let runtime_fields: Vec<Value> = field_values
+        .iter()
+        .copied()
+        .filter(|value| !types::is_zst_type(ctx, value.get_type(ctx)))
+        .collect();
+
+    let expected = 2 + space_tys.len();
+    if runtime_fields.len() != expected {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "DisjointSlice aggregate expected {} runtime fields for {}, found {}",
+                expected,
+                adt_ty.disp(ctx),
+                runtime_fields.len()
+            ))
+        );
+    }
+
+    // The data pointer reaches the slice through the generic address space,
+    // as the fat-pointer arm does for `*mut [T]`: a value coming from shared
+    // memory carries addrspace(3) and would not match the element pointer the
+    // verifier expects.
+    let expected_ptr_ty: TypeHandle =
+        facts::mint_generic_ptr_type(ctx, element_type, facts::abi_disjoint_slice_data_ptr())
+            .into();
+    let (data_val, current_prev_op) = cast_to_expected_pointer_type_if_needed(
+        ctx,
+        runtime_fields[0],
+        expected_ptr_ty,
+        block_ptr,
+        prev_op,
+        loc.clone(),
+    );
+
+    let mut operands = vec![data_val];
+    operands.extend_from_slice(&runtime_fields[1..]);
+
+    let op = Operation::new(
+        ctx,
+        dialect_mir::ops::MirConstructDisjointSliceOp::get_concrete_op_info(),
+        vec![adt_ty],
+        operands,
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc);
+
+    let result = op.deref(ctx).get_result(0);
+    Ok((Some(op), result, current_prev_op))
+}
+
+/// Translate ADT aggregate operands, synthesizing omitted runtime-ZST fields when
+/// MIR carries only the non-ZST runtime operands.
+pub(super) fn translate_adt_aggregate_field_values(
+    ctx: &mut Context,
+    body: &mir::Body,
+    adt_def: rustc_public::ty::AdtDef,
+    variant_idx: rustc_public::ty::VariantIdx,
+    substs: &rustc_public::ty::GenericArgs,
+    operands: &[mir::Operand],
+    value_map: &mut ValueMap,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Vec<Value>, Option<Ptr<Operation>>)> {
+    let variant_index = variant_idx.to_index();
+    let variant = &adt_def.variants()[variant_index];
+
+    let mut field_infos = Vec::with_capacity(variant.fields().len());
+    for field in variant.fields() {
+        let field_rust_ty = field.ty_with_args(substs);
+        let translated_ty = types::translate_type(ctx, &field_rust_ty)?;
+        let is_runtime_zst = field_rust_ty
+            .layout()
+            .map(|layout| layout.shape().is_1zst())
+            .unwrap_or(false);
+        field_infos.push((field_rust_ty, translated_ty, is_runtime_zst));
+    }
+
+    let total_field_count = field_infos.len();
+    let non_zst_count = field_infos
+        .iter()
+        .filter(|(_, _, is_runtime_zst)| !*is_runtime_zst)
+        .count();
+
+    let synthesize_runtime_zsts = if operands.len() == total_field_count {
+        false
+    } else if operands.len() == non_zst_count {
+        true
+    } else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "ADT aggregate '{}' variant '{}' has {} translated fields, {} non-ZST runtime fields, but MIR provided {} operands",
+                adt_def.trimmed_name(),
+                variant.name(),
+                total_field_count,
+                non_zst_count,
+                operands.len()
+            ))
+        );
+    };
+
+    let mut field_values = Vec::with_capacity(total_field_count);
+    let mut current_prev_op = prev_op;
+    let mut operand_iter = operands.iter();
+
+    for (field_rust_ty, translated_ty, is_runtime_zst) in field_infos {
+        if synthesize_runtime_zsts && is_runtime_zst {
+            let (value, new_prev_op) = translate_constant_value_from_bytes(
+                ctx,
+                &field_rust_ty,
+                translated_ty,
+                &[],
+                block_ptr,
+                current_prev_op,
+                loc.clone(),
+            )?;
+            field_values.push(value);
+            current_prev_op = new_prev_op;
+            continue;
+        }
+
+        let operand = operand_iter.next().ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "ADT aggregate '{}' variant '{}' ran out of MIR operands while translating fields",
+                adt_def.trimmed_name(),
+                variant.name()
+            )))
+        })?;
+        let (value, new_prev_op) = translate_operand(
+            ctx,
+            body,
+            operand,
+            value_map,
+            block_ptr,
+            current_prev_op,
+            loc.clone(),
+        )?;
+        field_values.push(value);
+        current_prev_op = new_prev_op;
+    }
+
+    if operand_iter.next().is_some() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "ADT aggregate '{}' variant '{}' left unused MIR operands after field translation",
+                adt_def.trimmed_name(),
+                variant.name()
+            ))
+        );
+    }
+
+    Ok((field_values, current_prev_op))
+}
+
+/// Construct a union by writing the one active field into shared storage.
+///
+/// MIR supplies exactly one operand plus the declaration index of its active
+/// field. Start with undefined union storage and use `mir.insert_field` to
+/// write that typed view at byte zero. The union-specific lowering preserves
+/// every other byte as undefined; it never invents one independent slot per
+/// field.
+#[allow(clippy::too_many_arguments)]
+pub(super) fn translate_union_aggregate(
+    ctx: &mut Context,
+    body: &mir::Body,
+    adt_def: rustc_public::ty::AdtDef,
+    union_ty: TypeHandle,
+    active_field_idx: Option<usize>,
+    operands: &[mir::Operand],
+    value_map: &mut ValueMap,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
+    let active_field_idx = active_field_idx.ok_or_else(|| {
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "Union aggregate '{}' did not identify an active field",
+            adt_def.trimmed_name()
+        )))
+    })?;
+
+    if operands.len() != 1 {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Union aggregate '{}' expected exactly one operand for active field {}, found {}",
+                adt_def.trimmed_name(),
+                active_field_idx,
+                operands.len()
+            ))
+        );
+    }
+
+    let (field_count, expected_field_ty) = {
+        let ty_ref = union_ty.deref(ctx);
+        let union = ty_ref
+            .downcast_ref::<dialect_mir::types::MirUnionType>()
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Union aggregate '{}' did not translate to MirUnionType",
+                    adt_def.trimmed_name()
+                )))
+            })?;
+        (union.field_count(), union.get_field_type(active_field_idx))
+    };
+    if active_field_idx >= field_count {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Union aggregate '{}' active field {} is out of bounds for {} fields",
+                adt_def.trimmed_name(),
+                active_field_idx,
+                field_count
+            ))
+        );
+    }
+    let expected_field_ty = expected_field_ty.expect("active union field was bounds-checked");
+
+    let (active_value, current_prev_op) = translate_operand(
+        ctx,
+        body,
+        &operands[0],
+        value_map,
+        block_ptr,
+        prev_op,
+        loc.clone(),
+    )?;
+    let (active_value, current_prev_op) = cast_to_expected_pointer_type_if_needed(
+        ctx,
+        active_value,
+        expected_field_ty,
+        block_ptr,
+        current_prev_op,
+        loc.clone(),
+    );
+
+    let undef_op = MirUndefOp::new(ctx, union_ty).get_operation();
+    undef_op.deref_mut(ctx).set_loc(loc.clone());
+    if let Some(prev) = current_prev_op {
+        undef_op.insert_after(ctx, prev);
+    } else {
+        undef_op.insert_at_front(block_ptr, ctx);
+    }
+    let undef_value = undef_op.deref(ctx).get_result(0);
+
+    let insert_op = Operation::new(
+        ctx,
+        MirInsertFieldOp::get_concrete_op_info(),
+        vec![union_ty],
+        vec![undef_value, active_value],
+        vec![],
+        0,
+    );
+    insert_op.deref_mut(ctx).set_loc(loc);
+    MirInsertFieldOp::new(insert_op).set_attr_insert_index(
+        ctx,
+        dialect_mir::attributes::FieldIndexAttr(active_field_idx as u32),
+    );
+    let result = insert_op.deref(ctx).get_result(0);
+
+    Ok((Some(insert_op), result, Some(undef_op)))
+}
+
+/// Translate a `Rvalue::Aggregate` into `dialect-mir` construction ops.
+///
+/// Aggregate constructs a compound type from individual values: tuples,
+/// structs/enums/unions, arrays, closures, and raw fat/thin pointers.
+#[allow(clippy::too_many_arguments)]
+pub(super) fn translate_aggregate_rvalue(
+    ctx: &mut Context,
+    body: &mir::Body,
+    rvalue: &mir::Rvalue,
+    aggregate_kind: &mir::AggregateKind,
+    operands: &[mir::Operand],
+    value_map: &mut ValueMap,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
+    // Aggregate constructs a compound type from individual values.
+    // This is used for:
+    // - Tuple construction: (a, b, c)
+    // - Struct construction: MyStruct { field1: a, field2: b }
+    // - Array construction: [a, b, c]
+
+    match aggregate_kind {
+        mir::AggregateKind::Adt(adt_def, variant_idx, substs, _, active_field_idx) => {
+            let adt_kind = adt_def.kind();
+
+            // Get the type using adt_def.ty_with_args()
+            let adt_ty_rust = adt_def.ty_with_args(substs);
+            let adt_ty = types::translate_type(ctx, &adt_ty_rust)?;
+            let translated_field_values = if matches!(adt_kind, AdtKind::Union) {
+                None
+            } else {
+                Some(translate_adt_aggregate_field_values(
+                    ctx,
+                    body,
+                    *adt_def,
+                    *variant_idx,
+                    substs,
+                    operands,
+                    value_map,
+                    block_ptr,
+                    prev_op,
+                    loc.clone(),
+                )?)
+            };
+
+            match adt_kind {
+                AdtKind::Struct => {
+                    let (field_values, current_prev_op) = translated_field_values
+                        .expect("non-union ADT fields should have been translated");
+                    // Check if the translated type is a struct type.
+                    // Scalar-lowered newtypes like ThreadIndex are translated to
+                    // their single runtime field type. They may still have ZST
+                    // marker fields in MIR, so select the one field whose
+                    // translated value matches the scalar result type.
+                    let is_struct_type = {
+                        let ty_obj = adt_ty.deref(ctx);
+                        ty_obj.is::<dialect_mir::types::MirStructType>()
+                            || ty_obj.is::<dialect_mir::types::MirTupleType>()
+                    };
+
+                    // A `DisjointSlice` literal, which
+                    // `DisjointSlice::from_raw_parts` builds. The type
+                    // translator gives the ADT its own slice type rather
+                    // than a struct, so without this arm the shape falls
+                    // into the scalar-lowered path below, where no field
+                    // carries the slice type and the search reports zero
+                    // runtime fields (issue #667).
+                    if adt_ty
+                        .deref(ctx)
+                        .is::<dialect_mir::types::MirDisjointSliceType>()
+                    {
+                        return construct_disjoint_slice_aggregate(
+                            ctx,
+                            adt_ty,
+                            &field_values,
+                            block_ptr,
+                            current_prev_op,
+                            loc,
+                        );
+                    }
+
+                    if !is_struct_type {
+                        // Scalar-lowered ADT: layout collapsed to a single runtime
+                        // value. The MIR Aggregate may still list ZST fields
+                        // (PhantomData, etc.) -- those translate to types other
+                        // than `adt_ty`, so filtering by "type matches the
+                        // collapsed scalar" reliably picks the one runtime field.
+                        //
+                        // This works for shapes like
+                        //     ThreadIndex { raw: usize, _kernel: PhantomData<...>, ... }
+                        // where exactly one field shares the scalar type. If a
+                        // future scalar-lowered ADT has two runtime fields with
+                        // the same type, the filter returns >1 match and we bail
+                        // -- the assumption is wrong and the translator needs an
+                        // explicit story for that shape.
+                        let runtime_fields: Vec<Value> = field_values
+                            .iter()
+                            .copied()
+                            .filter(|value| value.get_type(ctx) == adt_ty)
+                            .collect();
+
+                        if runtime_fields.len() == 1 {
+                            Ok((None, runtime_fields[0], current_prev_op))
+                        } else {
+                            input_err!(
+                                loc,
+                                TranslationErr::unsupported(format!(
+                                    "Scalar-lowered ADT expected exactly one runtime field, found {}",
+                                    runtime_fields.len()
+                                ))
+                            )
+                        }
+                    } else {
+                        // Cast field values to expected types (address space normalization)
+                        // This handles cases where field values have specific address spaces
+                        // (e.g., addrspace:3 for shared memory) but the struct type expects
+                        // generic address space (addrspace:0)
+                        let (casted_field_values, prev_after_casts) =
+                            cast_struct_fields_to_expected_types(
+                                ctx,
+                                field_values,
+                                adt_ty,
+                                block_ptr,
+                                current_prev_op,
+                                loc.clone(),
+                            );
+
+                        // Create the construct_struct operation
+                        let op = Operation::new(
+                            ctx,
+                            MirConstructStructOp::get_concrete_op_info(),
+                            vec![adt_ty],
+                            casted_field_values,
+                            vec![],
+                            0,
+                        );
+                        op.deref_mut(ctx).set_loc(loc);
+
+                        let result = op.deref(ctx).get_result(0);
+
+                        Ok((Some(op), result, prev_after_casts))
+                    }
+                }
+                AdtKind::Enum => {
+                    let (field_values, current_prev_op) = translated_field_values
+                        .expect("non-union ADT fields should have been translated");
+                    // Get the variant index for the enum
+                    // NOTE: variant_idx IS the index (0, 1, 2, ...), NOT the discriminant!
+                    // discriminant_for_variant returns the discriminant VALUE which may differ
+                    // (e.g., enum Foo { A = 0, B = 2, C = 6 } has indices 0,1,2 but discriminants 0,2,6)
+                    let variant_index_val: usize = variant_idx.to_index();
+
+                    // A value inhabiting this variant cannot exist,
+                    // so this construction sits on a dynamically dead
+                    // path rustc keeps in MIR (e.g. building
+                    // `ControlFlow::Break(NeverShortCircuitResidual)`
+                    // inside `array::try_from_fn`).
+                    // `mir.construct_enum` refuses uninhabited
+                    // variants by verification, so keep the dead path
+                    // representable with a typed undef instead.
+                    let variant_is_uninhabited = adt_ty
+                        .deref(ctx)
+                        .downcast_ref::<dialect_mir::types::MirEnumType>()
+                        .and_then(|enum_ty| enum_ty.variant_is_inhabited(variant_index_val))
+                        .is_some_and(|inhabited| !inhabited);
+                    if variant_is_uninhabited {
+                        let undef = MirUndefOp::new(ctx, adt_ty).get_operation();
+                        undef.deref_mut(ctx).set_loc(loc);
+                        let result = undef.deref(ctx).get_result(0);
+                        return Ok((Some(undef), result, current_prev_op));
+                    }
+
+                    // Cast field values to expected types (address space normalization)
+                    // This handles cases where field values have specific address spaces
+                    // (e.g., addrspace:3 for shared memory) but the enum type expects
+                    // generic address space (addrspace:0)
+                    let (casted_field_values, prev_after_casts) =
+                        cast_enum_fields_to_expected_types(
+                            ctx,
+                            field_values,
+                            adt_ty,
+                            variant_index_val,
+                            block_ptr,
+                            current_prev_op,
+                            loc.clone(),
+                        );
+
+                    // Create the construct_enum operation with variant_index attribute
+                    let op = Operation::new(
+                        ctx,
+                        MirConstructEnumOp::get_concrete_op_info(),
+                        vec![adt_ty],
+                        casted_field_values,
+                        vec![],
+                        0,
+                    );
+                    op.deref_mut(ctx).set_loc(loc.clone());
+
+                    let enum_op = MirConstructEnumOp::new(op);
+                    enum_op.set_attr_construct_enum_variant_index(
+                        ctx,
+                        dialect_mir::attributes::VariantIndexAttr(variant_index_val as u32),
+                    );
+
+                    let result = op.deref(ctx).get_result(0);
+
+                    Ok((Some(op), result, prev_after_casts))
+                }
+                AdtKind::Union => translate_union_aggregate(
+                    ctx,
+                    body,
+                    *adt_def,
+                    adt_ty,
+                    *active_field_idx,
+                    operands,
+                    value_map,
+                    block_ptr,
+                    prev_op,
+                    loc,
+                ),
+            }
+        }
+        mir::AggregateKind::Tuple => {
+            // Tuple construction: (a, b, c)
+            // Similar to struct construction but with positional fields
+
+            // Translate all element operands
+            let mut element_values = Vec::with_capacity(operands.len());
+            let mut current_prev_op = prev_op;
+
+            for operand in operands {
+                let (val, new_prev_op) = translate_operand(
+                    ctx,
+                    body,
+                    operand,
+                    value_map,
+                    block_ptr,
+                    current_prev_op,
+                    loc.clone(),
+                )?;
+                element_values.push(val);
+                current_prev_op = new_prev_op;
+            }
+
+            // Translate the tuple type from the rvalue's rustc type
+            // so it carries rustc's layout and uniques with the
+            // tuple type of the destination place.
+            let rust_tuple_ty = rvalue.ty(body.locals()).map_err(|e| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Failed to query tuple aggregate type: {:?}",
+                    e
+                )))
+            })?;
+            let tuple_ty = types::translate_type(ctx, &rust_tuple_ty)?;
+
+            // Create mir.construct_tuple operation
+            use dialect_mir::ops::MirConstructTupleOp;
+
+            let op = Operation::new(
+                ctx,
+                MirConstructTupleOp::get_concrete_op_info(),
+                vec![tuple_ty],
+                element_values,
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc);
+
+            let result = op.deref(ctx).get_result(0);
+
+            Ok((Some(op), result, current_prev_op))
+        }
+        mir::AggregateKind::Array(elem_ty) => {
+            // Array construction: [e0, e1, e2, ...] -> mir.construct_array
+            // Translate the element type
+            let element_type = types::translate_type(ctx, elem_ty)?;
+            let array_size = operands.len() as u64;
+
+            // Translate all element operands
+            let mut element_values = Vec::with_capacity(operands.len());
+            let mut current_prev_op = prev_op;
+
+            for operand in operands {
+                let (val, new_prev_op) = translate_operand(
+                    ctx,
+                    body,
+                    operand,
+                    value_map,
+                    block_ptr,
+                    current_prev_op,
+                    loc.clone(),
+                )?;
+                let (val, new_prev_op) = cast_to_expected_pointer_type_if_needed(
+                    ctx,
+                    val,
+                    element_type,
+                    block_ptr,
+                    new_prev_op,
+                    loc.clone(),
+                );
+                element_values.push(val);
+                current_prev_op = new_prev_op;
+            }
+
+            // Create the array type
+            let array_ty = dialect_mir::types::MirArrayType::get(ctx, element_type, array_size);
+
+            // Create mir.construct_array operation
+            let op = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                element_values,
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc);
+
+            let result = op.deref(ctx).get_result(0);
+
+            Ok((Some(op), result, current_prev_op))
+        }
+        mir::AggregateKind::Closure(closure_def, substs) => {
+            // Closure construction with captures
+            // The operands are the captured values that form the closure environment
+            //
+            // MIR: _N = Aggregate(Closure(...), [captured_val1, captured_val2, ...])
+            // We construct a struct with the captured values as fields
+
+            // Translate all captured operands
+            let mut capture_values = Vec::with_capacity(operands.len());
+            let mut current_prev_op = prev_op;
+
+            for operand in operands {
+                let (val, new_prev_op) = translate_operand(
+                    ctx,
+                    body,
+                    operand,
+                    value_map,
+                    block_ptr,
+                    current_prev_op,
+                    loc.clone(),
+                )?;
+                capture_values.push(val);
+                current_prev_op = new_prev_op;
+            }
+
+            // Get the closure type
+            let closure_ty_rust = rustc_public::ty::Ty::new_closure(*closure_def, substs.clone());
+            let closure_ty = types::translate_type(ctx, &closure_ty_rust)?;
+
+            if capture_values.is_empty() {
+                // ZST closure (no captures) - create empty struct
+                let op = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![closure_ty],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                op.deref_mut(ctx).set_loc(loc);
+                let result = op.deref(ctx).get_result(0);
+                Ok((Some(op), result, current_prev_op))
+            } else {
+                // Closure with captures - create struct with captured values
+                // Cast captured values to expected types (address space normalization)
+                let (casted_capture_values, prev_after_casts) =
+                    cast_struct_fields_to_expected_types(
+                        ctx,
+                        capture_values,
+                        closure_ty,
+                        block_ptr,
+                        current_prev_op,
+                        loc.clone(),
+                    );
+
+                let op = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![closure_ty],
+                    casted_capture_values,
+                    vec![],
+                    0,
+                );
+                op.deref_mut(ctx).set_loc(loc);
+                let result = op.deref(ctx).get_result(0);
+                Ok((Some(op), result, prev_after_casts))
+            }
+        }
+        mir::AggregateKind::RawPtr(pointee_ty, mutability) => {
+            // Raw pointer construction from parts: rustc lowers the
+            // `aggregate_raw_ptr` intrinsic to this aggregate kind.
+            // It is reached by re-slicing (`&bytes[2..]` goes through
+            // `slice::index::get_offset_len_noubcheck`) and by
+            // `ptr::slice_from_raw_parts` / `ptr::from_raw_parts`.
+            // The two operands are (data_pointer, metadata).
+            use rustc_public::ty::{RigidTy, TyKind};
+
+            if operands.len() != 2 {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "RawPtr aggregate expected 2 operands (data, metadata), found {}",
+                        operands.len()
+                    ))
+                );
+            }
+
+            let origin = facts::pointer_origin_of_raw_mutability(*mutability);
+            let is_mutable = origin.is_mutable();
+
+            match pointee_ty.kind() {
+                TyKind::RigidTy(RigidTy::Slice(elem_ty)) => {
+                    // `*const [T]` / `*mut [T]`: the metadata operand is
+                    // the element count. `*const [T]` translates to
+                    // `MirSliceType` (same runtime layout as `&[T]`), so
+                    // build the fat pointer with `mir.construct_slice`.
+                    let element_type = types::translate_type(ctx, &elem_ty)?;
+
+                    let (data_val, prev_after_data) = translate_operand(
+                        ctx,
+                        body,
+                        &operands[0],
+                        value_map,
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                    )?;
+                    let (len_val, prev_after_len) = translate_operand(
+                        ctx,
+                        body,
+                        &operands[1],
+                        value_map,
+                        block_ptr,
+                        prev_after_data,
+                        loc.clone(),
+                    )?;
+
+                    // The fat pointer's data slot is a generic-addrspace
+                    // pointer. Values coming from shared memory carry
+                    // addrspace(3); normalize them like the struct/array
+                    // arms do.
+                    let expected_ptr_ty: TypeHandle =
+                        facts::mint_generic_ptr_type(ctx, element_type, origin).into();
+                    let (data_val, current_prev_op) = cast_to_expected_pointer_type_if_needed(
+                        ctx,
+                        data_val,
+                        expected_ptr_ty,
+                        block_ptr,
+                        prev_after_len,
+                        loc.clone(),
+                    );
+
+                    // Coerce the data pointer to the slice element type: a
+                    // reinterpret cast feeding `from_raw_parts` can leave it
+                    // typed to the pre-cast pointee (e.g. `*mut u64` for a
+                    // `[(u64, u64)]` slice), which the fat pointer rejects.
+                    let (data_val, current_prev_op) = coerce_slice_data_pointee(
+                        ctx,
+                        data_val,
+                        element_type,
+                        is_mutable,
+                        block_ptr,
+                        current_prev_op,
+                        loc.clone(),
+                    );
+
+                    let slice_ty = facts::mint_slice_type(ctx, element_type, origin);
+
+                    use dialect_mir::ops::MirConstructSliceOp;
+                    let op = Operation::new(
+                        ctx,
+                        MirConstructSliceOp::get_concrete_op_info(),
+                        vec![slice_ty.into()],
+                        vec![data_val, len_val],
+                        vec![],
+                        0,
+                    );
+                    op.deref_mut(ctx).set_loc(loc);
+
+                    let result = op.deref(ctx).get_result(0);
+
+                    Ok((Some(op), result, current_prev_op))
+                }
+                TyKind::RigidTy(RigidTy::Str) => {
+                    // Blocked on `str` having a device-side type
+                    // translation (issue #76).
+                    input_err!(
+                        loc,
+                        TranslationErr::unsupported(
+                            "RawPtr aggregate with `str` pointee not yet supported \
+                                     (no `str` type translation on device)"
+                                .to_string()
+                        )
+                    )
+                }
+                TyKind::RigidTy(RigidTy::Dynamic(..)) => {
+                    // Trait objects need a vtable, which has no
+                    // device-side story.
+                    input_err!(
+                        loc,
+                        TranslationErr::unsupported(
+                            "RawPtr aggregate with `dyn Trait` pointee not supported \
+                                     (no vtable support on device)"
+                                .to_string()
+                        )
+                    )
+                }
+                _ => {
+                    // `Sized` pointee: the metadata operand is `()`, so
+                    // the aggregate is just the data pointer re-typed as
+                    // `*const P` / `*mut P`. Confirm the metadata really
+                    // is unit before dropping it; an unsized-tail struct
+                    // pointee would carry real metadata here.
+                    let metadata_ty = operands[1].ty(body.locals()).map_err(|e| {
+                        input_error!(
+                            loc.clone(),
+                            TranslationErr::unsupported(format!(
+                                "Cannot get RawPtr aggregate metadata type: {e}"
+                            ))
+                        )
+                    })?;
+                    let metadata_is_unit = matches!(
+                        metadata_ty.kind(),
+                        TyKind::RigidTy(RigidTy::Tuple(tys)) if tys.is_empty()
+                    );
+                    if !metadata_is_unit {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "RawPtr aggregate with non-unit metadata of type {:?} \
+                                         not yet supported",
+                                metadata_ty
+                            ))
+                        );
+                    }
+
+                    // Translate the target pointer type through the same
+                    // path as the destination local, so the two agree
+                    // (including SharedArray/Barrier special cases).
+                    let raw_ptr_ty_rust = rustc_public::ty::Ty::new_ptr(*pointee_ty, *mutability);
+                    let target_ty = types::translate_type(ctx, &raw_ptr_ty_rust)?;
+
+                    let (data_val, current_prev_op) = translate_operand(
+                        ctx,
+                        body,
+                        &operands[0],
+                        value_map,
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                    )?;
+
+                    if data_val.get_type(ctx) == target_ty {
+                        // Already the right pointer type: pass through.
+                        Ok((None, data_val, current_prev_op))
+                    } else {
+                        // Pointer re-typing, e.g. `*const ()` data
+                        // pointer becoming `*const P`.
+                        let cast_op = Operation::new(
+                            ctx,
+                            MirCastOp::get_concrete_op_info(),
+                            vec![target_ty],
+                            vec![data_val],
+                            vec![],
+                            0,
+                        );
+                        cast_op.deref_mut(ctx).set_loc(loc);
+                        MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+
+                        let result = cast_op.deref(ctx).get_result(0);
+
+                        Ok((Some(cast_op), result, current_prev_op))
+                    }
+                }
+            }
+        }
+        _ => {
+            input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Aggregate kind {:?} not yet supported",
+                    aggregate_kind
+                ))
+            )
+        }
+    }
+}
diff --git a/crates/mir-importer/src/translator/rvalue/coerce.rs b/crates/mir-importer/src/translator/rvalue/coerce.rs
new file mode 100644
index 0000000000..d9a3b4913d
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/coerce.rs
@@ -0,0 +1,485 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Pointer and type normalization helpers shared by expr/operand/place
+//! translation.
+
+use crate::translator::facts;
+use crate::translator::values::generic_pointer_kind_retype_allowed;
+use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
+use dialect_mir::ops::MirCastOp;
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+
+/// Normalize a pointer-like value without creating new Rust pointer semantics.
+///
+/// This helper is for representation adjustments such as address-space
+/// normalization and aggregate/local type reconciliation. Thin pointers must
+/// have the same pointee and fat slices the same element type. A concrete kind
+/// may be preserved or deliberately erased, but `Erased` cannot regain a
+/// concrete Rust kind and two distinct concrete kinds cannot be interconverted.
+pub(super) fn cast_to_expected_pointer_type_if_needed(
+    ctx: &mut Context,
+    value: Value,
+    expected_type: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> (Value, Option<Ptr<Operation>>) {
+    let value_type = value.get_type(ctx);
+    if value_type == expected_type {
+        return (value, prev_op);
+    }
+
+    let compatible = {
+        let value_ref = value_type.deref(ctx);
+        let expected_ref = expected_type.deref(ctx);
+
+        match (
+            value_ref.downcast_ref::<dialect_mir::types::MirPtrType>(),
+            expected_ref.downcast_ref::<dialect_mir::types::MirPtrType>(),
+        ) {
+            (Some(value_ptr), Some(expected_ptr)) => {
+                value_ptr.pointee == expected_ptr.pointee
+                    && value_ptr.is_mutable == expected_ptr.is_mutable
+                    && generic_pointer_kind_retype_allowed(value_ptr.kind, expected_ptr.kind)
+            }
+            _ => match (
+                value_ref.downcast_ref::<dialect_mir::types::MirSliceType>(),
+                expected_ref.downcast_ref::<dialect_mir::types::MirSliceType>(),
+            ) {
+                (Some(value_slice), Some(expected_slice)) => {
+                    value_slice.element_ty == expected_slice.element_ty
+                        && value_slice.is_mutable == expected_slice.is_mutable
+                        && generic_pointer_kind_retype_allowed(
+                            value_slice.kind,
+                            expected_slice.kind,
+                        )
+                }
+                _ => false,
+            },
+        }
+    };
+
+    if !compatible {
+        return (value, prev_op);
+    }
+
+    let cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![expected_type],
+        vec![value],
+        vec![],
+        0,
+    );
+    cast_op.deref_mut(ctx).set_loc(loc);
+    MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+
+    match prev_op {
+        Some(prev) => cast_op.insert_after(ctx, prev),
+        None => cast_op.insert_at_front(block_ptr, ctx),
+    }
+
+    (cast_op.deref(ctx).get_result(0), Some(cast_op))
+}
+
+/// Establish the exact pointer/reference type declared by rustc at a semantic boundary.
+///
+/// `Rvalue::Ref` and `Rvalue::AddressOf` are not representation-only
+/// normalizations: they create a new Rust pointer/reference value. The result
+/// type supplied by rustc is therefore authoritative, including legitimate
+/// transitions such as `RawMut -> UniqueRef` for `unsafe { &mut *raw }`. This
+/// helper still requires the same thin-pointee or fat-slice element shape so it
+/// cannot hide an unrelated representation mismatch.
+pub(super) fn cast_to_declared_rust_pointer_type_if_needed(
+    ctx: &mut Context,
+    value: Value,
+    expected_type: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+    authority: MirPointerKindAuthorityAttr,
+) -> (Value, Option<Ptr<Operation>>) {
+    let value_type = value.get_type(ctx);
+    if value_type == expected_type {
+        return (value, prev_op);
+    }
+
+    let compatible = {
+        let value_ref = value_type.deref(ctx);
+        let expected_ref = expected_type.deref(ctx);
+
+        match (
+            value_ref.downcast_ref::<dialect_mir::types::MirPtrType>(),
+            expected_ref.downcast_ref::<dialect_mir::types::MirPtrType>(),
+        ) {
+            (Some(value_ptr), Some(expected_ptr)) => value_ptr.pointee == expected_ptr.pointee,
+            _ => match (
+                value_ref.downcast_ref::<dialect_mir::types::MirSliceType>(),
+                expected_ref.downcast_ref::<dialect_mir::types::MirSliceType>(),
+            ) {
+                (Some(value_slice), Some(expected_slice)) => {
+                    value_slice.element_ty == expected_slice.element_ty
+                }
+                _ => false,
+            },
+        }
+    };
+
+    if !compatible {
+        return (value, prev_op);
+    }
+
+    let cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![expected_type],
+        vec![value],
+        vec![],
+        0,
+    );
+    cast_op.deref_mut(ctx).set_loc(loc);
+    let cast = MirCastOp::new(cast_op);
+    cast.set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+    cast.set_pointer_kind_authority(ctx, authority);
+
+    match prev_op {
+        Some(prev) => cast_op.insert_after(ctx, prev),
+        None => cast_op.insert_at_front(block_ptr, ctx),
+    }
+
+    (cast_op.deref(ctx).get_result(0), Some(cast_op))
+}
+
+/// Return the physical-storage form of a thin pointer type.
+///
+/// Allocation operations create addresses, not Rust borrows/raw-pointer
+/// values, so their results stay `Erased`. The translated Rust constant type
+/// is established by a separately marked boundary cast.
+pub(super) fn erase_thin_pointer_kind(
+    ctx: &mut Context,
+    pointer_ty: TypeHandle,
+) -> Option<TypeHandle> {
+    let (pointee, is_mutable, address_space) = {
+        let pointer_ty = pointer_ty.deref(ctx);
+        let pointer_ty = pointer_ty.downcast_ref::<dialect_mir::types::MirPtrType>()?;
+        (
+            pointer_ty.pointee,
+            pointer_ty.is_mutable,
+            pointer_ty.address_space,
+        )
+    };
+    Some(dialect_mir::types::MirPtrType::get(ctx, pointee, is_mutable, address_space).into())
+}
+
+/// Coerce a raw data pointer so it points to `element_type` in the generic
+/// address space.
+///
+/// `from_raw_parts`/`from_raw_parts_mut` build a `[T]` slice from a thin data
+/// pointer, but a reinterpret cast at the call site (e.g. `p as *mut (u64, u64)`
+/// feeding a `[(u64, u64)]` slice) can leave the data operand typed to the
+/// pre-cast pointee. The fat pointer's data slot must be a generic-address-space
+/// pointer to the slice element type, so when the pointee differs, emit a
+/// `PtrToPtr` cast to that type. The data carrier retains its existing pointer
+/// kind; otherwise constructing the fat pointer could launder an Erased carrier
+/// back into a concrete slice kind.
+pub(super) fn coerce_slice_data_pointee(
+    ctx: &mut Context,
+    value: Value,
+    element_type: TypeHandle,
+    _is_mutable: bool,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> (Value, Option<Ptr<Operation>>) {
+    let (pointee_matches, origin) = {
+        let value_type = value.get_type(ctx);
+        let ty_ref = value_type.deref(ctx);
+        match ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>() {
+            Some(pt) => (
+                pt.pointee == element_type,
+                facts::pointer_origin_of_ptr_carrier(pt),
+            ),
+            None => return (value, prev_op),
+        }
+    };
+    if pointee_matches {
+        return (value, prev_op);
+    }
+    let target_ptr_ty: TypeHandle = facts::mint_generic_ptr_type(ctx, element_type, origin).into();
+    let cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![target_ptr_ty],
+        vec![value],
+        vec![],
+        0,
+    );
+    cast_op.deref_mut(ctx).set_loc(loc);
+    MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+    match prev_op {
+        Some(p) => cast_op.insert_after(ctx, p),
+        None => cast_op.insert_at_front(block_ptr, ctx),
+    }
+    (cast_op.deref(ctx).get_result(0), Some(cast_op))
+}
+
+/// Cast struct field values to match expected field types (address space normalization).
+///
+/// When constructing a struct, field values may have specific address spaces (e.g., addrspace:3)
+/// but the struct type's field definitions use generic address space (addrspace:0).
+/// This function casts each field value to match its expected type.
+pub(super) fn cast_struct_fields_to_expected_types(
+    ctx: &mut Context,
+    field_values: Vec<Value>,
+    struct_type: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> (Vec<Value>, Option<Ptr<Operation>>) {
+    // Get field types from the struct type
+    let field_types: Vec<TypeHandle> = {
+        let ty_ref = struct_type.deref(ctx);
+        if let Some(st) = ty_ref.downcast_ref::<dialect_mir::types::MirStructType>() {
+            st.field_types.clone()
+        } else {
+            // Not a struct type, return as-is
+            return (field_values, prev_op);
+        }
+    };
+
+    let mut result_values = Vec::with_capacity(field_values.len());
+    let mut current_prev_op = prev_op;
+
+    for (i, value) in field_values.into_iter().enumerate() {
+        if let Some(expected_type) = field_types.get(i) {
+            let (casted_value, new_prev_op) = cast_to_expected_pointer_type_if_needed(
+                ctx,
+                value,
+                *expected_type,
+                block_ptr,
+                current_prev_op,
+                loc.clone(),
+            );
+            result_values.push(casted_value);
+            current_prev_op = new_prev_op;
+        } else {
+            result_values.push(value);
+        }
+    }
+
+    (result_values, current_prev_op)
+}
+
+/// Cast enum variant field values to match expected field types (address space normalization).
+///
+/// Similar to cast_struct_fields_to_expected_types, but for enum variants.
+/// Gets the field types for the specific variant and casts each field value.
+pub(super) fn cast_enum_fields_to_expected_types(
+    ctx: &mut Context,
+    field_values: Vec<Value>,
+    enum_type: TypeHandle,
+    variant_idx: usize,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> (Vec<Value>, Option<Ptr<Operation>>) {
+    // Get the field types for this variant from the enum type
+    let variant_field_types: Vec<TypeHandle> = {
+        let ty_ref = enum_type.deref(ctx);
+        if let Some(et) = ty_ref.downcast_ref::<dialect_mir::types::MirEnumType>() {
+            // Calculate the field offset for this variant
+            let field_offset: usize = et.variant_field_counts[..variant_idx]
+                .iter()
+                .map(|&x| x as usize)
+                .sum();
+            let field_count = et.variant_field_counts[variant_idx] as usize;
+
+            // Get the field types for this variant
+            et.all_field_types[field_offset..field_offset + field_count].to_vec()
+        } else {
+            // Not an enum type, return as-is
+            return (field_values, prev_op);
+        }
+    };
+
+    let mut result_values = Vec::with_capacity(field_values.len());
+    let mut current_prev_op = prev_op;
+
+    for (i, value) in field_values.into_iter().enumerate() {
+        if let Some(expected_type) = variant_field_types.get(i) {
+            let (casted_value, new_prev_op) = cast_to_expected_pointer_type_if_needed(
+                ctx,
+                value,
+                *expected_type,
+                block_ptr,
+                current_prev_op,
+                loc.clone(),
+            );
+            result_values.push(casted_value);
+            current_prev_op = new_prev_op;
+        } else {
+            result_values.push(value);
+        }
+    }
+
+    (result_values, current_prev_op)
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production code mints via facts::PointerOrigin.
+#[allow(clippy::disallowed_methods)]
+mod tests {
+    use super::*;
+    use dialect_mir::types::{MirPointerKind, MirPtrType};
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    #[test]
+    fn expected_pointer_normalization_rejects_concrete_kind_change() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let pointee_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let source_ty: TypeHandle = MirPtrType::get_generic_with_kind(
+            &mut ctx,
+            pointee_ty,
+            false,
+            MirPointerKind::SharedRef,
+        )
+        .into();
+        let target_ty: TypeHandle = MirPtrType::get_generic_with_kind(
+            &mut ctx,
+            pointee_ty,
+            true,
+            MirPointerKind::UniqueRef,
+        )
+        .into();
+        let block = BasicBlock::new(&mut ctx, None, vec![source_ty]);
+        let source = block.deref(&ctx).get_argument(0);
+
+        let (normalized, last_op) = cast_to_expected_pointer_type_if_needed(
+            &mut ctx,
+            source,
+            target_ty,
+            block,
+            None,
+            Location::Unknown,
+        );
+
+        assert_eq!(normalized.get_type(&ctx), source_ty);
+        assert!(
+            last_op.is_none(),
+            "generic normalization must not strengthen SharedRef into UniqueRef"
+        );
+
+        let erased_read: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee_ty, false).into();
+        let erased_write: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee_ty, true).into();
+        let erased_block = BasicBlock::new(&mut ctx, None, vec![erased_read]);
+        let erased_value = erased_block.deref(&ctx).get_argument(0);
+        let (normalized, last_op) = cast_to_expected_pointer_type_if_needed(
+            &mut ctx,
+            erased_value,
+            erased_write,
+            erased_block,
+            None,
+            Location::Unknown,
+        );
+        assert_eq!(normalized.get_type(&ctx), erased_read);
+        assert!(
+            last_op.is_none(),
+            "generic normalization must not manufacture writable Erased evidence"
+        );
+    }
+
+    #[test]
+    fn rust_pointer_boundary_allows_raw_mut_reborrow_to_unique_ref() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let pointee_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let raw_mut_ty: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, pointee_ty, true, MirPointerKind::RawMut)
+                .into();
+        let unique_ref_ty: TypeHandle = MirPtrType::get_generic_with_kind(
+            &mut ctx,
+            pointee_ty,
+            true,
+            MirPointerKind::UniqueRef,
+        )
+        .into();
+        let block = BasicBlock::new(&mut ctx, None, vec![raw_mut_ty]);
+        let raw_mut = block.deref(&ctx).get_argument(0);
+
+        let (reborrow, last_op) = cast_to_declared_rust_pointer_type_if_needed(
+            &mut ctx,
+            raw_mut,
+            unique_ref_ty,
+            block,
+            None,
+            Location::Unknown,
+            MirPointerKindAuthorityAttr::Reborrow,
+        );
+
+        assert_eq!(reborrow.get_type(&ctx), unique_ref_ty);
+        assert!(
+            last_op.is_some(),
+            "Rvalue::Ref must trust rustc's declared reborrow result kind"
+        );
+    }
+
+    #[test]
+    fn projected_address_normalization_matches_expected_pointer_type() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let pointee_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+
+        let physical_ptr_ty: TypeHandle = MirPtrType::get(&mut ctx, pointee_ty, false, 1).into();
+
+        let expected_rust_ptr_ty: TypeHandle = MirPtrType::get_generic_with_kind(
+            &mut ctx,
+            pointee_ty,
+            false,
+            MirPointerKind::SharedRef,
+        )
+        .into();
+
+        let block = BasicBlock::new(&mut ctx, None, vec![physical_ptr_ty]);
+        let physical_pointer = block.deref(&ctx).get_argument(0);
+
+        // Rvalue::Ref and Rvalue::AddressOf both use this normalization after
+        // computing a projected address in its physical address space.
+        let (normalized_pointer, last_op) = cast_to_declared_rust_pointer_type_if_needed(
+            &mut ctx,
+            physical_pointer,
+            expected_rust_ptr_ty,
+            block,
+            None,
+            Location::Unknown,
+            MirPointerKindAuthorityAttr::Reborrow,
+        );
+
+        assert_eq!(
+            normalized_pointer.get_type(&ctx),
+            expected_rust_ptr_ty,
+            "projected addresses must be normalized to the exact Rust pointer type and kind"
+        );
+
+        let cast_op = last_op.expect(
+            "normalizing addrspace(1) to the Rust generic address space must insert a cast",
+        );
+
+        assert!(
+            Operation::get_op::<MirCastOp>(cast_op, &ctx).is_some(),
+            "normalization must insert mir.cast"
+        );
+    }
+}
diff --git a/crates/mir-importer/src/translator/rvalue/const_alloc.rs b/crates/mir-importer/src/translator/rvalue/const_alloc.rs
new file mode 100644
index 0000000000..9c4b78c975
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/const_alloc.rs
@@ -0,0 +1,2282 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Relocation-aware `Allocation` decoding.
+
+use super::coerce::{cast_struct_fields_to_expected_types, coerce_slice_data_pointee};
+use super::const_bytes::{
+    constant_storage_size, rust_array_type_info, rust_type_layout_size,
+    translate_constant_value_from_bytes, translate_zero_sized_constant_value,
+};
+use super::const_enum::{read_uint_from_bytes, translate_enum_constant_from_alloc};
+use super::const_union::translate_union_constant_from_alloc;
+use super::static_global::{get_static_pointer_info, translate_static_global_pointer};
+use super::statics::static_target_from_allocation_at;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::facts;
+use crate::translator::types;
+use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
+use dialect_mir::ops::{MirCastOp, MirConstantOp, MirConstructArrayOp, MirConstructStructOp};
+use dialect_mir::types::MirFP16Type;
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{FP32Type, FP64Type, IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::TypeHandle;
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use pliron::{input_err, input_error, input_error_noloc};
+use rustc_public::CrateDef;
+use rustc_public::mir;
+use rustc_public::ty::ConstantKind;
+use std::num::NonZeroUsize;
+
+/// Detect zero-addend array→slice unsize: static `[T; N]` viewed as `[T]`.
+///
+/// Returns `(element_ty, N)` when the pointee is a slice of the same element
+/// type as the static array. Other pointee mismatches stay unsupported.
+/// `N` is an upper bound for validation only; the emitted slice length comes
+/// from the constant's own fat-pointer metadata word, which is what makes
+/// zero-addend prefix subslices (e.g. `split_at(2).0` over the static) carry
+/// their true length instead of the whole array's.
+///
+/// The `static_elem == slice_elem` restriction is deliberate: a zero-addend
+/// *flattening* view (e.g. `&NESTED[0]` over `[[f32; 2]; 3]` typed as
+/// `&[f32]`) is valid Rust but stays a diagnosed support gap; accepting it
+/// would need element-count arithmetic across the reinterpreted shape, not
+/// just the stored metadata word.
+pub(super) fn array_to_slice_unsize_info(
+    static_ty: &rustc_public::ty::Ty,
+    pointee_ty: &rustc_public::ty::Ty,
+    loc: Location,
+) -> TranslationResult<Option<(rustc_public::ty::Ty, u64)>> {
+    use rustc_public::ty::{RigidTy, TyKind};
+
+    match (static_ty.kind(), pointee_ty.kind()) {
+        (
+            TyKind::RigidTy(RigidTy::Array(static_elem, len_const)),
+            TyKind::RigidTy(RigidTy::Slice(slice_elem)),
+        ) if static_elem == slice_elem => {
+            let len = len_const.eval_target_usize().map_err(|error| {
+                input_error!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Failed to evaluate array length for static slice unsize: {error:?}"
+                    ))
+                )
+            })?;
+            Ok(Some((static_elem, len)))
+        }
+        _ => Ok(None),
+    }
+}
+
+/// Detect an interior array→slice unsize within a device static.
+///
+/// The walk is intentionally limited to arrays. At each nesting level, the
+/// byte addend selects one array element; when that array's element type
+/// matches the slice element type, the remaining element count is returned.
+/// This supports both an offset into a flat `[T; N]` and a slice over an array
+/// nested inside outer arrays, while keeping structs, tuples, enums, and other
+/// DST reinterpretations outside this lowering path.
+pub(super) fn interior_array_to_slice_unsize_info(
+    static_ty: &rustc_public::ty::Ty,
+    pointee_ty: &rustc_public::ty::Ty,
+    byte_offset: u64,
+    loc: Location,
+) -> TranslationResult<Option<(rustc_public::ty::Ty, u64)>> {
+    use rustc_public::ty::{RigidTy, Ty, TyKind};
+
+    let TyKind::RigidTy(RigidTy::Slice(slice_elem)) = pointee_ty.kind() else {
+        return Ok(None);
+    };
+
+    fn find_region(
+        array_ty: Ty,
+        slice_elem: Ty,
+        byte_offset: u64,
+        loc: &Location,
+    ) -> TranslationResult<Option<u64>> {
+        let TyKind::RigidTy(RigidTy::Array(array_elem, len_const)) = array_ty.kind() else {
+            return Ok(None);
+        };
+
+        let len = len_const.eval_target_usize().map_err(|error| {
+            input_error!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Failed to evaluate array length for interior static slice unsize: {error:?}"
+                ))
+            )
+        })?;
+        let elem_size = rust_type_layout_size(array_elem, loc.clone())? as u64;
+        let array_size = elem_size.checked_mul(len).ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Array byte size overflowed while resolving an interior static slice: \
+                 {len} elements x {elem_size} bytes"
+            )))
+        })?;
+
+        if byte_offset > array_size {
+            return Ok(None);
+        }
+
+        if array_elem == slice_elem {
+            // A non-zero byte addend cannot distinguish positions between
+            // zero-sized elements. Keep that case outside this path rather
+            // than manufacturing an arbitrary element index.
+            if elem_size == 0 || !byte_offset.is_multiple_of(elem_size) {
+                return Ok(None);
+            }
+
+            let start = byte_offset / elem_size;
+            if start > len {
+                return Ok(None);
+            }
+            return Ok(Some(len - start));
+        }
+
+        // Descend only through the concrete outer element containing the
+        // addend. An offset one-past this array has no child array region to
+        // inspect, even though it may be valid for an empty slice at this
+        // array's own element type (handled by the matching arm above).
+        if elem_size == 0 || byte_offset >= array_size {
+            return Ok(None);
+        }
+
+        let element_index = byte_offset / elem_size;
+        if element_index >= len {
+            return Ok(None);
+        }
+
+        find_region(array_elem, slice_elem, byte_offset % elem_size, loc)
+    }
+
+    Ok(find_region(*static_ty, slice_elem, byte_offset, &loc)?
+        .map(|remaining_len| (slice_elem, remaining_len)))
+}
+
+/// Validate the relocation shape of one slice fat pointer stored inside an
+/// allocation.
+///
+/// A slice occupies two pointer-width words. Exactly one relocation must back
+/// the data word at `fat_ptr_offset`; the metadata word is a literal `usize`
+/// and therefore must not overlap another relocation. Sibling relocations that
+/// end exactly at the field start or begin exactly at the field end are fine.
+///
+/// Returns `(metadata_offset, fat_pointer_end)` on success. Generic over the
+/// provenance payload so the boundary rules are unit testable without a rustc
+/// session.
+fn validate_slice_relocation_shape<P>(
+    ptrs: &[(usize, P)],
+    fat_ptr_offset: usize,
+    pointer_width: usize,
+) -> Result<(usize, usize), String> {
+    if pointer_width == 0 {
+        return Err("slice fat pointer has zero-width target pointers".to_string());
+    }
+
+    let metadata_offset = fat_ptr_offset
+        .checked_add(pointer_width)
+        .ok_or_else(|| "slice fat-pointer data-word end overflowed".to_string())?;
+    let fat_pointer_end = metadata_offset
+        .checked_add(pointer_width)
+        .ok_or_else(|| "slice fat-pointer metadata-word end overflowed".to_string())?;
+
+    let anchored = ptrs
+        .iter()
+        .filter(|(offset, _)| *offset == fat_ptr_offset)
+        .count();
+    if anchored != 1 {
+        return Err(format!(
+            "Slice fat pointer at byte {fat_ptr_offset} has {anchored} provenance entries at its \
+             data-word start; expected exactly one"
+        ));
+    }
+
+    let overlapping =
+        relocation_offsets_overlapping_range(ptrs, fat_ptr_offset, fat_pointer_end, pointer_width);
+    if let Some(other_offset) = overlapping
+        .into_iter()
+        .find(|offset| *offset != fat_ptr_offset)
+    {
+        return Err(format!(
+            "Slice fat pointer at byte {fat_ptr_offset} has an additional relocation at byte \
+             {other_offset}; the metadata word must remain literal usize bytes"
+        ));
+    }
+
+    Ok((metadata_offset, fat_pointer_end))
+}
+
+/// Read the slice length from a fat-pointer image stored at an arbitrary
+/// allocation offset.
+fn slice_len_from_alloc_at(
+    alloc: &rustc_public::ty::Allocation,
+    fat_ptr_offset: usize,
+    loc: Location,
+) -> TranslationResult<u64> {
+    let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+    let (metadata_offset, fat_pointer_end) =
+        validate_slice_relocation_shape(&alloc.provenance.ptrs, fat_ptr_offset, pointer_width)
+            .map_err(|message| input_error!(loc.clone(), TranslationErr::unsupported(message)))?;
+
+    if fat_pointer_end > alloc.bytes.len() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Slice fat pointer at byte {fat_ptr_offset} needs bytes through \
+                 {fat_pointer_end}, but the allocation is only {} bytes",
+                alloc.bytes.len()
+            ))
+        );
+    }
+
+    alloc
+        .read_partial_uint(metadata_offset..fat_pointer_end)
+        .map(|len| len as u64)
+        .map_err(|error| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Failed to read slice length metadata at byte {metadata_offset}: {error:?}"
+            )))
+        })
+}
+
+/// Read the slice length from a standalone fat-pointer constant's metadata
+/// word.
+///
+/// A `&[T]` / `*const [T]` constant is a two-word image: the data word (which
+/// carries the provenance to the static, read by `static_target_from_constant`)
+/// followed by the `usize` length. The length word is the source of truth for
+/// the emitted slice: a const like `split_at(2).0` over a `[f32; 4]` static is
+/// a zero-addend pointer whose stored length is 2, not the array's 4.
+pub(super) fn slice_len_from_constant(
+    constant: &mir::ConstOperand,
+    loc: Location,
+) -> TranslationResult<u64> {
+    let ConstantKind::Allocated(alloc) = constant.const_.kind() else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(
+                "static slice unsize constant is not an allocated constant".to_string()
+            )
+        );
+    };
+
+    let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+    let expected_size = pointer_width.checked_mul(2).ok_or_else(|| {
+        input_error_noloc!(TranslationErr::unsupported(
+            "static slice unsize constant pointer width overflowed".to_string()
+        ))
+    })?;
+    if alloc.bytes.len() != expected_size {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "static slice unsize constant has {} bytes; expected exactly two \
+                 pointer-width words ({expected_size} bytes)",
+                alloc.bytes.len()
+            ))
+        );
+    }
+
+    slice_len_from_alloc_at(alloc, 0, loc)
+}
+
+/// Materialize a region of a device static as a fat `&[T]` / `*const [T]`.
+///
+/// A zero addend preserves the established whole-array path. A non-zero
+/// addend reuses the byte-addressed static-pointer lowering to produce the
+/// interior `*T` data pointer before pairing it with the length stored in the
+/// constant's metadata word.
+pub(super) fn translate_static_array_as_slice(
+    ctx: &mut Context,
+    static_def: &rustc_public::mir::mono::StaticDef,
+    elem_ty: rustc_public::ty::Ty,
+    len: u64,
+    origin: facts::PointerOrigin,
+    byte_offset: u64,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    use dialect_mir::ops::MirConstructSliceOp;
+
+    let elem_mir_ty = types::translate_type(ctx, &elem_ty)?;
+    let is_mutable = origin.is_mutable();
+
+    let (data_ptr, prev_after_data) = if byte_offset == 0 {
+        let static_ty = static_def.ty();
+        let array_mir_ty = types::translate_type(ctx, &static_ty)?;
+
+        // Thin pointer to the full array object (exact Rust `&[T; N]` shape).
+        let thin_array_ptr_ty: TypeHandle =
+            facts::mint_generic_ptr_type(ctx, array_mir_ty, origin).into();
+
+        let (array_ptr, prev_after_array) = translate_static_global_pointer(
+            ctx,
+            static_def,
+            array_mir_ty,
+            thin_array_ptr_ty,
+            is_mutable,
+            0,
+            block_ptr,
+            prev_op,
+            loc.clone(),
+        )?;
+
+        // Fat-pointer data slot is a generic `*T` / `*mut T`.
+        coerce_slice_data_pointee(
+            ctx,
+            array_ptr,
+            elem_mir_ty,
+            is_mutable,
+            block_ptr,
+            prev_after_array,
+            loc.clone(),
+        )
+    } else {
+        let data_ptr_ty: TypeHandle = facts::mint_generic_ptr_type(ctx, elem_mir_ty, origin).into();
+
+        translate_static_global_pointer(
+            ctx,
+            static_def,
+            elem_mir_ty,
+            data_ptr_ty,
+            is_mutable,
+            byte_offset,
+            block_ptr,
+            prev_op,
+            loc.clone(),
+        )?
+    };
+
+    let usize_ty = types::get_usize_type(ctx);
+    let len_attr = pliron::builtin::attributes::IntegerAttr::new(
+        usize_ty,
+        APInt::from_u64(len, NonZeroUsize::new(64).unwrap()),
+    );
+    let len_op = Operation::new(
+        ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![usize_ty.to_handle()],
+        vec![],
+        vec![],
+        0,
+    );
+    len_op.deref_mut(ctx).set_loc(loc.clone());
+    MirConstantOp::new(len_op).set_attr_value(ctx, len_attr);
+    match prev_after_data {
+        Some(prev) => len_op.insert_after(ctx, prev),
+        None => len_op.insert_at_front(block_ptr, ctx),
+    };
+    let len_val = len_op.deref(ctx).get_result(0);
+
+    let slice_ty = facts::mint_slice_type(ctx, elem_mir_ty, origin);
+    let construct = Operation::new(
+        ctx,
+        MirConstructSliceOp::get_concrete_op_info(),
+        vec![slice_ty.into()],
+        vec![data_ptr, len_val],
+        vec![],
+        0,
+    );
+    construct.deref_mut(ctx).set_loc(loc);
+    construct.insert_after(ctx, len_op);
+
+    Ok((construct.deref(ctx).get_result(0), Some(construct)))
+}
+
+/// Return relocation starts whose pointer-width storage overlaps
+/// `range_start..range_end`.
+///
+/// Unlike a simple "starts in range" check, this catches a relocation that
+/// begins before the enum tag carrier but extends into it.
+pub(super) fn relocation_offsets_overlapping_range<P>(
+    ptrs: &[(usize, P)],
+    range_start: usize,
+    range_end: usize,
+    pointer_width: usize,
+) -> Vec<usize> {
+    ptrs.iter()
+        .map(|(pos, _)| *pos)
+        .filter(|pos| {
+            let relocation_end = pos.saturating_add(pointer_width);
+            *pos < range_end && relocation_end > range_start
+        })
+        .collect()
+}
+
+/// Match the provenance entries of a thin-pointer field spanning
+/// `pointer_offset..field_end`.
+///
+/// Returns the payload of the single relocation anchored at the field's base
+/// offset, or `None` when no entry starts inside the field (null or exposed
+/// provenance bytes). More than one entry anchored at the base, or an entry
+/// starting strictly inside the field (fat or multi-word pointer bits), is a
+/// hard error. Generic over the payload so the matching rules are unit
+/// testable without a rustc session (`Prov` wraps an unconstructible
+/// `AllocId`).
+fn match_thin_pointer_relocation<P: Copy>(
+    ptrs: &[(usize, P)],
+    pointer_offset: usize,
+    field_end: usize,
+) -> Result<Option<P>, String> {
+    let matches: Vec<P> = ptrs
+        .iter()
+        .filter(|(pos, _)| *pos == pointer_offset)
+        .map(|&(_, prov)| prov)
+        .collect();
+    if matches.len() > 1 {
+        return Err(format!(
+            "Thin pointer field at offset {pointer_offset} has {} provenance entries; \
+             expected at most one",
+            matches.len()
+        ));
+    }
+
+    // A thin pointer occupies one pointer-sized word; reject any additional
+    // provenance that lands inside this field's byte range.
+    if let Some(&(interior_pos, _)) = ptrs
+        .iter()
+        .find(|(pos, _)| *pos > pointer_offset && *pos < field_end)
+    {
+        return Err(format!(
+            "Pointer field at offset {pointer_offset} has interior provenance at byte \
+             {interior_pos}; fat or multi-word pointer provenance in aggregate constants \
+             is not supported"
+        ));
+    }
+
+    Ok(matches.first().copied())
+}
+
+/// Decode the byte addend stored under a thin-pointer relocation at
+/// `pointer_offset..pointer_offset + ptr_width`.
+///
+/// The bytes under a relocation encode the offset into the target allocation
+/// and are always initialized by rustc, so an uninitialized byte is a hard
+/// error rather than a zero. Endianness is a parameter so the decoding is
+/// unit testable without a rustc session.
+fn decode_relocation_addend(
+    bytes: &[Option<u8>],
+    pointer_offset: usize,
+    ptr_width: usize,
+    endianness: rustc_public::target::Endian,
+) -> Result<u128, String> {
+    if ptr_width > 16 {
+        return Err(format!(
+            "relocation addend width {ptr_width} exceeds the 16-byte decode limit"
+        ));
+    }
+    let field_end = pointer_offset
+        .checked_add(ptr_width)
+        .filter(|end| *end <= bytes.len())
+        .ok_or_else(|| {
+            format!(
+                "relocation addend at offset {pointer_offset} needs {ptr_width} bytes, \
+                 but the allocation holds {}",
+                bytes.len()
+            )
+        })?;
+    let raw = bytes[pointer_offset..field_end]
+        .iter()
+        .copied()
+        .collect::<Option<Vec<u8>>>()
+        .ok_or_else(|| {
+            format!("relocation addend at offset {pointer_offset} contains uninitialized bytes")
+        })?;
+    Ok(match endianness {
+        rustc_public::target::Endian::Little => {
+            raw.iter().enumerate().fold(0u128, |acc, (idx, byte)| {
+                acc | ((*byte as u128) << (idx * 8))
+            })
+        }
+        rustc_public::target::Endian::Big => raw
+            .iter()
+            .fold(0u128, |acc, byte| (acc << 8) | (*byte as u128)),
+    })
+}
+
+/// Materialize a thin pointer field from an aggregate constant's allocation.
+///
+/// Aggregate **const** values with thin pointers to device statics are
+/// materialized via [`MirGlobalAllocOp`] per field (addend taken from the
+/// relocation's stored bytes). This does **not** mean device-static
+/// *initializers* that themselves contain pointer relocations are supported —
+/// those remain rejected by [`allocation_initializer_data`].
+///
+/// When the field has no provenance entry, falls back to the existing
+/// inttoptr-of-bytes path (null / exposed provenance).
+pub(super) fn translate_thin_pointer_at_alloc_offset(
+    ctx: &mut Context,
+    alloc: &rustc_public::ty::Allocation,
+    pointer_offset: usize,
+    result_ptr_ty: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    use rustc_public::mir::alloc::GlobalAlloc;
+
+    let ptr_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+    let field_end = pointer_offset.checked_add(ptr_width).ok_or_else(|| {
+        input_error!(
+            loc.clone(),
+            TranslationErr::unsupported(format!(
+                "Thin pointer field offset {pointer_offset} + width {ptr_width} overflowed"
+            ))
+        )
+    })?;
+    if field_end > alloc.bytes.len() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Thin pointer field at offset {pointer_offset} needs {ptr_width} bytes, \
+                 but allocation is only {} bytes",
+                alloc.bytes.len()
+            ))
+        );
+    }
+
+    let relocation =
+        match_thin_pointer_relocation(&alloc.provenance.ptrs, pointer_offset, field_end)
+            .map_err(|message| input_error!(loc.clone(), TranslationErr::unsupported(message)))?;
+
+    if let Some(prov) = relocation {
+        let addend = decode_relocation_addend(
+            &alloc.bytes,
+            pointer_offset,
+            ptr_width,
+            rustc_public::target::MachineInfo::target_endianness(),
+        )
+        .map_err(|message| {
+            input_error!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Failed to read thin-pointer addend at offset {pointer_offset}: {message}"
+                ))
+            )
+        })?;
+
+        let (pointee_ty, is_mutable) = {
+            let ty_ref = result_ptr_ty.deref(ctx);
+            let ptr_ty = ty_ref
+                .downcast_ref::<dialect_mir::types::MirPtrType>()
+                .ok_or_else(|| {
+                    input_error_noloc!(TranslationErr::unsupported(
+                        "translate_thin_pointer_at_alloc_offset: expected MirPtrType"
+                    ))
+                })?;
+            (ptr_ty.pointee, ptr_ty.is_mutable)
+        };
+
+        match GlobalAlloc::from(prov.0) {
+            GlobalAlloc::Static(static_def) => {
+                let byte_offset = u64::try_from(addend).map_err(|_| {
+                    input_error_noloc!(TranslationErr::unsupported(format!(
+                        "Device-static pointer addend {addend} does not fit u64"
+                    )))
+                })?;
+                return translate_static_global_pointer(
+                    ctx,
+                    &static_def,
+                    pointee_ty,
+                    result_ptr_ty,
+                    is_mutable,
+                    byte_offset,
+                    block_ptr,
+                    prev_op,
+                    loc,
+                );
+            }
+            GlobalAlloc::Memory(_) => {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Aggregate constant thin pointer at offset {pointer_offset} points at \
+                        an anonymous promoted allocation; promoted aggregate pointer constants \
+                        are not yet supported"
+                    ))
+                );
+            }
+            other => {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Aggregate constant thin pointer at offset {pointer_offset} points at \
+                         unsupported allocation kind: {other:?}"
+                    ))
+                );
+            }
+        }
+    }
+
+    // No provenance: keep the existing inttoptr-of-bytes behavior (null / exposed).
+    let field_bytes: Vec<u8> = alloc.bytes[pointer_offset..field_end]
+        .iter()
+        .map(|opt| opt.unwrap_or(0))
+        .collect();
+    let ptr_val = read_uint_from_bytes(&field_bytes) as u64;
+    let i64_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);
+    let apint = APInt::from_u64(ptr_val, NonZeroUsize::new(64).unwrap());
+    let int_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, apint);
+
+    let int_op = Operation::new(
+        ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    int_op.deref_mut(ctx).set_loc(loc.clone());
+    let const_op = MirConstantOp::new(int_op);
+    const_op.set_attr_value(ctx, int_attr);
+    if let Some(prev) = prev_op {
+        const_op.get_operation().insert_after(ctx, prev);
+    } else {
+        const_op.get_operation().insert_at_front(block_ptr, ctx);
+    }
+
+    let const_value = const_op.get_operation().deref(ctx).get_result(0);
+    let cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![result_ptr_ty],
+        vec![const_value],
+        vec![],
+        0,
+    );
+    cast_op.deref_mut(ctx).set_loc(loc);
+    let cast = MirCastOp::new(cast_op);
+    cast.set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
+    if dialect_mir::types::type_contains_concrete_pointer_kind(ctx, result_ptr_ty) {
+        cast.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    }
+    cast_op.insert_after(ctx, const_op.get_operation());
+    Ok((cast_op.deref(ctx).get_result(0), Some(cast_op)))
+}
+
+/// Materialize a slice fat-pointer field from an aggregate constant allocation.
+///
+/// The data word keeps rustc provenance and may carry a non-zero byte addend
+/// into a device static. The metadata word is decoded independently as the
+/// stored slice length. This deliberately supports only same-element
+/// array-to-slice views over Rust statics, matching the standalone constant
+/// path; anonymous promoted allocations and other DST metadata remain
+/// fail-closed.
+#[allow(clippy::too_many_arguments)]
+fn translate_slice_at_alloc_offset(
+    ctx: &mut Context,
+    alloc: &rustc_public::ty::Allocation,
+    fat_ptr_offset: usize,
+    rust_ty: &rustc_public::ty::Ty,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let Some((pointee_ty, origin)) = get_static_pointer_info(rust_ty) else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Aggregate slice constant at byte {fat_ptr_offset} has unexpected Rust type \
+                 {rust_ty:?}; expected a reference or raw pointer to a slice"
+            ))
+        );
+    };
+
+    let len = slice_len_from_alloc_at(alloc, fat_ptr_offset, loc.clone())?;
+    let Some(static_target) = static_target_from_allocation_at(alloc, fat_ptr_offset)? else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Aggregate slice constant at byte {fat_ptr_offset} points at an anonymous or \
+                 unsupported allocation; slice provenance currently requires a Rust device static"
+            ))
+        );
+    };
+
+    let static_ty = static_target.static_def.ty();
+    let slice_region = if static_target.byte_offset == 0 {
+        array_to_slice_unsize_info(&static_ty, &pointee_ty, loc.clone())?
+    } else {
+        interior_array_to_slice_unsize_info(
+            &static_ty,
+            &pointee_ty,
+            static_target.byte_offset,
+            loc.clone(),
+        )?
+    };
+
+    let Some((elem_ty, available_len)) = slice_region else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Aggregate slice constant at byte {fat_ptr_offset} points into device static {} \
+                 at byte addend {}, but its pointee type {pointee_ty:?} is not a supported \
+                 same-element array-to-slice view of static type {static_ty:?}",
+                static_target.static_def.name(),
+                static_target.byte_offset
+            ))
+        );
+    };
+
+    if len > available_len {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Aggregate slice constant at byte {fat_ptr_offset} stores length {len}, which \
+                 exceeds the selected region's remaining length {available_len} in device \
+                 static {}",
+                static_target.static_def.name()
+            ))
+        );
+    }
+
+    translate_static_array_as_slice(
+        ctx,
+        &static_target.static_def,
+        elem_ty,
+        len,
+        origin,
+        static_target.byte_offset,
+        block_ptr,
+        prev_op,
+        loc,
+    )
+}
+
+/// Slice `size` bytes from `alloc` at `offset`, treating uninit as zero.
+pub(super) fn alloc_slice_bytes_zeroing_uninit(
+    alloc: &rustc_public::ty::Allocation,
+    offset: usize,
+    size: usize,
+    what: &str,
+    loc: &Location,
+) -> TranslationResult<Vec<u8>> {
+    let end = offset.checked_add(size).ok_or_else(|| {
+        input_error!(
+            loc.clone(),
+            TranslationErr::unsupported(format!(
+                "{what}: offset {offset} + size {size} overflowed"
+            ))
+        )
+    })?;
+    if end > alloc.bytes.len() {
+        return input_err!(
+            loc.clone(),
+            TranslationErr::unsupported(format!(
+                "{what}: need [{offset}..{end}), but allocation is only {} bytes",
+                alloc.bytes.len()
+            ))
+        );
+    }
+    Ok(alloc.bytes[offset..end]
+        .iter()
+        .map(|opt| opt.unwrap_or(0))
+        .collect())
+}
+
+/// Whether any provenance entry starts inside `offset..offset + size`.
+/// Generic over the payload so the predicate is unit testable without a
+/// rustc session.
+fn provenance_starts_in_range<P>(ptrs: &[(usize, P)], offset: usize, size: usize) -> bool {
+    let end = offset.saturating_add(size);
+    ptrs.iter().any(|(pos, _)| *pos >= offset && *pos < end)
+}
+
+fn alloc_has_provenance_in_range(
+    alloc: &rustc_public::ty::Allocation,
+    offset: usize,
+    size: usize,
+) -> bool {
+    provenance_starts_in_range(&alloc.provenance.ptrs, offset, size)
+}
+
+/// Return the start offset of the first provenance entry that lies inside
+/// the aggregate's byte range but inside none of its fields.
+///
+/// Field translation consumes (thin pointer) or rejects (every other kind)
+/// the relocations under the bytes it decodes, so a survivor here sits in
+/// padding: no field would ever consume it, and dropping it would silently
+/// strip a pointer from the constant. Generic over the payload so the audit
+/// is unit testable without a rustc session.
+fn find_unconsumed_relocation<P>(
+    ptrs: &[(usize, P)],
+    aggregate_start: usize,
+    aggregate_size: usize,
+    field_ranges: &[(usize, usize)],
+) -> Option<usize> {
+    let aggregate_end = aggregate_start.saturating_add(aggregate_size);
+    ptrs.iter().map(|(pos, _)| *pos).find(|&pos| {
+        pos >= aggregate_start
+            && pos < aggregate_end
+            && !field_ranges
+                .iter()
+                .any(|&(start, size)| pos >= start && pos < start.saturating_add(size))
+    })
+}
+
+/// Fail-closed audit run after all of an aggregate's fields have been
+/// translated: any relocation inside the aggregate's byte range that no
+/// field consumed is a hard error.
+pub(super) fn audit_aggregate_relocations(
+    alloc: &rustc_public::ty::Allocation,
+    aggregate_start: usize,
+    aggregate_size: usize,
+    field_ranges: &[(usize, usize)],
+    what: &str,
+    loc: &Location,
+) -> TranslationResult<()> {
+    if let Some(pos) = find_unconsumed_relocation(
+        &alloc.provenance.ptrs,
+        aggregate_start,
+        aggregate_size,
+        field_ranges,
+    ) {
+        return input_err!(
+            loc.clone(),
+            TranslationErr::unsupported(format!(
+                "{what} constant has a pointer relocation at byte {pos} that no field \
+                 consumes; provenance in padding bytes cannot be preserved"
+            ))
+        );
+    }
+    Ok(())
+}
+
+/// Byte width of a constant field: rustc layout when available, the dialect
+/// type's storage size as a fallback. Shared by the scalar decode path and
+/// the per-aggregate relocation audit so both see the same field extents.
+fn constant_field_byte_size(
+    ctx: &Context,
+    rust_ty: &rustc_public::ty::Ty,
+    ty_ptr: TypeHandle,
+    loc: &Location,
+) -> TranslationResult<usize> {
+    rust_type_layout_size(*rust_ty, loc.clone()).or_else(|_| {
+        constant_storage_size(ctx, ty_ptr).ok_or_else(|| {
+            input_error!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Cannot determine storage size for constant field of type {rust_ty:?}"
+                ))
+            )
+        })
+    })
+}
+
+/// Decode one typed value from an allocation at an absolute byte offset,
+/// preserving supported pointer provenance. Thin pointer fields resolve through
+/// [`translate_thin_pointer_at_alloc_offset`]; slice fields pair the relocated
+/// data word with their literal length metadata.
+pub(super) fn translate_constant_value_from_alloc(
+    ctx: &mut Context,
+    alloc: &rustc_public::ty::Allocation,
+    absolute_byte_offset: usize,
+    rust_ty: &rustc_public::ty::Ty,
+    ty_ptr: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    use rustc_public::ty::{RigidTy, TyKind};
+
+    let is_ptr = ty_ptr.deref(ctx).is::<dialect_mir::types::MirPtrType>();
+    if is_ptr {
+        return translate_thin_pointer_at_alloc_offset(
+            ctx,
+            alloc,
+            absolute_byte_offset,
+            ty_ptr,
+            block_ptr,
+            prev_op,
+            loc,
+        );
+    }
+
+    let is_slice = ty_ptr.deref(ctx).is::<dialect_mir::types::MirSliceType>();
+    if is_slice {
+        let size = rust_type_layout_size(*rust_ty, loc.clone())?;
+        let field_end = absolute_byte_offset.checked_add(size).ok_or_else(|| {
+            input_error!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Slice field at byte {absolute_byte_offset} with size {size} overflowed"
+                ))
+            )
+        })?;
+        let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+        let overlaps = relocation_offsets_overlapping_range(
+            &alloc.provenance.ptrs,
+            absolute_byte_offset,
+            field_end,
+            pointer_width,
+        );
+        if !overlaps.is_empty() {
+            return translate_slice_at_alloc_offset(
+                ctx,
+                alloc,
+                absolute_byte_offset,
+                rust_ty,
+                block_ptr,
+                prev_op,
+                loc,
+            );
+        }
+        let bytes = alloc_slice_bytes_zeroing_uninit(
+            alloc,
+            absolute_byte_offset,
+            size,
+            "Slice field",
+            &loc,
+        )?;
+        return translate_constant_value_from_bytes(
+            ctx, rust_ty, ty_ptr, &bytes, block_ptr, prev_op, loc,
+        );
+    }
+
+    let is_tuple = ty_ptr.deref(ctx).is::<dialect_mir::types::MirTupleType>();
+    if is_tuple {
+        return translate_tuple_constant_from_alloc(
+            ctx,
+            alloc,
+            absolute_byte_offset,
+            rust_ty,
+            ty_ptr,
+            block_ptr,
+            prev_op,
+            loc,
+        );
+    }
+
+    let is_struct = ty_ptr.deref(ctx).is::<dialect_mir::types::MirStructType>();
+    if is_struct {
+        return translate_struct_constant_from_alloc(
+            ctx,
+            alloc,
+            absolute_byte_offset,
+            rust_ty,
+            ty_ptr,
+            block_ptr,
+            prev_op,
+            loc,
+        );
+    }
+
+    let is_union = ty_ptr.deref(ctx).is::<dialect_mir::types::MirUnionType>();
+    if is_union {
+        return translate_union_constant_from_alloc(
+            ctx,
+            alloc,
+            absolute_byte_offset,
+            rust_ty,
+            ty_ptr,
+            block_ptr,
+            prev_op,
+            loc,
+        );
+    }
+
+    let is_array = ty_ptr.deref(ctx).is::<dialect_mir::types::MirArrayType>();
+    if is_array {
+        return translate_array_constant_from_alloc(
+            ctx,
+            alloc,
+            absolute_byte_offset,
+            rust_ty,
+            ty_ptr,
+            block_ptr,
+            prev_op,
+            loc,
+        );
+    }
+
+    let is_enum = ty_ptr.deref(ctx).is::<dialect_mir::types::MirEnumType>();
+    if is_enum {
+        let size = rust_type_layout_size(*rust_ty, loc.clone())?;
+        if alloc_has_provenance_in_range(alloc, absolute_byte_offset, size) {
+            return translate_enum_constant_from_alloc(
+                ctx,
+                alloc,
+                absolute_byte_offset,
+                rust_ty,
+                ty_ptr,
+                block_ptr,
+                prev_op,
+                loc,
+            );
+        }
+    }
+
+    let size = constant_field_byte_size(ctx, rust_ty, ty_ptr, &loc)?;
+    // Fail closed: the bytes under a relocation are an addend into the target
+    // allocation, not literal data. Decoding them as a non-pointer value
+    // would silently strip the pointer they represent.
+    if alloc_has_provenance_in_range(alloc, absolute_byte_offset, size) {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Constant field of type {rust_ty:?} at byte offset {absolute_byte_offset} \
+                 overlaps a pointer relocation; only supported pointer or slice fields can \
+                 carry provenance in aggregate constants"
+            ))
+        );
+    }
+    // ZSTs: layout size 0.
+    if size == 0 || types::is_zst_type(ctx, ty_ptr) {
+        // Still need Rust ADT metadata for empty aggregates.
+        if matches!(
+            rust_ty.kind(),
+            TyKind::RigidTy(RigidTy::Tuple(_)) | TyKind::RigidTy(RigidTy::Adt(_, _))
+        ) {
+            let bytes = alloc_slice_bytes_zeroing_uninit(
+                alloc,
+                absolute_byte_offset,
+                size,
+                "ZST field",
+                &loc,
+            )?;
+            return translate_constant_value_from_bytes(
+                ctx, rust_ty, ty_ptr, &bytes, block_ptr, prev_op, loc,
+            );
+        }
+        return translate_zero_sized_constant_value(ctx, ty_ptr, block_ptr, prev_op, loc);
+    }
+
+    let bytes = alloc_slice_bytes_zeroing_uninit(
+        alloc,
+        absolute_byte_offset,
+        size,
+        "Constant field",
+        &loc,
+    )?;
+    translate_constant_value_from_bytes(ctx, rust_ty, ty_ptr, &bytes, block_ptr, prev_op, loc)
+}
+
+pub(super) fn translate_tuple_constant_from_alloc(
+    ctx: &mut Context,
+    alloc: &rustc_public::ty::Allocation,
+    base_offset: usize,
+    rust_ty: &rustc_public::ty::Ty,
+    const_ty_ptr: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let field_types: Vec<TypeHandle> = {
+        let ty_ref = const_ty_ptr.deref(ctx);
+        let tuple_ty = ty_ref
+            .downcast_ref::<dialect_mir::types::MirTupleType>()
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(
+                    "translate_tuple_constant_from_alloc called on non-tuple type"
+                ))
+            })?;
+        tuple_ty.get_types().to_vec()
+    };
+
+    let rust_field_types = match rust_ty.kind() {
+        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Tuple(fields)) => {
+            fields.to_vec()
+        }
+        other => {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Tuple constant expected Rust tuple type, got {other:?}"
+                ))
+            );
+        }
+    };
+    if field_types.len() != rust_field_types.len() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Tuple constant type mismatch: MIR has {} fields, Rust type has {}",
+                field_types.len(),
+                rust_field_types.len()
+            ))
+        );
+    }
+
+    let field_offsets = crate::translator::layout::aggregate_field_offsets(rust_ty, "Tuple", &loc)?;
+    if field_offsets.len() != field_types.len() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Tuple constant layout has {} offsets for {} fields",
+                field_offsets.len(),
+                field_types.len()
+            ))
+        );
+    }
+
+    let mut values = Vec::with_capacity(field_types.len());
+    let mut field_ranges = Vec::with_capacity(field_types.len());
+    let mut current_prev_op = prev_op;
+    for (field_idx, (field_ty, rust_field_ty)) in field_types
+        .iter()
+        .copied()
+        .zip(rust_field_types.iter())
+        .enumerate()
+    {
+        let abs = base_offset
+            .checked_add(field_offsets[field_idx])
+            .ok_or_else(|| {
+                input_error!(
+                    loc.clone(),
+                    TranslationErr::unsupported(format!(
+                        "Tuple constant field {field_idx} offset overflowed"
+                    ))
+                )
+            })?;
+        let field_size = constant_field_byte_size(ctx, rust_field_ty, field_ty, &loc)?;
+        field_ranges.push((abs, field_size));
+        let (value, new_prev_op) = translate_constant_value_from_alloc(
+            ctx,
+            alloc,
+            abs,
+            rust_field_ty,
+            field_ty,
+            block_ptr,
+            current_prev_op,
+            loc.clone(),
+        )?;
+        values.push(value);
+        current_prev_op = new_prev_op;
+    }
+
+    let tuple_size = rust_type_layout_size(*rust_ty, loc.clone())?;
+    audit_aggregate_relocations(alloc, base_offset, tuple_size, &field_ranges, "Tuple", &loc)?;
+
+    use dialect_mir::ops::MirConstructTupleOp;
+    let op = Operation::new(
+        ctx,
+        MirConstructTupleOp::get_concrete_op_info(),
+        vec![const_ty_ptr],
+        values,
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc);
+    if let Some(prev) = current_prev_op {
+        op.insert_after(ctx, prev);
+    } else {
+        op.insert_at_front(block_ptr, ctx);
+    }
+    Ok((op.deref(ctx).get_result(0), Some(op)))
+}
+
+pub(super) fn translate_struct_constant_from_alloc(
+    ctx: &mut Context,
+    alloc: &rustc_public::ty::Allocation,
+    base_offset: usize,
+    rust_ty: &rustc_public::ty::Ty,
+    const_ty_ptr: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    use rustc_public::ty::{RigidTy, TyKind};
+
+    let field_types: Vec<TypeHandle> = {
+        let ty_obj = const_ty_ptr.deref(ctx);
+        let struct_ty = ty_obj
+            .downcast_ref::<dialect_mir::types::MirStructType>()
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(
+                    "translate_struct_constant_from_alloc called on non-struct type"
+                ))
+            })?;
+        struct_ty.field_types().to_vec()
+    };
+
+    // A zero-sized struct span holds no bytes and cannot carry relocations,
+    // and not every type that lands here as a MirStructType is an ADT:
+    // function items and non-capturing closures have no ADT metadata to
+    // consult. Synthesize such values from the dialect type alone.
+    let struct_size = rust_ty
+        .layout()
+        .map_err(|e| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Failed to query layout for struct constant: {:?}",
+                e
+            )))
+        })?
+        .shape()
+        .size
+        .bytes();
+    if struct_size == 0 {
+        return translate_zero_sized_constant_value(ctx, const_ty_ptr, block_ptr, prev_op, loc);
+    }
+
+    let field_offsets =
+        crate::translator::layout::aggregate_field_offsets(rust_ty, "Struct", &loc)?;
+    if field_offsets.len() != field_types.len() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Struct constant layout has {} field offsets, type has {} fields",
+                field_offsets.len(),
+                field_types.len()
+            ))
+        );
+    }
+
+    let (adt_def, substs) = match rust_ty.kind() {
+        TyKind::RigidTy(RigidTy::Adt(adt_def, substs)) => (adt_def, substs),
+        other => {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Expected ADT Rust type for struct constant, got {other:?}"
+                ))
+            );
+        }
+    };
+    let variants = adt_def.variants();
+    let struct_variant = variants.first().ok_or_else(|| {
+        input_error_noloc!(TranslationErr::unsupported(
+            "Struct ADT has no variants in metadata"
+        ))
+    })?;
+
+    let mut field_values = Vec::with_capacity(field_types.len());
+    let mut field_ranges = Vec::with_capacity(field_types.len());
+    let mut current_prev_op = prev_op;
+    for (field_idx, field_ty_ptr) in field_types.iter().copied().enumerate() {
+        let fields = struct_variant.fields();
+        let rust_field = fields.get(field_idx).ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Struct constant field {field_idx} is missing in rustc ADT metadata ({} field(s) recorded)",
+                fields.len()
+            )))
+        })?;
+        let rust_field_ty = rust_field.ty_with_args(&substs);
+        let abs = base_offset
+            .checked_add(field_offsets[field_idx])
+            .ok_or_else(|| {
+                input_error!(
+                    loc.clone(),
+                    TranslationErr::unsupported(format!(
+                        "Struct constant field {field_idx} offset overflowed"
+                    ))
+                )
+            })?;
+        let field_size = constant_field_byte_size(ctx, &rust_field_ty, field_ty_ptr, &loc)?;
+        field_ranges.push((abs, field_size));
+        let (field_val, new_prev_op) = translate_constant_value_from_alloc(
+            ctx,
+            alloc,
+            abs,
+            &rust_field_ty,
+            field_ty_ptr,
+            block_ptr,
+            current_prev_op,
+            loc.clone(),
+        )?;
+        field_values.push(field_val);
+        current_prev_op = new_prev_op;
+    }
+
+    let struct_size = rust_type_layout_size(*rust_ty, loc.clone())?;
+    audit_aggregate_relocations(
+        alloc,
+        base_offset,
+        struct_size,
+        &field_ranges,
+        "Struct",
+        &loc,
+    )?;
+
+    let (casted_field_values, prev_after_casts) = cast_struct_fields_to_expected_types(
+        ctx,
+        field_values,
+        const_ty_ptr,
+        block_ptr,
+        current_prev_op,
+        loc.clone(),
+    );
+
+    let op = Operation::new(
+        ctx,
+        MirConstructStructOp::get_concrete_op_info(),
+        vec![const_ty_ptr],
+        casted_field_values,
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc);
+    if let Some(prev) = prev_after_casts {
+        op.insert_after(ctx, prev);
+    } else {
+        op.insert_at_front(block_ptr, ctx);
+    }
+    Ok((op.deref(ctx).get_result(0), Some(op)))
+}
+
+/// Element kinds admitted by a bare array value constant
+/// (`translate_array_value_constant`).
+///
+/// Primitive scalars, enums, initialized unions, tuples, structs, and nested
+/// arrays are supported at this entry point. Nested arrays are walked
+/// recursively so an unsupported leaf cannot hide behind nesting. Struct
+/// elements reuse the same layout-aware aggregate decoders used when structs
+/// appear inside other constants. Arrays inside struct or tuple constants are
+/// dispatched through [`translate_constant_value_from_alloc`] and are not
+/// governed by this gate.
+pub(super) fn validate_array_value_element_type(
+    ctx: &Context,
+    element_ty: TypeHandle,
+    loc: &Location,
+) -> TranslationResult<()> {
+    let nested_element_ty = {
+        let elem_obj = element_ty.deref(ctx);
+        if elem_obj.is::<IntegerType>()
+            || elem_obj.is::<MirFP16Type>()
+            || elem_obj.is::<FP32Type>()
+            || elem_obj.is::<FP64Type>()
+            || elem_obj.is::<dialect_mir::types::MirTupleType>()
+            || elem_obj.is::<dialect_mir::types::MirStructType>()
+            || elem_obj.is::<dialect_mir::types::MirEnumType>()
+            || elem_obj.is::<dialect_mir::types::MirUnionType>()
+        {
+            return Ok(());
+        }
+        let Some(array_ty) = elem_obj.downcast_ref::<dialect_mir::types::MirArrayType>() else {
+            return input_err!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Array constant element type is not supported: {:?}. Supported array \
+                     constants are primitive scalars, enums, initialized unions, tuples, \
+                     structs, or nested arrays of those.",
+                    elem_obj
+                ))
+            );
+        };
+        array_ty.element_type()
+    };
+    validate_array_value_element_type(ctx, nested_element_ty, loc)
+}
+
+pub(super) fn translate_array_constant_from_alloc(
+    ctx: &mut Context,
+    alloc: &rustc_public::ty::Allocation,
+    base_offset: usize,
+    rust_array_ty: &rustc_public::ty::Ty,
+    array_ty: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let (element_ty_ptr, element_count) = {
+        let arr_ty_obj = array_ty.deref(ctx);
+        let arr_ty = arr_ty_obj
+            .downcast_ref::<dialect_mir::types::MirArrayType>()
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(
+                    "translate_array_constant_from_alloc: expected array type"
+                ))
+            })?;
+        (arr_ty.element_type(), arr_ty.size())
+    };
+
+    let (rust_element_ty, rust_element_count) = rust_array_type_info(*rust_array_ty, loc.clone())?;
+    if rust_element_count != element_count {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Array constant length mismatch: Rust type has {rust_element_count} elements, \
+                 dialect type has {element_count}"
+            ))
+        );
+    }
+    let element_byte_size = rust_type_layout_size(rust_element_ty, loc.clone())?;
+    let element_count_usize = usize::try_from(element_count).map_err(|_| {
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "Array constant element count {element_count} does not fit usize"
+        )))
+    })?;
+
+    let mut element_values = Vec::with_capacity(element_count_usize);
+    let mut element_ranges = Vec::with_capacity(element_count_usize);
+    let mut last_op = prev_op;
+    for i in 0..element_count_usize {
+        let abs = base_offset
+            .checked_add(i.checked_mul(element_byte_size).ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Array constant element {i} stride overflowed"
+                )))
+            })?)
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Array constant element {i} absolute offset overflowed"
+                )))
+            })?;
+        element_ranges.push((abs, element_byte_size));
+        let (elem_val, elem_last_op) = translate_constant_value_from_alloc(
+            ctx,
+            alloc,
+            abs,
+            &rust_element_ty,
+            element_ty_ptr,
+            block_ptr,
+            last_op,
+            loc.clone(),
+        )?;
+        element_values.push(elem_val);
+        last_op = elem_last_op;
+    }
+
+    let array_size = rust_type_layout_size(*rust_array_ty, loc.clone())?;
+    audit_aggregate_relocations(
+        alloc,
+        base_offset,
+        array_size,
+        &element_ranges,
+        "Array",
+        &loc,
+    )?;
+
+    let op = Operation::new(
+        ctx,
+        MirConstructArrayOp::get_concrete_op_info(),
+        vec![array_ty],
+        element_values,
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc);
+    if let Some(prev) = last_op {
+        op.insert_after(ctx, prev);
+    } else {
+        op.insert_at_front(block_ptr, ctx);
+    }
+    Ok((op.deref(ctx).get_result(0), Some(op)))
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production code mints via facts::PointerOrigin.
+#[allow(clippy::disallowed_methods)]
+mod aggregate_relocation_tests {
+    use super::super::const_bytes::constant_type_contains_pointer;
+    use super::super::const_union::{
+        UnionConstantStorageKind, UnionConstantUse, classify_union_constant_storage,
+        relocation_free_pointer_integer_union_storage_field,
+        translate_pointer_integer_union_constant_from_storage,
+        validate_device_static_union_storage,
+    };
+    use super::{
+        decode_relocation_addend, find_unconsumed_relocation, match_thin_pointer_relocation,
+        provenance_starts_in_range, relocation_offsets_overlapping_range,
+        validate_array_value_element_type, validate_slice_relocation_shape,
+    };
+    use dialect_mir::ops::{MirCastOp, MirInsertFieldOp};
+    use dialect_mir::types::{
+        EnumVariant, MirArrayType, MirEnumType, MirPointerKind, MirPtrType, MirStructType,
+        MirTupleType, MirUnionType, pointer_carriers_in_type,
+    };
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::common_traits::Verify;
+    use pliron::context::Context;
+    use pliron::linked_list::ContainsLinkedList;
+    use pliron::location::Location;
+    use pliron::op::Op;
+    use pliron::operation::Operation;
+    use pliron::r#type::TypeHandle;
+    use pliron::r#type::Typed;
+    use rustc_public::target::Endian;
+
+    #[test]
+    fn relocation_overlap_detects_exact_and_left_crossing_pointer_words() {
+        let ptrs = [(0usize, ()), (8, ()), (24, ())];
+        assert_eq!(
+            relocation_offsets_overlapping_range(&ptrs, 8, 16, 8),
+            vec![8],
+            "an exact full-width relocation covers the carrier"
+        );
+        assert_eq!(
+            relocation_offsets_overlapping_range(&ptrs, 4, 12, 8),
+            vec![0, 8],
+            "overlap detection must include relocations starting before the carrier"
+        );
+        assert!(
+            relocation_offsets_overlapping_range(&ptrs, 16, 24, 8).is_empty(),
+            "touching a range boundary is not an overlap"
+        );
+    }
+
+    #[test]
+    fn aggregate_slice_relocation_accepts_nonzero_field_offset_with_siblings() {
+        let ptrs = [(0usize, ()), (8, ()), (24, ())];
+        assert_eq!(
+            validate_slice_relocation_shape(&ptrs, 8, 8),
+            Ok((16, 24)),
+            "sibling relocations outside the fat-pointer bytes must not interfere"
+        );
+    }
+
+    #[test]
+    fn aggregate_slice_relocation_rejects_metadata_provenance() {
+        let ptrs = [(8usize, ()), (16, ())];
+        let error = validate_slice_relocation_shape(&ptrs, 8, 8)
+            .expect_err("the metadata word must remain literal usize bytes");
+        assert!(
+            error.contains("additional relocation at byte 16"),
+            "diagnostic must identify metadata provenance: {error}"
+        );
+    }
+
+    #[test]
+    fn aggregate_slice_relocation_requires_data_word_provenance_at_field_start() {
+        let ptrs = [(12usize, ())];
+        let error = validate_slice_relocation_shape(&ptrs, 8, 8)
+            .expect_err("interior provenance cannot stand in for the slice data word");
+        assert!(
+            error.contains("0 provenance entries at its data-word start"),
+            "diagnostic must require an anchored data relocation: {error}"
+        );
+
+        let duplicate = [(8usize, 1u8), (8, 2u8)];
+        let error = validate_slice_relocation_shape(&duplicate, 8, 8)
+            .expect_err("two data-word provenance entries are ambiguous");
+        assert!(
+            error.contains("2 provenance entries at its data-word start"),
+            "diagnostic must count duplicate anchored relocations: {error}"
+        );
+    }
+
+    #[test]
+    fn aggregate_slice_relocation_rejects_left_crossing_pointer_storage() {
+        let ptrs = [(4usize, ()), (8, ())];
+        let error = validate_slice_relocation_shape(&ptrs, 8, 8)
+            .expect_err("a relocation from the preceding bytes must not overlap the slice");
+        assert!(
+            error.contains("additional relocation at byte 4"),
+            "diagnostic must identify the crossing relocation: {error}"
+        );
+    }
+
+    #[test]
+    fn relocation_matching_is_anchored_to_the_field_base() {
+        let ptrs = [(0usize, 1u32), (16, 2)];
+        assert_eq!(
+            match_thin_pointer_relocation(&ptrs, 16, 24),
+            Ok(Some(2)),
+            "the entry at the field base must be matched"
+        );
+        assert_eq!(
+            match_thin_pointer_relocation(&ptrs, 8, 16),
+            Ok(None),
+            "entries outside the field belong to sibling fields, not this one"
+        );
+    }
+
+    #[test]
+    fn relocation_matching_rejects_duplicate_entries_at_the_base() {
+        let ptrs = [(8usize, 1u32), (8, 2)];
+        let error = match_thin_pointer_relocation(&ptrs, 8, 16)
+            .expect_err("two provenance entries at one offset must fail closed");
+        assert!(
+            error.contains("2 provenance entries"),
+            "diagnostic must count the entries: {error}"
+        );
+    }
+
+    #[test]
+    fn relocation_matching_rejects_interior_provenance() {
+        let ptrs = [(12usize, 7u32)];
+        let error = match_thin_pointer_relocation(&ptrs, 8, 16)
+            .expect_err("provenance strictly inside a thin field is fat-pointer bits");
+        assert!(
+            error.contains("interior provenance at byte 12"),
+            "diagnostic must name the interior byte: {error}"
+        );
+    }
+
+    #[test]
+    fn relocation_addend_decodes_with_the_given_endianness() {
+        let mut bytes = vec![Some(0u8); 16];
+        bytes[8] = Some(0x28);
+        assert_eq!(
+            decode_relocation_addend(&bytes, 8, 8, Endian::Little),
+            Ok(0x28),
+            "little-endian addend must read the low byte first"
+        );
+        assert_eq!(
+            decode_relocation_addend(&bytes, 8, 8, Endian::Big),
+            Ok(0x28u128 << 56),
+            "big-endian addend must read the high byte first"
+        );
+    }
+
+    #[test]
+    fn relocation_addend_rejects_uninitialized_and_out_of_bounds_bytes() {
+        let mut bytes = vec![Some(0u8); 16];
+        bytes[10] = None;
+        let error = decode_relocation_addend(&bytes, 8, 8, Endian::Little)
+            .expect_err("addend bytes under a relocation are always initialized");
+        assert!(
+            error.contains("uninitialized"),
+            "diagnostic must name the failure: {error}"
+        );
+
+        let error = decode_relocation_addend(&bytes, 12, 8, Endian::Little)
+            .expect_err("an addend past the allocation end must fail closed");
+        assert!(
+            error.contains("needs 8 bytes"),
+            "diagnostic must name the missing width: {error}"
+        );
+    }
+
+    #[test]
+    fn non_pointer_fields_detect_overlapping_relocations() {
+        let ptrs = [(4usize, ())];
+        assert!(
+            provenance_starts_in_range(&ptrs, 4, 4),
+            "a relocation at the field base overlaps the field"
+        );
+        assert!(
+            provenance_starts_in_range(&ptrs, 0, 8),
+            "a relocation inside the field range overlaps the field"
+        );
+        assert!(
+            !provenance_starts_in_range(&ptrs, 8, 8),
+            "a relocation before the field does not start inside it"
+        );
+        assert!(
+            !provenance_starts_in_range(&ptrs, 4, 0),
+            "a zero-sized field cannot overlap any relocation"
+        );
+    }
+
+    #[test]
+    fn unconsumed_relocation_audit_flags_padding_only() {
+        let padding_relocation = [(12usize, ())];
+        assert_eq!(
+            find_unconsumed_relocation(&padding_relocation, 0, 16, &[(0, 8), (8, 4)]),
+            Some(12),
+            "a relocation in padding is consumed by no field and must be reported"
+        );
+        assert_eq!(
+            find_unconsumed_relocation(&padding_relocation, 0, 16, &[(0, 8), (8, 8)]),
+            None,
+            "a relocation covered by a field is that field's responsibility"
+        );
+        assert_eq!(
+            find_unconsumed_relocation(&padding_relocation, 16, 16, &[(16, 8)]),
+            None,
+            "relocations outside the aggregate's range belong to its siblings"
+        );
+        assert_eq!(
+            find_unconsumed_relocation(&padding_relocation, 0, 16, &[(0, 12), (12, 0)]),
+            Some(12),
+            "a zero-sized field consumes nothing"
+        );
+    }
+
+    #[test]
+    fn bare_array_elements_follow_the_documented_contract() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        assert!(
+            validate_array_value_element_type(&ctx, u32_ty, &Location::Unknown).is_ok(),
+            "primitive scalar elements remain supported"
+        );
+
+        let tuple_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![u32_ty]).into();
+        assert!(
+            validate_array_value_element_type(&ctx, tuple_ty, &Location::Unknown).is_ok(),
+            "tuple elements remain supported"
+        );
+        let nested_array_ty: TypeHandle = MirArrayType::get(&mut ctx, u32_ty, 4).into();
+        assert!(
+            validate_array_value_element_type(&ctx, nested_array_ty, &Location::Unknown).is_ok(),
+            "nested array elements remain supported"
+        );
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "Side".into(),
+            u8_ty,
+            vec![2, 5],
+            vec![
+                EnumVariant::unit("Low".into()),
+                EnumVariant::unit("High".into()),
+            ],
+            0,
+            1,
+            1,
+        )
+        .into();
+        assert!(
+            validate_array_value_element_type(&ctx, enum_ty, &Location::Unknown).is_ok(),
+            "bare enum-array elements are supported"
+        );
+        let nested_enum_array: TypeHandle = MirArrayType::get(&mut ctx, enum_ty, 2).into();
+        assert!(
+            validate_array_value_element_type(&ctx, nested_enum_array, &Location::Unknown).is_ok(),
+            "nesting preserves supported enum leaves"
+        );
+
+        let bytes_ty: TypeHandle = MirArrayType::get(&mut ctx, u8_ty, 4).into();
+        let union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "Bits".into(),
+            vec!["word".into(), "bytes".into()],
+            vec![u32_ty, bytes_ty],
+            4,
+            4,
+        )
+        .into();
+        assert!(
+            validate_array_value_element_type(&ctx, union_ty, &Location::Unknown).is_ok(),
+            "initialized union elements are supported"
+        );
+        let nested_union_array: TypeHandle = MirArrayType::get(&mut ctx, union_ty, 2).into();
+        assert!(
+            validate_array_value_element_type(&ctx, nested_union_array, &Location::Unknown).is_ok(),
+            "nesting preserves supported union leaves"
+        );
+        assert!(
+            !constant_type_contains_pointer(&ctx, union_ty),
+            "the byte-materialized Bits shape is pointer-free"
+        );
+
+        let pointer_field_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let u8_pointer_field_ty: TypeHandle =
+            MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
+        let pointer_only_union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "PointerOnly".into(),
+            vec!["word".into(), "bytes".into()],
+            vec![pointer_field_ty, u8_pointer_field_ty],
+            8,
+            8,
+        )
+        .into();
+        assert!(
+            constant_type_contains_pointer(&ctx, pointer_only_union_ty),
+            "pointer-only union constants must use typed reconstruction"
+        );
+        assert_eq!(
+            classify_union_constant_storage(
+                &ctx,
+                pointer_only_union_ty,
+                UnionConstantUse::SsaReconstruction
+            ),
+            Ok(UnionConstantStorageKind::ThinPointer {
+                field_index: 0,
+                field_ty: pointer_field_ty,
+            }),
+            "compatible thin-pointer alternatives can share one provenance-bearing carrier"
+        );
+
+        assert!(
+            validate_array_value_element_type(&ctx, pointer_only_union_ty, &Location::Unknown)
+                .is_ok(),
+            "bare arrays of pointer-only unions must reach the provenance-aware union decoder"
+        );
+
+        let u64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let raw_const_pointer_field_ty: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::RawConst)
+                .into();
+        let pointer_integer_union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "PointerBits".into(),
+            vec!["ptr".into(), "bits".into()],
+            vec![raw_const_pointer_field_ty, u64_ty],
+            8,
+            8,
+        )
+        .into();
+        let pointer_integer_error = classify_union_constant_storage(
+            &ctx,
+            pointer_integer_union_ty,
+            UnionConstantUse::SsaReconstruction,
+        )
+        .expect_err("the provenance-aware classifier must keep pointer/integer overlap closed");
+        assert!(
+            pointer_integer_error.contains("pointer/integer union constants"),
+            "diagnostic must explain the provenance-vs-bits conflict: {pointer_integer_error}"
+        );
+        assert_eq!(
+            relocation_free_pointer_integer_union_storage_field(&ctx, pointer_integer_union_ty, 8),
+            Some((1, u64_ty)),
+            "a pointer-word ptr/u64 union is byte-image eligible when the allocation has no relocation"
+        );
+        assert_eq!(
+            relocation_free_pointer_integer_union_storage_field(&ctx, pointer_integer_union_ty, 4),
+            None,
+            "the exception must not cross a target pointer-width mismatch"
+        );
+
+        let u32_pointer_integer_union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "PointerNarrowBits".into(),
+            vec!["ptr".into(), "bits".into()],
+            vec![raw_const_pointer_field_ty, u32_ty],
+            8,
+            8,
+        )
+        .into();
+        assert_eq!(
+            relocation_free_pointer_integer_union_storage_field(
+                &ctx,
+                u32_pointer_integer_union_ty,
+                8
+            ),
+            None,
+            "partial-width integer alternatives stay outside the initial pointer-word exception"
+        );
+
+        let slice_ty: TypeHandle = dialect_mir::types::MirSliceType::get(&mut ctx, u32_ty).into();
+        let fat_pointer_union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "FatPointer".into(),
+            vec!["slice".into(), "ptr".into()],
+            vec![slice_ty, pointer_field_ty],
+            16,
+            8,
+        )
+        .into();
+        let fat_pointer_error = classify_union_constant_storage(
+            &ctx,
+            fat_pointer_union_ty,
+            UnionConstantUse::SsaReconstruction,
+        )
+        .expect_err("fat-pointer union storage must remain fail-closed");
+        assert!(
+            fat_pointer_error.contains("not a thin pointer"),
+            "diagnostic must identify unsupported fat/nested storage: {fat_pointer_error}"
+        );
+
+        let struct_ty: TypeHandle = MirStructType::get(
+            &mut ctx,
+            "ArrayValueElement".into(),
+            vec!["value".into()],
+            vec![u32_ty],
+        )
+        .into();
+        assert!(
+            validate_array_value_element_type(&ctx, struct_ty, &Location::Unknown).is_ok(),
+            "bare struct arrays are materialized by the layout-aware aggregate decoder"
+        );
+
+        let struct_array_ty: TypeHandle = MirArrayType::get(&mut ctx, struct_ty, 2).into();
+        assert!(
+            validate_array_value_element_type(&ctx, struct_array_ty, &Location::Unknown).is_ok(),
+            "nesting preserves supported struct leaves"
+        );
+
+        let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        assert!(
+            validate_array_value_element_type(&ctx, ptr_ty, &Location::Unknown).is_err(),
+            "direct pointer elements were never part of the bare array contract"
+        );
+    }
+
+    #[test]
+    fn relocation_free_pointer_integer_union_gate_is_raw_only() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let u64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let raw_mut_ty: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, true, MirPointerKind::RawMut)
+                .into();
+        let raw_mut_union: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "RawMutBits".into(),
+            vec!["ptr".into(), "bits".into()],
+            vec![raw_mut_ty, u64_ty],
+            8,
+            8,
+        )
+        .into();
+        assert_eq!(
+            relocation_free_pointer_integer_union_storage_field(&ctx, raw_mut_union, 8),
+            Some((1, u64_ty)),
+            "RawMut carries no uniqueness claim and may use the integer storage view"
+        );
+
+        let erased_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let shared_ty: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::SharedRef)
+                .into();
+        let unique_ty: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, true, MirPointerKind::UniqueRef)
+                .into();
+        let global_raw_ty: TypeHandle = MirPtrType::get_with_kind(
+            &mut ctx,
+            u32_ty,
+            false,
+            dialect_mir::types::address_space::GLOBAL,
+            MirPointerKind::RawConst,
+        )
+        .into();
+        let fn_marker: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "FnPtrTarget".into(),
+            vec![],
+            vec![],
+            vec![],
+            vec![],
+            0,
+            0,
+        )
+        .into();
+        let fn_token_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, fn_marker, false).into();
+
+        for (name, pointer_ty) in [
+            ("Erased", erased_ty),
+            ("SharedRef", shared_ty),
+            ("UniqueRef", unique_ty),
+            ("non-generic raw", global_raw_ty),
+            ("function token", fn_token_ty),
+        ] {
+            let union_ty: TypeHandle = MirUnionType::get(
+                &mut ctx,
+                format!("{name}Bits"),
+                vec!["ptr".into(), "bits".into()],
+                vec![pointer_ty, u64_ty],
+                8,
+                8,
+            )
+            .into();
+            assert_eq!(
+                relocation_free_pointer_integer_union_storage_field(&ctx, union_ty, 8),
+                None,
+                "{name} must not acquire a pointer category from integer-initialized union storage"
+            );
+        }
+    }
+
+    #[test]
+    fn pointer_only_union_classifier_preserves_reference_semantics() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let shared_u32: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::SharedRef)
+                .into();
+        let shared_u8: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u8_ty, false, MirPointerKind::SharedRef)
+                .into();
+        let raw_u32: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::RawConst)
+                .into();
+        let raw_u8: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u8_ty, false, MirPointerKind::RawConst)
+                .into();
+        let raw_mut_u32: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, true, MirPointerKind::RawMut)
+                .into();
+        let unique_u32: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, true, MirPointerKind::UniqueRef)
+                .into();
+
+        let raw_views: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "RawViews".into(),
+            vec!["word".into(), "byte".into()],
+            vec![raw_u32, raw_u8],
+            8,
+            8,
+        )
+        .into();
+        assert!(
+            classify_union_constant_storage(&ctx, raw_views, UnionConstantUse::SsaReconstruction)
+                .is_ok(),
+            "same-kind raw pointers may safely use different pointee views"
+        );
+
+        for (name, fields, expected) in [
+            (
+                "MixedReferencePointees",
+                vec![shared_u32, shared_u8],
+                "reference pointee types",
+            ),
+            (
+                "MixedRawKinds",
+                vec![raw_u32, raw_mut_u32],
+                "pointer storage semantics",
+            ),
+            ("UniqueReference", vec![unique_u32, unique_u32], "UniqueRef"),
+        ] {
+            let union_ty: TypeHandle = MirUnionType::get(
+                &mut ctx,
+                name.into(),
+                vec!["first".into(), "second".into()],
+                fields,
+                8,
+                8,
+            )
+            .into();
+            let error = classify_union_constant_storage(
+                &ctx,
+                union_ty,
+                UnionConstantUse::SsaReconstruction,
+            )
+            .expect_err("ambiguous pointer semantics must fail closed");
+            assert!(
+                error.contains(expected),
+                "{name} diagnostic must identify {expected}: {error}"
+            );
+        }
+
+        // Physical device-static storage emits exact bytes plus one
+        // integer-width relocation slot and never mints a typed reference, so
+        // same-kind reference alternatives with different pointee views stay
+        // supported there (e.g. `union { word: &'static u32, byte: &'static u8 }`).
+        let mixed_reference_pointees: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "MixedReferencePointees".into(),
+            vec!["first".into(), "second".into()],
+            vec![shared_u32, shared_u8],
+            8,
+            8,
+        )
+        .into();
+        assert!(
+            classify_union_constant_storage(
+                &ctx,
+                mixed_reference_pointees,
+                UnionConstantUse::PhysicalStorage
+            )
+            .is_ok(),
+            "physical initializer storage must keep mixed-pointee reference unions supported"
+        );
+    }
+
+    #[test]
+    fn pointer_integer_union_materialization_never_transmutes_to_a_pointer_carrier() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let u64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let raw_ty: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::RawConst)
+                .into();
+        let union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "PointerOrBits".into(),
+            vec!["pointer".into(), "bits".into()],
+            vec![raw_ty, u64_ty],
+            8,
+            8,
+        )
+        .into();
+        let block = BasicBlock::new(&mut ctx, None, vec![]);
+
+        let (value, last_op) = translate_pointer_integer_union_constant_from_storage(
+            &mut ctx,
+            union_ty,
+            1,
+            u64_ty,
+            &[
+                Some(0x88),
+                Some(0x77),
+                Some(0x66),
+                Some(0x55),
+                Some(0x44),
+                Some(0x33),
+                Some(0x22),
+                Some(0x11),
+            ],
+            block,
+            None,
+            Location::Unknown,
+        )
+        .expect("the exact raw-pointer/integer storage shape must materialize");
+        assert_eq!(value.get_type(&ctx), union_ty);
+
+        let last_op = last_op.expect("non-empty storage must emit an insert operation");
+        let insert = Operation::get_op::<MirInsertFieldOp>(last_op, &ctx)
+            .expect("the final operation must insert the integer union field");
+        assert_eq!(
+            insert.get_attr_insert_index(&ctx).map(|index| index.0),
+            Some(1)
+        );
+        assert!(insert.verify(&ctx).is_ok());
+
+        for operation in block.deref(&ctx).iter(&ctx) {
+            if let Some(cast) = Operation::get_op::<MirCastOp>(operation, &ctx) {
+                assert!(cast.verify(&ctx).is_ok());
+                let result_ty = cast
+                    .get_operation()
+                    .deref(&ctx)
+                    .get_result(0)
+                    .get_type(&ctx);
+                assert!(
+                    pointer_carriers_in_type(&ctx, result_ty).is_empty(),
+                    "constant storage may transmute bytes to the integer field, never to a pointer-bearing union"
+                );
+            }
+        }
+    }
+
+    #[test]
+    fn device_static_union_storage_gate_admits_only_one_anchored_pointer_word() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let word_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let byte_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
+        let thin_pointer_union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "ThinPointerWord".into(),
+            vec!["word".into(), "bytes".into()],
+            vec![word_ptr_ty, byte_ptr_ty],
+            8,
+            8,
+        )
+        .into();
+
+        assert_eq!(
+            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 8, 8, 8, &[(0, 8)]),
+            Ok(()),
+            "one naturally aligned pointer word with one anchored relocation is the \
+             accepted shape"
+        );
+
+        // The example shape `union { word: &'static u32, byte: &'static u8 }`:
+        // same-kind references with different pointee views. The storage gate
+        // emits bytes plus one relocation slot and never mints a typed
+        // reference, so this stays supported even though SSA reconstruction
+        // of the same union fails closed.
+        let shared_word_ty: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u32_ty, false, MirPointerKind::SharedRef)
+                .into();
+        let shared_byte_ty: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, u8_ty, false, MirPointerKind::SharedRef)
+                .into();
+        let mixed_reference_union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "MixedReferenceWord".into(),
+            vec!["word".into(), "byte".into()],
+            vec![shared_word_ty, shared_byte_ty],
+            8,
+            8,
+        )
+        .into();
+        assert_eq!(
+            validate_device_static_union_storage(
+                &ctx,
+                mixed_reference_union_ty,
+                8,
+                8,
+                8,
+                &[(0, 8)]
+            ),
+            Ok(()),
+            "mixed-pointee reference unions remain valid device-static storage"
+        );
+
+        let byte_image_error =
+            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 4, 8, 8, &[(0, 8)])
+                .expect_err("a 32-bit pointer target must remain fail-closed");
+        assert!(
+            byte_image_error.contains("8-byte NVPTX pointers"),
+            "diagnostic must name the pointer-width restriction: {byte_image_error}"
+        );
+
+        let bytes_ty: TypeHandle = MirArrayType::get(&mut ctx, u8_ty, 4).into();
+        let pointer_free_union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "Bits".into(),
+            vec!["word".into(), "bytes".into()],
+            vec![u32_ty, bytes_ty],
+            4,
+            4,
+        )
+        .into();
+        let storage_error =
+            validate_device_static_union_storage(&ctx, pointer_free_union_ty, 8, 4, 4, &[(0, 8)])
+                .expect_err("byte-image unions take the literal-bytes path, not this gate");
+        assert!(
+            storage_error.contains("without thin-pointer storage"),
+            "diagnostic must explain the thin-pointer requirement: {storage_error}"
+        );
+
+        let wide_union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "TwoWords".into(),
+            vec!["first".into(), "second".into()],
+            vec![word_ptr_ty, byte_ptr_ty],
+            16,
+            8,
+        )
+        .into();
+        let size_error =
+            validate_device_static_union_storage(&ctx, wide_union_ty, 8, 16, 8, &[(0, 8)])
+                .expect_err("a union wider than one pointer word must remain fail-closed");
+        assert!(
+            size_error.contains("size/alignment 16/8"),
+            "diagnostic must report the rejected layout: {size_error}"
+        );
+
+        let initializer_error =
+            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 8, 16, 8, &[(0, 8)])
+                .expect_err("an over-sized evaluated initializer must remain fail-closed");
+        assert!(
+            initializer_error.contains("initializer size/alignment 16/8"),
+            "diagnostic must report the evaluated-initializer mismatch: {initializer_error}"
+        );
+
+        let uninit_error =
+            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 8, 8, 8, &[])
+                .expect_err("zero relocations (e.g. a ZST-field initializer) must fail closed");
+        assert!(
+            uninit_error.contains("0 initializer relocations"),
+            "diagnostic must count the missing relocation: {uninit_error}"
+        );
+
+        let multi_error = validate_device_static_union_storage(
+            &ctx,
+            thin_pointer_union_ty,
+            8,
+            8,
+            8,
+            &[(0, 4), (4, 4)],
+        )
+        .expect_err("two relocations cannot describe one pointer word");
+        assert!(
+            multi_error.contains("2 initializer relocations"),
+            "diagnostic must count the extra relocations: {multi_error}"
+        );
+
+        let offset_error =
+            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 8, 8, 8, &[(4, 8)])
+                .expect_err("a relocation off the word base must remain fail-closed");
+        assert!(
+            offset_error.contains("occupies byte 4"),
+            "diagnostic must locate the misplaced relocation: {offset_error}"
+        );
+
+        let width_error =
+            validate_device_static_union_storage(&ctx, thin_pointer_union_ty, 8, 8, 8, &[(0, 4)])
+                .expect_err("a narrow relocation cannot carry full pointer provenance");
+        assert!(
+            width_error.contains("width 4"),
+            "diagnostic must report the short relocation: {width_error}"
+        );
+    }
+}
diff --git a/crates/mir-importer/src/translator/rvalue/const_bytes.rs b/crates/mir-importer/src/translator/rvalue/const_bytes.rs
new file mode 100644
index 0000000000..a9cde3fddb
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/const_bytes.rs
@@ -0,0 +1,1748 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Relocation-free constant decoding from raw allocation bytes.
+
+use super::coerce::cast_struct_fields_to_expected_types;
+use super::const_alloc::{
+    translate_array_constant_from_alloc, translate_struct_constant_from_alloc,
+    translate_tuple_constant_from_alloc, validate_array_value_element_type,
+};
+use super::const_enum::{read_uint_from_bytes, translate_enum_constant_from_bytes};
+use super::promoted::constant_allocation;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::types;
+use dialect_mir::attributes::MirFP16Attr;
+use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
+use dialect_mir::ops::{MirCastOp, MirConstructStructOp, MirUndefOp};
+use dialect_mir::types::MirFP16Type;
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{FP32Type, FP64Type, IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::TypeHandle;
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use pliron::{input_err, input_error, input_error_noloc};
+use rustc_public::mir;
+use rustc_public::ty::ConstantKind;
+use std::num::NonZeroUsize;
+
+/// Lower a bare `MirArrayType` value constant (e.g. `const TABLE: [f32; N] =
+/// [..]` indexed by runtime value) to a `MirConstructArrayOp`. Element stride
+/// and aggregate field offsets come from rustc layout. Thin pointer fields
+/// inside elements that relocate to device statics are materialized via
+/// [`MirGlobalAllocOp`] per field.
+pub(super) fn translate_array_value_constant(
+    ctx: &mut Context,
+    constant: &mir::ConstOperand,
+    const_ty_ptr: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let element_ty = {
+        let ty_obj = const_ty_ptr.deref(ctx);
+        let Some(array_ty) = ty_obj.downcast_ref::<dialect_mir::types::MirArrayType>() else {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported("translate_array_value_constant: expected array type")
+            );
+        };
+        array_ty.element_type()
+    };
+
+    // Bare array values support primitive scalars, enums, initialized unions,
+    // tuples, structs, and nested arrays of those. Struct elements are decoded
+    // through the existing layout-aware aggregate path while pointer-to-array
+    // promotion remains intentionally unchanged; arrays nested inside struct
+    // constants have their own layout-aware entry point.
+    validate_array_value_element_type(ctx, element_ty, &loc)?;
+
+    let rust_array_ty = constant.const_.ty();
+    let alloc = match constant.const_.kind() {
+        ConstantKind::Allocated(alloc) => alloc.clone(),
+        ConstantKind::Ty(ty_const) => match ty_const.kind() {
+            rustc_public::ty::TyConstKind::Value(_, alloc) => alloc.clone(),
+            other => {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Array value constant must be backed by bytes, found TyConstKind::{other:?}"
+                    ))
+                );
+            }
+        },
+        ConstantKind::ZeroSized => {
+            return translate_array_value_constant_inner(
+                ctx,
+                constant,
+                const_ty_ptr,
+                rust_array_ty,
+                block_ptr,
+                prev_op,
+                loc,
+            );
+        }
+        other => {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Array value constant must be Allocated or Ty::Value, got {other:?}"
+                ))
+            );
+        }
+    };
+
+    translate_array_constant_from_alloc(
+        ctx,
+        &alloc,
+        0,
+        &rust_array_ty,
+        const_ty_ptr,
+        block_ptr,
+        prev_op,
+        loc,
+    )
+}
+
+pub(super) fn rust_type_layout_size(
+    ty: rustc_public::ty::Ty,
+    loc: Location,
+) -> TranslationResult<usize> {
+    ty.layout()
+        .map(|layout| layout.shape().size.bytes())
+        .map_err(|error| {
+            input_error!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Failed to query rustc layout for constant type {ty:?}: {error:?}"
+                ))
+            )
+        })
+}
+
+pub(super) fn rust_array_type_info(
+    ty: rustc_public::ty::Ty,
+    loc: Location,
+) -> TranslationResult<(rustc_public::ty::Ty, u64)> {
+    match ty.kind() {
+        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Array(element_ty, count)) => {
+            let count = count.eval_target_usize().map_err(|error| {
+                input_error!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Failed to evaluate array constant length: {error:?}"
+                    ))
+                )
+            })?;
+            Ok((element_ty, count))
+        }
+        other => input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Array constant expected a Rust array type, got {other:?}"
+            ))
+        ),
+    }
+}
+
+/// Build a `MirConstructArrayOp` (and the necessary scalar / nested-array
+/// element ops) from a slice of raw bytes for an `array_ty`. Recurses on
+/// `MirArrayType` element types so multi-dimensional arrays (`[[T; M]; N]`,
+/// etc.) are handled by repeated decomposition.
+fn build_array_op_from_bytes(
+    ctx: &mut Context,
+    array_ty: TypeHandle,
+    rust_array_ty: rustc_public::ty::Ty,
+    bytes: &[u8],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    use pliron::builtin::types::{FP32Type, FP64Type, IntegerType};
+
+    // Element type + count.
+    let (element_ty_ptr, element_count) = {
+        let arr_ty_obj = array_ty.deref(ctx);
+        let arr_ty = arr_ty_obj
+            .downcast_ref::<dialect_mir::types::MirArrayType>()
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(
+                    "build_array_op_from_bytes: expected array type"
+                ))
+            })?;
+        (arr_ty.element_type(), arr_ty.size())
+    };
+
+    let (rust_element_ty, rust_element_count) = rust_array_type_info(rust_array_ty, loc.clone())?;
+    if rust_element_count != element_count {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Array constant length mismatch: Rust type has {rust_element_count} elements, dialect type has {element_count}"
+            ))
+        );
+    }
+    let element_byte_size = rust_type_layout_size(rust_element_ty, loc.clone())?;
+
+    let element_count_usize = usize::try_from(element_count).map_err(|_| {
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "Array constant element count {element_count} does not fit usize"
+        )))
+    })?;
+    let expected_bytes = element_count_usize
+        .checked_mul(element_byte_size)
+        .ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Array constant byte size overflowed: {} elements x {} bytes each",
+                element_count, element_byte_size
+            )))
+        })?;
+    if bytes.len() != expected_bytes {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Array constant has {} bytes but requires exactly {} ({} elements x {} bytes each)",
+                bytes.len(),
+                expected_bytes,
+                element_count,
+                element_byte_size
+            ))
+        );
+    }
+
+    #[derive(Clone, Copy)]
+    enum ElemKind {
+        F64,
+        F32,
+        F16,
+        Int { width: u32, signedness: Signedness },
+        Array,
+        Tuple,
+        Struct,
+    }
+    let elem_kind = {
+        let elem_obj = element_ty_ptr.deref(ctx);
+        if elem_obj.is::<FP64Type>() {
+            ElemKind::F64
+        } else if elem_obj.is::<FP32Type>() {
+            ElemKind::F32
+        } else if elem_obj.is::<MirFP16Type>() {
+            ElemKind::F16
+        } else if let Some(int_ty) = elem_obj.downcast_ref::<IntegerType>() {
+            ElemKind::Int {
+                width: int_ty.width(),
+                signedness: int_ty.signedness(),
+            }
+        } else if elem_obj.is::<dialect_mir::types::MirArrayType>() {
+            ElemKind::Array
+        } else if elem_obj.is::<dialect_mir::types::MirTupleType>() {
+            ElemKind::Tuple
+        } else if elem_obj.is::<dialect_mir::types::MirStructType>() {
+            ElemKind::Struct
+        } else {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Array constant element type is not supported by byte lowering: {:?}. \
+                     Byte lowering handles primitive scalars, tuples, structs, or nested \
+                     arrays of those. Enum elements decode from a constant \
+                     allocation instead, so an enum array that reaches byte lowering (e.g. \
+                     one with a zero-sized element) cannot be materialized here.",
+                    elem_obj
+                ))
+            );
+        }
+    };
+
+    let mut element_values = Vec::with_capacity(element_count_usize);
+    let mut last_op = prev_op;
+
+    for i in 0..element_count_usize {
+        let chunk = &bytes[i * element_byte_size..(i + 1) * element_byte_size];
+
+        let (elem_val, elem_last_op) = match elem_kind {
+            ElemKind::F64 => {
+                let mut buf = [0u8; 8];
+                buf.copy_from_slice(chunk);
+                let float_val = match rustc_public::target::MachineInfo::target_endianness() {
+                    rustc_public::target::Endian::Little => f64::from_le_bytes(buf),
+                    rustc_public::target::Endian::Big => f64::from_be_bytes(buf),
+                };
+                let float_attr = pliron::builtin::attributes::FPDoubleAttr::from(float_val);
+
+                use dialect_mir::ops::MirFloatConstantOp;
+                let op = Operation::new(
+                    ctx,
+                    MirFloatConstantOp::get_concrete_op_info(),
+                    vec![element_ty_ptr],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                op.deref_mut(ctx).set_loc(loc.clone());
+                let float_op = MirFloatConstantOp::new(op);
+                float_op.set_attr_float_value_f64(ctx, float_attr);
+
+                if let Some(prev) = last_op {
+                    float_op.get_operation().insert_after(ctx, prev);
+                } else {
+                    float_op.get_operation().insert_at_front(block_ptr, ctx);
+                }
+                (
+                    float_op.get_operation().deref(ctx).get_result(0),
+                    Some(float_op.get_operation()),
+                )
+            }
+            ElemKind::F32 => {
+                let mut buf = [0u8; 4];
+                buf.copy_from_slice(chunk);
+                let float_val = match rustc_public::target::MachineInfo::target_endianness() {
+                    rustc_public::target::Endian::Little => f32::from_le_bytes(buf),
+                    rustc_public::target::Endian::Big => f32::from_be_bytes(buf),
+                };
+                let float_attr = pliron::builtin::attributes::FPSingleAttr::from(float_val);
+
+                use dialect_mir::ops::MirFloatConstantOp;
+                let op = Operation::new(
+                    ctx,
+                    MirFloatConstantOp::get_concrete_op_info(),
+                    vec![element_ty_ptr],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                op.deref_mut(ctx).set_loc(loc.clone());
+                let float_op = MirFloatConstantOp::new(op);
+                float_op.set_attr_float_value(ctx, float_attr);
+
+                if let Some(prev) = last_op {
+                    float_op.get_operation().insert_after(ctx, prev);
+                } else {
+                    float_op.get_operation().insert_at_front(block_ptr, ctx);
+                }
+                (
+                    float_op.get_operation().deref(ctx).get_result(0),
+                    Some(float_op.get_operation()),
+                )
+            }
+            ElemKind::F16 => {
+                let bits = read_uint_from_bytes(chunk) as u16;
+                let float_attr = MirFP16Attr::from_bits(bits);
+
+                use dialect_mir::ops::MirFloatConstantOp;
+                let op = Operation::new(
+                    ctx,
+                    MirFloatConstantOp::get_concrete_op_info(),
+                    vec![element_ty_ptr],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                op.deref_mut(ctx).set_loc(loc.clone());
+                let float_op = MirFloatConstantOp::new(op);
+                float_op.set_attr_float_value_f16(ctx, float_attr);
+
+                if let Some(prev) = last_op {
+                    float_op.get_operation().insert_after(ctx, prev);
+                } else {
+                    float_op.get_operation().insert_at_front(block_ptr, ctx);
+                }
+                (
+                    float_op.get_operation().deref(ctx).get_result(0),
+                    Some(float_op.get_operation()),
+                )
+            }
+            ElemKind::Int { width, signedness } => {
+                let val = read_uint_from_bytes(chunk);
+                let apint = APInt::from_u128(val, NonZeroUsize::new(width as usize).unwrap());
+                let int_attr = pliron::builtin::attributes::IntegerAttr::new(
+                    IntegerType::get(ctx, width, signedness),
+                    apint,
+                );
+
+                use dialect_mir::ops::MirConstantOp;
+                let op = Operation::new(
+                    ctx,
+                    MirConstantOp::get_concrete_op_info(),
+                    vec![element_ty_ptr],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                op.deref_mut(ctx).set_loc(loc.clone());
+                let const_op = MirConstantOp::new(op);
+                const_op.set_attr_value(ctx, int_attr);
+
+                if let Some(prev) = last_op {
+                    const_op.get_operation().insert_after(ctx, prev);
+                } else {
+                    const_op.get_operation().insert_at_front(block_ptr, ctx);
+                }
+                (
+                    const_op.get_operation().deref(ctx).get_result(0),
+                    Some(const_op.get_operation()),
+                )
+            }
+            ElemKind::Array => build_array_op_from_bytes(
+                ctx,
+                element_ty_ptr,
+                rust_element_ty,
+                chunk,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?,
+            ElemKind::Tuple | ElemKind::Struct => translate_constant_value_from_bytes(
+                ctx,
+                &rust_element_ty,
+                element_ty_ptr,
+                chunk,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?,
+        };
+
+        element_values.push(elem_val);
+        last_op = elem_last_op;
+    }
+
+    use dialect_mir::ops::MirConstructArrayOp;
+    let construct_op = Operation::new(
+        ctx,
+        MirConstructArrayOp::get_concrete_op_info(),
+        vec![array_ty],
+        element_values,
+        vec![],
+        0,
+    );
+    construct_op.deref_mut(ctx).set_loc(loc.clone());
+
+    if let Some(prev) = last_op {
+        construct_op.insert_after(ctx, prev);
+    } else {
+        construct_op.insert_at_front(block_ptr, ctx);
+    }
+    last_op = Some(construct_op);
+
+    let array_val = construct_op.deref(ctx).get_result(0);
+    Ok((array_val, last_op))
+}
+
+/// Extract the raw allocation bytes for a bare array value, then recursively
+/// build the corresponding `MirConstructArrayOp`.
+fn translate_array_value_constant_inner(
+    ctx: &mut Context,
+    constant: &mir::ConstOperand,
+    array_ty: TypeHandle,
+    rust_array_ty: rustc_public::ty::Ty,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let bytes = constant_bytes(constant, "Array", loc.clone())?;
+
+    build_array_op_from_bytes(
+        ctx,
+        array_ty,
+        rust_array_ty,
+        &bytes,
+        block_ptr,
+        prev_op,
+        loc,
+    )
+}
+
+/// ## How it works
+///
+/// 1. Resolve the struct's own allocation (following by-ref provenance when the
+///    constant is a promoted `&Struct`)
+/// 2. Decode each field at its rustc layout offset from that allocation
+/// 3. Thin pointer fields that relocate to device statics become
+///    [`MirGlobalAllocOp`] results; other fields use the byte decoder
+/// 4. Create MirConstructStructOp with those operands
+///
+/// Each field is read at the byte offset rustc's layout records for it, so
+/// padding between fields and any reordering rustc applies are both accounted
+/// for. A field's size comes from the same layout, which is why a padded struct
+/// nested inside another is sliced at its true width rather than at the sum of
+/// its fields.
+///
+/// Aggregate **const** values with thin pointers to device statics are
+/// materialized per field; device-global initializers use a separate
+/// allocation-level relocation path instead of this value reconstruction.
+pub(super) fn translate_struct_constant(
+    ctx: &mut Context,
+    constant: &mir::ConstOperand,
+    rust_ty: &rustc_public::ty::Ty,
+    const_ty_ptr: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    // Confirm the MIR type is a struct before touching the allocation.
+    {
+        let ty_obj = const_ty_ptr.deref(ctx);
+        if ty_obj
+            .downcast_ref::<dialect_mir::types::MirStructType>()
+            .is_none()
+        {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported("translate_struct_constant called on non-struct type")
+            );
+        }
+    }
+
+    // The constant's Rust type decides how to read the allocation. A
+    // reference or raw pointer means stable_mir handed over a promoted
+    // constant indirectly (`&(8..16)`): the allocation is a thin pointer whose
+    // provenance names the allocation with the actual struct data, and the
+    // layout query must run on the pointee. An aggregate type means the
+    // allocation IS the struct's memory image. Deciding by "has provenance"
+    // conflated the two: a by-value struct with a pointer field would have had
+    // its own bytes silently replaced by the first pointee's.
+    let by_ref_pointee = match rust_ty.kind() {
+        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Ref(_, pointee, _))
+        | rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::RawPtr(pointee, _)) => {
+            Some(pointee)
+        }
+        _ => None,
+    };
+    let struct_rust_ty = by_ref_pointee.unwrap_or(*rust_ty);
+
+    let alloc = match constant.const_.kind() {
+        ConstantKind::Allocated(alloc) => {
+            if by_ref_pointee.is_some() {
+                use rustc_public::mir::alloc::GlobalAlloc;
+                let Some(&(prov_pos, prov)) = alloc.provenance.ptrs.first() else {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(
+                            "Reference-to-struct constant has no provenance to follow".to_string()
+                        )
+                    );
+                };
+                // The pointer's data bytes encode the byte offset into the
+                // target allocation. Field decoding below starts at byte zero
+                // of that target, so an interior reference must fail loudly.
+                let ptr_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+                let ref_offset = alloc
+                    .read_partial_uint(prov_pos..prov_pos + ptr_width)
+                    .map_err(|e| {
+                        input_error_noloc!(TranslationErr::unsupported(format!(
+                            "Failed to read struct constant provenance offset: {:?}",
+                            e
+                        )))
+                    })?;
+                if ref_offset != 0 {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "Reference-to-struct constant points at interior offset {ref_offset}; \
+                             cuda-oxide cannot yet decode interior references to constants"
+                        ))
+                    );
+                }
+                let alloc_id = prov.0;
+                match GlobalAlloc::from(alloc_id) {
+                    GlobalAlloc::Memory(target_alloc) => target_alloc,
+                    GlobalAlloc::Static(static_def) => {
+                        static_def.eval_initializer().map_err(|e| {
+                            input_error_noloc!(TranslationErr::unsupported(format!(
+                                "Failed to evaluate static initializer for struct constant: {:?}",
+                                e
+                            )))
+                        })?
+                    }
+                    other => {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "Struct constant provenance points to non-memory allocation: {:?}",
+                                other
+                            ))
+                        );
+                    }
+                }
+            } else {
+                // The allocation is the struct's own memory image (may contain
+                // thin-pointer relocations to device statics).
+                alloc.clone()
+            }
+        }
+        ConstantKind::ZeroSized => {
+            return translate_struct_constant_from_bytes(
+                ctx,
+                &struct_rust_ty,
+                const_ty_ptr,
+                &[],
+                block_ptr,
+                prev_op,
+                loc,
+            );
+        }
+        _ => {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Struct constant must be Allocated, got: {:?}. \
+                     Consider using inline construction: `let s = MyStruct {{ field: value }};`",
+                    constant.const_.kind()
+                ))
+            );
+        }
+    };
+
+    translate_struct_constant_from_alloc(
+        ctx,
+        &alloc,
+        0,
+        &struct_rust_ty,
+        const_ty_ptr,
+        block_ptr,
+        prev_op,
+        loc,
+    )
+}
+
+/// Byte image for a tuple constant, or `None` when a sized tuple has no
+/// backing allocation.
+///
+/// Undefined bytes in an allocation are padding; they are zeroed
+/// deterministically while the provenance map stays available separately for
+/// pointer-field reconstruction. `ConstantKind::ZeroSized`-style constants
+/// (e.g. `((), ())`) carry no allocation at all; a zero-byte layout is
+/// reproduced exactly by an empty image.
+fn tuple_constant_byte_image(
+    allocation: Option<&rustc_public::ty::Allocation>,
+    layout_size: usize,
+) -> Option<Vec<u8>> {
+    match allocation {
+        Some(allocation) => Some(
+            allocation
+                .bytes
+                .iter()
+                .map(|byte| byte.unwrap_or(0))
+                .collect(),
+        ),
+        None if layout_size == 0 => Some(Vec::new()),
+        None => None,
+    }
+}
+
+/// Translate a non-empty tuple constant from its own allocation image.
+///
+/// Unlike `constant_bytes`, this must not follow the first provenance entry:
+/// for a by-value tuple, that entry names one pointer field's target, while the
+/// allocation itself still contains the tuple's scalar fields and padding.
+/// Pointer fields consume their relocation entries through the
+/// allocation-aware decoder below.
+pub(super) fn translate_tuple_constant(
+    ctx: &mut Context,
+    constant: &mir::ConstOperand,
+    rust_ty: &rustc_public::ty::Ty,
+    const_ty_ptr: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let layout_size = rust_ty
+        .layout()
+        .map_err(|error| {
+            input_error!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Failed to query layout for tuple constant: {error:?}"
+                ))
+            )
+        })?
+        .shape()
+        .size
+        .bytes();
+
+    let Some(allocation) = constant_allocation(constant) else {
+        let bytes = tuple_constant_byte_image(None, layout_size).ok_or_else(|| {
+            input_error!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Tuple constant of {layout_size} byte(s) must be backed by an allocation, \
+                     found {:?}",
+                    constant.const_.kind()
+                ))
+            )
+        })?;
+        return translate_tuple_constant_from_bytes(
+            ctx,
+            rust_ty,
+            const_ty_ptr,
+            &bytes,
+            block_ptr,
+            prev_op,
+            loc,
+        );
+    };
+
+    translate_tuple_constant_from_alloc(
+        ctx,
+        allocation,
+        0,
+        rust_ty,
+        const_ty_ptr,
+        block_ptr,
+        prev_op,
+        loc,
+    )
+}
+
+/// Translate a tuple constant from bytes using rustc's field offsets.
+fn translate_tuple_constant_from_bytes(
+    ctx: &mut Context,
+    rust_ty: &rustc_public::ty::Ty,
+    const_ty_ptr: TypeHandle,
+    bytes: &[u8],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let (field_types, mir_field_offsets, mir_memory_order, mir_total_size, mir_abi_align) = {
+        let ty_ref = const_ty_ptr.deref(ctx);
+        let tuple_ty = ty_ref
+            .downcast_ref::<dialect_mir::types::MirTupleType>()
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(
+                    "translate_tuple_constant called on non-tuple type"
+                ))
+            })?;
+        (
+            tuple_ty.get_types().to_vec(),
+            tuple_ty.field_offsets().to_vec(),
+            tuple_ty.memory_order(),
+            tuple_ty.total_size(),
+            tuple_ty.abi_align(),
+        )
+    };
+
+    let rust_field_types = match rust_ty.kind() {
+        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Tuple(fields)) => {
+            fields.to_vec()
+        }
+        other => {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Tuple constant expected Rust tuple type, got {:?}",
+                    other
+                ))
+            );
+        }
+    };
+
+    if field_types.len() != rust_field_types.len() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Tuple constant type mismatch: MIR has {} fields, Rust type has {}",
+                field_types.len(),
+                rust_field_types.len()
+            ))
+        );
+    }
+
+    let layout = rust_ty.layout().map_err(|error| {
+        input_error!(
+            loc.clone(),
+            TranslationErr::unsupported(format!(
+                "Failed to query layout for tuple constant: {error:?}"
+            ))
+        )
+    })?;
+    let shape = layout.shape();
+    let tuple_size = shape.size.bytes();
+    if bytes.len() != tuple_size {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Tuple constant has {} bytes but rustc layout requires exactly {tuple_size}",
+                bytes.len()
+            ))
+        );
+    }
+
+    let field_offsets = match &shape.fields {
+        rustc_public::abi::FieldsShape::Primitive if field_types.is_empty() => vec![],
+        rustc_public::abi::FieldsShape::Arbitrary { offsets } => offsets
+            .iter()
+            .map(|offset| offset.bytes())
+            .collect::<Vec<_>>(),
+        fields => {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Tuple constant fields use unsupported layout shape {fields:?}"
+                ))
+            );
+        }
+    };
+    if field_offsets.len() != field_types.len() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Tuple constant layout has {} offsets for {} fields",
+                field_offsets.len(),
+                field_types.len()
+            ))
+        );
+    }
+    if !field_types.is_empty() {
+        let rust_field_offsets = field_offsets
+            .iter()
+            .map(|offset| *offset as u64)
+            .collect::<Vec<_>>();
+        let rust_memory_order = shape.fields.fields_by_offset_order();
+        if mir_field_offsets != rust_field_offsets
+            || mir_memory_order != rust_memory_order
+            || mir_total_size != tuple_size as u64
+            || mir_abi_align != shape.abi_align
+        {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Tuple constant layout disagrees between rustc and dialect-mir: rustc offsets/order/size/alignment {:?}/{:?}/{}/{}, dialect {:?}/{:?}/{}/{}",
+                    rust_field_offsets,
+                    rust_memory_order,
+                    tuple_size,
+                    shape.abi_align,
+                    mir_field_offsets,
+                    mir_memory_order,
+                    mir_total_size,
+                    mir_abi_align
+                ))
+            );
+        }
+    }
+
+    let mut values = Vec::with_capacity(field_types.len());
+    let mut current_prev_op = prev_op;
+
+    for (field_idx, (field_ty, rust_field_ty)) in field_types
+        .iter()
+        .copied()
+        .zip(rust_field_types.iter())
+        .enumerate()
+    {
+        let byte_offset = field_offsets[field_idx];
+        let byte_size = rust_type_layout_size(*rust_field_ty, loc.clone())?;
+
+        let field_end = byte_offset.checked_add(byte_size).ok_or_else(|| {
+            input_error!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Tuple constant field {field_idx} overflowed offset computation"
+                ))
+            )
+        })?;
+        let field_bytes = if byte_size == 0 {
+            &[][..]
+        } else if field_end <= bytes.len() {
+            &bytes[byte_offset..field_end]
+        } else {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Tuple constant has insufficient bytes for field {} (need {} bytes at offset {}, have {})",
+                    field_idx,
+                    byte_size,
+                    byte_offset,
+                    bytes.len()
+                ))
+            );
+        };
+
+        let (value, new_prev_op) = translate_constant_value_from_bytes(
+            ctx,
+            rust_field_ty,
+            field_ty,
+            field_bytes,
+            block_ptr,
+            current_prev_op,
+            loc.clone(),
+        )?;
+        values.push(value);
+        current_prev_op = new_prev_op;
+    }
+
+    use dialect_mir::ops::MirConstructTupleOp;
+    let op = Operation::new(
+        ctx,
+        MirConstructTupleOp::get_concrete_op_info(),
+        vec![const_ty_ptr],
+        values,
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc);
+
+    if let Some(prev) = current_prev_op {
+        op.insert_after(ctx, prev);
+    } else {
+        op.insert_at_front(block_ptr, ctx);
+    }
+
+    Ok((op.deref(ctx).get_result(0), Some(op)))
+}
+
+/// Storage size of a struct constant from its recorded layout, or `None` when
+/// that layout is missing.
+///
+/// rustc's size counts the padding between and after fields, so it is what a
+/// reader must stride by. Summing the field sizes would under-report any padded
+/// struct and hand a short byte slice to whoever reads it.
+///
+/// Recorded offsets are what separates a known layout from a failed query:
+/// `translator/types.rs` stores empty offsets and a zero size when `Ty::layout()`
+/// fails. A zero size on its own does not imply a failure, since a struct whose
+/// fields are all zero-sized is genuinely zero bytes wide. `is_zst_type` does not
+/// cover those, because it calls a struct zero-sized only when it has no fields
+/// at all, so a `PhantomData` newtype reaches here with one field and a size of
+/// zero.
+fn struct_storage_size(field_count: usize, offset_count: usize, total_size: u64) -> Option<usize> {
+    if offset_count == 0 && field_count > 0 {
+        None
+    } else {
+        Some(total_size as usize)
+    }
+}
+
+pub(super) fn constant_storage_size(ctx: &Context, ty_ptr: TypeHandle) -> Option<usize> {
+    let ty_ref = ty_ptr.deref(ctx);
+    if types::is_zst_type(ctx, ty_ptr) {
+        Some(0)
+    } else if let Some(int_ty) = ty_ref.downcast_ref::<IntegerType>() {
+        Some((int_ty.width() as usize).div_ceil(8))
+    } else if ty_ref.is::<MirFP16Type>() {
+        Some(2)
+    } else if ty_ref.is::<FP32Type>() {
+        Some(4)
+    } else if ty_ref.is::<FP64Type>() {
+        Some(8)
+    } else if ty_ref.is::<dialect_mir::types::MirPtrType>() {
+        Some(rustc_public::target::MachineInfo::target_pointer_width().bytes())
+    } else if let Some(st) = ty_ref.downcast_ref::<dialect_mir::types::MirStructType>() {
+        struct_storage_size(
+            st.field_types().len(),
+            st.field_offsets().len(),
+            st.total_size(),
+        )
+    } else if let Some(union_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirUnionType>() {
+        usize::try_from(union_ty.total_size()).ok()
+    } else if let Some(at) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
+        let elem = at.element_type();
+        let n = at.size() as usize;
+        Some(constant_storage_size(ctx, elem)? * n)
+    } else {
+        None
+    }
+}
+
+/// Whether a constant-storage type contains a pointer-bearing leaf.
+///
+/// Raw-byte constant materialization is only sound when this returns false.
+/// Provenance-aware aggregate paths use the same predicate to decide whether
+/// they need typed reconstruction instead.
+pub(super) fn constant_type_contains_pointer(ctx: &Context, ty: TypeHandle) -> bool {
+    let ty_ref = ty.deref(ctx);
+    if ty_ref.is::<dialect_mir::types::MirPtrType>()
+        || ty_ref.is::<dialect_mir::types::MirSliceType>()
+        || ty_ref.is::<dialect_mir::types::MirDisjointSliceType>()
+    {
+        return true;
+    }
+    if let Some(array) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
+        let element = array.element_type();
+        drop(ty_ref);
+        return constant_type_contains_pointer(ctx, element);
+    }
+    let children: Vec<TypeHandle> =
+        if let Some(tuple) = ty_ref.downcast_ref::<dialect_mir::types::MirTupleType>() {
+            tuple.get_types().to_vec()
+        } else if let Some(structure) = ty_ref.downcast_ref::<dialect_mir::types::MirStructType>() {
+            structure.field_types().to_vec()
+        } else if let Some(enumeration) = ty_ref.downcast_ref::<dialect_mir::types::MirEnumType>() {
+            enumeration.all_field_types.clone()
+        } else if let Some(union_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirUnionType>() {
+            union_ty.field_types().to_vec()
+        } else {
+            return false;
+        };
+    drop(ty_ref);
+    children
+        .into_iter()
+        .any(|child| constant_type_contains_pointer(ctx, child))
+}
+
+/// Translate a struct value from raw bytes plus the Rust type/layout metadata.
+///
+/// This is the byte-slice counterpart to [`translate_struct_constant`] and is
+/// used whenever a constant field has a struct type (e.g. `NonZero<T>` wrappers
+/// inside enum payloads). Each field is parsed recursively so nested newtypes
+/// are handled automatically.
+fn translate_struct_constant_from_bytes(
+    ctx: &mut Context,
+    rust_ty: &rustc_public::ty::Ty,
+    const_ty_ptr: TypeHandle,
+    struct_bytes: &[u8],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    use rustc_public::ty::{RigidTy, TyKind};
+
+    let field_types: Vec<TypeHandle> = {
+        let ty_obj = const_ty_ptr.deref(ctx);
+        let struct_ty = ty_obj
+            .downcast_ref::<dialect_mir::types::MirStructType>()
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(
+                    "translate_struct_constant_from_bytes called on non-struct type"
+                ))
+            })?;
+        struct_ty.field_types().to_vec()
+    };
+
+    let layout = rust_ty.layout().map_err(|e| {
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "Failed to query layout for struct constant: {:?}",
+            e
+        )))
+    })?;
+    let shape = layout.shape();
+
+    // A zero-sized struct span holds no bytes and cannot carry relocations,
+    // and not every type that lands here as a MirStructType is an ADT:
+    // function items and non-capturing closures have no ADT metadata to
+    // consult. Synthesize such values from the dialect type alone.
+    if shape.size.bytes() == 0 {
+        return translate_zero_sized_constant_value(ctx, const_ty_ptr, block_ptr, prev_op, loc);
+    }
+
+    let field_offsets: Vec<usize> = match &shape.fields {
+        rustc_public::abi::FieldsShape::Arbitrary { offsets } => {
+            offsets.iter().map(|offset| offset.bytes()).collect()
+        }
+        rustc_public::abi::FieldsShape::Primitive => vec![0; field_types.len()],
+        rustc_public::abi::FieldsShape::Union { .. } => vec![0; field_types.len()],
+        other => {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Struct constant fields use unsupported shape {:?}",
+                    other
+                ))
+            );
+        }
+    };
+
+    let (adt_def, substs) = match rust_ty.kind() {
+        TyKind::RigidTy(RigidTy::Adt(adt_def, substs)) => (adt_def, substs),
+        other => {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Expected ADT Rust type for struct constant, got {:?}",
+                    other
+                ))
+            );
+        }
+    };
+
+    // Structs have a single variant in the ADT metadata.
+    let variants = adt_def.variants();
+    let struct_variant = variants.first().ok_or_else(|| {
+        input_error_noloc!(TranslationErr::unsupported(
+            "Struct ADT has no variants in metadata"
+        ))
+    })?;
+
+    let mut field_values = Vec::with_capacity(field_types.len());
+    let mut current_prev_op = prev_op;
+
+    for (field_idx, field_ty_ptr) in field_types.iter().copied().enumerate() {
+        let fields = struct_variant.fields();
+        let rust_field = fields.get(field_idx).ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Struct constant field {} is missing in rustc ADT metadata ({} field(s) recorded)",
+                field_idx,
+                fields.len()
+            )))
+        })?;
+        let rust_field_ty = rust_field.ty_with_args(&substs);
+        let field_layout = rust_field_ty.layout().map_err(|e| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Failed to query layout for struct field {}: {:?}",
+                field_idx, e
+            )))
+        })?;
+        let field_size = field_layout.shape().size.bytes();
+        let field_offset = *field_offsets.get(field_idx).ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Missing layout offset for struct field {}",
+                field_idx
+            )))
+        })?;
+
+        if field_size == 0 {
+            let (zst_val, new_prev_op) = translate_zero_sized_constant_value(
+                ctx,
+                field_ty_ptr,
+                block_ptr,
+                current_prev_op,
+                loc.clone(),
+            )?;
+            field_values.push(zst_val);
+            current_prev_op = new_prev_op;
+            continue;
+        }
+
+        let field_end = field_offset.checked_add(field_size).ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Struct field {} offset {} + size {} overflowed",
+                field_idx, field_offset, field_size
+            )))
+        })?;
+        if field_end > struct_bytes.len() {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "Struct constant has {} bytes, but field {} needs [{}..{})",
+                    struct_bytes.len(),
+                    field_idx,
+                    field_offset,
+                    field_end
+                ))
+            );
+        }
+
+        let field_bytes = &struct_bytes[field_offset..field_end];
+        let (field_val, new_prev_op) = translate_constant_value_from_bytes(
+            ctx,
+            &rust_field_ty,
+            field_ty_ptr,
+            field_bytes,
+            block_ptr,
+            current_prev_op,
+            loc.clone(),
+        )?;
+        field_values.push(field_val);
+        current_prev_op = new_prev_op;
+    }
+
+    let (casted_field_values, prev_after_casts) = cast_struct_fields_to_expected_types(
+        ctx,
+        field_values,
+        const_ty_ptr,
+        block_ptr,
+        current_prev_op,
+        loc.clone(),
+    );
+
+    let op = Operation::new(
+        ctx,
+        MirConstructStructOp::get_concrete_op_info(),
+        vec![const_ty_ptr],
+        casted_field_values,
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc.clone());
+
+    if let Some(prev) = prev_after_casts {
+        op.insert_after(ctx, prev);
+    } else {
+        op.insert_at_front(block_ptr, ctx);
+    }
+
+    Ok((op.deref(ctx).get_result(0), Some(op)))
+}
+
+/// Translate one field-sized byte slice into a constant value.
+pub(super) fn translate_constant_value_from_bytes(
+    ctx: &mut Context,
+    rust_ty: &rustc_public::ty::Ty,
+    ty_ptr: TypeHandle,
+    bytes: &[u8],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let is_enum = {
+        let ty_ref = ty_ptr.deref(ctx);
+        ty_ref.is::<dialect_mir::types::MirEnumType>()
+    };
+    if is_enum {
+        return translate_enum_constant_from_bytes(
+            ctx, rust_ty, ty_ptr, bytes, block_ptr, prev_op, loc,
+        );
+    }
+
+    // Aggregate decoders own their complete field model, including non-empty
+    // aggregates whose every field is zero-sized. Dispatch them before the
+    // generic ZST synthesizer, which only has the translated type and cannot
+    // recover a Rust aggregate's active variant or field metadata.
+    if ty_ptr.deref(ctx).is::<dialect_mir::types::MirTupleType>() {
+        return translate_tuple_constant_from_bytes(
+            ctx, rust_ty, ty_ptr, bytes, block_ptr, prev_op, loc,
+        );
+    }
+
+    // Struct-typed constants (e.g. `NonZero<T>` wrappers inside enum payloads)
+    // need per-field construction rather than a single scalar constant.
+    let is_struct = {
+        let ty_ref = ty_ptr.deref(ctx);
+        ty_ref.is::<dialect_mir::types::MirStructType>()
+    };
+    if is_struct {
+        return translate_struct_constant_from_bytes(
+            ctx, rust_ty, ty_ptr, bytes, block_ptr, prev_op, loc,
+        );
+    }
+
+    let is_zst = rust_ty
+        .layout()
+        .map(|layout| layout.shape().is_1zst())
+        .map_err(|error| {
+            input_error!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Failed to query layout for aggregate constant field {rust_ty:?}: {error:?}"
+                ))
+            )
+        })?;
+    if is_zst || types::is_zst_type(ctx, ty_ptr) {
+        return translate_zero_sized_constant_value(ctx, ty_ptr, block_ptr, prev_op, loc);
+    }
+
+    if ty_ptr.deref(ctx).is::<dialect_mir::types::MirUnionType>() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(
+                "Initialized union constants require their rustc allocation so the initialization mask is preserved; byte-only union decoding is not supported"
+                    .to_string()
+            )
+        );
+    }
+
+    enum ValueKind {
+        Integer { width: u32, signedness: Signedness },
+        Float16,
+        Float32,
+        Float64,
+        Pointer,
+        Unsupported(String),
+    }
+
+    let value_kind = {
+        let ty_ref = ty_ptr.deref(ctx);
+        if let Some(int_ty) = ty_ref.downcast_ref::<IntegerType>() {
+            ValueKind::Integer {
+                width: int_ty.width(),
+                signedness: int_ty.signedness(),
+            }
+        } else if ty_ref.is::<MirFP16Type>() {
+            ValueKind::Float16
+        } else if ty_ref.is::<FP32Type>() {
+            ValueKind::Float32
+        } else if ty_ref.is::<FP64Type>() {
+            ValueKind::Float64
+        } else if ty_ref.is::<dialect_mir::types::MirPtrType>() {
+            ValueKind::Pointer
+        } else {
+            ValueKind::Unsupported(format!("{:?}", ty_ref))
+        }
+    };
+
+    match value_kind {
+        ValueKind::Integer { width, signedness } => {
+            let byte_size = (width as usize).div_ceil(8);
+            if bytes.len() < byte_size {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Integer constant needs {} bytes, found {}",
+                        byte_size,
+                        bytes.len()
+                    ))
+                );
+            }
+
+            let int_val = read_uint_from_bytes(&bytes[..byte_size]);
+            let width_nz = NonZeroUsize::new(width as usize).unwrap();
+            let apint = APInt::from_u128(int_val, width_nz);
+            let int_attr = pliron::builtin::attributes::IntegerAttr::new(
+                IntegerType::get(ctx, width, signedness),
+                apint,
+            );
+
+            use dialect_mir::ops::MirConstantOp;
+            let op = Operation::new(
+                ctx,
+                MirConstantOp::get_concrete_op_info(),
+                vec![ty_ptr],
+                vec![],
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc.clone());
+            let const_op = MirConstantOp::new(op);
+            const_op.set_attr_value(ctx, int_attr);
+
+            if let Some(prev) = prev_op {
+                const_op.get_operation().insert_after(ctx, prev);
+            } else {
+                const_op.get_operation().insert_at_front(block_ptr, ctx);
+            }
+
+            Ok((
+                const_op.get_operation().deref(ctx).get_result(0),
+                Some(const_op.get_operation()),
+            ))
+        }
+        ValueKind::Float16 => {
+            if bytes.len() < 2 {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "f16 constant needs 2 bytes, found {}",
+                        bytes.len()
+                    ))
+                );
+            }
+
+            let bits = read_uint_from_bytes(&bytes[..2]) as u16;
+            let float_attr = MirFP16Attr::from_bits(bits);
+
+            use dialect_mir::ops::MirFloatConstantOp;
+            let op = Operation::new(
+                ctx,
+                MirFloatConstantOp::get_concrete_op_info(),
+                vec![ty_ptr],
+                vec![],
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc.clone());
+            let float_op = MirFloatConstantOp::new(op);
+            float_op.set_attr_float_value_f16(ctx, float_attr);
+
+            if let Some(prev) = prev_op {
+                float_op.get_operation().insert_after(ctx, prev);
+            } else {
+                float_op.get_operation().insert_at_front(block_ptr, ctx);
+            }
+
+            Ok((
+                float_op.get_operation().deref(ctx).get_result(0),
+                Some(float_op.get_operation()),
+            ))
+        }
+        ValueKind::Float32 => {
+            if bytes.len() < 4 {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "f32 constant needs 4 bytes, found {}",
+                        bytes.len()
+                    ))
+                );
+            }
+
+            let mut field_bytes = [0u8; 4];
+            field_bytes.copy_from_slice(&bytes[..4]);
+            let float_val = match rustc_public::target::MachineInfo::target_endianness() {
+                rustc_public::target::Endian::Little => f32::from_le_bytes(field_bytes),
+                rustc_public::target::Endian::Big => f32::from_be_bytes(field_bytes),
+            };
+            let float_attr = pliron::builtin::attributes::FPSingleAttr::from(float_val);
+
+            use dialect_mir::ops::MirFloatConstantOp;
+            let op = Operation::new(
+                ctx,
+                MirFloatConstantOp::get_concrete_op_info(),
+                vec![ty_ptr],
+                vec![],
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc.clone());
+            let float_op = MirFloatConstantOp::new(op);
+            float_op.set_attr_float_value(ctx, float_attr);
+
+            if let Some(prev) = prev_op {
+                float_op.get_operation().insert_after(ctx, prev);
+            } else {
+                float_op.get_operation().insert_at_front(block_ptr, ctx);
+            }
+
+            Ok((
+                float_op.get_operation().deref(ctx).get_result(0),
+                Some(float_op.get_operation()),
+            ))
+        }
+        ValueKind::Float64 => {
+            if bytes.len() < 8 {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "f64 constant needs 8 bytes, found {}",
+                        bytes.len()
+                    ))
+                );
+            }
+
+            let mut field_bytes = [0u8; 8];
+            field_bytes.copy_from_slice(&bytes[..8]);
+            let float_val = match rustc_public::target::MachineInfo::target_endianness() {
+                rustc_public::target::Endian::Little => f64::from_le_bytes(field_bytes),
+                rustc_public::target::Endian::Big => f64::from_be_bytes(field_bytes),
+            };
+            let float_attr = pliron::builtin::attributes::FPDoubleAttr::from(float_val);
+
+            use dialect_mir::ops::MirFloatConstantOp;
+            let op = Operation::new(
+                ctx,
+                MirFloatConstantOp::get_concrete_op_info(),
+                vec![ty_ptr],
+                vec![],
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc.clone());
+            let float_op = MirFloatConstantOp::new(op);
+            float_op.set_attr_float_value_f64(ctx, float_attr);
+
+            if let Some(prev) = prev_op {
+                float_op.get_operation().insert_after(ctx, prev);
+            } else {
+                float_op.get_operation().insert_at_front(block_ptr, ctx);
+            }
+
+            Ok((
+                float_op.get_operation().deref(ctx).get_result(0),
+                Some(float_op.get_operation()),
+            ))
+        }
+        ValueKind::Pointer => {
+            let pointer_bytes = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+            if bytes.len() < pointer_bytes {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Pointer constant needs {} bytes, found {}",
+                        pointer_bytes,
+                        bytes.len()
+                    ))
+                );
+            }
+
+            let ptr_val = read_uint_from_bytes(&bytes[..pointer_bytes]) as u64;
+            let i64_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);
+            let apint = APInt::from_u64(ptr_val, NonZeroUsize::new(64).unwrap());
+            let int_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, apint);
+
+            use dialect_mir::ops::MirConstantOp;
+            let int_op = Operation::new(
+                ctx,
+                MirConstantOp::get_concrete_op_info(),
+                vec![i64_ty.into()],
+                vec![],
+                vec![],
+                0,
+            );
+            int_op.deref_mut(ctx).set_loc(loc.clone());
+            let const_op = MirConstantOp::new(int_op);
+            const_op.set_attr_value(ctx, int_attr);
+
+            if let Some(prev) = prev_op {
+                const_op.get_operation().insert_after(ctx, prev);
+            } else {
+                const_op.get_operation().insert_at_front(block_ptr, ctx);
+            }
+
+            let const_value = const_op.get_operation().deref(ctx).get_result(0);
+            let cast_op = Operation::new(
+                ctx,
+                MirCastOp::get_concrete_op_info(),
+                vec![ty_ptr],
+                vec![const_value],
+                vec![],
+                0,
+            );
+            cast_op.deref_mut(ctx).set_loc(loc.clone());
+            let cast = MirCastOp::new(cast_op);
+            cast.set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
+            if dialect_mir::types::type_contains_concrete_pointer_kind(ctx, ty_ptr) {
+                cast.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::StaticAddress);
+            }
+            cast_op.insert_after(ctx, const_op.get_operation());
+
+            Ok((cast_op.deref(ctx).get_result(0), Some(cast_op)))
+        }
+        ValueKind::Unsupported(ty_name) => input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Aggregate constant field type is not yet supported: {}",
+                ty_name
+            ))
+        ),
+    }
+}
+
+/// Build a zero-sized value while preserving its exact translated type.
+pub(super) fn translate_zero_sized_constant_value(
+    ctx: &mut Context,
+    ty_ptr: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    enum ZeroSizedKind {
+        Struct,
+        EmptyTuple,
+        Union,
+        Unsupported(String),
+    }
+
+    let zero_sized_kind = {
+        let ty_ref = ty_ptr.deref(ctx);
+        if ty_ref.is::<dialect_mir::types::MirStructType>() {
+            ZeroSizedKind::Struct
+        } else if ty_ref.is::<dialect_mir::types::MirUnionType>() {
+            ZeroSizedKind::Union
+        } else if let Some(tuple_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirTupleType>() {
+            if tuple_ty.get_types().is_empty() {
+                ZeroSizedKind::EmptyTuple
+            } else {
+                ZeroSizedKind::Unsupported(
+                    "Only empty tuple constants can be synthesized as zero-sized values"
+                        .to_string(),
+                )
+            }
+        } else {
+            ZeroSizedKind::Unsupported(format!(
+                "Zero-sized constant synthesis does not support type {:?}",
+                ty_ref
+            ))
+        }
+    };
+
+    // A zero-sized struct can still carry (zero-sized) fields in its type, and
+    // `MirConstructStructOp` requires one operand per field. Recursively
+    // synthesize a ZST value for each field type (e.g. `TryFromIntError(())`,
+    // which surfaces when building `core` for nvptx via `-Zbuild-std`).
+    if matches!(zero_sized_kind, ZeroSizedKind::Struct) {
+        let field_types: Vec<TypeHandle> = {
+            let ty_ref = ty_ptr.deref(ctx);
+            ty_ref
+                .downcast_ref::<dialect_mir::types::MirStructType>()
+                .map(|st| st.field_types.clone())
+                .unwrap_or_default()
+        };
+        let mut operands = Vec::with_capacity(field_types.len());
+        let mut cur_prev = prev_op;
+        for fty in field_types {
+            let (v, np) =
+                translate_zero_sized_constant_value(ctx, fty, block_ptr, cur_prev, loc.clone())?;
+            operands.push(v);
+            cur_prev = np;
+        }
+        let op = Operation::new(
+            ctx,
+            MirConstructStructOp::get_concrete_op_info(),
+            vec![ty_ptr],
+            operands,
+            vec![],
+            0,
+        );
+        op.deref_mut(ctx).set_loc(loc);
+        if let Some(prev) = cur_prev {
+            op.insert_after(ctx, prev);
+        } else {
+            op.insert_at_front(block_ptr, ctx);
+        }
+        return Ok((op.deref(ctx).get_result(0), Some(op)));
+    }
+
+    let op = match zero_sized_kind {
+        ZeroSizedKind::Struct => unreachable!("handled above"),
+        ZeroSizedKind::EmptyTuple => {
+            use dialect_mir::ops::MirConstructTupleOp;
+            Operation::new(
+                ctx,
+                MirConstructTupleOp::get_concrete_op_info(),
+                vec![ty_ptr],
+                vec![],
+                vec![],
+                0,
+            )
+        }
+        ZeroSizedKind::Union => MirUndefOp::new(ctx, ty_ptr).get_operation(),
+        ZeroSizedKind::Unsupported(message) => {
+            return input_err!(loc, TranslationErr::unsupported(message));
+        }
+    };
+    op.deref_mut(ctx).set_loc(loc);
+
+    if let Some(prev) = prev_op {
+        op.insert_after(ctx, prev);
+    } else {
+        op.insert_at_front(block_ptr, ctx);
+    }
+
+    Ok((op.deref(ctx).get_result(0), Some(op)))
+}
+
+/// Fetch the raw bytes backing a constant, following provenance for promoted
+/// aggregate constants when necessary.
+pub(crate) fn constant_bytes(
+    constant: &mir::ConstOperand,
+    kind_name: &str,
+    loc: Location,
+) -> TranslationResult<Vec<u8>> {
+    use rustc_public::ty::TyConstKind;
+
+    fn allocation_bytes_zeroing_uninit(alloc: &rustc_public::ty::Allocation) -> Vec<u8> {
+        alloc.raw_bytes().ok().unwrap_or_else(|| {
+            alloc
+                .bytes
+                .iter()
+                .map(|opt: &Option<u8>| opt.unwrap_or(0))
+                .collect::<Vec<u8>>()
+        })
+    }
+
+    fn allocation_bytes(
+        alloc: &rustc_public::ty::Allocation,
+        kind_name: &str,
+        loc: Location,
+    ) -> TranslationResult<Vec<u8>> {
+        use rustc_public::mir::alloc::GlobalAlloc;
+
+        if let Some((_, prov)) = alloc.provenance.ptrs.first() {
+            let alloc_id = prov.0;
+            match GlobalAlloc::from(alloc_id) {
+                GlobalAlloc::Memory(target_alloc) => {
+                    Ok(allocation_bytes_zeroing_uninit(&target_alloc))
+                }
+                GlobalAlloc::Static(static_def) => {
+                    let target_alloc = static_def.eval_initializer().map_err(|e| {
+                        input_error_noloc!(TranslationErr::unsupported(format!(
+                            "Failed to evaluate static initializer for {} constant: {:?}",
+                            kind_name, e
+                        )))
+                    })?;
+                    Ok(allocation_bytes_zeroing_uninit(&target_alloc))
+                }
+                other => input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "{} constant provenance points to non-memory allocation: {:?}",
+                        kind_name, other
+                    ))
+                ),
+            }
+        } else {
+            Ok(allocation_bytes_zeroing_uninit(alloc))
+        }
+    }
+
+    match constant.const_.kind() {
+        ConstantKind::Allocated(alloc) => allocation_bytes(alloc, kind_name, loc),
+        ConstantKind::Ty(ty_const) => match ty_const.kind() {
+            TyConstKind::Value(_, alloc) => allocation_bytes(alloc, kind_name, loc),
+            TyConstKind::ZSTValue(_) => Ok(vec![]),
+            other => input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "{} constant must be backed by bytes, found TyConstKind::{:?}",
+                    kind_name, other
+                ))
+            ),
+        },
+        ConstantKind::ZeroSized => Ok(vec![]),
+        other => input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "{} constant must be Allocated or Ty::Value, got {:?}",
+                kind_name, other
+            ))
+        ),
+    }
+}
+
+#[cfg(test)]
+mod tuple_constant_byte_image_tests {
+    use super::tuple_constant_byte_image;
+    use rustc_public::mir::Mutability;
+    use rustc_public::ty::{Allocation, ProvenanceMap};
+
+    #[test]
+    fn zst_tuple_constant_without_allocation_is_an_empty_image() {
+        // `ConstantKind::ZeroSized`-style tuple constants such as `((), ())`
+        // carry no allocation; a zero-byte layout translates as empty bytes.
+        assert_eq!(tuple_constant_byte_image(None, 0), Some(Vec::new()));
+    }
+
+    #[test]
+    fn sized_tuple_constant_without_allocation_is_rejected() {
+        assert_eq!(tuple_constant_byte_image(None, 16), None);
+    }
+
+    #[test]
+    fn allocation_padding_bytes_are_zeroed_deterministically() {
+        let allocation = Allocation {
+            bytes: vec![Some(0xAB), None, None, Some(0xCD)],
+            provenance: ProvenanceMap { ptrs: Vec::new() },
+            align: 4,
+            mutability: Mutability::Not,
+        };
+        assert_eq!(
+            tuple_constant_byte_image(Some(&allocation), 4),
+            Some(vec![0xAB, 0, 0, 0xCD])
+        );
+    }
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production code mints via facts::PointerOrigin.
+#[allow(clippy::disallowed_methods)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn struct_storage_size_reads_layout_presence_not_size() {
+        // Ordinary padded struct: size is the padded width, not the field sum.
+        assert_eq!(struct_storage_size(2, 2, 16), Some(16));
+
+        // A struct with fields that is genuinely zero-sized, such as a
+        // `PhantomData` newtype. rustc recorded an offset for the field, so the
+        // size of zero is the answer rather than a missing one.
+        assert_eq!(struct_storage_size(1, 1, 0), Some(0));
+
+        // Field-less struct. `is_zst_type` takes these before the struct arm is
+        // reached, but the predicate agrees with it.
+        assert_eq!(struct_storage_size(0, 0, 0), Some(0));
+
+        // `Ty::layout()` failed when the type was imported, which
+        // `translator/types.rs` records as no offsets and a zero size.
+        assert_eq!(struct_storage_size(2, 0, 0), None);
+
+        // Same failure on a type whose size was recorded before the query failed.
+        assert_eq!(struct_storage_size(1, 0, 8), None);
+    }
+}
diff --git a/crates/mir-importer/src/translator/rvalue/const_enum.rs b/crates/mir-importer/src/translator/rvalue/const_enum.rs
new file mode 100644
index 0000000000..8ccc21c796
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/const_enum.rs
@@ -0,0 +1,650 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Enum constant and niche decoding.
+
+use super::coerce::cast_enum_fields_to_expected_types;
+use super::const_alloc::{
+    alloc_slice_bytes_zeroing_uninit, audit_aggregate_relocations,
+    relocation_offsets_overlapping_range, translate_constant_value_from_alloc,
+};
+use super::const_bytes::{rust_type_layout_size, translate_constant_value_from_bytes};
+use super::promoted::constant_allocation;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::layout::{enum_tag_offset, enum_variant_field_offsets};
+use dialect_mir::ops::MirConstructEnumOp;
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::TypeHandle;
+use pliron::value::Value;
+use pliron::{input_err, input_error, input_error_noloc};
+use rustc_public::mir;
+use rustc_public_bridge::IndexedVal;
+
+/// Translate an enum constant by reconstructing both its active variant and any
+/// payload operands from the constant's allocation.
+///
+/// Pointer-bearing enums must retain the outer allocation: the bytes stored in a
+/// rustc relocation slot are only an addend, while the provenance map identifies
+/// the target allocation. Following the first relocation here would replace the
+/// enum's storage image with its pointee and lose both the tag and other fields.
+pub(super) fn translate_enum_constant(
+    ctx: &mut Context,
+    constant: &mir::ConstOperand,
+    rust_ty: &rustc_public::ty::Ty,
+    const_ty_ptr: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    if let Some(allocation) = constant_allocation(constant) {
+        return translate_enum_constant_from_alloc(
+            ctx,
+            allocation,
+            0,
+            rust_ty,
+            const_ty_ptr,
+            block_ptr,
+            prev_op,
+            loc,
+        );
+    }
+
+    let enum_size = rust_type_layout_size(*rust_ty, loc.clone())?;
+    if enum_size != 0 {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Enum constant of {enum_size} byte(s) must be backed by an allocation, found {:?}",
+                constant.const_.kind()
+            ))
+        );
+    }
+
+    translate_enum_constant_from_bytes(ctx, rust_ty, const_ty_ptr, &[], block_ptr, prev_op, loc)
+}
+
+/// Translate an enum constant while retaining rustc's provenance map.
+pub(super) fn translate_enum_constant_from_alloc(
+    ctx: &mut Context,
+    alloc: &rustc_public::ty::Allocation,
+    base_offset: usize,
+    rust_ty: &rustc_public::ty::Ty,
+    const_ty_ptr: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let enum_size = rust_type_layout_size(*rust_ty, loc.clone())?;
+    let enum_bytes =
+        alloc_slice_bytes_zeroing_uninit(alloc, base_offset, enum_size, "Enum constant", &loc)?;
+
+    translate_enum_constant_from_storage(
+        ctx,
+        rust_ty,
+        const_ty_ptr,
+        &enum_bytes,
+        Some((alloc, base_offset)),
+        block_ptr,
+        prev_op,
+        loc,
+    )
+}
+
+/// Translate an enum value from raw bytes plus the Rust type/layout metadata.
+pub(super) fn translate_enum_constant_from_bytes(
+    ctx: &mut Context,
+    rust_ty: &rustc_public::ty::Ty,
+    const_ty_ptr: TypeHandle,
+    enum_bytes: &[u8],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    translate_enum_constant_from_storage(
+        ctx,
+        rust_ty,
+        const_ty_ptr,
+        enum_bytes,
+        None,
+        block_ptr,
+        prev_op,
+        loc,
+    )
+}
+
+/// Shared enum decoder. When `allocation` is present, direct thin-pointer
+/// fields are reconstructed from rustc relocations and niche selection can
+/// distinguish a relocated pointer from the all-zero placeholder bytes.
+#[allow(clippy::too_many_arguments)]
+fn translate_enum_constant_from_storage(
+    ctx: &mut Context,
+    rust_ty: &rustc_public::ty::Ty,
+    const_ty_ptr: TypeHandle,
+    enum_bytes: &[u8],
+    allocation: Option<(&rustc_public::ty::Allocation, usize)>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let enum_variant = {
+        let ty_obj = const_ty_ptr.deref(ctx);
+        let enum_ty = ty_obj
+            .downcast_ref::<dialect_mir::types::MirEnumType>()
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(
+                    "translate_enum_constant_from_storage called on non-enum type"
+                ))
+            })?;
+
+        let variant_index = match allocation {
+            Some((alloc, base_offset)) => {
+                enum_variant_index_from_alloc(rust_ty, enum_bytes, alloc, base_offset, loc.clone())?
+            }
+            None => enum_variant_index_from_bytes(rust_ty, enum_bytes, loc.clone())?,
+        };
+        let variant = enum_ty.get_variant(variant_index).ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Enum constant resolved to variant index {} outside translated MIR enum '{}'",
+                variant_index,
+                enum_ty.name()
+            )))
+        })?;
+        (variant_index, variant)
+    };
+    let variant_index = enum_variant.0;
+    let variant = enum_variant.1;
+
+    let mut field_values = Vec::with_capacity(variant.field_types.len());
+    let mut field_ranges = Vec::with_capacity(variant.field_types.len());
+    let mut current_prev_op = prev_op;
+
+    if !variant.field_types.is_empty() {
+        use rustc_public::ty::{RigidTy, TyKind};
+
+        let layout = rust_ty.layout().map_err(|e| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Failed to query layout for enum constant: {:?}",
+                e
+            )))
+        })?;
+        let field_offsets =
+            enum_variant_field_offsets(&layout.shape(), variant_index, loc.clone())?;
+
+        let (adt_def, substs) = match rust_ty.kind() {
+            TyKind::RigidTy(RigidTy::Adt(adt_def, substs)) => (adt_def, substs),
+            other => {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Expected ADT Rust type for enum constant, got {:?}",
+                        other
+                    ))
+                );
+            }
+        };
+        let rust_variant = &adt_def.variants()[variant_index];
+
+        for (field_idx, field_ty_ptr) in variant.field_types.iter().copied().enumerate() {
+            let rust_field_ty = rust_variant.fields()[field_idx].ty_with_args(&substs);
+            let field_layout = rust_field_ty.layout().map_err(|e| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Failed to query layout for enum field {} of variant '{}': {:?}",
+                    field_idx,
+                    rust_variant.name(),
+                    e
+                )))
+            })?;
+            let field_offset = *field_offsets.get(field_idx).ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Missing layout offset for enum field {} of variant '{}'",
+                    field_idx,
+                    rust_variant.name()
+                )))
+            })?;
+            let field_size = field_layout.shape().size.bytes() as usize;
+            let field_end = field_offset.checked_add(field_size).ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Enum field {} of variant '{}' overflowed offset computation",
+                    field_idx,
+                    rust_variant.name()
+                )))
+            })?;
+
+            if field_end > enum_bytes.len() {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Enum constant for variant '{}' has {} bytes, but field {} needs [{}..{})",
+                        rust_variant.name(),
+                        enum_bytes.len(),
+                        field_idx,
+                        field_offset,
+                        field_end
+                    ))
+                );
+            }
+
+            let (field_val, new_prev_op) = match allocation {
+                Some((alloc, base_offset)) => {
+                    let absolute_field_offset =
+                        base_offset.checked_add(field_offset).ok_or_else(|| {
+                            input_error_noloc!(TranslationErr::unsupported(format!(
+                                "Enum field {} of variant '{}' overflowed absolute offset computation",
+                                field_idx,
+                                rust_variant.name()
+                            )))
+                        })?;
+                    field_ranges.push((absolute_field_offset, field_size));
+                    translate_constant_value_from_alloc(
+                        ctx,
+                        alloc,
+                        absolute_field_offset,
+                        &rust_field_ty,
+                        field_ty_ptr,
+                        block_ptr,
+                        current_prev_op,
+                        loc.clone(),
+                    )?
+                }
+                None => {
+                    let field_bytes = &enum_bytes[field_offset..field_end];
+                    translate_constant_value_from_bytes(
+                        ctx,
+                        &rust_field_ty,
+                        field_ty_ptr,
+                        field_bytes,
+                        block_ptr,
+                        current_prev_op,
+                        loc.clone(),
+                    )?
+                }
+            };
+            field_values.push(field_val);
+            current_prev_op = new_prev_op;
+        }
+
+        let (casted_field_values, prev_after_casts) = cast_enum_fields_to_expected_types(
+            ctx,
+            field_values,
+            const_ty_ptr,
+            variant_index,
+            block_ptr,
+            current_prev_op,
+            loc.clone(),
+        );
+        field_values = casted_field_values;
+        current_prev_op = prev_after_casts;
+    }
+
+    if let Some((alloc, base_offset)) = allocation {
+        let enum_size = rust_type_layout_size(*rust_ty, loc.clone())?;
+        audit_aggregate_relocations(alloc, base_offset, enum_size, &field_ranges, "Enum", &loc)?;
+    }
+
+    let op = Operation::new(
+        ctx,
+        MirConstructEnumOp::get_concrete_op_info(),
+        vec![const_ty_ptr],
+        field_values,
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc.clone());
+
+    let enum_op = MirConstructEnumOp::new(op);
+    enum_op.set_attr_construct_enum_variant_index(
+        ctx,
+        dialect_mir::attributes::VariantIndexAttr(variant_index as u32),
+    );
+
+    if let Some(prev) = current_prev_op {
+        enum_op.get_operation().insert_after(ctx, prev);
+    } else {
+        enum_op.get_operation().insert_at_front(block_ptr, ctx);
+    }
+
+    let val = enum_op.get_operation().deref(ctx).get_result(0);
+
+    Ok((val, Some(enum_op.get_operation())))
+}
+
+/// Determine the active enum variant from layout metadata plus raw bytes.
+fn decode_niche_variant_index(
+    tag_value: u128,
+    carrier_mask: u128,
+    niche_start: u128,
+    niche_variant_start: usize,
+    niche_variant_end: usize,
+    untagged_variant: usize,
+) -> usize {
+    let relative = tag_value.wrapping_sub(niche_start) & carrier_mask;
+    let span = (niche_variant_end - niche_variant_start) as u128;
+
+    // Compare at the full physical carrier width. Converting `relative` to
+    // host usize before this check can turn 2^64 into zero on a 64-bit host
+    // and select the wrong variant for an i128 carrier.
+    if relative <= span {
+        niche_variant_start + relative as usize
+    } else {
+        untagged_variant
+    }
+}
+
+fn enum_variant_index_from_bytes(
+    rust_ty: &rustc_public::ty::Ty,
+    enum_bytes: &[u8],
+    loc: Location,
+) -> TranslationResult<usize> {
+    enum_variant_index_from_storage(rust_ty, enum_bytes, None, loc)
+}
+
+fn enum_variant_index_from_alloc(
+    rust_ty: &rustc_public::ty::Ty,
+    enum_bytes: &[u8],
+    alloc: &rustc_public::ty::Allocation,
+    base_offset: usize,
+    loc: Location,
+) -> TranslationResult<usize> {
+    enum_variant_index_from_storage(rust_ty, enum_bytes, Some((alloc, base_offset)), loc)
+}
+
+/// Determine the active enum variant from layout metadata, raw bytes, and
+/// optionally the provenance map of the enclosing allocation.
+///
+/// A niche-encoded pointer enum such as `Option<&T>` stores its carrier in the
+/// pointer word itself. rustc leaves addend bytes in that word and records the
+/// target separately as a relocation, so all-zero bytes do not mean the niche
+/// variant when a full-width relocation covers the carrier.
+fn enum_variant_index_from_storage(
+    rust_ty: &rustc_public::ty::Ty,
+    enum_bytes: &[u8],
+    allocation: Option<(&rustc_public::ty::Allocation, usize)>,
+    loc: Location,
+) -> TranslationResult<usize> {
+    let layout = rust_ty.layout().map_err(|e| {
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "Failed to query enum layout: {:?}",
+            e
+        )))
+    })?;
+    let shape = layout.shape();
+
+    match &shape.variants {
+        rustc_public::abi::VariantsShape::Single { index } => Ok(index.to_index()),
+        rustc_public::abi::VariantsShape::Empty => input_err!(
+            loc,
+            TranslationErr::unsupported("Cannot materialize a constant for an uninhabited enum")
+        ),
+        rustc_public::abi::VariantsShape::Multiple {
+            tag,
+            tag_encoding,
+            tag_field,
+            ..
+        } => {
+            let primitive = match tag {
+                rustc_public::abi::Scalar::Initialized { value, .. }
+                | rustc_public::abi::Scalar::Union { value } => *value,
+            };
+            let scalar_size = primitive.size(&rustc_public::target::MachineInfo::target());
+            let mask = scalar_size.unsigned_int_max().ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Enum tag width {} exceeds 128 bits",
+                    scalar_size.bits()
+                )))
+            })?;
+
+            if let Some((alloc, base_offset)) = allocation {
+                let (relative_tag_offset, tag_size) =
+                    enum_tag_byte_range(&shape.fields, *tag_field, *tag, loc.clone())?;
+                let absolute_tag_offset =
+                    base_offset
+                        .checked_add(relative_tag_offset)
+                        .ok_or_else(|| {
+                            input_error_noloc!(TranslationErr::unsupported(
+                                "Enum tag absolute offset overflowed"
+                            ))
+                        })?;
+                let absolute_tag_end =
+                    absolute_tag_offset.checked_add(tag_size).ok_or_else(|| {
+                        input_error_noloc!(TranslationErr::unsupported(
+                            "Enum tag absolute range overflowed"
+                        ))
+                    })?;
+                let pointer_width =
+                    rustc_public::target::MachineInfo::target_pointer_width().bytes();
+                let overlaps = relocation_offsets_overlapping_range(
+                    &alloc.provenance.ptrs,
+                    absolute_tag_offset,
+                    absolute_tag_end,
+                    pointer_width,
+                );
+
+                if !overlaps.is_empty() {
+                    if let rustc_public::abi::TagEncoding::Niche {
+                        untagged_variant, ..
+                    } = tag_encoding
+                        && tag_size == pointer_width
+                        && overlaps.len() == 1
+                        && overlaps[0] == absolute_tag_offset
+                    {
+                        return Ok(untagged_variant.to_index());
+                    }
+
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "Enum tag bytes [{absolute_tag_offset}..{absolute_tag_end}) overlap \
+                             pointer relocation(s) at {overlaps:?}; only one full-width \
+                             relocation exactly covering a niche pointer carrier is supported"
+                        ))
+                    );
+                }
+            }
+
+            let tag_value =
+                read_enum_tag_value(enum_bytes, &shape.fields, *tag_field, *tag, loc.clone())?;
+
+            match tag_encoding {
+                rustc_public::abi::TagEncoding::Direct => {
+                    // The tag bytes hold a declared discriminant VALUE
+                    // truncated to the PHYSICAL tag width; the caller wants
+                    // a variant INDEX. `discriminant_for_variant().val` is
+                    // at the declared discriminant type's width (isize for
+                    // default-repr enums), so the comparison must mask both
+                    // sides to the tag width (`Neg::N = -5` is byte 0xFB in
+                    // an i8 tag but 0xFFFF_FFFF_FFFF_FFFB as isize). A tag
+                    // that matches no declared discriminant means we
+                    // misread the constant; falling back to
+                    // "value == index" would silently conflate the two
+                    // semantics (the issue #146 bug class).
+                    discriminant_to_variant_index(rust_ty, tag_value, mask).ok_or_else(|| {
+                        input_error!(
+                            loc.clone(),
+                            TranslationErr::unsupported(format!(
+                                "Enum constant tag value {} matches no declared discriminant",
+                                tag_value
+                            ))
+                        )
+                    })
+                }
+                rustc_public::abi::TagEncoding::Niche {
+                    untagged_variant,
+                    niche_variants,
+                    niche_start,
+                } => {
+                    let niche_start_idx = niche_variants.start().to_index();
+                    let niche_end_idx = niche_variants.end().to_index();
+                    Ok(decode_niche_variant_index(
+                        tag_value,
+                        mask,
+                        *niche_start,
+                        niche_start_idx,
+                        niche_end_idx,
+                        untagged_variant.to_index(),
+                    ))
+                }
+            }
+        }
+    }
+}
+
+/// Return the byte range occupied by an enum's direct tag or niche carrier.
+fn enum_tag_byte_range(
+    fields: &rustc_public::abi::FieldsShape,
+    tag_field: usize,
+    tag: rustc_public::abi::Scalar,
+    loc: Location,
+) -> TranslationResult<(usize, usize)> {
+    let primitive = match tag {
+        rustc_public::abi::Scalar::Initialized { value, .. }
+        | rustc_public::abi::Scalar::Union { value } => value,
+    };
+    let byte_size = primitive
+        .size(&rustc_public::target::MachineInfo::target())
+        .bytes();
+    let offset = enum_tag_offset(fields, tag_field, loc)?;
+    Ok((offset, byte_size))
+}
+
+/// Read an enum tag scalar from raw bytes using the stable layout metadata.
+fn read_enum_tag_value(
+    enum_bytes: &[u8],
+    fields: &rustc_public::abi::FieldsShape,
+    tag_field: usize,
+    tag: rustc_public::abi::Scalar,
+    loc: Location,
+) -> TranslationResult<u128> {
+    let (offset, byte_size) = enum_tag_byte_range(fields, tag_field, tag, loc.clone())?;
+
+    let end = offset.checked_add(byte_size).ok_or_else(|| {
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "Enum tag overflowed offset computation: offset={}, size={}",
+            offset, byte_size
+        )))
+    })?;
+    if end > enum_bytes.len() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Enum tag needs bytes [{}..{}), but constant only has {} bytes",
+                offset,
+                end,
+                enum_bytes.len()
+            ))
+        );
+    }
+
+    Ok(read_uint_from_bytes(&enum_bytes[offset..end]))
+}
+
+/// Decode an integer from raw bytes using the current target endianness.
+pub(super) fn read_uint_from_bytes(bytes: &[u8]) -> u128 {
+    match rustc_public::target::MachineInfo::target_endianness() {
+        rustc_public::target::Endian::Little => {
+            bytes.iter().enumerate().fold(0u128, |acc, (idx, byte)| {
+                acc | ((*byte as u128) << (idx * 8))
+            })
+        }
+        rustc_public::target::Endian::Big => bytes
+            .iter()
+            .fold(0u128, |acc, byte| (acc << 8) | (*byte as u128)),
+    }
+}
+
+/// Convert a discriminant value to a variant index.
+///
+/// For enums with explicit discriminants (e.g., `enum { A = 0, B = 2, C = 6 }`),
+/// the discriminant value differs from the variant index:
+/// - Variant index: position in the enum (0, 1, 2, ...)
+/// - Discriminant: the explicit or implicit value assigned to each variant
+///
+/// `tag_value` is the raw tag read from memory, i.e. the discriminant
+/// truncated to the PHYSICAL tag width, while `discriminant_for_variant`
+/// reports values at the declared discriminant type's width (isize for
+/// default-repr enums). `mask` is the tag width's unsigned max; both
+/// sides are masked to it so negative discriminants compare correctly
+/// (`-5` is `0xFB` in an i8 tag but `0xFFFF_FFFF_FFFF_FFFB` as isize).
+///
+/// This function iterates through variants to find which one has the given discriminant.
+fn discriminant_to_variant_index(
+    rust_ty: &rustc_public::ty::Ty,
+    tag_value: u128,
+    mask: u128,
+) -> Option<usize> {
+    use rustc_public::ty::{RigidTy, TyKind};
+
+    match rust_ty.kind() {
+        TyKind::RigidTy(RigidTy::Adt(adt_def, _)) => {
+            for (idx, _variant_def) in adt_def.variants().iter().enumerate() {
+                let variant_idx = rustc_public::ty::VariantIdx::to_val(idx);
+                let discr = adt_def.discriminant_for_variant(variant_idx);
+                if discr.val & mask == tag_value & mask {
+                    return Some(idx);
+                }
+            }
+            None
+        }
+        _ => None,
+    }
+}
+
+/// Create a placeholder `MirConstructEnumOp` for a ghost local.
+///
+/// Ghost locals are MIR locals that are referenced but never assigned — e.g.
+/// rustc optimised away their definition. When translation encounters one we
+/// synthesise a variant-0 enum value with no fields -- the moral equivalent
+/// of LLVM `undef` for an enum.
+///
+/// Typical trigger: `Option<Infallible>` which is always `None` (variant 0,
+/// no payload) after MIR optimisations.
+///
+/// The returned operation is **not** inserted into any block; the caller must
+/// link it via `insert_after` / `insert_at_front`.
+pub(super) fn create_ghost_enum_default(
+    ctx: &mut Context,
+    ty_ptr: pliron::r#type::TypeHandle,
+    loc: Location,
+) -> Ptr<Operation> {
+    use dialect_mir::ops::MirConstructEnumOp;
+    let op = Operation::new(
+        ctx,
+        MirConstructEnumOp::get_concrete_op_info(),
+        vec![ty_ptr],
+        vec![],
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc);
+    MirConstructEnumOp::new(op)
+        .set_attr_construct_enum_variant_index(ctx, dialect_mir::attributes::VariantIndexAttr(0));
+    op
+}
+
+#[cfg(test)]
+mod enum_niche_decode_tests {
+    use super::decode_niche_variant_index;
+
+    #[test]
+    fn i128_relative_value_is_checked_before_usize_conversion() {
+        assert_eq!(
+            decode_niche_variant_index(1u128 << 64, u128::MAX, 0, 0, 1, 2),
+            2,
+            "2^64 must not truncate to relative variant zero on a 64-bit host"
+        );
+    }
+
+    #[test]
+    fn niche_decode_wraps_at_the_carrier_width() {
+        assert_eq!(
+            decode_niche_variant_index(0, u8::MAX.into(), u8::MAX.into(), 3, 4, 1),
+            4,
+            "u8 carrier value 0 is one step after niche_start 255"
+        );
+    }
+}
diff --git a/crates/mir-importer/src/translator/rvalue/const_union.rs b/crates/mir-importer/src/translator/rvalue/const_union.rs
new file mode 100644
index 0000000000..f8b460aaf1
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/const_union.rs
@@ -0,0 +1,784 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Union constant storage classification and translation.
+
+use super::const_alloc::{
+    relocation_offsets_overlapping_range, translate_thin_pointer_at_alloc_offset,
+};
+use super::const_bytes::{
+    constant_type_contains_pointer, rust_type_layout_size, translate_zero_sized_constant_value,
+};
+use super::promoted::constant_allocation;
+use super::statics::GlobalInitializerData;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::types;
+use dialect_mir::attributes::MirCastKindAttr;
+use dialect_mir::ops::{
+    MirCastOp, MirConstantOp, MirConstructArrayOp, MirInsertFieldOp, MirUndefOp,
+};
+use dialect_mir::types::MirPointerKind;
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::TypeHandle;
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use pliron::{input_err, input_error, input_error_noloc};
+use rustc_public::CrateDef;
+use rustc_public::mir;
+use std::num::NonZeroUsize;
+
+/// Physical representation strategy for an initialized union constant.
+///
+/// rustc does not retain the source-level active field in an evaluated union
+/// allocation. Pointer-free unions can therefore use the exact byte image,
+/// while a provenance-bearing union is only reconstructible without guessing
+/// an active field when every non-ZST alternative is the same class of thin
+/// pointer storage.
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub(super) enum UnionConstantStorageKind {
+    ByteImage,
+    ThinPointer {
+        field_index: usize,
+        field_ty: TypeHandle,
+    },
+}
+
+/// How a classified union constant is consumed by its caller.
+///
+/// SSA reconstruction materializes the carrier field's own reference type, so
+/// a reference minted for the wrong alternative could claim validity for a
+/// pointee the program never wrote. Device-static physical storage emits the
+/// exact evaluated bytes plus one integer-width relocation slot and never
+/// mints a typed reference, so same-kind reference alternatives may keep
+/// different pointee views there; device code reads the storage through its
+/// own field types.
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub(super) enum UnionConstantUse {
+    SsaReconstruction,
+    PhysicalStorage,
+}
+
+pub(super) fn classify_union_constant_storage(
+    ctx: &Context,
+    union_ty: TypeHandle,
+    usage: UnionConstantUse,
+) -> Result<UnionConstantStorageKind, String> {
+    let (name, field_types) = {
+        let ty_ref = union_ty.deref(ctx);
+        let union_ty = ty_ref
+            .downcast_ref::<dialect_mir::types::MirUnionType>()
+            .ok_or_else(|| {
+                "classify_union_constant_storage called on non-union type".to_string()
+            })?;
+        (union_ty.name().to_string(), union_ty.field_types().to_vec())
+    };
+
+    if !field_types
+        .iter()
+        .copied()
+        .any(|field| constant_type_contains_pointer(ctx, field))
+    {
+        return Ok(UnionConstantStorageKind::ByteImage);
+    }
+
+    let mut carrier: Option<(usize, TypeHandle, u32, MirPointerKind, bool)> = None;
+    for (field_index, field_ty) in field_types.into_iter().enumerate() {
+        if types::is_zst_type(ctx, field_ty) {
+            continue;
+        }
+
+        let pointer_semantics = {
+            let field_ref = field_ty.deref(ctx);
+            field_ref
+                .downcast_ref::<dialect_mir::types::MirPtrType>()
+                .map(|ptr| (ptr.address_space, ptr.kind, ptr.is_mutable))
+        };
+
+        let Some((address_space, pointer_kind, is_mutable)) = pointer_semantics else {
+            if constant_type_contains_pointer(ctx, field_ty) {
+                return Err(format!(
+                    "Initialized union constant `{name}` contains pointer-bearing field \
+                     {field_index} that is not a thin pointer; fat or nested pointer storage \
+                     in union constants is not supported"
+                ));
+            }
+            return Err(format!(
+                "Initialized union constant `{name}` overlaps thin-pointer storage with \
+                 non-pointer field {field_index}; pointer/integer union constants cannot \
+                 preserve both provenance and exact integer bits"
+            ));
+        };
+
+        if dialect_mir::types::is_opaque_fn_pointer_type(ctx, field_ty) {
+            return Err(format!(
+                "Initialized union constant `{name}` contains canonical function-pointer \
+                 field {field_index}; function tokens cannot serve as data-pointer union storage"
+            ));
+        }
+        if pointer_kind == MirPointerKind::UniqueRef {
+            return Err(format!(
+                "Initialized union constant `{name}` contains UniqueRef field {field_index}; \
+                 constant reconstruction cannot establish uniqueness"
+            ));
+        }
+
+        match carrier {
+            None => {
+                carrier = Some((
+                    field_index,
+                    field_ty,
+                    address_space,
+                    pointer_kind,
+                    is_mutable,
+                ));
+            }
+            Some((
+                _,
+                carrier_field_ty,
+                carrier_address_space,
+                carrier_kind,
+                carrier_mutability,
+            )) if carrier_address_space == address_space
+                && carrier_kind == pointer_kind
+                && carrier_mutability == is_mutable =>
+            {
+                if usage == UnionConstantUse::SsaReconstruction
+                    && pointer_kind == MirPointerKind::SharedRef
+                    && carrier_field_ty != field_ty
+                {
+                    return Err(format!(
+                        "Initialized union constant `{name}` mixes reference pointee types; \
+                         rustc's evaluated allocation does not retain the active union field, \
+                         so reconstructing either reference view could invent pointee validity"
+                    ));
+                }
+            }
+            Some((_, _, carrier_address_space, carrier_kind, carrier_mutability)) => {
+                return Err(format!(
+                    "Initialized union constant `{name}` mixes pointer storage semantics \
+                     (address space/kind/mutability {carrier_address_space}/{carrier_kind:?}/{carrier_mutability} \
+                     and {address_space}/{pointer_kind:?}/{is_mutable}); one union carrier cannot \
+                     preserve both representations and Rust pointer categories"
+                ));
+            }
+        }
+    }
+
+    let Some((field_index, field_ty, _, _, _)) = carrier else {
+        return Err(format!(
+            "Initialized union constant `{name}` is pointer-bearing but has no non-ZST \
+             thin-pointer field"
+        ));
+    };
+
+    Ok(UnionConstantStorageKind::ThinPointer {
+        field_index,
+        field_ty,
+    })
+}
+
+/// Return the full-width integer field through which a relocation-free mixed
+/// raw-pointer/integer union can be reconstructed without producing a pointer.
+///
+/// Keep this deliberately narrower than [`classify_union_constant_storage`]:
+/// the ordinary classifier remains the provenance-preserving authority used by
+/// pointer-bearing constants and device-static union initializers. This helper
+/// only admits one naturally aligned pointer word whose non-ZST alternatives
+/// are semantically compatible generic raw pointers or full-width integers.
+pub(super) fn relocation_free_pointer_integer_union_storage_field(
+    ctx: &Context,
+    union_ty: TypeHandle,
+    pointer_width: usize,
+) -> Option<(usize, TypeHandle)> {
+    let (union_size, union_align, field_types) = {
+        let ty_ref = union_ty.deref(ctx);
+        let union_ty = ty_ref.downcast_ref::<dialect_mir::types::MirUnionType>()?;
+        (
+            union_ty.total_size(),
+            union_ty.abi_align(),
+            union_ty.field_types().to_vec(),
+        )
+    };
+
+    let pointer_width_u64 = pointer_width as u64;
+    if union_size != pointer_width_u64 || union_align != pointer_width_u64 {
+        return None;
+    }
+
+    let integer_width = (pointer_width * 8) as u32;
+    let mut pointer_semantics = None;
+    let mut saw_pointer = false;
+    let mut integer_field = None;
+
+    for (field_index, field_ty) in field_types.into_iter().enumerate() {
+        if types::is_zst_type(ctx, field_ty) {
+            continue;
+        }
+
+        let field_ref = field_ty.deref(ctx);
+        if let Some(pointer) = field_ref.downcast_ref::<dialect_mir::types::MirPtrType>() {
+            if !matches!(
+                pointer.kind,
+                MirPointerKind::RawConst | MirPointerKind::RawMut
+            ) || pointer.address_space != dialect_mir::types::address_space::GENERIC
+            {
+                return None;
+            }
+            let semantics = (pointer.address_space, pointer.kind, pointer.is_mutable);
+            match pointer_semantics {
+                None => pointer_semantics = Some(semantics),
+                Some(existing) if existing == semantics => {}
+                Some(_) => return None,
+            }
+            saw_pointer = true;
+            continue;
+        }
+
+        if field_ref
+            .downcast_ref::<IntegerType>()
+            .is_some_and(|integer| integer.width() == integer_width)
+        {
+            integer_field.get_or_insert((field_index, field_ty));
+            continue;
+        }
+
+        // Fat pointers, nested pointer aggregates, partial-width integers, and
+        // unrelated scalar/aggregate alternatives keep the existing fail-closed
+        // path. The byte-image exception is intentionally pointer-word exact.
+        return None;
+    }
+
+    saw_pointer.then_some(())?;
+    integer_field
+}
+
+/// Admit only the device-static union shape whose complete storage can be
+/// represented by one provenance-preserving thin-pointer relocation.
+///
+/// Device-global initializers do not retain a source-level active union field,
+/// so this path must prove the physical storage without guessing one. Keep the
+/// scope deliberately narrower than ordinary union SSA lowering: one top-level
+/// pointer-sized union, naturally aligned, one relocation at byte zero, and
+/// every non-ZST alternative a representation-compatible thin pointer.
+pub(super) fn validate_device_static_union_initializer(
+    ctx: &Context,
+    static_def: &rustc_public::mir::mono::StaticDef,
+    union_ty: TypeHandle,
+    initializer: &GlobalInitializerData,
+    loc: Location,
+) -> TranslationResult<()> {
+    let relocation_slots: Vec<(u64, u32)> = initializer
+        .relocations
+        .iter()
+        .map(|relocation| (relocation.source_offset, relocation.width_bytes))
+        .collect();
+    validate_device_static_union_storage(
+        ctx,
+        union_ty,
+        rustc_public::target::MachineInfo::target_pointer_width().bytes(),
+        initializer.bytes.len() as u64,
+        initializer.alignment,
+        &relocation_slots,
+    )
+    .map_err(|message| {
+        input_error!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "device static {} contains {message}",
+                static_def.name()
+            ))
+        )
+    })
+}
+
+/// Pure storage gate behind [`validate_device_static_union_initializer`]:
+/// accept only a union that is one naturally aligned pointer word whose
+/// evaluated initializer is exactly one full-width relocation at byte zero.
+/// The caller attaches the static's name and source location to rejections.
+pub(super) fn validate_device_static_union_storage(
+    ctx: &Context,
+    union_ty: TypeHandle,
+    pointer_width: usize,
+    initializer_len: u64,
+    initializer_align: u64,
+    relocation_slots: &[(u64, u32)],
+) -> Result<(), String> {
+    let (union_name, union_size, union_align) = {
+        let ty_ref = union_ty.deref(ctx);
+        let union_ty = ty_ref
+            .downcast_ref::<dialect_mir::types::MirUnionType>()
+            .ok_or_else(|| {
+                "a non-union type in the device-static union initializer gate".to_string()
+            })?;
+        (
+            union_ty.name().to_string(),
+            union_ty.total_size(),
+            union_ty.abi_align(),
+        )
+    };
+
+    let storage_kind =
+        classify_union_constant_storage(ctx, union_ty, UnionConstantUse::PhysicalStorage).map_err(
+            |message| {
+                format!(
+                    "union `{union_name}` whose initializer cannot preserve pointer provenance: \
+                 {message}"
+                )
+            },
+        )?;
+    if !matches!(storage_kind, UnionConstantStorageKind::ThinPointer { .. }) {
+        return Err(format!(
+            "union `{union_name}` without thin-pointer storage; device-global union \
+             initializers are supported only when every non-ZST alternative is a \
+             representation-compatible thin pointer"
+        ));
+    }
+
+    if pointer_width != 8 {
+        return Err(format!(
+            "union `{union_name}`, but cuda-oxide currently supports device-global union \
+             relocations only for 8-byte NVPTX pointers"
+        ));
+    }
+    let pointer_width_u64 = pointer_width as u64;
+
+    if union_size != pointer_width_u64 || union_align != pointer_width_u64 {
+        return Err(format!(
+            "union `{union_name}` with size/alignment {union_size}/{union_align}; \
+             device-global union relocations require exactly one naturally aligned \
+             {pointer_width}-byte pointer word"
+        ));
+    }
+    if initializer_len != pointer_width_u64 || initializer_align != pointer_width_u64 {
+        return Err(format!(
+            "union `{union_name}` with evaluated initializer size/alignment \
+             {initializer_len}/{initializer_align}, expected {pointer_width}/{pointer_width}"
+        ));
+    }
+
+    let [(source_offset, width_bytes)] = relocation_slots else {
+        return Err(format!(
+            "union `{union_name}` with {} initializer relocations; exactly one \
+             thin-pointer relocation is required",
+            relocation_slots.len()
+        ));
+    };
+    if *source_offset != 0 || u64::from(*width_bytes) != pointer_width_u64 {
+        return Err(format!(
+            "union `{union_name}` whose relocation occupies byte {source_offset} with \
+             width {width_bytes}, expected one {pointer_width}-byte slot at byte zero"
+        ));
+    }
+
+    Ok(())
+}
+
+/// Verify that rustc and the MIR union agree on the exact stored size.
+fn union_constant_storage_size(
+    ctx: &Context,
+    rust_ty: &rustc_public::ty::Ty,
+    union_ty: TypeHandle,
+    loc: &Location,
+) -> TranslationResult<usize> {
+    let rust_size = rust_type_layout_size(*rust_ty, loc.clone())?;
+    let (name, mir_size) = {
+        let ty_ref = union_ty.deref(ctx);
+        let union_ty = ty_ref
+            .downcast_ref::<dialect_mir::types::MirUnionType>()
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(
+                    "union_constant_storage_size called on non-union type"
+                ))
+            })?;
+        let size = usize::try_from(union_ty.total_size()).map_err(|_| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Union constant `{}` size {} does not fit usize",
+                union_ty.name(),
+                union_ty.total_size()
+            )))
+        })?;
+        (union_ty.name().to_string(), size)
+    };
+
+    if rust_size != mir_size {
+        return input_err!(
+            loc.clone(),
+            TranslationErr::unsupported(format!(
+                "Union constant `{name}` has rustc size {rust_size}, but MirUnionType records {mir_size}"
+            ))
+        );
+    }
+    Ok(rust_size)
+}
+
+/// Materialize a non-ZST union constant without guessing an active field.
+///
+/// rustc constant evaluation gives us the physical storage image and its
+/// initialization mask, but not a source-level active-field identity. Pointer-free
+/// unions therefore keep the exact byte image. Pointer-only unions use a typed
+/// carrier selected from representation-compatible fields so relocation provenance
+/// survives without claiming which source field initialized the allocation.
+pub(super) fn translate_union_constant(
+    ctx: &mut Context,
+    constant: &mir::ConstOperand,
+    rust_ty: &rustc_public::ty::Ty,
+    union_ty: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let size = union_constant_storage_size(ctx, rust_ty, union_ty, &loc)?;
+    if size == 0 {
+        return translate_zero_sized_constant_value(ctx, union_ty, block_ptr, prev_op, loc);
+    }
+
+    let Some(alloc) = constant_allocation(constant) else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Initialized union constant of {size} byte(s) must be backed by an allocation, found {:?}",
+                constant.const_.kind()
+            ))
+        );
+    };
+
+    translate_union_constant_from_alloc(ctx, alloc, 0, rust_ty, union_ty, block_ptr, prev_op, loc)
+}
+
+/// Materialize one union value from an allocation while preserving its storage semantics.
+///
+/// Pointer-free unions retain the existing byte-image path and exact initialization
+/// mask. A union whose every non-ZST alternative is a compatible thin pointer
+/// instead uses one typed pointer carrier so rustc relocation provenance never
+/// becomes integer bytes. A naturally aligned pointer-word union that overlaps
+/// compatible thin pointers with full-width integers may also use the byte image,
+/// but only when no relocation overlaps its storage. Relocation-bearing mixed
+/// unions, fat pointers, nested pointer aggregates, and ambiguous layouts remain
+/// fail-closed.
+#[allow(clippy::too_many_arguments)]
+pub(super) fn translate_union_constant_from_alloc(
+    ctx: &mut Context,
+    alloc: &rustc_public::ty::Allocation,
+    base_offset: usize,
+    rust_ty: &rustc_public::ty::Ty,
+    union_ty: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let size = union_constant_storage_size(ctx, rust_ty, union_ty, &loc)?;
+    if size == 0 {
+        return translate_zero_sized_constant_value(ctx, union_ty, block_ptr, prev_op, loc);
+    }
+
+    let end = base_offset.checked_add(size).ok_or_else(|| {
+        input_error!(
+            loc.clone(),
+            TranslationErr::unsupported(format!(
+                "Union constant byte range overflows: offset {base_offset} + size {size}"
+            ))
+        )
+    })?;
+    if end > alloc.bytes.len() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Union constant needs bytes [{base_offset}..{end}), but allocation is only {} bytes",
+                alloc.bytes.len()
+            ))
+        );
+    }
+
+    let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+    let relocations = relocation_offsets_overlapping_range(
+        &alloc.provenance.ptrs,
+        base_offset,
+        end,
+        pointer_width,
+    );
+    let storage = &alloc.bytes[base_offset..end];
+
+    // A mixed pointer/integer union initialized through the integer view carries
+    // no relocation provenance. When every byte is initialized, the evaluated
+    // byte image is the complete storage truth. Reconstruct it through the
+    // full-width integer field so no inactive pointer alternative is produced.
+    // Keep this no-relocation exception separate: #984's device-static gate and
+    // relocation-bearing union constants use the stricter pointer classifier.
+    if relocations.is_empty()
+        && storage.iter().all(Option::is_some)
+        && let Some((integer_field_index, integer_field_ty)) =
+            relocation_free_pointer_integer_union_storage_field(ctx, union_ty, pointer_width)
+    {
+        return translate_pointer_integer_union_constant_from_storage(
+            ctx,
+            union_ty,
+            integer_field_index,
+            integer_field_ty,
+            storage,
+            block_ptr,
+            prev_op,
+            loc,
+        );
+    }
+
+    let storage_kind =
+        classify_union_constant_storage(ctx, union_ty, UnionConstantUse::SsaReconstruction)
+            .map_err(|message| input_error!(loc.clone(), TranslationErr::unsupported(message)))?;
+
+    match storage_kind {
+        UnionConstantStorageKind::ByteImage => {
+            if !relocations.is_empty() {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Pointer-free union constant has relocation(s) overlapping byte offset(s) \
+                         {relocations:?}; the union type does not contain storage that can \
+                         preserve that provenance"
+                    ))
+                );
+            }
+
+            translate_union_constant_from_storage(ctx, union_ty, storage, block_ptr, prev_op, loc)
+        }
+        UnionConstantStorageKind::ThinPointer {
+            field_index,
+            field_ty,
+        } => {
+            if size != pointer_width {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Thin-pointer union constant has size {size}, but the target pointer width \
+                         is {pointer_width}; over-aligned or padded pointer-union constants are \
+                         not yet supported because their non-pointer bytes would need a separate \
+                         initialization-mask representation"
+                    ))
+                );
+            }
+
+            if relocations.iter().any(|offset| *offset != base_offset) || relocations.len() > 1 {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Thin-pointer union constant expects at most one relocation anchored at \
+                         byte {base_offset}, found overlapping relocation start(s) {relocations:?}"
+                    ))
+                );
+            }
+
+            let pointer_end = base_offset + pointer_width;
+            if alloc.bytes[base_offset..pointer_end]
+                .iter()
+                .any(|byte| byte.is_none())
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "Thin-pointer union constant contains uninitialized bytes in its pointer \
+                         carrier; partially initialized pointer storage cannot be reconstructed"
+                            .to_string()
+                    )
+                );
+            }
+
+            let (pointer, current_prev_op) = translate_thin_pointer_at_alloc_offset(
+                ctx,
+                alloc,
+                base_offset,
+                field_ty,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+
+            let undef_op = MirUndefOp::new(ctx, union_ty).get_operation();
+            undef_op.deref_mut(ctx).set_loc(loc.clone());
+            match current_prev_op {
+                Some(prev) => undef_op.insert_after(ctx, prev),
+                None => undef_op.insert_at_front(block_ptr, ctx),
+            }
+            let undef_value = undef_op.deref(ctx).get_result(0);
+
+            let insert_op = Operation::new(
+                ctx,
+                MirInsertFieldOp::get_concrete_op_info(),
+                vec![union_ty],
+                vec![undef_value, pointer],
+                vec![],
+                0,
+            );
+            insert_op.deref_mut(ctx).set_loc(loc);
+            MirInsertFieldOp::new(insert_op).set_attr_insert_index(
+                ctx,
+                dialect_mir::attributes::FieldIndexAttr(field_index as u32),
+            );
+            insert_op.insert_after(ctx, undef_op);
+
+            Ok((insert_op.deref(ctx).get_result(0), Some(insert_op)))
+        }
+    }
+}
+
+/// Build `[u8; size]` with one SSA value per physical byte and transmute it to
+/// the union type. `None` bytes become `mir.undef`; no inactive byte is invented.
+fn translate_union_constant_from_storage(
+    ctx: &mut Context,
+    union_ty: TypeHandle,
+    storage: &[Option<u8>],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    if storage.is_empty() {
+        return translate_zero_sized_constant_value(ctx, union_ty, block_ptr, prev_op, loc);
+    }
+
+    let (byte_array, array_op) =
+        translate_constant_storage_byte_array(ctx, storage, block_ptr, prev_op, loc.clone());
+
+    let cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![union_ty],
+        vec![byte_array],
+        vec![],
+        0,
+    );
+    cast_op.deref_mut(ctx).set_loc(loc);
+    MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::Transmute);
+    cast_op.insert_after(ctx, array_op);
+
+    Ok((cast_op.deref(ctx).get_result(0), Some(cast_op)))
+}
+
+/// Reconstruct a relocation-free pointer/integer union through its integer
+/// field, exactly as an ordinary Rust union aggregate is constructed.
+///
+/// The byte-array-to-integer transmute is representation-only and produces no
+/// pointer carrier. Inserting that integer into an undefined union therefore
+/// keeps the pointer alternatives inactive instead of asking a synthetic
+/// transmute to establish their raw-pointer kinds.
+#[allow(clippy::too_many_arguments)]
+pub(super) fn translate_pointer_integer_union_constant_from_storage(
+    ctx: &mut Context,
+    union_ty: TypeHandle,
+    integer_field_index: usize,
+    integer_field_ty: TypeHandle,
+    storage: &[Option<u8>],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    debug_assert!(!storage.is_empty());
+
+    let (byte_array, array_op) =
+        translate_constant_storage_byte_array(ctx, storage, block_ptr, prev_op, loc.clone());
+
+    let integer_cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![integer_field_ty],
+        vec![byte_array],
+        vec![],
+        0,
+    );
+    integer_cast_op.deref_mut(ctx).set_loc(loc.clone());
+    MirCastOp::new(integer_cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::Transmute);
+    integer_cast_op.insert_after(ctx, array_op);
+    let integer_value = integer_cast_op.deref(ctx).get_result(0);
+
+    let undef_op = MirUndefOp::new(ctx, union_ty).get_operation();
+    undef_op.deref_mut(ctx).set_loc(loc.clone());
+    undef_op.insert_after(ctx, integer_cast_op);
+    let undef_value = undef_op.deref(ctx).get_result(0);
+
+    let insert_op = Operation::new(
+        ctx,
+        MirInsertFieldOp::get_concrete_op_info(),
+        vec![union_ty],
+        vec![undef_value, integer_value],
+        vec![],
+        0,
+    );
+    insert_op.deref_mut(ctx).set_loc(loc);
+    MirInsertFieldOp::new(insert_op).set_attr_insert_index(
+        ctx,
+        dialect_mir::attributes::FieldIndexAttr(integer_field_index as u32),
+    );
+    insert_op.insert_after(ctx, undef_op);
+
+    Ok((insert_op.deref(ctx).get_result(0), Some(insert_op)))
+}
+
+/// Build the exact `[u8; size]` SSA image used by constant-storage
+/// reconstruction. `None` bytes remain `mir.undef`.
+fn translate_constant_storage_byte_array(
+    ctx: &mut Context,
+    storage: &[Option<u8>],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> (Value, Ptr<Operation>) {
+    debug_assert!(!storage.is_empty());
+
+    let byte_ty = IntegerType::get(ctx, 8, Signedness::Unsigned);
+    let byte_ty_handle: TypeHandle = byte_ty.into();
+    let mut bytes = Vec::with_capacity(storage.len());
+    let mut current_prev_op = prev_op;
+
+    for byte in storage {
+        let op = match byte {
+            Some(value) => {
+                let attr = pliron::builtin::attributes::IntegerAttr::new(
+                    byte_ty,
+                    APInt::from_u64(
+                        u64::from(*value),
+                        NonZeroUsize::new(8).expect("u8 width is non-zero"),
+                    ),
+                );
+                let op = Operation::new(
+                    ctx,
+                    MirConstantOp::get_concrete_op_info(),
+                    vec![byte_ty_handle],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                MirConstantOp::new(op).set_attr_value(ctx, attr);
+                op
+            }
+            None => MirUndefOp::new(ctx, byte_ty_handle).get_operation(),
+        };
+        op.deref_mut(ctx).set_loc(loc.clone());
+        match current_prev_op {
+            Some(prev) => op.insert_after(ctx, prev),
+            None => op.insert_at_front(block_ptr, ctx),
+        }
+        bytes.push(op.deref(ctx).get_result(0));
+        current_prev_op = Some(op);
+    }
+
+    let byte_array_ty: TypeHandle =
+        dialect_mir::types::MirArrayType::get(ctx, byte_ty_handle, storage.len() as u64).into();
+    let array_op = Operation::new(
+        ctx,
+        MirConstructArrayOp::get_concrete_op_info(),
+        vec![byte_array_ty],
+        bytes,
+        vec![],
+        0,
+    );
+    array_op.deref_mut(ctx).set_loc(loc.clone());
+    match current_prev_op {
+        Some(prev) => array_op.insert_after(ctx, prev),
+        None => array_op.insert_at_front(block_ptr, ctx),
+    }
+    (array_op.deref(ctx).get_result(0), array_op)
+}
diff --git a/crates/mir-importer/src/translator/rvalue/expr.rs b/crates/mir-importer/src/translator/rvalue/expr.rs
new file mode 100644
index 0000000000..ee42db79b2
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/expr.rs
@@ -0,0 +1,1057 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! [`translate_rvalue`]: the main rvalue dispatch.
+
+use super::aggregate::translate_aggregate_rvalue;
+use super::coerce::cast_to_declared_rust_pointer_type_if_needed;
+use super::const_bytes::translate_zero_sized_constant_value;
+use super::const_enum::create_ghost_enum_default;
+use super::fn_ptr::{translate_closure_fn_pointer, translate_reify_fn_pointer};
+use super::operand::translate_operand;
+use super::place_addr::translate_place_address;
+use super::place_read::translate_place;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::facts;
+use crate::translator::types;
+use crate::translator::values::ValueMap;
+use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
+use dialect_mir::ops::{
+    MirAddOp, MirBitAndOp, MirBitOrOp, MirBitXorOp, MirCastOp, MirCheckedAddOp, MirCheckedMulOp,
+    MirCheckedSubOp, MirCmpOp, MirConstructArrayOp, MirDivOp, MirEqOp, MirExtractFieldOp, MirGeOp,
+    MirGtOp, MirLeOp, MirLtOp, MirMulOp, MirNeOp, MirNegOp, MirNotOp, MirPtrOffsetOp, MirRefOp,
+    MirRemOp, MirShlOp, MirShrOp, MirSubOp, MirUndefOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{FP32Type, FP64Type, IntegerType};
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::Typed;
+use pliron::value::Value;
+use pliron::{input_err, input_error, input_error_noloc};
+use rustc_public::mir;
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+enum CheckedBinaryOpKind {
+    Add,
+    Sub,
+    Mul,
+}
+
+fn classify_checked_binary_op(bin_op: &mir::BinOp) -> Result<CheckedBinaryOpKind, String> {
+    match bin_op {
+        mir::BinOp::Add => Ok(CheckedBinaryOpKind::Add),
+        mir::BinOp::Sub => Ok(CheckedBinaryOpKind::Sub),
+        mir::BinOp::Mul => Ok(CheckedBinaryOpKind::Mul),
+        _ => Err(format!("CheckedBinaryOp {:?} not yet implemented", bin_op)),
+    }
+}
+
+/// Translates a MIR rvalue to pliron IR operation(s).
+///
+/// # Returns
+///
+/// Tuple of `(Option<op>, result_value, last_inserted)`:
+/// - `op`: The main operation (None for `Rvalue::Use`)
+/// - `result_value`: The SSA value produced
+/// - `last_inserted`: Last inserted helper op (for operation ordering)
+///
+/// The operation is created but **not inserted** - caller must insert it.
+pub fn translate_rvalue(
+    ctx: &mut Context,
+    body: &mir::Body,
+    rvalue: &mir::Rvalue,
+    value_map: &mut ValueMap,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
+    match rvalue {
+        mir::Rvalue::BinaryOp(bin_op, left, right) => {
+            let (left_val, prev_op_after_left) =
+                translate_operand(ctx, body, left, value_map, block_ptr, prev_op, loc.clone())?;
+            let (right_val, prev_op_after_right) = translate_operand(
+                ctx,
+                body,
+                right,
+                value_map,
+                block_ptr,
+                prev_op_after_left,
+                loc.clone(),
+            )?;
+
+            // Check if this is a comparison operation that may need type coercion
+            let is_comparison = matches!(
+                bin_op,
+                mir::BinOp::Eq
+                    | mir::BinOp::Ne
+                    | mir::BinOp::Lt
+                    | mir::BinOp::Le
+                    | mir::BinOp::Gt
+                    | mir::BinOp::Ge
+            );
+
+            // For comparison operations, handle type mismatches by casting the right operand
+            // to match the left operand's type. This commonly occurs when comparing enum
+            // discriminants (u8) against isize constants in Rust's MIR.
+            let (final_right_val, final_prev_op) = if is_comparison {
+                let left_type = left_val.get_type(ctx);
+                let right_type = right_val.get_type(ctx);
+
+                if left_type != right_type {
+                    // Insert a cast operation to coerce right to match left's type
+                    let cast_op = Operation::new(
+                        ctx,
+                        MirCastOp::get_concrete_op_info(),
+                        vec![left_type],
+                        vec![right_val],
+                        vec![],
+                        0,
+                    );
+                    cast_op.deref_mut(ctx).set_loc(loc.clone());
+                    let coercion_kind = {
+                        let l = left_type.deref(ctx);
+                        let r = right_type.deref(ctx);
+                        if l.downcast_ref::<IntegerType>().is_some()
+                            && r.downcast_ref::<IntegerType>().is_some()
+                        {
+                            MirCastKindAttr::IntToInt
+                        } else if l.downcast_ref::<FP32Type>().is_some()
+                            || l.downcast_ref::<FP64Type>().is_some()
+                        {
+                            if r.downcast_ref::<FP32Type>().is_some()
+                                || r.downcast_ref::<FP64Type>().is_some()
+                            {
+                                MirCastKindAttr::FloatToFloat
+                            } else {
+                                MirCastKindAttr::Transmute
+                            }
+                        } else if l.downcast_ref::<dialect_mir::types::MirPtrType>().is_some()
+                            && r.downcast_ref::<dialect_mir::types::MirPtrType>().is_some()
+                        {
+                            MirCastKindAttr::PtrToPtr
+                        } else {
+                            MirCastKindAttr::Transmute
+                        }
+                    };
+                    MirCastOp::new(cast_op).set_attr_cast_kind(ctx, coercion_kind);
+
+                    // Insert the cast op after the right operand was processed
+                    if let Some(prev) = prev_op_after_right {
+                        cast_op.insert_after(ctx, prev);
+                    } else {
+                        cast_op.insert_at_front(block_ptr, ctx);
+                    }
+
+                    let casted_right = cast_op.deref(ctx).get_result(0);
+                    (casted_right, Some(cast_op))
+                } else {
+                    (right_val, prev_op_after_right)
+                }
+            } else {
+                (right_val, prev_op_after_right)
+            };
+
+            // Determine result type and operation
+            // Comparison operations return bool (i1), arithmetic ops return operand type
+            let (op_id, result_type) = match bin_op {
+                // Arithmetic operations - return same type as operands
+                // Unchecked variants are identical - overflow check is elided at MIR level
+                mir::BinOp::Add | mir::BinOp::AddUnchecked => {
+                    (MirAddOp::get_concrete_op_info(), left_val.get_type(ctx))
+                }
+                mir::BinOp::Sub | mir::BinOp::SubUnchecked => {
+                    (MirSubOp::get_concrete_op_info(), left_val.get_type(ctx))
+                }
+                mir::BinOp::Mul | mir::BinOp::MulUnchecked => {
+                    (MirMulOp::get_concrete_op_info(), left_val.get_type(ctx))
+                }
+                mir::BinOp::Div => (MirDivOp::get_concrete_op_info(), left_val.get_type(ctx)),
+                mir::BinOp::Rem => (MirRemOp::get_concrete_op_info(), left_val.get_type(ctx)),
+
+                // Comparison operations - return bool (i1)
+                mir::BinOp::Lt => (
+                    MirLtOp::get_concrete_op_info(),
+                    types::get_bool_type(ctx).to_handle(),
+                ),
+                mir::BinOp::Le => (
+                    MirLeOp::get_concrete_op_info(),
+                    types::get_bool_type(ctx).to_handle(),
+                ),
+                mir::BinOp::Gt => (
+                    MirGtOp::get_concrete_op_info(),
+                    types::get_bool_type(ctx).to_handle(),
+                ),
+                mir::BinOp::Ge => (
+                    MirGeOp::get_concrete_op_info(),
+                    types::get_bool_type(ctx).to_handle(),
+                ),
+                mir::BinOp::Eq => (
+                    MirEqOp::get_concrete_op_info(),
+                    types::get_bool_type(ctx).to_handle(),
+                ),
+                mir::BinOp::Ne => (
+                    MirNeOp::get_concrete_op_info(),
+                    types::get_bool_type(ctx).to_handle(),
+                ),
+                // Three-way comparison (`Ord::cmp`) - returns
+                // `core::cmp::Ordering`. rustc's `BinOp::ty` knows the
+                // result type of every binop (including `Cmp`, for which it
+                // returns the `Ordering` enum), so derive it locally from
+                // the operand types instead of threading the assignment
+                // destination type through every translate_rvalue caller.
+                mir::BinOp::Cmp => {
+                    let left_ty = left.ty(body.locals()).map_err(|e| {
+                        pliron::input_error!(
+                            loc.clone(),
+                            TranslationErr::unsupported(format!(
+                                "Failed to resolve BinOp::Cmp lhs type: {:?}",
+                                e
+                            ))
+                        )
+                    })?;
+                    let right_ty = right.ty(body.locals()).map_err(|e| {
+                        pliron::input_error!(
+                            loc.clone(),
+                            TranslationErr::unsupported(format!(
+                                "Failed to resolve BinOp::Cmp rhs type: {:?}",
+                                e
+                            ))
+                        )
+                    })?;
+                    let ordering_ty = bin_op.ty(left_ty, right_ty);
+                    (
+                        MirCmpOp::get_concrete_op_info(),
+                        types::translate_type(ctx, &ordering_ty)?,
+                    )
+                }
+
+                // Pointer offset - ptr.add(n) returns ptr + n * sizeof(element)
+                mir::BinOp::Offset => (
+                    MirPtrOffsetOp::get_concrete_op_info(),
+                    left_val.get_type(ctx), // Result is same pointer type
+                ),
+
+                // Shift operations - result is same as left operand type
+                // Unchecked variants are identical - overflow check is elided at MIR level
+                mir::BinOp::Shr | mir::BinOp::ShrUnchecked => {
+                    (MirShrOp::get_concrete_op_info(), left_val.get_type(ctx))
+                }
+                mir::BinOp::Shl | mir::BinOp::ShlUnchecked => {
+                    (MirShlOp::get_concrete_op_info(), left_val.get_type(ctx))
+                }
+
+                // Bitwise operations - result is same as operand type
+                mir::BinOp::BitAnd => (MirBitAndOp::get_concrete_op_info(), left_val.get_type(ctx)),
+                mir::BinOp::BitOr => (MirBitOrOp::get_concrete_op_info(), left_val.get_type(ctx)),
+                mir::BinOp::BitXor => (MirBitXorOp::get_concrete_op_info(), left_val.get_type(ctx)),
+            };
+
+            let op = Operation::new(
+                ctx,
+                op_id,
+                vec![result_type],
+                vec![left_val, final_right_val],
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc);
+
+            let result = op.deref(ctx).get_result(0);
+
+            Ok((Some(op), result, final_prev_op))
+        }
+        mir::Rvalue::UnaryOp(un_op, operand) => {
+            match un_op {
+                mir::UnOp::PtrMetadata => {
+                    // PtrMetadata extracts the length from a slice (fat pointer)
+                    // For a slice &[T], this is field 1 (field 0 is the pointer, field 1 is length)
+                    let (operand_val, prev_op_after_operand) = translate_operand(
+                        ctx,
+                        body,
+                        operand,
+                        value_map,
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                    )?;
+
+                    // Result type is usize (the length)
+                    let result_type = types::get_usize_type(ctx);
+
+                    // Create an extract field operation to get field 1 (length)
+                    let op = Operation::new(
+                        ctx,
+                        MirExtractFieldOp::get_concrete_op_info(),
+                        vec![result_type.to_handle()],
+                        vec![operand_val],
+                        vec![],
+                        0,
+                    );
+                    op.deref_mut(ctx).set_loc(loc.clone());
+
+                    let extract_op = MirExtractFieldOp::new(op);
+                    extract_op.set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(1));
+
+                    let result = extract_op.get_operation().deref(ctx).get_result(0);
+
+                    Ok((
+                        Some(extract_op.get_operation()),
+                        result,
+                        prev_op_after_operand,
+                    ))
+                }
+                mir::UnOp::Not | mir::UnOp::Neg => {
+                    let (operand_val, prev_op_after_operand) = translate_operand(
+                        ctx,
+                        body,
+                        operand,
+                        value_map,
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                    )?;
+                    let result_type = operand_val.get_type(ctx);
+
+                    let op_id = match un_op {
+                        mir::UnOp::Not => MirNotOp::get_concrete_op_info(),
+                        mir::UnOp::Neg => MirNegOp::get_concrete_op_info(),
+                        _ => unreachable!(),
+                    };
+
+                    let op =
+                        Operation::new(ctx, op_id, vec![result_type], vec![operand_val], vec![], 0);
+                    op.deref_mut(ctx).set_loc(loc);
+
+                    let result = op.deref(ctx).get_result(0);
+
+                    Ok((Some(op), result, prev_op_after_operand))
+                }
+            }
+        }
+        mir::Rvalue::Cast(kind, operand, ty) => {
+            // `let f: fn(u32) -> u32 = inc;` compiles to a ReifyFnPointer
+            // cast. It is not a value conversion: the fn item `inc` is
+            // zero-sized, so there is nothing to convert. What the program
+            // needs is some address-like value identifying the function.
+            // Real code addresses do not exist on the device (the function
+            // may not even be compiled), so we make a stable stand-in: a
+            // hash of the function's mangled name, cast int -> ptr. With
+            // that, `f == f` is true and two different functions compare
+            // unequal (Rust permits, but does not promise, distinct fn
+            // addresses, so a hash stand-in is within contract). CALLING
+            // through the pointer is still unsupported and fails loudly at
+            // the call site. Handled before translate_operand because the
+            // zero-sized fn-item operand itself never becomes a value.
+            if let mir::CastKind::PointerCoercion(mir::PointerCoercion::ReifyFnPointer(_)) = kind {
+                return translate_reify_fn_pointer(ctx, body, operand, ty, block_ptr, prev_op, loc);
+            }
+            if let mir::CastKind::PointerCoercion(mir::PointerCoercion::ClosureFnPointer(_)) = kind
+            {
+                return translate_closure_fn_pointer(
+                    ctx, body, operand, ty, block_ptr, prev_op, loc,
+                );
+            }
+
+            let (operand_val, prev_op_after_operand) = translate_operand(
+                ctx,
+                body,
+                operand,
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+
+            let result_type = types::translate_type(ctx, ty)?;
+
+            let op = Operation::new(
+                ctx,
+                MirCastOp::get_concrete_op_info(),
+                vec![result_type],
+                vec![operand_val],
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc);
+
+            let cast_kind_attr = match kind {
+                mir::CastKind::IntToInt => MirCastKindAttr::IntToInt,
+                mir::CastKind::IntToFloat => MirCastKindAttr::IntToFloat,
+                mir::CastKind::FloatToInt => MirCastKindAttr::FloatToInt,
+                mir::CastKind::FloatToFloat => MirCastKindAttr::FloatToFloat,
+                mir::CastKind::PtrToPtr => MirCastKindAttr::PtrToPtr,
+                mir::CastKind::FnPtrToPtr => MirCastKindAttr::FnPtrToPtr,
+                mir::CastKind::PointerExposeAddress => MirCastKindAttr::PointerExposeAddress,
+                mir::CastKind::PointerWithExposedProvenance => {
+                    MirCastKindAttr::PointerWithExposedProvenance
+                }
+                mir::CastKind::Transmute => MirCastKindAttr::Transmute,
+                mir::CastKind::PointerCoercion(coercion) => match coercion {
+                    mir::PointerCoercion::Unsize => MirCastKindAttr::PointerCoercionUnsize,
+                    mir::PointerCoercion::MutToConstPointer => {
+                        MirCastKindAttr::PointerCoercionMutToConst
+                    }
+                    mir::PointerCoercion::ArrayToPointer => {
+                        MirCastKindAttr::PointerCoercionArrayToPointer
+                    }
+                    mir::PointerCoercion::ReifyFnPointer(_) => {
+                        MirCastKindAttr::PointerCoercionReifyFnPointer
+                    }
+                    mir::PointerCoercion::UnsafeFnPointer => {
+                        MirCastKindAttr::PointerCoercionUnsafeFnPointer
+                    }
+                    mir::PointerCoercion::ClosureFnPointer(_safety) => {
+                        MirCastKindAttr::PointerCoercionClosureFnPointer
+                    }
+                },
+                mir::CastKind::Subtype => MirCastKindAttr::Subtype,
+            };
+            let cast_op = MirCastOp::new(op);
+            cast_op.set_attr_cast_kind(ctx, cast_kind_attr.clone());
+            if dialect_mir::types::type_contains_concrete_pointer_kind(ctx, result_type)
+                || (cast_kind_attr == MirCastKindAttr::Transmute
+                    && !dialect_mir::types::pointer_kinds_in_type(ctx, result_type).is_empty())
+            {
+                // This operation comes directly from a rustc MIR CastKind, so
+                // any concrete result category, including one nested in an
+                // aggregate transmute, is an explicit Rust semantic boundary
+                // rather than a generic representation adjustment.
+                cast_op.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::RustCast);
+            }
+
+            let result = op.deref(ctx).get_result(0);
+
+            Ok((Some(op), result, prev_op_after_operand))
+        }
+        mir::Rvalue::CheckedBinaryOp(bin_op, left, right) => {
+            let checked_kind = classify_checked_binary_op(bin_op).map_err(|message| {
+                input_error!(loc.clone(), TranslationErr::unsupported(message))
+            })?;
+
+            let (left_val, prev_op_after_left) =
+                translate_operand(ctx, body, left, value_map, block_ptr, prev_op, loc.clone())?;
+            let (right_val, prev_op_after_right) = translate_operand(
+                ctx,
+                body,
+                right,
+                value_map,
+                block_ptr,
+                prev_op_after_left,
+                loc.clone(),
+            )?;
+
+            // The result type is the MIR-level `(T, bool)` tuple.
+            // Translate it from the rvalue's rustc type so it is the
+            // same uniqued, layout-carrying tuple type the rest of
+            // the body (locals, places) uses.
+            let rust_tuple_ty = rvalue.ty(body.locals()).map_err(|e| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Failed to query checked-arithmetic result type: {:?}",
+                    e
+                )))
+            })?;
+            let result_type = types::translate_type(ctx, &rust_tuple_ty)?;
+
+            let op_id = match checked_kind {
+                CheckedBinaryOpKind::Add => MirCheckedAddOp::get_concrete_op_info(),
+                CheckedBinaryOpKind::Sub => MirCheckedSubOp::get_concrete_op_info(),
+                CheckedBinaryOpKind::Mul => MirCheckedMulOp::get_concrete_op_info(),
+            };
+            let op = Operation::new(
+                ctx,
+                op_id,
+                vec![result_type],
+                vec![left_val, right_val],
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc);
+
+            let result = op.deref(ctx).get_result(0);
+            Ok((Some(op), result, prev_op_after_right))
+        }
+        mir::Rvalue::Use(operand) => {
+            // Use just copies/moves a value - no operation needed, just pass through
+            // The operand translation may insert field extraction operations
+            let (val, last_inserted) =
+                translate_operand(ctx, body, operand, value_map, block_ptr, prev_op, loc)?;
+
+            // Return None for operation - Use doesn't create an operation
+            // Any field extractions are already inserted and tracked in last_inserted
+            Ok((None, val, last_inserted))
+        }
+        mir::Rvalue::Ref(_region, borrow_kind, place) => {
+            // Ref creates a reference to a place: &place or &mut place.
+            //
+            // Strategy:
+            //
+            // 1. `&local` / `&mut local` -- return the local's alloca slot
+            //    pointer directly (ZST locals get a synthesised pointer).
+            // 2. Any projected place -- compute the real in-memory address
+            //    by walking the FULL projection list from the base local's
+            //    slot via `translate_place_address`: `&(*ptr)` loads the
+            //    pointer, `&(*ptr).field` adds a `mir.field_addr`,
+            //    `&x.arr[i]` adds a `mir.array_element_addr`, and arbitrary
+            //    combinations compose. Borrows produced this way ALIAS the
+            //    original storage, which is what Rust requires: e.g.
+            //    `Enumerate::next` takes `&mut (*_1).0` and `Iter::next`
+            //    must advance the ORIGINAL Iter in place -- a `mir.ref` of
+            //    an extracted field VALUE would mutate a copy and loop
+            //    forever.
+            // 3. Only when no address can be computed (slot-less computed
+            //    value, or a projection the walker cannot lower, e.g.
+            //    Downcast) do we fall back to materialising the VALUE and
+            //    wrapping it in `mir.ref` (fresh slot + store of a COPY).
+            //    That is sound for shared borrows (reads through a copy)
+            //    and a silent miscompile for mutable ones (writes land in
+            //    the copy), so mutable borrows hard-error instead.
+
+            // Case 1: bare local reference `&local` / `&mut local`.
+            //
+            // Alloca + load/store model: every non-ZST MIR local is backed by
+            // a stack slot emitted at the top of the entry block. Taking the
+            // address of the local therefore just returns that slot pointer --
+            // no extra allocation is needed. `mem2reg` folds this back into
+            // SSA when the borrow doesn't escape.
+            //
+            // Slots are always allocated mutable because the importer writes
+            // locals through them. They are compiler storage, not `&mut T`.
+            // The normalization below retypes the physical slot address to the
+            // exact Rust reference kind without treating slot mutability as
+            // evidence of uniqueness.
+            let origin = facts::pointer_origin_of_borrow(*borrow_kind);
+            let is_mutable = origin.is_mutable();
+            if place.projection.is_empty() {
+                if let Some(slot) = value_map.get_slot(place.local) {
+                    // The slot is compiler storage (`Erased`) and is always
+                    // mutable. Taking a Rust borrow is the semantic boundary
+                    // where that physical address acquires the exact `&T` /
+                    // `&mut T` type recorded by rustc.
+                    let rust_result_type = rvalue.ty(body.locals()).map_err(|error| {
+                        input_error_noloc!(TranslationErr::unsupported(format!(
+                            "failed to determine reference rvalue type: {error:?}"
+                        )))
+                    })?;
+                    let expected_ptr_type = types::translate_type(ctx, &rust_result_type)?;
+                    let (result, last_inserted) = cast_to_declared_rust_pointer_type_if_needed(
+                        ctx,
+                        slot,
+                        expected_ptr_type,
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                        MirPointerKindAuthorityAttr::Reborrow,
+                    );
+                    return Ok((None, result, last_inserted));
+                }
+                // ZST local (no slot). Synthesise a pointer-to-ZST via
+                // MirRefOp as a fallback so callers still get a well-typed
+                // pointer value.
+                let local_decl = &body.locals()[place.local];
+                let ty_ptr = crate::translator::types::translate_type(ctx, &local_decl.ty)?;
+                let (zst_val, last_inserted) =
+                    if ty_ptr.deref(ctx).is::<dialect_mir::types::MirEnumType>() {
+                        let op = create_ghost_enum_default(ctx, ty_ptr, loc.clone());
+                        match prev_op {
+                            Some(p) => op.insert_after(ctx, p),
+                            None => op.insert_at_front(block_ptr, ctx),
+                        }
+                        (op.deref(ctx).get_result(0), Some(op))
+                    } else {
+                        translate_zero_sized_constant_value(
+                            ctx,
+                            ty_ptr,
+                            block_ptr,
+                            prev_op,
+                            loc.clone(),
+                        )?
+                    };
+                let ptr_ty = facts::mint_generic_ptr_type(ctx, ty_ptr, origin);
+                let ref_op = Operation::new(
+                    ctx,
+                    MirRefOp::get_concrete_op_info(),
+                    vec![ptr_ty.into()],
+                    vec![zst_val],
+                    vec![],
+                    0,
+                );
+                ref_op.deref_mut(ctx).set_loc(loc);
+                let mir_ref = MirRefOp::new(ref_op);
+                mir_ref.set_mutable(ctx, is_mutable);
+                mir_ref.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::Reborrow);
+                match last_inserted {
+                    Some(p) => ref_op.insert_after(ctx, p),
+                    None => ref_op.insert_at_front(block_ptr, ctx),
+                }
+                let result_val = ref_op.deref(ctx).get_result(0);
+                return Ok((None, result_val, Some(ref_op)));
+            }
+
+            // Case 2: unified address path -- walk the full projection list
+            // (`Deref`, `Field`, `Index`, `ConstantIndex`) from the base
+            // local's alloca slot. This is the "correct-refs" path: the
+            // resulting pointer addresses the ORIGINAL storage, so writes
+            // through the borrow mutate the borrowed place.
+            if let Some((result_val, last_inserted)) = translate_place_address(
+                ctx,
+                body,
+                value_map,
+                place,
+                is_mutable,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )? {
+                // Address arithmetic remains in the physical address space, but the
+                // resulting Rust reference must have its exact translated Rust type.
+                let rust_result_type = rvalue.ty(body.locals()).map_err(|error| {
+                    input_error_noloc!(TranslationErr::unsupported(format!(
+                        "failed to determine reference rvalue type: {error:?}"
+                    )))
+                })?;
+                let expected_ptr_type = types::translate_type(ctx, &rust_result_type)?;
+
+                let (result_val, last_inserted) = cast_to_declared_rust_pointer_type_if_needed(
+                    ctx,
+                    result_val,
+                    expected_ptr_type,
+                    block_ptr,
+                    last_inserted,
+                    loc.clone(),
+                    MirPointerKindAuthorityAttr::Reborrow,
+                );
+
+                return Ok((None, result_val, last_inserted));
+            }
+
+            // No address could be computed. The only remaining strategy is
+            // the value-copy fallback below, which is a silent miscompile
+            // for mutable borrows: writes through the borrow would land in
+            // the copy and the original place would never change. Refuse
+            // loudly instead of emitting wrong code.
+            if is_mutable {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Rvalue::Ref: cannot compute an in-memory address for the mutable \
+                         borrow of place {:?} (projection {:?}); the value-copy fallback \
+                         would silently discard writes through the borrow",
+                        place, place.projection
+                    ))
+                );
+            }
+
+            // Case 3: shared-borrow fallback -- reference to a computed
+            // value that has no backing slot (e.g. the result of an rvalue
+            // expression) or whose projection the address walker cannot
+            // lower (e.g. enum Downcast, issues #131/#146). Emit `mir.ref`
+            // which allocates a fresh slot, stores a COPY of the value, and
+            // returns the pointer. Sound for shared borrows only (reads);
+            // mutable borrows were rejected above.
+            let (val, last_inserted) =
+                translate_place(ctx, body, place, value_map, block_ptr, prev_op, loc.clone())?;
+
+            let val_ty = val.get_type(ctx);
+            let ptr_ty = facts::mint_generic_ptr_type(ctx, val_ty, origin);
+
+            let ref_op = Operation::new(
+                ctx,
+                MirRefOp::get_concrete_op_info(),
+                vec![ptr_ty.into()],
+                vec![val],
+                vec![],
+                0,
+            );
+            ref_op.deref_mut(ctx).set_loc(loc);
+            let mir_ref = MirRefOp::new(ref_op);
+            mir_ref.set_mutable(ctx, is_mutable);
+            mir_ref.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::Reborrow);
+
+            let result_val = ref_op.deref(ctx).get_result(0);
+            Ok((Some(ref_op), result_val, last_inserted))
+        }
+        mir::Rvalue::AddressOf(mutability, place) => {
+            // AddressOf creates a raw pointer to a place: `&raw const place`
+            // / `&raw mut place` (also `core::ptr::addr_of!`). Raw pointers
+            // have the same aliasing requirement as references: the pointer
+            // must address the ORIGINAL place, so this routes through the
+            // same unified address walker as `Rvalue::Ref` (which also gives
+            // raw pointers the runtime-Index / ConstantIndex handling).
+            let origin = facts::pointer_origin_of_raw_ptr(*mutability);
+            let is_mutable = origin.is_mutable();
+
+            // Bare local: the alloca slot is the physical address, but the
+            // result must carry the exact raw-pointer kind rather than the
+            // slot's compiler-only `Erased` provenance.
+            if place.projection.is_empty()
+                && let Some(slot) = value_map.get_slot(place.local)
+            {
+                let rust_result_type = rvalue.ty(body.locals()).map_err(|error| {
+                    input_error_noloc!(TranslationErr::unsupported(format!(
+                        "failed to determine address-of rvalue type: {error:?}"
+                    )))
+                })?;
+                let expected_ptr_type = types::translate_type(ctx, &rust_result_type)?;
+                let (result, last_inserted) = cast_to_declared_rust_pointer_type_if_needed(
+                    ctx,
+                    slot,
+                    expected_ptr_type,
+                    block_ptr,
+                    prev_op,
+                    loc.clone(),
+                    MirPointerKindAuthorityAttr::RawAddress,
+                );
+                return Ok((None, result, last_inserted));
+            }
+
+            // Unified address path: full projection walk from the slot
+            // (`&raw (*ptr)` loads the pointer, `&raw (*ptr).field[i]`
+            // composes field + element addresses, ...).
+            if let Some((result_val, last_inserted)) = translate_place_address(
+                ctx,
+                body,
+                value_map,
+                place,
+                is_mutable,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )? {
+                // Preserve physical address spaces while walking the place, then restore
+                // the exact raw-pointer type required by the Rust rvalue.
+                let rust_result_type = rvalue.ty(body.locals()).map_err(|error| {
+                    input_error_noloc!(TranslationErr::unsupported(format!(
+                        "failed to determine address-of rvalue type: {error:?}"
+                    )))
+                })?;
+                let expected_ptr_type = types::translate_type(ctx, &rust_result_type)?;
+
+                let (result_val, last_inserted) = cast_to_declared_rust_pointer_type_if_needed(
+                    ctx,
+                    result_val,
+                    expected_ptr_type,
+                    block_ptr,
+                    last_inserted,
+                    loc.clone(),
+                    MirPointerKindAuthorityAttr::RawAddress,
+                );
+
+                return Ok((None, result_val, last_inserted));
+            }
+
+            // No address could be computed. The value-copy fallback below
+            // returns a pointer to a COPY, so writes through a `&raw mut`
+            // would be silently lost -- refuse loudly. Exception: a bare
+            // slot-less local is a ZST (no bytes), so a copy cannot lose
+            // writes; let it use the fallback for both mutabilities, the
+            // same way `Rvalue::Ref` synthesises ZST borrows.
+            if is_mutable && !place.projection.is_empty() {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Rvalue::AddressOf: cannot compute an in-memory address for \
+                         `&raw mut` of place {:?} (projection {:?}); the value-copy \
+                         fallback would silently discard writes through the pointer",
+                        place, place.projection
+                    ))
+                );
+            }
+
+            // Shared (or bare-ZST) fallback: translate to a value and
+            // materialize an address of a copy.
+            let (val, last_inserted) =
+                translate_place(ctx, body, place, value_map, block_ptr, prev_op, loc.clone())?;
+
+            let val_ty = val.get_type(ctx);
+            let ptr_ty = facts::mint_generic_ptr_type(ctx, val_ty, origin);
+
+            use dialect_mir::ops::MirRefOp;
+            let ref_op = Operation::new(
+                ctx,
+                MirRefOp::get_concrete_op_info(),
+                vec![ptr_ty.into()],
+                vec![val],
+                vec![],
+                0,
+            );
+            ref_op.deref_mut(ctx).set_loc(loc);
+
+            let mir_ref_op = MirRefOp::new(ref_op);
+            mir_ref_op.set_mutable(ctx, is_mutable);
+            mir_ref_op.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::RawAddress);
+
+            let result_val = ref_op.deref(ctx).get_result(0);
+
+            Ok((Some(ref_op), result_val, last_inserted))
+        }
+        mir::Rvalue::Aggregate(aggregate_kind, operands) => translate_aggregate_rvalue(
+            ctx,
+            body,
+            rvalue,
+            aggregate_kind,
+            operands,
+            value_map,
+            block_ptr,
+            prev_op,
+            loc,
+        ),
+        mir::Rvalue::Discriminant(place) => {
+            // Get the discriminant (tag) from an enum value.
+            //
+            // Two discriminant types can be in play:
+            //   - `native_tag_ty`: the logical result type produced by our
+            //     enum operation. For Direct layouts this is the physical tag
+            //     type; for Niche/Single layouts the operation decodes or
+            //     materializes the logical discriminant directly.
+            //   - `mir_discr_ty`: the type stable-MIR declares for the
+            //     `Rvalue::Discriminant(place)` value itself, via
+            //     `Ty::kind().discriminant_ty()`. This is what rustc uses
+            //     to type the destination local (often `i64`).
+            //
+            // When the two types disagree (normally a narrow Direct tag versus
+            // stable MIR's wider declared type), widen via `mir.cast IntToInt`
+            // so the rvalue matches what stable MIR promised. Without this,
+            // storing the result into its destination slot would fail
+            // verification.
+            use dialect_mir::ops::MirGetDiscriminantOp;
+            use dialect_mir::types::MirEnumType;
+            use pliron::builtin::types::IntegerType;
+            use pliron::printable::Printable;
+
+            let (enum_val, prev_op_after) =
+                translate_place(ctx, body, place, value_map, block_ptr, prev_op, loc.clone())?;
+
+            let enum_ty = enum_val.get_type(ctx);
+            let (native_tag_ty, enum_is_uninhabited) = {
+                let enum_ty_obj = enum_ty.deref(ctx);
+                if let Some(enum_type) = enum_ty_obj.downcast_ref::<MirEnumType>() {
+                    let uninhabited = !enum_type
+                        .variant_inhabited
+                        .iter()
+                        .any(|inhabited| *inhabited != 0);
+                    (enum_type.discriminant_type(), uninhabited)
+                } else {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "Discriminant on non-enum type: {}",
+                            enum_ty.disp(ctx)
+                        ))
+                    );
+                }
+            };
+
+            // No value of an uninhabited enum can exist, so this read sits
+            // on a dynamically dead path rustc keeps in MIR (e.g. matching
+            // the residual `ControlFlow<Infallible, NeverShortCircuitResidual>`
+            // inside `array::try_from_fn`). `mir.get_discriminant` refuses
+            // uninhabited enums by verification, so keep the dead path
+            // representable with a typed undef of the declared discriminant
+            // type instead.
+            if enum_is_uninhabited {
+                let declared_discr_ty = place
+                    .ty(body.locals())
+                    .ok()
+                    .and_then(|place_ty| place_ty.kind().discriminant_ty());
+                let undef_ty = match declared_discr_ty {
+                    Some(ty) => crate::translator::types::translate_type(ctx, &ty)?,
+                    None => native_tag_ty,
+                };
+                let undef = MirUndefOp::new(ctx, undef_ty).get_operation();
+                undef.deref_mut(ctx).set_loc(loc);
+                let result = undef.deref(ctx).get_result(0);
+                return Ok((Some(undef), result, prev_op_after));
+            }
+
+            let get_disc_op = Operation::new(
+                ctx,
+                MirGetDiscriminantOp::get_concrete_op_info(),
+                vec![native_tag_ty],
+                vec![enum_val],
+                vec![],
+                0,
+            );
+            get_disc_op.deref_mut(ctx).set_loc(loc.clone());
+            let native_result = get_disc_op.deref(ctx).get_result(0);
+
+            // Ask stable-MIR what the declared discriminant type of this
+            // place is. For well-formed MIR on an enum place this should
+            // always succeed; if we can't compute it, fall back to the
+            // native tag (no cast). In the fallback path we preserve the
+            // original contract: the caller inserts `get_disc_op`.
+            let place_ty = place.ty(body.locals()).map_err(|e| {
+                input_error!(
+                    loc.clone(),
+                    TranslationErr::unsupported(format!(
+                        "Failed to resolve place type for Discriminant: {:?}",
+                        e
+                    ))
+                )
+            })?;
+            let declared_discr_ty = place_ty.kind().discriminant_ty();
+
+            let mir_discr_ty = match declared_discr_ty {
+                Some(ty) => crate::translator::types::translate_type(ctx, &ty)?,
+                None => {
+                    return Ok((Some(get_disc_op), native_result, prev_op_after));
+                }
+            };
+
+            // Only widen when both sides are integers and differ. Anything
+            // else is either already matched or a dialect-level mismatch
+            // that deserves its own verifier error upstream.
+            let needs_cast = mir_discr_ty != native_tag_ty && {
+                let src = native_tag_ty.deref(ctx);
+                let dst = mir_discr_ty.deref(ctx);
+                src.is::<IntegerType>() && dst.is::<IntegerType>()
+            };
+
+            if !needs_cast {
+                return Ok((Some(get_disc_op), native_result, prev_op_after));
+            }
+
+            // Widening path: we emit two ops (get_discriminant + cast) and
+            // the caller only inserts a single "main" op. Insert both here
+            // and return `None` as the main op so the caller does not try
+            // to re-insert.
+            if let Some(prev) = prev_op_after {
+                get_disc_op.insert_after(ctx, prev);
+            } else {
+                get_disc_op.insert_at_front(block_ptr, ctx);
+            }
+
+            let cast_op = Operation::new(
+                ctx,
+                MirCastOp::get_concrete_op_info(),
+                vec![mir_discr_ty],
+                vec![native_result],
+                vec![],
+                0,
+            );
+            cast_op.deref_mut(ctx).set_loc(loc);
+            MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::IntToInt);
+            cast_op.insert_after(ctx, get_disc_op);
+
+            let result = cast_op.deref(ctx).get_result(0);
+            Ok((None, result, Some(cast_op)))
+        }
+        mir::Rvalue::Repeat(operand, count) => {
+            // Array repeat: [value; N] -> mir.construct_array with N copies of value
+            //
+            // MIR: _1 = Repeat(Constant(0.0f32), 16)
+            // Produces: [0.0, 0.0, 0.0, ...] (16 elements)
+
+            // Extract the count from TyConst
+            let array_size = count.eval_target_usize().map_err(|e| {
+                input_error!(
+                    loc.clone(),
+                    TranslationErr::unsupported(format!(
+                        "Failed to evaluate Repeat count: {:?}",
+                        e
+                    ))
+                )
+            })?;
+
+            // Translate the operand to get the element value
+            let (element_val, prev_op_after_operand) = translate_operand(
+                ctx,
+                body,
+                operand,
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+
+            // Get the element type from the value
+            let element_type = element_val.get_type(ctx);
+
+            // Create element values by repeating the single value
+            let element_values: Vec<Value> =
+                std::iter::repeat_n(element_val, array_size as usize).collect();
+
+            // Create the array type
+            let array_ty = dialect_mir::types::MirArrayType::get(ctx, element_type, array_size);
+
+            // Create mir.construct_array operation
+            let op = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                element_values,
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc);
+
+            let result = op.deref(ctx).get_result(0);
+
+            Ok((Some(op), result, prev_op_after_operand))
+        }
+        mir::Rvalue::CopyForDeref(place) => {
+            // CopyForDeref is semantically a place read. Any load or projection
+            // operations emitted by translate_place are already inserted and tracked.
+            //
+            // Note: on the pinned toolchain the MIR optimization pipeline
+            // (copy-prop/GVN) eliminates every CopyForDeref before the
+            // optimized MIR reaches this importer; nested-deref kernels
+            // (`**rr`, including through raw pointers) were probed and none
+            // produce one here today. This arm is defensive coverage so a
+            // future toolchain bump or lower mir-opt-level cannot regress
+            // valid nested-deref kernels into an "unsupported construct"
+            // failure.
+            let (value, last_inserted) =
+                translate_place(ctx, body, place, value_map, block_ptr, prev_op, loc)?;
+
+            Ok((None, value, last_inserted))
+        }
+        mir::Rvalue::Len(place) => input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Rvalue::Len for place {:?} not yet implemented",
+                place
+            ))
+        ),
+        mir::Rvalue::ThreadLocalRef(item) => input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Rvalue::ThreadLocalRef {:?} is not supported in device code",
+                item
+            ))
+        ),
+    }
+}
+
+#[cfg(test)]
+mod checked_binary_op_tests {
+    use super::*;
+
+    #[test]
+    fn checked_binary_op_accepts_supported_operators() {
+        assert_eq!(
+            classify_checked_binary_op(&mir::BinOp::Add),
+            Ok(CheckedBinaryOpKind::Add)
+        );
+        assert_eq!(
+            classify_checked_binary_op(&mir::BinOp::Sub),
+            Ok(CheckedBinaryOpKind::Sub)
+        );
+        assert_eq!(
+            classify_checked_binary_op(&mir::BinOp::Mul),
+            Ok(CheckedBinaryOpKind::Mul)
+        );
+    }
+
+    #[test]
+    fn checked_binary_op_rejects_unsupported_operator() {
+        let error = classify_checked_binary_op(&mir::BinOp::Div)
+            .expect_err("Div must remain unsupported as CheckedBinaryOp");
+
+        assert_eq!(error, "CheckedBinaryOp Div not yet implemented");
+    }
+}
diff --git a/crates/mir-importer/src/translator/rvalue/fn_ptr.rs b/crates/mir-importer/src/translator/rvalue/fn_ptr.rs
new file mode 100644
index 0000000000..7a6e0de1dc
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/fn_ptr.rs
@@ -0,0 +1,193 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Function-pointer reification.
+
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::types;
+use dialect_mir::attributes::MirCastKindAttr;
+use dialect_mir::ops::MirCastOp;
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use pliron::{input_err, input_error_noloc};
+use rustc_public::CrateDef;
+use rustc_public::mir;
+use std::num::NonZeroUsize;
+
+/// Lower a `fn item -> fn pointer` coercion (`ReifyFnPointer`).
+///
+/// Emits a stable per-function token (hash of the function's mangled
+/// name, never 0 so it cannot look like a null pointer) and casts it
+/// int -> ptr. See the comment at the `Rvalue::Cast` arm for why a token
+/// stands in for a code address on the device.
+pub(super) fn translate_reify_fn_pointer(
+    ctx: &mut Context,
+    body: &mir::Body,
+    operand: &mir::Operand,
+    dest_ty: &rustc_public::ty::Ty,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
+    use rustc_public::mir::mono::Instance;
+    use std::hash::{Hash, Hasher};
+
+    // The operand's type names the function being reified.
+    let operand_ty = operand.ty(body.locals()).map_err(|e| {
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "ReifyFnPointer: cannot read operand type: {e:?}"
+        )))
+    })?;
+    let rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::FnDef(fn_def, substs)) =
+        operand_ty.kind()
+    else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "ReifyFnPointer on a non-fn-item operand of type {operand_ty:?}"
+            ))
+        );
+    };
+    let raw_intrinsic =
+        crate::translator::terminator::intrinsics::generated::require_supported_raw_intrinsic(
+            fn_def, &loc,
+        )?;
+    let compatibility_path = fn_def.name().as_str().to_string();
+    if let Some(path) = raw_intrinsic.or_else(|| {
+        crate::translator::terminator::intrinsics::generated::is_generated_intrinsic_path(
+            &compatibility_path,
+        )
+        .then_some(compatibility_path)
+    }) {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "generated CUDA intrinsic `{path}` must be called directly and cannot be converted to a function pointer"
+            ))
+        );
+    }
+    let mangled = Instance::resolve(fn_def, &substs)
+        .map_err(|e| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "ReifyFnPointer: cannot resolve fn item: {e:?}"
+            )))
+        })?
+        .mangled_name();
+    let token = {
+        let mut h = std::collections::hash_map::DefaultHasher::new();
+        mangled.hash(&mut h);
+        h.finish() | 1
+    };
+
+    materialize_function_pointer_token(ctx, dest_ty, token, block_ptr, prev_op, loc)
+}
+
+/// Lower a non-capturing `closure -> fn pointer` coercion.
+///
+/// Like named function items, a closure value is zero-sized and contains no
+/// code address to extract. Resolve rustc's `FnOnce` closure shim and use its
+/// mangled identity to create the same non-null comparison token used by
+/// `translate_reify_fn_pointer`.
+pub(super) fn translate_closure_fn_pointer(
+    ctx: &mut Context,
+    body: &mir::Body,
+    operand: &mir::Operand,
+    dest_ty: &rustc_public::ty::Ty,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
+    use rustc_public::{
+        mir::mono::Instance,
+        ty::{ClosureKind, RigidTy, TyKind},
+    };
+    use std::hash::{Hash, Hasher};
+
+    let operand_ty = operand.ty(body.locals()).map_err(|error| {
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "ClosureFnPointer: cannot read operand type: {error:?}"
+        )))
+    })?;
+    let TyKind::RigidTy(RigidTy::Closure(closure_def, substs)) = operand_ty.kind() else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "ClosureFnPointer on a non-closure operand of type {operand_ty:?}"
+            ))
+        );
+    };
+    let mangled = Instance::resolve_closure(closure_def, &substs, ClosureKind::FnOnce)
+        .map_err(|error| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "ClosureFnPointer: cannot resolve closure shim: {error:?}"
+            )))
+        })?
+        .mangled_name();
+    let token = {
+        let mut hasher = std::collections::hash_map::DefaultHasher::new();
+        mangled.hash(&mut hasher);
+        hasher.finish() | 1
+    };
+
+    materialize_function_pointer_token(ctx, dest_ty, token, block_ptr, prev_op, loc)
+}
+
+fn materialize_function_pointer_token(
+    ctx: &mut Context,
+    dest_ty: &rustc_public::ty::Ty,
+    token: u64,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Option<Ptr<Operation>>, Value, Option<Ptr<Operation>>)> {
+    use dialect_mir::ops::MirConstantOp;
+
+    // Materialize the token and cast it to the fn-pointer type, the same
+    // two-op shape used for provenance-carrying pointer constants.
+    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+    let apint = APInt::from_u64(token, NonZeroUsize::new(64).unwrap());
+    let int_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, apint);
+    let int_op = Operation::new(
+        ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    int_op.deref_mut(ctx).set_loc(loc.clone());
+    MirConstantOp::new(int_op).set_attr_value(ctx, int_attr);
+    match prev_op {
+        Some(prev) => int_op.insert_after(ctx, prev),
+        None => int_op.insert_at_front(block_ptr, ctx),
+    }
+    let int_val = int_op.deref(ctx).get_result(0);
+
+    let result_type = types::translate_type(ctx, dest_ty)?;
+    let cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![result_type],
+        vec![int_val],
+        vec![],
+        0,
+    );
+    cast_op.deref_mut(ctx).set_loc(loc);
+    let cast = MirCastOp::new(cast_op);
+    cast.set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
+
+    let result = cast_op.deref(ctx).get_result(0);
+    Ok((Some(cast_op), result, Some(int_op)))
+}
+
+// Byte-offset lookups over rustc enum layout live in the shared
+// `translator::layout` module so type import and constant decoding cannot
+// drift on how an offset is derived.
diff --git a/crates/mir-importer/src/translator/rvalue/mod.rs b/crates/mir-importer/src/translator/rvalue/mod.rs
new file mode 100644
index 0000000000..654417b778
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/mod.rs
@@ -0,0 +1,57 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Rvalue translation: MIR expressions → `dialect-mir` operations.
+//!
+//! Translates the right-hand side of MIR assignments into `dialect-mir` ops.
+//!
+//! # Supported Rvalues
+//!
+//! | MIR Rvalue          | `dialect-mir` Op                                      |
+//! |---------------------|-------------------------------------------------------|
+//! | `BinaryOp(+,-,*,/)` | `mir.add`, `mir.sub`, `mir.mul`, `mir.div`            |
+//! | `BinaryOp(<,<=,>)`  | `mir.lt`, `mir.le`, `mir.gt`, etc.                    |
+//! | `CheckedBinaryOp`   | `mir.checked_add`, etc. (returns tuple)               |
+//! | `UnaryOp(Not,Neg)`  | `mir.not`, `mir.neg`                                  |
+//! | `Cast`              | `mir.cast`                                            |
+//! | `Ref`               | Slot pointer for locals; `mir.ref` for SSA values     |
+//! | `Use(operand)`      | `mir.load` of the source slot (no op for constants)   |
+//! | `Aggregate`         | `mir.construct_tuple/struct/enum/array`               |
+//! | `Repeat`            | `mir.construct_array` (array repeat syntax)           |
+//! | `CopyForDeref`      | Same place-read lowering as `Copy`/`Move`             |
+//!
+//! # Key Functions
+//!
+//! - [`translate_rvalue`]: Main entry point for rvalue translation
+//! - [`translate_operand`]: Translates operands (Copy/Move/Constant/RuntimeChecks)
+//! - [`translate_place`]: Translates places to their SSA values (handles ghost locals)
+//! - `translate_constant`: Translates MIR constants to `dialect-mir`
+//! - `create_ghost_enum_default`: Synthesises a placeholder for never-assigned enum locals
+
+mod aggregate;
+mod coerce;
+mod const_alloc;
+mod const_bytes;
+mod const_enum;
+mod const_union;
+mod expr;
+mod fn_ptr;
+mod operand;
+mod place_addr;
+mod place_iter;
+mod place_read;
+mod pointee;
+mod promoted;
+mod static_global;
+mod statics;
+
+pub use expr::translate_rvalue;
+pub use operand::translate_operand;
+pub use place_read::translate_place;
+
+pub(crate) use const_bytes::constant_bytes;
+pub(crate) use place_addr::{enum_payload_needs_storage_coercion_pub, translate_place_address};
+pub(crate) use place_read::apply_enum_field_projection_pub;
+pub(crate) use promoted::translate_array_constant_into_alloca;
diff --git a/crates/mir-importer/src/translator/rvalue/operand.rs b/crates/mir-importer/src/translator/rvalue/operand.rs
new file mode 100644
index 0000000000..92e1be5a80
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/operand.rs
@@ -0,0 +1,1313 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! [`translate_operand`] plus float-constant and shared-array helpers.
+
+use super::coerce::{cast_to_declared_rust_pointer_type_if_needed, erase_thin_pointer_kind};
+use super::const_alloc::{
+    array_to_slice_unsize_info, interior_array_to_slice_unsize_info, slice_len_from_constant,
+    translate_static_array_as_slice,
+};
+use super::const_bytes::{
+    constant_bytes, translate_array_value_constant, translate_constant_value_from_bytes,
+    translate_struct_constant, translate_tuple_constant, translate_zero_sized_constant_value,
+};
+use super::const_enum::{read_uint_from_bytes, translate_enum_constant};
+use super::const_union::translate_union_constant;
+use super::place_read::translate_place;
+use super::promoted::translate_ptr_to_array_constant;
+use super::static_global::{get_static_pointer_info, translate_static_global_pointer};
+use super::statics::{
+    shared_static_source_identity, shared_static_source_name, static_target_from_constant,
+};
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::facts;
+use crate::translator::types;
+use crate::translator::values::ValueMap;
+use dialect_iket::{ops::IketSentinelTokenOp, types::IketRangeTokenType};
+use dialect_mir::attributes::MirFP16Attr;
+use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
+use dialect_mir::ops::MirRefOp;
+use dialect_mir::types::MirFP16Type;
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{FP32Type, FP64Type, IntegerType};
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::TypeHandle;
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use pliron::{input_err, input_err_noloc, input_error, input_error_noloc};
+use rustc_public::CrateDef;
+use rustc_public::mir;
+use rustc_public::ty::ConstantKind;
+use std::num::NonZeroUsize;
+
+fn read_float_constant_bits(
+    constant: &mir::ConstOperand,
+    kind_name: &str,
+    byte_width: usize,
+    loc: Location,
+) -> TranslationResult<u128> {
+    let bytes = constant_bytes(constant, kind_name, loc.clone())?;
+
+    if bytes.len() < byte_width {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "{kind_name} constant needs {byte_width} bytes, found {}",
+                bytes.len()
+            ))
+        );
+    }
+
+    Ok(read_uint_from_bytes(&bytes[..byte_width]))
+}
+
+fn translate_float_constant(
+    ctx: &mut Context,
+    constant: &mir::ConstOperand,
+    const_ty: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    use dialect_mir::ops::MirFloatConstantOp;
+    use pliron::builtin::attributes::{FPDoubleAttr, FPSingleAttr};
+
+    /// Bit pattern decoded from the MIR constant, tagged by float width.
+    enum FloatBits {
+        F16(u16),
+        F32(u32),
+        F64(u64),
+    }
+
+    // Decode the constant bytes before allocating the op, so a decode
+    // error cannot leave an orphan operation behind in the context.
+    let bits = if const_ty.deref(ctx).is::<MirFP16Type>() {
+        FloatBits::F16(read_float_constant_bits(constant, "f16", 2, loc.clone())? as u16)
+    } else if const_ty.deref(ctx).is::<FP32Type>() {
+        FloatBits::F32(read_float_constant_bits(constant, "f32", 4, loc.clone())? as u32)
+    } else if const_ty.deref(ctx).is::<FP64Type>() {
+        FloatBits::F64(read_float_constant_bits(constant, "f64", 8, loc.clone())? as u64)
+    } else {
+        unreachable!("translate_float_constant called with a non-float type");
+    };
+
+    let op = Operation::new(
+        ctx,
+        MirFloatConstantOp::get_concrete_op_info(),
+        vec![const_ty],
+        vec![],
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc.clone());
+
+    let float_op = MirFloatConstantOp::new(op);
+
+    match bits {
+        FloatBits::F16(bits) => {
+            float_op.set_attr_float_value_f16(ctx, MirFP16Attr::from_bits(bits));
+        }
+        FloatBits::F32(bits) => {
+            float_op.set_attr_float_value(ctx, FPSingleAttr::from(f32::from_bits(bits)));
+        }
+        FloatBits::F64(bits) => {
+            float_op.set_attr_float_value_f64(ctx, FPDoubleAttr::from(f64::from_bits(bits)));
+        }
+    }
+
+    if let Some(prev) = prev_op {
+        float_op.get_operation().insert_after(ctx, prev);
+    } else {
+        float_op.get_operation().insert_at_front(block_ptr, ctx);
+    }
+
+    let value = float_op.get_operation().deref(ctx).get_result(0);
+    Ok((value, Some(float_op.get_operation())))
+}
+
+/// Translate a MIR Operand to a pliron IR [`Value`].
+/// Returns the value and the last inserted operation (for proper ordering).
+///
+/// Handles Copy, Move (via translate_place) and Constant operands.
+pub fn translate_operand(
+    ctx: &mut Context,
+    body: &mir::Body,
+    operand: &mir::Operand,
+    value_map: &mut ValueMap,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    match operand {
+        mir::Operand::Copy(place) | mir::Operand::Move(place) => {
+            // Get the value from the place
+            translate_place(ctx, body, place, value_map, block_ptr, prev_op, loc)
+        }
+        mir::Operand::Constant(constant) => {
+            // Get the Rust type of this constant
+            let rust_ty = constant.ty();
+
+            // Check if this is a pointer to SharedArray (static shared memory)
+            if is_shared_array_pointer(&rust_ty) {
+                // Extract element type, size, and alignment from SharedArray<T, N, ALIGN>
+                let (elem_ty, array_size, alignment) = extract_shared_array_info(ctx, &rust_ty)?;
+
+                // Allocation creates physical storage with Erased provenance.
+                // The Rust constant's exact reference/raw-pointer kind is
+                // established explicitly after the producer.
+                let declared_ptr_ty = types::translate_type(ctx, &rust_ty)?;
+                let storage_ptr_ty =
+                    erase_thin_pointer_kind(ctx, declared_ptr_ty).ok_or_else(|| {
+                        input_error_noloc!(TranslationErr::unsupported(
+                            "SharedArray constant did not translate to a thin pointer type"
+                        ))
+                    })?;
+
+                // Create a MirSharedAllocOp to represent the shared memory allocation
+                // This will be lowered to an LLVM global with addrspace(3)
+                //
+                // NOTE: We include the alloc key in the operation so the LLVM lowering
+                // phase can deduplicate multiple references to the same static.
+                use dialect_mir::ops::MirSharedAllocOp;
+                let op = Operation::new(
+                    ctx,
+                    MirSharedAllocOp::get_concrete_op_info(),
+                    vec![storage_ptr_ty],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                op.deref_mut(ctx).set_loc(loc.clone());
+
+                let shared_alloc = MirSharedAllocOp::new(op);
+
+                // Set the element type, size, and alloc key attributes
+                use pliron::builtin::attributes::{IntegerAttr, StringAttr, TypeAttr};
+                shared_alloc.set_attr_elem_type(ctx, TypeAttr::new(elem_ty));
+                let size_attr = IntegerAttr::new(
+                    pliron::builtin::types::IntegerType::get(
+                        ctx,
+                        64,
+                        pliron::builtin::types::Signedness::Signless,
+                    ),
+                    pliron::utils::apint::APInt::from_u64(
+                        array_size as u64,
+                        std::num::NonZeroUsize::new(64).unwrap(),
+                    ),
+                );
+                shared_alloc.set_attr_size(ctx, size_attr);
+
+                // Full debug resolves an injective static key.  Off and line
+                // tables deliberately retain the historical allocation key and
+                // avoid the extra stable-MIR identity work entirely.
+                let source_identity = value_map
+                    .debug_variables()
+                    .then(|| shared_static_source_identity(constant))
+                    .flatten();
+                let alloc_key = if let Some(identity) = &source_identity {
+                    identity.key.clone()
+                } else {
+                    format!("{:?}", constant.const_)
+                };
+                shared_alloc.set_attr_alloc_key(ctx, StringAttr::new(alloc_key));
+
+                // Record which Rust `static` this is. The alloc key above is
+                // opaque and lowering mints an anonymous `__shared_mem_N`
+                // symbol, so without this the generated shared-memory blocks
+                // cannot be attributed back to source.
+                if let Some(identity) = source_identity {
+                    shared_alloc.set_attr_source_name(ctx, StringAttr::new(identity.name));
+                    shared_alloc.set_attr_source_key(ctx, StringAttr::new(identity.key));
+                } else if let Some(source_name) = shared_static_source_name(constant) {
+                    shared_alloc.set_attr_source_name(ctx, StringAttr::new(source_name));
+                }
+
+                // Set alignment if specified (non-zero)
+                if alignment > 0 {
+                    shared_alloc.set_alignment_value(ctx, alignment as u64);
+                }
+
+                if let Some(prev) = prev_op {
+                    shared_alloc.get_operation().insert_after(ctx, prev);
+                } else {
+                    shared_alloc.get_operation().insert_at_front(block_ptr, ctx);
+                }
+
+                let storage = shared_alloc.get_operation().deref(ctx).get_result(0);
+                let (value, last_op) = cast_to_declared_rust_pointer_type_if_needed(
+                    ctx,
+                    storage,
+                    declared_ptr_ty,
+                    block_ptr,
+                    Some(shared_alloc.get_operation()),
+                    loc.clone(),
+                    MirPointerKindAuthorityAttr::StaticAddress,
+                );
+
+                return Ok((value, last_op));
+            }
+
+            // Check if this is a pointer to Barrier (static barrier in shared memory)
+            if is_barrier_pointer(&rust_ty) {
+                // Barrier is a single 64-bit value in shared memory (mbarrier state)
+                let elem_ty = pliron::builtin::types::IntegerType::get(
+                    ctx,
+                    64,
+                    pliron::builtin::types::Signedness::Unsigned,
+                )
+                .into();
+
+                // Keep the allocation itself Erased, then establish the Rust
+                // constant's declared pointer category at a visible boundary.
+                let declared_ptr_ty = types::translate_type(ctx, &rust_ty)?;
+                let storage_ptr_ty =
+                    erase_thin_pointer_kind(ctx, declared_ptr_ty).ok_or_else(|| {
+                        input_error_noloc!(TranslationErr::unsupported(
+                            "Barrier constant did not translate to a thin pointer type"
+                        ))
+                    })?;
+
+                // Create a MirSharedAllocOp for the barrier
+                use dialect_mir::ops::MirSharedAllocOp;
+                let op = Operation::new(
+                    ctx,
+                    MirSharedAllocOp::get_concrete_op_info(),
+                    vec![storage_ptr_ty],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                op.deref_mut(ctx).set_loc(loc.clone());
+
+                let shared_alloc = MirSharedAllocOp::new(op);
+
+                // Set attributes: element type (i64), size (1 element)
+                use pliron::builtin::attributes::{IntegerAttr, StringAttr, TypeAttr};
+                shared_alloc.set_attr_elem_type(ctx, TypeAttr::new(elem_ty));
+                let size_attr = IntegerAttr::new(
+                    pliron::builtin::types::IntegerType::get(
+                        ctx,
+                        64,
+                        pliron::builtin::types::Signedness::Signless,
+                    ),
+                    pliron::utils::apint::APInt::from_u64(
+                        1, // Single barrier element
+                        std::num::NonZeroUsize::new(64).unwrap(),
+                    ),
+                );
+                shared_alloc.set_attr_size(ctx, size_attr);
+
+                let source_identity = value_map
+                    .debug_variables()
+                    .then(|| shared_static_source_identity(constant))
+                    .flatten();
+                let alloc_key = if let Some(identity) = &source_identity {
+                    identity.key.clone()
+                } else {
+                    format!("{:?}", constant.const_)
+                };
+                shared_alloc.set_attr_alloc_key(ctx, StringAttr::new(alloc_key));
+
+                // A `Barrier` static occupies shared memory too, so name it
+                // for the same attribution reason as `SharedArray` above.
+                if let Some(identity) = source_identity {
+                    shared_alloc.set_attr_source_name(ctx, StringAttr::new(identity.name));
+                    shared_alloc.set_attr_source_key(ctx, StringAttr::new(identity.key));
+                } else if let Some(source_name) = shared_static_source_name(constant) {
+                    shared_alloc.set_attr_source_name(ctx, StringAttr::new(source_name));
+                }
+
+                if let Some(prev) = prev_op {
+                    shared_alloc.get_operation().insert_after(ctx, prev);
+                } else {
+                    shared_alloc.get_operation().insert_at_front(block_ptr, ctx);
+                }
+
+                let storage = shared_alloc.get_operation().deref(ctx).get_result(0);
+                let (value, last_op) = cast_to_declared_rust_pointer_type_if_needed(
+                    ctx,
+                    storage,
+                    declared_ptr_ty,
+                    block_ptr,
+                    Some(shared_alloc.get_operation()),
+                    loc.clone(),
+                    MirPointerKindAuthorityAttr::StaticAddress,
+                );
+
+                return Ok((value, last_op));
+            }
+
+            // Ordinary Rust `static` / `static mut` values in device code live in
+            // CUDA global memory (addrspace 1) by default. SharedArray/Barrier
+            // statics have already been intercepted above and remain addrspace 3.
+            // Statics tagged `#[constant]` (detected by the mangled symbol
+            // prefix) instead lower into constant memory (addrspace 4).
+            if let Some((pointee_ty, origin)) = get_static_pointer_info(&rust_ty)
+                && let Some(static_target) = static_target_from_constant(constant, loc.clone())?
+            {
+                let is_mutable = origin.is_mutable();
+                let static_ty = static_target.static_def.ty();
+                let pointee_mir_ty = types::translate_type(ctx, &pointee_ty)?;
+                let static_mir_ty = types::translate_type(ctx, &static_ty)?;
+
+                // A zero addend may name either the whole static or a subobject
+                // at byte zero (for example `&ARRAY[0]` or `&STRUCT.first`).
+                // Array→slice unsize remains special because it needs a fat
+                // pointer carrying the evaluated metadata word. Other sized
+                // pointees continue through byte-address normalization below.
+                if static_target.byte_offset == 0
+                    && pointee_mir_ty != static_mir_ty
+                    && let Some((elem_ty, array_len)) =
+                        array_to_slice_unsize_info(&static_ty, &pointee_ty, loc.clone())?
+                {
+                    // The emitted length is the constant's own metadata
+                    // word, not the array's N: a zero-addend prefix
+                    // subslice (`split_at(k).0` over the static) stores
+                    // k there. The array length only bounds it.
+                    let len = slice_len_from_constant(constant, loc.clone())?;
+                    if len > array_len {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "constant slice over device static {} stores length {}, \
+                                 which exceeds the static array's length {}",
+                                static_target.static_def.name(),
+                                len,
+                                array_len
+                            ))
+                        );
+                    }
+                    return translate_static_array_as_slice(
+                        ctx,
+                        &static_target.static_def,
+                        elem_ty,
+                        len,
+                        origin,
+                        0,
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                    );
+                }
+
+                if static_target.byte_offset != 0
+                    && let Some((elem_ty, remaining_len)) = interior_array_to_slice_unsize_info(
+                        &static_ty,
+                        &pointee_ty,
+                        static_target.byte_offset,
+                        loc.clone(),
+                    )?
+                {
+                    let len = slice_len_from_constant(constant, loc.clone())?;
+
+                    if len > remaining_len {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "constant slice over device static {} stores length {}, \
+                                 which exceeds the selected array region's remaining length {}",
+                                static_target.static_def.name(),
+                                len,
+                                remaining_len,
+                            ))
+                        );
+                    }
+
+                    return translate_static_array_as_slice(
+                        ctx,
+                        &static_target.static_def,
+                        elem_ty,
+                        len,
+                        origin,
+                        static_target.byte_offset,
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                    );
+                }
+
+                // Every remaining path emits a thin pointer, including a
+                // zero-addend pointer to a first field/element. A slice, str,
+                // trait object, or another DST requires metadata and cannot be
+                // represented here. Note that `layout()` succeeds for DSTs
+                // such as `[f32]`, so check the returned shape explicitly.
+                let pointee_layout = pointee_ty.layout().map_err(|e| {
+                    input_error!(
+                        loc.clone(),
+                        TranslationErr::unsupported(format!(
+                            "constant pointer into device static {} has byte offset {}, \
+                             but pointee type {:?} does not have a sized layout: {:?}",
+                            static_target.static_def.name(),
+                            static_target.byte_offset,
+                            pointee_ty,
+                            e
+                        ))
+                    )
+                })?;
+                if !pointee_layout.shape().is_sized() {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "constant pointer into device static {} has byte offset {}, \
+                             but pointee type {:?} is unsized; cuda-oxide does not yet \
+                             preserve the fat-pointer metadata this slice or DST pointer needs",
+                            static_target.static_def.name(),
+                            static_target.byte_offset,
+                            pointee_ty
+                        ))
+                    );
+                }
+
+                // The materialized constant pointer must carry the exact
+                // translated Rust operand type. Slot stores and mem2reg are
+                // type-strict, so shapes like `_1 = const &STATIC;
+                // &(*_1).field` need the operand normalized here rather
+                // than leaving the physical-address-space pointer type
+                // exposed to the rest of the function body.
+                let result_ptr_ty = types::translate_type(ctx, &rust_ty)?;
+
+                return translate_static_global_pointer(
+                    ctx,
+                    &static_target.static_def,
+                    pointee_mir_ty,
+                    result_ptr_ty,
+                    is_mutable,
+                    static_target.byte_offset,
+                    block_ptr,
+                    prev_op,
+                    loc.clone(),
+                );
+            }
+
+            let const_ty_ptr = types::translate_type(ctx, &rust_ty)?;
+
+            // `RangeToken<R>` is intentionally a Rust ZST. Optimized MIR can
+            // therefore materialize a token operand as an independent ZST
+            // constant instead of preserving the call-result SSA edge. Keep a
+            // well-typed semantic placeholder here; the frontend-provided
+            // static range key pairs range_start/range_end during lowering.
+            if const_ty_ptr.deref(ctx).is::<IketRangeTokenType>() {
+                let op = IketSentinelTokenOp::new(ctx).get_operation();
+                op.deref_mut(ctx).set_loc(loc);
+                if let Some(prev) = prev_op {
+                    op.insert_after(ctx, prev);
+                } else {
+                    op.insert_at_front(block_ptr, ctx);
+                }
+                return Ok((op.deref(ctx).get_result(0), Some(op)));
+            }
+
+            // ZSTs have no runtime bytes, but they still need a value with the
+            // exact translated type. This is critical for marker structs,
+            // unit, and zero-sized unions.
+            if types::is_zst_type(ctx, const_ty_ptr) {
+                return translate_zero_sized_constant_value(
+                    ctx,
+                    const_ty_ptr,
+                    block_ptr,
+                    prev_op,
+                    loc,
+                );
+            }
+
+            // A fully-uninitialized constant allocation (`MaybeUninit::uninit()`
+            // and similar: every byte uninit, no provenance) has no defined
+            // bytes to materialize for any type; its value is `undef`.
+            if let ConstantKind::Allocated(alloc) = constant.const_.kind()
+                && !alloc.bytes.is_empty()
+                && alloc.bytes.iter().all(|b| b.is_none())
+                && alloc.provenance.ptrs.is_empty()
+            {
+                use dialect_mir::ops::MirUndefOp;
+                let op = MirUndefOp::new(ctx, const_ty_ptr).get_operation();
+                op.deref_mut(ctx).set_loc(loc);
+                if let Some(prev) = prev_op {
+                    op.insert_after(ctx, prev);
+                } else {
+                    op.insert_at_front(block_ptr, ctx);
+                }
+                return Ok((op.deref(ctx).get_result(0), Some(op)));
+            }
+
+            // Check if this is a struct type (non-ZST)
+            // For struct constants, we need to construct the struct from its field values.
+            let is_struct = const_ty_ptr
+                .deref(ctx)
+                .is::<dialect_mir::types::MirStructType>();
+            let is_tuple = const_ty_ptr
+                .deref(ctx)
+                .is::<dialect_mir::types::MirTupleType>();
+
+            // Check if this is a float type (f16, f32, or f64)
+            let is_float_16 = const_ty_ptr.deref(ctx).is::<MirFP16Type>();
+            let is_float_32 = const_ty_ptr.deref(ctx).is::<FP32Type>();
+            let is_float_64 = const_ty_ptr.deref(ctx).is::<FP64Type>();
+            let is_float = is_float_16 || is_float_32 || is_float_64;
+
+            // Check if this is an enum type
+            let is_enum = const_ty_ptr
+                .deref(ctx)
+                .is::<dialect_mir::types::MirEnumType>();
+            let is_union = const_ty_ptr
+                .deref(ctx)
+                .is::<dialect_mir::types::MirUnionType>();
+
+            // Check if this is a pointer to an array (byte strings, or typed arrays like [f64; 3])
+            let is_ptr_to_array = const_ty_ptr
+                .deref(ctx)
+                .downcast_ref::<dialect_mir::types::MirPtrType>()
+                .map(|ptr_ty| {
+                    ptr_ty
+                        .pointee
+                        .deref(ctx)
+                        .is::<dialect_mir::types::MirArrayType>()
+                })
+                .unwrap_or(false);
+
+            // Check if this is a bare array value constant (e.g. `const TABLE: [f32; N]`
+            // referenced as `TABLE[runtime_idx]`, which materialises the whole array
+            // as an operand rather than a pointer to it).
+            let is_array_value = const_ty_ptr
+                .deref(ctx)
+                .is::<dialect_mir::types::MirArrayType>();
+
+            if is_float {
+                return translate_float_constant(
+                    ctx,
+                    constant,
+                    const_ty_ptr,
+                    block_ptr,
+                    prev_op,
+                    loc,
+                );
+            }
+
+            // Debug repr kept for diagnostics only (CUDA_OXIDE_DEBUG_CONST and
+            // the unsupported-constant error at the bottom); constant VALUES
+            // are read through typed rustc_public APIs, never parsed from it.
+            let const_str = format!("{:?}", constant.const_);
+
+            // Handle pointer-to-array constants (byte strings, typed arrays like [f64; 3], etc.)
+            if is_ptr_to_array {
+                return translate_ptr_to_array_constant(
+                    ctx,
+                    constant,
+                    const_ty_ptr,
+                    block_ptr,
+                    prev_op,
+                    loc,
+                );
+            }
+
+            // Handle bare array value constants (e.g. `TABLE[runtime_idx]` where
+            // `TABLE: [f32; N]` materialises the whole array by value).
+            if is_array_value {
+                return translate_array_value_constant(
+                    ctx,
+                    constant,
+                    const_ty_ptr,
+                    block_ptr,
+                    prev_op,
+                    loc,
+                );
+            }
+
+            if is_struct {
+                // Non-ZST struct constant - extract field values and construct the struct
+                translate_struct_constant(
+                    ctx,
+                    constant,
+                    &rust_ty,
+                    const_ty_ptr,
+                    block_ptr,
+                    prev_op,
+                    loc,
+                )
+            } else if is_tuple {
+                translate_tuple_constant(
+                    ctx,
+                    constant,
+                    &rust_ty,
+                    const_ty_ptr,
+                    block_ptr,
+                    prev_op,
+                    loc,
+                )
+            } else if is_enum {
+                translate_enum_constant(
+                    ctx,
+                    constant,
+                    &rust_ty,
+                    const_ty_ptr,
+                    block_ptr,
+                    prev_op,
+                    loc,
+                )
+            } else if is_union {
+                translate_union_constant(
+                    ctx,
+                    constant,
+                    &rust_ty,
+                    const_ty_ptr,
+                    block_ptr,
+                    prev_op,
+                    loc,
+                )
+            } else if const_ty_ptr
+                .deref(ctx)
+                .is::<dialect_mir::types::MirPtrType>()
+            {
+                // Pointer type constant - could be:
+                // 1. A raw pointer constant (like core::ptr::null()) - just bytes,
+                //    no provenance
+                // 2. A reference to a constant struct (like &(8..16)) - need
+                //    struct + mir.ref
+                // 3. A reference to any other promoted constant (like the `&77`
+                //    that -O const-folds out of `Option<&u32>::unwrap_or(&77)`,
+                //    issue #132) - follow the allocation provenance, materialize
+                //    the pointee constant, then mir.ref
+                //
+                // Only constants WITHOUT provenance may take the raw-pointer
+                // path; a provenance entry always names a real allocation, and
+                // ignoring it would lower the reference to `inttoptr 0` (a null
+                // pointer).
+
+                // Extract pointer type info before further borrows
+                let (pointee_ty, is_mutable, pointee_is_struct) = {
+                    let ty_ref = const_ty_ptr.deref(ctx);
+                    let ptr_ty = ty_ref
+                        .downcast_ref::<dialect_mir::types::MirPtrType>()
+                        .unwrap();
+                    let pointee = ptr_ty.pointee;
+                    let mutable = ptr_ty.is_mutable;
+                    let is_struct = pointee.deref(ctx).is::<dialect_mir::types::MirStructType>();
+                    (pointee, mutable, is_struct)
+                };
+
+                // Check if the constant has actual struct data (not all zeros)
+                // Handle both Allocated constants and promoted constants (Ty variant)
+                //
+                // Debug: print constant info for reference-to-struct types
+                if pointee_is_struct && std::env::var("CUDA_OXIDE_DEBUG_CONST").is_ok() {
+                    eprintln!(
+                        "[DEBUG] Ptr-to-struct constant: kind={:?}, str={:?}",
+                        constant.const_.kind(),
+                        const_str
+                    );
+                }
+
+                let has_struct_data = if pointee_is_struct {
+                    match constant.const_.kind() {
+                        ConstantKind::Allocated(alloc) => {
+                            // For promoted constants like &(8..16), the bytes are zeros
+                            // (pointer placeholder) but provenance indicates a real allocation.
+                            // Check for provenance OR non-zero bytes.
+                            let has_provenance = !alloc.provenance.ptrs.is_empty();
+                            let has_nonzero_bytes = alloc
+                                .raw_bytes()
+                                .ok()
+                                .map(|bytes| bytes.iter().any(|&b| b != 0))
+                                .unwrap_or(false);
+                            has_provenance || has_nonzero_bytes
+                        }
+                        ConstantKind::Ty(_) => {
+                            // Promoted constants (like &(8..16)) are Ty variants
+                            // These contain the actual struct data
+                            true
+                        }
+                        _ => false,
+                    }
+                } else {
+                    false
+                };
+
+                if has_struct_data {
+                    // This is a reference to a constant struct (like &(8..16))
+
+                    // Create the struct constant, then use mir.ref to get a pointer
+                    let (struct_val, last_op) = translate_struct_constant(
+                        ctx,
+                        constant,
+                        &rust_ty,
+                        pointee_ty,
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                    )?;
+
+                    // Now create mir.ref to get a pointer to the struct
+                    use dialect_mir::ops::MirRefOp;
+                    let ref_op = Operation::new(
+                        ctx,
+                        MirRefOp::get_concrete_op_info(),
+                        vec![const_ty_ptr], // Result is pointer to struct
+                        vec![struct_val],   // Operand is the struct value
+                        vec![],
+                        0,
+                    );
+                    ref_op.deref_mut(ctx).set_loc(loc);
+
+                    let mir_ref = MirRefOp::new(ref_op);
+
+                    mir_ref
+                        .set_attr_mutable(ctx, dialect_mir::attributes::MutabilityAttr(is_mutable));
+                    mir_ref.set_pointer_kind_authority(
+                        ctx,
+                        MirPointerKindAuthorityAttr::StaticAddress,
+                    );
+
+                    if let Some(prev) = last_op {
+                        mir_ref.get_operation().insert_after(ctx, prev);
+                    } else {
+                        mir_ref.get_operation().insert_at_front(block_ptr, ctx);
+                    }
+
+                    let ptr_val = mir_ref.get_operation().deref(ctx).get_result(0);
+                    return Ok((ptr_val, Some(mir_ref.get_operation())));
+                }
+
+                // Reference to a non-struct promoted constant (issue #132).
+                //
+                // Under -O, MIR const-folds e.g. the `None` arm of
+                // `Option<&u32>::unwrap_or(&77)` into a constant of type `&u32`
+                // whose data bytes are a pointer placeholder and whose
+                // provenance entry names the allocation holding the literal
+                // `77`. Struct pointees were already handled above; follow the
+                // provenance for every other pointee type too, materialize the
+                // pointee through the shared constant-from-bytes path, and take
+                // its address with mir.ref (mem2reg/lowering turn that into an
+                // alloca + store + address; sound because promoted constants
+                // are immutable).
+                let backing_alloc: Option<&rustc_public::ty::Allocation> =
+                    match constant.const_.kind() {
+                        ConstantKind::Allocated(alloc) => Some(alloc),
+                        ConstantKind::Ty(ty_const) => match ty_const.kind() {
+                            rustc_public::ty::TyConstKind::Value(_, alloc) => Some(alloc),
+                            _ => None,
+                        },
+                        _ => None,
+                    };
+
+                if let Some(alloc) = backing_alloc
+                    && let Some(&(prov_pos, prov)) = alloc.provenance.ptrs.first()
+                {
+                    use rustc_public::mir::alloc::GlobalAlloc;
+                    let alloc_id = prov.0;
+
+                    // The pointer's own data bytes encode the byte offset into
+                    // the target allocation (zero for plain promoted literals
+                    // like `&77`). The struct/array provenance branches assume
+                    // offset zero; here the slice below honors a non-zero
+                    // offset, and an unreadable offset is a hard error rather
+                    // than a silently wrong address.
+                    let ptr_width =
+                        rustc_public::target::MachineInfo::target_pointer_width().bytes();
+                    let target_offset = alloc
+                        .read_partial_uint(prov_pos..prov_pos + ptr_width)
+                        .map_err(|e| {
+                            input_error_noloc!(TranslationErr::unsupported(format!(
+                                "Failed to read pointer constant provenance offset: {:?}",
+                                e
+                            )))
+                        })? as usize;
+
+                    // The pointee is decoded from raw bytes below, with no
+                    // provenance map to resolve pointers nested inside it, so
+                    // a pointee that itself contains relocations must fail
+                    // loudly before its placeholder bytes decode as addresses.
+                    let reject_pointee_relocations = |relocations: usize| -> TranslationResult<()> {
+                        if relocations != 0 {
+                            return input_err!(
+                                loc.clone(),
+                                TranslationErr::unsupported(format!(
+                                    "Promoted constant's pointee contains {relocations} pointer \
+                                         relocation(s); cuda-oxide cannot yet preserve nested \
+                                         pointer provenance"
+                                ))
+                            );
+                        }
+                        Ok(())
+                    };
+                    let target_bytes: Vec<u8> = match GlobalAlloc::from(alloc_id) {
+                        GlobalAlloc::Memory(target_alloc) => {
+                            reject_pointee_relocations(target_alloc.provenance.ptrs.len())?;
+                            target_alloc.raw_bytes().ok().unwrap_or_else(|| {
+                                target_alloc
+                                    .bytes
+                                    .iter()
+                                    .map(|opt: &Option<u8>| opt.unwrap_or(0))
+                                    .collect::<Vec<u8>>()
+                            })
+                        }
+                        GlobalAlloc::Static(static_def) => {
+                            let target_alloc = static_def.eval_initializer().map_err(|e| {
+                                input_error_noloc!(TranslationErr::unsupported(format!(
+                                    "Failed to evaluate static initializer for pointer constant: {:?}",
+                                    e
+                                )))
+                            })?;
+                            reject_pointee_relocations(target_alloc.provenance.ptrs.len())?;
+                            target_alloc.raw_bytes().ok().unwrap_or_else(|| {
+                                target_alloc
+                                    .bytes
+                                    .iter()
+                                    .map(|opt: &Option<u8>| opt.unwrap_or(0))
+                                    .collect::<Vec<u8>>()
+                            })
+                        }
+                        other => {
+                            return input_err!(
+                                loc,
+                                TranslationErr::unsupported(format!(
+                                    "Pointer constant provenance points to non-memory allocation: {:?}",
+                                    other
+                                ))
+                            );
+                        }
+                    };
+
+                    if target_offset > target_bytes.len() {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "Pointer constant provenance offset {} exceeds target allocation size {}",
+                                target_offset,
+                                target_bytes.len()
+                            ))
+                        );
+                    }
+
+                    // The shared materializer needs the pointee's Rust type for
+                    // enum-layout queries and ZST detection.
+                    let Some((pointee_rust_ty, _)) = get_static_pointer_info(&rust_ty) else {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "Pointer constant with provenance has unsupported Rust type: {:?}",
+                                rust_ty
+                            ))
+                        );
+                    };
+
+                    let (pointee_val, last_op) = translate_constant_value_from_bytes(
+                        ctx,
+                        &pointee_rust_ty,
+                        pointee_ty,
+                        &target_bytes[target_offset..],
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                    )?;
+
+                    // Take the address of the materialized value, exactly like
+                    // the struct branch above.
+                    let ref_op = Operation::new(
+                        ctx,
+                        MirRefOp::get_concrete_op_info(),
+                        vec![const_ty_ptr], // Result is pointer to the pointee
+                        vec![pointee_val],  // Operand is the materialized value
+                        vec![],
+                        0,
+                    );
+                    ref_op.deref_mut(ctx).set_loc(loc);
+
+                    let mir_ref = MirRefOp::new(ref_op);
+                    mir_ref
+                        .set_attr_mutable(ctx, dialect_mir::attributes::MutabilityAttr(is_mutable));
+                    mir_ref.set_pointer_kind_authority(
+                        ctx,
+                        MirPointerKindAuthorityAttr::StaticAddress,
+                    );
+
+                    if let Some(prev) = last_op {
+                        mir_ref.get_operation().insert_after(ctx, prev);
+                    } else {
+                        mir_ref.get_operation().insert_at_front(block_ptr, ctx);
+                    }
+
+                    let ptr_val = mir_ref.get_operation().deref(ctx).get_result(0);
+                    return Ok((ptr_val, Some(mir_ref.get_operation())));
+                }
+
+                // Raw pointer constant (like core::ptr::null()).
+                //
+                // Only reachable for constants WITHOUT provenance (true null or
+                // int-to-ptr values); provenance-carrying constants returned
+                // above. Create an integer constant with the pointer value
+                // (0 for null), then convert it to a pointer type using
+                // MirCastOp
+                use dialect_mir::ops::MirCastOp;
+
+                // No provenance, so the data bytes ARE the address. Read the
+                // first pointer-width bytes as a target-endian uint:
+                //
+                //   bytes: [00 00 00 00 00 00 00 00] -> 0x00 (null)
+                //   bytes: [2a 00 00 00 00 00 00 00] -> 0x2a (without_provenance(42))
+                //
+                // A constant with no backing allocation, too few bytes, or an
+                // uninit byte in the range has no readable address; post-mono
+                // MIR should never produce that here, so fail loudly instead
+                // of defaulting to null.
+                let Some(alloc) = backing_alloc else {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "raw pointer constant has no backing allocation to read an \
+                             address from (constant kind: {:?})",
+                            constant.const_.kind()
+                        ))
+                    );
+                };
+                debug_assert!(
+                    alloc.provenance.ptrs.is_empty(),
+                    "provenance-carrying pointer constants must return earlier"
+                );
+                let ptr_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+                let ptr_val = alloc.read_partial_uint(0..ptr_width).map_err(|e| {
+                    input_error_noloc!(TranslationErr::unsupported(format!(
+                        "raw pointer constant needs {ptr_width} initialized address \
+                         bytes, but reading them failed: {e:?}"
+                    )))
+                })? as u64;
+
+                // Create integer constant (i64) for the pointer value
+                let i64_ty = pliron::builtin::types::IntegerType::get(
+                    ctx,
+                    64,
+                    pliron::builtin::types::Signedness::Signless,
+                );
+                let apint = APInt::from_u64(ptr_val, NonZeroUsize::new(64).unwrap());
+                let int_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, apint);
+
+                use dialect_mir::ops::MirConstantOp;
+                let int_op = Operation::new(
+                    ctx,
+                    MirConstantOp::get_concrete_op_info(),
+                    vec![i64_ty.into()],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                int_op.deref_mut(ctx).set_loc(loc.clone());
+
+                let const_op = MirConstantOp::new(int_op);
+                const_op.set_attr_value(ctx, int_attr);
+
+                if let Some(prev) = prev_op {
+                    const_op.get_operation().insert_after(ctx, prev);
+                } else {
+                    const_op.get_operation().insert_at_front(block_ptr, ctx);
+                }
+
+                let int_val = const_op.get_operation().deref(ctx).get_result(0);
+
+                // Cast integer to pointer type using MirCastOp
+                let cast_op = Operation::new(
+                    ctx,
+                    MirCastOp::get_concrete_op_info(),
+                    vec![const_ty_ptr], // Result is the pointer type
+                    vec![int_val],      // Operand is the integer value
+                    vec![],
+                    0,
+                );
+                cast_op.deref_mut(ctx).set_loc(loc);
+                let cast = MirCastOp::new(cast_op);
+                cast.set_attr_cast_kind(ctx, MirCastKindAttr::PointerWithExposedProvenance);
+                if dialect_mir::types::type_contains_concrete_pointer_kind(ctx, const_ty_ptr) {
+                    cast.set_pointer_kind_authority(
+                        ctx,
+                        MirPointerKindAuthorityAttr::StaticAddress,
+                    );
+                }
+
+                cast_op.insert_after(ctx, const_op.get_operation());
+
+                let ptr_val_result = cast_op.deref(ctx).get_result(0);
+
+                Ok((ptr_val_result, Some(cast_op)))
+            } else if const_ty_ptr.deref(ctx).is::<IntegerType>() {
+                // Integer constant
+                let (width_val, signedness) = {
+                    let const_ty_obj = const_ty_ptr.deref(ctx);
+                    let int_ty = const_ty_obj
+                        .downcast_ref::<IntegerType>()
+                        .expect("already checked is::<IntegerType>()");
+                    (int_ty.width(), int_ty.signedness())
+                };
+
+                let byte_size = (width_val as usize).div_ceil(8);
+
+                // Walk to the backing allocation directly instead of going
+                // through `constant_bytes`: that helper zero-fills uninit
+                // bytes, and an integer's value bytes must all be present.
+                //
+                //   bytes: [ff 7f] -> 0x7fff  (fine)
+                //   bytes: [-- 7f] -> error   (uninit byte, not 0x7f00)
+                //
+                // No fallback: a constant we cannot read here is a compiler
+                // bug, never a zero.
+                let alloc = match constant.const_.kind() {
+                    ConstantKind::Allocated(alloc) => alloc,
+                    ConstantKind::Ty(ty_const) => match ty_const.kind() {
+                        rustc_public::ty::TyConstKind::Value(_, alloc) => alloc,
+                        other => {
+                            return input_err!(
+                                loc,
+                                TranslationErr::unsupported(format!(
+                                    "integer constant is not an evaluated value \
+                                     (TyConstKind::{other:?}), so its bytes cannot be read"
+                                ))
+                            );
+                        }
+                    },
+                    other => {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "integer constant has no byte-backed allocation \
+                                 (constant kind: {other:?})"
+                            ))
+                        );
+                    }
+                };
+                if !alloc.provenance.ptrs.is_empty() {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(
+                            "integer constant carries pointer provenance; its bytes are \
+                             a relocation placeholder, not a number",
+                        )
+                    );
+                }
+                if alloc.bytes.len() < byte_size {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "integer constant has {} data bytes, expected at least \
+                             {byte_size} for i{width_val}",
+                            alloc.bytes.len()
+                        ))
+                    );
+                }
+                let int_val = alloc.read_partial_uint(0..byte_size).map_err(|e| {
+                    input_error_noloc!(TranslationErr::unsupported(format!(
+                        "integer constant has uninitialized bytes in its value range: {e:?}"
+                    )))
+                })?;
+
+                let width = NonZeroUsize::new(width_val as usize).unwrap();
+                let apint = APInt::from_u128(int_val, width);
+
+                let int_attr = pliron::builtin::attributes::IntegerAttr::new(
+                    pliron::builtin::types::IntegerType::get(ctx, width_val, signedness),
+                    apint,
+                );
+
+                use dialect_mir::ops::MirConstantOp;
+                let op = Operation::new(
+                    ctx,
+                    MirConstantOp::get_concrete_op_info(),
+                    vec![const_ty_ptr],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                op.deref_mut(ctx).set_loc(loc);
+
+                let const_op = MirConstantOp::new(op);
+                const_op.set_attr_value(ctx, int_attr);
+
+                if let Some(prev) = prev_op {
+                    const_op.get_operation().insert_after(ctx, prev);
+                } else {
+                    const_op.get_operation().insert_at_front(block_ptr, ctx);
+                }
+
+                let val = const_op.get_operation().deref(ctx).get_result(0);
+
+                Ok((val, Some(const_op.get_operation())))
+            } else {
+                // No matching type handler — report what we got so it's clear what needs support.
+                let pliron_ty_dbg = format!("{:?}", const_ty_ptr.deref(ctx));
+                Err(input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Unsupported constant type in translate_constant.\n\
+                     \n  Rust type : {:?}\
+                     \n  pliron type: {}\
+                     \n  const repr : {}\
+                     \n\
+                     \nThe type dispatch (ZST -> ptr_to_array -> array -> struct -> tuple -> enum -> union -> float -> pointer -> integer)\n\
+                     did not match this constant. A new handler may need to be added.",
+                    rust_ty, pliron_ty_dbg, const_str
+                ))))
+            }
+        }
+        mir::Operand::RuntimeChecks(_) => {
+            // RuntimeChecks variants (UbChecks, ContractChecks, OverflowChecks)
+            // evaluate to `false` on GPU -- runtime safety checks are disabled.
+            //
+            // Emits a `mir.constant false : i1` and inserts it into the current
+            // block. The op *must* be linked before returning; callers use the
+            // returned `last_op` as the insertion point for subsequent ops.
+            use dialect_mir::ops::MirConstantOp;
+            use pliron::builtin::attributes::IntegerAttr;
+            use pliron::builtin::types::{IntegerType, Signedness};
+            use pliron::utils::apint::APInt;
+
+            let bool_ty: TypeHandle = IntegerType::get(ctx, 1, Signedness::Signless).into();
+            let value = APInt::from_u64(
+                u64::from(crate::DEVICE_RUNTIME_CHECKS_VALUE),
+                std::num::NonZeroUsize::new(1).unwrap(),
+            );
+            let const_attr =
+                IntegerAttr::new(IntegerType::get(ctx, 1, Signedness::Signless), value);
+
+            let op = Operation::new(
+                ctx,
+                MirConstantOp::get_concrete_op_info(),
+                vec![bool_ty],
+                vec![],
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc);
+
+            let const_op = MirConstantOp::new(op);
+            const_op.set_attr_value(ctx, const_attr);
+
+            match prev_op {
+                Some(p) => op.insert_after(ctx, p),
+                None => op.insert_at_front(block_ptr, ctx),
+            }
+
+            let val = const_op.get_operation().deref(ctx).get_result(0);
+
+            Ok((val, Some(const_op.get_operation())))
+        }
+    }
+}
+
+/// Check if a type is a pointer to cuda-device's SharedArray.
+fn is_shared_array_pointer(ty: &rustc_public::ty::Ty) -> bool {
+    use rustc_public::ty::{RigidTy, TyKind};
+
+    match ty.kind() {
+        TyKind::RigidTy(RigidTy::RawPtr(pointee_ty, _)) => {
+            // Check if the pointee is SharedArray
+            match pointee_ty.kind() {
+                TyKind::RigidTy(RigidTy::Adt(adt_def, _)) => {
+                    types::is_cuda_device_adt(&adt_def, "SharedArray")
+                }
+                _ => false,
+            }
+        }
+        _ => false,
+    }
+}
+
+/// Check if a type is a pointer to cuda-device's Barrier (mbarrier state in
+/// shared memory).
+fn is_barrier_pointer(ty: &rustc_public::ty::Ty) -> bool {
+    use rustc_public::ty::{RigidTy, TyKind};
+
+    match ty.kind() {
+        TyKind::RigidTy(RigidTy::RawPtr(pointee_ty, _)) => {
+            // Check if the pointee is Barrier
+            match pointee_ty.kind() {
+                TyKind::RigidTy(RigidTy::Adt(adt_def, _)) => {
+                    types::is_cuda_device_adt(&adt_def, "Barrier")
+                }
+                _ => false,
+            }
+        }
+        _ => false,
+    }
+}
+
+/// Extract element type, size, and alignment from a pointer to SharedArray<T, N, ALIGN>.
+/// Returns (element_type, size, alignment) where alignment is 0 for natural alignment.
+fn extract_shared_array_info(
+    ctx: &mut Context,
+    ty: &rustc_public::ty::Ty,
+) -> TranslationResult<(pliron::r#type::TypeHandle, usize, usize)> {
+    use rustc_public::ty::{GenericArgKind, RigidTy, TyKind};
+
+    match ty.kind() {
+        TyKind::RigidTy(RigidTy::RawPtr(pointee_ty, _)) => {
+            match pointee_ty.kind() {
+                TyKind::RigidTy(RigidTy::Adt(adt_def, substs)) => {
+                    if !types::is_cuda_device_adt(&adt_def, "SharedArray") {
+                        return input_err_noloc!(TranslationErr::unsupported(format!(
+                            "Expected cuda_device::SharedArray, got {}",
+                            adt_def.trimmed_name()
+                        )));
+                    }
+
+                    let generic_args = &substs.0;
+
+                    // SharedArray substs arrive in declaration order, with
+                    // the ALIGN default already materialized by rustc:
+                    //
+                    //   SharedArray<T, N, ALIGN = 0>
+                    //     [0] T      type
+                    //     [1] N      const usize (element count)
+                    //     [2] ALIGN  const usize (0 = natural alignment)
+                    //
+                    // Reads are positional on purpose: if N fails to
+                    // evaluate that's an error, never "slide over and read
+                    // ALIGN as N". If cuda-device ever reorders these
+                    // generics, this read must change in the same commit.
+                    debug_assert!(
+                        generic_args.len() == 2 || generic_args.len() == 3,
+                        "SharedArray is declared <T, const N, const ALIGN = 0>; \
+                         got {} generic args",
+                        generic_args.len()
+                    );
+
+                    let Some(GenericArgKind::Type(elem_ty)) = generic_args.first() else {
+                        return input_err_noloc!(TranslationErr::unsupported(
+                            "SharedArray substs missing the element type at position 0"
+                        ));
+                    };
+
+                    let Some(GenericArgKind::Const(n_const)) = generic_args.get(1) else {
+                        return input_err_noloc!(TranslationErr::unsupported(
+                            "SharedArray substs missing the N const generic at position 1"
+                        ));
+                    };
+                    let size = facts::eval_usize_const(n_const, "SharedArray N", None)? as usize;
+
+                    // ALIGN = 0 means natural alignment (the declaration
+                    // default). Only a genuinely two-generic SharedArray may
+                    // omit it; a present-but-unreadable position 2 is an
+                    // error, silently dropping a user-requested
+                    // over-alignment would miscompile.
+                    let alignment = match generic_args.get(2) {
+                        Some(GenericArgKind::Const(align_const)) => {
+                            facts::eval_usize_const(align_const, "SharedArray ALIGN", None)?
+                                as usize
+                        }
+                        Some(_) => {
+                            return input_err_noloc!(TranslationErr::unsupported(
+                                "SharedArray substs position 2 is not the ALIGN const generic"
+                            ));
+                        }
+                        None => 0,
+                    };
+
+                    let translated_elem_ty = types::translate_type(ctx, elem_ty)?;
+                    Ok((translated_elem_ty, size, alignment))
+                }
+                _ => input_err_noloc!(TranslationErr::unsupported(
+                    "Expected ADT type for SharedArray"
+                )),
+            }
+        }
+        _ => input_err_noloc!(TranslationErr::unsupported("Expected raw pointer type")),
+    }
+}
diff --git a/crates/mir-importer/src/translator/rvalue/place_addr.rs b/crates/mir-importer/src/translator/rvalue/place_addr.rs
new file mode 100644
index 0000000000..0b09daa48c
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/place_addr.rs
@@ -0,0 +1,1454 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! [`translate_place_address`] and the stateful slot projection loop.
+
+use super::place_read::translate_place;
+use super::pointee::{
+    PointeeKind, emit_indexed_element_addr, erased_slice_data_pointer_type, is_empty_tuple_type,
+    mir_ptr_pointee, pointer_pointee_kind, projected_pointer_type, slice_like_element_type,
+};
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::facts;
+use crate::translator::types;
+use crate::translator::values::ValueMap;
+use dialect_mir::attributes::MirCastKindAttr;
+use dialect_mir::ops::{
+    MirCastOp, MirConstantOp, MirConstructArrayOp, MirExtractFieldOp, MirLoadOp, MirPtrOffsetOp,
+    MirSubOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::printable::Printable;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use pliron::{input_err, input_error_noloc};
+use rustc_public::mir;
+use rustc_public_bridge::IndexedVal;
+use std::num::NonZeroUsize;
+
+/// Compute the in-memory address of `place` by walking its FULL projection
+/// list starting from `place.local`'s alloca slot.
+///
+/// Single entry point for `Rvalue::Ref` / `Rvalue::AddressOf` address
+/// materialisation: `&(*ptr)` loads the pointer, `&(*ptr).field` adds a
+/// field address, `&x.arr[i]` adds an element address, and arbitrary
+/// combinations compose.
+///
+/// Returns `Ok(None)` when the local has no slot (ZST / ghost locals) or
+/// when the projection chain contains an element
+/// [`translate_place_addr_from_slot`] cannot lower. The caller decides
+/// whether a value-copy fallback is sound (shared borrows: reads through a
+/// copy are fine) or the construct must be rejected (mutable borrows / raw
+/// mut pointers: writes through a copy are silently lost).
+///
+/// Also used by statement translation to compute the destination address
+/// of projected assignments (indexed `(*ptr)[i]` writes and 3+ element
+/// projection chains), where the same "walk the chain, then act through
+/// the address" logic applies with a store instead of a borrow.
+#[allow(clippy::too_many_arguments)]
+pub(crate) fn translate_place_address(
+    ctx: &mut Context,
+    body: &mir::Body,
+    value_map: &ValueMap,
+    place: &mir::Place,
+    is_mutable: bool,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<Option<(Value, Option<Ptr<Operation>>)>> {
+    let Some(slot) = value_map.get_slot(place.local) else {
+        return Ok(None);
+    };
+    translate_place_addr_from_slot(
+        ctx,
+        body,
+        value_map,
+        slot,
+        &place.projection,
+        is_mutable,
+        block_ptr,
+        prev_op,
+        loc,
+    )
+}
+
+/// Whether an enum payload's SEMANTIC type needs canonical-storage coercion
+/// when its bytes live inside enum storage.
+///
+/// Mirrors what mir-lower's `enum_payload_storage_type` rewrites: `bool`
+/// leaves are stored as canonical `i8` bytes and shared-memory pointer
+/// leaves are stored as CUDA generic pointers, recursively through
+/// struct/tuple/array nesting. An address of such a payload cannot carry
+/// that coercion (the address escapes, and loads and stores through it are
+/// typed with the SEMANTIC type), so the address walker uses this predicate
+/// to punt SHARED borrows back to the sound value-copy fallback.
+///
+/// Layering: this predicate is allowed to be conservative. A nested enum
+/// payload, for example, is treated as needing coercion whenever any of its
+/// own payload fields does, without proving the leaf survives into the
+/// nested enum's converted storage. Over-punting only costs a copy for a
+/// shared borrow and stays sound. mir-lower's canonical-storage gate on
+/// `mir.field_addr` remains the fail-closed authority, so a miss here still
+/// errors loudly instead of miscompiling.
+pub(crate) fn enum_payload_needs_storage_coercion_pub(ctx: &Context, ty: TypeHandle) -> bool {
+    enum_payload_needs_storage_coercion(ctx, ty)
+}
+
+fn enum_payload_needs_storage_coercion(ctx: &Context, ty: TypeHandle) -> bool {
+    // Bool leaf: semantic i1, canonical i8 byte in enum storage.
+    if let Some(integer) = ty.deref(ctx).downcast_ref::<IntegerType>() {
+        return integer.width() == 1;
+    }
+    // Pointer leaf: shared-memory pointers are stored as generic pointers
+    // because their physical width is target-mode dependent.
+    if let Some(pointer) = ty
+        .deref(ctx)
+        .downcast_ref::<dialect_mir::types::MirPtrType>()
+    {
+        return pointer.address_space() == dialect_mir::types::address_space::SHARED;
+    }
+    // Aggregates: recurse through every leaf position the storage rewrite
+    // visits. Collect the children first so the type `Ref` is dropped
+    // before recursing.
+    let children: Vec<TypeHandle> = {
+        let ty_ref = ty.deref(ctx);
+        if let Some(tuple) = ty_ref.downcast_ref::<dialect_mir::types::MirTupleType>() {
+            tuple.types.clone()
+        } else if let Some(struct_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirStructType>() {
+            struct_ty.field_types.clone()
+        } else if let Some(array) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
+            vec![array.element_ty]
+        } else if let Some(enum_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirEnumType>() {
+            enum_ty.all_field_types.clone()
+        } else {
+            return false;
+        }
+    };
+    children
+        .into_iter()
+        .any(|child| enum_payload_needs_storage_coercion(ctx, child))
+}
+
+/// Extract the runtime element count from a slice-shaped fat value.
+///
+/// CUDA Oxide models slices as `(data_ptr, len)`, with the length in field 1.
+/// The extraction must use the fat value itself: inferring a length from the
+/// data pointer's pointee type is wrong for slices whose elements are arrays.
+pub(super) fn emit_slice_len_extract(
+    ctx: &mut Context,
+    slice_value: Value,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> (Value, Ptr<Operation>) {
+    let usize_ty = types::get_usize_type(ctx);
+    let op = Operation::new(
+        ctx,
+        MirExtractFieldOp::get_concrete_op_info(),
+        vec![usize_ty.to_handle()],
+        vec![slice_value],
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc);
+    MirExtractFieldOp::new(op).set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(1));
+    match prev_op {
+        Some(prev) => op.insert_after(ctx, prev),
+        None => op.insert_at_front(block_ptr, ctx),
+    }
+    (op.deref(ctx).get_result(0), op)
+}
+
+/// Materialize the zero-based index for
+/// `ConstantIndex { offset, from_end: true }` on a runtime-length slice.
+///
+/// rustc defines the offset as 1-based from the end, so the index is
+/// `slice_len - offset`. The MIR pattern-length test dominates this place,
+/// therefore the subtraction cannot underflow on an executed path.
+fn emit_from_end_slice_index(
+    ctx: &mut Context,
+    slice_len: Value,
+    offset: u64,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Ptr<Operation>)> {
+    let usize_ty = types::get_usize_type(ctx);
+    let usize_handle = usize_ty.to_handle();
+    if slice_len.get_type(ctx) != usize_handle {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "from-end ConstantIndex expected slice length of type {}, got {}",
+                usize_handle.disp(ctx),
+                slice_len.get_type(ctx).disp(ctx)
+            ))
+        );
+    }
+
+    let width = NonZeroUsize::new(
+        usize::try_from(usize_ty.deref(ctx).width()).expect("usize width must fit usize"),
+    )
+    .expect("usize integer width must be non-zero");
+    let offset_attr =
+        pliron::builtin::attributes::IntegerAttr::new(usize_ty, APInt::from_u64(offset, width));
+    let offset_op = Operation::new(
+        ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![usize_handle],
+        vec![],
+        vec![],
+        0,
+    );
+    offset_op.deref_mut(ctx).set_loc(loc.clone());
+    MirConstantOp::new(offset_op).set_attr_value(ctx, offset_attr);
+    match prev_op {
+        Some(prev) => offset_op.insert_after(ctx, prev),
+        None => offset_op.insert_at_front(block_ptr, ctx),
+    }
+    let offset_value = offset_op.deref(ctx).get_result(0);
+
+    let sub_op = Operation::new(
+        ctx,
+        MirSubOp::get_concrete_op_info(),
+        vec![usize_handle],
+        vec![slice_len, offset_value],
+        vec![],
+        0,
+    );
+    sub_op.deref_mut(ctx).set_loc(loc);
+    sub_op.insert_after(ctx, offset_op);
+
+    Ok((sub_op.deref(ctx).get_result(0), sub_op))
+}
+
+/// Emit a `usize` constant and insert it after `prev_op`.
+fn emit_usize_constant(
+    ctx: &mut Context,
+    value: u64,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> (Value, Ptr<Operation>) {
+    use pliron::builtin::attributes::IntegerAttr;
+
+    let usize_ty = types::get_usize_type(ctx);
+    let attr = IntegerAttr::new(
+        IntegerType::get(ctx, 64, Signedness::Unsigned),
+        APInt::from_u64(value, NonZeroUsize::new(64).unwrap()),
+    );
+    let op = Operation::new(
+        ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![usize_ty.to_handle()],
+        vec![],
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc);
+    MirConstantOp::new(op).set_attr_value(ctx, attr);
+    match prev_op {
+        Some(prev) => op.insert_after(ctx, prev),
+        None => op.insert_at_front(block_ptr, ctx),
+    }
+    (op.deref(ctx).get_result(0), op)
+}
+
+/// Compute the address of a sized array subslice.
+///
+/// For `Subslice { from, to, from_end: false }`, rustc codegen takes the
+/// address of element `from` and re-types that address as `[T; to - from]`.
+#[allow(clippy::too_many_arguments)]
+fn emit_array_subslice_address(
+    ctx: &mut Context,
+    array_ptr: Value,
+    from: u64,
+    to: u64,
+    is_mutable: bool,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Ptr<Operation>)> {
+    use dialect_mir::ops::MirArrayElementAddrOp;
+
+    let (element_ty, array_len) = {
+        let ptr_ty = array_ptr.get_type(ctx);
+        let ptr_ty = ptr_ty.deref(ctx);
+        let Some(ptr_ty) = ptr_ty.downcast_ref::<dialect_mir::types::MirPtrType>() else {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported("Subslice base is not a pointer".to_string())
+            );
+        };
+        let array_ty = ptr_ty.pointee.deref(ctx);
+        let Some(array_ty) = array_ty.downcast_ref::<dialect_mir::types::MirArrayType>() else {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(
+                    "array Subslice base pointer does not point to MirArrayType".to_string()
+                )
+            );
+        };
+        (array_ty.element_type(), array_ty.size())
+    };
+
+    let Some(projected_len) = to.checked_sub(from) else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "array Subslice has inverted bounds: from={from}, to={to}"
+            ))
+        );
+    };
+    if to > array_len {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "array Subslice end {to} exceeds array length {array_len}"
+            ))
+        );
+    }
+
+    let (from_value, from_op) = emit_usize_constant(ctx, from, block_ptr, prev_op, loc.clone());
+    let elem_ptr_ty = projected_pointer_type(
+        ctx,
+        array_ptr.get_type(ctx),
+        element_ty,
+        /* legacy requested mutability, ignored */ is_mutable,
+    )
+    .expect("array subslice base must be a MirPtrType");
+    let addr_op = Operation::new(
+        ctx,
+        MirArrayElementAddrOp::get_concrete_op_info(),
+        vec![elem_ptr_ty],
+        vec![array_ptr, from_value],
+        vec![],
+        0,
+    );
+    addr_op.deref_mut(ctx).set_loc(loc.clone());
+    addr_op.insert_after(ctx, from_op);
+    let elem_ptr = addr_op.deref(ctx).get_result(0);
+
+    let projected_array_ty: TypeHandle =
+        dialect_mir::types::MirArrayType::get(ctx, element_ty, projected_len).into();
+    let projected_ptr_ty = projected_pointer_type(
+        ctx,
+        elem_ptr.get_type(ctx),
+        projected_array_ty,
+        /* legacy requested mutability, ignored */ is_mutable,
+    )
+    .expect("array subslice element address must be a MirPtrType");
+    let cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![projected_ptr_ty],
+        vec![elem_ptr],
+        vec![],
+        0,
+    );
+    cast_op.deref_mut(ctx).set_loc(loc);
+    MirCastOp::new(cast_op).set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+    cast_op.insert_after(ctx, addr_op);
+
+    Ok((cast_op.deref(ctx).get_result(0), cast_op))
+}
+
+/// Build the fat value for a slice subslice from the original fat slice.
+///
+/// rustc's semantics for `from_end=true` are
+/// `slice[from..slice.len() - to]`: advance the data pointer by `from` and
+/// replace the metadata with `len - (from + to)`.
+#[allow(clippy::too_many_arguments)]
+pub(super) fn emit_slice_subslice_value(
+    ctx: &mut Context,
+    slice_value: Value,
+    element_ty: TypeHandle,
+    is_mutable: bool,
+    from: u64,
+    to: u64,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Ptr<Operation>)> {
+    // Subslice is a projection of an existing fat pointer, not a new borrow.
+    // Preserve the source pointer category; callers that explicitly form a
+    // reborrow/raw address normalize the terminal result to their new Rust
+    // type afterwards. A non-slice carrier keeps the caller's mutability with
+    // Erased provenance.
+    let origin = slice_value
+        .get_type(ctx)
+        .deref(ctx)
+        .downcast_ref::<dialect_mir::types::MirSliceType>()
+        .map(facts::pointer_origin_of_slice_carrier);
+
+    use dialect_mir::ops::MirConstructSliceOp;
+
+    let Some(trim) = from.checked_add(to) else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported("Subslice bounds overflow usize metadata".to_string())
+        );
+    };
+
+    let data_ptr_ty: TypeHandle = match origin {
+        Some(origin) => facts::mint_generic_ptr_type(ctx, element_ty, origin).into(),
+        None => dialect_mir::types::MirPtrType::get_generic(ctx, element_ty, is_mutable).into(),
+    };
+    let extract_ptr = Operation::new(
+        ctx,
+        MirExtractFieldOp::get_concrete_op_info(),
+        vec![data_ptr_ty],
+        vec![slice_value],
+        vec![],
+        0,
+    );
+    extract_ptr.deref_mut(ctx).set_loc(loc.clone());
+    MirExtractFieldOp::new(extract_ptr)
+        .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
+    match prev_op {
+        Some(prev) => extract_ptr.insert_after(ctx, prev),
+        None => extract_ptr.insert_at_front(block_ptr, ctx),
+    }
+    let data_ptr = extract_ptr.deref(ctx).get_result(0);
+
+    let usize_ty = types::get_usize_type(ctx);
+    let extract_len = Operation::new(
+        ctx,
+        MirExtractFieldOp::get_concrete_op_info(),
+        vec![usize_ty.to_handle()],
+        vec![slice_value],
+        vec![],
+        0,
+    );
+    extract_len.deref_mut(ctx).set_loc(loc.clone());
+    MirExtractFieldOp::new(extract_len)
+        .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(1));
+    extract_len.insert_after(ctx, extract_ptr);
+    let len = extract_len.deref(ctx).get_result(0);
+
+    let (from_value, from_op) =
+        emit_usize_constant(ctx, from, block_ptr, Some(extract_len), loc.clone());
+    let offset_op = Operation::new(
+        ctx,
+        MirPtrOffsetOp::get_concrete_op_info(),
+        vec![data_ptr_ty],
+        vec![data_ptr, from_value],
+        vec![],
+        0,
+    );
+    offset_op.deref_mut(ctx).set_loc(loc.clone());
+    offset_op.insert_after(ctx, from_op);
+    let new_data = offset_op.deref(ctx).get_result(0);
+
+    let (trim_value, trim_op) =
+        emit_usize_constant(ctx, trim, block_ptr, Some(offset_op), loc.clone());
+    let sub_op = Operation::new(
+        ctx,
+        MirSubOp::get_concrete_op_info(),
+        vec![usize_ty.to_handle()],
+        vec![len, trim_value],
+        vec![],
+        0,
+    );
+    sub_op.deref_mut(ctx).set_loc(loc.clone());
+    sub_op.insert_after(ctx, trim_op);
+    let new_len = sub_op.deref(ctx).get_result(0);
+
+    let slice_ty = match origin {
+        Some(origin) => facts::mint_slice_type(ctx, element_ty, origin),
+        None => dialect_mir::types::MirSliceType::get_with_mutability(ctx, element_ty, is_mutable),
+    };
+    let construct = Operation::new(
+        ctx,
+        MirConstructSliceOp::get_concrete_op_info(),
+        vec![slice_ty.into()],
+        vec![new_data, new_len],
+        vec![],
+        0,
+    );
+    construct.deref_mut(ctx).set_loc(loc);
+    construct.insert_after(ctx, sub_op);
+
+    Ok((construct.deref(ctx).get_result(0), construct))
+}
+
+/// Materialize a sized array subslice from an SSA array value.
+pub(super) fn emit_array_subslice_value(
+    ctx: &mut Context,
+    array_value: Value,
+    from: u64,
+    to: u64,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let (element_ty, array_len) = {
+        let array_ty = array_value.get_type(ctx);
+        let array_ty = array_ty.deref(ctx);
+        let Some(array_ty) = array_ty.downcast_ref::<dialect_mir::types::MirArrayType>() else {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported("Subslice value base is not MirArrayType".to_string())
+            );
+        };
+        (array_ty.element_type(), array_ty.size())
+    };
+
+    let Some(projected_len) = to.checked_sub(from) else {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "array Subslice has inverted bounds: from={from}, to={to}"
+            ))
+        );
+    };
+    if to > array_len {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "array Subslice end {to} exceeds array length {array_len}"
+            ))
+        );
+    }
+
+    let mut elements = Vec::with_capacity(projected_len as usize);
+    let mut current_prev = prev_op;
+    for index in from..to {
+        let field_index = u32::try_from(index).map_err(|_| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "array Subslice index {index} exceeds dialect field-index range"
+            )))
+        })?;
+        let extract = Operation::new(
+            ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![element_ty],
+            vec![array_value],
+            vec![],
+            0,
+        );
+        extract.deref_mut(ctx).set_loc(loc.clone());
+        MirExtractFieldOp::new(extract)
+            .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(field_index));
+        match current_prev {
+            Some(prev) => extract.insert_after(ctx, prev),
+            None => extract.insert_at_front(block_ptr, ctx),
+        }
+        elements.push(extract.deref(ctx).get_result(0));
+        current_prev = Some(extract);
+    }
+
+    let projected_array_ty: TypeHandle =
+        dialect_mir::types::MirArrayType::get(ctx, element_ty, projected_len).into();
+    let construct = Operation::new(
+        ctx,
+        MirConstructArrayOp::get_concrete_op_info(),
+        vec![projected_array_ty],
+        elements,
+        vec![],
+        0,
+    );
+    construct.deref_mut(ctx).set_loc(loc);
+    match current_prev {
+        Some(prev) => construct.insert_after(ctx, prev),
+        None => construct.insert_at_front(block_ptr, ctx),
+    }
+
+    Ok((construct.deref(ctx).get_result(0), Some(construct)))
+}
+
+/// Compute the in-memory address of `place` starting from its alloca `slot`.
+///
+/// Walks the projection chain and emits the correct pliron ops for each
+/// element:
+///
+/// - `Field(idx, _)`   → [`MirFieldAddrOp`]
+/// - `ConstantIndex {offset, from_end, ..}` → an element address. Forward
+///   indexes materialize `offset` directly; from-end indexes on slices extract
+///   the fat-pointer length and materialize `len - offset` at runtime.
+/// - `Index(local)`    → `load_local(local)` + [`MirArrayElementAddrOp`]
+///   (array pointee) or `load_local(local)` + [`MirPtrOffsetOp`] (slice data pointer)
+/// - `Deref`           → `MirLoadOp` of the pointer (the loaded pointer IS
+///   the pointee's address); subsequent projections apply to the pointee.
+///   ZST pointees skip the load (SharedArray exception). Fat (slice-shaped)
+///   pointees scalarize to a (data ptr, len) pair: a mid-chain fat deref
+///   loads the whole fat value and extracts the thin data pointer (field 0)
+///   so the walk continues against the ORIGINAL elements, while a trailing
+///   fat deref (`&*s` reborrow) is just a load of the fat value.
+///
+/// `Downcast` records the variant for the `Field` immediately after it (the
+/// pair addresses an enum payload through the flattened `all_field_types`
+/// index); rustc guarantees that pairing, and any other continuation punts.
+/// A SHARED borrow of a payload whose enum storage is canonical rather than
+/// semantic (see [`enum_payload_needs_storage_coercion`]) also punts, so the
+/// caller's value-copy fallback handles the read soundly instead of handing
+/// out an address that cannot honor the storage coercion.
+/// `Subslice` is handled for both sized arrays and slice fat pointers. Array
+/// subslices keep an in-memory address; slice subslices advance the data
+/// pointer and rebuild metadata as `len - (from + to)`, and can continue into
+/// element Index/forward-ConstantIndex projections. From-end `ConstantIndex`
+/// is accepted only when the immediately preceding fat-slice deref supplied
+/// runtime length metadata; other bases (including a from-end index after a
+/// Subslice) punt instead of guessing a length.
+///
+/// Returns `Ok(Some((addr, last_op)))` on success, `Ok(None)` if the
+/// projection chain contains an element this helper doesn't know how to
+/// turn into an address (the caller decides whether a value fallback is
+/// sound or the construct must be rejected), or `Err` if something
+/// structurally invalid happens (wrong pointee kind, unsupported type).
+///
+/// `is_mutable` governs the mutability of intermediate pointer types; the
+/// final result pointer also carries this mutability.
+fn translate_place_addr_from_slot(
+    ctx: &mut Context,
+    body: &mir::Body,
+    value_map: &ValueMap,
+    slot: Value,
+    projection: &[mir::ProjectionElem],
+    is_mutable: bool,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<Option<(Value, Option<Ptr<Operation>>)>> {
+    use dialect_mir::ops::MirConstantOp;
+
+    let mut current = slot;
+    let mut current_prev_op = prev_op;
+    let mut current_is_slice_data = false;
+    // A fat-slice Deref may lower the immediately following Subslice while its
+    // length metadata is still available. The next loop iteration then skips
+    // that already-consumed projection and preserves slice-data provenance for
+    // a following Index/ConstantIndex.
+    let mut consumed_slice_subslice = false;
+    // A fat DST Deref can consume the immediately following slice-tail Field
+    // while rebuilding the `(data_ptr, len)` value needed for an indexed
+    // element address. The next loop iteration skips that already-lowered
+    // Field and preserves slice-data provenance for Index/ConstantIndex.
+    let mut consumed_slice_tail_field = false;
+    let mut current_slice_len: Option<Value> = None;
+    // A fat reference to a slice-tailed struct carries the runtime length of
+    // its final slice field. Preserve that metadata while walking nested
+    // slice-tailed struct fields until the actual `[T]` field is reached.
+    let mut carried_slice_tail_len: Option<Value> = None;
+    // Set by a `Downcast` and consumed by the `Field` that follows it, which
+    // is the only projection pair that can name an enum payload.
+    let mut pending_variant: Option<usize> = None;
+
+    for (proj_idx, elem) in projection.iter().enumerate() {
+        // The slice-data provenance bit only describes the pointer produced by
+        // the immediately-preceding `Deref` of a fat slice (index it by
+        // element, not as a pointer to one array object). Capture it for this
+        // iteration and clear it up front, so the invariant stays local: it is
+        // true only when the previous step handed us a slice DATA pointer, and
+        // no later projection arm can accidentally leak it forward.
+        let entered_as_slice_data = current_is_slice_data;
+        let entered_slice_len = current_slice_len.take();
+        current_is_slice_data = false;
+
+        // The preceding fat-DST Deref already lowered this slice-tail Field
+        // so it could preserve the metadata before continuing to an element
+        // index. Skip the syntactic Field here and carry the normalized
+        // slice-data state into the following Index/ConstantIndex.
+        if consumed_slice_tail_field {
+            if !matches!(elem, mir::ProjectionElem::Field(_, _)) {
+                return Ok(None);
+            }
+            consumed_slice_tail_field = false;
+            current_is_slice_data = entered_as_slice_data;
+            current_slice_len = entered_slice_len;
+            continue;
+        }
+
+        // A `Downcast` names a variant only for the `Field` IMMEDIATELY
+        // after it (rustc's MIR validator enforces the pairing). Any other
+        // continuation is not a shape valid MIR produces; punt rather than
+        // let a stale variant leak into a later `Field` arm.
+        if pending_variant.is_some() && !matches!(elem, mir::ProjectionElem::Field(_, _)) {
+            return Ok(None);
+        }
+
+        match elem {
+            // `*place` -- the place walked so far holds a pointer; the
+            // address of the dereferenced place is that pointer VALUE, so a
+            // single `mir.load` of `current` yields it. Subsequent
+            // projections then apply to the pointee.
+            mir::ProjectionElem::Deref => {
+                // Type of the place being dereferenced (= pointee of the
+                // `current` address).
+                let Some(place_ty) = mir_ptr_pointee(ctx, current.get_type(ctx)) else {
+                    // `current` is not a pointer-typed address; punt to the
+                    // caller.
+                    return Ok(None);
+                };
+                let pointee_is_zst_tuple = is_empty_tuple_type(ctx, place_ty);
+                let pointee_is_thin_ptr =
+                    place_ty.deref(ctx).is::<dialect_mir::types::MirPtrType>();
+                // Slice-shaped (fat) pointees carry their element type.
+                let fat_elem_ty = slice_like_element_type(ctx, place_ty);
+
+                if pointee_is_zst_tuple {
+                    // ZST-pointee no-load exception (mirrors the Deref
+                    // handling in `translate_place`, where it covers
+                    // SharedArray): a pointer to a ZST *is* the runtime
+                    // representation of the ZST place, so the deref adds no
+                    // indirection. Keep `current` unchanged instead of
+                    // emitting a meaningless load.
+                    continue;
+                }
+
+                let is_last = proj_idx + 1 == projection.len();
+                if let Some(elem_ty) = fat_elem_ty {
+                    // Fat values (`&[T]`, `DisjointSlice<T>`, fat references
+                    // to slice-tailed structs) are a (data pointer, element
+                    // count) pair; dereferencing THROUGH them with a single
+                    // `mir.load` would treat the pair as a thin address, a
+                    // silent miscompile, so we never do that. What we CAN do:
+                    //
+                    // - Trailing `&*s` reborrow (the deref is the last
+                    //   projection): the borrow result IS the fat value,
+                    //   which lives whole in the slot, so the plain load
+                    //   below is exactly right.
+                    //
+                    // - When the next projection is one we understand,
+                    //   continue the walk by hand: load the fat PAIR,
+                    //   extract its data pointer (field 0), and process the
+                    //   following projection against that pointer. The data
+                    //   pointer addresses the ORIGINAL elements, so both
+                    //   shared and mutable borrows stay sound. This covers
+                    //   field access through a fat reference to a
+                    //   slice-tailed struct (the `(*iter).alive.start`
+                    //   accesses inside `core::array::IntoIter::next`,
+                    //   issue #138) and element access through a slice
+                    //   reference (`(*slice)[i]`, including the inlined
+                    //   body of `slice::get_mut`, issue #58).
+                    //
+                    // - Anything else keeps the loud failure (mutable) or
+                    //   the value-copy fallback (shared).
+                    if is_last {
+                        // Fall through to the load below.
+                    } else {
+                        // Load the fat (ptr, len) pair from the slot.
+                        let fat_load = Operation::new(
+                            ctx,
+                            MirLoadOp::get_concrete_op_info(),
+                            vec![place_ty],
+                            vec![current],
+                            vec![],
+                            0,
+                        );
+                        fat_load.deref_mut(ctx).set_loc(loc.clone());
+                        match current_prev_op {
+                            Some(p) => fat_load.insert_after(ctx, p),
+                            None => fat_load.insert_at_front(block_ptr, ctx),
+                        }
+                        let fat_val = fat_load.deref(ctx).get_result(0);
+
+                        if let mir::ProjectionElem::Subslice { from, to, from_end } =
+                            &projection[proj_idx + 1]
+                        {
+                            // Slice Subslice needs both halves of the fat value,
+                            // so lower it here before Deref would discard length
+                            // metadata. Optimized MIR can continue with an
+                            // Index/ConstantIndex, e.g. `(*s)[1:-1][0 of 1]`.
+                            if !*from_end {
+                                return Ok(None);
+                            }
+                            let (subslice, last_op) = emit_slice_subslice_value(
+                                ctx,
+                                fat_val,
+                                elem_ty,
+                                is_mutable,
+                                *from,
+                                *to,
+                                block_ptr,
+                                Some(fat_load),
+                                loc.clone(),
+                            )?;
+
+                            if proj_idx + 2 == projection.len() {
+                                return Ok(Some((subslice, Some(last_op))));
+                            }
+
+                            match &projection[proj_idx + 2] {
+                                mir::ProjectionElem::Index(_)
+                                | mir::ProjectionElem::ConstantIndex {
+                                    from_end: false, ..
+                                } => {
+                                    let Some(data_ptr_ty) =
+                                        erased_slice_data_pointer_type(ctx, subslice, elem_ty)
+                                    else {
+                                        return Ok(None);
+                                    };
+                                    let extract_ptr = Operation::new(
+                                        ctx,
+                                        MirExtractFieldOp::get_concrete_op_info(),
+                                        vec![data_ptr_ty],
+                                        vec![subslice],
+                                        vec![],
+                                        0,
+                                    );
+                                    extract_ptr.deref_mut(ctx).set_loc(loc.clone());
+                                    MirExtractFieldOp::new(extract_ptr).set_attr_index(
+                                        ctx,
+                                        dialect_mir::attributes::FieldIndexAttr(0),
+                                    );
+                                    extract_ptr.insert_after(ctx, last_op);
+                                    current = extract_ptr.deref(ctx).get_result(0);
+                                    current_prev_op = Some(extract_ptr);
+                                    current_is_slice_data = true;
+                                    consumed_slice_subslice = true;
+                                    continue;
+                                }
+                                _ => return Ok(None),
+                            }
+                        }
+
+                        // Extract the data pointer (field 0 of the pair).
+                        // Its pointee is the slice's element type: the
+                        // struct itself for a fat struct reference, or the
+                        // element for an ordinary `&[T]` / `DisjointSlice`.
+                        let Some(data_ptr_ty) =
+                            erased_slice_data_pointer_type(ctx, fat_val, elem_ty)
+                        else {
+                            return Ok(None);
+                        };
+                        let extract_ptr = Operation::new(
+                            ctx,
+                            MirExtractFieldOp::get_concrete_op_info(),
+                            vec![data_ptr_ty],
+                            vec![fat_val],
+                            vec![],
+                            0,
+                        );
+                        extract_ptr.deref_mut(ctx).set_loc(loc.clone());
+                        MirExtractFieldOp::new(extract_ptr)
+                            .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
+                        extract_ptr.insert_after(ctx, fat_load);
+                        let data_ptr = extract_ptr.deref(ctx).get_result(0);
+                        current_prev_op = Some(extract_ptr);
+
+                        // Borrow or index of the struct's unsized slice tail,
+                        // e.g. `&(*iter).data` or `&(*p).tail[k]`. No thin
+                        // pointer can represent the whole tail: rebuild the
+                        // `(tail pointer, len)` pair while the fat reference's
+                        // metadata is still available.
+                        if let mir::ProjectionElem::Field(field_idx, field_rust_ty) =
+                            &projection[proj_idx + 1]
+                            && let rustc_public::ty::TyKind::RigidTy(
+                                rustc_public::ty::RigidTy::Slice(tail_elem_rust_ty),
+                            ) = field_rust_ty.kind()
+                        {
+                            let tail_continuation = projection.get(proj_idx + 2);
+                            if !matches!(
+                                tail_continuation,
+                                None | Some(&mir::ProjectionElem::Index(_))
+                                    | Some(&mir::ProjectionElem::ConstantIndex { .. })
+                            ) {
+                                return Ok(None);
+                            }
+
+                            let tail_elem_ty = types::translate_type(ctx, &tail_elem_rust_ty)?;
+
+                            // Address of the first tail element. The struct
+                            // model stores the tail field with the ELEMENT
+                            // type (see `translate_type`'s ADT arm), so the
+                            // field-addr result is a pointer to the element
+                            // and the dialect verifier agrees.
+                            let tail_ptr_ty = projected_pointer_type(
+                                ctx,
+                                data_ptr.get_type(ctx),
+                                tail_elem_ty,
+                                /* legacy requested mutability, ignored */ is_mutable,
+                            )
+                            .expect("fat-pointer data extraction must yield a MirPtrType");
+                            let tail_addr = dialect_mir::ops::MirFieldAddrOp::build(
+                                ctx,
+                                data_ptr,
+                                tail_ptr_ty,
+                                *field_idx as u32,
+                            )?;
+                            tail_addr.deref_mut(ctx).set_loc(loc.clone());
+                            tail_addr.insert_after(ctx, extract_ptr);
+                            let tail_ptr = tail_addr.deref(ctx).get_result(0);
+
+                            // The element count (field 1 of the fat pair).
+                            let (len_val, extract_len) = emit_slice_len_extract(
+                                ctx,
+                                fat_val,
+                                block_ptr,
+                                Some(tail_addr),
+                                loc.clone(),
+                            );
+
+                            // Erased kind on purpose: this fat value is a projection-internal
+                            // reconstruction of the DST tail. A Rust kind is established only
+                            // when the value crosses an `Rvalue::Ref`/`AddressOf` boundary,
+                            // which retypes it to the declared kind.
+                            let tail_is_mutable = tail_ptr_ty
+                                .deref(ctx)
+                                .downcast_ref::<dialect_mir::types::MirPtrType>()
+                                .expect("slice-tail projection must produce a MirPtrType")
+                                .is_mutable;
+                            let slice_ty = dialect_mir::types::MirSliceType::get_with_mutability(
+                                ctx,
+                                tail_elem_ty,
+                                tail_is_mutable,
+                            );
+                            use dialect_mir::ops::MirConstructSliceOp;
+                            let construct = Operation::new(
+                                ctx,
+                                MirConstructSliceOp::get_concrete_op_info(),
+                                vec![slice_ty.into()],
+                                vec![tail_ptr, len_val],
+                                vec![],
+                                0,
+                            );
+                            construct.deref_mut(ctx).set_loc(loc.clone());
+                            construct.insert_after(ctx, extract_len);
+                            let tail_slice = construct.deref(ctx).get_result(0);
+
+                            // Whole-tail borrow/reborrow: return the fat value.
+                            if tail_continuation.is_none() {
+                                return Ok(Some((tail_slice, Some(construct))));
+                            }
+
+                            // Element borrow/write: normalize the rebuilt tail
+                            // to its data pointer, then let the existing
+                            // Index/ConstantIndex arms perform the element
+                            // offset and return the real address.
+                            let Some(indexed_data_ptr_ty) =
+                                erased_slice_data_pointer_type(ctx, tail_slice, tail_elem_ty)
+                            else {
+                                return Ok(None);
+                            };
+                            let indexed_extract = Operation::new(
+                                ctx,
+                                MirExtractFieldOp::get_concrete_op_info(),
+                                vec![indexed_data_ptr_ty],
+                                vec![tail_slice],
+                                vec![],
+                                0,
+                            );
+                            indexed_extract.deref_mut(ctx).set_loc(loc.clone());
+                            MirExtractFieldOp::new(indexed_extract)
+                                .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
+                            indexed_extract.insert_after(ctx, construct);
+
+                            current = indexed_extract.deref(ctx).get_result(0);
+                            current_prev_op = Some(indexed_extract);
+                            current_is_slice_data = true;
+                            current_slice_len = if matches!(
+                                tail_continuation,
+                                Some(&mir::ProjectionElem::ConstantIndex { from_end: true, .. })
+                            ) {
+                                Some(len_val)
+                            } else {
+                                None
+                            };
+                            consumed_slice_tail_field = true;
+                            continue;
+                        }
+
+                        match &projection[proj_idx + 1] {
+                            // Sized field access: hand the data pointer to
+                            // the field arm below. If the field is itself a
+                            // slice-tailed DST, preserve the fat reference's
+                            // metadata until the walk reaches the actual `[T]`
+                            // tail field.
+                            mir::ProjectionElem::Field(_, field_rust_ty) => {
+                                if types::slice_tail_element_ty(field_rust_ty).is_some() {
+                                    let (len, len_op) = emit_slice_len_extract(
+                                        ctx,
+                                        fat_val,
+                                        block_ptr,
+                                        current_prev_op,
+                                        loc.clone(),
+                                    );
+                                    current_prev_op = Some(len_op);
+                                    carried_slice_tail_len = Some(len);
+                                }
+                                current = data_ptr;
+                                continue;
+                            }
+                            // Element access through a slice data pointer is
+                            // pointer arithmetic over the slice element type.
+                            // That remains true when the element type is
+                            // itself an array (`&[[T; N]][i]`), where a
+                            // type-only check would otherwise mistake the
+                            // data pointer for a pointer to one array object
+                            // and index inside row 0.
+                            mir::ProjectionElem::Index(_) => {
+                                current = data_ptr;
+                                current_is_slice_data = true;
+                                continue;
+                            }
+                            mir::ProjectionElem::ConstantIndex { from_end, .. } => {
+                                current = data_ptr;
+                                current_is_slice_data = true;
+                                if *from_end {
+                                    let (len, len_op) = emit_slice_len_extract(
+                                        ctx,
+                                        fat_val,
+                                        block_ptr,
+                                        current_prev_op,
+                                        loc.clone(),
+                                    );
+                                    current_prev_op = Some(len_op);
+                                    current_slice_len = Some(len);
+                                }
+                                continue;
+                            }
+                            // Unknown continuation: keep the conservative
+                            // behaviour (loud failure for mutable borrows,
+                            // value-copy fallback for shared ones).
+                            _ => {
+                                if is_mutable {
+                                    return input_err!(
+                                        loc,
+                                        TranslationErr::unsupported(format!(
+                                            "cannot compute a mutable in-memory address through \
+                                             fat-pointer deref (projection {:?})",
+                                            projection
+                                        ))
+                                    );
+                                }
+                                return Ok(None);
+                            }
+                        }
+                    }
+                } else if !pointee_is_thin_ptr {
+                    // Deref of a non-pointer-typed place (a type the
+                    // importer models by value); punt to the caller.
+                    return Ok(None);
+                }
+
+                let load_op = Operation::new(
+                    ctx,
+                    MirLoadOp::get_concrete_op_info(),
+                    vec![place_ty],
+                    vec![current],
+                    vec![],
+                    0,
+                );
+                load_op.deref_mut(ctx).set_loc(loc.clone());
+                match current_prev_op {
+                    Some(p) => load_op.insert_after(ctx, p),
+                    None => load_op.insert_at_front(block_ptr, ctx),
+                }
+                current = load_op.deref(ctx).get_result(0);
+                current_prev_op = Some(load_op);
+            }
+
+            mir::ProjectionElem::Field(field_idx, field_ty) => {
+                let tail_elem_rust_ty = match field_ty.kind() {
+                    rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Slice(elem)) => {
+                        Some(elem)
+                    }
+                    _ => None,
+                };
+
+                if let Some(tail_len) = carried_slice_tail_len.take() {
+                    if let Some(tail_elem_rust_ty) = tail_elem_rust_ty {
+                        // Element-address traversal through an unsized tail is
+                        // intentionally left to #881. For #880 the address path
+                        // only needs to materialize the whole nested slice tail.
+                        if proj_idx + 1 != projection.len() || pending_variant.is_some() {
+                            return Ok(None);
+                        }
+
+                        let tail_elem_ty = types::translate_type(ctx, &tail_elem_rust_ty)?;
+                        let Some(tail_ptr_ty) = projected_pointer_type(
+                            ctx,
+                            current.get_type(ctx),
+                            tail_elem_ty,
+                            is_mutable,
+                        ) else {
+                            return Ok(None);
+                        };
+
+                        // The physical struct stores an unsized slice tail as
+                        // its element type, so the field address must be `*T`,
+                        // not `*[T]`.
+                        let tail_addr = dialect_mir::ops::MirFieldAddrOp::build(
+                            ctx,
+                            current,
+                            tail_ptr_ty,
+                            *field_idx as u32,
+                        )?;
+                        tail_addr.deref_mut(ctx).set_loc(loc.clone());
+                        match current_prev_op {
+                            Some(previous) => tail_addr.insert_after(ctx, previous),
+                            None => tail_addr.insert_at_front(block_ptr, ctx),
+                        }
+                        let tail_ptr = tail_addr.deref(ctx).get_result(0);
+
+                        // Erased kind on purpose: this fat value is a projection-internal
+                        // reconstruction of the DST tail. A Rust kind is established only
+                        // when the value crosses an `Rvalue::Ref`/`AddressOf` boundary,
+                        // which retypes it to the declared kind.
+                        let tail_is_mutable = tail_ptr_ty
+                            .deref(ctx)
+                            .downcast_ref::<dialect_mir::types::MirPtrType>()
+                            .expect("slice-tail projection must produce a MirPtrType")
+                            .is_mutable;
+                        let slice_ty = dialect_mir::types::MirSliceType::get_with_mutability(
+                            ctx,
+                            tail_elem_ty,
+                            tail_is_mutable,
+                        );
+                        use dialect_mir::ops::MirConstructSliceOp;
+                        let construct = Operation::new(
+                            ctx,
+                            MirConstructSliceOp::get_concrete_op_info(),
+                            vec![slice_ty.into()],
+                            vec![tail_ptr, tail_len],
+                            vec![],
+                            0,
+                        );
+                        construct.deref_mut(ctx).set_loc(loc.clone());
+                        construct.insert_after(ctx, tail_addr);
+                        return Ok(Some((construct.deref(ctx).get_result(0), Some(construct))));
+                    }
+
+                    // Metadata remains relevant only while descending through
+                    // another slice-tailed DST field. A sized field projects
+                    // away from the unsized tail, so discard it there.
+                    if types::slice_tail_element_ty(field_ty).is_some() {
+                        carried_slice_tail_len = Some(tail_len);
+                    }
+                }
+
+                let field_type = types::translate_type(ctx, field_ty)?;
+
+                // After a `Downcast`, the field belongs to that variant, and an
+                // enum names its payload fields by position in the flattened
+                // `all_field_types`. Translate the per-variant index into that
+                // flat one; a non-enum pointee keeps the index as written.
+                let pointee = current
+                    .get_type(ctx)
+                    .deref(ctx)
+                    .downcast_ref::<dialect_mir::types::MirPtrType>()
+                    .map(|ptr| ptr.pointee);
+                let pointee_is_enum = pointee.is_some_and(|pointee| {
+                    pointee.deref(ctx).is::<dialect_mir::types::MirEnumType>()
+                });
+                let flat_field_index = match pending_variant.take() {
+                    Some(variant) => {
+                        let flat = pointee.and_then(|pointee| {
+                            pointee
+                                .deref(ctx)
+                                .downcast_ref::<dialect_mir::types::MirEnumType>()
+                                .and_then(|enum_ty| enum_ty.flat_field_index(variant, *field_idx))
+                        });
+                        match flat {
+                            Some(flat) => {
+                                // A payload whose bytes use canonical storage
+                                // that differs from its semantic type (bool
+                                // leaves are i8 bytes, shared-memory pointer
+                                // leaves are generic pointers) has no honest
+                                // raw address: reads and writes through one
+                                // are typed with the SEMANTIC type. For a
+                                // SHARED borrow the value-copy fallback is
+                                // sound and matches what the importer did
+                                // before payload addressing existed, so punt.
+                                // Mutable borrows and assignment stores keep
+                                // the address path, where mir-lower's
+                                // canonical-storage gate stays the loud,
+                                // fail-closed authority (so a conservative
+                                // miss here errors instead of miscompiling).
+                                if !is_mutable
+                                    && enum_payload_needs_storage_coercion(ctx, field_type)
+                                {
+                                    return Ok(None);
+                                }
+                                flat as u32
+                            }
+                            // A downcast over something this walker cannot
+                            // resolve to an enum payload position. Punt rather
+                            // than address the wrong bytes.
+                            None => return Ok(None),
+                        }
+                    }
+                    // Valid MIR never applies `Field` to an enum place without
+                    // a `Downcast` naming the variant first (rustc's own place
+                    // typing has no answer for it). `MirFieldAddrOp` reads an
+                    // enum-pointee index as a FLATTENED (variant, field)
+                    // position, so passing this raw per-variant index through
+                    // could silently address another variant's payload. Only an
+                    // importer bug or invalid MIR reaches here; fail loudly.
+                    None if pointee_is_enum => {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "Field projection on an enum place without a preceding \
+                                 Downcast (projection {:?})",
+                                projection
+                            ))
+                        );
+                    }
+                    None => *field_idx as u32,
+                };
+
+                // Field address computation must remain in the address space of the
+                // aggregate pointer. LLVM GEP cannot change address spaces.
+                let Some(result_ptr_ty) =
+                    projected_pointer_type(ctx, current.get_type(ctx), field_type, is_mutable)
+                else {
+                    return Ok(None);
+                };
+
+                let op = dialect_mir::ops::MirFieldAddrOp::build(
+                    ctx,
+                    current,
+                    result_ptr_ty,
+                    flat_field_index,
+                )?;
+                op.deref_mut(ctx).set_loc(loc.clone());
+
+                match current_prev_op {
+                    Some(previous) => op.insert_after(ctx, previous),
+                    None => op.insert_at_front(block_ptr, ctx),
+                }
+
+                current = op.deref(ctx).get_result(0);
+                current_prev_op = Some(op);
+            }
+
+            mir::ProjectionElem::ConstantIndex {
+                offset,
+                min_length: _,
+                from_end,
+            } => {
+                let (mut pointee_kind, addr_space) = match pointer_pointee_kind(ctx, current) {
+                    Some(kind) => kind,
+                    None => return Ok(None),
+                };
+                if entered_as_slice_data {
+                    pointee_kind = PointeeKind::Direct;
+                }
+
+                let index_val = if *from_end {
+                    // Never derive this from the pointee type. For
+                    // `&[[T; N]]`, the pointee array length N is the row
+                    // width, while this index selects a row from the outer
+                    // runtime-length slice.
+                    if !entered_as_slice_data {
+                        return Ok(None);
+                    }
+                    let Some(slice_len) = entered_slice_len else {
+                        return Ok(None);
+                    };
+                    let (index, sub_op) = emit_from_end_slice_index(
+                        ctx,
+                        slice_len,
+                        *offset,
+                        block_ptr,
+                        current_prev_op,
+                        loc.clone(),
+                    )?;
+                    current_prev_op = Some(sub_op);
+                    index
+                } else {
+                    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signed);
+                    let index_apint =
+                        APInt::from_i64(*offset as i64, NonZeroUsize::new(64).unwrap());
+                    let const_attr =
+                        pliron::builtin::attributes::IntegerAttr::new(i64_ty, index_apint);
+                    let const_op_ptr = Operation::new(
+                        ctx,
+                        MirConstantOp::get_concrete_op_info(),
+                        vec![i64_ty.into()],
+                        vec![],
+                        vec![],
+                        0,
+                    );
+                    const_op_ptr.deref_mut(ctx).set_loc(loc.clone());
+                    MirConstantOp::new(const_op_ptr).set_attr_value(ctx, const_attr);
+                    match current_prev_op {
+                        Some(p) => const_op_ptr.insert_after(ctx, p),
+                        None => const_op_ptr.insert_at_front(block_ptr, ctx),
+                    }
+                    current_prev_op = Some(const_op_ptr);
+                    const_op_ptr.deref(ctx).get_result(0)
+                };
+
+                let (addr_op, next_current) = emit_indexed_element_addr(
+                    ctx,
+                    current,
+                    index_val,
+                    pointee_kind,
+                    addr_space,
+                    is_mutable,
+                    block_ptr,
+                    current_prev_op,
+                    loc.clone(),
+                );
+                current = next_current;
+                current_prev_op = Some(addr_op);
+            }
+
+            // Runtime `arr[i]` indexing. Without this arm, a place like
+            // `&(*ptr).field[i]` would silently drop the `Index` projection
+            // and return a pointer to the array's first slot, miscompiling
+            // every load through the reference into a load of element 0.
+            mir::ProjectionElem::Index(index_local) => {
+                let (mut pointee_kind, addr_space) = match pointer_pointee_kind(ctx, current) {
+                    Some(kind) => kind,
+                    None => return Ok(None),
+                };
+                if entered_as_slice_data {
+                    pointee_kind = PointeeKind::Direct;
+                }
+
+                let index_place = mir::Place {
+                    local: *index_local,
+                    projection: vec![],
+                };
+                let (index_val, next_prev_op) = translate_place(
+                    ctx,
+                    body,
+                    &index_place,
+                    value_map,
+                    block_ptr,
+                    current_prev_op,
+                    loc.clone(),
+                )?;
+                current_prev_op = next_prev_op;
+
+                let (addr_op, next_current) = emit_indexed_element_addr(
+                    ctx,
+                    current,
+                    index_val,
+                    pointee_kind,
+                    addr_space,
+                    is_mutable,
+                    block_ptr,
+                    current_prev_op,
+                    loc.clone(),
+                );
+                current = next_current;
+                current_prev_op = Some(addr_op);
+            }
+
+            mir::ProjectionElem::Subslice { from, to, from_end } => {
+                if *from_end && consumed_slice_subslice {
+                    consumed_slice_subslice = false;
+                    current_is_slice_data = true;
+                    continue;
+                }
+                // A slice Subslice must be lowered while the fat-pointer
+                // metadata is available in the preceding Deref arm.
+                if *from_end {
+                    return Ok(None);
+                }
+                let (subslice_ptr, last_op) = emit_array_subslice_address(
+                    ctx,
+                    current,
+                    *from,
+                    *to,
+                    is_mutable,
+                    block_ptr,
+                    current_prev_op,
+                    loc.clone(),
+                )?;
+                current = subslice_ptr;
+                current_prev_op = Some(last_op);
+            }
+
+            // Enum-variant downcast (`(x as Variant).field`). The downcast
+            // itself moves no address: a payload shares the enum's storage, so
+            // the variant only decides which field the next `Field` names.
+            // Record it and let that arm resolve the flattened payload
+            // position; lowering maps it to a slot or a byte offset through
+            // the enum slot map.
+            mir::ProjectionElem::Downcast(variant_idx) => {
+                pending_variant = Some(variant_idx.to_index());
+            }
+
+            // Remaining projection kinds (OpaqueCast, Subtype) aren't lowered
+            // to addresses here yet. Punt to the caller,
+            // which decides between a value fallback (shared borrows) and a
+            // hard error (mutable borrows).
+            _ => return Ok(None),
+        }
+    }
+
+    // A chain that ENDS on a `Downcast` never occurs in valid MIR (the
+    // validator requires a `Field` after it). Punt rather than hand back the
+    // enum's own address as if it were the variant's payload place.
+    if pending_variant.is_some() || carried_slice_tail_len.is_some() {
+        return Ok(None);
+    }
+
+    Ok(Some((current, current_prev_op)))
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production code mints via facts::PointerOrigin.
+#[allow(clippy::disallowed_methods)]
+mod tests {
+    use super::*;
+    use dialect_mir::types::{MirPtrType, MirStructType};
+    use pliron::builtin::types::FP32Type;
+
+    /// The shared-borrow punt predicate must flag exactly the payload shapes
+    /// whose enum storage differs from their semantic type: bool leaves and
+    /// shared-memory pointer leaves, at any nesting depth. Canonical scalars
+    /// and generic pointers must stay on the address path so shared reads of
+    /// ordinary payloads keep compiling without a copy.
+    #[test]
+    fn payload_storage_coercion_predicate_flags_bool_and_shared_pointer_leaves() {
+        use dialect_mir::types::{MirArrayType, MirTupleType};
+
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let bool_ty: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let f32_ty: TypeHandle = FP32Type::get(&ctx).into();
+        let shared_ptr: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
+        let generic_ptr: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+
+        // Leaves.
+        assert!(enum_payload_needs_storage_coercion(&ctx, bool_ty));
+        assert!(enum_payload_needs_storage_coercion(&ctx, shared_ptr));
+        assert!(!enum_payload_needs_storage_coercion(&ctx, u32_ty));
+        assert!(!enum_payload_needs_storage_coercion(&ctx, f32_ty));
+        assert!(!enum_payload_needs_storage_coercion(&ctx, generic_ptr));
+
+        // Nesting: one flagged leaf taints the aggregate, and a clean
+        // aggregate stays clean.
+        let mixed_tuple: TypeHandle = MirTupleType::get(&mut ctx, vec![u32_ty, bool_ty]).into();
+        let clean_tuple: TypeHandle = MirTupleType::get(&mut ctx, vec![u32_ty, f32_ty]).into();
+        assert!(enum_payload_needs_storage_coercion(&ctx, mixed_tuple));
+        assert!(!enum_payload_needs_storage_coercion(&ctx, clean_tuple));
+
+        let bool_struct: TypeHandle = MirStructType::get(
+            &mut ctx,
+            "HasBool".into(),
+            vec!["a".into(), "b".into()],
+            vec![u32_ty, bool_ty],
+        )
+        .into();
+        assert!(enum_payload_needs_storage_coercion(&ctx, bool_struct));
+
+        let bool_array: TypeHandle = MirArrayType::get(&mut ctx, bool_ty, 4).into();
+        let f32_array: TypeHandle = MirArrayType::get(&mut ctx, f32_ty, 4).into();
+        assert!(enum_payload_needs_storage_coercion(&ctx, bool_array));
+        assert!(!enum_payload_needs_storage_coercion(&ctx, f32_array));
+
+        // Deep nesting: struct-of-tuple-of-shared-pointer.
+        let inner: TypeHandle = MirTupleType::get(&mut ctx, vec![f32_ty, shared_ptr]).into();
+        let deep: TypeHandle =
+            MirStructType::get(&mut ctx, "Deep".into(), vec!["inner".into()], vec![inner]).into();
+        assert!(enum_payload_needs_storage_coercion(&ctx, deep));
+    }
+}
diff --git a/crates/mir-importer/src/translator/rvalue/place_iter.rs b/crates/mir-importer/src/translator/rvalue/place_iter.rs
new file mode 100644
index 0000000000..2beb14d9cd
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/place_iter.rs
@@ -0,0 +1,841 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! [`translate_place_iterative`]: the iterative place value walker.
+
+use super::const_bytes::translate_zero_sized_constant_value;
+use super::const_enum::create_ghost_enum_default;
+use super::place_addr::{
+    emit_array_subslice_value, emit_slice_len_extract, emit_slice_subslice_value,
+};
+use super::place_read::{
+    apply_deref_projection, apply_enum_field_projection, apply_field_addr_and_load,
+    apply_field_projection, translate_place,
+};
+use super::pointee::{normalize_slice_value_to_data_ptr, projected_pointer_type, rust_ty_is_slice};
+use super::static_global::get_static_pointer_info;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::types;
+use crate::translator::values::ValueMap;
+use dialect_mir::ops::{MirExtractFieldOp, MirLoadOp, MirPtrOffsetOp};
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::printable::Printable;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use pliron::{input_err, input_error};
+use rustc_public::mir;
+use rustc_public::mir::ProjectionElem;
+use std::num::NonZeroUsize;
+
+/// Translate a MIR Place using iterative projection processing.
+/// This handles arbitrary depth projections by processing each element in sequence.
+pub fn translate_place_iterative(
+    ctx: &mut Context,
+    body: &mir::Body,
+    place: &mir::Place,
+    value_map: &ValueMap,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    // Start with the base local's current value. In the alloca model every
+    // non-ZST local has a stack slot, so we emit `mir.load` once here and
+    // then layer projections on top of the loaded SSA value; `mem2reg` folds
+    // the load back into a direct SSA use when the slot is promotable. ZST /
+    // unsupported locals fall back to the same ghost-enum / empty-aggregate
+    // synthesis as [`translate_place`].
+    let local = place.local;
+    let (mut current_value, mut current_prev_op) = match value_map
+        .load_local(ctx, local, block_ptr, prev_op)
+    {
+        Some((load_op, val)) => (val, Some(load_op)),
+        None => {
+            let local_decl = &body.locals()[local];
+            let ty_ptr = types::translate_type(ctx, &local_decl.ty)?;
+            if ty_ptr.deref(ctx).is::<dialect_mir::types::MirEnumType>() {
+                let synth_op = create_ghost_enum_default(ctx, ty_ptr, loc.clone());
+                match prev_op {
+                    Some(p) => synth_op.insert_after(ctx, p),
+                    None => synth_op.insert_at_front(block_ptr, ctx),
+                }
+                let val = synth_op.deref(ctx).get_result(0);
+                (val, Some(synth_op))
+            } else if types::is_zst_type(ctx, ty_ptr) {
+                translate_zero_sized_constant_value(ctx, ty_ptr, block_ptr, prev_op, loc.clone())?
+            } else {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Local {} has no alloca slot and is not a ZST",
+                        Into::<usize>::into(local)
+                    ))
+                );
+            }
+        }
+    };
+
+    // Track the Rust type of `current_value` alongside the pliron value.
+    // Each iteration below advances it through rustc_public's own projection
+    // typing (`ProjectionElem::ty`) AFTER the arm has processed the element,
+    // so every arm observes the type *before* its own projection applies and
+    // the next iteration sees the narrowed type. `Downcast` deliberately
+    // leaves the type unchanged (still the enum ADT), which is exactly what
+    // `apply_enum_field_projection` expects when the following `Field` fires.
+    //
+    // This single fold is the only place `current_rust_ty` is updated;
+    // individual arms must not update it themselves. Per-arm updates were
+    // the cause of issue #131: only `Field` advanced the type, so chains
+    // like `[Index, Downcast, Field]` (from `match xs[i]` over an array of
+    // enums) handed the stale Array type to the Downcast/Field handler,
+    // which bailed with "Downcast on non-ADT type: Array". The same
+    // staleness affected `Deref` and `ConstantIndex`.
+    let mut current_rust_ty = body.locals()[local].ty;
+
+    // Track pending downcast (Downcast is a no-op, but we need variant info for Field on enums)
+    // Type inferred from ProjectionElem::Downcast pattern
+    let mut pending_downcast = None;
+
+    // When Deref of a slice is immediately followed by Subslice, keep the fat
+    // value intact for one iteration so Subslice can update both data and len.
+    // The ordinary Deref helper intentionally drops len and returns only the
+    // data pointer because Index/ConstantIndex do not need metadata.
+    let mut preserved_slice_deref_mutability: Option<bool> = None;
+
+    // A fat reference to a slice-tailed struct carries the runtime length of
+    // that tail in field 1. Keep the metadata alongside the projected address
+    // until the walk reaches the actual slice field. This mirrors rustc's
+    // `llextra` model and lets metadata survive through nested slice-tailed
+    // struct fields such as `outer.inner.tail[k]`.
+    let mut carried_slice_tail_len: Option<Value> = None;
+
+    // Process each projection element iteratively
+    for (proj_idx, projection) in place.projection.iter().enumerate() {
+        match projection {
+            ProjectionElem::Deref => {
+                let next_is_slice_subslice = matches!(
+                    place.projection.get(proj_idx + 1),
+                    Some(ProjectionElem::Subslice { from_end: true, .. })
+                );
+                let current_is_fat_slice = current_value
+                    .get_type(ctx)
+                    .deref(ctx)
+                    .is::<dialect_mir::types::MirSliceType>();
+                let pointer_info = get_static_pointer_info(&current_rust_ty);
+                let slice_deref_mutability = pointer_info.as_ref().and_then(|(pointee, origin)| {
+                    rust_ty_is_slice(pointee).then_some(origin.is_mutable())
+                });
+                let current_is_slice_tail_ref = pointer_info
+                    .as_ref()
+                    .is_some_and(|(pointee, _)| types::slice_tail_element_ty(pointee).is_some());
+
+                if next_is_slice_subslice
+                    && current_is_fat_slice
+                    && slice_deref_mutability.is_some()
+                {
+                    // Preserve the fat pair. The following Subslice consumes
+                    // both data and len and advances `current_rust_ty` normally.
+                    preserved_slice_deref_mutability = slice_deref_mutability;
+                    carried_slice_tail_len = None;
+                } else {
+                    // `&S<[T]>` uses the same fat-pair carrier as a slice, but
+                    // field 0 points at the struct prefix while field 1 is the
+                    // trailing slice length. Extract that metadata before Deref
+                    // reduces the value to the struct data pointer. Unlike the
+                    // old one-step handoff, keep it alive across any nested
+                    // slice-tailed struct fields until the real `[T]` field is
+                    // reached.
+                    carried_slice_tail_len = if current_is_fat_slice && current_is_slice_tail_ref {
+                        let (len, len_op) = emit_slice_len_extract(
+                            ctx,
+                            current_value,
+                            block_ptr,
+                            current_prev_op,
+                            loc.clone(),
+                        );
+                        current_prev_op = Some(len_op);
+                        Some(len)
+                    } else {
+                        None
+                    };
+
+                    (current_value, current_prev_op) = apply_deref_projection(
+                        ctx,
+                        current_value,
+                        block_ptr,
+                        current_prev_op,
+                        loc.clone(),
+                    )?;
+                    preserved_slice_deref_mutability = None;
+                }
+                pending_downcast = None;
+            }
+
+            ProjectionElem::Field(field_idx, field_ty) => {
+                // Check if this is a field access on an enum (preceded by Downcast).
+                if let Some(variant_idx) = pending_downcast.take() {
+                    if carried_slice_tail_len.is_some() {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(
+                                "slice-tail metadata cannot cross an enum Downcast/Field projection"
+                                    .to_string()
+                            )
+                        );
+                    }
+
+                    // Enum variant field access - use MirEnumPayloadOp.
+                    (current_value, current_prev_op) = apply_enum_field_projection(
+                        ctx,
+                        current_value,
+                        &current_rust_ty,
+                        variant_idx,
+                        *field_idx,
+                        field_ty,
+                        block_ptr,
+                        current_prev_op,
+                        loc.clone(),
+                    )?;
+                } else {
+                    let tail_elem_rust_ty = match field_ty.kind() {
+                        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Slice(
+                            elem,
+                        )) => Some(elem),
+                        _ => None,
+                    };
+                    let field_is_slice_tailed_adt =
+                        types::slice_tail_element_ty(field_ty).is_some();
+
+                    if let Some(tail_elem_rust_ty) = tail_elem_rust_ty
+                        && let Some(tail_len) = carried_slice_tail_len.take()
+                    {
+                        let tail_elem_ty = types::translate_type(ctx, &tail_elem_rust_ty)?;
+
+                        // The struct model stores an unsized `[T]` tail as the
+                        // element type `T`, because the elements live inline after
+                        // the sized prefix. Address the field as `*T`, not `*[T]`.
+                        use dialect_mir::ops::MirConstructSliceOp;
+                        let tail_ptr_ty = projected_pointer_type(
+                            ctx,
+                            current_value.get_type(ctx),
+                            tail_elem_ty,
+                            /* legacy requested mutability, ignored */ false,
+                        )
+                        .expect("slice-tail field base must be a MirPtrType");
+                        let tail_addr = dialect_mir::ops::MirFieldAddrOp::build(
+                            ctx,
+                            current_value,
+                            tail_ptr_ty,
+                            *field_idx as u32,
+                        )?;
+                        tail_addr.deref_mut(ctx).set_loc(loc.clone());
+                        match current_prev_op {
+                            Some(prev) => tail_addr.insert_after(ctx, prev),
+                            None => tail_addr.insert_at_front(block_ptr, ctx),
+                        }
+                        let tail_ptr = tail_addr.deref(ctx).get_result(0);
+
+                        // Reconstruct the semantic `[T]` value from the inline tail
+                        // address plus the metadata carried from the outer fat reference,
+                        // with an intentionally Erased pointer kind: a Rust kind is
+                        // established only at the `Rvalue::Ref`/`AddressOf` boundary.
+                        // A following Index or ConstantIndex can scalarize this
+                        // MirSliceType to field 0 and reuse the existing pointer-offset
+                        // + load path.
+                        let tail_is_mutable = tail_ptr_ty
+                            .deref(ctx)
+                            .downcast_ref::<dialect_mir::types::MirPtrType>()
+                            .expect("slice-tail projection must produce a MirPtrType")
+                            .is_mutable;
+                        let tail_slice_ty = dialect_mir::types::MirSliceType::get_with_mutability(
+                            ctx,
+                            tail_elem_ty,
+                            tail_is_mutable,
+                        );
+                        let construct_tail = Operation::new(
+                            ctx,
+                            MirConstructSliceOp::get_concrete_op_info(),
+                            vec![tail_slice_ty.into()],
+                            vec![tail_ptr, tail_len],
+                            vec![],
+                            0,
+                        );
+                        construct_tail.deref_mut(ctx).set_loc(loc.clone());
+                        construct_tail.insert_after(ctx, tail_addr);
+                        current_value = construct_tail.deref(ctx).get_result(0);
+                        current_prev_op = Some(construct_tail);
+                    } else if carried_slice_tail_len.is_some() && field_is_slice_tailed_adt {
+                        // The selected field is itself an unsized struct whose final
+                        // field eventually contains the same slice tail. Such a field
+                        // cannot be loaded as an SSA aggregate. Advance only the
+                        // address and keep the metadata riding alongside it for the
+                        // next projection step.
+                        if !current_value
+                            .get_type(ctx)
+                            .deref(ctx)
+                            .is::<dialect_mir::types::MirPtrType>()
+                        {
+                            return input_err!(
+                                loc,
+                                TranslationErr::unsupported(format!(
+                                    "slice-tail metadata reached nested DST field {:?}, but the current value is not an address",
+                                    field_ty
+                                ))
+                            );
+                        }
+
+                        let field_type = types::translate_type(ctx, field_ty)?;
+                        let field_ptr_ty = projected_pointer_type(
+                            ctx,
+                            current_value.get_type(ctx),
+                            field_type,
+                            /* legacy requested mutability, ignored */ false,
+                        )
+                        .expect("nested DST field base must be a MirPtrType");
+                        let field_addr = dialect_mir::ops::MirFieldAddrOp::build(
+                            ctx,
+                            current_value,
+                            field_ptr_ty,
+                            *field_idx as u32,
+                        )?;
+                        field_addr.deref_mut(ctx).set_loc(loc.clone());
+                        match current_prev_op {
+                            Some(prev) => field_addr.insert_after(ctx, prev),
+                            None => field_addr.insert_at_front(block_ptr, ctx),
+                        }
+                        current_value = field_addr.deref(ctx).get_result(0);
+                        current_prev_op = Some(field_addr);
+                    } else {
+                        // A sized field does not inherit DST metadata. Once the
+                        // projection leaves the unsized-tail path, drop the
+                        // metadata and lower the field normally.
+                        carried_slice_tail_len = None;
+
+                        let current_is_ptr = current_value
+                            .get_type(ctx)
+                            .deref(ctx)
+                            .is::<dialect_mir::types::MirPtrType>();
+                        if current_is_ptr {
+                            // `current_value` is an ADDRESS, not an aggregate
+                            // value. This happens after dereferencing a fat
+                            // pointer: `apply_deref_projection` cannot load an
+                            // unsized pointee, so it hands back the data
+                            // pointer instead (e.g. reading
+                            // `(*iter).alive.start` through the fat
+                            // `&mut PolymorphicIter<[MaybeUninit<T>]>` inside
+                            // `core::array::IntoIter::next`, issue #138).
+                            // Compute the field's address and load the field.
+                            (current_value, current_prev_op) = apply_field_addr_and_load(
+                                ctx,
+                                current_value,
+                                *field_idx,
+                                field_ty,
+                                block_ptr,
+                                current_prev_op,
+                                loc.clone(),
+                            )?;
+                        } else {
+                            // Regular struct/tuple field access.
+                            (current_value, current_prev_op) = apply_field_projection(
+                                ctx,
+                                current_value,
+                                *field_idx,
+                                field_ty,
+                                block_ptr,
+                                current_prev_op,
+                                loc.clone(),
+                            )?;
+                        }
+                    }
+                }
+            }
+
+            ProjectionElem::Downcast(variant_idx) => {
+                if carried_slice_tail_len.is_some() {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(
+                            "slice-tail metadata reached Downcast before the unsized slice field"
+                                .to_string()
+                        )
+                    );
+                }
+                // Downcast is a no-op - it just narrows the type for the next Field access
+                // Store the variant index for use by the next Field projection
+                pending_downcast = Some(*variant_idx);
+                // Don't change current_value
+            }
+
+            ProjectionElem::Index(index_local) => {
+                if carried_slice_tail_len.is_some() {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(
+                            "slice-tail metadata reached Index before the unsized slice field"
+                                .to_string()
+                        )
+                    );
+                }
+                let index_place = mir::Place {
+                    local: *index_local,
+                    projection: vec![],
+                };
+                let (index_value, next_prev_op) = translate_place(
+                    ctx,
+                    body,
+                    &index_place,
+                    value_map,
+                    block_ptr,
+                    current_prev_op,
+                    loc.clone(),
+                )?;
+                current_prev_op = next_prev_op;
+
+                // A projected unsized slice tail is represented as a fat
+                // `MirSliceType` value. Runtime Index only needs the data
+                // pointer, so normalize it before reusing the pointer path.
+                (current_value, current_prev_op) = normalize_slice_value_to_data_ptr(
+                    ctx,
+                    current_value,
+                    block_ptr,
+                    current_prev_op,
+                    loc.clone(),
+                );
+
+                // Determine indexable kind upfront so we drop the immutable borrow
+                // before creating operations (which need &mut ctx).
+                enum IndexableKind {
+                    Array {
+                        element_ty: TypeHandle,
+                    },
+                    Ptr {
+                        element_ty: TypeHandle,
+                        ptr_ty: TypeHandle,
+                    },
+                }
+
+                let cur_ty = current_value.get_type(ctx);
+                let kind = {
+                    let cur_ty_ref = cur_ty.deref(ctx);
+                    if let Some(arr_ty) =
+                        cur_ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>()
+                    {
+                        Ok(IndexableKind::Array {
+                            element_ty: arr_ty.element_type(),
+                        })
+                    } else if let Some(ptr_ty) =
+                        cur_ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>()
+                    {
+                        Ok(IndexableKind::Ptr {
+                            element_ty: ptr_ty.pointee,
+                            ptr_ty: cur_ty,
+                        })
+                    } else {
+                        let ty_dbg = format!("{:?}", cur_ty_ref);
+                        Err(ty_dbg)
+                    }
+                };
+
+                match kind {
+                    Ok(IndexableKind::Array { element_ty }) => {
+                        use dialect_mir::ops::MirExtractArrayElementOp;
+                        let op = Operation::new(
+                            ctx,
+                            MirExtractArrayElementOp::get_concrete_op_info(),
+                            vec![element_ty],
+                            vec![current_value, index_value],
+                            vec![],
+                            0,
+                        );
+                        op.deref_mut(ctx).set_loc(loc.clone());
+
+                        if let Some(prev) = current_prev_op {
+                            op.insert_after(ctx, prev);
+                        } else {
+                            op.insert_at_front(block_ptr, ctx);
+                        }
+
+                        current_value = op.deref(ctx).get_result(0);
+                        current_prev_op = Some(op);
+                    }
+                    Ok(IndexableKind::Ptr { element_ty, ptr_ty }) => {
+                        let offset_op = Operation::new(
+                            ctx,
+                            MirPtrOffsetOp::get_concrete_op_info(),
+                            vec![ptr_ty],
+                            vec![current_value, index_value],
+                            vec![],
+                            0,
+                        );
+                        offset_op.deref_mut(ctx).set_loc(loc.clone());
+                        if let Some(prev) = current_prev_op {
+                            offset_op.insert_after(ctx, prev);
+                        } else {
+                            offset_op.insert_at_front(block_ptr, ctx);
+                        }
+                        current_prev_op = Some(offset_op);
+                        let offset_ptr = offset_op.deref(ctx).get_result(0);
+
+                        let load_op = Operation::new(
+                            ctx,
+                            MirLoadOp::get_concrete_op_info(),
+                            vec![element_ty],
+                            vec![offset_ptr],
+                            vec![],
+                            0,
+                        );
+                        load_op.deref_mut(ctx).set_loc(loc.clone());
+                        let load = MirLoadOp::new(load_op);
+                        if let Some(prev) = current_prev_op {
+                            load.get_operation().insert_after(ctx, prev);
+                        } else {
+                            load.get_operation().insert_at_front(block_ptr, ctx);
+                        }
+
+                        current_value = load.get_operation().deref(ctx).get_result(0);
+                        current_prev_op = Some(load.get_operation());
+                    }
+                    Err(ty_dbg) => {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "Index projection on unsupported type.\n\
+                                 \n  pliron type: {}\n\
+                                 \n  display    : {}\n\
+                                 \n\
+                                 \nIndex handles MirArrayType (extract_array_element) and MirPtrType\n\
+                                 (pointer offset + load, e.g. after Deref on a slice). The type above\n\
+                                 matched neither. A new handler may need to be added.",
+                                ty_dbg,
+                                cur_ty.disp(ctx)
+                            ))
+                        );
+                    }
+                }
+                pending_downcast = None;
+            }
+
+            ProjectionElem::ConstantIndex {
+                offset,
+                min_length: _,
+                from_end,
+            } => {
+                if carried_slice_tail_len.is_some() {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(
+                            "slice-tail metadata reached ConstantIndex before the unsized slice field"
+                                .to_string()
+                        )
+                    );
+                }
+                if *from_end {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(
+                            "ConstantIndex with from_end=true not yet supported"
+                        )
+                    );
+                }
+                let index = *offset as usize;
+
+                // A projected unsized slice tail is represented as a fat
+                // `MirSliceType` value. ConstantIndex only needs the data
+                // pointer, so normalize it before reusing the pointer path.
+                (current_value, current_prev_op) = normalize_slice_value_to_data_ptr(
+                    ctx,
+                    current_value,
+                    block_ptr,
+                    current_prev_op,
+                    loc.clone(),
+                );
+
+                // Determine indexable kind upfront so we drop the immutable borrow
+                // before creating operations (which need &mut ctx).
+                enum ConstIndexKind {
+                    Array {
+                        element_ty: TypeHandle,
+                    },
+                    Ptr {
+                        element_ty: TypeHandle,
+                        ptr_ty: TypeHandle,
+                    },
+                }
+
+                let cur_ty = current_value.get_type(ctx);
+                let kind = {
+                    let cur_ty_ref = cur_ty.deref(ctx);
+                    if let Some(arr_ty) =
+                        cur_ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>()
+                    {
+                        Ok(ConstIndexKind::Array {
+                            element_ty: arr_ty.element_type(),
+                        })
+                    } else if let Some(ptr_ty) =
+                        cur_ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>()
+                    {
+                        Ok(ConstIndexKind::Ptr {
+                            element_ty: ptr_ty.pointee,
+                            ptr_ty: cur_ty,
+                        })
+                    } else {
+                        let ty_dbg = format!("{:?}", cur_ty_ref);
+                        Err(ty_dbg)
+                    }
+                };
+
+                match kind {
+                    Ok(ConstIndexKind::Array { element_ty }) => {
+                        let op = Operation::new(
+                            ctx,
+                            MirExtractFieldOp::get_concrete_op_info(),
+                            vec![element_ty],
+                            vec![current_value],
+                            vec![],
+                            0,
+                        );
+                        op.deref_mut(ctx).set_loc(loc.clone());
+                        let extract_op = MirExtractFieldOp::new(op);
+                        extract_op.set_attr_index(
+                            ctx,
+                            dialect_mir::attributes::FieldIndexAttr(index as u32),
+                        );
+
+                        if let Some(prev) = current_prev_op {
+                            extract_op.get_operation().insert_after(ctx, prev);
+                        } else {
+                            extract_op.get_operation().insert_at_front(block_ptr, ctx);
+                        }
+
+                        current_value = extract_op.get_operation().deref(ctx).get_result(0);
+                        current_prev_op = Some(extract_op.get_operation());
+                    }
+                    Ok(ConstIndexKind::Ptr { element_ty, ptr_ty }) => {
+                        // Create constant index value
+                        let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+                        let apint = APInt::from_u32(index as u32, NonZeroUsize::new(32).unwrap());
+                        let index_attr =
+                            pliron::builtin::attributes::IntegerAttr::new(i32_ty, apint);
+                        use dialect_mir::ops::MirConstantOp;
+                        let const_op = Operation::new(
+                            ctx,
+                            MirConstantOp::get_concrete_op_info(),
+                            vec![i32_ty.into()],
+                            vec![],
+                            vec![],
+                            0,
+                        );
+                        const_op.deref_mut(ctx).set_loc(loc.clone());
+                        let const_mir = MirConstantOp::new(const_op);
+                        const_mir.set_attr_value(ctx, index_attr);
+                        if let Some(prev) = current_prev_op {
+                            const_mir.get_operation().insert_after(ctx, prev);
+                        } else {
+                            const_mir.get_operation().insert_at_front(block_ptr, ctx);
+                        }
+                        current_prev_op = Some(const_mir.get_operation());
+                        let index_value = const_mir.get_operation().deref(ctx).get_result(0);
+
+                        // Pointer offset
+                        let offset_op = Operation::new(
+                            ctx,
+                            MirPtrOffsetOp::get_concrete_op_info(),
+                            vec![ptr_ty],
+                            vec![current_value, index_value],
+                            vec![],
+                            0,
+                        );
+                        offset_op.deref_mut(ctx).set_loc(loc.clone());
+                        if let Some(prev) = current_prev_op {
+                            offset_op.insert_after(ctx, prev);
+                        } else {
+                            offset_op.insert_at_front(block_ptr, ctx);
+                        }
+                        current_prev_op = Some(offset_op);
+                        let offset_ptr = offset_op.deref(ctx).get_result(0);
+
+                        // Load element
+                        let load_op = Operation::new(
+                            ctx,
+                            MirLoadOp::get_concrete_op_info(),
+                            vec![element_ty],
+                            vec![offset_ptr],
+                            vec![],
+                            0,
+                        );
+                        load_op.deref_mut(ctx).set_loc(loc.clone());
+                        let load = MirLoadOp::new(load_op);
+                        if let Some(prev) = current_prev_op {
+                            load.get_operation().insert_after(ctx, prev);
+                        } else {
+                            load.get_operation().insert_at_front(block_ptr, ctx);
+                        }
+
+                        current_value = load.get_operation().deref(ctx).get_result(0);
+                        current_prev_op = Some(load.get_operation());
+                    }
+                    Err(ty_dbg) => {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "ConstantIndex projection on unsupported type.\n\
+                                 \n  pliron type: {}\n\
+                                 \n  display    : {}\n\
+                                 \n  index      : {}\n\
+                                 \n\
+                                 \nConstantIndex handles MirArrayType (extractvalue) and MirPtrType\n\
+                                 (pointer offset + load, e.g. after Deref on a slice). The type above\n\
+                                 matched neither. A new handler may need to be added.",
+                                ty_dbg,
+                                cur_ty.disp(ctx),
+                                index
+                            ))
+                        );
+                    }
+                }
+                pending_downcast = None;
+            }
+
+            ProjectionElem::Subslice { from, to, from_end } => {
+                if carried_slice_tail_len.is_some() {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(
+                            "slice-tail metadata reached Subslice before the unsized slice field"
+                                .to_string()
+                        )
+                    );
+                }
+                if *from_end {
+                    let Some(is_mutable) = preserved_slice_deref_mutability.take() else {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(
+                                "slice Subslice reached iterative lowering without preserved fat-pointer metadata"
+                                    .to_string()
+                            )
+                        );
+                    };
+                    let element_ty = {
+                        let current_ty = current_value.get_type(ctx);
+                        let current_ty = current_ty.deref(ctx);
+                        let Some(slice_ty) =
+                            current_ty.downcast_ref::<dialect_mir::types::MirSliceType>()
+                        else {
+                            return input_err!(
+                                loc,
+                                TranslationErr::unsupported(
+                                    "slice Subslice preserved value is not MirSliceType"
+                                        .to_string()
+                                )
+                            );
+                        };
+                        slice_ty.element_type()
+                    };
+
+                    let (subslice, last_op) = emit_slice_subslice_value(
+                        ctx,
+                        current_value,
+                        element_ty,
+                        is_mutable,
+                        *from,
+                        *to,
+                        block_ptr,
+                        current_prev_op,
+                        loc.clone(),
+                    )?;
+                    current_value = subslice;
+                    current_prev_op = Some(last_op);
+
+                    // A subsequent element projection needs only the adjusted
+                    // data pointer. Keep a terminal Subslice as a fat value so
+                    // PtrMetadata/borrow users can observe the rebuilt length.
+                    if matches!(
+                        place.projection.get(proj_idx + 1),
+                        Some(ProjectionElem::Index(_))
+                            | Some(ProjectionElem::ConstantIndex {
+                                from_end: false,
+                                ..
+                            })
+                    ) {
+                        let data_ptr_ty: TypeHandle = dialect_mir::types::MirPtrType::get_generic(
+                            ctx, element_ty, is_mutable,
+                        )
+                        .into();
+                        let extract_ptr = Operation::new(
+                            ctx,
+                            MirExtractFieldOp::get_concrete_op_info(),
+                            vec![data_ptr_ty],
+                            vec![current_value],
+                            vec![],
+                            0,
+                        );
+                        extract_ptr.deref_mut(ctx).set_loc(loc.clone());
+                        MirExtractFieldOp::new(extract_ptr)
+                            .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
+                        extract_ptr.insert_after(ctx, last_op);
+                        current_value = extract_ptr.deref(ctx).get_result(0);
+                        current_prev_op = Some(extract_ptr);
+                    }
+                } else {
+                    (current_value, current_prev_op) = emit_array_subslice_value(
+                        ctx,
+                        current_value,
+                        *from,
+                        *to,
+                        block_ptr,
+                        current_prev_op,
+                        loc.clone(),
+                    )?;
+                    preserved_slice_deref_mutability = None;
+                }
+                pending_downcast = None;
+            }
+
+            // Unsupported projection types
+            other => {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Projection element {:?} not yet implemented in iterative mode",
+                        other
+                    ))
+                );
+            }
+        }
+
+        // Advance the running Rust type with rustc_public's own projection
+        // typing (single source of truth; see the comment on
+        // `current_rust_ty` above). For well-formed MIR this never fails;
+        // if it does, surface the projection element and the type it was
+        // applied to so the bail-out is actionable.
+        current_rust_ty = projection.ty(current_rust_ty).map_err(|e| {
+            input_error!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Failed to type projection {:?} applied to {:?}: {:?}",
+                    projection, current_rust_ty, e
+                ))
+            )
+        })?;
+    }
+
+    if carried_slice_tail_len.is_some() {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(
+                "place projection ended on a slice-tailed DST before its metadata was attached to the slice field"
+                    .to_string()
+            )
+        );
+    }
+
+    Ok((current_value, current_prev_op))
+}
diff --git a/crates/mir-importer/src/translator/rvalue/place_read.rs b/crates/mir-importer/src/translator/rvalue/place_read.rs
new file mode 100644
index 0000000000..d1e6a0f392
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/place_read.rs
@@ -0,0 +1,1245 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! [`translate_place`]: read-strategy classification and `apply_*`
+//! projection helpers.
+
+use super::const_bytes::translate_zero_sized_constant_value;
+use super::const_enum::create_ghost_enum_default;
+use super::place_addr::translate_place_address;
+use super::place_iter::translate_place_iterative;
+use super::pointee::{
+    PointeeKind, indexed_element_ptr_type, is_empty_tuple_type, mir_ptr_pointee,
+    pointer_type_pointee_kind, projected_pointer_type, rust_ty_is_slice, slice_like_element_type,
+    tuple_has_over_aligned_zst_field,
+};
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::facts;
+use crate::translator::types;
+use crate::translator::values::ValueMap;
+use dialect_mir::ops::{MirExtractFieldOp, MirLoadOp, MirUndefOp};
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::printable::Printable;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use pliron::{input_err, input_error, input_error_noloc};
+use rustc_public::mir;
+use rustc_public::mir::ProjectionElem;
+use rustc_public_bridge::IndexedVal;
+use std::num::NonZeroUsize;
+
+/// Translate MIR [`Place`](mir::Place) reads to pliron IR SSA [`Value`]s.
+///
+/// Reads for `Copy(place)` and `Move(place)` first ask a side-effect-free
+/// classifier whether the place has a real final load address. Addressable
+/// reads use the same
+/// `translate_place_address` walker as refs, raw addresses, and writes, then
+/// emit one `mir.load` at the end.
+///
+/// Places that are not representable as one final load address use the explicit
+/// value fallback below. The fallback handles value-only projections such as
+/// enum payload extraction, tuple field extraction, ZST reads, and no-slot
+/// locals.
+///
+/// A bare slot-backed local is the trivial addressable case: it reads by
+/// loading the local's alloca slot once. Projected reads compose address
+/// operations for `field`, `index`, and `deref` when the whole projection
+/// chain stays addressable.
+///
+/// # Value fallback and ghost locals
+///
+/// A local may have no backing slot in `value_map` if rustc optimised away its
+/// assignment, or if the local is ZST and has no runtime footprint.
+///
+/// When such a local is still *used* within a block (e.g. `discriminant(_6)`)
+/// and happens to be an enum, we synthesise a variant-0 default via
+/// `create_ghost_enum_default`. Non-enum ghost locals currently produce an
+/// error -- extend this match if new patterns appear in future toolchains.
+///
+/// This is the SSA equivalent of rustc's codegen reading an uninitialized
+/// alloca, which produces LLVM `undef`.
+///
+/// # Returns
+///
+/// `(value, last_inserted_op)` -- the pliron IR value for the place and the last
+/// operation inserted into the block (for op-ordering bookkeeping).
+pub fn translate_place(
+    ctx: &mut Context,
+    body: &mir::Body,
+    place: &mir::Place,
+    value_map: &ValueMap,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    match classify_place_read_strategy(ctx, place, value_map)? {
+        PlaceReadStrategy::Address => {
+            if let Some((value, last_op)) = translate_place_load_from_address(
+                ctx,
+                body,
+                place,
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )? {
+                return Ok((value, last_op));
+            }
+
+            input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "place read {:?} was classified as addressable but did not lower to a \
+                     final load address",
+                    place.projection
+                ))
+            )
+        }
+        PlaceReadStrategy::ValueFallback => {
+            translate_place_value_fallback(ctx, body, place, value_map, block_ptr, prev_op, loc)
+        }
+    }
+}
+
+// ============================================================================
+// Place Read Strategy and Address Path
+// ============================================================================
+
+enum PlaceReadStrategy {
+    /// Read the place by walking to its in-memory address and loading once.
+    Address,
+    /// Read the place through value projection because it is not representable
+    /// as one final load address.
+    ValueFallback,
+}
+
+/// Choose how to lower MIR place reads.
+///
+/// This deliberately does not emit IR. The address walker may create several
+/// operations before discovering an unsupported projection, so read lowering
+/// must not call it speculatively and then fall back to value projections.
+///
+/// Conservative fallback is part of the design. Enum payload addressing,
+/// unsupported slice forms, ZST results, and computed/no-slot values remain on
+/// the value path until they have dedicated address-lowering support.
+fn classify_place_read_strategy(
+    ctx: &mut Context,
+    place: &mir::Place,
+    value_map: &ValueMap,
+) -> TranslationResult<PlaceReadStrategy> {
+    let Some(slot) = value_map.get_slot(place.local) else {
+        return Ok(PlaceReadStrategy::ValueFallback);
+    };
+
+    if place.projection.is_empty() {
+        let Some(final_pointee) = mir_ptr_pointee(ctx, slot.get_type(ctx)) else {
+            return Ok(PlaceReadStrategy::ValueFallback);
+        };
+        if types::is_zst_type(ctx, final_pointee) {
+            return Ok(PlaceReadStrategy::ValueFallback);
+        }
+        return Ok(PlaceReadStrategy::Address);
+    };
+
+    let mut current_ptr_ty = slot.get_type(ctx);
+    let mut current_is_slice_data = false;
+
+    for (proj_idx, elem) in place.projection.iter().enumerate() {
+        let entered_as_slice_data = current_is_slice_data;
+        current_is_slice_data = false;
+
+        match elem {
+            mir::ProjectionElem::Deref => {
+                let Some(place_ty) = mir_ptr_pointee(ctx, current_ptr_ty) else {
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                };
+
+                if is_empty_tuple_type(ctx, place_ty) {
+                    continue;
+                }
+
+                if let Some(elem_ty) = slice_like_element_type(ctx, place_ty) {
+                    let is_last = proj_idx + 1 == place.projection.len();
+                    if is_last {
+                        // The address walker returns a loaded fat value for a
+                        // trailing slice-shaped deref. This helper handles only
+                        // paths whose final result is an address to load from.
+                        return Ok(PlaceReadStrategy::ValueFallback);
+                    }
+
+                    match &place.projection[proj_idx + 1] {
+                        mir::ProjectionElem::Field(_, field_rust_ty) => {
+                            if rust_ty_is_slice(field_rust_ty)
+                                || types::slice_tail_element_ty(field_rust_ty).is_some()
+                            {
+                                // A direct slice tail or a nested slice-tailed DST needs
+                                // fat-pointer metadata that the address read path does not carry
+                                // across fields. Keep it on the value path.
+                                return Ok(PlaceReadStrategy::ValueFallback);
+                            }
+
+                            current_ptr_ty = dialect_mir::types::MirPtrType::get_generic(
+                                ctx, elem_ty, /* is_mutable */ false,
+                            )
+                            .into();
+                        }
+                        mir::ProjectionElem::Index(_)
+                        | mir::ProjectionElem::ConstantIndex { .. } => {
+                            current_ptr_ty = dialect_mir::types::MirPtrType::get_generic(
+                                ctx, elem_ty, /* is_mutable */ false,
+                            )
+                            .into();
+                            current_is_slice_data = true;
+                        }
+                        _ => return Ok(PlaceReadStrategy::ValueFallback),
+                    }
+                } else if place_ty.deref(ctx).is::<dialect_mir::types::MirPtrType>() {
+                    current_ptr_ty = place_ty;
+                } else {
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                }
+            }
+
+            mir::ProjectionElem::Field(_, field_ty) => {
+                let Some(pointee) = mir_ptr_pointee(ctx, current_ptr_ty) else {
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                };
+                let is_struct_or_tuple =
+                    pointee.deref(ctx).is::<dialect_mir::types::MirStructType>()
+                        || pointee.deref(ctx).is::<dialect_mir::types::MirTupleType>();
+                if !is_struct_or_tuple {
+                    // `mir.field_addr` verifies struct, tuple, union and enum
+                    // pointees; anything else stays on the value path, where
+                    // `mir.extract_field` supports it instead.
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                }
+                if tuple_has_over_aligned_zst_field(ctx, pointee) {
+                    // Code-shape guard: the address path's final load states
+                    // natural alignment only, while a zero-byte
+                    // `repr(align(N))` field raises the tuple's ABI alignment
+                    // without appearing in its LLVM storage type. Keep such
+                    // tuples on the value path, which moves the whole
+                    // aggregate at its recorded alignment. Gate shape from
+                    // PR #715 (vyncint), with the byte-size gap closed.
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                }
+
+                let field_type = types::translate_type(ctx, field_ty)?;
+                let Some(projected_ptr_ty) = projected_pointer_type(
+                    ctx,
+                    current_ptr_ty,
+                    field_type,
+                    /* is_mutable */ false,
+                ) else {
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                };
+
+                current_ptr_ty = projected_ptr_ty;
+            }
+
+            mir::ProjectionElem::Index(_) => {
+                let Some((mut pointee_kind, addr_space)) =
+                    pointer_type_pointee_kind(ctx, current_ptr_ty)
+                else {
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                };
+                if entered_as_slice_data {
+                    pointee_kind = PointeeKind::Direct;
+                }
+                current_ptr_ty = indexed_element_ptr_type(
+                    ctx,
+                    current_ptr_ty,
+                    pointee_kind,
+                    addr_space,
+                    /* is_mutable */ false,
+                );
+            }
+
+            mir::ProjectionElem::ConstantIndex { from_end, .. } => {
+                // rustc emits from-end ConstantIndex only for runtime-length
+                // slices. Require the immediately preceding fat-slice deref;
+                // arrays never reach stable MIR with `from_end=true`.
+                if *from_end && !entered_as_slice_data {
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                }
+                let Some((mut pointee_kind, addr_space)) =
+                    pointer_type_pointee_kind(ctx, current_ptr_ty)
+                else {
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                };
+                if entered_as_slice_data {
+                    pointee_kind = PointeeKind::Direct;
+                }
+                current_ptr_ty = indexed_element_ptr_type(
+                    ctx,
+                    current_ptr_ty,
+                    pointee_kind,
+                    addr_space,
+                    /* is_mutable */ false,
+                );
+            }
+
+            mir::ProjectionElem::Subslice { from, to, from_end } => {
+                // PlaceElem::Subslice uses from_end=false for arrays and
+                // from_end=true for slices. A slice subslice is unsized and
+                // therefore is not a final load address; references/raw
+                // pointers to it are handled by the address walker directly.
+                if *from_end {
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                }
+
+                let (element_ty, array_len, addr_space) = {
+                    let ptr_ty = current_ptr_ty.deref(ctx);
+                    let Some(ptr_ty) = ptr_ty.downcast_ref::<dialect_mir::types::MirPtrType>()
+                    else {
+                        return Ok(PlaceReadStrategy::ValueFallback);
+                    };
+                    let array_ty = ptr_ty.pointee.deref(ctx);
+                    let Some(array_ty) =
+                        array_ty.downcast_ref::<dialect_mir::types::MirArrayType>()
+                    else {
+                        return Ok(PlaceReadStrategy::ValueFallback);
+                    };
+                    (
+                        array_ty.element_type(),
+                        array_ty.size(),
+                        ptr_ty.address_space,
+                    )
+                };
+                let Some(projected_len) = to.checked_sub(*from) else {
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                };
+                if *to > array_len {
+                    return Ok(PlaceReadStrategy::ValueFallback);
+                }
+
+                let projected_array_ty: TypeHandle =
+                    dialect_mir::types::MirArrayType::get(ctx, element_ty, projected_len).into();
+                current_ptr_ty = dialect_mir::types::MirPtrType::get(
+                    ctx,
+                    projected_array_ty,
+                    /* is_mutable */ false,
+                    addr_space,
+                )
+                .into();
+            }
+
+            // Enum payload addressing is a value projection, not a final load
+            // address. Other unknown projections stay on the conservative path.
+            mir::ProjectionElem::Downcast(_) => return Ok(PlaceReadStrategy::ValueFallback),
+            _ => return Ok(PlaceReadStrategy::ValueFallback),
+        }
+    }
+
+    let Some(final_pointee) = mir_ptr_pointee(ctx, current_ptr_ty) else {
+        return Ok(PlaceReadStrategy::ValueFallback);
+    };
+    if types::is_zst_type(ctx, final_pointee) {
+        return Ok(PlaceReadStrategy::ValueFallback);
+    }
+
+    Ok(PlaceReadStrategy::Address)
+}
+
+/// Lower an addressable place read by computing its in-memory address, then
+/// emitting one final `mir.load` from that address.
+///
+/// Returning `None` means the address walker did not produce a final load
+/// address. `translate_place` treats that as a checker/walker divergence when
+/// the classifier selected the address path.
+#[allow(clippy::too_many_arguments)]
+fn translate_place_load_from_address(
+    ctx: &mut Context,
+    body: &mir::Body,
+    place: &mir::Place,
+    value_map: &ValueMap,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<Option<(Value, Option<Ptr<Operation>>)>> {
+    let Some((addr, addr_prev_op)) = translate_place_address(
+        ctx,
+        body,
+        value_map,
+        place,
+        /* is_mutable */ false,
+        block_ptr,
+        prev_op,
+        loc.clone(),
+    )?
+    else {
+        return Ok(None);
+    };
+
+    let Some(pointee) = mir_ptr_pointee(ctx, addr.get_type(ctx)) else {
+        return Ok(None);
+    };
+    if types::is_zst_type(ctx, pointee) {
+        return Ok(None);
+    }
+
+    let load_op = Operation::new(
+        ctx,
+        MirLoadOp::get_concrete_op_info(),
+        vec![pointee],
+        vec![addr],
+        vec![],
+        0,
+    );
+    load_op.deref_mut(ctx).set_loc(loc);
+    match addr_prev_op.or(prev_op) {
+        Some(prev) => load_op.insert_after(ctx, prev),
+        None => load_op.insert_at_front(block_ptr, ctx),
+    }
+
+    let value = load_op.deref(ctx).get_result(0);
+    Ok(Some((value, Some(load_op))))
+}
+
+// ============================================================================
+// Place Read Value Fallback
+// ============================================================================
+
+/// Explicit value-projection fallback for place reads that are not addressable.
+///
+/// Handles value-only reads, including enum downcast/payload extraction, tuple
+/// field extraction, no-slot ghost locals, and ZST synthesis.
+fn translate_place_value_fallback(
+    ctx: &mut Context,
+    body: &mir::Body,
+    place: &mir::Place,
+    value_map: &ValueMap,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    if place.projection.is_empty() {
+        let local = place.local;
+        // Alloca + load/store model: emit `mir.load slot`. Every non-ZST local
+        // has a slot allocated in the entry block, so the loaded value is the
+        // local's current contents. `mem2reg` promotes these loads back into
+        // SSA form when the slot's address doesn't escape.
+        if let Some((load_op, val)) = value_map.load_local(ctx, local, block_ptr, prev_op) {
+            return Ok((val, Some(load_op)));
+        }
+        // ZST or unsupported local -- synthesise a value for it so callers
+        // can uniformly consume a `Value`. An enum gets its variant-0 default
+        // (ghost-enum), a struct/tuple ZST gets an empty aggregate. Loads of
+        // these are otherwise meaningless.
+        let local_decl = &body.locals()[local];
+        let ty_ptr = types::translate_type(ctx, &local_decl.ty)?;
+        if ty_ptr.deref(ctx).is::<dialect_mir::types::MirEnumType>() {
+            let op = create_ghost_enum_default(ctx, ty_ptr, loc.clone());
+            match prev_op {
+                Some(p) => op.insert_after(ctx, p),
+                None => op.insert_at_front(block_ptr, ctx),
+            }
+            let val = op.deref(ctx).get_result(0);
+            return Ok((val, Some(op)));
+        }
+        if types::is_zst_type(ctx, ty_ptr) {
+            return translate_zero_sized_constant_value(ctx, ty_ptr, block_ptr, prev_op, loc);
+        }
+        input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "Local {} has no alloca slot and is not a ZST",
+                Into::<usize>::into(local)
+            ))
+        )
+    } else {
+        // Handle projections (place.field, place[index], etc.)
+        // For now, handle tuple field projections (_3.0, _3.1, etc.)
+        if place.projection.len() == 1 {
+            // Check if this is a tuple field projection
+            match &place.projection[0] {
+                ProjectionElem::Deref => {
+                    // Dereference: *ptr
+                    // The base value must be a pointer
+                    let base_place = mir::Place {
+                        local: place.local,
+                        projection: vec![],
+                    };
+                    let (base_value, prev_op_after_base) = translate_place(
+                        ctx,
+                        body,
+                        &base_place,
+                        value_map,
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                    )?;
+
+                    // Get the result type from the pointer's element type
+                    let base_ty = base_value.get_type(ctx);
+
+                    // Extract pointee info while holding the borrow, then release before fallback
+                    let pointee_info: Option<(pliron::r#type::TypeHandle, bool)> = {
+                        let base_ty_ref = base_ty.deref(ctx);
+                        base_ty_ref
+                            .downcast_ref::<dialect_mir::types::MirPtrType>()
+                            .map(|ptr_ty| {
+                                let pointee = ptr_ty.pointee;
+                                let pointee_ref = pointee.deref(ctx);
+
+                                // Check if pointee is a ZST (empty tuple) - this happens for SharedArray
+                                // which is a zero-sized type. For ZSTs, dereferencing just returns the
+                                // same pointer (there's nothing to load).
+                                let is_empty_tuple = pointee_ref
+                                    .downcast_ref::<dialect_mir::types::MirTupleType>()
+                                    .is_some_and(|tt| tt.get_types().is_empty());
+
+                                (pointee, is_empty_tuple)
+                            })
+                    };
+
+                    let (res_ty, is_zst) = pointee_info.unwrap_or_else(|| {
+                        // Fallback: assume i32 if we can't determine the type
+                        (types::get_i32_type(ctx).to_handle(), false)
+                    });
+
+                    // For ZST pointees (like SharedArray), don't create a load op.
+                    // Instead, just return the pointer itself - dereferencing a pointer
+                    // to a ZST and taking a reference back gives the same pointer.
+                    // NOTE: We still load from shared memory pointers (addrspace:3) -
+                    // the ZST check only applies to SharedArray itself, not to data
+                    // stored in shared memory.
+                    if is_zst {
+                        return Ok((base_value, prev_op_after_base));
+                    }
+
+                    let op = Operation::new(
+                        ctx,
+                        MirLoadOp::get_concrete_op_info(),
+                        vec![res_ty],
+                        vec![base_value],
+                        vec![],
+                        0,
+                    );
+                    op.deref_mut(ctx).set_loc(loc);
+
+                    let load_op = MirLoadOp::new(op);
+
+                    if let Some(prev) = prev_op_after_base {
+                        load_op.get_operation().insert_after(ctx, prev);
+                    } else {
+                        load_op.get_operation().insert_at_front(block_ptr, ctx);
+                    }
+
+                    let loaded_val = load_op.get_operation().deref(ctx).get_result(0);
+
+                    Ok((loaded_val, Some(load_op.get_operation())))
+                }
+                ProjectionElem::Field(field_idx, ty) => {
+                    // Get the base value (the tuple/struct).
+                    //
+                    // In the alloca model the recursive call may emit a
+                    // `mir.load <slot>` into the block to materialise the
+                    // aggregate value; we must anchor our `mir.extract_field`
+                    // **after** that load, otherwise the extract ends up
+                    // before the load (and subsequent ops keep pushing the
+                    // load past the block's terminator).
+                    let base_place = mir::Place {
+                        local: place.local,
+                        projection: vec![],
+                    };
+                    let (base_value, prev_op_after_base) = translate_place(
+                        ctx,
+                        body,
+                        &base_place,
+                        value_map,
+                        block_ptr,
+                        prev_op,
+                        loc.clone(),
+                    )?;
+                    let anchor = prev_op_after_base.or(prev_op);
+
+                    let field_type = types::translate_type(ctx, ty)?;
+
+                    let op = Operation::new(
+                        ctx,
+                        MirExtractFieldOp::get_concrete_op_info(),
+                        vec![field_type],
+                        vec![base_value],
+                        vec![],
+                        0,
+                    );
+                    op.deref_mut(ctx).set_loc(loc);
+
+                    let extract_op = MirExtractFieldOp::new(op);
+                    extract_op.set_attr_index(
+                        ctx,
+                        dialect_mir::attributes::FieldIndexAttr(*field_idx as u32),
+                    );
+
+                    if let Some(prev) = anchor {
+                        extract_op.get_operation().insert_after(ctx, prev);
+                    } else {
+                        extract_op.get_operation().insert_at_front(block_ptr, ctx);
+                    }
+
+                    let field_value = extract_op.get_operation().deref(ctx).get_result(0);
+                    Ok((field_value, Some(extract_op.get_operation())))
+                }
+                ProjectionElem::Downcast(_variant_idx) => {
+                    // Downcast by itself is a no-op - it just narrows the type.
+                    // The actual field extraction happens with the following Field projection.
+                    // For now, just return the base value unchanged.
+                    let base_place = mir::Place {
+                        local: place.local,
+                        projection: vec![],
+                    };
+                    translate_place(ctx, body, &base_place, value_map, block_ptr, prev_op, loc)
+                }
+                ProjectionElem::Index(index_local) => {
+                    // Array indexing with a runtime index: array[index]
+                    //
+                    // Alloca model: `array` is backed by a stack slot whose
+                    // pointee is `MirArrayType`, so we compute the element
+                    // address from that slot directly (no MirRefOp needed)
+                    // and load the element.
+
+                    let mut current_prev = prev_op;
+
+                    let Some(arr_ptr) = value_map.get_slot(place.local) else {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(format!(
+                                "Array local {} has no alloca slot; cannot index",
+                                Into::<usize>::into(place.local)
+                            ))
+                        );
+                    };
+
+                    // Get the index value
+                    let index_place = mir::Place {
+                        local: *index_local,
+                        projection: vec![],
+                    };
+                    let (index_value, prev_op_after_index) = translate_place(
+                        ctx,
+                        body,
+                        &index_place,
+                        value_map,
+                        block_ptr,
+                        current_prev,
+                        loc.clone(),
+                    )?;
+                    current_prev = prev_op_after_index;
+
+                    // Get element type from pointer type
+                    let arr_ptr_ty = arr_ptr.get_type(ctx);
+                    let element_ty = {
+                        let arr_ptr_ty_ref = arr_ptr_ty.deref(ctx);
+                        let mir_ptr_ty = arr_ptr_ty_ref
+                            .downcast_ref::<dialect_mir::types::MirPtrType>()
+                            .expect("Memory array pointer should be MirPtrType");
+                        let array_ty = mir_ptr_ty.pointee;
+                        let array_ty_ref = array_ty.deref(ctx);
+                        array_ty_ref
+                            .downcast_ref::<dialect_mir::types::MirArrayType>()
+                            .expect("Pointee should be MirArrayType")
+                            .element_type()
+                    };
+
+                    // Projection keeps the slot address's machine mutability,
+                    // address space, and pointer kind (or explicitly erases
+                    // only the kind). A read does not require manufacturing
+                    // an immutable address type.
+                    let elem_ptr_ty = projected_pointer_type(
+                        ctx, arr_ptr_ty, element_ty,
+                        /* legacy requested mutability, ignored */ false,
+                    )
+                    .expect("array slot must be a MirPtrType");
+
+                    // Create MirArrayElementAddrOp to get element pointer
+                    use dialect_mir::ops::MirArrayElementAddrOp;
+                    let addr_op = Operation::new(
+                        ctx,
+                        MirArrayElementAddrOp::get_concrete_op_info(),
+                        vec![elem_ptr_ty],
+                        vec![arr_ptr, index_value],
+                        vec![],
+                        0,
+                    );
+                    addr_op.deref_mut(ctx).set_loc(loc.clone());
+
+                    if let Some(prev) = current_prev {
+                        addr_op.insert_after(ctx, prev);
+                    } else {
+                        addr_op.insert_at_front(block_ptr, ctx);
+                    }
+                    current_prev = Some(addr_op);
+
+                    let elem_ptr = addr_op.deref(ctx).get_result(0);
+
+                    // Load the element value
+                    use dialect_mir::ops::MirLoadOp;
+                    let load_op = Operation::new(
+                        ctx,
+                        MirLoadOp::get_concrete_op_info(),
+                        vec![element_ty],
+                        vec![elem_ptr],
+                        vec![],
+                        0,
+                    );
+                    load_op.deref_mut(ctx).set_loc(loc);
+
+                    if let Some(prev) = current_prev {
+                        load_op.insert_after(ctx, prev);
+                    } else {
+                        load_op.insert_at_front(block_ptr, ctx);
+                    }
+
+                    let result = load_op.deref(ctx).get_result(0);
+                    Ok((result, Some(load_op)))
+                }
+                ProjectionElem::ConstantIndex {
+                    offset,
+                    min_length: _,
+                    from_end,
+                } => {
+                    // Array indexing with a compile-time constant index.
+                    //
+                    // Alloca model: the array local already has a `*mut [T; N]`
+                    // slot, so compute the element address via
+                    // `MirConstantOp` + `MirArrayElementAddrOp` and load.
+                    // `mem2reg` collapses the resulting load-after-store pairs
+                    // back into SSA extracts for promotable arrays.
+
+                    let index = if *from_end {
+                        return input_err!(
+                            loc,
+                            TranslationErr::unsupported(
+                                "ConstantIndex with from_end=true not yet supported"
+                            )
+                        );
+                    } else {
+                        *offset as usize
+                    };
+
+                    // Load the current array value if we don't have a slot (ZST/edge case)
+                    // so that we fall back to the SSA extract-field behaviour.
+                    let Some(arr_ptr) = value_map.get_slot(place.local) else {
+                        // ZST / no-slot fallback: materialise the whole
+                        // aggregate and extract. Anchor the extract after
+                        // whatever the base-place materialiser inserted.
+                        let base_place = mir::Place {
+                            local: place.local,
+                            projection: vec![],
+                        };
+                        let (array_value, prev_op_after_base) = translate_place(
+                            ctx,
+                            body,
+                            &base_place,
+                            value_map,
+                            block_ptr,
+                            prev_op,
+                            loc.clone(),
+                        )?;
+                        let anchor = prev_op_after_base.or(prev_op);
+
+                        let array_ty = array_value.get_type(ctx);
+                        let element_ty = {
+                            let array_ty_ref = array_ty.deref(ctx);
+                            if let Some(arr_ty) =
+                                array_ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>()
+                            {
+                                arr_ty.element_type()
+                            } else {
+                                return input_err!(
+                                    loc,
+                                    TranslationErr::unsupported(format!(
+                                        "ConstantIndex projection on non-array type: {}",
+                                        array_ty.disp(ctx)
+                                    ))
+                                );
+                            }
+                        };
+
+                        let op = Operation::new(
+                            ctx,
+                            MirExtractFieldOp::get_concrete_op_info(),
+                            vec![element_ty],
+                            vec![array_value],
+                            vec![],
+                            0,
+                        );
+                        op.deref_mut(ctx).set_loc(loc);
+
+                        let extract_op = MirExtractFieldOp::new(op);
+                        extract_op.set_attr_index(
+                            ctx,
+                            dialect_mir::attributes::FieldIndexAttr(index as u32),
+                        );
+
+                        if let Some(prev) = anchor {
+                            extract_op.get_operation().insert_after(ctx, prev);
+                        } else {
+                            extract_op.get_operation().insert_at_front(block_ptr, ctx);
+                        }
+
+                        let result = extract_op.get_operation().deref(ctx).get_result(0);
+                        return Ok((result, Some(extract_op.get_operation())));
+                    };
+
+                    // Slot-backed path: GEP + load from the slot.
+                    let mut current_prev = prev_op;
+
+                    let (element_ty, arr_ptr_ty) = {
+                        let arr_ptr_ty = arr_ptr.get_type(ctx);
+                        let arr_ptr_ty_ref = arr_ptr_ty.deref(ctx);
+                        let mir_ptr_ty = arr_ptr_ty_ref
+                            .downcast_ref::<dialect_mir::types::MirPtrType>()
+                            .ok_or_else(|| {
+                                input_error!(
+                                    loc.clone(),
+                                    TranslationErr::unsupported(format!(
+                                        "ConstantIndex base slot is not a pointer: {}",
+                                        arr_ptr_ty.disp(ctx)
+                                    ))
+                                )
+                            })?;
+                        let array_ty_ref = mir_ptr_ty.pointee.deref(ctx);
+                        let elem_ty = array_ty_ref
+                            .downcast_ref::<dialect_mir::types::MirArrayType>()
+                            .ok_or_else(|| {
+                                input_error_noloc!(TranslationErr::unsupported(
+                                    "ConstantIndex base slot pointee is not MirArrayType"
+                                ))
+                            })?
+                            .element_type();
+                        (elem_ty, arr_ptr_ty)
+                    };
+
+                    use dialect_mir::ops::MirConstantOp;
+                    use pliron::builtin::attributes::IntegerAttr;
+
+                    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signed);
+                    let index_apint = APInt::from_i64(index as i64, NonZeroUsize::new(64).unwrap());
+                    let index_attr = IntegerAttr::new(i64_ty, index_apint);
+
+                    let const_op_ptr = Operation::new(
+                        ctx,
+                        MirConstantOp::get_concrete_op_info(),
+                        vec![i64_ty.into()],
+                        vec![],
+                        vec![],
+                        0,
+                    );
+                    const_op_ptr.deref_mut(ctx).set_loc(loc.clone());
+                    MirConstantOp::new(const_op_ptr).set_attr_value(ctx, index_attr);
+                    if let Some(prev) = current_prev {
+                        const_op_ptr.insert_after(ctx, prev);
+                    } else {
+                        const_op_ptr.insert_at_front(block_ptr, ctx);
+                    }
+                    current_prev = Some(const_op_ptr);
+                    let index_value = const_op_ptr.deref(ctx).get_result(0);
+
+                    let elem_ptr_ty = projected_pointer_type(
+                        ctx, arr_ptr_ty, element_ty,
+                        /* legacy requested mutability, ignored */ false,
+                    )
+                    .expect("array slot must be a MirPtrType");
+
+                    use dialect_mir::ops::MirArrayElementAddrOp;
+                    let addr_op = Operation::new(
+                        ctx,
+                        MirArrayElementAddrOp::get_concrete_op_info(),
+                        vec![elem_ptr_ty],
+                        vec![arr_ptr, index_value],
+                        vec![],
+                        0,
+                    );
+                    addr_op.deref_mut(ctx).set_loc(loc.clone());
+                    if let Some(prev) = current_prev {
+                        addr_op.insert_after(ctx, prev);
+                    } else {
+                        addr_op.insert_at_front(block_ptr, ctx);
+                    }
+                    current_prev = Some(addr_op);
+                    let elem_ptr = addr_op.deref(ctx).get_result(0);
+
+                    let load_op = Operation::new(
+                        ctx,
+                        MirLoadOp::get_concrete_op_info(),
+                        vec![element_ty],
+                        vec![elem_ptr],
+                        vec![],
+                        0,
+                    );
+                    load_op.deref_mut(ctx).set_loc(loc);
+                    if let Some(prev) = current_prev {
+                        load_op.insert_after(ctx, prev);
+                    } else {
+                        load_op.insert_at_front(block_ptr, ctx);
+                    }
+
+                    let result = load_op.deref(ctx).get_result(0);
+                    Ok((result, Some(load_op)))
+                }
+                _ => input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "Projection element {:?} not yet implemented",
+                        place.projection[0]
+                    ))
+                ),
+            }
+        } else {
+            // Multi-level projections (2+): use iterative processing.
+            // The iterative path handles Deref on slices (extracts data pointer),
+            // Index/ConstantIndex on both arrays and pointers, Field, Downcast, etc.
+            translate_place_iterative(ctx, body, place, value_map, block_ptr, prev_op, loc)
+        }
+    }
+}
+
+// ============================================================================
+// Iterative Projection Helpers
+// ============================================================================
+// These functions support the iterative processing of MIR projections.
+// Each projection element is handled independently, allowing arbitrary depth.
+
+/// Apply a Deref projection: load from pointer.
+pub(super) fn apply_deref_projection(
+    ctx: &mut Context,
+    ptr_value: Value,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let ptr_ty = ptr_value.get_type(ctx);
+
+    enum DerefKind {
+        Ptr {
+            pointee: pliron::r#type::TypeHandle,
+            is_zst: bool,
+        },
+        Slice {
+            element_ty: pliron::r#type::TypeHandle,
+        },
+    }
+
+    let deref_kind = {
+        let ptr_ty_ref = ptr_ty.deref(ctx);
+        if let Some(mir_ptr_ty) = ptr_ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>() {
+            let pointee = mir_ptr_ty.pointee;
+            let is_zst = pointee
+                .deref(ctx)
+                .downcast_ref::<dialect_mir::types::MirTupleType>()
+                .is_some_and(|tt| tt.get_types().is_empty());
+            Some(DerefKind::Ptr { pointee, is_zst })
+        } else {
+            ptr_ty_ref
+                .downcast_ref::<dialect_mir::types::MirSliceType>()
+                .map(|slice_ty| DerefKind::Slice {
+                    element_ty: slice_ty.element_type(),
+                })
+        }
+    };
+
+    let deref_kind = deref_kind.ok_or_else(|| {
+        let ty_dbg = format!("{:?}", ptr_ty.deref(ctx));
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "Deref projection on unsupported type in apply_deref_projection.\n\
+             \n  pliron type: {}\n\
+             \n  display    : {}\n\
+             \n\
+             \nDeref currently handles MirPtrType (thin pointer load) and MirSliceType\n\
+             (fat pointer → extract data pointer). The type above matched neither.\n\
+             A new handler may need to be added.",
+            ty_dbg,
+            ptr_ty.disp(ctx)
+        )))
+    })?;
+
+    match deref_kind {
+        DerefKind::Ptr { pointee, is_zst } => {
+            if is_zst {
+                return Ok((ptr_value, prev_op));
+            }
+
+            let op = Operation::new(
+                ctx,
+                MirLoadOp::get_concrete_op_info(),
+                vec![pointee],
+                vec![ptr_value],
+                vec![],
+                0,
+            );
+            op.deref_mut(ctx).set_loc(loc);
+            let load_op = MirLoadOp::new(op);
+
+            if let Some(prev) = prev_op {
+                load_op.get_operation().insert_after(ctx, prev);
+            } else {
+                load_op.get_operation().insert_at_front(block_ptr, ctx);
+            }
+
+            Ok((
+                load_op.get_operation().deref(ctx).get_result(0),
+                Some(load_op.get_operation()),
+            ))
+        }
+
+        DerefKind::Slice { element_ty } => {
+            // Slices are unsized — we can't load `[T]` into an SSA value.
+            // Extract the data pointer (field 0 of the fat pointer {ptr, len}).
+            // Subsequent Index/ConstantIndex projections will do ptr arithmetic + load.
+            let origin = ptr_value
+                .get_type(ctx)
+                .deref(ctx)
+                .downcast_ref::<dialect_mir::types::MirSliceType>()
+                .map(facts::pointer_origin_of_slice_carrier);
+            let ptr_ty: TypeHandle = match origin {
+                Some(origin) => facts::mint_generic_ptr_type(ctx, element_ty, origin).into(),
+                None => dialect_mir::types::MirPtrType::get_generic(ctx, element_ty, false).into(),
+            };
+
+            let extract_op = Operation::new(
+                ctx,
+                MirExtractFieldOp::get_concrete_op_info(),
+                vec![ptr_ty],
+                vec![ptr_value],
+                vec![],
+                0,
+            );
+            extract_op.deref_mut(ctx).set_loc(loc);
+
+            let extract = MirExtractFieldOp::new(extract_op);
+            extract.set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
+
+            if let Some(prev) = prev_op {
+                extract.get_operation().insert_after(ctx, prev);
+            } else {
+                extract.get_operation().insert_at_front(block_ptr, ctx);
+            }
+
+            Ok((
+                extract.get_operation().deref(ctx).get_result(0),
+                Some(extract.get_operation()),
+            ))
+        }
+    }
+}
+
+/// Apply a Field projection against a POINTER to the aggregate: compute the
+/// field's address with `mir.field_addr` and load the field value.
+///
+/// Used when the projection walk holds an address rather than an aggregate
+/// value, which happens after dereferencing a fat pointer (the unsized
+/// pointee cannot be loaded whole, so the deref hands back the data
+/// pointer; see `apply_deref_projection`).
+pub(super) fn apply_field_addr_and_load(
+    ctx: &mut Context,
+    aggregate_ptr: Value,
+    field_idx: mir::FieldIdx,
+    field_ty: &rustc_public::ty::Ty,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let field_type = types::translate_type(ctx, field_ty)?;
+    let field_ptr_ty = projected_pointer_type(
+        ctx,
+        aggregate_ptr.get_type(ctx),
+        field_type,
+        /* legacy requested mutability, ignored */ false,
+    )
+    .ok_or_else(|| {
+        input_error!(
+            loc.clone(),
+            TranslationErr::unsupported("field-address base is not a MIR pointer".to_string())
+        )
+    })?;
+
+    let addr_op = dialect_mir::ops::MirFieldAddrOp::build(
+        ctx,
+        aggregate_ptr,
+        field_ptr_ty,
+        field_idx as u32,
+    )?;
+    addr_op.deref_mut(ctx).set_loc(loc.clone());
+    match prev_op {
+        Some(p) => addr_op.insert_after(ctx, p),
+        None => addr_op.insert_at_front(block_ptr, ctx),
+    }
+    let field_ptr = addr_op.deref(ctx).get_result(0);
+
+    let load_op = Operation::new(
+        ctx,
+        MirLoadOp::get_concrete_op_info(),
+        vec![field_type],
+        vec![field_ptr],
+        vec![],
+        0,
+    );
+    load_op.deref_mut(ctx).set_loc(loc);
+    load_op.insert_after(ctx, addr_op);
+
+    Ok((load_op.deref(ctx).get_result(0), Some(load_op)))
+}
+
+/// Apply a Field projection: extract field from struct/tuple.
+pub(super) fn apply_field_projection(
+    ctx: &mut Context,
+    aggregate_value: Value,
+    field_idx: mir::FieldIdx,
+    field_ty: &rustc_public::ty::Ty,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let field_type = types::translate_type(ctx, field_ty)?;
+
+    let op = Operation::new(
+        ctx,
+        MirExtractFieldOp::get_concrete_op_info(),
+        vec![field_type],
+        vec![aggregate_value],
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc.clone());
+
+    let extract_op = MirExtractFieldOp::new(op);
+    extract_op.set_attr_index(
+        ctx,
+        dialect_mir::attributes::FieldIndexAttr(field_idx as u32),
+    );
+
+    if let Some(prev) = prev_op {
+        extract_op.get_operation().insert_after(ctx, prev);
+    } else {
+        extract_op.get_operation().insert_at_front(block_ptr, ctx);
+    }
+
+    let field_value = extract_op.get_operation().deref(ctx).get_result(0);
+
+    Ok((field_value, Some(extract_op.get_operation())))
+}
+
+/// Apply a Field projection on an enum variant (after Downcast).
+#[allow(clippy::too_many_arguments)]
+pub(crate) fn apply_enum_field_projection_pub(
+    ctx: &mut Context,
+    enum_value: Value,
+    enum_rust_ty: &rustc_public::ty::Ty,
+    variant_idx: rustc_public::ty::VariantIdx,
+    field_idx: mir::FieldIdx,
+    field_ty: &rustc_public::ty::Ty,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    apply_enum_field_projection(
+        ctx,
+        enum_value,
+        enum_rust_ty,
+        variant_idx,
+        field_idx,
+        field_ty,
+        block_ptr,
+        prev_op,
+        loc,
+    )
+}
+
+pub(super) fn apply_enum_field_projection(
+    ctx: &mut Context,
+    enum_value: Value,
+    enum_rust_ty: &rustc_public::ty::Ty,
+    variant_idx: rustc_public::ty::VariantIdx,
+    field_idx: mir::FieldIdx,
+    field_ty: &rustc_public::ty::Ty,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    use dialect_mir::ops::MirEnumPayloadOp;
+
+    let field_type = types::translate_type(ctx, field_ty)?;
+
+    // Get the variant index
+    // NOTE: variant_idx IS the index (0, 1, 2, ...), NOT the discriminant!
+    // We just need to validate it's an ADT type, then use the index directly.
+    let variant_idx_val: usize = match enum_rust_ty.kind() {
+        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Adt(_adt_def, _)) => {
+            variant_idx.to_index()
+        }
+        _ => {
+            return input_err!(
+                loc.clone(),
+                TranslationErr::unsupported(format!(
+                    "Downcast on non-ADT type: {:?}",
+                    enum_rust_ty
+                ))
+            );
+        }
+    };
+
+    // A value inhabiting this variant cannot exist, so the read sits on a
+    // dynamically dead path that rustc nevertheless keeps in MIR (e.g. the
+    // `ControlFlow::Break(NeverShortCircuitResidual)` arm inside
+    // `array::try_from_fn`). `mir.enum_payload` refuses uninhabited
+    // variants by verification, so keep the dead path representable with a
+    // typed undef instead — the same treatment `[T; 0]` extraction gets.
+    let variant_is_uninhabited = {
+        let enum_ty = enum_value.get_type(ctx);
+        enum_ty
+            .deref(ctx)
+            .downcast_ref::<dialect_mir::types::MirEnumType>()
+            .and_then(|enum_ty| enum_ty.variant_is_inhabited(variant_idx_val))
+            .is_some_and(|inhabited| !inhabited)
+    };
+    if variant_is_uninhabited {
+        let undef = MirUndefOp::new(ctx, field_type).get_operation();
+        undef.deref_mut(ctx).set_loc(loc);
+        match prev_op {
+            Some(prev) => undef.insert_after(ctx, prev),
+            None => undef.insert_at_front(block_ptr, ctx),
+        }
+        return Ok((undef.deref(ctx).get_result(0), Some(undef)));
+    }
+
+    let op = Operation::new(
+        ctx,
+        MirEnumPayloadOp::get_concrete_op_info(),
+        vec![field_type],
+        vec![enum_value],
+        vec![],
+        0,
+    );
+    op.deref_mut(ctx).set_loc(loc.clone());
+
+    let payload_op = MirEnumPayloadOp::new(op);
+
+    payload_op.set_attr_payload_variant_index(
+        ctx,
+        dialect_mir::attributes::VariantIndexAttr(variant_idx_val as u32),
+    );
+    payload_op.set_attr_payload_field_index(
+        ctx,
+        dialect_mir::attributes::FieldIndexAttr(field_idx as u32),
+    );
+
+    if let Some(prev) = prev_op {
+        payload_op.get_operation().insert_after(ctx, prev);
+    } else {
+        payload_op.get_operation().insert_at_front(block_ptr, ctx);
+    }
+
+    let payload_value = payload_op.get_operation().deref(ctx).get_result(0);
+
+    Ok((payload_value, Some(payload_op.get_operation())))
+}
diff --git a/crates/mir-importer/src/translator/rvalue/pointee.rs b/crates/mir-importer/src/translator/rvalue/pointee.rs
new file mode 100644
index 0000000000..f92a13e1c5
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/pointee.rs
@@ -0,0 +1,478 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! `PointeeKind` and pointee/type utilities.
+
+use crate::translator::facts;
+use dialect_mir::ops::{MirExtractFieldOp, MirPtrOffsetOp};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+
+/// Describes what a pointer points to (array vs. anything else) for
+/// address-computation dispatch.
+pub(super) enum PointeeKind {
+    /// Pointee is `[T; N]` (carries `T`). Element addressing GEPs through
+    /// the array type via `mir.array_element_addr`.
+    Array(TypeHandle),
+    /// Pointee is any other type. When an `Index` / `ConstantIndex`
+    /// projection meets such a pointer, MIR typing guarantees the indexed
+    /// place is a slice whose data pointer (produced by the fat-pointer
+    /// `Deref` arm) points directly at the elements, so element addressing
+    /// is a plain `mir.ptr_offset` keeping the pointer's own type.
+    Direct,
+}
+
+pub(super) fn indexed_element_ptr_type(
+    ctx: &mut Context,
+    current_ptr_ty: TypeHandle,
+    pointee_kind: PointeeKind,
+    _addr_space: u32,
+    _is_mutable: bool,
+) -> TypeHandle {
+    match pointee_kind {
+        PointeeKind::Array(element_ty) => projected_pointer_type(
+            ctx,
+            current_ptr_ty,
+            element_ty,
+            /* legacy requested mutability, ignored */ false,
+        )
+        .expect("indexed array base must be a MirPtrType"),
+        PointeeKind::Direct => current_ptr_ty,
+    }
+}
+
+/// Emit the address of element `index_val` behind `current`, which is either
+/// a pointer to a whole array (`&arr[i]`: `mir.array_element_addr`) or a
+/// pointer to a single ELEMENT, i.e. the data pointer of a fat slice value
+/// extracted by the Deref arm above (`(*slice)[i]`: element-size pointer
+/// arithmetic via `mir.ptr_offset`). Returns the emitted op and the element
+/// address it produces.
+#[allow(clippy::too_many_arguments)]
+pub(super) fn emit_indexed_element_addr(
+    ctx: &mut Context,
+    current: Value,
+    index_val: Value,
+    pointee_kind: PointeeKind,
+    _addr_space: u32,
+    is_mutable: bool,
+    block_ptr: Ptr<BasicBlock>,
+    current_prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> (Ptr<Operation>, Value) {
+    use dialect_mir::ops::MirArrayElementAddrOp;
+
+    let addr_op = match pointee_kind {
+        PointeeKind::Array(element_ty) => {
+            let elem_ptr_ty =
+                projected_pointer_type(ctx, current.get_type(ctx), element_ty, is_mutable)
+                    .expect("indexed array base must be a MirPtrType");
+            Operation::new(
+                ctx,
+                MirArrayElementAddrOp::get_concrete_op_info(),
+                vec![elem_ptr_ty],
+                vec![current, index_val],
+                vec![],
+                0,
+            )
+        }
+        PointeeKind::Direct => {
+            // The pointee IS the element type, so indexing is plain
+            // element-size pointer arithmetic and the result keeps the
+            // pointer's own type.
+            let ptr_ty = current.get_type(ctx);
+            Operation::new(
+                ctx,
+                MirPtrOffsetOp::get_concrete_op_info(),
+                vec![ptr_ty],
+                vec![current, index_val],
+                vec![],
+                0,
+            )
+        }
+    };
+    addr_op.deref_mut(ctx).set_loc(loc);
+    match current_prev_op {
+        Some(p) => addr_op.insert_after(ctx, p),
+        None => addr_op.insert_at_front(block_ptr, ctx),
+    }
+    let result = addr_op.deref(ctx).get_result(0);
+    (addr_op, result)
+}
+
+/// Inspect a pointer value and return its pointee kind + address space, or
+/// `None` if the value's type isn't a `MirPtrType`.
+pub(super) fn pointer_pointee_kind(ctx: &Context, ptr_value: Value) -> Option<(PointeeKind, u32)> {
+    pointer_type_pointee_kind(ctx, ptr_value.get_type(ctx))
+}
+
+/// Inspect a pointer type and return its pointee kind + address space, or
+/// `None` if the type isn't a `MirPtrType`.
+pub(super) fn pointer_type_pointee_kind(
+    ctx: &Context,
+    ptr_ty: TypeHandle,
+) -> Option<(PointeeKind, u32)> {
+    let ty_ref = ptr_ty.deref(ctx);
+    let mir_ptr_ty = ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>()?;
+    let pointee = mir_ptr_ty.pointee;
+    let addr_space = mir_ptr_ty.address_space;
+    let pointee_ref = pointee.deref(ctx);
+    let kind = if let Some(arr_ty) = pointee_ref.downcast_ref::<dialect_mir::types::MirArrayType>()
+    {
+        PointeeKind::Array(arr_ty.element_type())
+    } else {
+        PointeeKind::Direct
+    };
+    Some((kind, addr_space))
+}
+
+pub(super) fn mir_ptr_pointee(ctx: &Context, ptr_ty: TypeHandle) -> Option<TypeHandle> {
+    ptr_ty
+        .deref(ctx)
+        .downcast_ref::<dialect_mir::types::MirPtrType>()
+        .map(|ptr_ty| ptr_ty.pointee)
+}
+
+/// Build a pointer to `pointee` while preserving the address space of
+/// `base_ptr_ty`.
+///
+/// Address-producing projections such as field access are LLVM GEPs, and a
+/// GEP cannot change the address space of its base pointer.
+pub(super) fn projected_pointer_type(
+    ctx: &mut Context,
+    base_ptr_ty: TypeHandle,
+    pointee: TypeHandle,
+    _is_mutable: bool,
+) -> Option<TypeHandle> {
+    let (origin, address_space) = {
+        let base_ptr_ty = base_ptr_ty.deref(ctx);
+        let base_ptr_ty = base_ptr_ty.downcast_ref::<dialect_mir::types::MirPtrType>()?;
+        (
+            facts::pointer_origin_of_ptr_carrier(base_ptr_ty),
+            base_ptr_ty.address_space,
+        )
+    };
+
+    Some(facts::mint_ptr_type(ctx, pointee, address_space, origin).into())
+}
+
+pub(super) fn is_empty_tuple_type(ctx: &Context, ty: TypeHandle) -> bool {
+    ty.deref(ctx)
+        .downcast_ref::<dialect_mir::types::MirTupleType>()
+        .is_some_and(|tt| tt.get_types().is_empty())
+}
+
+/// Whether `ty` is a tuple carrying a field that owns zero bytes while
+/// demanding ABI alignment above 1, at any array nesting depth.
+///
+/// Code-shape guard for the read classifier: the address path's final
+/// `mir.load` states the loaded field's natural alignment only, so a tuple
+/// whose recorded ABI alignment comes from a zero-sized `repr(align(N))`
+/// field must keep the value path, which moves the whole aggregate at its
+/// recorded alignment. Gate shape from PR #715 (vyncint), with the byte-size
+/// gap closed: detection compares byte sizes, not element counts, so
+/// `[Align32; 2]` still reads as zero bytes.
+pub(super) fn tuple_has_over_aligned_zst_field(ctx: &Context, ty: TypeHandle) -> bool {
+    ty.deref(ctx)
+        .downcast_ref::<dialect_mir::types::MirTupleType>()
+        .is_some_and(|tuple_ty| {
+            tuple_ty
+                .get_types()
+                .iter()
+                .any(|field| is_over_aligned_zst_type(ctx, *field))
+        })
+}
+
+/// Whether `ty` occupies zero bytes while its recorded ABI alignment exceeds
+/// 1: a `repr(align(N))` ZST, possibly wrapped in arrays.
+fn is_over_aligned_zst_type(ctx: &Context, ty: TypeHandle) -> bool {
+    recorded_byte_size_and_abi_align(ctx, ty)
+        .is_some_and(|(byte_size, abi_align)| byte_size == 0 && abi_align > 1)
+}
+
+/// Byte size and ABI alignment of `ty`, when the dialect records them.
+///
+/// Aggregates carry rustc's `total_size` and `abi_align` directly. Arrays
+/// multiply the element's byte size by the element count
+/// (`MirArrayType::size()` is a count, not a byte size) and align like their
+/// element. Scalars and pointers return `None`: they always occupy at least
+/// one byte, so they can never be a zero-sized alignment carrier.
+fn recorded_byte_size_and_abi_align(ctx: &Context, ty: TypeHandle) -> Option<(u64, u64)> {
+    use dialect_mir::types::{
+        MirArrayType, MirEnumType, MirStructType, MirTupleType, MirUnionType,
+    };
+
+    let ty_ref = ty.deref(ctx);
+    if let Some(array_ty) = ty_ref.downcast_ref::<MirArrayType>() {
+        let element_ty = array_ty.element_type();
+        let element_count = array_ty.size();
+        return recorded_byte_size_and_abi_align(ctx, element_ty).map(
+            |(element_size, element_align)| {
+                (element_size.saturating_mul(element_count), element_align)
+            },
+        );
+    }
+    if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
+        return Some((tuple_ty.total_size(), tuple_ty.abi_align()));
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
+        return Some((struct_ty.total_size(), struct_ty.abi_align));
+    }
+    if let Some(enum_ty) = ty_ref.downcast_ref::<MirEnumType>() {
+        return Some((enum_ty.total_size(), enum_ty.abi_align()));
+    }
+    if let Some(union_ty) = ty_ref.downcast_ref::<MirUnionType>() {
+        return Some((union_ty.total_size(), union_ty.abi_align()));
+    }
+    None
+}
+
+pub(super) fn slice_like_element_type(ctx: &Context, ty: TypeHandle) -> Option<TypeHandle> {
+    let ty_ref = ty.deref(ctx);
+    ty_ref
+        .downcast_ref::<dialect_mir::types::MirSliceType>()
+        .map(|slice_ty| slice_ty.element_type())
+        .or_else(|| {
+            ty_ref
+                .downcast_ref::<dialect_mir::types::MirDisjointSliceType>()
+                .map(|slice_ty| slice_ty.element_type())
+        })
+}
+
+/// Return the projection-internal data-pointer type for a fat slice value.
+///
+/// Ordinary slices deliberately erase their Rust pointer kind while retaining
+/// the carrier's exact machine mutability. `DisjointSlice` instead has a fixed
+/// `RawMut` field contract. In both cases extraction is representation-only:
+/// it cannot invent writable evidence or a stronger Rust category.
+pub(super) fn erased_slice_data_pointer_type(
+    ctx: &mut Context,
+    slice_value: Value,
+    element_ty: TypeHandle,
+) -> Option<TypeHandle> {
+    let slice_ty = slice_value.get_type(ctx);
+    let ordinary_mutability = slice_ty
+        .deref(ctx)
+        .downcast_ref::<dialect_mir::types::MirSliceType>()
+        .map(|slice| slice.is_mutable);
+    if let Some(is_mutable) = ordinary_mutability {
+        return Some(
+            dialect_mir::types::MirPtrType::get_generic(ctx, element_ty, is_mutable).into(),
+        );
+    }
+    if slice_ty
+        .deref(ctx)
+        .downcast_ref::<dialect_mir::types::MirDisjointSliceType>()
+        .is_some()
+    {
+        return Some(
+            facts::mint_generic_ptr_type(ctx, element_ty, facts::abi_disjoint_slice_data_ptr())
+                .into(),
+        );
+    }
+    None
+}
+
+pub(super) fn rust_ty_is_slice(ty: &rustc_public::ty::Ty) -> bool {
+    matches!(
+        ty.kind(),
+        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Slice(_))
+    )
+}
+
+pub(super) fn normalize_slice_value_to_data_ptr(
+    ctx: &mut Context,
+    value: Value,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> (Value, Option<Ptr<Operation>>) {
+    let slice_element_ty = {
+        let value_ty = value.get_type(ctx);
+        let value_ty_ref = value_ty.deref(ctx);
+        value_ty_ref
+            .downcast_ref::<dialect_mir::types::MirSliceType>()
+            .map(|slice_ty| slice_ty.element_type())
+    };
+    let Some(element_ty) = slice_element_ty else {
+        return (value, prev_op);
+    };
+
+    let Some(data_ptr_ty) = erased_slice_data_pointer_type(ctx, value, element_ty) else {
+        return (value, prev_op);
+    };
+    let extract_ptr = Operation::new(
+        ctx,
+        MirExtractFieldOp::get_concrete_op_info(),
+        vec![data_ptr_ty],
+        vec![value],
+        vec![],
+        0,
+    );
+    extract_ptr.deref_mut(ctx).set_loc(loc);
+    MirExtractFieldOp::new(extract_ptr)
+        .set_attr_index(ctx, dialect_mir::attributes::FieldIndexAttr(0));
+    match prev_op {
+        Some(prev) => extract_ptr.insert_after(ctx, prev),
+        None => extract_ptr.insert_at_front(block_ptr, ctx),
+    }
+
+    (extract_ptr.deref(ctx).get_result(0), Some(extract_ptr))
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production code mints via facts::PointerOrigin.
+#[allow(clippy::disallowed_methods)]
+mod tests {
+    use super::*;
+    use dialect_mir::types::{MirArrayType, MirPtrType, MirStructType, MirTupleType};
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    #[test]
+    fn over_aligned_zst_tuple_fields_force_the_value_fallback_gate() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+
+        // `#[repr(align(32))] struct Align32;`: zero bytes, ABI alignment 32.
+        let align32_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Align32".into(),
+            vec![],
+            vec![],
+            vec![],
+            vec![],
+            0,
+            32,
+        )
+        .into();
+
+        // `(Align32, u8)` as rustc lays it out: one payload byte padded out
+        // to a 32-byte, align-32 allocation.
+        let pair_ty: TypeHandle = MirTupleType::get_with_layout(
+            &mut ctx,
+            vec![align32_ty, u8_ty],
+            vec![],
+            vec![0, 0],
+            32,
+            32,
+        )
+        .into();
+        assert!(
+            tuple_has_over_aligned_zst_field(&ctx, pair_ty),
+            "a zero-byte repr(align(32)) field must force the value path"
+        );
+
+        // The byte-size gap in PR #715's gate: `[Align32; 2]` has element
+        // count 2 but still owns zero bytes and still demands align 32, at
+        // any array nesting depth.
+        let align32_x2_ty: TypeHandle = MirArrayType::get(&mut ctx, align32_ty, 2).into();
+        let align32_x2x3_ty: TypeHandle = MirArrayType::get(&mut ctx, align32_x2_ty, 3).into();
+        for wrapped_ty in [align32_x2_ty, align32_x2x3_ty] {
+            let tuple_ty: TypeHandle = MirTupleType::get_with_layout(
+                &mut ctx,
+                vec![wrapped_ty, u8_ty],
+                vec![],
+                vec![0, 0],
+                32,
+                32,
+            )
+            .into();
+            assert!(
+                tuple_has_over_aligned_zst_field(&ctx, tuple_ty),
+                "a zero-byte array of over-aligned ZSTs must not slip through on element count"
+            );
+        }
+
+        // Ordinary tuples keep the address path: rustc's reordered
+        // `(u8, u32)` layout (u8 at offset 4, u32 at offset 0).
+        let plain_ty: TypeHandle = MirTupleType::get_with_layout(
+            &mut ctx,
+            vec![u8_ty, u32_ty],
+            vec![1, 0],
+            vec![4, 0],
+            8,
+            4,
+        )
+        .into();
+        assert!(
+            !tuple_has_over_aligned_zst_field(&ctx, plain_ty),
+            "tuples without over-aligned ZST fields must stay on the address path"
+        );
+
+        // An align-1 ZST field, the unit tuple, does not trip the gate:
+        // zero bytes alone raise nothing.
+        let unit_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![]).into();
+        let with_unit_ty: TypeHandle = MirTupleType::get_with_layout(
+            &mut ctx,
+            vec![unit_ty, u32_ty],
+            vec![],
+            vec![0, 0],
+            4,
+            4,
+        )
+        .into();
+        assert!(
+            !tuple_has_over_aligned_zst_field(&ctx, with_unit_ty),
+            "plain ZST fields raise no alignment and must not force the fallback"
+        );
+    }
+
+    #[test]
+    fn projected_pointer_type_preserves_base_address_space() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let field_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+
+        let aggregate_ty: TypeHandle = MirStructType::get(
+            &mut ctx,
+            "ProjectedAddressSpaceTest".into(),
+            vec!["field".into()],
+            vec![field_ty],
+        )
+        .into();
+
+        for address_space in [1, 4] {
+            let base_ptr_ty: TypeHandle =
+                MirPtrType::get(&mut ctx, aggregate_ty, false, address_space).into();
+
+            let projected_ty = projected_pointer_type(&mut ctx, base_ptr_ty, field_ty, false)
+                .expect("base type must be a MIR pointer");
+
+            let (projected_pointee, projected_mutability, projected_address_space) = {
+                let projected_ty = projected_ty.deref(&ctx);
+                let projected_ptr = projected_ty
+                    .downcast_ref::<MirPtrType>()
+                    .expect("projected type must remain a MIR pointer");
+
+                (
+                    projected_ptr.pointee,
+                    projected_ptr.is_mutable,
+                    projected_ptr.address_space,
+                )
+            };
+
+            assert_eq!(
+                projected_pointee, field_ty,
+                "field projection must change the pointee type"
+            );
+            assert!(
+                !projected_mutability,
+                "field projection must preserve the requested mutability"
+            );
+            assert_eq!(
+                projected_address_space, address_space,
+                "field projection must preserve the base pointer address space"
+            );
+        }
+    }
+}
diff --git a/crates/mir-importer/src/translator/rvalue/promoted.rs b/crates/mir-importer/src/translator/rvalue/promoted.rs
new file mode 100644
index 0000000000..2a5a0eeaa6
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/promoted.rs
@@ -0,0 +1,1713 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Promoted immutable device globals and their layout gates.
+
+use super::coerce::cast_to_declared_rust_pointer_type_if_needed;
+use super::const_bytes::rust_type_layout_size;
+use super::static_global::{
+    StaticGlobalMaterializationState, ensure_initializer_relocation_targets,
+    set_global_initializer_hex_attr, set_global_initializer_relocations_attr,
+    stored_type_union_name,
+};
+use super::statics::{
+    GlobalInitializerData, GlobalInitializerRelocation, bytes_to_hex,
+    encode_global_initializer_relocations, promoted_array_initializer,
+};
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::types;
+use crate::translator::values::ValueMap;
+use dialect_mir::attributes::MirPointerKindAuthorityAttr;
+use dialect_mir::ops::{MirConstantOp, MirGlobalAllocOp};
+use dialect_mir::types::MirFP16Type;
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{FP32Type, FP64Type, IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::TypeHandle;
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use pliron::{input_err, input_error_noloc};
+use rustc_public::mir;
+use rustc_public::ty::ConstantKind;
+use std::num::NonZeroUsize;
+
+/// Translate a pointer-to-array constant to MIR operations.
+///
+/// Handles both byte string literals (`&[u8; N]`, e.g. `b"hello\0"`) and typed
+/// array constants (`&[f64; 3]`, `&[u32; 4]`, etc.). The function:
+/// 1. Extracts raw bytes from the constant's allocation
+/// 2. Groups bytes into element-sized chunks based on the array element type
+/// 3. Creates typed constants for each element (u8, u32, f32, f64, etc.)
+/// 4. Returns a pointer to the constructed array
+pub(super) fn translate_ptr_to_array_constant(
+    ctx: &mut Context,
+    constant: &mir::ConstOperand,
+    const_ty_ptr: TypeHandle,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    // Extract array type from the pointer type. A pointer-to-array constant can
+    // outlive this function, so lowering it as `array value + mir.ref` would
+    // return a pointer to function-local stack storage. Materialize it as an
+    // immutable device global instead.
+    let array_ty = {
+        let ty_obj = const_ty_ptr.deref(ctx);
+        let ptr_ty = ty_obj
+            .downcast_ref::<dialect_mir::types::MirPtrType>()
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(
+                    "translate_ptr_to_array_constant: expected pointer type"
+                ))
+            })?;
+
+        let arr_ty_obj = ptr_ty.pointee.deref(ctx);
+        if arr_ty_obj
+            .downcast_ref::<dialect_mir::types::MirArrayType>()
+            .is_none()
+        {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(
+                    "translate_ptr_to_array_constant: expected array pointee"
+                )
+            );
+        }
+        ptr_ty.pointee
+    };
+
+    let rust_array_ty = match constant.const_.ty().kind() {
+        rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::RawPtr(pointee, _))
+        | rustc_public::ty::TyKind::RigidTy(rustc_public::ty::RigidTy::Ref(_, pointee, _)) => {
+            pointee
+        }
+        _ => constant.const_.ty(),
+    };
+    let expected_size = rust_type_layout_size(rust_array_ty, loc.clone())?;
+    if expected_size != 0
+        && let Some(union_name) = stored_type_union_name(rust_array_ty, &mut Vec::new())
+    {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "promoted array initializer contains union `{union_name}`; initialized union storage is not yet supported"
+            ))
+        );
+    }
+
+    validate_ptr_to_array_constant_type(ctx, array_ty, loc.clone())?;
+    // The same byte-size agreement the bare-array promotion demands: the
+    // global's declared type is the converted dialect type while its
+    // initializer bytes come from rustc's evaluated allocation, so the two
+    // layouts must agree before the byte image is trusted. Unlike that path
+    // there is no element-wise lowering to fall back to here, so disagreement
+    // is an error rather than a bail-out. Zero size stays exempt because
+    // `dialect_stored_size` cannot tell a genuine zero from an unrecorded
+    // layout, and an empty initializer has no bytes to misplace.
+    let stored_size = dialect_stored_size(ctx, array_ty);
+    if expected_size > 0 && stored_size != Some(expected_size as u64) {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "translate_ptr_to_array_constant: converted array storage size {stored_size:?} disagrees with rustc layout size {expected_size}"
+            ))
+        );
+    }
+    let initializer = promoted_array_initializer(constant, expected_size, "array", loc.clone())?;
+    let promoted_anchor = materialize_promoted_initializer_targets(
+        ctx,
+        &initializer.relocations,
+        block_ptr,
+        prev_op,
+        loc.clone(),
+    )?;
+
+    let global_alloc = emit_promoted_immutable_global(
+        ctx,
+        array_ty,
+        &initializer,
+        block_ptr,
+        promoted_anchor,
+        loc.clone(),
+    );
+
+    let global_ptr = global_alloc.get_operation().deref(ctx).get_result(0);
+    let (ptr_val, last_op) = cast_to_declared_rust_pointer_type_if_needed(
+        ctx,
+        global_ptr,
+        const_ty_ptr,
+        block_ptr,
+        Some(global_alloc.get_operation()),
+        loc,
+        MirPointerKindAuthorityAttr::StaticAddress,
+    );
+    Ok((ptr_val, last_op))
+}
+
+/// Materialize an evaluated constant allocation as an immutable device global.
+///
+/// Deduplicated by type, bytes, allocation alignment, and relocation identity.
+/// Pointer placeholder bytes alone are not enough: two constants can have
+/// identical byte images and addends while their rustc provenance targets
+/// different statics or their backing allocations require different alignment.
+///
+/// The global is marked immutable, which is what makes it useful beyond simply
+/// having an address: the exporter writes LLVM `constant`, so `opt` may treat
+/// reads of it as invariant. Pointer slots remain symbolic relocation metadata
+/// all the way to the exporter instead of being reconstructed from placeholder
+/// integer bytes.
+pub(crate) fn emit_promoted_immutable_global(
+    ctx: &mut Context,
+    value_ty: TypeHandle,
+    initializer: &GlobalInitializerData,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> MirGlobalAllocOp {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::attributes::{StringAttr, TypeAttr};
+
+    let initializer_hex = bytes_to_hex(&initializer.bytes);
+    let global_key = promoted_constant_dedup_key(ctx, value_ty, initializer);
+    let global_ptr_ty = MirPtrType::get_global(ctx, value_ty, false);
+    let validation_ty = promoted_global_validation_type(ctx, value_ty, initializer.bytes.len());
+    let global_op = Operation::new(
+        ctx,
+        MirGlobalAllocOp::get_concrete_op_info(),
+        vec![global_ptr_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    global_op.deref_mut(ctx).set_loc(loc);
+
+    let global_alloc = MirGlobalAllocOp::new(global_op);
+    global_alloc.set_attr_global_type(ctx, TypeAttr::new(validation_ty));
+    global_alloc.set_attr_global_key(ctx, StringAttr::new(global_key));
+    set_global_initializer_hex_attr(ctx, global_alloc.get_operation(), &initializer_hex);
+    if !initializer.relocations.is_empty() {
+        let encoded = encode_global_initializer_relocations(&initializer.relocations);
+        set_global_initializer_relocations_attr(ctx, global_alloc.get_operation(), &encoded);
+    }
+    if initializer.alignment > 0 {
+        global_alloc.set_alignment_value(ctx, initializer.alignment);
+    }
+    global_alloc.mark_immutable(ctx);
+
+    if let Some(prev) = prev_op {
+        global_alloc.get_operation().insert_after(ctx, prev);
+    } else {
+        global_alloc.get_operation().insert_at_front(block_ptr, ctx);
+    }
+
+    global_alloc
+}
+
+/// Ensure every Rust static referenced by a promoted initializer exists as a
+/// MIR global before the promoted table is emitted.
+///
+/// Without this step the old element-wise pointer decoder used to materialize
+/// the targets as a side effect. Once the entire table stays in one global, the
+/// relocation metadata is the only reference and the targets must be made
+/// explicit here.
+fn materialize_promoted_initializer_targets(
+    ctx: &mut Context,
+    relocations: &[GlobalInitializerRelocation],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    let mut state = StaticGlobalMaterializationState {
+        globals: std::collections::HashMap::new(),
+        last_op: prev_op,
+    };
+    ensure_initializer_relocation_targets(
+        ctx,
+        relocations,
+        "promoted constant table",
+        block_ptr,
+        loc,
+        &mut state,
+    )?;
+    Ok(state.last_op)
+}
+
+/// Whether an array's elements are cheap enough to be worth promoting the whole
+/// array to an immutable global and copying it in.
+///
+/// This is the element gate for the immutable-global promotion optimization
+/// used by bare array values ([`translate_array_constant_into_alloca`]) and for
+/// the pointer-to-array form ([`translate_ptr_to_array_constant`], via
+/// [`validate_ptr_to_array_constant_type`]). It is deliberately narrower than
+/// bare-array value admission: an unpromotable bare value can fall back to
+/// element-wise materialization, while a pointer-to-array constant cannot.
+///
+/// Admits primitive scalars, thin pointers, enums carrying no payload, tuples
+/// and structs whose every field is itself admissible, and nested arrays of any
+/// of those. Pointer admission is still relocation-gated later: only provenance
+/// that can be represented by [`GlobalInitializerRelocation`] reaches promotion.
+/// `ty` is
+/// the array type, and nesting is walked so an unsupported leaf cannot hide
+/// inside it. A zero-length array passes for any element type: its initializer
+/// is empty and nothing can ever be read through it, which is what admits a
+/// promoted empty-slice constant such as `&[]` (rustc promotes it to `&[T; 0]`)
+/// regardless of `T`.
+///
+/// Tuples are admitted when every field is itself promotable. That only became
+/// worth doing once a tuple field read stopped going through a copy of the whole
+/// array: while that copy stood it dominated, so promoting such a table changed
+/// nothing measurable and merely added a global to the module image. With the
+/// read addressed in place, the promotion is what removes the depot — the two
+/// only pay off together.
+///
+/// Structs are admitted recursively, including thin pointer fields. Unions,
+/// fat-pointer storage, payload-carrying enums, and any other unsupported leaf
+/// remain outside this path. A payload-carrying enum stays out because reading
+/// one back still
+/// round-trips the payload through memory: the address walker resolves enum
+/// payload fields for writes, not for reads.
+///
+/// A struct's recorded rustc layout must be byte-faithful in the LLVM storage
+/// selected by lowering. Ordinary layouts use the natural struct path; layouts
+/// such as `repr(C, packed)` may use the packed struct path when the recorded
+/// field ranges are non-overlapping and the packed representation can reproduce
+/// every offset and the final size exactly. Layouts that neither representation
+/// can express remain on the fallback path. See
+/// [`struct_layout_matches_llvm_storage`].
+fn promotable_array_element(ctx: &Context, ty: TypeHandle) -> bool {
+    use dialect_mir::types::{MirArrayType, MirEnumType, MirStructType, MirTupleType};
+
+    let obj = ty.deref(ctx);
+    if let Some(array) = obj.downcast_ref::<MirArrayType>() {
+        // No element values exist, so the element restriction is vacuous.
+        if array.size() == 0 {
+            return true;
+        }
+        return promotable_array_element(ctx, array.element_type());
+    }
+    if let Some(tuple) = obj.downcast_ref::<MirTupleType>() {
+        let fields = tuple.get_types().to_vec();
+        drop(obj);
+        return fields
+            .into_iter()
+            .all(|field| promotable_array_element(ctx, field));
+    }
+    if let Some(structure) = obj.downcast_ref::<MirStructType>() {
+        let fields = structure.field_types().to_vec();
+        let field_offsets = structure.field_offsets().to_vec();
+        let mem_to_decl = structure.mem_to_decl.clone();
+        let total_size = structure.total_size;
+        let has_zero_byte_over_alignment = total_size == 0 && structure.abi_align > 1;
+        drop(obj);
+
+        // A zero-byte `repr(align(N))` struct can raise the alignment of an
+        // enclosing tuple without contributing storage to its LLVM shape. Keep
+        // that established alignment-sensitive path out of immutable-global
+        // promotion; ordinary stored structs still recurse through their fields.
+        if has_zero_byte_over_alignment {
+            return false;
+        }
+
+        // Immutable promotion copies rustc's evaluated byte image into the
+        // exact storage type selected by lowering. Accept either the ordinary
+        // natural representation or the exact packed representation introduced
+        // for layout-divergent structs. Overlapping or otherwise unrepresentable
+        // field maps still fail closed.
+        if !struct_layout_matches_llvm_storage(
+            ctx,
+            &fields,
+            &field_offsets,
+            &mem_to_decl,
+            total_size,
+        ) {
+            return false;
+        }
+
+        return fields
+            .into_iter()
+            .all(|field| promotable_array_element(ctx, field));
+    }
+    if let Some(enumeration) = obj.downcast_ref::<MirEnumType>() {
+        // No variant carries a field, so the whole element *is* its discriminant
+        // and reading one is a single load.
+        return enumeration.total_size() > 0
+            && enumeration
+                .variant_field_counts
+                .iter()
+                .all(|&count| count == 0);
+    }
+    obj.is::<dialect_mir::types::MirPtrType>()
+        || obj.is::<IntegerType>()
+        || obj.is::<MirFP16Type>()
+        || obj.is::<FP32Type>()
+        || obj.is::<FP64Type>()
+}
+
+/// Whether rustc's recorded struct layout is byte-faithful in one of the LLVM
+/// struct representations available to lowering.
+///
+/// The natural representation remains preferred. When it cannot reproduce the
+/// recorded offsets, lowering can use a packed LLVM struct with explicit byte
+/// padding between stored fields. Such a representation is exact iff the stored
+/// fields are non-overlapping in rustc memory order and every field range plus
+/// the tail fits inside `total_size`. Alignment is intentionally not part of the
+/// packed check: LLVM packed structs permit an otherwise naturally aligned field
+/// at an unaligned byte offset, while the enclosing allocation keeps rustc's ABI
+/// alignment separately.
+///
+/// Unknown layouts retain the previous optimistic answer here; the promotion
+/// path's stored-size agreement check rejects a non-empty initializer whose
+/// concrete size cannot be established.
+fn struct_layout_matches_llvm_storage(
+    ctx: &Context,
+    field_types: &[TypeHandle],
+    field_offsets: &[u64],
+    mem_to_decl: &[usize],
+    total_size: u64,
+) -> bool {
+    if field_offsets.is_empty() || total_size == 0 {
+        return true;
+    }
+    if field_offsets.len() != field_types.len() {
+        return false;
+    }
+
+    if struct_layout_matches_llvm_natural(ctx, field_types, field_offsets, mem_to_decl, total_size)
+    {
+        return true;
+    }
+
+    // Empty `mem_to_decl` means identity (declaration order = memory order).
+    let identity: Vec<usize>;
+    let memory_order: &[usize] = if mem_to_decl.is_empty() {
+        identity = (0..field_types.len()).collect();
+        &identity
+    } else {
+        mem_to_decl
+    };
+
+    let mut end = 0u64;
+    for &decl_idx in memory_order {
+        if decl_idx >= field_types.len() {
+            return false;
+        }
+
+        let Some((size, _)) = llvm_natural_size_align(ctx, field_types[decl_idx]) else {
+            return false;
+        };
+        if size == 0 {
+            continue;
+        }
+
+        let offset = field_offsets[decl_idx];
+        if offset < end {
+            return false;
+        }
+        let Some(field_end) = offset.checked_add(size) else {
+            return false;
+        };
+        if field_end > total_size {
+            return false;
+        }
+        end = field_end;
+    }
+
+    end <= total_size
+}
+
+/// Type used by initialized-global validation for a promoted constant.
+///
+/// `mir.global_alloc` keeps the semantic result pointer separately from its
+/// `global_type` storage metadata. Pointer-free initializers are emitted as an
+/// exact `[N x i8]` allocation by lowering. For a semantic type that contains a
+/// byte-faithful packed struct, use that physical byte view for global-layout
+/// validation while retaining the semantic result pointer. Later typed GEPs and
+/// loads still use `value_ty`, whose packed representation is selected by #941.
+/// Ordinary layouts keep their semantic validation unchanged.
+fn promoted_global_validation_type(
+    ctx: &mut Context,
+    value_ty: TypeHandle,
+    byte_len: usize,
+) -> TypeHandle {
+    use dialect_mir::types::MirArrayType;
+
+    // A zero-byte allocation has no field bytes whose physical placement
+    // needs the packed-storage fallback. Retain the semantic type so the
+    // immutable-global root remains an exact authority for rustc-promoted
+    // `&mut [T; 0]`; lowering still checks its zero size and required
+    // alignment before emitting `[0 x i8]` storage.
+    if byte_len == 0 {
+        return value_ty;
+    }
+
+    if !type_contains_packed_struct_storage(ctx, value_ty) {
+        return value_ty;
+    }
+
+    let byte_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Unsigned).into();
+    MirArrayType::get(ctx, byte_ty, byte_len as u64).into()
+}
+
+/// Whether `ty` contains a struct whose exact LLVM storage must be packed.
+fn type_contains_packed_struct_storage(ctx: &Context, ty: TypeHandle) -> bool {
+    use dialect_mir::types::{MirArrayType, MirStructType, MirTupleType};
+
+    let obj = ty.deref(ctx);
+    if let Some(array) = obj.downcast_ref::<MirArrayType>() {
+        let element_ty = array.element_type();
+        drop(obj);
+        return type_contains_packed_struct_storage(ctx, element_ty);
+    }
+    if let Some(tuple) = obj.downcast_ref::<MirTupleType>() {
+        let fields = tuple.get_types().to_vec();
+        drop(obj);
+        return fields
+            .into_iter()
+            .any(|field| type_contains_packed_struct_storage(ctx, field));
+    }
+    if let Some(structure) = obj.downcast_ref::<MirStructType>() {
+        let fields = structure.field_types().to_vec();
+        let field_offsets = structure.field_offsets().to_vec();
+        let mem_to_decl = structure.mem_to_decl.clone();
+        let total_size = structure.total_size;
+        drop(obj);
+
+        let uses_packed_storage = !struct_layout_matches_llvm_natural(
+            ctx,
+            &fields,
+            &field_offsets,
+            &mem_to_decl,
+            total_size,
+        ) && struct_layout_matches_llvm_storage(
+            ctx,
+            &fields,
+            &field_offsets,
+            &mem_to_decl,
+            total_size,
+        );
+        return uses_packed_storage
+            || fields
+                .into_iter()
+                .any(|field| type_contains_packed_struct_storage(ctx, field));
+    }
+
+    false
+}
+
+/// Whether rustc's recorded struct layout is one the lowering's non-packed
+/// LLVM struct actually reproduces at the byte level.
+///
+/// The lowering places fields at their recorded offsets by inserting explicit
+/// `[N x i8]` padding slots, which can only ADD bytes: a field can never land
+/// below its natural LLVM alignment, and LLVM still rounds the struct's size
+/// up to its natural alignment. So the built type agrees with rustc's byte
+/// image exactly when every stored field's offset is naturally aligned and
+/// non-overlapping in memory order, and `total_size` is a multiple of the
+/// struct's natural alignment. `repr(packed)` breaks the former (a `u32` at
+/// offset 1) and usually the latter (a 5-byte total), and either divergence
+/// makes a byte-image copy land fields at the wrong bytes.
+///
+/// A struct with no recorded layout (`field_offsets` empty or `total_size`
+/// zero) answers `true`: the lowering builds no padded layout to diverge
+/// from, and the promotion path's stored-size agreement check already fails
+/// closed on the unknown size. Any field whose natural size or alignment
+/// cannot be established answers `false`: no verdict means no promotion.
+fn struct_layout_matches_llvm_natural(
+    ctx: &Context,
+    field_types: &[TypeHandle],
+    field_offsets: &[u64],
+    mem_to_decl: &[usize],
+    total_size: u64,
+) -> bool {
+    if field_offsets.is_empty() || total_size == 0 {
+        return true;
+    }
+    if field_offsets.len() != field_types.len() {
+        return false;
+    }
+    // Empty `mem_to_decl` means identity (declaration order = memory order).
+    let identity: Vec<usize>;
+    let memory_order: &[usize] = if mem_to_decl.is_empty() {
+        identity = (0..field_types.len()).collect();
+        &identity
+    } else {
+        mem_to_decl
+    };
+
+    let mut end: u64 = 0;
+    let mut max_align: u64 = 1;
+    for &decl_idx in memory_order {
+        if decl_idx >= field_types.len() {
+            return false;
+        }
+        let Some((size, align)) = llvm_natural_size_align(ctx, field_types[decl_idx]) else {
+            return false;
+        };
+        // Zero-sized fields are stripped from the LLVM struct: no slot, no
+        // bytes, no alignment contribution (over-aligned ZSTs are refused
+        // before this walk runs).
+        if size == 0 {
+            continue;
+        }
+        let offset = field_offsets[decl_idx];
+        if !offset.is_multiple_of(align) || offset < end {
+            return false;
+        }
+        end = offset + size;
+        max_align = max_align.max(align);
+    }
+    total_size >= end && total_size.is_multiple_of(max_align)
+}
+
+/// Natural size and alignment of the LLVM storage a dialect type converts to,
+/// or `None` when the walk cannot establish them.
+///
+/// "Natural" means what LLVM's datalayout assigns the converted type with no
+/// packing: leaves are their own width and self-aligned, arrays inherit their
+/// element's alignment, and aggregates align to their most-aligned stored
+/// field because the padding slots between fields are `[N x i8]` with
+/// alignment one. Aggregates answer with rustc's `total_size` for their size;
+/// that matches the built LLVM type only when their own layout is natural,
+/// which [`struct_layout_matches_llvm_storage`] validates recursively (via
+/// [`promotable_array_element`]) before the answer is trusted. A field-less
+/// enum stores only its discriminant, so it aligns as that integer does.
+fn llvm_natural_size_align(ctx: &Context, ty: TypeHandle) -> Option<(u64, u64)> {
+    use dialect_mir::types::{MirArrayType, MirEnumType, MirPtrType, MirStructType, MirTupleType};
+
+    let obj = ty.deref(ctx);
+    if let Some(array) = obj.downcast_ref::<MirArrayType>() {
+        let element_ty = array.element_type();
+        let count = array.size();
+        drop(obj);
+        let (element_size, element_align) = llvm_natural_size_align(ctx, element_ty)?;
+        return Some((element_size.checked_mul(count)?, element_align));
+    }
+    if let Some(tuple) = obj.downcast_ref::<MirTupleType>() {
+        let fields = tuple.get_types().to_vec();
+        let total_size = tuple.total_size();
+        drop(obj);
+        let align = aggregate_natural_align(ctx, &fields)?;
+        return Some((total_size, align));
+    }
+    if let Some(structure) = obj.downcast_ref::<MirStructType>() {
+        let fields = structure.field_types().to_vec();
+        let total_size = structure.total_size;
+        drop(obj);
+        let align = aggregate_natural_align(ctx, &fields)?;
+        return Some((total_size, align));
+    }
+    if let Some(enumeration) = obj.downcast_ref::<MirEnumType>() {
+        let discriminant_ty = enumeration.discriminant_ty;
+        let total_size = enumeration.total_size();
+        drop(obj);
+        let (_, align) = llvm_natural_size_align(ctx, discriminant_ty)?;
+        return Some((total_size, align));
+    }
+    let size = if obj.is::<MirPtrType>() {
+        // cuda-oxide lowers device code for 64-bit NVPTX. Keep this helper
+        // independent of rustc's session TLS so it remains unit-testable.
+        8
+    } else if let Some(integer) = obj.downcast_ref::<IntegerType>() {
+        // `bool` arrives as `i1` and occupies a byte.
+        u64::from(integer.width().div_ceil(8)).max(1)
+    } else if obj.is::<MirFP16Type>() {
+        2
+    } else if obj.is::<FP32Type>() {
+        4
+    } else if obj.is::<FP64Type>() {
+        8
+    } else {
+        return None;
+    };
+    // Every scalar Rust hands this path is self-aligned at a power-of-two
+    // width; anything else has no natural alignment to report.
+    size.is_power_of_two().then_some((size, size))
+}
+
+/// Natural alignment of the LLVM struct built for an aggregate's fields:
+/// the maximum over the stored (non-zero-sized) fields, one when nothing is
+/// stored. `None` when some field's alignment cannot be established.
+fn aggregate_natural_align(ctx: &Context, fields: &[TypeHandle]) -> Option<u64> {
+    let mut align: u64 = 1;
+    for &field in fields {
+        let (field_size, field_align) = llvm_natural_size_align(ctx, field)?;
+        if field_size > 0 {
+            align = align.max(field_align);
+        }
+    }
+    Some(align)
+}
+
+/// Bytes a dialect type occupies, as the converted LLVM storage will lay it out,
+/// or `None` when that cannot be established from the type alone.
+///
+/// Aggregates answer with the `total_size` rustc gave them, which is exactly what
+/// the storage builders reproduce: they pad to reach each field's recorded offset
+/// and pad the tail to reach `total_size`. Leaves answer with their own width, and
+/// `i1` counts as the one byte Rust gives a `bool` rather than an eighth of one.
+///
+/// A zero answer is reported as `None`: the dialect uses `total_size() == 0` both
+/// for a genuine zero-sized type and for a size it does not know, and only the
+/// caller's own size comparison could tell them apart.
+fn dialect_stored_size(ctx: &Context, ty: TypeHandle) -> Option<u64> {
+    use dialect_mir::types::{MirArrayType, MirEnumType, MirPtrType, MirStructType, MirTupleType};
+
+    let obj = ty.deref(ctx);
+    let size = if let Some(array) = obj.downcast_ref::<MirArrayType>() {
+        let element = dialect_stored_size(ctx, array.element_type())?;
+        element.checked_mul(array.size())?
+    } else if let Some(tuple) = obj.downcast_ref::<MirTupleType>() {
+        tuple.total_size()
+    } else if let Some(structure) = obj.downcast_ref::<MirStructType>() {
+        structure.total_size()
+    } else if let Some(enumeration) = obj.downcast_ref::<MirEnumType>() {
+        enumeration.total_size()
+    } else if obj.is::<MirPtrType>() {
+        // cuda-oxide lowers device code for 64-bit NVPTX. Keep this helper
+        // independent of rustc's session TLS so it remains unit-testable.
+        8
+    } else if let Some(integer) = obj.downcast_ref::<IntegerType>() {
+        // `bool` arrives as `i1` and occupies a byte.
+        u64::from(integer.width().div_ceil(8)).max(1)
+    } else if obj.is::<MirFP16Type>() {
+        2
+    } else if obj.is::<FP32Type>() {
+        4
+    } else if obj.is::<FP64Type>() {
+        8
+    } else {
+        return None;
+    };
+    (size > 0).then_some(size)
+}
+
+/// Whether `local` is written exactly once — by the assignment being translated
+/// — and never has an address handed out.
+///
+/// This chooses *which of two correct lowerings* to use, never correctness: both
+/// give the local a private copy of the constant, and whether that copy is later
+/// deleted is `opt`'s own sound decision. So an unrecognised write form here only
+/// costs performance, which is why the statement match ends in a catch-all rather
+/// than an error.
+///
+/// It has to exist because the two lowerings fail in opposite directions. When
+/// the local really is read-only the copy disappears; when it is written the
+/// copy survives, and NVPTX expands a surviving `memcpy` into a *byte* loop —
+/// measurably worse than the element-wise stores it replaced. Rejecting every
+/// borrow, not just mutable ones, keeps this on the shape that motivates it
+/// (`TABLE[i]`, which projects a place and borrows nothing).
+fn constant_local_is_written_once(body: &mir::Body, local: mir::Local) -> bool {
+    let mut assignments = 0usize;
+    for block in body.blocks.iter() {
+        for statement in block.statements.iter() {
+            match &statement.kind {
+                mir::StatementKind::Assign(place, rvalue) => {
+                    if place.local == local {
+                        // A projected write is a write to part of the local.
+                        if !place.projection.is_empty() {
+                            return false;
+                        }
+                        assignments += 1;
+                    }
+                    // Any borrow or raw pointer, of either mutability, is a
+                    // path this scan cannot follow.
+                    match rvalue {
+                        mir::Rvalue::Ref(_, _, source) if source.local == local => return false,
+                        mir::Rvalue::AddressOf(_, source) if source.local == local => return false,
+                        _ => {}
+                    }
+                }
+                mir::StatementKind::SetDiscriminant { place, .. } if place.local == local => {
+                    return false;
+                }
+                _ => {}
+            }
+        }
+        // A call writes its destination.
+        if let mir::TerminatorKind::Call { destination, .. } = &block.terminator.kind
+            && destination.local == local
+        {
+            return false;
+        }
+    }
+    assignments == 1
+}
+
+/// Fill an addressable local from a fully-constant array by copying an immutable
+/// device global into it, instead of building the array in registers first.
+///
+/// `Ok(None)` means "not this shape" and the caller keeps the ordinary path.
+///
+/// # Why a copy and not just the global's address
+///
+/// The local is ordinary mutable storage — `let mut t = TABLE; t[0] = x;` is
+/// legal — so handing out the global's address would be wrong in general. A
+/// `memcpy` from `constant` storage is unconditionally correct instead, and
+/// `opt` supplies the proof that removes it: `isOnlyCopiedFromConstantMemory`
+/// deletes the copy and rewrites the reads to the global wherever the local is
+/// never written.
+///
+/// [`constant_local_is_written_once`] gates the path on the same property, so
+/// the two agree. It is not redundant: a copy that survives is *worse* than what
+/// it replaced, because NVPTX expands a surviving `memcpy` into a byte loop.
+///
+/// # Why this is worth doing at all
+///
+/// The value form cannot reach the global no matter how it is spelled: LLVM
+/// splits every first-class-aggregate load, so a whole-array load from the
+/// global is folded straight back into one store per element. Only a `memcpy`
+/// survives to the point where the proof can run.
+///
+/// What this replaces, for `TABLE[i]` with a runtime `i`, is one `st.local` per
+/// element in *every thread* — a per-thread copy of data the module image
+/// already carries — followed by `ld.local` reads of thread-private memory.
+pub(crate) fn translate_array_constant_into_alloca(
+    ctx: &mut Context,
+    body: &mir::Body,
+    dest_place: &mir::Place,
+    constant: &mir::ConstOperand,
+    value_map: &ValueMap,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    use pliron::builtin::attributes::IntegerAttr;
+
+    // Whole-local assignment only. With a projection the copy would have to land
+    // at an offset, which the ordinary element-wise path already handles.
+    if !dest_place.projection.is_empty() {
+        return Ok(None);
+    }
+    let Some(dest_addr) = value_map.get_slot(dest_place.local) else {
+        return Ok(None);
+    };
+    if !constant_local_is_written_once(body, dest_place.local) {
+        return Ok(None);
+    }
+
+    let rust_ty = constant.const_.ty();
+    let Ok(value_ty) = types::translate_type(ctx, &rust_ty) else {
+        return Ok(None);
+    };
+    if !value_ty.deref(ctx).is::<dialect_mir::types::MirArrayType>() {
+        return Ok(None);
+    }
+    // Elements whose whole-element read is a single scalar-like load, or whose
+    // fields are each addressed in place: primitive scalars, field-less enums,
+    // recursively promotable tuples and structs, and nested arrays of those.
+    if !promotable_array_element(ctx, value_ty) {
+        return Ok(None);
+    }
+    let Ok(expected_size) = rust_type_layout_size(rust_ty, loc.clone()) else {
+        return Ok(None);
+    };
+    // The copy is sized from the destination's *converted* type, while the bytes
+    // come from rustc's evaluated allocation. Require the two to agree before
+    // trusting a byte image: a padded tuple or an enum reaches its layout through
+    // `build_struct_slot_map` / `build_enum_slot_map`, and if either ever stopped
+    // reproducing rustc's size, this is the check that keeps a byte image from
+    // being copied over a differently-sized local.
+    if dialect_stored_size(ctx, value_ty) != Some(expected_size as u64) {
+        return Ok(None);
+    }
+    // Preserve both the evaluated byte image and any supported pointer
+    // relocations. Unsupported relocation targets keep the existing element-wise
+    // fallback rather than partially promoting the table.
+    let Ok(initializer) = promoted_array_initializer(constant, expected_size, "array", loc.clone())
+    else {
+        return Ok(None);
+    };
+    let promoted_anchor = materialize_promoted_initializer_targets(
+        ctx,
+        &initializer.relocations,
+        block_ptr,
+        prev_op,
+        loc.clone(),
+    )?;
+
+    // Past every promotion bail-out: emit one immutable global and copy it into the local.
+    let global_alloc = emit_promoted_immutable_global(
+        ctx,
+        value_ty,
+        &initializer,
+        block_ptr,
+        promoted_anchor,
+        loc.clone(),
+    );
+    let src = global_alloc.get_operation().deref(ctx).get_result(0);
+
+    // `mir.memcpy`'s count is in destination-pointee elements, and the
+    // destination slot points at the whole array, so one element is the whole
+    // table.
+    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signed);
+    let count_attr = IntegerAttr::new(i64_ty, APInt::from_i64(1, NonZeroUsize::new(64).unwrap()));
+    let count_op = Operation::new(
+        ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    count_op.deref_mut(ctx).set_loc(loc.clone());
+    MirConstantOp::new(count_op).set_attr_value(ctx, count_attr);
+    count_op.insert_after(ctx, global_alloc.get_operation());
+    let count = count_op.deref(ctx).get_result(0);
+
+    // Typed builder: stamps the elem_type fact from dest_addr (the whole
+    // promoted aggregate type; count is 1), read back by lowering.
+    let memcpy_op = dialect_mir::ops::MirMemcpyOp::build(ctx, dest_addr, src, count)?;
+    memcpy_op.deref_mut(ctx).set_loc(loc);
+    memcpy_op.insert_after(ctx, count_op);
+
+    Ok(Some(memcpy_op))
+}
+
+/// Enforce the pointer-to-array constant element boundary, as a hard error.
+///
+/// The admission question is [`promotable_array_element`], the same predicate
+/// used by the bare array value path's immutable-global optimization. A bare
+/// array that fails this gate can still fall back to element-wise materialization;
+/// a pointer-to-array constant has no such fallback, so failure here is an input
+/// error. Structs pass only when every field is recursively promotable.
+fn validate_ptr_to_array_constant_type(
+    ctx: &Context,
+    ty: TypeHandle,
+    loc: Location,
+) -> TranslationResult<()> {
+    if promotable_array_element(ctx, ty) {
+        return Ok(());
+    }
+
+    input_err!(
+        loc,
+        TranslationErr::unsupported(format!(
+            "Array constant element type is not supported: {:?}. Supported promoted array constants are primitive scalars (integers, f16, f32, f64), thin pointers/references with supported static relocations, field-less enums, tuples and structs recursively composed of supported fields, or nested arrays of those.",
+            ty.deref(ctx)
+        ))
+    )
+}
+
+pub(super) fn constant_allocation(
+    constant: &mir::ConstOperand,
+) -> Option<&rustc_public::ty::Allocation> {
+    match constant.const_.kind() {
+        ConstantKind::Allocated(alloc) => Some(alloc),
+        ConstantKind::Ty(ty_const) => match ty_const.kind() {
+            rustc_public::ty::TyConstKind::Value(_, alloc) => Some(alloc),
+            _ => None,
+        },
+        _ => None,
+    }
+}
+
+fn promoted_constant_dedup_key(
+    ctx: &Context,
+    ty: TypeHandle,
+    initializer: &GlobalInitializerData,
+) -> String {
+    let relocations = encode_global_initializer_relocations(&initializer.relocations);
+    promoted_constant_dedup_key_from_parts(
+        ctx,
+        ty,
+        &initializer.bytes,
+        initializer.alignment,
+        &relocations,
+    )
+}
+
+fn promoted_constant_dedup_key_from_parts(
+    ctx: &Context,
+    ty: TypeHandle,
+    bytes: &[u8],
+    alignment: u64,
+    relocations: &str,
+) -> String {
+    // This string is only an in-pass map key; it never becomes the emitted
+    // symbol name. Keep the full type, byte image, allocation alignment, and
+    // relocation encoding so constants with identical bytes but different
+    // storage requirements or provenance targets cannot alias.
+    let ty = ty.deref(ctx).disp(ctx).to_string();
+    let bytes = bytes_to_hex(bytes);
+    let fingerprint = format!(
+        "__cuda_oxide_promoted_type{}:{ty}:bytes{}:{bytes}:align{alignment}:relocs{}:{relocations}",
+        ty.len(),
+        bytes.len() / 2,
+        relocations.len()
+    );
+    dialect_mir::ops::encode_promoted_global_key(&fingerprint)
+}
+
+#[cfg(test)]
+mod pointer_array_constant_type_tests {
+    use super::validate_ptr_to_array_constant_type;
+    use dialect_mir::types::{
+        EnumVariant, MirArrayType, MirEnumType, MirPtrType, MirStructType, MirTupleType,
+    };
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::context::Context;
+    use pliron::location::Location;
+    use pliron::r#type::TypeHandle;
+
+    #[test]
+    fn pointer_array_constant_boundary_admits_recursive_promotable_aggregates() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let primitive_array: TypeHandle = MirArrayType::get(&mut ctx, u32_ty, 3).into();
+        let nested_primitive_array: TypeHandle =
+            MirArrayType::get(&mut ctx, primitive_array, 2).into();
+        assert!(
+            validate_ptr_to_array_constant_type(&ctx, nested_primitive_array, Location::Unknown)
+                .is_ok(),
+            "recursively nested primitive arrays remain supported"
+        );
+
+        let struct_ty: TypeHandle = MirStructType::get(
+            &mut ctx,
+            "PointerArrayElement".into(),
+            vec!["value".into()],
+            vec![u32_ty],
+        )
+        .into();
+        let struct_array: TypeHandle = MirArrayType::get(&mut ctx, struct_ty, 2).into();
+        assert!(
+            validate_ptr_to_array_constant_type(&ctx, struct_array, Location::Unknown).is_ok(),
+            "pointer-to-array constants admit structs whose fields are promotable"
+        );
+
+        // The reference form shares the immutable-promotion gate. A packed
+        // struct whose selected packed LLVM storage reproduces rustc exactly
+        // must therefore be accepted here as well.
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let packed_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedPointerArrayElement".into(),
+            vec!["tag".into(), "value".into()],
+            vec![u8_ty, u32_ty],
+            vec![],
+            vec![0, 1],
+            5,
+            1,
+        )
+        .into();
+        let packed_struct_array: TypeHandle =
+            MirArrayType::get(&mut ctx, packed_struct_ty, 2).into();
+        assert!(
+            validate_ptr_to_array_constant_type(&ctx, packed_struct_array, Location::Unknown,)
+                .is_ok(),
+            "const R: &[Packed; N] = &TABLE must share the packed immutable global"
+        );
+
+        let nested_struct_array: TypeHandle = MirArrayType::get(&mut ctx, struct_array, 2).into();
+        assert!(
+            validate_ptr_to_array_constant_type(&ctx, nested_struct_array, Location::Unknown)
+                .is_ok(),
+            "nesting preserves a promotable struct leaf"
+        );
+
+        // The shared predicate gates both bare-value promotion and this
+        // reference form. The initializer is rustc's evaluated byte image and
+        // the size-agreement check rejects any layout the dialect reproduces
+        // differently, so recursive tuples and structs travel this path without
+        // rebuilding fields here.
+        let tuple_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![u32_ty]).into();
+        let tuple_array: TypeHandle = MirArrayType::get(&mut ctx, tuple_ty, 2).into();
+        assert!(
+            validate_ptr_to_array_constant_type(&ctx, tuple_array, Location::Unknown).is_ok(),
+            "const R: &[(u32,); N] = &TABLE must pass the same gate the bare table passes"
+        );
+
+        // A tuple containing a promotable struct is recursively admissible too.
+        let tuple_with_struct_ty: TypeHandle =
+            MirTupleType::get(&mut ctx, vec![u32_ty, struct_ty]).into();
+        let tuple_with_struct_array: TypeHandle =
+            MirArrayType::get(&mut ctx, tuple_with_struct_ty, 2).into();
+        assert!(
+            validate_ptr_to_array_constant_type(&ctx, tuple_with_struct_array, Location::Unknown)
+                .is_ok(),
+            "a promotable struct field keeps its tuple in the reference form"
+        );
+
+        // Pointer-bearing structs are promotable now that immutable globals
+        // preserve rustc relocation metadata instead of flattening pointer
+        // placeholder bytes.
+        let pointer_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let pointer_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PointerBearingElement".into(),
+            vec!["pointer".into()],
+            vec![pointer_ty],
+            vec![],
+            vec![0],
+            8,
+            8,
+        )
+        .into();
+        let pointer_struct_array: TypeHandle =
+            MirArrayType::get(&mut ctx, pointer_struct_ty, 2).into();
+        assert!(
+            validate_ptr_to_array_constant_type(&ctx, pointer_struct_array, Location::Unknown)
+                .is_ok(),
+            "pointer-bearing structs are admitted by relocation-aware promotion"
+        );
+    }
+
+    #[test]
+    fn pointer_array_constant_boundary_matches_the_bare_array_gate_for_enums() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let fieldless_variants = vec!["Add", "Sub"]
+            .into_iter()
+            .map(|name| EnumVariant {
+                name: name.into(),
+                field_types: vec![],
+                field_offsets: vec![],
+                field_sizes: vec![],
+            })
+            .collect();
+        let op_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "Op".into(),
+            u32_ty,
+            vec![0, 1],
+            fieldless_variants,
+            0,
+            4,
+            4,
+        )
+        .into();
+        let op_array: TypeHandle = MirArrayType::get(&mut ctx, op_ty, 8).into();
+        assert!(
+            validate_ptr_to_array_constant_type(&ctx, op_array, Location::Unknown).is_ok(),
+            "const R: &[Op; N] = &OPS must pass the same gate the bare table passes"
+        );
+
+        let payload_variants = vec![
+            EnumVariant {
+                name: "None".into(),
+                field_types: vec![],
+                field_offsets: vec![],
+                field_sizes: vec![],
+            },
+            EnumVariant {
+                name: "Some".into(),
+                field_types: vec![u32_ty],
+                field_offsets: vec![4],
+                field_sizes: vec![4],
+            },
+        ];
+        let maybe_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "Maybe".into(),
+            u32_ty,
+            vec![0, 1],
+            payload_variants,
+            0,
+            8,
+            4,
+        )
+        .into();
+        let maybe_array: TypeHandle = MirArrayType::get(&mut ctx, maybe_ty, 4).into();
+        assert!(
+            validate_ptr_to_array_constant_type(&ctx, maybe_array, Location::Unknown).is_err(),
+            "a payload-carrying enum stays out of the reference form too"
+        );
+
+        // The `&[]` shape: a promoted empty-slice constant keeps its
+        // any-element admission now that the check routes through the shared
+        // predicate.
+        let struct_ty: TypeHandle = MirStructType::get(
+            &mut ctx,
+            "EmptySliceElement".into(),
+            vec!["value".into()],
+            vec![u32_ty],
+        )
+        .into();
+        let empty_struct_array: TypeHandle = MirArrayType::get(&mut ctx, struct_ty, 0).into();
+        assert!(
+            validate_ptr_to_array_constant_type(&ctx, empty_struct_array, Location::Unknown)
+                .is_ok(),
+            "a zero-length array has nothing readable, whatever its element type"
+        );
+    }
+}
+
+#[cfg(test)]
+mod promotable_array_element_tests {
+    use super::super::const_alloc::validate_array_value_element_type;
+    use super::{dialect_stored_size, promotable_array_element, promoted_global_validation_type};
+    use dialect_mir::types::{
+        EnumVariant, MirArrayType, MirEnumType, MirPtrType, MirStructType, MirTupleType,
+    };
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::context::Context;
+    use pliron::location::Location;
+    use pliron::r#type::TypeHandle;
+
+    /// A field-less enum with a recorded layout, as rustc gives a `#[repr(u32)]`
+    /// C-like enum.
+    fn fieldless_enum(ctx: &mut Context, u32_ty: TypeHandle) -> TypeHandle {
+        let variants = vec!["Add", "Sub"]
+            .into_iter()
+            .map(|name| EnumVariant {
+                name: name.into(),
+                field_types: vec![],
+                field_offsets: vec![],
+                field_sizes: vec![],
+            })
+            .collect();
+        MirEnumType::get_with_layout(ctx, "Op".into(), u32_ty, vec![0, 1], variants, 0, 4, 4).into()
+    }
+
+    /// The same shape, except one variant carries a payload.
+    fn payload_enum(ctx: &mut Context, u32_ty: TypeHandle) -> TypeHandle {
+        let variants = vec![
+            EnumVariant {
+                name: "None".into(),
+                field_types: vec![],
+                field_offsets: vec![],
+                field_sizes: vec![],
+            },
+            EnumVariant {
+                name: "Some".into(),
+                field_types: vec![u32_ty],
+                field_offsets: vec![4],
+                field_sizes: vec![4],
+            },
+        ];
+        MirEnumType::get_with_layout(ctx, "Maybe".into(), u32_ty, vec![0, 1], variants, 0, 8, 4)
+            .into()
+    }
+
+    #[test]
+    fn promotion_admits_recursive_promotable_aggregates() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+
+        let scalars: TypeHandle = MirArrayType::get(&mut ctx, u32_ty, 4).into();
+        assert!(
+            promotable_array_element(&ctx, scalars),
+            "a scalar array is the shape this already promoted"
+        );
+        let nested: TypeHandle = MirArrayType::get(&mut ctx, scalars, 2).into();
+        assert!(
+            promotable_array_element(&ctx, nested),
+            "nesting must not lose a promotable leaf"
+        );
+
+        let op_ty = fieldless_enum(&mut ctx, u32_ty);
+        let op_array: TypeHandle = MirArrayType::get(&mut ctx, op_ty, 8).into();
+        assert!(
+            promotable_array_element(&ctx, op_array),
+            "a field-less enum element is its discriminant, so one load reads it"
+        );
+        let nested_ops: TypeHandle = MirArrayType::get(&mut ctx, op_array, 2).into();
+        assert!(
+            promotable_array_element(&ctx, nested_ops),
+            "nested field-less enum arrays stay promotable"
+        );
+
+        // Payload-carrying enums still use a value path that round-trips their
+        // payload through memory, so they remain outside immutable-global promotion.
+        let maybe_ty = payload_enum(&mut ctx, u32_ty);
+        let maybe_array: TypeHandle = MirArrayType::get(&mut ctx, maybe_ty, 4).into();
+        assert!(
+            !promotable_array_element(&ctx, maybe_array),
+            "a payload-carrying enum round-trips its payload through memory"
+        );
+
+        let tuple_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![u32_ty, u32_ty]).into();
+        let tuple_array: TypeHandle = MirArrayType::get(&mut ctx, tuple_ty, 4).into();
+        assert!(
+            promotable_array_element(&ctx, tuple_array),
+            "a tuple of promotable fields is promotable now that a field read \
+             addresses in place instead of copying the array"
+        );
+        let nested_tuple_arrays: TypeHandle = MirArrayType::get(&mut ctx, tuple_array, 2).into();
+        assert!(
+            promotable_array_element(&ctx, nested_tuple_arrays),
+            "nesting must not lose a promotable tuple leaf"
+        );
+
+        let struct_ty: TypeHandle = MirStructType::get(
+            &mut ctx,
+            "Element".into(),
+            vec!["value".into()],
+            vec![u32_ty],
+        )
+        .into();
+        let struct_array: TypeHandle = MirArrayType::get(&mut ctx, struct_ty, 4).into();
+        assert!(
+            promotable_array_element(&ctx, struct_array),
+            "a struct of promotable fields is promotable"
+        );
+
+        // Recursive aggregates remain promotable when every leaf is promotable.
+        let tuple_with_struct: TypeHandle =
+            MirTupleType::get(&mut ctx, vec![u32_ty, struct_ty]).into();
+        let tuple_with_struct_array: TypeHandle =
+            MirArrayType::get(&mut ctx, tuple_with_struct, 4).into();
+        assert!(
+            promotable_array_element(&ctx, tuple_with_struct_array),
+            "a promotable struct field keeps its tuple promotable"
+        );
+        let nested_struct_arrays: TypeHandle =
+            MirArrayType::get(&mut ctx, tuple_with_struct_array, 2).into();
+        assert!(
+            promotable_array_element(&ctx, nested_struct_arrays),
+            "nesting preserves recursive promotability"
+        );
+
+        // A zero-byte over-aligned struct carries an ABI constraint that is not
+        // visible in the lowered storage shape. Preserve the established
+        // alignment-sensitive value path for aggregates containing such a leaf.
+        let over_aligned_zst_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "OverAlignedZst".into(),
+            vec![],
+            vec![],
+            vec![],
+            vec![],
+            0,
+            32,
+        )
+        .into();
+        let tuple_with_over_aligned_zst: TypeHandle =
+            MirTupleType::get(&mut ctx, vec![over_aligned_zst_ty, u32_ty]).into();
+        let over_aligned_zst_array: TypeHandle =
+            MirArrayType::get(&mut ctx, tuple_with_over_aligned_zst, 2).into();
+        assert!(
+            !promotable_array_element(&ctx, over_aligned_zst_array),
+            "a zero-byte over-aligned struct must keep its containing aggregate on the alignment-sensitive path"
+        );
+
+        // Thin pointers are scalar load leaves once their initializer
+        // provenance is preserved as relocation metadata. Pin their concrete
+        // storage size too, so admission cannot later fail the byte-size gate.
+        let pointer_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let pointer_array: TypeHandle = MirArrayType::get(&mut ctx, pointer_ty, 4).into();
+        assert!(
+            promotable_array_element(&ctx, pointer_array),
+            "a thin pointer is itself a promotable scalar load leaf"
+        );
+        assert_eq!(
+            dialect_stored_size(&ctx, pointer_array),
+            Some(32),
+            "four NVPTX64 pointers occupy 32 bytes"
+        );
+
+        // Use a full rustc-style layout so this assertion exercises
+        // struct_layout_matches_llvm_natural instead of its unknown-layout
+        // early return.
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let pointer_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PointerBearingElement".into(),
+            vec!["pointer".into(), "tag".into()],
+            vec![pointer_ty, u8_ty],
+            vec![],
+            vec![0, 8],
+            16,
+            8,
+        )
+        .into();
+        let pointer_struct_array: TypeHandle =
+            MirArrayType::get(&mut ctx, pointer_struct_ty, 4).into();
+        assert!(
+            promotable_array_element(&ctx, pointer_struct_array),
+            "a naturally laid out struct containing a thin pointer is promotable"
+        );
+
+        let struct_with_payload_enum: TypeHandle = MirStructType::get(
+            &mut ctx,
+            "PayloadEnumElement".into(),
+            vec!["value".into()],
+            vec![maybe_ty],
+        )
+        .into();
+        let payload_struct_array: TypeHandle =
+            MirArrayType::get(&mut ctx, struct_with_payload_enum, 4).into();
+        assert!(
+            !promotable_array_element(&ctx, payload_struct_array),
+            "a payload-enum leaf must keep its containing struct out of promotion"
+        );
+    }
+
+    #[test]
+    fn packed_struct_promotion_requires_byte_faithful_storage() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+
+        // `#[repr(C, packed)] struct Packed { tag: u8, value: u32 }`: rustc
+        // records `value` at offset 1 and a five-byte total. The natural LLVM
+        // struct diverges, but the packed LLVM representation is exactly
+        // `<{ i8, i32 }>` and therefore preserves both offsets and stride.
+        let packed_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Packed".into(),
+            vec!["tag".into(), "value".into()],
+            vec![u8_ty, u32_ty],
+            vec![],
+            vec![0, 1],
+            5,
+            1,
+        )
+        .into();
+        let packed_struct_array: TypeHandle =
+            MirArrayType::get(&mut ctx, packed_struct_ty, 4).into();
+        assert!(
+            promotable_array_element(&ctx, packed_struct_array),
+            "a byte-faithful packed struct must use immutable-global promotion"
+        );
+        assert_eq!(
+            dialect_stored_size(&ctx, packed_struct_array),
+            Some(20),
+            "four packed five-byte elements must retain rustc's stride"
+        );
+
+        let empty_packed_array: TypeHandle =
+            MirArrayType::get(&mut ctx, packed_struct_ty, 0).into();
+        assert!(
+            promotable_array_element(&ctx, empty_packed_array),
+            "a zero-length packed array remains vacuously promotable"
+        );
+        assert_eq!(
+            promoted_global_validation_type(&mut ctx, empty_packed_array, 0),
+            empty_packed_array,
+            "zero-byte promotion must retain the semantic [Packed; 0] type"
+        );
+        let packed_byte_len = dialect_stored_size(&ctx, packed_struct_array).unwrap() as usize;
+        let packed_validation =
+            promoted_global_validation_type(&mut ctx, packed_struct_array, packed_byte_len);
+        let packed_validation_ref = packed_validation.deref(&ctx);
+        let packed_validation_array = packed_validation_ref
+            .downcast_ref::<MirArrayType>()
+            .expect("packed validation storage must be an array");
+        assert_eq!(packed_validation_array.size, 20);
+        assert_eq!(packed_validation_array.element_ty, u8_ty);
+        drop(packed_validation_ref);
+        // `repr(C, packed(2))` keeps one explicit byte between the fields and
+        // a six-byte stride. Natural LLVM still cannot place the u32 at offset
+        // two, while a packed struct plus one byte padding slot can.
+        let packed2_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Packed2".into(),
+            vec!["tag".into(), "value".into()],
+            vec![u8_ty, u32_ty],
+            vec![],
+            vec![0, 2],
+            6,
+            2,
+        )
+        .into();
+        let packed2_array: TypeHandle = MirArrayType::get(&mut ctx, packed2_struct_ty, 3).into();
+        assert!(
+            promotable_array_element(&ctx, packed2_array),
+            "packed(2) must be admitted when explicit padding reproduces rustc exactly"
+        );
+        assert_eq!(
+            dialect_stored_size(&ctx, packed2_array),
+            Some(18),
+            "packed(2) array promotion must preserve the six-byte element stride"
+        );
+
+        // A naturally laid-out outer struct may contain a packed child. The
+        // child's selected storage is already byte-faithful, so recursive
+        // promotion must not re-impose the child's natural alignment.
+        let outer_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "OuterWithPacked".into(),
+            vec!["head".into(), "inner".into()],
+            vec![u32_ty, packed_struct_ty],
+            vec![],
+            vec![0, 4],
+            12,
+            4,
+        )
+        .into();
+        let outer_array: TypeHandle = MirArrayType::get(&mut ctx, outer_ty, 2).into();
+        assert!(
+            promotable_array_element(&ctx, outer_array),
+            "a recursively byte-faithful packed child must remain promotable"
+        );
+
+        // Synthetic overlapping field ranges model layouts that no sequential
+        // natural or packed LLVM struct can express. Keep this fail-closed even
+        // though the individual leaves are promotable.
+        let overlapping_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Overlapping".into(),
+            vec!["tag".into(), "value".into()],
+            vec![u8_ty, u32_ty],
+            vec![],
+            vec![0, 0],
+            4,
+            1,
+        )
+        .into();
+        let overlapping_array: TypeHandle = MirArrayType::get(&mut ctx, overlapping_ty, 2).into();
+        assert!(
+            !promotable_array_element(&ctx, overlapping_array),
+            "overlapping storage must remain outside immutable-global promotion"
+        );
+
+        // Bare-array admission stays broader than promotion, so a layout that
+        // fails the promotion gate still has its existing element-wise fallback.
+        assert!(
+            validate_array_value_element_type(&ctx, overlapping_ty, &Location::Unknown).is_ok(),
+            "the bare-array fallback must remain available for an unpromotable struct"
+        );
+
+        let natural_struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Natural".into(),
+            vec!["tag".into(), "value".into()],
+            vec![u8_ty, u32_ty],
+            vec![],
+            vec![0, 4],
+            8,
+            4,
+        )
+        .into();
+        let natural_struct_array: TypeHandle =
+            MirArrayType::get(&mut ctx, natural_struct_ty, 4).into();
+        assert!(
+            promotable_array_element(&ctx, natural_struct_array),
+            "natural-layout struct promotion must remain unchanged"
+        );
+    }
+
+    /// Coupling oracle: every struct layout the promotion gate admits must be
+    /// one mir-lower actually lowers byte-faithfully (natural, or packed with
+    /// explicit padding). The promotion gate swaps the global's validation
+    /// type to a byte view, so this agreement is the only thing standing
+    /// between an admitted layout and typed reads through a divergent
+    /// natural-layout fallback. If this test fails after changing either
+    /// side's layout walk, the two predicates have drifted.
+    #[test]
+    fn promoted_struct_layouts_agree_with_the_mir_lower_storage_selection() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+
+        // (name, offsets, total_size, align) for each struct shape the
+        // promotion test admits; every one must be byte-faithful downstream.
+        let admitted = [
+            ("Packed", vec![0u64, 1], 5u64, 1u64),
+            ("Packed2", vec![0, 2], 6, 2),
+            ("Natural", vec![0, 4], 8, 4),
+        ];
+        for (name, offsets, total_size, align) in admitted {
+            let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+                &mut ctx,
+                name.into(),
+                vec!["tag".into(), "value".into()],
+                vec![u8_ty, u32_ty],
+                vec![],
+                offsets,
+                total_size,
+                align,
+            )
+            .into();
+            let array_ty: TypeHandle = MirArrayType::get(&mut ctx, struct_ty, 2).into();
+            assert!(
+                promotable_array_element(&ctx, array_ty),
+                "`{name}` must stay in the promotion corpus this test guards"
+            );
+            assert!(
+                mir_lower::convert::types::struct_value_lowering_is_byte_faithful(
+                    &mut ctx, struct_ty
+                )
+                .expect("slot map must build for an admitted layout"),
+                "`{name}` is admitted for promotion but mir-lower would fall \
+                 back to a divergent natural layout; the two layout walks have \
+                 drifted"
+            );
+        }
+
+        // The known-unfaithful shape must stay rejected on BOTH sides.
+        let overlapping_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Overlapping".into(),
+            vec!["tag".into(), "value".into()],
+            vec![u8_ty, u32_ty],
+            vec![],
+            vec![0, 0],
+            4,
+            1,
+        )
+        .into();
+        let overlapping_array: TypeHandle = MirArrayType::get(&mut ctx, overlapping_ty, 2).into();
+        assert!(
+            !promotable_array_element(&ctx, overlapping_array),
+            "overlapping storage must remain outside promotion"
+        );
+        assert!(
+            !mir_lower::convert::types::struct_value_lowering_is_byte_faithful(
+                &mut ctx,
+                overlapping_ty
+            )
+            .expect("slot map must still build for the overlapping layout"),
+            "mir-lower must agree that overlapping storage is not byte-faithful"
+        );
+    }
+
+    #[test]
+    fn an_enum_without_a_recorded_layout_is_not_promoted() {
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        // `total_size` 0 means the layout was never recorded, so the byte image
+        // has nothing to be checked against.
+        let variants = vec![EnumVariant {
+            name: "Only".into(),
+            field_types: vec![],
+            field_offsets: vec![],
+            field_sizes: vec![],
+        }];
+        let unsized_enum: TypeHandle =
+            MirEnumType::get(&mut ctx, "Unknown".into(), u32_ty, vec![0], variants).into();
+        let array: TypeHandle = MirArrayType::get(&mut ctx, unsized_enum, 4).into();
+        assert!(
+            !promotable_array_element(&ctx, array),
+            "an enum with no recorded size must not be promoted"
+        );
+    }
+}
+
+#[cfg(test)]
+mod promoted_global_tests {
+    use super::*;
+
+    #[test]
+    fn promoted_immutable_globals_are_marked_and_dedup_by_type_and_initializer() {
+        use dialect_mir::types::MirArrayType;
+        use pliron::builtin::ops::ModuleOp;
+        use pliron::linked_list::ContainsLinkedList;
+
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let module = ModuleOp::new(&mut ctx, "promoted_globals".try_into().unwrap());
+        let module_region = module.get_operation().deref(&ctx).get_region(0);
+        let block = {
+            let existing = module_region.deref(&ctx).iter(&ctx).next();
+            match existing {
+                Some(block) => block,
+                None => {
+                    let block = BasicBlock::new(&mut ctx, None, vec![]);
+                    block.insert_at_back(module_region, &ctx);
+                    block
+                }
+            }
+        };
+
+        let f32_ty: TypeHandle = FP32Type::get(&ctx).into();
+        let table_ty: TypeHandle = MirArrayType::get(&mut ctx, f32_ty, 2).into();
+        let bytes = vec![0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x00, 0x40]; // [1.0f32, 2.0f32]
+        let initializer = GlobalInitializerData {
+            bytes,
+            alignment: 4,
+            relocations: Vec::new(),
+        };
+
+        let first = emit_promoted_immutable_global(
+            &mut ctx,
+            table_ty,
+            &initializer,
+            block,
+            None,
+            Location::Unknown,
+        );
+
+        // The marker is the point: without it the exporter writes `global` and
+        // `opt` may not delete the per-thread copy this path exists to remove.
+        assert!(
+            first.is_immutable(&ctx),
+            "promoted global must be immutable"
+        );
+        let first_key = String::from(first.get_attr_global_key(&ctx).expect("dedup key").clone());
+
+        // The same table reached again, through another function or spelling,
+        // must produce the same key.
+        let again = emit_promoted_immutable_global(
+            &mut ctx,
+            table_ty,
+            &initializer,
+            block,
+            None,
+            Location::Unknown,
+        );
+        let again_key = String::from(again.get_attr_global_key(&ctx).expect("dedup key").clone());
+        assert_eq!(
+            first_key, again_key,
+            "same type, bytes, and relocations must share a key"
+        );
+
+        // A different byte image must not alias.
+        let other_initializer = GlobalInitializerData {
+            bytes: vec![0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x80, 0x3f],
+            alignment: 4,
+            relocations: Vec::new(),
+        };
+        let other = emit_promoted_immutable_global(
+            &mut ctx,
+            table_ty,
+            &other_initializer,
+            block,
+            None,
+            Location::Unknown,
+        );
+        let other_key = String::from(other.get_attr_global_key(&ctx).expect("dedup key").clone());
+        assert_ne!(first_key, other_key, "distinct bytes must not share a key");
+    }
+
+    #[test]
+    fn promoted_dedup_key_distinguishes_relocation_identity() {
+        use dialect_mir::types::MirArrayType;
+
+        let mut ctx = Context::new();
+        crate::translator::register_dialects(&mut ctx);
+
+        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let table_ty: TypeHandle = MirArrayType::get(&mut ctx, i64_ty, 1).into();
+        let bytes = [0u8; 8];
+
+        // Pointer placeholder bytes and addends may be identical. The target key
+        // is rustc's provenance identity and must therefore participate in the
+        // promoted-global dedup key.
+        let target_a = "v1 1 0 8 1 0 8 target_a ";
+        let target_b = "v1 1 0 8 1 0 8 target_b ";
+
+        let key_a = promoted_constant_dedup_key_from_parts(&ctx, table_ty, &bytes, 8, target_a);
+        let key_b = promoted_constant_dedup_key_from_parts(&ctx, table_ty, &bytes, 8, target_b);
+        assert_ne!(
+            key_a, key_b,
+            "identical bytes with different relocation targets must not alias"
+        );
+
+        let differently_aligned =
+            promoted_constant_dedup_key_from_parts(&ctx, table_ty, &bytes, 16, target_a);
+        assert_ne!(
+            key_a, differently_aligned,
+            "identical type, bytes, and relocations with different allocation alignment must not alias"
+        );
+    }
+}
diff --git a/crates/mir-importer/src/translator/rvalue/static_global.rs b/crates/mir-importer/src/translator/rvalue/static_global.rs
new file mode 100644
index 0000000000..3351ed07c7
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/static_global.rs
@@ -0,0 +1,484 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Static global materialization state machine.
+
+use super::const_union::validate_device_static_union_initializer;
+use super::statics::{
+    GlobalInitializerRelocation, bytes_to_hex, encode_global_initializer_relocations,
+    static_global_key, static_initializer_data,
+};
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::facts;
+use crate::translator::types;
+use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
+use dialect_mir::ops::{MirCastOp, MirConstantOp, MirGlobalAllocOp, MirPtrOffsetOp};
+use dialect_mir::types::MirPointerKind;
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use rustc_public::CrateDef;
+use std::num::NonZeroUsize;
+
+#[derive(Clone, Copy)]
+pub(super) struct MaterializedStaticGlobal {
+    base_ptr: Value,
+    global_op: Ptr<Operation>,
+    allocation_size: u64,
+}
+
+pub(super) struct StaticGlobalMaterializationState {
+    pub(super) globals: std::collections::HashMap<String, MaterializedStaticGlobal>,
+    pub(super) last_op: Option<Ptr<Operation>>,
+}
+
+/// Materialize one device static and every static reachable from its initializer.
+///
+/// The current global is registered before traversing its relocations. That
+/// makes self-references and mutually recursive static graphs finite while the
+/// lowering pass still performs module-wide deduplication by `global_key`.
+fn ensure_static_global_alloc(
+    ctx: &mut Context,
+    static_def: &rustc_public::mir::mono::StaticDef,
+    is_mutable: bool,
+    block_ptr: Ptr<BasicBlock>,
+    loc: Location,
+    state: &mut StaticGlobalMaterializationState,
+) -> TranslationResult<MaterializedStaticGlobal> {
+    let global_key = static_global_key(static_def);
+    if let Some(existing) = state.globals.get(&global_key) {
+        return Ok(*existing);
+    }
+
+    let initializer = static_initializer_data(static_def, loc.clone())?;
+    let allocation_size = initializer.bytes.len() as u64;
+    let initializer_hex = bytes_to_hex(&initializer.bytes);
+    let static_ty = static_def.ty();
+    let is_constant = is_constant_wrapper_type(&static_ty);
+    let global_ty = types::translate_type(ctx, &static_ty)?;
+
+    if let Some(union_name) = stored_type_union_name(static_ty, &mut Vec::new()) {
+        if global_ty
+            .deref(ctx)
+            .is::<dialect_mir::types::MirUnionType>()
+        {
+            validate_device_static_union_initializer(
+                ctx,
+                static_def,
+                global_ty,
+                &initializer,
+                loc.clone(),
+            )?;
+        } else {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "device static {} contains nested union `{union_name}`; device-global \
+                     union initializer relocations are supported only for a top-level \
+                     thin-pointer union",
+                    static_def.name()
+                ))
+            );
+        }
+    }
+    let global_ptr_ty: TypeHandle = if is_constant {
+        dialect_mir::types::MirPtrType::get_constant(ctx, global_ty, is_mutable).into()
+    } else {
+        dialect_mir::types::MirPtrType::get_global(ctx, global_ty, is_mutable).into()
+    };
+
+    let global_op = Operation::new(
+        ctx,
+        MirGlobalAllocOp::get_concrete_op_info(),
+        vec![global_ptr_ty],
+        vec![],
+        vec![],
+        0,
+    );
+    global_op.deref_mut(ctx).set_loc(loc.clone());
+
+    let global_alloc = MirGlobalAllocOp::new(global_op);
+
+    use pliron::builtin::attributes::{StringAttr, TypeAttr};
+
+    global_alloc.set_attr_global_type(ctx, TypeAttr::new(global_ty));
+    global_alloc.set_attr_global_key(ctx, StringAttr::new(global_key.clone()));
+    set_global_initializer_hex_attr(ctx, global_alloc.get_operation(), &initializer_hex);
+    if !initializer.relocations.is_empty() {
+        let encoded = encode_global_initializer_relocations(&initializer.relocations);
+        set_global_initializer_relocations_attr(ctx, global_alloc.get_operation(), &encoded);
+    }
+
+    if initializer.alignment > 0 {
+        global_alloc.set_alignment_value(ctx, initializer.alignment);
+    }
+
+    match state.last_op {
+        Some(previous) => global_alloc.get_operation().insert_after(ctx, previous),
+        None => global_alloc.get_operation().insert_at_front(block_ptr, ctx),
+    }
+    state.last_op = Some(global_alloc.get_operation());
+
+    let materialized = MaterializedStaticGlobal {
+        base_ptr: global_alloc.get_operation().deref(ctx).get_result(0),
+        global_op: global_alloc.get_operation(),
+        allocation_size,
+    };
+    state.globals.insert(global_key, materialized);
+
+    let owner_description = format!("device static {}", static_def.name());
+    ensure_initializer_relocation_targets(
+        ctx,
+        &initializer.relocations,
+        &owner_description,
+        block_ptr,
+        loc,
+        state,
+    )?;
+
+    Ok(materialized)
+}
+
+/// Materialize and validate every static referenced by an initializer.
+///
+/// The owner is already registered by [`ensure_static_global_alloc`] before
+/// recursion reaches this helper, so self-references and mutually recursive
+/// static graphs remain finite.
+pub(super) fn ensure_initializer_relocation_targets(
+    ctx: &mut Context,
+    relocations: &[GlobalInitializerRelocation],
+    owner_description: &str,
+    block_ptr: Ptr<BasicBlock>,
+    loc: Location,
+    state: &mut StaticGlobalMaterializationState,
+) -> TranslationResult<()> {
+    for relocation in relocations {
+        let target = ensure_static_global_alloc(
+            ctx,
+            &relocation.target_static,
+            false,
+            block_ptr,
+            loc.clone(),
+            state,
+        )?;
+        if relocation.target_addend > target.allocation_size {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "{owner_description} relocation at byte {} points {} bytes into {}, but the target allocation is only {} bytes",
+                    relocation.source_offset,
+                    relocation.target_addend,
+                    relocation.target_static.name(),
+                    target.allocation_size
+                ))
+            );
+        }
+    }
+    Ok(())
+}
+
+pub(super) fn translate_static_global_pointer(
+    ctx: &mut Context,
+    static_def: &rustc_public::mir::mono::StaticDef,
+    result_pointee_ty: TypeHandle,
+    result_ptr_ty: TypeHandle,
+    is_mutable: bool,
+    byte_offset: u64,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Value, Option<Ptr<Operation>>)> {
+    let mut state = StaticGlobalMaterializationState {
+        globals: std::collections::HashMap::new(),
+        last_op: prev_op,
+    };
+    let materialized = ensure_static_global_alloc(
+        ctx,
+        static_def,
+        is_mutable,
+        block_ptr,
+        loc.clone(),
+        &mut state,
+    )?;
+
+    // Rust const evaluation permits forming a pointer one past the end of
+    // an allocation (offset == allocation size); only offsets strictly
+    // beyond the allocation are impossible for rustc to have produced.
+    // Forming the pointer is what is translated here, so the check must
+    // not add a pointee-size term.
+    if byte_offset > materialized.allocation_size {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "constant pointer to device static {} has byte offset {}, \
+                 but the static allocation is only {} bytes",
+                static_def.name(),
+                byte_offset,
+                materialized.allocation_size
+            ))
+        );
+    }
+
+    let base_ptr = materialized.base_ptr;
+    let insert_after = state.last_op.unwrap_or(materialized.global_op);
+
+    let (base_pointee_ty, address_space) = {
+        let base_ty = base_ptr.get_type(ctx);
+        let base_ty = base_ty.deref(ctx);
+        let base_ptr_ty = base_ty
+            .downcast_ref::<dialect_mir::types::MirPtrType>()
+            .expect("MirGlobalAllocOp must return MirPtrType");
+        (base_ptr_ty.pointee, base_ptr_ty.address_space)
+    };
+
+    // Preserve the existing direct path. It avoids generating unnecessary
+    // casts and pointer arithmetic for ordinary references to whole statics.
+    // The result is still normalized to the exact translated Rust operand
+    // type: slot stores and mem2reg are type-strict, so the physical
+    // address-space pointer must not leak into the function body. A zero-addend
+    // relocation may still name the first element of an array static (or an
+    // equivalent differently typed view). Keep those on the byte-addressed
+    // path below so `StaticAddress` establishes only the final kind/address
+    // space after generic Erased casts have normalized the pointee shape.
+    if byte_offset == 0 && base_pointee_ty == result_pointee_ty {
+        let (result, last_op) =
+            retype_static_pointer_result(ctx, base_ptr, result_ptr_ty, insert_after, loc);
+        return Ok((result, Some(last_op)));
+    }
+
+    // mir.ptr_offset scales by sizeof(pointee). Cast to u8 first so the
+    // rustc addend is interpreted as bytes rather than static elements.
+    let byte_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Unsigned).into();
+
+    let byte_ptr_ty: TypeHandle =
+        dialect_mir::types::MirPtrType::get(ctx, byte_ty, is_mutable, address_space).into();
+
+    // The address arithmetic stays in the static's physical address space
+    // (LLVM GEPs cannot change address spaces); the exact-Rust-type
+    // normalization happens once, at the end.
+    let interior_ptr_ty: TypeHandle =
+        dialect_mir::types::MirPtrType::get(ctx, result_pointee_ty, is_mutable, address_space)
+            .into();
+
+    // 1. *StaticType addrspace(N) -> *u8 addrspace(N)
+    let to_byte_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![byte_ptr_ty],
+        vec![base_ptr],
+        vec![],
+        0,
+    );
+    to_byte_op.deref_mut(ctx).set_loc(loc.clone());
+
+    let to_byte_cast = MirCastOp::new(to_byte_op);
+    to_byte_cast.set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+    to_byte_cast.get_operation().insert_after(ctx, insert_after);
+
+    let byte_ptr = to_byte_cast.get_operation().deref(ctx).get_result(0);
+
+    // 2. Materialize the rustc byte addend as usize.
+    let offset_ty = types::get_usize_type(ctx);
+    let offset_attr = pliron::builtin::attributes::IntegerAttr::new(
+        offset_ty,
+        APInt::from_u64(
+            byte_offset,
+            NonZeroUsize::new(64).expect("usize must have non-zero width"),
+        ),
+    );
+
+    let offset_const_op = Operation::new(
+        ctx,
+        MirConstantOp::get_concrete_op_info(),
+        vec![offset_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    offset_const_op.deref_mut(ctx).set_loc(loc.clone());
+
+    let offset_const = MirConstantOp::new(offset_const_op);
+    offset_const.set_attr_value(ctx, offset_attr);
+    offset_const
+        .get_operation()
+        .insert_after(ctx, to_byte_cast.get_operation());
+
+    let offset_value = offset_const.get_operation().deref(ctx).get_result(0);
+
+    // 3. Apply the addend. Since the pointer now points to u8, one element
+    // equals exactly one byte.
+    let ptr_offset_op = Operation::new(
+        ctx,
+        MirPtrOffsetOp::get_concrete_op_info(),
+        vec![byte_ptr_ty],
+        vec![byte_ptr, offset_value],
+        vec![],
+        0,
+    );
+    ptr_offset_op.deref_mut(ctx).set_loc(loc.clone());
+    ptr_offset_op.insert_after(ctx, offset_const.get_operation());
+
+    let offset_byte_ptr = ptr_offset_op.deref(ctx).get_result(0);
+
+    // 4. *u8 addrspace(N) -> *ResultPointee addrspace(N)
+    let result_cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![interior_ptr_ty],
+        vec![offset_byte_ptr],
+        vec![],
+        0,
+    );
+    result_cast_op.deref_mut(ctx).set_loc(loc.clone());
+
+    let result_cast = MirCastOp::new(result_cast_op);
+    result_cast.set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+    result_cast.get_operation().insert_after(ctx, ptr_offset_op);
+
+    // 5. Normalize to the exact translated Rust operand type (lowering
+    // emits an `addrspacecast` when the address spaces differ).
+    let result = result_cast.get_operation().deref(ctx).get_result(0);
+    let (result, last_op) =
+        retype_static_pointer_result(ctx, result, result_ptr_ty, result_cast.get_operation(), loc);
+    Ok((result, Some(last_op)))
+}
+
+/// Retype a materialized static-pointer `value` to the exact translated Rust
+/// operand type.
+///
+/// `MirGlobalAllocOp` results (and interior-pointer arithmetic built on
+/// them) carry the static's physical address space, but slot stores and
+/// mem2reg are type-strict: the constant operand must have the exact
+/// translated Rust type. Lowering turns this `PtrToPtr` cast into an
+/// `addrspacecast` when the address spaces differ, which
+/// `InferAddressSpaces` later folds back through for direct loads.
+fn retype_static_pointer_result(
+    ctx: &mut Context,
+    value: Value,
+    result_ptr_ty: TypeHandle,
+    insert_after: Ptr<Operation>,
+    loc: Location,
+) -> (Value, Ptr<Operation>) {
+    if value.get_type(ctx) == result_ptr_ty {
+        return (value, insert_after);
+    }
+
+    let cast_op = Operation::new(
+        ctx,
+        MirCastOp::get_concrete_op_info(),
+        vec![result_ptr_ty],
+        vec![value],
+        vec![],
+        0,
+    );
+    cast_op.deref_mut(ctx).set_loc(loc);
+    let cast = MirCastOp::new(cast_op);
+    cast.set_attr_cast_kind(ctx, MirCastKindAttr::PtrToPtr);
+    if result_ptr_ty
+        .deref(ctx)
+        .downcast_ref::<dialect_mir::types::MirPtrType>()
+        .is_some_and(|pointer| pointer.kind != MirPointerKind::Erased)
+    {
+        cast.set_pointer_kind_authority(ctx, MirPointerKindAuthorityAttr::StaticAddress);
+    }
+    cast_op.insert_after(ctx, insert_after);
+
+    (cast_op.deref(ctx).get_result(0), cast_op)
+}
+
+/// Return the first union stored inline in `ty`.
+///
+/// Pointer pointees are deliberately not followed: their bytes are not part of
+/// the containing allocation, and initializer relocations are collected through
+/// rustc provenance separately. Arrays, tuples, structs, and enum payloads are
+/// inline and must be searched recursively.
+pub(super) fn stored_type_union_name(
+    ty: rustc_public::ty::Ty,
+    visited: &mut Vec<rustc_public::ty::Ty>,
+) -> Option<String> {
+    use rustc_public::ty::{AdtKind, RigidTy, TyKind};
+
+    if visited.contains(&ty) {
+        return None;
+    }
+    visited.push(ty);
+
+    match ty.kind() {
+        TyKind::RigidTy(RigidTy::Adt(adt_def, substs)) => {
+            if matches!(adt_def.kind(), AdtKind::Union) {
+                return Some(adt_def.trimmed_name());
+            }
+            for variant in adt_def.variants() {
+                for field in variant.fields() {
+                    if let Some(name) = stored_type_union_name(field.ty_with_args(&substs), visited)
+                    {
+                        return Some(name);
+                    }
+                }
+            }
+            None
+        }
+        TyKind::RigidTy(RigidTy::Array(element, _)) | TyKind::RigidTy(RigidTy::Slice(element)) => {
+            stored_type_union_name(element, visited)
+        }
+        TyKind::RigidTy(RigidTy::Tuple(elements)) => {
+            for element in elements.iter() {
+                if let Some(name) = stored_type_union_name(*element, visited) {
+                    return Some(name);
+                }
+            }
+            None
+        }
+        _ => None,
+    }
+}
+
+pub(super) fn set_global_initializer_hex_attr(
+    ctx: &mut Context,
+    op: Ptr<Operation>,
+    initializer_hex: &str,
+) {
+    use pliron::builtin::attributes::StringAttr;
+    use pliron::identifier::Identifier;
+
+    let key = Identifier::try_new("global_initializer_hex".to_string()).expect("valid identifier");
+    op.deref_mut(ctx)
+        .attributes
+        .set(key, StringAttr::new(initializer_hex.to_string()));
+}
+
+pub(super) fn set_global_initializer_relocations_attr(
+    ctx: &mut Context,
+    op: Ptr<Operation>,
+    relocations: &str,
+) {
+    use pliron::builtin::attributes::StringAttr;
+    use pliron::identifier::Identifier;
+
+    let key = Identifier::try_new("global_initializer_relocations".to_string())
+        .expect("valid identifier");
+    op.deref_mut(ctx)
+        .attributes
+        .set(key, StringAttr::new(relocations.to_string()));
+}
+
+/// Check if a type is a pointer/reference to a static allocation.
+/// Returns `(pointee_ty, origin)` when the type can carry a static address.
+/// Keeping the origin here prevents constant materialization from collapsing
+/// `&T`/`&mut T` and raw pointers before they enter `dialect-mir`.
+use crate::translator::values::is_constant_wrapper_type;
+
+pub(super) fn get_static_pointer_info(
+    ty: &rustc_public::ty::Ty,
+) -> Option<(rustc_public::ty::Ty, facts::PointerOrigin)> {
+    facts::pointer_origin_of_ty(ty)
+}
diff --git a/crates/mir-importer/src/translator/rvalue/statics.rs b/crates/mir-importer/src/translator/rvalue/statics.rs
new file mode 100644
index 0000000000..4d04409f4d
--- /dev/null
+++ b/crates/mir-importer/src/translator/rvalue/statics.rs
@@ -0,0 +1,563 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Static identity and initializer plumbing.
+
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::values::is_constant_wrapper_type;
+use pliron::location::Location;
+use pliron::{input_err, input_error_noloc};
+use rustc_public::CrateDef;
+use rustc_public::mir;
+use rustc_public::ty::ConstantKind;
+
+pub(super) struct SharedStaticSourceIdentity {
+    pub(super) name: String,
+    pub(super) key: String,
+}
+
+/// Resolve a whole-static shared allocation to both its display path and its
+/// injective compiler identity.
+///
+/// `StaticDef::name()` deliberately omits DefPath disambiguators, so distinct
+/// same-leaf nested statics can have the same display path. The mangled static
+/// instance remains unique and is used for both deduplication and the full-debug
+/// side-table join. Interior pointers are rejected: a `SharedArray` or
+/// `Barrier` allocation always represents the entire static.
+pub(super) fn shared_static_source_identity(
+    constant: &mir::ConstOperand,
+) -> Option<SharedStaticSourceIdentity> {
+    let ConstantKind::Allocated(allocation) = constant.const_.kind() else {
+        return None;
+    };
+    if allocation.provenance.ptrs.len() != 1 {
+        return None;
+    }
+    let &(relocation_offset, _) = allocation.provenance.ptrs.first()?;
+    let target = static_target_from_allocation_at(allocation, relocation_offset)
+        .ok()
+        .flatten()?;
+    if target.byte_offset != 0 {
+        return None;
+    }
+    let name = target.static_def.name();
+    let key = crate::device_static_global_key(&target.static_def);
+    Some(SharedStaticSourceIdentity { name, key })
+}
+
+/// Historical best-effort source label used by non-Full builds.
+///
+/// This intentionally performs no strict validation: the comment label must
+/// never turn an otherwise valid translation into an error.
+pub(super) fn shared_static_source_name(constant: &mir::ConstOperand) -> Option<String> {
+    use rustc_public::mir::alloc::GlobalAlloc;
+
+    let ConstantKind::Allocated(allocation) = constant.const_.kind() else {
+        return None;
+    };
+    let &(_, provenance) = allocation.provenance.ptrs.first()?;
+    match GlobalAlloc::from(provenance.0) {
+        GlobalAlloc::Static(static_def) => Some(static_def.name()),
+        _ => None,
+    }
+}
+
+/// Resolve a constant pointer/reference to the Rust static it points at, if any.
+///
+/// The source allocation stores the pointer's byte addend at the relocation
+/// offset, while the provenance entry identifies the target allocation. Keeping
+/// both pieces together prevents interior pointers from silently degrading to
+/// the static's base address. Anonymous allocations return `None`.
+pub(super) struct StaticPointerTarget {
+    pub(super) static_def: rustc_public::mir::mono::StaticDef,
+    pub(super) byte_offset: u64,
+}
+
+pub(super) fn static_target_from_constant(
+    constant: &mir::ConstOperand,
+    loc: Location,
+) -> TranslationResult<Option<StaticPointerTarget>> {
+    let ConstantKind::Allocated(allocation) = constant.const_.kind() else {
+        return Ok(None);
+    };
+
+    if allocation.is_null().unwrap_or(false) {
+        return Ok(None);
+    }
+
+    let Some(&(relocation_offset, _)) = allocation.provenance.ptrs.first() else {
+        return Ok(None);
+    };
+
+    if allocation.provenance.ptrs.len() != 1 {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "constant pointer contains {} provenance entries; expected one static target",
+                allocation.provenance.ptrs.len()
+            ))
+        );
+    }
+    static_target_from_allocation_at(allocation, relocation_offset)
+}
+
+/// Resolve the pointer relocation beginning at `relocation_offset` to a static.
+///
+/// Unlike `static_target_from_constant`, this operates on an aggregate's own
+/// allocation and therefore does not require that the allocation contain only
+/// one relocation.
+pub(super) fn static_target_from_allocation_at(
+    allocation: &rustc_public::ty::Allocation,
+    relocation_offset: usize,
+) -> TranslationResult<Option<StaticPointerTarget>> {
+    use rustc_public::mir::alloc::GlobalAlloc;
+
+    let Some(&(provenance_offset, provenance)) = allocation
+        .provenance
+        .ptrs
+        .iter()
+        .find(|(offset, _)| *offset == relocation_offset)
+    else {
+        return Ok(None);
+    };
+
+    let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+    let pointer_end = provenance_offset
+        .checked_add(pointer_width)
+        .ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "constant static-pointer relocation at byte {provenance_offset} overflowed"
+            )))
+        })?;
+    let byte_offset = allocation
+        .read_partial_uint(provenance_offset..pointer_end)
+        .map_err(|error| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "Failed to read constant static-pointer addend at byte {provenance_offset}: \
+                 {error:?}"
+            )))
+        })? as u64;
+
+    match GlobalAlloc::from(provenance.0) {
+        GlobalAlloc::Static(static_def) => Ok(Some(StaticPointerTarget {
+            static_def,
+            byte_offset,
+        })),
+        _ => Ok(None),
+    }
+}
+
+/// One pointer-width relocation inside an evaluated Rust static initializer.
+///
+/// The source and target offsets are byte offsets. `target_key` is the same
+/// domain-tagged rustc identity stored on the target `MirGlobalAllocOp`.
+pub(super) struct GlobalInitializerRelocation {
+    pub(super) source_offset: u64,
+    pub(super) width_bytes: u32,
+    target_address_space: u32,
+    pub(super) target_addend: u64,
+    target_key: String,
+    pub(super) target_static: rustc_public::mir::mono::StaticDef,
+}
+
+/// The byte image, ABI alignment, and pointer relocations of a global initializer.
+///
+/// Literal bytes remain byte-exact. Pointer slots are carried separately so
+/// lowering can replace their placeholder addend bytes with LLVM relocation
+/// expressions without changing padding, NaN payloads, or field offsets.
+pub(crate) struct GlobalInitializerData {
+    pub(super) bytes: Vec<u8>,
+    pub(super) alignment: u64,
+    pub(super) relocations: Vec<GlobalInitializerRelocation>,
+}
+
+pub(super) fn static_global_key(static_def: &rustc_public::mir::mono::StaticDef) -> String {
+    crate::device_static_global_key(static_def)
+}
+
+fn static_global_address_space(static_def: &rustc_public::mir::mono::StaticDef) -> u32 {
+    if is_constant_wrapper_type(&static_def.ty()) {
+        4
+    } else {
+        1
+    }
+}
+
+/// Encode initializer relocations using the versioned, length-prefixed format
+/// consumed by `mir-lower` and `llvm-export`.
+pub(super) fn encode_global_initializer_relocations(
+    relocations: &[GlobalInitializerRelocation],
+) -> String {
+    fn put_u64(out: &mut String, value: u64) {
+        out.push_str(&value.to_string());
+        out.push(' ');
+    }
+
+    fn put_str(out: &mut String, value: &str) {
+        put_u64(out, value.len() as u64);
+        out.push_str(value);
+        out.push(' ');
+    }
+
+    let mut encoded = String::from("v1 ");
+    put_u64(&mut encoded, relocations.len() as u64);
+    for relocation in relocations {
+        put_u64(&mut encoded, relocation.source_offset);
+        put_u64(&mut encoded, u64::from(relocation.width_bytes));
+        put_u64(&mut encoded, u64::from(relocation.target_address_space));
+        put_u64(&mut encoded, relocation.target_addend);
+        put_str(&mut encoded, &relocation.target_key);
+    }
+    encoded
+}
+
+/// Copy one evaluated allocation into a byte-exact global initializer.
+///
+/// Undefined bytes are Rust padding and become deterministic zeros. Each
+/// provenance entry is preserved as a static-to-static pointer relocation.
+/// Anonymous memory, functions, vtables, and malformed source ranges remain
+/// diagnosed rather than being flattened to integer bytes.
+pub(super) fn allocation_initializer_data(
+    alloc: &rustc_public::ty::Allocation,
+    description: &str,
+    loc: Location,
+) -> TranslationResult<GlobalInitializerData> {
+    use rustc_public::mir::alloc::GlobalAlloc;
+
+    let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+    let width_bytes = u32::try_from(pointer_width).map_err(|_| {
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "{description} uses a target pointer width that does not fit u32"
+        )))
+    })?;
+
+    if !alloc.provenance.ptrs.is_empty() && pointer_width != 8 {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "{description} contains pointer relocations, but cuda-oxide currently supports only 8-byte NVPTX pointers"
+            ))
+        );
+    }
+
+    let mut entries: Vec<_> = alloc.provenance.ptrs.to_vec();
+    entries.sort_by_key(|(source_offset, _)| *source_offset);
+
+    let mut relocations = Vec::with_capacity(entries.len());
+    let mut previous_end = 0usize;
+
+    for (index, (source_offset, provenance)) in entries.into_iter().enumerate() {
+        if source_offset < previous_end {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "{description} pointer relocation {index} overlaps the previous relocation"
+                ))
+            );
+        }
+
+        let end = source_offset.checked_add(pointer_width).ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "{description} pointer relocation {index} source range overflows"
+            )))
+        })?;
+        if end > alloc.bytes.len() {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "{description} pointer relocation {index} occupies bytes {source_offset}..{end}, but the allocation is only {} bytes",
+                    alloc.bytes.len()
+                ))
+            );
+        }
+
+        let target_addend = alloc
+            .read_partial_uint(source_offset..end)
+            .map_err(|error| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Failed to read {description} pointer relocation {index} addend: {error:?}"
+                )))
+            })? as u64;
+
+        let target_static = match GlobalAlloc::from(provenance.0) {
+            GlobalAlloc::Static(static_def) => static_def,
+            other => {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "{description} pointer relocation {index} targets unsupported allocation {other:?}; only Rust statics in CUDA global or constant memory are supported"
+                    ))
+                );
+            }
+        };
+
+        relocations.push(GlobalInitializerRelocation {
+            source_offset: u64::try_from(source_offset).map_err(|_| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "{description} pointer relocation {index} source offset does not fit u64"
+                )))
+            })?,
+            width_bytes,
+            target_address_space: static_global_address_space(&target_static),
+            target_addend,
+            target_key: static_global_key(&target_static),
+            target_static,
+        });
+        previous_end = end;
+    }
+
+    Ok(GlobalInitializerData {
+        bytes: alloc.bytes.iter().map(|byte| byte.unwrap_or(0)).collect(),
+        alignment: alloc.align,
+        relocations,
+    })
+}
+
+/// Build the byte-exact, relocation-aware initializer used by array promotion.
+///
+/// Bare `[T; N]` constants own their allocation directly, so provenance entries
+/// inside that allocation belong to pointer fields in the table. Pointer-to-array
+/// constants (`&[T; N]` / `*const [T; N]`) instead contain one outer relocation
+/// to the backing allocation; that relocation is followed once and any
+/// relocations inside the selected table range are preserved and rebased.
+pub(super) fn promoted_array_initializer(
+    constant: &mir::ConstOperand,
+    expected_size: usize,
+    kind_name: &str,
+    loc: Location,
+) -> TranslationResult<GlobalInitializerData> {
+    use rustc_public::mir::alloc::GlobalAlloc;
+    use rustc_public::ty::{RigidTy, TyConstKind, TyKind};
+
+    fn direct_initializer(
+        alloc: &rustc_public::ty::Allocation,
+        expected_size: usize,
+        kind_name: &str,
+        loc: Location,
+    ) -> TranslationResult<GlobalInitializerData> {
+        let data = allocation_initializer_data(
+            alloc,
+            &format!("promoted {kind_name} initializer"),
+            loc.clone(),
+        )?;
+        if data.bytes.len() != expected_size {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "promoted {kind_name} initializer is {} bytes, expected {expected_size}",
+                    data.bytes.len()
+                ))
+            );
+        }
+        Ok(data)
+    }
+
+    fn project_initializer_range(
+        data: GlobalInitializerData,
+        target_offset: usize,
+        expected_size: usize,
+        kind_name: &str,
+        loc: Location,
+    ) -> TranslationResult<GlobalInitializerData> {
+        let end = target_offset.checked_add(expected_size).ok_or_else(|| {
+            input_error_noloc!(TranslationErr::unsupported(format!(
+                "promoted {kind_name} initializer offset overflows its allocation"
+            )))
+        })?;
+        let bytes = data
+            .bytes
+            .get(target_offset..end)
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "promoted {kind_name} initializer needs bytes {target_offset}..{end}, but its backing allocation is only {} bytes",
+                    data.bytes.len()
+                )))
+            })?
+            .to_vec();
+        let alignment = data.alignment;
+
+        let mut relocations = Vec::new();
+        for relocation in data.relocations {
+            let source_start = usize::try_from(relocation.source_offset).map_err(|_| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "promoted {kind_name} relocation source offset {} does not fit usize",
+                    relocation.source_offset
+                )))
+            })?;
+            let width = usize::try_from(relocation.width_bytes).map_err(|_| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "promoted {kind_name} relocation width {} does not fit usize",
+                    relocation.width_bytes
+                )))
+            })?;
+            let source_end = source_start.checked_add(width).ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "promoted {kind_name} relocation at byte {source_start} overflows"
+                )))
+            })?;
+            let overlaps = source_start < end && source_end > target_offset;
+            if !overlaps {
+                continue;
+            }
+            if source_start < target_offset || source_end > end {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "promoted {kind_name} relocation bytes {source_start}..{source_end} cross selected initializer range {target_offset}..{end}"
+                    ))
+                );
+            }
+
+            relocations.push(GlobalInitializerRelocation {
+                source_offset: u64::try_from(source_start - target_offset).map_err(|_| {
+                    input_error_noloc!(TranslationErr::unsupported(format!(
+                        "promoted {kind_name} rebased relocation offset does not fit u64"
+                    )))
+                })?,
+                width_bytes: relocation.width_bytes,
+                target_address_space: relocation.target_address_space,
+                target_addend: relocation.target_addend,
+                target_key: relocation.target_key,
+                target_static: relocation.target_static,
+            });
+        }
+
+        Ok(GlobalInitializerData {
+            bytes,
+            alignment,
+            relocations,
+        })
+    }
+
+    fn pointer_initializer(
+        alloc: &rustc_public::ty::Allocation,
+        expected_size: usize,
+        kind_name: &str,
+        loc: Location,
+    ) -> TranslationResult<GlobalInitializerData> {
+        if alloc.provenance.ptrs.len() != 1 {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "promoted {kind_name} pointer contains {} provenance entries; expected exactly one backing allocation",
+                    alloc.provenance.ptrs.len()
+                ))
+            );
+        }
+        let &(provenance_offset, provenance) =
+            alloc.provenance.ptrs.first().expect("length checked above");
+
+        let pointer_width = rustc_public::target::MachineInfo::target_pointer_width().bytes();
+        let pointer_end = provenance_offset
+            .checked_add(pointer_width)
+            .ok_or_else(|| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "promoted {kind_name} outer pointer range overflows"
+                )))
+            })?;
+        let target_offset = alloc
+            .read_partial_uint(provenance_offset..pointer_end)
+            .map_err(|e| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Failed to read promoted {kind_name} pointer offset: {e:?}"
+                )))
+            })? as usize;
+
+        let target_alloc = match GlobalAlloc::from(provenance.0) {
+            GlobalAlloc::Memory(target_alloc) => target_alloc,
+            GlobalAlloc::Static(static_def) => static_def.eval_initializer().map_err(|e| {
+                input_error_noloc!(TranslationErr::unsupported(format!(
+                    "Failed to evaluate promoted {kind_name} backing static {}: {e:?}",
+                    static_def.name()
+                )))
+            })?,
+            other => {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(format!(
+                        "promoted {kind_name} provenance points to unsupported allocation {other:?}"
+                    ))
+                );
+            }
+        };
+
+        let data = allocation_initializer_data(
+            &target_alloc,
+            &format!("promoted {kind_name} backing allocation"),
+            loc.clone(),
+        )?;
+        project_initializer_range(data, target_offset, expected_size, kind_name, loc)
+    }
+
+    let pointer_form = matches!(
+        constant.const_.ty().kind(),
+        TyKind::RigidTy(RigidTy::RawPtr(_, _)) | TyKind::RigidTy(RigidTy::Ref(_, _, _))
+    );
+
+    match constant.const_.kind() {
+        ConstantKind::Allocated(alloc) => {
+            if pointer_form {
+                pointer_initializer(alloc, expected_size, kind_name, loc)
+            } else {
+                direct_initializer(alloc, expected_size, kind_name, loc)
+            }
+        }
+        ConstantKind::Ty(ty_const) => match ty_const.kind() {
+            TyConstKind::Value(_, alloc) => {
+                if pointer_form {
+                    pointer_initializer(alloc, expected_size, kind_name, loc)
+                } else {
+                    direct_initializer(alloc, expected_size, kind_name, loc)
+                }
+            }
+            TyConstKind::ZSTValue(_) if expected_size == 0 => Ok(GlobalInitializerData {
+                bytes: Vec::new(),
+                alignment: 1,
+                relocations: Vec::new(),
+            }),
+            other => input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "promoted {kind_name} initializer must be backed by bytes, found TyConstKind::{other:?}"
+                ))
+            ),
+        },
+        ConstantKind::ZeroSized if expected_size == 0 => Ok(GlobalInitializerData {
+            bytes: Vec::new(),
+            alignment: 1,
+            relocations: Vec::new(),
+        }),
+        other => input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "promoted {kind_name} initializer must be allocated, found {other:?}"
+            ))
+        ),
+    }
+}
+
+/// Return rustc's evaluated static initializer bytes, alignment, and relocations.
+pub(super) fn static_initializer_data(
+    static_def: &rustc_public::mir::mono::StaticDef,
+    loc: Location,
+) -> TranslationResult<GlobalInitializerData> {
+    let alloc = static_def.eval_initializer().map_err(|e| {
+        input_error_noloc!(TranslationErr::unsupported(format!(
+            "Failed to evaluate initializer for device static {}: {:?}",
+            static_def.name(),
+            e
+        )))
+    })?;
+    allocation_initializer_data(&alloc, &format!("device static {}", static_def.name()), loc)
+}
+
+pub(super) fn bytes_to_hex(bytes: &[u8]) -> String {
+    let mut hex = String::with_capacity(bytes.len() * 2);
+    for byte in bytes {
+        use std::fmt::Write as _;
+        write!(&mut hex, "{byte:02x}").expect("writing to String cannot fail");
+    }
+    hex
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated.rs
deleted file mode 100644
index 40fd19815c..0000000000
--- a/crates/mir-importer/src/translator/terminator/intrinsics/generated.rs
+++ /dev/null
@@ -1,94518 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
-// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
-// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
-
-//! Generated raw/compatibility path dispatch for CUDA intrinsics.
-
-use crate::error::{TranslationErr, TranslationResult};
-use crate::translator::values::ValueMap;
-use crate::translator::{rvalue, terminator::helpers, types};
-use dialect_nvvm::ops::{
-    AbsBf16x2Op, AbsF16x2Op, ActiveMaskOp, AddBf16x2Op, AddF16x2Op, AddF32x2Op, AddFtzF32x2Op,
-    BarWarpSyncOp, Barrier0Op, BarrierCtaArriveAlignedCountOp, BarrierCtaArriveCountOp,
-    BarrierCtaSyncAlignedCountOp, BarrierCtaSyncCountOp, BreakpointOp, ClcQueryGetFirstCtaidXOp,
-    ClcQueryGetFirstCtaidYOp, ClcQueryGetFirstCtaidZOp, ClcQueryIsCanceledOp,
-    ClcTryCancelMulticastOp, ClcTryCancelOp, ClusterBarrierModeAttr, ClusterBarrierOp,
-    CpAsyncCa4Op, CpAsyncCa8Op, CpAsyncCa16Op, CpAsyncCaZfill4Op, CpAsyncCaZfill8Op,
-    CpAsyncCaZfill16Op, CpAsyncCg16Op, CpAsyncCgZfill16Op, CpAsyncCommitGroupOp,
-    CpAsyncMbarrierArriveNoIncOp, CpAsyncMbarrierArriveNoIncSharedOp, CpAsyncMbarrierArriveOp,
-    CpAsyncMbarrierArriveSharedOp, CpAsyncWaitAllOp, CpAsyncWaitGroupOp, CvtF16x2F32Op,
-    CvtF32x2Bf16x2Op, CvtRnF16x2E4m3x2Op, CvtRnF16x2E5m2x2Op, CvtRnReluBf16x2F32Op,
-    CvtRnReluF16x2E4m3x2Op, CvtRnReluF16x2E5m2x2Op, CvtRnReluF16x2F32Op,
-    CvtRnSatfiniteE4m3x2F16x2Op, CvtRnSatfiniteE4m3x2F32Op, CvtRnSatfiniteE5m2x2F16x2Op,
-    CvtRnSatfiniteE5m2x2F32Op, CvtRnSatfiniteReluE4m3x2F16x2Op, CvtRnSatfiniteReluE4m3x2F32Op,
-    CvtRnSatfiniteReluE5m2x2F16x2Op, CvtRnSatfiniteReluE5m2x2F32Op, CvtRzBf16x2F32Op,
-    CvtRzF16x2F32Op, Dp2aS32Op, Dp2aU32Op, Dp4aS32Op, Dp4aU32Op, DsmemReadU32Op, ElectSyncOp,
-    ExtendedMinMaxFormatAttr, ExtendedMinMaxNanAttr, ExtendedMinMaxOp, ExtendedMinMaxOperationAttr,
-    ExtendedMinMaxSubnormalAttr, ExtendedMinMaxXorSignAbsAttr, FenceMbarrierInitReleaseClusterOp,
-    FenceProxyAsyncGenericAcquireSharedClusterClusterOp,
-    FenceProxyAsyncGenericReleaseSharedCtaClusterOp, FenceProxyAsyncSharedCtaOp, FmaBf16x2Op,
-    FmaF16x2Op, FmaF32x2Op, FmaFtzF16x2Op, FmaFtzF32x2Op, FmaFtzReluF16x2Op, FmaFtzSatF16x2Op,
-    FmaReluBf16x2Op, FmaReluF16x2Op, FmaSatF16x2Op, GridDependencyLaunchDependentsOp,
-    GridDependencyWaitOp, LdmatrixElementAttr, LdmatrixLayoutAttr, LdmatrixMultiplicityAttr,
-    LdmatrixOp, LdmatrixShapeAttr, LdmatrixStateSpaceAttr, MapaSharedClusterOp, MatchAllSyncI32Op,
-    MatchAllSyncI64Op, MatchAnySyncI32Op, MatchAnySyncI64Op, MaxBf16x2Op, MaxF16x2Op,
-    MaxReluS16x2Op, MaxReluS32Op, MaxS16x2Op, MaxU16x2Op, MbarrierArriveClusterOp,
-    MbarrierArriveExpectTxClusterOp, MbarrierArriveExpectTxSharedOp, MbarrierArriveSharedOp,
-    MbarrierInitSharedOp, MbarrierInvalSharedOp, MbarrierTestWaitSharedOp,
-    MbarrierTryWaitParityClusterOp, MbarrierTryWaitParitySharedOp, MbarrierTryWaitSharedOp,
-    MinBf16x2Op, MinF16x2Op, MinReluS16x2Op, MinReluS32Op, MinS16x2Op, MinU16x2Op,
-    MovmatrixTransB16Op, MulBf16x2Op, MulF16x2Op, MulF32x2Op, MulFtzF32x2Op, NanosleepOp,
-    NegBf16x2Op, NegF16x2Op, PackedAtomicAddOp, PackedAtomicFormatAttr, PmEventOp, PrmtModeAttr,
-    PrmtOp, ReadPtxSregClock64Op, ReadPtxSregClockOp, ReadPtxSregClusterCtaidXOp,
-    ReadPtxSregClusterCtaidYOp, ReadPtxSregClusterCtaidZOp, ReadPtxSregClusterCtarankOp,
-    ReadPtxSregClusterIdXOp, ReadPtxSregClusterIdYOp, ReadPtxSregClusterIdZOp,
-    ReadPtxSregClusterNctaidXOp, ReadPtxSregClusterNctaidYOp, ReadPtxSregClusterNctaidZOp,
-    ReadPtxSregClusterNctarankOp, ReadPtxSregCtaidXOp, ReadPtxSregCtaidYOp, ReadPtxSregCtaidZOp,
-    ReadPtxSregDynamicSmemSizeOp, ReadPtxSregEnvReg1Op, ReadPtxSregEnvReg2Op,
-    ReadPtxSregGlobaltimerOp, ReadPtxSregGridIdOp, ReadPtxSregLaneIdOp, ReadPtxSregLanemaskEqOp,
-    ReadPtxSregLanemaskGeOp, ReadPtxSregLanemaskGtOp, ReadPtxSregLanemaskLeOp,
-    ReadPtxSregLanemaskLtOp, ReadPtxSregNclusterIdXOp, ReadPtxSregNclusterIdYOp,
-    ReadPtxSregNclusterIdZOp, ReadPtxSregNctaidXOp, ReadPtxSregNctaidYOp, ReadPtxSregNctaidZOp,
-    ReadPtxSregNsmIdOp, ReadPtxSregNtidXOp, ReadPtxSregNtidYOp, ReadPtxSregNtidZOp,
-    ReadPtxSregNwarpIdOp, ReadPtxSregSmIdOp, ReadPtxSregTidXOp, ReadPtxSregTidYOp,
-    ReadPtxSregTidZOp, ReadPtxSregTotalSmemSizeOp, ReadPtxSregWarpIdOp, ReduxSyncAddOp,
-    ReduxSyncAndOp, ReduxSyncFmaxAbsNanOp, ReduxSyncFmaxAbsOp, ReduxSyncFmaxNanOp, ReduxSyncFmaxOp,
-    ReduxSyncFminAbsNanOp, ReduxSyncFminAbsOp, ReduxSyncFminNanOp, ReduxSyncFminOp, ReduxSyncMaxOp,
-    ReduxSyncMinOp, ReduxSyncOrOp, ReduxSyncUmaxOp, ReduxSyncUminOp, ReduxSyncXorOp,
-    RegisterMmaAccumulatorAttr, RegisterMmaElementAttr, RegisterMmaKindAttr, RegisterMmaLayoutAttr,
-    RegisterMmaOp, RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr,
-    ScalarArithmeticFormatAttr, ScalarArithmeticOp, ScalarArithmeticOperationAttr,
-    ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr,
-    ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr,
-    ScalarMathFormatAttr, ScalarMathOp, ScalarMathOperationAttr, ScalarMathPrecisionAttr,
-    ScalarMathSubnormalAttr, SetMaxNRegDecOp, SetMaxNRegIncOp, ShflSyncBflyF32Op,
-    ShflSyncBflyI32Op, ShflSyncBflyI64Op, ShflSyncDownF32Op, ShflSyncDownI32Op, ShflSyncDownI64Op,
-    ShflSyncIdxF32Op, ShflSyncIdxI32Op, ShflSyncIdxI64Op, ShflSyncUpF32Op, ShflSyncUpI32Op,
-    ShflSyncUpI64Op, SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr,
-    SparseMmaMetadataAttr, SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr,
-    SparseMmaShapeAttr, StmatrixM8n8X2Op, StmatrixM8n8X2TransOp, StmatrixM8n8X4Op,
-    StmatrixM8n8X4TransOp, SubBf16x2Op, SubF16x2Op, SubF32x2Op, SubFtzF32x2Op, Tcgen05AllocCg2Op,
-    Tcgen05AllocOp, Tcgen05CommitCg2Op, Tcgen05CommitMulticastCg2Op, Tcgen05CommitMulticastOp,
-    Tcgen05CommitOp, Tcgen05CommitSharedClusterCg2Op, Tcgen05CommitSharedClusterOp,
-    Tcgen05Cp4x256bB4x16P64Cg2Op, Tcgen05Cp4x256bB4x16P64Op, Tcgen05Cp4x256bB6x16P32Cg2Op,
-    Tcgen05Cp4x256bB6x16P32Op, Tcgen05Cp4x256bCg2Op, Tcgen05Cp4x256bOp,
-    Tcgen05Cp32x128bWarpx4B4x16P64Cg2Op, Tcgen05Cp32x128bWarpx4B4x16P64Op,
-    Tcgen05Cp32x128bWarpx4B6x16P32Cg2Op, Tcgen05Cp32x128bWarpx4B6x16P32Op,
-    Tcgen05Cp32x128bWarpx4Cg2Op, Tcgen05Cp32x128bWarpx4Op,
-    Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Op,
-    Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Op,
-    Tcgen05Cp64x128bWarpx2Pair0123Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123Op,
-    Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Op,
-    Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Op,
-    Tcgen05Cp64x128bWarpx2Pair0213Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213Op,
-    Tcgen05Cp128x128bB4x16P64Cg2Op, Tcgen05Cp128x128bB4x16P64Op, Tcgen05Cp128x128bB6x16P32Cg2Op,
-    Tcgen05Cp128x128bB6x16P32Op, Tcgen05Cp128x128bCg2Op, Tcgen05Cp128x128bOp,
-    Tcgen05Cp128x256bB4x16P64Cg2Op, Tcgen05Cp128x256bB4x16P64Op, Tcgen05Cp128x256bB6x16P32Cg2Op,
-    Tcgen05Cp128x256bB6x16P32Op, Tcgen05CpSmemToTmemCg2Op, Tcgen05CpSmemToTmemOp,
-    Tcgen05DeallocCg2Op, Tcgen05DeallocOp, Tcgen05FenceAfterThreadSyncOp,
-    Tcgen05FenceBeforeThreadSyncOp, Tcgen05Ld16x32bx2X1Pack16Op, Tcgen05Ld16x32bx2X1RawOp,
-    Tcgen05Ld16x32bx2X2Pack16Op, Tcgen05Ld16x32bx2X2RawOp, Tcgen05Ld16x32bx2X4Pack16Op,
-    Tcgen05Ld16x32bx2X4RawOp, Tcgen05Ld16x32bx2X8Pack16Op, Tcgen05Ld16x32bx2X8RawOp,
-    Tcgen05Ld16x32bx2X16Pack16Op, Tcgen05Ld16x32bx2X16RawOp, Tcgen05Ld16x32bx2X32Pack16Op,
-    Tcgen05Ld16x32bx2X32RawOp, Tcgen05Ld16x32bx2X64Pack16Op, Tcgen05Ld16x32bx2X64RawOp,
-    Tcgen05Ld16x32bx2X128Pack16Op, Tcgen05Ld16x32bx2X128RawOp, Tcgen05Ld16x64bX1Pack16Op,
-    Tcgen05Ld16x64bX1RawOp, Tcgen05Ld16x64bX2Pack16Op, Tcgen05Ld16x64bX2RawOp,
-    Tcgen05Ld16x64bX4Pack16Op, Tcgen05Ld16x64bX4RawOp, Tcgen05Ld16x64bX8Pack16Op,
-    Tcgen05Ld16x64bX8RawOp, Tcgen05Ld16x64bX16Pack16Op, Tcgen05Ld16x64bX16RawOp,
-    Tcgen05Ld16x64bX32Pack16Op, Tcgen05Ld16x64bX32RawOp, Tcgen05Ld16x64bX64Pack16Op,
-    Tcgen05Ld16x64bX64RawOp, Tcgen05Ld16x64bX128Pack16Op, Tcgen05Ld16x64bX128RawOp,
-    Tcgen05Ld16x128bX1Pack16Op, Tcgen05Ld16x128bX1RawOp, Tcgen05Ld16x128bX2Pack16Op,
-    Tcgen05Ld16x128bX2RawOp, Tcgen05Ld16x128bX4Pack16Op, Tcgen05Ld16x128bX4RawOp,
-    Tcgen05Ld16x128bX8Pack16Op, Tcgen05Ld16x128bX8RawOp, Tcgen05Ld16x128bX16Pack16Op,
-    Tcgen05Ld16x128bX16RawOp, Tcgen05Ld16x128bX32Pack16Op, Tcgen05Ld16x128bX32RawOp,
-    Tcgen05Ld16x128bX64Pack16Op, Tcgen05Ld16x128bX64RawOp, Tcgen05Ld16x256bPureOp,
-    Tcgen05Ld16x256bX1Pack16Op, Tcgen05Ld16x256bX1RawOp, Tcgen05Ld16x256bX2Pack16Op,
-    Tcgen05Ld16x256bX2RawOp, Tcgen05Ld16x256bX4Pack16Op, Tcgen05Ld16x256bX4RawOp,
-    Tcgen05Ld16x256bX8Pack16Op, Tcgen05Ld16x256bX8PureOp, Tcgen05Ld16x256bX8RawOp,
-    Tcgen05Ld16x256bX16Pack16Op, Tcgen05Ld16x256bX16RawOp, Tcgen05Ld16x256bX32Pack16Op,
-    Tcgen05Ld16x256bX32RawOp, Tcgen05Ld32x32bX1Pack16Op, Tcgen05Ld32x32bX1RawOp,
-    Tcgen05Ld32x32bX2Pack16Op, Tcgen05Ld32x32bX2RawOp, Tcgen05Ld32x32bX4Pack16Op,
-    Tcgen05Ld32x32bX4RawOp, Tcgen05Ld32x32bX8Pack16Op, Tcgen05Ld32x32bX8RawOp,
-    Tcgen05Ld32x32bX16Pack16Op, Tcgen05Ld32x32bX16RawOp, Tcgen05Ld32x32bX32Pack16Op,
-    Tcgen05Ld32x32bX32RawOp, Tcgen05Ld32x32bX64Pack16Op, Tcgen05Ld32x32bX64RawOp,
-    Tcgen05Ld32x32bX128Pack16Op, Tcgen05Ld32x32bX128RawOp, Tcgen05LoadWaitOp,
-    Tcgen05MmaBBufferAttr, Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr,
-    Tcgen05MmaF16Cg2Op, Tcgen05MmaF16Op, Tcgen05MmaFormAttr, Tcgen05MmaKindAttr, Tcgen05MmaOp,
-    Tcgen05MmaWsBf16Op, Tcgen05MmaWsF16Op, Tcgen05MmaWsTf32Op, Tcgen05RelinquishAllocPermitCg2Op,
-    Tcgen05RelinquishAllocPermitOp, Tcgen05ShiftDownCg2Op, Tcgen05ShiftDownOp,
-    Tcgen05St16x32bx2X1RawOp, Tcgen05St16x32bx2X1Unpack16Op, Tcgen05St16x32bx2X2RawOp,
-    Tcgen05St16x32bx2X2Unpack16Op, Tcgen05St16x32bx2X4RawOp, Tcgen05St16x32bx2X4Unpack16Op,
-    Tcgen05St16x32bx2X8RawOp, Tcgen05St16x32bx2X8Unpack16Op, Tcgen05St16x32bx2X16RawOp,
-    Tcgen05St16x32bx2X16Unpack16Op, Tcgen05St16x32bx2X32RawOp, Tcgen05St16x32bx2X32Unpack16Op,
-    Tcgen05St16x32bx2X64RawOp, Tcgen05St16x32bx2X64Unpack16Op, Tcgen05St16x32bx2X128RawOp,
-    Tcgen05St16x32bx2X128Unpack16Op, Tcgen05St16x64bX1RawOp, Tcgen05St16x64bX1Unpack16Op,
-    Tcgen05St16x64bX2RawOp, Tcgen05St16x64bX2Unpack16Op, Tcgen05St16x64bX4RawOp,
-    Tcgen05St16x64bX4Unpack16Op, Tcgen05St16x64bX8RawOp, Tcgen05St16x64bX8Unpack16Op,
-    Tcgen05St16x64bX16RawOp, Tcgen05St16x64bX16Unpack16Op, Tcgen05St16x64bX32RawOp,
-    Tcgen05St16x64bX32Unpack16Op, Tcgen05St16x64bX64RawOp, Tcgen05St16x64bX64Unpack16Op,
-    Tcgen05St16x64bX128RawOp, Tcgen05St16x64bX128Unpack16Op, Tcgen05St16x128bX1RawOp,
-    Tcgen05St16x128bX1Unpack16Op, Tcgen05St16x128bX2RawOp, Tcgen05St16x128bX2Unpack16Op,
-    Tcgen05St16x128bX4RawOp, Tcgen05St16x128bX4Unpack16Op, Tcgen05St16x128bX8RawOp,
-    Tcgen05St16x128bX8Unpack16Op, Tcgen05St16x128bX16RawOp, Tcgen05St16x128bX16Unpack16Op,
-    Tcgen05St16x128bX32RawOp, Tcgen05St16x128bX32Unpack16Op, Tcgen05St16x128bX64RawOp,
-    Tcgen05St16x128bX64Unpack16Op, Tcgen05St16x256bX1RawOp, Tcgen05St16x256bX1Unpack16Op,
-    Tcgen05St16x256bX2RawOp, Tcgen05St16x256bX2Unpack16Op, Tcgen05St16x256bX4RawOp,
-    Tcgen05St16x256bX4Unpack16Op, Tcgen05St16x256bX8RawOp, Tcgen05St16x256bX8Unpack16Op,
-    Tcgen05St16x256bX16RawOp, Tcgen05St16x256bX16Unpack16Op, Tcgen05St16x256bX32RawOp,
-    Tcgen05St16x256bX32Unpack16Op, Tcgen05St32x32bX1RawOp, Tcgen05St32x32bX1Unpack16Op,
-    Tcgen05St32x32bX2RawOp, Tcgen05St32x32bX2Unpack16Op, Tcgen05St32x32bX4RawOp,
-    Tcgen05St32x32bX4Unpack16Op, Tcgen05St32x32bX8RawOp, Tcgen05St32x32bX8Unpack16Op,
-    Tcgen05St32x32bX16RawOp, Tcgen05St32x32bX16Unpack16Op, Tcgen05St32x32bX32RawOp,
-    Tcgen05St32x32bX32Unpack16Op, Tcgen05St32x32bX64RawOp, Tcgen05St32x32bX64Unpack16Op,
-    Tcgen05St32x32bX128RawOp, Tcgen05St32x32bX128Unpack16Op, Tcgen05StoreWaitOp,
-    ThreadfenceBlockOp, ThreadfenceOp, ThreadfenceSystemOp, TrapOp, VoteSyncAllOp, VoteSyncAnyOp,
-    VoteSyncBallotOp, VoteSyncUniOp, WgmmaCommitGroupSyncAlignedOp, WgmmaFenceSyncAlignedOp,
-    WgmmaWaitGroupSyncAlignedOp,
-};
-use pliron::basic_block::BasicBlock;
-use pliron::context::{Context, Ptr};
-use pliron::input_err;
-use pliron::location::{Located, Location};
-use pliron::op::Op;
-use pliron::operation::Operation;
-use rustc_public::{CrateDef, mir, ty::FnDef};
-
-use dialect_mir::ops::{MirConstantOp, MirUnreachableOp};
-
-use dialect_mir::{
-    attributes::FieldIndexAttr,
-    ops::{MirConstructArrayOp, MirConstructStructOp, MirExtractFieldOp},
-    types::{MirArrayType, MirStructType},
-};
-use pliron::{
-    builtin::types::{FP32Type, FP64Type, IntegerType, Signedness},
-    r#type::{TypeHandle, Typed},
-    value::Value,
-};
-
-use dialect_mir::{ops::MirConstructTupleOp, types::MirTupleType};
-
-pub const GENERATED_INTRINSIC_ABI: u32 = 1;
-pub const GENERATED_INTRINSIC_ABI_NAMESPACE: &str = "__cuda_oxide_intrinsic_abi_v1";
-
-#[derive(Debug, Clone, PartialEq, Eq)]
-pub enum RawIntrinsicIdentity {
-    NotRawCrate,
-    Known(String),
-    UnsupportedAbi(String),
-    UnknownId(String),
-}
-
-/// Classify the unrewritten raw intrinsic DefPath. rustc's ordinary name
-/// printer may prefer a public re-export path, which is source API rather than ABI.
-pub fn classify_raw_intrinsic(fn_def: FnDef) -> RawIntrinsicIdentity {
-    let crate_name = fn_def.krate().name.to_string();
-    if !matches!(crate_name.as_str(), "cuda_intrinsics" | "cuda-intrinsics") {
-        return RawIntrinsicIdentity::NotRawCrate;
-    }
-
-    let mut segments = Vec::new();
-    let mut current = Some(fn_def.def_id());
-    while let Some(def_id) = current {
-        let printed = def_id.name();
-        let segment = printed.as_str().rsplit("::").next().unwrap_or_default();
-        if segment != crate_name {
-            segments.push(segment.to_owned());
-        }
-        current = def_id.parent();
-    }
-    segments.reverse();
-    classify_raw_intrinsic_path(
-        &crate_name,
-        format!("{crate_name}::{}", segments.join("::")),
-    )
-}
-
-fn classify_raw_intrinsic_path(crate_name: &str, path: String) -> RawIntrinsicIdentity {
-    if !matches!(crate_name, "cuda_intrinsics" | "cuda-intrinsics") {
-        return RawIntrinsicIdentity::NotRawCrate;
-    }
-    if is_raw_generated_intrinsic_path(&path) {
-        return RawIntrinsicIdentity::Known(path);
-    }
-    let namespace = path.split("::").nth(1).unwrap_or_default();
-    if namespace.starts_with("__cuda_oxide_intrinsic_abi_v")
-        && namespace != GENERATED_INTRINSIC_ABI_NAMESPACE
-    {
-        RawIntrinsicIdentity::UnsupportedAbi(path)
-    } else {
-        RawIntrinsicIdentity::UnknownId(path)
-    }
-}
-
-pub fn require_supported_raw_intrinsic(
-    fn_def: FnDef,
-    loc: &Location,
-) -> TranslationResult<Option<String>> {
-    match classify_raw_intrinsic(fn_def) {
-        RawIntrinsicIdentity::NotRawCrate => Ok(None),
-        RawIntrinsicIdentity::Known(path) => Ok(Some(path)),
-        RawIntrinsicIdentity::UnsupportedAbi(path) => input_err!(
-            loc.clone(),
-            TranslationErr::unsupported(format!(
-                "cuda-intrinsics ABI mismatch: `{path}` uses an unsupported intrinsic ABI; this compiler supports ABI v{GENERATED_INTRINSIC_ABI}"
-            ))
-        ),
-        RawIntrinsicIdentity::UnknownId(path) => input_err!(
-            loc.clone(),
-            TranslationErr::unsupported(format!(
-                "cuda-intrinsics ABI mismatch: `{path}` is not a known intrinsic ID in ABI v{GENERATED_INTRINSIC_ABI}"
-            ))
-        ),
-    }
-}
-
-pub fn is_generated_intrinsic_path(name: &str) -> bool {
-    matches!(
-        name,
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
-            | "cuda_device::bf16x2::abs_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
-            | "cuda_device::f16x2::abs_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
-            | "cuda_device::warp::active_mask"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
-            | "cuda_device::bf16x2::add_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
-            | "cuda_device::f16x2::add_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
-            | "cuda_device::f32x2::add_f32x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
-            | "cuda_device::f32x2::add_ftz_f32x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
-            | "cuda_device::float::add_rm_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
-            | "cuda_device::float::add_rm_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
-            | "cuda_device::float::add_rm_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
-            | "cuda_device::float::add_rm_ftz_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
-            | "cuda_device::float::add_rm_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
-            | "cuda_device::float::add_rn_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
-            | "cuda_device::float::add_rn_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
-            | "cuda_device::float::add_rn_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
-            | "cuda_device::float::add_rn_ftz_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
-            | "cuda_device::float::add_rn_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
-            | "cuda_device::float::add_rp_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
-            | "cuda_device::float::add_rp_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
-            | "cuda_device::float::add_rp_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
-            | "cuda_device::float::add_rp_ftz_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
-            | "cuda_device::float::add_rp_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
-            | "cuda_device::float::add_rz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
-            | "cuda_device::float::add_rz_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
-            | "cuda_device::float::add_rz_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
-            | "cuda_device::float::add_rz_ftz_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
-            | "cuda_device::float::add_rz_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040"
-            | "cuda_device::warp::all_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041"
-            | "cuda_device::warp::any_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
-            | "cuda_device::warp::ballot_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
-            | "cuda_device::cluster::barrier_cluster_arrive"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
-            | "cuda_device::cluster::barrier_cluster_arrive_aligned"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
-            | "cuda_device::cluster::barrier_cluster_arrive_relaxed"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
-            | "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
-            | "cuda_device::cluster::barrier_cluster_wait"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
-            | "cuda_device::cluster::barrier_cluster_wait_aligned"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
-            | "cuda_device::barrier::barrier_cta_arrive"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
-            | "cuda_device::barrier::barrier_cta_arrive_aligned"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
-            | "cuda_device::barrier::barrier_cta_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
-            | "cuda_device::barrier::barrier_cta_sync_aligned"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
-            | "cuda_device::thread::blockDim_x"
-            | "cuda_device::blockDim_x"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
-            | "cuda_device::thread::blockDim_y"
-            | "cuda_device::blockDim_y"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
-            | "cuda_device::thread::blockDim_z"
-            | "cuda_device::blockDim_z"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
-            | "cuda_device::thread::blockIdx_x"
-            | "cuda_device::blockIdx_x"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
-            | "cuda_device::thread::blockIdx_y"
-            | "cuda_device::blockIdx_y"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
-            | "cuda_device::thread::blockIdx_z"
-            | "cuda_device::blockIdx_z"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
-            | "cuda_device::debug::breakpoint"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
-            | "cuda_device::clc::clc_query_get_first_ctaid_x"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
-            | "cuda_device::clc::clc_query_get_first_ctaid_y"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
-            | "cuda_device::clc::clc_query_get_first_ctaid_z"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
-            | "cuda_device::clc::clc_query_is_canceled"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
-            | "cuda_device::clc::clc_try_cancel"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
-            | "cuda_device::clc::clc_try_cancel_multicast"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283"
-            | "cuda_device::debug::clock"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284"
-            | "cuda_device::debug::clock64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
-            | "cuda_device::cluster::cluster_ctaidX"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
-            | "cuda_device::cluster::cluster_ctaidY"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
-            | "cuda_device::cluster::cluster_ctaidZ"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
-            | "cuda_device::cluster::cluster_nctaidX"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
-            | "cuda_device::cluster::cluster_nctaidY"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
-            | "cuda_device::cluster::cluster_nctaidZ"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
-            | "cuda_device::cluster::__cluster_grid_dimX"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
-            | "cuda_device::cluster::__cluster_grid_dimY"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
-            | "cuda_device::cluster::__cluster_grid_dimZ"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
-            | "cuda_device::cluster::__cluster_idxX"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
-            | "cuda_device::cluster::__cluster_idxY"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
-            | "cuda_device::cluster::__cluster_idxZ"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
-            | "cuda_device::float::cos_approx_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
-            | "cuda_device::float::cos_approx_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
-            | "cuda_device::tma::cp_async_bulk_commit_group"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
-            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
-            | "cuda_device::tma::cp_async_bulk_tensor_1d_g2s"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
-            | "cuda_device::tma::cp_async_bulk_tensor_1d_s2g"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
-            | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
-            | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
-            | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
-            | "cuda_device::tma::cp_async_bulk_tensor_2d_s2g"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
-            | "cuda_device::tma::cp_async_bulk_tensor_3d_g2s"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
-            | "cuda_device::tma::cp_async_bulk_tensor_3d_s2g"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
-            | "cuda_device::tma::cp_async_bulk_tensor_4d_g2s"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
-            | "cuda_device::tma::cp_async_bulk_tensor_4d_s2g"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
-            | "cuda_device::tma::cp_async_bulk_tensor_5d_g2s"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
-            | "cuda_device::tma::cp_async_bulk_tensor_5d_s2g"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
-            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
-            | "cuda_device::tma::cp_async_bulk_wait_group"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
-            | "cuda_device::tma::cp_async_bulk_wait_group_read"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
-            | "cuda_device::async_copy::cp_async_ca_16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
-            | "cuda_device::async_copy::cp_async_ca_4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
-            | "cuda_device::async_copy::cp_async_ca_8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
-            | "cuda_device::async_copy::cp_async_ca_zfill_16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
-            | "cuda_device::async_copy::cp_async_ca_zfill_4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
-            | "cuda_device::async_copy::cp_async_ca_zfill_8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
-            | "cuda_device::async_copy::cp_async_cg_16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
-            | "cuda_device::async_copy::cp_async_cg_zfill_16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
-            | "cuda_device::async_copy::cp_async_commit_group"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
-            | "cuda_device::async_copy::cp_async_mbarrier_arrive"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
-            | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
-            | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
-            | "cuda_device::async_copy::cp_async_mbarrier_arrive_shared"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
-            | "cuda_device::async_copy::cp_async_wait_all"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
-            | "cuda_device::async_copy::cp_async_wait_group"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
-            | "cuda_device::convert::cvt_f16x2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
-            | "cuda_device::convert::cvt_bf16x2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
-            | "cuda_device::convert::cvt_rn_f16x2_e4m3x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
-            | "cuda_device::convert::cvt_rn_f16x2_e5m2x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
-            | "cuda_device::convert::cvt_rn_relu_bf16x2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
-            | "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
-            | "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
-            | "cuda_device::convert::cvt_rn_relu_f16x2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
-            | "cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
-            | "cuda_device::convert::cvt_rn_relu_tf32_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
-            | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
-            | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
-            | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
-            | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
-            | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
-            | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
-            | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
-            | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
-            | "cuda_device::convert::cvt_rn_satfinite_tf32_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
-            | "cuda_device::convert::cvt_rn_tf32_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
-            | "cuda_device::convert::cvt_rna_satfinite_tf32_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
-            | "cuda_device::convert::cvt_rna_tf32_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
-            | "cuda_device::convert::cvt_rz_bf16x2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
-            | "cuda_device::convert::cvt_rz_f16x2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
-            | "cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
-            | "cuda_device::convert::cvt_rz_relu_tf32_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
-            | "cuda_device::convert::cvt_rz_satfinite_tf32_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
-            | "cuda_device::convert::cvt_rz_tf32_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
-            | "cuda_device::float::div_rm_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
-            | "cuda_device::float::div_rm_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
-            | "cuda_device::float::div_rm_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
-            | "cuda_device::float::div_rn_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
-            | "cuda_device::float::div_rn_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
-            | "cuda_device::float::div_rn_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
-            | "cuda_device::float::div_rp_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
-            | "cuda_device::float::div_rp_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
-            | "cuda_device::float::div_rp_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
-            | "cuda_device::float::div_rz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
-            | "cuda_device::float::div_rz_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
-            | "cuda_device::float::div_rz_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
-            | "cuda_device::dotprod::dp2a_s32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
-            | "cuda_device::dotprod::dp2a_u32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
-            | "cuda_device::dotprod::dp4a_s32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
-            | "cuda_device::dotprod::dp4a_u32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
-            | "cuda_device::cluster::dsmem_read_u32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
-            | "cuda_device::shared::dynamic_smem_size"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
-            | "cuda_device::warp::elect_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286"
-            | "cuda_device::grid::envreg1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287"
-            | "cuda_device::grid::envreg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
-            | "cuda_device::float::ex2_approx_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
-            | "cuda_device::float::ex2_approx_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
-            | "cuda_device::float::ex2_approx_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
-            | "cuda_device::barrier::fence_mbarrier_init_release_cluster"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
-            | "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
-            | "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
-            | "cuda_device::barrier::fence_proxy_async_shared_cta"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
-            | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
-            | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
-            | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
-            | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
-            | "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
-            | "cuda_device::tma::fence_proxy_tensormap_generic_release_cta"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
-            | "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
-            | "cuda_device::tma::fence_proxy_tensormap_generic_release_system"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
-            | "cuda_device::bf16x2::fma_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
-            | "cuda_device::f16x2::fma_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
-            | "cuda_device::f32x2::fma_f32x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
-            | "cuda_device::f16x2::fma_ftz_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
-            | "cuda_device::f32x2::fma_ftz_f32x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
-            | "cuda_device::f16x2::fma_ftz_relu_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
-            | "cuda_device::f16x2::fma_ftz_sat_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
-            | "cuda_device::bf16x2::fma_relu_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
-            | "cuda_device::f16x2::fma_relu_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
-            | "cuda_device::float::fma_rm_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
-            | "cuda_device::float::fma_rm_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
-            | "cuda_device::float::fma_rm_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
-            | "cuda_device::float::fma_rm_ftz_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
-            | "cuda_device::float::fma_rm_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
-            | "cuda_device::float::fma_rn_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
-            | "cuda_device::float::fma_rn_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
-            | "cuda_device::float::fma_rn_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
-            | "cuda_device::float::fma_rn_ftz_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
-            | "cuda_device::float::fma_rn_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
-            | "cuda_device::float::fma_rp_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
-            | "cuda_device::float::fma_rp_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
-            | "cuda_device::float::fma_rp_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
-            | "cuda_device::float::fma_rp_ftz_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
-            | "cuda_device::float::fma_rp_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
-            | "cuda_device::float::fma_rz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
-            | "cuda_device::float::fma_rz_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
-            | "cuda_device::float::fma_rz_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
-            | "cuda_device::float::fma_rz_ftz_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
-            | "cuda_device::float::fma_rz_sat_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
-            | "cuda_device::f16x2::fma_sat_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
-            | "cuda_device::debug::globaltimer"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
-            | "cuda_device::grid::dependency::trigger_dependents"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
-            | "cuda_device::grid::dependency::wait"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
-            | "cuda_device::thread::gridDim_x"
-            | "cuda_device::gridDim_x"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
-            | "cuda_device::thread::gridDim_y"
-            | "cuda_device::gridDim_y"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
-            | "cuda_device::thread::gridDim_z"
-            | "cuda_device::gridDim_z"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
-            | "cuda_device::thread::gridid"
-            | "cuda_device::gridid"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016"
-            | "cuda_device::warp::lane_id"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
-            | "cuda_device::warp::lanemask_eq"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
-            | "cuda_device::warp::lanemask_ge"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
-            | "cuda_device::warp::lanemask_gt"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
-            | "cuda_device::warp::lanemask_le"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
-            | "cuda_device::warp::lanemask_lt"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
-            | "cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
-            | "cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
-            | "cuda_device::wmma::ldmatrix_x1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
-            | "cuda_device::wmma::ldmatrix_x1_trans"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
-            | "cuda_device::wmma::ldmatrix_x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
-            | "cuda_device::wmma::ldmatrix_x2_trans"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
-            | "cuda_device::wmma::ldmatrix_x4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
-            | "cuda_device::wmma::ldmatrix_x4_trans"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
-            | "cuda_device::float::lg2_approx_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
-            | "cuda_device::float::lg2_approx_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
-            | "cuda_device::cluster::map_shared_rank"
-            | "cuda_device::cluster::map_shared_rank_mut"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
-            | "cuda_device::warp::match_all_i64_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
-            | "cuda_device::warp::match_all_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
-            | "cuda_device::warp::match_any_i64_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
-            | "cuda_device::warp::match_any_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850"
-            | "cuda_device::bf16::max_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
-            | "cuda_device::bf16x2::max_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842"
-            | "cuda_device::f16::max_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
-            | "cuda_device::f16x2::max_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
-            | "cuda_device::f16::max_ftz_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
-            | "cuda_device::f16x2::max_ftz_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
-            | "cuda_device::f16::max_ftz_nan_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
-            | "cuda_device::f16x2::max_ftz_nan_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
-            | "cuda_device::f16::max_ftz_nan_xorsign_abs_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
-            | "cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
-            | "cuda_device::float::max_ftz_nan_xorsign_abs_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
-            | "cuda_device::f16::max_ftz_xorsign_abs_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
-            | "cuda_device::f16x2::max_ftz_xorsign_abs_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
-            | "cuda_device::float::max_ftz_xorsign_abs_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
-            | "cuda_device::bf16::max_nan_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
-            | "cuda_device::bf16x2::max_nan_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
-            | "cuda_device::f16::max_nan_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
-            | "cuda_device::f16x2::max_nan_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
-            | "cuda_device::bf16::max_nan_xorsign_abs_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
-            | "cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
-            | "cuda_device::f16::max_nan_xorsign_abs_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
-            | "cuda_device::f16x2::max_nan_xorsign_abs_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
-            | "cuda_device::float::max_nan_xorsign_abs_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
-            | "cuda_device::i16x2::max_relu_s16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
-            | "cuda_device::int::max_relu_s32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
-            | "cuda_device::i16x2::max_s16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
-            | "cuda_device::i16x2::max_u16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
-            | "cuda_device::bf16::max_xorsign_abs_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
-            | "cuda_device::bf16x2::max_xorsign_abs_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
-            | "cuda_device::f16::max_xorsign_abs_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
-            | "cuda_device::f16x2::max_xorsign_abs_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
-            | "cuda_device::float::max_xorsign_abs_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
-            | "cuda_device::barrier::mbarrier_arrive"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
-            | "cuda_device::barrier::mbarrier_arrive_cluster"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
-            | "cuda_device::barrier::mbarrier_arrive_expect_tx"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
-            | "cuda_device::barrier::mbarrier_arrive_expect_tx_cluster"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
-            | "cuda_device::barrier::mbarrier_init"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
-            | "cuda_device::barrier::mbarrier_inval"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
-            | "cuda_device::barrier::mbarrier_test_wait"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
-            | "cuda_device::barrier::mbarrier_try_wait"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
-            | "cuda_device::barrier::mbarrier_try_wait_parity"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
-            | "cuda_device::barrier::mbarrier_try_wait_parity_cluster"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838"
-            | "cuda_device::bf16::min_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
-            | "cuda_device::bf16x2::min_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830"
-            | "cuda_device::f16::min_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
-            | "cuda_device::f16x2::min_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
-            | "cuda_device::f16::min_ftz_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
-            | "cuda_device::f16x2::min_ftz_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
-            | "cuda_device::f16::min_ftz_nan_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
-            | "cuda_device::f16x2::min_ftz_nan_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
-            | "cuda_device::f16::min_ftz_nan_xorsign_abs_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
-            | "cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
-            | "cuda_device::float::min_ftz_nan_xorsign_abs_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
-            | "cuda_device::f16::min_ftz_xorsign_abs_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
-            | "cuda_device::f16x2::min_ftz_xorsign_abs_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
-            | "cuda_device::float::min_ftz_xorsign_abs_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
-            | "cuda_device::bf16::min_nan_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
-            | "cuda_device::bf16x2::min_nan_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
-            | "cuda_device::f16::min_nan_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
-            | "cuda_device::f16x2::min_nan_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
-            | "cuda_device::bf16::min_nan_xorsign_abs_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
-            | "cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
-            | "cuda_device::f16::min_nan_xorsign_abs_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
-            | "cuda_device::f16x2::min_nan_xorsign_abs_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
-            | "cuda_device::float::min_nan_xorsign_abs_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
-            | "cuda_device::i16x2::min_relu_s16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
-            | "cuda_device::int::min_relu_s32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
-            | "cuda_device::i16x2::min_s16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
-            | "cuda_device::i16x2::min_u16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
-            | "cuda_device::bf16::min_xorsign_abs_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
-            | "cuda_device::bf16x2::min_xorsign_abs_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
-            | "cuda_device::f16::min_xorsign_abs_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
-            | "cuda_device::f16x2::min_xorsign_abs_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
-            | "cuda_device::float::min_xorsign_abs_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
-            | "cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
-            | "cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
-            | "cuda_device::wmma::mma_m16n8k16_f16_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
-            | "cuda_device::wmma::mma_m16n8k16_f32_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
-            | "cuda_device::wmma::mma_m16n8k16_f32_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
-            | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
-            | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
-            | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
-            | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
-            | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
-            | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
-            | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
-            | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
-            | "cuda_device::wmma::mma_m16n8k16_s32_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
-            | "cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
-            | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
-            | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
-            | "cuda_device::wmma::mma_m16n8k16_s32_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
-            | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
-            | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
-            | "cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
-            | "cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
-            | "cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
-            | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
-            | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
-            | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
-            | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
-            | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
-            | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
-            | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
-            | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
-            | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
-            | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
-            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
-            | "cuda_device::wmma::mma_m16n8k32_s32_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
-            | "cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
-            | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
-            | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
-            | "cuda_device::wmma::mma_m16n8k32_s32_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
-            | "cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
-            | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
-            | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
-            | "cuda_device::wmma::mma_m16n8k32_s32_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
-            | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
-            | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
-            | "cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
-            | "cuda_device::wmma::mma_m16n8k32_s32_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
-            | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
-            | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
-            | "cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
-            | "cuda_device::wmma::mma_m16n8k4_f32_tf32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
-            | "cuda_device::wmma::mma_m16n8k64_s32_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
-            | "cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
-            | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
-            | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
-            | "cuda_device::wmma::mma_m16n8k64_s32_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
-            | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
-            | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
-            | "cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
-            | "cuda_device::wmma::mma_m16n8k8_f16_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
-            | "cuda_device::wmma::mma_m16n8k8_f32_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
-            | "cuda_device::wmma::mma_m16n8k8_f32_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
-            | "cuda_device::wmma::mma_m16n8k8_f32_tf32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
-            | "cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
-            | "cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
-            | "cuda_device::wmma::mma_m8n8k16_s32_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
-            | "cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
-            | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
-            | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
-            | "cuda_device::wmma::mma_m8n8k16_s32_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
-            | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
-            | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
-            | "cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
-            | "cuda_device::wmma::mma_m8n8k32_s32_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
-            | "cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
-            | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
-            | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
-            | "cuda_device::wmma::mma_m8n8k32_s32_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
-            | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
-            | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
-            | "cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
-            | "cuda_device::wmma::mma_m8n8k4_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
-            | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
-            | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
-            | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
-            | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
-            | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
-            | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
-            | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
-            | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
-            | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
-            | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
-            | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
-            | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
-            | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
-            | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
-            | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
-            | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
-            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
-            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
-            | "cuda_device::wmma::movmatrix_trans_b16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
-            | "cuda_device::bf16x2::mul_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
-            | "cuda_device::f16x2::mul_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
-            | "cuda_device::f32x2::mul_f32x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
-            | "cuda_device::f32x2::mul_ftz_f32x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
-            | "cuda_device::float::mul_rm_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
-            | "cuda_device::float::mul_rm_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
-            | "cuda_device::float::mul_rm_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
-            | "cuda_device::float::mul_rn_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
-            | "cuda_device::float::mul_rn_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
-            | "cuda_device::float::mul_rn_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
-            | "cuda_device::float::mul_rp_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
-            | "cuda_device::float::mul_rp_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
-            | "cuda_device::float::mul_rp_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
-            | "cuda_device::float::mul_rz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
-            | "cuda_device::float::mul_rz_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
-            | "cuda_device::float::mul_rz_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
-            | "cuda_device::barrier::nanosleep"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
-            | "cuda_device::bf16x2::neg_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
-            | "cuda_device::f16x2::neg_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
-            | "cuda_device::thread::nsmid"
-            | "cuda_device::nsmid"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292"
-            | "cuda_device::warp::nwarpid"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
-            | "cuda_device::atomic::atom_add_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
-            | "cuda_device::atomic::atom_add_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
-            | "cuda_device::debug::__prof_trigger"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
-            | "cuda_device::tma::prefetch_tma_descriptor"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252"
-            | "cuda_device::prmt::prmt"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254"
-            | "cuda_device::prmt::prmt_b4e"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256"
-            | "cuda_device::prmt::prmt_ecl"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257"
-            | "cuda_device::prmt::prmt_ecr"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253"
-            | "cuda_device::prmt::prmt_f4e"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
-            | "cuda_device::prmt::prmt_rc16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255"
-            | "cuda_device::prmt::prmt_rc8"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
-            | "cuda_device::float::rcp_approx_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
-            | "cuda_device::float::rcp_approx_ftz_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
-            | "cuda_device::float::rcp_rm_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
-            | "cuda_device::float::rcp_rm_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
-            | "cuda_device::float::rcp_rm_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
-            | "cuda_device::float::rcp_rn_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
-            | "cuda_device::float::rcp_rn_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
-            | "cuda_device::float::rcp_rn_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
-            | "cuda_device::float::rcp_rp_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
-            | "cuda_device::float::rcp_rp_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
-            | "cuda_device::float::rcp_rp_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
-            | "cuda_device::float::rcp_rz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
-            | "cuda_device::float::rcp_rz_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
-            | "cuda_device::float::rcp_rz_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
-            | "cuda_device::warp::redux_sync_add"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
-            | "cuda_device::warp::redux_sync_and"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
-            | "cuda_device::warp::redux_sync_max_abs_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
-            | "cuda_device::warp::redux_sync_max_abs_nan_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
-            | "cuda_device::warp::redux_sync_max_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
-            | "cuda_device::warp::redux_sync_max_i32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
-            | "cuda_device::warp::redux_sync_max_nan_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
-            | "cuda_device::warp::redux_sync_max_u32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
-            | "cuda_device::warp::redux_sync_min_abs_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
-            | "cuda_device::warp::redux_sync_min_abs_nan_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
-            | "cuda_device::warp::redux_sync_min_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
-            | "cuda_device::warp::redux_sync_min_i32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
-            | "cuda_device::warp::redux_sync_min_nan_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
-            | "cuda_device::warp::redux_sync_min_u32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
-            | "cuda_device::warp::redux_sync_or"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
-            | "cuda_device::warp::redux_sync_xor"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
-            | "cuda_device::float::rsqrt_approx_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
-            | "cuda_device::float::rsqrt_approx_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
-            | "cuda_device::float::rsqrt_approx_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
-            | "cuda_device::thread::__setmaxnreg_dec"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
-            | "cuda_device::thread::__setmaxnreg_inc"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
-            | "cuda_device::warp::shuffle_down_f32_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
-            | "cuda_device::warp::shuffle_down_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
-            | "cuda_device::warp::shuffle_down_u64_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
-            | "cuda_device::warp::shuffle_f32_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
-            | "cuda_device::warp::shuffle_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
-            | "cuda_device::warp::shuffle_u64_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
-            | "cuda_device::warp::shuffle_up_f32_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
-            | "cuda_device::warp::shuffle_up_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
-            | "cuda_device::warp::shuffle_up_u64_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
-            | "cuda_device::warp::shuffle_xor_f32_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
-            | "cuda_device::warp::shuffle_xor_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
-            | "cuda_device::warp::shuffle_xor_u64_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
-            | "cuda_device::float::sin_approx_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
-            | "cuda_device::float::sin_approx_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
-            | "cuda_device::thread::smid"
-            | "cuda_device::smid"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
-            | "cuda_device::float::sqrt_approx_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
-            | "cuda_device::float::sqrt_approx_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
-            | "cuda_device::float::sqrt_rm_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
-            | "cuda_device::float::sqrt_rm_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
-            | "cuda_device::float::sqrt_rm_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
-            | "cuda_device::float::sqrt_rn_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
-            | "cuda_device::float::sqrt_rn_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
-            | "cuda_device::float::sqrt_rn_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
-            | "cuda_device::float::sqrt_rp_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
-            | "cuda_device::float::sqrt_rp_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
-            | "cuda_device::float::sqrt_rp_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
-            | "cuda_device::float::sqrt_rz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
-            | "cuda_device::float::sqrt_rz_f64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
-            | "cuda_device::float::sqrt_rz_ftz_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
-            | "cuda_device::tcgen05::stmatrix_m8n8_x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
-            | "cuda_device::tcgen05::stmatrix_m8n8_x2_trans"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
-            | "cuda_device::tcgen05::stmatrix_m8n8_x4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
-            | "cuda_device::tcgen05::stmatrix_m8n8_x4_trans"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
-            | "cuda_device::bf16x2::sub_bf16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
-            | "cuda_device::f16x2::sub_f16x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
-            | "cuda_device::f32x2::sub_f32x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
-            | "cuda_device::f32x2::sub_ftz_f32x2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
-            | "cuda_device::warp::sync_mask"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
-            | "cuda_device::thread::sync_threads"
-            | "cuda_device::sync_threads"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
-            | "cuda_device::float::tanh_approx_f32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
-            | "cuda_device::tcgen05::tcgen05_alloc"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
-            | "cuda_device::tcgen05::tcgen05_alloc_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
-            | "cuda_device::tcgen05::tcgen05_commit"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
-            | "cuda_device::tcgen05::tcgen05_commit_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
-            | "cuda_device::tcgen05::tcgen05_commit_multicast"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
-            | "cuda_device::tcgen05::tcgen05_commit_multicast_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
-            | "cuda_device::tcgen05::tcgen05_commit_shared_cluster"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
-            | "cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
-            | "cuda_device::tcgen05::tcgen05_cp_128x128b"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
-            | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
-            | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
-            | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
-            | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
-            | "cuda_device::tcgen05::tcgen05_cp_128x128b_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
-            | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
-            | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
-            | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
-            | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
-            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
-            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
-            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
-            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
-            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
-            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
-            | "cuda_device::tcgen05::tcgen05_cp_4x256b"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
-            | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
-            | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
-            | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
-            | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
-            | "cuda_device::tcgen05::tcgen05_cp_4x256b_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
-            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
-            | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
-            | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
-            | "cuda_device::tcgen05::tcgen05_dealloc"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
-            | "cuda_device::tcgen05::tcgen05_dealloc_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
-            | "cuda_device::tcgen05::tcgen05_fence_after_thread_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
-            | "cuda_device::tcgen05::tcgen05_fence_before_thread_sync"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
-            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_pure"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
-            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
-            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
-            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
-            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
-            | "cuda_device::tcgen05::tcgen05_load_wait"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
-            | "cuda_device::tcgen05::tcgen05_mma_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
-            | "cuda_device::tcgen05::tcgen05_mma_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
-            | "cuda_device::tcgen05::tcgen05_mma_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
-            | "cuda_device::tcgen05::tcgen05_mma_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
-            | "cuda_device::tcgen05::tcgen05_mma_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
-            | "cuda_device::tcgen05::tcgen05_mma_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
-            | "cuda_device::tcgen05::tcgen05_mma_f16_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
-            | "cuda_device::tcgen05::__tcgen05_mma_shared"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
-            | "cuda_device::tcgen05::__tcgen05_mma_sp_shared"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
-            | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
-            | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
-            | "cuda_device::tcgen05::__tcgen05_mma_tensor"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
-            | "cuda_device::tcgen05::__tcgen05_mma_tensor_ashift"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
-            | "cuda_device::tcgen05::tcgen05_mma_ws_bf16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
-            | "cuda_device::tcgen05::tcgen05_mma_ws_e2m1"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
-            | "cuda_device::tcgen05::tcgen05_mma_ws_e2m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
-            | "cuda_device::tcgen05::tcgen05_mma_ws_e3m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
-            | "cuda_device::tcgen05::tcgen05_mma_ws_e4m3"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
-            | "cuda_device::tcgen05::tcgen05_mma_ws_e5m2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
-            | "cuda_device::tcgen05::tcgen05_mma_ws_f16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
-            | "cuda_device::tcgen05::__tcgen05_mma_ws_shared"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
-            | "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
-            | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
-            | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
-            | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
-            | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
-            | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
-            | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
-            | "cuda_device::tcgen05::tcgen05_mma_ws_tf32"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
-            | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
-            | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
-            | "cuda_device::tcgen05::tcgen05_shift_down"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
-            | "cuda_device::tcgen05::tcgen05_shift_down_cg2"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
-            | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
-            | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
-            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
-            | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
-            | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
-            | "cuda_device::tcgen05::tcgen05_store_wait"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
-            | "cuda_device::tma::tensormap_replace_box_dim"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
-            | "cuda_device::tma::tensormap_replace_element_stride"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
-            | "cuda_device::tma::tensormap_replace_element_type"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
-            | "cuda_device::tma::tensormap_replace_fill_mode"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
-            | "cuda_device::tma::tensormap_replace_global_address"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
-            | "cuda_device::tma::tensormap_replace_global_dim"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
-            | "cuda_device::tma::tensormap_replace_global_stride"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
-            | "cuda_device::tma::tensormap_replace_interleave_layout"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
-            | "cuda_device::tma::tensormap_replace_rank"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
-            | "cuda_device::tma::tensormap_replace_swizzle_atomicity"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
-            | "cuda_device::tma::tensormap_replace_swizzle_mode"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
-            | "cuda_device::thread::threadIdx_x"
-            | "cuda_device::threadIdx_x"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
-            | "cuda_device::thread::threadIdx_y"
-            | "cuda_device::threadIdx_y"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
-            | "cuda_device::thread::threadIdx_z"
-            | "cuda_device::threadIdx_z"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
-            | "cuda_device::fence::threadfence"
-            | "cuda_device::threadfence"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
-            | "cuda_device::fence::threadfence_block"
-            | "cuda_device::threadfence_block"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
-            | "cuda_device::fence::threadfence_system"
-            | "cuda_device::threadfence_system"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
-            | "cuda_device::shared::total_smem_size"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295"
-            | "cuda_device::debug::trap"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291"
-            | "cuda_device::warp::warpid"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
-            | "cuda_device::wgmma::wgmma_commit_group"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
-            | "cuda_device::wgmma::wgmma_fence"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
-            | "cuda_device::wgmma::__wgmma_wait_group"
-    )
-}
-
-pub fn is_raw_generated_intrinsic_path(name: &str) -> bool {
-    matches!(
-        name,
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
-            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
-    )
-}
-
-#[cfg(test)]
-pub fn generated_intrinsic_marker(name: &str) -> Option<&'static str> {
-    match name {
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
-        | "cuda_device::bf16x2::abs_bf16x2" => Some("v1:i0070"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
-        | "cuda_device::f16x2::abs_f16x2" => Some("v1:i0080"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
-        | "cuda_device::warp::active_mask" => Some("v1:i0044"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
-        | "cuda_device::bf16x2::add_bf16x2" => Some("v1:i0064"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
-        | "cuda_device::f16x2::add_f16x2" => Some("v1:i0074"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
-        | "cuda_device::f32x2::add_f32x2" => Some("v1:i0995"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
-        | "cuda_device::f32x2::add_ftz_f32x2" => Some("v1:i0996"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
-        | "cuda_device::float::add_rm_f32" => Some("v1:i0446"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
-        | "cuda_device::float::add_rm_f64" => Some("v1:i0436"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
-        | "cuda_device::float::add_rm_ftz_f32" => Some("v1:i0447"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
-        | "cuda_device::float::add_rm_ftz_sat_f32" => Some("v1:i0449"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
-        | "cuda_device::float::add_rm_sat_f32" => Some("v1:i0448"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
-        | "cuda_device::float::add_rn_f32" => Some("v1:i0438"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
-        | "cuda_device::float::add_rn_f64" => Some("v1:i0434"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
-        | "cuda_device::float::add_rn_ftz_f32" => Some("v1:i0439"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
-        | "cuda_device::float::add_rn_ftz_sat_f32" => Some("v1:i0441"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
-        | "cuda_device::float::add_rn_sat_f32" => Some("v1:i0440"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
-        | "cuda_device::float::add_rp_f32" => Some("v1:i0450"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
-        | "cuda_device::float::add_rp_f64" => Some("v1:i0437"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
-        | "cuda_device::float::add_rp_ftz_f32" => Some("v1:i0451"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
-        | "cuda_device::float::add_rp_ftz_sat_f32" => Some("v1:i0453"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
-        | "cuda_device::float::add_rp_sat_f32" => Some("v1:i0452"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
-        | "cuda_device::float::add_rz_f32" => Some("v1:i0442"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
-        | "cuda_device::float::add_rz_f64" => Some("v1:i0435"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
-        | "cuda_device::float::add_rz_ftz_f32" => Some("v1:i0443"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
-        | "cuda_device::float::add_rz_ftz_sat_f32" => Some("v1:i0445"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
-        | "cuda_device::float::add_rz_sat_f32" => Some("v1:i0444"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040" | "cuda_device::warp::all_sync" => {
-            Some("v1:i0040")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041" | "cuda_device::warp::any_sync" => {
-            Some("v1:i0041")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
-        | "cuda_device::warp::ballot_sync" => Some("v1:i0042"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
-        | "cuda_device::cluster::barrier_cluster_arrive" => Some("v1:i0277"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
-        | "cuda_device::cluster::barrier_cluster_arrive_aligned" => Some("v1:i0278"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
-        | "cuda_device::cluster::barrier_cluster_arrive_relaxed" => Some("v1:i0279"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
-        | "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned" => Some("v1:i0280"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
-        | "cuda_device::cluster::barrier_cluster_wait" => Some("v1:i0281"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
-        | "cuda_device::cluster::barrier_cluster_wait_aligned" => Some("v1:i0282"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
-        | "cuda_device::barrier::barrier_cta_arrive" => Some("v1:i0885"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
-        | "cuda_device::barrier::barrier_cta_arrive_aligned" => Some("v1:i0886"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
-        | "cuda_device::barrier::barrier_cta_sync" => Some("v1:i0883"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
-        | "cuda_device::barrier::barrier_cta_sync_aligned" => Some("v1:i0884"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
-        | "cuda_device::thread::blockDim_x"
-        | "cuda_device::blockDim_x" => Some("v1:i0003"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
-        | "cuda_device::thread::blockDim_y"
-        | "cuda_device::blockDim_y" => Some("v1:i0007"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
-        | "cuda_device::thread::blockDim_z"
-        | "cuda_device::blockDim_z" => Some("v1:i0011"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
-        | "cuda_device::thread::blockIdx_x"
-        | "cuda_device::blockIdx_x" => Some("v1:i0002"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
-        | "cuda_device::thread::blockIdx_y"
-        | "cuda_device::blockIdx_y" => Some("v1:i0006"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
-        | "cuda_device::thread::blockIdx_z"
-        | "cuda_device::blockIdx_z" => Some("v1:i0010"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
-        | "cuda_device::debug::breakpoint" => Some("v1:i0296"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
-        | "cuda_device::clc::clc_query_get_first_ctaid_x" => Some("v1:i0325"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
-        | "cuda_device::clc::clc_query_get_first_ctaid_y" => Some("v1:i0326"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
-        | "cuda_device::clc::clc_query_get_first_ctaid_z" => Some("v1:i0327"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
-        | "cuda_device::clc::clc_query_is_canceled" => Some("v1:i0324"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
-        | "cuda_device::clc::clc_try_cancel" => Some("v1:i0322"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
-        | "cuda_device::clc::clc_try_cancel_multicast" => Some("v1:i0323"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283" | "cuda_device::debug::clock" => {
-            Some("v1:i0283")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284" | "cuda_device::debug::clock64" => {
-            Some("v1:i0284")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276" => Some("v1:i0276"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
-        | "cuda_device::cluster::cluster_ctaidX" => Some("v1:i0263"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
-        | "cuda_device::cluster::cluster_ctaidY" => Some("v1:i0264"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
-        | "cuda_device::cluster::cluster_ctaidZ" => Some("v1:i0265"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275" => Some("v1:i0275"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
-        | "cuda_device::cluster::cluster_nctaidX" => Some("v1:i0266"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
-        | "cuda_device::cluster::cluster_nctaidY" => Some("v1:i0267"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
-        | "cuda_device::cluster::cluster_nctaidZ" => Some("v1:i0268"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
-        | "cuda_device::cluster::__cluster_grid_dimX" => Some("v1:i0272"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
-        | "cuda_device::cluster::__cluster_grid_dimY" => Some("v1:i0273"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
-        | "cuda_device::cluster::__cluster_grid_dimZ" => Some("v1:i0274"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
-        | "cuda_device::cluster::__cluster_idxX" => Some("v1:i0269"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
-        | "cuda_device::cluster::__cluster_idxY" => Some("v1:i0270"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
-        | "cuda_device::cluster::__cluster_idxZ" => Some("v1:i0271"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
-        | "cuda_device::float::cos_approx_f32" => Some("v1:i0784"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
-        | "cuda_device::float::cos_approx_ftz_f32" => Some("v1:i0785"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
-        | "cuda_device::tma::cp_async_bulk_commit_group" => Some("v1:i0340"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2" => Some("v1:i0888"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint" => Some("v1:i0917"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2" => Some("v1:i0889"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint" => Some("v1:i0918"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2" => Some("v1:i0890"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint" => Some("v1:i0919"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2" => Some("v1:i0891"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint" => Some("v1:i0920"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2" => Some("v1:i0892"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint" => Some("v1:i0921"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2" => Some("v1:i0893"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint" => {
-            Some("v1:i0922")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
-        | "cuda_device::tma::cp_async_bulk_tensor_1d_g2s" => Some("v1:i0328"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
-        | "cuda_device::tma::cp_async_bulk_tensor_1d_s2g" => Some("v1:i0335"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
-        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s" => Some("v1:i0329"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
-        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast" => Some("v1:i0330"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
-        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2" => Some("v1:i0331"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
-        | "cuda_device::tma::cp_async_bulk_tensor_2d_s2g" => Some("v1:i0336"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
-        | "cuda_device::tma::cp_async_bulk_tensor_3d_g2s" => Some("v1:i0332"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
-        | "cuda_device::tma::cp_async_bulk_tensor_3d_s2g" => Some("v1:i0337"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
-        | "cuda_device::tma::cp_async_bulk_tensor_4d_g2s" => Some("v1:i0333"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
-        | "cuda_device::tma::cp_async_bulk_tensor_4d_s2g" => Some("v1:i0338"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
-        | "cuda_device::tma::cp_async_bulk_tensor_5d_g2s" => Some("v1:i0334"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
-        | "cuda_device::tma::cp_async_bulk_tensor_5d_s2g" => Some("v1:i0339"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d" => Some("v1:i0928"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d" => Some("v1:i0929"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d" => Some("v1:i0930"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d" => Some("v1:i0923"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d" => Some("v1:i0924"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d" => Some("v1:i0925"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d" => Some("v1:i0926"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d" => Some("v1:i0927"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d" => Some("v1:i0936"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d" => Some("v1:i0937"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d" => Some("v1:i0938"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d" => Some("v1:i0931"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d" => Some("v1:i0932"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d" => Some("v1:i0933"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d" => Some("v1:i0934"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d" => Some("v1:i0935"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d" => Some("v1:i0944"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d" => Some("v1:i0945"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d" => Some("v1:i0946"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d" => Some("v1:i0939"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d" => Some("v1:i0940"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d" => Some("v1:i0941"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d" => Some("v1:i0942"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d" => Some("v1:i0943"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d" => Some("v1:i0952"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d" => Some("v1:i0953"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d" => Some("v1:i0954"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d" => Some("v1:i0947"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d" => Some("v1:i0948"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d" => Some("v1:i0949"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d" => Some("v1:i0950"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d" => Some("v1:i0951"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d" => Some("v1:i0960"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d" => Some("v1:i0961"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d" => Some("v1:i0962"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d" => Some("v1:i0955"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d" => Some("v1:i0956"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d" => Some("v1:i0957"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d" => Some("v1:i0958"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d" => Some("v1:i0959"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d" => Some("v1:i0968"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d" => Some("v1:i0969"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d" => Some("v1:i0970"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d" => Some("v1:i0963"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d" => Some("v1:i0964"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d" => Some("v1:i0965"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d" => Some("v1:i0966"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d" => Some("v1:i0967"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d" => Some("v1:i0976"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d" => Some("v1:i0977"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d" => Some("v1:i0978"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d" => Some("v1:i0971"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d" => Some("v1:i0972"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d" => Some("v1:i0973"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d" => Some("v1:i0974"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d" => Some("v1:i0975"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d" => Some("v1:i0984"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d" => Some("v1:i0985"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d" => Some("v1:i0986"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d" => Some("v1:i0979"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d" => Some("v1:i0980"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d" => Some("v1:i0981"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d" => Some("v1:i0982"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d" => Some("v1:i0983"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
-        | "cuda_device::tma::cp_async_bulk_wait_group" => Some("v1:i0341"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
-        | "cuda_device::tma::cp_async_bulk_wait_group_read" => Some("v1:i0342"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
-        | "cuda_device::async_copy::cp_async_ca_16" => Some("v1:i0090"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
-        | "cuda_device::async_copy::cp_async_ca_4" => Some("v1:i0086"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
-        | "cuda_device::async_copy::cp_async_ca_8" => Some("v1:i0088"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
-        | "cuda_device::async_copy::cp_async_ca_zfill_16" => Some("v1:i0091"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
-        | "cuda_device::async_copy::cp_async_ca_zfill_4" => Some("v1:i0087"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
-        | "cuda_device::async_copy::cp_async_ca_zfill_8" => Some("v1:i0089"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
-        | "cuda_device::async_copy::cp_async_cg_16" => Some("v1:i0092"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
-        | "cuda_device::async_copy::cp_async_cg_zfill_16" => Some("v1:i0093"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
-        | "cuda_device::async_copy::cp_async_commit_group" => Some("v1:i0094"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
-        | "cuda_device::async_copy::cp_async_mbarrier_arrive" => Some("v1:i0101"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
-        | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc" => Some("v1:i0103"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
-        | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared" => Some("v1:i0104"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
-        | "cuda_device::async_copy::cp_async_mbarrier_arrive_shared" => Some("v1:i0102"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
-        | "cuda_device::async_copy::cp_async_wait_all" => Some("v1:i0095"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
-        | "cuda_device::async_copy::cp_async_wait_group" => Some("v1:i0096"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
-        | "cuda_device::convert::cvt_f16x2_f32" => Some("v1:i0081"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
-        | "cuda_device::convert::cvt_bf16x2_f32" => Some("v1:i0071"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
-        | "cuda_device::convert::cvt_rn_f16x2_e4m3x2" => Some("v1:i0826"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
-        | "cuda_device::convert::cvt_rn_f16x2_e5m2x2" => Some("v1:i0828"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
-        | "cuda_device::convert::cvt_rn_relu_bf16x2_f32" => Some("v1:i0084"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
-        | "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2" => Some("v1:i0827"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
-        | "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2" => Some("v1:i0829"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
-        | "cuda_device::convert::cvt_rn_relu_f16x2_f32" => Some("v1:i0083"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
-        | "cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32" => Some("v1:i0373"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
-        | "cuda_device::convert::cvt_rn_relu_tf32_f32" => Some("v1:i0371"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
-        | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2" => Some("v1:i0822"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
-        | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32" => Some("v1:i0259"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
-        | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2" => Some("v1:i0824"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
-        | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32" => Some("v1:i0261"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
-        | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2" => Some("v1:i0823"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
-        | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32" => Some("v1:i0260"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
-        | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2" => Some("v1:i0825"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
-        | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32" => Some("v1:i0262"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
-        | "cuda_device::convert::cvt_rn_satfinite_tf32_f32" => Some("v1:i0372"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
-        | "cuda_device::convert::cvt_rn_tf32_f32" => Some("v1:i0370"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
-        | "cuda_device::convert::cvt_rna_satfinite_tf32_f32" => Some("v1:i0369"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
-        | "cuda_device::convert::cvt_rna_tf32_f32" => Some("v1:i0368"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
-        | "cuda_device::convert::cvt_rz_bf16x2_f32" => Some("v1:i0085"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
-        | "cuda_device::convert::cvt_rz_f16x2_f32" => Some("v1:i0082"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
-        | "cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32" => Some("v1:i0377"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
-        | "cuda_device::convert::cvt_rz_relu_tf32_f32" => Some("v1:i0375"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
-        | "cuda_device::convert::cvt_rz_satfinite_tf32_f32" => Some("v1:i0376"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
-        | "cuda_device::convert::cvt_rz_tf32_f32" => Some("v1:i0374"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
-        | "cuda_device::float::div_rm_f32" => Some("v1:i0414"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
-        | "cuda_device::float::div_rm_f64" => Some("v1:i0396"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
-        | "cuda_device::float::div_rm_ftz_f32" => Some("v1:i0415"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
-        | "cuda_device::float::div_rn_f32" => Some("v1:i0410"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
-        | "cuda_device::float::div_rn_f64" => Some("v1:i0394"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
-        | "cuda_device::float::div_rn_ftz_f32" => Some("v1:i0411"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
-        | "cuda_device::float::div_rp_f32" => Some("v1:i0416"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
-        | "cuda_device::float::div_rp_f64" => Some("v1:i0397"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
-        | "cuda_device::float::div_rp_ftz_f32" => Some("v1:i0417"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
-        | "cuda_device::float::div_rz_f32" => Some("v1:i0412"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
-        | "cuda_device::float::div_rz_f64" => Some("v1:i0395"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
-        | "cuda_device::float::div_rz_ftz_f32" => Some("v1:i0413"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
-        | "cuda_device::dotprod::dp2a_s32" => Some("v1:i0032"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
-        | "cuda_device::dotprod::dp2a_u32" => Some("v1:i0033"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
-        | "cuda_device::dotprod::dp4a_s32" => Some("v1:i0030"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
-        | "cuda_device::dotprod::dp4a_u32" => Some("v1:i0031"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
-        | "cuda_device::cluster::dsmem_read_u32" => Some("v1:i0321"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
-        | "cuda_device::shared::dynamic_smem_size" => Some("v1:i0293"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
-        | "cuda_device::warp::elect_sync" => Some("v1:i0367"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286" | "cuda_device::grid::envreg1" => {
-            Some("v1:i0286")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287" | "cuda_device::grid::envreg2" => {
-            Some("v1:i0287")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
-        | "cuda_device::float::ex2_approx_f16" => Some("v1:i1016"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
-        | "cuda_device::float::ex2_approx_f32" => Some("v1:i0819"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
-        | "cuda_device::float::ex2_approx_ftz_f32" => Some("v1:i0820"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
-        | "cuda_device::barrier::fence_mbarrier_init_release_cluster" => Some("v1:i0313"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
-        | "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster" => {
-            Some("v1:i0315")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
-        | "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster" => {
-            Some("v1:i0314")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
-        | "cuda_device::barrier::fence_proxy_async_shared_cta" => Some("v1:i0312"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster" => Some("v1:i0905"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta" => Some("v1:i0906"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu" => Some("v1:i0907"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system" => Some("v1:i0908"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster" => Some("v1:i0909"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_release_cta" => Some("v1:i0910"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu" => Some("v1:i0911"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_release_system" => Some("v1:i0912"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
-        | "cuda_device::bf16x2::fma_bf16x2" => Some("v1:i0062"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
-        | "cuda_device::f16x2::fma_f16x2" => Some("v1:i0072"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
-        | "cuda_device::f32x2::fma_f32x2" => Some("v1:i1001"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
-        | "cuda_device::f16x2::fma_ftz_f16x2" => Some("v1:i0854"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
-        | "cuda_device::f32x2::fma_ftz_f32x2" => Some("v1:i1002"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
-        | "cuda_device::f16x2::fma_ftz_relu_f16x2" => Some("v1:i0857"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
-        | "cuda_device::f16x2::fma_ftz_sat_f16x2" => Some("v1:i0856"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
-        | "cuda_device::bf16x2::fma_relu_bf16x2" => Some("v1:i0063"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
-        | "cuda_device::f16x2::fma_relu_f16x2" => Some("v1:i0073"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
-        | "cuda_device::float::fma_rm_f32" => Some("v1:i0426"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
-        | "cuda_device::float::fma_rm_f64" => Some("v1:i0400"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
-        | "cuda_device::float::fma_rm_ftz_f32" => Some("v1:i0427"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
-        | "cuda_device::float::fma_rm_ftz_sat_f32" => Some("v1:i0429"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
-        | "cuda_device::float::fma_rm_sat_f32" => Some("v1:i0428"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
-        | "cuda_device::float::fma_rn_f32" => Some("v1:i0418"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
-        | "cuda_device::float::fma_rn_f64" => Some("v1:i0398"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
-        | "cuda_device::float::fma_rn_ftz_f32" => Some("v1:i0419"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
-        | "cuda_device::float::fma_rn_ftz_sat_f32" => Some("v1:i0421"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
-        | "cuda_device::float::fma_rn_sat_f32" => Some("v1:i0420"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
-        | "cuda_device::float::fma_rp_f32" => Some("v1:i0430"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
-        | "cuda_device::float::fma_rp_f64" => Some("v1:i0401"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
-        | "cuda_device::float::fma_rp_ftz_f32" => Some("v1:i0431"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
-        | "cuda_device::float::fma_rp_ftz_sat_f32" => Some("v1:i0433"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
-        | "cuda_device::float::fma_rp_sat_f32" => Some("v1:i0432"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
-        | "cuda_device::float::fma_rz_f32" => Some("v1:i0422"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
-        | "cuda_device::float::fma_rz_f64" => Some("v1:i0399"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
-        | "cuda_device::float::fma_rz_ftz_f32" => Some("v1:i0423"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
-        | "cuda_device::float::fma_rz_ftz_sat_f32" => Some("v1:i0425"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
-        | "cuda_device::float::fma_rz_sat_f32" => Some("v1:i0424"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
-        | "cuda_device::f16x2::fma_sat_f16x2" => Some("v1:i0855"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
-        | "cuda_device::debug::globaltimer" => Some("v1:i0285"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
-        | "cuda_device::grid::dependency::trigger_dependents" => Some("v1:i0913"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
-        | "cuda_device::grid::dependency::wait" => Some("v1:i0914"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
-        | "cuda_device::thread::gridDim_x"
-        | "cuda_device::gridDim_x" => Some("v1:i0004"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
-        | "cuda_device::thread::gridDim_y"
-        | "cuda_device::gridDim_y" => Some("v1:i0008"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
-        | "cuda_device::thread::gridDim_z"
-        | "cuda_device::gridDim_z" => Some("v1:i0012"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
-        | "cuda_device::thread::gridid"
-        | "cuda_device::gridid" => Some("v1:i0290"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016" | "cuda_device::warp::lane_id" => {
-            Some("v1:i0016")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
-        | "cuda_device::warp::lanemask_eq" => Some("v1:i0037"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
-        | "cuda_device::warp::lanemask_ge" => Some("v1:i0038"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
-        | "cuda_device::warp::lanemask_gt" => Some("v1:i0039"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
-        | "cuda_device::warp::lanemask_le" => Some("v1:i0036"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
-        | "cuda_device::warp::lanemask_lt" => Some("v1:i0035"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378" => Some("v1:i0378"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379" => Some("v1:i0379"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380" => Some("v1:i0380"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381" => Some("v1:i0381"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382" => Some("v1:i0382"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383" => Some("v1:i0383"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384" => Some("v1:i0384"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385" => Some("v1:i0385"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
-        | "cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64" => Some("v1:i0386"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387" => Some("v1:i0387"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
-        | "cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64" => Some("v1:i0388"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389" => Some("v1:i0389"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
-        | "cuda_device::wmma::ldmatrix_x1" => Some("v1:i0025"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
-        | "cuda_device::wmma::ldmatrix_x1_trans" => Some("v1:i0026"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
-        | "cuda_device::wmma::ldmatrix_x2" => Some("v1:i0027"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
-        | "cuda_device::wmma::ldmatrix_x2_trans" => Some("v1:i0028"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
-        | "cuda_device::wmma::ldmatrix_x4" => Some("v1:i0013"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
-        | "cuda_device::wmma::ldmatrix_x4_trans" => Some("v1:i0029"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
-        | "cuda_device::float::lg2_approx_f32" => Some("v1:i0786"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
-        | "cuda_device::float::lg2_approx_ftz_f32" => Some("v1:i0787"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
-        | "cuda_device::cluster::map_shared_rank"
-        | "cuda_device::cluster::map_shared_rank_mut" => Some("v1:i0320"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
-        | "cuda_device::warp::match_all_i64_sync" => Some("v1:i0048"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
-        | "cuda_device::warp::match_all_sync" => Some("v1:i0047"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
-        | "cuda_device::warp::match_any_i64_sync" => Some("v1:i0046"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
-        | "cuda_device::warp::match_any_sync" => Some("v1:i0045"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850" | "cuda_device::bf16::max_bf16" => {
-            Some("v1:i0850")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
-        | "cuda_device::bf16x2::max_bf16x2" => Some("v1:i0068"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842" | "cuda_device::f16::max_f16" => {
-            Some("v1:i0842")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
-        | "cuda_device::f16x2::max_f16x2" => Some("v1:i0078"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
-        | "cuda_device::f16::max_ftz_f16" => Some("v1:i0843"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
-        | "cuda_device::f16x2::max_ftz_f16x2" => Some("v1:i0564"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
-        | "cuda_device::f16::max_ftz_nan_f16" => Some("v1:i0845"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
-        | "cuda_device::f16x2::max_ftz_nan_f16x2" => Some("v1:i0565"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
-        | "cuda_device::f16::max_ftz_nan_xorsign_abs_f16" => Some("v1:i0849"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
-        | "cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2" => Some("v1:i0567"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
-        | "cuda_device::float::max_ftz_nan_xorsign_abs_f32" => Some("v1:i0566"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
-        | "cuda_device::f16::max_ftz_xorsign_abs_f16" => Some("v1:i0847"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
-        | "cuda_device::f16x2::max_ftz_xorsign_abs_f16x2" => Some("v1:i0569"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
-        | "cuda_device::float::max_ftz_xorsign_abs_f32" => Some("v1:i0568"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
-        | "cuda_device::bf16::max_nan_bf16" => Some("v1:i0851"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
-        | "cuda_device::bf16x2::max_nan_bf16x2" => Some("v1:i0570"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
-        | "cuda_device::f16::max_nan_f16" => Some("v1:i0844"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
-        | "cuda_device::f16x2::max_nan_f16x2" => Some("v1:i0571"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
-        | "cuda_device::bf16::max_nan_xorsign_abs_bf16" => Some("v1:i0853"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
-        | "cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2" => Some("v1:i0572"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
-        | "cuda_device::f16::max_nan_xorsign_abs_f16" => Some("v1:i0848"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
-        | "cuda_device::f16x2::max_nan_xorsign_abs_f16x2" => Some("v1:i0574"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
-        | "cuda_device::float::max_nan_xorsign_abs_f32" => Some("v1:i0573"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
-        | "cuda_device::i16x2::max_relu_s16x2" => Some("v1:i0994"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
-        | "cuda_device::int::max_relu_s32" => Some("v1:i0988"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
-        | "cuda_device::i16x2::max_s16x2" => Some("v1:i0990"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
-        | "cuda_device::i16x2::max_u16x2" => Some("v1:i0992"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
-        | "cuda_device::bf16::max_xorsign_abs_bf16" => Some("v1:i0852"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
-        | "cuda_device::bf16x2::max_xorsign_abs_bf16x2" => Some("v1:i0575"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
-        | "cuda_device::f16::max_xorsign_abs_f16" => Some("v1:i0846"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
-        | "cuda_device::f16x2::max_xorsign_abs_f16x2" => Some("v1:i0577"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
-        | "cuda_device::float::max_xorsign_abs_f32" => Some("v1:i0576"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
-        | "cuda_device::barrier::mbarrier_arrive" => Some("v1:i0098"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
-        | "cuda_device::barrier::mbarrier_arrive_cluster" => Some("v1:i0308"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
-        | "cuda_device::barrier::mbarrier_arrive_expect_tx" => Some("v1:i0306"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
-        | "cuda_device::barrier::mbarrier_arrive_expect_tx_cluster" => Some("v1:i0307"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
-        | "cuda_device::barrier::mbarrier_init" => Some("v1:i0097"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
-        | "cuda_device::barrier::mbarrier_inval" => Some("v1:i0100"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
-        | "cuda_device::barrier::mbarrier_test_wait" => Some("v1:i0099"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
-        | "cuda_device::barrier::mbarrier_try_wait" => Some("v1:i0309"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
-        | "cuda_device::barrier::mbarrier_try_wait_parity" => Some("v1:i0310"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
-        | "cuda_device::barrier::mbarrier_try_wait_parity_cluster" => Some("v1:i0311"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838" | "cuda_device::bf16::min_bf16" => {
-            Some("v1:i0838")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
-        | "cuda_device::bf16x2::min_bf16x2" => Some("v1:i0067"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830" | "cuda_device::f16::min_f16" => {
-            Some("v1:i0830")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
-        | "cuda_device::f16x2::min_f16x2" => Some("v1:i0077"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
-        | "cuda_device::f16::min_ftz_f16" => Some("v1:i0831"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
-        | "cuda_device::f16x2::min_ftz_f16x2" => Some("v1:i0550"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
-        | "cuda_device::f16::min_ftz_nan_f16" => Some("v1:i0833"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
-        | "cuda_device::f16x2::min_ftz_nan_f16x2" => Some("v1:i0551"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
-        | "cuda_device::f16::min_ftz_nan_xorsign_abs_f16" => Some("v1:i0837"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
-        | "cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2" => Some("v1:i0553"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
-        | "cuda_device::float::min_ftz_nan_xorsign_abs_f32" => Some("v1:i0552"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
-        | "cuda_device::f16::min_ftz_xorsign_abs_f16" => Some("v1:i0835"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
-        | "cuda_device::f16x2::min_ftz_xorsign_abs_f16x2" => Some("v1:i0555"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
-        | "cuda_device::float::min_ftz_xorsign_abs_f32" => Some("v1:i0554"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
-        | "cuda_device::bf16::min_nan_bf16" => Some("v1:i0839"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
-        | "cuda_device::bf16x2::min_nan_bf16x2" => Some("v1:i0556"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
-        | "cuda_device::f16::min_nan_f16" => Some("v1:i0832"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
-        | "cuda_device::f16x2::min_nan_f16x2" => Some("v1:i0557"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
-        | "cuda_device::bf16::min_nan_xorsign_abs_bf16" => Some("v1:i0841"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
-        | "cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2" => Some("v1:i0558"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
-        | "cuda_device::f16::min_nan_xorsign_abs_f16" => Some("v1:i0836"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
-        | "cuda_device::f16x2::min_nan_xorsign_abs_f16x2" => Some("v1:i0560"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
-        | "cuda_device::float::min_nan_xorsign_abs_f32" => Some("v1:i0559"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
-        | "cuda_device::i16x2::min_relu_s16x2" => Some("v1:i0993"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
-        | "cuda_device::int::min_relu_s32" => Some("v1:i0987"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
-        | "cuda_device::i16x2::min_s16x2" => Some("v1:i0989"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
-        | "cuda_device::i16x2::min_u16x2" => Some("v1:i0991"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
-        | "cuda_device::bf16::min_xorsign_abs_bf16" => Some("v1:i0840"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
-        | "cuda_device::bf16x2::min_xorsign_abs_bf16x2" => Some("v1:i0561"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
-        | "cuda_device::f16::min_xorsign_abs_f16" => Some("v1:i0834"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
-        | "cuda_device::f16x2::min_xorsign_abs_f16x2" => Some("v1:i0563"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
-        | "cuda_device::float::min_xorsign_abs_f32" => Some("v1:i0562"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
-        | "cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc" => Some("v1:i0161"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
-        | "cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc" => Some("v1:i0158"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
-        | "cuda_device::wmma::mma_m16n8k16_f16_f16" => Some("v1:i0524"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
-        | "cuda_device::wmma::mma_m16n8k16_f32_bf16" => Some("v1:i0105"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
-        | "cuda_device::wmma::mma_m16n8k16_f32_f16" => Some("v1:i0106"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3" => Some("v1:i0504"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2" => Some("v1:i0505"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3" => Some("v1:i0506"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2" => Some("v1:i0507"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3" => Some("v1:i0508"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2" => Some("v1:i0509"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3" => Some("v1:i0510"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2" => Some("v1:i0511"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
-        | "cuda_device::wmma::mma_m16n8k16_s32_s8" => Some("v1:i0110"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
-        | "cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite" => Some("v1:i0117"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
-        | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8" => Some("v1:i0111"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
-        | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite" => Some("v1:i0118"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
-        | "cuda_device::wmma::mma_m16n8k16_s32_u8" => Some("v1:i0112"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
-        | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8" => Some("v1:i0113"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
-        | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite" => Some("v1:i0120"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
-        | "cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite" => Some("v1:i0119"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
-        | "cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc" => Some("v1:i0162"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
-        | "cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc" => Some("v1:i0159"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1" => Some("v1:i0479"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3" => Some("v1:i0480"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2" => Some("v1:i0481"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3" => Some("v1:i0482"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2" => Some("v1:i0483"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1" => Some("v1:i0484"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3" => Some("v1:i0485"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2" => Some("v1:i0486"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3" => Some("v1:i0487"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2" => Some("v1:i0488"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1" => Some("v1:i0489"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3" => Some("v1:i0490"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2" => Some("v1:i0491"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3" => Some("v1:i0492"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2" => Some("v1:i0493"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1" => Some("v1:i0494"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3" => Some("v1:i0495"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2" => Some("v1:i0496"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3" => Some("v1:i0497"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2" => Some("v1:i0498"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1" => Some("v1:i0499"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3" => Some("v1:i0500"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2" => Some("v1:i0501"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3" => Some("v1:i0502"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2" => Some("v1:i0503"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1" => Some("v1:i0454"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3" => Some("v1:i0455"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2" => Some("v1:i0456"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3" => Some("v1:i0457"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2" => Some("v1:i0458"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1" => Some("v1:i0459"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3" => Some("v1:i0460"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2" => Some("v1:i0461"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3" => Some("v1:i0462"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2" => Some("v1:i0463"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1" => Some("v1:i0464"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3" => Some("v1:i0465"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2" => Some("v1:i0466"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3" => Some("v1:i0467"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2" => Some("v1:i0468"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1" => Some("v1:i0469"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3" => Some("v1:i0470"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2" => Some("v1:i0471"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3" => Some("v1:i0472"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2" => Some("v1:i0473"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1" => Some("v1:i0474"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3" => Some("v1:i0475"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2" => Some("v1:i0476"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3" => Some("v1:i0477"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2" => Some("v1:i0478"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3" => Some("v1:i0512"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2" => Some("v1:i0513"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3" => Some("v1:i0514"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2" => Some("v1:i0515"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3" => Some("v1:i0516"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2" => Some("v1:i0517"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3" => Some("v1:i0518"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2" => Some("v1:i0519"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1" => Some("v1:i0858"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3" => Some("v1:i0859"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2" => Some("v1:i0860"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3" => Some("v1:i0861"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2" => Some("v1:i0862"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1" => Some("v1:i0863"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3" => Some("v1:i0864"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2" => Some("v1:i0865"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3" => Some("v1:i0866"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2" => Some("v1:i0867"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1" => Some("v1:i0868"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3" => Some("v1:i0869"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2" => Some("v1:i0870"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3" => Some("v1:i0871"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2" => Some("v1:i0872"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1" => Some("v1:i0873"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3" => Some("v1:i0874"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2" => Some("v1:i0875"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3" => Some("v1:i0876"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2" => Some("v1:i0877"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1" => Some("v1:i0878"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3" => Some("v1:i0879"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2" => Some("v1:i0880"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3" => Some("v1:i0881"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2" => Some("v1:i0882"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s4" => Some("v1:i0141"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite" => Some("v1:i0149"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4" => Some("v1:i0142"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite" => Some("v1:i0150"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s8" => Some("v1:i0108"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite" => Some("v1:i0121"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8" => Some("v1:i0114"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite" => Some("v1:i0122"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u4" => Some("v1:i0143"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4" => Some("v1:i0144"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite" => Some("v1:i0152"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite" => Some("v1:i0151"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u8" => Some("v1:i0115"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8" => Some("v1:i0116"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite" => Some("v1:i0124"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite" => Some("v1:i0123"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
-        | "cuda_device::wmma::mma_m16n8k4_f32_tf32" => Some("v1:i0520"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
-        | "cuda_device::wmma::mma_m16n8k64_s32_s4" => Some("v1:i0145"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
-        | "cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite" => Some("v1:i0153"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
-        | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4" => Some("v1:i0146"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
-        | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite" => Some("v1:i0154"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
-        | "cuda_device::wmma::mma_m16n8k64_s32_u4" => Some("v1:i0147"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
-        | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4" => Some("v1:i0148"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
-        | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite" => Some("v1:i0156"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
-        | "cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite" => Some("v1:i0155"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
-        | "cuda_device::wmma::mma_m16n8k8_f16_f16" => Some("v1:i0521"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
-        | "cuda_device::wmma::mma_m16n8k8_f32_bf16" => Some("v1:i0522"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
-        | "cuda_device::wmma::mma_m16n8k8_f32_f16" => Some("v1:i0523"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
-        | "cuda_device::wmma::mma_m16n8k8_f32_tf32" => Some("v1:i0107"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
-        | "cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc" => Some("v1:i0160"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
-        | "cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc" => Some("v1:i0157"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
-        | "cuda_device::wmma::mma_m8n8k16_s32_s8" => Some("v1:i0125"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
-        | "cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite" => Some("v1:i0129"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
-        | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8" => Some("v1:i0126"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
-        | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite" => Some("v1:i0130"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
-        | "cuda_device::wmma::mma_m8n8k16_s32_u8" => Some("v1:i0127"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
-        | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8" => Some("v1:i0128"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
-        | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite" => Some("v1:i0132"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
-        | "cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite" => Some("v1:i0131"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
-        | "cuda_device::wmma::mma_m8n8k32_s32_s4" => Some("v1:i0133"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
-        | "cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite" => Some("v1:i0137"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
-        | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4" => Some("v1:i0134"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
-        | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite" => Some("v1:i0138"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
-        | "cuda_device::wmma::mma_m8n8k32_s32_u4" => Some("v1:i0135"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
-        | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4" => Some("v1:i0136"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
-        | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite" => Some("v1:i0140"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
-        | "cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite" => Some("v1:i0139"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
-        | "cuda_device::wmma::mma_m8n8k4_f64" => Some("v1:i0109"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4" => Some("v1:i0219"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite" => Some("v1:i0223"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4" => Some("v1:i0220"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite" => Some("v1:i0224"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4" => Some("v1:i0221"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4" => Some("v1:i0222"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite" => Some("v1:i0226"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite" => Some("v1:i0225"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8" => Some("v1:i0163"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite" => Some("v1:i0167"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8" => Some("v1:i0164"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite" => Some("v1:i0168"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8" => Some("v1:i0165"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8" => Some("v1:i0166"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite" => Some("v1:i0170"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite" => Some("v1:i0169"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4" => Some("v1:i0211"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite" => Some("v1:i0215"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4" => Some("v1:i0212"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite" => Some("v1:i0216"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8" => Some("v1:i0187"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite" => Some("v1:i0191"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8" => Some("v1:i0188"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite" => Some("v1:i0192"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4" => Some("v1:i0213"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4" => Some("v1:i0214"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite" => Some("v1:i0218"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite" => Some("v1:i0217"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8" => Some("v1:i0189"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8" => Some("v1:i0190"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite" => Some("v1:i0194"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite" => Some("v1:i0193"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4" => Some("v1:i0203"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite" => {
-            Some("v1:i0207")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4" => Some("v1:i0204"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite" => {
-            Some("v1:i0208")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4" => Some("v1:i0205"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4" => Some("v1:i0206"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite" => {
-            Some("v1:i0210")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite" => {
-            Some("v1:i0209")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" => Some("v1:i0171"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite" => {
-            Some("v1:i0175")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8" => Some("v1:i0172"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite" => {
-            Some("v1:i0176")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8" => Some("v1:i0173"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8" => Some("v1:i0174"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite" => {
-            Some("v1:i0178")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite" => {
-            Some("v1:i0177")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16" => {
-            Some("v1:i0525")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16" => {
-            Some("v1:i0526")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16" => {
-            Some("v1:i0527")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16" => {
-            Some("v1:i0528")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16" => {
-            Some("v1:i0529")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16" => {
-            Some("v1:i0530")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16" => {
-            Some("v1:i0531")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16" => {
-            Some("v1:i0532")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16" => {
-            Some("v1:i0533")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16" => {
-            Some("v1:i0534")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16" => {
-            Some("v1:i0535")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16" => {
-            Some("v1:i0536")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16" => {
-            Some("v1:i0537")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16" => {
-            Some("v1:i0538")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16" => {
-            Some("v1:i0539")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16" => {
-            Some("v1:i0540")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16" => {
-            Some("v1:i0541")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16" => {
-            Some("v1:i0542")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16" => {
-            Some("v1:i0543")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16" => {
-            Some("v1:i0544")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16" => {
-            Some("v1:i0545")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16" => {
-            Some("v1:i0546")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16" => {
-            Some("v1:i0547")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16" => {
-            Some("v1:i0548")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16" => {
-            Some("v1:i0549")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32" => {
-            Some("v1:i0227")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32" => {
-            Some("v1:i0228")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32" => {
-            Some("v1:i0229")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32" => {
-            Some("v1:i0230")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32" => {
-            Some("v1:i0231")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32" => {
-            Some("v1:i0232")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32" => {
-            Some("v1:i0233")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32" => {
-            Some("v1:i0234")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32" => {
-            Some("v1:i0235")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32" => {
-            Some("v1:i0236")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32" => {
-            Some("v1:i0237")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32" => {
-            Some("v1:i0238")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32" => {
-            Some("v1:i0239")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32" => {
-            Some("v1:i0240")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32" => {
-            Some("v1:i0241")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32" => {
-            Some("v1:i0242")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32" => {
-            Some("v1:i0243")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32" => {
-            Some("v1:i0244")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32" => {
-            Some("v1:i0245")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32" => {
-            Some("v1:i0246")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32" => {
-            Some("v1:i0247")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32" => {
-            Some("v1:i0248")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32" => {
-            Some("v1:i0249")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32" => {
-            Some("v1:i0250")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32" => {
-            Some("v1:i0251")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4" => Some("v1:i0195"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite" => {
-            Some("v1:i0199")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4" => Some("v1:i0196"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite" => {
-            Some("v1:i0200")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8" => Some("v1:i0179"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite" => {
-            Some("v1:i0183")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8" => Some("v1:i0180"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite" => {
-            Some("v1:i0184")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4" => Some("v1:i0197"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4" => Some("v1:i0198"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite" => {
-            Some("v1:i0202")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite" => {
-            Some("v1:i0201")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8" => Some("v1:i0181"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8" => Some("v1:i0182"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" => {
-            Some("v1:i0186")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" => {
-            Some("v1:i0185")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
-        | "cuda_device::wmma::movmatrix_trans_b16" => Some("v1:i0305"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
-        | "cuda_device::bf16x2::mul_bf16x2" => Some("v1:i0066"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
-        | "cuda_device::f16x2::mul_f16x2" => Some("v1:i0076"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
-        | "cuda_device::f32x2::mul_f32x2" => Some("v1:i0999"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
-        | "cuda_device::f32x2::mul_ftz_f32x2" => Some("v1:i1000"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
-        | "cuda_device::float::mul_rm_f32" => Some("v1:i0406"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
-        | "cuda_device::float::mul_rm_f64" => Some("v1:i0392"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
-        | "cuda_device::float::mul_rm_ftz_f32" => Some("v1:i0407"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
-        | "cuda_device::float::mul_rn_f32" => Some("v1:i0402"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
-        | "cuda_device::float::mul_rn_f64" => Some("v1:i0390"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
-        | "cuda_device::float::mul_rn_ftz_f32" => Some("v1:i0403"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
-        | "cuda_device::float::mul_rp_f32" => Some("v1:i0408"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
-        | "cuda_device::float::mul_rp_f64" => Some("v1:i0393"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
-        | "cuda_device::float::mul_rp_ftz_f32" => Some("v1:i0409"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
-        | "cuda_device::float::mul_rz_f32" => Some("v1:i0404"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
-        | "cuda_device::float::mul_rz_f64" => Some("v1:i0391"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
-        | "cuda_device::float::mul_rz_ftz_f32" => Some("v1:i0405"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
-        | "cuda_device::barrier::nanosleep" => Some("v1:i0316"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
-        | "cuda_device::bf16x2::neg_bf16x2" => Some("v1:i0069"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
-        | "cuda_device::f16x2::neg_f16x2" => Some("v1:i0079"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
-        | "cuda_device::thread::nsmid"
-        | "cuda_device::nsmid" => Some("v1:i0289"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292" | "cuda_device::warp::nwarpid" => {
-            Some("v1:i0292")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
-        | "cuda_device::atomic::atom_add_bf16x2" => Some("v1:i0015"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
-        | "cuda_device::atomic::atom_add_f16x2" => Some("v1:i0014"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
-        | "cuda_device::debug::__prof_trigger" => Some("v1:i0297"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
-        | "cuda_device::tma::prefetch_tma_descriptor" => Some("v1:i0887"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252" | "cuda_device::prmt::prmt" => {
-            Some("v1:i0252")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254" | "cuda_device::prmt::prmt_b4e" => {
-            Some("v1:i0254")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256" | "cuda_device::prmt::prmt_ecl" => {
-            Some("v1:i0256")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257" | "cuda_device::prmt::prmt_ecr" => {
-            Some("v1:i0257")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253" | "cuda_device::prmt::prmt_f4e" => {
-            Some("v1:i0253")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
-        | "cuda_device::prmt::prmt_rc16" => Some("v1:i0258"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255" | "cuda_device::prmt::prmt_rc8" => {
-            Some("v1:i0255")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
-        | "cuda_device::float::rcp_approx_ftz_f32" => Some("v1:i0788"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
-        | "cuda_device::float::rcp_approx_ftz_f64" => Some("v1:i0797"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
-        | "cuda_device::float::rcp_rm_f32" => Some("v1:i0793"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
-        | "cuda_device::float::rcp_rm_f64" => Some("v1:i0800"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
-        | "cuda_device::float::rcp_rm_ftz_f32" => Some("v1:i0794"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
-        | "cuda_device::float::rcp_rn_f32" => Some("v1:i0789"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
-        | "cuda_device::float::rcp_rn_f64" => Some("v1:i0798"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
-        | "cuda_device::float::rcp_rn_ftz_f32" => Some("v1:i0790"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
-        | "cuda_device::float::rcp_rp_f32" => Some("v1:i0795"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
-        | "cuda_device::float::rcp_rp_f64" => Some("v1:i0801"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
-        | "cuda_device::float::rcp_rp_ftz_f32" => Some("v1:i0796"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
-        | "cuda_device::float::rcp_rz_f32" => Some("v1:i0791"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
-        | "cuda_device::float::rcp_rz_f64" => Some("v1:i0799"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
-        | "cuda_device::float::rcp_rz_ftz_f32" => Some("v1:i0792"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
-        | "cuda_device::warp::redux_sync_add" => Some("v1:i0017"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
-        | "cuda_device::warp::redux_sync_and" => Some("v1:i0022"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
-        | "cuda_device::warp::redux_sync_max_abs_f32" => Some("v1:i1009"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
-        | "cuda_device::warp::redux_sync_max_abs_nan_f32" => Some("v1:i1010"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
-        | "cuda_device::warp::redux_sync_max_f32" => Some("v1:i1007"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
-        | "cuda_device::warp::redux_sync_max_i32" => Some("v1:i0021"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
-        | "cuda_device::warp::redux_sync_max_nan_f32" => Some("v1:i1008"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
-        | "cuda_device::warp::redux_sync_max_u32" => Some("v1:i0020"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
-        | "cuda_device::warp::redux_sync_min_abs_f32" => Some("v1:i1005"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
-        | "cuda_device::warp::redux_sync_min_abs_nan_f32" => Some("v1:i1006"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
-        | "cuda_device::warp::redux_sync_min_f32" => Some("v1:i1003"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
-        | "cuda_device::warp::redux_sync_min_i32" => Some("v1:i0019"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
-        | "cuda_device::warp::redux_sync_min_nan_f32" => Some("v1:i1004"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
-        | "cuda_device::warp::redux_sync_min_u32" => Some("v1:i0018"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
-        | "cuda_device::warp::redux_sync_or" => Some("v1:i0023"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
-        | "cuda_device::warp::redux_sync_xor" => Some("v1:i0024"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
-        | "cuda_device::float::rsqrt_approx_f32" => Some("v1:i0802"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
-        | "cuda_device::float::rsqrt_approx_f64" => Some("v1:i0804"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
-        | "cuda_device::float::rsqrt_approx_ftz_f32" => Some("v1:i0803"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
-        | "cuda_device::thread::__setmaxnreg_dec" => Some("v1:i0916"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
-        | "cuda_device::thread::__setmaxnreg_inc" => Some("v1:i0915"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
-        | "cuda_device::warp::shuffle_down_f32_sync" => Some("v1:i0056"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
-        | "cuda_device::warp::shuffle_down_sync" => Some("v1:i0052"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
-        | "cuda_device::warp::shuffle_down_u64_sync" => Some("v1:i0060"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
-        | "cuda_device::warp::shuffle_f32_sync" => Some("v1:i0054"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
-        | "cuda_device::warp::shuffle_sync" => Some("v1:i0050"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
-        | "cuda_device::warp::shuffle_u64_sync" => Some("v1:i0058"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
-        | "cuda_device::warp::shuffle_up_f32_sync" => Some("v1:i0057"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
-        | "cuda_device::warp::shuffle_up_sync" => Some("v1:i0053"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
-        | "cuda_device::warp::shuffle_up_u64_sync" => Some("v1:i0061"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
-        | "cuda_device::warp::shuffle_xor_f32_sync" => Some("v1:i0055"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
-        | "cuda_device::warp::shuffle_xor_sync" => Some("v1:i0051"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
-        | "cuda_device::warp::shuffle_xor_u64_sync" => Some("v1:i0059"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
-        | "cuda_device::float::sin_approx_f32" => Some("v1:i0782"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
-        | "cuda_device::float::sin_approx_ftz_f32" => Some("v1:i0783"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
-        | "cuda_device::thread::smid"
-        | "cuda_device::smid" => Some("v1:i0288"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
-        | "cuda_device::float::sqrt_approx_f32" => Some("v1:i0805"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
-        | "cuda_device::float::sqrt_approx_ftz_f32" => Some("v1:i0806"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
-        | "cuda_device::float::sqrt_rm_f32" => Some("v1:i0811"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
-        | "cuda_device::float::sqrt_rm_f64" => Some("v1:i0817"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
-        | "cuda_device::float::sqrt_rm_ftz_f32" => Some("v1:i0812"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
-        | "cuda_device::float::sqrt_rn_f32" => Some("v1:i0807"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
-        | "cuda_device::float::sqrt_rn_f64" => Some("v1:i0815"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
-        | "cuda_device::float::sqrt_rn_ftz_f32" => Some("v1:i0808"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
-        | "cuda_device::float::sqrt_rp_f32" => Some("v1:i0813"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
-        | "cuda_device::float::sqrt_rp_f64" => Some("v1:i0818"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
-        | "cuda_device::float::sqrt_rp_ftz_f32" => Some("v1:i0814"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
-        | "cuda_device::float::sqrt_rz_f32" => Some("v1:i0809"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
-        | "cuda_device::float::sqrt_rz_f64" => Some("v1:i0816"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
-        | "cuda_device::float::sqrt_rz_ftz_f32" => Some("v1:i0810"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
-        | "cuda_device::tcgen05::stmatrix_m8n8_x2" => Some("v1:i0301"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
-        | "cuda_device::tcgen05::stmatrix_m8n8_x2_trans" => Some("v1:i0302"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
-        | "cuda_device::tcgen05::stmatrix_m8n8_x4" => Some("v1:i0303"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
-        | "cuda_device::tcgen05::stmatrix_m8n8_x4_trans" => Some("v1:i0304"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
-        | "cuda_device::bf16x2::sub_bf16x2" => Some("v1:i0065"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
-        | "cuda_device::f16x2::sub_f16x2" => Some("v1:i0075"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
-        | "cuda_device::f32x2::sub_f32x2" => Some("v1:i0997"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
-        | "cuda_device::f32x2::sub_ftz_f32x2" => Some("v1:i0998"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
-        | "cuda_device::warp::sync_mask" => Some("v1:i0049"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
-        | "cuda_device::thread::sync_threads"
-        | "cuda_device::sync_threads" => Some("v1:i0034"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
-        | "cuda_device::float::tanh_approx_f32" => Some("v1:i0821"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
-        | "cuda_device::tcgen05::tcgen05_alloc" => Some("v1:i0343"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
-        | "cuda_device::tcgen05::tcgen05_alloc_cg2" => Some("v1:i0359"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
-        | "cuda_device::tcgen05::tcgen05_commit" => Some("v1:i0348"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
-        | "cuda_device::tcgen05::tcgen05_commit_cg2" => Some("v1:i0363"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
-        | "cuda_device::tcgen05::tcgen05_commit_multicast" => Some("v1:i0760"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
-        | "cuda_device::tcgen05::tcgen05_commit_multicast_cg2" => Some("v1:i0365"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
-        | "cuda_device::tcgen05::tcgen05_commit_shared_cluster" => Some("v1:i0349"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
-        | "cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2" => Some("v1:i0364"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b" => Some("v1:i0582"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64" => Some("v1:i0578"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2" => Some("v1:i0579"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32" => Some("v1:i0580"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2" => Some("v1:i0581"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b_cg2" => Some("v1:i0583"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
-        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64" => Some("v1:i0584"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
-        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2" => Some("v1:i0585"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
-        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32" => Some("v1:i0586"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
-        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2" => Some("v1:i0587"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4" => Some("v1:i0592"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64" => Some("v1:i0588"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2" => Some("v1:i0589"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32" => Some("v1:i0590"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2" => Some("v1:i0591"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2" => Some("v1:i0593"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b" => Some("v1:i0598"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64" => Some("v1:i0594"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2" => Some("v1:i0595"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32" => Some("v1:i0596"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2" => Some("v1:i0597"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b_cg2" => Some("v1:i0599"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23" => Some("v1:i0604"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64" => Some("v1:i0600"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2" => Some("v1:i0601"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32" => Some("v1:i0602"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2" => Some("v1:i0603"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2" => Some("v1:i0605"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13" => Some("v1:i0610"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64" => Some("v1:i0606"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2" => Some("v1:i0607"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32" => Some("v1:i0608"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2" => Some("v1:i0609"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2" => Some("v1:i0611"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
-        | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem" => Some("v1:i0354"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
-        | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2" => Some("v1:i0366"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
-        | "cuda_device::tcgen05::tcgen05_dealloc" => Some("v1:i0344"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
-        | "cuda_device::tcgen05::tcgen05_dealloc_cg2" => Some("v1:i0360"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
-        | "cuda_device::tcgen05::tcgen05_fence_after_thread_sync" => Some("v1:i0347"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
-        | "cuda_device::tcgen05::tcgen05_fence_before_thread_sync" => Some("v1:i0346"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16" => Some("v1:i0637"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw" => Some("v1:i0636"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16" => Some("v1:i0629"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw" => Some("v1:i0628"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16" => Some("v1:i0631"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw" => Some("v1:i0630"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16" => Some("v1:i0639"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw" => Some("v1:i0638"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16" => Some("v1:i0633"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw" => Some("v1:i0632"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16" => Some("v1:i0641"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw" => Some("v1:i0640"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16" => Some("v1:i0635"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw" => Some("v1:i0634"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_pure" => Some("v1:i0356"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16" => Some("v1:i0651"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw" => Some("v1:i0650"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16" => Some("v1:i0643"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw" => Some("v1:i0642"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16" => Some("v1:i0645"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw" => Some("v1:i0644"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16" => Some("v1:i0653"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw" => Some("v1:i0652"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16" => Some("v1:i0647"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw" => Some("v1:i0646"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16" => Some("v1:i0649"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure" => Some("v1:i0355"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw" => Some("v1:i0648"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16" => Some("v1:i0743"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw" => Some("v1:i0742"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16" => Some("v1:i0737"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw" => Some("v1:i0736"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16" => Some("v1:i0729"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw" => Some("v1:i0728"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16" => Some("v1:i0731"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw" => Some("v1:i0730"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16" => Some("v1:i0739"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw" => Some("v1:i0738"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16" => Some("v1:i0733"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw" => Some("v1:i0732"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16" => Some("v1:i0741"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw" => Some("v1:i0740"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16" => Some("v1:i0735"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw" => Some("v1:i0734"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16" => Some("v1:i0627"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw" => Some("v1:i0626"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16" => Some("v1:i0621"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw" => Some("v1:i0620"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16" => Some("v1:i0613"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw" => Some("v1:i0612"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16" => Some("v1:i0615"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw" => Some("v1:i0614"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16" => Some("v1:i0623"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw" => Some("v1:i0622"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16" => Some("v1:i0617"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw" => Some("v1:i0616"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16" => Some("v1:i0625"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw" => Some("v1:i0624"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16" => Some("v1:i0619"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw" => Some("v1:i0618"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16" => Some("v1:i0669"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw" => Some("v1:i0668"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16" => Some("v1:i0663"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw" => Some("v1:i0662"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16" => Some("v1:i0655"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw" => Some("v1:i0654"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16" => Some("v1:i0657"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw" => Some("v1:i0656"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16" => Some("v1:i0665"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw" => Some("v1:i0664"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16" => Some("v1:i0659"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw" => Some("v1:i0658"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16" => Some("v1:i0667"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw" => Some("v1:i0666"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16" => Some("v1:i0661"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw" => Some("v1:i0660"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
-        | "cuda_device::tcgen05::tcgen05_load_wait" => Some("v1:i0357"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
-        | "cuda_device::tcgen05::tcgen05_mma_e2m1" => Some("v1:i1015"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
-        | "cuda_device::tcgen05::tcgen05_mma_e2m3" => Some("v1:i1013"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
-        | "cuda_device::tcgen05::tcgen05_mma_e3m2" => Some("v1:i1014"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
-        | "cuda_device::tcgen05::tcgen05_mma_e4m3" => Some("v1:i1011"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
-        | "cuda_device::tcgen05::tcgen05_mma_e5m2" => Some("v1:i1012"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
-        | "cuda_device::tcgen05::tcgen05_mma_f16" => Some("v1:i0351"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
-        | "cuda_device::tcgen05::tcgen05_mma_f16_cg2" => Some("v1:i0362"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
-        | "cuda_device::tcgen05::__tcgen05_mma_shared" => Some("v1:i0763"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
-        | "cuda_device::tcgen05::__tcgen05_mma_sp_shared" => Some("v1:i0766"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
-        | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor" => Some("v1:i0767"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
-        | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift" => Some("v1:i0768"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
-        | "cuda_device::tcgen05::__tcgen05_mma_tensor" => Some("v1:i0764"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
-        | "cuda_device::tcgen05::__tcgen05_mma_tensor_ashift" => Some("v1:i0765"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_bf16" => Some("v1:i0352"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_e2m1" => Some("v1:i0781"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_e2m3" => Some("v1:i0779"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_e3m2" => Some("v1:i0780"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_e4m3" => Some("v1:i0777"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_e5m2" => Some("v1:i0778"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_f16" => Some("v1:i0350"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_shared" => Some("v1:i0769"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask" => Some("v1:i0770"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared" => Some("v1:i0771"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask" => Some("v1:i0772"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor" => Some("v1:i0773"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask" => Some("v1:i0774"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor" => Some("v1:i0775"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask" => Some("v1:i0776"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_tf32" => Some("v1:i0353"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
-        | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit" => Some("v1:i0345"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
-        | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2" => Some("v1:i0361"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
-        | "cuda_device::tcgen05::tcgen05_shift_down" => Some("v1:i0761"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
-        | "cuda_device::tcgen05::tcgen05_shift_down_cg2" => Some("v1:i0762"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw" => Some("v1:i0694"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16" => Some("v1:i0695"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw" => Some("v1:i0686"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16" => Some("v1:i0687"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw" => Some("v1:i0688"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16" => Some("v1:i0689"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw" => Some("v1:i0696"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16" => Some("v1:i0697"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw" => Some("v1:i0690"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16" => Some("v1:i0691"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw" => Some("v1:i0698"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16" => Some("v1:i0699"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw" => Some("v1:i0692"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16" => Some("v1:i0693"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw" => Some("v1:i0708"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16" => Some("v1:i0709"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw" => Some("v1:i0700"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16" => Some("v1:i0701"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw" => Some("v1:i0702"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16" => Some("v1:i0703"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw" => Some("v1:i0710"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16" => Some("v1:i0711"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw" => Some("v1:i0704"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16" => Some("v1:i0705"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw" => Some("v1:i0706"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16" => Some("v1:i0707"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw" => Some("v1:i0758"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16" => Some("v1:i0759"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw" => Some("v1:i0752"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16" => Some("v1:i0753"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw" => Some("v1:i0744"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16" => Some("v1:i0745"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw" => Some("v1:i0746"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16" => Some("v1:i0747"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw" => Some("v1:i0754"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16" => Some("v1:i0755"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw" => Some("v1:i0748"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16" => Some("v1:i0749"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw" => Some("v1:i0756"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16" => Some("v1:i0757"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw" => Some("v1:i0750"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16" => Some("v1:i0751"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw" => Some("v1:i0684"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16" => Some("v1:i0685"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw" => Some("v1:i0678"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16" => Some("v1:i0679"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw" => Some("v1:i0670"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16" => Some("v1:i0671"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw" => Some("v1:i0672"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16" => Some("v1:i0673"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw" => Some("v1:i0680"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16" => Some("v1:i0681"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw" => Some("v1:i0674"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16" => Some("v1:i0675"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw" => Some("v1:i0682"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16" => Some("v1:i0683"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw" => Some("v1:i0676"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16" => Some("v1:i0677"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw" => Some("v1:i0726"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16" => Some("v1:i0727"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw" => Some("v1:i0720"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16" => Some("v1:i0721"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw" => Some("v1:i0712"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16" => Some("v1:i0713"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw" => Some("v1:i0714"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16" => Some("v1:i0715"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw" => Some("v1:i0722"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16" => Some("v1:i0723"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw" => Some("v1:i0716"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16" => Some("v1:i0717"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw" => Some("v1:i0724"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16" => Some("v1:i0725"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw" => Some("v1:i0718"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16" => Some("v1:i0719"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
-        | "cuda_device::tcgen05::tcgen05_store_wait" => Some("v1:i0358"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
-        | "cuda_device::tma::tensormap_replace_box_dim" => Some("v1:i0894"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
-        | "cuda_device::tma::tensormap_replace_element_stride" => Some("v1:i0895"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
-        | "cuda_device::tma::tensormap_replace_element_type" => Some("v1:i0896"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
-        | "cuda_device::tma::tensormap_replace_fill_mode" => Some("v1:i0897"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
-        | "cuda_device::tma::tensormap_replace_global_address" => Some("v1:i0898"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
-        | "cuda_device::tma::tensormap_replace_global_dim" => Some("v1:i0899"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
-        | "cuda_device::tma::tensormap_replace_global_stride" => Some("v1:i0900"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
-        | "cuda_device::tma::tensormap_replace_interleave_layout" => Some("v1:i0901"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
-        | "cuda_device::tma::tensormap_replace_rank" => Some("v1:i0902"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
-        | "cuda_device::tma::tensormap_replace_swizzle_atomicity" => Some("v1:i0903"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
-        | "cuda_device::tma::tensormap_replace_swizzle_mode" => Some("v1:i0904"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
-        | "cuda_device::thread::threadIdx_x"
-        | "cuda_device::threadIdx_x" => Some("v1:i0001"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
-        | "cuda_device::thread::threadIdx_y"
-        | "cuda_device::threadIdx_y" => Some("v1:i0005"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
-        | "cuda_device::thread::threadIdx_z"
-        | "cuda_device::threadIdx_z" => Some("v1:i0009"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
-        | "cuda_device::fence::threadfence"
-        | "cuda_device::threadfence" => Some("v1:i0299"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
-        | "cuda_device::fence::threadfence_block"
-        | "cuda_device::threadfence_block" => Some("v1:i0298"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
-        | "cuda_device::fence::threadfence_system"
-        | "cuda_device::threadfence_system" => Some("v1:i0300"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
-        | "cuda_device::shared::total_smem_size" => Some("v1:i0294"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295" | "cuda_device::debug::trap" => {
-            Some("v1:i0295")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043" => Some("v1:i0043"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291" | "cuda_device::warp::warpid" => {
-            Some("v1:i0291")
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
-        | "cuda_device::wgmma::wgmma_commit_group" => Some("v1:i0318"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
-        | "cuda_device::wgmma::wgmma_fence" => Some("v1:i0317"),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
-        | "cuda_device::wgmma::__wgmma_wait_group" => Some("v1:i0319"),
-        _ => None,
-    }
-}
-
-#[allow(clippy::too_many_arguments)]
-pub fn try_dispatch_generated_intrinsic(
-    ctx: &mut Context,
-    body: &mir::Body,
-    name: &str,
-    args: &[mir::Operand],
-    destination: &mir::Place,
-    target: &Option<usize>,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    value_map: &mut ValueMap,
-    block_map: &[Ptr<BasicBlock>],
-    loc: Location,
-) -> TranslationResult<Option<Ptr<Operation>>> {
-    match name {
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
-        | "cuda_device::thread::blockDim_x"
-        | "cuda_device::blockDim_x" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNtidXOp::get_concrete_op_info(),
-                "v1:i0003",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
-        | "cuda_device::thread::blockDim_y"
-        | "cuda_device::blockDim_y" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNtidYOp::get_concrete_op_info(),
-                "v1:i0007",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
-        | "cuda_device::thread::blockDim_z"
-        | "cuda_device::blockDim_z" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNtidZOp::get_concrete_op_info(),
-                "v1:i0011",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
-        | "cuda_device::thread::blockIdx_x"
-        | "cuda_device::blockIdx_x" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregCtaidXOp::get_concrete_op_info(),
-                "v1:i0002",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
-        | "cuda_device::thread::blockIdx_y"
-        | "cuda_device::blockIdx_y" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregCtaidYOp::get_concrete_op_info(),
-                "v1:i0006",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
-        | "cuda_device::thread::blockIdx_z"
-        | "cuda_device::blockIdx_z" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregCtaidZOp::get_concrete_op_info(),
-                "v1:i0010",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283" | "cuda_device::debug::clock" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClockOp::get_concrete_op_info(),
-                "v1:i0283",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284" | "cuda_device::debug::clock64" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic_u64(
-                ctx,
-                ReadPtxSregClock64Op::get_concrete_op_info(),
-                "v1:i0284",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterNctarankOp::get_concrete_op_info(),
-                "v1:i0276",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
-        | "cuda_device::cluster::cluster_ctaidX" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterCtaidXOp::get_concrete_op_info(),
-                "v1:i0263",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
-        | "cuda_device::cluster::cluster_ctaidY" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterCtaidYOp::get_concrete_op_info(),
-                "v1:i0264",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
-        | "cuda_device::cluster::cluster_ctaidZ" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterCtaidZOp::get_concrete_op_info(),
-                "v1:i0265",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterCtarankOp::get_concrete_op_info(),
-                "v1:i0275",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
-        | "cuda_device::cluster::cluster_nctaidX" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterNctaidXOp::get_concrete_op_info(),
-                "v1:i0266",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
-        | "cuda_device::cluster::cluster_nctaidY" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterNctaidYOp::get_concrete_op_info(),
-                "v1:i0267",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
-        | "cuda_device::cluster::cluster_nctaidZ" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterNctaidZOp::get_concrete_op_info(),
-                "v1:i0268",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
-        | "cuda_device::cluster::__cluster_grid_dimX" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNclusterIdXOp::get_concrete_op_info(),
-                "v1:i0272",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
-        | "cuda_device::cluster::__cluster_grid_dimY" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNclusterIdYOp::get_concrete_op_info(),
-                "v1:i0273",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
-        | "cuda_device::cluster::__cluster_grid_dimZ" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNclusterIdZOp::get_concrete_op_info(),
-                "v1:i0274",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
-        | "cuda_device::cluster::__cluster_idxX" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterIdXOp::get_concrete_op_info(),
-                "v1:i0269",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
-        | "cuda_device::cluster::__cluster_idxY" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterIdYOp::get_concrete_op_info(),
-                "v1:i0270",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
-        | "cuda_device::cluster::__cluster_idxZ" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregClusterIdZOp::get_concrete_op_info(),
-                "v1:i0271",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
-        | "cuda_device::shared::dynamic_smem_size" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregDynamicSmemSizeOp::get_concrete_op_info(),
-                "v1:i0293",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286" | "cuda_device::grid::envreg1" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregEnvReg1Op::get_concrete_op_info(),
-                "v1:i0286",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287" | "cuda_device::grid::envreg2" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregEnvReg2Op::get_concrete_op_info(),
-                "v1:i0287",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
-        | "cuda_device::debug::globaltimer" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic_u64(
-                ctx,
-                ReadPtxSregGlobaltimerOp::get_concrete_op_info(),
-                "v1:i0285",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
-        | "cuda_device::thread::gridDim_x"
-        | "cuda_device::gridDim_x" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNctaidXOp::get_concrete_op_info(),
-                "v1:i0004",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
-        | "cuda_device::thread::gridDim_y"
-        | "cuda_device::gridDim_y" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNctaidYOp::get_concrete_op_info(),
-                "v1:i0008",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
-        | "cuda_device::thread::gridDim_z"
-        | "cuda_device::gridDim_z" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNctaidZOp::get_concrete_op_info(),
-                "v1:i0012",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
-        | "cuda_device::thread::gridid"
-        | "cuda_device::gridid" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic_u64(
-                ctx,
-                ReadPtxSregGridIdOp::get_concrete_op_info(),
-                "v1:i0290",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016" | "cuda_device::warp::lane_id" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregLaneIdOp::get_concrete_op_info(),
-                "v1:i0016",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
-        | "cuda_device::warp::lanemask_eq" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregLanemaskEqOp::get_concrete_op_info(),
-                "v1:i0037",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
-        | "cuda_device::warp::lanemask_ge" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregLanemaskGeOp::get_concrete_op_info(),
-                "v1:i0038",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
-        | "cuda_device::warp::lanemask_gt" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregLanemaskGtOp::get_concrete_op_info(),
-                "v1:i0039",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
-        | "cuda_device::warp::lanemask_le" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregLanemaskLeOp::get_concrete_op_info(),
-                "v1:i0036",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
-        | "cuda_device::warp::lanemask_lt" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregLanemaskLtOp::get_concrete_op_info(),
-                "v1:i0035",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
-        | "cuda_device::thread::nsmid"
-        | "cuda_device::nsmid" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNsmIdOp::get_concrete_op_info(),
-                "v1:i0289",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292" | "cuda_device::warp::nwarpid" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregNwarpIdOp::get_concrete_op_info(),
-                "v1:i0292",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
-        | "cuda_device::thread::smid"
-        | "cuda_device::smid" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregSmIdOp::get_concrete_op_info(),
-                "v1:i0288",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
-        | "cuda_device::thread::threadIdx_x"
-        | "cuda_device::threadIdx_x" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregTidXOp::get_concrete_op_info(),
-                "v1:i0001",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
-        | "cuda_device::thread::threadIdx_y"
-        | "cuda_device::threadIdx_y" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregTidYOp::get_concrete_op_info(),
-                "v1:i0005",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
-        | "cuda_device::thread::threadIdx_z"
-        | "cuda_device::threadIdx_z" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregTidZOp::get_concrete_op_info(),
-                "v1:i0009",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
-        | "cuda_device::shared::total_smem_size" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregTotalSmemSizeOp::get_concrete_op_info(),
-                "v1:i0294",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291" | "cuda_device::warp::warpid" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
-                ctx,
-                ReadPtxSregWarpIdOp::get_concrete_op_info(),
-                "v1:i0291",
-                destination,
-                target,
-                block_ptr,
-                prev_op,
-                value_map,
-                block_map,
-                loc,
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
-        | "cuda_device::warp::active_mask" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let active_mask = ActiveMaskOp::build(ctx);
-            active_mask.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, active_mask, "v1:i0044");
-            helpers::insert_op(ctx, active_mask, block_ptr, prev_op);
-            let result = active_mask.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                active_mask,
-                value_map,
-                block_map,
-                loc,
-                "active_mask call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0378");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m16n16_x1_trans_b8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8x16B4x16P64,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0379");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8x16B6x16P32,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0380");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0381");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m16n16_x2_trans_b8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8x16B4x16P64,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0382");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M16n16,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B8x16B6x16P32,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0383");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B4x16P64,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0384");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let value = load.deref(ctx).get_result(0);
-            let last_op = load;
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n16_x1_b8x16_b4x16_p64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B6x16P32,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0385");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let value = load.deref(ctx).get_result(0);
-            let last_op = load;
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n16_x1_b8x16_b6x16_p32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
-        | "cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B4x16P64,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0386");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n16_x2_b8x16_b4x16_p64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B6x16P32,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0387");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n16_x2_b8x16_b6x16_p32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
-        | "cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X4,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B4x16P64,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0388");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n16_x4_b8x16_b4x16_p64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n16,
-                LdmatrixMultiplicityAttr::X4,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B8x16B6x16P32,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0389");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n16_x4_b8x16_b6x16_p32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
-        | "cuda_device::wmma::ldmatrix_x1" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n8,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B16,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0025");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let value = load.deref(ctx).get_result(0);
-            let last_op = load;
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n8_x1_b16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
-        | "cuda_device::wmma::ldmatrix_x1_trans" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n8,
-                LdmatrixMultiplicityAttr::X1,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B16,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0026");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let value = load.deref(ctx).get_result(0);
-            let last_op = load;
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n8_x1_trans_b16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
-        | "cuda_device::wmma::ldmatrix_x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n8,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B16,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0027");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n8_x2_b16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
-        | "cuda_device::wmma::ldmatrix_x2_trans" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n8,
-                LdmatrixMultiplicityAttr::X2,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B16,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0028");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n8_x2_trans_b16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
-        | "cuda_device::wmma::ldmatrix_x4" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n8,
-                LdmatrixMultiplicityAttr::X4,
-                LdmatrixLayoutAttr::Normal,
-                LdmatrixElementAttr::B16,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0013");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n8_x4_b16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
-        | "cuda_device::wmma::ldmatrix_x4_trans" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let load = LdmatrixOp::build(
-                ctx,
-                address,
-                LdmatrixShapeAttr::M8n8,
-                LdmatrixMultiplicityAttr::X4,
-                LdmatrixLayoutAttr::Transposed,
-                LdmatrixElementAttr::B16,
-                LdmatrixStateSpaceAttr::Shared,
-            );
-            load.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0029");
-            helpers::insert_op(ctx, load, block_ptr, last_op);
-            let (value, last_op) =
-                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "ldmatrix_m8n8_x4_trans_b16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
-        | "cuda_device::tcgen05::stmatrix_m8n8_x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let store = Operation::new(
-                ctx,
-                StmatrixM8n8X2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            store.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, store, "v1:i0301");
-            helpers::insert_op(ctx, store, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    store,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "stmatrix_m8n8_x2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
-        | "cuda_device::tcgen05::stmatrix_m8n8_x2_trans" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let store = Operation::new(
-                ctx,
-                StmatrixM8n8X2TransOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            store.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, store, "v1:i0302");
-            helpers::insert_op(ctx, store, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    store,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "stmatrix_m8n8_x2_trans call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
-        | "cuda_device::tcgen05::stmatrix_m8n8_x4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let store = Operation::new(
-                ctx,
-                StmatrixM8n8X4Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            store.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, store, "v1:i0303");
-            helpers::insert_op(ctx, store, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    store,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "stmatrix_m8n8_x4 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
-        | "cuda_device::tcgen05::stmatrix_m8n8_x4_trans" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let store = Operation::new(
-                ctx,
-                StmatrixM8n8X4TransOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            store.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, store, "v1:i0304");
-            helpers::insert_op(ctx, store, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    store,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "stmatrix_m8n8_x4_trans call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
-        | "cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::AndPopc);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0161");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k128_s32_b1_and_popc call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
-        | "cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::XorPopc);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0158");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k128_s32_b1_xor_popc call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
-        | "cuda_device::wmma::mma_m16n8k16_f16_f16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::F16);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0524");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_f16_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
-        | "cuda_device::wmma::mma_m16n8k16_f32_bf16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::Bf16);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::Bf16);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0105");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_f32_bf16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
-        | "cuda_device::wmma::mma_m16n8k16_f32_f16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::F16);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0106");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_f32_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0504");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_fp8_f16_e4m3_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0505");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_fp8_f16_e4m3_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0506");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_fp8_f16_e5m2_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0507");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_fp8_f16_e5m2_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0508");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_fp8_f32_e4m3_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0509");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_fp8_f32_e4m3_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0510");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_fp8_f32_e5m2_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
-        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0511");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_fp8_f32_e5m2_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
-        | "cuda_device::wmma::mma_m16n8k16_s32_s8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0110");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_s32_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
-        | "cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0117");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_s32_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
-        | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0111");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_s32_s8_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
-        | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0118");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_s32_s8_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
-        | "cuda_device::wmma::mma_m16n8k16_s32_u8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0112");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_s32_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
-        | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0113");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_s32_u8_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
-        | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0120");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_s32_u8_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
-        | "cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0119");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k16_s32_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
-        | "cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k256);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::AndPopc);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0162");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k256_s32_b1_and_popc call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
-        | "cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k256);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::XorPopc);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0159");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k256_s32_b1_xor_popc call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0479");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e2m1_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0480");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e2m1_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0481");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e2m1_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0482");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e2m1_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0483");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e2m1_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0484");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e2m3_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0485");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e2m3_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0486");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e2m3_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0487");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e2m3_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0488");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e2m3_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0489");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e3m2_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0490");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e3m2_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0491");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e3m2_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0492");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e3m2_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0493");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e3m2_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0494");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e4m3_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0495");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e4m3_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0496");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e4m3_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0497");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e4m3_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0498");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e4m3_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0499");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e5m2_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0500");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e5m2_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0501");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e5m2_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0502");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e5m2_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
-        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0503");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f16_e5m2_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0454");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e2m1_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0455");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e2m1_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0456");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e2m1_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0457");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e2m1_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0458");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e2m1_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0459");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e2m3_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0460");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e2m3_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0461");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e2m3_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0462");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e2m3_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0463");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e2m3_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0464");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e3m2_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0465");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e3m2_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0466");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e3m2_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0467");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e3m2_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0468");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e3m2_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0469");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e4m3_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0470");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e4m3_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0471");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e4m3_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0472");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e4m3_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0473");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e4m3_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0474");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e5m2_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0475");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e5m2_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0476");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e5m2_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0477");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e5m2_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
-        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0478");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_f32_e5m2_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0512");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_fp8_f16_e4m3_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0513");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_fp8_f16_e4m3_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0514");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_fp8_f16_e5m2_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0515");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_fp8_f16_e5m2_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0516");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_fp8_f32_e4m3_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0517");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_fp8_f32_e4m3_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0518");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_fp8_f32_e5m2_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
-        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0519");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_fp8_f32_e5m2_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0858");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0859");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0860");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0861");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0862");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0863");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0864");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0865");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0866");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0867");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0868");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0869");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0870");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0871");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0872");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0873");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0874");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0875");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0876");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0877");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0878");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0879");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0880");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0881");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
-        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0882");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0141");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0149");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0142");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_s4_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0150");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_s4_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0108");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0121");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0114");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_s8_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
-        | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0122");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_s8_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0143");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0144");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_u4_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0152");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_u4_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0151");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0115");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0116");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_u8_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0124");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_u8_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
-        | "cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0123");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k32_s32_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
-        | "cuda_device::wmma::mma_m16n8k4_f32_tf32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k4);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::Tf32);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::Tf32);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0520");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k4_f32_tf32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
-        | "cuda_device::wmma::mma_m16n8k64_s32_s4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0145");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k64_s32_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
-        | "cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0153");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k64_s32_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
-        | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0146");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k64_s32_s4_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
-        | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0154");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k64_s32_s4_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
-        | "cuda_device::wmma::mma_m16n8k64_s32_u4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0147");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k64_s32_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
-        | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0148");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k64_s32_u4_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
-        | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0156");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k64_s32_u4_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
-        | "cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0155");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k64_s32_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
-        | "cuda_device::wmma::mma_m16n8k8_f16_f16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k8);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::F16);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0521");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k8_f16_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
-        | "cuda_device::wmma::mma_m16n8k8_f32_bf16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k8);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::Bf16);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::Bf16);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0522");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k8_f32_bf16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
-        | "cuda_device::wmma::mma_m16n8k8_f32_f16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k8);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::F16);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::F16);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0523");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k8_f32_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
-        | "cuda_device::wmma::mma_m16n8k8_f32_tf32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k8);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::Tf32);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::Tf32);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0107");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m16n8k8_f32_tf32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
-        | "cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k128);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::AndPopc);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0160");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k128_s32_b1_and_popc call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
-        | "cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k128);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::XorPopc);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0157");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k128_s32_b1_xor_popc call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
-        | "cuda_device::wmma::mma_m8n8k16_s32_s8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0125");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k16_s32_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
-        | "cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0129");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k16_s32_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
-        | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0126");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k16_s32_s8_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
-        | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0130");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k16_s32_s8_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
-        | "cuda_device::wmma::mma_m8n8k16_s32_u8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0127");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k16_s32_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
-        | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0128");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k16_s32_u8_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
-        | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0132");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k16_s32_u8_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
-        | "cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0131");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k16_s32_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
-        | "cuda_device::wmma::mma_m8n8k32_s32_s4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0133");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k32_s32_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
-        | "cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0137");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k32_s32_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
-        | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0134");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k32_s32_s4_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
-        | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0138");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k32_s32_s4_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
-        | "cuda_device::wmma::mma_m8n8k32_s32_u4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0135");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k32_s32_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
-        | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0136");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k32_s32_u4_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
-        | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0140");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k32_s32_u4_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
-        | "cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0139");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k32_s32_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
-        | "cuda_device::wmma::mma_m8n8k4_f64" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2F64A1F64B1F64ToD2F64,
-            )?;
-            let mma = Operation::new(
-                ctx,
-                RegisterMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = RegisterMmaOp::new(mma);
-            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k4);
-            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
-            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
-            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F64);
-            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::F64);
-            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::F64);
-            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0109");
-            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_m8n8k4_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0219");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k128_s32_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0223");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k128_s32_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0220");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k128_s32_s4_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0224");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k128_s32_s4_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0221");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k128_s32_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0222");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k128_s32_u4_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0226");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k128_s32_u4_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
-        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0225");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k128_s32_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0163");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k32_s32_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0167");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k32_s32_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0164");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k32_s32_s8_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0168");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k32_s32_s8_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0165");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k32_s32_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0166");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k32_s32_u8_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0170");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k32_s32_u8_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
-        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0169");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k32_s32_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0211");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0215");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0212");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_s4_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0216");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_s4_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0187");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0191");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0188");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_s8_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0192");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_s8_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0213");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0214");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_u4_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0218");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_u4_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0217");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0189");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0190");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_u8_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0194");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_u8_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
-        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0193");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_m16n8k64_s32_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0203");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k128_s32_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0207");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0204");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0208");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0205");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k128_s32_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0206");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0210");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0209");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0171");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k32_s32_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0175");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0172");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0176");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0173");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k32_s32_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0174");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0178");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0177");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0525");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0526");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0527");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0528");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0529");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0530");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0531");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0532");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0533");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0534");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0535");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0536");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0537");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0538");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0539");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0540");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0541");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0542");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0543");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0544");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0545");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0546");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0547");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0548");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0549");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0227");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0228");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0229");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0230");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0231");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0232");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0233");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0234");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0235");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0236");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0237");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0238");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0239");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0240");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0241");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0242");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0243");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0244");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0245");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0246");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0247");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0248");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0249");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0250");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0251");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0195");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0199");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0196");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0200");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0179");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0183");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0180");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0184");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0197");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_u4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0198");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0202");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0201");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0181");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_u8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0182");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0186");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
-        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            if !matches!(&args[4], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sparse MMA selector must be the compile-time constant 0".to_owned()
-                    )
-                );
-            }
-            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
-                ctx,
-                body,
-                args,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
-            )?;
-            let (metadata, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[3],
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            operands.push(metadata);
-            let (selector_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[4],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            operands.push(selector_value);
-            let mma = Operation::new(
-                ctx,
-                SparseMmaOp::get_concrete_op_info(),
-                vec![result_ty; result_count],
-                operands,
-                vec![],
-                0,
-            );
-            mma.deref_mut(ctx).set_loc(loc.clone());
-            let mma = SparseMmaOp::new(mma);
-            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
-            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
-            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
-            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
-            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
-            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
-            let mma = mma.get_operation();
-            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0185");
-            helpers::insert_op(ctx, mma, block_ptr, last_op);
-            let (result, last_op) =
-                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                last_op,
-                value_map,
-                block_map,
-                loc,
-                "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
-        | "cuda_device::atomic::atom_add_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (addend, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let atom =
-                PackedAtomicAddOp::build(ctx, address, addend, PackedAtomicFormatAttr::Bf16x2);
-            atom.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, atom, "v1:i0015");
-            helpers::insert_op(ctx, atom, block_ptr, last_op);
-            let value = atom.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                atom,
-                value_map,
-                block_map,
-                loc,
-                "atom_add_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
-        | "cuda_device::atomic::atom_add_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (addend, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let atom =
-                PackedAtomicAddOp::build(ctx, address, addend, PackedAtomicFormatAttr::F16x2);
-            atom.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, atom, "v1:i0014");
-            helpers::insert_op(ctx, atom, block_ptr, last_op);
-            let value = atom.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                value,
-                target,
-                block_ptr,
-                atom,
-                value_map,
-                block_map,
-                loc,
-                "atom_add_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
-        | "cuda_device::warp::redux_sync_add" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncAddOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0017");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_add call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
-        | "cuda_device::warp::redux_sync_and" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncAndOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0022");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_and call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
-        | "cuda_device::warp::redux_sync_max_abs_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncFmaxAbsOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1009");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_max_abs_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
-        | "cuda_device::warp::redux_sync_max_abs_nan_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncFmaxAbsNanOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1010");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_max_abs_nan_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
-        | "cuda_device::warp::redux_sync_max_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncFmaxOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1007");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_max_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
-        | "cuda_device::warp::redux_sync_max_i32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncMaxOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0021");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_max_i32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
-        | "cuda_device::warp::redux_sync_max_nan_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncFmaxNanOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1008");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_max_nan_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
-        | "cuda_device::warp::redux_sync_max_u32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncUmaxOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0020");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_max_u32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
-        | "cuda_device::warp::redux_sync_min_abs_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncFminAbsOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1005");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_min_abs_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
-        | "cuda_device::warp::redux_sync_min_abs_nan_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncFminAbsNanOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1006");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_min_abs_nan_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
-        | "cuda_device::warp::redux_sync_min_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncFminOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1003");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_min_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
-        | "cuda_device::warp::redux_sync_min_i32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncMinOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0019");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_min_i32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
-        | "cuda_device::warp::redux_sync_min_nan_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncFminNanOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1004");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_min_nan_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
-        | "cuda_device::warp::redux_sync_min_u32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncUminOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0018");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_min_u32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
-        | "cuda_device::warp::redux_sync_or" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncOrOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0023");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_or call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
-        | "cuda_device::warp::redux_sync_xor" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let reduction = ReduxSyncXorOp::build(ctx, member_mask, value);
-            reduction.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0024");
-            helpers::insert_op(ctx, reduction, block_ptr, last_op);
-            let result = reduction.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                reduction,
-                value_map,
-                block_map,
-                loc,
-                "redux_sync_xor call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040" | "cuda_device::warp::all_sync" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (predicate, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let vote = VoteSyncAllOp::build(ctx, member_mask, predicate);
-            vote.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, vote, "v1:i0040");
-            helpers::insert_op(ctx, vote, block_ptr, last_op);
-            let result = vote.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                vote,
-                value_map,
-                block_map,
-                loc,
-                "all_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041" | "cuda_device::warp::any_sync" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (predicate, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let vote = VoteSyncAnyOp::build(ctx, member_mask, predicate);
-            vote.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, vote, "v1:i0041");
-            helpers::insert_op(ctx, vote, block_ptr, last_op);
-            let result = vote.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                vote,
-                value_map,
-                block_map,
-                loc,
-                "any_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
-        | "cuda_device::warp::ballot_sync" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (predicate, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let vote = VoteSyncBallotOp::build(ctx, member_mask, predicate);
-            vote.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, vote, "v1:i0042");
-            helpers::insert_op(ctx, vote, block_ptr, last_op);
-            let result = vote.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                vote,
-                value_map,
-                block_map,
-                loc,
-                "ballot_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (predicate, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let vote = VoteSyncUniOp::build(ctx, member_mask, predicate);
-            vote.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, vote, "v1:i0043");
-            helpers::insert_op(ctx, vote, block_ptr, last_op);
-            let result = vote.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                vote,
-                value_map,
-                block_map,
-                loc,
-                "uni_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
-        | "cuda_device::warp::match_all_i64_sync" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let warp_match = MatchAllSyncI64Op::build(ctx, member_mask, value);
-            warp_match.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, warp_match, "v1:i0048");
-            helpers::insert_op(ctx, warp_match, block_ptr, last_op);
-            let result = warp_match.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                warp_match,
-                value_map,
-                block_map,
-                loc,
-                "match_all_i64_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
-        | "cuda_device::warp::match_all_sync" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let warp_match = MatchAllSyncI32Op::build(ctx, member_mask, value);
-            warp_match.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, warp_match, "v1:i0047");
-            helpers::insert_op(ctx, warp_match, block_ptr, last_op);
-            let result = warp_match.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                warp_match,
-                value_map,
-                block_map,
-                loc,
-                "match_all_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
-        | "cuda_device::warp::match_any_i64_sync" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let warp_match = MatchAnySyncI64Op::build(ctx, member_mask, value);
-            warp_match.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, warp_match, "v1:i0046");
-            helpers::insert_op(ctx, warp_match, block_ptr, last_op);
-            let result = warp_match.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                warp_match,
-                value_map,
-                block_map,
-                loc,
-                "match_any_i64_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
-        | "cuda_device::warp::match_any_sync" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let warp_match = MatchAnySyncI32Op::build(ctx, member_mask, value);
-            warp_match.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, warp_match, "v1:i0045");
-            helpers::insert_op(ctx, warp_match, block_ptr, last_op);
-            let result = warp_match.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                warp_match,
-                value_map,
-                block_map,
-                loc,
-                "match_any_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
-        | "cuda_device::warp::elect_sync" => {
-            require_arity(name, args.len(), 1, &loc)?;
-
-            let tuple_ty =
-                crate::translator::types::translate_destination_type(ctx, body, destination, &loc)?;
-            let (leader_ty, elected_ty) = {
-                let ty = tuple_ty.deref(ctx);
-                match ty.downcast_ref::<MirTupleType>() {
-                    Some(tuple) if tuple.get_types().len() == 2 => {
-                        (tuple.get_types()[0], tuple.get_types()[1])
-                    }
-                    _ => {
-                        return input_err!(
-                            loc.clone(),
-                            TranslationErr::unsupported(
-                                "warp::elect_sync destination must be a (u32, bool) tuple"
-                                    .to_owned()
-                            )
-                        );
-                    }
-                }
-            };
-            let (mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let elect = Operation::new(
-                ctx,
-                ElectSyncOp::get_concrete_op_info(),
-                vec![leader_ty, elected_ty],
-                vec![mask],
-                vec![],
-                0,
-            );
-            elect.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, elect, "v1:i0367");
-            helpers::insert_op(ctx, elect, block_ptr, last_op);
-            let leader = elect.deref(ctx).get_result(0);
-            let elected = elect.deref(ctx).get_result(1);
-            let tuple = Operation::new(
-                ctx,
-                MirConstructTupleOp::get_concrete_op_info(),
-                vec![tuple_ty],
-                vec![leader, elected],
-                vec![],
-                0,
-            );
-            tuple.deref_mut(ctx).set_loc(loc.clone());
-            tuple.insert_after(ctx, elect);
-            let result = tuple.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                tuple,
-                value_map,
-                block_map,
-                loc,
-                "elect_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
-        | "cuda_device::warp::sync_mask" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let barrier = BarWarpSyncOp::build(ctx, member_mask);
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0049");
-            helpers::insert_op(ctx, barrier, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported("sync_mask call without target block".to_owned())
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
-        | "cuda_device::warp::shuffle_down_f32_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncDownF32Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0056");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_down_f32_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
-        | "cuda_device::warp::shuffle_down_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncDownI32Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0052");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_down_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
-        | "cuda_device::warp::shuffle_down_u64_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncDownI64Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0060");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_down_u64_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
-        | "cuda_device::warp::shuffle_f32_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncIdxF32Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0054");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_f32_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
-        | "cuda_device::warp::shuffle_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncIdxI32Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0050");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
-        | "cuda_device::warp::shuffle_u64_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncIdxI64Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0058");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_u64_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
-        | "cuda_device::warp::shuffle_up_f32_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncUpF32Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0057");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_up_f32_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
-        | "cuda_device::warp::shuffle_up_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncUpI32Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0053");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_up_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
-        | "cuda_device::warp::shuffle_up_u64_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncUpI64Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0061");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_up_u64_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
-        | "cuda_device::warp::shuffle_xor_f32_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncBflyF32Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0055");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_xor_f32_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
-        | "cuda_device::warp::shuffle_xor_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncBflyI32Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0051");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_xor_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
-        | "cuda_device::warp::shuffle_xor_u64_sync" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (member_mask, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (lane_or_delta, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let shuffle = ShflSyncBflyI64Op::build(ctx, member_mask, value, lane_or_delta);
-            shuffle.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0059");
-            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
-            let result = shuffle.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                shuffle,
-                value_map,
-                block_map,
-                loc,
-                "shuffle_xor_u64_sync call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
-        | "cuda_device::dotprod::dp2a_s32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (c, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let dot = Dp2aS32Op::build(ctx, a, b, c);
-            dot.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, dot, "v1:i0032");
-            helpers::insert_op(ctx, dot, block_ptr, last_op);
-            let result = dot.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                dot,
-                value_map,
-                block_map,
-                loc,
-                "dp2a_s32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
-        | "cuda_device::dotprod::dp2a_u32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (c, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let dot = Dp2aU32Op::build(ctx, a, b, c);
-            dot.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, dot, "v1:i0033");
-            helpers::insert_op(ctx, dot, block_ptr, last_op);
-            let result = dot.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                dot,
-                value_map,
-                block_map,
-                loc,
-                "dp2a_u32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
-        | "cuda_device::dotprod::dp4a_s32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (c, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let dot = Dp4aS32Op::build(ctx, a, b, c);
-            dot.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, dot, "v1:i0030");
-            helpers::insert_op(ctx, dot, block_ptr, last_op);
-            let result = dot.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                dot,
-                value_map,
-                block_map,
-                loc,
-                "dp4a_s32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
-        | "cuda_device::dotprod::dp4a_u32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (c, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let dot = Dp4aU32Op::build(ctx, a, b, c);
-            dot.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, dot, "v1:i0031");
-            helpers::insert_op(ctx, dot, block_ptr, last_op);
-            let result = dot.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                dot,
-                value_map,
-                block_map,
-                loc,
-                "dp4a_u32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
-        | "cuda_device::bf16x2::abs_bf16x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = AbsBf16x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0070");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "abs_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
-        | "cuda_device::f16x2::abs_f16x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = AbsF16x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0080");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "abs_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
-        | "cuda_device::bf16x2::add_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = AddBf16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0064");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
-        | "cuda_device::f16x2::add_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = AddF16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0074");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
-        | "cuda_device::f32x2::add_f32x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = AddF32x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0995");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_f32x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
-        | "cuda_device::f32x2::add_ftz_f32x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = AddFtzF32x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0996");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_ftz_f32x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
-        | "cuda_device::bf16x2::fma_bf16x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = FmaBf16x2Op::build(ctx, arg0, arg1, arg2);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0062");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
-        | "cuda_device::f16x2::fma_f16x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = FmaF16x2Op::build(ctx, arg0, arg1, arg2);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0072");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
-        | "cuda_device::f32x2::fma_f32x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = FmaF32x2Op::build(ctx, arg0, arg1, arg2);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1001");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_f32x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
-        | "cuda_device::f16x2::fma_ftz_f16x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = FmaFtzF16x2Op::build(ctx, arg0, arg1, arg2);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0854");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_ftz_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
-        | "cuda_device::f32x2::fma_ftz_f32x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = FmaFtzF32x2Op::build(ctx, arg0, arg1, arg2);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1002");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_ftz_f32x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
-        | "cuda_device::f16x2::fma_ftz_relu_f16x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = FmaFtzReluF16x2Op::build(ctx, arg0, arg1, arg2);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0857");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_ftz_relu_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
-        | "cuda_device::f16x2::fma_ftz_sat_f16x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = FmaFtzSatF16x2Op::build(ctx, arg0, arg1, arg2);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0856");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_ftz_sat_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
-        | "cuda_device::bf16x2::fma_relu_bf16x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = FmaReluBf16x2Op::build(ctx, arg0, arg1, arg2);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0063");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_relu_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
-        | "cuda_device::f16x2::fma_relu_f16x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = FmaReluF16x2Op::build(ctx, arg0, arg1, arg2);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0073");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_relu_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
-        | "cuda_device::f16x2::fma_sat_f16x2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = FmaSatF16x2Op::build(ctx, arg0, arg1, arg2);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0855");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_sat_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
-        | "cuda_device::bf16x2::max_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MaxBf16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0068");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
-        | "cuda_device::f16x2::max_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MaxF16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0078");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
-        | "cuda_device::bf16x2::min_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MinBf16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0067");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
-        | "cuda_device::f16x2::min_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MinF16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0077");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
-        | "cuda_device::bf16x2::mul_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MulBf16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0066");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
-        | "cuda_device::f16x2::mul_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MulF16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0076");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
-        | "cuda_device::f32x2::mul_f32x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MulF32x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0999");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_f32x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
-        | "cuda_device::f32x2::mul_ftz_f32x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MulFtzF32x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1000");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_ftz_f32x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
-        | "cuda_device::bf16x2::neg_bf16x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = NegBf16x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0069");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "neg_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
-        | "cuda_device::f16x2::neg_f16x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = NegF16x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0079");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "neg_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
-        | "cuda_device::bf16x2::sub_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = SubBf16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0065");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sub_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
-        | "cuda_device::f16x2::sub_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = SubF16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0075");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sub_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
-        | "cuda_device::f32x2::sub_f32x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = SubF32x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0997");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sub_f32x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
-        | "cuda_device::f32x2::sub_ftz_f32x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = SubFtzF32x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0998");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sub_ftz_f32x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
-        | "cuda_device::i16x2::max_relu_s16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MaxReluS16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0994");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_relu_s16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
-        | "cuda_device::int::max_relu_s32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MaxReluS32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0988");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_relu_s32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
-        | "cuda_device::i16x2::max_s16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MaxS16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0990");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_s16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
-        | "cuda_device::i16x2::max_u16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MaxU16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0992");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_u16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
-        | "cuda_device::i16x2::min_relu_s16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MinReluS16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0993");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_relu_s16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
-        | "cuda_device::int::min_relu_s32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MinReluS32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0987");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_relu_s32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
-        | "cuda_device::i16x2::min_s16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MinS16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0989");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_s16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
-        | "cuda_device::i16x2::min_u16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MinU16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0991");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_u16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
-        | "cuda_device::convert::cvt_f16x2_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtF16x2F32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0081");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_f16x2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
-        | "cuda_device::convert::cvt_bf16x2_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtF32x2Bf16x2Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0071");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_f32x2_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
-        | "cuda_device::convert::cvt_rn_f16x2_e4m3x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnF16x2E4m3x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0826");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_f16x2_e4m3x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
-        | "cuda_device::convert::cvt_rn_f16x2_e5m2x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnF16x2E5m2x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0828");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_f16x2_e5m2x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
-        | "cuda_device::convert::cvt_rn_relu_bf16x2_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnReluBf16x2F32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0084");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_relu_bf16x2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
-        | "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnReluF16x2E4m3x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0827");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_relu_f16x2_e4m3x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
-        | "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnReluF16x2E5m2x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0829");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_relu_f16x2_e5m2x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
-        | "cuda_device::convert::cvt_rn_relu_f16x2_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnReluF16x2F32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0083");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_relu_f16x2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
-        | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnSatfiniteE4m3x2F16x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0822");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_satfinite_e4m3x2_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
-        | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnSatfiniteE4m3x2F32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0259");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_satfinite_e4m3x2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
-        | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnSatfiniteE5m2x2F16x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0824");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_satfinite_e5m2x2_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
-        | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnSatfiniteE5m2x2F32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0261");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_satfinite_e5m2x2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
-        | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnSatfiniteReluE4m3x2F16x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0823");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_satfinite_relu_e4m3x2_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
-        | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnSatfiniteReluE4m3x2F32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0260");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_satfinite_relu_e4m3x2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
-        | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnSatfiniteReluE5m2x2F16x2Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0825");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_satfinite_relu_e5m2x2_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
-        | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRnSatfiniteReluE5m2x2F32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0262");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_satfinite_relu_e5m2x2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
-        | "cuda_device::convert::cvt_rz_bf16x2_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRzBf16x2F32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0085");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rz_bf16x2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
-        | "cuda_device::convert::cvt_rz_f16x2_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = CvtRzF16x2F32Op::build(ctx, arg0, arg1);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0082");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rz_f16x2_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
-        | "cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarConversionOp::build(
-                ctx,
-                value,
-                ScalarConversionRoundingAttr::NearestEven,
-                ScalarConversionSaturationAttr::ReluSatfinite,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0373");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_relu_satfinite_tf32_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
-        | "cuda_device::convert::cvt_rn_relu_tf32_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarConversionOp::build(
-                ctx,
-                value,
-                ScalarConversionRoundingAttr::NearestEven,
-                ScalarConversionSaturationAttr::Relu,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0371");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_relu_tf32_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
-        | "cuda_device::convert::cvt_rn_satfinite_tf32_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarConversionOp::build(
-                ctx,
-                value,
-                ScalarConversionRoundingAttr::NearestEven,
-                ScalarConversionSaturationAttr::Satfinite,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0372");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_satfinite_tf32_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
-        | "cuda_device::convert::cvt_rn_tf32_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarConversionOp::build(
-                ctx,
-                value,
-                ScalarConversionRoundingAttr::NearestEven,
-                ScalarConversionSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0370");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rn_tf32_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
-        | "cuda_device::convert::cvt_rna_satfinite_tf32_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarConversionOp::build(
-                ctx,
-                value,
-                ScalarConversionRoundingAttr::NearestAway,
-                ScalarConversionSaturationAttr::Satfinite,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0369");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rna_satfinite_tf32_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
-        | "cuda_device::convert::cvt_rna_tf32_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarConversionOp::build(
-                ctx,
-                value,
-                ScalarConversionRoundingAttr::NearestAway,
-                ScalarConversionSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0368");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rna_tf32_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
-        | "cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarConversionOp::build(
-                ctx,
-                value,
-                ScalarConversionRoundingAttr::TowardZero,
-                ScalarConversionSaturationAttr::ReluSatfinite,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0377");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rz_relu_satfinite_tf32_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
-        | "cuda_device::convert::cvt_rz_relu_tf32_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarConversionOp::build(
-                ctx,
-                value,
-                ScalarConversionRoundingAttr::TowardZero,
-                ScalarConversionSaturationAttr::Relu,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0375");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rz_relu_tf32_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
-        | "cuda_device::convert::cvt_rz_satfinite_tf32_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarConversionOp::build(
-                ctx,
-                value,
-                ScalarConversionRoundingAttr::TowardZero,
-                ScalarConversionSaturationAttr::Satfinite,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0376");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rz_satfinite_tf32_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
-        | "cuda_device::convert::cvt_rz_tf32_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarConversionOp::build(
-                ctx,
-                value,
-                ScalarConversionRoundingAttr::TowardZero,
-                ScalarConversionSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0374");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cvt_rz_tf32_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
-        | "cuda_device::float::add_rm_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0446");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rm_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
-        | "cuda_device::float::add_rm_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0436");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rm_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
-        | "cuda_device::float::add_rm_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0447");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rm_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
-        | "cuda_device::float::add_rm_ftz_sat_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0449");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rm_ftz_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
-        | "cuda_device::float::add_rm_sat_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0448");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rm_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
-        | "cuda_device::float::add_rn_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0438");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rn_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
-        | "cuda_device::float::add_rn_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0434");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rn_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
-        | "cuda_device::float::add_rn_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0439");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rn_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
-        | "cuda_device::float::add_rn_ftz_sat_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0441");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rn_ftz_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
-        | "cuda_device::float::add_rn_sat_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0440");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rn_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
-        | "cuda_device::float::add_rp_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0450");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rp_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
-        | "cuda_device::float::add_rp_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0437");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rp_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
-        | "cuda_device::float::add_rp_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0451");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rp_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
-        | "cuda_device::float::add_rp_ftz_sat_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0453");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rp_ftz_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
-        | "cuda_device::float::add_rp_sat_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0452");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rp_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
-        | "cuda_device::float::add_rz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0442");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
-        | "cuda_device::float::add_rz_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0435");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rz_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
-        | "cuda_device::float::add_rz_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0443");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rz_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
-        | "cuda_device::float::add_rz_ftz_sat_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0445");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rz_ftz_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
-        | "cuda_device::float::add_rz_sat_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Add,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0444");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "add_rz_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
-        | "cuda_device::float::div_rm_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0414");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rm_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
-        | "cuda_device::float::div_rm_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0396");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rm_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
-        | "cuda_device::float::div_rm_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0415");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rm_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
-        | "cuda_device::float::div_rn_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0410");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rn_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
-        | "cuda_device::float::div_rn_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0394");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rn_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
-        | "cuda_device::float::div_rn_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0411");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rn_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
-        | "cuda_device::float::div_rp_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0416");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rp_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
-        | "cuda_device::float::div_rp_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0397");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rp_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
-        | "cuda_device::float::div_rp_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0417");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rp_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
-        | "cuda_device::float::div_rz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0412");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
-        | "cuda_device::float::div_rz_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0395");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rz_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
-        | "cuda_device::float::div_rz_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Div,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0413");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "div_rz_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
-        | "cuda_device::float::fma_rm_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0426");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rm_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
-        | "cuda_device::float::fma_rm_f64" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0400");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rm_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
-        | "cuda_device::float::fma_rm_ftz_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0427");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rm_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
-        | "cuda_device::float::fma_rm_ftz_sat_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0429");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rm_ftz_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
-        | "cuda_device::float::fma_rm_sat_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0428");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rm_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
-        | "cuda_device::float::fma_rn_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0418");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rn_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
-        | "cuda_device::float::fma_rn_f64" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0398");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rn_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
-        | "cuda_device::float::fma_rn_ftz_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0419");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rn_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
-        | "cuda_device::float::fma_rn_ftz_sat_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0421");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rn_ftz_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
-        | "cuda_device::float::fma_rn_sat_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0420");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rn_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
-        | "cuda_device::float::fma_rp_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0430");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rp_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
-        | "cuda_device::float::fma_rp_f64" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0401");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rp_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
-        | "cuda_device::float::fma_rp_ftz_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0431");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rp_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
-        | "cuda_device::float::fma_rp_ftz_sat_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0433");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rp_ftz_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
-        | "cuda_device::float::fma_rp_sat_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0432");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rp_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
-        | "cuda_device::float::fma_rz_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0422");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
-        | "cuda_device::float::fma_rz_f64" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0399");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rz_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
-        | "cuda_device::float::fma_rz_ftz_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0423");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rz_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
-        | "cuda_device::float::fma_rz_ftz_sat_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0425");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rz_ftz_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
-        | "cuda_device::float::fma_rz_sat_f32" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1, arg2],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Fma,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::Sat,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0424");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "fma_rz_sat_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
-        | "cuda_device::float::mul_rm_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0406");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rm_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
-        | "cuda_device::float::mul_rm_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0392");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rm_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
-        | "cuda_device::float::mul_rm_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rm,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0407");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rm_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
-        | "cuda_device::float::mul_rn_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0402");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rn_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
-        | "cuda_device::float::mul_rn_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0390");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rn_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
-        | "cuda_device::float::mul_rn_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rn,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0403");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rn_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
-        | "cuda_device::float::mul_rp_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0408");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rp_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
-        | "cuda_device::float::mul_rp_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0393");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rp_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
-        | "cuda_device::float::mul_rp_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rp,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0409");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rp_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
-        | "cuda_device::float::mul_rz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0404");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
-        | "cuda_device::float::mul_rz_f64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F64,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Preserve,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0391");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rz_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
-        | "cuda_device::float::mul_rz_ftz_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarArithmeticOp::build(
-                ctx,
-                vec![arg0, arg1],
-                ScalarArithmeticFormatAttr::F32,
-                ScalarArithmeticOperationAttr::Mul,
-                ScalarArithmeticRoundingAttr::Rz,
-                ScalarArithmeticSubnormalAttr::Ftz,
-                ScalarArithmeticSaturationAttr::None,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0405");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "mul_rz_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
-        | "cuda_device::float::cos_approx_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Cos,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0784");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cos_approx_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
-        | "cuda_device::float::cos_approx_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Cos,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0785");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "cos_approx_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
-        | "cuda_device::float::ex2_approx_f16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F16,
-                ScalarMathOperationAttr::Ex2,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1016");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "ex2_approx_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
-        | "cuda_device::float::ex2_approx_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Ex2,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0819");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "ex2_approx_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
-        | "cuda_device::float::ex2_approx_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Ex2,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0820");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "ex2_approx_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
-        | "cuda_device::float::lg2_approx_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Lg2,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0786");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "lg2_approx_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
-        | "cuda_device::float::lg2_approx_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Lg2,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0787");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "lg2_approx_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
-        | "cuda_device::float::rcp_approx_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0788");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_approx_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
-        | "cuda_device::float::rcp_approx_ftz_f64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F64,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0797");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_approx_ftz_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
-        | "cuda_device::float::rcp_rm_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rm,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0793");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rm_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
-        | "cuda_device::float::rcp_rm_f64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F64,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rm,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0800");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rm_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
-        | "cuda_device::float::rcp_rm_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rm,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0794");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rm_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
-        | "cuda_device::float::rcp_rn_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rn,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0789");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rn_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
-        | "cuda_device::float::rcp_rn_f64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F64,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rn,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0798");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rn_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
-        | "cuda_device::float::rcp_rn_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rn,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0790");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rn_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
-        | "cuda_device::float::rcp_rp_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rp,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0795");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rp_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
-        | "cuda_device::float::rcp_rp_f64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F64,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rp,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0801");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rp_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
-        | "cuda_device::float::rcp_rp_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rp,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0796");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rp_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
-        | "cuda_device::float::rcp_rz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rz,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0791");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
-        | "cuda_device::float::rcp_rz_f64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F64,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rz,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0799");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rz_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
-        | "cuda_device::float::rcp_rz_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rcp,
-                ScalarMathPrecisionAttr::Rz,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0792");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rcp_rz_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
-        | "cuda_device::float::rsqrt_approx_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rsqrt,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0802");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rsqrt_approx_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
-        | "cuda_device::float::rsqrt_approx_f64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F64,
-                ScalarMathOperationAttr::Rsqrt,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0804");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rsqrt_approx_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
-        | "cuda_device::float::rsqrt_approx_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Rsqrt,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0803");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "rsqrt_approx_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
-        | "cuda_device::float::sin_approx_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sin,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0782");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sin_approx_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
-        | "cuda_device::float::sin_approx_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sin,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0783");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sin_approx_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
-        | "cuda_device::float::sqrt_approx_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0805");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_approx_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
-        | "cuda_device::float::sqrt_approx_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0806");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_approx_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
-        | "cuda_device::float::sqrt_rm_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rm,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0811");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rm_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
-        | "cuda_device::float::sqrt_rm_f64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F64,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rm,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0817");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rm_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
-        | "cuda_device::float::sqrt_rm_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rm,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0812");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rm_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
-        | "cuda_device::float::sqrt_rn_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rn,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0807");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rn_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
-        | "cuda_device::float::sqrt_rn_f64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F64,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rn,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0815");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rn_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
-        | "cuda_device::float::sqrt_rn_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rn,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0808");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rn_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
-        | "cuda_device::float::sqrt_rp_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rp,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0813");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rp_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
-        | "cuda_device::float::sqrt_rp_f64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F64,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rp,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0818");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rp_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
-        | "cuda_device::float::sqrt_rp_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rp,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0814");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rp_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
-        | "cuda_device::float::sqrt_rz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rz,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0809");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
-        | "cuda_device::float::sqrt_rz_f64" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F64,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rz,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0816");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rz_f64 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
-        | "cuda_device::float::sqrt_rz_ftz_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Sqrt,
-                ScalarMathPrecisionAttr::Rz,
-                ScalarMathSubnormalAttr::Ftz,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0810");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "sqrt_rz_ftz_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
-        | "cuda_device::float::tanh_approx_f32" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ScalarMathOp::build(
-                ctx,
-                arg0,
-                ScalarMathFormatAttr::F32,
-                ScalarMathOperationAttr::Tanh,
-                ScalarMathPrecisionAttr::Approx,
-                ScalarMathSubnormalAttr::Preserve,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0821");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "tanh_approx_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850" | "cuda_device::bf16::max_bf16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0850");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_bf16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842" | "cuda_device::f16::max_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0842");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
-        | "cuda_device::f16::max_ftz_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0843");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_ftz_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
-        | "cuda_device::f16x2::max_ftz_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0564");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_ftz_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
-        | "cuda_device::f16::max_ftz_nan_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0845");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_ftz_nan_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
-        | "cuda_device::f16x2::max_ftz_nan_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0565");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_ftz_nan_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
-        | "cuda_device::f16::max_ftz_nan_xorsign_abs_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0849");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_ftz_nan_xorsign_abs_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
-        | "cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0567");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_ftz_nan_xorsign_abs_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
-        | "cuda_device::float::max_ftz_nan_xorsign_abs_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F32,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0566");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_ftz_nan_xorsign_abs_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
-        | "cuda_device::f16::max_ftz_xorsign_abs_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0847");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_ftz_xorsign_abs_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
-        | "cuda_device::f16x2::max_ftz_xorsign_abs_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0569");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_ftz_xorsign_abs_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
-        | "cuda_device::float::max_ftz_xorsign_abs_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F32,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0568");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_ftz_xorsign_abs_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
-        | "cuda_device::bf16::max_nan_bf16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0851");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_nan_bf16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
-        | "cuda_device::bf16x2::max_nan_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16x2,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0570");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_nan_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
-        | "cuda_device::f16::max_nan_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0844");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_nan_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
-        | "cuda_device::f16x2::max_nan_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0571");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_nan_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
-        | "cuda_device::bf16::max_nan_xorsign_abs_bf16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0853");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_nan_xorsign_abs_bf16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
-        | "cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16x2,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0572");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_nan_xorsign_abs_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
-        | "cuda_device::f16::max_nan_xorsign_abs_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0848");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_nan_xorsign_abs_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
-        | "cuda_device::f16x2::max_nan_xorsign_abs_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0574");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_nan_xorsign_abs_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
-        | "cuda_device::float::max_nan_xorsign_abs_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F32,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0573");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_nan_xorsign_abs_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
-        | "cuda_device::bf16::max_xorsign_abs_bf16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0852");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_xorsign_abs_bf16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
-        | "cuda_device::bf16x2::max_xorsign_abs_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16x2,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0575");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_xorsign_abs_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
-        | "cuda_device::f16::max_xorsign_abs_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0846");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_xorsign_abs_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
-        | "cuda_device::f16x2::max_xorsign_abs_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0577");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_xorsign_abs_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
-        | "cuda_device::float::max_xorsign_abs_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F32,
-                ExtendedMinMaxOperationAttr::Max,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0576");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "max_xorsign_abs_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838" | "cuda_device::bf16::min_bf16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0838");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_bf16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830" | "cuda_device::f16::min_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0830");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
-        | "cuda_device::f16::min_ftz_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0831");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_ftz_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
-        | "cuda_device::f16x2::min_ftz_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0550");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_ftz_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
-        | "cuda_device::f16::min_ftz_nan_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0833");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_ftz_nan_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
-        | "cuda_device::f16x2::min_ftz_nan_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0551");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_ftz_nan_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
-        | "cuda_device::f16::min_ftz_nan_xorsign_abs_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0837");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_ftz_nan_xorsign_abs_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
-        | "cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0553");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_ftz_nan_xorsign_abs_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
-        | "cuda_device::float::min_ftz_nan_xorsign_abs_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F32,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0552");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_ftz_nan_xorsign_abs_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
-        | "cuda_device::f16::min_ftz_xorsign_abs_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0835");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_ftz_xorsign_abs_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
-        | "cuda_device::f16x2::min_ftz_xorsign_abs_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0555");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_ftz_xorsign_abs_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
-        | "cuda_device::float::min_ftz_xorsign_abs_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F32,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Ftz,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0554");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_ftz_xorsign_abs_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
-        | "cuda_device::bf16::min_nan_bf16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0839");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_nan_bf16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
-        | "cuda_device::bf16x2::min_nan_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16x2,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0556");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_nan_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
-        | "cuda_device::f16::min_nan_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0832");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_nan_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
-        | "cuda_device::f16x2::min_nan_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Disabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0557");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_nan_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
-        | "cuda_device::bf16::min_nan_xorsign_abs_bf16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0841");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_nan_xorsign_abs_bf16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
-        | "cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16x2,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0558");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_nan_xorsign_abs_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
-        | "cuda_device::f16::min_nan_xorsign_abs_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0836");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_nan_xorsign_abs_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
-        | "cuda_device::f16x2::min_nan_xorsign_abs_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0560");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_nan_xorsign_abs_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
-        | "cuda_device::float::min_nan_xorsign_abs_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F32,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Nan,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0559");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_nan_xorsign_abs_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
-        | "cuda_device::bf16::min_xorsign_abs_bf16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0840");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_xorsign_abs_bf16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
-        | "cuda_device::bf16x2::min_xorsign_abs_bf16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::Bf16x2,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0561");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_xorsign_abs_bf16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
-        | "cuda_device::f16::min_xorsign_abs_f16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0834");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_xorsign_abs_f16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
-        | "cuda_device::f16x2::min_xorsign_abs_f16x2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F16x2,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0563");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_xorsign_abs_f16x2 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
-        | "cuda_device::float::min_xorsign_abs_f32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (a, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (b, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = ExtendedMinMaxOp::build(
-                ctx,
-                a,
-                b,
-                ExtendedMinMaxFormatAttr::F32,
-                ExtendedMinMaxOperationAttr::Min,
-                ExtendedMinMaxSubnormalAttr::Preserve,
-                ExtendedMinMaxNanAttr::Number,
-                ExtendedMinMaxXorSignAbsAttr::Enabled,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0562");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "min_xorsign_abs_f32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
-        | "cuda_device::wmma::movmatrix_trans_b16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let intrinsic = MovmatrixTransB16Op::build(ctx, arg0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0305");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "movmatrix_trans_b16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252" | "cuda_device::prmt::prmt" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let prmt = PrmtOp::build(ctx, vec![arg0, arg1, arg2], PrmtModeAttr::Generic);
-            prmt.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0252");
-            helpers::insert_op(ctx, prmt, block_ptr, last_op);
-            let result = prmt.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                prmt,
-                value_map,
-                block_map,
-                loc,
-                "prmt call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254" | "cuda_device::prmt::prmt_b4e" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let prmt = PrmtOp::build(ctx, vec![arg0, arg1, arg2], PrmtModeAttr::B4e);
-            prmt.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0254");
-            helpers::insert_op(ctx, prmt, block_ptr, last_op);
-            let result = prmt.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                prmt,
-                value_map,
-                block_map,
-                loc,
-                "prmt_b4e call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256" | "cuda_device::prmt::prmt_ecl" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let prmt = PrmtOp::build(ctx, vec![arg0, arg1], PrmtModeAttr::Ecl);
-            prmt.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0256");
-            helpers::insert_op(ctx, prmt, block_ptr, last_op);
-            let result = prmt.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                prmt,
-                value_map,
-                block_map,
-                loc,
-                "prmt_ecl call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257" | "cuda_device::prmt::prmt_ecr" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let prmt = PrmtOp::build(ctx, vec![arg0, arg1], PrmtModeAttr::Ecr);
-            prmt.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0257");
-            helpers::insert_op(ctx, prmt, block_ptr, last_op);
-            let result = prmt.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                prmt,
-                value_map,
-                block_map,
-                loc,
-                "prmt_ecr call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253" | "cuda_device::prmt::prmt_f4e" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (arg2, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let prmt = PrmtOp::build(ctx, vec![arg0, arg1, arg2], PrmtModeAttr::F4e);
-            prmt.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0253");
-            helpers::insert_op(ctx, prmt, block_ptr, last_op);
-            let result = prmt.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                prmt,
-                value_map,
-                block_map,
-                loc,
-                "prmt_f4e call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
-        | "cuda_device::prmt::prmt_rc16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let prmt = PrmtOp::build(ctx, vec![arg0, arg1], PrmtModeAttr::Rc16);
-            prmt.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0258");
-            helpers::insert_op(ctx, prmt, block_ptr, last_op);
-            let result = prmt.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                prmt,
-                value_map,
-                block_map,
-                loc,
-                "prmt_rc16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255" | "cuda_device::prmt::prmt_rc8" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let prmt = PrmtOp::build(ctx, vec![arg0, arg1], PrmtModeAttr::Rc8);
-            prmt.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0255");
-            helpers::insert_op(ctx, prmt, block_ptr, last_op);
-            let result = prmt.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                prmt,
-                value_map,
-                block_map,
-                loc,
-                "prmt_rc8 call without target block",
-            )?))
-        }
-        "cuda_device::cluster::cluster_sync" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let arrive = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::ArriveAligned);
-            arrive.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, arrive, "v1:i0278");
-            helpers::insert_op(ctx, arrive, block_ptr, prev_op);
-            let wait = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::WaitAligned);
-            wait.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, wait, "v1:i0282");
-            helpers::insert_op(ctx, wait, block_ptr, Some(arrive));
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    wait,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cluster_sync call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
-        | "cuda_device::cluster::barrier_cluster_arrive" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let barrier = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::Arrive);
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0277");
-            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "barrier_cluster_arrive call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
-        | "cuda_device::cluster::barrier_cluster_arrive_aligned" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let barrier = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::ArriveAligned);
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0278");
-            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "barrier_cluster_arrive_aligned call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
-        | "cuda_device::cluster::barrier_cluster_arrive_relaxed" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let barrier = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::ArriveRelaxed);
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0279");
-            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "barrier_cluster_arrive_relaxed call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
-        | "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let barrier =
-                ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::ArriveRelaxedAligned);
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0280");
-            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "barrier_cluster_arrive_relaxed_aligned call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
-        | "cuda_device::cluster::barrier_cluster_wait" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let barrier = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::Wait);
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0281");
-            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "barrier_cluster_wait call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
-        | "cuda_device::cluster::barrier_cluster_wait_aligned" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let barrier = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::WaitAligned);
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0282");
-            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "barrier_cluster_wait_aligned call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
-        | "cuda_device::cluster::dsmem_read_u32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (source, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (rank, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let cluster = DsmemReadU32Op::build(ctx, source, rank);
-            cluster.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, cluster, "v1:i0321");
-            helpers::insert_op(ctx, cluster, block_ptr, last_op);
-            let result = cluster.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                cluster,
-                value_map,
-                block_map,
-                loc,
-                "dsmem_read_u32 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
-        | "cuda_device::cluster::map_shared_rank"
-        | "cuda_device::cluster::map_shared_rank_mut" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (source, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (rank, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let cluster = MapaSharedClusterOp::build(ctx, source, rank);
-            cluster.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, cluster, "v1:i0320");
-            helpers::insert_op(ctx, cluster, block_ptr, last_op);
-            let result = cluster.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                cluster,
-                value_map,
-                block_map,
-                loc,
-                "map_shared_rank call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
-        | "cuda_device::debug::breakpoint" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let debug = BreakpointOp::build(ctx);
-            debug.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, debug, "v1:i0296");
-            helpers::insert_op(ctx, debug, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    debug,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported("breakpoint call without target block".to_owned())
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
-        | "cuda_device::debug::__prof_trigger" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            if !matches!(&args[0], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "prof_trigger requires a compile-time constant event ID in 0..=15"
-                            .to_owned()
-                    )
-                );
-            }
-            let (event_id_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let event_id = event_id_value
-                .defining_op()
-                .and_then(|defining_op| Operation::get_op::<MirConstantOp>(defining_op, ctx))
-                .and_then(|constant| constant.get_attr_value(ctx))
-                .map(|value| value.value().to_u64())
-                .and_then(|value| u32::try_from(value).ok())
-                .filter(|value| *value <= 15);
-            let Some(event_id) = event_id else {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "prof_trigger requires a compile-time constant event ID in 0..=15"
-                            .to_owned()
-                    )
-                );
-            };
-            let debug = PmEventOp::build(ctx, event_id);
-            debug.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, debug, "v1:i0297");
-            helpers::insert_op(ctx, debug, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    debug,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported("pmevent call without target block".to_owned())
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295" | "cuda_device::debug::trap" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let debug = TrapOp::build(ctx);
-            debug.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, debug, "v1:i0295");
-            helpers::insert_op(ctx, debug, block_ptr, prev_op);
-            let unreachable = Operation::new(
-                ctx,
-                MirUnreachableOp::get_concrete_op_info(),
-                vec![],
-                vec![],
-                vec![],
-                0,
-            );
-            unreachable.deref_mut(ctx).set_loc(loc);
-            helpers::insert_op(ctx, unreachable, block_ptr, Some(debug));
-            Ok(Some(unreachable))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
-        | "cuda_device::clc::clc_query_get_first_ctaid_x" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                ClcQueryGetFirstCtaidXOp::get_concrete_op_info(),
-                vec![
-                    pliron::builtin::types::IntegerType::get(
-                        ctx,
-                        32,
-                        pliron::builtin::types::Signedness::Unsigned,
-                    )
-                    .into(),
-                ],
-                vec![arg0, arg1],
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0325");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "clc_query_get_first_ctaid_x call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
-        | "cuda_device::clc::clc_query_get_first_ctaid_y" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                ClcQueryGetFirstCtaidYOp::get_concrete_op_info(),
-                vec![
-                    pliron::builtin::types::IntegerType::get(
-                        ctx,
-                        32,
-                        pliron::builtin::types::Signedness::Unsigned,
-                    )
-                    .into(),
-                ],
-                vec![arg0, arg1],
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0326");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "clc_query_get_first_ctaid_y call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
-        | "cuda_device::clc::clc_query_get_first_ctaid_z" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                ClcQueryGetFirstCtaidZOp::get_concrete_op_info(),
-                vec![
-                    pliron::builtin::types::IntegerType::get(
-                        ctx,
-                        32,
-                        pliron::builtin::types::Signedness::Unsigned,
-                    )
-                    .into(),
-                ],
-                vec![arg0, arg1],
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0327");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "clc_query_get_first_ctaid_z call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
-        | "cuda_device::clc::clc_query_is_canceled" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                ClcQueryIsCanceledOp::get_concrete_op_info(),
-                vec![
-                    pliron::builtin::types::IntegerType::get(
-                        ctx,
-                        32,
-                        pliron::builtin::types::Signedness::Unsigned,
-                    )
-                    .into(),
-                ],
-                vec![arg0, arg1],
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0324");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                intrinsic,
-                value_map,
-                block_map,
-                loc,
-                "clc_query_is_canceled call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
-        | "cuda_device::clc::clc_try_cancel" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                ClcTryCancelOp::get_concrete_op_info(),
-                vec![],
-                vec![arg0, arg1],
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0322");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "clc_try_cancel call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
-        | "cuda_device::clc::clc_try_cancel_multicast" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (arg0, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (arg1, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                ClcTryCancelMulticastOp::get_concrete_op_info(),
-                vec![],
-                vec![arg0, arg1],
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0323");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "clc_try_cancel_multicast call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
-        | "cuda_device::wgmma::wgmma_commit_group" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let control = WgmmaCommitGroupSyncAlignedOp::build(ctx);
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0318");
-            helpers::insert_op(ctx, control, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "wgmma_commit_group call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
-        | "cuda_device::wgmma::wgmma_fence" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let control = WgmmaFenceSyncAlignedOp::build(ctx);
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0317");
-            helpers::insert_op(ctx, control, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported("wgmma_fence call without target block".to_owned())
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
-        | "cuda_device::wgmma::__wgmma_wait_group" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            if !matches!(&args[0], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "wgmma_wait_group requires a compile-time constant".to_owned()
-                    )
-                );
-            }
-            let (max_pending, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            if max_pending
-                .defining_op()
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "wgmma_wait_group requires a compile-time constant".to_owned()
-                    )
-                );
-            }
-            let control = WgmmaWaitGroupSyncAlignedOp::build(ctx, max_pending);
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0319");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "wgmma_wait_group call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
-        | "cuda_device::async_copy::cp_async_ca_16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (shared_dst, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (global_src, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let copy = CpAsyncCa16Op::build(ctx, shared_dst, global_src);
-            copy.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0090");
-            helpers::insert_op(ctx, copy, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    copy,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_ca_16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
-        | "cuda_device::async_copy::cp_async_ca_4" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (shared_dst, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (global_src, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let copy = CpAsyncCa4Op::build(ctx, shared_dst, global_src);
-            copy.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0086");
-            helpers::insert_op(ctx, copy, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    copy,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_ca_4 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
-        | "cuda_device::async_copy::cp_async_ca_8" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (shared_dst, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (global_src, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let copy = CpAsyncCa8Op::build(ctx, shared_dst, global_src);
-            copy.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0088");
-            helpers::insert_op(ctx, copy, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    copy,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_ca_8 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
-        | "cuda_device::async_copy::cp_async_ca_zfill_16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (shared_dst, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (global_src, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (source_size, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let copy = CpAsyncCaZfill16Op::build(ctx, shared_dst, global_src, source_size);
-            copy.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0091");
-            helpers::insert_op(ctx, copy, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    copy,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_ca_zfill_16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
-        | "cuda_device::async_copy::cp_async_ca_zfill_4" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (shared_dst, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (global_src, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (source_size, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let copy = CpAsyncCaZfill4Op::build(ctx, shared_dst, global_src, source_size);
-            copy.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0087");
-            helpers::insert_op(ctx, copy, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    copy,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_ca_zfill_4 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
-        | "cuda_device::async_copy::cp_async_ca_zfill_8" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (shared_dst, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (global_src, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (source_size, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let copy = CpAsyncCaZfill8Op::build(ctx, shared_dst, global_src, source_size);
-            copy.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0089");
-            helpers::insert_op(ctx, copy, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    copy,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_ca_zfill_8 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
-        | "cuda_device::async_copy::cp_async_cg_16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (shared_dst, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (global_src, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let copy = CpAsyncCg16Op::build(ctx, shared_dst, global_src);
-            copy.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0092");
-            helpers::insert_op(ctx, copy, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    copy,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_cg_16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
-        | "cuda_device::async_copy::cp_async_cg_zfill_16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (shared_dst, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (global_src, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let (source_size, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let copy = CpAsyncCgZfill16Op::build(ctx, shared_dst, global_src, source_size);
-            copy.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0093");
-            helpers::insert_op(ctx, copy, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    copy,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_cg_zfill_16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
-        | "cuda_device::async_copy::cp_async_commit_group" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let last_op = prev_op;
-            let control = CpAsyncCommitGroupOp::build(ctx);
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0094");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_commit_group call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
-        | "cuda_device::async_copy::cp_async_wait_all" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let last_op = prev_op;
-            let control = CpAsyncWaitAllOp::build(ctx);
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0095");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_wait_all call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
-        | "cuda_device::async_copy::cp_async_wait_group" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            if !matches!(&args[0], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_wait_group requires a compile-time constant max_pending value"
-                            .to_owned()
-                    )
-                );
-            }
-            let (max_pending, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let control = CpAsyncWaitGroupOp::build(ctx, max_pending);
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0096");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_wait_group call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
-        | "cuda_device::async_copy::cp_async_mbarrier_arrive" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let bridge = CpAsyncMbarrierArriveOp::build(ctx, barrier);
-            bridge.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, bridge, "v1:i0101");
-            helpers::insert_op(ctx, bridge, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    bridge,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_mbarrier_arrive call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
-        | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let bridge = CpAsyncMbarrierArriveNoIncOp::build(ctx, barrier);
-            bridge.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, bridge, "v1:i0103");
-            helpers::insert_op(ctx, bridge, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    bridge,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_mbarrier_arrive_noinc call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
-        | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let bridge = CpAsyncMbarrierArriveNoIncSharedOp::build(ctx, barrier);
-            bridge.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, bridge, "v1:i0104");
-            helpers::insert_op(ctx, bridge, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    bridge,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_mbarrier_arrive_noinc_shared call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
-        | "cuda_device::async_copy::cp_async_mbarrier_arrive_shared" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let bridge = CpAsyncMbarrierArriveSharedOp::build(ctx, barrier);
-            bridge.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, bridge, "v1:i0102");
-            helpers::insert_op(ctx, bridge, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    bridge,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_mbarrier_arrive_shared call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
-        | "cuda_device::barrier::mbarrier_arrive" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let mbarrier = MbarrierArriveSharedOp::build(ctx, barrier);
-            mbarrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, mbarrier, "v1:i0098");
-            helpers::insert_op(ctx, mbarrier, block_ptr, last_op);
-            let result = mbarrier.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                mbarrier,
-                value_map,
-                block_map,
-                loc,
-                "mbarrier_arrive call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
-        | "cuda_device::barrier::mbarrier_init" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (expected_count, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let mbarrier = MbarrierInitSharedOp::build(ctx, barrier, expected_count);
-            mbarrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, mbarrier, "v1:i0097");
-            helpers::insert_op(ctx, mbarrier, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    mbarrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "mbarrier_init call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
-        | "cuda_device::barrier::mbarrier_inval" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let mbarrier = MbarrierInvalSharedOp::build(ctx, barrier);
-            mbarrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, mbarrier, "v1:i0100");
-            helpers::insert_op(ctx, mbarrier, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    mbarrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "mbarrier_inval call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
-        | "cuda_device::barrier::mbarrier_test_wait" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (token, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let mbarrier = MbarrierTestWaitSharedOp::build(ctx, barrier, token);
-            mbarrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, mbarrier, "v1:i0099");
-            helpers::insert_op(ctx, mbarrier, block_ptr, last_op);
-            let result = mbarrier.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                mbarrier,
-                value_map,
-                block_map,
-                loc,
-                "mbarrier_test_wait call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
-        | "cuda_device::barrier::fence_mbarrier_init_release_cluster" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let last_op = prev_op;
-            let extended = FenceMbarrierInitReleaseClusterOp::build(ctx);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0313");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    extended,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "fence_mbarrier_init_release_cluster call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
-        | "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let last_op = prev_op;
-            let extended = FenceProxyAsyncGenericAcquireSharedClusterClusterOp::build(ctx);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0315");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    extended,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(loc, TranslationErr::unsupported("fence_proxy_async_generic_acquire_shared_cluster_cluster call without target block".to_owned()))
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
-        | "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let last_op = prev_op;
-            let extended = FenceProxyAsyncGenericReleaseSharedCtaClusterOp::build(ctx);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0314");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    extended,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(loc, TranslationErr::unsupported("fence_proxy_async_generic_release_shared_cta_cluster call without target block".to_owned()))
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
-        | "cuda_device::barrier::fence_proxy_async_shared_cta" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let last_op = prev_op;
-            let extended = FenceProxyAsyncSharedCtaOp::build(ctx);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0312");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    extended,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "fence_proxy_async_shared_cta call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
-        | "cuda_device::barrier::mbarrier_arrive_cluster" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (address, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let extended = MbarrierArriveClusterOp::build(ctx, address);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0308");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    extended,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "mbarrier_arrive_cluster call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
-        | "cuda_device::barrier::mbarrier_arrive_expect_tx" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (bytes, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let extended = MbarrierArriveExpectTxSharedOp::build(ctx, barrier, bytes);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0306");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            let result = extended.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                extended,
-                value_map,
-                block_map,
-                loc,
-                "mbarrier_arrive_expect_tx call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
-        | "cuda_device::barrier::mbarrier_arrive_expect_tx_cluster" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (bytes, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[2],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let extended = MbarrierArriveExpectTxClusterOp::build(ctx, barrier, bytes);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0307");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            let result = extended.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                extended,
-                value_map,
-                block_map,
-                loc,
-                "mbarrier_arrive_expect_tx_cluster call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
-        | "cuda_device::barrier::mbarrier_try_wait" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (token, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let extended = MbarrierTryWaitSharedOp::build(ctx, barrier, token);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0309");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            let result = extended.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                extended,
-                value_map,
-                block_map,
-                loc,
-                "mbarrier_try_wait call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
-        | "cuda_device::barrier::mbarrier_try_wait_parity" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (parity, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let extended = MbarrierTryWaitParitySharedOp::build(ctx, barrier, parity);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0310");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            let result = extended.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                extended,
-                value_map,
-                block_map,
-                loc,
-                "mbarrier_try_wait_parity call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
-        | "cuda_device::barrier::mbarrier_try_wait_parity_cluster" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (barrier, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let (parity, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[1],
-                value_map,
-                block_ptr,
-                last_op,
-                loc.clone(),
-            )?;
-            let extended = MbarrierTryWaitParityClusterOp::build(ctx, barrier, parity);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0311");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            let result = extended.deref(ctx).get_result(0);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                extended,
-                value_map,
-                block_map,
-                loc,
-                "mbarrier_try_wait_parity_cluster call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
-        | "cuda_device::barrier::nanosleep" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let (ns, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let extended = NanosleepOp::build(ctx, ns);
-            extended.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0316");
-            helpers::insert_op(ctx, extended, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    extended,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported("nanosleep call without target block".to_owned())
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
-        | "cuda_device::thread::sync_threads"
-        | "cuda_device::sync_threads" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let barrier = Operation::new(
-                ctx,
-                Barrier0Op::get_concrete_op_info(),
-                vec![],
-                vec![],
-                vec![],
-                0,
-            );
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0034");
-            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "sync_threads call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
-        | "cuda_device::fence::threadfence"
-        | "cuda_device::threadfence" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let barrier = Operation::new(
-                ctx,
-                ThreadfenceOp::get_concrete_op_info(),
-                vec![],
-                vec![],
-                vec![],
-                0,
-            );
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0299");
-            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported("threadfence call without target block".to_owned())
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
-        | "cuda_device::fence::threadfence_block"
-        | "cuda_device::threadfence_block" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let barrier = Operation::new(
-                ctx,
-                ThreadfenceBlockOp::get_concrete_op_info(),
-                vec![],
-                vec![],
-                vec![],
-                0,
-            );
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0298");
-            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "threadfence_block call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
-        | "cuda_device::fence::threadfence_system"
-        | "cuda_device::threadfence_system" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let barrier = Operation::new(
-                ctx,
-                ThreadfenceSystemOp::get_concrete_op_info(),
-                vec![],
-                vec![],
-                vec![],
-                0,
-            );
-            barrier.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0300");
-            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    barrier,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "threadfence_system call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
-        | "cuda_device::barrier::barrier_cta_arrive" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let control = Operation::new(
-                ctx,
-                BarrierCtaArriveCountOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0885");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "barrier_cta_arrive call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
-        | "cuda_device::barrier::barrier_cta_arrive_aligned" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let control = Operation::new(
-                ctx,
-                BarrierCtaArriveAlignedCountOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0886");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "barrier_cta_arrive_aligned call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
-        | "cuda_device::barrier::barrier_cta_sync" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let control = Operation::new(
-                ctx,
-                BarrierCtaSyncCountOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0883");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "barrier_cta_sync call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
-        | "cuda_device::barrier::barrier_cta_sync_aligned" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let control = Operation::new(
-                ctx,
-                BarrierCtaSyncAlignedCountOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0884");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "barrier_cta_sync_aligned call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
-        | "cuda_device::grid::dependency::trigger_dependents" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let last_op = prev_op;
-            let control = Operation::new(
-                ctx,
-                GridDependencyLaunchDependentsOp::get_concrete_op_info(),
-                vec![],
-                vec![],
-                vec![],
-                0,
-            );
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0913");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "grid_dependency_launch_dependents call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
-        | "cuda_device::grid::dependency::wait" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let last_op = prev_op;
-            let control = Operation::new(
-                ctx,
-                GridDependencyWaitOp::get_concrete_op_info(),
-                vec![],
-                vec![],
-                vec![],
-                0,
-            );
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0914");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "grid_dependency_wait call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
-        | "cuda_device::thread::__setmaxnreg_dec" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            if !matches!(&args[0], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "setmaxnreg requires a compile-time register count in 24..=256 divisible by 8".to_owned()
-                    )
-                );
-            }
-            let (register_count_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let register_count = register_count_value
-                .defining_op()
-                .and_then(|defining_op| Operation::get_op::<MirConstantOp>(defining_op, ctx))
-                .and_then(|constant| constant.get_attr_value(ctx))
-                .map(|value| value.value().to_u64())
-                .and_then(|value| u32::try_from(value).ok())
-                .filter(|value| (24..=256).contains(value) && value % 8 == 0);
-            let Some(register_count) = register_count else {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "setmaxnreg requires a compile-time register count in 24..=256 divisible by 8".to_owned()
-                    )
-                );
-            };
-            let control = SetMaxNRegDecOp::build(ctx, register_count);
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0916");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "setmaxnreg_dec call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
-        | "cuda_device::thread::__setmaxnreg_inc" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            if !matches!(&args[0], mir::Operand::Constant(_)) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "setmaxnreg requires a compile-time register count in 24..=256 divisible by 8".to_owned()
-                    )
-                );
-            }
-            let (register_count_value, last_op) = rvalue::translate_operand(
-                ctx,
-                body,
-                &args[0],
-                value_map,
-                block_ptr,
-                prev_op,
-                loc.clone(),
-            )?;
-            let register_count = register_count_value
-                .defining_op()
-                .and_then(|defining_op| Operation::get_op::<MirConstantOp>(defining_op, ctx))
-                .and_then(|constant| constant.get_attr_value(ctx))
-                .map(|value| value.value().to_u64())
-                .and_then(|value| u32::try_from(value).ok())
-                .filter(|value| (24..=256).contains(value) && value % 8 == 0);
-            let Some(register_count) = register_count else {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "setmaxnreg requires a compile-time register count in 24..=256 divisible by 8".to_owned()
-                    )
-                );
-            };
-            let control = SetMaxNRegIncOp::build(ctx, register_count);
-            control.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0915");
-            helpers::insert_op(ctx, control, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    control,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "setmaxnreg_inc call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
-        | "cuda_device::tma::cp_async_bulk_commit_group" => {
-            Ok(Some(super::tma::emit_tma_commit_group(
-                ctx, args, target, block_ptr, prev_op, block_map, loc, "v1:i0340",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor1dL2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0888");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_1d_l2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor1dL2CacheHintOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0917");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_1d_l2_cache_hint call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor2dL2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0889");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_2d_l2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint" => {
-            require_arity(name, args.len(), 4, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor2dL2CacheHintOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0918");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_2d_l2_cache_hint call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2" => {
-            require_arity(name, args.len(), 4, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor3dL2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0890");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_3d_l2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor3dL2CacheHintOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0919");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_3d_l2_cache_hint call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor4dL2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0891");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_4d_l2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor4dL2CacheHintOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0920");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_4d_l2_cache_hint call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor5dL2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0892");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_5d_l2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor5dL2CacheHintOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0921");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_5d_l2_cache_hint call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(ctx, dialect_nvvm::ops::CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op::get_concrete_op_info(), vec![], operands, vec![], 0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0893");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_prefetch_tensor_gather4_2d_l2 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
-        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(ctx, dialect_nvvm::ops::CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp::get_concrete_op_info(), vec![], operands, vec![], 0);
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0922");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(loc, TranslationErr::unsupported("cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint call without target block".to_owned()))
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
-        | "cuda_device::tma::cp_async_bulk_tensor_1d_g2s" => Ok(Some(super::tma::emit_tma_g2s(
-            ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 1, "v1:i0328",
-        )?)),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
-        | "cuda_device::tma::cp_async_bulk_tensor_1d_s2g" => Ok(Some(super::tma::emit_tma_s2g(
-            ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 1, "v1:i0335",
-        )?)),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
-        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s" => Ok(Some(super::tma::emit_tma_g2s(
-            ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 2, "v1:i0329",
-        )?)),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
-        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast" => {
-            Ok(Some(super::tma::emit_tma_g2s_multicast(
-                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, "v1:i0330",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
-        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2" => {
-            Ok(Some(super::tma::emit_tma_g2s_multicast_cg2(
-                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, "v1:i0331",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
-        | "cuda_device::tma::cp_async_bulk_tensor_2d_s2g" => Ok(Some(super::tma::emit_tma_s2g(
-            ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 2, "v1:i0336",
-        )?)),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
-        | "cuda_device::tma::cp_async_bulk_tensor_3d_g2s" => Ok(Some(super::tma::emit_tma_g2s(
-            ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 3, "v1:i0332",
-        )?)),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
-        | "cuda_device::tma::cp_async_bulk_tensor_3d_s2g" => Ok(Some(super::tma::emit_tma_s2g(
-            ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 3, "v1:i0337",
-        )?)),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
-        | "cuda_device::tma::cp_async_bulk_tensor_4d_g2s" => Ok(Some(super::tma::emit_tma_g2s(
-            ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 4, "v1:i0333",
-        )?)),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
-        | "cuda_device::tma::cp_async_bulk_tensor_4d_s2g" => Ok(Some(super::tma::emit_tma_s2g(
-            ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 4, "v1:i0338",
-        )?)),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
-        | "cuda_device::tma::cp_async_bulk_tensor_5d_g2s" => Ok(Some(super::tma::emit_tma_g2s(
-            ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 5, "v1:i0334",
-        )?)),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
-        | "cuda_device::tma::cp_async_bulk_tensor_5d_s2g" => Ok(Some(super::tma::emit_tma_s2g(
-            ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 5, "v1:i0339",
-        )?)),
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddIm2col3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0928");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_add_im2col_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddIm2col4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0929");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_add_im2col_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddIm2col5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0930");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_add_im2col_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile1dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0923");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_add_tile_1d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d" => {
-            require_arity(name, args.len(), 4, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile2dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0924");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_add_tile_2d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0925");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_add_tile_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0926");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_add_tile_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0927");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_add_tile_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndIm2col3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0936");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_and_im2col_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndIm2col4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0937");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_and_im2col_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndIm2col5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0938");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_and_im2col_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndTile1dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0931");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_and_tile_1d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d" => {
-            require_arity(name, args.len(), 4, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndTile2dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0932");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_and_tile_2d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndTile3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0933");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_and_tile_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndTile4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0934");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_and_tile_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndTile5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0935");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_and_tile_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecIm2col3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0944");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_dec_im2col_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecIm2col4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0945");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_dec_im2col_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecIm2col5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0946");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_dec_im2col_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecTile1dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0939");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_dec_tile_1d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d" => {
-            require_arity(name, args.len(), 4, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecTile2dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0940");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_dec_tile_2d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecTile3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0941");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_dec_tile_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecTile4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0942");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_dec_tile_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecTile5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0943");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_dec_tile_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncIm2col3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0952");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_inc_im2col_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncIm2col4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0953");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_inc_im2col_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncIm2col5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0954");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_inc_im2col_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncTile1dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0947");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_inc_tile_1d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d" => {
-            require_arity(name, args.len(), 4, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncTile2dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0948");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_inc_tile_2d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncTile3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0949");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_inc_tile_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncTile4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0950");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_inc_tile_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncTile5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0951");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_inc_tile_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxIm2col3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0960");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_max_im2col_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxIm2col4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0961");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_max_im2col_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxIm2col5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0962");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_max_im2col_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxTile1dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0955");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_max_tile_1d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d" => {
-            require_arity(name, args.len(), 4, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxTile2dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0956");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_max_tile_2d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxTile3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0957");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_max_tile_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxTile4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0958");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_max_tile_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxTile5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0959");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_max_tile_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinIm2col3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0968");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_min_im2col_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinIm2col4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0969");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_min_im2col_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinIm2col5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0970");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_min_im2col_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinTile1dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0963");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_min_tile_1d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d" => {
-            require_arity(name, args.len(), 4, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinTile2dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0964");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_min_tile_2d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinTile3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0965");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_min_tile_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinTile4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0966");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_min_tile_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinTile5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0967");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_min_tile_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrIm2col3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0976");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_or_im2col_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrIm2col4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0977");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_or_im2col_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrIm2col5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0978");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_or_im2col_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrTile1dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0971");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_or_tile_1d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d" => {
-            require_arity(name, args.len(), 4, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrTile2dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0972");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_or_tile_2d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrTile3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0973");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_or_tile_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrTile4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0974");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_or_tile_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrTile5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0975");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_or_tile_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorIm2col3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0984");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_xor_im2col_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorIm2col4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0985");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_xor_im2col_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorIm2col5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0986");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_xor_im2col_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorTile1dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0979");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_xor_tile_1d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d" => {
-            require_arity(name, args.len(), 4, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorTile2dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0980");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_xor_tile_2d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorTile3dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0981");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_xor_tile_3d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorTile4dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0982");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_xor_tile_4d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
-        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d" => {
-            require_arity(name, args.len(), 7, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorTile5dOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0983");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "cp_async_bulk_tensor_reduce_xor_tile_5d call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
-        | "cuda_device::tma::cp_async_bulk_wait_group" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            if !matches!(args.first(), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "TMA wait-group count must be a compile-time constant".to_owned()
-                    )
-                );
-            }
-            Ok(Some(super::tma::emit_tma_wait_group(
-                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, false,
-                "v1:i0341",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
-        | "cuda_device::tma::cp_async_bulk_wait_group_read" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            if !matches!(args.first(), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "TMA wait-group count must be a compile-time constant".to_owned()
-                    )
-                );
-            }
-            Ok(Some(super::tma::emit_tma_wait_group(
-                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, true,
-                "v1:i0342",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::FenceProxyTensorMapGenericAcquireClusterOp::get_concrete_op_info(
-                ),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0905");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "fence_proxy_tensormap_generic_acquire_cluster call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::FenceProxyTensorMapGenericAcquireCtaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0906");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "fence_proxy_tensormap_generic_acquire_cta call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::FenceProxyTensorMapGenericAcquireGpuOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0907");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "fence_proxy_tensormap_generic_acquire_gpu call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::FenceProxyTensorMapGenericAcquireSystemOp::get_concrete_op_info(
-                ),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0908");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "fence_proxy_tensormap_generic_acquire_system call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::FenceProxyTensorMapGenericReleaseClusterOp::get_concrete_op_info(
-                ),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0909");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "fence_proxy_tensormap_generic_release_cluster call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_release_cta" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::FenceProxyTensorMapGenericReleaseCtaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0910");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "fence_proxy_tensormap_generic_release_cta call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::FenceProxyTensorMapGenericReleaseGpuOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0911");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "fence_proxy_tensormap_generic_release_gpu call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
-        | "cuda_device::tma::fence_proxy_tensormap_generic_release_system" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::FenceProxyTensorMapGenericReleaseSystemOp::get_concrete_op_info(
-                ),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0912");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "fence_proxy_tensormap_generic_release_system call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
-        | "cuda_device::tma::prefetch_tma_descriptor" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::PrefetchTensorMapOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0887");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "prefetch_tma_descriptor call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
-        | "cuda_device::tma::tensormap_replace_box_dim" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensor-map replacement selector must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapBoxDimOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0894");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_box_dim call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
-        | "cuda_device::tma::tensormap_replace_element_stride" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensor-map replacement selector must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapElementStrideOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0895");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_element_stride call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
-        | "cuda_device::tma::tensormap_replace_element_type" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensor-map replacement selector must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapElementTypeOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0896");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_element_type call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
-        | "cuda_device::tma::tensormap_replace_fill_mode" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensor-map replacement selector must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapFillModeOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0897");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_fill_mode call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
-        | "cuda_device::tma::tensormap_replace_global_address" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapGlobalAddressOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0898");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_global_address call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
-        | "cuda_device::tma::tensormap_replace_global_dim" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensor-map replacement selector must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapGlobalDimOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0899");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_global_dim call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
-        | "cuda_device::tma::tensormap_replace_global_stride" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensor-map replacement selector must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapGlobalStrideOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0900");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_global_stride call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
-        | "cuda_device::tma::tensormap_replace_interleave_layout" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensor-map replacement selector must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapInterleaveLayoutOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0901");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_interleave_layout call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
-        | "cuda_device::tma::tensormap_replace_rank" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapRankOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0902");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_rank call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
-        | "cuda_device::tma::tensormap_replace_swizzle_atomicity" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensor-map replacement selector must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapSwizzleAtomicityOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0903");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_swizzle_atomicity call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
-        | "cuda_device::tma::tensormap_replace_swizzle_mode" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensor-map replacement selector must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                dialect_nvvm::ops::ReplaceTensorMapSwizzleModeOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0904");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tensormap_replace_swizzle_mode call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
-        | "cuda_device::tcgen05::tcgen05_alloc" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05AllocOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0343");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_alloc call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
-        | "cuda_device::tcgen05::tcgen05_alloc_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05AllocCg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0359");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_alloc_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
-        | "cuda_device::tcgen05::tcgen05_commit" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05CommitOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0348");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_commit call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
-        | "cuda_device::tcgen05::tcgen05_commit_cg2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05CommitCg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0363");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_commit_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
-        | "cuda_device::tcgen05::tcgen05_commit_multicast" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05CommitMulticastOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0760");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_commit_multicast call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
-        | "cuda_device::tcgen05::tcgen05_commit_multicast_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05CommitMulticastCg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0365");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_commit_multicast_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
-        | "cuda_device::tcgen05::tcgen05_commit_shared_cluster" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05CommitSharedClusterOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0349");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_commit_shared_cluster call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
-        | "cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05CommitSharedClusterCg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0364");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_commit_shared_cluster_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp128x128bOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0582");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_128x128b call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp128x128bB4x16P64Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0578");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_128x128b_b4x16_p64 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp128x128bB4x16P64Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0579");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_128x128b_b4x16_p64_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp128x128bB6x16P32Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0580");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_128x128b_b6x16_p32 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp128x128bB6x16P32Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0581");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_128x128b_b6x16_p32_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
-        | "cuda_device::tcgen05::tcgen05_cp_128x128b_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp128x128bCg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0583");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_128x128b_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
-        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp128x256bB4x16P64Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0584");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_128x256b_b4x16_p64 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
-        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp128x256bB4x16P64Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0585");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_128x256b_b4x16_p64_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
-        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp128x256bB6x16P32Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0586");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_128x256b_b6x16_p32 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
-        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp128x256bB6x16P32Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0587");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_128x256b_b6x16_p32_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp32x128bWarpx4Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0592");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_32x128b_warpx4 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp32x128bWarpx4B4x16P64Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0588");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_32x128b_warpx4_b4x16_p64 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp32x128bWarpx4B4x16P64Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0589");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp32x128bWarpx4B6x16P32Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0590");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_32x128b_warpx4_b6x16_p32 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp32x128bWarpx4B6x16P32Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0591");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
-        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp32x128bWarpx4Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0593");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_32x128b_warpx4_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp4x256bOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0598");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_4x256b call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp4x256bB4x16P64Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0594");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_4x256b_b4x16_p64 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp4x256bB4x16P64Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0595");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_4x256b_b4x16_p64_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp4x256bB6x16P32Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0596");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_4x256b_b6x16_p32 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp4x256bB6x16P32Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0597");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_4x256b_b6x16_p32_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
-        | "cuda_device::tcgen05::tcgen05_cp_4x256b_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp4x256bCg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0599");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_4x256b_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0123Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0604");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_01_23 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0600");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0601");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0602");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0603");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0123Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0605");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_01_23_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0213Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0610");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_02_13 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0606");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0607");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0608");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0609");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2 call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
-        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Cp64x128bWarpx2Pair0213Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0611");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_64x128b_warpx2_02_13_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
-        | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05CpSmemToTmemOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0354");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_smem_to_tmem call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
-        | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05CpSmemToTmemCg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0366");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_cp_smem_to_tmem_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
-        | "cuda_device::tcgen05::tcgen05_dealloc" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05DeallocOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0344");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_dealloc call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
-        | "cuda_device::tcgen05::tcgen05_dealloc_cg2" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05DeallocCg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0360");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_dealloc_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
-        | "cuda_device::tcgen05::tcgen05_fence_after_thread_sync" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05FenceAfterThreadSyncOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0347");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_fence_after_thread_sync call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
-        | "cuda_device::tcgen05::tcgen05_fence_before_thread_sync" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05FenceBeforeThreadSyncOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0346");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_fence_before_thread_sync call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX16Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0637");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x16_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX16RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0636");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x16_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..2).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX1Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0629");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..2)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 2);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x1_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..2).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX1RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0628");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..2)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 2);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x1_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX2Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0631");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x2_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX2RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0630");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x2_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..64).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX32Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0639");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..64)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 64);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x32_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..64).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX32RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0638");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..64)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 64);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x32_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..8).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX4Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0633");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..8)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 8);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x4_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..8).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX4RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0632");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..8)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 8);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x4_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..128).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX64Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0641");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..128)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 128);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x64_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..128).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX64RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0640");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..128)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 128);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x64_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..16).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX8Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0635");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..16)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 16);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x8_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
-        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..16).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x128bX8RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0634");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..16)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 16);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x128b_x8_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_pure" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = FP32Type::get(ctx).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bPureOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0356");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_pure call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..64).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX16Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0651");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..64)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 64);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x16_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..64).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX16RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0650");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..64)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 64);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x16_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX1Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0643");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x1_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX1RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0642");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x1_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..8).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX2Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0645");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..8)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 8);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x2_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..8).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX2RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0644");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..8)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 8);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x2_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..128).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX32Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0653");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..128)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 128);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x32_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..128).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX32RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0652");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..128)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 128);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x32_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..16).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX4Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0647");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..16)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 16);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x4_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..16).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX4RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0646");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..16)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 16);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x4_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX8Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0649");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x8_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = FP32Type::get(ctx).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX8PureOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0355");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x8_pure call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
-        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x256bX8RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0648");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x256b_x8_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..128).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X128Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0743");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..128)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 128);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x128_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..128).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X128RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0742");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..128)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 128);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x128_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..16).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X16Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0737");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..16)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 16);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x16_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..16).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X16RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0736");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..16)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 16);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x16_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..1).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X1Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0729");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            let value = intrinsic;
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x1_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..1).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X1RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0728");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            let value = intrinsic;
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x1_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..2).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X2Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0731");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..2)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 2);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x2_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..2).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X2RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0730");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..2)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 2);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x2_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X32Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0739");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x32_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X32RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0738");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x32_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X4Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0733");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x4_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X4RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0732");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x4_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..64).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X64Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0741");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..64)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 64);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x64_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..64).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X64RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0740");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..64)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 64);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x64_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..8).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X8Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0735");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..8)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 8);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x8_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
-        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            if operands
-                .get(1)
-                .and_then(|value| value.defining_op())
-                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-                .is_none()
-            {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                    )
-                );
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..8).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x32bx2X8RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0734");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..8)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 8);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x32bx2_x8_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..128).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX128Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0627");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..128)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 128);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x128_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..128).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX128RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0626");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..128)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 128);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x128_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..16).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX16Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0621");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..16)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 16);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x16_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..16).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX16RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0620");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..16)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 16);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x16_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..1).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX1Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0613");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            let value = intrinsic;
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x1_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..1).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX1RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0612");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            let value = intrinsic;
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x1_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..2).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX2Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0615");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..2)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 2);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x2_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..2).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX2RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0614");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..2)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 2);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x2_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX32Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0623");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x32_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX32RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0622");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x32_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX4Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0617");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x4_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX4RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0616");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x4_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..64).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX64Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0625");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..64)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 64);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x64_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..64).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX64RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0624");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..64)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 64);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x64_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..8).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX8Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0619");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..8)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 8);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x8_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
-        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..8).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld16x64bX8RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0618");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..8)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 8);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_16x64b_x8_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..128).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX128Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0669");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..128)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 128);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x128_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..128).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX128RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0668");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..128)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 128);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x128_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..16).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX16Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0663");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..16)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 16);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x16_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..16).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX16RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0662");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..16)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 16);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x16_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..1).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX1Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0655");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            let value = intrinsic;
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x1_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..1).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX1RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0654");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let result = intrinsic.deref(ctx).get_result(0);
-            let value = intrinsic;
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x1_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..2).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX2Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0657");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..2)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 2);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x2_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..2).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX2RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0656");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..2)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 2);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x2_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX32Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0665");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x32_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..32).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX32RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0664");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..32)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 32);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x32_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX4Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0659");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x4_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..4).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX4RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0658");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..4)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 4);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x4_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..64).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX64Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0667");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..64)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 64);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x64_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..64).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX64RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0666");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..64)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 64);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x64_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..8).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX8Pack16Op::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0661");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..8)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 8);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x8_pack16 call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
-        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-            let result_types = (0..8).map(|_| result_ty).collect();
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05Ld32x32bX8RawOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0660");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            let results: Vec<Value> = (0..8)
-                .map(|index| intrinsic.deref(ctx).get_result(index))
-                .collect();
-            let array_ty = MirArrayType::get(ctx, result_ty, 8);
-            let array = Operation::new(
-                ctx,
-                MirConstructArrayOp::get_concrete_op_info(),
-                vec![array_ty.into()],
-                results,
-                vec![],
-                0,
-            );
-            array.deref_mut(ctx).set_loc(loc.clone());
-            array.insert_after(ctx, intrinsic);
-            let destination_rust_ty = match destination.ty(body.locals()) {
-                Ok(ty) => ty,
-                Err(error) => {
-                    return input_err!(
-                        loc,
-                        TranslationErr::unsupported(format!(
-                            "failed to resolve destination type for intrinsic result: {error:?}"
-                        ))
-                    );
-                }
-            };
-            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
-            let array_result = array.deref(ctx).get_result(0);
-            let (result, value) = if destination_ty == array_result.get_type(ctx) {
-                (array_result, array)
-            } else {
-                let value = Operation::new(
-                    ctx,
-                    MirConstructStructOp::get_concrete_op_info(),
-                    vec![destination_ty],
-                    vec![array_result],
-                    vec![],
-                    0,
-                );
-                value.deref_mut(ctx).set_loc(loc.clone());
-                value.insert_after(ctx, array);
-                (value.deref(ctx).get_result(0), value)
-            };
-            helpers::set_compiler_result_bundle_marker(ctx, value);
-            Ok(Some(helpers::emit_store_result_and_goto(
-                ctx,
-                destination,
-                result,
-                target,
-                block_ptr,
-                value,
-                value_map,
-                block_map,
-                loc,
-                "tcgen05_ld_32x32b_x8_raw call without target block",
-            )?))
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
-        | "cuda_device::tcgen05::tcgen05_load_wait" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05LoadWaitOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0357");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_load_wait call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
-        | "cuda_device::tcgen05::tcgen05_mma_e2m1" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = Tcgen05MmaKindAttr::F8f6f4;
-            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;
-            let collector_a = Tcgen05MmaCollectorAAttr::Discard;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1015");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_e2m1 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
-        | "cuda_device::tcgen05::tcgen05_mma_e2m3" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = Tcgen05MmaKindAttr::F8f6f4;
-            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;
-            let collector_a = Tcgen05MmaCollectorAAttr::Discard;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1013");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_e2m3 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
-        | "cuda_device::tcgen05::tcgen05_mma_e3m2" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = Tcgen05MmaKindAttr::F8f6f4;
-            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;
-            let collector_a = Tcgen05MmaCollectorAAttr::Discard;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1014");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_e3m2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
-        | "cuda_device::tcgen05::tcgen05_mma_e4m3" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = Tcgen05MmaKindAttr::F8f6f4;
-            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;
-            let collector_a = Tcgen05MmaCollectorAAttr::Discard;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1011");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_e4m3 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
-        | "cuda_device::tcgen05::tcgen05_mma_e5m2" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = Tcgen05MmaKindAttr::F8f6f4;
-            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;
-            let collector_a = Tcgen05MmaCollectorAAttr::Discard;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1012");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_e5m2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
-        | "cuda_device::tcgen05::tcgen05_mma_f16" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaF16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0351");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_f16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
-        | "cuda_device::tcgen05::tcgen05_mma_f16_cg2" => {
-            require_arity(name, args.len(), 5, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaF16Cg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0362");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_f16_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
-        | "cuda_device::tcgen05::__tcgen05_mma_shared" => {
-            require_arity(name, args.len(), 8, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(5usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let cta_group = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
-                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let collector_a = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
-                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
-                Some(2) => Tcgen05MmaCollectorAAttr::Fill,
-                Some(3) => Tcgen05MmaCollectorAAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA collector-A selector is outside its closed range"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0763");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_shared call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
-        | "cuda_device::tcgen05::__tcgen05_mma_sp_shared" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let cta_group = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
-                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let collector_a = match generated_tcgen05_mma_selector(args.get(8usize)) {
-                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
-                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
-                Some(2) => Tcgen05MmaCollectorAAttr::Fill,
-                Some(3) => Tcgen05MmaCollectorAAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA collector-A selector is outside its closed range"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::SpShared);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0766");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_sp_shared call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
-        | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let cta_group = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
-                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let collector_a = match generated_tcgen05_mma_selector(args.get(8usize)) {
-                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
-                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
-                Some(2) => Tcgen05MmaCollectorAAttr::Fill,
-                Some(3) => Tcgen05MmaCollectorAAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA collector-A selector is outside its closed range"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::SpTensor);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0767");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_sp_tensor call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
-        | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let cta_group = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
-                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let collector_a = match generated_tcgen05_mma_selector(args.get(8usize)) {
-                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
-                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA collector-A selector is outside its closed range"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::SpTensorAshift);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0768");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_sp_tensor_ashift call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
-        | "cuda_device::tcgen05::__tcgen05_mma_tensor" => {
-            require_arity(name, args.len(), 8, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(5usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let cta_group = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
-                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let collector_a = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
-                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
-                Some(2) => Tcgen05MmaCollectorAAttr::Fill,
-                Some(3) => Tcgen05MmaCollectorAAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA collector-A selector is outside its closed range"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Tensor);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0764");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_tensor call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
-        | "cuda_device::tcgen05::__tcgen05_mma_tensor_ashift" => {
-            require_arity(name, args.len(), 8, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(5usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let cta_group = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
-                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let collector_a = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
-                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA collector-A selector is outside its closed range"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::TensorAshift);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
-            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0765");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_tensor_ashift call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_bf16" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaWsBf16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0352");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_bf16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_e2m1" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = Tcgen05MmaKindAttr::F8f6f4;
-            let b_buffer = Tcgen05MmaBBufferAttr::B0;
-            let b_usage = Tcgen05MmaBUsageAttr::Discard;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0781");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_e2m1 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_e2m3" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = Tcgen05MmaKindAttr::F8f6f4;
-            let b_buffer = Tcgen05MmaBBufferAttr::B0;
-            let b_usage = Tcgen05MmaBUsageAttr::Discard;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0779");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_e2m3 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_e3m2" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = Tcgen05MmaKindAttr::F8f6f4;
-            let b_buffer = Tcgen05MmaBBufferAttr::B0;
-            let b_usage = Tcgen05MmaBUsageAttr::Discard;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0780");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_e3m2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_e4m3" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = Tcgen05MmaKindAttr::F8f6f4;
-            let b_buffer = Tcgen05MmaBBufferAttr::B0;
-            let b_usage = Tcgen05MmaBUsageAttr::Discard;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0777");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_e4m3 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_e5m2" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = Tcgen05MmaKindAttr::F8f6f4;
-            let b_buffer = Tcgen05MmaBBufferAttr::B0;
-            let b_usage = Tcgen05MmaBUsageAttr::Discard;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0778");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_e5m2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_f16" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaWsF16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0350");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_f16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_shared" => {
-            require_arity(name, args.len(), 8, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(5usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_buffer = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(0) => Tcgen05MmaBBufferAttr::B0,
-                Some(1) => Tcgen05MmaBBufferAttr::B1,
-                Some(2) => Tcgen05MmaBBufferAttr::B2,
-                Some(3) => Tcgen05MmaBBufferAttr::B3,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_usage = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaBUsageAttr::Discard,
-                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
-                Some(2) => Tcgen05MmaBUsageAttr::Fill,
-                Some(3) => Tcgen05MmaBUsageAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsShared);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0769");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_shared call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_buffer = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaBBufferAttr::B0,
-                Some(1) => Tcgen05MmaBBufferAttr::B1,
-                Some(2) => Tcgen05MmaBBufferAttr::B2,
-                Some(3) => Tcgen05MmaBBufferAttr::B3,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_usage = match generated_tcgen05_mma_selector(args.get(8usize)) {
-                Some(0) => Tcgen05MmaBUsageAttr::Discard,
-                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
-                Some(2) => Tcgen05MmaBUsageAttr::Fill,
-                Some(3) => Tcgen05MmaBUsageAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsSharedZeroColMask);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0770");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_shared_zero_col_mask call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_buffer = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaBBufferAttr::B0,
-                Some(1) => Tcgen05MmaBBufferAttr::B1,
-                Some(2) => Tcgen05MmaBBufferAttr::B2,
-                Some(3) => Tcgen05MmaBBufferAttr::B3,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_usage = match generated_tcgen05_mma_selector(args.get(8usize)) {
-                Some(0) => Tcgen05MmaBUsageAttr::Discard,
-                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
-                Some(2) => Tcgen05MmaBUsageAttr::Fill,
-                Some(3) => Tcgen05MmaBUsageAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsSpShared);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0771");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_sp_shared call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask" => {
-            require_arity(name, args.len(), 10, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5, 6];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_buffer = match generated_tcgen05_mma_selector(args.get(8usize)) {
-                Some(0) => Tcgen05MmaBBufferAttr::B0,
-                Some(1) => Tcgen05MmaBBufferAttr::B1,
-                Some(2) => Tcgen05MmaBBufferAttr::B2,
-                Some(3) => Tcgen05MmaBBufferAttr::B3,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_usage = match generated_tcgen05_mma_selector(args.get(9usize)) {
-                Some(0) => Tcgen05MmaBUsageAttr::Discard,
-                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
-                Some(2) => Tcgen05MmaBUsageAttr::Fill,
-                Some(3) => Tcgen05MmaBUsageAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsSpSharedZeroColMask);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0772");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_sp_shared_zero_col_mask call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_buffer = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaBBufferAttr::B0,
-                Some(1) => Tcgen05MmaBBufferAttr::B1,
-                Some(2) => Tcgen05MmaBBufferAttr::B2,
-                Some(3) => Tcgen05MmaBBufferAttr::B3,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_usage = match generated_tcgen05_mma_selector(args.get(8usize)) {
-                Some(0) => Tcgen05MmaBUsageAttr::Discard,
-                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
-                Some(2) => Tcgen05MmaBUsageAttr::Fill,
-                Some(3) => Tcgen05MmaBUsageAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsSpTensor);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0773");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_sp_tensor call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask" => {
-            require_arity(name, args.len(), 10, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5, 6];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_buffer = match generated_tcgen05_mma_selector(args.get(8usize)) {
-                Some(0) => Tcgen05MmaBBufferAttr::B0,
-                Some(1) => Tcgen05MmaBBufferAttr::B1,
-                Some(2) => Tcgen05MmaBBufferAttr::B2,
-                Some(3) => Tcgen05MmaBBufferAttr::B3,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_usage = match generated_tcgen05_mma_selector(args.get(9usize)) {
-                Some(0) => Tcgen05MmaBUsageAttr::Discard,
-                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
-                Some(2) => Tcgen05MmaBUsageAttr::Fill,
-                Some(3) => Tcgen05MmaBUsageAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsSpTensorZeroColMask);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0774");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_sp_tensor_zero_col_mask call without target block"
-                            .to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor" => {
-            require_arity(name, args.len(), 8, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(5usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_buffer = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(0) => Tcgen05MmaBBufferAttr::B0,
-                Some(1) => Tcgen05MmaBBufferAttr::B1,
-                Some(2) => Tcgen05MmaBBufferAttr::B2,
-                Some(3) => Tcgen05MmaBBufferAttr::B3,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_usage = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaBUsageAttr::Discard,
-                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
-                Some(2) => Tcgen05MmaBUsageAttr::Fill,
-                Some(3) => Tcgen05MmaBUsageAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0775");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_tensor call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
-        | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask" => {
-            require_arity(name, args.len(), 9, &loc)?;
-            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(runtime_indices.len());
-            for &index in runtime_indices {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    &args[index],
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
-                Some(0) => Tcgen05MmaKindAttr::F16,
-                Some(1) => Tcgen05MmaKindAttr::Tf32,
-                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
-                Some(3) => Tcgen05MmaKindAttr::I8,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_buffer = match generated_tcgen05_mma_selector(args.get(7usize)) {
-                Some(0) => Tcgen05MmaBBufferAttr::B0,
-                Some(1) => Tcgen05MmaBBufferAttr::B1,
-                Some(2) => Tcgen05MmaBBufferAttr::B2,
-                Some(3) => Tcgen05MmaBBufferAttr::B3,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let b_usage = match generated_tcgen05_mma_selector(args.get(8usize)) {
-                Some(0) => Tcgen05MmaBUsageAttr::Discard,
-                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
-                Some(2) => Tcgen05MmaBUsageAttr::Fill,
-                Some(3) => Tcgen05MmaBUsageAttr::Use,
-                _ => {
-                    return input_err!(
-                        loc.clone(),
-                        TranslationErr::unsupported(
-                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
-                                .to_owned()
-                        )
-                    );
-                }
-            };
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            let mma_op = Tcgen05MmaOp::new(intrinsic);
-            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensorZeroColMask);
-            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
-            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0776");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_tensor_zero_col_mask call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
-        | "cuda_device::tcgen05::tcgen05_mma_ws_tf32" => {
-            require_arity(name, args.len(), 6, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05MmaWsTf32Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0353");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_mma_ws_tf32 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
-        | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05RelinquishAllocPermitOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0345");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_relinquish_alloc_permit call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
-        | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05RelinquishAllocPermitCg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0361");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_relinquish_alloc_permit_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
-        | "cuda_device::tcgen05::tcgen05_shift_down" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05ShiftDownOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0761");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_shift_down call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
-        | "cuda_device::tcgen05::tcgen05_shift_down_cg2" => {
-            require_arity(name, args.len(), 1, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05ShiftDownCg2Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0762");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_shift_down_cg2 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                32,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX16RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0694");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x16_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                32,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX16Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0695");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x16_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                2,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX1RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0686");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x1_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                2,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX1Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0687");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x1_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                4,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX2RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0688");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x2_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                4,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX2Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0689");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x2_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                64,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX32RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0696");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x32_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                64,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX32Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0697");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x32_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                8,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX4RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0690");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x4_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                8,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX4Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0691");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x4_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                128,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX64RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0698");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x64_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                128,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX64Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0699");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x64_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                16,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX8RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0692");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x8_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
-        | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                16,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x128bX8Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0693");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x128b_x8_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                64,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX16RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0708");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x16_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                64,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX16Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0709");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x16_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                4,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX1RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0700");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x1_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                4,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX1Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0701");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x1_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                8,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX2RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0702");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x2_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                8,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX2Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0703");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x2_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                128,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX32RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0710");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x32_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                128,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX32Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0711");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x32_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                16,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX4RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0704");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x4_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                16,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX4Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0705");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x4_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                32,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX8RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0706");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x8_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
-        | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                32,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x256bX8Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0707");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x256b_x8_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                128,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X128RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0758");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x128_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                128,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X128Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0759");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x128_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                16,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X16RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0752");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x16_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                16,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X16Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0753");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x16_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                1,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X1RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0744");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x1_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                1,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X1Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0745");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x1_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                2,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X2RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0746");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x2_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                2,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X2Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0747");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x2_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                32,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X32RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0754");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x32_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                32,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X32Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0755");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x32_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                4,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X4RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0748");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x4_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                4,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X4Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0749");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x4_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                64,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X64RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0756");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x64_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                64,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X64Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0757");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x64_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                8,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X8RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0750");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x8_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
-        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16" => {
-            require_arity(name, args.len(), 3, &loc)?;
-            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
-                return input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
-                            .to_owned()
-                    )
-                );
-            }
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                8,
-                true,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x32bx2X8Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0751");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x32bx2_x8_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                128,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX128RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0684");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x128_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                128,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX128Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0685");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x128_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                16,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX16RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0678");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x16_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                16,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX16Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0679");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x16_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                1,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX1RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0670");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x1_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                1,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX1Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0671");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x1_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                2,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX2RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0672");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x2_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                2,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX2Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0673");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x2_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                32,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX32RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0680");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x32_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                32,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX32Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0681");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x32_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                4,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX4RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0674");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x4_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                4,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX4Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0675");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x4_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                64,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX64RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0682");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x64_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                64,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX64Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0683");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x64_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                8,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX8RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0676");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x8_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
-        | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                8,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St16x64bX8Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0677");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_16x64b_x8_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                128,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX128RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0726");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x128_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                128,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX128Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0727");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x128_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                16,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX16RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0720");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x16_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                16,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX16Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0721");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x16_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                1,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX1RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0712");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x1_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                1,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX1Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0713");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x1_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                2,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX2RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0714");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x2_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                2,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX2Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0715");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x2_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                32,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX32RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0722");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x32_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                32,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX32Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0723");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x32_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                4,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX4RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0716");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x4_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                4,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX4Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0717");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x4_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                64,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX64RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0724");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x64_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                64,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX64Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0725");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x64_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                8,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX8RawOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0718");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x8_raw call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
-        | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16" => {
-            require_arity(name, args.len(), 2, &loc)?;
-            let (operands, last_op) = import_generated_tcgen05_store_operands(
-                ctx,
-                body,
-                args,
-                8,
-                false,
-                block_ptr,
-                prev_op,
-                value_map,
-                loc.clone(),
-            )?;
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05St32x32bX8Unpack16Op::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0719");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_st_32x32b_x8_unpack16 call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
-        | "cuda_device::tcgen05::tcgen05_store_wait" => {
-            require_arity(name, args.len(), 0, &loc)?;
-            let mut last_op = prev_op;
-            let mut operands = Vec::with_capacity(args.len());
-            for arg in args {
-                let (value, translated) = rvalue::translate_operand(
-                    ctx,
-                    body,
-                    arg,
-                    value_map,
-                    block_ptr,
-                    last_op,
-                    loc.clone(),
-                )?;
-                last_op = translated;
-                operands.push(value);
-            }
-            let intrinsic = Operation::new(
-                ctx,
-                Tcgen05StoreWaitOp::get_concrete_op_info(),
-                vec![],
-                operands,
-                vec![],
-                0,
-            );
-            intrinsic.deref_mut(ctx).set_loc(loc.clone());
-            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0358");
-            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
-            if let Some(target_idx) = target {
-                Ok(Some(helpers::emit_goto(
-                    ctx,
-                    *target_idx,
-                    intrinsic,
-                    block_map,
-                    loc,
-                )))
-            } else {
-                input_err!(
-                    loc,
-                    TranslationErr::unsupported(
-                        "tcgen05_store_wait call without target block".to_owned()
-                    )
-                )
-            }
-        }
-        _ => Ok(None),
-    }
-}
-
-fn require_arity(
-    name: &str,
-    actual: usize,
-    expected: usize,
-    loc: &Location,
-) -> TranslationResult<()> {
-    if actual != expected {
-        return input_err!(
-            loc.clone(),
-            TranslationErr::unsupported(format!(
-                "generated intrinsic `{name}` expects {expected} arguments, got {actual}"
-            ))
-        );
-    }
-    Ok(())
-}
-
-fn generated_tcgen05_mma_selector(operand: Option<&mir::Operand>) -> Option<u32> {
-    use rustc_public::ty::{ConstantKind, TyConstKind};
-    let mir::Operand::Constant(constant) = operand? else {
-        return None;
-    };
-    let value: u128 = match constant.const_.kind() {
-        ConstantKind::Allocated(alloc) => alloc.read_uint().ok()?,
-        ConstantKind::Ty(value) => match value.kind() {
-            TyConstKind::Value(_, alloc) => alloc.read_uint().ok()?,
-            _ => value.eval_target_usize().ok()? as u128,
-        },
-        ConstantKind::Unevaluated(_) | ConstantKind::Param(_) => return None,
-        ConstantKind::ZeroSized => return None,
-    };
-    u32::try_from(value).ok()
-}
-
-#[allow(clippy::too_many_arguments)]
-fn import_generated_tcgen05_store_operands(
-    ctx: &mut Context,
-    body: &mir::Body,
-    args: &[mir::Operand],
-    expected_len: usize,
-    has_half_split_offset: bool,
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    value_map: &mut ValueMap,
-    loc: Location,
-) -> TranslationResult<(Vec<Value>, Option<Ptr<Operation>>)> {
-    let expected_arity = if has_half_split_offset { 3 } else { 2 };
-    if args.len() != expected_arity || !(1..=128).contains(&expected_len) {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(
-                "generated tcgen05 store has an invalid address, offset, or register count"
-                    .to_owned()
-            )
-        );
-    }
-    let u32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-    let (address, last_op) = rvalue::translate_operand(
-        ctx,
-        body,
-        &args[0],
-        value_map,
-        block_ptr,
-        prev_op,
-        loc.clone(),
-    )?;
-    let (half_split_offset, last_op) = if has_half_split_offset {
-        let (offset, translated) = rvalue::translate_operand(
-            ctx,
-            body,
-            &args[1],
-            value_map,
-            block_ptr,
-            last_op,
-            loc.clone(),
-        )?;
-        if offset
-            .defining_op()
-            .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
-            .is_none()
-        {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(
-                    "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
-                )
-            );
-        }
-        (Some(offset), translated)
-    } else {
-        (None, last_op)
-    };
-    let data_index = if has_half_split_offset { 2 } else { 1 };
-    let (data, mut last_op) = rvalue::translate_operand(
-        ctx,
-        body,
-        &args[data_index],
-        value_map,
-        block_ptr,
-        last_op,
-        loc.clone(),
-    )?;
-    if expected_len == 1 {
-        if data.get_type(ctx) != u32_ty {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(
-                    "generated tcgen05 store data must be a u32 register".to_owned()
-                )
-            );
-        }
-        let mut operands = vec![address];
-        operands.extend(half_split_offset);
-        operands.push(data);
-        return Ok((operands, last_op));
-    }
-
-    let data_ty = data.get_type(ctx);
-    let direct_array = data_ty
-        .deref(ctx)
-        .downcast_ref::<MirArrayType>()
-        .is_some_and(|array| array.size() == expected_len as u64 && array.element_type() == u32_ty);
-    let array = if direct_array {
-        data
-    } else {
-        let wrapped_array_ty = data_ty
-            .deref(ctx)
-            .downcast_ref::<MirStructType>()
-            .filter(|structure| structure.field_count() == 1)
-            .and_then(|structure| structure.get_field_type(0));
-        let valid_wrapper = wrapped_array_ty.is_some_and(|field_ty| {
-            field_ty
-                .deref(ctx)
-                .downcast_ref::<MirArrayType>()
-                .is_some_and(|array| {
-                    array.size() == expected_len as u64 && array.element_type() == u32_ty
-                })
-        });
-        if !valid_wrapper {
-            return input_err!(
-                loc,
-                TranslationErr::unsupported(format!(
-                    "generated tcgen05 store data must contain {expected_len} u32 registers"
-                ))
-            );
-        }
-        let array_ty = wrapped_array_ty.expect("validated tcgen05 store wrapper");
-        let extract = Operation::new(
-            ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![array_ty],
-            vec![data],
-            vec![],
-            0,
-        );
-        extract.deref_mut(ctx).set_loc(loc.clone());
-        let extract = MirExtractFieldOp::new(extract);
-        extract.set_attr_index(ctx, FieldIndexAttr(0));
-        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
-        last_op = Some(extract.get_operation());
-        extract.get_operation().deref(ctx).get_result(0)
-    };
-
-    let mut operands = Vec::with_capacity(expected_len + 1 + usize::from(has_half_split_offset));
-    operands.push(address);
-    operands.extend(half_split_offset);
-    for index in 0..expected_len {
-        let extract = Operation::new(
-            ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![u32_ty],
-            vec![array],
-            vec![],
-            0,
-        );
-        extract.deref_mut(ctx).set_loc(loc.clone());
-        let extract = MirExtractFieldOp::new(extract);
-        extract.set_attr_index(ctx, FieldIndexAttr(index as u32));
-        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
-        last_op = Some(extract.get_operation());
-        operands.push(extract.get_operation().deref(ctx).get_result(0));
-    }
-    Ok((operands, last_op))
-}
-
-#[derive(Clone, Copy)]
-enum GeneratedMmaImportAdapter {
-    C2U32A2U32B1U32ToD2U32,
-    C2U32A4U32B2U32ToD2U32,
-    C2U32A4U32B4U32ToD2U32,
-    C4F32A2U32B1U32ToD4F32,
-    C4F32A4U32B2U32ToD4F32,
-    C4F32A4U32B4U32ToD4F32,
-    C2F64A1F64B1F64ToD2F64,
-    C2I32A1U32B1U32ToD2I32,
-    C4I32A4U32B2U32ToD4I32,
-    C4I32A4U32B4U32ToD4I32,
-    C4I32A2U32B1U32ToD4I32,
-    C4I32A2U32B2U32ToD4I32,
-    C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
-}
-
-#[allow(clippy::too_many_arguments)]
-fn extract_generated_mma_array(
-    ctx: &mut Context,
-    array: Value,
-    expected_element_ty: TypeHandle,
-    expected_len: usize,
-    block_ptr: Ptr<BasicBlock>,
-    mut last_op: Option<Ptr<Operation>>,
-    loc: Location,
-) -> TranslationResult<(Vec<Value>, Ptr<Operation>)> {
-    let valid = array
-        .get_type(ctx)
-        .deref(ctx)
-        .downcast_ref::<MirArrayType>()
-        .is_some_and(|array_ty| {
-            array_ty.size() == expected_len as u64 && array_ty.element_type() == expected_element_ty
-        });
-    if !valid {
-        return input_err!(
-            loc,
-            TranslationErr::unsupported(format!(
-                "generated MMA fragment must be an array of {expected_len} scalar registers"
-            ))
-        );
-    }
-    let mut registers = Vec::with_capacity(expected_len);
-    for index in 0..expected_len {
-        let extract = Operation::new(
-            ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![expected_element_ty],
-            vec![array],
-            vec![],
-            0,
-        );
-        extract.deref_mut(ctx).set_loc(loc.clone());
-        let extract = MirExtractFieldOp::new(extract);
-        extract.set_attr_index(ctx, FieldIndexAttr(index as u32));
-        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
-        last_op = Some(extract.get_operation());
-        registers.push(extract.get_operation().deref(ctx).get_result(0));
-    }
-    Ok((
-        registers,
-        last_op.expect("non-empty generated MMA fragment"),
-    ))
-}
-
-#[allow(clippy::too_many_arguments)]
-fn import_generated_mma_operands(
-    ctx: &mut Context,
-    body: &mir::Body,
-    args: &[mir::Operand],
-    block_ptr: Ptr<BasicBlock>,
-    prev_op: Option<Ptr<Operation>>,
-    value_map: &mut ValueMap,
-    loc: Location,
-    adapter: GeneratedMmaImportAdapter,
-) -> TranslationResult<(Vec<Value>, Ptr<Operation>, TypeHandle, usize)> {
-    let f32_ty: TypeHandle = FP32Type::get(ctx).into();
-    let f64_ty: TypeHandle = FP64Type::get(ctx).into();
-    let i32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Signed).into();
-    let u32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-    let (c_ty, c_count, a_ty, a_count, a_array, b_ty, b_count, b_array, result_ty, result_count) =
-        match adapter {
-            GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32 => {
-                (u32_ty, 2, u32_ty, 2, true, u32_ty, 1, false, u32_ty, 2)
-            }
-            GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32 => {
-                (u32_ty, 2, u32_ty, 4, true, u32_ty, 2, true, u32_ty, 2)
-            }
-            GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32 => {
-                (u32_ty, 2, u32_ty, 4, true, u32_ty, 4, true, u32_ty, 2)
-            }
-            GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32 => {
-                (f32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, f32_ty, 4)
-            }
-            GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32 => {
-                (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4)
-            }
-            GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32 => {
-                (f32_ty, 4, u32_ty, 4, true, u32_ty, 4, true, f32_ty, 4)
-            }
-            GeneratedMmaImportAdapter::C2F64A1F64B1F64ToD2F64 => {
-                (f64_ty, 2, f64_ty, 1, false, f64_ty, 1, false, f64_ty, 2)
-            }
-            GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32 => {
-                (i32_ty, 2, u32_ty, 1, false, u32_ty, 1, false, i32_ty, 2)
-            }
-            GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32 => {
-                (i32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, i32_ty, 4)
-            }
-            GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32 => {
-                (i32_ty, 4, u32_ty, 4, true, u32_ty, 4, true, i32_ty, 4)
-            }
-            GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32 => {
-                (i32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, i32_ty, 4)
-            }
-            GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32 => {
-                (i32_ty, 4, u32_ty, 2, true, u32_ty, 2, true, i32_ty, 4)
-            }
-            GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => {
-                (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4)
-            }
-        };
-    let (c_array, last_op) = rvalue::translate_operand(
-        ctx,
-        body,
-        &args[0],
-        value_map,
-        block_ptr,
-        prev_op,
-        loc.clone(),
-    )?;
-    let (mut operands, last_op) =
-        extract_generated_mma_array(ctx, c_array, c_ty, c_count, block_ptr, last_op, loc.clone())?;
-    let (a_value, last_after_a) = rvalue::translate_operand(
-        ctx,
-        body,
-        &args[1],
-        value_map,
-        block_ptr,
-        Some(last_op),
-        loc.clone(),
-    )?;
-    let (a_registers, last_op) = if a_array {
-        extract_generated_mma_array(
-            ctx,
-            a_value,
-            a_ty,
-            a_count,
-            block_ptr,
-            last_after_a,
-            loc.clone(),
-        )?
-    } else {
-        (
-            vec![a_value],
-            last_after_a.expect("generated MMA A translation keeps predecessor"),
-        )
-    };
-    operands.extend(a_registers);
-    let (b_value, last_after_b) = rvalue::translate_operand(
-        ctx,
-        body,
-        &args[2],
-        value_map,
-        block_ptr,
-        Some(last_op),
-        loc.clone(),
-    )?;
-    let (b_registers, last_op) = if b_array {
-        extract_generated_mma_array(
-            ctx,
-            b_value,
-            b_ty,
-            b_count,
-            block_ptr,
-            last_after_b,
-            loc.clone(),
-        )?
-    } else {
-        (
-            vec![b_value],
-            last_after_b.expect("generated MMA B translation keeps predecessor"),
-        )
-    };
-    operands.extend(b_registers);
-    let mut last_op = last_op;
-    if matches!(
-        adapter,
-        GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
-    ) {
-        for arg in &args[3..] {
-            let (value, translated) = rvalue::translate_operand(
-                ctx,
-                body,
-                arg,
-                value_map,
-                block_ptr,
-                Some(last_op),
-                loc.clone(),
-            )?;
-            last_op = translated
-                .expect("generated block-scale MMA operand translation keeps predecessor");
-            operands.push(value);
-        }
-    }
-    Ok((operands, last_op, result_ty, result_count))
-}
-
-fn bundle_generated_mma_results(
-    ctx: &mut Context,
-    mma: Ptr<Operation>,
-    result_ty: TypeHandle,
-    result_count: usize,
-    loc: Location,
-) -> (Value, Ptr<Operation>) {
-    let results = (0..result_count)
-        .map(|index| mma.deref(ctx).get_result(index))
-        .collect();
-    let array_ty = MirArrayType::get(ctx, result_ty, result_count as u64);
-    let array = Operation::new(
-        ctx,
-        MirConstructArrayOp::get_concrete_op_info(),
-        vec![array_ty.into()],
-        results,
-        vec![],
-        0,
-    );
-    array.deref_mut(ctx).set_loc(loc);
-    array.insert_after(ctx, mma);
-    (array.deref(ctx).get_result(0), array)
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-
-    #[test]
-    fn abs_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"),
-            Some("v1:i0070")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::abs_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::abs_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::abs_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::abs_bf16x2"),
-            Some("v1:i0070")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0070"
-        ));
-    }
-    #[test]
-    fn abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"),
-            Some("v1:i0080")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::abs_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16x2::abs_f16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::abs_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::abs_f16x2"),
-            Some("v1:i0080")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0080"
-        ));
-    }
-    #[test]
-    fn active_mask_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"),
-            Some("v1:i0044")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::active_mask"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::active_mask"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::active_mask"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::active_mask"),
-            Some("v1:i0044")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0044"
-        ));
-    }
-    #[test]
-    fn add_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"),
-            Some("v1:i0064")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::add_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::add_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::add_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::add_bf16x2"),
-            Some("v1:i0064")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0064"
-        ));
-    }
-    #[test]
-    fn add_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"),
-            Some("v1:i0074")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::add_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16x2::add_f16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::add_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::add_f16x2"),
-            Some("v1:i0074")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0074"
-        ));
-    }
-    #[test]
-    fn add_f32x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"),
-            Some("v1:i0995")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f32x2::add_f32x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f32x2::add_f32x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f32x2::add_f32x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f32x2::add_f32x2"),
-            Some("v1:i0995")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0995"
-        ));
-    }
-    #[test]
-    fn add_ftz_f32x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"),
-            Some("v1:i0996")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f32x2::add_ftz_f32x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f32x2::add_ftz_f32x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f32x2::add_ftz_f32x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f32x2::add_ftz_f32x2"),
-            Some("v1:i0996")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0996"
-        ));
-    }
-    #[test]
-    fn add_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"),
-            Some("v1:i0446")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rm_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rm_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rm_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rm_f32"),
-            Some("v1:i0446")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0446"
-        ));
-    }
-    #[test]
-    fn add_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"),
-            Some("v1:i0436")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rm_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rm_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rm_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rm_f64"),
-            Some("v1:i0436")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0436"
-        ));
-    }
-    #[test]
-    fn add_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"),
-            Some("v1:i0447")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rm_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rm_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rm_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rm_ftz_f32"),
-            Some("v1:i0447")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0447"
-        ));
-    }
-    #[test]
-    fn add_rm_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"),
-            Some("v1:i0449")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rm_ftz_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rm_ftz_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rm_ftz_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rm_ftz_sat_f32"),
-            Some("v1:i0449")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0449"
-        ));
-    }
-    #[test]
-    fn add_rm_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"),
-            Some("v1:i0448")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rm_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rm_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rm_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rm_sat_f32"),
-            Some("v1:i0448")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0448"
-        ));
-    }
-    #[test]
-    fn add_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"),
-            Some("v1:i0438")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rn_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rn_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rn_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rn_f32"),
-            Some("v1:i0438")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0438"
-        ));
-    }
-    #[test]
-    fn add_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"),
-            Some("v1:i0434")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rn_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rn_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rn_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rn_f64"),
-            Some("v1:i0434")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0434"
-        ));
-    }
-    #[test]
-    fn add_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"),
-            Some("v1:i0439")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rn_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rn_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rn_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rn_ftz_f32"),
-            Some("v1:i0439")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0439"
-        ));
-    }
-    #[test]
-    fn add_rn_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"),
-            Some("v1:i0441")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rn_ftz_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rn_ftz_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rn_ftz_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rn_ftz_sat_f32"),
-            Some("v1:i0441")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0441"
-        ));
-    }
-    #[test]
-    fn add_rn_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"),
-            Some("v1:i0440")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rn_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rn_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rn_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rn_sat_f32"),
-            Some("v1:i0440")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0440"
-        ));
-    }
-    #[test]
-    fn add_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"),
-            Some("v1:i0450")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rp_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rp_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rp_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rp_f32"),
-            Some("v1:i0450")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0450"
-        ));
-    }
-    #[test]
-    fn add_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"),
-            Some("v1:i0437")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rp_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rp_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rp_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rp_f64"),
-            Some("v1:i0437")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0437"
-        ));
-    }
-    #[test]
-    fn add_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"),
-            Some("v1:i0451")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rp_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rp_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rp_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rp_ftz_f32"),
-            Some("v1:i0451")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0451"
-        ));
-    }
-    #[test]
-    fn add_rp_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"),
-            Some("v1:i0453")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rp_ftz_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rp_ftz_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rp_ftz_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rp_ftz_sat_f32"),
-            Some("v1:i0453")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0453"
-        ));
-    }
-    #[test]
-    fn add_rp_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"),
-            Some("v1:i0452")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rp_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rp_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rp_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rp_sat_f32"),
-            Some("v1:i0452")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0452"
-        ));
-    }
-    #[test]
-    fn add_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"),
-            Some("v1:i0442")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rz_f32"),
-            Some("v1:i0442")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0442"
-        ));
-    }
-    #[test]
-    fn add_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"),
-            Some("v1:i0435")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rz_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rz_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rz_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rz_f64"),
-            Some("v1:i0435")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0435"
-        ));
-    }
-    #[test]
-    fn add_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"),
-            Some("v1:i0443")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rz_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rz_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rz_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rz_ftz_f32"),
-            Some("v1:i0443")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0443"
-        ));
-    }
-    #[test]
-    fn add_rz_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"),
-            Some("v1:i0445")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rz_ftz_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rz_ftz_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rz_ftz_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rz_ftz_sat_f32"),
-            Some("v1:i0445")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0445"
-        ));
-    }
-    #[test]
-    fn add_rz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"),
-            Some("v1:i0444")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::add_rz_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::add_rz_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::add_rz_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::add_rz_sat_f32"),
-            Some("v1:i0444")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0444"
-        ));
-    }
-    #[test]
-    fn all_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040"),
-            Some("v1:i0040")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::all_sync"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::warp::all_sync"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::all_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::all_sync"),
-            Some("v1:i0040")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0040"
-        ));
-    }
-    #[test]
-    fn any_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041"),
-            Some("v1:i0041")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::any_sync"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::warp::any_sync"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::any_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::any_sync"),
-            Some("v1:i0041")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0041"
-        ));
-    }
-    #[test]
-    fn ballot_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"),
-            Some("v1:i0042")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::ballot_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::ballot_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::ballot_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::ballot_sync"),
-            Some("v1:i0042")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0042"
-        ));
-    }
-    #[test]
-    fn barrier_cluster_arrive_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"),
-            Some("v1:i0277")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::cluster::barrier_cluster_arrive"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_arrive"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_arrive"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_arrive"),
-            Some("v1:i0277")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0277"
-        ));
-    }
-    #[test]
-    fn barrier_cluster_arrive_aligned_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"),
-            Some("v1:i0278")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::cluster::barrier_cluster_arrive_aligned"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_arrive_aligned"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_arrive_aligned"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_arrive_aligned"),
-            Some("v1:i0278")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0278"
-        ));
-    }
-    #[test]
-    fn barrier_cluster_arrive_relaxed_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"),
-            Some("v1:i0279")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::cluster::barrier_cluster_arrive_relaxed"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_arrive_relaxed"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_arrive_relaxed"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_arrive_relaxed"),
-            Some("v1:i0279")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0279"
-        ));
-    }
-    #[test]
-    fn barrier_cluster_arrive_relaxed_aligned_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"),
-            Some("v1:i0280")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::cluster::barrier_cluster_arrive_relaxed_aligned"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned"
-            ),
-            Some("v1:i0280")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0280"
-        ));
-    }
-    #[test]
-    fn barrier_cluster_wait_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"),
-            Some("v1:i0281")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::cluster::barrier_cluster_wait"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_wait"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_wait"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_wait"),
-            Some("v1:i0281")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0281"
-        ));
-    }
-    #[test]
-    fn barrier_cluster_wait_aligned_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"),
-            Some("v1:i0282")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::cluster::barrier_cluster_wait_aligned"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_wait_aligned"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::barrier_cluster_wait_aligned"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_wait_aligned"),
-            Some("v1:i0282")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0282"
-        ));
-    }
-    #[test]
-    fn barrier_cta_arrive_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"),
-            Some("v1:i0885")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::barrier_cta_arrive"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::barrier_cta_arrive"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::barrier_cta_arrive"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::barrier_cta_arrive"),
-            Some("v1:i0885")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0885"
-        ));
-    }
-    #[test]
-    fn barrier_cta_arrive_aligned_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"),
-            Some("v1:i0886")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::barrier_cta_arrive_aligned"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::barrier_cta_arrive_aligned"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::barrier_cta_arrive_aligned"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::barrier_cta_arrive_aligned"),
-            Some("v1:i0886")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0886"
-        ));
-    }
-    #[test]
-    fn barrier_cta_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"),
-            Some("v1:i0883")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::barrier_cta_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::barrier_cta_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::barrier_cta_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::barrier_cta_sync"),
-            Some("v1:i0883")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0883"
-        ));
-    }
-    #[test]
-    fn barrier_cta_sync_aligned_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"),
-            Some("v1:i0884")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::barrier_cta_sync_aligned"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::barrier_cta_sync_aligned"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::barrier_cta_sync_aligned"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::barrier_cta_sync_aligned"),
-            Some("v1:i0884")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0884"
-        ));
-    }
-    #[test]
-    fn block_dim_x_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"),
-            Some("v1:i0003")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::block_dim_x"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::blockDim_x"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::blockDim_x"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::blockDim_x"),
-            Some("v1:i0003")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::blockDim_x"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::blockDim_x"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::blockDim_x"),
-            Some("v1:i0003")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0003"
-        ));
-    }
-    #[test]
-    fn block_dim_y_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"),
-            Some("v1:i0007")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::block_dim_y"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::blockDim_y"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::blockDim_y"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::blockDim_y"),
-            Some("v1:i0007")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::blockDim_y"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::blockDim_y"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::blockDim_y"),
-            Some("v1:i0007")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0007"
-        ));
-    }
-    #[test]
-    fn block_dim_z_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"),
-            Some("v1:i0011")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::block_dim_z"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::blockDim_z"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::blockDim_z"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::blockDim_z"),
-            Some("v1:i0011")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::blockDim_z"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::blockDim_z"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::blockDim_z"),
-            Some("v1:i0011")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0011"
-        ));
-    }
-    #[test]
-    fn block_idx_x_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"),
-            Some("v1:i0002")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::block_idx_x"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::blockIdx_x"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::blockIdx_x"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::blockIdx_x"),
-            Some("v1:i0002")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::blockIdx_x"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::blockIdx_x"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::blockIdx_x"),
-            Some("v1:i0002")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0002"
-        ));
-    }
-    #[test]
-    fn block_idx_y_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"),
-            Some("v1:i0006")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::block_idx_y"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::blockIdx_y"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::blockIdx_y"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::blockIdx_y"),
-            Some("v1:i0006")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::blockIdx_y"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::blockIdx_y"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::blockIdx_y"),
-            Some("v1:i0006")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0006"
-        ));
-    }
-    #[test]
-    fn block_idx_z_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"),
-            Some("v1:i0010")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::block_idx_z"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::blockIdx_z"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::blockIdx_z"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::blockIdx_z"),
-            Some("v1:i0010")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::blockIdx_z"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::blockIdx_z"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::blockIdx_z"),
-            Some("v1:i0010")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0010"
-        ));
-    }
-    #[test]
-    fn breakpoint_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"),
-            Some("v1:i0296")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::debug::breakpoint"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::debug::breakpoint"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::debug::breakpoint"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::debug::breakpoint"),
-            Some("v1:i0296")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0296"
-        ));
-    }
-    #[test]
-    fn clc_query_get_first_ctaid_x_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"),
-            Some("v1:i0325")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::clc::clc_query_get_first_ctaid_x"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::clc::clc_query_get_first_ctaid_x"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::clc::clc_query_get_first_ctaid_x"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::clc::clc_query_get_first_ctaid_x"),
-            Some("v1:i0325")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0325"
-        ));
-    }
-    #[test]
-    fn clc_query_get_first_ctaid_y_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"),
-            Some("v1:i0326")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::clc::clc_query_get_first_ctaid_y"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::clc::clc_query_get_first_ctaid_y"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::clc::clc_query_get_first_ctaid_y"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::clc::clc_query_get_first_ctaid_y"),
-            Some("v1:i0326")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0326"
-        ));
-    }
-    #[test]
-    fn clc_query_get_first_ctaid_z_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"),
-            Some("v1:i0327")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::clc::clc_query_get_first_ctaid_z"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::clc::clc_query_get_first_ctaid_z"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::clc::clc_query_get_first_ctaid_z"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::clc::clc_query_get_first_ctaid_z"),
-            Some("v1:i0327")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0327"
-        ));
-    }
-    #[test]
-    fn clc_query_is_canceled_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"),
-            Some("v1:i0324")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::clc::clc_query_is_canceled"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::clc::clc_query_is_canceled"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::clc::clc_query_is_canceled"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::clc::clc_query_is_canceled"),
-            Some("v1:i0324")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0324"
-        ));
-    }
-    #[test]
-    fn clc_try_cancel_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"),
-            Some("v1:i0322")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::clc::clc_try_cancel"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::clc::clc_try_cancel"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::clc::clc_try_cancel"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::clc::clc_try_cancel"),
-            Some("v1:i0322")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0322"
-        ));
-    }
-    #[test]
-    fn clc_try_cancel_multicast_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"),
-            Some("v1:i0323")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::clc::clc_try_cancel_multicast"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::clc::clc_try_cancel_multicast"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::clc::clc_try_cancel_multicast"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::clc::clc_try_cancel_multicast"),
-            Some("v1:i0323")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0323"
-        ));
-    }
-    #[test]
-    fn clock_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283"),
-            Some("v1:i0283")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::debug::clock"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::debug::clock"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::debug::clock"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::debug::clock"),
-            Some("v1:i0283")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0283"
-        ));
-    }
-    #[test]
-    fn clock64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284"),
-            Some("v1:i0284")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::debug::clock64"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::debug::clock64"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::debug::clock64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::debug::clock64"),
-            Some("v1:i0284")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0284"
-        ));
-    }
-    #[test]
-    fn cluster_block_count_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276"),
-            Some("v1:i0276")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_block_count"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0276"
-        ));
-    }
-    #[test]
-    fn cluster_block_idx_x_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"),
-            Some("v1:i0263")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_block_idx_x"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_ctaidX"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_ctaidX"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::cluster_ctaidX"),
-            Some("v1:i0263")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0263"
-        ));
-    }
-    #[test]
-    fn cluster_block_idx_y_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"),
-            Some("v1:i0264")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_block_idx_y"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_ctaidY"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_ctaidY"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::cluster_ctaidY"),
-            Some("v1:i0264")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0264"
-        ));
-    }
-    #[test]
-    fn cluster_block_idx_z_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"),
-            Some("v1:i0265")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_block_idx_z"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_ctaidZ"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_ctaidZ"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::cluster_ctaidZ"),
-            Some("v1:i0265")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0265"
-        ));
-    }
-    #[test]
-    fn cluster_block_rank_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275"),
-            Some("v1:i0275")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_block_rank"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0275"
-        ));
-    }
-    #[test]
-    fn cluster_dim_x_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"),
-            Some("v1:i0266")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_dim_x"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_nctaidX"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_nctaidX"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::cluster_nctaidX"),
-            Some("v1:i0266")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0266"
-        ));
-    }
-    #[test]
-    fn cluster_dim_y_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"),
-            Some("v1:i0267")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_dim_y"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_nctaidY"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_nctaidY"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::cluster_nctaidY"),
-            Some("v1:i0267")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0267"
-        ));
-    }
-    #[test]
-    fn cluster_dim_z_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"),
-            Some("v1:i0268")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_dim_z"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_nctaidZ"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::cluster_nctaidZ"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::cluster_nctaidZ"),
-            Some("v1:i0268")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0268"
-        ));
-    }
-    #[test]
-    fn cluster_grid_dim_x_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"),
-            Some("v1:i0272")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_grid_dim_x"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_grid_dimX"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_grid_dimX"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::__cluster_grid_dimX"),
-            Some("v1:i0272")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0272"
-        ));
-    }
-    #[test]
-    fn cluster_grid_dim_y_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"),
-            Some("v1:i0273")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_grid_dim_y"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_grid_dimY"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_grid_dimY"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::__cluster_grid_dimY"),
-            Some("v1:i0273")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0273"
-        ));
-    }
-    #[test]
-    fn cluster_grid_dim_z_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"),
-            Some("v1:i0274")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_grid_dim_z"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_grid_dimZ"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_grid_dimZ"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::__cluster_grid_dimZ"),
-            Some("v1:i0274")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0274"
-        ));
-    }
-    #[test]
-    fn cluster_idx_x_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"),
-            Some("v1:i0269")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_idx_x"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_idxX"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_idxX"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::__cluster_idxX"),
-            Some("v1:i0269")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0269"
-        ));
-    }
-    #[test]
-    fn cluster_idx_y_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"),
-            Some("v1:i0270")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_idx_y"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_idxY"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_idxY"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::__cluster_idxY"),
-            Some("v1:i0270")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0270"
-        ));
-    }
-    #[test]
-    fn cluster_idx_z_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"),
-            Some("v1:i0271")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::cluster_idx_z"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_idxZ"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::__cluster_idxZ"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::__cluster_idxZ"),
-            Some("v1:i0271")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0271"
-        ));
-    }
-    #[test]
-    fn cos_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"),
-            Some("v1:i0784")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::cos_approx_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::cos_approx_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::cos_approx_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::cos_approx_f32"),
-            Some("v1:i0784")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0784"
-        ));
-    }
-    #[test]
-    fn cos_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"),
-            Some("v1:i0785")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::cos_approx_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::cos_approx_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::cos_approx_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::cos_approx_ftz_f32"),
-            Some("v1:i0785")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0785"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_commit_group_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"),
-            Some("v1:i0340")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_commit_group"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_commit_group"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_commit_group"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_commit_group"),
-            Some("v1:i0340")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0340"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_1d_l2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"),
-            Some("v1:i0888")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_1d_l2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2"),
-            Some("v1:i0888")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0888"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_1d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"),
-            Some("v1:i0917")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
-            ),
-            Some("v1:i0917")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0917"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_2d_l2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"),
-            Some("v1:i0889")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_2d_l2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2"),
-            Some("v1:i0889")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0889"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_2d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"),
-            Some("v1:i0918")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
-            ),
-            Some("v1:i0918")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0918"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_3d_l2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"),
-            Some("v1:i0890")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_3d_l2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2"),
-            Some("v1:i0890")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0890"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_3d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"),
-            Some("v1:i0919")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
-            ),
-            Some("v1:i0919")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0919"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_4d_l2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"),
-            Some("v1:i0891")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_4d_l2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2"),
-            Some("v1:i0891")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0891"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_4d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"),
-            Some("v1:i0920")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
-            ),
-            Some("v1:i0920")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0920"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_5d_l2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"),
-            Some("v1:i0892")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_5d_l2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2"),
-            Some("v1:i0892")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0892"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_5d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"),
-            Some("v1:i0921")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
-            ),
-            Some("v1:i0921")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0921"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_gather4_2d_l2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"),
-            Some("v1:i0893")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2"
-            ),
-            Some("v1:i0893")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0893"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"),
-            Some("v1:i0922")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
-            ),
-            Some("v1:i0922")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0922"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_1d_g2s_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"),
-            Some("v1:i0328")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_1d_g2s"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_1d_g2s"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_1d_g2s"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_1d_g2s"),
-            Some("v1:i0328")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0328"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_1d_s2g_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"),
-            Some("v1:i0335")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_1d_s2g"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_1d_s2g"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_1d_s2g"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_1d_s2g"),
-            Some("v1:i0335")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0335"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_2d_g2s_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"),
-            Some("v1:i0329")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_2d_g2s"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_2d_g2s"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_2d_g2s"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_2d_g2s"),
-            Some("v1:i0329")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0329"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_2d_g2s_multicast_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"),
-            Some("v1:i0330")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_2d_g2s_multicast"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast"),
-            Some("v1:i0330")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0330"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_2d_g2s_multicast_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"),
-            Some("v1:i0331")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2"
-            ),
-            Some("v1:i0331")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0331"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_2d_s2g_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"),
-            Some("v1:i0336")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_2d_s2g"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_2d_s2g"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_2d_s2g"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_2d_s2g"),
-            Some("v1:i0336")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0336"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_3d_g2s_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"),
-            Some("v1:i0332")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_3d_g2s"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_3d_g2s"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_3d_g2s"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_3d_g2s"),
-            Some("v1:i0332")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0332"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_3d_s2g_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"),
-            Some("v1:i0337")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_3d_s2g"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_3d_s2g"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_3d_s2g"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_3d_s2g"),
-            Some("v1:i0337")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0337"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_4d_g2s_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"),
-            Some("v1:i0333")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_4d_g2s"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_4d_g2s"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_4d_g2s"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_4d_g2s"),
-            Some("v1:i0333")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0333"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_4d_s2g_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"),
-            Some("v1:i0338")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_4d_s2g"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_4d_s2g"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_4d_s2g"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_4d_s2g"),
-            Some("v1:i0338")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0338"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_5d_g2s_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"),
-            Some("v1:i0334")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_5d_g2s"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_5d_g2s"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_5d_g2s"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_5d_g2s"),
-            Some("v1:i0334")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0334"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_5d_s2g_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"),
-            Some("v1:i0339")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_5d_s2g"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_5d_s2g"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_5d_s2g"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_5d_s2g"),
-            Some("v1:i0339")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0339"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_add_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"),
-            Some("v1:i0928")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_im2col_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d"
-            ),
-            Some("v1:i0928")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0928"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_add_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"),
-            Some("v1:i0929")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_im2col_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d"
-            ),
-            Some("v1:i0929")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0929"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_add_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"),
-            Some("v1:i0930")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_im2col_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d"
-            ),
-            Some("v1:i0930")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0930"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_add_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"),
-            Some("v1:i0923")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_tile_1d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d"),
-            Some("v1:i0923")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0923"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_add_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"),
-            Some("v1:i0924")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_tile_2d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d"),
-            Some("v1:i0924")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0924"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_add_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"),
-            Some("v1:i0925")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_tile_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d"),
-            Some("v1:i0925")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0925"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_add_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"),
-            Some("v1:i0926")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_tile_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d"),
-            Some("v1:i0926")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0926"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_add_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"),
-            Some("v1:i0927")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_tile_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d"),
-            Some("v1:i0927")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0927"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_and_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"),
-            Some("v1:i0936")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_im2col_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d"
-            ),
-            Some("v1:i0936")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0936"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_and_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"),
-            Some("v1:i0937")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_im2col_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d"
-            ),
-            Some("v1:i0937")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0937"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_and_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"),
-            Some("v1:i0938")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_im2col_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d"
-            ),
-            Some("v1:i0938")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0938"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_and_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"),
-            Some("v1:i0931")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_tile_1d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d"),
-            Some("v1:i0931")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0931"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_and_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"),
-            Some("v1:i0932")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_tile_2d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d"),
-            Some("v1:i0932")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0932"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_and_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"),
-            Some("v1:i0933")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_tile_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d"),
-            Some("v1:i0933")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0933"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_and_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"),
-            Some("v1:i0934")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_tile_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d"),
-            Some("v1:i0934")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0934"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_and_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"),
-            Some("v1:i0935")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_tile_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d"),
-            Some("v1:i0935")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0935"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_dec_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"),
-            Some("v1:i0944")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d"
-            ),
-            Some("v1:i0944")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0944"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_dec_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"),
-            Some("v1:i0945")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d"
-            ),
-            Some("v1:i0945")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0945"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_dec_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"),
-            Some("v1:i0946")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d"
-            ),
-            Some("v1:i0946")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0946"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_dec_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"),
-            Some("v1:i0939")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_tile_1d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d"),
-            Some("v1:i0939")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0939"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_dec_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"),
-            Some("v1:i0940")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_tile_2d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d"),
-            Some("v1:i0940")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0940"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_dec_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"),
-            Some("v1:i0941")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_tile_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d"),
-            Some("v1:i0941")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0941"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_dec_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"),
-            Some("v1:i0942")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_tile_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d"),
-            Some("v1:i0942")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0942"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_dec_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"),
-            Some("v1:i0943")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_tile_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d"),
-            Some("v1:i0943")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0943"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_inc_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"),
-            Some("v1:i0952")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d"
-            ),
-            Some("v1:i0952")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0952"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_inc_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"),
-            Some("v1:i0953")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d"
-            ),
-            Some("v1:i0953")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0953"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_inc_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"),
-            Some("v1:i0954")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d"
-            ),
-            Some("v1:i0954")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0954"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_inc_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"),
-            Some("v1:i0947")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_tile_1d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d"),
-            Some("v1:i0947")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0947"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_inc_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"),
-            Some("v1:i0948")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_tile_2d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d"),
-            Some("v1:i0948")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0948"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_inc_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"),
-            Some("v1:i0949")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_tile_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d"),
-            Some("v1:i0949")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0949"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_inc_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"),
-            Some("v1:i0950")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_tile_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d"),
-            Some("v1:i0950")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0950"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_inc_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"),
-            Some("v1:i0951")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_tile_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d"),
-            Some("v1:i0951")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0951"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_max_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"),
-            Some("v1:i0960")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_im2col_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d"
-            ),
-            Some("v1:i0960")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0960"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_max_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"),
-            Some("v1:i0961")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_im2col_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d"
-            ),
-            Some("v1:i0961")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0961"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_max_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"),
-            Some("v1:i0962")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_im2col_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d"
-            ),
-            Some("v1:i0962")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0962"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_max_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"),
-            Some("v1:i0955")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_tile_1d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d"),
-            Some("v1:i0955")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0955"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_max_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"),
-            Some("v1:i0956")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_tile_2d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d"),
-            Some("v1:i0956")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0956"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_max_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"),
-            Some("v1:i0957")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_tile_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d"),
-            Some("v1:i0957")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0957"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_max_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"),
-            Some("v1:i0958")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_tile_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d"),
-            Some("v1:i0958")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0958"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_max_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"),
-            Some("v1:i0959")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_tile_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d"),
-            Some("v1:i0959")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0959"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_min_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"),
-            Some("v1:i0968")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_im2col_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d"
-            ),
-            Some("v1:i0968")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0968"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_min_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"),
-            Some("v1:i0969")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_im2col_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d"
-            ),
-            Some("v1:i0969")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0969"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_min_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"),
-            Some("v1:i0970")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_im2col_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d"
-            ),
-            Some("v1:i0970")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0970"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_min_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"),
-            Some("v1:i0963")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_tile_1d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d"),
-            Some("v1:i0963")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0963"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_min_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"),
-            Some("v1:i0964")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_tile_2d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d"),
-            Some("v1:i0964")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0964"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_min_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"),
-            Some("v1:i0965")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_tile_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d"),
-            Some("v1:i0965")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0965"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_min_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"),
-            Some("v1:i0966")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_tile_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d"),
-            Some("v1:i0966")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0966"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_min_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"),
-            Some("v1:i0967")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_tile_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d"),
-            Some("v1:i0967")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0967"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_or_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"),
-            Some("v1:i0976")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_im2col_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d"
-            ),
-            Some("v1:i0976")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0976"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_or_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"),
-            Some("v1:i0977")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_im2col_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d"
-            ),
-            Some("v1:i0977")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0977"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_or_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"),
-            Some("v1:i0978")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_im2col_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d"
-            ),
-            Some("v1:i0978")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0978"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_or_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"),
-            Some("v1:i0971")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_tile_1d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d"),
-            Some("v1:i0971")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0971"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_or_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"),
-            Some("v1:i0972")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_tile_2d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d"),
-            Some("v1:i0972")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0972"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_or_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"),
-            Some("v1:i0973")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_tile_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d"),
-            Some("v1:i0973")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0973"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_or_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"),
-            Some("v1:i0974")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_tile_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d"),
-            Some("v1:i0974")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0974"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_or_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"),
-            Some("v1:i0975")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_tile_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d"),
-            Some("v1:i0975")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0975"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_xor_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"),
-            Some("v1:i0984")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d"
-            ),
-            Some("v1:i0984")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0984"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_xor_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"),
-            Some("v1:i0985")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d"
-            ),
-            Some("v1:i0985")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0985"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_xor_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"),
-            Some("v1:i0986")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d"
-            ),
-            Some("v1:i0986")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0986"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_xor_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"),
-            Some("v1:i0979")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_tile_1d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d"),
-            Some("v1:i0979")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0979"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_xor_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"),
-            Some("v1:i0980")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_tile_2d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d"),
-            Some("v1:i0980")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0980"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_xor_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"),
-            Some("v1:i0981")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_tile_3d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d"),
-            Some("v1:i0981")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0981"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_xor_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"),
-            Some("v1:i0982")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_tile_4d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d"),
-            Some("v1:i0982")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0982"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_tensor_reduce_xor_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"),
-            Some("v1:i0983")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_tile_5d"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d"),
-            Some("v1:i0983")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0983"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_wait_group_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"),
-            Some("v1:i0341")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_wait_group"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_wait_group"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_wait_group"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_wait_group"),
-            Some("v1:i0341")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0341"
-        ));
-    }
-    #[test]
-    fn cp_async_bulk_wait_group_read_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"),
-            Some("v1:i0342")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::cp_async_bulk_wait_group_read"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_wait_group_read"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::cp_async_bulk_wait_group_read"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_wait_group_read"),
-            Some("v1:i0342")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0342"
-        ));
-    }
-    #[test]
-    fn cp_async_ca_16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"),
-            Some("v1:i0090")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_ca_16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_16"),
-            Some("v1:i0090")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0090"
-        ));
-    }
-    #[test]
-    fn cp_async_ca_4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"),
-            Some("v1:i0086")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_ca_4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_4"),
-            Some("v1:i0086")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0086"
-        ));
-    }
-    #[test]
-    fn cp_async_ca_8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"),
-            Some("v1:i0088")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_ca_8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_8"),
-            Some("v1:i0088")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0088"
-        ));
-    }
-    #[test]
-    fn cp_async_ca_zfill_16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"),
-            Some("v1:i0091")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_ca_zfill_16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_zfill_16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_zfill_16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_zfill_16"),
-            Some("v1:i0091")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0091"
-        ));
-    }
-    #[test]
-    fn cp_async_ca_zfill_4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"),
-            Some("v1:i0087")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_ca_zfill_4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_zfill_4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_zfill_4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_zfill_4"),
-            Some("v1:i0087")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0087"
-        ));
-    }
-    #[test]
-    fn cp_async_ca_zfill_8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"),
-            Some("v1:i0089")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_ca_zfill_8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_zfill_8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_ca_zfill_8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_zfill_8"),
-            Some("v1:i0089")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0089"
-        ));
-    }
-    #[test]
-    fn cp_async_cg_16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"),
-            Some("v1:i0092")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_cg_16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_cg_16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_cg_16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_cg_16"),
-            Some("v1:i0092")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0092"
-        ));
-    }
-    #[test]
-    fn cp_async_cg_zfill_16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"),
-            Some("v1:i0093")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_cg_zfill_16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_cg_zfill_16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_cg_zfill_16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_cg_zfill_16"),
-            Some("v1:i0093")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0093"
-        ));
-    }
-    #[test]
-    fn cp_async_commit_group_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"),
-            Some("v1:i0094")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_commit_group"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_commit_group"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_commit_group"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_commit_group"),
-            Some("v1:i0094")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0094"
-        ));
-    }
-    #[test]
-    fn cp_async_mbarrier_arrive_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"),
-            Some("v1:i0101")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_mbarrier_arrive"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_mbarrier_arrive"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_mbarrier_arrive"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_mbarrier_arrive"),
-            Some("v1:i0101")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0101"
-        ));
-    }
-    #[test]
-    fn cp_async_mbarrier_arrive_noinc_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"),
-            Some("v1:i0103")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_mbarrier_arrive_noinc"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_mbarrier_arrive_noinc"),
-            Some("v1:i0103")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0103"
-        ));
-    }
-    #[test]
-    fn cp_async_mbarrier_arrive_noinc_shared_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"),
-            Some("v1:i0104")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_mbarrier_arrive_noinc_shared"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared"
-            ),
-            Some("v1:i0104")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0104"
-        ));
-    }
-    #[test]
-    fn cp_async_mbarrier_arrive_shared_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"),
-            Some("v1:i0102")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_mbarrier_arrive_shared"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_mbarrier_arrive_shared"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_mbarrier_arrive_shared"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_mbarrier_arrive_shared"),
-            Some("v1:i0102")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0102"
-        ));
-    }
-    #[test]
-    fn cp_async_wait_all_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"),
-            Some("v1:i0095")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_wait_all"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_wait_all"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_wait_all"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_wait_all"),
-            Some("v1:i0095")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0095"
-        ));
-    }
-    #[test]
-    fn cp_async_wait_group_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"),
-            Some("v1:i0096")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::async_copy::cp_async_wait_group"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_wait_group"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::async_copy::cp_async_wait_group"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::async_copy::cp_async_wait_group"),
-            Some("v1:i0096")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0096"
-        ));
-    }
-    #[test]
-    fn cvt_f16x2_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"),
-            Some("v1:i0081")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_f16x2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_f16x2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_f16x2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_f16x2_f32"),
-            Some("v1:i0081")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0081"
-        ));
-    }
-    #[test]
-    fn cvt_f32x2_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"),
-            Some("v1:i0071")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_f32x2_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_bf16x2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_bf16x2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_bf16x2_f32"),
-            Some("v1:i0071")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0071"
-        ));
-    }
-    #[test]
-    fn cvt_rn_f16x2_e4m3x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"),
-            Some("v1:i0826")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_f16x2_e4m3x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_f16x2_e4m3x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_f16x2_e4m3x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_f16x2_e4m3x2"),
-            Some("v1:i0826")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0826"
-        ));
-    }
-    #[test]
-    fn cvt_rn_f16x2_e5m2x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"),
-            Some("v1:i0828")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_f16x2_e5m2x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_f16x2_e5m2x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_f16x2_e5m2x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_f16x2_e5m2x2"),
-            Some("v1:i0828")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0828"
-        ));
-    }
-    #[test]
-    fn cvt_rn_relu_bf16x2_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"),
-            Some("v1:i0084")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_relu_bf16x2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_bf16x2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_bf16x2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_bf16x2_f32"),
-            Some("v1:i0084")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0084"
-        ));
-    }
-    #[test]
-    fn cvt_rn_relu_f16x2_e4m3x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"),
-            Some("v1:i0827")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_relu_f16x2_e4m3x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2"),
-            Some("v1:i0827")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0827"
-        ));
-    }
-    #[test]
-    fn cvt_rn_relu_f16x2_e5m2x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"),
-            Some("v1:i0829")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_relu_f16x2_e5m2x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2"),
-            Some("v1:i0829")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0829"
-        ));
-    }
-    #[test]
-    fn cvt_rn_relu_f16x2_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"),
-            Some("v1:i0083")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_relu_f16x2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_f16x2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_f16x2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_f16x2_f32"),
-            Some("v1:i0083")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0083"
-        ));
-    }
-    #[test]
-    fn cvt_rn_relu_satfinite_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"),
-            Some("v1:i0373")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_relu_satfinite_tf32_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32"),
-            Some("v1:i0373")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0373"
-        ));
-    }
-    #[test]
-    fn cvt_rn_relu_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"),
-            Some("v1:i0371")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_relu_tf32_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_tf32_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_relu_tf32_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_tf32_f32"),
-            Some("v1:i0371")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0371"
-        ));
-    }
-    #[test]
-    fn cvt_rn_satfinite_e4m3x2_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"),
-            Some("v1:i0822")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_satfinite_e4m3x2_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2"),
-            Some("v1:i0822")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0822"
-        ));
-    }
-    #[test]
-    fn cvt_rn_satfinite_e4m3x2_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"),
-            Some("v1:i0259")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_satfinite_e4m3x2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32"),
-            Some("v1:i0259")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0259"
-        ));
-    }
-    #[test]
-    fn cvt_rn_satfinite_e5m2x2_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"),
-            Some("v1:i0824")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_satfinite_e5m2x2_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2"),
-            Some("v1:i0824")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0824"
-        ));
-    }
-    #[test]
-    fn cvt_rn_satfinite_e5m2x2_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"),
-            Some("v1:i0261")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_satfinite_e5m2x2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32"),
-            Some("v1:i0261")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0261"
-        ));
-    }
-    #[test]
-    fn cvt_rn_satfinite_relu_e4m3x2_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"),
-            Some("v1:i0823")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2"),
-            Some("v1:i0823")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0823"
-        ));
-    }
-    #[test]
-    fn cvt_rn_satfinite_relu_e4m3x2_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"),
-            Some("v1:i0260")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_satfinite_relu_e4m3x2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32"),
-            Some("v1:i0260")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0260"
-        ));
-    }
-    #[test]
-    fn cvt_rn_satfinite_relu_e5m2x2_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"),
-            Some("v1:i0825")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2"),
-            Some("v1:i0825")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0825"
-        ));
-    }
-    #[test]
-    fn cvt_rn_satfinite_relu_e5m2x2_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"),
-            Some("v1:i0262")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_satfinite_relu_e5m2x2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32"),
-            Some("v1:i0262")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0262"
-        ));
-    }
-    #[test]
-    fn cvt_rn_satfinite_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"),
-            Some("v1:i0372")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_satfinite_tf32_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_tf32_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_satfinite_tf32_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_tf32_f32"),
-            Some("v1:i0372")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0372"
-        ));
-    }
-    #[test]
-    fn cvt_rn_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"),
-            Some("v1:i0370")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rn_tf32_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_tf32_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rn_tf32_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rn_tf32_f32"),
-            Some("v1:i0370")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0370"
-        ));
-    }
-    #[test]
-    fn cvt_rna_satfinite_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"),
-            Some("v1:i0369")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rna_satfinite_tf32_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rna_satfinite_tf32_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rna_satfinite_tf32_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rna_satfinite_tf32_f32"),
-            Some("v1:i0369")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0369"
-        ));
-    }
-    #[test]
-    fn cvt_rna_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"),
-            Some("v1:i0368")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rna_tf32_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rna_tf32_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rna_tf32_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rna_tf32_f32"),
-            Some("v1:i0368")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0368"
-        ));
-    }
-    #[test]
-    fn cvt_rz_bf16x2_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"),
-            Some("v1:i0085")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rz_bf16x2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_bf16x2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_bf16x2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rz_bf16x2_f32"),
-            Some("v1:i0085")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0085"
-        ));
-    }
-    #[test]
-    fn cvt_rz_f16x2_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"),
-            Some("v1:i0082")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rz_f16x2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_f16x2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_f16x2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rz_f16x2_f32"),
-            Some("v1:i0082")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0082"
-        ));
-    }
-    #[test]
-    fn cvt_rz_relu_satfinite_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"),
-            Some("v1:i0377")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rz_relu_satfinite_tf32_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32"),
-            Some("v1:i0377")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0377"
-        ));
-    }
-    #[test]
-    fn cvt_rz_relu_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"),
-            Some("v1:i0375")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rz_relu_tf32_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_relu_tf32_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_relu_tf32_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rz_relu_tf32_f32"),
-            Some("v1:i0375")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0375"
-        ));
-    }
-    #[test]
-    fn cvt_rz_satfinite_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"),
-            Some("v1:i0376")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rz_satfinite_tf32_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_satfinite_tf32_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_satfinite_tf32_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rz_satfinite_tf32_f32"),
-            Some("v1:i0376")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0376"
-        ));
-    }
-    #[test]
-    fn cvt_rz_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"),
-            Some("v1:i0374")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::convert::cvt_rz_tf32_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_tf32_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::convert::cvt_rz_tf32_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::convert::cvt_rz_tf32_f32"),
-            Some("v1:i0374")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0374"
-        ));
-    }
-    #[test]
-    fn div_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"),
-            Some("v1:i0414")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rm_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rm_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rm_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rm_f32"),
-            Some("v1:i0414")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0414"
-        ));
-    }
-    #[test]
-    fn div_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"),
-            Some("v1:i0396")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rm_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rm_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rm_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rm_f64"),
-            Some("v1:i0396")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0396"
-        ));
-    }
-    #[test]
-    fn div_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"),
-            Some("v1:i0415")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rm_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rm_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rm_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rm_ftz_f32"),
-            Some("v1:i0415")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0415"
-        ));
-    }
-    #[test]
-    fn div_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"),
-            Some("v1:i0410")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rn_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rn_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rn_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rn_f32"),
-            Some("v1:i0410")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0410"
-        ));
-    }
-    #[test]
-    fn div_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"),
-            Some("v1:i0394")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rn_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rn_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rn_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rn_f64"),
-            Some("v1:i0394")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0394"
-        ));
-    }
-    #[test]
-    fn div_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"),
-            Some("v1:i0411")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rn_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rn_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rn_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rn_ftz_f32"),
-            Some("v1:i0411")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0411"
-        ));
-    }
-    #[test]
-    fn div_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"),
-            Some("v1:i0416")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rp_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rp_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rp_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rp_f32"),
-            Some("v1:i0416")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0416"
-        ));
-    }
-    #[test]
-    fn div_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"),
-            Some("v1:i0397")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rp_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rp_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rp_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rp_f64"),
-            Some("v1:i0397")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0397"
-        ));
-    }
-    #[test]
-    fn div_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"),
-            Some("v1:i0417")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rp_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rp_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rp_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rp_ftz_f32"),
-            Some("v1:i0417")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0417"
-        ));
-    }
-    #[test]
-    fn div_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"),
-            Some("v1:i0412")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rz_f32"),
-            Some("v1:i0412")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0412"
-        ));
-    }
-    #[test]
-    fn div_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"),
-            Some("v1:i0395")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rz_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rz_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rz_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rz_f64"),
-            Some("v1:i0395")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0395"
-        ));
-    }
-    #[test]
-    fn div_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"),
-            Some("v1:i0413")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::div_rz_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::div_rz_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::div_rz_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::div_rz_ftz_f32"),
-            Some("v1:i0413")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0413"
-        ));
-    }
-    #[test]
-    fn dp2a_s32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"),
-            Some("v1:i0032")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::dotprod::dp2a_s32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::dotprod::dp2a_s32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::dotprod::dp2a_s32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::dotprod::dp2a_s32"),
-            Some("v1:i0032")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0032"
-        ));
-    }
-    #[test]
-    fn dp2a_u32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"),
-            Some("v1:i0033")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::dotprod::dp2a_u32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::dotprod::dp2a_u32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::dotprod::dp2a_u32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::dotprod::dp2a_u32"),
-            Some("v1:i0033")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0033"
-        ));
-    }
-    #[test]
-    fn dp4a_s32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"),
-            Some("v1:i0030")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::dotprod::dp4a_s32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::dotprod::dp4a_s32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::dotprod::dp4a_s32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::dotprod::dp4a_s32"),
-            Some("v1:i0030")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0030"
-        ));
-    }
-    #[test]
-    fn dp4a_u32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"),
-            Some("v1:i0031")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::dotprod::dp4a_u32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::dotprod::dp4a_u32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::dotprod::dp4a_u32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::dotprod::dp4a_u32"),
-            Some("v1:i0031")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0031"
-        ));
-    }
-    #[test]
-    fn dsmem_read_u32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"),
-            Some("v1:i0321")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::cluster::dsmem_read_u32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::dsmem_read_u32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::dsmem_read_u32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::dsmem_read_u32"),
-            Some("v1:i0321")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0321"
-        ));
-    }
-    #[test]
-    fn dynamic_smem_size_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"),
-            Some("v1:i0293")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::shared::dynamic_smem_size"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::shared::dynamic_smem_size"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::shared::dynamic_smem_size"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::shared::dynamic_smem_size"),
-            Some("v1:i0293")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0293"
-        ));
-    }
-    #[test]
-    fn elect_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"),
-            Some("v1:i0367")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::elect_sync"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::warp::elect_sync"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::elect_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::elect_sync"),
-            Some("v1:i0367")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0367"
-        ));
-    }
-    #[test]
-    fn envreg1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286"),
-            Some("v1:i0286")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::grid::envreg1"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::grid::envreg1"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::grid::envreg1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::grid::envreg1"),
-            Some("v1:i0286")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0286"
-        ));
-    }
-    #[test]
-    fn envreg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287"),
-            Some("v1:i0287")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::grid::envreg2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::grid::envreg2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::grid::envreg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::grid::envreg2"),
-            Some("v1:i0287")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0287"
-        ));
-    }
-    #[test]
-    fn ex2_approx_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"),
-            Some("v1:i1016")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::ex2_approx_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::ex2_approx_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::ex2_approx_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::ex2_approx_f16"),
-            Some("v1:i1016")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1016"
-        ));
-    }
-    #[test]
-    fn ex2_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"),
-            Some("v1:i0819")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::ex2_approx_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::ex2_approx_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::ex2_approx_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::ex2_approx_f32"),
-            Some("v1:i0819")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0819"
-        ));
-    }
-    #[test]
-    fn ex2_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"),
-            Some("v1:i0820")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::ex2_approx_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::ex2_approx_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::ex2_approx_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::ex2_approx_ftz_f32"),
-            Some("v1:i0820")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0820"
-        ));
-    }
-    #[test]
-    fn fence_mbarrier_init_release_cluster_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"),
-            Some("v1:i0313")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::fence_mbarrier_init_release_cluster"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::fence_mbarrier_init_release_cluster"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::fence_mbarrier_init_release_cluster"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::fence_mbarrier_init_release_cluster"),
-            Some("v1:i0313")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0313"
-        ));
-    }
-    #[test]
-    fn fence_proxy_async_generic_acquire_shared_cluster_cluster_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"),
-            Some("v1:i0315")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster"
-            ),
-            Some("v1:i0315")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0315"
-        ));
-    }
-    #[test]
-    fn fence_proxy_async_generic_release_shared_cta_cluster_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"),
-            Some("v1:i0314")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::fence_proxy_async_generic_release_shared_cta_cluster"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster"
-            ),
-            Some("v1:i0314")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0314"
-        ));
-    }
-    #[test]
-    fn fence_proxy_async_shared_cta_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"),
-            Some("v1:i0312")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::fence_proxy_async_shared_cta"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::fence_proxy_async_shared_cta"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::fence_proxy_async_shared_cta"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::fence_proxy_async_shared_cta"),
-            Some("v1:i0312")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0312"
-        ));
-    }
-    #[test]
-    fn fence_proxy_tensormap_generic_acquire_cluster_uses_only_canonical_or_compatibility_defpaths()
-    {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"),
-            Some("v1:i0905")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::fence_proxy_tensormap_generic_acquire_cluster"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster"
-            ),
-            Some("v1:i0905")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0905"
-        ));
-    }
-    #[test]
-    fn fence_proxy_tensormap_generic_acquire_cta_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"),
-            Some("v1:i0906")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::fence_proxy_tensormap_generic_acquire_cta"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta"
-            ),
-            Some("v1:i0906")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0906"
-        ));
-    }
-    #[test]
-    fn fence_proxy_tensormap_generic_acquire_gpu_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"),
-            Some("v1:i0907")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::fence_proxy_tensormap_generic_acquire_gpu"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu"
-            ),
-            Some("v1:i0907")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0907"
-        ));
-    }
-    #[test]
-    fn fence_proxy_tensormap_generic_acquire_system_uses_only_canonical_or_compatibility_defpaths()
-    {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"),
-            Some("v1:i0908")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::fence_proxy_tensormap_generic_acquire_system"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system"
-            ),
-            Some("v1:i0908")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0908"
-        ));
-    }
-    #[test]
-    fn fence_proxy_tensormap_generic_release_cluster_uses_only_canonical_or_compatibility_defpaths()
-    {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"),
-            Some("v1:i0909")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::fence_proxy_tensormap_generic_release_cluster"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster"
-            ),
-            Some("v1:i0909")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0909"
-        ));
-    }
-    #[test]
-    fn fence_proxy_tensormap_generic_release_cta_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"),
-            Some("v1:i0910")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::fence_proxy_tensormap_generic_release_cta"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_release_cta"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_release_cta"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::fence_proxy_tensormap_generic_release_cta"
-            ),
-            Some("v1:i0910")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0910"
-        ));
-    }
-    #[test]
-    fn fence_proxy_tensormap_generic_release_gpu_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"),
-            Some("v1:i0911")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::fence_proxy_tensormap_generic_release_gpu"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu"
-            ),
-            Some("v1:i0911")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0911"
-        ));
-    }
-    #[test]
-    fn fence_proxy_tensormap_generic_release_system_uses_only_canonical_or_compatibility_defpaths()
-    {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"),
-            Some("v1:i0912")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::fence_proxy_tensormap_generic_release_system"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_release_system"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::fence_proxy_tensormap_generic_release_system"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tma::fence_proxy_tensormap_generic_release_system"
-            ),
-            Some("v1:i0912")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0912"
-        ));
-    }
-    #[test]
-    fn fma_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"),
-            Some("v1:i0062")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::fma_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::fma_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::fma_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::fma_bf16x2"),
-            Some("v1:i0062")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0062"
-        ));
-    }
-    #[test]
-    fn fma_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"),
-            Some("v1:i0072")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::fma_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16x2::fma_f16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::fma_f16x2"),
-            Some("v1:i0072")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0072"
-        ));
-    }
-    #[test]
-    fn fma_f32x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"),
-            Some("v1:i1001")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f32x2::fma_f32x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f32x2::fma_f32x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f32x2::fma_f32x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f32x2::fma_f32x2"),
-            Some("v1:i1001")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1001"
-        ));
-    }
-    #[test]
-    fn fma_ftz_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"),
-            Some("v1:i0854")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::fma_ftz_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_ftz_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_ftz_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::fma_ftz_f16x2"),
-            Some("v1:i0854")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0854"
-        ));
-    }
-    #[test]
-    fn fma_ftz_f32x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"),
-            Some("v1:i1002")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f32x2::fma_ftz_f32x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f32x2::fma_ftz_f32x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f32x2::fma_ftz_f32x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f32x2::fma_ftz_f32x2"),
-            Some("v1:i1002")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1002"
-        ));
-    }
-    #[test]
-    fn fma_ftz_relu_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"),
-            Some("v1:i0857")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::fma_ftz_relu_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_ftz_relu_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_ftz_relu_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::fma_ftz_relu_f16x2"),
-            Some("v1:i0857")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0857"
-        ));
-    }
-    #[test]
-    fn fma_ftz_sat_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"),
-            Some("v1:i0856")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::fma_ftz_sat_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_ftz_sat_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_ftz_sat_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::fma_ftz_sat_f16x2"),
-            Some("v1:i0856")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0856"
-        ));
-    }
-    #[test]
-    fn fma_relu_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"),
-            Some("v1:i0063")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::fma_relu_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::fma_relu_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::fma_relu_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::fma_relu_bf16x2"),
-            Some("v1:i0063")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0063"
-        ));
-    }
-    #[test]
-    fn fma_relu_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"),
-            Some("v1:i0073")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::fma_relu_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_relu_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_relu_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::fma_relu_f16x2"),
-            Some("v1:i0073")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0073"
-        ));
-    }
-    #[test]
-    fn fma_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"),
-            Some("v1:i0426")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rm_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rm_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rm_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rm_f32"),
-            Some("v1:i0426")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0426"
-        ));
-    }
-    #[test]
-    fn fma_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"),
-            Some("v1:i0400")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rm_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rm_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rm_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rm_f64"),
-            Some("v1:i0400")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0400"
-        ));
-    }
-    #[test]
-    fn fma_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"),
-            Some("v1:i0427")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rm_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rm_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rm_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rm_ftz_f32"),
-            Some("v1:i0427")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0427"
-        ));
-    }
-    #[test]
-    fn fma_rm_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"),
-            Some("v1:i0429")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rm_ftz_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rm_ftz_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rm_ftz_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rm_ftz_sat_f32"),
-            Some("v1:i0429")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0429"
-        ));
-    }
-    #[test]
-    fn fma_rm_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"),
-            Some("v1:i0428")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rm_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rm_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rm_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rm_sat_f32"),
-            Some("v1:i0428")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0428"
-        ));
-    }
-    #[test]
-    fn fma_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"),
-            Some("v1:i0418")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rn_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rn_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rn_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rn_f32"),
-            Some("v1:i0418")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0418"
-        ));
-    }
-    #[test]
-    fn fma_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"),
-            Some("v1:i0398")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rn_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rn_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rn_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rn_f64"),
-            Some("v1:i0398")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0398"
-        ));
-    }
-    #[test]
-    fn fma_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"),
-            Some("v1:i0419")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rn_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rn_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rn_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rn_ftz_f32"),
-            Some("v1:i0419")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0419"
-        ));
-    }
-    #[test]
-    fn fma_rn_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"),
-            Some("v1:i0421")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rn_ftz_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rn_ftz_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rn_ftz_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rn_ftz_sat_f32"),
-            Some("v1:i0421")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0421"
-        ));
-    }
-    #[test]
-    fn fma_rn_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"),
-            Some("v1:i0420")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rn_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rn_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rn_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rn_sat_f32"),
-            Some("v1:i0420")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0420"
-        ));
-    }
-    #[test]
-    fn fma_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"),
-            Some("v1:i0430")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rp_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rp_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rp_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rp_f32"),
-            Some("v1:i0430")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0430"
-        ));
-    }
-    #[test]
-    fn fma_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"),
-            Some("v1:i0401")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rp_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rp_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rp_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rp_f64"),
-            Some("v1:i0401")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0401"
-        ));
-    }
-    #[test]
-    fn fma_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"),
-            Some("v1:i0431")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rp_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rp_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rp_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rp_ftz_f32"),
-            Some("v1:i0431")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0431"
-        ));
-    }
-    #[test]
-    fn fma_rp_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"),
-            Some("v1:i0433")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rp_ftz_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rp_ftz_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rp_ftz_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rp_ftz_sat_f32"),
-            Some("v1:i0433")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0433"
-        ));
-    }
-    #[test]
-    fn fma_rp_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"),
-            Some("v1:i0432")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rp_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rp_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rp_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rp_sat_f32"),
-            Some("v1:i0432")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0432"
-        ));
-    }
-    #[test]
-    fn fma_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"),
-            Some("v1:i0422")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rz_f32"),
-            Some("v1:i0422")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0422"
-        ));
-    }
-    #[test]
-    fn fma_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"),
-            Some("v1:i0399")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rz_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rz_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rz_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rz_f64"),
-            Some("v1:i0399")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0399"
-        ));
-    }
-    #[test]
-    fn fma_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"),
-            Some("v1:i0423")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rz_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rz_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rz_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rz_ftz_f32"),
-            Some("v1:i0423")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0423"
-        ));
-    }
-    #[test]
-    fn fma_rz_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"),
-            Some("v1:i0425")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rz_ftz_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rz_ftz_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rz_ftz_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rz_ftz_sat_f32"),
-            Some("v1:i0425")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0425"
-        ));
-    }
-    #[test]
-    fn fma_rz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"),
-            Some("v1:i0424")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::fma_rz_sat_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::fma_rz_sat_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::fma_rz_sat_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::fma_rz_sat_f32"),
-            Some("v1:i0424")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0424"
-        ));
-    }
-    #[test]
-    fn fma_sat_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"),
-            Some("v1:i0855")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::fma_sat_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_sat_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::fma_sat_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::fma_sat_f16x2"),
-            Some("v1:i0855")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0855"
-        ));
-    }
-    #[test]
-    fn globaltimer_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"),
-            Some("v1:i0285")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::debug::globaltimer"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::debug::globaltimer"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::debug::globaltimer"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::debug::globaltimer"),
-            Some("v1:i0285")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0285"
-        ));
-    }
-    #[test]
-    fn grid_dependency_launch_dependents_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"),
-            Some("v1:i0913")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::grid::grid_dependency_launch_dependents"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::grid::dependency::trigger_dependents"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::grid::dependency::trigger_dependents"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::grid::dependency::trigger_dependents"),
-            Some("v1:i0913")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0913"
-        ));
-    }
-    #[test]
-    fn grid_dependency_wait_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"),
-            Some("v1:i0914")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::grid::grid_dependency_wait"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::grid::dependency::wait"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::grid::dependency::wait"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::grid::dependency::wait"),
-            Some("v1:i0914")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0914"
-        ));
-    }
-    #[test]
-    fn grid_dim_x_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"),
-            Some("v1:i0004")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::grid_dim_x"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::gridDim_x"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::gridDim_x"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::gridDim_x"),
-            Some("v1:i0004")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::gridDim_x"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::gridDim_x"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::gridDim_x"),
-            Some("v1:i0004")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0004"
-        ));
-    }
-    #[test]
-    fn grid_dim_y_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"),
-            Some("v1:i0008")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::grid_dim_y"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::gridDim_y"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::gridDim_y"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::gridDim_y"),
-            Some("v1:i0008")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::gridDim_y"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::gridDim_y"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::gridDim_y"),
-            Some("v1:i0008")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0008"
-        ));
-    }
-    #[test]
-    fn grid_dim_z_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"),
-            Some("v1:i0012")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::grid_dim_z"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::gridDim_z"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::gridDim_z"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::gridDim_z"),
-            Some("v1:i0012")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::gridDim_z"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::gridDim_z"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::gridDim_z"),
-            Some("v1:i0012")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0012"
-        ));
-    }
-    #[test]
-    fn gridid_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"),
-            Some("v1:i0290")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::thread::gridid"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::thread::gridid"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::gridid"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::gridid"),
-            Some("v1:i0290")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::gridid"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::gridid"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::gridid"),
-            Some("v1:i0290")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0290"
-        ));
-    }
-    #[test]
-    fn lane_id_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016"),
-            Some("v1:i0016")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::lane_id"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::warp::lane_id"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::lane_id"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::lane_id"),
-            Some("v1:i0016")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0016"
-        ));
-    }
-    #[test]
-    fn lanemask_eq_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"),
-            Some("v1:i0037")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::lanemask_eq"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::lanemask_eq"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::lanemask_eq"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::lanemask_eq"),
-            Some("v1:i0037")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0037"
-        ));
-    }
-    #[test]
-    fn lanemask_ge_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"),
-            Some("v1:i0038")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::lanemask_ge"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::lanemask_ge"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::lanemask_ge"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::lanemask_ge"),
-            Some("v1:i0038")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0038"
-        ));
-    }
-    #[test]
-    fn lanemask_gt_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"),
-            Some("v1:i0039")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::lanemask_gt"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::lanemask_gt"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::lanemask_gt"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::lanemask_gt"),
-            Some("v1:i0039")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0039"
-        ));
-    }
-    #[test]
-    fn lanemask_le_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"),
-            Some("v1:i0036")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::lanemask_le"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::lanemask_le"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::lanemask_le"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::lanemask_le"),
-            Some("v1:i0036")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0036"
-        ));
-    }
-    #[test]
-    fn lanemask_lt_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"),
-            Some("v1:i0035")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::lanemask_lt"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::lanemask_lt"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::lanemask_lt"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::lanemask_lt"),
-            Some("v1:i0035")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0035"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m16n16_x1_trans_b8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378"),
-            Some("v1:i0378")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m16n16_x1_trans_b8"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0378"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379"),
-            Some("v1:i0379")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0379"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380"),
-            Some("v1:i0380")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0380"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m16n16_x2_trans_b8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381"),
-            Some("v1:i0381")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m16n16_x2_trans_b8"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0381"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382"),
-            Some("v1:i0382")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0382"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383"),
-            Some("v1:i0383")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0383"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n16_x1_b8x16_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384"),
-            Some("v1:i0384")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n16_x1_b8x16_b4x16_p64"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0384"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n16_x1_b8x16_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385"),
-            Some("v1:i0385")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n16_x1_b8x16_b6x16_p32"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0385"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n16_x2_b8x16_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"),
-            Some("v1:i0386")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n16_x2_b8x16_b4x16_p64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64"),
-            Some("v1:i0386")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0386"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n16_x2_b8x16_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387"),
-            Some("v1:i0387")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n16_x2_b8x16_b6x16_p32"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0387"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n16_x4_b8x16_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"),
-            Some("v1:i0388")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n16_x4_b8x16_b4x16_p64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64"),
-            Some("v1:i0388")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0388"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n16_x4_b8x16_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389"),
-            Some("v1:i0389")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n16_x4_b8x16_b6x16_p32"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0389"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n8_x1_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"),
-            Some("v1:i0025")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n8_x1_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x1"),
-            Some("v1:i0025")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0025"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n8_x1_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"),
-            Some("v1:i0026")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n8_x1_trans_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x1_trans"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x1_trans"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x1_trans"),
-            Some("v1:i0026")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0026"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n8_x2_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"),
-            Some("v1:i0027")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n8_x2_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x2"),
-            Some("v1:i0027")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0027"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n8_x2_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"),
-            Some("v1:i0028")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n8_x2_trans_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x2_trans"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x2_trans"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x2_trans"),
-            Some("v1:i0028")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0028"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n8_x4_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"),
-            Some("v1:i0013")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n8_x4_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x4"),
-            Some("v1:i0013")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0013"
-        ));
-    }
-    #[test]
-    fn ldmatrix_m8n8_x4_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"),
-            Some("v1:i0029")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::ldmatrix_m8n8_x4_trans_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x4_trans"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::ldmatrix_x4_trans"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x4_trans"),
-            Some("v1:i0029")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0029"
-        ));
-    }
-    #[test]
-    fn lg2_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"),
-            Some("v1:i0786")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::lg2_approx_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::lg2_approx_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::lg2_approx_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::lg2_approx_f32"),
-            Some("v1:i0786")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0786"
-        ));
-    }
-    #[test]
-    fn lg2_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"),
-            Some("v1:i0787")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::lg2_approx_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::lg2_approx_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::lg2_approx_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::lg2_approx_ftz_f32"),
-            Some("v1:i0787")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0787"
-        ));
-    }
-    #[test]
-    fn map_shared_rank_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"),
-            Some("v1:i0320")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::cluster::map_shared_rank"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::map_shared_rank"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::map_shared_rank"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::map_shared_rank"),
-            Some("v1:i0320")
-        );
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::cluster::map_shared_rank_mut"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::cluster::map_shared_rank_mut"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::cluster::map_shared_rank_mut"),
-            Some("v1:i0320")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0320"
-        ));
-    }
-    #[test]
-    fn match_all_i64_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"),
-            Some("v1:i0048")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::match_all_i64_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::match_all_i64_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::match_all_i64_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::match_all_i64_sync"),
-            Some("v1:i0048")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0048"
-        ));
-    }
-    #[test]
-    fn match_all_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"),
-            Some("v1:i0047")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::match_all_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::match_all_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::match_all_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::match_all_sync"),
-            Some("v1:i0047")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0047"
-        ));
-    }
-    #[test]
-    fn match_any_i64_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"),
-            Some("v1:i0046")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::match_any_i64_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::match_any_i64_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::match_any_i64_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::match_any_i64_sync"),
-            Some("v1:i0046")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0046"
-        ));
-    }
-    #[test]
-    fn match_any_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"),
-            Some("v1:i0045")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::match_any_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::match_any_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::match_any_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::match_any_sync"),
-            Some("v1:i0045")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0045"
-        ));
-    }
-    #[test]
-    fn max_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850"),
-            Some("v1:i0850")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16::max_bf16"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::bf16::max_bf16"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16::max_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16::max_bf16"),
-            Some("v1:i0850")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0850"
-        ));
-    }
-    #[test]
-    fn max_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"),
-            Some("v1:i0068")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::max_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::max_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::max_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::max_bf16x2"),
-            Some("v1:i0068")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0068"
-        ));
-    }
-    #[test]
-    fn max_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842"),
-            Some("v1:i0842")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::max_f16"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16::max_f16"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::max_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::max_f16"),
-            Some("v1:i0842")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0842"
-        ));
-    }
-    #[test]
-    fn max_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"),
-            Some("v1:i0078")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::max_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16x2::max_f16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::max_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::max_f16x2"),
-            Some("v1:i0078")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0078"
-        ));
-    }
-    #[test]
-    fn max_ftz_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"),
-            Some("v1:i0843")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::max_ftz_f16"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16::max_ftz_f16"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::max_ftz_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::max_ftz_f16"),
-            Some("v1:i0843")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0843"
-        ));
-    }
-    #[test]
-    fn max_ftz_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"),
-            Some("v1:i0564")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::max_ftz_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::max_ftz_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::max_ftz_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::max_ftz_f16x2"),
-            Some("v1:i0564")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0564"
-        ));
-    }
-    #[test]
-    fn max_ftz_nan_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"),
-            Some("v1:i0845")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::max_ftz_nan_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16::max_ftz_nan_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::max_ftz_nan_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::max_ftz_nan_f16"),
-            Some("v1:i0845")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0845"
-        ));
-    }
-    #[test]
-    fn max_ftz_nan_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"),
-            Some("v1:i0565")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::max_ftz_nan_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::max_ftz_nan_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::max_ftz_nan_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::max_ftz_nan_f16x2"),
-            Some("v1:i0565")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0565"
-        ));
-    }
-    #[test]
-    fn max_ftz_nan_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"),
-            Some("v1:i0849")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::max_ftz_nan_xorsign_abs_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16::max_ftz_nan_xorsign_abs_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::max_ftz_nan_xorsign_abs_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::max_ftz_nan_xorsign_abs_f16"),
-            Some("v1:i0849")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0849"
-        ));
-    }
-    #[test]
-    fn max_ftz_nan_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"),
-            Some("v1:i0567")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::max_ftz_nan_xorsign_abs_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2"),
-            Some("v1:i0567")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0567"
-        ));
-    }
-    #[test]
-    fn max_ftz_nan_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"),
-            Some("v1:i0566")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::max_ftz_nan_xorsign_abs_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::max_ftz_nan_xorsign_abs_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::max_ftz_nan_xorsign_abs_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::max_ftz_nan_xorsign_abs_f32"),
-            Some("v1:i0566")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0566"
-        ));
-    }
-    #[test]
-    fn max_ftz_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"),
-            Some("v1:i0847")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::max_ftz_xorsign_abs_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16::max_ftz_xorsign_abs_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::max_ftz_xorsign_abs_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::max_ftz_xorsign_abs_f16"),
-            Some("v1:i0847")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0847"
-        ));
-    }
-    #[test]
-    fn max_ftz_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"),
-            Some("v1:i0569")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::max_ftz_xorsign_abs_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::max_ftz_xorsign_abs_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::max_ftz_xorsign_abs_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::max_ftz_xorsign_abs_f16x2"),
-            Some("v1:i0569")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0569"
-        ));
-    }
-    #[test]
-    fn max_ftz_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"),
-            Some("v1:i0568")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::max_ftz_xorsign_abs_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::max_ftz_xorsign_abs_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::max_ftz_xorsign_abs_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::max_ftz_xorsign_abs_f32"),
-            Some("v1:i0568")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0568"
-        ));
-    }
-    #[test]
-    fn max_nan_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"),
-            Some("v1:i0851")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16::max_nan_bf16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16::max_nan_bf16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16::max_nan_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16::max_nan_bf16"),
-            Some("v1:i0851")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0851"
-        ));
-    }
-    #[test]
-    fn max_nan_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"),
-            Some("v1:i0570")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::max_nan_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::max_nan_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::max_nan_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::max_nan_bf16x2"),
-            Some("v1:i0570")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0570"
-        ));
-    }
-    #[test]
-    fn max_nan_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"),
-            Some("v1:i0844")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::max_nan_f16"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16::max_nan_f16"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::max_nan_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::max_nan_f16"),
-            Some("v1:i0844")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0844"
-        ));
-    }
-    #[test]
-    fn max_nan_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"),
-            Some("v1:i0571")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::max_nan_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::max_nan_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::max_nan_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::max_nan_f16x2"),
-            Some("v1:i0571")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0571"
-        ));
-    }
-    #[test]
-    fn max_nan_xorsign_abs_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"),
-            Some("v1:i0853")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16::max_nan_xorsign_abs_bf16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16::max_nan_xorsign_abs_bf16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16::max_nan_xorsign_abs_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16::max_nan_xorsign_abs_bf16"),
-            Some("v1:i0853")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0853"
-        ));
-    }
-    #[test]
-    fn max_nan_xorsign_abs_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"),
-            Some("v1:i0572")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::max_nan_xorsign_abs_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2"),
-            Some("v1:i0572")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0572"
-        ));
-    }
-    #[test]
-    fn max_nan_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"),
-            Some("v1:i0848")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::max_nan_xorsign_abs_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16::max_nan_xorsign_abs_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::max_nan_xorsign_abs_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::max_nan_xorsign_abs_f16"),
-            Some("v1:i0848")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0848"
-        ));
-    }
-    #[test]
-    fn max_nan_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"),
-            Some("v1:i0574")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::max_nan_xorsign_abs_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::max_nan_xorsign_abs_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::max_nan_xorsign_abs_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::max_nan_xorsign_abs_f16x2"),
-            Some("v1:i0574")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0574"
-        ));
-    }
-    #[test]
-    fn max_nan_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"),
-            Some("v1:i0573")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::max_nan_xorsign_abs_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::max_nan_xorsign_abs_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::max_nan_xorsign_abs_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::max_nan_xorsign_abs_f32"),
-            Some("v1:i0573")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0573"
-        ));
-    }
-    #[test]
-    fn max_relu_s16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"),
-            Some("v1:i0994")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::i16x2::max_relu_s16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::i16x2::max_relu_s16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::i16x2::max_relu_s16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::i16x2::max_relu_s16x2"),
-            Some("v1:i0994")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0994"
-        ));
-    }
-    #[test]
-    fn max_relu_s32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"),
-            Some("v1:i0988")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::int::max_relu_s32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::int::max_relu_s32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::int::max_relu_s32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::int::max_relu_s32"),
-            Some("v1:i0988")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0988"
-        ));
-    }
-    #[test]
-    fn max_s16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"),
-            Some("v1:i0990")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::i16x2::max_s16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::i16x2::max_s16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::i16x2::max_s16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::i16x2::max_s16x2"),
-            Some("v1:i0990")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0990"
-        ));
-    }
-    #[test]
-    fn max_u16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"),
-            Some("v1:i0992")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::i16x2::max_u16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::i16x2::max_u16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::i16x2::max_u16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::i16x2::max_u16x2"),
-            Some("v1:i0992")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0992"
-        ));
-    }
-    #[test]
-    fn max_xorsign_abs_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"),
-            Some("v1:i0852")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16::max_xorsign_abs_bf16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16::max_xorsign_abs_bf16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16::max_xorsign_abs_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16::max_xorsign_abs_bf16"),
-            Some("v1:i0852")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0852"
-        ));
-    }
-    #[test]
-    fn max_xorsign_abs_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"),
-            Some("v1:i0575")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::max_xorsign_abs_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::max_xorsign_abs_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::max_xorsign_abs_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::max_xorsign_abs_bf16x2"),
-            Some("v1:i0575")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0575"
-        ));
-    }
-    #[test]
-    fn max_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"),
-            Some("v1:i0846")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::max_xorsign_abs_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16::max_xorsign_abs_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::max_xorsign_abs_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::max_xorsign_abs_f16"),
-            Some("v1:i0846")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0846"
-        ));
-    }
-    #[test]
-    fn max_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"),
-            Some("v1:i0577")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::max_xorsign_abs_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::max_xorsign_abs_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::max_xorsign_abs_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::max_xorsign_abs_f16x2"),
-            Some("v1:i0577")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0577"
-        ));
-    }
-    #[test]
-    fn max_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"),
-            Some("v1:i0576")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::max_xorsign_abs_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::max_xorsign_abs_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::max_xorsign_abs_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::max_xorsign_abs_f32"),
-            Some("v1:i0576")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0576"
-        ));
-    }
-    #[test]
-    fn mbarrier_arrive_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"),
-            Some("v1:i0098")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::mbarrier_arrive"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_arrive"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_arrive"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::mbarrier_arrive"),
-            Some("v1:i0098")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0098"
-        ));
-    }
-    #[test]
-    fn mbarrier_arrive_cluster_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"),
-            Some("v1:i0308")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::mbarrier_arrive_cluster"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_arrive_cluster"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_arrive_cluster"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::mbarrier_arrive_cluster"),
-            Some("v1:i0308")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0308"
-        ));
-    }
-    #[test]
-    fn mbarrier_arrive_expect_tx_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"),
-            Some("v1:i0306")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::mbarrier_arrive_expect_tx"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_arrive_expect_tx"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_arrive_expect_tx"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::mbarrier_arrive_expect_tx"),
-            Some("v1:i0306")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0306"
-        ));
-    }
-    #[test]
-    fn mbarrier_arrive_expect_tx_cluster_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"),
-            Some("v1:i0307")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::mbarrier_arrive_expect_tx_cluster"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_arrive_expect_tx_cluster"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_arrive_expect_tx_cluster"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::mbarrier_arrive_expect_tx_cluster"),
-            Some("v1:i0307")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0307"
-        ));
-    }
-    #[test]
-    fn mbarrier_init_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"),
-            Some("v1:i0097")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::mbarrier_init"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_init"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_init"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::mbarrier_init"),
-            Some("v1:i0097")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0097"
-        ));
-    }
-    #[test]
-    fn mbarrier_inval_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"),
-            Some("v1:i0100")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::mbarrier_inval"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_inval"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_inval"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::mbarrier_inval"),
-            Some("v1:i0100")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0100"
-        ));
-    }
-    #[test]
-    fn mbarrier_test_wait_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"),
-            Some("v1:i0099")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::mbarrier_test_wait"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_test_wait"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_test_wait"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::mbarrier_test_wait"),
-            Some("v1:i0099")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0099"
-        ));
-    }
-    #[test]
-    fn mbarrier_try_wait_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"),
-            Some("v1:i0309")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::mbarrier_try_wait"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_try_wait"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_try_wait"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::mbarrier_try_wait"),
-            Some("v1:i0309")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0309"
-        ));
-    }
-    #[test]
-    fn mbarrier_try_wait_parity_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"),
-            Some("v1:i0310")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::mbarrier_try_wait_parity"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_try_wait_parity"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_try_wait_parity"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::mbarrier_try_wait_parity"),
-            Some("v1:i0310")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0310"
-        ));
-    }
-    #[test]
-    fn mbarrier_try_wait_parity_cluster_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"),
-            Some("v1:i0311")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::mbarrier_try_wait_parity_cluster"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_try_wait_parity_cluster"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::mbarrier_try_wait_parity_cluster"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::mbarrier_try_wait_parity_cluster"),
-            Some("v1:i0311")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0311"
-        ));
-    }
-    #[test]
-    fn min_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838"),
-            Some("v1:i0838")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16::min_bf16"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::bf16::min_bf16"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16::min_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16::min_bf16"),
-            Some("v1:i0838")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0838"
-        ));
-    }
-    #[test]
-    fn min_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"),
-            Some("v1:i0067")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::min_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::min_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::min_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::min_bf16x2"),
-            Some("v1:i0067")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0067"
-        ));
-    }
-    #[test]
-    fn min_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830"),
-            Some("v1:i0830")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::min_f16"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16::min_f16"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::min_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::min_f16"),
-            Some("v1:i0830")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0830"
-        ));
-    }
-    #[test]
-    fn min_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"),
-            Some("v1:i0077")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::min_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16x2::min_f16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::min_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::min_f16x2"),
-            Some("v1:i0077")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0077"
-        ));
-    }
-    #[test]
-    fn min_ftz_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"),
-            Some("v1:i0831")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::min_ftz_f16"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16::min_ftz_f16"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::min_ftz_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::min_ftz_f16"),
-            Some("v1:i0831")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0831"
-        ));
-    }
-    #[test]
-    fn min_ftz_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"),
-            Some("v1:i0550")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::min_ftz_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::min_ftz_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::min_ftz_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::min_ftz_f16x2"),
-            Some("v1:i0550")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0550"
-        ));
-    }
-    #[test]
-    fn min_ftz_nan_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"),
-            Some("v1:i0833")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::min_ftz_nan_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16::min_ftz_nan_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::min_ftz_nan_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::min_ftz_nan_f16"),
-            Some("v1:i0833")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0833"
-        ));
-    }
-    #[test]
-    fn min_ftz_nan_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"),
-            Some("v1:i0551")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::min_ftz_nan_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::min_ftz_nan_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::min_ftz_nan_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::min_ftz_nan_f16x2"),
-            Some("v1:i0551")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0551"
-        ));
-    }
-    #[test]
-    fn min_ftz_nan_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"),
-            Some("v1:i0837")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::min_ftz_nan_xorsign_abs_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16::min_ftz_nan_xorsign_abs_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::min_ftz_nan_xorsign_abs_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::min_ftz_nan_xorsign_abs_f16"),
-            Some("v1:i0837")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0837"
-        ));
-    }
-    #[test]
-    fn min_ftz_nan_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"),
-            Some("v1:i0553")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::min_ftz_nan_xorsign_abs_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2"),
-            Some("v1:i0553")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0553"
-        ));
-    }
-    #[test]
-    fn min_ftz_nan_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"),
-            Some("v1:i0552")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::min_ftz_nan_xorsign_abs_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::min_ftz_nan_xorsign_abs_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::min_ftz_nan_xorsign_abs_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::min_ftz_nan_xorsign_abs_f32"),
-            Some("v1:i0552")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0552"
-        ));
-    }
-    #[test]
-    fn min_ftz_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"),
-            Some("v1:i0835")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::min_ftz_xorsign_abs_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16::min_ftz_xorsign_abs_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::min_ftz_xorsign_abs_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::min_ftz_xorsign_abs_f16"),
-            Some("v1:i0835")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0835"
-        ));
-    }
-    #[test]
-    fn min_ftz_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"),
-            Some("v1:i0555")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::min_ftz_xorsign_abs_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::min_ftz_xorsign_abs_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::min_ftz_xorsign_abs_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::min_ftz_xorsign_abs_f16x2"),
-            Some("v1:i0555")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0555"
-        ));
-    }
-    #[test]
-    fn min_ftz_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"),
-            Some("v1:i0554")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::min_ftz_xorsign_abs_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::min_ftz_xorsign_abs_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::min_ftz_xorsign_abs_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::min_ftz_xorsign_abs_f32"),
-            Some("v1:i0554")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0554"
-        ));
-    }
-    #[test]
-    fn min_nan_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"),
-            Some("v1:i0839")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16::min_nan_bf16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16::min_nan_bf16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16::min_nan_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16::min_nan_bf16"),
-            Some("v1:i0839")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0839"
-        ));
-    }
-    #[test]
-    fn min_nan_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"),
-            Some("v1:i0556")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::min_nan_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::min_nan_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::min_nan_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::min_nan_bf16x2"),
-            Some("v1:i0556")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0556"
-        ));
-    }
-    #[test]
-    fn min_nan_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"),
-            Some("v1:i0832")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::min_nan_f16"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16::min_nan_f16"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::min_nan_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::min_nan_f16"),
-            Some("v1:i0832")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0832"
-        ));
-    }
-    #[test]
-    fn min_nan_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"),
-            Some("v1:i0557")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::min_nan_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::min_nan_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::min_nan_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::min_nan_f16x2"),
-            Some("v1:i0557")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0557"
-        ));
-    }
-    #[test]
-    fn min_nan_xorsign_abs_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"),
-            Some("v1:i0841")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16::min_nan_xorsign_abs_bf16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16::min_nan_xorsign_abs_bf16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16::min_nan_xorsign_abs_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16::min_nan_xorsign_abs_bf16"),
-            Some("v1:i0841")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0841"
-        ));
-    }
-    #[test]
-    fn min_nan_xorsign_abs_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"),
-            Some("v1:i0558")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::min_nan_xorsign_abs_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2"),
-            Some("v1:i0558")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0558"
-        ));
-    }
-    #[test]
-    fn min_nan_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"),
-            Some("v1:i0836")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::min_nan_xorsign_abs_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16::min_nan_xorsign_abs_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::min_nan_xorsign_abs_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::min_nan_xorsign_abs_f16"),
-            Some("v1:i0836")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0836"
-        ));
-    }
-    #[test]
-    fn min_nan_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"),
-            Some("v1:i0560")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::min_nan_xorsign_abs_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::min_nan_xorsign_abs_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::min_nan_xorsign_abs_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::min_nan_xorsign_abs_f16x2"),
-            Some("v1:i0560")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0560"
-        ));
-    }
-    #[test]
-    fn min_nan_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"),
-            Some("v1:i0559")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::min_nan_xorsign_abs_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::min_nan_xorsign_abs_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::min_nan_xorsign_abs_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::min_nan_xorsign_abs_f32"),
-            Some("v1:i0559")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0559"
-        ));
-    }
-    #[test]
-    fn min_relu_s16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"),
-            Some("v1:i0993")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::i16x2::min_relu_s16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::i16x2::min_relu_s16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::i16x2::min_relu_s16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::i16x2::min_relu_s16x2"),
-            Some("v1:i0993")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0993"
-        ));
-    }
-    #[test]
-    fn min_relu_s32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"),
-            Some("v1:i0987")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::int::min_relu_s32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::int::min_relu_s32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::int::min_relu_s32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::int::min_relu_s32"),
-            Some("v1:i0987")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0987"
-        ));
-    }
-    #[test]
-    fn min_s16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"),
-            Some("v1:i0989")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::i16x2::min_s16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::i16x2::min_s16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::i16x2::min_s16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::i16x2::min_s16x2"),
-            Some("v1:i0989")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0989"
-        ));
-    }
-    #[test]
-    fn min_u16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"),
-            Some("v1:i0991")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::i16x2::min_u16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::i16x2::min_u16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::i16x2::min_u16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::i16x2::min_u16x2"),
-            Some("v1:i0991")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0991"
-        ));
-    }
-    #[test]
-    fn min_xorsign_abs_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"),
-            Some("v1:i0840")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16::min_xorsign_abs_bf16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16::min_xorsign_abs_bf16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16::min_xorsign_abs_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16::min_xorsign_abs_bf16"),
-            Some("v1:i0840")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0840"
-        ));
-    }
-    #[test]
-    fn min_xorsign_abs_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"),
-            Some("v1:i0561")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::min_xorsign_abs_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::min_xorsign_abs_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::min_xorsign_abs_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::min_xorsign_abs_bf16x2"),
-            Some("v1:i0561")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0561"
-        ));
-    }
-    #[test]
-    fn min_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"),
-            Some("v1:i0834")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16::min_xorsign_abs_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16::min_xorsign_abs_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16::min_xorsign_abs_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16::min_xorsign_abs_f16"),
-            Some("v1:i0834")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0834"
-        ));
-    }
-    #[test]
-    fn min_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"),
-            Some("v1:i0563")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::min_xorsign_abs_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f16x2::min_xorsign_abs_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::min_xorsign_abs_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::min_xorsign_abs_f16x2"),
-            Some("v1:i0563")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0563"
-        ));
-    }
-    #[test]
-    fn min_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"),
-            Some("v1:i0562")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::min_xorsign_abs_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::min_xorsign_abs_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::min_xorsign_abs_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::min_xorsign_abs_f32"),
-            Some("v1:i0562")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0562"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k128_s32_b1_and_popc_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"),
-            Some("v1:i0161")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k128_s32_b1_and_popc"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc"),
-            Some("v1:i0161")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0161"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k128_s32_b1_xor_popc_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"),
-            Some("v1:i0158")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k128_s32_b1_xor_popc"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc"),
-            Some("v1:i0158")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0158"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_f16_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"),
-            Some("v1:i0524")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_f16_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_f16_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_f16_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_f16_f16"),
-            Some("v1:i0524")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0524"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_f32_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"),
-            Some("v1:i0105")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_f32_bf16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_f32_bf16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_f32_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_f32_bf16"),
-            Some("v1:i0105")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0105"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_f32_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"),
-            Some("v1:i0106")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_f32_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_f32_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_f32_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_f32_f16"),
-            Some("v1:i0106")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0106"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_fp8_f16_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"),
-            Some("v1:i0504")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f16_e4m3_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3"),
-            Some("v1:i0504")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0504"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_fp8_f16_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"),
-            Some("v1:i0505")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f16_e4m3_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2"),
-            Some("v1:i0505")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0505"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_fp8_f16_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"),
-            Some("v1:i0506")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f16_e5m2_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3"),
-            Some("v1:i0506")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0506"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_fp8_f16_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"),
-            Some("v1:i0507")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f16_e5m2_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2"),
-            Some("v1:i0507")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0507"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_fp8_f32_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"),
-            Some("v1:i0508")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f32_e4m3_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3"),
-            Some("v1:i0508")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0508"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_fp8_f32_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"),
-            Some("v1:i0509")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f32_e4m3_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2"),
-            Some("v1:i0509")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0509"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_fp8_f32_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"),
-            Some("v1:i0510")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f32_e5m2_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3"),
-            Some("v1:i0510")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0510"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_fp8_f32_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"),
-            Some("v1:i0511")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f32_e5m2_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2"),
-            Some("v1:i0511")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0511"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"),
-            Some("v1:i0110")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_s32_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_s8"),
-            Some("v1:i0110")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0110"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"),
-            Some("v1:i0117")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_s32_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite"),
-            Some("v1:i0117")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0117"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"),
-            Some("v1:i0111")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_s32_s8_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_s8_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_s8_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_s8_u8"),
-            Some("v1:i0111")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0111"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"),
-            Some("v1:i0118")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_s32_s8_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite"),
-            Some("v1:i0118")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0118"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"),
-            Some("v1:i0112")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_s32_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_u8"),
-            Some("v1:i0112")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0112"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"),
-            Some("v1:i0113")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_s32_u8_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_u8_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_u8_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_u8_s8"),
-            Some("v1:i0113")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0113"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"),
-            Some("v1:i0120")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_s32_u8_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite"),
-            Some("v1:i0120")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0120"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k16_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"),
-            Some("v1:i0119")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k16_s32_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite"),
-            Some("v1:i0119")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0119"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k256_s32_b1_and_popc_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"),
-            Some("v1:i0162")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k256_s32_b1_and_popc"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc"),
-            Some("v1:i0162")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0162"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k256_s32_b1_xor_popc_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"),
-            Some("v1:i0159")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k256_s32_b1_xor_popc"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc"),
-            Some("v1:i0159")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0159"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e2m1_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"),
-            Some("v1:i0479")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m1_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1"),
-            Some("v1:i0479")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0479"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e2m1_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"),
-            Some("v1:i0480")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m1_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3"),
-            Some("v1:i0480")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0480"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e2m1_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"),
-            Some("v1:i0481")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m1_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2"),
-            Some("v1:i0481")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0481"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e2m1_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"),
-            Some("v1:i0482")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m1_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3"),
-            Some("v1:i0482")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0482"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e2m1_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"),
-            Some("v1:i0483")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m1_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2"),
-            Some("v1:i0483")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0483"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e2m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"),
-            Some("v1:i0484")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m3_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1"),
-            Some("v1:i0484")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0484"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e2m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"),
-            Some("v1:i0485")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m3_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3"),
-            Some("v1:i0485")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0485"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e2m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"),
-            Some("v1:i0486")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m3_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2"),
-            Some("v1:i0486")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0486"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e2m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"),
-            Some("v1:i0487")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m3_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3"),
-            Some("v1:i0487")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0487"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e2m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"),
-            Some("v1:i0488")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m3_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2"),
-            Some("v1:i0488")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0488"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e3m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"),
-            Some("v1:i0489")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e3m2_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1"),
-            Some("v1:i0489")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0489"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e3m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"),
-            Some("v1:i0490")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e3m2_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3"),
-            Some("v1:i0490")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0490"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e3m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"),
-            Some("v1:i0491")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e3m2_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2"),
-            Some("v1:i0491")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0491"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e3m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"),
-            Some("v1:i0492")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e3m2_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3"),
-            Some("v1:i0492")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0492"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e3m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"),
-            Some("v1:i0493")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e3m2_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2"),
-            Some("v1:i0493")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0493"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e4m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"),
-            Some("v1:i0494")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e4m3_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1"),
-            Some("v1:i0494")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0494"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e4m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"),
-            Some("v1:i0495")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e4m3_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3"),
-            Some("v1:i0495")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0495"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e4m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"),
-            Some("v1:i0496")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e4m3_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2"),
-            Some("v1:i0496")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0496"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"),
-            Some("v1:i0497")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e4m3_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3"),
-            Some("v1:i0497")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0497"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"),
-            Some("v1:i0498")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e4m3_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2"),
-            Some("v1:i0498")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0498"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e5m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"),
-            Some("v1:i0499")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e5m2_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1"),
-            Some("v1:i0499")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0499"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e5m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"),
-            Some("v1:i0500")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e5m2_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3"),
-            Some("v1:i0500")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0500"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e5m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"),
-            Some("v1:i0501")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e5m2_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2"),
-            Some("v1:i0501")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0501"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"),
-            Some("v1:i0502")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e5m2_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3"),
-            Some("v1:i0502")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0502"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f16_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"),
-            Some("v1:i0503")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f16_e5m2_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2"),
-            Some("v1:i0503")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0503"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e2m1_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"),
-            Some("v1:i0454")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m1_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1"),
-            Some("v1:i0454")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0454"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e2m1_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"),
-            Some("v1:i0455")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m1_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3"),
-            Some("v1:i0455")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0455"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e2m1_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"),
-            Some("v1:i0456")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m1_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2"),
-            Some("v1:i0456")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0456"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e2m1_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"),
-            Some("v1:i0457")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m1_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3"),
-            Some("v1:i0457")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0457"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e2m1_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"),
-            Some("v1:i0458")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m1_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2"),
-            Some("v1:i0458")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0458"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e2m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"),
-            Some("v1:i0459")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m3_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1"),
-            Some("v1:i0459")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0459"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e2m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"),
-            Some("v1:i0460")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m3_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3"),
-            Some("v1:i0460")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0460"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e2m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"),
-            Some("v1:i0461")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m3_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2"),
-            Some("v1:i0461")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0461"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e2m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"),
-            Some("v1:i0462")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m3_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3"),
-            Some("v1:i0462")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0462"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e2m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"),
-            Some("v1:i0463")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m3_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2"),
-            Some("v1:i0463")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0463"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e3m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"),
-            Some("v1:i0464")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e3m2_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1"),
-            Some("v1:i0464")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0464"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e3m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"),
-            Some("v1:i0465")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e3m2_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3"),
-            Some("v1:i0465")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0465"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e3m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"),
-            Some("v1:i0466")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e3m2_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2"),
-            Some("v1:i0466")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0466"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e3m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"),
-            Some("v1:i0467")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e3m2_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3"),
-            Some("v1:i0467")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0467"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e3m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"),
-            Some("v1:i0468")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e3m2_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2"),
-            Some("v1:i0468")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0468"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e4m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"),
-            Some("v1:i0469")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e4m3_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1"),
-            Some("v1:i0469")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0469"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e4m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"),
-            Some("v1:i0470")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e4m3_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3"),
-            Some("v1:i0470")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0470"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e4m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"),
-            Some("v1:i0471")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e4m3_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2"),
-            Some("v1:i0471")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0471"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"),
-            Some("v1:i0472")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e4m3_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3"),
-            Some("v1:i0472")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0472"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"),
-            Some("v1:i0473")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e4m3_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2"),
-            Some("v1:i0473")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0473"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e5m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"),
-            Some("v1:i0474")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e5m2_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1"),
-            Some("v1:i0474")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0474"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e5m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"),
-            Some("v1:i0475")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e5m2_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3"),
-            Some("v1:i0475")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0475"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e5m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"),
-            Some("v1:i0476")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e5m2_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2"),
-            Some("v1:i0476")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0476"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"),
-            Some("v1:i0477")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e5m2_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3"),
-            Some("v1:i0477")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0477"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_f32_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"),
-            Some("v1:i0478")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_f32_e5m2_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2"),
-            Some("v1:i0478")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0478"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_fp8_f16_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"),
-            Some("v1:i0512")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f16_e4m3_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3"),
-            Some("v1:i0512")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0512"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_fp8_f16_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"),
-            Some("v1:i0513")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f16_e4m3_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2"),
-            Some("v1:i0513")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0513"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_fp8_f16_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"),
-            Some("v1:i0514")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f16_e5m2_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3"),
-            Some("v1:i0514")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0514"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_fp8_f16_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"),
-            Some("v1:i0515")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f16_e5m2_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2"),
-            Some("v1:i0515")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0515"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_fp8_f32_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"),
-            Some("v1:i0516")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f32_e4m3_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3"),
-            Some("v1:i0516")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0516"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_fp8_f32_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"),
-            Some("v1:i0517")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f32_e4m3_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2"),
-            Some("v1:i0517")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0517"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_fp8_f32_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"),
-            Some("v1:i0518")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f32_e5m2_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3"),
-            Some("v1:i0518")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0518"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_fp8_f32_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"),
-            Some("v1:i0519")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f32_e5m2_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2"),
-            Some("v1:i0519")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0519"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"),
-            Some("v1:i0858")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1"),
-            Some("v1:i0858")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0858"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"),
-            Some("v1:i0859")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3"),
-            Some("v1:i0859")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0859"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"),
-            Some("v1:i0860")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2"),
-            Some("v1:i0860")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0860"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"),
-            Some("v1:i0861")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3"),
-            Some("v1:i0861")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0861"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"),
-            Some("v1:i0862")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2"),
-            Some("v1:i0862")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0862"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"),
-            Some("v1:i0863")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1"),
-            Some("v1:i0863")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0863"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"),
-            Some("v1:i0864")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3"),
-            Some("v1:i0864")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0864"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"),
-            Some("v1:i0865")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2"),
-            Some("v1:i0865")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0865"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"),
-            Some("v1:i0866")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3"),
-            Some("v1:i0866")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0866"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"),
-            Some("v1:i0867")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2"),
-            Some("v1:i0867")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0867"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"),
-            Some("v1:i0868")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1"),
-            Some("v1:i0868")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0868"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"),
-            Some("v1:i0869")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3"),
-            Some("v1:i0869")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0869"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"),
-            Some("v1:i0870")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2"),
-            Some("v1:i0870")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0870"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"),
-            Some("v1:i0871")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3"),
-            Some("v1:i0871")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0871"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"),
-            Some("v1:i0872")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2"),
-            Some("v1:i0872")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0872"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"),
-            Some("v1:i0873")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1"),
-            Some("v1:i0873")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0873"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"),
-            Some("v1:i0874")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3"),
-            Some("v1:i0874")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0874"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"),
-            Some("v1:i0875")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2"),
-            Some("v1:i0875")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0875"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"),
-            Some("v1:i0876")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3"),
-            Some("v1:i0876")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0876"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"),
-            Some("v1:i0877")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2"),
-            Some("v1:i0877")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0877"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"),
-            Some("v1:i0878")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1"),
-            Some("v1:i0878")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0878"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"),
-            Some("v1:i0879")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3"),
-            Some("v1:i0879")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0879"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"),
-            Some("v1:i0880")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2"),
-            Some("v1:i0880")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0880"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"),
-            Some("v1:i0881")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3"),
-            Some("v1:i0881")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0881"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"),
-            Some("v1:i0882")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2"),
-            Some("v1:i0882")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0882"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"),
-            Some("v1:i0141")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s4"),
-            Some("v1:i0141")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0141"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"),
-            Some("v1:i0149")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite"),
-            Some("v1:i0149")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0149"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"),
-            Some("v1:i0142")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_s4_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s4_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s4_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s4_u4"),
-            Some("v1:i0142")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0142"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"),
-            Some("v1:i0150")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_s4_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite"),
-            Some("v1:i0150")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0150"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"),
-            Some("v1:i0108")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s8"),
-            Some("v1:i0108")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0108"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"),
-            Some("v1:i0121")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite"),
-            Some("v1:i0121")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0121"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"),
-            Some("v1:i0114")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_s8_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s8_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s8_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s8_u8"),
-            Some("v1:i0114")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0114"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"),
-            Some("v1:i0122")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_s8_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite"),
-            Some("v1:i0122")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0122"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"),
-            Some("v1:i0143")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u4"),
-            Some("v1:i0143")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0143"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"),
-            Some("v1:i0144")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_u4_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u4_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u4_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u4_s4"),
-            Some("v1:i0144")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0144"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"),
-            Some("v1:i0152")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_u4_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite"),
-            Some("v1:i0152")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0152"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"),
-            Some("v1:i0151")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite"),
-            Some("v1:i0151")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0151"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"),
-            Some("v1:i0115")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u8"),
-            Some("v1:i0115")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0115"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"),
-            Some("v1:i0116")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_u8_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u8_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u8_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u8_s8"),
-            Some("v1:i0116")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0116"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"),
-            Some("v1:i0124")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_u8_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite"),
-            Some("v1:i0124")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0124"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k32_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"),
-            Some("v1:i0123")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k32_s32_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite"),
-            Some("v1:i0123")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0123"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k4_f32_tf32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"),
-            Some("v1:i0520")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k4_f32_tf32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k4_f32_tf32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k4_f32_tf32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k4_f32_tf32"),
-            Some("v1:i0520")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0520"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k64_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"),
-            Some("v1:i0145")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k64_s32_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_s4"),
-            Some("v1:i0145")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0145"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k64_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"),
-            Some("v1:i0153")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k64_s32_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite"),
-            Some("v1:i0153")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0153"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k64_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"),
-            Some("v1:i0146")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k64_s32_s4_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_s4_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_s4_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_s4_u4"),
-            Some("v1:i0146")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0146"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k64_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"),
-            Some("v1:i0154")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k64_s32_s4_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite"),
-            Some("v1:i0154")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0154"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k64_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"),
-            Some("v1:i0147")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k64_s32_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_u4"),
-            Some("v1:i0147")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0147"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k64_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"),
-            Some("v1:i0148")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k64_s32_u4_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_u4_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_u4_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_u4_s4"),
-            Some("v1:i0148")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0148"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k64_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"),
-            Some("v1:i0156")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k64_s32_u4_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite"),
-            Some("v1:i0156")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0156"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k64_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"),
-            Some("v1:i0155")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k64_s32_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite"),
-            Some("v1:i0155")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0155"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k8_f16_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"),
-            Some("v1:i0521")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k8_f16_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k8_f16_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k8_f16_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k8_f16_f16"),
-            Some("v1:i0521")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0521"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k8_f32_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"),
-            Some("v1:i0522")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k8_f32_bf16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k8_f32_bf16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k8_f32_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k8_f32_bf16"),
-            Some("v1:i0522")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0522"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k8_f32_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"),
-            Some("v1:i0523")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k8_f32_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k8_f32_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k8_f32_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k8_f32_f16"),
-            Some("v1:i0523")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0523"
-        ));
-    }
-    #[test]
-    fn mma_m16n8k8_f32_tf32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"),
-            Some("v1:i0107")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m16n8k8_f32_tf32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k8_f32_tf32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m16n8k8_f32_tf32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k8_f32_tf32"),
-            Some("v1:i0107")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0107"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k128_s32_b1_and_popc_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"),
-            Some("v1:i0160")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k128_s32_b1_and_popc"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc"),
-            Some("v1:i0160")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0160"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k128_s32_b1_xor_popc_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"),
-            Some("v1:i0157")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k128_s32_b1_xor_popc"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc"),
-            Some("v1:i0157")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0157"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k16_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"),
-            Some("v1:i0125")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k16_s32_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_s8"),
-            Some("v1:i0125")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0125"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k16_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"),
-            Some("v1:i0129")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k16_s32_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite"),
-            Some("v1:i0129")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0129"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k16_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"),
-            Some("v1:i0126")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k16_s32_s8_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_s8_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_s8_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_s8_u8"),
-            Some("v1:i0126")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0126"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k16_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"),
-            Some("v1:i0130")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k16_s32_s8_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite"),
-            Some("v1:i0130")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0130"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k16_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"),
-            Some("v1:i0127")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k16_s32_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_u8"),
-            Some("v1:i0127")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0127"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k16_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"),
-            Some("v1:i0128")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k16_s32_u8_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_u8_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_u8_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_u8_s8"),
-            Some("v1:i0128")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0128"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k16_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"),
-            Some("v1:i0132")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k16_s32_u8_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite"),
-            Some("v1:i0132")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0132"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k16_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"),
-            Some("v1:i0131")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k16_s32_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite"),
-            Some("v1:i0131")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0131"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k32_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"),
-            Some("v1:i0133")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k32_s32_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_s4"),
-            Some("v1:i0133")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0133"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k32_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"),
-            Some("v1:i0137")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k32_s32_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite"),
-            Some("v1:i0137")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0137"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k32_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"),
-            Some("v1:i0134")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k32_s32_s4_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_s4_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_s4_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_s4_u4"),
-            Some("v1:i0134")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0134"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k32_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"),
-            Some("v1:i0138")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k32_s32_s4_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite"),
-            Some("v1:i0138")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0138"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k32_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"),
-            Some("v1:i0135")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k32_s32_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_u4"),
-            Some("v1:i0135")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0135"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k32_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"),
-            Some("v1:i0136")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k32_s32_u4_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_u4_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_u4_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_u4_s4"),
-            Some("v1:i0136")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0136"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k32_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"),
-            Some("v1:i0140")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k32_s32_u4_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite"),
-            Some("v1:i0140")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0140"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k32_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"),
-            Some("v1:i0139")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k32_s32_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite"),
-            Some("v1:i0139")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0139"
-        ));
-    }
-    #[test]
-    fn mma_m8n8k4_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"),
-            Some("v1:i0109")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_m8n8k4_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k4_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_m8n8k4_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k4_f64"),
-            Some("v1:i0109")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0109"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k128_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"),
-            Some("v1:i0219")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_s4"),
-            Some("v1:i0219")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0219"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k128_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"),
-            Some("v1:i0223")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite"),
-            Some("v1:i0223")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0223"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k128_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"),
-            Some("v1:i0220")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_s4_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4"),
-            Some("v1:i0220")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0220"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k128_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"),
-            Some("v1:i0224")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_s4_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite"),
-            Some("v1:i0224")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0224"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k128_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"),
-            Some("v1:i0221")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_u4"),
-            Some("v1:i0221")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0221"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k128_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"),
-            Some("v1:i0222")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_u4_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4"),
-            Some("v1:i0222")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0222"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k128_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"),
-            Some("v1:i0226")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_u4_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite"),
-            Some("v1:i0226")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0226"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k128_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"),
-            Some("v1:i0225")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite"),
-            Some("v1:i0225")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0225"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k32_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"),
-            Some("v1:i0163")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_s8"),
-            Some("v1:i0163")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0163"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k32_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"),
-            Some("v1:i0167")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite"),
-            Some("v1:i0167")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0167"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k32_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"),
-            Some("v1:i0164")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_s8_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8"),
-            Some("v1:i0164")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0164"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k32_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"),
-            Some("v1:i0168")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_s8_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite"),
-            Some("v1:i0168")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0168"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k32_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"),
-            Some("v1:i0165")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_u8"),
-            Some("v1:i0165")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0165"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k32_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"),
-            Some("v1:i0166")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_u8_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8"),
-            Some("v1:i0166")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0166"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k32_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"),
-            Some("v1:i0170")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_u8_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite"),
-            Some("v1:i0170")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0170"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k32_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"),
-            Some("v1:i0169")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite"),
-            Some("v1:i0169")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0169"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"),
-            Some("v1:i0211")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s4"),
-            Some("v1:i0211")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0211"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"),
-            Some("v1:i0215")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite"),
-            Some("v1:i0215")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0215"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"),
-            Some("v1:i0212")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s4_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4"),
-            Some("v1:i0212")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0212"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"),
-            Some("v1:i0216")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s4_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite"),
-            Some("v1:i0216")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0216"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"),
-            Some("v1:i0187")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s8"),
-            Some("v1:i0187")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0187"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"),
-            Some("v1:i0191")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite"),
-            Some("v1:i0191")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0191"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"),
-            Some("v1:i0188")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s8_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8"),
-            Some("v1:i0188")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0188"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"),
-            Some("v1:i0192")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s8_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite"),
-            Some("v1:i0192")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0192"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"),
-            Some("v1:i0213")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u4"),
-            Some("v1:i0213")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0213"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"),
-            Some("v1:i0214")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u4_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4"),
-            Some("v1:i0214")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0214"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"),
-            Some("v1:i0218")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u4_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite"),
-            Some("v1:i0218")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0218"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"),
-            Some("v1:i0217")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite"),
-            Some("v1:i0217")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0217"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"),
-            Some("v1:i0189")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u8"),
-            Some("v1:i0189")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0189"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"),
-            Some("v1:i0190")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u8_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8"),
-            Some("v1:i0190")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0190"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"),
-            Some("v1:i0194")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u8_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite"),
-            Some("v1:i0194")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0194"
-        ));
-    }
-    #[test]
-    fn mma_sp_m16n8k64_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"),
-            Some("v1:i0193")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite"),
-            Some("v1:i0193")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0193"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k128_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"),
-            Some("v1:i0203")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4"
-            ),
-            Some("v1:i0203")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0203"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"),
-            Some("v1:i0207")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
-            ),
-            Some("v1:i0207")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0207"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"),
-            Some("v1:i0204")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4"
-            ),
-            Some("v1:i0204")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0204"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"),
-            Some("v1:i0208")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
-            ),
-            Some("v1:i0208")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0208"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k128_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"),
-            Some("v1:i0205")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4"
-            ),
-            Some("v1:i0205")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0205"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"),
-            Some("v1:i0206")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4"
-            ),
-            Some("v1:i0206")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0206"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"),
-            Some("v1:i0210")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
-            ),
-            Some("v1:i0210")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0210"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"),
-            Some("v1:i0209")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
-            ),
-            Some("v1:i0209")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0209"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k32_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"),
-            Some("v1:i0171")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8"
-            ),
-            Some("v1:i0171")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0171"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"),
-            Some("v1:i0175")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
-            ),
-            Some("v1:i0175")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0175"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"),
-            Some("v1:i0172")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8"
-            ),
-            Some("v1:i0172")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0172"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"),
-            Some("v1:i0176")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
-            ),
-            Some("v1:i0176")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0176"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k32_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"),
-            Some("v1:i0173")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8"
-            ),
-            Some("v1:i0173")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0173"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"),
-            Some("v1:i0174")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8"
-            ),
-            Some("v1:i0174")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0174"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"),
-            Some("v1:i0178")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
-            ),
-            Some("v1:i0178")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0178"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"),
-            Some("v1:i0177")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
-            ),
-            Some("v1:i0177")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0177"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"),
-            Some("v1:i0525")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
-            ),
-            Some("v1:i0525")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0525"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"),
-            Some("v1:i0526")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
-            ),
-            Some("v1:i0526")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0526"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"),
-            Some("v1:i0527")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
-            ),
-            Some("v1:i0527")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0527"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"),
-            Some("v1:i0528")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
-            ),
-            Some("v1:i0528")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0528"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"),
-            Some("v1:i0529")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
-            ),
-            Some("v1:i0529")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0529"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"),
-            Some("v1:i0530")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
-            ),
-            Some("v1:i0530")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0530"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"),
-            Some("v1:i0531")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
-            ),
-            Some("v1:i0531")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0531"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"),
-            Some("v1:i0532")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
-            ),
-            Some("v1:i0532")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0532"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"),
-            Some("v1:i0533")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
-            ),
-            Some("v1:i0533")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0533"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"),
-            Some("v1:i0534")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
-            ),
-            Some("v1:i0534")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0534"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"),
-            Some("v1:i0535")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
-            ),
-            Some("v1:i0535")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0535"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"),
-            Some("v1:i0536")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
-            ),
-            Some("v1:i0536")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0536"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"),
-            Some("v1:i0537")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
-            ),
-            Some("v1:i0537")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0537"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"),
-            Some("v1:i0538")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
-            ),
-            Some("v1:i0538")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0538"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"),
-            Some("v1:i0539")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
-            ),
-            Some("v1:i0539")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0539"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"),
-            Some("v1:i0540")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
-            ),
-            Some("v1:i0540")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0540"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"),
-            Some("v1:i0541")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
-            ),
-            Some("v1:i0541")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0541"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"),
-            Some("v1:i0542")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
-            ),
-            Some("v1:i0542")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0542"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"),
-            Some("v1:i0543")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
-            ),
-            Some("v1:i0543")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0543"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"),
-            Some("v1:i0544")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
-            ),
-            Some("v1:i0544")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0544"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"),
-            Some("v1:i0545")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
-            ),
-            Some("v1:i0545")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0545"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"),
-            Some("v1:i0546")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
-            ),
-            Some("v1:i0546")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0546"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"),
-            Some("v1:i0547")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
-            ),
-            Some("v1:i0547")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0547"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"),
-            Some("v1:i0548")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
-            ),
-            Some("v1:i0548")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0548"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"),
-            Some("v1:i0549")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
-            ),
-            Some("v1:i0549")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0549"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"),
-            Some("v1:i0227")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
-            ),
-            Some("v1:i0227")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0227"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"),
-            Some("v1:i0228")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
-            ),
-            Some("v1:i0228")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0228"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"),
-            Some("v1:i0229")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
-            ),
-            Some("v1:i0229")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0229"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"),
-            Some("v1:i0230")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
-            ),
-            Some("v1:i0230")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0230"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"),
-            Some("v1:i0231")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
-            ),
-            Some("v1:i0231")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0231"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"),
-            Some("v1:i0232")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
-            ),
-            Some("v1:i0232")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0232"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"),
-            Some("v1:i0233")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
-            ),
-            Some("v1:i0233")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0233"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"),
-            Some("v1:i0234")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
-            ),
-            Some("v1:i0234")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0234"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"),
-            Some("v1:i0235")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
-            ),
-            Some("v1:i0235")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0235"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"),
-            Some("v1:i0236")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
-            ),
-            Some("v1:i0236")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0236"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"),
-            Some("v1:i0237")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
-            ),
-            Some("v1:i0237")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0237"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"),
-            Some("v1:i0238")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
-            ),
-            Some("v1:i0238")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0238"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"),
-            Some("v1:i0239")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
-            ),
-            Some("v1:i0239")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0239"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"),
-            Some("v1:i0240")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
-            ),
-            Some("v1:i0240")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0240"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"),
-            Some("v1:i0241")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
-            ),
-            Some("v1:i0241")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0241"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"),
-            Some("v1:i0242")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
-            ),
-            Some("v1:i0242")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0242"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"),
-            Some("v1:i0243")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
-            ),
-            Some("v1:i0243")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0243"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"),
-            Some("v1:i0244")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
-            ),
-            Some("v1:i0244")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0244"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"),
-            Some("v1:i0245")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
-            ),
-            Some("v1:i0245")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0245"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"),
-            Some("v1:i0246")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
-            ),
-            Some("v1:i0246")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0246"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"),
-            Some("v1:i0247")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
-            ),
-            Some("v1:i0247")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0247"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"),
-            Some("v1:i0248")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
-            ),
-            Some("v1:i0248")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0248"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"),
-            Some("v1:i0249")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
-            ),
-            Some("v1:i0249")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0249"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"),
-            Some("v1:i0250")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
-            ),
-            Some("v1:i0250")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0250"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"),
-            Some("v1:i0251")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
-            ),
-            Some("v1:i0251")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0251"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"),
-            Some("v1:i0195")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4"
-            ),
-            Some("v1:i0195")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0195"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"),
-            Some("v1:i0199")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
-            ),
-            Some("v1:i0199")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0199"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"),
-            Some("v1:i0196")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4"
-            ),
-            Some("v1:i0196")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0196"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"),
-            Some("v1:i0200")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
-            ),
-            Some("v1:i0200")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0200"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"),
-            Some("v1:i0179")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8"
-            ),
-            Some("v1:i0179")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0179"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"),
-            Some("v1:i0183")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
-            ),
-            Some("v1:i0183")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0183"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"),
-            Some("v1:i0180")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8"
-            ),
-            Some("v1:i0180")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0180"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"),
-            Some("v1:i0184")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
-            ),
-            Some("v1:i0184")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0184"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"),
-            Some("v1:i0197")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4"
-            ),
-            Some("v1:i0197")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0197"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"),
-            Some("v1:i0198")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4"
-            ),
-            Some("v1:i0198")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0198"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"),
-            Some("v1:i0202")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
-            ),
-            Some("v1:i0202")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0202"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"),
-            Some("v1:i0201")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
-            ),
-            Some("v1:i0201")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0201"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"),
-            Some("v1:i0181")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8"
-            ),
-            Some("v1:i0181")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0181"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"),
-            Some("v1:i0182")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8"
-            ),
-            Some("v1:i0182")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0182"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"),
-            Some("v1:i0186")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
-            ),
-            Some("v1:i0186")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0186"
-        ));
-    }
-    #[test]
-    fn mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths()
-     {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"),
-            Some("v1:i0185")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
-            ),
-            Some("v1:i0185")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0185"
-        ));
-    }
-    #[test]
-    fn movmatrix_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"),
-            Some("v1:i0305")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::movmatrix_trans_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wmma::movmatrix_trans_b16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wmma::movmatrix_trans_b16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wmma::movmatrix_trans_b16"),
-            Some("v1:i0305")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0305"
-        ));
-    }
-    #[test]
-    fn mul_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"),
-            Some("v1:i0066")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::mul_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::mul_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::mul_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::mul_bf16x2"),
-            Some("v1:i0066")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0066"
-        ));
-    }
-    #[test]
-    fn mul_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"),
-            Some("v1:i0076")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::mul_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16x2::mul_f16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::mul_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::mul_f16x2"),
-            Some("v1:i0076")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0076"
-        ));
-    }
-    #[test]
-    fn mul_f32x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"),
-            Some("v1:i0999")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f32x2::mul_f32x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f32x2::mul_f32x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f32x2::mul_f32x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f32x2::mul_f32x2"),
-            Some("v1:i0999")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0999"
-        ));
-    }
-    #[test]
-    fn mul_ftz_f32x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"),
-            Some("v1:i1000")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f32x2::mul_ftz_f32x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f32x2::mul_ftz_f32x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f32x2::mul_ftz_f32x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f32x2::mul_ftz_f32x2"),
-            Some("v1:i1000")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1000"
-        ));
-    }
-    #[test]
-    fn mul_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"),
-            Some("v1:i0406")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rm_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rm_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rm_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rm_f32"),
-            Some("v1:i0406")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0406"
-        ));
-    }
-    #[test]
-    fn mul_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"),
-            Some("v1:i0392")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rm_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rm_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rm_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rm_f64"),
-            Some("v1:i0392")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0392"
-        ));
-    }
-    #[test]
-    fn mul_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"),
-            Some("v1:i0407")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rm_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rm_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rm_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rm_ftz_f32"),
-            Some("v1:i0407")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0407"
-        ));
-    }
-    #[test]
-    fn mul_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"),
-            Some("v1:i0402")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rn_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rn_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rn_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rn_f32"),
-            Some("v1:i0402")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0402"
-        ));
-    }
-    #[test]
-    fn mul_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"),
-            Some("v1:i0390")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rn_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rn_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rn_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rn_f64"),
-            Some("v1:i0390")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0390"
-        ));
-    }
-    #[test]
-    fn mul_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"),
-            Some("v1:i0403")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rn_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rn_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rn_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rn_ftz_f32"),
-            Some("v1:i0403")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0403"
-        ));
-    }
-    #[test]
-    fn mul_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"),
-            Some("v1:i0408")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rp_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rp_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rp_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rp_f32"),
-            Some("v1:i0408")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0408"
-        ));
-    }
-    #[test]
-    fn mul_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"),
-            Some("v1:i0393")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rp_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rp_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rp_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rp_f64"),
-            Some("v1:i0393")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0393"
-        ));
-    }
-    #[test]
-    fn mul_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"),
-            Some("v1:i0409")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rp_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rp_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rp_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rp_ftz_f32"),
-            Some("v1:i0409")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0409"
-        ));
-    }
-    #[test]
-    fn mul_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"),
-            Some("v1:i0404")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rz_f32"),
-            Some("v1:i0404")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0404"
-        ));
-    }
-    #[test]
-    fn mul_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"),
-            Some("v1:i0391")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rz_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rz_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rz_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rz_f64"),
-            Some("v1:i0391")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0391"
-        ));
-    }
-    #[test]
-    fn mul_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"),
-            Some("v1:i0405")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::mul_rz_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::mul_rz_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::mul_rz_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::mul_rz_ftz_f32"),
-            Some("v1:i0405")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0405"
-        ));
-    }
-    #[test]
-    fn nanosleep_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"),
-            Some("v1:i0316")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::barrier::nanosleep"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::barrier::nanosleep"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::barrier::nanosleep"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::barrier::nanosleep"),
-            Some("v1:i0316")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0316"
-        ));
-    }
-    #[test]
-    fn neg_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"),
-            Some("v1:i0069")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::neg_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::neg_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::neg_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::neg_bf16x2"),
-            Some("v1:i0069")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0069"
-        ));
-    }
-    #[test]
-    fn neg_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"),
-            Some("v1:i0079")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::neg_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16x2::neg_f16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::neg_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::neg_f16x2"),
-            Some("v1:i0079")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0079"
-        ));
-    }
-    #[test]
-    fn nsmid_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"),
-            Some("v1:i0289")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::thread::nsmid"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::thread::nsmid"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::nsmid"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::nsmid"),
-            Some("v1:i0289")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::nsmid"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::nsmid"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::nsmid"),
-            Some("v1:i0289")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0289"
-        ));
-    }
-    #[test]
-    fn nwarpid_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292"),
-            Some("v1:i0292")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::nwarpid"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::warp::nwarpid"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::nwarpid"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::nwarpid"),
-            Some("v1:i0292")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0292"
-        ));
-    }
-    #[test]
-    fn packed_atomic_add_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"),
-            Some("v1:i0015")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::atomic::atom_add_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::atomic::atom_add_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::atomic::atom_add_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::atomic::atom_add_bf16x2"),
-            Some("v1:i0015")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0015"
-        ));
-    }
-    #[test]
-    fn packed_atomic_add_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"),
-            Some("v1:i0014")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::atomic::atom_add_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::atomic::atom_add_f16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::atomic::atom_add_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::atomic::atom_add_f16x2"),
-            Some("v1:i0014")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0014"
-        ));
-    }
-    #[test]
-    fn pmevent_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"),
-            Some("v1:i0297")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::debug::pmevent"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::debug::__prof_trigger"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::debug::__prof_trigger"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::debug::__prof_trigger"),
-            Some("v1:i0297")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0297"
-        ));
-    }
-    #[test]
-    fn prefetch_tma_descriptor_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"),
-            Some("v1:i0887")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::prefetch_tma_descriptor"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::prefetch_tma_descriptor"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::prefetch_tma_descriptor"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::prefetch_tma_descriptor"),
-            Some("v1:i0887")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0887"
-        ));
-    }
-    #[test]
-    fn prmt_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252"),
-            Some("v1:i0252")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path("cuda_intrinsics::prmt::prmt"));
-        assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::prmt::prmt"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::prmt::prmt"),
-            Some("v1:i0252")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0252"
-        ));
-    }
-    #[test]
-    fn prmt_b4e_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254"),
-            Some("v1:i0254")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::prmt::prmt_b4e"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_b4e"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::prmt::prmt_b4e"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::prmt::prmt_b4e"),
-            Some("v1:i0254")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0254"
-        ));
-    }
-    #[test]
-    fn prmt_ecl_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256"),
-            Some("v1:i0256")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::prmt::prmt_ecl"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_ecl"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::prmt::prmt_ecl"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::prmt::prmt_ecl"),
-            Some("v1:i0256")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0256"
-        ));
-    }
-    #[test]
-    fn prmt_ecr_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257"),
-            Some("v1:i0257")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::prmt::prmt_ecr"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_ecr"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::prmt::prmt_ecr"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::prmt::prmt_ecr"),
-            Some("v1:i0257")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0257"
-        ));
-    }
-    #[test]
-    fn prmt_f4e_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253"),
-            Some("v1:i0253")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::prmt::prmt_f4e"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_f4e"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::prmt::prmt_f4e"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::prmt::prmt_f4e"),
-            Some("v1:i0253")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0253"
-        ));
-    }
-    #[test]
-    fn prmt_rc16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"),
-            Some("v1:i0258")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::prmt::prmt_rc16"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_rc16"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::prmt::prmt_rc16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::prmt::prmt_rc16"),
-            Some("v1:i0258")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0258"
-        ));
-    }
-    #[test]
-    fn prmt_rc8_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255"),
-            Some("v1:i0255")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::prmt::prmt_rc8"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_rc8"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::prmt::prmt_rc8"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::prmt::prmt_rc8"),
-            Some("v1:i0255")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0255"
-        ));
-    }
-    #[test]
-    fn rcp_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"),
-            Some("v1:i0788")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_approx_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_approx_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_approx_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_approx_ftz_f32"),
-            Some("v1:i0788")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0788"
-        ));
-    }
-    #[test]
-    fn rcp_approx_ftz_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"),
-            Some("v1:i0797")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_approx_ftz_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_approx_ftz_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_approx_ftz_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_approx_ftz_f64"),
-            Some("v1:i0797")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0797"
-        ));
-    }
-    #[test]
-    fn rcp_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"),
-            Some("v1:i0793")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rm_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rm_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rm_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rm_f32"),
-            Some("v1:i0793")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0793"
-        ));
-    }
-    #[test]
-    fn rcp_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"),
-            Some("v1:i0800")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rm_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rm_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rm_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rm_f64"),
-            Some("v1:i0800")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0800"
-        ));
-    }
-    #[test]
-    fn rcp_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"),
-            Some("v1:i0794")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rm_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rm_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rm_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rm_ftz_f32"),
-            Some("v1:i0794")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0794"
-        ));
-    }
-    #[test]
-    fn rcp_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"),
-            Some("v1:i0789")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rn_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rn_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rn_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rn_f32"),
-            Some("v1:i0789")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0789"
-        ));
-    }
-    #[test]
-    fn rcp_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"),
-            Some("v1:i0798")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rn_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rn_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rn_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rn_f64"),
-            Some("v1:i0798")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0798"
-        ));
-    }
-    #[test]
-    fn rcp_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"),
-            Some("v1:i0790")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rn_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rn_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rn_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rn_ftz_f32"),
-            Some("v1:i0790")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0790"
-        ));
-    }
-    #[test]
-    fn rcp_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"),
-            Some("v1:i0795")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rp_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rp_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rp_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rp_f32"),
-            Some("v1:i0795")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0795"
-        ));
-    }
-    #[test]
-    fn rcp_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"),
-            Some("v1:i0801")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rp_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rp_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rp_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rp_f64"),
-            Some("v1:i0801")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0801"
-        ));
-    }
-    #[test]
-    fn rcp_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"),
-            Some("v1:i0796")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rp_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rp_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rp_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rp_ftz_f32"),
-            Some("v1:i0796")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0796"
-        ));
-    }
-    #[test]
-    fn rcp_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"),
-            Some("v1:i0791")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rz_f32"),
-            Some("v1:i0791")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0791"
-        ));
-    }
-    #[test]
-    fn rcp_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"),
-            Some("v1:i0799")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rz_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rz_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rz_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rz_f64"),
-            Some("v1:i0799")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0799"
-        ));
-    }
-    #[test]
-    fn rcp_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"),
-            Some("v1:i0792")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rcp_rz_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rcp_rz_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rcp_rz_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rcp_rz_ftz_f32"),
-            Some("v1:i0792")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0792"
-        ));
-    }
-    #[test]
-    fn redux_sync_add_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"),
-            Some("v1:i0017")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_add"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_add"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_add"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_add"),
-            Some("v1:i0017")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0017"
-        ));
-    }
-    #[test]
-    fn redux_sync_and_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"),
-            Some("v1:i0022")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_and"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_and"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_and"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_and"),
-            Some("v1:i0022")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0022"
-        ));
-    }
-    #[test]
-    fn redux_sync_max_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"),
-            Some("v1:i1009")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_max_abs_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_abs_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_abs_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_max_abs_f32"),
-            Some("v1:i1009")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1009"
-        ));
-    }
-    #[test]
-    fn redux_sync_max_abs_nan_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"),
-            Some("v1:i1010")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_max_abs_nan_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_abs_nan_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_abs_nan_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_max_abs_nan_f32"),
-            Some("v1:i1010")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1010"
-        ));
-    }
-    #[test]
-    fn redux_sync_max_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"),
-            Some("v1:i1007")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_max_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_max_f32"),
-            Some("v1:i1007")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1007"
-        ));
-    }
-    #[test]
-    fn redux_sync_max_i32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"),
-            Some("v1:i0021")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_max_i32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_i32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_i32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_max_i32"),
-            Some("v1:i0021")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0021"
-        ));
-    }
-    #[test]
-    fn redux_sync_max_nan_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"),
-            Some("v1:i1008")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_max_nan_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_nan_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_nan_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_max_nan_f32"),
-            Some("v1:i1008")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1008"
-        ));
-    }
-    #[test]
-    fn redux_sync_max_u32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"),
-            Some("v1:i0020")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_max_u32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_u32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_max_u32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_max_u32"),
-            Some("v1:i0020")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0020"
-        ));
-    }
-    #[test]
-    fn redux_sync_min_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"),
-            Some("v1:i1005")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_min_abs_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_abs_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_abs_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_min_abs_f32"),
-            Some("v1:i1005")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1005"
-        ));
-    }
-    #[test]
-    fn redux_sync_min_abs_nan_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"),
-            Some("v1:i1006")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_min_abs_nan_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_abs_nan_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_abs_nan_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_min_abs_nan_f32"),
-            Some("v1:i1006")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1006"
-        ));
-    }
-    #[test]
-    fn redux_sync_min_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"),
-            Some("v1:i1003")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_min_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_min_f32"),
-            Some("v1:i1003")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1003"
-        ));
-    }
-    #[test]
-    fn redux_sync_min_i32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"),
-            Some("v1:i0019")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_min_i32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_i32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_i32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_min_i32"),
-            Some("v1:i0019")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0019"
-        ));
-    }
-    #[test]
-    fn redux_sync_min_nan_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"),
-            Some("v1:i1004")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_min_nan_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_nan_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_nan_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_min_nan_f32"),
-            Some("v1:i1004")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1004"
-        ));
-    }
-    #[test]
-    fn redux_sync_min_u32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"),
-            Some("v1:i0018")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_min_u32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_u32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_min_u32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_min_u32"),
-            Some("v1:i0018")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0018"
-        ));
-    }
-    #[test]
-    fn redux_sync_or_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"),
-            Some("v1:i0023")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_or"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_or"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_or"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_or"),
-            Some("v1:i0023")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0023"
-        ));
-    }
-    #[test]
-    fn redux_sync_xor_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"),
-            Some("v1:i0024")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::redux_sync_xor"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_xor"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::redux_sync_xor"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::redux_sync_xor"),
-            Some("v1:i0024")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0024"
-        ));
-    }
-    #[test]
-    fn rsqrt_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"),
-            Some("v1:i0802")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rsqrt_approx_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rsqrt_approx_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rsqrt_approx_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rsqrt_approx_f32"),
-            Some("v1:i0802")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0802"
-        ));
-    }
-    #[test]
-    fn rsqrt_approx_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"),
-            Some("v1:i0804")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rsqrt_approx_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rsqrt_approx_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rsqrt_approx_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rsqrt_approx_f64"),
-            Some("v1:i0804")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0804"
-        ));
-    }
-    #[test]
-    fn rsqrt_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"),
-            Some("v1:i0803")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::rsqrt_approx_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::rsqrt_approx_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::rsqrt_approx_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::rsqrt_approx_ftz_f32"),
-            Some("v1:i0803")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0803"
-        ));
-    }
-    #[test]
-    fn setmaxnreg_dec_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"),
-            Some("v1:i0916")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::thread::setmaxnreg_dec"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::__setmaxnreg_dec"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::__setmaxnreg_dec"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::__setmaxnreg_dec"),
-            Some("v1:i0916")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0916"
-        ));
-    }
-    #[test]
-    fn setmaxnreg_inc_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"),
-            Some("v1:i0915")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::thread::setmaxnreg_inc"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::__setmaxnreg_inc"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::__setmaxnreg_inc"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::__setmaxnreg_inc"),
-            Some("v1:i0915")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0915"
-        ));
-    }
-    #[test]
-    fn shuffle_down_f32_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"),
-            Some("v1:i0056")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_down_f32_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_down_f32_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_down_f32_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_down_f32_sync"),
-            Some("v1:i0056")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0056"
-        ));
-    }
-    #[test]
-    fn shuffle_down_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"),
-            Some("v1:i0052")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_down_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_down_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_down_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_down_sync"),
-            Some("v1:i0052")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0052"
-        ));
-    }
-    #[test]
-    fn shuffle_down_u64_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"),
-            Some("v1:i0060")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_down_u64_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_down_u64_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_down_u64_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_down_u64_sync"),
-            Some("v1:i0060")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0060"
-        ));
-    }
-    #[test]
-    fn shuffle_f32_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"),
-            Some("v1:i0054")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_f32_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_f32_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_f32_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_f32_sync"),
-            Some("v1:i0054")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0054"
-        ));
-    }
-    #[test]
-    fn shuffle_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"),
-            Some("v1:i0050")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_sync"),
-            Some("v1:i0050")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0050"
-        ));
-    }
-    #[test]
-    fn shuffle_u64_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"),
-            Some("v1:i0058")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_u64_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_u64_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_u64_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_u64_sync"),
-            Some("v1:i0058")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0058"
-        ));
-    }
-    #[test]
-    fn shuffle_up_f32_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"),
-            Some("v1:i0057")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_up_f32_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_up_f32_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_up_f32_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_up_f32_sync"),
-            Some("v1:i0057")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0057"
-        ));
-    }
-    #[test]
-    fn shuffle_up_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"),
-            Some("v1:i0053")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_up_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_up_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_up_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_up_sync"),
-            Some("v1:i0053")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0053"
-        ));
-    }
-    #[test]
-    fn shuffle_up_u64_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"),
-            Some("v1:i0061")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_up_u64_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_up_u64_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_up_u64_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_up_u64_sync"),
-            Some("v1:i0061")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0061"
-        ));
-    }
-    #[test]
-    fn shuffle_xor_f32_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"),
-            Some("v1:i0055")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_xor_f32_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_xor_f32_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_xor_f32_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_xor_f32_sync"),
-            Some("v1:i0055")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0055"
-        ));
-    }
-    #[test]
-    fn shuffle_xor_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"),
-            Some("v1:i0051")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_xor_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_xor_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_xor_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_xor_sync"),
-            Some("v1:i0051")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0051"
-        ));
-    }
-    #[test]
-    fn shuffle_xor_u64_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"),
-            Some("v1:i0059")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::shuffle_xor_u64_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_xor_u64_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::shuffle_xor_u64_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::shuffle_xor_u64_sync"),
-            Some("v1:i0059")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0059"
-        ));
-    }
-    #[test]
-    fn sin_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"),
-            Some("v1:i0782")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sin_approx_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sin_approx_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sin_approx_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sin_approx_f32"),
-            Some("v1:i0782")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0782"
-        ));
-    }
-    #[test]
-    fn sin_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"),
-            Some("v1:i0783")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sin_approx_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sin_approx_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sin_approx_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sin_approx_ftz_f32"),
-            Some("v1:i0783")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0783"
-        ));
-    }
-    #[test]
-    fn smid_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"),
-            Some("v1:i0288")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::thread::smid"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::thread::smid"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::smid"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::smid"),
-            Some("v1:i0288")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::smid"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::smid"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::smid"),
-            Some("v1:i0288")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0288"
-        ));
-    }
-    #[test]
-    fn sqrt_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"),
-            Some("v1:i0805")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_approx_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_approx_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_approx_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_approx_f32"),
-            Some("v1:i0805")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0805"
-        ));
-    }
-    #[test]
-    fn sqrt_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"),
-            Some("v1:i0806")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_approx_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_approx_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_approx_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_approx_ftz_f32"),
-            Some("v1:i0806")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0806"
-        ));
-    }
-    #[test]
-    fn sqrt_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"),
-            Some("v1:i0811")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rm_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rm_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rm_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rm_f32"),
-            Some("v1:i0811")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0811"
-        ));
-    }
-    #[test]
-    fn sqrt_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"),
-            Some("v1:i0817")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rm_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rm_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rm_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rm_f64"),
-            Some("v1:i0817")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0817"
-        ));
-    }
-    #[test]
-    fn sqrt_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"),
-            Some("v1:i0812")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rm_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rm_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rm_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rm_ftz_f32"),
-            Some("v1:i0812")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0812"
-        ));
-    }
-    #[test]
-    fn sqrt_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"),
-            Some("v1:i0807")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rn_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rn_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rn_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rn_f32"),
-            Some("v1:i0807")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0807"
-        ));
-    }
-    #[test]
-    fn sqrt_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"),
-            Some("v1:i0815")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rn_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rn_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rn_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rn_f64"),
-            Some("v1:i0815")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0815"
-        ));
-    }
-    #[test]
-    fn sqrt_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"),
-            Some("v1:i0808")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rn_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rn_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rn_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rn_ftz_f32"),
-            Some("v1:i0808")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0808"
-        ));
-    }
-    #[test]
-    fn sqrt_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"),
-            Some("v1:i0813")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rp_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rp_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rp_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rp_f32"),
-            Some("v1:i0813")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0813"
-        ));
-    }
-    #[test]
-    fn sqrt_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"),
-            Some("v1:i0818")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rp_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rp_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rp_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rp_f64"),
-            Some("v1:i0818")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0818"
-        ));
-    }
-    #[test]
-    fn sqrt_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"),
-            Some("v1:i0814")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rp_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rp_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rp_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rp_ftz_f32"),
-            Some("v1:i0814")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0814"
-        ));
-    }
-    #[test]
-    fn sqrt_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"),
-            Some("v1:i0809")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rz_f32"),
-            Some("v1:i0809")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0809"
-        ));
-    }
-    #[test]
-    fn sqrt_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"),
-            Some("v1:i0816")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rz_f64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rz_f64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rz_f64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rz_f64"),
-            Some("v1:i0816")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0816"
-        ));
-    }
-    #[test]
-    fn sqrt_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"),
-            Some("v1:i0810")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::sqrt_rz_ftz_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rz_ftz_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::sqrt_rz_ftz_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::sqrt_rz_ftz_f32"),
-            Some("v1:i0810")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0810"
-        ));
-    }
-    #[test]
-    fn stmatrix_m8n8_x2_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"),
-            Some("v1:i0301")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::stmatrix_m8n8_x2_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::stmatrix_m8n8_x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::stmatrix_m8n8_x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::stmatrix_m8n8_x2"),
-            Some("v1:i0301")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0301"
-        ));
-    }
-    #[test]
-    fn stmatrix_m8n8_x2_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"),
-            Some("v1:i0302")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::stmatrix_m8n8_x2_trans_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::stmatrix_m8n8_x2_trans"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::stmatrix_m8n8_x2_trans"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::stmatrix_m8n8_x2_trans"),
-            Some("v1:i0302")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0302"
-        ));
-    }
-    #[test]
-    fn stmatrix_m8n8_x4_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"),
-            Some("v1:i0303")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::stmatrix_m8n8_x4_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::stmatrix_m8n8_x4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::stmatrix_m8n8_x4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::stmatrix_m8n8_x4"),
-            Some("v1:i0303")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0303"
-        ));
-    }
-    #[test]
-    fn stmatrix_m8n8_x4_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"),
-            Some("v1:i0304")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::matrix::stmatrix_m8n8_x4_trans_b16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::stmatrix_m8n8_x4_trans"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::stmatrix_m8n8_x4_trans"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::stmatrix_m8n8_x4_trans"),
-            Some("v1:i0304")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0304"
-        ));
-    }
-    #[test]
-    fn sub_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"),
-            Some("v1:i0065")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::bf16x2::sub_bf16x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::bf16x2::sub_bf16x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::bf16x2::sub_bf16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::bf16x2::sub_bf16x2"),
-            Some("v1:i0065")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0065"
-        ));
-    }
-    #[test]
-    fn sub_f16x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"),
-            Some("v1:i0075")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f16x2::sub_f16x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f16x2::sub_f16x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f16x2::sub_f16x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f16x2::sub_f16x2"),
-            Some("v1:i0075")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0075"
-        ));
-    }
-    #[test]
-    fn sub_f32x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"),
-            Some("v1:i0997")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f32x2::sub_f32x2"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::f32x2::sub_f32x2"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f32x2::sub_f32x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f32x2::sub_f32x2"),
-            Some("v1:i0997")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0997"
-        ));
-    }
-    #[test]
-    fn sub_ftz_f32x2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"),
-            Some("v1:i0998")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::f32x2::sub_ftz_f32x2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::f32x2::sub_ftz_f32x2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::f32x2::sub_ftz_f32x2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::f32x2::sub_ftz_f32x2"),
-            Some("v1:i0998")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0998"
-        ));
-    }
-    #[test]
-    fn sync_mask_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"),
-            Some("v1:i0049")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::sync_mask"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::warp::sync_mask"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::sync_mask"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::sync_mask"),
-            Some("v1:i0049")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0049"
-        ));
-    }
-    #[test]
-    fn sync_threads_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"),
-            Some("v1:i0034")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::thread::sync_threads"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::sync_threads"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::sync_threads"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::sync_threads"),
-            Some("v1:i0034")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::sync_threads"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::sync_threads"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::sync_threads"),
-            Some("v1:i0034")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0034"
-        ));
-    }
-    #[test]
-    fn tanh_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"),
-            Some("v1:i0821")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::float::tanh_approx_f32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::float::tanh_approx_f32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::float::tanh_approx_f32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::float::tanh_approx_f32"),
-            Some("v1:i0821")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0821"
-        ));
-    }
-    #[test]
-    fn tcgen05_alloc_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"),
-            Some("v1:i0343")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_alloc"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_alloc"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_alloc"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_alloc"),
-            Some("v1:i0343")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0343"
-        ));
-    }
-    #[test]
-    fn tcgen05_alloc_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"),
-            Some("v1:i0359")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_alloc_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_alloc_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_alloc_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_alloc_cg2"),
-            Some("v1:i0359")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0359"
-        ));
-    }
-    #[test]
-    fn tcgen05_commit_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"),
-            Some("v1:i0348")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_commit"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit"),
-            Some("v1:i0348")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0348"
-        ));
-    }
-    #[test]
-    fn tcgen05_commit_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"),
-            Some("v1:i0363")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_commit_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit_cg2"),
-            Some("v1:i0363")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0363"
-        ));
-    }
-    #[test]
-    fn tcgen05_commit_multicast_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"),
-            Some("v1:i0760")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_commit_multicast"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit_multicast"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit_multicast"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit_multicast"),
-            Some("v1:i0760")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0760"
-        ));
-    }
-    #[test]
-    fn tcgen05_commit_multicast_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"),
-            Some("v1:i0365")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_commit_multicast_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit_multicast_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit_multicast_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit_multicast_cg2"),
-            Some("v1:i0365")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0365"
-        ));
-    }
-    #[test]
-    fn tcgen05_commit_shared_cluster_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"),
-            Some("v1:i0349")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_commit_shared_cluster"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit_shared_cluster"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit_shared_cluster"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit_shared_cluster"),
-            Some("v1:i0349")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0349"
-        ));
-    }
-    #[test]
-    fn tcgen05_commit_shared_cluster_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"),
-            Some("v1:i0364")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_commit_shared_cluster_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2"),
-            Some("v1:i0364")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0364"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_128x128b_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"),
-            Some("v1:i0582")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b"),
-            Some("v1:i0582")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0582"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_128x128b_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"),
-            Some("v1:i0578")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b_b4x16_p64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64"),
-            Some("v1:i0578")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0578"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_128x128b_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"),
-            Some("v1:i0579")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2"),
-            Some("v1:i0579")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0579"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_128x128b_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"),
-            Some("v1:i0580")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b_b6x16_p32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32"),
-            Some("v1:i0580")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0580"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_128x128b_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"),
-            Some("v1:i0581")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2"),
-            Some("v1:i0581")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0581"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_128x128b_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"),
-            Some("v1:i0583")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x128b_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b_cg2"),
-            Some("v1:i0583")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0583"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_128x256b_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"),
-            Some("v1:i0584")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_128x256b_b4x16_p64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64"),
-            Some("v1:i0584")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0584"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_128x256b_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"),
-            Some("v1:i0585")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2"),
-            Some("v1:i0585")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0585"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_128x256b_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"),
-            Some("v1:i0586")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_128x256b_b6x16_p32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32"),
-            Some("v1:i0586")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0586"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_128x256b_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"),
-            Some("v1:i0587")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2"),
-            Some("v1:i0587")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0587"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_32x128b_warpx4_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"),
-            Some("v1:i0592")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4"),
-            Some("v1:i0592")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0592"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_32x128b_warpx4_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"),
-            Some("v1:i0588")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64"),
-            Some("v1:i0588")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0588"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"),
-            Some("v1:i0589")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
-            ),
-            Some("v1:i0589")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0589"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_32x128b_warpx4_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"),
-            Some("v1:i0590")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32"),
-            Some("v1:i0590")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0590"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"),
-            Some("v1:i0591")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
-            ),
-            Some("v1:i0591")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0591"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_32x128b_warpx4_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"),
-            Some("v1:i0593")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2"),
-            Some("v1:i0593")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0593"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_4x256b_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"),
-            Some("v1:i0598")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b"),
-            Some("v1:i0598")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0598"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_4x256b_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"),
-            Some("v1:i0594")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b_b4x16_p64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64"),
-            Some("v1:i0594")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0594"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_4x256b_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"),
-            Some("v1:i0595")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2"),
-            Some("v1:i0595")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0595"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_4x256b_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"),
-            Some("v1:i0596")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b_b6x16_p32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32"),
-            Some("v1:i0596")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0596"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_4x256b_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"),
-            Some("v1:i0597")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2"),
-            Some("v1:i0597")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0597"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_4x256b_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"),
-            Some("v1:i0599")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_4x256b_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b_cg2"),
-            Some("v1:i0599")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0599"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_01_23_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"),
-            Some("v1:i0604")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23"),
-            Some("v1:i0604")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0604"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"),
-            Some("v1:i0600")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
-            ),
-            Some("v1:i0600")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0600"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths()
-    {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"),
-            Some("v1:i0601")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
-            ),
-            Some("v1:i0601")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0601"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"),
-            Some("v1:i0602")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
-            ),
-            Some("v1:i0602")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0602"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths()
-    {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"),
-            Some("v1:i0603")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
-            ),
-            Some("v1:i0603")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0603"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_01_23_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"),
-            Some("v1:i0605")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2"),
-            Some("v1:i0605")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0605"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_02_13_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"),
-            Some("v1:i0610")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13"),
-            Some("v1:i0610")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0610"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"),
-            Some("v1:i0606")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
-            ),
-            Some("v1:i0606")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0606"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths()
-    {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"),
-            Some("v1:i0607")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
-            ),
-            Some("v1:i0607")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0607"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"),
-            Some("v1:i0608")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
-            ),
-            Some("v1:i0608")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0608"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths()
-    {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"),
-            Some("v1:i0609")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
-            ),
-            Some("v1:i0609")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0609"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_64x128b_warpx2_02_13_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"),
-            Some("v1:i0611")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2"),
-            Some("v1:i0611")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0611"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_smem_to_tmem_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"),
-            Some("v1:i0354")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_smem_to_tmem"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_smem_to_tmem"),
-            Some("v1:i0354")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0354"
-        ));
-    }
-    #[test]
-    fn tcgen05_cp_smem_to_tmem_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"),
-            Some("v1:i0366")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_cp_smem_to_tmem_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2"),
-            Some("v1:i0366")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0366"
-        ));
-    }
-    #[test]
-    fn tcgen05_dealloc_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"),
-            Some("v1:i0344")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_dealloc"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_dealloc"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_dealloc"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_dealloc"),
-            Some("v1:i0344")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0344"
-        ));
-    }
-    #[test]
-    fn tcgen05_dealloc_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"),
-            Some("v1:i0360")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_dealloc_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_dealloc_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_dealloc_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_dealloc_cg2"),
-            Some("v1:i0360")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0360"
-        ));
-    }
-    #[test]
-    fn tcgen05_fence_after_thread_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"),
-            Some("v1:i0347")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_fence_after_thread_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_fence_after_thread_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_fence_after_thread_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_fence_after_thread_sync"),
-            Some("v1:i0347")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0347"
-        ));
-    }
-    #[test]
-    fn tcgen05_fence_before_thread_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"),
-            Some("v1:i0346")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_fence_before_thread_sync"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_fence_before_thread_sync"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_fence_before_thread_sync"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_fence_before_thread_sync"),
-            Some("v1:i0346")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0346"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x16_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"),
-            Some("v1:i0637")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x16_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16"),
-            Some("v1:i0637")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0637"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"),
-            Some("v1:i0636")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x16_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw"),
-            Some("v1:i0636")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0636"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x1_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"),
-            Some("v1:i0629")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x1_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16"),
-            Some("v1:i0629")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0629"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"),
-            Some("v1:i0628")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x1_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw"),
-            Some("v1:i0628")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0628"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x2_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"),
-            Some("v1:i0631")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x2_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16"),
-            Some("v1:i0631")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0631"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"),
-            Some("v1:i0630")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x2_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw"),
-            Some("v1:i0630")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0630"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x32_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"),
-            Some("v1:i0639")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x32_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16"),
-            Some("v1:i0639")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0639"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"),
-            Some("v1:i0638")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x32_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw"),
-            Some("v1:i0638")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0638"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x4_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"),
-            Some("v1:i0633")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x4_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16"),
-            Some("v1:i0633")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0633"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"),
-            Some("v1:i0632")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x4_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw"),
-            Some("v1:i0632")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0632"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x64_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"),
-            Some("v1:i0641")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x64_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16"),
-            Some("v1:i0641")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0641"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"),
-            Some("v1:i0640")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x64_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw"),
-            Some("v1:i0640")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0640"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x8_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"),
-            Some("v1:i0635")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x8_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16"),
-            Some("v1:i0635")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0635"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x128b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"),
-            Some("v1:i0634")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x8_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw"),
-            Some("v1:i0634")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0634"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_pure_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"),
-            Some("v1:i0356")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_pure"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_pure"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_pure"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_pure"),
-            Some("v1:i0356")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0356"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x16_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"),
-            Some("v1:i0651")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x16_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16"),
-            Some("v1:i0651")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0651"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"),
-            Some("v1:i0650")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x16_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw"),
-            Some("v1:i0650")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0650"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x1_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"),
-            Some("v1:i0643")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x1_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16"),
-            Some("v1:i0643")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0643"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"),
-            Some("v1:i0642")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x1_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw"),
-            Some("v1:i0642")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0642"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x2_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"),
-            Some("v1:i0645")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x2_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16"),
-            Some("v1:i0645")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0645"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"),
-            Some("v1:i0644")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x2_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw"),
-            Some("v1:i0644")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0644"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x32_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"),
-            Some("v1:i0653")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x32_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16"),
-            Some("v1:i0653")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0653"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"),
-            Some("v1:i0652")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x32_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw"),
-            Some("v1:i0652")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0652"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x4_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"),
-            Some("v1:i0647")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x4_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16"),
-            Some("v1:i0647")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0647"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"),
-            Some("v1:i0646")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x4_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw"),
-            Some("v1:i0646")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0646"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x8_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"),
-            Some("v1:i0649")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x8_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16"),
-            Some("v1:i0649")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0649"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x8_pure_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"),
-            Some("v1:i0355")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x8_pure"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure"),
-            Some("v1:i0355")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0355"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x256b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"),
-            Some("v1:i0648")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x8_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw"),
-            Some("v1:i0648")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0648"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x128_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"),
-            Some("v1:i0743")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x128_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16"),
-            Some("v1:i0743")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0743"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"),
-            Some("v1:i0742")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x128_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw"),
-            Some("v1:i0742")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0742"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x16_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"),
-            Some("v1:i0737")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x16_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16"),
-            Some("v1:i0737")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0737"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"),
-            Some("v1:i0736")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x16_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw"),
-            Some("v1:i0736")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0736"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x1_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"),
-            Some("v1:i0729")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x1_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16"),
-            Some("v1:i0729")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0729"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"),
-            Some("v1:i0728")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x1_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw"),
-            Some("v1:i0728")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0728"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x2_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"),
-            Some("v1:i0731")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x2_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16"),
-            Some("v1:i0731")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0731"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"),
-            Some("v1:i0730")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x2_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw"),
-            Some("v1:i0730")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0730"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x32_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"),
-            Some("v1:i0739")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x32_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16"),
-            Some("v1:i0739")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0739"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"),
-            Some("v1:i0738")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x32_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw"),
-            Some("v1:i0738")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0738"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x4_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"),
-            Some("v1:i0733")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x4_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16"),
-            Some("v1:i0733")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0733"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"),
-            Some("v1:i0732")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x4_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw"),
-            Some("v1:i0732")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0732"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x64_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"),
-            Some("v1:i0741")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x64_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16"),
-            Some("v1:i0741")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0741"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"),
-            Some("v1:i0740")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x64_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw"),
-            Some("v1:i0740")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0740"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x8_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"),
-            Some("v1:i0735")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x8_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16"),
-            Some("v1:i0735")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0735"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x32bx2_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"),
-            Some("v1:i0734")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x8_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw"),
-            Some("v1:i0734")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0734"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x128_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"),
-            Some("v1:i0627")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x128_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16"),
-            Some("v1:i0627")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0627"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"),
-            Some("v1:i0626")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x128_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw"),
-            Some("v1:i0626")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0626"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x16_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"),
-            Some("v1:i0621")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x16_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16"),
-            Some("v1:i0621")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0621"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"),
-            Some("v1:i0620")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x16_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw"),
-            Some("v1:i0620")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0620"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x1_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"),
-            Some("v1:i0613")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x1_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16"),
-            Some("v1:i0613")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0613"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"),
-            Some("v1:i0612")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x1_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw"),
-            Some("v1:i0612")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0612"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x2_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"),
-            Some("v1:i0615")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x2_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16"),
-            Some("v1:i0615")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0615"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"),
-            Some("v1:i0614")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x2_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw"),
-            Some("v1:i0614")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0614"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x32_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"),
-            Some("v1:i0623")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x32_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16"),
-            Some("v1:i0623")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0623"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"),
-            Some("v1:i0622")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x32_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw"),
-            Some("v1:i0622")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0622"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x4_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"),
-            Some("v1:i0617")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x4_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16"),
-            Some("v1:i0617")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0617"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"),
-            Some("v1:i0616")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x4_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw"),
-            Some("v1:i0616")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0616"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x64_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"),
-            Some("v1:i0625")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x64_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16"),
-            Some("v1:i0625")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0625"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"),
-            Some("v1:i0624")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x64_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw"),
-            Some("v1:i0624")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0624"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x8_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"),
-            Some("v1:i0619")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x8_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16"),
-            Some("v1:i0619")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0619"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_16x64b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"),
-            Some("v1:i0618")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x8_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw"),
-            Some("v1:i0618")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0618"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x128_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"),
-            Some("v1:i0669")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x128_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16"),
-            Some("v1:i0669")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0669"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"),
-            Some("v1:i0668")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x128_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw"),
-            Some("v1:i0668")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0668"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x16_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"),
-            Some("v1:i0663")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x16_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16"),
-            Some("v1:i0663")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0663"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"),
-            Some("v1:i0662")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x16_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw"),
-            Some("v1:i0662")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0662"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x1_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"),
-            Some("v1:i0655")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x1_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16"),
-            Some("v1:i0655")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0655"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"),
-            Some("v1:i0654")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x1_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw"),
-            Some("v1:i0654")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0654"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x2_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"),
-            Some("v1:i0657")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x2_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16"),
-            Some("v1:i0657")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0657"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"),
-            Some("v1:i0656")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x2_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw"),
-            Some("v1:i0656")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0656"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x32_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"),
-            Some("v1:i0665")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x32_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16"),
-            Some("v1:i0665")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0665"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"),
-            Some("v1:i0664")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x32_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw"),
-            Some("v1:i0664")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0664"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x4_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"),
-            Some("v1:i0659")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x4_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16"),
-            Some("v1:i0659")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0659"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"),
-            Some("v1:i0658")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x4_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw"),
-            Some("v1:i0658")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0658"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x64_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"),
-            Some("v1:i0667")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x64_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16"),
-            Some("v1:i0667")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0667"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"),
-            Some("v1:i0666")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x64_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw"),
-            Some("v1:i0666")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0666"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x8_pack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"),
-            Some("v1:i0661")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x8_pack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16"),
-            Some("v1:i0661")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0661"
-        ));
-    }
-    #[test]
-    fn tcgen05_ld_32x32b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"),
-            Some("v1:i0660")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x8_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw"),
-            Some("v1:i0660")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0660"
-        ));
-    }
-    #[test]
-    fn tcgen05_load_wait_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"),
-            Some("v1:i0357")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_load_wait"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_load_wait"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_load_wait"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_load_wait"),
-            Some("v1:i0357")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0357"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"),
-            Some("v1:i1015")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_e2m1"),
-            Some("v1:i1015")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1015"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"),
-            Some("v1:i1013")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_e2m3"),
-            Some("v1:i1013")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1013"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"),
-            Some("v1:i1014")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_e3m2"),
-            Some("v1:i1014")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1014"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"),
-            Some("v1:i1011")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_e4m3"),
-            Some("v1:i1011")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1011"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"),
-            Some("v1:i1012")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_e5m2"),
-            Some("v1:i1012")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1012"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"),
-            Some("v1:i0351")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_f16"),
-            Some("v1:i0351")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0351"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_f16_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"),
-            Some("v1:i0362")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_f16_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_f16_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_f16_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_f16_cg2"),
-            Some("v1:i0362")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0362"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_shared_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"),
-            Some("v1:i0763")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_shared"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_shared"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_shared"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_shared"),
-            Some("v1:i0763")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0763"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_sp_shared_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"),
-            Some("v1:i0766")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_sp_shared"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_sp_shared"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_sp_shared"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_sp_shared"),
-            Some("v1:i0766")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0766"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_sp_tensor_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"),
-            Some("v1:i0767")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_sp_tensor"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_sp_tensor"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_sp_tensor"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_sp_tensor"),
-            Some("v1:i0767")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0767"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_sp_tensor_ashift_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"),
-            Some("v1:i0768")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_sp_tensor_ashift"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift"),
-            Some("v1:i0768")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0768"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_tensor_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"),
-            Some("v1:i0764")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_tensor"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_tensor"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_tensor"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_tensor"),
-            Some("v1:i0764")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0764"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_tensor_ashift_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"),
-            Some("v1:i0765")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_tensor_ashift"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_tensor_ashift"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_tensor_ashift"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_tensor_ashift"),
-            Some("v1:i0765")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0765"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_bf16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"),
-            Some("v1:i0352")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_bf16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_bf16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_bf16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_bf16"),
-            Some("v1:i0352")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0352"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_e2m1_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"),
-            Some("v1:i0781")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_e2m1"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_e2m1"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_e2m1"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_e2m1"),
-            Some("v1:i0781")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0781"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_e2m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"),
-            Some("v1:i0779")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_e2m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_e2m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_e2m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_e2m3"),
-            Some("v1:i0779")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0779"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_e3m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"),
-            Some("v1:i0780")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_e3m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_e3m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_e3m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_e3m2"),
-            Some("v1:i0780")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0780"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_e4m3_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"),
-            Some("v1:i0777")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_e4m3"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_e4m3"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_e4m3"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_e4m3"),
-            Some("v1:i0777")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0777"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_e5m2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"),
-            Some("v1:i0778")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_e5m2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_e5m2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_e5m2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_e5m2"),
-            Some("v1:i0778")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0778"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_f16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"),
-            Some("v1:i0350")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_f16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_f16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_f16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_f16"),
-            Some("v1:i0350")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0350"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_shared_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"),
-            Some("v1:i0769")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_shared"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_shared"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_shared"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_ws_shared"),
-            Some("v1:i0769")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0769"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_shared_zero_col_mask_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"),
-            Some("v1:i0770")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_shared_zero_col_mask"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask"
-            ),
-            Some("v1:i0770")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0770"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_sp_shared_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"),
-            Some("v1:i0771")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_sp_shared"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared"),
-            Some("v1:i0771")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0771"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_sp_shared_zero_col_mask_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"),
-            Some("v1:i0772")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_sp_shared_zero_col_mask"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask"
-            ),
-            Some("v1:i0772")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0772"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_sp_tensor_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"),
-            Some("v1:i0773")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_sp_tensor"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor"),
-            Some("v1:i0773")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0773"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_sp_tensor_zero_col_mask_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"),
-            Some("v1:i0774")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_sp_tensor_zero_col_mask"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask"
-            ),
-            Some("v1:i0774")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0774"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_tensor_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"),
-            Some("v1:i0775")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_tensor"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_tensor"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_tensor"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_ws_tensor"),
-            Some("v1:i0775")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0775"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_tensor_zero_col_mask_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"),
-            Some("v1:i0776")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_tensor_zero_col_mask"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker(
-                "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask"
-            ),
-            Some("v1:i0776")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0776"
-        ));
-    }
-    #[test]
-    fn tcgen05_mma_ws_tf32_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"),
-            Some("v1:i0353")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_mma_ws_tf32"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_tf32"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_mma_ws_tf32"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_tf32"),
-            Some("v1:i0353")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0353"
-        ));
-    }
-    #[test]
-    fn tcgen05_relinquish_alloc_permit_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"),
-            Some("v1:i0345")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_relinquish_alloc_permit"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_relinquish_alloc_permit"),
-            Some("v1:i0345")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0345"
-        ));
-    }
-    #[test]
-    fn tcgen05_relinquish_alloc_permit_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"),
-            Some("v1:i0361")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_relinquish_alloc_permit_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2"),
-            Some("v1:i0361")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0361"
-        ));
-    }
-    #[test]
-    fn tcgen05_shift_down_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"),
-            Some("v1:i0761")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_shift_down"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_shift_down"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_shift_down"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_shift_down"),
-            Some("v1:i0761")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0761"
-        ));
-    }
-    #[test]
-    fn tcgen05_shift_down_cg2_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"),
-            Some("v1:i0762")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_shift_down_cg2"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_shift_down_cg2"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_shift_down_cg2"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_shift_down_cg2"),
-            Some("v1:i0762")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0762"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"),
-            Some("v1:i0694")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x16_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw"),
-            Some("v1:i0694")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0694"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x16_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"),
-            Some("v1:i0695")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x16_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16"),
-            Some("v1:i0695")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0695"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"),
-            Some("v1:i0686")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x1_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw"),
-            Some("v1:i0686")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0686"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x1_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"),
-            Some("v1:i0687")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x1_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16"),
-            Some("v1:i0687")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0687"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"),
-            Some("v1:i0688")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x2_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw"),
-            Some("v1:i0688")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0688"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x2_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"),
-            Some("v1:i0689")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x2_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16"),
-            Some("v1:i0689")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0689"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"),
-            Some("v1:i0696")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x32_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw"),
-            Some("v1:i0696")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0696"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x32_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"),
-            Some("v1:i0697")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x32_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16"),
-            Some("v1:i0697")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0697"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"),
-            Some("v1:i0690")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x4_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw"),
-            Some("v1:i0690")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0690"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x4_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"),
-            Some("v1:i0691")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x4_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16"),
-            Some("v1:i0691")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0691"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"),
-            Some("v1:i0698")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x64_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw"),
-            Some("v1:i0698")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0698"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x64_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"),
-            Some("v1:i0699")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x64_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16"),
-            Some("v1:i0699")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0699"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"),
-            Some("v1:i0692")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x8_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw"),
-            Some("v1:i0692")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0692"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x128b_x8_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"),
-            Some("v1:i0693")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x8_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16"),
-            Some("v1:i0693")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0693"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"),
-            Some("v1:i0708")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x16_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw"),
-            Some("v1:i0708")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0708"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x16_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"),
-            Some("v1:i0709")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x16_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16"),
-            Some("v1:i0709")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0709"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"),
-            Some("v1:i0700")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x1_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw"),
-            Some("v1:i0700")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0700"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x1_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"),
-            Some("v1:i0701")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x1_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16"),
-            Some("v1:i0701")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0701"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"),
-            Some("v1:i0702")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x2_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw"),
-            Some("v1:i0702")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0702"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x2_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"),
-            Some("v1:i0703")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x2_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16"),
-            Some("v1:i0703")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0703"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"),
-            Some("v1:i0710")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x32_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw"),
-            Some("v1:i0710")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0710"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x32_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"),
-            Some("v1:i0711")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x32_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16"),
-            Some("v1:i0711")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0711"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"),
-            Some("v1:i0704")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x4_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw"),
-            Some("v1:i0704")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0704"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x4_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"),
-            Some("v1:i0705")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x4_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16"),
-            Some("v1:i0705")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0705"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"),
-            Some("v1:i0706")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x8_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw"),
-            Some("v1:i0706")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0706"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x256b_x8_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"),
-            Some("v1:i0707")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x8_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16"),
-            Some("v1:i0707")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0707"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"),
-            Some("v1:i0758")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x128_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw"),
-            Some("v1:i0758")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0758"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x128_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"),
-            Some("v1:i0759")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x128_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16"),
-            Some("v1:i0759")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0759"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"),
-            Some("v1:i0752")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x16_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw"),
-            Some("v1:i0752")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0752"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x16_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"),
-            Some("v1:i0753")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x16_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16"),
-            Some("v1:i0753")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0753"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"),
-            Some("v1:i0744")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x1_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw"),
-            Some("v1:i0744")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0744"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x1_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"),
-            Some("v1:i0745")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x1_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16"),
-            Some("v1:i0745")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0745"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"),
-            Some("v1:i0746")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x2_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw"),
-            Some("v1:i0746")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0746"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x2_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"),
-            Some("v1:i0747")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x2_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16"),
-            Some("v1:i0747")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0747"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"),
-            Some("v1:i0754")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x32_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw"),
-            Some("v1:i0754")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0754"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x32_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"),
-            Some("v1:i0755")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x32_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16"),
-            Some("v1:i0755")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0755"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"),
-            Some("v1:i0748")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x4_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw"),
-            Some("v1:i0748")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0748"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x4_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"),
-            Some("v1:i0749")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x4_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16"),
-            Some("v1:i0749")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0749"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"),
-            Some("v1:i0756")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x64_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw"),
-            Some("v1:i0756")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0756"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x64_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"),
-            Some("v1:i0757")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x64_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16"),
-            Some("v1:i0757")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0757"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"),
-            Some("v1:i0750")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x8_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw"),
-            Some("v1:i0750")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0750"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x32bx2_x8_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"),
-            Some("v1:i0751")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x8_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16"),
-            Some("v1:i0751")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0751"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"),
-            Some("v1:i0684")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x128_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw"),
-            Some("v1:i0684")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0684"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x128_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"),
-            Some("v1:i0685")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x128_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16"),
-            Some("v1:i0685")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0685"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"),
-            Some("v1:i0678")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x16_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw"),
-            Some("v1:i0678")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0678"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x16_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"),
-            Some("v1:i0679")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x16_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16"),
-            Some("v1:i0679")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0679"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"),
-            Some("v1:i0670")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x1_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw"),
-            Some("v1:i0670")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0670"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x1_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"),
-            Some("v1:i0671")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x1_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16"),
-            Some("v1:i0671")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0671"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"),
-            Some("v1:i0672")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x2_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw"),
-            Some("v1:i0672")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0672"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x2_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"),
-            Some("v1:i0673")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x2_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16"),
-            Some("v1:i0673")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0673"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"),
-            Some("v1:i0680")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x32_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw"),
-            Some("v1:i0680")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0680"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x32_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"),
-            Some("v1:i0681")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x32_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16"),
-            Some("v1:i0681")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0681"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"),
-            Some("v1:i0674")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x4_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw"),
-            Some("v1:i0674")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0674"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x4_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"),
-            Some("v1:i0675")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x4_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16"),
-            Some("v1:i0675")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0675"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"),
-            Some("v1:i0682")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x64_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw"),
-            Some("v1:i0682")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0682"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x64_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"),
-            Some("v1:i0683")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x64_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16"),
-            Some("v1:i0683")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0683"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"),
-            Some("v1:i0676")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x8_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw"),
-            Some("v1:i0676")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0676"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_16x64b_x8_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"),
-            Some("v1:i0677")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x8_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16"),
-            Some("v1:i0677")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0677"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"),
-            Some("v1:i0726")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x128_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw"),
-            Some("v1:i0726")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0726"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x128_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"),
-            Some("v1:i0727")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x128_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16"),
-            Some("v1:i0727")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0727"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"),
-            Some("v1:i0720")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x16_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw"),
-            Some("v1:i0720")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0720"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x16_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"),
-            Some("v1:i0721")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x16_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16"),
-            Some("v1:i0721")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0721"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"),
-            Some("v1:i0712")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x1_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw"),
-            Some("v1:i0712")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0712"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x1_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"),
-            Some("v1:i0713")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x1_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16"),
-            Some("v1:i0713")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0713"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"),
-            Some("v1:i0714")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x2_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw"),
-            Some("v1:i0714")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0714"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x2_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"),
-            Some("v1:i0715")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x2_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16"),
-            Some("v1:i0715")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0715"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"),
-            Some("v1:i0722")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x32_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw"),
-            Some("v1:i0722")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0722"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x32_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"),
-            Some("v1:i0723")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x32_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16"),
-            Some("v1:i0723")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0723"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"),
-            Some("v1:i0716")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x4_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw"),
-            Some("v1:i0716")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0716"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x4_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"),
-            Some("v1:i0717")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x4_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16"),
-            Some("v1:i0717")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0717"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"),
-            Some("v1:i0724")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x64_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw"),
-            Some("v1:i0724")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0724"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x64_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"),
-            Some("v1:i0725")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x64_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16"),
-            Some("v1:i0725")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0725"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"),
-            Some("v1:i0718")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x8_raw"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw"),
-            Some("v1:i0718")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0718"
-        ));
-    }
-    #[test]
-    fn tcgen05_st_32x32b_x8_unpack16_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"),
-            Some("v1:i0719")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x8_unpack16"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16"),
-            Some("v1:i0719")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0719"
-        ));
-    }
-    #[test]
-    fn tcgen05_store_wait_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"),
-            Some("v1:i0358")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tcgen05::tcgen05_store_wait"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_store_wait"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tcgen05::tcgen05_store_wait"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_store_wait"),
-            Some("v1:i0358")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0358"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_box_dim_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"),
-            Some("v1:i0894")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_box_dim"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_box_dim"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_box_dim"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_box_dim"),
-            Some("v1:i0894")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0894"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_element_stride_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"),
-            Some("v1:i0895")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_element_stride"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_element_stride"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_element_stride"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_element_stride"),
-            Some("v1:i0895")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0895"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_element_type_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"),
-            Some("v1:i0896")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_element_type"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_element_type"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_element_type"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_element_type"),
-            Some("v1:i0896")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0896"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_fill_mode_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"),
-            Some("v1:i0897")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_fill_mode"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_fill_mode"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_fill_mode"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_fill_mode"),
-            Some("v1:i0897")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0897"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_global_address_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"),
-            Some("v1:i0898")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_global_address"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_global_address"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_global_address"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_global_address"),
-            Some("v1:i0898")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0898"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_global_dim_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"),
-            Some("v1:i0899")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_global_dim"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_global_dim"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_global_dim"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_global_dim"),
-            Some("v1:i0899")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0899"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_global_stride_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"),
-            Some("v1:i0900")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_global_stride"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_global_stride"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_global_stride"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_global_stride"),
-            Some("v1:i0900")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0900"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_interleave_layout_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"),
-            Some("v1:i0901")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_interleave_layout"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_interleave_layout"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_interleave_layout"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_interleave_layout"),
-            Some("v1:i0901")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0901"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_rank_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"),
-            Some("v1:i0902")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_rank"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_rank"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_rank"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_rank"),
-            Some("v1:i0902")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0902"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_swizzle_atomicity_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"),
-            Some("v1:i0903")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_swizzle_atomicity"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_swizzle_atomicity"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_swizzle_atomicity"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_swizzle_atomicity"),
-            Some("v1:i0903")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0903"
-        ));
-    }
-    #[test]
-    fn tensormap_replace_swizzle_mode_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"),
-            Some("v1:i0904")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::tma::tensormap_replace_swizzle_mode"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_swizzle_mode"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::tma::tensormap_replace_swizzle_mode"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::tma::tensormap_replace_swizzle_mode"),
-            Some("v1:i0904")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0904"
-        ));
-    }
-    #[test]
-    fn thread_idx_x_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"),
-            Some("v1:i0001")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::thread_idx_x"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::threadIdx_x"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::threadIdx_x"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::threadIdx_x"),
-            Some("v1:i0001")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::threadIdx_x"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::threadIdx_x"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::threadIdx_x"),
-            Some("v1:i0001")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0001"
-        ));
-    }
-    #[test]
-    fn thread_idx_y_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"),
-            Some("v1:i0005")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::thread_idx_y"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::threadIdx_y"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::threadIdx_y"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::threadIdx_y"),
-            Some("v1:i0005")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::threadIdx_y"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::threadIdx_y"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::threadIdx_y"),
-            Some("v1:i0005")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0005"
-        ));
-    }
-    #[test]
-    fn thread_idx_z_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"),
-            Some("v1:i0009")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::sreg::thread_idx_z"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::thread::threadIdx_z"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::thread::threadIdx_z"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::thread::threadIdx_z"),
-            Some("v1:i0009")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::threadIdx_z"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::threadIdx_z"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::threadIdx_z"),
-            Some("v1:i0009")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0009"
-        ));
-    }
-    #[test]
-    fn threadfence_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"),
-            Some("v1:i0299")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::fence::threadfence"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::fence::threadfence"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::fence::threadfence"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::fence::threadfence"),
-            Some("v1:i0299")
-        );
-        assert!(is_generated_intrinsic_path("cuda_device::threadfence"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::threadfence"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::threadfence"),
-            Some("v1:i0299")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0299"
-        ));
-    }
-    #[test]
-    fn threadfence_block_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"),
-            Some("v1:i0298")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::fence::threadfence_block"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::fence::threadfence_block"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::fence::threadfence_block"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::fence::threadfence_block"),
-            Some("v1:i0298")
-        );
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::threadfence_block"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::threadfence_block"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::threadfence_block"),
-            Some("v1:i0298")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0298"
-        ));
-    }
-    #[test]
-    fn threadfence_system_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"),
-            Some("v1:i0300")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::fence::threadfence_system"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::fence::threadfence_system"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::fence::threadfence_system"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::fence::threadfence_system"),
-            Some("v1:i0300")
-        );
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::threadfence_system"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::threadfence_system"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::threadfence_system"),
-            Some("v1:i0300")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0300"
-        ));
-    }
-    #[test]
-    fn total_smem_size_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"),
-            Some("v1:i0294")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::shared::total_smem_size"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::shared::total_smem_size"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::shared::total_smem_size"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::shared::total_smem_size"),
-            Some("v1:i0294")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0294"
-        ));
-    }
-    #[test]
-    fn trap_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295"),
-            Some("v1:i0295")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path("cuda_intrinsics::debug::trap"));
-        assert!(is_generated_intrinsic_path("cuda_device::debug::trap"));
-        assert!(!is_raw_generated_intrinsic_path("cuda_device::debug::trap"));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::debug::trap"),
-            Some("v1:i0295")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0295"
-        ));
-    }
-    #[test]
-    fn uni_sync_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043"),
-            Some("v1:i0043")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::uni_sync"
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0043"
-        ));
-    }
-    #[test]
-    fn warpid_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291"),
-            Some("v1:i0291")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::warp::warpid"
-        ));
-        assert!(is_generated_intrinsic_path("cuda_device::warp::warpid"));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::warp::warpid"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::warp::warpid"),
-            Some("v1:i0291")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0291"
-        ));
-    }
-    #[test]
-    fn wgmma_commit_group_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"),
-            Some("v1:i0318")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::wgmma::wgmma_commit_group"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wgmma::wgmma_commit_group"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wgmma::wgmma_commit_group"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wgmma::wgmma_commit_group"),
-            Some("v1:i0318")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0318"
-        ));
-    }
-    #[test]
-    fn wgmma_fence_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"),
-            Some("v1:i0317")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::wgmma::wgmma_fence"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wgmma::wgmma_fence"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wgmma::wgmma_fence"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wgmma::wgmma_fence"),
-            Some("v1:i0317")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0317"
-        ));
-    }
-    #[test]
-    fn wgmma_wait_group_uses_only_canonical_or_compatibility_defpaths() {
-        assert!(is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
-        ));
-        assert!(is_raw_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"),
-            Some("v1:i0319")
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319".into()
-            ),
-            RawIntrinsicIdentity::Known(_)
-        ));
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::wgmma::wgmma_wait_group"
-        ));
-        assert!(is_generated_intrinsic_path(
-            "cuda_device::wgmma::__wgmma_wait_group"
-        ));
-        assert!(!is_raw_generated_intrinsic_path(
-            "cuda_device::wgmma::__wgmma_wait_group"
-        ));
-        assert_eq!(
-            generated_intrinsic_marker("cuda_device::wgmma::__wgmma_wait_group"),
-            Some("v1:i0319")
-        );
-        assert!(!is_generated_intrinsic_path(
-            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0319"
-        ));
-    }
-
-    #[test]
-    fn raw_intrinsic_identity_classification_fails_closed() {
-        assert_eq!(
-            classify_raw_intrinsic_path("serde", "serde::helper".into()),
-            RawIntrinsicIdentity::NotRawCrate
-        );
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0001".into()
-            ),
-            RawIntrinsicIdentity::UnsupportedAbi(_)
-        ));
-        assert!(matches!(
-            classify_raw_intrinsic_path(
-                "cuda_intrinsics",
-                "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i9999".into()
-            ),
-            RawIntrinsicIdentity::UnknownId(_)
-        ));
-        assert!(matches!(
-            classify_raw_intrinsic_path("cuda_intrinsics", "cuda_intrinsics::helper".into()),
-            RawIntrinsicIdentity::UnknownId(_)
-        ));
-    }
-}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs
new file mode 100644
index 0000000000..7b091e4dca
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs
@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `active_mask` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::ActiveMaskOp;
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    _body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
+        | "cuda_device::warp::active_mask" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let active_mask = ActiveMaskOp::build(ctx);
+            active_mask.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, active_mask, "v1:i0044");
+            helpers::insert_op(ctx, active_mask, block_ptr, prev_op);
+            let result = active_mask.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                active_mask,
+                value_map,
+                block_map,
+                loc,
+                "active_mask call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs
new file mode 100644
index 0000000000..630f6be22c
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs
@@ -0,0 +1,354 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `clc` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    ClcQueryGetFirstCtaidXOp, ClcQueryGetFirstCtaidYOp, ClcQueryGetFirstCtaidZOp,
+    ClcQueryIsCanceledOp, ClcTryCancelMulticastOp, ClcTryCancelOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
+        | "cuda_device::clc::clc_query_get_first_ctaid_x" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                ClcQueryGetFirstCtaidXOp::get_concrete_op_info(),
+                vec![
+                    pliron::builtin::types::IntegerType::get(
+                        ctx,
+                        32,
+                        pliron::builtin::types::Signedness::Unsigned,
+                    )
+                    .into(),
+                ],
+                vec![arg0, arg1],
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0325");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "clc_query_get_first_ctaid_x call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
+        | "cuda_device::clc::clc_query_get_first_ctaid_y" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                ClcQueryGetFirstCtaidYOp::get_concrete_op_info(),
+                vec![
+                    pliron::builtin::types::IntegerType::get(
+                        ctx,
+                        32,
+                        pliron::builtin::types::Signedness::Unsigned,
+                    )
+                    .into(),
+                ],
+                vec![arg0, arg1],
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0326");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "clc_query_get_first_ctaid_y call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
+        | "cuda_device::clc::clc_query_get_first_ctaid_z" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                ClcQueryGetFirstCtaidZOp::get_concrete_op_info(),
+                vec![
+                    pliron::builtin::types::IntegerType::get(
+                        ctx,
+                        32,
+                        pliron::builtin::types::Signedness::Unsigned,
+                    )
+                    .into(),
+                ],
+                vec![arg0, arg1],
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0327");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "clc_query_get_first_ctaid_z call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
+        | "cuda_device::clc::clc_query_is_canceled" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                ClcQueryIsCanceledOp::get_concrete_op_info(),
+                vec![
+                    pliron::builtin::types::IntegerType::get(
+                        ctx,
+                        32,
+                        pliron::builtin::types::Signedness::Unsigned,
+                    )
+                    .into(),
+                ],
+                vec![arg0, arg1],
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0324");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "clc_query_is_canceled call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
+        | "cuda_device::clc::clc_try_cancel" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                ClcTryCancelOp::get_concrete_op_info(),
+                vec![],
+                vec![arg0, arg1],
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0322");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "clc_try_cancel call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
+        | "cuda_device::clc::clc_try_cancel_multicast" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                ClcTryCancelMulticastOp::get_concrete_op_info(),
+                vec![],
+                vec![arg0, arg1],
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0323");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "clc_try_cancel_multicast call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs
new file mode 100644
index 0000000000..adf200add5
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs
@@ -0,0 +1,213 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `cluster_barrier` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{ClusterBarrierModeAttr, ClusterBarrierOp};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    _body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    _value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_device::cluster::cluster_sync" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let arrive = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::ArriveAligned);
+            arrive.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, arrive, "v1:i0278");
+            helpers::insert_op(ctx, arrive, block_ptr, prev_op);
+            let wait = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::WaitAligned);
+            wait.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, wait, "v1:i0282");
+            helpers::insert_op(ctx, wait, block_ptr, Some(arrive));
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    wait,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cluster_sync call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
+        | "cuda_device::cluster::barrier_cluster_arrive" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let barrier = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::Arrive);
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0277");
+            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "barrier_cluster_arrive call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
+        | "cuda_device::cluster::barrier_cluster_arrive_aligned" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let barrier = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::ArriveAligned);
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0278");
+            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "barrier_cluster_arrive_aligned call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
+        | "cuda_device::cluster::barrier_cluster_arrive_relaxed" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let barrier = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::ArriveRelaxed);
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0279");
+            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "barrier_cluster_arrive_relaxed call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
+        | "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let barrier =
+                ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::ArriveRelaxedAligned);
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0280");
+            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "barrier_cluster_arrive_relaxed_aligned call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
+        | "cuda_device::cluster::barrier_cluster_wait" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let barrier = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::Wait);
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0281");
+            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "barrier_cluster_wait call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
+        | "cuda_device::cluster::barrier_cluster_wait_aligned" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let barrier = ClusterBarrierOp::build(ctx, ClusterBarrierModeAttr::WaitAligned);
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0282");
+            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "barrier_cluster_wait_aligned call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs
new file mode 100644
index 0000000000..d848958bf8
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs
@@ -0,0 +1,118 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `cluster_memory` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{DsmemReadU32Op, MapaSharedClusterOp};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
+        | "cuda_device::cluster::dsmem_read_u32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (source, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (rank, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let cluster = DsmemReadU32Op::build(ctx, source, rank);
+            cluster.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, cluster, "v1:i0321");
+            helpers::insert_op(ctx, cluster, block_ptr, last_op);
+            let result = cluster.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                cluster,
+                value_map,
+                block_map,
+                loc,
+                "dsmem_read_u32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
+        | "cuda_device::cluster::map_shared_rank"
+        | "cuda_device::cluster::map_shared_rank_mut" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (source, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (rank, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let cluster = MapaSharedClusterOp::build(ctx, source, rank);
+            cluster.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, cluster, "v1:i0320");
+            helpers::insert_op(ctx, cluster, block_ptr, last_op);
+            let result = cluster.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                cluster,
+                value_map,
+                block_map,
+                loc,
+                "map_shared_rank call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs
new file mode 100644
index 0000000000..4d37f11111
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs
@@ -0,0 +1,642 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `cp_async` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    CpAsyncCa4Op, CpAsyncCa8Op, CpAsyncCa16Op, CpAsyncCaZfill4Op, CpAsyncCaZfill8Op,
+    CpAsyncCaZfill16Op, CpAsyncCg16Op, CpAsyncCgZfill16Op, CpAsyncCommitGroupOp,
+    CpAsyncMbarrierArriveNoIncOp, CpAsyncMbarrierArriveNoIncSharedOp, CpAsyncMbarrierArriveOp,
+    CpAsyncMbarrierArriveSharedOp, CpAsyncWaitAllOp, CpAsyncWaitGroupOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
+        | "cuda_device::async_copy::cp_async_ca_16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (shared_dst, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (global_src, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let copy = CpAsyncCa16Op::build(ctx, shared_dst, global_src);
+            copy.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0090");
+            helpers::insert_op(ctx, copy, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    copy,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_ca_16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
+        | "cuda_device::async_copy::cp_async_ca_4" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (shared_dst, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (global_src, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let copy = CpAsyncCa4Op::build(ctx, shared_dst, global_src);
+            copy.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0086");
+            helpers::insert_op(ctx, copy, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    copy,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_ca_4 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
+        | "cuda_device::async_copy::cp_async_ca_8" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (shared_dst, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (global_src, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let copy = CpAsyncCa8Op::build(ctx, shared_dst, global_src);
+            copy.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0088");
+            helpers::insert_op(ctx, copy, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    copy,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_ca_8 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
+        | "cuda_device::async_copy::cp_async_ca_zfill_16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (shared_dst, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (global_src, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (source_size, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let copy = CpAsyncCaZfill16Op::build(ctx, shared_dst, global_src, source_size);
+            copy.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0091");
+            helpers::insert_op(ctx, copy, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    copy,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_ca_zfill_16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
+        | "cuda_device::async_copy::cp_async_ca_zfill_4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (shared_dst, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (global_src, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (source_size, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let copy = CpAsyncCaZfill4Op::build(ctx, shared_dst, global_src, source_size);
+            copy.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0087");
+            helpers::insert_op(ctx, copy, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    copy,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_ca_zfill_4 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
+        | "cuda_device::async_copy::cp_async_ca_zfill_8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (shared_dst, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (global_src, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (source_size, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let copy = CpAsyncCaZfill8Op::build(ctx, shared_dst, global_src, source_size);
+            copy.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0089");
+            helpers::insert_op(ctx, copy, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    copy,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_ca_zfill_8 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
+        | "cuda_device::async_copy::cp_async_cg_16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (shared_dst, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (global_src, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let copy = CpAsyncCg16Op::build(ctx, shared_dst, global_src);
+            copy.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0092");
+            helpers::insert_op(ctx, copy, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    copy,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_cg_16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
+        | "cuda_device::async_copy::cp_async_cg_zfill_16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (shared_dst, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (global_src, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (source_size, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let copy = CpAsyncCgZfill16Op::build(ctx, shared_dst, global_src, source_size);
+            copy.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, copy, "v1:i0093");
+            helpers::insert_op(ctx, copy, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    copy,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_cg_zfill_16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
+        | "cuda_device::async_copy::cp_async_commit_group" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let last_op = prev_op;
+            let control = CpAsyncCommitGroupOp::build(ctx);
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0094");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_commit_group call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
+        | "cuda_device::async_copy::cp_async_wait_all" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let last_op = prev_op;
+            let control = CpAsyncWaitAllOp::build(ctx);
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0095");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_wait_all call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
+        | "cuda_device::async_copy::cp_async_wait_group" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            if !matches!(&args[0], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_wait_group requires a compile-time constant max_pending value"
+                            .to_owned()
+                    )
+                );
+            }
+            let (max_pending, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let control = CpAsyncWaitGroupOp::build(ctx, max_pending);
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0096");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_wait_group call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
+        | "cuda_device::async_copy::cp_async_mbarrier_arrive" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let bridge = CpAsyncMbarrierArriveOp::build(ctx, barrier);
+            bridge.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, bridge, "v1:i0101");
+            helpers::insert_op(ctx, bridge, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    bridge,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_mbarrier_arrive call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
+        | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let bridge = CpAsyncMbarrierArriveNoIncOp::build(ctx, barrier);
+            bridge.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, bridge, "v1:i0103");
+            helpers::insert_op(ctx, bridge, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    bridge,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_mbarrier_arrive_noinc call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
+        | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let bridge = CpAsyncMbarrierArriveNoIncSharedOp::build(ctx, barrier);
+            bridge.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, bridge, "v1:i0104");
+            helpers::insert_op(ctx, bridge, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    bridge,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_mbarrier_arrive_noinc_shared call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
+        | "cuda_device::async_copy::cp_async_mbarrier_arrive_shared" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let bridge = CpAsyncMbarrierArriveSharedOp::build(ctx, barrier);
+            bridge.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, bridge, "v1:i0102");
+            helpers::insert_op(ctx, bridge, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    bridge,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_mbarrier_arrive_shared call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs
new file mode 100644
index 0000000000..c3c9ca33d2
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs
@@ -0,0 +1,138 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `debug_control` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_mir::ops::{MirConstantOp, MirUnreachableOp};
+use dialect_nvvm::ops::{BreakpointOp, PmEventOp, TrapOp};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
+        | "cuda_device::debug::breakpoint" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let debug = BreakpointOp::build(ctx);
+            debug.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, debug, "v1:i0296");
+            helpers::insert_op(ctx, debug, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    debug,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported("breakpoint call without target block".to_owned())
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
+        | "cuda_device::debug::__prof_trigger" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            if !matches!(&args[0], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "prof_trigger requires a compile-time constant event ID in 0..=15"
+                            .to_owned()
+                    )
+                );
+            }
+            let (event_id_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let event_id = event_id_value
+                .defining_op()
+                .and_then(|defining_op| Operation::get_op::<MirConstantOp>(defining_op, ctx))
+                .and_then(|constant| constant.get_attr_value(ctx))
+                .map(|value| value.value().to_u64())
+                .and_then(|value| u32::try_from(value).ok())
+                .filter(|value| *value <= 15);
+            let Some(event_id) = event_id else {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "prof_trigger requires a compile-time constant event ID in 0..=15"
+                            .to_owned()
+                    )
+                );
+            };
+            let debug = PmEventOp::build(ctx, event_id);
+            debug.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, debug, "v1:i0297");
+            helpers::insert_op(ctx, debug, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    debug,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported("pmevent call without target block".to_owned())
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295" | "cuda_device::debug::trap" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let debug = TrapOp::build(ctx);
+            debug.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, debug, "v1:i0295");
+            helpers::insert_op(ctx, debug, block_ptr, prev_op);
+            let unreachable = Operation::new(
+                ctx,
+                MirUnreachableOp::get_concrete_op_info(),
+                vec![],
+                vec![],
+                vec![],
+                0,
+            );
+            unreachable.deref_mut(ctx).set_loc(loc);
+            helpers::insert_op(ctx, unreachable, block_ptr, Some(debug));
+            Ok(Some(unreachable))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs
new file mode 100644
index 0000000000..1e4e0768bb
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs
@@ -0,0 +1,231 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `dotprod` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{Dp2aS32Op, Dp2aU32Op, Dp4aS32Op, Dp4aU32Op};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
+        | "cuda_device::dotprod::dp2a_s32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (c, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let dot = Dp2aS32Op::build(ctx, a, b, c);
+            dot.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, dot, "v1:i0032");
+            helpers::insert_op(ctx, dot, block_ptr, last_op);
+            let result = dot.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                dot,
+                value_map,
+                block_map,
+                loc,
+                "dp2a_s32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
+        | "cuda_device::dotprod::dp2a_u32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (c, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let dot = Dp2aU32Op::build(ctx, a, b, c);
+            dot.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, dot, "v1:i0033");
+            helpers::insert_op(ctx, dot, block_ptr, last_op);
+            let result = dot.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                dot,
+                value_map,
+                block_map,
+                loc,
+                "dp2a_u32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
+        | "cuda_device::dotprod::dp4a_s32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (c, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let dot = Dp4aS32Op::build(ctx, a, b, c);
+            dot.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, dot, "v1:i0030");
+            helpers::insert_op(ctx, dot, block_ptr, last_op);
+            let result = dot.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                dot,
+                value_map,
+                block_map,
+                loc,
+                "dp4a_s32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
+        | "cuda_device::dotprod::dp4a_u32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (c, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let dot = Dp4aU32Op::build(ctx, a, b, c);
+            dot.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, dot, "v1:i0031");
+            helpers::insert_op(ctx, dot, block_ptr, last_op);
+            let result = dot.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                dot,
+                value_map,
+                block_map,
+                loc,
+                "dp4a_u32 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs
new file mode 100644
index 0000000000..c562481c51
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs
@@ -0,0 +1,111 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `elect` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_mir::{ops::MirConstructTupleOp, types::MirTupleType};
+use dialect_nvvm::ops::ElectSyncOp;
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
+        | "cuda_device::warp::elect_sync" => {
+            require_arity(name, args.len(), 1, &loc)?;
+
+            let tuple_ty =
+                crate::translator::types::translate_destination_type(ctx, body, destination, &loc)?;
+            let (leader_ty, elected_ty) = {
+                let ty = tuple_ty.deref(ctx);
+                match ty.downcast_ref::<MirTupleType>() {
+                    Some(tuple) if tuple.get_types().len() == 2 => {
+                        (tuple.get_types()[0], tuple.get_types()[1])
+                    }
+                    _ => {
+                        return input_err!(
+                            loc.clone(),
+                            TranslationErr::unsupported(
+                                "warp::elect_sync destination must be a (u32, bool) tuple"
+                                    .to_owned()
+                            )
+                        );
+                    }
+                }
+            };
+            let (mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let elect = Operation::new(
+                ctx,
+                ElectSyncOp::get_concrete_op_info(),
+                vec![leader_ty, elected_ty],
+                vec![mask],
+                vec![],
+                0,
+            );
+            elect.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, elect, "v1:i0367");
+            helpers::insert_op(ctx, elect, block_ptr, last_op);
+            let leader = elect.deref(ctx).get_result(0);
+            let elected = elect.deref(ctx).get_result(1);
+            let tuple = Operation::new(
+                ctx,
+                MirConstructTupleOp::get_concrete_op_info(),
+                vec![tuple_ty],
+                vec![leader, elected],
+                vec![],
+                0,
+            );
+            tuple.deref_mut(ctx).set_loc(loc.clone());
+            tuple.insert_after(ctx, elect);
+            let result = tuple.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                tuple,
+                value_map,
+                block_map,
+                loc,
+                "elect_sync call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs
new file mode 100644
index 0000000000..6c6417b711
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs
@@ -0,0 +1,406 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `execution_control` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_mir::ops::MirConstantOp;
+use dialect_nvvm::ops::{
+    BarrierCtaArriveAlignedCountOp, BarrierCtaArriveCountOp, BarrierCtaSyncAlignedCountOp,
+    BarrierCtaSyncCountOp, GridDependencyLaunchDependentsOp, GridDependencyWaitOp, SetMaxNRegDecOp,
+    SetMaxNRegIncOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
+        | "cuda_device::barrier::barrier_cta_arrive" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let control = Operation::new(
+                ctx,
+                BarrierCtaArriveCountOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0885");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "barrier_cta_arrive call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
+        | "cuda_device::barrier::barrier_cta_arrive_aligned" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let control = Operation::new(
+                ctx,
+                BarrierCtaArriveAlignedCountOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0886");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "barrier_cta_arrive_aligned call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
+        | "cuda_device::barrier::barrier_cta_sync" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let control = Operation::new(
+                ctx,
+                BarrierCtaSyncCountOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0883");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "barrier_cta_sync call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
+        | "cuda_device::barrier::barrier_cta_sync_aligned" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let control = Operation::new(
+                ctx,
+                BarrierCtaSyncAlignedCountOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0884");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "barrier_cta_sync_aligned call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
+        | "cuda_device::grid::dependency::trigger_dependents" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let last_op = prev_op;
+            let control = Operation::new(
+                ctx,
+                GridDependencyLaunchDependentsOp::get_concrete_op_info(),
+                vec![],
+                vec![],
+                vec![],
+                0,
+            );
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0913");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "grid_dependency_launch_dependents call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
+        | "cuda_device::grid::dependency::wait" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let last_op = prev_op;
+            let control = Operation::new(
+                ctx,
+                GridDependencyWaitOp::get_concrete_op_info(),
+                vec![],
+                vec![],
+                vec![],
+                0,
+            );
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0914");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "grid_dependency_wait call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
+        | "cuda_device::thread::__setmaxnreg_dec" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            if !matches!(&args[0], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "setmaxnreg requires a compile-time register count in 24..=256 divisible by 8".to_owned()
+                    )
+                );
+            }
+            let (register_count_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let register_count = register_count_value
+                .defining_op()
+                .and_then(|defining_op| Operation::get_op::<MirConstantOp>(defining_op, ctx))
+                .and_then(|constant| constant.get_attr_value(ctx))
+                .map(|value| value.value().to_u64())
+                .and_then(|value| u32::try_from(value).ok())
+                .filter(|value| (24..=256).contains(value) && value % 8 == 0);
+            let Some(register_count) = register_count else {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "setmaxnreg requires a compile-time register count in 24..=256 divisible by 8".to_owned()
+                    )
+                );
+            };
+            let control = SetMaxNRegDecOp::build(ctx, register_count);
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0916");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "setmaxnreg_dec call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
+        | "cuda_device::thread::__setmaxnreg_inc" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            if !matches!(&args[0], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "setmaxnreg requires a compile-time register count in 24..=256 divisible by 8".to_owned()
+                    )
+                );
+            }
+            let (register_count_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let register_count = register_count_value
+                .defining_op()
+                .and_then(|defining_op| Operation::get_op::<MirConstantOp>(defining_op, ctx))
+                .and_then(|constant| constant.get_attr_value(ctx))
+                .map(|value| value.value().to_u64())
+                .and_then(|value| u32::try_from(value).ok())
+                .filter(|value| (24..=256).contains(value) && value % 8 == 0);
+            let Some(register_count) = register_count else {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "setmaxnreg requires a compile-time register count in 24..=256 divisible by 8".to_owned()
+                    )
+                );
+            };
+            let control = SetMaxNRegIncOp::build(ctx, register_count);
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0915");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "setmaxnreg_inc call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs
new file mode 100644
index 0000000000..1cf983f8ee
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs
@@ -0,0 +1,2534 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `extended_minmax` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    ExtendedMinMaxFormatAttr, ExtendedMinMaxNanAttr, ExtendedMinMaxOp, ExtendedMinMaxOperationAttr,
+    ExtendedMinMaxSubnormalAttr, ExtendedMinMaxXorSignAbsAttr,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850" | "cuda_device::bf16::max_bf16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0850");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_bf16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842" | "cuda_device::f16::max_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0842");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
+        | "cuda_device::f16::max_ftz_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0843");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_ftz_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
+        | "cuda_device::f16x2::max_ftz_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0564");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_ftz_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
+        | "cuda_device::f16::max_ftz_nan_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0845");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_ftz_nan_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
+        | "cuda_device::f16x2::max_ftz_nan_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0565");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_ftz_nan_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
+        | "cuda_device::f16::max_ftz_nan_xorsign_abs_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0849");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_ftz_nan_xorsign_abs_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
+        | "cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0567");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_ftz_nan_xorsign_abs_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
+        | "cuda_device::float::max_ftz_nan_xorsign_abs_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F32,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0566");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_ftz_nan_xorsign_abs_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
+        | "cuda_device::f16::max_ftz_xorsign_abs_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0847");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_ftz_xorsign_abs_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
+        | "cuda_device::f16x2::max_ftz_xorsign_abs_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0569");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_ftz_xorsign_abs_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
+        | "cuda_device::float::max_ftz_xorsign_abs_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F32,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0568");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_ftz_xorsign_abs_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
+        | "cuda_device::bf16::max_nan_bf16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0851");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_nan_bf16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
+        | "cuda_device::bf16x2::max_nan_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16x2,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0570");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_nan_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
+        | "cuda_device::f16::max_nan_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0844");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_nan_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
+        | "cuda_device::f16x2::max_nan_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0571");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_nan_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
+        | "cuda_device::bf16::max_nan_xorsign_abs_bf16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0853");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_nan_xorsign_abs_bf16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
+        | "cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16x2,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0572");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_nan_xorsign_abs_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
+        | "cuda_device::f16::max_nan_xorsign_abs_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0848");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_nan_xorsign_abs_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
+        | "cuda_device::f16x2::max_nan_xorsign_abs_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0574");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_nan_xorsign_abs_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
+        | "cuda_device::float::max_nan_xorsign_abs_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F32,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0573");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_nan_xorsign_abs_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
+        | "cuda_device::bf16::max_xorsign_abs_bf16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0852");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_xorsign_abs_bf16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
+        | "cuda_device::bf16x2::max_xorsign_abs_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16x2,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0575");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_xorsign_abs_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
+        | "cuda_device::f16::max_xorsign_abs_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0846");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_xorsign_abs_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
+        | "cuda_device::f16x2::max_xorsign_abs_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0577");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_xorsign_abs_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
+        | "cuda_device::float::max_xorsign_abs_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F32,
+                ExtendedMinMaxOperationAttr::Max,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0576");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_xorsign_abs_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838" | "cuda_device::bf16::min_bf16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0838");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_bf16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830" | "cuda_device::f16::min_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0830");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
+        | "cuda_device::f16::min_ftz_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0831");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_ftz_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
+        | "cuda_device::f16x2::min_ftz_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0550");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_ftz_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
+        | "cuda_device::f16::min_ftz_nan_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0833");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_ftz_nan_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
+        | "cuda_device::f16x2::min_ftz_nan_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0551");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_ftz_nan_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
+        | "cuda_device::f16::min_ftz_nan_xorsign_abs_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0837");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_ftz_nan_xorsign_abs_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
+        | "cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0553");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_ftz_nan_xorsign_abs_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
+        | "cuda_device::float::min_ftz_nan_xorsign_abs_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F32,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0552");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_ftz_nan_xorsign_abs_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
+        | "cuda_device::f16::min_ftz_xorsign_abs_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0835");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_ftz_xorsign_abs_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
+        | "cuda_device::f16x2::min_ftz_xorsign_abs_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0555");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_ftz_xorsign_abs_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
+        | "cuda_device::float::min_ftz_xorsign_abs_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F32,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Ftz,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0554");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_ftz_xorsign_abs_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
+        | "cuda_device::bf16::min_nan_bf16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0839");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_nan_bf16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
+        | "cuda_device::bf16x2::min_nan_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16x2,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0556");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_nan_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
+        | "cuda_device::f16::min_nan_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0832");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_nan_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
+        | "cuda_device::f16x2::min_nan_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Disabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0557");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_nan_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
+        | "cuda_device::bf16::min_nan_xorsign_abs_bf16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0841");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_nan_xorsign_abs_bf16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
+        | "cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16x2,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0558");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_nan_xorsign_abs_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
+        | "cuda_device::f16::min_nan_xorsign_abs_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0836");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_nan_xorsign_abs_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
+        | "cuda_device::f16x2::min_nan_xorsign_abs_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0560");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_nan_xorsign_abs_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
+        | "cuda_device::float::min_nan_xorsign_abs_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F32,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Nan,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0559");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_nan_xorsign_abs_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
+        | "cuda_device::bf16::min_xorsign_abs_bf16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0840");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_xorsign_abs_bf16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
+        | "cuda_device::bf16x2::min_xorsign_abs_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::Bf16x2,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0561");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_xorsign_abs_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
+        | "cuda_device::f16::min_xorsign_abs_f16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0834");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_xorsign_abs_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
+        | "cuda_device::f16x2::min_xorsign_abs_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F16x2,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0563");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_xorsign_abs_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
+        | "cuda_device::float::min_xorsign_abs_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (a, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (b, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ExtendedMinMaxOp::build(
+                ctx,
+                a,
+                b,
+                ExtendedMinMaxFormatAttr::F32,
+                ExtendedMinMaxOperationAttr::Min,
+                ExtendedMinMaxSubnormalAttr::Preserve,
+                ExtendedMinMaxNanAttr::Number,
+                ExtendedMinMaxXorSignAbsAttr::Enabled,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0562");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_xorsign_abs_f32 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs
new file mode 100644
index 0000000000..9fc89544ff
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs
@@ -0,0 +1,445 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Shared glue for the generated intrinsic dispatch shards.
+
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_mir::{
+    attributes::FieldIndexAttr,
+    ops::{MirConstantOp, MirConstructArrayOp, MirExtractFieldOp},
+    types::{MirArrayType, MirStructType},
+};
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{FP32Type, FP64Type, IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+use rustc_public::mir;
+
+pub(super) fn require_arity(
+    name: &str,
+    actual: usize,
+    expected: usize,
+    loc: &Location,
+) -> TranslationResult<()> {
+    if actual != expected {
+        return input_err!(
+            loc.clone(),
+            TranslationErr::unsupported(format!(
+                "generated intrinsic `{name}` expects {expected} arguments, got {actual}"
+            ))
+        );
+    }
+    Ok(())
+}
+
+pub(super) fn generated_tcgen05_mma_selector(operand: Option<&mir::Operand>) -> Option<u32> {
+    use rustc_public::ty::{ConstantKind, TyConstKind};
+    let mir::Operand::Constant(constant) = operand? else {
+        return None;
+    };
+    let value: u128 = match constant.const_.kind() {
+        ConstantKind::Allocated(alloc) => alloc.read_uint().ok()?,
+        ConstantKind::Ty(value) => match value.kind() {
+            TyConstKind::Value(_, alloc) => alloc.read_uint().ok()?,
+            _ => value.eval_target_usize().ok()? as u128,
+        },
+        ConstantKind::Unevaluated(_) | ConstantKind::Param(_) => return None,
+        ConstantKind::ZeroSized => return None,
+    };
+    u32::try_from(value).ok()
+}
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn import_generated_tcgen05_store_operands(
+    ctx: &mut Context,
+    body: &mir::Body,
+    args: &[mir::Operand],
+    expected_len: usize,
+    has_half_split_offset: bool,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    loc: Location,
+) -> TranslationResult<(Vec<Value>, Option<Ptr<Operation>>)> {
+    let expected_arity = if has_half_split_offset { 3 } else { 2 };
+    if args.len() != expected_arity || !(1..=128).contains(&expected_len) {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(
+                "generated tcgen05 store has an invalid address, offset, or register count"
+                    .to_owned()
+            )
+        );
+    }
+    let u32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+    let (address, last_op) = rvalue::translate_operand(
+        ctx,
+        body,
+        &args[0],
+        value_map,
+        block_ptr,
+        prev_op,
+        loc.clone(),
+    )?;
+    let (half_split_offset, last_op) = if has_half_split_offset {
+        let (offset, translated) = rvalue::translate_operand(
+            ctx,
+            body,
+            &args[1],
+            value_map,
+            block_ptr,
+            last_op,
+            loc.clone(),
+        )?;
+        if offset
+            .defining_op()
+            .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+            .is_none()
+        {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(
+                    "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                )
+            );
+        }
+        (Some(offset), translated)
+    } else {
+        (None, last_op)
+    };
+    let data_index = if has_half_split_offset { 2 } else { 1 };
+    let (data, mut last_op) = rvalue::translate_operand(
+        ctx,
+        body,
+        &args[data_index],
+        value_map,
+        block_ptr,
+        last_op,
+        loc.clone(),
+    )?;
+    if expected_len == 1 {
+        if data.get_type(ctx) != u32_ty {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(
+                    "generated tcgen05 store data must be a u32 register".to_owned()
+                )
+            );
+        }
+        let mut operands = vec![address];
+        operands.extend(half_split_offset);
+        operands.push(data);
+        return Ok((operands, last_op));
+    }
+
+    let data_ty = data.get_type(ctx);
+    let direct_array = data_ty
+        .deref(ctx)
+        .downcast_ref::<MirArrayType>()
+        .is_some_and(|array| array.size() == expected_len as u64 && array.element_type() == u32_ty);
+    let array = if direct_array {
+        data
+    } else {
+        let wrapped_array_ty = data_ty
+            .deref(ctx)
+            .downcast_ref::<MirStructType>()
+            .filter(|structure| structure.field_count() == 1)
+            .and_then(|structure| structure.get_field_type(0));
+        let valid_wrapper = wrapped_array_ty.is_some_and(|field_ty| {
+            field_ty
+                .deref(ctx)
+                .downcast_ref::<MirArrayType>()
+                .is_some_and(|array| {
+                    array.size() == expected_len as u64 && array.element_type() == u32_ty
+                })
+        });
+        if !valid_wrapper {
+            return input_err!(
+                loc,
+                TranslationErr::unsupported(format!(
+                    "generated tcgen05 store data must contain {expected_len} u32 registers"
+                ))
+            );
+        }
+        let array_ty = wrapped_array_ty.expect("validated tcgen05 store wrapper");
+        let extract = Operation::new(
+            ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![array_ty],
+            vec![data],
+            vec![],
+            0,
+        );
+        extract.deref_mut(ctx).set_loc(loc.clone());
+        let extract = MirExtractFieldOp::new(extract);
+        extract.set_attr_index(ctx, FieldIndexAttr(0));
+        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
+        last_op = Some(extract.get_operation());
+        extract.get_operation().deref(ctx).get_result(0)
+    };
+
+    let mut operands = Vec::with_capacity(expected_len + 1 + usize::from(has_half_split_offset));
+    operands.push(address);
+    operands.extend(half_split_offset);
+    for index in 0..expected_len {
+        let extract = Operation::new(
+            ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![u32_ty],
+            vec![array],
+            vec![],
+            0,
+        );
+        extract.deref_mut(ctx).set_loc(loc.clone());
+        let extract = MirExtractFieldOp::new(extract);
+        extract.set_attr_index(ctx, FieldIndexAttr(index as u32));
+        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
+        last_op = Some(extract.get_operation());
+        operands.push(extract.get_operation().deref(ctx).get_result(0));
+    }
+    Ok((operands, last_op))
+}
+
+#[derive(Clone, Copy)]
+pub(super) enum GeneratedMmaImportAdapter {
+    C2U32A2U32B1U32ToD2U32,
+    C2U32A4U32B2U32ToD2U32,
+    C2U32A4U32B4U32ToD2U32,
+    C4F32A2U32B1U32ToD4F32,
+    C4F32A4U32B2U32ToD4F32,
+    C4F32A4U32B4U32ToD4F32,
+    C2F64A1F64B1F64ToD2F64,
+    C2I32A1U32B1U32ToD2I32,
+    C4I32A4U32B2U32ToD4I32,
+    C4I32A4U32B4U32ToD4I32,
+    C4I32A2U32B1U32ToD4I32,
+    C4I32A2U32B2U32ToD4I32,
+    C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+}
+
+#[allow(clippy::too_many_arguments)]
+fn extract_generated_mma_array(
+    ctx: &mut Context,
+    array: Value,
+    expected_element_ty: TypeHandle,
+    expected_len: usize,
+    block_ptr: Ptr<BasicBlock>,
+    mut last_op: Option<Ptr<Operation>>,
+    loc: Location,
+) -> TranslationResult<(Vec<Value>, Ptr<Operation>)> {
+    let valid = array
+        .get_type(ctx)
+        .deref(ctx)
+        .downcast_ref::<MirArrayType>()
+        .is_some_and(|array_ty| {
+            array_ty.size() == expected_len as u64 && array_ty.element_type() == expected_element_ty
+        });
+    if !valid {
+        return input_err!(
+            loc,
+            TranslationErr::unsupported(format!(
+                "generated MMA fragment must be an array of {expected_len} scalar registers"
+            ))
+        );
+    }
+    let mut registers = Vec::with_capacity(expected_len);
+    for index in 0..expected_len {
+        let extract = Operation::new(
+            ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![expected_element_ty],
+            vec![array],
+            vec![],
+            0,
+        );
+        extract.deref_mut(ctx).set_loc(loc.clone());
+        let extract = MirExtractFieldOp::new(extract);
+        extract.set_attr_index(ctx, FieldIndexAttr(index as u32));
+        helpers::insert_op(ctx, extract.get_operation(), block_ptr, last_op);
+        last_op = Some(extract.get_operation());
+        registers.push(extract.get_operation().deref(ctx).get_result(0));
+    }
+    Ok((
+        registers,
+        last_op.expect("non-empty generated MMA fragment"),
+    ))
+}
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn import_generated_mma_operands(
+    ctx: &mut Context,
+    body: &mir::Body,
+    args: &[mir::Operand],
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    loc: Location,
+    adapter: GeneratedMmaImportAdapter,
+) -> TranslationResult<(Vec<Value>, Ptr<Operation>, TypeHandle, usize)> {
+    let f32_ty: TypeHandle = FP32Type::get(ctx).into();
+    let f64_ty: TypeHandle = FP64Type::get(ctx).into();
+    let i32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Signed).into();
+    let u32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+    let (c_ty, c_count, a_ty, a_count, a_array, b_ty, b_count, b_array, result_ty, result_count) =
+        match adapter {
+            GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32 => {
+                (u32_ty, 2, u32_ty, 2, true, u32_ty, 1, false, u32_ty, 2)
+            }
+            GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32 => {
+                (u32_ty, 2, u32_ty, 4, true, u32_ty, 2, true, u32_ty, 2)
+            }
+            GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32 => {
+                (u32_ty, 2, u32_ty, 4, true, u32_ty, 4, true, u32_ty, 2)
+            }
+            GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32 => {
+                (f32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, f32_ty, 4)
+            }
+            GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32 => {
+                (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4)
+            }
+            GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32 => {
+                (f32_ty, 4, u32_ty, 4, true, u32_ty, 4, true, f32_ty, 4)
+            }
+            GeneratedMmaImportAdapter::C2F64A1F64B1F64ToD2F64 => {
+                (f64_ty, 2, f64_ty, 1, false, f64_ty, 1, false, f64_ty, 2)
+            }
+            GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32 => {
+                (i32_ty, 2, u32_ty, 1, false, u32_ty, 1, false, i32_ty, 2)
+            }
+            GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32 => {
+                (i32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, i32_ty, 4)
+            }
+            GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32 => {
+                (i32_ty, 4, u32_ty, 4, true, u32_ty, 4, true, i32_ty, 4)
+            }
+            GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32 => {
+                (i32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, i32_ty, 4)
+            }
+            GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32 => {
+                (i32_ty, 4, u32_ty, 2, true, u32_ty, 2, true, i32_ty, 4)
+            }
+            GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32 => {
+                (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4)
+            }
+        };
+    let (c_array, last_op) = rvalue::translate_operand(
+        ctx,
+        body,
+        &args[0],
+        value_map,
+        block_ptr,
+        prev_op,
+        loc.clone(),
+    )?;
+    let (mut operands, last_op) =
+        extract_generated_mma_array(ctx, c_array, c_ty, c_count, block_ptr, last_op, loc.clone())?;
+    let (a_value, last_after_a) = rvalue::translate_operand(
+        ctx,
+        body,
+        &args[1],
+        value_map,
+        block_ptr,
+        Some(last_op),
+        loc.clone(),
+    )?;
+    let (a_registers, last_op) = if a_array {
+        extract_generated_mma_array(
+            ctx,
+            a_value,
+            a_ty,
+            a_count,
+            block_ptr,
+            last_after_a,
+            loc.clone(),
+        )?
+    } else {
+        (
+            vec![a_value],
+            last_after_a.expect("generated MMA A translation keeps predecessor"),
+        )
+    };
+    operands.extend(a_registers);
+    let (b_value, last_after_b) = rvalue::translate_operand(
+        ctx,
+        body,
+        &args[2],
+        value_map,
+        block_ptr,
+        Some(last_op),
+        loc.clone(),
+    )?;
+    let (b_registers, last_op) = if b_array {
+        extract_generated_mma_array(
+            ctx,
+            b_value,
+            b_ty,
+            b_count,
+            block_ptr,
+            last_after_b,
+            loc.clone(),
+        )?
+    } else {
+        (
+            vec![b_value],
+            last_after_b.expect("generated MMA B translation keeps predecessor"),
+        )
+    };
+    operands.extend(b_registers);
+    let mut last_op = last_op;
+    if matches!(
+        adapter,
+        GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32
+    ) {
+        for arg in &args[3..] {
+            let (value, translated) = rvalue::translate_operand(
+                ctx,
+                body,
+                arg,
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            last_op = translated
+                .expect("generated block-scale MMA operand translation keeps predecessor");
+            operands.push(value);
+        }
+    }
+    Ok((operands, last_op, result_ty, result_count))
+}
+
+pub(super) fn bundle_generated_mma_results(
+    ctx: &mut Context,
+    mma: Ptr<Operation>,
+    result_ty: TypeHandle,
+    result_count: usize,
+    loc: Location,
+) -> (Value, Ptr<Operation>) {
+    let results = (0..result_count)
+        .map(|index| mma.deref(ctx).get_result(index))
+        .collect();
+    let array_ty = MirArrayType::get(ctx, result_ty, result_count as u64);
+    let array = Operation::new(
+        ctx,
+        MirConstructArrayOp::get_concrete_op_info(),
+        vec![array_ty.into()],
+        results,
+        vec![],
+        0,
+    );
+    array.deref_mut(ctx).set_loc(loc);
+    array.insert_after(ctx, mma);
+    (array.deref(ctx).get_result(0), array)
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs
new file mode 100644
index 0000000000..4e67745367
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs
@@ -0,0 +1,354 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `integer_minmax` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    MaxReluS16x2Op, MaxReluS32Op, MaxS16x2Op, MaxU16x2Op, MinReluS16x2Op, MinReluS32Op, MinS16x2Op,
+    MinU16x2Op,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
+        | "cuda_device::i16x2::max_relu_s16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MaxReluS16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0994");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_relu_s16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
+        | "cuda_device::int::max_relu_s32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MaxReluS32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0988");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_relu_s32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
+        | "cuda_device::i16x2::max_s16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MaxS16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0990");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_s16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
+        | "cuda_device::i16x2::max_u16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MaxU16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0992");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_u16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
+        | "cuda_device::i16x2::min_relu_s16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MinReluS16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0993");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_relu_s16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
+        | "cuda_device::int::min_relu_s32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MinReluS32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0987");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_relu_s32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
+        | "cuda_device::i16x2::min_s16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MinS16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0989");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_s16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
+        | "cuda_device::i16x2::min_u16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MinU16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0991");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_u16x2 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs
new file mode 100644
index 0000000000..672fbb74c2
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs
@@ -0,0 +1,734 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `ldmatrix` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    LdmatrixElementAttr, LdmatrixLayoutAttr, LdmatrixMultiplicityAttr, LdmatrixOp,
+    LdmatrixShapeAttr, LdmatrixStateSpaceAttr,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0378");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m16n16_x1_trans_b8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8x16B4x16P64,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0379");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8x16B6x16P32,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0380");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0381");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m16n16_x2_trans_b8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8x16B4x16P64,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0382");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M16n16,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B8x16B6x16P32,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0383");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B4x16P64,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0384");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let value = load.deref(ctx).get_result(0);
+            let last_op = load;
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n16_x1_b8x16_b4x16_p64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B6x16P32,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0385");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let value = load.deref(ctx).get_result(0);
+            let last_op = load;
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n16_x1_b8x16_b6x16_p32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
+        | "cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B4x16P64,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0386");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n16_x2_b8x16_b4x16_p64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B6x16P32,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0387");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n16_x2_b8x16_b6x16_p32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
+        | "cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X4,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B4x16P64,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0388");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n16_x4_b8x16_b4x16_p64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n16,
+                LdmatrixMultiplicityAttr::X4,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B8x16B6x16P32,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0389");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n16_x4_b8x16_b6x16_p32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
+        | "cuda_device::wmma::ldmatrix_x1" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n8,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B16,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0025");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let value = load.deref(ctx).get_result(0);
+            let last_op = load;
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n8_x1_b16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
+        | "cuda_device::wmma::ldmatrix_x1_trans" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n8,
+                LdmatrixMultiplicityAttr::X1,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B16,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0026");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let value = load.deref(ctx).get_result(0);
+            let last_op = load;
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n8_x1_trans_b16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
+        | "cuda_device::wmma::ldmatrix_x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n8,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B16,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0027");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n8_x2_b16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
+        | "cuda_device::wmma::ldmatrix_x2_trans" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n8,
+                LdmatrixMultiplicityAttr::X2,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B16,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0028");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 2, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n8_x2_trans_b16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
+        | "cuda_device::wmma::ldmatrix_x4" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n8,
+                LdmatrixMultiplicityAttr::X4,
+                LdmatrixLayoutAttr::Normal,
+                LdmatrixElementAttr::B16,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0013");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n8_x4_b16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
+        | "cuda_device::wmma::ldmatrix_x4_trans" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let load = LdmatrixOp::build(
+                ctx,
+                address,
+                LdmatrixShapeAttr::M8n8,
+                LdmatrixMultiplicityAttr::X4,
+                LdmatrixLayoutAttr::Transposed,
+                LdmatrixElementAttr::B16,
+                LdmatrixStateSpaceAttr::Shared,
+            );
+            load.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, load, "v1:i0029");
+            helpers::insert_op(ctx, load, block_ptr, last_op);
+            let (value, last_op) =
+                helpers::bundle_generated_u32_results_as_array(ctx, load, 4, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "ldmatrix_m8n8_x4_trans_b16 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs
new file mode 100644
index 0000000000..d6cd2a299c
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs
@@ -0,0 +1,186 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `mbarrier_basic` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    MbarrierArriveSharedOp, MbarrierInitSharedOp, MbarrierInvalSharedOp, MbarrierTestWaitSharedOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
+        | "cuda_device::barrier::mbarrier_arrive" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let mbarrier = MbarrierArriveSharedOp::build(ctx, barrier);
+            mbarrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, mbarrier, "v1:i0098");
+            helpers::insert_op(ctx, mbarrier, block_ptr, last_op);
+            let result = mbarrier.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                mbarrier,
+                value_map,
+                block_map,
+                loc,
+                "mbarrier_arrive call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
+        | "cuda_device::barrier::mbarrier_init" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (expected_count, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let mbarrier = MbarrierInitSharedOp::build(ctx, barrier, expected_count);
+            mbarrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, mbarrier, "v1:i0097");
+            helpers::insert_op(ctx, mbarrier, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    mbarrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "mbarrier_init call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
+        | "cuda_device::barrier::mbarrier_inval" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let mbarrier = MbarrierInvalSharedOp::build(ctx, barrier);
+            mbarrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, mbarrier, "v1:i0100");
+            helpers::insert_op(ctx, mbarrier, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    mbarrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "mbarrier_inval call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
+        | "cuda_device::barrier::mbarrier_test_wait" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (token, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let mbarrier = MbarrierTestWaitSharedOp::build(ctx, barrier, token);
+            mbarrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, mbarrier, "v1:i0099");
+            helpers::insert_op(ctx, mbarrier, block_ptr, last_op);
+            let result = mbarrier.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                mbarrier,
+                value_map,
+                block_map,
+                loc,
+                "mbarrier_test_wait call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs
new file mode 100644
index 0000000000..ec86e7cac6
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs
@@ -0,0 +1,395 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `mbarrier_extended` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    FenceMbarrierInitReleaseClusterOp, FenceProxyAsyncGenericAcquireSharedClusterClusterOp,
+    FenceProxyAsyncGenericReleaseSharedCtaClusterOp, FenceProxyAsyncSharedCtaOp,
+    MbarrierArriveClusterOp, MbarrierArriveExpectTxClusterOp, MbarrierArriveExpectTxSharedOp,
+    MbarrierTryWaitParityClusterOp, MbarrierTryWaitParitySharedOp, MbarrierTryWaitSharedOp,
+    NanosleepOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
+        | "cuda_device::barrier::fence_mbarrier_init_release_cluster" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let last_op = prev_op;
+            let extended = FenceMbarrierInitReleaseClusterOp::build(ctx);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0313");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    extended,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "fence_mbarrier_init_release_cluster call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
+        | "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let last_op = prev_op;
+            let extended = FenceProxyAsyncGenericAcquireSharedClusterClusterOp::build(ctx);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0315");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    extended,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(loc, TranslationErr::unsupported("fence_proxy_async_generic_acquire_shared_cluster_cluster call without target block".to_owned()))
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
+        | "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let last_op = prev_op;
+            let extended = FenceProxyAsyncGenericReleaseSharedCtaClusterOp::build(ctx);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0314");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    extended,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(loc, TranslationErr::unsupported("fence_proxy_async_generic_release_shared_cta_cluster call without target block".to_owned()))
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
+        | "cuda_device::barrier::fence_proxy_async_shared_cta" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let last_op = prev_op;
+            let extended = FenceProxyAsyncSharedCtaOp::build(ctx);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0312");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    extended,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "fence_proxy_async_shared_cta call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
+        | "cuda_device::barrier::mbarrier_arrive_cluster" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let extended = MbarrierArriveClusterOp::build(ctx, address);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0308");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    extended,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "mbarrier_arrive_cluster call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
+        | "cuda_device::barrier::mbarrier_arrive_expect_tx" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (bytes, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let extended = MbarrierArriveExpectTxSharedOp::build(ctx, barrier, bytes);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0306");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            let result = extended.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                extended,
+                value_map,
+                block_map,
+                loc,
+                "mbarrier_arrive_expect_tx call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
+        | "cuda_device::barrier::mbarrier_arrive_expect_tx_cluster" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (bytes, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let extended = MbarrierArriveExpectTxClusterOp::build(ctx, barrier, bytes);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0307");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            let result = extended.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                extended,
+                value_map,
+                block_map,
+                loc,
+                "mbarrier_arrive_expect_tx_cluster call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
+        | "cuda_device::barrier::mbarrier_try_wait" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (token, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let extended = MbarrierTryWaitSharedOp::build(ctx, barrier, token);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0309");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            let result = extended.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                extended,
+                value_map,
+                block_map,
+                loc,
+                "mbarrier_try_wait call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
+        | "cuda_device::barrier::mbarrier_try_wait_parity" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (parity, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let extended = MbarrierTryWaitParitySharedOp::build(ctx, barrier, parity);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0310");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            let result = extended.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                extended,
+                value_map,
+                block_map,
+                loc,
+                "mbarrier_try_wait_parity call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
+        | "cuda_device::barrier::mbarrier_try_wait_parity_cluster" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (barrier, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (parity, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let extended = MbarrierTryWaitParityClusterOp::build(ctx, barrier, parity);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0311");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            let result = extended.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                extended,
+                value_map,
+                block_map,
+                loc,
+                "mbarrier_try_wait_parity_cluster call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
+        | "cuda_device::barrier::nanosleep" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (ns, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let extended = NanosleepOp::build(ctx, ns);
+            extended.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, extended, "v1:i0316");
+            helpers::insert_op(ctx, extended, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    extended,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported("nanosleep call without target block".to_owned())
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs
new file mode 100644
index 0000000000..cc7a2d219c
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs
@@ -0,0 +1,6010 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility path dispatch for CUDA intrinsics.
+
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::values::ValueMap;
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::Location;
+use pliron::operation::Operation;
+use rustc_public::{CrateDef, mir, ty::FnDef};
+
+mod active_mask;
+mod clc;
+mod cluster_barrier;
+mod cluster_memory;
+mod cp_async;
+mod debug_control;
+mod dotprod;
+mod elect;
+mod execution_control;
+mod extended_minmax;
+mod helpers;
+mod integer_minmax;
+mod ldmatrix;
+mod mbarrier_basic;
+mod mbarrier_extended;
+mod movmatrix;
+mod packed_alu;
+mod packed_atomic;
+mod packed_conversion;
+mod prmt;
+mod redux;
+mod register_mma;
+mod scalar_arithmetic;
+mod scalar_conversion;
+mod scalar_math;
+mod sparse_mma;
+mod sreg;
+mod stmatrix;
+mod sync;
+mod tcgen05_cp;
+mod tcgen05_ld;
+mod tcgen05_mma;
+mod tcgen05_other;
+mod tcgen05_st;
+#[cfg(test)]
+mod tests;
+mod tma;
+mod vote;
+mod warp_barrier;
+mod warp_match;
+mod warp_shuffle;
+mod wgmma_control;
+
+pub const GENERATED_INTRINSIC_ABI: u32 = 1;
+pub const GENERATED_INTRINSIC_ABI_NAMESPACE: &str = "__cuda_oxide_intrinsic_abi_v1";
+
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub enum RawIntrinsicIdentity {
+    NotRawCrate,
+    Known(String),
+    UnsupportedAbi(String),
+    UnknownId(String),
+}
+
+/// Classify the unrewritten raw intrinsic DefPath. rustc's ordinary name
+/// printer may prefer a public re-export path, which is source API rather than ABI.
+pub fn classify_raw_intrinsic(fn_def: FnDef) -> RawIntrinsicIdentity {
+    let crate_name = fn_def.krate().name.to_string();
+    if !matches!(crate_name.as_str(), "cuda_intrinsics" | "cuda-intrinsics") {
+        return RawIntrinsicIdentity::NotRawCrate;
+    }
+
+    let mut segments = Vec::new();
+    let mut current = Some(fn_def.def_id());
+    while let Some(def_id) = current {
+        let printed = def_id.name();
+        let segment = printed.as_str().rsplit("::").next().unwrap_or_default();
+        if segment != crate_name {
+            segments.push(segment.to_owned());
+        }
+        current = def_id.parent();
+    }
+    segments.reverse();
+    classify_raw_intrinsic_path(
+        &crate_name,
+        format!("{crate_name}::{}", segments.join("::")),
+    )
+}
+
+fn classify_raw_intrinsic_path(crate_name: &str, path: String) -> RawIntrinsicIdentity {
+    if !matches!(crate_name, "cuda_intrinsics" | "cuda-intrinsics") {
+        return RawIntrinsicIdentity::NotRawCrate;
+    }
+    if is_raw_generated_intrinsic_path(&path) {
+        return RawIntrinsicIdentity::Known(path);
+    }
+    let namespace = path.split("::").nth(1).unwrap_or_default();
+    if namespace.starts_with("__cuda_oxide_intrinsic_abi_v")
+        && namespace != GENERATED_INTRINSIC_ABI_NAMESPACE
+    {
+        RawIntrinsicIdentity::UnsupportedAbi(path)
+    } else {
+        RawIntrinsicIdentity::UnknownId(path)
+    }
+}
+
+pub fn require_supported_raw_intrinsic(
+    fn_def: FnDef,
+    loc: &Location,
+) -> TranslationResult<Option<String>> {
+    match classify_raw_intrinsic(fn_def) {
+        RawIntrinsicIdentity::NotRawCrate => Ok(None),
+        RawIntrinsicIdentity::Known(path) => Ok(Some(path)),
+        RawIntrinsicIdentity::UnsupportedAbi(path) => input_err!(
+            loc.clone(),
+            TranslationErr::unsupported(format!(
+                "cuda-intrinsics ABI mismatch: `{path}` uses an unsupported intrinsic ABI; this compiler supports ABI v{GENERATED_INTRINSIC_ABI}"
+            ))
+        ),
+        RawIntrinsicIdentity::UnknownId(path) => input_err!(
+            loc.clone(),
+            TranslationErr::unsupported(format!(
+                "cuda-intrinsics ABI mismatch: `{path}` is not a known intrinsic ID in ABI v{GENERATED_INTRINSIC_ABI}"
+            ))
+        ),
+    }
+}
+
+pub fn is_generated_intrinsic_path(name: &str) -> bool {
+    matches!(
+        name,
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
+            | "cuda_device::bf16x2::abs_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
+            | "cuda_device::f16x2::abs_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
+            | "cuda_device::warp::active_mask"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
+            | "cuda_device::bf16x2::add_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
+            | "cuda_device::f16x2::add_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
+            | "cuda_device::f32x2::add_f32x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
+            | "cuda_device::f32x2::add_ftz_f32x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
+            | "cuda_device::float::add_rm_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
+            | "cuda_device::float::add_rm_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
+            | "cuda_device::float::add_rm_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
+            | "cuda_device::float::add_rm_ftz_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
+            | "cuda_device::float::add_rm_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
+            | "cuda_device::float::add_rn_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
+            | "cuda_device::float::add_rn_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
+            | "cuda_device::float::add_rn_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
+            | "cuda_device::float::add_rn_ftz_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
+            | "cuda_device::float::add_rn_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
+            | "cuda_device::float::add_rp_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
+            | "cuda_device::float::add_rp_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
+            | "cuda_device::float::add_rp_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
+            | "cuda_device::float::add_rp_ftz_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
+            | "cuda_device::float::add_rp_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
+            | "cuda_device::float::add_rz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
+            | "cuda_device::float::add_rz_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
+            | "cuda_device::float::add_rz_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
+            | "cuda_device::float::add_rz_ftz_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
+            | "cuda_device::float::add_rz_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040"
+            | "cuda_device::warp::all_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041"
+            | "cuda_device::warp::any_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
+            | "cuda_device::warp::ballot_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
+            | "cuda_device::cluster::barrier_cluster_arrive"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
+            | "cuda_device::cluster::barrier_cluster_arrive_aligned"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
+            | "cuda_device::cluster::barrier_cluster_arrive_relaxed"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
+            | "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
+            | "cuda_device::cluster::barrier_cluster_wait"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
+            | "cuda_device::cluster::barrier_cluster_wait_aligned"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
+            | "cuda_device::barrier::barrier_cta_arrive"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
+            | "cuda_device::barrier::barrier_cta_arrive_aligned"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
+            | "cuda_device::barrier::barrier_cta_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
+            | "cuda_device::barrier::barrier_cta_sync_aligned"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
+            | "cuda_device::thread::blockDim_x"
+            | "cuda_device::blockDim_x"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
+            | "cuda_device::thread::blockDim_y"
+            | "cuda_device::blockDim_y"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
+            | "cuda_device::thread::blockDim_z"
+            | "cuda_device::blockDim_z"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
+            | "cuda_device::thread::blockIdx_x"
+            | "cuda_device::blockIdx_x"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
+            | "cuda_device::thread::blockIdx_y"
+            | "cuda_device::blockIdx_y"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
+            | "cuda_device::thread::blockIdx_z"
+            | "cuda_device::blockIdx_z"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
+            | "cuda_device::debug::breakpoint"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
+            | "cuda_device::clc::clc_query_get_first_ctaid_x"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
+            | "cuda_device::clc::clc_query_get_first_ctaid_y"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
+            | "cuda_device::clc::clc_query_get_first_ctaid_z"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
+            | "cuda_device::clc::clc_query_is_canceled"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
+            | "cuda_device::clc::clc_try_cancel"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
+            | "cuda_device::clc::clc_try_cancel_multicast"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283"
+            | "cuda_device::debug::clock"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284"
+            | "cuda_device::debug::clock64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
+            | "cuda_device::cluster::cluster_ctaidX"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
+            | "cuda_device::cluster::cluster_ctaidY"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
+            | "cuda_device::cluster::cluster_ctaidZ"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
+            | "cuda_device::cluster::cluster_nctaidX"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
+            | "cuda_device::cluster::cluster_nctaidY"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
+            | "cuda_device::cluster::cluster_nctaidZ"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
+            | "cuda_device::cluster::__cluster_grid_dimX"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
+            | "cuda_device::cluster::__cluster_grid_dimY"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
+            | "cuda_device::cluster::__cluster_grid_dimZ"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
+            | "cuda_device::cluster::__cluster_idxX"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
+            | "cuda_device::cluster::__cluster_idxY"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
+            | "cuda_device::cluster::__cluster_idxZ"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
+            | "cuda_device::float::cos_approx_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
+            | "cuda_device::float::cos_approx_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
+            | "cuda_device::tma::cp_async_bulk_commit_group"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
+            | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
+            | "cuda_device::tma::cp_async_bulk_tensor_1d_g2s"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
+            | "cuda_device::tma::cp_async_bulk_tensor_1d_s2g"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
+            | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
+            | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
+            | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
+            | "cuda_device::tma::cp_async_bulk_tensor_2d_s2g"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
+            | "cuda_device::tma::cp_async_bulk_tensor_3d_g2s"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
+            | "cuda_device::tma::cp_async_bulk_tensor_3d_s2g"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
+            | "cuda_device::tma::cp_async_bulk_tensor_4d_g2s"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
+            | "cuda_device::tma::cp_async_bulk_tensor_4d_s2g"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
+            | "cuda_device::tma::cp_async_bulk_tensor_5d_g2s"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
+            | "cuda_device::tma::cp_async_bulk_tensor_5d_s2g"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
+            | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
+            | "cuda_device::tma::cp_async_bulk_wait_group"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
+            | "cuda_device::tma::cp_async_bulk_wait_group_read"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
+            | "cuda_device::async_copy::cp_async_ca_16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
+            | "cuda_device::async_copy::cp_async_ca_4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
+            | "cuda_device::async_copy::cp_async_ca_8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
+            | "cuda_device::async_copy::cp_async_ca_zfill_16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
+            | "cuda_device::async_copy::cp_async_ca_zfill_4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
+            | "cuda_device::async_copy::cp_async_ca_zfill_8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
+            | "cuda_device::async_copy::cp_async_cg_16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
+            | "cuda_device::async_copy::cp_async_cg_zfill_16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
+            | "cuda_device::async_copy::cp_async_commit_group"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
+            | "cuda_device::async_copy::cp_async_mbarrier_arrive"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
+            | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
+            | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
+            | "cuda_device::async_copy::cp_async_mbarrier_arrive_shared"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
+            | "cuda_device::async_copy::cp_async_wait_all"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
+            | "cuda_device::async_copy::cp_async_wait_group"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
+            | "cuda_device::convert::cvt_f16x2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
+            | "cuda_device::convert::cvt_bf16x2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
+            | "cuda_device::convert::cvt_rn_f16x2_e4m3x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
+            | "cuda_device::convert::cvt_rn_f16x2_e5m2x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
+            | "cuda_device::convert::cvt_rn_relu_bf16x2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
+            | "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
+            | "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
+            | "cuda_device::convert::cvt_rn_relu_f16x2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
+            | "cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
+            | "cuda_device::convert::cvt_rn_relu_tf32_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
+            | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
+            | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
+            | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
+            | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
+            | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
+            | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
+            | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
+            | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
+            | "cuda_device::convert::cvt_rn_satfinite_tf32_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
+            | "cuda_device::convert::cvt_rn_tf32_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
+            | "cuda_device::convert::cvt_rna_satfinite_tf32_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
+            | "cuda_device::convert::cvt_rna_tf32_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
+            | "cuda_device::convert::cvt_rz_bf16x2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
+            | "cuda_device::convert::cvt_rz_f16x2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
+            | "cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
+            | "cuda_device::convert::cvt_rz_relu_tf32_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
+            | "cuda_device::convert::cvt_rz_satfinite_tf32_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
+            | "cuda_device::convert::cvt_rz_tf32_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
+            | "cuda_device::float::div_rm_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
+            | "cuda_device::float::div_rm_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
+            | "cuda_device::float::div_rm_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
+            | "cuda_device::float::div_rn_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
+            | "cuda_device::float::div_rn_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
+            | "cuda_device::float::div_rn_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
+            | "cuda_device::float::div_rp_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
+            | "cuda_device::float::div_rp_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
+            | "cuda_device::float::div_rp_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
+            | "cuda_device::float::div_rz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
+            | "cuda_device::float::div_rz_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
+            | "cuda_device::float::div_rz_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
+            | "cuda_device::dotprod::dp2a_s32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
+            | "cuda_device::dotprod::dp2a_u32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
+            | "cuda_device::dotprod::dp4a_s32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
+            | "cuda_device::dotprod::dp4a_u32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
+            | "cuda_device::cluster::dsmem_read_u32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
+            | "cuda_device::shared::dynamic_smem_size"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
+            | "cuda_device::warp::elect_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286"
+            | "cuda_device::grid::envreg1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287"
+            | "cuda_device::grid::envreg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
+            | "cuda_device::float::ex2_approx_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
+            | "cuda_device::float::ex2_approx_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
+            | "cuda_device::float::ex2_approx_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
+            | "cuda_device::barrier::fence_mbarrier_init_release_cluster"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
+            | "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
+            | "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
+            | "cuda_device::barrier::fence_proxy_async_shared_cta"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
+            | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
+            | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
+            | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
+            | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
+            | "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
+            | "cuda_device::tma::fence_proxy_tensormap_generic_release_cta"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
+            | "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
+            | "cuda_device::tma::fence_proxy_tensormap_generic_release_system"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
+            | "cuda_device::bf16x2::fma_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
+            | "cuda_device::f16x2::fma_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
+            | "cuda_device::f32x2::fma_f32x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
+            | "cuda_device::f16x2::fma_ftz_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
+            | "cuda_device::f32x2::fma_ftz_f32x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
+            | "cuda_device::f16x2::fma_ftz_relu_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
+            | "cuda_device::f16x2::fma_ftz_sat_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
+            | "cuda_device::bf16x2::fma_relu_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
+            | "cuda_device::f16x2::fma_relu_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
+            | "cuda_device::float::fma_rm_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
+            | "cuda_device::float::fma_rm_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
+            | "cuda_device::float::fma_rm_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
+            | "cuda_device::float::fma_rm_ftz_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
+            | "cuda_device::float::fma_rm_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
+            | "cuda_device::float::fma_rn_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
+            | "cuda_device::float::fma_rn_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
+            | "cuda_device::float::fma_rn_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
+            | "cuda_device::float::fma_rn_ftz_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
+            | "cuda_device::float::fma_rn_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
+            | "cuda_device::float::fma_rp_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
+            | "cuda_device::float::fma_rp_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
+            | "cuda_device::float::fma_rp_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
+            | "cuda_device::float::fma_rp_ftz_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
+            | "cuda_device::float::fma_rp_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
+            | "cuda_device::float::fma_rz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
+            | "cuda_device::float::fma_rz_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
+            | "cuda_device::float::fma_rz_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
+            | "cuda_device::float::fma_rz_ftz_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
+            | "cuda_device::float::fma_rz_sat_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
+            | "cuda_device::f16x2::fma_sat_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
+            | "cuda_device::debug::globaltimer"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
+            | "cuda_device::grid::dependency::trigger_dependents"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
+            | "cuda_device::grid::dependency::wait"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
+            | "cuda_device::thread::gridDim_x"
+            | "cuda_device::gridDim_x"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
+            | "cuda_device::thread::gridDim_y"
+            | "cuda_device::gridDim_y"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
+            | "cuda_device::thread::gridDim_z"
+            | "cuda_device::gridDim_z"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
+            | "cuda_device::thread::gridid"
+            | "cuda_device::gridid"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016"
+            | "cuda_device::warp::lane_id"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
+            | "cuda_device::warp::lanemask_eq"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
+            | "cuda_device::warp::lanemask_ge"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
+            | "cuda_device::warp::lanemask_gt"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
+            | "cuda_device::warp::lanemask_le"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
+            | "cuda_device::warp::lanemask_lt"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
+            | "cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
+            | "cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
+            | "cuda_device::wmma::ldmatrix_x1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
+            | "cuda_device::wmma::ldmatrix_x1_trans"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
+            | "cuda_device::wmma::ldmatrix_x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
+            | "cuda_device::wmma::ldmatrix_x2_trans"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
+            | "cuda_device::wmma::ldmatrix_x4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
+            | "cuda_device::wmma::ldmatrix_x4_trans"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
+            | "cuda_device::float::lg2_approx_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
+            | "cuda_device::float::lg2_approx_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
+            | "cuda_device::cluster::map_shared_rank"
+            | "cuda_device::cluster::map_shared_rank_mut"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
+            | "cuda_device::warp::match_all_i64_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
+            | "cuda_device::warp::match_all_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
+            | "cuda_device::warp::match_any_i64_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
+            | "cuda_device::warp::match_any_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850"
+            | "cuda_device::bf16::max_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
+            | "cuda_device::bf16x2::max_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842"
+            | "cuda_device::f16::max_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
+            | "cuda_device::f16x2::max_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
+            | "cuda_device::f16::max_ftz_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
+            | "cuda_device::f16x2::max_ftz_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
+            | "cuda_device::f16::max_ftz_nan_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
+            | "cuda_device::f16x2::max_ftz_nan_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
+            | "cuda_device::f16::max_ftz_nan_xorsign_abs_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
+            | "cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
+            | "cuda_device::float::max_ftz_nan_xorsign_abs_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
+            | "cuda_device::f16::max_ftz_xorsign_abs_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
+            | "cuda_device::f16x2::max_ftz_xorsign_abs_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
+            | "cuda_device::float::max_ftz_xorsign_abs_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
+            | "cuda_device::bf16::max_nan_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
+            | "cuda_device::bf16x2::max_nan_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
+            | "cuda_device::f16::max_nan_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
+            | "cuda_device::f16x2::max_nan_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
+            | "cuda_device::bf16::max_nan_xorsign_abs_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
+            | "cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
+            | "cuda_device::f16::max_nan_xorsign_abs_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
+            | "cuda_device::f16x2::max_nan_xorsign_abs_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
+            | "cuda_device::float::max_nan_xorsign_abs_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
+            | "cuda_device::i16x2::max_relu_s16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
+            | "cuda_device::int::max_relu_s32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
+            | "cuda_device::i16x2::max_s16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
+            | "cuda_device::i16x2::max_u16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
+            | "cuda_device::bf16::max_xorsign_abs_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
+            | "cuda_device::bf16x2::max_xorsign_abs_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
+            | "cuda_device::f16::max_xorsign_abs_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
+            | "cuda_device::f16x2::max_xorsign_abs_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
+            | "cuda_device::float::max_xorsign_abs_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
+            | "cuda_device::barrier::mbarrier_arrive"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
+            | "cuda_device::barrier::mbarrier_arrive_cluster"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
+            | "cuda_device::barrier::mbarrier_arrive_expect_tx"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
+            | "cuda_device::barrier::mbarrier_arrive_expect_tx_cluster"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
+            | "cuda_device::barrier::mbarrier_init"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
+            | "cuda_device::barrier::mbarrier_inval"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
+            | "cuda_device::barrier::mbarrier_test_wait"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
+            | "cuda_device::barrier::mbarrier_try_wait"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
+            | "cuda_device::barrier::mbarrier_try_wait_parity"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
+            | "cuda_device::barrier::mbarrier_try_wait_parity_cluster"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838"
+            | "cuda_device::bf16::min_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
+            | "cuda_device::bf16x2::min_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830"
+            | "cuda_device::f16::min_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
+            | "cuda_device::f16x2::min_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
+            | "cuda_device::f16::min_ftz_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
+            | "cuda_device::f16x2::min_ftz_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
+            | "cuda_device::f16::min_ftz_nan_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
+            | "cuda_device::f16x2::min_ftz_nan_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
+            | "cuda_device::f16::min_ftz_nan_xorsign_abs_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
+            | "cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
+            | "cuda_device::float::min_ftz_nan_xorsign_abs_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
+            | "cuda_device::f16::min_ftz_xorsign_abs_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
+            | "cuda_device::f16x2::min_ftz_xorsign_abs_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
+            | "cuda_device::float::min_ftz_xorsign_abs_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
+            | "cuda_device::bf16::min_nan_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
+            | "cuda_device::bf16x2::min_nan_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
+            | "cuda_device::f16::min_nan_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
+            | "cuda_device::f16x2::min_nan_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
+            | "cuda_device::bf16::min_nan_xorsign_abs_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
+            | "cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
+            | "cuda_device::f16::min_nan_xorsign_abs_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
+            | "cuda_device::f16x2::min_nan_xorsign_abs_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
+            | "cuda_device::float::min_nan_xorsign_abs_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
+            | "cuda_device::i16x2::min_relu_s16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
+            | "cuda_device::int::min_relu_s32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
+            | "cuda_device::i16x2::min_s16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
+            | "cuda_device::i16x2::min_u16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
+            | "cuda_device::bf16::min_xorsign_abs_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
+            | "cuda_device::bf16x2::min_xorsign_abs_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
+            | "cuda_device::f16::min_xorsign_abs_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
+            | "cuda_device::f16x2::min_xorsign_abs_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
+            | "cuda_device::float::min_xorsign_abs_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
+            | "cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
+            | "cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
+            | "cuda_device::wmma::mma_m16n8k16_f16_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
+            | "cuda_device::wmma::mma_m16n8k16_f32_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
+            | "cuda_device::wmma::mma_m16n8k16_f32_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
+            | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
+            | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
+            | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
+            | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
+            | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
+            | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
+            | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
+            | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
+            | "cuda_device::wmma::mma_m16n8k16_s32_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
+            | "cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
+            | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
+            | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
+            | "cuda_device::wmma::mma_m16n8k16_s32_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
+            | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
+            | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
+            | "cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
+            | "cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
+            | "cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
+            | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
+            | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
+            | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
+            | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
+            | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
+            | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
+            | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
+            | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
+            | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
+            | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
+            | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
+            | "cuda_device::wmma::mma_m16n8k32_s32_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
+            | "cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
+            | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
+            | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
+            | "cuda_device::wmma::mma_m16n8k32_s32_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
+            | "cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
+            | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
+            | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
+            | "cuda_device::wmma::mma_m16n8k32_s32_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
+            | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
+            | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
+            | "cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
+            | "cuda_device::wmma::mma_m16n8k32_s32_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
+            | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
+            | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
+            | "cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
+            | "cuda_device::wmma::mma_m16n8k4_f32_tf32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
+            | "cuda_device::wmma::mma_m16n8k64_s32_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
+            | "cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
+            | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
+            | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
+            | "cuda_device::wmma::mma_m16n8k64_s32_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
+            | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
+            | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
+            | "cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
+            | "cuda_device::wmma::mma_m16n8k8_f16_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
+            | "cuda_device::wmma::mma_m16n8k8_f32_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
+            | "cuda_device::wmma::mma_m16n8k8_f32_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
+            | "cuda_device::wmma::mma_m16n8k8_f32_tf32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
+            | "cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
+            | "cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
+            | "cuda_device::wmma::mma_m8n8k16_s32_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
+            | "cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
+            | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
+            | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
+            | "cuda_device::wmma::mma_m8n8k16_s32_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
+            | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
+            | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
+            | "cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
+            | "cuda_device::wmma::mma_m8n8k32_s32_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
+            | "cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
+            | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
+            | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
+            | "cuda_device::wmma::mma_m8n8k32_s32_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
+            | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
+            | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
+            | "cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
+            | "cuda_device::wmma::mma_m8n8k4_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
+            | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
+            | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
+            | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
+            | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
+            | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
+            | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
+            | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
+            | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
+            | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
+            | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
+            | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
+            | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
+            | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
+            | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
+            | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
+            | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
+            | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
+            | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
+            | "cuda_device::wmma::movmatrix_trans_b16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
+            | "cuda_device::bf16x2::mul_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
+            | "cuda_device::f16x2::mul_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
+            | "cuda_device::f32x2::mul_f32x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
+            | "cuda_device::f32x2::mul_ftz_f32x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
+            | "cuda_device::float::mul_rm_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
+            | "cuda_device::float::mul_rm_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
+            | "cuda_device::float::mul_rm_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
+            | "cuda_device::float::mul_rn_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
+            | "cuda_device::float::mul_rn_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
+            | "cuda_device::float::mul_rn_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
+            | "cuda_device::float::mul_rp_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
+            | "cuda_device::float::mul_rp_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
+            | "cuda_device::float::mul_rp_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
+            | "cuda_device::float::mul_rz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
+            | "cuda_device::float::mul_rz_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
+            | "cuda_device::float::mul_rz_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
+            | "cuda_device::barrier::nanosleep"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
+            | "cuda_device::bf16x2::neg_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
+            | "cuda_device::f16x2::neg_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
+            | "cuda_device::thread::nsmid"
+            | "cuda_device::nsmid"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292"
+            | "cuda_device::warp::nwarpid"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
+            | "cuda_device::atomic::atom_add_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
+            | "cuda_device::atomic::atom_add_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
+            | "cuda_device::debug::__prof_trigger"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
+            | "cuda_device::tma::prefetch_tma_descriptor"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252"
+            | "cuda_device::prmt::prmt"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254"
+            | "cuda_device::prmt::prmt_b4e"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256"
+            | "cuda_device::prmt::prmt_ecl"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257"
+            | "cuda_device::prmt::prmt_ecr"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253"
+            | "cuda_device::prmt::prmt_f4e"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
+            | "cuda_device::prmt::prmt_rc16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255"
+            | "cuda_device::prmt::prmt_rc8"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
+            | "cuda_device::float::rcp_approx_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
+            | "cuda_device::float::rcp_approx_ftz_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
+            | "cuda_device::float::rcp_rm_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
+            | "cuda_device::float::rcp_rm_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
+            | "cuda_device::float::rcp_rm_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
+            | "cuda_device::float::rcp_rn_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
+            | "cuda_device::float::rcp_rn_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
+            | "cuda_device::float::rcp_rn_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
+            | "cuda_device::float::rcp_rp_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
+            | "cuda_device::float::rcp_rp_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
+            | "cuda_device::float::rcp_rp_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
+            | "cuda_device::float::rcp_rz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
+            | "cuda_device::float::rcp_rz_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
+            | "cuda_device::float::rcp_rz_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
+            | "cuda_device::warp::redux_sync_add"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
+            | "cuda_device::warp::redux_sync_and"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
+            | "cuda_device::warp::redux_sync_max_abs_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
+            | "cuda_device::warp::redux_sync_max_abs_nan_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
+            | "cuda_device::warp::redux_sync_max_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
+            | "cuda_device::warp::redux_sync_max_i32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
+            | "cuda_device::warp::redux_sync_max_nan_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
+            | "cuda_device::warp::redux_sync_max_u32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
+            | "cuda_device::warp::redux_sync_min_abs_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
+            | "cuda_device::warp::redux_sync_min_abs_nan_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
+            | "cuda_device::warp::redux_sync_min_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
+            | "cuda_device::warp::redux_sync_min_i32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
+            | "cuda_device::warp::redux_sync_min_nan_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
+            | "cuda_device::warp::redux_sync_min_u32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
+            | "cuda_device::warp::redux_sync_or"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
+            | "cuda_device::warp::redux_sync_xor"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
+            | "cuda_device::float::rsqrt_approx_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
+            | "cuda_device::float::rsqrt_approx_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
+            | "cuda_device::float::rsqrt_approx_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
+            | "cuda_device::thread::__setmaxnreg_dec"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
+            | "cuda_device::thread::__setmaxnreg_inc"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
+            | "cuda_device::warp::shuffle_down_f32_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
+            | "cuda_device::warp::shuffle_down_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
+            | "cuda_device::warp::shuffle_down_u64_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
+            | "cuda_device::warp::shuffle_f32_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
+            | "cuda_device::warp::shuffle_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
+            | "cuda_device::warp::shuffle_u64_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
+            | "cuda_device::warp::shuffle_up_f32_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
+            | "cuda_device::warp::shuffle_up_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
+            | "cuda_device::warp::shuffle_up_u64_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
+            | "cuda_device::warp::shuffle_xor_f32_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
+            | "cuda_device::warp::shuffle_xor_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
+            | "cuda_device::warp::shuffle_xor_u64_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
+            | "cuda_device::float::sin_approx_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
+            | "cuda_device::float::sin_approx_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
+            | "cuda_device::thread::smid"
+            | "cuda_device::smid"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
+            | "cuda_device::float::sqrt_approx_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
+            | "cuda_device::float::sqrt_approx_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
+            | "cuda_device::float::sqrt_rm_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
+            | "cuda_device::float::sqrt_rm_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
+            | "cuda_device::float::sqrt_rm_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
+            | "cuda_device::float::sqrt_rn_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
+            | "cuda_device::float::sqrt_rn_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
+            | "cuda_device::float::sqrt_rn_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
+            | "cuda_device::float::sqrt_rp_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
+            | "cuda_device::float::sqrt_rp_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
+            | "cuda_device::float::sqrt_rp_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
+            | "cuda_device::float::sqrt_rz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
+            | "cuda_device::float::sqrt_rz_f64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
+            | "cuda_device::float::sqrt_rz_ftz_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
+            | "cuda_device::tcgen05::stmatrix_m8n8_x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
+            | "cuda_device::tcgen05::stmatrix_m8n8_x2_trans"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
+            | "cuda_device::tcgen05::stmatrix_m8n8_x4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
+            | "cuda_device::tcgen05::stmatrix_m8n8_x4_trans"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
+            | "cuda_device::bf16x2::sub_bf16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
+            | "cuda_device::f16x2::sub_f16x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
+            | "cuda_device::f32x2::sub_f32x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
+            | "cuda_device::f32x2::sub_ftz_f32x2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
+            | "cuda_device::warp::sync_mask"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
+            | "cuda_device::thread::sync_threads"
+            | "cuda_device::sync_threads"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
+            | "cuda_device::float::tanh_approx_f32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
+            | "cuda_device::tcgen05::tcgen05_alloc"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
+            | "cuda_device::tcgen05::tcgen05_alloc_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
+            | "cuda_device::tcgen05::tcgen05_commit"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
+            | "cuda_device::tcgen05::tcgen05_commit_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
+            | "cuda_device::tcgen05::tcgen05_commit_multicast"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
+            | "cuda_device::tcgen05::tcgen05_commit_multicast_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
+            | "cuda_device::tcgen05::tcgen05_commit_shared_cluster"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
+            | "cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
+            | "cuda_device::tcgen05::tcgen05_cp_128x128b"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
+            | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
+            | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
+            | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
+            | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
+            | "cuda_device::tcgen05::tcgen05_cp_128x128b_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
+            | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
+            | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
+            | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
+            | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
+            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
+            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
+            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
+            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
+            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
+            | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
+            | "cuda_device::tcgen05::tcgen05_cp_4x256b"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
+            | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
+            | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
+            | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
+            | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
+            | "cuda_device::tcgen05::tcgen05_cp_4x256b_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
+            | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
+            | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
+            | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
+            | "cuda_device::tcgen05::tcgen05_dealloc"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
+            | "cuda_device::tcgen05::tcgen05_dealloc_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
+            | "cuda_device::tcgen05::tcgen05_fence_after_thread_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
+            | "cuda_device::tcgen05::tcgen05_fence_before_thread_sync"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
+            | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_pure"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
+            | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
+            | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
+            | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
+            | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
+            | "cuda_device::tcgen05::tcgen05_load_wait"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
+            | "cuda_device::tcgen05::tcgen05_mma_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
+            | "cuda_device::tcgen05::tcgen05_mma_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
+            | "cuda_device::tcgen05::tcgen05_mma_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
+            | "cuda_device::tcgen05::tcgen05_mma_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
+            | "cuda_device::tcgen05::tcgen05_mma_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
+            | "cuda_device::tcgen05::tcgen05_mma_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
+            | "cuda_device::tcgen05::tcgen05_mma_f16_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
+            | "cuda_device::tcgen05::__tcgen05_mma_shared"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
+            | "cuda_device::tcgen05::__tcgen05_mma_sp_shared"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
+            | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
+            | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
+            | "cuda_device::tcgen05::__tcgen05_mma_tensor"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
+            | "cuda_device::tcgen05::__tcgen05_mma_tensor_ashift"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
+            | "cuda_device::tcgen05::tcgen05_mma_ws_bf16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
+            | "cuda_device::tcgen05::tcgen05_mma_ws_e2m1"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
+            | "cuda_device::tcgen05::tcgen05_mma_ws_e2m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
+            | "cuda_device::tcgen05::tcgen05_mma_ws_e3m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
+            | "cuda_device::tcgen05::tcgen05_mma_ws_e4m3"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
+            | "cuda_device::tcgen05::tcgen05_mma_ws_e5m2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
+            | "cuda_device::tcgen05::tcgen05_mma_ws_f16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
+            | "cuda_device::tcgen05::__tcgen05_mma_ws_shared"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
+            | "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
+            | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
+            | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
+            | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
+            | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
+            | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
+            | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
+            | "cuda_device::tcgen05::tcgen05_mma_ws_tf32"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
+            | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
+            | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
+            | "cuda_device::tcgen05::tcgen05_shift_down"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
+            | "cuda_device::tcgen05::tcgen05_shift_down_cg2"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
+            | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
+            | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
+            | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
+            | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
+            | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
+            | "cuda_device::tcgen05::tcgen05_store_wait"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
+            | "cuda_device::tma::tensormap_replace_box_dim"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
+            | "cuda_device::tma::tensormap_replace_element_stride"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
+            | "cuda_device::tma::tensormap_replace_element_type"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
+            | "cuda_device::tma::tensormap_replace_fill_mode"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
+            | "cuda_device::tma::tensormap_replace_global_address"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
+            | "cuda_device::tma::tensormap_replace_global_dim"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
+            | "cuda_device::tma::tensormap_replace_global_stride"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
+            | "cuda_device::tma::tensormap_replace_interleave_layout"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
+            | "cuda_device::tma::tensormap_replace_rank"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
+            | "cuda_device::tma::tensormap_replace_swizzle_atomicity"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
+            | "cuda_device::tma::tensormap_replace_swizzle_mode"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
+            | "cuda_device::thread::threadIdx_x"
+            | "cuda_device::threadIdx_x"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
+            | "cuda_device::thread::threadIdx_y"
+            | "cuda_device::threadIdx_y"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
+            | "cuda_device::thread::threadIdx_z"
+            | "cuda_device::threadIdx_z"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
+            | "cuda_device::fence::threadfence"
+            | "cuda_device::threadfence"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
+            | "cuda_device::fence::threadfence_block"
+            | "cuda_device::threadfence_block"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
+            | "cuda_device::fence::threadfence_system"
+            | "cuda_device::threadfence_system"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
+            | "cuda_device::shared::total_smem_size"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295"
+            | "cuda_device::debug::trap"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291"
+            | "cuda_device::warp::warpid"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
+            | "cuda_device::wgmma::wgmma_commit_group"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
+            | "cuda_device::wgmma::wgmma_fence"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
+            | "cuda_device::wgmma::__wgmma_wait_group"
+    )
+}
+
+pub fn is_raw_generated_intrinsic_path(name: &str) -> bool {
+    matches!(
+        name,
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
+            | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
+    )
+}
+
+#[cfg(test)]
+pub fn generated_intrinsic_marker(name: &str) -> Option<&'static str> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
+        | "cuda_device::bf16x2::abs_bf16x2" => Some("v1:i0070"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
+        | "cuda_device::f16x2::abs_f16x2" => Some("v1:i0080"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
+        | "cuda_device::warp::active_mask" => Some("v1:i0044"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
+        | "cuda_device::bf16x2::add_bf16x2" => Some("v1:i0064"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
+        | "cuda_device::f16x2::add_f16x2" => Some("v1:i0074"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
+        | "cuda_device::f32x2::add_f32x2" => Some("v1:i0995"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
+        | "cuda_device::f32x2::add_ftz_f32x2" => Some("v1:i0996"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
+        | "cuda_device::float::add_rm_f32" => Some("v1:i0446"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
+        | "cuda_device::float::add_rm_f64" => Some("v1:i0436"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
+        | "cuda_device::float::add_rm_ftz_f32" => Some("v1:i0447"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
+        | "cuda_device::float::add_rm_ftz_sat_f32" => Some("v1:i0449"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
+        | "cuda_device::float::add_rm_sat_f32" => Some("v1:i0448"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
+        | "cuda_device::float::add_rn_f32" => Some("v1:i0438"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
+        | "cuda_device::float::add_rn_f64" => Some("v1:i0434"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
+        | "cuda_device::float::add_rn_ftz_f32" => Some("v1:i0439"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
+        | "cuda_device::float::add_rn_ftz_sat_f32" => Some("v1:i0441"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
+        | "cuda_device::float::add_rn_sat_f32" => Some("v1:i0440"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
+        | "cuda_device::float::add_rp_f32" => Some("v1:i0450"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
+        | "cuda_device::float::add_rp_f64" => Some("v1:i0437"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
+        | "cuda_device::float::add_rp_ftz_f32" => Some("v1:i0451"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
+        | "cuda_device::float::add_rp_ftz_sat_f32" => Some("v1:i0453"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
+        | "cuda_device::float::add_rp_sat_f32" => Some("v1:i0452"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
+        | "cuda_device::float::add_rz_f32" => Some("v1:i0442"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
+        | "cuda_device::float::add_rz_f64" => Some("v1:i0435"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
+        | "cuda_device::float::add_rz_ftz_f32" => Some("v1:i0443"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
+        | "cuda_device::float::add_rz_ftz_sat_f32" => Some("v1:i0445"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
+        | "cuda_device::float::add_rz_sat_f32" => Some("v1:i0444"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040" | "cuda_device::warp::all_sync" => {
+            Some("v1:i0040")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041" | "cuda_device::warp::any_sync" => {
+            Some("v1:i0041")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
+        | "cuda_device::warp::ballot_sync" => Some("v1:i0042"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
+        | "cuda_device::cluster::barrier_cluster_arrive" => Some("v1:i0277"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
+        | "cuda_device::cluster::barrier_cluster_arrive_aligned" => Some("v1:i0278"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
+        | "cuda_device::cluster::barrier_cluster_arrive_relaxed" => Some("v1:i0279"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
+        | "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned" => Some("v1:i0280"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
+        | "cuda_device::cluster::barrier_cluster_wait" => Some("v1:i0281"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
+        | "cuda_device::cluster::barrier_cluster_wait_aligned" => Some("v1:i0282"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
+        | "cuda_device::barrier::barrier_cta_arrive" => Some("v1:i0885"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
+        | "cuda_device::barrier::barrier_cta_arrive_aligned" => Some("v1:i0886"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
+        | "cuda_device::barrier::barrier_cta_sync" => Some("v1:i0883"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
+        | "cuda_device::barrier::barrier_cta_sync_aligned" => Some("v1:i0884"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
+        | "cuda_device::thread::blockDim_x"
+        | "cuda_device::blockDim_x" => Some("v1:i0003"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
+        | "cuda_device::thread::blockDim_y"
+        | "cuda_device::blockDim_y" => Some("v1:i0007"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
+        | "cuda_device::thread::blockDim_z"
+        | "cuda_device::blockDim_z" => Some("v1:i0011"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
+        | "cuda_device::thread::blockIdx_x"
+        | "cuda_device::blockIdx_x" => Some("v1:i0002"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
+        | "cuda_device::thread::blockIdx_y"
+        | "cuda_device::blockIdx_y" => Some("v1:i0006"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
+        | "cuda_device::thread::blockIdx_z"
+        | "cuda_device::blockIdx_z" => Some("v1:i0010"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
+        | "cuda_device::debug::breakpoint" => Some("v1:i0296"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
+        | "cuda_device::clc::clc_query_get_first_ctaid_x" => Some("v1:i0325"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
+        | "cuda_device::clc::clc_query_get_first_ctaid_y" => Some("v1:i0326"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
+        | "cuda_device::clc::clc_query_get_first_ctaid_z" => Some("v1:i0327"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
+        | "cuda_device::clc::clc_query_is_canceled" => Some("v1:i0324"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
+        | "cuda_device::clc::clc_try_cancel" => Some("v1:i0322"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
+        | "cuda_device::clc::clc_try_cancel_multicast" => Some("v1:i0323"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283" | "cuda_device::debug::clock" => {
+            Some("v1:i0283")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284" | "cuda_device::debug::clock64" => {
+            Some("v1:i0284")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276" => Some("v1:i0276"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
+        | "cuda_device::cluster::cluster_ctaidX" => Some("v1:i0263"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
+        | "cuda_device::cluster::cluster_ctaidY" => Some("v1:i0264"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
+        | "cuda_device::cluster::cluster_ctaidZ" => Some("v1:i0265"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275" => Some("v1:i0275"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
+        | "cuda_device::cluster::cluster_nctaidX" => Some("v1:i0266"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
+        | "cuda_device::cluster::cluster_nctaidY" => Some("v1:i0267"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
+        | "cuda_device::cluster::cluster_nctaidZ" => Some("v1:i0268"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
+        | "cuda_device::cluster::__cluster_grid_dimX" => Some("v1:i0272"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
+        | "cuda_device::cluster::__cluster_grid_dimY" => Some("v1:i0273"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
+        | "cuda_device::cluster::__cluster_grid_dimZ" => Some("v1:i0274"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
+        | "cuda_device::cluster::__cluster_idxX" => Some("v1:i0269"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
+        | "cuda_device::cluster::__cluster_idxY" => Some("v1:i0270"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
+        | "cuda_device::cluster::__cluster_idxZ" => Some("v1:i0271"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
+        | "cuda_device::float::cos_approx_f32" => Some("v1:i0784"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
+        | "cuda_device::float::cos_approx_ftz_f32" => Some("v1:i0785"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
+        | "cuda_device::tma::cp_async_bulk_commit_group" => Some("v1:i0340"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2" => Some("v1:i0888"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint" => Some("v1:i0917"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2" => Some("v1:i0889"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint" => Some("v1:i0918"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2" => Some("v1:i0890"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint" => Some("v1:i0919"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2" => Some("v1:i0891"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint" => Some("v1:i0920"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2" => Some("v1:i0892"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint" => Some("v1:i0921"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2" => Some("v1:i0893"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint" => {
+            Some("v1:i0922")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
+        | "cuda_device::tma::cp_async_bulk_tensor_1d_g2s" => Some("v1:i0328"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
+        | "cuda_device::tma::cp_async_bulk_tensor_1d_s2g" => Some("v1:i0335"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
+        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s" => Some("v1:i0329"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
+        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast" => Some("v1:i0330"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
+        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2" => Some("v1:i0331"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
+        | "cuda_device::tma::cp_async_bulk_tensor_2d_s2g" => Some("v1:i0336"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
+        | "cuda_device::tma::cp_async_bulk_tensor_3d_g2s" => Some("v1:i0332"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
+        | "cuda_device::tma::cp_async_bulk_tensor_3d_s2g" => Some("v1:i0337"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
+        | "cuda_device::tma::cp_async_bulk_tensor_4d_g2s" => Some("v1:i0333"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
+        | "cuda_device::tma::cp_async_bulk_tensor_4d_s2g" => Some("v1:i0338"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
+        | "cuda_device::tma::cp_async_bulk_tensor_5d_g2s" => Some("v1:i0334"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
+        | "cuda_device::tma::cp_async_bulk_tensor_5d_s2g" => Some("v1:i0339"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d" => Some("v1:i0928"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d" => Some("v1:i0929"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d" => Some("v1:i0930"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d" => Some("v1:i0923"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d" => Some("v1:i0924"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d" => Some("v1:i0925"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d" => Some("v1:i0926"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d" => Some("v1:i0927"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d" => Some("v1:i0936"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d" => Some("v1:i0937"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d" => Some("v1:i0938"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d" => Some("v1:i0931"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d" => Some("v1:i0932"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d" => Some("v1:i0933"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d" => Some("v1:i0934"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d" => Some("v1:i0935"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d" => Some("v1:i0944"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d" => Some("v1:i0945"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d" => Some("v1:i0946"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d" => Some("v1:i0939"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d" => Some("v1:i0940"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d" => Some("v1:i0941"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d" => Some("v1:i0942"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d" => Some("v1:i0943"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d" => Some("v1:i0952"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d" => Some("v1:i0953"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d" => Some("v1:i0954"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d" => Some("v1:i0947"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d" => Some("v1:i0948"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d" => Some("v1:i0949"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d" => Some("v1:i0950"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d" => Some("v1:i0951"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d" => Some("v1:i0960"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d" => Some("v1:i0961"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d" => Some("v1:i0962"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d" => Some("v1:i0955"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d" => Some("v1:i0956"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d" => Some("v1:i0957"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d" => Some("v1:i0958"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d" => Some("v1:i0959"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d" => Some("v1:i0968"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d" => Some("v1:i0969"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d" => Some("v1:i0970"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d" => Some("v1:i0963"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d" => Some("v1:i0964"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d" => Some("v1:i0965"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d" => Some("v1:i0966"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d" => Some("v1:i0967"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d" => Some("v1:i0976"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d" => Some("v1:i0977"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d" => Some("v1:i0978"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d" => Some("v1:i0971"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d" => Some("v1:i0972"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d" => Some("v1:i0973"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d" => Some("v1:i0974"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d" => Some("v1:i0975"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d" => Some("v1:i0984"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d" => Some("v1:i0985"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d" => Some("v1:i0986"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d" => Some("v1:i0979"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d" => Some("v1:i0980"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d" => Some("v1:i0981"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d" => Some("v1:i0982"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d" => Some("v1:i0983"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
+        | "cuda_device::tma::cp_async_bulk_wait_group" => Some("v1:i0341"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
+        | "cuda_device::tma::cp_async_bulk_wait_group_read" => Some("v1:i0342"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
+        | "cuda_device::async_copy::cp_async_ca_16" => Some("v1:i0090"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
+        | "cuda_device::async_copy::cp_async_ca_4" => Some("v1:i0086"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
+        | "cuda_device::async_copy::cp_async_ca_8" => Some("v1:i0088"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
+        | "cuda_device::async_copy::cp_async_ca_zfill_16" => Some("v1:i0091"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
+        | "cuda_device::async_copy::cp_async_ca_zfill_4" => Some("v1:i0087"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
+        | "cuda_device::async_copy::cp_async_ca_zfill_8" => Some("v1:i0089"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
+        | "cuda_device::async_copy::cp_async_cg_16" => Some("v1:i0092"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
+        | "cuda_device::async_copy::cp_async_cg_zfill_16" => Some("v1:i0093"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
+        | "cuda_device::async_copy::cp_async_commit_group" => Some("v1:i0094"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
+        | "cuda_device::async_copy::cp_async_mbarrier_arrive" => Some("v1:i0101"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
+        | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc" => Some("v1:i0103"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
+        | "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared" => Some("v1:i0104"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
+        | "cuda_device::async_copy::cp_async_mbarrier_arrive_shared" => Some("v1:i0102"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
+        | "cuda_device::async_copy::cp_async_wait_all" => Some("v1:i0095"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
+        | "cuda_device::async_copy::cp_async_wait_group" => Some("v1:i0096"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
+        | "cuda_device::convert::cvt_f16x2_f32" => Some("v1:i0081"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
+        | "cuda_device::convert::cvt_bf16x2_f32" => Some("v1:i0071"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
+        | "cuda_device::convert::cvt_rn_f16x2_e4m3x2" => Some("v1:i0826"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
+        | "cuda_device::convert::cvt_rn_f16x2_e5m2x2" => Some("v1:i0828"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
+        | "cuda_device::convert::cvt_rn_relu_bf16x2_f32" => Some("v1:i0084"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
+        | "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2" => Some("v1:i0827"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
+        | "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2" => Some("v1:i0829"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
+        | "cuda_device::convert::cvt_rn_relu_f16x2_f32" => Some("v1:i0083"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
+        | "cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32" => Some("v1:i0373"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
+        | "cuda_device::convert::cvt_rn_relu_tf32_f32" => Some("v1:i0371"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
+        | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2" => Some("v1:i0822"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
+        | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32" => Some("v1:i0259"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
+        | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2" => Some("v1:i0824"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
+        | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32" => Some("v1:i0261"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
+        | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2" => Some("v1:i0823"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
+        | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32" => Some("v1:i0260"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
+        | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2" => Some("v1:i0825"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
+        | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32" => Some("v1:i0262"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
+        | "cuda_device::convert::cvt_rn_satfinite_tf32_f32" => Some("v1:i0372"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
+        | "cuda_device::convert::cvt_rn_tf32_f32" => Some("v1:i0370"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
+        | "cuda_device::convert::cvt_rna_satfinite_tf32_f32" => Some("v1:i0369"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
+        | "cuda_device::convert::cvt_rna_tf32_f32" => Some("v1:i0368"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
+        | "cuda_device::convert::cvt_rz_bf16x2_f32" => Some("v1:i0085"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
+        | "cuda_device::convert::cvt_rz_f16x2_f32" => Some("v1:i0082"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
+        | "cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32" => Some("v1:i0377"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
+        | "cuda_device::convert::cvt_rz_relu_tf32_f32" => Some("v1:i0375"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
+        | "cuda_device::convert::cvt_rz_satfinite_tf32_f32" => Some("v1:i0376"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
+        | "cuda_device::convert::cvt_rz_tf32_f32" => Some("v1:i0374"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
+        | "cuda_device::float::div_rm_f32" => Some("v1:i0414"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
+        | "cuda_device::float::div_rm_f64" => Some("v1:i0396"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
+        | "cuda_device::float::div_rm_ftz_f32" => Some("v1:i0415"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
+        | "cuda_device::float::div_rn_f32" => Some("v1:i0410"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
+        | "cuda_device::float::div_rn_f64" => Some("v1:i0394"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
+        | "cuda_device::float::div_rn_ftz_f32" => Some("v1:i0411"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
+        | "cuda_device::float::div_rp_f32" => Some("v1:i0416"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
+        | "cuda_device::float::div_rp_f64" => Some("v1:i0397"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
+        | "cuda_device::float::div_rp_ftz_f32" => Some("v1:i0417"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
+        | "cuda_device::float::div_rz_f32" => Some("v1:i0412"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
+        | "cuda_device::float::div_rz_f64" => Some("v1:i0395"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
+        | "cuda_device::float::div_rz_ftz_f32" => Some("v1:i0413"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
+        | "cuda_device::dotprod::dp2a_s32" => Some("v1:i0032"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
+        | "cuda_device::dotprod::dp2a_u32" => Some("v1:i0033"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
+        | "cuda_device::dotprod::dp4a_s32" => Some("v1:i0030"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
+        | "cuda_device::dotprod::dp4a_u32" => Some("v1:i0031"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
+        | "cuda_device::cluster::dsmem_read_u32" => Some("v1:i0321"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
+        | "cuda_device::shared::dynamic_smem_size" => Some("v1:i0293"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
+        | "cuda_device::warp::elect_sync" => Some("v1:i0367"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286" | "cuda_device::grid::envreg1" => {
+            Some("v1:i0286")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287" | "cuda_device::grid::envreg2" => {
+            Some("v1:i0287")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
+        | "cuda_device::float::ex2_approx_f16" => Some("v1:i1016"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
+        | "cuda_device::float::ex2_approx_f32" => Some("v1:i0819"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
+        | "cuda_device::float::ex2_approx_ftz_f32" => Some("v1:i0820"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
+        | "cuda_device::barrier::fence_mbarrier_init_release_cluster" => Some("v1:i0313"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
+        | "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster" => {
+            Some("v1:i0315")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
+        | "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster" => {
+            Some("v1:i0314")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
+        | "cuda_device::barrier::fence_proxy_async_shared_cta" => Some("v1:i0312"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster" => Some("v1:i0905"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta" => Some("v1:i0906"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu" => Some("v1:i0907"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system" => Some("v1:i0908"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster" => Some("v1:i0909"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_release_cta" => Some("v1:i0910"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu" => Some("v1:i0911"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_release_system" => Some("v1:i0912"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
+        | "cuda_device::bf16x2::fma_bf16x2" => Some("v1:i0062"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
+        | "cuda_device::f16x2::fma_f16x2" => Some("v1:i0072"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
+        | "cuda_device::f32x2::fma_f32x2" => Some("v1:i1001"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
+        | "cuda_device::f16x2::fma_ftz_f16x2" => Some("v1:i0854"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
+        | "cuda_device::f32x2::fma_ftz_f32x2" => Some("v1:i1002"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
+        | "cuda_device::f16x2::fma_ftz_relu_f16x2" => Some("v1:i0857"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
+        | "cuda_device::f16x2::fma_ftz_sat_f16x2" => Some("v1:i0856"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
+        | "cuda_device::bf16x2::fma_relu_bf16x2" => Some("v1:i0063"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
+        | "cuda_device::f16x2::fma_relu_f16x2" => Some("v1:i0073"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
+        | "cuda_device::float::fma_rm_f32" => Some("v1:i0426"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
+        | "cuda_device::float::fma_rm_f64" => Some("v1:i0400"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
+        | "cuda_device::float::fma_rm_ftz_f32" => Some("v1:i0427"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
+        | "cuda_device::float::fma_rm_ftz_sat_f32" => Some("v1:i0429"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
+        | "cuda_device::float::fma_rm_sat_f32" => Some("v1:i0428"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
+        | "cuda_device::float::fma_rn_f32" => Some("v1:i0418"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
+        | "cuda_device::float::fma_rn_f64" => Some("v1:i0398"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
+        | "cuda_device::float::fma_rn_ftz_f32" => Some("v1:i0419"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
+        | "cuda_device::float::fma_rn_ftz_sat_f32" => Some("v1:i0421"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
+        | "cuda_device::float::fma_rn_sat_f32" => Some("v1:i0420"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
+        | "cuda_device::float::fma_rp_f32" => Some("v1:i0430"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
+        | "cuda_device::float::fma_rp_f64" => Some("v1:i0401"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
+        | "cuda_device::float::fma_rp_ftz_f32" => Some("v1:i0431"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
+        | "cuda_device::float::fma_rp_ftz_sat_f32" => Some("v1:i0433"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
+        | "cuda_device::float::fma_rp_sat_f32" => Some("v1:i0432"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
+        | "cuda_device::float::fma_rz_f32" => Some("v1:i0422"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
+        | "cuda_device::float::fma_rz_f64" => Some("v1:i0399"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
+        | "cuda_device::float::fma_rz_ftz_f32" => Some("v1:i0423"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
+        | "cuda_device::float::fma_rz_ftz_sat_f32" => Some("v1:i0425"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
+        | "cuda_device::float::fma_rz_sat_f32" => Some("v1:i0424"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
+        | "cuda_device::f16x2::fma_sat_f16x2" => Some("v1:i0855"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
+        | "cuda_device::debug::globaltimer" => Some("v1:i0285"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
+        | "cuda_device::grid::dependency::trigger_dependents" => Some("v1:i0913"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
+        | "cuda_device::grid::dependency::wait" => Some("v1:i0914"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
+        | "cuda_device::thread::gridDim_x"
+        | "cuda_device::gridDim_x" => Some("v1:i0004"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
+        | "cuda_device::thread::gridDim_y"
+        | "cuda_device::gridDim_y" => Some("v1:i0008"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
+        | "cuda_device::thread::gridDim_z"
+        | "cuda_device::gridDim_z" => Some("v1:i0012"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
+        | "cuda_device::thread::gridid"
+        | "cuda_device::gridid" => Some("v1:i0290"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016" | "cuda_device::warp::lane_id" => {
+            Some("v1:i0016")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
+        | "cuda_device::warp::lanemask_eq" => Some("v1:i0037"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
+        | "cuda_device::warp::lanemask_ge" => Some("v1:i0038"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
+        | "cuda_device::warp::lanemask_gt" => Some("v1:i0039"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
+        | "cuda_device::warp::lanemask_le" => Some("v1:i0036"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
+        | "cuda_device::warp::lanemask_lt" => Some("v1:i0035"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378" => Some("v1:i0378"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379" => Some("v1:i0379"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380" => Some("v1:i0380"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381" => Some("v1:i0381"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382" => Some("v1:i0382"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383" => Some("v1:i0383"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384" => Some("v1:i0384"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385" => Some("v1:i0385"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
+        | "cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64" => Some("v1:i0386"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387" => Some("v1:i0387"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
+        | "cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64" => Some("v1:i0388"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389" => Some("v1:i0389"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
+        | "cuda_device::wmma::ldmatrix_x1" => Some("v1:i0025"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
+        | "cuda_device::wmma::ldmatrix_x1_trans" => Some("v1:i0026"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
+        | "cuda_device::wmma::ldmatrix_x2" => Some("v1:i0027"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
+        | "cuda_device::wmma::ldmatrix_x2_trans" => Some("v1:i0028"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
+        | "cuda_device::wmma::ldmatrix_x4" => Some("v1:i0013"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
+        | "cuda_device::wmma::ldmatrix_x4_trans" => Some("v1:i0029"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
+        | "cuda_device::float::lg2_approx_f32" => Some("v1:i0786"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
+        | "cuda_device::float::lg2_approx_ftz_f32" => Some("v1:i0787"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
+        | "cuda_device::cluster::map_shared_rank"
+        | "cuda_device::cluster::map_shared_rank_mut" => Some("v1:i0320"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
+        | "cuda_device::warp::match_all_i64_sync" => Some("v1:i0048"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
+        | "cuda_device::warp::match_all_sync" => Some("v1:i0047"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
+        | "cuda_device::warp::match_any_i64_sync" => Some("v1:i0046"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
+        | "cuda_device::warp::match_any_sync" => Some("v1:i0045"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850" | "cuda_device::bf16::max_bf16" => {
+            Some("v1:i0850")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
+        | "cuda_device::bf16x2::max_bf16x2" => Some("v1:i0068"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842" | "cuda_device::f16::max_f16" => {
+            Some("v1:i0842")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
+        | "cuda_device::f16x2::max_f16x2" => Some("v1:i0078"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
+        | "cuda_device::f16::max_ftz_f16" => Some("v1:i0843"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
+        | "cuda_device::f16x2::max_ftz_f16x2" => Some("v1:i0564"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
+        | "cuda_device::f16::max_ftz_nan_f16" => Some("v1:i0845"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
+        | "cuda_device::f16x2::max_ftz_nan_f16x2" => Some("v1:i0565"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
+        | "cuda_device::f16::max_ftz_nan_xorsign_abs_f16" => Some("v1:i0849"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
+        | "cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2" => Some("v1:i0567"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
+        | "cuda_device::float::max_ftz_nan_xorsign_abs_f32" => Some("v1:i0566"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
+        | "cuda_device::f16::max_ftz_xorsign_abs_f16" => Some("v1:i0847"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
+        | "cuda_device::f16x2::max_ftz_xorsign_abs_f16x2" => Some("v1:i0569"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
+        | "cuda_device::float::max_ftz_xorsign_abs_f32" => Some("v1:i0568"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
+        | "cuda_device::bf16::max_nan_bf16" => Some("v1:i0851"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
+        | "cuda_device::bf16x2::max_nan_bf16x2" => Some("v1:i0570"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
+        | "cuda_device::f16::max_nan_f16" => Some("v1:i0844"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
+        | "cuda_device::f16x2::max_nan_f16x2" => Some("v1:i0571"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
+        | "cuda_device::bf16::max_nan_xorsign_abs_bf16" => Some("v1:i0853"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
+        | "cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2" => Some("v1:i0572"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
+        | "cuda_device::f16::max_nan_xorsign_abs_f16" => Some("v1:i0848"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
+        | "cuda_device::f16x2::max_nan_xorsign_abs_f16x2" => Some("v1:i0574"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
+        | "cuda_device::float::max_nan_xorsign_abs_f32" => Some("v1:i0573"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
+        | "cuda_device::i16x2::max_relu_s16x2" => Some("v1:i0994"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
+        | "cuda_device::int::max_relu_s32" => Some("v1:i0988"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
+        | "cuda_device::i16x2::max_s16x2" => Some("v1:i0990"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
+        | "cuda_device::i16x2::max_u16x2" => Some("v1:i0992"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
+        | "cuda_device::bf16::max_xorsign_abs_bf16" => Some("v1:i0852"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
+        | "cuda_device::bf16x2::max_xorsign_abs_bf16x2" => Some("v1:i0575"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
+        | "cuda_device::f16::max_xorsign_abs_f16" => Some("v1:i0846"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
+        | "cuda_device::f16x2::max_xorsign_abs_f16x2" => Some("v1:i0577"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
+        | "cuda_device::float::max_xorsign_abs_f32" => Some("v1:i0576"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
+        | "cuda_device::barrier::mbarrier_arrive" => Some("v1:i0098"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
+        | "cuda_device::barrier::mbarrier_arrive_cluster" => Some("v1:i0308"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
+        | "cuda_device::barrier::mbarrier_arrive_expect_tx" => Some("v1:i0306"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
+        | "cuda_device::barrier::mbarrier_arrive_expect_tx_cluster" => Some("v1:i0307"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
+        | "cuda_device::barrier::mbarrier_init" => Some("v1:i0097"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
+        | "cuda_device::barrier::mbarrier_inval" => Some("v1:i0100"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
+        | "cuda_device::barrier::mbarrier_test_wait" => Some("v1:i0099"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
+        | "cuda_device::barrier::mbarrier_try_wait" => Some("v1:i0309"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
+        | "cuda_device::barrier::mbarrier_try_wait_parity" => Some("v1:i0310"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
+        | "cuda_device::barrier::mbarrier_try_wait_parity_cluster" => Some("v1:i0311"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838" | "cuda_device::bf16::min_bf16" => {
+            Some("v1:i0838")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
+        | "cuda_device::bf16x2::min_bf16x2" => Some("v1:i0067"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830" | "cuda_device::f16::min_f16" => {
+            Some("v1:i0830")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
+        | "cuda_device::f16x2::min_f16x2" => Some("v1:i0077"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
+        | "cuda_device::f16::min_ftz_f16" => Some("v1:i0831"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
+        | "cuda_device::f16x2::min_ftz_f16x2" => Some("v1:i0550"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
+        | "cuda_device::f16::min_ftz_nan_f16" => Some("v1:i0833"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
+        | "cuda_device::f16x2::min_ftz_nan_f16x2" => Some("v1:i0551"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
+        | "cuda_device::f16::min_ftz_nan_xorsign_abs_f16" => Some("v1:i0837"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
+        | "cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2" => Some("v1:i0553"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
+        | "cuda_device::float::min_ftz_nan_xorsign_abs_f32" => Some("v1:i0552"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
+        | "cuda_device::f16::min_ftz_xorsign_abs_f16" => Some("v1:i0835"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
+        | "cuda_device::f16x2::min_ftz_xorsign_abs_f16x2" => Some("v1:i0555"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
+        | "cuda_device::float::min_ftz_xorsign_abs_f32" => Some("v1:i0554"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
+        | "cuda_device::bf16::min_nan_bf16" => Some("v1:i0839"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
+        | "cuda_device::bf16x2::min_nan_bf16x2" => Some("v1:i0556"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
+        | "cuda_device::f16::min_nan_f16" => Some("v1:i0832"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
+        | "cuda_device::f16x2::min_nan_f16x2" => Some("v1:i0557"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
+        | "cuda_device::bf16::min_nan_xorsign_abs_bf16" => Some("v1:i0841"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
+        | "cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2" => Some("v1:i0558"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
+        | "cuda_device::f16::min_nan_xorsign_abs_f16" => Some("v1:i0836"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
+        | "cuda_device::f16x2::min_nan_xorsign_abs_f16x2" => Some("v1:i0560"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
+        | "cuda_device::float::min_nan_xorsign_abs_f32" => Some("v1:i0559"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
+        | "cuda_device::i16x2::min_relu_s16x2" => Some("v1:i0993"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
+        | "cuda_device::int::min_relu_s32" => Some("v1:i0987"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
+        | "cuda_device::i16x2::min_s16x2" => Some("v1:i0989"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
+        | "cuda_device::i16x2::min_u16x2" => Some("v1:i0991"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
+        | "cuda_device::bf16::min_xorsign_abs_bf16" => Some("v1:i0840"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
+        | "cuda_device::bf16x2::min_xorsign_abs_bf16x2" => Some("v1:i0561"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
+        | "cuda_device::f16::min_xorsign_abs_f16" => Some("v1:i0834"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
+        | "cuda_device::f16x2::min_xorsign_abs_f16x2" => Some("v1:i0563"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
+        | "cuda_device::float::min_xorsign_abs_f32" => Some("v1:i0562"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
+        | "cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc" => Some("v1:i0161"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
+        | "cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc" => Some("v1:i0158"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
+        | "cuda_device::wmma::mma_m16n8k16_f16_f16" => Some("v1:i0524"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
+        | "cuda_device::wmma::mma_m16n8k16_f32_bf16" => Some("v1:i0105"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
+        | "cuda_device::wmma::mma_m16n8k16_f32_f16" => Some("v1:i0106"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3" => Some("v1:i0504"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2" => Some("v1:i0505"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3" => Some("v1:i0506"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2" => Some("v1:i0507"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3" => Some("v1:i0508"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2" => Some("v1:i0509"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3" => Some("v1:i0510"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2" => Some("v1:i0511"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
+        | "cuda_device::wmma::mma_m16n8k16_s32_s8" => Some("v1:i0110"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
+        | "cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite" => Some("v1:i0117"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
+        | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8" => Some("v1:i0111"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
+        | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite" => Some("v1:i0118"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
+        | "cuda_device::wmma::mma_m16n8k16_s32_u8" => Some("v1:i0112"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
+        | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8" => Some("v1:i0113"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
+        | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite" => Some("v1:i0120"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
+        | "cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite" => Some("v1:i0119"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
+        | "cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc" => Some("v1:i0162"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
+        | "cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc" => Some("v1:i0159"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1" => Some("v1:i0479"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3" => Some("v1:i0480"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2" => Some("v1:i0481"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3" => Some("v1:i0482"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2" => Some("v1:i0483"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1" => Some("v1:i0484"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3" => Some("v1:i0485"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2" => Some("v1:i0486"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3" => Some("v1:i0487"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2" => Some("v1:i0488"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1" => Some("v1:i0489"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3" => Some("v1:i0490"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2" => Some("v1:i0491"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3" => Some("v1:i0492"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2" => Some("v1:i0493"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1" => Some("v1:i0494"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3" => Some("v1:i0495"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2" => Some("v1:i0496"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3" => Some("v1:i0497"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2" => Some("v1:i0498"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1" => Some("v1:i0499"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3" => Some("v1:i0500"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2" => Some("v1:i0501"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3" => Some("v1:i0502"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2" => Some("v1:i0503"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1" => Some("v1:i0454"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3" => Some("v1:i0455"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2" => Some("v1:i0456"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3" => Some("v1:i0457"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2" => Some("v1:i0458"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1" => Some("v1:i0459"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3" => Some("v1:i0460"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2" => Some("v1:i0461"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3" => Some("v1:i0462"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2" => Some("v1:i0463"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1" => Some("v1:i0464"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3" => Some("v1:i0465"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2" => Some("v1:i0466"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3" => Some("v1:i0467"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2" => Some("v1:i0468"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1" => Some("v1:i0469"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3" => Some("v1:i0470"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2" => Some("v1:i0471"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3" => Some("v1:i0472"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2" => Some("v1:i0473"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1" => Some("v1:i0474"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3" => Some("v1:i0475"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2" => Some("v1:i0476"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3" => Some("v1:i0477"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2" => Some("v1:i0478"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3" => Some("v1:i0512"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2" => Some("v1:i0513"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3" => Some("v1:i0514"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2" => Some("v1:i0515"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3" => Some("v1:i0516"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2" => Some("v1:i0517"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3" => Some("v1:i0518"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2" => Some("v1:i0519"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1" => Some("v1:i0858"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3" => Some("v1:i0859"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2" => Some("v1:i0860"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3" => Some("v1:i0861"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2" => Some("v1:i0862"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1" => Some("v1:i0863"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3" => Some("v1:i0864"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2" => Some("v1:i0865"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3" => Some("v1:i0866"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2" => Some("v1:i0867"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1" => Some("v1:i0868"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3" => Some("v1:i0869"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2" => Some("v1:i0870"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3" => Some("v1:i0871"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2" => Some("v1:i0872"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1" => Some("v1:i0873"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3" => Some("v1:i0874"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2" => Some("v1:i0875"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3" => Some("v1:i0876"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2" => Some("v1:i0877"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1" => Some("v1:i0878"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3" => Some("v1:i0879"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2" => Some("v1:i0880"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3" => Some("v1:i0881"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2" => Some("v1:i0882"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s4" => Some("v1:i0141"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite" => Some("v1:i0149"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4" => Some("v1:i0142"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite" => Some("v1:i0150"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s8" => Some("v1:i0108"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite" => Some("v1:i0121"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8" => Some("v1:i0114"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite" => Some("v1:i0122"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u4" => Some("v1:i0143"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4" => Some("v1:i0144"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite" => Some("v1:i0152"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite" => Some("v1:i0151"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u8" => Some("v1:i0115"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8" => Some("v1:i0116"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite" => Some("v1:i0124"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite" => Some("v1:i0123"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
+        | "cuda_device::wmma::mma_m16n8k4_f32_tf32" => Some("v1:i0520"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
+        | "cuda_device::wmma::mma_m16n8k64_s32_s4" => Some("v1:i0145"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
+        | "cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite" => Some("v1:i0153"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
+        | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4" => Some("v1:i0146"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
+        | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite" => Some("v1:i0154"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
+        | "cuda_device::wmma::mma_m16n8k64_s32_u4" => Some("v1:i0147"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
+        | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4" => Some("v1:i0148"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
+        | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite" => Some("v1:i0156"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
+        | "cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite" => Some("v1:i0155"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
+        | "cuda_device::wmma::mma_m16n8k8_f16_f16" => Some("v1:i0521"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
+        | "cuda_device::wmma::mma_m16n8k8_f32_bf16" => Some("v1:i0522"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
+        | "cuda_device::wmma::mma_m16n8k8_f32_f16" => Some("v1:i0523"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
+        | "cuda_device::wmma::mma_m16n8k8_f32_tf32" => Some("v1:i0107"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
+        | "cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc" => Some("v1:i0160"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
+        | "cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc" => Some("v1:i0157"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
+        | "cuda_device::wmma::mma_m8n8k16_s32_s8" => Some("v1:i0125"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
+        | "cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite" => Some("v1:i0129"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
+        | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8" => Some("v1:i0126"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
+        | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite" => Some("v1:i0130"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
+        | "cuda_device::wmma::mma_m8n8k16_s32_u8" => Some("v1:i0127"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
+        | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8" => Some("v1:i0128"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
+        | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite" => Some("v1:i0132"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
+        | "cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite" => Some("v1:i0131"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
+        | "cuda_device::wmma::mma_m8n8k32_s32_s4" => Some("v1:i0133"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
+        | "cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite" => Some("v1:i0137"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
+        | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4" => Some("v1:i0134"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
+        | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite" => Some("v1:i0138"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
+        | "cuda_device::wmma::mma_m8n8k32_s32_u4" => Some("v1:i0135"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
+        | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4" => Some("v1:i0136"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
+        | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite" => Some("v1:i0140"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
+        | "cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite" => Some("v1:i0139"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
+        | "cuda_device::wmma::mma_m8n8k4_f64" => Some("v1:i0109"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4" => Some("v1:i0219"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite" => Some("v1:i0223"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4" => Some("v1:i0220"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite" => Some("v1:i0224"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4" => Some("v1:i0221"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4" => Some("v1:i0222"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite" => Some("v1:i0226"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite" => Some("v1:i0225"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8" => Some("v1:i0163"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite" => Some("v1:i0167"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8" => Some("v1:i0164"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite" => Some("v1:i0168"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8" => Some("v1:i0165"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8" => Some("v1:i0166"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite" => Some("v1:i0170"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite" => Some("v1:i0169"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4" => Some("v1:i0211"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite" => Some("v1:i0215"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4" => Some("v1:i0212"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite" => Some("v1:i0216"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8" => Some("v1:i0187"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite" => Some("v1:i0191"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8" => Some("v1:i0188"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite" => Some("v1:i0192"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4" => Some("v1:i0213"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4" => Some("v1:i0214"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite" => Some("v1:i0218"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite" => Some("v1:i0217"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8" => Some("v1:i0189"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8" => Some("v1:i0190"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite" => Some("v1:i0194"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite" => Some("v1:i0193"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4" => Some("v1:i0203"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite" => {
+            Some("v1:i0207")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4" => Some("v1:i0204"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite" => {
+            Some("v1:i0208")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4" => Some("v1:i0205"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4" => Some("v1:i0206"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite" => {
+            Some("v1:i0210")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite" => {
+            Some("v1:i0209")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" => Some("v1:i0171"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite" => {
+            Some("v1:i0175")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8" => Some("v1:i0172"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite" => {
+            Some("v1:i0176")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8" => Some("v1:i0173"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8" => Some("v1:i0174"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite" => {
+            Some("v1:i0178")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite" => {
+            Some("v1:i0177")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16" => {
+            Some("v1:i0525")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16" => {
+            Some("v1:i0526")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16" => {
+            Some("v1:i0527")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16" => {
+            Some("v1:i0528")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16" => {
+            Some("v1:i0529")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16" => {
+            Some("v1:i0530")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16" => {
+            Some("v1:i0531")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16" => {
+            Some("v1:i0532")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16" => {
+            Some("v1:i0533")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16" => {
+            Some("v1:i0534")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16" => {
+            Some("v1:i0535")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16" => {
+            Some("v1:i0536")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16" => {
+            Some("v1:i0537")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16" => {
+            Some("v1:i0538")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16" => {
+            Some("v1:i0539")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16" => {
+            Some("v1:i0540")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16" => {
+            Some("v1:i0541")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16" => {
+            Some("v1:i0542")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16" => {
+            Some("v1:i0543")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16" => {
+            Some("v1:i0544")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16" => {
+            Some("v1:i0545")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16" => {
+            Some("v1:i0546")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16" => {
+            Some("v1:i0547")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16" => {
+            Some("v1:i0548")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16" => {
+            Some("v1:i0549")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32" => {
+            Some("v1:i0227")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32" => {
+            Some("v1:i0228")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32" => {
+            Some("v1:i0229")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32" => {
+            Some("v1:i0230")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32" => {
+            Some("v1:i0231")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32" => {
+            Some("v1:i0232")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32" => {
+            Some("v1:i0233")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32" => {
+            Some("v1:i0234")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32" => {
+            Some("v1:i0235")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32" => {
+            Some("v1:i0236")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32" => {
+            Some("v1:i0237")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32" => {
+            Some("v1:i0238")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32" => {
+            Some("v1:i0239")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32" => {
+            Some("v1:i0240")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32" => {
+            Some("v1:i0241")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32" => {
+            Some("v1:i0242")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32" => {
+            Some("v1:i0243")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32" => {
+            Some("v1:i0244")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32" => {
+            Some("v1:i0245")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32" => {
+            Some("v1:i0246")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32" => {
+            Some("v1:i0247")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32" => {
+            Some("v1:i0248")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32" => {
+            Some("v1:i0249")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32" => {
+            Some("v1:i0250")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32" => {
+            Some("v1:i0251")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4" => Some("v1:i0195"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite" => {
+            Some("v1:i0199")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4" => Some("v1:i0196"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite" => {
+            Some("v1:i0200")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8" => Some("v1:i0179"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite" => {
+            Some("v1:i0183")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8" => Some("v1:i0180"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite" => {
+            Some("v1:i0184")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4" => Some("v1:i0197"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4" => Some("v1:i0198"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite" => {
+            Some("v1:i0202")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite" => {
+            Some("v1:i0201")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8" => Some("v1:i0181"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8" => Some("v1:i0182"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" => {
+            Some("v1:i0186")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" => {
+            Some("v1:i0185")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
+        | "cuda_device::wmma::movmatrix_trans_b16" => Some("v1:i0305"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
+        | "cuda_device::bf16x2::mul_bf16x2" => Some("v1:i0066"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
+        | "cuda_device::f16x2::mul_f16x2" => Some("v1:i0076"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
+        | "cuda_device::f32x2::mul_f32x2" => Some("v1:i0999"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
+        | "cuda_device::f32x2::mul_ftz_f32x2" => Some("v1:i1000"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
+        | "cuda_device::float::mul_rm_f32" => Some("v1:i0406"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
+        | "cuda_device::float::mul_rm_f64" => Some("v1:i0392"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
+        | "cuda_device::float::mul_rm_ftz_f32" => Some("v1:i0407"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
+        | "cuda_device::float::mul_rn_f32" => Some("v1:i0402"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
+        | "cuda_device::float::mul_rn_f64" => Some("v1:i0390"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
+        | "cuda_device::float::mul_rn_ftz_f32" => Some("v1:i0403"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
+        | "cuda_device::float::mul_rp_f32" => Some("v1:i0408"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
+        | "cuda_device::float::mul_rp_f64" => Some("v1:i0393"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
+        | "cuda_device::float::mul_rp_ftz_f32" => Some("v1:i0409"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
+        | "cuda_device::float::mul_rz_f32" => Some("v1:i0404"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
+        | "cuda_device::float::mul_rz_f64" => Some("v1:i0391"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
+        | "cuda_device::float::mul_rz_ftz_f32" => Some("v1:i0405"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
+        | "cuda_device::barrier::nanosleep" => Some("v1:i0316"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
+        | "cuda_device::bf16x2::neg_bf16x2" => Some("v1:i0069"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
+        | "cuda_device::f16x2::neg_f16x2" => Some("v1:i0079"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
+        | "cuda_device::thread::nsmid"
+        | "cuda_device::nsmid" => Some("v1:i0289"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292" | "cuda_device::warp::nwarpid" => {
+            Some("v1:i0292")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
+        | "cuda_device::atomic::atom_add_bf16x2" => Some("v1:i0015"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
+        | "cuda_device::atomic::atom_add_f16x2" => Some("v1:i0014"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
+        | "cuda_device::debug::__prof_trigger" => Some("v1:i0297"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
+        | "cuda_device::tma::prefetch_tma_descriptor" => Some("v1:i0887"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252" | "cuda_device::prmt::prmt" => {
+            Some("v1:i0252")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254" | "cuda_device::prmt::prmt_b4e" => {
+            Some("v1:i0254")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256" | "cuda_device::prmt::prmt_ecl" => {
+            Some("v1:i0256")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257" | "cuda_device::prmt::prmt_ecr" => {
+            Some("v1:i0257")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253" | "cuda_device::prmt::prmt_f4e" => {
+            Some("v1:i0253")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
+        | "cuda_device::prmt::prmt_rc16" => Some("v1:i0258"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255" | "cuda_device::prmt::prmt_rc8" => {
+            Some("v1:i0255")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
+        | "cuda_device::float::rcp_approx_ftz_f32" => Some("v1:i0788"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
+        | "cuda_device::float::rcp_approx_ftz_f64" => Some("v1:i0797"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
+        | "cuda_device::float::rcp_rm_f32" => Some("v1:i0793"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
+        | "cuda_device::float::rcp_rm_f64" => Some("v1:i0800"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
+        | "cuda_device::float::rcp_rm_ftz_f32" => Some("v1:i0794"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
+        | "cuda_device::float::rcp_rn_f32" => Some("v1:i0789"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
+        | "cuda_device::float::rcp_rn_f64" => Some("v1:i0798"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
+        | "cuda_device::float::rcp_rn_ftz_f32" => Some("v1:i0790"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
+        | "cuda_device::float::rcp_rp_f32" => Some("v1:i0795"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
+        | "cuda_device::float::rcp_rp_f64" => Some("v1:i0801"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
+        | "cuda_device::float::rcp_rp_ftz_f32" => Some("v1:i0796"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
+        | "cuda_device::float::rcp_rz_f32" => Some("v1:i0791"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
+        | "cuda_device::float::rcp_rz_f64" => Some("v1:i0799"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
+        | "cuda_device::float::rcp_rz_ftz_f32" => Some("v1:i0792"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
+        | "cuda_device::warp::redux_sync_add" => Some("v1:i0017"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
+        | "cuda_device::warp::redux_sync_and" => Some("v1:i0022"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
+        | "cuda_device::warp::redux_sync_max_abs_f32" => Some("v1:i1009"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
+        | "cuda_device::warp::redux_sync_max_abs_nan_f32" => Some("v1:i1010"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
+        | "cuda_device::warp::redux_sync_max_f32" => Some("v1:i1007"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
+        | "cuda_device::warp::redux_sync_max_i32" => Some("v1:i0021"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
+        | "cuda_device::warp::redux_sync_max_nan_f32" => Some("v1:i1008"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
+        | "cuda_device::warp::redux_sync_max_u32" => Some("v1:i0020"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
+        | "cuda_device::warp::redux_sync_min_abs_f32" => Some("v1:i1005"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
+        | "cuda_device::warp::redux_sync_min_abs_nan_f32" => Some("v1:i1006"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
+        | "cuda_device::warp::redux_sync_min_f32" => Some("v1:i1003"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
+        | "cuda_device::warp::redux_sync_min_i32" => Some("v1:i0019"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
+        | "cuda_device::warp::redux_sync_min_nan_f32" => Some("v1:i1004"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
+        | "cuda_device::warp::redux_sync_min_u32" => Some("v1:i0018"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
+        | "cuda_device::warp::redux_sync_or" => Some("v1:i0023"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
+        | "cuda_device::warp::redux_sync_xor" => Some("v1:i0024"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
+        | "cuda_device::float::rsqrt_approx_f32" => Some("v1:i0802"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
+        | "cuda_device::float::rsqrt_approx_f64" => Some("v1:i0804"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
+        | "cuda_device::float::rsqrt_approx_ftz_f32" => Some("v1:i0803"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
+        | "cuda_device::thread::__setmaxnreg_dec" => Some("v1:i0916"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
+        | "cuda_device::thread::__setmaxnreg_inc" => Some("v1:i0915"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
+        | "cuda_device::warp::shuffle_down_f32_sync" => Some("v1:i0056"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
+        | "cuda_device::warp::shuffle_down_sync" => Some("v1:i0052"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
+        | "cuda_device::warp::shuffle_down_u64_sync" => Some("v1:i0060"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
+        | "cuda_device::warp::shuffle_f32_sync" => Some("v1:i0054"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
+        | "cuda_device::warp::shuffle_sync" => Some("v1:i0050"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
+        | "cuda_device::warp::shuffle_u64_sync" => Some("v1:i0058"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
+        | "cuda_device::warp::shuffle_up_f32_sync" => Some("v1:i0057"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
+        | "cuda_device::warp::shuffle_up_sync" => Some("v1:i0053"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
+        | "cuda_device::warp::shuffle_up_u64_sync" => Some("v1:i0061"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
+        | "cuda_device::warp::shuffle_xor_f32_sync" => Some("v1:i0055"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
+        | "cuda_device::warp::shuffle_xor_sync" => Some("v1:i0051"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
+        | "cuda_device::warp::shuffle_xor_u64_sync" => Some("v1:i0059"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
+        | "cuda_device::float::sin_approx_f32" => Some("v1:i0782"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
+        | "cuda_device::float::sin_approx_ftz_f32" => Some("v1:i0783"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
+        | "cuda_device::thread::smid"
+        | "cuda_device::smid" => Some("v1:i0288"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
+        | "cuda_device::float::sqrt_approx_f32" => Some("v1:i0805"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
+        | "cuda_device::float::sqrt_approx_ftz_f32" => Some("v1:i0806"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
+        | "cuda_device::float::sqrt_rm_f32" => Some("v1:i0811"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
+        | "cuda_device::float::sqrt_rm_f64" => Some("v1:i0817"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
+        | "cuda_device::float::sqrt_rm_ftz_f32" => Some("v1:i0812"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
+        | "cuda_device::float::sqrt_rn_f32" => Some("v1:i0807"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
+        | "cuda_device::float::sqrt_rn_f64" => Some("v1:i0815"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
+        | "cuda_device::float::sqrt_rn_ftz_f32" => Some("v1:i0808"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
+        | "cuda_device::float::sqrt_rp_f32" => Some("v1:i0813"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
+        | "cuda_device::float::sqrt_rp_f64" => Some("v1:i0818"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
+        | "cuda_device::float::sqrt_rp_ftz_f32" => Some("v1:i0814"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
+        | "cuda_device::float::sqrt_rz_f32" => Some("v1:i0809"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
+        | "cuda_device::float::sqrt_rz_f64" => Some("v1:i0816"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
+        | "cuda_device::float::sqrt_rz_ftz_f32" => Some("v1:i0810"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
+        | "cuda_device::tcgen05::stmatrix_m8n8_x2" => Some("v1:i0301"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
+        | "cuda_device::tcgen05::stmatrix_m8n8_x2_trans" => Some("v1:i0302"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
+        | "cuda_device::tcgen05::stmatrix_m8n8_x4" => Some("v1:i0303"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
+        | "cuda_device::tcgen05::stmatrix_m8n8_x4_trans" => Some("v1:i0304"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
+        | "cuda_device::bf16x2::sub_bf16x2" => Some("v1:i0065"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
+        | "cuda_device::f16x2::sub_f16x2" => Some("v1:i0075"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
+        | "cuda_device::f32x2::sub_f32x2" => Some("v1:i0997"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
+        | "cuda_device::f32x2::sub_ftz_f32x2" => Some("v1:i0998"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
+        | "cuda_device::warp::sync_mask" => Some("v1:i0049"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
+        | "cuda_device::thread::sync_threads"
+        | "cuda_device::sync_threads" => Some("v1:i0034"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
+        | "cuda_device::float::tanh_approx_f32" => Some("v1:i0821"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
+        | "cuda_device::tcgen05::tcgen05_alloc" => Some("v1:i0343"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
+        | "cuda_device::tcgen05::tcgen05_alloc_cg2" => Some("v1:i0359"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
+        | "cuda_device::tcgen05::tcgen05_commit" => Some("v1:i0348"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
+        | "cuda_device::tcgen05::tcgen05_commit_cg2" => Some("v1:i0363"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
+        | "cuda_device::tcgen05::tcgen05_commit_multicast" => Some("v1:i0760"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
+        | "cuda_device::tcgen05::tcgen05_commit_multicast_cg2" => Some("v1:i0365"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
+        | "cuda_device::tcgen05::tcgen05_commit_shared_cluster" => Some("v1:i0349"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
+        | "cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2" => Some("v1:i0364"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b" => Some("v1:i0582"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64" => Some("v1:i0578"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2" => Some("v1:i0579"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32" => Some("v1:i0580"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2" => Some("v1:i0581"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b_cg2" => Some("v1:i0583"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
+        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64" => Some("v1:i0584"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
+        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2" => Some("v1:i0585"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
+        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32" => Some("v1:i0586"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
+        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2" => Some("v1:i0587"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4" => Some("v1:i0592"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64" => Some("v1:i0588"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2" => Some("v1:i0589"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32" => Some("v1:i0590"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2" => Some("v1:i0591"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2" => Some("v1:i0593"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b" => Some("v1:i0598"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64" => Some("v1:i0594"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2" => Some("v1:i0595"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32" => Some("v1:i0596"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2" => Some("v1:i0597"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b_cg2" => Some("v1:i0599"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23" => Some("v1:i0604"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64" => Some("v1:i0600"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2" => Some("v1:i0601"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32" => Some("v1:i0602"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2" => Some("v1:i0603"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2" => Some("v1:i0605"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13" => Some("v1:i0610"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64" => Some("v1:i0606"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2" => Some("v1:i0607"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32" => Some("v1:i0608"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2" => Some("v1:i0609"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2" => Some("v1:i0611"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
+        | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem" => Some("v1:i0354"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
+        | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2" => Some("v1:i0366"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
+        | "cuda_device::tcgen05::tcgen05_dealloc" => Some("v1:i0344"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
+        | "cuda_device::tcgen05::tcgen05_dealloc_cg2" => Some("v1:i0360"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
+        | "cuda_device::tcgen05::tcgen05_fence_after_thread_sync" => Some("v1:i0347"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
+        | "cuda_device::tcgen05::tcgen05_fence_before_thread_sync" => Some("v1:i0346"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16" => Some("v1:i0637"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw" => Some("v1:i0636"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16" => Some("v1:i0629"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw" => Some("v1:i0628"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16" => Some("v1:i0631"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw" => Some("v1:i0630"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16" => Some("v1:i0639"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw" => Some("v1:i0638"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16" => Some("v1:i0633"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw" => Some("v1:i0632"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16" => Some("v1:i0641"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw" => Some("v1:i0640"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16" => Some("v1:i0635"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw" => Some("v1:i0634"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_pure" => Some("v1:i0356"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16" => Some("v1:i0651"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw" => Some("v1:i0650"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16" => Some("v1:i0643"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw" => Some("v1:i0642"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16" => Some("v1:i0645"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw" => Some("v1:i0644"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16" => Some("v1:i0653"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw" => Some("v1:i0652"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16" => Some("v1:i0647"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw" => Some("v1:i0646"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16" => Some("v1:i0649"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure" => Some("v1:i0355"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw" => Some("v1:i0648"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16" => Some("v1:i0743"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw" => Some("v1:i0742"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16" => Some("v1:i0737"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw" => Some("v1:i0736"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16" => Some("v1:i0729"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw" => Some("v1:i0728"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16" => Some("v1:i0731"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw" => Some("v1:i0730"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16" => Some("v1:i0739"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw" => Some("v1:i0738"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16" => Some("v1:i0733"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw" => Some("v1:i0732"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16" => Some("v1:i0741"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw" => Some("v1:i0740"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16" => Some("v1:i0735"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw" => Some("v1:i0734"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16" => Some("v1:i0627"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw" => Some("v1:i0626"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16" => Some("v1:i0621"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw" => Some("v1:i0620"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16" => Some("v1:i0613"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw" => Some("v1:i0612"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16" => Some("v1:i0615"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw" => Some("v1:i0614"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16" => Some("v1:i0623"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw" => Some("v1:i0622"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16" => Some("v1:i0617"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw" => Some("v1:i0616"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16" => Some("v1:i0625"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw" => Some("v1:i0624"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16" => Some("v1:i0619"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw" => Some("v1:i0618"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16" => Some("v1:i0669"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw" => Some("v1:i0668"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16" => Some("v1:i0663"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw" => Some("v1:i0662"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16" => Some("v1:i0655"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw" => Some("v1:i0654"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16" => Some("v1:i0657"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw" => Some("v1:i0656"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16" => Some("v1:i0665"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw" => Some("v1:i0664"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16" => Some("v1:i0659"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw" => Some("v1:i0658"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16" => Some("v1:i0667"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw" => Some("v1:i0666"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16" => Some("v1:i0661"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw" => Some("v1:i0660"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
+        | "cuda_device::tcgen05::tcgen05_load_wait" => Some("v1:i0357"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
+        | "cuda_device::tcgen05::tcgen05_mma_e2m1" => Some("v1:i1015"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
+        | "cuda_device::tcgen05::tcgen05_mma_e2m3" => Some("v1:i1013"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
+        | "cuda_device::tcgen05::tcgen05_mma_e3m2" => Some("v1:i1014"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
+        | "cuda_device::tcgen05::tcgen05_mma_e4m3" => Some("v1:i1011"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
+        | "cuda_device::tcgen05::tcgen05_mma_e5m2" => Some("v1:i1012"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
+        | "cuda_device::tcgen05::tcgen05_mma_f16" => Some("v1:i0351"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
+        | "cuda_device::tcgen05::tcgen05_mma_f16_cg2" => Some("v1:i0362"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
+        | "cuda_device::tcgen05::__tcgen05_mma_shared" => Some("v1:i0763"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
+        | "cuda_device::tcgen05::__tcgen05_mma_sp_shared" => Some("v1:i0766"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
+        | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor" => Some("v1:i0767"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
+        | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift" => Some("v1:i0768"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
+        | "cuda_device::tcgen05::__tcgen05_mma_tensor" => Some("v1:i0764"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
+        | "cuda_device::tcgen05::__tcgen05_mma_tensor_ashift" => Some("v1:i0765"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_bf16" => Some("v1:i0352"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_e2m1" => Some("v1:i0781"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_e2m3" => Some("v1:i0779"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_e3m2" => Some("v1:i0780"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_e4m3" => Some("v1:i0777"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_e5m2" => Some("v1:i0778"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_f16" => Some("v1:i0350"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_shared" => Some("v1:i0769"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask" => Some("v1:i0770"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared" => Some("v1:i0771"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask" => Some("v1:i0772"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor" => Some("v1:i0773"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask" => Some("v1:i0774"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor" => Some("v1:i0775"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask" => Some("v1:i0776"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_tf32" => Some("v1:i0353"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
+        | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit" => Some("v1:i0345"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
+        | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2" => Some("v1:i0361"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
+        | "cuda_device::tcgen05::tcgen05_shift_down" => Some("v1:i0761"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
+        | "cuda_device::tcgen05::tcgen05_shift_down_cg2" => Some("v1:i0762"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw" => Some("v1:i0694"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16" => Some("v1:i0695"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw" => Some("v1:i0686"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16" => Some("v1:i0687"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw" => Some("v1:i0688"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16" => Some("v1:i0689"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw" => Some("v1:i0696"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16" => Some("v1:i0697"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw" => Some("v1:i0690"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16" => Some("v1:i0691"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw" => Some("v1:i0698"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16" => Some("v1:i0699"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw" => Some("v1:i0692"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16" => Some("v1:i0693"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw" => Some("v1:i0708"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16" => Some("v1:i0709"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw" => Some("v1:i0700"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16" => Some("v1:i0701"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw" => Some("v1:i0702"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16" => Some("v1:i0703"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw" => Some("v1:i0710"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16" => Some("v1:i0711"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw" => Some("v1:i0704"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16" => Some("v1:i0705"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw" => Some("v1:i0706"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16" => Some("v1:i0707"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw" => Some("v1:i0758"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16" => Some("v1:i0759"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw" => Some("v1:i0752"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16" => Some("v1:i0753"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw" => Some("v1:i0744"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16" => Some("v1:i0745"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw" => Some("v1:i0746"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16" => Some("v1:i0747"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw" => Some("v1:i0754"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16" => Some("v1:i0755"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw" => Some("v1:i0748"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16" => Some("v1:i0749"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw" => Some("v1:i0756"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16" => Some("v1:i0757"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw" => Some("v1:i0750"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16" => Some("v1:i0751"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw" => Some("v1:i0684"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16" => Some("v1:i0685"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw" => Some("v1:i0678"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16" => Some("v1:i0679"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw" => Some("v1:i0670"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16" => Some("v1:i0671"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw" => Some("v1:i0672"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16" => Some("v1:i0673"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw" => Some("v1:i0680"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16" => Some("v1:i0681"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw" => Some("v1:i0674"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16" => Some("v1:i0675"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw" => Some("v1:i0682"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16" => Some("v1:i0683"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw" => Some("v1:i0676"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16" => Some("v1:i0677"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw" => Some("v1:i0726"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16" => Some("v1:i0727"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw" => Some("v1:i0720"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16" => Some("v1:i0721"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw" => Some("v1:i0712"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16" => Some("v1:i0713"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw" => Some("v1:i0714"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16" => Some("v1:i0715"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw" => Some("v1:i0722"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16" => Some("v1:i0723"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw" => Some("v1:i0716"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16" => Some("v1:i0717"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw" => Some("v1:i0724"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16" => Some("v1:i0725"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw" => Some("v1:i0718"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16" => Some("v1:i0719"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
+        | "cuda_device::tcgen05::tcgen05_store_wait" => Some("v1:i0358"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
+        | "cuda_device::tma::tensormap_replace_box_dim" => Some("v1:i0894"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
+        | "cuda_device::tma::tensormap_replace_element_stride" => Some("v1:i0895"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
+        | "cuda_device::tma::tensormap_replace_element_type" => Some("v1:i0896"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
+        | "cuda_device::tma::tensormap_replace_fill_mode" => Some("v1:i0897"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
+        | "cuda_device::tma::tensormap_replace_global_address" => Some("v1:i0898"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
+        | "cuda_device::tma::tensormap_replace_global_dim" => Some("v1:i0899"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
+        | "cuda_device::tma::tensormap_replace_global_stride" => Some("v1:i0900"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
+        | "cuda_device::tma::tensormap_replace_interleave_layout" => Some("v1:i0901"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
+        | "cuda_device::tma::tensormap_replace_rank" => Some("v1:i0902"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
+        | "cuda_device::tma::tensormap_replace_swizzle_atomicity" => Some("v1:i0903"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
+        | "cuda_device::tma::tensormap_replace_swizzle_mode" => Some("v1:i0904"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
+        | "cuda_device::thread::threadIdx_x"
+        | "cuda_device::threadIdx_x" => Some("v1:i0001"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
+        | "cuda_device::thread::threadIdx_y"
+        | "cuda_device::threadIdx_y" => Some("v1:i0005"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
+        | "cuda_device::thread::threadIdx_z"
+        | "cuda_device::threadIdx_z" => Some("v1:i0009"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
+        | "cuda_device::fence::threadfence"
+        | "cuda_device::threadfence" => Some("v1:i0299"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
+        | "cuda_device::fence::threadfence_block"
+        | "cuda_device::threadfence_block" => Some("v1:i0298"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
+        | "cuda_device::fence::threadfence_system"
+        | "cuda_device::threadfence_system" => Some("v1:i0300"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
+        | "cuda_device::shared::total_smem_size" => Some("v1:i0294"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295" | "cuda_device::debug::trap" => {
+            Some("v1:i0295")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043" => Some("v1:i0043"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291" | "cuda_device::warp::warpid" => {
+            Some("v1:i0291")
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
+        | "cuda_device::wgmma::wgmma_commit_group" => Some("v1:i0318"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
+        | "cuda_device::wgmma::wgmma_fence" => Some("v1:i0317"),
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
+        | "cuda_device::wgmma::__wgmma_wait_group" => Some("v1:i0319"),
+        _ => None,
+    }
+}
+
+#[allow(clippy::too_many_arguments)]
+pub fn try_dispatch_generated_intrinsic(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    if let Some(operation) = sreg::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = active_mask::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = ldmatrix::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = stmatrix::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = register_mma::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = sparse_mma::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = packed_atomic::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = redux::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = vote::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = warp_match::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = elect::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = warp_barrier::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = warp_shuffle::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = dotprod::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = packed_alu::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = integer_minmax::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = packed_conversion::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = scalar_conversion::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = scalar_arithmetic::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = scalar_math::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = extended_minmax::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = movmatrix::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = prmt::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = cluster_barrier::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = cluster_memory::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = debug_control::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = clc::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = wgmma_control::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = cp_async::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = mbarrier_basic::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = mbarrier_extended::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = sync::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = execution_control::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = tma::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = tcgen05_mma::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = tcgen05_ld::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = tcgen05_st::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = tcgen05_cp::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    if let Some(operation) = tcgen05_other::try_dispatch(
+        ctx,
+        body,
+        name,
+        args,
+        destination,
+        target,
+        block_ptr,
+        prev_op,
+        value_map,
+        block_map,
+        loc.clone(),
+    )? {
+        return Ok(Some(operation));
+    }
+    Ok(None)
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs
new file mode 100644
index 0000000000..54a5416520
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs
@@ -0,0 +1,69 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `movmatrix` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::MovmatrixTransB16Op;
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
+        | "cuda_device::wmma::movmatrix_trans_b16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MovmatrixTransB16Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0305");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "movmatrix_trans_b16 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs
new file mode 100644
index 0000000000..6ec41a5697
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs
@@ -0,0 +1,1269 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `packed_alu` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    AbsBf16x2Op, AbsF16x2Op, AddBf16x2Op, AddF16x2Op, AddF32x2Op, AddFtzF32x2Op, FmaBf16x2Op,
+    FmaF16x2Op, FmaF32x2Op, FmaFtzF16x2Op, FmaFtzF32x2Op, FmaFtzReluF16x2Op, FmaFtzSatF16x2Op,
+    FmaReluBf16x2Op, FmaReluF16x2Op, FmaSatF16x2Op, MaxBf16x2Op, MaxF16x2Op, MinBf16x2Op,
+    MinF16x2Op, MulBf16x2Op, MulF16x2Op, MulF32x2Op, MulFtzF32x2Op, NegBf16x2Op, NegF16x2Op,
+    SubBf16x2Op, SubF16x2Op, SubF32x2Op, SubFtzF32x2Op,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
+        | "cuda_device::bf16x2::abs_bf16x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = AbsBf16x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0070");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "abs_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
+        | "cuda_device::f16x2::abs_f16x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = AbsF16x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0080");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "abs_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
+        | "cuda_device::bf16x2::add_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = AddBf16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0064");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
+        | "cuda_device::f16x2::add_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = AddF16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0074");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
+        | "cuda_device::f32x2::add_f32x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = AddF32x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0995");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_f32x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
+        | "cuda_device::f32x2::add_ftz_f32x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = AddFtzF32x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0996");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_ftz_f32x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
+        | "cuda_device::bf16x2::fma_bf16x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = FmaBf16x2Op::build(ctx, arg0, arg1, arg2);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0062");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
+        | "cuda_device::f16x2::fma_f16x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = FmaF16x2Op::build(ctx, arg0, arg1, arg2);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0072");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
+        | "cuda_device::f32x2::fma_f32x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = FmaF32x2Op::build(ctx, arg0, arg1, arg2);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1001");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_f32x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
+        | "cuda_device::f16x2::fma_ftz_f16x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = FmaFtzF16x2Op::build(ctx, arg0, arg1, arg2);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0854");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_ftz_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
+        | "cuda_device::f32x2::fma_ftz_f32x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = FmaFtzF32x2Op::build(ctx, arg0, arg1, arg2);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1002");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_ftz_f32x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
+        | "cuda_device::f16x2::fma_ftz_relu_f16x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = FmaFtzReluF16x2Op::build(ctx, arg0, arg1, arg2);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0857");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_ftz_relu_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
+        | "cuda_device::f16x2::fma_ftz_sat_f16x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = FmaFtzSatF16x2Op::build(ctx, arg0, arg1, arg2);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0856");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_ftz_sat_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
+        | "cuda_device::bf16x2::fma_relu_bf16x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = FmaReluBf16x2Op::build(ctx, arg0, arg1, arg2);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0063");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_relu_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
+        | "cuda_device::f16x2::fma_relu_f16x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = FmaReluF16x2Op::build(ctx, arg0, arg1, arg2);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0073");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_relu_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
+        | "cuda_device::f16x2::fma_sat_f16x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = FmaSatF16x2Op::build(ctx, arg0, arg1, arg2);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0855");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_sat_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
+        | "cuda_device::bf16x2::max_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MaxBf16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0068");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
+        | "cuda_device::f16x2::max_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MaxF16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0078");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "max_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
+        | "cuda_device::bf16x2::min_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MinBf16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0067");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
+        | "cuda_device::f16x2::min_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MinF16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0077");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "min_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
+        | "cuda_device::bf16x2::mul_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MulBf16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0066");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
+        | "cuda_device::f16x2::mul_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MulF16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0076");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
+        | "cuda_device::f32x2::mul_f32x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MulF32x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0999");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_f32x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
+        | "cuda_device::f32x2::mul_ftz_f32x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = MulFtzF32x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1000");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_ftz_f32x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
+        | "cuda_device::bf16x2::neg_bf16x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = NegBf16x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0069");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "neg_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
+        | "cuda_device::f16x2::neg_f16x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = NegF16x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0079");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "neg_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
+        | "cuda_device::bf16x2::sub_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = SubBf16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0065");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sub_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
+        | "cuda_device::f16x2::sub_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = SubF16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0075");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sub_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
+        | "cuda_device::f32x2::sub_f32x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = SubF32x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0997");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sub_f32x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
+        | "cuda_device::f32x2::sub_ftz_f32x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = SubFtzF32x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0998");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sub_ftz_f32x2 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs
new file mode 100644
index 0000000000..46b466e361
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs
@@ -0,0 +1,119 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `packed_atomic` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{PackedAtomicAddOp, PackedAtomicFormatAttr};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
+        | "cuda_device::atomic::atom_add_bf16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (addend, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let atom =
+                PackedAtomicAddOp::build(ctx, address, addend, PackedAtomicFormatAttr::Bf16x2);
+            atom.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, atom, "v1:i0015");
+            helpers::insert_op(ctx, atom, block_ptr, last_op);
+            let value = atom.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                atom,
+                value_map,
+                block_map,
+                loc,
+                "atom_add_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
+        | "cuda_device::atomic::atom_add_f16x2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (address, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (addend, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let atom =
+                PackedAtomicAddOp::build(ctx, address, addend, PackedAtomicFormatAttr::F16x2);
+            atom.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, atom, "v1:i0014");
+            helpers::insert_op(ctx, atom, block_ptr, last_op);
+            let value = atom.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                value,
+                target,
+                block_ptr,
+                atom,
+                value_map,
+                block_map,
+                loc,
+                "atom_add_f16x2 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs
new file mode 100644
index 0000000000..0d2efb0af0
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs
@@ -0,0 +1,676 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `packed_conversion` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    CvtF16x2F32Op, CvtF32x2Bf16x2Op, CvtRnF16x2E4m3x2Op, CvtRnF16x2E5m2x2Op, CvtRnReluBf16x2F32Op,
+    CvtRnReluF16x2E4m3x2Op, CvtRnReluF16x2E5m2x2Op, CvtRnReluF16x2F32Op,
+    CvtRnSatfiniteE4m3x2F16x2Op, CvtRnSatfiniteE4m3x2F32Op, CvtRnSatfiniteE5m2x2F16x2Op,
+    CvtRnSatfiniteE5m2x2F32Op, CvtRnSatfiniteReluE4m3x2F16x2Op, CvtRnSatfiniteReluE4m3x2F32Op,
+    CvtRnSatfiniteReluE5m2x2F16x2Op, CvtRnSatfiniteReluE5m2x2F32Op, CvtRzBf16x2F32Op,
+    CvtRzF16x2F32Op,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
+        | "cuda_device::convert::cvt_f16x2_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtF16x2F32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0081");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_f16x2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
+        | "cuda_device::convert::cvt_bf16x2_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtF32x2Bf16x2Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0071");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_f32x2_bf16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
+        | "cuda_device::convert::cvt_rn_f16x2_e4m3x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnF16x2E4m3x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0826");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_f16x2_e4m3x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
+        | "cuda_device::convert::cvt_rn_f16x2_e5m2x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnF16x2E5m2x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0828");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_f16x2_e5m2x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
+        | "cuda_device::convert::cvt_rn_relu_bf16x2_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnReluBf16x2F32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0084");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_relu_bf16x2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
+        | "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnReluF16x2E4m3x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0827");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_relu_f16x2_e4m3x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
+        | "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnReluF16x2E5m2x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0829");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_relu_f16x2_e5m2x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
+        | "cuda_device::convert::cvt_rn_relu_f16x2_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnReluF16x2F32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0083");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_relu_f16x2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
+        | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnSatfiniteE4m3x2F16x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0822");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_satfinite_e4m3x2_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
+        | "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnSatfiniteE4m3x2F32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0259");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_satfinite_e4m3x2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
+        | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnSatfiniteE5m2x2F16x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0824");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_satfinite_e5m2x2_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
+        | "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnSatfiniteE5m2x2F32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0261");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_satfinite_e5m2x2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
+        | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnSatfiniteReluE4m3x2F16x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0823");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_satfinite_relu_e4m3x2_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
+        | "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnSatfiniteReluE4m3x2F32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0260");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_satfinite_relu_e4m3x2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
+        | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnSatfiniteReluE5m2x2F16x2Op::build(ctx, arg0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0825");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_satfinite_relu_e5m2x2_f16x2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
+        | "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRnSatfiniteReluE5m2x2F32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0262");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_satfinite_relu_e5m2x2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
+        | "cuda_device::convert::cvt_rz_bf16x2_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRzBf16x2F32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0085");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rz_bf16x2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
+        | "cuda_device::convert::cvt_rz_f16x2_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = CvtRzF16x2F32Op::build(ctx, arg0, arg1);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0082");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rz_f16x2_f32 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs
new file mode 100644
index 0000000000..942a64fa14
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs
@@ -0,0 +1,333 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `prmt` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{PrmtModeAttr, PrmtOp};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252" | "cuda_device::prmt::prmt" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let prmt = PrmtOp::build(ctx, vec![arg0, arg1, arg2], PrmtModeAttr::Generic);
+            prmt.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0252");
+            helpers::insert_op(ctx, prmt, block_ptr, last_op);
+            let result = prmt.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                prmt,
+                value_map,
+                block_map,
+                loc,
+                "prmt call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254" | "cuda_device::prmt::prmt_b4e" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let prmt = PrmtOp::build(ctx, vec![arg0, arg1, arg2], PrmtModeAttr::B4e);
+            prmt.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0254");
+            helpers::insert_op(ctx, prmt, block_ptr, last_op);
+            let result = prmt.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                prmt,
+                value_map,
+                block_map,
+                loc,
+                "prmt_b4e call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256" | "cuda_device::prmt::prmt_ecl" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let prmt = PrmtOp::build(ctx, vec![arg0, arg1], PrmtModeAttr::Ecl);
+            prmt.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0256");
+            helpers::insert_op(ctx, prmt, block_ptr, last_op);
+            let result = prmt.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                prmt,
+                value_map,
+                block_map,
+                loc,
+                "prmt_ecl call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257" | "cuda_device::prmt::prmt_ecr" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let prmt = PrmtOp::build(ctx, vec![arg0, arg1], PrmtModeAttr::Ecr);
+            prmt.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0257");
+            helpers::insert_op(ctx, prmt, block_ptr, last_op);
+            let result = prmt.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                prmt,
+                value_map,
+                block_map,
+                loc,
+                "prmt_ecr call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253" | "cuda_device::prmt::prmt_f4e" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let prmt = PrmtOp::build(ctx, vec![arg0, arg1, arg2], PrmtModeAttr::F4e);
+            prmt.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0253");
+            helpers::insert_op(ctx, prmt, block_ptr, last_op);
+            let result = prmt.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                prmt,
+                value_map,
+                block_map,
+                loc,
+                "prmt_f4e call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
+        | "cuda_device::prmt::prmt_rc16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let prmt = PrmtOp::build(ctx, vec![arg0, arg1], PrmtModeAttr::Rc16);
+            prmt.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0258");
+            helpers::insert_op(ctx, prmt, block_ptr, last_op);
+            let result = prmt.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                prmt,
+                value_map,
+                block_map,
+                loc,
+                "prmt_rc16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255" | "cuda_device::prmt::prmt_rc8" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let prmt = PrmtOp::build(ctx, vec![arg0, arg1], PrmtModeAttr::Rc8);
+            prmt.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, prmt, "v1:i0255");
+            helpers::insert_op(ctx, prmt, block_ptr, last_op);
+            let result = prmt.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                prmt,
+                value_map,
+                block_map,
+                loc,
+                "prmt_rc8 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs
new file mode 100644
index 0000000000..5f21615a0d
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs
@@ -0,0 +1,668 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `redux` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    ReduxSyncAddOp, ReduxSyncAndOp, ReduxSyncFmaxAbsNanOp, ReduxSyncFmaxAbsOp, ReduxSyncFmaxNanOp,
+    ReduxSyncFmaxOp, ReduxSyncFminAbsNanOp, ReduxSyncFminAbsOp, ReduxSyncFminNanOp,
+    ReduxSyncFminOp, ReduxSyncMaxOp, ReduxSyncMinOp, ReduxSyncOrOp, ReduxSyncUmaxOp,
+    ReduxSyncUminOp, ReduxSyncXorOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
+        | "cuda_device::warp::redux_sync_add" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncAddOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0017");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_add call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
+        | "cuda_device::warp::redux_sync_and" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncAndOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0022");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_and call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
+        | "cuda_device::warp::redux_sync_max_abs_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncFmaxAbsOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1009");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_max_abs_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
+        | "cuda_device::warp::redux_sync_max_abs_nan_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncFmaxAbsNanOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1010");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_max_abs_nan_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
+        | "cuda_device::warp::redux_sync_max_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncFmaxOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1007");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_max_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
+        | "cuda_device::warp::redux_sync_max_i32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncMaxOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0021");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_max_i32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
+        | "cuda_device::warp::redux_sync_max_nan_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncFmaxNanOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1008");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_max_nan_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
+        | "cuda_device::warp::redux_sync_max_u32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncUmaxOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0020");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_max_u32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
+        | "cuda_device::warp::redux_sync_min_abs_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncFminAbsOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1005");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_min_abs_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
+        | "cuda_device::warp::redux_sync_min_abs_nan_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncFminAbsNanOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1006");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_min_abs_nan_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
+        | "cuda_device::warp::redux_sync_min_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncFminOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1003");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_min_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
+        | "cuda_device::warp::redux_sync_min_i32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncMinOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0019");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_min_i32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
+        | "cuda_device::warp::redux_sync_min_nan_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncFminNanOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1004");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_min_nan_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
+        | "cuda_device::warp::redux_sync_min_u32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncUminOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0018");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_min_u32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
+        | "cuda_device::warp::redux_sync_or" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncOrOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0023");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_or call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
+        | "cuda_device::warp::redux_sync_xor" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let reduction = ReduxSyncXorOp::build(ctx, member_mask, value);
+            reduction.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i0024");
+            helpers::insert_op(ctx, reduction, block_ptr, last_op);
+            let result = reduction.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                reduction,
+                value_map,
+                block_map,
+                loc,
+                "redux_sync_xor call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs
new file mode 100644
index 0000000000..c2936dba45
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs
@@ -0,0 +1,7746 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `register_mma` intrinsics.
+
+use super::helpers::{
+    GeneratedMmaImportAdapter, bundle_generated_mma_results, import_generated_mma_operands,
+    require_arity,
+};
+use crate::error::TranslationResult;
+use crate::translator::{terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    RegisterMmaAccumulatorAttr, RegisterMmaElementAttr, RegisterMmaKindAttr, RegisterMmaLayoutAttr,
+    RegisterMmaOp, RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
+        | "cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::AndPopc);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0161");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k128_s32_b1_and_popc call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
+        | "cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::XorPopc);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0158");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k128_s32_b1_xor_popc call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
+        | "cuda_device::wmma::mma_m16n8k16_f16_f16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::F16);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0524");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_f16_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
+        | "cuda_device::wmma::mma_m16n8k16_f32_bf16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::Bf16);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::Bf16);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0105");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_f32_bf16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
+        | "cuda_device::wmma::mma_m16n8k16_f32_f16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::F16);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0106");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_f32_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0504");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_fp8_f16_e4m3_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0505");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_fp8_f16_e4m3_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0506");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_fp8_f16_e5m2_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0507");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_fp8_f16_e5m2_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0508");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_fp8_f32_e4m3_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0509");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_fp8_f32_e4m3_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0510");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_fp8_f32_e5m2_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
+        | "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0511");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_fp8_f32_e5m2_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
+        | "cuda_device::wmma::mma_m16n8k16_s32_s8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0110");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_s32_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
+        | "cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0117");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_s32_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
+        | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0111");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_s32_s8_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
+        | "cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0118");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_s32_s8_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
+        | "cuda_device::wmma::mma_m16n8k16_s32_u8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0112");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_s32_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
+        | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0113");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_s32_u8_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
+        | "cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0120");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_s32_u8_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
+        | "cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0119");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k16_s32_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
+        | "cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k256);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::AndPopc);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0162");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k256_s32_b1_and_popc call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
+        | "cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k256);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::XorPopc);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0159");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k256_s32_b1_xor_popc call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0479");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e2m1_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0480");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e2m1_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0481");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e2m1_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0482");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e2m1_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0483");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e2m1_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0484");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e2m3_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0485");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e2m3_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0486");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e2m3_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0487");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e2m3_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0488");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e2m3_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0489");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e3m2_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0490");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e3m2_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0491");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e3m2_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0492");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e3m2_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0493");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e3m2_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0494");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e4m3_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0495");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e4m3_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0496");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e4m3_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0497");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e4m3_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0498");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e4m3_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0499");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e5m2_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0500");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e5m2_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0501");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e5m2_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0502");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e5m2_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
+        | "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0503");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f16_e5m2_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0454");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e2m1_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0455");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e2m1_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0456");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e2m1_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0457");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e2m1_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0458");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e2m1_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0459");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e2m3_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0460");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e2m3_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0461");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e2m3_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0462");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e2m3_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0463");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e2m3_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0464");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e3m2_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0465");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e3m2_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0466");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e3m2_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0467");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e3m2_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0468");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e3m2_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0469");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e4m3_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0470");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e4m3_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0471");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e4m3_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0472");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e4m3_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0473");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e4m3_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0474");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e5m2_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0475");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e5m2_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0476");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e5m2_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0477");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e5m2_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
+        | "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::F8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0478");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_f32_e5m2_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0512");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_fp8_f16_e4m3_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0513");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_fp8_f16_e4m3_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0514");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_fp8_f16_e5m2_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0515");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_fp8_f16_e5m2_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0516");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_fp8_f32_e4m3_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0517");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_fp8_f32_e4m3_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0518");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_fp8_f32_e5m2_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
+        | "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0519");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_fp8_f32_e5m2_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0858");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0859");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0860");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0861");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0862");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0863");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0864");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0865");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0866");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0867");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0868");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0869");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0870");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0871");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0872");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0873");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0874");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0875");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0876");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0877");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0878");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0879");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0880");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0881");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
+        | "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32Scales2U32Selectors4U16ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Mxf8f6f4);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0882");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0141");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0149");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0142");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_s4_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0150");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_s4_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0108");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0121");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0114");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_s8_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
+        | "cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0122");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_s8_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0143");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0144");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_u4_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0152");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_u4_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B1U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0151");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0115");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0116");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_u8_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0124");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_u8_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
+        | "cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0123");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k32_s32_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
+        | "cuda_device::wmma::mma_m16n8k4_f32_tf32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k4);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::Tf32);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::Tf32);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0520");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k4_f32_tf32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
+        | "cuda_device::wmma::mma_m16n8k64_s32_s4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0145");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k64_s32_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
+        | "cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0153");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k64_s32_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
+        | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0146");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k64_s32_s4_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
+        | "cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0154");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k64_s32_s4_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
+        | "cuda_device::wmma::mma_m16n8k64_s32_u4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0147");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k64_s32_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
+        | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0148");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k64_s32_u4_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
+        | "cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0156");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k64_s32_u4_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
+        | "cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B2U32ToD4I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0155");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k64_s32_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
+        | "cuda_device::wmma::mma_m16n8k8_f16_f16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k8);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::F16);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0521");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k8_f16_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
+        | "cuda_device::wmma::mma_m16n8k8_f32_bf16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k8);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::Bf16);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::Bf16);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0522");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k8_f32_bf16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
+        | "cuda_device::wmma::mma_m16n8k8_f32_f16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k8);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::F16);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::F16);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0523");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k8_f32_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
+        | "cuda_device::wmma::mma_m16n8k8_f32_tf32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M16n8k8);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::Tf32);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::Tf32);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0107");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m16n8k8_f32_tf32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
+        | "cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k128);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::AndPopc);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0160");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k128_s32_b1_and_popc call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
+        | "cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k128);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::XorPopc);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::B1);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0157");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k128_s32_b1_xor_popc call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
+        | "cuda_device::wmma::mma_m8n8k16_s32_s8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0125");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k16_s32_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
+        | "cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0129");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k16_s32_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
+        | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0126");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k16_s32_s8_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
+        | "cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0130");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k16_s32_s8_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
+        | "cuda_device::wmma::mma_m8n8k16_s32_u8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0127");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k16_s32_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
+        | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0128");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k16_s32_u8_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
+        | "cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0132");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k16_s32_u8_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
+        | "cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k16);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U8);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0131");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k16_s32_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
+        | "cuda_device::wmma::mma_m8n8k32_s32_s4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0133");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k32_s32_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
+        | "cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0137");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k32_s32_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
+        | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0134");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k32_s32_s4_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
+        | "cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0138");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k32_s32_s4_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
+        | "cuda_device::wmma::mma_m8n8k32_s32_u4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0135");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k32_s32_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
+        | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Wrapping);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0136");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k32_s32_u4_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
+        | "cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::S4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0140");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k32_s32_u4_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
+        | "cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2I32A1U32B1U32ToD2I32,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k32);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::U4);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::Satfinite);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0139");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k32_s32_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
+        | "cuda_device::wmma::mma_m8n8k4_f64" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2F64A1F64B1F64ToD2F64,
+            )?;
+            let mma = Operation::new(
+                ctx,
+                RegisterMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = RegisterMmaOp::new(mma);
+            mma.set_attr_nvvm_register_mma_shape(ctx, RegisterMmaShapeAttr::M8n8k4);
+            mma.set_attr_nvvm_register_mma_operation(ctx, RegisterMmaOperationAttr::Multiply);
+            mma.set_attr_nvvm_register_mma_kind(ctx, RegisterMmaKindAttr::Standard);
+            mma.set_attr_nvvm_register_mma_accumulator(ctx, RegisterMmaAccumulatorAttr::F64);
+            mma.set_attr_nvvm_register_mma_a_element(ctx, RegisterMmaElementAttr::F64);
+            mma.set_attr_nvvm_register_mma_b_element(ctx, RegisterMmaElementAttr::F64);
+            mma.set_attr_nvvm_register_mma_a_layout(ctx, RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(ctx, RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(ctx, RegisterMmaOverflowAttr::NotApplicable);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0109");
+            helpers::insert_op(ctx, mma, block_ptr, Some(last_op));
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_m8n8k4_f64 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs
new file mode 100644
index 0000000000..24e64acdf8
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs
@@ -0,0 +1,3230 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `scalar_arithmetic` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    ScalarArithmeticFormatAttr, ScalarArithmeticOp, ScalarArithmeticOperationAttr,
+    ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
+        | "cuda_device::float::add_rm_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0446");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rm_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
+        | "cuda_device::float::add_rm_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0436");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rm_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
+        | "cuda_device::float::add_rm_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0447");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rm_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
+        | "cuda_device::float::add_rm_ftz_sat_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0449");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rm_ftz_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
+        | "cuda_device::float::add_rm_sat_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0448");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rm_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
+        | "cuda_device::float::add_rn_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0438");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rn_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
+        | "cuda_device::float::add_rn_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0434");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rn_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
+        | "cuda_device::float::add_rn_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0439");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rn_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
+        | "cuda_device::float::add_rn_ftz_sat_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0441");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rn_ftz_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
+        | "cuda_device::float::add_rn_sat_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0440");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rn_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
+        | "cuda_device::float::add_rp_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0450");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rp_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
+        | "cuda_device::float::add_rp_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0437");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rp_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
+        | "cuda_device::float::add_rp_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0451");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rp_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
+        | "cuda_device::float::add_rp_ftz_sat_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0453");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rp_ftz_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
+        | "cuda_device::float::add_rp_sat_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0452");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rp_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
+        | "cuda_device::float::add_rz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0442");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
+        | "cuda_device::float::add_rz_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0435");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rz_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
+        | "cuda_device::float::add_rz_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0443");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rz_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
+        | "cuda_device::float::add_rz_ftz_sat_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0445");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rz_ftz_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
+        | "cuda_device::float::add_rz_sat_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Add,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0444");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "add_rz_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
+        | "cuda_device::float::div_rm_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0414");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rm_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
+        | "cuda_device::float::div_rm_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0396");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rm_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
+        | "cuda_device::float::div_rm_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0415");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rm_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
+        | "cuda_device::float::div_rn_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0410");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rn_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
+        | "cuda_device::float::div_rn_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0394");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rn_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
+        | "cuda_device::float::div_rn_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0411");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rn_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
+        | "cuda_device::float::div_rp_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0416");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rp_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
+        | "cuda_device::float::div_rp_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0397");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rp_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
+        | "cuda_device::float::div_rp_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0417");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rp_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
+        | "cuda_device::float::div_rz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0412");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
+        | "cuda_device::float::div_rz_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0395");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rz_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
+        | "cuda_device::float::div_rz_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Div,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0413");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "div_rz_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
+        | "cuda_device::float::fma_rm_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0426");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rm_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
+        | "cuda_device::float::fma_rm_f64" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0400");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rm_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
+        | "cuda_device::float::fma_rm_ftz_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0427");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rm_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
+        | "cuda_device::float::fma_rm_ftz_sat_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0429");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rm_ftz_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
+        | "cuda_device::float::fma_rm_sat_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0428");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rm_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
+        | "cuda_device::float::fma_rn_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0418");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rn_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
+        | "cuda_device::float::fma_rn_f64" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0398");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rn_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
+        | "cuda_device::float::fma_rn_ftz_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0419");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rn_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
+        | "cuda_device::float::fma_rn_ftz_sat_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0421");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rn_ftz_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
+        | "cuda_device::float::fma_rn_sat_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0420");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rn_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
+        | "cuda_device::float::fma_rp_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0430");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rp_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
+        | "cuda_device::float::fma_rp_f64" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0401");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rp_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
+        | "cuda_device::float::fma_rp_ftz_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0431");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rp_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
+        | "cuda_device::float::fma_rp_ftz_sat_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0433");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rp_ftz_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
+        | "cuda_device::float::fma_rp_sat_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0432");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rp_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
+        | "cuda_device::float::fma_rz_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0422");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
+        | "cuda_device::float::fma_rz_f64" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0399");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rz_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
+        | "cuda_device::float::fma_rz_ftz_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0423");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rz_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
+        | "cuda_device::float::fma_rz_ftz_sat_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0425");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rz_ftz_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
+        | "cuda_device::float::fma_rz_sat_f32" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (arg2, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1, arg2],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Fma,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::Sat,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0424");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "fma_rz_sat_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
+        | "cuda_device::float::mul_rm_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0406");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rm_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
+        | "cuda_device::float::mul_rm_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0392");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rm_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
+        | "cuda_device::float::mul_rm_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rm,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0407");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rm_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
+        | "cuda_device::float::mul_rn_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0402");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rn_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
+        | "cuda_device::float::mul_rn_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0390");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rn_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
+        | "cuda_device::float::mul_rn_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rn,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0403");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rn_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
+        | "cuda_device::float::mul_rp_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0408");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rp_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
+        | "cuda_device::float::mul_rp_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0393");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rp_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
+        | "cuda_device::float::mul_rp_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rp,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0409");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rp_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
+        | "cuda_device::float::mul_rz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0404");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
+        | "cuda_device::float::mul_rz_f64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F64,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Preserve,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0391");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rz_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
+        | "cuda_device::float::mul_rz_ftz_f32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (arg1, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarArithmeticOp::build(
+                ctx,
+                vec![arg0, arg1],
+                ScalarArithmeticFormatAttr::F32,
+                ScalarArithmeticOperationAttr::Mul,
+                ScalarArithmeticRoundingAttr::Rz,
+                ScalarArithmeticSubnormalAttr::Ftz,
+                ScalarArithmeticSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0405");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "mul_rz_ftz_f32 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs
new file mode 100644
index 0000000000..a0b62085ec
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs
@@ -0,0 +1,391 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `scalar_conversion` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
+        | "cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarConversionOp::build(
+                ctx,
+                value,
+                ScalarConversionRoundingAttr::NearestEven,
+                ScalarConversionSaturationAttr::ReluSatfinite,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0373");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_relu_satfinite_tf32_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
+        | "cuda_device::convert::cvt_rn_relu_tf32_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarConversionOp::build(
+                ctx,
+                value,
+                ScalarConversionRoundingAttr::NearestEven,
+                ScalarConversionSaturationAttr::Relu,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0371");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_relu_tf32_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
+        | "cuda_device::convert::cvt_rn_satfinite_tf32_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarConversionOp::build(
+                ctx,
+                value,
+                ScalarConversionRoundingAttr::NearestEven,
+                ScalarConversionSaturationAttr::Satfinite,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0372");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_satfinite_tf32_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
+        | "cuda_device::convert::cvt_rn_tf32_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarConversionOp::build(
+                ctx,
+                value,
+                ScalarConversionRoundingAttr::NearestEven,
+                ScalarConversionSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0370");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rn_tf32_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
+        | "cuda_device::convert::cvt_rna_satfinite_tf32_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarConversionOp::build(
+                ctx,
+                value,
+                ScalarConversionRoundingAttr::NearestAway,
+                ScalarConversionSaturationAttr::Satfinite,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0369");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rna_satfinite_tf32_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
+        | "cuda_device::convert::cvt_rna_tf32_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarConversionOp::build(
+                ctx,
+                value,
+                ScalarConversionRoundingAttr::NearestAway,
+                ScalarConversionSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0368");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rna_tf32_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
+        | "cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarConversionOp::build(
+                ctx,
+                value,
+                ScalarConversionRoundingAttr::TowardZero,
+                ScalarConversionSaturationAttr::ReluSatfinite,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0377");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rz_relu_satfinite_tf32_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
+        | "cuda_device::convert::cvt_rz_relu_tf32_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarConversionOp::build(
+                ctx,
+                value,
+                ScalarConversionRoundingAttr::TowardZero,
+                ScalarConversionSaturationAttr::Relu,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0375");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rz_relu_tf32_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
+        | "cuda_device::convert::cvt_rz_satfinite_tf32_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarConversionOp::build(
+                ctx,
+                value,
+                ScalarConversionRoundingAttr::TowardZero,
+                ScalarConversionSaturationAttr::Satfinite,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0376");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rz_satfinite_tf32_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
+        | "cuda_device::convert::cvt_rz_tf32_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarConversionOp::build(
+                ctx,
+                value,
+                ScalarConversionRoundingAttr::TowardZero,
+                ScalarConversionSaturationAttr::None,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0374");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cvt_rz_tf32_f32 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs
new file mode 100644
index 0000000000..ec2ec28b2d
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs
@@ -0,0 +1,1559 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `scalar_math` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    ScalarMathFormatAttr, ScalarMathOp, ScalarMathOperationAttr, ScalarMathPrecisionAttr,
+    ScalarMathSubnormalAttr,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
+        | "cuda_device::float::cos_approx_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Cos,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0784");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cos_approx_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
+        | "cuda_device::float::cos_approx_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Cos,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0785");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "cos_approx_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
+        | "cuda_device::float::ex2_approx_f16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F16,
+                ScalarMathOperationAttr::Ex2,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1016");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "ex2_approx_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
+        | "cuda_device::float::ex2_approx_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Ex2,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0819");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "ex2_approx_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
+        | "cuda_device::float::ex2_approx_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Ex2,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0820");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "ex2_approx_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
+        | "cuda_device::float::lg2_approx_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Lg2,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0786");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "lg2_approx_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
+        | "cuda_device::float::lg2_approx_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Lg2,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0787");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "lg2_approx_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
+        | "cuda_device::float::rcp_approx_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0788");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_approx_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
+        | "cuda_device::float::rcp_approx_ftz_f64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F64,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0797");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_approx_ftz_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
+        | "cuda_device::float::rcp_rm_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rm,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0793");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rm_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
+        | "cuda_device::float::rcp_rm_f64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F64,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rm,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0800");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rm_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
+        | "cuda_device::float::rcp_rm_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rm,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0794");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rm_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
+        | "cuda_device::float::rcp_rn_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rn,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0789");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rn_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
+        | "cuda_device::float::rcp_rn_f64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F64,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rn,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0798");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rn_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
+        | "cuda_device::float::rcp_rn_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rn,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0790");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rn_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
+        | "cuda_device::float::rcp_rp_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rp,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0795");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rp_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
+        | "cuda_device::float::rcp_rp_f64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F64,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rp,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0801");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rp_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
+        | "cuda_device::float::rcp_rp_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rp,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0796");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rp_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
+        | "cuda_device::float::rcp_rz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rz,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0791");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
+        | "cuda_device::float::rcp_rz_f64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F64,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rz,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0799");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rz_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
+        | "cuda_device::float::rcp_rz_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rcp,
+                ScalarMathPrecisionAttr::Rz,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0792");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rcp_rz_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
+        | "cuda_device::float::rsqrt_approx_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rsqrt,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0802");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rsqrt_approx_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
+        | "cuda_device::float::rsqrt_approx_f64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F64,
+                ScalarMathOperationAttr::Rsqrt,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0804");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rsqrt_approx_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
+        | "cuda_device::float::rsqrt_approx_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Rsqrt,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0803");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "rsqrt_approx_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
+        | "cuda_device::float::sin_approx_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sin,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0782");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sin_approx_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
+        | "cuda_device::float::sin_approx_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sin,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0783");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sin_approx_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
+        | "cuda_device::float::sqrt_approx_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0805");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_approx_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
+        | "cuda_device::float::sqrt_approx_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0806");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_approx_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
+        | "cuda_device::float::sqrt_rm_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rm,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0811");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rm_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
+        | "cuda_device::float::sqrt_rm_f64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F64,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rm,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0817");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rm_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
+        | "cuda_device::float::sqrt_rm_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rm,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0812");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rm_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
+        | "cuda_device::float::sqrt_rn_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rn,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0807");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rn_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
+        | "cuda_device::float::sqrt_rn_f64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F64,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rn,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0815");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rn_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
+        | "cuda_device::float::sqrt_rn_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rn,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0808");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rn_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
+        | "cuda_device::float::sqrt_rp_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rp,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0813");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rp_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
+        | "cuda_device::float::sqrt_rp_f64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F64,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rp,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0818");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rp_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
+        | "cuda_device::float::sqrt_rp_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rp,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0814");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rp_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
+        | "cuda_device::float::sqrt_rz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rz,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0809");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
+        | "cuda_device::float::sqrt_rz_f64" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F64,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rz,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0816");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rz_f64 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
+        | "cuda_device::float::sqrt_rz_ftz_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Sqrt,
+                ScalarMathPrecisionAttr::Rz,
+                ScalarMathSubnormalAttr::Ftz,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0810");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "sqrt_rz_ftz_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
+        | "cuda_device::float::tanh_approx_f32" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (arg0, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let intrinsic = ScalarMathOp::build(
+                ctx,
+                arg0,
+                ScalarMathFormatAttr::F32,
+                ScalarMathOperationAttr::Tanh,
+                ScalarMathPrecisionAttr::Approx,
+                ScalarMathSubnormalAttr::Preserve,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0821");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                intrinsic,
+                value_map,
+                block_map,
+                loc,
+                "tanh_approx_f32 call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs
new file mode 100644
index 0000000000..b057716084
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs
@@ -0,0 +1,8939 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `sparse_mma` intrinsics.
+
+use super::helpers::{
+    GeneratedMmaImportAdapter, bundle_generated_mma_results, import_generated_mma_operands,
+    require_arity,
+};
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr,
+    SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0219");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k128_s32_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0223");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k128_s32_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0220");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k128_s32_s4_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0224");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k128_s32_s4_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0221");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k128_s32_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0222");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k128_s32_u4_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0226");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k128_s32_u4_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
+        | "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0225");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k128_s32_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0163");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k32_s32_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0167");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k32_s32_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0164");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k32_s32_s8_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0168");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k32_s32_s8_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0165");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k32_s32_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0166");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k32_s32_u8_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0170");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k32_s32_u8_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
+        | "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0169");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k32_s32_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0211");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0215");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0212");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_s4_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0216");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_s4_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0187");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0191");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0188");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_s8_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0192");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_s8_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0213");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0214");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_u4_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0218");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_u4_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0217");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0189");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0190");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_u8_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0194");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_u8_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
+        | "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Standard);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0193");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_m16n8k64_s32_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0203");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k128_s32_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0207");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0204");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0208");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0205");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k128_s32_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0206");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0210");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k128);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0209");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0171");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k32_s32_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0175");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0172");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0176");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0173");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k32_s32_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0174");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0178");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0177");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0525");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0526");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0527");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0528");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0529");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0530");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0531");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0532");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0533");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0534");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0535");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0536");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0537");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0538");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0539");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0540");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0541");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0542");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0543");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0544");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0545");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0546");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0547");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0548");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0549");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0227");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0228");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0229");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0230");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0231");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0232");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0233");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0234");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0235");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0236");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0237");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0238");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0239");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0240");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0241");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0242");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0243");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0244");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0245");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0246");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m1);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0247");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E2m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0248");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E3m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0249");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E4m3);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0250");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::E5m2);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0251");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0195");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0199");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0196");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0200");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0179");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0183");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0180");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0184");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0197");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_u4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0198");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0202");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0 or 1".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A2U32B2U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U4);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0201");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0181");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_u8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Wrapping);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0182");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::S8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0186");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
+        | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            if !matches!(&args[4], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sparse MMA selector must be the compile-time constant 0".to_owned()
+                    )
+                );
+            }
+            let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands(
+                ctx,
+                body,
+                args,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+                GeneratedMmaImportAdapter::C4I32A4U32B4U32ToD4I32,
+            )?;
+            let (metadata, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[3],
+                value_map,
+                block_ptr,
+                Some(last_op),
+                loc.clone(),
+            )?;
+            operands.push(metadata);
+            let (selector_value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[4],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            operands.push(selector_value);
+            let mma = Operation::new(
+                ctx,
+                SparseMmaOp::get_concrete_op_info(),
+                vec![result_ty; result_count],
+                operands,
+                vec![],
+                0,
+            );
+            mma.deref_mut(ctx).set_loc(loc.clone());
+            let mma = SparseMmaOp::new(mma);
+            mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k64);
+            mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::S32);
+            mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::U8);
+            mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::Satfinite);
+            mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered);
+            mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZero);
+            let mma = mma.get_operation();
+            helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i0185");
+            helpers::insert_op(ctx, mma, block_ptr, last_op);
+            let (result, last_op) =
+                bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone());
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                last_op,
+                value_map,
+                block_map,
+                loc,
+                "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs
new file mode 100644
index 0000000000..a58ee1883d
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs
@@ -0,0 +1,764 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `sreg` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    ReadPtxSregClock64Op, ReadPtxSregClockOp, ReadPtxSregClusterCtaidXOp,
+    ReadPtxSregClusterCtaidYOp, ReadPtxSregClusterCtaidZOp, ReadPtxSregClusterCtarankOp,
+    ReadPtxSregClusterIdXOp, ReadPtxSregClusterIdYOp, ReadPtxSregClusterIdZOp,
+    ReadPtxSregClusterNctaidXOp, ReadPtxSregClusterNctaidYOp, ReadPtxSregClusterNctaidZOp,
+    ReadPtxSregClusterNctarankOp, ReadPtxSregCtaidXOp, ReadPtxSregCtaidYOp, ReadPtxSregCtaidZOp,
+    ReadPtxSregDynamicSmemSizeOp, ReadPtxSregEnvReg1Op, ReadPtxSregEnvReg2Op,
+    ReadPtxSregGlobaltimerOp, ReadPtxSregGridIdOp, ReadPtxSregLaneIdOp, ReadPtxSregLanemaskEqOp,
+    ReadPtxSregLanemaskGeOp, ReadPtxSregLanemaskGtOp, ReadPtxSregLanemaskLeOp,
+    ReadPtxSregLanemaskLtOp, ReadPtxSregNclusterIdXOp, ReadPtxSregNclusterIdYOp,
+    ReadPtxSregNclusterIdZOp, ReadPtxSregNctaidXOp, ReadPtxSregNctaidYOp, ReadPtxSregNctaidZOp,
+    ReadPtxSregNsmIdOp, ReadPtxSregNtidXOp, ReadPtxSregNtidYOp, ReadPtxSregNtidZOp,
+    ReadPtxSregNwarpIdOp, ReadPtxSregSmIdOp, ReadPtxSregTidXOp, ReadPtxSregTidYOp,
+    ReadPtxSregTidZOp, ReadPtxSregTotalSmemSizeOp, ReadPtxSregWarpIdOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::Location;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    _body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
+        | "cuda_device::thread::blockDim_x"
+        | "cuda_device::blockDim_x" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNtidXOp::get_concrete_op_info(),
+                "v1:i0003",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
+        | "cuda_device::thread::blockDim_y"
+        | "cuda_device::blockDim_y" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNtidYOp::get_concrete_op_info(),
+                "v1:i0007",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
+        | "cuda_device::thread::blockDim_z"
+        | "cuda_device::blockDim_z" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNtidZOp::get_concrete_op_info(),
+                "v1:i0011",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
+        | "cuda_device::thread::blockIdx_x"
+        | "cuda_device::blockIdx_x" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregCtaidXOp::get_concrete_op_info(),
+                "v1:i0002",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
+        | "cuda_device::thread::blockIdx_y"
+        | "cuda_device::blockIdx_y" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregCtaidYOp::get_concrete_op_info(),
+                "v1:i0006",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
+        | "cuda_device::thread::blockIdx_z"
+        | "cuda_device::blockIdx_z" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregCtaidZOp::get_concrete_op_info(),
+                "v1:i0010",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283" | "cuda_device::debug::clock" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClockOp::get_concrete_op_info(),
+                "v1:i0283",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284" | "cuda_device::debug::clock64" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic_u64(
+                ctx,
+                ReadPtxSregClock64Op::get_concrete_op_info(),
+                "v1:i0284",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterNctarankOp::get_concrete_op_info(),
+                "v1:i0276",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
+        | "cuda_device::cluster::cluster_ctaidX" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterCtaidXOp::get_concrete_op_info(),
+                "v1:i0263",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
+        | "cuda_device::cluster::cluster_ctaidY" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterCtaidYOp::get_concrete_op_info(),
+                "v1:i0264",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
+        | "cuda_device::cluster::cluster_ctaidZ" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterCtaidZOp::get_concrete_op_info(),
+                "v1:i0265",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterCtarankOp::get_concrete_op_info(),
+                "v1:i0275",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
+        | "cuda_device::cluster::cluster_nctaidX" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterNctaidXOp::get_concrete_op_info(),
+                "v1:i0266",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
+        | "cuda_device::cluster::cluster_nctaidY" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterNctaidYOp::get_concrete_op_info(),
+                "v1:i0267",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
+        | "cuda_device::cluster::cluster_nctaidZ" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterNctaidZOp::get_concrete_op_info(),
+                "v1:i0268",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
+        | "cuda_device::cluster::__cluster_grid_dimX" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNclusterIdXOp::get_concrete_op_info(),
+                "v1:i0272",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
+        | "cuda_device::cluster::__cluster_grid_dimY" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNclusterIdYOp::get_concrete_op_info(),
+                "v1:i0273",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
+        | "cuda_device::cluster::__cluster_grid_dimZ" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNclusterIdZOp::get_concrete_op_info(),
+                "v1:i0274",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
+        | "cuda_device::cluster::__cluster_idxX" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterIdXOp::get_concrete_op_info(),
+                "v1:i0269",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
+        | "cuda_device::cluster::__cluster_idxY" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterIdYOp::get_concrete_op_info(),
+                "v1:i0270",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
+        | "cuda_device::cluster::__cluster_idxZ" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregClusterIdZOp::get_concrete_op_info(),
+                "v1:i0271",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
+        | "cuda_device::shared::dynamic_smem_size" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregDynamicSmemSizeOp::get_concrete_op_info(),
+                "v1:i0293",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286" | "cuda_device::grid::envreg1" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregEnvReg1Op::get_concrete_op_info(),
+                "v1:i0286",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287" | "cuda_device::grid::envreg2" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregEnvReg2Op::get_concrete_op_info(),
+                "v1:i0287",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
+        | "cuda_device::debug::globaltimer" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic_u64(
+                ctx,
+                ReadPtxSregGlobaltimerOp::get_concrete_op_info(),
+                "v1:i0285",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
+        | "cuda_device::thread::gridDim_x"
+        | "cuda_device::gridDim_x" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNctaidXOp::get_concrete_op_info(),
+                "v1:i0004",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
+        | "cuda_device::thread::gridDim_y"
+        | "cuda_device::gridDim_y" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNctaidYOp::get_concrete_op_info(),
+                "v1:i0008",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
+        | "cuda_device::thread::gridDim_z"
+        | "cuda_device::gridDim_z" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNctaidZOp::get_concrete_op_info(),
+                "v1:i0012",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
+        | "cuda_device::thread::gridid"
+        | "cuda_device::gridid" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic_u64(
+                ctx,
+                ReadPtxSregGridIdOp::get_concrete_op_info(),
+                "v1:i0290",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016" | "cuda_device::warp::lane_id" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregLaneIdOp::get_concrete_op_info(),
+                "v1:i0016",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
+        | "cuda_device::warp::lanemask_eq" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregLanemaskEqOp::get_concrete_op_info(),
+                "v1:i0037",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
+        | "cuda_device::warp::lanemask_ge" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregLanemaskGeOp::get_concrete_op_info(),
+                "v1:i0038",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
+        | "cuda_device::warp::lanemask_gt" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregLanemaskGtOp::get_concrete_op_info(),
+                "v1:i0039",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
+        | "cuda_device::warp::lanemask_le" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregLanemaskLeOp::get_concrete_op_info(),
+                "v1:i0036",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
+        | "cuda_device::warp::lanemask_lt" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregLanemaskLtOp::get_concrete_op_info(),
+                "v1:i0035",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
+        | "cuda_device::thread::nsmid"
+        | "cuda_device::nsmid" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNsmIdOp::get_concrete_op_info(),
+                "v1:i0289",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292" | "cuda_device::warp::nwarpid" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregNwarpIdOp::get_concrete_op_info(),
+                "v1:i0292",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
+        | "cuda_device::thread::smid"
+        | "cuda_device::smid" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregSmIdOp::get_concrete_op_info(),
+                "v1:i0288",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
+        | "cuda_device::thread::threadIdx_x"
+        | "cuda_device::threadIdx_x" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregTidXOp::get_concrete_op_info(),
+                "v1:i0001",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
+        | "cuda_device::thread::threadIdx_y"
+        | "cuda_device::threadIdx_y" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregTidYOp::get_concrete_op_info(),
+                "v1:i0005",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
+        | "cuda_device::thread::threadIdx_z"
+        | "cuda_device::threadIdx_z" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregTidZOp::get_concrete_op_info(),
+                "v1:i0009",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
+        | "cuda_device::shared::total_smem_size" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregTotalSmemSizeOp::get_concrete_op_info(),
+                "v1:i0294",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291" | "cuda_device::warp::warpid" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            Ok(Some(helpers::emit_generated_nvvm_intrinsic(
+                ctx,
+                ReadPtxSregWarpIdOp::get_concrete_op_info(),
+                "v1:i0291",
+                destination,
+                target,
+                block_ptr,
+                prev_op,
+                value_map,
+                block_map,
+                loc,
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs
new file mode 100644
index 0000000000..f7809f4f65
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs
@@ -0,0 +1,227 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `stmatrix` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    StmatrixM8n8X2Op, StmatrixM8n8X2TransOp, StmatrixM8n8X4Op, StmatrixM8n8X4TransOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
+        | "cuda_device::tcgen05::stmatrix_m8n8_x2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let store = Operation::new(
+                ctx,
+                StmatrixM8n8X2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            store.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, store, "v1:i0301");
+            helpers::insert_op(ctx, store, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    store,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "stmatrix_m8n8_x2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
+        | "cuda_device::tcgen05::stmatrix_m8n8_x2_trans" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let store = Operation::new(
+                ctx,
+                StmatrixM8n8X2TransOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            store.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, store, "v1:i0302");
+            helpers::insert_op(ctx, store, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    store,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "stmatrix_m8n8_x2_trans call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
+        | "cuda_device::tcgen05::stmatrix_m8n8_x4" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let store = Operation::new(
+                ctx,
+                StmatrixM8n8X4Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            store.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, store, "v1:i0303");
+            helpers::insert_op(ctx, store, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    store,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "stmatrix_m8n8_x4 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
+        | "cuda_device::tcgen05::stmatrix_m8n8_x4_trans" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let store = Operation::new(
+                ctx,
+                StmatrixM8n8X4TransOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            store.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, store, "v1:i0304");
+            helpers::insert_op(ctx, store, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    store,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "stmatrix_m8n8_x4_trans call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs
new file mode 100644
index 0000000000..b2cc10f8f6
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs
@@ -0,0 +1,167 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `sync` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{Barrier0Op, ThreadfenceBlockOp, ThreadfenceOp, ThreadfenceSystemOp};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    _body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    _value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
+        | "cuda_device::thread::sync_threads"
+        | "cuda_device::sync_threads" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let barrier = Operation::new(
+                ctx,
+                Barrier0Op::get_concrete_op_info(),
+                vec![],
+                vec![],
+                vec![],
+                0,
+            );
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0034");
+            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "sync_threads call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
+        | "cuda_device::fence::threadfence"
+        | "cuda_device::threadfence" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let barrier = Operation::new(
+                ctx,
+                ThreadfenceOp::get_concrete_op_info(),
+                vec![],
+                vec![],
+                vec![],
+                0,
+            );
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0299");
+            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported("threadfence call without target block".to_owned())
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
+        | "cuda_device::fence::threadfence_block"
+        | "cuda_device::threadfence_block" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let barrier = Operation::new(
+                ctx,
+                ThreadfenceBlockOp::get_concrete_op_info(),
+                vec![],
+                vec![],
+                vec![],
+                0,
+            );
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0298");
+            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "threadfence_block call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
+        | "cuda_device::fence::threadfence_system"
+        | "cuda_device::threadfence_system" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let barrier = Operation::new(
+                ctx,
+                ThreadfenceSystemOp::get_concrete_op_info(),
+                vec![],
+                vec![],
+                vec![],
+                0,
+            );
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0300");
+            helpers::insert_op(ctx, barrier, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "threadfence_system call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs
new file mode 100644
index 0000000000..ec8811eb71
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs
@@ -0,0 +1,1631 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `tcgen05_cp` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    Tcgen05Cp4x256bB4x16P64Cg2Op, Tcgen05Cp4x256bB4x16P64Op, Tcgen05Cp4x256bB6x16P32Cg2Op,
+    Tcgen05Cp4x256bB6x16P32Op, Tcgen05Cp4x256bCg2Op, Tcgen05Cp4x256bOp,
+    Tcgen05Cp32x128bWarpx4B4x16P64Cg2Op, Tcgen05Cp32x128bWarpx4B4x16P64Op,
+    Tcgen05Cp32x128bWarpx4B6x16P32Cg2Op, Tcgen05Cp32x128bWarpx4B6x16P32Op,
+    Tcgen05Cp32x128bWarpx4Cg2Op, Tcgen05Cp32x128bWarpx4Op,
+    Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Op,
+    Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Op,
+    Tcgen05Cp64x128bWarpx2Pair0123Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123Op,
+    Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Op,
+    Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Op,
+    Tcgen05Cp64x128bWarpx2Pair0213Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213Op,
+    Tcgen05Cp128x128bB4x16P64Cg2Op, Tcgen05Cp128x128bB4x16P64Op, Tcgen05Cp128x128bB6x16P32Cg2Op,
+    Tcgen05Cp128x128bB6x16P32Op, Tcgen05Cp128x128bCg2Op, Tcgen05Cp128x128bOp,
+    Tcgen05Cp128x256bB4x16P64Cg2Op, Tcgen05Cp128x256bB4x16P64Op, Tcgen05Cp128x256bB6x16P32Cg2Op,
+    Tcgen05Cp128x256bB6x16P32Op,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp128x128bOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0582");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_128x128b call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp128x128bB4x16P64Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0578");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_128x128b_b4x16_p64 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp128x128bB4x16P64Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0579");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_128x128b_b4x16_p64_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp128x128bB6x16P32Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0580");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_128x128b_b6x16_p32 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp128x128bB6x16P32Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0581");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_128x128b_b6x16_p32_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
+        | "cuda_device::tcgen05::tcgen05_cp_128x128b_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp128x128bCg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0583");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_128x128b_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
+        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp128x256bB4x16P64Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0584");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_128x256b_b4x16_p64 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
+        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp128x256bB4x16P64Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0585");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_128x256b_b4x16_p64_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
+        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp128x256bB6x16P32Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0586");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_128x256b_b6x16_p32 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
+        | "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp128x256bB6x16P32Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0587");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_128x256b_b6x16_p32_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp32x128bWarpx4Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0592");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_32x128b_warpx4 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp32x128bWarpx4B4x16P64Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0588");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_32x128b_warpx4_b4x16_p64 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp32x128bWarpx4B4x16P64Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0589");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp32x128bWarpx4B6x16P32Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0590");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_32x128b_warpx4_b6x16_p32 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp32x128bWarpx4B6x16P32Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0591");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
+        | "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp32x128bWarpx4Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0593");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_32x128b_warpx4_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp4x256bOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0598");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_4x256b call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp4x256bB4x16P64Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0594");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_4x256b_b4x16_p64 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp4x256bB4x16P64Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0595");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_4x256b_b4x16_p64_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp4x256bB6x16P32Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0596");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_4x256b_b6x16_p32 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp4x256bB6x16P32Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0597");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_4x256b_b6x16_p32_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
+        | "cuda_device::tcgen05::tcgen05_cp_4x256b_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp4x256bCg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0599");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_4x256b_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0123Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0604");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_01_23 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0600");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0601");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0602");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0603");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0123Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0605");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_01_23_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0213Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0610");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_02_13 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0606");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0607");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0608");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0609");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
+        | "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Cp64x128bWarpx2Pair0213Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0611");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_64x128b_warpx2_02_13_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs
new file mode 100644
index 0000000000..ef2de66ed3
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs
@@ -0,0 +1,6618 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `tcgen05_ld` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, types, values::ValueMap};
+use dialect_mir::{
+    ops::{MirConstantOp, MirConstructArrayOp, MirConstructStructOp},
+    types::MirArrayType,
+};
+use dialect_nvvm::ops::{
+    Tcgen05Ld16x32bx2X1Pack16Op, Tcgen05Ld16x32bx2X1RawOp, Tcgen05Ld16x32bx2X2Pack16Op,
+    Tcgen05Ld16x32bx2X2RawOp, Tcgen05Ld16x32bx2X4Pack16Op, Tcgen05Ld16x32bx2X4RawOp,
+    Tcgen05Ld16x32bx2X8Pack16Op, Tcgen05Ld16x32bx2X8RawOp, Tcgen05Ld16x32bx2X16Pack16Op,
+    Tcgen05Ld16x32bx2X16RawOp, Tcgen05Ld16x32bx2X32Pack16Op, Tcgen05Ld16x32bx2X32RawOp,
+    Tcgen05Ld16x32bx2X64Pack16Op, Tcgen05Ld16x32bx2X64RawOp, Tcgen05Ld16x32bx2X128Pack16Op,
+    Tcgen05Ld16x32bx2X128RawOp, Tcgen05Ld16x64bX1Pack16Op, Tcgen05Ld16x64bX1RawOp,
+    Tcgen05Ld16x64bX2Pack16Op, Tcgen05Ld16x64bX2RawOp, Tcgen05Ld16x64bX4Pack16Op,
+    Tcgen05Ld16x64bX4RawOp, Tcgen05Ld16x64bX8Pack16Op, Tcgen05Ld16x64bX8RawOp,
+    Tcgen05Ld16x64bX16Pack16Op, Tcgen05Ld16x64bX16RawOp, Tcgen05Ld16x64bX32Pack16Op,
+    Tcgen05Ld16x64bX32RawOp, Tcgen05Ld16x64bX64Pack16Op, Tcgen05Ld16x64bX64RawOp,
+    Tcgen05Ld16x64bX128Pack16Op, Tcgen05Ld16x64bX128RawOp, Tcgen05Ld16x128bX1Pack16Op,
+    Tcgen05Ld16x128bX1RawOp, Tcgen05Ld16x128bX2Pack16Op, Tcgen05Ld16x128bX2RawOp,
+    Tcgen05Ld16x128bX4Pack16Op, Tcgen05Ld16x128bX4RawOp, Tcgen05Ld16x128bX8Pack16Op,
+    Tcgen05Ld16x128bX8RawOp, Tcgen05Ld16x128bX16Pack16Op, Tcgen05Ld16x128bX16RawOp,
+    Tcgen05Ld16x128bX32Pack16Op, Tcgen05Ld16x128bX32RawOp, Tcgen05Ld16x128bX64Pack16Op,
+    Tcgen05Ld16x128bX64RawOp, Tcgen05Ld16x256bX1Pack16Op, Tcgen05Ld16x256bX1RawOp,
+    Tcgen05Ld16x256bX2Pack16Op, Tcgen05Ld16x256bX2RawOp, Tcgen05Ld16x256bX4Pack16Op,
+    Tcgen05Ld16x256bX4RawOp, Tcgen05Ld16x256bX8Pack16Op, Tcgen05Ld16x256bX8RawOp,
+    Tcgen05Ld16x256bX16Pack16Op, Tcgen05Ld16x256bX16RawOp, Tcgen05Ld16x256bX32Pack16Op,
+    Tcgen05Ld16x256bX32RawOp, Tcgen05Ld32x32bX1Pack16Op, Tcgen05Ld32x32bX1RawOp,
+    Tcgen05Ld32x32bX2Pack16Op, Tcgen05Ld32x32bX2RawOp, Tcgen05Ld32x32bX4Pack16Op,
+    Tcgen05Ld32x32bX4RawOp, Tcgen05Ld32x32bX8Pack16Op, Tcgen05Ld32x32bX8RawOp,
+    Tcgen05Ld32x32bX16Pack16Op, Tcgen05Ld32x32bX16RawOp, Tcgen05Ld32x32bX32Pack16Op,
+    Tcgen05Ld32x32bX32RawOp, Tcgen05Ld32x32bX64Pack16Op, Tcgen05Ld32x32bX64RawOp,
+    Tcgen05Ld32x32bX128Pack16Op, Tcgen05Ld32x32bX128RawOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX16Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0637");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x16_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX16RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0636");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x16_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..2).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX1Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0629");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..2)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 2);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x1_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..2).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX1RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0628");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..2)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 2);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x1_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX2Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0631");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x2_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX2RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0630");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x2_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..64).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX32Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0639");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..64)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 64);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x32_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..64).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX32RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0638");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..64)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 64);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x32_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..8).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX4Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0633");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..8)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 8);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x4_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..8).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX4RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0632");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..8)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 8);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x4_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..128).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX64Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0641");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..128)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 128);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x64_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..128).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX64RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0640");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..128)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 128);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x64_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..16).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX8Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0635");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..16)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 16);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x8_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
+        | "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..16).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x128bX8RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0634");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..16)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 16);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x128b_x8_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..64).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX16Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0651");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..64)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 64);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x16_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..64).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX16RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0650");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..64)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 64);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x16_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX1Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0643");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x1_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX1RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0642");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x1_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..8).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX2Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0645");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..8)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 8);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x2_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..8).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX2RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0644");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..8)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 8);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x2_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..128).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX32Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0653");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..128)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 128);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x32_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..128).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX32RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0652");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..128)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 128);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x32_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..16).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX4Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0647");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..16)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 16);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x4_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..16).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX4RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0646");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..16)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 16);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x4_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX8Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0649");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x8_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX8RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0648");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x8_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..128).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X128Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0743");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..128)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 128);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x128_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..128).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X128RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0742");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..128)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 128);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x128_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..16).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X16Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0737");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..16)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 16);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x16_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..16).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X16RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0736");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..16)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 16);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x16_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..1).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X1Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0729");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            let value = intrinsic;
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x1_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..1).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X1RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0728");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            let value = intrinsic;
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x1_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..2).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X2Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0731");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..2)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 2);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x2_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..2).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X2RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0730");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..2)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 2);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x2_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X32Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0739");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x32_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X32RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0738");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x32_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X4Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0733");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x4_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X4RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0732");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x4_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..64).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X64Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0741");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..64)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 64);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x64_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..64).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X64RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0740");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..64)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 64);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x64_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..8).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X8Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0735");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..8)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 8);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x8_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
+        | "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            if operands
+                .get(1)
+                .and_then(|value| value.defining_op())
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must lower to a constant".to_owned()
+                    )
+                );
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..8).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x32bx2X8RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0734");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..8)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 8);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x32bx2_x8_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..128).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX128Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0627");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..128)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 128);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x128_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..128).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX128RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0626");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..128)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 128);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x128_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..16).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX16Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0621");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..16)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 16);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x16_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..16).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX16RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0620");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..16)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 16);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x16_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..1).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX1Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0613");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            let value = intrinsic;
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x1_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..1).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX1RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0612");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            let value = intrinsic;
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x1_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..2).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX2Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0615");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..2)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 2);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x2_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..2).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX2RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0614");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..2)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 2);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x2_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX32Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0623");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x32_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX32RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0622");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x32_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX4Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0617");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x4_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX4RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0616");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x4_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..64).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX64Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0625");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..64)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 64);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x64_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..64).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX64RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0624");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..64)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 64);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x64_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..8).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX8Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0619");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..8)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 8);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x8_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
+        | "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..8).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x64bX8RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0618");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..8)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 8);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x64b_x8_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..128).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX128Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0669");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..128)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 128);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x128_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..128).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX128RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0668");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..128)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 128);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x128_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..16).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX16Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0663");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..16)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 16);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x16_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..16).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX16RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0662");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..16)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 16);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x16_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..1).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX1Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0655");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            let value = intrinsic;
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x1_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..1).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX1RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0654");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let result = intrinsic.deref(ctx).get_result(0);
+            let value = intrinsic;
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x1_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..2).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX2Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0657");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..2)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 2);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x2_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..2).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX2RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0656");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..2)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 2);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x2_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX32Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0665");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x32_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX32RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0664");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x32_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX4Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0659");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x4_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX4RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0658");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x4_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..64).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX64Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0667");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..64)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 64);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x64_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..64).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX64RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0666");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..64)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 64);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x64_raw call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..8).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX8Pack16Op::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0661");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..8)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 8);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x8_pack16 call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
+        | "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+            let result_types = (0..8).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld32x32bX8RawOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0660");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..8)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 8);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_32x32b_x8_raw call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs
new file mode 100644
index 0000000000..cb4afc3232
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs
@@ -0,0 +1,1938 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `tcgen05_mma` intrinsics.
+
+use super::helpers::{generated_tcgen05_mma_selector, require_arity};
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    Tcgen05MmaBBufferAttr, Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr,
+    Tcgen05MmaFormAttr, Tcgen05MmaKindAttr, Tcgen05MmaOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
+        | "cuda_device::tcgen05::tcgen05_mma_e2m1" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = Tcgen05MmaKindAttr::F8f6f4;
+            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;
+            let collector_a = Tcgen05MmaCollectorAAttr::Discard;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1015");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_e2m1 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
+        | "cuda_device::tcgen05::tcgen05_mma_e2m3" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = Tcgen05MmaKindAttr::F8f6f4;
+            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;
+            let collector_a = Tcgen05MmaCollectorAAttr::Discard;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1013");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_e2m3 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
+        | "cuda_device::tcgen05::tcgen05_mma_e3m2" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = Tcgen05MmaKindAttr::F8f6f4;
+            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;
+            let collector_a = Tcgen05MmaCollectorAAttr::Discard;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1014");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_e3m2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
+        | "cuda_device::tcgen05::tcgen05_mma_e4m3" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = Tcgen05MmaKindAttr::F8f6f4;
+            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;
+            let collector_a = Tcgen05MmaCollectorAAttr::Discard;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1011");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_e4m3 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
+        | "cuda_device::tcgen05::tcgen05_mma_e5m2" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = Tcgen05MmaKindAttr::F8f6f4;
+            let cta_group = Tcgen05MmaCtaGroupAttr::Cg1;
+            let collector_a = Tcgen05MmaCollectorAAttr::Discard;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i1012");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_e5m2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
+        | "cuda_device::tcgen05::__tcgen05_mma_shared" => {
+            require_arity(name, args.len(), 8, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(5usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let cta_group = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
+                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let collector_a = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
+                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
+                Some(2) => Tcgen05MmaCollectorAAttr::Fill,
+                Some(3) => Tcgen05MmaCollectorAAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA collector-A selector is outside its closed range"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Shared);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0763");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_shared call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
+        | "cuda_device::tcgen05::__tcgen05_mma_sp_shared" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let cta_group = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
+                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let collector_a = match generated_tcgen05_mma_selector(args.get(8usize)) {
+                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
+                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
+                Some(2) => Tcgen05MmaCollectorAAttr::Fill,
+                Some(3) => Tcgen05MmaCollectorAAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA collector-A selector is outside its closed range"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::SpShared);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0766");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_sp_shared call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
+        | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let cta_group = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
+                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let collector_a = match generated_tcgen05_mma_selector(args.get(8usize)) {
+                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
+                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
+                Some(2) => Tcgen05MmaCollectorAAttr::Fill,
+                Some(3) => Tcgen05MmaCollectorAAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA collector-A selector is outside its closed range"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::SpTensor);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0767");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_sp_tensor call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
+        | "cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let cta_group = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
+                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let collector_a = match generated_tcgen05_mma_selector(args.get(8usize)) {
+                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
+                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA collector-A selector is outside its closed range"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::SpTensorAshift);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0768");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_sp_tensor_ashift call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
+        | "cuda_device::tcgen05::__tcgen05_mma_tensor" => {
+            require_arity(name, args.len(), 8, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(5usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let cta_group = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
+                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let collector_a = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
+                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
+                Some(2) => Tcgen05MmaCollectorAAttr::Fill,
+                Some(3) => Tcgen05MmaCollectorAAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA collector-A selector is outside its closed range"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::Tensor);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0764");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_tensor call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
+        | "cuda_device::tcgen05::__tcgen05_mma_tensor_ashift" => {
+            require_arity(name, args.len(), 8, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(5usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let cta_group = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(1) => Tcgen05MmaCtaGroupAttr::Cg1,
+                Some(2) => Tcgen05MmaCtaGroupAttr::Cg2,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA CTA group must be the compile-time u32 constant 1 or 2"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let collector_a = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaCollectorAAttr::Discard,
+                Some(1) => Tcgen05MmaCollectorAAttr::LastUse,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA collector-A selector is outside its closed range"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::TensorAshift);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_cta_group(ctx, cta_group);
+            mma_op.set_attr_nvvm_tcgen05_mma_collector_a(ctx, collector_a);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0765");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_tensor_ashift call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_e2m1" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = Tcgen05MmaKindAttr::F8f6f4;
+            let b_buffer = Tcgen05MmaBBufferAttr::B0;
+            let b_usage = Tcgen05MmaBUsageAttr::Discard;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0781");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_e2m1 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_e2m3" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = Tcgen05MmaKindAttr::F8f6f4;
+            let b_buffer = Tcgen05MmaBBufferAttr::B0;
+            let b_usage = Tcgen05MmaBUsageAttr::Discard;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0779");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_e2m3 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_e3m2" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = Tcgen05MmaKindAttr::F8f6f4;
+            let b_buffer = Tcgen05MmaBBufferAttr::B0;
+            let b_usage = Tcgen05MmaBUsageAttr::Discard;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0780");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_e3m2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_e4m3" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = Tcgen05MmaKindAttr::F8f6f4;
+            let b_buffer = Tcgen05MmaBBufferAttr::B0;
+            let b_usage = Tcgen05MmaBUsageAttr::Discard;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0777");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_e4m3 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_e5m2" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = Tcgen05MmaKindAttr::F8f6f4;
+            let b_buffer = Tcgen05MmaBBufferAttr::B0;
+            let b_usage = Tcgen05MmaBUsageAttr::Discard;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0778");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_e5m2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_shared" => {
+            require_arity(name, args.len(), 8, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(5usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_buffer = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(0) => Tcgen05MmaBBufferAttr::B0,
+                Some(1) => Tcgen05MmaBBufferAttr::B1,
+                Some(2) => Tcgen05MmaBBufferAttr::B2,
+                Some(3) => Tcgen05MmaBBufferAttr::B3,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_usage = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaBUsageAttr::Discard,
+                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
+                Some(2) => Tcgen05MmaBUsageAttr::Fill,
+                Some(3) => Tcgen05MmaBUsageAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsShared);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0769");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_shared call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_buffer = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaBBufferAttr::B0,
+                Some(1) => Tcgen05MmaBBufferAttr::B1,
+                Some(2) => Tcgen05MmaBBufferAttr::B2,
+                Some(3) => Tcgen05MmaBBufferAttr::B3,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_usage = match generated_tcgen05_mma_selector(args.get(8usize)) {
+                Some(0) => Tcgen05MmaBUsageAttr::Discard,
+                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
+                Some(2) => Tcgen05MmaBUsageAttr::Fill,
+                Some(3) => Tcgen05MmaBUsageAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsSharedZeroColMask);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0770");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_shared_zero_col_mask call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_buffer = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaBBufferAttr::B0,
+                Some(1) => Tcgen05MmaBBufferAttr::B1,
+                Some(2) => Tcgen05MmaBBufferAttr::B2,
+                Some(3) => Tcgen05MmaBBufferAttr::B3,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_usage = match generated_tcgen05_mma_selector(args.get(8usize)) {
+                Some(0) => Tcgen05MmaBUsageAttr::Discard,
+                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
+                Some(2) => Tcgen05MmaBUsageAttr::Fill,
+                Some(3) => Tcgen05MmaBUsageAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsSpShared);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0771");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_sp_shared call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask" => {
+            require_arity(name, args.len(), 10, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5, 6];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_buffer = match generated_tcgen05_mma_selector(args.get(8usize)) {
+                Some(0) => Tcgen05MmaBBufferAttr::B0,
+                Some(1) => Tcgen05MmaBBufferAttr::B1,
+                Some(2) => Tcgen05MmaBBufferAttr::B2,
+                Some(3) => Tcgen05MmaBBufferAttr::B3,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_usage = match generated_tcgen05_mma_selector(args.get(9usize)) {
+                Some(0) => Tcgen05MmaBUsageAttr::Discard,
+                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
+                Some(2) => Tcgen05MmaBUsageAttr::Fill,
+                Some(3) => Tcgen05MmaBUsageAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsSpSharedZeroColMask);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0772");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_sp_shared_zero_col_mask call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_buffer = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaBBufferAttr::B0,
+                Some(1) => Tcgen05MmaBBufferAttr::B1,
+                Some(2) => Tcgen05MmaBBufferAttr::B2,
+                Some(3) => Tcgen05MmaBBufferAttr::B3,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_usage = match generated_tcgen05_mma_selector(args.get(8usize)) {
+                Some(0) => Tcgen05MmaBUsageAttr::Discard,
+                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
+                Some(2) => Tcgen05MmaBUsageAttr::Fill,
+                Some(3) => Tcgen05MmaBUsageAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsSpTensor);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0773");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_sp_tensor call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask" => {
+            require_arity(name, args.len(), 10, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5, 6];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_buffer = match generated_tcgen05_mma_selector(args.get(8usize)) {
+                Some(0) => Tcgen05MmaBBufferAttr::B0,
+                Some(1) => Tcgen05MmaBBufferAttr::B1,
+                Some(2) => Tcgen05MmaBBufferAttr::B2,
+                Some(3) => Tcgen05MmaBBufferAttr::B3,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_usage = match generated_tcgen05_mma_selector(args.get(9usize)) {
+                Some(0) => Tcgen05MmaBUsageAttr::Discard,
+                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
+                Some(2) => Tcgen05MmaBUsageAttr::Fill,
+                Some(3) => Tcgen05MmaBUsageAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsSpTensorZeroColMask);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0774");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_sp_tensor_zero_col_mask call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor" => {
+            require_arity(name, args.len(), 8, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(5usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_buffer = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(0) => Tcgen05MmaBBufferAttr::B0,
+                Some(1) => Tcgen05MmaBBufferAttr::B1,
+                Some(2) => Tcgen05MmaBBufferAttr::B2,
+                Some(3) => Tcgen05MmaBBufferAttr::B3,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_usage = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaBUsageAttr::Discard,
+                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
+                Some(2) => Tcgen05MmaBUsageAttr::Fill,
+                Some(3) => Tcgen05MmaBUsageAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensor);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0775");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_tensor call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
+        | "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask" => {
+            require_arity(name, args.len(), 9, &loc)?;
+            let runtime_indices: &[usize] = &[0, 1, 2, 3, 4, 5];
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(runtime_indices.len());
+            for &index in runtime_indices {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    &args[index],
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let kind = match generated_tcgen05_mma_selector(args.get(6usize)) {
+                Some(0) => Tcgen05MmaKindAttr::F16,
+                Some(1) => Tcgen05MmaKindAttr::Tf32,
+                Some(2) => Tcgen05MmaKindAttr::F8f6f4,
+                Some(3) => Tcgen05MmaKindAttr::I8,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA kind must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_buffer = match generated_tcgen05_mma_selector(args.get(7usize)) {
+                Some(0) => Tcgen05MmaBBufferAttr::B0,
+                Some(1) => Tcgen05MmaBBufferAttr::B1,
+                Some(2) => Tcgen05MmaBBufferAttr::B2,
+                Some(3) => Tcgen05MmaBBufferAttr::B3,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B buffer must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let b_usage = match generated_tcgen05_mma_selector(args.get(8usize)) {
+                Some(0) => Tcgen05MmaBUsageAttr::Discard,
+                Some(1) => Tcgen05MmaBUsageAttr::LastUse,
+                Some(2) => Tcgen05MmaBUsageAttr::Fill,
+                Some(3) => Tcgen05MmaBUsageAttr::Use,
+                _ => {
+                    return input_err!(
+                        loc.clone(),
+                        TranslationErr::unsupported(
+                            "tcgen05 MMA B usage must be a compile-time u32 constant in 0..=3"
+                                .to_owned()
+                        )
+                    );
+                }
+            };
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            let mma_op = Tcgen05MmaOp::new(intrinsic);
+            mma_op.set_attr_nvvm_tcgen05_mma_form(ctx, Tcgen05MmaFormAttr::WsTensorZeroColMask);
+            mma_op.set_attr_nvvm_tcgen05_mma_kind(ctx, kind);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_buffer(ctx, b_buffer);
+            mma_op.set_attr_nvvm_tcgen05_mma_b_usage(ctx, b_usage);
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0776");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_tensor_zero_col_mask call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs
new file mode 100644
index 0000000000..55db0afffd
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs
@@ -0,0 +1,1381 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `tcgen05_other` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, types, values::ValueMap};
+use dialect_mir::{
+    ops::{MirConstructArrayOp, MirConstructStructOp},
+    types::MirArrayType,
+};
+use dialect_nvvm::ops::{
+    Tcgen05AllocCg2Op, Tcgen05AllocOp, Tcgen05CommitCg2Op, Tcgen05CommitMulticastCg2Op,
+    Tcgen05CommitMulticastOp, Tcgen05CommitOp, Tcgen05CommitSharedClusterCg2Op,
+    Tcgen05CommitSharedClusterOp, Tcgen05CpSmemToTmemCg2Op, Tcgen05CpSmemToTmemOp,
+    Tcgen05DeallocCg2Op, Tcgen05DeallocOp, Tcgen05FenceAfterThreadSyncOp,
+    Tcgen05FenceBeforeThreadSyncOp, Tcgen05Ld16x256bPureOp, Tcgen05Ld16x256bX8PureOp,
+    Tcgen05LoadWaitOp, Tcgen05MmaF16Cg2Op, Tcgen05MmaF16Op, Tcgen05MmaWsBf16Op, Tcgen05MmaWsF16Op,
+    Tcgen05MmaWsTf32Op, Tcgen05RelinquishAllocPermitCg2Op, Tcgen05RelinquishAllocPermitOp,
+    Tcgen05ShiftDownCg2Op, Tcgen05ShiftDownOp, Tcgen05StoreWaitOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::types::FP32Type;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
+        | "cuda_device::tcgen05::tcgen05_alloc" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05AllocOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0343");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_alloc call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
+        | "cuda_device::tcgen05::tcgen05_alloc_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05AllocCg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0359");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_alloc_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
+        | "cuda_device::tcgen05::tcgen05_commit" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05CommitOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0348");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_commit call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
+        | "cuda_device::tcgen05::tcgen05_commit_cg2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05CommitCg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0363");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_commit_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
+        | "cuda_device::tcgen05::tcgen05_commit_multicast" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05CommitMulticastOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0760");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_commit_multicast call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
+        | "cuda_device::tcgen05::tcgen05_commit_multicast_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05CommitMulticastCg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0365");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_commit_multicast_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
+        | "cuda_device::tcgen05::tcgen05_commit_shared_cluster" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05CommitSharedClusterOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0349");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_commit_shared_cluster call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
+        | "cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05CommitSharedClusterCg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0364");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_commit_shared_cluster_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
+        | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05CpSmemToTmemOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0354");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_smem_to_tmem call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
+        | "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05CpSmemToTmemCg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0366");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_cp_smem_to_tmem_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
+        | "cuda_device::tcgen05::tcgen05_dealloc" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05DeallocOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0344");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_dealloc call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
+        | "cuda_device::tcgen05::tcgen05_dealloc_cg2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05DeallocCg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0360");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_dealloc_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
+        | "cuda_device::tcgen05::tcgen05_fence_after_thread_sync" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05FenceAfterThreadSyncOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0347");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_fence_after_thread_sync call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
+        | "cuda_device::tcgen05::tcgen05_fence_before_thread_sync" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05FenceBeforeThreadSyncOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0346");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_fence_before_thread_sync call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_pure" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = FP32Type::get(ctx).into();
+            let result_types = (0..4).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bPureOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0356");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..4)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 4);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_pure call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
+        | "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let result_ty: TypeHandle = FP32Type::get(ctx).into();
+            let result_types = (0..32).map(|_| result_ty).collect();
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05Ld16x256bX8PureOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0355");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            let results: Vec<Value> = (0..32)
+                .map(|index| intrinsic.deref(ctx).get_result(index))
+                .collect();
+            let array_ty = MirArrayType::get(ctx, result_ty, 32);
+            let array = Operation::new(
+                ctx,
+                MirConstructArrayOp::get_concrete_op_info(),
+                vec![array_ty.into()],
+                results,
+                vec![],
+                0,
+            );
+            array.deref_mut(ctx).set_loc(loc.clone());
+            array.insert_after(ctx, intrinsic);
+            let destination_rust_ty = match destination.ty(body.locals()) {
+                Ok(ty) => ty,
+                Err(error) => {
+                    return input_err!(
+                        loc,
+                        TranslationErr::unsupported(format!(
+                            "failed to resolve destination type for intrinsic result: {error:?}"
+                        ))
+                    );
+                }
+            };
+            let destination_ty = types::translate_type(ctx, &destination_rust_ty)?;
+            let array_result = array.deref(ctx).get_result(0);
+            let (result, value) = if destination_ty == array_result.get_type(ctx) {
+                (array_result, array)
+            } else {
+                let value = Operation::new(
+                    ctx,
+                    MirConstructStructOp::get_concrete_op_info(),
+                    vec![destination_ty],
+                    vec![array_result],
+                    vec![],
+                    0,
+                );
+                value.deref_mut(ctx).set_loc(loc.clone());
+                value.insert_after(ctx, array);
+                (value.deref(ctx).get_result(0), value)
+            };
+            helpers::set_compiler_result_bundle_marker(ctx, value);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                value,
+                value_map,
+                block_map,
+                loc,
+                "tcgen05_ld_16x256b_x8_pure call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
+        | "cuda_device::tcgen05::tcgen05_load_wait" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05LoadWaitOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0357");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_load_wait call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
+        | "cuda_device::tcgen05::tcgen05_mma_f16" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaF16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0351");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_f16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
+        | "cuda_device::tcgen05::tcgen05_mma_f16_cg2" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaF16Cg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0362");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_f16_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_bf16" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaWsBf16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0352");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_bf16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_f16" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaWsF16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0350");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_f16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
+        | "cuda_device::tcgen05::tcgen05_mma_ws_tf32" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05MmaWsTf32Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0353");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_mma_ws_tf32 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
+        | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05RelinquishAllocPermitOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0345");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_relinquish_alloc_permit call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
+        | "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05RelinquishAllocPermitCg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0361");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_relinquish_alloc_permit_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
+        | "cuda_device::tcgen05::tcgen05_shift_down" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05ShiftDownOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0761");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_shift_down call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
+        | "cuda_device::tcgen05::tcgen05_shift_down_cg2" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05ShiftDownCg2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0762");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_shift_down_cg2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
+        | "cuda_device::tcgen05::tcgen05_store_wait" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05StoreWaitOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0358");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_store_wait call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs
new file mode 100644
index 0000000000..3486693682
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs
@@ -0,0 +1,3319 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `tcgen05_st` intrinsics.
+
+use super::helpers::{import_generated_tcgen05_store_operands, require_arity};
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    Tcgen05St16x32bx2X1RawOp, Tcgen05St16x32bx2X1Unpack16Op, Tcgen05St16x32bx2X2RawOp,
+    Tcgen05St16x32bx2X2Unpack16Op, Tcgen05St16x32bx2X4RawOp, Tcgen05St16x32bx2X4Unpack16Op,
+    Tcgen05St16x32bx2X8RawOp, Tcgen05St16x32bx2X8Unpack16Op, Tcgen05St16x32bx2X16RawOp,
+    Tcgen05St16x32bx2X16Unpack16Op, Tcgen05St16x32bx2X32RawOp, Tcgen05St16x32bx2X32Unpack16Op,
+    Tcgen05St16x32bx2X64RawOp, Tcgen05St16x32bx2X64Unpack16Op, Tcgen05St16x32bx2X128RawOp,
+    Tcgen05St16x32bx2X128Unpack16Op, Tcgen05St16x64bX1RawOp, Tcgen05St16x64bX1Unpack16Op,
+    Tcgen05St16x64bX2RawOp, Tcgen05St16x64bX2Unpack16Op, Tcgen05St16x64bX4RawOp,
+    Tcgen05St16x64bX4Unpack16Op, Tcgen05St16x64bX8RawOp, Tcgen05St16x64bX8Unpack16Op,
+    Tcgen05St16x64bX16RawOp, Tcgen05St16x64bX16Unpack16Op, Tcgen05St16x64bX32RawOp,
+    Tcgen05St16x64bX32Unpack16Op, Tcgen05St16x64bX64RawOp, Tcgen05St16x64bX64Unpack16Op,
+    Tcgen05St16x64bX128RawOp, Tcgen05St16x64bX128Unpack16Op, Tcgen05St16x128bX1RawOp,
+    Tcgen05St16x128bX1Unpack16Op, Tcgen05St16x128bX2RawOp, Tcgen05St16x128bX2Unpack16Op,
+    Tcgen05St16x128bX4RawOp, Tcgen05St16x128bX4Unpack16Op, Tcgen05St16x128bX8RawOp,
+    Tcgen05St16x128bX8Unpack16Op, Tcgen05St16x128bX16RawOp, Tcgen05St16x128bX16Unpack16Op,
+    Tcgen05St16x128bX32RawOp, Tcgen05St16x128bX32Unpack16Op, Tcgen05St16x128bX64RawOp,
+    Tcgen05St16x128bX64Unpack16Op, Tcgen05St16x256bX1RawOp, Tcgen05St16x256bX1Unpack16Op,
+    Tcgen05St16x256bX2RawOp, Tcgen05St16x256bX2Unpack16Op, Tcgen05St16x256bX4RawOp,
+    Tcgen05St16x256bX4Unpack16Op, Tcgen05St16x256bX8RawOp, Tcgen05St16x256bX8Unpack16Op,
+    Tcgen05St16x256bX16RawOp, Tcgen05St16x256bX16Unpack16Op, Tcgen05St16x256bX32RawOp,
+    Tcgen05St16x256bX32Unpack16Op, Tcgen05St32x32bX1RawOp, Tcgen05St32x32bX1Unpack16Op,
+    Tcgen05St32x32bX2RawOp, Tcgen05St32x32bX2Unpack16Op, Tcgen05St32x32bX4RawOp,
+    Tcgen05St32x32bX4Unpack16Op, Tcgen05St32x32bX8RawOp, Tcgen05St32x32bX8Unpack16Op,
+    Tcgen05St32x32bX16RawOp, Tcgen05St32x32bX16Unpack16Op, Tcgen05St32x32bX32RawOp,
+    Tcgen05St32x32bX32Unpack16Op, Tcgen05St32x32bX64RawOp, Tcgen05St32x32bX64Unpack16Op,
+    Tcgen05St32x32bX128RawOp, Tcgen05St32x32bX128Unpack16Op,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                32,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX16RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0694");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x16_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                32,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX16Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0695");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x16_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                2,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX1RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0686");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x1_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                2,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX1Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0687");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x1_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                4,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX2RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0688");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x2_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                4,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX2Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0689");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x2_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                64,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX32RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0696");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x32_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                64,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX32Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0697");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x32_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                8,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX4RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0690");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x4_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                8,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX4Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0691");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x4_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                128,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX64RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0698");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x64_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                128,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX64Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0699");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x64_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                16,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX8RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0692");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x8_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
+        | "cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                16,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x128bX8Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0693");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x128b_x8_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                64,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX16RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0708");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x16_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                64,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX16Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0709");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x16_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                4,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX1RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0700");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x1_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                4,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX1Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0701");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x1_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                8,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX2RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0702");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x2_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                8,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX2Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0703");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x2_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                128,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX32RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0710");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x32_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                128,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX32Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0711");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x32_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                16,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX4RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0704");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x4_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                16,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX4Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0705");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x4_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                32,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX8RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0706");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x8_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
+        | "cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                32,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x256bX8Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0707");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x256b_x8_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                128,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X128RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0758");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x128_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                128,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X128Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0759");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x128_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                16,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X16RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0752");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x16_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                16,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X16Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0753");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x16_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                1,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X1RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0744");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x1_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                1,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X1Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0745");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x1_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                2,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X2RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0746");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x2_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                2,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X2Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0747");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x2_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                32,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X32RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0754");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x32_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                32,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X32Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0755");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x32_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                4,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X4RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0748");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x4_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                4,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X4Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0749");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x4_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                64,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X64RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0756");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x64_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                64,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X64Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0757");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x64_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                8,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X8RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0750");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x8_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
+        | "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05 16x32bx2 half-split offset must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                8,
+                true,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x32bx2X8Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0751");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x32bx2_x8_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                128,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX128RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0684");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x128_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                128,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX128Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0685");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x128_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                16,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX16RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0678");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x16_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                16,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX16Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0679");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x16_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                1,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX1RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0670");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x1_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                1,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX1Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0671");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x1_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                2,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX2RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0672");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x2_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                2,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX2Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0673");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x2_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                32,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX32RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0680");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x32_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                32,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX32Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0681");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x32_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                4,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX4RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0674");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x4_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                4,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX4Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0675");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x4_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                64,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX64RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0682");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x64_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                64,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX64Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0683");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x64_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                8,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX8RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0676");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x8_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
+        | "cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                8,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St16x64bX8Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0677");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_16x64b_x8_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                128,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX128RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0726");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x128_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                128,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX128Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0727");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x128_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                16,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX16RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0720");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x16_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                16,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX16Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0721");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x16_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                1,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX1RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0712");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x1_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                1,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX1Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0713");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x1_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                2,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX2RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0714");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x2_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                2,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX2Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0715");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x2_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                32,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX32RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0722");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x32_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                32,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX32Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0723");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x32_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                4,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX4RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0716");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x4_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                4,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX4Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0717");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x4_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                64,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX64RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0724");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x64_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                64,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX64Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0725");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x64_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                8,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX8RawOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0718");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x8_raw call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
+        | "cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (operands, last_op) = import_generated_tcgen05_store_operands(
+                ctx,
+                body,
+                args,
+                8,
+                false,
+                block_ptr,
+                prev_op,
+                value_map,
+                loc.clone(),
+            )?;
+            let intrinsic = Operation::new(
+                ctx,
+                Tcgen05St32x32bX8Unpack16Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0719");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tcgen05_st_32x32b_x8_unpack16 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs
new file mode 100644
index 0000000000..2349de51b9
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs
@@ -0,0 +1,49 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `active_mask` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn active_mask_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044"),
+        Some("v1:i0044")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0044".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::active_mask"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::active_mask"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::active_mask"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::active_mask"),
+        Some("v1:i0044")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0044"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs
new file mode 100644
index 0000000000..3053cb6690
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs
@@ -0,0 +1,229 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `clc` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn clc_query_get_first_ctaid_x_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325"),
+        Some("v1:i0325")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0325".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::clc::clc_query_get_first_ctaid_x"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::clc::clc_query_get_first_ctaid_x"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::clc::clc_query_get_first_ctaid_x"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::clc::clc_query_get_first_ctaid_x"),
+        Some("v1:i0325")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0325"
+    ));
+}
+#[test]
+fn clc_query_get_first_ctaid_y_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326"),
+        Some("v1:i0326")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0326".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::clc::clc_query_get_first_ctaid_y"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::clc::clc_query_get_first_ctaid_y"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::clc::clc_query_get_first_ctaid_y"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::clc::clc_query_get_first_ctaid_y"),
+        Some("v1:i0326")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0326"
+    ));
+}
+#[test]
+fn clc_query_get_first_ctaid_z_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327"),
+        Some("v1:i0327")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0327".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::clc::clc_query_get_first_ctaid_z"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::clc::clc_query_get_first_ctaid_z"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::clc::clc_query_get_first_ctaid_z"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::clc::clc_query_get_first_ctaid_z"),
+        Some("v1:i0327")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0327"
+    ));
+}
+#[test]
+fn clc_query_is_canceled_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324"),
+        Some("v1:i0324")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0324".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::clc::clc_query_is_canceled"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::clc::clc_query_is_canceled"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::clc::clc_query_is_canceled"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::clc::clc_query_is_canceled"),
+        Some("v1:i0324")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0324"
+    ));
+}
+#[test]
+fn clc_try_cancel_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322"),
+        Some("v1:i0322")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0322".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::clc::clc_try_cancel"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::clc::clc_try_cancel"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::clc::clc_try_cancel"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::clc::clc_try_cancel"),
+        Some("v1:i0322")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0322"
+    ));
+}
+#[test]
+fn clc_try_cancel_multicast_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323"),
+        Some("v1:i0323")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0323".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::clc::clc_try_cancel_multicast"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::clc::clc_try_cancel_multicast"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::clc::clc_try_cancel_multicast"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::clc::clc_try_cancel_multicast"),
+        Some("v1:i0323")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0323"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs
new file mode 100644
index 0000000000..598af79af8
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs
@@ -0,0 +1,229 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `cluster_barrier` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn barrier_cluster_arrive_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277"),
+        Some("v1:i0277")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0277".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::cluster::barrier_cluster_arrive"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_arrive"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_arrive"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_arrive"),
+        Some("v1:i0277")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0277"
+    ));
+}
+#[test]
+fn barrier_cluster_arrive_aligned_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278"),
+        Some("v1:i0278")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0278".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::cluster::barrier_cluster_arrive_aligned"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_arrive_aligned"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_arrive_aligned"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_arrive_aligned"),
+        Some("v1:i0278")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0278"
+    ));
+}
+#[test]
+fn barrier_cluster_arrive_relaxed_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279"),
+        Some("v1:i0279")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0279".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::cluster::barrier_cluster_arrive_relaxed"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_arrive_relaxed"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_arrive_relaxed"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_arrive_relaxed"),
+        Some("v1:i0279")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0279"
+    ));
+}
+#[test]
+fn barrier_cluster_arrive_relaxed_aligned_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280"),
+        Some("v1:i0280")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0280".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::cluster::barrier_cluster_arrive_relaxed_aligned"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_arrive_relaxed_aligned"),
+        Some("v1:i0280")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0280"
+    ));
+}
+#[test]
+fn barrier_cluster_wait_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281"),
+        Some("v1:i0281")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0281".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::cluster::barrier_cluster_wait"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_wait"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_wait"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_wait"),
+        Some("v1:i0281")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0281"
+    ));
+}
+#[test]
+fn barrier_cluster_wait_aligned_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282"),
+        Some("v1:i0282")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::cluster::barrier_cluster_wait_aligned"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_wait_aligned"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::barrier_cluster_wait_aligned"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::barrier_cluster_wait_aligned"),
+        Some("v1:i0282")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0282"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs
new file mode 100644
index 0000000000..73728072ff
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs
@@ -0,0 +1,95 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `cluster_memory` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn dsmem_read_u32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321"),
+        Some("v1:i0321")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0321".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::cluster::dsmem_read_u32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::dsmem_read_u32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::dsmem_read_u32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::dsmem_read_u32"),
+        Some("v1:i0321")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0321"
+    ));
+}
+#[test]
+fn map_shared_rank_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320"),
+        Some("v1:i0320")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0320".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::cluster::map_shared_rank"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::map_shared_rank"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::map_shared_rank"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::map_shared_rank"),
+        Some("v1:i0320")
+    );
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::map_shared_rank_mut"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::map_shared_rank_mut"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::map_shared_rank_mut"),
+        Some("v1:i0320")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0320"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs
new file mode 100644
index 0000000000..5f55375832
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs
@@ -0,0 +1,555 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `cp_async` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn cp_async_ca_16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090"),
+        Some("v1:i0090")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0090".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_ca_16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_16"),
+        Some("v1:i0090")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0090"
+    ));
+}
+#[test]
+fn cp_async_ca_4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086"),
+        Some("v1:i0086")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0086".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_ca_4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_4"),
+        Some("v1:i0086")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0086"
+    ));
+}
+#[test]
+fn cp_async_ca_8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088"),
+        Some("v1:i0088")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0088".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_ca_8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_8"),
+        Some("v1:i0088")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0088"
+    ));
+}
+#[test]
+fn cp_async_ca_zfill_16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091"),
+        Some("v1:i0091")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0091".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_ca_zfill_16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_zfill_16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_zfill_16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_zfill_16"),
+        Some("v1:i0091")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0091"
+    ));
+}
+#[test]
+fn cp_async_ca_zfill_4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087"),
+        Some("v1:i0087")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0087".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_ca_zfill_4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_zfill_4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_zfill_4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_zfill_4"),
+        Some("v1:i0087")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0087"
+    ));
+}
+#[test]
+fn cp_async_ca_zfill_8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089"),
+        Some("v1:i0089")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0089".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_ca_zfill_8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_zfill_8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_ca_zfill_8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_ca_zfill_8"),
+        Some("v1:i0089")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0089"
+    ));
+}
+#[test]
+fn cp_async_cg_16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092"),
+        Some("v1:i0092")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0092".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_cg_16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_cg_16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_cg_16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_cg_16"),
+        Some("v1:i0092")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0092"
+    ));
+}
+#[test]
+fn cp_async_cg_zfill_16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093"),
+        Some("v1:i0093")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0093".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_cg_zfill_16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_cg_zfill_16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_cg_zfill_16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_cg_zfill_16"),
+        Some("v1:i0093")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0093"
+    ));
+}
+#[test]
+fn cp_async_commit_group_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094"),
+        Some("v1:i0094")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0094".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_commit_group"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_commit_group"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_commit_group"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_commit_group"),
+        Some("v1:i0094")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0094"
+    ));
+}
+#[test]
+fn cp_async_mbarrier_arrive_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101"),
+        Some("v1:i0101")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0101".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_mbarrier_arrive"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_mbarrier_arrive"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_mbarrier_arrive"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_mbarrier_arrive"),
+        Some("v1:i0101")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0101"
+    ));
+}
+#[test]
+fn cp_async_mbarrier_arrive_noinc_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103"),
+        Some("v1:i0103")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0103".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_mbarrier_arrive_noinc"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_mbarrier_arrive_noinc"),
+        Some("v1:i0103")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0103"
+    ));
+}
+#[test]
+fn cp_async_mbarrier_arrive_noinc_shared_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104"),
+        Some("v1:i0104")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0104".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_mbarrier_arrive_noinc_shared"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::async_copy::cp_async_mbarrier_arrive_noinc_shared"
+        ),
+        Some("v1:i0104")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0104"
+    ));
+}
+#[test]
+fn cp_async_mbarrier_arrive_shared_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102"),
+        Some("v1:i0102")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0102".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_mbarrier_arrive_shared"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_mbarrier_arrive_shared"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_mbarrier_arrive_shared"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_mbarrier_arrive_shared"),
+        Some("v1:i0102")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0102"
+    ));
+}
+#[test]
+fn cp_async_wait_all_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095"),
+        Some("v1:i0095")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0095".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_wait_all"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_wait_all"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_wait_all"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_wait_all"),
+        Some("v1:i0095")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0095"
+    ));
+}
+#[test]
+fn cp_async_wait_group_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096"),
+        Some("v1:i0096")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0096".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::async_copy::cp_async_wait_group"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_wait_group"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::async_copy::cp_async_wait_group"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::async_copy::cp_async_wait_group"),
+        Some("v1:i0096")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0096"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs
new file mode 100644
index 0000000000..a1fcd6b031
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs
@@ -0,0 +1,115 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `debug_control` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn breakpoint_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296"),
+        Some("v1:i0296")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0296".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::debug::breakpoint"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::debug::breakpoint"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::debug::breakpoint"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::debug::breakpoint"),
+        Some("v1:i0296")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0296"
+    ));
+}
+#[test]
+fn pmevent_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297"),
+        Some("v1:i0297")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0297".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::debug::pmevent"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::debug::__prof_trigger"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::debug::__prof_trigger"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::debug::__prof_trigger"),
+        Some("v1:i0297")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0297"
+    ));
+}
+#[test]
+fn trap_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295"),
+        Some("v1:i0295")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0295".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path("cuda_intrinsics::debug::trap"));
+    assert!(is_generated_intrinsic_path("cuda_device::debug::trap"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::debug::trap"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::debug::trap"),
+        Some("v1:i0295")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0295"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs
new file mode 100644
index 0000000000..b60aa820de
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs
@@ -0,0 +1,157 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `dotprod` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn dp2a_s32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032"),
+        Some("v1:i0032")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0032".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::dotprod::dp2a_s32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::dotprod::dp2a_s32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::dotprod::dp2a_s32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::dotprod::dp2a_s32"),
+        Some("v1:i0032")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0032"
+    ));
+}
+#[test]
+fn dp2a_u32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033"),
+        Some("v1:i0033")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0033".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::dotprod::dp2a_u32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::dotprod::dp2a_u32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::dotprod::dp2a_u32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::dotprod::dp2a_u32"),
+        Some("v1:i0033")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0033"
+    ));
+}
+#[test]
+fn dp4a_s32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030"),
+        Some("v1:i0030")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0030".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::dotprod::dp4a_s32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::dotprod::dp4a_s32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::dotprod::dp4a_s32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::dotprod::dp4a_s32"),
+        Some("v1:i0030")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0030"
+    ));
+}
+#[test]
+fn dp4a_u32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031"),
+        Some("v1:i0031")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0031".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::dotprod::dp4a_u32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::dotprod::dp4a_u32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::dotprod::dp4a_u32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::dotprod::dp4a_u32"),
+        Some("v1:i0031")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0031"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs
new file mode 100644
index 0000000000..348cd2d4e2
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs
@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `elect` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn elect_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367"),
+        Some("v1:i0367")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0367".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::elect_sync"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::warp::elect_sync"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::elect_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::elect_sync"),
+        Some("v1:i0367")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0367"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs
new file mode 100644
index 0000000000..822811645e
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs
@@ -0,0 +1,301 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `execution_control` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn barrier_cta_arrive_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885"),
+        Some("v1:i0885")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::barrier_cta_arrive"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::barrier_cta_arrive"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::barrier_cta_arrive"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::barrier_cta_arrive"),
+        Some("v1:i0885")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0885"
+    ));
+}
+#[test]
+fn barrier_cta_arrive_aligned_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886"),
+        Some("v1:i0886")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::barrier_cta_arrive_aligned"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::barrier_cta_arrive_aligned"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::barrier_cta_arrive_aligned"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::barrier_cta_arrive_aligned"),
+        Some("v1:i0886")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0886"
+    ));
+}
+#[test]
+fn barrier_cta_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883"),
+        Some("v1:i0883")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::barrier_cta_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::barrier_cta_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::barrier_cta_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::barrier_cta_sync"),
+        Some("v1:i0883")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0883"
+    ));
+}
+#[test]
+fn barrier_cta_sync_aligned_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884"),
+        Some("v1:i0884")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::barrier_cta_sync_aligned"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::barrier_cta_sync_aligned"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::barrier_cta_sync_aligned"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::barrier_cta_sync_aligned"),
+        Some("v1:i0884")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0884"
+    ));
+}
+#[test]
+fn grid_dependency_launch_dependents_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913"),
+        Some("v1:i0913")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::grid::grid_dependency_launch_dependents"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::grid::dependency::trigger_dependents"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::grid::dependency::trigger_dependents"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::grid::dependency::trigger_dependents"),
+        Some("v1:i0913")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0913"
+    ));
+}
+#[test]
+fn grid_dependency_wait_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914"),
+        Some("v1:i0914")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0914".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::grid::grid_dependency_wait"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::grid::dependency::wait"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::grid::dependency::wait"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::grid::dependency::wait"),
+        Some("v1:i0914")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0914"
+    ));
+}
+#[test]
+fn setmaxnreg_dec_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916"),
+        Some("v1:i0916")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0916".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::thread::setmaxnreg_dec"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::__setmaxnreg_dec"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::__setmaxnreg_dec"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::__setmaxnreg_dec"),
+        Some("v1:i0916")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0916"
+    ));
+}
+#[test]
+fn setmaxnreg_inc_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915"),
+        Some("v1:i0915")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0915".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::thread::setmaxnreg_inc"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::__setmaxnreg_inc"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::__setmaxnreg_inc"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::__setmaxnreg_inc"),
+        Some("v1:i0915")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0915"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs
new file mode 100644
index 0000000000..b80e3a45dd
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs
@@ -0,0 +1,1869 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `extended_minmax` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn max_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850"),
+        Some("v1:i0850")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0850".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16::max_bf16"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::bf16::max_bf16"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16::max_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16::max_bf16"),
+        Some("v1:i0850")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0850"
+    ));
+}
+#[test]
+fn max_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842"),
+        Some("v1:i0842")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0842".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::max_f16"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16::max_f16"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::max_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::max_f16"),
+        Some("v1:i0842")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0842"
+    ));
+}
+#[test]
+fn max_ftz_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843"),
+        Some("v1:i0843")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0843".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::max_ftz_f16"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16::max_ftz_f16"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::max_ftz_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::max_ftz_f16"),
+        Some("v1:i0843")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0843"
+    ));
+}
+#[test]
+fn max_ftz_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564"),
+        Some("v1:i0564")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0564".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::max_ftz_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::max_ftz_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::max_ftz_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::max_ftz_f16x2"),
+        Some("v1:i0564")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0564"
+    ));
+}
+#[test]
+fn max_ftz_nan_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845"),
+        Some("v1:i0845")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0845".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::max_ftz_nan_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16::max_ftz_nan_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::max_ftz_nan_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::max_ftz_nan_f16"),
+        Some("v1:i0845")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0845"
+    ));
+}
+#[test]
+fn max_ftz_nan_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565"),
+        Some("v1:i0565")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0565".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::max_ftz_nan_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::max_ftz_nan_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::max_ftz_nan_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::max_ftz_nan_f16x2"),
+        Some("v1:i0565")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0565"
+    ));
+}
+#[test]
+fn max_ftz_nan_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849"),
+        Some("v1:i0849")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0849".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::max_ftz_nan_xorsign_abs_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16::max_ftz_nan_xorsign_abs_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::max_ftz_nan_xorsign_abs_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::max_ftz_nan_xorsign_abs_f16"),
+        Some("v1:i0849")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0849"
+    ));
+}
+#[test]
+fn max_ftz_nan_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567"),
+        Some("v1:i0567")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0567".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::max_ftz_nan_xorsign_abs_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::max_ftz_nan_xorsign_abs_f16x2"),
+        Some("v1:i0567")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0567"
+    ));
+}
+#[test]
+fn max_ftz_nan_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566"),
+        Some("v1:i0566")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0566".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::max_ftz_nan_xorsign_abs_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::max_ftz_nan_xorsign_abs_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::max_ftz_nan_xorsign_abs_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::max_ftz_nan_xorsign_abs_f32"),
+        Some("v1:i0566")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0566"
+    ));
+}
+#[test]
+fn max_ftz_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847"),
+        Some("v1:i0847")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0847".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::max_ftz_xorsign_abs_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16::max_ftz_xorsign_abs_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::max_ftz_xorsign_abs_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::max_ftz_xorsign_abs_f16"),
+        Some("v1:i0847")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0847"
+    ));
+}
+#[test]
+fn max_ftz_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569"),
+        Some("v1:i0569")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0569".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::max_ftz_xorsign_abs_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::max_ftz_xorsign_abs_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::max_ftz_xorsign_abs_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::max_ftz_xorsign_abs_f16x2"),
+        Some("v1:i0569")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0569"
+    ));
+}
+#[test]
+fn max_ftz_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568"),
+        Some("v1:i0568")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0568".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::max_ftz_xorsign_abs_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::max_ftz_xorsign_abs_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::max_ftz_xorsign_abs_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::max_ftz_xorsign_abs_f32"),
+        Some("v1:i0568")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0568"
+    ));
+}
+#[test]
+fn max_nan_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851"),
+        Some("v1:i0851")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0851".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16::max_nan_bf16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16::max_nan_bf16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16::max_nan_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16::max_nan_bf16"),
+        Some("v1:i0851")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0851"
+    ));
+}
+#[test]
+fn max_nan_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570"),
+        Some("v1:i0570")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0570".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::max_nan_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::max_nan_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::max_nan_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::max_nan_bf16x2"),
+        Some("v1:i0570")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0570"
+    ));
+}
+#[test]
+fn max_nan_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844"),
+        Some("v1:i0844")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0844".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::max_nan_f16"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16::max_nan_f16"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::max_nan_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::max_nan_f16"),
+        Some("v1:i0844")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0844"
+    ));
+}
+#[test]
+fn max_nan_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571"),
+        Some("v1:i0571")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0571".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::max_nan_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::max_nan_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::max_nan_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::max_nan_f16x2"),
+        Some("v1:i0571")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0571"
+    ));
+}
+#[test]
+fn max_nan_xorsign_abs_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853"),
+        Some("v1:i0853")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0853".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16::max_nan_xorsign_abs_bf16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16::max_nan_xorsign_abs_bf16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16::max_nan_xorsign_abs_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16::max_nan_xorsign_abs_bf16"),
+        Some("v1:i0853")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0853"
+    ));
+}
+#[test]
+fn max_nan_xorsign_abs_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572"),
+        Some("v1:i0572")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0572".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::max_nan_xorsign_abs_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::max_nan_xorsign_abs_bf16x2"),
+        Some("v1:i0572")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0572"
+    ));
+}
+#[test]
+fn max_nan_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848"),
+        Some("v1:i0848")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0848".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::max_nan_xorsign_abs_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16::max_nan_xorsign_abs_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::max_nan_xorsign_abs_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::max_nan_xorsign_abs_f16"),
+        Some("v1:i0848")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0848"
+    ));
+}
+#[test]
+fn max_nan_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574"),
+        Some("v1:i0574")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0574".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::max_nan_xorsign_abs_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::max_nan_xorsign_abs_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::max_nan_xorsign_abs_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::max_nan_xorsign_abs_f16x2"),
+        Some("v1:i0574")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0574"
+    ));
+}
+#[test]
+fn max_nan_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573"),
+        Some("v1:i0573")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0573".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::max_nan_xorsign_abs_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::max_nan_xorsign_abs_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::max_nan_xorsign_abs_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::max_nan_xorsign_abs_f32"),
+        Some("v1:i0573")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0573"
+    ));
+}
+#[test]
+fn max_xorsign_abs_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852"),
+        Some("v1:i0852")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0852".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16::max_xorsign_abs_bf16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16::max_xorsign_abs_bf16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16::max_xorsign_abs_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16::max_xorsign_abs_bf16"),
+        Some("v1:i0852")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0852"
+    ));
+}
+#[test]
+fn max_xorsign_abs_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575"),
+        Some("v1:i0575")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0575".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::max_xorsign_abs_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::max_xorsign_abs_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::max_xorsign_abs_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::max_xorsign_abs_bf16x2"),
+        Some("v1:i0575")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0575"
+    ));
+}
+#[test]
+fn max_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846"),
+        Some("v1:i0846")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0846".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::max_xorsign_abs_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16::max_xorsign_abs_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::max_xorsign_abs_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::max_xorsign_abs_f16"),
+        Some("v1:i0846")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0846"
+    ));
+}
+#[test]
+fn max_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577"),
+        Some("v1:i0577")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0577".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::max_xorsign_abs_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::max_xorsign_abs_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::max_xorsign_abs_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::max_xorsign_abs_f16x2"),
+        Some("v1:i0577")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0577"
+    ));
+}
+#[test]
+fn max_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576"),
+        Some("v1:i0576")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0576".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::max_xorsign_abs_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::max_xorsign_abs_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::max_xorsign_abs_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::max_xorsign_abs_f32"),
+        Some("v1:i0576")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0576"
+    ));
+}
+#[test]
+fn min_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838"),
+        Some("v1:i0838")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0838".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16::min_bf16"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::bf16::min_bf16"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16::min_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16::min_bf16"),
+        Some("v1:i0838")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0838"
+    ));
+}
+#[test]
+fn min_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830"),
+        Some("v1:i0830")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0830".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::min_f16"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16::min_f16"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::min_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::min_f16"),
+        Some("v1:i0830")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0830"
+    ));
+}
+#[test]
+fn min_ftz_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831"),
+        Some("v1:i0831")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0831".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::min_ftz_f16"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16::min_ftz_f16"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::min_ftz_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::min_ftz_f16"),
+        Some("v1:i0831")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0831"
+    ));
+}
+#[test]
+fn min_ftz_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550"),
+        Some("v1:i0550")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0550".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::min_ftz_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::min_ftz_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::min_ftz_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::min_ftz_f16x2"),
+        Some("v1:i0550")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0550"
+    ));
+}
+#[test]
+fn min_ftz_nan_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833"),
+        Some("v1:i0833")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0833".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::min_ftz_nan_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16::min_ftz_nan_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::min_ftz_nan_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::min_ftz_nan_f16"),
+        Some("v1:i0833")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0833"
+    ));
+}
+#[test]
+fn min_ftz_nan_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551"),
+        Some("v1:i0551")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0551".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::min_ftz_nan_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::min_ftz_nan_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::min_ftz_nan_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::min_ftz_nan_f16x2"),
+        Some("v1:i0551")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0551"
+    ));
+}
+#[test]
+fn min_ftz_nan_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837"),
+        Some("v1:i0837")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0837".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::min_ftz_nan_xorsign_abs_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16::min_ftz_nan_xorsign_abs_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::min_ftz_nan_xorsign_abs_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::min_ftz_nan_xorsign_abs_f16"),
+        Some("v1:i0837")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0837"
+    ));
+}
+#[test]
+fn min_ftz_nan_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553"),
+        Some("v1:i0553")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0553".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::min_ftz_nan_xorsign_abs_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::min_ftz_nan_xorsign_abs_f16x2"),
+        Some("v1:i0553")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0553"
+    ));
+}
+#[test]
+fn min_ftz_nan_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552"),
+        Some("v1:i0552")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0552".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::min_ftz_nan_xorsign_abs_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::min_ftz_nan_xorsign_abs_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::min_ftz_nan_xorsign_abs_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::min_ftz_nan_xorsign_abs_f32"),
+        Some("v1:i0552")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0552"
+    ));
+}
+#[test]
+fn min_ftz_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835"),
+        Some("v1:i0835")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0835".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::min_ftz_xorsign_abs_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16::min_ftz_xorsign_abs_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::min_ftz_xorsign_abs_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::min_ftz_xorsign_abs_f16"),
+        Some("v1:i0835")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0835"
+    ));
+}
+#[test]
+fn min_ftz_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555"),
+        Some("v1:i0555")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0555".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::min_ftz_xorsign_abs_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::min_ftz_xorsign_abs_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::min_ftz_xorsign_abs_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::min_ftz_xorsign_abs_f16x2"),
+        Some("v1:i0555")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0555"
+    ));
+}
+#[test]
+fn min_ftz_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554"),
+        Some("v1:i0554")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0554".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::min_ftz_xorsign_abs_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::min_ftz_xorsign_abs_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::min_ftz_xorsign_abs_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::min_ftz_xorsign_abs_f32"),
+        Some("v1:i0554")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0554"
+    ));
+}
+#[test]
+fn min_nan_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839"),
+        Some("v1:i0839")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0839".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16::min_nan_bf16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16::min_nan_bf16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16::min_nan_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16::min_nan_bf16"),
+        Some("v1:i0839")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0839"
+    ));
+}
+#[test]
+fn min_nan_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556"),
+        Some("v1:i0556")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0556".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::min_nan_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::min_nan_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::min_nan_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::min_nan_bf16x2"),
+        Some("v1:i0556")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0556"
+    ));
+}
+#[test]
+fn min_nan_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832"),
+        Some("v1:i0832")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0832".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::min_nan_f16"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16::min_nan_f16"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::min_nan_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::min_nan_f16"),
+        Some("v1:i0832")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0832"
+    ));
+}
+#[test]
+fn min_nan_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557"),
+        Some("v1:i0557")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0557".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::min_nan_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::min_nan_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::min_nan_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::min_nan_f16x2"),
+        Some("v1:i0557")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0557"
+    ));
+}
+#[test]
+fn min_nan_xorsign_abs_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841"),
+        Some("v1:i0841")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0841".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16::min_nan_xorsign_abs_bf16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16::min_nan_xorsign_abs_bf16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16::min_nan_xorsign_abs_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16::min_nan_xorsign_abs_bf16"),
+        Some("v1:i0841")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0841"
+    ));
+}
+#[test]
+fn min_nan_xorsign_abs_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558"),
+        Some("v1:i0558")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0558".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::min_nan_xorsign_abs_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::min_nan_xorsign_abs_bf16x2"),
+        Some("v1:i0558")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0558"
+    ));
+}
+#[test]
+fn min_nan_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836"),
+        Some("v1:i0836")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0836".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::min_nan_xorsign_abs_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16::min_nan_xorsign_abs_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::min_nan_xorsign_abs_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::min_nan_xorsign_abs_f16"),
+        Some("v1:i0836")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0836"
+    ));
+}
+#[test]
+fn min_nan_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560"),
+        Some("v1:i0560")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0560".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::min_nan_xorsign_abs_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::min_nan_xorsign_abs_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::min_nan_xorsign_abs_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::min_nan_xorsign_abs_f16x2"),
+        Some("v1:i0560")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0560"
+    ));
+}
+#[test]
+fn min_nan_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559"),
+        Some("v1:i0559")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0559".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::min_nan_xorsign_abs_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::min_nan_xorsign_abs_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::min_nan_xorsign_abs_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::min_nan_xorsign_abs_f32"),
+        Some("v1:i0559")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0559"
+    ));
+}
+#[test]
+fn min_xorsign_abs_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840"),
+        Some("v1:i0840")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0840".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16::min_xorsign_abs_bf16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16::min_xorsign_abs_bf16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16::min_xorsign_abs_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16::min_xorsign_abs_bf16"),
+        Some("v1:i0840")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0840"
+    ));
+}
+#[test]
+fn min_xorsign_abs_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561"),
+        Some("v1:i0561")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0561".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::min_xorsign_abs_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::min_xorsign_abs_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::min_xorsign_abs_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::min_xorsign_abs_bf16x2"),
+        Some("v1:i0561")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0561"
+    ));
+}
+#[test]
+fn min_xorsign_abs_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834"),
+        Some("v1:i0834")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0834".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16::min_xorsign_abs_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16::min_xorsign_abs_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16::min_xorsign_abs_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16::min_xorsign_abs_f16"),
+        Some("v1:i0834")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0834"
+    ));
+}
+#[test]
+fn min_xorsign_abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563"),
+        Some("v1:i0563")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0563".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::min_xorsign_abs_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::min_xorsign_abs_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::min_xorsign_abs_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::min_xorsign_abs_f16x2"),
+        Some("v1:i0563")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0563"
+    ));
+}
+#[test]
+fn min_xorsign_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562"),
+        Some("v1:i0562")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0562".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::min_xorsign_abs_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::min_xorsign_abs_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::min_xorsign_abs_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::min_xorsign_abs_f32"),
+        Some("v1:i0562")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0562"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs
new file mode 100644
index 0000000000..3ce62c39e8
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs
@@ -0,0 +1,293 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `integer_minmax` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn max_relu_s16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994"),
+        Some("v1:i0994")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0994".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::i16x2::max_relu_s16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::i16x2::max_relu_s16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::i16x2::max_relu_s16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::i16x2::max_relu_s16x2"),
+        Some("v1:i0994")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0994"
+    ));
+}
+#[test]
+fn max_relu_s32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988"),
+        Some("v1:i0988")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0988".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::int::max_relu_s32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::int::max_relu_s32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::int::max_relu_s32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::int::max_relu_s32"),
+        Some("v1:i0988")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0988"
+    ));
+}
+#[test]
+fn max_s16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990"),
+        Some("v1:i0990")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0990".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::i16x2::max_s16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::i16x2::max_s16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::i16x2::max_s16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::i16x2::max_s16x2"),
+        Some("v1:i0990")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0990"
+    ));
+}
+#[test]
+fn max_u16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992"),
+        Some("v1:i0992")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0992".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::i16x2::max_u16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::i16x2::max_u16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::i16x2::max_u16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::i16x2::max_u16x2"),
+        Some("v1:i0992")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0992"
+    ));
+}
+#[test]
+fn min_relu_s16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993"),
+        Some("v1:i0993")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0993".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::i16x2::min_relu_s16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::i16x2::min_relu_s16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::i16x2::min_relu_s16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::i16x2::min_relu_s16x2"),
+        Some("v1:i0993")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0993"
+    ));
+}
+#[test]
+fn min_relu_s32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987"),
+        Some("v1:i0987")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0987".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::int::min_relu_s32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::int::min_relu_s32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::int::min_relu_s32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::int::min_relu_s32"),
+        Some("v1:i0987")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0987"
+    ));
+}
+#[test]
+fn min_s16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989"),
+        Some("v1:i0989")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0989".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::i16x2::min_s16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::i16x2::min_s16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::i16x2::min_s16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::i16x2::min_s16x2"),
+        Some("v1:i0989")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0989"
+    ));
+}
+#[test]
+fn min_u16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991"),
+        Some("v1:i0991")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0991".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::i16x2::min_u16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::i16x2::min_u16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::i16x2::min_u16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::i16x2::min_u16x2"),
+        Some("v1:i0991")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0991"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs
new file mode 100644
index 0000000000..6d808470f7
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs
@@ -0,0 +1,561 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `ldmatrix` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn ldmatrix_m16n16_x1_trans_b8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378"),
+        Some("v1:i0378")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0378".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m16n16_x1_trans_b8"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0378"
+    ));
+}
+#[test]
+fn ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379"),
+        Some("v1:i0379")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0379".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0379"
+    ));
+}
+#[test]
+fn ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380"),
+        Some("v1:i0380")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0380".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0380"
+    ));
+}
+#[test]
+fn ldmatrix_m16n16_x2_trans_b8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381"),
+        Some("v1:i0381")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0381".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m16n16_x2_trans_b8"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0381"
+    ));
+}
+#[test]
+fn ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382"),
+        Some("v1:i0382")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0382".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0382"
+    ));
+}
+#[test]
+fn ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383"),
+        Some("v1:i0383")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0383".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0383"
+    ));
+}
+#[test]
+fn ldmatrix_m8n16_x1_b8x16_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384"),
+        Some("v1:i0384")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0384".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n16_x1_b8x16_b4x16_p64"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0384"
+    ));
+}
+#[test]
+fn ldmatrix_m8n16_x1_b8x16_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385"),
+        Some("v1:i0385")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0385".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n16_x1_b8x16_b6x16_p32"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0385"
+    ));
+}
+#[test]
+fn ldmatrix_m8n16_x2_b8x16_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386"),
+        Some("v1:i0386")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0386".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n16_x2_b8x16_b4x16_p64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::ldmatrix_m8n16_x2_b8x16_b4x16_p64"),
+        Some("v1:i0386")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0386"
+    ));
+}
+#[test]
+fn ldmatrix_m8n16_x2_b8x16_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387"),
+        Some("v1:i0387")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0387".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n16_x2_b8x16_b6x16_p32"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0387"
+    ));
+}
+#[test]
+fn ldmatrix_m8n16_x4_b8x16_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388"),
+        Some("v1:i0388")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0388".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n16_x4_b8x16_b4x16_p64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::ldmatrix_m8n16_x4_b8x16_b4x16_p64"),
+        Some("v1:i0388")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0388"
+    ));
+}
+#[test]
+fn ldmatrix_m8n16_x4_b8x16_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389"),
+        Some("v1:i0389")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0389".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n16_x4_b8x16_b6x16_p32"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0389"
+    ));
+}
+#[test]
+fn ldmatrix_m8n8_x1_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025"),
+        Some("v1:i0025")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0025".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n8_x1_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x1"),
+        Some("v1:i0025")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0025"
+    ));
+}
+#[test]
+fn ldmatrix_m8n8_x1_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026"),
+        Some("v1:i0026")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0026".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n8_x1_trans_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x1_trans"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x1_trans"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x1_trans"),
+        Some("v1:i0026")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0026"
+    ));
+}
+#[test]
+fn ldmatrix_m8n8_x2_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027"),
+        Some("v1:i0027")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0027".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n8_x2_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x2"),
+        Some("v1:i0027")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0027"
+    ));
+}
+#[test]
+fn ldmatrix_m8n8_x2_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028"),
+        Some("v1:i0028")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0028".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n8_x2_trans_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x2_trans"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x2_trans"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x2_trans"),
+        Some("v1:i0028")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0028"
+    ));
+}
+#[test]
+fn ldmatrix_m8n8_x4_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013"),
+        Some("v1:i0013")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0013".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n8_x4_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x4"),
+        Some("v1:i0013")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0013"
+    ));
+}
+#[test]
+fn ldmatrix_m8n8_x4_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029"),
+        Some("v1:i0029")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0029".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::ldmatrix_m8n8_x4_trans_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x4_trans"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::ldmatrix_x4_trans"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::ldmatrix_x4_trans"),
+        Some("v1:i0029")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0029"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs
new file mode 100644
index 0000000000..d459977aba
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs
@@ -0,0 +1,157 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `mbarrier_basic` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn mbarrier_arrive_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098"),
+        Some("v1:i0098")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0098".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::mbarrier_arrive"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_arrive"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_arrive"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::mbarrier_arrive"),
+        Some("v1:i0098")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0098"
+    ));
+}
+#[test]
+fn mbarrier_init_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097"),
+        Some("v1:i0097")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0097".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::mbarrier_init"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_init"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_init"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::mbarrier_init"),
+        Some("v1:i0097")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0097"
+    ));
+}
+#[test]
+fn mbarrier_inval_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100"),
+        Some("v1:i0100")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0100".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::mbarrier_inval"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_inval"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_inval"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::mbarrier_inval"),
+        Some("v1:i0100")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0100"
+    ));
+}
+#[test]
+fn mbarrier_test_wait_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099"),
+        Some("v1:i0099")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0099".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::mbarrier_test_wait"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_test_wait"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_test_wait"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::mbarrier_test_wait"),
+        Some("v1:i0099")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0099"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs
new file mode 100644
index 0000000000..cdbeba1e50
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs
@@ -0,0 +1,415 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `mbarrier_extended` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn fence_mbarrier_init_release_cluster_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313"),
+        Some("v1:i0313")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0313".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::fence_mbarrier_init_release_cluster"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::fence_mbarrier_init_release_cluster"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::fence_mbarrier_init_release_cluster"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::fence_mbarrier_init_release_cluster"),
+        Some("v1:i0313")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0313"
+    ));
+}
+#[test]
+fn fence_proxy_async_generic_acquire_shared_cluster_cluster_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315"),
+        Some("v1:i0315")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0315".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::barrier::fence_proxy_async_generic_acquire_shared_cluster_cluster"
+        ),
+        Some("v1:i0315")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0315"
+    ));
+}
+#[test]
+fn fence_proxy_async_generic_release_shared_cta_cluster_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314"),
+        Some("v1:i0314")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0314".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::fence_proxy_async_generic_release_shared_cta_cluster"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::barrier::fence_proxy_async_generic_release_shared_cta_cluster"
+        ),
+        Some("v1:i0314")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0314"
+    ));
+}
+#[test]
+fn fence_proxy_async_shared_cta_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312"),
+        Some("v1:i0312")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0312".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::fence_proxy_async_shared_cta"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::fence_proxy_async_shared_cta"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::fence_proxy_async_shared_cta"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::fence_proxy_async_shared_cta"),
+        Some("v1:i0312")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0312"
+    ));
+}
+#[test]
+fn mbarrier_arrive_cluster_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308"),
+        Some("v1:i0308")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0308".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::mbarrier_arrive_cluster"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_arrive_cluster"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_arrive_cluster"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::mbarrier_arrive_cluster"),
+        Some("v1:i0308")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0308"
+    ));
+}
+#[test]
+fn mbarrier_arrive_expect_tx_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306"),
+        Some("v1:i0306")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0306".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::mbarrier_arrive_expect_tx"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_arrive_expect_tx"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_arrive_expect_tx"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::mbarrier_arrive_expect_tx"),
+        Some("v1:i0306")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0306"
+    ));
+}
+#[test]
+fn mbarrier_arrive_expect_tx_cluster_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307"),
+        Some("v1:i0307")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0307".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::mbarrier_arrive_expect_tx_cluster"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_arrive_expect_tx_cluster"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_arrive_expect_tx_cluster"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::mbarrier_arrive_expect_tx_cluster"),
+        Some("v1:i0307")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0307"
+    ));
+}
+#[test]
+fn mbarrier_try_wait_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309"),
+        Some("v1:i0309")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0309".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::mbarrier_try_wait"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_try_wait"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_try_wait"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::mbarrier_try_wait"),
+        Some("v1:i0309")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0309"
+    ));
+}
+#[test]
+fn mbarrier_try_wait_parity_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310"),
+        Some("v1:i0310")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0310".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::mbarrier_try_wait_parity"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_try_wait_parity"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_try_wait_parity"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::mbarrier_try_wait_parity"),
+        Some("v1:i0310")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0310"
+    ));
+}
+#[test]
+fn mbarrier_try_wait_parity_cluster_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311"),
+        Some("v1:i0311")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0311".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::mbarrier_try_wait_parity_cluster"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_try_wait_parity_cluster"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::mbarrier_try_wait_parity_cluster"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::mbarrier_try_wait_parity_cluster"),
+        Some("v1:i0311")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0311"
+    ));
+}
+#[test]
+fn nanosleep_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316"),
+        Some("v1:i0316")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0316".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::barrier::nanosleep"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::barrier::nanosleep"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::barrier::nanosleep"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::barrier::nanosleep"),
+        Some("v1:i0316")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0316"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs
new file mode 100644
index 0000000000..5f34b512c5
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs
@@ -0,0 +1,74 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests, grouped per intrinsic family.
+
+use super::*;
+
+mod active_mask;
+mod clc;
+mod cluster_barrier;
+mod cluster_memory;
+mod cp_async;
+mod debug_control;
+mod dotprod;
+mod elect;
+mod execution_control;
+mod extended_minmax;
+mod integer_minmax;
+mod ldmatrix;
+mod mbarrier_basic;
+mod mbarrier_extended;
+mod movmatrix;
+mod packed_alu;
+mod packed_atomic;
+mod packed_conversion;
+mod prmt;
+mod redux;
+mod register_mma;
+mod scalar_arithmetic;
+mod scalar_conversion;
+mod scalar_math;
+mod sparse_mma;
+mod sreg;
+mod stmatrix;
+mod sync;
+mod tcgen05;
+mod tma;
+mod vote;
+mod warp_barrier;
+mod warp_match;
+mod warp_shuffle;
+mod wgmma_control;
+
+#[test]
+fn raw_intrinsic_identity_classification_fails_closed() {
+    assert_eq!(
+        classify_raw_intrinsic_path("serde", "serde::helper".into()),
+        RawIntrinsicIdentity::NotRawCrate
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0001".into()
+        ),
+        RawIntrinsicIdentity::UnsupportedAbi(_)
+    ));
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i9999".into()
+        ),
+        RawIntrinsicIdentity::UnknownId(_)
+    ));
+    assert!(matches!(
+        classify_raw_intrinsic_path("cuda_intrinsics", "cuda_intrinsics::helper".into()),
+        RawIntrinsicIdentity::UnknownId(_)
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs
new file mode 100644
index 0000000000..fdcad5f796
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs
@@ -0,0 +1,49 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `movmatrix` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn movmatrix_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305"),
+        Some("v1:i0305")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::movmatrix_trans_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::movmatrix_trans_b16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::movmatrix_trans_b16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::movmatrix_trans_b16"),
+        Some("v1:i0305")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0305"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs
new file mode 100644
index 0000000000..7354f1660a
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs
@@ -0,0 +1,1069 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `packed_alu` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn abs_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070"),
+        Some("v1:i0070")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0070".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::abs_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::abs_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::abs_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::abs_bf16x2"),
+        Some("v1:i0070")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0070"
+    ));
+}
+#[test]
+fn abs_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080"),
+        Some("v1:i0080")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0080".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::abs_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16x2::abs_f16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::abs_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::abs_f16x2"),
+        Some("v1:i0080")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0080"
+    ));
+}
+#[test]
+fn add_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064"),
+        Some("v1:i0064")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0064".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::add_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::add_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::add_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::add_bf16x2"),
+        Some("v1:i0064")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0064"
+    ));
+}
+#[test]
+fn add_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074"),
+        Some("v1:i0074")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0074".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::add_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16x2::add_f16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::add_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::add_f16x2"),
+        Some("v1:i0074")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0074"
+    ));
+}
+#[test]
+fn add_f32x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995"),
+        Some("v1:i0995")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0995".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f32x2::add_f32x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f32x2::add_f32x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f32x2::add_f32x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f32x2::add_f32x2"),
+        Some("v1:i0995")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0995"
+    ));
+}
+#[test]
+fn add_ftz_f32x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996"),
+        Some("v1:i0996")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0996".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f32x2::add_ftz_f32x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f32x2::add_ftz_f32x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f32x2::add_ftz_f32x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f32x2::add_ftz_f32x2"),
+        Some("v1:i0996")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0996"
+    ));
+}
+#[test]
+fn fma_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062"),
+        Some("v1:i0062")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0062".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::fma_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::fma_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::fma_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::fma_bf16x2"),
+        Some("v1:i0062")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0062"
+    ));
+}
+#[test]
+fn fma_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072"),
+        Some("v1:i0072")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0072".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::fma_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16x2::fma_f16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::fma_f16x2"),
+        Some("v1:i0072")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0072"
+    ));
+}
+#[test]
+fn fma_f32x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001"),
+        Some("v1:i1001")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1001".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f32x2::fma_f32x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f32x2::fma_f32x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f32x2::fma_f32x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f32x2::fma_f32x2"),
+        Some("v1:i1001")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1001"
+    ));
+}
+#[test]
+fn fma_ftz_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854"),
+        Some("v1:i0854")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0854".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::fma_ftz_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_ftz_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_ftz_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::fma_ftz_f16x2"),
+        Some("v1:i0854")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0854"
+    ));
+}
+#[test]
+fn fma_ftz_f32x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002"),
+        Some("v1:i1002")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1002".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f32x2::fma_ftz_f32x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f32x2::fma_ftz_f32x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f32x2::fma_ftz_f32x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f32x2::fma_ftz_f32x2"),
+        Some("v1:i1002")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1002"
+    ));
+}
+#[test]
+fn fma_ftz_relu_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857"),
+        Some("v1:i0857")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0857".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::fma_ftz_relu_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_ftz_relu_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_ftz_relu_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::fma_ftz_relu_f16x2"),
+        Some("v1:i0857")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0857"
+    ));
+}
+#[test]
+fn fma_ftz_sat_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856"),
+        Some("v1:i0856")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0856".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::fma_ftz_sat_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_ftz_sat_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_ftz_sat_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::fma_ftz_sat_f16x2"),
+        Some("v1:i0856")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0856"
+    ));
+}
+#[test]
+fn fma_relu_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063"),
+        Some("v1:i0063")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0063".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::fma_relu_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::fma_relu_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::fma_relu_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::fma_relu_bf16x2"),
+        Some("v1:i0063")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0063"
+    ));
+}
+#[test]
+fn fma_relu_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073"),
+        Some("v1:i0073")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0073".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::fma_relu_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_relu_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_relu_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::fma_relu_f16x2"),
+        Some("v1:i0073")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0073"
+    ));
+}
+#[test]
+fn fma_sat_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855"),
+        Some("v1:i0855")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0855".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::fma_sat_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_sat_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::fma_sat_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::fma_sat_f16x2"),
+        Some("v1:i0855")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0855"
+    ));
+}
+#[test]
+fn max_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068"),
+        Some("v1:i0068")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0068".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::max_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::max_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::max_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::max_bf16x2"),
+        Some("v1:i0068")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0068"
+    ));
+}
+#[test]
+fn max_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078"),
+        Some("v1:i0078")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0078".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::max_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16x2::max_f16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::max_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::max_f16x2"),
+        Some("v1:i0078")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0078"
+    ));
+}
+#[test]
+fn min_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067"),
+        Some("v1:i0067")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0067".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::min_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::min_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::min_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::min_bf16x2"),
+        Some("v1:i0067")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0067"
+    ));
+}
+#[test]
+fn min_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077"),
+        Some("v1:i0077")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0077".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::min_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16x2::min_f16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::min_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::min_f16x2"),
+        Some("v1:i0077")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0077"
+    ));
+}
+#[test]
+fn mul_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066"),
+        Some("v1:i0066")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::mul_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::mul_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::mul_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::mul_bf16x2"),
+        Some("v1:i0066")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0066"
+    ));
+}
+#[test]
+fn mul_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076"),
+        Some("v1:i0076")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::mul_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16x2::mul_f16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::mul_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::mul_f16x2"),
+        Some("v1:i0076")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0076"
+    ));
+}
+#[test]
+fn mul_f32x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999"),
+        Some("v1:i0999")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0999".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f32x2::mul_f32x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f32x2::mul_f32x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f32x2::mul_f32x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f32x2::mul_f32x2"),
+        Some("v1:i0999")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0999"
+    ));
+}
+#[test]
+fn mul_ftz_f32x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000"),
+        Some("v1:i1000")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1000".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f32x2::mul_ftz_f32x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f32x2::mul_ftz_f32x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f32x2::mul_ftz_f32x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f32x2::mul_ftz_f32x2"),
+        Some("v1:i1000")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1000"
+    ));
+}
+#[test]
+fn neg_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069"),
+        Some("v1:i0069")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0069".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::neg_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::neg_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::neg_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::neg_bf16x2"),
+        Some("v1:i0069")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0069"
+    ));
+}
+#[test]
+fn neg_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079"),
+        Some("v1:i0079")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0079".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::neg_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16x2::neg_f16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::neg_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::neg_f16x2"),
+        Some("v1:i0079")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0079"
+    ));
+}
+#[test]
+fn sub_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065"),
+        Some("v1:i0065")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0065".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::bf16x2::sub_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::bf16x2::sub_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::bf16x2::sub_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::bf16x2::sub_bf16x2"),
+        Some("v1:i0065")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0065"
+    ));
+}
+#[test]
+fn sub_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075"),
+        Some("v1:i0075")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0075".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f16x2::sub_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f16x2::sub_f16x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f16x2::sub_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f16x2::sub_f16x2"),
+        Some("v1:i0075")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0075"
+    ));
+}
+#[test]
+fn sub_f32x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997"),
+        Some("v1:i0997")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0997".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f32x2::sub_f32x2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::f32x2::sub_f32x2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f32x2::sub_f32x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f32x2::sub_f32x2"),
+        Some("v1:i0997")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0997"
+    ));
+}
+#[test]
+fn sub_ftz_f32x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998"),
+        Some("v1:i0998")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0998".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::f32x2::sub_ftz_f32x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::f32x2::sub_ftz_f32x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::f32x2::sub_ftz_f32x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::f32x2::sub_ftz_f32x2"),
+        Some("v1:i0998")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0998"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs
new file mode 100644
index 0000000000..f31e02ed35
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs
@@ -0,0 +1,85 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `packed_atomic` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn packed_atomic_add_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015"),
+        Some("v1:i0015")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0015".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::atomic::atom_add_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::atomic::atom_add_bf16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::atomic::atom_add_bf16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::atomic::atom_add_bf16x2"),
+        Some("v1:i0015")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0015"
+    ));
+}
+#[test]
+fn packed_atomic_add_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014"),
+        Some("v1:i0014")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0014".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::atomic::atom_add_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::atomic::atom_add_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::atomic::atom_add_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::atomic::atom_add_f16x2"),
+        Some("v1:i0014")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0014"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs
new file mode 100644
index 0000000000..a996d6eb8b
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs
@@ -0,0 +1,661 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `packed_conversion` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn cvt_f16x2_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081"),
+        Some("v1:i0081")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0081".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_f16x2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_f16x2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_f16x2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_f16x2_f32"),
+        Some("v1:i0081")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0081"
+    ));
+}
+#[test]
+fn cvt_f32x2_bf16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071"),
+        Some("v1:i0071")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0071".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_f32x2_bf16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_bf16x2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_bf16x2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_bf16x2_f32"),
+        Some("v1:i0071")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0071"
+    ));
+}
+#[test]
+fn cvt_rn_f16x2_e4m3x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826"),
+        Some("v1:i0826")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0826".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_f16x2_e4m3x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_f16x2_e4m3x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_f16x2_e4m3x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_f16x2_e4m3x2"),
+        Some("v1:i0826")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0826"
+    ));
+}
+#[test]
+fn cvt_rn_f16x2_e5m2x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828"),
+        Some("v1:i0828")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0828".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_f16x2_e5m2x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_f16x2_e5m2x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_f16x2_e5m2x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_f16x2_e5m2x2"),
+        Some("v1:i0828")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0828"
+    ));
+}
+#[test]
+fn cvt_rn_relu_bf16x2_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084"),
+        Some("v1:i0084")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0084".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_relu_bf16x2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_bf16x2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_bf16x2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_bf16x2_f32"),
+        Some("v1:i0084")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0084"
+    ));
+}
+#[test]
+fn cvt_rn_relu_f16x2_e4m3x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827"),
+        Some("v1:i0827")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0827".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_relu_f16x2_e4m3x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_f16x2_e4m3x2"),
+        Some("v1:i0827")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0827"
+    ));
+}
+#[test]
+fn cvt_rn_relu_f16x2_e5m2x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829"),
+        Some("v1:i0829")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0829".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_relu_f16x2_e5m2x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_f16x2_e5m2x2"),
+        Some("v1:i0829")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0829"
+    ));
+}
+#[test]
+fn cvt_rn_relu_f16x2_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083"),
+        Some("v1:i0083")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0083".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_relu_f16x2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_f16x2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_f16x2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_f16x2_f32"),
+        Some("v1:i0083")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0083"
+    ));
+}
+#[test]
+fn cvt_rn_satfinite_e4m3x2_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822"),
+        Some("v1:i0822")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0822".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_satfinite_e4m3x2_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_e4m3x2_f16x2"),
+        Some("v1:i0822")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0822"
+    ));
+}
+#[test]
+fn cvt_rn_satfinite_e4m3x2_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259"),
+        Some("v1:i0259")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0259".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_satfinite_e4m3x2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_e4m3x2_f32"),
+        Some("v1:i0259")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0259"
+    ));
+}
+#[test]
+fn cvt_rn_satfinite_e5m2x2_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824"),
+        Some("v1:i0824")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0824".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_satfinite_e5m2x2_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_e5m2x2_f16x2"),
+        Some("v1:i0824")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0824"
+    ));
+}
+#[test]
+fn cvt_rn_satfinite_e5m2x2_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261"),
+        Some("v1:i0261")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0261".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_satfinite_e5m2x2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_e5m2x2_f32"),
+        Some("v1:i0261")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0261"
+    ));
+}
+#[test]
+fn cvt_rn_satfinite_relu_e4m3x2_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823"),
+        Some("v1:i0823")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0823".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f16x2"),
+        Some("v1:i0823")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0823"
+    ));
+}
+#[test]
+fn cvt_rn_satfinite_relu_e4m3x2_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260"),
+        Some("v1:i0260")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0260".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_satfinite_relu_e4m3x2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_relu_e4m3x2_f32"),
+        Some("v1:i0260")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0260"
+    ));
+}
+#[test]
+fn cvt_rn_satfinite_relu_e5m2x2_f16x2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825"),
+        Some("v1:i0825")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0825".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f16x2"),
+        Some("v1:i0825")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0825"
+    ));
+}
+#[test]
+fn cvt_rn_satfinite_relu_e5m2x2_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262"),
+        Some("v1:i0262")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0262".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_satfinite_relu_e5m2x2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_relu_e5m2x2_f32"),
+        Some("v1:i0262")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0262"
+    ));
+}
+#[test]
+fn cvt_rz_bf16x2_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085"),
+        Some("v1:i0085")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0085".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rz_bf16x2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_bf16x2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_bf16x2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rz_bf16x2_f32"),
+        Some("v1:i0085")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0085"
+    ));
+}
+#[test]
+fn cvt_rz_f16x2_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082"),
+        Some("v1:i0082")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0082".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rz_f16x2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_f16x2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_f16x2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rz_f16x2_f32"),
+        Some("v1:i0082")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0082"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs
new file mode 100644
index 0000000000..75737110f1
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs
@@ -0,0 +1,247 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `prmt` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn prmt_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252"),
+        Some("v1:i0252")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0252".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path("cuda_intrinsics::prmt::prmt"));
+    assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::prmt::prmt"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::prmt::prmt"),
+        Some("v1:i0252")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0252"
+    ));
+}
+#[test]
+fn prmt_b4e_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254"),
+        Some("v1:i0254")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0254".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::prmt::prmt_b4e"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_b4e"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::prmt::prmt_b4e"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::prmt::prmt_b4e"),
+        Some("v1:i0254")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0254"
+    ));
+}
+#[test]
+fn prmt_ecl_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256"),
+        Some("v1:i0256")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0256".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::prmt::prmt_ecl"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_ecl"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::prmt::prmt_ecl"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::prmt::prmt_ecl"),
+        Some("v1:i0256")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0256"
+    ));
+}
+#[test]
+fn prmt_ecr_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257"),
+        Some("v1:i0257")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0257".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::prmt::prmt_ecr"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_ecr"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::prmt::prmt_ecr"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::prmt::prmt_ecr"),
+        Some("v1:i0257")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0257"
+    ));
+}
+#[test]
+fn prmt_f4e_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253"),
+        Some("v1:i0253")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0253".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::prmt::prmt_f4e"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_f4e"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::prmt::prmt_f4e"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::prmt::prmt_f4e"),
+        Some("v1:i0253")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0253"
+    ));
+}
+#[test]
+fn prmt_rc16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258"),
+        Some("v1:i0258")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0258".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::prmt::prmt_rc16"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_rc16"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::prmt::prmt_rc16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::prmt::prmt_rc16"),
+        Some("v1:i0258")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0258"
+    ));
+}
+#[test]
+fn prmt_rc8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255"),
+        Some("v1:i0255")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0255".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::prmt::prmt_rc8"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::prmt::prmt_rc8"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::prmt::prmt_rc8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::prmt::prmt_rc8"),
+        Some("v1:i0255")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0255"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs
new file mode 100644
index 0000000000..8b84e65644
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs
@@ -0,0 +1,589 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `redux` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn redux_sync_add_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017"),
+        Some("v1:i0017")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0017".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_add"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_add"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_add"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_add"),
+        Some("v1:i0017")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0017"
+    ));
+}
+#[test]
+fn redux_sync_and_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022"),
+        Some("v1:i0022")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0022".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_and"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_and"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_and"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_and"),
+        Some("v1:i0022")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0022"
+    ));
+}
+#[test]
+fn redux_sync_max_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009"),
+        Some("v1:i1009")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1009".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_max_abs_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_abs_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_abs_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_max_abs_f32"),
+        Some("v1:i1009")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1009"
+    ));
+}
+#[test]
+fn redux_sync_max_abs_nan_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010"),
+        Some("v1:i1010")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1010".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_max_abs_nan_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_abs_nan_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_abs_nan_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_max_abs_nan_f32"),
+        Some("v1:i1010")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1010"
+    ));
+}
+#[test]
+fn redux_sync_max_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007"),
+        Some("v1:i1007")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1007".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_max_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_max_f32"),
+        Some("v1:i1007")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1007"
+    ));
+}
+#[test]
+fn redux_sync_max_i32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021"),
+        Some("v1:i0021")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0021".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_max_i32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_i32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_i32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_max_i32"),
+        Some("v1:i0021")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0021"
+    ));
+}
+#[test]
+fn redux_sync_max_nan_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008"),
+        Some("v1:i1008")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1008".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_max_nan_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_nan_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_nan_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_max_nan_f32"),
+        Some("v1:i1008")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1008"
+    ));
+}
+#[test]
+fn redux_sync_max_u32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020"),
+        Some("v1:i0020")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0020".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_max_u32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_u32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_max_u32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_max_u32"),
+        Some("v1:i0020")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0020"
+    ));
+}
+#[test]
+fn redux_sync_min_abs_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005"),
+        Some("v1:i1005")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1005".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_min_abs_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_abs_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_abs_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_min_abs_f32"),
+        Some("v1:i1005")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1005"
+    ));
+}
+#[test]
+fn redux_sync_min_abs_nan_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006"),
+        Some("v1:i1006")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1006".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_min_abs_nan_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_abs_nan_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_abs_nan_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_min_abs_nan_f32"),
+        Some("v1:i1006")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1006"
+    ));
+}
+#[test]
+fn redux_sync_min_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003"),
+        Some("v1:i1003")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1003".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_min_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_min_f32"),
+        Some("v1:i1003")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1003"
+    ));
+}
+#[test]
+fn redux_sync_min_i32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019"),
+        Some("v1:i0019")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0019".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_min_i32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_i32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_i32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_min_i32"),
+        Some("v1:i0019")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0019"
+    ));
+}
+#[test]
+fn redux_sync_min_nan_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004"),
+        Some("v1:i1004")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1004".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_min_nan_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_nan_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_nan_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_min_nan_f32"),
+        Some("v1:i1004")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1004"
+    ));
+}
+#[test]
+fn redux_sync_min_u32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018"),
+        Some("v1:i0018")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0018".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_min_u32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_u32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_min_u32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_min_u32"),
+        Some("v1:i0018")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0018"
+    ));
+}
+#[test]
+fn redux_sync_or_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023"),
+        Some("v1:i0023")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0023".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_or"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_or"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_or"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_or"),
+        Some("v1:i0023")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0023"
+    ));
+}
+#[test]
+fn redux_sync_xor_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024"),
+        Some("v1:i0024")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0024".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::redux_sync_xor"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_xor"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::redux_sync_xor"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::redux_sync_xor"),
+        Some("v1:i0024")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0024"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs
new file mode 100644
index 0000000000..816be43a71
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs
@@ -0,0 +1,5557 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `register_mma` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn mma_m16n8k128_s32_b1_and_popc_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161"),
+        Some("v1:i0161")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0161".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k128_s32_b1_and_popc"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k128_s32_b1_and_popc"),
+        Some("v1:i0161")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0161"
+    ));
+}
+#[test]
+fn mma_m16n8k128_s32_b1_xor_popc_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158"),
+        Some("v1:i0158")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0158".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k128_s32_b1_xor_popc"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k128_s32_b1_xor_popc"),
+        Some("v1:i0158")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0158"
+    ));
+}
+#[test]
+fn mma_m16n8k16_f16_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524"),
+        Some("v1:i0524")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0524".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_f16_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_f16_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_f16_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_f16_f16"),
+        Some("v1:i0524")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0524"
+    ));
+}
+#[test]
+fn mma_m16n8k16_f32_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105"),
+        Some("v1:i0105")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0105".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_f32_bf16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_f32_bf16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_f32_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_f32_bf16"),
+        Some("v1:i0105")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0105"
+    ));
+}
+#[test]
+fn mma_m16n8k16_f32_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106"),
+        Some("v1:i0106")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0106".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_f32_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_f32_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_f32_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_f32_f16"),
+        Some("v1:i0106")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0106"
+    ));
+}
+#[test]
+fn mma_m16n8k16_fp8_f16_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504"),
+        Some("v1:i0504")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0504".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f16_e4m3_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e4m3"),
+        Some("v1:i0504")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0504"
+    ));
+}
+#[test]
+fn mma_m16n8k16_fp8_f16_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505"),
+        Some("v1:i0505")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0505".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f16_e4m3_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f16_e4m3_e5m2"),
+        Some("v1:i0505")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0505"
+    ));
+}
+#[test]
+fn mma_m16n8k16_fp8_f16_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506"),
+        Some("v1:i0506")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0506".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f16_e5m2_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e4m3"),
+        Some("v1:i0506")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0506"
+    ));
+}
+#[test]
+fn mma_m16n8k16_fp8_f16_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507"),
+        Some("v1:i0507")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0507".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f16_e5m2_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f16_e5m2_e5m2"),
+        Some("v1:i0507")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0507"
+    ));
+}
+#[test]
+fn mma_m16n8k16_fp8_f32_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508"),
+        Some("v1:i0508")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0508".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f32_e4m3_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e4m3"),
+        Some("v1:i0508")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0508"
+    ));
+}
+#[test]
+fn mma_m16n8k16_fp8_f32_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509"),
+        Some("v1:i0509")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0509".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f32_e4m3_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f32_e4m3_e5m2"),
+        Some("v1:i0509")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0509"
+    ));
+}
+#[test]
+fn mma_m16n8k16_fp8_f32_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510"),
+        Some("v1:i0510")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0510".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f32_e5m2_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e4m3"),
+        Some("v1:i0510")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0510"
+    ));
+}
+#[test]
+fn mma_m16n8k16_fp8_f32_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511"),
+        Some("v1:i0511")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0511".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_fp8_f32_e5m2_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_fp8_f32_e5m2_e5m2"),
+        Some("v1:i0511")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0511"
+    ));
+}
+#[test]
+fn mma_m16n8k16_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110"),
+        Some("v1:i0110")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0110".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_s32_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_s8"),
+        Some("v1:i0110")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0110"
+    ));
+}
+#[test]
+fn mma_m16n8k16_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117"),
+        Some("v1:i0117")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0117".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_s32_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_s8_satfinite"),
+        Some("v1:i0117")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0117"
+    ));
+}
+#[test]
+fn mma_m16n8k16_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111"),
+        Some("v1:i0111")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0111".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_s32_s8_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_s8_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_s8_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_s8_u8"),
+        Some("v1:i0111")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0111"
+    ));
+}
+#[test]
+fn mma_m16n8k16_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118"),
+        Some("v1:i0118")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0118".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_s32_s8_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_s8_u8_satfinite"),
+        Some("v1:i0118")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0118"
+    ));
+}
+#[test]
+fn mma_m16n8k16_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112"),
+        Some("v1:i0112")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0112".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_s32_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_u8"),
+        Some("v1:i0112")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0112"
+    ));
+}
+#[test]
+fn mma_m16n8k16_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113"),
+        Some("v1:i0113")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0113".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_s32_u8_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_u8_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_u8_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_u8_s8"),
+        Some("v1:i0113")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0113"
+    ));
+}
+#[test]
+fn mma_m16n8k16_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120"),
+        Some("v1:i0120")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0120".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_s32_u8_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_u8_s8_satfinite"),
+        Some("v1:i0120")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0120"
+    ));
+}
+#[test]
+fn mma_m16n8k16_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119"),
+        Some("v1:i0119")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0119".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k16_s32_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k16_s32_u8_satfinite"),
+        Some("v1:i0119")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0119"
+    ));
+}
+#[test]
+fn mma_m16n8k256_s32_b1_and_popc_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162"),
+        Some("v1:i0162")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0162".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k256_s32_b1_and_popc"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k256_s32_b1_and_popc"),
+        Some("v1:i0162")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0162"
+    ));
+}
+#[test]
+fn mma_m16n8k256_s32_b1_xor_popc_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159"),
+        Some("v1:i0159")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0159".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k256_s32_b1_xor_popc"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k256_s32_b1_xor_popc"),
+        Some("v1:i0159")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0159"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e2m1_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479"),
+        Some("v1:i0479")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0479".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m1_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m1"),
+        Some("v1:i0479")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0479"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e2m1_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480"),
+        Some("v1:i0480")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0480".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m1_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m1_e2m3"),
+        Some("v1:i0480")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0480"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e2m1_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481"),
+        Some("v1:i0481")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0481".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m1_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m1_e3m2"),
+        Some("v1:i0481")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0481"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e2m1_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482"),
+        Some("v1:i0482")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0482".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m1_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m1_e4m3"),
+        Some("v1:i0482")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0482"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e2m1_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483"),
+        Some("v1:i0483")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0483".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m1_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m1_e5m2"),
+        Some("v1:i0483")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0483"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e2m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484"),
+        Some("v1:i0484")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0484".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m3_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m1"),
+        Some("v1:i0484")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0484"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e2m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485"),
+        Some("v1:i0485")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0485".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m3_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m3_e2m3"),
+        Some("v1:i0485")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0485"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e2m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486"),
+        Some("v1:i0486")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0486".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m3_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m3_e3m2"),
+        Some("v1:i0486")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0486"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e2m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487"),
+        Some("v1:i0487")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0487".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m3_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m3_e4m3"),
+        Some("v1:i0487")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0487"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e2m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488"),
+        Some("v1:i0488")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0488".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e2m3_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e2m3_e5m2"),
+        Some("v1:i0488")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0488"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e3m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489"),
+        Some("v1:i0489")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0489".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e3m2_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m1"),
+        Some("v1:i0489")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0489"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e3m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490"),
+        Some("v1:i0490")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0490".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e3m2_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e3m2_e2m3"),
+        Some("v1:i0490")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0490"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e3m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491"),
+        Some("v1:i0491")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0491".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e3m2_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e3m2_e3m2"),
+        Some("v1:i0491")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0491"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e3m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492"),
+        Some("v1:i0492")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0492".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e3m2_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e3m2_e4m3"),
+        Some("v1:i0492")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0492"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e3m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493"),
+        Some("v1:i0493")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0493".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e3m2_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e3m2_e5m2"),
+        Some("v1:i0493")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0493"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e4m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494"),
+        Some("v1:i0494")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0494".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e4m3_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m1"),
+        Some("v1:i0494")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0494"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e4m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495"),
+        Some("v1:i0495")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0495".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e4m3_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e4m3_e2m3"),
+        Some("v1:i0495")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0495"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e4m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496"),
+        Some("v1:i0496")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0496".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e4m3_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e4m3_e3m2"),
+        Some("v1:i0496")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0496"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497"),
+        Some("v1:i0497")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0497".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e4m3_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e4m3_e4m3"),
+        Some("v1:i0497")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0497"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498"),
+        Some("v1:i0498")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0498".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e4m3_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e4m3_e5m2"),
+        Some("v1:i0498")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0498"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e5m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499"),
+        Some("v1:i0499")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0499".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e5m2_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m1"),
+        Some("v1:i0499")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0499"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e5m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500"),
+        Some("v1:i0500")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0500".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e5m2_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e5m2_e2m3"),
+        Some("v1:i0500")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0500"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e5m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501"),
+        Some("v1:i0501")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0501".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e5m2_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e5m2_e3m2"),
+        Some("v1:i0501")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0501"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502"),
+        Some("v1:i0502")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0502".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e5m2_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e5m2_e4m3"),
+        Some("v1:i0502")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0502"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f16_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503"),
+        Some("v1:i0503")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0503".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f16_e5m2_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f16_e5m2_e5m2"),
+        Some("v1:i0503")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0503"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e2m1_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454"),
+        Some("v1:i0454")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0454".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m1_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m1"),
+        Some("v1:i0454")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0454"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e2m1_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455"),
+        Some("v1:i0455")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0455".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m1_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m1_e2m3"),
+        Some("v1:i0455")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0455"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e2m1_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456"),
+        Some("v1:i0456")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0456".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m1_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m1_e3m2"),
+        Some("v1:i0456")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0456"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e2m1_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457"),
+        Some("v1:i0457")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0457".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m1_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m1_e4m3"),
+        Some("v1:i0457")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0457"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e2m1_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458"),
+        Some("v1:i0458")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0458".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m1_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m1_e5m2"),
+        Some("v1:i0458")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0458"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e2m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459"),
+        Some("v1:i0459")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0459".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m3_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m1"),
+        Some("v1:i0459")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0459"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e2m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460"),
+        Some("v1:i0460")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0460".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m3_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m3_e2m3"),
+        Some("v1:i0460")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0460"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e2m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461"),
+        Some("v1:i0461")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0461".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m3_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m3_e3m2"),
+        Some("v1:i0461")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0461"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e2m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462"),
+        Some("v1:i0462")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0462".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m3_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m3_e4m3"),
+        Some("v1:i0462")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0462"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e2m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463"),
+        Some("v1:i0463")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0463".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e2m3_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e2m3_e5m2"),
+        Some("v1:i0463")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0463"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e3m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464"),
+        Some("v1:i0464")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0464".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e3m2_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m1"),
+        Some("v1:i0464")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0464"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e3m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465"),
+        Some("v1:i0465")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0465".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e3m2_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e3m2_e2m3"),
+        Some("v1:i0465")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0465"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e3m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466"),
+        Some("v1:i0466")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0466".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e3m2_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e3m2_e3m2"),
+        Some("v1:i0466")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0466"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e3m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467"),
+        Some("v1:i0467")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0467".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e3m2_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e3m2_e4m3"),
+        Some("v1:i0467")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0467"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e3m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468"),
+        Some("v1:i0468")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0468".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e3m2_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e3m2_e5m2"),
+        Some("v1:i0468")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0468"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e4m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469"),
+        Some("v1:i0469")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0469".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e4m3_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m1"),
+        Some("v1:i0469")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0469"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e4m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470"),
+        Some("v1:i0470")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0470".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e4m3_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e4m3_e2m3"),
+        Some("v1:i0470")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0470"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e4m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471"),
+        Some("v1:i0471")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0471".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e4m3_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e4m3_e3m2"),
+        Some("v1:i0471")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0471"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472"),
+        Some("v1:i0472")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0472".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e4m3_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e4m3_e4m3"),
+        Some("v1:i0472")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0472"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473"),
+        Some("v1:i0473")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0473".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e4m3_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e4m3_e5m2"),
+        Some("v1:i0473")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0473"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e5m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474"),
+        Some("v1:i0474")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0474".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e5m2_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m1"),
+        Some("v1:i0474")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0474"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e5m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475"),
+        Some("v1:i0475")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0475".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e5m2_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e5m2_e2m3"),
+        Some("v1:i0475")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0475"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e5m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476"),
+        Some("v1:i0476")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0476".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e5m2_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e5m2_e3m2"),
+        Some("v1:i0476")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0476"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477"),
+        Some("v1:i0477")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0477".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e5m2_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e5m2_e4m3"),
+        Some("v1:i0477")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0477"
+    ));
+}
+#[test]
+fn mma_m16n8k32_f32_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478"),
+        Some("v1:i0478")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0478".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_f32_e5m2_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_f32_e5m2_e5m2"),
+        Some("v1:i0478")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0478"
+    ));
+}
+#[test]
+fn mma_m16n8k32_fp8_f16_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512"),
+        Some("v1:i0512")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0512".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f16_e4m3_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e4m3"),
+        Some("v1:i0512")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0512"
+    ));
+}
+#[test]
+fn mma_m16n8k32_fp8_f16_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513"),
+        Some("v1:i0513")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0513".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f16_e4m3_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f16_e4m3_e5m2"),
+        Some("v1:i0513")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0513"
+    ));
+}
+#[test]
+fn mma_m16n8k32_fp8_f16_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514"),
+        Some("v1:i0514")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0514".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f16_e5m2_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e4m3"),
+        Some("v1:i0514")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0514"
+    ));
+}
+#[test]
+fn mma_m16n8k32_fp8_f16_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515"),
+        Some("v1:i0515")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0515".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f16_e5m2_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f16_e5m2_e5m2"),
+        Some("v1:i0515")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0515"
+    ));
+}
+#[test]
+fn mma_m16n8k32_fp8_f32_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516"),
+        Some("v1:i0516")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0516".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f32_e4m3_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e4m3"),
+        Some("v1:i0516")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0516"
+    ));
+}
+#[test]
+fn mma_m16n8k32_fp8_f32_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517"),
+        Some("v1:i0517")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0517".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f32_e4m3_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f32_e4m3_e5m2"),
+        Some("v1:i0517")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0517"
+    ));
+}
+#[test]
+fn mma_m16n8k32_fp8_f32_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518"),
+        Some("v1:i0518")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0518".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f32_e5m2_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e4m3"),
+        Some("v1:i0518")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0518"
+    ));
+}
+#[test]
+fn mma_m16n8k32_fp8_f32_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519"),
+        Some("v1:i0519")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0519".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_fp8_f32_e5m2_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_fp8_f32_e5m2_e5m2"),
+        Some("v1:i0519")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0519"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858"),
+        Some("v1:i0858")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0858".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1"),
+        Some("v1:i0858")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0858"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859"),
+        Some("v1:i0859")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0859".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3"),
+        Some("v1:i0859")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0859"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860"),
+        Some("v1:i0860")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0860".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2"),
+        Some("v1:i0860")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0860"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861"),
+        Some("v1:i0861")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0861".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3"),
+        Some("v1:i0861")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0861"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862"),
+        Some("v1:i0862")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0862".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2"),
+        Some("v1:i0862")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0862"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863"),
+        Some("v1:i0863")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0863".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1"),
+        Some("v1:i0863")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0863"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864"),
+        Some("v1:i0864")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0864".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3"),
+        Some("v1:i0864")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0864"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865"),
+        Some("v1:i0865")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0865".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2"),
+        Some("v1:i0865")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0865"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866"),
+        Some("v1:i0866")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0866".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3"),
+        Some("v1:i0866")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0866"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867"),
+        Some("v1:i0867")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0867".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2"),
+        Some("v1:i0867")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0867"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868"),
+        Some("v1:i0868")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0868".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1"),
+        Some("v1:i0868")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0868"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869"),
+        Some("v1:i0869")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0869".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3"),
+        Some("v1:i0869")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0869"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870"),
+        Some("v1:i0870")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0870".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2"),
+        Some("v1:i0870")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0870"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871"),
+        Some("v1:i0871")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0871".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3"),
+        Some("v1:i0871")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0871"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872"),
+        Some("v1:i0872")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0872".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2"),
+        Some("v1:i0872")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0872"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873"),
+        Some("v1:i0873")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0873".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1"),
+        Some("v1:i0873")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0873"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874"),
+        Some("v1:i0874")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0874".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3"),
+        Some("v1:i0874")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0874"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875"),
+        Some("v1:i0875")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0875".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2"),
+        Some("v1:i0875")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0875"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876"),
+        Some("v1:i0876")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0876".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3"),
+        Some("v1:i0876")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0876"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877"),
+        Some("v1:i0877")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0877".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2"),
+        Some("v1:i0877")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0877"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878"),
+        Some("v1:i0878")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0878".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1"),
+        Some("v1:i0878")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0878"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879"),
+        Some("v1:i0879")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0879".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3"),
+        Some("v1:i0879")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0879"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880"),
+        Some("v1:i0880")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0880".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2"),
+        Some("v1:i0880")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0880"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881"),
+        Some("v1:i0881")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0881".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3"),
+        Some("v1:i0881")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0881"
+    ));
+}
+#[test]
+fn mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882"),
+        Some("v1:i0882")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0882".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2"),
+        Some("v1:i0882")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0882"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141"),
+        Some("v1:i0141")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0141".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s4"),
+        Some("v1:i0141")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0141"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149"),
+        Some("v1:i0149")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0149".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s4_satfinite"),
+        Some("v1:i0149")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0149"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142"),
+        Some("v1:i0142")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0142".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_s4_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s4_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s4_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s4_u4"),
+        Some("v1:i0142")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0142"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150"),
+        Some("v1:i0150")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0150".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_s4_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s4_u4_satfinite"),
+        Some("v1:i0150")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0150"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108"),
+        Some("v1:i0108")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0108".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s8"),
+        Some("v1:i0108")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0108"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121"),
+        Some("v1:i0121")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0121".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s8_satfinite"),
+        Some("v1:i0121")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0121"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114"),
+        Some("v1:i0114")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0114".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_s8_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s8_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s8_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s8_u8"),
+        Some("v1:i0114")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0114"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122"),
+        Some("v1:i0122")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0122".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_s8_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_s8_u8_satfinite"),
+        Some("v1:i0122")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0122"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143"),
+        Some("v1:i0143")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0143".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u4"),
+        Some("v1:i0143")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0143"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144"),
+        Some("v1:i0144")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0144".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_u4_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u4_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u4_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u4_s4"),
+        Some("v1:i0144")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0144"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152"),
+        Some("v1:i0152")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0152".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_u4_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u4_s4_satfinite"),
+        Some("v1:i0152")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0152"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151"),
+        Some("v1:i0151")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0151".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u4_satfinite"),
+        Some("v1:i0151")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0151"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115"),
+        Some("v1:i0115")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0115".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u8"),
+        Some("v1:i0115")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0115"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116"),
+        Some("v1:i0116")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0116".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_u8_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u8_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u8_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u8_s8"),
+        Some("v1:i0116")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0116"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124"),
+        Some("v1:i0124")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0124".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_u8_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u8_s8_satfinite"),
+        Some("v1:i0124")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0124"
+    ));
+}
+#[test]
+fn mma_m16n8k32_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123"),
+        Some("v1:i0123")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0123".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k32_s32_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k32_s32_u8_satfinite"),
+        Some("v1:i0123")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0123"
+    ));
+}
+#[test]
+fn mma_m16n8k4_f32_tf32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520"),
+        Some("v1:i0520")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0520".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k4_f32_tf32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k4_f32_tf32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k4_f32_tf32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k4_f32_tf32"),
+        Some("v1:i0520")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0520"
+    ));
+}
+#[test]
+fn mma_m16n8k64_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145"),
+        Some("v1:i0145")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0145".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k64_s32_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_s4"),
+        Some("v1:i0145")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0145"
+    ));
+}
+#[test]
+fn mma_m16n8k64_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153"),
+        Some("v1:i0153")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0153".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k64_s32_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_s4_satfinite"),
+        Some("v1:i0153")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0153"
+    ));
+}
+#[test]
+fn mma_m16n8k64_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146"),
+        Some("v1:i0146")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0146".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k64_s32_s4_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_s4_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_s4_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_s4_u4"),
+        Some("v1:i0146")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0146"
+    ));
+}
+#[test]
+fn mma_m16n8k64_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154"),
+        Some("v1:i0154")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0154".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k64_s32_s4_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_s4_u4_satfinite"),
+        Some("v1:i0154")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0154"
+    ));
+}
+#[test]
+fn mma_m16n8k64_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147"),
+        Some("v1:i0147")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0147".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k64_s32_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_u4"),
+        Some("v1:i0147")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0147"
+    ));
+}
+#[test]
+fn mma_m16n8k64_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148"),
+        Some("v1:i0148")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0148".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k64_s32_u4_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_u4_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_u4_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_u4_s4"),
+        Some("v1:i0148")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0148"
+    ));
+}
+#[test]
+fn mma_m16n8k64_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156"),
+        Some("v1:i0156")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0156".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k64_s32_u4_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_u4_s4_satfinite"),
+        Some("v1:i0156")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0156"
+    ));
+}
+#[test]
+fn mma_m16n8k64_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155"),
+        Some("v1:i0155")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0155".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k64_s32_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k64_s32_u4_satfinite"),
+        Some("v1:i0155")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0155"
+    ));
+}
+#[test]
+fn mma_m16n8k8_f16_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521"),
+        Some("v1:i0521")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0521".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k8_f16_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k8_f16_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k8_f16_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k8_f16_f16"),
+        Some("v1:i0521")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0521"
+    ));
+}
+#[test]
+fn mma_m16n8k8_f32_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522"),
+        Some("v1:i0522")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0522".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k8_f32_bf16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k8_f32_bf16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k8_f32_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k8_f32_bf16"),
+        Some("v1:i0522")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0522"
+    ));
+}
+#[test]
+fn mma_m16n8k8_f32_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523"),
+        Some("v1:i0523")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0523".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k8_f32_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k8_f32_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k8_f32_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k8_f32_f16"),
+        Some("v1:i0523")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0523"
+    ));
+}
+#[test]
+fn mma_m16n8k8_f32_tf32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107"),
+        Some("v1:i0107")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0107".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m16n8k8_f32_tf32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k8_f32_tf32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m16n8k8_f32_tf32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m16n8k8_f32_tf32"),
+        Some("v1:i0107")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0107"
+    ));
+}
+#[test]
+fn mma_m8n8k128_s32_b1_and_popc_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160"),
+        Some("v1:i0160")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0160".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k128_s32_b1_and_popc"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k128_s32_b1_and_popc"),
+        Some("v1:i0160")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0160"
+    ));
+}
+#[test]
+fn mma_m8n8k128_s32_b1_xor_popc_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157"),
+        Some("v1:i0157")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0157".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k128_s32_b1_xor_popc"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k128_s32_b1_xor_popc"),
+        Some("v1:i0157")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0157"
+    ));
+}
+#[test]
+fn mma_m8n8k16_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125"),
+        Some("v1:i0125")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0125".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k16_s32_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_s8"),
+        Some("v1:i0125")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0125"
+    ));
+}
+#[test]
+fn mma_m8n8k16_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129"),
+        Some("v1:i0129")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0129".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k16_s32_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_s8_satfinite"),
+        Some("v1:i0129")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0129"
+    ));
+}
+#[test]
+fn mma_m8n8k16_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126"),
+        Some("v1:i0126")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0126".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k16_s32_s8_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_s8_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_s8_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_s8_u8"),
+        Some("v1:i0126")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0126"
+    ));
+}
+#[test]
+fn mma_m8n8k16_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130"),
+        Some("v1:i0130")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0130".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k16_s32_s8_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_s8_u8_satfinite"),
+        Some("v1:i0130")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0130"
+    ));
+}
+#[test]
+fn mma_m8n8k16_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127"),
+        Some("v1:i0127")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0127".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k16_s32_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_u8"),
+        Some("v1:i0127")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0127"
+    ));
+}
+#[test]
+fn mma_m8n8k16_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128"),
+        Some("v1:i0128")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0128".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k16_s32_u8_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_u8_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_u8_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_u8_s8"),
+        Some("v1:i0128")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0128"
+    ));
+}
+#[test]
+fn mma_m8n8k16_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132"),
+        Some("v1:i0132")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0132".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k16_s32_u8_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_u8_s8_satfinite"),
+        Some("v1:i0132")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0132"
+    ));
+}
+#[test]
+fn mma_m8n8k16_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131"),
+        Some("v1:i0131")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0131".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k16_s32_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k16_s32_u8_satfinite"),
+        Some("v1:i0131")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0131"
+    ));
+}
+#[test]
+fn mma_m8n8k32_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133"),
+        Some("v1:i0133")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0133".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k32_s32_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_s4"),
+        Some("v1:i0133")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0133"
+    ));
+}
+#[test]
+fn mma_m8n8k32_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137"),
+        Some("v1:i0137")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0137".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k32_s32_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_s4_satfinite"),
+        Some("v1:i0137")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0137"
+    ));
+}
+#[test]
+fn mma_m8n8k32_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134"),
+        Some("v1:i0134")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0134".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k32_s32_s4_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_s4_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_s4_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_s4_u4"),
+        Some("v1:i0134")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0134"
+    ));
+}
+#[test]
+fn mma_m8n8k32_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138"),
+        Some("v1:i0138")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0138".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k32_s32_s4_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_s4_u4_satfinite"),
+        Some("v1:i0138")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0138"
+    ));
+}
+#[test]
+fn mma_m8n8k32_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135"),
+        Some("v1:i0135")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0135".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k32_s32_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_u4"),
+        Some("v1:i0135")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0135"
+    ));
+}
+#[test]
+fn mma_m8n8k32_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136"),
+        Some("v1:i0136")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0136".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k32_s32_u4_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_u4_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_u4_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_u4_s4"),
+        Some("v1:i0136")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0136"
+    ));
+}
+#[test]
+fn mma_m8n8k32_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140"),
+        Some("v1:i0140")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0140".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k32_s32_u4_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_u4_s4_satfinite"),
+        Some("v1:i0140")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0140"
+    ));
+}
+#[test]
+fn mma_m8n8k32_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139"),
+        Some("v1:i0139")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0139".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k32_s32_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k32_s32_u4_satfinite"),
+        Some("v1:i0139")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0139"
+    ));
+}
+#[test]
+fn mma_m8n8k4_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109"),
+        Some("v1:i0109")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0109".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_m8n8k4_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k4_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_m8n8k4_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_m8n8k4_f64"),
+        Some("v1:i0109")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0109"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs
new file mode 100644
index 0000000000..e3b00510ee
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs
@@ -0,0 +1,2317 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `scalar_arithmetic` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn add_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446"),
+        Some("v1:i0446")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0446".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rm_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rm_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rm_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rm_f32"),
+        Some("v1:i0446")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0446"
+    ));
+}
+#[test]
+fn add_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436"),
+        Some("v1:i0436")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0436".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rm_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rm_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rm_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rm_f64"),
+        Some("v1:i0436")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0436"
+    ));
+}
+#[test]
+fn add_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447"),
+        Some("v1:i0447")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0447".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rm_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rm_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rm_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rm_ftz_f32"),
+        Some("v1:i0447")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0447"
+    ));
+}
+#[test]
+fn add_rm_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449"),
+        Some("v1:i0449")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0449".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rm_ftz_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rm_ftz_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rm_ftz_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rm_ftz_sat_f32"),
+        Some("v1:i0449")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0449"
+    ));
+}
+#[test]
+fn add_rm_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448"),
+        Some("v1:i0448")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0448".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rm_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rm_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rm_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rm_sat_f32"),
+        Some("v1:i0448")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0448"
+    ));
+}
+#[test]
+fn add_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438"),
+        Some("v1:i0438")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0438".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rn_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rn_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rn_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rn_f32"),
+        Some("v1:i0438")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0438"
+    ));
+}
+#[test]
+fn add_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434"),
+        Some("v1:i0434")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0434".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rn_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rn_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rn_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rn_f64"),
+        Some("v1:i0434")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0434"
+    ));
+}
+#[test]
+fn add_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439"),
+        Some("v1:i0439")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0439".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rn_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rn_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rn_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rn_ftz_f32"),
+        Some("v1:i0439")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0439"
+    ));
+}
+#[test]
+fn add_rn_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441"),
+        Some("v1:i0441")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0441".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rn_ftz_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rn_ftz_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rn_ftz_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rn_ftz_sat_f32"),
+        Some("v1:i0441")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0441"
+    ));
+}
+#[test]
+fn add_rn_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440"),
+        Some("v1:i0440")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0440".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rn_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rn_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rn_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rn_sat_f32"),
+        Some("v1:i0440")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0440"
+    ));
+}
+#[test]
+fn add_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450"),
+        Some("v1:i0450")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0450".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rp_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rp_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rp_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rp_f32"),
+        Some("v1:i0450")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0450"
+    ));
+}
+#[test]
+fn add_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437"),
+        Some("v1:i0437")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0437".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rp_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rp_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rp_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rp_f64"),
+        Some("v1:i0437")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0437"
+    ));
+}
+#[test]
+fn add_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451"),
+        Some("v1:i0451")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0451".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rp_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rp_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rp_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rp_ftz_f32"),
+        Some("v1:i0451")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0451"
+    ));
+}
+#[test]
+fn add_rp_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453"),
+        Some("v1:i0453")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0453".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rp_ftz_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rp_ftz_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rp_ftz_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rp_ftz_sat_f32"),
+        Some("v1:i0453")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0453"
+    ));
+}
+#[test]
+fn add_rp_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452"),
+        Some("v1:i0452")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0452".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rp_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rp_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rp_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rp_sat_f32"),
+        Some("v1:i0452")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0452"
+    ));
+}
+#[test]
+fn add_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442"),
+        Some("v1:i0442")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0442".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rz_f32"),
+        Some("v1:i0442")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0442"
+    ));
+}
+#[test]
+fn add_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435"),
+        Some("v1:i0435")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0435".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rz_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rz_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rz_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rz_f64"),
+        Some("v1:i0435")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0435"
+    ));
+}
+#[test]
+fn add_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443"),
+        Some("v1:i0443")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0443".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rz_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rz_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rz_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rz_ftz_f32"),
+        Some("v1:i0443")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0443"
+    ));
+}
+#[test]
+fn add_rz_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445"),
+        Some("v1:i0445")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0445".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rz_ftz_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rz_ftz_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rz_ftz_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rz_ftz_sat_f32"),
+        Some("v1:i0445")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0445"
+    ));
+}
+#[test]
+fn add_rz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444"),
+        Some("v1:i0444")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0444".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::add_rz_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::add_rz_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::add_rz_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::add_rz_sat_f32"),
+        Some("v1:i0444")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0444"
+    ));
+}
+#[test]
+fn div_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414"),
+        Some("v1:i0414")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0414".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rm_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rm_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rm_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rm_f32"),
+        Some("v1:i0414")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0414"
+    ));
+}
+#[test]
+fn div_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396"),
+        Some("v1:i0396")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0396".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rm_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rm_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rm_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rm_f64"),
+        Some("v1:i0396")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0396"
+    ));
+}
+#[test]
+fn div_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415"),
+        Some("v1:i0415")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0415".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rm_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rm_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rm_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rm_ftz_f32"),
+        Some("v1:i0415")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0415"
+    ));
+}
+#[test]
+fn div_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410"),
+        Some("v1:i0410")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0410".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rn_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rn_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rn_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rn_f32"),
+        Some("v1:i0410")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0410"
+    ));
+}
+#[test]
+fn div_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394"),
+        Some("v1:i0394")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0394".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rn_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rn_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rn_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rn_f64"),
+        Some("v1:i0394")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0394"
+    ));
+}
+#[test]
+fn div_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411"),
+        Some("v1:i0411")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0411".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rn_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rn_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rn_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rn_ftz_f32"),
+        Some("v1:i0411")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0411"
+    ));
+}
+#[test]
+fn div_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416"),
+        Some("v1:i0416")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0416".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rp_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rp_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rp_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rp_f32"),
+        Some("v1:i0416")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0416"
+    ));
+}
+#[test]
+fn div_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397"),
+        Some("v1:i0397")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0397".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rp_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rp_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rp_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rp_f64"),
+        Some("v1:i0397")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0397"
+    ));
+}
+#[test]
+fn div_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417"),
+        Some("v1:i0417")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0417".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rp_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rp_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rp_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rp_ftz_f32"),
+        Some("v1:i0417")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0417"
+    ));
+}
+#[test]
+fn div_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412"),
+        Some("v1:i0412")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0412".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rz_f32"),
+        Some("v1:i0412")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0412"
+    ));
+}
+#[test]
+fn div_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395"),
+        Some("v1:i0395")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0395".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rz_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rz_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rz_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rz_f64"),
+        Some("v1:i0395")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0395"
+    ));
+}
+#[test]
+fn div_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413"),
+        Some("v1:i0413")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0413".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::div_rz_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::div_rz_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::div_rz_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::div_rz_ftz_f32"),
+        Some("v1:i0413")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0413"
+    ));
+}
+#[test]
+fn fma_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426"),
+        Some("v1:i0426")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0426".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rm_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rm_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rm_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rm_f32"),
+        Some("v1:i0426")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0426"
+    ));
+}
+#[test]
+fn fma_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400"),
+        Some("v1:i0400")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0400".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rm_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rm_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rm_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rm_f64"),
+        Some("v1:i0400")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0400"
+    ));
+}
+#[test]
+fn fma_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427"),
+        Some("v1:i0427")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0427".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rm_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rm_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rm_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rm_ftz_f32"),
+        Some("v1:i0427")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0427"
+    ));
+}
+#[test]
+fn fma_rm_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429"),
+        Some("v1:i0429")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0429".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rm_ftz_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rm_ftz_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rm_ftz_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rm_ftz_sat_f32"),
+        Some("v1:i0429")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0429"
+    ));
+}
+#[test]
+fn fma_rm_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428"),
+        Some("v1:i0428")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0428".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rm_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rm_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rm_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rm_sat_f32"),
+        Some("v1:i0428")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0428"
+    ));
+}
+#[test]
+fn fma_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418"),
+        Some("v1:i0418")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0418".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rn_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rn_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rn_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rn_f32"),
+        Some("v1:i0418")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0418"
+    ));
+}
+#[test]
+fn fma_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398"),
+        Some("v1:i0398")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0398".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rn_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rn_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rn_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rn_f64"),
+        Some("v1:i0398")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0398"
+    ));
+}
+#[test]
+fn fma_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419"),
+        Some("v1:i0419")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0419".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rn_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rn_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rn_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rn_ftz_f32"),
+        Some("v1:i0419")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0419"
+    ));
+}
+#[test]
+fn fma_rn_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421"),
+        Some("v1:i0421")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0421".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rn_ftz_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rn_ftz_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rn_ftz_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rn_ftz_sat_f32"),
+        Some("v1:i0421")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0421"
+    ));
+}
+#[test]
+fn fma_rn_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420"),
+        Some("v1:i0420")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0420".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rn_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rn_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rn_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rn_sat_f32"),
+        Some("v1:i0420")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0420"
+    ));
+}
+#[test]
+fn fma_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430"),
+        Some("v1:i0430")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0430".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rp_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rp_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rp_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rp_f32"),
+        Some("v1:i0430")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0430"
+    ));
+}
+#[test]
+fn fma_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401"),
+        Some("v1:i0401")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0401".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rp_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rp_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rp_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rp_f64"),
+        Some("v1:i0401")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0401"
+    ));
+}
+#[test]
+fn fma_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431"),
+        Some("v1:i0431")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0431".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rp_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rp_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rp_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rp_ftz_f32"),
+        Some("v1:i0431")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0431"
+    ));
+}
+#[test]
+fn fma_rp_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433"),
+        Some("v1:i0433")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0433".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rp_ftz_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rp_ftz_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rp_ftz_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rp_ftz_sat_f32"),
+        Some("v1:i0433")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0433"
+    ));
+}
+#[test]
+fn fma_rp_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432"),
+        Some("v1:i0432")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0432".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rp_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rp_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rp_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rp_sat_f32"),
+        Some("v1:i0432")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0432"
+    ));
+}
+#[test]
+fn fma_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422"),
+        Some("v1:i0422")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0422".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rz_f32"),
+        Some("v1:i0422")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0422"
+    ));
+}
+#[test]
+fn fma_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399"),
+        Some("v1:i0399")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0399".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rz_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rz_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rz_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rz_f64"),
+        Some("v1:i0399")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0399"
+    ));
+}
+#[test]
+fn fma_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423"),
+        Some("v1:i0423")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0423".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rz_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rz_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rz_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rz_ftz_f32"),
+        Some("v1:i0423")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0423"
+    ));
+}
+#[test]
+fn fma_rz_ftz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425"),
+        Some("v1:i0425")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0425".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rz_ftz_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rz_ftz_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rz_ftz_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rz_ftz_sat_f32"),
+        Some("v1:i0425")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0425"
+    ));
+}
+#[test]
+fn fma_rz_sat_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424"),
+        Some("v1:i0424")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0424".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::fma_rz_sat_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::fma_rz_sat_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::fma_rz_sat_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::fma_rz_sat_f32"),
+        Some("v1:i0424")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0424"
+    ));
+}
+#[test]
+fn mul_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406"),
+        Some("v1:i0406")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0406".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rm_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rm_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rm_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rm_f32"),
+        Some("v1:i0406")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0406"
+    ));
+}
+#[test]
+fn mul_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392"),
+        Some("v1:i0392")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0392".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rm_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rm_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rm_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rm_f64"),
+        Some("v1:i0392")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0392"
+    ));
+}
+#[test]
+fn mul_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407"),
+        Some("v1:i0407")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0407".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rm_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rm_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rm_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rm_ftz_f32"),
+        Some("v1:i0407")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0407"
+    ));
+}
+#[test]
+fn mul_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402"),
+        Some("v1:i0402")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0402".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rn_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rn_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rn_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rn_f32"),
+        Some("v1:i0402")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0402"
+    ));
+}
+#[test]
+fn mul_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390"),
+        Some("v1:i0390")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0390".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rn_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rn_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rn_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rn_f64"),
+        Some("v1:i0390")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0390"
+    ));
+}
+#[test]
+fn mul_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403"),
+        Some("v1:i0403")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0403".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rn_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rn_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rn_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rn_ftz_f32"),
+        Some("v1:i0403")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0403"
+    ));
+}
+#[test]
+fn mul_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408"),
+        Some("v1:i0408")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0408".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rp_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rp_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rp_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rp_f32"),
+        Some("v1:i0408")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0408"
+    ));
+}
+#[test]
+fn mul_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393"),
+        Some("v1:i0393")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0393".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rp_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rp_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rp_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rp_f64"),
+        Some("v1:i0393")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0393"
+    ));
+}
+#[test]
+fn mul_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409"),
+        Some("v1:i0409")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0409".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rp_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rp_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rp_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rp_ftz_f32"),
+        Some("v1:i0409")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0409"
+    ));
+}
+#[test]
+fn mul_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404"),
+        Some("v1:i0404")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0404".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rz_f32"),
+        Some("v1:i0404")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0404"
+    ));
+}
+#[test]
+fn mul_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391"),
+        Some("v1:i0391")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0391".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rz_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rz_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rz_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rz_f64"),
+        Some("v1:i0391")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0391"
+    ));
+}
+#[test]
+fn mul_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405"),
+        Some("v1:i0405")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0405".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::mul_rz_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::mul_rz_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::mul_rz_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::mul_rz_ftz_f32"),
+        Some("v1:i0405")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0405"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs
new file mode 100644
index 0000000000..e775faade4
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs
@@ -0,0 +1,373 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `scalar_conversion` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn cvt_rn_relu_satfinite_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373"),
+        Some("v1:i0373")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0373".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_relu_satfinite_tf32_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_satfinite_tf32_f32"),
+        Some("v1:i0373")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0373"
+    ));
+}
+#[test]
+fn cvt_rn_relu_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371"),
+        Some("v1:i0371")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0371".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_relu_tf32_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_tf32_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_relu_tf32_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_relu_tf32_f32"),
+        Some("v1:i0371")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0371"
+    ));
+}
+#[test]
+fn cvt_rn_satfinite_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372"),
+        Some("v1:i0372")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0372".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_satfinite_tf32_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_tf32_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_satfinite_tf32_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_satfinite_tf32_f32"),
+        Some("v1:i0372")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0372"
+    ));
+}
+#[test]
+fn cvt_rn_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370"),
+        Some("v1:i0370")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0370".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rn_tf32_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_tf32_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rn_tf32_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rn_tf32_f32"),
+        Some("v1:i0370")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0370"
+    ));
+}
+#[test]
+fn cvt_rna_satfinite_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369"),
+        Some("v1:i0369")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0369".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rna_satfinite_tf32_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rna_satfinite_tf32_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rna_satfinite_tf32_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rna_satfinite_tf32_f32"),
+        Some("v1:i0369")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0369"
+    ));
+}
+#[test]
+fn cvt_rna_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368"),
+        Some("v1:i0368")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0368".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rna_tf32_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rna_tf32_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rna_tf32_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rna_tf32_f32"),
+        Some("v1:i0368")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0368"
+    ));
+}
+#[test]
+fn cvt_rz_relu_satfinite_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377"),
+        Some("v1:i0377")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0377".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rz_relu_satfinite_tf32_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rz_relu_satfinite_tf32_f32"),
+        Some("v1:i0377")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0377"
+    ));
+}
+#[test]
+fn cvt_rz_relu_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375"),
+        Some("v1:i0375")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0375".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rz_relu_tf32_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_relu_tf32_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_relu_tf32_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rz_relu_tf32_f32"),
+        Some("v1:i0375")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0375"
+    ));
+}
+#[test]
+fn cvt_rz_satfinite_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376"),
+        Some("v1:i0376")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0376".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rz_satfinite_tf32_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_satfinite_tf32_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_satfinite_tf32_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rz_satfinite_tf32_f32"),
+        Some("v1:i0376")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0376"
+    ));
+}
+#[test]
+fn cvt_rz_tf32_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374"),
+        Some("v1:i0374")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0374".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::convert::cvt_rz_tf32_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_tf32_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::convert::cvt_rz_tf32_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::convert::cvt_rz_tf32_f32"),
+        Some("v1:i0374")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0374"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs
new file mode 100644
index 0000000000..1db5b57d17
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs
@@ -0,0 +1,1489 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `scalar_math` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn cos_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784"),
+        Some("v1:i0784")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0784".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::cos_approx_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::cos_approx_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::cos_approx_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::cos_approx_f32"),
+        Some("v1:i0784")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0784"
+    ));
+}
+#[test]
+fn cos_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785"),
+        Some("v1:i0785")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0785".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::cos_approx_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::cos_approx_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::cos_approx_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::cos_approx_ftz_f32"),
+        Some("v1:i0785")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0785"
+    ));
+}
+#[test]
+fn ex2_approx_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"),
+        Some("v1:i1016")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::ex2_approx_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::ex2_approx_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::ex2_approx_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::ex2_approx_f16"),
+        Some("v1:i1016")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1016"
+    ));
+}
+#[test]
+fn ex2_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819"),
+        Some("v1:i0819")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0819".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::ex2_approx_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::ex2_approx_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::ex2_approx_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::ex2_approx_f32"),
+        Some("v1:i0819")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0819"
+    ));
+}
+#[test]
+fn ex2_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820"),
+        Some("v1:i0820")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0820".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::ex2_approx_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::ex2_approx_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::ex2_approx_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::ex2_approx_ftz_f32"),
+        Some("v1:i0820")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0820"
+    ));
+}
+#[test]
+fn lg2_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786"),
+        Some("v1:i0786")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0786".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::lg2_approx_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::lg2_approx_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::lg2_approx_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::lg2_approx_f32"),
+        Some("v1:i0786")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0786"
+    ));
+}
+#[test]
+fn lg2_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787"),
+        Some("v1:i0787")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0787".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::lg2_approx_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::lg2_approx_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::lg2_approx_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::lg2_approx_ftz_f32"),
+        Some("v1:i0787")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0787"
+    ));
+}
+#[test]
+fn rcp_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788"),
+        Some("v1:i0788")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0788".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_approx_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_approx_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_approx_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_approx_ftz_f32"),
+        Some("v1:i0788")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0788"
+    ));
+}
+#[test]
+fn rcp_approx_ftz_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797"),
+        Some("v1:i0797")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0797".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_approx_ftz_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_approx_ftz_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_approx_ftz_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_approx_ftz_f64"),
+        Some("v1:i0797")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0797"
+    ));
+}
+#[test]
+fn rcp_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793"),
+        Some("v1:i0793")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0793".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rm_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rm_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rm_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rm_f32"),
+        Some("v1:i0793")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0793"
+    ));
+}
+#[test]
+fn rcp_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800"),
+        Some("v1:i0800")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0800".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rm_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rm_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rm_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rm_f64"),
+        Some("v1:i0800")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0800"
+    ));
+}
+#[test]
+fn rcp_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794"),
+        Some("v1:i0794")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0794".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rm_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rm_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rm_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rm_ftz_f32"),
+        Some("v1:i0794")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0794"
+    ));
+}
+#[test]
+fn rcp_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789"),
+        Some("v1:i0789")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0789".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rn_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rn_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rn_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rn_f32"),
+        Some("v1:i0789")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0789"
+    ));
+}
+#[test]
+fn rcp_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798"),
+        Some("v1:i0798")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0798".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rn_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rn_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rn_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rn_f64"),
+        Some("v1:i0798")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0798"
+    ));
+}
+#[test]
+fn rcp_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790"),
+        Some("v1:i0790")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0790".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rn_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rn_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rn_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rn_ftz_f32"),
+        Some("v1:i0790")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0790"
+    ));
+}
+#[test]
+fn rcp_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795"),
+        Some("v1:i0795")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0795".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rp_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rp_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rp_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rp_f32"),
+        Some("v1:i0795")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0795"
+    ));
+}
+#[test]
+fn rcp_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801"),
+        Some("v1:i0801")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0801".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rp_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rp_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rp_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rp_f64"),
+        Some("v1:i0801")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0801"
+    ));
+}
+#[test]
+fn rcp_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796"),
+        Some("v1:i0796")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0796".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rp_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rp_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rp_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rp_ftz_f32"),
+        Some("v1:i0796")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0796"
+    ));
+}
+#[test]
+fn rcp_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791"),
+        Some("v1:i0791")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0791".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rz_f32"),
+        Some("v1:i0791")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0791"
+    ));
+}
+#[test]
+fn rcp_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799"),
+        Some("v1:i0799")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0799".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rz_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rz_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rz_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rz_f64"),
+        Some("v1:i0799")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0799"
+    ));
+}
+#[test]
+fn rcp_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792"),
+        Some("v1:i0792")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0792".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rcp_rz_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rcp_rz_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rcp_rz_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rcp_rz_ftz_f32"),
+        Some("v1:i0792")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0792"
+    ));
+}
+#[test]
+fn rsqrt_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802"),
+        Some("v1:i0802")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0802".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rsqrt_approx_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rsqrt_approx_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rsqrt_approx_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rsqrt_approx_f32"),
+        Some("v1:i0802")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0802"
+    ));
+}
+#[test]
+fn rsqrt_approx_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804"),
+        Some("v1:i0804")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0804".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rsqrt_approx_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rsqrt_approx_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rsqrt_approx_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rsqrt_approx_f64"),
+        Some("v1:i0804")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0804"
+    ));
+}
+#[test]
+fn rsqrt_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803"),
+        Some("v1:i0803")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0803".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::rsqrt_approx_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::rsqrt_approx_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::rsqrt_approx_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::rsqrt_approx_ftz_f32"),
+        Some("v1:i0803")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0803"
+    ));
+}
+#[test]
+fn sin_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782"),
+        Some("v1:i0782")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0782".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sin_approx_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sin_approx_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sin_approx_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sin_approx_f32"),
+        Some("v1:i0782")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0782"
+    ));
+}
+#[test]
+fn sin_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783"),
+        Some("v1:i0783")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0783".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sin_approx_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sin_approx_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sin_approx_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sin_approx_ftz_f32"),
+        Some("v1:i0783")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0783"
+    ));
+}
+#[test]
+fn sqrt_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805"),
+        Some("v1:i0805")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0805".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_approx_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_approx_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_approx_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_approx_f32"),
+        Some("v1:i0805")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0805"
+    ));
+}
+#[test]
+fn sqrt_approx_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806"),
+        Some("v1:i0806")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0806".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_approx_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_approx_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_approx_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_approx_ftz_f32"),
+        Some("v1:i0806")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0806"
+    ));
+}
+#[test]
+fn sqrt_rm_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811"),
+        Some("v1:i0811")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0811".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rm_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rm_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rm_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rm_f32"),
+        Some("v1:i0811")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0811"
+    ));
+}
+#[test]
+fn sqrt_rm_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817"),
+        Some("v1:i0817")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0817".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rm_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rm_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rm_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rm_f64"),
+        Some("v1:i0817")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0817"
+    ));
+}
+#[test]
+fn sqrt_rm_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812"),
+        Some("v1:i0812")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0812".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rm_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rm_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rm_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rm_ftz_f32"),
+        Some("v1:i0812")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0812"
+    ));
+}
+#[test]
+fn sqrt_rn_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807"),
+        Some("v1:i0807")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0807".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rn_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rn_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rn_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rn_f32"),
+        Some("v1:i0807")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0807"
+    ));
+}
+#[test]
+fn sqrt_rn_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815"),
+        Some("v1:i0815")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0815".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rn_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rn_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rn_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rn_f64"),
+        Some("v1:i0815")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0815"
+    ));
+}
+#[test]
+fn sqrt_rn_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808"),
+        Some("v1:i0808")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0808".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rn_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rn_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rn_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rn_ftz_f32"),
+        Some("v1:i0808")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0808"
+    ));
+}
+#[test]
+fn sqrt_rp_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813"),
+        Some("v1:i0813")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0813".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rp_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rp_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rp_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rp_f32"),
+        Some("v1:i0813")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0813"
+    ));
+}
+#[test]
+fn sqrt_rp_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818"),
+        Some("v1:i0818")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0818".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rp_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rp_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rp_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rp_f64"),
+        Some("v1:i0818")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0818"
+    ));
+}
+#[test]
+fn sqrt_rp_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814"),
+        Some("v1:i0814")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0814".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rp_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rp_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rp_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rp_ftz_f32"),
+        Some("v1:i0814")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0814"
+    ));
+}
+#[test]
+fn sqrt_rz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809"),
+        Some("v1:i0809")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0809".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rz_f32"),
+        Some("v1:i0809")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0809"
+    ));
+}
+#[test]
+fn sqrt_rz_f64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816"),
+        Some("v1:i0816")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0816".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rz_f64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rz_f64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rz_f64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rz_f64"),
+        Some("v1:i0816")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0816"
+    ));
+}
+#[test]
+fn sqrt_rz_ftz_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810"),
+        Some("v1:i0810")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0810".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::sqrt_rz_ftz_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rz_ftz_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::sqrt_rz_ftz_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::sqrt_rz_ftz_f32"),
+        Some("v1:i0810")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0810"
+    ));
+}
+#[test]
+fn tanh_approx_f32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821"),
+        Some("v1:i0821")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0821".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::float::tanh_approx_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::float::tanh_approx_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::float::tanh_approx_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::float::tanh_approx_f32"),
+        Some("v1:i0821")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0821"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs
new file mode 100644
index 0000000000..3b41ef27b1
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs
@@ -0,0 +1,4319 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `sparse_mma` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn mma_sp_m16n8k128_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219"),
+        Some("v1:i0219")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0219".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_s4"),
+        Some("v1:i0219")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0219"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k128_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223"),
+        Some("v1:i0223")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0223".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_s4_satfinite"),
+        Some("v1:i0223")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0223"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k128_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220"),
+        Some("v1:i0220")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0220".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_s4_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4"),
+        Some("v1:i0220")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0220"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k128_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224"),
+        Some("v1:i0224")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0224".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_s4_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_s4_u4_satfinite"),
+        Some("v1:i0224")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0224"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k128_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221"),
+        Some("v1:i0221")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0221".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_u4"),
+        Some("v1:i0221")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0221"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k128_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222"),
+        Some("v1:i0222")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0222".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_u4_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4"),
+        Some("v1:i0222")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0222"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k128_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226"),
+        Some("v1:i0226")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0226".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_u4_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_u4_s4_satfinite"),
+        Some("v1:i0226")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0226"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k128_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225"),
+        Some("v1:i0225")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0225".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k128_s32_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k128_s32_u4_satfinite"),
+        Some("v1:i0225")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0225"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k32_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163"),
+        Some("v1:i0163")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0163".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_s8"),
+        Some("v1:i0163")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0163"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k32_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167"),
+        Some("v1:i0167")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0167".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_s8_satfinite"),
+        Some("v1:i0167")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0167"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k32_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164"),
+        Some("v1:i0164")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0164".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_s8_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8"),
+        Some("v1:i0164")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0164"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k32_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168"),
+        Some("v1:i0168")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0168".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_s8_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_s8_u8_satfinite"),
+        Some("v1:i0168")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0168"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k32_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165"),
+        Some("v1:i0165")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0165".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_u8"),
+        Some("v1:i0165")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0165"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k32_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166"),
+        Some("v1:i0166")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0166".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_u8_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8"),
+        Some("v1:i0166")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0166"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k32_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170"),
+        Some("v1:i0170")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0170".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_u8_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_u8_s8_satfinite"),
+        Some("v1:i0170")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0170"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k32_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169"),
+        Some("v1:i0169")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0169".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k32_s32_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k32_s32_u8_satfinite"),
+        Some("v1:i0169")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0169"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211"),
+        Some("v1:i0211")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0211".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s4"),
+        Some("v1:i0211")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0211"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215"),
+        Some("v1:i0215")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0215".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s4_satfinite"),
+        Some("v1:i0215")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0215"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212"),
+        Some("v1:i0212")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0212".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s4_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4"),
+        Some("v1:i0212")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0212"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216"),
+        Some("v1:i0216")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0216".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s4_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s4_u4_satfinite"),
+        Some("v1:i0216")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0216"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187"),
+        Some("v1:i0187")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0187".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s8"),
+        Some("v1:i0187")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0187"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191"),
+        Some("v1:i0191")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0191".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s8_satfinite"),
+        Some("v1:i0191")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0191"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188"),
+        Some("v1:i0188")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0188".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s8_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8"),
+        Some("v1:i0188")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0188"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192"),
+        Some("v1:i0192")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0192".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_s8_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_s8_u8_satfinite"),
+        Some("v1:i0192")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0192"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213"),
+        Some("v1:i0213")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0213".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u4"),
+        Some("v1:i0213")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0213"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214"),
+        Some("v1:i0214")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0214".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u4_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4"),
+        Some("v1:i0214")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0214"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218"),
+        Some("v1:i0218")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0218".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u4_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u4_s4_satfinite"),
+        Some("v1:i0218")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0218"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217"),
+        Some("v1:i0217")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0217".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u4_satfinite"),
+        Some("v1:i0217")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0217"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189"),
+        Some("v1:i0189")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0189".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u8"),
+        Some("v1:i0189")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0189"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190"),
+        Some("v1:i0190")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0190".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u8_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8"),
+        Some("v1:i0190")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0190"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194"),
+        Some("v1:i0194")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0194".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u8_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u8_s8_satfinite"),
+        Some("v1:i0194")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0194"
+    ));
+}
+#[test]
+fn mma_sp_m16n8k64_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193"),
+        Some("v1:i0193")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0193".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_m16n8k64_s32_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_m16n8k64_s32_u8_satfinite"),
+        Some("v1:i0193")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0193"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203"),
+        Some("v1:i0203")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0203".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4"),
+        Some("v1:i0203")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0203"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207"),
+        Some("v1:i0207")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0207".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite"
+        ),
+        Some("v1:i0207")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0207"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204"),
+        Some("v1:i0204")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0204".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4"
+        ),
+        Some("v1:i0204")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0204"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208"),
+        Some("v1:i0208")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0208".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite"
+        ),
+        Some("v1:i0208")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0208"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205"),
+        Some("v1:i0205")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0205".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4"),
+        Some("v1:i0205")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0205"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206"),
+        Some("v1:i0206")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4"
+        ),
+        Some("v1:i0206")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0206"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210"),
+        Some("v1:i0210")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite"
+        ),
+        Some("v1:i0210")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0210"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209"),
+        Some("v1:i0209")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite"
+        ),
+        Some("v1:i0209")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0209"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171"),
+        Some("v1:i0171")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8"),
+        Some("v1:i0171")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0171"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths()
+{
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175"),
+        Some("v1:i0175")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite"
+        ),
+        Some("v1:i0175")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0175"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172"),
+        Some("v1:i0172")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8"),
+        Some("v1:i0172")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0172"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176"),
+        Some("v1:i0176")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite"
+        ),
+        Some("v1:i0176")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0176"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173"),
+        Some("v1:i0173")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8"),
+        Some("v1:i0173")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0173"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174"),
+        Some("v1:i0174")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8"),
+        Some("v1:i0174")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0174"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178"),
+        Some("v1:i0178")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite"
+        ),
+        Some("v1:i0178")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0178"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths()
+{
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177"),
+        Some("v1:i0177")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite"
+        ),
+        Some("v1:i0177")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0177"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525"),
+        Some("v1:i0525")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16"
+        ),
+        Some("v1:i0525")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0525"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526"),
+        Some("v1:i0526")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16"
+        ),
+        Some("v1:i0526")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0526"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527"),
+        Some("v1:i0527")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16"
+        ),
+        Some("v1:i0527")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0527"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528"),
+        Some("v1:i0528")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16"
+        ),
+        Some("v1:i0528")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0528"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529"),
+        Some("v1:i0529")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16"
+        ),
+        Some("v1:i0529")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0529"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530"),
+        Some("v1:i0530")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16"
+        ),
+        Some("v1:i0530")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0530"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531"),
+        Some("v1:i0531")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16"
+        ),
+        Some("v1:i0531")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0531"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532"),
+        Some("v1:i0532")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16"
+        ),
+        Some("v1:i0532")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0532"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533"),
+        Some("v1:i0533")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16"
+        ),
+        Some("v1:i0533")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0533"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534"),
+        Some("v1:i0534")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16"
+        ),
+        Some("v1:i0534")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0534"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535"),
+        Some("v1:i0535")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16"
+        ),
+        Some("v1:i0535")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0535"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536"),
+        Some("v1:i0536")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16"
+        ),
+        Some("v1:i0536")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0536"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537"),
+        Some("v1:i0537")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16"
+        ),
+        Some("v1:i0537")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0537"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538"),
+        Some("v1:i0538")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16"
+        ),
+        Some("v1:i0538")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0538"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539"),
+        Some("v1:i0539")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16"
+        ),
+        Some("v1:i0539")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0539"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540"),
+        Some("v1:i0540")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16"
+        ),
+        Some("v1:i0540")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0540"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541"),
+        Some("v1:i0541")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16"
+        ),
+        Some("v1:i0541")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0541"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542"),
+        Some("v1:i0542")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16"
+        ),
+        Some("v1:i0542")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0542"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543"),
+        Some("v1:i0543")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16"
+        ),
+        Some("v1:i0543")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0543"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544"),
+        Some("v1:i0544")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16"
+        ),
+        Some("v1:i0544")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0544"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545"),
+        Some("v1:i0545")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16"
+        ),
+        Some("v1:i0545")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0545"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546"),
+        Some("v1:i0546")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16"
+        ),
+        Some("v1:i0546")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0546"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547"),
+        Some("v1:i0547")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16"
+        ),
+        Some("v1:i0547")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0547"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548"),
+        Some("v1:i0548")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16"
+        ),
+        Some("v1:i0548")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0548"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549"),
+        Some("v1:i0549")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16"
+        ),
+        Some("v1:i0549")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0549"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227"),
+        Some("v1:i0227")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32"
+        ),
+        Some("v1:i0227")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0227"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228"),
+        Some("v1:i0228")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32"
+        ),
+        Some("v1:i0228")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0228"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229"),
+        Some("v1:i0229")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32"
+        ),
+        Some("v1:i0229")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0229"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230"),
+        Some("v1:i0230")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32"
+        ),
+        Some("v1:i0230")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0230"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231"),
+        Some("v1:i0231")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32"
+        ),
+        Some("v1:i0231")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0231"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232"),
+        Some("v1:i0232")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32"
+        ),
+        Some("v1:i0232")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0232"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233"),
+        Some("v1:i0233")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32"
+        ),
+        Some("v1:i0233")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0233"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234"),
+        Some("v1:i0234")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32"
+        ),
+        Some("v1:i0234")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0234"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235"),
+        Some("v1:i0235")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32"
+        ),
+        Some("v1:i0235")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0235"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236"),
+        Some("v1:i0236")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32"
+        ),
+        Some("v1:i0236")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0236"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237"),
+        Some("v1:i0237")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32"
+        ),
+        Some("v1:i0237")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0237"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238"),
+        Some("v1:i0238")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32"
+        ),
+        Some("v1:i0238")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0238"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239"),
+        Some("v1:i0239")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32"
+        ),
+        Some("v1:i0239")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0239"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240"),
+        Some("v1:i0240")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32"
+        ),
+        Some("v1:i0240")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0240"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241"),
+        Some("v1:i0241")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32"
+        ),
+        Some("v1:i0241")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0241"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242"),
+        Some("v1:i0242")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32"
+        ),
+        Some("v1:i0242")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0242"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243"),
+        Some("v1:i0243")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32"
+        ),
+        Some("v1:i0243")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0243"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244"),
+        Some("v1:i0244")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32"
+        ),
+        Some("v1:i0244")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0244"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245"),
+        Some("v1:i0245")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32"
+        ),
+        Some("v1:i0245")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0245"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246"),
+        Some("v1:i0246")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32"
+        ),
+        Some("v1:i0246")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0246"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247"),
+        Some("v1:i0247")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32"
+        ),
+        Some("v1:i0247")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0247"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248"),
+        Some("v1:i0248")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32"
+        ),
+        Some("v1:i0248")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0248"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249"),
+        Some("v1:i0249")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32"
+        ),
+        Some("v1:i0249")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0249"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250"),
+        Some("v1:i0250")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32"
+        ),
+        Some("v1:i0250")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0250"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251"),
+        Some("v1:i0251")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32"
+        ),
+        Some("v1:i0251")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0251"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195"),
+        Some("v1:i0195")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4"),
+        Some("v1:i0195")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0195"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite_uses_only_canonical_or_compatibility_defpaths()
+{
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199"),
+        Some("v1:i0199")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite"
+        ),
+        Some("v1:i0199")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0199"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196"),
+        Some("v1:i0196")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4"),
+        Some("v1:i0196")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0196"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200"),
+        Some("v1:i0200")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite"
+        ),
+        Some("v1:i0200")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0200"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179"),
+        Some("v1:i0179")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8"),
+        Some("v1:i0179")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0179"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite_uses_only_canonical_or_compatibility_defpaths()
+{
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183"),
+        Some("v1:i0183")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite"
+        ),
+        Some("v1:i0183")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0183"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180"),
+        Some("v1:i0180")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8"),
+        Some("v1:i0180")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0180"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184"),
+        Some("v1:i0184")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite"
+        ),
+        Some("v1:i0184")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0184"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197"),
+        Some("v1:i0197")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4"),
+        Some("v1:i0197")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0197"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198"),
+        Some("v1:i0198")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4"),
+        Some("v1:i0198")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0198"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202"),
+        Some("v1:i0202")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite"
+        ),
+        Some("v1:i0202")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0202"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite_uses_only_canonical_or_compatibility_defpaths()
+{
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201"),
+        Some("v1:i0201")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite"
+        ),
+        Some("v1:i0201")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0201"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181"),
+        Some("v1:i0181")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8"),
+        Some("v1:i0181")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0181"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182"),
+        Some("v1:i0182")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8"),
+        Some("v1:i0182")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0182"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186"),
+        Some("v1:i0186")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite"
+        ),
+        Some("v1:i0186")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0186"
+    ));
+}
+#[test]
+fn mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite_uses_only_canonical_or_compatibility_defpaths()
+{
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185"),
+        Some("v1:i0185")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite"
+        ),
+        Some("v1:i0185")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0185"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs
new file mode 100644
index 0000000000..28550e420d
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs
@@ -0,0 +1,1647 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `sreg` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn block_dim_x_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003"),
+        Some("v1:i0003")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::block_dim_x"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::blockDim_x"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::blockDim_x"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::blockDim_x"),
+        Some("v1:i0003")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::blockDim_x"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::blockDim_x"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::blockDim_x"),
+        Some("v1:i0003")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0003"
+    ));
+}
+#[test]
+fn block_dim_y_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007"),
+        Some("v1:i0007")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::block_dim_y"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::blockDim_y"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::blockDim_y"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::blockDim_y"),
+        Some("v1:i0007")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::blockDim_y"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::blockDim_y"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::blockDim_y"),
+        Some("v1:i0007")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0007"
+    ));
+}
+#[test]
+fn block_dim_z_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011"),
+        Some("v1:i0011")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::block_dim_z"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::blockDim_z"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::blockDim_z"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::blockDim_z"),
+        Some("v1:i0011")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::blockDim_z"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::blockDim_z"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::blockDim_z"),
+        Some("v1:i0011")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0011"
+    ));
+}
+#[test]
+fn block_idx_x_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002"),
+        Some("v1:i0002")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0002".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::block_idx_x"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::blockIdx_x"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::blockIdx_x"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::blockIdx_x"),
+        Some("v1:i0002")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::blockIdx_x"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::blockIdx_x"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::blockIdx_x"),
+        Some("v1:i0002")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0002"
+    ));
+}
+#[test]
+fn block_idx_y_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006"),
+        Some("v1:i0006")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0006".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::block_idx_y"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::blockIdx_y"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::blockIdx_y"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::blockIdx_y"),
+        Some("v1:i0006")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::blockIdx_y"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::blockIdx_y"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::blockIdx_y"),
+        Some("v1:i0006")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0006"
+    ));
+}
+#[test]
+fn block_idx_z_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010"),
+        Some("v1:i0010")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0010".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::block_idx_z"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::blockIdx_z"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::blockIdx_z"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::blockIdx_z"),
+        Some("v1:i0010")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::blockIdx_z"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::blockIdx_z"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::blockIdx_z"),
+        Some("v1:i0010")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0010"
+    ));
+}
+#[test]
+fn clock_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283"),
+        Some("v1:i0283")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0283".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::debug::clock"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::debug::clock"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::debug::clock"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::debug::clock"),
+        Some("v1:i0283")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0283"
+    ));
+}
+#[test]
+fn clock64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284"),
+        Some("v1:i0284")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0284".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::debug::clock64"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::debug::clock64"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::debug::clock64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::debug::clock64"),
+        Some("v1:i0284")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0284"
+    ));
+}
+#[test]
+fn cluster_block_count_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276"),
+        Some("v1:i0276")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0276".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_block_count"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0276"
+    ));
+}
+#[test]
+fn cluster_block_idx_x_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263"),
+        Some("v1:i0263")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0263".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_block_idx_x"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_ctaidX"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_ctaidX"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::cluster_ctaidX"),
+        Some("v1:i0263")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0263"
+    ));
+}
+#[test]
+fn cluster_block_idx_y_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264"),
+        Some("v1:i0264")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0264".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_block_idx_y"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_ctaidY"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_ctaidY"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::cluster_ctaidY"),
+        Some("v1:i0264")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0264"
+    ));
+}
+#[test]
+fn cluster_block_idx_z_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265"),
+        Some("v1:i0265")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0265".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_block_idx_z"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_ctaidZ"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_ctaidZ"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::cluster_ctaidZ"),
+        Some("v1:i0265")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0265"
+    ));
+}
+#[test]
+fn cluster_block_rank_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275"),
+        Some("v1:i0275")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0275".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_block_rank"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0275"
+    ));
+}
+#[test]
+fn cluster_dim_x_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266"),
+        Some("v1:i0266")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0266".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_dim_x"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_nctaidX"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_nctaidX"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::cluster_nctaidX"),
+        Some("v1:i0266")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0266"
+    ));
+}
+#[test]
+fn cluster_dim_y_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267"),
+        Some("v1:i0267")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0267".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_dim_y"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_nctaidY"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_nctaidY"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::cluster_nctaidY"),
+        Some("v1:i0267")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0267"
+    ));
+}
+#[test]
+fn cluster_dim_z_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268"),
+        Some("v1:i0268")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0268".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_dim_z"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_nctaidZ"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::cluster_nctaidZ"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::cluster_nctaidZ"),
+        Some("v1:i0268")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0268"
+    ));
+}
+#[test]
+fn cluster_grid_dim_x_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272"),
+        Some("v1:i0272")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0272".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_grid_dim_x"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_grid_dimX"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_grid_dimX"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::__cluster_grid_dimX"),
+        Some("v1:i0272")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0272"
+    ));
+}
+#[test]
+fn cluster_grid_dim_y_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273"),
+        Some("v1:i0273")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0273".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_grid_dim_y"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_grid_dimY"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_grid_dimY"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::__cluster_grid_dimY"),
+        Some("v1:i0273")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0273"
+    ));
+}
+#[test]
+fn cluster_grid_dim_z_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274"),
+        Some("v1:i0274")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0274".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_grid_dim_z"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_grid_dimZ"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_grid_dimZ"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::__cluster_grid_dimZ"),
+        Some("v1:i0274")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0274"
+    ));
+}
+#[test]
+fn cluster_idx_x_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269"),
+        Some("v1:i0269")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0269".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_idx_x"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_idxX"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_idxX"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::__cluster_idxX"),
+        Some("v1:i0269")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0269"
+    ));
+}
+#[test]
+fn cluster_idx_y_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270"),
+        Some("v1:i0270")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0270".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_idx_y"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_idxY"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_idxY"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::__cluster_idxY"),
+        Some("v1:i0270")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0270"
+    ));
+}
+#[test]
+fn cluster_idx_z_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271"),
+        Some("v1:i0271")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0271".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::cluster_idx_z"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_idxZ"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::cluster::__cluster_idxZ"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::cluster::__cluster_idxZ"),
+        Some("v1:i0271")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0271"
+    ));
+}
+#[test]
+fn dynamic_smem_size_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293"),
+        Some("v1:i0293")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0293".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::shared::dynamic_smem_size"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::shared::dynamic_smem_size"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::shared::dynamic_smem_size"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::shared::dynamic_smem_size"),
+        Some("v1:i0293")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0293"
+    ));
+}
+#[test]
+fn envreg1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286"),
+        Some("v1:i0286")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0286".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::grid::envreg1"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::grid::envreg1"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::grid::envreg1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::grid::envreg1"),
+        Some("v1:i0286")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0286"
+    ));
+}
+#[test]
+fn envreg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287"),
+        Some("v1:i0287")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0287".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::grid::envreg2"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::grid::envreg2"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::grid::envreg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::grid::envreg2"),
+        Some("v1:i0287")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0287"
+    ));
+}
+#[test]
+fn globaltimer_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285"),
+        Some("v1:i0285")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0285".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::debug::globaltimer"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::debug::globaltimer"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::debug::globaltimer"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::debug::globaltimer"),
+        Some("v1:i0285")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0285"
+    ));
+}
+#[test]
+fn grid_dim_x_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004"),
+        Some("v1:i0004")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0004".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::grid_dim_x"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::gridDim_x"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::gridDim_x"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::gridDim_x"),
+        Some("v1:i0004")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::gridDim_x"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::gridDim_x"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::gridDim_x"),
+        Some("v1:i0004")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0004"
+    ));
+}
+#[test]
+fn grid_dim_y_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008"),
+        Some("v1:i0008")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0008".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::grid_dim_y"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::gridDim_y"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::gridDim_y"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::gridDim_y"),
+        Some("v1:i0008")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::gridDim_y"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::gridDim_y"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::gridDim_y"),
+        Some("v1:i0008")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0008"
+    ));
+}
+#[test]
+fn grid_dim_z_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012"),
+        Some("v1:i0012")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0012".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::grid_dim_z"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::gridDim_z"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::gridDim_z"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::gridDim_z"),
+        Some("v1:i0012")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::gridDim_z"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::gridDim_z"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::gridDim_z"),
+        Some("v1:i0012")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0012"
+    ));
+}
+#[test]
+fn gridid_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290"),
+        Some("v1:i0290")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0290".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::thread::gridid"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::thread::gridid"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::gridid"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::gridid"),
+        Some("v1:i0290")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::gridid"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::gridid"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::gridid"),
+        Some("v1:i0290")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0290"
+    ));
+}
+#[test]
+fn lane_id_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016"),
+        Some("v1:i0016")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0016".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::lane_id"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::warp::lane_id"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::lane_id"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::lane_id"),
+        Some("v1:i0016")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0016"
+    ));
+}
+#[test]
+fn lanemask_eq_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037"),
+        Some("v1:i0037")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0037".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::lanemask_eq"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::lanemask_eq"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::lanemask_eq"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::lanemask_eq"),
+        Some("v1:i0037")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0037"
+    ));
+}
+#[test]
+fn lanemask_ge_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038"),
+        Some("v1:i0038")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0038".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::lanemask_ge"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::lanemask_ge"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::lanemask_ge"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::lanemask_ge"),
+        Some("v1:i0038")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0038"
+    ));
+}
+#[test]
+fn lanemask_gt_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039"),
+        Some("v1:i0039")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0039".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::lanemask_gt"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::lanemask_gt"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::lanemask_gt"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::lanemask_gt"),
+        Some("v1:i0039")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0039"
+    ));
+}
+#[test]
+fn lanemask_le_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036"),
+        Some("v1:i0036")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0036".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::lanemask_le"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::lanemask_le"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::lanemask_le"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::lanemask_le"),
+        Some("v1:i0036")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0036"
+    ));
+}
+#[test]
+fn lanemask_lt_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035"),
+        Some("v1:i0035")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0035".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::lanemask_lt"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::lanemask_lt"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::lanemask_lt"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::lanemask_lt"),
+        Some("v1:i0035")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0035"
+    ));
+}
+#[test]
+fn nsmid_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289"),
+        Some("v1:i0289")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0289".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::thread::nsmid"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::thread::nsmid"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::nsmid"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::nsmid"),
+        Some("v1:i0289")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::nsmid"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::nsmid"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::nsmid"),
+        Some("v1:i0289")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0289"
+    ));
+}
+#[test]
+fn nwarpid_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292"),
+        Some("v1:i0292")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0292".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::nwarpid"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::warp::nwarpid"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::nwarpid"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::nwarpid"),
+        Some("v1:i0292")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0292"
+    ));
+}
+#[test]
+fn smid_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288"),
+        Some("v1:i0288")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0288".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::thread::smid"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::thread::smid"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::smid"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::smid"),
+        Some("v1:i0288")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::smid"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::smid"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::smid"),
+        Some("v1:i0288")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0288"
+    ));
+}
+#[test]
+fn thread_idx_x_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001"),
+        Some("v1:i0001")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0001".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::thread_idx_x"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::threadIdx_x"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::threadIdx_x"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::threadIdx_x"),
+        Some("v1:i0001")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::threadIdx_x"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::threadIdx_x"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::threadIdx_x"),
+        Some("v1:i0001")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0001"
+    ));
+}
+#[test]
+fn thread_idx_y_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005"),
+        Some("v1:i0005")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0005".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::thread_idx_y"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::threadIdx_y"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::threadIdx_y"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::threadIdx_y"),
+        Some("v1:i0005")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::threadIdx_y"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::threadIdx_y"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::threadIdx_y"),
+        Some("v1:i0005")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0005"
+    ));
+}
+#[test]
+fn thread_idx_z_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009"),
+        Some("v1:i0009")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0009".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::sreg::thread_idx_z"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::threadIdx_z"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::threadIdx_z"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::threadIdx_z"),
+        Some("v1:i0009")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::threadIdx_z"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::threadIdx_z"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::threadIdx_z"),
+        Some("v1:i0009")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0009"
+    ));
+}
+#[test]
+fn total_smem_size_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294"),
+        Some("v1:i0294")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0294".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::shared::total_smem_size"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::shared::total_smem_size"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::shared::total_smem_size"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::shared::total_smem_size"),
+        Some("v1:i0294")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0294"
+    ));
+}
+#[test]
+fn warpid_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291"),
+        Some("v1:i0291")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0291".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::warpid"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::warp::warpid"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::warpid"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::warpid"),
+        Some("v1:i0291")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0291"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs
new file mode 100644
index 0000000000..864dae0c04
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs
@@ -0,0 +1,157 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `stmatrix` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn stmatrix_m8n8_x2_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301"),
+        Some("v1:i0301")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0301".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::stmatrix_m8n8_x2_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::stmatrix_m8n8_x2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::stmatrix_m8n8_x2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::stmatrix_m8n8_x2"),
+        Some("v1:i0301")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0301"
+    ));
+}
+#[test]
+fn stmatrix_m8n8_x2_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302"),
+        Some("v1:i0302")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0302".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::stmatrix_m8n8_x2_trans_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::stmatrix_m8n8_x2_trans"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::stmatrix_m8n8_x2_trans"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::stmatrix_m8n8_x2_trans"),
+        Some("v1:i0302")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0302"
+    ));
+}
+#[test]
+fn stmatrix_m8n8_x4_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303"),
+        Some("v1:i0303")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0303".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::stmatrix_m8n8_x4_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::stmatrix_m8n8_x4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::stmatrix_m8n8_x4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::stmatrix_m8n8_x4"),
+        Some("v1:i0303")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0303"
+    ));
+}
+#[test]
+fn stmatrix_m8n8_x4_trans_b16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304"),
+        Some("v1:i0304")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0304".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::matrix::stmatrix_m8n8_x4_trans_b16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::stmatrix_m8n8_x4_trans"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::stmatrix_m8n8_x4_trans"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::stmatrix_m8n8_x4_trans"),
+        Some("v1:i0304")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0304"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs
new file mode 100644
index 0000000000..5c53164e3e
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs
@@ -0,0 +1,191 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `sync` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn sync_threads_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034"),
+        Some("v1:i0034")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0034".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::thread::sync_threads"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::thread::sync_threads"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::thread::sync_threads"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::thread::sync_threads"),
+        Some("v1:i0034")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::sync_threads"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::sync_threads"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::sync_threads"),
+        Some("v1:i0034")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0034"
+    ));
+}
+#[test]
+fn threadfence_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299"),
+        Some("v1:i0299")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0299".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::fence::threadfence"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::fence::threadfence"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::fence::threadfence"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::fence::threadfence"),
+        Some("v1:i0299")
+    );
+    assert!(is_generated_intrinsic_path("cuda_device::threadfence"));
+    assert!(!is_raw_generated_intrinsic_path("cuda_device::threadfence"));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::threadfence"),
+        Some("v1:i0299")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0299"
+    ));
+}
+#[test]
+fn threadfence_block_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298"),
+        Some("v1:i0298")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0298".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::fence::threadfence_block"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::fence::threadfence_block"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::fence::threadfence_block"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::fence::threadfence_block"),
+        Some("v1:i0298")
+    );
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::threadfence_block"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::threadfence_block"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::threadfence_block"),
+        Some("v1:i0298")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0298"
+    ));
+}
+#[test]
+fn threadfence_system_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300"),
+        Some("v1:i0300")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0300".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::fence::threadfence_system"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::fence::threadfence_system"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::fence::threadfence_system"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::fence::threadfence_system"),
+        Some("v1:i0300")
+    );
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::threadfence_system"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::threadfence_system"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::threadfence_system"),
+        Some("v1:i0300")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0300"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs
new file mode 100644
index 0000000000..f642b119f9
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs
@@ -0,0 +1,8421 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `tcgen05` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn tcgen05_alloc_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343"),
+        Some("v1:i0343")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0343".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_alloc"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_alloc"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_alloc"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_alloc"),
+        Some("v1:i0343")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0343"
+    ));
+}
+#[test]
+fn tcgen05_alloc_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359"),
+        Some("v1:i0359")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0359".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_alloc_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_alloc_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_alloc_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_alloc_cg2"),
+        Some("v1:i0359")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0359"
+    ));
+}
+#[test]
+fn tcgen05_commit_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348"),
+        Some("v1:i0348")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0348".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_commit"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit"),
+        Some("v1:i0348")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0348"
+    ));
+}
+#[test]
+fn tcgen05_commit_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363"),
+        Some("v1:i0363")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0363".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_commit_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit_cg2"),
+        Some("v1:i0363")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0363"
+    ));
+}
+#[test]
+fn tcgen05_commit_multicast_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760"),
+        Some("v1:i0760")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0760".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_commit_multicast"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit_multicast"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit_multicast"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit_multicast"),
+        Some("v1:i0760")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0760"
+    ));
+}
+#[test]
+fn tcgen05_commit_multicast_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365"),
+        Some("v1:i0365")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0365".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_commit_multicast_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit_multicast_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit_multicast_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit_multicast_cg2"),
+        Some("v1:i0365")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0365"
+    ));
+}
+#[test]
+fn tcgen05_commit_shared_cluster_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349"),
+        Some("v1:i0349")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0349".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_commit_shared_cluster"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit_shared_cluster"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit_shared_cluster"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit_shared_cluster"),
+        Some("v1:i0349")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0349"
+    ));
+}
+#[test]
+fn tcgen05_commit_shared_cluster_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364"),
+        Some("v1:i0364")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0364".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_commit_shared_cluster_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_commit_shared_cluster_cg2"),
+        Some("v1:i0364")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0364"
+    ));
+}
+#[test]
+fn tcgen05_cp_128x128b_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582"),
+        Some("v1:i0582")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0582".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b"),
+        Some("v1:i0582")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0582"
+    ));
+}
+#[test]
+fn tcgen05_cp_128x128b_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578"),
+        Some("v1:i0578")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0578".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b_b4x16_p64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64"),
+        Some("v1:i0578")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0578"
+    ));
+}
+#[test]
+fn tcgen05_cp_128x128b_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579"),
+        Some("v1:i0579")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0579".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b_b4x16_p64_cg2"),
+        Some("v1:i0579")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0579"
+    ));
+}
+#[test]
+fn tcgen05_cp_128x128b_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580"),
+        Some("v1:i0580")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0580".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b_b6x16_p32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32"),
+        Some("v1:i0580")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0580"
+    ));
+}
+#[test]
+fn tcgen05_cp_128x128b_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581"),
+        Some("v1:i0581")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0581".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b_b6x16_p32_cg2"),
+        Some("v1:i0581")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0581"
+    ));
+}
+#[test]
+fn tcgen05_cp_128x128b_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583"),
+        Some("v1:i0583")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0583".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_128x128b_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x128b_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x128b_cg2"),
+        Some("v1:i0583")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0583"
+    ));
+}
+#[test]
+fn tcgen05_cp_128x256b_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584"),
+        Some("v1:i0584")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0584".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_128x256b_b4x16_p64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64"),
+        Some("v1:i0584")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0584"
+    ));
+}
+#[test]
+fn tcgen05_cp_128x256b_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585"),
+        Some("v1:i0585")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0585".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x256b_b4x16_p64_cg2"),
+        Some("v1:i0585")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0585"
+    ));
+}
+#[test]
+fn tcgen05_cp_128x256b_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586"),
+        Some("v1:i0586")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0586".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_128x256b_b6x16_p32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32"),
+        Some("v1:i0586")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0586"
+    ));
+}
+#[test]
+fn tcgen05_cp_128x256b_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587"),
+        Some("v1:i0587")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0587".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_128x256b_b6x16_p32_cg2"),
+        Some("v1:i0587")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0587"
+    ));
+}
+#[test]
+fn tcgen05_cp_32x128b_warpx4_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592"),
+        Some("v1:i0592")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0592".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4"),
+        Some("v1:i0592")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0592"
+    ));
+}
+#[test]
+fn tcgen05_cp_32x128b_warpx4_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588"),
+        Some("v1:i0588")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0588".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64"),
+        Some("v1:i0588")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0588"
+    ));
+}
+#[test]
+fn tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589"),
+        Some("v1:i0589")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0589".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2"),
+        Some("v1:i0589")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0589"
+    ));
+}
+#[test]
+fn tcgen05_cp_32x128b_warpx4_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590"),
+        Some("v1:i0590")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0590".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32"),
+        Some("v1:i0590")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0590"
+    ));
+}
+#[test]
+fn tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591"),
+        Some("v1:i0591")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0591".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2"),
+        Some("v1:i0591")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0591"
+    ));
+}
+#[test]
+fn tcgen05_cp_32x128b_warpx4_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593"),
+        Some("v1:i0593")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0593".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_32x128b_warpx4_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_32x128b_warpx4_cg2"),
+        Some("v1:i0593")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0593"
+    ));
+}
+#[test]
+fn tcgen05_cp_4x256b_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598"),
+        Some("v1:i0598")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0598".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b"),
+        Some("v1:i0598")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0598"
+    ));
+}
+#[test]
+fn tcgen05_cp_4x256b_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594"),
+        Some("v1:i0594")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0594".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b_b4x16_p64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64"),
+        Some("v1:i0594")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0594"
+    ));
+}
+#[test]
+fn tcgen05_cp_4x256b_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595"),
+        Some("v1:i0595")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0595".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b_b4x16_p64_cg2"),
+        Some("v1:i0595")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0595"
+    ));
+}
+#[test]
+fn tcgen05_cp_4x256b_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596"),
+        Some("v1:i0596")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0596".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b_b6x16_p32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32"),
+        Some("v1:i0596")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0596"
+    ));
+}
+#[test]
+fn tcgen05_cp_4x256b_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597"),
+        Some("v1:i0597")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0597".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b_b6x16_p32_cg2"),
+        Some("v1:i0597")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0597"
+    ));
+}
+#[test]
+fn tcgen05_cp_4x256b_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599"),
+        Some("v1:i0599")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0599".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_4x256b_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_4x256b_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_4x256b_cg2"),
+        Some("v1:i0599")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0599"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604"),
+        Some("v1:i0604")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0604".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23"),
+        Some("v1:i0604")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0604"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600"),
+        Some("v1:i0600")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0600".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64"
+        ),
+        Some("v1:i0600")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0600"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601"),
+        Some("v1:i0601")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0601".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2"
+        ),
+        Some("v1:i0601")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0601"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602"),
+        Some("v1:i0602")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0602".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32"
+        ),
+        Some("v1:i0602")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0602"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603"),
+        Some("v1:i0603")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0603".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2"
+        ),
+        Some("v1:i0603")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0603"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_01_23_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605"),
+        Some("v1:i0605")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0605".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_01_23_cg2"),
+        Some("v1:i0605")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0605"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610"),
+        Some("v1:i0610")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0610".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13"),
+        Some("v1:i0610")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0610"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606"),
+        Some("v1:i0606")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0606".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64"
+        ),
+        Some("v1:i0606")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0606"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607"),
+        Some("v1:i0607")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0607".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2"
+        ),
+        Some("v1:i0607")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0607"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608"),
+        Some("v1:i0608")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0608".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32"
+        ),
+        Some("v1:i0608")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0608"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609"),
+        Some("v1:i0609")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0609".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2"
+        ),
+        Some("v1:i0609")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0609"
+    ));
+}
+#[test]
+fn tcgen05_cp_64x128b_warpx2_02_13_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611"),
+        Some("v1:i0611")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0611".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_64x128b_warpx2_02_13_cg2"),
+        Some("v1:i0611")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0611"
+    ));
+}
+#[test]
+fn tcgen05_cp_smem_to_tmem_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354"),
+        Some("v1:i0354")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0354".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_smem_to_tmem"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_smem_to_tmem"),
+        Some("v1:i0354")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0354"
+    ));
+}
+#[test]
+fn tcgen05_cp_smem_to_tmem_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366"),
+        Some("v1:i0366")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0366".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_cp_smem_to_tmem_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_cp_smem_to_tmem_cg2"),
+        Some("v1:i0366")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0366"
+    ));
+}
+#[test]
+fn tcgen05_dealloc_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344"),
+        Some("v1:i0344")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0344".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_dealloc"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_dealloc"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_dealloc"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_dealloc"),
+        Some("v1:i0344")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0344"
+    ));
+}
+#[test]
+fn tcgen05_dealloc_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360"),
+        Some("v1:i0360")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0360".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_dealloc_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_dealloc_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_dealloc_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_dealloc_cg2"),
+        Some("v1:i0360")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0360"
+    ));
+}
+#[test]
+fn tcgen05_fence_after_thread_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347"),
+        Some("v1:i0347")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0347".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_fence_after_thread_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_fence_after_thread_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_fence_after_thread_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_fence_after_thread_sync"),
+        Some("v1:i0347")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0347"
+    ));
+}
+#[test]
+fn tcgen05_fence_before_thread_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346"),
+        Some("v1:i0346")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0346".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_fence_before_thread_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_fence_before_thread_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_fence_before_thread_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_fence_before_thread_sync"),
+        Some("v1:i0346")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0346"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x16_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637"),
+        Some("v1:i0637")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0637".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x16_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x16_pack16"),
+        Some("v1:i0637")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0637"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636"),
+        Some("v1:i0636")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0636".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x16_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x16_raw"),
+        Some("v1:i0636")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0636"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x1_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629"),
+        Some("v1:i0629")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0629".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x1_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x1_pack16"),
+        Some("v1:i0629")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0629"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628"),
+        Some("v1:i0628")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0628".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x1_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x1_raw"),
+        Some("v1:i0628")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0628"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x2_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631"),
+        Some("v1:i0631")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0631".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x2_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x2_pack16"),
+        Some("v1:i0631")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0631"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630"),
+        Some("v1:i0630")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0630".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x2_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x2_raw"),
+        Some("v1:i0630")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0630"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x32_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639"),
+        Some("v1:i0639")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0639".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x32_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x32_pack16"),
+        Some("v1:i0639")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0639"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638"),
+        Some("v1:i0638")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0638".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x32_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x32_raw"),
+        Some("v1:i0638")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0638"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x4_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633"),
+        Some("v1:i0633")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0633".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x4_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x4_pack16"),
+        Some("v1:i0633")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0633"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632"),
+        Some("v1:i0632")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0632".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x4_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x4_raw"),
+        Some("v1:i0632")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0632"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x64_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641"),
+        Some("v1:i0641")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0641".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x64_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x64_pack16"),
+        Some("v1:i0641")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0641"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640"),
+        Some("v1:i0640")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0640".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x64_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x64_raw"),
+        Some("v1:i0640")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0640"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x8_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635"),
+        Some("v1:i0635")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0635".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x8_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x8_pack16"),
+        Some("v1:i0635")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0635"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x128b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634"),
+        Some("v1:i0634")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0634".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x128b_x8_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x128b_x8_raw"),
+        Some("v1:i0634")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0634"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_pure_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356"),
+        Some("v1:i0356")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0356".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_pure"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_pure"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_pure"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_pure"),
+        Some("v1:i0356")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0356"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x16_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651"),
+        Some("v1:i0651")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0651".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x16_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x16_pack16"),
+        Some("v1:i0651")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0651"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650"),
+        Some("v1:i0650")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0650".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x16_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x16_raw"),
+        Some("v1:i0650")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0650"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x1_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643"),
+        Some("v1:i0643")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0643".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x1_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x1_pack16"),
+        Some("v1:i0643")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0643"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642"),
+        Some("v1:i0642")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0642".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x1_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x1_raw"),
+        Some("v1:i0642")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0642"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x2_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645"),
+        Some("v1:i0645")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0645".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x2_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x2_pack16"),
+        Some("v1:i0645")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0645"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644"),
+        Some("v1:i0644")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0644".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x2_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x2_raw"),
+        Some("v1:i0644")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0644"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x32_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653"),
+        Some("v1:i0653")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0653".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x32_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x32_pack16"),
+        Some("v1:i0653")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0653"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652"),
+        Some("v1:i0652")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0652".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x32_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x32_raw"),
+        Some("v1:i0652")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0652"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x4_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647"),
+        Some("v1:i0647")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0647".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x4_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x4_pack16"),
+        Some("v1:i0647")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0647"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646"),
+        Some("v1:i0646")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0646".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x4_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x4_raw"),
+        Some("v1:i0646")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0646"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x8_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649"),
+        Some("v1:i0649")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0649".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x8_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pack16"),
+        Some("v1:i0649")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0649"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x8_pure_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355"),
+        Some("v1:i0355")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0355".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x8_pure"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x8_pure"),
+        Some("v1:i0355")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0355"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x256b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648"),
+        Some("v1:i0648")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0648".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x256b_x8_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x256b_x8_raw"),
+        Some("v1:i0648")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0648"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x128_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743"),
+        Some("v1:i0743")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0743".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x128_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_pack16"),
+        Some("v1:i0743")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0743"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742"),
+        Some("v1:i0742")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0742".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x128_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x128_raw"),
+        Some("v1:i0742")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0742"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x16_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737"),
+        Some("v1:i0737")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0737".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x16_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_pack16"),
+        Some("v1:i0737")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0737"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736"),
+        Some("v1:i0736")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0736".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x16_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x16_raw"),
+        Some("v1:i0736")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0736"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x1_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729"),
+        Some("v1:i0729")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0729".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x1_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_pack16"),
+        Some("v1:i0729")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0729"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728"),
+        Some("v1:i0728")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0728".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x1_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x1_raw"),
+        Some("v1:i0728")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0728"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x2_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731"),
+        Some("v1:i0731")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0731".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x2_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_pack16"),
+        Some("v1:i0731")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0731"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730"),
+        Some("v1:i0730")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0730".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x2_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x2_raw"),
+        Some("v1:i0730")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0730"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x32_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739"),
+        Some("v1:i0739")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0739".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x32_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_pack16"),
+        Some("v1:i0739")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0739"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738"),
+        Some("v1:i0738")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0738".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x32_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x32_raw"),
+        Some("v1:i0738")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0738"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x4_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733"),
+        Some("v1:i0733")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0733".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x4_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_pack16"),
+        Some("v1:i0733")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0733"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732"),
+        Some("v1:i0732")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0732".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x4_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x4_raw"),
+        Some("v1:i0732")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0732"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x64_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741"),
+        Some("v1:i0741")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0741".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x64_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_pack16"),
+        Some("v1:i0741")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0741"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740"),
+        Some("v1:i0740")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0740".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x64_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x64_raw"),
+        Some("v1:i0740")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0740"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x8_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735"),
+        Some("v1:i0735")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0735".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x8_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_pack16"),
+        Some("v1:i0735")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0735"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x32bx2_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734"),
+        Some("v1:i0734")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0734".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x32bx2_x8_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_ld_16x32bx2_x8_raw"),
+        Some("v1:i0734")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0734"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x128_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627"),
+        Some("v1:i0627")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0627".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x128_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x128_pack16"),
+        Some("v1:i0627")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0627"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626"),
+        Some("v1:i0626")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0626".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x128_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x128_raw"),
+        Some("v1:i0626")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0626"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x16_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621"),
+        Some("v1:i0621")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0621".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x16_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x16_pack16"),
+        Some("v1:i0621")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0621"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620"),
+        Some("v1:i0620")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0620".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x16_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x16_raw"),
+        Some("v1:i0620")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0620"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x1_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613"),
+        Some("v1:i0613")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0613".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x1_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x1_pack16"),
+        Some("v1:i0613")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0613"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612"),
+        Some("v1:i0612")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0612".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x1_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x1_raw"),
+        Some("v1:i0612")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0612"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x2_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615"),
+        Some("v1:i0615")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0615".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x2_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x2_pack16"),
+        Some("v1:i0615")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0615"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614"),
+        Some("v1:i0614")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0614".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x2_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x2_raw"),
+        Some("v1:i0614")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0614"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x32_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623"),
+        Some("v1:i0623")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0623".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x32_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x32_pack16"),
+        Some("v1:i0623")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0623"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622"),
+        Some("v1:i0622")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0622".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x32_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x32_raw"),
+        Some("v1:i0622")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0622"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x4_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617"),
+        Some("v1:i0617")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0617".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x4_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x4_pack16"),
+        Some("v1:i0617")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0617"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616"),
+        Some("v1:i0616")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0616".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x4_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x4_raw"),
+        Some("v1:i0616")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0616"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x64_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625"),
+        Some("v1:i0625")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0625".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x64_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x64_pack16"),
+        Some("v1:i0625")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0625"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624"),
+        Some("v1:i0624")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0624".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x64_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x64_raw"),
+        Some("v1:i0624")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0624"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x8_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619"),
+        Some("v1:i0619")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0619".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x8_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x8_pack16"),
+        Some("v1:i0619")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0619"
+    ));
+}
+#[test]
+fn tcgen05_ld_16x64b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618"),
+        Some("v1:i0618")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0618".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_16x64b_x8_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_16x64b_x8_raw"),
+        Some("v1:i0618")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0618"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x128_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669"),
+        Some("v1:i0669")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0669".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x128_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x128_pack16"),
+        Some("v1:i0669")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0669"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668"),
+        Some("v1:i0668")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0668".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x128_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x128_raw"),
+        Some("v1:i0668")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0668"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x16_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663"),
+        Some("v1:i0663")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0663".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x16_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x16_pack16"),
+        Some("v1:i0663")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0663"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662"),
+        Some("v1:i0662")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0662".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x16_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x16_raw"),
+        Some("v1:i0662")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0662"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x1_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655"),
+        Some("v1:i0655")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0655".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x1_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x1_pack16"),
+        Some("v1:i0655")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0655"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654"),
+        Some("v1:i0654")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0654".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x1_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x1_raw"),
+        Some("v1:i0654")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0654"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x2_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657"),
+        Some("v1:i0657")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0657".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x2_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x2_pack16"),
+        Some("v1:i0657")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0657"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656"),
+        Some("v1:i0656")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0656".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x2_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x2_raw"),
+        Some("v1:i0656")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0656"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x32_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665"),
+        Some("v1:i0665")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0665".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x32_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x32_pack16"),
+        Some("v1:i0665")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0665"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664"),
+        Some("v1:i0664")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0664".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x32_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x32_raw"),
+        Some("v1:i0664")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0664"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x4_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659"),
+        Some("v1:i0659")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0659".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x4_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x4_pack16"),
+        Some("v1:i0659")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0659"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658"),
+        Some("v1:i0658")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0658".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x4_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x4_raw"),
+        Some("v1:i0658")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0658"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x64_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667"),
+        Some("v1:i0667")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0667".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x64_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x64_pack16"),
+        Some("v1:i0667")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0667"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666"),
+        Some("v1:i0666")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0666".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x64_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x64_raw"),
+        Some("v1:i0666")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0666"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x8_pack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661"),
+        Some("v1:i0661")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0661".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x8_pack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x8_pack16"),
+        Some("v1:i0661")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0661"
+    ));
+}
+#[test]
+fn tcgen05_ld_32x32b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660"),
+        Some("v1:i0660")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0660".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_ld_32x32b_x8_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_ld_32x32b_x8_raw"),
+        Some("v1:i0660")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0660"
+    ));
+}
+#[test]
+fn tcgen05_load_wait_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357"),
+        Some("v1:i0357")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0357".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_load_wait"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_load_wait"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_load_wait"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_load_wait"),
+        Some("v1:i0357")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0357"
+    ));
+}
+#[test]
+fn tcgen05_mma_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015"),
+        Some("v1:i1015")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1015".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_e2m1"),
+        Some("v1:i1015")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1015"
+    ));
+}
+#[test]
+fn tcgen05_mma_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013"),
+        Some("v1:i1013")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1013".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_e2m3"),
+        Some("v1:i1013")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1013"
+    ));
+}
+#[test]
+fn tcgen05_mma_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014"),
+        Some("v1:i1014")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1014".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_e3m2"),
+        Some("v1:i1014")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1014"
+    ));
+}
+#[test]
+fn tcgen05_mma_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011"),
+        Some("v1:i1011")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1011".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_e4m3"),
+        Some("v1:i1011")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1011"
+    ));
+}
+#[test]
+fn tcgen05_mma_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012"),
+        Some("v1:i1012")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1012".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_e5m2"),
+        Some("v1:i1012")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1012"
+    ));
+}
+#[test]
+fn tcgen05_mma_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351"),
+        Some("v1:i0351")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0351".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_f16"),
+        Some("v1:i0351")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0351"
+    ));
+}
+#[test]
+fn tcgen05_mma_f16_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362"),
+        Some("v1:i0362")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0362".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_f16_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_f16_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_f16_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_f16_cg2"),
+        Some("v1:i0362")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0362"
+    ));
+}
+#[test]
+fn tcgen05_mma_shared_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763"),
+        Some("v1:i0763")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0763".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_shared"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_shared"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_shared"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_shared"),
+        Some("v1:i0763")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0763"
+    ));
+}
+#[test]
+fn tcgen05_mma_sp_shared_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766"),
+        Some("v1:i0766")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0766".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_sp_shared"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_sp_shared"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_sp_shared"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_sp_shared"),
+        Some("v1:i0766")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0766"
+    ));
+}
+#[test]
+fn tcgen05_mma_sp_tensor_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767"),
+        Some("v1:i0767")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0767".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_sp_tensor"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_sp_tensor"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_sp_tensor"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_sp_tensor"),
+        Some("v1:i0767")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0767"
+    ));
+}
+#[test]
+fn tcgen05_mma_sp_tensor_ashift_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768"),
+        Some("v1:i0768")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0768".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_sp_tensor_ashift"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_sp_tensor_ashift"),
+        Some("v1:i0768")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0768"
+    ));
+}
+#[test]
+fn tcgen05_mma_tensor_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764"),
+        Some("v1:i0764")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0764".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_tensor"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_tensor"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_tensor"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_tensor"),
+        Some("v1:i0764")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0764"
+    ));
+}
+#[test]
+fn tcgen05_mma_tensor_ashift_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765"),
+        Some("v1:i0765")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0765".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_tensor_ashift"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_tensor_ashift"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_tensor_ashift"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_tensor_ashift"),
+        Some("v1:i0765")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0765"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_bf16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352"),
+        Some("v1:i0352")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0352".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_bf16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_bf16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_bf16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_bf16"),
+        Some("v1:i0352")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0352"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_e2m1_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781"),
+        Some("v1:i0781")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0781".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_e2m1"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_e2m1"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_e2m1"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_e2m1"),
+        Some("v1:i0781")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0781"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_e2m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779"),
+        Some("v1:i0779")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0779".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_e2m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_e2m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_e2m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_e2m3"),
+        Some("v1:i0779")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0779"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_e3m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780"),
+        Some("v1:i0780")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0780".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_e3m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_e3m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_e3m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_e3m2"),
+        Some("v1:i0780")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0780"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_e4m3_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777"),
+        Some("v1:i0777")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0777".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_e4m3"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_e4m3"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_e4m3"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_e4m3"),
+        Some("v1:i0777")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0777"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_e5m2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778"),
+        Some("v1:i0778")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0778".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_e5m2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_e5m2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_e5m2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_e5m2"),
+        Some("v1:i0778")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0778"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_f16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350"),
+        Some("v1:i0350")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0350".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_f16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_f16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_f16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_f16"),
+        Some("v1:i0350")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0350"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_shared_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769"),
+        Some("v1:i0769")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0769".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_shared"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_shared"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_shared"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_ws_shared"),
+        Some("v1:i0769")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0769"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_shared_zero_col_mask_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770"),
+        Some("v1:i0770")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0770".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_shared_zero_col_mask"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_ws_shared_zero_col_mask"),
+        Some("v1:i0770")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0770"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_sp_shared_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771"),
+        Some("v1:i0771")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0771".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_sp_shared"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared"),
+        Some("v1:i0771")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0771"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_sp_shared_zero_col_mask_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772"),
+        Some("v1:i0772")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0772".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_sp_shared_zero_col_mask"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tcgen05::__tcgen05_mma_ws_sp_shared_zero_col_mask"
+        ),
+        Some("v1:i0772")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0772"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_sp_tensor_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773"),
+        Some("v1:i0773")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0773".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_sp_tensor"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor"),
+        Some("v1:i0773")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0773"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_sp_tensor_zero_col_mask_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774"),
+        Some("v1:i0774")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0774".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_sp_tensor_zero_col_mask"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tcgen05::__tcgen05_mma_ws_sp_tensor_zero_col_mask"
+        ),
+        Some("v1:i0774")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0774"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_tensor_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775"),
+        Some("v1:i0775")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0775".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_tensor"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_tensor"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_tensor"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_ws_tensor"),
+        Some("v1:i0775")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0775"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_tensor_zero_col_mask_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776"),
+        Some("v1:i0776")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0776".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_tensor_zero_col_mask"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_mma_ws_tensor_zero_col_mask"),
+        Some("v1:i0776")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0776"
+    ));
+}
+#[test]
+fn tcgen05_mma_ws_tf32_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353"),
+        Some("v1:i0353")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0353".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_mma_ws_tf32"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_tf32"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_mma_ws_tf32"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_mma_ws_tf32"),
+        Some("v1:i0353")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0353"
+    ));
+}
+#[test]
+fn tcgen05_relinquish_alloc_permit_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345"),
+        Some("v1:i0345")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0345".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_relinquish_alloc_permit"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_relinquish_alloc_permit"),
+        Some("v1:i0345")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0345"
+    ));
+}
+#[test]
+fn tcgen05_relinquish_alloc_permit_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361"),
+        Some("v1:i0361")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0361".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_relinquish_alloc_permit_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_relinquish_alloc_permit_cg2"),
+        Some("v1:i0361")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0361"
+    ));
+}
+#[test]
+fn tcgen05_shift_down_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761"),
+        Some("v1:i0761")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0761".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_shift_down"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_shift_down"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_shift_down"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_shift_down"),
+        Some("v1:i0761")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0761"
+    ));
+}
+#[test]
+fn tcgen05_shift_down_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762"),
+        Some("v1:i0762")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0762".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_shift_down_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_shift_down_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_shift_down_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_shift_down_cg2"),
+        Some("v1:i0762")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0762"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694"),
+        Some("v1:i0694")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0694".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x16_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x16_raw"),
+        Some("v1:i0694")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0694"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x16_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695"),
+        Some("v1:i0695")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0695".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x16_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x16_unpack16"),
+        Some("v1:i0695")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0695"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686"),
+        Some("v1:i0686")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0686".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x1_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x1_raw"),
+        Some("v1:i0686")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0686"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x1_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687"),
+        Some("v1:i0687")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0687".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x1_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x1_unpack16"),
+        Some("v1:i0687")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0687"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688"),
+        Some("v1:i0688")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0688".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x2_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x2_raw"),
+        Some("v1:i0688")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0688"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x2_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689"),
+        Some("v1:i0689")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0689".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x2_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x2_unpack16"),
+        Some("v1:i0689")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0689"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696"),
+        Some("v1:i0696")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0696".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x32_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x32_raw"),
+        Some("v1:i0696")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0696"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x32_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697"),
+        Some("v1:i0697")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0697".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x32_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x32_unpack16"),
+        Some("v1:i0697")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0697"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690"),
+        Some("v1:i0690")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0690".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x4_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x4_raw"),
+        Some("v1:i0690")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0690"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x4_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691"),
+        Some("v1:i0691")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0691".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x4_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x4_unpack16"),
+        Some("v1:i0691")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0691"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698"),
+        Some("v1:i0698")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0698".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x64_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x64_raw"),
+        Some("v1:i0698")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0698"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x64_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699"),
+        Some("v1:i0699")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0699".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x64_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x64_unpack16"),
+        Some("v1:i0699")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0699"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692"),
+        Some("v1:i0692")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0692".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x8_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x8_raw"),
+        Some("v1:i0692")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0692"
+    ));
+}
+#[test]
+fn tcgen05_st_16x128b_x8_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693"),
+        Some("v1:i0693")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0693".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x128b_x8_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x128b_x8_unpack16"),
+        Some("v1:i0693")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0693"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708"),
+        Some("v1:i0708")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0708".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x16_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x16_raw"),
+        Some("v1:i0708")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0708"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x16_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709"),
+        Some("v1:i0709")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0709".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x16_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x16_unpack16"),
+        Some("v1:i0709")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0709"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700"),
+        Some("v1:i0700")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0700".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x1_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x1_raw"),
+        Some("v1:i0700")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0700"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x1_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701"),
+        Some("v1:i0701")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0701".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x1_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x1_unpack16"),
+        Some("v1:i0701")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0701"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702"),
+        Some("v1:i0702")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0702".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x2_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x2_raw"),
+        Some("v1:i0702")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0702"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x2_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703"),
+        Some("v1:i0703")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0703".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x2_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x2_unpack16"),
+        Some("v1:i0703")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0703"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710"),
+        Some("v1:i0710")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0710".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x32_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x32_raw"),
+        Some("v1:i0710")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0710"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x32_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711"),
+        Some("v1:i0711")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0711".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x32_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x32_unpack16"),
+        Some("v1:i0711")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0711"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704"),
+        Some("v1:i0704")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0704".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x4_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x4_raw"),
+        Some("v1:i0704")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0704"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x4_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705"),
+        Some("v1:i0705")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0705".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x4_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x4_unpack16"),
+        Some("v1:i0705")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0705"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706"),
+        Some("v1:i0706")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0706".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x8_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x8_raw"),
+        Some("v1:i0706")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0706"
+    ));
+}
+#[test]
+fn tcgen05_st_16x256b_x8_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707"),
+        Some("v1:i0707")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0707".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x256b_x8_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x256b_x8_unpack16"),
+        Some("v1:i0707")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0707"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758"),
+        Some("v1:i0758")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0758".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x128_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_raw"),
+        Some("v1:i0758")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0758"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x128_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759"),
+        Some("v1:i0759")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0759".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x128_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x128_unpack16"),
+        Some("v1:i0759")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0759"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752"),
+        Some("v1:i0752")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0752".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x16_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_raw"),
+        Some("v1:i0752")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0752"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x16_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753"),
+        Some("v1:i0753")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0753".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x16_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x16_unpack16"),
+        Some("v1:i0753")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0753"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744"),
+        Some("v1:i0744")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0744".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x1_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_raw"),
+        Some("v1:i0744")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0744"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x1_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745"),
+        Some("v1:i0745")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0745".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x1_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x1_unpack16"),
+        Some("v1:i0745")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0745"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746"),
+        Some("v1:i0746")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0746".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x2_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_raw"),
+        Some("v1:i0746")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0746"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x2_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747"),
+        Some("v1:i0747")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0747".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x2_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x2_unpack16"),
+        Some("v1:i0747")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0747"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754"),
+        Some("v1:i0754")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0754".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x32_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_raw"),
+        Some("v1:i0754")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0754"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x32_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755"),
+        Some("v1:i0755")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0755".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x32_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x32_unpack16"),
+        Some("v1:i0755")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0755"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748"),
+        Some("v1:i0748")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0748".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x4_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_raw"),
+        Some("v1:i0748")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0748"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x4_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749"),
+        Some("v1:i0749")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0749".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x4_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x4_unpack16"),
+        Some("v1:i0749")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0749"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756"),
+        Some("v1:i0756")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0756".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x64_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_raw"),
+        Some("v1:i0756")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0756"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x64_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757"),
+        Some("v1:i0757")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0757".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x64_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x64_unpack16"),
+        Some("v1:i0757")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0757"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750"),
+        Some("v1:i0750")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0750".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x8_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_raw"),
+        Some("v1:i0750")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0750"
+    ));
+}
+#[test]
+fn tcgen05_st_16x32bx2_x8_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751"),
+        Some("v1:i0751")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0751".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x32bx2_x8_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::__tcgen05_st_16x32bx2_x8_unpack16"),
+        Some("v1:i0751")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0751"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684"),
+        Some("v1:i0684")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0684".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x128_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x128_raw"),
+        Some("v1:i0684")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0684"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x128_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685"),
+        Some("v1:i0685")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0685".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x128_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x128_unpack16"),
+        Some("v1:i0685")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0685"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678"),
+        Some("v1:i0678")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0678".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x16_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x16_raw"),
+        Some("v1:i0678")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0678"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x16_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679"),
+        Some("v1:i0679")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0679".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x16_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x16_unpack16"),
+        Some("v1:i0679")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0679"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670"),
+        Some("v1:i0670")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0670".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x1_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x1_raw"),
+        Some("v1:i0670")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0670"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x1_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671"),
+        Some("v1:i0671")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0671".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x1_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x1_unpack16"),
+        Some("v1:i0671")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0671"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672"),
+        Some("v1:i0672")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0672".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x2_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x2_raw"),
+        Some("v1:i0672")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0672"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x2_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673"),
+        Some("v1:i0673")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0673".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x2_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x2_unpack16"),
+        Some("v1:i0673")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0673"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680"),
+        Some("v1:i0680")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0680".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x32_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x32_raw"),
+        Some("v1:i0680")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0680"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x32_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681"),
+        Some("v1:i0681")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0681".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x32_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x32_unpack16"),
+        Some("v1:i0681")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0681"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674"),
+        Some("v1:i0674")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0674".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x4_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x4_raw"),
+        Some("v1:i0674")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0674"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x4_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675"),
+        Some("v1:i0675")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0675".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x4_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x4_unpack16"),
+        Some("v1:i0675")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0675"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682"),
+        Some("v1:i0682")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0682".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x64_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x64_raw"),
+        Some("v1:i0682")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0682"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x64_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683"),
+        Some("v1:i0683")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0683".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x64_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x64_unpack16"),
+        Some("v1:i0683")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0683"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676"),
+        Some("v1:i0676")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0676".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x8_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x8_raw"),
+        Some("v1:i0676")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0676"
+    ));
+}
+#[test]
+fn tcgen05_st_16x64b_x8_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677"),
+        Some("v1:i0677")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0677".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_16x64b_x8_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_16x64b_x8_unpack16"),
+        Some("v1:i0677")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0677"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x128_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726"),
+        Some("v1:i0726")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0726".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x128_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x128_raw"),
+        Some("v1:i0726")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0726"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x128_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727"),
+        Some("v1:i0727")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0727".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x128_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x128_unpack16"),
+        Some("v1:i0727")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0727"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x16_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720"),
+        Some("v1:i0720")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0720".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x16_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x16_raw"),
+        Some("v1:i0720")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0720"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x16_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721"),
+        Some("v1:i0721")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0721".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x16_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x16_unpack16"),
+        Some("v1:i0721")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0721"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x1_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712"),
+        Some("v1:i0712")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0712".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x1_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x1_raw"),
+        Some("v1:i0712")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0712"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x1_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713"),
+        Some("v1:i0713")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0713".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x1_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x1_unpack16"),
+        Some("v1:i0713")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0713"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x2_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714"),
+        Some("v1:i0714")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0714".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x2_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x2_raw"),
+        Some("v1:i0714")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0714"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x2_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715"),
+        Some("v1:i0715")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0715".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x2_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x2_unpack16"),
+        Some("v1:i0715")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0715"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x32_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722"),
+        Some("v1:i0722")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0722".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x32_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x32_raw"),
+        Some("v1:i0722")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0722"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x32_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723"),
+        Some("v1:i0723")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0723".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x32_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x32_unpack16"),
+        Some("v1:i0723")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0723"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x4_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716"),
+        Some("v1:i0716")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0716".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x4_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x4_raw"),
+        Some("v1:i0716")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0716"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x4_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717"),
+        Some("v1:i0717")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0717".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x4_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x4_unpack16"),
+        Some("v1:i0717")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0717"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x64_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724"),
+        Some("v1:i0724")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0724".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x64_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x64_raw"),
+        Some("v1:i0724")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0724"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x64_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725"),
+        Some("v1:i0725")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0725".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x64_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x64_unpack16"),
+        Some("v1:i0725")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0725"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x8_raw_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718"),
+        Some("v1:i0718")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0718".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x8_raw"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x8_raw"),
+        Some("v1:i0718")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0718"
+    ));
+}
+#[test]
+fn tcgen05_st_32x32b_x8_unpack16_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719"),
+        Some("v1:i0719")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0719".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_st_32x32b_x8_unpack16"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_st_32x32b_x8_unpack16"),
+        Some("v1:i0719")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0719"
+    ));
+}
+#[test]
+fn tcgen05_store_wait_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358"),
+        Some("v1:i0358")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0358".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tcgen05::tcgen05_store_wait"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_store_wait"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tcgen05::tcgen05_store_wait"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tcgen05::tcgen05_store_wait"),
+        Some("v1:i0358")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0358"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs
new file mode 100644
index 0000000000..f2e407340d
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs
@@ -0,0 +1,4030 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `tma` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn cp_async_bulk_commit_group_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"),
+        Some("v1:i0340")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_commit_group"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_commit_group"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_commit_group"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_commit_group"),
+        Some("v1:i0340")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0340"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_1d_l2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"),
+        Some("v1:i0888")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_1d_l2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2"),
+        Some("v1:i0888")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0888"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_1d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"),
+        Some("v1:i0917")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint"
+        ),
+        Some("v1:i0917")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0917"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_2d_l2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"),
+        Some("v1:i0889")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_2d_l2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2"),
+        Some("v1:i0889")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0889"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_2d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"),
+        Some("v1:i0918")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint"
+        ),
+        Some("v1:i0918")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0918"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_3d_l2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"),
+        Some("v1:i0890")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_3d_l2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2"),
+        Some("v1:i0890")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0890"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_3d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"),
+        Some("v1:i0919")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint"
+        ),
+        Some("v1:i0919")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0919"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_4d_l2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"),
+        Some("v1:i0891")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_4d_l2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2"),
+        Some("v1:i0891")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0891"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_4d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"),
+        Some("v1:i0920")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint"
+        ),
+        Some("v1:i0920")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0920"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_5d_l2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"),
+        Some("v1:i0892")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_5d_l2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2"),
+        Some("v1:i0892")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0892"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_5d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"),
+        Some("v1:i0921")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint"
+        ),
+        Some("v1:i0921")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0921"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_gather4_2d_l2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"),
+        Some("v1:i0893")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2"),
+        Some("v1:i0893")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0893"
+    ));
+}
+#[test]
+fn cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint_uses_only_canonical_or_compatibility_defpaths()
+ {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"),
+        Some("v1:i0922")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint"
+        ),
+        Some("v1:i0922")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0922"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_1d_g2s_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"),
+        Some("v1:i0328")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_1d_g2s"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_1d_g2s"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_1d_g2s"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_1d_g2s"),
+        Some("v1:i0328")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0328"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_1d_s2g_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"),
+        Some("v1:i0335")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_1d_s2g"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_1d_s2g"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_1d_s2g"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_1d_s2g"),
+        Some("v1:i0335")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0335"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_2d_g2s_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"),
+        Some("v1:i0329")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_2d_g2s"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_2d_g2s"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_2d_g2s"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_2d_g2s"),
+        Some("v1:i0329")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0329"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_2d_g2s_multicast_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"),
+        Some("v1:i0330")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_2d_g2s_multicast"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast"),
+        Some("v1:i0330")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0330"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_2d_g2s_multicast_cg2_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"),
+        Some("v1:i0331")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2"),
+        Some("v1:i0331")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0331"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_2d_s2g_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"),
+        Some("v1:i0336")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_2d_s2g"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_2d_s2g"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_2d_s2g"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_2d_s2g"),
+        Some("v1:i0336")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0336"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_3d_g2s_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"),
+        Some("v1:i0332")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_3d_g2s"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_3d_g2s"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_3d_g2s"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_3d_g2s"),
+        Some("v1:i0332")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0332"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_3d_s2g_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"),
+        Some("v1:i0337")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_3d_s2g"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_3d_s2g"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_3d_s2g"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_3d_s2g"),
+        Some("v1:i0337")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0337"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_4d_g2s_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"),
+        Some("v1:i0333")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_4d_g2s"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_4d_g2s"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_4d_g2s"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_4d_g2s"),
+        Some("v1:i0333")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0333"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_4d_s2g_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"),
+        Some("v1:i0338")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_4d_s2g"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_4d_s2g"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_4d_s2g"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_4d_s2g"),
+        Some("v1:i0338")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0338"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_5d_g2s_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"),
+        Some("v1:i0334")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_5d_g2s"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_5d_g2s"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_5d_g2s"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_5d_g2s"),
+        Some("v1:i0334")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0334"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_5d_s2g_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"),
+        Some("v1:i0339")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_5d_s2g"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_5d_s2g"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_5d_s2g"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_5d_s2g"),
+        Some("v1:i0339")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0339"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_add_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"),
+        Some("v1:i0928")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_im2col_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d"),
+        Some("v1:i0928")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0928"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_add_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"),
+        Some("v1:i0929")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_im2col_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d"),
+        Some("v1:i0929")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0929"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_add_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"),
+        Some("v1:i0930")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_im2col_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d"),
+        Some("v1:i0930")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0930"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_add_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"),
+        Some("v1:i0923")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_tile_1d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d"),
+        Some("v1:i0923")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0923"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_add_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"),
+        Some("v1:i0924")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_tile_2d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d"),
+        Some("v1:i0924")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0924"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_add_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"),
+        Some("v1:i0925")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_tile_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d"),
+        Some("v1:i0925")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0925"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_add_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"),
+        Some("v1:i0926")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_tile_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d"),
+        Some("v1:i0926")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0926"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_add_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"),
+        Some("v1:i0927")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_add_tile_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d"),
+        Some("v1:i0927")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0927"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_and_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"),
+        Some("v1:i0936")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_im2col_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d"),
+        Some("v1:i0936")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0936"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_and_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"),
+        Some("v1:i0937")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_im2col_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d"),
+        Some("v1:i0937")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0937"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_and_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"),
+        Some("v1:i0938")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_im2col_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d"),
+        Some("v1:i0938")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0938"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_and_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"),
+        Some("v1:i0931")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_tile_1d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d"),
+        Some("v1:i0931")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0931"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_and_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"),
+        Some("v1:i0932")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_tile_2d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d"),
+        Some("v1:i0932")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0932"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_and_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"),
+        Some("v1:i0933")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_tile_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d"),
+        Some("v1:i0933")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0933"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_and_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"),
+        Some("v1:i0934")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_tile_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d"),
+        Some("v1:i0934")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0934"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_and_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"),
+        Some("v1:i0935")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_and_tile_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d"),
+        Some("v1:i0935")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0935"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"),
+        Some("v1:i0944")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d"),
+        Some("v1:i0944")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0944"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"),
+        Some("v1:i0945")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d"),
+        Some("v1:i0945")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0945"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"),
+        Some("v1:i0946")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d"),
+        Some("v1:i0946")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0946"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"),
+        Some("v1:i0939")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_tile_1d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d"),
+        Some("v1:i0939")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0939"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"),
+        Some("v1:i0940")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_tile_2d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d"),
+        Some("v1:i0940")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0940"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"),
+        Some("v1:i0941")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_tile_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d"),
+        Some("v1:i0941")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0941"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"),
+        Some("v1:i0942")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_tile_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d"),
+        Some("v1:i0942")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0942"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_dec_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"),
+        Some("v1:i0943")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_dec_tile_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d"),
+        Some("v1:i0943")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0943"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"),
+        Some("v1:i0952")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d"),
+        Some("v1:i0952")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0952"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"),
+        Some("v1:i0953")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d"),
+        Some("v1:i0953")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0953"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"),
+        Some("v1:i0954")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d"),
+        Some("v1:i0954")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0954"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"),
+        Some("v1:i0947")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_tile_1d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d"),
+        Some("v1:i0947")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0947"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"),
+        Some("v1:i0948")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_tile_2d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d"),
+        Some("v1:i0948")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0948"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"),
+        Some("v1:i0949")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_tile_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d"),
+        Some("v1:i0949")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0949"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"),
+        Some("v1:i0950")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_tile_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d"),
+        Some("v1:i0950")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0950"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_inc_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"),
+        Some("v1:i0951")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_inc_tile_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d"),
+        Some("v1:i0951")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0951"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_max_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"),
+        Some("v1:i0960")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_im2col_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d"),
+        Some("v1:i0960")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0960"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_max_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"),
+        Some("v1:i0961")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_im2col_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d"),
+        Some("v1:i0961")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0961"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_max_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"),
+        Some("v1:i0962")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_im2col_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d"),
+        Some("v1:i0962")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0962"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_max_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"),
+        Some("v1:i0955")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_tile_1d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d"),
+        Some("v1:i0955")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0955"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_max_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"),
+        Some("v1:i0956")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_tile_2d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d"),
+        Some("v1:i0956")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0956"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_max_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"),
+        Some("v1:i0957")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_tile_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d"),
+        Some("v1:i0957")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0957"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_max_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"),
+        Some("v1:i0958")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_tile_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d"),
+        Some("v1:i0958")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0958"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_max_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"),
+        Some("v1:i0959")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_max_tile_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d"),
+        Some("v1:i0959")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0959"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_min_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"),
+        Some("v1:i0968")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_im2col_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d"),
+        Some("v1:i0968")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0968"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_min_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"),
+        Some("v1:i0969")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_im2col_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d"),
+        Some("v1:i0969")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0969"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_min_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"),
+        Some("v1:i0970")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_im2col_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d"),
+        Some("v1:i0970")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0970"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_min_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"),
+        Some("v1:i0963")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_tile_1d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d"),
+        Some("v1:i0963")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0963"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_min_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"),
+        Some("v1:i0964")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_tile_2d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d"),
+        Some("v1:i0964")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0964"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_min_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"),
+        Some("v1:i0965")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_tile_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d"),
+        Some("v1:i0965")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0965"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_min_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"),
+        Some("v1:i0966")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_tile_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d"),
+        Some("v1:i0966")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0966"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_min_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"),
+        Some("v1:i0967")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_min_tile_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d"),
+        Some("v1:i0967")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0967"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_or_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"),
+        Some("v1:i0976")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_im2col_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d"),
+        Some("v1:i0976")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0976"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_or_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"),
+        Some("v1:i0977")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_im2col_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d"),
+        Some("v1:i0977")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0977"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_or_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"),
+        Some("v1:i0978")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_im2col_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d"),
+        Some("v1:i0978")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0978"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_or_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"),
+        Some("v1:i0971")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_tile_1d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d"),
+        Some("v1:i0971")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0971"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_or_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"),
+        Some("v1:i0972")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_tile_2d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d"),
+        Some("v1:i0972")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0972"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_or_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"),
+        Some("v1:i0973")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_tile_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d"),
+        Some("v1:i0973")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0973"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_or_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"),
+        Some("v1:i0974")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_tile_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d"),
+        Some("v1:i0974")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0974"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_or_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"),
+        Some("v1:i0975")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_or_tile_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d"),
+        Some("v1:i0975")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0975"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_im2col_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"),
+        Some("v1:i0984")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d"),
+        Some("v1:i0984")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0984"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_im2col_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"),
+        Some("v1:i0985")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d"),
+        Some("v1:i0985")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0985"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_im2col_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"),
+        Some("v1:i0986")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d"),
+        Some("v1:i0986")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0986"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_tile_1d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"),
+        Some("v1:i0979")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_tile_1d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d"),
+        Some("v1:i0979")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0979"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_tile_2d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"),
+        Some("v1:i0980")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_tile_2d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d"),
+        Some("v1:i0980")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0980"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_tile_3d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"),
+        Some("v1:i0981")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_tile_3d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d"),
+        Some("v1:i0981")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0981"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_tile_4d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"),
+        Some("v1:i0982")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_tile_4d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d"),
+        Some("v1:i0982")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0982"
+    ));
+}
+#[test]
+fn cp_async_bulk_tensor_reduce_xor_tile_5d_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"),
+        Some("v1:i0983")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_tensor_reduce_xor_tile_5d"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d"),
+        Some("v1:i0983")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0983"
+    ));
+}
+#[test]
+fn cp_async_bulk_wait_group_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"),
+        Some("v1:i0341")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_wait_group"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_wait_group"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_wait_group"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_wait_group"),
+        Some("v1:i0341")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0341"
+    ));
+}
+#[test]
+fn cp_async_bulk_wait_group_read_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"),
+        Some("v1:i0342")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::cp_async_bulk_wait_group_read"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_wait_group_read"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::cp_async_bulk_wait_group_read"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::cp_async_bulk_wait_group_read"),
+        Some("v1:i0342")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0342"
+    ));
+}
+#[test]
+fn fence_proxy_tensormap_generic_acquire_cluster_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"),
+        Some("v1:i0905")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::fence_proxy_tensormap_generic_acquire_cluster"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster"
+        ),
+        Some("v1:i0905")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0905"
+    ));
+}
+#[test]
+fn fence_proxy_tensormap_generic_acquire_cta_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"),
+        Some("v1:i0906")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::fence_proxy_tensormap_generic_acquire_cta"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta"),
+        Some("v1:i0906")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0906"
+    ));
+}
+#[test]
+fn fence_proxy_tensormap_generic_acquire_gpu_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"),
+        Some("v1:i0907")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::fence_proxy_tensormap_generic_acquire_gpu"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu"),
+        Some("v1:i0907")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0907"
+    ));
+}
+#[test]
+fn fence_proxy_tensormap_generic_acquire_system_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"),
+        Some("v1:i0908")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::fence_proxy_tensormap_generic_acquire_system"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system"
+        ),
+        Some("v1:i0908")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0908"
+    ));
+}
+#[test]
+fn fence_proxy_tensormap_generic_release_cluster_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"),
+        Some("v1:i0909")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::fence_proxy_tensormap_generic_release_cluster"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster"
+        ),
+        Some("v1:i0909")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0909"
+    ));
+}
+#[test]
+fn fence_proxy_tensormap_generic_release_cta_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"),
+        Some("v1:i0910")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::fence_proxy_tensormap_generic_release_cta"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_release_cta"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_release_cta"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::fence_proxy_tensormap_generic_release_cta"),
+        Some("v1:i0910")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0910"
+    ));
+}
+#[test]
+fn fence_proxy_tensormap_generic_release_gpu_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"),
+        Some("v1:i0911")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::fence_proxy_tensormap_generic_release_gpu"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::fence_proxy_tensormap_generic_release_gpu"),
+        Some("v1:i0911")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0911"
+    ));
+}
+#[test]
+fn fence_proxy_tensormap_generic_release_system_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"),
+        Some("v1:i0912")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::fence_proxy_tensormap_generic_release_system"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_release_system"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::fence_proxy_tensormap_generic_release_system"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker(
+            "cuda_device::tma::fence_proxy_tensormap_generic_release_system"
+        ),
+        Some("v1:i0912")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0912"
+    ));
+}
+#[test]
+fn prefetch_tma_descriptor_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"),
+        Some("v1:i0887")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::prefetch_tma_descriptor"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::prefetch_tma_descriptor"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::prefetch_tma_descriptor"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::prefetch_tma_descriptor"),
+        Some("v1:i0887")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0887"
+    ));
+}
+#[test]
+fn tensormap_replace_box_dim_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"),
+        Some("v1:i0894")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_box_dim"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_box_dim"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_box_dim"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_box_dim"),
+        Some("v1:i0894")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0894"
+    ));
+}
+#[test]
+fn tensormap_replace_element_stride_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"),
+        Some("v1:i0895")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_element_stride"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_element_stride"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_element_stride"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_element_stride"),
+        Some("v1:i0895")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0895"
+    ));
+}
+#[test]
+fn tensormap_replace_element_type_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"),
+        Some("v1:i0896")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_element_type"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_element_type"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_element_type"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_element_type"),
+        Some("v1:i0896")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0896"
+    ));
+}
+#[test]
+fn tensormap_replace_fill_mode_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"),
+        Some("v1:i0897")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_fill_mode"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_fill_mode"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_fill_mode"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_fill_mode"),
+        Some("v1:i0897")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0897"
+    ));
+}
+#[test]
+fn tensormap_replace_global_address_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"),
+        Some("v1:i0898")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_global_address"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_global_address"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_global_address"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_global_address"),
+        Some("v1:i0898")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0898"
+    ));
+}
+#[test]
+fn tensormap_replace_global_dim_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"),
+        Some("v1:i0899")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_global_dim"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_global_dim"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_global_dim"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_global_dim"),
+        Some("v1:i0899")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0899"
+    ));
+}
+#[test]
+fn tensormap_replace_global_stride_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"),
+        Some("v1:i0900")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_global_stride"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_global_stride"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_global_stride"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_global_stride"),
+        Some("v1:i0900")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0900"
+    ));
+}
+#[test]
+fn tensormap_replace_interleave_layout_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"),
+        Some("v1:i0901")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_interleave_layout"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_interleave_layout"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_interleave_layout"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_interleave_layout"),
+        Some("v1:i0901")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0901"
+    ));
+}
+#[test]
+fn tensormap_replace_rank_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"),
+        Some("v1:i0902")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_rank"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_rank"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_rank"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_rank"),
+        Some("v1:i0902")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0902"
+    ));
+}
+#[test]
+fn tensormap_replace_swizzle_atomicity_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"),
+        Some("v1:i0903")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_swizzle_atomicity"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_swizzle_atomicity"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_swizzle_atomicity"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_swizzle_atomicity"),
+        Some("v1:i0903")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0903"
+    ));
+}
+#[test]
+fn tensormap_replace_swizzle_mode_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"),
+        Some("v1:i0904")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::tma::tensormap_replace_swizzle_mode"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_swizzle_mode"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::tma::tensormap_replace_swizzle_mode"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::tma::tensormap_replace_swizzle_mode"),
+        Some("v1:i0904")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0904"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs
new file mode 100644
index 0000000000..3857ba798c
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs
@@ -0,0 +1,143 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `vote` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn all_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040"),
+        Some("v1:i0040")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::all_sync"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::warp::all_sync"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::all_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::all_sync"),
+        Some("v1:i0040")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0040"
+    ));
+}
+#[test]
+fn any_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041"),
+        Some("v1:i0041")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::any_sync"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::warp::any_sync"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::any_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::any_sync"),
+        Some("v1:i0041")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0041"
+    ));
+}
+#[test]
+fn ballot_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"),
+        Some("v1:i0042")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::ballot_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::ballot_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::ballot_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::ballot_sync"),
+        Some("v1:i0042")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0042"
+    ));
+}
+#[test]
+fn uni_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043"),
+        Some("v1:i0043")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::uni_sync"
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0043"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs
new file mode 100644
index 0000000000..8c4446ed5f
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs
@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `warp_barrier` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn sync_mask_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"),
+        Some("v1:i0049")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::sync_mask"
+    ));
+    assert!(is_generated_intrinsic_path("cuda_device::warp::sync_mask"));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::sync_mask"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::sync_mask"),
+        Some("v1:i0049")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0049"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs
new file mode 100644
index 0000000000..0ecc2baa8d
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs
@@ -0,0 +1,157 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `warp_match` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn match_all_i64_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"),
+        Some("v1:i0048")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::match_all_i64_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::match_all_i64_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::match_all_i64_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::match_all_i64_sync"),
+        Some("v1:i0048")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0048"
+    ));
+}
+#[test]
+fn match_all_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"),
+        Some("v1:i0047")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::match_all_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::match_all_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::match_all_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::match_all_sync"),
+        Some("v1:i0047")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0047"
+    ));
+}
+#[test]
+fn match_any_i64_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"),
+        Some("v1:i0046")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::match_any_i64_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::match_any_i64_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::match_any_i64_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::match_any_i64_sync"),
+        Some("v1:i0046")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0046"
+    ));
+}
+#[test]
+fn match_any_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"),
+        Some("v1:i0045")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::match_any_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::match_any_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::match_any_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::match_any_sync"),
+        Some("v1:i0045")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0045"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs
new file mode 100644
index 0000000000..3236f26a35
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs
@@ -0,0 +1,445 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `warp_shuffle` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn shuffle_down_f32_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"),
+        Some("v1:i0056")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_down_f32_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_down_f32_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_down_f32_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_down_f32_sync"),
+        Some("v1:i0056")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0056"
+    ));
+}
+#[test]
+fn shuffle_down_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"),
+        Some("v1:i0052")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_down_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_down_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_down_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_down_sync"),
+        Some("v1:i0052")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0052"
+    ));
+}
+#[test]
+fn shuffle_down_u64_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"),
+        Some("v1:i0060")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_down_u64_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_down_u64_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_down_u64_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_down_u64_sync"),
+        Some("v1:i0060")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0060"
+    ));
+}
+#[test]
+fn shuffle_f32_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"),
+        Some("v1:i0054")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_f32_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_f32_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_f32_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_f32_sync"),
+        Some("v1:i0054")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0054"
+    ));
+}
+#[test]
+fn shuffle_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"),
+        Some("v1:i0050")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_sync"),
+        Some("v1:i0050")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0050"
+    ));
+}
+#[test]
+fn shuffle_u64_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"),
+        Some("v1:i0058")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_u64_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_u64_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_u64_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_u64_sync"),
+        Some("v1:i0058")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0058"
+    ));
+}
+#[test]
+fn shuffle_up_f32_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"),
+        Some("v1:i0057")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_up_f32_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_up_f32_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_up_f32_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_up_f32_sync"),
+        Some("v1:i0057")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0057"
+    ));
+}
+#[test]
+fn shuffle_up_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"),
+        Some("v1:i0053")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_up_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_up_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_up_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_up_sync"),
+        Some("v1:i0053")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0053"
+    ));
+}
+#[test]
+fn shuffle_up_u64_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"),
+        Some("v1:i0061")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_up_u64_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_up_u64_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_up_u64_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_up_u64_sync"),
+        Some("v1:i0061")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0061"
+    ));
+}
+#[test]
+fn shuffle_xor_f32_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"),
+        Some("v1:i0055")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_xor_f32_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_xor_f32_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_xor_f32_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_xor_f32_sync"),
+        Some("v1:i0055")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0055"
+    ));
+}
+#[test]
+fn shuffle_xor_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"),
+        Some("v1:i0051")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_xor_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_xor_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_xor_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_xor_sync"),
+        Some("v1:i0051")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0051"
+    ));
+}
+#[test]
+fn shuffle_xor_u64_sync_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"),
+        Some("v1:i0059")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::warp::shuffle_xor_u64_sync"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_xor_u64_sync"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::warp::shuffle_xor_u64_sync"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::warp::shuffle_xor_u64_sync"),
+        Some("v1:i0059")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0059"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs
new file mode 100644
index 0000000000..3d8084c72f
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs
@@ -0,0 +1,121 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated dispatch-path tests: `wgmma_control` intrinsics.
+
+use super::super::*;
+
+#[test]
+fn wgmma_commit_group_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"),
+        Some("v1:i0318")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::wgmma::wgmma_commit_group"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wgmma::wgmma_commit_group"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wgmma::wgmma_commit_group"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wgmma::wgmma_commit_group"),
+        Some("v1:i0318")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0318"
+    ));
+}
+#[test]
+fn wgmma_fence_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"),
+        Some("v1:i0317")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::wgmma::wgmma_fence"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wgmma::wgmma_fence"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wgmma::wgmma_fence"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wgmma::wgmma_fence"),
+        Some("v1:i0317")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0317"
+    ));
+}
+#[test]
+fn wgmma_wait_group_uses_only_canonical_or_compatibility_defpaths() {
+    assert!(is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
+    ));
+    assert!(is_raw_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"),
+        Some("v1:i0319")
+    );
+    assert!(matches!(
+        classify_raw_intrinsic_path(
+            "cuda_intrinsics",
+            "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319".into()
+        ),
+        RawIntrinsicIdentity::Known(_)
+    ));
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::wgmma::wgmma_wait_group"
+    ));
+    assert!(is_generated_intrinsic_path(
+        "cuda_device::wgmma::__wgmma_wait_group"
+    ));
+    assert!(!is_raw_generated_intrinsic_path(
+        "cuda_device::wgmma::__wgmma_wait_group"
+    ));
+    assert_eq!(
+        generated_intrinsic_marker("cuda_device::wgmma::__wgmma_wait_group"),
+        Some("v1:i0319")
+    );
+    assert!(!is_generated_intrinsic_path(
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0319"
+    ));
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs
new file mode 100644
index 0000000000..874406d302
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs
@@ -0,0 +1,4720 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `tma` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0340"
+        | "cuda_device::tma::cp_async_bulk_commit_group" => {
+            Ok(Some(super::super::tma::emit_tma_commit_group(
+                ctx, args, target, block_ptr, prev_op, block_map, loc, "v1:i0340",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0888"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor1dL2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0888");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_1d_l2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0917"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_1d_l2_cache_hint" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor1dL2CacheHintOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0917");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_1d_l2_cache_hint call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0889"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor2dL2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0889");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_2d_l2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0918"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_2d_l2_cache_hint" => {
+            require_arity(name, args.len(), 4, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor2dL2CacheHintOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0918");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_2d_l2_cache_hint call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0890"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2" => {
+            require_arity(name, args.len(), 4, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor3dL2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0890");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_3d_l2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0919"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_3d_l2_cache_hint" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor3dL2CacheHintOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0919");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_3d_l2_cache_hint call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0891"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor4dL2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0891");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_4d_l2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0920"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_4d_l2_cache_hint" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor4dL2CacheHintOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0920");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_4d_l2_cache_hint call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0892"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor5dL2Op::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0892");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_5d_l2 call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0921"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_5d_l2_cache_hint" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkPrefetchTensor5dL2CacheHintOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0921");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_5d_l2_cache_hint call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0893"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(ctx, dialect_nvvm::ops::CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op::get_concrete_op_info(), vec![], operands, vec![], 0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0893");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_prefetch_tensor_gather4_2d_l2 call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0922"
+        | "cuda_device::tma::cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(ctx, dialect_nvvm::ops::CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp::get_concrete_op_info(), vec![], operands, vec![], 0);
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0922");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(loc, TranslationErr::unsupported("cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint call without target block".to_owned()))
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0328"
+        | "cuda_device::tma::cp_async_bulk_tensor_1d_g2s" => {
+            Ok(Some(super::super::tma::emit_tma_g2s(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 1,
+                "v1:i0328",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0335"
+        | "cuda_device::tma::cp_async_bulk_tensor_1d_s2g" => {
+            Ok(Some(super::super::tma::emit_tma_s2g(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 1,
+                "v1:i0335",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0329"
+        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s" => {
+            Ok(Some(super::super::tma::emit_tma_g2s(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 2,
+                "v1:i0329",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0330"
+        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast" => {
+            Ok(Some(super::super::tma::emit_tma_g2s_multicast(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, "v1:i0330",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0331"
+        | "cuda_device::tma::cp_async_bulk_tensor_2d_g2s_multicast_cg2" => {
+            Ok(Some(super::super::tma::emit_tma_g2s_multicast_cg2(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, "v1:i0331",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0336"
+        | "cuda_device::tma::cp_async_bulk_tensor_2d_s2g" => {
+            Ok(Some(super::super::tma::emit_tma_s2g(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 2,
+                "v1:i0336",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0332"
+        | "cuda_device::tma::cp_async_bulk_tensor_3d_g2s" => {
+            Ok(Some(super::super::tma::emit_tma_g2s(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 3,
+                "v1:i0332",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0337"
+        | "cuda_device::tma::cp_async_bulk_tensor_3d_s2g" => {
+            Ok(Some(super::super::tma::emit_tma_s2g(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 3,
+                "v1:i0337",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0333"
+        | "cuda_device::tma::cp_async_bulk_tensor_4d_g2s" => {
+            Ok(Some(super::super::tma::emit_tma_g2s(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 4,
+                "v1:i0333",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0338"
+        | "cuda_device::tma::cp_async_bulk_tensor_4d_s2g" => {
+            Ok(Some(super::super::tma::emit_tma_s2g(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 4,
+                "v1:i0338",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0334"
+        | "cuda_device::tma::cp_async_bulk_tensor_5d_g2s" => {
+            Ok(Some(super::super::tma::emit_tma_g2s(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 5,
+                "v1:i0334",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0339"
+        | "cuda_device::tma::cp_async_bulk_tensor_5d_s2g" => {
+            Ok(Some(super::super::tma::emit_tma_s2g(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, 5,
+                "v1:i0339",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0928"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddIm2col3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0928");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_add_im2col_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0929"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddIm2col4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0929");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_add_im2col_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0930"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_im2col_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddIm2col5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0930");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_add_im2col_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0923"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_1d" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile1dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0923");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_add_tile_1d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0924"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_2d" => {
+            require_arity(name, args.len(), 4, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile2dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0924");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_add_tile_2d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0925"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0925");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_add_tile_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0926"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0926");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_add_tile_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0927"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_add_tile_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAddTile5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0927");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_add_tile_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0936"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndIm2col3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0936");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_and_im2col_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0937"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndIm2col4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0937");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_and_im2col_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0938"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_im2col_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndIm2col5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0938");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_and_im2col_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0931"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_1d" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndTile1dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0931");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_and_tile_1d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0932"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_2d" => {
+            require_arity(name, args.len(), 4, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndTile2dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0932");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_and_tile_2d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0933"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndTile3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0933");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_and_tile_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0934"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndTile4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0934");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_and_tile_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0935"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_and_tile_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceAndTile5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0935");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_and_tile_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0944"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecIm2col3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0944");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_dec_im2col_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0945"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecIm2col4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0945");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_dec_im2col_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0946"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_im2col_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecIm2col5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0946");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_dec_im2col_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0939"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_1d" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecTile1dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0939");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_dec_tile_1d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0940"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_2d" => {
+            require_arity(name, args.len(), 4, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecTile2dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0940");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_dec_tile_2d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0941"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecTile3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0941");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_dec_tile_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0942"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecTile4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0942");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_dec_tile_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0943"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_dec_tile_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceDecTile5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0943");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_dec_tile_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0952"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncIm2col3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0952");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_inc_im2col_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0953"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncIm2col4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0953");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_inc_im2col_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0954"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_im2col_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncIm2col5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0954");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_inc_im2col_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0947"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_1d" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncTile1dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0947");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_inc_tile_1d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0948"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_2d" => {
+            require_arity(name, args.len(), 4, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncTile2dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0948");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_inc_tile_2d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0949"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncTile3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0949");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_inc_tile_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0950"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncTile4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0950");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_inc_tile_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0951"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_inc_tile_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceIncTile5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0951");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_inc_tile_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0960"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxIm2col3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0960");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_max_im2col_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0961"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxIm2col4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0961");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_max_im2col_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0962"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_im2col_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxIm2col5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0962");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_max_im2col_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0955"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_1d" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxTile1dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0955");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_max_tile_1d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0956"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_2d" => {
+            require_arity(name, args.len(), 4, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxTile2dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0956");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_max_tile_2d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0957"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxTile3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0957");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_max_tile_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0958"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxTile4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0958");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_max_tile_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0959"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_max_tile_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMaxTile5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0959");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_max_tile_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0968"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinIm2col3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0968");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_min_im2col_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0969"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinIm2col4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0969");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_min_im2col_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0970"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_im2col_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinIm2col5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0970");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_min_im2col_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0963"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_1d" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinTile1dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0963");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_min_tile_1d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0964"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_2d" => {
+            require_arity(name, args.len(), 4, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinTile2dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0964");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_min_tile_2d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0965"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinTile3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0965");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_min_tile_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0966"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinTile4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0966");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_min_tile_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0967"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_min_tile_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceMinTile5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0967");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_min_tile_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0976"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrIm2col3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0976");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_or_im2col_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0977"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrIm2col4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0977");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_or_im2col_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0978"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_im2col_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrIm2col5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0978");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_or_im2col_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0971"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_1d" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrTile1dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0971");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_or_tile_1d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0972"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_2d" => {
+            require_arity(name, args.len(), 4, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrTile2dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0972");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_or_tile_2d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0973"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrTile3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0973");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_or_tile_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0974"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrTile4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0974");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_or_tile_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0975"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_or_tile_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceOrTile5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0975");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_or_tile_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0984"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorIm2col3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0984");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_xor_im2col_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0985"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorIm2col4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0985");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_xor_im2col_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0986"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_im2col_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorIm2col5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0986");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_xor_im2col_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0979"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_1d" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorTile1dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0979");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_xor_tile_1d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0980"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_2d" => {
+            require_arity(name, args.len(), 4, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorTile2dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0980");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_xor_tile_2d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0981"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_3d" => {
+            require_arity(name, args.len(), 5, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorTile3dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0981");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_xor_tile_3d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0982"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_4d" => {
+            require_arity(name, args.len(), 6, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorTile4dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0982");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_xor_tile_4d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0983"
+        | "cuda_device::tma::cp_async_bulk_tensor_reduce_xor_tile_5d" => {
+            require_arity(name, args.len(), 7, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::CpAsyncBulkTensorReduceXorTile5dOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0983");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "cp_async_bulk_tensor_reduce_xor_tile_5d call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0341"
+        | "cuda_device::tma::cp_async_bulk_wait_group" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            if !matches!(args.first(), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "TMA wait-group count must be a compile-time constant".to_owned()
+                    )
+                );
+            }
+            Ok(Some(super::super::tma::emit_tma_wait_group(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, false,
+                "v1:i0341",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0342"
+        | "cuda_device::tma::cp_async_bulk_wait_group_read" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            if !matches!(args.first(), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "TMA wait-group count must be a compile-time constant".to_owned()
+                    )
+                );
+            }
+            Ok(Some(super::super::tma::emit_tma_wait_group(
+                ctx, body, args, target, block_ptr, prev_op, value_map, block_map, loc, true,
+                "v1:i0342",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0905"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cluster" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::FenceProxyTensorMapGenericAcquireClusterOp::get_concrete_op_info(
+                ),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0905");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "fence_proxy_tensormap_generic_acquire_cluster call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0906"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_cta" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::FenceProxyTensorMapGenericAcquireCtaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0906");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "fence_proxy_tensormap_generic_acquire_cta call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0907"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_gpu" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::FenceProxyTensorMapGenericAcquireGpuOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0907");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "fence_proxy_tensormap_generic_acquire_gpu call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0908"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_acquire_system" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::FenceProxyTensorMapGenericAcquireSystemOp::get_concrete_op_info(
+                ),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0908");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "fence_proxy_tensormap_generic_acquire_system call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0909"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_release_cluster" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::FenceProxyTensorMapGenericReleaseClusterOp::get_concrete_op_info(
+                ),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0909");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "fence_proxy_tensormap_generic_release_cluster call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0910"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_release_cta" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::FenceProxyTensorMapGenericReleaseCtaOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0910");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "fence_proxy_tensormap_generic_release_cta call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0911"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_release_gpu" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::FenceProxyTensorMapGenericReleaseGpuOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0911");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "fence_proxy_tensormap_generic_release_gpu call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0912"
+        | "cuda_device::tma::fence_proxy_tensormap_generic_release_system" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::FenceProxyTensorMapGenericReleaseSystemOp::get_concrete_op_info(
+                ),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0912");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "fence_proxy_tensormap_generic_release_system call without target block"
+                            .to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0887"
+        | "cuda_device::tma::prefetch_tma_descriptor" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::PrefetchTensorMapOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0887");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "prefetch_tma_descriptor call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0894"
+        | "cuda_device::tma::tensormap_replace_box_dim" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensor-map replacement selector must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapBoxDimOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0894");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_box_dim call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0895"
+        | "cuda_device::tma::tensormap_replace_element_stride" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensor-map replacement selector must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapElementStrideOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0895");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_element_stride call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0896"
+        | "cuda_device::tma::tensormap_replace_element_type" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensor-map replacement selector must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapElementTypeOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0896");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_element_type call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0897"
+        | "cuda_device::tma::tensormap_replace_fill_mode" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensor-map replacement selector must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapFillModeOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0897");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_fill_mode call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0898"
+        | "cuda_device::tma::tensormap_replace_global_address" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapGlobalAddressOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0898");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_global_address call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0899"
+        | "cuda_device::tma::tensormap_replace_global_dim" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensor-map replacement selector must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapGlobalDimOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0899");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_global_dim call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0900"
+        | "cuda_device::tma::tensormap_replace_global_stride" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensor-map replacement selector must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapGlobalStrideOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0900");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_global_stride call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0901"
+        | "cuda_device::tma::tensormap_replace_interleave_layout" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensor-map replacement selector must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapInterleaveLayoutOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0901");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_interleave_layout call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0902"
+        | "cuda_device::tma::tensormap_replace_rank" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapRankOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0902");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_rank call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0903"
+        | "cuda_device::tma::tensormap_replace_swizzle_atomicity" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensor-map replacement selector must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapSwizzleAtomicityOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0903");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_swizzle_atomicity call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0904"
+        | "cuda_device::tma::tensormap_replace_swizzle_mode" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            if !matches!(args.get(1), Some(mir::Operand::Constant(_))) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensor-map replacement selector must be a compile-time constant"
+                            .to_owned()
+                    )
+                );
+            }
+            let mut last_op = prev_op;
+            let mut operands = Vec::with_capacity(args.len());
+            for arg in args {
+                let (value, translated) = rvalue::translate_operand(
+                    ctx,
+                    body,
+                    arg,
+                    value_map,
+                    block_ptr,
+                    last_op,
+                    loc.clone(),
+                )?;
+                last_op = translated;
+                operands.push(value);
+            }
+            let intrinsic = Operation::new(
+                ctx,
+                dialect_nvvm::ops::ReplaceTensorMapSwizzleModeOp::get_concrete_op_info(),
+                vec![],
+                operands,
+                vec![],
+                0,
+            );
+            intrinsic.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, intrinsic, "v1:i0904");
+            helpers::insert_op(ctx, intrinsic, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    intrinsic,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "tensormap_replace_swizzle_mode call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs
new file mode 100644
index 0000000000..94e9aad2dd
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs
@@ -0,0 +1,192 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `vote` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{VoteSyncAllOp, VoteSyncAnyOp, VoteSyncBallotOp, VoteSyncUniOp};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0040" | "cuda_device::warp::all_sync" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (predicate, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let vote = VoteSyncAllOp::build(ctx, member_mask, predicate);
+            vote.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, vote, "v1:i0040");
+            helpers::insert_op(ctx, vote, block_ptr, last_op);
+            let result = vote.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                vote,
+                value_map,
+                block_map,
+                loc,
+                "all_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0041" | "cuda_device::warp::any_sync" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (predicate, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let vote = VoteSyncAnyOp::build(ctx, member_mask, predicate);
+            vote.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, vote, "v1:i0041");
+            helpers::insert_op(ctx, vote, block_ptr, last_op);
+            let result = vote.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                vote,
+                value_map,
+                block_map,
+                loc,
+                "any_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0042"
+        | "cuda_device::warp::ballot_sync" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (predicate, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let vote = VoteSyncBallotOp::build(ctx, member_mask, predicate);
+            vote.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, vote, "v1:i0042");
+            helpers::insert_op(ctx, vote, block_ptr, last_op);
+            let result = vote.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                vote,
+                value_map,
+                block_map,
+                loc,
+                "ballot_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0043" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (predicate, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let vote = VoteSyncUniOp::build(ctx, member_mask, predicate);
+            vote.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, vote, "v1:i0043");
+            helpers::insert_op(ctx, vote, block_ptr, last_op);
+            let result = vote.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                vote,
+                value_map,
+                block_map,
+                loc,
+                "uni_sync call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs
new file mode 100644
index 0000000000..75388fe03d
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs
@@ -0,0 +1,71 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `warp_barrier` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::BarWarpSyncOp;
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0049"
+        | "cuda_device::warp::sync_mask" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let barrier = BarWarpSyncOp::build(ctx, member_mask);
+            barrier.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, barrier, "v1:i0049");
+            helpers::insert_op(ctx, barrier, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    barrier,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported("sync_mask call without target block".to_owned())
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs
new file mode 100644
index 0000000000..51b80b686a
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs
@@ -0,0 +1,197 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `warp_match` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    MatchAllSyncI32Op, MatchAllSyncI64Op, MatchAnySyncI32Op, MatchAnySyncI64Op,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048"
+        | "cuda_device::warp::match_all_i64_sync" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let warp_match = MatchAllSyncI64Op::build(ctx, member_mask, value);
+            warp_match.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, warp_match, "v1:i0048");
+            helpers::insert_op(ctx, warp_match, block_ptr, last_op);
+            let result = warp_match.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                warp_match,
+                value_map,
+                block_map,
+                loc,
+                "match_all_i64_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0047"
+        | "cuda_device::warp::match_all_sync" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let warp_match = MatchAllSyncI32Op::build(ctx, member_mask, value);
+            warp_match.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, warp_match, "v1:i0047");
+            helpers::insert_op(ctx, warp_match, block_ptr, last_op);
+            let result = warp_match.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                warp_match,
+                value_map,
+                block_map,
+                loc,
+                "match_all_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0046"
+        | "cuda_device::warp::match_any_i64_sync" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let warp_match = MatchAnySyncI64Op::build(ctx, member_mask, value);
+            warp_match.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, warp_match, "v1:i0046");
+            helpers::insert_op(ctx, warp_match, block_ptr, last_op);
+            let result = warp_match.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                warp_match,
+                value_map,
+                block_map,
+                loc,
+                "match_any_i64_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0045"
+        | "cuda_device::warp::match_any_sync" => {
+            require_arity(name, args.len(), 2, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let warp_match = MatchAnySyncI32Op::build(ctx, member_mask, value);
+            warp_match.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, warp_match, "v1:i0045");
+            helpers::insert_op(ctx, warp_match, block_ptr, last_op);
+            let result = warp_match.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                warp_match,
+                value_map,
+                block_map,
+                loc,
+                "match_any_sync call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs
new file mode 100644
index 0000000000..ac247d8ce0
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs
@@ -0,0 +1,619 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `warp_shuffle` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::TranslationResult;
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_nvvm::ops::{
+    ShflSyncBflyF32Op, ShflSyncBflyI32Op, ShflSyncBflyI64Op, ShflSyncDownF32Op, ShflSyncDownI32Op,
+    ShflSyncDownI64Op, ShflSyncIdxF32Op, ShflSyncIdxI32Op, ShflSyncIdxI64Op, ShflSyncUpF32Op,
+    ShflSyncUpI32Op, ShflSyncUpI64Op,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0056"
+        | "cuda_device::warp::shuffle_down_f32_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncDownF32Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0056");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_down_f32_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0052"
+        | "cuda_device::warp::shuffle_down_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncDownI32Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0052");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_down_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0060"
+        | "cuda_device::warp::shuffle_down_u64_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncDownI64Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0060");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_down_u64_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0054"
+        | "cuda_device::warp::shuffle_f32_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncIdxF32Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0054");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_f32_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0050"
+        | "cuda_device::warp::shuffle_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncIdxI32Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0050");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0058"
+        | "cuda_device::warp::shuffle_u64_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncIdxI64Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0058");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_u64_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0057"
+        | "cuda_device::warp::shuffle_up_f32_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncUpF32Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0057");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_up_f32_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0053"
+        | "cuda_device::warp::shuffle_up_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncUpI32Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0053");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_up_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0061"
+        | "cuda_device::warp::shuffle_up_u64_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncUpI64Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0061");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_up_u64_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0055"
+        | "cuda_device::warp::shuffle_xor_f32_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncBflyF32Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0055");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_xor_f32_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0051"
+        | "cuda_device::warp::shuffle_xor_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncBflyI32Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0051");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_xor_sync call without target block",
+            )?))
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0059"
+        | "cuda_device::warp::shuffle_xor_u64_sync" => {
+            require_arity(name, args.len(), 3, &loc)?;
+            let (member_mask, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            let (value, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[1],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let (lane_or_delta, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[2],
+                value_map,
+                block_ptr,
+                last_op,
+                loc.clone(),
+            )?;
+            let shuffle = ShflSyncBflyI64Op::build(ctx, member_mask, value, lane_or_delta);
+            shuffle.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, shuffle, "v1:i0059");
+            helpers::insert_op(ctx, shuffle, block_ptr, last_op);
+            let result = shuffle.deref(ctx).get_result(0);
+            Ok(Some(helpers::emit_store_result_and_goto(
+                ctx,
+                destination,
+                result,
+                target,
+                block_ptr,
+                shuffle,
+                value_map,
+                block_map,
+                loc,
+                "shuffle_xor_u64_sync call without target block",
+            )?))
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs
new file mode 100644
index 0000000000..cf8deeaddc
--- /dev/null
+++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs
@@ -0,0 +1,142 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated raw/compatibility dispatch arms: `wgmma_control` intrinsics.
+
+use super::helpers::require_arity;
+use crate::error::{TranslationErr, TranslationResult};
+use crate::translator::{rvalue, terminator::helpers, values::ValueMap};
+use dialect_mir::ops::MirConstantOp;
+use dialect_nvvm::ops::{
+    WgmmaCommitGroupSyncAlignedOp, WgmmaFenceSyncAlignedOp, WgmmaWaitGroupSyncAlignedOp,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::context::{Context, Ptr};
+use pliron::input_err;
+use pliron::location::{Located, Location};
+use pliron::operation::Operation;
+use rustc_public::mir;
+
+#[allow(clippy::too_many_arguments)]
+pub(super) fn try_dispatch(
+    ctx: &mut Context,
+    body: &mir::Body,
+    name: &str,
+    args: &[mir::Operand],
+    _destination: &mir::Place,
+    target: &Option<usize>,
+    block_ptr: Ptr<BasicBlock>,
+    prev_op: Option<Ptr<Operation>>,
+    value_map: &mut ValueMap,
+    block_map: &[Ptr<BasicBlock>],
+    loc: Location,
+) -> TranslationResult<Option<Ptr<Operation>>> {
+    match name {
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0318"
+        | "cuda_device::wgmma::wgmma_commit_group" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let control = WgmmaCommitGroupSyncAlignedOp::build(ctx);
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0318");
+            helpers::insert_op(ctx, control, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "wgmma_commit_group call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0317"
+        | "cuda_device::wgmma::wgmma_fence" => {
+            require_arity(name, args.len(), 0, &loc)?;
+            let control = WgmmaFenceSyncAlignedOp::build(ctx);
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0317");
+            helpers::insert_op(ctx, control, block_ptr, prev_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported("wgmma_fence call without target block".to_owned())
+                )
+            }
+        }
+        "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0319"
+        | "cuda_device::wgmma::__wgmma_wait_group" => {
+            require_arity(name, args.len(), 1, &loc)?;
+            if !matches!(&args[0], mir::Operand::Constant(_)) {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "wgmma_wait_group requires a compile-time constant".to_owned()
+                    )
+                );
+            }
+            let (max_pending, last_op) = rvalue::translate_operand(
+                ctx,
+                body,
+                &args[0],
+                value_map,
+                block_ptr,
+                prev_op,
+                loc.clone(),
+            )?;
+            if max_pending
+                .defining_op()
+                .and_then(|op| Operation::get_op::<MirConstantOp>(op, ctx))
+                .is_none()
+            {
+                return input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "wgmma_wait_group requires a compile-time constant".to_owned()
+                    )
+                );
+            }
+            let control = WgmmaWaitGroupSyncAlignedOp::build(ctx, max_pending);
+            control.deref_mut(ctx).set_loc(loc.clone());
+            helpers::set_generated_intrinsic_marker(ctx, control, "v1:i0319");
+            helpers::insert_op(ctx, control, block_ptr, last_op);
+            if let Some(target_idx) = target {
+                Ok(Some(helpers::emit_goto(
+                    ctx,
+                    *target_idx,
+                    control,
+                    block_map,
+                    loc,
+                )))
+            } else {
+                input_err!(
+                    loc,
+                    TranslationErr::unsupported(
+                        "wgmma_wait_group call without target block".to_owned()
+                    )
+                )
+            }
+        }
+        _ => Ok(None),
+    }
+}
diff --git a/crates/mir-lower/README.md b/crates/mir-lower/README.md
index a48b8e8736..610efa7c9e 100644
--- a/crates/mir-lower/README.md
+++ b/crates/mir-lower/README.md
@@ -84,7 +84,7 @@ For each `MirFuncOp`, `convert_func` (in `lowering.rs`):
 | `aggregate`    | Struct/tuple/array/enum extract, insert, construct, field/element addr                                         |
 | `call`         | `mir.call` (function calls with arg flattening)                                                                |
 
-### Type Converter (`convert/types.rs`)
+### Type Converter (`convert/types/`)
 
 | `dialect-mir` Type   | LLVM dialect Type                                   |
 |----------------------|-----------------------------------------------------|
diff --git a/crates/mir-lower/src/convert/generated_intrinsics.rs b/crates/mir-lower/src/convert/generated_intrinsics.rs
deleted file mode 100644
index 80cf3642a9..0000000000
--- a/crates/mir-lower/src/convert/generated_intrinsics.rs
+++ /dev/null
@@ -1,17861 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
-// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
-// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
-
-//! Generated conversion interfaces for admitted CUDA intrinsic families.
-
-use crate::conversion_interface::MirToLlvmConversion;
-use crate::convert::intrinsics::{
-    atomic::convert_packed_atom_add,
-    basic::convert_sreg_read_inline,
-    clc::{convert_generated_clc_query, convert_generated_clc_try_cancel},
-    common::{
-        call_intrinsic, cast_to_shared_addrspace, create_i32_const, inline_asm_convergent,
-        inline_asm_sideeffect, trunc_to_i1,
-    },
-    cp_async::{
-        convert_generated_cp_async_control, convert_generated_cp_async_copy,
-        convert_generated_cp_async_mbarrier,
-    },
-    dotprod::convert_generated_dot_product,
-    execution_control::{convert_counted_barrier, convert_grid_dependency, convert_setmaxnreg},
-    extended_minmax::{MinMaxCarrier, convert_generated_extended_minmax},
-    integer_minmax::convert_generated_integer_minmax,
-    ldmatrix::convert_generated_ldmatrix,
-    mbarrier::{convert_arrive, convert_init, convert_inval, convert_test_wait},
-    packed::{
-        convert_generated_packed_alu, convert_generated_packed_f32x2,
-        convert_generated_packed_unary,
-    },
-    prmt::convert_generated_prmt,
-    scalar_arithmetic::convert_generated_scalar_arithmetic,
-    scalar_conversion::convert_generated_scalar_conversion,
-    scalar_math::convert_generated_scalar_math,
-    tma::{
-        PrefetchTileConfig, ReduceConfig, convert_control, convert_g2s, convert_g2s_multicast_cg2,
-        convert_prefetch_tensormap, convert_prefetch_tile, convert_reduce_s2g, convert_s2g,
-        convert_tensormap_fence, convert_tensormap_replace,
-    },
-    warp::{
-        convert_active_mask, convert_bar_warp_sync, convert_elect_sync_inline,
-        convert_elect_sync_typed, convert_match_all, convert_match_any, convert_redux,
-        convert_shuffle_f32, convert_shuffle_i32, convert_shuffle_i64, convert_vote,
-    },
-    wmma::{GeneratedMmaResultType, convert_generated_register_mma, convert_generated_sparse_mma},
-};
-use crate::{IntrinsicBackend, context};
-use dialect_nvvm::ops::{
-    AbsBf16x2Op, AbsF16x2Op, ActiveMaskOp, AddBf16x2Op, AddF16x2Op, AddF32x2Op, AddFtzF32x2Op,
-    BarWarpSyncOp, Barrier0Op, BarrierCtaArriveAlignedCountOp, BarrierCtaArriveCountOp,
-    BarrierCtaSyncAlignedCountOp, BarrierCtaSyncCountOp, BreakpointOp, ClcQueryGetFirstCtaidXOp,
-    ClcQueryGetFirstCtaidYOp, ClcQueryGetFirstCtaidZOp, ClcQueryIsCanceledOp,
-    ClcTryCancelMulticastOp, ClcTryCancelOp, ClusterBarrierModeAttr, ClusterBarrierOp,
-    ClusterSyncOp, CpAsyncBulkCommitGroupOp, CpAsyncBulkPrefetchTensor1dL2CacheHintOp,
-    CpAsyncBulkPrefetchTensor1dL2Op, CpAsyncBulkPrefetchTensor2dL2CacheHintOp,
-    CpAsyncBulkPrefetchTensor2dL2Op, CpAsyncBulkPrefetchTensor3dL2CacheHintOp,
-    CpAsyncBulkPrefetchTensor3dL2Op, CpAsyncBulkPrefetchTensor4dL2CacheHintOp,
-    CpAsyncBulkPrefetchTensor4dL2Op, CpAsyncBulkPrefetchTensor5dL2CacheHintOp,
-    CpAsyncBulkPrefetchTensor5dL2Op, CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp,
-    CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op, CpAsyncBulkTensorG2sTile1dOp,
-    CpAsyncBulkTensorG2sTile2dMulticastCg2Op, CpAsyncBulkTensorG2sTile2dMulticastOp,
-    CpAsyncBulkTensorG2sTile2dOp, CpAsyncBulkTensorG2sTile3dOp, CpAsyncBulkTensorG2sTile4dOp,
-    CpAsyncBulkTensorG2sTile5dOp, CpAsyncBulkTensorReduceAddIm2col3dOp,
-    CpAsyncBulkTensorReduceAddIm2col4dOp, CpAsyncBulkTensorReduceAddIm2col5dOp,
-    CpAsyncBulkTensorReduceAddTile1dOp, CpAsyncBulkTensorReduceAddTile2dOp,
-    CpAsyncBulkTensorReduceAddTile3dOp, CpAsyncBulkTensorReduceAddTile4dOp,
-    CpAsyncBulkTensorReduceAddTile5dOp, CpAsyncBulkTensorReduceAndIm2col3dOp,
-    CpAsyncBulkTensorReduceAndIm2col4dOp, CpAsyncBulkTensorReduceAndIm2col5dOp,
-    CpAsyncBulkTensorReduceAndTile1dOp, CpAsyncBulkTensorReduceAndTile2dOp,
-    CpAsyncBulkTensorReduceAndTile3dOp, CpAsyncBulkTensorReduceAndTile4dOp,
-    CpAsyncBulkTensorReduceAndTile5dOp, CpAsyncBulkTensorReduceDecIm2col3dOp,
-    CpAsyncBulkTensorReduceDecIm2col4dOp, CpAsyncBulkTensorReduceDecIm2col5dOp,
-    CpAsyncBulkTensorReduceDecTile1dOp, CpAsyncBulkTensorReduceDecTile2dOp,
-    CpAsyncBulkTensorReduceDecTile3dOp, CpAsyncBulkTensorReduceDecTile4dOp,
-    CpAsyncBulkTensorReduceDecTile5dOp, CpAsyncBulkTensorReduceIncIm2col3dOp,
-    CpAsyncBulkTensorReduceIncIm2col4dOp, CpAsyncBulkTensorReduceIncIm2col5dOp,
-    CpAsyncBulkTensorReduceIncTile1dOp, CpAsyncBulkTensorReduceIncTile2dOp,
-    CpAsyncBulkTensorReduceIncTile3dOp, CpAsyncBulkTensorReduceIncTile4dOp,
-    CpAsyncBulkTensorReduceIncTile5dOp, CpAsyncBulkTensorReduceMaxIm2col3dOp,
-    CpAsyncBulkTensorReduceMaxIm2col4dOp, CpAsyncBulkTensorReduceMaxIm2col5dOp,
-    CpAsyncBulkTensorReduceMaxTile1dOp, CpAsyncBulkTensorReduceMaxTile2dOp,
-    CpAsyncBulkTensorReduceMaxTile3dOp, CpAsyncBulkTensorReduceMaxTile4dOp,
-    CpAsyncBulkTensorReduceMaxTile5dOp, CpAsyncBulkTensorReduceMinIm2col3dOp,
-    CpAsyncBulkTensorReduceMinIm2col4dOp, CpAsyncBulkTensorReduceMinIm2col5dOp,
-    CpAsyncBulkTensorReduceMinTile1dOp, CpAsyncBulkTensorReduceMinTile2dOp,
-    CpAsyncBulkTensorReduceMinTile3dOp, CpAsyncBulkTensorReduceMinTile4dOp,
-    CpAsyncBulkTensorReduceMinTile5dOp, CpAsyncBulkTensorReduceOrIm2col3dOp,
-    CpAsyncBulkTensorReduceOrIm2col4dOp, CpAsyncBulkTensorReduceOrIm2col5dOp,
-    CpAsyncBulkTensorReduceOrTile1dOp, CpAsyncBulkTensorReduceOrTile2dOp,
-    CpAsyncBulkTensorReduceOrTile3dOp, CpAsyncBulkTensorReduceOrTile4dOp,
-    CpAsyncBulkTensorReduceOrTile5dOp, CpAsyncBulkTensorReduceXorIm2col3dOp,
-    CpAsyncBulkTensorReduceXorIm2col4dOp, CpAsyncBulkTensorReduceXorIm2col5dOp,
-    CpAsyncBulkTensorReduceXorTile1dOp, CpAsyncBulkTensorReduceXorTile2dOp,
-    CpAsyncBulkTensorReduceXorTile3dOp, CpAsyncBulkTensorReduceXorTile4dOp,
-    CpAsyncBulkTensorReduceXorTile5dOp, CpAsyncBulkTensorS2gTile1dOp, CpAsyncBulkTensorS2gTile2dOp,
-    CpAsyncBulkTensorS2gTile3dOp, CpAsyncBulkTensorS2gTile4dOp, CpAsyncBulkTensorS2gTile5dOp,
-    CpAsyncBulkWaitGroupOp, CpAsyncBulkWaitGroupReadOp, CpAsyncCa4Op, CpAsyncCa8Op, CpAsyncCa16Op,
-    CpAsyncCaZfill4Op, CpAsyncCaZfill8Op, CpAsyncCaZfill16Op, CpAsyncCg16Op, CpAsyncCgZfill16Op,
-    CpAsyncCommitGroupOp, CpAsyncMbarrierArriveNoIncOp, CpAsyncMbarrierArriveNoIncSharedOp,
-    CpAsyncMbarrierArriveOp, CpAsyncMbarrierArriveSharedOp, CpAsyncWaitAllOp, CpAsyncWaitGroupOp,
-    CvtF16x2F32Op, CvtF32x2Bf16x2Op, CvtRnF16x2E4m3x2Op, CvtRnF16x2E5m2x2Op, CvtRnReluBf16x2F32Op,
-    CvtRnReluF16x2E4m3x2Op, CvtRnReluF16x2E5m2x2Op, CvtRnReluF16x2F32Op,
-    CvtRnSatfiniteE4m3x2F16x2Op, CvtRnSatfiniteE4m3x2F32Op, CvtRnSatfiniteE5m2x2F16x2Op,
-    CvtRnSatfiniteE5m2x2F32Op, CvtRnSatfiniteReluE4m3x2F16x2Op, CvtRnSatfiniteReluE4m3x2F32Op,
-    CvtRnSatfiniteReluE5m2x2F16x2Op, CvtRnSatfiniteReluE5m2x2F32Op, CvtRzBf16x2F32Op,
-    CvtRzF16x2F32Op, Dp2aS32Op, Dp2aU32Op, Dp4aS32Op, Dp4aU32Op, DsmemReadU32Op, ElectSyncOp,
-    ExtendedMinMaxFormatAttr, ExtendedMinMaxNanAttr, ExtendedMinMaxOp, ExtendedMinMaxOperationAttr,
-    ExtendedMinMaxSubnormalAttr, ExtendedMinMaxXorSignAbsAttr, FenceMbarrierInitReleaseClusterOp,
-    FenceProxyAsyncGenericAcquireSharedClusterClusterOp,
-    FenceProxyAsyncGenericReleaseSharedCtaClusterOp, FenceProxyAsyncSharedCtaOp,
-    FenceProxyTensorMapGenericAcquireClusterOp, FenceProxyTensorMapGenericAcquireCtaOp,
-    FenceProxyTensorMapGenericAcquireGpuOp, FenceProxyTensorMapGenericAcquireSystemOp,
-    FenceProxyTensorMapGenericReleaseClusterOp, FenceProxyTensorMapGenericReleaseCtaOp,
-    FenceProxyTensorMapGenericReleaseGpuOp, FenceProxyTensorMapGenericReleaseSystemOp, FmaBf16x2Op,
-    FmaF16x2Op, FmaF32x2Op, FmaFtzF16x2Op, FmaFtzF32x2Op, FmaFtzReluF16x2Op, FmaFtzSatF16x2Op,
-    FmaReluBf16x2Op, FmaReluF16x2Op, FmaSatF16x2Op, GridDependencyLaunchDependentsOp,
-    GridDependencyWaitOp, LdmatrixElementAttr, LdmatrixLayoutAttr, LdmatrixMultiplicityAttr,
-    LdmatrixOp, LdmatrixShapeAttr, LdmatrixStateSpaceAttr, LdmatrixX1Op, LdmatrixX1TransOp,
-    LdmatrixX2Op, LdmatrixX2TransOp, LdmatrixX4Op, LdmatrixX4TransOp, MapaSharedClusterOp,
-    MatchAllSyncI32Op, MatchAllSyncI64Op, MatchAnySyncI32Op, MatchAnySyncI64Op, MaxBf16x2Op,
-    MaxF16x2Op, MaxReluS16x2Op, MaxReluS32Op, MaxS16x2Op, MaxU16x2Op, MbarrierArriveClusterOp,
-    MbarrierArriveExpectTxClusterOp, MbarrierArriveExpectTxSharedOp, MbarrierArriveSharedOp,
-    MbarrierInitSharedOp, MbarrierInvalSharedOp, MbarrierTestWaitSharedOp,
-    MbarrierTryWaitParityClusterOp, MbarrierTryWaitParitySharedOp, MbarrierTryWaitSharedOp,
-    MinBf16x2Op, MinF16x2Op, MinReluS16x2Op, MinReluS32Op, MinS16x2Op, MinU16x2Op, MmaM8N8K4F64Op,
-    MmaM16N8K8F32Tf32Op, MmaM16N8K16F32Bf16Op, MmaM16N8K16F32F16Op, MmaM16N8K32S32S8Op,
-    MovmatrixTransB16Op, MulBf16x2Op, MulF16x2Op, MulF32x2Op, MulFtzF32x2Op, NanosleepOp,
-    NegBf16x2Op, NegF16x2Op, NvvmAtomAddBf16x2Op, NvvmAtomAddF16x2Op, PackedAtomicAddOp,
-    PackedAtomicAtomicityAttr, PackedAtomicFormatAttr, PackedAtomicOrderingAttr,
-    PackedAtomicRoundingAttr, PackedAtomicScopeAttr, PackedAtomicStateSpaceAttr,
-    PackedAtomicSubnormalAttr, PmEventOp, PrefetchTensorMapOp, PrmtModeAttr, PrmtOp,
-    ReadPtxSregClock64Op, ReadPtxSregClockOp, ReadPtxSregClusterCtaidXOp,
-    ReadPtxSregClusterCtaidYOp, ReadPtxSregClusterCtaidZOp, ReadPtxSregClusterCtarankOp,
-    ReadPtxSregClusterIdXOp, ReadPtxSregClusterIdYOp, ReadPtxSregClusterIdZOp,
-    ReadPtxSregClusterNctaidXOp, ReadPtxSregClusterNctaidYOp, ReadPtxSregClusterNctaidZOp,
-    ReadPtxSregClusterNctarankOp, ReadPtxSregCtaidXOp, ReadPtxSregCtaidYOp, ReadPtxSregCtaidZOp,
-    ReadPtxSregDynamicSmemSizeOp, ReadPtxSregEnvReg1Op, ReadPtxSregEnvReg2Op,
-    ReadPtxSregGlobaltimerOp, ReadPtxSregGridIdOp, ReadPtxSregLaneIdOp, ReadPtxSregLanemaskEqOp,
-    ReadPtxSregLanemaskGeOp, ReadPtxSregLanemaskGtOp, ReadPtxSregLanemaskLeOp,
-    ReadPtxSregLanemaskLtOp, ReadPtxSregNclusterIdXOp, ReadPtxSregNclusterIdYOp,
-    ReadPtxSregNclusterIdZOp, ReadPtxSregNctaidXOp, ReadPtxSregNctaidYOp, ReadPtxSregNctaidZOp,
-    ReadPtxSregNsmIdOp, ReadPtxSregNtidXOp, ReadPtxSregNtidYOp, ReadPtxSregNtidZOp,
-    ReadPtxSregNwarpIdOp, ReadPtxSregSmIdOp, ReadPtxSregTidXOp, ReadPtxSregTidYOp,
-    ReadPtxSregTidZOp, ReadPtxSregTotalSmemSizeOp, ReadPtxSregWarpIdOp, ReduxSyncAddOp,
-    ReduxSyncAndOp, ReduxSyncFmaxAbsNanOp, ReduxSyncFmaxAbsOp, ReduxSyncFmaxNanOp, ReduxSyncFmaxOp,
-    ReduxSyncFminAbsNanOp, ReduxSyncFminAbsOp, ReduxSyncFminNanOp, ReduxSyncFminOp, ReduxSyncMaxOp,
-    ReduxSyncMinOp, ReduxSyncOrOp, ReduxSyncUmaxOp, ReduxSyncUminOp, ReduxSyncXorOp,
-    RegisterMmaAccumulatorAttr, RegisterMmaElementAttr, RegisterMmaKindAttr, RegisterMmaLayoutAttr,
-    RegisterMmaOp, RegisterMmaOperationAttr, RegisterMmaOverflowAttr, RegisterMmaShapeAttr,
-    ReplaceTensorMapBoxDimOp, ReplaceTensorMapElementStrideOp, ReplaceTensorMapElementTypeOp,
-    ReplaceTensorMapFillModeOp, ReplaceTensorMapGlobalAddressOp, ReplaceTensorMapGlobalDimOp,
-    ReplaceTensorMapGlobalStrideOp, ReplaceTensorMapInterleaveLayoutOp, ReplaceTensorMapRankOp,
-    ReplaceTensorMapSwizzleAtomicityOp, ReplaceTensorMapSwizzleModeOp, ScalarArithmeticFormatAttr,
-    ScalarArithmeticOp, ScalarArithmeticOperationAttr, ScalarArithmeticRoundingAttr,
-    ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr, ScalarConversionOp,
-    ScalarConversionRoundingAttr, ScalarConversionSaturationAttr, ScalarMathFormatAttr,
-    ScalarMathOp, ScalarMathOperationAttr, ScalarMathPrecisionAttr, ScalarMathSubnormalAttr,
-    SetMaxNRegDecOp, SetMaxNRegIncOp, ShflSyncBflyF32Op, ShflSyncBflyI32Op, ShflSyncBflyI64Op,
-    ShflSyncDownF32Op, ShflSyncDownI32Op, ShflSyncDownI64Op, ShflSyncIdxF32Op, ShflSyncIdxI32Op,
-    ShflSyncIdxI64Op, ShflSyncUpF32Op, ShflSyncUpI32Op, ShflSyncUpI64Op, SparseMmaAccumulatorAttr,
-    SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr, SparseMmaOp,
-    SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr, StmatrixM8n8X2Op,
-    StmatrixM8n8X2TransOp, StmatrixM8n8X4Op, StmatrixM8n8X4TransOp, SubBf16x2Op, SubF16x2Op,
-    SubF32x2Op, SubFtzF32x2Op, Tcgen05AllocCg2Op, Tcgen05AllocOp, Tcgen05CommitCg2Op,
-    Tcgen05CommitMulticastCg2Op, Tcgen05CommitMulticastOp, Tcgen05CommitOp,
-    Tcgen05CommitSharedClusterCg2Op, Tcgen05CommitSharedClusterOp, Tcgen05Cp4x256bB4x16P64Cg2Op,
-    Tcgen05Cp4x256bB4x16P64Op, Tcgen05Cp4x256bB6x16P32Cg2Op, Tcgen05Cp4x256bB6x16P32Op,
-    Tcgen05Cp4x256bCg2Op, Tcgen05Cp4x256bOp, Tcgen05Cp32x128bWarpx4B4x16P64Cg2Op,
-    Tcgen05Cp32x128bWarpx4B4x16P64Op, Tcgen05Cp32x128bWarpx4B6x16P32Cg2Op,
-    Tcgen05Cp32x128bWarpx4B6x16P32Op, Tcgen05Cp32x128bWarpx4Cg2Op, Tcgen05Cp32x128bWarpx4Op,
-    Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Op,
-    Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Op,
-    Tcgen05Cp64x128bWarpx2Pair0123Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123Op,
-    Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Op,
-    Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Op,
-    Tcgen05Cp64x128bWarpx2Pair0213Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213Op,
-    Tcgen05Cp128x128bB4x16P64Cg2Op, Tcgen05Cp128x128bB4x16P64Op, Tcgen05Cp128x128bB6x16P32Cg2Op,
-    Tcgen05Cp128x128bB6x16P32Op, Tcgen05Cp128x128bCg2Op, Tcgen05Cp128x128bOp,
-    Tcgen05Cp128x256bB4x16P64Cg2Op, Tcgen05Cp128x256bB4x16P64Op, Tcgen05Cp128x256bB6x16P32Cg2Op,
-    Tcgen05Cp128x256bB6x16P32Op, Tcgen05CpSmemToTmemCg2Op, Tcgen05CpSmemToTmemOp,
-    Tcgen05DeallocCg2Op, Tcgen05DeallocOp, Tcgen05FenceAfterThreadSyncOp,
-    Tcgen05FenceBeforeThreadSyncOp, Tcgen05Ld16x32bx2X1Pack16Op, Tcgen05Ld16x32bx2X1RawOp,
-    Tcgen05Ld16x32bx2X2Pack16Op, Tcgen05Ld16x32bx2X2RawOp, Tcgen05Ld16x32bx2X4Pack16Op,
-    Tcgen05Ld16x32bx2X4RawOp, Tcgen05Ld16x32bx2X8Pack16Op, Tcgen05Ld16x32bx2X8RawOp,
-    Tcgen05Ld16x32bx2X16Pack16Op, Tcgen05Ld16x32bx2X16RawOp, Tcgen05Ld16x32bx2X32Pack16Op,
-    Tcgen05Ld16x32bx2X32RawOp, Tcgen05Ld16x32bx2X64Pack16Op, Tcgen05Ld16x32bx2X64RawOp,
-    Tcgen05Ld16x32bx2X128Pack16Op, Tcgen05Ld16x32bx2X128RawOp, Tcgen05Ld16x64bX1Pack16Op,
-    Tcgen05Ld16x64bX1RawOp, Tcgen05Ld16x64bX2Pack16Op, Tcgen05Ld16x64bX2RawOp,
-    Tcgen05Ld16x64bX4Pack16Op, Tcgen05Ld16x64bX4RawOp, Tcgen05Ld16x64bX8Pack16Op,
-    Tcgen05Ld16x64bX8RawOp, Tcgen05Ld16x64bX16Pack16Op, Tcgen05Ld16x64bX16RawOp,
-    Tcgen05Ld16x64bX32Pack16Op, Tcgen05Ld16x64bX32RawOp, Tcgen05Ld16x64bX64Pack16Op,
-    Tcgen05Ld16x64bX64RawOp, Tcgen05Ld16x64bX128Pack16Op, Tcgen05Ld16x64bX128RawOp,
-    Tcgen05Ld16x128bX1Pack16Op, Tcgen05Ld16x128bX1RawOp, Tcgen05Ld16x128bX2Pack16Op,
-    Tcgen05Ld16x128bX2RawOp, Tcgen05Ld16x128bX4Pack16Op, Tcgen05Ld16x128bX4RawOp,
-    Tcgen05Ld16x128bX8Pack16Op, Tcgen05Ld16x128bX8RawOp, Tcgen05Ld16x128bX16Pack16Op,
-    Tcgen05Ld16x128bX16RawOp, Tcgen05Ld16x128bX32Pack16Op, Tcgen05Ld16x128bX32RawOp,
-    Tcgen05Ld16x128bX64Pack16Op, Tcgen05Ld16x128bX64RawOp, Tcgen05Ld16x256bPureOp,
-    Tcgen05Ld16x256bX1Pack16Op, Tcgen05Ld16x256bX1RawOp, Tcgen05Ld16x256bX2Pack16Op,
-    Tcgen05Ld16x256bX2RawOp, Tcgen05Ld16x256bX4Pack16Op, Tcgen05Ld16x256bX4RawOp,
-    Tcgen05Ld16x256bX8Pack16Op, Tcgen05Ld16x256bX8PureOp, Tcgen05Ld16x256bX8RawOp,
-    Tcgen05Ld16x256bX16Pack16Op, Tcgen05Ld16x256bX16RawOp, Tcgen05Ld16x256bX32Pack16Op,
-    Tcgen05Ld16x256bX32RawOp, Tcgen05Ld32x32bX1Pack16Op, Tcgen05Ld32x32bX1RawOp,
-    Tcgen05Ld32x32bX2Pack16Op, Tcgen05Ld32x32bX2RawOp, Tcgen05Ld32x32bX4Pack16Op,
-    Tcgen05Ld32x32bX4RawOp, Tcgen05Ld32x32bX8Pack16Op, Tcgen05Ld32x32bX8RawOp,
-    Tcgen05Ld32x32bX16Pack16Op, Tcgen05Ld32x32bX16RawOp, Tcgen05Ld32x32bX32Pack16Op,
-    Tcgen05Ld32x32bX32RawOp, Tcgen05Ld32x32bX64Pack16Op, Tcgen05Ld32x32bX64RawOp,
-    Tcgen05Ld32x32bX128Pack16Op, Tcgen05Ld32x32bX128RawOp, Tcgen05LoadWaitOp,
-    Tcgen05MmaBBufferAttr, Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr,
-    Tcgen05MmaF16Cg2Op, Tcgen05MmaF16Op, Tcgen05MmaFormAttr, Tcgen05MmaKindAttr, Tcgen05MmaOp,
-    Tcgen05MmaWsBf16Op, Tcgen05MmaWsF16Op, Tcgen05MmaWsTf32Op, Tcgen05RelinquishAllocPermitCg2Op,
-    Tcgen05RelinquishAllocPermitOp, Tcgen05ShiftDownCg2Op, Tcgen05ShiftDownOp,
-    Tcgen05St16x32bx2X1RawOp, Tcgen05St16x32bx2X1Unpack16Op, Tcgen05St16x32bx2X2RawOp,
-    Tcgen05St16x32bx2X2Unpack16Op, Tcgen05St16x32bx2X4RawOp, Tcgen05St16x32bx2X4Unpack16Op,
-    Tcgen05St16x32bx2X8RawOp, Tcgen05St16x32bx2X8Unpack16Op, Tcgen05St16x32bx2X16RawOp,
-    Tcgen05St16x32bx2X16Unpack16Op, Tcgen05St16x32bx2X32RawOp, Tcgen05St16x32bx2X32Unpack16Op,
-    Tcgen05St16x32bx2X64RawOp, Tcgen05St16x32bx2X64Unpack16Op, Tcgen05St16x32bx2X128RawOp,
-    Tcgen05St16x32bx2X128Unpack16Op, Tcgen05St16x64bX1RawOp, Tcgen05St16x64bX1Unpack16Op,
-    Tcgen05St16x64bX2RawOp, Tcgen05St16x64bX2Unpack16Op, Tcgen05St16x64bX4RawOp,
-    Tcgen05St16x64bX4Unpack16Op, Tcgen05St16x64bX8RawOp, Tcgen05St16x64bX8Unpack16Op,
-    Tcgen05St16x64bX16RawOp, Tcgen05St16x64bX16Unpack16Op, Tcgen05St16x64bX32RawOp,
-    Tcgen05St16x64bX32Unpack16Op, Tcgen05St16x64bX64RawOp, Tcgen05St16x64bX64Unpack16Op,
-    Tcgen05St16x64bX128RawOp, Tcgen05St16x64bX128Unpack16Op, Tcgen05St16x128bX1RawOp,
-    Tcgen05St16x128bX1Unpack16Op, Tcgen05St16x128bX2RawOp, Tcgen05St16x128bX2Unpack16Op,
-    Tcgen05St16x128bX4RawOp, Tcgen05St16x128bX4Unpack16Op, Tcgen05St16x128bX8RawOp,
-    Tcgen05St16x128bX8Unpack16Op, Tcgen05St16x128bX16RawOp, Tcgen05St16x128bX16Unpack16Op,
-    Tcgen05St16x128bX32RawOp, Tcgen05St16x128bX32Unpack16Op, Tcgen05St16x128bX64RawOp,
-    Tcgen05St16x128bX64Unpack16Op, Tcgen05St16x256bX1RawOp, Tcgen05St16x256bX1Unpack16Op,
-    Tcgen05St16x256bX2RawOp, Tcgen05St16x256bX2Unpack16Op, Tcgen05St16x256bX4RawOp,
-    Tcgen05St16x256bX4Unpack16Op, Tcgen05St16x256bX8RawOp, Tcgen05St16x256bX8Unpack16Op,
-    Tcgen05St16x256bX16RawOp, Tcgen05St16x256bX16Unpack16Op, Tcgen05St16x256bX32RawOp,
-    Tcgen05St16x256bX32Unpack16Op, Tcgen05St32x32bX1RawOp, Tcgen05St32x32bX1Unpack16Op,
-    Tcgen05St32x32bX2RawOp, Tcgen05St32x32bX2Unpack16Op, Tcgen05St32x32bX4RawOp,
-    Tcgen05St32x32bX4Unpack16Op, Tcgen05St32x32bX8RawOp, Tcgen05St32x32bX8Unpack16Op,
-    Tcgen05St32x32bX16RawOp, Tcgen05St32x32bX16Unpack16Op, Tcgen05St32x32bX32RawOp,
-    Tcgen05St32x32bX32Unpack16Op, Tcgen05St32x32bX64RawOp, Tcgen05St32x32bX64Unpack16Op,
-    Tcgen05St32x32bX128RawOp, Tcgen05St32x32bX128Unpack16Op, Tcgen05StoreWaitOp,
-    ThreadfenceBlockOp, ThreadfenceOp, ThreadfenceSystemOp, TrapOp, VoteSyncAllOp, VoteSyncAnyOp,
-    VoteSyncBallotOp, VoteSyncUniOp, WgmmaCommitGroupSyncAlignedOp, WgmmaFenceSyncAlignedOp,
-    WgmmaWaitGroupSyncAlignedOp,
-};
-use llvm_export::{
-    op_interfaces::CastOpInterface, ops as llvm_ops, ops::AsmKind, types as llvm_types,
-};
-use pliron::{
-    builtin::types::{FP32Type, IntegerType, Signedness},
-    context::{Context, Ptr},
-    derive::op_interface_impl,
-    irbuild::{
-        dialect_conversion::{DialectConversionRewriter, OperandsInfo},
-        inserter::Inserter,
-        rewriter::Rewriter,
-    },
-    op::Op,
-    operation::Operation,
-    result::Result,
-};
-
-use pliron::location::Located;
-
-use pliron::value::DefiningEntity;
-
-fn convert_zero_operand_scalar_direct(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    width: u32,
-    intrinsic_name: &str,
-) -> Result<()> {
-    let result_ty = IntegerType::get(ctx, width, Signedness::Signless);
-    let function_ty = llvm_types::FuncType::get(ctx, result_ty.into(), vec![], false);
-    let call = call_intrinsic(ctx, rewriter, op, intrinsic_name, function_ty, vec![])?;
-    rewriter.replace_operation(ctx, op, call);
-    Ok(())
-}
-
-fn convert_generated_tcgen05_void(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    arity: usize,
-    template: &str,
-    constraints: &str,
-) -> Result<()> {
-    let operands: Vec<_> = op.deref(ctx).operands().collect();
-    if operands.len() != arity {
-        return pliron::input_err_noloc!(
-            "generated tcgen05 operation expects {arity} operands, got {}",
-            operands.len()
-        );
-    }
-    let void_ty = llvm_types::VoidType::get(ctx);
-    inline_asm_convergent(
-        ctx,
-        rewriter,
-        op,
-        void_ty.into(),
-        operands,
-        template,
-        constraints,
-    );
-    rewriter.erase_operation(ctx, op);
-    Ok(())
-}
-
-#[allow(clippy::too_many_arguments)]
-fn convert_generated_tcgen05_load(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    arity: usize,
-    count: usize,
-    integer_results: bool,
-    template: &str,
-    constraints: &str,
-) -> Result<()> {
-    let operands: Vec<_> = op.deref(ctx).operands().collect();
-    if operands.len() != arity
-        || !(1..=2).contains(&arity)
-        || !(1..=128).contains(&count)
-        || op.deref(ctx).get_num_results() != count
-    {
-        return pliron::input_err_noloc!(
-            "generated tcgen05 load requires 1..=2 operands and 1..=128 results"
-        );
-    }
-    let scalar_ty: pliron::r#type::TypeHandle = if integer_results {
-        IntegerType::get(ctx, 32, Signedness::Signless).into()
-    } else {
-        FP32Type::get(ctx).into()
-    };
-    if count == 1 {
-        let inline_asm = inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            scalar_ty,
-            operands,
-            template,
-            constraints,
-        );
-        let result = inline_asm.deref(ctx).get_result(0);
-        rewriter.replace_operation_with_values(ctx, op, vec![result]);
-        return Ok(());
-    }
-    let result_ty = llvm_types::StructType::get_unnamed(
-        ctx,
-        (
-            (0..count).map(|_| scalar_ty).collect(),
-            llvm_types::StructLayout::Unpacked,
-        ),
-    );
-    let inline_asm = inline_asm_convergent(
-        ctx,
-        rewriter,
-        op,
-        result_ty.into(),
-        operands,
-        template,
-        constraints,
-    );
-    let result = inline_asm.deref(ctx).get_result(0);
-    let mut values = Vec::with_capacity(count);
-    for index in 0..count as u32 {
-        let extract = llvm_ops::ExtractValueOp::new(ctx, result, vec![index])
-            .map_err(|error| pliron::input_error_noloc!("{}", error))?;
-        rewriter.insert_operation(ctx, extract.get_operation());
-        values.push(extract.get_operation().deref(ctx).get_result(0));
-    }
-    rewriter.replace_operation_with_values(ctx, op, values);
-    Ok(())
-}
-
-fn convert_generated_stmatrix(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    register_count: usize,
-    transposed: bool,
-    typed_intrinsic_name: &str,
-) -> Result<()> {
-    let operands: Vec<_> = op.deref(ctx).operands().collect();
-    if operands.len() != register_count + 1 || !matches!(register_count, 2 | 4) {
-        return pliron::input_err_noloc!("stmatrix requires one pointer and two or four registers");
-    }
-    let void_ty = llvm_types::VoidType::get(ctx);
-    match context::lowering_options(ctx).intrinsic_backend {
-        IntrinsicBackend::LlvmNvptx => {
-            let shared = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
-            let shared_ty = llvm_types::PointerType::get(ctx, llvm_types::address_space::SHARED);
-            let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-            let argument_types = std::iter::once(shared_ty.into())
-                .chain(std::iter::repeat_n(i32_ty.into(), register_count))
-                .collect();
-            let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), argument_types, false);
-            let arguments = std::iter::once(shared)
-                .chain(operands.iter().skip(1).copied())
-                .collect();
-            call_intrinsic(
-                ctx,
-                rewriter,
-                op,
-                typed_intrinsic_name,
-                function_ty,
-                arguments,
-            )?;
-        }
-        IntrinsicBackend::LibNvvm => {
-            let registers = (1..=register_count)
-                .map(|index| format!("${index}"))
-                .collect::<Vec<_>>()
-                .join(", ");
-            let trans = if transposed { ".trans" } else { "" };
-            let template = format!(
-                "{{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x{register_count}{trans}.shared.b16 [%ptr32], {{{registers}}}; }}"
-            );
-            let constraints = std::iter::once("l")
-                .chain(std::iter::repeat_n("r", register_count))
-                .chain(std::iter::once("~{memory}"))
-                .collect::<Vec<_>>()
-                .join(",");
-            inline_asm_convergent(
-                ctx,
-                rewriter,
-                op,
-                void_ty.into(),
-                operands,
-                &template,
-                &constraints,
-            );
-        }
-    }
-    rewriter.erase_operation(ctx, op);
-    Ok(())
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNtidXOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_ntid_x",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNtidYOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_ntid_y",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNtidZOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_ntid_z",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregCtaidXOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_ctaid_x",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregCtaidYOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_ctaid_y",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregCtaidZOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_ctaid_z",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClockOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "llvm_nvvm_read_ptx_sreg_clock",
-            ),
-            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "llvm_nvvm_read_ptx_sreg_clock",
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClock64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                64,
-                "llvm_nvvm_read_ptx_sreg_clock64",
-            ),
-            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                64,
-                "llvm_nvvm_read_ptx_sreg_clock64",
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterNctarankOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_cluster_nctarank",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterCtaidXOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_cluster_ctaid_x",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterCtaidYOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_cluster_ctaid_y",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterCtaidZOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_cluster_ctaid_z",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterCtarankOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_cluster_ctarank",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterNctaidXOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_cluster_nctaid_x",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterNctaidYOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_cluster_nctaid_y",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterNctaidZOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_cluster_nctaid_z",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNclusterIdXOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_nclusterid_x",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNclusterIdYOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_nclusterid_y",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNclusterIdZOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_nclusterid_z",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterIdXOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_clusterid_x",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterIdYOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_clusterid_y",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregClusterIdZOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_clusterid_z",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregDynamicSmemSizeOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "mov.u32 $0, %dynamic_smem_size;",
-                "=r",
-                AsmKind::Pure,
-            ),
-            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "mov.u32 $0, %dynamic_smem_size;",
-                "=r",
-                AsmKind::Pure,
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregEnvReg1Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "llvm_nvvm_read_ptx_sreg_envreg1",
-            ),
-            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "llvm_nvvm_read_ptx_sreg_envreg1",
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregEnvReg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "llvm_nvvm_read_ptx_sreg_envreg2",
-            ),
-            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "llvm_nvvm_read_ptx_sreg_envreg2",
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregGlobaltimerOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                64,
-                "llvm_nvvm_read_ptx_sreg_globaltimer",
-            ),
-            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                64,
-                "mov.u64 $0, %globaltimer;",
-                "=l",
-                AsmKind::SideEffect,
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNctaidXOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_nctaid_x",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNctaidYOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_nctaid_y",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNctaidZOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_nctaid_z",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregGridIdOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                64,
-                "mov.u64 $0, %gridid;",
-                "=l",
-                AsmKind::Pure,
-            ),
-            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                64,
-                "mov.u64 $0, %gridid;",
-                "=l",
-                AsmKind::Pure,
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregLaneIdOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_laneid",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregLanemaskEqOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_lanemask_eq",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregLanemaskGeOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_lanemask_ge",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregLanemaskGtOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_lanemask_gt",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregLanemaskLeOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_lanemask_le",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregLanemaskLtOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_lanemask_lt",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNsmIdOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "llvm_nvvm_read_ptx_sreg_nsmid",
-            ),
-            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "llvm_nvvm_read_ptx_sreg_nsmid",
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregNwarpIdOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "llvm_nvvm_read_ptx_sreg_nwarpid",
-            ),
-            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "llvm_nvvm_read_ptx_sreg_nwarpid",
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregSmIdOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "mov.u32 $0, %smid;",
-                "=r",
-                AsmKind::SideEffect,
-            ),
-            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "mov.u32 $0, %smid;",
-                "=r",
-                AsmKind::SideEffect,
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregTidXOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_tid_x",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregTidYOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_tid_y",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregTidZOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_zero_operand_scalar_direct(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            32,
-            "llvm_nvvm_read_ptx_sreg_tid_z",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregTotalSmemSizeOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "mov.u32 $0, %total_smem_size;",
-                "=r",
-                AsmKind::Pure,
-            ),
-            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "mov.u32 $0, %total_smem_size;",
-                "=r",
-                AsmKind::Pure,
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReadPtxSregWarpIdOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "mov.u32 $0, %warpid;",
-                "=r",
-                AsmKind::SideEffect,
-            ),
-            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                32,
-                "mov.u32 $0, %warpid;",
-                "=r",
-                AsmKind::SideEffect,
-            ),
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ActiveMaskOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_active_mask(ctx, rewriter, op, operands_info),
-            IntrinsicBackend::LibNvvm => {
-                let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-                let inline_asm = inline_asm_convergent(
-                    ctx,
-                    rewriter,
-                    op,
-                    i32_ty.into(),
-                    vec![],
-                    "activemask.b32 $0;",
-                    "=r,~{memory}",
-                );
-                rewriter.replace_operation(ctx, op, inline_asm);
-                Ok(())
-            }
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for LdmatrixOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let recipe = {
-            let shape = self.get_attr_nvvm_ldmatrix_shape(ctx);
-            let multiplicity = self.get_attr_nvvm_ldmatrix_multiplicity(ctx);
-            let layout = self.get_attr_nvvm_ldmatrix_layout(ctx);
-            let element = self.get_attr_nvvm_ldmatrix_element(ctx);
-            let state_space = self.get_attr_nvvm_ldmatrix_state_space(ctx);
-            match (
-                shape.as_deref(),
-                multiplicity.as_deref(),
-                layout.as_deref(),
-                element.as_deref(),
-                state_space.as_deref(),
-            ) {
-                (
-                    Some(&LdmatrixShapeAttr::M16n16),
-                    Some(&LdmatrixMultiplicityAttr::X1),
-                    Some(&LdmatrixLayoutAttr::Transposed),
-                    Some(&LdmatrixElementAttr::B8),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    2,
-                    "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8",
-                    "llvm_nvvm_ldmatrix_sync_aligned_m16n16_x1_trans_b8_p3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M16n16),
-                    Some(&LdmatrixMultiplicityAttr::X1),
-                    Some(&LdmatrixLayoutAttr::Transposed),
-                    Some(&LdmatrixElementAttr::B8x16B4x16P64),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    2,
-                    "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b4x16_p64",
-                    "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db4x16_up64_dp3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M16n16),
-                    Some(&LdmatrixMultiplicityAttr::X1),
-                    Some(&LdmatrixLayoutAttr::Transposed),
-                    Some(&LdmatrixElementAttr::B8x16B6x16P32),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    2,
-                    "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b6x16_p32",
-                    "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db6x16_up32_dp3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M16n16),
-                    Some(&LdmatrixMultiplicityAttr::X2),
-                    Some(&LdmatrixLayoutAttr::Transposed),
-                    Some(&LdmatrixElementAttr::B8),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    4,
-                    "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8",
-                    "llvm_nvvm_ldmatrix_sync_aligned_m16n16_x2_trans_b8_p3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M16n16),
-                    Some(&LdmatrixMultiplicityAttr::X2),
-                    Some(&LdmatrixLayoutAttr::Transposed),
-                    Some(&LdmatrixElementAttr::B8x16B4x16P64),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    4,
-                    "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b4x16_p64",
-                    "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx2_dtrans_db8x16_db4x16_up64_dp3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M16n16),
-                    Some(&LdmatrixMultiplicityAttr::X2),
-                    Some(&LdmatrixLayoutAttr::Transposed),
-                    Some(&LdmatrixElementAttr::B8x16B6x16P32),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    4,
-                    "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b6x16_p32",
-                    "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx2_dtrans_db8x16_db6x16_up32_dp3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n16),
-                    Some(&LdmatrixMultiplicityAttr::X1),
-                    Some(&LdmatrixLayoutAttr::Normal),
-                    Some(&LdmatrixElementAttr::B8x16B4x16P64),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    1,
-                    "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b4x16_p64",
-                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx1_db8x16_db4x16_up64_dp3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n16),
-                    Some(&LdmatrixMultiplicityAttr::X1),
-                    Some(&LdmatrixLayoutAttr::Normal),
-                    Some(&LdmatrixElementAttr::B8x16B6x16P32),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    1,
-                    "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b6x16_p32",
-                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx1_db8x16_db6x16_up32_dp3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n16),
-                    Some(&LdmatrixMultiplicityAttr::X2),
-                    Some(&LdmatrixLayoutAttr::Normal),
-                    Some(&LdmatrixElementAttr::B8x16B4x16P64),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    2,
-                    "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b4x16_p64",
-                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx2_db8x16_db4x16_up64_dp3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n16),
-                    Some(&LdmatrixMultiplicityAttr::X2),
-                    Some(&LdmatrixLayoutAttr::Normal),
-                    Some(&LdmatrixElementAttr::B8x16B6x16P32),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    2,
-                    "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b6x16_p32",
-                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx2_db8x16_db6x16_up32_dp3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n16),
-                    Some(&LdmatrixMultiplicityAttr::X4),
-                    Some(&LdmatrixLayoutAttr::Normal),
-                    Some(&LdmatrixElementAttr::B8x16B4x16P64),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    4,
-                    "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b4x16_p64",
-                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx4_db8x16_db4x16_up64_dp3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n16),
-                    Some(&LdmatrixMultiplicityAttr::X4),
-                    Some(&LdmatrixLayoutAttr::Normal),
-                    Some(&LdmatrixElementAttr::B8x16B6x16P32),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    4,
-                    "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b6x16_p32",
-                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx4_db8x16_db6x16_up32_dp3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n8),
-                    Some(&LdmatrixMultiplicityAttr::X1),
-                    Some(&LdmatrixLayoutAttr::Normal),
-                    Some(&LdmatrixElementAttr::B16),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    1,
-                    "ldmatrix.sync.aligned.m8n8.x1.shared.b16",
-                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_b16_p3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n8),
-                    Some(&LdmatrixMultiplicityAttr::X1),
-                    Some(&LdmatrixLayoutAttr::Transposed),
-                    Some(&LdmatrixElementAttr::B16),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    1,
-                    "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16",
-                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_trans_b16_p3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n8),
-                    Some(&LdmatrixMultiplicityAttr::X2),
-                    Some(&LdmatrixLayoutAttr::Normal),
-                    Some(&LdmatrixElementAttr::B16),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    2,
-                    "ldmatrix.sync.aligned.m8n8.x2.shared.b16",
-                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_b16_p3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n8),
-                    Some(&LdmatrixMultiplicityAttr::X2),
-                    Some(&LdmatrixLayoutAttr::Transposed),
-                    Some(&LdmatrixElementAttr::B16),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    2,
-                    "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16",
-                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n8),
-                    Some(&LdmatrixMultiplicityAttr::X4),
-                    Some(&LdmatrixLayoutAttr::Normal),
-                    Some(&LdmatrixElementAttr::B16),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    4,
-                    "ldmatrix.sync.aligned.m8n8.x4.shared.b16",
-                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_b16_p3",
-                ),
-                (
-                    Some(&LdmatrixShapeAttr::M8n8),
-                    Some(&LdmatrixMultiplicityAttr::X4),
-                    Some(&LdmatrixLayoutAttr::Transposed),
-                    Some(&LdmatrixElementAttr::B16),
-                    Some(&LdmatrixStateSpaceAttr::Shared),
-                ) => (
-                    4,
-                    "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16",
-                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
-                ),
-                _ => {
-                    return pliron::input_err!(
-                        self.get_operation().deref(ctx).loc(),
-                        "nvvm.ldmatrix variant has no generated lowering recipe",
-                    );
-                }
-            }
-        };
-        convert_generated_ldmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            recipe.0,
-            recipe.1,
-            recipe.2,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for LdmatrixX1Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_ldmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            "ldmatrix.sync.aligned.m8n8.x1.shared.b16",
-            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_b16_p3",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for LdmatrixX1TransOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_ldmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16",
-            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_trans_b16_p3",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for LdmatrixX2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_ldmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "ldmatrix.sync.aligned.m8n8.x2.shared.b16",
-            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_b16_p3",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for LdmatrixX2TransOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_ldmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16",
-            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for LdmatrixX4Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_ldmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            4,
-            "ldmatrix.sync.aligned.m8n8.x4.shared.b16",
-            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_b16_p3",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for LdmatrixX4TransOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_ldmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            4,
-            "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16",
-            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for StmatrixM8n8X2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_stmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            false,
-            "llvm_nvvm_stmatrix_sync_aligned_m8n8_x2_b16_p3",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for StmatrixM8n8X2TransOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_stmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            true,
-            "llvm_nvvm_stmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for StmatrixM8n8X4Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_stmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            4,
-            false,
-            "llvm_nvvm_stmatrix_sync_aligned_m8n8_x4_b16_p3",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for StmatrixM8n8X4TransOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_stmatrix(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            4,
-            true,
-            "llvm_nvvm_stmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MovmatrixTransB16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let operands: Vec<_> = op.deref(ctx).operands().collect();
-        if operands.len() != 1 {
-            return pliron::input_err_noloc!(
-                "movmatrix_trans_b16 requires 1 operand, got {}",
-                operands.len()
-            );
-        }
-        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-        let asm = inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            result_ty.into(),
-            operands,
-            "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;",
-            "=r,r",
-        );
-        rewriter.replace_operation(ctx, op, asm);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for RegisterMmaOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let operation = self.operation_or_multiply(ctx);
-        let kind = self.kind_or_inferred(ctx);
-        let recipe = match (
-            self.get_attr_nvvm_register_mma_shape(ctx).as_deref(),
-            operation,
-            kind,
-            self.get_attr_nvvm_register_mma_accumulator(ctx).as_deref(),
-            self.get_attr_nvvm_register_mma_a_element(ctx).as_deref(),
-            self.get_attr_nvvm_register_mma_b_element(ctx).as_deref(),
-            self.get_attr_nvvm_register_mma_a_layout(ctx).as_deref(),
-            self.get_attr_nvvm_register_mma_b_layout(ctx).as_deref(),
-            self.get_attr_nvvm_register_mma_overflow(ctx).as_deref(),
-        ) {
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k128),
-                RegisterMmaOperationAttr::AndPopc,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k128),
-                RegisterMmaOperationAttr::XorPopc,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::F16),
-                Some(&RegisterMmaElementAttr::F16),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::Bf16),
-                Some(&RegisterMmaElementAttr::Bf16),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::F16),
-                Some(&RegisterMmaElementAttr::F16),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                5,
-                "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e4m3.f16 {$0, $1}, {$4, $5}, {$6}, {$2, $3};",
-                "=r,=r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                5,
-                "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e5m2.f16 {$0, $1}, {$4, $5}, {$6}, {$2, $3};",
-                "=r,=r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                5,
-                "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e4m3.f16 {$0, $1}, {$4, $5}, {$6}, {$2, $3};",
-                "=r,=r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                5,
-                "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e5m2.f16 {$0, $1}, {$4, $5}, {$6}, {$2, $3};",
-                "=r,=r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k256),
-                RegisterMmaOperationAttr::AndPopc,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k256),
-                RegisterMmaOperationAttr::XorPopc,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::F8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                8,
-                "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
-                "=r,=r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e3m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e4m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e5m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e3m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e4m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e5m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e3m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e4m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e5m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e3m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e4m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e5m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E2m1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E2m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E3m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e3m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E4m3),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e4m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Mxf8f6f4,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaElementAttr::E5m2),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                16,
-                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e5m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k32.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k32.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k4),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::Tf32),
-                Some(&RegisterMmaElementAttr::Tf32),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k4.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k64),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k64),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k64),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k64),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k64),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k64),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k64),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k64),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k8),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F16),
-                Some(&RegisterMmaElementAttr::F16),
-                Some(&RegisterMmaElementAttr::F16),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                5,
-                "mma.sync.aligned.m16n8k8.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6}, {$2, $3};",
-                "=r,=r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k8),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::Bf16),
-                Some(&RegisterMmaElementAttr::Bf16),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k8),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::F16),
-                Some(&RegisterMmaElementAttr::F16),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                7,
-                "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M16n8k8),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F32),
-                Some(&RegisterMmaElementAttr::Tf32),
-                Some(&RegisterMmaElementAttr::Tf32),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                10,
-                "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k128),
-                RegisterMmaOperationAttr::AndPopc,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k128),
-                RegisterMmaOperationAttr::XorPopc,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaElementAttr::B1),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k16.row.col.s32.u8.s8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::S8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k16),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaElementAttr::U8),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.u8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.s4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k32.row.col.s32.u4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Wrapping),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k32.row.col.s32.u4.s4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::S4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k32),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::S32),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaElementAttr::U4),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::Satfinite),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=r,=r,r,r,r,r",
-            ),
-            (
-                Some(&RegisterMmaShapeAttr::M8n8k4),
-                RegisterMmaOperationAttr::Multiply,
-                RegisterMmaKindAttr::Standard,
-                Some(&RegisterMmaAccumulatorAttr::F64),
-                Some(&RegisterMmaElementAttr::F64),
-                Some(&RegisterMmaElementAttr::F64),
-                Some(&RegisterMmaLayoutAttr::Row),
-                Some(&RegisterMmaLayoutAttr::Col),
-                Some(&RegisterMmaOverflowAttr::NotApplicable),
-            ) => (
-                GeneratedMmaResultType::F64,
-                2,
-                4,
-                "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$4}, {$5}, {$2, $3};",
-                "=d,=d,d,d,d,d",
-            ),
-            _ => {
-                return pliron::input_err!(
-                    self.get_operation().deref(ctx).loc(),
-                    "nvvm.register_mma variant has no generated lowering recipe",
-                );
-            }
-        };
-        convert_generated_register_mma(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            recipe.0,
-            recipe.1,
-            recipe.2,
-            recipe.3,
-            recipe.4,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MmaM16N8K16F32Bf16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_register_mma(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            GeneratedMmaResultType::F32,
-            4,
-            10,
-            "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-            "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MmaM16N8K16F32F16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_register_mma(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            GeneratedMmaResultType::F32,
-            4,
-            10,
-            "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-            "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MmaM16N8K32S32S8Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_register_mma(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            GeneratedMmaResultType::I32,
-            4,
-            10,
-            "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MmaM16N8K8F32Tf32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_register_mma(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            GeneratedMmaResultType::F32,
-            4,
-            10,
-            "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
-            "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MmaM8N8K4F64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_register_mma(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            GeneratedMmaResultType::F64,
-            2,
-            4,
-            "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$4}, {$5}, {$2, $3};",
-            "=d,=d,d,d,d,d",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for SparseMmaOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let recipe = match (
-            self.get_attr_nvvm_sparse_mma_shape(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref(),
-            self.get_attr_nvvm_sparse_mma_selector(ctx).as_deref(),
-        ) {
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Standard),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k128),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k32),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F16),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                2,
-                12,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
-                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaElementAttr::E2m1),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaElementAttr::E2m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaElementAttr::E3m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaElementAttr::E4m3),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::F32),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaElementAttr::E5m2),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::NotApplicable),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::F32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::S4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaElementAttr::U4),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                10,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Wrapping),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::S8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            (
-                Some(&SparseMmaShapeAttr::M16n8k64),
-                Some(&SparseMmaAccumulatorAttr::S32),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaElementAttr::U8),
-                Some(&SparseMmaLayoutAttr::Row),
-                Some(&SparseMmaLayoutAttr::Col),
-                Some(&SparseMmaOverflowAttr::Satfinite),
-                Some(&SparseMmaMetadataAttr::Ordered),
-                Some(&SparseMmaSelectorAttr::ImmediateZero),
-            ) => (
-                GeneratedMmaResultType::I32,
-                4,
-                14,
-                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
-                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
-            ),
-            _ => {
-                return pliron::input_err!(
-                    self.get_operation().deref(ctx).loc(),
-                    "nvvm.sparse_mma variant has no generated lowering recipe",
-                );
-            }
-        };
-        convert_generated_sparse_mma(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            recipe.0,
-            recipe.1,
-            recipe.2,
-            recipe.3,
-            recipe.4,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for PrmtOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let recipe = match self.get_attr_nvvm_prmt_mode(ctx).as_deref() {
-            Some(&PrmtModeAttr::Generic) => ("llvm_nvvm_prmt", "prmt.b32 $0, $1, $2, $3;"),
-            Some(&PrmtModeAttr::B4e) => ("llvm_nvvm_prmt_b4e", "prmt.b32.b4e $0, $1, $2, $3;"),
-            Some(&PrmtModeAttr::Ecl) => ("llvm_nvvm_prmt_ecl", "prmt.b32.ecl $0, $1, 0, $2;"),
-            Some(&PrmtModeAttr::Ecr) => ("llvm_nvvm_prmt_ecr", "prmt.b32.ecr $0, $1, 0, $2;"),
-            Some(&PrmtModeAttr::F4e) => ("llvm_nvvm_prmt_f4e", "prmt.b32.f4e $0, $1, $2, $3;"),
-            Some(&PrmtModeAttr::Rc16) => ("llvm_nvvm_prmt_rc16", "prmt.b32.rc16 $0, $1, 0, $2;"),
-            Some(&PrmtModeAttr::Rc8) => ("llvm_nvvm_prmt_rc8", "prmt.b32.rc8 $0, $1, 0, $2;"),
-            _ => {
-                return pliron::input_err!(
-                    self.get_operation().deref(ctx).loc(),
-                    "nvvm.prmt mode has no generated lowering recipe",
-                );
-            }
-        };
-        convert_generated_prmt(ctx, rewriter, self.get_operation(), recipe.0, recipe.1)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ScalarConversionOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let recipe = match (
-            self.get_attr_nvvm_scalar_conversion_rounding(ctx)
-                .as_deref(),
-            self.get_attr_nvvm_scalar_conversion_saturation(ctx)
-                .as_deref(),
-        ) {
-            (
-                Some(&ScalarConversionRoundingAttr::NearestEven),
-                Some(&ScalarConversionSaturationAttr::ReluSatfinite),
-            ) => (
-                "llvm_nvvm_f2tf32_rn_relu_satfinite",
-                "cvt.rn.relu.satfinite.tf32.f32",
-            ),
-            (
-                Some(&ScalarConversionRoundingAttr::NearestEven),
-                Some(&ScalarConversionSaturationAttr::Relu),
-            ) => ("llvm_nvvm_f2tf32_rn_relu", "cvt.rn.relu.tf32.f32"),
-            (
-                Some(&ScalarConversionRoundingAttr::NearestEven),
-                Some(&ScalarConversionSaturationAttr::Satfinite),
-            ) => ("llvm_nvvm_f2tf32_rn_satfinite", "cvt.rn.satfinite.tf32.f32"),
-            (
-                Some(&ScalarConversionRoundingAttr::NearestEven),
-                Some(&ScalarConversionSaturationAttr::None),
-            ) => ("llvm_nvvm_f2tf32_rn", "cvt.rn.tf32.f32"),
-            (
-                Some(&ScalarConversionRoundingAttr::NearestAway),
-                Some(&ScalarConversionSaturationAttr::Satfinite),
-            ) => (
-                "llvm_nvvm_f2tf32_rna_satfinite",
-                "cvt.rna.satfinite.tf32.f32",
-            ),
-            (
-                Some(&ScalarConversionRoundingAttr::NearestAway),
-                Some(&ScalarConversionSaturationAttr::None),
-            ) => ("llvm_nvvm_f2tf32_rna", "cvt.rna.tf32.f32"),
-            (
-                Some(&ScalarConversionRoundingAttr::TowardZero),
-                Some(&ScalarConversionSaturationAttr::ReluSatfinite),
-            ) => (
-                "llvm_nvvm_f2tf32_rz_relu_satfinite",
-                "cvt.rz.relu.satfinite.tf32.f32",
-            ),
-            (
-                Some(&ScalarConversionRoundingAttr::TowardZero),
-                Some(&ScalarConversionSaturationAttr::Relu),
-            ) => ("llvm_nvvm_f2tf32_rz_relu", "cvt.rz.relu.tf32.f32"),
-            (
-                Some(&ScalarConversionRoundingAttr::TowardZero),
-                Some(&ScalarConversionSaturationAttr::Satfinite),
-            ) => ("llvm_nvvm_f2tf32_rz_satfinite", "cvt.rz.satfinite.tf32.f32"),
-            (
-                Some(&ScalarConversionRoundingAttr::TowardZero),
-                Some(&ScalarConversionSaturationAttr::None),
-            ) => ("llvm_nvvm_f2tf32_rz", "cvt.rz.tf32.f32"),
-            _ => {
-                return pliron::input_err!(
-                    self.get_operation().deref(ctx).loc(),
-                    "nvvm.scalar_conversion variant has no generated lowering recipe",
-                );
-            }
-        };
-        convert_generated_scalar_conversion(ctx, rewriter, self.get_operation(), recipe.0, recipe.1)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ScalarArithmeticOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let recipe = match (
-            self.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref(),
-            self.get_attr_nvvm_scalar_arithmetic_operation(ctx)
-                .as_deref(),
-            self.get_attr_nvvm_scalar_arithmetic_rounding(ctx)
-                .as_deref(),
-            self.get_attr_nvvm_scalar_arithmetic_subnormal(ctx)
-                .as_deref(),
-            self.get_attr_nvvm_scalar_arithmetic_saturation(ctx)
-                .as_deref(),
-        ) {
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rm_f", "add.rm.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rm_d", "add.rm.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rm_ftz_f", "add.rm.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => (
-                "llvm_nvvm_add_rm_ftz_sat_f",
-                "add.rm.sat.ftz.f32",
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => ("llvm_nvvm_add_rm_sat_f", "add.rm.sat.f32", false, true),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rn_f", "add.rn.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rn_d", "add.rn.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rn_ftz_f", "add.rn.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => (
-                "llvm_nvvm_add_rn_ftz_sat_f",
-                "add.rn.sat.ftz.f32",
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => ("llvm_nvvm_add_rn_sat_f", "add.rn.sat.f32", false, true),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rp_f", "add.rp.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rp_d", "add.rp.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rp_ftz_f", "add.rp.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => (
-                "llvm_nvvm_add_rp_ftz_sat_f",
-                "add.rp.sat.ftz.f32",
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => ("llvm_nvvm_add_rp_sat_f", "add.rp.sat.f32", false, true),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rz_f", "add.rz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rz_d", "add.rz.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_add_rz_ftz_f", "add.rz.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => (
-                "llvm_nvvm_add_rz_ftz_sat_f",
-                "add.rz.sat.ftz.f32",
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Add),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => ("llvm_nvvm_add_rz_sat_f", "add.rz.sat.f32", false, true),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rm_f", "div.rm.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rm_d", "div.rm.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rm_ftz_f", "div.rm.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rn_f", "div.rn.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rn_d", "div.rn.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rn_ftz_f", "div.rn.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rp_f", "div.rp.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rp_d", "div.rp.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rp_ftz_f", "div.rp.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rz_f", "div.rz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rz_d", "div.rz.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Div),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_div_rz_ftz_f", "div.rz.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rm_f", "fma.rm.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rm_d", "fma.rm.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rm_ftz_f", "fma.rm.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => (
-                "llvm_nvvm_fma_rm_ftz_sat_f",
-                "fma.rm.ftz.sat.f32",
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => ("llvm_nvvm_fma_rm_sat_f", "fma.rm.sat.f32", false, true),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rn_f", "fma.rn.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rn_d", "fma.rn.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rn_ftz_f", "fma.rn.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => (
-                "llvm_nvvm_fma_rn_ftz_sat_f",
-                "fma.rn.ftz.sat.f32",
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => ("llvm_nvvm_fma_rn_sat_f", "fma.rn.sat.f32", false, true),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rp_f", "fma.rp.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rp_d", "fma.rp.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rp_ftz_f", "fma.rp.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => (
-                "llvm_nvvm_fma_rp_ftz_sat_f",
-                "fma.rp.ftz.sat.f32",
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => ("llvm_nvvm_fma_rp_sat_f", "fma.rp.sat.f32", false, true),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rz_f", "fma.rz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rz_d", "fma.rz.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_fma_rz_ftz_f", "fma.rz.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => (
-                "llvm_nvvm_fma_rz_ftz_sat_f",
-                "fma.rz.ftz.sat.f32",
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Fma),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::Sat),
-            ) => ("llvm_nvvm_fma_rz_sat_f", "fma.rz.sat.f32", false, true),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rm_f", "mul.rm.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rm_d", "mul.rm.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rm),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rm_ftz_f", "mul.rm.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rn_f", "mul.rn.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rn_d", "mul.rn.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rn),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rn_ftz_f", "mul.rn.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rp_f", "mul.rp.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rp_d", "mul.rp.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rp),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rp_ftz_f", "mul.rp.ftz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rz_f", "mul.rz.f32", false, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F64),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Preserve),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rz_d", "mul.rz.f64", true, false),
-            (
-                Some(&ScalarArithmeticFormatAttr::F32),
-                Some(&ScalarArithmeticOperationAttr::Mul),
-                Some(&ScalarArithmeticRoundingAttr::Rz),
-                Some(&ScalarArithmeticSubnormalAttr::Ftz),
-                Some(&ScalarArithmeticSaturationAttr::None),
-            ) => ("llvm_nvvm_mul_rz_ftz_f", "mul.rz.ftz.f32", false, false),
-            _ => {
-                return pliron::input_err!(
-                    self.get_operation().deref(ctx).loc(),
-                    "nvvm.scalar_arithmetic variant has no generated lowering recipe",
-                );
-            }
-        };
-        convert_generated_scalar_arithmetic(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            recipe.0,
-            recipe.1,
-            recipe.2,
-            recipe.3,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ScalarMathOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let recipe = match (
-            self.get_attr_nvvm_scalar_math_format(ctx).as_deref(),
-            self.get_attr_nvvm_scalar_math_operation(ctx).as_deref(),
-            self.get_attr_nvvm_scalar_math_precision(ctx).as_deref(),
-            self.get_attr_nvvm_scalar_math_subnormal(ctx).as_deref(),
-        ) {
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Cos),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => (
-                "llvm_nvvm_cos_approx_f",
-                "cos.approx.f32",
-                false,
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Cos),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_cos_approx_ftz_f",
-                "cos.approx.ftz.f32",
-                false,
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F16),
-                Some(&ScalarMathOperationAttr::Ex2),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_ex2_approx", "ex2.approx.f16", true, false, true),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Ex2),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_ex2_approx", "ex2.approx.f32", false, false, true),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Ex2),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_ex2_approx_ftz",
-                "ex2.approx.ftz.f32",
-                false,
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Lg2),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => (
-                "llvm_nvvm_lg2_approx_f",
-                "lg2.approx.f32",
-                false,
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Lg2),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_lg2_approx_ftz_f",
-                "lg2.approx.ftz.f32",
-                false,
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_rcp_approx_ftz_f",
-                "rcp.approx.ftz.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F64),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_rcp_approx_ftz_d",
-                "rcp.approx.ftz.f64",
-                false,
-                true,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rm),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_rcp_rm_f", "rcp.rm.f32", false, false, false),
-            (
-                Some(&ScalarMathFormatAttr::F64),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rm),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_rcp_rm_d", "rcp.rm.f64", false, true, false),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rm),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_rcp_rm_ftz_f",
-                "rcp.rm.ftz.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rn),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_rcp_rn_f", "rcp.rn.f32", false, false, false),
-            (
-                Some(&ScalarMathFormatAttr::F64),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rn),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_rcp_rn_d", "rcp.rn.f64", false, true, false),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rn),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_rcp_rn_ftz_f",
-                "rcp.rn.ftz.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rp),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_rcp_rp_f", "rcp.rp.f32", false, false, false),
-            (
-                Some(&ScalarMathFormatAttr::F64),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rp),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_rcp_rp_d", "rcp.rp.f64", false, true, false),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rp),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_rcp_rp_ftz_f",
-                "rcp.rp.ftz.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rz),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_rcp_rz_f", "rcp.rz.f32", false, false, false),
-            (
-                Some(&ScalarMathFormatAttr::F64),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rz),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_rcp_rz_d", "rcp.rz.f64", false, true, false),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rcp),
-                Some(&ScalarMathPrecisionAttr::Rz),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_rcp_rz_ftz_f",
-                "rcp.rz.ftz.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rsqrt),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => (
-                "llvm_nvvm_rsqrt_approx_f",
-                "rsqrt.approx.f32",
-                false,
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F64),
-                Some(&ScalarMathOperationAttr::Rsqrt),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => (
-                "llvm_nvvm_rsqrt_approx_d",
-                "rsqrt.approx.f64",
-                false,
-                true,
-                true,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Rsqrt),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_rsqrt_approx_ftz_f",
-                "rsqrt.approx.ftz.f32",
-                false,
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sin),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => (
-                "llvm_nvvm_sin_approx_f",
-                "sin.approx.f32",
-                false,
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sin),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_sin_approx_ftz_f",
-                "sin.approx.ftz.f32",
-                false,
-                false,
-                true,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => (
-                "llvm_nvvm_sqrt_approx_f",
-                "sqrt.approx.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_sqrt_approx_ftz_f",
-                "sqrt.approx.ftz.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rm),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_sqrt_rm_f", "sqrt.rm.f32", false, false, false),
-            (
-                Some(&ScalarMathFormatAttr::F64),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rm),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_sqrt_rm_d", "sqrt.rm.f64", false, true, false),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rm),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_sqrt_rm_ftz_f",
-                "sqrt.rm.ftz.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rn),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_sqrt_rn_f", "sqrt.rn.f32", false, false, false),
-            (
-                Some(&ScalarMathFormatAttr::F64),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rn),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_sqrt_rn_d", "sqrt.rn.f64", false, true, false),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rn),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_sqrt_rn_ftz_f",
-                "sqrt.rn.ftz.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rp),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_sqrt_rp_f", "sqrt.rp.f32", false, false, false),
-            (
-                Some(&ScalarMathFormatAttr::F64),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rp),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_sqrt_rp_d", "sqrt.rp.f64", false, true, false),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rp),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_sqrt_rp_ftz_f",
-                "sqrt.rp.ftz.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rz),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_sqrt_rz_f", "sqrt.rz.f32", false, false, false),
-            (
-                Some(&ScalarMathFormatAttr::F64),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rz),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("llvm_nvvm_sqrt_rz_d", "sqrt.rz.f64", false, true, false),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Sqrt),
-                Some(&ScalarMathPrecisionAttr::Rz),
-                Some(&ScalarMathSubnormalAttr::Ftz),
-            ) => (
-                "llvm_nvvm_sqrt_rz_ftz_f",
-                "sqrt.rz.ftz.f32",
-                false,
-                false,
-                false,
-            ),
-            (
-                Some(&ScalarMathFormatAttr::F32),
-                Some(&ScalarMathOperationAttr::Tanh),
-                Some(&ScalarMathPrecisionAttr::Approx),
-                Some(&ScalarMathSubnormalAttr::Preserve),
-            ) => ("", "tanh.approx.f32", false, false, true),
-            _ => {
-                return pliron::input_err!(
-                    self.get_operation().deref(ctx).loc(),
-                    "nvvm.scalar_math variant has no generated lowering recipe",
-                );
-            }
-        };
-        convert_generated_scalar_math(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            recipe.0,
-            recipe.1,
-            recipe.2,
-            recipe.3,
-            recipe.4,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ExtendedMinMaxOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let recipe = match (
-            self.get_attr_nvvm_extended_minmax_format(ctx).as_deref(),
-            self.get_attr_nvvm_extended_minmax_operation(ctx).as_deref(),
-            self.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref(),
-            self.get_attr_nvvm_extended_minmax_nan(ctx).as_deref(),
-            self.get_attr_nvvm_extended_minmax_xorsign_abs(ctx)
-                .as_deref(),
-        ) {
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("max.bf16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("max.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("max.ftz.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("max.ftz.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("max.ftz.NaN.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("max.ftz.NaN.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.ftz.NaN.xorsign.abs.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.ftz.NaN.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F32),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.ftz.NaN.xorsign.abs.f32", MinMaxCarrier::F32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.ftz.xorsign.abs.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.ftz.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F32),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.ftz.xorsign.abs.f32", MinMaxCarrier::F32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("max.NaN.bf16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("max.NaN.bf16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("max.NaN.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("max.NaN.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.NaN.xorsign.abs.bf16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.NaN.xorsign.abs.bf16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.NaN.xorsign.abs.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.NaN.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F32),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.NaN.xorsign.abs.f32", MinMaxCarrier::F32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.xorsign.abs.bf16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.xorsign.abs.bf16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.xorsign.abs.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F32),
-                Some(&ExtendedMinMaxOperationAttr::Max),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("max.xorsign.abs.f32", MinMaxCarrier::F32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("min.bf16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("min.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("min.ftz.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("min.ftz.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("min.ftz.NaN.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("min.ftz.NaN.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.ftz.NaN.xorsign.abs.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.ftz.NaN.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F32),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.ftz.NaN.xorsign.abs.f32", MinMaxCarrier::F32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.ftz.xorsign.abs.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.ftz.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F32),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.ftz.xorsign.abs.f32", MinMaxCarrier::F32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("min.NaN.bf16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("min.NaN.bf16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("min.NaN.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
-            ) => ("min.NaN.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.NaN.xorsign.abs.bf16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.NaN.xorsign.abs.bf16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.NaN.xorsign.abs.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.NaN.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F32),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Nan),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.NaN.xorsign.abs.f32", MinMaxCarrier::F32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.xorsign.abs.bf16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.xorsign.abs.bf16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.xorsign.abs.f16", MinMaxCarrier::Half16),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F16x2),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
-            (
-                Some(&ExtendedMinMaxFormatAttr::F32),
-                Some(&ExtendedMinMaxOperationAttr::Min),
-                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
-                Some(&ExtendedMinMaxNanAttr::Number),
-                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
-            ) => ("min.xorsign.abs.f32", MinMaxCarrier::F32),
-            _ => {
-                return pliron::input_err!(
-                    self.get_operation().deref(ctx).loc(),
-                    "nvvm.extended_minmax variant has no generated lowering recipe",
-                );
-            }
-        };
-        convert_generated_extended_minmax(ctx, rewriter, self.get_operation(), recipe.0, recipe.1)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ClusterBarrierOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let recipe = match self.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() {
-            Some(&ClusterBarrierModeAttr::Arrive) => (
-                "llvm_nvvm_barrier_cluster_arrive",
-                "barrier.cluster.arrive;",
-            ),
-            Some(&ClusterBarrierModeAttr::ArriveAligned) => (
-                "llvm_nvvm_barrier_cluster_arrive_aligned",
-                "barrier.cluster.arrive.aligned;",
-            ),
-            Some(&ClusterBarrierModeAttr::ArriveRelaxed) => (
-                "llvm_nvvm_barrier_cluster_arrive_relaxed",
-                "barrier.cluster.arrive.relaxed;",
-            ),
-            Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned) => (
-                "llvm_nvvm_barrier_cluster_arrive_relaxed_aligned",
-                "barrier.cluster.arrive.relaxed.aligned;",
-            ),
-            Some(&ClusterBarrierModeAttr::Wait) => {
-                ("llvm_nvvm_barrier_cluster_wait", "barrier.cluster.wait;")
-            }
-            Some(&ClusterBarrierModeAttr::WaitAligned) => (
-                "llvm_nvvm_barrier_cluster_wait_aligned",
-                "barrier.cluster.wait.aligned;",
-            ),
-            _ => {
-                return pliron::input_err!(
-                    self.get_operation().deref(ctx).loc(),
-                    "nvvm.cluster_barrier mode has no generated lowering recipe",
-                );
-            }
-        };
-        let op = self.get_operation();
-        let void_ty = llvm_types::VoidType::get(ctx);
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => {
-                let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);
-                call_intrinsic(ctx, rewriter, op, recipe.0, function_ty, vec![])?;
-            }
-            IntrinsicBackend::LibNvvm => {
-                inline_asm_convergent(
-                    ctx,
-                    rewriter,
-                    op,
-                    void_ty.into(),
-                    vec![],
-                    recipe.1,
-                    "~{memory}",
-                );
-            }
-        }
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ClusterSyncOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let void_ty = llvm_types::VoidType::get(ctx);
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => {
-                let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);
-                call_intrinsic(
-                    ctx,
-                    rewriter,
-                    op,
-                    "llvm_nvvm_barrier_cluster_arrive_aligned",
-                    function_ty,
-                    vec![],
-                )?;
-                call_intrinsic(
-                    ctx,
-                    rewriter,
-                    op,
-                    "llvm_nvvm_barrier_cluster_wait_aligned",
-                    function_ty,
-                    vec![],
-                )?;
-            }
-            IntrinsicBackend::LibNvvm => {
-                inline_asm_convergent(
-                    ctx,
-                    rewriter,
-                    op,
-                    void_ty.into(),
-                    vec![],
-                    "barrier.cluster.arrive.aligned; barrier.cluster.wait.aligned;",
-                    "~{memory}",
-                );
-            }
-        }
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-fn convert_generated_wgmma_control(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    intrinsic_name: &str,
-    ptx: &str,
-    has_immediate: bool,
-) -> Result<()> {
-    let operands: Vec<_> = op.deref(ctx).operands().collect();
-    if operands.len() != usize::from(has_immediate) {
-        return pliron::input_err!(
-            op.deref(ctx).loc(),
-            "generated WGMMA control has the wrong operand count",
-        );
-    }
-    let void_ty = llvm_types::VoidType::get(ctx);
-    match context::lowering_options(ctx).intrinsic_backend {
-        IntrinsicBackend::LlvmNvptx => {
-            let arguments = if has_immediate {
-                vec![IntegerType::get(ctx, 64, Signedness::Signless).into()]
-            } else {
-                vec![]
-            };
-            let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), arguments, false);
-            call_intrinsic(ctx, rewriter, op, intrinsic_name, function_ty, operands)?;
-        }
-        IntrinsicBackend::LibNvvm => {
-            let constraints = if has_immediate {
-                "n,~{memory}"
-            } else {
-                "~{memory}"
-            };
-            inline_asm_convergent(
-                ctx,
-                rewriter,
-                op,
-                void_ty.into(),
-                operands,
-                ptx,
-                constraints,
-            );
-        }
-    }
-    rewriter.erase_operation(ctx, op);
-    Ok(())
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for WgmmaCommitGroupSyncAlignedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_wgmma_control(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "llvm__nvvm_dwgmma_dcommit_ugroup_dsync_daligned",
-            "wgmma.commit_group.sync.aligned;",
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for WgmmaFenceSyncAlignedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_wgmma_control(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "llvm_nvvm_wgmma_fence_sync_aligned",
-            "wgmma.fence.sync.aligned;",
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for WgmmaWaitGroupSyncAlignedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_wgmma_control(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "llvm__nvvm_dwgmma_dwait_ugroup_dsync_daligned",
-            "wgmma.wait_group.sync.aligned $0;",
-            true,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for PackedAtomicAddOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let format = self.get_attr_nvvm_packed_atomic_format(ctx);
-        let state_space = self.get_attr_nvvm_packed_atomic_state_space(ctx);
-        let ordering = self.get_attr_nvvm_packed_atomic_ordering(ctx);
-        let scope = self.get_attr_nvvm_packed_atomic_scope(ctx);
-        let rounding = self.get_attr_nvvm_packed_atomic_rounding(ctx);
-        let subnormal = self.get_attr_nvvm_packed_atomic_subnormal(ctx);
-        let atomicity = self.get_attr_nvvm_packed_atomic_atomicity(ctx);
-        let ptx_type = match (
-            format.as_deref(),
-            state_space.as_deref(),
-            ordering.as_deref(),
-            scope.as_deref(),
-            rounding.as_deref(),
-            subnormal.as_deref(),
-            atomicity.as_deref(),
-        ) {
-            (
-                Some(&PackedAtomicFormatAttr::F16x2),
-                Some(&PackedAtomicStateSpaceAttr::Global),
-                Some(&PackedAtomicOrderingAttr::Relaxed),
-                Some(&PackedAtomicScopeAttr::Gpu),
-                Some(&PackedAtomicRoundingAttr::Rn),
-                Some(&PackedAtomicSubnormalAttr::NoFtz),
-                Some(&PackedAtomicAtomicityAttr::PerElement),
-            ) => "f16x2",
-            (
-                Some(&PackedAtomicFormatAttr::Bf16x2),
-                Some(&PackedAtomicStateSpaceAttr::Global),
-                Some(&PackedAtomicOrderingAttr::Relaxed),
-                Some(&PackedAtomicScopeAttr::Gpu),
-                Some(&PackedAtomicRoundingAttr::Rn),
-                Some(&PackedAtomicSubnormalAttr::NoFtz),
-                Some(&PackedAtomicAtomicityAttr::PerElement),
-            ) => "bf16x2",
-            _ => {
-                return pliron::input_err!(
-                    self.get_operation().deref(ctx).loc(),
-                    "nvvm.packed_atomic_add attributes have no generated lowering recipe",
-                );
-            }
-        };
-        drop((
-            format,
-            state_space,
-            ordering,
-            scope,
-            rounding,
-            subnormal,
-            atomicity,
-        ));
-        convert_packed_atom_add(ctx, rewriter, self.get_operation(), ptx_type)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for NvvmAtomAddF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_packed_atom_add(ctx, rewriter, self.get_operation(), "f16x2")
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for NvvmAtomAddBf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_packed_atom_add(ctx, rewriter, self.get_operation(), "bf16x2")
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncAddOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_add",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncAndOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_and",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncFmaxAbsOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_fmax_abs",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncFmaxAbsNanOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_fmax_abs_NaN",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncFmaxOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_fmax",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncMaxOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_max",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncFmaxNanOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_fmax_NaN",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncUmaxOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_umax",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncFminAbsOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_fmin_abs",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncFminAbsNanOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_fmin_abs_NaN",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncFminOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_fmin",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncMinOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_min",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncFminNanOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_fmin_NaN",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncUminOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_umin",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncOrOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_or",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReduxSyncXorOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_redux(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_redux_sync_xor",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for VoteSyncAllOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_vote(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_vote_all_sync",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for VoteSyncAnyOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_vote(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_vote_any_sync",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for VoteSyncBallotOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_vote(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_vote_ballot_sync",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for VoteSyncUniOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_vote(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_vote_uni_sync",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MatchAllSyncI64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let value_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-        convert_match_all(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_match_all_sync_i64p",
-            value_ty.into(),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MatchAllSyncI32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let value_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-        convert_match_all(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_match_all_sync_i32p",
-            value_ty.into(),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MatchAnySyncI64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let value_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-        convert_match_any(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_match_any_sync_i64",
-            value_ty.into(),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MatchAnySyncI32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let value_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-        convert_match_any(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_match_any_sync_i32",
-            value_ty.into(),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ElectSyncOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => convert_elect_sync_typed(
-                ctx,
-                rewriter,
-                self.get_operation(),
-                operands_info,
-                "llvm_nvvm_elect_sync",
-            ),
-            IntrinsicBackend::LibNvvm => {
-                convert_elect_sync_inline(ctx, rewriter, self.get_operation(), operands_info)
-            }
-        }
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for BarWarpSyncOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_bar_warp_sync(ctx, rewriter, self.get_operation(), operands_info)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncDownF32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_f32(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_shfl_sync_down_f32",
-            31,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncDownI32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_i32(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_shfl_sync_down_i32",
-            31,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncDownI64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_i64(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "down",
-            31,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncIdxF32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_f32(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_shfl_sync_idx_f32",
-            31,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncIdxI32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_i32(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_shfl_sync_idx_i32",
-            31,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncIdxI64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_i64(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "idx",
-            31,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncUpF32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_f32(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_shfl_sync_up_f32",
-            0,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncUpI32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_i32(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_shfl_sync_up_i32",
-            0,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncUpI64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_i64(ctx, rewriter, self.get_operation(), operands_info, "up", 0)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncBflyF32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_f32(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_shfl_sync_bfly_f32",
-            31,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncBflyI32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_i32(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_shfl_sync_bfly_i32",
-            31,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ShflSyncBflyI64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_shuffle_i64(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "bfly",
-            31,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for AbsBf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "abs.bf16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for AbsF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "abs.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for AddBf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "add.rn.bf16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for AddF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "add.rn.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for AddF32x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "add.rn.f32x2", 64)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for AddFtzF32x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "add.rn.ftz.f32x2", 64)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FmaBf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.bf16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FmaF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FmaF32x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.f32x2", 64)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FmaFtzF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.ftz.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FmaFtzF32x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.ftz.f32x2", 64)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FmaFtzReluF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "fma.rn.ftz.relu.f16x2",
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FmaFtzSatF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "fma.rn.ftz.sat.f16x2",
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FmaReluBf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "fma.rn.relu.bf16x2",
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FmaReluF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.relu.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FmaSatF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.sat.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MaxBf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "max.bf16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MaxF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "max.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MinBf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "min.bf16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MinF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "min.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MulBf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "mul.rn.bf16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MulF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "mul.rn.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MulF32x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "mul.rn.f32x2", 64)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MulFtzF32x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "mul.rn.ftz.f32x2", 64)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for NegBf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "neg.bf16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for NegF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "neg.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for SubBf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "sub.rn.bf16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for SubF16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "sub.rn.f16x2", 32)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for SubF32x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "sub.rn.f32x2", 64)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for SubFtzF32x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "sub.rn.ftz.f32x2", 64)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MaxReluS16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "max.relu.s16x2")
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MaxReluS32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "max.relu.s32")
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MaxS16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "max.s16x2")
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MaxU16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "max.u16x2")
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MinReluS16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "min.relu.s16x2")
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MinReluS32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "min.relu.s32")
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MinS16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "min.s16x2")
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MinU16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "min.u16x2")
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtF16x2F32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_f32x2(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            None,
-            "cvt.rn.f16x2.f32",
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtF32x2Bf16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_f32x2(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            None,
-            "cvt.rn.bf16x2.f32",
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnF16x2E4m3x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_unary(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "cvt.rn.f16x2.e4m3x2",
-            32,
-            16,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnF16x2E5m2x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_unary(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "cvt.rn.f16x2.e5m2x2",
-            32,
-            16,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnReluBf16x2F32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_f32x2(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            None,
-            "cvt.rn.relu.bf16x2.f32",
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnReluF16x2E4m3x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_unary(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "cvt.rn.relu.f16x2.e4m3x2",
-            32,
-            16,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnReluF16x2E5m2x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_unary(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "cvt.rn.relu.f16x2.e5m2x2",
-            32,
-            16,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnReluF16x2F32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_f32x2(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            None,
-            "cvt.rn.relu.f16x2.f32",
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnSatfiniteE4m3x2F16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_unary(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "cvt.rn.satfinite.e4m3x2.f16x2",
-            16,
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnSatfiniteE4m3x2F32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_f32x2(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            Some("llvm_nvvm_ff_to_e4m3x2_rn"),
-            "cvt.rn.satfinite.e4m3x2.f32",
-            16,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnSatfiniteE5m2x2F16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_unary(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "cvt.rn.satfinite.e5m2x2.f16x2",
-            16,
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnSatfiniteE5m2x2F32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_f32x2(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            Some("llvm_nvvm_ff_to_e5m2x2_rn"),
-            "cvt.rn.satfinite.e5m2x2.f32",
-            16,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnSatfiniteReluE4m3x2F16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_unary(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "cvt.rn.satfinite.relu.e4m3x2.f16x2",
-            16,
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnSatfiniteReluE4m3x2F32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_f32x2(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            Some("llvm_nvvm_ff_to_e4m3x2_rn_relu"),
-            "cvt.rn.satfinite.relu.e4m3x2.f32",
-            16,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnSatfiniteReluE5m2x2F16x2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_unary(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "cvt.rn.satfinite.relu.e5m2x2.f16x2",
-            16,
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRnSatfiniteReluE5m2x2F32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_f32x2(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            Some("llvm_nvvm_ff_to_e5m2x2_rn_relu"),
-            "cvt.rn.satfinite.relu.e5m2x2.f32",
-            16,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRzBf16x2F32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_f32x2(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            None,
-            "cvt.rz.bf16x2.f32",
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CvtRzF16x2F32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_packed_f32x2(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            None,
-            "cvt.rz.f16x2.f32",
-            32,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncCa16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_copy(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "ca",
-            16,
-            false,
-            "llvm_nvvm_cp_async_ca_shared_global_16",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncCa4Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_copy(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "ca",
-            4,
-            false,
-            "llvm_nvvm_cp_async_ca_shared_global_4",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncCa8Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_copy(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "ca",
-            8,
-            false,
-            "llvm_nvvm_cp_async_ca_shared_global_8",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncCaZfill16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_copy(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "ca",
-            16,
-            true,
-            "llvm_nvvm_cp_async_ca_shared_global_16_s",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncCaZfill4Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_copy(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "ca",
-            4,
-            true,
-            "llvm_nvvm_cp_async_ca_shared_global_4_s",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncCaZfill8Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_copy(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "ca",
-            8,
-            true,
-            "llvm_nvvm_cp_async_ca_shared_global_8_s",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncCg16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_copy(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "cg",
-            16,
-            false,
-            "llvm_nvvm_cp_async_cg_shared_global_16",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncCgZfill16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_copy(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "cg",
-            16,
-            true,
-            "llvm_nvvm_cp_async_cg_shared_global_16_s",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncCommitGroupOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_control(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "commit_group",
-            "llvm_nvvm_cp_async_commit_group",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncWaitAllOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_control(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "wait_all",
-            "llvm_nvvm_cp_async_wait_all",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncWaitGroupOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_control(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "wait_group",
-            "llvm_nvvm_cp_async_wait_group",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncMbarrierArriveOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_mbarrier(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "arrive",
-            "generic",
-            "llvm_nvvm_cp_async_mbarrier_arrive",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncMbarrierArriveNoIncOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_mbarrier(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "arrive_no_inc",
-            "generic",
-            "llvm_nvvm_cp_async_mbarrier_arrive_noinc",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncMbarrierArriveNoIncSharedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_mbarrier(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "arrive_no_inc",
-            "shared",
-            "llvm_nvvm_cp_async_mbarrier_arrive_noinc_shared",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncMbarrierArriveSharedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_cp_async_mbarrier(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "arrive",
-            "shared",
-            "llvm_nvvm_cp_async_mbarrier_arrive_shared",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MbarrierArriveSharedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_arrive(ctx, rewriter, self.get_operation(), operands_info)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MbarrierInitSharedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_init(ctx, rewriter, self.get_operation(), operands_info)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MbarrierInvalSharedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_inval(ctx, rewriter, self.get_operation(), operands_info)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MbarrierTestWaitSharedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_test_wait(ctx, rewriter, self.get_operation(), operands_info)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for DsmemReadU32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let operands: Vec<_> = op.deref(ctx).operands().collect();
-        if operands.len() != 2 {
-            return pliron::input_err_noloc!(
-                "dsmem_read_u32 requires 2 operands, got {}",
-                operands.len()
-            );
-        }
-        let shared_pointer = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
-        let rank = operands[1];
-        let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-        let asm = inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            i32_ty.into(),
-            vec![shared_pointer, rank],
-            "{ .reg .u64 %mapped; mapa.shared::cluster.u64 %mapped, $1, $2; ld.shared::cluster.u32 $0, [%mapped]; }",
-            "=r,l,r,~{memory}",
-        );
-        rewriter.replace_operation(ctx, op, asm);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MapaSharedClusterOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let operands: Vec<_> = op.deref(ctx).operands().collect();
-        if operands.len() != 2 {
-            return pliron::input_err_noloc!(
-                "map_shared_rank requires 2 operands, got {}",
-                operands.len()
-            );
-        }
-        let shared_pointer = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
-        let rank = operands[1];
-        let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-        let asm = inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            i64_ty.into(),
-            vec![shared_pointer, rank],
-            "mapa.shared::cluster.u64 $0, $1, $2;",
-            "=l,l,r",
-        );
-        let mapped = asm.deref(ctx).get_result(0);
-        let cluster_shared_pointer_ty = llvm_types::PointerType::get(ctx, 7);
-        let int_to_ptr = llvm_ops::IntToPtrOp::new(ctx, mapped, cluster_shared_pointer_ty.into());
-        rewriter.insert_operation(ctx, int_to_ptr.get_operation());
-        rewriter.replace_operation(ctx, op, int_to_ptr.get_operation());
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceMbarrierInitReleaseClusterOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let operands: Vec<_> = op.deref(ctx).operands().collect();
-        if !operands.is_empty() {
-            return pliron::input_err_noloc!(
-                "fence_mbarrier_init_release_cluster requires 0 operands, got {}",
-                operands.len()
-            );
-        }
-        let void_ty = llvm_types::VoidType::get(ctx);
-        inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            void_ty.into(),
-            operands,
-            "fence.mbarrier_init.release.cluster;",
-            "~{memory}",
-        );
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyAsyncGenericAcquireSharedClusterClusterOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let operands: Vec<_> = op.deref(ctx).operands().collect();
-        if !operands.is_empty() {
-            return pliron::input_err_noloc!(
-                "fence_proxy_async_generic_acquire_shared_cluster_cluster requires 0 operands, got {}",
-                operands.len()
-            );
-        }
-        let void_ty = llvm_types::VoidType::get(ctx);
-        inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            void_ty.into(),
-            operands,
-            "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;",
-            "~{memory}",
-        );
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyAsyncGenericReleaseSharedCtaClusterOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let operands: Vec<_> = op.deref(ctx).operands().collect();
-        if !operands.is_empty() {
-            return pliron::input_err_noloc!(
-                "fence_proxy_async_generic_release_shared_cta_cluster requires 0 operands, got {}",
-                operands.len()
-            );
-        }
-        let void_ty = llvm_types::VoidType::get(ctx);
-        inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            void_ty.into(),
-            operands,
-            "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
-            "~{memory}",
-        );
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyAsyncSharedCtaOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let operands: Vec<_> = op.deref(ctx).operands().collect();
-        if !operands.is_empty() {
-            return pliron::input_err_noloc!(
-                "fence_proxy_async_shared_cta requires 0 operands, got {}",
-                operands.len()
-            );
-        }
-        let void_ty = llvm_types::VoidType::get(ctx);
-        inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            void_ty.into(),
-            operands,
-            "fence.proxy.async.shared::cta;",
-            "~{memory}",
-        );
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MbarrierArriveClusterOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let operands: Vec<_> = op.deref(ctx).operands().collect();
-        if operands.len() != 1 {
-            return pliron::input_err_noloc!(
-                "mbarrier_arrive_cluster requires 1 operands, got {}",
-                operands.len()
-            );
-        }
-        let void_ty = llvm_types::VoidType::get(ctx);
-        inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            void_ty.into(),
-            operands,
-            "mbarrier.arrive.release.cluster.shared::cluster.b64 _, [$0];",
-            "l,~{memory}",
-        );
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MbarrierArriveExpectTxSharedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let mut operands: Vec<_> = op.deref(ctx).operands().collect();
-        if operands.len() != 2 {
-            return pliron::input_err_noloc!(
-                "mbarrier_arrive_expect_tx requires 2 operands, got {}",
-                operands.len()
-            );
-        }
-        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
-        let result_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-        let asm = inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            result_ty.into(),
-            operands,
-            "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 $0, [$1], $2;",
-            "=l,l,r,~{memory}",
-        );
-        rewriter.replace_operation(ctx, op, asm);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MbarrierArriveExpectTxClusterOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let mut operands: Vec<_> = op.deref(ctx).operands().collect();
-        if operands.len() != 2 {
-            return pliron::input_err_noloc!(
-                "mbarrier_arrive_expect_tx_cluster requires 2 operands, got {}",
-                operands.len()
-            );
-        }
-        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
-        let result_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-        let asm = inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            result_ty.into(),
-            operands,
-            "mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 $0, [$1], $2;",
-            "=l,l,r,~{memory}",
-        );
-        rewriter.replace_operation(ctx, op, asm);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MbarrierTryWaitSharedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let mut operands: Vec<_> = op.deref(ctx).operands().collect();
-        if operands.len() != 2 {
-            return pliron::input_err_noloc!(
-                "mbarrier_try_wait requires 2 operands, got {}",
-                operands.len()
-            );
-        }
-        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
-        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-        let asm = inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            result_ty.into(),
-            operands,
-            "{ .reg .pred %p0; mbarrier.try_wait.shared.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
-            "=r,l,l,~{memory}",
-        );
-        let asm_result = asm.deref(ctx).get_result(0);
-        let result = trunc_to_i1(ctx, rewriter, asm_result);
-        let DefiningEntity::Op(result_op) = result.defining_entity() else {
-            unreachable!()
-        };
-        rewriter.replace_operation(ctx, op, result_op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MbarrierTryWaitParitySharedOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let mut operands: Vec<_> = op.deref(ctx).operands().collect();
-        if operands.len() != 2 {
-            return pliron::input_err_noloc!(
-                "mbarrier_try_wait_parity requires 2 operands, got {}",
-                operands.len()
-            );
-        }
-        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
-        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-        let asm = inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            result_ty.into(),
-            operands,
-            "{ .reg .pred %p0; mbarrier.try_wait.parity.shared::cta.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
-            "=r,l,r,~{memory}",
-        );
-        let asm_result = asm.deref(ctx).get_result(0);
-        let result = trunc_to_i1(ctx, rewriter, asm_result);
-        let DefiningEntity::Op(result_op) = result.defining_entity() else {
-            unreachable!()
-        };
-        rewriter.replace_operation(ctx, op, result_op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for MbarrierTryWaitParityClusterOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let mut operands: Vec<_> = op.deref(ctx).operands().collect();
-        if operands.len() != 2 {
-            return pliron::input_err_noloc!(
-                "mbarrier_try_wait_parity_cluster requires 2 operands, got {}",
-                operands.len()
-            );
-        }
-        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
-        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-        let asm = inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            result_ty.into(),
-            operands,
-            "{ .reg .pred %p0; mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
-            "=r,l,r,~{memory}",
-        );
-        let asm_result = asm.deref(ctx).get_result(0);
-        let result = trunc_to_i1(ctx, rewriter, asm_result);
-        let DefiningEntity::Op(result_op) = result.defining_entity() else {
-            unreachable!()
-        };
-        rewriter.replace_operation(ctx, op, result_op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for NanosleepOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let operands: Vec<_> = op.deref(ctx).operands().collect();
-        if operands.len() != 1 {
-            return pliron::input_err_noloc!(
-                "nanosleep requires 1 operands, got {}",
-                operands.len()
-            );
-        }
-        let void_ty = llvm_types::VoidType::get(ctx);
-        inline_asm_convergent(
-            ctx,
-            rewriter,
-            op,
-            void_ty.into(),
-            operands,
-            "nanosleep.u32 $0;",
-            "r,~{memory}",
-        );
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Dp2aS32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_dot_product(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "llvm_nvvm_idp2a_s_s",
-            "dp2a.lo.s32.s32 $0, $1, $2, $3;",
-            true,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Dp2aU32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_dot_product(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "llvm_nvvm_idp2a_u_u",
-            "dp2a.lo.u32.u32 $0, $1, $2, $3;",
-            true,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Dp4aS32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_dot_product(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "llvm_nvvm_idp4a_s_s",
-            "dp4a.s32.s32 $0, $1, $2, $3;",
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Dp4aU32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_dot_product(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            "llvm_nvvm_idp4a_u_u",
-            "dp4a.u32.u32 $0, $1, $2, $3;",
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ClcQueryGetFirstCtaidXOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_clc_query(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dclusterlaunchcontrol_dquery_ucancel_dget_ufirst_uctaid_dx",
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ClcQueryGetFirstCtaidYOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_clc_query(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dclusterlaunchcontrol_dquery_ucancel_dget_ufirst_uctaid_dy",
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ClcQueryGetFirstCtaidZOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_clc_query(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dclusterlaunchcontrol_dquery_ucancel_dget_ufirst_uctaid_dz",
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ClcQueryIsCanceledOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_clc_query(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dclusterlaunchcontrol_dquery_ucancel_dis_ucanceled",
-            true,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ClcTryCancelOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_clc_try_cancel(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dclusterlaunchcontrol_dtry_ucancel_dasync_dshared",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ClcTryCancelMulticastOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_clc_try_cancel(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dclusterlaunchcontrol_dtry_ucancel_dasync_dmulticast_dshared",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for BarrierCtaArriveCountOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_counted_barrier(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_barrier_cta_arrive_count",
-            "barrier.arrive $0, $1;",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for BarrierCtaArriveAlignedCountOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_counted_barrier(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_barrier_cta_arrive_aligned_count",
-            "bar.arrive $0, $1;",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for BarrierCtaSyncCountOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_counted_barrier(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_barrier_cta_sync_count",
-            "barrier.sync $0, $1;",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for BarrierCtaSyncAlignedCountOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_counted_barrier(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_barrier_cta_sync_aligned_count",
-            "bar.sync $0, $1;",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for GridDependencyLaunchDependentsOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_grid_dependency(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_griddepcontrol_launch_dependents",
-            "griddepcontrol.launch_dependents;",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for GridDependencyWaitOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_grid_dependency(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_griddepcontrol_wait",
-            "griddepcontrol.wait;",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for SetMaxNRegDecOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let register_count = self.register_count(ctx).ok_or_else(|| {
-            pliron::input_error_noloc!("setmaxnreg register-count attribute is invalid")
-        })?;
-        convert_setmaxnreg(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            register_count,
-            "llvm_nvvm_setmaxnreg_dec_sync_aligned_u32",
-            "dec",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for SetMaxNRegIncOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let register_count = self.register_count(ctx).ok_or_else(|| {
-            pliron::input_error_noloc!("setmaxnreg register-count attribute is invalid")
-        })?;
-        convert_setmaxnreg(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            register_count,
-            "llvm_nvvm_setmaxnreg_inc_sync_aligned_u32",
-            "inc",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkCommitGroupOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_control(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "commit_group",
-            "llvm_nvvm_cp_async_bulk_commit_group",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor1dL2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                1,
-                false,
-                false,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_1d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor1dL2CacheHintOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                1,
-                false,
-                true,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_1d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor2dL2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                2,
-                false,
-                false,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor2dL2CacheHintOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                2,
-                false,
-                true,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor3dL2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                3,
-                false,
-                false,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor3dL2CacheHintOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                3,
-                false,
-                true,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor4dL2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                4,
-                false,
-                false,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor4dL2CacheHintOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                4,
-                false,
-                true,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor5dL2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                5,
-                false,
-                false,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor5dL2CacheHintOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                5,
-                false,
-                true,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                5,
-                true,
-                false,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_gather4_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tile(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            PrefetchTileConfig::new(
-                5,
-                true,
-                true,
-                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_gather4_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile1dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 1, false)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorS2gTile1dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 1)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile2dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 2, false)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile2dMulticastOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 2, true)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile2dMulticastCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_g2s_multicast_cg2(ctx, rewriter, self.get_operation(), operands_info)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorS2gTile2dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 2)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 3, false)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorS2gTile3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 3)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 4, false)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorS2gTile4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 4)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 5, false)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorS2gTile5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 5)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddIm2col3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "add",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_im2col_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddIm2col4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "add",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_im2col_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddIm2col5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "add",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_im2col_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddTile1dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                1,
-                "add",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_1d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddTile2dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                2,
-                "add",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddTile3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "add",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddTile4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "add",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddTile5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "add",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndIm2col3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "and",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_im2col_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndIm2col4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "and",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_im2col_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndIm2col5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "and",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_im2col_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndTile1dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                1,
-                "and",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_tile_1d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndTile2dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                2,
-                "and",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_tile_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndTile3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "and",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_tile_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndTile4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "and",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_tile_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndTile5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "and",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_tile_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecIm2col3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "dec",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_im2col_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecIm2col4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "dec",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_im2col_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecIm2col5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "dec",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_im2col_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecTile1dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                1,
-                "dec",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_tile_1d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecTile2dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                2,
-                "dec",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_tile_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecTile3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "dec",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_tile_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecTile4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "dec",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_tile_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecTile5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "dec",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_tile_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncIm2col3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "inc",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_im2col_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncIm2col4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "inc",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_im2col_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncIm2col5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "inc",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_im2col_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncTile1dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                1,
-                "inc",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_tile_1d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncTile2dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                2,
-                "inc",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_tile_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncTile3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "inc",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_tile_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncTile4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "inc",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_tile_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncTile5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "inc",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_tile_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxIm2col3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "max",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_im2col_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxIm2col4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "max",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_im2col_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxIm2col5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "max",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_im2col_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxTile1dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                1,
-                "max",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_tile_1d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxTile2dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                2,
-                "max",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_tile_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxTile3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "max",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_tile_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxTile4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "max",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_tile_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxTile5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "max",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_tile_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinIm2col3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "min",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_im2col_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinIm2col4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "min",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_im2col_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinIm2col5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "min",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_im2col_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinTile1dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                1,
-                "min",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_tile_1d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinTile2dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                2,
-                "min",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_tile_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinTile3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "min",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_tile_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinTile4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "min",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_tile_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinTile5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "min",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_tile_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrIm2col3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "or",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_im2col_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrIm2col4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "or",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_im2col_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrIm2col5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "or",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_im2col_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrTile1dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                1,
-                "or",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_tile_1d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrTile2dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                2,
-                "or",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_tile_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrTile3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "or",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_tile_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrTile4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "or",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_tile_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrTile5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "or",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_tile_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorIm2col3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "xor",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_im2col_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorIm2col4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "xor",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_im2col_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorIm2col5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "xor",
-                "im2col",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_im2col_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorTile1dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                1,
-                "xor",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_tile_1d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorTile2dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                2,
-                "xor",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_tile_2d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorTile3dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                3,
-                "xor",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_tile_3d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorTile4dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                4,
-                "xor",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_tile_4d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorTile5dOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_reduce_s2g(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            ReduceConfig::new(
-                5,
-                "xor",
-                "tile",
-                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_tile_5d",
-            ),
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkWaitGroupOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_control(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "wait_group",
-            "llvm_nvvm_cp_async_bulk_wait_group",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for CpAsyncBulkWaitGroupReadOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_control(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "wait_group_read",
-            "llvm_nvvm_cp_async_bulk_wait_group_read",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyTensorMapGenericAcquireClusterOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_fence(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_dacquire_dcluster",
-            true,
-            "cluster",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyTensorMapGenericAcquireCtaOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_fence(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_dacquire_dcta",
-            true,
-            "cta",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyTensorMapGenericAcquireGpuOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_fence(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_dacquire_dgpu",
-            true,
-            "gpu",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyTensorMapGenericAcquireSystemOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_fence(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_dacquire_dsys",
-            true,
-            "sys",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyTensorMapGenericReleaseClusterOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_fence(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_drelease_dcluster",
-            false,
-            "cluster",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyTensorMapGenericReleaseCtaOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_fence(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_drelease_dcta",
-            false,
-            "cta",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyTensorMapGenericReleaseGpuOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_fence(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_drelease_dgpu",
-            false,
-            "gpu",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for FenceProxyTensorMapGenericReleaseSystemOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_fence(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_drelease_dsys",
-            false,
-            "sys",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for PrefetchTensorMapOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_prefetch_tensormap(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_prefetch_tensormap_p0",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapBoxDimOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_box_dim",
-            "box_dim",
-            "u32",
-            true,
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapElementStrideOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_element_stride",
-            "element_stride",
-            "u32",
-            true,
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapElementTypeOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_elemtype",
-            "elemtype",
-            "u32",
-            false,
-            true,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapFillModeOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_fill_mode",
-            "fill_mode",
-            "u32",
-            false,
-            true,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapGlobalAddressOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_global_address",
-            "global_address",
-            "address",
-            false,
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapGlobalDimOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_global_dim",
-            "global_dim",
-            "u32",
-            true,
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapGlobalStrideOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_global_stride",
-            "global_stride",
-            "u64",
-            true,
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapInterleaveLayoutOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_interleave_layout",
-            "interleave_layout",
-            "u32",
-            false,
-            true,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapRankOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_rank",
-            "rank",
-            "u32",
-            false,
-            false,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapSwizzleAtomicityOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_swizzle_atomicity",
-            "swizzle_atomicity",
-            "u32",
-            false,
-            true,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ReplaceTensorMapSwizzleModeOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_tensormap_replace(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            operands_info,
-            "llvm_nvvm_tensormap_replace_swizzle_mode",
-            "swizzle_mode",
-            "u32",
-            false,
-            true,
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05AllocOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "{ .reg .u64 %shared64; .reg .u32 %shared32; cvta.to.shared.u64 %shared64, $0; cvt.u32.u64 %shared32, %shared64; tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%shared32], $1; }",
-            "l,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05AllocCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "{ .reg .u64 %shared64; .reg .u32 %shared32; cvta.to.shared.u64 %shared64, $0; cvt.u32.u64 %shared32, %shared64; tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 [%shared32], $1; }",
-            "l,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05CommitOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            "tcgen05.commit.cta_group::1.mbarrier::arrive::one.b64 [$0];",
-            "r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05CommitCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            "tcgen05.commit.cta_group::2.mbarrier::arrive::one.b64 [$0];",
-            "r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05CommitMulticastOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;",
-            "r,h,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05CommitMulticastCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;",
-            "r,h,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05CommitSharedClusterOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [$0];",
-            "r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05CommitSharedClusterCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 [$0];",
-            "r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp128x128bOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.128x128b [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp128x128bB4x16P64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp128x128bB4x16P64Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp128x128bB6x16P32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp128x128bB6x16P32Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp128x128bCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.128x128b [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp128x256bB4x16P64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp128x256bB4x16P64Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp128x256bB6x16P32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp128x256bB6x16P32Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.32x128b.warpx4 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4B4x16P64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4B4x16P64Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4B6x16P32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4B6x16P32Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.32x128b.warpx4 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp4x256bOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.4x256b [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp4x256bB4x16P64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp4x256bB4x16P64Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp4x256bB6x16P32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp4x256bB6x16P32Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp4x256bCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.4x256b [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05CpSmemToTmemOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::1.128x256b [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05CpSmemToTmemCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.cp.cta_group::2.128x256b [$0], $1;",
-            "r,l,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05DeallocOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.dealloc.cta_group::1.sync.aligned.b32 $0, $1;",
-            "r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05DeallocCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.dealloc.cta_group::2.sync.aligned.b32 $0, $1;",
-            "r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05FenceAfterThreadSyncOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            0,
-            "tcgen05.fence::after_thread_sync;",
-            "~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05FenceBeforeThreadSyncOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            0,
-            "tcgen05.fence::before_thread_sync;",
-            "~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX16Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            32,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x16.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX16RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            32,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x16.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX1Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            2,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32 {$0,$1}, [$2];",
-            "=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX1RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            2,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x1.b32 {$0,$1}, [$2];",
-            "=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX2Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            4,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32 {$0,$1,$2,$3}, [$4];",
-            "=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX2RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            4,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x2.b32 {$0,$1,$2,$3}, [$4];",
-            "=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX32Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            64,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x32.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX32RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            64,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x32.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX4Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            8,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX4RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            8,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x4.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX64Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            128,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x64.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX64RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            128,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x64.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX8Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            16,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x8.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x128bX8RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            16,
-            true,
-            "tcgen05.ld.sync.aligned.16x128b.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bPureOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            4,
-            false,
-            "tcgen05.ld.sync.aligned.16x256b.x1.b32 {$0,$1,$2,$3}, [$4];",
-            "=f,=f,=f,=f,r",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX16Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            64,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX16RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            64,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x16.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX1Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            4,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32 {$0,$1,$2,$3}, [$4];",
-            "=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX1RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            4,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x1.b32 {$0,$1,$2,$3}, [$4];",
-            "=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX2Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            8,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX2RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            8,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x2.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX32Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            128,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x32.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX32RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            128,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x32.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX4Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            16,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX4RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            16,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x4.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX8Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            32,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX8PureOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            32,
-            false,
-            "tcgen05.ld.sync.aligned.16x256b.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
-            "=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,r",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x256bX8RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            32,
-            true,
-            "tcgen05.ld.sync.aligned.16x256b.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X128Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            128,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x128.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128], $129;",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X128RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            128,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x128.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128], $129;",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X16Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            16,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x16.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16], $17;",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X16RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            16,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x16.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16], $17;",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X1Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            1,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 {$0}, [$1], $2;",
-            "=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X1RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            1,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x1.b32 {$0}, [$1], $2;",
-            "=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X2Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            2,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32 {$0,$1}, [$2], $3;",
-            "=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X2RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            2,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x2.b32 {$0,$1}, [$2], $3;",
-            "=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X32Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            32,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x32.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32], $33;",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X32RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            32,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x32.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32], $33;",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X4Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            4,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32 {$0,$1,$2,$3}, [$4], $5;",
-            "=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X4RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            4,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x4.b32 {$0,$1,$2,$3}, [$4], $5;",
-            "=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X64Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            64,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x64.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64], $65;",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X64RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            64,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x64.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64], $65;",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X8Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            8,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x8.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8], $9;",
-            "=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x32bx2X8RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            8,
-            true,
-            "tcgen05.ld.sync.aligned.16x32bx2.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8], $9;",
-            "=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX128Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            128,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x128.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX128RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            128,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x128.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX16Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            16,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x16.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX16RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            16,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x16.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX1Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            1,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 {$0}, [$1];",
-            "=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX1RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            1,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x1.b32 {$0}, [$1];",
-            "=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX2Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            2,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32 {$0,$1}, [$2];",
-            "=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX2RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            2,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x2.b32 {$0,$1}, [$2];",
-            "=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX32Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            32,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x32.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX32RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            32,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x32.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX4Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            4,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32 {$0,$1,$2,$3}, [$4];",
-            "=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX4RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            4,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x4.b32 {$0,$1,$2,$3}, [$4];",
-            "=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX64Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            64,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x64.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX64RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            64,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x64.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX8Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            8,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x8.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld16x64bX8RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            8,
-            true,
-            "tcgen05.ld.sync.aligned.16x64b.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX128Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            128,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX128RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            128,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x128.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX16Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            16,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x16.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX16RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            16,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x16.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX1Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            1,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32 {$0}, [$1];",
-            "=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX1RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            1,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x1.b32 {$0}, [$1];",
-            "=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX2Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            2,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32 {$0,$1}, [$2];",
-            "=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX2RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            2,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x2.b32 {$0,$1}, [$2];",
-            "=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX32Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            32,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x32.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX32RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            32,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x32.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX4Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            4,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32 {$0,$1,$2,$3}, [$4];",
-            "=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX4RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            4,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x4.b32 {$0,$1,$2,$3}, [$4];",
-            "=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX64Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            64,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x64.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX64RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            64,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x64.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX8Pack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            8,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x8.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05Ld32x32bX8RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_load(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            8,
-            true,
-            "tcgen05.ld.sync.aligned.32x32b.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
-            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05LoadWaitOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            0,
-            "tcgen05.wait::ld.sync.aligned;",
-            "~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05MmaF16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            5,
-            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; .reg .u32 %z; mov.u32 %z, 0; tcgen05.mma.cta_group::1.kind::f16 [$0], $1, $2, $3, {%z, %z, %z, %z}, %enable_pred; }",
-            "r,l,l,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05MmaF16Cg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            5,
-            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; .reg .u32 %z; mov.u32 %z, 0; tcgen05.mma.cta_group::2.kind::f16 [$0], $1, $2, $3, {%z, %z, %z, %z, %z, %z, %z, %z}, %enable_pred; }",
-            "r,l,l,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05MmaWsBf16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            6,
-            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::f16 [$0], [$1], $3, $4, %enable_pred; }",
-            "r,r,l,l,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05MmaWsF16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            6,
-            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::f16 [$0], [$1], $3, $4, %enable_pred; }",
-            "r,r,l,l,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05MmaWsTf32Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            6,
-            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::tf32 [$0], [$1], $3, $4, %enable_pred; }",
-            "r,r,l,l,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05RelinquishAllocPermitOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            0,
-            "tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;",
-            "~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05RelinquishAllocPermitCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            0,
-            "tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;",
-            "~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05ShiftDownOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            "tcgen05.shift.cta_group::1.down [$0];",
-            "r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05ShiftDownCg2Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            1,
-            "tcgen05.shift.cta_group::2.down [$0];",
-            "r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX16RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            33,
-            "tcgen05.st.sync.aligned.16x128b.x16.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX16Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            33,
-            "tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX1RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            3,
-            "tcgen05.st.sync.aligned.16x128b.x1.b32 [$0], {$1,$2};",
-            "r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX1Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            3,
-            "tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [$0], {$1,$2};",
-            "r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX2RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            5,
-            "tcgen05.st.sync.aligned.16x128b.x2.b32 [$0], {$1,$2,$3,$4};",
-            "r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX2Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            5,
-            "tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [$0], {$1,$2,$3,$4};",
-            "r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX32RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            65,
-            "tcgen05.st.sync.aligned.16x128b.x32.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX32Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            65,
-            "tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX4RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            9,
-            "tcgen05.st.sync.aligned.16x128b.x4.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
-            "r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX4Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            9,
-            "tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
-            "r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX64RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            129,
-            "tcgen05.st.sync.aligned.16x128b.x64.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX64Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            129,
-            "tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX8RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            17,
-            "tcgen05.st.sync.aligned.16x128b.x8.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x128bX8Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            17,
-            "tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX16RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            65,
-            "tcgen05.st.sync.aligned.16x256b.x16.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX16Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            65,
-            "tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX1RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            5,
-            "tcgen05.st.sync.aligned.16x256b.x1.b32 [$0], {$1,$2,$3,$4};",
-            "r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX1Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            5,
-            "tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [$0], {$1,$2,$3,$4};",
-            "r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX2RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            9,
-            "tcgen05.st.sync.aligned.16x256b.x2.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
-            "r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX2Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            9,
-            "tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
-            "r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX32RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            129,
-            "tcgen05.st.sync.aligned.16x256b.x32.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX32Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            129,
-            "tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX4RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            17,
-            "tcgen05.st.sync.aligned.16x256b.x4.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX4Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            17,
-            "tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX8RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            33,
-            "tcgen05.st.sync.aligned.16x256b.x8.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x256bX8Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            33,
-            "tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X128RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            130,
-            "tcgen05.st.sync.aligned.16x32bx2.x128.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128,$129};",
-            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X128Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            130,
-            "tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128,$129};",
-            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X16RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            18,
-            "tcgen05.st.sync.aligned.16x32bx2.x16.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17};",
-            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X16Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            18,
-            "tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17};",
-            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X1RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            3,
-            "tcgen05.st.sync.aligned.16x32bx2.x1.b32 [$0], $1, {$2};",
-            "r,n,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X1Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            3,
-            "tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [$0], $1, {$2};",
-            "r,n,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X2RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            4,
-            "tcgen05.st.sync.aligned.16x32bx2.x2.b32 [$0], $1, {$2,$3};",
-            "r,n,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X2Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            4,
-            "tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [$0], $1, {$2,$3};",
-            "r,n,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X32RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            34,
-            "tcgen05.st.sync.aligned.16x32bx2.x32.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33};",
-            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X32Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            34,
-            "tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33};",
-            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X4RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            6,
-            "tcgen05.st.sync.aligned.16x32bx2.x4.b32 [$0], $1, {$2,$3,$4,$5};",
-            "r,n,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X4Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            6,
-            "tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5};",
-            "r,n,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X64RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            66,
-            "tcgen05.st.sync.aligned.16x32bx2.x64.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65};",
-            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X64Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            66,
-            "tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65};",
-            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X8RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            10,
-            "tcgen05.st.sync.aligned.16x32bx2.x8.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9};",
-            "r,n,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x32bx2X8Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            10,
-            "tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9};",
-            "r,n,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX128RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            129,
-            "tcgen05.st.sync.aligned.16x64b.x128.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX128Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            129,
-            "tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX16RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            17,
-            "tcgen05.st.sync.aligned.16x64b.x16.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX16Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            17,
-            "tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX1RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.st.sync.aligned.16x64b.x1.b32 [$0], {$1};",
-            "r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX1Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [$0], {$1};",
-            "r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX2RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            3,
-            "tcgen05.st.sync.aligned.16x64b.x2.b32 [$0], {$1,$2};",
-            "r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX2Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            3,
-            "tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [$0], {$1,$2};",
-            "r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX32RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            33,
-            "tcgen05.st.sync.aligned.16x64b.x32.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX32Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            33,
-            "tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX4RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            5,
-            "tcgen05.st.sync.aligned.16x64b.x4.b32 [$0], {$1,$2,$3,$4};",
-            "r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX4Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            5,
-            "tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [$0], {$1,$2,$3,$4};",
-            "r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX64RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            65,
-            "tcgen05.st.sync.aligned.16x64b.x64.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX64Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            65,
-            "tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX8RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            9,
-            "tcgen05.st.sync.aligned.16x64b.x8.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
-            "r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St16x64bX8Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            9,
-            "tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
-            "r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX128RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            129,
-            "tcgen05.st.sync.aligned.32x32b.x128.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX128Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            129,
-            "tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX16RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            17,
-            "tcgen05.st.sync.aligned.32x32b.x16.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX16Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            17,
-            "tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX1RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.st.sync.aligned.32x32b.x1.b32 [$0], {$1};",
-            "r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX1Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            2,
-            "tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [$0], {$1};",
-            "r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX2RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            3,
-            "tcgen05.st.sync.aligned.32x32b.x2.b32 [$0], {$1,$2};",
-            "r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX2Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            3,
-            "tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [$0], {$1,$2};",
-            "r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX32RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            33,
-            "tcgen05.st.sync.aligned.32x32b.x32.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX32Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            33,
-            "tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX4RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            5,
-            "tcgen05.st.sync.aligned.32x32b.x4.b32 [$0], {$1,$2,$3,$4};",
-            "r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX4Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            5,
-            "tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [$0], {$1,$2,$3,$4};",
-            "r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX64RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            65,
-            "tcgen05.st.sync.aligned.32x32b.x64.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX64Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            65,
-            "tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
-            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX8RawOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            9,
-            "tcgen05.st.sync.aligned.32x32b.x8.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
-            "r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05St32x32bX8Unpack16Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            9,
-            "tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
-            "r,r,r,r,r,r,r,r,r,~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05StoreWaitOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        convert_generated_tcgen05_void(
-            ctx,
-            rewriter,
-            self.get_operation(),
-            0,
-            "tcgen05.wait::st.sync.aligned;",
-            "~{memory}",
-        )
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Tcgen05MmaOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let form = self.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref().cloned();
-        let kind = self.get_attr_nvvm_tcgen05_mma_kind(ctx).as_deref().cloned();
-        let cta_group = self
-            .get_attr_nvvm_tcgen05_mma_cta_group(ctx)
-            .as_deref()
-            .cloned();
-        let collector_a = self
-            .get_attr_nvvm_tcgen05_mma_collector_a(ctx)
-            .as_deref()
-            .cloned();
-        let b_buffer = self
-            .get_attr_nvvm_tcgen05_mma_b_buffer(ctx)
-            .as_deref()
-            .cloned();
-        let b_usage = self
-            .get_attr_nvvm_tcgen05_mma_b_usage(ctx)
-            .as_deref()
-            .cloned();
-        let kind = match kind {
-            Some(Tcgen05MmaKindAttr::F16) => "f16",
-            Some(Tcgen05MmaKindAttr::Tf32) => "tf32",
-            Some(Tcgen05MmaKindAttr::F8f6f4) => "f8f6f4",
-            Some(Tcgen05MmaKindAttr::I8) => "i8",
-            None => {
-                return pliron::input_err!(op.deref(ctx).loc(), "nvvm.tcgen05_mma requires a kind",);
-            }
-        };
-        let (prefix, a, metadata, zero_mask, constraints, arity, base, ashift) = match form {
-            Some(Tcgen05MmaFormAttr::Shared) => (
-                "tcgen05.mma",
-                "$1",
-                None,
-                None,
-                "r,l,l,r,r,~{memory}",
-                5,
-                true,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::Tensor) => (
-                "tcgen05.mma",
-                "[$1]",
-                None,
-                None,
-                "r,r,l,r,r,~{memory}",
-                5,
-                true,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::TensorAshift) => (
-                "tcgen05.mma",
-                "[$1]",
-                None,
-                None,
-                "r,r,l,r,r,~{memory}",
-                5,
-                true,
-                true,
-            ),
-            Some(Tcgen05MmaFormAttr::SpShared) => (
-                "tcgen05.mma.sp",
-                "$1",
-                Some("$5"),
-                None,
-                "r,l,l,r,r,r,~{memory}",
-                6,
-                true,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::SpTensor) => (
-                "tcgen05.mma.sp",
-                "[$1]",
-                Some("$5"),
-                None,
-                "r,r,l,r,r,r,~{memory}",
-                6,
-                true,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::SpTensorAshift) => (
-                "tcgen05.mma.sp",
-                "[$1]",
-                Some("$5"),
-                None,
-                "r,r,l,r,r,r,~{memory}",
-                6,
-                true,
-                true,
-            ),
-            Some(Tcgen05MmaFormAttr::WsShared) => (
-                "tcgen05.mma.ws",
-                "$1",
-                None,
-                None,
-                "r,l,l,r,r,~{memory}",
-                5,
-                false,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::WsSharedZeroColMask) => (
-                "tcgen05.mma.ws",
-                "$1",
-                None,
-                Some("$5"),
-                "r,l,l,r,r,l,~{memory}",
-                6,
-                false,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::WsSpShared) => (
-                "tcgen05.mma.ws.sp",
-                "$1",
-                Some("$5"),
-                None,
-                "r,l,l,r,r,r,~{memory}",
-                6,
-                false,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::WsSpSharedZeroColMask) => (
-                "tcgen05.mma.ws.sp",
-                "$1",
-                Some("$5"),
-                Some("$6"),
-                "r,l,l,r,r,r,l,~{memory}",
-                7,
-                false,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::WsSpTensor) => (
-                "tcgen05.mma.ws.sp",
-                "[$1]",
-                Some("$5"),
-                None,
-                "r,r,l,r,r,r,~{memory}",
-                6,
-                false,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::WsSpTensorZeroColMask) => (
-                "tcgen05.mma.ws.sp",
-                "[$1]",
-                Some("$5"),
-                Some("$6"),
-                "r,r,l,r,r,r,l,~{memory}",
-                7,
-                false,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::WsTensor) => (
-                "tcgen05.mma.ws",
-                "[$1]",
-                None,
-                None,
-                "r,r,l,r,r,~{memory}",
-                5,
-                false,
-                false,
-            ),
-            Some(Tcgen05MmaFormAttr::WsTensorZeroColMask) => (
-                "tcgen05.mma.ws",
-                "[$1]",
-                None,
-                Some("$5"),
-                "r,r,l,r,r,l,~{memory}",
-                6,
-                false,
-                false,
-            ),
-            None => {
-                return pliron::input_err!(op.deref(ctx).loc(), "nvvm.tcgen05_mma requires a form",);
-            }
-        };
-
-        let selector = if base {
-            let group = match cta_group {
-                Some(Tcgen05MmaCtaGroupAttr::Cg1) => 1,
-                Some(Tcgen05MmaCtaGroupAttr::Cg2) => 2,
-                None => {
-                    return pliron::input_err!(
-                        op.deref(ctx).loc(),
-                        "base tcgen05 MMA requires a CTA-group selector",
-                    );
-                }
-            };
-            let usage = match collector_a {
-                Some(Tcgen05MmaCollectorAAttr::Discard) => "discard",
-                Some(Tcgen05MmaCollectorAAttr::LastUse) => "lastuse",
-                Some(Tcgen05MmaCollectorAAttr::Fill) if !ashift => "fill",
-                Some(Tcgen05MmaCollectorAAttr::Use) if !ashift => "use",
-                _ => {
-                    return pliron::input_err!(
-                        op.deref(ctx).loc(),
-                        "tcgen05 MMA collector-A selector has no generated recipe",
-                    );
-                }
-            };
-            format!(
-                ".cta_group::{group}.kind::{kind}.collector::a::{usage}{}",
-                if ashift { ".ashift" } else { "" },
-            )
-        } else {
-            let buffer = match b_buffer {
-                Some(Tcgen05MmaBBufferAttr::B0) => 0,
-                Some(Tcgen05MmaBBufferAttr::B1) => 1,
-                Some(Tcgen05MmaBBufferAttr::B2) => 2,
-                Some(Tcgen05MmaBBufferAttr::B3) => 3,
-                None => {
-                    return pliron::input_err!(
-                        op.deref(ctx).loc(),
-                        "warp-specialized tcgen05 MMA requires a B-buffer selector",
-                    );
-                }
-            };
-            let usage = match b_usage {
-                Some(Tcgen05MmaBUsageAttr::Discard) => "discard",
-                Some(Tcgen05MmaBUsageAttr::LastUse) => "lastuse",
-                Some(Tcgen05MmaBUsageAttr::Fill) => "fill",
-                Some(Tcgen05MmaBUsageAttr::Use) => "use",
-                None => {
-                    return pliron::input_err!(
-                        op.deref(ctx).loc(),
-                        "warp-specialized tcgen05 MMA requires a B-usage selector",
-                    );
-                }
-            };
-            format!(".cta_group::1.kind::{kind}.collector::b{buffer}::{usage}")
-        };
-
-        let mut operands = format!("[$0], {a}, $2");
-        if let Some(metadata) = metadata {
-            operands.push_str(&format!(", [{metadata}]"));
-        }
-        operands.push_str(", $3, %enable_pred");
-        if let Some(zero_mask) = zero_mask {
-            operands.push_str(&format!(", {zero_mask}"));
-        }
-        let template = format!(
-            "{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; {prefix}{selector} {operands}; }}"
-        );
-        convert_generated_tcgen05_void(ctx, rewriter, op, arity, &template, constraints)
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for BreakpointOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let void_ty = llvm_types::VoidType::get(ctx);
-        inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], "brkpt;", "");
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for PmEventOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let void_ty = llvm_types::VoidType::get(ctx);
-        let Some(event_id) = self.event_id(ctx) else {
-            return pliron::input_err!(
-                op.deref(ctx).loc(),
-                "nvvm.pmevent requires a u32 event ID in 0..=15",
-            );
-        };
-        let template = format!("pmevent {event_id};");
-        inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], &template, "");
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for TrapOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let void_ty = llvm_types::VoidType::get(ctx);
-        inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], "trap;", "");
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for Barrier0Op {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let void_ty = llvm_types::VoidType::get(ctx);
-        match context::lowering_options(ctx).intrinsic_backend {
-            IntrinsicBackend::LlvmNvptx => {
-                let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-                let barrier_id = create_i32_const(ctx, rewriter, 0);
-                let function_ty =
-                    llvm_types::FuncType::get(ctx, void_ty.into(), vec![i32_ty.into()], false);
-                call_intrinsic(
-                    ctx,
-                    rewriter,
-                    op,
-                    "llvm_nvvm_barrier_cta_sync_aligned_all",
-                    function_ty,
-                    vec![barrier_id],
-                )?;
-            }
-            IntrinsicBackend::LibNvvm => {
-                inline_asm_convergent(
-                    ctx,
-                    rewriter,
-                    op,
-                    void_ty.into(),
-                    vec![],
-                    "bar.sync 0;",
-                    "~{memory}",
-                );
-            }
-        }
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ThreadfenceOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let void_ty = llvm_types::VoidType::get(ctx);
-        let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);
-        call_intrinsic(
-            ctx,
-            rewriter,
-            op,
-            "llvm_nvvm_membar_gl",
-            function_ty,
-            vec![],
-        )?;
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ThreadfenceBlockOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let void_ty = llvm_types::VoidType::get(ctx);
-        let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);
-        call_intrinsic(
-            ctx,
-            rewriter,
-            op,
-            "llvm_nvvm_membar_cta",
-            function_ty,
-            vec![],
-        )?;
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
-
-#[op_interface_impl]
-impl MirToLlvmConversion for ThreadfenceSystemOp {
-    fn convert(
-        &self,
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        _operands_info: &OperandsInfo,
-    ) -> Result<()> {
-        let op = self.get_operation();
-        let void_ty = llvm_types::VoidType::get(ctx);
-        let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);
-        call_intrinsic(
-            ctx,
-            rewriter,
-            op,
-            "llvm_nvvm_membar_sys",
-            function_ty,
-            vec![],
-        )?;
-        rewriter.erase_operation(ctx, op);
-        Ok(())
-    }
-}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs b/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs
new file mode 100644
index 0000000000..1ef7e16c94
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs
@@ -0,0 +1,51 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `active_mask` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{common::inline_asm_convergent, warp::convert_active_mask};
+use crate::{IntrinsicBackend, context};
+use dialect_nvvm::ops::ActiveMaskOp;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ActiveMaskOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_active_mask(ctx, rewriter, op, operands_info),
+            IntrinsicBackend::LibNvvm => {
+                let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+                let inline_asm = inline_asm_convergent(
+                    ctx,
+                    rewriter,
+                    op,
+                    i32_ty.into(),
+                    vec![],
+                    "activemask.b32 $0;",
+                    "=r,~{memory}",
+                );
+                rewriter.replace_operation(ctx, op, inline_asm);
+                Ok(())
+            }
+        }
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/clc.rs b/crates/mir-lower/src/convert/generated_intrinsics/clc.rs
new file mode 100644
index 0000000000..b40856f749
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/clc.rs
@@ -0,0 +1,136 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `clc` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    clc::convert_generated_clc_query, clc::convert_generated_clc_try_cancel,
+};
+use dialect_nvvm::ops::{
+    ClcQueryGetFirstCtaidXOp, ClcQueryGetFirstCtaidYOp, ClcQueryGetFirstCtaidZOp,
+    ClcQueryIsCanceledOp, ClcTryCancelMulticastOp, ClcTryCancelOp,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ClcQueryGetFirstCtaidXOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_clc_query(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dclusterlaunchcontrol_dquery_ucancel_dget_ufirst_uctaid_dx",
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ClcQueryGetFirstCtaidYOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_clc_query(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dclusterlaunchcontrol_dquery_ucancel_dget_ufirst_uctaid_dy",
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ClcQueryGetFirstCtaidZOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_clc_query(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dclusterlaunchcontrol_dquery_ucancel_dget_ufirst_uctaid_dz",
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ClcQueryIsCanceledOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_clc_query(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dclusterlaunchcontrol_dquery_ucancel_dis_ucanceled",
+            true,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ClcTryCancelOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_clc_try_cancel(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dclusterlaunchcontrol_dtry_ucancel_dasync_dshared",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ClcTryCancelMulticastOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_clc_try_cancel(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dclusterlaunchcontrol_dtry_ucancel_dasync_dmulticast_dshared",
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs b/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs
new file mode 100644
index 0000000000..e5eba21fc1
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs
@@ -0,0 +1,133 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `cluster_barrier` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{common::call_intrinsic, common::inline_asm_convergent};
+use crate::{IntrinsicBackend, context};
+use dialect_nvvm::ops::{ClusterBarrierModeAttr, ClusterBarrierOp, ClusterSyncOp};
+use llvm_export::types as llvm_types;
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ClusterBarrierOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let recipe = match self.get_attr_nvvm_cluster_barrier_mode(ctx).as_deref() {
+            Some(&ClusterBarrierModeAttr::Arrive) => (
+                "llvm_nvvm_barrier_cluster_arrive",
+                "barrier.cluster.arrive;",
+            ),
+            Some(&ClusterBarrierModeAttr::ArriveAligned) => (
+                "llvm_nvvm_barrier_cluster_arrive_aligned",
+                "barrier.cluster.arrive.aligned;",
+            ),
+            Some(&ClusterBarrierModeAttr::ArriveRelaxed) => (
+                "llvm_nvvm_barrier_cluster_arrive_relaxed",
+                "barrier.cluster.arrive.relaxed;",
+            ),
+            Some(&ClusterBarrierModeAttr::ArriveRelaxedAligned) => (
+                "llvm_nvvm_barrier_cluster_arrive_relaxed_aligned",
+                "barrier.cluster.arrive.relaxed.aligned;",
+            ),
+            Some(&ClusterBarrierModeAttr::Wait) => {
+                ("llvm_nvvm_barrier_cluster_wait", "barrier.cluster.wait;")
+            }
+            Some(&ClusterBarrierModeAttr::WaitAligned) => (
+                "llvm_nvvm_barrier_cluster_wait_aligned",
+                "barrier.cluster.wait.aligned;",
+            ),
+            _ => {
+                return pliron::input_err!(
+                    self.get_operation().deref(ctx).loc(),
+                    "nvvm.cluster_barrier mode has no generated lowering recipe",
+                );
+            }
+        };
+        let op = self.get_operation();
+        let void_ty = llvm_types::VoidType::get(ctx);
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => {
+                let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);
+                call_intrinsic(ctx, rewriter, op, recipe.0, function_ty, vec![])?;
+            }
+            IntrinsicBackend::LibNvvm => {
+                inline_asm_convergent(
+                    ctx,
+                    rewriter,
+                    op,
+                    void_ty.into(),
+                    vec![],
+                    recipe.1,
+                    "~{memory}",
+                );
+            }
+        }
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ClusterSyncOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let void_ty = llvm_types::VoidType::get(ctx);
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => {
+                let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);
+                call_intrinsic(
+                    ctx,
+                    rewriter,
+                    op,
+                    "llvm_nvvm_barrier_cluster_arrive_aligned",
+                    function_ty,
+                    vec![],
+                )?;
+                call_intrinsic(
+                    ctx,
+                    rewriter,
+                    op,
+                    "llvm_nvvm_barrier_cluster_wait_aligned",
+                    function_ty,
+                    vec![],
+                )?;
+            }
+            IntrinsicBackend::LibNvvm => {
+                inline_asm_convergent(
+                    ctx,
+                    rewriter,
+                    op,
+                    void_ty.into(),
+                    vec![],
+                    "barrier.cluster.arrive.aligned; barrier.cluster.wait.aligned;",
+                    "~{memory}",
+                );
+            }
+        }
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs b/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs
new file mode 100644
index 0000000000..b298d12a89
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs
@@ -0,0 +1,93 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `cluster_memory` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{common::cast_to_shared_addrspace, common::inline_asm_convergent};
+use dialect_nvvm::ops::{DsmemReadU32Op, MapaSharedClusterOp};
+use llvm_export::{op_interfaces::CastOpInterface, ops as llvm_ops, types as llvm_types};
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for DsmemReadU32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let operands: Vec<_> = op.deref(ctx).operands().collect();
+        if operands.len() != 2 {
+            return pliron::input_err_noloc!(
+                "dsmem_read_u32 requires 2 operands, got {}",
+                operands.len()
+            );
+        }
+        let shared_pointer = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
+        let rank = operands[1];
+        let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+        let asm = inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            i32_ty.into(),
+            vec![shared_pointer, rank],
+            "{ .reg .u64 %mapped; mapa.shared::cluster.u64 %mapped, $1, $2; ld.shared::cluster.u32 $0, [%mapped]; }",
+            "=r,l,r,~{memory}",
+        );
+        rewriter.replace_operation(ctx, op, asm);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MapaSharedClusterOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let operands: Vec<_> = op.deref(ctx).operands().collect();
+        if operands.len() != 2 {
+            return pliron::input_err_noloc!(
+                "map_shared_rank requires 2 operands, got {}",
+                operands.len()
+            );
+        }
+        let shared_pointer = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
+        let rank = operands[1];
+        let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+        let asm = inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            i64_ty.into(),
+            vec![shared_pointer, rank],
+            "mapa.shared::cluster.u64 $0, $1, $2;",
+            "=l,l,r",
+        );
+        let mapped = asm.deref(ctx).get_result(0);
+        let cluster_shared_pointer_ty = llvm_types::PointerType::get(ctx, 7);
+        let int_to_ptr = llvm_ops::IntToPtrOp::new(ctx, mapped, cluster_shared_pointer_ty.into());
+        rewriter.insert_operation(ctx, int_to_ptr.get_operation());
+        rewriter.replace_operation(ctx, op, int_to_ptr.get_operation());
+        Ok(())
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs b/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs
new file mode 100644
index 0000000000..c3381555fe
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs
@@ -0,0 +1,317 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `cp_async` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    cp_async::convert_generated_cp_async_control, cp_async::convert_generated_cp_async_copy,
+    cp_async::convert_generated_cp_async_mbarrier,
+};
+use dialect_nvvm::ops::{
+    CpAsyncCa4Op, CpAsyncCa8Op, CpAsyncCa16Op, CpAsyncCaZfill4Op, CpAsyncCaZfill8Op,
+    CpAsyncCaZfill16Op, CpAsyncCg16Op, CpAsyncCgZfill16Op, CpAsyncCommitGroupOp,
+    CpAsyncMbarrierArriveNoIncOp, CpAsyncMbarrierArriveNoIncSharedOp, CpAsyncMbarrierArriveOp,
+    CpAsyncMbarrierArriveSharedOp, CpAsyncWaitAllOp, CpAsyncWaitGroupOp,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncCa16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_copy(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "ca",
+            16,
+            false,
+            "llvm_nvvm_cp_async_ca_shared_global_16",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncCa4Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_copy(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "ca",
+            4,
+            false,
+            "llvm_nvvm_cp_async_ca_shared_global_4",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncCa8Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_copy(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "ca",
+            8,
+            false,
+            "llvm_nvvm_cp_async_ca_shared_global_8",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncCaZfill16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_copy(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "ca",
+            16,
+            true,
+            "llvm_nvvm_cp_async_ca_shared_global_16_s",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncCaZfill4Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_copy(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "ca",
+            4,
+            true,
+            "llvm_nvvm_cp_async_ca_shared_global_4_s",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncCaZfill8Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_copy(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "ca",
+            8,
+            true,
+            "llvm_nvvm_cp_async_ca_shared_global_8_s",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncCg16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_copy(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "cg",
+            16,
+            false,
+            "llvm_nvvm_cp_async_cg_shared_global_16",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncCgZfill16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_copy(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "cg",
+            16,
+            true,
+            "llvm_nvvm_cp_async_cg_shared_global_16_s",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncCommitGroupOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_control(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "commit_group",
+            "llvm_nvvm_cp_async_commit_group",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncWaitAllOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_control(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "wait_all",
+            "llvm_nvvm_cp_async_wait_all",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncWaitGroupOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_control(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "wait_group",
+            "llvm_nvvm_cp_async_wait_group",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncMbarrierArriveOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_mbarrier(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "arrive",
+            "generic",
+            "llvm_nvvm_cp_async_mbarrier_arrive",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncMbarrierArriveNoIncOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_mbarrier(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "arrive_no_inc",
+            "generic",
+            "llvm_nvvm_cp_async_mbarrier_arrive_noinc",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncMbarrierArriveNoIncSharedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_mbarrier(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "arrive_no_inc",
+            "shared",
+            "llvm_nvvm_cp_async_mbarrier_arrive_noinc_shared",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncMbarrierArriveSharedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_cp_async_mbarrier(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "arrive",
+            "shared",
+            "llvm_nvvm_cp_async_mbarrier_arrive_shared",
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs
new file mode 100644
index 0000000000..0f805fd47d
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs
@@ -0,0 +1,77 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `debug_control` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::common::inline_asm_sideeffect;
+use dialect_nvvm::ops::{BreakpointOp, PmEventOp, TrapOp};
+use llvm_export::types as llvm_types;
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for BreakpointOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let void_ty = llvm_types::VoidType::get(ctx);
+        inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], "brkpt;", "");
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for PmEventOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let void_ty = llvm_types::VoidType::get(ctx);
+        let Some(event_id) = self.event_id(ctx) else {
+            return pliron::input_err!(
+                op.deref(ctx).loc(),
+                "nvvm.pmevent requires a u32 event ID in 0..=15",
+            );
+        };
+        let template = format!("pmevent {event_id};");
+        inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], &template, "");
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for TrapOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let void_ty = llvm_types::VoidType::get(ctx);
+        inline_asm_sideeffect(ctx, rewriter, op, void_ty.into(), vec![], "trap;", "");
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs b/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs
new file mode 100644
index 0000000000..25da07ad24
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs
@@ -0,0 +1,95 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `dotprod` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::dotprod::convert_generated_dot_product;
+use dialect_nvvm::ops::{Dp2aS32Op, Dp2aU32Op, Dp4aS32Op, Dp4aU32Op};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Dp2aS32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_dot_product(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "llvm_nvvm_idp2a_s_s",
+            "dp2a.lo.s32.s32 $0, $1, $2, $3;",
+            true,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Dp2aU32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_dot_product(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "llvm_nvvm_idp2a_u_u",
+            "dp2a.lo.u32.u32 $0, $1, $2, $3;",
+            true,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Dp4aS32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_dot_product(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "llvm_nvvm_idp4a_s_s",
+            "dp4a.s32.s32 $0, $1, $2, $3;",
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Dp4aU32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_dot_product(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "llvm_nvvm_idp4a_u_u",
+            "dp4a.u32.u32 $0, $1, $2, $3;",
+            false,
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/elect.rs b/crates/mir-lower/src/convert/generated_intrinsics/elect.rs
new file mode 100644
index 0000000000..a302b8e8c6
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/elect.rs
@@ -0,0 +1,43 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `elect` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{warp::convert_elect_sync_inline, warp::convert_elect_sync_typed};
+use crate::{IntrinsicBackend, context};
+use dialect_nvvm::ops::ElectSyncOp;
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ElectSyncOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_elect_sync_typed(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                operands_info,
+                "llvm_nvvm_elect_sync",
+            ),
+            IntrinsicBackend::LibNvvm => {
+                convert_elect_sync_inline(ctx, rewriter, self.get_operation(), operands_info)
+            }
+        }
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs
new file mode 100644
index 0000000000..0ad0a9cdc4
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs
@@ -0,0 +1,186 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `execution_control` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    execution_control::convert_counted_barrier, execution_control::convert_grid_dependency,
+    execution_control::convert_setmaxnreg,
+};
+use dialect_nvvm::ops::{
+    BarrierCtaArriveAlignedCountOp, BarrierCtaArriveCountOp, BarrierCtaSyncAlignedCountOp,
+    BarrierCtaSyncCountOp, GridDependencyLaunchDependentsOp, GridDependencyWaitOp, SetMaxNRegDecOp,
+    SetMaxNRegIncOp,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for BarrierCtaArriveCountOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_counted_barrier(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_barrier_cta_arrive_count",
+            "barrier.arrive $0, $1;",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for BarrierCtaArriveAlignedCountOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_counted_barrier(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_barrier_cta_arrive_aligned_count",
+            "bar.arrive $0, $1;",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for BarrierCtaSyncCountOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_counted_barrier(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_barrier_cta_sync_count",
+            "barrier.sync $0, $1;",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for BarrierCtaSyncAlignedCountOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_counted_barrier(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_barrier_cta_sync_aligned_count",
+            "bar.sync $0, $1;",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for GridDependencyLaunchDependentsOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_grid_dependency(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_griddepcontrol_launch_dependents",
+            "griddepcontrol.launch_dependents;",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for GridDependencyWaitOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_grid_dependency(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_griddepcontrol_wait",
+            "griddepcontrol.wait;",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for SetMaxNRegDecOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let register_count = self.register_count(ctx).ok_or_else(|| {
+            pliron::input_error_noloc!("setmaxnreg register-count attribute is invalid")
+        })?;
+        convert_setmaxnreg(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            register_count,
+            "llvm_nvvm_setmaxnreg_dec_sync_aligned_u32",
+            "dec",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for SetMaxNRegIncOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let register_count = self.register_count(ctx).ok_or_else(|| {
+            pliron::input_error_noloc!("setmaxnreg register-count attribute is invalid")
+        })?;
+        convert_setmaxnreg(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            register_count,
+            "llvm_nvvm_setmaxnreg_inc_sync_aligned_u32",
+            "inc",
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs b/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs
new file mode 100644
index 0000000000..9ee8e772b1
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs
@@ -0,0 +1,416 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `extended_minmax` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    extended_minmax::MinMaxCarrier, extended_minmax::convert_generated_extended_minmax,
+};
+use dialect_nvvm::ops::{
+    ExtendedMinMaxFormatAttr, ExtendedMinMaxNanAttr, ExtendedMinMaxOp, ExtendedMinMaxOperationAttr,
+    ExtendedMinMaxSubnormalAttr, ExtendedMinMaxXorSignAbsAttr,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ExtendedMinMaxOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let recipe = match (
+            self.get_attr_nvvm_extended_minmax_format(ctx).as_deref(),
+            self.get_attr_nvvm_extended_minmax_operation(ctx).as_deref(),
+            self.get_attr_nvvm_extended_minmax_subnormal(ctx).as_deref(),
+            self.get_attr_nvvm_extended_minmax_nan(ctx).as_deref(),
+            self.get_attr_nvvm_extended_minmax_xorsign_abs(ctx)
+                .as_deref(),
+        ) {
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("max.bf16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("max.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("max.ftz.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("max.ftz.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("max.ftz.NaN.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("max.ftz.NaN.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.ftz.NaN.xorsign.abs.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.ftz.NaN.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F32),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.ftz.NaN.xorsign.abs.f32", MinMaxCarrier::F32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.ftz.xorsign.abs.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.ftz.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F32),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.ftz.xorsign.abs.f32", MinMaxCarrier::F32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("max.NaN.bf16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("max.NaN.bf16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("max.NaN.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("max.NaN.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.NaN.xorsign.abs.bf16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.NaN.xorsign.abs.bf16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.NaN.xorsign.abs.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.NaN.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F32),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.NaN.xorsign.abs.f32", MinMaxCarrier::F32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.xorsign.abs.bf16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.xorsign.abs.bf16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.xorsign.abs.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F32),
+                Some(&ExtendedMinMaxOperationAttr::Max),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("max.xorsign.abs.f32", MinMaxCarrier::F32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("min.bf16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("min.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("min.ftz.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("min.ftz.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("min.ftz.NaN.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("min.ftz.NaN.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.ftz.NaN.xorsign.abs.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.ftz.NaN.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F32),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.ftz.NaN.xorsign.abs.f32", MinMaxCarrier::F32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.ftz.xorsign.abs.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.ftz.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F32),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Ftz),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.ftz.xorsign.abs.f32", MinMaxCarrier::F32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("min.NaN.bf16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("min.NaN.bf16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("min.NaN.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Disabled),
+            ) => ("min.NaN.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.NaN.xorsign.abs.bf16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.NaN.xorsign.abs.bf16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.NaN.xorsign.abs.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.NaN.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F32),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Nan),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.NaN.xorsign.abs.f32", MinMaxCarrier::F32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.xorsign.abs.bf16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::Bf16x2),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.xorsign.abs.bf16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.xorsign.abs.f16", MinMaxCarrier::Half16),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F16x2),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.xorsign.abs.f16x2", MinMaxCarrier::PackedU32),
+            (
+                Some(&ExtendedMinMaxFormatAttr::F32),
+                Some(&ExtendedMinMaxOperationAttr::Min),
+                Some(&ExtendedMinMaxSubnormalAttr::Preserve),
+                Some(&ExtendedMinMaxNanAttr::Number),
+                Some(&ExtendedMinMaxXorSignAbsAttr::Enabled),
+            ) => ("min.xorsign.abs.f32", MinMaxCarrier::F32),
+            _ => {
+                return pliron::input_err!(
+                    self.get_operation().deref(ctx).loc(),
+                    "nvvm.extended_minmax variant has no generated lowering recipe",
+                );
+            }
+        };
+        convert_generated_extended_minmax(ctx, rewriter, self.get_operation(), recipe.0, recipe.1)
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs b/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs
new file mode 100644
index 0000000000..187e2ae539
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs
@@ -0,0 +1,118 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `integer_minmax` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::integer_minmax::convert_generated_integer_minmax;
+use dialect_nvvm::ops::{
+    MaxReluS16x2Op, MaxReluS32Op, MaxS16x2Op, MaxU16x2Op, MinReluS16x2Op, MinReluS32Op, MinS16x2Op,
+    MinU16x2Op,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MaxReluS16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "max.relu.s16x2")
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MaxReluS32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "max.relu.s32")
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MaxS16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "max.s16x2")
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MaxU16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "max.u16x2")
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MinReluS16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "min.relu.s16x2")
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MinReluS32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "min.relu.s32")
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MinS16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "min.s16x2")
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MinU16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_integer_minmax(ctx, rewriter, self.get_operation(), "min.u16x2")
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs
new file mode 100644
index 0000000000..feb712c6fc
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs
@@ -0,0 +1,376 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `ldmatrix` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::ldmatrix::convert_generated_ldmatrix;
+use dialect_nvvm::ops::{
+    LdmatrixElementAttr, LdmatrixLayoutAttr, LdmatrixMultiplicityAttr, LdmatrixOp,
+    LdmatrixShapeAttr, LdmatrixStateSpaceAttr, LdmatrixX1Op, LdmatrixX1TransOp, LdmatrixX2Op,
+    LdmatrixX2TransOp, LdmatrixX4Op, LdmatrixX4TransOp,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for LdmatrixOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let recipe = {
+            let shape = self.get_attr_nvvm_ldmatrix_shape(ctx);
+            let multiplicity = self.get_attr_nvvm_ldmatrix_multiplicity(ctx);
+            let layout = self.get_attr_nvvm_ldmatrix_layout(ctx);
+            let element = self.get_attr_nvvm_ldmatrix_element(ctx);
+            let state_space = self.get_attr_nvvm_ldmatrix_state_space(ctx);
+            match (
+                shape.as_deref(),
+                multiplicity.as_deref(),
+                layout.as_deref(),
+                element.as_deref(),
+                state_space.as_deref(),
+            ) {
+                (
+                    Some(&LdmatrixShapeAttr::M16n16),
+                    Some(&LdmatrixMultiplicityAttr::X1),
+                    Some(&LdmatrixLayoutAttr::Transposed),
+                    Some(&LdmatrixElementAttr::B8),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    2,
+                    "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8",
+                    "llvm_nvvm_ldmatrix_sync_aligned_m16n16_x1_trans_b8_p3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M16n16),
+                    Some(&LdmatrixMultiplicityAttr::X1),
+                    Some(&LdmatrixLayoutAttr::Transposed),
+                    Some(&LdmatrixElementAttr::B8x16B4x16P64),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    2,
+                    "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b4x16_p64",
+                    "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db4x16_up64_dp3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M16n16),
+                    Some(&LdmatrixMultiplicityAttr::X1),
+                    Some(&LdmatrixLayoutAttr::Transposed),
+                    Some(&LdmatrixElementAttr::B8x16B6x16P32),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    2,
+                    "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b6x16_p32",
+                    "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db6x16_up32_dp3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M16n16),
+                    Some(&LdmatrixMultiplicityAttr::X2),
+                    Some(&LdmatrixLayoutAttr::Transposed),
+                    Some(&LdmatrixElementAttr::B8),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    4,
+                    "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8",
+                    "llvm_nvvm_ldmatrix_sync_aligned_m16n16_x2_trans_b8_p3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M16n16),
+                    Some(&LdmatrixMultiplicityAttr::X2),
+                    Some(&LdmatrixLayoutAttr::Transposed),
+                    Some(&LdmatrixElementAttr::B8x16B4x16P64),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    4,
+                    "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b4x16_p64",
+                    "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx2_dtrans_db8x16_db4x16_up64_dp3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M16n16),
+                    Some(&LdmatrixMultiplicityAttr::X2),
+                    Some(&LdmatrixLayoutAttr::Transposed),
+                    Some(&LdmatrixElementAttr::B8x16B6x16P32),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    4,
+                    "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b6x16_p32",
+                    "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx2_dtrans_db8x16_db6x16_up32_dp3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n16),
+                    Some(&LdmatrixMultiplicityAttr::X1),
+                    Some(&LdmatrixLayoutAttr::Normal),
+                    Some(&LdmatrixElementAttr::B8x16B4x16P64),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    1,
+                    "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b4x16_p64",
+                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx1_db8x16_db4x16_up64_dp3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n16),
+                    Some(&LdmatrixMultiplicityAttr::X1),
+                    Some(&LdmatrixLayoutAttr::Normal),
+                    Some(&LdmatrixElementAttr::B8x16B6x16P32),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    1,
+                    "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b6x16_p32",
+                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx1_db8x16_db6x16_up32_dp3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n16),
+                    Some(&LdmatrixMultiplicityAttr::X2),
+                    Some(&LdmatrixLayoutAttr::Normal),
+                    Some(&LdmatrixElementAttr::B8x16B4x16P64),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    2,
+                    "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b4x16_p64",
+                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx2_db8x16_db4x16_up64_dp3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n16),
+                    Some(&LdmatrixMultiplicityAttr::X2),
+                    Some(&LdmatrixLayoutAttr::Normal),
+                    Some(&LdmatrixElementAttr::B8x16B6x16P32),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    2,
+                    "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b6x16_p32",
+                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx2_db8x16_db6x16_up32_dp3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n16),
+                    Some(&LdmatrixMultiplicityAttr::X4),
+                    Some(&LdmatrixLayoutAttr::Normal),
+                    Some(&LdmatrixElementAttr::B8x16B4x16P64),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    4,
+                    "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b4x16_p64",
+                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx4_db8x16_db4x16_up64_dp3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n16),
+                    Some(&LdmatrixMultiplicityAttr::X4),
+                    Some(&LdmatrixLayoutAttr::Normal),
+                    Some(&LdmatrixElementAttr::B8x16B6x16P32),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    4,
+                    "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b6x16_p32",
+                    "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx4_db8x16_db6x16_up32_dp3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n8),
+                    Some(&LdmatrixMultiplicityAttr::X1),
+                    Some(&LdmatrixLayoutAttr::Normal),
+                    Some(&LdmatrixElementAttr::B16),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    1,
+                    "ldmatrix.sync.aligned.m8n8.x1.shared.b16",
+                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_b16_p3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n8),
+                    Some(&LdmatrixMultiplicityAttr::X1),
+                    Some(&LdmatrixLayoutAttr::Transposed),
+                    Some(&LdmatrixElementAttr::B16),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    1,
+                    "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16",
+                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_trans_b16_p3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n8),
+                    Some(&LdmatrixMultiplicityAttr::X2),
+                    Some(&LdmatrixLayoutAttr::Normal),
+                    Some(&LdmatrixElementAttr::B16),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    2,
+                    "ldmatrix.sync.aligned.m8n8.x2.shared.b16",
+                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_b16_p3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n8),
+                    Some(&LdmatrixMultiplicityAttr::X2),
+                    Some(&LdmatrixLayoutAttr::Transposed),
+                    Some(&LdmatrixElementAttr::B16),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    2,
+                    "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16",
+                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n8),
+                    Some(&LdmatrixMultiplicityAttr::X4),
+                    Some(&LdmatrixLayoutAttr::Normal),
+                    Some(&LdmatrixElementAttr::B16),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    4,
+                    "ldmatrix.sync.aligned.m8n8.x4.shared.b16",
+                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_b16_p3",
+                ),
+                (
+                    Some(&LdmatrixShapeAttr::M8n8),
+                    Some(&LdmatrixMultiplicityAttr::X4),
+                    Some(&LdmatrixLayoutAttr::Transposed),
+                    Some(&LdmatrixElementAttr::B16),
+                    Some(&LdmatrixStateSpaceAttr::Shared),
+                ) => (
+                    4,
+                    "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16",
+                    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
+                ),
+                _ => {
+                    return pliron::input_err!(
+                        self.get_operation().deref(ctx).loc(),
+                        "nvvm.ldmatrix variant has no generated lowering recipe",
+                    );
+                }
+            }
+        };
+        convert_generated_ldmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            recipe.0,
+            recipe.1,
+            recipe.2,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for LdmatrixX1Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_ldmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            "ldmatrix.sync.aligned.m8n8.x1.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_b16_p3",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for LdmatrixX1TransOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_ldmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_trans_b16_p3",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for LdmatrixX2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_ldmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "ldmatrix.sync.aligned.m8n8.x2.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_b16_p3",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for LdmatrixX2TransOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_ldmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for LdmatrixX4Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_ldmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            4,
+            "ldmatrix.sync.aligned.m8n8.x4.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_b16_p3",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for LdmatrixX4TransOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_ldmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            4,
+            "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16",
+            "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs
new file mode 100644
index 0000000000..a3cffcae3a
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs
@@ -0,0 +1,72 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `mbarrier_basic` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    mbarrier::convert_arrive, mbarrier::convert_init, mbarrier::convert_inval,
+    mbarrier::convert_test_wait,
+};
+use dialect_nvvm::ops::{
+    MbarrierArriveSharedOp, MbarrierInitSharedOp, MbarrierInvalSharedOp, MbarrierTestWaitSharedOp,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MbarrierArriveSharedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_arrive(ctx, rewriter, self.get_operation(), operands_info)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MbarrierInitSharedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_init(ctx, rewriter, self.get_operation(), operands_info)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MbarrierInvalSharedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_inval(ctx, rewriter, self.get_operation(), operands_info)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MbarrierTestWaitSharedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_test_wait(ctx, rewriter, self.get_operation(), operands_info)
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs
new file mode 100644
index 0000000000..9733987457
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs
@@ -0,0 +1,392 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `mbarrier_extended` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    common::cast_to_shared_addrspace, common::inline_asm_convergent, common::trunc_to_i1,
+};
+use dialect_nvvm::ops::{
+    FenceMbarrierInitReleaseClusterOp, FenceProxyAsyncGenericAcquireSharedClusterClusterOp,
+    FenceProxyAsyncGenericReleaseSharedCtaClusterOp, FenceProxyAsyncSharedCtaOp,
+    MbarrierArriveClusterOp, MbarrierArriveExpectTxClusterOp, MbarrierArriveExpectTxSharedOp,
+    MbarrierTryWaitParityClusterOp, MbarrierTryWaitParitySharedOp, MbarrierTryWaitSharedOp,
+    NanosleepOp,
+};
+use llvm_export::types as llvm_types;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::op::Op;
+use pliron::result::Result;
+use pliron::value::DefiningEntity;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceMbarrierInitReleaseClusterOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let operands: Vec<_> = op.deref(ctx).operands().collect();
+        if !operands.is_empty() {
+            return pliron::input_err_noloc!(
+                "fence_mbarrier_init_release_cluster requires 0 operands, got {}",
+                operands.len()
+            );
+        }
+        let void_ty = llvm_types::VoidType::get(ctx);
+        inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            void_ty.into(),
+            operands,
+            "fence.mbarrier_init.release.cluster;",
+            "~{memory}",
+        );
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyAsyncGenericAcquireSharedClusterClusterOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let operands: Vec<_> = op.deref(ctx).operands().collect();
+        if !operands.is_empty() {
+            return pliron::input_err_noloc!(
+                "fence_proxy_async_generic_acquire_shared_cluster_cluster requires 0 operands, got {}",
+                operands.len()
+            );
+        }
+        let void_ty = llvm_types::VoidType::get(ctx);
+        inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            void_ty.into(),
+            operands,
+            "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;",
+            "~{memory}",
+        );
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyAsyncGenericReleaseSharedCtaClusterOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let operands: Vec<_> = op.deref(ctx).operands().collect();
+        if !operands.is_empty() {
+            return pliron::input_err_noloc!(
+                "fence_proxy_async_generic_release_shared_cta_cluster requires 0 operands, got {}",
+                operands.len()
+            );
+        }
+        let void_ty = llvm_types::VoidType::get(ctx);
+        inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            void_ty.into(),
+            operands,
+            "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
+            "~{memory}",
+        );
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyAsyncSharedCtaOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let operands: Vec<_> = op.deref(ctx).operands().collect();
+        if !operands.is_empty() {
+            return pliron::input_err_noloc!(
+                "fence_proxy_async_shared_cta requires 0 operands, got {}",
+                operands.len()
+            );
+        }
+        let void_ty = llvm_types::VoidType::get(ctx);
+        inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            void_ty.into(),
+            operands,
+            "fence.proxy.async.shared::cta;",
+            "~{memory}",
+        );
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MbarrierArriveClusterOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let operands: Vec<_> = op.deref(ctx).operands().collect();
+        if operands.len() != 1 {
+            return pliron::input_err_noloc!(
+                "mbarrier_arrive_cluster requires 1 operands, got {}",
+                operands.len()
+            );
+        }
+        let void_ty = llvm_types::VoidType::get(ctx);
+        inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            void_ty.into(),
+            operands,
+            "mbarrier.arrive.release.cluster.shared::cluster.b64 _, [$0];",
+            "l,~{memory}",
+        );
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MbarrierArriveExpectTxSharedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let mut operands: Vec<_> = op.deref(ctx).operands().collect();
+        if operands.len() != 2 {
+            return pliron::input_err_noloc!(
+                "mbarrier_arrive_expect_tx requires 2 operands, got {}",
+                operands.len()
+            );
+        }
+        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
+        let result_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+        let asm = inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            result_ty.into(),
+            operands,
+            "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 $0, [$1], $2;",
+            "=l,l,r,~{memory}",
+        );
+        rewriter.replace_operation(ctx, op, asm);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MbarrierArriveExpectTxClusterOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let mut operands: Vec<_> = op.deref(ctx).operands().collect();
+        if operands.len() != 2 {
+            return pliron::input_err_noloc!(
+                "mbarrier_arrive_expect_tx_cluster requires 2 operands, got {}",
+                operands.len()
+            );
+        }
+        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
+        let result_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+        let asm = inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            result_ty.into(),
+            operands,
+            "mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 $0, [$1], $2;",
+            "=l,l,r,~{memory}",
+        );
+        rewriter.replace_operation(ctx, op, asm);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MbarrierTryWaitSharedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let mut operands: Vec<_> = op.deref(ctx).operands().collect();
+        if operands.len() != 2 {
+            return pliron::input_err_noloc!(
+                "mbarrier_try_wait requires 2 operands, got {}",
+                operands.len()
+            );
+        }
+        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
+        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+        let asm = inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            result_ty.into(),
+            operands,
+            "{ .reg .pred %p0; mbarrier.try_wait.shared.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
+            "=r,l,l,~{memory}",
+        );
+        let asm_result = asm.deref(ctx).get_result(0);
+        let result = trunc_to_i1(ctx, rewriter, asm_result);
+        let DefiningEntity::Op(result_op) = result.defining_entity() else {
+            unreachable!()
+        };
+        rewriter.replace_operation(ctx, op, result_op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MbarrierTryWaitParitySharedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let mut operands: Vec<_> = op.deref(ctx).operands().collect();
+        if operands.len() != 2 {
+            return pliron::input_err_noloc!(
+                "mbarrier_try_wait_parity requires 2 operands, got {}",
+                operands.len()
+            );
+        }
+        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
+        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+        let asm = inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            result_ty.into(),
+            operands,
+            "{ .reg .pred %p0; mbarrier.try_wait.parity.shared::cta.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
+            "=r,l,r,~{memory}",
+        );
+        let asm_result = asm.deref(ctx).get_result(0);
+        let result = trunc_to_i1(ctx, rewriter, asm_result);
+        let DefiningEntity::Op(result_op) = result.defining_entity() else {
+            unreachable!()
+        };
+        rewriter.replace_operation(ctx, op, result_op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MbarrierTryWaitParityClusterOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let mut operands: Vec<_> = op.deref(ctx).operands().collect();
+        if operands.len() != 2 {
+            return pliron::input_err_noloc!(
+                "mbarrier_try_wait_parity_cluster requires 2 operands, got {}",
+                operands.len()
+            );
+        }
+        operands[0] = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
+        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+        let asm = inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            result_ty.into(),
+            operands,
+            "{ .reg .pred %p0; mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
+            "=r,l,r,~{memory}",
+        );
+        let asm_result = asm.deref(ctx).get_result(0);
+        let result = trunc_to_i1(ctx, rewriter, asm_result);
+        let DefiningEntity::Op(result_op) = result.defining_entity() else {
+            unreachable!()
+        };
+        rewriter.replace_operation(ctx, op, result_op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for NanosleepOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let operands: Vec<_> = op.deref(ctx).operands().collect();
+        if operands.len() != 1 {
+            return pliron::input_err_noloc!(
+                "nanosleep requires 1 operands, got {}",
+                operands.len()
+            );
+        }
+        let void_ty = llvm_types::VoidType::get(ctx);
+        inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            void_ty.into(),
+            operands,
+            "nanosleep.u32 $0;",
+            "r,~{memory}",
+        );
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mod.rs b/crates/mir-lower/src/convert/generated_intrinsics/mod.rs
new file mode 100644
index 0000000000..47dca45637
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/mod.rs
@@ -0,0 +1,234 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces for admitted CUDA intrinsic families.
+
+use crate::convert::intrinsics::{
+    common::call_intrinsic, common::cast_to_shared_addrspace, common::inline_asm_convergent,
+};
+use crate::{IntrinsicBackend, context};
+use llvm_export::{ops as llvm_ops, types as llvm_types};
+use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::DialectConversionRewriter;
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+
+mod active_mask;
+mod clc;
+mod cluster_barrier;
+mod cluster_memory;
+mod cp_async;
+mod debug_control;
+mod dotprod;
+mod elect;
+mod execution_control;
+mod extended_minmax;
+mod integer_minmax;
+mod ldmatrix;
+mod mbarrier_basic;
+mod mbarrier_extended;
+mod movmatrix;
+mod packed_alu;
+mod packed_atomic;
+mod packed_conversion;
+mod prmt;
+mod redux;
+mod register_mma;
+mod scalar_arithmetic;
+mod scalar_conversion;
+mod scalar_math;
+mod sparse_mma;
+mod sreg;
+mod stmatrix;
+mod sync;
+mod tcgen05;
+mod tma;
+mod vote;
+mod warp_barrier;
+mod warp_match;
+mod warp_shuffle;
+mod wgmma_control;
+
+fn convert_zero_operand_scalar_direct(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    width: u32,
+    intrinsic_name: &str,
+) -> Result<()> {
+    let result_ty = IntegerType::get(ctx, width, Signedness::Signless);
+    let function_ty = llvm_types::FuncType::get(ctx, result_ty.into(), vec![], false);
+    let call = call_intrinsic(ctx, rewriter, op, intrinsic_name, function_ty, vec![])?;
+    rewriter.replace_operation(ctx, op, call);
+    Ok(())
+}
+
+fn convert_generated_tcgen05_void(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    arity: usize,
+    template: &str,
+    constraints: &str,
+) -> Result<()> {
+    let operands: Vec<_> = op.deref(ctx).operands().collect();
+    if operands.len() != arity {
+        return pliron::input_err_noloc!(
+            "generated tcgen05 operation expects {arity} operands, got {}",
+            operands.len()
+        );
+    }
+    let void_ty = llvm_types::VoidType::get(ctx);
+    inline_asm_convergent(
+        ctx,
+        rewriter,
+        op,
+        void_ty.into(),
+        operands,
+        template,
+        constraints,
+    );
+    rewriter.erase_operation(ctx, op);
+    Ok(())
+}
+
+#[allow(clippy::too_many_arguments)]
+fn convert_generated_tcgen05_load(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    arity: usize,
+    count: usize,
+    integer_results: bool,
+    template: &str,
+    constraints: &str,
+) -> Result<()> {
+    let operands: Vec<_> = op.deref(ctx).operands().collect();
+    if operands.len() != arity
+        || !(1..=2).contains(&arity)
+        || !(1..=128).contains(&count)
+        || op.deref(ctx).get_num_results() != count
+    {
+        return pliron::input_err_noloc!(
+            "generated tcgen05 load requires 1..=2 operands and 1..=128 results"
+        );
+    }
+    let scalar_ty: pliron::r#type::TypeHandle = if integer_results {
+        IntegerType::get(ctx, 32, Signedness::Signless).into()
+    } else {
+        FP32Type::get(ctx).into()
+    };
+    if count == 1 {
+        let inline_asm = inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            scalar_ty,
+            operands,
+            template,
+            constraints,
+        );
+        let result = inline_asm.deref(ctx).get_result(0);
+        rewriter.replace_operation_with_values(ctx, op, vec![result]);
+        return Ok(());
+    }
+    let result_ty = llvm_types::StructType::get_unnamed(
+        ctx,
+        (
+            (0..count).map(|_| scalar_ty).collect(),
+            llvm_types::StructLayout::Unpacked,
+        ),
+    );
+    let inline_asm = inline_asm_convergent(
+        ctx,
+        rewriter,
+        op,
+        result_ty.into(),
+        operands,
+        template,
+        constraints,
+    );
+    let result = inline_asm.deref(ctx).get_result(0);
+    let mut values = Vec::with_capacity(count);
+    for index in 0..count as u32 {
+        let extract = llvm_ops::ExtractValueOp::new(ctx, result, vec![index])
+            .map_err(|error| pliron::input_error_noloc!("{}", error))?;
+        rewriter.insert_operation(ctx, extract.get_operation());
+        values.push(extract.get_operation().deref(ctx).get_result(0));
+    }
+    rewriter.replace_operation_with_values(ctx, op, values);
+    Ok(())
+}
+
+fn convert_generated_stmatrix(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    register_count: usize,
+    transposed: bool,
+    typed_intrinsic_name: &str,
+) -> Result<()> {
+    let operands: Vec<_> = op.deref(ctx).operands().collect();
+    if operands.len() != register_count + 1 || !matches!(register_count, 2 | 4) {
+        return pliron::input_err_noloc!("stmatrix requires one pointer and two or four registers");
+    }
+    let void_ty = llvm_types::VoidType::get(ctx);
+    match context::lowering_options(ctx).intrinsic_backend {
+        IntrinsicBackend::LlvmNvptx => {
+            let shared = cast_to_shared_addrspace(ctx, rewriter, operands[0]);
+            let shared_ty = llvm_types::PointerType::get(ctx, llvm_types::address_space::SHARED);
+            let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+            let argument_types = std::iter::once(shared_ty.into())
+                .chain(std::iter::repeat_n(i32_ty.into(), register_count))
+                .collect();
+            let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), argument_types, false);
+            let arguments = std::iter::once(shared)
+                .chain(operands.iter().skip(1).copied())
+                .collect();
+            call_intrinsic(
+                ctx,
+                rewriter,
+                op,
+                typed_intrinsic_name,
+                function_ty,
+                arguments,
+            )?;
+        }
+        IntrinsicBackend::LibNvvm => {
+            let registers = (1..=register_count)
+                .map(|index| format!("${index}"))
+                .collect::<Vec<_>>()
+                .join(", ");
+            let trans = if transposed { ".trans" } else { "" };
+            let template = format!(
+                "{{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x{register_count}{trans}.shared.b16 [%ptr32], {{{registers}}}; }}"
+            );
+            let constraints = std::iter::once("l")
+                .chain(std::iter::repeat_n("r", register_count))
+                .chain(std::iter::once("~{memory}"))
+                .collect::<Vec<_>>()
+                .join(",");
+            inline_asm_convergent(
+                ctx,
+                rewriter,
+                op,
+                void_ty.into(),
+                operands,
+                &template,
+                &constraints,
+            );
+        }
+    }
+    rewriter.erase_operation(ctx, op);
+    Ok(())
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs
new file mode 100644
index 0000000000..00ae007cec
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs
@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `movmatrix` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::common::inline_asm_convergent;
+use dialect_nvvm::ops::MovmatrixTransB16Op;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MovmatrixTransB16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let operands: Vec<_> = op.deref(ctx).operands().collect();
+        if operands.len() != 1 {
+            return pliron::input_err_noloc!(
+                "movmatrix_trans_b16 requires 1 operand, got {}",
+                operands.len()
+            );
+        }
+        let result_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+        let asm = inline_asm_convergent(
+            ctx,
+            rewriter,
+            op,
+            result_ty.into(),
+            operands,
+            "movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;",
+            "=r,r",
+        );
+        rewriter.replace_operation(ctx, op, asm);
+        Ok(())
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs
new file mode 100644
index 0000000000..1901c7aa20
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs
@@ -0,0 +1,403 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `packed_alu` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::packed::convert_generated_packed_alu;
+use dialect_nvvm::ops::{
+    AbsBf16x2Op, AbsF16x2Op, AddBf16x2Op, AddF16x2Op, AddF32x2Op, AddFtzF32x2Op, FmaBf16x2Op,
+    FmaF16x2Op, FmaF32x2Op, FmaFtzF16x2Op, FmaFtzF32x2Op, FmaFtzReluF16x2Op, FmaFtzSatF16x2Op,
+    FmaReluBf16x2Op, FmaReluF16x2Op, FmaSatF16x2Op, MaxBf16x2Op, MaxF16x2Op, MinBf16x2Op,
+    MinF16x2Op, MulBf16x2Op, MulF16x2Op, MulF32x2Op, MulFtzF32x2Op, NegBf16x2Op, NegF16x2Op,
+    SubBf16x2Op, SubF16x2Op, SubF32x2Op, SubFtzF32x2Op,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for AbsBf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "abs.bf16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for AbsF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "abs.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for AddBf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "add.rn.bf16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for AddF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "add.rn.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for AddF32x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "add.rn.f32x2", 64)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for AddFtzF32x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "add.rn.ftz.f32x2", 64)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FmaBf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.bf16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FmaF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FmaF32x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.f32x2", 64)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FmaFtzF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.ftz.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FmaFtzF32x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.ftz.f32x2", 64)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FmaFtzReluF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "fma.rn.ftz.relu.f16x2",
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FmaFtzSatF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "fma.rn.ftz.sat.f16x2",
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FmaReluBf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "fma.rn.relu.bf16x2",
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FmaReluF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.relu.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FmaSatF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "fma.rn.sat.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MaxBf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "max.bf16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MaxF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "max.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MinBf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "min.bf16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MinF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "min.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MulBf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "mul.rn.bf16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MulF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "mul.rn.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MulF32x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "mul.rn.f32x2", 64)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MulFtzF32x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "mul.rn.ftz.f32x2", 64)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for NegBf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "neg.bf16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for NegF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "neg.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for SubBf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "sub.rn.bf16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for SubF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "sub.rn.f16x2", 32)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for SubF32x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "sub.rn.f32x2", 64)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for SubFtzF32x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_alu(ctx, rewriter, self.get_operation(), "sub.rn.ftz.f32x2", 64)
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs
new file mode 100644
index 0000000000..aa96845441
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs
@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `packed_atomic` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::atomic::convert_packed_atom_add;
+use dialect_nvvm::ops::{
+    NvvmAtomAddBf16x2Op, NvvmAtomAddF16x2Op, PackedAtomicAddOp, PackedAtomicAtomicityAttr,
+    PackedAtomicFormatAttr, PackedAtomicOrderingAttr, PackedAtomicRoundingAttr,
+    PackedAtomicScopeAttr, PackedAtomicStateSpaceAttr, PackedAtomicSubnormalAttr,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for PackedAtomicAddOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let format = self.get_attr_nvvm_packed_atomic_format(ctx);
+        let state_space = self.get_attr_nvvm_packed_atomic_state_space(ctx);
+        let ordering = self.get_attr_nvvm_packed_atomic_ordering(ctx);
+        let scope = self.get_attr_nvvm_packed_atomic_scope(ctx);
+        let rounding = self.get_attr_nvvm_packed_atomic_rounding(ctx);
+        let subnormal = self.get_attr_nvvm_packed_atomic_subnormal(ctx);
+        let atomicity = self.get_attr_nvvm_packed_atomic_atomicity(ctx);
+        let ptx_type = match (
+            format.as_deref(),
+            state_space.as_deref(),
+            ordering.as_deref(),
+            scope.as_deref(),
+            rounding.as_deref(),
+            subnormal.as_deref(),
+            atomicity.as_deref(),
+        ) {
+            (
+                Some(&PackedAtomicFormatAttr::F16x2),
+                Some(&PackedAtomicStateSpaceAttr::Global),
+                Some(&PackedAtomicOrderingAttr::Relaxed),
+                Some(&PackedAtomicScopeAttr::Gpu),
+                Some(&PackedAtomicRoundingAttr::Rn),
+                Some(&PackedAtomicSubnormalAttr::NoFtz),
+                Some(&PackedAtomicAtomicityAttr::PerElement),
+            ) => "f16x2",
+            (
+                Some(&PackedAtomicFormatAttr::Bf16x2),
+                Some(&PackedAtomicStateSpaceAttr::Global),
+                Some(&PackedAtomicOrderingAttr::Relaxed),
+                Some(&PackedAtomicScopeAttr::Gpu),
+                Some(&PackedAtomicRoundingAttr::Rn),
+                Some(&PackedAtomicSubnormalAttr::NoFtz),
+                Some(&PackedAtomicAtomicityAttr::PerElement),
+            ) => "bf16x2",
+            _ => {
+                return pliron::input_err!(
+                    self.get_operation().deref(ctx).loc(),
+                    "nvvm.packed_atomic_add attributes have no generated lowering recipe",
+                );
+            }
+        };
+        drop((
+            format,
+            state_space,
+            ordering,
+            scope,
+            rounding,
+            subnormal,
+            atomicity,
+        ));
+        convert_packed_atom_add(ctx, rewriter, self.get_operation(), ptx_type)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for NvvmAtomAddF16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_packed_atom_add(ctx, rewriter, self.get_operation(), "f16x2")
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for NvvmAtomAddBf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_packed_atom_add(ctx, rewriter, self.get_operation(), "bf16x2")
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs
new file mode 100644
index 0000000000..11696b30ee
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs
@@ -0,0 +1,370 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `packed_conversion` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    packed::convert_generated_packed_f32x2, packed::convert_generated_packed_unary,
+};
+use dialect_nvvm::ops::{
+    CvtF16x2F32Op, CvtF32x2Bf16x2Op, CvtRnF16x2E4m3x2Op, CvtRnF16x2E5m2x2Op, CvtRnReluBf16x2F32Op,
+    CvtRnReluF16x2E4m3x2Op, CvtRnReluF16x2E5m2x2Op, CvtRnReluF16x2F32Op,
+    CvtRnSatfiniteE4m3x2F16x2Op, CvtRnSatfiniteE4m3x2F32Op, CvtRnSatfiniteE5m2x2F16x2Op,
+    CvtRnSatfiniteE5m2x2F32Op, CvtRnSatfiniteReluE4m3x2F16x2Op, CvtRnSatfiniteReluE4m3x2F32Op,
+    CvtRnSatfiniteReluE5m2x2F16x2Op, CvtRnSatfiniteReluE5m2x2F32Op, CvtRzBf16x2F32Op,
+    CvtRzF16x2F32Op,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtF16x2F32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_f32x2(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            None,
+            "cvt.rn.f16x2.f32",
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtF32x2Bf16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_f32x2(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            None,
+            "cvt.rn.bf16x2.f32",
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnF16x2E4m3x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_unary(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "cvt.rn.f16x2.e4m3x2",
+            32,
+            16,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnF16x2E5m2x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_unary(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "cvt.rn.f16x2.e5m2x2",
+            32,
+            16,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnReluBf16x2F32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_f32x2(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            None,
+            "cvt.rn.relu.bf16x2.f32",
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnReluF16x2E4m3x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_unary(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "cvt.rn.relu.f16x2.e4m3x2",
+            32,
+            16,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnReluF16x2E5m2x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_unary(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "cvt.rn.relu.f16x2.e5m2x2",
+            32,
+            16,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnReluF16x2F32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_f32x2(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            None,
+            "cvt.rn.relu.f16x2.f32",
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnSatfiniteE4m3x2F16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_unary(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "cvt.rn.satfinite.e4m3x2.f16x2",
+            16,
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnSatfiniteE4m3x2F32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_f32x2(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            Some("llvm_nvvm_ff_to_e4m3x2_rn"),
+            "cvt.rn.satfinite.e4m3x2.f32",
+            16,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnSatfiniteE5m2x2F16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_unary(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "cvt.rn.satfinite.e5m2x2.f16x2",
+            16,
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnSatfiniteE5m2x2F32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_f32x2(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            Some("llvm_nvvm_ff_to_e5m2x2_rn"),
+            "cvt.rn.satfinite.e5m2x2.f32",
+            16,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnSatfiniteReluE4m3x2F16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_unary(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "cvt.rn.satfinite.relu.e4m3x2.f16x2",
+            16,
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnSatfiniteReluE4m3x2F32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_f32x2(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            Some("llvm_nvvm_ff_to_e4m3x2_rn_relu"),
+            "cvt.rn.satfinite.relu.e4m3x2.f32",
+            16,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnSatfiniteReluE5m2x2F16x2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_unary(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "cvt.rn.satfinite.relu.e5m2x2.f16x2",
+            16,
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRnSatfiniteReluE5m2x2F32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_f32x2(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            Some("llvm_nvvm_ff_to_e5m2x2_rn_relu"),
+            "cvt.rn.satfinite.relu.e5m2x2.f32",
+            16,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRzBf16x2F32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_f32x2(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            None,
+            "cvt.rz.bf16x2.f32",
+            32,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CvtRzF16x2F32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_packed_f32x2(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            None,
+            "cvt.rz.f16x2.f32",
+            32,
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs b/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs
new file mode 100644
index 0000000000..558cfd2684
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs
@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `prmt` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::prmt::convert_generated_prmt;
+use dialect_nvvm::ops::{PrmtModeAttr, PrmtOp};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for PrmtOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let recipe = match self.get_attr_nvvm_prmt_mode(ctx).as_deref() {
+            Some(&PrmtModeAttr::Generic) => ("llvm_nvvm_prmt", "prmt.b32 $0, $1, $2, $3;"),
+            Some(&PrmtModeAttr::B4e) => ("llvm_nvvm_prmt_b4e", "prmt.b32.b4e $0, $1, $2, $3;"),
+            Some(&PrmtModeAttr::Ecl) => ("llvm_nvvm_prmt_ecl", "prmt.b32.ecl $0, $1, 0, $2;"),
+            Some(&PrmtModeAttr::Ecr) => ("llvm_nvvm_prmt_ecr", "prmt.b32.ecr $0, $1, 0, $2;"),
+            Some(&PrmtModeAttr::F4e) => ("llvm_nvvm_prmt_f4e", "prmt.b32.f4e $0, $1, $2, $3;"),
+            Some(&PrmtModeAttr::Rc16) => ("llvm_nvvm_prmt_rc16", "prmt.b32.rc16 $0, $1, 0, $2;"),
+            Some(&PrmtModeAttr::Rc8) => ("llvm_nvvm_prmt_rc8", "prmt.b32.rc8 $0, $1, 0, $2;"),
+            _ => {
+                return pliron::input_err!(
+                    self.get_operation().deref(ctx).loc(),
+                    "nvvm.prmt mode has no generated lowering recipe",
+                );
+            }
+        };
+        convert_generated_prmt(ctx, rewriter, self.get_operation(), recipe.0, recipe.1)
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/redux.rs b/crates/mir-lower/src/convert/generated_intrinsics/redux.rs
new file mode 100644
index 0000000000..1513d4f8cf
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/redux.rs
@@ -0,0 +1,312 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `redux` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::warp::convert_redux;
+use dialect_nvvm::ops::{
+    ReduxSyncAddOp, ReduxSyncAndOp, ReduxSyncFmaxAbsNanOp, ReduxSyncFmaxAbsOp, ReduxSyncFmaxNanOp,
+    ReduxSyncFmaxOp, ReduxSyncFminAbsNanOp, ReduxSyncFminAbsOp, ReduxSyncFminNanOp,
+    ReduxSyncFminOp, ReduxSyncMaxOp, ReduxSyncMinOp, ReduxSyncOrOp, ReduxSyncUmaxOp,
+    ReduxSyncUminOp, ReduxSyncXorOp,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncAddOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_add",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncAndOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_and",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncFmaxAbsOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_fmax_abs",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncFmaxAbsNanOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_fmax_abs_NaN",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncFmaxOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_fmax",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncMaxOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_max",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncFmaxNanOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_fmax_NaN",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncUmaxOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_umax",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncFminAbsOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_fmin_abs",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncFminAbsNanOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_fmin_abs_NaN",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncFminOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_fmin",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncMinOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_min",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncFminNanOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_fmin_NaN",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncUminOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_umin",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncOrOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_or",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReduxSyncXorOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_redux(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_redux_sync_xor",
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs b/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs
new file mode 100644
index 0000000000..a05834d670
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs
@@ -0,0 +1,2791 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `register_mma` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    wmma::GeneratedMmaResultType, wmma::convert_generated_register_mma,
+};
+use dialect_nvvm::ops::{
+    MmaM8N8K4F64Op, MmaM16N8K8F32Tf32Op, MmaM16N8K16F32Bf16Op, MmaM16N8K16F32F16Op,
+    MmaM16N8K32S32S8Op, RegisterMmaAccumulatorAttr, RegisterMmaElementAttr, RegisterMmaKindAttr,
+    RegisterMmaLayoutAttr, RegisterMmaOp, RegisterMmaOperationAttr, RegisterMmaOverflowAttr,
+    RegisterMmaShapeAttr,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for RegisterMmaOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let operation = self.operation_or_multiply(ctx);
+        let kind = self.kind_or_inferred(ctx);
+        let recipe = match (
+            self.get_attr_nvvm_register_mma_shape(ctx).as_deref(),
+            operation,
+            kind,
+            self.get_attr_nvvm_register_mma_accumulator(ctx).as_deref(),
+            self.get_attr_nvvm_register_mma_a_element(ctx).as_deref(),
+            self.get_attr_nvvm_register_mma_b_element(ctx).as_deref(),
+            self.get_attr_nvvm_register_mma_a_layout(ctx).as_deref(),
+            self.get_attr_nvvm_register_mma_b_layout(ctx).as_deref(),
+            self.get_attr_nvvm_register_mma_overflow(ctx).as_deref(),
+        ) {
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k128),
+                RegisterMmaOperationAttr::AndPopc,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k128),
+                RegisterMmaOperationAttr::XorPopc,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::F16),
+                Some(&RegisterMmaElementAttr::F16),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::Bf16),
+                Some(&RegisterMmaElementAttr::Bf16),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::F16),
+                Some(&RegisterMmaElementAttr::F16),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                5,
+                "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e4m3.f16 {$0, $1}, {$4, $5}, {$6}, {$2, $3};",
+                "=r,=r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                5,
+                "mma.sync.aligned.m16n8k16.row.col.f16.e4m3.e5m2.f16 {$0, $1}, {$4, $5}, {$6}, {$2, $3};",
+                "=r,=r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                5,
+                "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e4m3.f16 {$0, $1}, {$4, $5}, {$6}, {$2, $3};",
+                "=r,=r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                5,
+                "mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e5m2.f16 {$0, $1}, {$4, $5}, {$6}, {$2, $3};",
+                "=r,=r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.f32.e4m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k16.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k256),
+                RegisterMmaOperationAttr::AndPopc,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k256),
+                RegisterMmaOperationAttr::XorPopc,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::F8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                8,
+                "mma.sync.aligned.m16n8k32.row.col.f16.e5m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9}, {$2, $3};",
+                "=r,=r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.f32.e5m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e2m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e3m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e4m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m1.e5m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e2m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e3m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e4m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e2m3.e5m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e2m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e3m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e4m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e3m2.e5m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e2m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e3m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e4m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e4m3.e5m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E2m1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m1.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E2m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e2m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E3m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e3m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E4m3),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e4m3.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Mxf8f6f4,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaElementAttr::E5m2),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                16,
+                "mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.f32.e5m2.e5m2.f32.ue8m0 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7}, $14, {$15, $16}, $17, {$18, $19};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,h,h,r,h,h",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k32.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k32.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k32.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k32.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k4),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::Tf32),
+                Some(&RegisterMmaElementAttr::Tf32),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k4.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k64),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k64),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k64),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k64),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k64),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k64),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k64),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k64),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k8),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F16),
+                Some(&RegisterMmaElementAttr::F16),
+                Some(&RegisterMmaElementAttr::F16),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                5,
+                "mma.sync.aligned.m16n8k8.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6}, {$2, $3};",
+                "=r,=r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k8),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::Bf16),
+                Some(&RegisterMmaElementAttr::Bf16),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k8),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::F16),
+                Some(&RegisterMmaElementAttr::F16),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                7,
+                "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M16n8k8),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F32),
+                Some(&RegisterMmaElementAttr::Tf32),
+                Some(&RegisterMmaElementAttr::Tf32),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                10,
+                "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k128),
+                RegisterMmaOperationAttr::AndPopc,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k128),
+                RegisterMmaOperationAttr::XorPopc,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaElementAttr::B1),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k16.row.col.s32.s8.s8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.s8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k16.row.col.s32.s8.u8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k16.row.col.s32.u8.s8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::S8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.s8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k16),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaElementAttr::U8),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k16.row.col.satfinite.s32.u8.u8.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.s4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k32.row.col.s32.s4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.s4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k32.row.col.s32.u4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Wrapping),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k32.row.col.s32.u4.s4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::S4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.s4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k32),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::S32),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaElementAttr::U4),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::Satfinite),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=r,=r,r,r,r,r",
+            ),
+            (
+                Some(&RegisterMmaShapeAttr::M8n8k4),
+                RegisterMmaOperationAttr::Multiply,
+                RegisterMmaKindAttr::Standard,
+                Some(&RegisterMmaAccumulatorAttr::F64),
+                Some(&RegisterMmaElementAttr::F64),
+                Some(&RegisterMmaElementAttr::F64),
+                Some(&RegisterMmaLayoutAttr::Row),
+                Some(&RegisterMmaLayoutAttr::Col),
+                Some(&RegisterMmaOverflowAttr::NotApplicable),
+            ) => (
+                GeneratedMmaResultType::F64,
+                2,
+                4,
+                "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$4}, {$5}, {$2, $3};",
+                "=d,=d,d,d,d,d",
+            ),
+            _ => {
+                return pliron::input_err!(
+                    self.get_operation().deref(ctx).loc(),
+                    "nvvm.register_mma variant has no generated lowering recipe",
+                );
+            }
+        };
+        convert_generated_register_mma(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            recipe.0,
+            recipe.1,
+            recipe.2,
+            recipe.3,
+            recipe.4,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MmaM16N8K16F32Bf16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_register_mma(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            GeneratedMmaResultType::F32,
+            4,
+            10,
+            "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+            "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MmaM16N8K16F32F16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_register_mma(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            GeneratedMmaResultType::F32,
+            4,
+            10,
+            "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+            "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MmaM16N8K32S32S8Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_register_mma(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            GeneratedMmaResultType::I32,
+            4,
+            10,
+            "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MmaM16N8K8F32Tf32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_register_mma(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            GeneratedMmaResultType::F32,
+            4,
+            10,
+            "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13}, {$4, $5, $6, $7};",
+            "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MmaM8N8K4F64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_register_mma(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            GeneratedMmaResultType::F64,
+            2,
+            4,
+            "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$4}, {$5}, {$2, $3};",
+            "=d,=d,d,d,d,d",
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs
new file mode 100644
index 0000000000..bda81e7c25
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs
@@ -0,0 +1,549 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `scalar_arithmetic` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::scalar_arithmetic::convert_generated_scalar_arithmetic;
+use dialect_nvvm::ops::{
+    ScalarArithmeticFormatAttr, ScalarArithmeticOp, ScalarArithmeticOperationAttr,
+    ScalarArithmeticRoundingAttr, ScalarArithmeticSaturationAttr, ScalarArithmeticSubnormalAttr,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ScalarArithmeticOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let recipe = match (
+            self.get_attr_nvvm_scalar_arithmetic_format(ctx).as_deref(),
+            self.get_attr_nvvm_scalar_arithmetic_operation(ctx)
+                .as_deref(),
+            self.get_attr_nvvm_scalar_arithmetic_rounding(ctx)
+                .as_deref(),
+            self.get_attr_nvvm_scalar_arithmetic_subnormal(ctx)
+                .as_deref(),
+            self.get_attr_nvvm_scalar_arithmetic_saturation(ctx)
+                .as_deref(),
+        ) {
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rm_f", "add.rm.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rm_d", "add.rm.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rm_ftz_f", "add.rm.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => (
+                "llvm_nvvm_add_rm_ftz_sat_f",
+                "add.rm.sat.ftz.f32",
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => ("llvm_nvvm_add_rm_sat_f", "add.rm.sat.f32", false, true),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rn_f", "add.rn.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rn_d", "add.rn.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rn_ftz_f", "add.rn.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => (
+                "llvm_nvvm_add_rn_ftz_sat_f",
+                "add.rn.sat.ftz.f32",
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => ("llvm_nvvm_add_rn_sat_f", "add.rn.sat.f32", false, true),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rp_f", "add.rp.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rp_d", "add.rp.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rp_ftz_f", "add.rp.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => (
+                "llvm_nvvm_add_rp_ftz_sat_f",
+                "add.rp.sat.ftz.f32",
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => ("llvm_nvvm_add_rp_sat_f", "add.rp.sat.f32", false, true),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rz_f", "add.rz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rz_d", "add.rz.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_add_rz_ftz_f", "add.rz.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => (
+                "llvm_nvvm_add_rz_ftz_sat_f",
+                "add.rz.sat.ftz.f32",
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Add),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => ("llvm_nvvm_add_rz_sat_f", "add.rz.sat.f32", false, true),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rm_f", "div.rm.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rm_d", "div.rm.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rm_ftz_f", "div.rm.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rn_f", "div.rn.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rn_d", "div.rn.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rn_ftz_f", "div.rn.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rp_f", "div.rp.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rp_d", "div.rp.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rp_ftz_f", "div.rp.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rz_f", "div.rz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rz_d", "div.rz.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Div),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_div_rz_ftz_f", "div.rz.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rm_f", "fma.rm.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rm_d", "fma.rm.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rm_ftz_f", "fma.rm.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => (
+                "llvm_nvvm_fma_rm_ftz_sat_f",
+                "fma.rm.ftz.sat.f32",
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => ("llvm_nvvm_fma_rm_sat_f", "fma.rm.sat.f32", false, true),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rn_f", "fma.rn.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rn_d", "fma.rn.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rn_ftz_f", "fma.rn.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => (
+                "llvm_nvvm_fma_rn_ftz_sat_f",
+                "fma.rn.ftz.sat.f32",
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => ("llvm_nvvm_fma_rn_sat_f", "fma.rn.sat.f32", false, true),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rp_f", "fma.rp.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rp_d", "fma.rp.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rp_ftz_f", "fma.rp.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => (
+                "llvm_nvvm_fma_rp_ftz_sat_f",
+                "fma.rp.ftz.sat.f32",
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => ("llvm_nvvm_fma_rp_sat_f", "fma.rp.sat.f32", false, true),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rz_f", "fma.rz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rz_d", "fma.rz.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_fma_rz_ftz_f", "fma.rz.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => (
+                "llvm_nvvm_fma_rz_ftz_sat_f",
+                "fma.rz.ftz.sat.f32",
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Fma),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::Sat),
+            ) => ("llvm_nvvm_fma_rz_sat_f", "fma.rz.sat.f32", false, true),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rm_f", "mul.rm.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rm_d", "mul.rm.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rm),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rm_ftz_f", "mul.rm.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rn_f", "mul.rn.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rn_d", "mul.rn.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rn),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rn_ftz_f", "mul.rn.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rp_f", "mul.rp.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rp_d", "mul.rp.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rp),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rp_ftz_f", "mul.rp.ftz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rz_f", "mul.rz.f32", false, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F64),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Preserve),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rz_d", "mul.rz.f64", true, false),
+            (
+                Some(&ScalarArithmeticFormatAttr::F32),
+                Some(&ScalarArithmeticOperationAttr::Mul),
+                Some(&ScalarArithmeticRoundingAttr::Rz),
+                Some(&ScalarArithmeticSubnormalAttr::Ftz),
+                Some(&ScalarArithmeticSaturationAttr::None),
+            ) => ("llvm_nvvm_mul_rz_ftz_f", "mul.rz.ftz.f32", false, false),
+            _ => {
+                return pliron::input_err!(
+                    self.get_operation().deref(ctx).loc(),
+                    "nvvm.scalar_arithmetic variant has no generated lowering recipe",
+                );
+            }
+        };
+        convert_generated_scalar_arithmetic(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            recipe.0,
+            recipe.1,
+            recipe.2,
+            recipe.3,
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs
new file mode 100644
index 0000000000..515a68ac65
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs
@@ -0,0 +1,96 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `scalar_conversion` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::scalar_conversion::convert_generated_scalar_conversion;
+use dialect_nvvm::ops::{
+    ScalarConversionOp, ScalarConversionRoundingAttr, ScalarConversionSaturationAttr,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ScalarConversionOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let recipe = match (
+            self.get_attr_nvvm_scalar_conversion_rounding(ctx)
+                .as_deref(),
+            self.get_attr_nvvm_scalar_conversion_saturation(ctx)
+                .as_deref(),
+        ) {
+            (
+                Some(&ScalarConversionRoundingAttr::NearestEven),
+                Some(&ScalarConversionSaturationAttr::ReluSatfinite),
+            ) => (
+                "llvm_nvvm_f2tf32_rn_relu_satfinite",
+                "cvt.rn.relu.satfinite.tf32.f32",
+            ),
+            (
+                Some(&ScalarConversionRoundingAttr::NearestEven),
+                Some(&ScalarConversionSaturationAttr::Relu),
+            ) => ("llvm_nvvm_f2tf32_rn_relu", "cvt.rn.relu.tf32.f32"),
+            (
+                Some(&ScalarConversionRoundingAttr::NearestEven),
+                Some(&ScalarConversionSaturationAttr::Satfinite),
+            ) => ("llvm_nvvm_f2tf32_rn_satfinite", "cvt.rn.satfinite.tf32.f32"),
+            (
+                Some(&ScalarConversionRoundingAttr::NearestEven),
+                Some(&ScalarConversionSaturationAttr::None),
+            ) => ("llvm_nvvm_f2tf32_rn", "cvt.rn.tf32.f32"),
+            (
+                Some(&ScalarConversionRoundingAttr::NearestAway),
+                Some(&ScalarConversionSaturationAttr::Satfinite),
+            ) => (
+                "llvm_nvvm_f2tf32_rna_satfinite",
+                "cvt.rna.satfinite.tf32.f32",
+            ),
+            (
+                Some(&ScalarConversionRoundingAttr::NearestAway),
+                Some(&ScalarConversionSaturationAttr::None),
+            ) => ("llvm_nvvm_f2tf32_rna", "cvt.rna.tf32.f32"),
+            (
+                Some(&ScalarConversionRoundingAttr::TowardZero),
+                Some(&ScalarConversionSaturationAttr::ReluSatfinite),
+            ) => (
+                "llvm_nvvm_f2tf32_rz_relu_satfinite",
+                "cvt.rz.relu.satfinite.tf32.f32",
+            ),
+            (
+                Some(&ScalarConversionRoundingAttr::TowardZero),
+                Some(&ScalarConversionSaturationAttr::Relu),
+            ) => ("llvm_nvvm_f2tf32_rz_relu", "cvt.rz.relu.tf32.f32"),
+            (
+                Some(&ScalarConversionRoundingAttr::TowardZero),
+                Some(&ScalarConversionSaturationAttr::Satfinite),
+            ) => ("llvm_nvvm_f2tf32_rz_satfinite", "cvt.rz.satfinite.tf32.f32"),
+            (
+                Some(&ScalarConversionRoundingAttr::TowardZero),
+                Some(&ScalarConversionSaturationAttr::None),
+            ) => ("llvm_nvvm_f2tf32_rz", "cvt.rz.tf32.f32"),
+            _ => {
+                return pliron::input_err!(
+                    self.get_operation().deref(ctx).loc(),
+                    "nvvm.scalar_conversion variant has no generated lowering recipe",
+                );
+            }
+        };
+        convert_generated_scalar_conversion(ctx, rewriter, self.get_operation(), recipe.0, recipe.1)
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs
new file mode 100644
index 0000000000..827490aaff
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs
@@ -0,0 +1,435 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `scalar_math` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::scalar_math::convert_generated_scalar_math;
+use dialect_nvvm::ops::{
+    ScalarMathFormatAttr, ScalarMathOp, ScalarMathOperationAttr, ScalarMathPrecisionAttr,
+    ScalarMathSubnormalAttr,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ScalarMathOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let recipe = match (
+            self.get_attr_nvvm_scalar_math_format(ctx).as_deref(),
+            self.get_attr_nvvm_scalar_math_operation(ctx).as_deref(),
+            self.get_attr_nvvm_scalar_math_precision(ctx).as_deref(),
+            self.get_attr_nvvm_scalar_math_subnormal(ctx).as_deref(),
+        ) {
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Cos),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => (
+                "llvm_nvvm_cos_approx_f",
+                "cos.approx.f32",
+                false,
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Cos),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_cos_approx_ftz_f",
+                "cos.approx.ftz.f32",
+                false,
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F16),
+                Some(&ScalarMathOperationAttr::Ex2),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_ex2_approx", "ex2.approx.f16", true, false, true),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Ex2),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_ex2_approx", "ex2.approx.f32", false, false, true),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Ex2),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_ex2_approx_ftz",
+                "ex2.approx.ftz.f32",
+                false,
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Lg2),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => (
+                "llvm_nvvm_lg2_approx_f",
+                "lg2.approx.f32",
+                false,
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Lg2),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_lg2_approx_ftz_f",
+                "lg2.approx.ftz.f32",
+                false,
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_rcp_approx_ftz_f",
+                "rcp.approx.ftz.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F64),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_rcp_approx_ftz_d",
+                "rcp.approx.ftz.f64",
+                false,
+                true,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rm),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_rcp_rm_f", "rcp.rm.f32", false, false, false),
+            (
+                Some(&ScalarMathFormatAttr::F64),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rm),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_rcp_rm_d", "rcp.rm.f64", false, true, false),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rm),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_rcp_rm_ftz_f",
+                "rcp.rm.ftz.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rn),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_rcp_rn_f", "rcp.rn.f32", false, false, false),
+            (
+                Some(&ScalarMathFormatAttr::F64),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rn),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_rcp_rn_d", "rcp.rn.f64", false, true, false),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rn),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_rcp_rn_ftz_f",
+                "rcp.rn.ftz.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rp),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_rcp_rp_f", "rcp.rp.f32", false, false, false),
+            (
+                Some(&ScalarMathFormatAttr::F64),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rp),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_rcp_rp_d", "rcp.rp.f64", false, true, false),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rp),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_rcp_rp_ftz_f",
+                "rcp.rp.ftz.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rz),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_rcp_rz_f", "rcp.rz.f32", false, false, false),
+            (
+                Some(&ScalarMathFormatAttr::F64),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rz),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_rcp_rz_d", "rcp.rz.f64", false, true, false),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rcp),
+                Some(&ScalarMathPrecisionAttr::Rz),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_rcp_rz_ftz_f",
+                "rcp.rz.ftz.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rsqrt),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => (
+                "llvm_nvvm_rsqrt_approx_f",
+                "rsqrt.approx.f32",
+                false,
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F64),
+                Some(&ScalarMathOperationAttr::Rsqrt),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => (
+                "llvm_nvvm_rsqrt_approx_d",
+                "rsqrt.approx.f64",
+                false,
+                true,
+                true,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Rsqrt),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_rsqrt_approx_ftz_f",
+                "rsqrt.approx.ftz.f32",
+                false,
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sin),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => (
+                "llvm_nvvm_sin_approx_f",
+                "sin.approx.f32",
+                false,
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sin),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_sin_approx_ftz_f",
+                "sin.approx.ftz.f32",
+                false,
+                false,
+                true,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => (
+                "llvm_nvvm_sqrt_approx_f",
+                "sqrt.approx.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_sqrt_approx_ftz_f",
+                "sqrt.approx.ftz.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rm),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_sqrt_rm_f", "sqrt.rm.f32", false, false, false),
+            (
+                Some(&ScalarMathFormatAttr::F64),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rm),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_sqrt_rm_d", "sqrt.rm.f64", false, true, false),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rm),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_sqrt_rm_ftz_f",
+                "sqrt.rm.ftz.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rn),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_sqrt_rn_f", "sqrt.rn.f32", false, false, false),
+            (
+                Some(&ScalarMathFormatAttr::F64),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rn),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_sqrt_rn_d", "sqrt.rn.f64", false, true, false),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rn),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_sqrt_rn_ftz_f",
+                "sqrt.rn.ftz.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rp),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_sqrt_rp_f", "sqrt.rp.f32", false, false, false),
+            (
+                Some(&ScalarMathFormatAttr::F64),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rp),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_sqrt_rp_d", "sqrt.rp.f64", false, true, false),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rp),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_sqrt_rp_ftz_f",
+                "sqrt.rp.ftz.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rz),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_sqrt_rz_f", "sqrt.rz.f32", false, false, false),
+            (
+                Some(&ScalarMathFormatAttr::F64),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rz),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("llvm_nvvm_sqrt_rz_d", "sqrt.rz.f64", false, true, false),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Sqrt),
+                Some(&ScalarMathPrecisionAttr::Rz),
+                Some(&ScalarMathSubnormalAttr::Ftz),
+            ) => (
+                "llvm_nvvm_sqrt_rz_ftz_f",
+                "sqrt.rz.ftz.f32",
+                false,
+                false,
+                false,
+            ),
+            (
+                Some(&ScalarMathFormatAttr::F32),
+                Some(&ScalarMathOperationAttr::Tanh),
+                Some(&ScalarMathPrecisionAttr::Approx),
+                Some(&ScalarMathSubnormalAttr::Preserve),
+            ) => ("", "tanh.approx.f32", false, false, true),
+            _ => {
+                return pliron::input_err!(
+                    self.get_operation().deref(ctx).loc(),
+                    "nvvm.scalar_math variant has no generated lowering recipe",
+                );
+            }
+        };
+        convert_generated_scalar_math(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            recipe.0,
+            recipe.1,
+            recipe.2,
+            recipe.3,
+            recipe.4,
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs b/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs
new file mode 100644
index 0000000000..9be4093d88
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs
@@ -0,0 +1,2002 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `sparse_mma` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    wmma::GeneratedMmaResultType, wmma::convert_generated_sparse_mma,
+};
+use dialect_nvvm::ops::{
+    SparseMmaAccumulatorAttr, SparseMmaElementAttr, SparseMmaLayoutAttr, SparseMmaMetadataAttr,
+    SparseMmaOp, SparseMmaOverflowAttr, SparseMmaSelectorAttr, SparseMmaShapeAttr,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for SparseMmaOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let recipe = match (
+            self.get_attr_nvvm_sparse_mma_shape(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref(),
+            self.get_attr_nvvm_sparse_mma_selector(ctx).as_deref(),
+        ) {
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Standard),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k128),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k32),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F16),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                2,
+                12,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;",
+                "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaElementAttr::E2m1),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaElementAttr::E2m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaElementAttr::E3m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaElementAttr::E4m3),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::F32),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaElementAttr::E5m2),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::NotApplicable),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::F32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::S4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaElementAttr::U4),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                10,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Wrapping),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::S8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            (
+                Some(&SparseMmaShapeAttr::M16n8k64),
+                Some(&SparseMmaAccumulatorAttr::S32),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaElementAttr::U8),
+                Some(&SparseMmaLayoutAttr::Row),
+                Some(&SparseMmaLayoutAttr::Col),
+                Some(&SparseMmaOverflowAttr::Satfinite),
+                Some(&SparseMmaMetadataAttr::Ordered),
+                Some(&SparseMmaSelectorAttr::ImmediateZero),
+            ) => (
+                GeneratedMmaResultType::I32,
+                4,
+                14,
+                "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;",
+                "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n",
+            ),
+            _ => {
+                return pliron::input_err!(
+                    self.get_operation().deref(ctx).loc(),
+                    "nvvm.sparse_mma variant has no generated lowering recipe",
+                );
+            }
+        };
+        convert_generated_sparse_mma(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            recipe.0,
+            recipe.1,
+            recipe.2,
+            recipe.3,
+            recipe.4,
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs b/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs
new file mode 100644
index 0000000000..e17ae55c0f
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs
@@ -0,0 +1,958 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `sreg` intrinsics.
+
+use super::convert_zero_operand_scalar_direct;
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::basic::convert_sreg_read_inline;
+use crate::{IntrinsicBackend, context};
+use dialect_nvvm::ops::{
+    ReadPtxSregClock64Op, ReadPtxSregClockOp, ReadPtxSregClusterCtaidXOp,
+    ReadPtxSregClusterCtaidYOp, ReadPtxSregClusterCtaidZOp, ReadPtxSregClusterCtarankOp,
+    ReadPtxSregClusterIdXOp, ReadPtxSregClusterIdYOp, ReadPtxSregClusterIdZOp,
+    ReadPtxSregClusterNctaidXOp, ReadPtxSregClusterNctaidYOp, ReadPtxSregClusterNctaidZOp,
+    ReadPtxSregClusterNctarankOp, ReadPtxSregCtaidXOp, ReadPtxSregCtaidYOp, ReadPtxSregCtaidZOp,
+    ReadPtxSregDynamicSmemSizeOp, ReadPtxSregEnvReg1Op, ReadPtxSregEnvReg2Op,
+    ReadPtxSregGlobaltimerOp, ReadPtxSregGridIdOp, ReadPtxSregLaneIdOp, ReadPtxSregLanemaskEqOp,
+    ReadPtxSregLanemaskGeOp, ReadPtxSregLanemaskGtOp, ReadPtxSregLanemaskLeOp,
+    ReadPtxSregLanemaskLtOp, ReadPtxSregNclusterIdXOp, ReadPtxSregNclusterIdYOp,
+    ReadPtxSregNclusterIdZOp, ReadPtxSregNctaidXOp, ReadPtxSregNctaidYOp, ReadPtxSregNctaidZOp,
+    ReadPtxSregNsmIdOp, ReadPtxSregNtidXOp, ReadPtxSregNtidYOp, ReadPtxSregNtidZOp,
+    ReadPtxSregNwarpIdOp, ReadPtxSregSmIdOp, ReadPtxSregTidXOp, ReadPtxSregTidYOp,
+    ReadPtxSregTidZOp, ReadPtxSregTotalSmemSizeOp, ReadPtxSregWarpIdOp,
+};
+use llvm_export::ops::AsmKind;
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNtidXOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_ntid_x",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNtidYOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_ntid_y",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNtidZOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_ntid_z",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregCtaidXOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_ctaid_x",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregCtaidYOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_ctaid_y",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregCtaidZOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_ctaid_z",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClockOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "llvm_nvvm_read_ptx_sreg_clock",
+            ),
+            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "llvm_nvvm_read_ptx_sreg_clock",
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClock64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                64,
+                "llvm_nvvm_read_ptx_sreg_clock64",
+            ),
+            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                64,
+                "llvm_nvvm_read_ptx_sreg_clock64",
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterNctarankOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_cluster_nctarank",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterCtaidXOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_cluster_ctaid_x",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterCtaidYOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_cluster_ctaid_y",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterCtaidZOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_cluster_ctaid_z",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterCtarankOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_cluster_ctarank",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterNctaidXOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_cluster_nctaid_x",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterNctaidYOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_cluster_nctaid_y",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterNctaidZOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_cluster_nctaid_z",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNclusterIdXOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_nclusterid_x",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNclusterIdYOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_nclusterid_y",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNclusterIdZOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_nclusterid_z",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterIdXOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_clusterid_x",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterIdYOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_clusterid_y",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregClusterIdZOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_clusterid_z",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregDynamicSmemSizeOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "mov.u32 $0, %dynamic_smem_size;",
+                "=r",
+                AsmKind::Pure,
+            ),
+            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "mov.u32 $0, %dynamic_smem_size;",
+                "=r",
+                AsmKind::Pure,
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregEnvReg1Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "llvm_nvvm_read_ptx_sreg_envreg1",
+            ),
+            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "llvm_nvvm_read_ptx_sreg_envreg1",
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregEnvReg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "llvm_nvvm_read_ptx_sreg_envreg2",
+            ),
+            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "llvm_nvvm_read_ptx_sreg_envreg2",
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregGlobaltimerOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                64,
+                "llvm_nvvm_read_ptx_sreg_globaltimer",
+            ),
+            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                64,
+                "mov.u64 $0, %globaltimer;",
+                "=l",
+                AsmKind::SideEffect,
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNctaidXOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_nctaid_x",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNctaidYOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_nctaid_y",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNctaidZOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_nctaid_z",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregGridIdOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                64,
+                "mov.u64 $0, %gridid;",
+                "=l",
+                AsmKind::Pure,
+            ),
+            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                64,
+                "mov.u64 $0, %gridid;",
+                "=l",
+                AsmKind::Pure,
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregLaneIdOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_laneid",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregLanemaskEqOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_lanemask_eq",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregLanemaskGeOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_lanemask_ge",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregLanemaskGtOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_lanemask_gt",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregLanemaskLeOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_lanemask_le",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregLanemaskLtOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_lanemask_lt",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNsmIdOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "llvm_nvvm_read_ptx_sreg_nsmid",
+            ),
+            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "llvm_nvvm_read_ptx_sreg_nsmid",
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregNwarpIdOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "llvm_nvvm_read_ptx_sreg_nwarpid",
+            ),
+            IntrinsicBackend::LibNvvm => convert_zero_operand_scalar_direct(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "llvm_nvvm_read_ptx_sreg_nwarpid",
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregSmIdOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "mov.u32 $0, %smid;",
+                "=r",
+                AsmKind::SideEffect,
+            ),
+            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "mov.u32 $0, %smid;",
+                "=r",
+                AsmKind::SideEffect,
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregTidXOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_tid_x",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregTidYOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_tid_y",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregTidZOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_zero_operand_scalar_direct(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            32,
+            "llvm_nvvm_read_ptx_sreg_tid_z",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregTotalSmemSizeOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "mov.u32 $0, %total_smem_size;",
+                "=r",
+                AsmKind::Pure,
+            ),
+            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "mov.u32 $0, %total_smem_size;",
+                "=r",
+                AsmKind::Pure,
+            ),
+        }
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReadPtxSregWarpIdOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "mov.u32 $0, %warpid;",
+                "=r",
+                AsmKind::SideEffect,
+            ),
+            IntrinsicBackend::LibNvvm => convert_sreg_read_inline(
+                ctx,
+                rewriter,
+                self.get_operation(),
+                32,
+                "mov.u32 $0, %warpid;",
+                "=r",
+                AsmKind::SideEffect,
+            ),
+        }
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs
new file mode 100644
index 0000000000..f5a708c78b
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs
@@ -0,0 +1,97 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `stmatrix` intrinsics.
+
+use super::convert_generated_stmatrix;
+use crate::conversion_interface::MirToLlvmConversion;
+use dialect_nvvm::ops::{
+    StmatrixM8n8X2Op, StmatrixM8n8X2TransOp, StmatrixM8n8X4Op, StmatrixM8n8X4TransOp,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for StmatrixM8n8X2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_stmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            false,
+            "llvm_nvvm_stmatrix_sync_aligned_m8n8_x2_b16_p3",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for StmatrixM8n8X2TransOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_stmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            true,
+            "llvm_nvvm_stmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for StmatrixM8n8X4Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_stmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            4,
+            false,
+            "llvm_nvvm_stmatrix_sync_aligned_m8n8_x4_b16_p3",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for StmatrixM8n8X4TransOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_stmatrix(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            4,
+            true,
+            "llvm_nvvm_stmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sync.rs b/crates/mir-lower/src/convert/generated_intrinsics/sync.rs
new file mode 100644
index 0000000000..fa93f5eab0
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/sync.rs
@@ -0,0 +1,139 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `sync` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    common::call_intrinsic, common::create_i32_const, common::inline_asm_convergent,
+};
+use crate::{IntrinsicBackend, context};
+use dialect_nvvm::ops::{Barrier0Op, ThreadfenceBlockOp, ThreadfenceOp, ThreadfenceSystemOp};
+use llvm_export::types as llvm_types;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Barrier0Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let void_ty = llvm_types::VoidType::get(ctx);
+        match context::lowering_options(ctx).intrinsic_backend {
+            IntrinsicBackend::LlvmNvptx => {
+                let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+                let barrier_id = create_i32_const(ctx, rewriter, 0);
+                let function_ty =
+                    llvm_types::FuncType::get(ctx, void_ty.into(), vec![i32_ty.into()], false);
+                call_intrinsic(
+                    ctx,
+                    rewriter,
+                    op,
+                    "llvm_nvvm_barrier_cta_sync_aligned_all",
+                    function_ty,
+                    vec![barrier_id],
+                )?;
+            }
+            IntrinsicBackend::LibNvvm => {
+                inline_asm_convergent(
+                    ctx,
+                    rewriter,
+                    op,
+                    void_ty.into(),
+                    vec![],
+                    "bar.sync 0;",
+                    "~{memory}",
+                );
+            }
+        }
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ThreadfenceOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let void_ty = llvm_types::VoidType::get(ctx);
+        let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);
+        call_intrinsic(
+            ctx,
+            rewriter,
+            op,
+            "llvm_nvvm_membar_gl",
+            function_ty,
+            vec![],
+        )?;
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ThreadfenceBlockOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let void_ty = llvm_types::VoidType::get(ctx);
+        let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);
+        call_intrinsic(
+            ctx,
+            rewriter,
+            op,
+            "llvm_nvvm_membar_cta",
+            function_ty,
+            vec![],
+        )?;
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ThreadfenceSystemOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let void_ty = llvm_types::VoidType::get(ctx);
+        let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), vec![], false);
+        call_intrinsic(
+            ctx,
+            rewriter,
+            op,
+            "llvm_nvvm_membar_sys",
+            function_ty,
+            vec![],
+        )?;
+        rewriter.erase_operation(ctx, op);
+        Ok(())
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs b/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs
new file mode 100644
index 0000000000..99f7568467
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs
@@ -0,0 +1,4469 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `tcgen05` intrinsics.
+
+use super::{convert_generated_tcgen05_load, convert_generated_tcgen05_void};
+use crate::conversion_interface::MirToLlvmConversion;
+use dialect_nvvm::ops::{
+    Tcgen05AllocCg2Op, Tcgen05AllocOp, Tcgen05CommitCg2Op, Tcgen05CommitMulticastCg2Op,
+    Tcgen05CommitMulticastOp, Tcgen05CommitOp, Tcgen05CommitSharedClusterCg2Op,
+    Tcgen05CommitSharedClusterOp, Tcgen05Cp4x256bB4x16P64Cg2Op, Tcgen05Cp4x256bB4x16P64Op,
+    Tcgen05Cp4x256bB6x16P32Cg2Op, Tcgen05Cp4x256bB6x16P32Op, Tcgen05Cp4x256bCg2Op,
+    Tcgen05Cp4x256bOp, Tcgen05Cp32x128bWarpx4B4x16P64Cg2Op, Tcgen05Cp32x128bWarpx4B4x16P64Op,
+    Tcgen05Cp32x128bWarpx4B6x16P32Cg2Op, Tcgen05Cp32x128bWarpx4B6x16P32Op,
+    Tcgen05Cp32x128bWarpx4Cg2Op, Tcgen05Cp32x128bWarpx4Op,
+    Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Op,
+    Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Op,
+    Tcgen05Cp64x128bWarpx2Pair0123Cg2Op, Tcgen05Cp64x128bWarpx2Pair0123Op,
+    Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Op,
+    Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Op,
+    Tcgen05Cp64x128bWarpx2Pair0213Cg2Op, Tcgen05Cp64x128bWarpx2Pair0213Op,
+    Tcgen05Cp128x128bB4x16P64Cg2Op, Tcgen05Cp128x128bB4x16P64Op, Tcgen05Cp128x128bB6x16P32Cg2Op,
+    Tcgen05Cp128x128bB6x16P32Op, Tcgen05Cp128x128bCg2Op, Tcgen05Cp128x128bOp,
+    Tcgen05Cp128x256bB4x16P64Cg2Op, Tcgen05Cp128x256bB4x16P64Op, Tcgen05Cp128x256bB6x16P32Cg2Op,
+    Tcgen05Cp128x256bB6x16P32Op, Tcgen05CpSmemToTmemCg2Op, Tcgen05CpSmemToTmemOp,
+    Tcgen05DeallocCg2Op, Tcgen05DeallocOp, Tcgen05FenceAfterThreadSyncOp,
+    Tcgen05FenceBeforeThreadSyncOp, Tcgen05Ld16x32bx2X1Pack16Op, Tcgen05Ld16x32bx2X1RawOp,
+    Tcgen05Ld16x32bx2X2Pack16Op, Tcgen05Ld16x32bx2X2RawOp, Tcgen05Ld16x32bx2X4Pack16Op,
+    Tcgen05Ld16x32bx2X4RawOp, Tcgen05Ld16x32bx2X8Pack16Op, Tcgen05Ld16x32bx2X8RawOp,
+    Tcgen05Ld16x32bx2X16Pack16Op, Tcgen05Ld16x32bx2X16RawOp, Tcgen05Ld16x32bx2X32Pack16Op,
+    Tcgen05Ld16x32bx2X32RawOp, Tcgen05Ld16x32bx2X64Pack16Op, Tcgen05Ld16x32bx2X64RawOp,
+    Tcgen05Ld16x32bx2X128Pack16Op, Tcgen05Ld16x32bx2X128RawOp, Tcgen05Ld16x64bX1Pack16Op,
+    Tcgen05Ld16x64bX1RawOp, Tcgen05Ld16x64bX2Pack16Op, Tcgen05Ld16x64bX2RawOp,
+    Tcgen05Ld16x64bX4Pack16Op, Tcgen05Ld16x64bX4RawOp, Tcgen05Ld16x64bX8Pack16Op,
+    Tcgen05Ld16x64bX8RawOp, Tcgen05Ld16x64bX16Pack16Op, Tcgen05Ld16x64bX16RawOp,
+    Tcgen05Ld16x64bX32Pack16Op, Tcgen05Ld16x64bX32RawOp, Tcgen05Ld16x64bX64Pack16Op,
+    Tcgen05Ld16x64bX64RawOp, Tcgen05Ld16x64bX128Pack16Op, Tcgen05Ld16x64bX128RawOp,
+    Tcgen05Ld16x128bX1Pack16Op, Tcgen05Ld16x128bX1RawOp, Tcgen05Ld16x128bX2Pack16Op,
+    Tcgen05Ld16x128bX2RawOp, Tcgen05Ld16x128bX4Pack16Op, Tcgen05Ld16x128bX4RawOp,
+    Tcgen05Ld16x128bX8Pack16Op, Tcgen05Ld16x128bX8RawOp, Tcgen05Ld16x128bX16Pack16Op,
+    Tcgen05Ld16x128bX16RawOp, Tcgen05Ld16x128bX32Pack16Op, Tcgen05Ld16x128bX32RawOp,
+    Tcgen05Ld16x128bX64Pack16Op, Tcgen05Ld16x128bX64RawOp, Tcgen05Ld16x256bPureOp,
+    Tcgen05Ld16x256bX1Pack16Op, Tcgen05Ld16x256bX1RawOp, Tcgen05Ld16x256bX2Pack16Op,
+    Tcgen05Ld16x256bX2RawOp, Tcgen05Ld16x256bX4Pack16Op, Tcgen05Ld16x256bX4RawOp,
+    Tcgen05Ld16x256bX8Pack16Op, Tcgen05Ld16x256bX8PureOp, Tcgen05Ld16x256bX8RawOp,
+    Tcgen05Ld16x256bX16Pack16Op, Tcgen05Ld16x256bX16RawOp, Tcgen05Ld16x256bX32Pack16Op,
+    Tcgen05Ld16x256bX32RawOp, Tcgen05Ld32x32bX1Pack16Op, Tcgen05Ld32x32bX1RawOp,
+    Tcgen05Ld32x32bX2Pack16Op, Tcgen05Ld32x32bX2RawOp, Tcgen05Ld32x32bX4Pack16Op,
+    Tcgen05Ld32x32bX4RawOp, Tcgen05Ld32x32bX8Pack16Op, Tcgen05Ld32x32bX8RawOp,
+    Tcgen05Ld32x32bX16Pack16Op, Tcgen05Ld32x32bX16RawOp, Tcgen05Ld32x32bX32Pack16Op,
+    Tcgen05Ld32x32bX32RawOp, Tcgen05Ld32x32bX64Pack16Op, Tcgen05Ld32x32bX64RawOp,
+    Tcgen05Ld32x32bX128Pack16Op, Tcgen05Ld32x32bX128RawOp, Tcgen05LoadWaitOp,
+    Tcgen05MmaBBufferAttr, Tcgen05MmaBUsageAttr, Tcgen05MmaCollectorAAttr, Tcgen05MmaCtaGroupAttr,
+    Tcgen05MmaF16Cg2Op, Tcgen05MmaF16Op, Tcgen05MmaFormAttr, Tcgen05MmaKindAttr, Tcgen05MmaOp,
+    Tcgen05MmaWsBf16Op, Tcgen05MmaWsF16Op, Tcgen05MmaWsTf32Op, Tcgen05RelinquishAllocPermitCg2Op,
+    Tcgen05RelinquishAllocPermitOp, Tcgen05ShiftDownCg2Op, Tcgen05ShiftDownOp,
+    Tcgen05St16x32bx2X1RawOp, Tcgen05St16x32bx2X1Unpack16Op, Tcgen05St16x32bx2X2RawOp,
+    Tcgen05St16x32bx2X2Unpack16Op, Tcgen05St16x32bx2X4RawOp, Tcgen05St16x32bx2X4Unpack16Op,
+    Tcgen05St16x32bx2X8RawOp, Tcgen05St16x32bx2X8Unpack16Op, Tcgen05St16x32bx2X16RawOp,
+    Tcgen05St16x32bx2X16Unpack16Op, Tcgen05St16x32bx2X32RawOp, Tcgen05St16x32bx2X32Unpack16Op,
+    Tcgen05St16x32bx2X64RawOp, Tcgen05St16x32bx2X64Unpack16Op, Tcgen05St16x32bx2X128RawOp,
+    Tcgen05St16x32bx2X128Unpack16Op, Tcgen05St16x64bX1RawOp, Tcgen05St16x64bX1Unpack16Op,
+    Tcgen05St16x64bX2RawOp, Tcgen05St16x64bX2Unpack16Op, Tcgen05St16x64bX4RawOp,
+    Tcgen05St16x64bX4Unpack16Op, Tcgen05St16x64bX8RawOp, Tcgen05St16x64bX8Unpack16Op,
+    Tcgen05St16x64bX16RawOp, Tcgen05St16x64bX16Unpack16Op, Tcgen05St16x64bX32RawOp,
+    Tcgen05St16x64bX32Unpack16Op, Tcgen05St16x64bX64RawOp, Tcgen05St16x64bX64Unpack16Op,
+    Tcgen05St16x64bX128RawOp, Tcgen05St16x64bX128Unpack16Op, Tcgen05St16x128bX1RawOp,
+    Tcgen05St16x128bX1Unpack16Op, Tcgen05St16x128bX2RawOp, Tcgen05St16x128bX2Unpack16Op,
+    Tcgen05St16x128bX4RawOp, Tcgen05St16x128bX4Unpack16Op, Tcgen05St16x128bX8RawOp,
+    Tcgen05St16x128bX8Unpack16Op, Tcgen05St16x128bX16RawOp, Tcgen05St16x128bX16Unpack16Op,
+    Tcgen05St16x128bX32RawOp, Tcgen05St16x128bX32Unpack16Op, Tcgen05St16x128bX64RawOp,
+    Tcgen05St16x128bX64Unpack16Op, Tcgen05St16x256bX1RawOp, Tcgen05St16x256bX1Unpack16Op,
+    Tcgen05St16x256bX2RawOp, Tcgen05St16x256bX2Unpack16Op, Tcgen05St16x256bX4RawOp,
+    Tcgen05St16x256bX4Unpack16Op, Tcgen05St16x256bX8RawOp, Tcgen05St16x256bX8Unpack16Op,
+    Tcgen05St16x256bX16RawOp, Tcgen05St16x256bX16Unpack16Op, Tcgen05St16x256bX32RawOp,
+    Tcgen05St16x256bX32Unpack16Op, Tcgen05St32x32bX1RawOp, Tcgen05St32x32bX1Unpack16Op,
+    Tcgen05St32x32bX2RawOp, Tcgen05St32x32bX2Unpack16Op, Tcgen05St32x32bX4RawOp,
+    Tcgen05St32x32bX4Unpack16Op, Tcgen05St32x32bX8RawOp, Tcgen05St32x32bX8Unpack16Op,
+    Tcgen05St32x32bX16RawOp, Tcgen05St32x32bX16Unpack16Op, Tcgen05St32x32bX32RawOp,
+    Tcgen05St32x32bX32Unpack16Op, Tcgen05St32x32bX64RawOp, Tcgen05St32x32bX64Unpack16Op,
+    Tcgen05St32x32bX128RawOp, Tcgen05St32x32bX128Unpack16Op, Tcgen05StoreWaitOp,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05AllocOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "{ .reg .u64 %shared64; .reg .u32 %shared32; cvta.to.shared.u64 %shared64, $0; cvt.u32.u64 %shared32, %shared64; tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%shared32], $1; }",
+            "l,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05AllocCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "{ .reg .u64 %shared64; .reg .u32 %shared32; cvta.to.shared.u64 %shared64, $0; cvt.u32.u64 %shared32, %shared64; tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 [%shared32], $1; }",
+            "l,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05CommitOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            "tcgen05.commit.cta_group::1.mbarrier::arrive::one.b64 [$0];",
+            "r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05CommitCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            "tcgen05.commit.cta_group::2.mbarrier::arrive::one.b64 [$0];",
+            "r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05CommitMulticastOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;",
+            "r,h,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05CommitMulticastCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [$0], $1;",
+            "r,h,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05CommitSharedClusterOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [$0];",
+            "r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05CommitSharedClusterCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 [$0];",
+            "r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp128x128bOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.128x128b [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp128x128bB4x16P64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp128x128bB4x16P64Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp128x128bB6x16P32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp128x128bB6x16P32Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp128x128bCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.128x128b [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp128x256bB4x16P64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp128x256bB4x16P64Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp128x256bB6x16P32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp128x256bB6x16P32Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.32x128b.warpx4 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4B4x16P64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4B4x16P64Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4B6x16P32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4B6x16P32Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp32x128bWarpx4Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.32x128b.warpx4 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp4x256bOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.4x256b [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp4x256bB4x16P64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp4x256bB4x16P64Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp4x256bB6x16P32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp4x256bB6x16P32Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp4x256bCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.4x256b [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123B4x16P64Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123B6x16P32Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0123Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213B4x16P64Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213B6x16P32Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Cp64x128bWarpx2Pair0213Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05CpSmemToTmemOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::1.128x256b [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05CpSmemToTmemCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.cp.cta_group::2.128x256b [$0], $1;",
+            "r,l,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05DeallocOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.dealloc.cta_group::1.sync.aligned.b32 $0, $1;",
+            "r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05DeallocCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.dealloc.cta_group::2.sync.aligned.b32 $0, $1;",
+            "r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05FenceAfterThreadSyncOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            0,
+            "tcgen05.fence::after_thread_sync;",
+            "~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05FenceBeforeThreadSyncOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            0,
+            "tcgen05.fence::before_thread_sync;",
+            "~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX16Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            32,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x16.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX16RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            32,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x16.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX1Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            2,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32 {$0,$1}, [$2];",
+            "=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX1RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            2,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x1.b32 {$0,$1}, [$2];",
+            "=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX2Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            4,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32 {$0,$1,$2,$3}, [$4];",
+            "=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX2RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            4,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x2.b32 {$0,$1,$2,$3}, [$4];",
+            "=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX32Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            64,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x32.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX32RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            64,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x32.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX4Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            8,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX4RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            8,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x4.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX64Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            128,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x64.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX64RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            128,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x64.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX8Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            16,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x8.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x128bX8RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            16,
+            true,
+            "tcgen05.ld.sync.aligned.16x128b.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bPureOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            4,
+            false,
+            "tcgen05.ld.sync.aligned.16x256b.x1.b32 {$0,$1,$2,$3}, [$4];",
+            "=f,=f,=f,=f,r",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX16Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            64,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX16RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            64,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x16.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX1Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            4,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32 {$0,$1,$2,$3}, [$4];",
+            "=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX1RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            4,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x1.b32 {$0,$1,$2,$3}, [$4];",
+            "=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX2Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            8,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX2RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            8,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x2.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX32Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            128,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x32.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX32RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            128,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x32.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX4Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            16,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX4RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            16,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x4.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX8Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            32,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX8PureOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            32,
+            false,
+            "tcgen05.ld.sync.aligned.16x256b.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
+            "=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,=f,r",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x256bX8RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            32,
+            true,
+            "tcgen05.ld.sync.aligned.16x256b.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X128Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            128,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x128.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128], $129;",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X128RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            128,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x128.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128], $129;",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X16Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            16,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x16.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16], $17;",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X16RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            16,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x16.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16], $17;",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X1Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            1,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 {$0}, [$1], $2;",
+            "=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X1RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            1,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x1.b32 {$0}, [$1], $2;",
+            "=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X2Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            2,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32 {$0,$1}, [$2], $3;",
+            "=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X2RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            2,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x2.b32 {$0,$1}, [$2], $3;",
+            "=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X32Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            32,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x32.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32], $33;",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X32RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            32,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x32.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32], $33;",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X4Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            4,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32 {$0,$1,$2,$3}, [$4], $5;",
+            "=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X4RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            4,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x4.b32 {$0,$1,$2,$3}, [$4], $5;",
+            "=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X64Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            64,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x64.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64], $65;",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X64RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            64,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x64.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64], $65;",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X8Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            8,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x8.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8], $9;",
+            "=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x32bx2X8RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            8,
+            true,
+            "tcgen05.ld.sync.aligned.16x32bx2.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8], $9;",
+            "=r,=r,=r,=r,=r,=r,=r,=r,r,n,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX128Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            128,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x128.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX128RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            128,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x128.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX16Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            16,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x16.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX16RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            16,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x16.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX1Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            1,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 {$0}, [$1];",
+            "=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX1RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            1,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x1.b32 {$0}, [$1];",
+            "=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX2Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            2,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32 {$0,$1}, [$2];",
+            "=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX2RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            2,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x2.b32 {$0,$1}, [$2];",
+            "=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX32Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            32,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x32.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX32RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            32,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x32.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX4Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            4,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32 {$0,$1,$2,$3}, [$4];",
+            "=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX4RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            4,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x4.b32 {$0,$1,$2,$3}, [$4];",
+            "=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX64Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            64,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x64.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX64RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            64,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x64.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX8Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            8,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x8.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld16x64bX8RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            8,
+            true,
+            "tcgen05.ld.sync.aligned.16x64b.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX128Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            128,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX128RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            128,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x128.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127}, [$128];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX16Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            16,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x16.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX16RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            16,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x16.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15}, [$16];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX1Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            1,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32 {$0}, [$1];",
+            "=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX1RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            1,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x1.b32 {$0}, [$1];",
+            "=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX2Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            2,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32 {$0,$1}, [$2];",
+            "=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX2RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            2,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x2.b32 {$0,$1}, [$2];",
+            "=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX32Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            32,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x32.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX32RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            32,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x32.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31}, [$32];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX4Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            4,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32 {$0,$1,$2,$3}, [$4];",
+            "=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX4RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            4,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x4.b32 {$0,$1,$2,$3}, [$4];",
+            "=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX64Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            64,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x64.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX64RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            64,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x64.b32 {$0,$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63}, [$64];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX8Pack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            8,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x8.pack::16b.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05Ld32x32bX8RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_load(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            8,
+            true,
+            "tcgen05.ld.sync.aligned.32x32b.x8.b32 {$0,$1,$2,$3,$4,$5,$6,$7}, [$8];",
+            "=r,=r,=r,=r,=r,=r,=r,=r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05LoadWaitOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            0,
+            "tcgen05.wait::ld.sync.aligned;",
+            "~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05MmaF16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            5,
+            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; .reg .u32 %z; mov.u32 %z, 0; tcgen05.mma.cta_group::1.kind::f16 [$0], $1, $2, $3, {%z, %z, %z, %z}, %enable_pred; }",
+            "r,l,l,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05MmaF16Cg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            5,
+            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; .reg .u32 %z; mov.u32 %z, 0; tcgen05.mma.cta_group::2.kind::f16 [$0], $1, $2, $3, {%z, %z, %z, %z, %z, %z, %z, %z}, %enable_pred; }",
+            "r,l,l,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05MmaWsBf16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            6,
+            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::f16 [$0], [$1], $3, $4, %enable_pred; }",
+            "r,r,l,l,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05MmaWsF16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            6,
+            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::f16 [$0], [$1], $3, $4, %enable_pred; }",
+            "r,r,l,l,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05MmaWsTf32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            6,
+            "{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $5, 0; tcgen05.mma.ws.cta_group::1.kind::tf32 [$0], [$1], $3, $4, %enable_pred; }",
+            "r,r,l,l,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05RelinquishAllocPermitOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            0,
+            "tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;",
+            "~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05RelinquishAllocPermitCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            0,
+            "tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;",
+            "~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05ShiftDownOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            "tcgen05.shift.cta_group::1.down [$0];",
+            "r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05ShiftDownCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            1,
+            "tcgen05.shift.cta_group::2.down [$0];",
+            "r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX16RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            33,
+            "tcgen05.st.sync.aligned.16x128b.x16.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX16Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            33,
+            "tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX1RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            3,
+            "tcgen05.st.sync.aligned.16x128b.x1.b32 [$0], {$1,$2};",
+            "r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX1Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            3,
+            "tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [$0], {$1,$2};",
+            "r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX2RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            5,
+            "tcgen05.st.sync.aligned.16x128b.x2.b32 [$0], {$1,$2,$3,$4};",
+            "r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX2Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            5,
+            "tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [$0], {$1,$2,$3,$4};",
+            "r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX32RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            65,
+            "tcgen05.st.sync.aligned.16x128b.x32.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX32Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            65,
+            "tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX4RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            9,
+            "tcgen05.st.sync.aligned.16x128b.x4.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
+            "r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX4Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            9,
+            "tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
+            "r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX64RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            129,
+            "tcgen05.st.sync.aligned.16x128b.x64.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX64Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            129,
+            "tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX8RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            17,
+            "tcgen05.st.sync.aligned.16x128b.x8.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x128bX8Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            17,
+            "tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX16RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            65,
+            "tcgen05.st.sync.aligned.16x256b.x16.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX16Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            65,
+            "tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX1RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            5,
+            "tcgen05.st.sync.aligned.16x256b.x1.b32 [$0], {$1,$2,$3,$4};",
+            "r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX1Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            5,
+            "tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [$0], {$1,$2,$3,$4};",
+            "r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX2RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            9,
+            "tcgen05.st.sync.aligned.16x256b.x2.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
+            "r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX2Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            9,
+            "tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
+            "r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX32RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            129,
+            "tcgen05.st.sync.aligned.16x256b.x32.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX32Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            129,
+            "tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX4RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            17,
+            "tcgen05.st.sync.aligned.16x256b.x4.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX4Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            17,
+            "tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX8RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            33,
+            "tcgen05.st.sync.aligned.16x256b.x8.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x256bX8Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            33,
+            "tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X128RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            130,
+            "tcgen05.st.sync.aligned.16x32bx2.x128.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128,$129};",
+            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X128Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            130,
+            "tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128,$129};",
+            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X16RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            18,
+            "tcgen05.st.sync.aligned.16x32bx2.x16.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17};",
+            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X16Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            18,
+            "tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17};",
+            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X1RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            3,
+            "tcgen05.st.sync.aligned.16x32bx2.x1.b32 [$0], $1, {$2};",
+            "r,n,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X1Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            3,
+            "tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [$0], $1, {$2};",
+            "r,n,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X2RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            4,
+            "tcgen05.st.sync.aligned.16x32bx2.x2.b32 [$0], $1, {$2,$3};",
+            "r,n,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X2Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            4,
+            "tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [$0], $1, {$2,$3};",
+            "r,n,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X32RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            34,
+            "tcgen05.st.sync.aligned.16x32bx2.x32.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33};",
+            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X32Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            34,
+            "tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33};",
+            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X4RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            6,
+            "tcgen05.st.sync.aligned.16x32bx2.x4.b32 [$0], $1, {$2,$3,$4,$5};",
+            "r,n,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X4Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            6,
+            "tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5};",
+            "r,n,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X64RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            66,
+            "tcgen05.st.sync.aligned.16x32bx2.x64.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65};",
+            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X64Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            66,
+            "tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65};",
+            "r,n,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X8RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            10,
+            "tcgen05.st.sync.aligned.16x32bx2.x8.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9};",
+            "r,n,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x32bx2X8Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            10,
+            "tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [$0], $1, {$2,$3,$4,$5,$6,$7,$8,$9};",
+            "r,n,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX128RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            129,
+            "tcgen05.st.sync.aligned.16x64b.x128.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX128Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            129,
+            "tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX16RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            17,
+            "tcgen05.st.sync.aligned.16x64b.x16.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX16Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            17,
+            "tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX1RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.st.sync.aligned.16x64b.x1.b32 [$0], {$1};",
+            "r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX1Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [$0], {$1};",
+            "r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX2RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            3,
+            "tcgen05.st.sync.aligned.16x64b.x2.b32 [$0], {$1,$2};",
+            "r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX2Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            3,
+            "tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [$0], {$1,$2};",
+            "r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX32RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            33,
+            "tcgen05.st.sync.aligned.16x64b.x32.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX32Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            33,
+            "tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX4RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            5,
+            "tcgen05.st.sync.aligned.16x64b.x4.b32 [$0], {$1,$2,$3,$4};",
+            "r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX4Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            5,
+            "tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [$0], {$1,$2,$3,$4};",
+            "r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX64RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            65,
+            "tcgen05.st.sync.aligned.16x64b.x64.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX64Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            65,
+            "tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX8RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            9,
+            "tcgen05.st.sync.aligned.16x64b.x8.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
+            "r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St16x64bX8Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            9,
+            "tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
+            "r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX128RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            129,
+            "tcgen05.st.sync.aligned.32x32b.x128.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX128Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            129,
+            "tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$100,$101,$102,$103,$104,$105,$106,$107,$108,$109,$110,$111,$112,$113,$114,$115,$116,$117,$118,$119,$120,$121,$122,$123,$124,$125,$126,$127,$128};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX16RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            17,
+            "tcgen05.st.sync.aligned.32x32b.x16.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX16Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            17,
+            "tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX1RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.st.sync.aligned.32x32b.x1.b32 [$0], {$1};",
+            "r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX1Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            2,
+            "tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [$0], {$1};",
+            "r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX2RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            3,
+            "tcgen05.st.sync.aligned.32x32b.x2.b32 [$0], {$1,$2};",
+            "r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX2Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            3,
+            "tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [$0], {$1,$2};",
+            "r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX32RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            33,
+            "tcgen05.st.sync.aligned.32x32b.x32.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX32Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            33,
+            "tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX4RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            5,
+            "tcgen05.st.sync.aligned.32x32b.x4.b32 [$0], {$1,$2,$3,$4};",
+            "r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX4Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            5,
+            "tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [$0], {$1,$2,$3,$4};",
+            "r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX64RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            65,
+            "tcgen05.st.sync.aligned.32x32b.x64.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX64Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            65,
+            "tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8,$9,$10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$40,$41,$42,$43,$44,$45,$46,$47,$48,$49,$50,$51,$52,$53,$54,$55,$56,$57,$58,$59,$60,$61,$62,$63,$64};",
+            "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX8RawOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            9,
+            "tcgen05.st.sync.aligned.32x32b.x8.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
+            "r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05St32x32bX8Unpack16Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            9,
+            "tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [$0], {$1,$2,$3,$4,$5,$6,$7,$8};",
+            "r,r,r,r,r,r,r,r,r,~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05StoreWaitOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_tcgen05_void(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            0,
+            "tcgen05.wait::st.sync.aligned;",
+            "~{memory}",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for Tcgen05MmaOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let op = self.get_operation();
+        let form = self.get_attr_nvvm_tcgen05_mma_form(ctx).as_deref().cloned();
+        let kind = self.get_attr_nvvm_tcgen05_mma_kind(ctx).as_deref().cloned();
+        let cta_group = self
+            .get_attr_nvvm_tcgen05_mma_cta_group(ctx)
+            .as_deref()
+            .cloned();
+        let collector_a = self
+            .get_attr_nvvm_tcgen05_mma_collector_a(ctx)
+            .as_deref()
+            .cloned();
+        let b_buffer = self
+            .get_attr_nvvm_tcgen05_mma_b_buffer(ctx)
+            .as_deref()
+            .cloned();
+        let b_usage = self
+            .get_attr_nvvm_tcgen05_mma_b_usage(ctx)
+            .as_deref()
+            .cloned();
+        let kind = match kind {
+            Some(Tcgen05MmaKindAttr::F16) => "f16",
+            Some(Tcgen05MmaKindAttr::Tf32) => "tf32",
+            Some(Tcgen05MmaKindAttr::F8f6f4) => "f8f6f4",
+            Some(Tcgen05MmaKindAttr::I8) => "i8",
+            None => {
+                return pliron::input_err!(op.deref(ctx).loc(), "nvvm.tcgen05_mma requires a kind",);
+            }
+        };
+        let (prefix, a, metadata, zero_mask, constraints, arity, base, ashift) = match form {
+            Some(Tcgen05MmaFormAttr::Shared) => (
+                "tcgen05.mma",
+                "$1",
+                None,
+                None,
+                "r,l,l,r,r,~{memory}",
+                5,
+                true,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::Tensor) => (
+                "tcgen05.mma",
+                "[$1]",
+                None,
+                None,
+                "r,r,l,r,r,~{memory}",
+                5,
+                true,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::TensorAshift) => (
+                "tcgen05.mma",
+                "[$1]",
+                None,
+                None,
+                "r,r,l,r,r,~{memory}",
+                5,
+                true,
+                true,
+            ),
+            Some(Tcgen05MmaFormAttr::SpShared) => (
+                "tcgen05.mma.sp",
+                "$1",
+                Some("$5"),
+                None,
+                "r,l,l,r,r,r,~{memory}",
+                6,
+                true,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::SpTensor) => (
+                "tcgen05.mma.sp",
+                "[$1]",
+                Some("$5"),
+                None,
+                "r,r,l,r,r,r,~{memory}",
+                6,
+                true,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::SpTensorAshift) => (
+                "tcgen05.mma.sp",
+                "[$1]",
+                Some("$5"),
+                None,
+                "r,r,l,r,r,r,~{memory}",
+                6,
+                true,
+                true,
+            ),
+            Some(Tcgen05MmaFormAttr::WsShared) => (
+                "tcgen05.mma.ws",
+                "$1",
+                None,
+                None,
+                "r,l,l,r,r,~{memory}",
+                5,
+                false,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::WsSharedZeroColMask) => (
+                "tcgen05.mma.ws",
+                "$1",
+                None,
+                Some("$5"),
+                "r,l,l,r,r,l,~{memory}",
+                6,
+                false,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::WsSpShared) => (
+                "tcgen05.mma.ws.sp",
+                "$1",
+                Some("$5"),
+                None,
+                "r,l,l,r,r,r,~{memory}",
+                6,
+                false,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::WsSpSharedZeroColMask) => (
+                "tcgen05.mma.ws.sp",
+                "$1",
+                Some("$5"),
+                Some("$6"),
+                "r,l,l,r,r,r,l,~{memory}",
+                7,
+                false,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::WsSpTensor) => (
+                "tcgen05.mma.ws.sp",
+                "[$1]",
+                Some("$5"),
+                None,
+                "r,r,l,r,r,r,~{memory}",
+                6,
+                false,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::WsSpTensorZeroColMask) => (
+                "tcgen05.mma.ws.sp",
+                "[$1]",
+                Some("$5"),
+                Some("$6"),
+                "r,r,l,r,r,r,l,~{memory}",
+                7,
+                false,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::WsTensor) => (
+                "tcgen05.mma.ws",
+                "[$1]",
+                None,
+                None,
+                "r,r,l,r,r,~{memory}",
+                5,
+                false,
+                false,
+            ),
+            Some(Tcgen05MmaFormAttr::WsTensorZeroColMask) => (
+                "tcgen05.mma.ws",
+                "[$1]",
+                None,
+                Some("$5"),
+                "r,r,l,r,r,l,~{memory}",
+                6,
+                false,
+                false,
+            ),
+            None => {
+                return pliron::input_err!(op.deref(ctx).loc(), "nvvm.tcgen05_mma requires a form",);
+            }
+        };
+
+        let selector = if base {
+            let group = match cta_group {
+                Some(Tcgen05MmaCtaGroupAttr::Cg1) => 1,
+                Some(Tcgen05MmaCtaGroupAttr::Cg2) => 2,
+                None => {
+                    return pliron::input_err!(
+                        op.deref(ctx).loc(),
+                        "base tcgen05 MMA requires a CTA-group selector",
+                    );
+                }
+            };
+            let usage = match collector_a {
+                Some(Tcgen05MmaCollectorAAttr::Discard) => "discard",
+                Some(Tcgen05MmaCollectorAAttr::LastUse) => "lastuse",
+                Some(Tcgen05MmaCollectorAAttr::Fill) if !ashift => "fill",
+                Some(Tcgen05MmaCollectorAAttr::Use) if !ashift => "use",
+                _ => {
+                    return pliron::input_err!(
+                        op.deref(ctx).loc(),
+                        "tcgen05 MMA collector-A selector has no generated recipe",
+                    );
+                }
+            };
+            format!(
+                ".cta_group::{group}.kind::{kind}.collector::a::{usage}{}",
+                if ashift { ".ashift" } else { "" },
+            )
+        } else {
+            let buffer = match b_buffer {
+                Some(Tcgen05MmaBBufferAttr::B0) => 0,
+                Some(Tcgen05MmaBBufferAttr::B1) => 1,
+                Some(Tcgen05MmaBBufferAttr::B2) => 2,
+                Some(Tcgen05MmaBBufferAttr::B3) => 3,
+                None => {
+                    return pliron::input_err!(
+                        op.deref(ctx).loc(),
+                        "warp-specialized tcgen05 MMA requires a B-buffer selector",
+                    );
+                }
+            };
+            let usage = match b_usage {
+                Some(Tcgen05MmaBUsageAttr::Discard) => "discard",
+                Some(Tcgen05MmaBUsageAttr::LastUse) => "lastuse",
+                Some(Tcgen05MmaBUsageAttr::Fill) => "fill",
+                Some(Tcgen05MmaBUsageAttr::Use) => "use",
+                None => {
+                    return pliron::input_err!(
+                        op.deref(ctx).loc(),
+                        "warp-specialized tcgen05 MMA requires a B-usage selector",
+                    );
+                }
+            };
+            format!(".cta_group::1.kind::{kind}.collector::b{buffer}::{usage}")
+        };
+
+        let mut operands = format!("[$0], {a}, $2");
+        if let Some(metadata) = metadata {
+            operands.push_str(&format!(", [{metadata}]"));
+        }
+        operands.push_str(", $3, %enable_pred");
+        if let Some(zero_mask) = zero_mask {
+            operands.push_str(&format!(", {zero_mask}"));
+        }
+        let template = format!(
+            "{{ .reg .pred %enable_pred; setp.ne.s32 %enable_pred, $4, 0; {prefix}{selector} {operands}; }}"
+        );
+        convert_generated_tcgen05_void(ctx, rewriter, op, arity, &template, constraints)
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/tma.rs b/crates/mir-lower/src/convert/generated_intrinsics/tma.rs
new file mode 100644
index 0000000000..745bf0ee64
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/tma.rs
@@ -0,0 +1,2446 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `tma` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    tma::PrefetchTileConfig, tma::ReduceConfig, tma::convert_control, tma::convert_g2s,
+    tma::convert_g2s_multicast_cg2, tma::convert_prefetch_tensormap, tma::convert_prefetch_tile,
+    tma::convert_reduce_s2g, tma::convert_s2g, tma::convert_tensormap_fence,
+    tma::convert_tensormap_replace,
+};
+use dialect_nvvm::ops::{
+    CpAsyncBulkCommitGroupOp, CpAsyncBulkPrefetchTensor1dL2CacheHintOp,
+    CpAsyncBulkPrefetchTensor1dL2Op, CpAsyncBulkPrefetchTensor2dL2CacheHintOp,
+    CpAsyncBulkPrefetchTensor2dL2Op, CpAsyncBulkPrefetchTensor3dL2CacheHintOp,
+    CpAsyncBulkPrefetchTensor3dL2Op, CpAsyncBulkPrefetchTensor4dL2CacheHintOp,
+    CpAsyncBulkPrefetchTensor4dL2Op, CpAsyncBulkPrefetchTensor5dL2CacheHintOp,
+    CpAsyncBulkPrefetchTensor5dL2Op, CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp,
+    CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op, CpAsyncBulkTensorG2sTile1dOp,
+    CpAsyncBulkTensorG2sTile2dMulticastCg2Op, CpAsyncBulkTensorG2sTile2dMulticastOp,
+    CpAsyncBulkTensorG2sTile2dOp, CpAsyncBulkTensorG2sTile3dOp, CpAsyncBulkTensorG2sTile4dOp,
+    CpAsyncBulkTensorG2sTile5dOp, CpAsyncBulkTensorReduceAddIm2col3dOp,
+    CpAsyncBulkTensorReduceAddIm2col4dOp, CpAsyncBulkTensorReduceAddIm2col5dOp,
+    CpAsyncBulkTensorReduceAddTile1dOp, CpAsyncBulkTensorReduceAddTile2dOp,
+    CpAsyncBulkTensorReduceAddTile3dOp, CpAsyncBulkTensorReduceAddTile4dOp,
+    CpAsyncBulkTensorReduceAddTile5dOp, CpAsyncBulkTensorReduceAndIm2col3dOp,
+    CpAsyncBulkTensorReduceAndIm2col4dOp, CpAsyncBulkTensorReduceAndIm2col5dOp,
+    CpAsyncBulkTensorReduceAndTile1dOp, CpAsyncBulkTensorReduceAndTile2dOp,
+    CpAsyncBulkTensorReduceAndTile3dOp, CpAsyncBulkTensorReduceAndTile4dOp,
+    CpAsyncBulkTensorReduceAndTile5dOp, CpAsyncBulkTensorReduceDecIm2col3dOp,
+    CpAsyncBulkTensorReduceDecIm2col4dOp, CpAsyncBulkTensorReduceDecIm2col5dOp,
+    CpAsyncBulkTensorReduceDecTile1dOp, CpAsyncBulkTensorReduceDecTile2dOp,
+    CpAsyncBulkTensorReduceDecTile3dOp, CpAsyncBulkTensorReduceDecTile4dOp,
+    CpAsyncBulkTensorReduceDecTile5dOp, CpAsyncBulkTensorReduceIncIm2col3dOp,
+    CpAsyncBulkTensorReduceIncIm2col4dOp, CpAsyncBulkTensorReduceIncIm2col5dOp,
+    CpAsyncBulkTensorReduceIncTile1dOp, CpAsyncBulkTensorReduceIncTile2dOp,
+    CpAsyncBulkTensorReduceIncTile3dOp, CpAsyncBulkTensorReduceIncTile4dOp,
+    CpAsyncBulkTensorReduceIncTile5dOp, CpAsyncBulkTensorReduceMaxIm2col3dOp,
+    CpAsyncBulkTensorReduceMaxIm2col4dOp, CpAsyncBulkTensorReduceMaxIm2col5dOp,
+    CpAsyncBulkTensorReduceMaxTile1dOp, CpAsyncBulkTensorReduceMaxTile2dOp,
+    CpAsyncBulkTensorReduceMaxTile3dOp, CpAsyncBulkTensorReduceMaxTile4dOp,
+    CpAsyncBulkTensorReduceMaxTile5dOp, CpAsyncBulkTensorReduceMinIm2col3dOp,
+    CpAsyncBulkTensorReduceMinIm2col4dOp, CpAsyncBulkTensorReduceMinIm2col5dOp,
+    CpAsyncBulkTensorReduceMinTile1dOp, CpAsyncBulkTensorReduceMinTile2dOp,
+    CpAsyncBulkTensorReduceMinTile3dOp, CpAsyncBulkTensorReduceMinTile4dOp,
+    CpAsyncBulkTensorReduceMinTile5dOp, CpAsyncBulkTensorReduceOrIm2col3dOp,
+    CpAsyncBulkTensorReduceOrIm2col4dOp, CpAsyncBulkTensorReduceOrIm2col5dOp,
+    CpAsyncBulkTensorReduceOrTile1dOp, CpAsyncBulkTensorReduceOrTile2dOp,
+    CpAsyncBulkTensorReduceOrTile3dOp, CpAsyncBulkTensorReduceOrTile4dOp,
+    CpAsyncBulkTensorReduceOrTile5dOp, CpAsyncBulkTensorReduceXorIm2col3dOp,
+    CpAsyncBulkTensorReduceXorIm2col4dOp, CpAsyncBulkTensorReduceXorIm2col5dOp,
+    CpAsyncBulkTensorReduceXorTile1dOp, CpAsyncBulkTensorReduceXorTile2dOp,
+    CpAsyncBulkTensorReduceXorTile3dOp, CpAsyncBulkTensorReduceXorTile4dOp,
+    CpAsyncBulkTensorReduceXorTile5dOp, CpAsyncBulkTensorS2gTile1dOp, CpAsyncBulkTensorS2gTile2dOp,
+    CpAsyncBulkTensorS2gTile3dOp, CpAsyncBulkTensorS2gTile4dOp, CpAsyncBulkTensorS2gTile5dOp,
+    CpAsyncBulkWaitGroupOp, CpAsyncBulkWaitGroupReadOp, FenceProxyTensorMapGenericAcquireClusterOp,
+    FenceProxyTensorMapGenericAcquireCtaOp, FenceProxyTensorMapGenericAcquireGpuOp,
+    FenceProxyTensorMapGenericAcquireSystemOp, FenceProxyTensorMapGenericReleaseClusterOp,
+    FenceProxyTensorMapGenericReleaseCtaOp, FenceProxyTensorMapGenericReleaseGpuOp,
+    FenceProxyTensorMapGenericReleaseSystemOp, PrefetchTensorMapOp, ReplaceTensorMapBoxDimOp,
+    ReplaceTensorMapElementStrideOp, ReplaceTensorMapElementTypeOp, ReplaceTensorMapFillModeOp,
+    ReplaceTensorMapGlobalAddressOp, ReplaceTensorMapGlobalDimOp, ReplaceTensorMapGlobalStrideOp,
+    ReplaceTensorMapInterleaveLayoutOp, ReplaceTensorMapRankOp, ReplaceTensorMapSwizzleAtomicityOp,
+    ReplaceTensorMapSwizzleModeOp,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkCommitGroupOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_control(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "commit_group",
+            "llvm_nvvm_cp_async_bulk_commit_group",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor1dL2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                1,
+                false,
+                false,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_1d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor1dL2CacheHintOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                1,
+                false,
+                true,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_1d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor2dL2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                2,
+                false,
+                false,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor2dL2CacheHintOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                2,
+                false,
+                true,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor3dL2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                3,
+                false,
+                false,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor3dL2CacheHintOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                3,
+                false,
+                true,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor4dL2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                4,
+                false,
+                false,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor4dL2CacheHintOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                4,
+                false,
+                true,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor5dL2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                5,
+                false,
+                false,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensor5dL2CacheHintOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                5,
+                false,
+                true,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                5,
+                true,
+                false,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_gather4_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tile(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            PrefetchTileConfig::new(
+                5,
+                true,
+                true,
+                "llvm_nvvm_cp_async_bulk_tensor_prefetch_tile_gather4_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile1dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 1, false)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorS2gTile1dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 1)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile2dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 2, false)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile2dMulticastOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 2, true)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile2dMulticastCg2Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_g2s_multicast_cg2(ctx, rewriter, self.get_operation(), operands_info)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorS2gTile2dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 2)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 3, false)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorS2gTile3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 3)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 4, false)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorS2gTile4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 4)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorG2sTile5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_g2s(ctx, rewriter, self.get_operation(), operands_info, 5, false)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorS2gTile5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_s2g(ctx, rewriter, self.get_operation(), operands_info, 5)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddIm2col3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "add",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_im2col_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddIm2col4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "add",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_im2col_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddIm2col5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "add",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_im2col_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddTile1dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                1,
+                "add",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_1d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddTile2dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                2,
+                "add",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddTile3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "add",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddTile4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "add",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAddTile5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "add",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_add_tile_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndIm2col3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "and",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_im2col_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndIm2col4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "and",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_im2col_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndIm2col5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "and",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_im2col_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndTile1dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                1,
+                "and",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_tile_1d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndTile2dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                2,
+                "and",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_tile_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndTile3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "and",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_tile_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndTile4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "and",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_tile_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceAndTile5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "and",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_and_tile_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecIm2col3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "dec",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_im2col_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecIm2col4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "dec",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_im2col_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecIm2col5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "dec",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_im2col_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecTile1dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                1,
+                "dec",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_tile_1d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecTile2dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                2,
+                "dec",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_tile_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecTile3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "dec",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_tile_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecTile4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "dec",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_tile_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceDecTile5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "dec",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_dec_tile_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncIm2col3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "inc",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_im2col_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncIm2col4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "inc",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_im2col_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncIm2col5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "inc",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_im2col_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncTile1dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                1,
+                "inc",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_tile_1d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncTile2dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                2,
+                "inc",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_tile_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncTile3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "inc",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_tile_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncTile4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "inc",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_tile_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceIncTile5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "inc",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_inc_tile_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxIm2col3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "max",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_im2col_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxIm2col4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "max",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_im2col_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxIm2col5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "max",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_im2col_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxTile1dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                1,
+                "max",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_tile_1d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxTile2dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                2,
+                "max",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_tile_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxTile3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "max",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_tile_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxTile4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "max",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_tile_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMaxTile5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "max",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_max_tile_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinIm2col3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "min",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_im2col_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinIm2col4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "min",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_im2col_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinIm2col5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "min",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_im2col_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinTile1dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                1,
+                "min",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_tile_1d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinTile2dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                2,
+                "min",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_tile_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinTile3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "min",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_tile_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinTile4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "min",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_tile_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceMinTile5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "min",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_min_tile_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrIm2col3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "or",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_im2col_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrIm2col4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "or",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_im2col_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrIm2col5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "or",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_im2col_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrTile1dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                1,
+                "or",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_tile_1d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrTile2dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                2,
+                "or",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_tile_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrTile3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "or",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_tile_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrTile4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "or",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_tile_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceOrTile5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "or",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_or_tile_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorIm2col3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "xor",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_im2col_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorIm2col4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "xor",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_im2col_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorIm2col5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "xor",
+                "im2col",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_im2col_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorTile1dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                1,
+                "xor",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_tile_1d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorTile2dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                2,
+                "xor",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_tile_2d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorTile3dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                3,
+                "xor",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_tile_3d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorTile4dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                4,
+                "xor",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_tile_4d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkTensorReduceXorTile5dOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_reduce_s2g(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            ReduceConfig::new(
+                5,
+                "xor",
+                "tile",
+                "llvm_nvvm_cp_async_bulk_tensor_reduce_xor_tile_5d",
+            ),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkWaitGroupOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_control(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "wait_group",
+            "llvm_nvvm_cp_async_bulk_wait_group",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for CpAsyncBulkWaitGroupReadOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_control(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "wait_group_read",
+            "llvm_nvvm_cp_async_bulk_wait_group_read",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyTensorMapGenericAcquireClusterOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_fence(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_dacquire_dcluster",
+            true,
+            "cluster",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyTensorMapGenericAcquireCtaOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_fence(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_dacquire_dcta",
+            true,
+            "cta",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyTensorMapGenericAcquireGpuOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_fence(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_dacquire_dgpu",
+            true,
+            "gpu",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyTensorMapGenericAcquireSystemOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_fence(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_dacquire_dsys",
+            true,
+            "sys",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyTensorMapGenericReleaseClusterOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_fence(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_drelease_dcluster",
+            false,
+            "cluster",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyTensorMapGenericReleaseCtaOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_fence(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_drelease_dcta",
+            false,
+            "cta",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyTensorMapGenericReleaseGpuOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_fence(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_drelease_dgpu",
+            false,
+            "gpu",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for FenceProxyTensorMapGenericReleaseSystemOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_fence(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm__nvvm_dfence_dproxy_dtensormap_ugeneric_drelease_dsys",
+            false,
+            "sys",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for PrefetchTensorMapOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_prefetch_tensormap(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_prefetch_tensormap_p0",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapBoxDimOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_box_dim",
+            "box_dim",
+            "u32",
+            true,
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapElementStrideOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_element_stride",
+            "element_stride",
+            "u32",
+            true,
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapElementTypeOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_elemtype",
+            "elemtype",
+            "u32",
+            false,
+            true,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapFillModeOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_fill_mode",
+            "fill_mode",
+            "u32",
+            false,
+            true,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapGlobalAddressOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_global_address",
+            "global_address",
+            "address",
+            false,
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapGlobalDimOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_global_dim",
+            "global_dim",
+            "u32",
+            true,
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapGlobalStrideOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_global_stride",
+            "global_stride",
+            "u64",
+            true,
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapInterleaveLayoutOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_interleave_layout",
+            "interleave_layout",
+            "u32",
+            false,
+            true,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapRankOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_rank",
+            "rank",
+            "u32",
+            false,
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapSwizzleAtomicityOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_swizzle_atomicity",
+            "swizzle_atomicity",
+            "u32",
+            false,
+            true,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ReplaceTensorMapSwizzleModeOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_tensormap_replace(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_tensormap_replace_swizzle_mode",
+            "swizzle_mode",
+            "u32",
+            false,
+            true,
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/vote.rs b/crates/mir-lower/src/convert/generated_intrinsics/vote.rs
new file mode 100644
index 0000000000..fadf6ef801
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/vote.rs
@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `vote` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::warp::convert_vote;
+use dialect_nvvm::ops::{VoteSyncAllOp, VoteSyncAnyOp, VoteSyncBallotOp, VoteSyncUniOp};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for VoteSyncAllOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_vote(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_vote_all_sync",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for VoteSyncAnyOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_vote(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_vote_any_sync",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for VoteSyncBallotOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_vote(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_vote_ballot_sync",
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for VoteSyncUniOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_vote(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_vote_uni_sync",
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs
new file mode 100644
index 0000000000..5be73094a5
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs
@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `warp_barrier` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::warp::convert_bar_warp_sync;
+use dialect_nvvm::ops::BarWarpSyncOp;
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for BarWarpSyncOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_bar_warp_sync(ctx, rewriter, self.get_operation(), operands_info)
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs
new file mode 100644
index 0000000000..d2122bfd26
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs
@@ -0,0 +1,102 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `warp_match` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{warp::convert_match_all, warp::convert_match_any};
+use dialect_nvvm::ops::{
+    MatchAllSyncI32Op, MatchAllSyncI64Op, MatchAnySyncI32Op, MatchAnySyncI64Op,
+};
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MatchAllSyncI64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let value_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+        convert_match_all(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_match_all_sync_i64p",
+            value_ty.into(),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MatchAllSyncI32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let value_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+        convert_match_all(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_match_all_sync_i32p",
+            value_ty.into(),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MatchAnySyncI64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let value_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+        convert_match_any(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_match_any_sync_i64",
+            value_ty.into(),
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for MatchAnySyncI32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        let value_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+        convert_match_any(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_match_any_sync_i32",
+            value_ty.into(),
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs
new file mode 100644
index 0000000000..45991cd55b
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs
@@ -0,0 +1,246 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `warp_shuffle` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{
+    warp::convert_shuffle_f32, warp::convert_shuffle_i32, warp::convert_shuffle_i64,
+};
+use dialect_nvvm::ops::{
+    ShflSyncBflyF32Op, ShflSyncBflyI32Op, ShflSyncBflyI64Op, ShflSyncDownF32Op, ShflSyncDownI32Op,
+    ShflSyncDownI64Op, ShflSyncIdxF32Op, ShflSyncIdxI32Op, ShflSyncIdxI64Op, ShflSyncUpF32Op,
+    ShflSyncUpI32Op, ShflSyncUpI64Op,
+};
+use pliron::context::Context;
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::op::Op;
+use pliron::result::Result;
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncDownF32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_f32(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_shfl_sync_down_f32",
+            31,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncDownI32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_i32(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_shfl_sync_down_i32",
+            31,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncDownI64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_i64(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "down",
+            31,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncIdxF32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_f32(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_shfl_sync_idx_f32",
+            31,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncIdxI32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_i32(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_shfl_sync_idx_i32",
+            31,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncIdxI64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_i64(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "idx",
+            31,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncUpF32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_f32(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_shfl_sync_up_f32",
+            0,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncUpI32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_i32(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_shfl_sync_up_i32",
+            0,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncUpI64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_i64(ctx, rewriter, self.get_operation(), operands_info, "up", 0)
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncBflyF32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_f32(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_shfl_sync_bfly_f32",
+            31,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncBflyI32Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_i32(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "llvm_nvvm_shfl_sync_bfly_i32",
+            31,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for ShflSyncBflyI64Op {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_shuffle_i64(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            operands_info,
+            "bfly",
+            31,
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs
new file mode 100644
index 0000000000..2f7eac198e
--- /dev/null
+++ b/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs
@@ -0,0 +1,131 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT.
+// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 90f843cce5f56a1499b53ac77a837864c9c04e091becb9a950a0aef2aae2a31a.
+// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e.
+
+//! Generated conversion interfaces: `wgmma_control` intrinsics.
+
+use crate::conversion_interface::MirToLlvmConversion;
+use crate::convert::intrinsics::{common::call_intrinsic, common::inline_asm_convergent};
+use crate::{IntrinsicBackend, context};
+use dialect_nvvm::ops::{
+    WgmmaCommitGroupSyncAlignedOp, WgmmaFenceSyncAlignedOp, WgmmaWaitGroupSyncAlignedOp,
+};
+use llvm_export::types as llvm_types;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::derive::op_interface_impl;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+
+fn convert_generated_wgmma_control(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    intrinsic_name: &str,
+    ptx: &str,
+    has_immediate: bool,
+) -> Result<()> {
+    let operands: Vec<_> = op.deref(ctx).operands().collect();
+    if operands.len() != usize::from(has_immediate) {
+        return pliron::input_err!(
+            op.deref(ctx).loc(),
+            "generated WGMMA control has the wrong operand count",
+        );
+    }
+    let void_ty = llvm_types::VoidType::get(ctx);
+    match context::lowering_options(ctx).intrinsic_backend {
+        IntrinsicBackend::LlvmNvptx => {
+            let arguments = if has_immediate {
+                vec![IntegerType::get(ctx, 64, Signedness::Signless).into()]
+            } else {
+                vec![]
+            };
+            let function_ty = llvm_types::FuncType::get(ctx, void_ty.into(), arguments, false);
+            call_intrinsic(ctx, rewriter, op, intrinsic_name, function_ty, operands)?;
+        }
+        IntrinsicBackend::LibNvvm => {
+            let constraints = if has_immediate {
+                "n,~{memory}"
+            } else {
+                "~{memory}"
+            };
+            inline_asm_convergent(
+                ctx,
+                rewriter,
+                op,
+                void_ty.into(),
+                operands,
+                ptx,
+                constraints,
+            );
+        }
+    }
+    rewriter.erase_operation(ctx, op);
+    Ok(())
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for WgmmaCommitGroupSyncAlignedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_wgmma_control(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "llvm__nvvm_dwgmma_dcommit_ugroup_dsync_daligned",
+            "wgmma.commit_group.sync.aligned;",
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for WgmmaFenceSyncAlignedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_wgmma_control(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "llvm_nvvm_wgmma_fence_sync_aligned",
+            "wgmma.fence.sync.aligned;",
+            false,
+        )
+    }
+}
+
+#[op_interface_impl]
+impl MirToLlvmConversion for WgmmaWaitGroupSyncAlignedOp {
+    fn convert(
+        &self,
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        _operands_info: &OperandsInfo,
+    ) -> Result<()> {
+        convert_generated_wgmma_control(
+            ctx,
+            rewriter,
+            self.get_operation(),
+            "llvm__nvvm_dwgmma_dwait_ugroup_dsync_daligned",
+            "wgmma.wait_group.sync.aligned $0;",
+            true,
+        )
+    }
+}
diff --git a/crates/mir-lower/src/convert/intrinsics/mod.rs b/crates/mir-lower/src/convert/intrinsics/mod.rs
index 460c8de290..abf1551702 100644
--- a/crates/mir-lower/src/convert/intrinsics/mod.rs
+++ b/crates/mir-lower/src/convert/intrinsics/mod.rs
@@ -51,7 +51,7 @@
 //! # Module Organization
 //!
 //! Everything `intrinsics/catalog.json` describes is lowered by
-//! `convert/generated_intrinsics.rs` -- beside this module, not inside it (it is
+//! `convert/generated_intrinsics/` -- beside this module, not inside it (it is
 //! a private module, so this is a path rather than a link). What follows is the
 //! hand-written converters, one row per file. Every module name in the table is
 //! an intra-doc link on purpose: the docs gate runs under `-D warnings`, so a row
diff --git a/crates/mir-lower/src/convert/ops/aggregate.rs b/crates/mir-lower/src/convert/ops/aggregate.rs
deleted file mode 100644
index e60d3e5214..0000000000
--- a/crates/mir-lower/src/convert/ops/aggregate.rs
+++ /dev/null
@@ -1,4967 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-//! Aggregate operation conversion: `dialect-mir` → LLVM dialect.
-//!
-//! Converts `dialect-mir` aggregate operations (structs, tuples, enums) to
-//! their LLVM dialect equivalents.
-//!
-//! # Operations
-//!
-//! | MIR Operation            | LLVM Operation(s)                    | Description            |
-//! |--------------------------|--------------------------------------|------------------------|
-//! | `mir.extract_field`      | `llvm.extractvalue`                  | Get struct/tuple field |
-//! | `mir.insert_field`       | `llvm.insertvalue`                   | Set struct/tuple field |
-//! | `mir.construct_struct`   | `llvm.undef` + `llvm.insertvalue`    | Build struct           |
-//! | `mir.construct_tuple`    | `llvm.undef` + `llvm.insertvalue`    | Build tuple            |
-//! | `mir.construct_slice`    | `llvm.undef` + `llvm.insertvalue`    | Build slice fat ptr    |
-//! | `mir.construct_enum`     | `llvm.undef` + `llvm.insertvalue`    | Build enum             |
-//! | `mir.get_discriminant`   | `llvm.extractvalue`                  | Get enum tag           |
-//! | `mir.set_discriminant`   | `llvm.getelementptr` + `llvm.store`  | Write enum tag         |
-//! | `mir.enum_payload`       | `llvm.extractvalue`                  | Get enum payload       |
-//!
-//! # Enum Representation
-//!
-//! Enums use rustc's physical layout, not a cuda-oxide-only tagged struct.
-//! `build_enum_slot_map` places the direct tag or niche carrier and every
-//! payload at rustc's byte offsets, reuses identical overlapping storage, and
-//! routes differently typed overlaps through byte-addressed memory. `Single`
-//! and `Empty` layouts have no carrier at all.
-//!
-//! A direct tag holds the variant's DECLARED discriminant value, not its
-//! position. For `core::cmp::Ordering`, `Less` therefore stores -1 (the i8 bit
-//! pattern 255), `Equal` stores 0, and `Greater` stores 1. A niche layout
-//! instead uses rustc's wrapping `niche_start + variant_offset` encoding and
-//! introduces no extra tag.
-
-use crate::convert::enum_payload_storage::{coerce_enum_payload_value, enum_payload_storage_type};
-use crate::convert::types::{
-    EnumSlotMap, StructLayoutInfo, StructSlotMap, build_enum_slot_map, build_struct_slot_map,
-    build_union_storage_type, convert_type, is_zero_sized_type, llvm_byte_faithful_twin,
-    llvm_packed_struct_contains_pointer_in_address_space, llvm_type_contains_i1,
-    llvm_type_size_align, make_slice_struct, mir_element_stride, mir_type_abi_align,
-    packed_shared_internal_abi_info,
-};
-use dialect_mir::ops::{
-    MirConstantOp, MirConstructEnumOp, MirEnumPayloadOp, MirExtractFieldOp, MirFieldAddrOp,
-    MirInsertFieldOp, MirSetDiscriminantOp,
-};
-use dialect_mir::types::{
-    EnumCarrierKind, EnumLayoutKind, MirArrayType, MirDisjointSliceType, MirEnumType, MirPtrType,
-    MirSliceType, MirStructType, MirTupleType, MirUnionType,
-};
-use llvm_export::attributes::{ICmpPredicateAttr, IntegerOverflowFlagsAttr};
-use llvm_export::op_interfaces::{
-    CastOpInterface, CastOpWithNNegInterface, IntBinArithOpWithOverflowFlag,
-};
-use llvm_export::ops as llvm;
-use llvm_export::types as llvm_types;
-use pliron::builtin::types::{IntegerType, Signedness};
-use pliron::context::{Context, Ptr};
-use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
-use pliron::irbuild::inserter::Inserter;
-use pliron::irbuild::rewriter::Rewriter;
-use pliron::location::Located;
-use pliron::op::Op;
-use pliron::operation::Operation;
-use pliron::result::Result;
-use pliron::r#type::{TypeHandle, Typed};
-use pliron::utils::apint::APInt;
-use pliron::value::Value;
-use std::num::NonZeroUsize;
-
-fn anyhow_to_pliron(e: anyhow::Error) -> pliron::result::Error {
-    pliron::input_error_noloc!("{e}")
-}
-
-/// How the MIR-level field indices of an aggregate operand map onto the
-/// lowered LLVM aggregate.
-enum AggregateSlots {
-    /// Lowered from a `MirStructType`/`MirTupleType`: use the slot map the
-    /// type converter built (accounts for reordering, `[N x i8]` padding
-    /// slots and stripped ZST fields).
-    Mapped(StructSlotMap),
-    /// The MIR index is already the final LLVM index. Sound only for
-    /// aggregates whose lowered layout is index-preserving by construction:
-    /// arrays and slice fat pointers (`{ ptr, i64 }`).
-    Identity,
-}
-
-/// Resolve how field indices of `aggregate` map onto its lowered type.
-///
-/// Recover-or-error (issue #128): when the operand has no recorded
-/// `MirStructType`/`MirTupleType` conversion history, identity indexing is
-/// only sound for aggregates the converter lowers without reordering,
-/// padding, or ZST stripping: arrays and slice fat pointers. Anything
-/// else is a lowering bug; guessing identity there silently reads or
-/// writes the wrong field, so we error out loudly instead.
-fn resolve_aggregate_slots(
-    ctx: &mut Context,
-    operands_info: &OperandsInfo,
-    aggregate: Value,
-) -> Result<AggregateSlots> {
-    let layout = operands_info
-        .lookup_most_recent_of_type::<MirStructType>(ctx, aggregate)
-        .map(|struct_ref| StructLayoutInfo::of_struct(&struct_ref))
-        .or_else(|| {
-            operands_info
-                .lookup_most_recent_of_type::<MirTupleType>(ctx, aggregate)
-                .map(|tuple_ref| StructLayoutInfo::of_tuple(&tuple_ref))
-        });
-
-    if let Some(layout) = layout {
-        let map = build_struct_slot_map(ctx, &layout).map_err(anyhow_to_pliron)?;
-        return Ok(AggregateSlots::Mapped(map));
-    }
-
-    // Arrays keep their element indices: `[N x T]` has no reorder, no
-    // padding, no ZST stripping.
-    let is_array_history = operands_info
-        .lookup_most_recent_of_type::<MirArrayType>(ctx, aggregate)
-        .is_some();
-    // Slices lower to the `{ ptr, i64 }` fat pointer, where index 0 = ptr
-    // and index 1 = len by construction.
-    let is_slice_history = operands_info
-        .lookup_most_recent_of_type::<MirSliceType>(ctx, aggregate)
-        .is_some()
-        || operands_info
-            .lookup_most_recent_of_type::<MirDisjointSliceType>(ctx, aggregate)
-            .is_some();
-    if is_array_history || is_slice_history {
-        return Ok(AggregateSlots::Identity);
-    }
-
-    // No conversion history at all (e.g. a slice reconstructed in the entry
-    // prologue, which is born as an LLVM struct). Identity is still fine if
-    // the current type is a slice fat pointer or an LLVM array. A disjoint
-    // slice with a runtime row width is the same case one word longer: every
-    // runtime index space today carries a single `u32` row width, and the struct the type
-    // converter builds for it (`make_disjoint_slice_struct`) is
-    // index-preserving by construction, exactly like the two-field fat
-    // pointer. Both shape checks share the two-field caveat that an unnamed
-    // user struct with the identical lowered layout would be accepted too;
-    // that has been the accepted trade-off for `{ ptr, i64 }` since issue
-    // #128, and a struct needing a slot map still errors below whenever its
-    // lowered shape differs (padding slots, reordering, other field types).
-    let aggregate_ty = aggregate.get_type(ctx);
-    let slice_struct_ty = make_slice_struct(ctx);
-    let row_width_slice_struct_ty = {
-        // The one runtime layout current `SpaceLayout` impls produce: a
-        // single u32 row width. Built through the real constructor so this
-        // check cannot drift from the lowered shape. A future space with a
-        // different `Data` shape is not listed here and thus fails closed
-        // into the refuse-to-guess error until this site learns it.
-        let width_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-        crate::convert::types::make_disjoint_slice_struct(ctx, &[width_ty])
-            .map_err(anyhow_to_pliron)?
-    };
-    let is_llvm_array = aggregate_ty
-        .deref(ctx)
-        .is::<llvm_export::types::ArrayType>();
-    if aggregate_ty == slice_struct_ty || aggregate_ty == row_width_slice_struct_ty || is_llvm_array
-    {
-        return Ok(AggregateSlots::Identity);
-    }
-
-    let ty_disp = aggregate_ty.deref(ctx).disp(ctx).to_string();
-    pliron::input_err_noloc!(
-        "Cannot map field indices for aggregate of type {ty_disp}: no struct/tuple \
-         conversion history was recorded for this operand, and identity indexing is \
-         only sound for arrays and slice fat pointers (with or without the runtime \
-         row-width word). Refusing to guess a field mapping (issue #128)."
-    )
-}
-
-/// Convert `mir.extract_field` to `llvm.extractvalue`.
-///
-/// Handles scalar-lowered newtype case: if the operand is a scalar (e.g., `ThreadIndex`),
-/// no extraction is needed.
-///
-/// The declaration-order field index is mapped to the LLVM slot via
-/// [`resolve_aggregate_slots`], which shares the type converter's view of
-/// the struct (reorder, `[N x i8]` padding slots, stripped ZSTs). If
-/// extracting a ZST field, we return undef of its (empty) type.
-pub(crate) fn convert_extract_field(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    let aggregate = op.deref(ctx).get_operand(0);
-
-    let extract_op = MirExtractFieldOp::new(op);
-    let decl_index = match extract_op.get_attr_index(ctx) {
-        Some(attr) => attr.0 as usize,
-        None => return pliron::input_err_noloc!("Missing index attribute on extract_field"),
-    };
-
-    if operands_info
-        .lookup_most_recent_of_type::<MirUnionType>(ctx, aggregate)
-        .is_some()
-    {
-        return convert_extract_union_field(
-            ctx,
-            rewriter,
-            op,
-            aggregate,
-            decl_index,
-            operands_info,
-        );
-    }
-
-    let is_scalar = aggregate
-        .get_type(ctx)
-        .deref(ctx)
-        .downcast_ref::<IntegerType>()
-        .is_some();
-
-    if is_scalar {
-        rewriter.replace_operation_with_values(ctx, op, vec![aggregate]);
-        return Ok(());
-    }
-
-    let llvm_index = match resolve_aggregate_slots(ctx, operands_info, aggregate)? {
-        AggregateSlots::Mapped(map) => match map.decl_to_llvm.get(decl_index) {
-            Some(Some(slot)) => *slot,
-            Some(None) => {
-                // ZST field: stripped from the LLVM struct, so there is
-                // nothing to extract. Materialize undef of its empty type.
-                let zst_ty = map.field_llvm_types[decl_index];
-                let undef_op = llvm::UndefOp::new(ctx, zst_ty);
-                rewriter.insert_operation(ctx, undef_op.get_operation());
-                rewriter.replace_operation(ctx, op, undef_op.get_operation());
-                return Ok(());
-            }
-            None => {
-                return pliron::input_err_noloc!(
-                    "extract_field index {} out of bounds for aggregate with {} fields",
-                    decl_index,
-                    map.decl_to_llvm.len()
-                );
-            }
-        },
-        AggregateSlots::Identity => decl_index as u32,
-    };
-
-    let llvm_extract = llvm::ExtractValueOp::new(ctx, aggregate, vec![llvm_index])?;
-    rewriter.insert_operation(ctx, llvm_extract.get_operation());
-    rewriter.replace_operation(ctx, op, llvm_extract.get_operation());
-
-    Ok(())
-}
-
-/// Convert `mir.insert_field` to `llvm.insertvalue`.
-///
-/// Operands: `[aggregate, new_value]`
-/// Returns a new aggregate with the field at `insert_index` replaced.
-///
-/// The declaration-order field index is mapped to the LLVM slot via
-/// [`resolve_aggregate_slots`] (arrays keep their element index). If
-/// inserting a ZST field, we return the original aggregate unchanged.
-pub(crate) fn convert_insert_field(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    let aggregate = op.deref(ctx).get_operand(0);
-    let new_value = op.deref(ctx).get_operand(1);
-
-    let insert_op = MirInsertFieldOp::new(op);
-    let decl_index = match insert_op.get_attr_insert_index(ctx) {
-        Some(attr) => attr.0 as usize,
-        None => return pliron::input_err_noloc!("Missing insert_index attribute on insert_field"),
-    };
-
-    if operands_info
-        .lookup_most_recent_of_type::<MirUnionType>(ctx, aggregate)
-        .is_some()
-    {
-        return convert_insert_union_field(
-            ctx,
-            rewriter,
-            op,
-            aggregate,
-            new_value,
-            decl_index,
-            operands_info,
-        );
-    }
-
-    let llvm_index = match resolve_aggregate_slots(ctx, operands_info, aggregate)? {
-        AggregateSlots::Mapped(map) => match map.decl_to_llvm.get(decl_index) {
-            Some(Some(slot)) => *slot,
-            Some(None) => {
-                // ZST field: stripped from the LLVM struct, so inserting
-                // into it is a no-op. Forward the aggregate unchanged.
-                rewriter.replace_operation_with_values(ctx, op, vec![aggregate]);
-                return Ok(());
-            }
-            None => {
-                return pliron::input_err_noloc!(
-                    "insert_field index {} out of bounds for aggregate with {} fields",
-                    decl_index,
-                    map.decl_to_llvm.len()
-                );
-            }
-        },
-        AggregateSlots::Identity => decl_index as u32,
-    };
-
-    let llvm_insert = llvm::InsertValueOp::new(ctx, aggregate, new_value, vec![llvm_index]);
-    rewriter.insert_operation(ctx, llvm_insert.get_operation());
-    rewriter.replace_operation(ctx, op, llvm_insert.get_operation());
-
-    Ok(())
-}
-
-fn union_type_of_operand(
-    ctx: &Context,
-    operands_info: &OperandsInfo,
-    value: Value,
-) -> Result<MirUnionType> {
-    operands_info
-        .lookup_most_recent_of_type::<MirUnionType>(ctx, value)
-        .map(|union_ty| union_ty.clone())
-        .ok_or_else(|| {
-            pliron::create_error!(
-                pliron::location::Location::Unknown,
-                pliron::result::ErrorKind::VerificationFailed,
-                pliron::result::StringError(
-                    "Expected MirUnionType conversion history for union value".to_string()
-                )
-            )
-        })
-}
-
-/// Read one typed view of a union's shared bytes.
-fn convert_extract_union_field(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    union_value: Value,
-    field_index: usize,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    let union_ty = union_type_of_operand(ctx, operands_info, union_value)?;
-    let Some(field_mir_ty) = union_ty.get_field_type(field_index) else {
-        return pliron::input_err_noloc!(
-            "union field index {} is out of bounds for `{}`",
-            field_index,
-            union_ty.name()
-        );
-    };
-    let field_llvm_ty = convert_type(ctx, field_mir_ty).map_err(anyhow_to_pliron)?;
-    if is_zero_sized_type(ctx, field_llvm_ty) {
-        let undef = llvm::UndefOp::new(ctx, field_llvm_ty);
-        rewriter.insert_operation(ctx, undef.get_operation());
-        rewriter.replace_operation(ctx, op, undef.get_operation());
-        return Ok(());
-    }
-
-    let storage_ty = build_union_storage_type(ctx, &union_ty).map_err(anyhow_to_pliron)?;
-    let ptr = spill_enum_value(ctx, rewriter, union_value, storage_ty, union_ty.abi_align());
-    let load = llvm::LoadOp::new(ctx, ptr, field_llvm_ty);
-    llvm_export::ops::set_op_alignment(ctx, load.get_operation(), union_ty.abi_align() as u32);
-    rewriter.insert_operation(ctx, load.get_operation());
-    rewriter.replace_operation(ctx, op, load.get_operation());
-    Ok(())
-}
-
-/// Write one typed view at byte zero while preserving the rest of the union.
-fn convert_insert_union_field(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    union_value: Value,
-    new_value: Value,
-    field_index: usize,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    let union_ty = union_type_of_operand(ctx, operands_info, union_value)?;
-    let Some(field_mir_ty) = union_ty.get_field_type(field_index) else {
-        return pliron::input_err_noloc!(
-            "union field index {} is out of bounds for `{}`",
-            field_index,
-            union_ty.name()
-        );
-    };
-    let field_llvm_ty = convert_type(ctx, field_mir_ty).map_err(anyhow_to_pliron)?;
-    if is_zero_sized_type(ctx, field_llvm_ty) {
-        rewriter.replace_operation_with_values(ctx, op, vec![union_value]);
-        return Ok(());
-    }
-
-    let storage_ty = build_union_storage_type(ctx, &union_ty).map_err(anyhow_to_pliron)?;
-    let ptr = spill_enum_value(ctx, rewriter, union_value, storage_ty, union_ty.abi_align());
-    let store = llvm::StoreOp::new(ctx, new_value, ptr);
-    llvm_export::ops::set_op_alignment(ctx, store.get_operation(), union_ty.abi_align() as u32);
-    rewriter.insert_operation(ctx, store.get_operation());
-
-    let load = llvm::LoadOp::new(ctx, ptr, storage_ty);
-    llvm_export::ops::set_op_alignment(ctx, load.get_operation(), union_ty.abi_align() as u32);
-    rewriter.insert_operation(ctx, load.get_operation());
-    rewriter.replace_operation(ctx, op, load.get_operation());
-    Ok(())
-}
-
-/// Convert `mir.construct_struct` to a chain of `llvm.insertvalue` operations.
-///
-/// Builds a struct by:
-/// 1. Creating an `undef` value of the lowered struct type
-/// 2. Inserting each operand at the LLVM slot its field landed in
-///
-/// Operand order matches field order in the struct type (declaration order).
-/// The LLVM struct type and the slot of each field both come from
-/// [`build_struct_slot_map`], so the insert indices skip `[N x i8]` padding
-/// slots exactly the way the type converter laid them out. ZST fields
-/// (e.g. PhantomData) have no slot and are skipped.
-pub(crate) fn convert_construct_struct(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let (result_ty, operands) = {
-        let mir_op = op.deref(ctx);
-        let result_ty = mir_op.get_result(0).get_type(ctx);
-        let operands: Vec<_> = mir_op.operands().collect();
-        (result_ty, operands)
-    };
-
-    let layout = {
-        let ty_ref = result_ty.deref(ctx);
-        match ty_ref.downcast_ref::<MirStructType>() {
-            Some(s) => StructLayoutInfo::of_struct(s),
-            None => {
-                return pliron::input_err_noloc!(
-                    "MirConstructStructOp result type must be MirStructType"
-                );
-            }
-        }
-    };
-
-    if operands.len() != layout.field_types.len() {
-        return pliron::input_err_noloc!(
-            "construct_struct has {} operands for a struct with {} fields",
-            operands.len(),
-            layout.field_types.len()
-        );
-    }
-
-    let map = build_struct_slot_map(ctx, &layout).map_err(anyhow_to_pliron)?;
-
-    // A divergent rustc layout is constructible by value only when the slot
-    // map proved that a sequential LLVM packed struct reproduces every byte.
-    // Overlapping/union-like legacy struct models remain unrepresentable.
-    if !map.by_value_layout_faithful {
-        return pliron::input_err_noloc!(
-            "constructing a struct whose rustc layout cannot be represented by an LLVM \
-             struct value is not supported; keep the value behind a pointer and access \
-             fields through their byte-accurate address path"
-        );
-    }
-
-    // A packed struct containing AS3 remains target-dependent as a physical
-    // memory image. The internal-call ABI exception is safe to construct in SSA
-    // because its return boundary recursively rebuilds every supported AS3 leaf
-    // into a target-stable generic-pointer carrier before the aggregate crosses
-    // the function ABI.
-    if llvm_packed_struct_contains_pointer_in_address_space(
-        ctx,
-        map.llvm_struct_ty,
-        llvm_types::address_space::SHARED,
-    ) && packed_shared_internal_abi_info(ctx, result_ty)
-        .map_err(anyhow_to_pliron)?
-        .is_none()
-    {
-        return pliron::input_err_noloc!(
-            "constructing a packed aggregate containing a shared-memory pointer by value is \
-             target-mode dependent and is not yet supported"
-        );
-    }
-
-    let undef_op = llvm::UndefOp::new(ctx, map.llvm_struct_ty);
-    rewriter.insert_operation(ctx, undef_op.get_operation());
-    let mut current_struct = undef_op.get_operation().deref(ctx).get_result(0);
-
-    let mut last_insert: Option<Ptr<Operation>> = None;
-    // Walk in memory order so the insertvalue chain ascends slot indices.
-    for &decl_idx in &layout.mem_to_decl {
-        let Some(slot) = map.decl_to_llvm[decl_idx] else {
-            continue; // ZST field: no slot in the LLVM struct.
-        };
-
-        let insert_op =
-            llvm::InsertValueOp::new(ctx, current_struct, operands[decl_idx], vec![slot]);
-        rewriter.insert_operation(ctx, insert_op.get_operation());
-        current_struct = insert_op.get_operation().deref(ctx).get_result(0);
-        last_insert = Some(insert_op.get_operation());
-    }
-
-    match last_insert {
-        Some(last_op) => rewriter.replace_operation(ctx, op, last_op),
-        None => rewriter.replace_operation(ctx, op, undef_op.get_operation()),
-    }
-
-    Ok(())
-}
-
-/// Convert `mir.construct_tuple` to a chain of `llvm.insertvalue` operations.
-///
-/// Tuples are represented as LLVM structs. Same construction pattern as
-/// structs, and like structs the element slots come from
-/// [`build_struct_slot_map`] (identity order, no padding; ZST elements are
-/// stripped and skipped).
-pub(crate) fn convert_construct_tuple(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let (result_ty, operands) = {
-        let mir_op = op.deref(ctx);
-        let result_ty = mir_op.get_result(0).get_type(ctx);
-        let operands: Vec<_> = mir_op.operands().collect();
-        (result_ty, operands)
-    };
-
-    let layout = {
-        let ty_ref = result_ty.deref(ctx);
-        match ty_ref.downcast_ref::<MirTupleType>() {
-            Some(t) => StructLayoutInfo::of_tuple(t),
-            None => {
-                return pliron::input_err_noloc!(
-                    "MirConstructTupleOp result type must be MirTupleType"
-                );
-            }
-        }
-    };
-
-    if operands.len() != layout.field_types.len() {
-        return pliron::input_err_noloc!(
-            "construct_tuple has {} operands for a tuple with {} elements",
-            operands.len(),
-            layout.field_types.len()
-        );
-    }
-
-    let map = build_struct_slot_map(ctx, &layout).map_err(anyhow_to_pliron)?;
-
-    let undef_op = llvm::UndefOp::new(ctx, map.llvm_struct_ty);
-    rewriter.insert_operation(ctx, undef_op.get_operation());
-    let mut current_tuple = undef_op.get_operation().deref(ctx).get_result(0);
-
-    let mut last_insert: Option<Ptr<Operation>> = None;
-    for (mir_idx, operand) in operands.iter().enumerate() {
-        let Some(slot) = map.decl_to_llvm[mir_idx] else {
-            continue; // ZST element: no slot in the LLVM struct.
-        };
-
-        let insert_op = llvm::InsertValueOp::new(ctx, current_tuple, *operand, vec![slot]);
-        rewriter.insert_operation(ctx, insert_op.get_operation());
-        current_tuple = insert_op.get_operation().deref(ctx).get_result(0);
-        last_insert = Some(insert_op.get_operation());
-    }
-
-    match last_insert {
-        Some(last_op) => rewriter.replace_operation(ctx, op, last_op),
-        None => rewriter.replace_operation(ctx, op, undef_op.get_operation()),
-    }
-
-    Ok(())
-}
-
-/// Convert `mir.construct_slice` to `llvm.undef` + two `llvm.insertvalue`s.
-///
-/// `MirSliceType` lowers to the `{ ptr, i64 }` fat-pointer struct, where
-/// field 0 is the data pointer and field 1 is the element count by
-/// construction (the same layout the entry prologue's `reconstruct_slice`
-/// and the Unsize cast path build). `MirSliceType::kind` is intentionally
-/// semantic-only: all reference/raw-pointer kinds share this physical layout
-/// and no LLVM alias metadata is inferred here.
-pub(crate) fn convert_construct_slice(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let (result_ty, data_val, len_val) = {
-        let mir_op = op.deref(ctx);
-        (
-            mir_op.get_result(0).get_type(ctx),
-            mir_op.get_operand(0),
-            mir_op.get_operand(1),
-        )
-    };
-
-    if !result_ty.deref(ctx).is::<MirSliceType>() {
-        return pliron::input_err_noloc!("MirConstructSliceOp result type must be MirSliceType");
-    }
-
-    let slice_struct_ty = make_slice_struct(ctx);
-
-    let undef_op = llvm::UndefOp::new(ctx, slice_struct_ty);
-    rewriter.insert_operation(ctx, undef_op.get_operation());
-    let undef_val = undef_op.get_operation().deref(ctx).get_result(0);
-
-    let insert_ptr = llvm::InsertValueOp::new(ctx, undef_val, data_val, vec![0]);
-    rewriter.insert_operation(ctx, insert_ptr.get_operation());
-    let with_ptr = insert_ptr.get_operation().deref(ctx).get_result(0);
-
-    let insert_len = llvm::InsertValueOp::new(ctx, with_ptr, len_val, vec![1]);
-    rewriter.insert_operation(ctx, insert_len.get_operation());
-
-    rewriter.replace_operation(ctx, op, insert_len.get_operation());
-
-    Ok(())
-}
-
-/// Convert `mir.construct_disjoint_slice` to a chain of `llvm.insertvalue`
-/// operations.
-///
-/// The same shape as [`convert_construct_slice`], one insert longer per
-/// runtime layout word the index space carries. The struct type comes from
-/// [`make_disjoint_slice_struct`], the same constructor the type converter
-/// uses, so the field order here cannot drift from the lowered layout that
-/// [`resolve_aggregate_slots`] indexes identically.
-pub(crate) fn convert_construct_disjoint_slice(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let (result_ty, operands) = {
-        let mir_op = op.deref(ctx);
-        let operands: Vec<_> = mir_op.operands().collect();
-        (mir_op.get_result(0).get_type(ctx), operands)
-    };
-
-    let space_tys = {
-        let ty_ref = result_ty.deref(ctx);
-        match ty_ref.downcast_ref::<MirDisjointSliceType>() {
-            Some(slice_ty) => slice_ty.space_types().to_vec(),
-            None => {
-                return pliron::input_err_noloc!(
-                    "MirConstructDisjointSliceOp result type must be MirDisjointSliceType"
-                );
-            }
-        }
-    };
-
-    // The verifier already pins the operand count to the result type. Check
-    // it here too: this pass runs on operations the verifier accepted, and a
-    // short operand list would otherwise index past the end below.
-    let expected_operands = 2 + space_tys.len();
-    if operands.len() != expected_operands {
-        return pliron::input_err_noloc!(
-            "MirConstructDisjointSliceOp expects {expected_operands} operands, got {}",
-            operands.len()
-        );
-    }
-
-    let slice_struct_ty = crate::convert::types::make_disjoint_slice_struct(ctx, &space_tys)
-        .map_err(anyhow_to_pliron)?;
-
-    let undef_op = llvm::UndefOp::new(ctx, slice_struct_ty);
-    rewriter.insert_operation(ctx, undef_op.get_operation());
-    let mut current = undef_op.get_operation().deref(ctx).get_result(0);
-    let mut last_insert = undef_op.get_operation();
-
-    for (slot, operand) in operands.into_iter().enumerate() {
-        let insert = llvm::InsertValueOp::new(ctx, current, operand, vec![slot as u32]);
-        rewriter.insert_operation(ctx, insert.get_operation());
-        current = insert.get_operation().deref(ctx).get_result(0);
-        last_insert = insert.get_operation();
-    }
-
-    rewriter.replace_operation(ctx, op, last_insert);
-
-    Ok(())
-}
-
-/// Convert `mir.construct_array` to a chain of `llvm.insertvalue` operations.
-///
-/// Arrays are represented as LLVM arrays. Same construction pattern as structs:
-/// 1. Create `undef` of the array type
-/// 2. Insert each element at its index
-pub(crate) fn convert_construct_array(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let (result_ty, operands) = {
-        let mir_op = op.deref(ctx);
-        let result_ty = mir_op.get_result(0).get_type(ctx);
-        let operands: Vec<_> = mir_op.operands().collect();
-        (result_ty, operands)
-    };
-
-    let (element_ty, array_size) = {
-        let ty_ref = result_ty.deref(ctx);
-        match ty_ref.downcast_ref::<MirArrayType>() {
-            Some(a) => (a.element_type(), a.size()),
-            None => {
-                return pliron::input_err_noloc!(
-                    "MirConstructArrayOp result type must be MirArrayType"
-                );
-            }
-        }
-    };
-
-    let llvm_element_ty = convert_type(ctx, element_ty).map_err(anyhow_to_pliron)?;
-    let llvm_array_ty = llvm_export::types::ArrayType::get(ctx, llvm_element_ty, array_size);
-
-    let undef_op = llvm::UndefOp::new(ctx, llvm_array_ty.into());
-    rewriter.insert_operation(ctx, undef_op.get_operation());
-    let mut current_array = undef_op.get_operation().deref(ctx).get_result(0);
-
-    let mut last_insert: Option<Ptr<Operation>> = None;
-    for (i, operand) in operands.iter().enumerate() {
-        let insert_op = llvm::InsertValueOp::new(ctx, current_array, *operand, vec![i as u32]);
-        rewriter.insert_operation(ctx, insert_op.get_operation());
-        current_array = insert_op.get_operation().deref(ctx).get_result(0);
-        last_insert = Some(insert_op.get_operation());
-    }
-
-    match last_insert {
-        Some(last_op) => rewriter.replace_operation(ctx, op, last_op),
-        None => rewriter.replace_operation(ctx, op, undef_op.get_operation()),
-    }
-
-    Ok(())
-}
-/// Convert `mir.extract_array_element` to LLVM operations.
-///
-/// A runtime index normally requires materializing the array in memory because
-/// LLVM `extractvalue` accepts only constant indices. When the index is proven
-/// to be `urem value, C`, however, it is in `0..C`. For small `C` within the
-/// array bounds, emit one constant `extractvalue` per candidate and select the
-/// runtime result in SSA. This avoids the temporary alloca that otherwise
-/// becomes NVPTX local memory.
-///
-/// Unbounded, oversized, or otherwise unsupported indices retain the existing
-/// alloca+store+GEP+load fallback.
-pub(crate) fn convert_extract_array_element(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    // One shared cap for the candidate chain, so the mir-transforms
-    // canonicalization and this lowering fast path cannot drift apart.
-    use dialect_mir::ops::MAX_SCALARIZED_CANDIDATES;
-
-    fn integer_constant_u64(ctx: &Context, value: Value) -> Option<u64> {
-        let defining_op = value.defining_op()?;
-        let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, ctx)?;
-        let attribute = constant.get_value(ctx);
-        let integer = attribute.downcast_ref::<pliron::builtin::attributes::IntegerAttr>()?;
-        let integer_value = integer.value();
-        // `APInt::to_u64` truncates wider values, so a >64-bit constant could
-        // be misread as a small in-range divisor. Fail closed on such widths.
-        (integer_value.bw() <= 64).then(|| integer_value.to_u64())
-    }
-
-    fn bounded_urem_candidate_count(ctx: &Context, index: Value, array_size: u64) -> Option<u64> {
-        let defining_op = index.defining_op()?;
-        Operation::get_op::<llvm::URemOp>(defining_op, ctx)?;
-
-        let divisor = defining_op.deref(ctx).get_operand(1);
-        let candidate_count = integer_constant_u64(ctx, divisor)?;
-        (candidate_count > 0
-            && candidate_count <= array_size
-            && candidate_count <= MAX_SCALARIZED_CANDIDATES)
-            .then_some(candidate_count)
-    }
-
-    fn integer_constant_like(
-        ctx: &mut Context,
-        rewriter: &mut DialectConversionRewriter,
-        reference: Value,
-        value: u64,
-    ) -> Result<Value> {
-        let reference_ty = reference.get_type(ctx);
-        let width = reference_ty
-            .deref(ctx)
-            .downcast_ref::<IntegerType>()
-            .ok_or_else(|| {
-                pliron::input_error_noloc!(
-                    "mir.extract_array_element index must lower to an integer"
-                )
-            })?
-            .width();
-
-        let integer_ty = IntegerType::get(ctx, width, Signedness::Signless);
-        let attribute = pliron::builtin::attributes::IntegerAttr::new(
-            integer_ty,
-            APInt::from_u64(
-                value,
-                NonZeroUsize::new(width as usize).expect("integer width is nonzero"),
-            ),
-        );
-        let constant = llvm::ConstantOp::new(ctx, attribute.into());
-        rewriter.insert_operation(ctx, constant.get_operation());
-        Ok(constant.get_operation().deref(ctx).get_result(0))
-    }
-
-    let array_val = op.deref(ctx).get_operand(0);
-    let index_val = op.deref(ctx).get_operand(1);
-
-    let (element_ty, array_size) = {
-        match operands_info.lookup_most_recent_of_type::<MirArrayType>(ctx, array_val) {
-            Some(r) => (r.element_type(), r.size()),
-            None => return pliron::input_err_noloc!("Expected MirArrayType"),
-        }
-    };
-
-    if let Some(candidate_count) = bounded_urem_candidate_count(ctx, index_val, array_size) {
-        let mut candidates = Vec::with_capacity(candidate_count as usize);
-        for candidate_index in 0..candidate_count {
-            let extract = llvm::ExtractValueOp::new(ctx, array_val, vec![candidate_index as u32])?;
-            rewriter.insert_operation(ctx, extract.get_operation());
-            candidates.push(extract.get_operation().deref(ctx).get_result(0));
-        }
-
-        let mut selected = *candidates
-            .last()
-            .expect("candidate count is proven nonzero");
-        for candidate_index in (0..candidates.len().saturating_sub(1)).rev() {
-            let candidate_constant =
-                integer_constant_like(ctx, rewriter, index_val, candidate_index as u64)?;
-            let compare =
-                llvm::ICmpOp::new(ctx, ICmpPredicateAttr::EQ, index_val, candidate_constant);
-            rewriter.insert_operation(ctx, compare.get_operation());
-            let condition = compare.get_operation().deref(ctx).get_result(0);
-
-            let select = llvm::SelectOp::new(ctx, condition, candidates[candidate_index], selected);
-            rewriter.insert_operation(ctx, select.get_operation());
-            selected = select.get_operation().deref(ctx).get_result(0);
-        }
-
-        rewriter.replace_operation_with_values(ctx, op, vec![selected]);
-        return Ok(());
-    }
-
-    let llvm_element_ty = convert_type(ctx, element_ty).map_err(anyhow_to_pliron)?;
-    let llvm_array_ty = llvm_export::types::ArrayType::get(ctx, llvm_element_ty, array_size);
-    let abi_align = mir_type_abi_align(ctx, element_ty);
-
-    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-    let one_val = {
-        let one_apint = APInt::from_i64(1, NonZeroUsize::new(64).unwrap());
-        let one_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, one_apint);
-        let const_op = llvm::ConstantOp::new(ctx, one_attr.into());
-        rewriter.insert_operation(ctx, const_op.get_operation());
-        const_op.get_operation().deref(ctx).get_result(0)
-    };
-
-    let alloca_op = llvm::AllocaOp::new(ctx, llvm_array_ty.into(), one_val);
-    rewriter.insert_operation(ctx, alloca_op.get_operation());
-    if let Some(align) = abi_align {
-        llvm_export::ops::set_op_alignment(ctx, alloca_op.get_operation(), align as u32);
-    }
-    let array_ptr = alloca_op.get_operation().deref(ctx).get_result(0);
-
-    let store_op = llvm::StoreOp::new(ctx, array_val, array_ptr);
-    rewriter.insert_operation(ctx, store_op.get_operation());
-    if let Some(align) = abi_align {
-        llvm_export::ops::set_op_alignment(ctx, store_op.get_operation(), align as u32);
-    }
-
-    use llvm_export::ops::GepIndex;
-    let gep_indices = vec![GepIndex::Constant(0), GepIndex::Value(index_val)];
-    let gep_op = llvm::GetElementPtrOp::new(ctx, array_ptr, gep_indices, llvm_array_ty.into());
-    rewriter.insert_operation(ctx, gep_op.get_operation());
-    let element_ptr = gep_op.get_operation().deref(ctx).get_result(0);
-
-    let load_op = llvm::LoadOp::new(ctx, element_ptr, llvm_element_ty);
-    rewriter.insert_operation(ctx, load_op.get_operation());
-    if let Some(align) = abi_align {
-        llvm_export::ops::set_op_alignment(ctx, load_op.get_operation(), align as u32);
-    }
-    rewriter.replace_operation(ctx, op, load_op.get_operation());
-
-    Ok(())
-}
-
-/// Copy an enum value into a fresh stack slot and return the pointer.
-///
-/// This is how we reach a payload field that has no struct slot of its
-/// own (its bytes are shared with a different-typed field of another
-/// variant): once the value sits in memory, a byte-precise pointer can
-/// read or write any part of it, no struct field needed.
-///
-/// The slot is marked with the enum's real (rustc) alignment. The struct
-/// type alone can look under-aligned: `{ i8, [7 x i8] }` says "align 1"
-/// to LLVM, while Rust may require 8.
-///
-/// The alloca lands at the use site, same as
-/// [`convert_extract_array_element`]; the standard `opt -O2` run (SROA)
-/// removes it again. Hoisting these into the function's entry block is a
-/// known follow-up for the unoptimized (`CUDA_OXIDE_NO_OPT=1`) path.
-fn spill_enum_value(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    enum_val: Value,
-    llvm_struct_ty: TypeHandle,
-    abi_align: u64,
-) -> Value {
-    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-    let one_apint = APInt::from_i64(1, NonZeroUsize::new(64).unwrap());
-    let one_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, one_apint);
-    let one_const = llvm::ConstantOp::new(ctx, one_attr.into());
-    rewriter.insert_operation(ctx, one_const.get_operation());
-    let one_val = one_const.get_operation().deref(ctx).get_result(0);
-
-    let alloca_op = llvm::AllocaOp::new(ctx, llvm_struct_ty, one_val);
-    rewriter.insert_operation(ctx, alloca_op.get_operation());
-    if abi_align > 0 {
-        llvm_export::ops::set_op_alignment(ctx, alloca_op.get_operation(), abi_align as u32);
-    }
-    let slot_ptr = alloca_op.get_operation().deref(ctx).get_result(0);
-
-    let store_op = llvm::StoreOp::new(ctx, enum_val, slot_ptr);
-    rewriter.insert_operation(ctx, store_op.get_operation());
-    if abi_align > 0 {
-        llvm_export::ops::set_op_alignment(ctx, store_op.get_operation(), abi_align as u32);
-    }
-    slot_ptr
-}
-
-/// Pointer to `base + offset` bytes (`getelementptr i8, ptr base, offset`).
-///
-/// Used whenever rustc's physical byte offset cannot be represented faithfully
-/// by a typed LLVM aggregate GEP, as with overlapping enum payloads or packed
-/// struct fields.
-fn byte_offset_gep(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    base: Value,
-    offset: u64,
-) -> Value {
-    use llvm_export::ops::GepIndex;
-    let i8_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
-    let offset = emit_integer_constant(ctx, rewriter, 64, u128::from(offset));
-    let gep_op = llvm::GetElementPtrOp::new(ctx, base, vec![GepIndex::Value(offset)], i8_ty);
-    rewriter.insert_operation(ctx, gep_op.get_operation());
-    gep_op.get_operation().deref(ctx).get_result(0)
-}
-
-/// The physical carrier write required to select one source variant.
-/// `None` is a real semantic result for the untagged niche variant and for
-/// rustc's single inhabited variant; it must never be replaced by a guessed
-/// memory write.
-fn enum_carrier_bits_for_variant(
-    enum_ty: &MirEnumType,
-    variant: usize,
-) -> std::result::Result<Option<u128>, String> {
-    if variant >= enum_ty.variant_count() || enum_ty.variant_is_inhabited(variant) != Some(true) {
-        return Err(format!(
-            "cannot select uninhabited or missing variant {} of '{}'",
-            variant,
-            enum_ty.name()
-        ));
-    }
-
-    match enum_ty.layout_kind {
-        EnumLayoutKind::Direct => enum_ty
-            .variant_discriminants
-            .get(variant)
-            .copied()
-            .map(|bits| Some(u128::from(bits)))
-            .ok_or_else(|| format!("variant {} has no declared discriminant", variant)),
-        EnumLayoutKind::Niche => {
-            // This check deliberately comes before the encoded range check:
-            // rustc permits the untagged variant index to lie inside that
-            // range. Its range position is a dead niche value; selecting the
-            // actual untagged variant remains a no-op.
-            if variant == enum_ty.untagged_variant as usize {
-                return Ok(None);
-            }
-            if !(enum_ty.niche_variant_start as usize..=enum_ty.niche_variant_end as usize)
-                .contains(&variant)
-            {
-                return Err(format!(
-                    "inhabited variant {} is not representable by niche layout of '{}'",
-                    variant,
-                    enum_ty.name()
-                ));
-            }
-            let offset = (variant as u128) - u128::from(enum_ty.niche_variant_start);
-            let mut bits = enum_ty.niche_start().wrapping_add(offset);
-            if enum_ty.carrier_width < 128 {
-                bits &= (1u128 << enum_ty.carrier_width) - 1;
-            }
-            Ok(Some(bits))
-        }
-        EnumLayoutKind::Single if variant == enum_ty.single_variant as usize => Ok(None),
-        EnumLayoutKind::Single => Err(format!(
-            "variant {} is not the single inhabited variant of '{}'",
-            variant,
-            enum_ty.name()
-        )),
-        EnumLayoutKind::Empty => Err(format!("enum '{}' is uninhabited", enum_ty.name())),
-        EnumLayoutKind::Unknown => Err(format!(
-            "enum '{}' has unknown physical layout",
-            enum_ty.name()
-        )),
-    }
-}
-
-fn emit_integer_constant(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    width: u32,
-    bits: u128,
-) -> Value {
-    let ty = IntegerType::get(ctx, width, Signedness::Signless);
-    let attr = pliron::builtin::attributes::IntegerAttr::new(
-        ty,
-        APInt::from_u128(bits, NonZeroUsize::new(width as usize).unwrap()),
-    );
-    let op = llvm::ConstantOp::new(ctx, attr.into());
-    rewriter.insert_operation(ctx, op.get_operation());
-    op.get_operation().deref(ctx).get_result(0)
-}
-
-fn emit_carrier_constant(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    enum_ty: &MirEnumType,
-    carrier_ty: TypeHandle,
-    bits: u128,
-) -> Result<Value> {
-    let integer = emit_integer_constant(ctx, rewriter, enum_ty.carrier_width, bits);
-    match enum_ty.carrier_kind {
-        EnumCarrierKind::Integer => Ok(integer),
-        EnumCarrierKind::Pointer => {
-            let cast = llvm::IntToPtrOp::new(ctx, integer, carrier_ty);
-            rewriter.insert_operation(ctx, cast.get_operation());
-            Ok(cast.get_operation().deref(ctx).get_result(0))
-        }
-        _ => pliron::input_err_noloc!("enum carrier constant requested without a carrier"),
-    }
-}
-
-/// Convert a value to its byte-faithful storage twin: every `i1` leaf is
-/// zero-extended to its canonical `i8` memory byte, recursively through
-/// structs and arrays. Values without `i1` storage pass through unchanged.
-///
-/// This is the value-level half of [`llvm_byte_faithful_twin`]: the enum
-/// slot map claims twin-typed storage for bool-bearing payloads, and this
-/// produces the twin-typed value the store into that storage needs.
-fn canonicalize_bool_value_bytes(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    value: Value,
-) -> Result<Value> {
-    let ty = value.get_type(ctx);
-    if !llvm_type_contains_i1(ctx, ty) {
-        return Ok(value);
-    }
-    let is_scalar_i1 = ty
-        .deref(ctx)
-        .downcast_ref::<IntegerType>()
-        .is_some_and(|integer| integer.width() == 1);
-    if is_scalar_i1 {
-        let byte_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
-        let zext = llvm::ZExtOp::new_with_nneg(ctx, value, byte_ty, false);
-        rewriter.insert_operation(ctx, zext.get_operation());
-        return Ok(zext.get_operation().deref(ctx).get_result(0));
-    }
-    let Some(twin) = llvm_byte_faithful_twin(ctx, ty) else {
-        return pliron::input_err_noloc!(
-            "enum construction: bool storage in this value's shape cannot be canonicalized"
-        );
-    };
-    let element_count = {
-        let ty_ref = ty.deref(ctx);
-        if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-            struct_ty.fields().count() as u64
-        } else if let Some(array_ty) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-            array_ty.size()
-        } else {
-            return pliron::input_err_noloc!(
-                "enum construction: unexpected container for bool storage canonicalization"
-            );
-        }
-    };
-    let undef_op = llvm::UndefOp::new(ctx, twin);
-    rewriter.insert_operation(ctx, undef_op.get_operation());
-    let mut current = undef_op.get_operation().deref(ctx).get_result(0);
-    for index in 0..element_count {
-        let extract_op = llvm::ExtractValueOp::new(ctx, value, vec![index as u32])?;
-        rewriter.insert_operation(ctx, extract_op.get_operation());
-        let element = extract_op.get_operation().deref(ctx).get_result(0);
-        let converted = canonicalize_bool_value_bytes(ctx, rewriter, element)?;
-        let insert_op = llvm::InsertValueOp::new(ctx, current, converted, vec![index as u32]);
-        rewriter.insert_operation(ctx, insert_op.get_operation());
-        current = insert_op.get_operation().deref(ctx).get_result(0);
-    }
-    Ok(current)
-}
-
-/// Adapt a semantic enum payload value to or from its physical storage type.
-///
-/// Shared pointer leaves are converted through CUDA generic space recursively
-/// through struct/tuple payloads. Bool leaves are canonicalized separately on
-/// construction and narrowed recursively on extraction.
-fn coerce_enum_payload_storage(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    value: Value,
-    target_ty: TypeHandle,
-) -> Result<Value> {
-    coerce_enum_payload_value(ctx, rewriter, value, target_ty)
-}
-
-/// Convert `mir.construct_enum` (e.g. `E::A(x)`) to LLVM operations.
-///
-/// Builds the enum value slot by slot, taking every index from
-/// [`build_enum_slot_map`] (indexes are never computed by hand here):
-///
-/// 1. Put the variant's declared discriminant VALUE into the tag slot.
-/// 2. `insertvalue` each payload field that owns a struct slot.
-/// 3. If some field has no slot (its bytes are shared with a
-///    different-typed field of another variant), finish through memory:
-///    copy the value to a stack slot, store that field at its byte
-///    position, and load the completed enum back.
-pub(crate) fn convert_construct_enum(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let (result_ty, operands, variant_index) = {
-        let mir_op = op.deref(ctx);
-        let result_ty = mir_op.get_result(0).get_type(ctx);
-        let operands: Vec<_> = mir_op.operands().collect();
-
-        let enum_op = MirConstructEnumOp::new(op);
-        let variant_index = enum_op
-            .get_attr_construct_enum_variant_index(ctx)
-            .map(|attr| attr.0 as usize)
-            .unwrap_or(0);
-
-        (result_ty, operands, variant_index)
-    };
-
-    let enum_ty: MirEnumType = {
-        let ty_ref = result_ty.deref(ctx);
-        match ty_ref.downcast_ref::<MirEnumType>() {
-            Some(e) => e.clone(),
-            None => {
-                return pliron::input_err_noloc!(
-                    "MirConstructEnumOp result type must be MirEnumType"
-                );
-            }
-        }
-    };
-
-    // Build the value as the SAME struct type the type converter
-    // produces everywhere else (block args, loads, allocas, ...). Taking
-    // both the type and the indices from one slot map is what keeps them
-    // in agreement. Filler slots are simply never written.
-    let slot_map = build_enum_slot_map(ctx, result_ty).map_err(anyhow_to_pliron)?;
-    let llvm_struct_ty = slot_map.llvm_struct_ty;
-
-    let undef_op = llvm::UndefOp::new(ctx, llvm_struct_ty);
-    rewriter.insert_operation(ctx, undef_op.get_operation());
-    let mut current_struct = undef_op.get_operation().deref(ctx).get_result(0);
-    let mut last_op = undef_op.get_operation();
-
-    if let Some(bits) = enum_carrier_bits_for_variant(&enum_ty, variant_index)
-        .map_err(|error| pliron::input_error_noloc!("MirConstructEnumOp: {error}"))?
-    {
-        let carrier_slot = slot_map.carrier_slot.ok_or_else(|| {
-            pliron::input_error_noloc!("MirConstructEnumOp requires a physical carrier slot")
-        })?;
-        let carrier_ty = slot_map.carrier_llvm_ty.ok_or_else(|| {
-            pliron::input_error_noloc!("MirConstructEnumOp requires a physical carrier type")
-        })?;
-        let carrier = emit_carrier_constant(ctx, rewriter, &enum_ty, carrier_ty, bits)?;
-        let insert = llvm::InsertValueOp::new(ctx, current_struct, carrier, vec![carrier_slot]);
-        rewriter.insert_operation(ctx, insert.get_operation());
-        current_struct = insert.get_operation().deref(ctx).get_result(0);
-        last_op = insert.get_operation();
-    }
-
-    let field_base: usize = enum_ty
-        .variant_field_counts
-        .iter()
-        .take(variant_index)
-        .map(|&c| c as usize)
-        .sum();
-
-    // Insert every payload field that owns a struct slot; remember the
-    // slotless ones for the memory pass below.
-    let mut deferred: Vec<(usize, Value)> = Vec::new();
-    for (i, operand) in operands.into_iter().enumerate() {
-        let flat = field_base + i;
-        let Some(slot) = slot_map.field_slots.get(flat) else {
-            return pliron::input_err_noloc!(
-                "MirConstructEnumOp field {} of variant {} is out of range for the enum's {} fields",
-                i,
-                variant_index,
-                slot_map.field_slots.len()
-            );
-        };
-        match slot {
-            Some(slot) => {
-                let storage_ty = {
-                    let storage_type = llvm_struct_ty.deref(ctx);
-                    let storage_struct = storage_type
-                        .downcast_ref::<llvm_types::StructType>()
-                        .ok_or_else(|| {
-                            pliron::input_error_noloc!(
-                                "MirConstructEnumOp physical storage is not an LLVM struct"
-                            )
-                        })?;
-                    let storage_slot = *slot as usize;
-                    if storage_slot >= storage_struct.num_fields() {
-                        return pliron::input_err_noloc!(
-                            "MirConstructEnumOp physical field slot {} is out of range",
-                            slot
-                        );
-                    }
-                    storage_struct.field_type(storage_slot)
-                };
-                let stored_operand =
-                    coerce_enum_payload_storage(ctx, rewriter, operand, storage_ty)?;
-                let insert_op =
-                    llvm::InsertValueOp::new(ctx, current_struct, stored_operand, vec![*slot]);
-                rewriter.insert_operation(ctx, insert_op.get_operation());
-                current_struct = insert_op.get_operation().deref(ctx).get_result(0);
-                last_op = insert_op.get_operation();
-            }
-            None => {
-                // Zero-sized fields own no bytes; nothing to write.
-                if is_zero_sized_type(ctx, slot_map.field_llvm_types[flat]) {
-                    continue;
-                }
-                deferred.push((flat, operand));
-            }
-        }
-    }
-
-    if deferred.is_empty() {
-        rewriter.replace_operation(ctx, op, last_op);
-        return Ok(());
-    }
-
-    // Slotless fields: copy the half-built value to the stack, write
-    // each remaining payload at its byte position, and load the finished
-    // enum back as the result.
-    let abi_align = enum_ty.abi_align();
-    let slot_ptr = spill_enum_value(ctx, rewriter, current_struct, llvm_struct_ty, abi_align);
-    for (flat, operand) in deferred {
-        let field_ptr = byte_offset_gep(ctx, rewriter, slot_ptr, slot_map.field_offsets[flat]);
-        // `bool` is an LLVM i1 as a value but occupies one full byte in
-        // Rust memory. Enum storage claims the byte-faithful twin of every
-        // bool-bearing payload (scalar i8 byte, or an aggregate with each
-        // i1 leaf widened to i8), so canonicalize the stored value to that
-        // twin: every physical bool byte becomes an unambiguous 0 or 1.
-        let semantic_ty = slot_map.field_llvm_types[flat];
-        let storage_ty = enum_payload_storage_type(ctx, semantic_ty).map_err(anyhow_to_pliron)?;
-        let canonical_operand = canonicalize_bool_value_bytes(ctx, rewriter, operand)?;
-        let stored_operand =
-            coerce_enum_payload_storage(ctx, rewriter, canonical_operand, storage_ty)?;
-        let store_op = llvm::StoreOp::new(ctx, stored_operand, field_ptr);
-        rewriter.insert_operation(ctx, store_op.get_operation());
-    }
-    let load_op = llvm::LoadOp::new(ctx, slot_ptr, llvm_struct_ty);
-    rewriter.insert_operation(ctx, load_op.get_operation());
-    if abi_align > 0 {
-        llvm_export::ops::set_op_alignment(ctx, load_op.get_operation(), abi_align as u32);
-    }
-    rewriter.replace_operation(ctx, op, load_op.get_operation());
-
-    Ok(())
-}
-
-/// Get the slot map for an enum operand.
-///
-/// By the time an op is converted, its operand's type has already been
-/// rewritten to the LLVM struct, so we look up the ORIGINAL `MirEnumType`
-/// the framework recorded for it and rebuild the map from that. Also
-/// returns the enum's rustc alignment, which spill slots need.
-fn enum_slot_map_of_operand(
-    ctx: &mut Context,
-    operands_info: &OperandsInfo,
-    enum_val: Value,
-) -> Result<(EnumSlotMap, u64)> {
-    // Clone the type data out so the `Ref` borrow of `ctx` ends before
-    // re-interning (types are hash-consed: registering an equal instance
-    // returns the existing pointer).
-    let enum_ty: MirEnumType = {
-        match operands_info.lookup_most_recent_of_type::<MirEnumType>(ctx, enum_val) {
-            Some(r) => r.clone(),
-            None => {
-                return pliron::input_err_noloc!("Expected MirEnumType for enum value access");
-            }
-        }
-    };
-    let abi_align = enum_ty.abi_align();
-    let mir_ty: TypeHandle = pliron::r#type::Type::instantiate(enum_ty, ctx).into();
-    let map = build_enum_slot_map(ctx, mir_ty).map_err(anyhow_to_pliron)?;
-    Ok((map, abi_align))
-}
-
-/// Convert `mir.set_discriminant` to the one physical carrier write rustc's
-/// layout requires. Direct layouts write the declared discriminant; Niche
-/// layouts write wrapping `niche_start + range_offset`. Selecting the
-/// untagged Niche variant or an inhabited Single variant is a no-op.
-///
-/// The enum layout comes from the op's own `set_discriminant_enum_ty`
-/// attribute, stamped at build time. Operand type history is not usable
-/// here: a kind-only `mir.cast` lowers to a plain value forwarding, history
-/// does not follow that edge, and a stale hit would write the tag at the
-/// wrong offset.
-pub(crate) fn convert_set_discriminant(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let enum_ptr = op.deref(ctx).get_operand(0);
-    let target = MirSetDiscriminantOp::new(op)
-        .get_attr_set_discriminant_variant_index(ctx)
-        .map(|attr| attr.0 as usize)
-        .ok_or_else(|| {
-            pliron::input_error_noloc!(
-                "MirSetDiscriminantOp missing set_discriminant_variant_index"
-            )
-        })?;
-
-    let enum_ty: MirEnumType = {
-        let stamped_ty = MirSetDiscriminantOp::new(op)
-            .get_attr_set_discriminant_enum_ty(ctx)
-            .map(|attr| attr.get_type(ctx))
-            .ok_or_else(|| {
-                pliron::input_error_noloc!(
-                    "mir.set_discriminant missing enum type attribute; \
-                     discriminant write has no fact to derive from"
-                )
-            })?;
-        match stamped_ty.deref(ctx).downcast_ref::<MirEnumType>() {
-            Some(et) => et.clone(),
-            None => {
-                return pliron::input_err_noloc!(
-                    "mir.set_discriminant enum type attribute must be an enum type"
-                );
-            }
-        }
-    };
-
-    let Some(bits) = enum_carrier_bits_for_variant(&enum_ty, target)
-        .map_err(|error| pliron::input_error_noloc!("MirSetDiscriminantOp: {error}"))?
-    else {
-        rewriter.erase_operation(ctx, op);
-        return Ok(());
-    };
-
-    let tag_offset = enum_ty.tag_offset();
-    let mir_ty: TypeHandle = pliron::r#type::Type::instantiate(enum_ty.clone(), ctx).into();
-    let slot_map = build_enum_slot_map(ctx, mir_ty).map_err(anyhow_to_pliron)?;
-    let carrier_ty = slot_map.carrier_llvm_ty.ok_or_else(|| {
-        pliron::input_error_noloc!("MirSetDiscriminantOp physical write has no carrier type")
-    })?;
-    let carrier = emit_carrier_constant(ctx, rewriter, &enum_ty, carrier_ty, bits)?;
-    let carrier_ptr = byte_offset_gep(ctx, rewriter, enum_ptr, tag_offset);
-    let store_op = llvm::StoreOp::new(ctx, carrier, carrier_ptr);
-    rewriter.insert_operation(ctx, store_op.get_operation());
-
-    rewriter.erase_operation(ctx, op);
-    Ok(())
-}
-
-/// Convert `mir.get_discriminant` (reading which variant is alive) to
-/// `llvm.extractvalue`.
-///
-/// Direct layouts read the tag from the slot map's carrier slot. Niche
-/// layouts decode rustc's wrapping carrier range; Single layouts materialize
-/// their one logical discriminant as a constant. No slot number is assumed.
-pub(crate) fn convert_get_discriminant(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    let enum_val = match op.deref(ctx).operands().next() {
-        Some(v) => v,
-        None => return pliron::input_err_noloc!("MirGetDiscriminantOp requires an operand"),
-    };
-
-    let enum_ty: MirEnumType = operands_info
-        .lookup_most_recent_of_type::<MirEnumType>(ctx, enum_val)
-        .map(|ty| ty.clone())
-        .ok_or_else(|| pliron::input_error_noloc!("Expected MirEnumType for discriminant read"))?;
-    let mir_ty: TypeHandle = pliron::r#type::Type::instantiate(enum_ty.clone(), ctx).into();
-    let slot_map = build_enum_slot_map(ctx, mir_ty).map_err(anyhow_to_pliron)?;
-    let logical_ty = convert_type(ctx, enum_ty.discriminant_ty).map_err(anyhow_to_pliron)?;
-    let logical_width = logical_ty
-        .deref(ctx)
-        .downcast_ref::<IntegerType>()
-        .map(IntegerType::width)
-        .ok_or_else(|| {
-            pliron::input_error_noloc!("MirGetDiscriminantOp logical result must be integer")
-        })?;
-
-    let result = match enum_ty.layout_kind {
-        EnumLayoutKind::Direct => {
-            let slot = slot_map.carrier_slot.ok_or_else(|| {
-                pliron::input_error_noloc!("Direct enum has no physical carrier slot")
-            })?;
-            let extract = llvm::ExtractValueOp::new(ctx, enum_val, vec![slot])?;
-            rewriter.insert_operation(ctx, extract.get_operation());
-            extract.get_operation().deref(ctx).get_result(0)
-        }
-        EnumLayoutKind::Single => {
-            if enum_ty.variant_is_inhabited(enum_ty.single_variant as usize) != Some(true) {
-                return pliron::input_err_noloc!(
-                    "Cannot read discriminant of an uninhabited single-variant enum"
-                );
-            }
-            let value = *enum_ty
-                .variant_discriminants
-                .get(enum_ty.single_variant as usize)
-                .ok_or_else(|| {
-                    pliron::input_error_noloc!("Single enum has no declared discriminant")
-                })?;
-            emit_integer_constant(ctx, rewriter, logical_width, u128::from(value))
-        }
-        EnumLayoutKind::Niche => {
-            let slot = slot_map.carrier_slot.ok_or_else(|| {
-                pliron::input_error_noloc!("Niche enum has no physical carrier slot")
-            })?;
-            let extract = llvm::ExtractValueOp::new(ctx, enum_val, vec![slot])?;
-            rewriter.insert_operation(ctx, extract.get_operation());
-            let carrier = extract.get_operation().deref(ctx).get_result(0);
-            let carrier_int_ty: TypeHandle =
-                IntegerType::get(ctx, enum_ty.carrier_width, Signedness::Signless).into();
-            let carrier_int = if enum_ty.carrier_kind == EnumCarrierKind::Pointer {
-                let cast = llvm::PtrToIntOp::new(ctx, carrier, carrier_int_ty);
-                rewriter.insert_operation(ctx, cast.get_operation());
-                cast.get_operation().deref(ctx).get_result(0)
-            } else {
-                carrier
-            };
-
-            let niche_start =
-                emit_integer_constant(ctx, rewriter, enum_ty.carrier_width, enum_ty.niche_start());
-            let relative = llvm::SubOp::new_with_overflow_flag(
-                ctx,
-                carrier_int,
-                niche_start,
-                IntegerOverflowFlagsAttr::default(),
-            )
-            .get_operation();
-            rewriter.insert_operation(ctx, relative);
-            let relative_val = relative.deref(ctx).get_result(0);
-            let max = emit_integer_constant(
-                ctx,
-                rewriter,
-                enum_ty.carrier_width,
-                u128::from(enum_ty.niche_variant_end - enum_ty.niche_variant_start),
-            );
-            let in_range =
-                llvm::ICmpOp::new(ctx, ICmpPredicateAttr::ULE, relative_val, max).get_operation();
-            rewriter.insert_operation(ctx, in_range);
-            // The range test is carrier-width wrapping arithmetic, exactly
-            // like rustc. Variant indices themselves live at the logical
-            // discriminant width: the start index may be larger than the
-            // carrier can represent (e.g. variants 298..=299 in an i8 niche).
-            let logical_relative = match enum_ty.carrier_width.cmp(&logical_width) {
-                std::cmp::Ordering::Equal => relative_val,
-                std::cmp::Ordering::Greater => {
-                    let cast = llvm::TruncOp::new(ctx, relative_val, logical_ty).get_operation();
-                    rewriter.insert_operation(ctx, cast);
-                    cast.deref(ctx).get_result(0)
-                }
-                std::cmp::Ordering::Less => {
-                    // LLVM's zext op requires its explicit `nneg` flag even
-                    // when the flag is false. Niche decoding is ordinary
-                    // unsigned extension, so it must never claim nneg.
-                    let cast = llvm::ZExtOp::new_with_nneg(ctx, relative_val, logical_ty, false)
-                        .get_operation();
-                    rewriter.insert_operation(ctx, cast);
-                    cast.deref(ctx).get_result(0)
-                }
-            };
-            let niche_base = emit_integer_constant(
-                ctx,
-                rewriter,
-                logical_width,
-                u128::from(enum_ty.niche_variant_start),
-            );
-            let niche_variant = llvm::AddOp::new_with_overflow_flag(
-                ctx,
-                logical_relative,
-                niche_base,
-                IntegerOverflowFlagsAttr::default(),
-            )
-            .get_operation();
-            rewriter.insert_operation(ctx, niche_variant);
-            let untagged = emit_integer_constant(
-                ctx,
-                rewriter,
-                logical_width,
-                u128::from(enum_ty.untagged_variant),
-            );
-            let in_range_value = in_range.deref(ctx).get_result(0);
-            let niche_variant_value = niche_variant.deref(ctx).get_result(0);
-            let select = llvm::SelectOp::new(ctx, in_range_value, niche_variant_value, untagged)
-                .get_operation();
-            rewriter.insert_operation(ctx, select);
-            select.deref(ctx).get_result(0)
-        }
-        EnumLayoutKind::Empty => {
-            return pliron::input_err_noloc!("Cannot read discriminant of uninhabited enum");
-        }
-        _ => {
-            return pliron::input_err_noloc!(
-                "Cannot read discriminant of enum with unknown physical layout"
-            );
-        }
-    };
-
-    rewriter.replace_operation_with_values(ctx, op, vec![result]);
-
-    Ok(())
-}
-
-/// Convert `mir.enum_payload` (reading a variant's field, e.g. the `x`
-/// in `E::A(x) => x`) to a payload-field read.
-///
-/// Three cases, decided by the [`EnumSlotMap`]:
-///
-/// - The field owns a struct slot: a plain `llvm.extractvalue`.
-/// - The field has no slot (its bytes are shared with a different-typed
-///   field of another variant): go through memory. Copy the enum to a
-///   stack slot, point at the field's byte position, and load it with
-///   its own type. Same trick as [`convert_extract_array_element`], and
-///   it avoids LLVM `bitcast` entirely.
-/// - The field is zero-sized: there is nothing to read; produce `undef`.
-pub(crate) fn convert_enum_payload(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    let enum_val = match op.deref(ctx).operands().next() {
-        Some(v) => v,
-        None => return pliron::input_err_noloc!("MirEnumPayloadOp requires an operand"),
-    };
-
-    let payload_op = MirEnumPayloadOp::new(op);
-    let variant_index = payload_op
-        .get_attr_payload_variant_index(ctx)
-        .map(|attr| attr.0 as usize)
-        .unwrap_or(0);
-    let field_index = payload_op
-        .get_attr_payload_field_index(ctx)
-        .map(|attr| attr.0 as usize)
-        .unwrap_or(0);
-
-    let variant_field_counts = {
-        match operands_info.lookup_most_recent_of_type::<MirEnumType>(ctx, enum_val) {
-            Some(r) => r.variant_field_counts.clone(),
-            None => {
-                return pliron::input_err_noloc!(
-                    "Expected MirEnumType for enum payload extraction"
-                );
-            }
-        }
-    };
-    let (slot_map, abi_align) = enum_slot_map_of_operand(ctx, operands_info, enum_val)?;
-
-    let field_base: usize = variant_field_counts
-        .iter()
-        .take(variant_index)
-        .map(|&c| c as usize)
-        .sum();
-    let flat = field_base + field_index;
-    let Some(slot) = slot_map.field_slots.get(flat).copied() else {
-        return pliron::input_err_noloc!(
-            "MirEnumPayloadOp field {} of variant {} is out of range for the enum's {} fields",
-            field_index,
-            variant_index,
-            slot_map.field_slots.len()
-        );
-    };
-
-    match slot {
-        Some(slot) => {
-            let extract_op = llvm::ExtractValueOp::new(ctx, enum_val, vec![slot])?;
-            rewriter.insert_operation(ctx, extract_op.get_operation());
-            let extracted = extract_op.get_operation().deref(ctx).get_result(0);
-            let semantic_value = coerce_enum_payload_storage(
-                ctx,
-                rewriter,
-                extracted,
-                slot_map.field_llvm_types[flat],
-            )?;
-            rewriter.replace_operation_with_values(ctx, op, vec![semantic_value]);
-        }
-        None if is_zero_sized_type(ctx, slot_map.field_llvm_types[flat]) => {
-            let undef_op = llvm::UndefOp::new(ctx, slot_map.field_llvm_types[flat]);
-            rewriter.insert_operation(ctx, undef_op.get_operation());
-            rewriter.replace_operation(ctx, op, undef_op.get_operation());
-        }
-        None => {
-            let slot_ptr =
-                spill_enum_value(ctx, rewriter, enum_val, slot_map.llvm_struct_ty, abi_align);
-            let field_ptr = byte_offset_gep(ctx, rewriter, slot_ptr, slot_map.field_offsets[flat]);
-            let semantic_ty = slot_map.field_llvm_types[flat];
-            let storage_ty =
-                enum_payload_storage_type(ctx, semantic_ty).map_err(anyhow_to_pliron)?;
-            let load_op = llvm::LoadOp::new(ctx, field_ptr, storage_ty);
-            rewriter.insert_operation(ctx, load_op.get_operation());
-            let stored = load_op.get_operation().deref(ctx).get_result(0);
-            let semantic = coerce_enum_payload_storage(ctx, rewriter, stored, semantic_ty)?;
-            rewriter.replace_operation_with_values(ctx, op, vec![semantic]);
-        }
-    }
-
-    Ok(())
-}
-
-// ============================================================================
-// MirFieldAddrOp Conversion
-// ============================================================================
-
-/// Convert `mir.field_addr` to `llvm.getelementptr`.
-///
-/// Computes the address of a struct field using GEP. This is needed when
-/// Rust code takes `&mut self.field` — we need the ADDRESS of the field,
-/// not a COPY of its value.
-///
-/// The GEP field index and the struct type it indexes into both come from
-/// [`build_struct_slot_map`], so the index accounts for reordering,
-/// `[N x i8]` padding slots and stripped ZSTs (ZST-ness is decided on the
-/// converted LLVM field type, like the value-level sites).
-///
-/// Taking the address of a ZST field emits a distinct zero-offset `i8` GEP
-/// off the base pointer (a ZST field lives at byte 0 of the struct), the
-/// same idiom the union branch uses. It must NOT forward the base SSA value
-/// itself: a 1:1 `replace_operation_with_values` that aliases the op's
-/// result to an already-existing value records the result's pointee type
-/// (the ZST field's own zero-field type) onto that value's conversion type
-/// history, so a sibling `field_addr` on the same base would later resolve
-/// the base's pointee to the ZST type instead of the struct and fail with
-/// "field_addr index N out of bounds for struct with 0 fields". The
-/// distinct GEP result leaves the base pointer's recorded pointee intact
-/// and carries the field's pointee type on its own result, which is what
-/// nested projections through the field address look up.
-pub(crate) fn convert_field_addr(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    let ptr_operand = op.deref(ctx).get_operand(0);
-
-    let field_addr_op = MirFieldAddrOp::new(op);
-    let field_index = match field_addr_op.get_attr_field_index(ctx) {
-        Some(attr) => attr.0 as usize,
-        None => return pliron::input_err_noloc!("MirFieldAddrOp missing field_index attribute"),
-    };
-
-    let mir_ptr_pointee =
-        match operands_info.lookup_most_recent_of_type::<MirPtrType>(ctx, ptr_operand) {
-            Some(r) => r.pointee,
-            None => {
-                return pliron::input_err_noloc!("MirFieldAddrOp operand must be pointer type");
-            }
-        };
-
-    let union_field_count = mir_ptr_pointee
-        .deref(ctx)
-        .downcast_ref::<MirUnionType>()
-        .map(MirUnionType::field_count);
-    if let Some(field_count) = union_field_count {
-        if field_index >= field_count {
-            return pliron::input_err_noloc!(
-                "field_addr index {} out of bounds for union with {} fields",
-                field_index,
-                field_count
-            );
-        }
-        // Every union field begins at byte zero. Emit an explicit zero-offset
-        // GEP instead of forwarding the base SSA value directly: the distinct
-        // result keeps dialect conversion's pointer-type history unambiguous
-        // for repeated field accesses and for `union.struct_field.inner`.
-        use llvm_export::ops::GepIndex;
-        let i8_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
-        let gep = llvm::GetElementPtrOp::new(ctx, ptr_operand, vec![GepIndex::Constant(0)], i8_ty);
-        rewriter.insert_operation(ctx, gep.get_operation());
-        rewriter.replace_operation(ctx, op, gep.get_operation());
-        return Ok(());
-    }
-
-    // An enum payload field, addressed by its position in the flattened
-    // `all_field_types`. Variants share bytes, so the slot map resolves each
-    // field one of two ways: its own LLVM slot, or, when its bytes are already
-    // held by a differently typed field of another variant, a byte offset into
-    // the enum. Both give the address of the same storage, which is what makes
-    // a write through the returned pointer land in the enum rather than a copy.
-    let enum_name = mir_ptr_pointee
-        .deref(ctx)
-        .downcast_ref::<MirEnumType>()
-        .map(|enum_ty| enum_ty.name().to_string());
-    if let Some(enum_name) = enum_name {
-        let map = build_enum_slot_map(ctx, mir_ptr_pointee).map_err(anyhow_to_pliron)?;
-        let Some(slot_entry) = map.field_slots.get(field_index).copied() else {
-            return pliron::input_err_noloc!(
-                "field_addr index {} out of bounds for enum with {} payload fields",
-                field_index,
-                map.field_slots.len()
-            );
-        };
-
-        // Enum payload bytes hold one CANONICAL storage type that can differ
-        // from the field's semantic type: a bool is physically an i8 byte and
-        // a shared-memory pointer is stored as a generic pointer, with the
-        // value paths (construct/extract) coercing exactly at that boundary.
-        // The address computed here ESCAPES this site: the loads and stores
-        // made through it happen at arbitrary other sites and are typed with
-        // the SEMANTIC type, so no storage coercion can be attached at
-        // address-formation time. Handing the address out anyway would let an
-        // i1 store leave the byte's upper seven bits undefined for the i8 and
-        // niche-tag readers, or write a shared-pointer representation into
-        // bytes every other reader interprets (and, on modern NVVM, sizes) as
-        // a generic pointer. Fail closed instead, the same way the slot map
-        // already rejects bool bytes hidden behind unions.
-        let semantic_ty = map.field_llvm_types[field_index];
-        let storage_ty = enum_payload_storage_type(ctx, semantic_ty).map_err(anyhow_to_pliron)?;
-        if storage_ty != semantic_ty {
-            return pliron::input_err_noloc!(
-                "field_addr: cannot hand out the in-place address of payload field {} of enum `{}`: its bytes use canonical storage type {} while its semantic type is {}, and loads or stores made through an escaped payload address are typed with the semantic type, which the canonical bytes cannot honor; shared reads of such payloads are compiled through a value copy automatically, and a write that stays inside its function is compiled by rebuilding the enum around the new payload; a borrow that escapes into a call keeps no such rewrite and is refused here",
-                field_index,
-                enum_name,
-                storage_ty.deref(ctx).disp(ctx),
-                semantic_ty.deref(ctx).disp(ctx)
-            );
-        }
-
-        use llvm_export::ops::GepIndex;
-        let gep = match slot_entry {
-            Some(slot) => llvm::GetElementPtrOp::new(
-                ctx,
-                ptr_operand,
-                vec![GepIndex::Constant(0), GepIndex::Constant(slot)],
-                map.llvm_struct_ty,
-            ),
-            None => {
-                // No slot of its own: address the bytes directly, off the
-                // ORIGINAL enum pointer, so a write through the result lands
-                // in the enum. A zero-sized field lands at its offset like
-                // any other and simply spans nothing. The offset is always
-                // present: the slot map builds `field_offsets` and
-                // `field_slots` from one walk over the same fields, and the
-                // bounds check above already validated the index.
-                let offset = map.field_offsets[field_index];
-                let offset = u32::try_from(offset).map_err(|_| {
-                    pliron::input_error_noloc!(
-                        "field_addr: payload byte offset {} of enum `{}` exceeds u32",
-                        offset,
-                        enum_name
-                    )
-                })?;
-                let i8_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
-                llvm::GetElementPtrOp::new(
-                    ctx,
-                    ptr_operand,
-                    vec![GepIndex::Constant(offset)],
-                    i8_ty,
-                )
-            }
-        };
-        rewriter.insert_operation(ctx, gep.get_operation());
-        rewriter.replace_operation(ctx, op, gep.get_operation());
-        return Ok(());
-    }
-
-    // Carried alongside the layout so the field address can record what it
-    // proves about its own alignment; see `stamp_field_address_alignment`.
-    let aggregate_abi_align;
-    let layout = {
-        let pointee_ref = mir_ptr_pointee.deref(ctx);
-        if let Some(struct_ty) = pointee_ref.downcast_ref::<MirStructType>() {
-            aggregate_abi_align = struct_ty.abi_align;
-            StructLayoutInfo::of_struct(struct_ty)
-        } else if let Some(tuple_ty) = pointee_ref.downcast_ref::<MirTupleType>() {
-            aggregate_abi_align = tuple_ty.abi_align();
-            StructLayoutInfo::of_tuple(tuple_ty)
-        } else {
-            return pliron::input_err_noloc!(
-                "MirFieldAddrOp pointer must point to a struct, tuple, union or enum type, got {}",
-                mir_ptr_pointee.deref(ctx).disp(ctx)
-            );
-        }
-    };
-
-    let map = build_struct_slot_map(ctx, &layout).map_err(anyhow_to_pliron)?;
-
-    let slot = match map.decl_to_llvm.get(field_index) {
-        Some(Some(slot)) => *slot,
-        Some(None) => {
-            // ZST field: it has no storage; the struct address stands in for
-            // the field address. Emit an explicit zero-offset GEP instead of
-            // forwarding the base SSA value directly (mirrors the union branch
-            // above): the distinct result keeps dialect conversion's pointer-type
-            // history unambiguous for repeated field accesses off the same base
-            // pointer. Forwarding the base value here type-puns it to the field's
-            // pointee, corrupting the base pointer's recorded type so a sibling
-            // field_addr on the same base later resolves to the wrong (0-field)
-            // pointee -- the "field_addr index N out of bounds for struct with 0
-            // fields" failure on a struct with >= 2 ZST fields (e.g. a closure
-            // that captures other ZST closures, like iter map_fold).
-            use llvm_export::ops::GepIndex;
-            let i8_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
-            let gep =
-                llvm::GetElementPtrOp::new(ctx, ptr_operand, vec![GepIndex::Constant(0)], i8_ty);
-            rewriter.insert_operation(ctx, gep.get_operation());
-            rewriter.replace_operation(ctx, op, gep.get_operation());
-            return Ok(());
-        }
-        None => {
-            return pliron::input_err_noloc!(
-                "field_addr index {} out of bounds for struct with {} fields",
-                field_index,
-                map.decl_to_llvm.len()
-            );
-        }
-    };
-
-    let rustc_offset = layout.field_offsets.get(field_index).copied();
-
-    // Preserve the #859 address-path contract independently of the value
-    // representation. `build_struct_slot_map` retains the offsets the same
-    // fields would have under natural LLVM layout; when those differ from
-    // rustc's recorded offsets, keep using the original aggregate pointer plus
-    // a byte GEP. The semantic value type may now be an LLVM packed struct, but
-    // changing this established field-address path is outside this change.
-    if let Some(expected_offset) = rustc_offset {
-        let actual_offset = map
-            .natural_slot_offsets
-            .as_ref()
-            .and_then(|offsets| offsets.get(slot as usize).copied())
-            .ok_or_else(|| {
-                pliron::input_error_noloc!(
-                    "field_addr: cannot determine LLVM byte offset of slot {} for field {}",
-                    slot,
-                    field_index
-                )
-            })?;
-        if map.layout_diverges && actual_offset != expected_offset {
-            let field_ptr = byte_offset_gep(ctx, rewriter, ptr_operand, expected_offset);
-            let gep = field_ptr
-                .defining_op()
-                .expect("byte_offset_gep always returns a GEP result");
-            stamp_field_address_alignment(ctx, gep, aggregate_abi_align, Some(expected_offset));
-            rewriter.replace_operation(ctx, op, gep);
-            return Ok(());
-        }
-    }
-
-    use llvm_export::ops::GepIndex;
-    let gep_indices = vec![GepIndex::Constant(0), GepIndex::Constant(slot)];
-
-    let gep_op = llvm::GetElementPtrOp::new(ctx, ptr_operand, gep_indices, map.llvm_struct_ty);
-    rewriter.insert_operation(ctx, gep_op.get_operation());
-    stamp_field_address_alignment(
-        ctx,
-        gep_op.get_operation(),
-        aggregate_abi_align,
-        rustc_offset,
-    );
-    rewriter.replace_operation(ctx, op, gep_op.get_operation());
-
-    Ok(())
-}
-
-/// Record on a field address what its alignment provably is.
-///
-/// A load reads its alignment from its own result type, and a scalar records
-/// none -- so `p.x` on an `#[repr(C, align(8))]` struct would export with LLVM's
-/// default `align 4`, dropping the guarantee rustc gave the aggregate. That is
-/// what stops LoadStoreVectorizer from fusing two adjacent field reads into one
-/// wide access; a whole-element copy of the same struct already vectorizes,
-/// because there the load's result type *is* the aggregate.
-///
-/// The aggregate is aligned to `abi_align`, so its field at byte `offset` is
-/// aligned to `gcd(abi_align, offset)`, and to `abi_align` itself at offset
-/// zero. Both numbers are rustc's own layout, so this claims nothing the source
-/// did not already guarantee.
-///
-/// Stamps nothing when the aggregate records no alignment (`abi_align == 0`,
-/// which also stands for "layout unknown") or the field has no recorded offset.
-/// A wrong alignment here is a miscompile, so every uncertain case declines and
-/// leaves the previous, weaker-but-sound behaviour.
-fn stamp_field_address_alignment(
-    ctx: &mut Context,
-    gep: Ptr<Operation>,
-    abi_align: u64,
-    field_offset: Option<u64>,
-) {
-    const fn gcd(a: u64, b: u64) -> u64 {
-        if b == 0 { a } else { gcd(b, a % b) }
-    }
-
-    if abi_align == 0 {
-        return;
-    }
-    let Some(offset) = field_offset else {
-        return;
-    };
-    let provable = if offset == 0 {
-        abi_align
-    } else {
-        gcd(abi_align, offset)
-    };
-    // Every rustc layout has a power-of-two `abi_align`, but dialect-mir only
-    // verifier-enforces that for unions and enums; a malformed hand-built
-    // struct or tuple layout could reach here with e.g. 12, and a
-    // non-power-of-two `align N` is invalid LLVM IR that llc rejects.
-    if !provable.is_power_of_two() {
-        return;
-    }
-    if let Ok(align) = u32::try_from(provable) {
-        llvm_export::ops::set_address_alignment(ctx, gep, align);
-    }
-}
-
-// ============================================================================
-// MirArrayElementAddrOp Conversion
-// ============================================================================
-
-/// Convert `mir.array_element_addr` to `llvm.getelementptr`.
-///
-/// ```text
-/// &arr[i]  ──►  getelementptr T, ptr %arr_ptr, i64 %i
-/// ```
-///
-/// - The element type `T` comes from the op's OWN result type
-///   (`mir.ptr<T>`), which the dialect verifier ties to the operand
-///   array's element type. Same address as the old two-index
-///   `[N x T]` GEP, minus the dead `[N x T]` base.
-/// - Operand type history is not usable here: a kind-only `mir.cast`
-///   lowers to a plain value forwarding, history does not follow that
-///   edge, and a stale hit would stride by the wrong element size.
-pub(crate) fn convert_array_element_addr(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let loc = op.deref(ctx).loc();
-    let arr_ptr = op.deref(ctx).get_operand(0);
-    let index = op.deref(ctx).get_operand(1);
-
-    let result_ty = op.deref(ctx).get_result(0).get_type(ctx);
-    let element_ty = result_ty
-        .deref(ctx)
-        .downcast_ref::<MirPtrType>()
-        .map(|mir_ptr| mir_ptr.pointee)
-        .ok_or_else(|| {
-            pliron::input_error!(
-                loc.clone(),
-                "mir.array_element_addr result must be a MIR pointer type; \
-                 element sizing has no fact to derive from"
-            )
-        })?;
-
-    let llvm_element_ty = convert_type(ctx, element_ty).map_err(anyhow_to_pliron)?;
-
-    // The typed GEP strides by the LLVM allocation size of the element type.
-    // Keep the rustc-stride comparison as a fail-closed backstop for any
-    // element representation whose LLVM allocation size differs.
-    {
-        let rustc_stride = mir_element_stride(ctx, element_ty);
-        let llvm_size = llvm_type_size_align(ctx, llvm_element_ty).map(|(size, _)| size);
-        if let (Some(stride), Some(llvm_size)) = (rustc_stride, llvm_size)
-            && stride != llvm_size
-        {
-            return pliron::input_err_noloc!(
-                "addressing elements of an array whose LLVM allocation size differs from \
-                 rustc's stored stride is not supported: rustc strides by {} bytes but \
-                 the LLVM element type occupies {}",
-                stride,
-                llvm_size
-            );
-        }
-    }
-
-    use llvm_export::ops::GepIndex;
-    let gep_indices = vec![GepIndex::Value(index)];
-
-    let element_align = element_address_provable_alignment(ctx, arr_ptr, element_ty, index);
-
-    let gep_op = llvm::GetElementPtrOp::new(ctx, arr_ptr, gep_indices, llvm_element_ty);
-    rewriter.insert_operation(ctx, gep_op.get_operation());
-    if let Some(align) = element_align {
-        llvm_export::ops::set_address_alignment(ctx, gep_op.get_operation(), align);
-    }
-    rewriter.replace_operation(ctx, op, gep_op.get_operation());
-
-    Ok(())
-}
-
-/// Alignment an array-element address provably has, in bytes.
-///
-/// The field path records this already ([`stamp_field_address_alignment`]), but
-/// an element address recorded nothing, so `lanes[0] + lanes[1]` on an
-/// `#[repr(C, align(8))]` `[f32; 2]` still exported two `align 4` loads and
-/// LoadStoreVectorizer refused to fuse them. Reading the same element into a
-/// local first happens to work, because SROA then loads the whole aggregate and
-/// the alignment comes from its type — so the cost depended on whether the
-/// source copied the element or read through it.
-///
-/// Two facts combine. The element's `abi_align` equals the array's (a Rust
-/// array aligns to its element), and whatever the *base pointer* already
-/// proved is stronger when the array is itself a field of an over-aligned
-/// aggregate: `&table[i].lanes` carries the outer struct's alignment, which
-/// the element type alone does not know. Element `i` then sits at byte
-/// `i * stride`, so it is aligned to `gcd(base, i * stride)`, and to `base`
-/// itself at index zero. A runtime index can land on any element, so it gets
-/// `gcd(base, stride)`, which every element satisfies.
-///
-/// Answers `None`, leaving the previous behaviour, when neither the base nor
-/// the element type records an alignment, or the stride is unknown. As on the
-/// field path, a wrong answer here is a miscompile, so every uncertain case
-/// declines rather than guesses. That is why the stride comes from
-/// [`mir_element_stride`], which is exact or `None`: an LLVM-level size
-/// approximation would guess 8 for a MIR aggregate element it does not
-/// model, and e.g. `[[f32; 3]; 4]` under an align-8 base would then claim
-/// align 8 on element addresses that are only 4-aligned.
-fn element_address_provable_alignment(
-    ctx: &Context,
-    arr_ptr: Value,
-    element_ty: TypeHandle,
-    index: Value,
-) -> Option<u32> {
-    const fn gcd(a: u64, b: u64) -> u64 {
-        if b == 0 { a } else { gcd(b, a % b) }
-    }
-
-    // What the base address already proved, else what the element type
-    // states (identical to the array's own alignment).
-    let base_align = arr_ptr
-        .defining_op()
-        .and_then(|def| llvm_export::ops::address_alignment(ctx, def))
-        .map(u64::from)
-        .or_else(|| mir_type_abi_align(ctx, element_ty))?;
-    if base_align == 0 {
-        return None;
-    }
-
-    let stride = mir_element_stride(ctx, element_ty)?;
-    if stride == 0 {
-        return None;
-    }
-
-    let provable = match constant_index_value(ctx, index) {
-        Some(0) => base_align,
-        Some(i) => gcd(base_align, i.checked_mul(stride)?),
-        // Any element is reachable, so claim only what every stride preserves.
-        None => gcd(base_align, stride),
-    };
-
-    // Same guard as the field path: dialect-mir does not verifier-enforce a
-    // power-of-two `abi_align` for every aggregate, and a non-power-of-two
-    // `align N` is invalid LLVM IR that llc rejects.
-    if !provable.is_power_of_two() {
-        return None;
-    }
-    u32::try_from(provable).ok()
-}
-
-/// The constant an index operand holds, if it is one.
-///
-/// `APInt::to_u64` truncates wider values, so a >64-bit constant could be
-/// misread as a small offset multiplier. Fail closed on such widths, as
-/// `integer_constant_u64` in the extract-element fast path does.
-fn constant_index_value(ctx: &Context, index: Value) -> Option<u64> {
-    let defining_op = index.defining_op()?;
-    if let Some(constant) = Operation::get_op::<MirConstantOp>(defining_op, ctx) {
-        let value = constant.get_attr_value(ctx)?.value();
-        return (value.bw() <= 64).then(|| value.to_u64());
-    }
-    let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, ctx)?;
-    let attribute = constant.get_value(ctx);
-    let integer = attribute.downcast_ref::<pliron::builtin::attributes::IntegerAttr>()?;
-    let value = integer.value();
-    (value.bw() <= 64).then(|| value.to_u64())
-}
-
-#[cfg(test)]
-// Tests build kinded fixture types directly; production minting lives in mir-importer's facts.rs.
-#[allow(clippy::disallowed_methods)]
-mod tests {
-    use super::*;
-    use crate::convert::ops::test_util::*;
-    use dialect_mir::attributes::{FieldIndexAttr, MirCastKindAttr, VariantIndexAttr};
-    use dialect_mir::ops as mir;
-    use dialect_mir::types::{
-        EnumEncoding, EnumVariant, MirArrayType, MirPointerKind, MirPtrType, MirSliceType,
-        MirStructType, MirTupleType,
-    };
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::common_traits::Verify;
-
-    fn insert_indices(ctx: &Context, inserts: &[llvm::InsertValueOp]) -> Vec<Vec<u32>> {
-        inserts.iter().map(|op| op.indices(ctx)).collect()
-    }
-
-    fn empty_struct_ty(ctx: &mut Context, name: &str) -> TypeHandle {
-        MirStructType::get(ctx, name.to_string(), vec![], vec![]).into()
-    }
-
-    fn padded_struct_with_zst_ty(ctx: &mut Context) -> (TypeHandle, TypeHandle) {
-        let i8_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
-        let i64_ty: TypeHandle = IntegerType::get(ctx, 64, Signedness::Signless).into();
-        let zst_ty = empty_struct_ty(ctx, "Marker");
-
-        let struct_ty = MirStructType::get_with_full_layout(
-            ctx,
-            "Padded".to_string(),
-            vec!["a".to_string(), "marker".to_string(), "b".to_string()],
-            vec![i8_ty, zst_ty, i64_ty],
-            vec![0, 1, 2],
-            vec![0, 1, 8],
-            16,
-            8,
-        );
-
-        (struct_ty.into(), zst_ty)
-    }
-
-    fn append_empty_struct_value(
-        ctx: &mut Context,
-        block: Ptr<pliron::basic_block::BasicBlock>,
-        zst_ty: TypeHandle,
-    ) -> Value {
-        let op = Operation::new(
-            ctx,
-            mir::MirConstructStructOp::get_concrete_op_info(),
-            vec![zst_ty],
-            vec![],
-            vec![],
-            0,
-        );
-        op.insert_at_back(block, ctx);
-        op.deref(ctx).get_result(0)
-    }
-
-    fn byte_gep_constant_offset(ctx: &Context, gep: &llvm::GetElementPtrOp) -> Option<u64> {
-        use llvm_export::ops::GepIndex;
-
-        let indices = gep.indices(ctx);
-        let [GepIndex::Value(offset)] = indices.as_slice() else {
-            return None;
-        };
-        let defining_op = offset.defining_op()?;
-        let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, ctx)?;
-        let attribute = constant.get_value(ctx);
-        attribute
-            .downcast_ref::<IntegerAttr>()
-            .map(|integer| integer.value().to_u64())
-    }
-
-    fn assert_byte_addressed_field(
-        ctx: &Context,
-        module: Ptr<Operation>,
-        expected_offset: u64,
-        expected_alignment: u32,
-    ) {
-        let body = kernel_blocks(ctx, module);
-        let geps = find_all::<llvm::GetElementPtrOp>(ctx, &body);
-        assert_eq!(geps.len(), 1, "one field_addr must lower to one GEP");
-
-        let gep = &geps[0];
-        assert_eq!(
-            gep.src_elem_type(ctx),
-            IntegerType::get(ctx, 8, Signedness::Signless).into(),
-            "a layout-mismatched field must be addressed in byte units"
-        );
-        assert_eq!(
-            byte_gep_constant_offset(ctx, gep),
-            Some(expected_offset),
-            "the byte GEP must use rustc's exact field offset"
-        );
-        assert_eq!(
-            llvm_export::ops::address_alignment(ctx, gep.get_operation()),
-            Some(expected_alignment),
-            "the byte GEP must retain the alignment proved by rustc's aggregate layout"
-        );
-    }
-
-    /// `mir.construct_slice` lowers to the canonical fat-pointer value:
-    /// `undef { ptr, i64 }`, then insert data pointer at slot 0 and length at slot 1.
-    #[test]
-    fn construct_slice_lowers_to_ptr_len_insert_values() {
-        let mut ctx = make_ctx();
-
-        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let usize_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, i8_ty, false).into();
-        let slice_ty: TypeHandle = MirSliceType::get(&mut ctx, i8_ty).into();
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty, usize_ty], vec![]);
-        let data_ptr = block.deref(&ctx).get_argument(0);
-        let len = block.deref(&ctx).get_argument(1);
-
-        let op = Operation::new(
-            &mut ctx,
-            mir::MirConstructSliceOp::get_concrete_op_info(),
-            vec![slice_ty],
-            vec![data_ptr, len],
-            vec![],
-            0,
-        );
-        op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
-
-        assert_eq!(
-            insert_indices(&ctx, &inserts),
-            vec![vec![0], vec![1]],
-            "slice construction must insert data pointer at slot 0 and length at slot 1"
-        );
-        let first_insert = inserts[0].get_operation();
-        let second_insert = inserts[1].get_operation();
-        assert_eq!(
-            first_insert.deref(&ctx).get_operand(1),
-            data_ptr,
-            "slice slot 0 must receive the original data pointer"
-        );
-        assert_eq!(
-            second_insert.deref(&ctx).get_operand(0),
-            first_insert.deref(&ctx).get_result(0),
-            "the length insertion must consume the aggregate produced by the pointer insertion"
-        );
-        assert_eq!(
-            second_insert.deref(&ctx).get_operand(1),
-            len,
-            "slice slot 1 must receive the original length"
-        );
-        assert!(
-            inserts.iter().all(|insert| insert.verify(&ctx).is_ok()),
-            "both slice insertions must satisfy LLVM dialect verification"
-        );
-        assert_eq!(
-            count_ops::<llvm::UndefOp>(&ctx, &body),
-            1,
-            "slice construction should start from one undef aggregate"
-        );
-    }
-
-    /// `mir.construct_disjoint_slice` lowers to the same insert chain as the
-    /// fat pointer for an index space with no runtime layout.
-    #[test]
-    fn construct_disjoint_slice_lowers_to_ptr_len_insert_values() {
-        let mut ctx = make_ctx();
-
-        let f32_ty: TypeHandle = pliron::builtin::types::FP32Type::get(&ctx).into();
-        let usize_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let ptr_ty: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, f32_ty, true, MirPointerKind::RawMut)
-                .into();
-        let slice_ty: TypeHandle = MirDisjointSliceType::get(&mut ctx, f32_ty).into();
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty, usize_ty], vec![]);
-        let data_ptr = block.deref(&ctx).get_argument(0);
-        let len = block.deref(&ctx).get_argument(1);
-
-        let op = Operation::new(
-            &mut ctx,
-            mir::MirConstructDisjointSliceOp::get_concrete_op_info(),
-            vec![slice_ty],
-            vec![data_ptr, len],
-            vec![],
-            0,
-        );
-        op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
-        assert_eq!(
-            insert_indices(&ctx, &inserts),
-            vec![vec![0], vec![1]],
-            "a space-free disjoint slice must insert pointer at slot 0 and length at slot 1"
-        );
-        assert_eq!(
-            inserts[0].get_operation().deref(&ctx).get_operand(1),
-            data_ptr,
-            "slot 0 must receive the original data pointer"
-        );
-        assert_eq!(
-            inserts[1].get_operation().deref(&ctx).get_operand(1),
-            len,
-            "slot 1 must receive the original length"
-        );
-        assert_eq!(
-            count_ops::<llvm::UndefOp>(&ctx, &body),
-            1,
-            "construction should start from one undef aggregate"
-        );
-    }
-
-    /// The runtime row width is the third operand and must land in slot 2.
-    /// Writing it into the length slot, or dropping it, gives a slice whose
-    /// row width reads back as something else at every access site.
-    #[test]
-    fn construct_disjoint_slice_places_the_row_width_after_ptr_and_len() {
-        let mut ctx = make_ctx();
-
-        let f32_ty: TypeHandle = pliron::builtin::types::FP32Type::get(&ctx).into();
-        let usize_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let width_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let ptr_ty: TypeHandle =
-            MirPtrType::get_generic_with_kind(&mut ctx, f32_ty, true, MirPointerKind::RawMut)
-                .into();
-        let slice_ty: TypeHandle =
-            MirDisjointSliceType::get_with_space(&mut ctx, f32_ty, vec![width_ty]).into();
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty, usize_ty, width_ty], vec![]);
-        let data_ptr = block.deref(&ctx).get_argument(0);
-        let len = block.deref(&ctx).get_argument(1);
-        let width = block.deref(&ctx).get_argument(2);
-
-        let op = Operation::new(
-            &mut ctx,
-            mir::MirConstructDisjointSliceOp::get_concrete_op_info(),
-            vec![slice_ty],
-            vec![data_ptr, len, width],
-            vec![],
-            0,
-        );
-        op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
-        assert_eq!(
-            insert_indices(&ctx, &inserts),
-            vec![vec![0], vec![1], vec![2]],
-            "the row width must occupy slot 2, after the pointer and the length"
-        );
-        assert_eq!(
-            inserts[2].get_operation().deref(&ctx).get_operand(1),
-            width,
-            "slot 2 must receive the row width operand, not the length"
-        );
-        assert_eq!(
-            inserts[1].get_operation().deref(&ctx).get_operand(1),
-            len,
-            "slot 1 must still receive the length"
-        );
-    }
-
-    /// Explicit rustc layout must be respected: field `b` is at byte offset 8,
-    /// so the lowered LLVM struct has a padding slot between `a` and `b`.
-    /// The ZST marker field is stripped and receives no insert_value.
-    #[test]
-    fn construct_struct_uses_layout_slots_and_skips_zst() {
-        let mut ctx = make_ctx();
-
-        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
-        let (struct_ty, zst_ty) = padded_struct_with_zst_ty(&mut ctx);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![i8_ty, i64_ty], vec![]);
-        let a = block.deref(&ctx).get_argument(0);
-        let b = block.deref(&ctx).get_argument(1);
-        let marker = append_empty_struct_value(&mut ctx, block, zst_ty);
-
-        let op = Operation::new(
-            &mut ctx,
-            mir::MirConstructStructOp::get_concrete_op_info(),
-            vec![struct_ty],
-            vec![a, marker, b],
-            vec![],
-            0,
-        );
-        op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
-
-        assert_eq!(
-            insert_indices(&ctx, &inserts),
-            vec![vec![0], vec![2]],
-            "non-ZST fields must be inserted at their layout slots, skipping padding and ZSTs"
-        );
-        let first_insert = inserts[0].get_operation();
-        let second_insert = inserts[1].get_operation();
-        assert_eq!(
-            first_insert.deref(&ctx).get_operand(1),
-            a,
-            "struct slot 0 must receive field `a`"
-        );
-        assert_eq!(
-            second_insert.deref(&ctx).get_operand(0),
-            first_insert.deref(&ctx).get_result(0),
-            "field `b` must be inserted into the aggregate containing field `a`"
-        );
-        assert_eq!(
-            second_insert.deref(&ctx).get_operand(1),
-            b,
-            "struct slot 2 must receive field `b`"
-        );
-        assert!(
-            inserts.iter().all(|insert| insert.verify(&ctx).is_ok()),
-            "both struct insertions must satisfy LLVM dialect verification"
-        );
-    }
-
-    /// Extracting a ZST field must not emit `extract_value`: the field has no
-    /// storage in the lowered LLVM struct, so lowering materializes an undef
-    /// zero-sized value instead.
-    #[test]
-    fn extract_zst_field_lowers_to_undef_without_extract_value() {
-        let mut ctx = make_ctx();
-
-        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
-        let (struct_ty, zst_ty) = padded_struct_with_zst_ty(&mut ctx);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![i8_ty, i64_ty], vec![]);
-        let a = block.deref(&ctx).get_argument(0);
-        let b = block.deref(&ctx).get_argument(1);
-        let marker = append_empty_struct_value(&mut ctx, block, zst_ty);
-
-        let construct = Operation::new(
-            &mut ctx,
-            mir::MirConstructStructOp::get_concrete_op_info(),
-            vec![struct_ty],
-            vec![a, marker, b],
-            vec![],
-            0,
-        );
-        construct.insert_at_back(block, &ctx);
-        let aggregate = construct.deref(&ctx).get_result(0);
-
-        let extract = Operation::new(
-            &mut ctx,
-            MirExtractFieldOp::get_concrete_op_info(),
-            vec![zst_ty],
-            vec![aggregate],
-            vec![],
-            0,
-        );
-        MirExtractFieldOp::new(extract).set_attr_index(&ctx, FieldIndexAttr(1));
-        extract.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-
-        assert_eq!(
-            count_ops::<llvm::ExtractValueOp>(&ctx, &body),
-            0,
-            "extracting a stripped ZST field must not emit llvm.extractvalue"
-        );
-
-        let zst_un_defs = find_all::<llvm::UndefOp>(&ctx, &body)
-            .into_iter()
-            .filter(|op| {
-                let result_ty = op.get_operation().deref(&ctx).get_result(0).get_type(&ctx);
-                is_zero_sized_type(&ctx, result_ty)
-            })
-            .count();
-
-        assert_eq!(
-            zst_un_defs, 2,
-            "one undef should build the ZST value and one should materialize the extracted ZST"
-        );
-    }
-
-    /// Sibling ZST field addresses off one base pointer must each lower to
-    /// their own zero-offset `i8` GEP, never to the base SSA value itself.
-    /// Forwarding the base (the pre-fix behavior) recorded the first field's
-    /// zero-field pointee type onto the base pointer's conversion history, so
-    /// the second `field_addr` resolved the base's pointee to "struct with 0
-    /// fields" and lowering aborted. This is the `iter().map(..).sum()` shape:
-    /// a composed closure holding two captureless (zero-sized) closures.
-    #[test]
-    fn sibling_zst_field_addrs_lower_to_distinct_zero_offset_geps() {
-        use llvm_export::ops::GepIndex;
-
-        let mut ctx = make_ctx();
-
-        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
-        let zst_f = empty_struct_ty(&mut ctx, "MapClosure");
-        let zst_g = empty_struct_ty(&mut ctx, "SumClosure");
-
-        // struct Composed { f: MapClosure (ZST), g: SumClosure (ZST), acc: i64 }
-        let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Composed".to_string(),
-            vec!["f".to_string(), "g".to_string(), "acc".to_string()],
-            vec![zst_f, zst_g, i64_ty],
-            vec![0, 1, 2],
-            vec![0, 0, 0],
-            8,
-            8,
-        )
-        .into();
-
-        let base_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, struct_ty, true).into();
-        // Each field_addr result records the field's own pointee type; for the
-        // ZST fields that zero-field pointee is exactly what poisoned the base
-        // pointer's history when the result aliased the base.
-        let f_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, zst_f, true).into();
-        let g_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, zst_g, true).into();
-        let acc_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, i64_ty, true).into();
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![base_ptr_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-
-        for (field_index, result_ty) in [(0u32, f_ptr_ty), (1, g_ptr_ty), (2, acc_ptr_ty)] {
-            let op = MirFieldAddrOp::build(&mut ctx, base, result_ty, field_index)
-                .expect("field_addr build");
-            op.insert_at_back(block, &ctx);
-        }
-        append_mir_return(&mut ctx, block, vec![]);
-
-        // Pre-fix this failed with "field_addr index 1 out of bounds for
-        // struct with 0 fields" on the second (sibling) ZST field_addr.
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let geps = find_all::<llvm::GetElementPtrOp>(&ctx, &body);
-        assert_eq!(geps.len(), 3, "each field_addr must lower to its own GEP");
-        assert!(
-            geps.iter().all(|gep| gep.verify(&ctx).is_ok()),
-            "every field-address GEP must satisfy LLVM dialect verification"
-        );
-
-        let zst_geps: Vec<_> = geps
-            .iter()
-            .filter(|gep| {
-                gep.src_elem_type(&ctx) == i8_ty
-                    && matches!(gep.indices(&ctx).as_slice(), [GepIndex::Constant(0)])
-            })
-            .collect();
-        assert_eq!(
-            zst_geps.len(),
-            2,
-            "both ZST field addresses must lower to zero-offset i8 GEPs"
-        );
-
-        let gep_base = |gep: &llvm::GetElementPtrOp| gep.get_operation().deref(&ctx).get_operand(0);
-        let gep_result =
-            |gep: &llvm::GetElementPtrOp| gep.get_operation().deref(&ctx).get_result(0);
-        assert_eq!(
-            gep_base(zst_geps[0]),
-            gep_base(zst_geps[1]),
-            "both ZST field addresses must be taken off the same base pointer"
-        );
-        assert_ne!(
-            gep_result(zst_geps[0]),
-            gep_base(zst_geps[0]),
-            "a ZST field address must be a value distinct from the base pointer"
-        );
-        assert_ne!(
-            gep_result(zst_geps[1]),
-            gep_base(zst_geps[1]),
-            "a ZST field address must be a value distinct from the base pointer"
-        );
-        assert_ne!(
-            gep_result(zst_geps[0]),
-            gep_result(zst_geps[1]),
-            "each sibling ZST field address must get its own GEP result"
-        );
-
-        // The non-ZST sibling still resolves the base's pointee to the struct
-        // (slot 0 holds `acc`): the base pointer's type history stayed intact.
-        let acc_geps: Vec<_> = geps
-            .iter()
-            .filter(|gep| {
-                matches!(
-                    gep.indices(&ctx).as_slice(),
-                    [GepIndex::Constant(0), GepIndex::Constant(0)]
-                )
-            })
-            .collect();
-        assert_eq!(
-            acc_geps.len(),
-            1,
-            "the non-ZST field address must index the struct's layout slot"
-        );
-    }
-
-    /// `mir.field_addr` on a TUPLE pointee (the `#693` shape: `let (a, b) =
-    /// TABLE[i];`) must resolve the GEP index through the tuple's memory-order
-    /// layout, exactly like the struct path above, not through the
-    /// declaration index directly.
-    ///
-    /// `(u8, u32)` is rustc's own layout for this pair: the `u32` field is
-    /// placed FIRST in memory for alignment, so declaration field 0 (`u8`,
-    /// `.0`) lives at memory slot 1 and declaration field 1 (`u32`, `.1`)
-    /// lives at memory slot 0. A GEP index equal to the declaration index
-    /// would silently address the WRONG field's bytes.
-    #[test]
-    fn field_addr_tuple_pointee_resolves_memory_order_gep_index() {
-        use llvm_export::ops::GepIndex;
-
-        let mut ctx = make_ctx();
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-
-        // decl order [u8, u32]; memory order [u32, u8] (mem_to_decl = [1, 0]).
-        let tuple_ty: TypeHandle = MirTupleType::get_with_layout(
-            &mut ctx,
-            vec![u8_ty, u32_ty],
-            vec![1, 0],
-            vec![4, 0],
-            8,
-            4,
-        )
-        .into();
-
-        let tuple_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, tuple_ty, false).into();
-        let u8_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
-        let u32_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![tuple_ptr_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-
-        // Declaration field 0 (`.0`, u8) first, then declaration field 1
-        // (`.1`, u32) -- source order, not memory order.
-        for (field_index, result_ty) in [(0u32, u8_ptr_ty), (1, u32_ptr_ty)] {
-            let op = MirFieldAddrOp::build(&mut ctx, base, result_ty, field_index)
-                .expect("field_addr build");
-            op.insert_at_back(block, &ctx);
-        }
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let geps = find_all::<llvm::GetElementPtrOp>(&ctx, &body);
-        assert_eq!(geps.len(), 2, "each field_addr must lower to its own GEP");
-        assert!(
-            geps.iter().all(|gep| gep.verify(&ctx).is_ok()),
-            "every field-address GEP must satisfy LLVM dialect verification"
-        );
-
-        // `.0` (u8, declared first) must land at MEMORY slot 1.
-        let field0_geps: Vec<_> = geps
-            .iter()
-            .filter(|gep| {
-                matches!(
-                    gep.indices(&ctx).as_slice(),
-                    [GepIndex::Constant(0), GepIndex::Constant(1)]
-                )
-            })
-            .collect();
-        assert_eq!(
-            field0_geps.len(),
-            1,
-            "declaration field 0 (u8) must resolve to its memory slot 1, not slot 0"
-        );
-
-        // `.1` (u32, declared second) must land at MEMORY slot 0.
-        let field1_geps: Vec<_> = geps
-            .iter()
-            .filter(|gep| {
-                matches!(
-                    gep.indices(&ctx).as_slice(),
-                    [GepIndex::Constant(0), GepIndex::Constant(0)]
-                )
-            })
-            .collect();
-        assert_eq!(
-            field1_geps.len(),
-            1,
-            "declaration field 1 (u32) must resolve to its memory slot 0, not slot 1"
-        );
-    }
-
-    /// A `#[repr(C, packed)]`-style layout can place a naturally aligned
-    /// scalar at an offset LLVM's ordinary struct layout cannot express. The
-    /// field address must therefore use rustc's byte offset rather than a
-    /// typed struct GEP that would silently land at byte 4.
-    #[test]
-    fn packed_field_addr_uses_rustc_byte_offset_and_alignment_one() {
-        let mut ctx = make_ctx();
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Packed".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![0, 1],
-            vec![0, 1],
-            5,
-            1,
-        )
-        .into();
-
-        let base_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, packed_ty, false).into();
-        let field_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let (module, block) = build_kernel(&mut ctx, vec![base_ptr_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-
-        let field_addr =
-            MirFieldAddrOp::build(&mut ctx, base, field_ptr_ty, 1).expect("field_addr build");
-        field_addr.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        assert_byte_addressed_field(&ctx, module, 1, 1);
-    }
-
-    /// `repr(packed(2))` is not equivalent to byte alignment: the same u32
-    /// field is allowed to sit at byte 2 and the address still proves align 2.
-    #[test]
-    fn packed_two_field_addr_uses_rustc_byte_offset_and_alignment_two() {
-        let mut ctx = make_ctx();
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Packed2".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![0, 1],
-            vec![0, 2],
-            6,
-            2,
-        )
-        .into();
-
-        let base_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, packed_ty, false).into();
-        let field_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let (module, block) = build_kernel(&mut ctx, vec![base_ptr_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-
-        let field_addr =
-            MirFieldAddrOp::build(&mut ctx, base, field_ptr_ty, 1).expect("field_addr build");
-        field_addr.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        assert_byte_addressed_field(&ctx, module, 2, 2);
-    }
-
-    /// The decision must compare physical offsets, not merely the selected
-    /// field's own alignment. In `{ u8, u32, u8 }` the final u8 is naturally
-    /// byte-aligned, but LLVM has already shifted it because the packed u32
-    /// before it was placed at byte 4 instead of byte 1.
-    #[test]
-    fn packed_trailing_byte_field_uses_accumulated_rustc_offset() {
-        let mut ctx = make_ctx();
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedTrailing".into(),
-            vec!["head".into(), "value".into(), "tail".into()],
-            vec![u8_ty, u32_ty, u8_ty],
-            vec![0, 1, 2],
-            vec![0, 1, 5],
-            6,
-            1,
-        )
-        .into();
-
-        let base_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, packed_ty, false).into();
-        let field_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
-        let (module, block) = build_kernel(&mut ctx, vec![base_ptr_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-
-        let field_addr =
-            MirFieldAddrOp::build(&mut ctx, base, field_ptr_ty, 2).expect("field_addr build");
-        field_addr.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        assert_byte_addressed_field(&ctx, module, 5, 1);
-    }
-
-    /// A by-value packed struct is represented by an LLVM packed struct, so
-    /// construction can use the ordinary insertvalue chain without changing
-    /// rustc's field offsets or total byte size.
-    #[test]
-    fn packed_struct_construction_by_value_uses_packed_layout() {
-        use dialect_mir::ops::MirConstructStructOp;
-
-        let mut ctx = make_ctx();
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Packed".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![0, 1],
-            vec![0, 1],
-            5,
-            1,
-        )
-        .into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![u8_ty, u32_ty], vec![]);
-        let tag = block.deref(&ctx).get_argument(0);
-        let value = block.deref(&ctx).get_argument(1);
-
-        let construct = Operation::new(
-            &mut ctx,
-            MirConstructStructOp::get_concrete_op_info(),
-            vec![packed_ty],
-            vec![tag, value],
-            vec![],
-            0,
-        );
-        construct.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module)
-            .expect("constructing a pointer-free packed struct by value must lower");
-
-        let body = kernel_blocks(&ctx, module);
-        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
-        assert_eq!(
-            insert_indices(&ctx, &inserts),
-            vec![vec![0], vec![1]],
-            "packed construction must keep declaration fields in their packed LLVM slots"
-        );
-        let result_ty = inserts
-            .last()
-            .expect("packed construction must emit insertvalue")
-            .get_operation()
-            .deref(&ctx)
-            .get_result(0)
-            .get_type(&ctx);
-        let result_ty_ref = result_ty.deref(&ctx);
-        let struct_ty = result_ty_ref
-            .downcast_ref::<llvm_types::StructType>()
-            .expect("packed construction result must be an LLVM struct");
-        assert_eq!(struct_ty.layout(), llvm_types::StructLayout::Packed);
-        assert_eq!(llvm_type_size_align(&ctx, result_ty), Some((5, 1)));
-    }
-
-    #[test]
-    fn packed_struct_construction_with_one_direct_shared_pointer_stays_semantic_in_ssa() {
-        use dialect_mir::ops::MirConstructStructOp;
-
-        let mut ctx = make_ctx();
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let shared_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedShared".into(),
-            vec!["tag".into(), "ptr".into()],
-            vec![u8_ty, shared_ty],
-            vec![0, 1],
-            vec![0, 1],
-            9,
-            1,
-        )
-        .into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![u8_ty, shared_ty], vec![]);
-        let tag = block.deref(&ctx).get_argument(0);
-        let ptr = block.deref(&ctx).get_argument(1);
-        let construct = Operation::new(
-            &mut ctx,
-            MirConstructStructOp::get_concrete_op_info(),
-            vec![packed_ty],
-            vec![tag, ptr],
-            vec![],
-            0,
-        );
-        construct.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module)
-            .expect("one direct AS3 pointer in a packed SSA aggregate must lower");
-
-        let body = kernel_blocks(&ctx, module);
-        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
-        assert_eq!(
-            insert_indices(&ctx, &inserts),
-            vec![vec![0], vec![1]],
-            "packed AS3 construction must preserve the semantic packed field slots"
-        );
-
-        let result_ty = inserts
-            .last()
-            .expect("packed AS3 construction must emit insertvalue")
-            .get_operation()
-            .deref(&ctx)
-            .get_result(0)
-            .get_type(&ctx);
-        let result_ty_ref = result_ty.deref(&ctx);
-        let struct_ty = result_ty_ref
-            .downcast_ref::<llvm_types::StructType>()
-            .expect("packed AS3 construction result must be an LLVM struct");
-        assert_eq!(struct_ty.layout(), llvm_types::StructLayout::Packed);
-        assert_eq!(llvm_type_size_align(&ctx, result_ty), Some((9, 1)));
-
-        let pointer_ty = struct_ty.field_type(1);
-        let pointer_ty_ref = pointer_ty.deref(&ctx);
-        let pointer = pointer_ty_ref
-            .downcast_ref::<llvm_types::PointerType>()
-            .expect("second packed field must remain a pointer");
-        assert_eq!(
-            pointer.address_space(),
-            llvm_types::address_space::SHARED,
-            "construction must keep the semantic pointer in AS3"
-        );
-        assert_eq!(
-            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
-            0,
-            "construction itself must not genericize the shared pointer"
-        );
-    }
-
-    #[test]
-    fn packed_struct_construction_with_multiple_direct_shared_pointers_stays_semantic_in_ssa() {
-        use dialect_mir::ops::MirConstructStructOp;
-
-        let mut ctx = make_ctx();
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let shared_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedSharedPair".into(),
-            vec!["tag".into(), "left".into(), "right".into()],
-            vec![u8_ty, shared_ty, shared_ty],
-            vec![0, 1, 2],
-            vec![0, 1, 9],
-            17,
-            1,
-        )
-        .into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![u8_ty, shared_ty, shared_ty], vec![]);
-        let tag = block.deref(&ctx).get_argument(0);
-        let left = block.deref(&ctx).get_argument(1);
-        let right = block.deref(&ctx).get_argument(2);
-        let construct = Operation::new(
-            &mut ctx,
-            MirConstructStructOp::get_concrete_op_info(),
-            vec![packed_ty],
-            vec![tag, left, right],
-            vec![],
-            0,
-        );
-        construct.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module)
-            .expect("multiple direct AS3 leaves in a packed SSA aggregate must lower");
-
-        let body = kernel_blocks(&ctx, module);
-        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
-        assert_eq!(
-            insert_indices(&ctx, &inserts),
-            vec![vec![0], vec![1], vec![2]],
-            "all direct shared leaves must remain in their semantic packed slots"
-        );
-
-        let result_ty = inserts
-            .last()
-            .expect("packed AS3 construction must emit insertvalue")
-            .get_operation()
-            .deref(&ctx)
-            .get_result(0)
-            .get_type(&ctx);
-        let result_ty_ref = result_ty.deref(&ctx);
-        let struct_ty = result_ty_ref
-            .downcast_ref::<llvm_types::StructType>()
-            .expect("packed AS3 construction result must be an LLVM struct");
-        assert_eq!(struct_ty.layout(), llvm_types::StructLayout::Packed);
-        assert_eq!(llvm_type_size_align(&ctx, result_ty), Some((17, 1)));
-        for slot in [1usize, 2] {
-            let pointer_ty = struct_ty.field_type(slot);
-            let pointer_ty_ref = pointer_ty.deref(&ctx);
-            let pointer = pointer_ty_ref
-                .downcast_ref::<llvm_types::PointerType>()
-                .expect("direct shared leaves must remain pointer-typed");
-            assert_eq!(pointer.address_space(), llvm_types::address_space::SHARED);
-        }
-        assert_eq!(
-            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
-            0,
-            "semantic construction must not genericize any direct shared leaf"
-        );
-    }
-
-    #[test]
-    fn packed_struct_construction_with_nested_shared_pointers_stays_semantic_in_ssa() {
-        use dialect_mir::ops::MirConstructStructOp;
-
-        let mut ctx = make_ctx();
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let shared_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let inner_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "SharedPair".into(),
-            vec!["left".into(), "right".into()],
-            vec![shared_ty, shared_ty],
-            vec![0, 1],
-            vec![0, 8],
-            16,
-            8,
-        )
-        .into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedNestedShared".into(),
-            vec!["tag".into(), "pair".into()],
-            vec![u8_ty, inner_ty],
-            vec![0, 1],
-            vec![0, 1],
-            17,
-            1,
-        )
-        .into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![u8_ty, shared_ty, shared_ty], vec![]);
-        let tag = block.deref(&ctx).get_argument(0);
-        let left = block.deref(&ctx).get_argument(1);
-        let right = block.deref(&ctx).get_argument(2);
-
-        let inner = Operation::new(
-            &mut ctx,
-            MirConstructStructOp::get_concrete_op_info(),
-            vec![inner_ty],
-            vec![left, right],
-            vec![],
-            0,
-        );
-        inner.insert_at_back(block, &ctx);
-        let inner_value = inner.deref(&ctx).get_result(0);
-
-        let outer = Operation::new(
-            &mut ctx,
-            MirConstructStructOp::get_concrete_op_info(),
-            vec![packed_ty],
-            vec![tag, inner_value],
-            vec![],
-            0,
-        );
-        outer.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module)
-            .expect("nested AS3 leaves in a packed SSA aggregate must lower");
-
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(
-            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
-            0,
-            "semantic construction must keep nested shared leaves in AS3"
-        );
-
-        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
-        let packed_result = inserts
-            .iter()
-            .filter_map(|insert| {
-                let result_ty = insert
-                    .get_operation()
-                    .deref(&ctx)
-                    .get_result(0)
-                    .get_type(&ctx);
-                let is_packed = result_ty
-                    .deref(&ctx)
-                    .downcast_ref::<llvm_types::StructType>()
-                    .is_some_and(|ty| ty.layout() == llvm_types::StructLayout::Packed);
-                is_packed.then_some(result_ty)
-            })
-            .last()
-            .expect("outer packed construction must produce a packed LLVM struct");
-
-        assert_eq!(llvm_type_size_align(&ctx, packed_result), Some((17, 1)));
-        assert!(
-            llvm_packed_struct_contains_pointer_in_address_space(
-                &ctx,
-                packed_result,
-                llvm_types::address_space::SHARED,
-            ),
-            "the semantic packed value must retain its recursively nested AS3 leaves"
-        );
-    }
-
-    #[test]
-    fn packed_struct_construction_with_bounded_shared_pointer_array_stays_semantic_in_ssa() {
-        use dialect_mir::ops::{MirConstructArrayOp, MirConstructStructOp};
-
-        let mut ctx = make_ctx();
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let shared_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let array_ty: TypeHandle = MirArrayType::get(&mut ctx, shared_ty, 2).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedSharedArray".into(),
-            vec!["tag".into(), "ptrs".into()],
-            vec![u8_ty, array_ty],
-            vec![0, 1],
-            vec![0, 1],
-            17,
-            1,
-        )
-        .into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![u8_ty, shared_ty, shared_ty], vec![]);
-        let tag = block.deref(&ctx).get_argument(0);
-        let left = block.deref(&ctx).get_argument(1);
-        let right = block.deref(&ctx).get_argument(2);
-
-        let array = Operation::new(
-            &mut ctx,
-            MirConstructArrayOp::get_concrete_op_info(),
-            vec![array_ty],
-            vec![left, right],
-            vec![],
-            0,
-        );
-        array.insert_at_back(block, &ctx);
-        let array_value = array.deref(&ctx).get_result(0);
-
-        let outer = Operation::new(
-            &mut ctx,
-            MirConstructStructOp::get_concrete_op_info(),
-            vec![packed_ty],
-            vec![tag, array_value],
-            vec![],
-            0,
-        );
-        outer.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module)
-            .expect("a bounded AS3 array in a packed SSA aggregate must lower");
-
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(
-            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
-            0,
-            "semantic construction must keep array elements in AS3"
-        );
-
-        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
-        let packed_result = inserts
-            .iter()
-            .filter_map(|insert| {
-                let result_ty = insert
-                    .get_operation()
-                    .deref(&ctx)
-                    .get_result(0)
-                    .get_type(&ctx);
-                let is_packed = result_ty
-                    .deref(&ctx)
-                    .downcast_ref::<llvm_types::StructType>()
-                    .is_some_and(|ty| ty.layout() == llvm_types::StructLayout::Packed);
-                is_packed.then_some(result_ty)
-            })
-            .last()
-            .expect("outer packed array construction must produce a packed LLVM struct");
-        assert_eq!(llvm_type_size_align(&ctx, packed_result), Some((17, 1)));
-        assert!(
-            llvm_packed_struct_contains_pointer_in_address_space(
-                &ctx,
-                packed_result,
-                llvm_types::address_space::SHARED,
-            ),
-            "the semantic packed value must retain AS3 array elements"
-        );
-    }
-
-    /// Packed LLVM element types carry the same allocation size as rustc, so
-    /// typed array GEPs now stride by the correct packed byte count.
-    #[test]
-    fn packed_array_element_addressing_uses_packed_stride() {
-        use dialect_mir::ops::MirArrayElementAddrOp;
-
-        let mut ctx = make_ctx();
-
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let u64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Packed".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![0, 1],
-            vec![0, 1],
-            5,
-            1,
-        )
-        .into();
-        let array_ty: TypeHandle = MirArrayType::get(&mut ctx, packed_ty, 4).into();
-        let base_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, array_ty, false).into();
-        let elem_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, packed_ty, false).into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![base_ptr_ty, u64_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-        let index = block.deref(&ctx).get_argument(1);
-
-        let elem_addr = Operation::new(
-            &mut ctx,
-            MirArrayElementAddrOp::get_concrete_op_info(),
-            vec![elem_ptr_ty],
-            vec![base, index],
-            vec![],
-            0,
-        );
-        elem_addr.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module)
-            .expect("packed element addressing must use the packed LLVM stride");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(
-            count_ops::<llvm::GetElementPtrOp>(&ctx, &body),
-            1,
-            "packed array element addressing should lower to one typed GEP"
-        );
-    }
-
-    /// Enum construction must store the declared discriminant value, not the
-    /// variant index. This locks the `Ordering::Less = -1` style case as the
-    /// i8 bit-pattern `255`.
-    #[test]
-    fn construct_enum_uses_declared_discriminant_not_variant_index() {
-        let mut ctx = make_ctx();
-
-        let discr_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signed).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "OrderingLike".to_string(),
-            discr_ty,
-            vec![255, 0, 1],
-            vec![
-                EnumVariant::unit("Less".to_string()),
-                EnumVariant::unit("Equal".to_string()),
-                EnumVariant::unit("Greater".to_string()),
-            ],
-            0,
-            1,
-            1,
-        )
-        .into();
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-
-        let op = Operation::new(
-            &mut ctx,
-            MirConstructEnumOp::get_concrete_op_info(),
-            vec![enum_ty],
-            vec![],
-            vec![],
-            0,
-        );
-        MirConstructEnumOp::new(op)
-            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
-        op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
-
-        assert_eq!(
-            insert_indices(&ctx, &inserts),
-            vec![vec![0]],
-            "unit enum construction should insert only the discriminant tag"
-        );
-        let tag_insert = &inserts[0];
-        assert!(
-            tag_insert.verify(&ctx).is_ok(),
-            "the enum tag insertion must satisfy LLVM dialect verification"
-        );
-        let tag = tag_insert.get_operation().deref(&ctx).get_operand(1);
-        let tag_def = tag
-            .defining_op()
-            .expect("the inserted enum tag must have a defining operation");
-        let tag_constant = Operation::get_op::<llvm::ConstantOp>(tag_def, &ctx)
-            .expect("the inserted enum tag must be defined by llvm.constant");
-        let tag_attr = tag_constant.get_value(&ctx);
-        let tag_integer = tag_attr
-            .downcast_ref::<IntegerAttr>()
-            .expect("the inserted enum tag must be an integer constant");
-        assert_eq!(tag_integer.value().bw(), 8, "the enum tag must be 8-bit");
-        assert_eq!(
-            tag_integer.value().to_u64(),
-            255,
-            "Less must lower to its declared i8 bit-pattern 255, not variant index 0"
-        );
-    }
-
-    #[test]
-    fn nested_pointer_niche_tuple_construct_extract_and_discriminant_lower() {
-        let mut ctx = make_ctx();
-        let logical: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
-        let index: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
-        let tuple_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![index, pointer]).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "Option".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![tuple_ty], vec![0], vec![16]),
-            ],
-            EnumEncoding {
-                tag_offset: 8,
-                total_size: 16,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        let slot_map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(slot_map.carrier_slot, Some(1));
-        assert_eq!(slot_map.field_slots, vec![None]);
-        let lowered_tuple = convert_type(&mut ctx, tuple_ty).unwrap();
-
-        let (module, block) = build_kernel(&mut ctx, vec![index, pointer], vec![]);
-        let index_value = block.deref(&ctx).get_argument(0);
-        let pointer_value = block.deref(&ctx).get_argument(1);
-        let tuple = Operation::new(
-            &mut ctx,
-            mir::MirConstructTupleOp::get_concrete_op_info(),
-            vec![tuple_ty],
-            vec![index_value, pointer_value],
-            vec![],
-            0,
-        );
-        tuple.insert_at_back(block, &ctx);
-        let tuple_value = tuple.deref(&ctx).get_result(0);
-
-        let construct = Operation::new(
-            &mut ctx,
-            mir::MirConstructEnumOp::get_concrete_op_info(),
-            vec![enum_ty],
-            vec![tuple_value],
-            vec![],
-            0,
-        );
-        mir::MirConstructEnumOp::new(construct)
-            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
-        construct.insert_at_back(block, &ctx);
-        let enum_value = construct.deref(&ctx).get_result(0);
-
-        let payload = Operation::new(
-            &mut ctx,
-            mir::MirEnumPayloadOp::get_concrete_op_info(),
-            vec![tuple_ty],
-            vec![enum_value],
-            vec![],
-            0,
-        );
-        mir::MirEnumPayloadOp::new(payload)
-            .set_attr_payload_variant_index(&ctx, VariantIndexAttr(1));
-        mir::MirEnumPayloadOp::new(payload).set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
-        payload.insert_at_back(block, &ctx);
-
-        let discriminant = Operation::new(
-            &mut ctx,
-            mir::MirGetDiscriminantOp::get_concrete_op_info(),
-            vec![logical],
-            vec![enum_value],
-            vec![],
-            0,
-        );
-        discriminant.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(
-            count_ops::<llvm::IntToPtrOp>(&ctx, &body),
-            0,
-            "constructing the untagged Some payload must not recreate its pointer from bits"
-        );
-        assert_eq!(
-            count_ops::<llvm::PtrToIntOp>(&ctx, &body),
-            1,
-            "reading the pointer niche should inspect the carrier exactly once"
-        );
-        assert_eq!(
-            count_ops::<llvm::StoreOp>(&ctx, &body),
-            3,
-            "construction and extraction should each spill the enum, plus one tuple payload store"
-        );
-        assert_eq!(
-            count_ops::<llvm::LoadOp>(&ctx, &body),
-            2,
-            "construction should reload the enum and extraction should load the tuple payload"
-        );
-        // What this test is about is that the payload moves as one unit, never
-        // field by field. Assert that property directly instead of counting
-        // whole-aggregate accesses.
-        //
-        // Counting was the fragile form. The enum's physical storage here is
-        // `{i64, ptr}` -- the *same interned type* as the lowered payload tuple,
-        // since the niche carrier claims the pointer at byte 8 and the 8 bytes
-        // below it become one `i64` filler. So a count of `lowered_tuple`-typed
-        // accesses cannot separate the payload write from the enum spill, and
-        // the expected numbers move whenever that coincidence appears or
-        // disappears -- which has nothing to do with the property under test.
-        //
-        // A lowering that decomposed the payload is recognisable by what it
-        // emits instead: traffic in the tuple's *field* types. Look for that,
-        // and the assertion holds whatever the enum storage type happens to be.
-        let field_tys: Vec<TypeHandle> = lowered_tuple
-            .deref(&ctx)
-            .downcast_ref::<llvm_types::StructType>()
-            .expect("the lowered tuple is an LLVM struct")
-            .fields()
-            .collect();
-
-        let store_tys: Vec<TypeHandle> = find_all::<llvm::StoreOp>(&ctx, &body)
-            .iter()
-            .map(|store| store.get_operand_value(&ctx).get_type(&ctx))
-            .collect();
-        let load_tys: Vec<TypeHandle> = find_all::<llvm::LoadOp>(&ctx, &body)
-            .iter()
-            .map(|load| {
-                load.get_operation()
-                    .deref(&ctx)
-                    .get_result(0)
-                    .get_type(&ctx)
-            })
-            .collect();
-
-        let describe = |tys: &[TypeHandle]| -> Vec<String> {
-            tys.iter()
-                .filter(|ty| field_tys.contains(ty))
-                .map(|ty| ty.deref(&ctx).disp(&ctx).to_string())
-                .collect()
-        };
-        assert!(
-            describe(&store_tys).is_empty(),
-            "the payload must be stored whole, but these field-typed stores appear: {:?}",
-            describe(&store_tys)
-        );
-        assert!(
-            describe(&load_tys).is_empty(),
-            "the payload must be read whole, but these field-typed loads appear: {:?}",
-            describe(&load_tys)
-        );
-
-        // And it must actually be moved: without this the checks above would
-        // also pass a lowering that emitted no payload traffic at all.
-        assert!(
-            store_tys.contains(&lowered_tuple),
-            "at least one store must move the complete {{i64, ptr}} payload"
-        );
-        assert!(
-            load_tys.contains(&lowered_tuple),
-            "at least one load must read the complete {{i64, ptr}} payload"
-        );
-    }
-
-    /// SetDiscriminant must use the slot map instead of assuming that the tag
-    /// is field zero, and its GEP must retain the source pointer's GPU address
-    /// space. This shape puts an i64 payload first and an i8 tag above the
-    /// u32 range, proving the byte GEP does not truncate offsets to u32.
-    #[test]
-    fn set_discriminant_uses_tag_slot_and_preserves_shared_address_space() {
-        use llvm_export::ops::GepIndex;
-        use llvm_export::types::{PointerType, address_space};
-
-        let mut ctx = make_ctx();
-        let discr_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let payload_a: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let payload_b: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let tag_offset = u64::from(u32::MAX) + 1;
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "TagAfterPayload".to_string(),
-            discr_ty,
-            vec![3, 7],
-            vec![
-                EnumVariant::new_with_layout("A".to_string(), vec![payload_a], vec![0], vec![8]),
-                EnumVariant::new_with_layout("B".to_string(), vec![payload_b], vec![0], vec![8]),
-            ],
-            tag_offset,
-            tag_offset + 8,
-            8,
-        )
-        .into();
-        let ptr_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, enum_ty, true).into();
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty], vec![]);
-        let enum_ptr = block.deref(&ctx).get_argument(0);
-        let set = Operation::new(
-            &mut ctx,
-            mir::MirSetDiscriminantOp::get_concrete_op_info(),
-            vec![],
-            vec![enum_ptr],
-            vec![],
-            0,
-        );
-        let set_op = mir::MirSetDiscriminantOp::new(set);
-        set_op.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(1));
-        set_op.set_attr_set_discriminant_enum_ty(
-            &ctx,
-            pliron::builtin::attributes::TypeAttr::new(enum_ty),
-        );
-        set.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        assert_eq!(count_ops::<mir::MirSetDiscriminantOp>(&ctx, &body), 0);
-        assert_eq!(count_ops::<llvm::GetElementPtrOp>(&ctx, &body), 1);
-        assert_eq!(count_ops::<llvm::StoreOp>(&ctx, &body), 1);
-
-        let gep = find_first::<llvm::GetElementPtrOp>(&ctx, &body).unwrap();
-        let indices = gep.indices(&ctx);
-        assert!(matches!(indices.as_slice(), [GepIndex::Value(_)]));
-        let GepIndex::Value(offset) = indices[0] else {
-            unreachable!()
-        };
-        let offset_def = offset.defining_op().expect("byte offset must be constant");
-        let offset_constant = Operation::get_op::<llvm::ConstantOp>(offset_def, &ctx)
-            .expect("byte offset must be an LLVM constant");
-        let offset_attr = offset_constant.get_value(&ctx);
-        assert_eq!(
-            offset_attr
-                .downcast_ref::<IntegerAttr>()
-                .expect("byte offset must be integer")
-                .value()
-                .to_u64(),
-            tag_offset,
-            "the write must use rustc's absolute carrier byte offset"
-        );
-        let gep_result_ty = gep.get_operation().deref(&ctx).get_result(0).get_type(&ctx);
-        assert_eq!(
-            gep_result_ty
-                .deref(&ctx)
-                .downcast_ref::<PointerType>()
-                .expect("GEP result must be a pointer")
-                .address_space(),
-            address_space::SHARED,
-            "tag GEP must preserve shared address space"
-        );
-
-        let store = find_first::<llvm::StoreOp>(&ctx, &body).unwrap();
-        let stored_ty = store.get_operand_value(&ctx).get_type(&ctx);
-        assert_eq!(
-            stored_ty
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .expect("stored tag must be an integer")
-                .width(),
-            8
-        );
-        assert_eq!(
-            store.get_operand_address(&ctx),
-            gep.get_operation().deref(&ctx).get_result(0),
-            "the store must use the tag GEP result"
-        );
-    }
-
-    fn unit_niche_enum(
-        ctx: &mut Context,
-        carrier: (EnumCarrierKind, u32, u32),
-        niche_start: u128,
-        niche_range: std::ops::RangeInclusive<u32>,
-        untagged_variant: u32,
-        inhabited: Vec<u8>,
-    ) -> TypeHandle {
-        let (carrier_kind, carrier_width, carrier_address_space) = carrier;
-        let logical_width = if inhabited.len() > u8::MAX as usize {
-            16
-        } else {
-            8
-        };
-        let logical_ty: TypeHandle =
-            IntegerType::get(ctx, logical_width, Signedness::Unsigned).into();
-        let variants = (0..inhabited.len())
-            .map(|index| EnumVariant::unit(format!("V{index}")))
-            .collect::<Vec<_>>();
-        let discriminants = (0..inhabited.len() as u64).collect();
-        let carrier_size = u64::from(carrier_width).div_ceil(8);
-        let carrier_align = carrier_size.next_power_of_two().min(16);
-        MirEnumType::get_with_encoding(
-            ctx,
-            "UnitNiche".into(),
-            logical_ty,
-            discriminants,
-            variants,
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: carrier_size,
-                abi_align: carrier_align,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind,
-                carrier_width,
-                carrier_address_space,
-                niche_start,
-                niche_variant_start: *niche_range.start(),
-                niche_variant_end: *niche_range.end(),
-                untagged_variant,
-                variant_inhabited: inhabited,
-                ..EnumEncoding::default()
-            },
-        )
-        .into()
-    }
-
-    fn over_aligned_tuple_ty(ctx: &mut Context) -> TypeHandle {
-        let byte: TypeHandle = IntegerType::get(ctx, 8, Signedness::Unsigned).into();
-        let marker: TypeHandle = MirStructType::get_with_full_layout(
-            ctx,
-            "Align32".into(),
-            vec![],
-            vec![],
-            vec![],
-            vec![],
-            0,
-            32,
-        )
-        .into();
-        MirTupleType::get_with_layout(ctx, vec![marker, byte], vec![0, 1], vec![0, 0], 32, 32)
-            .into()
-    }
-
-    fn lower_array_extract_case(
-        ctx: &mut Context,
-        array_size: u64,
-        divisor: Option<u64>,
-    ) -> Ptr<Operation> {
-        let element_type: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-        let index_type = IntegerType::get(ctx, 64, Signedness::Unsigned);
-        let index_handle: TypeHandle = index_type.into();
-        let array_type: TypeHandle = MirArrayType::get(ctx, element_type, array_size).into();
-
-        let (module, block) = build_kernel(ctx, vec![index_handle], vec![element_type]);
-        let raw_index = block.deref(ctx).get_argument(0);
-
-        let undef = mir::MirUndefOp::new(ctx, array_type);
-        undef.get_operation().insert_at_back(block, ctx);
-        let array = undef.get_operation().deref(ctx).get_result(0);
-
-        let index = if let Some(divisor) = divisor {
-            let constant = Operation::new(
-                ctx,
-                mir::MirConstantOp::get_concrete_op_info(),
-                vec![index_handle],
-                vec![],
-                vec![],
-                0,
-            );
-            mir::MirConstantOp::new(constant).set_attr_value(
-                ctx,
-                IntegerAttr::new(
-                    index_type,
-                    APInt::from_u64(divisor, NonZeroUsize::new(64).unwrap()),
-                ),
-            );
-            constant.insert_at_back(block, ctx);
-            let divisor_value = constant.deref(ctx).get_result(0);
-
-            let rem = Operation::new(
-                ctx,
-                mir::MirRemOp::get_concrete_op_info(),
-                vec![index_handle],
-                vec![raw_index, divisor_value],
-                vec![],
-                0,
-            );
-            rem.insert_at_back(block, ctx);
-            rem.deref(ctx).get_result(0)
-        } else {
-            raw_index
-        };
-
-        let extract = Operation::new(
-            ctx,
-            mir::MirExtractArrayElementOp::get_concrete_op_info(),
-            vec![element_type],
-            vec![array, index],
-            vec![],
-            0,
-        );
-        extract.insert_at_back(block, ctx);
-        let result = extract.deref(ctx).get_result(0);
-        append_mir_return(ctx, block, vec![result]);
-
-        crate::lower_mir_to_llvm(ctx, module).expect("lowering failed");
-        module
-    }
-
-    fn assert_array_extract_memory_fallback(ctx: &Context, module: Ptr<Operation>) {
-        let body = kernel_blocks(ctx, module);
-        assert_eq!(count_ops::<llvm::AllocaOp>(ctx, &body), 1);
-        assert_eq!(count_ops::<llvm::StoreOp>(ctx, &body), 1);
-        assert_eq!(count_ops::<llvm::GetElementPtrOp>(ctx, &body), 1);
-        assert_eq!(count_ops::<llvm::LoadOp>(ctx, &body), 1);
-        assert_eq!(count_ops::<llvm::SelectOp>(ctx, &body), 0);
-    }
-
-    #[test]
-    fn bounded_urem_array_extract_stays_in_ssa() {
-        let mut ctx = make_ctx();
-        let module = lower_array_extract_case(&mut ctx, 3, Some(3));
-        let body = kernel_blocks(&ctx, module);
-
-        assert_eq!(count_ops::<llvm::ExtractValueOp>(&ctx, &body), 3);
-        assert_eq!(count_ops::<llvm::ICmpOp>(&ctx, &body), 2);
-        assert_eq!(count_ops::<llvm::SelectOp>(&ctx, &body), 2);
-        assert_eq!(count_ops::<llvm::AllocaOp>(&ctx, &body), 0);
-        assert_eq!(count_ops::<llvm::StoreOp>(&ctx, &body), 0);
-        assert_eq!(count_ops::<llvm::GetElementPtrOp>(&ctx, &body), 0);
-        assert_eq!(count_ops::<llvm::LoadOp>(&ctx, &body), 0);
-    }
-
-    #[test]
-    fn unbounded_array_extract_keeps_memory_fallback() {
-        let mut ctx = make_ctx();
-        let module = lower_array_extract_case(&mut ctx, 3, None);
-        assert_array_extract_memory_fallback(&ctx, module);
-    }
-
-    #[test]
-    fn oversized_urem_array_extract_keeps_memory_fallback() {
-        let mut ctx = make_ctx();
-        let module = lower_array_extract_case(&mut ctx, 17, Some(17));
-        assert_array_extract_memory_fallback(&ctx, module);
-    }
-
-    #[test]
-    fn dynamic_array_extract_preserves_recursive_element_alignment() {
-        let mut ctx = make_ctx();
-        let tuple_ty = over_aligned_tuple_ty(&mut ctx);
-        let inner: TypeHandle = MirArrayType::get(&mut ctx, tuple_ty, 2).into();
-        let outer: TypeHandle = MirArrayType::get(&mut ctx, inner, 3).into();
-        let index_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![index_ty], vec![]);
-        let index = block.deref(&ctx).get_argument(0);
-
-        let undef = mir::MirUndefOp::new(&mut ctx, outer);
-        undef.get_operation().insert_at_back(block, &ctx);
-        let array = undef.get_operation().deref(&ctx).get_result(0);
-        let extract = Operation::new(
-            &mut ctx,
-            mir::MirExtractArrayElementOp::get_concrete_op_info(),
-            vec![inner],
-            vec![array, index],
-            vec![],
-            0,
-        );
-        extract.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).expect("expected llvm.alloca");
-        let store = find_first::<llvm::StoreOp>(&ctx, &body).expect("expected llvm.store");
-        let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected llvm.load");
-        for memory_op in [
-            alloca.get_operation(),
-            store.get_operation(),
-            load.get_operation(),
-        ] {
-            assert_eq!(llvm_export::ops::op_alignment(&ctx, memory_op), Some(32));
-        }
-    }
-
-    #[test]
-    fn niche_encoding_handles_untagged_inside_range_and_u128_wrap() {
-        let mut ctx = make_ctx();
-        let inside = unit_niche_enum(
-            &mut ctx,
-            (EnumCarrierKind::Integer, 8, 0),
-            42,
-            0..=1,
-            1,
-            vec![1, 1],
-        );
-        let inside_ref = inside.deref(&ctx);
-        let inside_enum = inside_ref.downcast_ref::<MirEnumType>().unwrap();
-        assert_eq!(enum_carrier_bits_for_variant(inside_enum, 0), Ok(Some(42)));
-        assert_eq!(
-            enum_carrier_bits_for_variant(inside_enum, 1),
-            Ok(None),
-            "the untagged variant is a no-op even when its index is in the niche range"
-        );
-        drop(inside_ref);
-
-        let wrapping = unit_niche_enum(
-            &mut ctx,
-            (EnumCarrierKind::Integer, 128, 0),
-            u128::MAX,
-            0..=1,
-            0,
-            vec![1, 1],
-        );
-        let wrapping_ref = wrapping.deref(&ctx);
-        let wrapping_enum = wrapping_ref.downcast_ref::<MirEnumType>().unwrap();
-        assert_eq!(
-            enum_carrier_bits_for_variant(wrapping_enum, 1),
-            Ok(Some(0)),
-            "niche arithmetic must wrap across the full u128 carrier"
-        );
-    }
-
-    #[test]
-    fn set_discriminant_niche_writes_only_tagged_variant_carrier() {
-        for (target, expected_stores) in [(0, 1), (1, 0)] {
-            let mut ctx = make_ctx();
-            let enum_ty = unit_niche_enum(
-                &mut ctx,
-                (EnumCarrierKind::Integer, 8, 0),
-                0,
-                0..=0,
-                1,
-                vec![1, 1],
-            );
-            let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, true).into();
-            let (module, block) = build_kernel(&mut ctx, vec![ptr_ty], vec![]);
-            let ptr = block.deref(&ctx).get_argument(0);
-            let set = Operation::new(
-                &mut ctx,
-                mir::MirSetDiscriminantOp::get_concrete_op_info(),
-                vec![],
-                vec![ptr],
-                vec![],
-                0,
-            );
-            let set_op = mir::MirSetDiscriminantOp::new(set);
-            set_op.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(target));
-            set_op.set_attr_set_discriminant_enum_ty(
-                &ctx,
-                pliron::builtin::attributes::TypeAttr::new(enum_ty),
-            );
-            set.insert_at_back(block, &ctx);
-            append_mir_return(&mut ctx, block, vec![]);
-
-            crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-            let body = kernel_blocks(&ctx, module);
-            assert_eq!(count_ops::<llvm::StoreOp>(&ctx, &body), expected_stores);
-            assert_eq!(count_ops::<mir::MirSetDiscriminantOp>(&ctx, &body), 0);
-        }
-    }
-
-    #[test]
-    fn shared_pointer_niche_carrier_rejects_target_dependent_width() {
-        let mut ctx = make_ctx();
-        let enum_ty = unit_niche_enum(
-            &mut ctx,
-            (EnumCarrierKind::Pointer, 64, 3),
-            0,
-            0..=0,
-            1,
-            vec![1, 1],
-        );
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("shared pointer carrier must reject");
-        assert!(
-            error.to_string().contains("target-mode dependent"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn shared_pointer_niche_payload_round_trips_through_generic_storage() {
-        let mut ctx = make_ctx();
-        let logical: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
-        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, true).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "OptionShared".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![shared], vec![0], vec![8]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 8,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                carrier_address_space: llvm_types::address_space::GENERIC,
-                niche_start: 0,
-                niche_variant_start: 0,
-                niche_variant_end: 0,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![shared], vec![shared]);
-        let pointer = block.deref(&ctx).get_argument(0);
-        let construct = Operation::new(
-            &mut ctx,
-            MirConstructEnumOp::get_concrete_op_info(),
-            vec![enum_ty],
-            vec![pointer],
-            vec![],
-            0,
-        );
-        MirConstructEnumOp::new(construct)
-            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
-        construct.insert_at_back(block, &ctx);
-        let option = construct.deref(&ctx).get_result(0);
-
-        let discriminant = Operation::new(
-            &mut ctx,
-            mir::MirGetDiscriminantOp::get_concrete_op_info(),
-            vec![logical],
-            vec![option],
-            vec![],
-            0,
-        );
-        discriminant.insert_at_back(block, &ctx);
-
-        let payload = Operation::new(
-            &mut ctx,
-            MirEnumPayloadOp::get_concrete_op_info(),
-            vec![shared],
-            vec![option],
-            vec![],
-            0,
-        );
-        let payload_op = MirEnumPayloadOp::new(payload);
-        payload_op.set_attr_payload_variant_index(&ctx, VariantIndexAttr(1));
-        payload_op.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
-        payload.insert_at_back(block, &ctx);
-        let result = payload.deref(&ctx).get_result(0);
-        append_mir_return(&mut ctx, block, vec![result]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(
-            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
-            2,
-            "construction must genericize the pointer and extraction must restore shared space"
-        );
-        assert_eq!(
-            count_ops::<llvm::PtrToIntOp>(&ctx, &body),
-            1,
-            "niche discrimination must inspect the generic pointer carrier"
-        );
-        assert_eq!(count_ops::<MirConstructEnumOp>(&ctx, &body), 0);
-        assert_eq!(count_ops::<MirEnumPayloadOp>(&ctx, &body), 0);
-    }
-
-    #[test]
-    fn nested_shared_pointer_payload_round_trips_through_recursive_storage() {
-        let mut ctx = make_ctx();
-        let logical: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, true).into();
-        let inner: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "SharedPointerInner".into(),
-            vec!["pointer".into(), "cookie".into()],
-            vec![shared, logical],
-            vec![0, 1],
-            vec![0, 8],
-            16,
-            8,
-        )
-        .into();
-        let outer: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "SharedPointerOuter".into(),
-            vec!["inner".into(), "guard".into()],
-            vec![inner, logical],
-            vec![0, 1],
-            vec![0, 16],
-            24,
-            8,
-        )
-        .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "NestedSharedPointer".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![outer], vec![8], vec![24]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 32,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Direct,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 32,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![outer], vec![outer]);
-        let wrapper = block.deref(&ctx).get_argument(0);
-        let construct = Operation::new(
-            &mut ctx,
-            MirConstructEnumOp::get_concrete_op_info(),
-            vec![enum_ty],
-            vec![wrapper],
-            vec![],
-            0,
-        );
-        MirConstructEnumOp::new(construct)
-            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
-        construct.insert_at_back(block, &ctx);
-        let option = construct.deref(&ctx).get_result(0);
-
-        let payload = Operation::new(
-            &mut ctx,
-            MirEnumPayloadOp::get_concrete_op_info(),
-            vec![outer],
-            vec![option],
-            vec![],
-            0,
-        );
-        let payload_op = MirEnumPayloadOp::new(payload);
-        payload_op.set_attr_payload_variant_index(&ctx, VariantIndexAttr(1));
-        payload_op.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
-        payload.insert_at_back(block, &ctx);
-        let result = payload.deref(&ctx).get_result(0);
-        append_mir_return(&mut ctx, block, vec![result]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(
-            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
-            2,
-            "construction and extraction must cast the nested shared pointer leaf"
-        );
-        assert_eq!(count_ops::<MirConstructEnumOp>(&ctx, &body), 0);
-        assert_eq!(count_ops::<MirEnumPayloadOp>(&ctx, &body), 0);
-    }
-
-    #[test]
-    fn bounded_shared_pointer_array_niche_payload_round_trips_through_recursive_storage() {
-        let mut ctx = make_ctx();
-        let logical: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
-        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, true).into();
-        let pointers: TypeHandle = MirArrayType::get(&mut ctx, shared, 2).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "OptionSharedPointerArray".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![pointers], vec![0], vec![16]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 16,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                carrier_address_space: llvm_types::address_space::GENERIC,
-                niche_start: 0,
-                niche_variant_start: 0,
-                niche_variant_end: 0,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![pointers], vec![pointers]);
-        let array = block.deref(&ctx).get_argument(0);
-        let construct = Operation::new(
-            &mut ctx,
-            MirConstructEnumOp::get_concrete_op_info(),
-            vec![enum_ty],
-            vec![array],
-            vec![],
-            0,
-        );
-        MirConstructEnumOp::new(construct)
-            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
-        construct.insert_at_back(block, &ctx);
-        let option = construct.deref(&ctx).get_result(0);
-
-        let discriminant = Operation::new(
-            &mut ctx,
-            mir::MirGetDiscriminantOp::get_concrete_op_info(),
-            vec![logical],
-            vec![option],
-            vec![],
-            0,
-        );
-        discriminant.insert_at_back(block, &ctx);
-
-        let payload = Operation::new(
-            &mut ctx,
-            MirEnumPayloadOp::get_concrete_op_info(),
-            vec![pointers],
-            vec![option],
-            vec![],
-            0,
-        );
-        let payload_op = MirEnumPayloadOp::new(payload);
-        payload_op.set_attr_payload_variant_index(&ctx, VariantIndexAttr(1));
-        payload_op.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
-        payload.insert_at_back(block, &ctx);
-        let result = payload.deref(&ctx).get_result(0);
-        append_mir_return(&mut ctx, block, vec![result]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(
-            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
-            4,
-            "construction and extraction must cast both shared-pointer array elements"
-        );
-        assert_eq!(
-            count_ops::<llvm::PtrToIntOp>(&ctx, &body),
-            1,
-            "niche discrimination must inspect the generic first-pointer carrier"
-        );
-        assert_eq!(count_ops::<MirConstructEnumOp>(&ctx, &body), 0);
-        assert_eq!(count_ops::<MirEnumPayloadOp>(&ctx, &body), 0);
-    }
-
-    #[test]
-    fn option_bool_uses_i8_carrier_and_spills_i1_payload() {
-        let mut ctx = make_ctx();
-        let logical: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let bool_ty: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "OptionBool".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![bool_ty], vec![0], vec![1]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 1,
-                abi_align: 1,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 8,
-                niche_start: 2,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        let slot_map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(
-            slot_map
-                .carrier_llvm_ty
-                .unwrap()
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .unwrap()
-                .width(),
-            8,
-            "Option<bool>'s memory carrier is i8, not bool's semantic i1"
-        );
-        assert_eq!(slot_map.field_slots, vec![None]);
-
-        let (module, block) = build_kernel(&mut ctx, vec![bool_ty], vec![enum_ty]);
-        let payload = block.deref(&ctx).get_argument(0);
-        let construct = Operation::new(
-            &mut ctx,
-            mir::MirConstructEnumOp::get_concrete_op_info(),
-            vec![enum_ty],
-            vec![payload],
-            vec![],
-            0,
-        );
-        mir::MirConstructEnumOp::new(construct)
-            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
-        construct.insert_at_back(block, &ctx);
-        let result = construct.deref(&ctx).get_result(0);
-        append_mir_return(&mut ctx, block, vec![result]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(count_ops::<llvm::InsertValueOp>(&ctx, &body), 0);
-        assert!(find_all::<llvm::ZExtOp>(&ctx, &body).iter().any(|zext| {
-            zext.get_operation()
-                .deref(&ctx)
-                .get_operand(0)
-                .get_type(&ctx)
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .is_some_and(|integer| integer.width() == 1)
-                && zext
-                    .get_operation()
-                    .deref(&ctx)
-                    .get_result(0)
-                    .get_type(&ctx)
-                    .deref(&ctx)
-                    .downcast_ref::<IntegerType>()
-                    .is_some_and(|integer| integer.width() == 8)
-        }));
-        assert!(find_all::<llvm::StoreOp>(&ctx, &body).iter().any(|store| {
-            store
-                .get_operand_value(&ctx)
-                .get_type(&ctx)
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .is_some_and(|integer| integer.width() == 8)
-        }));
-    }
-
-    #[test]
-    fn direct_bool_uses_i8_storage_and_spills_i1_payload() {
-        let mut ctx = make_ctx();
-        let tag: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let bool_ty: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "DirectBool".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout("A".into(), vec![bool_ty], vec![4], vec![1]),
-                EnumVariant::unit("B".into()),
-            ],
-            0,
-            8,
-            4,
-        )
-        .into();
-        let slot_map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(slot_map.field_slots, vec![None]);
-        let storage_fields = slot_map
-            .llvm_struct_ty
-            .deref(&ctx)
-            .downcast_ref::<llvm_types::StructType>()
-            .expect("enum storage must be an LLVM struct")
-            .fields()
-            .collect::<Vec<_>>();
-        assert_eq!(
-            storage_fields[1]
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .map(IntegerType::width),
-            Some(8),
-            "the standalone Rust bool byte must use physical i8 storage"
-        );
-
-        let (module, block) = build_kernel(&mut ctx, vec![bool_ty], vec![enum_ty]);
-        let payload = block.deref(&ctx).get_argument(0);
-        let construct = Operation::new(
-            &mut ctx,
-            mir::MirConstructEnumOp::get_concrete_op_info(),
-            vec![enum_ty],
-            vec![payload],
-            vec![],
-            0,
-        );
-        mir::MirConstructEnumOp::new(construct)
-            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
-        construct.insert_at_back(block, &ctx);
-        let result = construct.deref(&ctx).get_result(0);
-        append_mir_return(&mut ctx, block, vec![result]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(
-            count_ops::<llvm::InsertValueOp>(&ctx, &body),
-            1,
-            "only the direct tag should be inserted as an SSA struct field"
-        );
-        assert!(find_all::<llvm::ZExtOp>(&ctx, &body).iter().any(|zext| {
-            zext.get_operation()
-                .deref(&ctx)
-                .get_operand(0)
-                .get_type(&ctx)
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .is_some_and(|integer| integer.width() == 1)
-                && zext
-                    .get_operation()
-                    .deref(&ctx)
-                    .get_result(0)
-                    .get_type(&ctx)
-                    .deref(&ctx)
-                    .downcast_ref::<IntegerType>()
-                    .is_some_and(|integer| integer.width() == 8)
-        }));
-        assert!(find_all::<llvm::StoreOp>(&ctx, &body).iter().any(|store| {
-            store
-                .get_operand_value(&ctx)
-                .get_type(&ctx)
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .is_some_and(|integer| integer.width() == 8)
-        }));
-    }
-
-    /// Taking the in-place address of a bool payload must fail loudly: the
-    /// payload's canonical storage is an i8 byte, and a semantic i1 store
-    /// through the escaped address would leave that byte's upper seven bits
-    /// undefined for every i8 reader (including a niche tag sharing them).
-    #[test]
-    fn bool_payload_field_addr_fails_closed() {
-        let mut ctx = make_ctx();
-        let tag: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let bool_ty: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "DirectBool".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout("A".into(), vec![bool_ty], vec![4], vec![1]),
-                EnumVariant::unit("B".into()),
-            ],
-            0,
-            8,
-            4,
-        )
-        .into();
-        let enum_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, true).into();
-        let bool_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, bool_ty, true).into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![enum_ptr_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-        let op = MirFieldAddrOp::build(&mut ctx, base, bool_ptr_ty, 0).expect("field_addr build");
-        op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        let err = crate::lower_mir_to_llvm(&mut ctx, module)
-            .expect_err("addressing a bool enum payload in place must fail to lower");
-        assert!(
-            err.err.to_string().contains("canonical storage type"),
-            "unexpected error: {}",
-            err.err
-        );
-    }
-
-    /// Same gate for the slot arm: a shared-memory pointer payload is stored
-    /// as a GENERIC pointer (its slot is typed `ptr`), so an in-place address
-    /// would let a semantic `ptr addrspace(3)` store write a representation
-    /// every other reader interprets as a generic pointer.
-    #[test]
-    fn shared_pointer_payload_field_addr_fails_closed() {
-        let mut ctx = make_ctx();
-        let logical: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
-        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, true).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "OptionShared".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![shared], vec![0], vec![8]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 8,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                carrier_address_space: llvm_types::address_space::GENERIC,
-                niche_start: 0,
-                niche_variant_start: 0,
-                niche_variant_end: 0,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        let enum_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, true).into();
-        let payload_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, shared, true).into();
-
-        let (module, block) = build_kernel(&mut ctx, vec![enum_ptr_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-        let op =
-            MirFieldAddrOp::build(&mut ctx, base, payload_ptr_ty, 0).expect("field_addr build");
-        op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        let err = crate::lower_mir_to_llvm(&mut ctx, module)
-            .expect_err("addressing a shared-pointer enum payload in place must fail to lower");
-        assert!(
-            err.err.to_string().contains("canonical storage type"),
-            "unexpected error: {}",
-            err.err
-        );
-    }
-
-    /// A payload with no slot of its own is addressed at its byte offset off
-    /// the ORIGINAL enum pointer: no stack spill is introduced, so a write
-    /// through the result lands in the enum rather than in a copy.
-    #[test]
-    fn slotless_payload_field_addr_geps_original_storage_at_byte_offset() {
-        use llvm_export::ops::GepIndex;
-        use pliron::builtin::types::FP32Type;
-
-        let mut ctx = make_ctx();
-        let tag: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let f32_ty: TypeHandle = FP32Type::get(&ctx).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "Either".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout("Real".into(), vec![f32_ty], vec![4], vec![4]),
-                EnumVariant::new_with_layout("Bits".into(), vec![u32_ty], vec![4], vec![4]),
-            ],
-            0,
-            8,
-            4,
-        )
-        .into();
-        let slot_map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(
-            slot_map.field_slots,
-            vec![Some(1), None],
-            "Real's f32 claims byte 4 first; Bits shares those bytes slotless"
-        );
-
-        let enum_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, true).into();
-        let u32_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, true).into();
-        let (module, block) = build_kernel(&mut ctx, vec![enum_ptr_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-        let op = MirFieldAddrOp::build(&mut ctx, base, u32_ptr_ty, 1).expect("field_addr build");
-        op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(
-            count_ops::<llvm::AllocaOp>(&ctx, &body),
-            0,
-            "an in-place payload address must not spill the enum to a stack copy"
-        );
-        let geps = find_all::<llvm::GetElementPtrOp>(&ctx, &body);
-        assert_eq!(geps.len(), 1, "one field_addr lowers to one GEP");
-        let gep = &geps[0];
-        // The MIR entry block and its arguments are the ORIGINALS (moved by
-        // `inline_region`), so the enum pointer argument keeps its identity
-        // through lowering and the GEP must be based directly on it.
-        assert_eq!(
-            gep.get_operation().deref(&ctx).get_operand(0),
-            base,
-            "the byte-offset GEP must address the ORIGINAL enum storage"
-        );
-        assert!(
-            matches!(gep.indices(&ctx).as_slice(), [GepIndex::Constant(4)]),
-            "the slotless payload must be addressed at its rustc byte offset"
-        );
-        assert_eq!(
-            gep.src_elem_type(&ctx),
-            IntegerType::get(&ctx, 8, Signedness::Signless).into(),
-            "byte addressing must step in i8 units"
-        );
-    }
-
-    /// The capability split, read side: a payload whose storage IS its
-    /// semantic type keeps the address path even for a SHARED borrow. The
-    /// borrow lowers to one GEP into the ORIGINAL enum storage and the read
-    /// to one load through it: no stack spill, no value copy. (Non-canonical
-    /// payloads never get here for shared borrows; the importer punts them
-    /// to the value-copy fallback before an address is formed.)
-    #[test]
-    fn canonical_payload_shared_read_loads_through_gep_without_copy() {
-        use llvm_export::ops::GepIndex;
-        use pliron::builtin::types::FP32Type;
-
-        let mut ctx = make_ctx();
-        let tag: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let f32_ty: TypeHandle = FP32Type::get(&ctx).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "Slot".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout("Occupied".into(), vec![f32_ty], vec![4], vec![4]),
-                EnumVariant::unit("Empty".into()),
-            ],
-            0,
-            8,
-            4,
-        )
-        .into();
-        let slot_map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(
-            slot_map.field_slots,
-            vec![Some(1)],
-            "an f32 payload owns its LLVM slot; storage equals semantic type"
-        );
-
-        // Immutable pointer types model the shared borrow.
-        let enum_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, false).into();
-        let f32_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, f32_ty, false).into();
-        let (module, block) = build_kernel(&mut ctx, vec![enum_ptr_ty], vec![f32_ty]);
-        let base = block.deref(&ctx).get_argument(0);
-        let addr = MirFieldAddrOp::build(&mut ctx, base, f32_ptr_ty, 0).expect("field_addr build");
-        addr.insert_at_back(block, &ctx);
-        let payload_ptr = addr.deref(&ctx).get_result(0);
-
-        let load = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![f32_ty],
-            vec![payload_ptr],
-            vec![],
-            0,
-        );
-        load.insert_at_back(block, &ctx);
-        let loaded = load.deref(&ctx).get_result(0);
-        append_mir_return(&mut ctx, block, vec![loaded]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(
-            count_ops::<llvm::AllocaOp>(&ctx, &body),
-            0,
-            "a canonical payload read must not spill or copy the enum"
-        );
-        let geps = find_all::<llvm::GetElementPtrOp>(&ctx, &body);
-        assert_eq!(geps.len(), 1, "one field_addr lowers to one GEP");
-        let gep = &geps[0];
-        assert_eq!(
-            gep.get_operation().deref(&ctx).get_operand(0),
-            base,
-            "the GEP must address the ORIGINAL enum storage"
-        );
-        assert!(
-            matches!(
-                gep.indices(&ctx).as_slice(),
-                [GepIndex::Constant(0), GepIndex::Constant(1)]
-            ),
-            "an own-slot payload is addressed through its struct slot"
-        );
-        let loads = find_all::<llvm::LoadOp>(&ctx, &body);
-        assert_eq!(
-            loads.len(),
-            1,
-            "the read is a single load through the payload address"
-        );
-        let gep_result = gep.get_operation().deref(&ctx).get_result(0);
-        assert_eq!(
-            loads[0].get_operation().deref(&ctx).get_operand(0),
-            gep_result,
-            "the load must go through the GEP result, not a copy"
-        );
-        assert_eq!(
-            loads[0]
-                .get_operation()
-                .deref(&ctx)
-                .get_result(0)
-                .get_type(&ctx),
-            f32_ty,
-            "the load reads the payload at its semantic type"
-        );
-    }
-
-    #[test]
-    fn later_field_niche_set_writes_exact_carrier_offset() {
-        use llvm_export::ops::GepIndex;
-
-        let mut ctx = make_ctx();
-        let logical: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let wrapper: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Wrapper".into(),
-            vec!["pad".into(), "nz".into()],
-            vec![u32_ty, u32_ty],
-            vec![0, 1],
-            vec![0, 4],
-            8,
-            4,
-        )
-        .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "MaybeWrapper".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![wrapper], vec![0], vec![8]),
-            ],
-            EnumEncoding {
-                tag_offset: 4,
-                total_size: 8,
-                abi_align: 4,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 32,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, true).into();
-        let (module, block) = build_kernel(&mut ctx, vec![ptr_ty], vec![]);
-        let ptr = block.deref(&ctx).get_argument(0);
-        let set = Operation::new(
-            &mut ctx,
-            mir::MirSetDiscriminantOp::get_concrete_op_info(),
-            vec![],
-            vec![ptr],
-            vec![],
-            0,
-        );
-        let set_op = mir::MirSetDiscriminantOp::new(set);
-        set_op.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(0));
-        set_op.set_attr_set_discriminant_enum_ty(
-            &ctx,
-            pliron::builtin::attributes::TypeAttr::new(enum_ty),
-        );
-        set.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        let gep = find_first::<llvm::GetElementPtrOp>(&ctx, &body).unwrap();
-        let indices = gep.indices(&ctx);
-        let [GepIndex::Value(offset)] = indices.as_slice() else {
-            panic!("carrier access must use a byte-offset SSA value");
-        };
-        let constant =
-            Operation::get_op::<llvm::ConstantOp>(offset.defining_op().unwrap(), &ctx).unwrap();
-        assert_eq!(
-            constant
-                .get_value(&ctx)
-                .downcast_ref::<IntegerAttr>()
-                .unwrap()
-                .value()
-                .to_u64(),
-            4
-        );
-    }
-
-    #[test]
-    fn get_niche_discriminant_adds_large_range_start_at_logical_width() {
-        let mut ctx = make_ctx();
-        let logical_ty: TypeHandle = IntegerType::get(&ctx, 16, Signedness::Unsigned).into();
-        let carrier_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let mut variants = (0..300)
-            .map(|index| EnumVariant::unit(format!("V{index}")))
-            .collect::<Vec<_>>();
-        // A valid niche layout stores the carrier inside the untagged
-        // variant's payload. Keep the large logical-variant test realistic
-        // instead of relying on a carrier with no backing field.
-        variants[0] = EnumVariant::new_with_layout("V0".into(), vec![carrier_ty], vec![0], vec![1]);
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "LargeNiche".into(),
-            logical_ty,
-            (0..300).collect(),
-            variants,
-            EnumEncoding {
-                total_size: 1,
-                abi_align: 1,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 8,
-                niche_variant_start: 298,
-                niche_variant_end: 299,
-                untagged_variant: 0,
-                variant_inhabited: {
-                    let mut inhabited = vec![0; 300];
-                    inhabited[0] = 1;
-                    inhabited[298] = 1;
-                    inhabited[299] = 1;
-                    inhabited
-                },
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        let (module, block) = build_kernel(&mut ctx, vec![enum_ty], vec![logical_ty]);
-        let value = block.deref(&ctx).get_argument(0);
-        let get = Operation::new(
-            &mut ctx,
-            mir::MirGetDiscriminantOp::get_concrete_op_info(),
-            vec![logical_ty],
-            vec![value],
-            vec![],
-            0,
-        );
-        get.insert_at_back(block, &ctx);
-        let result = get.deref(&ctx).get_result(0);
-        append_mir_return(&mut ctx, block, vec![result]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(count_ops::<llvm::ZExtOp>(&ctx, &body), 1);
-        let add = find_first::<llvm::AddOp>(&ctx, &body).expect("logical variant add");
-        for operand in add.get_operation().deref(&ctx).operands() {
-            assert_eq!(
-                operand
-                    .get_type(&ctx)
-                    .deref(&ctx)
-                    .downcast_ref::<IntegerType>()
-                    .unwrap()
-                    .width(),
-                16,
-                "variant-index arithmetic must occur at logical width"
-            );
-        }
-    }
-
-    #[test]
-    fn direct_negative_discriminant_read_remains_signed_for_widening() {
-        let mut ctx = make_ctx();
-        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signed).into();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signed).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "Negative".into(),
-            i8_ty,
-            vec![255, 0],
-            vec![EnumVariant::unit("N".into()), EnumVariant::unit("Z".into())],
-            0,
-            1,
-            1,
-        )
-        .into();
-        let (module, block) = build_kernel(&mut ctx, vec![], vec![i32_ty]);
-        let construct = Operation::new(
-            &mut ctx,
-            mir::MirConstructEnumOp::get_concrete_op_info(),
-            vec![enum_ty],
-            vec![],
-            vec![],
-            0,
-        );
-        mir::MirConstructEnumOp::new(construct)
-            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
-        construct.insert_at_back(block, &ctx);
-        let enum_value = construct.deref(&ctx).get_result(0);
-        let get = Operation::new(
-            &mut ctx,
-            mir::MirGetDiscriminantOp::get_concrete_op_info(),
-            vec![i8_ty],
-            vec![enum_value],
-            vec![],
-            0,
-        );
-        get.insert_at_back(block, &ctx);
-        let discriminant = get.deref(&ctx).get_result(0);
-        let cast = Operation::new(
-            &mut ctx,
-            mir::MirCastOp::get_concrete_op_info(),
-            vec![i32_ty],
-            vec![discriminant],
-            vec![],
-            0,
-        );
-        mir::MirCastOp::new(cast).set_attr_cast_kind(&ctx, MirCastKindAttr::IntToInt);
-        cast.insert_at_back(block, &ctx);
-        let widened = cast.deref(&ctx).get_result(0);
-        append_mir_return(&mut ctx, block, vec![widened]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-        let body = kernel_blocks(&ctx, module);
-        assert_eq!(count_ops::<llvm::SExtOp>(&ctx, &body), 1);
-        assert_eq!(count_ops::<llvm::ZExtOp>(&ctx, &body), 0);
-    }
-
-    #[test]
-    fn single_layout_preserves_large_and_negative_declared_discriminants() {
-        for (width, signedness, bits, widened_width, expects_sext) in [
-            (16, Signedness::Unsigned, 1_000, 16, false),
-            (8, Signedness::Signed, 251, 32, true),
-        ] {
-            let mut ctx = make_ctx();
-            let logical: TypeHandle = IntegerType::get(&ctx, width, signedness).into();
-            let destination: TypeHandle = IntegerType::get(&ctx, widened_width, signedness).into();
-            let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-                &mut ctx,
-                "Single".into(),
-                logical,
-                vec![bits],
-                vec![EnumVariant::unit("Only".into())],
-                EnumEncoding {
-                    tag_offset: 0,
-                    total_size: 0,
-                    abi_align: 1,
-                    layout_kind: EnumLayoutKind::Single,
-                    variant_inhabited: vec![1],
-                    ..EnumEncoding::default()
-                },
-            )
-            .into();
-            let (module, block) = build_kernel(&mut ctx, vec![], vec![destination]);
-            let construct = Operation::new(
-                &mut ctx,
-                mir::MirConstructEnumOp::get_concrete_op_info(),
-                vec![enum_ty],
-                vec![],
-                vec![],
-                0,
-            );
-            mir::MirConstructEnumOp::new(construct)
-                .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
-            construct.insert_at_back(block, &ctx);
-            let enum_value = construct.deref(&ctx).get_result(0);
-            let get = Operation::new(
-                &mut ctx,
-                mir::MirGetDiscriminantOp::get_concrete_op_info(),
-                vec![logical],
-                vec![enum_value],
-                vec![],
-                0,
-            );
-            get.insert_at_back(block, &ctx);
-            let discr = get.deref(&ctx).get_result(0);
-            let returned = if widened_width == width {
-                discr
-            } else {
-                let cast = Operation::new(
-                    &mut ctx,
-                    mir::MirCastOp::get_concrete_op_info(),
-                    vec![destination],
-                    vec![discr],
-                    vec![],
-                    0,
-                );
-                mir::MirCastOp::new(cast).set_attr_cast_kind(&ctx, MirCastKindAttr::IntToInt);
-                cast.insert_at_back(block, &ctx);
-                cast.deref(&ctx).get_result(0)
-            };
-            append_mir_return(&mut ctx, block, vec![returned]);
-
-            crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
-            let body = kernel_blocks(&ctx, module);
-            let found_bits = find_all::<llvm::ConstantOp>(&ctx, &body)
-                .iter()
-                .any(|constant| {
-                    constant
-                        .get_value(&ctx)
-                        .downcast_ref::<IntegerAttr>()
-                        .is_some_and(|value| value.value().to_u64() == bits)
-                });
-            assert!(
-                found_bits,
-                "single discriminant {bits} must not be truncated"
-            );
-            assert_eq!(count_ops::<llvm::SExtOp>(&ctx, &body) == 1, expects_sext);
-        }
-    }
-
-    /// The row-width arm of [`resolve_aggregate_slots`]' no-history fallback
-    /// is defensive symmetry: no current lowering path produces a runtime-width
-    /// slice value with an empty conversion history, so no end-to-end pipeline
-    /// test can reach it. This exercises the fallback directly: a value born as
-    /// the lowered `{ ptr, i64, i32 }` row-width shape (a block argument, which
-    /// carries no history) must resolve to identity indexing exactly like the
-    /// two-field `{ ptr, i64 }` fat pointer, and any other unrecognized
-    /// no-history shape must keep failing closed into the refuse-to-guess
-    /// error (issue #128).
-    #[test]
-    fn no_history_fallback_resolves_row_width_slice_shape_and_stays_closed_otherwise() {
-        let mut ctx = make_ctx();
-
-        // The exact struct the type converter lowers a runtime-width
-        // disjoint slice to, built through the same constructor the fallback
-        // uses so the test cannot drift from the lowered shape.
-        let width_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let row_width_ty = crate::convert::types::make_disjoint_slice_struct(&mut ctx, &[width_ty])
-            .expect("building the row-width slice struct must succeed");
-
-        // A three-field control shape that is NOT the row-width slice: i64
-        // where the u32 row-width word belongs.
-        use llvm_export::types::PointerTypeExt;
-        let ptr_ty: TypeHandle = llvm_types::PointerType::get_generic(&mut ctx).into();
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
-        let foreign_ty: TypeHandle = llvm_types::StructType::get_unnamed(
-            &ctx,
-            (
-                vec![ptr_ty, i64_ty, i64_ty],
-                llvm_types::StructLayout::Unpacked,
-            ),
-        )
-        .into();
-
-        let (_module, block) = build_kernel(&mut ctx, vec![row_width_ty, foreign_ty], vec![]);
-        let row_width_value = block.deref(&ctx).get_argument(0);
-        let foreign_value = block.deref(&ctx).get_argument(1);
-
-        // Block arguments have no recorded conversion history at all.
-        let no_history = OperandsInfo::default();
-
-        let resolved = resolve_aggregate_slots(&mut ctx, &no_history, row_width_value)
-            .expect("the row-width slice shape with no history must resolve");
-        assert!(
-            matches!(resolved, AggregateSlots::Identity),
-            "the row-width {{ ptr, i64, u32 }} shape is index-preserving and must map identically"
-        );
-
-        let refused = resolve_aggregate_slots(&mut ctx, &no_history, foreign_value);
-        assert!(
-            refused.is_err(),
-            "a no-history shape that is not a slice fat pointer (with or without \
-             the row-width word) must fail closed"
-        );
-    }
-}
diff --git a/crates/mir-lower/src/convert/ops/aggregate/addressing.rs b/crates/mir-lower/src/convert/ops/aggregate/addressing.rs
new file mode 100644
index 0000000000..e112f93681
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/aggregate/addressing.rs
@@ -0,0 +1,1185 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::common::{anyhow_to_pliron, byte_offset_gep};
+use crate::convert::enum_payload_storage::enum_payload_storage_type;
+use crate::convert::types::{
+    StructLayoutInfo, build_enum_slot_map, build_struct_slot_map, convert_type,
+    llvm_type_size_align, mir_element_stride, mir_type_abi_align,
+};
+use dialect_mir::ops::{MirConstantOp, MirFieldAddrOp};
+use dialect_mir::types::{MirEnumType, MirPtrType, MirStructType, MirTupleType, MirUnionType};
+use llvm_export::ops as llvm;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+
+// ============================================================================
+// MirFieldAddrOp Conversion
+// ============================================================================
+
+/// Convert `mir.field_addr` to `llvm.getelementptr`.
+///
+/// Computes the address of a struct field using GEP. This is needed when
+/// Rust code takes `&mut self.field` — we need the ADDRESS of the field,
+/// not a COPY of its value.
+///
+/// The GEP field index and the struct type it indexes into both come from
+/// [`build_struct_slot_map`], so the index accounts for reordering,
+/// `[N x i8]` padding slots and stripped ZSTs (ZST-ness is decided on the
+/// converted LLVM field type, like the value-level sites).
+///
+/// Taking the address of a ZST field emits a distinct zero-offset `i8` GEP
+/// off the base pointer (a ZST field lives at byte 0 of the struct), the
+/// same idiom the union branch uses. It must NOT forward the base SSA value
+/// itself: a 1:1 `replace_operation_with_values` that aliases the op's
+/// result to an already-existing value records the result's pointee type
+/// (the ZST field's own zero-field type) onto that value's conversion type
+/// history, so a sibling `field_addr` on the same base would later resolve
+/// the base's pointee to the ZST type instead of the struct and fail with
+/// "field_addr index N out of bounds for struct with 0 fields". The
+/// distinct GEP result leaves the base pointer's recorded pointee intact
+/// and carries the field's pointee type on its own result, which is what
+/// nested projections through the field address look up.
+pub(crate) fn convert_field_addr(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    let ptr_operand = op.deref(ctx).get_operand(0);
+
+    let field_addr_op = MirFieldAddrOp::new(op);
+    let field_index = match field_addr_op.get_attr_field_index(ctx) {
+        Some(attr) => attr.0 as usize,
+        None => return pliron::input_err_noloc!("MirFieldAddrOp missing field_index attribute"),
+    };
+
+    let mir_ptr_pointee =
+        match operands_info.lookup_most_recent_of_type::<MirPtrType>(ctx, ptr_operand) {
+            Some(r) => r.pointee,
+            None => {
+                return pliron::input_err_noloc!("MirFieldAddrOp operand must be pointer type");
+            }
+        };
+
+    let union_field_count = mir_ptr_pointee
+        .deref(ctx)
+        .downcast_ref::<MirUnionType>()
+        .map(MirUnionType::field_count);
+    if let Some(field_count) = union_field_count {
+        if field_index >= field_count {
+            return pliron::input_err_noloc!(
+                "field_addr index {} out of bounds for union with {} fields",
+                field_index,
+                field_count
+            );
+        }
+        // Every union field begins at byte zero. Emit an explicit zero-offset
+        // GEP instead of forwarding the base SSA value directly: the distinct
+        // result keeps dialect conversion's pointer-type history unambiguous
+        // for repeated field accesses and for `union.struct_field.inner`.
+        use llvm_export::ops::GepIndex;
+        let i8_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
+        let gep = llvm::GetElementPtrOp::new(ctx, ptr_operand, vec![GepIndex::Constant(0)], i8_ty);
+        rewriter.insert_operation(ctx, gep.get_operation());
+        rewriter.replace_operation(ctx, op, gep.get_operation());
+        return Ok(());
+    }
+
+    // An enum payload field, addressed by its position in the flattened
+    // `all_field_types`. Variants share bytes, so the slot map resolves each
+    // field one of two ways: its own LLVM slot, or, when its bytes are already
+    // held by a differently typed field of another variant, a byte offset into
+    // the enum. Both give the address of the same storage, which is what makes
+    // a write through the returned pointer land in the enum rather than a copy.
+    let enum_name = mir_ptr_pointee
+        .deref(ctx)
+        .downcast_ref::<MirEnumType>()
+        .map(|enum_ty| enum_ty.name().to_string());
+    if let Some(enum_name) = enum_name {
+        let map = build_enum_slot_map(ctx, mir_ptr_pointee).map_err(anyhow_to_pliron)?;
+        let Some(slot_entry) = map.field_slots.get(field_index).copied() else {
+            return pliron::input_err_noloc!(
+                "field_addr index {} out of bounds for enum with {} payload fields",
+                field_index,
+                map.field_slots.len()
+            );
+        };
+
+        // Enum payload bytes hold one CANONICAL storage type that can differ
+        // from the field's semantic type: a bool is physically an i8 byte and
+        // a shared-memory pointer is stored as a generic pointer, with the
+        // value paths (construct/extract) coercing exactly at that boundary.
+        // The address computed here ESCAPES this site: the loads and stores
+        // made through it happen at arbitrary other sites and are typed with
+        // the SEMANTIC type, so no storage coercion can be attached at
+        // address-formation time. Handing the address out anyway would let an
+        // i1 store leave the byte's upper seven bits undefined for the i8 and
+        // niche-tag readers, or write a shared-pointer representation into
+        // bytes every other reader interprets (and, on modern NVVM, sizes) as
+        // a generic pointer. Fail closed instead, the same way the slot map
+        // already rejects bool bytes hidden behind unions.
+        let semantic_ty = map.field_llvm_types[field_index];
+        let storage_ty = enum_payload_storage_type(ctx, semantic_ty).map_err(anyhow_to_pliron)?;
+        if storage_ty != semantic_ty {
+            return pliron::input_err_noloc!(
+                "field_addr: cannot hand out the in-place address of payload field {} of enum `{}`: its bytes use canonical storage type {} while its semantic type is {}, and loads or stores made through an escaped payload address are typed with the semantic type, which the canonical bytes cannot honor; shared reads of such payloads are compiled through a value copy automatically, and a write that stays inside its function is compiled by rebuilding the enum around the new payload; a borrow that escapes into a call keeps no such rewrite and is refused here",
+                field_index,
+                enum_name,
+                storage_ty.deref(ctx).disp(ctx),
+                semantic_ty.deref(ctx).disp(ctx)
+            );
+        }
+
+        use llvm_export::ops::GepIndex;
+        let gep = match slot_entry {
+            Some(slot) => llvm::GetElementPtrOp::new(
+                ctx,
+                ptr_operand,
+                vec![GepIndex::Constant(0), GepIndex::Constant(slot)],
+                map.llvm_struct_ty,
+            ),
+            None => {
+                // No slot of its own: address the bytes directly, off the
+                // ORIGINAL enum pointer, so a write through the result lands
+                // in the enum. A zero-sized field lands at its offset like
+                // any other and simply spans nothing. The offset is always
+                // present: the slot map builds `field_offsets` and
+                // `field_slots` from one walk over the same fields, and the
+                // bounds check above already validated the index.
+                let offset = map.field_offsets[field_index];
+                let offset = u32::try_from(offset).map_err(|_| {
+                    pliron::input_error_noloc!(
+                        "field_addr: payload byte offset {} of enum `{}` exceeds u32",
+                        offset,
+                        enum_name
+                    )
+                })?;
+                let i8_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
+                llvm::GetElementPtrOp::new(
+                    ctx,
+                    ptr_operand,
+                    vec![GepIndex::Constant(offset)],
+                    i8_ty,
+                )
+            }
+        };
+        rewriter.insert_operation(ctx, gep.get_operation());
+        rewriter.replace_operation(ctx, op, gep.get_operation());
+        return Ok(());
+    }
+
+    // Carried alongside the layout so the field address can record what it
+    // proves about its own alignment; see `stamp_field_address_alignment`.
+    let aggregate_abi_align;
+    let layout = {
+        let pointee_ref = mir_ptr_pointee.deref(ctx);
+        if let Some(struct_ty) = pointee_ref.downcast_ref::<MirStructType>() {
+            aggregate_abi_align = struct_ty.abi_align;
+            StructLayoutInfo::of_struct(struct_ty)
+        } else if let Some(tuple_ty) = pointee_ref.downcast_ref::<MirTupleType>() {
+            aggregate_abi_align = tuple_ty.abi_align();
+            StructLayoutInfo::of_tuple(tuple_ty)
+        } else {
+            return pliron::input_err_noloc!(
+                "MirFieldAddrOp pointer must point to a struct, tuple, union or enum type, got {}",
+                mir_ptr_pointee.deref(ctx).disp(ctx)
+            );
+        }
+    };
+
+    let map = build_struct_slot_map(ctx, &layout).map_err(anyhow_to_pliron)?;
+
+    let slot = match map.decl_to_llvm.get(field_index) {
+        Some(Some(slot)) => *slot,
+        Some(None) => {
+            // ZST field: it has no storage; the struct address stands in for
+            // the field address. Emit an explicit zero-offset GEP instead of
+            // forwarding the base SSA value directly (mirrors the union branch
+            // above): the distinct result keeps dialect conversion's pointer-type
+            // history unambiguous for repeated field accesses off the same base
+            // pointer. Forwarding the base value here type-puns it to the field's
+            // pointee, corrupting the base pointer's recorded type so a sibling
+            // field_addr on the same base later resolves to the wrong (0-field)
+            // pointee -- the "field_addr index N out of bounds for struct with 0
+            // fields" failure on a struct with >= 2 ZST fields (e.g. a closure
+            // that captures other ZST closures, like iter map_fold).
+            use llvm_export::ops::GepIndex;
+            let i8_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
+            let gep =
+                llvm::GetElementPtrOp::new(ctx, ptr_operand, vec![GepIndex::Constant(0)], i8_ty);
+            rewriter.insert_operation(ctx, gep.get_operation());
+            rewriter.replace_operation(ctx, op, gep.get_operation());
+            return Ok(());
+        }
+        None => {
+            return pliron::input_err_noloc!(
+                "field_addr index {} out of bounds for struct with {} fields",
+                field_index,
+                map.decl_to_llvm.len()
+            );
+        }
+    };
+
+    let rustc_offset = layout.field_offsets.get(field_index).copied();
+
+    // Preserve the #859 address-path contract independently of the value
+    // representation. `build_struct_slot_map` retains the offsets the same
+    // fields would have under natural LLVM layout; when those differ from
+    // rustc's recorded offsets, keep using the original aggregate pointer plus
+    // a byte GEP. The semantic value type may now be an LLVM packed struct, but
+    // changing this established field-address path is outside this change.
+    if let Some(expected_offset) = rustc_offset {
+        let actual_offset = map
+            .natural_slot_offsets
+            .as_ref()
+            .and_then(|offsets| offsets.get(slot as usize).copied())
+            .ok_or_else(|| {
+                pliron::input_error_noloc!(
+                    "field_addr: cannot determine LLVM byte offset of slot {} for field {}",
+                    slot,
+                    field_index
+                )
+            })?;
+        if map.layout_diverges && actual_offset != expected_offset {
+            let field_ptr = byte_offset_gep(ctx, rewriter, ptr_operand, expected_offset);
+            let gep = field_ptr
+                .defining_op()
+                .expect("byte_offset_gep always returns a GEP result");
+            stamp_field_address_alignment(ctx, gep, aggregate_abi_align, Some(expected_offset));
+            rewriter.replace_operation(ctx, op, gep);
+            return Ok(());
+        }
+    }
+
+    use llvm_export::ops::GepIndex;
+    let gep_indices = vec![GepIndex::Constant(0), GepIndex::Constant(slot)];
+
+    let gep_op = llvm::GetElementPtrOp::new(ctx, ptr_operand, gep_indices, map.llvm_struct_ty);
+    rewriter.insert_operation(ctx, gep_op.get_operation());
+    stamp_field_address_alignment(
+        ctx,
+        gep_op.get_operation(),
+        aggregate_abi_align,
+        rustc_offset,
+    );
+    rewriter.replace_operation(ctx, op, gep_op.get_operation());
+
+    Ok(())
+}
+
+/// Record on a field address what its alignment provably is.
+///
+/// A load reads its alignment from its own result type, and a scalar records
+/// none -- so `p.x` on an `#[repr(C, align(8))]` struct would export with LLVM's
+/// default `align 4`, dropping the guarantee rustc gave the aggregate. That is
+/// what stops LoadStoreVectorizer from fusing two adjacent field reads into one
+/// wide access; a whole-element copy of the same struct already vectorizes,
+/// because there the load's result type *is* the aggregate.
+///
+/// The aggregate is aligned to `abi_align`, so its field at byte `offset` is
+/// aligned to `gcd(abi_align, offset)`, and to `abi_align` itself at offset
+/// zero. Both numbers are rustc's own layout, so this claims nothing the source
+/// did not already guarantee.
+///
+/// Stamps nothing when the aggregate records no alignment (`abi_align == 0`,
+/// which also stands for "layout unknown") or the field has no recorded offset.
+/// A wrong alignment here is a miscompile, so every uncertain case declines and
+/// leaves the previous, weaker-but-sound behaviour.
+fn stamp_field_address_alignment(
+    ctx: &mut Context,
+    gep: Ptr<Operation>,
+    abi_align: u64,
+    field_offset: Option<u64>,
+) {
+    const fn gcd(a: u64, b: u64) -> u64 {
+        if b == 0 { a } else { gcd(b, a % b) }
+    }
+
+    if abi_align == 0 {
+        return;
+    }
+    let Some(offset) = field_offset else {
+        return;
+    };
+    let provable = if offset == 0 {
+        abi_align
+    } else {
+        gcd(abi_align, offset)
+    };
+    // Every rustc layout has a power-of-two `abi_align`, but dialect-mir only
+    // verifier-enforces that for unions and enums; a malformed hand-built
+    // struct or tuple layout could reach here with e.g. 12, and a
+    // non-power-of-two `align N` is invalid LLVM IR that llc rejects.
+    if !provable.is_power_of_two() {
+        return;
+    }
+    if let Ok(align) = u32::try_from(provable) {
+        llvm_export::ops::set_address_alignment(ctx, gep, align);
+    }
+}
+
+// ============================================================================
+// MirArrayElementAddrOp Conversion
+// ============================================================================
+
+/// Convert `mir.array_element_addr` to `llvm.getelementptr`.
+///
+/// ```text
+/// &arr[i]  ──►  getelementptr T, ptr %arr_ptr, i64 %i
+/// ```
+///
+/// - The element type `T` comes from the op's OWN result type
+///   (`mir.ptr<T>`), which the dialect verifier ties to the operand
+///   array's element type. Same address as the old two-index
+///   `[N x T]` GEP, minus the dead `[N x T]` base.
+/// - Operand type history is not usable here: a kind-only `mir.cast`
+///   lowers to a plain value forwarding, history does not follow that
+///   edge, and a stale hit would stride by the wrong element size.
+pub(crate) fn convert_array_element_addr(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let loc = op.deref(ctx).loc();
+    let arr_ptr = op.deref(ctx).get_operand(0);
+    let index = op.deref(ctx).get_operand(1);
+
+    let result_ty = op.deref(ctx).get_result(0).get_type(ctx);
+    let element_ty = result_ty
+        .deref(ctx)
+        .downcast_ref::<MirPtrType>()
+        .map(|mir_ptr| mir_ptr.pointee)
+        .ok_or_else(|| {
+            pliron::input_error!(
+                loc.clone(),
+                "mir.array_element_addr result must be a MIR pointer type; \
+                 element sizing has no fact to derive from"
+            )
+        })?;
+
+    let llvm_element_ty = convert_type(ctx, element_ty).map_err(anyhow_to_pliron)?;
+
+    // The typed GEP strides by the LLVM allocation size of the element type.
+    // Keep the rustc-stride comparison as a fail-closed backstop for any
+    // element representation whose LLVM allocation size differs.
+    {
+        let rustc_stride = mir_element_stride(ctx, element_ty);
+        let llvm_size = llvm_type_size_align(ctx, llvm_element_ty).map(|(size, _)| size);
+        if let (Some(stride), Some(llvm_size)) = (rustc_stride, llvm_size)
+            && stride != llvm_size
+        {
+            return pliron::input_err_noloc!(
+                "addressing elements of an array whose LLVM allocation size differs from \
+                 rustc's stored stride is not supported: rustc strides by {} bytes but \
+                 the LLVM element type occupies {}",
+                stride,
+                llvm_size
+            );
+        }
+    }
+
+    use llvm_export::ops::GepIndex;
+    let gep_indices = vec![GepIndex::Value(index)];
+
+    let element_align = element_address_provable_alignment(ctx, arr_ptr, element_ty, index);
+
+    let gep_op = llvm::GetElementPtrOp::new(ctx, arr_ptr, gep_indices, llvm_element_ty);
+    rewriter.insert_operation(ctx, gep_op.get_operation());
+    if let Some(align) = element_align {
+        llvm_export::ops::set_address_alignment(ctx, gep_op.get_operation(), align);
+    }
+    rewriter.replace_operation(ctx, op, gep_op.get_operation());
+
+    Ok(())
+}
+
+/// Alignment an array-element address provably has, in bytes.
+///
+/// The field path records this already ([`stamp_field_address_alignment`]), but
+/// an element address recorded nothing, so `lanes[0] + lanes[1]` on an
+/// `#[repr(C, align(8))]` `[f32; 2]` still exported two `align 4` loads and
+/// LoadStoreVectorizer refused to fuse them. Reading the same element into a
+/// local first happens to work, because SROA then loads the whole aggregate and
+/// the alignment comes from its type — so the cost depended on whether the
+/// source copied the element or read through it.
+///
+/// Two facts combine. The element's `abi_align` equals the array's (a Rust
+/// array aligns to its element), and whatever the *base pointer* already
+/// proved is stronger when the array is itself a field of an over-aligned
+/// aggregate: `&table[i].lanes` carries the outer struct's alignment, which
+/// the element type alone does not know. Element `i` then sits at byte
+/// `i * stride`, so it is aligned to `gcd(base, i * stride)`, and to `base`
+/// itself at index zero. A runtime index can land on any element, so it gets
+/// `gcd(base, stride)`, which every element satisfies.
+///
+/// Answers `None`, leaving the previous behaviour, when neither the base nor
+/// the element type records an alignment, or the stride is unknown. As on the
+/// field path, a wrong answer here is a miscompile, so every uncertain case
+/// declines rather than guesses. That is why the stride comes from
+/// [`mir_element_stride`], which is exact or `None`: an LLVM-level size
+/// approximation would guess 8 for a MIR aggregate element it does not
+/// model, and e.g. `[[f32; 3]; 4]` under an align-8 base would then claim
+/// align 8 on element addresses that are only 4-aligned.
+fn element_address_provable_alignment(
+    ctx: &Context,
+    arr_ptr: Value,
+    element_ty: TypeHandle,
+    index: Value,
+) -> Option<u32> {
+    const fn gcd(a: u64, b: u64) -> u64 {
+        if b == 0 { a } else { gcd(b, a % b) }
+    }
+
+    // What the base address already proved, else what the element type
+    // states (identical to the array's own alignment).
+    let base_align = arr_ptr
+        .defining_op()
+        .and_then(|def| llvm_export::ops::address_alignment(ctx, def))
+        .map(u64::from)
+        .or_else(|| mir_type_abi_align(ctx, element_ty))?;
+    if base_align == 0 {
+        return None;
+    }
+
+    let stride = mir_element_stride(ctx, element_ty)?;
+    if stride == 0 {
+        return None;
+    }
+
+    let provable = match constant_index_value(ctx, index) {
+        Some(0) => base_align,
+        Some(i) => gcd(base_align, i.checked_mul(stride)?),
+        // Any element is reachable, so claim only what every stride preserves.
+        None => gcd(base_align, stride),
+    };
+
+    // Same guard as the field path: dialect-mir does not verifier-enforce a
+    // power-of-two `abi_align` for every aggregate, and a non-power-of-two
+    // `align N` is invalid LLVM IR that llc rejects.
+    if !provable.is_power_of_two() {
+        return None;
+    }
+    u32::try_from(provable).ok()
+}
+
+/// The constant an index operand holds, if it is one.
+///
+/// `APInt::to_u64` truncates wider values, so a >64-bit constant could be
+/// misread as a small offset multiplier. Fail closed on such widths, as
+/// `integer_constant_u64` in the extract-element fast path does.
+fn constant_index_value(ctx: &Context, index: Value) -> Option<u64> {
+    let defining_op = index.defining_op()?;
+    if let Some(constant) = Operation::get_op::<MirConstantOp>(defining_op, ctx) {
+        let value = constant.get_attr_value(ctx)?.value();
+        return (value.bw() <= 64).then(|| value.to_u64());
+    }
+    let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, ctx)?;
+    let attribute = constant.get_value(ctx);
+    let integer = attribute.downcast_ref::<pliron::builtin::attributes::IntegerAttr>()?;
+    let value = integer.value();
+    (value.bw() <= 64).then(|| value.to_u64())
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production minting lives in mir-importer's facts.rs.
+#[allow(clippy::disallowed_methods)]
+mod tests {
+    use super::*;
+    use crate::convert::ops::test_util::*;
+
+    use dialect_mir::ops as mir;
+    use dialect_mir::types::{
+        EnumCarrierKind, EnumEncoding, EnumLayoutKind, EnumVariant, MirArrayType, MirPtrType,
+        MirStructType, MirTupleType,
+    };
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::common_traits::Verify;
+
+    use super::super::test_support::*;
+
+    fn byte_gep_constant_offset(ctx: &Context, gep: &llvm::GetElementPtrOp) -> Option<u64> {
+        use llvm_export::ops::GepIndex;
+
+        let indices = gep.indices(ctx);
+        let [GepIndex::Value(offset)] = indices.as_slice() else {
+            return None;
+        };
+        let defining_op = offset.defining_op()?;
+        let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, ctx)?;
+        let attribute = constant.get_value(ctx);
+        attribute
+            .downcast_ref::<IntegerAttr>()
+            .map(|integer| integer.value().to_u64())
+    }
+
+    fn assert_byte_addressed_field(
+        ctx: &Context,
+        module: Ptr<Operation>,
+        expected_offset: u64,
+        expected_alignment: u32,
+    ) {
+        let body = kernel_blocks(ctx, module);
+        let geps = find_all::<llvm::GetElementPtrOp>(ctx, &body);
+        assert_eq!(geps.len(), 1, "one field_addr must lower to one GEP");
+
+        let gep = &geps[0];
+        assert_eq!(
+            gep.src_elem_type(ctx),
+            IntegerType::get(ctx, 8, Signedness::Signless).into(),
+            "a layout-mismatched field must be addressed in byte units"
+        );
+        assert_eq!(
+            byte_gep_constant_offset(ctx, gep),
+            Some(expected_offset),
+            "the byte GEP must use rustc's exact field offset"
+        );
+        assert_eq!(
+            llvm_export::ops::address_alignment(ctx, gep.get_operation()),
+            Some(expected_alignment),
+            "the byte GEP must retain the alignment proved by rustc's aggregate layout"
+        );
+    }
+
+    /// Sibling ZST field addresses off one base pointer must each lower to
+    /// their own zero-offset `i8` GEP, never to the base SSA value itself.
+    /// Forwarding the base (the pre-fix behavior) recorded the first field's
+    /// zero-field pointee type onto the base pointer's conversion history, so
+    /// the second `field_addr` resolved the base's pointee to "struct with 0
+    /// fields" and lowering aborted. This is the `iter().map(..).sum()` shape:
+    /// a composed closure holding two captureless (zero-sized) closures.
+    #[test]
+    fn sibling_zst_field_addrs_lower_to_distinct_zero_offset_geps() {
+        use llvm_export::ops::GepIndex;
+
+        let mut ctx = make_ctx();
+
+        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
+        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
+        let zst_f = empty_struct_ty(&mut ctx, "MapClosure");
+        let zst_g = empty_struct_ty(&mut ctx, "SumClosure");
+
+        // struct Composed { f: MapClosure (ZST), g: SumClosure (ZST), acc: i64 }
+        let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Composed".to_string(),
+            vec!["f".to_string(), "g".to_string(), "acc".to_string()],
+            vec![zst_f, zst_g, i64_ty],
+            vec![0, 1, 2],
+            vec![0, 0, 0],
+            8,
+            8,
+        )
+        .into();
+
+        let base_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, struct_ty, true).into();
+        // Each field_addr result records the field's own pointee type; for the
+        // ZST fields that zero-field pointee is exactly what poisoned the base
+        // pointer's history when the result aliased the base.
+        let f_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, zst_f, true).into();
+        let g_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, zst_g, true).into();
+        let acc_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, i64_ty, true).into();
+
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![base_ptr_ty], vec![]);
+        let base = block.deref(&ctx).get_argument(0);
+
+        for (field_index, result_ty) in [(0u32, f_ptr_ty), (1, g_ptr_ty), (2, acc_ptr_ty)] {
+            let op = MirFieldAddrOp::build(&mut ctx, base, result_ty, field_index)
+                .expect("field_addr build");
+            op.insert_at_back(block, &ctx);
+        }
+        append_mir_return(&mut ctx, block, vec![]);
+
+        // Pre-fix this failed with "field_addr index 1 out of bounds for
+        // struct with 0 fields" on the second (sibling) ZST field_addr.
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+        let geps = find_all::<llvm::GetElementPtrOp>(&ctx, &body);
+        assert_eq!(geps.len(), 3, "each field_addr must lower to its own GEP");
+        assert!(
+            geps.iter().all(|gep| gep.verify(&ctx).is_ok()),
+            "every field-address GEP must satisfy LLVM dialect verification"
+        );
+
+        let zst_geps: Vec<_> = geps
+            .iter()
+            .filter(|gep| {
+                gep.src_elem_type(&ctx) == i8_ty
+                    && matches!(gep.indices(&ctx).as_slice(), [GepIndex::Constant(0)])
+            })
+            .collect();
+        assert_eq!(
+            zst_geps.len(),
+            2,
+            "both ZST field addresses must lower to zero-offset i8 GEPs"
+        );
+
+        let gep_base = |gep: &llvm::GetElementPtrOp| gep.get_operation().deref(&ctx).get_operand(0);
+        let gep_result =
+            |gep: &llvm::GetElementPtrOp| gep.get_operation().deref(&ctx).get_result(0);
+        assert_eq!(
+            gep_base(zst_geps[0]),
+            gep_base(zst_geps[1]),
+            "both ZST field addresses must be taken off the same base pointer"
+        );
+        assert_ne!(
+            gep_result(zst_geps[0]),
+            gep_base(zst_geps[0]),
+            "a ZST field address must be a value distinct from the base pointer"
+        );
+        assert_ne!(
+            gep_result(zst_geps[1]),
+            gep_base(zst_geps[1]),
+            "a ZST field address must be a value distinct from the base pointer"
+        );
+        assert_ne!(
+            gep_result(zst_geps[0]),
+            gep_result(zst_geps[1]),
+            "each sibling ZST field address must get its own GEP result"
+        );
+
+        // The non-ZST sibling still resolves the base's pointee to the struct
+        // (slot 0 holds `acc`): the base pointer's type history stayed intact.
+        let acc_geps: Vec<_> = geps
+            .iter()
+            .filter(|gep| {
+                matches!(
+                    gep.indices(&ctx).as_slice(),
+                    [GepIndex::Constant(0), GepIndex::Constant(0)]
+                )
+            })
+            .collect();
+        assert_eq!(
+            acc_geps.len(),
+            1,
+            "the non-ZST field address must index the struct's layout slot"
+        );
+    }
+
+    /// `mir.field_addr` on a TUPLE pointee (the `#693` shape: `let (a, b) =
+    /// TABLE[i];`) must resolve the GEP index through the tuple's memory-order
+    /// layout, exactly like the struct path above, not through the
+    /// declaration index directly.
+    ///
+    /// `(u8, u32)` is rustc's own layout for this pair: the `u32` field is
+    /// placed FIRST in memory for alignment, so declaration field 0 (`u8`,
+    /// `.0`) lives at memory slot 1 and declaration field 1 (`u32`, `.1`)
+    /// lives at memory slot 0. A GEP index equal to the declaration index
+    /// would silently address the WRONG field's bytes.
+    #[test]
+    fn field_addr_tuple_pointee_resolves_memory_order_gep_index() {
+        use llvm_export::ops::GepIndex;
+
+        let mut ctx = make_ctx();
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+
+        // decl order [u8, u32]; memory order [u32, u8] (mem_to_decl = [1, 0]).
+        let tuple_ty: TypeHandle = MirTupleType::get_with_layout(
+            &mut ctx,
+            vec![u8_ty, u32_ty],
+            vec![1, 0],
+            vec![4, 0],
+            8,
+            4,
+        )
+        .into();
+
+        let tuple_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, tuple_ty, false).into();
+        let u8_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
+        let u32_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![tuple_ptr_ty], vec![]);
+        let base = block.deref(&ctx).get_argument(0);
+
+        // Declaration field 0 (`.0`, u8) first, then declaration field 1
+        // (`.1`, u32) -- source order, not memory order.
+        for (field_index, result_ty) in [(0u32, u8_ptr_ty), (1, u32_ptr_ty)] {
+            let op = MirFieldAddrOp::build(&mut ctx, base, result_ty, field_index)
+                .expect("field_addr build");
+            op.insert_at_back(block, &ctx);
+        }
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+        let geps = find_all::<llvm::GetElementPtrOp>(&ctx, &body);
+        assert_eq!(geps.len(), 2, "each field_addr must lower to its own GEP");
+        assert!(
+            geps.iter().all(|gep| gep.verify(&ctx).is_ok()),
+            "every field-address GEP must satisfy LLVM dialect verification"
+        );
+
+        // `.0` (u8, declared first) must land at MEMORY slot 1.
+        let field0_geps: Vec<_> = geps
+            .iter()
+            .filter(|gep| {
+                matches!(
+                    gep.indices(&ctx).as_slice(),
+                    [GepIndex::Constant(0), GepIndex::Constant(1)]
+                )
+            })
+            .collect();
+        assert_eq!(
+            field0_geps.len(),
+            1,
+            "declaration field 0 (u8) must resolve to its memory slot 1, not slot 0"
+        );
+
+        // `.1` (u32, declared second) must land at MEMORY slot 0.
+        let field1_geps: Vec<_> = geps
+            .iter()
+            .filter(|gep| {
+                matches!(
+                    gep.indices(&ctx).as_slice(),
+                    [GepIndex::Constant(0), GepIndex::Constant(0)]
+                )
+            })
+            .collect();
+        assert_eq!(
+            field1_geps.len(),
+            1,
+            "declaration field 1 (u32) must resolve to its memory slot 0, not slot 1"
+        );
+    }
+
+    /// A `#[repr(C, packed)]`-style layout can place a naturally aligned
+    /// scalar at an offset LLVM's ordinary struct layout cannot express. The
+    /// field address must therefore use rustc's byte offset rather than a
+    /// typed struct GEP that would silently land at byte 4.
+    #[test]
+    fn packed_field_addr_uses_rustc_byte_offset_and_alignment_one() {
+        let mut ctx = make_ctx();
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Packed".into(),
+            vec!["tag".into(), "value".into()],
+            vec![u8_ty, u32_ty],
+            vec![0, 1],
+            vec![0, 1],
+            5,
+            1,
+        )
+        .into();
+
+        let base_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, packed_ty, false).into();
+        let field_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let (module, block) = build_kernel(&mut ctx, vec![base_ptr_ty], vec![]);
+        let base = block.deref(&ctx).get_argument(0);
+
+        let field_addr =
+            MirFieldAddrOp::build(&mut ctx, base, field_ptr_ty, 1).expect("field_addr build");
+        field_addr.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        assert_byte_addressed_field(&ctx, module, 1, 1);
+    }
+
+    /// `repr(packed(2))` is not equivalent to byte alignment: the same u32
+    /// field is allowed to sit at byte 2 and the address still proves align 2.
+    #[test]
+    fn packed_two_field_addr_uses_rustc_byte_offset_and_alignment_two() {
+        let mut ctx = make_ctx();
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Packed2".into(),
+            vec!["tag".into(), "value".into()],
+            vec![u8_ty, u32_ty],
+            vec![0, 1],
+            vec![0, 2],
+            6,
+            2,
+        )
+        .into();
+
+        let base_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, packed_ty, false).into();
+        let field_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let (module, block) = build_kernel(&mut ctx, vec![base_ptr_ty], vec![]);
+        let base = block.deref(&ctx).get_argument(0);
+
+        let field_addr =
+            MirFieldAddrOp::build(&mut ctx, base, field_ptr_ty, 1).expect("field_addr build");
+        field_addr.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        assert_byte_addressed_field(&ctx, module, 2, 2);
+    }
+
+    /// The decision must compare physical offsets, not merely the selected
+    /// field's own alignment. In `{ u8, u32, u8 }` the final u8 is naturally
+    /// byte-aligned, but LLVM has already shifted it because the packed u32
+    /// before it was placed at byte 4 instead of byte 1.
+    #[test]
+    fn packed_trailing_byte_field_uses_accumulated_rustc_offset() {
+        let mut ctx = make_ctx();
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedTrailing".into(),
+            vec!["head".into(), "value".into(), "tail".into()],
+            vec![u8_ty, u32_ty, u8_ty],
+            vec![0, 1, 2],
+            vec![0, 1, 5],
+            6,
+            1,
+        )
+        .into();
+
+        let base_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, packed_ty, false).into();
+        let field_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
+        let (module, block) = build_kernel(&mut ctx, vec![base_ptr_ty], vec![]);
+        let base = block.deref(&ctx).get_argument(0);
+
+        let field_addr =
+            MirFieldAddrOp::build(&mut ctx, base, field_ptr_ty, 2).expect("field_addr build");
+        field_addr.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        assert_byte_addressed_field(&ctx, module, 5, 1);
+    }
+
+    /// Packed LLVM element types carry the same allocation size as rustc, so
+    /// typed array GEPs now stride by the correct packed byte count.
+    #[test]
+    fn packed_array_element_addressing_uses_packed_stride() {
+        use dialect_mir::ops::MirArrayElementAddrOp;
+
+        let mut ctx = make_ctx();
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let u64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Packed".into(),
+            vec!["tag".into(), "value".into()],
+            vec![u8_ty, u32_ty],
+            vec![0, 1],
+            vec![0, 1],
+            5,
+            1,
+        )
+        .into();
+        let array_ty: TypeHandle = MirArrayType::get(&mut ctx, packed_ty, 4).into();
+        let base_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, array_ty, false).into();
+        let elem_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, packed_ty, false).into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![base_ptr_ty, u64_ty], vec![]);
+        let base = block.deref(&ctx).get_argument(0);
+        let index = block.deref(&ctx).get_argument(1);
+
+        let elem_addr = Operation::new(
+            &mut ctx,
+            MirArrayElementAddrOp::get_concrete_op_info(),
+            vec![elem_ptr_ty],
+            vec![base, index],
+            vec![],
+            0,
+        );
+        elem_addr.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module)
+            .expect("packed element addressing must use the packed LLVM stride");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(
+            count_ops::<llvm::GetElementPtrOp>(&ctx, &body),
+            1,
+            "packed array element addressing should lower to one typed GEP"
+        );
+    }
+
+    /// Taking the in-place address of a bool payload must fail loudly: the
+    /// payload's canonical storage is an i8 byte, and a semantic i1 store
+    /// through the escaped address would leave that byte's upper seven bits
+    /// undefined for every i8 reader (including a niche tag sharing them).
+    #[test]
+    fn bool_payload_field_addr_fails_closed() {
+        let mut ctx = make_ctx();
+        let tag: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let bool_ty: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "DirectBool".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::new_with_layout("A".into(), vec![bool_ty], vec![4], vec![1]),
+                EnumVariant::unit("B".into()),
+            ],
+            0,
+            8,
+            4,
+        )
+        .into();
+        let enum_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, true).into();
+        let bool_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, bool_ty, true).into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![enum_ptr_ty], vec![]);
+        let base = block.deref(&ctx).get_argument(0);
+        let op = MirFieldAddrOp::build(&mut ctx, base, bool_ptr_ty, 0).expect("field_addr build");
+        op.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        let err = crate::lower_mir_to_llvm(&mut ctx, module)
+            .expect_err("addressing a bool enum payload in place must fail to lower");
+        assert!(
+            err.err.to_string().contains("canonical storage type"),
+            "unexpected error: {}",
+            err.err
+        );
+    }
+
+    /// Same gate for the slot arm: a shared-memory pointer payload is stored
+    /// as a GENERIC pointer (its slot is typed `ptr`), so an in-place address
+    /// would let a semantic `ptr addrspace(3)` store write a representation
+    /// every other reader interprets as a generic pointer.
+    #[test]
+    fn shared_pointer_payload_field_addr_fails_closed() {
+        let mut ctx = make_ctx();
+        let logical: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
+        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, true).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "OptionShared".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![shared], vec![0], vec![8]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 8,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                carrier_address_space: llvm_types::address_space::GENERIC,
+                niche_start: 0,
+                niche_variant_start: 0,
+                niche_variant_end: 0,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        let enum_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, true).into();
+        let payload_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, shared, true).into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![enum_ptr_ty], vec![]);
+        let base = block.deref(&ctx).get_argument(0);
+        let op =
+            MirFieldAddrOp::build(&mut ctx, base, payload_ptr_ty, 0).expect("field_addr build");
+        op.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        let err = crate::lower_mir_to_llvm(&mut ctx, module)
+            .expect_err("addressing a shared-pointer enum payload in place must fail to lower");
+        assert!(
+            err.err.to_string().contains("canonical storage type"),
+            "unexpected error: {}",
+            err.err
+        );
+    }
+
+    /// A payload with no slot of its own is addressed at its byte offset off
+    /// the ORIGINAL enum pointer: no stack spill is introduced, so a write
+    /// through the result lands in the enum rather than in a copy.
+    #[test]
+    fn slotless_payload_field_addr_geps_original_storage_at_byte_offset() {
+        use llvm_export::ops::GepIndex;
+        use pliron::builtin::types::FP32Type;
+
+        let mut ctx = make_ctx();
+        let tag: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let f32_ty: TypeHandle = FP32Type::get(&ctx).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "Either".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::new_with_layout("Real".into(), vec![f32_ty], vec![4], vec![4]),
+                EnumVariant::new_with_layout("Bits".into(), vec![u32_ty], vec![4], vec![4]),
+            ],
+            0,
+            8,
+            4,
+        )
+        .into();
+        let slot_map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(
+            slot_map.field_slots,
+            vec![Some(1), None],
+            "Real's f32 claims byte 4 first; Bits shares those bytes slotless"
+        );
+
+        let enum_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, true).into();
+        let u32_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, true).into();
+        let (module, block) = build_kernel(&mut ctx, vec![enum_ptr_ty], vec![]);
+        let base = block.deref(&ctx).get_argument(0);
+        let op = MirFieldAddrOp::build(&mut ctx, base, u32_ptr_ty, 1).expect("field_addr build");
+        op.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(
+            count_ops::<llvm::AllocaOp>(&ctx, &body),
+            0,
+            "an in-place payload address must not spill the enum to a stack copy"
+        );
+        let geps = find_all::<llvm::GetElementPtrOp>(&ctx, &body);
+        assert_eq!(geps.len(), 1, "one field_addr lowers to one GEP");
+        let gep = &geps[0];
+        // The MIR entry block and its arguments are the ORIGINALS (moved by
+        // `inline_region`), so the enum pointer argument keeps its identity
+        // through lowering and the GEP must be based directly on it.
+        assert_eq!(
+            gep.get_operation().deref(&ctx).get_operand(0),
+            base,
+            "the byte-offset GEP must address the ORIGINAL enum storage"
+        );
+        assert!(
+            matches!(gep.indices(&ctx).as_slice(), [GepIndex::Constant(4)]),
+            "the slotless payload must be addressed at its rustc byte offset"
+        );
+        assert_eq!(
+            gep.src_elem_type(&ctx),
+            IntegerType::get(&ctx, 8, Signedness::Signless).into(),
+            "byte addressing must step in i8 units"
+        );
+    }
+
+    /// The capability split, read side: a payload whose storage IS its
+    /// semantic type keeps the address path even for a SHARED borrow. The
+    /// borrow lowers to one GEP into the ORIGINAL enum storage and the read
+    /// to one load through it: no stack spill, no value copy. (Non-canonical
+    /// payloads never get here for shared borrows; the importer punts them
+    /// to the value-copy fallback before an address is formed.)
+    #[test]
+    fn canonical_payload_shared_read_loads_through_gep_without_copy() {
+        use llvm_export::ops::GepIndex;
+        use pliron::builtin::types::FP32Type;
+
+        let mut ctx = make_ctx();
+        let tag: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let f32_ty: TypeHandle = FP32Type::get(&ctx).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "Slot".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::new_with_layout("Occupied".into(), vec![f32_ty], vec![4], vec![4]),
+                EnumVariant::unit("Empty".into()),
+            ],
+            0,
+            8,
+            4,
+        )
+        .into();
+        let slot_map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(
+            slot_map.field_slots,
+            vec![Some(1)],
+            "an f32 payload owns its LLVM slot; storage equals semantic type"
+        );
+
+        // Immutable pointer types model the shared borrow.
+        let enum_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, false).into();
+        let f32_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, f32_ty, false).into();
+        let (module, block) = build_kernel(&mut ctx, vec![enum_ptr_ty], vec![f32_ty]);
+        let base = block.deref(&ctx).get_argument(0);
+        let addr = MirFieldAddrOp::build(&mut ctx, base, f32_ptr_ty, 0).expect("field_addr build");
+        addr.insert_at_back(block, &ctx);
+        let payload_ptr = addr.deref(&ctx).get_result(0);
+
+        let load = Operation::new(
+            &mut ctx,
+            mir::MirLoadOp::get_concrete_op_info(),
+            vec![f32_ty],
+            vec![payload_ptr],
+            vec![],
+            0,
+        );
+        load.insert_at_back(block, &ctx);
+        let loaded = load.deref(&ctx).get_result(0);
+        append_mir_return(&mut ctx, block, vec![loaded]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(
+            count_ops::<llvm::AllocaOp>(&ctx, &body),
+            0,
+            "a canonical payload read must not spill or copy the enum"
+        );
+        let geps = find_all::<llvm::GetElementPtrOp>(&ctx, &body);
+        assert_eq!(geps.len(), 1, "one field_addr lowers to one GEP");
+        let gep = &geps[0];
+        assert_eq!(
+            gep.get_operation().deref(&ctx).get_operand(0),
+            base,
+            "the GEP must address the ORIGINAL enum storage"
+        );
+        assert!(
+            matches!(
+                gep.indices(&ctx).as_slice(),
+                [GepIndex::Constant(0), GepIndex::Constant(1)]
+            ),
+            "an own-slot payload is addressed through its struct slot"
+        );
+        let loads = find_all::<llvm::LoadOp>(&ctx, &body);
+        assert_eq!(
+            loads.len(),
+            1,
+            "the read is a single load through the payload address"
+        );
+        let gep_result = gep.get_operation().deref(&ctx).get_result(0);
+        assert_eq!(
+            loads[0].get_operation().deref(&ctx).get_operand(0),
+            gep_result,
+            "the load must go through the GEP result, not a copy"
+        );
+        assert_eq!(
+            loads[0]
+                .get_operation()
+                .deref(&ctx)
+                .get_result(0)
+                .get_type(&ctx),
+            f32_ty,
+            "the load reads the payload at its semantic type"
+        );
+    }
+}
diff --git a/crates/mir-lower/src/convert/ops/aggregate/array_extract.rs b/crates/mir-lower/src/convert/ops/aggregate/array_extract.rs
new file mode 100644
index 0000000000..b4d0a36ba7
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/aggregate/array_extract.rs
@@ -0,0 +1,351 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::common::anyhow_to_pliron;
+use crate::convert::types::{convert_type, mir_type_abi_align};
+use dialect_mir::types::MirArrayType;
+use llvm_export::attributes::ICmpPredicateAttr;
+use llvm_export::ops as llvm;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+use pliron::r#type::Typed;
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use std::num::NonZeroUsize;
+
+/// Convert `mir.extract_array_element` to LLVM operations.
+///
+/// A runtime index normally requires materializing the array in memory because
+/// LLVM `extractvalue` accepts only constant indices. When the index is proven
+/// to be `urem value, C`, however, it is in `0..C`. For small `C` within the
+/// array bounds, emit one constant `extractvalue` per candidate and select the
+/// runtime result in SSA. This avoids the temporary alloca that otherwise
+/// becomes NVPTX local memory.
+///
+/// Unbounded, oversized, or otherwise unsupported indices retain the existing
+/// alloca+store+GEP+load fallback.
+pub(crate) fn convert_extract_array_element(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    // One shared cap for the candidate chain, so the mir-transforms
+    // canonicalization and this lowering fast path cannot drift apart.
+    use dialect_mir::ops::MAX_SCALARIZED_CANDIDATES;
+
+    fn integer_constant_u64(ctx: &Context, value: Value) -> Option<u64> {
+        let defining_op = value.defining_op()?;
+        let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, ctx)?;
+        let attribute = constant.get_value(ctx);
+        let integer = attribute.downcast_ref::<pliron::builtin::attributes::IntegerAttr>()?;
+        let integer_value = integer.value();
+        // `APInt::to_u64` truncates wider values, so a >64-bit constant could
+        // be misread as a small in-range divisor. Fail closed on such widths.
+        (integer_value.bw() <= 64).then(|| integer_value.to_u64())
+    }
+
+    fn bounded_urem_candidate_count(ctx: &Context, index: Value, array_size: u64) -> Option<u64> {
+        let defining_op = index.defining_op()?;
+        Operation::get_op::<llvm::URemOp>(defining_op, ctx)?;
+
+        let divisor = defining_op.deref(ctx).get_operand(1);
+        let candidate_count = integer_constant_u64(ctx, divisor)?;
+        (candidate_count > 0
+            && candidate_count <= array_size
+            && candidate_count <= MAX_SCALARIZED_CANDIDATES)
+            .then_some(candidate_count)
+    }
+
+    fn integer_constant_like(
+        ctx: &mut Context,
+        rewriter: &mut DialectConversionRewriter,
+        reference: Value,
+        value: u64,
+    ) -> Result<Value> {
+        let reference_ty = reference.get_type(ctx);
+        let width = reference_ty
+            .deref(ctx)
+            .downcast_ref::<IntegerType>()
+            .ok_or_else(|| {
+                pliron::input_error_noloc!(
+                    "mir.extract_array_element index must lower to an integer"
+                )
+            })?
+            .width();
+
+        let integer_ty = IntegerType::get(ctx, width, Signedness::Signless);
+        let attribute = pliron::builtin::attributes::IntegerAttr::new(
+            integer_ty,
+            APInt::from_u64(
+                value,
+                NonZeroUsize::new(width as usize).expect("integer width is nonzero"),
+            ),
+        );
+        let constant = llvm::ConstantOp::new(ctx, attribute.into());
+        rewriter.insert_operation(ctx, constant.get_operation());
+        Ok(constant.get_operation().deref(ctx).get_result(0))
+    }
+
+    let array_val = op.deref(ctx).get_operand(0);
+    let index_val = op.deref(ctx).get_operand(1);
+
+    let (element_ty, array_size) = {
+        match operands_info.lookup_most_recent_of_type::<MirArrayType>(ctx, array_val) {
+            Some(r) => (r.element_type(), r.size()),
+            None => return pliron::input_err_noloc!("Expected MirArrayType"),
+        }
+    };
+
+    if let Some(candidate_count) = bounded_urem_candidate_count(ctx, index_val, array_size) {
+        let mut candidates = Vec::with_capacity(candidate_count as usize);
+        for candidate_index in 0..candidate_count {
+            let extract = llvm::ExtractValueOp::new(ctx, array_val, vec![candidate_index as u32])?;
+            rewriter.insert_operation(ctx, extract.get_operation());
+            candidates.push(extract.get_operation().deref(ctx).get_result(0));
+        }
+
+        let mut selected = *candidates
+            .last()
+            .expect("candidate count is proven nonzero");
+        for candidate_index in (0..candidates.len().saturating_sub(1)).rev() {
+            let candidate_constant =
+                integer_constant_like(ctx, rewriter, index_val, candidate_index as u64)?;
+            let compare =
+                llvm::ICmpOp::new(ctx, ICmpPredicateAttr::EQ, index_val, candidate_constant);
+            rewriter.insert_operation(ctx, compare.get_operation());
+            let condition = compare.get_operation().deref(ctx).get_result(0);
+
+            let select = llvm::SelectOp::new(ctx, condition, candidates[candidate_index], selected);
+            rewriter.insert_operation(ctx, select.get_operation());
+            selected = select.get_operation().deref(ctx).get_result(0);
+        }
+
+        rewriter.replace_operation_with_values(ctx, op, vec![selected]);
+        return Ok(());
+    }
+
+    let llvm_element_ty = convert_type(ctx, element_ty).map_err(anyhow_to_pliron)?;
+    let llvm_array_ty = llvm_export::types::ArrayType::get(ctx, llvm_element_ty, array_size);
+    let abi_align = mir_type_abi_align(ctx, element_ty);
+
+    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+    let one_val = {
+        let one_apint = APInt::from_i64(1, NonZeroUsize::new(64).unwrap());
+        let one_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, one_apint);
+        let const_op = llvm::ConstantOp::new(ctx, one_attr.into());
+        rewriter.insert_operation(ctx, const_op.get_operation());
+        const_op.get_operation().deref(ctx).get_result(0)
+    };
+
+    let alloca_op = llvm::AllocaOp::new(ctx, llvm_array_ty.into(), one_val);
+    rewriter.insert_operation(ctx, alloca_op.get_operation());
+    if let Some(align) = abi_align {
+        llvm_export::ops::set_op_alignment(ctx, alloca_op.get_operation(), align as u32);
+    }
+    let array_ptr = alloca_op.get_operation().deref(ctx).get_result(0);
+
+    let store_op = llvm::StoreOp::new(ctx, array_val, array_ptr);
+    rewriter.insert_operation(ctx, store_op.get_operation());
+    if let Some(align) = abi_align {
+        llvm_export::ops::set_op_alignment(ctx, store_op.get_operation(), align as u32);
+    }
+
+    use llvm_export::ops::GepIndex;
+    let gep_indices = vec![GepIndex::Constant(0), GepIndex::Value(index_val)];
+    let gep_op = llvm::GetElementPtrOp::new(ctx, array_ptr, gep_indices, llvm_array_ty.into());
+    rewriter.insert_operation(ctx, gep_op.get_operation());
+    let element_ptr = gep_op.get_operation().deref(ctx).get_result(0);
+
+    let load_op = llvm::LoadOp::new(ctx, element_ptr, llvm_element_ty);
+    rewriter.insert_operation(ctx, load_op.get_operation());
+    if let Some(align) = abi_align {
+        llvm_export::ops::set_op_alignment(ctx, load_op.get_operation(), align as u32);
+    }
+    rewriter.replace_operation(ctx, op, load_op.get_operation());
+
+    Ok(())
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production minting lives in mir-importer's facts.rs.
+#[allow(clippy::disallowed_methods)]
+mod tests {
+    use super::*;
+    use crate::convert::ops::test_util::*;
+
+    use dialect_mir::ops as mir;
+    use dialect_mir::types::{MirArrayType, MirStructType, MirTupleType};
+
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::r#type::TypeHandle;
+
+    fn over_aligned_tuple_ty(ctx: &mut Context) -> TypeHandle {
+        let byte: TypeHandle = IntegerType::get(ctx, 8, Signedness::Unsigned).into();
+        let marker: TypeHandle = MirStructType::get_with_full_layout(
+            ctx,
+            "Align32".into(),
+            vec![],
+            vec![],
+            vec![],
+            vec![],
+            0,
+            32,
+        )
+        .into();
+        MirTupleType::get_with_layout(ctx, vec![marker, byte], vec![0, 1], vec![0, 0], 32, 32)
+            .into()
+    }
+
+    fn lower_array_extract_case(
+        ctx: &mut Context,
+        array_size: u64,
+        divisor: Option<u64>,
+    ) -> Ptr<Operation> {
+        let element_type: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+        let index_type = IntegerType::get(ctx, 64, Signedness::Unsigned);
+        let index_handle: TypeHandle = index_type.into();
+        let array_type: TypeHandle = MirArrayType::get(ctx, element_type, array_size).into();
+
+        let (module, block) = build_kernel(ctx, vec![index_handle], vec![element_type]);
+        let raw_index = block.deref(ctx).get_argument(0);
+
+        let undef = mir::MirUndefOp::new(ctx, array_type);
+        undef.get_operation().insert_at_back(block, ctx);
+        let array = undef.get_operation().deref(ctx).get_result(0);
+
+        let index = if let Some(divisor) = divisor {
+            let constant = Operation::new(
+                ctx,
+                mir::MirConstantOp::get_concrete_op_info(),
+                vec![index_handle],
+                vec![],
+                vec![],
+                0,
+            );
+            mir::MirConstantOp::new(constant).set_attr_value(
+                ctx,
+                IntegerAttr::new(
+                    index_type,
+                    APInt::from_u64(divisor, NonZeroUsize::new(64).unwrap()),
+                ),
+            );
+            constant.insert_at_back(block, ctx);
+            let divisor_value = constant.deref(ctx).get_result(0);
+
+            let rem = Operation::new(
+                ctx,
+                mir::MirRemOp::get_concrete_op_info(),
+                vec![index_handle],
+                vec![raw_index, divisor_value],
+                vec![],
+                0,
+            );
+            rem.insert_at_back(block, ctx);
+            rem.deref(ctx).get_result(0)
+        } else {
+            raw_index
+        };
+
+        let extract = Operation::new(
+            ctx,
+            mir::MirExtractArrayElementOp::get_concrete_op_info(),
+            vec![element_type],
+            vec![array, index],
+            vec![],
+            0,
+        );
+        extract.insert_at_back(block, ctx);
+        let result = extract.deref(ctx).get_result(0);
+        append_mir_return(ctx, block, vec![result]);
+
+        crate::lower_mir_to_llvm(ctx, module).expect("lowering failed");
+        module
+    }
+
+    fn assert_array_extract_memory_fallback(ctx: &Context, module: Ptr<Operation>) {
+        let body = kernel_blocks(ctx, module);
+        assert_eq!(count_ops::<llvm::AllocaOp>(ctx, &body), 1);
+        assert_eq!(count_ops::<llvm::StoreOp>(ctx, &body), 1);
+        assert_eq!(count_ops::<llvm::GetElementPtrOp>(ctx, &body), 1);
+        assert_eq!(count_ops::<llvm::LoadOp>(ctx, &body), 1);
+        assert_eq!(count_ops::<llvm::SelectOp>(ctx, &body), 0);
+    }
+
+    #[test]
+    fn bounded_urem_array_extract_stays_in_ssa() {
+        let mut ctx = make_ctx();
+        let module = lower_array_extract_case(&mut ctx, 3, Some(3));
+        let body = kernel_blocks(&ctx, module);
+
+        assert_eq!(count_ops::<llvm::ExtractValueOp>(&ctx, &body), 3);
+        assert_eq!(count_ops::<llvm::ICmpOp>(&ctx, &body), 2);
+        assert_eq!(count_ops::<llvm::SelectOp>(&ctx, &body), 2);
+        assert_eq!(count_ops::<llvm::AllocaOp>(&ctx, &body), 0);
+        assert_eq!(count_ops::<llvm::StoreOp>(&ctx, &body), 0);
+        assert_eq!(count_ops::<llvm::GetElementPtrOp>(&ctx, &body), 0);
+        assert_eq!(count_ops::<llvm::LoadOp>(&ctx, &body), 0);
+    }
+
+    #[test]
+    fn unbounded_array_extract_keeps_memory_fallback() {
+        let mut ctx = make_ctx();
+        let module = lower_array_extract_case(&mut ctx, 3, None);
+        assert_array_extract_memory_fallback(&ctx, module);
+    }
+
+    #[test]
+    fn oversized_urem_array_extract_keeps_memory_fallback() {
+        let mut ctx = make_ctx();
+        let module = lower_array_extract_case(&mut ctx, 17, Some(17));
+        assert_array_extract_memory_fallback(&ctx, module);
+    }
+
+    #[test]
+    fn dynamic_array_extract_preserves_recursive_element_alignment() {
+        let mut ctx = make_ctx();
+        let tuple_ty = over_aligned_tuple_ty(&mut ctx);
+        let inner: TypeHandle = MirArrayType::get(&mut ctx, tuple_ty, 2).into();
+        let outer: TypeHandle = MirArrayType::get(&mut ctx, inner, 3).into();
+        let index_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![index_ty], vec![]);
+        let index = block.deref(&ctx).get_argument(0);
+
+        let undef = mir::MirUndefOp::new(&mut ctx, outer);
+        undef.get_operation().insert_at_back(block, &ctx);
+        let array = undef.get_operation().deref(&ctx).get_result(0);
+        let extract = Operation::new(
+            &mut ctx,
+            mir::MirExtractArrayElementOp::get_concrete_op_info(),
+            vec![inner],
+            vec![array, index],
+            vec![],
+            0,
+        );
+        extract.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+        let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).expect("expected llvm.alloca");
+        let store = find_first::<llvm::StoreOp>(&ctx, &body).expect("expected llvm.store");
+        let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected llvm.load");
+        for memory_op in [
+            alloca.get_operation(),
+            store.get_operation(),
+            load.get_operation(),
+        ] {
+            assert_eq!(llvm_export::ops::op_alignment(&ctx, memory_op), Some(32));
+        }
+    }
+}
diff --git a/crates/mir-lower/src/convert/ops/aggregate/common.rs b/crates/mir-lower/src/convert/ops/aggregate/common.rs
new file mode 100644
index 0000000000..5ac33287ee
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/aggregate/common.rs
@@ -0,0 +1,99 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use llvm_export::ops as llvm;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::irbuild::dialect_conversion::DialectConversionRewriter;
+use pliron::irbuild::inserter::Inserter;
+use pliron::op::Op;
+use pliron::r#type::TypeHandle;
+use pliron::utils::apint::APInt;
+use pliron::value::Value;
+use std::num::NonZeroUsize;
+
+pub(super) fn anyhow_to_pliron(e: anyhow::Error) -> pliron::result::Error {
+    pliron::input_error_noloc!("{e}")
+}
+
+/// Copy an enum value into a fresh stack slot and return the pointer.
+///
+/// This is how we reach a payload field that has no struct slot of its
+/// own (its bytes are shared with a different-typed field of another
+/// variant): once the value sits in memory, a byte-precise pointer can
+/// read or write any part of it, no struct field needed.
+///
+/// The slot is marked with the enum's real (rustc) alignment. The struct
+/// type alone can look under-aligned: `{ i8, [7 x i8] }` says "align 1"
+/// to LLVM, while Rust may require 8.
+///
+/// The alloca lands at the use site, same as
+/// [`convert_extract_array_element`](super::array_extract::convert_extract_array_element);
+/// the standard `opt -O2` run (SROA)
+/// removes it again. Hoisting these into the function's entry block is a
+/// known follow-up for the unoptimized (`CUDA_OXIDE_NO_OPT=1`) path.
+pub(super) fn spill_enum_value(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    enum_val: Value,
+    llvm_struct_ty: TypeHandle,
+    abi_align: u64,
+) -> Value {
+    let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+    let one_apint = APInt::from_i64(1, NonZeroUsize::new(64).unwrap());
+    let one_attr = pliron::builtin::attributes::IntegerAttr::new(i64_ty, one_apint);
+    let one_const = llvm::ConstantOp::new(ctx, one_attr.into());
+    rewriter.insert_operation(ctx, one_const.get_operation());
+    let one_val = one_const.get_operation().deref(ctx).get_result(0);
+
+    let alloca_op = llvm::AllocaOp::new(ctx, llvm_struct_ty, one_val);
+    rewriter.insert_operation(ctx, alloca_op.get_operation());
+    if abi_align > 0 {
+        llvm_export::ops::set_op_alignment(ctx, alloca_op.get_operation(), abi_align as u32);
+    }
+    let slot_ptr = alloca_op.get_operation().deref(ctx).get_result(0);
+
+    let store_op = llvm::StoreOp::new(ctx, enum_val, slot_ptr);
+    rewriter.insert_operation(ctx, store_op.get_operation());
+    if abi_align > 0 {
+        llvm_export::ops::set_op_alignment(ctx, store_op.get_operation(), abi_align as u32);
+    }
+    slot_ptr
+}
+
+/// Pointer to `base + offset` bytes (`getelementptr i8, ptr base, offset`).
+///
+/// Used whenever rustc's physical byte offset cannot be represented faithfully
+/// by a typed LLVM aggregate GEP, as with overlapping enum payloads or packed
+/// struct fields.
+pub(super) fn byte_offset_gep(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    base: Value,
+    offset: u64,
+) -> Value {
+    use llvm_export::ops::GepIndex;
+    let i8_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
+    let offset = emit_integer_constant(ctx, rewriter, 64, u128::from(offset));
+    let gep_op = llvm::GetElementPtrOp::new(ctx, base, vec![GepIndex::Value(offset)], i8_ty);
+    rewriter.insert_operation(ctx, gep_op.get_operation());
+    gep_op.get_operation().deref(ctx).get_result(0)
+}
+
+pub(super) fn emit_integer_constant(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    width: u32,
+    bits: u128,
+) -> Value {
+    let ty = IntegerType::get(ctx, width, Signedness::Signless);
+    let attr = pliron::builtin::attributes::IntegerAttr::new(
+        ty,
+        APInt::from_u128(bits, NonZeroUsize::new(width as usize).unwrap()),
+    );
+    let op = llvm::ConstantOp::new(ctx, attr.into());
+    rewriter.insert_operation(ctx, op.get_operation());
+    op.get_operation().deref(ctx).get_result(0)
+}
diff --git a/crates/mir-lower/src/convert/ops/aggregate/construct.rs b/crates/mir-lower/src/convert/ops/aggregate/construct.rs
new file mode 100644
index 0000000000..cc377cff49
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/aggregate/construct.rs
@@ -0,0 +1,1001 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::common::anyhow_to_pliron;
+use crate::convert::types::{
+    StructLayoutInfo, build_struct_slot_map, convert_type,
+    llvm_packed_struct_contains_pointer_in_address_space, make_slice_struct,
+    packed_shared_internal_abi_info,
+};
+use dialect_mir::types::{
+    MirArrayType, MirDisjointSliceType, MirSliceType, MirStructType, MirTupleType,
+};
+use llvm_export::ops as llvm;
+use llvm_export::types as llvm_types;
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+use pliron::r#type::Typed;
+
+/// Convert `mir.construct_struct` to a chain of `llvm.insertvalue` operations.
+///
+/// Builds a struct by:
+/// 1. Creating an `undef` value of the lowered struct type
+/// 2. Inserting each operand at the LLVM slot its field landed in
+///
+/// Operand order matches field order in the struct type (declaration order).
+/// The LLVM struct type and the slot of each field both come from
+/// [`build_struct_slot_map`], so the insert indices skip `[N x i8]` padding
+/// slots exactly the way the type converter laid them out. ZST fields
+/// (e.g. PhantomData) have no slot and are skipped.
+pub(crate) fn convert_construct_struct(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let (result_ty, operands) = {
+        let mir_op = op.deref(ctx);
+        let result_ty = mir_op.get_result(0).get_type(ctx);
+        let operands: Vec<_> = mir_op.operands().collect();
+        (result_ty, operands)
+    };
+
+    let layout = {
+        let ty_ref = result_ty.deref(ctx);
+        match ty_ref.downcast_ref::<MirStructType>() {
+            Some(s) => StructLayoutInfo::of_struct(s),
+            None => {
+                return pliron::input_err_noloc!(
+                    "MirConstructStructOp result type must be MirStructType"
+                );
+            }
+        }
+    };
+
+    if operands.len() != layout.field_types.len() {
+        return pliron::input_err_noloc!(
+            "construct_struct has {} operands for a struct with {} fields",
+            operands.len(),
+            layout.field_types.len()
+        );
+    }
+
+    let map = build_struct_slot_map(ctx, &layout).map_err(anyhow_to_pliron)?;
+
+    // A divergent rustc layout is constructible by value only when the slot
+    // map proved that a sequential LLVM packed struct reproduces every byte.
+    // Overlapping/union-like legacy struct models remain unrepresentable.
+    if !map.by_value_layout_faithful {
+        return pliron::input_err_noloc!(
+            "constructing a struct whose rustc layout cannot be represented by an LLVM \
+             struct value is not supported; keep the value behind a pointer and access \
+             fields through their byte-accurate address path"
+        );
+    }
+
+    // A packed struct containing AS3 remains target-dependent as a physical
+    // memory image. The internal-call ABI exception is safe to construct in SSA
+    // because its return boundary recursively rebuilds every supported AS3 leaf
+    // into a target-stable generic-pointer carrier before the aggregate crosses
+    // the function ABI.
+    if llvm_packed_struct_contains_pointer_in_address_space(
+        ctx,
+        map.llvm_struct_ty,
+        llvm_types::address_space::SHARED,
+    ) && packed_shared_internal_abi_info(ctx, result_ty)
+        .map_err(anyhow_to_pliron)?
+        .is_none()
+    {
+        return pliron::input_err_noloc!(
+            "constructing a packed aggregate containing a shared-memory pointer by value is \
+             target-mode dependent and is not yet supported"
+        );
+    }
+
+    let undef_op = llvm::UndefOp::new(ctx, map.llvm_struct_ty);
+    rewriter.insert_operation(ctx, undef_op.get_operation());
+    let mut current_struct = undef_op.get_operation().deref(ctx).get_result(0);
+
+    let mut last_insert: Option<Ptr<Operation>> = None;
+    // Walk in memory order so the insertvalue chain ascends slot indices.
+    for &decl_idx in &layout.mem_to_decl {
+        let Some(slot) = map.decl_to_llvm[decl_idx] else {
+            continue; // ZST field: no slot in the LLVM struct.
+        };
+
+        let insert_op =
+            llvm::InsertValueOp::new(ctx, current_struct, operands[decl_idx], vec![slot]);
+        rewriter.insert_operation(ctx, insert_op.get_operation());
+        current_struct = insert_op.get_operation().deref(ctx).get_result(0);
+        last_insert = Some(insert_op.get_operation());
+    }
+
+    match last_insert {
+        Some(last_op) => rewriter.replace_operation(ctx, op, last_op),
+        None => rewriter.replace_operation(ctx, op, undef_op.get_operation()),
+    }
+
+    Ok(())
+}
+
+/// Convert `mir.construct_tuple` to a chain of `llvm.insertvalue` operations.
+///
+/// Tuples are represented as LLVM structs. Same construction pattern as
+/// structs, and like structs the element slots come from
+/// [`build_struct_slot_map`] (identity order, no padding; ZST elements are
+/// stripped and skipped).
+pub(crate) fn convert_construct_tuple(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let (result_ty, operands) = {
+        let mir_op = op.deref(ctx);
+        let result_ty = mir_op.get_result(0).get_type(ctx);
+        let operands: Vec<_> = mir_op.operands().collect();
+        (result_ty, operands)
+    };
+
+    let layout = {
+        let ty_ref = result_ty.deref(ctx);
+        match ty_ref.downcast_ref::<MirTupleType>() {
+            Some(t) => StructLayoutInfo::of_tuple(t),
+            None => {
+                return pliron::input_err_noloc!(
+                    "MirConstructTupleOp result type must be MirTupleType"
+                );
+            }
+        }
+    };
+
+    if operands.len() != layout.field_types.len() {
+        return pliron::input_err_noloc!(
+            "construct_tuple has {} operands for a tuple with {} elements",
+            operands.len(),
+            layout.field_types.len()
+        );
+    }
+
+    let map = build_struct_slot_map(ctx, &layout).map_err(anyhow_to_pliron)?;
+
+    let undef_op = llvm::UndefOp::new(ctx, map.llvm_struct_ty);
+    rewriter.insert_operation(ctx, undef_op.get_operation());
+    let mut current_tuple = undef_op.get_operation().deref(ctx).get_result(0);
+
+    let mut last_insert: Option<Ptr<Operation>> = None;
+    for (mir_idx, operand) in operands.iter().enumerate() {
+        let Some(slot) = map.decl_to_llvm[mir_idx] else {
+            continue; // ZST element: no slot in the LLVM struct.
+        };
+
+        let insert_op = llvm::InsertValueOp::new(ctx, current_tuple, *operand, vec![slot]);
+        rewriter.insert_operation(ctx, insert_op.get_operation());
+        current_tuple = insert_op.get_operation().deref(ctx).get_result(0);
+        last_insert = Some(insert_op.get_operation());
+    }
+
+    match last_insert {
+        Some(last_op) => rewriter.replace_operation(ctx, op, last_op),
+        None => rewriter.replace_operation(ctx, op, undef_op.get_operation()),
+    }
+
+    Ok(())
+}
+
+/// Convert `mir.construct_slice` to `llvm.undef` + two `llvm.insertvalue`s.
+///
+/// `MirSliceType` lowers to the `{ ptr, i64 }` fat-pointer struct, where
+/// field 0 is the data pointer and field 1 is the element count by
+/// construction (the same layout the entry prologue's `reconstruct_slice`
+/// and the Unsize cast path build). `MirSliceType::kind` is intentionally
+/// semantic-only: all reference/raw-pointer kinds share this physical layout
+/// and no LLVM alias metadata is inferred here.
+pub(crate) fn convert_construct_slice(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let (result_ty, data_val, len_val) = {
+        let mir_op = op.deref(ctx);
+        (
+            mir_op.get_result(0).get_type(ctx),
+            mir_op.get_operand(0),
+            mir_op.get_operand(1),
+        )
+    };
+
+    if !result_ty.deref(ctx).is::<MirSliceType>() {
+        return pliron::input_err_noloc!("MirConstructSliceOp result type must be MirSliceType");
+    }
+
+    let slice_struct_ty = make_slice_struct(ctx);
+
+    let undef_op = llvm::UndefOp::new(ctx, slice_struct_ty);
+    rewriter.insert_operation(ctx, undef_op.get_operation());
+    let undef_val = undef_op.get_operation().deref(ctx).get_result(0);
+
+    let insert_ptr = llvm::InsertValueOp::new(ctx, undef_val, data_val, vec![0]);
+    rewriter.insert_operation(ctx, insert_ptr.get_operation());
+    let with_ptr = insert_ptr.get_operation().deref(ctx).get_result(0);
+
+    let insert_len = llvm::InsertValueOp::new(ctx, with_ptr, len_val, vec![1]);
+    rewriter.insert_operation(ctx, insert_len.get_operation());
+
+    rewriter.replace_operation(ctx, op, insert_len.get_operation());
+
+    Ok(())
+}
+
+/// Convert `mir.construct_disjoint_slice` to a chain of `llvm.insertvalue`
+/// operations.
+///
+/// The same shape as [`convert_construct_slice`], one insert longer per
+/// runtime layout word the index space carries. The struct type comes from
+/// [`make_disjoint_slice_struct`], the same constructor the type converter
+/// uses, so the field order here cannot drift from the lowered layout that
+/// [`resolve_aggregate_slots`](super::fields::resolve_aggregate_slots) indexes identically.
+pub(crate) fn convert_construct_disjoint_slice(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let (result_ty, operands) = {
+        let mir_op = op.deref(ctx);
+        let operands: Vec<_> = mir_op.operands().collect();
+        (mir_op.get_result(0).get_type(ctx), operands)
+    };
+
+    let space_tys = {
+        let ty_ref = result_ty.deref(ctx);
+        match ty_ref.downcast_ref::<MirDisjointSliceType>() {
+            Some(slice_ty) => slice_ty.space_types().to_vec(),
+            None => {
+                return pliron::input_err_noloc!(
+                    "MirConstructDisjointSliceOp result type must be MirDisjointSliceType"
+                );
+            }
+        }
+    };
+
+    // The verifier already pins the operand count to the result type. Check
+    // it here too: this pass runs on operations the verifier accepted, and a
+    // short operand list would otherwise index past the end below.
+    let expected_operands = 2 + space_tys.len();
+    if operands.len() != expected_operands {
+        return pliron::input_err_noloc!(
+            "MirConstructDisjointSliceOp expects {expected_operands} operands, got {}",
+            operands.len()
+        );
+    }
+
+    let slice_struct_ty = crate::convert::types::make_disjoint_slice_struct(ctx, &space_tys)
+        .map_err(anyhow_to_pliron)?;
+
+    let undef_op = llvm::UndefOp::new(ctx, slice_struct_ty);
+    rewriter.insert_operation(ctx, undef_op.get_operation());
+    let mut current = undef_op.get_operation().deref(ctx).get_result(0);
+    let mut last_insert = undef_op.get_operation();
+
+    for (slot, operand) in operands.into_iter().enumerate() {
+        let insert = llvm::InsertValueOp::new(ctx, current, operand, vec![slot as u32]);
+        rewriter.insert_operation(ctx, insert.get_operation());
+        current = insert.get_operation().deref(ctx).get_result(0);
+        last_insert = insert.get_operation();
+    }
+
+    rewriter.replace_operation(ctx, op, last_insert);
+
+    Ok(())
+}
+
+/// Convert `mir.construct_array` to a chain of `llvm.insertvalue` operations.
+///
+/// Arrays are represented as LLVM arrays. Same construction pattern as structs:
+/// 1. Create `undef` of the array type
+/// 2. Insert each element at its index
+pub(crate) fn convert_construct_array(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let (result_ty, operands) = {
+        let mir_op = op.deref(ctx);
+        let result_ty = mir_op.get_result(0).get_type(ctx);
+        let operands: Vec<_> = mir_op.operands().collect();
+        (result_ty, operands)
+    };
+
+    let (element_ty, array_size) = {
+        let ty_ref = result_ty.deref(ctx);
+        match ty_ref.downcast_ref::<MirArrayType>() {
+            Some(a) => (a.element_type(), a.size()),
+            None => {
+                return pliron::input_err_noloc!(
+                    "MirConstructArrayOp result type must be MirArrayType"
+                );
+            }
+        }
+    };
+
+    let llvm_element_ty = convert_type(ctx, element_ty).map_err(anyhow_to_pliron)?;
+    let llvm_array_ty = llvm_export::types::ArrayType::get(ctx, llvm_element_ty, array_size);
+
+    let undef_op = llvm::UndefOp::new(ctx, llvm_array_ty.into());
+    rewriter.insert_operation(ctx, undef_op.get_operation());
+    let mut current_array = undef_op.get_operation().deref(ctx).get_result(0);
+
+    let mut last_insert: Option<Ptr<Operation>> = None;
+    for (i, operand) in operands.iter().enumerate() {
+        let insert_op = llvm::InsertValueOp::new(ctx, current_array, *operand, vec![i as u32]);
+        rewriter.insert_operation(ctx, insert_op.get_operation());
+        current_array = insert_op.get_operation().deref(ctx).get_result(0);
+        last_insert = Some(insert_op.get_operation());
+    }
+
+    match last_insert {
+        Some(last_op) => rewriter.replace_operation(ctx, op, last_op),
+        None => rewriter.replace_operation(ctx, op, undef_op.get_operation()),
+    }
+
+    Ok(())
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production minting lives in mir-importer's facts.rs.
+#[allow(clippy::disallowed_methods)]
+mod tests {
+    use super::*;
+    use crate::convert::ops::test_util::*;
+
+    use dialect_mir::ops as mir;
+    use dialect_mir::types::{
+        MirArrayType, MirPointerKind, MirPtrType, MirSliceType, MirStructType,
+    };
+    use llvm_export::types as llvm_types;
+
+    use pliron::common_traits::Verify;
+
+    use crate::convert::types::llvm_type_size_align;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::r#type::TypeHandle;
+
+    use super::super::test_support::*;
+
+    /// `mir.construct_slice` lowers to the canonical fat-pointer value:
+    /// `undef { ptr, i64 }`, then insert data pointer at slot 0 and length at slot 1.
+    #[test]
+    fn construct_slice_lowers_to_ptr_len_insert_values() {
+        let mut ctx = make_ctx();
+
+        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let usize_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, i8_ty, false).into();
+        let slice_ty: TypeHandle = MirSliceType::get(&mut ctx, i8_ty).into();
+
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty, usize_ty], vec![]);
+        let data_ptr = block.deref(&ctx).get_argument(0);
+        let len = block.deref(&ctx).get_argument(1);
+
+        let op = Operation::new(
+            &mut ctx,
+            mir::MirConstructSliceOp::get_concrete_op_info(),
+            vec![slice_ty],
+            vec![data_ptr, len],
+            vec![],
+            0,
+        );
+        op.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
+
+        assert_eq!(
+            insert_indices(&ctx, &inserts),
+            vec![vec![0], vec![1]],
+            "slice construction must insert data pointer at slot 0 and length at slot 1"
+        );
+        let first_insert = inserts[0].get_operation();
+        let second_insert = inserts[1].get_operation();
+        assert_eq!(
+            first_insert.deref(&ctx).get_operand(1),
+            data_ptr,
+            "slice slot 0 must receive the original data pointer"
+        );
+        assert_eq!(
+            second_insert.deref(&ctx).get_operand(0),
+            first_insert.deref(&ctx).get_result(0),
+            "the length insertion must consume the aggregate produced by the pointer insertion"
+        );
+        assert_eq!(
+            second_insert.deref(&ctx).get_operand(1),
+            len,
+            "slice slot 1 must receive the original length"
+        );
+        assert!(
+            inserts.iter().all(|insert| insert.verify(&ctx).is_ok()),
+            "both slice insertions must satisfy LLVM dialect verification"
+        );
+        assert_eq!(
+            count_ops::<llvm::UndefOp>(&ctx, &body),
+            1,
+            "slice construction should start from one undef aggregate"
+        );
+    }
+
+    /// `mir.construct_disjoint_slice` lowers to the same insert chain as the
+    /// fat pointer for an index space with no runtime layout.
+    #[test]
+    fn construct_disjoint_slice_lowers_to_ptr_len_insert_values() {
+        let mut ctx = make_ctx();
+
+        let f32_ty: TypeHandle = pliron::builtin::types::FP32Type::get(&ctx).into();
+        let usize_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let ptr_ty: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, f32_ty, true, MirPointerKind::RawMut)
+                .into();
+        let slice_ty: TypeHandle = MirDisjointSliceType::get(&mut ctx, f32_ty).into();
+
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty, usize_ty], vec![]);
+        let data_ptr = block.deref(&ctx).get_argument(0);
+        let len = block.deref(&ctx).get_argument(1);
+
+        let op = Operation::new(
+            &mut ctx,
+            mir::MirConstructDisjointSliceOp::get_concrete_op_info(),
+            vec![slice_ty],
+            vec![data_ptr, len],
+            vec![],
+            0,
+        );
+        op.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
+        assert_eq!(
+            insert_indices(&ctx, &inserts),
+            vec![vec![0], vec![1]],
+            "a space-free disjoint slice must insert pointer at slot 0 and length at slot 1"
+        );
+        assert_eq!(
+            inserts[0].get_operation().deref(&ctx).get_operand(1),
+            data_ptr,
+            "slot 0 must receive the original data pointer"
+        );
+        assert_eq!(
+            inserts[1].get_operation().deref(&ctx).get_operand(1),
+            len,
+            "slot 1 must receive the original length"
+        );
+        assert_eq!(
+            count_ops::<llvm::UndefOp>(&ctx, &body),
+            1,
+            "construction should start from one undef aggregate"
+        );
+    }
+
+    /// The runtime row width is the third operand and must land in slot 2.
+    /// Writing it into the length slot, or dropping it, gives a slice whose
+    /// row width reads back as something else at every access site.
+    #[test]
+    fn construct_disjoint_slice_places_the_row_width_after_ptr_and_len() {
+        let mut ctx = make_ctx();
+
+        let f32_ty: TypeHandle = pliron::builtin::types::FP32Type::get(&ctx).into();
+        let usize_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let width_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let ptr_ty: TypeHandle =
+            MirPtrType::get_generic_with_kind(&mut ctx, f32_ty, true, MirPointerKind::RawMut)
+                .into();
+        let slice_ty: TypeHandle =
+            MirDisjointSliceType::get_with_space(&mut ctx, f32_ty, vec![width_ty]).into();
+
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty, usize_ty, width_ty], vec![]);
+        let data_ptr = block.deref(&ctx).get_argument(0);
+        let len = block.deref(&ctx).get_argument(1);
+        let width = block.deref(&ctx).get_argument(2);
+
+        let op = Operation::new(
+            &mut ctx,
+            mir::MirConstructDisjointSliceOp::get_concrete_op_info(),
+            vec![slice_ty],
+            vec![data_ptr, len, width],
+            vec![],
+            0,
+        );
+        op.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
+        assert_eq!(
+            insert_indices(&ctx, &inserts),
+            vec![vec![0], vec![1], vec![2]],
+            "the row width must occupy slot 2, after the pointer and the length"
+        );
+        assert_eq!(
+            inserts[2].get_operation().deref(&ctx).get_operand(1),
+            width,
+            "slot 2 must receive the row width operand, not the length"
+        );
+        assert_eq!(
+            inserts[1].get_operation().deref(&ctx).get_operand(1),
+            len,
+            "slot 1 must still receive the length"
+        );
+    }
+
+    /// Explicit rustc layout must be respected: field `b` is at byte offset 8,
+    /// so the lowered LLVM struct has a padding slot between `a` and `b`.
+    /// The ZST marker field is stripped and receives no insert_value.
+    #[test]
+    fn construct_struct_uses_layout_slots_and_skips_zst() {
+        let mut ctx = make_ctx();
+
+        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
+        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
+        let (struct_ty, zst_ty) = padded_struct_with_zst_ty(&mut ctx);
+
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![i8_ty, i64_ty], vec![]);
+        let a = block.deref(&ctx).get_argument(0);
+        let b = block.deref(&ctx).get_argument(1);
+        let marker = append_empty_struct_value(&mut ctx, block, zst_ty);
+
+        let op = Operation::new(
+            &mut ctx,
+            mir::MirConstructStructOp::get_concrete_op_info(),
+            vec![struct_ty],
+            vec![a, marker, b],
+            vec![],
+            0,
+        );
+        op.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
+
+        assert_eq!(
+            insert_indices(&ctx, &inserts),
+            vec![vec![0], vec![2]],
+            "non-ZST fields must be inserted at their layout slots, skipping padding and ZSTs"
+        );
+        let first_insert = inserts[0].get_operation();
+        let second_insert = inserts[1].get_operation();
+        assert_eq!(
+            first_insert.deref(&ctx).get_operand(1),
+            a,
+            "struct slot 0 must receive field `a`"
+        );
+        assert_eq!(
+            second_insert.deref(&ctx).get_operand(0),
+            first_insert.deref(&ctx).get_result(0),
+            "field `b` must be inserted into the aggregate containing field `a`"
+        );
+        assert_eq!(
+            second_insert.deref(&ctx).get_operand(1),
+            b,
+            "struct slot 2 must receive field `b`"
+        );
+        assert!(
+            inserts.iter().all(|insert| insert.verify(&ctx).is_ok()),
+            "both struct insertions must satisfy LLVM dialect verification"
+        );
+    }
+
+    /// A by-value packed struct is represented by an LLVM packed struct, so
+    /// construction can use the ordinary insertvalue chain without changing
+    /// rustc's field offsets or total byte size.
+    #[test]
+    fn packed_struct_construction_by_value_uses_packed_layout() {
+        use dialect_mir::ops::MirConstructStructOp;
+
+        let mut ctx = make_ctx();
+
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Packed".into(),
+            vec!["tag".into(), "value".into()],
+            vec![u8_ty, u32_ty],
+            vec![0, 1],
+            vec![0, 1],
+            5,
+            1,
+        )
+        .into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![u8_ty, u32_ty], vec![]);
+        let tag = block.deref(&ctx).get_argument(0);
+        let value = block.deref(&ctx).get_argument(1);
+
+        let construct = Operation::new(
+            &mut ctx,
+            MirConstructStructOp::get_concrete_op_info(),
+            vec![packed_ty],
+            vec![tag, value],
+            vec![],
+            0,
+        );
+        construct.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module)
+            .expect("constructing a pointer-free packed struct by value must lower");
+
+        let body = kernel_blocks(&ctx, module);
+        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
+        assert_eq!(
+            insert_indices(&ctx, &inserts),
+            vec![vec![0], vec![1]],
+            "packed construction must keep declaration fields in their packed LLVM slots"
+        );
+        let result_ty = inserts
+            .last()
+            .expect("packed construction must emit insertvalue")
+            .get_operation()
+            .deref(&ctx)
+            .get_result(0)
+            .get_type(&ctx);
+        let result_ty_ref = result_ty.deref(&ctx);
+        let struct_ty = result_ty_ref
+            .downcast_ref::<llvm_types::StructType>()
+            .expect("packed construction result must be an LLVM struct");
+        assert_eq!(struct_ty.layout(), llvm_types::StructLayout::Packed);
+        assert_eq!(llvm_type_size_align(&ctx, result_ty), Some((5, 1)));
+    }
+
+    #[test]
+    fn packed_struct_construction_with_one_direct_shared_pointer_stays_semantic_in_ssa() {
+        use dialect_mir::ops::MirConstructStructOp;
+
+        let mut ctx = make_ctx();
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let shared_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedShared".into(),
+            vec!["tag".into(), "ptr".into()],
+            vec![u8_ty, shared_ty],
+            vec![0, 1],
+            vec![0, 1],
+            9,
+            1,
+        )
+        .into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![u8_ty, shared_ty], vec![]);
+        let tag = block.deref(&ctx).get_argument(0);
+        let ptr = block.deref(&ctx).get_argument(1);
+        let construct = Operation::new(
+            &mut ctx,
+            MirConstructStructOp::get_concrete_op_info(),
+            vec![packed_ty],
+            vec![tag, ptr],
+            vec![],
+            0,
+        );
+        construct.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module)
+            .expect("one direct AS3 pointer in a packed SSA aggregate must lower");
+
+        let body = kernel_blocks(&ctx, module);
+        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
+        assert_eq!(
+            insert_indices(&ctx, &inserts),
+            vec![vec![0], vec![1]],
+            "packed AS3 construction must preserve the semantic packed field slots"
+        );
+
+        let result_ty = inserts
+            .last()
+            .expect("packed AS3 construction must emit insertvalue")
+            .get_operation()
+            .deref(&ctx)
+            .get_result(0)
+            .get_type(&ctx);
+        let result_ty_ref = result_ty.deref(&ctx);
+        let struct_ty = result_ty_ref
+            .downcast_ref::<llvm_types::StructType>()
+            .expect("packed AS3 construction result must be an LLVM struct");
+        assert_eq!(struct_ty.layout(), llvm_types::StructLayout::Packed);
+        assert_eq!(llvm_type_size_align(&ctx, result_ty), Some((9, 1)));
+
+        let pointer_ty = struct_ty.field_type(1);
+        let pointer_ty_ref = pointer_ty.deref(&ctx);
+        let pointer = pointer_ty_ref
+            .downcast_ref::<llvm_types::PointerType>()
+            .expect("second packed field must remain a pointer");
+        assert_eq!(
+            pointer.address_space(),
+            llvm_types::address_space::SHARED,
+            "construction must keep the semantic pointer in AS3"
+        );
+        assert_eq!(
+            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
+            0,
+            "construction itself must not genericize the shared pointer"
+        );
+    }
+
+    #[test]
+    fn packed_struct_construction_with_multiple_direct_shared_pointers_stays_semantic_in_ssa() {
+        use dialect_mir::ops::MirConstructStructOp;
+
+        let mut ctx = make_ctx();
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let shared_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedSharedPair".into(),
+            vec!["tag".into(), "left".into(), "right".into()],
+            vec![u8_ty, shared_ty, shared_ty],
+            vec![0, 1, 2],
+            vec![0, 1, 9],
+            17,
+            1,
+        )
+        .into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![u8_ty, shared_ty, shared_ty], vec![]);
+        let tag = block.deref(&ctx).get_argument(0);
+        let left = block.deref(&ctx).get_argument(1);
+        let right = block.deref(&ctx).get_argument(2);
+        let construct = Operation::new(
+            &mut ctx,
+            MirConstructStructOp::get_concrete_op_info(),
+            vec![packed_ty],
+            vec![tag, left, right],
+            vec![],
+            0,
+        );
+        construct.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module)
+            .expect("multiple direct AS3 leaves in a packed SSA aggregate must lower");
+
+        let body = kernel_blocks(&ctx, module);
+        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
+        assert_eq!(
+            insert_indices(&ctx, &inserts),
+            vec![vec![0], vec![1], vec![2]],
+            "all direct shared leaves must remain in their semantic packed slots"
+        );
+
+        let result_ty = inserts
+            .last()
+            .expect("packed AS3 construction must emit insertvalue")
+            .get_operation()
+            .deref(&ctx)
+            .get_result(0)
+            .get_type(&ctx);
+        let result_ty_ref = result_ty.deref(&ctx);
+        let struct_ty = result_ty_ref
+            .downcast_ref::<llvm_types::StructType>()
+            .expect("packed AS3 construction result must be an LLVM struct");
+        assert_eq!(struct_ty.layout(), llvm_types::StructLayout::Packed);
+        assert_eq!(llvm_type_size_align(&ctx, result_ty), Some((17, 1)));
+        for slot in [1usize, 2] {
+            let pointer_ty = struct_ty.field_type(slot);
+            let pointer_ty_ref = pointer_ty.deref(&ctx);
+            let pointer = pointer_ty_ref
+                .downcast_ref::<llvm_types::PointerType>()
+                .expect("direct shared leaves must remain pointer-typed");
+            assert_eq!(pointer.address_space(), llvm_types::address_space::SHARED);
+        }
+        assert_eq!(
+            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
+            0,
+            "semantic construction must not genericize any direct shared leaf"
+        );
+    }
+
+    #[test]
+    fn packed_struct_construction_with_nested_shared_pointers_stays_semantic_in_ssa() {
+        use dialect_mir::ops::MirConstructStructOp;
+
+        let mut ctx = make_ctx();
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let shared_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let inner_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "SharedPair".into(),
+            vec!["left".into(), "right".into()],
+            vec![shared_ty, shared_ty],
+            vec![0, 1],
+            vec![0, 8],
+            16,
+            8,
+        )
+        .into();
+        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedNestedShared".into(),
+            vec!["tag".into(), "pair".into()],
+            vec![u8_ty, inner_ty],
+            vec![0, 1],
+            vec![0, 1],
+            17,
+            1,
+        )
+        .into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![u8_ty, shared_ty, shared_ty], vec![]);
+        let tag = block.deref(&ctx).get_argument(0);
+        let left = block.deref(&ctx).get_argument(1);
+        let right = block.deref(&ctx).get_argument(2);
+
+        let inner = Operation::new(
+            &mut ctx,
+            MirConstructStructOp::get_concrete_op_info(),
+            vec![inner_ty],
+            vec![left, right],
+            vec![],
+            0,
+        );
+        inner.insert_at_back(block, &ctx);
+        let inner_value = inner.deref(&ctx).get_result(0);
+
+        let outer = Operation::new(
+            &mut ctx,
+            MirConstructStructOp::get_concrete_op_info(),
+            vec![packed_ty],
+            vec![tag, inner_value],
+            vec![],
+            0,
+        );
+        outer.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module)
+            .expect("nested AS3 leaves in a packed SSA aggregate must lower");
+
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(
+            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
+            0,
+            "semantic construction must keep nested shared leaves in AS3"
+        );
+
+        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
+        let packed_result = inserts
+            .iter()
+            .filter_map(|insert| {
+                let result_ty = insert
+                    .get_operation()
+                    .deref(&ctx)
+                    .get_result(0)
+                    .get_type(&ctx);
+                let is_packed = result_ty
+                    .deref(&ctx)
+                    .downcast_ref::<llvm_types::StructType>()
+                    .is_some_and(|ty| ty.layout() == llvm_types::StructLayout::Packed);
+                is_packed.then_some(result_ty)
+            })
+            .last()
+            .expect("outer packed construction must produce a packed LLVM struct");
+
+        assert_eq!(llvm_type_size_align(&ctx, packed_result), Some((17, 1)));
+        assert!(
+            llvm_packed_struct_contains_pointer_in_address_space(
+                &ctx,
+                packed_result,
+                llvm_types::address_space::SHARED,
+            ),
+            "the semantic packed value must retain its recursively nested AS3 leaves"
+        );
+    }
+
+    #[test]
+    fn packed_struct_construction_with_bounded_shared_pointer_array_stays_semantic_in_ssa() {
+        use dialect_mir::ops::{MirConstructArrayOp, MirConstructStructOp};
+
+        let mut ctx = make_ctx();
+        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let shared_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let array_ty: TypeHandle = MirArrayType::get(&mut ctx, shared_ty, 2).into();
+        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedSharedArray".into(),
+            vec!["tag".into(), "ptrs".into()],
+            vec![u8_ty, array_ty],
+            vec![0, 1],
+            vec![0, 1],
+            17,
+            1,
+        )
+        .into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![u8_ty, shared_ty, shared_ty], vec![]);
+        let tag = block.deref(&ctx).get_argument(0);
+        let left = block.deref(&ctx).get_argument(1);
+        let right = block.deref(&ctx).get_argument(2);
+
+        let array = Operation::new(
+            &mut ctx,
+            MirConstructArrayOp::get_concrete_op_info(),
+            vec![array_ty],
+            vec![left, right],
+            vec![],
+            0,
+        );
+        array.insert_at_back(block, &ctx);
+        let array_value = array.deref(&ctx).get_result(0);
+
+        let outer = Operation::new(
+            &mut ctx,
+            MirConstructStructOp::get_concrete_op_info(),
+            vec![packed_ty],
+            vec![tag, array_value],
+            vec![],
+            0,
+        );
+        outer.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module)
+            .expect("a bounded AS3 array in a packed SSA aggregate must lower");
+
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(
+            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
+            0,
+            "semantic construction must keep array elements in AS3"
+        );
+
+        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
+        let packed_result = inserts
+            .iter()
+            .filter_map(|insert| {
+                let result_ty = insert
+                    .get_operation()
+                    .deref(&ctx)
+                    .get_result(0)
+                    .get_type(&ctx);
+                let is_packed = result_ty
+                    .deref(&ctx)
+                    .downcast_ref::<llvm_types::StructType>()
+                    .is_some_and(|ty| ty.layout() == llvm_types::StructLayout::Packed);
+                is_packed.then_some(result_ty)
+            })
+            .last()
+            .expect("outer packed array construction must produce a packed LLVM struct");
+        assert_eq!(llvm_type_size_align(&ctx, packed_result), Some((17, 1)));
+        assert!(
+            llvm_packed_struct_contains_pointer_in_address_space(
+                &ctx,
+                packed_result,
+                llvm_types::address_space::SHARED,
+            ),
+            "the semantic packed value must retain AS3 array elements"
+        );
+    }
+}
diff --git a/crates/mir-lower/src/convert/ops/aggregate/enum_layout.rs b/crates/mir-lower/src/convert/ops/aggregate/enum_layout.rs
new file mode 100644
index 0000000000..179ce032b6
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/aggregate/enum_layout.rs
@@ -0,0 +1,220 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::common::emit_integer_constant;
+use crate::convert::enum_payload_storage::coerce_enum_payload_value;
+use crate::convert::types::{llvm_byte_faithful_twin, llvm_type_contains_i1};
+use dialect_mir::types::{EnumCarrierKind, EnumLayoutKind, MirEnumType};
+use llvm_export::op_interfaces::{CastOpInterface, CastOpWithNNegInterface};
+use llvm_export::ops as llvm;
+use llvm_export::types as llvm_types;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::irbuild::dialect_conversion::DialectConversionRewriter;
+use pliron::irbuild::inserter::Inserter;
+use pliron::op::Op;
+use pliron::result::Result;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+
+/// The physical carrier write required to select one source variant.
+/// `None` is a real semantic result for the untagged niche variant and for
+/// rustc's single inhabited variant; it must never be replaced by a guessed
+/// memory write.
+pub(super) fn enum_carrier_bits_for_variant(
+    enum_ty: &MirEnumType,
+    variant: usize,
+) -> std::result::Result<Option<u128>, String> {
+    if variant >= enum_ty.variant_count() || enum_ty.variant_is_inhabited(variant) != Some(true) {
+        return Err(format!(
+            "cannot select uninhabited or missing variant {} of '{}'",
+            variant,
+            enum_ty.name()
+        ));
+    }
+
+    match enum_ty.layout_kind {
+        EnumLayoutKind::Direct => enum_ty
+            .variant_discriminants
+            .get(variant)
+            .copied()
+            .map(|bits| Some(u128::from(bits)))
+            .ok_or_else(|| format!("variant {} has no declared discriminant", variant)),
+        EnumLayoutKind::Niche => {
+            // This check deliberately comes before the encoded range check:
+            // rustc permits the untagged variant index to lie inside that
+            // range. Its range position is a dead niche value; selecting the
+            // actual untagged variant remains a no-op.
+            if variant == enum_ty.untagged_variant as usize {
+                return Ok(None);
+            }
+            if !(enum_ty.niche_variant_start as usize..=enum_ty.niche_variant_end as usize)
+                .contains(&variant)
+            {
+                return Err(format!(
+                    "inhabited variant {} is not representable by niche layout of '{}'",
+                    variant,
+                    enum_ty.name()
+                ));
+            }
+            let offset = (variant as u128) - u128::from(enum_ty.niche_variant_start);
+            let mut bits = enum_ty.niche_start().wrapping_add(offset);
+            if enum_ty.carrier_width < 128 {
+                bits &= (1u128 << enum_ty.carrier_width) - 1;
+            }
+            Ok(Some(bits))
+        }
+        EnumLayoutKind::Single if variant == enum_ty.single_variant as usize => Ok(None),
+        EnumLayoutKind::Single => Err(format!(
+            "variant {} is not the single inhabited variant of '{}'",
+            variant,
+            enum_ty.name()
+        )),
+        EnumLayoutKind::Empty => Err(format!("enum '{}' is uninhabited", enum_ty.name())),
+        EnumLayoutKind::Unknown => Err(format!(
+            "enum '{}' has unknown physical layout",
+            enum_ty.name()
+        )),
+    }
+}
+
+pub(super) fn emit_carrier_constant(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    enum_ty: &MirEnumType,
+    carrier_ty: TypeHandle,
+    bits: u128,
+) -> Result<Value> {
+    let integer = emit_integer_constant(ctx, rewriter, enum_ty.carrier_width, bits);
+    match enum_ty.carrier_kind {
+        EnumCarrierKind::Integer => Ok(integer),
+        EnumCarrierKind::Pointer => {
+            let cast = llvm::IntToPtrOp::new(ctx, integer, carrier_ty);
+            rewriter.insert_operation(ctx, cast.get_operation());
+            Ok(cast.get_operation().deref(ctx).get_result(0))
+        }
+        _ => pliron::input_err_noloc!("enum carrier constant requested without a carrier"),
+    }
+}
+
+/// Convert a value to its byte-faithful storage twin: every `i1` leaf is
+/// zero-extended to its canonical `i8` memory byte, recursively through
+/// structs and arrays. Values without `i1` storage pass through unchanged.
+///
+/// This is the value-level half of [`llvm_byte_faithful_twin`]: the enum
+/// slot map claims twin-typed storage for bool-bearing payloads, and this
+/// produces the twin-typed value the store into that storage needs.
+pub(super) fn canonicalize_bool_value_bytes(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    value: Value,
+) -> Result<Value> {
+    let ty = value.get_type(ctx);
+    if !llvm_type_contains_i1(ctx, ty) {
+        return Ok(value);
+    }
+    let is_scalar_i1 = ty
+        .deref(ctx)
+        .downcast_ref::<IntegerType>()
+        .is_some_and(|integer| integer.width() == 1);
+    if is_scalar_i1 {
+        let byte_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
+        let zext = llvm::ZExtOp::new_with_nneg(ctx, value, byte_ty, false);
+        rewriter.insert_operation(ctx, zext.get_operation());
+        return Ok(zext.get_operation().deref(ctx).get_result(0));
+    }
+    let Some(twin) = llvm_byte_faithful_twin(ctx, ty) else {
+        return pliron::input_err_noloc!(
+            "enum construction: bool storage in this value's shape cannot be canonicalized"
+        );
+    };
+    let element_count = {
+        let ty_ref = ty.deref(ctx);
+        if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+            struct_ty.fields().count() as u64
+        } else if let Some(array_ty) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+            array_ty.size()
+        } else {
+            return pliron::input_err_noloc!(
+                "enum construction: unexpected container for bool storage canonicalization"
+            );
+        }
+    };
+    let undef_op = llvm::UndefOp::new(ctx, twin);
+    rewriter.insert_operation(ctx, undef_op.get_operation());
+    let mut current = undef_op.get_operation().deref(ctx).get_result(0);
+    for index in 0..element_count {
+        let extract_op = llvm::ExtractValueOp::new(ctx, value, vec![index as u32])?;
+        rewriter.insert_operation(ctx, extract_op.get_operation());
+        let element = extract_op.get_operation().deref(ctx).get_result(0);
+        let converted = canonicalize_bool_value_bytes(ctx, rewriter, element)?;
+        let insert_op = llvm::InsertValueOp::new(ctx, current, converted, vec![index as u32]);
+        rewriter.insert_operation(ctx, insert_op.get_operation());
+        current = insert_op.get_operation().deref(ctx).get_result(0);
+    }
+    Ok(current)
+}
+
+/// Adapt a semantic enum payload value to or from its physical storage type.
+///
+/// Shared pointer leaves are converted through CUDA generic space recursively
+/// through struct/tuple payloads. Bool leaves are canonicalized separately on
+/// construction and narrowed recursively on extraction.
+pub(super) fn coerce_enum_payload_storage(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    value: Value,
+    target_ty: TypeHandle,
+) -> Result<Value> {
+    coerce_enum_payload_value(ctx, rewriter, value, target_ty)
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production minting lives in mir-importer's facts.rs.
+#[allow(clippy::disallowed_methods)]
+mod tests {
+    use super::*;
+    use crate::convert::ops::test_util::*;
+
+    use super::super::test_support::*;
+
+    #[test]
+    fn niche_encoding_handles_untagged_inside_range_and_u128_wrap() {
+        let mut ctx = make_ctx();
+        let inside = unit_niche_enum(
+            &mut ctx,
+            (EnumCarrierKind::Integer, 8, 0),
+            42,
+            0..=1,
+            1,
+            vec![1, 1],
+        );
+        let inside_ref = inside.deref(&ctx);
+        let inside_enum = inside_ref.downcast_ref::<MirEnumType>().unwrap();
+        assert_eq!(enum_carrier_bits_for_variant(inside_enum, 0), Ok(Some(42)));
+        assert_eq!(
+            enum_carrier_bits_for_variant(inside_enum, 1),
+            Ok(None),
+            "the untagged variant is a no-op even when its index is in the niche range"
+        );
+        drop(inside_ref);
+
+        let wrapping = unit_niche_enum(
+            &mut ctx,
+            (EnumCarrierKind::Integer, 128, 0),
+            u128::MAX,
+            0..=1,
+            0,
+            vec![1, 1],
+        );
+        let wrapping_ref = wrapping.deref(&ctx);
+        let wrapping_enum = wrapping_ref.downcast_ref::<MirEnumType>().unwrap();
+        assert_eq!(
+            enum_carrier_bits_for_variant(wrapping_enum, 1),
+            Ok(Some(0)),
+            "niche arithmetic must wrap across the full u128 carrier"
+        );
+    }
+}
diff --git a/crates/mir-lower/src/convert/ops/aggregate/enums.rs b/crates/mir-lower/src/convert/ops/aggregate/enums.rs
new file mode 100644
index 0000000000..99a33c080e
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/aggregate/enums.rs
@@ -0,0 +1,1704 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::common::{anyhow_to_pliron, byte_offset_gep, emit_integer_constant, spill_enum_value};
+use super::enum_layout::{
+    canonicalize_bool_value_bytes, coerce_enum_payload_storage, emit_carrier_constant,
+    enum_carrier_bits_for_variant,
+};
+use crate::convert::enum_payload_storage::enum_payload_storage_type;
+use crate::convert::types::{EnumSlotMap, build_enum_slot_map, convert_type, is_zero_sized_type};
+use dialect_mir::ops::{MirConstructEnumOp, MirEnumPayloadOp, MirSetDiscriminantOp};
+use dialect_mir::types::{EnumCarrierKind, EnumLayoutKind, MirEnumType};
+use llvm_export::attributes::{ICmpPredicateAttr, IntegerOverflowFlagsAttr};
+use llvm_export::op_interfaces::{
+    CastOpInterface, CastOpWithNNegInterface, IntBinArithOpWithOverflowFlag,
+};
+use llvm_export::ops as llvm;
+use llvm_export::types as llvm_types;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+
+/// Convert `mir.construct_enum` (e.g. `E::A(x)`) to LLVM operations.
+///
+/// Builds the enum value slot by slot, taking every index from
+/// [`build_enum_slot_map`] (indexes are never computed by hand here):
+///
+/// 1. Put the variant's declared discriminant VALUE into the tag slot.
+/// 2. `insertvalue` each payload field that owns a struct slot.
+/// 3. If some field has no slot (its bytes are shared with a
+///    different-typed field of another variant), finish through memory:
+///    copy the value to a stack slot, store that field at its byte
+///    position, and load the completed enum back.
+pub(crate) fn convert_construct_enum(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let (result_ty, operands, variant_index) = {
+        let mir_op = op.deref(ctx);
+        let result_ty = mir_op.get_result(0).get_type(ctx);
+        let operands: Vec<_> = mir_op.operands().collect();
+
+        let enum_op = MirConstructEnumOp::new(op);
+        let variant_index = enum_op
+            .get_attr_construct_enum_variant_index(ctx)
+            .map(|attr| attr.0 as usize)
+            .unwrap_or(0);
+
+        (result_ty, operands, variant_index)
+    };
+
+    let enum_ty: MirEnumType = {
+        let ty_ref = result_ty.deref(ctx);
+        match ty_ref.downcast_ref::<MirEnumType>() {
+            Some(e) => e.clone(),
+            None => {
+                return pliron::input_err_noloc!(
+                    "MirConstructEnumOp result type must be MirEnumType"
+                );
+            }
+        }
+    };
+
+    // Build the value as the SAME struct type the type converter
+    // produces everywhere else (block args, loads, allocas, ...). Taking
+    // both the type and the indices from one slot map is what keeps them
+    // in agreement. Filler slots are simply never written.
+    let slot_map = build_enum_slot_map(ctx, result_ty).map_err(anyhow_to_pliron)?;
+    let llvm_struct_ty = slot_map.llvm_struct_ty;
+
+    let undef_op = llvm::UndefOp::new(ctx, llvm_struct_ty);
+    rewriter.insert_operation(ctx, undef_op.get_operation());
+    let mut current_struct = undef_op.get_operation().deref(ctx).get_result(0);
+    let mut last_op = undef_op.get_operation();
+
+    if let Some(bits) = enum_carrier_bits_for_variant(&enum_ty, variant_index)
+        .map_err(|error| pliron::input_error_noloc!("MirConstructEnumOp: {error}"))?
+    {
+        let carrier_slot = slot_map.carrier_slot.ok_or_else(|| {
+            pliron::input_error_noloc!("MirConstructEnumOp requires a physical carrier slot")
+        })?;
+        let carrier_ty = slot_map.carrier_llvm_ty.ok_or_else(|| {
+            pliron::input_error_noloc!("MirConstructEnumOp requires a physical carrier type")
+        })?;
+        let carrier = emit_carrier_constant(ctx, rewriter, &enum_ty, carrier_ty, bits)?;
+        let insert = llvm::InsertValueOp::new(ctx, current_struct, carrier, vec![carrier_slot]);
+        rewriter.insert_operation(ctx, insert.get_operation());
+        current_struct = insert.get_operation().deref(ctx).get_result(0);
+        last_op = insert.get_operation();
+    }
+
+    let field_base: usize = enum_ty
+        .variant_field_counts
+        .iter()
+        .take(variant_index)
+        .map(|&c| c as usize)
+        .sum();
+
+    // Insert every payload field that owns a struct slot; remember the
+    // slotless ones for the memory pass below.
+    let mut deferred: Vec<(usize, Value)> = Vec::new();
+    for (i, operand) in operands.into_iter().enumerate() {
+        let flat = field_base + i;
+        let Some(slot) = slot_map.field_slots.get(flat) else {
+            return pliron::input_err_noloc!(
+                "MirConstructEnumOp field {} of variant {} is out of range for the enum's {} fields",
+                i,
+                variant_index,
+                slot_map.field_slots.len()
+            );
+        };
+        match slot {
+            Some(slot) => {
+                let storage_ty = {
+                    let storage_type = llvm_struct_ty.deref(ctx);
+                    let storage_struct = storage_type
+                        .downcast_ref::<llvm_types::StructType>()
+                        .ok_or_else(|| {
+                            pliron::input_error_noloc!(
+                                "MirConstructEnumOp physical storage is not an LLVM struct"
+                            )
+                        })?;
+                    let storage_slot = *slot as usize;
+                    if storage_slot >= storage_struct.num_fields() {
+                        return pliron::input_err_noloc!(
+                            "MirConstructEnumOp physical field slot {} is out of range",
+                            slot
+                        );
+                    }
+                    storage_struct.field_type(storage_slot)
+                };
+                let stored_operand =
+                    coerce_enum_payload_storage(ctx, rewriter, operand, storage_ty)?;
+                let insert_op =
+                    llvm::InsertValueOp::new(ctx, current_struct, stored_operand, vec![*slot]);
+                rewriter.insert_operation(ctx, insert_op.get_operation());
+                current_struct = insert_op.get_operation().deref(ctx).get_result(0);
+                last_op = insert_op.get_operation();
+            }
+            None => {
+                // Zero-sized fields own no bytes; nothing to write.
+                if is_zero_sized_type(ctx, slot_map.field_llvm_types[flat]) {
+                    continue;
+                }
+                deferred.push((flat, operand));
+            }
+        }
+    }
+
+    if deferred.is_empty() {
+        rewriter.replace_operation(ctx, op, last_op);
+        return Ok(());
+    }
+
+    // Slotless fields: copy the half-built value to the stack, write
+    // each remaining payload at its byte position, and load the finished
+    // enum back as the result.
+    let abi_align = enum_ty.abi_align();
+    let slot_ptr = spill_enum_value(ctx, rewriter, current_struct, llvm_struct_ty, abi_align);
+    for (flat, operand) in deferred {
+        let field_ptr = byte_offset_gep(ctx, rewriter, slot_ptr, slot_map.field_offsets[flat]);
+        // `bool` is an LLVM i1 as a value but occupies one full byte in
+        // Rust memory. Enum storage claims the byte-faithful twin of every
+        // bool-bearing payload (scalar i8 byte, or an aggregate with each
+        // i1 leaf widened to i8), so canonicalize the stored value to that
+        // twin: every physical bool byte becomes an unambiguous 0 or 1.
+        let semantic_ty = slot_map.field_llvm_types[flat];
+        let storage_ty = enum_payload_storage_type(ctx, semantic_ty).map_err(anyhow_to_pliron)?;
+        let canonical_operand = canonicalize_bool_value_bytes(ctx, rewriter, operand)?;
+        let stored_operand =
+            coerce_enum_payload_storage(ctx, rewriter, canonical_operand, storage_ty)?;
+        let store_op = llvm::StoreOp::new(ctx, stored_operand, field_ptr);
+        rewriter.insert_operation(ctx, store_op.get_operation());
+    }
+    let load_op = llvm::LoadOp::new(ctx, slot_ptr, llvm_struct_ty);
+    rewriter.insert_operation(ctx, load_op.get_operation());
+    if abi_align > 0 {
+        llvm_export::ops::set_op_alignment(ctx, load_op.get_operation(), abi_align as u32);
+    }
+    rewriter.replace_operation(ctx, op, load_op.get_operation());
+
+    Ok(())
+}
+
+/// Get the slot map for an enum operand.
+///
+/// By the time an op is converted, its operand's type has already been
+/// rewritten to the LLVM struct, so we look up the ORIGINAL `MirEnumType`
+/// the framework recorded for it and rebuild the map from that. Also
+/// returns the enum's rustc alignment, which spill slots need.
+fn enum_slot_map_of_operand(
+    ctx: &mut Context,
+    operands_info: &OperandsInfo,
+    enum_val: Value,
+) -> Result<(EnumSlotMap, u64)> {
+    // Clone the type data out so the `Ref` borrow of `ctx` ends before
+    // re-interning (types are hash-consed: registering an equal instance
+    // returns the existing pointer).
+    let enum_ty: MirEnumType = {
+        match operands_info.lookup_most_recent_of_type::<MirEnumType>(ctx, enum_val) {
+            Some(r) => r.clone(),
+            None => {
+                return pliron::input_err_noloc!("Expected MirEnumType for enum value access");
+            }
+        }
+    };
+    let abi_align = enum_ty.abi_align();
+    let mir_ty: TypeHandle = pliron::r#type::Type::instantiate(enum_ty, ctx).into();
+    let map = build_enum_slot_map(ctx, mir_ty).map_err(anyhow_to_pliron)?;
+    Ok((map, abi_align))
+}
+
+/// Convert `mir.set_discriminant` to the one physical carrier write rustc's
+/// layout requires. Direct layouts write the declared discriminant; Niche
+/// layouts write wrapping `niche_start + range_offset`. Selecting the
+/// untagged Niche variant or an inhabited Single variant is a no-op.
+///
+/// The enum layout comes from the op's own `set_discriminant_enum_ty`
+/// attribute, stamped at build time. Operand type history is not usable
+/// here: a kind-only `mir.cast` lowers to a plain value forwarding, history
+/// does not follow that edge, and a stale hit would write the tag at the
+/// wrong offset.
+pub(crate) fn convert_set_discriminant(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let enum_ptr = op.deref(ctx).get_operand(0);
+    let target = MirSetDiscriminantOp::new(op)
+        .get_attr_set_discriminant_variant_index(ctx)
+        .map(|attr| attr.0 as usize)
+        .ok_or_else(|| {
+            pliron::input_error_noloc!(
+                "MirSetDiscriminantOp missing set_discriminant_variant_index"
+            )
+        })?;
+
+    let enum_ty: MirEnumType = {
+        let stamped_ty = MirSetDiscriminantOp::new(op)
+            .get_attr_set_discriminant_enum_ty(ctx)
+            .map(|attr| attr.get_type(ctx))
+            .ok_or_else(|| {
+                pliron::input_error_noloc!(
+                    "mir.set_discriminant missing enum type attribute; \
+                     discriminant write has no fact to derive from"
+                )
+            })?;
+        match stamped_ty.deref(ctx).downcast_ref::<MirEnumType>() {
+            Some(et) => et.clone(),
+            None => {
+                return pliron::input_err_noloc!(
+                    "mir.set_discriminant enum type attribute must be an enum type"
+                );
+            }
+        }
+    };
+
+    let Some(bits) = enum_carrier_bits_for_variant(&enum_ty, target)
+        .map_err(|error| pliron::input_error_noloc!("MirSetDiscriminantOp: {error}"))?
+    else {
+        rewriter.erase_operation(ctx, op);
+        return Ok(());
+    };
+
+    let tag_offset = enum_ty.tag_offset();
+    let mir_ty: TypeHandle = pliron::r#type::Type::instantiate(enum_ty.clone(), ctx).into();
+    let slot_map = build_enum_slot_map(ctx, mir_ty).map_err(anyhow_to_pliron)?;
+    let carrier_ty = slot_map.carrier_llvm_ty.ok_or_else(|| {
+        pliron::input_error_noloc!("MirSetDiscriminantOp physical write has no carrier type")
+    })?;
+    let carrier = emit_carrier_constant(ctx, rewriter, &enum_ty, carrier_ty, bits)?;
+    let carrier_ptr = byte_offset_gep(ctx, rewriter, enum_ptr, tag_offset);
+    let store_op = llvm::StoreOp::new(ctx, carrier, carrier_ptr);
+    rewriter.insert_operation(ctx, store_op.get_operation());
+
+    rewriter.erase_operation(ctx, op);
+    Ok(())
+}
+
+/// Convert `mir.get_discriminant` (reading which variant is alive) to
+/// `llvm.extractvalue`.
+///
+/// Direct layouts read the tag from the slot map's carrier slot. Niche
+/// layouts decode rustc's wrapping carrier range; Single layouts materialize
+/// their one logical discriminant as a constant. No slot number is assumed.
+pub(crate) fn convert_get_discriminant(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    let enum_val = match op.deref(ctx).operands().next() {
+        Some(v) => v,
+        None => return pliron::input_err_noloc!("MirGetDiscriminantOp requires an operand"),
+    };
+
+    let enum_ty: MirEnumType = operands_info
+        .lookup_most_recent_of_type::<MirEnumType>(ctx, enum_val)
+        .map(|ty| ty.clone())
+        .ok_or_else(|| pliron::input_error_noloc!("Expected MirEnumType for discriminant read"))?;
+    let mir_ty: TypeHandle = pliron::r#type::Type::instantiate(enum_ty.clone(), ctx).into();
+    let slot_map = build_enum_slot_map(ctx, mir_ty).map_err(anyhow_to_pliron)?;
+    let logical_ty = convert_type(ctx, enum_ty.discriminant_ty).map_err(anyhow_to_pliron)?;
+    let logical_width = logical_ty
+        .deref(ctx)
+        .downcast_ref::<IntegerType>()
+        .map(IntegerType::width)
+        .ok_or_else(|| {
+            pliron::input_error_noloc!("MirGetDiscriminantOp logical result must be integer")
+        })?;
+
+    let result = match enum_ty.layout_kind {
+        EnumLayoutKind::Direct => {
+            let slot = slot_map.carrier_slot.ok_or_else(|| {
+                pliron::input_error_noloc!("Direct enum has no physical carrier slot")
+            })?;
+            let extract = llvm::ExtractValueOp::new(ctx, enum_val, vec![slot])?;
+            rewriter.insert_operation(ctx, extract.get_operation());
+            extract.get_operation().deref(ctx).get_result(0)
+        }
+        EnumLayoutKind::Single => {
+            if enum_ty.variant_is_inhabited(enum_ty.single_variant as usize) != Some(true) {
+                return pliron::input_err_noloc!(
+                    "Cannot read discriminant of an uninhabited single-variant enum"
+                );
+            }
+            let value = *enum_ty
+                .variant_discriminants
+                .get(enum_ty.single_variant as usize)
+                .ok_or_else(|| {
+                    pliron::input_error_noloc!("Single enum has no declared discriminant")
+                })?;
+            emit_integer_constant(ctx, rewriter, logical_width, u128::from(value))
+        }
+        EnumLayoutKind::Niche => {
+            let slot = slot_map.carrier_slot.ok_or_else(|| {
+                pliron::input_error_noloc!("Niche enum has no physical carrier slot")
+            })?;
+            let extract = llvm::ExtractValueOp::new(ctx, enum_val, vec![slot])?;
+            rewriter.insert_operation(ctx, extract.get_operation());
+            let carrier = extract.get_operation().deref(ctx).get_result(0);
+            let carrier_int_ty: TypeHandle =
+                IntegerType::get(ctx, enum_ty.carrier_width, Signedness::Signless).into();
+            let carrier_int = if enum_ty.carrier_kind == EnumCarrierKind::Pointer {
+                let cast = llvm::PtrToIntOp::new(ctx, carrier, carrier_int_ty);
+                rewriter.insert_operation(ctx, cast.get_operation());
+                cast.get_operation().deref(ctx).get_result(0)
+            } else {
+                carrier
+            };
+
+            let niche_start =
+                emit_integer_constant(ctx, rewriter, enum_ty.carrier_width, enum_ty.niche_start());
+            let relative = llvm::SubOp::new_with_overflow_flag(
+                ctx,
+                carrier_int,
+                niche_start,
+                IntegerOverflowFlagsAttr::default(),
+            )
+            .get_operation();
+            rewriter.insert_operation(ctx, relative);
+            let relative_val = relative.deref(ctx).get_result(0);
+            let max = emit_integer_constant(
+                ctx,
+                rewriter,
+                enum_ty.carrier_width,
+                u128::from(enum_ty.niche_variant_end - enum_ty.niche_variant_start),
+            );
+            let in_range =
+                llvm::ICmpOp::new(ctx, ICmpPredicateAttr::ULE, relative_val, max).get_operation();
+            rewriter.insert_operation(ctx, in_range);
+            // The range test is carrier-width wrapping arithmetic, exactly
+            // like rustc. Variant indices themselves live at the logical
+            // discriminant width: the start index may be larger than the
+            // carrier can represent (e.g. variants 298..=299 in an i8 niche).
+            let logical_relative = match enum_ty.carrier_width.cmp(&logical_width) {
+                std::cmp::Ordering::Equal => relative_val,
+                std::cmp::Ordering::Greater => {
+                    let cast = llvm::TruncOp::new(ctx, relative_val, logical_ty).get_operation();
+                    rewriter.insert_operation(ctx, cast);
+                    cast.deref(ctx).get_result(0)
+                }
+                std::cmp::Ordering::Less => {
+                    // LLVM's zext op requires its explicit `nneg` flag even
+                    // when the flag is false. Niche decoding is ordinary
+                    // unsigned extension, so it must never claim nneg.
+                    let cast = llvm::ZExtOp::new_with_nneg(ctx, relative_val, logical_ty, false)
+                        .get_operation();
+                    rewriter.insert_operation(ctx, cast);
+                    cast.deref(ctx).get_result(0)
+                }
+            };
+            let niche_base = emit_integer_constant(
+                ctx,
+                rewriter,
+                logical_width,
+                u128::from(enum_ty.niche_variant_start),
+            );
+            let niche_variant = llvm::AddOp::new_with_overflow_flag(
+                ctx,
+                logical_relative,
+                niche_base,
+                IntegerOverflowFlagsAttr::default(),
+            )
+            .get_operation();
+            rewriter.insert_operation(ctx, niche_variant);
+            let untagged = emit_integer_constant(
+                ctx,
+                rewriter,
+                logical_width,
+                u128::from(enum_ty.untagged_variant),
+            );
+            let in_range_value = in_range.deref(ctx).get_result(0);
+            let niche_variant_value = niche_variant.deref(ctx).get_result(0);
+            let select = llvm::SelectOp::new(ctx, in_range_value, niche_variant_value, untagged)
+                .get_operation();
+            rewriter.insert_operation(ctx, select);
+            select.deref(ctx).get_result(0)
+        }
+        EnumLayoutKind::Empty => {
+            return pliron::input_err_noloc!("Cannot read discriminant of uninhabited enum");
+        }
+        _ => {
+            return pliron::input_err_noloc!(
+                "Cannot read discriminant of enum with unknown physical layout"
+            );
+        }
+    };
+
+    rewriter.replace_operation_with_values(ctx, op, vec![result]);
+
+    Ok(())
+}
+
+/// Convert `mir.enum_payload` (reading a variant's field, e.g. the `x`
+/// in `E::A(x) => x`) to a payload-field read.
+///
+/// Three cases, decided by the [`EnumSlotMap`]:
+///
+/// - The field owns a struct slot: a plain `llvm.extractvalue`.
+/// - The field has no slot (its bytes are shared with a different-typed
+///   field of another variant): go through memory. Copy the enum to a
+///   stack slot, point at the field's byte position, and load it with
+///   its own type. Same trick as
+///   [`convert_extract_array_element`](super::array_extract::convert_extract_array_element),
+///   and
+///   it avoids LLVM `bitcast` entirely.
+/// - The field is zero-sized: there is nothing to read; produce `undef`.
+pub(crate) fn convert_enum_payload(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    let enum_val = match op.deref(ctx).operands().next() {
+        Some(v) => v,
+        None => return pliron::input_err_noloc!("MirEnumPayloadOp requires an operand"),
+    };
+
+    let payload_op = MirEnumPayloadOp::new(op);
+    let variant_index = payload_op
+        .get_attr_payload_variant_index(ctx)
+        .map(|attr| attr.0 as usize)
+        .unwrap_or(0);
+    let field_index = payload_op
+        .get_attr_payload_field_index(ctx)
+        .map(|attr| attr.0 as usize)
+        .unwrap_or(0);
+
+    let variant_field_counts = {
+        match operands_info.lookup_most_recent_of_type::<MirEnumType>(ctx, enum_val) {
+            Some(r) => r.variant_field_counts.clone(),
+            None => {
+                return pliron::input_err_noloc!(
+                    "Expected MirEnumType for enum payload extraction"
+                );
+            }
+        }
+    };
+    let (slot_map, abi_align) = enum_slot_map_of_operand(ctx, operands_info, enum_val)?;
+
+    let field_base: usize = variant_field_counts
+        .iter()
+        .take(variant_index)
+        .map(|&c| c as usize)
+        .sum();
+    let flat = field_base + field_index;
+    let Some(slot) = slot_map.field_slots.get(flat).copied() else {
+        return pliron::input_err_noloc!(
+            "MirEnumPayloadOp field {} of variant {} is out of range for the enum's {} fields",
+            field_index,
+            variant_index,
+            slot_map.field_slots.len()
+        );
+    };
+
+    match slot {
+        Some(slot) => {
+            let extract_op = llvm::ExtractValueOp::new(ctx, enum_val, vec![slot])?;
+            rewriter.insert_operation(ctx, extract_op.get_operation());
+            let extracted = extract_op.get_operation().deref(ctx).get_result(0);
+            let semantic_value = coerce_enum_payload_storage(
+                ctx,
+                rewriter,
+                extracted,
+                slot_map.field_llvm_types[flat],
+            )?;
+            rewriter.replace_operation_with_values(ctx, op, vec![semantic_value]);
+        }
+        None if is_zero_sized_type(ctx, slot_map.field_llvm_types[flat]) => {
+            let undef_op = llvm::UndefOp::new(ctx, slot_map.field_llvm_types[flat]);
+            rewriter.insert_operation(ctx, undef_op.get_operation());
+            rewriter.replace_operation(ctx, op, undef_op.get_operation());
+        }
+        None => {
+            let slot_ptr =
+                spill_enum_value(ctx, rewriter, enum_val, slot_map.llvm_struct_ty, abi_align);
+            let field_ptr = byte_offset_gep(ctx, rewriter, slot_ptr, slot_map.field_offsets[flat]);
+            let semantic_ty = slot_map.field_llvm_types[flat];
+            let storage_ty =
+                enum_payload_storage_type(ctx, semantic_ty).map_err(anyhow_to_pliron)?;
+            let load_op = llvm::LoadOp::new(ctx, field_ptr, storage_ty);
+            rewriter.insert_operation(ctx, load_op.get_operation());
+            let stored = load_op.get_operation().deref(ctx).get_result(0);
+            let semantic = coerce_enum_payload_storage(ctx, rewriter, stored, semantic_ty)?;
+            rewriter.replace_operation_with_values(ctx, op, vec![semantic]);
+        }
+    }
+
+    Ok(())
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production minting lives in mir-importer's facts.rs.
+#[allow(clippy::disallowed_methods)]
+mod tests {
+    use super::*;
+    use crate::convert::ops::test_util::*;
+    use dialect_mir::attributes::{FieldIndexAttr, MirCastKindAttr, VariantIndexAttr};
+    use dialect_mir::ops as mir;
+    use dialect_mir::types::{
+        EnumEncoding, EnumVariant, MirArrayType, MirPtrType, MirStructType, MirTupleType,
+    };
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::common_traits::Verify;
+
+    use super::super::test_support::*;
+
+    /// Enum construction must store the declared discriminant value, not the
+    /// variant index. This locks the `Ordering::Less = -1` style case as the
+    /// i8 bit-pattern `255`.
+    #[test]
+    fn construct_enum_uses_declared_discriminant_not_variant_index() {
+        let mut ctx = make_ctx();
+
+        let discr_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signed).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "OrderingLike".to_string(),
+            discr_ty,
+            vec![255, 0, 1],
+            vec![
+                EnumVariant::unit("Less".to_string()),
+                EnumVariant::unit("Equal".to_string()),
+                EnumVariant::unit("Greater".to_string()),
+            ],
+            0,
+            1,
+            1,
+        )
+        .into();
+
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+
+        let op = Operation::new(
+            &mut ctx,
+            MirConstructEnumOp::get_concrete_op_info(),
+            vec![enum_ty],
+            vec![],
+            vec![],
+            0,
+        );
+        MirConstructEnumOp::new(op)
+            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
+        op.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+        let inserts = find_all::<llvm::InsertValueOp>(&ctx, &body);
+
+        assert_eq!(
+            insert_indices(&ctx, &inserts),
+            vec![vec![0]],
+            "unit enum construction should insert only the discriminant tag"
+        );
+        let tag_insert = &inserts[0];
+        assert!(
+            tag_insert.verify(&ctx).is_ok(),
+            "the enum tag insertion must satisfy LLVM dialect verification"
+        );
+        let tag = tag_insert.get_operation().deref(&ctx).get_operand(1);
+        let tag_def = tag
+            .defining_op()
+            .expect("the inserted enum tag must have a defining operation");
+        let tag_constant = Operation::get_op::<llvm::ConstantOp>(tag_def, &ctx)
+            .expect("the inserted enum tag must be defined by llvm.constant");
+        let tag_attr = tag_constant.get_value(&ctx);
+        let tag_integer = tag_attr
+            .downcast_ref::<IntegerAttr>()
+            .expect("the inserted enum tag must be an integer constant");
+        assert_eq!(tag_integer.value().bw(), 8, "the enum tag must be 8-bit");
+        assert_eq!(
+            tag_integer.value().to_u64(),
+            255,
+            "Less must lower to its declared i8 bit-pattern 255, not variant index 0"
+        );
+    }
+
+    #[test]
+    fn nested_pointer_niche_tuple_construct_extract_and_discriminant_lower() {
+        let mut ctx = make_ctx();
+        let logical: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
+        let index: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
+        let tuple_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![index, pointer]).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "Option".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![tuple_ty], vec![0], vec![16]),
+            ],
+            EnumEncoding {
+                tag_offset: 8,
+                total_size: 16,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        let slot_map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(slot_map.carrier_slot, Some(1));
+        assert_eq!(slot_map.field_slots, vec![None]);
+        let lowered_tuple = convert_type(&mut ctx, tuple_ty).unwrap();
+
+        let (module, block) = build_kernel(&mut ctx, vec![index, pointer], vec![]);
+        let index_value = block.deref(&ctx).get_argument(0);
+        let pointer_value = block.deref(&ctx).get_argument(1);
+        let tuple = Operation::new(
+            &mut ctx,
+            mir::MirConstructTupleOp::get_concrete_op_info(),
+            vec![tuple_ty],
+            vec![index_value, pointer_value],
+            vec![],
+            0,
+        );
+        tuple.insert_at_back(block, &ctx);
+        let tuple_value = tuple.deref(&ctx).get_result(0);
+
+        let construct = Operation::new(
+            &mut ctx,
+            mir::MirConstructEnumOp::get_concrete_op_info(),
+            vec![enum_ty],
+            vec![tuple_value],
+            vec![],
+            0,
+        );
+        mir::MirConstructEnumOp::new(construct)
+            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
+        construct.insert_at_back(block, &ctx);
+        let enum_value = construct.deref(&ctx).get_result(0);
+
+        let payload = Operation::new(
+            &mut ctx,
+            mir::MirEnumPayloadOp::get_concrete_op_info(),
+            vec![tuple_ty],
+            vec![enum_value],
+            vec![],
+            0,
+        );
+        mir::MirEnumPayloadOp::new(payload)
+            .set_attr_payload_variant_index(&ctx, VariantIndexAttr(1));
+        mir::MirEnumPayloadOp::new(payload).set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
+        payload.insert_at_back(block, &ctx);
+
+        let discriminant = Operation::new(
+            &mut ctx,
+            mir::MirGetDiscriminantOp::get_concrete_op_info(),
+            vec![logical],
+            vec![enum_value],
+            vec![],
+            0,
+        );
+        discriminant.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(
+            count_ops::<llvm::IntToPtrOp>(&ctx, &body),
+            0,
+            "constructing the untagged Some payload must not recreate its pointer from bits"
+        );
+        assert_eq!(
+            count_ops::<llvm::PtrToIntOp>(&ctx, &body),
+            1,
+            "reading the pointer niche should inspect the carrier exactly once"
+        );
+        assert_eq!(
+            count_ops::<llvm::StoreOp>(&ctx, &body),
+            3,
+            "construction and extraction should each spill the enum, plus one tuple payload store"
+        );
+        assert_eq!(
+            count_ops::<llvm::LoadOp>(&ctx, &body),
+            2,
+            "construction should reload the enum and extraction should load the tuple payload"
+        );
+        // What this test is about is that the payload moves as one unit, never
+        // field by field. Assert that property directly instead of counting
+        // whole-aggregate accesses.
+        //
+        // Counting was the fragile form. The enum's physical storage here is
+        // `{i64, ptr}` -- the *same interned type* as the lowered payload tuple,
+        // since the niche carrier claims the pointer at byte 8 and the 8 bytes
+        // below it become one `i64` filler. So a count of `lowered_tuple`-typed
+        // accesses cannot separate the payload write from the enum spill, and
+        // the expected numbers move whenever that coincidence appears or
+        // disappears -- which has nothing to do with the property under test.
+        //
+        // A lowering that decomposed the payload is recognisable by what it
+        // emits instead: traffic in the tuple's *field* types. Look for that,
+        // and the assertion holds whatever the enum storage type happens to be.
+        let field_tys: Vec<TypeHandle> = lowered_tuple
+            .deref(&ctx)
+            .downcast_ref::<llvm_types::StructType>()
+            .expect("the lowered tuple is an LLVM struct")
+            .fields()
+            .collect();
+
+        let store_tys: Vec<TypeHandle> = find_all::<llvm::StoreOp>(&ctx, &body)
+            .iter()
+            .map(|store| store.get_operand_value(&ctx).get_type(&ctx))
+            .collect();
+        let load_tys: Vec<TypeHandle> = find_all::<llvm::LoadOp>(&ctx, &body)
+            .iter()
+            .map(|load| {
+                load.get_operation()
+                    .deref(&ctx)
+                    .get_result(0)
+                    .get_type(&ctx)
+            })
+            .collect();
+
+        let describe = |tys: &[TypeHandle]| -> Vec<String> {
+            tys.iter()
+                .filter(|ty| field_tys.contains(ty))
+                .map(|ty| ty.deref(&ctx).disp(&ctx).to_string())
+                .collect()
+        };
+        assert!(
+            describe(&store_tys).is_empty(),
+            "the payload must be stored whole, but these field-typed stores appear: {:?}",
+            describe(&store_tys)
+        );
+        assert!(
+            describe(&load_tys).is_empty(),
+            "the payload must be read whole, but these field-typed loads appear: {:?}",
+            describe(&load_tys)
+        );
+
+        // And it must actually be moved: without this the checks above would
+        // also pass a lowering that emitted no payload traffic at all.
+        assert!(
+            store_tys.contains(&lowered_tuple),
+            "at least one store must move the complete {{i64, ptr}} payload"
+        );
+        assert!(
+            load_tys.contains(&lowered_tuple),
+            "at least one load must read the complete {{i64, ptr}} payload"
+        );
+    }
+
+    /// SetDiscriminant must use the slot map instead of assuming that the tag
+    /// is field zero, and its GEP must retain the source pointer's GPU address
+    /// space. This shape puts an i64 payload first and an i8 tag above the
+    /// u32 range, proving the byte GEP does not truncate offsets to u32.
+    #[test]
+    fn set_discriminant_uses_tag_slot_and_preserves_shared_address_space() {
+        use llvm_export::ops::GepIndex;
+        use llvm_export::types::{PointerType, address_space};
+
+        let mut ctx = make_ctx();
+        let discr_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let payload_a: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let payload_b: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+        let tag_offset = u64::from(u32::MAX) + 1;
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "TagAfterPayload".to_string(),
+            discr_ty,
+            vec![3, 7],
+            vec![
+                EnumVariant::new_with_layout("A".to_string(), vec![payload_a], vec![0], vec![8]),
+                EnumVariant::new_with_layout("B".to_string(), vec![payload_b], vec![0], vec![8]),
+            ],
+            tag_offset,
+            tag_offset + 8,
+            8,
+        )
+        .into();
+        let ptr_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, enum_ty, true).into();
+
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty], vec![]);
+        let enum_ptr = block.deref(&ctx).get_argument(0);
+        let set = Operation::new(
+            &mut ctx,
+            mir::MirSetDiscriminantOp::get_concrete_op_info(),
+            vec![],
+            vec![enum_ptr],
+            vec![],
+            0,
+        );
+        let set_op = mir::MirSetDiscriminantOp::new(set);
+        set_op.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(1));
+        set_op.set_attr_set_discriminant_enum_ty(
+            &ctx,
+            pliron::builtin::attributes::TypeAttr::new(enum_ty),
+        );
+        set.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+        assert_eq!(count_ops::<mir::MirSetDiscriminantOp>(&ctx, &body), 0);
+        assert_eq!(count_ops::<llvm::GetElementPtrOp>(&ctx, &body), 1);
+        assert_eq!(count_ops::<llvm::StoreOp>(&ctx, &body), 1);
+
+        let gep = find_first::<llvm::GetElementPtrOp>(&ctx, &body).unwrap();
+        let indices = gep.indices(&ctx);
+        assert!(matches!(indices.as_slice(), [GepIndex::Value(_)]));
+        let GepIndex::Value(offset) = indices[0] else {
+            unreachable!()
+        };
+        let offset_def = offset.defining_op().expect("byte offset must be constant");
+        let offset_constant = Operation::get_op::<llvm::ConstantOp>(offset_def, &ctx)
+            .expect("byte offset must be an LLVM constant");
+        let offset_attr = offset_constant.get_value(&ctx);
+        assert_eq!(
+            offset_attr
+                .downcast_ref::<IntegerAttr>()
+                .expect("byte offset must be integer")
+                .value()
+                .to_u64(),
+            tag_offset,
+            "the write must use rustc's absolute carrier byte offset"
+        );
+        let gep_result_ty = gep.get_operation().deref(&ctx).get_result(0).get_type(&ctx);
+        assert_eq!(
+            gep_result_ty
+                .deref(&ctx)
+                .downcast_ref::<PointerType>()
+                .expect("GEP result must be a pointer")
+                .address_space(),
+            address_space::SHARED,
+            "tag GEP must preserve shared address space"
+        );
+
+        let store = find_first::<llvm::StoreOp>(&ctx, &body).unwrap();
+        let stored_ty = store.get_operand_value(&ctx).get_type(&ctx);
+        assert_eq!(
+            stored_ty
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .expect("stored tag must be an integer")
+                .width(),
+            8
+        );
+        assert_eq!(
+            store.get_operand_address(&ctx),
+            gep.get_operation().deref(&ctx).get_result(0),
+            "the store must use the tag GEP result"
+        );
+    }
+
+    #[test]
+    fn set_discriminant_niche_writes_only_tagged_variant_carrier() {
+        for (target, expected_stores) in [(0, 1), (1, 0)] {
+            let mut ctx = make_ctx();
+            let enum_ty = unit_niche_enum(
+                &mut ctx,
+                (EnumCarrierKind::Integer, 8, 0),
+                0,
+                0..=0,
+                1,
+                vec![1, 1],
+            );
+            let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, true).into();
+            let (module, block) = build_kernel(&mut ctx, vec![ptr_ty], vec![]);
+            let ptr = block.deref(&ctx).get_argument(0);
+            let set = Operation::new(
+                &mut ctx,
+                mir::MirSetDiscriminantOp::get_concrete_op_info(),
+                vec![],
+                vec![ptr],
+                vec![],
+                0,
+            );
+            let set_op = mir::MirSetDiscriminantOp::new(set);
+            set_op.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(target));
+            set_op.set_attr_set_discriminant_enum_ty(
+                &ctx,
+                pliron::builtin::attributes::TypeAttr::new(enum_ty),
+            );
+            set.insert_at_back(block, &ctx);
+            append_mir_return(&mut ctx, block, vec![]);
+
+            crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+            let body = kernel_blocks(&ctx, module);
+            assert_eq!(count_ops::<llvm::StoreOp>(&ctx, &body), expected_stores);
+            assert_eq!(count_ops::<mir::MirSetDiscriminantOp>(&ctx, &body), 0);
+        }
+    }
+
+    #[test]
+    fn shared_pointer_niche_carrier_rejects_target_dependent_width() {
+        let mut ctx = make_ctx();
+        let enum_ty = unit_niche_enum(
+            &mut ctx,
+            (EnumCarrierKind::Pointer, 64, 3),
+            0,
+            0..=0,
+            1,
+            vec![1, 1],
+        );
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("shared pointer carrier must reject");
+        assert!(
+            error.to_string().contains("target-mode dependent"),
+            "{error}"
+        );
+    }
+
+    #[test]
+    fn shared_pointer_niche_payload_round_trips_through_generic_storage() {
+        let mut ctx = make_ctx();
+        let logical: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
+        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, true).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "OptionShared".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![shared], vec![0], vec![8]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 8,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                carrier_address_space: llvm_types::address_space::GENERIC,
+                niche_start: 0,
+                niche_variant_start: 0,
+                niche_variant_end: 0,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![shared], vec![shared]);
+        let pointer = block.deref(&ctx).get_argument(0);
+        let construct = Operation::new(
+            &mut ctx,
+            MirConstructEnumOp::get_concrete_op_info(),
+            vec![enum_ty],
+            vec![pointer],
+            vec![],
+            0,
+        );
+        MirConstructEnumOp::new(construct)
+            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
+        construct.insert_at_back(block, &ctx);
+        let option = construct.deref(&ctx).get_result(0);
+
+        let discriminant = Operation::new(
+            &mut ctx,
+            mir::MirGetDiscriminantOp::get_concrete_op_info(),
+            vec![logical],
+            vec![option],
+            vec![],
+            0,
+        );
+        discriminant.insert_at_back(block, &ctx);
+
+        let payload = Operation::new(
+            &mut ctx,
+            MirEnumPayloadOp::get_concrete_op_info(),
+            vec![shared],
+            vec![option],
+            vec![],
+            0,
+        );
+        let payload_op = MirEnumPayloadOp::new(payload);
+        payload_op.set_attr_payload_variant_index(&ctx, VariantIndexAttr(1));
+        payload_op.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
+        payload.insert_at_back(block, &ctx);
+        let result = payload.deref(&ctx).get_result(0);
+        append_mir_return(&mut ctx, block, vec![result]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(
+            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
+            2,
+            "construction must genericize the pointer and extraction must restore shared space"
+        );
+        assert_eq!(
+            count_ops::<llvm::PtrToIntOp>(&ctx, &body),
+            1,
+            "niche discrimination must inspect the generic pointer carrier"
+        );
+        assert_eq!(count_ops::<MirConstructEnumOp>(&ctx, &body), 0);
+        assert_eq!(count_ops::<MirEnumPayloadOp>(&ctx, &body), 0);
+    }
+
+    #[test]
+    fn nested_shared_pointer_payload_round_trips_through_recursive_storage() {
+        let mut ctx = make_ctx();
+        let logical: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, true).into();
+        let inner: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "SharedPointerInner".into(),
+            vec!["pointer".into(), "cookie".into()],
+            vec![shared, logical],
+            vec![0, 1],
+            vec![0, 8],
+            16,
+            8,
+        )
+        .into();
+        let outer: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "SharedPointerOuter".into(),
+            vec!["inner".into(), "guard".into()],
+            vec![inner, logical],
+            vec![0, 1],
+            vec![0, 16],
+            24,
+            8,
+        )
+        .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "NestedSharedPointer".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![outer], vec![8], vec![24]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 32,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Direct,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 32,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![outer], vec![outer]);
+        let wrapper = block.deref(&ctx).get_argument(0);
+        let construct = Operation::new(
+            &mut ctx,
+            MirConstructEnumOp::get_concrete_op_info(),
+            vec![enum_ty],
+            vec![wrapper],
+            vec![],
+            0,
+        );
+        MirConstructEnumOp::new(construct)
+            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
+        construct.insert_at_back(block, &ctx);
+        let option = construct.deref(&ctx).get_result(0);
+
+        let payload = Operation::new(
+            &mut ctx,
+            MirEnumPayloadOp::get_concrete_op_info(),
+            vec![outer],
+            vec![option],
+            vec![],
+            0,
+        );
+        let payload_op = MirEnumPayloadOp::new(payload);
+        payload_op.set_attr_payload_variant_index(&ctx, VariantIndexAttr(1));
+        payload_op.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
+        payload.insert_at_back(block, &ctx);
+        let result = payload.deref(&ctx).get_result(0);
+        append_mir_return(&mut ctx, block, vec![result]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(
+            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
+            2,
+            "construction and extraction must cast the nested shared pointer leaf"
+        );
+        assert_eq!(count_ops::<MirConstructEnumOp>(&ctx, &body), 0);
+        assert_eq!(count_ops::<MirEnumPayloadOp>(&ctx, &body), 0);
+    }
+
+    #[test]
+    fn bounded_shared_pointer_array_niche_payload_round_trips_through_recursive_storage() {
+        let mut ctx = make_ctx();
+        let logical: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
+        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, true).into();
+        let pointers: TypeHandle = MirArrayType::get(&mut ctx, shared, 2).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "OptionSharedPointerArray".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![pointers], vec![0], vec![16]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 16,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                carrier_address_space: llvm_types::address_space::GENERIC,
+                niche_start: 0,
+                niche_variant_start: 0,
+                niche_variant_end: 0,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let (module, block) = build_kernel(&mut ctx, vec![pointers], vec![pointers]);
+        let array = block.deref(&ctx).get_argument(0);
+        let construct = Operation::new(
+            &mut ctx,
+            MirConstructEnumOp::get_concrete_op_info(),
+            vec![enum_ty],
+            vec![array],
+            vec![],
+            0,
+        );
+        MirConstructEnumOp::new(construct)
+            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
+        construct.insert_at_back(block, &ctx);
+        let option = construct.deref(&ctx).get_result(0);
+
+        let discriminant = Operation::new(
+            &mut ctx,
+            mir::MirGetDiscriminantOp::get_concrete_op_info(),
+            vec![logical],
+            vec![option],
+            vec![],
+            0,
+        );
+        discriminant.insert_at_back(block, &ctx);
+
+        let payload = Operation::new(
+            &mut ctx,
+            MirEnumPayloadOp::get_concrete_op_info(),
+            vec![pointers],
+            vec![option],
+            vec![],
+            0,
+        );
+        let payload_op = MirEnumPayloadOp::new(payload);
+        payload_op.set_attr_payload_variant_index(&ctx, VariantIndexAttr(1));
+        payload_op.set_attr_payload_field_index(&ctx, FieldIndexAttr(0));
+        payload.insert_at_back(block, &ctx);
+        let result = payload.deref(&ctx).get_result(0);
+        append_mir_return(&mut ctx, block, vec![result]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(
+            count_ops::<llvm::AddrSpaceCastOp>(&ctx, &body),
+            4,
+            "construction and extraction must cast both shared-pointer array elements"
+        );
+        assert_eq!(
+            count_ops::<llvm::PtrToIntOp>(&ctx, &body),
+            1,
+            "niche discrimination must inspect the generic first-pointer carrier"
+        );
+        assert_eq!(count_ops::<MirConstructEnumOp>(&ctx, &body), 0);
+        assert_eq!(count_ops::<MirEnumPayloadOp>(&ctx, &body), 0);
+    }
+
+    #[test]
+    fn option_bool_uses_i8_carrier_and_spills_i1_payload() {
+        let mut ctx = make_ctx();
+        let logical: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let bool_ty: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "OptionBool".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![bool_ty], vec![0], vec![1]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 1,
+                abi_align: 1,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 8,
+                niche_start: 2,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        let slot_map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(
+            slot_map
+                .carrier_llvm_ty
+                .unwrap()
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .unwrap()
+                .width(),
+            8,
+            "Option<bool>'s memory carrier is i8, not bool's semantic i1"
+        );
+        assert_eq!(slot_map.field_slots, vec![None]);
+
+        let (module, block) = build_kernel(&mut ctx, vec![bool_ty], vec![enum_ty]);
+        let payload = block.deref(&ctx).get_argument(0);
+        let construct = Operation::new(
+            &mut ctx,
+            mir::MirConstructEnumOp::get_concrete_op_info(),
+            vec![enum_ty],
+            vec![payload],
+            vec![],
+            0,
+        );
+        mir::MirConstructEnumOp::new(construct)
+            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(1));
+        construct.insert_at_back(block, &ctx);
+        let result = construct.deref(&ctx).get_result(0);
+        append_mir_return(&mut ctx, block, vec![result]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(count_ops::<llvm::InsertValueOp>(&ctx, &body), 0);
+        assert!(find_all::<llvm::ZExtOp>(&ctx, &body).iter().any(|zext| {
+            zext.get_operation()
+                .deref(&ctx)
+                .get_operand(0)
+                .get_type(&ctx)
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .is_some_and(|integer| integer.width() == 1)
+                && zext
+                    .get_operation()
+                    .deref(&ctx)
+                    .get_result(0)
+                    .get_type(&ctx)
+                    .deref(&ctx)
+                    .downcast_ref::<IntegerType>()
+                    .is_some_and(|integer| integer.width() == 8)
+        }));
+        assert!(find_all::<llvm::StoreOp>(&ctx, &body).iter().any(|store| {
+            store
+                .get_operand_value(&ctx)
+                .get_type(&ctx)
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .is_some_and(|integer| integer.width() == 8)
+        }));
+    }
+
+    #[test]
+    fn direct_bool_uses_i8_storage_and_spills_i1_payload() {
+        let mut ctx = make_ctx();
+        let tag: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let bool_ty: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "DirectBool".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::new_with_layout("A".into(), vec![bool_ty], vec![4], vec![1]),
+                EnumVariant::unit("B".into()),
+            ],
+            0,
+            8,
+            4,
+        )
+        .into();
+        let slot_map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(slot_map.field_slots, vec![None]);
+        let storage_fields = slot_map
+            .llvm_struct_ty
+            .deref(&ctx)
+            .downcast_ref::<llvm_types::StructType>()
+            .expect("enum storage must be an LLVM struct")
+            .fields()
+            .collect::<Vec<_>>();
+        assert_eq!(
+            storage_fields[1]
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .map(IntegerType::width),
+            Some(8),
+            "the standalone Rust bool byte must use physical i8 storage"
+        );
+
+        let (module, block) = build_kernel(&mut ctx, vec![bool_ty], vec![enum_ty]);
+        let payload = block.deref(&ctx).get_argument(0);
+        let construct = Operation::new(
+            &mut ctx,
+            mir::MirConstructEnumOp::get_concrete_op_info(),
+            vec![enum_ty],
+            vec![payload],
+            vec![],
+            0,
+        );
+        mir::MirConstructEnumOp::new(construct)
+            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
+        construct.insert_at_back(block, &ctx);
+        let result = construct.deref(&ctx).get_result(0);
+        append_mir_return(&mut ctx, block, vec![result]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(
+            count_ops::<llvm::InsertValueOp>(&ctx, &body),
+            1,
+            "only the direct tag should be inserted as an SSA struct field"
+        );
+        assert!(find_all::<llvm::ZExtOp>(&ctx, &body).iter().any(|zext| {
+            zext.get_operation()
+                .deref(&ctx)
+                .get_operand(0)
+                .get_type(&ctx)
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .is_some_and(|integer| integer.width() == 1)
+                && zext
+                    .get_operation()
+                    .deref(&ctx)
+                    .get_result(0)
+                    .get_type(&ctx)
+                    .deref(&ctx)
+                    .downcast_ref::<IntegerType>()
+                    .is_some_and(|integer| integer.width() == 8)
+        }));
+        assert!(find_all::<llvm::StoreOp>(&ctx, &body).iter().any(|store| {
+            store
+                .get_operand_value(&ctx)
+                .get_type(&ctx)
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .is_some_and(|integer| integer.width() == 8)
+        }));
+    }
+
+    #[test]
+    fn later_field_niche_set_writes_exact_carrier_offset() {
+        use llvm_export::ops::GepIndex;
+
+        let mut ctx = make_ctx();
+        let logical: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let wrapper: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Wrapper".into(),
+            vec!["pad".into(), "nz".into()],
+            vec![u32_ty, u32_ty],
+            vec![0, 1],
+            vec![0, 4],
+            8,
+            4,
+        )
+        .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "MaybeWrapper".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![wrapper], vec![0], vec![8]),
+            ],
+            EnumEncoding {
+                tag_offset: 4,
+                total_size: 8,
+                abi_align: 4,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 32,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, enum_ty, true).into();
+        let (module, block) = build_kernel(&mut ctx, vec![ptr_ty], vec![]);
+        let ptr = block.deref(&ctx).get_argument(0);
+        let set = Operation::new(
+            &mut ctx,
+            mir::MirSetDiscriminantOp::get_concrete_op_info(),
+            vec![],
+            vec![ptr],
+            vec![],
+            0,
+        );
+        let set_op = mir::MirSetDiscriminantOp::new(set);
+        set_op.set_attr_set_discriminant_variant_index(&ctx, VariantIndexAttr(0));
+        set_op.set_attr_set_discriminant_enum_ty(
+            &ctx,
+            pliron::builtin::attributes::TypeAttr::new(enum_ty),
+        );
+        set.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        let gep = find_first::<llvm::GetElementPtrOp>(&ctx, &body).unwrap();
+        let indices = gep.indices(&ctx);
+        let [GepIndex::Value(offset)] = indices.as_slice() else {
+            panic!("carrier access must use a byte-offset SSA value");
+        };
+        let constant =
+            Operation::get_op::<llvm::ConstantOp>(offset.defining_op().unwrap(), &ctx).unwrap();
+        assert_eq!(
+            constant
+                .get_value(&ctx)
+                .downcast_ref::<IntegerAttr>()
+                .unwrap()
+                .value()
+                .to_u64(),
+            4
+        );
+    }
+
+    #[test]
+    fn get_niche_discriminant_adds_large_range_start_at_logical_width() {
+        let mut ctx = make_ctx();
+        let logical_ty: TypeHandle = IntegerType::get(&ctx, 16, Signedness::Unsigned).into();
+        let carrier_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+        let mut variants = (0..300)
+            .map(|index| EnumVariant::unit(format!("V{index}")))
+            .collect::<Vec<_>>();
+        // A valid niche layout stores the carrier inside the untagged
+        // variant's payload. Keep the large logical-variant test realistic
+        // instead of relying on a carrier with no backing field.
+        variants[0] = EnumVariant::new_with_layout("V0".into(), vec![carrier_ty], vec![0], vec![1]);
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "LargeNiche".into(),
+            logical_ty,
+            (0..300).collect(),
+            variants,
+            EnumEncoding {
+                total_size: 1,
+                abi_align: 1,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 8,
+                niche_variant_start: 298,
+                niche_variant_end: 299,
+                untagged_variant: 0,
+                variant_inhabited: {
+                    let mut inhabited = vec![0; 300];
+                    inhabited[0] = 1;
+                    inhabited[298] = 1;
+                    inhabited[299] = 1;
+                    inhabited
+                },
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        let (module, block) = build_kernel(&mut ctx, vec![enum_ty], vec![logical_ty]);
+        let value = block.deref(&ctx).get_argument(0);
+        let get = Operation::new(
+            &mut ctx,
+            mir::MirGetDiscriminantOp::get_concrete_op_info(),
+            vec![logical_ty],
+            vec![value],
+            vec![],
+            0,
+        );
+        get.insert_at_back(block, &ctx);
+        let result = get.deref(&ctx).get_result(0);
+        append_mir_return(&mut ctx, block, vec![result]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(count_ops::<llvm::ZExtOp>(&ctx, &body), 1);
+        let add = find_first::<llvm::AddOp>(&ctx, &body).expect("logical variant add");
+        for operand in add.get_operation().deref(&ctx).operands() {
+            assert_eq!(
+                operand
+                    .get_type(&ctx)
+                    .deref(&ctx)
+                    .downcast_ref::<IntegerType>()
+                    .unwrap()
+                    .width(),
+                16,
+                "variant-index arithmetic must occur at logical width"
+            );
+        }
+    }
+
+    #[test]
+    fn direct_negative_discriminant_read_remains_signed_for_widening() {
+        let mut ctx = make_ctx();
+        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signed).into();
+        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signed).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "Negative".into(),
+            i8_ty,
+            vec![255, 0],
+            vec![EnumVariant::unit("N".into()), EnumVariant::unit("Z".into())],
+            0,
+            1,
+            1,
+        )
+        .into();
+        let (module, block) = build_kernel(&mut ctx, vec![], vec![i32_ty]);
+        let construct = Operation::new(
+            &mut ctx,
+            mir::MirConstructEnumOp::get_concrete_op_info(),
+            vec![enum_ty],
+            vec![],
+            vec![],
+            0,
+        );
+        mir::MirConstructEnumOp::new(construct)
+            .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
+        construct.insert_at_back(block, &ctx);
+        let enum_value = construct.deref(&ctx).get_result(0);
+        let get = Operation::new(
+            &mut ctx,
+            mir::MirGetDiscriminantOp::get_concrete_op_info(),
+            vec![i8_ty],
+            vec![enum_value],
+            vec![],
+            0,
+        );
+        get.insert_at_back(block, &ctx);
+        let discriminant = get.deref(&ctx).get_result(0);
+        let cast = Operation::new(
+            &mut ctx,
+            mir::MirCastOp::get_concrete_op_info(),
+            vec![i32_ty],
+            vec![discriminant],
+            vec![],
+            0,
+        );
+        mir::MirCastOp::new(cast).set_attr_cast_kind(&ctx, MirCastKindAttr::IntToInt);
+        cast.insert_at_back(block, &ctx);
+        let widened = cast.deref(&ctx).get_result(0);
+        append_mir_return(&mut ctx, block, vec![widened]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+        let body = kernel_blocks(&ctx, module);
+        assert_eq!(count_ops::<llvm::SExtOp>(&ctx, &body), 1);
+        assert_eq!(count_ops::<llvm::ZExtOp>(&ctx, &body), 0);
+    }
+
+    #[test]
+    fn single_layout_preserves_large_and_negative_declared_discriminants() {
+        for (width, signedness, bits, widened_width, expects_sext) in [
+            (16, Signedness::Unsigned, 1_000, 16, false),
+            (8, Signedness::Signed, 251, 32, true),
+        ] {
+            let mut ctx = make_ctx();
+            let logical: TypeHandle = IntegerType::get(&ctx, width, signedness).into();
+            let destination: TypeHandle = IntegerType::get(&ctx, widened_width, signedness).into();
+            let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+                &mut ctx,
+                "Single".into(),
+                logical,
+                vec![bits],
+                vec![EnumVariant::unit("Only".into())],
+                EnumEncoding {
+                    tag_offset: 0,
+                    total_size: 0,
+                    abi_align: 1,
+                    layout_kind: EnumLayoutKind::Single,
+                    variant_inhabited: vec![1],
+                    ..EnumEncoding::default()
+                },
+            )
+            .into();
+            let (module, block) = build_kernel(&mut ctx, vec![], vec![destination]);
+            let construct = Operation::new(
+                &mut ctx,
+                mir::MirConstructEnumOp::get_concrete_op_info(),
+                vec![enum_ty],
+                vec![],
+                vec![],
+                0,
+            );
+            mir::MirConstructEnumOp::new(construct)
+                .set_attr_construct_enum_variant_index(&ctx, VariantIndexAttr(0));
+            construct.insert_at_back(block, &ctx);
+            let enum_value = construct.deref(&ctx).get_result(0);
+            let get = Operation::new(
+                &mut ctx,
+                mir::MirGetDiscriminantOp::get_concrete_op_info(),
+                vec![logical],
+                vec![enum_value],
+                vec![],
+                0,
+            );
+            get.insert_at_back(block, &ctx);
+            let discr = get.deref(&ctx).get_result(0);
+            let returned = if widened_width == width {
+                discr
+            } else {
+                let cast = Operation::new(
+                    &mut ctx,
+                    mir::MirCastOp::get_concrete_op_info(),
+                    vec![destination],
+                    vec![discr],
+                    vec![],
+                    0,
+                );
+                mir::MirCastOp::new(cast).set_attr_cast_kind(&ctx, MirCastKindAttr::IntToInt);
+                cast.insert_at_back(block, &ctx);
+                cast.deref(&ctx).get_result(0)
+            };
+            append_mir_return(&mut ctx, block, vec![returned]);
+
+            crate::lower_mir_to_llvm(&mut ctx, module).expect("lowering failed");
+            let body = kernel_blocks(&ctx, module);
+            let found_bits = find_all::<llvm::ConstantOp>(&ctx, &body)
+                .iter()
+                .any(|constant| {
+                    constant
+                        .get_value(&ctx)
+                        .downcast_ref::<IntegerAttr>()
+                        .is_some_and(|value| value.value().to_u64() == bits)
+                });
+            assert!(
+                found_bits,
+                "single discriminant {bits} must not be truncated"
+            );
+            assert_eq!(count_ops::<llvm::SExtOp>(&ctx, &body) == 1, expects_sext);
+        }
+    }
+}
diff --git a/crates/mir-lower/src/convert/ops/aggregate/fields.rs b/crates/mir-lower/src/convert/ops/aggregate/fields.rs
new file mode 100644
index 0000000000..41ca9756cf
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/aggregate/fields.rs
@@ -0,0 +1,489 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use super::common::{anyhow_to_pliron, spill_enum_value};
+use crate::convert::types::{
+    StructLayoutInfo, StructSlotMap, build_struct_slot_map, build_union_storage_type, convert_type,
+    is_zero_sized_type, make_slice_struct,
+};
+use dialect_mir::ops::{MirExtractFieldOp, MirInsertFieldOp};
+use dialect_mir::types::{
+    MirArrayType, MirDisjointSliceType, MirSliceType, MirStructType, MirTupleType, MirUnionType,
+};
+use llvm_export::ops as llvm;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+
+/// How the MIR-level field indices of an aggregate operand map onto the
+/// lowered LLVM aggregate.
+pub(super) enum AggregateSlots {
+    /// Lowered from a `MirStructType`/`MirTupleType`: use the slot map the
+    /// type converter built (accounts for reordering, `[N x i8]` padding
+    /// slots and stripped ZST fields).
+    Mapped(StructSlotMap),
+    /// The MIR index is already the final LLVM index. Sound only for
+    /// aggregates whose lowered layout is index-preserving by construction:
+    /// arrays and slice fat pointers (`{ ptr, i64 }`).
+    Identity,
+}
+
+/// Resolve how field indices of `aggregate` map onto its lowered type.
+///
+/// Recover-or-error (issue #128): when the operand has no recorded
+/// `MirStructType`/`MirTupleType` conversion history, identity indexing is
+/// only sound for aggregates the converter lowers without reordering,
+/// padding, or ZST stripping: arrays and slice fat pointers. Anything
+/// else is a lowering bug; guessing identity there silently reads or
+/// writes the wrong field, so we error out loudly instead.
+pub(super) fn resolve_aggregate_slots(
+    ctx: &mut Context,
+    operands_info: &OperandsInfo,
+    aggregate: Value,
+) -> Result<AggregateSlots> {
+    let layout = operands_info
+        .lookup_most_recent_of_type::<MirStructType>(ctx, aggregate)
+        .map(|struct_ref| StructLayoutInfo::of_struct(&struct_ref))
+        .or_else(|| {
+            operands_info
+                .lookup_most_recent_of_type::<MirTupleType>(ctx, aggregate)
+                .map(|tuple_ref| StructLayoutInfo::of_tuple(&tuple_ref))
+        });
+
+    if let Some(layout) = layout {
+        let map = build_struct_slot_map(ctx, &layout).map_err(anyhow_to_pliron)?;
+        return Ok(AggregateSlots::Mapped(map));
+    }
+
+    // Arrays keep their element indices: `[N x T]` has no reorder, no
+    // padding, no ZST stripping.
+    let is_array_history = operands_info
+        .lookup_most_recent_of_type::<MirArrayType>(ctx, aggregate)
+        .is_some();
+    // Slices lower to the `{ ptr, i64 }` fat pointer, where index 0 = ptr
+    // and index 1 = len by construction.
+    let is_slice_history = operands_info
+        .lookup_most_recent_of_type::<MirSliceType>(ctx, aggregate)
+        .is_some()
+        || operands_info
+            .lookup_most_recent_of_type::<MirDisjointSliceType>(ctx, aggregate)
+            .is_some();
+    if is_array_history || is_slice_history {
+        return Ok(AggregateSlots::Identity);
+    }
+
+    // No conversion history at all (e.g. a slice reconstructed in the entry
+    // prologue, which is born as an LLVM struct). Identity is still fine if
+    // the current type is a slice fat pointer or an LLVM array. A disjoint
+    // slice with a runtime row width is the same case one word longer: every
+    // runtime index space today carries a single `u32` row width, and the struct the type
+    // converter builds for it (`make_disjoint_slice_struct`) is
+    // index-preserving by construction, exactly like the two-field fat
+    // pointer. Both shape checks share the two-field caveat that an unnamed
+    // user struct with the identical lowered layout would be accepted too;
+    // that has been the accepted trade-off for `{ ptr, i64 }` since issue
+    // #128, and a struct needing a slot map still errors below whenever its
+    // lowered shape differs (padding slots, reordering, other field types).
+    let aggregate_ty = aggregate.get_type(ctx);
+    let slice_struct_ty = make_slice_struct(ctx);
+    let row_width_slice_struct_ty = {
+        // The one runtime layout current `SpaceLayout` impls produce: a
+        // single u32 row width. Built through the real constructor so this
+        // check cannot drift from the lowered shape. A future space with a
+        // different `Data` shape is not listed here and thus fails closed
+        // into the refuse-to-guess error until this site learns it.
+        let width_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+        crate::convert::types::make_disjoint_slice_struct(ctx, &[width_ty])
+            .map_err(anyhow_to_pliron)?
+    };
+    let is_llvm_array = aggregate_ty
+        .deref(ctx)
+        .is::<llvm_export::types::ArrayType>();
+    if aggregate_ty == slice_struct_ty || aggregate_ty == row_width_slice_struct_ty || is_llvm_array
+    {
+        return Ok(AggregateSlots::Identity);
+    }
+
+    let ty_disp = aggregate_ty.deref(ctx).disp(ctx).to_string();
+    pliron::input_err_noloc!(
+        "Cannot map field indices for aggregate of type {ty_disp}: no struct/tuple \
+         conversion history was recorded for this operand, and identity indexing is \
+         only sound for arrays and slice fat pointers (with or without the runtime \
+         row-width word). Refusing to guess a field mapping (issue #128)."
+    )
+}
+
+/// Convert `mir.extract_field` to `llvm.extractvalue`.
+///
+/// Handles scalar-lowered newtype case: if the operand is a scalar (e.g., `ThreadIndex`),
+/// no extraction is needed.
+///
+/// The declaration-order field index is mapped to the LLVM slot via
+/// [`resolve_aggregate_slots`], which shares the type converter's view of
+/// the struct (reorder, `[N x i8]` padding slots, stripped ZSTs). If
+/// extracting a ZST field, we return undef of its (empty) type.
+pub(crate) fn convert_extract_field(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    let aggregate = op.deref(ctx).get_operand(0);
+
+    let extract_op = MirExtractFieldOp::new(op);
+    let decl_index = match extract_op.get_attr_index(ctx) {
+        Some(attr) => attr.0 as usize,
+        None => return pliron::input_err_noloc!("Missing index attribute on extract_field"),
+    };
+
+    if operands_info
+        .lookup_most_recent_of_type::<MirUnionType>(ctx, aggregate)
+        .is_some()
+    {
+        return convert_extract_union_field(
+            ctx,
+            rewriter,
+            op,
+            aggregate,
+            decl_index,
+            operands_info,
+        );
+    }
+
+    let is_scalar = aggregate
+        .get_type(ctx)
+        .deref(ctx)
+        .downcast_ref::<IntegerType>()
+        .is_some();
+
+    if is_scalar {
+        rewriter.replace_operation_with_values(ctx, op, vec![aggregate]);
+        return Ok(());
+    }
+
+    let llvm_index = match resolve_aggregate_slots(ctx, operands_info, aggregate)? {
+        AggregateSlots::Mapped(map) => match map.decl_to_llvm.get(decl_index) {
+            Some(Some(slot)) => *slot,
+            Some(None) => {
+                // ZST field: stripped from the LLVM struct, so there is
+                // nothing to extract. Materialize undef of its empty type.
+                let zst_ty = map.field_llvm_types[decl_index];
+                let undef_op = llvm::UndefOp::new(ctx, zst_ty);
+                rewriter.insert_operation(ctx, undef_op.get_operation());
+                rewriter.replace_operation(ctx, op, undef_op.get_operation());
+                return Ok(());
+            }
+            None => {
+                return pliron::input_err_noloc!(
+                    "extract_field index {} out of bounds for aggregate with {} fields",
+                    decl_index,
+                    map.decl_to_llvm.len()
+                );
+            }
+        },
+        AggregateSlots::Identity => decl_index as u32,
+    };
+
+    let llvm_extract = llvm::ExtractValueOp::new(ctx, aggregate, vec![llvm_index])?;
+    rewriter.insert_operation(ctx, llvm_extract.get_operation());
+    rewriter.replace_operation(ctx, op, llvm_extract.get_operation());
+
+    Ok(())
+}
+
+/// Convert `mir.insert_field` to `llvm.insertvalue`.
+///
+/// Operands: `[aggregate, new_value]`
+/// Returns a new aggregate with the field at `insert_index` replaced.
+///
+/// The declaration-order field index is mapped to the LLVM slot via
+/// [`resolve_aggregate_slots`] (arrays keep their element index). If
+/// inserting a ZST field, we return the original aggregate unchanged.
+pub(crate) fn convert_insert_field(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    let aggregate = op.deref(ctx).get_operand(0);
+    let new_value = op.deref(ctx).get_operand(1);
+
+    let insert_op = MirInsertFieldOp::new(op);
+    let decl_index = match insert_op.get_attr_insert_index(ctx) {
+        Some(attr) => attr.0 as usize,
+        None => return pliron::input_err_noloc!("Missing insert_index attribute on insert_field"),
+    };
+
+    if operands_info
+        .lookup_most_recent_of_type::<MirUnionType>(ctx, aggregate)
+        .is_some()
+    {
+        return convert_insert_union_field(
+            ctx,
+            rewriter,
+            op,
+            aggregate,
+            new_value,
+            decl_index,
+            operands_info,
+        );
+    }
+
+    let llvm_index = match resolve_aggregate_slots(ctx, operands_info, aggregate)? {
+        AggregateSlots::Mapped(map) => match map.decl_to_llvm.get(decl_index) {
+            Some(Some(slot)) => *slot,
+            Some(None) => {
+                // ZST field: stripped from the LLVM struct, so inserting
+                // into it is a no-op. Forward the aggregate unchanged.
+                rewriter.replace_operation_with_values(ctx, op, vec![aggregate]);
+                return Ok(());
+            }
+            None => {
+                return pliron::input_err_noloc!(
+                    "insert_field index {} out of bounds for aggregate with {} fields",
+                    decl_index,
+                    map.decl_to_llvm.len()
+                );
+            }
+        },
+        AggregateSlots::Identity => decl_index as u32,
+    };
+
+    let llvm_insert = llvm::InsertValueOp::new(ctx, aggregate, new_value, vec![llvm_index]);
+    rewriter.insert_operation(ctx, llvm_insert.get_operation());
+    rewriter.replace_operation(ctx, op, llvm_insert.get_operation());
+
+    Ok(())
+}
+
+fn union_type_of_operand(
+    ctx: &Context,
+    operands_info: &OperandsInfo,
+    value: Value,
+) -> Result<MirUnionType> {
+    operands_info
+        .lookup_most_recent_of_type::<MirUnionType>(ctx, value)
+        .map(|union_ty| union_ty.clone())
+        .ok_or_else(|| {
+            pliron::create_error!(
+                pliron::location::Location::Unknown,
+                pliron::result::ErrorKind::VerificationFailed,
+                pliron::result::StringError(
+                    "Expected MirUnionType conversion history for union value".to_string()
+                )
+            )
+        })
+}
+
+/// Read one typed view of a union's shared bytes.
+fn convert_extract_union_field(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    union_value: Value,
+    field_index: usize,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    let union_ty = union_type_of_operand(ctx, operands_info, union_value)?;
+    let Some(field_mir_ty) = union_ty.get_field_type(field_index) else {
+        return pliron::input_err_noloc!(
+            "union field index {} is out of bounds for `{}`",
+            field_index,
+            union_ty.name()
+        );
+    };
+    let field_llvm_ty = convert_type(ctx, field_mir_ty).map_err(anyhow_to_pliron)?;
+    if is_zero_sized_type(ctx, field_llvm_ty) {
+        let undef = llvm::UndefOp::new(ctx, field_llvm_ty);
+        rewriter.insert_operation(ctx, undef.get_operation());
+        rewriter.replace_operation(ctx, op, undef.get_operation());
+        return Ok(());
+    }
+
+    let storage_ty = build_union_storage_type(ctx, &union_ty).map_err(anyhow_to_pliron)?;
+    let ptr = spill_enum_value(ctx, rewriter, union_value, storage_ty, union_ty.abi_align());
+    let load = llvm::LoadOp::new(ctx, ptr, field_llvm_ty);
+    llvm_export::ops::set_op_alignment(ctx, load.get_operation(), union_ty.abi_align() as u32);
+    rewriter.insert_operation(ctx, load.get_operation());
+    rewriter.replace_operation(ctx, op, load.get_operation());
+    Ok(())
+}
+
+/// Write one typed view at byte zero while preserving the rest of the union.
+fn convert_insert_union_field(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    union_value: Value,
+    new_value: Value,
+    field_index: usize,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    let union_ty = union_type_of_operand(ctx, operands_info, union_value)?;
+    let Some(field_mir_ty) = union_ty.get_field_type(field_index) else {
+        return pliron::input_err_noloc!(
+            "union field index {} is out of bounds for `{}`",
+            field_index,
+            union_ty.name()
+        );
+    };
+    let field_llvm_ty = convert_type(ctx, field_mir_ty).map_err(anyhow_to_pliron)?;
+    if is_zero_sized_type(ctx, field_llvm_ty) {
+        rewriter.replace_operation_with_values(ctx, op, vec![union_value]);
+        return Ok(());
+    }
+
+    let storage_ty = build_union_storage_type(ctx, &union_ty).map_err(anyhow_to_pliron)?;
+    let ptr = spill_enum_value(ctx, rewriter, union_value, storage_ty, union_ty.abi_align());
+    let store = llvm::StoreOp::new(ctx, new_value, ptr);
+    llvm_export::ops::set_op_alignment(ctx, store.get_operation(), union_ty.abi_align() as u32);
+    rewriter.insert_operation(ctx, store.get_operation());
+
+    let load = llvm::LoadOp::new(ctx, ptr, storage_ty);
+    llvm_export::ops::set_op_alignment(ctx, load.get_operation(), union_ty.abi_align() as u32);
+    rewriter.insert_operation(ctx, load.get_operation());
+    rewriter.replace_operation(ctx, op, load.get_operation());
+    Ok(())
+}
+
+#[cfg(test)]
+// Tests build kinded fixture types directly; production minting lives in mir-importer's facts.rs.
+#[allow(clippy::disallowed_methods)]
+mod tests {
+    use super::*;
+    use crate::convert::ops::test_util::*;
+    use dialect_mir::attributes::FieldIndexAttr;
+    use dialect_mir::ops as mir;
+
+    use llvm_export::types as llvm_types;
+
+    use super::super::test_support::*;
+
+    /// Extracting a ZST field must not emit `extract_value`: the field has no
+    /// storage in the lowered LLVM struct, so lowering materializes an undef
+    /// zero-sized value instead.
+    #[test]
+    fn extract_zst_field_lowers_to_undef_without_extract_value() {
+        let mut ctx = make_ctx();
+
+        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
+        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
+        let (struct_ty, zst_ty) = padded_struct_with_zst_ty(&mut ctx);
+
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![i8_ty, i64_ty], vec![]);
+        let a = block.deref(&ctx).get_argument(0);
+        let b = block.deref(&ctx).get_argument(1);
+        let marker = append_empty_struct_value(&mut ctx, block, zst_ty);
+
+        let construct = Operation::new(
+            &mut ctx,
+            mir::MirConstructStructOp::get_concrete_op_info(),
+            vec![struct_ty],
+            vec![a, marker, b],
+            vec![],
+            0,
+        );
+        construct.insert_at_back(block, &ctx);
+        let aggregate = construct.deref(&ctx).get_result(0);
+
+        let extract = Operation::new(
+            &mut ctx,
+            MirExtractFieldOp::get_concrete_op_info(),
+            vec![zst_ty],
+            vec![aggregate],
+            vec![],
+            0,
+        );
+        MirExtractFieldOp::new(extract).set_attr_index(&ctx, FieldIndexAttr(1));
+        extract.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+
+        assert_eq!(
+            count_ops::<llvm::ExtractValueOp>(&ctx, &body),
+            0,
+            "extracting a stripped ZST field must not emit llvm.extractvalue"
+        );
+
+        let zst_un_defs = find_all::<llvm::UndefOp>(&ctx, &body)
+            .into_iter()
+            .filter(|op| {
+                let result_ty = op.get_operation().deref(&ctx).get_result(0).get_type(&ctx);
+                is_zero_sized_type(&ctx, result_ty)
+            })
+            .count();
+
+        assert_eq!(
+            zst_un_defs, 2,
+            "one undef should build the ZST value and one should materialize the extracted ZST"
+        );
+    }
+
+    /// The row-width arm of [`resolve_aggregate_slots`]' no-history fallback
+    /// is defensive symmetry: no current lowering path produces a runtime-width
+    /// slice value with an empty conversion history, so no end-to-end pipeline
+    /// test can reach it. This exercises the fallback directly: a value born as
+    /// the lowered `{ ptr, i64, i32 }` row-width shape (a block argument, which
+    /// carries no history) must resolve to identity indexing exactly like the
+    /// two-field `{ ptr, i64 }` fat pointer, and any other unrecognized
+    /// no-history shape must keep failing closed into the refuse-to-guess
+    /// error (issue #128).
+    #[test]
+    fn no_history_fallback_resolves_row_width_slice_shape_and_stays_closed_otherwise() {
+        let mut ctx = make_ctx();
+
+        // The exact struct the type converter lowers a runtime-width
+        // disjoint slice to, built through the same constructor the fallback
+        // uses so the test cannot drift from the lowered shape.
+        let width_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let row_width_ty = crate::convert::types::make_disjoint_slice_struct(&mut ctx, &[width_ty])
+            .expect("building the row-width slice struct must succeed");
+
+        // A three-field control shape that is NOT the row-width slice: i64
+        // where the u32 row-width word belongs.
+        use llvm_export::types::PointerTypeExt;
+        let ptr_ty: TypeHandle = llvm_types::PointerType::get_generic(&mut ctx).into();
+        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
+        let foreign_ty: TypeHandle = llvm_types::StructType::get_unnamed(
+            &ctx,
+            (
+                vec![ptr_ty, i64_ty, i64_ty],
+                llvm_types::StructLayout::Unpacked,
+            ),
+        )
+        .into();
+
+        let (_module, block) = build_kernel(&mut ctx, vec![row_width_ty, foreign_ty], vec![]);
+        let row_width_value = block.deref(&ctx).get_argument(0);
+        let foreign_value = block.deref(&ctx).get_argument(1);
+
+        // Block arguments have no recorded conversion history at all.
+        let no_history = OperandsInfo::default();
+
+        let resolved = resolve_aggregate_slots(&mut ctx, &no_history, row_width_value)
+            .expect("the row-width slice shape with no history must resolve");
+        assert!(
+            matches!(resolved, AggregateSlots::Identity),
+            "the row-width {{ ptr, i64, u32 }} shape is index-preserving and must map identically"
+        );
+
+        let refused = resolve_aggregate_slots(&mut ctx, &no_history, foreign_value);
+        assert!(
+            refused.is_err(),
+            "a no-history shape that is not a slice fat pointer (with or without \
+             the row-width word) must fail closed"
+        );
+    }
+}
diff --git a/crates/mir-lower/src/convert/ops/aggregate/mod.rs b/crates/mir-lower/src/convert/ops/aggregate/mod.rs
new file mode 100644
index 0000000000..37a574d53c
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/aggregate/mod.rs
@@ -0,0 +1,59 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Aggregate operation conversion: `dialect-mir` → LLVM dialect.
+//!
+//! Converts `dialect-mir` aggregate operations (structs, tuples, enums) to
+//! their LLVM dialect equivalents.
+//!
+//! # Operations
+//!
+//! | MIR Operation            | LLVM Operation(s)                    | Description            |
+//! |--------------------------|--------------------------------------|------------------------|
+//! | `mir.extract_field`      | `llvm.extractvalue`                  | Get struct/tuple field |
+//! | `mir.insert_field`       | `llvm.insertvalue`                   | Set struct/tuple field |
+//! | `mir.construct_struct`   | `llvm.undef` + `llvm.insertvalue`    | Build struct           |
+//! | `mir.construct_tuple`    | `llvm.undef` + `llvm.insertvalue`    | Build tuple            |
+//! | `mir.construct_slice`    | `llvm.undef` + `llvm.insertvalue`    | Build slice fat ptr    |
+//! | `mir.construct_enum`     | `llvm.undef` + `llvm.insertvalue`    | Build enum             |
+//! | `mir.get_discriminant`   | `llvm.extractvalue`                  | Get enum tag           |
+//! | `mir.set_discriminant`   | `llvm.getelementptr` + `llvm.store`  | Write enum tag         |
+//! | `mir.enum_payload`       | `llvm.extractvalue`                  | Get enum payload       |
+//!
+//! # Enum Representation
+//!
+//! Enums use rustc's physical layout, not a cuda-oxide-only tagged struct.
+//! `build_enum_slot_map` places the direct tag or niche carrier and every
+//! payload at rustc's byte offsets, reuses identical overlapping storage, and
+//! routes differently typed overlaps through byte-addressed memory. `Single`
+//! and `Empty` layouts have no carrier at all.
+//!
+//! A direct tag holds the variant's DECLARED discriminant value, not its
+//! position. For `core::cmp::Ordering`, `Less` therefore stores -1 (the i8 bit
+//! pattern 255), `Equal` stores 0, and `Greater` stores 1. A niche layout
+//! instead uses rustc's wrapping `niche_start + variant_offset` encoding and
+//! introduces no extra tag.
+
+mod addressing;
+mod array_extract;
+mod common;
+mod construct;
+mod enum_layout;
+mod enums;
+mod fields;
+#[cfg(test)]
+mod test_support;
+
+pub(crate) use addressing::{convert_array_element_addr, convert_field_addr};
+pub(crate) use array_extract::convert_extract_array_element;
+pub(crate) use construct::{
+    convert_construct_array, convert_construct_disjoint_slice, convert_construct_slice,
+    convert_construct_struct, convert_construct_tuple,
+};
+pub(crate) use enums::{
+    convert_construct_enum, convert_enum_payload, convert_get_discriminant,
+    convert_set_discriminant,
+};
+pub(crate) use fields::{convert_extract_field, convert_insert_field};
diff --git a/crates/mir-lower/src/convert/ops/aggregate/test_support.rs b/crates/mir-lower/src/convert/ops/aggregate/test_support.rs
new file mode 100644
index 0000000000..22d3a22d4a
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/aggregate/test_support.rs
@@ -0,0 +1,109 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Tests build kinded fixture types directly; production minting lives in mir-importer's facts.rs.
+#![allow(clippy::disallowed_methods)]
+
+use dialect_mir::ops as mir;
+use dialect_mir::types::{
+    EnumCarrierKind, EnumEncoding, EnumLayoutKind, EnumVariant, MirEnumType, MirStructType,
+};
+use llvm_export::ops as llvm;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::TypeHandle;
+use pliron::value::Value;
+
+pub(super) fn insert_indices(ctx: &Context, inserts: &[llvm::InsertValueOp]) -> Vec<Vec<u32>> {
+    inserts.iter().map(|op| op.indices(ctx)).collect()
+}
+
+pub(super) fn empty_struct_ty(ctx: &mut Context, name: &str) -> TypeHandle {
+    MirStructType::get(ctx, name.to_string(), vec![], vec![]).into()
+}
+
+pub(super) fn padded_struct_with_zst_ty(ctx: &mut Context) -> (TypeHandle, TypeHandle) {
+    let i8_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
+    let i64_ty: TypeHandle = IntegerType::get(ctx, 64, Signedness::Signless).into();
+    let zst_ty = empty_struct_ty(ctx, "Marker");
+
+    let struct_ty = MirStructType::get_with_full_layout(
+        ctx,
+        "Padded".to_string(),
+        vec!["a".to_string(), "marker".to_string(), "b".to_string()],
+        vec![i8_ty, zst_ty, i64_ty],
+        vec![0, 1, 2],
+        vec![0, 1, 8],
+        16,
+        8,
+    );
+
+    (struct_ty.into(), zst_ty)
+}
+
+pub(super) fn append_empty_struct_value(
+    ctx: &mut Context,
+    block: Ptr<pliron::basic_block::BasicBlock>,
+    zst_ty: TypeHandle,
+) -> Value {
+    let op = Operation::new(
+        ctx,
+        mir::MirConstructStructOp::get_concrete_op_info(),
+        vec![zst_ty],
+        vec![],
+        vec![],
+        0,
+    );
+    op.insert_at_back(block, ctx);
+    op.deref(ctx).get_result(0)
+}
+
+pub(super) fn unit_niche_enum(
+    ctx: &mut Context,
+    carrier: (EnumCarrierKind, u32, u32),
+    niche_start: u128,
+    niche_range: std::ops::RangeInclusive<u32>,
+    untagged_variant: u32,
+    inhabited: Vec<u8>,
+) -> TypeHandle {
+    let (carrier_kind, carrier_width, carrier_address_space) = carrier;
+    let logical_width = if inhabited.len() > u8::MAX as usize {
+        16
+    } else {
+        8
+    };
+    let logical_ty: TypeHandle = IntegerType::get(ctx, logical_width, Signedness::Unsigned).into();
+    let variants = (0..inhabited.len())
+        .map(|index| EnumVariant::unit(format!("V{index}")))
+        .collect::<Vec<_>>();
+    let discriminants = (0..inhabited.len() as u64).collect();
+    let carrier_size = u64::from(carrier_width).div_ceil(8);
+    let carrier_align = carrier_size.next_power_of_two().min(16);
+    MirEnumType::get_with_encoding(
+        ctx,
+        "UnitNiche".into(),
+        logical_ty,
+        discriminants,
+        variants,
+        EnumEncoding {
+            tag_offset: 0,
+            total_size: carrier_size,
+            abi_align: carrier_align,
+            layout_kind: EnumLayoutKind::Niche,
+            carrier_kind,
+            carrier_width,
+            carrier_address_space,
+            niche_start,
+            niche_variant_start: *niche_range.start(),
+            niche_variant_end: *niche_range.end(),
+            untagged_variant,
+            variant_inhabited: inhabited,
+            ..EnumEncoding::default()
+        },
+    )
+    .into()
+}
diff --git a/crates/mir-lower/src/convert/ops/memory.rs b/crates/mir-lower/src/convert/ops/memory.rs
deleted file mode 100644
index 232b516d5e..0000000000
--- a/crates/mir-lower/src/convert/ops/memory.rs
+++ /dev/null
@@ -1,4754 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-//! Memory operation conversion: `dialect-mir` → LLVM dialect.
-//!
-//! Converts `dialect-mir` memory operations to their LLVM dialect equivalents.
-//!
-//! # Operations
-//!
-//! | MIR Operation        | LLVM Operation(s)                 | Description                  |
-//! |----------------------|-----------------------------------|------------------------------|
-//! | `mir.load`           | `llvm.load`                       | Load from pointer            |
-//! | `mir.store`          | `llvm.store`                      | Store to pointer             |
-//! | `mir.ref`            | `llvm.alloca` + `llvm.store`      | Materialize aggregate in mem |
-//! | `mir.ptr_offset`     | `llvm.getelementptr`              | Pointer arithmetic           |
-//! | `mir.shared_alloc`   | `llvm.global` + `llvm.addressof`  | Static shared memory         |
-//! | `mir.extern_shared`  | `llvm.global` + `llvm.addressof`  | Dynamic shared memory        |
-//!
-//! # Shared Memory
-//!
-//! ## Static Shared Memory (`SharedArray<T, N, ALIGN>`)
-//!
-//! Each static shared memory allocation gets a unique global symbol (`__shared_mem_N`).
-//! Multiple allocations in the same or different kernels each have their own symbol
-//! with their own size and alignment.
-//!
-//! ## Dynamic Shared Memory (`DynamicSharedArray<T, ALIGN>`)
-//!
-//! Dynamic shared memory uses a symbol for each function that owns an access
-//! (`__dynamic_smem_{function_name}`).
-//! Key characteristics:
-//!
-//! - **Per-owner symbols**: Each function containing an access gets an extern symbol
-//! - **Pre-computed alignment**: A pre-pass combines the owner's body alignment with
-//!   the strongest launch-contract marker that can reach it
-//! - **Single runtime pool per launch**: The symbols refer to dynamic shared memory
-//!   sized by `shared_mem_bytes` at launch
-//!
-//! ### PTX Output Example
-//!
-//! ```ptx
-//! ; Kernel with 128-byte aligned dynamic shared memory
-//! .extern .shared .align 128 .b8 __dynamic_smem_my_kernel[];
-//!
-//! ; Another kernel with 16-byte aligned (default)
-//! .extern .shared .align 16 .b8 __dynamic_smem_other_kernel[];
-//! ```
-
-use crate::context::{
-    DeviceGlobalDeclaration, DeviceGlobalRecord, DeviceGlobalsMap, DynamicSmemAlignmentMap,
-    SharedGlobalDeclaration, SharedGlobalKind, SharedGlobalRecord, SharedGlobalsMap,
-};
-use crate::convert::types::{
-    StructLayoutInfo, build_struct_slot_map, convert_type,
-    llvm_packed_struct_contains_pointer_in_address_space, llvm_type_size_align, mir_element_stride,
-    mir_type_abi_align, validate_initialized_global_layout,
-    validate_relocated_initialized_global_layout,
-};
-use crate::helpers;
-use dialect_mir::types::{MirPtrType, MirStructType};
-use llvm_export::attributes::IntegerOverflowFlagsAttr;
-use llvm_export::op_interfaces::IntBinArithOpWithOverflowFlag;
-use llvm_export::ops as llvm;
-use llvm_export::ops::GlobalOpExt;
-use llvm_export::types::{ArrayType, FuncType, StructLayout, StructType, VoidType};
-use pliron::attribute::AttrObj;
-use pliron::builtin::attributes::IntegerAttr;
-use pliron::builtin::op_interfaces::CallOpCallable;
-use pliron::builtin::op_interfaces::SymbolOpInterface;
-use pliron::builtin::types::{IntegerType, Signedness};
-use pliron::context::{Context, Ptr};
-use pliron::identifier::Identifier;
-use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
-use pliron::irbuild::inserter::Inserter;
-use pliron::irbuild::rewriter::Rewriter;
-use pliron::linked_list::ContainsLinkedList;
-use pliron::location::Located;
-use pliron::op::Op;
-use pliron::operation::Operation;
-use pliron::result::Result;
-use pliron::r#type::{TypeHandle, Typed};
-use pliron::utils::apint::APInt;
-use pliron::value::Value;
-
-fn anyhow_to_pliron(e: anyhow::Error) -> pliron::result::Error {
-    pliron::create_error!(
-        pliron::location::Location::Unknown,
-        pliron::result::ErrorKind::VerificationFailed,
-        pliron::result::StringError(e.to_string())
-    )
-}
-
-/// Convert `mir.store` to `llvm.store`.
-///
-/// Operand order: `[ptr, value]` - stores `value` to address `ptr`.
-/// No result is produced (store is a side effect).
-pub(crate) fn convert_store(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    let operands: Vec<_> = op.deref(ctx).operands().collect();
-
-    let (ptr, val) = match operands.as_slice() {
-        [ptr, val] => (*ptr, *val),
-        _ => {
-            return pliron::input_err_noloc!("Store operation requires exactly 2 operands");
-        }
-    };
-
-    // Packed whole-value stores are byte-faithful now that divergent rustc
-    // layouts lower to LLVM packed structs. Keep the target-dependent AS3 case
-    // fail-closed because its physical pointer width is selected only later.
-    fail_on_target_dependent_packed_aggregate(
-        ctx,
-        value_mir_type(ctx, operands_info, val),
-        "storing",
-    )?;
-
-    let llvm_store = llvm::StoreOp::new(ctx, val, ptr);
-    if dialect_mir::ops::MirStoreOp::new(op).is_volatile(ctx) {
-        llvm_export::ops::set_op_volatile(ctx, llvm_store.get_operation(), true);
-    }
-    // The stored value's own type answers first, as it did before. A scalar
-    // records none, though, so fall back to whatever the address itself proved
-    // when it was computed -- for a field projection that is the aggregate's
-    // `abi_align` narrowed to the field's offset, which is otherwise lost here
-    // and costs the pair its vectorization. This mirrors `convert_load`, which
-    // consults the same record for the same reason. When both answer, the
-    // weaker wins: a field of a packed aggregate can place an abi-aligned type
-    // at a byte-aligned address, and the address's proved alignment is the
-    // ceiling of what the store may claim.
-    let abi = value_abi_align(ctx, operands_info, val);
-    let proved = pointer_proved_alignment(ctx, ptr);
-    let align = match (abi, proved) {
-        (Some(abi), Some(proved)) => Some(abi.min(proved)),
-        (abi, proved) => abi.or(proved),
-    };
-    if let Some(align) = align {
-        llvm_export::ops::set_op_alignment(ctx, llvm_store.get_operation(), align as u32);
-    }
-    crate::convert::preserve_location(ctx, op, llvm_store.get_operation());
-    rewriter.insert_operation(ctx, llvm_store.get_operation());
-    rewriter.erase_operation(ctx, op);
-    Ok(())
-}
-
-/// Recover the `repr(align(N))` ABI alignment of `value` at conversion time.
-///
-/// The alignment lives on MIR aggregate types (`abi_align`); the converted
-/// LLVM struct types cannot express over-alignment. The conversion driver may
-/// already have converted the value's type (block arguments are converted
-/// before any rewrite runs; replaced op results carry the new type), but it
-/// records every such change. So check the current type first, then walk the
-/// value's conversion history, newest first, for a MIR type that records an
-/// alignment.
-fn value_abi_align(ctx: &Context, operands_info: &OperandsInfo, value: Value) -> Option<u64> {
-    mir_type_abi_align(ctx, value.get_type(ctx)).or_else(|| {
-        operands_info
-            .lookup_operand_history(value)
-            .iter()
-            .rev()
-            .find_map(|ty| mir_type_abi_align(ctx, *ty))
-    })
-}
-
-/// The MIR type of `value`: its current type when that is still a MIR type,
-/// else the newest MIR type in its conversion history (same walk as
-/// [`value_abi_align`], for the same reason).
-fn value_mir_type(ctx: &Context, operands_info: &OperandsInfo, value: Value) -> TypeHandle {
-    let current = value.get_type(ctx);
-    if current.deref(ctx).is::<MirStructType>() {
-        return current;
-    }
-    operands_info
-        .lookup_operand_history(value)
-        .iter()
-        .rev()
-        .copied()
-        .find(|ty| ty.deref(ctx).is::<MirStructType>())
-        .unwrap_or(current)
-}
-
-/// Refuse only packed by-value images whose physical bytes depend on the
-/// selected NVPTX mode.
-///
-/// Shared-memory pointers are 32-bit in modern NVVM p3:32 but 64-bit in the
-/// PTX/legacy layouts. Lowering runs before that target mode is selected, so a
-/// packed aggregate containing AS3 cannot safely be loaded or stored as one
-/// physical value. Pointer-free packed aggregates and packed aggregates whose
-/// pointers use target-stable address spaces are allowed.
-fn fail_on_target_dependent_packed_aggregate(
-    ctx: &mut Context,
-    ty: TypeHandle,
-    verb: &str,
-) -> Result<()> {
-    let llvm_ty = {
-        let layout = {
-            let ty_ref = ty.deref(ctx);
-            ty_ref
-                .downcast_ref::<MirStructType>()
-                .map(StructLayoutInfo::of_struct)
-        };
-        if let Some(layout) = layout {
-            let map = build_struct_slot_map(ctx, &layout).map_err(anyhow_to_pliron)?;
-            if !map.by_value_layout_faithful {
-                return pliron::input_err_noloc!(
-                    "{} a struct whose rustc layout cannot be represented by an LLVM \
-                     struct value is not supported",
-                    verb
-                );
-            }
-            map.llvm_struct_ty
-        } else {
-            convert_type(ctx, ty).map_err(anyhow_to_pliron)?
-        }
-    };
-    if llvm_packed_struct_contains_pointer_in_address_space(
-        ctx,
-        llvm_ty,
-        llvm_export::types::address_space::SHARED,
-    ) {
-        return pliron::input_err_noloc!(
-            "{} a packed aggregate containing a shared-memory pointer by value is \
-             target-mode dependent and is not yet supported",
-            verb
-        );
-    }
-    Ok(())
-}
-
-fn copy_debug_local_variable(ctx: &mut Context, mir_op: Ptr<Operation>, llvm_op: Ptr<Operation>) {
-    if let Some(info) = llvm_export::ops::debug_local_variable(ctx, mir_op) {
-        llvm_export::ops::set_debug_local_variable(ctx, llvm_op, info);
-    }
-    let projected = llvm_export::ops::debug_projected_variables(ctx, mir_op);
-    if !projected.is_empty() {
-        llvm_export::ops::set_debug_projected_variables(ctx, llvm_op, &projected);
-    }
-    let fragments = llvm_export::ops::debug_fragment_variables(ctx, mir_op);
-    if !fragments.is_empty() {
-        llvm_export::ops::set_debug_fragment_variables(ctx, llvm_op, &fragments);
-    }
-    if let Some(scope) = llvm_export::ops::debug_local_source_scope(ctx, mir_op) {
-        llvm_export::ops::set_debug_local_source_scope(ctx, llvm_op, scope);
-    }
-    if let Some((file, pos)) = llvm_export::ops::debug_local_declaration_location(ctx, mir_op) {
-        llvm_export::ops::set_debug_local_declaration_location(
-            ctx, llvm_op, file, pos.line, pos.column,
-        );
-    }
-    if let Some(expression) = llvm_export::ops::debug_value_expression(ctx, mir_op) {
-        llvm_export::ops::set_debug_value_expression(ctx, llvm_op, &expression);
-    }
-}
-
-/// Carry Rust-local provenance from the MIR alloca to the LLVM alloca.
-///
-/// This is compiler-only metadata stored in the in-memory dialect operation;
-/// it is not emitted as LLVM metadata because an unrecognized metadata node is
-/// not a preservation contract for middle-end passes. The textual exporter
-/// instead consumes the attribute to choose a stable SSA name before `opt`.
-fn copy_local_memory_provenance(
-    ctx: &mut Context,
-    mir_op: Ptr<Operation>,
-    llvm_op: Ptr<Operation>,
-) {
-    if let Some(provenance) = llvm_export::ops::local_memory_provenance(ctx, mir_op) {
-        llvm_export::ops::set_local_memory_provenance(ctx, llvm_op, provenance);
-    }
-}
-
-/// Convert `mir.memcpy` to the matching `llvm.memcpy.p<dst>.p<src>.i<bits>`.
-///
-/// MIR's count is measured in pointee elements, while LLVM's memcpy intrinsic
-/// expects bytes. The pre-conversion destination pointer type still carries the
-/// MIR pointee, so use it to scale the count before emitting the call.
-///
-/// The intrinsic name is an overload: LLVM encodes each pointer's address
-/// space and the length width into it, and its verifier rejects a call whose
-/// argument types disagree with the name. Today every pointer reaching a
-/// `copy_nonoverlapping` is a Rust raw pointer, which cuda-oxide normalizes to
-/// the generic address space (an `addrspacecast` is inserted when the raw
-/// pointer is formed), so the operands are always `p0` and `i64`. We still
-/// derive the suffix from the real operand types rather than hardcoding
-/// `p0.p0.i64`: it matches how every other overloaded intrinsic is named here
-/// (`ctpop`, `fptosi.sat`, ...), and it keeps this lowering correct if raw
-/// pointers ever start carrying a non-generic address space.
-pub(crate) fn convert_memcpy(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    convert_mem_transfer(ctx, rewriter, op, operands_info, "memcpy")
-}
-
-/// Convert `mir.memmove` to the matching `llvm.memmove.p<dst>.p<src>.i<bits>`.
-///
-/// Identical to [`convert_memcpy`] except it emits the overlap-safe
-/// `llvm.memmove` intrinsic. `mir.memmove` backs `core::intrinsics::copy`
-/// (`ptr::copy`); `mir.memcpy` backs the non-overlapping variant.
-pub(crate) fn convert_memmove(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    convert_mem_transfer(ctx, rewriter, op, operands_info, "memmove")
-}
-
-/// Shared lowering for `mir.memcpy` / `mir.memmove`. `intrinsic_base` selects
-/// the LLVM intrinsic family ("memcpy" or "memmove"); both share the same
-/// `(dst, src, len_bytes, isvolatile)` signature and element->byte count scaling.
-///
-/// The element type comes from the op's own `elem_type` attribute, stamped
-/// at build time from dst's pointer type. Operand type history is not
-/// usable here: a kind-only `mir.cast` lowers to a plain value forwarding,
-/// history does not follow that edge, and a stale hit would scale the byte
-/// count by the wrong element size.
-fn convert_mem_transfer(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-    intrinsic_base: &str,
-) -> Result<()> {
-    let operands: Vec<_> = op.deref(ctx).operands().collect();
-    let (dst, src, count) = match operands.as_slice() {
-        [dst, src, count] => (*dst, *src, *count),
-        _ => {
-            return pliron::input_err_noloc!(
-                "{intrinsic_base} operation requires exactly 3 operands"
-            );
-        }
-    };
-
-    let pointee = {
-        let op_ref = op.deref(ctx);
-        op_ref
-            .attributes
-            .get::<pliron::builtin::attributes::TypeAttr>(
-                &format!("{intrinsic_base}_elem_type").try_into().unwrap(),
-            )
-            .map(|attr| attr.get_type(ctx))
-            .ok_or_else(|| {
-                pliron::create_error!(
-                    op_ref.loc(),
-                    pliron::result::ErrorKind::VerificationFailed,
-                    pliron::result::StringError(format!(
-                        "mir.{intrinsic_base} missing its elem_type attribute; \
-                         byte count has no fact to derive from"
-                    ))
-                )
-            })?
-    };
-    // Byte-count policy: exact or error, never guessed. rustc's stride of the
-    // stamped MIR elem type is the primary fact; the converted LLVM type's
-    // natural layout is the fallback.
-    let elem_size = match mir_element_stride(ctx, pointee) {
-        Some(stride) => stride,
-        None => {
-            let elem_ty = convert_type(ctx, pointee).map_err(anyhow_to_pliron)?;
-            match llvm_type_size_align(ctx, elem_ty) {
-                Some((size, _)) => size,
-                None => {
-                    let type_display = pointee.deref(ctx).disp(ctx).to_string();
-                    return Err(pliron::create_error!(
-                        op.deref(ctx).loc(),
-                        pliron::result::ErrorKind::VerificationFailed,
-                        pliron::result::StringError(format!(
-                            "mir.{intrinsic_base} element type `{type_display}` has no exact \
-                             byte size; refusing to guess the copy length"
-                        ))
-                    ));
-                }
-            }
-        }
-    };
-
-    let bytes = if elem_size == 1 {
-        count
-    } else {
-        let count_ty = count.get_type(ctx);
-        let bits = count_ty
-            .deref(ctx)
-            .downcast_ref::<IntegerType>()
-            .map(|ty| ty.width())
-            .unwrap_or(64);
-        let count_int_ty = IntegerType::get(ctx, bits, Signedness::Signless);
-        let size_attr: AttrObj = IntegerAttr::new(
-            count_int_ty,
-            APInt::from_u64(
-                elem_size,
-                std::num::NonZeroUsize::new(bits as usize).unwrap(),
-            ),
-        )
-        .into();
-        let size_const = llvm::ConstantOp::new(ctx, size_attr);
-        let size_val = size_const.get_operation().deref(ctx).get_result(0);
-        rewriter.insert_operation(ctx, size_const.get_operation());
-
-        let flags = IntegerOverflowFlagsAttr::default();
-        let mul = llvm::MulOp::new_with_overflow_flag(ctx, count, size_val, flags);
-        rewriter.insert_operation(ctx, mul.get_operation());
-        mul.get_operation().deref(ctx).get_result(0)
-    };
-
-    let i1_ty = IntegerType::get(ctx, 1, Signedness::Signless);
-    let false_attr: AttrObj = IntegerAttr::new(
-        i1_ty,
-        APInt::from_u64(0, std::num::NonZeroUsize::new(1).unwrap()),
-    )
-    .into();
-    let volatile = llvm::ConstantOp::new(ctx, false_attr);
-    rewriter.insert_operation(ctx, volatile.get_operation());
-    let volatile_val = volatile.get_operation().deref(ctx).get_result(0);
-
-    let void_ty = VoidType::get(ctx);
-    let func_ty = FuncType::get(
-        ctx,
-        void_ty.into(),
-        vec![
-            dst.get_type(ctx),
-            src.get_type(ctx),
-            bytes.get_type(ctx),
-            volatile_val.get_type(ctx),
-        ],
-        false,
-    );
-    let parent_block = op.deref(ctx).get_parent_block().ok_or_else(|| {
-        pliron::create_error!(
-            op.deref(ctx).loc(),
-            pliron::result::ErrorKind::VerificationFailed,
-            pliron::result::StringError(format!("{intrinsic_base} operation has no parent block"))
-        )
-    })?;
-    // Derive the overload suffix from the real (already type-converted)
-    // operands so the name can never disagree with the argument types.
-    let dst_ty = dst.get_type(ctx);
-    let dst_as = dst_ty
-        .deref(ctx)
-        .downcast_ref::<llvm_export::types::PointerType>()
-        .map(|pt| pt.address_space())
-        .unwrap_or(0);
-    let src_ty = src.get_type(ctx);
-    let src_as = src_ty
-        .deref(ctx)
-        .downcast_ref::<llvm_export::types::PointerType>()
-        .map(|pt| pt.address_space())
-        .unwrap_or(0);
-    let len_bits = bytes
-        .get_type(ctx)
-        .deref(ctx)
-        .downcast_ref::<IntegerType>()
-        .map(|t| t.width())
-        .unwrap_or(64);
-    let intrinsic_name = format!("llvm_{intrinsic_base}_p{dst_as}_p{src_as}_i{len_bits}");
-    helpers::ensure_intrinsic_declared(ctx, parent_block, &intrinsic_name, func_ty)
-        .map_err(anyhow_to_pliron)?;
-
-    let callee: Identifier = intrinsic_name.as_str().try_into().map_err(|e| {
-        pliron::create_error!(
-            op.deref(ctx).loc(),
-            pliron::result::ErrorKind::VerificationFailed,
-            pliron::result::StringError(format!("Invalid memcpy intrinsic name: {e:?}"))
-        )
-    })?;
-    let call = llvm::CallOp::new(
-        ctx,
-        CallOpCallable::Direct(callee),
-        func_ty,
-        vec![dst, src, bytes, volatile_val],
-    );
-    crate::convert::preserve_location(ctx, op, call.get_operation());
-    rewriter.insert_operation(ctx, call.get_operation());
-    rewriter.erase_operation(ctx, op);
-    Ok(())
-}
-
-/// Alignment the op that computed `ptr` recorded about the address it produced.
-///
-/// Field addresses stamp this during their own conversion, where the aggregate's
-/// `abi_align` is still in hand; by the time a load that consumes the address is
-/// converted, `mir.field_addr` is already a GEP and the MIR aggregate type is no
-/// longer reachable from the load's operands.
-///
-/// Known fidelity limit: the claim rides the address value, not the place
-/// access that justified it. `&raw const (*p).x` through a merely 4-aligned
-/// `p: *const Aligned8` is legal Rust so long as the place itself is never
-/// accessed, yet the later read through the raw pointer consumes this same
-/// stamped GEP and inherits the aggregate's alignment, an over-claim for that
-/// pointer. rustc keeps the two apart by threading alignment through place
-/// evaluation and dropping it at the `&raw` boundary; dialect-mir erases that
-/// distinction before lowering runs, so full fidelity would require stamping
-/// loads during MIR translation instead. Accepted for now: the pattern needs
-/// an actually under-aligned pointer to an over-aligned aggregate, projected
-/// via `&raw` inside a kernel, and any direct access through such a place is
-/// UB to begin with.
-fn pointer_proved_alignment(ctx: &Context, ptr: Value) -> Option<u64> {
-    let defining_op = ptr.defining_op()?;
-    llvm_export::ops::address_alignment(ctx, defining_op).map(u64::from)
-}
-
-/// Convert `mir.load` to `llvm.load`.
-///
-/// Takes a single pointer operand and returns the loaded value.
-/// The result type is derived from the MIR operation's result type.
-pub(crate) fn convert_load(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let ptr = op.deref(ctx).get_operand(0);
-    let result_ty = op.deref(ctx).get_result(0).get_type(ctx);
-
-    // Packed whole-value loads are byte-faithful now that divergent rustc
-    // layouts lower to LLVM packed structs. Keep only the target-dependent AS3
-    // physical-image case fail-closed.
-    fail_on_target_dependent_packed_aggregate(ctx, result_ty, "loading")?;
-
-    let llvm_ty = convert_type(ctx, result_ty).map_err(anyhow_to_pliron)?;
-
-    let llvm_load = llvm::LoadOp::new(ctx, ptr, llvm_ty);
-    if dialect_mir::ops::MirLoadOp::new(op).is_volatile(ctx) {
-        llvm_export::ops::set_op_volatile(ctx, llvm_load.get_operation(), true);
-    }
-    // The loaded value's ABI alignment comes from this op's own result type,
-    // which is still the MIR type: result types are only converted by the
-    // op's own rewrite. A scalar records none, so fall back to whatever the
-    // address itself proved when it was computed -- for a field projection
-    // that is the aggregate's `abi_align` narrowed to the field's offset,
-    // which is otherwise lost here and costs the pair its vectorization.
-    // When both answer, the weaker wins: a field of a packed aggregate can
-    // place an abi-aligned type at a byte-aligned address, and the address's
-    // proved alignment is the ceiling of what the load may claim.
-    let abi = mir_type_abi_align(ctx, result_ty);
-    let proved = pointer_proved_alignment(ctx, ptr);
-    let align = match (abi, proved) {
-        (Some(abi), Some(proved)) => Some(abi.min(proved)),
-        (abi, proved) => abi.or(proved),
-    };
-    if let Some(align) = align {
-        llvm_export::ops::set_op_alignment(ctx, llvm_load.get_operation(), align as u32);
-    }
-    rewriter.insert_operation(ctx, llvm_load.get_operation());
-    rewriter.replace_operation(ctx, op, llvm_load.get_operation());
-
-    Ok(())
-}
-
-/// Convert `mir.dbg_value` to the LLVM-export debug marker.
-///
-/// The op is still debug-only after lowering. The textual LLVM exporter later
-/// prints it as an `llvm.dbg.value` intrinsic call.
-pub(crate) fn convert_dbg_value(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let value = op.deref(ctx).get_operand(0);
-    let loc = op.deref(ctx).loc().clone();
-    let llvm_dbg_value = llvm::DebugValueOp::new(ctx, value);
-    llvm_dbg_value.get_operation().deref_mut(ctx).set_loc(loc);
-    copy_debug_local_variable(ctx, op, llvm_dbg_value.get_operation());
-    rewriter.insert_operation(ctx, llvm_dbg_value.get_operation());
-    rewriter.erase_operation(ctx, op);
-    Ok(())
-}
-
-/// Convert `mir.dbg_value_list` to the LLVM-export multi-value debug marker.
-///
-/// The ordered operands become a `DIArgList` during textual export. The typed
-/// location recipe is carried as generic metadata and copied unchanged here.
-pub(crate) fn convert_dbg_value_list(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let values: Vec<_> = op.deref(ctx).operands().collect();
-    if values.len() < 2 {
-        return pliron::input_err_noloc!("mir.dbg_value_list requires at least two operands");
-    }
-    if llvm_export::ops::debug_value_expression(ctx, op).is_none() {
-        return pliron::input_err_noloc!("mir.dbg_value_list is missing its debug expression");
-    }
-
-    let loc = op.deref(ctx).loc().clone();
-    let llvm_dbg_value = llvm::DebugValueListOp::new(ctx, values);
-    llvm_dbg_value.get_operation().deref_mut(ctx).set_loc(loc);
-    copy_debug_local_variable(ctx, op, llvm_dbg_value.get_operation());
-    rewriter.insert_operation(ctx, llvm_dbg_value.get_operation());
-    rewriter.erase_operation(ctx, op);
-    Ok(())
-}
-
-/// Convert `mir.alloca` to `llvm.alloca`.
-///
-/// `mir.alloca` carries its element type on the result pointer's pointee, and
-/// emits a single-element stack slot of that type. We therefore convert the
-/// pointee to an LLVM type and emit `llvm.alloca <pointee_ty>, i32 1`.
-///
-/// No value is stored into the slot; that is the caller's job via subsequent
-/// `mir.store` / `llvm.store` ops. This matches the mem2reg-ready translator
-/// model where every local is backed by one alloca in the entry block and
-/// defs/uses go through `store`/`load` rather than SSA values.
-pub(crate) fn convert_alloca(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let result_ty = op.deref(ctx).get_result(0).get_type(ctx);
-    let mir_pointee = {
-        let ty_ref = result_ty.deref(ctx);
-        let mir_ptr = ty_ref.downcast_ref::<MirPtrType>().ok_or_else(|| {
-            anyhow_to_pliron(anyhow::anyhow!(
-                "MirAllocaOp result must be MirPtrType (enforced by verifier)"
-            ))
-        })?;
-        mir_ptr.pointee
-    };
-    let llvm_pointee = convert_type(ctx, mir_pointee).map_err(anyhow_to_pliron)?;
-
-    let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-    let one_apint =
-        pliron::utils::apint::APInt::from_i64(1, std::num::NonZeroUsize::new(32).unwrap());
-    let one_attr = pliron::builtin::attributes::IntegerAttr::new(i32_ty, one_apint);
-    let one_const = llvm::ConstantOp::new(ctx, one_attr.into());
-    rewriter.insert_operation(ctx, one_const.get_operation());
-    let one_val = one_const.get_operation().deref(ctx).get_result(0);
-
-    let alloca = llvm::AllocaOp::new(ctx, llvm_pointee, one_val);
-    // The allocated type's ABI alignment comes from this op's own result
-    // pointee, which is still the MIR type at rewrite time.
-    if let Some(align) = mir_type_abi_align(ctx, mir_pointee) {
-        llvm_export::ops::set_op_alignment(ctx, alloca.get_operation(), align as u32);
-    }
-    copy_debug_local_variable(ctx, op, alloca.get_operation());
-    copy_local_memory_provenance(ctx, op, alloca.get_operation());
-    rewriter.insert_operation(ctx, alloca.get_operation());
-    rewriter.replace_operation(ctx, op, alloca.get_operation());
-
-    Ok(())
-}
-
-/// Convert `mir.ref` — materialize the operand in stack memory via alloca+store.
-///
-/// `mir.ref` creates a pointer to an SSA value. In SSA form, values don't have
-/// addresses, so we must place the value in memory to obtain a pointer.
-/// This applies to all types: scalars (e.g. `&factor` where factor is `u32`),
-/// aggregates (e.g. `&closure_env`), and pointers (e.g. `&&T`).
-pub(crate) fn convert_ref(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    operands_info: &OperandsInfo,
-) -> Result<()> {
-    let operand = op.deref(ctx).get_operand(0);
-    let operand_ty = operand.get_type(ctx);
-    let abi_align = value_abi_align(ctx, operands_info, operand);
-
-    let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
-    let one_apint =
-        pliron::utils::apint::APInt::from_i64(1, std::num::NonZeroUsize::new(32).unwrap());
-    let one_attr = pliron::builtin::attributes::IntegerAttr::new(i32_ty, one_apint);
-    let one_const = llvm::ConstantOp::new(ctx, one_attr.into());
-    rewriter.insert_operation(ctx, one_const.get_operation());
-    let one_val = one_const.get_operation().deref(ctx).get_result(0);
-
-    let alloca = llvm::AllocaOp::new(ctx, operand_ty, one_val);
-    // Honour the referent's repr(align(N)) ABI alignment. Without this, the
-    // synthesised alloca would be under-aligned relative to any loads/stores
-    // that claim the struct's true alignment.
-    if let Some(align) = abi_align {
-        llvm_export::ops::set_op_alignment(ctx, alloca.get_operation(), align as u32);
-    }
-    rewriter.insert_operation(ctx, alloca.get_operation());
-    let alloca_ptr = alloca.get_operation().deref(ctx).get_result(0);
-
-    let store = llvm::StoreOp::new(ctx, operand, alloca_ptr);
-    if let Some(align) = abi_align {
-        llvm_export::ops::set_op_alignment(ctx, store.get_operation(), align as u32);
-    }
-    rewriter.insert_operation(ctx, store.get_operation());
-
-    rewriter.replace_operation_with_values(ctx, op, vec![alloca_ptr]);
-
-    Ok(())
-}
-
-/// Convert `mir.ptr_offset` to `llvm.getelementptr`.
-///
-/// Operands: `[ptr, offset]` where offset is an integer index.
-/// Element sizing comes from the op's own result type, which is still the
-/// MIR pointer type when this converter runs. The operand's recorded type
-/// history is not usable here: a kind-only `mir.cast` lowers to a plain
-/// value forwarding, and the history does not follow that replacement
-/// edge, so a history miss would silently misscale the offset.
-pub(crate) fn convert_ptr_offset(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-) -> Result<()> {
-    let loc = op.deref(ctx).loc();
-    let operands: Vec<_> = op.deref(ctx).operands().collect();
-
-    let (ptr, offset) = match operands.as_slice() {
-        [ptr, offset] => (*ptr, *offset),
-        _ => return pliron::input_err!(loc, "PtrOffset requires exactly 2 operands"),
-    };
-
-    let result_ty = op.deref(ctx).get_result(0).get_type(ctx);
-    let pointee = result_ty
-        .deref(ctx)
-        .downcast_ref::<MirPtrType>()
-        .map(|mir_ptr| mir_ptr.pointee)
-        .ok_or_else(|| {
-            pliron::input_error!(
-                loc.clone(),
-                "mir.ptr_offset result must be a MIR pointer type; \
-                 element sizing has no fact to derive from"
-            )
-        })?;
-    let elem_ty = convert_type(ctx, pointee).map_err(anyhow_to_pliron)?;
-
-    let llvm_gep = llvm::GetElementPtrOp::new(
-        ctx,
-        ptr,
-        vec![llvm_export::ops::GepIndex::Value(offset)],
-        elem_ty,
-    );
-    let inbounds = dialect_mir::ops::MirPtrOffsetOp::new(op).is_inbounds(ctx);
-    llvm::set_gep_inbounds(ctx, llvm_gep.get_operation(), inbounds);
-    rewriter.insert_operation(ctx, llvm_gep.get_operation());
-    rewriter.replace_operation(ctx, op, llvm_gep.get_operation());
-
-    Ok(())
-}
-
-/// Convert `mir.shared_alloc` to LLVM global variable in shared address space.
-///
-/// GPU shared memory is represented as a global variable with address space 3.
-/// Uses `shared_globals` to deduplicate: multiple allocations with the same
-/// `alloc_key` share the same global.
-///
-/// Called directly from `MirToLlvmConversionDriver::rewrite` (not through
-/// op_cast dispatch) because it needs the cross-function `SharedGlobalsMap`.
-pub fn convert_shared_alloc_dc(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-    shared_globals: &mut SharedGlobalsMap,
-    next_shared_mem_index: &mut usize,
-) -> Result<()> {
-    use pliron::builtin::attributes::{IntegerAttr, TypeAttr};
-
-    let (alloc_key, source_name, mir_elem_type, size, alignment, debug_info, debug_owner_function) = {
-        let shared_alloc_op = dialect_mir::ops::MirSharedAllocOp::new(op);
-        let op_ref = op.deref(ctx);
-
-        let alloc_key: Option<String> = shared_alloc_op
-            .get_attr_alloc_key(ctx)
-            .map(|s| String::from((*s).clone()));
-
-        // Optional and diagnostic: the Rust path of the originating `static`,
-        // carried through so the emitted global can name its source.
-        let source_name: Option<String> = shared_alloc_op
-            .get_attr_source_name(ctx)
-            .map(|s| String::from((*s).clone()));
-
-        let elem_type_attr = op_ref
-            .attributes
-            .get::<TypeAttr>(&"elem_type".try_into().unwrap())
-            .ok_or_else(|| {
-                anyhow_to_pliron(anyhow::anyhow!(
-                    "MirSharedAllocOp missing elem_type TypeAttr attribute"
-                ))
-            })?;
-        let mir_elem_type = elem_type_attr.get_type(ctx);
-
-        let size_attr = op_ref
-            .attributes
-            .get::<IntegerAttr>(&"size".try_into().unwrap())
-            .ok_or_else(|| {
-                anyhow_to_pliron(anyhow::anyhow!(
-                    "MirSharedAllocOp missing size IntegerAttr attribute"
-                ))
-            })?;
-        let size = size_attr.value().to_u64();
-
-        let alignment = shared_alloc_op.get_alignment_value(ctx).unwrap_or(0);
-        let debug_info = llvm::debug_global_variable(ctx, op);
-        let debug_owner_function = llvm::debug_global_owner_function(ctx, op);
-
-        (
-            alloc_key,
-            source_name,
-            mir_elem_type,
-            size,
-            alignment,
-            debug_info,
-            debug_owner_function,
-        )
-    };
-
-    // A shared variable DIE must describe the physical allocation. Gate the
-    // optional debug identity against the lowered element layout before it
-    // can reach the declaration record or the emitted global.
-    let llvm_elem_type = convert_type(ctx, mir_elem_type).map_err(anyhow_to_pliron)?;
-    let debug_info = debug_info
-        .filter(|info| shared_debug_type_matches_physical(ctx, info, llvm_elem_type, size));
-    let debug_owner_function = debug_info.as_ref().and(debug_owner_function);
-
-    let declaration = SharedGlobalDeclaration {
-        kind: SharedGlobalKind::Static,
-        mir_elem_type,
-        size,
-        alignment,
-        debug_info,
-        debug_owner_function,
-    };
-
-    // A key names one physical allocation, not merely a preferred symbol.
-    // Reuse it only when the complete storage declaration agrees; otherwise
-    // the later address would silently inherit the first allocation's type,
-    // extent, or alignment.
-    let global_name = if let Some(key) = alloc_key.as_ref()
-        && let Some(existing) = shared_globals.get(key)
-    {
-        if !existing.declaration.same_storage(&declaration) {
-            return Err(anyhow_to_pliron(anyhow::anyhow!(
-                "duplicate shared alloc_key {:?} has an incompatible declaration",
-                key
-            )));
-        }
-        let symbol = existing.symbol.clone();
-        let debug_identity_matches = existing.declaration.debug_info == declaration.debug_info
-            && existing.declaration.debug_owner_function == declaration.debug_owner_function;
-        if !debug_identity_matches {
-            // One physical allocation reached under two debug identities, for
-            // example a function-local static whose owning function was
-            // materialized (or inlined) into two kernels. Debug metadata must
-            // never fail a build that a release build accepts, and DWARF
-            // cannot truthfully scope one AS3 object to two subprograms, so
-            // fail open: drop the attachment from the materialized global and
-            // demote the cached record to metadata-free.
-            strip_shared_debug_identity(ctx, op, &symbol)?;
-            if let Some(record) = shared_globals.get_mut(key) {
-                record.declaration.debug_info = None;
-                record.declaration.debug_owner_function = None;
-            }
-        }
-        symbol
-    } else {
-        create_shared_global(
-            ctx,
-            op,
-            shared_globals,
-            next_shared_mem_index,
-            SharedAllocSpec {
-                mir_elem_type,
-                size,
-                alignment,
-                alloc_key,
-                source_name: source_name.as_deref(),
-                debug_info: declaration.debug_info.as_ref(),
-                debug_owner_function: declaration.debug_owner_function.as_deref(),
-            },
-        )?
-    };
-
-    let address_of_op = llvm::AddressOfOp::new(ctx, global_name, 3);
-    rewriter.insert_operation(ctx, address_of_op.get_operation());
-    rewriter.replace_operation(ctx, op, address_of_op.get_operation());
-
-    Ok(())
-}
-
-/// Everything `create_shared_global` needs about one `mir.shared_alloc`.
-///
-/// Mirrors [`DeviceGlobalSpec`] for the shared-memory path.
-struct SharedAllocSpec<'a> {
-    mir_elem_type: TypeHandle,
-    size: u64,
-    alignment: u64,
-    alloc_key: Option<String>,
-    source_name: Option<&'a str>,
-    debug_info: Option<&'a llvm::DebugGlobalVariableInfo>,
-    debug_owner_function: Option<&'a str>,
-}
-
-/// Create a shared memory global variable in the module.
-///
-/// Creates an LLVM global variable with:
-/// - Array type: `[size x element_type]`
-/// - Address space 3 (shared memory)
-/// - Optional alignment
-/// - Unique generated name (`__shared_mem_N`)
-///
-/// The global is inserted at the front of the module block. When
-/// `spec.alloc_key` is `Some`, the key is moved into `shared_globals` so that
-/// later allocations with the same key reuse this global only after the caller
-/// has checked that their complete declarations agree.
-///
-/// `spec.source_name`, when present, is the Rust path of the `static` this
-/// allocation came from. The generated symbol stays anonymous; the name is
-/// recorded as an attribute on the global so the exporter can render it
-/// beside the definition. Only the allocation that *creates* the global
-/// contributes a name — a later allocation with the same `alloc_key` hits
-/// the cache and never reaches this function — which is consistent because
-/// the key and the name are both derived from the same constant.
-///
-/// `next_shared_mem_index` is scoped to one `MirToLlvmConversionDriver`
-/// instance (one module), not a process-global counter: `N` is a function of
-/// this module's own MIR walk order, not of how many other modules have
-/// lowered a shared allocation earlier in the process (#706).
-fn create_shared_global(
-    ctx: &mut Context,
-    op: Ptr<Operation>,
-    shared_globals: &mut SharedGlobalsMap,
-    next_shared_mem_index: &mut usize,
-    spec: SharedAllocSpec<'_>,
-) -> Result<pliron::identifier::Identifier> {
-    let llvm_elem_type = convert_type(ctx, spec.mir_elem_type).map_err(anyhow_to_pliron)?;
-    let array_type = ArrayType::get(ctx, llvm_elem_type, spec.size);
-
-    let counter = *next_shared_mem_index;
-    *next_shared_mem_index += 1;
-    let name: pliron::identifier::Identifier =
-        format!("__shared_mem_{counter}").try_into().unwrap();
-
-    let global_op = if spec.alignment > 0 {
-        llvm::GlobalOp::new_with_alignment(ctx, name.clone(), array_type.into(), spec.alignment)
-    } else {
-        llvm::GlobalOp::new(ctx, name.clone(), array_type.into())
-    };
-    global_op.set_address_space(ctx, llvm_export::types::address_space::SHARED);
-    if let Some(source_name) = spec.source_name {
-        use llvm_export::ops::GlobalOpExt;
-        global_op.set_shared_source_name(ctx, source_name);
-    }
-    if let Some(info) = spec.debug_info {
-        llvm::set_debug_global_variable(ctx, global_op.get_operation(), info);
-    }
-    if let Some(owner) = spec.debug_owner_function {
-        llvm::set_debug_global_owner_function(ctx, global_op.get_operation(), owner);
-    }
-
-    let parent_block = op
-        .deref(ctx)
-        .get_parent_block()
-        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Op has no parent block")))?;
-    let module_op = helpers::get_module_from_block(ctx, parent_block).map_err(anyhow_to_pliron)?;
-    let region = module_op.deref(ctx).get_region(0);
-    let module_block = region
-        .deref(ctx)
-        .iter(ctx)
-        .next()
-        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Module is empty")))?;
-
-    global_op.get_operation().insert_at_front(module_block, ctx);
-
-    if let Some(key) = spec.alloc_key {
-        shared_globals.insert(
-            key,
-            SharedGlobalRecord {
-                symbol: name.clone(),
-                declaration: SharedGlobalDeclaration {
-                    kind: SharedGlobalKind::Static,
-                    mir_elem_type: spec.mir_elem_type,
-                    size: spec.size,
-                    alignment: spec.alignment,
-                    debug_info: spec.debug_info.cloned(),
-                    debug_owner_function: spec.debug_owner_function.map(str::to_owned),
-                },
-            },
-        );
-    }
-
-    Ok(name)
-}
-
-/// A shared variable DIE must describe the compiler-materialized allocation,
-/// never the marker ZST or an element graph whose pointer base types are not
-/// representable yet. The frontend checks semantic element layout; this final
-/// boundary verifies total physical bits/count against the LLVM backing.
-fn shared_debug_type_matches_physical(
-    ctx: &Context,
-    info: &llvm::DebugGlobalVariableInfo,
-    llvm_elem_type: TypeHandle,
-    count: u64,
-) -> bool {
-    let Some((element_size, _)) = llvm_type_size_align(ctx, llvm_elem_type) else {
-        return false;
-    };
-    let Some(element_bytes) = element_size.checked_mul(count) else {
-        return false;
-    };
-    let Some(physical_bits) = element_bytes.checked_mul(8) else {
-        return false;
-    };
-    if info.ty.size_bits() != physical_bits {
-        return false;
-    }
-    match &info.ty {
-        llvm::DebugLocalTypeKind::Array {
-            element,
-            count: debug_count,
-            ..
-        } => *debug_count == count && element.size_bits() == element_size.saturating_mul(8),
-        // `Barrier` retains its semantic repr(C) struct while the backing is
-        // one i64. Other marker types are never admitted by the frontend.
-        llvm::DebugLocalTypeKind::Struct { .. } => count == 1,
-        _ => false,
-    }
-}
-
-/// Detach the debug identity from an already-materialized shared global.
-///
-/// The fail-open path for divergent debug identities on one `alloc_key`:
-/// the storage stays shared and valid, only the optional DWARF attachment is
-/// dropped so it cannot misattribute the allocation to the wrong static or
-/// owner function.
-fn strip_shared_debug_identity(
-    ctx: &mut Context,
-    op: Ptr<Operation>,
-    name: &pliron::identifier::Identifier,
-) -> Result<()> {
-    let parent_block = op
-        .deref(ctx)
-        .get_parent_block()
-        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Op has no parent block")))?;
-    let module_op = helpers::get_module_from_block(ctx, parent_block).map_err(anyhow_to_pliron)?;
-    let module_block = module_op
-        .deref(ctx)
-        .get_region(0)
-        .deref(ctx)
-        .iter(ctx)
-        .next()
-        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Module is empty")))?;
-    let existing = module_block
-        .deref(ctx)
-        .iter(ctx)
-        .filter_map(|candidate| Operation::get_op::<llvm::GlobalOp>(candidate, ctx))
-        .find(|global| global.get_symbol_name(ctx) == *name)
-        .ok_or_else(|| {
-            anyhow_to_pliron(anyhow::anyhow!(
-                "shared allocation cache refers to missing LLVM global `@{name}`"
-            ))
-        })?;
-    llvm::clear_debug_global_identity(ctx, existing.get_operation());
-    Ok(())
-}
-
-/// Convert `mir.global_alloc` to an LLVM global in CUDA global memory.
-///
-/// Ordinary Rust `static` / `static mut` values have grid scope and
-/// application lifetime, so they live in address space 1 rather than the
-/// per-block shared-memory address space.
-pub fn convert_global_alloc_dc(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-    device_globals: &mut DeviceGlobalsMap,
-    next_device_global_index: &mut usize,
-) -> Result<()> {
-    use pliron::builtin::attributes::{StringAttr, TypeAttr};
-
-    let (
-        global_key,
-        mir_global_type,
-        alignment,
-        addr_space,
-        initializer_hex,
-        initializer_relocations,
-        immutable,
-        debug_info,
-    ) = {
-        let global_op = dialect_mir::ops::MirGlobalAllocOp::new(op);
-        let op_ref = op.deref(ctx);
-
-        let global_key_attr = op_ref
-            .attributes
-            .get::<StringAttr>(&"global_key".try_into().unwrap())
-            .ok_or_else(|| {
-                anyhow_to_pliron(anyhow::anyhow!(
-                    "MirGlobalAllocOp missing global_key StringAttr attribute"
-                ))
-            })?;
-        let global_key = String::from((*global_key_attr).clone());
-
-        let global_type_attr = op_ref
-            .attributes
-            .get::<TypeAttr>(&"global_type".try_into().unwrap())
-            .ok_or_else(|| {
-                anyhow_to_pliron(anyhow::anyhow!(
-                    "MirGlobalAllocOp missing global_type TypeAttr attribute"
-                ))
-            })?;
-        let mir_global_type = global_type_attr.get_type(ctx);
-
-        let alignment = global_op.get_alignment_value(ctx).unwrap_or(0);
-        let initializer_hex = op_ref
-            .attributes
-            .get::<StringAttr>(&"global_initializer_hex".try_into().unwrap())
-            .map(|attr| String::from((*attr).clone()));
-        let initializer_relocations = op_ref
-            .attributes
-            .get::<StringAttr>(&"global_initializer_relocations".try_into().unwrap())
-            .map(|attr| String::from((*attr).clone()));
-        let debug_info = llvm::debug_global_variable(ctx, op);
-
-        // Read the address space the op's result already carries — set by
-        // mir-importer based on the static's type (`ConstantMemory<T>` → 4,
-        // ordinary → 1). The dialect verifier accepts both.
-        let res_ty = op_ref.get_result(0).get_type(ctx);
-        let addr_space = res_ty
-            .deref(ctx)
-            .downcast_ref::<dialect_mir::types::MirPtrType>()
-            .map(|p| {
-                if p.address_space == dialect_mir::types::address_space::CONSTANT {
-                    llvm_export::types::address_space::CONSTANT
-                } else {
-                    llvm_export::types::address_space::GLOBAL
-                }
-            })
-            .ok_or_else(|| {
-                anyhow_to_pliron(anyhow::anyhow!(
-                    "MirGlobalAllocOp result is not a MirPtrType"
-                ))
-            })?;
-
-        (
-            global_key,
-            mir_global_type,
-            alignment,
-            addr_space,
-            initializer_hex,
-            initializer_relocations,
-            global_op.is_immutable(ctx),
-            debug_info,
-        )
-    };
-
-    let declaration = DeviceGlobalDeclaration {
-        mir_type: mir_global_type,
-        alignment,
-        addr_space,
-        initializer_hex: initializer_hex.clone(),
-        initializer_relocations: initializer_relocations.clone(),
-        debug_info: debug_info.clone(),
-        immutable,
-    };
-
-    let global_name = if let Some(existing) = device_globals.get(&global_key) {
-        if existing.declaration != declaration {
-            return Err(anyhow_to_pliron(anyhow::anyhow!(
-                "duplicate global_key {:?} has an incompatible declaration",
-                global_key
-            )));
-        }
-        existing.symbol.clone()
-    } else {
-        create_device_global(
-            ctx,
-            op,
-            device_globals,
-            next_device_global_index,
-            DeviceGlobalSpec {
-                key: &global_key,
-                mir_type: mir_global_type,
-                alignment,
-                addr_space,
-                initializer_hex: initializer_hex.as_deref(),
-                initializer_relocations: initializer_relocations.as_deref(),
-                debug_info: debug_info.as_ref(),
-                immutable,
-            },
-        )?
-    };
-
-    let address_of_op = llvm::AddressOfOp::new(ctx, global_name, addr_space);
-    rewriter.insert_operation(ctx, address_of_op.get_operation());
-    rewriter.replace_operation(ctx, op, address_of_op.get_operation());
-
-    Ok(())
-}
-
-struct DeviceGlobalSpec<'a> {
-    key: &'a str,
-    mir_type: TypeHandle,
-    alignment: u64,
-    addr_space: u32,
-    initializer_hex: Option<&'a str>,
-    initializer_relocations: Option<&'a str>,
-    debug_info: Option<&'a llvm::DebugGlobalVariableInfo>,
-    /// Nothing writes this storage, so it exports as LLVM `constant`. Set only
-    /// for the compiler's own promoted constants; see `MirGlobalAllocOp`.
-    immutable: bool,
-}
-
-/// `next_device_global_index` is scoped to one `MirToLlvmConversionDriver`
-/// instance (one module), not a process-global counter: `N` is a function of
-/// this module's own MIR walk order, not of how many other modules have
-/// lowered a device global earlier in the process (#706).
-fn create_device_global(
-    ctx: &mut Context,
-    op: Ptr<Operation>,
-    device_globals: &mut DeviceGlobalsMap,
-    next_device_global_index: &mut usize,
-    spec: DeviceGlobalSpec<'_>,
-) -> Result<pliron::identifier::Identifier> {
-    // An explicit initializer is already the evaluated Rust allocation image.
-    // Pointer-free data stays `[N x i8]`. Initializers with relocations use a
-    // segmented LLVM struct whose literal spans remain byte arrays and whose
-    // pointer slots become pointer-width integers. This preserves both exact
-    // bytes and linker-visible pointer provenance.
-    let semantic_llvm_type = convert_type(ctx, spec.mir_type).map_err(anyhow_to_pliron)?;
-    let (llvm_global_type, alignment) = if let Some(initializer_hex) = spec.initializer_hex {
-        let byte_count = initializer_hex_byte_count(initializer_hex).map_err(anyhow_to_pliron)?;
-        if spec.alignment == 0 {
-            return Err(anyhow_to_pliron(anyhow::anyhow!(
-                "device global initializer is missing its evaluated Rust allocation alignment"
-            )));
-        }
-        let storage_type = if let Some(encoded) = spec.initializer_relocations {
-            validate_relocated_initialized_global_layout(
-                ctx,
-                spec.mir_type,
-                byte_count,
-                spec.alignment,
-            )
-            .map_err(anyhow_to_pliron)?;
-            relocated_initializer_storage_type(ctx, byte_count, spec.alignment, encoded)
-                .map_err(anyhow_to_pliron)?
-        } else {
-            validate_initialized_global_layout(ctx, spec.mir_type, byte_count, spec.alignment)
-                .map_err(anyhow_to_pliron)?;
-            let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
-            ArrayType::get(ctx, i8_ty.into(), byte_count).into()
-        };
-        (storage_type, spec.alignment)
-    } else {
-        if spec.initializer_relocations.is_some() {
-            return Err(anyhow_to_pliron(anyhow::anyhow!(
-                "device global carries relocation metadata without initializer bytes"
-            )));
-        }
-        (semantic_llvm_type, spec.alignment)
-    };
-
-    // Constant-memory globals reuse the Rust-side mangled name so host code can
-    // resolve them by name via `cuModuleGetGlobal`. Ordinary device globals
-    // are private to the kernel and get a counter-based unique name.
-    let name: pliron::identifier::Identifier =
-        if spec.addr_space == llvm_export::types::address_space::CONSTANT {
-            let symbol = dialect_mir::ops::rust_static_symbol_from_global_key(spec.key)
-                .ok_or_else(|| {
-                    anyhow_to_pliron(anyhow::anyhow!(
-                        "constant global_key {:?} is not a tagged Rust static identity",
-                        spec.key
-                    ))
-                })?;
-            symbol.try_into().map_err(|e| {
-                anyhow_to_pliron(anyhow::anyhow!(
-                    "constant Rust static symbol {:?} is not a valid identifier: {e:?}",
-                    symbol
-                ))
-            })?
-        } else {
-            let counter = *next_device_global_index;
-            *next_device_global_index += 1;
-            format!("__device_global_{counter}").try_into().unwrap()
-        };
-
-    let global_op = if alignment > 0 {
-        llvm::GlobalOp::new_with_alignment(ctx, name.clone(), llvm_global_type, alignment)
-    } else {
-        llvm::GlobalOp::new(ctx, name.clone(), llvm_global_type)
-    };
-    global_op.set_address_space(ctx, spec.addr_space);
-    global_op.set_source_global_key(ctx, spec.key);
-    if spec.addr_space == llvm_export::types::address_space::GLOBAL
-        && let Some(info) = spec.debug_info
-    {
-        llvm::set_debug_global_variable(ctx, global_op.get_operation(), info);
-    }
-    if let Some(initializer_hex) = spec.initializer_hex {
-        global_op.set_initializer_hex(ctx, initializer_hex);
-    }
-    if let Some(initializer_relocations) = spec.initializer_relocations {
-        global_op.set_initializer_relocations(ctx, initializer_relocations);
-    }
-    if spec.immutable {
-        global_op.mark_immutable(ctx);
-    }
-
-    let parent_block = op
-        .deref(ctx)
-        .get_parent_block()
-        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Op has no parent block")))?;
-    let module_op = helpers::get_module_from_block(ctx, parent_block).map_err(anyhow_to_pliron)?;
-    let region = module_op.deref(ctx).get_region(0);
-    let module_block = region
-        .deref(ctx)
-        .iter(ctx)
-        .next()
-        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Module is empty")))?;
-
-    global_op.get_operation().insert_at_front(module_block, ctx);
-    device_globals.insert(
-        spec.key.to_string(),
-        DeviceGlobalRecord {
-            symbol: name.clone(),
-            declaration: DeviceGlobalDeclaration {
-                mir_type: spec.mir_type,
-                alignment: spec.alignment,
-                addr_space: spec.addr_space,
-                initializer_hex: spec.initializer_hex.map(str::to_owned),
-                initializer_relocations: spec.initializer_relocations.map(str::to_owned),
-                debug_info: spec.debug_info.cloned(),
-                immutable: spec.immutable,
-            },
-        },
-    );
-
-    Ok(name)
-}
-
-fn relocated_initializer_storage_type(
-    ctx: &mut Context,
-    byte_count: u64,
-    allocation_alignment: u64,
-    encoded: &str,
-) -> std::result::Result<TypeHandle, anyhow::Error> {
-    let mut relocations =
-        llvm::decode_global_initializer_relocations(encoded).map_err(anyhow::Error::msg)?;
-    if relocations.is_empty() {
-        anyhow::bail!("device global relocation metadata contains no relocations");
-    }
-    relocations.sort_by_key(|relocation| relocation.source_offset);
-
-    let mut cursor = 0u64;
-    let mut fields = Vec::with_capacity(relocations.len() * 2 + 1);
-    let mut requires_packed_storage = false;
-    let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
-
-    for (index, relocation) in relocations.iter().enumerate() {
-        if relocation.width_bytes != 8 {
-            anyhow::bail!(
-                "device global relocation {index} uses unsupported {}-byte pointer storage; CUDA global/constant pointers require 8 bytes",
-                relocation.width_bytes
-            );
-        }
-        if !matches!(relocation.target_address_space, 1 | 4) {
-            anyhow::bail!(
-                "device global relocation {index} targets unsupported CUDA address space {}",
-                relocation.target_address_space
-            );
-        }
-        if relocation.target_key.is_empty() {
-            anyhow::bail!("device global relocation {index} has an empty target key");
-        }
-
-        let width = u64::from(relocation.width_bytes);
-        requires_packed_storage |=
-            allocation_alignment < width || !relocation.source_offset.is_multiple_of(width);
-        if relocation.source_offset < cursor {
-            anyhow::bail!(
-                "device global relocation {index} overlaps the previous relocation or literal span"
-            );
-        }
-        let end = relocation
-            .source_offset
-            .checked_add(width)
-            .ok_or_else(|| anyhow::anyhow!("device global relocation {index} offset overflows"))?;
-        if end > byte_count {
-            anyhow::bail!(
-                "device global relocation {index} occupies bytes {}..{} but the initializer is only {} bytes",
-                relocation.source_offset,
-                end,
-                byte_count
-            );
-        }
-
-        if relocation.source_offset > cursor {
-            fields
-                .push(ArrayType::get(ctx, i8_ty.into(), relocation.source_offset - cursor).into());
-        }
-        fields.push(IntegerType::get(ctx, relocation.width_bytes * 8, Signedness::Signless).into());
-        cursor = end;
-    }
-
-    if cursor < byte_count {
-        fields.push(ArrayType::get(ctx, i8_ty.into(), byte_count - cursor).into());
-    }
-
-    let layout = if requires_packed_storage {
-        StructLayout::Packed
-    } else {
-        StructLayout::Unpacked
-    };
-    let storage: TypeHandle = StructType::get_unnamed(ctx, (fields, layout)).into();
-    // Exact or error, never guessed: the storage type is built from i8 arrays
-    // and integer slots, so its natural size is always computable, and it must
-    // land exactly on rustc's byte count or the relocation offsets are wrong.
-    let Some((lowered_size, _)) = llvm_type_size_align(ctx, storage) else {
-        anyhow::bail!(
-            "relocated device global storage `{}` has no exact size",
-            storage.deref(ctx).disp(ctx)
-        );
-    };
-    if lowered_size != byte_count {
-        anyhow::bail!(
-            "relocated device global storage lowers to {} bytes, but rustc evaluated {} bytes",
-            lowered_size,
-            byte_count
-        );
-    }
-    Ok(storage)
-}
-
-fn initializer_hex_byte_count(hex: &str) -> std::result::Result<u64, anyhow::Error> {
-    if !hex.len().is_multiple_of(2) {
-        anyhow::bail!("device global initializer has an odd-length hex byte string");
-    }
-    if let Some(invalid) = hex.bytes().find(|byte| !byte.is_ascii_hexdigit()) {
-        anyhow::bail!(
-            "device global initializer contains invalid hex digit {:?}",
-            invalid as char
-        );
-    }
-    u64::try_from(hex.len() / 2)
-        .map_err(|_| anyhow::anyhow!("device global initializer is too large for LLVM"))
-}
-
-/// Convert `mir.extern_shared` to LLVM extern global variable in shared address space.
-///
-/// Dynamic (extern) shared memory is represented as an external global variable
-/// with address space 3 and zero-length array type `[0 x i8]`. The actual size
-/// is determined at kernel launch via `LaunchConfig::shared_mem_bytes`.
-///
-/// # Per-Owner Symbols
-///
-/// Each function that owns an access gets a dynamic shared-memory symbol
-/// (`__dynamic_smem_{function_name}`).
-///
-/// # Alignment
-///
-/// The alignment is pre-computed during the lowering pre-pass. It is the
-/// maximum of the owner's body requirements and every launch-contract marker
-/// that can reach it.
-///
-/// # Byte Offset
-///
-/// - `DynamicSharedArray::get()` / `get_raw()`: offset = 0, returns base pointer
-/// - `DynamicSharedArray::offset(N)`: offset = N bytes, returns base + N
-///
-/// Called directly from `MirToLlvmConversionDriver::rewrite` (not through
-/// op_cast dispatch) because it needs cross-function state maps.
-pub fn convert_extern_shared_dc(
-    ctx: &mut Context,
-    rewriter: &mut DialectConversionRewriter,
-    op: Ptr<Operation>,
-    _operands_info: &OperandsInfo,
-    shared_globals: &mut SharedGlobalsMap,
-    dynamic_smem_alignments: &mut DynamicSmemAlignmentMap,
-) -> Result<()> {
-    let (byte_offset, alignment) = {
-        let extern_shared_op = dialect_mir::ops::MirExternSharedOp::new(op);
-        let byte_offset = extern_shared_op.get_byte_offset_value(ctx);
-        let alignment = extern_shared_op.get_alignment_value(ctx);
-        (byte_offset, alignment)
-    };
-
-    let func_name: String = {
-        let parent_block = op
-            .deref(ctx)
-            .get_parent_block()
-            .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Op has no parent block")))?;
-        let func_op_ptr = helpers::get_parent_func(ctx, parent_block).map_err(anyhow_to_pliron)?;
-        let llvm_func = Operation::get_op::<llvm::FuncOp>(func_op_ptr, ctx)
-            .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Parent op is not an llvm.func")))?;
-        llvm_func.get_symbol_name(ctx).to_string()
-    };
-
-    let global_name = get_or_create_extern_shared_global(
-        ctx,
-        op,
-        &func_name,
-        shared_globals,
-        dynamic_smem_alignments,
-        alignment,
-    )?;
-
-    let address_of_op = llvm::AddressOfOp::new(ctx, global_name, 3);
-    rewriter.insert_operation(ctx, address_of_op.get_operation());
-
-    let base_ptr = address_of_op.get_operation().deref(ctx).get_result(0);
-
-    if byte_offset > 0 {
-        let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-        let offset_attr = pliron::builtin::attributes::IntegerAttr::new(
-            i64_ty,
-            pliron::utils::apint::APInt::from_u64(
-                byte_offset,
-                std::num::NonZeroUsize::new(64).unwrap(),
-            ),
-        );
-        let offset_const = llvm::ConstantOp::new(ctx, offset_attr.into());
-        rewriter.insert_operation(ctx, offset_const.get_operation());
-        let offset_value = offset_const.get_operation().deref(ctx).get_result(0);
-
-        let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
-        let gep_op = llvm::GetElementPtrOp::new(
-            ctx,
-            base_ptr,
-            vec![llvm_export::ops::GepIndex::Value(offset_value)],
-            i8_ty.into(),
-        );
-        rewriter.insert_operation(ctx, gep_op.get_operation());
-        rewriter.replace_operation(ctx, op, gep_op.get_operation());
-    } else {
-        rewriter.replace_operation(ctx, op, address_of_op.get_operation());
-    }
-
-    Ok(())
-}
-
-/// Get or create the extern shared memory global for an owning function.
-///
-/// Creates an LLVM global variable with:
-/// - Zero-length array type: `[0 x i8]`
-/// - External linkage (no initializer)
-/// - Address space 3 (shared memory)
-/// - Pre-computed body and calling-kernel contract alignment
-///
-/// Each owning function gets its own dynamic shared memory symbol. Uses
-/// `shared_globals` for deduplication (only one global per function).
-fn get_or_create_extern_shared_global(
-    ctx: &mut Context,
-    op: Ptr<Operation>,
-    func_name: &str,
-    shared_globals: &mut SharedGlobalsMap,
-    dynamic_smem_alignments: &mut DynamicSmemAlignmentMap,
-    _requested_alignment: u64,
-) -> Result<pliron::identifier::Identifier> {
-    let (symbol_name, max_alignment) = dynamic_smem_alignments.get(func_name).cloned().ok_or_else(
-        || {
-            anyhow_to_pliron(anyhow::anyhow!(
-                "Internal error: dynamic shared memory alignment not pre-computed for function '{}'. \
-                 This should have been done in compute_max_dynamic_smem_alignment.",
-                func_name
-            ))
-        },
-    )?;
-
-    let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
-    let declaration = SharedGlobalDeclaration {
-        kind: SharedGlobalKind::DynamicExtern,
-        mir_elem_type: i8_ty.into(),
-        size: 0,
-        alignment: max_alignment,
-        // The dynamic pool is per-launch storage with no originating static;
-        // it never carries a source-level debug identity.
-        debug_info: None,
-        debug_owner_function: None,
-    };
-    let global_created_key = format!("__dynamic_smem_global_created_{}", func_name);
-    if let Some(existing) = shared_globals.get(&global_created_key) {
-        if existing.declaration != declaration || existing.symbol != symbol_name {
-            return Err(anyhow_to_pliron(anyhow::anyhow!(
-                "dynamic shared-memory key {:?} has an incompatible declaration",
-                global_created_key
-            )));
-        }
-        return Ok(existing.symbol.clone());
-    }
-
-    let array_type = ArrayType::get(ctx, i8_ty.into(), 0);
-
-    let global_op = llvm::GlobalOp::new_with_alignment(
-        ctx,
-        symbol_name.clone(),
-        array_type.into(),
-        max_alignment,
-    );
-    global_op.set_address_space(ctx, llvm_export::types::address_space::SHARED);
-
-    {
-        use llvm_export::attributes::LinkageAttr;
-        global_op.set_attr_llvm_global_linkage(ctx, LinkageAttr::ExternalLinkage);
-    }
-
-    let parent_block = op
-        .deref(ctx)
-        .get_parent_block()
-        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Op has no parent block")))?;
-    let module_op = helpers::get_module_from_block(ctx, parent_block).map_err(anyhow_to_pliron)?;
-    let region = module_op.deref(ctx).get_region(0);
-    let module_block = region
-        .deref(ctx)
-        .iter(ctx)
-        .next()
-        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Module is empty")))?;
-
-    global_op.get_operation().insert_at_front(module_block, ctx);
-
-    shared_globals.insert(
-        global_created_key,
-        SharedGlobalRecord {
-            symbol: symbol_name.clone(),
-            declaration,
-        },
-    );
-
-    Ok(symbol_name)
-}
-
-#[cfg(test)]
-// Tests build kinded fixture types directly; production minting lives in mir-importer's facts.rs.
-#[allow(clippy::disallowed_methods)]
-mod tests {
-    //! End-to-end lowering tests for `dialect-mir` memory ops.
-    //!
-    //! The `convert_*` functions in this file take a live
-    //! `DialectConversionRewriter`, which is owned by pliron's conversion
-    //! driver and not constructible standalone. So each test builds a small
-    //! MIR module, runs the full `lower_mir_to_llvm` pass on it, and asserts
-    //! the lowered module contains the expected `dialect-llvm` shape — same
-    //! pattern as `tests/lowering_test.rs`.
-
-    use super::*;
-    use crate::convert::ops::test_util::*;
-    use dialect_mir::attributes::MirPointerKindAuthorityAttr;
-    use dialect_mir::ops as mir;
-    use dialect_mir::types::{
-        MirArrayType, MirPointerKind, MirPtrType, MirStructType, MirTupleType, MirUnionType,
-    };
-    use llvm_export::op_interfaces::PointerTypeResult;
-    use llvm_export::ops as llvm;
-    use llvm_export::types::{PointerType, StructType, address_space as llvm_addr};
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::attributes::{StringAttr, TypeAttr};
-    use pliron::builtin::op_interfaces::SymbolOpInterface;
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::context::Context;
-    use pliron::linked_list::ContainsLinkedList;
-    use pliron::location::{Location, Source};
-    use pliron::op::Op;
-    use pliron::operation::Operation;
-    use std::path::PathBuf;
-
-    fn ptr_addrspace(ctx: &Context, ty: TypeHandle) -> u32 {
-        ty.deref(ctx)
-            .downcast_ref::<PointerType>()
-            .expect("expected llvm.PointerType")
-            .address_space()
-    }
-
-    fn src_location(ctx: &mut Context, file: &str, line: i32, column: i32) -> Location {
-        Location::SrcPos {
-            src: Source::new_from_file(ctx, PathBuf::from(file)),
-            pos: combine::stream::position::SourcePosition { line, column },
-        }
-    }
-
-    fn over_aligned_tuple_ty(ctx: &mut Context) -> TypeHandle {
-        let byte: TypeHandle = IntegerType::get(ctx, 8, Signedness::Unsigned).into();
-        let marker: TypeHandle = MirStructType::get_with_full_layout(
-            ctx,
-            "Align32".into(),
-            vec![],
-            vec![],
-            vec![],
-            vec![],
-            0,
-            32,
-        )
-        .into();
-        MirTupleType::get_with_layout(ctx, vec![marker, byte], vec![0, 1], vec![0, 0], 32, 32)
-            .into()
-    }
-
-    #[test]
-    fn convert_alloca_lowers_to_llvm_alloca() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-
-        let alloca_op = Operation::new(
-            &mut ctx,
-            mir::MirAllocaOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        alloca_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        assert_eq!(
-            count_ops::<llvm::AllocaOp>(&ctx, &body),
-            1,
-            "expected exactly one llvm.alloca"
-        );
-        let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).unwrap();
-        // Element type should round-trip through convert_type as i32.
-        let elem_ty = alloca.result_pointee_type(&ctx);
-        assert!(elem_ty.deref(&ctx).is::<IntegerType>());
-    }
-
-    #[test]
-    fn convert_alloca_preserves_nested_array_element_alignment() {
-        let mut ctx = make_ctx();
-        let tuple_ty = over_aligned_tuple_ty(&mut ctx);
-        let inner: TypeHandle = MirArrayType::get(&mut ctx, tuple_ty, 2).into();
-        let outer: TypeHandle = MirArrayType::get(&mut ctx, inner, 3).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, outer, true);
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-
-        let alloca_op = Operation::new(
-            &mut ctx,
-            mir::MirAllocaOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        alloca_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).expect("expected llvm.alloca");
-        assert_eq!(
-            llvm_export::ops::op_alignment(&ctx, alloca.get_operation()),
-            Some(32)
-        );
-    }
-
-    #[test]
-    fn convert_alloca_preserves_debug_local_metadata() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-
-        let alloca_op = Operation::new(
-            &mut ctx,
-            mir::MirAllocaOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        llvm::set_debug_local_variable(
-            &mut ctx,
-            alloca_op,
-            llvm::DebugLocalVariableInfo {
-                name: "x".to_string(),
-                argument_index: Some(1),
-                ty: llvm::DebugLocalTypeKind::Basic {
-                    name: "i32".to_string(),
-                    size_bits: 32,
-                    encoding: "DW_ATE_signed",
-                },
-            },
-        );
-        alloca_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).unwrap();
-        let info = llvm::debug_local_variable(&ctx, alloca.get_operation())
-            .expect("debug local metadata should survive lowering");
-
-        assert_eq!(info.name, "x");
-        assert_eq!(info.argument_index, Some(1));
-        assert_eq!(
-            info.ty,
-            llvm::DebugLocalTypeKind::Basic {
-                name: "i32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_signed",
-            }
-        );
-    }
-
-    #[test]
-    fn convert_store_lowers_to_llvm_store() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
-
-        // Kernel takes (ptr, val) so we can store one into the other.
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into(), i32_ty], vec![]);
-        let ptr_val = block.deref(&ctx).get_argument(0);
-        let val = block.deref(&ctx).get_argument(1);
-
-        let store_op = Operation::new(
-            &mut ctx,
-            mir::MirStoreOp::get_concrete_op_info(),
-            vec![],
-            vec![ptr_val, val],
-            vec![],
-            0,
-        );
-        store_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        assert_eq!(
-            count_ops::<llvm::StoreOp>(&ctx, &body),
-            1,
-            "expected one llvm.store"
-        );
-        // The original mir.store must be gone.
-        assert_eq!(count_ops::<mir::MirStoreOp>(&ctx, &body), 0);
-
-        // convert_store swaps operand order: mir.store is [ptr, value] but
-        // llvm.store takes (value, ptr). Verify that mapping survived.
-        let store = find_first::<llvm::StoreOp>(&ctx, &body).unwrap();
-        let addr_ty = store.get_operand_address(&ctx).get_type(&ctx);
-        assert!(addr_ty.deref(&ctx).is::<PointerType>(), "operand 1 is ptr");
-    }
-
-    #[test]
-    fn convert_store_preserves_volatile() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into(), i32_ty], vec![]);
-        let ptr_val = block.deref(&ctx).get_argument(0);
-        let val = block.deref(&ctx).get_argument(1);
-
-        let store_op = Operation::new(
-            &mut ctx,
-            mir::MirStoreOp::get_concrete_op_info(),
-            vec![],
-            vec![ptr_val, val],
-            vec![],
-            0,
-        );
-        mir::MirStoreOp::new(store_op).set_volatile(&mut ctx, true);
-        store_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let store = find_first::<llvm::StoreOp>(&ctx, &body).unwrap();
-        assert!(
-            llvm_export::ops::op_volatile(&ctx, store.get_operation()),
-            "volatile mir.store must lower to a volatile llvm.store"
-        );
-    }
-
-    #[test]
-    fn convert_load_lowers_to_llvm_load() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, false);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into()], vec![]);
-        let ptr_val = block.deref(&ctx).get_argument(0);
-
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![i32_ty],
-            vec![ptr_val],
-            vec![],
-            0,
-        );
-        load_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        assert_eq!(count_ops::<llvm::LoadOp>(&ctx, &body), 1);
-        assert_eq!(count_ops::<mir::MirLoadOp>(&ctx, &body), 0);
-    }
-
-    /// Lower `mir.load (mir.field_addr %p, field_index)` for a struct of
-    /// signless integer fields with the given layout and report the alignment
-    /// stamped on the resulting `llvm.load`. `None` means no stamp survived
-    /// and the exporter's natural-alignment default applies.
-    fn lowered_field_load_alignment(
-        field_bit_widths: Vec<u32>,
-        field_offsets: Vec<u64>,
-        total_size: u64,
-        abi_align: u64,
-        field_index: u32,
-    ) -> Option<u32> {
-        let mut ctx = make_ctx();
-        let field_types: Vec<TypeHandle> = field_bit_widths
-            .iter()
-            .map(|w| IntegerType::get(&ctx, *w, Signedness::Signless).into())
-            .collect();
-        let field_names = (0..field_types.len()).map(|i| format!("f{i}")).collect();
-        let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "FieldLoadAlign".into(),
-            field_names,
-            field_types.clone(),
-            vec![],
-            field_offsets,
-            total_size,
-            abi_align,
-        )
-        .into();
-        let struct_ptr_ty = MirPtrType::get_generic(&mut ctx, struct_ty, false);
-        let field_ty = field_types[field_index as usize];
-        let field_ptr_ty = MirPtrType::get_generic(&mut ctx, field_ty, false);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![struct_ptr_ty.into()], vec![]);
-        let struct_ptr_val = block.deref(&ctx).get_argument(0);
-
-        let field_addr_op =
-            mir::MirFieldAddrOp::build(&mut ctx, struct_ptr_val, field_ptr_ty.into(), field_index)
-                .expect("field_addr build");
-        field_addr_op.insert_at_back(block, &ctx);
-        let field_ptr_val = field_addr_op.deref(&ctx).get_result(0);
-
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![field_ty],
-            vec![field_ptr_val],
-            vec![],
-            0,
-        );
-        load_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected one llvm.load");
-        llvm_export::ops::op_alignment(&ctx, load.get_operation())
-    }
-
-    /// Field 0 of an over-aligned struct sits at the aggregate's own
-    /// alignment, which the field's scalar result type cannot state on its
-    /// own. This is what lets LoadStoreVectorizer fuse the adjacent pair.
-    #[test]
-    fn convert_load_inherits_overaligned_field_alignment_at_offset_zero() {
-        // #[repr(C, align(8))] struct { a: i32, b: i32 }
-        assert_eq!(
-            lowered_field_load_alignment(vec![32, 32], vec![0, 4], 8, 8, 0),
-            Some(8)
-        );
-    }
-
-    /// A field at a nonzero offset proves `gcd(abi_align, offset)`: an i32 at
-    /// offset 8 of an align-16 struct proves 8, beating its natural 4.
-    #[test]
-    fn convert_load_narrows_field_alignment_to_gcd_of_align_and_offset() {
-        // #[repr(C, align(16))] struct { a: i64, b: i32 }
-        assert_eq!(
-            lowered_field_load_alignment(vec![64, 32], vec![0, 8], 16, 16, 1),
-            Some(8)
-        );
-    }
-
-    /// Whole-value loads of pointer-free packed structs use the packed LLVM
-    /// representation, preserving rustc's byte size and field offsets.
-    #[test]
-    fn packed_struct_whole_value_load_uses_packed_layout() {
-        let mut ctx = make_ctx();
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Packed".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![0, 1],
-            vec![0, 1],
-            5,
-            1,
-        )
-        .into();
-        let ptr_ty = MirPtrType::get_generic(&mut ctx, packed_ty, false);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty.into()], vec![]);
-        let ptr_val = block.deref(&ctx).get_argument(0);
-
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![packed_ty],
-            vec![ptr_val],
-            vec![],
-            0,
-        );
-        load_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect("whole-value load of a pointer-free packed struct must lower");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected packed llvm.load");
-        let result_ty = load
-            .get_operation()
-            .deref(&ctx)
-            .get_result(0)
-            .get_type(&ctx);
-        let result_ty_ref = result_ty.deref(&ctx);
-        let struct_ty = result_ty_ref
-            .downcast_ref::<StructType>()
-            .expect("packed load result must be an LLVM struct");
-        assert_eq!(struct_ty.layout(), StructLayout::Packed);
-        assert_eq!(
-            crate::convert::types::llvm_type_size_align(&ctx, result_ty),
-            Some((5, 1))
-        );
-        assert_eq!(
-            llvm_export::ops::op_alignment(&ctx, load.get_operation()),
-            Some(1)
-        );
-    }
-
-    #[test]
-    fn packed_struct_whole_value_load_with_shared_pointer_fails_closed() {
-        let mut ctx = make_ctx();
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let shared_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedShared".into(),
-            vec!["tag".into(), "ptr".into()],
-            vec![u8_ty, shared_ty],
-            vec![0, 1],
-            vec![0, 1],
-            9,
-            1,
-        )
-        .into();
-        let ptr_ty = MirPtrType::get_generic(&mut ctx, packed_ty, false);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty.into()], vec![]);
-        let ptr_val = block.deref(&ctx).get_argument(0);
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![packed_ty],
-            vec![ptr_val],
-            vec![],
-            0,
-        );
-        load_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        let err = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect_err("packed whole-value load containing AS3 must remain fail-closed");
-        assert!(
-            format!("{err:?}").contains("target-mode dependent"),
-            "the refusal must identify the target-dependent packed AS3 image: {err:?}"
-        );
-    }
-
-    /// Whole-value stores use the same packed representation as construction
-    /// and loads, while preserving the MIR aggregate's proved ABI alignment.
-    #[test]
-    fn packed_struct_whole_value_store_uses_packed_layout() {
-        let mut ctx = make_ctx();
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Packed".into(),
-            vec!["tag".into(), "value".into()],
-            vec![u8_ty, u32_ty],
-            vec![0, 1],
-            vec![0, 1],
-            5,
-            1,
-        )
-        .into();
-        let ptr_ty = MirPtrType::get_generic(&mut ctx, packed_ty, false);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty.into(), packed_ty], vec![]);
-        let ptr_val = block.deref(&ctx).get_argument(0);
-        let val = block.deref(&ctx).get_argument(1);
-
-        let store_op = Operation::new(
-            &mut ctx,
-            mir::MirStoreOp::get_concrete_op_info(),
-            vec![],
-            vec![ptr_val, val],
-            vec![],
-            0,
-        );
-        store_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect("whole-value store of a pointer-free packed struct must lower");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let store = find_first::<llvm::StoreOp>(&ctx, &body).expect("expected packed llvm.store");
-        let value_ty = store
-            .get_operation()
-            .deref(&ctx)
-            .get_operand(0)
-            .get_type(&ctx);
-        let value_ty_ref = value_ty.deref(&ctx);
-        let struct_ty = value_ty_ref
-            .downcast_ref::<StructType>()
-            .expect("packed store value must be an LLVM struct");
-        assert_eq!(struct_ty.layout(), StructLayout::Packed);
-        assert_eq!(
-            crate::convert::types::llvm_type_size_align(&ctx, value_ty),
-            Some((5, 1))
-        );
-        assert_eq!(
-            llvm_export::ops::op_alignment(&ctx, store.get_operation()),
-            Some(1)
-        );
-    }
-
-    /// A naturally aligned inner struct sitting at a packed byte offset: the
-    /// field address only proves align 1, and the load must claim that over
-    /// the inner type's recorded abi alignment. Claiming the abi would stamp
-    /// `align 4` on a 1-aligned address, which llc may honor with a wider
-    /// access than the bytes allow.
-    #[test]
-    fn convert_load_claims_address_alignment_over_abi_at_packed_offsets() {
-        let mut ctx = make_ctx();
-        let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-        let inner_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Inner".into(),
-            vec!["v".into()],
-            vec![u32_ty],
-            vec![0],
-            vec![0],
-            4,
-            4,
-        )
-        .into();
-        let outer_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedOuter".into(),
-            vec!["tag".into(), "inner".into()],
-            vec![u8_ty, inner_ty],
-            vec![0, 1],
-            vec![0, 1],
-            5,
-            1,
-        )
-        .into();
-        let outer_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, outer_ty, false).into();
-        let inner_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, inner_ty, false).into();
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![outer_ptr_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-
-        let field_addr_op =
-            mir::MirFieldAddrOp::build(&mut ctx, base, inner_ptr_ty, 1).expect("field_addr build");
-        field_addr_op.insert_at_back(block, &ctx);
-        let field_ptr_val = field_addr_op.deref(&ctx).get_result(0);
-
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![inner_ty],
-            vec![field_ptr_val],
-            vec![],
-            0,
-        );
-        load_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected one llvm.load");
-        assert_eq!(
-            llvm_export::ops::op_alignment(&ctx, load.get_operation()),
-            Some(1),
-            "the load must claim the address's proved alignment, not the inner abi"
-        );
-    }
-
-    /// A struct with no extra alignment proves nothing beyond the scalar's
-    /// natural alignment: the stamp equals the exporter's default 4, so the
-    /// emitted access is unchanged.
-    #[test]
-    fn convert_load_keeps_natural_alignment_without_overalignment() {
-        // struct { a: i32, b: i32 } with rustc's natural abi_align 4
-        assert_eq!(
-            lowered_field_load_alignment(vec![32, 32], vec![0, 4], 8, 4, 1),
-            Some(4)
-        );
-    }
-
-    /// dialect-mir only verifier-enforces power-of-two alignment for unions
-    /// and enums. A malformed hand-built struct layout must decline the stamp
-    /// rather than emit a non-power-of-two `align N` that llc rejects.
-    #[test]
-    fn convert_load_declines_non_power_of_two_field_alignment() {
-        assert_eq!(
-            lowered_field_load_alignment(vec![32], vec![0], 12, 12, 0),
-            None
-        );
-    }
-
-    /// Lower `mir.store %v, (mir.field_addr %p, field_index)` for a struct of
-    /// signless integer fields with the given layout and report the alignment
-    /// stamped on the resulting `llvm.store`. `None` means no stamp survived
-    /// and the exporter's natural-alignment default applies.
-    fn lowered_field_store_alignment(
-        field_bit_widths: Vec<u32>,
-        field_offsets: Vec<u64>,
-        total_size: u64,
-        abi_align: u64,
-        field_index: u32,
-    ) -> Option<u32> {
-        let mut ctx = make_ctx();
-        let field_types: Vec<TypeHandle> = field_bit_widths
-            .iter()
-            .map(|w| IntegerType::get(&ctx, *w, Signedness::Signless).into())
-            .collect();
-        let field_names = (0..field_types.len()).map(|i| format!("f{i}")).collect();
-        let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "FieldStoreAlign".into(),
-            field_names,
-            field_types.clone(),
-            vec![],
-            field_offsets,
-            total_size,
-            abi_align,
-        )
-        .into();
-        let struct_ptr_ty = MirPtrType::get_generic(&mut ctx, struct_ty, true);
-        let field_ty = field_types[field_index as usize];
-        let field_ptr_ty = MirPtrType::get_generic(&mut ctx, field_ty, true);
-
-        // The stored value arrives as a kernel argument of the field's own
-        // scalar type, so `value_abi_align` reports nothing about it and the
-        // address's stamp is the only alignment left -- the case this covers.
-        let (module_ptr, block) =
-            build_kernel(&mut ctx, vec![struct_ptr_ty.into(), field_ty], vec![]);
-        let struct_ptr_val = block.deref(&ctx).get_argument(0);
-        let val = block.deref(&ctx).get_argument(1);
-
-        let field_addr_op =
-            mir::MirFieldAddrOp::build(&mut ctx, struct_ptr_val, field_ptr_ty.into(), field_index)
-                .expect("field_addr build");
-        field_addr_op.insert_at_back(block, &ctx);
-        let field_ptr_val = field_addr_op.deref(&ctx).get_result(0);
-
-        let store_op = Operation::new(
-            &mut ctx,
-            mir::MirStoreOp::get_concrete_op_info(),
-            vec![],
-            vec![field_ptr_val, val],
-            vec![],
-            0,
-        );
-        store_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let store = find_first::<llvm::StoreOp>(&ctx, &body).expect("expected one llvm.store");
-        llvm_export::ops::op_alignment(&ctx, store.get_operation())
-    }
-
-    /// Field 0 of an over-aligned struct sits at the aggregate's own alignment,
-    /// which the stored scalar's type cannot state. This is what lets
-    /// LoadStoreVectorizer fuse the adjacent pair into one wide store.
-    #[test]
-    fn convert_store_inherits_overaligned_field_alignment_at_offset_zero() {
-        // #[repr(C, align(8))] struct { a: i32, b: i32 }
-        assert_eq!(
-            lowered_field_store_alignment(vec![32, 32], vec![0, 4], 8, 8, 0),
-            Some(8)
-        );
-    }
-
-    /// A field at a nonzero offset proves `gcd(abi_align, offset)`: an i32 at
-    /// offset 8 of an align-16 struct proves 8, beating its natural 4.
-    #[test]
-    fn convert_store_narrows_field_alignment_to_gcd_of_align_and_offset() {
-        // #[repr(C, align(16))] struct { a: i64, b: i32 }
-        assert_eq!(
-            lowered_field_store_alignment(vec![64, 32], vec![0, 8], 16, 16, 1),
-            Some(8)
-        );
-    }
-
-    /// A struct with no extra alignment proves nothing beyond the scalar's
-    /// natural alignment, so the emitted store is unchanged. Widening here
-    /// would claim an alignment the source never guaranteed.
-    #[test]
-    fn convert_store_keeps_natural_alignment_without_overalignment() {
-        // struct { a: i32, b: i32 } with rustc's natural abi_align 4
-        assert_eq!(
-            lowered_field_store_alignment(vec![32, 32], vec![0, 4], 8, 4, 1),
-            Some(4)
-        );
-    }
-
-    /// A malformed hand-built layout must decline the stamp rather than emit a
-    /// non-power-of-two `align N` that llc rejects. Same guard the load path
-    /// has, and it matters more here: an over-aligned store instruction on an
-    /// under-aligned address is undefined, not merely slow.
-    #[test]
-    fn convert_store_declines_non_power_of_two_field_alignment() {
-        assert_eq!(
-            lowered_field_store_alignment(vec![32], vec![0], 12, 12, 0),
-            None
-        );
-    }
-
-    /// Lower `load (&arr[index])` where `arr` is the array field of an
-    /// over-aligned struct, and report the alignment the load ends up with.
-    ///
-    /// `index` of `Some(i)` builds a constant index, `None` a runtime one.
-    fn lowered_element_load_alignment(
-        element_bits: u32,
-        element_count: u64,
-        struct_abi_align: u64,
-        index: Option<u64>,
-    ) -> Option<u32> {
-        use pliron::builtin::attributes::IntegerAttr;
-        use std::num::NonZeroUsize;
-
-        let mut ctx = make_ctx();
-        let element_ty: TypeHandle =
-            IntegerType::get(&ctx, element_bits, Signedness::Signless).into();
-        let array_ty: TypeHandle =
-            dialect_mir::types::MirArrayType::get(&mut ctx, element_ty, element_count).into();
-        let elem_bytes = u64::from(element_bits) / 8;
-        let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "ElementLoadAlign".into(),
-            vec!["lanes".into()],
-            vec![array_ty],
-            vec![],
-            vec![0],
-            elem_bytes * element_count,
-            struct_abi_align,
-        )
-        .into();
-        let struct_ptr_ty = MirPtrType::get_generic(&mut ctx, struct_ty, false);
-        let array_ptr_ty = MirPtrType::get_generic(&mut ctx, array_ty, false);
-        let element_ptr_ty = MirPtrType::get_generic(&mut ctx, element_ty, false);
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
-
-        let (module_ptr, block) =
-            build_kernel(&mut ctx, vec![struct_ptr_ty.into(), i64_ty], vec![]);
-        let struct_ptr_val = block.deref(&ctx).get_argument(0);
-
-        // &s.lanes -- carries the struct's alignment onto the array address.
-        let field_addr_op =
-            mir::MirFieldAddrOp::build(&mut ctx, struct_ptr_val, array_ptr_ty.into(), 0)
-                .expect("field_addr build");
-        field_addr_op.insert_at_back(block, &ctx);
-        let array_ptr_val = field_addr_op.deref(&ctx).get_result(0);
-
-        let index_val = match index {
-            Some(i) => {
-                let constant = Operation::new(
-                    &mut ctx,
-                    mir::MirConstantOp::get_concrete_op_info(),
-                    vec![i64_ty],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                mir::MirConstantOp::new(constant).set_attr_value(
-                    &ctx,
-                    IntegerAttr::new(
-                        IntegerType::get(&ctx, 64, Signedness::Signed),
-                        APInt::from_u64(i, NonZeroUsize::new(64).unwrap()),
-                    ),
-                );
-                constant.insert_at_back(block, &ctx);
-                constant.deref(&ctx).get_result(0)
-            }
-            None => block.deref(&ctx).get_argument(1),
-        };
-
-        let elem_addr_op = Operation::new(
-            &mut ctx,
-            mir::MirArrayElementAddrOp::get_concrete_op_info(),
-            vec![element_ptr_ty.into()],
-            vec![array_ptr_val, index_val],
-            vec![],
-            0,
-        );
-        elem_addr_op.insert_at_back(block, &ctx);
-        let elem_ptr_val = elem_addr_op.deref(&ctx).get_result(0);
-
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![element_ty],
-            vec![elem_ptr_val],
-            vec![],
-            0,
-        );
-        load_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected one llvm.load");
-        llvm_export::ops::op_alignment(&ctx, load.get_operation())
-    }
-
-    /// Element 0 inherits the whole alignment the base address proved, which is
-    /// what lets the adjacent pair fuse into one wide load.
-    #[test]
-    fn convert_load_inherits_base_alignment_at_element_zero() {
-        // &(#[repr(C, align(8))] struct { lanes: [i32; 2] }).lanes[0]
-        assert_eq!(lowered_element_load_alignment(32, 2, 8, Some(0)), Some(8));
-    }
-
-    /// A nonzero constant index proves `gcd(base, i * stride)`: element 1 of an
-    /// align-8 `[i32; 2]` sits at byte 4, so it proves 4, not 8.
-    #[test]
-    fn convert_load_narrows_element_alignment_to_gcd_with_offset() {
-        assert_eq!(lowered_element_load_alignment(32, 2, 8, Some(1)), Some(4));
-    }
-
-    /// A runtime index can land on any element, so only what every stride
-    /// preserves may be claimed -- `gcd(base, stride)`, never the base itself.
-    #[test]
-    fn convert_load_claims_only_stride_alignment_for_a_runtime_index() {
-        assert_eq!(lowered_element_load_alignment(32, 2, 8, None), Some(4));
-    }
-
-    /// A base with no extra alignment proves nothing beyond the element's own
-    /// natural alignment, so the emitted access is unchanged.
-    #[test]
-    fn convert_load_keeps_natural_element_alignment_without_overalignment() {
-        assert_eq!(lowered_element_load_alignment(32, 2, 4, Some(0)), Some(4));
-    }
-
-    /// Like [`lowered_element_load_alignment`], but for an array whose element
-    /// is an aggregate built by `element_ty_of` (which also reports the
-    /// element's stored size in bytes). The claim on the element address must
-    /// then come from the element's *exact* stride — rustc's stored size,
-    /// padding included — not from any LLVM-level approximation.
-    ///
-    /// With `load_first_scalar` the element must itself be an array and the
-    /// access becomes `s.lanes[index][0]`, mirroring the nested-read chain
-    /// where the outer stamp is inherited by the inner index-0 address and
-    /// ends up on a scalar load that LoadStoreVectorizer trusts. Without it,
-    /// the element itself is loaded.
-    ///
-    /// Reports `(element address stamp, final load alignment)`.
-    fn lowered_aggregate_element_alignments(
-        element_ty_of: impl FnOnce(&mut Context) -> (TypeHandle, u64),
-        element_count: u64,
-        struct_abi_align: u64,
-        index: Option<u64>,
-        load_first_scalar: bool,
-    ) -> (Option<u32>, Option<u32>) {
-        use pliron::builtin::attributes::IntegerAttr;
-        use std::num::NonZeroUsize;
-
-        let mut ctx = make_ctx();
-        let (element_ty, elem_bytes) = element_ty_of(&mut ctx);
-        let inner_scalar_ty = load_first_scalar.then(|| {
-            let element_ref = element_ty.deref(&ctx);
-            element_ref
-                .downcast_ref::<MirArrayType>()
-                .expect("load_first_scalar needs an array element")
-                .element_type()
-        });
-        let array_ty: TypeHandle = MirArrayType::get(&mut ctx, element_ty, element_count).into();
-        let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "AggregateElementAlign".into(),
-            vec!["lanes".into()],
-            vec![array_ty],
-            vec![],
-            vec![0],
-            elem_bytes * element_count,
-            struct_abi_align,
-        )
-        .into();
-        let struct_ptr_ty = MirPtrType::get_generic(&mut ctx, struct_ty, false);
-        let array_ptr_ty = MirPtrType::get_generic(&mut ctx, array_ty, false);
-        let element_ptr_ty = MirPtrType::get_generic(&mut ctx, element_ty, false);
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
-
-        let (module_ptr, block) =
-            build_kernel(&mut ctx, vec![struct_ptr_ty.into(), i64_ty], vec![]);
-        let struct_ptr_val = block.deref(&ctx).get_argument(0);
-
-        // &s.lanes -- carries the struct's alignment onto the array address.
-        let field_addr_op =
-            mir::MirFieldAddrOp::build(&mut ctx, struct_ptr_val, array_ptr_ty.into(), 0)
-                .expect("field_addr build");
-        field_addr_op.insert_at_back(block, &ctx);
-        let array_ptr_val = field_addr_op.deref(&ctx).get_result(0);
-
-        let constant_index = |ctx: &mut Context, i: u64| {
-            let constant = Operation::new(
-                ctx,
-                mir::MirConstantOp::get_concrete_op_info(),
-                vec![i64_ty],
-                vec![],
-                vec![],
-                0,
-            );
-            mir::MirConstantOp::new(constant).set_attr_value(
-                ctx,
-                IntegerAttr::new(
-                    IntegerType::get(ctx, 64, Signedness::Signed),
-                    APInt::from_u64(i, NonZeroUsize::new(64).unwrap()),
-                ),
-            );
-            constant.insert_at_back(block, ctx);
-            constant.deref(ctx).get_result(0)
-        };
-
-        let index_val = match index {
-            Some(i) => constant_index(&mut ctx, i),
-            None => block.deref(&ctx).get_argument(1),
-        };
-
-        let elem_addr_op = Operation::new(
-            &mut ctx,
-            mir::MirArrayElementAddrOp::get_concrete_op_info(),
-            vec![element_ptr_ty.into()],
-            vec![array_ptr_val, index_val],
-            vec![],
-            0,
-        );
-        elem_addr_op.insert_at_back(block, &ctx);
-        let elem_ptr_val = elem_addr_op.deref(&ctx).get_result(0);
-
-        let (loaded_ty, loaded_ptr_val) = match inner_scalar_ty {
-            Some(scalar_ty) => {
-                let zero_val = constant_index(&mut ctx, 0);
-                let scalar_ptr_ty = MirPtrType::get_generic(&mut ctx, scalar_ty, false);
-                let inner_addr_op = Operation::new(
-                    &mut ctx,
-                    mir::MirArrayElementAddrOp::get_concrete_op_info(),
-                    vec![scalar_ptr_ty.into()],
-                    vec![elem_ptr_val, zero_val],
-                    vec![],
-                    0,
-                );
-                inner_addr_op.insert_at_back(block, &ctx);
-                (scalar_ty, inner_addr_op.deref(&ctx).get_result(0))
-            }
-            None => (element_ty, elem_ptr_val),
-        };
-
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![loaded_ty],
-            vec![loaded_ptr_val],
-            vec![],
-            0,
-        );
-        load_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        // GEP order follows source order: field address, then the element
-        // address under test (then the inner index-0 address when nested).
-        let geps = find_all::<llvm::GetElementPtrOp>(&ctx, &body);
-        assert_eq!(geps.len(), if load_first_scalar { 3 } else { 2 });
-        let element_gep_align = llvm_export::ops::address_alignment(&ctx, geps[1].get_operation());
-        let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected one llvm.load");
-        let load_align = llvm_export::ops::op_alignment(&ctx, load.get_operation());
-        (element_gep_align, load_align)
-    }
-
-    /// `[f32; 3]` element under an align-8 base: stride is 12, so a runtime
-    /// index proves `gcd(8, 12) = 4` — and the inner index-0 scalar read
-    /// inherits exactly that. Guards against sizing the element through an
-    /// LLVM-level approximation, whose guessed stride of 8 would stamp
-    /// align 8 onto addresses that are only 4-aligned (a miscompile once
-    /// LoadStoreVectorizer trusts it).
-    #[test]
-    fn convert_load_claims_exact_aggregate_stride_for_nested_array_elements() {
-        use pliron::builtin::types::FP32Type;
-        // &(#[repr(C, align(8))] struct { lanes: [[f32; 3]; 4] }).lanes[i][0]
-        let nested_f32x3 = |ctx: &mut Context| {
-            let f32_ty: TypeHandle = FP32Type::get(ctx).into();
-            (MirArrayType::get(ctx, f32_ty, 3).into(), 12)
-        };
-        assert_eq!(
-            lowered_aggregate_element_alignments(nested_f32x3, 4, 8, None, true),
-            (Some(4), Some(4))
-        );
-    }
-
-    /// A constant index into the same nested array uses the exact byte
-    /// offset: element 1 sits at byte 12 (`gcd(8, 12) = 4`), element 2 at
-    /// byte 24 (`gcd(8, 24) = 8`, the full base alignment again).
-    #[test]
-    fn convert_load_narrows_nested_element_alignment_by_exact_byte_offset() {
-        use pliron::builtin::types::FP32Type;
-        let nested_f32x3 = |ctx: &mut Context| {
-            let f32_ty: TypeHandle = FP32Type::get(ctx).into();
-            (MirArrayType::get(ctx, f32_ty, 3).into(), 12)
-        };
-        assert_eq!(
-            lowered_aggregate_element_alignments(nested_f32x3, 4, 8, Some(1), true),
-            (Some(4), Some(4))
-        );
-        assert_eq!(
-            lowered_aggregate_element_alignments(nested_f32x3, 4, 8, Some(2), true),
-            (Some(8), Some(8))
-        );
-    }
-
-    /// A tuple element's stride comes from rustc's recorded `total_size`
-    /// (trailing padding included): `(f32, f32, f32)` stores 12 bytes, so an
-    /// align-8 base proves only 4 on a runtime element address.
-    #[test]
-    fn convert_array_element_addr_takes_tuple_stride_from_recorded_layout() {
-        use pliron::builtin::types::FP32Type;
-        let f32x3_tuple = |ctx: &mut Context| {
-            let f32_ty: TypeHandle = FP32Type::get(ctx).into();
-            let tuple_ty: TypeHandle =
-                MirTupleType::get_with_layout(ctx, vec![f32_ty; 3], vec![], vec![0, 4, 8], 12, 4)
-                    .into();
-            (tuple_ty, 12)
-        };
-        let (element_gep_align, _load_align) =
-            lowered_aggregate_element_alignments(f32x3_tuple, 4, 8, None, false);
-        assert_eq!(element_gep_align, Some(4));
-    }
-
-    /// `f16` arrives from the importer as `MirFP16Type`, not the converted
-    /// LLVM `half`, and its stride is exactly 2: an align-8 base proves 2 on
-    /// a runtime element address and `gcd(8, 4) = 4` at element 2. Guards
-    /// the arm the importer actually exercises — the old sizing guessed 8
-    /// for this type too, the same over-claim as the aggregate cases.
-    #[test]
-    fn convert_load_claims_exact_f16_element_stride() {
-        let f16_scalar = |ctx: &mut Context| {
-            let f16_ty: TypeHandle = dialect_mir::types::MirFP16Type::get(ctx).into();
-            (f16_ty, 2)
-        };
-        assert_eq!(
-            lowered_aggregate_element_alignments(f16_scalar, 4, 8, None, false),
-            (Some(2), Some(2))
-        );
-        assert_eq!(
-            lowered_aggregate_element_alignments(f16_scalar, 4, 8, Some(2), false),
-            (Some(4), Some(4))
-        );
-    }
-
-    /// An element whose stored size is unknown (a struct built without rustc
-    /// layout) must not have its stride guessed: the element address claims
-    /// nothing and the load keeps the previous, weaker-but-sound behaviour.
-    #[test]
-    fn convert_array_element_addr_declines_unknown_element_stride() {
-        use pliron::builtin::types::FP32Type;
-        let opaque_struct = |ctx: &mut Context| {
-            let f32_ty: TypeHandle = FP32Type::get(ctx).into();
-            let struct_ty: TypeHandle =
-                MirStructType::get(ctx, "OpaqueElement".into(), vec!["x".into()], vec![f32_ty])
-                    .into();
-            (struct_ty, 4)
-        };
-        assert_eq!(
-            lowered_aggregate_element_alignments(opaque_struct, 4, 8, None, false),
-            (None, None)
-        );
-    }
-
-    #[test]
-    fn convert_dbg_value_lowers_to_llvm_dbg_value() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![i32_ty], vec![]);
-        let value = block.deref(&ctx).get_argument(0);
-
-        let dbg_op = mir::MirDbgValueOp::new(&mut ctx, value);
-        let dbg_loc = pliron::location::Location::Named {
-            name: "current value location".to_string(),
-            child_loc: Box::new(pliron::location::Location::Unknown),
-        };
-        dbg_op
-            .get_operation()
-            .deref_mut(&ctx)
-            .set_loc(dbg_loc.clone());
-        llvm::set_debug_local_variable(
-            &mut ctx,
-            dbg_op.get_operation(),
-            llvm::DebugLocalVariableInfo {
-                name: "x".to_string(),
-                argument_index: None,
-                ty: llvm::DebugLocalTypeKind::Basic {
-                    name: "i32".to_string(),
-                    size_bits: 32,
-                    encoding: "DW_ATE_signed",
-                },
-            },
-        );
-        llvm::set_debug_local_source_scope(&mut ctx, dbg_op.get_operation(), 42);
-        llvm::set_debug_fragment_variables(
-            &mut ctx,
-            dbg_op.get_operation(),
-            &[llvm::DebugFragmentVariableInfo {
-                variable: llvm::DebugLocalVariableInfo {
-                    name: "pair".to_string(),
-                    argument_index: None,
-                    ty: llvm::DebugLocalTypeKind::Array {
-                        name: "[u32; 2]".to_string(),
-                        size_bits: 64,
-                        element: Box::new(llvm::DebugLocalTypeKind::Basic {
-                            name: "u32".to_string(),
-                            size_bits: 32,
-                            encoding: "DW_ATE_unsigned",
-                        }),
-                        count: 2,
-                    },
-                },
-                fragment: llvm::DebugFragment {
-                    offset_bits: 32,
-                    size_bits: 32,
-                },
-                source_scope: Some(42),
-                declaration: Some(llvm::DebugSourcePosition {
-                    file: PathBuf::from("decl.rs"),
-                    line: 7,
-                    column: 3,
-                }),
-            }],
-        );
-        llvm::set_debug_local_declaration_location(
-            &mut ctx,
-            dbg_op.get_operation(),
-            PathBuf::from("decl.rs"),
-            7,
-            3,
-        );
-        dbg_op.get_operation().insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        assert_eq!(count_ops::<mir::MirDbgValueOp>(&ctx, &body), 0);
-        let dbg_value = find_first::<llvm::DebugValueOp>(&ctx, &body)
-            .expect("expected lowered llvm.dbg_value marker");
-        assert_eq!(
-            dbg_value.get_operation().deref(&ctx).loc(),
-            dbg_loc,
-            "dbg.value lowering should keep the current-value source location"
-        );
-        let info = llvm::debug_local_variable(&ctx, dbg_value.get_operation())
-            .expect("debug local metadata should survive dbg_value lowering");
-
-        assert_eq!(info.name, "x");
-        assert_eq!(
-            llvm::debug_local_source_scope(&ctx, dbg_value.get_operation()),
-            Some(42),
-            "dbg.value lowering should keep the MIR source-scope owner"
-        );
-        let (decl_file, decl_pos) =
-            llvm::debug_local_declaration_location(&ctx, dbg_value.get_operation())
-                .expect("declaration location should survive dbg_value lowering");
-        assert_eq!(decl_file, PathBuf::from("decl.rs"));
-        assert_eq!(decl_pos.line, 7);
-        assert_eq!(decl_pos.column, 3);
-        assert_eq!(
-            info.ty,
-            llvm::DebugLocalTypeKind::Basic {
-                name: "i32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_signed",
-            }
-        );
-        let fragments = llvm::debug_fragment_variables(&ctx, dbg_value.get_operation());
-        assert_eq!(fragments.len(), 1);
-        assert_eq!(fragments[0].fragment.offset_bits, 32);
-        assert_eq!(fragments[0].fragment.size_bits, 32);
-        assert_eq!(fragments[0].variable.name, "pair");
-    }
-
-    #[test]
-    fn convert_dbg_value_list_preserves_operands_and_expression() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, false);
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty.into(), i64_ty], vec![]);
-        let base = block.deref(&ctx).get_argument(0);
-        let index = block.deref(&ctx).get_argument(1);
-
-        let dbg_op = mir::MirDbgValueListOp::new(&mut ctx, vec![base, index]);
-        llvm::set_debug_local_variable(
-            &mut ctx,
-            dbg_op.get_operation(),
-            llvm::DebugLocalVariableInfo {
-                name: "item".to_string(),
-                argument_index: None,
-                ty: llvm::DebugLocalTypeKind::Basic {
-                    name: "u32".to_string(),
-                    size_bits: 32,
-                    encoding: "DW_ATE_unsigned",
-                },
-            },
-        );
-        let expression = llvm::DebugValueExpression::new(vec![
-            llvm::DebugValueExpressionOp::Arg(0),
-            llvm::DebugValueExpressionOp::Arg(1),
-            llvm::DebugValueExpressionOp::ConstU(4),
-            llvm::DebugValueExpressionOp::Mul,
-            llvm::DebugValueExpressionOp::Plus,
-            llvm::DebugValueExpressionOp::Deref,
-        ]);
-        llvm::set_debug_value_expression(&mut ctx, dbg_op.get_operation(), &expression);
-        dbg_op.get_operation().insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        assert_eq!(count_ops::<mir::MirDbgValueListOp>(&ctx, &body), 0);
-        let dbg_value = find_first::<llvm::DebugValueListOp>(&ctx, &body)
-            .expect("expected lowered llvm.dbg_value_list marker");
-        assert_eq!(dbg_value.values(&ctx), vec![base, index]);
-        assert_eq!(
-            llvm::debug_value_expression(&ctx, dbg_value.get_operation()),
-            Some(expression)
-        );
-    }
-
-    #[test]
-    fn convert_alloca_preserves_local_memory_provenance() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-
-        let alloca_op = Operation::new(
-            &mut ctx,
-            mir::MirAllocaOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        let provenance = llvm_export::ops::LocalMemoryProvenanceAttr {
-            local_index: 3,
-            size_bytes: 16,
-            binding_name: "scratch".into(),
-            type_name: "[u32; 4]".into(),
-        };
-        llvm_export::ops::set_local_memory_provenance(&mut ctx, alloca_op, provenance.clone());
-        alloca_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).unwrap();
-        let copied =
-            llvm_export::ops::local_memory_provenance(&ctx, alloca.get_operation()).unwrap();
-        assert_eq!(copied, provenance);
-    }
-
-    #[test]
-    fn mem2reg_salvages_tagged_alloca_into_mir_dbg_value() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![i32_ty], vec![i32_ty]);
-        let arg = block.deref(&ctx).get_argument(0);
-
-        let alloca_op = Operation::new(
-            &mut ctx,
-            mir::MirAllocaOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        let decl_loc = src_location(&mut ctx, "kernel.rs", 12, 9);
-        alloca_op.deref_mut(&ctx).set_loc(decl_loc.clone());
-        llvm::set_debug_local_variable(
-            &mut ctx,
-            alloca_op,
-            llvm::DebugLocalVariableInfo {
-                name: "x".to_string(),
-                argument_index: Some(1),
-                ty: llvm::DebugLocalTypeKind::Basic {
-                    name: "i32".to_string(),
-                    size_bits: 32,
-                    encoding: "DW_ATE_signed",
-                },
-            },
-        );
-        llvm::set_debug_local_source_scope(&mut ctx, alloca_op, 9);
-        alloca_op.insert_at_back(block, &ctx);
-        let slot = alloca_op.deref(&ctx).get_result(0);
-
-        let store_op = Operation::new(
-            &mut ctx,
-            mir::MirStoreOp::get_concrete_op_info(),
-            vec![],
-            vec![slot, arg],
-            vec![],
-            0,
-        );
-        store_op.insert_at_back(block, &ctx);
-
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![i32_ty],
-            vec![slot],
-            vec![],
-            0,
-        );
-        load_op.insert_at_back(block, &ctx);
-        let loaded = load_op.deref(&ctx).get_result(0);
-        append_mir_return(&mut ctx, block, vec![loaded]);
-
-        let mut analyses = pliron::pass::AnalysisManager::default();
-        pliron::opts::mem2reg::mem2reg(module_ptr, &mut ctx, &mut analyses)
-            .expect("mem2reg should promote the local slot");
-
-        let blocks = vec![block];
-        assert_eq!(count_ops::<mir::MirAllocaOp>(&ctx, &blocks), 0);
-        assert_eq!(count_ops::<mir::MirStoreOp>(&ctx, &blocks), 0);
-        assert_eq!(count_ops::<mir::MirLoadOp>(&ctx, &blocks), 0);
-
-        let dbg_values = find_all::<mir::MirDbgValueOp>(&ctx, &blocks);
-        assert!(
-            !dbg_values.is_empty(),
-            "mem2reg should leave value-based debug records for promoted locals"
-        );
-        let info = llvm::debug_local_variable(&ctx, dbg_values[0].get_operation())
-            .expect("mir.dbg_value should carry the promoted local metadata");
-        assert_eq!(info.name, "x");
-        assert_eq!(info.argument_index, Some(1));
-        assert_eq!(
-            llvm::debug_local_source_scope(&ctx, dbg_values[0].get_operation()),
-            Some(9),
-            "mem2reg salvage should keep the local's MIR source-scope owner"
-        );
-        assert_eq!(
-            dbg_values[0].get_operation().deref(&ctx).loc(),
-            decl_loc,
-            "debug records for source-less promoted ops should fall back to the local declaration"
-        );
-    }
-
-    #[test]
-    fn mem2reg_salvages_fragment_only_alloca_into_mir_dbg_value() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![i32_ty], vec![i32_ty]);
-        let arg = block.deref(&ctx).get_argument(0);
-
-        let alloca_op = Operation::new(
-            &mut ctx,
-            mir::MirAllocaOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        let alloca_loc = src_location(&mut ctx, "kernel.rs", 20, 9);
-        alloca_op.deref_mut(&ctx).set_loc(alloca_loc);
-        llvm::set_debug_fragment_variables(
-            &mut ctx,
-            alloca_op,
-            &[llvm::DebugFragmentVariableInfo {
-                variable: llvm::DebugLocalVariableInfo {
-                    name: "pair".to_string(),
-                    argument_index: None,
-                    ty: llvm::DebugLocalTypeKind::Array {
-                        name: "[u32; 2]".to_string(),
-                        size_bits: 64,
-                        element: Box::new(llvm::DebugLocalTypeKind::Basic {
-                            name: "u32".to_string(),
-                            size_bits: 32,
-                            encoding: "DW_ATE_unsigned",
-                        }),
-                        count: 2,
-                    },
-                },
-                fragment: llvm::DebugFragment {
-                    offset_bits: 32,
-                    size_bits: 32,
-                },
-                source_scope: Some(9),
-                declaration: Some(llvm::DebugSourcePosition {
-                    file: PathBuf::from("kernel.rs"),
-                    line: 20,
-                    column: 9,
-                }),
-            }],
-        );
-        alloca_op.insert_at_back(block, &ctx);
-        let slot = alloca_op.deref(&ctx).get_result(0);
-
-        let store_op = Operation::new(
-            &mut ctx,
-            mir::MirStoreOp::get_concrete_op_info(),
-            vec![],
-            vec![slot, arg],
-            vec![],
-            0,
-        );
-        store_op.insert_at_back(block, &ctx);
-
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![i32_ty],
-            vec![slot],
-            vec![],
-            0,
-        );
-        load_op.insert_at_back(block, &ctx);
-        let loaded = load_op.deref(&ctx).get_result(0);
-        append_mir_return(&mut ctx, block, vec![loaded]);
-
-        let mut analyses = pliron::pass::AnalysisManager::default();
-        pliron::opts::mem2reg::mem2reg(module_ptr, &mut ctx, &mut analyses)
-            .expect("mem2reg should promote fragment storage");
-
-        let dbg_values = find_all::<mir::MirDbgValueOp>(&ctx, &[block]);
-        assert!(
-            !dbg_values.is_empty(),
-            "fragment-only storage should still produce mir.dbg_value salvage"
-        );
-        let fragments = llvm::debug_fragment_variables(&ctx, dbg_values[0].get_operation());
-        assert_eq!(fragments.len(), 1);
-        assert_eq!(fragments[0].variable.name, "pair");
-        assert_eq!(fragments[0].fragment.offset_bits, 32);
-        assert_eq!(fragments[0].fragment.size_bits, 32);
-    }
-
-    #[test]
-    fn convert_load_preserves_volatile() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, false);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into()], vec![]);
-        let ptr_val = block.deref(&ctx).get_argument(0);
-
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![i32_ty],
-            vec![ptr_val],
-            vec![],
-            0,
-        );
-        mir::MirLoadOp::new(load_op).set_volatile(&mut ctx, true);
-        load_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let load = find_first::<llvm::LoadOp>(&ctx, &body).unwrap();
-        assert!(
-            llvm_export::ops::op_volatile(&ctx, load.get_operation()),
-            "volatile mir.load must lower to a volatile llvm.load"
-        );
-    }
-
-    #[test]
-    fn convert_ref_lowers_to_alloca_then_store() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let mir_ptr_ty =
-            MirPtrType::get_generic_with_kind(&mut ctx, i32_ty, false, MirPointerKind::SharedRef);
-
-        // Take a u32 by value, build `&x`.
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![i32_ty], vec![]);
-        let arg = block.deref(&ctx).get_argument(0);
-
-        let ref_op_ptr = Operation::new(
-            &mut ctx,
-            mir::MirRefOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![arg],
-            vec![],
-            0,
-        );
-        let ref_op = mir::MirRefOp::new(ref_op_ptr);
-        ref_op.set_mutable(&mut ctx, false);
-        ref_op.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-        ref_op_ptr.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        assert_eq!(
-            count_ops::<llvm::AllocaOp>(&ctx, &body),
-            1,
-            "ref must materialize via alloca"
-        );
-        assert_eq!(
-            count_ops::<llvm::StoreOp>(&ctx, &body),
-            1,
-            "ref must store the value into the alloca"
-        );
-        assert_eq!(count_ops::<mir::MirRefOp>(&ctx, &body), 0);
-    }
-
-    #[test]
-    fn convert_ref_preserves_tuple_alignment_on_alloca_and_store() {
-        let mut ctx = make_ctx();
-        let tuple_ty = over_aligned_tuple_ty(&mut ctx);
-        let mir_ptr_ty =
-            MirPtrType::get_generic_with_kind(&mut ctx, tuple_ty, false, MirPointerKind::SharedRef);
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-
-        let undef = mir::MirUndefOp::new(&mut ctx, tuple_ty);
-        undef.get_operation().insert_at_back(block, &ctx);
-        let value = undef.get_operation().deref(&ctx).get_result(0);
-        let ref_op = Operation::new(
-            &mut ctx,
-            mir::MirRefOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![value],
-            vec![],
-            0,
-        );
-        let mir_ref = mir::MirRefOp::new(ref_op);
-        mir_ref.set_mutable(&mut ctx, false);
-        mir_ref.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-        ref_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).expect("expected llvm.alloca");
-        let store = find_first::<llvm::StoreOp>(&ctx, &body).expect("expected llvm.store");
-        assert_eq!(
-            llvm_export::ops::op_alignment(&ctx, alloca.get_operation()),
-            Some(32)
-        );
-        assert_eq!(
-            llvm_export::ops::op_alignment(&ctx, store.get_operation()),
-            Some(32)
-        );
-    }
-
-    #[test]
-    fn convert_ref_preserves_over_aligned_union_array_layout_and_alignment() {
-        for abi_align in [32, 64] {
-            let mut ctx = make_ctx();
-            let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
-            let union_ty: TypeHandle = MirUnionType::get(
-                &mut ctx,
-                format!("Align{abi_align}Union"),
-                vec!["word".into()],
-                vec![u32_ty],
-                abi_align,
-                abi_align,
-            )
-            .into();
-            let array_ty: TypeHandle = MirArrayType::get(&mut ctx, union_ty, 3).into();
-            let mir_ptr_ty = MirPtrType::get_generic_with_kind(
-                &mut ctx,
-                array_ty,
-                false,
-                MirPointerKind::SharedRef,
-            );
-            let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-
-            let undef = mir::MirUndefOp::new(&mut ctx, array_ty);
-            undef.get_operation().insert_at_back(block, &ctx);
-            let value = undef.get_operation().deref(&ctx).get_result(0);
-            let ref_op = Operation::new(
-                &mut ctx,
-                mir::MirRefOp::get_concrete_op_info(),
-                vec![mir_ptr_ty.into()],
-                vec![value],
-                vec![],
-                0,
-            );
-            let mir_ref = mir::MirRefOp::new(ref_op);
-            mir_ref.set_mutable(&mut ctx, false);
-            mir_ref.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-            ref_op.insert_at_back(block, &ctx);
-            append_mir_return(&mut ctx, block, vec![]);
-
-            crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-            let body = kernel_blocks(&ctx, module_ptr);
-            let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).expect("expected llvm.alloca");
-            let store = find_first::<llvm::StoreOp>(&ctx, &body).expect("expected llvm.store");
-            let llvm_array_ty = alloca.result_pointee_type(&ctx);
-            let llvm_array_data = llvm_array_ty.deref(&ctx);
-            let llvm_array = llvm_array_data
-                .downcast_ref::<ArrayType>()
-                .expect("over-aligned union array must remain an LLVM array");
-
-            assert_eq!(llvm_array.size(), 3);
-            assert_eq!(
-                crate::convert::types::llvm_type_size_align(&ctx, llvm_array.elem_type()),
-                Some((abi_align, 16))
-            );
-            assert_eq!(
-                crate::convert::types::llvm_type_size_align(&ctx, llvm_array_ty),
-                Some((abi_align * 3, 16))
-            );
-            assert_eq!(
-                llvm_export::ops::op_alignment(&ctx, alloca.get_operation()),
-                Some(abi_align as u32)
-            );
-            assert_eq!(
-                llvm_export::ops::op_alignment(&ctx, store.get_operation()),
-                Some(abi_align as u32)
-            );
-        }
-    }
-
-    #[test]
-    fn convert_ptr_offset_lowers_to_gep_with_pointee_elem_type() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into(), i64_ty], vec![]);
-        let ptr_val = block.deref(&ctx).get_argument(0);
-        let off_val = block.deref(&ctx).get_argument(1);
-
-        let off_op = Operation::new(
-            &mut ctx,
-            mir::MirPtrOffsetOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![ptr_val, off_val],
-            vec![],
-            0,
-        );
-        off_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let gep = find_first::<llvm::GetElementPtrOp>(&ctx, &body).expect("expected one llvm.gep");
-        // Element type must come from the MirPtrType pointee (i32), not the
-        // i8 fallback used when no operand-type info is available.
-        let elem_ty = gep.src_elem_type(&ctx);
-        let elem_ty_ref = elem_ty.deref(&ctx);
-        let int_ty = elem_ty_ref
-            .downcast_ref::<IntegerType>()
-            .expect("gep src_elem_type should be IntegerType");
-        assert_eq!(int_ty.width(), 32, "gep elem type must be i32 (pointee)");
-        assert!(
-            llvm::gep_inbounds(&ctx, gep.get_operation()),
-            "ordinary pointer offsets retain the in-bounds contract"
-        );
-    }
-
-    #[test]
-    fn convert_wrapping_ptr_offset_lowers_to_non_inbounds_gep() {
-        let mut ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, false);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into(), i64_ty], vec![]);
-        let ptr_val = block.deref(&ctx).get_argument(0);
-        let off_val = block.deref(&ctx).get_argument(1);
-
-        let off_op = Operation::new(
-            &mut ctx,
-            mir::MirPtrOffsetOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![ptr_val, off_val],
-            vec![],
-            0,
-        );
-        mir::MirPtrOffsetOp::new(off_op).set_inbounds(&mut ctx, false);
-        off_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let gep = find_first::<llvm::GetElementPtrOp>(&ctx, &body).expect("expected one llvm.gep");
-        assert!(
-            !llvm::gep_inbounds(&ctx, gep.get_operation()),
-            "wrapping pointer offsets must not promise in-bounds arithmetic"
-        );
-    }
-
-    // =========================================================================
-    // Enum layout: converted width per shape + divergent-enum rejection
-    // =========================================================================
-
-    use dialect_mir::types::{EnumVariant, MirEnumType};
-
-    /// Build a Direct-tag `MirEnumType` the way the importer does:
-    /// unsigned tag of `tag_bits`, plus rustc's `total_size`/`abi_align`.
-    fn make_enum_ty(
-        ctx: &mut Context,
-        name: &str,
-        tag_bits: u32,
-        variants: Vec<EnumVariant>,
-        total_size: u64,
-        abi_align: u64,
-    ) -> TypeHandle {
-        let tag_ty: TypeHandle = IntegerType::get(ctx, tag_bits, Signedness::Unsigned).into();
-        // Sequential 0..n discriminants: these layout tests only exercise
-        // size/width, not value mapping.
-        let discriminants: Vec<u64> = (0..variants.len() as u64).collect();
-        MirEnumType::get_with_layout(
-            ctx,
-            name.to_string(),
-            tag_ty,
-            discriminants,
-            variants,
-            0, // tag at byte 0, like every shape these tests exercise
-            total_size,
-            abi_align,
-        )
-        .into()
-    }
-
-    fn unit_variants(n: usize) -> Vec<EnumVariant> {
-        (0..n).map(|i| EnumVariant::unit(format!("V{i}"))).collect()
-    }
-
-    /// Converted enum allocation size must equal rustc's `total_size` for
-    /// every memory-faithful tag shape: that size is what GEP strides by.
-    #[test]
-    fn enum_conversion_strides_by_rustc_size() {
-        use crate::convert::types::llvm_type_size_align;
-
-        let mut ctx = make_ctx();
-
-        // #[repr(u32)] fieldless (issue #118 shape): {i32}, 4 bytes.
-        let repr_u32 = make_enum_ty(&mut ctx, "ReprU32", 32, unit_variants(4), 4, 4);
-        let conv = convert_type(&mut ctx, repr_u32).unwrap();
-        assert_eq!(
-            llvm_type_size_align(&ctx, conv),
-            Some((4, 4)),
-            "repr(u32) tag"
-        );
-
-        // #[repr(usize)] fieldless: {i64}, 8 bytes.
-        let repr_usize = make_enum_ty(&mut ctx, "ReprUsize", 64, unit_variants(4), 8, 8);
-        let conv = convert_type(&mut ctx, repr_usize).unwrap();
-        assert_eq!(
-            llvm_type_size_align(&ctx, conv),
-            Some((8, 8)),
-            "repr(usize) tag"
-        );
-
-        // repr(align(8)) with an i8 tag: the byte claims alone would give
-        // alignment 1, so the slot map raises the storage alignment with a
-        // zero-length anchor field. Size and alignment must both match
-        // rustc, or arrays and by-value ABI uses would be unsound.
-        let padded = make_enum_ty(&mut ctx, "Padded", 8, unit_variants(2), 8, 8);
-        let conv = convert_type(&mut ctx, padded).unwrap();
-        assert_eq!(
-            llvm_type_size_align(&ctx, conv),
-            Some((8, 8)),
-            "repr(align(8)) i8 tag"
-        );
-
-        // u8 tag + i64 payload, rustc size 16: the slot map places the
-        // payload at its rustc byte offset 8 behind an explicit
-        // [7 x i8] filler, making the layout datalayout-independent.
-        let i64_payload: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let payload = make_enum_ty(
-            &mut ctx,
-            "OnePayload",
-            8,
-            vec![
-                EnumVariant::new_with_layout("A".to_string(), vec![i64_payload], vec![8], vec![8]),
-                EnumVariant::unit("B".to_string()),
-            ],
-            16,
-            8,
-        );
-        let conv = convert_type(&mut ctx, payload).unwrap();
-        let (size, _align) = llvm_type_size_align(&ctx, conv).unwrap();
-        assert_eq!(size, 16, "natural layout matches rustc size, no pad");
-        let conv_ref = conv.deref(&ctx);
-        let struct_ty = conv_ref
-            .downcast_ref::<llvm_export::types::StructType>()
-            .expect("converted enum is a struct");
-        assert_eq!(
-            struct_ty.fields().count(),
-            3,
-            "{{tag, [7 x i8] filler, payload}}: explicit filler to byte 8"
-        );
-    }
-
-    /// Multi-payload enum: variants overlap in Rust, and identical
-    /// (offset, converted type) payloads share one typed slot, so the
-    /// converted struct is byte-identical to rustc's layout AND every
-    /// access stays pure SSA (no spill).
-    #[test]
-    fn multi_payload_enum_shares_payload_slot() {
-        use crate::convert::types::{build_enum_slot_map, llvm_type_size_align};
-
-        let mut ctx = make_ctx();
-        let e = make_multi_payload_enum_ty(&mut ctx);
-        let map = build_enum_slot_map(&mut ctx, e).unwrap();
-        assert_eq!(map.carrier_slot, Some(0));
-        assert_eq!(
-            map.field_slots,
-            vec![Some(1), Some(1)],
-            "A.0 and B.0 overlap at byte 4 with the same type: one shared slot"
-        );
-        assert_eq!(
-            llvm_type_size_align(&ctx, map.llvm_struct_ty),
-            Some((8, 4)),
-            "byte-identical to rustc's 8-byte layout, not the 12-byte concat"
-        );
-    }
-
-    /// rustc may place the tag AFTER payload bytes; the slot map must
-    /// follow the recorded tag_offset, never assume slot 0.
-    #[test]
-    fn enum_slot_map_tag_not_at_zero() {
-        use crate::convert::types::{build_enum_slot_map, llvm_type_size_align};
-
-        let mut ctx = make_ctx();
-        let u64_a: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let u64_b: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let tag_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        // enum F { A(u64), B(u64) }: payloads share byte 0, tag at byte 8.
-        let ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "TagAtEight".to_string(),
-            tag_ty,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout("A".to_string(), vec![u64_a], vec![0], vec![8]),
-                EnumVariant::new_with_layout("B".to_string(), vec![u64_b], vec![0], vec![8]),
-            ],
-            8,
-            16,
-            8,
-        )
-        .into();
-        let map = build_enum_slot_map(&mut ctx, ty).unwrap();
-        assert_eq!(
-            map.field_slots,
-            vec![Some(0), Some(0)],
-            "payloads share the first slot"
-        );
-        assert_eq!(
-            map.carrier_slot,
-            Some(1),
-            "tag claims its own slot at byte 8"
-        );
-        let (size, _align) = llvm_type_size_align(&ctx, map.llvm_struct_ty).unwrap();
-        assert_eq!(size, 16, "{{ i64, i8, [7 x i8] }}");
-    }
-
-    /// Multi-payload enum whose variants overlap in Rust: both payloads use
-    /// bytes 4..8 after the direct `u32` tag, so the complete value is eight
-    /// bytes. Mimics `#[repr(u32)] enum E { A(u32), B(u32) }`.
-    fn make_multi_payload_enum_ty(ctx: &mut Context) -> TypeHandle {
-        let i32_a: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-        let i32_b: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
-        make_enum_ty(
-            ctx,
-            "MultiPayload",
-            32,
-            vec![
-                EnumVariant::new_with_layout("A".to_string(), vec![i32_a], vec![4], vec![4]),
-                EnumVariant::new_with_layout("B".to_string(), vec![i32_b], vec![4], vec![4]),
-            ],
-            8,
-            4,
-        )
-    }
-
-    /// Device-local GEP + load must use the same exact eight-byte rustc layout
-    /// as every other enum path. This protects pointer stride in issue #131's
-    /// in-kernel `[E; 4]` arrays; the sibling kernel-parameter test proves the
-    /// same representation is also valid at the host/device boundary.
-    #[test]
-    fn device_local_multi_payload_enum_gep_and_load_lower() {
-        let mut ctx = make_ctx();
-        let enum_ty = make_multi_payload_enum_ty(&mut ctx);
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, enum_ty, true);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into(), i64_ty], vec![]);
-        let ptr_val = block.deref(&ctx).get_argument(0);
-        let off_val = block.deref(&ctx).get_argument(1);
-
-        let off_op = Operation::new(
-            &mut ctx,
-            mir::MirPtrOffsetOp::get_concrete_op_info(),
-            vec![mir_ptr_ty.into()],
-            vec![ptr_val, off_val],
-            vec![],
-            0,
-        );
-        off_op.insert_at_back(block, &ctx);
-        let elem_ptr = off_op.deref(&ctx).get_result(0);
-
-        let load_op = Operation::new(
-            &mut ctx,
-            mir::MirLoadOp::get_concrete_op_info(),
-            vec![enum_ty],
-            vec![elem_ptr],
-            vec![],
-            0,
-        );
-        load_op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect("device-local rustc-layout enum GEP + load must lower");
-    }
-
-    /// A kernel parameter may carry this enum because the device slot map is
-    /// byte-identical to rustc's overlapped host layout.
-    #[test]
-    fn kernel_param_accepts_multi_payload_enum() {
-        use pliron::builtin::attributes::StringAttr;
-
-        let mut ctx = make_ctx();
-        let enum_ty = make_multi_payload_enum_ty(&mut ctx);
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, enum_ty, false);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into()], vec![]);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        // Mark the function as a GPU kernel the way the importer does.
-        {
-            let module_block = module_ptr
-                .deref(&ctx)
-                .get_region(0)
-                .deref(&ctx)
-                .iter(&ctx)
-                .next()
-                .unwrap();
-            let func_op = module_block.deref(&ctx).iter(&ctx).next().unwrap();
-            let kernel_attr = StringAttr::new("true".to_string());
-            let key: pliron::identifier::Identifier = "gpu_kernel".try_into().unwrap();
-            func_op.deref_mut(&ctx).attributes.set(key, kernel_attr);
-        }
-
-        // The slot map lowers MultiPayload byte-identically to rustc's
-        // layout ({ i32, i32 }, 8 bytes), so the kernel ABI accepts it.
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect("multi-payload enum kernel param must lower");
-    }
-
-    /// A legacy enum without physical rustc metadata must be rejected at the
-    /// kernel boundary. Importer-produced niche layouts are now known and are
-    /// accepted; this fixture deliberately constructs `Unknown` metadata.
-    #[test]
-    fn kernel_param_rejects_enum_with_unknown_layout() {
-        use pliron::builtin::attributes::StringAttr;
-
-        let mut ctx = make_ctx();
-        // MirEnumType::get with no layout is the legacy Unknown form.
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let pointee = MirPtrType::get_generic(&mut ctx, i32_ty, false);
-        let tag_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
-        let niched: TypeHandle = MirEnumType::get(
-            &mut ctx,
-            "Option".to_string(),
-            tag_ty,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".to_string()),
-                EnumVariant::new("Some".to_string(), vec![pointee.into()]),
-            ],
-        )
-        .into();
-        let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, niched, false);
-
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into()], vec![]);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        {
-            let module_block = module_ptr
-                .deref(&ctx)
-                .get_region(0)
-                .deref(&ctx)
-                .iter(&ctx)
-                .next()
-                .unwrap();
-            let func_op = module_block.deref(&ctx).iter(&ctx).next().unwrap();
-            let kernel_attr = StringAttr::new("true".to_string());
-            let key: pliron::identifier::Identifier = "gpu_kernel".try_into().unwrap();
-            func_op.deref_mut(&ctx).attributes.set(key, kernel_attr);
-        }
-
-        let err = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect_err("unknown-layout enum kernel param must be rejected");
-        let msg = format!("{err}");
-        assert!(
-            msg.contains("Option") && msg.contains("kernel boundary"),
-            "error must name the enum and the kernel boundary, got: {msg}"
-        );
-        assert!(msg.contains("unknown physical rustc layout"));
-    }
-
-    /// Build a `mir.shared_alloc` returning `MirPtrType<i32, addrspace=3>` of
-    /// length `size`, with the given alloc_key, and append it to `block`.
-    fn append_shared_alloc(
-        ctx: &mut Context,
-        block: Ptr<BasicBlock>,
-        alloc_key: &str,
-        size: u64,
-    ) -> Ptr<Operation> {
-        append_shared_alloc_named(ctx, block, alloc_key, size, None)
-    }
-
-    /// As [`append_shared_alloc`], additionally carrying the Rust path of the
-    /// `static` the allocation came from.
-    fn append_shared_alloc_named(
-        ctx: &mut Context,
-        block: Ptr<BasicBlock>,
-        alloc_key: &str,
-        size: u64,
-        source_name: Option<&str>,
-    ) -> Ptr<Operation> {
-        let i32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Signless).into();
-        append_shared_alloc_typed(ctx, block, alloc_key, i32_ty, size, source_name, 0)
-    }
-
-    #[allow(clippy::too_many_arguments)]
-    fn append_shared_alloc_typed(
-        ctx: &mut Context,
-        block: Ptr<BasicBlock>,
-        alloc_key: &str,
-        element_type: TypeHandle,
-        size: u64,
-        source_name: Option<&str>,
-        alignment: u64,
-    ) -> Ptr<Operation> {
-        use pliron::builtin::attributes::IntegerAttr;
-        use pliron::utils::apint::APInt;
-
-        let i32_ty = element_type;
-        let result_ty = MirPtrType::get_shared(ctx, i32_ty, true);
-        let op = Operation::new(
-            ctx,
-            mir::MirSharedAllocOp::get_concrete_op_info(),
-            vec![result_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        let alloc = mir::MirSharedAllocOp::new(op);
-        alloc.set_attr_elem_type(ctx, TypeAttr::new(i32_ty));
-        let size_attr = IntegerAttr::new(
-            IntegerType::get(ctx, 64, Signedness::Signless),
-            APInt::from_u64(size, std::num::NonZeroUsize::new(64).unwrap()),
-        );
-        alloc.set_attr_size(ctx, size_attr);
-        alloc.set_attr_alloc_key(ctx, StringAttr::new(alloc_key.to_string()));
-        if let Some(source_name) = source_name {
-            alloc.set_attr_source_name(ctx, StringAttr::new(source_name.to_string()));
-        }
-        if alignment != 0 {
-            alloc.set_alignment_value(ctx, alignment);
-        }
-        op.insert_at_back(block, ctx);
-        op
-    }
-
-    fn shared_array_debug_info(count: u64) -> llvm::DebugGlobalVariableInfo {
-        llvm::DebugGlobalVariableInfo {
-            name: "TILE".to_string(),
-            namespace: vec!["fixture".to_string(), "kernel".to_string()],
-            ty: llvm::DebugLocalTypeKind::Array {
-                name: format!("[i32; {count}]"),
-                size_bits: count * 32,
-                element: Box::new(llvm::DebugLocalTypeKind::Basic {
-                    name: "i32".to_string(),
-                    size_bits: 32,
-                    encoding: "DW_ATE_signed",
-                }),
-                count,
-            },
-            declaration: llvm::DebugSourcePosition {
-                file: PathBuf::from("/tmp/shared.rs"),
-                line: 7,
-                column: 5,
-            },
-            is_local_to_unit: true,
-            is_function_local: true,
-        }
-    }
-
-    fn shared_static_key(symbol: &str) -> String {
-        dialect_mir::ops::encode_rust_static_global_key(symbol)
-    }
-
-    #[test]
-    fn convert_shared_alloc_creates_global_in_addrspace_3() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        append_shared_alloc(&mut ctx, block, "k1", 64);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        // Global lives at module level; addressof lives in the function body.
-        let top = module_top_block(&ctx, module_ptr);
-        let global = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .find_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-            .expect("expected an llvm.global for the shared allocation");
-        assert_eq!(
-            global.address_space(&ctx),
-            llvm_addr::SHARED,
-            "shared_alloc global must live in addrspace 3"
-        );
-        assert!(
-            global
-                .get_symbol_name(&ctx)
-                .to_string()
-                .starts_with("__shared_mem_"),
-            "shared global should have __shared_mem_ prefix"
-        );
-
-        let body = kernel_blocks(&ctx, module_ptr);
-        let addrof =
-            find_first::<llvm::AddressOfOp>(&ctx, &body).expect("expected an llvm.addressof");
-        assert_eq!(
-            ptr_addrspace(
-                &ctx,
-                addrof
-                    .get_operation()
-                    .deref(&ctx)
-                    .get_result(0)
-                    .get_type(&ctx)
-            ),
-            llvm_addr::SHARED,
-        );
-    }
-
-    #[test]
-    fn convert_shared_alloc_deduplicates_by_alloc_key() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        // Two allocations sharing the same alloc_key — they must collapse to
-        // a single underlying global (this is what enables a single `static`
-        // referenced from multiple sites to land in one shared region).
-        append_shared_alloc(&mut ctx, block, "same-key", 64);
-        append_shared_alloc(&mut ctx, block, "same-key", 64);
-        // A third with a different key must NOT dedupe with them.
-        append_shared_alloc(&mut ctx, block, "other-key", 32);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let top = module_top_block(&ctx, module_ptr);
-        let shared_globals = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-            .filter(|g| g.address_space(&ctx) == llvm_addr::SHARED)
-            .count();
-        assert_eq!(
-            shared_globals, 2,
-            "two distinct alloc_keys must produce two globals"
-        );
-
-        // Each of the three mir.shared_alloc ops becomes one addressof.
-        let body = kernel_blocks(&ctx, module_ptr);
-        assert_eq!(count_ops::<llvm::AddressOfOp>(&ctx, &body), 3);
-    }
-
-    #[test]
-    fn convert_shared_alloc_rejects_conflicting_key_declarations() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        append_shared_alloc(&mut ctx, block, "conflicting-key", 1);
-        let differently_aligned = append_shared_alloc(&mut ctx, block, "conflicting-key", 1);
-        mir::MirSharedAllocOp::new(differently_aligned).set_alignment_value(&mut ctx, 16);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        let error = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect_err("one shared alloc_key must not name differently aligned storage");
-        assert!(
-            error.to_string().contains("incompatible declaration"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn shared_alloc_repeated_debug_identity_is_attached_once() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let key = shared_static_key("_Rfixture4TILE");
-        for _ in 0..2 {
-            let op =
-                append_shared_alloc_named(&mut ctx, block, &key, 32, Some("fixture::kernel::TILE"));
-            let info = shared_array_debug_info(32);
-            llvm::set_debug_global_variable(&mut ctx, op, &info);
-            llvm::set_debug_global_owner_function(&mut ctx, op, "fixture_kernel");
-        }
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-        let top = module_top_block(&ctx, module_ptr);
-        let globals: Vec<_> = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-            .filter(|global| global.address_space(&ctx) == llvm_addr::SHARED)
-            .collect();
-        assert_eq!(
-            globals.len(),
-            1,
-            "repeated references must share one global"
-        );
-        assert_eq!(
-            llvm::debug_global_variable(&ctx, globals[0].get_operation()),
-            Some(shared_array_debug_info(32))
-        );
-        assert_eq!(
-            llvm::debug_global_owner_function(&ctx, globals[0].get_operation()).as_deref(),
-            Some("fixture_kernel")
-        );
-    }
-
-    /// One function-local shared static materialized in two owning functions
-    /// (for example a `#[device]` helper inlined into two kernels) is a valid
-    /// release build, so debug metadata must not turn it into an error. DWARF
-    /// cannot truthfully scope one AS3 object to two subprograms either, so
-    /// the divergent identity fails open: the storage is still shared and the
-    /// debug attachment is dropped.
-    #[test]
-    fn shared_alloc_owner_conflict_drops_debug_metadata() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let key = shared_static_key("_Rfixture4TILE");
-        for owner in ["fixture_kernel", "other_kernel"] {
-            let op =
-                append_shared_alloc_named(&mut ctx, block, &key, 32, Some("fixture::kernel::TILE"));
-            let info = shared_array_debug_info(32);
-            llvm::set_debug_global_variable(&mut ctx, op, &info);
-            llvm::set_debug_global_owner_function(&mut ctx, op, owner);
-        }
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect("divergent debug identity must not fail a build release accepts");
-        let top = module_top_block(&ctx, module_ptr);
-        let globals: Vec<_> = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-            .filter(|global| global.address_space(&ctx) == llvm_addr::SHARED)
-            .collect();
-        assert_eq!(
-            globals.len(),
-            1,
-            "the physical storage must still be shared"
-        );
-        assert!(llvm::debug_global_variable(&ctx, globals[0].get_operation()).is_none());
-        assert!(llvm::debug_global_owner_function(&ctx, globals[0].get_operation()).is_none());
-    }
-
-    #[test]
-    fn dynamic_extern_then_static_shared_rejects_reserved_key_collision() {
-        use pliron::builtin::attributes::IntegerAttr;
-        use pliron::utils::apint::APInt;
-
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
-        let shared_i8 = MirPtrType::get_shared(&mut ctx, i8_ty, true);
-
-        // Lower the dynamic declaration first. Its internal cache key is
-        // deliberately then reused by a static allocation with the same
-        // physical type, size, and alignment. Those declarations must still
-        // be rejected because one is extern storage and one is fixed storage.
-        let dynamic = Operation::new(
-            &mut ctx,
-            mir::MirExternSharedOp::get_concrete_op_info(),
-            vec![shared_i8.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        mir::MirExternSharedOp::new(dynamic).set_alignment_value(&mut ctx, 128);
-        dynamic.insert_at_back(block, &ctx);
-
-        let fixed = Operation::new(
-            &mut ctx,
-            mir::MirSharedAllocOp::get_concrete_op_info(),
-            vec![shared_i8.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        let fixed_alloc = mir::MirSharedAllocOp::new(fixed);
-        fixed_alloc.set_attr_elem_type(&ctx, TypeAttr::new(i8_ty));
-        fixed_alloc.set_attr_size(
-            &ctx,
-            IntegerAttr::new(
-                IntegerType::get(&ctx, 64, Signedness::Unsigned),
-                APInt::from_u64(0, std::num::NonZeroUsize::new(64).unwrap()),
-            ),
-        );
-        fixed_alloc.set_attr_alloc_key(
-            &ctx,
-            StringAttr::new("__dynamic_smem_global_created_kernel_func".to_string()),
-        );
-        fixed_alloc.set_alignment_value(&mut ctx, 128);
-        fixed.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        let error = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect_err("a static allocation must not reuse a dynamic extern declaration");
-        let message = error.to_string();
-        assert!(message.contains("incompatible declaration"), "{message}");
-        assert!(
-            message.contains("duplicate shared alloc_key"),
-            "the dynamic declaration must be observed first, got: {message}"
-        );
-    }
-
-    #[test]
-    fn shared_alloc_mismatched_debug_type_fails_closed_without_failing_lowering() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let key = shared_static_key("_Rfixture4TILE");
-        let op =
-            append_shared_alloc_named(&mut ctx, block, &key, 32, Some("fixture::kernel::TILE"));
-        llvm::set_debug_global_variable(&mut ctx, op, &shared_array_debug_info(31));
-        llvm::set_debug_global_owner_function(&mut ctx, op, "fixture_kernel");
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect("bad optional metadata must not fail compilation");
-        let top = module_top_block(&ctx, module_ptr);
-        let global = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .find_map(|candidate| Operation::get_op::<llvm::GlobalOp>(candidate, &ctx))
-            .expect("shared global");
-        assert!(llvm::debug_global_variable(&ctx, global.get_operation()).is_none());
-        assert!(llvm::debug_global_owner_function(&ctx, global.get_operation()).is_none());
-    }
-
-    #[test]
-    fn barrier_semantic_struct_matches_single_i64_shared_backing() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let key = shared_static_key("_Rfixture7BARRIER");
-        let op = append_shared_alloc_typed(
-            &mut ctx,
-            block,
-            &key,
-            i64_ty,
-            1,
-            Some("fixture::kernel::BARRIER"),
-            8,
-        );
-        let info = llvm::DebugGlobalVariableInfo {
-            name: "BARRIER".to_string(),
-            namespace: vec!["fixture".to_string(), "kernel".to_string()],
-            ty: llvm::DebugLocalTypeKind::Struct {
-                name: "Barrier".to_string(),
-                size_bits: 64,
-                members: vec![llvm::DebugTypeMember {
-                    name: "_state".to_string(),
-                    offset_bits: 0,
-                    ty: llvm::DebugLocalTypeKind::Basic {
-                        name: "u64".to_string(),
-                        size_bits: 64,
-                        encoding: "DW_ATE_unsigned",
-                    },
-                }],
-            },
-            declaration: llvm::DebugSourcePosition {
-                file: PathBuf::from("/tmp/barrier.rs"),
-                line: 8,
-                column: 9,
-            },
-            is_local_to_unit: true,
-            is_function_local: true,
-        };
-        llvm::set_debug_global_variable(&mut ctx, op, &info);
-        llvm::set_debug_global_owner_function(&mut ctx, op, "fixture_kernel");
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("Barrier lowering succeeds");
-        let top = module_top_block(&ctx, module_ptr);
-        let global = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .find_map(|candidate| Operation::get_op::<llvm::GlobalOp>(candidate, &ctx))
-            .expect("Barrier shared global");
-        assert_eq!(global.get_alignment(&ctx), Some(8));
-        assert_eq!(
-            llvm::debug_global_variable(&ctx, global.get_operation()),
-            Some(info)
-        );
-    }
-
-    /// Collect `(symbol, source_name)` for every shared global in the module.
-    fn shared_global_source_names(
-        ctx: &Context,
-        module_ptr: Ptr<Operation>,
-    ) -> Vec<(String, Option<String>)> {
-        use llvm_export::ops::GlobalOpExt;
-
-        let top = module_top_block(ctx, module_ptr);
-        let mut named: Vec<_> = top
-            .deref(ctx)
-            .iter(ctx)
-            .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, ctx))
-            .filter(|g| g.address_space(ctx) == llvm_addr::SHARED)
-            .map(|g| {
-                (
-                    g.get_symbol_name(ctx).to_string(),
-                    g.shared_source_name(ctx),
-                )
-            })
-            .collect();
-        // Globals are inserted at the front of the module block, so iteration
-        // order is the reverse of creation order. Sort for a stable assertion.
-        named.sort();
-        named
-    }
-
-    #[test]
-    fn shared_alloc_source_name_reaches_the_generated_global() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        append_shared_alloc_named(&mut ctx, block, "k1", 64, Some("my_kernel::TILE"));
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let named = shared_global_source_names(&ctx, module_ptr);
-        assert_eq!(named.len(), 1, "expected exactly one shared global");
-        let (symbol, source_name) = &named[0];
-        // The symbol itself must stay anonymous: the whole point of the
-        // sidecar attribute is that it does not perturb the emitted name.
-        assert!(
-            symbol.starts_with("__shared_mem_"),
-            "the generated symbol must not be renamed, got `{symbol}`"
-        );
-        assert_eq!(source_name.as_deref(), Some("my_kernel::TILE"));
-    }
-
-    #[test]
-    fn shared_alloc_without_source_name_leaves_the_global_unlabelled() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        append_shared_alloc(&mut ctx, block, "k1", 64);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let named = shared_global_source_names(&ctx, module_ptr);
-        assert_eq!(named.len(), 1);
-        assert_eq!(named[0].1, None, "an unnamed allocation must stay unnamed");
-    }
-
-    #[test]
-    fn shared_alloc_source_names_are_per_global_not_shared_across_them() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        // Two references to one static dedupe onto a single global, and a
-        // second static gets its own. Each global must carry its own name —
-        // the failure this guards is one name leaking onto every allocation.
-        append_shared_alloc_named(&mut ctx, block, "tile", 64, Some("my_kernel::TILE"));
-        append_shared_alloc_named(&mut ctx, block, "tile", 64, Some("my_kernel::TILE"));
-        append_shared_alloc_named(&mut ctx, block, "scratch", 32, Some("my_kernel::SCRATCH"));
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let names: Vec<_> = shared_global_source_names(&ctx, module_ptr)
-            .into_iter()
-            .map(|(_, source_name)| source_name)
-            .collect();
-        assert_eq!(names.len(), 2, "the shared alloc_key must still dedupe");
-        let mut names: Vec<_> = names.into_iter().map(|n| n.expect("named")).collect();
-        names.sort();
-        assert_eq!(names, vec!["my_kernel::SCRATCH", "my_kernel::TILE"]);
-    }
-
-    #[test]
-    fn shared_alloc_source_name_reaches_the_exported_llvm_ir() {
-        // The end the feature exists for: a consumer holding only the emitted
-        // artifact can tell which Rust `static` a `__shared_mem_N` block is.
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        append_shared_alloc_named(&mut ctx, block, "tile", 64, Some("my_kernel::TILE"));
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let module = Operation::get_op::<pliron::builtin::ops::ModuleOp>(module_ptr, &ctx)
-            .expect("lowered top-level op is a module");
-        let ir = llvm_export::export::export_module_to_string(&ctx, &module).expect("export");
-
-        let comment_index = ir
-            .find("; shared source: my_kernel::TILE")
-            .unwrap_or_else(|| panic!("exported IR must name the shared source:\n{ir}"));
-        let definition_index = ir
-            .find("__shared_mem_")
-            .expect("exported IR must declare the shared global");
-        assert!(
-            comment_index < definition_index,
-            "the source comment must precede the global it describes:\n{ir}"
-        );
-    }
-
-    /// A `__shared_mem_N` or `__device_global_N` index must depend only on
-    /// the module being lowered, not on how many allocations any OTHER
-    /// module has already lowered in this process (#706). Before the fix,
-    /// each `N` came from a `static AtomicUsize` shared across every call in
-    /// the process, so lowering the second of these two modules would have
-    /// produced `__shared_mem_1` and `__device_global_1`, not the `_0` names.
-    #[test]
-    fn shared_and_device_global_indices_are_per_module_not_process_global() {
-        for _ in 0..2 {
-            let mut ctx = make_ctx();
-            let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-            append_shared_alloc(&mut ctx, block, "k", 64);
-            append_global_alloc(&mut ctx, block, "ordinary_static", false);
-            append_mir_return(&mut ctx, block, vec![]);
-
-            crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-            let top = module_top_block(&ctx, module_ptr);
-            let names: Vec<String> = top
-                .deref(&ctx)
-                .iter(&ctx)
-                .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-                .map(|g| g.get_symbol_name(&ctx).to_string())
-                .collect();
-            assert!(
-                names.iter().any(|n| n == "__shared_mem_0"),
-                "a module with exactly one shared allocation must always name it \
-                 __shared_mem_0, regardless of how many other modules already lowered \
-                 one in this process (got {names:?})"
-            );
-            assert!(
-                names.iter().any(|n| n == "__device_global_0"),
-                "a module with exactly one ordinary device global must always name it \
-                 __device_global_0, regardless of how many other modules already \
-                 lowered one in this process (got {names:?})"
-            );
-        }
-    }
-
-    fn append_global_alloc(
-        ctx: &mut Context,
-        block: Ptr<BasicBlock>,
-        global_key: &str,
-        constant: bool,
-    ) -> Ptr<Operation> {
-        let i32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Signless).into();
-        append_global_alloc_typed(ctx, block, global_key, constant, !constant, i32_ty)
-    }
-
-    fn append_global_alloc_typed(
-        ctx: &mut Context,
-        block: Ptr<BasicBlock>,
-        global_key: &str,
-        constant: bool,
-        is_mutable: bool,
-        global_ty: TypeHandle,
-    ) -> Ptr<Operation> {
-        let result_ty = if constant {
-            MirPtrType::get_constant(ctx, global_ty, is_mutable)
-        } else {
-            MirPtrType::get_global(ctx, global_ty, is_mutable)
-        };
-        let op = Operation::new(
-            ctx,
-            mir::MirGlobalAllocOp::get_concrete_op_info(),
-            vec![result_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        let alloc = mir::MirGlobalAllocOp::new(op);
-        alloc.set_attr_global_type(ctx, TypeAttr::new(global_ty));
-        alloc.set_attr_global_key(ctx, StringAttr::new(global_key.to_string()));
-        op.insert_at_back(block, ctx);
-        op
-    }
-
-    #[test]
-    fn convert_global_alloc_deduplicates_matching_storage_across_pointer_mutability() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        append_global_alloc_typed(&mut ctx, block, "same-global", false, false, i32_ty);
-        append_global_alloc_typed(&mut ctx, block, "same-global", false, true, i32_ty);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect("pointer-carrier mutability does not change physical global storage");
-
-        let top = module_top_block(&ctx, module_ptr);
-        let globals = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-            .filter(|global| global.source_global_key(&ctx).as_deref() == Some("same-global"))
-            .count();
-        assert_eq!(globals, 1);
-        assert_eq!(
-            count_ops::<llvm::AddressOfOp>(&ctx, &kernel_blocks(&ctx, module_ptr)),
-            2
-        );
-    }
-
-    #[test]
-    fn convert_global_alloc_rejects_conflicting_key_declarations() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let byte_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
-        let word_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let empty_words: TypeHandle = MirArrayType::get(&mut ctx, word_ty, 0).into();
-
-        let byte =
-            append_global_alloc_typed(&mut ctx, block, "conflicting-global", false, false, byte_ty);
-        let byte = mir::MirGlobalAllocOp::new(byte);
-        byte.set_alignment_value(&mut ctx, 1);
-        byte.mark_immutable(&mut ctx);
-
-        let words = append_global_alloc_typed(
-            &mut ctx,
-            block,
-            "conflicting-global",
-            false,
-            false,
-            empty_words,
-        );
-        let words = mir::MirGlobalAllocOp::new(words);
-        words.set_alignment_value(&mut ctx, 4);
-        words.mark_immutable(&mut ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        let error = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect_err("one global_key must not name incompatible type/alignment storage");
-        assert!(
-            error.to_string().contains("incompatible declaration"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn device_global_declaration_identity_covers_every_storage_property() {
-        let ctx = make_ctx();
-        let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
-        let base = DeviceGlobalDeclaration {
-            mir_type: i32_ty,
-            alignment: 4,
-            addr_space: llvm_addr::GLOBAL,
-            initializer_hex: Some("00000000".to_string()),
-            initializer_relocations: Some("reloc-a".to_string()),
-            debug_info: None,
-            immutable: true,
-        };
-
-        let mut changed = base.clone();
-        changed.mir_type = i64_ty;
-        assert!(base != changed);
-        changed = base.clone();
-        changed.alignment = 8;
-        assert!(base != changed);
-        changed = base.clone();
-        changed.addr_space = llvm_addr::CONSTANT;
-        assert!(base != changed);
-        changed = base.clone();
-        changed.initializer_hex = Some("01000000".to_string());
-        assert!(base != changed);
-        changed = base.clone();
-        changed.initializer_relocations = Some("reloc-b".to_string());
-        assert!(base != changed);
-        changed = base.clone();
-        changed.debug_info = Some(llvm::DebugGlobalVariableInfo {
-            name: "COUNTER".to_string(),
-            namespace: vec!["my_crate".to_string()],
-            ty: llvm::DebugLocalTypeKind::Basic {
-                name: "u32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_unsigned",
-            },
-            declaration: llvm::DebugSourcePosition {
-                file: PathBuf::from("/tmp/global.rs"),
-                line: 7,
-                column: 1,
-            },
-            is_local_to_unit: true,
-            is_function_local: false,
-        });
-        assert!(base != changed);
-        changed = base.clone();
-        changed.immutable = false;
-        assert!(base != changed);
-    }
-
-    #[test]
-    fn convert_global_alloc_places_in_global_or_constant_addrspace() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        append_global_alloc(&mut ctx, block, "ordinary_static", false);
-        let constant_key = dialect_mir::ops::encode_rust_static_global_key("_ZN7my_mod3KEYE");
-        append_global_alloc(&mut ctx, block, &constant_key, true);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let top = module_top_block(&ctx, module_ptr);
-        let globals: Vec<_> = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-            .collect();
-        let global_addr_global = globals
-            .iter()
-            .find(|g| g.address_space(&ctx) == llvm_addr::GLOBAL)
-            .expect("expected one global in addrspace(1)");
-        let global_addr_const = globals
-            .iter()
-            .find(|g| g.address_space(&ctx) == llvm_addr::CONSTANT)
-            .expect("expected one global in addrspace(4)");
-
-        // Constant-memory globals reuse the Rust mangled name so host code can
-        // resolve them by name via `cuModuleGetGlobal`; ordinary globals get
-        // a counter-suffixed `__device_global_N`.
-        assert_eq!(
-            global_addr_const.get_symbol_name(&ctx).to_string(),
-            "_ZN7my_mod3KEYE",
-            "constant globals must keep the raw rustc symbol payload as their name"
-        );
-        assert!(
-            global_addr_global
-                .get_symbol_name(&ctx)
-                .to_string()
-                .starts_with("__device_global_"),
-            "ordinary device globals get the __device_global_ prefix"
-        );
-    }
-
-    #[test]
-    fn ordinary_global_debug_info_survives_lowering_but_constant_memory_stays_out_of_scope() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let ordinary = append_global_alloc(&mut ctx, block, "crate::GLOBAL_COUNTER", false);
-        let constant_key = dialect_mir::ops::encode_rust_static_global_key("_ZN5crate5COEFFE");
-        let constant = append_global_alloc(&mut ctx, block, &constant_key, true);
-        let info = llvm::DebugGlobalVariableInfo {
-            name: "GLOBAL_COUNTER".to_string(),
-            namespace: vec!["crate".to_string(), "state".to_string()],
-            ty: llvm::DebugLocalTypeKind::Basic {
-                name: "u32".to_string(),
-                size_bits: 32,
-                encoding: "DW_ATE_unsigned",
-            },
-            declaration: llvm::DebugSourcePosition {
-                file: PathBuf::from("/tmp/global.rs"),
-                line: 7,
-                column: 1,
-            },
-            is_local_to_unit: true,
-            is_function_local: false,
-        };
-        llvm::set_debug_global_variable(&mut ctx, ordinary, &info);
-        // Deliberately tag AS4 too: the AS1-only implementation must not
-        // accidentally expand its behavior merely because the generic debug
-        // carrier can be attached to any op.
-        llvm::set_debug_global_variable(&mut ctx, constant, &info);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let top = module_top_block(&ctx, module_ptr);
-        let globals: Vec<_> = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-            .collect();
-        let ordinary = globals
-            .iter()
-            .find(|global| global.address_space(&ctx) == llvm_addr::GLOBAL)
-            .expect("ordinary global");
-        let constant = globals
-            .iter()
-            .find(|global| global.address_space(&ctx) == llvm_addr::CONSTANT)
-            .expect("constant global");
-
-        assert_eq!(
-            llvm::debug_global_variable(&ctx, ordinary.get_operation()),
-            Some(info),
-            "source identity and semantic type must survive MIR-to-LLVM lowering"
-        );
-        assert!(
-            llvm::debug_global_variable(&ctx, constant.get_operation()).is_none(),
-            "AS4 debug metadata is a separate feature and must not leak into this AS1 change"
-        );
-    }
-
-    #[test]
-    fn immutable_marking_survives_lowering_and_is_not_assumed() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-
-        // Two ordinary addrspace(1) globals, distinguished by their source key.
-        // Only the promoted one claims immutability; the plain static must not
-        // acquire it, or the exporter would write `constant` for storage the
-        // host can still overwrite by symbol.
-        let promoted = append_global_alloc(&mut ctx, block, "promoted_table", false);
-        mir::MirGlobalAllocOp::new(promoted).mark_immutable(&mut ctx);
-        append_global_alloc(&mut ctx, block, "plain_static", false);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let top = module_top_block(&ctx, module_ptr);
-        let globals: Vec<llvm::GlobalOp> = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-            .collect();
-        let by_key = |key: &str| -> llvm::GlobalOp {
-            *globals
-                .iter()
-                .find(|g| g.source_global_key(&ctx).as_deref() == Some(key))
-                .unwrap_or_else(|| panic!("no lowered global carries source key {key}"))
-        };
-
-        assert!(
-            by_key("promoted_table").is_immutable(&ctx),
-            "a global marked immutable in MIR must stay immutable through lowering"
-        );
-        assert!(
-            !by_key("plain_static").is_immutable(&ctx),
-            "lowering must not infer immutability; only the promoted-constant \
-             sites may claim it"
-        );
-    }
-
-    #[test]
-    fn convert_global_alloc_rejects_conflicting_immutability() {
-        // A plain static and a promoted constant that end up sharing one key
-        // differ only in the immutable flag; that alone must fail closed
-        // instead of silently reusing the first allocation's storage.
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        append_global_alloc(&mut ctx, block, "collision", false);
-        let promoted = append_global_alloc(&mut ctx, block, "collision", false);
-        mir::MirGlobalAllocOp::new(promoted).mark_immutable(&mut ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        let error = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect_err("a shared string with different origins must fail closed");
-        assert!(
-            error.to_string().contains("incompatible declaration"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn initialized_global_lowers_to_byte_storage() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let op = append_global_alloc(&mut ctx, block, "nan_payload", false);
-        let alloc = mir::MirGlobalAllocOp::new(op);
-        alloc.set_alignment_value(&mut ctx, 4);
-        let initializer_key: Identifier = "global_initializer_hex".try_into().unwrap();
-        op.deref_mut(&ctx)
-            .attributes
-            .set(initializer_key, StringAttr::new("3412c07f".to_string()));
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let top = module_top_block(&ctx, module_ptr);
-        let global = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .find_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-            .expect("expected lowered device global");
-        let global_ty = global.get_type(&ctx);
-        let global_ty_ref = global_ty.deref(&ctx);
-        let array_ty = global_ty_ref
-            .downcast_ref::<ArrayType>()
-            .expect("initialized global must use byte-array storage");
-        assert_eq!(array_ty.size(), 4);
-        let elem_ty = array_ty.elem_type();
-        let elem_ty_ref = elem_ty.deref(&ctx);
-        let elem = elem_ty_ref
-            .downcast_ref::<IntegerType>()
-            .expect("byte-array element must be an integer");
-        assert_eq!(elem.width(), 8);
-        assert_eq!(global.get_alignment(&ctx), Some(4));
-        assert_eq!(global.initializer_hex(&ctx).as_deref(), Some("3412c07f"));
-    }
-
-    #[test]
-    fn relocated_global_lowers_to_segmented_storage() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let word_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let mir_global_ty: TypeHandle = MirArrayType::get(&mut ctx, word_ty, 3).into();
-        let result_ty = MirPtrType::get_global(&mut ctx, mir_global_ty, false);
-        let op = Operation::new(
-            &mut ctx,
-            mir::MirGlobalAllocOp::get_concrete_op_info(),
-            vec![result_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        let alloc = mir::MirGlobalAllocOp::new(op);
-        alloc.set_attr_global_type(&ctx, TypeAttr::new(mir_global_ty));
-        alloc.set_attr_global_key(&ctx, StringAttr::new("reference_table".to_string()));
-        alloc.set_alignment_value(&mut ctx, 8);
-        op.deref_mut(&ctx).attributes.set(
-            "global_initializer_hex".try_into().unwrap(),
-            StringAttr::new("000000000000000000000000000000000000000000000000".to_string()),
-        );
-        let encoded =
-            llvm::encode_global_initializer_relocations(&[llvm::GlobalInitializerRelocation {
-                source_offset: 8,
-                width_bytes: 8,
-                target_address_space: llvm_addr::GLOBAL,
-                target_addend: 4,
-                target_key: "target_static".to_string(),
-            }]);
-        op.deref_mut(&ctx).attributes.set(
-            "global_initializer_relocations".try_into().unwrap(),
-            StringAttr::new(encoded.clone()),
-        );
-        op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
-
-        let top = module_top_block(&ctx, module_ptr);
-        let global = top
-            .deref(&ctx)
-            .iter(&ctx)
-            .find_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
-            .expect("expected lowered device global");
-        let global_ty = global.get_type(&ctx);
-        let global_ty_ref = global_ty.deref(&ctx);
-        let storage = global_ty_ref
-            .downcast_ref::<StructType>()
-            .expect("relocated initializer must use segmented struct storage");
-        assert_eq!(storage.num_fields(), 3);
-        assert_eq!(
-            global.source_global_key(&ctx).as_deref(),
-            Some("reference_table")
-        );
-        assert_eq!(
-            global.initializer_relocations(&ctx).as_deref(),
-            Some(encoded.as_str())
-        );
-    }
-
-    #[test]
-    fn relocated_global_uses_packed_storage_for_unaligned_pointer_slot() {
-        let mut ctx = make_ctx();
-        let encoded =
-            llvm::encode_global_initializer_relocations(&[llvm::GlobalInitializerRelocation {
-                source_offset: 1,
-                width_bytes: 8,
-                target_address_space: llvm_addr::GLOBAL,
-                target_addend: 0,
-                target_key: "target_static".to_string(),
-            }]);
-
-        let storage = relocated_initializer_storage_type(&mut ctx, 9, 1, &encoded)
-            .expect("unaligned relocation should use packed storage");
-        let storage_ref = storage.deref(&ctx);
-        let struct_ty = storage_ref
-            .downcast_ref::<StructType>()
-            .expect("relocated initializer must use struct storage");
-        assert_eq!(struct_ty.layout(), StructLayout::Packed);
-        assert_eq!(struct_ty.num_fields(), 2);
-        assert_eq!(
-            crate::convert::types::llvm_type_size_align(&ctx, storage),
-            Some((9, 1))
-        );
-
-        let fields: Vec<_> = struct_ty.fields().collect();
-        let literal_ref = fields[0].deref(&ctx);
-        let literal = literal_ref
-            .downcast_ref::<ArrayType>()
-            .expect("leading literal span must be a byte array");
-        assert_eq!(literal.size(), 1);
-        let pointer_ref = fields[1].deref(&ctx);
-        let pointer = pointer_ref
-            .downcast_ref::<IntegerType>()
-            .expect("relocation slot must be an integer carrier");
-        assert_eq!(pointer.width(), 64);
-    }
-
-    #[test]
-    fn relocated_global_uses_packed_storage_for_underaligned_allocation() {
-        let mut ctx = make_ctx();
-        let encoded =
-            llvm::encode_global_initializer_relocations(&[llvm::GlobalInitializerRelocation {
-                source_offset: 0,
-                width_bytes: 8,
-                target_address_space: llvm_addr::GLOBAL,
-                target_addend: 0,
-                target_key: "target_static".to_string(),
-            }]);
-
-        let storage = relocated_initializer_storage_type(&mut ctx, 8, 1, &encoded)
-            .expect("underaligned allocation should use packed storage");
-        let storage_ref = storage.deref(&ctx);
-        let struct_ty = storage_ref
-            .downcast_ref::<StructType>()
-            .expect("relocated initializer must use struct storage");
-        assert_eq!(struct_ty.layout(), StructLayout::Packed);
-        assert_eq!(
-            crate::convert::types::llvm_type_size_align(&ctx, storage),
-            Some((8, 1))
-        );
-    }
-
-    #[test]
-    fn relocated_global_keeps_naturally_aligned_storage_unpacked() {
-        let mut ctx = make_ctx();
-        let encoded =
-            llvm::encode_global_initializer_relocations(&[llvm::GlobalInitializerRelocation {
-                source_offset: 8,
-                width_bytes: 8,
-                target_address_space: llvm_addr::GLOBAL,
-                target_addend: 0,
-                target_key: "target_static".to_string(),
-            }]);
-
-        let storage = relocated_initializer_storage_type(&mut ctx, 16, 8, &encoded)
-            .expect("aligned relocation should keep ordinary storage");
-        let storage_ref = storage.deref(&ctx);
-        let struct_ty = storage_ref
-            .downcast_ref::<StructType>()
-            .expect("relocated initializer must use struct storage");
-        assert_eq!(struct_ty.layout(), StructLayout::Unpacked);
-    }
-
-    #[test]
-    fn relocated_global_rejects_overlapping_slots() {
-        let mut ctx = make_ctx();
-        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
-        let word_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
-        let mir_global_ty: TypeHandle = MirArrayType::get(&mut ctx, word_ty, 2).into();
-        let result_ty = MirPtrType::get_global(&mut ctx, mir_global_ty, false);
-        let op = Operation::new(
-            &mut ctx,
-            mir::MirGlobalAllocOp::get_concrete_op_info(),
-            vec![result_ty.into()],
-            vec![],
-            vec![],
-            0,
-        );
-        let alloc = mir::MirGlobalAllocOp::new(op);
-        alloc.set_attr_global_type(&ctx, TypeAttr::new(mir_global_ty));
-        alloc.set_attr_global_key(&ctx, StringAttr::new("overlap".to_string()));
-        alloc.set_alignment_value(&mut ctx, 8);
-        op.deref_mut(&ctx).attributes.set(
-            "global_initializer_hex".try_into().unwrap(),
-            StringAttr::new("00000000000000000000000000000000".to_string()),
-        );
-        let encoded = llvm::encode_global_initializer_relocations(&[
-            llvm::GlobalInitializerRelocation {
-                source_offset: 0,
-                width_bytes: 8,
-                target_address_space: llvm_addr::GLOBAL,
-                target_addend: 0,
-                target_key: "a".to_string(),
-            },
-            llvm::GlobalInitializerRelocation {
-                source_offset: 0,
-                width_bytes: 8,
-                target_address_space: llvm_addr::GLOBAL,
-                target_addend: 0,
-                target_key: "b".to_string(),
-            },
-        ]);
-        op.deref_mut(&ctx).attributes.set(
-            "global_initializer_relocations".try_into().unwrap(),
-            StringAttr::new(encoded),
-        );
-        op.insert_at_back(block, &ctx);
-        append_mir_return(&mut ctx, block, vec![]);
-
-        let error = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .expect_err("overlapping relocations must fail closed");
-        assert!(error.to_string().contains("overlaps"), "{error}");
-    }
-}
diff --git a/crates/mir-lower/src/convert/ops/memory/access.rs b/crates/mir-lower/src/convert/ops/memory/access.rs
new file mode 100644
index 0000000000..933b249874
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/access.rs
@@ -0,0 +1,274 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Conversions for `mir.store`, `mir.load`, `mir.alloca`, `mir.ref`, and `mir.ptr_offset`.
+
+use super::common::{
+    anyhow_to_pliron, copy_local_memory_provenance, fail_on_target_dependent_packed_aggregate,
+    pointer_proved_alignment, value_abi_align, value_mir_type,
+};
+use super::debug::copy_debug_local_variable;
+use crate::convert::types::{convert_type, mir_type_abi_align};
+use dialect_mir::types::MirPtrType;
+use llvm_export::ops as llvm;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+use pliron::r#type::Typed;
+
+/// Convert `mir.store` to `llvm.store`.
+///
+/// Operand order: `[ptr, value]` - stores `value` to address `ptr`.
+/// No result is produced (store is a side effect).
+pub(crate) fn convert_store(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    let operands: Vec<_> = op.deref(ctx).operands().collect();
+
+    let (ptr, val) = match operands.as_slice() {
+        [ptr, val] => (*ptr, *val),
+        _ => {
+            return pliron::input_err_noloc!("Store operation requires exactly 2 operands");
+        }
+    };
+
+    // Packed whole-value stores are byte-faithful now that divergent rustc
+    // layouts lower to LLVM packed structs. Keep the target-dependent AS3 case
+    // fail-closed because its physical pointer width is selected only later.
+    fail_on_target_dependent_packed_aggregate(
+        ctx,
+        value_mir_type(ctx, operands_info, val),
+        "storing",
+    )?;
+
+    let llvm_store = llvm::StoreOp::new(ctx, val, ptr);
+    if dialect_mir::ops::MirStoreOp::new(op).is_volatile(ctx) {
+        llvm_export::ops::set_op_volatile(ctx, llvm_store.get_operation(), true);
+    }
+    // The stored value's own type answers first, as it did before. A scalar
+    // records none, though, so fall back to whatever the address itself proved
+    // when it was computed -- for a field projection that is the aggregate's
+    // `abi_align` narrowed to the field's offset, which is otherwise lost here
+    // and costs the pair its vectorization. This mirrors `convert_load`, which
+    // consults the same record for the same reason. When both answer, the
+    // weaker wins: a field of a packed aggregate can place an abi-aligned type
+    // at a byte-aligned address, and the address's proved alignment is the
+    // ceiling of what the store may claim.
+    let abi = value_abi_align(ctx, operands_info, val);
+    let proved = pointer_proved_alignment(ctx, ptr);
+    let align = match (abi, proved) {
+        (Some(abi), Some(proved)) => Some(abi.min(proved)),
+        (abi, proved) => abi.or(proved),
+    };
+    if let Some(align) = align {
+        llvm_export::ops::set_op_alignment(ctx, llvm_store.get_operation(), align as u32);
+    }
+    crate::convert::preserve_location(ctx, op, llvm_store.get_operation());
+    rewriter.insert_operation(ctx, llvm_store.get_operation());
+    rewriter.erase_operation(ctx, op);
+    Ok(())
+}
+
+/// Convert `mir.load` to `llvm.load`.
+///
+/// Takes a single pointer operand and returns the loaded value.
+/// The result type is derived from the MIR operation's result type.
+pub(crate) fn convert_load(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let ptr = op.deref(ctx).get_operand(0);
+    let result_ty = op.deref(ctx).get_result(0).get_type(ctx);
+
+    // Packed whole-value loads are byte-faithful now that divergent rustc
+    // layouts lower to LLVM packed structs. Keep only the target-dependent AS3
+    // physical-image case fail-closed.
+    fail_on_target_dependent_packed_aggregate(ctx, result_ty, "loading")?;
+
+    let llvm_ty = convert_type(ctx, result_ty).map_err(anyhow_to_pliron)?;
+
+    let llvm_load = llvm::LoadOp::new(ctx, ptr, llvm_ty);
+    if dialect_mir::ops::MirLoadOp::new(op).is_volatile(ctx) {
+        llvm_export::ops::set_op_volatile(ctx, llvm_load.get_operation(), true);
+    }
+    // The loaded value's ABI alignment comes from this op's own result type,
+    // which is still the MIR type: result types are only converted by the
+    // op's own rewrite. A scalar records none, so fall back to whatever the
+    // address itself proved when it was computed -- for a field projection
+    // that is the aggregate's `abi_align` narrowed to the field's offset,
+    // which is otherwise lost here and costs the pair its vectorization.
+    // When both answer, the weaker wins: a field of a packed aggregate can
+    // place an abi-aligned type at a byte-aligned address, and the address's
+    // proved alignment is the ceiling of what the load may claim.
+    let abi = mir_type_abi_align(ctx, result_ty);
+    let proved = pointer_proved_alignment(ctx, ptr);
+    let align = match (abi, proved) {
+        (Some(abi), Some(proved)) => Some(abi.min(proved)),
+        (abi, proved) => abi.or(proved),
+    };
+    if let Some(align) = align {
+        llvm_export::ops::set_op_alignment(ctx, llvm_load.get_operation(), align as u32);
+    }
+    rewriter.insert_operation(ctx, llvm_load.get_operation());
+    rewriter.replace_operation(ctx, op, llvm_load.get_operation());
+
+    Ok(())
+}
+
+/// Convert `mir.alloca` to `llvm.alloca`.
+///
+/// `mir.alloca` carries its element type on the result pointer's pointee, and
+/// emits a single-element stack slot of that type. We therefore convert the
+/// pointee to an LLVM type and emit `llvm.alloca <pointee_ty>, i32 1`.
+///
+/// No value is stored into the slot; that is the caller's job via subsequent
+/// `mir.store` / `llvm.store` ops. This matches the mem2reg-ready translator
+/// model where every local is backed by one alloca in the entry block and
+/// defs/uses go through `store`/`load` rather than SSA values.
+pub(crate) fn convert_alloca(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let result_ty = op.deref(ctx).get_result(0).get_type(ctx);
+    let mir_pointee = {
+        let ty_ref = result_ty.deref(ctx);
+        let mir_ptr = ty_ref.downcast_ref::<MirPtrType>().ok_or_else(|| {
+            anyhow_to_pliron(anyhow::anyhow!(
+                "MirAllocaOp result must be MirPtrType (enforced by verifier)"
+            ))
+        })?;
+        mir_ptr.pointee
+    };
+    let llvm_pointee = convert_type(ctx, mir_pointee).map_err(anyhow_to_pliron)?;
+
+    let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+    let one_apint =
+        pliron::utils::apint::APInt::from_i64(1, std::num::NonZeroUsize::new(32).unwrap());
+    let one_attr = pliron::builtin::attributes::IntegerAttr::new(i32_ty, one_apint);
+    let one_const = llvm::ConstantOp::new(ctx, one_attr.into());
+    rewriter.insert_operation(ctx, one_const.get_operation());
+    let one_val = one_const.get_operation().deref(ctx).get_result(0);
+
+    let alloca = llvm::AllocaOp::new(ctx, llvm_pointee, one_val);
+    // The allocated type's ABI alignment comes from this op's own result
+    // pointee, which is still the MIR type at rewrite time.
+    if let Some(align) = mir_type_abi_align(ctx, mir_pointee) {
+        llvm_export::ops::set_op_alignment(ctx, alloca.get_operation(), align as u32);
+    }
+    copy_debug_local_variable(ctx, op, alloca.get_operation());
+    copy_local_memory_provenance(ctx, op, alloca.get_operation());
+    rewriter.insert_operation(ctx, alloca.get_operation());
+    rewriter.replace_operation(ctx, op, alloca.get_operation());
+
+    Ok(())
+}
+
+/// Convert `mir.ref` — materialize the operand in stack memory via alloca+store.
+///
+/// `mir.ref` creates a pointer to an SSA value. In SSA form, values don't have
+/// addresses, so we must place the value in memory to obtain a pointer.
+/// This applies to all types: scalars (e.g. `&factor` where factor is `u32`),
+/// aggregates (e.g. `&closure_env`), and pointers (e.g. `&&T`).
+pub(crate) fn convert_ref(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    let operand = op.deref(ctx).get_operand(0);
+    let operand_ty = operand.get_type(ctx);
+    let abi_align = value_abi_align(ctx, operands_info, operand);
+
+    let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless);
+    let one_apint =
+        pliron::utils::apint::APInt::from_i64(1, std::num::NonZeroUsize::new(32).unwrap());
+    let one_attr = pliron::builtin::attributes::IntegerAttr::new(i32_ty, one_apint);
+    let one_const = llvm::ConstantOp::new(ctx, one_attr.into());
+    rewriter.insert_operation(ctx, one_const.get_operation());
+    let one_val = one_const.get_operation().deref(ctx).get_result(0);
+
+    let alloca = llvm::AllocaOp::new(ctx, operand_ty, one_val);
+    // Honour the referent's repr(align(N)) ABI alignment. Without this, the
+    // synthesised alloca would be under-aligned relative to any loads/stores
+    // that claim the struct's true alignment.
+    if let Some(align) = abi_align {
+        llvm_export::ops::set_op_alignment(ctx, alloca.get_operation(), align as u32);
+    }
+    rewriter.insert_operation(ctx, alloca.get_operation());
+    let alloca_ptr = alloca.get_operation().deref(ctx).get_result(0);
+
+    let store = llvm::StoreOp::new(ctx, operand, alloca_ptr);
+    if let Some(align) = abi_align {
+        llvm_export::ops::set_op_alignment(ctx, store.get_operation(), align as u32);
+    }
+    rewriter.insert_operation(ctx, store.get_operation());
+
+    rewriter.replace_operation_with_values(ctx, op, vec![alloca_ptr]);
+
+    Ok(())
+}
+
+/// Convert `mir.ptr_offset` to `llvm.getelementptr`.
+///
+/// Operands: `[ptr, offset]` where offset is an integer index.
+/// Element sizing comes from the op's own result type, which is still the
+/// MIR pointer type when this converter runs. The operand's recorded type
+/// history is not usable here: a kind-only `mir.cast` lowers to a plain
+/// value forwarding, and the history does not follow that replacement
+/// edge, so a history miss would silently misscale the offset.
+pub(crate) fn convert_ptr_offset(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let loc = op.deref(ctx).loc();
+    let operands: Vec<_> = op.deref(ctx).operands().collect();
+
+    let (ptr, offset) = match operands.as_slice() {
+        [ptr, offset] => (*ptr, *offset),
+        _ => return pliron::input_err!(loc, "PtrOffset requires exactly 2 operands"),
+    };
+
+    let result_ty = op.deref(ctx).get_result(0).get_type(ctx);
+    let pointee = result_ty
+        .deref(ctx)
+        .downcast_ref::<MirPtrType>()
+        .map(|mir_ptr| mir_ptr.pointee)
+        .ok_or_else(|| {
+            pliron::input_error!(
+                loc.clone(),
+                "mir.ptr_offset result must be a MIR pointer type; \
+                 element sizing has no fact to derive from"
+            )
+        })?;
+    let elem_ty = convert_type(ctx, pointee).map_err(anyhow_to_pliron)?;
+
+    let llvm_gep = llvm::GetElementPtrOp::new(
+        ctx,
+        ptr,
+        vec![llvm_export::ops::GepIndex::Value(offset)],
+        elem_ty,
+    );
+    let inbounds = dialect_mir::ops::MirPtrOffsetOp::new(op).is_inbounds(ctx);
+    llvm::set_gep_inbounds(ctx, llvm_gep.get_operation(), inbounds);
+    rewriter.insert_operation(ctx, llvm_gep.get_operation());
+    rewriter.replace_operation(ctx, op, llvm_gep.get_operation());
+
+    Ok(())
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/common.rs b/crates/mir-lower/src/convert/ops/memory/common.rs
new file mode 100644
index 0000000000..14bba3d328
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/common.rs
@@ -0,0 +1,158 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Helpers shared by the memory-op conversions in this module.
+
+use crate::convert::types::{
+    StructLayoutInfo, build_struct_slot_map, convert_type,
+    llvm_packed_struct_contains_pointer_in_address_space, mir_type_abi_align,
+};
+use dialect_mir::types::MirStructType;
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::OperandsInfo;
+use pliron::operation::Operation;
+use pliron::result::Result;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::value::Value;
+
+pub(super) fn anyhow_to_pliron(e: anyhow::Error) -> pliron::result::Error {
+    pliron::create_error!(
+        pliron::location::Location::Unknown,
+        pliron::result::ErrorKind::VerificationFailed,
+        pliron::result::StringError(e.to_string())
+    )
+}
+
+/// Recover the `repr(align(N))` ABI alignment of `value` at conversion time.
+///
+/// The alignment lives on MIR aggregate types (`abi_align`); the converted
+/// LLVM struct types cannot express over-alignment. The conversion driver may
+/// already have converted the value's type (block arguments are converted
+/// before any rewrite runs; replaced op results carry the new type), but it
+/// records every such change. So check the current type first, then walk the
+/// value's conversion history, newest first, for a MIR type that records an
+/// alignment.
+pub(super) fn value_abi_align(
+    ctx: &Context,
+    operands_info: &OperandsInfo,
+    value: Value,
+) -> Option<u64> {
+    mir_type_abi_align(ctx, value.get_type(ctx)).or_else(|| {
+        operands_info
+            .lookup_operand_history(value)
+            .iter()
+            .rev()
+            .find_map(|ty| mir_type_abi_align(ctx, *ty))
+    })
+}
+
+/// The MIR type of `value`: its current type when that is still a MIR type,
+/// else the newest MIR type in its conversion history (same walk as
+/// [`value_abi_align`], for the same reason).
+pub(super) fn value_mir_type(
+    ctx: &Context,
+    operands_info: &OperandsInfo,
+    value: Value,
+) -> TypeHandle {
+    let current = value.get_type(ctx);
+    if current.deref(ctx).is::<MirStructType>() {
+        return current;
+    }
+    operands_info
+        .lookup_operand_history(value)
+        .iter()
+        .rev()
+        .copied()
+        .find(|ty| ty.deref(ctx).is::<MirStructType>())
+        .unwrap_or(current)
+}
+
+/// Refuse only packed by-value images whose physical bytes depend on the
+/// selected NVPTX mode.
+///
+/// Shared-memory pointers are 32-bit in modern NVVM p3:32 but 64-bit in the
+/// PTX/legacy layouts. Lowering runs before that target mode is selected, so a
+/// packed aggregate containing AS3 cannot safely be loaded or stored as one
+/// physical value. Pointer-free packed aggregates and packed aggregates whose
+/// pointers use target-stable address spaces are allowed.
+pub(super) fn fail_on_target_dependent_packed_aggregate(
+    ctx: &mut Context,
+    ty: TypeHandle,
+    verb: &str,
+) -> Result<()> {
+    let llvm_ty = {
+        let layout = {
+            let ty_ref = ty.deref(ctx);
+            ty_ref
+                .downcast_ref::<MirStructType>()
+                .map(StructLayoutInfo::of_struct)
+        };
+        if let Some(layout) = layout {
+            let map = build_struct_slot_map(ctx, &layout).map_err(anyhow_to_pliron)?;
+            if !map.by_value_layout_faithful {
+                return pliron::input_err_noloc!(
+                    "{} a struct whose rustc layout cannot be represented by an LLVM \
+                     struct value is not supported",
+                    verb
+                );
+            }
+            map.llvm_struct_ty
+        } else {
+            convert_type(ctx, ty).map_err(anyhow_to_pliron)?
+        }
+    };
+    if llvm_packed_struct_contains_pointer_in_address_space(
+        ctx,
+        llvm_ty,
+        llvm_export::types::address_space::SHARED,
+    ) {
+        return pliron::input_err_noloc!(
+            "{} a packed aggregate containing a shared-memory pointer by value is \
+             target-mode dependent and is not yet supported",
+            verb
+        );
+    }
+    Ok(())
+}
+
+/// Carry Rust-local provenance from the MIR alloca to the LLVM alloca.
+///
+/// This is compiler-only metadata stored in the in-memory dialect operation;
+/// it is not emitted as LLVM metadata because an unrecognized metadata node is
+/// not a preservation contract for middle-end passes. The textual exporter
+/// instead consumes the attribute to choose a stable SSA name before `opt`.
+pub(super) fn copy_local_memory_provenance(
+    ctx: &mut Context,
+    mir_op: Ptr<Operation>,
+    llvm_op: Ptr<Operation>,
+) {
+    if let Some(provenance) = llvm_export::ops::local_memory_provenance(ctx, mir_op) {
+        llvm_export::ops::set_local_memory_provenance(ctx, llvm_op, provenance);
+    }
+}
+
+/// Alignment the op that computed `ptr` recorded about the address it produced.
+///
+/// Field addresses stamp this during their own conversion, where the aggregate's
+/// `abi_align` is still in hand; by the time a load that consumes the address is
+/// converted, `mir.field_addr` is already a GEP and the MIR aggregate type is no
+/// longer reachable from the load's operands.
+///
+/// Known fidelity limit: the claim rides the address value, not the place
+/// access that justified it. `&raw const (*p).x` through a merely 4-aligned
+/// `p: *const Aligned8` is legal Rust so long as the place itself is never
+/// accessed, yet the later read through the raw pointer consumes this same
+/// stamped GEP and inherits the aggregate's alignment, an over-claim for that
+/// pointer. rustc keeps the two apart by threading alignment through place
+/// evaluation and dropping it at the `&raw` boundary; dialect-mir erases that
+/// distinction before lowering runs, so full fidelity would require stamping
+/// loads during MIR translation instead. Accepted for now: the pattern needs
+/// an actually under-aligned pointer to an over-aligned aggregate, projected
+/// via `&raw` inside a kernel, and any direct access through such a place is
+/// UB to begin with.
+pub(super) fn pointer_proved_alignment(ctx: &Context, ptr: Value) -> Option<u64> {
+    let defining_op = ptr.defining_op()?;
+    llvm_export::ops::address_alignment(ctx, defining_op).map(u64::from)
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/debug.rs b/crates/mir-lower/src/convert/ops/memory/debug.rs
new file mode 100644
index 0000000000..91e9e95b67
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/debug.rs
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Conversions for the debug-value markers and debug-local metadata copying.
+
+use llvm_export::ops as llvm;
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+
+pub(super) fn copy_debug_local_variable(
+    ctx: &mut Context,
+    mir_op: Ptr<Operation>,
+    llvm_op: Ptr<Operation>,
+) {
+    if let Some(info) = llvm_export::ops::debug_local_variable(ctx, mir_op) {
+        llvm_export::ops::set_debug_local_variable(ctx, llvm_op, info);
+    }
+    let projected = llvm_export::ops::debug_projected_variables(ctx, mir_op);
+    if !projected.is_empty() {
+        llvm_export::ops::set_debug_projected_variables(ctx, llvm_op, &projected);
+    }
+    let fragments = llvm_export::ops::debug_fragment_variables(ctx, mir_op);
+    if !fragments.is_empty() {
+        llvm_export::ops::set_debug_fragment_variables(ctx, llvm_op, &fragments);
+    }
+    if let Some(scope) = llvm_export::ops::debug_local_source_scope(ctx, mir_op) {
+        llvm_export::ops::set_debug_local_source_scope(ctx, llvm_op, scope);
+    }
+    if let Some((file, pos)) = llvm_export::ops::debug_local_declaration_location(ctx, mir_op) {
+        llvm_export::ops::set_debug_local_declaration_location(
+            ctx, llvm_op, file, pos.line, pos.column,
+        );
+    }
+    if let Some(expression) = llvm_export::ops::debug_value_expression(ctx, mir_op) {
+        llvm_export::ops::set_debug_value_expression(ctx, llvm_op, &expression);
+    }
+}
+
+/// Convert `mir.dbg_value` to the LLVM-export debug marker.
+///
+/// The op is still debug-only after lowering. The textual LLVM exporter later
+/// prints it as an `llvm.dbg.value` intrinsic call.
+pub(crate) fn convert_dbg_value(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let value = op.deref(ctx).get_operand(0);
+    let loc = op.deref(ctx).loc().clone();
+    let llvm_dbg_value = llvm::DebugValueOp::new(ctx, value);
+    llvm_dbg_value.get_operation().deref_mut(ctx).set_loc(loc);
+    copy_debug_local_variable(ctx, op, llvm_dbg_value.get_operation());
+    rewriter.insert_operation(ctx, llvm_dbg_value.get_operation());
+    rewriter.erase_operation(ctx, op);
+    Ok(())
+}
+
+/// Convert `mir.dbg_value_list` to the LLVM-export multi-value debug marker.
+///
+/// The ordered operands become a `DIArgList` during textual export. The typed
+/// location recipe is carried as generic metadata and copied unchanged here.
+pub(crate) fn convert_dbg_value_list(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+) -> Result<()> {
+    let values: Vec<_> = op.deref(ctx).operands().collect();
+    if values.len() < 2 {
+        return pliron::input_err_noloc!("mir.dbg_value_list requires at least two operands");
+    }
+    if llvm_export::ops::debug_value_expression(ctx, op).is_none() {
+        return pliron::input_err_noloc!("mir.dbg_value_list is missing its debug expression");
+    }
+
+    let loc = op.deref(ctx).loc().clone();
+    let llvm_dbg_value = llvm::DebugValueListOp::new(ctx, values);
+    llvm_dbg_value.get_operation().deref_mut(ctx).set_loc(loc);
+    copy_debug_local_variable(ctx, op, llvm_dbg_value.get_operation());
+    rewriter.insert_operation(ctx, llvm_dbg_value.get_operation());
+    rewriter.erase_operation(ctx, op);
+    Ok(())
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/device_global.rs b/crates/mir-lower/src/convert/ops/memory/device_global.rs
new file mode 100644
index 0000000000..dd591c88a1
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/device_global.rs
@@ -0,0 +1,410 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Conversion of `mir.global_alloc` to device globals, including relocated initializers.
+
+use super::common::anyhow_to_pliron;
+use crate::context::{DeviceGlobalDeclaration, DeviceGlobalRecord, DeviceGlobalsMap};
+use crate::convert::types::{
+    convert_type, llvm_type_size_align, validate_initialized_global_layout,
+    validate_relocated_initialized_global_layout,
+};
+use crate::helpers;
+use llvm_export::ops as llvm;
+use llvm_export::ops::GlobalOpExt;
+use llvm_export::types::{ArrayType, StructLayout, StructType};
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+use pliron::r#type::{TypeHandle, Typed};
+
+/// Convert `mir.global_alloc` to an LLVM global in CUDA global memory.
+///
+/// Ordinary Rust `static` / `static mut` values have grid scope and
+/// application lifetime, so they live in address space 1 rather than the
+/// per-block shared-memory address space.
+pub fn convert_global_alloc_dc(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+    device_globals: &mut DeviceGlobalsMap,
+    next_device_global_index: &mut usize,
+) -> Result<()> {
+    use pliron::builtin::attributes::{StringAttr, TypeAttr};
+
+    let (
+        global_key,
+        mir_global_type,
+        alignment,
+        addr_space,
+        initializer_hex,
+        initializer_relocations,
+        immutable,
+        debug_info,
+    ) = {
+        let global_op = dialect_mir::ops::MirGlobalAllocOp::new(op);
+        let op_ref = op.deref(ctx);
+
+        let global_key_attr = op_ref
+            .attributes
+            .get::<StringAttr>(&"global_key".try_into().unwrap())
+            .ok_or_else(|| {
+                anyhow_to_pliron(anyhow::anyhow!(
+                    "MirGlobalAllocOp missing global_key StringAttr attribute"
+                ))
+            })?;
+        let global_key = String::from((*global_key_attr).clone());
+
+        let global_type_attr = op_ref
+            .attributes
+            .get::<TypeAttr>(&"global_type".try_into().unwrap())
+            .ok_or_else(|| {
+                anyhow_to_pliron(anyhow::anyhow!(
+                    "MirGlobalAllocOp missing global_type TypeAttr attribute"
+                ))
+            })?;
+        let mir_global_type = global_type_attr.get_type(ctx);
+
+        let alignment = global_op.get_alignment_value(ctx).unwrap_or(0);
+        let initializer_hex = op_ref
+            .attributes
+            .get::<StringAttr>(&"global_initializer_hex".try_into().unwrap())
+            .map(|attr| String::from((*attr).clone()));
+        let initializer_relocations = op_ref
+            .attributes
+            .get::<StringAttr>(&"global_initializer_relocations".try_into().unwrap())
+            .map(|attr| String::from((*attr).clone()));
+        let debug_info = llvm::debug_global_variable(ctx, op);
+
+        // Read the address space the op's result already carries — set by
+        // mir-importer based on the static's type (`ConstantMemory<T>` → 4,
+        // ordinary → 1). The dialect verifier accepts both.
+        let res_ty = op_ref.get_result(0).get_type(ctx);
+        let addr_space = res_ty
+            .deref(ctx)
+            .downcast_ref::<dialect_mir::types::MirPtrType>()
+            .map(|p| {
+                if p.address_space == dialect_mir::types::address_space::CONSTANT {
+                    llvm_export::types::address_space::CONSTANT
+                } else {
+                    llvm_export::types::address_space::GLOBAL
+                }
+            })
+            .ok_or_else(|| {
+                anyhow_to_pliron(anyhow::anyhow!(
+                    "MirGlobalAllocOp result is not a MirPtrType"
+                ))
+            })?;
+
+        (
+            global_key,
+            mir_global_type,
+            alignment,
+            addr_space,
+            initializer_hex,
+            initializer_relocations,
+            global_op.is_immutable(ctx),
+            debug_info,
+        )
+    };
+
+    let declaration = DeviceGlobalDeclaration {
+        mir_type: mir_global_type,
+        alignment,
+        addr_space,
+        initializer_hex: initializer_hex.clone(),
+        initializer_relocations: initializer_relocations.clone(),
+        debug_info: debug_info.clone(),
+        immutable,
+    };
+
+    let global_name = if let Some(existing) = device_globals.get(&global_key) {
+        if existing.declaration != declaration {
+            return Err(anyhow_to_pliron(anyhow::anyhow!(
+                "duplicate global_key {:?} has an incompatible declaration",
+                global_key
+            )));
+        }
+        existing.symbol.clone()
+    } else {
+        create_device_global(
+            ctx,
+            op,
+            device_globals,
+            next_device_global_index,
+            DeviceGlobalSpec {
+                key: &global_key,
+                mir_type: mir_global_type,
+                alignment,
+                addr_space,
+                initializer_hex: initializer_hex.as_deref(),
+                initializer_relocations: initializer_relocations.as_deref(),
+                debug_info: debug_info.as_ref(),
+                immutable,
+            },
+        )?
+    };
+
+    let address_of_op = llvm::AddressOfOp::new(ctx, global_name, addr_space);
+    rewriter.insert_operation(ctx, address_of_op.get_operation());
+    rewriter.replace_operation(ctx, op, address_of_op.get_operation());
+
+    Ok(())
+}
+
+struct DeviceGlobalSpec<'a> {
+    key: &'a str,
+    mir_type: TypeHandle,
+    alignment: u64,
+    addr_space: u32,
+    initializer_hex: Option<&'a str>,
+    initializer_relocations: Option<&'a str>,
+    debug_info: Option<&'a llvm::DebugGlobalVariableInfo>,
+    /// Nothing writes this storage, so it exports as LLVM `constant`. Set only
+    /// for the compiler's own promoted constants; see `MirGlobalAllocOp`.
+    immutable: bool,
+}
+
+/// `next_device_global_index` is scoped to one `MirToLlvmConversionDriver`
+/// instance (one module), not a process-global counter: `N` is a function of
+/// this module's own MIR walk order, not of how many other modules have
+/// lowered a device global earlier in the process (#706).
+fn create_device_global(
+    ctx: &mut Context,
+    op: Ptr<Operation>,
+    device_globals: &mut DeviceGlobalsMap,
+    next_device_global_index: &mut usize,
+    spec: DeviceGlobalSpec<'_>,
+) -> Result<pliron::identifier::Identifier> {
+    // An explicit initializer is already the evaluated Rust allocation image.
+    // Pointer-free data stays `[N x i8]`. Initializers with relocations use a
+    // segmented LLVM struct whose literal spans remain byte arrays and whose
+    // pointer slots become pointer-width integers. This preserves both exact
+    // bytes and linker-visible pointer provenance.
+    let semantic_llvm_type = convert_type(ctx, spec.mir_type).map_err(anyhow_to_pliron)?;
+    let (llvm_global_type, alignment) = if let Some(initializer_hex) = spec.initializer_hex {
+        let byte_count = initializer_hex_byte_count(initializer_hex).map_err(anyhow_to_pliron)?;
+        if spec.alignment == 0 {
+            return Err(anyhow_to_pliron(anyhow::anyhow!(
+                "device global initializer is missing its evaluated Rust allocation alignment"
+            )));
+        }
+        let storage_type = if let Some(encoded) = spec.initializer_relocations {
+            validate_relocated_initialized_global_layout(
+                ctx,
+                spec.mir_type,
+                byte_count,
+                spec.alignment,
+            )
+            .map_err(anyhow_to_pliron)?;
+            relocated_initializer_storage_type(ctx, byte_count, spec.alignment, encoded)
+                .map_err(anyhow_to_pliron)?
+        } else {
+            validate_initialized_global_layout(ctx, spec.mir_type, byte_count, spec.alignment)
+                .map_err(anyhow_to_pliron)?;
+            let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
+            ArrayType::get(ctx, i8_ty.into(), byte_count).into()
+        };
+        (storage_type, spec.alignment)
+    } else {
+        if spec.initializer_relocations.is_some() {
+            return Err(anyhow_to_pliron(anyhow::anyhow!(
+                "device global carries relocation metadata without initializer bytes"
+            )));
+        }
+        (semantic_llvm_type, spec.alignment)
+    };
+
+    // Constant-memory globals reuse the Rust-side mangled name so host code can
+    // resolve them by name via `cuModuleGetGlobal`. Ordinary device globals
+    // are private to the kernel and get a counter-based unique name.
+    let name: pliron::identifier::Identifier =
+        if spec.addr_space == llvm_export::types::address_space::CONSTANT {
+            let symbol = dialect_mir::ops::rust_static_symbol_from_global_key(spec.key)
+                .ok_or_else(|| {
+                    anyhow_to_pliron(anyhow::anyhow!(
+                        "constant global_key {:?} is not a tagged Rust static identity",
+                        spec.key
+                    ))
+                })?;
+            symbol.try_into().map_err(|e| {
+                anyhow_to_pliron(anyhow::anyhow!(
+                    "constant Rust static symbol {:?} is not a valid identifier: {e:?}",
+                    symbol
+                ))
+            })?
+        } else {
+            let counter = *next_device_global_index;
+            *next_device_global_index += 1;
+            format!("__device_global_{counter}").try_into().unwrap()
+        };
+
+    let global_op = if alignment > 0 {
+        llvm::GlobalOp::new_with_alignment(ctx, name.clone(), llvm_global_type, alignment)
+    } else {
+        llvm::GlobalOp::new(ctx, name.clone(), llvm_global_type)
+    };
+    global_op.set_address_space(ctx, spec.addr_space);
+    global_op.set_source_global_key(ctx, spec.key);
+    if spec.addr_space == llvm_export::types::address_space::GLOBAL
+        && let Some(info) = spec.debug_info
+    {
+        llvm::set_debug_global_variable(ctx, global_op.get_operation(), info);
+    }
+    if let Some(initializer_hex) = spec.initializer_hex {
+        global_op.set_initializer_hex(ctx, initializer_hex);
+    }
+    if let Some(initializer_relocations) = spec.initializer_relocations {
+        global_op.set_initializer_relocations(ctx, initializer_relocations);
+    }
+    if spec.immutable {
+        global_op.mark_immutable(ctx);
+    }
+
+    let parent_block = op
+        .deref(ctx)
+        .get_parent_block()
+        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Op has no parent block")))?;
+    let module_op = helpers::get_module_from_block(ctx, parent_block).map_err(anyhow_to_pliron)?;
+    let region = module_op.deref(ctx).get_region(0);
+    let module_block = region
+        .deref(ctx)
+        .iter(ctx)
+        .next()
+        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Module is empty")))?;
+
+    global_op.get_operation().insert_at_front(module_block, ctx);
+    device_globals.insert(
+        spec.key.to_string(),
+        DeviceGlobalRecord {
+            symbol: name.clone(),
+            declaration: DeviceGlobalDeclaration {
+                mir_type: spec.mir_type,
+                alignment: spec.alignment,
+                addr_space: spec.addr_space,
+                initializer_hex: spec.initializer_hex.map(str::to_owned),
+                initializer_relocations: spec.initializer_relocations.map(str::to_owned),
+                debug_info: spec.debug_info.cloned(),
+                immutable: spec.immutable,
+            },
+        },
+    );
+
+    Ok(name)
+}
+
+pub(super) fn relocated_initializer_storage_type(
+    ctx: &mut Context,
+    byte_count: u64,
+    allocation_alignment: u64,
+    encoded: &str,
+) -> std::result::Result<TypeHandle, anyhow::Error> {
+    let mut relocations =
+        llvm::decode_global_initializer_relocations(encoded).map_err(anyhow::Error::msg)?;
+    if relocations.is_empty() {
+        anyhow::bail!("device global relocation metadata contains no relocations");
+    }
+    relocations.sort_by_key(|relocation| relocation.source_offset);
+
+    let mut cursor = 0u64;
+    let mut fields = Vec::with_capacity(relocations.len() * 2 + 1);
+    let mut requires_packed_storage = false;
+    let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
+
+    for (index, relocation) in relocations.iter().enumerate() {
+        if relocation.width_bytes != 8 {
+            anyhow::bail!(
+                "device global relocation {index} uses unsupported {}-byte pointer storage; CUDA global/constant pointers require 8 bytes",
+                relocation.width_bytes
+            );
+        }
+        if !matches!(relocation.target_address_space, 1 | 4) {
+            anyhow::bail!(
+                "device global relocation {index} targets unsupported CUDA address space {}",
+                relocation.target_address_space
+            );
+        }
+        if relocation.target_key.is_empty() {
+            anyhow::bail!("device global relocation {index} has an empty target key");
+        }
+
+        let width = u64::from(relocation.width_bytes);
+        requires_packed_storage |=
+            allocation_alignment < width || !relocation.source_offset.is_multiple_of(width);
+        if relocation.source_offset < cursor {
+            anyhow::bail!(
+                "device global relocation {index} overlaps the previous relocation or literal span"
+            );
+        }
+        let end = relocation
+            .source_offset
+            .checked_add(width)
+            .ok_or_else(|| anyhow::anyhow!("device global relocation {index} offset overflows"))?;
+        if end > byte_count {
+            anyhow::bail!(
+                "device global relocation {index} occupies bytes {}..{} but the initializer is only {} bytes",
+                relocation.source_offset,
+                end,
+                byte_count
+            );
+        }
+
+        if relocation.source_offset > cursor {
+            fields
+                .push(ArrayType::get(ctx, i8_ty.into(), relocation.source_offset - cursor).into());
+        }
+        fields.push(IntegerType::get(ctx, relocation.width_bytes * 8, Signedness::Signless).into());
+        cursor = end;
+    }
+
+    if cursor < byte_count {
+        fields.push(ArrayType::get(ctx, i8_ty.into(), byte_count - cursor).into());
+    }
+
+    let layout = if requires_packed_storage {
+        StructLayout::Packed
+    } else {
+        StructLayout::Unpacked
+    };
+    let storage: TypeHandle = StructType::get_unnamed(ctx, (fields, layout)).into();
+    // Exact or error, never guessed: the storage type is built from i8 arrays
+    // and integer slots, so its natural size is always computable, and it must
+    // land exactly on rustc's byte count or the relocation offsets are wrong.
+    let Some((lowered_size, _)) = llvm_type_size_align(ctx, storage) else {
+        anyhow::bail!(
+            "relocated device global storage `{}` has no exact size",
+            storage.deref(ctx).disp(ctx)
+        );
+    };
+    if lowered_size != byte_count {
+        anyhow::bail!(
+            "relocated device global storage lowers to {} bytes, but rustc evaluated {} bytes",
+            lowered_size,
+            byte_count
+        );
+    }
+    Ok(storage)
+}
+
+fn initializer_hex_byte_count(hex: &str) -> std::result::Result<u64, anyhow::Error> {
+    if !hex.len().is_multiple_of(2) {
+        anyhow::bail!("device global initializer has an odd-length hex byte string");
+    }
+    if let Some(invalid) = hex.bytes().find(|byte| !byte.is_ascii_hexdigit()) {
+        anyhow::bail!(
+            "device global initializer contains invalid hex digit {:?}",
+            invalid as char
+        );
+    }
+    u64::try_from(hex.len() / 2)
+        .map_err(|_| anyhow::anyhow!("device global initializer is too large for LLVM"))
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/extern_shared.rs b/crates/mir-lower/src/convert/ops/memory/extern_shared.rs
new file mode 100644
index 0000000000..4db8ff6aa6
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/extern_shared.rs
@@ -0,0 +1,209 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Conversion of `mir.extern_shared` to dynamic shared-memory extern globals.
+
+use super::common::anyhow_to_pliron;
+use crate::context::{
+    DynamicSmemAlignmentMap, SharedGlobalDeclaration, SharedGlobalKind, SharedGlobalRecord,
+    SharedGlobalsMap,
+};
+use crate::helpers;
+use llvm_export::ops as llvm;
+use llvm_export::ops::GlobalOpExt;
+use llvm_export::types::ArrayType;
+use pliron::builtin::op_interfaces::SymbolOpInterface;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+
+/// Convert `mir.extern_shared` to LLVM extern global variable in shared address space.
+///
+/// Dynamic (extern) shared memory is represented as an external global variable
+/// with address space 3 and zero-length array type `[0 x i8]`. The actual size
+/// is determined at kernel launch via `LaunchConfig::shared_mem_bytes`.
+///
+/// # Per-Owner Symbols
+///
+/// Each function that owns an access gets a dynamic shared-memory symbol
+/// (`__dynamic_smem_{function_name}`).
+///
+/// # Alignment
+///
+/// The alignment is pre-computed during the lowering pre-pass. It is the
+/// maximum of the owner's body requirements and every launch-contract marker
+/// that can reach it.
+///
+/// # Byte Offset
+///
+/// - `DynamicSharedArray::get()` / `get_raw()`: offset = 0, returns base pointer
+/// - `DynamicSharedArray::offset(N)`: offset = N bytes, returns base + N
+///
+/// Called directly from `MirToLlvmConversionDriver::rewrite` (not through
+/// op_cast dispatch) because it needs cross-function state maps.
+pub fn convert_extern_shared_dc(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+    shared_globals: &mut SharedGlobalsMap,
+    dynamic_smem_alignments: &mut DynamicSmemAlignmentMap,
+) -> Result<()> {
+    let (byte_offset, alignment) = {
+        let extern_shared_op = dialect_mir::ops::MirExternSharedOp::new(op);
+        let byte_offset = extern_shared_op.get_byte_offset_value(ctx);
+        let alignment = extern_shared_op.get_alignment_value(ctx);
+        (byte_offset, alignment)
+    };
+
+    let func_name: String = {
+        let parent_block = op
+            .deref(ctx)
+            .get_parent_block()
+            .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Op has no parent block")))?;
+        let func_op_ptr = helpers::get_parent_func(ctx, parent_block).map_err(anyhow_to_pliron)?;
+        let llvm_func = Operation::get_op::<llvm::FuncOp>(func_op_ptr, ctx)
+            .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Parent op is not an llvm.func")))?;
+        llvm_func.get_symbol_name(ctx).to_string()
+    };
+
+    let global_name = get_or_create_extern_shared_global(
+        ctx,
+        op,
+        &func_name,
+        shared_globals,
+        dynamic_smem_alignments,
+        alignment,
+    )?;
+
+    let address_of_op = llvm::AddressOfOp::new(ctx, global_name, 3);
+    rewriter.insert_operation(ctx, address_of_op.get_operation());
+
+    let base_ptr = address_of_op.get_operation().deref(ctx).get_result(0);
+
+    if byte_offset > 0 {
+        let i64_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+        let offset_attr = pliron::builtin::attributes::IntegerAttr::new(
+            i64_ty,
+            pliron::utils::apint::APInt::from_u64(
+                byte_offset,
+                std::num::NonZeroUsize::new(64).unwrap(),
+            ),
+        );
+        let offset_const = llvm::ConstantOp::new(ctx, offset_attr.into());
+        rewriter.insert_operation(ctx, offset_const.get_operation());
+        let offset_value = offset_const.get_operation().deref(ctx).get_result(0);
+
+        let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
+        let gep_op = llvm::GetElementPtrOp::new(
+            ctx,
+            base_ptr,
+            vec![llvm_export::ops::GepIndex::Value(offset_value)],
+            i8_ty.into(),
+        );
+        rewriter.insert_operation(ctx, gep_op.get_operation());
+        rewriter.replace_operation(ctx, op, gep_op.get_operation());
+    } else {
+        rewriter.replace_operation(ctx, op, address_of_op.get_operation());
+    }
+
+    Ok(())
+}
+
+/// Get or create the extern shared memory global for an owning function.
+///
+/// Creates an LLVM global variable with:
+/// - Zero-length array type: `[0 x i8]`
+/// - External linkage (no initializer)
+/// - Address space 3 (shared memory)
+/// - Pre-computed body and calling-kernel contract alignment
+///
+/// Each owning function gets its own dynamic shared memory symbol. Uses
+/// `shared_globals` for deduplication (only one global per function).
+fn get_or_create_extern_shared_global(
+    ctx: &mut Context,
+    op: Ptr<Operation>,
+    func_name: &str,
+    shared_globals: &mut SharedGlobalsMap,
+    dynamic_smem_alignments: &mut DynamicSmemAlignmentMap,
+    _requested_alignment: u64,
+) -> Result<pliron::identifier::Identifier> {
+    let (symbol_name, max_alignment) = dynamic_smem_alignments.get(func_name).cloned().ok_or_else(
+        || {
+            anyhow_to_pliron(anyhow::anyhow!(
+                "Internal error: dynamic shared memory alignment not pre-computed for function '{}'. \
+                 This should have been done in compute_max_dynamic_smem_alignment.",
+                func_name
+            ))
+        },
+    )?;
+
+    let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
+    let declaration = SharedGlobalDeclaration {
+        kind: SharedGlobalKind::DynamicExtern,
+        mir_elem_type: i8_ty.into(),
+        size: 0,
+        alignment: max_alignment,
+        // The dynamic pool is per-launch storage with no originating static;
+        // it never carries a source-level debug identity.
+        debug_info: None,
+        debug_owner_function: None,
+    };
+    let global_created_key = format!("__dynamic_smem_global_created_{}", func_name);
+    if let Some(existing) = shared_globals.get(&global_created_key) {
+        if existing.declaration != declaration || existing.symbol != symbol_name {
+            return Err(anyhow_to_pliron(anyhow::anyhow!(
+                "dynamic shared-memory key {:?} has an incompatible declaration",
+                global_created_key
+            )));
+        }
+        return Ok(existing.symbol.clone());
+    }
+
+    let array_type = ArrayType::get(ctx, i8_ty.into(), 0);
+
+    let global_op = llvm::GlobalOp::new_with_alignment(
+        ctx,
+        symbol_name.clone(),
+        array_type.into(),
+        max_alignment,
+    );
+    global_op.set_address_space(ctx, llvm_export::types::address_space::SHARED);
+
+    {
+        use llvm_export::attributes::LinkageAttr;
+        global_op.set_attr_llvm_global_linkage(ctx, LinkageAttr::ExternalLinkage);
+    }
+
+    let parent_block = op
+        .deref(ctx)
+        .get_parent_block()
+        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Op has no parent block")))?;
+    let module_op = helpers::get_module_from_block(ctx, parent_block).map_err(anyhow_to_pliron)?;
+    let region = module_op.deref(ctx).get_region(0);
+    let module_block = region
+        .deref(ctx)
+        .iter(ctx)
+        .next()
+        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Module is empty")))?;
+
+    global_op.get_operation().insert_at_front(module_block, ctx);
+
+    shared_globals.insert(
+        global_created_key,
+        SharedGlobalRecord {
+            symbol: symbol_name.clone(),
+            declaration,
+        },
+    );
+
+    Ok(symbol_name)
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/mod.rs b/crates/mir-lower/src/convert/ops/memory/mod.rs
new file mode 100644
index 0000000000..99f085cce3
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/mod.rs
@@ -0,0 +1,69 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Memory operation conversion: `dialect-mir` → LLVM dialect.
+//!
+//! Converts `dialect-mir` memory operations to their LLVM dialect equivalents.
+//!
+//! # Operations
+//!
+//! | MIR Operation        | LLVM Operation(s)                 | Description                  |
+//! |----------------------|-----------------------------------|------------------------------|
+//! | `mir.load`           | `llvm.load`                       | Load from pointer            |
+//! | `mir.store`          | `llvm.store`                      | Store to pointer             |
+//! | `mir.ref`            | `llvm.alloca` + `llvm.store`      | Materialize aggregate in mem |
+//! | `mir.ptr_offset`     | `llvm.getelementptr`              | Pointer arithmetic           |
+//! | `mir.shared_alloc`   | `llvm.global` + `llvm.addressof`  | Static shared memory         |
+//! | `mir.extern_shared`  | `llvm.global` + `llvm.addressof`  | Dynamic shared memory        |
+//!
+//! # Shared Memory
+//!
+//! ## Static Shared Memory (`SharedArray<T, N, ALIGN>`)
+//!
+//! Each static shared memory allocation gets a unique global symbol (`__shared_mem_N`).
+//! Multiple allocations in the same or different kernels each have their own symbol
+//! with their own size and alignment.
+//!
+//! ## Dynamic Shared Memory (`DynamicSharedArray<T, ALIGN>`)
+//!
+//! Dynamic shared memory uses a symbol for each function that owns an access
+//! (`__dynamic_smem_{function_name}`).
+//! Key characteristics:
+//!
+//! - **Per-owner symbols**: Each function containing an access gets an extern symbol
+//! - **Pre-computed alignment**: A pre-pass combines the owner's body alignment with
+//!   the strongest launch-contract marker that can reach it
+//! - **Single runtime pool per launch**: The symbols refer to dynamic shared memory
+//!   sized by `shared_mem_bytes` at launch
+//!
+//! ### PTX Output Example
+//!
+//! ```ptx
+//! ; Kernel with 128-byte aligned dynamic shared memory
+//! .extern .shared .align 128 .b8 __dynamic_smem_my_kernel[];
+//!
+//! ; Another kernel with 16-byte aligned (default)
+//! .extern .shared .align 16 .b8 __dynamic_smem_other_kernel[];
+//! ```
+
+mod access;
+mod common;
+mod debug;
+mod device_global;
+mod extern_shared;
+mod shared;
+mod transfer;
+
+pub(crate) use access::{
+    convert_alloca, convert_load, convert_ptr_offset, convert_ref, convert_store,
+};
+pub(crate) use debug::{convert_dbg_value, convert_dbg_value_list};
+pub use device_global::convert_global_alloc_dc;
+pub use extern_shared::convert_extern_shared_dc;
+pub use shared::convert_shared_alloc_dc;
+pub(crate) use transfer::{convert_memcpy, convert_memmove};
+
+#[cfg(test)]
+mod tests;
diff --git a/crates/mir-lower/src/convert/ops/memory/shared.rs b/crates/mir-lower/src/convert/ops/memory/shared.rs
new file mode 100644
index 0000000000..05d63840da
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/shared.rs
@@ -0,0 +1,342 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Conversion of `mir.shared_alloc` to static shared-memory globals.
+
+use super::common::anyhow_to_pliron;
+use crate::context::{
+    SharedGlobalDeclaration, SharedGlobalKind, SharedGlobalRecord, SharedGlobalsMap,
+};
+use crate::convert::types::{convert_type, llvm_type_size_align};
+use crate::helpers;
+use llvm_export::ops as llvm;
+use llvm_export::ops::GlobalOpExt;
+use llvm_export::types::ArrayType;
+use pliron::builtin::op_interfaces::SymbolOpInterface;
+use pliron::context::{Context, Ptr};
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+use pliron::r#type::{TypeHandle, Typed};
+
+/// Convert `mir.shared_alloc` to LLVM global variable in shared address space.
+///
+/// GPU shared memory is represented as a global variable with address space 3.
+/// Uses `shared_globals` to deduplicate: multiple allocations with the same
+/// `alloc_key` share the same global.
+///
+/// Called directly from `MirToLlvmConversionDriver::rewrite` (not through
+/// op_cast dispatch) because it needs the cross-function `SharedGlobalsMap`.
+pub fn convert_shared_alloc_dc(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+    shared_globals: &mut SharedGlobalsMap,
+    next_shared_mem_index: &mut usize,
+) -> Result<()> {
+    use pliron::builtin::attributes::{IntegerAttr, TypeAttr};
+
+    let (alloc_key, source_name, mir_elem_type, size, alignment, debug_info, debug_owner_function) = {
+        let shared_alloc_op = dialect_mir::ops::MirSharedAllocOp::new(op);
+        let op_ref = op.deref(ctx);
+
+        let alloc_key: Option<String> = shared_alloc_op
+            .get_attr_alloc_key(ctx)
+            .map(|s| String::from((*s).clone()));
+
+        // Optional and diagnostic: the Rust path of the originating `static`,
+        // carried through so the emitted global can name its source.
+        let source_name: Option<String> = shared_alloc_op
+            .get_attr_source_name(ctx)
+            .map(|s| String::from((*s).clone()));
+
+        let elem_type_attr = op_ref
+            .attributes
+            .get::<TypeAttr>(&"elem_type".try_into().unwrap())
+            .ok_or_else(|| {
+                anyhow_to_pliron(anyhow::anyhow!(
+                    "MirSharedAllocOp missing elem_type TypeAttr attribute"
+                ))
+            })?;
+        let mir_elem_type = elem_type_attr.get_type(ctx);
+
+        let size_attr = op_ref
+            .attributes
+            .get::<IntegerAttr>(&"size".try_into().unwrap())
+            .ok_or_else(|| {
+                anyhow_to_pliron(anyhow::anyhow!(
+                    "MirSharedAllocOp missing size IntegerAttr attribute"
+                ))
+            })?;
+        let size = size_attr.value().to_u64();
+
+        let alignment = shared_alloc_op.get_alignment_value(ctx).unwrap_or(0);
+        let debug_info = llvm::debug_global_variable(ctx, op);
+        let debug_owner_function = llvm::debug_global_owner_function(ctx, op);
+
+        (
+            alloc_key,
+            source_name,
+            mir_elem_type,
+            size,
+            alignment,
+            debug_info,
+            debug_owner_function,
+        )
+    };
+
+    // A shared variable DIE must describe the physical allocation. Gate the
+    // optional debug identity against the lowered element layout before it
+    // can reach the declaration record or the emitted global.
+    let llvm_elem_type = convert_type(ctx, mir_elem_type).map_err(anyhow_to_pliron)?;
+    let debug_info = debug_info
+        .filter(|info| shared_debug_type_matches_physical(ctx, info, llvm_elem_type, size));
+    let debug_owner_function = debug_info.as_ref().and(debug_owner_function);
+
+    let declaration = SharedGlobalDeclaration {
+        kind: SharedGlobalKind::Static,
+        mir_elem_type,
+        size,
+        alignment,
+        debug_info,
+        debug_owner_function,
+    };
+
+    // A key names one physical allocation, not merely a preferred symbol.
+    // Reuse it only when the complete storage declaration agrees; otherwise
+    // the later address would silently inherit the first allocation's type,
+    // extent, or alignment.
+    let global_name = if let Some(key) = alloc_key.as_ref()
+        && let Some(existing) = shared_globals.get(key)
+    {
+        if !existing.declaration.same_storage(&declaration) {
+            return Err(anyhow_to_pliron(anyhow::anyhow!(
+                "duplicate shared alloc_key {:?} has an incompatible declaration",
+                key
+            )));
+        }
+        let symbol = existing.symbol.clone();
+        let debug_identity_matches = existing.declaration.debug_info == declaration.debug_info
+            && existing.declaration.debug_owner_function == declaration.debug_owner_function;
+        if !debug_identity_matches {
+            // One physical allocation reached under two debug identities, for
+            // example a function-local static whose owning function was
+            // materialized (or inlined) into two kernels. Debug metadata must
+            // never fail a build that a release build accepts, and DWARF
+            // cannot truthfully scope one AS3 object to two subprograms, so
+            // fail open: drop the attachment from the materialized global and
+            // demote the cached record to metadata-free.
+            strip_shared_debug_identity(ctx, op, &symbol)?;
+            if let Some(record) = shared_globals.get_mut(key) {
+                record.declaration.debug_info = None;
+                record.declaration.debug_owner_function = None;
+            }
+        }
+        symbol
+    } else {
+        create_shared_global(
+            ctx,
+            op,
+            shared_globals,
+            next_shared_mem_index,
+            SharedAllocSpec {
+                mir_elem_type,
+                size,
+                alignment,
+                alloc_key,
+                source_name: source_name.as_deref(),
+                debug_info: declaration.debug_info.as_ref(),
+                debug_owner_function: declaration.debug_owner_function.as_deref(),
+            },
+        )?
+    };
+
+    let address_of_op = llvm::AddressOfOp::new(ctx, global_name, 3);
+    rewriter.insert_operation(ctx, address_of_op.get_operation());
+    rewriter.replace_operation(ctx, op, address_of_op.get_operation());
+
+    Ok(())
+}
+
+/// Everything `create_shared_global` needs about one `mir.shared_alloc`.
+///
+/// Mirrors [`DeviceGlobalSpec`] for the shared-memory path.
+struct SharedAllocSpec<'a> {
+    mir_elem_type: TypeHandle,
+    size: u64,
+    alignment: u64,
+    alloc_key: Option<String>,
+    source_name: Option<&'a str>,
+    debug_info: Option<&'a llvm::DebugGlobalVariableInfo>,
+    debug_owner_function: Option<&'a str>,
+}
+
+/// Create a shared memory global variable in the module.
+///
+/// Creates an LLVM global variable with:
+/// - Array type: `[size x element_type]`
+/// - Address space 3 (shared memory)
+/// - Optional alignment
+/// - Unique generated name (`__shared_mem_N`)
+///
+/// The global is inserted at the front of the module block. When
+/// `spec.alloc_key` is `Some`, the key is moved into `shared_globals` so that
+/// later allocations with the same key reuse this global only after the caller
+/// has checked that their complete declarations agree.
+///
+/// `spec.source_name`, when present, is the Rust path of the `static` this
+/// allocation came from. The generated symbol stays anonymous; the name is
+/// recorded as an attribute on the global so the exporter can render it
+/// beside the definition. Only the allocation that *creates* the global
+/// contributes a name — a later allocation with the same `alloc_key` hits
+/// the cache and never reaches this function — which is consistent because
+/// the key and the name are both derived from the same constant.
+///
+/// `next_shared_mem_index` is scoped to one `MirToLlvmConversionDriver`
+/// instance (one module), not a process-global counter: `N` is a function of
+/// this module's own MIR walk order, not of how many other modules have
+/// lowered a shared allocation earlier in the process (#706).
+fn create_shared_global(
+    ctx: &mut Context,
+    op: Ptr<Operation>,
+    shared_globals: &mut SharedGlobalsMap,
+    next_shared_mem_index: &mut usize,
+    spec: SharedAllocSpec<'_>,
+) -> Result<pliron::identifier::Identifier> {
+    let llvm_elem_type = convert_type(ctx, spec.mir_elem_type).map_err(anyhow_to_pliron)?;
+    let array_type = ArrayType::get(ctx, llvm_elem_type, spec.size);
+
+    let counter = *next_shared_mem_index;
+    *next_shared_mem_index += 1;
+    let name: pliron::identifier::Identifier =
+        format!("__shared_mem_{counter}").try_into().unwrap();
+
+    let global_op = if spec.alignment > 0 {
+        llvm::GlobalOp::new_with_alignment(ctx, name.clone(), array_type.into(), spec.alignment)
+    } else {
+        llvm::GlobalOp::new(ctx, name.clone(), array_type.into())
+    };
+    global_op.set_address_space(ctx, llvm_export::types::address_space::SHARED);
+    if let Some(source_name) = spec.source_name {
+        use llvm_export::ops::GlobalOpExt;
+        global_op.set_shared_source_name(ctx, source_name);
+    }
+    if let Some(info) = spec.debug_info {
+        llvm::set_debug_global_variable(ctx, global_op.get_operation(), info);
+    }
+    if let Some(owner) = spec.debug_owner_function {
+        llvm::set_debug_global_owner_function(ctx, global_op.get_operation(), owner);
+    }
+
+    let parent_block = op
+        .deref(ctx)
+        .get_parent_block()
+        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Op has no parent block")))?;
+    let module_op = helpers::get_module_from_block(ctx, parent_block).map_err(anyhow_to_pliron)?;
+    let region = module_op.deref(ctx).get_region(0);
+    let module_block = region
+        .deref(ctx)
+        .iter(ctx)
+        .next()
+        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Module is empty")))?;
+
+    global_op.get_operation().insert_at_front(module_block, ctx);
+
+    if let Some(key) = spec.alloc_key {
+        shared_globals.insert(
+            key,
+            SharedGlobalRecord {
+                symbol: name.clone(),
+                declaration: SharedGlobalDeclaration {
+                    kind: SharedGlobalKind::Static,
+                    mir_elem_type: spec.mir_elem_type,
+                    size: spec.size,
+                    alignment: spec.alignment,
+                    debug_info: spec.debug_info.cloned(),
+                    debug_owner_function: spec.debug_owner_function.map(str::to_owned),
+                },
+            },
+        );
+    }
+
+    Ok(name)
+}
+
+/// A shared variable DIE must describe the compiler-materialized allocation,
+/// never the marker ZST or an element graph whose pointer base types are not
+/// representable yet. The frontend checks semantic element layout; this final
+/// boundary verifies total physical bits/count against the LLVM backing.
+fn shared_debug_type_matches_physical(
+    ctx: &Context,
+    info: &llvm::DebugGlobalVariableInfo,
+    llvm_elem_type: TypeHandle,
+    count: u64,
+) -> bool {
+    let Some((element_size, _)) = llvm_type_size_align(ctx, llvm_elem_type) else {
+        return false;
+    };
+    let Some(element_bytes) = element_size.checked_mul(count) else {
+        return false;
+    };
+    let Some(physical_bits) = element_bytes.checked_mul(8) else {
+        return false;
+    };
+    if info.ty.size_bits() != physical_bits {
+        return false;
+    }
+    match &info.ty {
+        llvm::DebugLocalTypeKind::Array {
+            element,
+            count: debug_count,
+            ..
+        } => *debug_count == count && element.size_bits() == element_size.saturating_mul(8),
+        // `Barrier` retains its semantic repr(C) struct while the backing is
+        // one i64. Other marker types are never admitted by the frontend.
+        llvm::DebugLocalTypeKind::Struct { .. } => count == 1,
+        _ => false,
+    }
+}
+
+/// Detach the debug identity from an already-materialized shared global.
+///
+/// The fail-open path for divergent debug identities on one `alloc_key`:
+/// the storage stays shared and valid, only the optional DWARF attachment is
+/// dropped so it cannot misattribute the allocation to the wrong static or
+/// owner function.
+fn strip_shared_debug_identity(
+    ctx: &mut Context,
+    op: Ptr<Operation>,
+    name: &pliron::identifier::Identifier,
+) -> Result<()> {
+    let parent_block = op
+        .deref(ctx)
+        .get_parent_block()
+        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Op has no parent block")))?;
+    let module_op = helpers::get_module_from_block(ctx, parent_block).map_err(anyhow_to_pliron)?;
+    let module_block = module_op
+        .deref(ctx)
+        .get_region(0)
+        .deref(ctx)
+        .iter(ctx)
+        .next()
+        .ok_or_else(|| anyhow_to_pliron(anyhow::anyhow!("Module is empty")))?;
+    let existing = module_block
+        .deref(ctx)
+        .iter(ctx)
+        .filter_map(|candidate| Operation::get_op::<llvm::GlobalOp>(candidate, ctx))
+        .find(|global| global.get_symbol_name(ctx) == *name)
+        .ok_or_else(|| {
+            anyhow_to_pliron(anyhow::anyhow!(
+                "shared allocation cache refers to missing LLVM global `@{name}`"
+            ))
+        })?;
+    llvm::clear_debug_global_identity(ctx, existing.get_operation());
+    Ok(())
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/tests/access.rs b/crates/mir-lower/src/convert/ops/memory/tests/access.rs
new file mode 100644
index 0000000000..954c1afc27
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/tests/access.rs
@@ -0,0 +1,473 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#![allow(clippy::disallowed_methods)]
+
+use super::*;
+
+#[test]
+fn convert_alloca_lowers_to_llvm_alloca() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+
+    let alloca_op = Operation::new(
+        &mut ctx,
+        mir::MirAllocaOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    alloca_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    assert_eq!(
+        count_ops::<llvm::AllocaOp>(&ctx, &body),
+        1,
+        "expected exactly one llvm.alloca"
+    );
+    let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).unwrap();
+    // Element type should round-trip through convert_type as i32.
+    let elem_ty = alloca.result_pointee_type(&ctx);
+    assert!(elem_ty.deref(&ctx).is::<IntegerType>());
+}
+
+#[test]
+fn convert_alloca_preserves_nested_array_element_alignment() {
+    let mut ctx = make_ctx();
+    let tuple_ty = over_aligned_tuple_ty(&mut ctx);
+    let inner: TypeHandle = MirArrayType::get(&mut ctx, tuple_ty, 2).into();
+    let outer: TypeHandle = MirArrayType::get(&mut ctx, inner, 3).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, outer, true);
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+
+    let alloca_op = Operation::new(
+        &mut ctx,
+        mir::MirAllocaOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    alloca_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).expect("expected llvm.alloca");
+    assert_eq!(
+        llvm_export::ops::op_alignment(&ctx, alloca.get_operation()),
+        Some(32)
+    );
+}
+
+#[test]
+fn convert_alloca_preserves_debug_local_metadata() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+
+    let alloca_op = Operation::new(
+        &mut ctx,
+        mir::MirAllocaOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    llvm::set_debug_local_variable(
+        &mut ctx,
+        alloca_op,
+        llvm::DebugLocalVariableInfo {
+            name: "x".to_string(),
+            argument_index: Some(1),
+            ty: llvm::DebugLocalTypeKind::Basic {
+                name: "i32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_signed",
+            },
+        },
+    );
+    alloca_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).unwrap();
+    let info = llvm::debug_local_variable(&ctx, alloca.get_operation())
+        .expect("debug local metadata should survive lowering");
+
+    assert_eq!(info.name, "x");
+    assert_eq!(info.argument_index, Some(1));
+    assert_eq!(
+        info.ty,
+        llvm::DebugLocalTypeKind::Basic {
+            name: "i32".to_string(),
+            size_bits: 32,
+            encoding: "DW_ATE_signed",
+        }
+    );
+}
+
+#[test]
+fn convert_store_lowers_to_llvm_store() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
+
+    // Kernel takes (ptr, val) so we can store one into the other.
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into(), i32_ty], vec![]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let val = block.deref(&ctx).get_argument(1);
+
+    let store_op = Operation::new(
+        &mut ctx,
+        mir::MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![ptr_val, val],
+        vec![],
+        0,
+    );
+    store_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    assert_eq!(
+        count_ops::<llvm::StoreOp>(&ctx, &body),
+        1,
+        "expected one llvm.store"
+    );
+    // The original mir.store must be gone.
+    assert_eq!(count_ops::<mir::MirStoreOp>(&ctx, &body), 0);
+
+    // convert_store swaps operand order: mir.store is [ptr, value] but
+    // llvm.store takes (value, ptr). Verify that mapping survived.
+    let store = find_first::<llvm::StoreOp>(&ctx, &body).unwrap();
+    let addr_ty = store.get_operand_address(&ctx).get_type(&ctx);
+    assert!(addr_ty.deref(&ctx).is::<PointerType>(), "operand 1 is ptr");
+}
+
+#[test]
+fn convert_store_preserves_volatile() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into(), i32_ty], vec![]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let val = block.deref(&ctx).get_argument(1);
+
+    let store_op = Operation::new(
+        &mut ctx,
+        mir::MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![ptr_val, val],
+        vec![],
+        0,
+    );
+    mir::MirStoreOp::new(store_op).set_volatile(&mut ctx, true);
+    store_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let store = find_first::<llvm::StoreOp>(&ctx, &body).unwrap();
+    assert!(
+        llvm_export::ops::op_volatile(&ctx, store.get_operation()),
+        "volatile mir.store must lower to a volatile llvm.store"
+    );
+}
+
+#[test]
+fn convert_load_lowers_to_llvm_load() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, false);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into()], vec![]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![i32_ty],
+        vec![ptr_val],
+        vec![],
+        0,
+    );
+    load_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    assert_eq!(count_ops::<llvm::LoadOp>(&ctx, &body), 1);
+    assert_eq!(count_ops::<mir::MirLoadOp>(&ctx, &body), 0);
+}
+
+#[test]
+fn convert_load_preserves_volatile() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, false);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into()], vec![]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![i32_ty],
+        vec![ptr_val],
+        vec![],
+        0,
+    );
+    mir::MirLoadOp::new(load_op).set_volatile(&mut ctx, true);
+    load_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let load = find_first::<llvm::LoadOp>(&ctx, &body).unwrap();
+    assert!(
+        llvm_export::ops::op_volatile(&ctx, load.get_operation()),
+        "volatile mir.load must lower to a volatile llvm.load"
+    );
+}
+
+#[test]
+fn convert_ref_lowers_to_alloca_then_store() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let mir_ptr_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, i32_ty, false, MirPointerKind::SharedRef);
+
+    // Take a u32 by value, build `&x`.
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![i32_ty], vec![]);
+    let arg = block.deref(&ctx).get_argument(0);
+
+    let ref_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirRefOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![arg],
+        vec![],
+        0,
+    );
+    let ref_op = mir::MirRefOp::new(ref_op_ptr);
+    ref_op.set_mutable(&mut ctx, false);
+    ref_op.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    ref_op_ptr.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    assert_eq!(
+        count_ops::<llvm::AllocaOp>(&ctx, &body),
+        1,
+        "ref must materialize via alloca"
+    );
+    assert_eq!(
+        count_ops::<llvm::StoreOp>(&ctx, &body),
+        1,
+        "ref must store the value into the alloca"
+    );
+    assert_eq!(count_ops::<mir::MirRefOp>(&ctx, &body), 0);
+}
+
+#[test]
+fn convert_ref_preserves_tuple_alignment_on_alloca_and_store() {
+    let mut ctx = make_ctx();
+    let tuple_ty = over_aligned_tuple_ty(&mut ctx);
+    let mir_ptr_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, tuple_ty, false, MirPointerKind::SharedRef);
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+
+    let undef = mir::MirUndefOp::new(&mut ctx, tuple_ty);
+    undef.get_operation().insert_at_back(block, &ctx);
+    let value = undef.get_operation().deref(&ctx).get_result(0);
+    let ref_op = Operation::new(
+        &mut ctx,
+        mir::MirRefOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![value],
+        vec![],
+        0,
+    );
+    let mir_ref = mir::MirRefOp::new(ref_op);
+    mir_ref.set_mutable(&mut ctx, false);
+    mir_ref.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    ref_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).expect("expected llvm.alloca");
+    let store = find_first::<llvm::StoreOp>(&ctx, &body).expect("expected llvm.store");
+    assert_eq!(
+        llvm_export::ops::op_alignment(&ctx, alloca.get_operation()),
+        Some(32)
+    );
+    assert_eq!(
+        llvm_export::ops::op_alignment(&ctx, store.get_operation()),
+        Some(32)
+    );
+}
+
+#[test]
+fn convert_ref_preserves_over_aligned_union_array_layout_and_alignment() {
+    for abi_align in [32, 64] {
+        let mut ctx = make_ctx();
+        let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+        let union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            format!("Align{abi_align}Union"),
+            vec!["word".into()],
+            vec![u32_ty],
+            abi_align,
+            abi_align,
+        )
+        .into();
+        let array_ty: TypeHandle = MirArrayType::get(&mut ctx, union_ty, 3).into();
+        let mir_ptr_ty =
+            MirPtrType::get_generic_with_kind(&mut ctx, array_ty, false, MirPointerKind::SharedRef);
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+
+        let undef = mir::MirUndefOp::new(&mut ctx, array_ty);
+        undef.get_operation().insert_at_back(block, &ctx);
+        let value = undef.get_operation().deref(&ctx).get_result(0);
+        let ref_op = Operation::new(
+            &mut ctx,
+            mir::MirRefOp::get_concrete_op_info(),
+            vec![mir_ptr_ty.into()],
+            vec![value],
+            vec![],
+            0,
+        );
+        let mir_ref = mir::MirRefOp::new(ref_op);
+        mir_ref.set_mutable(&mut ctx, false);
+        mir_ref.set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+        ref_op.insert_at_back(block, &ctx);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let body = kernel_blocks(&ctx, module_ptr);
+        let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).expect("expected llvm.alloca");
+        let store = find_first::<llvm::StoreOp>(&ctx, &body).expect("expected llvm.store");
+        let llvm_array_ty = alloca.result_pointee_type(&ctx);
+        let llvm_array_data = llvm_array_ty.deref(&ctx);
+        let llvm_array = llvm_array_data
+            .downcast_ref::<ArrayType>()
+            .expect("over-aligned union array must remain an LLVM array");
+
+        assert_eq!(llvm_array.size(), 3);
+        assert_eq!(
+            crate::convert::types::llvm_type_size_align(&ctx, llvm_array.elem_type()),
+            Some((abi_align, 16))
+        );
+        assert_eq!(
+            crate::convert::types::llvm_type_size_align(&ctx, llvm_array_ty),
+            Some((abi_align * 3, 16))
+        );
+        assert_eq!(
+            llvm_export::ops::op_alignment(&ctx, alloca.get_operation()),
+            Some(abi_align as u32)
+        );
+        assert_eq!(
+            llvm_export::ops::op_alignment(&ctx, store.get_operation()),
+            Some(abi_align as u32)
+        );
+    }
+}
+
+#[test]
+fn convert_ptr_offset_lowers_to_gep_with_pointee_elem_type() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into(), i64_ty], vec![]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let off_val = block.deref(&ctx).get_argument(1);
+
+    let off_op = Operation::new(
+        &mut ctx,
+        mir::MirPtrOffsetOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![ptr_val, off_val],
+        vec![],
+        0,
+    );
+    off_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let gep = find_first::<llvm::GetElementPtrOp>(&ctx, &body).expect("expected one llvm.gep");
+    // Element type must come from the MirPtrType pointee (i32), not the
+    // i8 fallback used when no operand-type info is available.
+    let elem_ty = gep.src_elem_type(&ctx);
+    let elem_ty_ref = elem_ty.deref(&ctx);
+    let int_ty = elem_ty_ref
+        .downcast_ref::<IntegerType>()
+        .expect("gep src_elem_type should be IntegerType");
+    assert_eq!(int_ty.width(), 32, "gep elem type must be i32 (pointee)");
+    assert!(
+        llvm::gep_inbounds(&ctx, gep.get_operation()),
+        "ordinary pointer offsets retain the in-bounds contract"
+    );
+}
+
+#[test]
+fn convert_wrapping_ptr_offset_lowers_to_non_inbounds_gep() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, false);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into(), i64_ty], vec![]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let off_val = block.deref(&ctx).get_argument(1);
+
+    let off_op = Operation::new(
+        &mut ctx,
+        mir::MirPtrOffsetOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![ptr_val, off_val],
+        vec![],
+        0,
+    );
+    mir::MirPtrOffsetOp::new(off_op).set_inbounds(&mut ctx, false);
+    off_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let gep = find_first::<llvm::GetElementPtrOp>(&ctx, &body).expect("expected one llvm.gep");
+    assert!(
+        !llvm::gep_inbounds(&ctx, gep.get_operation()),
+        "wrapping pointer offsets must not promise in-bounds arithmetic"
+    );
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/tests/alignment.rs b/crates/mir-lower/src/convert/ops/memory/tests/alignment.rs
new file mode 100644
index 0000000000..aae268bb08
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/tests/alignment.rs
@@ -0,0 +1,806 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#![allow(clippy::disallowed_methods)]
+
+use super::*;
+
+/// Lower `mir.load (mir.field_addr %p, field_index)` for a struct of
+/// signless integer fields with the given layout and report the alignment
+/// stamped on the resulting `llvm.load`. `None` means no stamp survived
+/// and the exporter's natural-alignment default applies.
+fn lowered_field_load_alignment(
+    field_bit_widths: Vec<u32>,
+    field_offsets: Vec<u64>,
+    total_size: u64,
+    abi_align: u64,
+    field_index: u32,
+) -> Option<u32> {
+    let mut ctx = make_ctx();
+    let field_types: Vec<TypeHandle> = field_bit_widths
+        .iter()
+        .map(|w| IntegerType::get(&ctx, *w, Signedness::Signless).into())
+        .collect();
+    let field_names = (0..field_types.len()).map(|i| format!("f{i}")).collect();
+    let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "FieldLoadAlign".into(),
+        field_names,
+        field_types.clone(),
+        vec![],
+        field_offsets,
+        total_size,
+        abi_align,
+    )
+    .into();
+    let struct_ptr_ty = MirPtrType::get_generic(&mut ctx, struct_ty, false);
+    let field_ty = field_types[field_index as usize];
+    let field_ptr_ty = MirPtrType::get_generic(&mut ctx, field_ty, false);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![struct_ptr_ty.into()], vec![]);
+    let struct_ptr_val = block.deref(&ctx).get_argument(0);
+
+    let field_addr_op =
+        mir::MirFieldAddrOp::build(&mut ctx, struct_ptr_val, field_ptr_ty.into(), field_index)
+            .expect("field_addr build");
+    field_addr_op.insert_at_back(block, &ctx);
+    let field_ptr_val = field_addr_op.deref(&ctx).get_result(0);
+
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![field_ty],
+        vec![field_ptr_val],
+        vec![],
+        0,
+    );
+    load_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected one llvm.load");
+    llvm_export::ops::op_alignment(&ctx, load.get_operation())
+}
+
+/// Field 0 of an over-aligned struct sits at the aggregate's own
+/// alignment, which the field's scalar result type cannot state on its
+/// own. This is what lets LoadStoreVectorizer fuse the adjacent pair.
+#[test]
+fn convert_load_inherits_overaligned_field_alignment_at_offset_zero() {
+    // #[repr(C, align(8))] struct { a: i32, b: i32 }
+    assert_eq!(
+        lowered_field_load_alignment(vec![32, 32], vec![0, 4], 8, 8, 0),
+        Some(8)
+    );
+}
+
+/// A field at a nonzero offset proves `gcd(abi_align, offset)`: an i32 at
+/// offset 8 of an align-16 struct proves 8, beating its natural 4.
+#[test]
+fn convert_load_narrows_field_alignment_to_gcd_of_align_and_offset() {
+    // #[repr(C, align(16))] struct { a: i64, b: i32 }
+    assert_eq!(
+        lowered_field_load_alignment(vec![64, 32], vec![0, 8], 16, 16, 1),
+        Some(8)
+    );
+}
+
+/// Whole-value loads of pointer-free packed structs use the packed LLVM
+/// representation, preserving rustc's byte size and field offsets.
+#[test]
+fn packed_struct_whole_value_load_uses_packed_layout() {
+    let mut ctx = make_ctx();
+    let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+    let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+    let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "Packed".into(),
+        vec!["tag".into(), "value".into()],
+        vec![u8_ty, u32_ty],
+        vec![0, 1],
+        vec![0, 1],
+        5,
+        1,
+    )
+    .into();
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, packed_ty, false);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty.into()], vec![]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![packed_ty],
+        vec![ptr_val],
+        vec![],
+        0,
+    );
+    load_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect("whole-value load of a pointer-free packed struct must lower");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected packed llvm.load");
+    let result_ty = load
+        .get_operation()
+        .deref(&ctx)
+        .get_result(0)
+        .get_type(&ctx);
+    let result_ty_ref = result_ty.deref(&ctx);
+    let struct_ty = result_ty_ref
+        .downcast_ref::<StructType>()
+        .expect("packed load result must be an LLVM struct");
+    assert_eq!(struct_ty.layout(), StructLayout::Packed);
+    assert_eq!(
+        crate::convert::types::llvm_type_size_align(&ctx, result_ty),
+        Some((5, 1))
+    );
+    assert_eq!(
+        llvm_export::ops::op_alignment(&ctx, load.get_operation()),
+        Some(1)
+    );
+}
+
+#[test]
+fn packed_struct_whole_value_load_with_shared_pointer_fails_closed() {
+    let mut ctx = make_ctx();
+    let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+    let pointee: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+    let shared_ty: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+    let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "PackedShared".into(),
+        vec!["tag".into(), "ptr".into()],
+        vec![u8_ty, shared_ty],
+        vec![0, 1],
+        vec![0, 1],
+        9,
+        1,
+    )
+    .into();
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, packed_ty, false);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty.into()], vec![]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![packed_ty],
+        vec![ptr_val],
+        vec![],
+        0,
+    );
+    load_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    let err = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect_err("packed whole-value load containing AS3 must remain fail-closed");
+    assert!(
+        format!("{err:?}").contains("target-mode dependent"),
+        "the refusal must identify the target-dependent packed AS3 image: {err:?}"
+    );
+}
+
+/// Whole-value stores use the same packed representation as construction
+/// and loads, while preserving the MIR aggregate's proved ABI alignment.
+#[test]
+fn packed_struct_whole_value_store_uses_packed_layout() {
+    let mut ctx = make_ctx();
+    let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+    let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+    let packed_ty: TypeHandle = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "Packed".into(),
+        vec!["tag".into(), "value".into()],
+        vec![u8_ty, u32_ty],
+        vec![0, 1],
+        vec![0, 1],
+        5,
+        1,
+    )
+    .into();
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, packed_ty, false);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty.into(), packed_ty], vec![]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let val = block.deref(&ctx).get_argument(1);
+
+    let store_op = Operation::new(
+        &mut ctx,
+        mir::MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![ptr_val, val],
+        vec![],
+        0,
+    );
+    store_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect("whole-value store of a pointer-free packed struct must lower");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let store = find_first::<llvm::StoreOp>(&ctx, &body).expect("expected packed llvm.store");
+    let value_ty = store
+        .get_operation()
+        .deref(&ctx)
+        .get_operand(0)
+        .get_type(&ctx);
+    let value_ty_ref = value_ty.deref(&ctx);
+    let struct_ty = value_ty_ref
+        .downcast_ref::<StructType>()
+        .expect("packed store value must be an LLVM struct");
+    assert_eq!(struct_ty.layout(), StructLayout::Packed);
+    assert_eq!(
+        crate::convert::types::llvm_type_size_align(&ctx, value_ty),
+        Some((5, 1))
+    );
+    assert_eq!(
+        llvm_export::ops::op_alignment(&ctx, store.get_operation()),
+        Some(1)
+    );
+}
+
+/// A naturally aligned inner struct sitting at a packed byte offset: the
+/// field address only proves align 1, and the load must claim that over
+/// the inner type's recorded abi alignment. Claiming the abi would stamp
+/// `align 4` on a 1-aligned address, which llc may honor with a wider
+/// access than the bytes allow.
+#[test]
+fn convert_load_claims_address_alignment_over_abi_at_packed_offsets() {
+    let mut ctx = make_ctx();
+    let u8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+    let u32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Unsigned).into();
+    let inner_ty: TypeHandle = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "Inner".into(),
+        vec!["v".into()],
+        vec![u32_ty],
+        vec![0],
+        vec![0],
+        4,
+        4,
+    )
+    .into();
+    let outer_ty: TypeHandle = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "PackedOuter".into(),
+        vec!["tag".into(), "inner".into()],
+        vec![u8_ty, inner_ty],
+        vec![0, 1],
+        vec![0, 1],
+        5,
+        1,
+    )
+    .into();
+    let outer_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, outer_ty, false).into();
+    let inner_ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, inner_ty, false).into();
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![outer_ptr_ty], vec![]);
+    let base = block.deref(&ctx).get_argument(0);
+
+    let field_addr_op =
+        mir::MirFieldAddrOp::build(&mut ctx, base, inner_ptr_ty, 1).expect("field_addr build");
+    field_addr_op.insert_at_back(block, &ctx);
+    let field_ptr_val = field_addr_op.deref(&ctx).get_result(0);
+
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![inner_ty],
+        vec![field_ptr_val],
+        vec![],
+        0,
+    );
+    load_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected one llvm.load");
+    assert_eq!(
+        llvm_export::ops::op_alignment(&ctx, load.get_operation()),
+        Some(1),
+        "the load must claim the address's proved alignment, not the inner abi"
+    );
+}
+
+/// A struct with no extra alignment proves nothing beyond the scalar's
+/// natural alignment: the stamp equals the exporter's default 4, so the
+/// emitted access is unchanged.
+#[test]
+fn convert_load_keeps_natural_alignment_without_overalignment() {
+    // struct { a: i32, b: i32 } with rustc's natural abi_align 4
+    assert_eq!(
+        lowered_field_load_alignment(vec![32, 32], vec![0, 4], 8, 4, 1),
+        Some(4)
+    );
+}
+
+/// dialect-mir only verifier-enforces power-of-two alignment for unions
+/// and enums. A malformed hand-built struct layout must decline the stamp
+/// rather than emit a non-power-of-two `align N` that llc rejects.
+#[test]
+fn convert_load_declines_non_power_of_two_field_alignment() {
+    assert_eq!(
+        lowered_field_load_alignment(vec![32], vec![0], 12, 12, 0),
+        None
+    );
+}
+
+/// Lower `mir.store %v, (mir.field_addr %p, field_index)` for a struct of
+/// signless integer fields with the given layout and report the alignment
+/// stamped on the resulting `llvm.store`. `None` means no stamp survived
+/// and the exporter's natural-alignment default applies.
+fn lowered_field_store_alignment(
+    field_bit_widths: Vec<u32>,
+    field_offsets: Vec<u64>,
+    total_size: u64,
+    abi_align: u64,
+    field_index: u32,
+) -> Option<u32> {
+    let mut ctx = make_ctx();
+    let field_types: Vec<TypeHandle> = field_bit_widths
+        .iter()
+        .map(|w| IntegerType::get(&ctx, *w, Signedness::Signless).into())
+        .collect();
+    let field_names = (0..field_types.len()).map(|i| format!("f{i}")).collect();
+    let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "FieldStoreAlign".into(),
+        field_names,
+        field_types.clone(),
+        vec![],
+        field_offsets,
+        total_size,
+        abi_align,
+    )
+    .into();
+    let struct_ptr_ty = MirPtrType::get_generic(&mut ctx, struct_ty, true);
+    let field_ty = field_types[field_index as usize];
+    let field_ptr_ty = MirPtrType::get_generic(&mut ctx, field_ty, true);
+
+    // The stored value arrives as a kernel argument of the field's own
+    // scalar type, so `value_abi_align` reports nothing about it and the
+    // address's stamp is the only alignment left -- the case this covers.
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![struct_ptr_ty.into(), field_ty], vec![]);
+    let struct_ptr_val = block.deref(&ctx).get_argument(0);
+    let val = block.deref(&ctx).get_argument(1);
+
+    let field_addr_op =
+        mir::MirFieldAddrOp::build(&mut ctx, struct_ptr_val, field_ptr_ty.into(), field_index)
+            .expect("field_addr build");
+    field_addr_op.insert_at_back(block, &ctx);
+    let field_ptr_val = field_addr_op.deref(&ctx).get_result(0);
+
+    let store_op = Operation::new(
+        &mut ctx,
+        mir::MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![field_ptr_val, val],
+        vec![],
+        0,
+    );
+    store_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let store = find_first::<llvm::StoreOp>(&ctx, &body).expect("expected one llvm.store");
+    llvm_export::ops::op_alignment(&ctx, store.get_operation())
+}
+
+/// Field 0 of an over-aligned struct sits at the aggregate's own alignment,
+/// which the stored scalar's type cannot state. This is what lets
+/// LoadStoreVectorizer fuse the adjacent pair into one wide store.
+#[test]
+fn convert_store_inherits_overaligned_field_alignment_at_offset_zero() {
+    // #[repr(C, align(8))] struct { a: i32, b: i32 }
+    assert_eq!(
+        lowered_field_store_alignment(vec![32, 32], vec![0, 4], 8, 8, 0),
+        Some(8)
+    );
+}
+
+/// A field at a nonzero offset proves `gcd(abi_align, offset)`: an i32 at
+/// offset 8 of an align-16 struct proves 8, beating its natural 4.
+#[test]
+fn convert_store_narrows_field_alignment_to_gcd_of_align_and_offset() {
+    // #[repr(C, align(16))] struct { a: i64, b: i32 }
+    assert_eq!(
+        lowered_field_store_alignment(vec![64, 32], vec![0, 8], 16, 16, 1),
+        Some(8)
+    );
+}
+
+/// A struct with no extra alignment proves nothing beyond the scalar's
+/// natural alignment, so the emitted store is unchanged. Widening here
+/// would claim an alignment the source never guaranteed.
+#[test]
+fn convert_store_keeps_natural_alignment_without_overalignment() {
+    // struct { a: i32, b: i32 } with rustc's natural abi_align 4
+    assert_eq!(
+        lowered_field_store_alignment(vec![32, 32], vec![0, 4], 8, 4, 1),
+        Some(4)
+    );
+}
+
+/// A malformed hand-built layout must decline the stamp rather than emit a
+/// non-power-of-two `align N` that llc rejects. Same guard the load path
+/// has, and it matters more here: an over-aligned store instruction on an
+/// under-aligned address is undefined, not merely slow.
+#[test]
+fn convert_store_declines_non_power_of_two_field_alignment() {
+    assert_eq!(
+        lowered_field_store_alignment(vec![32], vec![0], 12, 12, 0),
+        None
+    );
+}
+
+/// Lower `load (&arr[index])` where `arr` is the array field of an
+/// over-aligned struct, and report the alignment the load ends up with.
+///
+/// `index` of `Some(i)` builds a constant index, `None` a runtime one.
+fn lowered_element_load_alignment(
+    element_bits: u32,
+    element_count: u64,
+    struct_abi_align: u64,
+    index: Option<u64>,
+) -> Option<u32> {
+    use pliron::builtin::attributes::IntegerAttr;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = make_ctx();
+    let element_ty: TypeHandle = IntegerType::get(&ctx, element_bits, Signedness::Signless).into();
+    let array_ty: TypeHandle =
+        dialect_mir::types::MirArrayType::get(&mut ctx, element_ty, element_count).into();
+    let elem_bytes = u64::from(element_bits) / 8;
+    let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "ElementLoadAlign".into(),
+        vec!["lanes".into()],
+        vec![array_ty],
+        vec![],
+        vec![0],
+        elem_bytes * element_count,
+        struct_abi_align,
+    )
+    .into();
+    let struct_ptr_ty = MirPtrType::get_generic(&mut ctx, struct_ty, false);
+    let array_ptr_ty = MirPtrType::get_generic(&mut ctx, array_ty, false);
+    let element_ptr_ty = MirPtrType::get_generic(&mut ctx, element_ty, false);
+    let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![struct_ptr_ty.into(), i64_ty], vec![]);
+    let struct_ptr_val = block.deref(&ctx).get_argument(0);
+
+    // &s.lanes -- carries the struct's alignment onto the array address.
+    let field_addr_op =
+        mir::MirFieldAddrOp::build(&mut ctx, struct_ptr_val, array_ptr_ty.into(), 0)
+            .expect("field_addr build");
+    field_addr_op.insert_at_back(block, &ctx);
+    let array_ptr_val = field_addr_op.deref(&ctx).get_result(0);
+
+    let index_val = match index {
+        Some(i) => {
+            let constant = Operation::new(
+                &mut ctx,
+                mir::MirConstantOp::get_concrete_op_info(),
+                vec![i64_ty],
+                vec![],
+                vec![],
+                0,
+            );
+            mir::MirConstantOp::new(constant).set_attr_value(
+                &ctx,
+                IntegerAttr::new(
+                    IntegerType::get(&ctx, 64, Signedness::Signed),
+                    APInt::from_u64(i, NonZeroUsize::new(64).unwrap()),
+                ),
+            );
+            constant.insert_at_back(block, &ctx);
+            constant.deref(&ctx).get_result(0)
+        }
+        None => block.deref(&ctx).get_argument(1),
+    };
+
+    let elem_addr_op = Operation::new(
+        &mut ctx,
+        mir::MirArrayElementAddrOp::get_concrete_op_info(),
+        vec![element_ptr_ty.into()],
+        vec![array_ptr_val, index_val],
+        vec![],
+        0,
+    );
+    elem_addr_op.insert_at_back(block, &ctx);
+    let elem_ptr_val = elem_addr_op.deref(&ctx).get_result(0);
+
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![element_ty],
+        vec![elem_ptr_val],
+        vec![],
+        0,
+    );
+    load_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected one llvm.load");
+    llvm_export::ops::op_alignment(&ctx, load.get_operation())
+}
+
+/// Element 0 inherits the whole alignment the base address proved, which is
+/// what lets the adjacent pair fuse into one wide load.
+#[test]
+fn convert_load_inherits_base_alignment_at_element_zero() {
+    // &(#[repr(C, align(8))] struct { lanes: [i32; 2] }).lanes[0]
+    assert_eq!(lowered_element_load_alignment(32, 2, 8, Some(0)), Some(8));
+}
+
+/// A nonzero constant index proves `gcd(base, i * stride)`: element 1 of an
+/// align-8 `[i32; 2]` sits at byte 4, so it proves 4, not 8.
+#[test]
+fn convert_load_narrows_element_alignment_to_gcd_with_offset() {
+    assert_eq!(lowered_element_load_alignment(32, 2, 8, Some(1)), Some(4));
+}
+
+/// A runtime index can land on any element, so only what every stride
+/// preserves may be claimed -- `gcd(base, stride)`, never the base itself.
+#[test]
+fn convert_load_claims_only_stride_alignment_for_a_runtime_index() {
+    assert_eq!(lowered_element_load_alignment(32, 2, 8, None), Some(4));
+}
+
+/// A base with no extra alignment proves nothing beyond the element's own
+/// natural alignment, so the emitted access is unchanged.
+#[test]
+fn convert_load_keeps_natural_element_alignment_without_overalignment() {
+    assert_eq!(lowered_element_load_alignment(32, 2, 4, Some(0)), Some(4));
+}
+
+/// Like [`lowered_element_load_alignment`], but for an array whose element
+/// is an aggregate built by `element_ty_of` (which also reports the
+/// element's stored size in bytes). The claim on the element address must
+/// then come from the element's *exact* stride — rustc's stored size,
+/// padding included — not from any LLVM-level approximation.
+///
+/// With `load_first_scalar` the element must itself be an array and the
+/// access becomes `s.lanes[index][0]`, mirroring the nested-read chain
+/// where the outer stamp is inherited by the inner index-0 address and
+/// ends up on a scalar load that LoadStoreVectorizer trusts. Without it,
+/// the element itself is loaded.
+///
+/// Reports `(element address stamp, final load alignment)`.
+fn lowered_aggregate_element_alignments(
+    element_ty_of: impl FnOnce(&mut Context) -> (TypeHandle, u64),
+    element_count: u64,
+    struct_abi_align: u64,
+    index: Option<u64>,
+    load_first_scalar: bool,
+) -> (Option<u32>, Option<u32>) {
+    use pliron::builtin::attributes::IntegerAttr;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = make_ctx();
+    let (element_ty, elem_bytes) = element_ty_of(&mut ctx);
+    let inner_scalar_ty = load_first_scalar.then(|| {
+        let element_ref = element_ty.deref(&ctx);
+        element_ref
+            .downcast_ref::<MirArrayType>()
+            .expect("load_first_scalar needs an array element")
+            .element_type()
+    });
+    let array_ty: TypeHandle = MirArrayType::get(&mut ctx, element_ty, element_count).into();
+    let struct_ty: TypeHandle = MirStructType::get_with_full_layout(
+        &mut ctx,
+        "AggregateElementAlign".into(),
+        vec!["lanes".into()],
+        vec![array_ty],
+        vec![],
+        vec![0],
+        elem_bytes * element_count,
+        struct_abi_align,
+    )
+    .into();
+    let struct_ptr_ty = MirPtrType::get_generic(&mut ctx, struct_ty, false);
+    let array_ptr_ty = MirPtrType::get_generic(&mut ctx, array_ty, false);
+    let element_ptr_ty = MirPtrType::get_generic(&mut ctx, element_ty, false);
+    let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signed).into();
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![struct_ptr_ty.into(), i64_ty], vec![]);
+    let struct_ptr_val = block.deref(&ctx).get_argument(0);
+
+    // &s.lanes -- carries the struct's alignment onto the array address.
+    let field_addr_op =
+        mir::MirFieldAddrOp::build(&mut ctx, struct_ptr_val, array_ptr_ty.into(), 0)
+            .expect("field_addr build");
+    field_addr_op.insert_at_back(block, &ctx);
+    let array_ptr_val = field_addr_op.deref(&ctx).get_result(0);
+
+    let constant_index = |ctx: &mut Context, i: u64| {
+        let constant = Operation::new(
+            ctx,
+            mir::MirConstantOp::get_concrete_op_info(),
+            vec![i64_ty],
+            vec![],
+            vec![],
+            0,
+        );
+        mir::MirConstantOp::new(constant).set_attr_value(
+            ctx,
+            IntegerAttr::new(
+                IntegerType::get(ctx, 64, Signedness::Signed),
+                APInt::from_u64(i, NonZeroUsize::new(64).unwrap()),
+            ),
+        );
+        constant.insert_at_back(block, ctx);
+        constant.deref(ctx).get_result(0)
+    };
+
+    let index_val = match index {
+        Some(i) => constant_index(&mut ctx, i),
+        None => block.deref(&ctx).get_argument(1),
+    };
+
+    let elem_addr_op = Operation::new(
+        &mut ctx,
+        mir::MirArrayElementAddrOp::get_concrete_op_info(),
+        vec![element_ptr_ty.into()],
+        vec![array_ptr_val, index_val],
+        vec![],
+        0,
+    );
+    elem_addr_op.insert_at_back(block, &ctx);
+    let elem_ptr_val = elem_addr_op.deref(&ctx).get_result(0);
+
+    let (loaded_ty, loaded_ptr_val) = match inner_scalar_ty {
+        Some(scalar_ty) => {
+            let zero_val = constant_index(&mut ctx, 0);
+            let scalar_ptr_ty = MirPtrType::get_generic(&mut ctx, scalar_ty, false);
+            let inner_addr_op = Operation::new(
+                &mut ctx,
+                mir::MirArrayElementAddrOp::get_concrete_op_info(),
+                vec![scalar_ptr_ty.into()],
+                vec![elem_ptr_val, zero_val],
+                vec![],
+                0,
+            );
+            inner_addr_op.insert_at_back(block, &ctx);
+            (scalar_ty, inner_addr_op.deref(&ctx).get_result(0))
+        }
+        None => (element_ty, elem_ptr_val),
+    };
+
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![loaded_ty],
+        vec![loaded_ptr_val],
+        vec![],
+        0,
+    );
+    load_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    // GEP order follows source order: field address, then the element
+    // address under test (then the inner index-0 address when nested).
+    let geps = find_all::<llvm::GetElementPtrOp>(&ctx, &body);
+    assert_eq!(geps.len(), if load_first_scalar { 3 } else { 2 });
+    let element_gep_align = llvm_export::ops::address_alignment(&ctx, geps[1].get_operation());
+    let load = find_first::<llvm::LoadOp>(&ctx, &body).expect("expected one llvm.load");
+    let load_align = llvm_export::ops::op_alignment(&ctx, load.get_operation());
+    (element_gep_align, load_align)
+}
+
+/// `[f32; 3]` element under an align-8 base: stride is 12, so a runtime
+/// index proves `gcd(8, 12) = 4` — and the inner index-0 scalar read
+/// inherits exactly that. Guards against sizing the element through an
+/// LLVM-level approximation, whose guessed stride of 8 would stamp
+/// align 8 onto addresses that are only 4-aligned (a miscompile once
+/// LoadStoreVectorizer trusts it).
+#[test]
+fn convert_load_claims_exact_aggregate_stride_for_nested_array_elements() {
+    use pliron::builtin::types::FP32Type;
+    // &(#[repr(C, align(8))] struct { lanes: [[f32; 3]; 4] }).lanes[i][0]
+    let nested_f32x3 = |ctx: &mut Context| {
+        let f32_ty: TypeHandle = FP32Type::get(ctx).into();
+        (MirArrayType::get(ctx, f32_ty, 3).into(), 12)
+    };
+    assert_eq!(
+        lowered_aggregate_element_alignments(nested_f32x3, 4, 8, None, true),
+        (Some(4), Some(4))
+    );
+}
+
+/// A constant index into the same nested array uses the exact byte
+/// offset: element 1 sits at byte 12 (`gcd(8, 12) = 4`), element 2 at
+/// byte 24 (`gcd(8, 24) = 8`, the full base alignment again).
+#[test]
+fn convert_load_narrows_nested_element_alignment_by_exact_byte_offset() {
+    use pliron::builtin::types::FP32Type;
+    let nested_f32x3 = |ctx: &mut Context| {
+        let f32_ty: TypeHandle = FP32Type::get(ctx).into();
+        (MirArrayType::get(ctx, f32_ty, 3).into(), 12)
+    };
+    assert_eq!(
+        lowered_aggregate_element_alignments(nested_f32x3, 4, 8, Some(1), true),
+        (Some(4), Some(4))
+    );
+    assert_eq!(
+        lowered_aggregate_element_alignments(nested_f32x3, 4, 8, Some(2), true),
+        (Some(8), Some(8))
+    );
+}
+
+/// A tuple element's stride comes from rustc's recorded `total_size`
+/// (trailing padding included): `(f32, f32, f32)` stores 12 bytes, so an
+/// align-8 base proves only 4 on a runtime element address.
+#[test]
+fn convert_array_element_addr_takes_tuple_stride_from_recorded_layout() {
+    use pliron::builtin::types::FP32Type;
+    let f32x3_tuple = |ctx: &mut Context| {
+        let f32_ty: TypeHandle = FP32Type::get(ctx).into();
+        let tuple_ty: TypeHandle =
+            MirTupleType::get_with_layout(ctx, vec![f32_ty; 3], vec![], vec![0, 4, 8], 12, 4)
+                .into();
+        (tuple_ty, 12)
+    };
+    let (element_gep_align, _load_align) =
+        lowered_aggregate_element_alignments(f32x3_tuple, 4, 8, None, false);
+    assert_eq!(element_gep_align, Some(4));
+}
+
+/// `f16` arrives from the importer as `MirFP16Type`, not the converted
+/// LLVM `half`, and its stride is exactly 2: an align-8 base proves 2 on
+/// a runtime element address and `gcd(8, 4) = 4` at element 2. Guards
+/// the arm the importer actually exercises — the old sizing guessed 8
+/// for this type too, the same over-claim as the aggregate cases.
+#[test]
+fn convert_load_claims_exact_f16_element_stride() {
+    let f16_scalar = |ctx: &mut Context| {
+        let f16_ty: TypeHandle = dialect_mir::types::MirFP16Type::get(ctx).into();
+        (f16_ty, 2)
+    };
+    assert_eq!(
+        lowered_aggregate_element_alignments(f16_scalar, 4, 8, None, false),
+        (Some(2), Some(2))
+    );
+    assert_eq!(
+        lowered_aggregate_element_alignments(f16_scalar, 4, 8, Some(2), false),
+        (Some(4), Some(4))
+    );
+}
+
+/// An element whose stored size is unknown (a struct built without rustc
+/// layout) must not have its stride guessed: the element address claims
+/// nothing and the load keeps the previous, weaker-but-sound behaviour.
+#[test]
+fn convert_array_element_addr_declines_unknown_element_stride() {
+    use pliron::builtin::types::FP32Type;
+    let opaque_struct = |ctx: &mut Context| {
+        let f32_ty: TypeHandle = FP32Type::get(ctx).into();
+        let struct_ty: TypeHandle =
+            MirStructType::get(ctx, "OpaqueElement".into(), vec!["x".into()], vec![f32_ty]).into();
+        (struct_ty, 4)
+    };
+    assert_eq!(
+        lowered_aggregate_element_alignments(opaque_struct, 4, 8, None, false),
+        (None, None)
+    );
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/tests/debug_provenance.rs b/crates/mir-lower/src/convert/ops/memory/tests/debug_provenance.rs
new file mode 100644
index 0000000000..5b34793741
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/tests/debug_provenance.rs
@@ -0,0 +1,381 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#![allow(clippy::disallowed_methods)]
+
+use super::*;
+
+#[test]
+fn convert_dbg_value_lowers_to_llvm_dbg_value() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![i32_ty], vec![]);
+    let value = block.deref(&ctx).get_argument(0);
+
+    let dbg_op = mir::MirDbgValueOp::new(&mut ctx, value);
+    let dbg_loc = pliron::location::Location::Named {
+        name: "current value location".to_string(),
+        child_loc: Box::new(pliron::location::Location::Unknown),
+    };
+    dbg_op
+        .get_operation()
+        .deref_mut(&ctx)
+        .set_loc(dbg_loc.clone());
+    llvm::set_debug_local_variable(
+        &mut ctx,
+        dbg_op.get_operation(),
+        llvm::DebugLocalVariableInfo {
+            name: "x".to_string(),
+            argument_index: None,
+            ty: llvm::DebugLocalTypeKind::Basic {
+                name: "i32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_signed",
+            },
+        },
+    );
+    llvm::set_debug_local_source_scope(&mut ctx, dbg_op.get_operation(), 42);
+    llvm::set_debug_fragment_variables(
+        &mut ctx,
+        dbg_op.get_operation(),
+        &[llvm::DebugFragmentVariableInfo {
+            variable: llvm::DebugLocalVariableInfo {
+                name: "pair".to_string(),
+                argument_index: None,
+                ty: llvm::DebugLocalTypeKind::Array {
+                    name: "[u32; 2]".to_string(),
+                    size_bits: 64,
+                    element: Box::new(llvm::DebugLocalTypeKind::Basic {
+                        name: "u32".to_string(),
+                        size_bits: 32,
+                        encoding: "DW_ATE_unsigned",
+                    }),
+                    count: 2,
+                },
+            },
+            fragment: llvm::DebugFragment {
+                offset_bits: 32,
+                size_bits: 32,
+            },
+            source_scope: Some(42),
+            declaration: Some(llvm::DebugSourcePosition {
+                file: PathBuf::from("decl.rs"),
+                line: 7,
+                column: 3,
+            }),
+        }],
+    );
+    llvm::set_debug_local_declaration_location(
+        &mut ctx,
+        dbg_op.get_operation(),
+        PathBuf::from("decl.rs"),
+        7,
+        3,
+    );
+    dbg_op.get_operation().insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    assert_eq!(count_ops::<mir::MirDbgValueOp>(&ctx, &body), 0);
+    let dbg_value = find_first::<llvm::DebugValueOp>(&ctx, &body)
+        .expect("expected lowered llvm.dbg_value marker");
+    assert_eq!(
+        dbg_value.get_operation().deref(&ctx).loc(),
+        dbg_loc,
+        "dbg.value lowering should keep the current-value source location"
+    );
+    let info = llvm::debug_local_variable(&ctx, dbg_value.get_operation())
+        .expect("debug local metadata should survive dbg_value lowering");
+
+    assert_eq!(info.name, "x");
+    assert_eq!(
+        llvm::debug_local_source_scope(&ctx, dbg_value.get_operation()),
+        Some(42),
+        "dbg.value lowering should keep the MIR source-scope owner"
+    );
+    let (decl_file, decl_pos) =
+        llvm::debug_local_declaration_location(&ctx, dbg_value.get_operation())
+            .expect("declaration location should survive dbg_value lowering");
+    assert_eq!(decl_file, PathBuf::from("decl.rs"));
+    assert_eq!(decl_pos.line, 7);
+    assert_eq!(decl_pos.column, 3);
+    assert_eq!(
+        info.ty,
+        llvm::DebugLocalTypeKind::Basic {
+            name: "i32".to_string(),
+            size_bits: 32,
+            encoding: "DW_ATE_signed",
+        }
+    );
+    let fragments = llvm::debug_fragment_variables(&ctx, dbg_value.get_operation());
+    assert_eq!(fragments.len(), 1);
+    assert_eq!(fragments[0].fragment.offset_bits, 32);
+    assert_eq!(fragments[0].fragment.size_bits, 32);
+    assert_eq!(fragments[0].variable.name, "pair");
+}
+
+#[test]
+fn convert_dbg_value_list_preserves_operands_and_expression() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, false);
+    let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![ptr_ty.into(), i64_ty], vec![]);
+    let base = block.deref(&ctx).get_argument(0);
+    let index = block.deref(&ctx).get_argument(1);
+
+    let dbg_op = mir::MirDbgValueListOp::new(&mut ctx, vec![base, index]);
+    llvm::set_debug_local_variable(
+        &mut ctx,
+        dbg_op.get_operation(),
+        llvm::DebugLocalVariableInfo {
+            name: "item".to_string(),
+            argument_index: None,
+            ty: llvm::DebugLocalTypeKind::Basic {
+                name: "u32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_unsigned",
+            },
+        },
+    );
+    let expression = llvm::DebugValueExpression::new(vec![
+        llvm::DebugValueExpressionOp::Arg(0),
+        llvm::DebugValueExpressionOp::Arg(1),
+        llvm::DebugValueExpressionOp::ConstU(4),
+        llvm::DebugValueExpressionOp::Mul,
+        llvm::DebugValueExpressionOp::Plus,
+        llvm::DebugValueExpressionOp::Deref,
+    ]);
+    llvm::set_debug_value_expression(&mut ctx, dbg_op.get_operation(), &expression);
+    dbg_op.get_operation().insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    assert_eq!(count_ops::<mir::MirDbgValueListOp>(&ctx, &body), 0);
+    let dbg_value = find_first::<llvm::DebugValueListOp>(&ctx, &body)
+        .expect("expected lowered llvm.dbg_value_list marker");
+    assert_eq!(dbg_value.values(&ctx), vec![base, index]);
+    assert_eq!(
+        llvm::debug_value_expression(&ctx, dbg_value.get_operation()),
+        Some(expression)
+    );
+}
+
+#[test]
+fn convert_alloca_preserves_local_memory_provenance() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+
+    let alloca_op = Operation::new(
+        &mut ctx,
+        mir::MirAllocaOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let provenance = llvm_export::ops::LocalMemoryProvenanceAttr {
+        local_index: 3,
+        size_bytes: 16,
+        binding_name: "scratch".into(),
+        type_name: "[u32; 4]".into(),
+    };
+    llvm_export::ops::set_local_memory_provenance(&mut ctx, alloca_op, provenance.clone());
+    alloca_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let alloca = find_first::<llvm::AllocaOp>(&ctx, &body).unwrap();
+    let copied = llvm_export::ops::local_memory_provenance(&ctx, alloca.get_operation()).unwrap();
+    assert_eq!(copied, provenance);
+}
+
+#[test]
+fn mem2reg_salvages_tagged_alloca_into_mir_dbg_value() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![i32_ty], vec![i32_ty]);
+    let arg = block.deref(&ctx).get_argument(0);
+
+    let alloca_op = Operation::new(
+        &mut ctx,
+        mir::MirAllocaOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let decl_loc = src_location(&mut ctx, "kernel.rs", 12, 9);
+    alloca_op.deref_mut(&ctx).set_loc(decl_loc.clone());
+    llvm::set_debug_local_variable(
+        &mut ctx,
+        alloca_op,
+        llvm::DebugLocalVariableInfo {
+            name: "x".to_string(),
+            argument_index: Some(1),
+            ty: llvm::DebugLocalTypeKind::Basic {
+                name: "i32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_signed",
+            },
+        },
+    );
+    llvm::set_debug_local_source_scope(&mut ctx, alloca_op, 9);
+    alloca_op.insert_at_back(block, &ctx);
+    let slot = alloca_op.deref(&ctx).get_result(0);
+
+    let store_op = Operation::new(
+        &mut ctx,
+        mir::MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![slot, arg],
+        vec![],
+        0,
+    );
+    store_op.insert_at_back(block, &ctx);
+
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![i32_ty],
+        vec![slot],
+        vec![],
+        0,
+    );
+    load_op.insert_at_back(block, &ctx);
+    let loaded = load_op.deref(&ctx).get_result(0);
+    append_mir_return(&mut ctx, block, vec![loaded]);
+
+    let mut analyses = pliron::pass::AnalysisManager::default();
+    pliron::opts::mem2reg::mem2reg(module_ptr, &mut ctx, &mut analyses)
+        .expect("mem2reg should promote the local slot");
+
+    let blocks = vec![block];
+    assert_eq!(count_ops::<mir::MirAllocaOp>(&ctx, &blocks), 0);
+    assert_eq!(count_ops::<mir::MirStoreOp>(&ctx, &blocks), 0);
+    assert_eq!(count_ops::<mir::MirLoadOp>(&ctx, &blocks), 0);
+
+    let dbg_values = find_all::<mir::MirDbgValueOp>(&ctx, &blocks);
+    assert!(
+        !dbg_values.is_empty(),
+        "mem2reg should leave value-based debug records for promoted locals"
+    );
+    let info = llvm::debug_local_variable(&ctx, dbg_values[0].get_operation())
+        .expect("mir.dbg_value should carry the promoted local metadata");
+    assert_eq!(info.name, "x");
+    assert_eq!(info.argument_index, Some(1));
+    assert_eq!(
+        llvm::debug_local_source_scope(&ctx, dbg_values[0].get_operation()),
+        Some(9),
+        "mem2reg salvage should keep the local's MIR source-scope owner"
+    );
+    assert_eq!(
+        dbg_values[0].get_operation().deref(&ctx).loc(),
+        decl_loc,
+        "debug records for source-less promoted ops should fall back to the local declaration"
+    );
+}
+
+#[test]
+fn mem2reg_salvages_fragment_only_alloca_into_mir_dbg_value() {
+    let mut ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty, true);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![i32_ty], vec![i32_ty]);
+    let arg = block.deref(&ctx).get_argument(0);
+
+    let alloca_op = Operation::new(
+        &mut ctx,
+        mir::MirAllocaOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let alloca_loc = src_location(&mut ctx, "kernel.rs", 20, 9);
+    alloca_op.deref_mut(&ctx).set_loc(alloca_loc);
+    llvm::set_debug_fragment_variables(
+        &mut ctx,
+        alloca_op,
+        &[llvm::DebugFragmentVariableInfo {
+            variable: llvm::DebugLocalVariableInfo {
+                name: "pair".to_string(),
+                argument_index: None,
+                ty: llvm::DebugLocalTypeKind::Array {
+                    name: "[u32; 2]".to_string(),
+                    size_bits: 64,
+                    element: Box::new(llvm::DebugLocalTypeKind::Basic {
+                        name: "u32".to_string(),
+                        size_bits: 32,
+                        encoding: "DW_ATE_unsigned",
+                    }),
+                    count: 2,
+                },
+            },
+            fragment: llvm::DebugFragment {
+                offset_bits: 32,
+                size_bits: 32,
+            },
+            source_scope: Some(9),
+            declaration: Some(llvm::DebugSourcePosition {
+                file: PathBuf::from("kernel.rs"),
+                line: 20,
+                column: 9,
+            }),
+        }],
+    );
+    alloca_op.insert_at_back(block, &ctx);
+    let slot = alloca_op.deref(&ctx).get_result(0);
+
+    let store_op = Operation::new(
+        &mut ctx,
+        mir::MirStoreOp::get_concrete_op_info(),
+        vec![],
+        vec![slot, arg],
+        vec![],
+        0,
+    );
+    store_op.insert_at_back(block, &ctx);
+
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![i32_ty],
+        vec![slot],
+        vec![],
+        0,
+    );
+    load_op.insert_at_back(block, &ctx);
+    let loaded = load_op.deref(&ctx).get_result(0);
+    append_mir_return(&mut ctx, block, vec![loaded]);
+
+    let mut analyses = pliron::pass::AnalysisManager::default();
+    pliron::opts::mem2reg::mem2reg(module_ptr, &mut ctx, &mut analyses)
+        .expect("mem2reg should promote fragment storage");
+
+    let dbg_values = find_all::<mir::MirDbgValueOp>(&ctx, &[block]);
+    assert!(
+        !dbg_values.is_empty(),
+        "fragment-only storage should still produce mir.dbg_value salvage"
+    );
+    let fragments = llvm::debug_fragment_variables(&ctx, dbg_values[0].get_operation());
+    assert_eq!(fragments.len(), 1);
+    assert_eq!(fragments[0].variable.name, "pair");
+    assert_eq!(fragments[0].fragment.offset_bits, 32);
+    assert_eq!(fragments[0].fragment.size_bits, 32);
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/tests/device_global.rs b/crates/mir-lower/src/convert/ops/memory/tests/device_global.rs
new file mode 100644
index 0000000000..0d1a236fc6
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/tests/device_global.rs
@@ -0,0 +1,555 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#![allow(clippy::disallowed_methods)]
+
+use super::*;
+
+pub(super) fn append_global_alloc(
+    ctx: &mut Context,
+    block: Ptr<BasicBlock>,
+    global_key: &str,
+    constant: bool,
+) -> Ptr<Operation> {
+    let i32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Signless).into();
+    append_global_alloc_typed(ctx, block, global_key, constant, !constant, i32_ty)
+}
+
+fn append_global_alloc_typed(
+    ctx: &mut Context,
+    block: Ptr<BasicBlock>,
+    global_key: &str,
+    constant: bool,
+    is_mutable: bool,
+    global_ty: TypeHandle,
+) -> Ptr<Operation> {
+    let result_ty = if constant {
+        MirPtrType::get_constant(ctx, global_ty, is_mutable)
+    } else {
+        MirPtrType::get_global(ctx, global_ty, is_mutable)
+    };
+    let op = Operation::new(
+        ctx,
+        mir::MirGlobalAllocOp::get_concrete_op_info(),
+        vec![result_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let alloc = mir::MirGlobalAllocOp::new(op);
+    alloc.set_attr_global_type(ctx, TypeAttr::new(global_ty));
+    alloc.set_attr_global_key(ctx, StringAttr::new(global_key.to_string()));
+    op.insert_at_back(block, ctx);
+    op
+}
+
+#[test]
+fn convert_global_alloc_deduplicates_matching_storage_across_pointer_mutability() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    append_global_alloc_typed(&mut ctx, block, "same-global", false, false, i32_ty);
+    append_global_alloc_typed(&mut ctx, block, "same-global", false, true, i32_ty);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect("pointer-carrier mutability does not change physical global storage");
+
+    let top = module_top_block(&ctx, module_ptr);
+    let globals = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+        .filter(|global| global.source_global_key(&ctx).as_deref() == Some("same-global"))
+        .count();
+    assert_eq!(globals, 1);
+    assert_eq!(
+        count_ops::<llvm::AddressOfOp>(&ctx, &kernel_blocks(&ctx, module_ptr)),
+        2
+    );
+}
+
+#[test]
+fn convert_global_alloc_rejects_conflicting_key_declarations() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let byte_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
+    let word_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let empty_words: TypeHandle = MirArrayType::get(&mut ctx, word_ty, 0).into();
+
+    let byte =
+        append_global_alloc_typed(&mut ctx, block, "conflicting-global", false, false, byte_ty);
+    let byte = mir::MirGlobalAllocOp::new(byte);
+    byte.set_alignment_value(&mut ctx, 1);
+    byte.mark_immutable(&mut ctx);
+
+    let words = append_global_alloc_typed(
+        &mut ctx,
+        block,
+        "conflicting-global",
+        false,
+        false,
+        empty_words,
+    );
+    let words = mir::MirGlobalAllocOp::new(words);
+    words.set_alignment_value(&mut ctx, 4);
+    words.mark_immutable(&mut ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    let error = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect_err("one global_key must not name incompatible type/alignment storage");
+    assert!(
+        error.to_string().contains("incompatible declaration"),
+        "{error}"
+    );
+}
+
+#[test]
+fn device_global_declaration_identity_covers_every_storage_property() {
+    let ctx = make_ctx();
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
+    let base = DeviceGlobalDeclaration {
+        mir_type: i32_ty,
+        alignment: 4,
+        addr_space: llvm_addr::GLOBAL,
+        initializer_hex: Some("00000000".to_string()),
+        initializer_relocations: Some("reloc-a".to_string()),
+        debug_info: None,
+        immutable: true,
+    };
+
+    let mut changed = base.clone();
+    changed.mir_type = i64_ty;
+    assert!(base != changed);
+    changed = base.clone();
+    changed.alignment = 8;
+    assert!(base != changed);
+    changed = base.clone();
+    changed.addr_space = llvm_addr::CONSTANT;
+    assert!(base != changed);
+    changed = base.clone();
+    changed.initializer_hex = Some("01000000".to_string());
+    assert!(base != changed);
+    changed = base.clone();
+    changed.initializer_relocations = Some("reloc-b".to_string());
+    assert!(base != changed);
+    changed = base.clone();
+    changed.debug_info = Some(llvm::DebugGlobalVariableInfo {
+        name: "COUNTER".to_string(),
+        namespace: vec!["my_crate".to_string()],
+        ty: llvm::DebugLocalTypeKind::Basic {
+            name: "u32".to_string(),
+            size_bits: 32,
+            encoding: "DW_ATE_unsigned",
+        },
+        declaration: llvm::DebugSourcePosition {
+            file: PathBuf::from("/tmp/global.rs"),
+            line: 7,
+            column: 1,
+        },
+        is_local_to_unit: true,
+        is_function_local: false,
+    });
+    assert!(base != changed);
+    changed = base.clone();
+    changed.immutable = false;
+    assert!(base != changed);
+}
+
+#[test]
+fn convert_global_alloc_places_in_global_or_constant_addrspace() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    append_global_alloc(&mut ctx, block, "ordinary_static", false);
+    let constant_key = dialect_mir::ops::encode_rust_static_global_key("_ZN7my_mod3KEYE");
+    append_global_alloc(&mut ctx, block, &constant_key, true);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let top = module_top_block(&ctx, module_ptr);
+    let globals: Vec<_> = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+        .collect();
+    let global_addr_global = globals
+        .iter()
+        .find(|g| g.address_space(&ctx) == llvm_addr::GLOBAL)
+        .expect("expected one global in addrspace(1)");
+    let global_addr_const = globals
+        .iter()
+        .find(|g| g.address_space(&ctx) == llvm_addr::CONSTANT)
+        .expect("expected one global in addrspace(4)");
+
+    // Constant-memory globals reuse the Rust mangled name so host code can
+    // resolve them by name via `cuModuleGetGlobal`; ordinary globals get
+    // a counter-suffixed `__device_global_N`.
+    assert_eq!(
+        global_addr_const.get_symbol_name(&ctx).to_string(),
+        "_ZN7my_mod3KEYE",
+        "constant globals must keep the raw rustc symbol payload as their name"
+    );
+    assert!(
+        global_addr_global
+            .get_symbol_name(&ctx)
+            .to_string()
+            .starts_with("__device_global_"),
+        "ordinary device globals get the __device_global_ prefix"
+    );
+}
+
+#[test]
+fn ordinary_global_debug_info_survives_lowering_but_constant_memory_stays_out_of_scope() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let ordinary = append_global_alloc(&mut ctx, block, "crate::GLOBAL_COUNTER", false);
+    let constant_key = dialect_mir::ops::encode_rust_static_global_key("_ZN5crate5COEFFE");
+    let constant = append_global_alloc(&mut ctx, block, &constant_key, true);
+    let info = llvm::DebugGlobalVariableInfo {
+        name: "GLOBAL_COUNTER".to_string(),
+        namespace: vec!["crate".to_string(), "state".to_string()],
+        ty: llvm::DebugLocalTypeKind::Basic {
+            name: "u32".to_string(),
+            size_bits: 32,
+            encoding: "DW_ATE_unsigned",
+        },
+        declaration: llvm::DebugSourcePosition {
+            file: PathBuf::from("/tmp/global.rs"),
+            line: 7,
+            column: 1,
+        },
+        is_local_to_unit: true,
+        is_function_local: false,
+    };
+    llvm::set_debug_global_variable(&mut ctx, ordinary, &info);
+    // Deliberately tag AS4 too: the AS1-only implementation must not
+    // accidentally expand its behavior merely because the generic debug
+    // carrier can be attached to any op.
+    llvm::set_debug_global_variable(&mut ctx, constant, &info);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let top = module_top_block(&ctx, module_ptr);
+    let globals: Vec<_> = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+        .collect();
+    let ordinary = globals
+        .iter()
+        .find(|global| global.address_space(&ctx) == llvm_addr::GLOBAL)
+        .expect("ordinary global");
+    let constant = globals
+        .iter()
+        .find(|global| global.address_space(&ctx) == llvm_addr::CONSTANT)
+        .expect("constant global");
+
+    assert_eq!(
+        llvm::debug_global_variable(&ctx, ordinary.get_operation()),
+        Some(info),
+        "source identity and semantic type must survive MIR-to-LLVM lowering"
+    );
+    assert!(
+        llvm::debug_global_variable(&ctx, constant.get_operation()).is_none(),
+        "AS4 debug metadata is a separate feature and must not leak into this AS1 change"
+    );
+}
+
+#[test]
+fn immutable_marking_survives_lowering_and_is_not_assumed() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+
+    // Two ordinary addrspace(1) globals, distinguished by their source key.
+    // Only the promoted one claims immutability; the plain static must not
+    // acquire it, or the exporter would write `constant` for storage the
+    // host can still overwrite by symbol.
+    let promoted = append_global_alloc(&mut ctx, block, "promoted_table", false);
+    mir::MirGlobalAllocOp::new(promoted).mark_immutable(&mut ctx);
+    append_global_alloc(&mut ctx, block, "plain_static", false);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let top = module_top_block(&ctx, module_ptr);
+    let globals: Vec<llvm::GlobalOp> = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+        .collect();
+    let by_key = |key: &str| -> llvm::GlobalOp {
+        *globals
+            .iter()
+            .find(|g| g.source_global_key(&ctx).as_deref() == Some(key))
+            .unwrap_or_else(|| panic!("no lowered global carries source key {key}"))
+    };
+
+    assert!(
+        by_key("promoted_table").is_immutable(&ctx),
+        "a global marked immutable in MIR must stay immutable through lowering"
+    );
+    assert!(
+        !by_key("plain_static").is_immutable(&ctx),
+        "lowering must not infer immutability; only the promoted-constant \
+             sites may claim it"
+    );
+}
+
+#[test]
+fn convert_global_alloc_rejects_conflicting_immutability() {
+    // A plain static and a promoted constant that end up sharing one key
+    // differ only in the immutable flag; that alone must fail closed
+    // instead of silently reusing the first allocation's storage.
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    append_global_alloc(&mut ctx, block, "collision", false);
+    let promoted = append_global_alloc(&mut ctx, block, "collision", false);
+    mir::MirGlobalAllocOp::new(promoted).mark_immutable(&mut ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    let error = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect_err("a shared string with different origins must fail closed");
+    assert!(
+        error.to_string().contains("incompatible declaration"),
+        "{error}"
+    );
+}
+
+#[test]
+fn initialized_global_lowers_to_byte_storage() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let op = append_global_alloc(&mut ctx, block, "nan_payload", false);
+    let alloc = mir::MirGlobalAllocOp::new(op);
+    alloc.set_alignment_value(&mut ctx, 4);
+    let initializer_key: Identifier = "global_initializer_hex".try_into().unwrap();
+    op.deref_mut(&ctx)
+        .attributes
+        .set(initializer_key, StringAttr::new("3412c07f".to_string()));
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let top = module_top_block(&ctx, module_ptr);
+    let global = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .find_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+        .expect("expected lowered device global");
+    let global_ty = global.get_type(&ctx);
+    let global_ty_ref = global_ty.deref(&ctx);
+    let array_ty = global_ty_ref
+        .downcast_ref::<ArrayType>()
+        .expect("initialized global must use byte-array storage");
+    assert_eq!(array_ty.size(), 4);
+    let elem_ty = array_ty.elem_type();
+    let elem_ty_ref = elem_ty.deref(&ctx);
+    let elem = elem_ty_ref
+        .downcast_ref::<IntegerType>()
+        .expect("byte-array element must be an integer");
+    assert_eq!(elem.width(), 8);
+    assert_eq!(global.get_alignment(&ctx), Some(4));
+    assert_eq!(global.initializer_hex(&ctx).as_deref(), Some("3412c07f"));
+}
+
+#[test]
+fn relocated_global_lowers_to_segmented_storage() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let word_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+    let mir_global_ty: TypeHandle = MirArrayType::get(&mut ctx, word_ty, 3).into();
+    let result_ty = MirPtrType::get_global(&mut ctx, mir_global_ty, false);
+    let op = Operation::new(
+        &mut ctx,
+        mir::MirGlobalAllocOp::get_concrete_op_info(),
+        vec![result_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let alloc = mir::MirGlobalAllocOp::new(op);
+    alloc.set_attr_global_type(&ctx, TypeAttr::new(mir_global_ty));
+    alloc.set_attr_global_key(&ctx, StringAttr::new("reference_table".to_string()));
+    alloc.set_alignment_value(&mut ctx, 8);
+    op.deref_mut(&ctx).attributes.set(
+        "global_initializer_hex".try_into().unwrap(),
+        StringAttr::new("000000000000000000000000000000000000000000000000".to_string()),
+    );
+    let encoded =
+        llvm::encode_global_initializer_relocations(&[llvm::GlobalInitializerRelocation {
+            source_offset: 8,
+            width_bytes: 8,
+            target_address_space: llvm_addr::GLOBAL,
+            target_addend: 4,
+            target_key: "target_static".to_string(),
+        }]);
+    op.deref_mut(&ctx).attributes.set(
+        "global_initializer_relocations".try_into().unwrap(),
+        StringAttr::new(encoded.clone()),
+    );
+    op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let top = module_top_block(&ctx, module_ptr);
+    let global = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .find_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+        .expect("expected lowered device global");
+    let global_ty = global.get_type(&ctx);
+    let global_ty_ref = global_ty.deref(&ctx);
+    let storage = global_ty_ref
+        .downcast_ref::<StructType>()
+        .expect("relocated initializer must use segmented struct storage");
+    assert_eq!(storage.num_fields(), 3);
+    assert_eq!(
+        global.source_global_key(&ctx).as_deref(),
+        Some("reference_table")
+    );
+    assert_eq!(
+        global.initializer_relocations(&ctx).as_deref(),
+        Some(encoded.as_str())
+    );
+}
+
+#[test]
+fn relocated_global_uses_packed_storage_for_unaligned_pointer_slot() {
+    let mut ctx = make_ctx();
+    let encoded =
+        llvm::encode_global_initializer_relocations(&[llvm::GlobalInitializerRelocation {
+            source_offset: 1,
+            width_bytes: 8,
+            target_address_space: llvm_addr::GLOBAL,
+            target_addend: 0,
+            target_key: "target_static".to_string(),
+        }]);
+
+    let storage = relocated_initializer_storage_type(&mut ctx, 9, 1, &encoded)
+        .expect("unaligned relocation should use packed storage");
+    let storage_ref = storage.deref(&ctx);
+    let struct_ty = storage_ref
+        .downcast_ref::<StructType>()
+        .expect("relocated initializer must use struct storage");
+    assert_eq!(struct_ty.layout(), StructLayout::Packed);
+    assert_eq!(struct_ty.num_fields(), 2);
+    assert_eq!(
+        crate::convert::types::llvm_type_size_align(&ctx, storage),
+        Some((9, 1))
+    );
+
+    let fields: Vec<_> = struct_ty.fields().collect();
+    let literal_ref = fields[0].deref(&ctx);
+    let literal = literal_ref
+        .downcast_ref::<ArrayType>()
+        .expect("leading literal span must be a byte array");
+    assert_eq!(literal.size(), 1);
+    let pointer_ref = fields[1].deref(&ctx);
+    let pointer = pointer_ref
+        .downcast_ref::<IntegerType>()
+        .expect("relocation slot must be an integer carrier");
+    assert_eq!(pointer.width(), 64);
+}
+
+#[test]
+fn relocated_global_uses_packed_storage_for_underaligned_allocation() {
+    let mut ctx = make_ctx();
+    let encoded =
+        llvm::encode_global_initializer_relocations(&[llvm::GlobalInitializerRelocation {
+            source_offset: 0,
+            width_bytes: 8,
+            target_address_space: llvm_addr::GLOBAL,
+            target_addend: 0,
+            target_key: "target_static".to_string(),
+        }]);
+
+    let storage = relocated_initializer_storage_type(&mut ctx, 8, 1, &encoded)
+        .expect("underaligned allocation should use packed storage");
+    let storage_ref = storage.deref(&ctx);
+    let struct_ty = storage_ref
+        .downcast_ref::<StructType>()
+        .expect("relocated initializer must use struct storage");
+    assert_eq!(struct_ty.layout(), StructLayout::Packed);
+    assert_eq!(
+        crate::convert::types::llvm_type_size_align(&ctx, storage),
+        Some((8, 1))
+    );
+}
+
+#[test]
+fn relocated_global_keeps_naturally_aligned_storage_unpacked() {
+    let mut ctx = make_ctx();
+    let encoded =
+        llvm::encode_global_initializer_relocations(&[llvm::GlobalInitializerRelocation {
+            source_offset: 8,
+            width_bytes: 8,
+            target_address_space: llvm_addr::GLOBAL,
+            target_addend: 0,
+            target_key: "target_static".to_string(),
+        }]);
+
+    let storage = relocated_initializer_storage_type(&mut ctx, 16, 8, &encoded)
+        .expect("aligned relocation should keep ordinary storage");
+    let storage_ref = storage.deref(&ctx);
+    let struct_ty = storage_ref
+        .downcast_ref::<StructType>()
+        .expect("relocated initializer must use struct storage");
+    assert_eq!(struct_ty.layout(), StructLayout::Unpacked);
+}
+
+#[test]
+fn relocated_global_rejects_overlapping_slots() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let word_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+    let mir_global_ty: TypeHandle = MirArrayType::get(&mut ctx, word_ty, 2).into();
+    let result_ty = MirPtrType::get_global(&mut ctx, mir_global_ty, false);
+    let op = Operation::new(
+        &mut ctx,
+        mir::MirGlobalAllocOp::get_concrete_op_info(),
+        vec![result_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let alloc = mir::MirGlobalAllocOp::new(op);
+    alloc.set_attr_global_type(&ctx, TypeAttr::new(mir_global_ty));
+    alloc.set_attr_global_key(&ctx, StringAttr::new("overlap".to_string()));
+    alloc.set_alignment_value(&mut ctx, 8);
+    op.deref_mut(&ctx).attributes.set(
+        "global_initializer_hex".try_into().unwrap(),
+        StringAttr::new("00000000000000000000000000000000".to_string()),
+    );
+    let encoded = llvm::encode_global_initializer_relocations(&[
+        llvm::GlobalInitializerRelocation {
+            source_offset: 0,
+            width_bytes: 8,
+            target_address_space: llvm_addr::GLOBAL,
+            target_addend: 0,
+            target_key: "a".to_string(),
+        },
+        llvm::GlobalInitializerRelocation {
+            source_offset: 0,
+            width_bytes: 8,
+            target_address_space: llvm_addr::GLOBAL,
+            target_addend: 0,
+            target_key: "b".to_string(),
+        },
+    ]);
+    op.deref_mut(&ctx).attributes.set(
+        "global_initializer_relocations".try_into().unwrap(),
+        StringAttr::new(encoded),
+    );
+    op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    let error = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect_err("overlapping relocations must fail closed");
+    assert!(error.to_string().contains("overlaps"), "{error}");
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/tests/enums.rs b/crates/mir-lower/src/convert/ops/memory/tests/enums.rs
new file mode 100644
index 0000000000..5658a39cc1
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/tests/enums.rs
@@ -0,0 +1,322 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#![allow(clippy::disallowed_methods)]
+
+use super::*;
+
+// =========================================================================
+// Enum layout: converted width per shape + divergent-enum rejection
+// =========================================================================
+
+use dialect_mir::types::{EnumVariant, MirEnumType};
+
+/// Build a Direct-tag `MirEnumType` the way the importer does:
+/// unsigned tag of `tag_bits`, plus rustc's `total_size`/`abi_align`.
+fn make_enum_ty(
+    ctx: &mut Context,
+    name: &str,
+    tag_bits: u32,
+    variants: Vec<EnumVariant>,
+    total_size: u64,
+    abi_align: u64,
+) -> TypeHandle {
+    let tag_ty: TypeHandle = IntegerType::get(ctx, tag_bits, Signedness::Unsigned).into();
+    // Sequential 0..n discriminants: these layout tests only exercise
+    // size/width, not value mapping.
+    let discriminants: Vec<u64> = (0..variants.len() as u64).collect();
+    MirEnumType::get_with_layout(
+        ctx,
+        name.to_string(),
+        tag_ty,
+        discriminants,
+        variants,
+        0, // tag at byte 0, like every shape these tests exercise
+        total_size,
+        abi_align,
+    )
+    .into()
+}
+
+fn unit_variants(n: usize) -> Vec<EnumVariant> {
+    (0..n).map(|i| EnumVariant::unit(format!("V{i}"))).collect()
+}
+
+/// Converted enum allocation size must equal rustc's `total_size` for
+/// every memory-faithful tag shape: that size is what GEP strides by.
+#[test]
+fn enum_conversion_strides_by_rustc_size() {
+    use crate::convert::types::llvm_type_size_align;
+
+    let mut ctx = make_ctx();
+
+    // #[repr(u32)] fieldless (issue #118 shape): {i32}, 4 bytes.
+    let repr_u32 = make_enum_ty(&mut ctx, "ReprU32", 32, unit_variants(4), 4, 4);
+    let conv = convert_type(&mut ctx, repr_u32).unwrap();
+    assert_eq!(
+        llvm_type_size_align(&ctx, conv),
+        Some((4, 4)),
+        "repr(u32) tag"
+    );
+
+    // #[repr(usize)] fieldless: {i64}, 8 bytes.
+    let repr_usize = make_enum_ty(&mut ctx, "ReprUsize", 64, unit_variants(4), 8, 8);
+    let conv = convert_type(&mut ctx, repr_usize).unwrap();
+    assert_eq!(
+        llvm_type_size_align(&ctx, conv),
+        Some((8, 8)),
+        "repr(usize) tag"
+    );
+
+    // repr(align(8)) with an i8 tag: the byte claims alone would give
+    // alignment 1, so the slot map raises the storage alignment with a
+    // zero-length anchor field. Size and alignment must both match
+    // rustc, or arrays and by-value ABI uses would be unsound.
+    let padded = make_enum_ty(&mut ctx, "Padded", 8, unit_variants(2), 8, 8);
+    let conv = convert_type(&mut ctx, padded).unwrap();
+    assert_eq!(
+        llvm_type_size_align(&ctx, conv),
+        Some((8, 8)),
+        "repr(align(8)) i8 tag"
+    );
+
+    // u8 tag + i64 payload, rustc size 16: the slot map places the
+    // payload at its rustc byte offset 8 behind an explicit
+    // [7 x i8] filler, making the layout datalayout-independent.
+    let i64_payload: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+    let payload = make_enum_ty(
+        &mut ctx,
+        "OnePayload",
+        8,
+        vec![
+            EnumVariant::new_with_layout("A".to_string(), vec![i64_payload], vec![8], vec![8]),
+            EnumVariant::unit("B".to_string()),
+        ],
+        16,
+        8,
+    );
+    let conv = convert_type(&mut ctx, payload).unwrap();
+    let (size, _align) = llvm_type_size_align(&ctx, conv).unwrap();
+    assert_eq!(size, 16, "natural layout matches rustc size, no pad");
+    let conv_ref = conv.deref(&ctx);
+    let struct_ty = conv_ref
+        .downcast_ref::<llvm_export::types::StructType>()
+        .expect("converted enum is a struct");
+    assert_eq!(
+        struct_ty.fields().count(),
+        3,
+        "{{tag, [7 x i8] filler, payload}}: explicit filler to byte 8"
+    );
+}
+
+/// Multi-payload enum: variants overlap in Rust, and identical
+/// (offset, converted type) payloads share one typed slot, so the
+/// converted struct is byte-identical to rustc's layout AND every
+/// access stays pure SSA (no spill).
+#[test]
+fn multi_payload_enum_shares_payload_slot() {
+    use crate::convert::types::{build_enum_slot_map, llvm_type_size_align};
+
+    let mut ctx = make_ctx();
+    let e = make_multi_payload_enum_ty(&mut ctx);
+    let map = build_enum_slot_map(&mut ctx, e).unwrap();
+    assert_eq!(map.carrier_slot, Some(0));
+    assert_eq!(
+        map.field_slots,
+        vec![Some(1), Some(1)],
+        "A.0 and B.0 overlap at byte 4 with the same type: one shared slot"
+    );
+    assert_eq!(
+        llvm_type_size_align(&ctx, map.llvm_struct_ty),
+        Some((8, 4)),
+        "byte-identical to rustc's 8-byte layout, not the 12-byte concat"
+    );
+}
+
+/// rustc may place the tag AFTER payload bytes; the slot map must
+/// follow the recorded tag_offset, never assume slot 0.
+#[test]
+fn enum_slot_map_tag_not_at_zero() {
+    use crate::convert::types::{build_enum_slot_map, llvm_type_size_align};
+
+    let mut ctx = make_ctx();
+    let u64_a: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+    let u64_b: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+    let tag_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+    // enum F { A(u64), B(u64) }: payloads share byte 0, tag at byte 8.
+    let ty: TypeHandle = MirEnumType::get_with_layout(
+        &mut ctx,
+        "TagAtEight".to_string(),
+        tag_ty,
+        vec![0, 1],
+        vec![
+            EnumVariant::new_with_layout("A".to_string(), vec![u64_a], vec![0], vec![8]),
+            EnumVariant::new_with_layout("B".to_string(), vec![u64_b], vec![0], vec![8]),
+        ],
+        8,
+        16,
+        8,
+    )
+    .into();
+    let map = build_enum_slot_map(&mut ctx, ty).unwrap();
+    assert_eq!(
+        map.field_slots,
+        vec![Some(0), Some(0)],
+        "payloads share the first slot"
+    );
+    assert_eq!(
+        map.carrier_slot,
+        Some(1),
+        "tag claims its own slot at byte 8"
+    );
+    let (size, _align) = llvm_type_size_align(&ctx, map.llvm_struct_ty).unwrap();
+    assert_eq!(size, 16, "{{ i64, i8, [7 x i8] }}");
+}
+
+/// Multi-payload enum whose variants overlap in Rust: both payloads use
+/// bytes 4..8 after the direct `u32` tag, so the complete value is eight
+/// bytes. Mimics `#[repr(u32)] enum E { A(u32), B(u32) }`.
+fn make_multi_payload_enum_ty(ctx: &mut Context) -> TypeHandle {
+    let i32_a: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+    let i32_b: TypeHandle = IntegerType::get(ctx, 32, Signedness::Unsigned).into();
+    make_enum_ty(
+        ctx,
+        "MultiPayload",
+        32,
+        vec![
+            EnumVariant::new_with_layout("A".to_string(), vec![i32_a], vec![4], vec![4]),
+            EnumVariant::new_with_layout("B".to_string(), vec![i32_b], vec![4], vec![4]),
+        ],
+        8,
+        4,
+    )
+}
+
+/// Device-local GEP + load must use the same exact eight-byte rustc layout
+/// as every other enum path. This protects pointer stride in issue #131's
+/// in-kernel `[E; 4]` arrays; the sibling kernel-parameter test proves the
+/// same representation is also valid at the host/device boundary.
+#[test]
+fn device_local_multi_payload_enum_gep_and_load_lower() {
+    let mut ctx = make_ctx();
+    let enum_ty = make_multi_payload_enum_ty(&mut ctx);
+    let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Signless).into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, enum_ty, true);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into(), i64_ty], vec![]);
+    let ptr_val = block.deref(&ctx).get_argument(0);
+    let off_val = block.deref(&ctx).get_argument(1);
+
+    let off_op = Operation::new(
+        &mut ctx,
+        mir::MirPtrOffsetOp::get_concrete_op_info(),
+        vec![mir_ptr_ty.into()],
+        vec![ptr_val, off_val],
+        vec![],
+        0,
+    );
+    off_op.insert_at_back(block, &ctx);
+    let elem_ptr = off_op.deref(&ctx).get_result(0);
+
+    let load_op = Operation::new(
+        &mut ctx,
+        mir::MirLoadOp::get_concrete_op_info(),
+        vec![enum_ty],
+        vec![elem_ptr],
+        vec![],
+        0,
+    );
+    load_op.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect("device-local rustc-layout enum GEP + load must lower");
+}
+
+/// A kernel parameter may carry this enum because the device slot map is
+/// byte-identical to rustc's overlapped host layout.
+#[test]
+fn kernel_param_accepts_multi_payload_enum() {
+    use pliron::builtin::attributes::StringAttr;
+
+    let mut ctx = make_ctx();
+    let enum_ty = make_multi_payload_enum_ty(&mut ctx);
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, enum_ty, false);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into()], vec![]);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    // Mark the function as a GPU kernel the way the importer does.
+    {
+        let module_block = module_ptr
+            .deref(&ctx)
+            .get_region(0)
+            .deref(&ctx)
+            .iter(&ctx)
+            .next()
+            .unwrap();
+        let func_op = module_block.deref(&ctx).iter(&ctx).next().unwrap();
+        let kernel_attr = StringAttr::new("true".to_string());
+        let key: pliron::identifier::Identifier = "gpu_kernel".try_into().unwrap();
+        func_op.deref_mut(&ctx).attributes.set(key, kernel_attr);
+    }
+
+    // The slot map lowers MultiPayload byte-identically to rustc's
+    // layout ({ i32, i32 }, 8 bytes), so the kernel ABI accepts it.
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect("multi-payload enum kernel param must lower");
+}
+
+/// A legacy enum without physical rustc metadata must be rejected at the
+/// kernel boundary. Importer-produced niche layouts are now known and are
+/// accepted; this fixture deliberately constructs `Unknown` metadata.
+#[test]
+fn kernel_param_rejects_enum_with_unknown_layout() {
+    use pliron::builtin::attributes::StringAttr;
+
+    let mut ctx = make_ctx();
+    // MirEnumType::get with no layout is the legacy Unknown form.
+    let i32_ty: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+    let pointee = MirPtrType::get_generic(&mut ctx, i32_ty, false);
+    let tag_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Unsigned).into();
+    let niched: TypeHandle = MirEnumType::get(
+        &mut ctx,
+        "Option".to_string(),
+        tag_ty,
+        vec![0, 1],
+        vec![
+            EnumVariant::unit("None".to_string()),
+            EnumVariant::new("Some".to_string(), vec![pointee.into()]),
+        ],
+    )
+    .into();
+    let mir_ptr_ty = MirPtrType::get_generic(&mut ctx, niched, false);
+
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![mir_ptr_ty.into()], vec![]);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    {
+        let module_block = module_ptr
+            .deref(&ctx)
+            .get_region(0)
+            .deref(&ctx)
+            .iter(&ctx)
+            .next()
+            .unwrap();
+        let func_op = module_block.deref(&ctx).iter(&ctx).next().unwrap();
+        let kernel_attr = StringAttr::new("true".to_string());
+        let key: pliron::identifier::Identifier = "gpu_kernel".try_into().unwrap();
+        func_op.deref_mut(&ctx).attributes.set(key, kernel_attr);
+    }
+
+    let err = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect_err("unknown-layout enum kernel param must be rejected");
+    let msg = format!("{err}");
+    assert!(
+        msg.contains("Option") && msg.contains("kernel boundary"),
+        "error must name the enum and the kernel boundary, got: {msg}"
+    );
+    assert!(msg.contains("unknown physical rustc layout"));
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/tests/mod.rs b/crates/mir-lower/src/convert/ops/memory/tests/mod.rs
new file mode 100644
index 0000000000..616fe704f7
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/tests/mod.rs
@@ -0,0 +1,83 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! End-to-end lowering tests for `dialect-mir` memory ops.
+//!
+//! The `convert_*` functions in this file take a live
+//! `DialectConversionRewriter`, which is owned by pliron's conversion
+//! driver and not constructible standalone. So each test builds a small
+//! MIR module, runs the full `lower_mir_to_llvm` pass on it, and asserts
+//! the lowered module contains the expected `dialect-llvm` shape — same
+//! pattern as `tests/lowering_test.rs`.
+
+// Tests build kinded fixture types directly; production minting lives in mir-importer's facts.rs.
+#![allow(clippy::disallowed_methods)]
+
+mod access;
+mod alignment;
+mod debug_provenance;
+mod device_global;
+mod enums;
+mod shared;
+
+use crate::context::DeviceGlobalDeclaration;
+use crate::convert::ops::test_util::*;
+use crate::convert::types::convert_type;
+use dialect_mir::attributes::MirPointerKindAuthorityAttr;
+use dialect_mir::ops as mir;
+use dialect_mir::types::{
+    MirArrayType, MirPointerKind, MirPtrType, MirStructType, MirTupleType, MirUnionType,
+};
+use llvm_export::op_interfaces::PointerTypeResult;
+use llvm_export::ops as llvm;
+use llvm_export::ops::GlobalOpExt;
+use llvm_export::types::{
+    ArrayType, PointerType, StructLayout, StructType, address_space as llvm_addr,
+};
+use pliron::basic_block::BasicBlock;
+use pliron::builtin::attributes::{StringAttr, TypeAttr};
+use pliron::builtin::op_interfaces::SymbolOpInterface;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::identifier::Identifier;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::location::{Located, Location, Source};
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::{TypeHandle, Typed};
+use pliron::utils::apint::APInt;
+use std::path::PathBuf;
+
+use super::device_global::relocated_initializer_storage_type;
+
+fn ptr_addrspace(ctx: &Context, ty: TypeHandle) -> u32 {
+    ty.deref(ctx)
+        .downcast_ref::<PointerType>()
+        .expect("expected llvm.PointerType")
+        .address_space()
+}
+
+fn src_location(ctx: &mut Context, file: &str, line: i32, column: i32) -> Location {
+    Location::SrcPos {
+        src: Source::new_from_file(ctx, PathBuf::from(file)),
+        pos: combine::stream::position::SourcePosition { line, column },
+    }
+}
+
+fn over_aligned_tuple_ty(ctx: &mut Context) -> TypeHandle {
+    let byte: TypeHandle = IntegerType::get(ctx, 8, Signedness::Unsigned).into();
+    let marker: TypeHandle = MirStructType::get_with_full_layout(
+        ctx,
+        "Align32".into(),
+        vec![],
+        vec![],
+        vec![],
+        vec![],
+        0,
+        32,
+    )
+    .into();
+    MirTupleType::get_with_layout(ctx, vec![marker, byte], vec![0, 1], vec![0, 0], 32, 32).into()
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/tests/shared.rs b/crates/mir-lower/src/convert/ops/memory/tests/shared.rs
new file mode 100644
index 0000000000..9cb4fa0cef
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/tests/shared.rs
@@ -0,0 +1,560 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#![allow(clippy::disallowed_methods)]
+
+use super::device_global::append_global_alloc;
+use super::*;
+
+/// Build a `mir.shared_alloc` returning `MirPtrType<i32, addrspace=3>` of
+/// length `size`, with the given alloc_key, and append it to `block`.
+fn append_shared_alloc(
+    ctx: &mut Context,
+    block: Ptr<BasicBlock>,
+    alloc_key: &str,
+    size: u64,
+) -> Ptr<Operation> {
+    append_shared_alloc_named(ctx, block, alloc_key, size, None)
+}
+
+/// As [`append_shared_alloc`], additionally carrying the Rust path of the
+/// `static` the allocation came from.
+fn append_shared_alloc_named(
+    ctx: &mut Context,
+    block: Ptr<BasicBlock>,
+    alloc_key: &str,
+    size: u64,
+    source_name: Option<&str>,
+) -> Ptr<Operation> {
+    let i32_ty: TypeHandle = IntegerType::get(ctx, 32, Signedness::Signless).into();
+    append_shared_alloc_typed(ctx, block, alloc_key, i32_ty, size, source_name, 0)
+}
+
+#[allow(clippy::too_many_arguments)]
+fn append_shared_alloc_typed(
+    ctx: &mut Context,
+    block: Ptr<BasicBlock>,
+    alloc_key: &str,
+    element_type: TypeHandle,
+    size: u64,
+    source_name: Option<&str>,
+    alignment: u64,
+) -> Ptr<Operation> {
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::utils::apint::APInt;
+
+    let i32_ty = element_type;
+    let result_ty = MirPtrType::get_shared(ctx, i32_ty, true);
+    let op = Operation::new(
+        ctx,
+        mir::MirSharedAllocOp::get_concrete_op_info(),
+        vec![result_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let alloc = mir::MirSharedAllocOp::new(op);
+    alloc.set_attr_elem_type(ctx, TypeAttr::new(i32_ty));
+    let size_attr = IntegerAttr::new(
+        IntegerType::get(ctx, 64, Signedness::Signless),
+        APInt::from_u64(size, std::num::NonZeroUsize::new(64).unwrap()),
+    );
+    alloc.set_attr_size(ctx, size_attr);
+    alloc.set_attr_alloc_key(ctx, StringAttr::new(alloc_key.to_string()));
+    if let Some(source_name) = source_name {
+        alloc.set_attr_source_name(ctx, StringAttr::new(source_name.to_string()));
+    }
+    if alignment != 0 {
+        alloc.set_alignment_value(ctx, alignment);
+    }
+    op.insert_at_back(block, ctx);
+    op
+}
+
+fn shared_array_debug_info(count: u64) -> llvm::DebugGlobalVariableInfo {
+    llvm::DebugGlobalVariableInfo {
+        name: "TILE".to_string(),
+        namespace: vec!["fixture".to_string(), "kernel".to_string()],
+        ty: llvm::DebugLocalTypeKind::Array {
+            name: format!("[i32; {count}]"),
+            size_bits: count * 32,
+            element: Box::new(llvm::DebugLocalTypeKind::Basic {
+                name: "i32".to_string(),
+                size_bits: 32,
+                encoding: "DW_ATE_signed",
+            }),
+            count,
+        },
+        declaration: llvm::DebugSourcePosition {
+            file: PathBuf::from("/tmp/shared.rs"),
+            line: 7,
+            column: 5,
+        },
+        is_local_to_unit: true,
+        is_function_local: true,
+    }
+}
+
+fn shared_static_key(symbol: &str) -> String {
+    dialect_mir::ops::encode_rust_static_global_key(symbol)
+}
+
+#[test]
+fn convert_shared_alloc_creates_global_in_addrspace_3() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    append_shared_alloc(&mut ctx, block, "k1", 64);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    // Global lives at module level; addressof lives in the function body.
+    let top = module_top_block(&ctx, module_ptr);
+    let global = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .find_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+        .expect("expected an llvm.global for the shared allocation");
+    assert_eq!(
+        global.address_space(&ctx),
+        llvm_addr::SHARED,
+        "shared_alloc global must live in addrspace 3"
+    );
+    assert!(
+        global
+            .get_symbol_name(&ctx)
+            .to_string()
+            .starts_with("__shared_mem_"),
+        "shared global should have __shared_mem_ prefix"
+    );
+
+    let body = kernel_blocks(&ctx, module_ptr);
+    let addrof = find_first::<llvm::AddressOfOp>(&ctx, &body).expect("expected an llvm.addressof");
+    assert_eq!(
+        ptr_addrspace(
+            &ctx,
+            addrof
+                .get_operation()
+                .deref(&ctx)
+                .get_result(0)
+                .get_type(&ctx)
+        ),
+        llvm_addr::SHARED,
+    );
+}
+
+#[test]
+fn convert_shared_alloc_deduplicates_by_alloc_key() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    // Two allocations sharing the same alloc_key — they must collapse to
+    // a single underlying global (this is what enables a single `static`
+    // referenced from multiple sites to land in one shared region).
+    append_shared_alloc(&mut ctx, block, "same-key", 64);
+    append_shared_alloc(&mut ctx, block, "same-key", 64);
+    // A third with a different key must NOT dedupe with them.
+    append_shared_alloc(&mut ctx, block, "other-key", 32);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let top = module_top_block(&ctx, module_ptr);
+    let shared_globals = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+        .filter(|g| g.address_space(&ctx) == llvm_addr::SHARED)
+        .count();
+    assert_eq!(
+        shared_globals, 2,
+        "two distinct alloc_keys must produce two globals"
+    );
+
+    // Each of the three mir.shared_alloc ops becomes one addressof.
+    let body = kernel_blocks(&ctx, module_ptr);
+    assert_eq!(count_ops::<llvm::AddressOfOp>(&ctx, &body), 3);
+}
+
+#[test]
+fn convert_shared_alloc_rejects_conflicting_key_declarations() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    append_shared_alloc(&mut ctx, block, "conflicting-key", 1);
+    let differently_aligned = append_shared_alloc(&mut ctx, block, "conflicting-key", 1);
+    mir::MirSharedAllocOp::new(differently_aligned).set_alignment_value(&mut ctx, 16);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    let error = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect_err("one shared alloc_key must not name differently aligned storage");
+    assert!(
+        error.to_string().contains("incompatible declaration"),
+        "{error}"
+    );
+}
+
+#[test]
+fn shared_alloc_repeated_debug_identity_is_attached_once() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let key = shared_static_key("_Rfixture4TILE");
+    for _ in 0..2 {
+        let op =
+            append_shared_alloc_named(&mut ctx, block, &key, 32, Some("fixture::kernel::TILE"));
+        let info = shared_array_debug_info(32);
+        llvm::set_debug_global_variable(&mut ctx, op, &info);
+        llvm::set_debug_global_owner_function(&mut ctx, op, "fixture_kernel");
+    }
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+    let top = module_top_block(&ctx, module_ptr);
+    let globals: Vec<_> = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+        .filter(|global| global.address_space(&ctx) == llvm_addr::SHARED)
+        .collect();
+    assert_eq!(
+        globals.len(),
+        1,
+        "repeated references must share one global"
+    );
+    assert_eq!(
+        llvm::debug_global_variable(&ctx, globals[0].get_operation()),
+        Some(shared_array_debug_info(32))
+    );
+    assert_eq!(
+        llvm::debug_global_owner_function(&ctx, globals[0].get_operation()).as_deref(),
+        Some("fixture_kernel")
+    );
+}
+
+/// One function-local shared static materialized in two owning functions
+/// (for example a `#[device]` helper inlined into two kernels) is a valid
+/// release build, so debug metadata must not turn it into an error. DWARF
+/// cannot truthfully scope one AS3 object to two subprograms either, so
+/// the divergent identity fails open: the storage is still shared and the
+/// debug attachment is dropped.
+#[test]
+fn shared_alloc_owner_conflict_drops_debug_metadata() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let key = shared_static_key("_Rfixture4TILE");
+    for owner in ["fixture_kernel", "other_kernel"] {
+        let op =
+            append_shared_alloc_named(&mut ctx, block, &key, 32, Some("fixture::kernel::TILE"));
+        let info = shared_array_debug_info(32);
+        llvm::set_debug_global_variable(&mut ctx, op, &info);
+        llvm::set_debug_global_owner_function(&mut ctx, op, owner);
+    }
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect("divergent debug identity must not fail a build release accepts");
+    let top = module_top_block(&ctx, module_ptr);
+    let globals: Vec<_> = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+        .filter(|global| global.address_space(&ctx) == llvm_addr::SHARED)
+        .collect();
+    assert_eq!(
+        globals.len(),
+        1,
+        "the physical storage must still be shared"
+    );
+    assert!(llvm::debug_global_variable(&ctx, globals[0].get_operation()).is_none());
+    assert!(llvm::debug_global_owner_function(&ctx, globals[0].get_operation()).is_none());
+}
+
+#[test]
+fn dynamic_extern_then_static_shared_rejects_reserved_key_collision() {
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::utils::apint::APInt;
+
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let i8_ty: TypeHandle = IntegerType::get(&ctx, 8, Signedness::Signless).into();
+    let shared_i8 = MirPtrType::get_shared(&mut ctx, i8_ty, true);
+
+    // Lower the dynamic declaration first. Its internal cache key is
+    // deliberately then reused by a static allocation with the same
+    // physical type, size, and alignment. Those declarations must still
+    // be rejected because one is extern storage and one is fixed storage.
+    let dynamic = Operation::new(
+        &mut ctx,
+        mir::MirExternSharedOp::get_concrete_op_info(),
+        vec![shared_i8.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    mir::MirExternSharedOp::new(dynamic).set_alignment_value(&mut ctx, 128);
+    dynamic.insert_at_back(block, &ctx);
+
+    let fixed = Operation::new(
+        &mut ctx,
+        mir::MirSharedAllocOp::get_concrete_op_info(),
+        vec![shared_i8.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let fixed_alloc = mir::MirSharedAllocOp::new(fixed);
+    fixed_alloc.set_attr_elem_type(&ctx, TypeAttr::new(i8_ty));
+    fixed_alloc.set_attr_size(
+        &ctx,
+        IntegerAttr::new(
+            IntegerType::get(&ctx, 64, Signedness::Unsigned),
+            APInt::from_u64(0, std::num::NonZeroUsize::new(64).unwrap()),
+        ),
+    );
+    fixed_alloc.set_attr_alloc_key(
+        &ctx,
+        StringAttr::new("__dynamic_smem_global_created_kernel_func".to_string()),
+    );
+    fixed_alloc.set_alignment_value(&mut ctx, 128);
+    fixed.insert_at_back(block, &ctx);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    let error = crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect_err("a static allocation must not reuse a dynamic extern declaration");
+    let message = error.to_string();
+    assert!(message.contains("incompatible declaration"), "{message}");
+    assert!(
+        message.contains("duplicate shared alloc_key"),
+        "the dynamic declaration must be observed first, got: {message}"
+    );
+}
+
+#[test]
+fn shared_alloc_mismatched_debug_type_fails_closed_without_failing_lowering() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let key = shared_static_key("_Rfixture4TILE");
+    let op = append_shared_alloc_named(&mut ctx, block, &key, 32, Some("fixture::kernel::TILE"));
+    llvm::set_debug_global_variable(&mut ctx, op, &shared_array_debug_info(31));
+    llvm::set_debug_global_owner_function(&mut ctx, op, "fixture_kernel");
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect("bad optional metadata must not fail compilation");
+    let top = module_top_block(&ctx, module_ptr);
+    let global = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .find_map(|candidate| Operation::get_op::<llvm::GlobalOp>(candidate, &ctx))
+        .expect("shared global");
+    assert!(llvm::debug_global_variable(&ctx, global.get_operation()).is_none());
+    assert!(llvm::debug_global_owner_function(&ctx, global.get_operation()).is_none());
+}
+
+#[test]
+fn barrier_semantic_struct_matches_single_i64_shared_backing() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    let i64_ty: TypeHandle = IntegerType::get(&ctx, 64, Signedness::Unsigned).into();
+    let key = shared_static_key("_Rfixture7BARRIER");
+    let op = append_shared_alloc_typed(
+        &mut ctx,
+        block,
+        &key,
+        i64_ty,
+        1,
+        Some("fixture::kernel::BARRIER"),
+        8,
+    );
+    let info = llvm::DebugGlobalVariableInfo {
+        name: "BARRIER".to_string(),
+        namespace: vec!["fixture".to_string(), "kernel".to_string()],
+        ty: llvm::DebugLocalTypeKind::Struct {
+            name: "Barrier".to_string(),
+            size_bits: 64,
+            members: vec![llvm::DebugTypeMember {
+                name: "_state".to_string(),
+                offset_bits: 0,
+                ty: llvm::DebugLocalTypeKind::Basic {
+                    name: "u64".to_string(),
+                    size_bits: 64,
+                    encoding: "DW_ATE_unsigned",
+                },
+            }],
+        },
+        declaration: llvm::DebugSourcePosition {
+            file: PathBuf::from("/tmp/barrier.rs"),
+            line: 8,
+            column: 9,
+        },
+        is_local_to_unit: true,
+        is_function_local: true,
+    };
+    llvm::set_debug_global_variable(&mut ctx, op, &info);
+    llvm::set_debug_global_owner_function(&mut ctx, op, "fixture_kernel");
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("Barrier lowering succeeds");
+    let top = module_top_block(&ctx, module_ptr);
+    let global = top
+        .deref(&ctx)
+        .iter(&ctx)
+        .find_map(|candidate| Operation::get_op::<llvm::GlobalOp>(candidate, &ctx))
+        .expect("Barrier shared global");
+    assert_eq!(global.get_alignment(&ctx), Some(8));
+    assert_eq!(
+        llvm::debug_global_variable(&ctx, global.get_operation()),
+        Some(info)
+    );
+}
+
+/// Collect `(symbol, source_name)` for every shared global in the module.
+fn shared_global_source_names(
+    ctx: &Context,
+    module_ptr: Ptr<Operation>,
+) -> Vec<(String, Option<String>)> {
+    use llvm_export::ops::GlobalOpExt;
+
+    let top = module_top_block(ctx, module_ptr);
+    let mut named: Vec<_> = top
+        .deref(ctx)
+        .iter(ctx)
+        .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, ctx))
+        .filter(|g| g.address_space(ctx) == llvm_addr::SHARED)
+        .map(|g| {
+            (
+                g.get_symbol_name(ctx).to_string(),
+                g.shared_source_name(ctx),
+            )
+        })
+        .collect();
+    // Globals are inserted at the front of the module block, so iteration
+    // order is the reverse of creation order. Sort for a stable assertion.
+    named.sort();
+    named
+}
+
+#[test]
+fn shared_alloc_source_name_reaches_the_generated_global() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    append_shared_alloc_named(&mut ctx, block, "k1", 64, Some("my_kernel::TILE"));
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let named = shared_global_source_names(&ctx, module_ptr);
+    assert_eq!(named.len(), 1, "expected exactly one shared global");
+    let (symbol, source_name) = &named[0];
+    // The symbol itself must stay anonymous: the whole point of the
+    // sidecar attribute is that it does not perturb the emitted name.
+    assert!(
+        symbol.starts_with("__shared_mem_"),
+        "the generated symbol must not be renamed, got `{symbol}`"
+    );
+    assert_eq!(source_name.as_deref(), Some("my_kernel::TILE"));
+}
+
+#[test]
+fn shared_alloc_without_source_name_leaves_the_global_unlabelled() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    append_shared_alloc(&mut ctx, block, "k1", 64);
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let named = shared_global_source_names(&ctx, module_ptr);
+    assert_eq!(named.len(), 1);
+    assert_eq!(named[0].1, None, "an unnamed allocation must stay unnamed");
+}
+
+#[test]
+fn shared_alloc_source_names_are_per_global_not_shared_across_them() {
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    // Two references to one static dedupe onto a single global, and a
+    // second static gets its own. Each global must carry its own name —
+    // the failure this guards is one name leaking onto every allocation.
+    append_shared_alloc_named(&mut ctx, block, "tile", 64, Some("my_kernel::TILE"));
+    append_shared_alloc_named(&mut ctx, block, "tile", 64, Some("my_kernel::TILE"));
+    append_shared_alloc_named(&mut ctx, block, "scratch", 32, Some("my_kernel::SCRATCH"));
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let names: Vec<_> = shared_global_source_names(&ctx, module_ptr)
+        .into_iter()
+        .map(|(_, source_name)| source_name)
+        .collect();
+    assert_eq!(names.len(), 2, "the shared alloc_key must still dedupe");
+    let mut names: Vec<_> = names.into_iter().map(|n| n.expect("named")).collect();
+    names.sort();
+    assert_eq!(names, vec!["my_kernel::SCRATCH", "my_kernel::TILE"]);
+}
+
+#[test]
+fn shared_alloc_source_name_reaches_the_exported_llvm_ir() {
+    // The end the feature exists for: a consumer holding only the emitted
+    // artifact can tell which Rust `static` a `__shared_mem_N` block is.
+    let mut ctx = make_ctx();
+    let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+    append_shared_alloc_named(&mut ctx, block, "tile", 64, Some("my_kernel::TILE"));
+    append_mir_return(&mut ctx, block, vec![]);
+
+    crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+    let module = Operation::get_op::<pliron::builtin::ops::ModuleOp>(module_ptr, &ctx)
+        .expect("lowered top-level op is a module");
+    let ir = llvm_export::export::export_module_to_string(&ctx, &module).expect("export");
+
+    let comment_index = ir
+        .find("; shared source: my_kernel::TILE")
+        .unwrap_or_else(|| panic!("exported IR must name the shared source:\n{ir}"));
+    let definition_index = ir
+        .find("__shared_mem_")
+        .expect("exported IR must declare the shared global");
+    assert!(
+        comment_index < definition_index,
+        "the source comment must precede the global it describes:\n{ir}"
+    );
+}
+
+/// A `__shared_mem_N` or `__device_global_N` index must depend only on
+/// the module being lowered, not on how many allocations any OTHER
+/// module has already lowered in this process (#706). Before the fix,
+/// each `N` came from a `static AtomicUsize` shared across every call in
+/// the process, so lowering the second of these two modules would have
+/// produced `__shared_mem_1` and `__device_global_1`, not the `_0` names.
+#[test]
+fn shared_and_device_global_indices_are_per_module_not_process_global() {
+    for _ in 0..2 {
+        let mut ctx = make_ctx();
+        let (module_ptr, block) = build_kernel(&mut ctx, vec![], vec![]);
+        append_shared_alloc(&mut ctx, block, "k", 64);
+        append_global_alloc(&mut ctx, block, "ordinary_static", false);
+        append_mir_return(&mut ctx, block, vec![]);
+
+        crate::lower_mir_to_llvm(&mut ctx, module_ptr).expect("lowering failed");
+
+        let top = module_top_block(&ctx, module_ptr);
+        let names: Vec<String> = top
+            .deref(&ctx)
+            .iter(&ctx)
+            .filter_map(|op| Operation::get_op::<llvm::GlobalOp>(op, &ctx))
+            .map(|g| g.get_symbol_name(&ctx).to_string())
+            .collect();
+        assert!(
+            names.iter().any(|n| n == "__shared_mem_0"),
+            "a module with exactly one shared allocation must always name it \
+                 __shared_mem_0, regardless of how many other modules already lowered \
+                 one in this process (got {names:?})"
+        );
+        assert!(
+            names.iter().any(|n| n == "__device_global_0"),
+            "a module with exactly one ordinary device global must always name it \
+                 __device_global_0, regardless of how many other modules already \
+                 lowered one in this process (got {names:?})"
+        );
+    }
+}
diff --git a/crates/mir-lower/src/convert/ops/memory/transfer.rs b/crates/mir-lower/src/convert/ops/memory/transfer.rs
new file mode 100644
index 0000000000..f2d5367b07
--- /dev/null
+++ b/crates/mir-lower/src/convert/ops/memory/transfer.rs
@@ -0,0 +1,237 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Conversions for `mir.memcpy` / `mir.memmove` and their shared lowering body.
+
+use super::common::anyhow_to_pliron;
+use crate::convert::types::{convert_type, llvm_type_size_align, mir_element_stride};
+use crate::helpers;
+use llvm_export::attributes::IntegerOverflowFlagsAttr;
+use llvm_export::op_interfaces::IntBinArithOpWithOverflowFlag;
+use llvm_export::ops as llvm;
+use llvm_export::types::{FuncType, VoidType};
+use pliron::attribute::AttrObj;
+use pliron::builtin::attributes::IntegerAttr;
+use pliron::builtin::op_interfaces::CallOpCallable;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::identifier::Identifier;
+use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo};
+use pliron::irbuild::inserter::Inserter;
+use pliron::irbuild::rewriter::Rewriter;
+use pliron::location::Located;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::result::Result;
+use pliron::r#type::Typed;
+use pliron::utils::apint::APInt;
+
+/// Convert `mir.memcpy` to the matching `llvm.memcpy.p<dst>.p<src>.i<bits>`.
+///
+/// MIR's count is measured in pointee elements, while LLVM's memcpy intrinsic
+/// expects bytes. The pre-conversion destination pointer type still carries the
+/// MIR pointee, so use it to scale the count before emitting the call.
+///
+/// The intrinsic name is an overload: LLVM encodes each pointer's address
+/// space and the length width into it, and its verifier rejects a call whose
+/// argument types disagree with the name. Today every pointer reaching a
+/// `copy_nonoverlapping` is a Rust raw pointer, which cuda-oxide normalizes to
+/// the generic address space (an `addrspacecast` is inserted when the raw
+/// pointer is formed), so the operands are always `p0` and `i64`. We still
+/// derive the suffix from the real operand types rather than hardcoding
+/// `p0.p0.i64`: it matches how every other overloaded intrinsic is named here
+/// (`ctpop`, `fptosi.sat`, ...), and it keeps this lowering correct if raw
+/// pointers ever start carrying a non-generic address space.
+pub(crate) fn convert_memcpy(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    convert_mem_transfer(ctx, rewriter, op, operands_info, "memcpy")
+}
+
+/// Convert `mir.memmove` to the matching `llvm.memmove.p<dst>.p<src>.i<bits>`.
+///
+/// Identical to [`convert_memcpy`] except it emits the overlap-safe
+/// `llvm.memmove` intrinsic. `mir.memmove` backs `core::intrinsics::copy`
+/// (`ptr::copy`); `mir.memcpy` backs the non-overlapping variant.
+pub(crate) fn convert_memmove(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    operands_info: &OperandsInfo,
+) -> Result<()> {
+    convert_mem_transfer(ctx, rewriter, op, operands_info, "memmove")
+}
+
+/// Shared lowering for `mir.memcpy` / `mir.memmove`. `intrinsic_base` selects
+/// the LLVM intrinsic family ("memcpy" or "memmove"); both share the same
+/// `(dst, src, len_bytes, isvolatile)` signature and element->byte count scaling.
+///
+/// The element type comes from the op's own `elem_type` attribute, stamped
+/// at build time from dst's pointer type. Operand type history is not
+/// usable here: a kind-only `mir.cast` lowers to a plain value forwarding,
+/// history does not follow that edge, and a stale hit would scale the byte
+/// count by the wrong element size.
+fn convert_mem_transfer(
+    ctx: &mut Context,
+    rewriter: &mut DialectConversionRewriter,
+    op: Ptr<Operation>,
+    _operands_info: &OperandsInfo,
+    intrinsic_base: &str,
+) -> Result<()> {
+    let operands: Vec<_> = op.deref(ctx).operands().collect();
+    let (dst, src, count) = match operands.as_slice() {
+        [dst, src, count] => (*dst, *src, *count),
+        _ => {
+            return pliron::input_err_noloc!(
+                "{intrinsic_base} operation requires exactly 3 operands"
+            );
+        }
+    };
+
+    let pointee = {
+        let op_ref = op.deref(ctx);
+        op_ref
+            .attributes
+            .get::<pliron::builtin::attributes::TypeAttr>(
+                &format!("{intrinsic_base}_elem_type").try_into().unwrap(),
+            )
+            .map(|attr| attr.get_type(ctx))
+            .ok_or_else(|| {
+                pliron::create_error!(
+                    op_ref.loc(),
+                    pliron::result::ErrorKind::VerificationFailed,
+                    pliron::result::StringError(format!(
+                        "mir.{intrinsic_base} missing its elem_type attribute; \
+                         byte count has no fact to derive from"
+                    ))
+                )
+            })?
+    };
+    // Byte-count policy: exact or error, never guessed. rustc's stride of the
+    // stamped MIR elem type is the primary fact; the converted LLVM type's
+    // natural layout is the fallback.
+    let elem_size = match mir_element_stride(ctx, pointee) {
+        Some(stride) => stride,
+        None => {
+            let elem_ty = convert_type(ctx, pointee).map_err(anyhow_to_pliron)?;
+            match llvm_type_size_align(ctx, elem_ty) {
+                Some((size, _)) => size,
+                None => {
+                    let type_display = pointee.deref(ctx).disp(ctx).to_string();
+                    return Err(pliron::create_error!(
+                        op.deref(ctx).loc(),
+                        pliron::result::ErrorKind::VerificationFailed,
+                        pliron::result::StringError(format!(
+                            "mir.{intrinsic_base} element type `{type_display}` has no exact \
+                             byte size; refusing to guess the copy length"
+                        ))
+                    ));
+                }
+            }
+        }
+    };
+
+    let bytes = if elem_size == 1 {
+        count
+    } else {
+        let count_ty = count.get_type(ctx);
+        let bits = count_ty
+            .deref(ctx)
+            .downcast_ref::<IntegerType>()
+            .map(|ty| ty.width())
+            .unwrap_or(64);
+        let count_int_ty = IntegerType::get(ctx, bits, Signedness::Signless);
+        let size_attr: AttrObj = IntegerAttr::new(
+            count_int_ty,
+            APInt::from_u64(
+                elem_size,
+                std::num::NonZeroUsize::new(bits as usize).unwrap(),
+            ),
+        )
+        .into();
+        let size_const = llvm::ConstantOp::new(ctx, size_attr);
+        let size_val = size_const.get_operation().deref(ctx).get_result(0);
+        rewriter.insert_operation(ctx, size_const.get_operation());
+
+        let flags = IntegerOverflowFlagsAttr::default();
+        let mul = llvm::MulOp::new_with_overflow_flag(ctx, count, size_val, flags);
+        rewriter.insert_operation(ctx, mul.get_operation());
+        mul.get_operation().deref(ctx).get_result(0)
+    };
+
+    let i1_ty = IntegerType::get(ctx, 1, Signedness::Signless);
+    let false_attr: AttrObj = IntegerAttr::new(
+        i1_ty,
+        APInt::from_u64(0, std::num::NonZeroUsize::new(1).unwrap()),
+    )
+    .into();
+    let volatile = llvm::ConstantOp::new(ctx, false_attr);
+    rewriter.insert_operation(ctx, volatile.get_operation());
+    let volatile_val = volatile.get_operation().deref(ctx).get_result(0);
+
+    let void_ty = VoidType::get(ctx);
+    let func_ty = FuncType::get(
+        ctx,
+        void_ty.into(),
+        vec![
+            dst.get_type(ctx),
+            src.get_type(ctx),
+            bytes.get_type(ctx),
+            volatile_val.get_type(ctx),
+        ],
+        false,
+    );
+    let parent_block = op.deref(ctx).get_parent_block().ok_or_else(|| {
+        pliron::create_error!(
+            op.deref(ctx).loc(),
+            pliron::result::ErrorKind::VerificationFailed,
+            pliron::result::StringError(format!("{intrinsic_base} operation has no parent block"))
+        )
+    })?;
+    // Derive the overload suffix from the real (already type-converted)
+    // operands so the name can never disagree with the argument types.
+    let dst_ty = dst.get_type(ctx);
+    let dst_as = dst_ty
+        .deref(ctx)
+        .downcast_ref::<llvm_export::types::PointerType>()
+        .map(|pt| pt.address_space())
+        .unwrap_or(0);
+    let src_ty = src.get_type(ctx);
+    let src_as = src_ty
+        .deref(ctx)
+        .downcast_ref::<llvm_export::types::PointerType>()
+        .map(|pt| pt.address_space())
+        .unwrap_or(0);
+    let len_bits = bytes
+        .get_type(ctx)
+        .deref(ctx)
+        .downcast_ref::<IntegerType>()
+        .map(|t| t.width())
+        .unwrap_or(64);
+    let intrinsic_name = format!("llvm_{intrinsic_base}_p{dst_as}_p{src_as}_i{len_bits}");
+    helpers::ensure_intrinsic_declared(ctx, parent_block, &intrinsic_name, func_ty)
+        .map_err(anyhow_to_pliron)?;
+
+    let callee: Identifier = intrinsic_name.as_str().try_into().map_err(|e| {
+        pliron::create_error!(
+            op.deref(ctx).loc(),
+            pliron::result::ErrorKind::VerificationFailed,
+            pliron::result::StringError(format!("Invalid memcpy intrinsic name: {e:?}"))
+        )
+    })?;
+    let call = llvm::CallOp::new(
+        ctx,
+        CallOpCallable::Direct(callee),
+        func_ty,
+        vec![dst, src, bytes, volatile_val],
+    );
+    crate::convert::preserve_location(ctx, op, call.get_operation());
+    rewriter.insert_operation(ctx, call.get_operation());
+    rewriter.erase_operation(ctx, op);
+    Ok(())
+}
diff --git a/crates/mir-lower/src/convert/types.rs b/crates/mir-lower/src/convert/types.rs
deleted file mode 100644
index 79aef815d8..0000000000
--- a/crates/mir-lower/src/convert/types.rs
+++ /dev/null
@@ -1,5845 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-//! Type conversion from `dialect-mir` types to LLVM dialect types.
-//!
-//! This module handles the translation of `dialect-mir` type representations
-//! to their LLVM dialect equivalents. Type conversion is foundational to
-//! the lowering pass—most operation converters depend on it.
-//!
-//! # Overview
-//!
-//! `dialect-mir` types are high-level, Rust-like types that preserve semantic
-//! information (signedness, slice semantics, etc.). LLVM dialect types are
-//! lower-level and match LLVM IR types directly.
-//!
-//! # Type Mapping Table
-//!
-//! | `dialect-mir` Type              | LLVM dialect Type                 | Notes                       |
-//! |---------------------------------|-----------------------------------|-----------------------------|
-//! | `IntegerType` (signed/unsigned) | `IntegerType` (signless)          | Width preserved             |
-//! | `MirFP16Type`                   | `HalfType`                        | Rust `f16` → LLVM `half`    |
-//! | `FP32Type`, `FP64Type`          | Same (builtin)                    | Pass-through                |
-//! | `MirPtrType`                    | `PointerType`                     | Address space preserved     |
-//! | `MirSliceType`                  | `StructType { ptr, i64 }`         | Fat pointer                 |
-//! | `MirDisjointSliceType`          | `StructType { ptr, i64 }`         | Same as slice               |
-//! | `MirTupleType`                  | `StructType`                      | Empty tuple → empty struct  |
-//! | `MirStructType`                 | `StructType`                      | Fields recursively converted|
-//! | `MirUnionType`                  | Aligned shared-storage struct    | All fields start at byte zero|
-//! | `MirEnumType`                   | `StructType` (rustc byte layout)  | See "Enum Type Representation" |
-//! | `ArrayType`                     | `ArrayType`                       | Element type converted      |
-//! | `VectorType`                    | `VectorType`                      | Element type converted      |
-//!
-//! # Signedness Handling
-//!
-//! LLVM IR integers are signless—the signedness is encoded in the operations
-//! that use them (e.g., `sdiv` vs `udiv`). During type conversion:
-//!
-//! - Signed/unsigned MIR integers → signless LLVM integers
-//! - The original signedness is preserved in operations (see `arithmetic.rs`)
-//!
-//! # Address Space Handling
-//!
-//! GPU memory uses address spaces to distinguish memory types:
-//!
-//! | Address Space | Memory Type | Usage                     |
-//! |---------------|-------------|---------------------------|
-//! | 0             | Generic     | Can point to any memory   |
-//! | 1             | Global      | Device memory (VRAM)      |
-//! | 3             | Shared      | Per-block shared memory   |
-//! | 4             | Constant    | Read-only device memory   |
-//! | 5             | Local       | Per-thread stack/spill    |
-//!
-//! Pointer address spaces are preserved through conversion. Slice types use
-//! generic address space (0) because they can point to any memory type.
-//!
-//! # Slice Type Representation
-//!
-//! Rust slices (`&[T]`) are represented as fat pointers in LLVM:
-//!
-//! ```text
-//! MIR: MirSliceType<f32>
-//! LLVM: struct { ptr, i64 }  ; pointer + length
-//! ```
-//!
-//! This matches the Rust ABI for slices passed by value.
-//!
-//! # Enum Type Representation
-//!
-//! A Rust enum is one tag plus the payload of whichever variant is
-//! alive; all variants share the same bytes. We build an LLVM struct
-//! that puts the tag and every payload field at the exact byte position
-//! rustc chose, inserting `[N x i8]` filler for the gaps:
-//!
-//! ```text
-//! #[repr(u32)] enum E { A(u32), B(f32), C }   // rustc: 8 bytes,
-//!                                             // tag at 0, payloads at 4
-//! LLVM: { i32, i32 }   ; slot 0 = tag, slot 1 = A's payload
-//!                      ; B's f32 also lives at byte 4 but has a
-//!                      ; different type, so it is read/written through
-//!                      ; memory instead of owning a slot
-//! ```
-//!
-//! Because the bytes match rustc exactly, enum data can cross the
-//! host/device boundary safely. The tag slot stores the variant's
-//! DECLARED discriminant value (`enum E { A = 7 }` stores 7), not its
-//! position. See `build_enum_slot_map` in this module for the full
-//! story.
-//!
-//! # Function Type Conversion
-//!
-//! Function types undergo ABI transformations:
-//!
-//! - Slice arguments are flattened to `(ptr, len)` pairs
-//! - Struct arguments are flattened to individual fields
-//! - Empty tuple return type becomes void
-//!
-//! This matches the C ABI for GPU kernels.
-
-use dialect_mir::types::{
-    EnumCarrierKind, EnumLayoutKind, MirArrayType, MirDisjointSliceType, MirEnumType, MirFP16Type,
-    MirPtrType, MirSliceType, MirStructType, MirTupleType, MirUnionType,
-};
-use llvm_export::types as llvm_types;
-use llvm_export::types::PointerTypeExt;
-use pliron::builtin::type_interfaces::{FloatTypeInterface, FunctionTypeInterface};
-use pliron::builtin::types::{FP32Type, FP64Type, FunctionType, IntegerType, Signedness};
-use pliron::context::{Context, Ptr};
-use pliron::operation::Operation;
-use pliron::r#type::{TypeHandle, type_cast};
-
-use super::enum_payload_storage::{
-    MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES, enum_payload_storage_type,
-};
-use super::target_stable_storage::{StorageRewriteOptions, target_stable_storage_type};
-use crate::type_conversion_interface::MirTypeConversion;
-
-// =============================================================================
-// Kernel-Boundary Detection
-// =============================================================================
-
-/// Identifier of the attribute that marks a `MirFuncOp` / `llvm.func` as a
-/// GPU kernel entry point.
-///
-/// Kept as a function (rather than a `const`) because pliron `Identifier`
-/// construction needs the `try_into()` fallible path.
-fn gpu_kernel_attr() -> pliron::identifier::Identifier {
-    "gpu_kernel".try_into().expect("static identifier")
-}
-
-/// Returns `true` when `op` carries the `gpu_kernel` attribute.
-///
-/// The kernel-entry ABI differs from internal device-function ABI: at
-/// kernel boundaries, aggregate parameters (structs, closures) are passed
-/// as a single byval value to match what the host pushes via
-/// `cuLaunchKernel`. Internal call sites still flatten aggregates the
-/// same way they always did. This helper is the single source of truth
-/// for that branch and is consumed by both [`convert_function_type`] and
-/// the entry-block prologue in `lowering.rs`.
-pub fn is_kernel_func(ctx: &Context, op: Ptr<Operation>) -> bool {
-    op.deref(ctx)
-        .attributes
-        .get::<pliron::builtin::attributes::StringAttr>(&gpu_kernel_attr())
-        .is_some()
-}
-
-// =============================================================================
-// Zero-Sized Type (ZST) Detection
-// =============================================================================
-
-/// Check if a type is zero-sized (empty struct).
-///
-/// Zero-sized types include:
-/// - Empty structs `struct {}`
-/// - PhantomData markers (which become empty structs in MIR)
-/// - Structs where all fields are themselves zero-sized
-///
-/// # Why This Matters
-///
-/// LLVM's NVPTX backend doesn't support empty struct types in function
-/// signatures. We strip these during type conversion to avoid:
-/// `LLVM ERROR: Empty parameter types are not supported`
-///
-/// # Background
-///
-/// Rust's `#[inline(always)]` attribute is stored in `codegen_fn_attrs`, which
-/// is not exposed through the stable_mir API. Since we intercept MIR and generate
-/// our own LLVM IR, we don't propagate inline hints. When LLVM decides not to
-/// inline a function, the empty struct parameters/returns cause NVPTX to crash.
-///
-/// By stripping ZSTs at the LLVM type level, we avoid this issue regardless of
-/// inlining decisions.
-pub fn is_zero_sized_type(ctx: &Context, ty: TypeHandle) -> bool {
-    if let Some(array_ty) = ty.deref(ctx).downcast_ref::<llvm_types::ArrayType>() {
-        return array_ty.size() == 0 || is_zero_sized_type(ctx, array_ty.elem_type());
-    }
-
-    // Check if LLVM StructType with zero fields
-    if let Some(struct_ty) = ty.deref(ctx).downcast_ref::<llvm_types::StructType>() {
-        let num_fields = struct_ty.num_fields();
-        if num_fields == 0 {
-            return true;
-        }
-        // Also check if ALL fields are zero-sized (nested PhantomData)
-        return struct_ty.fields().all(|f| is_zero_sized_type(ctx, f));
-    }
-    false
-}
-
-// =============================================================================
-// Type Conversion
-// =============================================================================
-
-/// Convert a `dialect-mir` type to its LLVM dialect equivalent.
-///
-/// Dispatches via `MirTypeConversion` type interface — each supported type
-/// registers a converter function pointer through `#[type_interface_impl]`
-/// in [`super::type_interface_impls`].
-///
-/// The function-pointer indirection avoids a borrow-checker conflict:
-/// `type_cast` borrows `ctx` immutably, but conversion needs `&mut ctx`.
-/// We extract the `Copy` function pointer, drop the borrow, then call it.
-pub fn convert_type(ctx: &mut Context, ty: TypeHandle) -> Result<TypeHandle, anyhow::Error> {
-    // Phase 1: extract a Copy function pointer while ctx is immutably borrowed.
-    let converter_fn = {
-        let ty_ref = ty.deref(ctx);
-        type_cast::<dyn MirTypeConversion>(&*ty_ref).map(|conv| conv.converter())
-    };
-    // Phase 2: borrow dropped — ctx is free for &mut.
-    if let Some(conv_fn) = converter_fn {
-        return conv_fn(ty, ctx);
-    }
-
-    let type_display = ty.deref(ctx).disp(ctx).to_string();
-    Err(anyhow::anyhow!(
-        "Unsupported type conversion: {}\n\
-         Supported: integers, fp32, fp64, pointers, slices, tuples, structs, enums, arrays, vectors.",
-        type_display
-    ))
-}
-
-/// Return the declaration index and type of the single non-ZST field of a
-/// rustc-proven transparent scalar struct.
-///
-/// The importer marks the outer ABI from rustc rather than inferring it from
-/// source field count. We still validate the MIR shape here so malformed or
-/// hand-written dialect input cannot turn an arbitrary aggregate into a scalar
-/// ABI value.
-fn transparent_scalar_field_with_index(
-    ctx: &mut Context,
-    struct_ty: TypeHandle,
-) -> Result<(usize, TypeHandle), anyhow::Error> {
-    let (name, field_types, mem_to_decl, is_transparent_scalar) = {
-        let ty_ref = struct_ty.deref(ctx);
-        let s = ty_ref
-            .downcast_ref::<MirStructType>()
-            .ok_or_else(|| anyhow::anyhow!("transparent scalar ABI requires a MirStructType"))?;
-        (
-            s.name.clone(),
-            s.field_types.clone(),
-            s.memory_order(),
-            s.is_transparent_scalar(),
-        )
-    };
-
-    if !is_transparent_scalar {
-        return Err(anyhow::anyhow!(
-            "struct `{}` is not marked as a transparent scalar",
-            name
-        ));
-    }
-
-    let mut scalar_field = None;
-    for decl_idx in mem_to_decl {
-        let field_ty = field_types[decl_idx];
-        let converted = convert_type(ctx, field_ty)?;
-        if is_zero_sized_type(ctx, converted) {
-            continue;
-        }
-        if scalar_field.replace((decl_idx, field_ty)).is_some() {
-            return Err(anyhow::anyhow!(
-                "transparent scalar struct `{}` has more than one non-ZST field",
-                name
-            ));
-        }
-    }
-
-    scalar_field
-        .ok_or_else(|| anyhow::anyhow!("transparent scalar struct `{}` has no non-ZST field", name))
-}
-
-/// Return the single non-ZST field of a rustc-proven transparent scalar struct.
-pub(crate) fn transparent_scalar_field(
-    ctx: &mut Context,
-    struct_ty: TypeHandle,
-) -> Result<TypeHandle, anyhow::Error> {
-    Ok(transparent_scalar_field_with_index(ctx, struct_ty)?.1)
-}
-
-/// One aggregate layer traversed when a transparent scalar wrapper crosses an
-/// ABI boundary. `field_slot` is the LLVM struct slot containing the next
-/// nested wrapper or the final scalar.
-#[derive(Clone, Copy, Debug)]
-pub(crate) struct TransparentScalarLayer {
-    pub llvm_struct_ty: TypeHandle,
-    pub field_slot: u32,
-}
-
-/// Complete ABI projection for a rustc-proven transparent scalar wrapper.
-///
-/// `layers` are ordered outermost to innermost. A return lowers by extracting
-/// those slots in order; a call result is rebuilt by inserting the scalar into
-/// the same layers in reverse order.
-#[derive(Clone, Debug)]
-pub(crate) struct TransparentScalarAbiInfo {
-    pub scalar_ty: TypeHandle,
-    pub layers: Vec<TransparentScalarLayer>,
-}
-
-/// Build the scalar ABI projection, including the exact LLVM slot used at every
-/// wrapper layer.
-///
-/// Slot indices come from [`build_struct_slot_map`], so ZST markers, explicit
-/// padding, and rustc memory order cannot make the return/call paths disagree
-/// with ordinary aggregate conversion.
-pub(crate) fn transparent_scalar_abi_info(
-    ctx: &mut Context,
-    struct_ty: TypeHandle,
-) -> Result<TransparentScalarAbiInfo, anyhow::Error> {
-    let mut current = struct_ty;
-    let mut layers = Vec::new();
-
-    loop {
-        let (decl_idx, field_ty) = transparent_scalar_field_with_index(ctx, current)?;
-        let layout = {
-            let ty_ref = current.deref(ctx);
-            let s = ty_ref.downcast_ref::<MirStructType>().ok_or_else(|| {
-                anyhow::anyhow!("transparent scalar ABI requires a MirStructType")
-            })?;
-            StructLayoutInfo::of_struct(s)
-        };
-        let map = build_struct_slot_map(ctx, &layout)?;
-        let field_slot = map.decl_to_llvm[decl_idx].ok_or_else(|| {
-            anyhow::anyhow!(
-                "transparent scalar field {} unexpectedly lowered as a ZST",
-                decl_idx
-            )
-        })?;
-        layers.push(TransparentScalarLayer {
-            llvm_struct_ty: map.llvm_struct_ty,
-            field_slot,
-        });
-
-        let nested_transparent = {
-            let field_ref = field_ty.deref(ctx);
-            field_ref
-                .downcast_ref::<MirStructType>()
-                .is_some_and(MirStructType::is_transparent_scalar)
-        };
-        if nested_transparent {
-            current = field_ty;
-            continue;
-        }
-
-        let scalar_ty = convert_type(ctx, field_ty)?;
-        if is_zero_sized_type(ctx, scalar_ty) {
-            return Err(anyhow::anyhow!(
-                "transparent scalar ABI resolved to a zero-sized field"
-            ));
-        }
-        return Ok(TransparentScalarAbiInfo { scalar_ty, layers });
-    }
-}
-
-/// LLVM ABI type for a rustc-proven transparent scalar struct.
-///
-/// Transparent wrappers can nest (`Outer(Inner(u32))`). rustc still reports
-/// the outer ADT as one scalar, so recurse through transparent scalar fields
-/// until reaching the actual scalar/pointer representation.
-pub(crate) fn transparent_scalar_llvm_type(
-    ctx: &mut Context,
-    struct_ty: TypeHandle,
-) -> Result<TypeHandle, anyhow::Error> {
-    Ok(transparent_scalar_abi_info(ctx, struct_ty)?.scalar_ty)
-}
-
-/// Target-stable ABI projection for packed aggregates containing AS3 leaves
-/// across the internal device return boundary.
-///
-/// The function body continues to use the semantic packed LLVM struct with
-/// shared pointers. Only the physical return value recursively replaces AS3
-/// leaves with generic pointers, whose width is stable across the legacy/PTX
-/// and modern NVVM data layouts.
-#[derive(Clone, Copy, Debug)]
-pub(crate) struct PackedSharedInternalAbiInfo {
-    pub semantic_ty: TypeHandle,
-    pub storage_ty: TypeHandle,
-}
-
-/// Maximum number of shared-pointer leaves introduced by fixed-array expansion
-/// in one packed-AS3 internal return carrier.
-///
-/// Struct/tuple nesting and direct pointer leaves remain proportional to source
-/// structure. Arrays can encode an arbitrarily large number of per-element
-/// extract/cast/insert sequences compactly, so only array-expanded AS3 leaves
-/// count against this code-shape budget.
-pub(crate) const MAX_PACKED_SHARED_INTERNAL_ABI_ARRAY_REWRITE_LEAVES: u64 = 16;
-
-/// Whether a MIR type converts to a zero-sized LLVM type.
-///
-/// MIR-side mirror of [`is_zero_sized_type`]: zero-length arrays, arrays of
-/// zero-sized elements, and structs/tuples whose fields are all zero-sized
-/// (including empty ones such as `PhantomData`) vanish at the LLVM level and
-/// must not affect ABI-lane classification.
-fn mir_type_is_zero_sized(ctx: &Context, ty: TypeHandle) -> bool {
-    let ty_ref = ty.deref(ctx);
-    if let Some(array_ty) = ty_ref.downcast_ref::<MirArrayType>() {
-        return array_ty.size() == 0 || mir_type_is_zero_sized(ctx, array_ty.element_type());
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
-        return struct_ty
-            .field_types
-            .iter()
-            .all(|field| mir_type_is_zero_sized(ctx, *field));
-    }
-    if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
-        return tuple_ty
-            .get_types()
-            .iter()
-            .all(|field| mir_type_is_zero_sized(ctx, *field));
-    }
-    false
-}
-
-/// Whether a MIR value shape belongs to the recursive packed-AS3 ABI lane.
-///
-/// Structs, tuples, and fixed arrays may nest recursively and may contain any
-/// number of scalar pointer leaves. Zero-sized fields are skipped, matching the
-/// post-conversion field scan this predicate replaced. The array-specific
-/// expansion budget is enforced after conversion from the storage rewrite's
-/// exact AS3 leaf count. Vectors and unrelated aggregate kinds remain
-/// deliberately fail-closed.
-fn packed_shared_internal_abi_mir_shape_is_supported(ctx: &Context, mir_ty: TypeHandle) -> bool {
-    let children = {
-        let ty_ref = mir_ty.deref(ctx);
-        if ty_ref.is::<IntegerType>()
-            || ty_ref.is::<MirFP16Type>()
-            || ty_ref.is::<llvm_types::HalfType>()
-            || ty_ref.is::<FP32Type>()
-            || ty_ref.is::<FP64Type>()
-            || ty_ref.is::<MirPtrType>()
-            || ty_ref.is::<llvm_types::PointerType>()
-        {
-            return true;
-        }
-        if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
-            Some(struct_ty.field_types.clone())
-        } else if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
-            Some(tuple_ty.get_types().to_vec())
-        } else {
-            ty_ref
-                .downcast_ref::<MirArrayType>()
-                .map(|array_ty| vec![array_ty.element_type()])
-        }
-    };
-
-    children.is_some_and(|children| {
-        children.into_iter().all(|child| {
-            mir_type_is_zero_sized(ctx, child)
-                || packed_shared_internal_abi_mir_shape_is_supported(ctx, child)
-        })
-    })
-}
-
-/// Recognize a recursive packed-AS3 internal ABI shape.
-///
-/// The root must remain a byte-faithful packed struct. Nested structs/tuples,
-/// multiple AS3 leaves, and bounded fixed arrays are admitted. Vectors and
-/// unrelated aggregate kinds remain out of scope. The target-stable storage
-/// utility owns the recursive AS3 -> generic rewrite and this classifier only
-/// decides which semantic shapes may use it.
-pub(crate) fn packed_shared_internal_abi_info(
-    ctx: &mut Context,
-    mir_ty: TypeHandle,
-) -> Result<Option<PackedSharedInternalAbiInfo>, anyhow::Error> {
-    let layout = {
-        let ty_ref = mir_ty.deref(ctx);
-        let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() else {
-            return Ok(None);
-        };
-        StructLayoutInfo::of_struct(struct_ty)
-    };
-
-    if !packed_shared_internal_abi_mir_shape_is_supported(ctx, mir_ty) {
-        return Ok(None);
-    }
-
-    let map = build_struct_slot_map(ctx, &layout)?;
-    if !map.by_value_layout_faithful {
-        return Ok(None);
-    }
-    let is_packed = map
-        .llvm_struct_ty
-        .deref(ctx)
-        .downcast_ref::<llvm_types::StructType>()
-        .is_some_and(|struct_ty| struct_ty.layout() == llvm_types::StructLayout::Packed);
-    if !is_packed {
-        return Ok(None);
-    }
-
-    let rewrite = target_stable_storage_type(
-        ctx,
-        map.llvm_struct_ty,
-        StorageRewriteOptions {
-            canonicalize_bool: false,
-        },
-        "packed shared internal ABI",
-    )?;
-    if rewrite.shared_pointer_leaves == 0
-        || rewrite.array_shared_pointer_leaves > MAX_PACKED_SHARED_INTERNAL_ABI_ARRAY_REWRITE_LEAVES
-    {
-        return Ok(None);
-    }
-    let Some((storage_size, _)) = llvm_type_size_align(ctx, rewrite.ty) else {
-        return Ok(None);
-    };
-    if layout.total_size > 0 && storage_size != layout.total_size {
-        return Ok(None);
-    }
-
-    Ok(Some(PackedSharedInternalAbiInfo {
-        semantic_ty: map.llvm_struct_ty,
-        storage_ty: rewrite.ty,
-    }))
-}
-
-/// Convert a type that crosses a function boundary as one LLVM value.
-///
-/// A struct with a natural-layout divergence is legal by value only when
-/// [`build_struct_slot_map`] proved that a sequential packed LLVM struct
-/// reproduces rustc's offsets and size. This keeps overlapping/union-like
-/// legacy struct models fail-closed while allowing real `repr(packed)` values.
-/// Packed values containing shared-memory pointers remain target-dependent
-/// because AS3 pointer width differs between modern NVVM and PTX/legacy modes.
-fn convert_by_value_abi_type(
-    ctx: &mut Context,
-    mir_ty: TypeHandle,
-    role: &str,
-) -> Result<TypeHandle, anyhow::Error> {
-    let layout = {
-        let ty_ref = mir_ty.deref(ctx);
-        ty_ref
-            .downcast_ref::<MirStructType>()
-            .map(StructLayoutInfo::of_struct)
-    };
-    let llvm_ty = if let Some(layout) = layout {
-        let map = build_struct_slot_map(ctx, &layout)?;
-        if !map.by_value_layout_faithful {
-            return Err(anyhow::anyhow!(
-                "{} has a rustc struct layout that cannot be represented by an LLVM struct value",
-                role
-            ));
-        }
-        map.llvm_struct_ty
-    } else {
-        convert_type(ctx, mir_ty)?
-    };
-
-    if llvm_packed_struct_contains_pointer_in_address_space(
-        ctx,
-        llvm_ty,
-        llvm_types::address_space::SHARED,
-    ) {
-        return Err(anyhow::anyhow!(
-            "{} contains a packed aggregate with a target-dependent shared-memory pointer",
-            role
-        ));
-    }
-
-    Ok(llvm_ty)
-}
-
-/// Convert a MIR function type to an LLVM function type.
-///
-/// This handles the ABI-level transformations required for GPU kernels.
-/// The transformations ensure that the generated LLVM IR matches the
-/// C ABI expected by the CUDA runtime.
-///
-/// # ABI Transformations
-///
-/// ## Argument Flattening
-///
-/// Aggregate types are flattened to primitive types:
-///
-/// ```text
-/// MIR:  fn kernel(slice: &[f32], point: Point)
-/// LLVM: fn internal_fn(ptr: !ptr, len: i64, x: f32, y: f32)
-/// ```
-///
-/// | MIR Argument            | Internal call ABI       | Kernel-entry ABI       |
-/// |-------------------------|-------------------------|------------------------|
-/// | `&[T]`                  | `(ptr, i64)`            | `(ptr, i64)`           |
-/// | `DisjointSlice<T>`      | `(ptr, i64)`            | `(ptr, i64)`           |
-/// | `struct { a: A, b: B }` | `(a: A', b: B')`        | one byval `{A', B'}`   |
-/// | `repr(transparent)` scalar ADT | underlying scalar      | underlying scalar      |
-/// | closure with N captures | N separate field args   | one byval struct       |
-/// | Other                   | Converted type          | Converted type         |
-///
-/// Slices keep their `(ptr, len)` flattening on both sides because the
-/// host-side launch helpers push the pointer and length as two driver
-/// args. Structs and closures are unflattened only at kernel boundaries
-/// because the host pushes them as a single scalar — see
-/// `cuda_host::push_kernel_scalar`. The exception is a rustc-proven
-/// `#[repr(transparent)]` `ValueAbi::Scalar` struct: its single non-ZST
-/// field is the kernel parameter, matching the source type's transparent ABI.
-/// Internal device-side call sites stay flattened: caller and callee are both
-/// inside this backend, so the ABI is private and there is no host to disagree
-/// with.
-///
-/// ## Return Type Handling
-///
-/// - Empty tuple `()` becomes `void`
-/// - Empty struct `struct {}` becomes `void`
-/// - Rustc-proven `repr(transparent)` scalar ADTs return the underlying scalar
-/// - Other types are converted normally
-///
-/// # Arguments
-///
-/// * `ctx` - The pliron context
-/// * `func_type` - The MIR function type to convert
-/// * `is_kernel_entry` - When `true`, treat aggregate (non-slice) params
-///   as single byval values to match the host-side push ABI. When `false`,
-///   keep the existing internal device-fn ABI that flattens struct fields
-///   into individual scalars.
-///
-/// # Returns
-///
-/// The equivalent LLVM function type with ABI transformations applied.
-///
-/// # Example
-///
-/// ```text
-/// MIR:  fn foo(a: &[f32], b: i32) -> f32
-/// LLVM: fn foo(ptr, i64, i32) -> f32
-///
-/// MIR:  fn bar() -> ()
-/// LLVM: fn bar() -> void
-/// ```
-///
-/// # Note
-///
-/// At internal device-function boundaries the struct flattening must be
-/// reversed in the entry block. At kernel-entry boundaries ordinary structs
-/// arrive as one byval aggregate, while rustc-proven transparent scalar
-/// wrappers arrive as their single non-ZST scalar field and must be rebuilt.
-/// See `lowering.rs::build_entry_prologue` for the reconstruction paths.
-pub fn convert_function_type(
-    ctx: &mut Context,
-    func_type: pliron::r#type::TypedHandle<FunctionType>,
-    is_kernel_entry: bool,
-) -> Result<pliron::r#type::TypedHandle<llvm_types::FuncType>, anyhow::Error> {
-    // Extract input/output types before mutating context
-    let (inputs_ptr, results_ptr) = {
-        let func_ty_ref = func_type.deref(ctx);
-        let interface = type_cast::<dyn FunctionTypeInterface>(&*func_ty_ref)
-            .ok_or_else(|| anyhow::anyhow!("Type does not implement FunctionTypeInterface"))?;
-        (interface.arg_types(), interface.res_types())
-    };
-
-    // Convert inputs, flattening slice/struct types for ABI compatibility.
-    // Slices flatten on both ABIs; structs flatten only on the internal
-    // device-fn ABI.
-    let mut inputs = Vec::new();
-    let inputs_vec: Vec<_> = inputs_ptr.to_vec();
-
-    for t in inputs_vec {
-        // Determine what kind of flattening this type needs
-        // Extract all info first, then drop the borrow
-        enum FlattenKind {
-            /// `{ ptr, len }`, then one parameter per index-space layout field.
-            Slice {
-                space_tys: Vec<TypeHandle>,
-            },
-            Struct {
-                field_types: Vec<TypeHandle>,
-                mem_to_decl: Vec<usize>,
-            },
-            TransparentScalar(TypeHandle),
-            None,
-        }
-
-        let flatten_kind = {
-            let ty_ref = t.deref(ctx);
-            if ty_ref.is::<MirSliceType>() {
-                FlattenKind::Slice {
-                    space_tys: Vec::new(),
-                }
-            } else if let Some(slice_ty) = ty_ref.downcast_ref::<MirDisjointSliceType>() {
-                FlattenKind::Slice {
-                    space_tys: slice_ty.space_tys.clone(),
-                }
-            } else if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
-                if is_kernel_entry && struct_ty.is_transparent_scalar() {
-                    // rustc proves that this `repr(transparent)` ADT has a
-                    // scalar ABI. Emit exactly its one non-ZST field as the
-                    // kernel parameter instead of an aggregate `.b8[]` param.
-                    FlattenKind::TransparentScalar(t)
-                } else if is_kernel_entry {
-                    // Ordinary kernel-boundary structs remain intact so the
-                    // host's single `push_kernel_scalar(&closure)` push
-                    // matches a single aggregate .param entry.
-                    FlattenKind::None
-                } else {
-                    FlattenKind::Struct {
-                        field_types: struct_ty.field_types.clone(),
-                        mem_to_decl: struct_ty.memory_order(),
-                    }
-                }
-            } else {
-                FlattenKind::None
-            }
-        };
-
-        match flatten_kind {
-            FlattenKind::Slice { space_tys } => {
-                let ptr_ty = llvm_types::PointerType::get_generic(ctx);
-                let len_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-                inputs.push(ptr_ty.into());
-                inputs.push(len_ty.into());
-                for space_ty in space_tys {
-                    let converted = convert_type(ctx, space_ty)?;
-                    // A zero-sized index-space field contributes no parameter,
-                    // as NVPTX has no empty `.param`.
-                    if !is_zero_sized_type(ctx, converted) {
-                        inputs.push(converted);
-                    }
-                }
-            }
-            FlattenKind::Struct {
-                field_types,
-                mem_to_decl,
-            } => {
-                // Flatten in MEMORY ORDER to match struct layout
-                for mem_idx in 0..field_types.len() {
-                    let decl_idx = mem_to_decl[mem_idx];
-                    let converted = convert_by_value_abi_type(
-                        ctx,
-                        field_types[decl_idx],
-                        "by-value function argument",
-                    )?;
-                    // Skip ZST fields - NVPTX can't handle empty params
-                    if !is_zero_sized_type(ctx, converted) {
-                        inputs.push(converted);
-                    }
-                }
-            }
-            FlattenKind::TransparentScalar(struct_ty) => {
-                inputs.push(transparent_scalar_llvm_type(ctx, struct_ty)?);
-            }
-            FlattenKind::None => {
-                let converted = convert_by_value_abi_type(ctx, t, "by-value function argument")?;
-                // Skip ZST args - NVPTX can't handle empty params
-                if !is_zero_sized_type(ctx, converted) {
-                    inputs.push(converted);
-                }
-            }
-        }
-    }
-
-    // Convert return type. A rustc-proven transparent scalar wrapper uses
-    // the underlying scalar at the function ABI boundary, while its body
-    // continues to use the ordinary converted aggregate representation.
-    let ret_ty = if results_ptr.is_empty() {
-        llvm_types::VoidType::get(ctx).into()
-    } else {
-        let mir_ret_ty = results_ptr[0];
-        let is_transparent_scalar = {
-            let ty_ref = mir_ret_ty.deref(ctx);
-            ty_ref
-                .downcast_ref::<MirStructType>()
-                .is_some_and(MirStructType::is_transparent_scalar)
-        };
-        let ty = if is_transparent_scalar {
-            transparent_scalar_llvm_type(ctx, mir_ret_ty)?
-        } else if !is_kernel_entry {
-            match packed_shared_internal_abi_info(ctx, mir_ret_ty)? {
-                Some(abi) => abi.storage_ty,
-                None => convert_by_value_abi_type(ctx, mir_ret_ty, "by-value function return")?,
-            }
-        } else {
-            convert_by_value_abi_type(ctx, mir_ret_ty, "by-value function return")?
-        };
-        // Check if zero-sized (empty struct or struct with only ZST fields).
-        if is_zero_sized_type(ctx, ty) {
-            llvm_types::VoidType::get(ctx).into()
-        } else {
-            ty
-        }
-    };
-
-    Ok(llvm_types::FuncType::get(ctx, ret_ty, inputs, false))
-}
-
-// =============================================================================
-// Struct Slot Mapping (single source of truth, issue #128)
-// =============================================================================
-
-/// Declaration-order layout facts for one MIR aggregate, in the exact form
-/// [`build_struct_slot_map`] consumes.
-///
-/// Extracting this owned carrier first (and dropping the `Ref` returned by
-/// `Ptr::deref`) keeps the borrow checker happy: the slot-map build needs
-/// `&mut Context` for type interning.
-pub(crate) struct StructLayoutInfo {
-    /// Field types in declaration order.
-    pub field_types: Vec<TypeHandle>,
-    /// Memory order: `mem_to_decl[mem_idx] = decl_idx`. Always full length
-    /// (identity when rustc did not reorder).
-    pub mem_to_decl: Vec<usize>,
-    /// Byte offset of each field in declaration order; empty when rustc
-    /// layout is unknown.
-    pub field_offsets: Vec<u64>,
-    /// Total size in bytes including trailing padding; 0 when unknown.
-    pub total_size: u64,
-}
-
-impl StructLayoutInfo {
-    /// Layout facts of a `MirStructType`.
-    pub(crate) fn of_struct(s: &MirStructType) -> Self {
-        StructLayoutInfo {
-            field_types: s.field_types.clone(),
-            mem_to_decl: s.memory_order(),
-            field_offsets: s.field_offsets().to_vec(),
-            total_size: s.total_size(),
-        }
-    }
-
-    /// Layout facts of a `MirTupleType`.
-    ///
-    /// Tuples translated from a rustc type carry rustc's exact layout
-    /// (offsets, memory order, size), which is consumed here identically to
-    /// structs, so reordered tuples like `(u32, &T)` lower byte-correctly.
-    /// Only synthetic layout-less tuples (the unit tuple, hand-built test
-    /// types) fall back to LLVM natural layout.
-    pub(crate) fn of_tuple(t: &MirTupleType) -> Self {
-        StructLayoutInfo {
-            field_types: t.get_types().to_vec(),
-            mem_to_decl: t.memory_order(),
-            field_offsets: t.field_offsets().to_vec(),
-            total_size: t.total_size(),
-        }
-    }
-}
-
-/// One lowered LLVM struct plus the value-level slot mapping into it.
-///
-/// [`build_struct_slot_map`] produces the struct type and the index map in
-/// the same walk, so every op that indexes into the struct (`insertvalue`,
-/// `extractvalue`, GEP, call-boundary flatten/reconstruct) shares the type
-/// converter's view of where each field landed. Computing the indices
-/// separately is how the issue #128 class of bug (indices that ignore the
-/// `[N x i8]` padding slots) happened.
-pub(crate) struct StructSlotMap {
-    /// The final LLVM struct type, including any `[N x i8]` padding slots.
-    pub llvm_struct_ty: TypeHandle,
-    /// `decl_to_llvm[decl_idx]` = LLVM slot of that declaration-order field;
-    /// `None` when the field is zero-sized and was stripped.
-    pub decl_to_llvm: Vec<Option<u32>>,
-    /// Converted LLVM type of each declaration-order field (ZSTs included).
-    pub field_llvm_types: Vec<TypeHandle>,
-    /// Natural (non-packed) LLVM byte offset of every slot of
-    /// `llvm_struct_ty`, padding slots included; `None` when some field type
-    /// cannot be sized ([`llvm_type_size_align`] declined).
-    pub natural_slot_offsets: Option<Vec<u64>>,
-    /// True when rustc's recorded byte layout cannot be represented by a
-    /// naturally laid-out LLVM struct: some field's natural slot offset differs
-    /// from rustc's byte offset, or the natural struct size differs from
-    /// rustc's total size. `repr(packed)` is the canonical case. Address-path
-    /// consumers retain this signal and the natural offsets so the #859
-    /// byte-GEP fallback stays stable for packed field projections.
-    pub layout_diverges: bool,
-    /// True when the selected LLVM struct representation reproduces rustc's
-    /// recorded field offsets and total size for by-value movement. Natural
-    /// layouts are faithful when they do not diverge; divergent layouts are
-    /// faithful only when a sequential LLVM packed struct can express them.
-    /// Overlapping/union-like legacy struct models therefore remain false.
-    pub by_value_layout_faithful: bool,
-}
-
-/// Whether a `MirStructType` value lowers to a byte-faithful LLVM struct:
-/// either its natural LLVM layout already matches rustc's offsets and total
-/// size, or the packed-with-explicit-padding representation reproduces them
-/// exactly.
-///
-/// Public only as a coupling oracle for mir-importer: its constant-promotion
-/// gate must never admit a struct layout whose converted storage falls back
-/// to a divergent natural layout, because a promoted constant's byte image
-/// would then disagree with every typed read through the converted struct.
-/// mir-importer asserts agreement against this function in its tests.
-pub fn struct_value_lowering_is_byte_faithful(
-    ctx: &mut Context,
-    struct_ty: TypeHandle,
-) -> Result<bool, anyhow::Error> {
-    let layout = {
-        let ty_ref = struct_ty.deref(ctx);
-        let mir_struct = ty_ref
-            .downcast_ref::<MirStructType>()
-            .ok_or_else(|| anyhow::anyhow!("expected a MirStructType"))?;
-        StructLayoutInfo::of_struct(mir_struct)
-    };
-    Ok(build_struct_slot_map(ctx, &layout)?.by_value_layout_faithful)
-}
-
-/// Lower a struct/tuple layout to its LLVM struct type and slot map.
-///
-/// When rustc layout is present (`field_offsets` non-empty and
-/// `total_size > 0`), fields are placed at their exact byte offsets with
-/// explicit `[N x i8]` padding slots in between, plus a trailing pad up to
-/// `total_size`. This makes the layout independent of LLVM's datalayout
-/// and so ABI-identical to what rustc computed on the host. For
-/// `struct Extreme { a: u8, b: i128 }` where rustc puts `b` at offset 0
-/// and `a` at offset 16 with total size 32, we build:
-///
-/// ```text
-/// { i128, i8, [15 x i8] }   ; slots:  b = 0, a = 1, pad = 2
-/// ```
-///
-/// Without rustc layout, fields are emitted in memory order with no
-/// padding. On both paths zero-sized fields (e.g. `PhantomData`) are
-/// stripped, because NVPTX rejects empty types; stripped fields get
-/// `None` in `decl_to_llvm`.
-///
-/// Malformed layout metadata (a `mem_to_decl` that is not a permutation,
-/// or an offsets vector of the wrong length) is rejected loudly: guessing
-/// here would scramble every downstream field access.
-pub(crate) fn build_struct_slot_map(
-    ctx: &mut Context,
-    layout: &StructLayoutInfo,
-) -> Result<StructSlotMap, anyhow::Error> {
-    let num_fields = layout.field_types.len();
-
-    if layout.mem_to_decl.len() != num_fields {
-        return Err(anyhow::anyhow!(
-            "struct slot map: memory order has {} entries but the struct has {} fields",
-            layout.mem_to_decl.len(),
-            num_fields
-        ));
-    }
-    let mut seen = vec![false; num_fields];
-    for &decl_idx in &layout.mem_to_decl {
-        if decl_idx >= num_fields || seen[decl_idx] {
-            return Err(anyhow::anyhow!(
-                "struct slot map: memory order {:?} is not a permutation of 0..{}",
-                layout.mem_to_decl,
-                num_fields
-            ));
-        }
-        seen[decl_idx] = true;
-    }
-    let has_explicit_layout = !layout.field_offsets.is_empty() && layout.total_size > 0;
-    if has_explicit_layout && layout.field_offsets.len() != num_fields {
-        return Err(anyhow::anyhow!(
-            "struct slot map: {} field offsets for {} fields",
-            layout.field_offsets.len(),
-            num_fields
-        ));
-    }
-
-    // Convert every field up front, in declaration order.
-    let mut field_llvm_types = Vec::with_capacity(num_fields);
-    for &field_ty in &layout.field_types {
-        field_llvm_types.push(convert_type(ctx, field_ty)?);
-    }
-
-    let mut llvm_fields: Vec<TypeHandle> = Vec::new();
-    let mut decl_to_llvm: Vec<Option<u32>> = vec![None; num_fields];
-    let mut current_offset: u64 = 0;
-
-    // Place fields in memory order.
-    for &decl_idx in &layout.mem_to_decl {
-        let llvm_ty = field_llvm_types[decl_idx];
-
-        // ZST fields are stripped: no slot, no offset advance (rustc gives
-        // them size 0).
-        if is_zero_sized_type(ctx, llvm_ty) {
-            continue;
-        }
-
-        if has_explicit_layout {
-            // Insert padding if needed to reach the rustc field offset.
-            let target_offset = layout.field_offsets[decl_idx];
-            if current_offset < target_offset {
-                let padding_ty = make_padding_type(ctx, target_offset - current_offset);
-                llvm_fields.push(padding_ty);
-                current_offset = target_offset;
-            }
-        }
-
-        decl_to_llvm[decl_idx] = Some(llvm_fields.len() as u32);
-        llvm_fields.push(llvm_ty);
-
-        if has_explicit_layout {
-            // Offset advance is exact or an error, never guessed. Prefer
-            // rustc's stored size for the field: nested aggregates carry
-            // interior/trailing padding the converted type cannot always
-            // reproduce, and a wrong advance here either forces interior
-            // padding where rustc has none or overshoots the next field's
-            // offset. Scalars and other rustc-silent types fall back to the
-            // LLVM natural size.
-            let advance = match mir_stored_size(ctx, layout.field_types[decl_idx]) {
-                Some(size) => size,
-                None => llvm_type_size_align(ctx, llvm_ty)
-                    .map(|(size, _)| size)
-                    .ok_or_else(|| {
-                        anyhow::anyhow!(
-                            "struct slot map: field {decl_idx} lowers to `{}`, which has no \
-                             exact size; refusing to guess the next field offset",
-                            llvm_ty.deref(ctx).disp(ctx)
-                        )
-                    })?,
-            };
-            current_offset += advance;
-        }
-    }
-
-    // Add trailing padding to reach total_size.
-    if has_explicit_layout && current_offset < layout.total_size {
-        let padding_ty = make_padding_type(ctx, layout.total_size - current_offset);
-        llvm_fields.push(padding_ty);
-    }
-
-    // The explicit `[N x i8]` gaps above can only ADD bytes; they cannot make
-    // LLVM place a slot earlier than its natural alignment allows. So when
-    // rustc's layout is tighter than natural (repr(packed)), the struct built
-    // here is a lie at the byte level, and every consumer needs to know.
-    // Unsizable field types leave no verdict: consumers that need the
-    // comparison (field_addr with a recorded rustc offset) fail closed at
-    // their own sites.
-    let walk = natural_layout_walk(ctx, &llvm_fields);
-    let natural_slot_offsets = walk.as_ref().map(|(offsets, _, _)| offsets.clone());
-    let mut layout_diverges = false;
-    if has_explicit_layout && let Some((offsets, end, align)) = &walk {
-        for (decl_idx, slot) in decl_to_llvm.iter().enumerate() {
-            if let Some(slot) = slot
-                && offsets[*slot as usize] != layout.field_offsets[decl_idx]
-            {
-                layout_diverges = true;
-            }
-        }
-        let natural_size = end.div_ceil(*align) * *align;
-        if natural_size != layout.total_size {
-            layout_diverges = true;
-        }
-    }
-
-    // A packed LLVM struct is sequential with alignment 1. That faithfully
-    // represents repr(packed) only when the sequential packed offsets and
-    // final byte count exactly match rustc's metadata. A divergent layout can
-    // also be an old union-like/overlapping model; selecting Packed for such a
-    // shape would merely turn one incorrect sequential layout into another.
-    let packed_walk = if layout_diverges && has_explicit_layout {
-        let mut offsets = Vec::with_capacity(llvm_fields.len());
-        let mut end = 0u64;
-        let mut sizeable = true;
-        for &field in &llvm_fields {
-            offsets.push(end);
-            let Some((field_size, _)) = llvm_type_size_align(ctx, field) else {
-                sizeable = false;
-                break;
-            };
-            let Some(next) = end.checked_add(field_size) else {
-                sizeable = false;
-                break;
-            };
-            end = next;
-        }
-        sizeable.then_some((offsets, end))
-    } else {
-        None
-    };
-    let packed_representable = packed_walk.as_ref().is_some_and(|(offsets, end)| {
-        *end == layout.total_size
-            && decl_to_llvm
-                .iter()
-                .enumerate()
-                .all(|(decl_idx, slot)| match slot {
-                    Some(slot) => offsets[*slot as usize] == layout.field_offsets[decl_idx],
-                    None => true,
-                })
-    });
-
-    let struct_layout = if packed_representable {
-        llvm_types::StructLayout::Packed
-    } else {
-        llvm_types::StructLayout::Unpacked
-    };
-    let llvm_struct_ty: TypeHandle =
-        llvm_types::StructType::get_unnamed(ctx, (llvm_fields, struct_layout)).into();
-    let by_value_layout_faithful = !layout_diverges || packed_representable;
-
-    Ok(StructSlotMap {
-        llvm_struct_ty,
-        decl_to_llvm,
-        field_llvm_types,
-        natural_slot_offsets,
-        layout_diverges,
-        by_value_layout_faithful,
-    })
-}
-
-/// Create a padding type: `[N x i8]` for N bytes of padding.
-fn make_padding_type(ctx: &mut Context, size: u64) -> TypeHandle {
-    let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
-    llvm_types::ArrayType::get(ctx, i8_ty.into(), size).into()
-}
-
-/// Storage for `size` bytes of enum filler at byte `offset`: bytes the payload
-/// occupies that no typed slot claims.
-///
-/// `[N x i8]` is byte-exact but costs one leaf *per byte* everywhere a payload
-/// value is built, merged, or taken apart. `Option<&[T]>` is the shape that
-/// shows it: the niche carrier claims the pointer, the length is left to an
-/// 8-byte filler, and building the value then decomposes that length into
-/// eight `i8` `insertvalue`s, every block merge carries eight `phi i8`, and
-/// reading it back is a chain of `prmt` byte permutes with the aggregate
-/// spilled to `.local` in between. Measured on sm_86, it costs the *pointer*
-/// too: it rides through the same byte soup, `InferAddressSpaces` can no
-/// longer follow it, and the access lands in the generic window (`ld.v2.b64`)
-/// instead of `ld.global.v2.b64`.
-///
-/// One integer of the same width is the same bytes in one leaf. It is only
-/// legal where it moves nothing:
-///
-/// - the width is 2, 4 or 8 bytes, so the integer is byte-faithful (a multiple
-///   of 8 bits, hence no padding of its own). 16 is deliberately excluded:
-///   `i128` is legal LLVM but lowers to register pairs on NVPTX, so widening
-///   that far trades one win for another cost and wants its own measurement;
-/// - `offset` is a multiple of the width, so LLVM inserts no gap ahead of the
-///   field and every later field keeps its byte offset;
-/// - the width does not exceed the enum's alignment, or the struct's natural
-///   alignment would rise above rustc's.
-///
-/// Anything else keeps the byte array. The filler is a *vehicle*, not a claim:
-/// nothing reads it field-wise, because a payload that has no typed slot
-/// round-trips through memory as a whole aggregate, and both ends of that
-/// round trip are byte-exact. `build_enum_slot_map`'s own size and alignment
-/// assertions — hard errors, not debug checks — backstop all three conditions.
-fn make_enum_filler_type(ctx: &mut Context, offset: u64, size: u64, abi_align: u64) -> TypeHandle {
-    if matches!(size, 2 | 4 | 8) && offset.is_multiple_of(size) && size <= abi_align.max(1) {
-        let width = u32::try_from(size * 8).expect("size is at most 8, so width is at most 64");
-        return IntegerType::get(ctx, width, Signedness::Signless).into();
-    }
-    make_padding_type(ctx, size)
-}
-
-/// Build byte-exact LLVM storage for a Rust union.
-///
-/// A union cannot be represented as an LLVM struct containing every declared
-/// field: struct fields are consecutive, while union fields all start at byte
-/// zero. We choose one byte-faithful field as the storage view and add explicit
-/// tail bytes. A zero-length integer array raises the LLVM type's natural
-/// alignment without consuming storage. Pointer-bearing fields are preferred
-/// so an ordinary union copy keeps LLVM pointer provenance.
-///
-/// NVPTX gives scalar integers natural alignments up to 16 bytes. Stronger
-/// Rust alignment is carried explicitly on memory operations because LLVM
-/// aggregate types cannot encode over-alignment; the storage type still keeps
-/// the union's exact size and therefore its array stride.
-pub(crate) fn build_union_storage_type(
-    ctx: &mut Context,
-    union_ty: &MirUnionType,
-) -> Result<TypeHandle, anyhow::Error> {
-    let size = union_ty.total_size();
-    let align = union_ty.abi_align();
-    if align == 0 || !align.is_power_of_two() {
-        return Err(anyhow::anyhow!(
-            "union `{}` has invalid ABI alignment {}",
-            union_ty.name(),
-            align
-        ));
-    }
-    if size > 0 && !size.is_multiple_of(align) {
-        return Err(anyhow::anyhow!(
-            "union `{}` size {} is not a multiple of its {}-byte ABI alignment",
-            union_ty.name(),
-            size,
-            align
-        ));
-    }
-
-    let mut fields = Vec::with_capacity(union_ty.field_count());
-    let mut pointer_carrier: Option<TypeHandle> = None;
-    for (index, &field_ty) in union_ty.field_types().iter().enumerate() {
-        let llvm_field_ty = convert_type(ctx, field_ty)?;
-        let (field_size, field_align) =
-            llvm_type_size_align(ctx, llvm_field_ty).ok_or_else(|| {
-                anyhow::anyhow!(
-                    "union `{}` field {} has unsupported LLVM size/alignment",
-                    union_ty.name(),
-                    index
-                )
-            })?;
-        if field_size > size {
-            return Err(anyhow::anyhow!(
-                "union `{}` field {} lowers to {} bytes but the union is only {} bytes",
-                union_ty.name(),
-                index,
-                field_size,
-                size
-            ));
-        }
-        if field_align > align {
-            return Err(anyhow::anyhow!(
-                "union `{}` field {} lowers with alignment {} but rustc reports union alignment {}",
-                union_ty.name(),
-                index,
-                field_align,
-                align
-            ));
-        }
-        let contains_pointer = llvm_type_contains_pointer(ctx, llvm_field_ty);
-        if contains_pointer {
-            if let Some(first) = pointer_carrier
-                && first != llvm_field_ty
-            {
-                return Err(anyhow::anyhow!(
-                    "union `{}` has pointer-bearing fields with different LLVM representations; preserving provenance for that shape is not yet supported",
-                    union_ty.name()
-                ));
-            }
-            pointer_carrier = Some(llvm_field_ty);
-        }
-        fields.push((llvm_field_ty, field_size, field_align, contains_pointer));
-    }
-
-    let storage_align = align.min(16);
-    let anchor_int = IntegerType::get(ctx, (storage_align * 8) as u32, Signedness::Signless);
-    let anchor: TypeHandle = llvm_types::ArrayType::get(ctx, anchor_int.into(), 0).into();
-    let mut storage_fields = vec![anchor];
-    if size > 0 {
-        let representative = fields
-            .iter()
-            .filter(|(ty, field_size, _, _)| {
-                *field_size > 0
-                    && llvm_type_is_byte_faithful(ctx, *ty)
-                    && (pointer_carrier.is_none() || llvm_type_contains_pointer(ctx, *ty))
-            })
-            .max_by_key(|(_, field_size, field_align, contains_pointer)| {
-                (*contains_pointer, *field_align, *field_size)
-            });
-        if let Some(representative) = representative {
-            storage_fields.push(representative.0);
-            if representative.1 < size {
-                storage_fields.push(make_padding_type(ctx, size - representative.1));
-            }
-        } else if pointer_carrier.is_some() {
-            return Err(anyhow::anyhow!(
-                "union `{}` has pointer-bearing fields but no byte-faithful pointer carrier; lowering it as raw bytes would discard pointer provenance",
-                union_ty.name()
-            ));
-        } else {
-            // Pointer-free unions may safely use raw bytes as their SSA
-            // carrier. Field loads/stores still use their declared types.
-            storage_fields.push(make_padding_type(ctx, size));
-        }
-    }
-    let storage: TypeHandle = llvm_types::StructType::get_unnamed(
-        ctx,
-        (storage_fields, llvm_types::StructLayout::Unpacked),
-    )
-    .into();
-    let (llvm_size, llvm_align) = llvm_type_size_align(ctx, storage).ok_or_else(|| {
-        anyhow::anyhow!(
-            "union `{}` storage has unsupported LLVM layout",
-            union_ty.name()
-        )
-    })?;
-    if llvm_size != size || llvm_align > align {
-        return Err(anyhow::anyhow!(
-            "union `{}` storage lowered to incompatible size/alignment {}/{} but rustc requires {}/{}",
-            union_ty.name(),
-            llvm_size,
-            llvm_align,
-            size,
-            align
-        ));
-    }
-    Ok(storage)
-}
-
-fn llvm_type_contains_pointer(ctx: &Context, ty: TypeHandle) -> bool {
-    let ty_ref = ty.deref(ctx);
-    if ty_ref.is::<llvm_types::PointerType>() {
-        return true;
-    }
-    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-        return llvm_type_contains_pointer(ctx, array.elem_type());
-    }
-    if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
-        return llvm_type_contains_pointer(ctx, vector.elem_type());
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-        return struct_ty
-            .fields()
-            .any(|field| llvm_type_contains_pointer(ctx, field));
-    }
-    false
-}
-
-/// One pointer-valued leaf in an LLVM aggregate's physical storage.
-///
-/// Offsets are absolute within the enclosing enum. Keeping the address space
-/// in the identity prevents an AS0 pointer carrier from being treated as the
-/// same storage as an AS1 payload pointer merely because both are eight bytes.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord)]
-struct LlvmPointerStorage {
-    offset: u64,
-    size: u64,
-    address_space: u32,
-}
-
-/// Why a pointer-storage walk refused a type or an overlap.
-///
-/// Distinguishing bounded array expansion from genuine provenance loss keeps
-/// the user-facing diagnostic specific: an oversized pointer array reports the
-/// same "rewrite requires N pointer conversions" contract as the payload
-/// storage gate instead of a misleading provenance error.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-enum PointerOverlapRejection {
-    /// Expanding the walked type's fixed arrays into per-leaf records would
-    /// exceed [`MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES`]; `required` is the
-    /// total number of array-expanded pointer leaves.
-    OverArrayLeafBound { required: u64 },
-    /// The type holds pointer storage this walk cannot represent, or the
-    /// overlap would pun a pointer against non-matching bytes.
-    ProvenanceLoss,
-}
-
-/// Total pointer leaves in `ty`, through arrays and structs, with checked
-/// arithmetic. Pointer vectors count zero; every walk that expands leaves
-/// fails closed on them separately.
-fn count_pointer_leaves(ctx: &Context, ty: TypeHandle) -> Option<u64> {
-    let ty_ref = ty.deref(ctx);
-    if ty_ref.is::<llvm_types::PointerType>() {
-        return Some(1);
-    }
-    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-        return count_pointer_leaves(ctx, array.elem_type())?.checked_mul(array.size());
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-        let fields: Vec<_> = struct_ty.fields().collect();
-        let mut total = 0u64;
-        for field in fields {
-            total = total.checked_add(count_pointer_leaves(ctx, field)?)?;
-        }
-        return Some(total);
-    }
-    Some(0)
-}
-
-/// Pointer leaves that expanding `ty`'s fixed arrays contributes to a
-/// pointer-storage walk.
-///
-/// Leaves outside arrays are proportional to the source text and stay
-/// unbounded, exactly like struct nesting in `enum_payload_storage_type`.
-/// `[&T; N]` expands from three tokens into `N` records, so only
-/// array-expanded leaves count against
-/// [`MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES`].
-fn count_array_pointer_leaves(ctx: &Context, ty: TypeHandle) -> Option<u64> {
-    let ty_ref = ty.deref(ctx);
-    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-        return count_pointer_leaves(ctx, array.elem_type())?.checked_mul(array.size());
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-        let fields: Vec<_> = struct_ty.fields().collect();
-        let mut total = 0u64;
-        for field in fields {
-            total = total.checked_add(count_array_pointer_leaves(ctx, field)?)?;
-        }
-        return Some(total);
-    }
-    Some(0)
-}
-
-/// Record every pointer-valued leaf in `ty` at its natural LLVM byte offset.
-///
-/// This is deliberately a physical-layout walk rather than a simple
-/// `contains_pointer` predicate. A niche carrier may be one field inside an
-/// aggregate payload, for example the pointer at byte 8 in
-/// `Option<(usize, &T)>`. In that case the aggregate and the carrier overlap,
-/// but they agree exactly about which bytes hold the pointer.
-///
-/// Expanding an arbitrary array into one record per pointer would let a valid
-/// but enormous type consume unbounded verifier memory, so the walk first
-/// counts the array-expanded leaves and refuses anything over
-/// [`MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES`] with the bound-specific
-/// rejection before allocating a single record.
-fn collect_llvm_pointer_storage(
-    ctx: &Context,
-    ty: TypeHandle,
-    base_offset: u64,
-    out: &mut Vec<LlvmPointerStorage>,
-) -> std::result::Result<(), PointerOverlapRejection> {
-    fn collect(
-        ctx: &Context,
-        ty: TypeHandle,
-        base_offset: u64,
-        out: &mut Vec<LlvmPointerStorage>,
-    ) -> Option<()> {
-        let ty_ref = ty.deref(ctx);
-        if let Some(pointer) = ty_ref.downcast_ref::<llvm_types::PointerType>() {
-            let (size, _) = llvm_type_size_align(ctx, ty)?;
-            out.push(LlvmPointerStorage {
-                offset: base_offset,
-                size,
-                address_space: pointer.address_space(),
-            });
-            return Some(());
-        }
-        if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-            let element_ty = array.elem_type();
-            if !llvm_type_contains_pointer(ctx, element_ty) {
-                return Some(());
-            }
-            let (element_size, _) = llvm_type_size_align(ctx, element_ty)?;
-            for index in 0..array.size() {
-                let element_offset = element_size.checked_mul(index)?;
-                collect(
-                    ctx,
-                    element_ty,
-                    base_offset.checked_add(element_offset)?,
-                    out,
-                )?;
-            }
-            return Some(());
-        }
-        if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
-            // Pointer vectors carry vector-specific ABI alignment and cast
-            // semantics. Keep them fail-closed rather than treating them like
-            // fixed arrays.
-            return (!llvm_type_contains_pointer(ctx, vector.elem_type())).then_some(());
-        }
-        if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-            let fields: Vec<_> = struct_ty.fields().collect();
-            let packed = struct_ty.layout() == llvm_types::StructLayout::Packed;
-            let mut end = 0u64;
-            for field in fields {
-                let (field_size, field_align) = llvm_type_size_align(ctx, field)?;
-                let field_offset = if packed {
-                    end
-                } else {
-                    let field_align = field_align.max(1);
-                    let remainder = end % field_align;
-                    if remainder == 0 {
-                        end
-                    } else {
-                        end.checked_add(field_align - remainder)?
-                    }
-                };
-                collect(ctx, field, base_offset.checked_add(field_offset)?, out)?;
-                end = field_offset.checked_add(field_size)?;
-            }
-            return Some(());
-        }
-
-        // All pointer-bearing LLVM types understood by this lowering are
-        // handled above. Unknown pointer containers must fail closed.
-        (!llvm_type_contains_pointer(ctx, ty)).then_some(())
-    }
-
-    let required =
-        count_array_pointer_leaves(ctx, ty).ok_or(PointerOverlapRejection::ProvenanceLoss)?;
-    if required > MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES {
-        return Err(PointerOverlapRejection::OverArrayLeafBound { required });
-    }
-    collect(ctx, ty, base_offset, out).ok_or(PointerOverlapRejection::ProvenanceLoss)
-}
-
-/// Analyze how a slotless incoming pointer-bearing field overlaps the enum's
-/// already-selected storage, and report how to back every one of its pointers
-/// with a real `ptr` slot.
-///
-/// Returns `Ok(extra)` when the field is representable without erasing any
-/// pointer's provenance: every pointer leaf that coincides with an existing
-/// claim reuses that claim, and each remaining ("extra") pointer leaf lands on
-/// bytes no other claim covers, so it can be backed by its own fresh `ptr`
-/// slot. `extra` lists exactly those leaves for the caller to add as claims.
-/// An empty `extra` is the exact-match case (e.g. `Option<(usize, &T)>`, whose
-/// single pointer already coincides with the niche carrier); a non-empty
-/// `extra` is the multi-pointer payload case (e.g. `Option<(&mut [T],
-/// &mut [T])>` from `split_at_mut_checked`, whose second slice pointer needs a
-/// slot of its own beside the carrier).
-///
-/// Returns [`PointerOverlapRejection::ProvenanceLoss`] when the field cannot
-/// be represented without punning a pointer against non-pointer bits: an
-/// existing pointer slot the incoming field does not also carry at the same
-/// offset/size/address space, or an extra pointer leaf that would overlap an
-/// existing (necessarily non-pointer) claim. That genuine pointer/integer
-/// union stays fail-closed — there is no single LLVM slot type that is both
-/// provenance-carrying and integer-exact.
-///
-/// Returns [`PointerOverlapRejection::OverArrayLeafBound`] when a walked type
-/// holds more array-expanded pointer leaves than the bounded rewrite limit,
-/// so the caller can report the bound instead of a provenance error.
-fn analyze_pointer_overlap(
-    ctx: &Context,
-    incoming_offset: u64,
-    incoming_size: u64,
-    incoming_ty: TypeHandle,
-    colliding_claims: &[&(u64, u64, TypeHandle)],
-) -> std::result::Result<Vec<LlvmPointerStorage>, PointerOverlapRejection> {
-    use PointerOverlapRejection::ProvenanceLoss;
-
-    let incoming_end = incoming_offset
-        .checked_add(incoming_size)
-        .ok_or(ProvenanceLoss)?;
-
-    let mut incoming = Vec::new();
-    collect_llvm_pointer_storage(ctx, incoming_ty, incoming_offset, &mut incoming)?;
-
-    let mut existing = Vec::new();
-    for &&(offset, _size, claim_ty) in colliding_claims {
-        let mut regions = Vec::new();
-        collect_llvm_pointer_storage(ctx, claim_ty, offset, &mut regions)?;
-        existing.extend(regions.into_iter().filter(|region| {
-            let Some(region_end) = region.offset.checked_add(region.size) else {
-                return true;
-            };
-            region.offset < incoming_end && incoming_offset < region_end
-        }));
-    }
-
-    // Every existing pointer leaf overlapping this field must be one the field
-    // also carries at the same offset/size/address space; otherwise a pointer
-    // slot would be backed by non-matching bytes (an address-space mismatch, or
-    // a pointer claim where the field has integer bits).
-    for leaf in &existing {
-        if !incoming.contains(leaf) {
-            return Err(ProvenanceLoss);
-        }
-    }
-
-    // Each incoming pointer leaf that does not reuse an existing claim needs its
-    // own slot, and may only get one if it lands on otherwise-unclaimed bytes. A
-    // leaf overlapping a claim it did not match is a pointer/non-pointer pun and
-    // stays fail-closed.
-    let mut extra = Vec::new();
-    for leaf in &incoming {
-        if existing.contains(leaf) {
-            continue;
-        }
-        let leaf_end = leaf.offset.checked_add(leaf.size).ok_or(ProvenanceLoss)?;
-        let overlaps_claim = colliding_claims.iter().any(|&&(o, s, _)| {
-            let Some(claim_end) = o.checked_add(s) else {
-                return true;
-            };
-            o < leaf_end && leaf.offset < claim_end
-        });
-        if overlaps_claim {
-            return Err(ProvenanceLoss);
-        }
-        extra.push(*leaf);
-    }
-
-    Ok(extra)
-}
-
-pub(crate) fn llvm_type_contains_pointer_in_address_space(
-    ctx: &Context,
-    ty: TypeHandle,
-    address_space: u32,
-) -> bool {
-    let ty_ref = ty.deref(ctx);
-    if let Some(pointer) = ty_ref.downcast_ref::<llvm_types::PointerType>() {
-        return pointer.address_space() == address_space;
-    }
-    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-        return llvm_type_contains_pointer_in_address_space(ctx, array.elem_type(), address_space);
-    }
-    if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
-        return llvm_type_contains_pointer_in_address_space(ctx, vector.elem_type(), address_space);
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-        return struct_ty
-            .fields()
-            .any(|field| llvm_type_contains_pointer_in_address_space(ctx, field, address_space));
-    }
-    false
-}
-
-/// Whether a physical by-value image contains a packed struct whose bytes
-/// include a pointer in `address_space`.
-///
-/// Direct pointers in an unpacked aggregate do not trigger this predicate:
-/// their ABI can preserve address-space semantics without observing the
-/// pointer's raw storage width. A pointer nested anywhere under an LLVM packed
-/// struct does trigger it because whole-value construction/load/store/ABI
-/// traffic observes that packed physical image. This distinction keeps normal
-/// AS3 aggregate handling intact while rejecting the target-dependent packed
-/// case (modern NVVM p3:32 versus 64-bit PTX/legacy).
-pub(crate) fn llvm_packed_struct_contains_pointer_in_address_space(
-    ctx: &Context,
-    ty: TypeHandle,
-    address_space: u32,
-) -> bool {
-    let ty_ref = ty.deref(ctx);
-    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-        return llvm_packed_struct_contains_pointer_in_address_space(
-            ctx,
-            array.elem_type(),
-            address_space,
-        );
-    }
-    if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
-        return llvm_packed_struct_contains_pointer_in_address_space(
-            ctx,
-            vector.elem_type(),
-            address_space,
-        );
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-        let fields: Vec<_> = struct_ty.fields().collect();
-        if struct_ty.layout() == llvm_types::StructLayout::Packed
-            && fields
-                .iter()
-                .copied()
-                .any(|field| llvm_type_contains_pointer_in_address_space(ctx, field, address_space))
-        {
-            return true;
-        }
-        return fields.into_iter().any(|field| {
-            llvm_packed_struct_contains_pointer_in_address_space(ctx, field, address_space)
-        });
-    }
-    false
-}
-
-/// Whether this is an aggregate/vector that contains LLVM `i1` storage.
-///
-/// Rust `bool` is an SSA `i1`, but its memory representation is one complete
-/// byte whose only valid values are 0 and 1. Enum storage never uses `i1` as
-/// a physical type: scalar bools claim an explicit i8 byte, and aggregates
-/// containing bools claim their byte-faithful twin (see
-/// [`llvm_byte_faithful_twin`]), with construction canonicalizing the value
-/// before the store.
-pub(crate) fn llvm_type_contains_i1(ctx: &Context, ty: TypeHandle) -> bool {
-    let ty_ref = ty.deref(ctx);
-    if let Some(integer) = ty_ref.downcast_ref::<IntegerType>() {
-        return integer.width() == 1;
-    }
-    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-        return llvm_type_contains_i1(ctx, array.elem_type());
-    }
-    if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
-        return llvm_type_contains_i1(ctx, vector.elem_type());
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-        return struct_ty
-            .fields()
-            .any(|field| llvm_type_contains_i1(ctx, field));
-    }
-    false
-}
-
-/// The byte-faithful storage twin of an LLVM type: every `i1` leaf becomes
-/// its canonical `i8` memory byte, recursively through structs and arrays.
-///
-/// Rust guarantees a bool occupies one full byte holding exactly 0 or 1, so
-/// storing the twin (with each bool zero-extended) writes the same bytes the
-/// host writes, while re-loading the original type from those canonical
-/// bytes remains well-defined. Sizes and alignments are unchanged because an
-/// `i1` already occupies one byte of storage.
-///
-/// Returns `None` for shapes with a different memory story (`i1` vectors are
-/// bit-packed masks) or unknown containers; callers must fail closed.
-pub(crate) fn llvm_byte_faithful_twin(ctx: &mut Context, ty: TypeHandle) -> Option<TypeHandle> {
-    if !llvm_type_contains_i1(ctx, ty) {
-        return Some(ty);
-    }
-    enum Shape {
-        Bool,
-        Array(TypeHandle, u64),
-        Struct {
-            fields: Vec<TypeHandle>,
-            layout: llvm_types::StructLayout,
-        },
-        Other,
-    }
-    let shape = {
-        let ty_ref = ty.deref(ctx);
-        if ty_ref
-            .downcast_ref::<IntegerType>()
-            .is_some_and(|integer| integer.width() == 1)
-        {
-            Shape::Bool
-        } else if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-            Shape::Array(array.elem_type(), array.size())
-        } else if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-            Shape::Struct {
-                fields: struct_ty.fields().collect(),
-                layout: struct_ty.layout(),
-            }
-        } else {
-            Shape::Other
-        }
-    };
-    match shape {
-        Shape::Bool => Some(IntegerType::get(ctx, 8, Signedness::Signless).into()),
-        Shape::Array(elem, count) => {
-            let twin = llvm_byte_faithful_twin(ctx, elem)?;
-            Some(llvm_types::ArrayType::get(ctx, twin, count).into())
-        }
-        Shape::Struct { fields, layout } => {
-            let twins = fields
-                .into_iter()
-                .map(|field| llvm_byte_faithful_twin(ctx, field))
-                .collect::<Option<Vec<_>>>()?;
-            Some(llvm_types::StructType::get_unnamed(ctx, (twins, layout)).into())
-        }
-        Shape::Other => None,
-    }
-}
-
-/// Whether a MIR aggregate contains a semantic Rust bool value.
-///
-/// This deliberately stops at pointers/slices: a pointee bool does not occupy
-/// bytes in the aggregate itself. It also stops at nested enums, whose own
-/// slot-map construction is responsible for canonicalizing a top-level bool
-/// or rejecting a deeper one. Inspecting the MIR type is necessary because a
-/// union may lower to raw i8 storage and thereby hide a bool from the LLVM
-/// type-level check above.
-fn mir_type_contains_i1(ctx: &Context, ty: TypeHandle) -> bool {
-    let ty_ref = ty.deref(ctx);
-    if let Some(integer) = ty_ref.downcast_ref::<IntegerType>() {
-        return integer.width() == 1;
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
-        return struct_ty
-            .field_types()
-            .iter()
-            .copied()
-            .any(|field| mir_type_contains_i1(ctx, field));
-    }
-    if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
-        return tuple_ty
-            .get_types()
-            .iter()
-            .copied()
-            .any(|field| mir_type_contains_i1(ctx, field));
-    }
-    if let Some(array_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
-        return mir_type_contains_i1(ctx, array_ty.element_ty);
-    }
-    if let Some(union_ty) = ty_ref.downcast_ref::<MirUnionType>() {
-        return union_ty
-            .field_types()
-            .iter()
-            .copied()
-            .any(|field| mir_type_contains_i1(ctx, field));
-    }
-    false
-}
-
-/// Whether loading and storing this LLVM value preserves every byte in its
-/// allocation. In particular, `i1` is not byte-faithful: it occupies one
-/// addressable byte, but LLVM does not define the upper seven stored bits.
-pub(crate) fn llvm_type_is_byte_faithful(ctx: &Context, ty: TypeHandle) -> bool {
-    let ty_ref = ty.deref(ctx);
-    if let Some(int_ty) = ty_ref.downcast_ref::<IntegerType>() {
-        return int_ty.width().is_multiple_of(8);
-    }
-    if ty_ref.is::<llvm_types::HalfType>()
-        || ty_ref.is::<FP32Type>()
-        || ty_ref.is::<FP64Type>()
-        || ty_ref.is::<llvm_types::PointerType>()
-    {
-        return true;
-    }
-    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-        return llvm_type_is_byte_faithful(ctx, array.elem_type());
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-        let fields: Vec<_> = struct_ty.fields().collect();
-        if struct_ty.layout() == llvm_types::StructLayout::Packed {
-            return fields
-                .into_iter()
-                .all(|field| llvm_type_is_byte_faithful(ctx, field));
-        }
-
-        let mut end = 0u64;
-        let mut max_align = 1u64;
-        for field in fields {
-            if !llvm_type_is_byte_faithful(ctx, field) {
-                return false;
-            }
-            let Some((field_size, field_align)) = llvm_type_size_align(ctx, field) else {
-                return false;
-            };
-            let field_align = field_align.max(1);
-            let aligned_end = end.div_ceil(field_align) * field_align;
-            if aligned_end != end {
-                // LLVM would insert bytes that are not represented by an SSA
-                // field. Loading and re-storing the aggregate would lose them.
-                return false;
-            }
-            end += field_size;
-            max_align = max_align.max(field_align);
-        }
-        // Reject implicit trailing padding for the same reason. Explicit
-        // `[N x i8]` padding fields keep `end` equal to the allocation size.
-        return end.div_ceil(max_align) * max_align == end;
-    }
-    false
-}
-
-/// Size of a MIR-level type from rustc layout truth, when stored.
-///
-/// `MirStructType`, `MirTupleType`, `MirUnionType`, and `MirEnumType` carry
-/// `total_size` (interior and trailing padding included) straight from
-/// rustc's layout query; arrays of such aggregates multiply it out. Returns
-/// `None` when no stored size is available (e.g. niched/single-variant enums
-/// store 0) and the caller must fall back to the LLVM-level approximation.
-fn mir_stored_size(ctx: &Context, mir_ty: TypeHandle) -> Option<u64> {
-    let ty_ref = mir_ty.deref(ctx);
-    if let Some(s) = ty_ref.downcast_ref::<MirStructType>() {
-        if s.total_size() > 0 {
-            return Some(s.total_size());
-        }
-        return None;
-    }
-    if let Some(t) = ty_ref.downcast_ref::<MirTupleType>() {
-        if t.total_size > 0 {
-            return Some(t.total_size);
-        }
-        return None;
-    }
-    if let Some(e) = ty_ref.downcast_ref::<MirEnumType>() {
-        if e.total_size() > 0 {
-            return Some(e.total_size());
-        }
-        return None;
-    }
-    if let Some(u) = ty_ref.downcast_ref::<MirUnionType>() {
-        return Some(u.total_size());
-    }
-    if let Some(a) = ty_ref.downcast_ref::<MirArrayType>() {
-        let elem_ty = a.element_ty;
-        let size = a.size;
-        // Checked: alignment claims consume this, and a wrapped product
-        // would masquerade as a small, trusted stride.
-        return mir_stored_size(ctx, elem_ty).and_then(|elem_size| elem_size.checked_mul(size));
-    }
-    None
-}
-
-/// Exact byte stride of a MIR array's element, when provable.
-///
-/// Element `i` of an array lives at byte `i * stride`, so any alignment
-/// claim about an element address is only as strong as the stride it
-/// multiplies, and a wrong stride is a miscompile. Scalars have exact
-/// sizes; MIR aggregates answer with rustc's stored size (interior and
-/// trailing padding included) via [`mir_stored_size`]; arrays of scalars
-/// multiply out. Everything else answers `None` so the caller declines
-/// instead of guessing.
-pub(crate) fn mir_element_stride(ctx: &Context, mir_ty: TypeHandle) -> Option<u64> {
-    if let Some(size) = mir_stored_size(ctx, mir_ty) {
-        return Some(size);
-    }
-    let ty_ref = mir_ty.deref(ctx);
-    if let Some(int_ty) = ty_ref.downcast_ref::<IntegerType>() {
-        return Some(u64::from(int_ty.width()).div_ceil(8));
-    }
-    // The importer's f16 is MirFP16Type; the HalfType arm covers IR that
-    // already carries the converted LLVM scalar.
-    if ty_ref.is::<MirFP16Type>() || ty_ref.is::<llvm_types::HalfType>() {
-        return Some(2);
-    }
-    if ty_ref.is::<FP32Type>() {
-        return Some(4);
-    }
-    if ty_ref.is::<FP64Type>() {
-        return Some(8);
-    }
-    if let Some(ptr_ty) = ty_ref.downcast_ref::<MirPtrType>() {
-        // Generic-space pointers are 64-bit under every data layout the
-        // exporter can choose; a shared-space pointer is 32-bit under the
-        // modern NVVM layout alone, so its stored stride is target-dependent.
-        // Claim the former, decline the latter.
-        return (ptr_ty.address_space == 0).then_some(8);
-    }
-    if let Some(array_ty) = ty_ref.downcast_ref::<MirArrayType>() {
-        // Arrays of sized aggregates already answered through
-        // `mir_stored_size` above; this recursion serves arrays of
-        // scalars and pointers, and deeper such arrays.
-        let element_ty = array_ty.element_type();
-        let count = array_ty.size();
-        drop(ty_ref);
-        return mir_element_stride(ctx, element_ty)?.checked_mul(count);
-    }
-    None
-}
-
-/// Exact ABI alignment carried by a MIR aggregate type, when rustc layout is
-/// available.
-///
-/// LLVM aggregate types cannot encode a Rust `repr(align(N))` raise. Tuples,
-/// structs, enums, and unions therefore carry rustc's alignment explicitly in
-/// the MIR dialect. Arrays have the same ABI alignment as their element, so
-/// recurse through any number of array layers instead of relying on the
-/// converted LLVM element's structural alignment.
-pub(crate) fn mir_type_abi_align(ctx: &Context, mir_ty: TypeHandle) -> Option<u64> {
-    let ty_ref = mir_ty.deref(ctx);
-    if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
-        return Some(tuple_ty.abi_align()).filter(|align| *align > 0);
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
-        return Some(struct_ty.abi_align).filter(|align| *align > 0);
-    }
-    if let Some(enum_ty) = ty_ref.downcast_ref::<MirEnumType>() {
-        return Some(enum_ty.abi_align()).filter(|align| *align > 0);
-    }
-    if let Some(union_ty) = ty_ref.downcast_ref::<MirUnionType>() {
-        return Some(union_ty.abi_align()).filter(|align| *align > 0);
-    }
-    if let Some(array_ty) = ty_ref.downcast_ref::<MirArrayType>() {
-        let element_ty = array_ty.element_type();
-        return mir_type_abi_align(ctx, element_ty);
-    }
-    None
-}
-
-/// LLVM natural-layout `(size, align)` of an exported LLVM type, in bytes.
-///
-/// Mirrors LLVM's default data layout for nvptx64 (scalars align to their
-/// size, arrays to their element, non-packed structs to their widest field).
-/// Computes the real allocation size (interior and trailing padding
-/// included), which is what GEP striding and the enum size check below
-/// need. Answers `None` rather than guess: sizes here are exact or absent.
-pub(crate) fn llvm_type_size_align(ctx: &Context, ty: TypeHandle) -> Option<(u64, u64)> {
-    let ty_ref = ty.deref(ctx);
-
-    if let Some(int_ty) = ty_ref.downcast_ref::<IntegerType>() {
-        let size = (int_ty.width() as u64).div_ceil(8);
-        // i8 → 1, i16 → 2, i32 → 4, i64 → 8, i128 → 16.
-        return Some((size, size.next_power_of_two().min(16)));
-    }
-    if ty_ref.is::<llvm_types::HalfType>() {
-        return Some((2, 2));
-    }
-    if ty_ref.is::<FP32Type>() {
-        return Some((4, 4));
-    }
-    if ty_ref.is::<FP64Type>() {
-        return Some((8, 8));
-    }
-    if ty_ref.is::<llvm_types::PointerType>() {
-        // Lowering runs before the exporter chooses the minimal, legacy, or
-        // modern NVPTX data layout. The first two use 64-bit pointers in all
-        // address spaces; modern NVVM alone uses p3:32. Callers that expose
-        // physical shared-pointer width must either genericize a direct
-        // pointer first or reject the target-dependent representation.
-        return Some((8, 8));
-    }
-    if let Some(arr_ty) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
-        let (elem_size, elem_align) = llvm_type_size_align(ctx, arr_ty.elem_type())?;
-        return Some((elem_size.checked_mul(arr_ty.size())?, elem_align.max(1)));
-    }
-    if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
-        if vector.is_scalable() {
-            return None;
-        }
-        let element_bits = {
-            let element = vector.elem_type();
-            let element_ref = element.deref(ctx);
-            if let Some(integer) = element_ref.downcast_ref::<IntegerType>() {
-                u64::from(integer.width())
-            } else if let Some(float) = type_cast::<dyn FloatTypeInterface>(&*element_ref) {
-                u64::try_from(float.get_semantics().bits).ok()?
-            } else if element_ref.is::<llvm_types::PointerType>() {
-                64
-            } else {
-                return None;
-            }
-        };
-        let total_bits = element_bits.checked_mul(u64::from(vector.num_elements()))?;
-        let size = total_bits.div_ceil(8);
-        // Both cuda-oxide NVPTX data layouts explicitly define fixed vector
-        // ABI alignment only for these widths. Refuse to guess LLVM defaults
-        // for any other width in physical Rust layout code.
-        let align = match total_bits {
-            16 => 2,
-            32 => 4,
-            64 => 8,
-            128 => 16,
-            _ => return None,
-        };
-        return Some((size, align));
-    }
-    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
-        let fields: Vec<_> = struct_ty.fields().collect();
-        if struct_ty.layout() == llvm_types::StructLayout::Packed {
-            let mut size = 0u64;
-            for field in fields {
-                let (field_size, _) = llvm_type_size_align(ctx, field)?;
-                size = size.checked_add(field_size)?;
-            }
-            return Some((size, 1));
-        }
-
-        let (_end, size, align) = natural_struct_layout(ctx, &fields)?;
-        return Some((size, align));
-    }
-
-    None
-}
-
-/// The one walk defining natural (non-packed) LLVM struct placement: each
-/// field starts at the running offset rounded up to its own alignment.
-///
-/// Returns `(offsets, end, align)`: the byte offset of every field, the
-/// unrounded offset just past the last field, and the widest field alignment.
-/// [`natural_struct_layout`] and [`StructSlotMap::natural_slot_offsets`] are
-/// both views of this walk, so a size question and an offset question can
-/// never disagree.
-fn natural_layout_walk(ctx: &Context, fields: &[TypeHandle]) -> Option<(Vec<u64>, u64, u64)> {
-    let mut offsets = Vec::with_capacity(fields.len());
-    let mut end = 0u64;
-    let mut align = 1u64;
-    for field in fields {
-        let (field_size, field_align) = llvm_type_size_align(ctx, *field)?;
-        let field_align = field_align.max(1);
-        end = end.div_ceil(field_align) * field_align;
-        offsets.push(end);
-        end = end.checked_add(field_size)?;
-        align = align.max(field_align);
-    }
-    Some((offsets, end, align))
-}
-
-/// Natural (non-packed) LLVM struct layout over `fields`.
-///
-/// Returns `(end, size, align)` where `end` is the unrounded offset just past
-/// the last field, `size` is `end` rounded up to the struct alignment (the
-/// allocation size LLVM uses for GEP striding), and `align` is the widest
-/// field alignment.
-pub(crate) fn natural_struct_layout(
-    ctx: &Context,
-    fields: &[TypeHandle],
-) -> Option<(u64, u64, u64)> {
-    let (_offsets, end, align) = natural_layout_walk(ctx, fields)?;
-    let size = end.div_ceil(align) * align;
-    Some((end, size, align))
-}
-
-/// The LLVM struct for an enum, plus a map saying where the tag and each
-/// payload field ended up.
-///
-/// The struct type and the indices into it are produced by one walk in
-/// [`build_enum_slot_map`], so they can never disagree. (Computing them
-/// separately is how the issue #128 class of bug happened for structs.)
-pub(crate) struct EnumSlotMap {
-    /// The final LLVM struct type, including any `[N x i8]` filler slots.
-    pub llvm_struct_ty: TypeHandle,
-    /// Which struct slot holds rustc's physical tag/niche carrier. `None`
-    /// for `Single` and `Empty` layouts, which have no tag in memory.
-    pub carrier_slot: Option<u32>,
-    /// Converted physical carrier type (integer or pointer), when present.
-    pub carrier_llvm_ty: Option<TypeHandle>,
-    /// Which struct slot holds each payload field, in the flattened
-    /// order of `MirEnumType::all_field_types`. `None` means the field
-    /// has no slot of its own: it is zero-sized, or its bytes are shared
-    /// with a different-typed field of another variant. Such fields are
-    /// read and written through memory at `field_offsets` instead.
-    pub field_slots: Vec<Option<u32>>,
-    /// Byte position of each payload field inside the enum.
-    pub field_offsets: Vec<u64>,
-    /// Converted LLVM type of each payload field.
-    pub field_llvm_types: Vec<TypeHandle>,
-}
-
-/// Build the LLVM struct for an enum, placing everything at the byte
-/// positions rustc chose.
-///
-/// Why this matters: the host (CPU) lays out enum values with rustc's
-/// layout. If the device used different byte positions, every enum
-/// passed to a kernel would be read wrong. So the device struct is built
-/// to have the same bytes, position for position.
-///
-/// The wrinkle is that enum variants SHARE bytes (only one variant is
-/// alive at a time), and an LLVM struct cannot say "these two fields
-/// overlap". The slot map resolves each field one of three ways:
-///
-/// ```text
-/// #[repr(u32)] enum E { A(u32), B(f32), C }
-/// rustc: 8 bytes, tag at byte 0, A's u32 and B's f32 both at byte 4
-///
-/// LLVM struct: { i32, i32 }
-///                 |     |
-///        tag_slot=0     A's payload: own slot (nothing else typed i32
-///                       wanted byte 4 first... B did, see below)
-///
-/// - own slot:   the field's bytes collide with nothing already placed.
-/// - shared slot: another variant already placed the SAME type at the
-///                SAME position; both map to that slot. (If B were
-///                B(u32), A and B would simply share slot 1.)
-/// - no slot:    the bytes are taken by a different type (B's f32 vs
-///                A's u32 here). The field is still at byte 4, just not
-///                nameable as a struct field; reads and writes go
-///                through memory: spill the value to a stack slot, then
-///                use a byte-precise pointer. No slot, but no lie.
-/// ```
-///
-/// Gaps between placed fields, and the tail, are covered with explicit
-/// `[N x i8]` filler so the struct's size is exactly rustc's no matter
-/// what LLVM's own layout rules would have done.
-///
-/// Direct and Niche carriers are claimed first, so a semantic field with a
-/// different SSA type cannot redefine the same physical bytes. Single and
-/// Empty layouts simply have no carrier. Unknown layouts are rejected.
-///
-/// If the finished struct's size does not come out equal to rustc's,
-/// something is deeply wrong and lowering would miscompile, so that is a
-/// hard error rather than a debug assertion.
-pub(crate) fn build_enum_slot_map(
-    ctx: &mut Context,
-    ty: TypeHandle,
-) -> Result<EnumSlotMap, anyhow::Error> {
-    let (
-        name,
-        discriminant_ty,
-        all_field_types,
-        all_field_offsets,
-        all_field_sizes,
-        variant_field_counts,
-        variant_inhabited,
-        tag_offset,
-        total_size,
-        abi_align,
-        layout_kind,
-        carrier_kind,
-        carrier_width,
-        carrier_address_space,
-    ) = {
-        let ty_ref = ty.deref(ctx);
-        let enum_ty = ty_ref
-            .downcast_ref::<MirEnumType>()
-            .ok_or_else(|| anyhow::anyhow!("build_enum_slot_map: expected MirEnumType"))?;
-        (
-            enum_ty.name().to_string(),
-            enum_ty.discriminant_ty,
-            enum_ty.all_field_types.clone(),
-            enum_ty.all_field_offsets.clone(),
-            enum_ty.all_field_sizes.clone(),
-            enum_ty.variant_field_counts.clone(),
-            enum_ty.variant_inhabited.clone(),
-            enum_ty.tag_offset(),
-            enum_ty.total_size(),
-            enum_ty.abi_align(),
-            enum_ty.layout_kind,
-            enum_ty.carrier_kind,
-            enum_ty.carrier_width,
-            enum_ty.carrier_address_space,
-        )
-    };
-
-    if layout_kind == EnumLayoutKind::Unknown {
-        return Err(anyhow::anyhow!(
-            "enum slot map: `{}` has unknown physical layout; refusing to guess its bytes",
-            name
-        ));
-    }
-    if carrier_kind == EnumCarrierKind::Pointer
-        && carrier_address_space == llvm_types::address_space::SHARED
-    {
-        return Err(anyhow::anyhow!(
-            "enum slot map: `{}` uses a shared-memory pointer carrier whose size is target-mode dependent (64-bit PTX/legacy, 32-bit modern NVVM); refusing target-agnostic enum lowering",
-            name
-        ));
-    }
-    if carrier_kind == EnumCarrierKind::Integer && !carrier_width.is_multiple_of(8) {
-        return Err(anyhow::anyhow!(
-            "enum slot map: `{}` integer carrier width {} is not a whole number of bytes; refusing physical storage with unspecified upper byte bits",
-            name,
-            carrier_width
-        ));
-    }
-
-    let carrier_ty: Option<TypeHandle> = match carrier_kind {
-        EnumCarrierKind::None => None,
-        EnumCarrierKind::Integer if layout_kind == EnumLayoutKind::Direct => {
-            let converted = convert_type(ctx, discriminant_ty)?;
-            let width = converted
-                .deref(ctx)
-                .downcast_ref::<IntegerType>()
-                .map(IntegerType::width);
-            if width != Some(carrier_width) {
-                return Err(anyhow::anyhow!(
-                    "enum slot map: `{}` direct carrier does not match its declared discriminant type",
-                    name
-                ));
-            }
-            Some(converted)
-        }
-        EnumCarrierKind::Integer => {
-            Some(IntegerType::get(ctx, carrier_width, Signedness::Signless).into())
-        }
-        EnumCarrierKind::Pointer => {
-            Some(llvm_types::PointerType::get(ctx, carrier_address_space).into())
-        }
-    };
-    let mut field_llvm_types = Vec::with_capacity(all_field_types.len());
-    for &field_ty in &all_field_types {
-        field_llvm_types.push(convert_type(ctx, field_ty)?);
-    }
-
-    if all_field_offsets.len() != all_field_types.len()
-        || all_field_sizes.len() != all_field_types.len()
-    {
-        return Err(anyhow::anyhow!(
-            "enum slot map: `{}` has {} field offsets for {} fields",
-            name,
-            all_field_offsets.len().min(all_field_sizes.len()),
-            all_field_types.len()
-        ));
-    }
-
-    // Phase 1: decide who gets a struct slot. The physical carrier goes
-    // first so a semantic field can never claim its bytes using a different
-    // type (e.g. `bool` is i1 semantically but i8 in Option<bool> storage).
-    // claims: (byte position, byte size, converted type), no two overlap.
-    let mut claims: Vec<(u64, u64, TypeHandle)> = Vec::new();
-    let carrier_claim = if let Some(carrier_ty) = carrier_ty {
-        let (carrier_size, carrier_align) =
-            llvm_type_size_align(ctx, carrier_ty).ok_or_else(|| {
-                anyhow::anyhow!(
-                    "enum slot map: `{}` carrier has unsupported LLVM layout",
-                    name
-                )
-            })?;
-        let expected_size = u64::from(carrier_width).div_ceil(8);
-        if carrier_size != expected_size
-            || tag_offset % carrier_align.max(1) != 0
-            || tag_offset
-                .checked_add(carrier_size)
-                .is_none_or(|end| end > total_size)
-        {
-            return Err(anyhow::anyhow!(
-                "enum slot map: `{}` carrier (size {}, align {}) cannot sit at byte {} of {}",
-                name,
-                carrier_size,
-                carrier_align,
-                tag_offset,
-                total_size
-            ));
-        }
-        claims.push((tag_offset, carrier_size, carrier_ty));
-        Some(0usize)
-    } else {
-        None
-    };
-
-    let mut claim_of_field: Vec<Option<usize>> = vec![None; field_llvm_types.len()];
-    let mut field_is_inhabited = Vec::with_capacity(field_llvm_types.len());
-    for (variant, count) in variant_field_counts.iter().enumerate() {
-        field_is_inhabited.extend(std::iter::repeat_n(
-            variant_inhabited.get(variant).copied().unwrap_or(0) != 0,
-            *count as usize,
-        ));
-    }
-    let mut order: Vec<usize> = (0..field_llvm_types.len()).collect();
-    // At one byte position, prefer a representation that preserves all of
-    // its stored bits. This makes the result independent of source-variant
-    // order and prevents an i1/bool view from claiming storage that a later
-    // i8 view needs to preserve. A scalar i1 always uses an i8 storage claim:
-    // construction explicitly zero-extends that scalar below.
-    order.sort_by_key(|&i| {
-        (
-            all_field_offsets[i],
-            !llvm_type_is_byte_faithful(ctx, field_llvm_types[i]),
-            i,
-        )
-    });
-    for flat in order {
-        if !field_is_inhabited.get(flat).copied().unwrap_or(false) {
-            continue;
-        }
-        let llvm_ty = field_llvm_types[flat];
-        // Enum payload storage uses one target-stable physical view. Shared
-        // pointer leaves become generic pointers recursively through LLVM
-        // structs (MIR structs/tuples) and bounded arrays, while bool leaves
-        // become canonical i8 bytes. Oversized shared-pointer arrays and
-        // pointer vectors fail closed here.
-        let storage_ty = enum_payload_storage_type(ctx, llvm_ty).map_err(|error| {
-            anyhow::anyhow!("enum slot map: `{}` field {}: {error}", name, flat)
-        })?;
-        let (size, align) = llvm_type_size_align(ctx, storage_ty).ok_or_else(|| {
-            anyhow::anyhow!(
-                "enum slot map: `{}` field {} has unsupported LLVM size/alignment",
-                name,
-                flat
-            )
-        })?;
-        if size != all_field_sizes[flat] {
-            return Err(anyhow::anyhow!(
-                "enum slot map: `{}` field {} lowers to {} bytes but rustc says {}",
-                name,
-                flat,
-                size,
-                all_field_sizes[flat]
-            ));
-        }
-        if size == 0 || is_zero_sized_type(ctx, llvm_ty) {
-            // ZSTs own no bytes and no slot.
-            continue;
-        }
-        let offset = all_field_offsets[flat];
-        if offset.checked_add(size).is_none_or(|end| end > total_size) {
-            return Err(anyhow::anyhow!(
-                "enum slot map: `{}` field {} (size {}) at byte {} exceeds total size {}",
-                name,
-                flat,
-                size,
-                offset,
-                total_size
-            ));
-        }
-        if !offset.is_multiple_of(align.max(1)) {
-            return Err(anyhow::anyhow!(
-                "enum slot map: `{}` field {} requires alignment {} but rustc offset {} is not aligned; packed enum payload access is not yet supported",
-                name,
-                flat,
-                align,
-                offset
-            ));
-        }
-
-        let is_scalar_i1 = llvm_ty
-            .deref(ctx)
-            .downcast_ref::<IntegerType>()
-            .is_some_and(|integer| integer.width() == 1);
-        // A bool the MIR type promises but the LLVM lowering hides (a union
-        // whose storage is a raw byte blob) cannot be canonicalized here:
-        // its bytes were written by the union's own stores, not by this
-        // enum's construction.
-        if !is_scalar_i1
-            && mir_type_contains_i1(ctx, all_field_types[flat])
-            && !llvm_type_contains_i1(ctx, llvm_ty)
-        {
-            return Err(anyhow::anyhow!(
-                "enum slot map: `{}` field {} contains bool storage hidden behind a union; cuda-oxide cannot prove those bytes are canonical",
-                name,
-                flat
-            ));
-        }
-
-        // Rust bool is a semantic i1 but occupies a complete byte in memory.
-        // Never make i1 the struct's physical storage type: give a standalone
-        // bool an i8 claim, or reuse the exact i8 carrier/field claim already
-        // covering that byte. Construction leaves the bool slotless and the
-        // deferred store below explicitly zero-extends i1 -> i8; extraction
-        // loads i1 from that byte.
-        if is_scalar_i1 {
-            let colliding_claims = claims
-                .iter()
-                .filter(|&&(o, s, _)| offset < o + s && o < offset + size)
-                .collect::<Vec<_>>();
-            if colliding_claims.is_empty() {
-                let byte_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
-                claims.push((offset, 1, byte_ty));
-                continue;
-            }
-            let has_exact_i8_storage = colliding_claims.iter().all(|&&(o, s, claim_ty)| {
-                o == offset
-                    && s == 1
-                    && claim_ty
-                        .deref(ctx)
-                        .downcast_ref::<IntegerType>()
-                        .is_some_and(|integer| integer.width() == 8)
-            });
-            if has_exact_i8_storage {
-                continue;
-            }
-            return Err(anyhow::anyhow!(
-                "enum slot map: `{}` scalar bool field {} overlaps storage other than one exact i8 byte; refusing to expose non-canonical bool bits",
-                name,
-                flat
-            ));
-        }
-
-        // Aggregates containing bool claim their byte-faithful twin (every
-        // i1 leaf becomes its canonical i8 memory byte) and stay slotless:
-        // construction canonicalizes the value and writes it at its byte
-        // offset; extraction re-loads the original type from the canonical
-        // bytes, exactly like the scalar-bool path above.
-        // Bool-bearing aggregates remain slotless so their canonical byte view
-        // continues through the established spill path. Pointer-only nested
-        // aggregates may own a slot because construction/extraction now rebuild
-        // them recursively at the semantic/physical boundary.
-        let field_gets_slot = !llvm_type_contains_i1(ctx, llvm_ty);
-
-        // Another variant already placed the same storage type at the same
-        // position? Then both fields can simply use that claim: variants
-        // share bytes, and here they even agree on the type.
-        if let Some(ci) = claims
-            .iter()
-            .position(|&(o, _, t)| o == offset && t == storage_ty)
-        {
-            if field_gets_slot {
-                claim_of_field[flat] = Some(ci);
-            }
-            continue;
-        }
-        // The bytes are taken by a different type. Pointer-free values can
-        // use the memory fallback below. Pointer-bearing values may do so only
-        // when a physical-layout walk proves that every pointer leaf exactly
-        // matches an existing pointer slot. This is the common
-        // `Option<(usize, &T)>` shape: the niche carrier is the tuple's pointer
-        // field. A pointer/non-pointer overlap, address-space mismatch, or
-        // additional pointer without a pointer slot still fails closed.
-        let colliding_claims = claims
-            .iter()
-            .filter(|&&(o, s, _)| offset < o + s && o < offset + size)
-            .collect::<Vec<_>>();
-        if !colliding_claims.is_empty() {
-            let has_pointer_overlap = llvm_type_contains_pointer(ctx, storage_ty)
-                || colliding_claims
-                    .iter()
-                    .any(|&&(_, _, claim_ty)| llvm_type_contains_pointer(ctx, claim_ty));
-            // Pointer-bearing overlaps must back every pointer leaf with a real
-            // `ptr` slot so the memory round-trip preserves provenance. The
-            // niche carrier backs the leaf that coincides with it; any further
-            // pointer leaf (the extra slice pointer in `split_at_mut_checked`'s
-            // `Option<(&mut [T], &mut [T])>`) gets its own fresh `ptr` slot.
-            // `ProvenanceLoss` means a pointer punned against non-pointer
-            // bits, which stays fail-closed; `OverArrayLeafBound` reports the
-            // same bounded rewrite contract as the payload storage gate.
-            let extra_pointer_claims = if has_pointer_overlap {
-                match analyze_pointer_overlap(ctx, offset, size, storage_ty, &colliding_claims) {
-                    Ok(extra) => extra,
-                    Err(PointerOverlapRejection::OverArrayLeafBound { required }) => {
-                        return Err(anyhow::anyhow!(
-                            "enum slot map: `{}` field {} overlaps pointer storage whose arrays are not supported above the bounded rewrite limit; rewrite requires {required} pointer conversions, supported bound is {MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES}",
-                            name,
-                            flat
-                        ));
-                    }
-                    Err(PointerOverlapRejection::ProvenanceLoss) => {
-                        return Err(anyhow::anyhow!(
-                            "enum slot map: `{}` has overlapping pointer and non-identical storage at byte {}; refusing to erase LLVM pointer provenance",
-                            name,
-                            offset
-                        ));
-                    }
-                }
-            } else {
-                Vec::new()
-            };
-            let incoming_is_byte_faithful = llvm_type_is_byte_faithful(ctx, storage_ty);
-            let claims_are_byte_faithful = colliding_claims
-                .iter()
-                .all(|&&(_, _, claim_ty)| llvm_type_is_byte_faithful(ctx, claim_ty));
-            if !incoming_is_byte_faithful || !claims_are_byte_faithful {
-                return Err(anyhow::anyhow!(
-                    "enum slot map: `{}` field {} overlaps non-identical storage but its lowered type is not byte-faithful (for example, it may contain implicit padding); refusing a type-punned store",
-                    name,
-                    flat
-                ));
-            }
-            // Back each extra pointer leaf with its own `ptr` slot (the field
-            // itself stays slotless and round-trips through memory). Added after
-            // the byte-faithfulness gate so `colliding_claims`'s borrow of
-            // `claims` has ended before we push.
-            for leaf in extra_pointer_claims {
-                let ptr_ty = llvm_types::PointerType::get(ctx, leaf.address_space).into();
-                claims.push((leaf.offset, leaf.size, ptr_ty));
-            }
-            continue;
-        }
-        claims.push((offset, size, storage_ty));
-        if field_gets_slot {
-            claim_of_field[flat] = Some(claims.len() - 1);
-        }
-    }
-
-    // Phase 2: lay the slots down in byte order, filling every gap (and
-    // the tail) so the struct's size is exactly rustc's. One integer per gap
-    // where that is layout-neutral, else [N x i8]; see `make_enum_filler_type`.
-    let mut emit_order: Vec<usize> = (0..claims.len()).collect();
-    emit_order.sort_by_key(|&ci| claims[ci].0);
-    let mut llvm_fields: Vec<TypeHandle> = Vec::new();
-    let mut slot_of_claim: Vec<u32> = vec![0; claims.len()];
-    let mut current_offset: u64 = 0;
-    for &ci in &emit_order {
-        let (offset, size, llvm_ty) = claims[ci];
-        if current_offset < offset {
-            let filler =
-                make_enum_filler_type(ctx, current_offset, offset - current_offset, abi_align);
-            llvm_fields.push(filler);
-            current_offset = offset;
-        }
-        slot_of_claim[ci] = llvm_fields.len() as u32;
-        llvm_fields.push(llvm_ty);
-        current_offset += size;
-    }
-    if current_offset < total_size {
-        let filler =
-            make_enum_filler_type(ctx, current_offset, total_size - current_offset, abi_align);
-        llvm_fields.push(filler);
-    }
-
-    // Sanity: the struct we just built must be exactly rustc's size.
-    // Arrays of enums step by this size, so a mismatch means every
-    // element after the first is read from the wrong place. That is a
-    // guaranteed miscompile, hence a hard error, not a debug check.
-    let (_end, natural_size, natural_align) = natural_struct_layout(ctx, &llvm_fields)
-        .ok_or_else(|| anyhow::anyhow!("enum slot map: `{}` has unsupported LLVM layout", name))?;
-    if natural_size != total_size {
-        return Err(anyhow::anyhow!(
-            "enum slot map: `{}` lowered to {} bytes but rustc says {}",
-            name,
-            natural_size,
-            total_size
-        ));
-    }
-    let required_align = abi_align.max(1);
-    if natural_align > required_align {
-        return Err(anyhow::anyhow!(
-            "enum slot map: `{}` lowered with alignment {} but rustc requires {}; explicit over-aligned enum storage is not yet supported",
-            name,
-            natural_align,
-            abi_align
-        ));
-    }
-    if natural_align < required_align {
-        // The byte claims alone can under-align the storage, e.g. when the
-        // only claim is an i8 niche carrier inside a 4-aligned enum. Raise
-        // the struct's alignment with a zero-length anchor field, the same
-        // mechanism union storage uses; it occupies no bytes, so every slot
-        // index simply shifts by one.
-        let anchor_int = IntegerType::get(ctx, (required_align * 8) as u32, Signedness::Signless);
-        let anchor: TypeHandle = llvm_types::ArrayType::get(ctx, anchor_int.into(), 0).into();
-        llvm_fields.insert(0, anchor);
-        for slot in &mut slot_of_claim {
-            *slot += 1;
-        }
-    }
-
-    let field_slots = claim_of_field
-        .into_iter()
-        .map(|c| c.map(|ci| slot_of_claim[ci]))
-        .collect();
-    Ok(EnumSlotMap {
-        llvm_struct_ty: llvm_types::StructType::get_unnamed(
-            ctx,
-            (llvm_fields, llvm_types::StructLayout::Unpacked),
-        )
-        .into(),
-        carrier_slot: carrier_claim.map(|claim| slot_of_claim[claim]),
-        carrier_llvm_ty: carrier_ty,
-        field_slots,
-        field_offsets: all_field_offsets,
-        field_llvm_types,
-    })
-}
-
-/// Convert a `MirEnumType` to its LLVM struct representation.
-///
-/// Thin wrapper over [`build_enum_slot_map`], which explains the layout.
-/// Any op that needs an index into the converted enum must take it from
-/// the slot map, never compute it by hand.
-pub(crate) fn convert_enum_to_llvm(
-    ctx: &mut Context,
-    ty: TypeHandle,
-) -> Result<TypeHandle, anyhow::Error> {
-    Ok(build_enum_slot_map(ctx, ty)?.llvm_struct_ty)
-}
-
-/// Return an enum name only when the dialect lacks rustc's physical layout.
-/// All importer-produced Direct, Niche, Single, and Empty layouts are
-/// byte-faithful; legacy `Unknown` values are rejected everywhere rather than
-/// receiving a guessed internal representation.
-pub(crate) fn enum_unmodeled_in_memory(ctx: &Context, ty: TypeHandle) -> Option<String> {
-    let ty_ref = ty.deref(ctx);
-    let enum_ty = ty_ref.downcast_ref::<MirEnumType>()?;
-    (enum_ty.layout_kind == EnumLayoutKind::Unknown).then(|| enum_ty.name().to_string())
-}
-
-/// Search a kernel parameter's type for an enum the host and device
-/// would disagree about (see [`enum_unmodeled_in_memory`]).
-///
-/// The search looks everywhere host data can hide: behind pointers,
-/// inside slices and arrays, in struct/tuple fields, and in other enums'
-/// payloads. It returns the first offending enum's name.
-///
-/// Kernel signatures are checked early for a focused diagnostic. Lowering also
-/// rejects Unknown layouts for locals, globals, and physical operations, so no
-/// guessed representation can escape through an internal-only path.
-///
-/// `visited` breaks cycles through recursive types (`TypeHandle` is
-/// interned, so equality is identity).
-pub(crate) fn find_unmodeled_enum_in_abi(
-    ctx: &mut Context,
-    ty: TypeHandle,
-    visited: &mut Vec<TypeHandle>,
-) -> Result<Option<String>, anyhow::Error> {
-    if visited.contains(&ty) {
-        return Ok(None);
-    }
-    visited.push(ty);
-
-    if let Some(name) = enum_unmodeled_in_memory(ctx, ty) {
-        return Ok(Some(name));
-    }
-
-    let children: Vec<TypeHandle> = {
-        let ty_ref = ty.deref(ctx);
-        if let Some(p) = ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>() {
-            vec![p.pointee]
-        } else if let Some(s) = ty_ref.downcast_ref::<MirSliceType>() {
-            vec![s.element_ty]
-        } else if let Some(s) = ty_ref.downcast_ref::<MirDisjointSliceType>() {
-            let mut nested = vec![s.element_ty];
-            nested.extend_from_slice(&s.space_tys);
-            nested
-        } else if let Some(a) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
-            vec![a.element_ty]
-        } else if let Some(s) = ty_ref.downcast_ref::<MirStructType>() {
-            s.field_types.clone()
-        } else if let Some(u) = ty_ref.downcast_ref::<MirUnionType>() {
-            u.field_types.clone()
-        } else if let Some(t) = ty_ref.downcast_ref::<MirTupleType>() {
-            t.get_types().to_vec()
-        } else if let Some(e) = ty_ref.downcast_ref::<MirEnumType>() {
-            e.all_field_types.clone()
-        } else {
-            vec![]
-        }
-    };
-
-    for child in children {
-        if let Some(name) = find_unmodeled_enum_in_abi(ctx, child, visited)? {
-            return Ok(Some(name));
-        }
-    }
-    Ok(None)
-}
-
-/// Prove that an initialized Rust global can be accessed through the LLVM
-/// semantic type produced by this lowering pipeline.
-///
-/// The initializer itself is emitted as exact bytes. That is only half of the
-/// contract: later field GEPs and typed loads still use `mir_ty`. If that type
-/// places a field at a different byte offset, an exact initializer can still be
-/// read incorrectly (or even past the end of the object). Reject every shape
-/// for which we cannot prove that the two views agree.
-pub(crate) fn validate_initialized_global_layout(
-    ctx: &mut Context,
-    mir_ty: TypeHandle,
-    initializer_size: u64,
-    initializer_align: u64,
-) -> Result<(), anyhow::Error> {
-    if initializer_align == 0 || !initializer_align.is_power_of_two() {
-        return Err(anyhow::anyhow!(
-            "initialized global has invalid rustc allocation alignment {}",
-            initializer_align
-        ));
-    }
-
-    validate_initialized_global_type(ctx, mir_ty, &mut Vec::new())?;
-
-    let llvm_ty = convert_type(ctx, mir_ty)?;
-    let (llvm_size, llvm_align) = llvm_type_size_align(ctx, llvm_ty)
-        .ok_or_else(|| anyhow::anyhow!("initialized global has unsupported LLVM size/alignment"))?;
-    if llvm_size != initializer_size || llvm_align > initializer_align {
-        return Err(anyhow::anyhow!(
-            "initialized global type is not byte-compatible with rustc's allocation: the lowered LLVM value has size/alignment {}/{}, but the initializer has size/alignment {}/{}",
-            llvm_size,
-            llvm_align,
-            initializer_size,
-            initializer_align
-        ));
-    }
-
-    Ok(())
-}
-
-/// Validate an initialized global that carries pointer relocations.
-///
-/// Ordinary initialized globals keep their existing conservative semantic
-/// layout validator. Relocated globals use a separate segmented physical
-/// carrier, so a top-level `repr(packed)` struct may use that relocation path
-/// as long as rustc's field ranges are explicit, non-overlapping, and in-bounds.
-/// One direct nested struct may use the same relaxation when the top-level
-/// struct itself has an ordinary, non-divergent LLVM layout and the child's
-/// LLVM packed representation exactly reproduces rustc's offsets and size. A
-/// packed top-level struct may not stack the relaxation on a packed child, and
-/// deeper packed nesting remains on the ordinary fail-closed path.
-pub(crate) fn validate_relocated_initialized_global_layout(
-    ctx: &mut Context,
-    mir_ty: TypeHandle,
-    initializer_size: u64,
-    initializer_align: u64,
-) -> Result<(), anyhow::Error> {
-    match validate_initialized_global_layout(ctx, mir_ty, initializer_size, initializer_align) {
-        Ok(()) => Ok(()),
-        Err(original_error) => {
-            if initializer_align == 0 || !initializer_align.is_power_of_two() {
-                return Err(original_error);
-            }
-
-            let struct_ty = {
-                let ty_ref = mir_ty.deref(ctx);
-                ty_ref.downcast_ref::<MirStructType>().cloned()
-            };
-            let Some(struct_ty) = struct_ty else {
-                return Err(original_error);
-            };
-            if !struct_ty.has_explicit_layout()
-                || struct_ty.total_size() != initializer_size
-                || struct_ty.abi_align != initializer_align
-            {
-                return Err(original_error);
-            }
-
-            validate_relocated_struct_field_ranges(ctx, &struct_ty)?;
-
-            let top_level_layout = StructLayoutInfo::of_struct(&struct_ty);
-            let top_level_map = build_struct_slot_map(ctx, &top_level_layout)?;
-            let top_level_is_ordinary = !top_level_map.layout_diverges
-                && top_level_map.by_value_layout_faithful
-                && top_level_map
-                    .llvm_struct_ty
-                    .deref(ctx)
-                    .downcast_ref::<llvm_types::StructType>()
-                    .is_some_and(|ty| ty.layout() == llvm_types::StructLayout::Unpacked);
-
-            let mut visited = vec![mir_ty];
-            for field_ty in struct_ty.field_types.iter().copied() {
-                if top_level_is_ordinary {
-                    validate_relocated_initialized_global_child(ctx, field_ty, &mut visited)?;
-                } else {
-                    validate_initialized_global_type(ctx, field_ty, &mut visited)?;
-                }
-            }
-            Ok(())
-        }
-    }
-}
-
-/// Prove that rustc's explicit field ranges for a relocated top-level struct
-/// are non-overlapping and fit within the evaluated allocation.
-fn validate_relocated_struct_field_ranges(
-    ctx: &mut Context,
-    struct_ty: &MirStructType,
-) -> Result<(), anyhow::Error> {
-    let layout = StructLayoutInfo::of_struct(struct_ty);
-
-    // Relocated globals relax only natural LLVM placement. Preserve the
-    // ordinary struct-layout metadata invariants before accepting rustc's
-    // explicit byte ranges as the physical initializer contract.
-    build_struct_slot_map(ctx, &layout)?;
-
-    let mut ranges = Vec::with_capacity(layout.field_types.len());
-    for (decl_index, field_ty) in layout.field_types.iter().copied().enumerate() {
-        let field_size = if let Some(size) = mir_stored_size(ctx, field_ty) {
-            size
-        } else {
-            let llvm_ty = convert_type(ctx, field_ty)?;
-            llvm_type_size_align(ctx, llvm_ty)
-                .map(|(size, _)| size)
-                .ok_or_else(|| {
-                    anyhow::anyhow!(
-                        "relocated initialized struct `{}` field {} has unsupported size",
-                        struct_ty.name(),
-                        decl_index
-                    )
-                })?
-        };
-        if field_size == 0 {
-            continue;
-        }
-
-        let start = layout.field_offsets[decl_index];
-        let end = start.checked_add(field_size).ok_or_else(|| {
-            anyhow::anyhow!(
-                "relocated initialized struct `{}` field {} range overflows",
-                struct_ty.name(),
-                decl_index
-            )
-        })?;
-        if end > layout.total_size {
-            return Err(anyhow::anyhow!(
-                "relocated initialized struct `{}` field {} occupies bytes {}..{}, but the allocation is only {} bytes",
-                struct_ty.name(),
-                decl_index,
-                start,
-                end,
-                layout.total_size
-            ));
-        }
-        ranges.push((start, end, decl_index));
-    }
-
-    ranges.sort_by_key(|(start, _, _)| *start);
-    for pair in ranges.windows(2) {
-        let (_, previous_end, previous_index) = pair[0];
-        let (next_start, _, next_index) = pair[1];
-        if next_start < previous_end {
-            return Err(anyhow::anyhow!(
-                "relocated initialized struct `{}` fields {} and {} overlap in rustc's byte layout",
-                struct_ty.name(),
-                previous_index,
-                next_index
-            ));
-        }
-    }
-
-    Ok(())
-}
-
-/// Validate one direct child of an ordinary relocated initialized global.
-///
-/// The ordinary initialized-global validator remains the default. Only when it
-/// rejects a direct `MirStructType` do we consider the relocation-specific
-/// relaxation, and only if `build_struct_slot_map` proves that the divergent
-/// rustc layout is represented exactly by an LLVM packed struct. Its own field
-/// ranges must still be explicit, non-overlapping, and in-bounds. Children of
-/// that packed struct go back through the ordinary validator, deliberately
-/// limiting this exception to one nesting level.
-fn validate_relocated_initialized_global_child(
-    ctx: &mut Context,
-    mir_ty: TypeHandle,
-    visited: &mut Vec<TypeHandle>,
-) -> Result<(), anyhow::Error> {
-    if visited.contains(&mir_ty) {
-        return Ok(());
-    }
-
-    let mut ordinary_visited = visited.clone();
-    let original_error = match validate_initialized_global_type(ctx, mir_ty, &mut ordinary_visited)
-    {
-        Ok(()) => {
-            *visited = ordinary_visited;
-            return Ok(());
-        }
-        Err(error) => error,
-    };
-
-    let struct_ty = {
-        let ty_ref = mir_ty.deref(ctx);
-        ty_ref.downcast_ref::<MirStructType>().cloned()
-    };
-    let Some(struct_ty) = struct_ty else {
-        return Err(original_error);
-    };
-    if !struct_ty.has_explicit_layout() {
-        return Err(original_error);
-    }
-
-    let layout = StructLayoutInfo::of_struct(&struct_ty);
-    let map = build_struct_slot_map(ctx, &layout)?;
-    let is_exact_packed = map.layout_diverges
-        && map.by_value_layout_faithful
-        && map
-            .llvm_struct_ty
-            .deref(ctx)
-            .downcast_ref::<llvm_types::StructType>()
-            .is_some_and(|ty| ty.layout() == llvm_types::StructLayout::Packed);
-    if !is_exact_packed {
-        return Err(original_error);
-    }
-
-    validate_relocated_struct_field_ranges(ctx, &struct_ty)?;
-
-    visited.push(mir_ty);
-    for field_ty in struct_ty.field_types.iter().copied() {
-        validate_initialized_global_type(ctx, field_ty, visited)?;
-    }
-    Ok(())
-}
-
-fn validate_initialized_global_type(
-    ctx: &mut Context,
-    mir_ty: TypeHandle,
-    visited: &mut Vec<TypeHandle>,
-) -> Result<(), anyhow::Error> {
-    if visited.contains(&mir_ty) {
-        return Ok(());
-    }
-    visited.push(mir_ty);
-
-    if let Some(name) = enum_unmodeled_in_memory(ctx, mir_ty) {
-        return Err(anyhow::anyhow!(
-            "initialized global contains enum `{}` with unknown physical layout; refusing to guess a byte representation",
-            name
-        ));
-    }
-
-    enum Kind {
-        Struct(MirStructType),
-        Tuple(MirTupleType),
-        Enum(MirEnumType),
-        Array { element_ty: TypeHandle, size: u64 },
-        Leaf,
-    }
-
-    let kind = {
-        let ty_ref = mir_ty.deref(ctx);
-        if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
-            Kind::Struct(struct_ty.clone())
-        } else if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
-            Kind::Tuple(tuple_ty.clone())
-        } else if let Some(enum_ty) = ty_ref.downcast_ref::<MirEnumType>() {
-            Kind::Enum(enum_ty.clone())
-        } else if let Some(array_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
-            Kind::Array {
-                element_ty: array_ty.element_ty,
-                size: array_ty.size,
-            }
-        } else {
-            Kind::Leaf
-        }
-    };
-
-    match kind {
-        Kind::Struct(struct_ty) => {
-            validate_initialized_struct_layout(ctx, mir_ty, &struct_ty)?;
-            for field_ty in struct_ty.field_types {
-                validate_initialized_global_type(ctx, field_ty, visited)?;
-            }
-        }
-        Kind::Tuple(tuple_ty) => {
-            if !tuple_ty.get_types().is_empty() {
-                // Tuples carry rustc's field offsets exactly like structs;
-                // prove the lowered aggregate reproduces them byte-for-byte.
-                let layout = StructLayoutInfo::of_tuple(&tuple_ty);
-                validate_initialized_aggregate_layout(
-                    ctx,
-                    mir_ty,
-                    "tuple",
-                    "tuple",
-                    &layout,
-                    tuple_ty.abi_align(),
-                    tuple_ty.has_explicit_layout(),
-                )?;
-            }
-            for field_ty in tuple_ty.get_types().iter().copied() {
-                validate_initialized_global_type(ctx, field_ty, visited)?;
-            }
-        }
-        Kind::Enum(enum_ty) => {
-            if enum_ty.total_size() > 0 {
-                let llvm_ty = convert_type(ctx, mir_ty)?;
-                let (llvm_size, llvm_align) =
-                    llvm_type_size_align(ctx, llvm_ty).ok_or_else(|| {
-                        anyhow::anyhow!(
-                            "initialized enum `{}` has unsupported LLVM size/alignment",
-                            enum_ty.name()
-                        )
-                    })?;
-                if llvm_size != enum_ty.total_size() || llvm_align > enum_ty.abi_align() {
-                    return Err(anyhow::anyhow!(
-                        "initialized enum `{}` is not byte-compatible with rustc's layout: the lowered LLVM value has size/alignment {}/{}, but rustc requires {}/{}",
-                        enum_ty.name(),
-                        llvm_size,
-                        llvm_align,
-                        enum_ty.total_size(),
-                        enum_ty.abi_align()
-                    ));
-                }
-            }
-            for field_ty in enum_ty.all_field_types {
-                validate_initialized_global_type(ctx, field_ty, visited)?;
-            }
-        }
-        Kind::Array { element_ty, size } => {
-            // A zero-length array contributes no element bytes. Its outer LLVM
-            // size/alignment is still checked by
-            // `validate_initialized_global_layout`, but recursively rejecting
-            // an element layout would incorrectly reject valid promoted
-            // `&mut [Packed; 0]` constants whose physical allocation is empty.
-            if size != 0 {
-                validate_initialized_global_type(ctx, element_ty, visited)?;
-            }
-        }
-        Kind::Leaf => {}
-    }
-
-    Ok(())
-}
-
-fn validate_initialized_struct_layout(
-    ctx: &mut Context,
-    mir_ty: TypeHandle,
-    struct_ty: &MirStructType,
-) -> Result<(), anyhow::Error> {
-    let has_layout = struct_ty.has_explicit_layout();
-    let layout = StructLayoutInfo::of_struct(struct_ty);
-    let name = struct_ty.name().to_string();
-    validate_initialized_aggregate_layout(
-        ctx,
-        mir_ty,
-        "struct",
-        &name,
-        &layout,
-        struct_ty.abi_align,
-        has_layout,
-    )
-}
-
-/// Shared byte-layout validation for initialized-global structs and tuples.
-///
-/// Proves that the lowered LLVM aggregate places every field at exactly the
-/// byte offset rustc chose and matches rustc's total size, so a constant
-/// initializer written slot-by-slot reproduces the host bytes.
-#[allow(clippy::too_many_arguments)]
-fn validate_initialized_aggregate_layout(
-    ctx: &mut Context,
-    mir_ty: TypeHandle,
-    kind_noun: &str,
-    name: &str,
-    layout: &StructLayoutInfo,
-    abi_align: u64,
-    has_explicit_layout: bool,
-) -> Result<(), anyhow::Error> {
-    if layout.total_size == 0 {
-        let llvm_ty = convert_type(ctx, mir_ty)?;
-        let (llvm_size, _) = llvm_type_size_align(ctx, llvm_ty).ok_or_else(|| {
-            anyhow::anyhow!(
-                "initialized {} `{}` has unsupported LLVM size/alignment",
-                kind_noun,
-                name
-            )
-        })?;
-        if llvm_size == 0 {
-            return Ok(());
-        }
-        return Err(anyhow::anyhow!(
-            "initialized {} `{}` has no stored size but lowers to {} bytes",
-            kind_noun,
-            name,
-            llvm_size
-        ));
-    }
-    if !has_explicit_layout {
-        return Err(anyhow::anyhow!(
-            "initialized {} `{}` has no rustc field-offset metadata",
-            kind_noun,
-            name
-        ));
-    }
-
-    let slots = build_struct_slot_map(ctx, layout)?;
-    let llvm_fields: Vec<_> = slots
-        .llvm_struct_ty
-        .deref(ctx)
-        .downcast_ref::<llvm_types::StructType>()
-        .expect("aggregate slot map must produce an LLVM struct")
-        .fields()
-        .collect();
-
-    let mut slot_offsets = Vec::with_capacity(llvm_fields.len());
-    let mut current_offset = 0u64;
-    for llvm_field in &llvm_fields {
-        let (field_size, field_align) =
-            llvm_type_size_align(ctx, *llvm_field).ok_or_else(|| {
-                anyhow::anyhow!(
-                    "initialized {} `{}` field has unsupported LLVM size/alignment",
-                    kind_noun,
-                    name
-                )
-            })?;
-        current_offset = current_offset.div_ceil(field_align.max(1)) * field_align.max(1);
-        slot_offsets.push(current_offset);
-        current_offset += field_size;
-    }
-
-    for (decl_index, slot) in slots.decl_to_llvm.iter().enumerate() {
-        let Some(slot) = slot else {
-            continue;
-        };
-        let actual_offset = slot_offsets[*slot as usize];
-        let expected_offset = layout.field_offsets[decl_index];
-        if actual_offset != expected_offset {
-            return Err(anyhow::anyhow!(
-                "initialized {} `{}` field {} lowers at byte {}, but rustc placed it at byte {}; packed and overlapping field layouts are not yet supported",
-                kind_noun,
-                name,
-                decl_index,
-                actual_offset,
-                expected_offset
-            ));
-        }
-    }
-
-    let (llvm_size, llvm_align) =
-        llvm_type_size_align(ctx, slots.llvm_struct_ty).ok_or_else(|| {
-            anyhow::anyhow!(
-                "initialized {} `{}` has unsupported LLVM size/alignment",
-                kind_noun,
-                name
-            )
-        })?;
-    if llvm_size != layout.total_size || llvm_align > abi_align {
-        return Err(anyhow::anyhow!(
-            "initialized {} `{}` lowers to size/alignment {}/{}, but rustc requires {}/{}",
-            kind_noun,
-            name,
-            llvm_size,
-            llvm_align,
-            layout.total_size,
-            abi_align
-        ));
-    }
-
-    Ok(())
-}
-
-/// Create the LLVM struct type used for slice representations.
-///
-/// Slices are represented as fat pointers: `{ ptr, i64 }` where:
-/// - `ptr` is a generic address space (0) pointer to the data
-/// - `i64` is the number of elements (not bytes)
-///
-/// # Layout
-///
-/// ```text
-/// struct {
-///     ptr: !llvm.ptr,     ; offset 0, size 8
-///     len: i64,           ; offset 8, size 8
-/// }                       ; total size: 16 bytes
-/// ```
-///
-/// # Address Space
-///
-/// The pointer uses generic address space (0) because:
-/// - Slices passed to kernels may point to global memory
-/// - The kernel doesn't know at compile time which memory space
-/// - Generic pointers can be used with any memory type
-///
-/// # Usage
-///
-/// This type is used for:
-/// - `&[T]` slice arguments
-/// - `DisjointSlice<T>` (unique-ownership slice) arguments
-/// - Any other fat pointer representation
-pub(crate) fn make_slice_struct(ctx: &mut Context) -> TypeHandle {
-    let ptr_ty = llvm_types::PointerType::get_generic(ctx);
-    let len_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-    llvm_types::StructType::get_unnamed(
-        ctx,
-        (
-            vec![ptr_ty.into(), len_ty.into()],
-            llvm_types::StructLayout::Unpacked,
-        ),
-    )
-    .into()
-}
-
-/// The fat pointer, followed by an index space's runtime layout fields.
-///
-/// With no such fields this is exactly [`make_slice_struct`], so a slice over
-/// an index space fixed in its type keeps its two-field representation.
-pub(crate) fn make_disjoint_slice_struct(
-    ctx: &mut Context,
-    space_tys: &[TypeHandle],
-) -> anyhow::Result<TypeHandle> {
-    if space_tys.is_empty() {
-        return Ok(make_slice_struct(ctx));
-    }
-    let ptr_ty = llvm_types::PointerType::get_generic(ctx);
-    let len_ty = IntegerType::get(ctx, 64, Signedness::Signless);
-    let mut fields: Vec<TypeHandle> = vec![ptr_ty.into(), len_ty.into()];
-    for space_ty in space_tys {
-        fields.push(convert_type(ctx, *space_ty)?);
-    }
-    Ok(
-        llvm_types::StructType::get_unnamed(ctx, (fields, llvm_types::StructLayout::Unpacked))
-            .into(),
-    )
-}
-
-#[cfg(test)]
-mod tests {
-    //! Hardware-free unit tests for [`build_struct_slot_map`]: the slot map
-    //! and the LLVM struct type are produced by the same walk, so these
-    //! tests pin down both for the layout shapes from issue #128.
-
-    use super::*;
-    use dialect_mir::types::{
-        EnumEncoding, EnumVariant, MirArrayType, MirEnumType, MirPtrType, MirStructType,
-        MirTupleType, MirUnionType, StructAbiKind,
-    };
-
-    fn make_ctx() -> Context {
-        let mut ctx = Context::new();
-        dialect_mir::register(&mut ctx);
-        crate::register(&mut ctx);
-        ctx
-    }
-
-    /// A MIR-level unsigned integer type (what the importer produces).
-    fn mir_uint(ctx: &mut Context, width: u32) -> TypeHandle {
-        IntegerType::get(ctx, width, Signedness::Unsigned).into()
-    }
-
-    /// A converted (signless) LLVM integer type.
-    fn llvm_int(ctx: &mut Context, width: u32) -> TypeHandle {
-        IntegerType::get(ctx, width, Signedness::Signless).into()
-    }
-
-    /// `[n x i8]` padding type, as `make_padding_type` builds it.
-    fn pad(ctx: &mut Context, n: u64) -> TypeHandle {
-        make_padding_type(ctx, n)
-    }
-
-    /// A zero-sized MIR struct (PhantomData shape).
-    fn mir_zst(ctx: &mut Context) -> TypeHandle {
-        MirStructType::get(ctx, "Phantom".into(), vec![], vec![]).into()
-    }
-
-    fn struct_fields(ctx: &Context, ty: TypeHandle) -> Vec<TypeHandle> {
-        ty.deref(ctx)
-            .downcast_ref::<llvm_types::StructType>()
-            .expect("expected an LLVM struct type")
-            .fields()
-            .collect()
-    }
-
-    fn transparent_u32(ctx: &mut Context, name: &str) -> TypeHandle {
-        let u32_ty = mir_uint(ctx, 32);
-        MirStructType::get_with_full_layout_and_abi(
-            ctx,
-            name.into(),
-            vec!["value".into()],
-            vec![u32_ty],
-            vec![0],
-            vec![0],
-            4,
-            4,
-            StructAbiKind::TransparentScalar,
-        )
-        .into()
-    }
-
-    #[test]
-    fn transparent_scalar_return_type_uses_underlying_scalar() {
-        let mut ctx = make_ctx();
-        let wrapper = transparent_u32(&mut ctx, "Scalar");
-        let func_ty = FunctionType::get(&ctx, vec![], vec![wrapper]);
-
-        let lowered = convert_function_type(&mut ctx, func_ty, false).unwrap();
-        let result_ty = lowered.deref(&ctx).result_type();
-        let result_ty_ref = result_ty.deref(&ctx);
-        let integer = result_ty_ref
-            .downcast_ref::<IntegerType>()
-            .expect("transparent u32 return must lower to an integer");
-        assert_eq!(integer.width(), 32);
-    }
-
-    #[test]
-    fn nested_transparent_scalar_abi_records_each_rebuild_layer() {
-        let mut ctx = make_ctx();
-        let inner = transparent_u32(&mut ctx, "Inner");
-        let outer: TypeHandle = MirStructType::get_with_full_layout_and_abi(
-            &mut ctx,
-            "Outer".into(),
-            vec!["inner".into()],
-            vec![inner],
-            vec![0],
-            vec![0],
-            4,
-            4,
-            StructAbiKind::TransparentScalar,
-        )
-        .into();
-
-        let info = transparent_scalar_abi_info(&mut ctx, outer).unwrap();
-        let scalar_ty_ref = info.scalar_ty.deref(&ctx);
-        let integer = scalar_ty_ref
-            .downcast_ref::<IntegerType>()
-            .expect("nested transparent wrapper must resolve to u32");
-        assert_eq!(integer.width(), 32);
-        assert_eq!(info.layers.len(), 2);
-        assert_eq!(info.layers[0].field_slot, 0);
-        assert_eq!(info.layers[1].field_slot, 0);
-    }
-
-    #[test]
-    fn ordinary_one_field_return_remains_aggregate() {
-        let mut ctx = make_ctx();
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let ordinary: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Ordinary".into(),
-            vec!["value".into()],
-            vec![u32_ty],
-            vec![0],
-            vec![0],
-            4,
-            4,
-        )
-        .into();
-        let func_ty = FunctionType::get(&ctx, vec![], vec![ordinary]);
-
-        let lowered = convert_function_type(&mut ctx, func_ty, false).unwrap();
-        assert!(
-            lowered
-                .deref(&ctx)
-                .result_type()
-                .deref(&ctx)
-                .is::<llvm_types::StructType>(),
-            "ordinary one-field structs must not be scalarized"
-        );
-    }
-
-    #[test]
-    fn mir_abi_alignment_recurses_through_nested_arrays() {
-        let mut ctx = make_ctx();
-        let byte = mir_uint(&mut ctx, 8);
-        let marker: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Align32".into(),
-            vec![],
-            vec![],
-            vec![],
-            vec![],
-            0,
-            32,
-        )
-        .into();
-        let tuple: TypeHandle = MirTupleType::get_with_layout(
-            &mut ctx,
-            vec![marker, byte],
-            vec![0, 1],
-            vec![0, 0],
-            32,
-            32,
-        )
-        .into();
-        let inner: TypeHandle = MirArrayType::get(&mut ctx, tuple, 2).into();
-        let outer: TypeHandle = MirArrayType::get(&mut ctx, inner, 3).into();
-        let plain: TypeHandle = MirArrayType::get(&mut ctx, byte, 4).into();
-
-        assert_eq!(mir_type_abi_align(&ctx, tuple), Some(32));
-        assert_eq!(mir_type_abi_align(&ctx, inner), Some(32));
-        assert_eq!(mir_type_abi_align(&ctx, outer), Some(32));
-        assert_eq!(mir_type_abi_align(&ctx, plain), None);
-    }
-
-    #[test]
-    fn union_storage_has_exact_size_alignment_and_stride() {
-        let mut ctx = make_ctx();
-        let u8_ty = mir_uint(&mut ctx, 8);
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let bytes_ty: TypeHandle = MirArrayType::get(&mut ctx, u8_ty, 4).into();
-        let union_ty = MirUnionType::get(
-            &mut ctx,
-            "Bits".into(),
-            vec!["word".into(), "bytes".into()],
-            vec![u32_ty, bytes_ty],
-            4,
-            4,
-        );
-        let union_data = union_ty.deref(&ctx).clone();
-        let storage = build_union_storage_type(&mut ctx, &union_data).unwrap();
-        assert_eq!(llvm_type_size_align(&ctx, storage), Some((4, 4)));
-
-        let union_handle: TypeHandle = union_ty.into();
-        let array: TypeHandle = MirArrayType::get(&mut ctx, union_handle, 3).into();
-        let llvm_array = convert_type(&mut ctx, array).unwrap();
-        assert_eq!(llvm_type_size_align(&ctx, llvm_array), Some((12, 4)));
-    }
-
-    #[test]
-    fn fixed_vector_layout_uses_packed_bit_width_and_rejects_unknown_widths() {
-        let mut ctx = make_ctx();
-        let i1 = llvm_int(&mut ctx, 1);
-        let v16i1: TypeHandle =
-            llvm_types::VectorType::get(&ctx, i1, 16, llvm_types::VectorTypeKind::Fixed).into();
-        assert_eq!(
-            llvm_type_size_align(&ctx, v16i1),
-            Some((2, 2)),
-            "<16 x i1> is 16 packed bits, not sixteen bytes"
-        );
-
-        let i8 = llvm_int(&mut ctx, 8);
-        let v3i8: TypeHandle =
-            llvm_types::VectorType::get(&ctx, i8, 3, llvm_types::VectorTypeKind::Fixed).into();
-        assert_eq!(
-            llvm_type_size_align(&ctx, v3i8),
-            None,
-            "the NVPTX data layout does not define a 24-bit vector alignment"
-        );
-    }
-
-    #[test]
-    fn enum_array_payload_keeps_exact_size_alignment_and_stride() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 8);
-        let element = mir_uint(&mut ctx, 16);
-        let payload: TypeHandle = MirArrayType::get(&mut ctx, element, 3).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "ArrayPayload".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("Empty".into()),
-                EnumVariant::new_with_layout("Data".into(), vec![payload], vec![2], vec![6]),
-            ],
-            0,
-            8,
-            2,
-        )
-        .into();
-        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((8, 2)));
-
-        let array: TypeHandle = MirArrayType::get(&mut ctx, enum_ty, 5).into();
-        let lowered = convert_type(&mut ctx, array).unwrap();
-        assert_eq!(llvm_type_size_align(&ctx, lowered), Some((40, 2)));
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_partial_byte_integer_carriers() {
-        let mut ctx = make_ctx();
-        let partial_discriminant = mir_uint(&mut ctx, 7);
-        let direct: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "PartialDirect".into(),
-            partial_discriminant,
-            vec![0, 1],
-            vec![EnumVariant::unit("A".into()), EnumVariant::unit("B".into())],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 1,
-                abi_align: 1,
-                layout_kind: EnumLayoutKind::Direct,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 7,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        let error = build_enum_slot_map(&mut ctx, direct)
-            .err()
-            .expect("partial-byte Direct carrier must fail closed");
-        assert!(
-            error.to_string().contains("whole number of bytes"),
-            "{error}"
-        );
-
-        let logical = mir_uint(&mut ctx, 8);
-        let payload = mir_uint(&mut ctx, 8);
-        let niche: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "PartialNiche".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![1]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 1,
-                abi_align: 1,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 7,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        let error = build_enum_slot_map(&mut ctx, niche)
-            .err()
-            .expect("partial-byte Niche carrier must fail closed");
-        assert!(
-            error.to_string().contains("whole number of bytes"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_misaligned_inhabited_payload() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 8);
-        let word = mir_uint(&mut ctx, 32);
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "PackedPayload".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("Empty".into()),
-                EnumVariant::new_with_layout("Data".into(), vec![word], vec![1], vec![4]),
-            ],
-            0,
-            8,
-            4,
-        )
-        .into();
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("misaligned payload must be rejected");
-        assert!(error.to_string().contains("offset 1 is not aligned"));
-    }
-
-    #[test]
-    fn enum_slot_map_uses_i8_storage_for_nonoverlapping_scalar_bool() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 32);
-        let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "DirectBool".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout("A".into(), vec![boolean], vec![4], vec![1]),
-                EnumVariant::unit("B".into()),
-            ],
-            0,
-            8,
-            4,
-        )
-        .into();
-
-        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(map.field_slots, vec![None]);
-        let fields = struct_fields(&ctx, map.llvm_struct_ty);
-        assert_eq!(fields.len(), 3, "tag, canonical bool byte, tail pad");
-        assert_eq!(
-            fields[1]
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .map(IntegerType::width),
-            Some(8),
-            "Rust bool storage must be an i8 byte, never an LLVM i1 slot"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_allows_nonoverlapping_aggregate_padding_without_bool() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 32);
-        let byte = mir_uint(&mut ctx, 8);
-        let word = mir_uint(&mut ctx, 32);
-        let padded: TypeHandle = MirTupleType::get(&mut ctx, vec![byte, word]).into();
-        let lowered_padded = convert_type(&mut ctx, padded).unwrap();
-        assert!(
-            !llvm_type_is_byte_faithful(&ctx, lowered_padded),
-            "the LLVM i8/i32 tuple has harmless implicit padding"
-        );
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "PaddedPayload".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout("Data".into(), vec![padded], vec![4], vec![8]),
-                EnumVariant::unit("Empty".into()),
-            ],
-            0,
-            12,
-            4,
-        )
-        .into();
-
-        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(map.field_slots, vec![Some(1)]);
-        assert_eq!(
-            llvm_type_size_align(&ctx, map.llvm_struct_ty),
-            Some((12, 4))
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_nonoverlapping_nested_bool_storage() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 32);
-        let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
-        let wrapper: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "BoolWrapper".into(),
-            vec!["value".into()],
-            vec![boolean],
-            vec![0],
-            vec![0],
-            1,
-            1,
-        )
-        .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "DirectBoolWrapper".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout("A".into(), vec![wrapper], vec![4], vec![1]),
-                EnumVariant::unit("B".into()),
-            ],
-            0,
-            8,
-            4,
-        )
-        .into();
-
-        // The wrapper claims its byte-faithful twin ({i8}) and stays
-        // slotless: construction canonicalizes the bool byte, extraction
-        // re-loads the original {i1} shape from the canonical byte.
-        let map = build_enum_slot_map(&mut ctx, enum_ty)
-            .expect("nested bool storage canonicalizes through its byte-faithful twin");
-        assert_eq!(map.field_slots, vec![None]);
-        assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((8, 4)));
-        let struct_fields: Vec<_> = map
-            .llvm_struct_ty
-            .deref(&ctx)
-            .downcast_ref::<llvm_types::StructType>()
-            .unwrap()
-            .fields()
-            .collect();
-        assert!(
-            struct_fields
-                .iter()
-                .all(|field| !llvm_type_contains_i1(&ctx, *field)),
-            "enum storage must never contain physical i1"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_bool_hidden_by_union_byte_storage() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 32);
-        let byte = mir_uint(&mut ctx, 8);
-        let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
-        let union: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "BoolOrByte".into(),
-            vec!["flag".into(), "byte".into()],
-            vec![boolean, byte],
-            1,
-            1,
-        )
-        .into();
-        let lowered_union = convert_type(&mut ctx, union).unwrap();
-        assert!(
-            !llvm_type_contains_i1(&ctx, lowered_union),
-            "the union's raw-byte carrier intentionally hides its semantic bool"
-        );
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "DirectUnionBool".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout("A".into(), vec![union], vec![4], vec![1]),
-                EnumVariant::unit("B".into()),
-            ],
-            0,
-            8,
-            4,
-        )
-        .into();
-
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("a bool hidden by union byte storage must still fail closed");
-        assert!(
-            error.to_string().contains("hidden behind a union"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_does_not_descend_through_pointer_to_bool() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 32);
-        let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
-        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, boolean, false).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "PointerToBool".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout("A".into(), vec![pointer], vec![8], vec![8]),
-                EnumVariant::unit("B".into()),
-            ],
-            0,
-            16,
-            8,
-        )
-        .into();
-
-        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert!(map.field_slots[0].is_some());
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_pointer_nonpointer_overlap_in_either_variant_order() {
-        for pointer_first in [false, true] {
-            let mut ctx = make_ctx();
-            let discr = mir_uint(&mut ctx, 32);
-            let u8_ty = mir_uint(&mut ctx, 8);
-            let u64_ty = mir_uint(&mut ctx, 64);
-            let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
-            let (first_name, first_ty, second_name, second_ty) = if pointer_first {
-                ("Ptr", pointer, "Bits", u64_ty)
-            } else {
-                ("Bits", u64_ty, "Ptr", pointer)
-            };
-            let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-                &mut ctx,
-                "PointerOrBits".into(),
-                discr,
-                vec![0, 1],
-                vec![
-                    EnumVariant::new_with_layout(
-                        first_name.into(),
-                        vec![first_ty],
-                        vec![8],
-                        vec![8],
-                    ),
-                    EnumVariant::new_with_layout(
-                        second_name.into(),
-                        vec![second_ty],
-                        vec![8],
-                        vec![8],
-                    ),
-                ],
-                EnumEncoding {
-                    tag_offset: 0,
-                    total_size: 16,
-                    abi_align: 8,
-                    layout_kind: EnumLayoutKind::Direct,
-                    carrier_kind: EnumCarrierKind::Integer,
-                    carrier_width: 32,
-                    variant_inhabited: vec![1, 1],
-                    ..EnumEncoding::default()
-                },
-            )
-            .into();
-            let error = build_enum_slot_map(&mut ctx, enum_ty)
-                .err()
-                .expect("pointer overlap must reject");
-            assert!(
-                error.to_string().contains("pointer provenance"),
-                "pointer_first={pointer_first}: {error}"
-            );
-        }
-    }
-
-    #[test]
-    fn enum_slot_map_canonicalizes_overlapping_bool_wrapper_storage() {
-        let mut ctx = make_ctx();
-        let logical = mir_uint(&mut ctx, 8);
-        let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
-        let wrapper: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "BoolWrapper".into(),
-            vec!["value".into()],
-            vec![boolean],
-            vec![0],
-            vec![0],
-            1,
-            1,
-        )
-        .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "MaybeBoolWrapper".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![wrapper], vec![0], vec![1]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 1,
-                abi_align: 1,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 8,
-                niche_start: 2,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        // Option<Wrapper(bool)>: the wrapper's byte-faithful twin ({i8})
-        // shares the single canonical byte with the i8 niche carrier. The
-        // wrapper stays slotless; construction zero-extends its bool.
-        let map = build_enum_slot_map(&mut ctx, enum_ty)
-            .expect("a bool wrapper shares its canonical byte with the i8 carrier");
-        assert_eq!(map.field_slots, vec![None]);
-        assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((1, 1)));
-        assert!(
-            !llvm_type_contains_i1(&ctx, map.llvm_struct_ty),
-            "enum storage must never contain physical i1"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_canonicalizes_bool_wrapper_overlap_in_either_variant_order() {
-        for wrapper_first in [false, true] {
-            let mut ctx = make_ctx();
-            let tag = mir_uint(&mut ctx, 32);
-            let byte = mir_uint(&mut ctx, 8);
-            let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
-            let wrapper: TypeHandle = MirStructType::get_with_full_layout(
-                &mut ctx,
-                "BoolWrapper".into(),
-                vec!["value".into()],
-                vec![boolean],
-                vec![0],
-                vec![0],
-                1,
-                1,
-            )
-            .into();
-            let (first, second) = if wrapper_first {
-                (wrapper, byte)
-            } else {
-                (byte, wrapper)
-            };
-            let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-                &mut ctx,
-                "BoolWrapperOrByte".into(),
-                tag,
-                vec![0, 1],
-                vec![
-                    EnumVariant::new_with_layout("First".into(), vec![first], vec![4], vec![1]),
-                    EnumVariant::new_with_layout("Second".into(), vec![second], vec![4], vec![1]),
-                ],
-                EnumEncoding {
-                    tag_offset: 0,
-                    total_size: 8,
-                    abi_align: 4,
-                    layout_kind: EnumLayoutKind::Direct,
-                    carrier_kind: EnumCarrierKind::Integer,
-                    carrier_width: 32,
-                    variant_inhabited: vec![1, 1],
-                    ..EnumEncoding::default()
-                },
-            )
-            .into();
-
-            // The wrapper's canonical twin ({i8}) and the plain u8 variant
-            // share one byte-faithful byte, independent of declaration
-            // order; the wrapper stays slotless either way.
-            let map = build_enum_slot_map(&mut ctx, enum_ty)
-                .expect("canonical bool bytes may share storage with a u8 variant");
-            assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((8, 4)));
-            assert!(
-                !llvm_type_contains_i1(&ctx, map.llvm_struct_ty),
-                "wrapper_first={wrapper_first}: enum storage must never contain physical i1"
-            );
-            let wrapper_flat = if wrapper_first { 0 } else { 1 };
-            assert_eq!(map.field_slots[wrapper_flat], None);
-        }
-    }
-
-    #[test]
-    fn enum_slot_map_backs_pointer_beside_integer_niche_carrier() {
-        let mut ctx = make_ctx();
-        let logical = mir_uint(&mut ctx, 8);
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let payload: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PointerThenNiche".into(),
-            vec!["pointer".into(), "niche".into()],
-            vec![pointer, u32_ty],
-            vec![0, 1],
-            vec![0, 8],
-            16,
-            8,
-        )
-        .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "MaybePointerThenNiche".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
-            ],
-            EnumEncoding {
-                tag_offset: 8,
-                total_size: 16,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 32,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        // The pointer at byte 0 never shares bytes with the integer niche
-        // carrier at byte 8, so it is representable: it gets its own `ptr` slot
-        // and the carrier stays an integer slot. `{ptr@0, i32@8, i32 filler}`
-        // -- the trailing 4 bytes are 4-aligned inside an 8-aligned enum, so
-        // they lower to one `i32` rather than `[4 x i8]`.
-        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(map.field_slots, vec![None]);
-        let lowered_pointer = convert_type(&mut ctx, pointer).unwrap();
-        let carrier: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
-        assert_eq!(
-            struct_fields(&ctx, map.llvm_struct_ty),
-            vec![lowered_pointer, carrier, llvm_int(&mut ctx, 32)]
-        );
-        assert_eq!(
-            llvm_type_size_align(&ctx, map.llvm_struct_ty),
-            Some((16, 8))
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_keeps_plain_pointer_niche_in_one_pointer_slot() {
-        let mut ctx = make_ctx();
-        let logical = mir_uint(&mut ctx, 8);
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "MaybePointer".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![pointer], vec![0], vec![8]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 8,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(map.carrier_slot, Some(0));
-        assert_eq!(map.field_slots, vec![Some(0)]);
-        assert!(
-            struct_fields(&ctx, map.llvm_struct_ty)[0]
-                .deref(&ctx)
-                .is::<llvm_types::PointerType>()
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_accepts_pointer_first_and_pointer_second_aggregate_niches() {
-        for pointer_first in [true, false] {
-            let mut ctx = make_ctx();
-            let logical = mir_uint(&mut ctx, 64);
-            let index = mir_uint(&mut ctx, 64);
-            let pointee = mir_uint(&mut ctx, 32);
-            let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
-            let payload_types = if pointer_first {
-                vec![pointer, index]
-            } else {
-                vec![index, pointer]
-            };
-            let payload: TypeHandle = MirTupleType::get(&mut ctx, payload_types).into();
-            let tag_offset = if pointer_first { 0 } else { 8 };
-            let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-                &mut ctx,
-                "MaybeIndexedRef".into(),
-                logical,
-                vec![0, 1],
-                vec![
-                    EnumVariant::unit("None".into()),
-                    EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
-                ],
-                EnumEncoding {
-                    tag_offset,
-                    total_size: 16,
-                    abi_align: 8,
-                    layout_kind: EnumLayoutKind::Niche,
-                    carrier_kind: EnumCarrierKind::Pointer,
-                    carrier_width: 64,
-                    untagged_variant: 1,
-                    variant_inhabited: vec![1, 1],
-                    ..EnumEncoding::default()
-                },
-            )
-            .into();
-
-            let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-            assert_eq!(map.field_slots, vec![None]);
-            assert_eq!(map.carrier_slot, Some(if pointer_first { 0 } else { 1 }));
-            assert_eq!(
-                llvm_type_size_align(&ctx, map.llvm_struct_ty),
-                Some((16, 8))
-            );
-            let lowered_pointer = convert_type(&mut ctx, pointer).unwrap();
-            // The 8 bytes the pointer slot does not claim are 8-aligned inside
-            // an 8-aligned enum, so they lower to one `i64`, not `[8 x i8]`.
-            let filler = llvm_int(&mut ctx, 64);
-            let expected = if pointer_first {
-                vec![lowered_pointer, filler]
-            } else {
-                vec![filler, lowered_pointer]
-            };
-            assert_eq!(struct_fields(&ctx, map.llvm_struct_ty), expected);
-        }
-    }
-
-    #[test]
-    fn enum_slot_map_backs_each_aggregate_pointer_leaf_with_its_own_slot() {
-        let mut ctx = make_ctx();
-        let logical = mir_uint(&mut ctx, 64);
-        let pointee = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
-        let payload: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "TwoRefs".into(),
-            vec!["first".into(), "second".into()],
-            vec![pointer, pointer],
-            vec![0, 1],
-            vec![0, 8],
-            16,
-            8,
-        )
-        .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "MaybeTwoRefs".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
-            ],
-            EnumEncoding {
-                tag_offset: 8,
-                total_size: 16,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        // Both pointer leaves are representable without erasing provenance: the
-        // carrier backs the leaf at byte 8, and the leaf at byte 0 gets its own
-        // fresh `ptr` slot. The payload stays slotless and round-trips through
-        // `{ptr@0, ptr@8}`.
-        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(map.field_slots, vec![None]);
-        let lowered_pointer = convert_type(&mut ctx, pointer).unwrap();
-        assert_eq!(
-            struct_fields(&ctx, map.llvm_struct_ty),
-            vec![lowered_pointer, lowered_pointer]
-        );
-        assert_eq!(
-            llvm_type_size_align(&ctx, map.llvm_struct_ty),
-            Some((16, 8))
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_backs_split_at_mut_slice_pair() {
-        // Models `Option<(&mut [u32], &mut [u32])>`, the `split_at_mut_checked`
-        // return type: two fat slice pointers `{ptr, len}` back to back. The
-        // None niche lives in the first data pointer; both data pointers must
-        // keep their own `ptr` slot so provenance survives the memory
-        // round-trip, with the two `len` fields as raw byte storage.
-        let mut ctx = make_ctx();
-        let logical = mir_uint(&mut ctx, 64);
-        let len = mir_uint(&mut ctx, 64);
-        let pointee = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
-        let payload: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "SlicePair".into(),
-            vec![
-                "a_ptr".into(),
-                "a_len".into(),
-                "b_ptr".into(),
-                "b_len".into(),
-            ],
-            vec![pointer, len, pointer, len],
-            vec![0, 1, 2, 3],
-            vec![0, 8, 16, 24],
-            32,
-            8,
-        )
-        .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "MaybeSlicePair".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![32]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 32,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
-        assert_eq!(map.field_slots, vec![None]);
-        let lowered_pointer = convert_type(&mut ctx, pointer).unwrap();
-        // Each slice's length sits in the 8 bytes after its pointer, 8-aligned
-        // inside an 8-aligned enum, so both lower to one `i64`. This is the
-        // `split_at_mut_checked` shape, and the whole point of the widening:
-        // `{ptr, i64, ptr, i64}` moves two lengths as two values, where
-        // `{ptr, [8 x i8], ptr, [8 x i8]}` moved them as sixteen separate bytes.
-        let filler = llvm_int(&mut ctx, 64);
-        assert_eq!(
-            struct_fields(&ctx, map.llvm_struct_ty),
-            vec![lowered_pointer, filler, lowered_pointer, filler]
-        );
-        assert_eq!(
-            llvm_type_size_align(&ctx, map.llvm_struct_ty),
-            Some((32, 8))
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_three_field_tuple_follows_recorded_offsets() {
-        // rustc lays out `(u32, f32, &T)` with the pointer first in memory:
-        // ptr @ 0, u32 @ 8, f32 @ 12, size 16. With those offsets recorded on
-        // the tuple, the pointer leaf coincides exactly with the niche
-        // carrier at byte 0 and the payload is accepted.
-        let mut ctx = make_ctx();
-        let logical = mir_uint(&mut ctx, 64);
-        let word = mir_uint(&mut ctx, 32);
-        let float: TypeHandle = FP32Type::get(&ctx).into();
-        let pointee = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
-        let payload: TypeHandle = MirTupleType::get_with_layout(
-            &mut ctx,
-            vec![word, float, pointer],
-            vec![2, 0, 1],
-            vec![8, 12, 0],
-            16,
-            8,
-        )
-        .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "MaybeMixedTuple".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 16,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let map = build_enum_slot_map(&mut ctx, enum_ty)
-            .expect("recorded tuple offsets prove the pointer word matches the carrier");
-        assert_eq!(map.carrier_slot, Some(0));
-        assert_eq!(
-            llvm_type_size_align(&ctx, map.llvm_struct_ty),
-            Some((16, 8))
-        );
-
-        // The same tuple with offsets that put the u32 over the pointer
-        // carrier (ptr @ 8 instead) must still fail closed: integer bytes
-        // may not alias pointer storage.
-        let mismatched_payload: TypeHandle = MirTupleType::get_with_layout(
-            &mut ctx,
-            vec![word, float, pointer],
-            vec![0, 1, 2],
-            vec![0, 4, 8],
-            16,
-            8,
-        )
-        .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "MaybeMixedTupleShifted".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout(
-                    "Some".into(),
-                    vec![mismatched_payload],
-                    vec![0],
-                    vec![16],
-                ),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 16,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("a non-pointer word over the pointer carrier must fail closed");
-        assert!(error.to_string().contains("pointer provenance"), "{error}");
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_shifted_nested_pointer_carrier() {
-        let mut ctx = make_ctx();
-        let logical = mir_uint(&mut ctx, 64);
-        let index = mir_uint(&mut ctx, 64);
-        let pointee = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
-        let payload: TypeHandle = MirTupleType::get(&mut ctx, vec![index, pointer]).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "ShiftedPointerCarrier".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 16,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("pointer leaves at different offsets must not be conflated");
-        assert!(error.to_string().contains("pointer provenance"), "{error}");
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_nested_carrier_address_space_mismatch() {
-        let mut ctx = make_ctx();
-        let logical = mir_uint(&mut ctx, 64);
-        let index = mir_uint(&mut ctx, 64);
-        let pointee = mir_uint(&mut ctx, 32);
-        let generic_pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
-        let payload: TypeHandle = MirTupleType::get(&mut ctx, vec![generic_pointer, index]).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "MismatchedPointerSpace".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 16,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                carrier_address_space: llvm_types::address_space::GLOBAL,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("equal byte ranges in different address spaces must not alias");
-        assert!(error.to_string().contains("pointer provenance"), "{error}");
-    }
-
-    #[test]
-    fn enum_slot_map_genericizes_nonoverlapping_shared_pointer_payload() {
-        let mut ctx = make_ctx();
-        let discr = mir_uint(&mut ctx, 32);
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "SharedPointerPayload".into(),
-            discr,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("Unit".into()),
-                EnumVariant::new_with_layout("Ptr".into(), vec![shared], vec![8], vec![8]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 16,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Direct,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 32,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-        let map = build_enum_slot_map(&mut ctx, enum_ty)
-            .expect("a direct shared-pointer payload should use generic physical storage");
-        let field_slot = map.field_slots[0].expect("shared pointer field should own a slot");
-        let stored_ty = map
-            .llvm_struct_ty
-            .deref(&ctx)
-            .downcast_ref::<llvm_types::StructType>()
-            .map(|struct_ty| struct_ty.field_type(field_slot as usize))
-            .expect("field slot must exist");
-        assert_eq!(
-            stored_ty
-                .deref(&ctx)
-                .downcast_ref::<llvm_types::PointerType>()
-                .expect("shared pointer storage must remain a pointer")
-                .address_space(),
-            llvm_types::address_space::GENERIC,
-            "enum storage must use a target-stable generic pointer"
-        );
-        assert_eq!(
-            map.field_llvm_types[0]
-                .deref(&ctx)
-                .downcast_ref::<llvm_types::PointerType>()
-                .expect("semantic field must remain a pointer")
-                .address_space(),
-            llvm_types::address_space::SHARED,
-            "payload operations must retain the semantic shared address space"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_genericizes_nested_shared_pointer_payload() {
-        let mut ctx = make_ctx();
-        let discr = mir_uint(&mut ctx, 32);
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
-        let wrapper: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "SharedPointerWrapper".into(),
-            vec!["pointer".into()],
-            vec![shared],
-            vec![0],
-            vec![0],
-            8,
-            8,
-        )
-        .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "NestedSharedPointerPayload".into(),
-            discr,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("Unit".into()),
-                EnumVariant::new_with_layout("Ptr".into(), vec![wrapper], vec![8], vec![8]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 16,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Direct,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 32,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let map = build_enum_slot_map(&mut ctx, enum_ty)
-            .expect("a struct-nested shared pointer should use generic physical storage");
-        let field_slot = map.field_slots[0].expect("nested payload should own a slot");
-        let stored_ty = map
-            .llvm_struct_ty
-            .deref(&ctx)
-            .downcast_ref::<llvm_types::StructType>()
-            .map(|struct_ty| struct_ty.field_type(field_slot as usize))
-            .expect("field slot must exist");
-        assert!(
-            llvm_type_contains_pointer_in_address_space(
-                &ctx,
-                stored_ty,
-                llvm_types::address_space::GENERIC
-            ),
-            "physical nested payload must contain a generic pointer"
-        );
-        assert!(
-            !llvm_type_contains_pointer_in_address_space(
-                &ctx,
-                stored_ty,
-                llvm_types::address_space::SHARED
-            ),
-            "physical nested payload must not retain the target-dependent AS3 pointer"
-        );
-        assert!(
-            llvm_type_contains_pointer_in_address_space(
-                &ctx,
-                map.field_llvm_types[0],
-                llvm_types::address_space::SHARED
-            ),
-            "semantic payload type must retain shared address-space semantics"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_genericizes_bounded_shared_pointer_array_payload() {
-        let mut ctx = make_ctx();
-        let discr = mir_uint(&mut ctx, 32);
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
-        let pointers: TypeHandle = MirArrayType::get(&mut ctx, shared, 2).into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "SharedPointerArrayPayload".into(),
-            discr,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("Unit".into()),
-                EnumVariant::new_with_layout("Pointers".into(), vec![pointers], vec![8], vec![16]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 24,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Direct,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 32,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let map = build_enum_slot_map(&mut ctx, enum_ty)
-            .expect("a bounded shared-pointer array should use generic physical storage");
-        let field_slot = map.field_slots[0].expect("bounded pointer array should own a slot");
-        let stored_ty = map
-            .llvm_struct_ty
-            .deref(&ctx)
-            .downcast_ref::<llvm_types::StructType>()
-            .map(|struct_ty| struct_ty.field_type(field_slot as usize))
-            .expect("field slot must exist");
-        assert!(
-            llvm_type_contains_pointer_in_address_space(
-                &ctx,
-                stored_ty,
-                llvm_types::address_space::GENERIC
-            ),
-            "physical array payload must contain generic pointers"
-        );
-        assert!(
-            !llvm_type_contains_pointer_in_address_space(
-                &ctx,
-                stored_ty,
-                llvm_types::address_space::SHARED
-            ),
-            "physical array payload must not retain target-dependent AS3 pointers"
-        );
-        assert!(
-            llvm_type_contains_pointer_in_address_space(
-                &ctx,
-                map.field_llvm_types[0],
-                llvm_types::address_space::SHARED
-            ),
-            "semantic array payload must retain shared address-space semantics"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_oversized_shared_pointer_array_payload() {
-        let mut ctx = make_ctx();
-        let discr = mir_uint(&mut ctx, 32);
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
-        let count = MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES + 1;
-        let pointers: TypeHandle = MirArrayType::get(&mut ctx, shared, count).into();
-        let payload_size = count * 8;
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "OversizedSharedPointerArrayPayload".into(),
-            discr,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("Unit".into()),
-                EnumVariant::new_with_layout(
-                    "Pointers".into(),
-                    vec![pointers],
-                    vec![8],
-                    vec![payload_size],
-                ),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 8 + payload_size,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Direct,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 32,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("an oversized shared-pointer array must remain fail-closed");
-        assert!(
-            error
-                .to_string()
-                .contains("arrays containing shared-memory pointers are not supported"),
-            "{error}"
-        );
-        assert!(
-            error.to_string().contains(&format!(
-                "supported bound is {MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES}"
-            )),
-            "{error}"
-        );
-    }
-
-    /// A struct payload holding two shared-pointer arrays whose leaves exceed
-    /// the bound only in total. The slot map is target-mode agnostic (it is
-    /// built once, before the exporter picks the legacy 64-bit or modern
-    /// p3:32 data layout), so this one gate covers both output modes.
-    fn struct_of_shared_pointer_arrays_over_total_bound(ctx: &mut Context) -> TypeHandle {
-        let u32_ty = mir_uint(ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(ctx, u32_ty, false).into();
-        let first: TypeHandle = MirArrayType::get(ctx, shared, 9).into();
-        let second: TypeHandle = MirArrayType::get(ctx, shared, 8).into();
-        MirStructType::get_with_full_layout(
-            ctx,
-            "SharedPointerArrayPair".into(),
-            vec!["first".into(), "second".into()],
-            vec![first, second],
-            vec![],
-            vec![0, 72],
-            136,
-            8,
-        )
-        .into()
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_struct_of_shared_pointer_arrays_over_total_bound() {
-        // Each array alone (9 and 8 leaves) is within the bound; their total
-        // of 17 is not. The payload-root gate must reject the direct layout
-        // with the same bound diagnostic as a single oversized array.
-        let mut ctx = make_ctx();
-        let discr = mir_uint(&mut ctx, 32);
-        let payload = struct_of_shared_pointer_arrays_over_total_bound(&mut ctx);
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "StructOfSharedPointerArraysPayload".into(),
-            discr,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("Unit".into()),
-                EnumVariant::new_with_layout("Pointers".into(), vec![payload], vec![8], vec![136]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 144,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Direct,
-                carrier_kind: EnumCarrierKind::Integer,
-                carrier_width: 32,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("two in-bound arrays exceeding the bound in total must fail closed");
-        assert!(
-            error
-                .to_string()
-                .contains("arrays containing shared-memory pointers are not supported"),
-            "{error}"
-        );
-        assert!(
-            error.to_string().contains(&format!(
-                "rewrite requires 17 pointer conversions, supported bound is {MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES}"
-            )),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_struct_of_shared_pointer_arrays_in_niche_layout() {
-        // The same over-bound payload in a niche layout must report the same
-        // bound diagnostic as the direct layout, not a pointer-provenance
-        // error from the overlap walk: the payload-root gate runs first in
-        // both layouts.
-        let mut ctx = make_ctx();
-        let logical = mir_uint(&mut ctx, 64);
-        let payload = struct_of_shared_pointer_arrays_over_total_bound(&mut ctx);
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "NicheStructOfSharedPointerArrays".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![136]),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: 136,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("the payload-root bound must also gate niche layouts");
-        assert!(
-            error.to_string().contains(&format!(
-                "rewrite requires 17 pointer conversions, supported bound is {MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES}"
-            )),
-            "{error}"
-        );
-        assert!(
-            !error.to_string().contains("pointer provenance"),
-            "the bound diagnostic must not be masked by the provenance error: {error}"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_reports_bound_for_oversized_pointer_array_over_niche_carrier() {
-        // Generic pointers pass the shared-pointer storage gate untouched, so
-        // an oversized generic-pointer array reaches the overlap walk. Its
-        // exhausted expansion budget must surface the bound diagnostic, not
-        // the unrelated provenance error.
-        let mut ctx = make_ctx();
-        let logical = mir_uint(&mut ctx, 64);
-        let pointee = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
-        let count = MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES + 1;
-        let pointers: TypeHandle = MirArrayType::get(&mut ctx, pointer, count).into();
-        let payload_size = count * 8;
-        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
-            &mut ctx,
-            "NicheOversizedGenericPointerArray".into(),
-            logical,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new_with_layout(
-                    "Some".into(),
-                    vec![pointers],
-                    vec![0],
-                    vec![payload_size],
-                ),
-            ],
-            EnumEncoding {
-                tag_offset: 0,
-                total_size: payload_size,
-                abi_align: 8,
-                layout_kind: EnumLayoutKind::Niche,
-                carrier_kind: EnumCarrierKind::Pointer,
-                carrier_width: 64,
-                untagged_variant: 1,
-                variant_inhabited: vec![1, 1],
-                ..EnumEncoding::default()
-            },
-        )
-        .into();
-
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("an oversized pointer-array expansion over a niche carrier must fail closed");
-        assert!(
-            error.to_string().contains(&format!(
-                "rewrite requires {count} pointer conversions, supported bound is {MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES}"
-            )),
-            "{error}"
-        );
-        assert!(
-            !error.to_string().contains("pointer provenance"),
-            "the bound diagnostic must not be masked by the provenance error: {error}"
-        );
-    }
-
-    #[test]
-    fn enum_slot_map_rejects_shared_pointer_vector_payload() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 32);
-        let shared_pointer: TypeHandle =
-            llvm_types::PointerType::get(&ctx, llvm_types::address_space::SHARED).into();
-        let shared_vector: TypeHandle =
-            llvm_types::VectorType::get(&ctx, shared_pointer, 2, llvm_types::VectorTypeKind::Fixed)
-                .into();
-        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "SharedPointerVector".into(),
-            tag,
-            vec![0, 1],
-            vec![
-                EnumVariant::new_with_layout(
-                    "Data".into(),
-                    vec![shared_vector],
-                    vec![16],
-                    vec![16],
-                ),
-                EnumVariant::unit("Empty".into()),
-            ],
-            0,
-            32,
-            16,
-        )
-        .into();
-
-        let error = build_enum_slot_map(&mut ctx, enum_ty)
-            .err()
-            .expect("a vector of shared pointers must fail closed");
-        assert!(
-            error.to_string().contains("shared-memory pointer"),
-            "{error}"
-        );
-    }
-
-    #[test]
-    fn union_storage_prefers_pointer_carrier() {
-        let mut ctx = make_ctx();
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let u64_ty = mir_uint(&mut ctx, 64);
-        let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let union_ty = MirUnionType::get(
-            &mut ctx,
-            "PointerBits".into(),
-            vec!["ptr".into(), "bits".into()],
-            vec![ptr_ty, u64_ty],
-            8,
-            8,
-        );
-        let union_data = union_ty.deref(&ctx).clone();
-        let storage = build_union_storage_type(&mut ctx, &union_data).unwrap();
-        let fields = struct_fields(&ctx, storage);
-        assert!(fields[1].deref(&ctx).is::<llvm_types::PointerType>());
-        assert_eq!(llvm_type_size_align(&ctx, storage), Some((8, 8)));
-    }
-
-    #[test]
-    fn union_storage_rejects_incompatible_pointer_address_spaces() {
-        let mut ctx = make_ctx();
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let generic: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
-        let union_ty = MirUnionType::get(
-            &mut ctx,
-            "MixedPointers".into(),
-            vec!["generic".into(), "shared".into()],
-            vec![generic, shared],
-            8,
-            8,
-        );
-        let union_data = union_ty.deref(&ctx).clone();
-        let err = build_union_storage_type(&mut ctx, &union_data).unwrap_err();
-        assert!(err.to_string().contains("different LLVM representations"));
-    }
-
-    #[test]
-    fn union_storage_rejects_non_byte_faithful_pointer_carrier() {
-        let mut ctx = make_ctx();
-        let u8_ty = mir_uint(&mut ctx, 8);
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let bool_ty = mir_uint(&mut ctx, 1);
-        let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let ptr_bool: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PtrBool".into(),
-            vec!["ptr".into(), "flag".into()],
-            vec![ptr_ty, bool_ty],
-            vec![0, 1],
-            vec![0, 8],
-            16,
-            8,
-        )
-        .into();
-        let bytes_ty: TypeHandle = MirArrayType::get(&mut ctx, u8_ty, 16).into();
-        let union_ty = MirUnionType::get(
-            &mut ctx,
-            "PointerBoolBytes".into(),
-            vec!["view".into(), "bytes".into()],
-            vec![ptr_bool, bytes_ty],
-            16,
-            8,
-        );
-        let union_data = union_ty.deref(&ctx).clone();
-        let err = build_union_storage_type(&mut ctx, &union_data).unwrap_err();
-        assert!(err.to_string().contains("no byte-faithful pointer carrier"));
-    }
-
-    #[test]
-    fn union_storage_preserves_over_aligned_size_and_stride() {
-        let mut ctx = make_ctx();
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let union_ty = MirUnionType::get(
-            &mut ctx,
-            "OverAligned".into(),
-            vec!["word".into()],
-            vec![u32_ty],
-            32,
-            32,
-        );
-        let union_data = union_ty.deref(&ctx).clone();
-        let storage = build_union_storage_type(&mut ctx, &union_data).unwrap();
-        assert_eq!(llvm_type_size_align(&ctx, storage), Some((32, 16)));
-
-        let union_handle: TypeHandle = union_ty.into();
-        let array: TypeHandle = MirArrayType::get(&mut ctx, union_handle, 3).into();
-        let llvm_array = convert_type(&mut ctx, array).unwrap();
-        assert_eq!(llvm_type_size_align(&ctx, llvm_array), Some((96, 16)));
-    }
-
-    #[test]
-    fn slot_map_reorder_only() {
-        let mut ctx = make_ctx();
-        // struct { a: u8, b: u64 }, memory order [b, a], no rustc offsets.
-        let a = mir_uint(&mut ctx, 8);
-        let b = mir_uint(&mut ctx, 64);
-        let layout = StructLayoutInfo {
-            field_types: vec![a, b],
-            mem_to_decl: vec![1, 0],
-            field_offsets: vec![],
-            total_size: 0,
-        };
-        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
-
-        assert_eq!(map.decl_to_llvm, vec![Some(1), Some(0)]);
-        let i8s = llvm_int(&mut ctx, 8);
-        let i64s = llvm_int(&mut ctx, 64);
-        assert_eq!(struct_fields(&ctx, map.llvm_struct_ty), vec![i64s, i8s]);
-    }
-
-    #[test]
-    fn slot_map_padding_only() {
-        let mut ctx = make_ctx();
-        // struct { a: u8 @ 0, b: u64 @ 8 }, declaration order == memory
-        // order, size 16: lowers to { i8, [7 x i8], i64 }. The pad consumes
-        // slot 1, so b lands at slot 2 (the issue #128 sites used 1).
-        let a = mir_uint(&mut ctx, 8);
-        let b = mir_uint(&mut ctx, 64);
-        let layout = StructLayoutInfo {
-            field_types: vec![a, b],
-            mem_to_decl: vec![0, 1],
-            field_offsets: vec![0, 8],
-            total_size: 16,
-        };
-        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
-
-        assert_eq!(map.decl_to_llvm, vec![Some(0), Some(2)]);
-        let i8s = llvm_int(&mut ctx, 8);
-        let i64s = llvm_int(&mut ctx, 64);
-        let pad7 = pad(&mut ctx, 7);
-        assert_eq!(
-            struct_fields(&ctx, map.llvm_struct_ty),
-            vec![i8s, pad7, i64s]
-        );
-    }
-
-    #[test]
-    fn slot_map_uses_packed_layout_when_natural_offsets_diverge() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 8);
-        let value = mir_uint(&mut ctx, 32);
-        let layout = StructLayoutInfo {
-            field_types: vec![tag, value],
-            mem_to_decl: vec![0, 1],
-            field_offsets: vec![0, 1],
-            total_size: 5,
-        };
-
-        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
-
-        assert!(map.layout_diverges);
-        assert_eq!(map.decl_to_llvm, vec![Some(0), Some(1)]);
-        let llvm_struct_ty_ref = map.llvm_struct_ty.deref(&ctx);
-        let struct_ty = llvm_struct_ty_ref
-            .downcast_ref::<llvm_types::StructType>()
-            .expect("slot map must produce an LLVM struct");
-        assert_eq!(struct_ty.layout(), llvm_types::StructLayout::Packed);
-        assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((5, 1)));
-    }
-
-    #[test]
-    fn slot_map_packed_two_keeps_explicit_padding_slot() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 8);
-        let value = mir_uint(&mut ctx, 32);
-        let layout = StructLayoutInfo {
-            field_types: vec![tag, value],
-            mem_to_decl: vec![0, 1],
-            field_offsets: vec![0, 2],
-            total_size: 6,
-        };
-
-        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
-
-        assert!(map.layout_diverges);
-        assert_eq!(map.decl_to_llvm, vec![Some(0), Some(2)]);
-        let i8s = llvm_int(&mut ctx, 8);
-        let i32s = llvm_int(&mut ctx, 32);
-        let pad1 = pad(&mut ctx, 1);
-        assert_eq!(
-            struct_fields(&ctx, map.llvm_struct_ty),
-            vec![i8s, pad1, i32s]
-        );
-        let llvm_struct_ty_ref = map.llvm_struct_ty.deref(&ctx);
-        let struct_ty = llvm_struct_ty_ref
-            .downcast_ref::<llvm_types::StructType>()
-            .expect("slot map must produce an LLVM struct");
-        assert_eq!(struct_ty.layout(), llvm_types::StructLayout::Packed);
-        assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((6, 1)));
-    }
-
-    #[test]
-    fn slot_map_reorder_plus_padding() {
-        let mut ctx = make_ctx();
-        // struct { a: u8 @ 8, b: u64 @ 0 }, memory order [b, a], size 16:
-        // lowers to { i64, i8, [7 x i8] } with a trailing pad.
-        let a = mir_uint(&mut ctx, 8);
-        let b = mir_uint(&mut ctx, 64);
-        let layout = StructLayoutInfo {
-            field_types: vec![a, b],
-            mem_to_decl: vec![1, 0],
-            field_offsets: vec![8, 0],
-            total_size: 16,
-        };
-        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
-
-        assert_eq!(map.decl_to_llvm, vec![Some(1), Some(0)]);
-        let i8s = llvm_int(&mut ctx, 8);
-        let i64s = llvm_int(&mut ctx, 64);
-        let pad7 = pad(&mut ctx, 7);
-        assert_eq!(
-            struct_fields(&ctx, map.llvm_struct_ty),
-            vec![i64s, i8s, pad7]
-        );
-    }
-
-    #[test]
-    fn slot_map_zst_interleaving() {
-        let mut ctx = make_ctx();
-        // struct { a: u32 @ 0, z: PhantomData @ 4, b: u32 @ 4 }, size 8.
-        // The ZST is stripped (no slot, no pad split): { i32, i32 }.
-        let a = mir_uint(&mut ctx, 32);
-        let z = mir_zst(&mut ctx);
-        let b = mir_uint(&mut ctx, 32);
-        let layout = StructLayoutInfo {
-            field_types: vec![a, z, b],
-            mem_to_decl: vec![0, 1, 2],
-            field_offsets: vec![0, 4, 4],
-            total_size: 8,
-        };
-        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
-
-        assert_eq!(map.decl_to_llvm, vec![Some(0), None, Some(1)]);
-        let i32s = llvm_int(&mut ctx, 32);
-        assert_eq!(struct_fields(&ctx, map.llvm_struct_ty), vec![i32s, i32s]);
-    }
-
-    #[test]
-    fn slot_map_issue128_arena_shape() {
-        let mut ctx = make_ctx();
-        // The exact shape from issue #128 (examples/struct_field_layout):
-        //
-        //   enum Layout { Aos, Soa, AoSoA(u32) }          // -> { i8, i32 }
-        //   struct Arena { layout: Layout, cap: u32, stride: u32, big: u64 }
-        //
-        // rustc layout: layout @ 0 (8 bytes), big @ 8, cap @ 16,
-        // stride @ 20, size 24. The enum now carries its own explicit
-        // internal padding, so the OUTER struct needs no extra padding slot:
-        //
-        //   { { i8, [3 x i8], i32 }, i64, i32, i32 }
-        //     layout=0                  big=1 cap=2 stride=3
-        let discr = mir_uint(&mut ctx, 8);
-        let payload = mir_uint(&mut ctx, 32);
-        let layout_enum: TypeHandle = MirEnumType::get_with_layout(
-            &mut ctx,
-            "Layout".into(),
-            discr,
-            vec![0, 1, 2],
-            vec![
-                EnumVariant::unit("Aos".into()),
-                EnumVariant::unit("Soa".into()),
-                EnumVariant::new_with_layout("AoSoA".into(), vec![payload], vec![4], vec![4]),
-            ],
-            0,
-            8,
-            4,
-        )
-        .into();
-        let cap = mir_uint(&mut ctx, 32);
-        let stride = mir_uint(&mut ctx, 32);
-        let big = mir_uint(&mut ctx, 64);
-
-        let layout = StructLayoutInfo {
-            field_types: vec![layout_enum, cap, stride, big],
-            mem_to_decl: vec![0, 3, 1, 2],
-            field_offsets: vec![0, 16, 20, 8],
-            total_size: 24,
-        };
-        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
-
-        assert_eq!(
-            map.decl_to_llvm,
-            vec![Some(0), Some(2), Some(3), Some(1)],
-            "the enum's internal pad must not create an outer struct slot"
-        );
-
-        let i8s = llvm_int(&mut ctx, 8);
-        let i32s = llvm_int(&mut ctx, 32);
-        let i64s = llvm_int(&mut ctx, 64);
-        let enum_pad3 = pad(&mut ctx, 3);
-        let enum_llvm: TypeHandle = llvm_types::StructType::get_unnamed(
-            &ctx,
-            (
-                vec![i8s, enum_pad3, i32s],
-                llvm_types::StructLayout::Unpacked,
-            ),
-        )
-        .into();
-        assert_eq!(
-            struct_fields(&ctx, map.llvm_struct_ty),
-            vec![enum_llvm, i64s, i32s, i32s]
-        );
-    }
-
-    #[test]
-    fn slot_map_nested_struct_uses_stored_size() {
-        let mut ctx = make_ctx();
-        // Inner struct whose stored rustc size (16) exceeds the sum of its
-        // converted LLVM field sizes (i8 + i64 = 9, no offsets stored).
-        // The outer walk must advance by the stored 16, reaching the next
-        // field's offset exactly: NO interior pad before it.
-        let x = mir_uint(&mut ctx, 8);
-        let y = mir_uint(&mut ctx, 64);
-        let inner: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Inner".into(),
-            vec!["x".into(), "y".into()],
-            vec![x, y],
-            vec![],
-            vec![],
-            16,
-            0,
-        )
-        .into();
-        let c = mir_uint(&mut ctx, 8);
-
-        let layout = StructLayoutInfo {
-            field_types: vec![inner, c],
-            mem_to_decl: vec![0, 1],
-            field_offsets: vec![0, 16],
-            total_size: 24,
-        };
-        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
-
-        // inner = slot 0, c = slot 1 (adjacent), trailing [7 x i8] pad.
-        assert_eq!(map.decl_to_llvm, vec![Some(0), Some(1)]);
-        let fields = struct_fields(&ctx, map.llvm_struct_ty);
-        assert_eq!(fields.len(), 3, "exactly one (trailing) pad slot");
-        let pad7 = pad(&mut ctx, 7);
-        assert_eq!(fields[2], pad7);
-    }
-
-    #[test]
-    fn packed_shared_pointer_predicate_ignores_unpacked_direct_pointer() {
-        let ctx = make_ctx();
-        let shared: TypeHandle =
-            llvm_types::PointerType::get(&ctx, llvm_types::address_space::SHARED).into();
-        let unpacked: TypeHandle = llvm_types::StructType::get_unnamed(
-            &ctx,
-            (vec![shared], llvm_types::StructLayout::Unpacked),
-        )
-        .into();
-        assert!(
-            !llvm_packed_struct_contains_pointer_in_address_space(
-                &ctx,
-                unpacked,
-                llvm_types::address_space::SHARED,
-            ),
-            "a direct AS3 pointer in an unpacked aggregate is not a packed physical-image hazard"
-        );
-
-        let packed: TypeHandle = llvm_types::StructType::get_unnamed(
-            &ctx,
-            (vec![shared], llvm_types::StructLayout::Packed),
-        )
-        .into();
-        assert!(
-            llvm_packed_struct_contains_pointer_in_address_space(
-                &ctx,
-                packed,
-                llvm_types::address_space::SHARED,
-            ),
-            "an AS3 pointer under a packed struct must be rejected by by-value paths"
-        );
-    }
-
-    #[test]
-    fn packed_shared_internal_abi_genericizes_one_direct_shared_pointer() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 8);
-        let pointee = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let packed: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedShared".into(),
-            vec!["tag".into(), "ptr".into()],
-            vec![tag, shared],
-            vec![0, 1],
-            vec![0, 1],
-            9,
-            1,
-        )
-        .into();
-
-        let abi = packed_shared_internal_abi_info(&mut ctx, packed)
-            .expect("ABI classification must succeed")
-            .expect("one direct packed AS3 pointer must use the internal carrier");
-        assert_eq!(llvm_type_size_align(&ctx, abi.semantic_ty), Some((9, 1)));
-        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((9, 1)));
-        assert!(llvm_packed_struct_contains_pointer_in_address_space(
-            &ctx,
-            abi.semantic_ty,
-            llvm_types::address_space::SHARED,
-        ));
-        assert!(!llvm_type_contains_pointer_in_address_space(
-            &ctx,
-            abi.storage_ty,
-            llvm_types::address_space::SHARED,
-        ));
-        assert!(llvm_type_contains_pointer_in_address_space(
-            &ctx,
-            abi.storage_ty,
-            llvm_types::address_space::GENERIC,
-        ));
-    }
-
-    #[test]
-    fn packed_shared_internal_abi_genericizes_multiple_direct_shared_pointers() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 8);
-        let pointee = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let packed: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedSharedPair".into(),
-            vec!["tag".into(), "left".into(), "right".into()],
-            vec![tag, shared, shared],
-            vec![0, 1, 2],
-            vec![0, 1, 9],
-            17,
-            1,
-        )
-        .into();
-
-        let abi = packed_shared_internal_abi_info(&mut ctx, packed)
-            .expect("ABI classification must succeed")
-            .expect("multiple direct AS3 leaves must use the recursive internal carrier");
-        assert_eq!(llvm_type_size_align(&ctx, abi.semantic_ty), Some((17, 1)));
-        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((17, 1)));
-        assert!(llvm_packed_struct_contains_pointer_in_address_space(
-            &ctx,
-            abi.semantic_ty,
-            llvm_types::address_space::SHARED,
-        ));
-        assert!(!llvm_type_contains_pointer_in_address_space(
-            &ctx,
-            abi.storage_ty,
-            llvm_types::address_space::SHARED,
-        ));
-
-        let fields = struct_fields(&ctx, abi.storage_ty);
-        assert_eq!(fields.len(), 3);
-        for field in &fields[1..] {
-            let field_ref = field.deref(&ctx);
-            let pointer = field_ref
-                .downcast_ref::<llvm_types::PointerType>()
-                .expect("both pointer leaves must remain pointer-typed");
-            assert_eq!(pointer.address_space(), llvm_types::address_space::GENERIC);
-        }
-    }
-
-    #[test]
-    fn packed_shared_internal_abi_genericizes_nested_struct_shared_pointers() {
-        let mut ctx = make_ctx();
-        let pointee = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let inner: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "InnerSharedPair".into(),
-            vec!["left".into(), "right".into()],
-            vec![shared, shared],
-            vec![0, 1],
-            vec![0, 8],
-            16,
-            8,
-        )
-        .into();
-        let tag = mir_uint(&mut ctx, 8);
-        let outer: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedNestedShared".into(),
-            vec!["tag".into(), "inner".into()],
-            vec![tag, inner],
-            vec![0, 1],
-            vec![0, 1],
-            17,
-            1,
-        )
-        .into();
-
-        let abi = packed_shared_internal_abi_info(&mut ctx, outer)
-            .expect("classification must not error")
-            .expect("nested AS3 leaves must use the recursive internal carrier");
-        assert_eq!(llvm_type_size_align(&ctx, abi.semantic_ty), Some((17, 1)));
-        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((17, 1)));
-        assert!(!llvm_type_contains_pointer_in_address_space(
-            &ctx,
-            abi.storage_ty,
-            llvm_types::address_space::SHARED,
-        ));
-
-        let outer_fields = struct_fields(&ctx, abi.storage_ty);
-        let inner_fields = struct_fields(&ctx, outer_fields[1]);
-        assert_eq!(inner_fields.len(), 2);
-        for field in inner_fields {
-            let field_ref = field.deref(&ctx);
-            let pointer = field_ref
-                .downcast_ref::<llvm_types::PointerType>()
-                .expect("nested shared leaves must remain pointer-typed");
-            assert_eq!(pointer.address_space(), llvm_types::address_space::GENERIC);
-        }
-    }
-
-    #[test]
-    fn packed_shared_internal_abi_genericizes_nested_tuple_shared_pointer() {
-        let mut ctx = make_ctx();
-        let pointee = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let word = mir_uint(&mut ctx, 32);
-        let inner: TypeHandle = MirTupleType::get_with_layout(
-            &mut ctx,
-            vec![shared, word],
-            vec![0, 1],
-            vec![0, 8],
-            16,
-            8,
-        )
-        .into();
-        let tag = mir_uint(&mut ctx, 8);
-        let outer: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedNestedTupleShared".into(),
-            vec!["tag".into(), "inner".into()],
-            vec![tag, inner],
-            vec![0, 1],
-            vec![0, 1],
-            17,
-            1,
-        )
-        .into();
-
-        let abi = packed_shared_internal_abi_info(&mut ctx, outer)
-            .expect("classification must not error")
-            .expect("an AS3 leaf nested in a tuple must use the recursive carrier");
-        let outer_fields = struct_fields(&ctx, abi.storage_ty);
-        let inner_fields = struct_fields(&ctx, outer_fields[1]);
-        let inner_field_ref = inner_fields[0].deref(&ctx);
-        let pointer = inner_field_ref
-            .downcast_ref::<llvm_types::PointerType>()
-            .expect("nested tuple leaf must remain pointer-typed");
-        assert_eq!(pointer.address_space(), llvm_types::address_space::GENERIC);
-        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((17, 1)));
-    }
-
-    #[test]
-    fn packed_shared_internal_abi_skips_zero_sized_fields() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 8);
-        let byte = mir_uint(&mut ctx, 8);
-        let marker: TypeHandle = MirArrayType::get(&mut ctx, byte, 0).into();
-        let pointee = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let packed: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedSharedZstMarker".into(),
-            vec!["tag".into(), "marker".into(), "ptr".into()],
-            vec![tag, marker, shared],
-            vec![0, 1, 2],
-            vec![0, 1, 1],
-            9,
-            1,
-        )
-        .into();
-
-        let abi = packed_shared_internal_abi_info(&mut ctx, packed)
-            .expect("ABI classification must succeed")
-            .expect("a zero-sized field must not knock the struct out of the ABI lane");
-        assert_eq!(llvm_type_size_align(&ctx, abi.semantic_ty), Some((9, 1)));
-        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((9, 1)));
-        assert!(!llvm_type_contains_pointer_in_address_space(
-            &ctx,
-            abi.storage_ty,
-            llvm_types::address_space::SHARED,
-        ));
-    }
-
-    #[test]
-    fn packed_shared_internal_abi_genericizes_bounded_shared_pointer_array() {
-        let mut ctx = make_ctx();
-        let pointee = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let shared_array: TypeHandle = MirArrayType::get(&mut ctx, shared, 2).into();
-        let tag = mir_uint(&mut ctx, 8);
-        let outer: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedSharedArray".into(),
-            vec!["tag".into(), "ptrs".into()],
-            vec![tag, shared_array],
-            vec![0, 1],
-            vec![0, 1],
-            17,
-            1,
-        )
-        .into();
-
-        let abi = packed_shared_internal_abi_info(&mut ctx, outer)
-            .expect("classification must not error")
-            .expect("a bounded AS3 array must use the target-stable internal carrier");
-        assert_eq!(llvm_type_size_align(&ctx, abi.semantic_ty), Some((17, 1)));
-        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((17, 1)));
-        assert!(!llvm_type_contains_pointer_in_address_space(
-            &ctx,
-            abi.storage_ty,
-            llvm_types::address_space::SHARED,
-        ));
-
-        let outer_fields = struct_fields(&ctx, abi.storage_ty);
-        let array_ref = outer_fields[1].deref(&ctx);
-        let array = array_ref
-            .downcast_ref::<llvm_types::ArrayType>()
-            .expect("bounded array field must remain an LLVM array");
-        assert_eq!(array.size(), 2);
-        let element = array.elem_type();
-        let element_ref = element.deref(&ctx);
-        let pointer = element_ref
-            .downcast_ref::<llvm_types::PointerType>()
-            .expect("array elements must remain pointer-typed");
-        assert_eq!(pointer.address_space(), llvm_types::address_space::GENERIC);
-    }
-
-    #[test]
-    fn packed_shared_internal_abi_accepts_array_rewrite_at_exact_bound() {
-        let mut ctx = make_ctx();
-        let pointee = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let count = MAX_PACKED_SHARED_INTERNAL_ABI_ARRAY_REWRITE_LEAVES;
-        let shared_array: TypeHandle = MirArrayType::get(&mut ctx, shared, count).into();
-        let tag = mir_uint(&mut ctx, 8);
-        let outer: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedSharedArrayAtBound".into(),
-            vec!["tag".into(), "ptrs".into()],
-            vec![tag, shared_array],
-            vec![0, 1],
-            vec![0, 1],
-            1 + 8 * count,
-            1,
-        )
-        .into();
-
-        assert!(
-            packed_shared_internal_abi_info(&mut ctx, outer)
-                .expect("classification must not error")
-                .is_some(),
-            "the exact bounded-array rewrite limit must remain supported"
-        );
-    }
-
-    #[test]
-    fn packed_shared_internal_abi_rejects_array_rewrite_above_bound() {
-        let mut ctx = make_ctx();
-        let pointee = mir_uint(&mut ctx, 32);
-        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
-        let count = MAX_PACKED_SHARED_INTERNAL_ABI_ARRAY_REWRITE_LEAVES + 1;
-        let shared_array: TypeHandle = MirArrayType::get(&mut ctx, shared, count).into();
-        let tag = mir_uint(&mut ctx, 8);
-        let outer: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedSharedArrayAboveBound".into(),
-            vec!["tag".into(), "ptrs".into()],
-            vec![tag, shared_array],
-            vec![0, 1],
-            vec![0, 1],
-            1 + 8 * count,
-            1,
-        )
-        .into();
-
-        assert!(
-            packed_shared_internal_abi_info(&mut ctx, outer)
-                .expect("classification must not error")
-                .is_none(),
-            "array-expanded AS3 leaves above the explicit budget must fail closed"
-        );
-    }
-
-    #[test]
-    fn packed_shared_internal_abi_rejects_shared_pointer_vector() {
-        let mut ctx = make_ctx();
-        let tag = mir_uint(&mut ctx, 8);
-        let shared_pointer: TypeHandle =
-            llvm_types::PointerType::get(&ctx, llvm_types::address_space::SHARED).into();
-        let shared_vector: TypeHandle =
-            llvm_types::VectorType::get(&ctx, shared_pointer, 2, llvm_types::VectorTypeKind::Fixed)
-                .into();
-        let outer: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedSharedVector".into(),
-            vec!["tag".into(), "ptrs".into()],
-            vec![tag, shared_vector],
-            vec![0, 1],
-            vec![0, 1],
-            17,
-            1,
-        )
-        .into();
-
-        assert!(
-            packed_shared_internal_abi_info(&mut ctx, outer)
-                .expect("classification must not error")
-                .is_none(),
-            "shared-pointer vectors must remain outside the packed-AS3 internal ABI lane"
-        );
-    }
-
-    #[test]
-    fn slot_map_rejects_malformed_memory_order() {
-        let mut ctx = make_ctx();
-        let a = mir_uint(&mut ctx, 8);
-        let b = mir_uint(&mut ctx, 64);
-
-        // Not a permutation: decl index 0 appears twice.
-        let dup = StructLayoutInfo {
-            field_types: vec![a, b],
-            mem_to_decl: vec![0, 0],
-            field_offsets: vec![],
-            total_size: 0,
-        };
-        assert!(build_struct_slot_map(&mut ctx, &dup).is_err());
-
-        // Wrong length.
-        let short = StructLayoutInfo {
-            field_types: vec![a, b],
-            mem_to_decl: vec![0],
-            field_offsets: vec![],
-            total_size: 0,
-        };
-        assert!(build_struct_slot_map(&mut ctx, &short).is_err());
-
-        // Offsets vector length mismatch (with explicit layout engaged).
-        let bad_offsets = StructLayoutInfo {
-            field_types: vec![a, b],
-            mem_to_decl: vec![0, 1],
-            field_offsets: vec![0],
-            total_size: 16,
-        };
-        assert!(build_struct_slot_map(&mut ctx, &bad_offsets).is_err());
-    }
-
-    #[test]
-    fn initialized_global_layout_accepts_explicit_overalignment() {
-        let mut ctx = make_ctx();
-        let zst = mir_zst(&mut ctx);
-        validate_initialized_global_layout(&mut ctx, zst, 0, 1).unwrap();
-
-        let byte = mir_uint(&mut ctx, 8);
-        let over_aligned: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "OverAligned".into(),
-            vec!["byte".into()],
-            vec![byte],
-            vec![0],
-            vec![0],
-            16,
-            16,
-        )
-        .into();
-
-        validate_initialized_global_layout(&mut ctx, over_aligned, 16, 16).unwrap();
-    }
-
-    #[test]
-    fn initialized_global_layout_rejects_packed_and_nested_packed_structs() {
-        let mut ctx = make_ctx();
-        let byte = mir_uint(&mut ctx, 8);
-        let word = mir_uint(&mut ctx, 32);
-        let packed: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Packed".into(),
-            vec!["tag".into(), "word".into()],
-            vec![byte, word],
-            vec![0, 1],
-            vec![0, 1],
-            5,
-            1,
-        )
-        .into();
-
-        let empty_packed: TypeHandle = MirArrayType::get(&mut ctx, packed, 0).into();
-        validate_initialized_global_layout(&mut ctx, empty_packed, 0, 1)
-            .expect("[Packed; 0] has no element bytes whose field layout can diverge");
-
-        let err = validate_initialized_global_layout(&mut ctx, packed, 5, 1).unwrap_err();
-        assert!(err.to_string().contains("field 1 lowers at byte 4"));
-
-        // Nesting must not hide the incompatible packed representation.
-        let wide = mir_uint(&mut ctx, 64);
-        let outer: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "Outer".into(),
-            vec!["packed".into(), "wide".into()],
-            vec![packed, wide],
-            vec![0, 1],
-            vec![0, 8],
-            16,
-            8,
-        )
-        .into();
-        let err = validate_initialized_global_layout(&mut ctx, outer, 16, 8).unwrap_err();
-        assert!(err.to_string().contains("lowers at byte"));
-    }
-
-    #[test]
-    fn relocated_initialized_global_layout_accepts_top_level_packed_struct() {
-        let mut ctx = make_ctx();
-        let byte = mir_uint(&mut ctx, 8);
-        let target = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_global(&mut ctx, target, false).into();
-        let packed: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedRelocation".into(),
-            vec!["tag".into(), "ptr".into()],
-            vec![byte, pointer],
-            vec![0, 1],
-            vec![0, 1],
-            9,
-            1,
-        )
-        .into();
-
-        validate_relocated_initialized_global_layout(&mut ctx, packed, 9, 1)
-            .expect("relocated top-level packed struct must be accepted");
-        assert!(validate_initialized_global_layout(&mut ctx, packed, 9, 1).is_err());
-    }
-
-    #[test]
-    fn relocated_initialized_global_layout_accepts_thin_pointer_union() {
-        let mut ctx = make_ctx();
-        let u32_ty = mir_uint(&mut ctx, 32);
-        let u8_ty = mir_uint(&mut ctx, 8);
-        let word_ptr: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
-        let byte_ptr: TypeHandle = MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
-        let union_ty: TypeHandle = MirUnionType::get(
-            &mut ctx,
-            "RelocatedPointerUnion".into(),
-            vec!["word".into(), "byte".into()],
-            vec![word_ptr, byte_ptr],
-            8,
-            8,
-        )
-        .into();
-
-        validate_relocated_initialized_global_layout(&mut ctx, union_ty, 8, 8)
-            .expect("one pointer-word union must be valid relocated global storage");
-    }
-
-    #[test]
-    fn relocated_initialized_global_layout_rejects_malformed_memory_order() {
-        let mut ctx = make_ctx();
-        let byte = mir_uint(&mut ctx, 8);
-        let target = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_global(&mut ctx, target, false).into();
-        let malformed: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "MalformedPackedRelocation".into(),
-            vec!["tag".into(), "ptr".into()],
-            vec![byte, pointer],
-            vec![0, 0],
-            vec![0, 1],
-            9,
-            1,
-        )
-        .into();
-
-        let error = validate_relocated_initialized_global_layout(&mut ctx, malformed, 9, 1)
-            .expect_err("malformed memory order must remain unsupported");
-        assert!(error.to_string().contains("not a permutation"), "{error}");
-    }
-
-    #[test]
-    fn relocated_initialized_global_layout_accepts_one_direct_nested_packed_struct() {
-        let mut ctx = make_ctx();
-        let byte = mir_uint(&mut ctx, 8);
-        let word = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_global(&mut ctx, word, false).into();
-        let nested_packed: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "NestedPackedRelocation".into(),
-            vec!["tag".into(), "ptr".into()],
-            vec![byte, pointer],
-            vec![0, 1],
-            vec![0, 1],
-            9,
-            1,
-        )
-        .into();
-        let outer: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "OuterPackedRelocation".into(),
-            vec!["head".into(), "nested".into()],
-            vec![word, nested_packed],
-            vec![0, 1],
-            vec![0, 4],
-            16,
-            4,
-        )
-        .into();
-
-        validate_relocated_initialized_global_layout(&mut ctx, outer, 16, 4)
-            .expect("one direct nested packed relocation carrier must be accepted");
-        assert!(validate_initialized_global_layout(&mut ctx, outer, 16, 4).is_err());
-    }
-
-    #[test]
-    fn relocated_initialized_global_layout_rejects_packed_root_with_packed_child() {
-        let mut ctx = make_ctx();
-        let byte = mir_uint(&mut ctx, 8);
-        let word = mir_uint(&mut ctx, 32);
-        let target = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_global(&mut ctx, target, false).into();
-        let nested_packed: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "NestedPackedRelocation".into(),
-            vec!["tag".into(), "ptr".into()],
-            vec![byte, pointer],
-            vec![0, 1],
-            vec![0, 1],
-            9,
-            1,
-        )
-        .into();
-        let packed_root: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "PackedRootRelocation".into(),
-            vec!["tag".into(), "word".into(), "nested".into()],
-            vec![byte, word, nested_packed],
-            vec![0, 1, 2],
-            vec![0, 1, 5],
-            14,
-            1,
-        )
-        .into();
-
-        let error = validate_relocated_initialized_global_layout(&mut ctx, packed_root, 14, 1)
-            .expect_err("a packed top-level struct must not stack the nested packed relaxation");
-        assert!(error.to_string().contains("lowers at byte"), "{error}");
-    }
-
-    #[test]
-    fn relocated_initialized_global_layout_rejects_deeper_packed_nesting() {
-        let mut ctx = make_ctx();
-        let byte = mir_uint(&mut ctx, 8);
-        let word = mir_uint(&mut ctx, 32);
-        let target = mir_uint(&mut ctx, 32);
-        let pointer: TypeHandle = MirPtrType::get_global(&mut ctx, target, false).into();
-        let inner_packed: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "InnerPackedRelocation".into(),
-            vec!["tag".into(), "ptr".into()],
-            vec![byte, pointer],
-            vec![0, 1],
-            vec![0, 1],
-            9,
-            1,
-        )
-        .into();
-        let middle_packed: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "MiddlePackedRelocation".into(),
-            vec!["tag".into(), "word".into(), "inner".into()],
-            vec![byte, word, inner_packed],
-            vec![0, 1, 2],
-            vec![0, 1, 5],
-            14,
-            1,
-        )
-        .into();
-        let outer: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "OuterDeepPackedRelocation".into(),
-            vec!["head".into(), "middle".into()],
-            vec![word, middle_packed],
-            vec![0, 1],
-            vec![0, 4],
-            20,
-            4,
-        )
-        .into();
-
-        let error = validate_relocated_initialized_global_layout(&mut ctx, outer, 20, 4)
-            .expect_err("packed relocation relaxation must stop after one nesting level");
-        assert!(error.to_string().contains("lowers at byte"), "{error}");
-    }
-
-    #[test]
-    fn relocated_initialized_global_layout_rejects_overlapping_struct_fields() {
-        let mut ctx = make_ctx();
-        let word = mir_uint(&mut ctx, 32);
-        let overlapping: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "OverlappingRelocation".into(),
-            vec!["left".into(), "right".into()],
-            vec![word, word],
-            vec![0, 1],
-            vec![0, 0],
-            4,
-            1,
-        )
-        .into();
-
-        let error = validate_relocated_initialized_global_layout(&mut ctx, overlapping, 4, 1)
-            .expect_err("overlapping field ranges must remain unsupported");
-        assert!(error.to_string().contains("overlap"), "{error}");
-    }
-
-    #[test]
-    fn initialized_global_layout_rejects_old_union_and_tuple_models() {
-        let mut ctx = make_ctx();
-        let word = mir_uint(&mut ctx, 32);
-        let union_as_struct: TypeHandle = MirStructType::get_with_full_layout(
-            &mut ctx,
-            "UnionBeforeSharedStorageLowering".into(),
-            vec!["left".into(), "right".into()],
-            vec![word, word],
-            vec![0, 1],
-            vec![0, 0],
-            4,
-            4,
-        )
-        .into();
-        let err = validate_initialized_global_layout(&mut ctx, union_as_struct, 4, 4).unwrap_err();
-        assert!(err.to_string().contains("field 1 lowers at byte 4"));
-
-        // A tuple without recorded rustc layout cannot prove its bytes.
-        let byte = mir_uint(&mut ctx, 8);
-        let wide = mir_uint(&mut ctx, 64);
-        let tuple: TypeHandle = MirTupleType::get(&mut ctx, vec![byte, wide]).into();
-        let err = validate_initialized_global_layout(&mut ctx, tuple, 16, 8).unwrap_err();
-        assert!(
-            err.to_string()
-                .contains("no stored size but lowers to 16 bytes"),
-            "{err}"
-        );
-
-        // The same tuple carrying rustc's real (reordered) layout validates:
-        // memory order is (wide @ 0, byte @ 8), total size 16.
-        let laid_out_tuple: TypeHandle = MirTupleType::get_with_layout(
-            &mut ctx,
-            vec![byte, wide],
-            vec![1, 0],
-            vec![8, 0],
-            16,
-            8,
-        )
-        .into();
-        validate_initialized_global_layout(&mut ctx, laid_out_tuple, 16, 8)
-            .expect("tuples with recorded rustc offsets are provable initialized-global storage");
-    }
-
-    #[test]
-    fn initialized_global_layout_rejects_enum_with_unknown_physical_layout() {
-        let mut ctx = make_ctx();
-        let discr = mir_uint(&mut ctx, 8);
-        let payload = mir_uint(&mut ctx, 32);
-        let niche: TypeHandle = MirEnumType::get(
-            &mut ctx,
-            "OptionNonZero".into(),
-            discr,
-            vec![0, 1],
-            vec![
-                EnumVariant::unit("None".into()),
-                EnumVariant::new("Some".into(), vec![payload]),
-            ],
-        )
-        .into();
-
-        let err = validate_initialized_global_layout(&mut ctx, niche, 4, 4).unwrap_err();
-        assert!(err.to_string().contains("unknown physical layout"));
-    }
-}
diff --git a/crates/mir-lower/src/convert/types/conversion.rs b/crates/mir-lower/src/convert/types/conversion.rs
new file mode 100644
index 0000000000..1df786d65f
--- /dev/null
+++ b/crates/mir-lower/src/convert/types/conversion.rs
@@ -0,0 +1,153 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! `convert_type` dispatch, ZST detection, and the slice fat-pointer builders.
+
+use llvm_export::types as llvm_types;
+use llvm_export::types::PointerTypeExt;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::r#type::{TypeHandle, type_cast};
+
+use crate::type_conversion_interface::MirTypeConversion;
+
+// =============================================================================
+// Zero-Sized Type (ZST) Detection
+// =============================================================================
+
+/// Check if a type is zero-sized (empty struct).
+///
+/// Zero-sized types include:
+/// - Empty structs `struct {}`
+/// - PhantomData markers (which become empty structs in MIR)
+/// - Structs where all fields are themselves zero-sized
+///
+/// # Why This Matters
+///
+/// LLVM's NVPTX backend doesn't support empty struct types in function
+/// signatures. We strip these during type conversion to avoid:
+/// `LLVM ERROR: Empty parameter types are not supported`
+///
+/// # Background
+///
+/// Rust's `#[inline(always)]` attribute is stored in `codegen_fn_attrs`, which
+/// is not exposed through the stable_mir API. Since we intercept MIR and generate
+/// our own LLVM IR, we don't propagate inline hints. When LLVM decides not to
+/// inline a function, the empty struct parameters/returns cause NVPTX to crash.
+///
+/// By stripping ZSTs at the LLVM type level, we avoid this issue regardless of
+/// inlining decisions.
+pub fn is_zero_sized_type(ctx: &Context, ty: TypeHandle) -> bool {
+    if let Some(array_ty) = ty.deref(ctx).downcast_ref::<llvm_types::ArrayType>() {
+        return array_ty.size() == 0 || is_zero_sized_type(ctx, array_ty.elem_type());
+    }
+
+    // Check if LLVM StructType with zero fields
+    if let Some(struct_ty) = ty.deref(ctx).downcast_ref::<llvm_types::StructType>() {
+        let num_fields = struct_ty.num_fields();
+        if num_fields == 0 {
+            return true;
+        }
+        // Also check if ALL fields are zero-sized (nested PhantomData)
+        return struct_ty.fields().all(|f| is_zero_sized_type(ctx, f));
+    }
+    false
+}
+
+// =============================================================================
+// Type Conversion
+// =============================================================================
+
+/// Convert a `dialect-mir` type to its LLVM dialect equivalent.
+///
+/// Dispatches via `MirTypeConversion` type interface — each supported type
+/// registers a converter function pointer through `#[type_interface_impl]`
+/// in [`crate::convert::type_interface_impls`].
+///
+/// The function-pointer indirection avoids a borrow-checker conflict:
+/// `type_cast` borrows `ctx` immutably, but conversion needs `&mut ctx`.
+/// We extract the `Copy` function pointer, drop the borrow, then call it.
+pub fn convert_type(ctx: &mut Context, ty: TypeHandle) -> Result<TypeHandle, anyhow::Error> {
+    // Phase 1: extract a Copy function pointer while ctx is immutably borrowed.
+    let converter_fn = {
+        let ty_ref = ty.deref(ctx);
+        type_cast::<dyn MirTypeConversion>(&*ty_ref).map(|conv| conv.converter())
+    };
+    // Phase 2: borrow dropped — ctx is free for &mut.
+    if let Some(conv_fn) = converter_fn {
+        return conv_fn(ty, ctx);
+    }
+
+    let type_display = ty.deref(ctx).disp(ctx).to_string();
+    Err(anyhow::anyhow!(
+        "Unsupported type conversion: {}\n\
+         Supported: integers, fp32, fp64, pointers, slices, tuples, structs, enums, arrays, vectors.",
+        type_display
+    ))
+}
+
+/// Create the LLVM struct type used for slice representations.
+///
+/// Slices are represented as fat pointers: `{ ptr, i64 }` where:
+/// - `ptr` is a generic address space (0) pointer to the data
+/// - `i64` is the number of elements (not bytes)
+///
+/// # Layout
+///
+/// ```text
+/// struct {
+///     ptr: !llvm.ptr,     ; offset 0, size 8
+///     len: i64,           ; offset 8, size 8
+/// }                       ; total size: 16 bytes
+/// ```
+///
+/// # Address Space
+///
+/// The pointer uses generic address space (0) because:
+/// - Slices passed to kernels may point to global memory
+/// - The kernel doesn't know at compile time which memory space
+/// - Generic pointers can be used with any memory type
+///
+/// # Usage
+///
+/// This type is used for:
+/// - `&[T]` slice arguments
+/// - `DisjointSlice<T>` (unique-ownership slice) arguments
+/// - Any other fat pointer representation
+pub(crate) fn make_slice_struct(ctx: &mut Context) -> TypeHandle {
+    let ptr_ty = llvm_types::PointerType::get_generic(ctx);
+    let len_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+    llvm_types::StructType::get_unnamed(
+        ctx,
+        (
+            vec![ptr_ty.into(), len_ty.into()],
+            llvm_types::StructLayout::Unpacked,
+        ),
+    )
+    .into()
+}
+
+/// The fat pointer, followed by an index space's runtime layout fields.
+///
+/// With no such fields this is exactly [`make_slice_struct`], so a slice over
+/// an index space fixed in its type keeps its two-field representation.
+pub(crate) fn make_disjoint_slice_struct(
+    ctx: &mut Context,
+    space_tys: &[TypeHandle],
+) -> anyhow::Result<TypeHandle> {
+    if space_tys.is_empty() {
+        return Ok(make_slice_struct(ctx));
+    }
+    let ptr_ty = llvm_types::PointerType::get_generic(ctx);
+    let len_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+    let mut fields: Vec<TypeHandle> = vec![ptr_ty.into(), len_ty.into()];
+    for space_ty in space_tys {
+        fields.push(convert_type(ctx, *space_ty)?);
+    }
+    Ok(
+        llvm_types::StructType::get_unnamed(ctx, (fields, llvm_types::StructLayout::Unpacked))
+            .into(),
+    )
+}
diff --git a/crates/mir-lower/src/convert/types/enum_layout.rs b/crates/mir-lower/src/convert/types/enum_layout.rs
new file mode 100644
index 0000000000..25eb043d10
--- /dev/null
+++ b/crates/mir-lower/src/convert/types/enum_layout.rs
@@ -0,0 +1,2014 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! The `EnumSlotMap` placement engine and enum type conversion
+//! (`build_enum_slot_map`, `convert_enum_to_llvm`, unmodeled-enum probes).
+
+use dialect_mir::types::{
+    EnumCarrierKind, EnumLayoutKind, MirDisjointSliceType, MirEnumType, MirSliceType,
+    MirStructType, MirTupleType, MirUnionType,
+};
+use llvm_export::types as llvm_types;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::r#type::TypeHandle;
+
+use super::layout::{make_enum_filler_type, mir_type_contains_i1};
+use super::pointer_storage::{
+    PointerOverlapRejection, analyze_pointer_overlap, llvm_type_contains_pointer,
+};
+use super::{
+    convert_type, is_zero_sized_type, llvm_type_contains_i1, llvm_type_is_byte_faithful,
+    llvm_type_size_align, natural_struct_layout,
+};
+use crate::convert::enum_payload_storage::{
+    MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES, enum_payload_storage_type,
+};
+
+/// The LLVM struct for an enum, plus a map saying where the tag and each
+/// payload field ended up.
+///
+/// The struct type and the indices into it are produced by one walk in
+/// [`build_enum_slot_map`], so they can never disagree. (Computing them
+/// separately is how the issue #128 class of bug happened for structs.)
+pub(crate) struct EnumSlotMap {
+    /// The final LLVM struct type, including any `[N x i8]` filler slots.
+    pub llvm_struct_ty: TypeHandle,
+    /// Which struct slot holds rustc's physical tag/niche carrier. `None`
+    /// for `Single` and `Empty` layouts, which have no tag in memory.
+    pub carrier_slot: Option<u32>,
+    /// Converted physical carrier type (integer or pointer), when present.
+    pub carrier_llvm_ty: Option<TypeHandle>,
+    /// Which struct slot holds each payload field, in the flattened
+    /// order of `MirEnumType::all_field_types`. `None` means the field
+    /// has no slot of its own: it is zero-sized, or its bytes are shared
+    /// with a different-typed field of another variant. Such fields are
+    /// read and written through memory at `field_offsets` instead.
+    pub field_slots: Vec<Option<u32>>,
+    /// Byte position of each payload field inside the enum.
+    pub field_offsets: Vec<u64>,
+    /// Converted LLVM type of each payload field.
+    pub field_llvm_types: Vec<TypeHandle>,
+}
+
+/// Build the LLVM struct for an enum, placing everything at the byte
+/// positions rustc chose.
+///
+/// Why this matters: the host (CPU) lays out enum values with rustc's
+/// layout. If the device used different byte positions, every enum
+/// passed to a kernel would be read wrong. So the device struct is built
+/// to have the same bytes, position for position.
+///
+/// The wrinkle is that enum variants SHARE bytes (only one variant is
+/// alive at a time), and an LLVM struct cannot say "these two fields
+/// overlap". The slot map resolves each field one of three ways:
+///
+/// ```text
+/// #[repr(u32)] enum E { A(u32), B(f32), C }
+/// rustc: 8 bytes, tag at byte 0, A's u32 and B's f32 both at byte 4
+///
+/// LLVM struct: { i32, i32 }
+///                 |     |
+///        tag_slot=0     A's payload: own slot (nothing else typed i32
+///                       wanted byte 4 first... B did, see below)
+///
+/// - own slot:   the field's bytes collide with nothing already placed.
+/// - shared slot: another variant already placed the SAME type at the
+///                SAME position; both map to that slot. (If B were
+///                B(u32), A and B would simply share slot 1.)
+/// - no slot:    the bytes are taken by a different type (B's f32 vs
+///                A's u32 here). The field is still at byte 4, just not
+///                nameable as a struct field; reads and writes go
+///                through memory: spill the value to a stack slot, then
+///                use a byte-precise pointer. No slot, but no lie.
+/// ```
+///
+/// Gaps between placed fields, and the tail, are covered with explicit
+/// `[N x i8]` filler so the struct's size is exactly rustc's no matter
+/// what LLVM's own layout rules would have done.
+///
+/// Direct and Niche carriers are claimed first, so a semantic field with a
+/// different SSA type cannot redefine the same physical bytes. Single and
+/// Empty layouts simply have no carrier. Unknown layouts are rejected.
+///
+/// If the finished struct's size does not come out equal to rustc's,
+/// something is deeply wrong and lowering would miscompile, so that is a
+/// hard error rather than a debug assertion.
+pub(crate) fn build_enum_slot_map(
+    ctx: &mut Context,
+    ty: TypeHandle,
+) -> Result<EnumSlotMap, anyhow::Error> {
+    let (
+        name,
+        discriminant_ty,
+        all_field_types,
+        all_field_offsets,
+        all_field_sizes,
+        variant_field_counts,
+        variant_inhabited,
+        tag_offset,
+        total_size,
+        abi_align,
+        layout_kind,
+        carrier_kind,
+        carrier_width,
+        carrier_address_space,
+    ) = {
+        let ty_ref = ty.deref(ctx);
+        let enum_ty = ty_ref
+            .downcast_ref::<MirEnumType>()
+            .ok_or_else(|| anyhow::anyhow!("build_enum_slot_map: expected MirEnumType"))?;
+        (
+            enum_ty.name().to_string(),
+            enum_ty.discriminant_ty,
+            enum_ty.all_field_types.clone(),
+            enum_ty.all_field_offsets.clone(),
+            enum_ty.all_field_sizes.clone(),
+            enum_ty.variant_field_counts.clone(),
+            enum_ty.variant_inhabited.clone(),
+            enum_ty.tag_offset(),
+            enum_ty.total_size(),
+            enum_ty.abi_align(),
+            enum_ty.layout_kind,
+            enum_ty.carrier_kind,
+            enum_ty.carrier_width,
+            enum_ty.carrier_address_space,
+        )
+    };
+
+    if layout_kind == EnumLayoutKind::Unknown {
+        return Err(anyhow::anyhow!(
+            "enum slot map: `{}` has unknown physical layout; refusing to guess its bytes",
+            name
+        ));
+    }
+    if carrier_kind == EnumCarrierKind::Pointer
+        && carrier_address_space == llvm_types::address_space::SHARED
+    {
+        return Err(anyhow::anyhow!(
+            "enum slot map: `{}` uses a shared-memory pointer carrier whose size is target-mode dependent (64-bit PTX/legacy, 32-bit modern NVVM); refusing target-agnostic enum lowering",
+            name
+        ));
+    }
+    if carrier_kind == EnumCarrierKind::Integer && !carrier_width.is_multiple_of(8) {
+        return Err(anyhow::anyhow!(
+            "enum slot map: `{}` integer carrier width {} is not a whole number of bytes; refusing physical storage with unspecified upper byte bits",
+            name,
+            carrier_width
+        ));
+    }
+
+    let carrier_ty: Option<TypeHandle> = match carrier_kind {
+        EnumCarrierKind::None => None,
+        EnumCarrierKind::Integer if layout_kind == EnumLayoutKind::Direct => {
+            let converted = convert_type(ctx, discriminant_ty)?;
+            let width = converted
+                .deref(ctx)
+                .downcast_ref::<IntegerType>()
+                .map(IntegerType::width);
+            if width != Some(carrier_width) {
+                return Err(anyhow::anyhow!(
+                    "enum slot map: `{}` direct carrier does not match its declared discriminant type",
+                    name
+                ));
+            }
+            Some(converted)
+        }
+        EnumCarrierKind::Integer => {
+            Some(IntegerType::get(ctx, carrier_width, Signedness::Signless).into())
+        }
+        EnumCarrierKind::Pointer => {
+            Some(llvm_types::PointerType::get(ctx, carrier_address_space).into())
+        }
+    };
+    let mut field_llvm_types = Vec::with_capacity(all_field_types.len());
+    for &field_ty in &all_field_types {
+        field_llvm_types.push(convert_type(ctx, field_ty)?);
+    }
+
+    if all_field_offsets.len() != all_field_types.len()
+        || all_field_sizes.len() != all_field_types.len()
+    {
+        return Err(anyhow::anyhow!(
+            "enum slot map: `{}` has {} field offsets for {} fields",
+            name,
+            all_field_offsets.len().min(all_field_sizes.len()),
+            all_field_types.len()
+        ));
+    }
+
+    // Phase 1: decide who gets a struct slot. The physical carrier goes
+    // first so a semantic field can never claim its bytes using a different
+    // type (e.g. `bool` is i1 semantically but i8 in Option<bool> storage).
+    // claims: (byte position, byte size, converted type), no two overlap.
+    let mut claims: Vec<(u64, u64, TypeHandle)> = Vec::new();
+    let carrier_claim = if let Some(carrier_ty) = carrier_ty {
+        let (carrier_size, carrier_align) =
+            llvm_type_size_align(ctx, carrier_ty).ok_or_else(|| {
+                anyhow::anyhow!(
+                    "enum slot map: `{}` carrier has unsupported LLVM layout",
+                    name
+                )
+            })?;
+        let expected_size = u64::from(carrier_width).div_ceil(8);
+        if carrier_size != expected_size
+            || tag_offset % carrier_align.max(1) != 0
+            || tag_offset
+                .checked_add(carrier_size)
+                .is_none_or(|end| end > total_size)
+        {
+            return Err(anyhow::anyhow!(
+                "enum slot map: `{}` carrier (size {}, align {}) cannot sit at byte {} of {}",
+                name,
+                carrier_size,
+                carrier_align,
+                tag_offset,
+                total_size
+            ));
+        }
+        claims.push((tag_offset, carrier_size, carrier_ty));
+        Some(0usize)
+    } else {
+        None
+    };
+
+    let mut claim_of_field: Vec<Option<usize>> = vec![None; field_llvm_types.len()];
+    let mut field_is_inhabited = Vec::with_capacity(field_llvm_types.len());
+    for (variant, count) in variant_field_counts.iter().enumerate() {
+        field_is_inhabited.extend(std::iter::repeat_n(
+            variant_inhabited.get(variant).copied().unwrap_or(0) != 0,
+            *count as usize,
+        ));
+    }
+    let mut order: Vec<usize> = (0..field_llvm_types.len()).collect();
+    // At one byte position, prefer a representation that preserves all of
+    // its stored bits. This makes the result independent of source-variant
+    // order and prevents an i1/bool view from claiming storage that a later
+    // i8 view needs to preserve. A scalar i1 always uses an i8 storage claim:
+    // construction explicitly zero-extends that scalar below.
+    order.sort_by_key(|&i| {
+        (
+            all_field_offsets[i],
+            !llvm_type_is_byte_faithful(ctx, field_llvm_types[i]),
+            i,
+        )
+    });
+    for flat in order {
+        if !field_is_inhabited.get(flat).copied().unwrap_or(false) {
+            continue;
+        }
+        let llvm_ty = field_llvm_types[flat];
+        // Enum payload storage uses one target-stable physical view. Shared
+        // pointer leaves become generic pointers recursively through LLVM
+        // structs (MIR structs/tuples) and bounded arrays, while bool leaves
+        // become canonical i8 bytes. Oversized shared-pointer arrays and
+        // pointer vectors fail closed here.
+        let storage_ty = enum_payload_storage_type(ctx, llvm_ty).map_err(|error| {
+            anyhow::anyhow!("enum slot map: `{}` field {}: {error}", name, flat)
+        })?;
+        let (size, align) = llvm_type_size_align(ctx, storage_ty).ok_or_else(|| {
+            anyhow::anyhow!(
+                "enum slot map: `{}` field {} has unsupported LLVM size/alignment",
+                name,
+                flat
+            )
+        })?;
+        if size != all_field_sizes[flat] {
+            return Err(anyhow::anyhow!(
+                "enum slot map: `{}` field {} lowers to {} bytes but rustc says {}",
+                name,
+                flat,
+                size,
+                all_field_sizes[flat]
+            ));
+        }
+        if size == 0 || is_zero_sized_type(ctx, llvm_ty) {
+            // ZSTs own no bytes and no slot.
+            continue;
+        }
+        let offset = all_field_offsets[flat];
+        if offset.checked_add(size).is_none_or(|end| end > total_size) {
+            return Err(anyhow::anyhow!(
+                "enum slot map: `{}` field {} (size {}) at byte {} exceeds total size {}",
+                name,
+                flat,
+                size,
+                offset,
+                total_size
+            ));
+        }
+        if !offset.is_multiple_of(align.max(1)) {
+            return Err(anyhow::anyhow!(
+                "enum slot map: `{}` field {} requires alignment {} but rustc offset {} is not aligned; packed enum payload access is not yet supported",
+                name,
+                flat,
+                align,
+                offset
+            ));
+        }
+
+        let is_scalar_i1 = llvm_ty
+            .deref(ctx)
+            .downcast_ref::<IntegerType>()
+            .is_some_and(|integer| integer.width() == 1);
+        // A bool the MIR type promises but the LLVM lowering hides (a union
+        // whose storage is a raw byte blob) cannot be canonicalized here:
+        // its bytes were written by the union's own stores, not by this
+        // enum's construction.
+        if !is_scalar_i1
+            && mir_type_contains_i1(ctx, all_field_types[flat])
+            && !llvm_type_contains_i1(ctx, llvm_ty)
+        {
+            return Err(anyhow::anyhow!(
+                "enum slot map: `{}` field {} contains bool storage hidden behind a union; cuda-oxide cannot prove those bytes are canonical",
+                name,
+                flat
+            ));
+        }
+
+        // Rust bool is a semantic i1 but occupies a complete byte in memory.
+        // Never make i1 the struct's physical storage type: give a standalone
+        // bool an i8 claim, or reuse the exact i8 carrier/field claim already
+        // covering that byte. Construction leaves the bool slotless and the
+        // deferred store below explicitly zero-extends i1 -> i8; extraction
+        // loads i1 from that byte.
+        if is_scalar_i1 {
+            let colliding_claims = claims
+                .iter()
+                .filter(|&&(o, s, _)| offset < o + s && o < offset + size)
+                .collect::<Vec<_>>();
+            if colliding_claims.is_empty() {
+                let byte_ty: TypeHandle = IntegerType::get(ctx, 8, Signedness::Signless).into();
+                claims.push((offset, 1, byte_ty));
+                continue;
+            }
+            let has_exact_i8_storage = colliding_claims.iter().all(|&&(o, s, claim_ty)| {
+                o == offset
+                    && s == 1
+                    && claim_ty
+                        .deref(ctx)
+                        .downcast_ref::<IntegerType>()
+                        .is_some_and(|integer| integer.width() == 8)
+            });
+            if has_exact_i8_storage {
+                continue;
+            }
+            return Err(anyhow::anyhow!(
+                "enum slot map: `{}` scalar bool field {} overlaps storage other than one exact i8 byte; refusing to expose non-canonical bool bits",
+                name,
+                flat
+            ));
+        }
+
+        // Aggregates containing bool claim their byte-faithful twin (every
+        // i1 leaf becomes its canonical i8 memory byte) and stay slotless:
+        // construction canonicalizes the value and writes it at its byte
+        // offset; extraction re-loads the original type from the canonical
+        // bytes, exactly like the scalar-bool path above.
+        // Bool-bearing aggregates remain slotless so their canonical byte view
+        // continues through the established spill path. Pointer-only nested
+        // aggregates may own a slot because construction/extraction now rebuild
+        // them recursively at the semantic/physical boundary.
+        let field_gets_slot = !llvm_type_contains_i1(ctx, llvm_ty);
+
+        // Another variant already placed the same storage type at the same
+        // position? Then both fields can simply use that claim: variants
+        // share bytes, and here they even agree on the type.
+        if let Some(ci) = claims
+            .iter()
+            .position(|&(o, _, t)| o == offset && t == storage_ty)
+        {
+            if field_gets_slot {
+                claim_of_field[flat] = Some(ci);
+            }
+            continue;
+        }
+        // The bytes are taken by a different type. Pointer-free values can
+        // use the memory fallback below. Pointer-bearing values may do so only
+        // when a physical-layout walk proves that every pointer leaf exactly
+        // matches an existing pointer slot. This is the common
+        // `Option<(usize, &T)>` shape: the niche carrier is the tuple's pointer
+        // field. A pointer/non-pointer overlap, address-space mismatch, or
+        // additional pointer without a pointer slot still fails closed.
+        let colliding_claims = claims
+            .iter()
+            .filter(|&&(o, s, _)| offset < o + s && o < offset + size)
+            .collect::<Vec<_>>();
+        if !colliding_claims.is_empty() {
+            let has_pointer_overlap = llvm_type_contains_pointer(ctx, storage_ty)
+                || colliding_claims
+                    .iter()
+                    .any(|&&(_, _, claim_ty)| llvm_type_contains_pointer(ctx, claim_ty));
+            // Pointer-bearing overlaps must back every pointer leaf with a real
+            // `ptr` slot so the memory round-trip preserves provenance. The
+            // niche carrier backs the leaf that coincides with it; any further
+            // pointer leaf (the extra slice pointer in `split_at_mut_checked`'s
+            // `Option<(&mut [T], &mut [T])>`) gets its own fresh `ptr` slot.
+            // `ProvenanceLoss` means a pointer punned against non-pointer
+            // bits, which stays fail-closed; `OverArrayLeafBound` reports the
+            // same bounded rewrite contract as the payload storage gate.
+            let extra_pointer_claims = if has_pointer_overlap {
+                match analyze_pointer_overlap(ctx, offset, size, storage_ty, &colliding_claims) {
+                    Ok(extra) => extra,
+                    Err(PointerOverlapRejection::OverArrayLeafBound { required }) => {
+                        return Err(anyhow::anyhow!(
+                            "enum slot map: `{}` field {} overlaps pointer storage whose arrays are not supported above the bounded rewrite limit; rewrite requires {required} pointer conversions, supported bound is {MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES}",
+                            name,
+                            flat
+                        ));
+                    }
+                    Err(PointerOverlapRejection::ProvenanceLoss) => {
+                        return Err(anyhow::anyhow!(
+                            "enum slot map: `{}` has overlapping pointer and non-identical storage at byte {}; refusing to erase LLVM pointer provenance",
+                            name,
+                            offset
+                        ));
+                    }
+                }
+            } else {
+                Vec::new()
+            };
+            let incoming_is_byte_faithful = llvm_type_is_byte_faithful(ctx, storage_ty);
+            let claims_are_byte_faithful = colliding_claims
+                .iter()
+                .all(|&&(_, _, claim_ty)| llvm_type_is_byte_faithful(ctx, claim_ty));
+            if !incoming_is_byte_faithful || !claims_are_byte_faithful {
+                return Err(anyhow::anyhow!(
+                    "enum slot map: `{}` field {} overlaps non-identical storage but its lowered type is not byte-faithful (for example, it may contain implicit padding); refusing a type-punned store",
+                    name,
+                    flat
+                ));
+            }
+            // Back each extra pointer leaf with its own `ptr` slot (the field
+            // itself stays slotless and round-trips through memory). Added after
+            // the byte-faithfulness gate so `colliding_claims`'s borrow of
+            // `claims` has ended before we push.
+            for leaf in extra_pointer_claims {
+                let ptr_ty = llvm_types::PointerType::get(ctx, leaf.address_space).into();
+                claims.push((leaf.offset, leaf.size, ptr_ty));
+            }
+            continue;
+        }
+        claims.push((offset, size, storage_ty));
+        if field_gets_slot {
+            claim_of_field[flat] = Some(claims.len() - 1);
+        }
+    }
+
+    // Phase 2: lay the slots down in byte order, filling every gap (and
+    // the tail) so the struct's size is exactly rustc's. One integer per gap
+    // where that is layout-neutral, else [N x i8]; see `make_enum_filler_type`.
+    let mut emit_order: Vec<usize> = (0..claims.len()).collect();
+    emit_order.sort_by_key(|&ci| claims[ci].0);
+    let mut llvm_fields: Vec<TypeHandle> = Vec::new();
+    let mut slot_of_claim: Vec<u32> = vec![0; claims.len()];
+    let mut current_offset: u64 = 0;
+    for &ci in &emit_order {
+        let (offset, size, llvm_ty) = claims[ci];
+        if current_offset < offset {
+            let filler =
+                make_enum_filler_type(ctx, current_offset, offset - current_offset, abi_align);
+            llvm_fields.push(filler);
+            current_offset = offset;
+        }
+        slot_of_claim[ci] = llvm_fields.len() as u32;
+        llvm_fields.push(llvm_ty);
+        current_offset += size;
+    }
+    if current_offset < total_size {
+        let filler =
+            make_enum_filler_type(ctx, current_offset, total_size - current_offset, abi_align);
+        llvm_fields.push(filler);
+    }
+
+    // Sanity: the struct we just built must be exactly rustc's size.
+    // Arrays of enums step by this size, so a mismatch means every
+    // element after the first is read from the wrong place. That is a
+    // guaranteed miscompile, hence a hard error, not a debug check.
+    let (_end, natural_size, natural_align) = natural_struct_layout(ctx, &llvm_fields)
+        .ok_or_else(|| anyhow::anyhow!("enum slot map: `{}` has unsupported LLVM layout", name))?;
+    if natural_size != total_size {
+        return Err(anyhow::anyhow!(
+            "enum slot map: `{}` lowered to {} bytes but rustc says {}",
+            name,
+            natural_size,
+            total_size
+        ));
+    }
+    let required_align = abi_align.max(1);
+    if natural_align > required_align {
+        return Err(anyhow::anyhow!(
+            "enum slot map: `{}` lowered with alignment {} but rustc requires {}; explicit over-aligned enum storage is not yet supported",
+            name,
+            natural_align,
+            abi_align
+        ));
+    }
+    if natural_align < required_align {
+        // The byte claims alone can under-align the storage, e.g. when the
+        // only claim is an i8 niche carrier inside a 4-aligned enum. Raise
+        // the struct's alignment with a zero-length anchor field, the same
+        // mechanism union storage uses; it occupies no bytes, so every slot
+        // index simply shifts by one.
+        let anchor_int = IntegerType::get(ctx, (required_align * 8) as u32, Signedness::Signless);
+        let anchor: TypeHandle = llvm_types::ArrayType::get(ctx, anchor_int.into(), 0).into();
+        llvm_fields.insert(0, anchor);
+        for slot in &mut slot_of_claim {
+            *slot += 1;
+        }
+    }
+
+    let field_slots = claim_of_field
+        .into_iter()
+        .map(|c| c.map(|ci| slot_of_claim[ci]))
+        .collect();
+    Ok(EnumSlotMap {
+        llvm_struct_ty: llvm_types::StructType::get_unnamed(
+            ctx,
+            (llvm_fields, llvm_types::StructLayout::Unpacked),
+        )
+        .into(),
+        carrier_slot: carrier_claim.map(|claim| slot_of_claim[claim]),
+        carrier_llvm_ty: carrier_ty,
+        field_slots,
+        field_offsets: all_field_offsets,
+        field_llvm_types,
+    })
+}
+
+/// Convert a `MirEnumType` to its LLVM struct representation.
+///
+/// Thin wrapper over [`build_enum_slot_map`], which explains the layout.
+/// Any op that needs an index into the converted enum must take it from
+/// the slot map, never compute it by hand.
+pub(crate) fn convert_enum_to_llvm(
+    ctx: &mut Context,
+    ty: TypeHandle,
+) -> Result<TypeHandle, anyhow::Error> {
+    Ok(build_enum_slot_map(ctx, ty)?.llvm_struct_ty)
+}
+
+/// Return an enum name only when the dialect lacks rustc's physical layout.
+/// All importer-produced Direct, Niche, Single, and Empty layouts are
+/// byte-faithful; legacy `Unknown` values are rejected everywhere rather than
+/// receiving a guessed internal representation.
+pub(crate) fn enum_unmodeled_in_memory(ctx: &Context, ty: TypeHandle) -> Option<String> {
+    let ty_ref = ty.deref(ctx);
+    let enum_ty = ty_ref.downcast_ref::<MirEnumType>()?;
+    (enum_ty.layout_kind == EnumLayoutKind::Unknown).then(|| enum_ty.name().to_string())
+}
+
+/// Search a kernel parameter's type for an enum the host and device
+/// would disagree about (see [`enum_unmodeled_in_memory`]).
+///
+/// The search looks everywhere host data can hide: behind pointers,
+/// inside slices and arrays, in struct/tuple fields, and in other enums'
+/// payloads. It returns the first offending enum's name.
+///
+/// Kernel signatures are checked early for a focused diagnostic. Lowering also
+/// rejects Unknown layouts for locals, globals, and physical operations, so no
+/// guessed representation can escape through an internal-only path.
+///
+/// `visited` breaks cycles through recursive types (`TypeHandle` is
+/// interned, so equality is identity).
+pub(crate) fn find_unmodeled_enum_in_abi(
+    ctx: &mut Context,
+    ty: TypeHandle,
+    visited: &mut Vec<TypeHandle>,
+) -> Result<Option<String>, anyhow::Error> {
+    if visited.contains(&ty) {
+        return Ok(None);
+    }
+    visited.push(ty);
+
+    if let Some(name) = enum_unmodeled_in_memory(ctx, ty) {
+        return Ok(Some(name));
+    }
+
+    let children: Vec<TypeHandle> = {
+        let ty_ref = ty.deref(ctx);
+        if let Some(p) = ty_ref.downcast_ref::<dialect_mir::types::MirPtrType>() {
+            vec![p.pointee]
+        } else if let Some(s) = ty_ref.downcast_ref::<MirSliceType>() {
+            vec![s.element_ty]
+        } else if let Some(s) = ty_ref.downcast_ref::<MirDisjointSliceType>() {
+            let mut nested = vec![s.element_ty];
+            nested.extend_from_slice(&s.space_tys);
+            nested
+        } else if let Some(a) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
+            vec![a.element_ty]
+        } else if let Some(s) = ty_ref.downcast_ref::<MirStructType>() {
+            s.field_types.clone()
+        } else if let Some(u) = ty_ref.downcast_ref::<MirUnionType>() {
+            u.field_types.clone()
+        } else if let Some(t) = ty_ref.downcast_ref::<MirTupleType>() {
+            t.get_types().to_vec()
+        } else if let Some(e) = ty_ref.downcast_ref::<MirEnumType>() {
+            e.all_field_types.clone()
+        } else {
+            vec![]
+        }
+    };
+
+    for child in children {
+        if let Some(name) = find_unmodeled_enum_in_abi(ctx, child, visited)? {
+            return Ok(Some(name));
+        }
+    }
+    Ok(None)
+}
+
+#[cfg(test)]
+mod tests {
+    use super::super::llvm_type_contains_pointer_in_address_space;
+    use super::super::test_support::{llvm_int, make_ctx, mir_uint, struct_fields};
+    use super::*;
+    use dialect_mir::types::{EnumEncoding, EnumVariant, MirArrayType, MirPtrType};
+    use pliron::builtin::types::FP32Type;
+
+    #[test]
+    fn enum_array_payload_keeps_exact_size_alignment_and_stride() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 8);
+        let element = mir_uint(&mut ctx, 16);
+        let payload: TypeHandle = MirArrayType::get(&mut ctx, element, 3).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "ArrayPayload".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("Empty".into()),
+                EnumVariant::new_with_layout("Data".into(), vec![payload], vec![2], vec![6]),
+            ],
+            0,
+            8,
+            2,
+        )
+        .into();
+        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((8, 2)));
+
+        let array: TypeHandle = MirArrayType::get(&mut ctx, enum_ty, 5).into();
+        let lowered = convert_type(&mut ctx, array).unwrap();
+        assert_eq!(llvm_type_size_align(&ctx, lowered), Some((40, 2)));
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_partial_byte_integer_carriers() {
+        let mut ctx = make_ctx();
+        let partial_discriminant = mir_uint(&mut ctx, 7);
+        let direct: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "PartialDirect".into(),
+            partial_discriminant,
+            vec![0, 1],
+            vec![EnumVariant::unit("A".into()), EnumVariant::unit("B".into())],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 1,
+                abi_align: 1,
+                layout_kind: EnumLayoutKind::Direct,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 7,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        let error = build_enum_slot_map(&mut ctx, direct)
+            .err()
+            .expect("partial-byte Direct carrier must fail closed");
+        assert!(
+            error.to_string().contains("whole number of bytes"),
+            "{error}"
+        );
+
+        let logical = mir_uint(&mut ctx, 8);
+        let payload = mir_uint(&mut ctx, 8);
+        let niche: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "PartialNiche".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![1]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 1,
+                abi_align: 1,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 7,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        let error = build_enum_slot_map(&mut ctx, niche)
+            .err()
+            .expect("partial-byte Niche carrier must fail closed");
+        assert!(
+            error.to_string().contains("whole number of bytes"),
+            "{error}"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_misaligned_inhabited_payload() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 8);
+        let word = mir_uint(&mut ctx, 32);
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "PackedPayload".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("Empty".into()),
+                EnumVariant::new_with_layout("Data".into(), vec![word], vec![1], vec![4]),
+            ],
+            0,
+            8,
+            4,
+        )
+        .into();
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("misaligned payload must be rejected");
+        assert!(error.to_string().contains("offset 1 is not aligned"));
+    }
+
+    #[test]
+    fn enum_slot_map_uses_i8_storage_for_nonoverlapping_scalar_bool() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 32);
+        let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "DirectBool".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::new_with_layout("A".into(), vec![boolean], vec![4], vec![1]),
+                EnumVariant::unit("B".into()),
+            ],
+            0,
+            8,
+            4,
+        )
+        .into();
+
+        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(map.field_slots, vec![None]);
+        let fields = struct_fields(&ctx, map.llvm_struct_ty);
+        assert_eq!(fields.len(), 3, "tag, canonical bool byte, tail pad");
+        assert_eq!(
+            fields[1]
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .map(IntegerType::width),
+            Some(8),
+            "Rust bool storage must be an i8 byte, never an LLVM i1 slot"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_allows_nonoverlapping_aggregate_padding_without_bool() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 32);
+        let byte = mir_uint(&mut ctx, 8);
+        let word = mir_uint(&mut ctx, 32);
+        let padded: TypeHandle = MirTupleType::get(&mut ctx, vec![byte, word]).into();
+        let lowered_padded = convert_type(&mut ctx, padded).unwrap();
+        assert!(
+            !llvm_type_is_byte_faithful(&ctx, lowered_padded),
+            "the LLVM i8/i32 tuple has harmless implicit padding"
+        );
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "PaddedPayload".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::new_with_layout("Data".into(), vec![padded], vec![4], vec![8]),
+                EnumVariant::unit("Empty".into()),
+            ],
+            0,
+            12,
+            4,
+        )
+        .into();
+
+        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(map.field_slots, vec![Some(1)]);
+        assert_eq!(
+            llvm_type_size_align(&ctx, map.llvm_struct_ty),
+            Some((12, 4))
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_nonoverlapping_nested_bool_storage() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 32);
+        let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
+        let wrapper: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "BoolWrapper".into(),
+            vec!["value".into()],
+            vec![boolean],
+            vec![0],
+            vec![0],
+            1,
+            1,
+        )
+        .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "DirectBoolWrapper".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::new_with_layout("A".into(), vec![wrapper], vec![4], vec![1]),
+                EnumVariant::unit("B".into()),
+            ],
+            0,
+            8,
+            4,
+        )
+        .into();
+
+        // The wrapper claims its byte-faithful twin ({i8}) and stays
+        // slotless: construction canonicalizes the bool byte, extraction
+        // re-loads the original {i1} shape from the canonical byte.
+        let map = build_enum_slot_map(&mut ctx, enum_ty)
+            .expect("nested bool storage canonicalizes through its byte-faithful twin");
+        assert_eq!(map.field_slots, vec![None]);
+        assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((8, 4)));
+        let struct_fields: Vec<_> = map
+            .llvm_struct_ty
+            .deref(&ctx)
+            .downcast_ref::<llvm_types::StructType>()
+            .unwrap()
+            .fields()
+            .collect();
+        assert!(
+            struct_fields
+                .iter()
+                .all(|field| !llvm_type_contains_i1(&ctx, *field)),
+            "enum storage must never contain physical i1"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_bool_hidden_by_union_byte_storage() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 32);
+        let byte = mir_uint(&mut ctx, 8);
+        let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
+        let union: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "BoolOrByte".into(),
+            vec!["flag".into(), "byte".into()],
+            vec![boolean, byte],
+            1,
+            1,
+        )
+        .into();
+        let lowered_union = convert_type(&mut ctx, union).unwrap();
+        assert!(
+            !llvm_type_contains_i1(&ctx, lowered_union),
+            "the union's raw-byte carrier intentionally hides its semantic bool"
+        );
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "DirectUnionBool".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::new_with_layout("A".into(), vec![union], vec![4], vec![1]),
+                EnumVariant::unit("B".into()),
+            ],
+            0,
+            8,
+            4,
+        )
+        .into();
+
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("a bool hidden by union byte storage must still fail closed");
+        assert!(
+            error.to_string().contains("hidden behind a union"),
+            "{error}"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_does_not_descend_through_pointer_to_bool() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 32);
+        let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
+        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, boolean, false).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "PointerToBool".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::new_with_layout("A".into(), vec![pointer], vec![8], vec![8]),
+                EnumVariant::unit("B".into()),
+            ],
+            0,
+            16,
+            8,
+        )
+        .into();
+
+        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert!(map.field_slots[0].is_some());
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_pointer_nonpointer_overlap_in_either_variant_order() {
+        for pointer_first in [false, true] {
+            let mut ctx = make_ctx();
+            let discr = mir_uint(&mut ctx, 32);
+            let u8_ty = mir_uint(&mut ctx, 8);
+            let u64_ty = mir_uint(&mut ctx, 64);
+            let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
+            let (first_name, first_ty, second_name, second_ty) = if pointer_first {
+                ("Ptr", pointer, "Bits", u64_ty)
+            } else {
+                ("Bits", u64_ty, "Ptr", pointer)
+            };
+            let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+                &mut ctx,
+                "PointerOrBits".into(),
+                discr,
+                vec![0, 1],
+                vec![
+                    EnumVariant::new_with_layout(
+                        first_name.into(),
+                        vec![first_ty],
+                        vec![8],
+                        vec![8],
+                    ),
+                    EnumVariant::new_with_layout(
+                        second_name.into(),
+                        vec![second_ty],
+                        vec![8],
+                        vec![8],
+                    ),
+                ],
+                EnumEncoding {
+                    tag_offset: 0,
+                    total_size: 16,
+                    abi_align: 8,
+                    layout_kind: EnumLayoutKind::Direct,
+                    carrier_kind: EnumCarrierKind::Integer,
+                    carrier_width: 32,
+                    variant_inhabited: vec![1, 1],
+                    ..EnumEncoding::default()
+                },
+            )
+            .into();
+            let error = build_enum_slot_map(&mut ctx, enum_ty)
+                .err()
+                .expect("pointer overlap must reject");
+            assert!(
+                error.to_string().contains("pointer provenance"),
+                "pointer_first={pointer_first}: {error}"
+            );
+        }
+    }
+
+    #[test]
+    fn enum_slot_map_canonicalizes_overlapping_bool_wrapper_storage() {
+        let mut ctx = make_ctx();
+        let logical = mir_uint(&mut ctx, 8);
+        let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
+        let wrapper: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "BoolWrapper".into(),
+            vec!["value".into()],
+            vec![boolean],
+            vec![0],
+            vec![0],
+            1,
+            1,
+        )
+        .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "MaybeBoolWrapper".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![wrapper], vec![0], vec![1]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 1,
+                abi_align: 1,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 8,
+                niche_start: 2,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        // Option<Wrapper(bool)>: the wrapper's byte-faithful twin ({i8})
+        // shares the single canonical byte with the i8 niche carrier. The
+        // wrapper stays slotless; construction zero-extends its bool.
+        let map = build_enum_slot_map(&mut ctx, enum_ty)
+            .expect("a bool wrapper shares its canonical byte with the i8 carrier");
+        assert_eq!(map.field_slots, vec![None]);
+        assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((1, 1)));
+        assert!(
+            !llvm_type_contains_i1(&ctx, map.llvm_struct_ty),
+            "enum storage must never contain physical i1"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_canonicalizes_bool_wrapper_overlap_in_either_variant_order() {
+        for wrapper_first in [false, true] {
+            let mut ctx = make_ctx();
+            let tag = mir_uint(&mut ctx, 32);
+            let byte = mir_uint(&mut ctx, 8);
+            let boolean: TypeHandle = IntegerType::get(&ctx, 1, Signedness::Signless).into();
+            let wrapper: TypeHandle = MirStructType::get_with_full_layout(
+                &mut ctx,
+                "BoolWrapper".into(),
+                vec!["value".into()],
+                vec![boolean],
+                vec![0],
+                vec![0],
+                1,
+                1,
+            )
+            .into();
+            let (first, second) = if wrapper_first {
+                (wrapper, byte)
+            } else {
+                (byte, wrapper)
+            };
+            let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+                &mut ctx,
+                "BoolWrapperOrByte".into(),
+                tag,
+                vec![0, 1],
+                vec![
+                    EnumVariant::new_with_layout("First".into(), vec![first], vec![4], vec![1]),
+                    EnumVariant::new_with_layout("Second".into(), vec![second], vec![4], vec![1]),
+                ],
+                EnumEncoding {
+                    tag_offset: 0,
+                    total_size: 8,
+                    abi_align: 4,
+                    layout_kind: EnumLayoutKind::Direct,
+                    carrier_kind: EnumCarrierKind::Integer,
+                    carrier_width: 32,
+                    variant_inhabited: vec![1, 1],
+                    ..EnumEncoding::default()
+                },
+            )
+            .into();
+
+            // The wrapper's canonical twin ({i8}) and the plain u8 variant
+            // share one byte-faithful byte, independent of declaration
+            // order; the wrapper stays slotless either way.
+            let map = build_enum_slot_map(&mut ctx, enum_ty)
+                .expect("canonical bool bytes may share storage with a u8 variant");
+            assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((8, 4)));
+            assert!(
+                !llvm_type_contains_i1(&ctx, map.llvm_struct_ty),
+                "wrapper_first={wrapper_first}: enum storage must never contain physical i1"
+            );
+            let wrapper_flat = if wrapper_first { 0 } else { 1 };
+            assert_eq!(map.field_slots[wrapper_flat], None);
+        }
+    }
+
+    #[test]
+    fn enum_slot_map_backs_pointer_beside_integer_niche_carrier() {
+        let mut ctx = make_ctx();
+        let logical = mir_uint(&mut ctx, 8);
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let payload: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PointerThenNiche".into(),
+            vec!["pointer".into(), "niche".into()],
+            vec![pointer, u32_ty],
+            vec![0, 1],
+            vec![0, 8],
+            16,
+            8,
+        )
+        .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "MaybePointerThenNiche".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
+            ],
+            EnumEncoding {
+                tag_offset: 8,
+                total_size: 16,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 32,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        // The pointer at byte 0 never shares bytes with the integer niche
+        // carrier at byte 8, so it is representable: it gets its own `ptr` slot
+        // and the carrier stays an integer slot. `{ptr@0, i32@8, i32 filler}`
+        // -- the trailing 4 bytes are 4-aligned inside an 8-aligned enum, so
+        // they lower to one `i32` rather than `[4 x i8]`.
+        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(map.field_slots, vec![None]);
+        let lowered_pointer = convert_type(&mut ctx, pointer).unwrap();
+        let carrier: TypeHandle = IntegerType::get(&ctx, 32, Signedness::Signless).into();
+        assert_eq!(
+            struct_fields(&ctx, map.llvm_struct_ty),
+            vec![lowered_pointer, carrier, llvm_int(&mut ctx, 32)]
+        );
+        assert_eq!(
+            llvm_type_size_align(&ctx, map.llvm_struct_ty),
+            Some((16, 8))
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_keeps_plain_pointer_niche_in_one_pointer_slot() {
+        let mut ctx = make_ctx();
+        let logical = mir_uint(&mut ctx, 8);
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "MaybePointer".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![pointer], vec![0], vec![8]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 8,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(map.carrier_slot, Some(0));
+        assert_eq!(map.field_slots, vec![Some(0)]);
+        assert!(
+            struct_fields(&ctx, map.llvm_struct_ty)[0]
+                .deref(&ctx)
+                .is::<llvm_types::PointerType>()
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_accepts_pointer_first_and_pointer_second_aggregate_niches() {
+        for pointer_first in [true, false] {
+            let mut ctx = make_ctx();
+            let logical = mir_uint(&mut ctx, 64);
+            let index = mir_uint(&mut ctx, 64);
+            let pointee = mir_uint(&mut ctx, 32);
+            let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
+            let payload_types = if pointer_first {
+                vec![pointer, index]
+            } else {
+                vec![index, pointer]
+            };
+            let payload: TypeHandle = MirTupleType::get(&mut ctx, payload_types).into();
+            let tag_offset = if pointer_first { 0 } else { 8 };
+            let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+                &mut ctx,
+                "MaybeIndexedRef".into(),
+                logical,
+                vec![0, 1],
+                vec![
+                    EnumVariant::unit("None".into()),
+                    EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
+                ],
+                EnumEncoding {
+                    tag_offset,
+                    total_size: 16,
+                    abi_align: 8,
+                    layout_kind: EnumLayoutKind::Niche,
+                    carrier_kind: EnumCarrierKind::Pointer,
+                    carrier_width: 64,
+                    untagged_variant: 1,
+                    variant_inhabited: vec![1, 1],
+                    ..EnumEncoding::default()
+                },
+            )
+            .into();
+
+            let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+            assert_eq!(map.field_slots, vec![None]);
+            assert_eq!(map.carrier_slot, Some(if pointer_first { 0 } else { 1 }));
+            assert_eq!(
+                llvm_type_size_align(&ctx, map.llvm_struct_ty),
+                Some((16, 8))
+            );
+            let lowered_pointer = convert_type(&mut ctx, pointer).unwrap();
+            // The 8 bytes the pointer slot does not claim are 8-aligned inside
+            // an 8-aligned enum, so they lower to one `i64`, not `[8 x i8]`.
+            let filler = llvm_int(&mut ctx, 64);
+            let expected = if pointer_first {
+                vec![lowered_pointer, filler]
+            } else {
+                vec![filler, lowered_pointer]
+            };
+            assert_eq!(struct_fields(&ctx, map.llvm_struct_ty), expected);
+        }
+    }
+
+    #[test]
+    fn enum_slot_map_backs_each_aggregate_pointer_leaf_with_its_own_slot() {
+        let mut ctx = make_ctx();
+        let logical = mir_uint(&mut ctx, 64);
+        let pointee = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
+        let payload: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "TwoRefs".into(),
+            vec!["first".into(), "second".into()],
+            vec![pointer, pointer],
+            vec![0, 1],
+            vec![0, 8],
+            16,
+            8,
+        )
+        .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "MaybeTwoRefs".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
+            ],
+            EnumEncoding {
+                tag_offset: 8,
+                total_size: 16,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        // Both pointer leaves are representable without erasing provenance: the
+        // carrier backs the leaf at byte 8, and the leaf at byte 0 gets its own
+        // fresh `ptr` slot. The payload stays slotless and round-trips through
+        // `{ptr@0, ptr@8}`.
+        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(map.field_slots, vec![None]);
+        let lowered_pointer = convert_type(&mut ctx, pointer).unwrap();
+        assert_eq!(
+            struct_fields(&ctx, map.llvm_struct_ty),
+            vec![lowered_pointer, lowered_pointer]
+        );
+        assert_eq!(
+            llvm_type_size_align(&ctx, map.llvm_struct_ty),
+            Some((16, 8))
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_backs_split_at_mut_slice_pair() {
+        // Models `Option<(&mut [u32], &mut [u32])>`, the `split_at_mut_checked`
+        // return type: two fat slice pointers `{ptr, len}` back to back. The
+        // None niche lives in the first data pointer; both data pointers must
+        // keep their own `ptr` slot so provenance survives the memory
+        // round-trip, with the two `len` fields as raw byte storage.
+        let mut ctx = make_ctx();
+        let logical = mir_uint(&mut ctx, 64);
+        let len = mir_uint(&mut ctx, 64);
+        let pointee = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
+        let payload: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "SlicePair".into(),
+            vec![
+                "a_ptr".into(),
+                "a_len".into(),
+                "b_ptr".into(),
+                "b_len".into(),
+            ],
+            vec![pointer, len, pointer, len],
+            vec![0, 1, 2, 3],
+            vec![0, 8, 16, 24],
+            32,
+            8,
+        )
+        .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "MaybeSlicePair".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![32]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 32,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let map = build_enum_slot_map(&mut ctx, enum_ty).unwrap();
+        assert_eq!(map.field_slots, vec![None]);
+        let lowered_pointer = convert_type(&mut ctx, pointer).unwrap();
+        // Each slice's length sits in the 8 bytes after its pointer, 8-aligned
+        // inside an 8-aligned enum, so both lower to one `i64`. This is the
+        // `split_at_mut_checked` shape, and the whole point of the widening:
+        // `{ptr, i64, ptr, i64}` moves two lengths as two values, where
+        // `{ptr, [8 x i8], ptr, [8 x i8]}` moved them as sixteen separate bytes.
+        let filler = llvm_int(&mut ctx, 64);
+        assert_eq!(
+            struct_fields(&ctx, map.llvm_struct_ty),
+            vec![lowered_pointer, filler, lowered_pointer, filler]
+        );
+        assert_eq!(
+            llvm_type_size_align(&ctx, map.llvm_struct_ty),
+            Some((32, 8))
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_three_field_tuple_follows_recorded_offsets() {
+        // rustc lays out `(u32, f32, &T)` with the pointer first in memory:
+        // ptr @ 0, u32 @ 8, f32 @ 12, size 16. With those offsets recorded on
+        // the tuple, the pointer leaf coincides exactly with the niche
+        // carrier at byte 0 and the payload is accepted.
+        let mut ctx = make_ctx();
+        let logical = mir_uint(&mut ctx, 64);
+        let word = mir_uint(&mut ctx, 32);
+        let float: TypeHandle = FP32Type::get(&ctx).into();
+        let pointee = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
+        let payload: TypeHandle = MirTupleType::get_with_layout(
+            &mut ctx,
+            vec![word, float, pointer],
+            vec![2, 0, 1],
+            vec![8, 12, 0],
+            16,
+            8,
+        )
+        .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "MaybeMixedTuple".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 16,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let map = build_enum_slot_map(&mut ctx, enum_ty)
+            .expect("recorded tuple offsets prove the pointer word matches the carrier");
+        assert_eq!(map.carrier_slot, Some(0));
+        assert_eq!(
+            llvm_type_size_align(&ctx, map.llvm_struct_ty),
+            Some((16, 8))
+        );
+
+        // The same tuple with offsets that put the u32 over the pointer
+        // carrier (ptr @ 8 instead) must still fail closed: integer bytes
+        // may not alias pointer storage.
+        let mismatched_payload: TypeHandle = MirTupleType::get_with_layout(
+            &mut ctx,
+            vec![word, float, pointer],
+            vec![0, 1, 2],
+            vec![0, 4, 8],
+            16,
+            8,
+        )
+        .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "MaybeMixedTupleShifted".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout(
+                    "Some".into(),
+                    vec![mismatched_payload],
+                    vec![0],
+                    vec![16],
+                ),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 16,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("a non-pointer word over the pointer carrier must fail closed");
+        assert!(error.to_string().contains("pointer provenance"), "{error}");
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_shifted_nested_pointer_carrier() {
+        let mut ctx = make_ctx();
+        let logical = mir_uint(&mut ctx, 64);
+        let index = mir_uint(&mut ctx, 64);
+        let pointee = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
+        let payload: TypeHandle = MirTupleType::get(&mut ctx, vec![index, pointer]).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "ShiftedPointerCarrier".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 16,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("pointer leaves at different offsets must not be conflated");
+        assert!(error.to_string().contains("pointer provenance"), "{error}");
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_nested_carrier_address_space_mismatch() {
+        let mut ctx = make_ctx();
+        let logical = mir_uint(&mut ctx, 64);
+        let index = mir_uint(&mut ctx, 64);
+        let pointee = mir_uint(&mut ctx, 32);
+        let generic_pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
+        let payload: TypeHandle = MirTupleType::get(&mut ctx, vec![generic_pointer, index]).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "MismatchedPointerSpace".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![16]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 16,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                carrier_address_space: llvm_types::address_space::GLOBAL,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("equal byte ranges in different address spaces must not alias");
+        assert!(error.to_string().contains("pointer provenance"), "{error}");
+    }
+
+    #[test]
+    fn enum_slot_map_genericizes_nonoverlapping_shared_pointer_payload() {
+        let mut ctx = make_ctx();
+        let discr = mir_uint(&mut ctx, 32);
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "SharedPointerPayload".into(),
+            discr,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("Unit".into()),
+                EnumVariant::new_with_layout("Ptr".into(), vec![shared], vec![8], vec![8]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 16,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Direct,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 32,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+        let map = build_enum_slot_map(&mut ctx, enum_ty)
+            .expect("a direct shared-pointer payload should use generic physical storage");
+        let field_slot = map.field_slots[0].expect("shared pointer field should own a slot");
+        let stored_ty = map
+            .llvm_struct_ty
+            .deref(&ctx)
+            .downcast_ref::<llvm_types::StructType>()
+            .map(|struct_ty| struct_ty.field_type(field_slot as usize))
+            .expect("field slot must exist");
+        assert_eq!(
+            stored_ty
+                .deref(&ctx)
+                .downcast_ref::<llvm_types::PointerType>()
+                .expect("shared pointer storage must remain a pointer")
+                .address_space(),
+            llvm_types::address_space::GENERIC,
+            "enum storage must use a target-stable generic pointer"
+        );
+        assert_eq!(
+            map.field_llvm_types[0]
+                .deref(&ctx)
+                .downcast_ref::<llvm_types::PointerType>()
+                .expect("semantic field must remain a pointer")
+                .address_space(),
+            llvm_types::address_space::SHARED,
+            "payload operations must retain the semantic shared address space"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_genericizes_nested_shared_pointer_payload() {
+        let mut ctx = make_ctx();
+        let discr = mir_uint(&mut ctx, 32);
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
+        let wrapper: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "SharedPointerWrapper".into(),
+            vec!["pointer".into()],
+            vec![shared],
+            vec![0],
+            vec![0],
+            8,
+            8,
+        )
+        .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "NestedSharedPointerPayload".into(),
+            discr,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("Unit".into()),
+                EnumVariant::new_with_layout("Ptr".into(), vec![wrapper], vec![8], vec![8]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 16,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Direct,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 32,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let map = build_enum_slot_map(&mut ctx, enum_ty)
+            .expect("a struct-nested shared pointer should use generic physical storage");
+        let field_slot = map.field_slots[0].expect("nested payload should own a slot");
+        let stored_ty = map
+            .llvm_struct_ty
+            .deref(&ctx)
+            .downcast_ref::<llvm_types::StructType>()
+            .map(|struct_ty| struct_ty.field_type(field_slot as usize))
+            .expect("field slot must exist");
+        assert!(
+            llvm_type_contains_pointer_in_address_space(
+                &ctx,
+                stored_ty,
+                llvm_types::address_space::GENERIC
+            ),
+            "physical nested payload must contain a generic pointer"
+        );
+        assert!(
+            !llvm_type_contains_pointer_in_address_space(
+                &ctx,
+                stored_ty,
+                llvm_types::address_space::SHARED
+            ),
+            "physical nested payload must not retain the target-dependent AS3 pointer"
+        );
+        assert!(
+            llvm_type_contains_pointer_in_address_space(
+                &ctx,
+                map.field_llvm_types[0],
+                llvm_types::address_space::SHARED
+            ),
+            "semantic payload type must retain shared address-space semantics"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_genericizes_bounded_shared_pointer_array_payload() {
+        let mut ctx = make_ctx();
+        let discr = mir_uint(&mut ctx, 32);
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
+        let pointers: TypeHandle = MirArrayType::get(&mut ctx, shared, 2).into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "SharedPointerArrayPayload".into(),
+            discr,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("Unit".into()),
+                EnumVariant::new_with_layout("Pointers".into(), vec![pointers], vec![8], vec![16]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 24,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Direct,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 32,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let map = build_enum_slot_map(&mut ctx, enum_ty)
+            .expect("a bounded shared-pointer array should use generic physical storage");
+        let field_slot = map.field_slots[0].expect("bounded pointer array should own a slot");
+        let stored_ty = map
+            .llvm_struct_ty
+            .deref(&ctx)
+            .downcast_ref::<llvm_types::StructType>()
+            .map(|struct_ty| struct_ty.field_type(field_slot as usize))
+            .expect("field slot must exist");
+        assert!(
+            llvm_type_contains_pointer_in_address_space(
+                &ctx,
+                stored_ty,
+                llvm_types::address_space::GENERIC
+            ),
+            "physical array payload must contain generic pointers"
+        );
+        assert!(
+            !llvm_type_contains_pointer_in_address_space(
+                &ctx,
+                stored_ty,
+                llvm_types::address_space::SHARED
+            ),
+            "physical array payload must not retain target-dependent AS3 pointers"
+        );
+        assert!(
+            llvm_type_contains_pointer_in_address_space(
+                &ctx,
+                map.field_llvm_types[0],
+                llvm_types::address_space::SHARED
+            ),
+            "semantic array payload must retain shared address-space semantics"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_oversized_shared_pointer_array_payload() {
+        let mut ctx = make_ctx();
+        let discr = mir_uint(&mut ctx, 32);
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
+        let count = MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES + 1;
+        let pointers: TypeHandle = MirArrayType::get(&mut ctx, shared, count).into();
+        let payload_size = count * 8;
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "OversizedSharedPointerArrayPayload".into(),
+            discr,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("Unit".into()),
+                EnumVariant::new_with_layout(
+                    "Pointers".into(),
+                    vec![pointers],
+                    vec![8],
+                    vec![payload_size],
+                ),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 8 + payload_size,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Direct,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 32,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("an oversized shared-pointer array must remain fail-closed");
+        assert!(
+            error
+                .to_string()
+                .contains("arrays containing shared-memory pointers are not supported"),
+            "{error}"
+        );
+        assert!(
+            error.to_string().contains(&format!(
+                "supported bound is {MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES}"
+            )),
+            "{error}"
+        );
+    }
+
+    /// A struct payload holding two shared-pointer arrays whose leaves exceed
+    /// the bound only in total. The slot map is target-mode agnostic (it is
+    /// built once, before the exporter picks the legacy 64-bit or modern
+    /// p3:32 data layout), so this one gate covers both output modes.
+    fn struct_of_shared_pointer_arrays_over_total_bound(ctx: &mut Context) -> TypeHandle {
+        let u32_ty = mir_uint(ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(ctx, u32_ty, false).into();
+        let first: TypeHandle = MirArrayType::get(ctx, shared, 9).into();
+        let second: TypeHandle = MirArrayType::get(ctx, shared, 8).into();
+        MirStructType::get_with_full_layout(
+            ctx,
+            "SharedPointerArrayPair".into(),
+            vec!["first".into(), "second".into()],
+            vec![first, second],
+            vec![],
+            vec![0, 72],
+            136,
+            8,
+        )
+        .into()
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_struct_of_shared_pointer_arrays_over_total_bound() {
+        // Each array alone (9 and 8 leaves) is within the bound; their total
+        // of 17 is not. The payload-root gate must reject the direct layout
+        // with the same bound diagnostic as a single oversized array.
+        let mut ctx = make_ctx();
+        let discr = mir_uint(&mut ctx, 32);
+        let payload = struct_of_shared_pointer_arrays_over_total_bound(&mut ctx);
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "StructOfSharedPointerArraysPayload".into(),
+            discr,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("Unit".into()),
+                EnumVariant::new_with_layout("Pointers".into(), vec![payload], vec![8], vec![136]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 144,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Direct,
+                carrier_kind: EnumCarrierKind::Integer,
+                carrier_width: 32,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("two in-bound arrays exceeding the bound in total must fail closed");
+        assert!(
+            error
+                .to_string()
+                .contains("arrays containing shared-memory pointers are not supported"),
+            "{error}"
+        );
+        assert!(
+            error.to_string().contains(&format!(
+                "rewrite requires 17 pointer conversions, supported bound is {MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES}"
+            )),
+            "{error}"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_struct_of_shared_pointer_arrays_in_niche_layout() {
+        // The same over-bound payload in a niche layout must report the same
+        // bound diagnostic as the direct layout, not a pointer-provenance
+        // error from the overlap walk: the payload-root gate runs first in
+        // both layouts.
+        let mut ctx = make_ctx();
+        let logical = mir_uint(&mut ctx, 64);
+        let payload = struct_of_shared_pointer_arrays_over_total_bound(&mut ctx);
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "NicheStructOfSharedPointerArrays".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout("Some".into(), vec![payload], vec![0], vec![136]),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: 136,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("the payload-root bound must also gate niche layouts");
+        assert!(
+            error.to_string().contains(&format!(
+                "rewrite requires 17 pointer conversions, supported bound is {MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES}"
+            )),
+            "{error}"
+        );
+        assert!(
+            !error.to_string().contains("pointer provenance"),
+            "the bound diagnostic must not be masked by the provenance error: {error}"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_reports_bound_for_oversized_pointer_array_over_niche_carrier() {
+        // Generic pointers pass the shared-pointer storage gate untouched, so
+        // an oversized generic-pointer array reaches the overlap walk. Its
+        // exhausted expansion budget must surface the bound diagnostic, not
+        // the unrelated provenance error.
+        let mut ctx = make_ctx();
+        let logical = mir_uint(&mut ctx, 64);
+        let pointee = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_generic(&mut ctx, pointee, false).into();
+        let count = MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES + 1;
+        let pointers: TypeHandle = MirArrayType::get(&mut ctx, pointer, count).into();
+        let payload_size = count * 8;
+        let enum_ty: TypeHandle = MirEnumType::get_with_encoding(
+            &mut ctx,
+            "NicheOversizedGenericPointerArray".into(),
+            logical,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new_with_layout(
+                    "Some".into(),
+                    vec![pointers],
+                    vec![0],
+                    vec![payload_size],
+                ),
+            ],
+            EnumEncoding {
+                tag_offset: 0,
+                total_size: payload_size,
+                abi_align: 8,
+                layout_kind: EnumLayoutKind::Niche,
+                carrier_kind: EnumCarrierKind::Pointer,
+                carrier_width: 64,
+                untagged_variant: 1,
+                variant_inhabited: vec![1, 1],
+                ..EnumEncoding::default()
+            },
+        )
+        .into();
+
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("an oversized pointer-array expansion over a niche carrier must fail closed");
+        assert!(
+            error.to_string().contains(&format!(
+                "rewrite requires {count} pointer conversions, supported bound is {MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES}"
+            )),
+            "{error}"
+        );
+        assert!(
+            !error.to_string().contains("pointer provenance"),
+            "the bound diagnostic must not be masked by the provenance error: {error}"
+        );
+    }
+
+    #[test]
+    fn enum_slot_map_rejects_shared_pointer_vector_payload() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 32);
+        let shared_pointer: TypeHandle =
+            llvm_types::PointerType::get(&ctx, llvm_types::address_space::SHARED).into();
+        let shared_vector: TypeHandle =
+            llvm_types::VectorType::get(&ctx, shared_pointer, 2, llvm_types::VectorTypeKind::Fixed)
+                .into();
+        let enum_ty: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "SharedPointerVector".into(),
+            tag,
+            vec![0, 1],
+            vec![
+                EnumVariant::new_with_layout(
+                    "Data".into(),
+                    vec![shared_vector],
+                    vec![16],
+                    vec![16],
+                ),
+                EnumVariant::unit("Empty".into()),
+            ],
+            0,
+            32,
+            16,
+        )
+        .into();
+
+        let error = build_enum_slot_map(&mut ctx, enum_ty)
+            .err()
+            .expect("a vector of shared pointers must fail closed");
+        assert!(
+            error.to_string().contains("shared-memory pointer"),
+            "{error}"
+        );
+    }
+}
diff --git a/crates/mir-lower/src/convert/types/func_abi.rs b/crates/mir-lower/src/convert/types/func_abi.rs
new file mode 100644
index 0000000000..a5f61c909c
--- /dev/null
+++ b/crates/mir-lower/src/convert/types/func_abi.rs
@@ -0,0 +1,1069 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Kernel-boundary detection, transparent-scalar ABI, and function-type
+//! conversion (the boundary ABI: slice flattening, struct flattening,
+//! packed shared-pointer rewrites).
+
+use dialect_mir::types::{
+    MirArrayType, MirDisjointSliceType, MirFP16Type, MirPtrType, MirSliceType, MirStructType,
+    MirTupleType,
+};
+use llvm_export::types as llvm_types;
+use llvm_export::types::PointerTypeExt;
+use pliron::builtin::type_interfaces::FunctionTypeInterface;
+use pliron::builtin::types::{FP32Type, FP64Type, FunctionType, IntegerType, Signedness};
+use pliron::context::{Context, Ptr};
+use pliron::operation::Operation;
+use pliron::r#type::{TypeHandle, type_cast};
+
+use super::{
+    StructLayoutInfo, build_struct_slot_map, convert_type, is_zero_sized_type,
+    llvm_packed_struct_contains_pointer_in_address_space, llvm_type_size_align,
+};
+use crate::convert::target_stable_storage::{StorageRewriteOptions, target_stable_storage_type};
+
+// =============================================================================
+// Kernel-Boundary Detection
+// =============================================================================
+
+/// Identifier of the attribute that marks a `MirFuncOp` / `llvm.func` as a
+/// GPU kernel entry point.
+///
+/// Kept as a function (rather than a `const`) because pliron `Identifier`
+/// construction needs the `try_into()` fallible path.
+fn gpu_kernel_attr() -> pliron::identifier::Identifier {
+    "gpu_kernel".try_into().expect("static identifier")
+}
+
+/// Returns `true` when `op` carries the `gpu_kernel` attribute.
+///
+/// The kernel-entry ABI differs from internal device-function ABI: at
+/// kernel boundaries, aggregate parameters (structs, closures) are passed
+/// as a single byval value to match what the host pushes via
+/// `cuLaunchKernel`. Internal call sites still flatten aggregates the
+/// same way they always did. This helper is the single source of truth
+/// for that branch and is consumed by both [`convert_function_type`] and
+/// the entry-block prologue in `lowering.rs`.
+pub fn is_kernel_func(ctx: &Context, op: Ptr<Operation>) -> bool {
+    op.deref(ctx)
+        .attributes
+        .get::<pliron::builtin::attributes::StringAttr>(&gpu_kernel_attr())
+        .is_some()
+}
+
+/// Return the declaration index and type of the single non-ZST field of a
+/// rustc-proven transparent scalar struct.
+///
+/// The importer marks the outer ABI from rustc rather than inferring it from
+/// source field count. We still validate the MIR shape here so malformed or
+/// hand-written dialect input cannot turn an arbitrary aggregate into a scalar
+/// ABI value.
+fn transparent_scalar_field_with_index(
+    ctx: &mut Context,
+    struct_ty: TypeHandle,
+) -> Result<(usize, TypeHandle), anyhow::Error> {
+    let (name, field_types, mem_to_decl, is_transparent_scalar) = {
+        let ty_ref = struct_ty.deref(ctx);
+        let s = ty_ref
+            .downcast_ref::<MirStructType>()
+            .ok_or_else(|| anyhow::anyhow!("transparent scalar ABI requires a MirStructType"))?;
+        (
+            s.name.clone(),
+            s.field_types.clone(),
+            s.memory_order(),
+            s.is_transparent_scalar(),
+        )
+    };
+
+    if !is_transparent_scalar {
+        return Err(anyhow::anyhow!(
+            "struct `{}` is not marked as a transparent scalar",
+            name
+        ));
+    }
+
+    let mut scalar_field = None;
+    for decl_idx in mem_to_decl {
+        let field_ty = field_types[decl_idx];
+        let converted = convert_type(ctx, field_ty)?;
+        if is_zero_sized_type(ctx, converted) {
+            continue;
+        }
+        if scalar_field.replace((decl_idx, field_ty)).is_some() {
+            return Err(anyhow::anyhow!(
+                "transparent scalar struct `{}` has more than one non-ZST field",
+                name
+            ));
+        }
+    }
+
+    scalar_field
+        .ok_or_else(|| anyhow::anyhow!("transparent scalar struct `{}` has no non-ZST field", name))
+}
+
+/// Return the single non-ZST field of a rustc-proven transparent scalar struct.
+pub(crate) fn transparent_scalar_field(
+    ctx: &mut Context,
+    struct_ty: TypeHandle,
+) -> Result<TypeHandle, anyhow::Error> {
+    Ok(transparent_scalar_field_with_index(ctx, struct_ty)?.1)
+}
+
+/// One aggregate layer traversed when a transparent scalar wrapper crosses an
+/// ABI boundary. `field_slot` is the LLVM struct slot containing the next
+/// nested wrapper or the final scalar.
+#[derive(Clone, Copy, Debug)]
+pub(crate) struct TransparentScalarLayer {
+    pub llvm_struct_ty: TypeHandle,
+    pub field_slot: u32,
+}
+
+/// Complete ABI projection for a rustc-proven transparent scalar wrapper.
+///
+/// `layers` are ordered outermost to innermost. A return lowers by extracting
+/// those slots in order; a call result is rebuilt by inserting the scalar into
+/// the same layers in reverse order.
+#[derive(Clone, Debug)]
+pub(crate) struct TransparentScalarAbiInfo {
+    pub scalar_ty: TypeHandle,
+    pub layers: Vec<TransparentScalarLayer>,
+}
+
+/// Build the scalar ABI projection, including the exact LLVM slot used at every
+/// wrapper layer.
+///
+/// Slot indices come from [`build_struct_slot_map`], so ZST markers, explicit
+/// padding, and rustc memory order cannot make the return/call paths disagree
+/// with ordinary aggregate conversion.
+pub(crate) fn transparent_scalar_abi_info(
+    ctx: &mut Context,
+    struct_ty: TypeHandle,
+) -> Result<TransparentScalarAbiInfo, anyhow::Error> {
+    let mut current = struct_ty;
+    let mut layers = Vec::new();
+
+    loop {
+        let (decl_idx, field_ty) = transparent_scalar_field_with_index(ctx, current)?;
+        let layout = {
+            let ty_ref = current.deref(ctx);
+            let s = ty_ref.downcast_ref::<MirStructType>().ok_or_else(|| {
+                anyhow::anyhow!("transparent scalar ABI requires a MirStructType")
+            })?;
+            StructLayoutInfo::of_struct(s)
+        };
+        let map = build_struct_slot_map(ctx, &layout)?;
+        let field_slot = map.decl_to_llvm[decl_idx].ok_or_else(|| {
+            anyhow::anyhow!(
+                "transparent scalar field {} unexpectedly lowered as a ZST",
+                decl_idx
+            )
+        })?;
+        layers.push(TransparentScalarLayer {
+            llvm_struct_ty: map.llvm_struct_ty,
+            field_slot,
+        });
+
+        let nested_transparent = {
+            let field_ref = field_ty.deref(ctx);
+            field_ref
+                .downcast_ref::<MirStructType>()
+                .is_some_and(MirStructType::is_transparent_scalar)
+        };
+        if nested_transparent {
+            current = field_ty;
+            continue;
+        }
+
+        let scalar_ty = convert_type(ctx, field_ty)?;
+        if is_zero_sized_type(ctx, scalar_ty) {
+            return Err(anyhow::anyhow!(
+                "transparent scalar ABI resolved to a zero-sized field"
+            ));
+        }
+        return Ok(TransparentScalarAbiInfo { scalar_ty, layers });
+    }
+}
+
+/// LLVM ABI type for a rustc-proven transparent scalar struct.
+///
+/// Transparent wrappers can nest (`Outer(Inner(u32))`). rustc still reports
+/// the outer ADT as one scalar, so recurse through transparent scalar fields
+/// until reaching the actual scalar/pointer representation.
+pub(crate) fn transparent_scalar_llvm_type(
+    ctx: &mut Context,
+    struct_ty: TypeHandle,
+) -> Result<TypeHandle, anyhow::Error> {
+    Ok(transparent_scalar_abi_info(ctx, struct_ty)?.scalar_ty)
+}
+
+/// Target-stable ABI projection for packed aggregates containing AS3 leaves
+/// across the internal device return boundary.
+///
+/// The function body continues to use the semantic packed LLVM struct with
+/// shared pointers. Only the physical return value recursively replaces AS3
+/// leaves with generic pointers, whose width is stable across the legacy/PTX
+/// and modern NVVM data layouts.
+#[derive(Clone, Copy, Debug)]
+pub(crate) struct PackedSharedInternalAbiInfo {
+    pub semantic_ty: TypeHandle,
+    pub storage_ty: TypeHandle,
+}
+
+/// Maximum number of shared-pointer leaves introduced by fixed-array expansion
+/// in one packed-AS3 internal return carrier.
+///
+/// Struct/tuple nesting and direct pointer leaves remain proportional to source
+/// structure. Arrays can encode an arbitrarily large number of per-element
+/// extract/cast/insert sequences compactly, so only array-expanded AS3 leaves
+/// count against this code-shape budget.
+pub(crate) const MAX_PACKED_SHARED_INTERNAL_ABI_ARRAY_REWRITE_LEAVES: u64 = 16;
+
+/// Whether a MIR type converts to a zero-sized LLVM type.
+///
+/// MIR-side mirror of [`is_zero_sized_type`]: zero-length arrays, arrays of
+/// zero-sized elements, and structs/tuples whose fields are all zero-sized
+/// (including empty ones such as `PhantomData`) vanish at the LLVM level and
+/// must not affect ABI-lane classification.
+fn mir_type_is_zero_sized(ctx: &Context, ty: TypeHandle) -> bool {
+    let ty_ref = ty.deref(ctx);
+    if let Some(array_ty) = ty_ref.downcast_ref::<MirArrayType>() {
+        return array_ty.size() == 0 || mir_type_is_zero_sized(ctx, array_ty.element_type());
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
+        return struct_ty
+            .field_types
+            .iter()
+            .all(|field| mir_type_is_zero_sized(ctx, *field));
+    }
+    if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
+        return tuple_ty
+            .get_types()
+            .iter()
+            .all(|field| mir_type_is_zero_sized(ctx, *field));
+    }
+    false
+}
+
+/// Whether a MIR value shape belongs to the recursive packed-AS3 ABI lane.
+///
+/// Structs, tuples, and fixed arrays may nest recursively and may contain any
+/// number of scalar pointer leaves. Zero-sized fields are skipped, matching the
+/// post-conversion field scan this predicate replaced. The array-specific
+/// expansion budget is enforced after conversion from the storage rewrite's
+/// exact AS3 leaf count. Vectors and unrelated aggregate kinds remain
+/// deliberately fail-closed.
+fn packed_shared_internal_abi_mir_shape_is_supported(ctx: &Context, mir_ty: TypeHandle) -> bool {
+    let children = {
+        let ty_ref = mir_ty.deref(ctx);
+        if ty_ref.is::<IntegerType>()
+            || ty_ref.is::<MirFP16Type>()
+            || ty_ref.is::<llvm_types::HalfType>()
+            || ty_ref.is::<FP32Type>()
+            || ty_ref.is::<FP64Type>()
+            || ty_ref.is::<MirPtrType>()
+            || ty_ref.is::<llvm_types::PointerType>()
+        {
+            return true;
+        }
+        if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
+            Some(struct_ty.field_types.clone())
+        } else if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
+            Some(tuple_ty.get_types().to_vec())
+        } else {
+            ty_ref
+                .downcast_ref::<MirArrayType>()
+                .map(|array_ty| vec![array_ty.element_type()])
+        }
+    };
+
+    children.is_some_and(|children| {
+        children.into_iter().all(|child| {
+            mir_type_is_zero_sized(ctx, child)
+                || packed_shared_internal_abi_mir_shape_is_supported(ctx, child)
+        })
+    })
+}
+
+/// Recognize a recursive packed-AS3 internal ABI shape.
+///
+/// The root must remain a byte-faithful packed struct. Nested structs/tuples,
+/// multiple AS3 leaves, and bounded fixed arrays are admitted. Vectors and
+/// unrelated aggregate kinds remain out of scope. The target-stable storage
+/// utility owns the recursive AS3 -> generic rewrite and this classifier only
+/// decides which semantic shapes may use it.
+pub(crate) fn packed_shared_internal_abi_info(
+    ctx: &mut Context,
+    mir_ty: TypeHandle,
+) -> Result<Option<PackedSharedInternalAbiInfo>, anyhow::Error> {
+    let layout = {
+        let ty_ref = mir_ty.deref(ctx);
+        let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() else {
+            return Ok(None);
+        };
+        StructLayoutInfo::of_struct(struct_ty)
+    };
+
+    if !packed_shared_internal_abi_mir_shape_is_supported(ctx, mir_ty) {
+        return Ok(None);
+    }
+
+    let map = build_struct_slot_map(ctx, &layout)?;
+    if !map.by_value_layout_faithful {
+        return Ok(None);
+    }
+    let is_packed = map
+        .llvm_struct_ty
+        .deref(ctx)
+        .downcast_ref::<llvm_types::StructType>()
+        .is_some_and(|struct_ty| struct_ty.layout() == llvm_types::StructLayout::Packed);
+    if !is_packed {
+        return Ok(None);
+    }
+
+    let rewrite = target_stable_storage_type(
+        ctx,
+        map.llvm_struct_ty,
+        StorageRewriteOptions {
+            canonicalize_bool: false,
+        },
+        "packed shared internal ABI",
+    )?;
+    if rewrite.shared_pointer_leaves == 0
+        || rewrite.array_shared_pointer_leaves > MAX_PACKED_SHARED_INTERNAL_ABI_ARRAY_REWRITE_LEAVES
+    {
+        return Ok(None);
+    }
+    let Some((storage_size, _)) = llvm_type_size_align(ctx, rewrite.ty) else {
+        return Ok(None);
+    };
+    if layout.total_size > 0 && storage_size != layout.total_size {
+        return Ok(None);
+    }
+
+    Ok(Some(PackedSharedInternalAbiInfo {
+        semantic_ty: map.llvm_struct_ty,
+        storage_ty: rewrite.ty,
+    }))
+}
+
+/// Convert a type that crosses a function boundary as one LLVM value.
+///
+/// A struct with a natural-layout divergence is legal by value only when
+/// [`build_struct_slot_map`] proved that a sequential packed LLVM struct
+/// reproduces rustc's offsets and size. This keeps overlapping/union-like
+/// legacy struct models fail-closed while allowing real `repr(packed)` values.
+/// Packed values containing shared-memory pointers remain target-dependent
+/// because AS3 pointer width differs between modern NVVM and PTX/legacy modes.
+fn convert_by_value_abi_type(
+    ctx: &mut Context,
+    mir_ty: TypeHandle,
+    role: &str,
+) -> Result<TypeHandle, anyhow::Error> {
+    let layout = {
+        let ty_ref = mir_ty.deref(ctx);
+        ty_ref
+            .downcast_ref::<MirStructType>()
+            .map(StructLayoutInfo::of_struct)
+    };
+    let llvm_ty = if let Some(layout) = layout {
+        let map = build_struct_slot_map(ctx, &layout)?;
+        if !map.by_value_layout_faithful {
+            return Err(anyhow::anyhow!(
+                "{} has a rustc struct layout that cannot be represented by an LLVM struct value",
+                role
+            ));
+        }
+        map.llvm_struct_ty
+    } else {
+        convert_type(ctx, mir_ty)?
+    };
+
+    if llvm_packed_struct_contains_pointer_in_address_space(
+        ctx,
+        llvm_ty,
+        llvm_types::address_space::SHARED,
+    ) {
+        return Err(anyhow::anyhow!(
+            "{} contains a packed aggregate with a target-dependent shared-memory pointer",
+            role
+        ));
+    }
+
+    Ok(llvm_ty)
+}
+
+/// Convert a MIR function type to an LLVM function type.
+///
+/// This handles the ABI-level transformations required for GPU kernels.
+/// The transformations ensure that the generated LLVM IR matches the
+/// C ABI expected by the CUDA runtime.
+///
+/// # ABI Transformations
+///
+/// ## Argument Flattening
+///
+/// Aggregate types are flattened to primitive types:
+///
+/// ```text
+/// MIR:  fn kernel(slice: &[f32], point: Point)
+/// LLVM: fn internal_fn(ptr: !ptr, len: i64, x: f32, y: f32)
+/// ```
+///
+/// | MIR Argument            | Internal call ABI       | Kernel-entry ABI       |
+/// |-------------------------|-------------------------|------------------------|
+/// | `&[T]`                  | `(ptr, i64)`            | `(ptr, i64)`           |
+/// | `DisjointSlice<T>`      | `(ptr, i64)`            | `(ptr, i64)`           |
+/// | `struct { a: A, b: B }` | `(a: A', b: B')`        | one byval `{A', B'}`   |
+/// | `repr(transparent)` scalar ADT | underlying scalar      | underlying scalar      |
+/// | closure with N captures | N separate field args   | one byval struct       |
+/// | Other                   | Converted type          | Converted type         |
+///
+/// Slices keep their `(ptr, len)` flattening on both sides because the
+/// host-side launch helpers push the pointer and length as two driver
+/// args. Structs and closures are unflattened only at kernel boundaries
+/// because the host pushes them as a single scalar — see
+/// `cuda_host::push_kernel_scalar`. The exception is a rustc-proven
+/// `#[repr(transparent)]` `ValueAbi::Scalar` struct: its single non-ZST
+/// field is the kernel parameter, matching the source type's transparent ABI.
+/// Internal device-side call sites stay flattened: caller and callee are both
+/// inside this backend, so the ABI is private and there is no host to disagree
+/// with.
+///
+/// ## Return Type Handling
+///
+/// - Empty tuple `()` becomes `void`
+/// - Empty struct `struct {}` becomes `void`
+/// - Rustc-proven `repr(transparent)` scalar ADTs return the underlying scalar
+/// - Other types are converted normally
+///
+/// # Arguments
+///
+/// * `ctx` - The pliron context
+/// * `func_type` - The MIR function type to convert
+/// * `is_kernel_entry` - When `true`, treat aggregate (non-slice) params
+///   as single byval values to match the host-side push ABI. When `false`,
+///   keep the existing internal device-fn ABI that flattens struct fields
+///   into individual scalars.
+///
+/// # Returns
+///
+/// The equivalent LLVM function type with ABI transformations applied.
+///
+/// # Example
+///
+/// ```text
+/// MIR:  fn foo(a: &[f32], b: i32) -> f32
+/// LLVM: fn foo(ptr, i64, i32) -> f32
+///
+/// MIR:  fn bar() -> ()
+/// LLVM: fn bar() -> void
+/// ```
+///
+/// # Note
+///
+/// At internal device-function boundaries the struct flattening must be
+/// reversed in the entry block. At kernel-entry boundaries ordinary structs
+/// arrive as one byval aggregate, while rustc-proven transparent scalar
+/// wrappers arrive as their single non-ZST scalar field and must be rebuilt.
+/// See `lowering.rs::build_entry_prologue` for the reconstruction paths.
+pub fn convert_function_type(
+    ctx: &mut Context,
+    func_type: pliron::r#type::TypedHandle<FunctionType>,
+    is_kernel_entry: bool,
+) -> Result<pliron::r#type::TypedHandle<llvm_types::FuncType>, anyhow::Error> {
+    // Extract input/output types before mutating context
+    let (inputs_ptr, results_ptr) = {
+        let func_ty_ref = func_type.deref(ctx);
+        let interface = type_cast::<dyn FunctionTypeInterface>(&*func_ty_ref)
+            .ok_or_else(|| anyhow::anyhow!("Type does not implement FunctionTypeInterface"))?;
+        (interface.arg_types(), interface.res_types())
+    };
+
+    // Convert inputs, flattening slice/struct types for ABI compatibility.
+    // Slices flatten on both ABIs; structs flatten only on the internal
+    // device-fn ABI.
+    let mut inputs = Vec::new();
+    let inputs_vec: Vec<_> = inputs_ptr.to_vec();
+
+    for t in inputs_vec {
+        // Determine what kind of flattening this type needs
+        // Extract all info first, then drop the borrow
+        enum FlattenKind {
+            /// `{ ptr, len }`, then one parameter per index-space layout field.
+            Slice {
+                space_tys: Vec<TypeHandle>,
+            },
+            Struct {
+                field_types: Vec<TypeHandle>,
+                mem_to_decl: Vec<usize>,
+            },
+            TransparentScalar(TypeHandle),
+            None,
+        }
+
+        let flatten_kind = {
+            let ty_ref = t.deref(ctx);
+            if ty_ref.is::<MirSliceType>() {
+                FlattenKind::Slice {
+                    space_tys: Vec::new(),
+                }
+            } else if let Some(slice_ty) = ty_ref.downcast_ref::<MirDisjointSliceType>() {
+                FlattenKind::Slice {
+                    space_tys: slice_ty.space_tys.clone(),
+                }
+            } else if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
+                if is_kernel_entry && struct_ty.is_transparent_scalar() {
+                    // rustc proves that this `repr(transparent)` ADT has a
+                    // scalar ABI. Emit exactly its one non-ZST field as the
+                    // kernel parameter instead of an aggregate `.b8[]` param.
+                    FlattenKind::TransparentScalar(t)
+                } else if is_kernel_entry {
+                    // Ordinary kernel-boundary structs remain intact so the
+                    // host's single `push_kernel_scalar(&closure)` push
+                    // matches a single aggregate .param entry.
+                    FlattenKind::None
+                } else {
+                    FlattenKind::Struct {
+                        field_types: struct_ty.field_types.clone(),
+                        mem_to_decl: struct_ty.memory_order(),
+                    }
+                }
+            } else {
+                FlattenKind::None
+            }
+        };
+
+        match flatten_kind {
+            FlattenKind::Slice { space_tys } => {
+                let ptr_ty = llvm_types::PointerType::get_generic(ctx);
+                let len_ty = IntegerType::get(ctx, 64, Signedness::Signless);
+                inputs.push(ptr_ty.into());
+                inputs.push(len_ty.into());
+                for space_ty in space_tys {
+                    let converted = convert_type(ctx, space_ty)?;
+                    // A zero-sized index-space field contributes no parameter,
+                    // as NVPTX has no empty `.param`.
+                    if !is_zero_sized_type(ctx, converted) {
+                        inputs.push(converted);
+                    }
+                }
+            }
+            FlattenKind::Struct {
+                field_types,
+                mem_to_decl,
+            } => {
+                // Flatten in MEMORY ORDER to match struct layout
+                for mem_idx in 0..field_types.len() {
+                    let decl_idx = mem_to_decl[mem_idx];
+                    let converted = convert_by_value_abi_type(
+                        ctx,
+                        field_types[decl_idx],
+                        "by-value function argument",
+                    )?;
+                    // Skip ZST fields - NVPTX can't handle empty params
+                    if !is_zero_sized_type(ctx, converted) {
+                        inputs.push(converted);
+                    }
+                }
+            }
+            FlattenKind::TransparentScalar(struct_ty) => {
+                inputs.push(transparent_scalar_llvm_type(ctx, struct_ty)?);
+            }
+            FlattenKind::None => {
+                let converted = convert_by_value_abi_type(ctx, t, "by-value function argument")?;
+                // Skip ZST args - NVPTX can't handle empty params
+                if !is_zero_sized_type(ctx, converted) {
+                    inputs.push(converted);
+                }
+            }
+        }
+    }
+
+    // Convert return type. A rustc-proven transparent scalar wrapper uses
+    // the underlying scalar at the function ABI boundary, while its body
+    // continues to use the ordinary converted aggregate representation.
+    let ret_ty = if results_ptr.is_empty() {
+        llvm_types::VoidType::get(ctx).into()
+    } else {
+        let mir_ret_ty = results_ptr[0];
+        let is_transparent_scalar = {
+            let ty_ref = mir_ret_ty.deref(ctx);
+            ty_ref
+                .downcast_ref::<MirStructType>()
+                .is_some_and(MirStructType::is_transparent_scalar)
+        };
+        let ty = if is_transparent_scalar {
+            transparent_scalar_llvm_type(ctx, mir_ret_ty)?
+        } else if !is_kernel_entry {
+            match packed_shared_internal_abi_info(ctx, mir_ret_ty)? {
+                Some(abi) => abi.storage_ty,
+                None => convert_by_value_abi_type(ctx, mir_ret_ty, "by-value function return")?,
+            }
+        } else {
+            convert_by_value_abi_type(ctx, mir_ret_ty, "by-value function return")?
+        };
+        // Check if zero-sized (empty struct or struct with only ZST fields).
+        if is_zero_sized_type(ctx, ty) {
+            llvm_types::VoidType::get(ctx).into()
+        } else {
+            ty
+        }
+    };
+
+    Ok(llvm_types::FuncType::get(ctx, ret_ty, inputs, false))
+}
+
+#[cfg(test)]
+mod tests {
+    use super::super::llvm_type_contains_pointer_in_address_space;
+    use super::super::test_support::{make_ctx, mir_uint, struct_fields, transparent_u32};
+    use super::*;
+    use dialect_mir::types::StructAbiKind;
+
+    #[test]
+    fn transparent_scalar_return_type_uses_underlying_scalar() {
+        let mut ctx = make_ctx();
+        let wrapper = transparent_u32(&mut ctx, "Scalar");
+        let func_ty = FunctionType::get(&ctx, vec![], vec![wrapper]);
+
+        let lowered = convert_function_type(&mut ctx, func_ty, false).unwrap();
+        let result_ty = lowered.deref(&ctx).result_type();
+        let result_ty_ref = result_ty.deref(&ctx);
+        let integer = result_ty_ref
+            .downcast_ref::<IntegerType>()
+            .expect("transparent u32 return must lower to an integer");
+        assert_eq!(integer.width(), 32);
+    }
+
+    #[test]
+    fn nested_transparent_scalar_abi_records_each_rebuild_layer() {
+        let mut ctx = make_ctx();
+        let inner = transparent_u32(&mut ctx, "Inner");
+        let outer: TypeHandle = MirStructType::get_with_full_layout_and_abi(
+            &mut ctx,
+            "Outer".into(),
+            vec!["inner".into()],
+            vec![inner],
+            vec![0],
+            vec![0],
+            4,
+            4,
+            StructAbiKind::TransparentScalar,
+        )
+        .into();
+
+        let info = transparent_scalar_abi_info(&mut ctx, outer).unwrap();
+        let scalar_ty_ref = info.scalar_ty.deref(&ctx);
+        let integer = scalar_ty_ref
+            .downcast_ref::<IntegerType>()
+            .expect("nested transparent wrapper must resolve to u32");
+        assert_eq!(integer.width(), 32);
+        assert_eq!(info.layers.len(), 2);
+        assert_eq!(info.layers[0].field_slot, 0);
+        assert_eq!(info.layers[1].field_slot, 0);
+    }
+
+    #[test]
+    fn ordinary_one_field_return_remains_aggregate() {
+        let mut ctx = make_ctx();
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let ordinary: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Ordinary".into(),
+            vec!["value".into()],
+            vec![u32_ty],
+            vec![0],
+            vec![0],
+            4,
+            4,
+        )
+        .into();
+        let func_ty = FunctionType::get(&ctx, vec![], vec![ordinary]);
+
+        let lowered = convert_function_type(&mut ctx, func_ty, false).unwrap();
+        assert!(
+            lowered
+                .deref(&ctx)
+                .result_type()
+                .deref(&ctx)
+                .is::<llvm_types::StructType>(),
+            "ordinary one-field structs must not be scalarized"
+        );
+    }
+
+    #[test]
+    fn packed_shared_pointer_predicate_ignores_unpacked_direct_pointer() {
+        let ctx = make_ctx();
+        let shared: TypeHandle =
+            llvm_types::PointerType::get(&ctx, llvm_types::address_space::SHARED).into();
+        let unpacked: TypeHandle = llvm_types::StructType::get_unnamed(
+            &ctx,
+            (vec![shared], llvm_types::StructLayout::Unpacked),
+        )
+        .into();
+        assert!(
+            !llvm_packed_struct_contains_pointer_in_address_space(
+                &ctx,
+                unpacked,
+                llvm_types::address_space::SHARED,
+            ),
+            "a direct AS3 pointer in an unpacked aggregate is not a packed physical-image hazard"
+        );
+
+        let packed: TypeHandle = llvm_types::StructType::get_unnamed(
+            &ctx,
+            (vec![shared], llvm_types::StructLayout::Packed),
+        )
+        .into();
+        assert!(
+            llvm_packed_struct_contains_pointer_in_address_space(
+                &ctx,
+                packed,
+                llvm_types::address_space::SHARED,
+            ),
+            "an AS3 pointer under a packed struct must be rejected by by-value paths"
+        );
+    }
+
+    #[test]
+    fn packed_shared_internal_abi_genericizes_one_direct_shared_pointer() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 8);
+        let pointee = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let packed: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedShared".into(),
+            vec!["tag".into(), "ptr".into()],
+            vec![tag, shared],
+            vec![0, 1],
+            vec![0, 1],
+            9,
+            1,
+        )
+        .into();
+
+        let abi = packed_shared_internal_abi_info(&mut ctx, packed)
+            .expect("ABI classification must succeed")
+            .expect("one direct packed AS3 pointer must use the internal carrier");
+        assert_eq!(llvm_type_size_align(&ctx, abi.semantic_ty), Some((9, 1)));
+        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((9, 1)));
+        assert!(llvm_packed_struct_contains_pointer_in_address_space(
+            &ctx,
+            abi.semantic_ty,
+            llvm_types::address_space::SHARED,
+        ));
+        assert!(!llvm_type_contains_pointer_in_address_space(
+            &ctx,
+            abi.storage_ty,
+            llvm_types::address_space::SHARED,
+        ));
+        assert!(llvm_type_contains_pointer_in_address_space(
+            &ctx,
+            abi.storage_ty,
+            llvm_types::address_space::GENERIC,
+        ));
+    }
+
+    #[test]
+    fn packed_shared_internal_abi_genericizes_multiple_direct_shared_pointers() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 8);
+        let pointee = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let packed: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedSharedPair".into(),
+            vec!["tag".into(), "left".into(), "right".into()],
+            vec![tag, shared, shared],
+            vec![0, 1, 2],
+            vec![0, 1, 9],
+            17,
+            1,
+        )
+        .into();
+
+        let abi = packed_shared_internal_abi_info(&mut ctx, packed)
+            .expect("ABI classification must succeed")
+            .expect("multiple direct AS3 leaves must use the recursive internal carrier");
+        assert_eq!(llvm_type_size_align(&ctx, abi.semantic_ty), Some((17, 1)));
+        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((17, 1)));
+        assert!(llvm_packed_struct_contains_pointer_in_address_space(
+            &ctx,
+            abi.semantic_ty,
+            llvm_types::address_space::SHARED,
+        ));
+        assert!(!llvm_type_contains_pointer_in_address_space(
+            &ctx,
+            abi.storage_ty,
+            llvm_types::address_space::SHARED,
+        ));
+
+        let fields = struct_fields(&ctx, abi.storage_ty);
+        assert_eq!(fields.len(), 3);
+        for field in &fields[1..] {
+            let field_ref = field.deref(&ctx);
+            let pointer = field_ref
+                .downcast_ref::<llvm_types::PointerType>()
+                .expect("both pointer leaves must remain pointer-typed");
+            assert_eq!(pointer.address_space(), llvm_types::address_space::GENERIC);
+        }
+    }
+
+    #[test]
+    fn packed_shared_internal_abi_genericizes_nested_struct_shared_pointers() {
+        let mut ctx = make_ctx();
+        let pointee = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let inner: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "InnerSharedPair".into(),
+            vec!["left".into(), "right".into()],
+            vec![shared, shared],
+            vec![0, 1],
+            vec![0, 8],
+            16,
+            8,
+        )
+        .into();
+        let tag = mir_uint(&mut ctx, 8);
+        let outer: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedNestedShared".into(),
+            vec!["tag".into(), "inner".into()],
+            vec![tag, inner],
+            vec![0, 1],
+            vec![0, 1],
+            17,
+            1,
+        )
+        .into();
+
+        let abi = packed_shared_internal_abi_info(&mut ctx, outer)
+            .expect("classification must not error")
+            .expect("nested AS3 leaves must use the recursive internal carrier");
+        assert_eq!(llvm_type_size_align(&ctx, abi.semantic_ty), Some((17, 1)));
+        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((17, 1)));
+        assert!(!llvm_type_contains_pointer_in_address_space(
+            &ctx,
+            abi.storage_ty,
+            llvm_types::address_space::SHARED,
+        ));
+
+        let outer_fields = struct_fields(&ctx, abi.storage_ty);
+        let inner_fields = struct_fields(&ctx, outer_fields[1]);
+        assert_eq!(inner_fields.len(), 2);
+        for field in inner_fields {
+            let field_ref = field.deref(&ctx);
+            let pointer = field_ref
+                .downcast_ref::<llvm_types::PointerType>()
+                .expect("nested shared leaves must remain pointer-typed");
+            assert_eq!(pointer.address_space(), llvm_types::address_space::GENERIC);
+        }
+    }
+
+    #[test]
+    fn packed_shared_internal_abi_genericizes_nested_tuple_shared_pointer() {
+        let mut ctx = make_ctx();
+        let pointee = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let word = mir_uint(&mut ctx, 32);
+        let inner: TypeHandle = MirTupleType::get_with_layout(
+            &mut ctx,
+            vec![shared, word],
+            vec![0, 1],
+            vec![0, 8],
+            16,
+            8,
+        )
+        .into();
+        let tag = mir_uint(&mut ctx, 8);
+        let outer: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedNestedTupleShared".into(),
+            vec!["tag".into(), "inner".into()],
+            vec![tag, inner],
+            vec![0, 1],
+            vec![0, 1],
+            17,
+            1,
+        )
+        .into();
+
+        let abi = packed_shared_internal_abi_info(&mut ctx, outer)
+            .expect("classification must not error")
+            .expect("an AS3 leaf nested in a tuple must use the recursive carrier");
+        let outer_fields = struct_fields(&ctx, abi.storage_ty);
+        let inner_fields = struct_fields(&ctx, outer_fields[1]);
+        let inner_field_ref = inner_fields[0].deref(&ctx);
+        let pointer = inner_field_ref
+            .downcast_ref::<llvm_types::PointerType>()
+            .expect("nested tuple leaf must remain pointer-typed");
+        assert_eq!(pointer.address_space(), llvm_types::address_space::GENERIC);
+        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((17, 1)));
+    }
+
+    #[test]
+    fn packed_shared_internal_abi_skips_zero_sized_fields() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 8);
+        let byte = mir_uint(&mut ctx, 8);
+        let marker: TypeHandle = MirArrayType::get(&mut ctx, byte, 0).into();
+        let pointee = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let packed: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedSharedZstMarker".into(),
+            vec!["tag".into(), "marker".into(), "ptr".into()],
+            vec![tag, marker, shared],
+            vec![0, 1, 2],
+            vec![0, 1, 1],
+            9,
+            1,
+        )
+        .into();
+
+        let abi = packed_shared_internal_abi_info(&mut ctx, packed)
+            .expect("ABI classification must succeed")
+            .expect("a zero-sized field must not knock the struct out of the ABI lane");
+        assert_eq!(llvm_type_size_align(&ctx, abi.semantic_ty), Some((9, 1)));
+        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((9, 1)));
+        assert!(!llvm_type_contains_pointer_in_address_space(
+            &ctx,
+            abi.storage_ty,
+            llvm_types::address_space::SHARED,
+        ));
+    }
+
+    #[test]
+    fn packed_shared_internal_abi_genericizes_bounded_shared_pointer_array() {
+        let mut ctx = make_ctx();
+        let pointee = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let shared_array: TypeHandle = MirArrayType::get(&mut ctx, shared, 2).into();
+        let tag = mir_uint(&mut ctx, 8);
+        let outer: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedSharedArray".into(),
+            vec!["tag".into(), "ptrs".into()],
+            vec![tag, shared_array],
+            vec![0, 1],
+            vec![0, 1],
+            17,
+            1,
+        )
+        .into();
+
+        let abi = packed_shared_internal_abi_info(&mut ctx, outer)
+            .expect("classification must not error")
+            .expect("a bounded AS3 array must use the target-stable internal carrier");
+        assert_eq!(llvm_type_size_align(&ctx, abi.semantic_ty), Some((17, 1)));
+        assert_eq!(llvm_type_size_align(&ctx, abi.storage_ty), Some((17, 1)));
+        assert!(!llvm_type_contains_pointer_in_address_space(
+            &ctx,
+            abi.storage_ty,
+            llvm_types::address_space::SHARED,
+        ));
+
+        let outer_fields = struct_fields(&ctx, abi.storage_ty);
+        let array_ref = outer_fields[1].deref(&ctx);
+        let array = array_ref
+            .downcast_ref::<llvm_types::ArrayType>()
+            .expect("bounded array field must remain an LLVM array");
+        assert_eq!(array.size(), 2);
+        let element = array.elem_type();
+        let element_ref = element.deref(&ctx);
+        let pointer = element_ref
+            .downcast_ref::<llvm_types::PointerType>()
+            .expect("array elements must remain pointer-typed");
+        assert_eq!(pointer.address_space(), llvm_types::address_space::GENERIC);
+    }
+
+    #[test]
+    fn packed_shared_internal_abi_accepts_array_rewrite_at_exact_bound() {
+        let mut ctx = make_ctx();
+        let pointee = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let count = MAX_PACKED_SHARED_INTERNAL_ABI_ARRAY_REWRITE_LEAVES;
+        let shared_array: TypeHandle = MirArrayType::get(&mut ctx, shared, count).into();
+        let tag = mir_uint(&mut ctx, 8);
+        let outer: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedSharedArrayAtBound".into(),
+            vec!["tag".into(), "ptrs".into()],
+            vec![tag, shared_array],
+            vec![0, 1],
+            vec![0, 1],
+            1 + 8 * count,
+            1,
+        )
+        .into();
+
+        assert!(
+            packed_shared_internal_abi_info(&mut ctx, outer)
+                .expect("classification must not error")
+                .is_some(),
+            "the exact bounded-array rewrite limit must remain supported"
+        );
+    }
+
+    #[test]
+    fn packed_shared_internal_abi_rejects_array_rewrite_above_bound() {
+        let mut ctx = make_ctx();
+        let pointee = mir_uint(&mut ctx, 32);
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, pointee, false).into();
+        let count = MAX_PACKED_SHARED_INTERNAL_ABI_ARRAY_REWRITE_LEAVES + 1;
+        let shared_array: TypeHandle = MirArrayType::get(&mut ctx, shared, count).into();
+        let tag = mir_uint(&mut ctx, 8);
+        let outer: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedSharedArrayAboveBound".into(),
+            vec!["tag".into(), "ptrs".into()],
+            vec![tag, shared_array],
+            vec![0, 1],
+            vec![0, 1],
+            1 + 8 * count,
+            1,
+        )
+        .into();
+
+        assert!(
+            packed_shared_internal_abi_info(&mut ctx, outer)
+                .expect("classification must not error")
+                .is_none(),
+            "array-expanded AS3 leaves above the explicit budget must fail closed"
+        );
+    }
+
+    #[test]
+    fn packed_shared_internal_abi_rejects_shared_pointer_vector() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 8);
+        let shared_pointer: TypeHandle =
+            llvm_types::PointerType::get(&ctx, llvm_types::address_space::SHARED).into();
+        let shared_vector: TypeHandle =
+            llvm_types::VectorType::get(&ctx, shared_pointer, 2, llvm_types::VectorTypeKind::Fixed)
+                .into();
+        let outer: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedSharedVector".into(),
+            vec!["tag".into(), "ptrs".into()],
+            vec![tag, shared_vector],
+            vec![0, 1],
+            vec![0, 1],
+            17,
+            1,
+        )
+        .into();
+
+        assert!(
+            packed_shared_internal_abi_info(&mut ctx, outer)
+                .expect("classification must not error")
+                .is_none(),
+            "shared-pointer vectors must remain outside the packed-AS3 internal ABI lane"
+        );
+    }
+}
diff --git a/crates/mir-lower/src/convert/types/global_layout.rs b/crates/mir-lower/src/convert/types/global_layout.rs
new file mode 100644
index 0000000000..89807ca5e1
--- /dev/null
+++ b/crates/mir-lower/src/convert/types/global_layout.rs
@@ -0,0 +1,826 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Layout validators for initialized (and relocated) device globals.
+
+use dialect_mir::types::{MirEnumType, MirStructType, MirTupleType};
+use llvm_export::types as llvm_types;
+use pliron::context::Context;
+use pliron::r#type::TypeHandle;
+
+use super::layout::mir_stored_size;
+use super::{
+    StructLayoutInfo, build_struct_slot_map, convert_type, enum_unmodeled_in_memory,
+    llvm_type_size_align,
+};
+
+/// Prove that an initialized Rust global can be accessed through the LLVM
+/// semantic type produced by this lowering pipeline.
+///
+/// The initializer itself is emitted as exact bytes. That is only half of the
+/// contract: later field GEPs and typed loads still use `mir_ty`. If that type
+/// places a field at a different byte offset, an exact initializer can still be
+/// read incorrectly (or even past the end of the object). Reject every shape
+/// for which we cannot prove that the two views agree.
+pub(crate) fn validate_initialized_global_layout(
+    ctx: &mut Context,
+    mir_ty: TypeHandle,
+    initializer_size: u64,
+    initializer_align: u64,
+) -> Result<(), anyhow::Error> {
+    if initializer_align == 0 || !initializer_align.is_power_of_two() {
+        return Err(anyhow::anyhow!(
+            "initialized global has invalid rustc allocation alignment {}",
+            initializer_align
+        ));
+    }
+
+    validate_initialized_global_type(ctx, mir_ty, &mut Vec::new())?;
+
+    let llvm_ty = convert_type(ctx, mir_ty)?;
+    let (llvm_size, llvm_align) = llvm_type_size_align(ctx, llvm_ty)
+        .ok_or_else(|| anyhow::anyhow!("initialized global has unsupported LLVM size/alignment"))?;
+    if llvm_size != initializer_size || llvm_align > initializer_align {
+        return Err(anyhow::anyhow!(
+            "initialized global type is not byte-compatible with rustc's allocation: the lowered LLVM value has size/alignment {}/{}, but the initializer has size/alignment {}/{}",
+            llvm_size,
+            llvm_align,
+            initializer_size,
+            initializer_align
+        ));
+    }
+
+    Ok(())
+}
+
+/// Validate an initialized global that carries pointer relocations.
+///
+/// Ordinary initialized globals keep their existing conservative semantic
+/// layout validator. Relocated globals use a separate segmented physical
+/// carrier, so a top-level `repr(packed)` struct may use that relocation path
+/// as long as rustc's field ranges are explicit, non-overlapping, and in-bounds.
+/// One direct nested struct may use the same relaxation when the top-level
+/// struct itself has an ordinary, non-divergent LLVM layout and the child's
+/// LLVM packed representation exactly reproduces rustc's offsets and size. A
+/// packed top-level struct may not stack the relaxation on a packed child, and
+/// deeper packed nesting remains on the ordinary fail-closed path.
+pub(crate) fn validate_relocated_initialized_global_layout(
+    ctx: &mut Context,
+    mir_ty: TypeHandle,
+    initializer_size: u64,
+    initializer_align: u64,
+) -> Result<(), anyhow::Error> {
+    match validate_initialized_global_layout(ctx, mir_ty, initializer_size, initializer_align) {
+        Ok(()) => Ok(()),
+        Err(original_error) => {
+            if initializer_align == 0 || !initializer_align.is_power_of_two() {
+                return Err(original_error);
+            }
+
+            let struct_ty = {
+                let ty_ref = mir_ty.deref(ctx);
+                ty_ref.downcast_ref::<MirStructType>().cloned()
+            };
+            let Some(struct_ty) = struct_ty else {
+                return Err(original_error);
+            };
+            if !struct_ty.has_explicit_layout()
+                || struct_ty.total_size() != initializer_size
+                || struct_ty.abi_align != initializer_align
+            {
+                return Err(original_error);
+            }
+
+            validate_relocated_struct_field_ranges(ctx, &struct_ty)?;
+
+            let top_level_layout = StructLayoutInfo::of_struct(&struct_ty);
+            let top_level_map = build_struct_slot_map(ctx, &top_level_layout)?;
+            let top_level_is_ordinary = !top_level_map.layout_diverges
+                && top_level_map.by_value_layout_faithful
+                && top_level_map
+                    .llvm_struct_ty
+                    .deref(ctx)
+                    .downcast_ref::<llvm_types::StructType>()
+                    .is_some_and(|ty| ty.layout() == llvm_types::StructLayout::Unpacked);
+
+            let mut visited = vec![mir_ty];
+            for field_ty in struct_ty.field_types.iter().copied() {
+                if top_level_is_ordinary {
+                    validate_relocated_initialized_global_child(ctx, field_ty, &mut visited)?;
+                } else {
+                    validate_initialized_global_type(ctx, field_ty, &mut visited)?;
+                }
+            }
+            Ok(())
+        }
+    }
+}
+
+/// Prove that rustc's explicit field ranges for a relocated top-level struct
+/// are non-overlapping and fit within the evaluated allocation.
+fn validate_relocated_struct_field_ranges(
+    ctx: &mut Context,
+    struct_ty: &MirStructType,
+) -> Result<(), anyhow::Error> {
+    let layout = StructLayoutInfo::of_struct(struct_ty);
+
+    // Relocated globals relax only natural LLVM placement. Preserve the
+    // ordinary struct-layout metadata invariants before accepting rustc's
+    // explicit byte ranges as the physical initializer contract.
+    build_struct_slot_map(ctx, &layout)?;
+
+    let mut ranges = Vec::with_capacity(layout.field_types.len());
+    for (decl_index, field_ty) in layout.field_types.iter().copied().enumerate() {
+        let field_size = if let Some(size) = mir_stored_size(ctx, field_ty) {
+            size
+        } else {
+            let llvm_ty = convert_type(ctx, field_ty)?;
+            llvm_type_size_align(ctx, llvm_ty)
+                .map(|(size, _)| size)
+                .ok_or_else(|| {
+                    anyhow::anyhow!(
+                        "relocated initialized struct `{}` field {} has unsupported size",
+                        struct_ty.name(),
+                        decl_index
+                    )
+                })?
+        };
+        if field_size == 0 {
+            continue;
+        }
+
+        let start = layout.field_offsets[decl_index];
+        let end = start.checked_add(field_size).ok_or_else(|| {
+            anyhow::anyhow!(
+                "relocated initialized struct `{}` field {} range overflows",
+                struct_ty.name(),
+                decl_index
+            )
+        })?;
+        if end > layout.total_size {
+            return Err(anyhow::anyhow!(
+                "relocated initialized struct `{}` field {} occupies bytes {}..{}, but the allocation is only {} bytes",
+                struct_ty.name(),
+                decl_index,
+                start,
+                end,
+                layout.total_size
+            ));
+        }
+        ranges.push((start, end, decl_index));
+    }
+
+    ranges.sort_by_key(|(start, _, _)| *start);
+    for pair in ranges.windows(2) {
+        let (_, previous_end, previous_index) = pair[0];
+        let (next_start, _, next_index) = pair[1];
+        if next_start < previous_end {
+            return Err(anyhow::anyhow!(
+                "relocated initialized struct `{}` fields {} and {} overlap in rustc's byte layout",
+                struct_ty.name(),
+                previous_index,
+                next_index
+            ));
+        }
+    }
+
+    Ok(())
+}
+
+/// Validate one direct child of an ordinary relocated initialized global.
+///
+/// The ordinary initialized-global validator remains the default. Only when it
+/// rejects a direct `MirStructType` do we consider the relocation-specific
+/// relaxation, and only if `build_struct_slot_map` proves that the divergent
+/// rustc layout is represented exactly by an LLVM packed struct. Its own field
+/// ranges must still be explicit, non-overlapping, and in-bounds. Children of
+/// that packed struct go back through the ordinary validator, deliberately
+/// limiting this exception to one nesting level.
+fn validate_relocated_initialized_global_child(
+    ctx: &mut Context,
+    mir_ty: TypeHandle,
+    visited: &mut Vec<TypeHandle>,
+) -> Result<(), anyhow::Error> {
+    if visited.contains(&mir_ty) {
+        return Ok(());
+    }
+
+    let mut ordinary_visited = visited.clone();
+    let original_error = match validate_initialized_global_type(ctx, mir_ty, &mut ordinary_visited)
+    {
+        Ok(()) => {
+            *visited = ordinary_visited;
+            return Ok(());
+        }
+        Err(error) => error,
+    };
+
+    let struct_ty = {
+        let ty_ref = mir_ty.deref(ctx);
+        ty_ref.downcast_ref::<MirStructType>().cloned()
+    };
+    let Some(struct_ty) = struct_ty else {
+        return Err(original_error);
+    };
+    if !struct_ty.has_explicit_layout() {
+        return Err(original_error);
+    }
+
+    let layout = StructLayoutInfo::of_struct(&struct_ty);
+    let map = build_struct_slot_map(ctx, &layout)?;
+    let is_exact_packed = map.layout_diverges
+        && map.by_value_layout_faithful
+        && map
+            .llvm_struct_ty
+            .deref(ctx)
+            .downcast_ref::<llvm_types::StructType>()
+            .is_some_and(|ty| ty.layout() == llvm_types::StructLayout::Packed);
+    if !is_exact_packed {
+        return Err(original_error);
+    }
+
+    validate_relocated_struct_field_ranges(ctx, &struct_ty)?;
+
+    visited.push(mir_ty);
+    for field_ty in struct_ty.field_types.iter().copied() {
+        validate_initialized_global_type(ctx, field_ty, visited)?;
+    }
+    Ok(())
+}
+
+fn validate_initialized_global_type(
+    ctx: &mut Context,
+    mir_ty: TypeHandle,
+    visited: &mut Vec<TypeHandle>,
+) -> Result<(), anyhow::Error> {
+    if visited.contains(&mir_ty) {
+        return Ok(());
+    }
+    visited.push(mir_ty);
+
+    if let Some(name) = enum_unmodeled_in_memory(ctx, mir_ty) {
+        return Err(anyhow::anyhow!(
+            "initialized global contains enum `{}` with unknown physical layout; refusing to guess a byte representation",
+            name
+        ));
+    }
+
+    enum Kind {
+        Struct(MirStructType),
+        Tuple(MirTupleType),
+        Enum(MirEnumType),
+        Array { element_ty: TypeHandle, size: u64 },
+        Leaf,
+    }
+
+    let kind = {
+        let ty_ref = mir_ty.deref(ctx);
+        if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
+            Kind::Struct(struct_ty.clone())
+        } else if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
+            Kind::Tuple(tuple_ty.clone())
+        } else if let Some(enum_ty) = ty_ref.downcast_ref::<MirEnumType>() {
+            Kind::Enum(enum_ty.clone())
+        } else if let Some(array_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
+            Kind::Array {
+                element_ty: array_ty.element_ty,
+                size: array_ty.size,
+            }
+        } else {
+            Kind::Leaf
+        }
+    };
+
+    match kind {
+        Kind::Struct(struct_ty) => {
+            validate_initialized_struct_layout(ctx, mir_ty, &struct_ty)?;
+            for field_ty in struct_ty.field_types {
+                validate_initialized_global_type(ctx, field_ty, visited)?;
+            }
+        }
+        Kind::Tuple(tuple_ty) => {
+            if !tuple_ty.get_types().is_empty() {
+                // Tuples carry rustc's field offsets exactly like structs;
+                // prove the lowered aggregate reproduces them byte-for-byte.
+                let layout = StructLayoutInfo::of_tuple(&tuple_ty);
+                validate_initialized_aggregate_layout(
+                    ctx,
+                    mir_ty,
+                    "tuple",
+                    "tuple",
+                    &layout,
+                    tuple_ty.abi_align(),
+                    tuple_ty.has_explicit_layout(),
+                )?;
+            }
+            for field_ty in tuple_ty.get_types().iter().copied() {
+                validate_initialized_global_type(ctx, field_ty, visited)?;
+            }
+        }
+        Kind::Enum(enum_ty) => {
+            if enum_ty.total_size() > 0 {
+                let llvm_ty = convert_type(ctx, mir_ty)?;
+                let (llvm_size, llvm_align) =
+                    llvm_type_size_align(ctx, llvm_ty).ok_or_else(|| {
+                        anyhow::anyhow!(
+                            "initialized enum `{}` has unsupported LLVM size/alignment",
+                            enum_ty.name()
+                        )
+                    })?;
+                if llvm_size != enum_ty.total_size() || llvm_align > enum_ty.abi_align() {
+                    return Err(anyhow::anyhow!(
+                        "initialized enum `{}` is not byte-compatible with rustc's layout: the lowered LLVM value has size/alignment {}/{}, but rustc requires {}/{}",
+                        enum_ty.name(),
+                        llvm_size,
+                        llvm_align,
+                        enum_ty.total_size(),
+                        enum_ty.abi_align()
+                    ));
+                }
+            }
+            for field_ty in enum_ty.all_field_types {
+                validate_initialized_global_type(ctx, field_ty, visited)?;
+            }
+        }
+        Kind::Array { element_ty, size } => {
+            // A zero-length array contributes no element bytes. Its outer LLVM
+            // size/alignment is still checked by
+            // `validate_initialized_global_layout`, but recursively rejecting
+            // an element layout would incorrectly reject valid promoted
+            // `&mut [Packed; 0]` constants whose physical allocation is empty.
+            if size != 0 {
+                validate_initialized_global_type(ctx, element_ty, visited)?;
+            }
+        }
+        Kind::Leaf => {}
+    }
+
+    Ok(())
+}
+
+fn validate_initialized_struct_layout(
+    ctx: &mut Context,
+    mir_ty: TypeHandle,
+    struct_ty: &MirStructType,
+) -> Result<(), anyhow::Error> {
+    let has_layout = struct_ty.has_explicit_layout();
+    let layout = StructLayoutInfo::of_struct(struct_ty);
+    let name = struct_ty.name().to_string();
+    validate_initialized_aggregate_layout(
+        ctx,
+        mir_ty,
+        "struct",
+        &name,
+        &layout,
+        struct_ty.abi_align,
+        has_layout,
+    )
+}
+
+/// Shared byte-layout validation for initialized-global structs and tuples.
+///
+/// Proves that the lowered LLVM aggregate places every field at exactly the
+/// byte offset rustc chose and matches rustc's total size, so a constant
+/// initializer written slot-by-slot reproduces the host bytes.
+#[allow(clippy::too_many_arguments)]
+fn validate_initialized_aggregate_layout(
+    ctx: &mut Context,
+    mir_ty: TypeHandle,
+    kind_noun: &str,
+    name: &str,
+    layout: &StructLayoutInfo,
+    abi_align: u64,
+    has_explicit_layout: bool,
+) -> Result<(), anyhow::Error> {
+    if layout.total_size == 0 {
+        let llvm_ty = convert_type(ctx, mir_ty)?;
+        let (llvm_size, _) = llvm_type_size_align(ctx, llvm_ty).ok_or_else(|| {
+            anyhow::anyhow!(
+                "initialized {} `{}` has unsupported LLVM size/alignment",
+                kind_noun,
+                name
+            )
+        })?;
+        if llvm_size == 0 {
+            return Ok(());
+        }
+        return Err(anyhow::anyhow!(
+            "initialized {} `{}` has no stored size but lowers to {} bytes",
+            kind_noun,
+            name,
+            llvm_size
+        ));
+    }
+    if !has_explicit_layout {
+        return Err(anyhow::anyhow!(
+            "initialized {} `{}` has no rustc field-offset metadata",
+            kind_noun,
+            name
+        ));
+    }
+
+    let slots = build_struct_slot_map(ctx, layout)?;
+    let llvm_fields: Vec<_> = slots
+        .llvm_struct_ty
+        .deref(ctx)
+        .downcast_ref::<llvm_types::StructType>()
+        .expect("aggregate slot map must produce an LLVM struct")
+        .fields()
+        .collect();
+
+    let mut slot_offsets = Vec::with_capacity(llvm_fields.len());
+    let mut current_offset = 0u64;
+    for llvm_field in &llvm_fields {
+        let (field_size, field_align) =
+            llvm_type_size_align(ctx, *llvm_field).ok_or_else(|| {
+                anyhow::anyhow!(
+                    "initialized {} `{}` field has unsupported LLVM size/alignment",
+                    kind_noun,
+                    name
+                )
+            })?;
+        current_offset = current_offset.div_ceil(field_align.max(1)) * field_align.max(1);
+        slot_offsets.push(current_offset);
+        current_offset += field_size;
+    }
+
+    for (decl_index, slot) in slots.decl_to_llvm.iter().enumerate() {
+        let Some(slot) = slot else {
+            continue;
+        };
+        let actual_offset = slot_offsets[*slot as usize];
+        let expected_offset = layout.field_offsets[decl_index];
+        if actual_offset != expected_offset {
+            return Err(anyhow::anyhow!(
+                "initialized {} `{}` field {} lowers at byte {}, but rustc placed it at byte {}; packed and overlapping field layouts are not yet supported",
+                kind_noun,
+                name,
+                decl_index,
+                actual_offset,
+                expected_offset
+            ));
+        }
+    }
+
+    let (llvm_size, llvm_align) =
+        llvm_type_size_align(ctx, slots.llvm_struct_ty).ok_or_else(|| {
+            anyhow::anyhow!(
+                "initialized {} `{}` has unsupported LLVM size/alignment",
+                kind_noun,
+                name
+            )
+        })?;
+    if llvm_size != layout.total_size || llvm_align > abi_align {
+        return Err(anyhow::anyhow!(
+            "initialized {} `{}` lowers to size/alignment {}/{}, but rustc requires {}/{}",
+            kind_noun,
+            name,
+            llvm_size,
+            llvm_align,
+            layout.total_size,
+            abi_align
+        ));
+    }
+
+    Ok(())
+}
+
+#[cfg(test)]
+mod tests {
+    use super::super::test_support::{make_ctx, mir_uint, mir_zst};
+    use super::*;
+    use dialect_mir::types::{EnumVariant, MirArrayType, MirPtrType, MirUnionType};
+
+    #[test]
+    fn initialized_global_layout_accepts_explicit_overalignment() {
+        let mut ctx = make_ctx();
+        let zst = mir_zst(&mut ctx);
+        validate_initialized_global_layout(&mut ctx, zst, 0, 1).unwrap();
+
+        let byte = mir_uint(&mut ctx, 8);
+        let over_aligned: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "OverAligned".into(),
+            vec!["byte".into()],
+            vec![byte],
+            vec![0],
+            vec![0],
+            16,
+            16,
+        )
+        .into();
+
+        validate_initialized_global_layout(&mut ctx, over_aligned, 16, 16).unwrap();
+    }
+
+    #[test]
+    fn initialized_global_layout_rejects_packed_and_nested_packed_structs() {
+        let mut ctx = make_ctx();
+        let byte = mir_uint(&mut ctx, 8);
+        let word = mir_uint(&mut ctx, 32);
+        let packed: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Packed".into(),
+            vec!["tag".into(), "word".into()],
+            vec![byte, word],
+            vec![0, 1],
+            vec![0, 1],
+            5,
+            1,
+        )
+        .into();
+
+        let empty_packed: TypeHandle = MirArrayType::get(&mut ctx, packed, 0).into();
+        validate_initialized_global_layout(&mut ctx, empty_packed, 0, 1)
+            .expect("[Packed; 0] has no element bytes whose field layout can diverge");
+
+        let err = validate_initialized_global_layout(&mut ctx, packed, 5, 1).unwrap_err();
+        assert!(err.to_string().contains("field 1 lowers at byte 4"));
+
+        // Nesting must not hide the incompatible packed representation.
+        let wide = mir_uint(&mut ctx, 64);
+        let outer: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Outer".into(),
+            vec!["packed".into(), "wide".into()],
+            vec![packed, wide],
+            vec![0, 1],
+            vec![0, 8],
+            16,
+            8,
+        )
+        .into();
+        let err = validate_initialized_global_layout(&mut ctx, outer, 16, 8).unwrap_err();
+        assert!(err.to_string().contains("lowers at byte"));
+    }
+
+    #[test]
+    fn relocated_initialized_global_layout_accepts_top_level_packed_struct() {
+        let mut ctx = make_ctx();
+        let byte = mir_uint(&mut ctx, 8);
+        let target = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_global(&mut ctx, target, false).into();
+        let packed: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedRelocation".into(),
+            vec!["tag".into(), "ptr".into()],
+            vec![byte, pointer],
+            vec![0, 1],
+            vec![0, 1],
+            9,
+            1,
+        )
+        .into();
+
+        validate_relocated_initialized_global_layout(&mut ctx, packed, 9, 1)
+            .expect("relocated top-level packed struct must be accepted");
+        assert!(validate_initialized_global_layout(&mut ctx, packed, 9, 1).is_err());
+    }
+
+    #[test]
+    fn relocated_initialized_global_layout_accepts_thin_pointer_union() {
+        let mut ctx = make_ctx();
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let u8_ty = mir_uint(&mut ctx, 8);
+        let word_ptr: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let byte_ptr: TypeHandle = MirPtrType::get_generic(&mut ctx, u8_ty, false).into();
+        let union_ty: TypeHandle = MirUnionType::get(
+            &mut ctx,
+            "RelocatedPointerUnion".into(),
+            vec!["word".into(), "byte".into()],
+            vec![word_ptr, byte_ptr],
+            8,
+            8,
+        )
+        .into();
+
+        validate_relocated_initialized_global_layout(&mut ctx, union_ty, 8, 8)
+            .expect("one pointer-word union must be valid relocated global storage");
+    }
+
+    #[test]
+    fn relocated_initialized_global_layout_rejects_malformed_memory_order() {
+        let mut ctx = make_ctx();
+        let byte = mir_uint(&mut ctx, 8);
+        let target = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_global(&mut ctx, target, false).into();
+        let malformed: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "MalformedPackedRelocation".into(),
+            vec!["tag".into(), "ptr".into()],
+            vec![byte, pointer],
+            vec![0, 0],
+            vec![0, 1],
+            9,
+            1,
+        )
+        .into();
+
+        let error = validate_relocated_initialized_global_layout(&mut ctx, malformed, 9, 1)
+            .expect_err("malformed memory order must remain unsupported");
+        assert!(error.to_string().contains("not a permutation"), "{error}");
+    }
+
+    #[test]
+    fn relocated_initialized_global_layout_accepts_one_direct_nested_packed_struct() {
+        let mut ctx = make_ctx();
+        let byte = mir_uint(&mut ctx, 8);
+        let word = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_global(&mut ctx, word, false).into();
+        let nested_packed: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "NestedPackedRelocation".into(),
+            vec!["tag".into(), "ptr".into()],
+            vec![byte, pointer],
+            vec![0, 1],
+            vec![0, 1],
+            9,
+            1,
+        )
+        .into();
+        let outer: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "OuterPackedRelocation".into(),
+            vec!["head".into(), "nested".into()],
+            vec![word, nested_packed],
+            vec![0, 1],
+            vec![0, 4],
+            16,
+            4,
+        )
+        .into();
+
+        validate_relocated_initialized_global_layout(&mut ctx, outer, 16, 4)
+            .expect("one direct nested packed relocation carrier must be accepted");
+        assert!(validate_initialized_global_layout(&mut ctx, outer, 16, 4).is_err());
+    }
+
+    #[test]
+    fn relocated_initialized_global_layout_rejects_packed_root_with_packed_child() {
+        let mut ctx = make_ctx();
+        let byte = mir_uint(&mut ctx, 8);
+        let word = mir_uint(&mut ctx, 32);
+        let target = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_global(&mut ctx, target, false).into();
+        let nested_packed: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "NestedPackedRelocation".into(),
+            vec!["tag".into(), "ptr".into()],
+            vec![byte, pointer],
+            vec![0, 1],
+            vec![0, 1],
+            9,
+            1,
+        )
+        .into();
+        let packed_root: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PackedRootRelocation".into(),
+            vec!["tag".into(), "word".into(), "nested".into()],
+            vec![byte, word, nested_packed],
+            vec![0, 1, 2],
+            vec![0, 1, 5],
+            14,
+            1,
+        )
+        .into();
+
+        let error = validate_relocated_initialized_global_layout(&mut ctx, packed_root, 14, 1)
+            .expect_err("a packed top-level struct must not stack the nested packed relaxation");
+        assert!(error.to_string().contains("lowers at byte"), "{error}");
+    }
+
+    #[test]
+    fn relocated_initialized_global_layout_rejects_deeper_packed_nesting() {
+        let mut ctx = make_ctx();
+        let byte = mir_uint(&mut ctx, 8);
+        let word = mir_uint(&mut ctx, 32);
+        let target = mir_uint(&mut ctx, 32);
+        let pointer: TypeHandle = MirPtrType::get_global(&mut ctx, target, false).into();
+        let inner_packed: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "InnerPackedRelocation".into(),
+            vec!["tag".into(), "ptr".into()],
+            vec![byte, pointer],
+            vec![0, 1],
+            vec![0, 1],
+            9,
+            1,
+        )
+        .into();
+        let middle_packed: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "MiddlePackedRelocation".into(),
+            vec!["tag".into(), "word".into(), "inner".into()],
+            vec![byte, word, inner_packed],
+            vec![0, 1, 2],
+            vec![0, 1, 5],
+            14,
+            1,
+        )
+        .into();
+        let outer: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "OuterDeepPackedRelocation".into(),
+            vec!["head".into(), "middle".into()],
+            vec![word, middle_packed],
+            vec![0, 1],
+            vec![0, 4],
+            20,
+            4,
+        )
+        .into();
+
+        let error = validate_relocated_initialized_global_layout(&mut ctx, outer, 20, 4)
+            .expect_err("packed relocation relaxation must stop after one nesting level");
+        assert!(error.to_string().contains("lowers at byte"), "{error}");
+    }
+
+    #[test]
+    fn relocated_initialized_global_layout_rejects_overlapping_struct_fields() {
+        let mut ctx = make_ctx();
+        let word = mir_uint(&mut ctx, 32);
+        let overlapping: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "OverlappingRelocation".into(),
+            vec!["left".into(), "right".into()],
+            vec![word, word],
+            vec![0, 1],
+            vec![0, 0],
+            4,
+            1,
+        )
+        .into();
+
+        let error = validate_relocated_initialized_global_layout(&mut ctx, overlapping, 4, 1)
+            .expect_err("overlapping field ranges must remain unsupported");
+        assert!(error.to_string().contains("overlap"), "{error}");
+    }
+
+    #[test]
+    fn initialized_global_layout_rejects_old_union_and_tuple_models() {
+        let mut ctx = make_ctx();
+        let word = mir_uint(&mut ctx, 32);
+        let union_as_struct: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "UnionBeforeSharedStorageLowering".into(),
+            vec!["left".into(), "right".into()],
+            vec![word, word],
+            vec![0, 1],
+            vec![0, 0],
+            4,
+            4,
+        )
+        .into();
+        let err = validate_initialized_global_layout(&mut ctx, union_as_struct, 4, 4).unwrap_err();
+        assert!(err.to_string().contains("field 1 lowers at byte 4"));
+
+        // A tuple without recorded rustc layout cannot prove its bytes.
+        let byte = mir_uint(&mut ctx, 8);
+        let wide = mir_uint(&mut ctx, 64);
+        let tuple: TypeHandle = MirTupleType::get(&mut ctx, vec![byte, wide]).into();
+        let err = validate_initialized_global_layout(&mut ctx, tuple, 16, 8).unwrap_err();
+        assert!(
+            err.to_string()
+                .contains("no stored size but lowers to 16 bytes"),
+            "{err}"
+        );
+
+        // The same tuple carrying rustc's real (reordered) layout validates:
+        // memory order is (wide @ 0, byte @ 8), total size 16.
+        let laid_out_tuple: TypeHandle = MirTupleType::get_with_layout(
+            &mut ctx,
+            vec![byte, wide],
+            vec![1, 0],
+            vec![8, 0],
+            16,
+            8,
+        )
+        .into();
+        validate_initialized_global_layout(&mut ctx, laid_out_tuple, 16, 8)
+            .expect("tuples with recorded rustc offsets are provable initialized-global storage");
+    }
+
+    #[test]
+    fn initialized_global_layout_rejects_enum_with_unknown_physical_layout() {
+        let mut ctx = make_ctx();
+        let discr = mir_uint(&mut ctx, 8);
+        let payload = mir_uint(&mut ctx, 32);
+        let niche: TypeHandle = MirEnumType::get(
+            &mut ctx,
+            "OptionNonZero".into(),
+            discr,
+            vec![0, 1],
+            vec![
+                EnumVariant::unit("None".into()),
+                EnumVariant::new("Some".into(), vec![payload]),
+            ],
+        )
+        .into();
+
+        let err = validate_initialized_global_layout(&mut ctx, niche, 4, 4).unwrap_err();
+        assert!(err.to_string().contains("unknown physical layout"));
+    }
+}
diff --git a/crates/mir-lower/src/convert/types/layout.rs b/crates/mir-lower/src/convert/types/layout.rs
new file mode 100644
index 0000000000..54083e2424
--- /dev/null
+++ b/crates/mir-lower/src/convert/types/layout.rs
@@ -0,0 +1,548 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Size/alignment metrics, padding/filler type builders, byte-faithfulness
+//! and `i1`-storage predicates, and natural struct layout walks.
+
+use dialect_mir::types::{
+    MirArrayType, MirEnumType, MirFP16Type, MirPtrType, MirStructType, MirTupleType, MirUnionType,
+};
+use llvm_export::types as llvm_types;
+use pliron::builtin::type_interfaces::FloatTypeInterface;
+use pliron::builtin::types::{FP32Type, FP64Type, IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::r#type::{TypeHandle, type_cast};
+
+/// Create a padding type: `[N x i8]` for N bytes of padding.
+pub(super) fn make_padding_type(ctx: &mut Context, size: u64) -> TypeHandle {
+    let i8_ty = IntegerType::get(ctx, 8, Signedness::Signless);
+    llvm_types::ArrayType::get(ctx, i8_ty.into(), size).into()
+}
+
+/// Storage for `size` bytes of enum filler at byte `offset`: bytes the payload
+/// occupies that no typed slot claims.
+///
+/// `[N x i8]` is byte-exact but costs one leaf *per byte* everywhere a payload
+/// value is built, merged, or taken apart. `Option<&[T]>` is the shape that
+/// shows it: the niche carrier claims the pointer, the length is left to an
+/// 8-byte filler, and building the value then decomposes that length into
+/// eight `i8` `insertvalue`s, every block merge carries eight `phi i8`, and
+/// reading it back is a chain of `prmt` byte permutes with the aggregate
+/// spilled to `.local` in between. Measured on sm_86, it costs the *pointer*
+/// too: it rides through the same byte soup, `InferAddressSpaces` can no
+/// longer follow it, and the access lands in the generic window (`ld.v2.b64`)
+/// instead of `ld.global.v2.b64`.
+///
+/// One integer of the same width is the same bytes in one leaf. It is only
+/// legal where it moves nothing:
+///
+/// - the width is 2, 4 or 8 bytes, so the integer is byte-faithful (a multiple
+///   of 8 bits, hence no padding of its own). 16 is deliberately excluded:
+///   `i128` is legal LLVM but lowers to register pairs on NVPTX, so widening
+///   that far trades one win for another cost and wants its own measurement;
+/// - `offset` is a multiple of the width, so LLVM inserts no gap ahead of the
+///   field and every later field keeps its byte offset;
+/// - the width does not exceed the enum's alignment, or the struct's natural
+///   alignment would rise above rustc's.
+///
+/// Anything else keeps the byte array. The filler is a *vehicle*, not a claim:
+/// nothing reads it field-wise, because a payload that has no typed slot
+/// round-trips through memory as a whole aggregate, and both ends of that
+/// round trip are byte-exact. `build_enum_slot_map`'s own size and alignment
+/// assertions — hard errors, not debug checks — backstop all three conditions.
+pub(super) fn make_enum_filler_type(
+    ctx: &mut Context,
+    offset: u64,
+    size: u64,
+    abi_align: u64,
+) -> TypeHandle {
+    if matches!(size, 2 | 4 | 8) && offset.is_multiple_of(size) && size <= abi_align.max(1) {
+        let width = u32::try_from(size * 8).expect("size is at most 8, so width is at most 64");
+        return IntegerType::get(ctx, width, Signedness::Signless).into();
+    }
+    make_padding_type(ctx, size)
+}
+
+/// Whether this is an aggregate/vector that contains LLVM `i1` storage.
+///
+/// Rust `bool` is an SSA `i1`, but its memory representation is one complete
+/// byte whose only valid values are 0 and 1. Enum storage never uses `i1` as
+/// a physical type: scalar bools claim an explicit i8 byte, and aggregates
+/// containing bools claim their byte-faithful twin (see
+/// [`llvm_byte_faithful_twin`]), with construction canonicalizing the value
+/// before the store.
+pub(crate) fn llvm_type_contains_i1(ctx: &Context, ty: TypeHandle) -> bool {
+    let ty_ref = ty.deref(ctx);
+    if let Some(integer) = ty_ref.downcast_ref::<IntegerType>() {
+        return integer.width() == 1;
+    }
+    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+        return llvm_type_contains_i1(ctx, array.elem_type());
+    }
+    if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
+        return llvm_type_contains_i1(ctx, vector.elem_type());
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+        return struct_ty
+            .fields()
+            .any(|field| llvm_type_contains_i1(ctx, field));
+    }
+    false
+}
+
+/// The byte-faithful storage twin of an LLVM type: every `i1` leaf becomes
+/// its canonical `i8` memory byte, recursively through structs and arrays.
+///
+/// Rust guarantees a bool occupies one full byte holding exactly 0 or 1, so
+/// storing the twin (with each bool zero-extended) writes the same bytes the
+/// host writes, while re-loading the original type from those canonical
+/// bytes remains well-defined. Sizes and alignments are unchanged because an
+/// `i1` already occupies one byte of storage.
+///
+/// Returns `None` for shapes with a different memory story (`i1` vectors are
+/// bit-packed masks) or unknown containers; callers must fail closed.
+pub(crate) fn llvm_byte_faithful_twin(ctx: &mut Context, ty: TypeHandle) -> Option<TypeHandle> {
+    if !llvm_type_contains_i1(ctx, ty) {
+        return Some(ty);
+    }
+    enum Shape {
+        Bool,
+        Array(TypeHandle, u64),
+        Struct {
+            fields: Vec<TypeHandle>,
+            layout: llvm_types::StructLayout,
+        },
+        Other,
+    }
+    let shape = {
+        let ty_ref = ty.deref(ctx);
+        if ty_ref
+            .downcast_ref::<IntegerType>()
+            .is_some_and(|integer| integer.width() == 1)
+        {
+            Shape::Bool
+        } else if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+            Shape::Array(array.elem_type(), array.size())
+        } else if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+            Shape::Struct {
+                fields: struct_ty.fields().collect(),
+                layout: struct_ty.layout(),
+            }
+        } else {
+            Shape::Other
+        }
+    };
+    match shape {
+        Shape::Bool => Some(IntegerType::get(ctx, 8, Signedness::Signless).into()),
+        Shape::Array(elem, count) => {
+            let twin = llvm_byte_faithful_twin(ctx, elem)?;
+            Some(llvm_types::ArrayType::get(ctx, twin, count).into())
+        }
+        Shape::Struct { fields, layout } => {
+            let twins = fields
+                .into_iter()
+                .map(|field| llvm_byte_faithful_twin(ctx, field))
+                .collect::<Option<Vec<_>>>()?;
+            Some(llvm_types::StructType::get_unnamed(ctx, (twins, layout)).into())
+        }
+        Shape::Other => None,
+    }
+}
+
+/// Whether a MIR aggregate contains a semantic Rust bool value.
+///
+/// This deliberately stops at pointers/slices: a pointee bool does not occupy
+/// bytes in the aggregate itself. It also stops at nested enums, whose own
+/// slot-map construction is responsible for canonicalizing a top-level bool
+/// or rejecting a deeper one. Inspecting the MIR type is necessary because a
+/// union may lower to raw i8 storage and thereby hide a bool from the LLVM
+/// type-level check above.
+pub(super) fn mir_type_contains_i1(ctx: &Context, ty: TypeHandle) -> bool {
+    let ty_ref = ty.deref(ctx);
+    if let Some(integer) = ty_ref.downcast_ref::<IntegerType>() {
+        return integer.width() == 1;
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
+        return struct_ty
+            .field_types()
+            .iter()
+            .copied()
+            .any(|field| mir_type_contains_i1(ctx, field));
+    }
+    if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
+        return tuple_ty
+            .get_types()
+            .iter()
+            .copied()
+            .any(|field| mir_type_contains_i1(ctx, field));
+    }
+    if let Some(array_ty) = ty_ref.downcast_ref::<dialect_mir::types::MirArrayType>() {
+        return mir_type_contains_i1(ctx, array_ty.element_ty);
+    }
+    if let Some(union_ty) = ty_ref.downcast_ref::<MirUnionType>() {
+        return union_ty
+            .field_types()
+            .iter()
+            .copied()
+            .any(|field| mir_type_contains_i1(ctx, field));
+    }
+    false
+}
+
+/// Whether loading and storing this LLVM value preserves every byte in its
+/// allocation. In particular, `i1` is not byte-faithful: it occupies one
+/// addressable byte, but LLVM does not define the upper seven stored bits.
+pub(crate) fn llvm_type_is_byte_faithful(ctx: &Context, ty: TypeHandle) -> bool {
+    let ty_ref = ty.deref(ctx);
+    if let Some(int_ty) = ty_ref.downcast_ref::<IntegerType>() {
+        return int_ty.width().is_multiple_of(8);
+    }
+    if ty_ref.is::<llvm_types::HalfType>()
+        || ty_ref.is::<FP32Type>()
+        || ty_ref.is::<FP64Type>()
+        || ty_ref.is::<llvm_types::PointerType>()
+    {
+        return true;
+    }
+    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+        return llvm_type_is_byte_faithful(ctx, array.elem_type());
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+        let fields: Vec<_> = struct_ty.fields().collect();
+        if struct_ty.layout() == llvm_types::StructLayout::Packed {
+            return fields
+                .into_iter()
+                .all(|field| llvm_type_is_byte_faithful(ctx, field));
+        }
+
+        let mut end = 0u64;
+        let mut max_align = 1u64;
+        for field in fields {
+            if !llvm_type_is_byte_faithful(ctx, field) {
+                return false;
+            }
+            let Some((field_size, field_align)) = llvm_type_size_align(ctx, field) else {
+                return false;
+            };
+            let field_align = field_align.max(1);
+            let aligned_end = end.div_ceil(field_align) * field_align;
+            if aligned_end != end {
+                // LLVM would insert bytes that are not represented by an SSA
+                // field. Loading and re-storing the aggregate would lose them.
+                return false;
+            }
+            end += field_size;
+            max_align = max_align.max(field_align);
+        }
+        // Reject implicit trailing padding for the same reason. Explicit
+        // `[N x i8]` padding fields keep `end` equal to the allocation size.
+        return end.div_ceil(max_align) * max_align == end;
+    }
+    false
+}
+
+/// Size of a MIR-level type from rustc layout truth, when stored.
+///
+/// `MirStructType`, `MirTupleType`, `MirUnionType`, and `MirEnumType` carry
+/// `total_size` (interior and trailing padding included) straight from
+/// rustc's layout query; arrays of such aggregates multiply it out. Returns
+/// `None` when no stored size is available (e.g. niched/single-variant enums
+/// store 0) and the caller must fall back to the LLVM-level approximation.
+pub(super) fn mir_stored_size(ctx: &Context, mir_ty: TypeHandle) -> Option<u64> {
+    let ty_ref = mir_ty.deref(ctx);
+    if let Some(s) = ty_ref.downcast_ref::<MirStructType>() {
+        if s.total_size() > 0 {
+            return Some(s.total_size());
+        }
+        return None;
+    }
+    if let Some(t) = ty_ref.downcast_ref::<MirTupleType>() {
+        if t.total_size > 0 {
+            return Some(t.total_size);
+        }
+        return None;
+    }
+    if let Some(e) = ty_ref.downcast_ref::<MirEnumType>() {
+        if e.total_size() > 0 {
+            return Some(e.total_size());
+        }
+        return None;
+    }
+    if let Some(u) = ty_ref.downcast_ref::<MirUnionType>() {
+        return Some(u.total_size());
+    }
+    if let Some(a) = ty_ref.downcast_ref::<MirArrayType>() {
+        let elem_ty = a.element_ty;
+        let size = a.size;
+        // Checked: alignment claims consume this, and a wrapped product
+        // would masquerade as a small, trusted stride.
+        return mir_stored_size(ctx, elem_ty).and_then(|elem_size| elem_size.checked_mul(size));
+    }
+    None
+}
+
+/// Exact byte stride of a MIR array's element, when provable.
+///
+/// Element `i` of an array lives at byte `i * stride`, so any alignment
+/// claim about an element address is only as strong as the stride it
+/// multiplies, and a wrong stride is a miscompile. Scalars have exact
+/// sizes; MIR aggregates answer with rustc's stored size (interior and
+/// trailing padding included) via [`mir_stored_size`]; arrays of scalars
+/// multiply out. Everything else answers `None` so the caller declines
+/// instead of guessing.
+pub(crate) fn mir_element_stride(ctx: &Context, mir_ty: TypeHandle) -> Option<u64> {
+    if let Some(size) = mir_stored_size(ctx, mir_ty) {
+        return Some(size);
+    }
+    let ty_ref = mir_ty.deref(ctx);
+    if let Some(int_ty) = ty_ref.downcast_ref::<IntegerType>() {
+        return Some(u64::from(int_ty.width()).div_ceil(8));
+    }
+    // The importer's f16 is MirFP16Type; the HalfType arm covers IR that
+    // already carries the converted LLVM scalar.
+    if ty_ref.is::<MirFP16Type>() || ty_ref.is::<llvm_types::HalfType>() {
+        return Some(2);
+    }
+    if ty_ref.is::<FP32Type>() {
+        return Some(4);
+    }
+    if ty_ref.is::<FP64Type>() {
+        return Some(8);
+    }
+    if let Some(ptr_ty) = ty_ref.downcast_ref::<MirPtrType>() {
+        // Generic-space pointers are 64-bit under every data layout the
+        // exporter can choose; a shared-space pointer is 32-bit under the
+        // modern NVVM layout alone, so its stored stride is target-dependent.
+        // Claim the former, decline the latter.
+        return (ptr_ty.address_space == 0).then_some(8);
+    }
+    if let Some(array_ty) = ty_ref.downcast_ref::<MirArrayType>() {
+        // Arrays of sized aggregates already answered through
+        // `mir_stored_size` above; this recursion serves arrays of
+        // scalars and pointers, and deeper such arrays.
+        let element_ty = array_ty.element_type();
+        let count = array_ty.size();
+        drop(ty_ref);
+        return mir_element_stride(ctx, element_ty)?.checked_mul(count);
+    }
+    None
+}
+
+/// Exact ABI alignment carried by a MIR aggregate type, when rustc layout is
+/// available.
+///
+/// LLVM aggregate types cannot encode a Rust `repr(align(N))` raise. Tuples,
+/// structs, enums, and unions therefore carry rustc's alignment explicitly in
+/// the MIR dialect. Arrays have the same ABI alignment as their element, so
+/// recurse through any number of array layers instead of relying on the
+/// converted LLVM element's structural alignment.
+pub(crate) fn mir_type_abi_align(ctx: &Context, mir_ty: TypeHandle) -> Option<u64> {
+    let ty_ref = mir_ty.deref(ctx);
+    if let Some(tuple_ty) = ty_ref.downcast_ref::<MirTupleType>() {
+        return Some(tuple_ty.abi_align()).filter(|align| *align > 0);
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<MirStructType>() {
+        return Some(struct_ty.abi_align).filter(|align| *align > 0);
+    }
+    if let Some(enum_ty) = ty_ref.downcast_ref::<MirEnumType>() {
+        return Some(enum_ty.abi_align()).filter(|align| *align > 0);
+    }
+    if let Some(union_ty) = ty_ref.downcast_ref::<MirUnionType>() {
+        return Some(union_ty.abi_align()).filter(|align| *align > 0);
+    }
+    if let Some(array_ty) = ty_ref.downcast_ref::<MirArrayType>() {
+        let element_ty = array_ty.element_type();
+        return mir_type_abi_align(ctx, element_ty);
+    }
+    None
+}
+
+/// LLVM natural-layout `(size, align)` of an exported LLVM type, in bytes.
+///
+/// Mirrors LLVM's default data layout for nvptx64 (scalars align to their
+/// size, arrays to their element, non-packed structs to their widest field).
+/// Computes the real allocation size (interior and trailing padding
+/// included), which is what GEP striding and the enum size check below
+/// need. Answers `None` rather than guess: sizes here are exact or absent.
+pub(crate) fn llvm_type_size_align(ctx: &Context, ty: TypeHandle) -> Option<(u64, u64)> {
+    let ty_ref = ty.deref(ctx);
+
+    if let Some(int_ty) = ty_ref.downcast_ref::<IntegerType>() {
+        let size = (int_ty.width() as u64).div_ceil(8);
+        // i8 → 1, i16 → 2, i32 → 4, i64 → 8, i128 → 16.
+        return Some((size, size.next_power_of_two().min(16)));
+    }
+    if ty_ref.is::<llvm_types::HalfType>() {
+        return Some((2, 2));
+    }
+    if ty_ref.is::<FP32Type>() {
+        return Some((4, 4));
+    }
+    if ty_ref.is::<FP64Type>() {
+        return Some((8, 8));
+    }
+    if ty_ref.is::<llvm_types::PointerType>() {
+        // Lowering runs before the exporter chooses the minimal, legacy, or
+        // modern NVPTX data layout. The first two use 64-bit pointers in all
+        // address spaces; modern NVVM alone uses p3:32. Callers that expose
+        // physical shared-pointer width must either genericize a direct
+        // pointer first or reject the target-dependent representation.
+        return Some((8, 8));
+    }
+    if let Some(arr_ty) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+        let (elem_size, elem_align) = llvm_type_size_align(ctx, arr_ty.elem_type())?;
+        return Some((elem_size.checked_mul(arr_ty.size())?, elem_align.max(1)));
+    }
+    if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
+        if vector.is_scalable() {
+            return None;
+        }
+        let element_bits = {
+            let element = vector.elem_type();
+            let element_ref = element.deref(ctx);
+            if let Some(integer) = element_ref.downcast_ref::<IntegerType>() {
+                u64::from(integer.width())
+            } else if let Some(float) = type_cast::<dyn FloatTypeInterface>(&*element_ref) {
+                u64::try_from(float.get_semantics().bits).ok()?
+            } else if element_ref.is::<llvm_types::PointerType>() {
+                64
+            } else {
+                return None;
+            }
+        };
+        let total_bits = element_bits.checked_mul(u64::from(vector.num_elements()))?;
+        let size = total_bits.div_ceil(8);
+        // Both cuda-oxide NVPTX data layouts explicitly define fixed vector
+        // ABI alignment only for these widths. Refuse to guess LLVM defaults
+        // for any other width in physical Rust layout code.
+        let align = match total_bits {
+            16 => 2,
+            32 => 4,
+            64 => 8,
+            128 => 16,
+            _ => return None,
+        };
+        return Some((size, align));
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+        let fields: Vec<_> = struct_ty.fields().collect();
+        if struct_ty.layout() == llvm_types::StructLayout::Packed {
+            let mut size = 0u64;
+            for field in fields {
+                let (field_size, _) = llvm_type_size_align(ctx, field)?;
+                size = size.checked_add(field_size)?;
+            }
+            return Some((size, 1));
+        }
+
+        let (_end, size, align) = natural_struct_layout(ctx, &fields)?;
+        return Some((size, align));
+    }
+
+    None
+}
+
+/// The one walk defining natural (non-packed) LLVM struct placement: each
+/// field starts at the running offset rounded up to its own alignment.
+///
+/// Returns `(offsets, end, align)`: the byte offset of every field, the
+/// unrounded offset just past the last field, and the widest field alignment.
+/// [`natural_struct_layout`] and [`StructSlotMap::natural_slot_offsets`] are
+/// both views of this walk, so a size question and an offset question can
+/// never disagree.
+pub(super) fn natural_layout_walk(
+    ctx: &Context,
+    fields: &[TypeHandle],
+) -> Option<(Vec<u64>, u64, u64)> {
+    let mut offsets = Vec::with_capacity(fields.len());
+    let mut end = 0u64;
+    let mut align = 1u64;
+    for field in fields {
+        let (field_size, field_align) = llvm_type_size_align(ctx, *field)?;
+        let field_align = field_align.max(1);
+        end = end.div_ceil(field_align) * field_align;
+        offsets.push(end);
+        end = end.checked_add(field_size)?;
+        align = align.max(field_align);
+    }
+    Some((offsets, end, align))
+}
+
+/// Natural (non-packed) LLVM struct layout over `fields`.
+///
+/// Returns `(end, size, align)` where `end` is the unrounded offset just past
+/// the last field, `size` is `end` rounded up to the struct alignment (the
+/// allocation size LLVM uses for GEP striding), and `align` is the widest
+/// field alignment.
+pub(crate) fn natural_struct_layout(
+    ctx: &Context,
+    fields: &[TypeHandle],
+) -> Option<(u64, u64, u64)> {
+    let (_offsets, end, align) = natural_layout_walk(ctx, fields)?;
+    let size = end.div_ceil(align) * align;
+    Some((end, size, align))
+}
+
+#[cfg(test)]
+mod tests {
+    use super::super::test_support::{llvm_int, make_ctx, mir_uint};
+    use super::*;
+
+    #[test]
+    fn mir_abi_alignment_recurses_through_nested_arrays() {
+        let mut ctx = make_ctx();
+        let byte = mir_uint(&mut ctx, 8);
+        let marker: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Align32".into(),
+            vec![],
+            vec![],
+            vec![],
+            vec![],
+            0,
+            32,
+        )
+        .into();
+        let tuple: TypeHandle = MirTupleType::get_with_layout(
+            &mut ctx,
+            vec![marker, byte],
+            vec![0, 1],
+            vec![0, 0],
+            32,
+            32,
+        )
+        .into();
+        let inner: TypeHandle = MirArrayType::get(&mut ctx, tuple, 2).into();
+        let outer: TypeHandle = MirArrayType::get(&mut ctx, inner, 3).into();
+        let plain: TypeHandle = MirArrayType::get(&mut ctx, byte, 4).into();
+
+        assert_eq!(mir_type_abi_align(&ctx, tuple), Some(32));
+        assert_eq!(mir_type_abi_align(&ctx, inner), Some(32));
+        assert_eq!(mir_type_abi_align(&ctx, outer), Some(32));
+        assert_eq!(mir_type_abi_align(&ctx, plain), None);
+    }
+
+    #[test]
+    fn fixed_vector_layout_uses_packed_bit_width_and_rejects_unknown_widths() {
+        let mut ctx = make_ctx();
+        let i1 = llvm_int(&mut ctx, 1);
+        let v16i1: TypeHandle =
+            llvm_types::VectorType::get(&ctx, i1, 16, llvm_types::VectorTypeKind::Fixed).into();
+        assert_eq!(
+            llvm_type_size_align(&ctx, v16i1),
+            Some((2, 2)),
+            "<16 x i1> is 16 packed bits, not sixteen bytes"
+        );
+
+        let i8 = llvm_int(&mut ctx, 8);
+        let v3i8: TypeHandle =
+            llvm_types::VectorType::get(&ctx, i8, 3, llvm_types::VectorTypeKind::Fixed).into();
+        assert_eq!(
+            llvm_type_size_align(&ctx, v3i8),
+            None,
+            "the NVPTX data layout does not define a 24-bit vector alignment"
+        );
+    }
+}
diff --git a/crates/mir-lower/src/convert/types/mod.rs b/crates/mir-lower/src/convert/types/mod.rs
new file mode 100644
index 0000000000..44f3640d20
--- /dev/null
+++ b/crates/mir-lower/src/convert/types/mod.rs
@@ -0,0 +1,145 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Type conversion from `dialect-mir` types to LLVM dialect types.
+//!
+//! This module handles the translation of `dialect-mir` type representations
+//! to their LLVM dialect equivalents. Type conversion is foundational to
+//! the lowering pass—most operation converters depend on it.
+//!
+//! # Overview
+//!
+//! `dialect-mir` types are high-level, Rust-like types that preserve semantic
+//! information (signedness, slice semantics, etc.). LLVM dialect types are
+//! lower-level and match LLVM IR types directly.
+//!
+//! # Type Mapping Table
+//!
+//! | `dialect-mir` Type              | LLVM dialect Type                 | Notes                       |
+//! |---------------------------------|-----------------------------------|-----------------------------|
+//! | `IntegerType` (signed/unsigned) | `IntegerType` (signless)          | Width preserved             |
+//! | `MirFP16Type`                   | `HalfType`                        | Rust `f16` → LLVM `half`    |
+//! | `FP32Type`, `FP64Type`          | Same (builtin)                    | Pass-through                |
+//! | `MirPtrType`                    | `PointerType`                     | Address space preserved     |
+//! | `MirSliceType`                  | `StructType { ptr, i64 }`         | Fat pointer                 |
+//! | `MirDisjointSliceType`          | `StructType { ptr, i64 }`         | Same as slice               |
+//! | `MirTupleType`                  | `StructType`                      | Empty tuple → empty struct  |
+//! | `MirStructType`                 | `StructType`                      | Fields recursively converted|
+//! | `MirUnionType`                  | Aligned shared-storage struct    | All fields start at byte zero|
+//! | `MirEnumType`                   | `StructType` (rustc byte layout)  | See "Enum Type Representation" |
+//! | `ArrayType`                     | `ArrayType`                       | Element type converted      |
+//! | `VectorType`                    | `VectorType`                      | Element type converted      |
+//!
+//! # Signedness Handling
+//!
+//! LLVM IR integers are signless—the signedness is encoded in the operations
+//! that use them (e.g., `sdiv` vs `udiv`). During type conversion:
+//!
+//! - Signed/unsigned MIR integers → signless LLVM integers
+//! - The original signedness is preserved in operations (see `arithmetic.rs`)
+//!
+//! # Address Space Handling
+//!
+//! GPU memory uses address spaces to distinguish memory types:
+//!
+//! | Address Space | Memory Type | Usage                     |
+//! |---------------|-------------|---------------------------|
+//! | 0             | Generic     | Can point to any memory   |
+//! | 1             | Global      | Device memory (VRAM)      |
+//! | 3             | Shared      | Per-block shared memory   |
+//! | 4             | Constant    | Read-only device memory   |
+//! | 5             | Local       | Per-thread stack/spill    |
+//!
+//! Pointer address spaces are preserved through conversion. Slice types use
+//! generic address space (0) because they can point to any memory type.
+//!
+//! # Slice Type Representation
+//!
+//! Rust slices (`&[T]`) are represented as fat pointers in LLVM:
+//!
+//! ```text
+//! MIR: MirSliceType<f32>
+//! LLVM: struct { ptr, i64 }  ; pointer + length
+//! ```
+//!
+//! This matches the Rust ABI for slices passed by value.
+//!
+//! # Enum Type Representation
+//!
+//! A Rust enum is one tag plus the payload of whichever variant is
+//! alive; all variants share the same bytes. We build an LLVM struct
+//! that puts the tag and every payload field at the exact byte position
+//! rustc chose, inserting `[N x i8]` filler for the gaps:
+//!
+//! ```text
+//! #[repr(u32)] enum E { A(u32), B(f32), C }   // rustc: 8 bytes,
+//!                                             // tag at 0, payloads at 4
+//! LLVM: { i32, i32 }   ; slot 0 = tag, slot 1 = A's payload
+//!                      ; B's f32 also lives at byte 4 but has a
+//!                      ; different type, so it is read/written through
+//!                      ; memory instead of owning a slot
+//! ```
+//!
+//! Because the bytes match rustc exactly, enum data can cross the
+//! host/device boundary safely. The tag slot stores the variant's
+//! DECLARED discriminant value (`enum E { A = 7 }` stores 7), not its
+//! position. See `build_enum_slot_map` in this module for the full
+//! story.
+//!
+//! # Function Type Conversion
+//!
+//! Function types undergo ABI transformations:
+//!
+//! - Slice arguments are flattened to `(ptr, len)` pairs
+//! - Struct arguments are flattened to individual fields
+//! - Empty tuple return type becomes void
+//!
+//! This matches the C ABI for GPU kernels.
+
+mod conversion;
+mod enum_layout;
+mod func_abi;
+mod global_layout;
+mod layout;
+mod pointer_storage;
+mod struct_layout;
+#[cfg(test)]
+mod test_support;
+mod union_storage;
+
+pub use conversion::{convert_type, is_zero_sized_type};
+pub(crate) use conversion::{make_disjoint_slice_struct, make_slice_struct};
+pub(crate) use enum_layout::{
+    EnumSlotMap, build_enum_slot_map, convert_enum_to_llvm, enum_unmodeled_in_memory,
+    find_unmodeled_enum_in_abi,
+};
+pub(crate) use func_abi::{
+    TransparentScalarAbiInfo, packed_shared_internal_abi_info, transparent_scalar_abi_info,
+    transparent_scalar_field,
+};
+pub use func_abi::{convert_function_type, is_kernel_func};
+// Surface parity with the pre-split `types.rs`: these four are currently
+// consumed only inside `func_abi` itself or under `cfg(test)` (e.g.
+// `transparent_scalar_llvm_type` from the `lowering.rs` tests), so the
+// re-export trips `unused_imports` in non-test builds.
+#[allow(unused_imports)]
+pub(crate) use func_abi::{
+    MAX_PACKED_SHARED_INTERNAL_ABI_ARRAY_REWRITE_LEAVES, PackedSharedInternalAbiInfo,
+    TransparentScalarLayer, transparent_scalar_llvm_type,
+};
+pub(crate) use global_layout::{
+    validate_initialized_global_layout, validate_relocated_initialized_global_layout,
+};
+pub(crate) use layout::{
+    llvm_byte_faithful_twin, llvm_type_contains_i1, llvm_type_is_byte_faithful,
+    llvm_type_size_align, mir_element_stride, mir_type_abi_align, natural_struct_layout,
+};
+pub(crate) use pointer_storage::{
+    llvm_packed_struct_contains_pointer_in_address_space,
+    llvm_type_contains_pointer_in_address_space,
+};
+pub use struct_layout::struct_value_lowering_is_byte_faithful;
+pub(crate) use struct_layout::{StructLayoutInfo, StructSlotMap, build_struct_slot_map};
+pub(crate) use union_storage::build_union_storage_type;
diff --git a/crates/mir-lower/src/convert/types/pointer_storage.rs b/crates/mir-lower/src/convert/types/pointer_storage.rs
new file mode 100644
index 0000000000..ab97df737d
--- /dev/null
+++ b/crates/mir-lower/src/convert/types/pointer_storage.rs
@@ -0,0 +1,360 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Pointer provenance/overlap analysis over lowered LLVM aggregate storage.
+
+use llvm_export::types as llvm_types;
+use pliron::context::Context;
+use pliron::r#type::TypeHandle;
+
+use super::llvm_type_size_align;
+use crate::convert::enum_payload_storage::MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES;
+
+pub(super) fn llvm_type_contains_pointer(ctx: &Context, ty: TypeHandle) -> bool {
+    let ty_ref = ty.deref(ctx);
+    if ty_ref.is::<llvm_types::PointerType>() {
+        return true;
+    }
+    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+        return llvm_type_contains_pointer(ctx, array.elem_type());
+    }
+    if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
+        return llvm_type_contains_pointer(ctx, vector.elem_type());
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+        return struct_ty
+            .fields()
+            .any(|field| llvm_type_contains_pointer(ctx, field));
+    }
+    false
+}
+
+/// One pointer-valued leaf in an LLVM aggregate's physical storage.
+///
+/// Offsets are absolute within the enclosing enum. Keeping the address space
+/// in the identity prevents an AS0 pointer carrier from being treated as the
+/// same storage as an AS1 payload pointer merely because both are eight bytes.
+#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord)]
+pub(super) struct LlvmPointerStorage {
+    pub(super) offset: u64,
+    pub(super) size: u64,
+    pub(super) address_space: u32,
+}
+
+/// Why a pointer-storage walk refused a type or an overlap.
+///
+/// Distinguishing bounded array expansion from genuine provenance loss keeps
+/// the user-facing diagnostic specific: an oversized pointer array reports the
+/// same "rewrite requires N pointer conversions" contract as the payload
+/// storage gate instead of a misleading provenance error.
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub(super) enum PointerOverlapRejection {
+    /// Expanding the walked type's fixed arrays into per-leaf records would
+    /// exceed [`MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES`]; `required` is the
+    /// total number of array-expanded pointer leaves.
+    OverArrayLeafBound { required: u64 },
+    /// The type holds pointer storage this walk cannot represent, or the
+    /// overlap would pun a pointer against non-matching bytes.
+    ProvenanceLoss,
+}
+
+/// Total pointer leaves in `ty`, through arrays and structs, with checked
+/// arithmetic. Pointer vectors count zero; every walk that expands leaves
+/// fails closed on them separately.
+fn count_pointer_leaves(ctx: &Context, ty: TypeHandle) -> Option<u64> {
+    let ty_ref = ty.deref(ctx);
+    if ty_ref.is::<llvm_types::PointerType>() {
+        return Some(1);
+    }
+    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+        return count_pointer_leaves(ctx, array.elem_type())?.checked_mul(array.size());
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+        let fields: Vec<_> = struct_ty.fields().collect();
+        let mut total = 0u64;
+        for field in fields {
+            total = total.checked_add(count_pointer_leaves(ctx, field)?)?;
+        }
+        return Some(total);
+    }
+    Some(0)
+}
+
+/// Pointer leaves that expanding `ty`'s fixed arrays contributes to a
+/// pointer-storage walk.
+///
+/// Leaves outside arrays are proportional to the source text and stay
+/// unbounded, exactly like struct nesting in `enum_payload_storage_type`.
+/// `[&T; N]` expands from three tokens into `N` records, so only
+/// array-expanded leaves count against
+/// [`MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES`].
+fn count_array_pointer_leaves(ctx: &Context, ty: TypeHandle) -> Option<u64> {
+    let ty_ref = ty.deref(ctx);
+    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+        return count_pointer_leaves(ctx, array.elem_type())?.checked_mul(array.size());
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+        let fields: Vec<_> = struct_ty.fields().collect();
+        let mut total = 0u64;
+        for field in fields {
+            total = total.checked_add(count_array_pointer_leaves(ctx, field)?)?;
+        }
+        return Some(total);
+    }
+    Some(0)
+}
+
+/// Record every pointer-valued leaf in `ty` at its natural LLVM byte offset.
+///
+/// This is deliberately a physical-layout walk rather than a simple
+/// `contains_pointer` predicate. A niche carrier may be one field inside an
+/// aggregate payload, for example the pointer at byte 8 in
+/// `Option<(usize, &T)>`. In that case the aggregate and the carrier overlap,
+/// but they agree exactly about which bytes hold the pointer.
+///
+/// Expanding an arbitrary array into one record per pointer would let a valid
+/// but enormous type consume unbounded verifier memory, so the walk first
+/// counts the array-expanded leaves and refuses anything over
+/// [`MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES`] with the bound-specific
+/// rejection before allocating a single record.
+fn collect_llvm_pointer_storage(
+    ctx: &Context,
+    ty: TypeHandle,
+    base_offset: u64,
+    out: &mut Vec<LlvmPointerStorage>,
+) -> std::result::Result<(), PointerOverlapRejection> {
+    fn collect(
+        ctx: &Context,
+        ty: TypeHandle,
+        base_offset: u64,
+        out: &mut Vec<LlvmPointerStorage>,
+    ) -> Option<()> {
+        let ty_ref = ty.deref(ctx);
+        if let Some(pointer) = ty_ref.downcast_ref::<llvm_types::PointerType>() {
+            let (size, _) = llvm_type_size_align(ctx, ty)?;
+            out.push(LlvmPointerStorage {
+                offset: base_offset,
+                size,
+                address_space: pointer.address_space(),
+            });
+            return Some(());
+        }
+        if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+            let element_ty = array.elem_type();
+            if !llvm_type_contains_pointer(ctx, element_ty) {
+                return Some(());
+            }
+            let (element_size, _) = llvm_type_size_align(ctx, element_ty)?;
+            for index in 0..array.size() {
+                let element_offset = element_size.checked_mul(index)?;
+                collect(
+                    ctx,
+                    element_ty,
+                    base_offset.checked_add(element_offset)?,
+                    out,
+                )?;
+            }
+            return Some(());
+        }
+        if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
+            // Pointer vectors carry vector-specific ABI alignment and cast
+            // semantics. Keep them fail-closed rather than treating them like
+            // fixed arrays.
+            return (!llvm_type_contains_pointer(ctx, vector.elem_type())).then_some(());
+        }
+        if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+            let fields: Vec<_> = struct_ty.fields().collect();
+            let packed = struct_ty.layout() == llvm_types::StructLayout::Packed;
+            let mut end = 0u64;
+            for field in fields {
+                let (field_size, field_align) = llvm_type_size_align(ctx, field)?;
+                let field_offset = if packed {
+                    end
+                } else {
+                    let field_align = field_align.max(1);
+                    let remainder = end % field_align;
+                    if remainder == 0 {
+                        end
+                    } else {
+                        end.checked_add(field_align - remainder)?
+                    }
+                };
+                collect(ctx, field, base_offset.checked_add(field_offset)?, out)?;
+                end = field_offset.checked_add(field_size)?;
+            }
+            return Some(());
+        }
+
+        // All pointer-bearing LLVM types understood by this lowering are
+        // handled above. Unknown pointer containers must fail closed.
+        (!llvm_type_contains_pointer(ctx, ty)).then_some(())
+    }
+
+    let required =
+        count_array_pointer_leaves(ctx, ty).ok_or(PointerOverlapRejection::ProvenanceLoss)?;
+    if required > MAX_ENUM_PAYLOAD_ARRAY_REWRITE_LEAVES {
+        return Err(PointerOverlapRejection::OverArrayLeafBound { required });
+    }
+    collect(ctx, ty, base_offset, out).ok_or(PointerOverlapRejection::ProvenanceLoss)
+}
+
+/// Analyze how a slotless incoming pointer-bearing field overlaps the enum's
+/// already-selected storage, and report how to back every one of its pointers
+/// with a real `ptr` slot.
+///
+/// Returns `Ok(extra)` when the field is representable without erasing any
+/// pointer's provenance: every pointer leaf that coincides with an existing
+/// claim reuses that claim, and each remaining ("extra") pointer leaf lands on
+/// bytes no other claim covers, so it can be backed by its own fresh `ptr`
+/// slot. `extra` lists exactly those leaves for the caller to add as claims.
+/// An empty `extra` is the exact-match case (e.g. `Option<(usize, &T)>`, whose
+/// single pointer already coincides with the niche carrier); a non-empty
+/// `extra` is the multi-pointer payload case (e.g. `Option<(&mut [T],
+/// &mut [T])>` from `split_at_mut_checked`, whose second slice pointer needs a
+/// slot of its own beside the carrier).
+///
+/// Returns [`PointerOverlapRejection::ProvenanceLoss`] when the field cannot
+/// be represented without punning a pointer against non-pointer bits: an
+/// existing pointer slot the incoming field does not also carry at the same
+/// offset/size/address space, or an extra pointer leaf that would overlap an
+/// existing (necessarily non-pointer) claim. That genuine pointer/integer
+/// union stays fail-closed — there is no single LLVM slot type that is both
+/// provenance-carrying and integer-exact.
+///
+/// Returns [`PointerOverlapRejection::OverArrayLeafBound`] when a walked type
+/// holds more array-expanded pointer leaves than the bounded rewrite limit,
+/// so the caller can report the bound instead of a provenance error.
+pub(super) fn analyze_pointer_overlap(
+    ctx: &Context,
+    incoming_offset: u64,
+    incoming_size: u64,
+    incoming_ty: TypeHandle,
+    colliding_claims: &[&(u64, u64, TypeHandle)],
+) -> std::result::Result<Vec<LlvmPointerStorage>, PointerOverlapRejection> {
+    use PointerOverlapRejection::ProvenanceLoss;
+
+    let incoming_end = incoming_offset
+        .checked_add(incoming_size)
+        .ok_or(ProvenanceLoss)?;
+
+    let mut incoming = Vec::new();
+    collect_llvm_pointer_storage(ctx, incoming_ty, incoming_offset, &mut incoming)?;
+
+    let mut existing = Vec::new();
+    for &&(offset, _size, claim_ty) in colliding_claims {
+        let mut regions = Vec::new();
+        collect_llvm_pointer_storage(ctx, claim_ty, offset, &mut regions)?;
+        existing.extend(regions.into_iter().filter(|region| {
+            let Some(region_end) = region.offset.checked_add(region.size) else {
+                return true;
+            };
+            region.offset < incoming_end && incoming_offset < region_end
+        }));
+    }
+
+    // Every existing pointer leaf overlapping this field must be one the field
+    // also carries at the same offset/size/address space; otherwise a pointer
+    // slot would be backed by non-matching bytes (an address-space mismatch, or
+    // a pointer claim where the field has integer bits).
+    for leaf in &existing {
+        if !incoming.contains(leaf) {
+            return Err(ProvenanceLoss);
+        }
+    }
+
+    // Each incoming pointer leaf that does not reuse an existing claim needs its
+    // own slot, and may only get one if it lands on otherwise-unclaimed bytes. A
+    // leaf overlapping a claim it did not match is a pointer/non-pointer pun and
+    // stays fail-closed.
+    let mut extra = Vec::new();
+    for leaf in &incoming {
+        if existing.contains(leaf) {
+            continue;
+        }
+        let leaf_end = leaf.offset.checked_add(leaf.size).ok_or(ProvenanceLoss)?;
+        let overlaps_claim = colliding_claims.iter().any(|&&(o, s, _)| {
+            let Some(claim_end) = o.checked_add(s) else {
+                return true;
+            };
+            o < leaf_end && leaf.offset < claim_end
+        });
+        if overlaps_claim {
+            return Err(ProvenanceLoss);
+        }
+        extra.push(*leaf);
+    }
+
+    Ok(extra)
+}
+
+pub(crate) fn llvm_type_contains_pointer_in_address_space(
+    ctx: &Context,
+    ty: TypeHandle,
+    address_space: u32,
+) -> bool {
+    let ty_ref = ty.deref(ctx);
+    if let Some(pointer) = ty_ref.downcast_ref::<llvm_types::PointerType>() {
+        return pointer.address_space() == address_space;
+    }
+    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+        return llvm_type_contains_pointer_in_address_space(ctx, array.elem_type(), address_space);
+    }
+    if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
+        return llvm_type_contains_pointer_in_address_space(ctx, vector.elem_type(), address_space);
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+        return struct_ty
+            .fields()
+            .any(|field| llvm_type_contains_pointer_in_address_space(ctx, field, address_space));
+    }
+    false
+}
+
+/// Whether a physical by-value image contains a packed struct whose bytes
+/// include a pointer in `address_space`.
+///
+/// Direct pointers in an unpacked aggregate do not trigger this predicate:
+/// their ABI can preserve address-space semantics without observing the
+/// pointer's raw storage width. A pointer nested anywhere under an LLVM packed
+/// struct does trigger it because whole-value construction/load/store/ABI
+/// traffic observes that packed physical image. This distinction keeps normal
+/// AS3 aggregate handling intact while rejecting the target-dependent packed
+/// case (modern NVVM p3:32 versus 64-bit PTX/legacy).
+pub(crate) fn llvm_packed_struct_contains_pointer_in_address_space(
+    ctx: &Context,
+    ty: TypeHandle,
+    address_space: u32,
+) -> bool {
+    let ty_ref = ty.deref(ctx);
+    if let Some(array) = ty_ref.downcast_ref::<llvm_types::ArrayType>() {
+        return llvm_packed_struct_contains_pointer_in_address_space(
+            ctx,
+            array.elem_type(),
+            address_space,
+        );
+    }
+    if let Some(vector) = ty_ref.downcast_ref::<llvm_types::VectorType>() {
+        return llvm_packed_struct_contains_pointer_in_address_space(
+            ctx,
+            vector.elem_type(),
+            address_space,
+        );
+    }
+    if let Some(struct_ty) = ty_ref.downcast_ref::<llvm_types::StructType>() {
+        let fields: Vec<_> = struct_ty.fields().collect();
+        if struct_ty.layout() == llvm_types::StructLayout::Packed
+            && fields
+                .iter()
+                .copied()
+                .any(|field| llvm_type_contains_pointer_in_address_space(ctx, field, address_space))
+        {
+            return true;
+        }
+        return fields.into_iter().any(|field| {
+            llvm_packed_struct_contains_pointer_in_address_space(ctx, field, address_space)
+        });
+    }
+    false
+}
diff --git a/crates/mir-lower/src/convert/types/struct_layout.rs b/crates/mir-lower/src/convert/types/struct_layout.rs
new file mode 100644
index 0000000000..d477a60130
--- /dev/null
+++ b/crates/mir-lower/src/convert/types/struct_layout.rs
@@ -0,0 +1,619 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Struct slot mapping: `StructLayoutInfo`, `StructSlotMap`, and
+//! `build_struct_slot_map` (single source of truth, issue #128).
+
+use dialect_mir::types::{MirStructType, MirTupleType};
+use llvm_export::types as llvm_types;
+use pliron::context::Context;
+use pliron::r#type::TypeHandle;
+
+use super::layout::{make_padding_type, mir_stored_size, natural_layout_walk};
+use super::{convert_type, is_zero_sized_type, llvm_type_size_align};
+
+// =============================================================================
+// Struct Slot Mapping (single source of truth, issue #128)
+// =============================================================================
+
+/// Declaration-order layout facts for one MIR aggregate, in the exact form
+/// [`build_struct_slot_map`] consumes.
+///
+/// Extracting this owned carrier first (and dropping the `Ref` returned by
+/// `Ptr::deref`) keeps the borrow checker happy: the slot-map build needs
+/// `&mut Context` for type interning.
+pub(crate) struct StructLayoutInfo {
+    /// Field types in declaration order.
+    pub field_types: Vec<TypeHandle>,
+    /// Memory order: `mem_to_decl[mem_idx] = decl_idx`. Always full length
+    /// (identity when rustc did not reorder).
+    pub mem_to_decl: Vec<usize>,
+    /// Byte offset of each field in declaration order; empty when rustc
+    /// layout is unknown.
+    pub field_offsets: Vec<u64>,
+    /// Total size in bytes including trailing padding; 0 when unknown.
+    pub total_size: u64,
+}
+
+impl StructLayoutInfo {
+    /// Layout facts of a `MirStructType`.
+    pub(crate) fn of_struct(s: &MirStructType) -> Self {
+        StructLayoutInfo {
+            field_types: s.field_types.clone(),
+            mem_to_decl: s.memory_order(),
+            field_offsets: s.field_offsets().to_vec(),
+            total_size: s.total_size(),
+        }
+    }
+
+    /// Layout facts of a `MirTupleType`.
+    ///
+    /// Tuples translated from a rustc type carry rustc's exact layout
+    /// (offsets, memory order, size), which is consumed here identically to
+    /// structs, so reordered tuples like `(u32, &T)` lower byte-correctly.
+    /// Only synthetic layout-less tuples (the unit tuple, hand-built test
+    /// types) fall back to LLVM natural layout.
+    pub(crate) fn of_tuple(t: &MirTupleType) -> Self {
+        StructLayoutInfo {
+            field_types: t.get_types().to_vec(),
+            mem_to_decl: t.memory_order(),
+            field_offsets: t.field_offsets().to_vec(),
+            total_size: t.total_size(),
+        }
+    }
+}
+
+/// One lowered LLVM struct plus the value-level slot mapping into it.
+///
+/// [`build_struct_slot_map`] produces the struct type and the index map in
+/// the same walk, so every op that indexes into the struct (`insertvalue`,
+/// `extractvalue`, GEP, call-boundary flatten/reconstruct) shares the type
+/// converter's view of where each field landed. Computing the indices
+/// separately is how the issue #128 class of bug (indices that ignore the
+/// `[N x i8]` padding slots) happened.
+pub(crate) struct StructSlotMap {
+    /// The final LLVM struct type, including any `[N x i8]` padding slots.
+    pub llvm_struct_ty: TypeHandle,
+    /// `decl_to_llvm[decl_idx]` = LLVM slot of that declaration-order field;
+    /// `None` when the field is zero-sized and was stripped.
+    pub decl_to_llvm: Vec<Option<u32>>,
+    /// Converted LLVM type of each declaration-order field (ZSTs included).
+    pub field_llvm_types: Vec<TypeHandle>,
+    /// Natural (non-packed) LLVM byte offset of every slot of
+    /// `llvm_struct_ty`, padding slots included; `None` when some field type
+    /// cannot be sized ([`llvm_type_size_align`] declined).
+    pub natural_slot_offsets: Option<Vec<u64>>,
+    /// True when rustc's recorded byte layout cannot be represented by a
+    /// naturally laid-out LLVM struct: some field's natural slot offset differs
+    /// from rustc's byte offset, or the natural struct size differs from
+    /// rustc's total size. `repr(packed)` is the canonical case. Address-path
+    /// consumers retain this signal and the natural offsets so the #859
+    /// byte-GEP fallback stays stable for packed field projections.
+    pub layout_diverges: bool,
+    /// True when the selected LLVM struct representation reproduces rustc's
+    /// recorded field offsets and total size for by-value movement. Natural
+    /// layouts are faithful when they do not diverge; divergent layouts are
+    /// faithful only when a sequential LLVM packed struct can express them.
+    /// Overlapping/union-like legacy struct models therefore remain false.
+    pub by_value_layout_faithful: bool,
+}
+
+/// Whether a `MirStructType` value lowers to a byte-faithful LLVM struct:
+/// either its natural LLVM layout already matches rustc's offsets and total
+/// size, or the packed-with-explicit-padding representation reproduces them
+/// exactly.
+///
+/// Public only as a coupling oracle for mir-importer: its constant-promotion
+/// gate must never admit a struct layout whose converted storage falls back
+/// to a divergent natural layout, because a promoted constant's byte image
+/// would then disagree with every typed read through the converted struct.
+/// mir-importer asserts agreement against this function in its tests.
+pub fn struct_value_lowering_is_byte_faithful(
+    ctx: &mut Context,
+    struct_ty: TypeHandle,
+) -> Result<bool, anyhow::Error> {
+    let layout = {
+        let ty_ref = struct_ty.deref(ctx);
+        let mir_struct = ty_ref
+            .downcast_ref::<MirStructType>()
+            .ok_or_else(|| anyhow::anyhow!("expected a MirStructType"))?;
+        StructLayoutInfo::of_struct(mir_struct)
+    };
+    Ok(build_struct_slot_map(ctx, &layout)?.by_value_layout_faithful)
+}
+
+/// Lower a struct/tuple layout to its LLVM struct type and slot map.
+///
+/// When rustc layout is present (`field_offsets` non-empty and
+/// `total_size > 0`), fields are placed at their exact byte offsets with
+/// explicit `[N x i8]` padding slots in between, plus a trailing pad up to
+/// `total_size`. This makes the layout independent of LLVM's datalayout
+/// and so ABI-identical to what rustc computed on the host. For
+/// `struct Extreme { a: u8, b: i128 }` where rustc puts `b` at offset 0
+/// and `a` at offset 16 with total size 32, we build:
+///
+/// ```text
+/// { i128, i8, [15 x i8] }   ; slots:  b = 0, a = 1, pad = 2
+/// ```
+///
+/// Without rustc layout, fields are emitted in memory order with no
+/// padding. On both paths zero-sized fields (e.g. `PhantomData`) are
+/// stripped, because NVPTX rejects empty types; stripped fields get
+/// `None` in `decl_to_llvm`.
+///
+/// Malformed layout metadata (a `mem_to_decl` that is not a permutation,
+/// or an offsets vector of the wrong length) is rejected loudly: guessing
+/// here would scramble every downstream field access.
+pub(crate) fn build_struct_slot_map(
+    ctx: &mut Context,
+    layout: &StructLayoutInfo,
+) -> Result<StructSlotMap, anyhow::Error> {
+    let num_fields = layout.field_types.len();
+
+    if layout.mem_to_decl.len() != num_fields {
+        return Err(anyhow::anyhow!(
+            "struct slot map: memory order has {} entries but the struct has {} fields",
+            layout.mem_to_decl.len(),
+            num_fields
+        ));
+    }
+    let mut seen = vec![false; num_fields];
+    for &decl_idx in &layout.mem_to_decl {
+        if decl_idx >= num_fields || seen[decl_idx] {
+            return Err(anyhow::anyhow!(
+                "struct slot map: memory order {:?} is not a permutation of 0..{}",
+                layout.mem_to_decl,
+                num_fields
+            ));
+        }
+        seen[decl_idx] = true;
+    }
+    let has_explicit_layout = !layout.field_offsets.is_empty() && layout.total_size > 0;
+    if has_explicit_layout && layout.field_offsets.len() != num_fields {
+        return Err(anyhow::anyhow!(
+            "struct slot map: {} field offsets for {} fields",
+            layout.field_offsets.len(),
+            num_fields
+        ));
+    }
+
+    // Convert every field up front, in declaration order.
+    let mut field_llvm_types = Vec::with_capacity(num_fields);
+    for &field_ty in &layout.field_types {
+        field_llvm_types.push(convert_type(ctx, field_ty)?);
+    }
+
+    let mut llvm_fields: Vec<TypeHandle> = Vec::new();
+    let mut decl_to_llvm: Vec<Option<u32>> = vec![None; num_fields];
+    let mut current_offset: u64 = 0;
+
+    // Place fields in memory order.
+    for &decl_idx in &layout.mem_to_decl {
+        let llvm_ty = field_llvm_types[decl_idx];
+
+        // ZST fields are stripped: no slot, no offset advance (rustc gives
+        // them size 0).
+        if is_zero_sized_type(ctx, llvm_ty) {
+            continue;
+        }
+
+        if has_explicit_layout {
+            // Insert padding if needed to reach the rustc field offset.
+            let target_offset = layout.field_offsets[decl_idx];
+            if current_offset < target_offset {
+                let padding_ty = make_padding_type(ctx, target_offset - current_offset);
+                llvm_fields.push(padding_ty);
+                current_offset = target_offset;
+            }
+        }
+
+        decl_to_llvm[decl_idx] = Some(llvm_fields.len() as u32);
+        llvm_fields.push(llvm_ty);
+
+        if has_explicit_layout {
+            // Offset advance is exact or an error, never guessed. Prefer
+            // rustc's stored size for the field: nested aggregates carry
+            // interior/trailing padding the converted type cannot always
+            // reproduce, and a wrong advance here either forces interior
+            // padding where rustc has none or overshoots the next field's
+            // offset. Scalars and other rustc-silent types fall back to the
+            // LLVM natural size.
+            let advance = match mir_stored_size(ctx, layout.field_types[decl_idx]) {
+                Some(size) => size,
+                None => llvm_type_size_align(ctx, llvm_ty)
+                    .map(|(size, _)| size)
+                    .ok_or_else(|| {
+                        anyhow::anyhow!(
+                            "struct slot map: field {decl_idx} lowers to `{}`, which has no \
+                             exact size; refusing to guess the next field offset",
+                            llvm_ty.deref(ctx).disp(ctx)
+                        )
+                    })?,
+            };
+            current_offset += advance;
+        }
+    }
+
+    // Add trailing padding to reach total_size.
+    if has_explicit_layout && current_offset < layout.total_size {
+        let padding_ty = make_padding_type(ctx, layout.total_size - current_offset);
+        llvm_fields.push(padding_ty);
+    }
+
+    // The explicit `[N x i8]` gaps above can only ADD bytes; they cannot make
+    // LLVM place a slot earlier than its natural alignment allows. So when
+    // rustc's layout is tighter than natural (repr(packed)), the struct built
+    // here is a lie at the byte level, and every consumer needs to know.
+    // Unsizable field types leave no verdict: consumers that need the
+    // comparison (field_addr with a recorded rustc offset) fail closed at
+    // their own sites.
+    let walk = natural_layout_walk(ctx, &llvm_fields);
+    let natural_slot_offsets = walk.as_ref().map(|(offsets, _, _)| offsets.clone());
+    let mut layout_diverges = false;
+    if has_explicit_layout && let Some((offsets, end, align)) = &walk {
+        for (decl_idx, slot) in decl_to_llvm.iter().enumerate() {
+            if let Some(slot) = slot
+                && offsets[*slot as usize] != layout.field_offsets[decl_idx]
+            {
+                layout_diverges = true;
+            }
+        }
+        let natural_size = end.div_ceil(*align) * *align;
+        if natural_size != layout.total_size {
+            layout_diverges = true;
+        }
+    }
+
+    // A packed LLVM struct is sequential with alignment 1. That faithfully
+    // represents repr(packed) only when the sequential packed offsets and
+    // final byte count exactly match rustc's metadata. A divergent layout can
+    // also be an old union-like/overlapping model; selecting Packed for such a
+    // shape would merely turn one incorrect sequential layout into another.
+    let packed_walk = if layout_diverges && has_explicit_layout {
+        let mut offsets = Vec::with_capacity(llvm_fields.len());
+        let mut end = 0u64;
+        let mut sizeable = true;
+        for &field in &llvm_fields {
+            offsets.push(end);
+            let Some((field_size, _)) = llvm_type_size_align(ctx, field) else {
+                sizeable = false;
+                break;
+            };
+            let Some(next) = end.checked_add(field_size) else {
+                sizeable = false;
+                break;
+            };
+            end = next;
+        }
+        sizeable.then_some((offsets, end))
+    } else {
+        None
+    };
+    let packed_representable = packed_walk.as_ref().is_some_and(|(offsets, end)| {
+        *end == layout.total_size
+            && decl_to_llvm
+                .iter()
+                .enumerate()
+                .all(|(decl_idx, slot)| match slot {
+                    Some(slot) => offsets[*slot as usize] == layout.field_offsets[decl_idx],
+                    None => true,
+                })
+    });
+
+    let struct_layout = if packed_representable {
+        llvm_types::StructLayout::Packed
+    } else {
+        llvm_types::StructLayout::Unpacked
+    };
+    let llvm_struct_ty: TypeHandle =
+        llvm_types::StructType::get_unnamed(ctx, (llvm_fields, struct_layout)).into();
+    let by_value_layout_faithful = !layout_diverges || packed_representable;
+
+    Ok(StructSlotMap {
+        llvm_struct_ty,
+        decl_to_llvm,
+        field_llvm_types,
+        natural_slot_offsets,
+        layout_diverges,
+        by_value_layout_faithful,
+    })
+}
+
+#[cfg(test)]
+mod tests {
+    //! Hardware-free unit tests for [`build_struct_slot_map`]: the slot map
+    //! and the LLVM struct type are produced by the same walk, so these
+    //! tests pin down both for the layout shapes from issue #128.
+
+    use super::super::test_support::{llvm_int, make_ctx, mir_uint, mir_zst, pad, struct_fields};
+    use super::*;
+    use dialect_mir::types::{EnumVariant, MirEnumType};
+
+    #[test]
+    fn slot_map_reorder_only() {
+        let mut ctx = make_ctx();
+        // struct { a: u8, b: u64 }, memory order [b, a], no rustc offsets.
+        let a = mir_uint(&mut ctx, 8);
+        let b = mir_uint(&mut ctx, 64);
+        let layout = StructLayoutInfo {
+            field_types: vec![a, b],
+            mem_to_decl: vec![1, 0],
+            field_offsets: vec![],
+            total_size: 0,
+        };
+        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
+
+        assert_eq!(map.decl_to_llvm, vec![Some(1), Some(0)]);
+        let i8s = llvm_int(&mut ctx, 8);
+        let i64s = llvm_int(&mut ctx, 64);
+        assert_eq!(struct_fields(&ctx, map.llvm_struct_ty), vec![i64s, i8s]);
+    }
+
+    #[test]
+    fn slot_map_padding_only() {
+        let mut ctx = make_ctx();
+        // struct { a: u8 @ 0, b: u64 @ 8 }, declaration order == memory
+        // order, size 16: lowers to { i8, [7 x i8], i64 }. The pad consumes
+        // slot 1, so b lands at slot 2 (the issue #128 sites used 1).
+        let a = mir_uint(&mut ctx, 8);
+        let b = mir_uint(&mut ctx, 64);
+        let layout = StructLayoutInfo {
+            field_types: vec![a, b],
+            mem_to_decl: vec![0, 1],
+            field_offsets: vec![0, 8],
+            total_size: 16,
+        };
+        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
+
+        assert_eq!(map.decl_to_llvm, vec![Some(0), Some(2)]);
+        let i8s = llvm_int(&mut ctx, 8);
+        let i64s = llvm_int(&mut ctx, 64);
+        let pad7 = pad(&mut ctx, 7);
+        assert_eq!(
+            struct_fields(&ctx, map.llvm_struct_ty),
+            vec![i8s, pad7, i64s]
+        );
+    }
+
+    #[test]
+    fn slot_map_uses_packed_layout_when_natural_offsets_diverge() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 8);
+        let value = mir_uint(&mut ctx, 32);
+        let layout = StructLayoutInfo {
+            field_types: vec![tag, value],
+            mem_to_decl: vec![0, 1],
+            field_offsets: vec![0, 1],
+            total_size: 5,
+        };
+
+        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
+
+        assert!(map.layout_diverges);
+        assert_eq!(map.decl_to_llvm, vec![Some(0), Some(1)]);
+        let llvm_struct_ty_ref = map.llvm_struct_ty.deref(&ctx);
+        let struct_ty = llvm_struct_ty_ref
+            .downcast_ref::<llvm_types::StructType>()
+            .expect("slot map must produce an LLVM struct");
+        assert_eq!(struct_ty.layout(), llvm_types::StructLayout::Packed);
+        assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((5, 1)));
+    }
+
+    #[test]
+    fn slot_map_packed_two_keeps_explicit_padding_slot() {
+        let mut ctx = make_ctx();
+        let tag = mir_uint(&mut ctx, 8);
+        let value = mir_uint(&mut ctx, 32);
+        let layout = StructLayoutInfo {
+            field_types: vec![tag, value],
+            mem_to_decl: vec![0, 1],
+            field_offsets: vec![0, 2],
+            total_size: 6,
+        };
+
+        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
+
+        assert!(map.layout_diverges);
+        assert_eq!(map.decl_to_llvm, vec![Some(0), Some(2)]);
+        let i8s = llvm_int(&mut ctx, 8);
+        let i32s = llvm_int(&mut ctx, 32);
+        let pad1 = pad(&mut ctx, 1);
+        assert_eq!(
+            struct_fields(&ctx, map.llvm_struct_ty),
+            vec![i8s, pad1, i32s]
+        );
+        let llvm_struct_ty_ref = map.llvm_struct_ty.deref(&ctx);
+        let struct_ty = llvm_struct_ty_ref
+            .downcast_ref::<llvm_types::StructType>()
+            .expect("slot map must produce an LLVM struct");
+        assert_eq!(struct_ty.layout(), llvm_types::StructLayout::Packed);
+        assert_eq!(llvm_type_size_align(&ctx, map.llvm_struct_ty), Some((6, 1)));
+    }
+
+    #[test]
+    fn slot_map_reorder_plus_padding() {
+        let mut ctx = make_ctx();
+        // struct { a: u8 @ 8, b: u64 @ 0 }, memory order [b, a], size 16:
+        // lowers to { i64, i8, [7 x i8] } with a trailing pad.
+        let a = mir_uint(&mut ctx, 8);
+        let b = mir_uint(&mut ctx, 64);
+        let layout = StructLayoutInfo {
+            field_types: vec![a, b],
+            mem_to_decl: vec![1, 0],
+            field_offsets: vec![8, 0],
+            total_size: 16,
+        };
+        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
+
+        assert_eq!(map.decl_to_llvm, vec![Some(1), Some(0)]);
+        let i8s = llvm_int(&mut ctx, 8);
+        let i64s = llvm_int(&mut ctx, 64);
+        let pad7 = pad(&mut ctx, 7);
+        assert_eq!(
+            struct_fields(&ctx, map.llvm_struct_ty),
+            vec![i64s, i8s, pad7]
+        );
+    }
+
+    #[test]
+    fn slot_map_zst_interleaving() {
+        let mut ctx = make_ctx();
+        // struct { a: u32 @ 0, z: PhantomData @ 4, b: u32 @ 4 }, size 8.
+        // The ZST is stripped (no slot, no pad split): { i32, i32 }.
+        let a = mir_uint(&mut ctx, 32);
+        let z = mir_zst(&mut ctx);
+        let b = mir_uint(&mut ctx, 32);
+        let layout = StructLayoutInfo {
+            field_types: vec![a, z, b],
+            mem_to_decl: vec![0, 1, 2],
+            field_offsets: vec![0, 4, 4],
+            total_size: 8,
+        };
+        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
+
+        assert_eq!(map.decl_to_llvm, vec![Some(0), None, Some(1)]);
+        let i32s = llvm_int(&mut ctx, 32);
+        assert_eq!(struct_fields(&ctx, map.llvm_struct_ty), vec![i32s, i32s]);
+    }
+
+    #[test]
+    fn slot_map_issue128_arena_shape() {
+        let mut ctx = make_ctx();
+        // The exact shape from issue #128 (examples/struct_field_layout):
+        //
+        //   enum Layout { Aos, Soa, AoSoA(u32) }          // -> { i8, i32 }
+        //   struct Arena { layout: Layout, cap: u32, stride: u32, big: u64 }
+        //
+        // rustc layout: layout @ 0 (8 bytes), big @ 8, cap @ 16,
+        // stride @ 20, size 24. The enum now carries its own explicit
+        // internal padding, so the OUTER struct needs no extra padding slot:
+        //
+        //   { { i8, [3 x i8], i32 }, i64, i32, i32 }
+        //     layout=0                  big=1 cap=2 stride=3
+        let discr = mir_uint(&mut ctx, 8);
+        let payload = mir_uint(&mut ctx, 32);
+        let layout_enum: TypeHandle = MirEnumType::get_with_layout(
+            &mut ctx,
+            "Layout".into(),
+            discr,
+            vec![0, 1, 2],
+            vec![
+                EnumVariant::unit("Aos".into()),
+                EnumVariant::unit("Soa".into()),
+                EnumVariant::new_with_layout("AoSoA".into(), vec![payload], vec![4], vec![4]),
+            ],
+            0,
+            8,
+            4,
+        )
+        .into();
+        let cap = mir_uint(&mut ctx, 32);
+        let stride = mir_uint(&mut ctx, 32);
+        let big = mir_uint(&mut ctx, 64);
+
+        let layout = StructLayoutInfo {
+            field_types: vec![layout_enum, cap, stride, big],
+            mem_to_decl: vec![0, 3, 1, 2],
+            field_offsets: vec![0, 16, 20, 8],
+            total_size: 24,
+        };
+        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
+
+        assert_eq!(
+            map.decl_to_llvm,
+            vec![Some(0), Some(2), Some(3), Some(1)],
+            "the enum's internal pad must not create an outer struct slot"
+        );
+
+        let i8s = llvm_int(&mut ctx, 8);
+        let i32s = llvm_int(&mut ctx, 32);
+        let i64s = llvm_int(&mut ctx, 64);
+        let enum_pad3 = pad(&mut ctx, 3);
+        let enum_llvm: TypeHandle = llvm_types::StructType::get_unnamed(
+            &ctx,
+            (
+                vec![i8s, enum_pad3, i32s],
+                llvm_types::StructLayout::Unpacked,
+            ),
+        )
+        .into();
+        assert_eq!(
+            struct_fields(&ctx, map.llvm_struct_ty),
+            vec![enum_llvm, i64s, i32s, i32s]
+        );
+    }
+
+    #[test]
+    fn slot_map_nested_struct_uses_stored_size() {
+        let mut ctx = make_ctx();
+        // Inner struct whose stored rustc size (16) exceeds the sum of its
+        // converted LLVM field sizes (i8 + i64 = 9, no offsets stored).
+        // The outer walk must advance by the stored 16, reaching the next
+        // field's offset exactly: NO interior pad before it.
+        let x = mir_uint(&mut ctx, 8);
+        let y = mir_uint(&mut ctx, 64);
+        let inner: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "Inner".into(),
+            vec!["x".into(), "y".into()],
+            vec![x, y],
+            vec![],
+            vec![],
+            16,
+            0,
+        )
+        .into();
+        let c = mir_uint(&mut ctx, 8);
+
+        let layout = StructLayoutInfo {
+            field_types: vec![inner, c],
+            mem_to_decl: vec![0, 1],
+            field_offsets: vec![0, 16],
+            total_size: 24,
+        };
+        let map = build_struct_slot_map(&mut ctx, &layout).unwrap();
+
+        // inner = slot 0, c = slot 1 (adjacent), trailing [7 x i8] pad.
+        assert_eq!(map.decl_to_llvm, vec![Some(0), Some(1)]);
+        let fields = struct_fields(&ctx, map.llvm_struct_ty);
+        assert_eq!(fields.len(), 3, "exactly one (trailing) pad slot");
+        let pad7 = pad(&mut ctx, 7);
+        assert_eq!(fields[2], pad7);
+    }
+
+    #[test]
+    fn slot_map_rejects_malformed_memory_order() {
+        let mut ctx = make_ctx();
+        let a = mir_uint(&mut ctx, 8);
+        let b = mir_uint(&mut ctx, 64);
+
+        // Not a permutation: decl index 0 appears twice.
+        let dup = StructLayoutInfo {
+            field_types: vec![a, b],
+            mem_to_decl: vec![0, 0],
+            field_offsets: vec![],
+            total_size: 0,
+        };
+        assert!(build_struct_slot_map(&mut ctx, &dup).is_err());
+
+        // Wrong length.
+        let short = StructLayoutInfo {
+            field_types: vec![a, b],
+            mem_to_decl: vec![0],
+            field_offsets: vec![],
+            total_size: 0,
+        };
+        assert!(build_struct_slot_map(&mut ctx, &short).is_err());
+
+        // Offsets vector length mismatch (with explicit layout engaged).
+        let bad_offsets = StructLayoutInfo {
+            field_types: vec![a, b],
+            mem_to_decl: vec![0, 1],
+            field_offsets: vec![0],
+            total_size: 16,
+        };
+        assert!(build_struct_slot_map(&mut ctx, &bad_offsets).is_err());
+    }
+}
diff --git a/crates/mir-lower/src/convert/types/test_support.rs b/crates/mir-lower/src/convert/types/test_support.rs
new file mode 100644
index 0000000000..5e47bfcb1d
--- /dev/null
+++ b/crates/mir-lower/src/convert/types/test_support.rs
@@ -0,0 +1,65 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Shared fixtures for the `types` submodule unit tests.
+
+use dialect_mir::types::{MirStructType, StructAbiKind};
+use llvm_export::types as llvm_types;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::r#type::TypeHandle;
+
+use super::layout::make_padding_type;
+
+pub(super) fn make_ctx() -> Context {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    crate::register(&mut ctx);
+    ctx
+}
+
+/// A MIR-level unsigned integer type (what the importer produces).
+pub(super) fn mir_uint(ctx: &mut Context, width: u32) -> TypeHandle {
+    IntegerType::get(ctx, width, Signedness::Unsigned).into()
+}
+
+/// A converted (signless) LLVM integer type.
+pub(super) fn llvm_int(ctx: &mut Context, width: u32) -> TypeHandle {
+    IntegerType::get(ctx, width, Signedness::Signless).into()
+}
+
+/// `[n x i8]` padding type, as `make_padding_type` builds it.
+pub(super) fn pad(ctx: &mut Context, n: u64) -> TypeHandle {
+    make_padding_type(ctx, n)
+}
+
+/// A zero-sized MIR struct (PhantomData shape).
+pub(super) fn mir_zst(ctx: &mut Context) -> TypeHandle {
+    MirStructType::get(ctx, "Phantom".into(), vec![], vec![]).into()
+}
+
+pub(super) fn struct_fields(ctx: &Context, ty: TypeHandle) -> Vec<TypeHandle> {
+    ty.deref(ctx)
+        .downcast_ref::<llvm_types::StructType>()
+        .expect("expected an LLVM struct type")
+        .fields()
+        .collect()
+}
+
+pub(super) fn transparent_u32(ctx: &mut Context, name: &str) -> TypeHandle {
+    let u32_ty = mir_uint(ctx, 32);
+    MirStructType::get_with_full_layout_and_abi(
+        ctx,
+        name.into(),
+        vec!["value".into()],
+        vec![u32_ty],
+        vec![0],
+        vec![0],
+        4,
+        4,
+        StructAbiKind::TransparentScalar,
+    )
+    .into()
+}
diff --git a/crates/mir-lower/src/convert/types/union_storage.rs b/crates/mir-lower/src/convert/types/union_storage.rs
new file mode 100644
index 0000000000..aa821690ff
--- /dev/null
+++ b/crates/mir-lower/src/convert/types/union_storage.rs
@@ -0,0 +1,276 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! Byte-exact LLVM storage for Rust unions.
+
+use dialect_mir::types::MirUnionType;
+use llvm_export::types as llvm_types;
+use pliron::builtin::types::{IntegerType, Signedness};
+use pliron::context::Context;
+use pliron::r#type::TypeHandle;
+
+use super::layout::make_padding_type;
+use super::pointer_storage::llvm_type_contains_pointer;
+use super::{convert_type, llvm_type_is_byte_faithful, llvm_type_size_align};
+
+/// Build byte-exact LLVM storage for a Rust union.
+///
+/// A union cannot be represented as an LLVM struct containing every declared
+/// field: struct fields are consecutive, while union fields all start at byte
+/// zero. We choose one byte-faithful field as the storage view and add explicit
+/// tail bytes. A zero-length integer array raises the LLVM type's natural
+/// alignment without consuming storage. Pointer-bearing fields are preferred
+/// so an ordinary union copy keeps LLVM pointer provenance.
+///
+/// NVPTX gives scalar integers natural alignments up to 16 bytes. Stronger
+/// Rust alignment is carried explicitly on memory operations because LLVM
+/// aggregate types cannot encode over-alignment; the storage type still keeps
+/// the union's exact size and therefore its array stride.
+pub(crate) fn build_union_storage_type(
+    ctx: &mut Context,
+    union_ty: &MirUnionType,
+) -> Result<TypeHandle, anyhow::Error> {
+    let size = union_ty.total_size();
+    let align = union_ty.abi_align();
+    if align == 0 || !align.is_power_of_two() {
+        return Err(anyhow::anyhow!(
+            "union `{}` has invalid ABI alignment {}",
+            union_ty.name(),
+            align
+        ));
+    }
+    if size > 0 && !size.is_multiple_of(align) {
+        return Err(anyhow::anyhow!(
+            "union `{}` size {} is not a multiple of its {}-byte ABI alignment",
+            union_ty.name(),
+            size,
+            align
+        ));
+    }
+
+    let mut fields = Vec::with_capacity(union_ty.field_count());
+    let mut pointer_carrier: Option<TypeHandle> = None;
+    for (index, &field_ty) in union_ty.field_types().iter().enumerate() {
+        let llvm_field_ty = convert_type(ctx, field_ty)?;
+        let (field_size, field_align) =
+            llvm_type_size_align(ctx, llvm_field_ty).ok_or_else(|| {
+                anyhow::anyhow!(
+                    "union `{}` field {} has unsupported LLVM size/alignment",
+                    union_ty.name(),
+                    index
+                )
+            })?;
+        if field_size > size {
+            return Err(anyhow::anyhow!(
+                "union `{}` field {} lowers to {} bytes but the union is only {} bytes",
+                union_ty.name(),
+                index,
+                field_size,
+                size
+            ));
+        }
+        if field_align > align {
+            return Err(anyhow::anyhow!(
+                "union `{}` field {} lowers with alignment {} but rustc reports union alignment {}",
+                union_ty.name(),
+                index,
+                field_align,
+                align
+            ));
+        }
+        let contains_pointer = llvm_type_contains_pointer(ctx, llvm_field_ty);
+        if contains_pointer {
+            if let Some(first) = pointer_carrier
+                && first != llvm_field_ty
+            {
+                return Err(anyhow::anyhow!(
+                    "union `{}` has pointer-bearing fields with different LLVM representations; preserving provenance for that shape is not yet supported",
+                    union_ty.name()
+                ));
+            }
+            pointer_carrier = Some(llvm_field_ty);
+        }
+        fields.push((llvm_field_ty, field_size, field_align, contains_pointer));
+    }
+
+    let storage_align = align.min(16);
+    let anchor_int = IntegerType::get(ctx, (storage_align * 8) as u32, Signedness::Signless);
+    let anchor: TypeHandle = llvm_types::ArrayType::get(ctx, anchor_int.into(), 0).into();
+    let mut storage_fields = vec![anchor];
+    if size > 0 {
+        let representative = fields
+            .iter()
+            .filter(|(ty, field_size, _, _)| {
+                *field_size > 0
+                    && llvm_type_is_byte_faithful(ctx, *ty)
+                    && (pointer_carrier.is_none() || llvm_type_contains_pointer(ctx, *ty))
+            })
+            .max_by_key(|(_, field_size, field_align, contains_pointer)| {
+                (*contains_pointer, *field_align, *field_size)
+            });
+        if let Some(representative) = representative {
+            storage_fields.push(representative.0);
+            if representative.1 < size {
+                storage_fields.push(make_padding_type(ctx, size - representative.1));
+            }
+        } else if pointer_carrier.is_some() {
+            return Err(anyhow::anyhow!(
+                "union `{}` has pointer-bearing fields but no byte-faithful pointer carrier; lowering it as raw bytes would discard pointer provenance",
+                union_ty.name()
+            ));
+        } else {
+            // Pointer-free unions may safely use raw bytes as their SSA
+            // carrier. Field loads/stores still use their declared types.
+            storage_fields.push(make_padding_type(ctx, size));
+        }
+    }
+    let storage: TypeHandle = llvm_types::StructType::get_unnamed(
+        ctx,
+        (storage_fields, llvm_types::StructLayout::Unpacked),
+    )
+    .into();
+    let (llvm_size, llvm_align) = llvm_type_size_align(ctx, storage).ok_or_else(|| {
+        anyhow::anyhow!(
+            "union `{}` storage has unsupported LLVM layout",
+            union_ty.name()
+        )
+    })?;
+    if llvm_size != size || llvm_align > align {
+        return Err(anyhow::anyhow!(
+            "union `{}` storage lowered to incompatible size/alignment {}/{} but rustc requires {}/{}",
+            union_ty.name(),
+            llvm_size,
+            llvm_align,
+            size,
+            align
+        ));
+    }
+    Ok(storage)
+}
+
+#[cfg(test)]
+mod tests {
+    use super::super::test_support::{make_ctx, mir_uint, struct_fields};
+    use super::*;
+    use dialect_mir::types::{MirArrayType, MirPtrType, MirStructType};
+
+    #[test]
+    fn union_storage_has_exact_size_alignment_and_stride() {
+        let mut ctx = make_ctx();
+        let u8_ty = mir_uint(&mut ctx, 8);
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let bytes_ty: TypeHandle = MirArrayType::get(&mut ctx, u8_ty, 4).into();
+        let union_ty = MirUnionType::get(
+            &mut ctx,
+            "Bits".into(),
+            vec!["word".into(), "bytes".into()],
+            vec![u32_ty, bytes_ty],
+            4,
+            4,
+        );
+        let union_data = union_ty.deref(&ctx).clone();
+        let storage = build_union_storage_type(&mut ctx, &union_data).unwrap();
+        assert_eq!(llvm_type_size_align(&ctx, storage), Some((4, 4)));
+
+        let union_handle: TypeHandle = union_ty.into();
+        let array: TypeHandle = MirArrayType::get(&mut ctx, union_handle, 3).into();
+        let llvm_array = convert_type(&mut ctx, array).unwrap();
+        assert_eq!(llvm_type_size_align(&ctx, llvm_array), Some((12, 4)));
+    }
+
+    #[test]
+    fn union_storage_prefers_pointer_carrier() {
+        let mut ctx = make_ctx();
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let u64_ty = mir_uint(&mut ctx, 64);
+        let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let union_ty = MirUnionType::get(
+            &mut ctx,
+            "PointerBits".into(),
+            vec!["ptr".into(), "bits".into()],
+            vec![ptr_ty, u64_ty],
+            8,
+            8,
+        );
+        let union_data = union_ty.deref(&ctx).clone();
+        let storage = build_union_storage_type(&mut ctx, &union_data).unwrap();
+        let fields = struct_fields(&ctx, storage);
+        assert!(fields[1].deref(&ctx).is::<llvm_types::PointerType>());
+        assert_eq!(llvm_type_size_align(&ctx, storage), Some((8, 8)));
+    }
+
+    #[test]
+    fn union_storage_rejects_incompatible_pointer_address_spaces() {
+        let mut ctx = make_ctx();
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let generic: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let shared: TypeHandle = MirPtrType::get_shared(&mut ctx, u32_ty, false).into();
+        let union_ty = MirUnionType::get(
+            &mut ctx,
+            "MixedPointers".into(),
+            vec!["generic".into(), "shared".into()],
+            vec![generic, shared],
+            8,
+            8,
+        );
+        let union_data = union_ty.deref(&ctx).clone();
+        let err = build_union_storage_type(&mut ctx, &union_data).unwrap_err();
+        assert!(err.to_string().contains("different LLVM representations"));
+    }
+
+    #[test]
+    fn union_storage_rejects_non_byte_faithful_pointer_carrier() {
+        let mut ctx = make_ctx();
+        let u8_ty = mir_uint(&mut ctx, 8);
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let bool_ty = mir_uint(&mut ctx, 1);
+        let ptr_ty: TypeHandle = MirPtrType::get_generic(&mut ctx, u32_ty, false).into();
+        let ptr_bool: TypeHandle = MirStructType::get_with_full_layout(
+            &mut ctx,
+            "PtrBool".into(),
+            vec!["ptr".into(), "flag".into()],
+            vec![ptr_ty, bool_ty],
+            vec![0, 1],
+            vec![0, 8],
+            16,
+            8,
+        )
+        .into();
+        let bytes_ty: TypeHandle = MirArrayType::get(&mut ctx, u8_ty, 16).into();
+        let union_ty = MirUnionType::get(
+            &mut ctx,
+            "PointerBoolBytes".into(),
+            vec!["view".into(), "bytes".into()],
+            vec![ptr_bool, bytes_ty],
+            16,
+            8,
+        );
+        let union_data = union_ty.deref(&ctx).clone();
+        let err = build_union_storage_type(&mut ctx, &union_data).unwrap_err();
+        assert!(err.to_string().contains("no byte-faithful pointer carrier"));
+    }
+
+    #[test]
+    fn union_storage_preserves_over_aligned_size_and_stride() {
+        let mut ctx = make_ctx();
+        let u32_ty = mir_uint(&mut ctx, 32);
+        let union_ty = MirUnionType::get(
+            &mut ctx,
+            "OverAligned".into(),
+            vec!["word".into()],
+            vec![u32_ty],
+            32,
+            32,
+        );
+        let union_data = union_ty.deref(&ctx).clone();
+        let storage = build_union_storage_type(&mut ctx, &union_data).unwrap();
+        assert_eq!(llvm_type_size_align(&ctx, storage), Some((32, 16)));
+
+        let union_handle: TypeHandle = union_ty.into();
+        let array: TypeHandle = MirArrayType::get(&mut ctx, union_handle, 3).into();
+        let llvm_array = convert_type(&mut ctx, array).unwrap();
+        assert_eq!(llvm_type_size_align(&ctx, llvm_array), Some((96, 16)));
+    }
+}
diff --git a/crates/mir-lower/tests/lowering_test.rs b/crates/mir-lower/tests/lowering_test.rs
deleted file mode 100644
index e393cee672..0000000000
--- a/crates/mir-lower/tests/lowering_test.rs
+++ /dev/null
@@ -1,13177 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// Tests build kinded fixture types directly; production minting lives in
-// mir-importer's facts.rs (see the workspace clippy.toml disallowed-methods).
-#![allow(clippy::disallowed_methods)]
-
-use dialect_mir::ops as mir;
-use dialect_nvvm::ops as nvvm;
-use llvm_export::ops as llvm;
-use pliron::builtin::op_interfaces::{
-    CallOpCallable, CallOpInterface, OneRegionInterface, SymbolOpInterface,
-};
-use pliron::builtin::ops::ModuleOp;
-use pliron::context::Context;
-use pliron::linked_list::ContainsLinkedList;
-use pliron::location::{Located, Location};
-use pliron::op::Op;
-use pliron::operation::Operation;
-use pliron::r#type::Typed;
-
-#[test]
-fn test_standalone_lowering_rejects_builtin_pointer_constant() {
-    use dialect_mir::types::{MirPointerKind, MirPtrType};
-    use pliron::builtin::{
-        attributes::IntegerAttr,
-        ops::ConstantOp,
-        types::{IntegerType, Signedness},
-    };
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let module = ModuleOp::new(&mut ctx, "pointer_constant".try_into().unwrap());
-    let block = module
-        .get_region(&ctx)
-        .deref(&ctx)
-        .iter(&ctx)
-        .next()
-        .unwrap();
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let pointer_ty =
-        MirPtrType::get_generic_with_kind(&mut ctx, u32_ty.into(), true, MirPointerKind::UniqueRef);
-    let value = APInt::from_u64(0, NonZeroUsize::new(32).unwrap());
-    let constant = ConstantOp::new(&mut ctx, IntegerAttr::new(u32_ty, value).into());
-    let result = constant.get_operation().deref(&ctx).get_result(0);
-    result.set_type(&ctx, pointer_ty.into());
-    constant.get_operation().insert_at_back(block, &ctx);
-
-    let error = mir_lower::lower_mir_to_llvm(&mut ctx, module.get_operation()).unwrap_err();
-    assert!(
-        error
-            .to_string()
-            .contains("builtin.constant cannot produce a MIR pointer carrier")
-    );
-}
-
-#[test]
-fn test_intrinsic_insertion() -> Result<(), anyhow::Error> {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    // Create Module
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_ptr = module.get_operation();
-
-    // Create MirFunc
-    let func_name = "kernel_func";
-    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, vec![], vec![]);
-
-    // Manual construction of MirFuncOp
-    let func_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1, // 1 region
-    );
-    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
-    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
-    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
-
-    // Add body - MirFuncOp has 1 region
-    let region = func.get_operation().deref(&ctx).get_region(0);
-
-    // Create block if empty (it is empty by default from Operation::new)
-    let block = {
-        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, vec![]);
-        b.insert_at_back(region, &ctx);
-        b
-    };
-
-    // Add ReadPtxSregTidXOp
-    let int32_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        32,
-        pliron::builtin::types::Signedness::Signless,
-    );
-
-    let tid_op_ptr = Operation::new(
-        &mut ctx,
-        nvvm::ReadPtxSregTidXOp::get_concrete_op_info(),
-        vec![int32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    let tid_op = nvvm::ReadPtxSregTidXOp::new(tid_op_ptr);
-    let expected_location = Location::Named {
-        name: "source-tid-x".to_string(),
-        child_loc: Box::new(Location::Unknown),
-    };
-    tid_op
-        .get_operation()
-        .deref_mut(&ctx)
-        .set_loc(expected_location.clone());
-    tid_op.get_operation().insert_at_back(block, &ctx);
-
-    // Add Return
-    let ret_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirReturnOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    let ret_op = mir::MirReturnOp::new(ret_op_ptr);
-    ret_op.get_operation().insert_at_back(block, &ctx);
-
-    // Add Func to Module
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    // Run DialectConversion-based lowering
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    // Verify result
-    let mut found_intrinsic = false;
-    let mut found_intrinsic_call = false;
-    let mut found_kernel = false;
-
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-
-    for op in block.deref(&ctx).iter(&ctx) {
-        if let Some(func_op) = Operation::get_op::<llvm_export::ops::FuncOp>(op, &ctx) {
-            let name = func_op.get_symbol_name(&ctx).to_string();
-            if name == "llvm_nvvm_read_ptx_sreg_tid_x" {
-                found_intrinsic = true;
-                // Intrinsic (declaration) should have 0 regions or empty region
-                let num_regions = func_op.get_operation().deref(&ctx).regions().count();
-                if num_regions > 0 {
-                    assert!(
-                        func_op
-                            .get_operation()
-                            .deref(&ctx)
-                            .get_region(0)
-                            .deref(&ctx)
-                            .iter(&ctx)
-                            .next()
-                            .is_none()
-                    );
-                }
-            } else if name == "kernel_func" {
-                found_kernel = true;
-                // Kernel should have body (1 region, not empty)
-                assert!(func_op.get_operation().deref(&ctx).regions().count() > 0);
-                assert!(
-                    func_op
-                        .get_operation()
-                        .deref(&ctx)
-                        .get_region(0)
-                        .deref(&ctx)
-                        .iter(&ctx)
-                        .next()
-                        .is_some()
-                );
-                let kernel_region = func_op.get_operation().deref(&ctx).get_region(0);
-                for kernel_block in kernel_region.deref(&ctx).iter(&ctx) {
-                    for body_op in kernel_block.deref(&ctx).iter(&ctx) {
-                        let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx) else {
-                            continue;
-                        };
-                        if matches!(
-                            call.callee(&ctx),
-                            CallOpCallable::Direct(symbol)
-                                if symbol.to_string() == "llvm_nvvm_read_ptx_sreg_tid_x"
-                        ) {
-                            found_intrinsic_call = true;
-                            assert_eq!(call.get_operation().deref(&ctx).loc(), expected_location);
-                        }
-                    }
-                }
-            }
-        }
-    }
-
-    assert!(found_intrinsic, "Intrinsic function declaration not found");
-    assert!(found_intrinsic_call, "Intrinsic call not found in kernel");
-    assert!(found_kernel, "Kernel function not found");
-
-    Ok(())
-}
-
-#[test]
-fn test_assertfail_orphaned_successor_block_is_removed() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_ptr = module.get_operation();
-
-    let func_name = "kernel_func";
-    let u8_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        8,
-        pliron::builtin::types::Signedness::Unsigned,
-    );
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
-    let u32_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        32,
-        pliron::builtin::types::Signedness::Unsigned,
-    );
-    let u64_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        64,
-        pliron::builtin::types::Signedness::Unsigned,
-    );
-    let arg_tys: Vec<pliron::r#type::TypeHandle> = vec![
-        ptr_ty.into(),
-        ptr_ty.into(),
-        u32_ty.into(),
-        ptr_ty.into(),
-        u64_ty.into(),
-    ];
-    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, arg_tys.clone(), vec![]);
-
-    let func_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
-    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
-    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
-
-    let region = func.get_operation().deref(&ctx).get_region(0);
-    let entry = {
-        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, arg_tys);
-        b.insert_at_back(region, &ctx);
-        b
-    };
-    // A block reachable only through the assert's success edge, carrying a
-    // block argument: the CFG a constant-false `gpu_assert!` leaves behind
-    // after MIR optimization folds the direct edge away.
-    let tail = {
-        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, vec![u32_ty.into()]);
-        b.insert_at_back(region, &ctx);
-        b
-    };
-
-    let message = entry.deref(&ctx).get_argument(0);
-    let file = entry.deref(&ctx).get_argument(1);
-    let line = entry.deref(&ctx).get_argument(2);
-    let function = entry.deref(&ctx).get_argument(3);
-    let char_size = entry.deref(&ctx).get_argument(4);
-
-    let assertfail_op =
-        nvvm::AssertFailOp::build(&mut ctx, message, file, line, function, char_size);
-    assertfail_op.insert_at_back(entry, &ctx);
-
-    // The success edge forwards `line` into the tail block's argument.
-    // Lowering erases this branch (the call never returns), orphaning the
-    // tail block, which then cannot be exported: a block argument needs one
-    // PHI incoming value per predecessor and there are none left.
-    let goto_op = Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![line],
-        vec![tail],
-        0,
-    );
-    goto_op.insert_at_back(entry, &ctx);
-
-    let ret_op = Operation::new(
-        &mut ctx,
-        mir::MirReturnOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    ret_op.insert_at_back(tail, &ctx);
-
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut found_kernel = false;
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != func_name {
-            continue;
-        }
-        found_kernel = true;
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        let blocks: Vec<_> = func_region.deref(&ctx).iter(&ctx).collect();
-        for block in blocks.iter().skip(1) {
-            assert!(
-                !block.preds(&ctx).is_empty(),
-                "an unreachable block survived lowering; with block arguments \
-                 it cannot be exported (a PHI needs an incoming value per \
-                 predecessor and there are none)"
-            );
-        }
-    }
-    assert!(found_kernel, "Kernel function not found");
-
-    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-    let ir =
-        llvm_export::export::export_module_to_string(&ctx, &module).map_err(anyhow::Error::msg)?;
-    let lines: Vec<_> = ir.lines().collect();
-    let call_line = lines
-        .iter()
-        .position(|line| line.contains("call void @__assertfail("))
-        .expect("expected exported __assertfail call");
-    assert_eq!(lines[call_line + 1].trim(), "unreachable", "{ir}");
-
-    Ok(())
-}
-
-#[test]
-fn test_globaltimer_lowers_to_intrinsic_call() -> Result<(), anyhow::Error> {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_ptr = module.get_operation();
-
-    let func_name = "kernel_func";
-    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, vec![], vec![]);
-
-    let func_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
-    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
-    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
-
-    let region = func.get_operation().deref(&ctx).get_region(0);
-    let block = {
-        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, vec![]);
-        b.insert_at_back(region, &ctx);
-        b
-    };
-
-    let i64_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        64,
-        pliron::builtin::types::Signedness::Signless,
-    );
-    let timer_op = Operation::new(
-        &mut ctx,
-        nvvm::ReadPtxSregGlobaltimerOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    timer_op.insert_at_back(block, &ctx);
-
-    let ret_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirReturnOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    let ret_op = mir::MirReturnOp::new(ret_op_ptr);
-    ret_op.get_operation().insert_at_back(block, &ctx);
-
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    const INTRINSIC: &str = "llvm_nvvm_read_ptx_sreg_globaltimer";
-
-    let mut found_decl = false;
-    let mut found_call = false;
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm_export::ops::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        let name = func_op.get_symbol_name(&ctx).to_string();
-
-        if name == INTRINSIC {
-            // Intrinsic declaration: present with empty body.
-            found_decl = true;
-            let num_regions = func_op.get_operation().deref(&ctx).regions().count();
-            if num_regions > 0 {
-                assert!(
-                    func_op
-                        .get_operation()
-                        .deref(&ctx)
-                        .get_region(0)
-                        .deref(&ctx)
-                        .iter(&ctx)
-                        .next()
-                        .is_none(),
-                    "intrinsic declaration must have empty body"
-                );
-            }
-        } else if name == func_name {
-            let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-            for func_block in func_region.deref(&ctx).iter(&ctx) {
-                for body_op in func_block.deref(&ctx).iter(&ctx) {
-                    if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
-                        && let CallOpCallable::Direct(sym) = call.callee(&ctx)
-                        && sym.to_string() == INTRINSIC
-                    {
-                        found_call = true;
-                    }
-                    assert!(
-                        Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx).is_none(),
-                        "globaltimer must not lower to inline asm"
-                    );
-                }
-            }
-        }
-    }
-
-    assert!(
-        found_decl,
-        "Expected `{INTRINSIC}` declaration in lowered module"
-    );
-    assert!(
-        found_call,
-        "Expected call to `{INTRINSIC}` in lowered kernel body"
-    );
-    Ok(())
-}
-
-#[test]
-fn test_assertfail_lowers_to_noreturn_call_and_unreachable() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_ptr = module.get_operation();
-
-    let func_name = "kernel_func";
-    let u8_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        8,
-        pliron::builtin::types::Signedness::Unsigned,
-    );
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
-    let u32_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        32,
-        pliron::builtin::types::Signedness::Unsigned,
-    );
-    let u64_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        64,
-        pliron::builtin::types::Signedness::Unsigned,
-    );
-    let arg_tys: Vec<pliron::r#type::TypeHandle> = vec![
-        ptr_ty.into(),
-        ptr_ty.into(),
-        u32_ty.into(),
-        ptr_ty.into(),
-        u64_ty.into(),
-    ];
-    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, arg_tys.clone(), vec![]);
-
-    let func_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
-    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
-    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
-
-    let region = func.get_operation().deref(&ctx).get_region(0);
-    let block = {
-        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, arg_tys);
-        b.insert_at_back(region, &ctx);
-        b
-    };
-
-    let message = block.deref(&ctx).get_argument(0);
-    let file = block.deref(&ctx).get_argument(1);
-    let line = block.deref(&ctx).get_argument(2);
-    let function = block.deref(&ctx).get_argument(3);
-    let char_size = block.deref(&ctx).get_argument(4);
-
-    let assertfail_op =
-        nvvm::AssertFailOp::build(&mut ctx, message, file, line, function, char_size);
-    assertfail_op.insert_at_back(block, &ctx);
-
-    // This return must be removed by lowering because __assertfail never returns.
-    let ret_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirReturnOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    ret_op_ptr.insert_at_back(block, &ctx);
-
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    const EXTERN: &str = "__assertfail";
-
-    let mut found_decl = false;
-    let mut found_call = false;
-    let mut found_unreachable = false;
-
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        let name = func_op.get_symbol_name(&ctx).to_string();
-
-        if name == EXTERN {
-            found_decl = true;
-            assert!(
-                llvm::op_noreturn(&ctx, func_op.get_operation()),
-                "__assertfail declaration must be marked noreturn"
-            );
-            continue;
-        }
-
-        if name != func_name {
-            continue;
-        }
-
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            let body_ops: Vec<_> = func_block.deref(&ctx).iter(&ctx).collect();
-
-            for (index, body_op) in body_ops.iter().copied().enumerate() {
-                if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
-                    && let CallOpCallable::Direct(sym) = call.callee(&ctx)
-                    && sym.to_string() == EXTERN
-                {
-                    found_call = true;
-
-                    assert!(
-                        llvm::op_noreturn(&ctx, body_op),
-                        "__assertfail call must be marked noreturn"
-                    );
-                    assert_eq!(
-                        body_op.deref(&ctx).get_num_operands(),
-                        5,
-                        "__assertfail call must forward all five operands"
-                    );
-                    assert!(
-                        body_ops.get(index + 1).is_some_and(|next| {
-                            Operation::get_op::<llvm::UnreachableOp>(*next, &ctx).is_some()
-                        }),
-                        "llvm.unreachable must immediately follow __assertfail"
-                    );
-                    assert_eq!(
-                        index + 2,
-                        body_ops.len(),
-                        "no operations may remain after llvm.unreachable"
-                    );
-                }
-
-                if Operation::get_op::<llvm::UnreachableOp>(body_op, &ctx).is_some() {
-                    found_unreachable = true;
-                }
-
-                assert!(
-                    Operation::get_op::<nvvm::AssertFailOp>(body_op, &ctx).is_none(),
-                    "nvvm.assertfail must be fully consumed by the lowering"
-                );
-            }
-        }
-    }
-
-    assert!(
-        found_decl,
-        "Expected `{EXTERN}` declaration in lowered module"
-    );
-    assert!(
-        found_call,
-        "Expected call to `{EXTERN}` in lowered kernel body"
-    );
-    assert!(
-        found_unreachable,
-        "__assertfail must terminate the block with llvm.unreachable"
-    );
-
-    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-    let ir =
-        llvm_export::export::export_module_to_string(&ctx, &module).map_err(anyhow::Error::msg)?;
-
-    let declaration = ir
-        .lines()
-        .find(|line| line.contains("declare void @__assertfail("))
-        .expect("expected exported __assertfail declaration");
-    assert!(declaration.contains("noreturn"), "{ir}");
-
-    let lines: Vec<_> = ir.lines().collect();
-    let call_line = lines
-        .iter()
-        .position(|line| line.contains("call void @__assertfail("))
-        .expect("expected exported __assertfail call");
-    assert!(lines[call_line].contains("noreturn"), "{ir}");
-    assert_eq!(lines[call_line + 1].trim(), "unreachable", "{ir}");
-
-    Ok(())
-}
-
-/// Lower a single zero-operand, i32-result special-register op and assert it
-/// emits a declaration of and direct call to `intrinsic` (and no inline asm).
-fn assert_sreg_i32_lowers_to_intrinsic(
-    op_info: (
-        fn(pliron::context::Ptr<pliron::operation::Operation>) -> pliron::op::OpObj,
-        std::any::TypeId,
-    ),
-    intrinsic: &str,
-) -> Result<(), anyhow::Error> {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_ptr = module.get_operation();
-
-    let func_name = "kernel_func";
-    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, vec![], vec![]);
-
-    let func_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
-    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
-    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
-
-    let region = func.get_operation().deref(&ctx).get_region(0);
-    let block = {
-        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, vec![]);
-        b.insert_at_back(region, &ctx);
-        b
-    };
-
-    let i32_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        32,
-        pliron::builtin::types::Signedness::Signless,
-    );
-    let sreg_op = Operation::new(&mut ctx, op_info, vec![i32_ty.into()], vec![], vec![], 0);
-    sreg_op.insert_at_back(block, &ctx);
-
-    let ret_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirReturnOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    let ret_op = mir::MirReturnOp::new(ret_op_ptr);
-    ret_op.get_operation().insert_at_back(block, &ctx);
-
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    let mut found_decl = false;
-    let mut found_call = false;
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm_export::ops::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        let name = func_op.get_symbol_name(&ctx).to_string();
-
-        if name == intrinsic {
-            found_decl = true;
-        } else if name == func_name {
-            let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-            for func_block in func_region.deref(&ctx).iter(&ctx) {
-                for body_op in func_block.deref(&ctx).iter(&ctx) {
-                    if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
-                        && let CallOpCallable::Direct(sym) = call.callee(&ctx)
-                        && sym.to_string() == intrinsic
-                    {
-                        found_call = true;
-                    }
-                    assert!(
-                        Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx).is_none(),
-                        "{intrinsic} must not lower to inline asm"
-                    );
-                }
-            }
-        }
-    }
-
-    assert!(
-        found_decl,
-        "Expected `{intrinsic}` declaration in lowered module"
-    );
-    assert!(
-        found_call,
-        "Expected call to `{intrinsic}` in lowered kernel body"
-    );
-    Ok(())
-}
-
-fn assert_sreg_lowers_to_inline_asm(
-    op_info: (
-        fn(pliron::context::Ptr<Operation>) -> pliron::op::OpObj,
-        std::any::TypeId,
-    ),
-    result_width: u32,
-    expected_template: &str,
-    expected_constraints: &str,
-    expected_kind: llvm::AsmKind,
-) -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let result_ty = IntegerType::get(&ctx, result_width, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
-    let sreg_op = Operation::new(&mut ctx, op_info, vec![result_ty.into()], vec![], vec![], 0);
-    sreg_op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut matches = 0usize;
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = inline_asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                if template.as_deref() != Some(expected_template) {
-                    continue;
-                }
-
-                matches += 1;
-                assert_eq!(
-                    inline_asm
-                        .get_attr_inline_asm_constraints(&ctx)
-                        .map(|value| String::from((*value).clone()))
-                        .as_deref(),
-                    Some(expected_constraints)
-                );
-                assert_eq!(llvm::asm_kind(&ctx, &inline_asm), expected_kind);
-            }
-        }
-    }
-
-    assert_eq!(matches, 1, "expected one exact `{expected_template}` read");
-    Ok(())
-}
-
-#[test]
-fn test_lanemask_ops_lower_to_sreg_intrinsic_calls() -> Result<(), anyhow::Error> {
-    // Each lane-position mask op lowers to its matching read-only sreg intrinsic
-    // (underscores become dots on export: `..._lanemask_lt` -> `...lanemask.lt`).
-    assert_sreg_i32_lowers_to_intrinsic(
-        nvvm::ReadPtxSregLanemaskLtOp::get_concrete_op_info(),
-        "llvm_nvvm_read_ptx_sreg_lanemask_lt",
-    )?;
-    assert_sreg_i32_lowers_to_intrinsic(
-        nvvm::ReadPtxSregLanemaskLeOp::get_concrete_op_info(),
-        "llvm_nvvm_read_ptx_sreg_lanemask_le",
-    )?;
-    assert_sreg_i32_lowers_to_intrinsic(
-        nvvm::ReadPtxSregLanemaskEqOp::get_concrete_op_info(),
-        "llvm_nvvm_read_ptx_sreg_lanemask_eq",
-    )?;
-    assert_sreg_i32_lowers_to_intrinsic(
-        nvvm::ReadPtxSregLanemaskGeOp::get_concrete_op_info(),
-        "llvm_nvvm_read_ptx_sreg_lanemask_ge",
-    )?;
-    assert_sreg_i32_lowers_to_intrinsic(
-        nvvm::ReadPtxSregLanemaskGtOp::get_concrete_op_info(),
-        "llvm_nvvm_read_ptx_sreg_lanemask_gt",
-    )?;
-    Ok(())
-}
-
-#[test]
-fn test_generated_vote_sync_family_lowers_to_exact_typed_intrinsics() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::r#type::Typed;
-
-    let mut ctx = make_test_ctx();
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into(), i1_ty.into()]);
-    let mask = entry.deref(&ctx).get_argument(0);
-    let predicate = entry.deref(&ctx).get_argument(1);
-
-    for vote in [
-        nvvm::VoteSyncAllOp::build(&mut ctx, mask, predicate),
-        nvvm::VoteSyncAnyOp::build(&mut ctx, mask, predicate),
-        nvvm::VoteSyncBallotOp::build(&mut ctx, mask, predicate),
-        nvvm::VoteSyncUniOp::build(&mut ctx, mask, predicate),
-    ] {
-        vote.insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let expected = [
-        ("llvm_nvvm_vote_all_sync", 1),
-        ("llvm_nvvm_vote_any_sync", 1),
-        ("llvm_nvvm_vote_ballot_sync", 32),
-        ("llvm_nvvm_vote_uni_sync", 1),
-    ];
-    let mut found = Vec::new();
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        assert!(
-            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-            "generated vote.sync operations must use typed LLVM intrinsics"
-        );
-        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-            continue;
-        };
-        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-            continue;
-        };
-        let callee = callee.to_string();
-        let Some((_, result_width)) = expected.iter().find(|(name, _)| *name == callee) else {
-            continue;
-        };
-
-        let call = call.get_operation().deref(&ctx);
-        assert_eq!(call.get_num_operands(), 2);
-        assert_eq!(call.get_num_results(), 1);
-
-        let integer_shape = |value: pliron::value::Value| {
-            let ty = value.get_type(&ctx);
-            let ty = ty.deref(&ctx);
-            let integer = ty
-                .downcast_ref::<IntegerType>()
-                .expect("vote.sync operands and results are integers");
-            (integer.width(), integer.signedness())
-        };
-        assert_eq!(
-            [
-                integer_shape(call.get_operand(0)),
-                integer_shape(call.get_operand(1)),
-            ],
-            [(32, Signedness::Signless), (1, Signedness::Signless),],
-            "{callee} must preserve [mask, predicate] operand order"
-        );
-        assert_eq!(
-            integer_shape(call.get_result(0)),
-            (*result_width, Signedness::Signless),
-            "{callee} returned the wrong LLVM integer type"
-        );
-        found.push((callee, *result_width));
-    }
-
-    found.sort();
-    let mut expected = expected
-        .map(|(name, width)| (name.to_owned(), width))
-        .to_vec();
-    expected.sort();
-    assert_eq!(found, expected);
-    Ok(())
-}
-
-fn lower_generated_active_mask(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
-    nvvm::ActiveMaskOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn test_generated_active_mask_llvm_nvptx_uses_typed_intrinsic() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::IntegerType;
-    use pliron::r#type::Typed;
-
-    let (ctx, module_ptr) = lower_generated_active_mask(mir_lower::IntrinsicBackend::LlvmNvptx)?;
-    let mut found = 0;
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        assert!(
-            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-            "LLVM-NVPTX active_mask must use the typed intrinsic"
-        );
-        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-            continue;
-        };
-        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-            continue;
-        };
-        if callee.to_string() != "llvm_nvvm_activemask" {
-            continue;
-        }
-
-        found += 1;
-        let call = op.deref(&ctx);
-        assert_eq!(call.get_num_operands(), 0);
-        assert_eq!(call.get_num_results(), 1);
-        let result_ty = call.get_result(0).get_type(&ctx);
-        let result_ty = result_ty.deref(&ctx);
-        let result_ty = result_ty
-            .downcast_ref::<IntegerType>()
-            .expect("active_mask returns an integer");
-        assert_eq!(result_ty.width(), 32);
-    }
-    assert_eq!(found, 1, "expected one typed active_mask call");
-
-    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-        .map_err(|error| anyhow::anyhow!(error))?;
-    assert!(ir.contains("call i32 @llvm.nvvm.activemask()"), "{ir}");
-    Ok(())
-}
-
-#[test]
-fn test_generated_active_mask_libnvvm_uses_convergent_sideeffect_asm() -> Result<(), anyhow::Error>
-{
-    use pliron::builtin::types::IntegerType;
-    use pliron::r#type::Typed;
-
-    let (ctx, module_ptr) = lower_generated_active_mask(mir_lower::IntrinsicBackend::LibNvvm)?;
-    let mut found = 0;
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-        {
-            assert_ne!(callee.to_string(), "llvm_nvvm_activemask");
-        }
-        let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            continue;
-        };
-
-        found += 1;
-        assert_eq!(
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some("activemask.b32 $0;")
-        );
-        assert_eq!(
-            asm.get_attr_inline_asm_constraints(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some("=r,~{memory}")
-        );
-        assert_eq!(llvm::asm_kind(&ctx, &asm), llvm::AsmKind::Convergent);
-        assert!(
-            asm.get_attr_inline_asm_convergent(&ctx)
-                .is_some_and(|value| bool::from((*value).clone()))
-        );
-        let asm = op.deref(&ctx);
-        assert_eq!(asm.get_num_operands(), 0);
-        assert_eq!(asm.get_num_results(), 1);
-        let result_ty = asm.get_result(0).get_type(&ctx);
-        let result_ty = result_ty.deref(&ctx);
-        let result_ty = result_ty
-            .downcast_ref::<IntegerType>()
-            .expect("active_mask inline asm returns an integer");
-        assert_eq!(result_ty.width(), 32);
-    }
-    assert_eq!(found, 1, "expected one exact active_mask asm block");
-
-    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-        .map_err(|error| anyhow::anyhow!(error))?;
-    assert!(
-        ir.contains("call i32 asm sideeffect \"activemask.b32 $0;\", \"=r,~{memory}\"()"),
-        "{ir}"
-    );
-    assert!(ir.contains("attributes #0 = { convergent }"), "{ir}");
-    Ok(())
-}
-
-#[test]
-fn test_generated_warp_match_family_uses_exact_typed_calls_and_mask_projection()
--> Result<(), anyhow::Error> {
-    use llvm_export::types::StructType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::r#type::Typed;
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![i32_ty.into(), i32_ty.into(), i64_ty.into()]);
-    let mask = entry.deref(&ctx).get_argument(0);
-    let value32 = entry.deref(&ctx).get_argument(1);
-    let value64 = entry.deref(&ctx).get_argument(2);
-    for warp_match in [
-        nvvm::MatchAnySyncI32Op::build(&mut ctx, mask, value32),
-        nvvm::MatchAnySyncI64Op::build(&mut ctx, mask, value64),
-        nvvm::MatchAllSyncI32Op::build(&mut ctx, mask, value32),
-        nvvm::MatchAllSyncI64Op::build(&mut ctx, mask, value64),
-    ] {
-        warp_match.insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: mir_lower::IntrinsicBackend::LlvmNvptx,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let expected = [
-        ("llvm_nvvm_match_any_sync_i32", 32, false),
-        ("llvm_nvvm_match_any_sync_i64", 64, false),
-        ("llvm_nvvm_match_all_sync_i32p", 32, true),
-        ("llvm_nvvm_match_all_sync_i64p", 64, true),
-    ];
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let integer_width = |value: pliron::value::Value| {
-        let ty = value.get_type(&ctx);
-        let ty = ty.deref(&ctx);
-        ty.downcast_ref::<IntegerType>()
-            .expect("warp-match value is an integer")
-            .width()
-    };
-    let mut found = Vec::new();
-    let mut aggregate_results = Vec::new();
-    for &op in &body {
-        assert!(
-            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-            "warp match must use typed LLVM intrinsics"
-        );
-        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-            continue;
-        };
-        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-            continue;
-        };
-        let callee = callee.to_string();
-        let Some((_, value_width, aggregate)) =
-            expected.iter().find(|(name, _, _)| *name == callee)
-        else {
-            continue;
-        };
-
-        let call = op.deref(&ctx);
-        assert_eq!(call.get_num_operands(), 2);
-        assert_eq!(
-            [
-                integer_width(call.get_operand(0)),
-                integer_width(call.get_operand(1)),
-            ],
-            [32, *value_width],
-            "{callee} has the wrong typed signature"
-        );
-        assert_eq!(call.get_num_results(), 1);
-        let result = call.get_result(0);
-        if *aggregate {
-            let result_ty = result.get_type(&ctx);
-            let result_ty = result_ty.deref(&ctx);
-            let result_ty = result_ty
-                .downcast_ref::<StructType>()
-                .expect("match.all returns an LLVM aggregate");
-            assert_eq!(result_ty.num_fields(), 2);
-            let field_widths = (0..2)
-                .map(|index| {
-                    let field = result_ty.field_type(index);
-                    let field = field.deref(&ctx);
-                    field
-                        .downcast_ref::<IntegerType>()
-                        .expect("match.all aggregate fields are integers")
-                        .width()
-                })
-                .collect::<Vec<_>>();
-            assert_eq!(field_widths, [32, 1]);
-            aggregate_results.push((callee.clone(), result));
-        } else {
-            assert_eq!(integer_width(result), 32);
-        }
-        found.push(callee);
-    }
-
-    found.sort();
-    let mut expected_calls = expected.map(|(name, _, _)| name.to_owned());
-    expected_calls.sort();
-    assert_eq!(found, expected_calls);
-
-    let mut projected = Vec::new();
-    for &op in &body {
-        let Some(extract) = Operation::get_op::<llvm::ExtractValueOp>(op, &ctx) else {
-            continue;
-        };
-        assert_eq!(extract.indices(&ctx), vec![0]);
-        let extract = op.deref(&ctx);
-        assert_eq!(extract.get_num_operands(), 1);
-        assert_eq!(extract.get_num_results(), 1);
-        assert_eq!(integer_width(extract.get_result(0)), 32);
-        let aggregate = extract.get_operand(0);
-        let callee = aggregate_results
-            .iter()
-            .find_map(|(callee, result)| (*result == aggregate).then(|| callee.clone()))
-            .expect("match.all must extract from its aggregate call result");
-        projected.push(callee);
-    }
-    projected.sort();
-    assert_eq!(
-        projected,
-        [
-            "llvm_nvvm_match_all_sync_i32p".to_owned(),
-            "llvm_nvvm_match_all_sync_i64p".to_owned(),
-        ]
-    );
-    Ok(())
-}
-
-#[test]
-fn test_warpid_ops_preserve_snapshot_semantics() -> Result<(), anyhow::Error> {
-    assert_sreg_lowers_to_inline_asm(
-        nvvm::ReadPtxSregWarpIdOp::get_concrete_op_info(),
-        32,
-        "mov.u32 $0, %warpid;",
-        "=r",
-        llvm::AsmKind::SideEffect,
-    )?;
-    assert_sreg_i32_lowers_to_intrinsic(
-        nvvm::ReadPtxSregNwarpIdOp::get_concrete_op_info(),
-        "llvm_nvvm_read_ptx_sreg_nwarpid",
-    )?;
-    Ok(())
-}
-
-#[test]
-fn test_smid_ops_preserve_snapshot_semantics() -> Result<(), anyhow::Error> {
-    assert_sreg_lowers_to_inline_asm(
-        nvvm::ReadPtxSregSmIdOp::get_concrete_op_info(),
-        32,
-        "mov.u32 $0, %smid;",
-        "=r",
-        llvm::AsmKind::SideEffect,
-    )?;
-    assert_sreg_i32_lowers_to_intrinsic(
-        nvvm::ReadPtxSregNsmIdOp::get_concrete_op_info(),
-        "llvm_nvvm_read_ptx_sreg_nsmid",
-    )?;
-    Ok(())
-}
-
-#[test]
-fn test_repeated_location_samples_remain_side_effecting_reads() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
-
-    for op_info in [
-        nvvm::ReadPtxSregWarpIdOp::get_concrete_op_info(),
-        nvvm::ReadPtxSregSmIdOp::get_concrete_op_info(),
-        nvvm::ReadPtxSregWarpIdOp::get_concrete_op_info(),
-        nvvm::ReadPtxSregSmIdOp::get_concrete_op_info(),
-    ] {
-        let op = Operation::new(&mut ctx, op_info, vec![i32_ty.into()], vec![], vec![], 0);
-        op.insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut warpid_reads = 0usize;
-    let mut smid_reads = 0usize;
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = inline_asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                match template.as_deref() {
-                    Some("mov.u32 $0, %warpid;") => warpid_reads += 1,
-                    Some("mov.u32 $0, %smid;") => smid_reads += 1,
-                    _ => continue,
-                }
-                assert_eq!(
-                    llvm::asm_kind(&ctx, &inline_asm),
-                    llvm::AsmKind::SideEffect,
-                    "location snapshots must survive LLVM CSE"
-                );
-            }
-        }
-    }
-
-    assert_eq!(warpid_reads, 2);
-    assert_eq!(smid_reads, 2);
-    Ok(())
-}
-
-#[test]
-fn test_gridid_op_lowers_to_full_width_inline_ptx() -> Result<(), anyhow::Error> {
-    assert_sreg_lowers_to_inline_asm(
-        nvvm::ReadPtxSregGridIdOp::get_concrete_op_info(),
-        64,
-        "mov.u64 $0, %gridid;",
-        "=l",
-        llvm::AsmKind::Pure,
-    )
-}
-
-#[test]
-fn test_smem_size_ops_lower_to_portable_inline_ptx() -> Result<(), anyhow::Error> {
-    assert_sreg_lowers_to_inline_asm(
-        nvvm::ReadPtxSregDynamicSmemSizeOp::get_concrete_op_info(),
-        32,
-        "mov.u32 $0, %dynamic_smem_size;",
-        "=r",
-        llvm::AsmKind::Pure,
-    )?;
-    assert_sreg_lowers_to_inline_asm(
-        nvvm::ReadPtxSregTotalSmemSizeOp::get_concrete_op_info(),
-        32,
-        "mov.u32 $0, %total_smem_size;",
-        "=r",
-        llvm::AsmKind::Pure,
-    )?;
-    Ok(())
-}
-
-#[test]
-fn generated_threadfences_use_typed_intrinsics_on_both_backends() -> Result<(), anyhow::Error> {
-    const EXPECTED: [&str; 3] = [
-        "llvm_nvvm_membar_cta",
-        "llvm_nvvm_membar_gl",
-        "llvm_nvvm_membar_sys",
-    ];
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        let mut ctx = make_test_ctx();
-        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
-        for op_info in [
-            nvvm::ThreadfenceBlockOp::get_concrete_op_info(),
-            nvvm::ThreadfenceOp::get_concrete_op_info(),
-            nvvm::ThreadfenceSystemOp::get_concrete_op_info(),
-        ] {
-            Operation::new(&mut ctx, op_info, vec![], vec![], vec![], 0)
-                .insert_at_back(entry, &ctx);
-        }
-        append_return(&mut ctx, entry);
-
-        mir_lower::lower_mir_to_llvm_with_options(
-            &mut ctx,
-            module_ptr,
-            mir_lower::LoweringOptions {
-                intrinsic_backend: backend,
-                ..Default::default()
-            },
-        )
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-        let mut found = Vec::new();
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            assert!(
-                Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-                "threadfences must use their reviewed typed route"
-            );
-            let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-                continue;
-            };
-            let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-                continue;
-            };
-            let callee = callee.to_string();
-            if EXPECTED.contains(&callee.as_str()) {
-                assert_eq!(op.deref(&ctx).get_num_operands(), 0);
-                found.push(callee);
-            }
-        }
-        found.sort();
-        assert_eq!(found, EXPECTED);
-
-        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-            .map_err(|error| anyhow::anyhow!(error))?;
-        for symbol in [
-            "llvm.nvvm.membar.cta",
-            "llvm.nvvm.membar.gl",
-            "llvm.nvvm.membar.sys",
-        ] {
-            assert!(ir.contains(&format!("call void @{symbol}()")), "{ir}");
-        }
-    }
-    Ok(())
-}
-
-/// LLVM uses its typed intrinsic. libNVVM uses the reviewed inline-PTX fallback.
-#[test]
-fn generated_elect_sync_uses_the_selected_backend_route() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        let mut ctx = make_test_ctx();
-        let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-        let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
-        let mask = entry.deref(&ctx).get_argument(0);
-        Operation::new(
-            &mut ctx,
-            nvvm::ElectSyncOp::get_concrete_op_info(),
-            vec![i32_ty.into(), i1_ty.into()],
-            vec![mask],
-            vec![],
-            0,
-        )
-        .insert_at_back(entry, &ctx);
-        append_return(&mut ctx, entry);
-
-        mir_lower::lower_mir_to_llvm_with_options(
-            &mut ctx,
-            module_ptr,
-            mir_lower::LoweringOptions {
-                intrinsic_backend: backend,
-                ..Default::default()
-            },
-        )
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-        let mut inline_asm_count = 0;
-        let mut typed_call_count = 0;
-        let mut extract_count = 0;
-        let mut trunc_count = 0;
-        for body_op in lowered_kernel_body(&ctx, module_ptr) {
-            if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) {
-                assert_eq!(
-                    inline_asm
-                        .get_attr_inline_asm_template(&ctx)
-                        .map(|value| String::from((*value).clone()))
-                        .as_deref(),
-                    Some("{ .reg .pred p; elect.sync $0|p, $2; selp.b32 $1, 1, 0, p; }")
-                );
-                assert_eq!(
-                    inline_asm
-                        .get_attr_inline_asm_constraints(&ctx)
-                        .map(|value| String::from((*value).clone()))
-                        .as_deref(),
-                    Some("=r,=r,r")
-                );
-                assert!(
-                    inline_asm
-                        .get_attr_inline_asm_convergent(&ctx)
-                        .is_some_and(|value| bool::from((*value).clone()))
-                );
-                inline_asm_count += 1;
-            }
-            if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
-                && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-                && callee.to_string() == "llvm_nvvm_elect_sync"
-            {
-                typed_call_count += 1;
-            }
-            if Operation::get_op::<llvm::ExtractValueOp>(body_op, &ctx).is_some() {
-                extract_count += 1;
-            }
-            if Operation::get_op::<llvm::TruncOp>(body_op, &ctx).is_some() {
-                trunc_count += 1;
-            }
-        }
-
-        assert_eq!(extract_count, 2);
-        match backend {
-            mir_lower::IntrinsicBackend::LlvmNvptx => {
-                assert_eq!(typed_call_count, 1);
-                assert_eq!(inline_asm_count, 0);
-                assert_eq!(trunc_count, 0);
-            }
-            mir_lower::IntrinsicBackend::LibNvvm => {
-                assert_eq!(typed_call_count, 0);
-                assert_eq!(inline_asm_count, 1);
-                assert_eq!(trunc_count, 1);
-            }
-        }
-    }
-    Ok(())
-}
-
-/// The exact inline-PTX template `convert_shuffle_i64` must emit for `mode`/`clamp`.
-/// Mirrors the production `format!` so a drift in either side fails the test.
-fn expected_shfl_i64_template(mode: &str, clamp: i32) -> String {
-    format!(
-        "{{ .reg .b32 lo; .reg .b32 hi; mov.b64 {{lo, hi}}, $1; \
-         shfl.sync.{mode}.b32 lo, lo, $2, {clamp}, $3; \
-         shfl.sync.{mode}.b32 hi, hi, $2, {clamp}, $3; \
-         mov.b64 $0, {{lo, hi}}; }}"
-    )
-}
-
-/// 64-bit warp shuffle has no LLVM intrinsic (`shfl.sync` is 32-bit only), so it
-/// lowers to convergent inline PTX that splits the value into two halves and runs
-/// two `shfl.sync.*.b32`. Inline asm is opaque to LLVM, so a wrong mnemonic,
-/// swapped operand order, wrong clamp, or missing `convergent` would only surface
-/// as bad PTX downstream. This pins, for every mode, the exact template (incl. the
-/// per-mode clamp: 31 for idx/bfly/down, 0 for up), the `=l,l,r,r` constraints,
-/// and the convergent flag.
-#[test]
-fn test_shuffle_i64_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
-    // Kernel args: [mask (i32), value (i64), lane/delta (i32)].
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![i32_ty.into(), i64_ty.into(), i32_ty.into()]);
-    let mask = entry.deref(&ctx).get_argument(0);
-    let value = entry.deref(&ctx).get_argument(1);
-    let lane = entry.deref(&ctx).get_argument(2);
-
-    // One op per mode, all sharing the same [mask, value, lane] operands.
-    type OpInfo = (
-        fn(pliron::context::Ptr<Operation>) -> pliron::op::OpObj,
-        std::any::TypeId,
-    );
-    let modes: [(OpInfo, &str, i32); 4] = [
-        (nvvm::ShflSyncIdxI64Op::get_concrete_op_info(), "idx", 31),
-        (nvvm::ShflSyncBflyI64Op::get_concrete_op_info(), "bfly", 31),
-        (nvvm::ShflSyncDownI64Op::get_concrete_op_info(), "down", 31),
-        (nvvm::ShflSyncUpI64Op::get_concrete_op_info(), "up", 0),
-    ];
-    for (opid, _, _) in modes {
-        let op = Operation::new(
-            &mut ctx,
-            opid,
-            vec![i64_ty.into()],
-            vec![mask, value, lane],
-            vec![],
-            0,
-        );
-        op.insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    // Collect every inline-asm template emitted into the kernel body.
-    let mut templates: Vec<String> = Vec::new();
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                assert_eq!(
-                    inline_asm
-                        .get_attr_inline_asm_constraints(&ctx)
-                        .map(|s| String::from((*s).clone()))
-                        .as_deref(),
-                    Some("=l,l,r,r"),
-                    "shfl.b64 constraints must be [out i64, value i64, lane i32, mask i32]"
-                );
-                assert!(
-                    inline_asm
-                        .get_attr_inline_asm_convergent(&ctx)
-                        .is_some_and(|b| bool::from((*b).clone())),
-                    "shfl.b64 inline asm must be convergent"
-                );
-                templates.push(
-                    inline_asm
-                        .get_attr_inline_asm_template(&ctx)
-                        .map(|s| String::from((*s).clone()))
-                        .unwrap_or_default(),
-                );
-            }
-        }
-    }
-
-    assert_eq!(
-        templates.len(),
-        4,
-        "each of the 4 shfl.b64 modes must lower to one inline-asm op"
-    );
-    for (_, mode, clamp) in modes {
-        let want = expected_shfl_i64_template(mode, clamp);
-        assert!(
-            templates.contains(&want),
-            "missing inline PTX for shfl.sync.{mode}.b32 (clamp {clamp}); got {templates:?}"
-        );
-    }
-
-    Ok(())
-}
-
-/// Regression cover for explicit MIR address-space coercion before a call.
-///
-/// When a caller passes a pointer in one address space to a callee whose
-/// declared parameter lives in a different address space (the
-/// `*mut SharedArray<T, N>` / `addrspace(3)` case that surfaces from
-/// `block_reduce` and friends), MIR must record the representational cast
-/// before the exact call-signature verifier sees the argument. Lowering then
-/// emits the corresponding `llvm.addrspacecast`.
-///
-/// This test builds two MIR functions in one module:
-///   - `callee(p: *mut i32 in addrspace(3))`
-///   - `caller(p: *mut i32 in addrspace(0)) { callee(p) }`
-///
-/// and asserts the lowered `caller` body contains an `AddrSpaceCastOp`.
-#[test]
-fn addrspace_coercion_inserts_addrspacecast_at_call_site() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use llvm_export::ops::AddrSpaceCastOp;
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::attributes::{StringAttr, TypeAttr};
-    use pliron::builtin::types::{FunctionType, IntegerType, Signedness};
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let module = ModuleOp::new(&mut ctx, "test_addrspace_coercion".try_into().unwrap());
-    let module_ptr = module.get_operation();
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let shared_ptr_ty = MirPtrType::get_shared(&mut ctx, i32_ty.into(), true);
-    let generic_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let expected_call_location = Location::Named {
-        name: "source-device-call".to_string(),
-        child_loc: Box::new(Location::Unknown),
-    };
-
-    // Callee: takes a *mut i32 in addrspace(3), returns ().
-    let callee_func_ty = FunctionType::get(&ctx, vec![shared_ptr_ty.into()], vec![]);
-    let callee_func_op = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let callee_func = mir::MirFuncOp::new(
-        &mut ctx,
-        callee_func_op,
-        TypeAttr::new(callee_func_ty.into()),
-    );
-    callee_func.set_symbol_name(&mut ctx, "callee".try_into().unwrap());
-    {
-        let region = callee_func.get_operation().deref(&ctx).get_region(0);
-        let block = BasicBlock::new(&mut ctx, None, vec![shared_ptr_ty.into()]);
-        block.insert_at_back(region, &ctx);
-
-        let ret_op = Operation::new(
-            &mut ctx,
-            mir::MirReturnOp::get_concrete_op_info(),
-            vec![],
-            vec![],
-            vec![],
-            0,
-        );
-        ret_op.insert_at_back(block, &ctx);
-    }
-    callee_func
-        .get_operation()
-        .insert_at_back(module_block, &ctx);
-
-    // Caller: takes a *mut i32 in addrspace(0), calls `callee` with that
-    // pointer. The lowerer is responsible for inserting an addrspacecast
-    // since the callee's declared addrspace differs.
-    let caller_func_ty = FunctionType::get(&ctx, vec![generic_ptr_ty.into()], vec![]);
-    let caller_func_op = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let caller_func = mir::MirFuncOp::new(
-        &mut ctx,
-        caller_func_op,
-        TypeAttr::new(caller_func_ty.into()),
-    );
-    caller_func.set_symbol_name(&mut ctx, "caller".try_into().unwrap());
-    {
-        let region = caller_func.get_operation().deref(&ctx).get_region(0);
-        let block = BasicBlock::new(&mut ctx, None, vec![generic_ptr_ty.into()]);
-        block.insert_at_back(region, &ctx);
-        let arg = block.deref(&ctx).get_argument(0);
-        let cast_op_ptr = Operation::new(
-            &mut ctx,
-            mir::MirCastOp::get_concrete_op_info(),
-            vec![shared_ptr_ty.into()],
-            vec![arg],
-            vec![],
-            0,
-        );
-        mir::MirCastOp::new(cast_op_ptr)
-            .set_attr_cast_kind(&ctx, dialect_mir::attributes::MirCastKindAttr::PtrToPtr);
-        cast_op_ptr.insert_at_back(block, &ctx);
-        let coerced_arg = cast_op_ptr.deref(&ctx).get_result(0);
-
-        let call_op_ptr = Operation::new(
-            &mut ctx,
-            mir::MirCallOp::get_concrete_op_info(),
-            vec![],
-            vec![coerced_arg],
-            vec![],
-            0,
-        );
-        let call_op = mir::MirCallOp::new(call_op_ptr);
-        call_op.set_attr_callee(&ctx, StringAttr::new("callee".to_string()));
-        call_op_ptr
-            .deref_mut(&ctx)
-            .set_loc(expected_call_location.clone());
-        call_op_ptr.insert_at_back(block, &ctx);
-
-        let ret_op = Operation::new(
-            &mut ctx,
-            mir::MirReturnOp::get_concrete_op_info(),
-            vec![],
-            vec![],
-            vec![],
-            0,
-        );
-        ret_op.insert_at_back(block, &ctx);
-    }
-    caller_func
-        .get_operation()
-        .insert_at_back(module_block, &ctx);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    let mut found_addrspace_cast = false;
-    let mut found_call = false;
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != "caller" {
-            continue;
-        }
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                if Operation::get_op::<AddrSpaceCastOp>(body_op, &ctx).is_some() {
-                    found_addrspace_cast = true;
-                }
-                if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
-                    && matches!(
-                        call.callee(&ctx),
-                        CallOpCallable::Direct(symbol) if symbol.to_string() == "callee"
-                    )
-                {
-                    found_call = true;
-                    assert_eq!(
-                        call.get_operation().deref(&ctx).loc(),
-                        expected_call_location
-                    );
-                }
-            }
-        }
-    }
-
-    assert!(
-        found_addrspace_cast,
-        "caller body must contain llvm.addrspacecast for the addrspace(0) -> (3) coercion at the call site",
-    );
-    assert!(found_call, "caller body must contain the lowered call");
-    Ok(())
-}
-
-/// A zero-sized MIR result is erased from the NVPTX function ABI, but its
-/// typed value can remain live inside MIR (for example, when one ZST-returning
-/// function returns the result of another). Lowering must keep the void call
-/// for side effects and replace only its value result with a typed LLVM undef.
-#[test]
-fn zst_union_call_result_keeps_void_call_and_replaces_live_uses() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::{MirTupleType, MirUnionType};
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::attributes::{StringAttr, TypeAttr};
-    use pliron::builtin::types::FunctionType;
-    use pliron::r#type::{TypeHandle, Typed};
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let unit_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![]).into();
-    let union_ty: TypeHandle = MirUnionType::get(
-        &mut ctx,
-        "AlignedZeroUnion".into(),
-        vec!["unit".into()],
-        vec![unit_ty],
-        0,
-        16,
-    )
-    .into();
-
-    let module = ModuleOp::new(&mut ctx, "test_zst_union_call".try_into().unwrap());
-    let module_ptr = module.get_operation();
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-
-    let callee_ty = FunctionType::get(&ctx, vec![], vec![union_ty]);
-    let callee_ptr = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let callee = mir::MirFuncOp::new(&mut ctx, callee_ptr, TypeAttr::new(callee_ty.into()));
-    callee.set_symbol_name(&mut ctx, "make_zero".try_into().unwrap());
-    {
-        let region = callee.get_operation().deref(&ctx).get_region(0);
-        let block = BasicBlock::new(&mut ctx, None, vec![]);
-        block.insert_at_back(region, &ctx);
-
-        let undef = mir::MirUndefOp::new(&mut ctx, union_ty);
-        undef.get_operation().insert_at_back(block, &ctx);
-        let value = undef.get_operation().deref(&ctx).get_result(0);
-
-        let ret = Operation::new(
-            &mut ctx,
-            mir::MirReturnOp::get_concrete_op_info(),
-            vec![],
-            vec![value],
-            vec![],
-            0,
-        );
-        ret.insert_at_back(block, &ctx);
-    }
-    callee.get_operation().insert_at_back(module_block, &ctx);
-
-    let caller_ty = FunctionType::get(&ctx, vec![], vec![union_ty]);
-    let caller_ptr = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let caller = mir::MirFuncOp::new(&mut ctx, caller_ptr, TypeAttr::new(caller_ty.into()));
-    caller.set_symbol_name(&mut ctx, "return_called_zero".try_into().unwrap());
-    {
-        let region = caller.get_operation().deref(&ctx).get_region(0);
-        let block = BasicBlock::new(&mut ctx, None, vec![]);
-        block.insert_at_back(region, &ctx);
-
-        let call_ptr = Operation::new(
-            &mut ctx,
-            mir::MirCallOp::get_concrete_op_info(),
-            vec![union_ty],
-            vec![],
-            vec![],
-            0,
-        );
-        let call = mir::MirCallOp::new(call_ptr);
-        call.set_attr_callee(&ctx, StringAttr::new("make_zero".to_string()));
-        call_ptr.insert_at_back(block, &ctx);
-        let value = call_ptr.deref(&ctx).get_result(0);
-
-        let ret = Operation::new(
-            &mut ctx,
-            mir::MirReturnOp::get_concrete_op_info(),
-            vec![],
-            vec![value],
-            vec![],
-            0,
-        );
-        ret.insert_at_back(block, &ctx);
-    }
-    caller.get_operation().insert_at_back(module_block, &ctx);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{e}"))?;
-
-    let mut found_void_call = false;
-    let mut caller_undefs = 0;
-    let mut found_void_return = false;
-    for op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(func) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func.get_symbol_name(&ctx).to_string() != "return_called_zero" {
-            continue;
-        }
-        let region = func.get_operation().deref(&ctx).get_region(0);
-        for block in region.deref(&ctx).iter(&ctx) {
-            for body_op in block.deref(&ctx).iter(&ctx) {
-                if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
-                    && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-                    && callee.to_string() == "make_zero"
-                {
-                    let call_op = call.get_operation().deref(&ctx);
-                    assert_eq!(call_op.get_num_results(), 1);
-                    assert!(
-                        call_op
-                            .get_result(0)
-                            .get_type(&ctx)
-                            .deref(&ctx)
-                            .is::<llvm_export::types::VoidType>(),
-                        "the ZST-returning call must use the void ABI"
-                    );
-                    found_void_call = true;
-                }
-                if Operation::get_op::<llvm::UndefOp>(body_op, &ctx).is_some() {
-                    caller_undefs += 1;
-                }
-                if let Some(ret) = Operation::get_op::<llvm::ReturnOp>(body_op, &ctx) {
-                    assert_eq!(
-                        ret.get_operation().deref(&ctx).get_num_operands(),
-                        0,
-                        "the caller's ZST return must also use the void ABI"
-                    );
-                    found_void_return = true;
-                }
-            }
-        }
-    }
-
-    assert!(
-        found_void_call,
-        "the LLVM call must be retained because the callee may have side effects"
-    );
-    assert_eq!(
-        caller_undefs, 1,
-        "the live MIR result must be replaced by one typed LLVM undef"
-    );
-    assert!(
-        found_void_return,
-        "the caller must retain its return terminator"
-    );
-    Ok(())
-}
-
-/// Lock the comparison-predicate lowering table to the rustc_codegen_ssa
-/// reference (`bin_op_to_fcmp_predicate` / `bin_op_to_icmp_predicate`):
-///
-/// | MIR op   | float `fcmp`      | signed `icmp` | unsigned `icmp` |
-/// |----------|-------------------|---------------|-----------------|
-/// | `mir.eq` | `oeq` (ordered)   | `eq`          | `eq`            |
-/// | `mir.ne` | `une` (UNordered) | `ne`          | `ne`            |
-/// | `mir.lt` | `olt`             | `slt`         | `ult`           |
-/// | `mir.le` | `ole`             | `sle`         | `ule`           |
-/// | `mir.gt` | `ogt`             | `sgt`         | `ugt`           |
-/// | `mir.ge` | `oge`             | `sge`         | `uge`           |
-///
-/// `ne` is the one float predicate that must be UNordered: Rust requires
-/// `a != b == !(a == b)`, so `x != x` must be true for NaN (issue #123;
-/// the ordered `one` folds the canonical NaN check to `false`).
-///
-/// The test also locks fastmath flags to *empty* on every lowered `fcmp`:
-/// a future `nnan` default would make `fcmp nnan une x, x` poison for NaN
-/// and silently re-break NaN detection while the predicate assertion above
-/// stays green.
-#[test]
-fn test_cmp_predicate_lowering() -> Result<(), anyhow::Error> {
-    use llvm_export::attributes::{FCmpPredicateAttr, FastmathFlagsAttr, ICmpPredicateAttr};
-    use llvm_export::op_interfaces::FastMathFlags;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_ptr = module.get_operation();
-
-    let f32_ty = pliron::builtin::types::FP32Type::get(&ctx);
-    let i32_signed = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        32,
-        pliron::builtin::types::Signedness::Signed,
-    );
-    let u32_unsigned = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        32,
-        pliron::builtin::types::Signedness::Unsigned,
-    );
-    let bool_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        1,
-        pliron::builtin::types::Signedness::Signless,
-    );
-
-    // Args: (f32, f32, i32, u32). The integer args carry pre-conversion
-    // signedness, which is what selects signed vs unsigned icmp predicates.
-    let arg_tys: Vec<pliron::r#type::TypeHandle> = vec![
-        f32_ty.into(),
-        f32_ty.into(),
-        i32_signed.into(),
-        u32_unsigned.into(),
-    ];
-    let func_name = "cmp_func";
-    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, arg_tys.clone(), vec![]);
-
-    let func_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
-    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
-    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
-
-    let region = func.get_operation().deref(&ctx).get_region(0);
-    let block = {
-        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, arg_tys);
-        b.insert_at_back(region, &ctx);
-        b
-    };
-    let fa = block.deref(&ctx).get_argument(0);
-    let fb = block.deref(&ctx).get_argument(1);
-    let si = block.deref(&ctx).get_argument(2);
-    let ui = block.deref(&ctx).get_argument(3);
-
-    // One comparison op per table row, in a fixed program order. The raw
-    // `Operation::new` construction mirrors how the importer builds these
-    // ops (mir-importer translator/rvalue.rs BinaryOp arm).
-    let cmp_infos = [
-        // Floats: all six predicates.
-        (mir::MirEqOp::get_concrete_op_info(), fa, fb),
-        (mir::MirNeOp::get_concrete_op_info(), fa, fb),
-        (mir::MirLtOp::get_concrete_op_info(), fa, fb),
-        (mir::MirLeOp::get_concrete_op_info(), fa, fb),
-        (mir::MirGtOp::get_concrete_op_info(), fa, fb),
-        (mir::MirGeOp::get_concrete_op_info(), fa, fb),
-        // Signed integers: eq/ne are sign-agnostic, the rest must be s*.
-        (mir::MirEqOp::get_concrete_op_info(), si, si),
-        (mir::MirNeOp::get_concrete_op_info(), si, si),
-        (mir::MirLtOp::get_concrete_op_info(), si, si),
-        (mir::MirLeOp::get_concrete_op_info(), si, si),
-        (mir::MirGtOp::get_concrete_op_info(), si, si),
-        (mir::MirGeOp::get_concrete_op_info(), si, si),
-        // Unsigned integers: the relational predicates must be u*.
-        (mir::MirLtOp::get_concrete_op_info(), ui, ui),
-        (mir::MirLeOp::get_concrete_op_info(), ui, ui),
-        (mir::MirGtOp::get_concrete_op_info(), ui, ui),
-        (mir::MirGeOp::get_concrete_op_info(), ui, ui),
-    ];
-    for (info, lhs, rhs) in cmp_infos {
-        let op = Operation::new(
-            &mut ctx,
-            info,
-            vec![bool_ty.into()],
-            vec![lhs, rhs],
-            vec![],
-            0,
-        );
-        op.insert_at_back(block, &ctx);
-    }
-
-    let ret_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirReturnOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    ret_op_ptr.insert_at_back(block, &ctx);
-
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    // Collect lowered predicates in program order.
-    let mut fcmp_preds = Vec::new();
-    let mut icmp_preds = Vec::new();
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != func_name {
-            continue;
-        }
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                if let Some(fcmp) = Operation::get_op::<llvm::FCmpOp>(body_op, &ctx) {
-                    fcmp_preds.push(fcmp.predicate(&ctx));
-                    // fcmp carries `contract` (set by add_fastmath_flags) which is a
-                    // no-op for comparisons at the LLVM / PTX level. Critically, nnan
-                    // is NOT set, so NaN checks like `x != x` still evaluate correctly.
-                    let expected: FastmathFlagsAttr =
-                        llvm_export::attributes::FastmathFlags::CONTRACT.into();
-                    assert_eq!(
-                        fcmp.fast_math_flags(&ctx),
-                        expected,
-                        "fcmp must carry only the contract flag (nnan would poison NaN checks)"
-                    );
-                }
-                if let Some(icmp) = Operation::get_op::<llvm::ICmpOp>(body_op, &ctx) {
-                    icmp_preds.push(icmp.predicate(&ctx));
-                }
-            }
-        }
-    }
-
-    assert_eq!(
-        fcmp_preds,
-        vec![
-            FCmpPredicateAttr::OEQ,
-            FCmpPredicateAttr::UNE,
-            FCmpPredicateAttr::OLT,
-            FCmpPredicateAttr::OLE,
-            FCmpPredicateAttr::OGT,
-            FCmpPredicateAttr::OGE,
-        ],
-        "float comparison predicates must mirror rustc: ordered except Ne (une)"
-    );
-    assert_eq!(
-        icmp_preds,
-        vec![
-            ICmpPredicateAttr::EQ,
-            ICmpPredicateAttr::NE,
-            ICmpPredicateAttr::SLT,
-            ICmpPredicateAttr::SLE,
-            ICmpPredicateAttr::SGT,
-            ICmpPredicateAttr::SGE,
-            ICmpPredicateAttr::ULT,
-            ICmpPredicateAttr::ULE,
-            ICmpPredicateAttr::UGT,
-            ICmpPredicateAttr::UGE,
-        ],
-        "integer comparison predicates must respect pre-conversion signedness"
-    );
-    Ok(())
-}
-
-/// Helper: fresh context with all dialects registered.
-fn make_test_ctx() -> Context {
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-    ctx
-}
-
-/// Helper: build a module + MirFuncOp("kernel_func") with given arg types,
-/// returning the module ptr and entry block.
-fn build_test_kernel(
-    ctx: &mut Context,
-    arg_tys: Vec<pliron::r#type::TypeHandle>,
-) -> (
-    pliron::context::Ptr<Operation>,
-    pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-) {
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::attributes::TypeAttr;
-    use pliron::builtin::types::FunctionType;
-
-    let module = ModuleOp::new(ctx, "test_module".try_into().unwrap());
-    let module_ptr = module.get_operation();
-
-    let func_ty = FunctionType::get(ctx, arg_tys.clone(), vec![]);
-    let func_op_ptr = Operation::new(
-        ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let func = mir::MirFuncOp::new(ctx, func_op_ptr, TypeAttr::new(func_ty.into()));
-    func.set_symbol_name(ctx, "kernel_func".try_into().unwrap());
-
-    let region = func.get_operation().deref(ctx).get_region(0);
-    let entry = BasicBlock::new(ctx, None, arg_tys);
-    entry.insert_at_back(region, ctx);
-
-    let module_region = module_ptr.deref(ctx).get_region(0);
-    let module_block = module_region.deref(ctx).iter(ctx).next().unwrap();
-    func.get_operation().insert_at_back(module_block, ctx);
-
-    (module_ptr, entry)
-}
-
-/// Helper: append a mir.return (void) to a block.
-fn append_return(ctx: &mut Context, block: pliron::context::Ptr<pliron::basic_block::BasicBlock>) {
-    let ret = Operation::new(
-        ctx,
-        mir::MirReturnOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    ret.insert_at_back(block, ctx);
-}
-
-fn lower_basic_mbarrier(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let bar_ptr_ty = MirPtrType::get_shared(&mut ctx, u64_ty.into(), false);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![bar_ptr_ty.into(), u32_ty.into()]);
-    let barrier = entry.deref(&ctx).get_argument(0);
-    let count = entry.deref(&ctx).get_argument(1);
-
-    nvvm::MbarrierInitSharedOp::build(&mut ctx, barrier, count).insert_at_back(entry, &ctx);
-    let arrive = nvvm::MbarrierArriveSharedOp::build(&mut ctx, barrier);
-    let token = arrive.deref(&ctx).get_result(0);
-    arrive.insert_at_back(entry, &ctx);
-    nvvm::MbarrierTestWaitSharedOp::build(&mut ctx, barrier, token).insert_at_back(entry, &ctx);
-    nvvm::MbarrierInvalSharedOp::build(&mut ctx, barrier).insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn test_generated_basic_mbarrier_uses_shared_lowering_on_both_backends() -> Result<(), anyhow::Error>
-{
-    let expected_calls = [
-        ("llvm_nvvm_mbarrier_init_shared", 2),
-        ("llvm_nvvm_mbarrier_arrive_shared", 1),
-        ("llvm_nvvm_mbarrier_inval_shared", 1),
-    ];
-    let init_template = "mbarrier.init.shared.b64 [$0], $1;";
-    let arrive_template = "mbarrier.arrive.shared.b64 $0, [$1];";
-    let test_wait_template =
-        "{ .reg .pred %p0; mbarrier.test_wait.shared.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }";
-    let inval_template = "mbarrier.inval.shared.b64 [$0];";
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        let (ctx, module_ptr) = lower_basic_mbarrier(backend)?;
-        let mut call_counts = [0usize; 3];
-        let expected_asm = match backend {
-            mir_lower::IntrinsicBackend::LlvmNvptx => {
-                vec![(test_wait_template, "=r,l,l,~{memory}", 2)]
-            }
-            mir_lower::IntrinsicBackend::LibNvvm => vec![
-                (init_template, "l,r,~{memory}", 2),
-                (arrive_template, "=l,l,~{memory}", 1),
-                (test_wait_template, "=r,l,l,~{memory}", 2),
-                (inval_template, "l,~{memory}", 1),
-            ],
-        };
-        let mut asm_counts = vec![0usize; expected_asm.len()];
-        let mut trunc_count = 0;
-
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) {
-                let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-                    continue;
-                };
-                let callee = callee.to_string();
-                let Some(index) = expected_calls
-                    .iter()
-                    .position(|(expected, _)| callee == *expected)
-                else {
-                    assert_ne!(callee, "llvm_nvvm_mbarrier_test_wait_shared");
-                    continue;
-                };
-                call_counts[index] += 1;
-                assert_eq!(op.deref(&ctx).get_num_operands(), expected_calls[index].1);
-            }
-
-            if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
-                let template = inline_asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                let index = expected_asm
-                    .iter()
-                    .position(|(expected, _, _)| template.as_deref() == Some(*expected))
-                    .unwrap_or_else(|| panic!("unexpected {backend:?} inline PTX: {template:?}"));
-                let (_, constraints, operand_count) = expected_asm[index];
-                asm_counts[index] += 1;
-                assert_eq!(
-                    inline_asm
-                        .get_attr_inline_asm_constraints(&ctx)
-                        .map(|value| String::from((*value).clone()))
-                        .as_deref(),
-                    Some(constraints)
-                );
-                assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Convergent);
-                let asm = op.deref(&ctx);
-                assert_eq!(asm.get_num_operands(), operand_count);
-                assert_eq!(asm.get_num_results(), 1);
-            }
-
-            if Operation::get_op::<llvm::TruncOp>(op, &ctx).is_some() {
-                trunc_count += 1;
-            }
-        }
-
-        match backend {
-            mir_lower::IntrinsicBackend::LlvmNvptx => assert_eq!(call_counts, [1; 3]),
-            mir_lower::IntrinsicBackend::LibNvvm => assert_eq!(call_counts, [0; 3]),
-        }
-        assert_eq!(asm_counts, vec![1; expected_asm.len()]);
-        assert_eq!(
-            trunc_count, 1,
-            "test-wait must adapt its i32 predicate to i1"
-        );
-
-        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-            .map_err(|error| anyhow::anyhow!(error))?;
-        match backend {
-            mir_lower::IntrinsicBackend::LlvmNvptx => {
-                assert!(
-                    ir.contains("call void @llvm.nvvm.mbarrier.init.shared(ptr addrspace(3)"),
-                    "{ir}"
-                );
-                assert!(
-                    ir.contains("call i64 @llvm.nvvm.mbarrier.arrive.shared(ptr addrspace(3)"),
-                    "{ir}"
-                );
-                assert!(
-                    ir.contains("call void @llvm.nvvm.mbarrier.inval.shared(ptr addrspace(3)"),
-                    "{ir}"
-                );
-                assert!(!ir.contains(init_template), "{ir}");
-                assert!(!ir.contains(arrive_template), "{ir}");
-                assert!(!ir.contains(inval_template), "{ir}");
-            }
-            mir_lower::IntrinsicBackend::LibNvvm => {
-                for symbol in [
-                    "@llvm.nvvm.mbarrier.init.shared",
-                    "@llvm.nvvm.mbarrier.arrive.shared",
-                    "@llvm.nvvm.mbarrier.inval.shared",
-                ] {
-                    assert!(
-                        !ir.contains(symbol),
-                        "libNVVM route retained {symbol}:\n{ir}"
-                    );
-                }
-                for template in [init_template, arrive_template, inval_template] {
-                    assert!(ir.contains(template), "{ir}");
-                }
-            }
-        }
-        assert!(ir.contains(test_wait_template), "{ir}");
-        assert!(ir.contains("asm sideeffect"), "{ir}");
-        assert!(ir.contains("trunc i32") && ir.contains("to i1"), "{ir}");
-        assert!(ir.contains("attributes #0 = { convergent }"), "{ir}");
-    }
-    Ok(())
-}
-
-fn lower_cluster_barriers(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
-    for mode in [
-        nvvm::ClusterBarrierModeAttr::Arrive,
-        nvvm::ClusterBarrierModeAttr::ArriveAligned,
-        nvvm::ClusterBarrierModeAttr::ArriveRelaxed,
-        nvvm::ClusterBarrierModeAttr::ArriveRelaxedAligned,
-        nvvm::ClusterBarrierModeAttr::Wait,
-        nvvm::ClusterBarrierModeAttr::WaitAligned,
-    ] {
-        nvvm::ClusterBarrierOp::build(&mut ctx, mode).insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn generated_cluster_barriers_lower_exactly_on_both_backends() -> Result<(), anyhow::Error> {
-    let recipes = [
-        (
-            "llvm_nvvm_barrier_cluster_arrive",
-            "barrier.cluster.arrive;",
-        ),
-        (
-            "llvm_nvvm_barrier_cluster_arrive_aligned",
-            "barrier.cluster.arrive.aligned;",
-        ),
-        (
-            "llvm_nvvm_barrier_cluster_arrive_relaxed",
-            "barrier.cluster.arrive.relaxed;",
-        ),
-        (
-            "llvm_nvvm_barrier_cluster_arrive_relaxed_aligned",
-            "barrier.cluster.arrive.relaxed.aligned;",
-        ),
-        ("llvm_nvvm_barrier_cluster_wait", "barrier.cluster.wait;"),
-        (
-            "llvm_nvvm_barrier_cluster_wait_aligned",
-            "barrier.cluster.wait.aligned;",
-        ),
-    ];
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        let (ctx, module_ptr) = lower_cluster_barriers(backend)?;
-        let mut calls = [0usize; 6];
-        let mut asm = [0usize; 6];
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) {
-                let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-                    continue;
-                };
-                if let Some(index) = recipes
-                    .iter()
-                    .position(|(symbol, _)| callee.to_string() == *symbol)
-                {
-                    calls[index] += 1;
-                }
-            }
-            if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
-                let template = inline_asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                if let Some(index) = recipes
-                    .iter()
-                    .position(|(_, expected)| template.as_deref() == Some(*expected))
-                {
-                    asm[index] += 1;
-                    assert_eq!(
-                        inline_asm
-                            .get_attr_inline_asm_constraints(&ctx)
-                            .map(|value| String::from((*value).clone()))
-                            .as_deref(),
-                        Some("~{memory}")
-                    );
-                    assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Convergent);
-                }
-            }
-        }
-        match backend {
-            mir_lower::IntrinsicBackend::LlvmNvptx => {
-                assert_eq!(calls, [1; 6]);
-                assert_eq!(asm, [0; 6]);
-            }
-            mir_lower::IntrinsicBackend::LibNvvm => {
-                assert_eq!(calls, [0; 6]);
-                assert_eq!(asm, [1; 6]);
-            }
-        }
-    }
-    Ok(())
-}
-
-#[test]
-fn test_cluster_mbarrier_and_fences_lower_to_exact_inline_ptx() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let bar_ptr_ty = MirPtrType::get_shared(&mut ctx, i64_ty.into(), false);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![bar_ptr_ty.into(), i32_ty.into()]);
-
-    let bar_ptr = entry.deref(&ctx).get_argument(0);
-    let bytes_or_parity = entry.deref(&ctx).get_argument(1);
-
-    let arrive = Operation::new(
-        &mut ctx,
-        nvvm::MbarrierArriveExpectTxClusterOp::get_concrete_op_info(),
-        vec![i64_ty.into()],
-        vec![bar_ptr, bytes_or_parity],
-        vec![],
-        0,
-    );
-    arrive.insert_at_back(entry, &ctx);
-
-    let try_wait = Operation::new(
-        &mut ctx,
-        nvvm::MbarrierTryWaitParityClusterOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![bar_ptr, bytes_or_parity],
-        vec![],
-        0,
-    );
-    try_wait.insert_at_back(entry, &ctx);
-
-    let mbarrier_fence = Operation::new(
-        &mut ctx,
-        nvvm::FenceMbarrierInitReleaseClusterOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    mbarrier_fence.insert_at_back(entry, &ctx);
-
-    let proxy_release_fence = Operation::new(
-        &mut ctx,
-        nvvm::FenceProxyAsyncGenericReleaseSharedCtaClusterOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    proxy_release_fence.insert_at_back(entry, &ctx);
-
-    let proxy_acquire_fence = Operation::new(
-        &mut ctx,
-        nvvm::FenceProxyAsyncGenericAcquireSharedClusterClusterOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    proxy_acquire_fence.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let expected = [
-        (
-            "mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 $0, [$1], $2;",
-            "=l,l,r,~{memory}",
-        ),
-        (
-            "{ .reg .pred %p0; mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
-            "=r,l,r,~{memory}",
-        ),
-        ("fence.mbarrier_init.release.cluster;", "~{memory}"),
-        (
-            "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
-            "~{memory}",
-        ),
-        (
-            "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;",
-            "~{memory}",
-        ),
-    ];
-    let mut matches = [0usize; 5];
-
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = inline_asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                let Some(index) = expected.iter().position(|(expected_template, _)| {
-                    template.as_deref() == Some(*expected_template)
-                }) else {
-                    continue;
-                };
-
-                matches[index] += 1;
-                assert_eq!(
-                    inline_asm
-                        .get_attr_inline_asm_constraints(&ctx)
-                        .map(|value| String::from((*value).clone()))
-                        .as_deref(),
-                    Some(expected[index].1)
-                );
-                assert_eq!(
-                    llvm::asm_kind_opt(&ctx, &inline_asm),
-                    Some(llvm::AsmKind::Convergent)
-                );
-            }
-        }
-    }
-
-    assert_eq!(
-        matches, [1; 5],
-        "each cluster barrier/fence must lower to its exact PTX template once"
-    );
-    Ok(())
-}
-
-#[test]
-fn test_fast_float_intrinsics_lower_to_explicit_fast_binops() -> Result<(), anyhow::Error> {
-    use dialect_mir::rust_intrinsics;
-    use llvm_export::attributes::{FastmathFlags, FastmathFlagsAttr};
-    use llvm_export::op_interfaces::FastMathFlags;
-    use pliron::builtin::attributes::StringAttr;
-    use pliron::builtin::op_interfaces::CallOpInterface;
-    use pliron::builtin::types::{FP32Type, FP64Type};
-    use pliron::r#type::{TypeHandle, Typed};
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let f64_ty = FP64Type::get(&ctx);
-    let f32_ty_obj: TypeHandle = f32_ty.into();
-    let f64_ty_obj: TypeHandle = f64_ty.into();
-    let (module_ptr, entry) = build_test_kernel(
-        &mut ctx,
-        vec![f32_ty_obj, f32_ty_obj, f64_ty_obj, f64_ty_obj],
-    );
-    let f32_lhs = entry.deref(&ctx).get_argument(0);
-    let f32_rhs = entry.deref(&ctx).get_argument(1);
-    let f64_lhs = entry.deref(&ctx).get_argument(2);
-    let f64_rhs = entry.deref(&ctx).get_argument(3);
-
-    for (callee, lhs, rhs, result_ty) in [
-        (
-            rust_intrinsics::CALLEE_FADD_FAST,
-            f32_lhs,
-            f32_rhs,
-            f32_ty_obj,
-        ),
-        (
-            rust_intrinsics::CALLEE_FSUB_FAST,
-            f32_lhs,
-            f32_rhs,
-            f32_ty_obj,
-        ),
-        (
-            rust_intrinsics::CALLEE_FMUL_FAST,
-            f32_lhs,
-            f32_rhs,
-            f32_ty_obj,
-        ),
-        (
-            rust_intrinsics::CALLEE_FDIV_FAST,
-            f32_lhs,
-            f32_rhs,
-            f32_ty_obj,
-        ),
-        (
-            rust_intrinsics::CALLEE_FREM_FAST,
-            f32_lhs,
-            f32_rhs,
-            f32_ty_obj,
-        ),
-        (
-            rust_intrinsics::CALLEE_FADD_FAST,
-            f64_lhs,
-            f64_rhs,
-            f64_ty_obj,
-        ),
-        (
-            rust_intrinsics::CALLEE_FSUB_FAST,
-            f64_lhs,
-            f64_rhs,
-            f64_ty_obj,
-        ),
-        (
-            rust_intrinsics::CALLEE_FMUL_FAST,
-            f64_lhs,
-            f64_rhs,
-            f64_ty_obj,
-        ),
-        (
-            rust_intrinsics::CALLEE_FDIV_FAST,
-            f64_lhs,
-            f64_rhs,
-            f64_ty_obj,
-        ),
-        (
-            rust_intrinsics::CALLEE_FREM_FAST,
-            f64_lhs,
-            f64_rhs,
-            f64_ty_obj,
-        ),
-    ] {
-        let call_ptr = Operation::new(
-            &mut ctx,
-            mir::MirCallOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![lhs, rhs],
-            vec![],
-            0,
-        );
-        let call = mir::MirCallOp::new(call_ptr);
-        call.set_attr_callee(&ctx, StringAttr::new(callee.to_string()));
-        call_ptr.insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    let explicit_fast_flags: FastmathFlagsAttr = FastmathFlags::FAST.into();
-    assert_ne!(
-        explicit_fast_flags,
-        FastmathFlagsAttr::default(),
-        "FastmathFlagsAttr::default() is empty; f*_fast must use explicit fast flags"
-    );
-
-    let mut fadd_counts = [0usize; 2];
-    let mut fsub_counts = [0usize; 2];
-    let mut fmul_counts = [0usize; 2];
-    let mut fdiv_counts = [0usize; 2];
-    let mut frem_counts = [0usize; 2];
-
-    macro_rules! count_fast_binop {
-        ($body_op:expr, $op_ty:ty, $counts:ident, $name:literal) => {
-            if let Some(op) = Operation::get_op::<$op_ty>($body_op, &ctx) {
-                assert_eq!(
-                    op.fast_math_flags(&ctx),
-                    explicit_fast_flags,
-                    concat!($name, " must carry explicit LLVM fast-math flags")
-                );
-                let result_ty = op.get_operation().deref(&ctx).get_result(0).get_type(&ctx);
-                if result_ty == f32_ty_obj {
-                    $counts[0] += 1;
-                } else if result_ty == f64_ty_obj {
-                    $counts[1] += 1;
-                } else {
-                    panic!(concat!($name, " lowered to an unexpected result type"));
-                }
-            }
-        };
-    }
-
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                assert!(
-                    Operation::get_op::<mir::MirCallOp>(body_op, &ctx).is_none(),
-                    "f*_fast placeholder mir.call must not survive MIR lowering"
-                );
-                if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
-                    && let CallOpCallable::Direct(sym) = call.callee(&ctx)
-                {
-                    let callee = sym.to_string();
-                    assert!(
-                        !callee.starts_with(rust_intrinsics::PLACEHOLDER_PREFIX),
-                        "lowered LLVM must not call unresolved Rust intrinsic placeholder `{callee}`"
-                    );
-                }
-                count_fast_binop!(body_op, llvm::FAddOp, fadd_counts, "fadd_fast");
-                count_fast_binop!(body_op, llvm::FSubOp, fsub_counts, "fsub_fast");
-                count_fast_binop!(body_op, llvm::FMulOp, fmul_counts, "fmul_fast");
-                count_fast_binop!(body_op, llvm::FDivOp, fdiv_counts, "fdiv_fast");
-                count_fast_binop!(body_op, llvm::FRemOp, frem_counts, "frem_fast");
-            }
-        }
-    }
-
-    assert_eq!(fadd_counts, [1, 1], "fadd_fast must lower for f32 and f64");
-    assert_eq!(fsub_counts, [1, 1], "fsub_fast must lower for f32 and f64");
-    assert_eq!(fmul_counts, [1, 1], "fmul_fast must lower for f32 and f64");
-    assert_eq!(fdiv_counts, [1, 1], "fdiv_fast must lower for f32 and f64");
-    assert_eq!(frem_counts, [1, 1], "frem_fast must lower for f32 and f64");
-
-    Ok(())
-}
-
-#[test]
-fn test_inline_ptx_op_lowers_to_inline_asm_attrs() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
-    let input = entry.deref(&ctx).get_argument(0);
-
-    let inline_ptx = nvvm::InlinePtxOp::build(
-        &mut ctx,
-        vec![i32_ty.into()],
-        vec![input],
-        "add.u32 $0, $1, $1;",
-        "=r,r",
-        true,
-        true,
-    );
-    inline_ptx.insert_at_back(entry, &ctx);
-    let register_only_ptx = nvvm::InlinePtxOp::build(
-        &mut ctx,
-        vec![i32_ty.into()],
-        vec![input],
-        "mul.lo.u32 $0, $1, $1;",
-        "=r,r",
-        false,
-        true,
-    );
-    register_only_ptx.insert_at_back(entry, &ctx);
-    let may_diverge_ptx = nvvm::InlinePtxOp::build(
-        &mut ctx,
-        vec![i32_ty.into()],
-        vec![input],
-        "cvt.u32.u32 $0, $1;",
-        "=r,r",
-        false,
-        false,
-    );
-    may_diverge_ptx.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    let mut found_conservative = false;
-    let mut found_register_only = false;
-    let mut found_may_diverge = false;
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = inline_asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|s| String::from((*s).clone()));
-                match template.as_deref() {
-                    Some("add.u32 $0, $1, $1;") => {
-                        found_conservative = true;
-                        assert_eq!(
-                            inline_asm
-                                .get_attr_inline_asm_constraints(&ctx)
-                                .map(|s| String::from((*s).clone()))
-                                .as_deref(),
-                            Some("=r,r")
-                        );
-                        assert!(
-                            inline_asm
-                                .get_attr_inline_asm_convergent(&ctx)
-                                .is_some_and(|b| bool::from((*b).clone()))
-                        );
-                        assert!(llvm::inline_asm_sideeffect(
-                            &ctx,
-                            inline_asm.get_operation()
-                        ));
-                    }
-                    Some("mul.lo.u32 $0, $1, $1;") => {
-                        found_register_only = true;
-                        assert_eq!(
-                            inline_asm
-                                .get_attr_inline_asm_constraints(&ctx)
-                                .map(|s| String::from((*s).clone()))
-                                .as_deref(),
-                            Some("=r,r")
-                        );
-                        assert!(
-                            inline_asm
-                                .get_attr_inline_asm_convergent(&ctx)
-                                .is_some_and(|b| bool::from((*b).clone()))
-                        );
-                        assert!(!llvm::inline_asm_sideeffect(
-                            &ctx,
-                            inline_asm.get_operation()
-                        ));
-                    }
-                    Some("cvt.u32.u32 $0, $1;") => {
-                        found_may_diverge = true;
-                        assert_eq!(
-                            inline_asm
-                                .get_attr_inline_asm_constraints(&ctx)
-                                .map(|s| String::from((*s).clone()))
-                                .as_deref(),
-                            Some("=r,r")
-                        );
-                        assert!(
-                            inline_asm
-                                .get_attr_inline_asm_convergent(&ctx)
-                                .is_some_and(|b| !bool::from((*b).clone()))
-                        );
-                        assert!(!llvm::inline_asm_sideeffect(
-                            &ctx,
-                            inline_asm.get_operation()
-                        ));
-                    }
-                    _ => continue,
-                }
-            }
-        }
-    }
-
-    assert!(
-        found_conservative,
-        "Expected conservative inline PTX asm op"
-    );
-    assert!(
-        found_register_only,
-        "Expected register-only inline PTX asm op"
-    );
-    assert!(found_may_diverge, "Expected may-diverge inline PTX asm op");
-    Ok(())
-}
-
-#[test]
-fn test_multi_result_inline_ptx_lowers_to_struct_asm_and_extractvalues() -> Result<(), anyhow::Error>
-{
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::r#type::Typed;
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
-    let input = entry.deref(&ctx).get_argument(0);
-
-    let inline_ptx = nvvm::InlinePtxOp::build(
-        &mut ctx,
-        vec![i32_ty.into(), i32_ty.into()],
-        vec![input],
-        "add.u32 $0, $2, $2; mul.lo.u32 $1, $2, $2;",
-        "=r,=r,r",
-        true,
-        false,
-    );
-    let expected_location = Location::Named {
-        name: "source-inline-ptx".to_string(),
-        child_loc: Box::new(Location::Unknown),
-    };
-    inline_ptx
-        .deref_mut(&ctx)
-        .set_loc(expected_location.clone());
-    inline_ptx.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    let mut asm_result = None;
-    let mut extract_indices = Vec::new();
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
-            assert_eq!(
-                inline_asm.get_operation().deref(&ctx).loc(),
-                expected_location
-            );
-            assert_eq!(
-                inline_asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|s| String::from((*s).clone()))
-                    .as_deref(),
-                Some("add.u32 $0, $2, $2; mul.lo.u32 $1, $2, $2;")
-            );
-            assert_eq!(
-                inline_asm
-                    .get_attr_inline_asm_constraints(&ctx)
-                    .map(|s| String::from((*s).clone()))
-                    .as_deref(),
-                Some("=r,=r,r")
-            );
-            let result = inline_asm.get_operation().deref(&ctx).get_result(0);
-            let result_ty = result.get_type(&ctx);
-            let result_ty = result_ty.deref(&ctx);
-            let struct_ty = result_ty
-                .downcast_ref::<llvm_types::StructType>()
-                .expect("multi-output inline PTX must return an LLVM struct");
-            assert_eq!(struct_ty.num_fields(), 2);
-            for index in 0..2 {
-                assert_eq!(
-                    struct_ty
-                        .field_type(index)
-                        .deref(&ctx)
-                        .downcast_ref::<IntegerType>()
-                        .expect("multi-output inline PTX struct field must stay i32")
-                        .width(),
-                    32
-                );
-            }
-            asm_result = Some(result);
-        } else if let Some(extract) = Operation::get_op::<llvm::ExtractValueOp>(op, &ctx) {
-            assert_eq!(extract.get_operation().deref(&ctx).loc(), expected_location);
-            let aggregate = extract.get_operation().deref(&ctx).get_operand(0);
-            assert_eq!(
-                Some(aggregate),
-                asm_result,
-                "extractvalue must consume the struct-returning asm result"
-            );
-            extract_indices.push(extract.indices(&ctx));
-        }
-    }
-
-    assert!(
-        asm_result.is_some(),
-        "Expected struct-returning inline PTX asm op"
-    );
-    assert_eq!(
-        extract_indices,
-        vec![vec![0], vec![1]],
-        "each output must be extracted once, in constraint order"
-    );
-    Ok(())
-}
-
-#[test]
-fn test_inline_ptx_supports_thirty_two_tied_f32_results() -> Result<(), anyhow::Error> {
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::types::FP32Type;
-    use pliron::r#type::Typed;
-
-    const ACCUMULATOR_LEN: usize = 32;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty.into(); ACCUMULATOR_LEN]);
-
-    let inputs = (0..ACCUMULATOR_LEN)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect::<Vec<_>>();
-
-    let template = (0..ACCUMULATOR_LEN)
-        .map(|index| format!("mov.f32 ${index}, ${index};"))
-        .collect::<Vec<_>>()
-        .join(" ");
-
-    let mut constraints = vec!["=f".to_string(); ACCUMULATOR_LEN];
-    constraints.extend((0..ACCUMULATOR_LEN).map(|index| index.to_string()));
-    let constraints = constraints.join(",");
-
-    let inline_ptx = nvvm::InlinePtxOp::build(
-        &mut ctx,
-        vec![f32_ty.into(); ACCUMULATOR_LEN],
-        inputs,
-        &template,
-        &constraints,
-        true,
-        true,
-    );
-    inline_ptx.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut asm_result = None;
-    let mut extract_indices = Vec::new();
-
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
-            assert_eq!(
-                inline_asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .as_deref(),
-                Some(template.as_str()),
-            );
-
-            assert_eq!(
-                inline_asm
-                    .get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .as_deref(),
-                Some(constraints.as_str()),
-            );
-
-            let result = inline_asm.get_operation().deref(&ctx).get_result(0);
-            let result_ty = result.get_type(&ctx);
-            let result_ty = result_ty.deref(&ctx);
-
-            let struct_ty = result_ty
-                .downcast_ref::<llvm_types::StructType>()
-                .expect("32-output inline PTX must return an LLVM struct");
-
-            assert_eq!(
-                struct_ty.num_fields(),
-                ACCUMULATOR_LEN,
-                "inline PTX must return exactly 32 accumulator values",
-            );
-
-            for index in 0..ACCUMULATOR_LEN {
-                assert!(
-                    struct_ty
-                        .field_type(index)
-                        .deref(&ctx)
-                        .downcast_ref::<FP32Type>()
-                        .is_some(),
-                    "inline PTX result field {index} must remain f32",
-                );
-            }
-
-            assert!(
-                asm_result.replace(result).is_none(),
-                "expected exactly one inline PTX operation",
-            );
-        } else if let Some(extract) = Operation::get_op::<llvm::ExtractValueOp>(op, &ctx) {
-            let aggregate = extract.get_operation().deref(&ctx).get_operand(0);
-
-            assert_eq!(
-                Some(aggregate),
-                asm_result,
-                "extractvalue must consume the struct-returning asm result",
-            );
-
-            extract_indices.push(extract.indices(&ctx));
-        }
-    }
-
-    assert!(
-        asm_result.is_some(),
-        "expected a struct-returning inline PTX asm operation",
-    );
-
-    let expected_indices = (0..ACCUMULATOR_LEN)
-        .map(|index| vec![index as u32])
-        .collect::<Vec<_>>();
-
-    assert_eq!(
-        extract_indices, expected_indices,
-        "each accumulator output must be extracted exactly once and in constraint order",
-    );
-
-    Ok(())
-}
-
-/// The mir-importer encodes `core::sync::atomic::compiler_fence` (issue #781)
-/// as an empty, volatile, non-convergent inline-PTX block whose only content
-/// is a `~{memory}` clobber. It must lower to a void side-effecting inline asm
-/// call with the clobber intact and no instruction text, so no hardware
-/// `fence` or `membar` can reach the emitted PTX.
-#[test]
-fn test_compiler_fence_encoding_lowers_to_empty_sideeffect_asm() -> Result<(), anyhow::Error> {
-    use llvm_export::types as llvm_types;
-    use pliron::r#type::Typed;
-
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
-
-    let barrier = nvvm::InlinePtxOp::build(&mut ctx, vec![], vec![], "", "~{memory}", true, false);
-    barrier.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    let mut found_barrier = false;
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            continue;
-        };
-        assert!(
-            !found_barrier,
-            "expected exactly one inline asm op in the lowered kernel"
-        );
-        found_barrier = true;
-
-        let template = inline_asm
-            .get_attr_inline_asm_template(&ctx)
-            .map(|s| String::from((*s).clone()));
-        assert_eq!(
-            template.as_deref(),
-            Some(""),
-            "compiler fence must emit no PTX instruction"
-        );
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_constraints(&ctx)
-                .map(|s| String::from((*s).clone()))
-                .as_deref(),
-            Some("~{memory}"),
-            "compiler fence must keep its memory clobber"
-        );
-        assert!(
-            llvm::inline_asm_sideeffect(&ctx, inline_asm.get_operation()),
-            "compiler fence must stay side-effecting so the optimizer cannot drop it"
-        );
-        assert!(
-            inline_asm
-                .get_attr_inline_asm_convergent(&ctx)
-                .is_some_and(|b| !bool::from((*b).clone())),
-            "compiler fence must not be convergent"
-        );
-        // The zero-result lowering path models the void call as a single
-        // result of `llvm.void` type, so assert on the type rather than on
-        // the result count.
-        let result_ty = inline_asm
-            .get_operation()
-            .deref(&ctx)
-            .get_result(0)
-            .get_type(&ctx);
-        assert!(
-            result_ty
-                .deref(&ctx)
-                .downcast_ref::<llvm_types::VoidType>()
-                .is_some(),
-            "compiler fence lowers to a void inline asm call"
-        );
-    }
-
-    assert!(
-        found_barrier,
-        "expected the compiler-fence inline asm op in the lowered kernel"
-    );
-    Ok(())
-}
-
-#[test]
-fn test_cluster_grid_compatibility_ops_keep_original_lowering() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_type = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
-    for op_info in [
-        nvvm::ReadPtxSregClusterIdxOp::get_concrete_op_info(),
-        nvvm::ReadPtxSregNclusterIdOp::get_concrete_op_info(),
-    ] {
-        Operation::new(&mut ctx, op_info, vec![i32_type.into()], vec![], vec![], 0)
-            .insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let lowered = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(op, &ctx))
-        .filter_map(|asm| {
-            let template = asm
-                .get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))?;
-            (template.contains("%clusterid") || template.contains("%nclusterid"))
-                .then_some((template, asm))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(lowered.len(), 2);
-    assert!(lowered.iter().any(|(template, _)| {
-        template
-            == "{ .reg .u32 %cx, %cy, %cz, %nx, %ny, %nxy, %xy; mov.u32 %cx, %clusterid.x; mov.u32 %cy, %clusterid.y; mov.u32 %cz, %clusterid.z; mov.u32 %nx, %nclusterid.x; mov.u32 %ny, %nclusterid.y; mul.lo.u32 %nxy, %nx, %ny; mad.lo.u32 %xy, %cy, %nx, %cx; mad.lo.u32 $0, %cz, %nxy, %xy; }"
-    }));
-    assert!(lowered.iter().any(|(template, _)| {
-        template
-            == "{ .reg .u32 %nx, %ny, %nz, %nxy; mov.u32 %nx, %nclusterid.x; mov.u32 %ny, %nclusterid.y; mov.u32 %nz, %nclusterid.z; mul.lo.u32 %nxy, %nx, %ny; mul.lo.u32 $0, %nxy, %nz; }"
-    }));
-    for (_, asm) in lowered {
-        assert_eq!(
-            asm.get_attr_inline_asm_constraints(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some("=r")
-        );
-        assert_eq!(llvm::asm_kind(&ctx, &asm), llvm::AsmKind::Convergent);
-    }
-    Ok(())
-}
-
-/// Regression cover for PR #141: comparisons whose operand is a bool phi.
-///
-/// Bools are signless i1, which `can_convert_type` rejects (signless is
-/// already the LLVM form), so DialectConversion records no type history for
-/// a bool block argument. `is_signed_int_op` used to error out for such
-/// operands ("expected IntegerType or MirPtrType operand in arithmetic op");
-/// it must instead fall back to the live operand type and lower the
-/// comparison as unsigned.
-///
-/// The function mirrors the MIR of a short-circuit kernel:
-///
-/// ```text
-/// let p = a || b;            // bool phi: merge block argument
-/// out = (p == q, p < q);     // icmp eq i1 / icmp ult i1
-/// ```
-///
-/// ```text
-/// bb0(a: i1, b: i1, q: i1):  mir.cond_br a, bb2(a), bb1()
-/// bb1():                     mir.goto bb2(b)
-/// bb2(p: i1):                mir.eq p, q ; mir.lt p, q ; mir.return
-/// ```
-#[test]
-fn test_bool_phi_cmp_lowers_to_unsigned_i1_icmp() -> Result<(), anyhow::Error> {
-    use llvm_export::attributes::ICmpPredicateAttr;
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::op_interfaces::OperandSegmentInterface;
-    use pliron::builtin::types::{FunctionType, IntegerType, Signedness};
-    use pliron::r#type::Typed;
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
-    let module_ptr = module.get_operation();
-
-    let bool_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let arg_tys: Vec<pliron::r#type::TypeHandle> =
-        vec![bool_ty.into(), bool_ty.into(), bool_ty.into()];
-    let func_name = "bool_phi_cmp";
-    let func_ty = FunctionType::get(&ctx, arg_tys.clone(), vec![]);
-
-    let func_op_ptr = Operation::new(
-        &mut ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
-    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
-    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
-
-    let region = func.get_operation().deref(&ctx).get_region(0);
-
-    // bb0(a, b, q): the function entry.
-    let bb0 = BasicBlock::new(&mut ctx, None, arg_tys);
-    bb0.insert_at_back(region, &ctx);
-    let a = bb0.deref(&ctx).get_argument(0);
-    let b = bb0.deref(&ctx).get_argument(1);
-    let q = bb0.deref(&ctx).get_argument(2);
-
-    // bb1(): the short-circuit "evaluate b" block.
-    let bb1 = BasicBlock::new(&mut ctx, None, vec![]);
-    bb1.insert_at_back(region, &ctx);
-
-    // bb2(p): the merge block; `p` is the bool phi.
-    let bb2 = BasicBlock::new(&mut ctx, None, vec![bool_ty.into()]);
-    bb2.insert_at_back(region, &ctx);
-    let p = bb2.deref(&ctx).get_argument(0);
-
-    // bb0: cond_br a, bb2(a), bb1(). On the true edge `a` is true, so
-    // passing `a` itself is `a || b` without needing a constant.
-    let (flat_operands, segment_sizes) =
-        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![a], vec![a], vec![]]);
-    let cond_br = Operation::new(
-        &mut ctx,
-        mir::MirCondBranchOp::get_concrete_op_info(),
-        vec![],
-        flat_operands,
-        vec![bb2, bb1],
-        0,
-    );
-    Operation::get_op::<mir::MirCondBranchOp>(cond_br, &ctx)
-        .expect("MirCondBranchOp")
-        .set_operand_segment_sizes(&ctx, segment_sizes);
-    cond_br.insert_at_back(bb0, &ctx);
-
-    // bb1: goto bb2(b).
-    let goto = Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![b],
-        vec![bb2],
-        0,
-    );
-    goto.insert_at_back(bb1, &ctx);
-
-    // bb2: p == q, then p < q.
-    for info in [
-        mir::MirEqOp::get_concrete_op_info(),
-        mir::MirLtOp::get_concrete_op_info(),
-    ] {
-        let cmp = Operation::new(&mut ctx, info, vec![bool_ty.into()], vec![p, q], vec![], 0);
-        cmp.insert_at_back(bb2, &ctx);
-    }
-    let ret_op = Operation::new(
-        &mut ctx,
-        mir::MirReturnOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    );
-    ret_op.insert_at_back(bb2, &ctx);
-
-    let module_region = module.get_operation().deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    func.get_operation().insert_at_back(module_block, &ctx);
-
-    // Before the fallback, this failed with "expected IntegerType or
-    // MirPtrType operand in arithmetic op".
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    let mut icmps = Vec::new();
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != func_name {
-            continue;
-        }
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                if let Some(icmp) = Operation::get_op::<llvm::ICmpOp>(body_op, &ctx) {
-                    let lhs_ty = body_op.deref(&ctx).get_operand(0).get_type(&ctx);
-                    icmps.push((icmp.predicate(&ctx), lhs_ty));
-                }
-            }
-        }
-    }
-
-    let i1: pliron::r#type::TypeHandle = bool_ty.into();
-    assert_eq!(
-        icmps,
-        vec![(ICmpPredicateAttr::EQ, i1), (ICmpPredicateAttr::ULT, i1),],
-        "bool-phi comparisons must lower to `icmp eq i1` and `icmp ult i1`"
-    );
-    Ok(())
-}
-
-// =============================================================================
-// Scalar math lowering tests
-// =============================================================================
-
-#[test]
-fn test_ex2_approx_f16_uses_exact_pure_i16_inline_ptx_on_both_backends() -> Result<(), anyhow::Error>
-{
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::r#type::Typed;
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        let mut ctx = make_test_ctx();
-        let i16_ty = IntegerType::get(&ctx, 16, Signedness::Unsigned);
-        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i16_ty.into()]);
-        let operand = entry.deref(&ctx).get_argument(0);
-        nvvm::ScalarMathOp::build(
-            &mut ctx,
-            operand,
-            nvvm::ScalarMathFormatAttr::F16,
-            nvvm::ScalarMathOperationAttr::Ex2,
-            nvvm::ScalarMathPrecisionAttr::Approx,
-            nvvm::ScalarMathSubnormalAttr::Preserve,
-        )
-        .insert_at_back(entry, &ctx);
-        append_return(&mut ctx, entry);
-
-        mir_lower::lower_mir_to_llvm_with_options(
-            &mut ctx,
-            module_ptr,
-            mir_lower::LoweringOptions {
-                intrinsic_backend: backend,
-                ..Default::default()
-            },
-        )
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-        let inline_asm = lowered_kernel_body(&ctx, module_ptr)
-            .into_iter()
-            .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(op, &ctx))
-            .collect::<Vec<_>>();
-        assert_eq!(inline_asm.len(), 1);
-        let inline_asm = &inline_asm[0];
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some("ex2.approx.f16 $0, $1;")
-        );
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_constraints(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some("=h,h")
-        );
-        assert_eq!(llvm::asm_kind(&ctx, inline_asm), llvm::AsmKind::Pure);
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_convergent(&ctx)
-                .map(|value| bool::from((*value).clone())),
-            Some(false)
-        );
-
-        let op = inline_asm.get_operation().deref(&ctx);
-        assert_eq!(op.get_num_operands(), 1);
-        assert_eq!(op.get_num_results(), 1);
-        for ty in [
-            op.get_operand(0).get_type(&ctx),
-            op.get_result(0).get_type(&ctx),
-        ] {
-            let ty = ty.deref(&ctx);
-            let integer = ty
-                .downcast_ref::<IntegerType>()
-                .expect("f16 values use an i16 transport type");
-            assert_eq!(integer.width(), 16);
-        }
-
-        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-            .expect("ex2.approx.f16 module exports to LLVM IR");
-        assert!(
-            ir.contains("call i16 asm \"ex2.approx.f16 $0, $1;\", \"=h,h\"(i16"),
-            "{ir}"
-        );
-        assert!(!ir.contains("asm sideeffect"), "{ir}");
-        assert!(!ir.contains("~{memory}"), "{ir}");
-    }
-    Ok(())
-}
-
-#[test]
-fn test_ex2_approx_f16_lowering_rejects_wrong_type_and_format() {
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        let mut wrong_type_ctx = make_test_ctx();
-        let f32_ty = FP32Type::get(&wrong_type_ctx);
-        let (module_ptr, entry) = build_test_kernel(&mut wrong_type_ctx, vec![f32_ty.into()]);
-        let operand = entry.deref(&wrong_type_ctx).get_argument(0);
-        nvvm::ScalarMathOp::build(
-            &mut wrong_type_ctx,
-            operand,
-            nvvm::ScalarMathFormatAttr::F16,
-            nvvm::ScalarMathOperationAttr::Ex2,
-            nvvm::ScalarMathPrecisionAttr::Approx,
-            nvvm::ScalarMathSubnormalAttr::Preserve,
-        )
-        .insert_at_back(entry, &wrong_type_ctx);
-        append_return(&mut wrong_type_ctx, entry);
-        let error = mir_lower::lower_mir_to_llvm_with_options(
-            &mut wrong_type_ctx,
-            module_ptr,
-            mir_lower::LoweringOptions {
-                intrinsic_backend: backend,
-                ..Default::default()
-            },
-        )
-        .expect_err("an f16 operation with an f32 operand must fail closed")
-        .to_string();
-        assert!(
-            error.contains("nvvm.scalar_math types do not match its format"),
-            "{error}"
-        );
-
-        let mut wrong_format_ctx = make_test_ctx();
-        let i16_ty = IntegerType::get(&wrong_format_ctx, 16, Signedness::Unsigned);
-        let (module_ptr, entry) = build_test_kernel(&mut wrong_format_ctx, vec![i16_ty.into()]);
-        let operand = entry.deref(&wrong_format_ctx).get_argument(0);
-        nvvm::ScalarMathOp::build(
-            &mut wrong_format_ctx,
-            operand,
-            nvvm::ScalarMathFormatAttr::F16,
-            nvvm::ScalarMathOperationAttr::Ex2,
-            nvvm::ScalarMathPrecisionAttr::Approx,
-            nvvm::ScalarMathSubnormalAttr::Ftz,
-        )
-        .insert_at_back(entry, &wrong_format_ctx);
-        append_return(&mut wrong_format_ctx, entry);
-        let error = mir_lower::lower_mir_to_llvm_with_options(
-            &mut wrong_format_ctx,
-            module_ptr,
-            mir_lower::LoweringOptions {
-                intrinsic_backend: backend,
-                ..Default::default()
-            },
-        )
-        .expect_err("unadmitted ex2.approx.ftz.f16 must fail closed")
-        .to_string();
-        assert!(
-            error.contains("nvvm.scalar_math variant is not admitted"),
-            "{error}"
-        );
-    }
-}
-
-// =============================================================================
-// Integer dot product (dp4a / dp2a) lowering tests
-// =============================================================================
-
-const DOT_PRODUCT_TYPED_INTRINSICS: [&str; 4] = [
-    "llvm_nvvm_idp4a_s_s",
-    "llvm_nvvm_idp4a_u_u",
-    "llvm_nvvm_idp2a_s_s",
-    "llvm_nvvm_idp2a_u_u",
-];
-
-const DOT_PRODUCT_PTX: [&str; 4] = [
-    "dp4a.s32.s32 $0, $1, $2, $3;",
-    "dp4a.u32.u32 $0, $1, $2, $3;",
-    "dp2a.lo.s32.s32 $0, $1, $2, $3;",
-    "dp2a.lo.u32.u32 $0, $1, $2, $3;",
-];
-
-fn lower_all_dot_product_forms(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![i32_ty.into(), i32_ty.into(), i32_ty.into()]);
-    let operands = (0..3)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect::<Vec<_>>();
-    for op_info in [
-        nvvm::Dp4aS32Op::get_concrete_op_info(),
-        nvvm::Dp4aU32Op::get_concrete_op_info(),
-        nvvm::Dp2aS32Op::get_concrete_op_info(),
-        nvvm::Dp2aU32Op::get_concrete_op_info(),
-    ] {
-        Operation::new(
-            &mut ctx,
-            op_info,
-            vec![i32_ty.into()],
-            operands.clone(),
-            vec![],
-            0,
-        )
-        .insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn test_dot_product_llvm_nvptx_uses_typed_intrinsics_and_low_selector() -> Result<(), anyhow::Error>
-{
-    use pliron::builtin::attributes::IntegerAttr;
-
-    let (ctx, module_ptr) = lower_all_dot_product_forms(mir_lower::IntrinsicBackend::LlvmNvptx)?;
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let mut calls = Vec::new();
-    for op in body {
-        assert!(
-            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-            "LLVM-NVPTX dot products must use typed intrinsics"
-        );
-        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-            continue;
-        };
-        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-            continue;
-        };
-        let callee = callee.to_string();
-        if !callee.starts_with("llvm_nvvm_idp") {
-            continue;
-        }
-        let expected_arity = if callee.contains("idp2a") { 4 } else { 3 };
-        assert_eq!(op.deref(&ctx).get_num_operands(), expected_arity);
-        if expected_arity == 4 {
-            let selector = op.deref(&ctx).get_operand(2);
-            let defining_op = selector.defining_op().expect("selector is a constant");
-            let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
-                .expect("selector is an LLVM constant");
-            let attribute = constant.get_value(&ctx);
-            let integer = attribute
-                .downcast_ref::<IntegerAttr>()
-                .expect("selector constant is an integer");
-            assert_eq!(integer.value().bw(), 1);
-            assert_eq!(integer.value().to_u64(), 0, "dp2a must select `.lo`");
-        }
-        calls.push(callee);
-    }
-    calls.sort();
-    let mut expected = DOT_PRODUCT_TYPED_INTRINSICS.map(str::to_owned);
-    expected.sort();
-    assert_eq!(calls, expected);
-    Ok(())
-}
-
-#[test]
-fn test_dot_product_libnvvm_uses_exact_pure_inline_ptx() -> Result<(), anyhow::Error> {
-    let (ctx, module_ptr) = lower_all_dot_product_forms(mir_lower::IntrinsicBackend::LibNvvm)?;
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let mut inline_ptx = Vec::new();
-    for op in body {
-        assert!(
-            Operation::get_op::<llvm::CallOp>(op, &ctx).is_none(),
-            "libNVVM dot products must not use typed intrinsic calls"
-        );
-        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            continue;
-        };
-        inline_ptx.push(
-            inline_asm
-                .get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .unwrap_or_default(),
-        );
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_constraints(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some("=r,r,r,r")
-        );
-        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
-        assert_eq!(op.deref(&ctx).get_num_operands(), 3);
-        assert_eq!(op.deref(&ctx).get_num_results(), 1);
-    }
-    inline_ptx.sort();
-    let mut expected = DOT_PRODUCT_PTX.map(str::to_owned);
-    expected.sort();
-    assert_eq!(inline_ptx, expected);
-    Ok(())
-}
-
-// =============================================================================
-// Byte permutation lowering tests
-// =============================================================================
-
-const PRMT_TYPED_INTRINSICS: [(&str, usize); 7] = [
-    ("llvm_nvvm_prmt", 3),
-    ("llvm_nvvm_prmt_f4e", 3),
-    ("llvm_nvvm_prmt_b4e", 3),
-    ("llvm_nvvm_prmt_rc8", 2),
-    ("llvm_nvvm_prmt_ecl", 2),
-    ("llvm_nvvm_prmt_ecr", 2),
-    ("llvm_nvvm_prmt_rc16", 2),
-];
-
-const PRMT_INLINE_PTX: [(&str, &str, usize); 7] = [
-    ("prmt.b32 $0, $1, $2, $3;", "=r,r,r,r", 3),
-    ("prmt.b32.f4e $0, $1, $2, $3;", "=r,r,r,r", 3),
-    ("prmt.b32.b4e $0, $1, $2, $3;", "=r,r,r,r", 3),
-    ("prmt.b32.rc8 $0, $1, 0, $2;", "=r,r,r", 2),
-    ("prmt.b32.ecl $0, $1, 0, $2;", "=r,r,r", 2),
-    ("prmt.b32.ecr $0, $1, 0, $2;", "=r,r,r", 2),
-    ("prmt.b32.rc16 $0, $1, 0, $2;", "=r,r,r", 2),
-];
-
-fn lower_all_prmt_modes(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![i32_ty.into(), i32_ty.into(), i32_ty.into()]);
-    let operands = (0..3)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect::<Vec<_>>();
-
-    for mode in [
-        nvvm::PrmtModeAttr::Generic,
-        nvvm::PrmtModeAttr::F4e,
-        nvvm::PrmtModeAttr::B4e,
-    ] {
-        nvvm::PrmtOp::build(&mut ctx, operands.clone(), mode).insert_at_back(entry, &ctx);
-    }
-    for mode in [
-        nvvm::PrmtModeAttr::Rc8,
-        nvvm::PrmtModeAttr::Ecl,
-        nvvm::PrmtModeAttr::Ecr,
-        nvvm::PrmtModeAttr::Rc16,
-    ] {
-        nvvm::PrmtOp::build(&mut ctx, vec![operands[0], operands[2]], mode)
-            .insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn test_prmt_llvm_nvptx_uses_exact_typed_intrinsics() -> Result<(), anyhow::Error> {
-    let (ctx, module_ptr) = lower_all_prmt_modes(mir_lower::IntrinsicBackend::LlvmNvptx)?;
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let mut calls = Vec::new();
-    for op in body {
-        assert!(
-            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-            "LLVM-NVPTX byte permutations must use typed intrinsics"
-        );
-        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-            continue;
-        };
-        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-            continue;
-        };
-        let callee = callee.to_string();
-        let Some((_, expected_arity)) = PRMT_TYPED_INTRINSICS
-            .iter()
-            .find(|(expected, _)| *expected == callee)
-        else {
-            continue;
-        };
-        assert_eq!(op.deref(&ctx).get_num_operands(), *expected_arity);
-        calls.push((callee, *expected_arity));
-    }
-    calls.sort();
-    let mut expected = PRMT_TYPED_INTRINSICS.map(|(name, arity)| (name.to_owned(), arity));
-    expected.sort();
-    assert_eq!(calls, expected);
-    Ok(())
-}
-
-#[test]
-fn test_prmt_libnvvm_uses_exact_pure_inline_ptx() -> Result<(), anyhow::Error> {
-    let (ctx, module_ptr) = lower_all_prmt_modes(mir_lower::IntrinsicBackend::LibNvvm)?;
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let mut inline_ptx = Vec::new();
-    for op in body {
-        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-        {
-            assert!(
-                !callee.to_string().starts_with("llvm_nvvm_prmt"),
-                "libNVVM byte permutations must not use typed intrinsic calls"
-            );
-        }
-        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            continue;
-        };
-        let template = inline_asm
-            .get_attr_inline_asm_template(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .unwrap_or_default();
-        let Some((_, expected_constraints, expected_arity)) = PRMT_INLINE_PTX
-            .iter()
-            .find(|(expected, _, _)| *expected == template)
-        else {
-            continue;
-        };
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_constraints(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some(*expected_constraints)
-        );
-        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
-        assert_eq!(op.deref(&ctx).get_num_operands(), *expected_arity);
-        assert_eq!(op.deref(&ctx).get_num_results(), 1);
-        inline_ptx.push((template, *expected_constraints, *expected_arity));
-    }
-    inline_ptx.sort();
-    let mut expected = PRMT_INLINE_PTX
-        .map(|(template, constraints, arity)| (template.to_owned(), constraints, arity));
-    expected.sort();
-    assert_eq!(inline_ptx, expected);
-    Ok(())
-}
-
-fn lower_sync_threads(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
-    Operation::new(
-        &mut ctx,
-        nvvm::Barrier0Op::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        0,
-    )
-    .insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn test_sync_threads_llvm_nvptx_uses_typed_intrinsic_with_fixed_zero() -> Result<(), anyhow::Error>
-{
-    use pliron::builtin::attributes::IntegerAttr;
-
-    let (ctx, module_ptr) = lower_sync_threads(mir_lower::IntrinsicBackend::LlvmNvptx)?;
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let mut found = false;
-    for op in body {
-        assert!(
-            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-            "LLVM-NVPTX sync_threads must use the typed intrinsic"
-        );
-        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-            continue;
-        };
-        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-            continue;
-        };
-        if callee.to_string() != "llvm_nvvm_barrier_cta_sync_aligned_all" {
-            continue;
-        }
-        let call = op.deref(&ctx);
-        assert_eq!(call.get_num_operands(), 1);
-        let barrier_id = call.get_operand(0);
-        let defining_op = barrier_id.defining_op().expect("barrier ID is constant");
-        let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
-            .expect("barrier ID is an LLVM constant");
-        let value = constant.get_value(&ctx);
-        let integer = value
-            .downcast_ref::<IntegerAttr>()
-            .expect("barrier ID is an integer");
-        assert_eq!(integer.value().bw(), 32);
-        assert_eq!(integer.value().to_u64(), 0);
-        found = true;
-    }
-    assert!(found, "modern typed CTA barrier call was not emitted");
-
-    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-        .map_err(|error| anyhow::anyhow!(error))?;
-    assert!(ir.contains("@llvm.nvvm.barrier.cta.sync.aligned.all(i32 0)"));
-    assert!(!ir.contains("@llvm.nvvm.barrier0"));
-    Ok(())
-}
-
-#[test]
-fn test_sync_threads_libnvvm_uses_exact_convergent_inline_ptx() -> Result<(), anyhow::Error> {
-    let (ctx, module_ptr) = lower_sync_threads(mir_lower::IntrinsicBackend::LibNvvm)?;
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let mut found = false;
-    for op in body {
-        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-                && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-            {
-                assert_ne!(callee.to_string(), "llvm_nvvm_barrier_cta_sync_aligned_all");
-            }
-            continue;
-        };
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some("bar.sync 0;")
-        );
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_constraints(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some("~{memory}")
-        );
-        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Convergent);
-        assert_eq!(op.deref(&ctx).get_num_operands(), 0);
-        found = true;
-    }
-    assert!(found, "exact libNVVM barrier inline PTX was not emitted");
-
-    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-        .map_err(|error| anyhow::anyhow!(error))?;
-    assert!(
-        ir.contains("call void asm sideeffect \"bar.sync 0;\", \"~{memory}\"() #0"),
-        "{ir}"
-    );
-    assert!(ir.contains("attributes #0 = { convergent }"), "{ir}");
-    assert!(!ir.contains("@llvm.nvvm.barrier.cta.sync.aligned.all"));
-    Ok(())
-}
-
-fn lower_warp_barrier(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
-    let member_mask = entry.deref(&ctx).get_argument(0);
-    nvvm::BarWarpSyncOp::build(&mut ctx, member_mask).insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn test_warp_barrier_uses_typed_intrinsic_on_both_backends() -> Result<(), anyhow::Error> {
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        let (ctx, module_ptr) = lower_warp_barrier(backend)?;
-        let body = lowered_kernel_body(&ctx, module_ptr);
-        let mut calls = 0;
-        for op in body {
-            assert!(
-                Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-                "warp barrier must use its typed intrinsic"
-            );
-            let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-                continue;
-            };
-            let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-                continue;
-            };
-            if callee.to_string() == "llvm_nvvm_bar_warp_sync" {
-                assert_eq!(op.deref(&ctx).get_num_operands(), 1);
-                assert_eq!(op.deref(&ctx).get_num_results(), 1);
-                calls += 1;
-            }
-        }
-        assert_eq!(calls, 1, "expected one typed warp-barrier call");
-
-        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-            .map_err(|error| anyhow::anyhow!(error))?;
-        assert!(ir.contains("@llvm.nvvm.bar.warp.sync(i32"), "{ir}");
-    }
-    Ok(())
-}
-
-// =============================================================================
-// cp.async lowering tests
-// =============================================================================
-
-fn lower_all_classic_cp_async(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let mut ctx = make_test_ctx();
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let dst_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
-    let src32_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
-    let src8_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
-    let (module_ptr, entry) = build_test_kernel(
-        &mut ctx,
-        vec![
-            dst_ty.into(),
-            src32_ty.into(),
-            src8_ty.into(),
-            u32_ty.into(),
-        ],
-    );
-    let dst = entry.deref(&ctx).get_argument(0);
-    let src32 = entry.deref(&ctx).get_argument(1);
-    let src8 = entry.deref(&ctx).get_argument(2);
-    let source_size = entry.deref(&ctx).get_argument(3);
-
-    let zero_op = Operation::new(
-        &mut ctx,
-        mir::MirConstantOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    mir::MirConstantOp::new(zero_op).set_attr_value(
-        &ctx,
-        IntegerAttr::new(u32_ty, APInt::from_u32(0, NonZeroUsize::new(32).unwrap())),
-    );
-    zero_op.insert_at_back(entry, &ctx);
-    let zero = zero_op.deref(&ctx).get_result(0);
-
-    for copy in [
-        nvvm::CpAsyncCa4Op::build(&mut ctx, dst, src32),
-        nvvm::CpAsyncCa8Op::build(&mut ctx, dst, src32),
-        nvvm::CpAsyncCa16Op::build(&mut ctx, dst, src32),
-        nvvm::CpAsyncCaZfill4Op::build(&mut ctx, dst, src8, source_size),
-        nvvm::CpAsyncCaZfill8Op::build(&mut ctx, dst, src8, source_size),
-        nvvm::CpAsyncCaZfill16Op::build(&mut ctx, dst, src8, source_size),
-        nvvm::CpAsyncCg16Op::build(&mut ctx, dst, src32),
-        nvvm::CpAsyncCgZfill16Op::build(&mut ctx, dst, src8, source_size),
-    ] {
-        copy.insert_at_back(entry, &ctx);
-    }
-    for control in [
-        nvvm::CpAsyncCommitGroupOp::build(&mut ctx),
-        nvvm::CpAsyncWaitGroupOp::build(&mut ctx, zero),
-        nvvm::CpAsyncWaitAllOp::build(&mut ctx),
-    ] {
-        control.insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-fn lower_all_cp_async_mbarrier(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let generic_ty = MirPtrType::get_generic(&mut ctx, u64_ty.into(), true);
-    let shared_ty = MirPtrType::get_shared(&mut ctx, u64_ty.into(), true);
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![generic_ty.into(), shared_ty.into()]);
-    let generic = entry.deref(&ctx).get_argument(0);
-    let shared = entry.deref(&ctx).get_argument(1);
-
-    for bridge in [
-        nvvm::CpAsyncMbarrierArriveOp::build(&mut ctx, shared),
-        nvvm::CpAsyncMbarrierArriveSharedOp::build(&mut ctx, generic),
-        nvvm::CpAsyncMbarrierArriveNoIncOp::build(&mut ctx, shared),
-        nvvm::CpAsyncMbarrierArriveNoIncSharedOp::build(&mut ctx, generic),
-    ] {
-        bridge.insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn test_generated_cp_async_mbarrier_preserves_backend_and_address_routes()
--> Result<(), anyhow::Error> {
-    use llvm_export::types::PointerType;
-    use pliron::r#type::Typed;
-
-    let typed = [
-        ("llvm_nvvm_cp_async_mbarrier_arrive", 0),
-        ("llvm_nvvm_cp_async_mbarrier_arrive_shared", 3),
-        ("llvm_nvvm_cp_async_mbarrier_arrive_noinc", 0),
-        ("llvm_nvvm_cp_async_mbarrier_arrive_noinc_shared", 3),
-    ];
-    let templates = [
-        ("cp.async.mbarrier.arrive.b64 [$0];", 0),
-        ("cp.async.mbarrier.arrive.shared.b64 [$0];", 3),
-        ("cp.async.mbarrier.arrive.noinc.b64 [$0];", 0),
-        ("cp.async.mbarrier.arrive.noinc.shared.b64 [$0];", 3),
-    ];
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        let (ctx, module_ptr) = lower_all_cp_async_mbarrier(backend)?;
-        let mut call_counts = [0usize; 4];
-        let mut asm_counts = [0usize; 4];
-
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) {
-                let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-                    continue;
-                };
-                let callee = callee.to_string();
-                let Some(index) = typed.iter().position(|(name, _)| callee == *name) else {
-                    continue;
-                };
-                call_counts[index] += 1;
-                let pointer = op.deref(&ctx).get_operand(0).get_type(&ctx);
-                assert_eq!(
-                    pointer
-                        .deref(&ctx)
-                        .downcast_ref::<PointerType>()
-                        .unwrap()
-                        .address_space(),
-                    typed[index].1
-                );
-            }
-            if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
-                let template = inline_asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .unwrap();
-                let Some(index) = templates
-                    .iter()
-                    .position(|(expected, _)| template == *expected)
-                else {
-                    continue;
-                };
-                asm_counts[index] += 1;
-                assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Convergent);
-                assert!(
-                    inline_asm
-                        .get_attr_inline_asm_convergent(&ctx)
-                        .is_some_and(|value| bool::from((*value).clone()))
-                );
-                assert_eq!(
-                    inline_asm
-                        .get_attr_inline_asm_constraints(&ctx)
-                        .map(|value| String::from((*value).clone()))
-                        .as_deref(),
-                    Some("l,~{memory}")
-                );
-                let pointer = op.deref(&ctx).get_operand(0).get_type(&ctx);
-                assert_eq!(
-                    pointer
-                        .deref(&ctx)
-                        .downcast_ref::<PointerType>()
-                        .unwrap()
-                        .address_space(),
-                    templates[index].1
-                );
-            }
-        }
-
-        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-            .map_err(|error| anyhow::anyhow!(error))?;
-        match backend {
-            mir_lower::IntrinsicBackend::LlvmNvptx => {
-                assert_eq!(call_counts, [1; 4]);
-                assert_eq!(asm_counts, [0; 4]);
-                assert!(
-                    ir.contains("@llvm.nvvm.cp.async.mbarrier.arrive(ptr"),
-                    "{ir}"
-                );
-                assert!(
-                    ir.contains("@llvm.nvvm.cp.async.mbarrier.arrive.shared(ptr addrspace(3)"),
-                    "{ir}"
-                );
-                assert!(
-                    ir.contains("@llvm.nvvm.cp.async.mbarrier.arrive.noinc(ptr"),
-                    "{ir}"
-                );
-                assert!(
-                    ir.contains(
-                        "@llvm.nvvm.cp.async.mbarrier.arrive.noinc.shared(ptr addrspace(3)"
-                    ),
-                    "{ir}"
-                );
-                assert!(!ir.contains("cp.async.mbarrier.arrive.b64 [$0]"), "{ir}");
-            }
-            mir_lower::IntrinsicBackend::LibNvvm => {
-                assert_eq!(call_counts, [0; 4]);
-                assert_eq!(asm_counts, [1; 4]);
-                assert!(!ir.contains("@llvm.nvvm.cp.async.mbarrier"), "{ir}");
-                for (template, _) in templates {
-                    assert!(ir.contains(template), "{ir}");
-                }
-                assert!(ir.contains("asm sideeffect"), "{ir}");
-                assert!(ir.contains("convergent"), "{ir}");
-            }
-        }
-    }
-    Ok(())
-}
-
-#[test]
-fn test_generated_cp_async_llvm_nvptx_uses_all_typed_intrinsics() -> Result<(), anyhow::Error> {
-    use llvm_export::types::PointerType;
-    use pliron::r#type::Typed;
-
-    let (ctx, module_ptr) = lower_all_classic_cp_async(mir_lower::IntrinsicBackend::LlvmNvptx)?;
-    let mut found = Vec::new();
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        assert!(
-            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-            "LLVM-NVPTX cp.async must use typed intrinsics"
-        );
-        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-            continue;
-        };
-        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-            continue;
-        };
-        let callee = callee.to_string();
-        if !callee.starts_with("llvm_nvvm_cp_async") {
-            continue;
-        }
-        if callee.contains("shared_global") {
-            let call = op.deref(&ctx);
-            let destination_ty = call.get_operand(0).get_type(&ctx);
-            let source_ty = call.get_operand(1).get_type(&ctx);
-            assert_eq!(
-                destination_ty
-                    .deref(&ctx)
-                    .downcast_ref::<PointerType>()
-                    .unwrap()
-                    .address_space(),
-                3
-            );
-            assert_eq!(
-                source_ty
-                    .deref(&ctx)
-                    .downcast_ref::<PointerType>()
-                    .unwrap()
-                    .address_space(),
-                1
-            );
-        }
-        found.push(callee);
-    }
-    found.sort();
-    let mut expected = [
-        "llvm_nvvm_cp_async_ca_shared_global_4",
-        "llvm_nvvm_cp_async_ca_shared_global_4_s",
-        "llvm_nvvm_cp_async_ca_shared_global_8",
-        "llvm_nvvm_cp_async_ca_shared_global_8_s",
-        "llvm_nvvm_cp_async_ca_shared_global_16",
-        "llvm_nvvm_cp_async_ca_shared_global_16_s",
-        "llvm_nvvm_cp_async_cg_shared_global_16",
-        "llvm_nvvm_cp_async_cg_shared_global_16_s",
-        "llvm_nvvm_cp_async_commit_group",
-        "llvm_nvvm_cp_async_wait_all",
-        "llvm_nvvm_cp_async_wait_group",
-    ]
-    .map(str::to_owned);
-    expected.sort();
-    assert_eq!(found, expected);
-    Ok(())
-}
-
-#[test]
-fn test_generated_cp_async_libnvvm_uses_all_exact_inline_ptx() -> Result<(), anyhow::Error> {
-    let (ctx, module_ptr) = lower_all_classic_cp_async(mir_lower::IntrinsicBackend::LibNvvm)?;
-    let mut lowered = Vec::new();
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            continue;
-        };
-        assert_eq!(llvm::asm_kind(&ctx, &asm), llvm::AsmKind::SideEffect);
-        assert!(
-            asm.get_attr_inline_asm_convergent(&ctx)
-                .is_some_and(|value| !bool::from((*value).clone()))
-        );
-        lowered.push((
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .unwrap(),
-            asm.get_attr_inline_asm_constraints(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .unwrap(),
-        ));
-    }
-
-    let expected = [
-        (
-            "cp.async.ca.shared.global [%smem32], [%gmem64], 4;",
-            "l,l,~{memory}",
-        ),
-        (
-            "cp.async.ca.shared.global [%smem32], [%gmem64], 8;",
-            "l,l,~{memory}",
-        ),
-        (
-            "cp.async.ca.shared.global [%smem32], [%gmem64], 16;",
-            "l,l,~{memory}",
-        ),
-        (
-            "cp.async.ca.shared.global [%smem32], [%gmem64], 4, $2;",
-            "l,l,r,~{memory}",
-        ),
-        (
-            "cp.async.ca.shared.global [%smem32], [%gmem64], 8, $2;",
-            "l,l,r,~{memory}",
-        ),
-        (
-            "cp.async.ca.shared.global [%smem32], [%gmem64], 16, $2;",
-            "l,l,r,~{memory}",
-        ),
-        (
-            "cp.async.cg.shared.global [%smem32], [%gmem64], 16;",
-            "l,l,~{memory}",
-        ),
-        (
-            "cp.async.cg.shared.global [%smem32], [%gmem64], 16, $2;",
-            "l,l,r,~{memory}",
-        ),
-        ("cp.async.commit_group;", "~{memory}"),
-        ("cp.async.wait_group $0;", "n,~{memory}"),
-        ("cp.async.wait_all;", "~{memory}"),
-    ];
-    for (instruction, constraints) in expected {
-        assert_eq!(
-            lowered
-                .iter()
-                .filter(|(template, actual_constraints)| {
-                    template.contains(instruction) && actual_constraints == constraints
-                })
-                .count(),
-            1,
-            "missing exact `{instruction}`"
-        );
-    }
-    assert_eq!(lowered.len(), expected.len());
-    Ok(())
-}
-
-#[test]
-fn test_cp_async_ca_4_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let dst_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let src_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![dst_ty.into(), src_ty.into()]);
-
-    let dst = entry.deref(&ctx).get_argument(0);
-    let src = entry.deref(&ctx).get_argument(1);
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::CpAsyncCa4Op::get_concrete_op_info(),
-        vec![],
-        vec![dst, src],
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    assert_cp_async_inline_asm_lowering(&mut ctx, module_ptr, 4)
-}
-
-#[test]
-fn test_cp_async_ca_8_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let dst_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let src_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![dst_ty.into(), src_ty.into()]);
-
-    let dst = entry.deref(&ctx).get_argument(0);
-    let src = entry.deref(&ctx).get_argument(1);
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::CpAsyncCa8Op::get_concrete_op_info(),
-        vec![],
-        vec![dst, src],
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    assert_cp_async_inline_asm_lowering(&mut ctx, module_ptr, 8)
-}
-
-fn assert_cp_async_inline_asm_lowering(
-    ctx: &mut Context,
-    module_ptr: pliron::context::Ptr<Operation>,
-    copy_size: u32,
-) -> Result<(), anyhow::Error> {
-    use pliron::r#type::Typed;
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: mir_lower::IntrinsicBackend::LibNvvm,
-            ..Default::default()
-        },
-    )
-    .map_err(|e| anyhow::anyhow!("{e}"))?;
-
-    let expected_template = format!(
-        "{{ .reg .u64 %smem64; .reg .u32 %smem32; .reg .u64 %gmem64; \
-         cvta.to.shared.u64 %smem64, $0; cvt.u32.u64 %smem32, %smem64; \
-         cvta.to.global.u64 %gmem64, $1; \
-         cp.async.ca.shared.global [%smem32], [%gmem64], {copy_size}; }}"
-    );
-    let mut matches = 0;
-    let module_region = module_ptr.deref(ctx).get_region(0);
-    let module_block = module_region.deref(ctx).iter(ctx).next().unwrap();
-
-    for op in module_block.deref(ctx).iter(ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(ctx).to_string() != "kernel_func" {
-            continue;
-        }
-
-        let func_region = func_op.get_operation().deref(ctx).get_region(0);
-        for func_block in func_region.deref(ctx).iter(ctx) {
-            for body_op in func_block.deref(ctx).iter(ctx) {
-                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, ctx) else {
-                    continue;
-                };
-                let template = inline_asm
-                    .get_attr_inline_asm_template(ctx)
-                    .map(|s| String::from((*s).clone()));
-                if template.as_deref() != Some(expected_template.as_str()) {
-                    continue;
-                }
-
-                matches += 1;
-                assert_eq!(
-                    inline_asm
-                        .get_attr_inline_asm_constraints(ctx)
-                        .map(|s| String::from((*s).clone()))
-                        .as_deref(),
-                    Some("l,l,~{memory}")
-                );
-                assert_eq!(llvm::asm_kind(ctx, &inline_asm), llvm::AsmKind::SideEffect);
-                assert!(
-                    inline_asm
-                        .get_attr_inline_asm_convergent(ctx)
-                        .is_some_and(|value| !bool::from((*value).clone()))
-                );
-
-                let operands: Vec<_> = inline_asm.get_operation().deref(ctx).operands().collect();
-                assert_eq!(operands.len(), 2);
-                for operand in operands {
-                    let ty = operand.get_type(ctx);
-                    let ty = ty.deref(ctx);
-                    let ptr_ty = ty
-                        .downcast_ref::<llvm_export::types::PointerType>()
-                        .expect("cp.async operands must lower to LLVM pointers");
-                    assert_eq!(ptr_ty.address_space(), 0);
-                }
-            }
-        }
-    }
-
-    assert_eq!(matches, 1, "missing exact {copy_size}-byte cp.async asm");
-    Ok(())
-}
-
-// =============================================================================
-// cp.async zero-fill lowering tests
-// =============================================================================
-
-#[test]
-fn test_cp_async_ca_zfill_4_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let dst_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let src_ty = MirPtrType::get_generic(&mut ctx, i8_ty.into(), false);
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![dst_ty.into(), src_ty.into(), i32_ty.into()]);
-
-    let dst = entry.deref(&ctx).get_argument(0);
-    let src = entry.deref(&ctx).get_argument(1);
-    let src_size = entry.deref(&ctx).get_argument(2);
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::CpAsyncCaZfill4Op::get_concrete_op_info(),
-        vec![],
-        vec![dst, src, src_size],
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    assert_cp_async_zfill_inline_asm_lowering(&mut ctx, module_ptr, 4)
-}
-
-#[test]
-fn test_cp_async_ca_zfill_8_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let dst_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let src_ty = MirPtrType::get_generic(&mut ctx, i8_ty.into(), false);
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![dst_ty.into(), src_ty.into(), i32_ty.into()]);
-
-    let dst = entry.deref(&ctx).get_argument(0);
-    let src = entry.deref(&ctx).get_argument(1);
-    let src_size = entry.deref(&ctx).get_argument(2);
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::CpAsyncCaZfill8Op::get_concrete_op_info(),
-        vec![],
-        vec![dst, src, src_size],
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    assert_cp_async_zfill_inline_asm_lowering(&mut ctx, module_ptr, 8)
-}
-
-#[test]
-fn test_cp_async_ca_zfill_16_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let dst_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
-    let src_ty = MirPtrType::get_generic(&mut ctx, i8_ty.into(), false);
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![dst_ty.into(), src_ty.into(), i32_ty.into()]);
-
-    let dst = entry.deref(&ctx).get_argument(0);
-    let src = entry.deref(&ctx).get_argument(1);
-    let src_size = entry.deref(&ctx).get_argument(2);
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::CpAsyncCaZfill16Op::get_concrete_op_info(),
-        vec![],
-        vec![dst, src, src_size],
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    assert_cp_async_zfill_inline_asm_lowering(&mut ctx, module_ptr, 16)
-}
-
-fn assert_cp_async_zfill_inline_asm_lowering(
-    ctx: &mut Context,
-    module_ptr: pliron::context::Ptr<Operation>,
-    copy_size: u32,
-) -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::IntegerType;
-    use pliron::r#type::Typed;
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: mir_lower::IntrinsicBackend::LibNvvm,
-            ..Default::default()
-        },
-    )
-    .map_err(|e| anyhow::anyhow!("{e}"))?;
-
-    let expected_template = format!(
-        "{{ .reg .u64 %smem64; .reg .u32 %smem32; .reg .u64 %gmem64; \
-         cvta.to.shared.u64 %smem64, $0; cvt.u32.u64 %smem32, %smem64; \
-         cvta.to.global.u64 %gmem64, $1; \
-         cp.async.ca.shared.global [%smem32], [%gmem64], {copy_size}, $2; }}"
-    );
-    let mut matches = 0;
-    let module_region = module_ptr.deref(ctx).get_region(0);
-    let module_block = module_region.deref(ctx).iter(ctx).next().unwrap();
-
-    for op in module_block.deref(ctx).iter(ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(ctx).to_string() != "kernel_func" {
-            continue;
-        }
-
-        let func_region = func_op.get_operation().deref(ctx).get_region(0);
-        for func_block in func_region.deref(ctx).iter(ctx) {
-            for body_op in func_block.deref(ctx).iter(ctx) {
-                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, ctx) else {
-                    continue;
-                };
-                let template = inline_asm
-                    .get_attr_inline_asm_template(ctx)
-                    .map(|s| String::from((*s).clone()));
-                if template.as_deref() != Some(expected_template.as_str()) {
-                    continue;
-                }
-
-                matches += 1;
-                assert_eq!(
-                    inline_asm
-                        .get_attr_inline_asm_constraints(ctx)
-                        .map(|s| String::from((*s).clone()))
-                        .as_deref(),
-                    Some("l,l,r,~{memory}")
-                );
-                assert_eq!(llvm::asm_kind(ctx, &inline_asm), llvm::AsmKind::SideEffect);
-                assert!(
-                    inline_asm
-                        .get_attr_inline_asm_convergent(ctx)
-                        .is_some_and(|value| !bool::from((*value).clone()))
-                );
-
-                let operands: Vec<_> = inline_asm.get_operation().deref(ctx).operands().collect();
-                assert_eq!(operands.len(), 3);
-                for operand in &operands[..2] {
-                    let ty = operand.get_type(ctx);
-                    let ty = ty.deref(ctx);
-                    let ptr_ty = ty
-                        .downcast_ref::<llvm_export::types::PointerType>()
-                        .expect("cp.async pointer operands must lower to LLVM pointers");
-                    assert_eq!(ptr_ty.address_space(), 0);
-                }
-
-                let src_size_ty = operands[2].get_type(ctx);
-                let src_size_ty = src_size_ty.deref(ctx);
-                let src_size_ty = src_size_ty
-                    .downcast_ref::<IntegerType>()
-                    .expect("cp.async src_size must lower to an integer");
-                assert_eq!(src_size_ty.width(), 32);
-            }
-        }
-    }
-
-    assert_eq!(
-        matches, 1,
-        "missing exact {copy_size}-byte zero-fill cp.async asm"
-    );
-    Ok(())
-}
-
-// =============================================================================
-// Generated packed arithmetic lowering tests
-// =============================================================================
-
-#[test]
-fn test_generated_packed_arithmetic_lowers_to_exact_pure_inline_asm() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![i32_ty.into(), i32_ty.into(), i32_ty.into()]);
-
-    type OpInfo = (
-        fn(pliron::context::Ptr<Operation>) -> pliron::op::OpObj,
-        std::any::TypeId,
-    );
-    let cases: [(OpInfo, usize, &str, &str); 18] = [
-        (
-            nvvm::FmaBf16x2Op::get_concrete_op_info(),
-            3,
-            "fma.rn.bf16x2 $0, $1, $2, $3;",
-            "=r,r,r,r",
-        ),
-        (
-            nvvm::FmaReluBf16x2Op::get_concrete_op_info(),
-            3,
-            "fma.rn.relu.bf16x2 $0, $1, $2, $3;",
-            "=r,r,r,r",
-        ),
-        (
-            nvvm::AddBf16x2Op::get_concrete_op_info(),
-            2,
-            "add.rn.bf16x2 $0, $1, $2;",
-            "=r,r,r",
-        ),
-        (
-            nvvm::SubBf16x2Op::get_concrete_op_info(),
-            2,
-            "sub.rn.bf16x2 $0, $1, $2;",
-            "=r,r,r",
-        ),
-        (
-            nvvm::MulBf16x2Op::get_concrete_op_info(),
-            2,
-            "mul.rn.bf16x2 $0, $1, $2;",
-            "=r,r,r",
-        ),
-        (
-            nvvm::MinBf16x2Op::get_concrete_op_info(),
-            2,
-            "min.bf16x2 $0, $1, $2;",
-            "=r,r,r",
-        ),
-        (
-            nvvm::MaxBf16x2Op::get_concrete_op_info(),
-            2,
-            "max.bf16x2 $0, $1, $2;",
-            "=r,r,r",
-        ),
-        (
-            nvvm::NegBf16x2Op::get_concrete_op_info(),
-            1,
-            "neg.bf16x2 $0, $1;",
-            "=r,r",
-        ),
-        (
-            nvvm::AbsBf16x2Op::get_concrete_op_info(),
-            1,
-            "abs.bf16x2 $0, $1;",
-            "=r,r",
-        ),
-        (
-            nvvm::FmaF16x2Op::get_concrete_op_info(),
-            3,
-            "fma.rn.f16x2 $0, $1, $2, $3;",
-            "=r,r,r,r",
-        ),
-        (
-            nvvm::FmaReluF16x2Op::get_concrete_op_info(),
-            3,
-            "fma.rn.relu.f16x2 $0, $1, $2, $3;",
-            "=r,r,r,r",
-        ),
-        (
-            nvvm::AddF16x2Op::get_concrete_op_info(),
-            2,
-            "add.rn.f16x2 $0, $1, $2;",
-            "=r,r,r",
-        ),
-        (
-            nvvm::SubF16x2Op::get_concrete_op_info(),
-            2,
-            "sub.rn.f16x2 $0, $1, $2;",
-            "=r,r,r",
-        ),
-        (
-            nvvm::MulF16x2Op::get_concrete_op_info(),
-            2,
-            "mul.rn.f16x2 $0, $1, $2;",
-            "=r,r,r",
-        ),
-        (
-            nvvm::MinF16x2Op::get_concrete_op_info(),
-            2,
-            "min.f16x2 $0, $1, $2;",
-            "=r,r,r",
-        ),
-        (
-            nvvm::MaxF16x2Op::get_concrete_op_info(),
-            2,
-            "max.f16x2 $0, $1, $2;",
-            "=r,r,r",
-        ),
-        (
-            nvvm::NegF16x2Op::get_concrete_op_info(),
-            1,
-            "neg.f16x2 $0, $1;",
-            "=r,r",
-        ),
-        (
-            nvvm::AbsF16x2Op::get_concrete_op_info(),
-            1,
-            "abs.f16x2 $0, $1;",
-            "=r,r",
-        ),
-    ];
-
-    let operands = [
-        entry.deref(&ctx).get_argument(0),
-        entry.deref(&ctx).get_argument(1),
-        entry.deref(&ctx).get_argument(2),
-    ];
-    for &(op_info, operand_count, _, _) in &cases {
-        let op = Operation::new(
-            &mut ctx,
-            op_info,
-            vec![i32_ty.into()],
-            operands[..operand_count].to_vec(),
-            vec![],
-            0,
-        );
-        op.insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    let mut lowered = Vec::new();
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let inline_asm_op = inline_asm.get_operation();
-                let operand_count = inline_asm_op.deref(&ctx).operands().count();
-                let result_count = inline_asm_op.deref(&ctx).get_num_results();
-                lowered.push((
-                    inline_asm
-                        .get_attr_inline_asm_template(&ctx)
-                        .map(|s| String::from((*s).clone()))
-                        .expect("packed inline asm must have a template"),
-                    inline_asm
-                        .get_attr_inline_asm_constraints(&ctx)
-                        .map(|s| String::from((*s).clone()))
-                        .expect("packed inline asm must have constraints"),
-                    llvm::asm_kind_opt(&ctx, &inline_asm),
-                    inline_asm
-                        .get_attr_inline_asm_convergent(&ctx)
-                        .map(|b| bool::from((*b).clone())),
-                    operand_count,
-                    result_count,
-                ));
-            }
-        }
-    }
-
-    assert_eq!(
-        lowered.len(),
-        cases.len(),
-        "each packed operation must lower to exactly one inline-asm op"
-    );
-    for &(_, expected_operand_count, expected_template, expected_constraints) in &cases {
-        let matches: Vec<_> = lowered
-            .iter()
-            .filter(|(template, _, _, _, _, _)| template == expected_template)
-            .collect();
-        assert_eq!(
-            matches.len(),
-            1,
-            "expected one exact `{expected_template}` lowering"
-        );
-        let (_, constraints, kind, convergent, operand_count, result_count) = matches[0];
-        assert_eq!(constraints, expected_constraints, "{expected_template}");
-        assert_eq!(*kind, Some(llvm::AsmKind::Pure), "{expected_template}");
-        assert_eq!(*convergent, Some(false), "{expected_template}");
-        assert_eq!(
-            *operand_count, expected_operand_count,
-            "{expected_template} input arity"
-        );
-        assert_eq!(*result_count, 1, "{expected_template} result arity");
-    }
-
-    Ok(())
-}
-
-#[test]
-fn test_generated_integer_minmax_lowers_to_exact_pure_inline_asm() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into(), i32_ty.into()]);
-
-    type OpInfo = (
-        fn(pliron::context::Ptr<Operation>) -> pliron::op::OpObj,
-        std::any::TypeId,
-    );
-    let cases: [(OpInfo, &str); 8] = [
-        (
-            nvvm::MinReluS32Op::get_concrete_op_info(),
-            "min.relu.s32 $0, $1, $2;",
-        ),
-        (
-            nvvm::MaxReluS32Op::get_concrete_op_info(),
-            "max.relu.s32 $0, $1, $2;",
-        ),
-        (
-            nvvm::MinS16x2Op::get_concrete_op_info(),
-            "min.s16x2 $0, $1, $2;",
-        ),
-        (
-            nvvm::MaxS16x2Op::get_concrete_op_info(),
-            "max.s16x2 $0, $1, $2;",
-        ),
-        (
-            nvvm::MinU16x2Op::get_concrete_op_info(),
-            "min.u16x2 $0, $1, $2;",
-        ),
-        (
-            nvvm::MaxU16x2Op::get_concrete_op_info(),
-            "max.u16x2 $0, $1, $2;",
-        ),
-        (
-            nvvm::MinReluS16x2Op::get_concrete_op_info(),
-            "min.relu.s16x2 $0, $1, $2;",
-        ),
-        (
-            nvvm::MaxReluS16x2Op::get_concrete_op_info(),
-            "max.relu.s16x2 $0, $1, $2;",
-        ),
-    ];
-
-    let operands = [
-        entry.deref(&ctx).get_argument(0),
-        entry.deref(&ctx).get_argument(1),
-    ];
-    for &(op_info, _) in &cases {
-        let op = Operation::new(
-            &mut ctx,
-            op_info,
-            vec![i32_ty.into()],
-            operands.to_vec(),
-            vec![],
-            0,
-        );
-        op.insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    let mut lowered = Vec::new();
-    let module_op = module_ptr.deref(&ctx);
-    let region = module_op.get_region(0);
-    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let inline_asm_op = inline_asm.get_operation();
-                let operand_count = inline_asm_op.deref(&ctx).operands().count();
-                let result_count = inline_asm_op.deref(&ctx).get_num_results();
-                lowered.push((
-                    inline_asm
-                        .get_attr_inline_asm_template(&ctx)
-                        .map(|s| String::from((*s).clone()))
-                        .expect("integer min/max inline asm must have a template"),
-                    inline_asm
-                        .get_attr_inline_asm_constraints(&ctx)
-                        .map(|s| String::from((*s).clone()))
-                        .expect("integer min/max inline asm must have constraints"),
-                    llvm::asm_kind_opt(&ctx, &inline_asm),
-                    inline_asm
-                        .get_attr_inline_asm_convergent(&ctx)
-                        .map(|b| bool::from((*b).clone())),
-                    operand_count,
-                    result_count,
-                ));
-            }
-        }
-    }
-
-    assert_eq!(
-        lowered.len(),
-        cases.len(),
-        "each integer min/max operation must lower to exactly one inline-asm op"
-    );
-    for &(_, expected_template) in &cases {
-        let matches: Vec<_> = lowered
-            .iter()
-            .filter(|(template, _, _, _, _, _)| template == expected_template)
-            .collect();
-        assert_eq!(
-            matches.len(),
-            1,
-            "expected one exact `{expected_template}` lowering"
-        );
-        let (_, constraints, kind, convergent, operand_count, result_count) = matches[0];
-        assert_eq!(constraints, "=r,r,r", "{expected_template}");
-        assert_eq!(*kind, Some(llvm::AsmKind::Pure), "{expected_template}");
-        assert_eq!(*convergent, Some(false), "{expected_template}");
-        assert_eq!(*operand_count, 2, "{expected_template} input arity");
-        assert_eq!(*result_count, 1, "{expected_template} result arity");
-    }
-
-    Ok(())
-}
-
-#[test]
-fn test_generated_packed_conversions_lower_to_exact_pure_inline_asm() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty.into(), f32_ty.into()]);
-    let low = entry.deref(&ctx).get_argument(0);
-    let high = entry.deref(&ctx).get_argument(1);
-
-    type OpInfo = (
-        fn(pliron::context::Ptr<Operation>) -> pliron::op::OpObj,
-        std::any::TypeId,
-    );
-    let cases: [(OpInfo, &str); 6] = [
-        (
-            nvvm::CvtF32x2Bf16x2Op::get_concrete_op_info(),
-            "cvt.rn.bf16x2.f32 $0, $2, $1;",
-        ),
-        (
-            nvvm::CvtF16x2F32Op::get_concrete_op_info(),
-            "cvt.rn.f16x2.f32 $0, $2, $1;",
-        ),
-        (
-            nvvm::CvtRzF16x2F32Op::get_concrete_op_info(),
-            "cvt.rz.f16x2.f32 $0, $2, $1;",
-        ),
-        (
-            nvvm::CvtRnReluF16x2F32Op::get_concrete_op_info(),
-            "cvt.rn.relu.f16x2.f32 $0, $2, $1;",
-        ),
-        (
-            nvvm::CvtRnReluBf16x2F32Op::get_concrete_op_info(),
-            "cvt.rn.relu.bf16x2.f32 $0, $2, $1;",
-        ),
-        (
-            nvvm::CvtRzBf16x2F32Op::get_concrete_op_info(),
-            "cvt.rz.bf16x2.f32 $0, $2, $1;",
-        ),
-    ];
-    for &(op_info, _) in &cases {
-        let op = Operation::new(
-            &mut ctx,
-            op_info,
-            vec![i32_ty.into()],
-            vec![low, high],
-            vec![],
-            0,
-        );
-        op.insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
-
-    let mut lowered = Vec::new();
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(func) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if func.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let region = func.get_operation().deref(&ctx).get_region(0);
-        for block in region.deref(&ctx).iter(&ctx) {
-            for body_op in block.deref(&ctx).iter(&ctx) {
-                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .expect("packed conversion must have an asm template");
-                if !template.starts_with("cvt.") {
-                    continue;
-                }
-                lowered.push((
-                    template,
-                    asm.get_attr_inline_asm_constraints(&ctx)
-                        .map(|value| String::from((*value).clone())),
-                    asm.get_attr_inline_asm_convergent(&ctx)
-                        .map(|value| bool::from((*value).clone())),
-                    llvm::asm_kind_opt(&ctx, &asm),
-                    asm.get_operation().deref(&ctx).operands().count(),
-                    asm.get_operation().deref(&ctx).get_num_results(),
-                ));
-            }
-        }
-    }
-
-    assert_eq!(
-        lowered.len(),
-        cases.len(),
-        "each packed conversion must lower to one inline-asm op"
-    );
-    for &(_, expected_template) in &cases {
-        let matches: Vec<_> = lowered
-            .iter()
-            .filter(|(template, _, _, _, _, _)| template == expected_template)
-            .collect();
-        assert_eq!(
-            matches.len(),
-            1,
-            "expected one exact `{expected_template}` lowering"
-        );
-        let (_, constraints, convergent, kind, operands, results) = matches[0];
-        assert_eq!(
-            constraints.as_deref(),
-            Some("=r,f,f"),
-            "{expected_template}"
-        );
-        assert_eq!(*convergent, Some(false), "{expected_template}");
-        assert_eq!(*kind, Some(llvm::AsmKind::Pure), "{expected_template}");
-        assert_eq!(*operands, 2, "{expected_template} input arity");
-        assert_eq!(*results, 1, "{expected_template} result arity");
-    }
-
-    Ok(())
-}
-
-const FP8_CONVERSION_INTRINSICS: [&str; 4] = [
-    "llvm_nvvm_ff_to_e4m3x2_rn",
-    "llvm_nvvm_ff_to_e4m3x2_rn_relu",
-    "llvm_nvvm_ff_to_e5m2x2_rn",
-    "llvm_nvvm_ff_to_e5m2x2_rn_relu",
-];
-
-const FP8_CONVERSION_PTX: [&str; 4] = [
-    "cvt.rn.satfinite.e4m3x2.f32 $0, $2, $1;",
-    "cvt.rn.satfinite.relu.e4m3x2.f32 $0, $2, $1;",
-    "cvt.rn.satfinite.e5m2x2.f32 $0, $2, $1;",
-    "cvt.rn.satfinite.relu.e5m2x2.f32 $0, $2, $1;",
-];
-
-fn lower_all_fp8_conversions(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use pliron::builtin::types::FP32Type;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty.into(), f32_ty.into()]);
-    let low = entry.deref(&ctx).get_argument(0);
-    let high = entry.deref(&ctx).get_argument(1);
-
-    nvvm::CvtRnSatfiniteE4m3x2F32Op::build(&mut ctx, low, high).insert_at_back(entry, &ctx);
-    nvvm::CvtRnSatfiniteReluE4m3x2F32Op::build(&mut ctx, low, high).insert_at_back(entry, &ctx);
-    nvvm::CvtRnSatfiniteE5m2x2F32Op::build(&mut ctx, low, high).insert_at_back(entry, &ctx);
-    nvvm::CvtRnSatfiniteReluE5m2x2F32Op::build(&mut ctx, low, high).insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn test_fp8_conversions_llvm_nvptx_use_exact_typed_calls() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::IntegerType;
-    use pliron::r#type::Typed;
-
-    let (ctx, module_ptr) = lower_all_fp8_conversions(mir_lower::IntrinsicBackend::LlvmNvptx)?;
-    let mut calls = Vec::new();
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        assert!(
-            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-            "LLVM-NVPTX FP8 conversions must use typed intrinsics"
-        );
-        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-            continue;
-        };
-        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-            continue;
-        };
-        let callee = callee.to_string();
-        if !FP8_CONVERSION_INTRINSICS.contains(&callee.as_str()) {
-            continue;
-        }
-        let call_op = call.get_operation();
-        assert_eq!(call_op.deref(&ctx).get_num_operands(), 2);
-        assert_eq!(call_op.deref(&ctx).get_num_results(), 1);
-        let block = call_op.deref(&ctx).get_parent_block().unwrap();
-        assert_eq!(
-            call_op.deref(&ctx).get_operand(0),
-            block.deref(&ctx).get_argument(1)
-        );
-        assert_eq!(
-            call_op.deref(&ctx).get_operand(1),
-            block.deref(&ctx).get_argument(0)
-        );
-        let result_ty = call_op.deref(&ctx).get_result(0).get_type(&ctx);
-        assert_eq!(
-            result_ty
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .expect("FP8 conversion result is an integer")
-                .width(),
-            16
-        );
-        calls.push(callee);
-    }
-    calls.sort();
-    let mut expected = FP8_CONVERSION_INTRINSICS.map(str::to_owned);
-    expected.sort();
-    assert_eq!(calls, expected);
-    Ok(())
-}
-
-#[test]
-fn test_fp8_conversions_libnvvm_use_exact_pure_inline_ptx() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::IntegerType;
-    use pliron::r#type::Typed;
-
-    let (ctx, module_ptr) = lower_all_fp8_conversions(mir_lower::IntrinsicBackend::LibNvvm)?;
-    let mut templates = Vec::new();
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-        {
-            assert!(
-                !FP8_CONVERSION_INTRINSICS.contains(&callee.as_ref()),
-                "libNVVM FP8 conversions must not use typed intrinsics"
-            );
-        }
-        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            continue;
-        };
-        let template = inline_asm
-            .get_attr_inline_asm_template(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .unwrap_or_default();
-        if !FP8_CONVERSION_PTX.contains(&template.as_str()) {
-            continue;
-        }
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_constraints(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some("=h,f,f")
-        );
-        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_convergent(&ctx)
-                .map(|value| bool::from((*value).clone())),
-            Some(false)
-        );
-        let asm_op = inline_asm.get_operation();
-        assert_eq!(asm_op.deref(&ctx).get_num_operands(), 2);
-        assert_eq!(asm_op.deref(&ctx).get_num_results(), 1);
-        let result_ty = asm_op.deref(&ctx).get_result(0).get_type(&ctx);
-        assert_eq!(
-            result_ty
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .expect("FP8 conversion result is an integer")
-                .width(),
-            16
-        );
-        templates.push(template);
-    }
-    templates.sort();
-    let mut expected = FP8_CONVERSION_PTX.map(str::to_owned);
-    expected.sort();
-    assert_eq!(templates, expected);
-    Ok(())
-}
-
-const SCALAR_CONVERSION_INTRINSICS: [&str; 10] = [
-    "llvm_nvvm_f2tf32_rna",
-    "llvm_nvvm_f2tf32_rna_satfinite",
-    "llvm_nvvm_f2tf32_rn",
-    "llvm_nvvm_f2tf32_rn_relu",
-    "llvm_nvvm_f2tf32_rn_satfinite",
-    "llvm_nvvm_f2tf32_rn_relu_satfinite",
-    "llvm_nvvm_f2tf32_rz",
-    "llvm_nvvm_f2tf32_rz_relu",
-    "llvm_nvvm_f2tf32_rz_satfinite",
-    "llvm_nvvm_f2tf32_rz_relu_satfinite",
-];
-
-const SCALAR_CONVERSION_PTX: [&str; 10] = [
-    "cvt.rna.tf32.f32 $0, $1;",
-    "cvt.rna.satfinite.tf32.f32 $0, $1;",
-    "cvt.rn.tf32.f32 $0, $1;",
-    "cvt.rn.relu.tf32.f32 $0, $1;",
-    "cvt.rn.satfinite.tf32.f32 $0, $1;",
-    "cvt.rn.relu.satfinite.tf32.f32 $0, $1;",
-    "cvt.rz.tf32.f32 $0, $1;",
-    "cvt.rz.relu.tf32.f32 $0, $1;",
-    "cvt.rz.satfinite.tf32.f32 $0, $1;",
-    "cvt.rz.relu.satfinite.tf32.f32 $0, $1;",
-];
-
-fn lower_all_scalar_conversions(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use pliron::builtin::types::FP32Type;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty.into()]);
-    let value = entry.deref(&ctx).get_argument(0);
-
-    let variants = [
-        (
-            nvvm::ScalarConversionRoundingAttr::NearestAway,
-            nvvm::ScalarConversionSaturationAttr::None,
-        ),
-        (
-            nvvm::ScalarConversionRoundingAttr::NearestAway,
-            nvvm::ScalarConversionSaturationAttr::Satfinite,
-        ),
-        (
-            nvvm::ScalarConversionRoundingAttr::NearestEven,
-            nvvm::ScalarConversionSaturationAttr::None,
-        ),
-        (
-            nvvm::ScalarConversionRoundingAttr::NearestEven,
-            nvvm::ScalarConversionSaturationAttr::Relu,
-        ),
-        (
-            nvvm::ScalarConversionRoundingAttr::NearestEven,
-            nvvm::ScalarConversionSaturationAttr::Satfinite,
-        ),
-        (
-            nvvm::ScalarConversionRoundingAttr::NearestEven,
-            nvvm::ScalarConversionSaturationAttr::ReluSatfinite,
-        ),
-        (
-            nvvm::ScalarConversionRoundingAttr::TowardZero,
-            nvvm::ScalarConversionSaturationAttr::None,
-        ),
-        (
-            nvvm::ScalarConversionRoundingAttr::TowardZero,
-            nvvm::ScalarConversionSaturationAttr::Relu,
-        ),
-        (
-            nvvm::ScalarConversionRoundingAttr::TowardZero,
-            nvvm::ScalarConversionSaturationAttr::Satfinite,
-        ),
-        (
-            nvvm::ScalarConversionRoundingAttr::TowardZero,
-            nvvm::ScalarConversionSaturationAttr::ReluSatfinite,
-        ),
-    ];
-    for (rounding, saturation) in variants {
-        nvvm::ScalarConversionOp::build(&mut ctx, value, rounding, saturation)
-            .insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn test_scalar_conversions_llvm_nvptx_use_exact_typed_calls() -> Result<(), anyhow::Error> {
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::type_interfaces::FunctionTypeInterface;
-    use pliron::builtin::types::{FP32Type, IntegerType};
-
-    let (ctx, module_ptr) = lower_all_scalar_conversions(mir_lower::IntrinsicBackend::LlvmNvptx)?;
-    let mut calls = Vec::new();
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        assert!(
-            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-            "LLVM-NVPTX scalar conversions must use typed intrinsics"
-        );
-        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-            continue;
-        };
-        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-            continue;
-        };
-        let callee = callee.to_string();
-        if !SCALAR_CONVERSION_INTRINSICS.contains(&callee.as_str()) {
-            continue;
-        }
-
-        let call_op = call.get_operation();
-        assert_eq!(call_op.deref(&ctx).get_num_operands(), 1, "{callee}");
-        assert_eq!(call_op.deref(&ctx).get_num_results(), 1, "{callee}");
-        let block = call_op.deref(&ctx).get_parent_block().unwrap();
-        assert_eq!(
-            call_op.deref(&ctx).get_operand(0),
-            block.deref(&ctx).get_argument(0),
-            "{callee} source operand"
-        );
-
-        let function_ty = call.callee_type(&ctx);
-        let function_ty = function_ty.deref(&ctx);
-        let function_ty = function_ty
-            .downcast_ref::<llvm_types::FuncType>()
-            .expect("scalar conversion callee has an LLVM function type");
-        assert_eq!(function_ty.arg_types().len(), 1, "{callee}");
-        assert!(
-            function_ty.arg_types()[0]
-                .deref(&ctx)
-                .downcast_ref::<FP32Type>()
-                .is_some(),
-            "{callee} source type"
-        );
-        assert_eq!(
-            function_ty
-                .result_type()
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .expect("scalar conversion result is an integer")
-                .width(),
-            32,
-            "{callee} result type"
-        );
-        calls.push(callee);
-    }
-    calls.sort();
-    let mut expected = SCALAR_CONVERSION_INTRINSICS.map(str::to_owned);
-    expected.sort();
-    assert_eq!(calls, expected);
-
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    let mut declarations: Vec<_> = module_block
-        .deref(&ctx)
-        .iter(&ctx)
-        .filter_map(|op| Operation::get_op::<llvm::FuncOp>(op, &ctx))
-        .map(|func| func.get_symbol_name(&ctx).to_string())
-        .filter(|name| SCALAR_CONVERSION_INTRINSICS.contains(&name.as_str()))
-        .collect();
-    declarations.sort();
-    assert_eq!(declarations, expected);
-    Ok(())
-}
-
-#[test]
-fn test_scalar_conversions_libnvvm_use_exact_pure_inline_ptx() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::IntegerType;
-    use pliron::r#type::Typed;
-
-    let (ctx, module_ptr) = lower_all_scalar_conversions(mir_lower::IntrinsicBackend::LibNvvm)?;
-    let mut templates = Vec::new();
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-        {
-            assert!(
-                !SCALAR_CONVERSION_INTRINSICS.contains(&callee.as_ref()),
-                "libNVVM scalar conversions must not use typed intrinsics"
-            );
-        }
-        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            continue;
-        };
-        let template = inline_asm
-            .get_attr_inline_asm_template(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .unwrap_or_default();
-        assert!(
-            SCALAR_CONVERSION_PTX.contains(&template.as_str()),
-            "unexpected scalar conversion template `{template}`"
-        );
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_constraints(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .as_deref(),
-            Some("=r,f"),
-            "{template}"
-        );
-        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_convergent(&ctx)
-                .map(|value| bool::from((*value).clone())),
-            Some(false),
-            "{template}"
-        );
-
-        let asm_op = inline_asm.get_operation();
-        assert_eq!(asm_op.deref(&ctx).get_num_operands(), 1, "{template}");
-        assert_eq!(asm_op.deref(&ctx).get_num_results(), 1, "{template}");
-        let block = asm_op.deref(&ctx).get_parent_block().unwrap();
-        assert_eq!(
-            asm_op.deref(&ctx).get_operand(0),
-            block.deref(&ctx).get_argument(0),
-            "{template} source operand"
-        );
-        assert_eq!(
-            asm_op
-                .deref(&ctx)
-                .get_result(0)
-                .get_type(&ctx)
-                .deref(&ctx)
-                .downcast_ref::<IntegerType>()
-                .expect("scalar conversion result is an integer")
-                .width(),
-            32,
-            "{template} result type"
-        );
-        templates.push(template);
-    }
-    templates.sort();
-    let mut expected = SCALAR_CONVERSION_PTX.map(str::to_owned);
-    expected.sort();
-    assert_eq!(templates, expected);
-    Ok(())
-}
-
-#[test]
-fn test_scalar_conversion_invalid_variant_fails_closed() {
-    use pliron::builtin::types::FP32Type;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty.into()]);
-    let value = entry.deref(&ctx).get_argument(0);
-    nvvm::ScalarConversionOp::build(
-        &mut ctx,
-        value,
-        nvvm::ScalarConversionRoundingAttr::NearestAway,
-        nvvm::ScalarConversionSaturationAttr::Relu,
-    )
-    .insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    let result = mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: mir_lower::IntrinsicBackend::LlvmNvptx,
-            ..Default::default()
-        },
-    );
-    let error = result.expect_err("unadmitted scalar conversion must not lower");
-    assert!(
-        error.to_string().contains("scalar_conversion"),
-        "unexpected error: {error}"
-    );
-}
-
-fn lower_representative_scalar_arithmetic(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use pliron::builtin::types::FP32Type;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![f32_ty.into(), f32_ty.into(), f32_ty.into()]);
-    let args: Vec<_> = (0..3)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect();
-
-    for (operation, saturation, operands) in [
-        (
-            nvvm::ScalarArithmeticOperationAttr::Add,
-            nvvm::ScalarArithmeticSaturationAttr::None,
-            vec![args[0], args[1]],
-        ),
-        (
-            nvvm::ScalarArithmeticOperationAttr::Add,
-            nvvm::ScalarArithmeticSaturationAttr::Sat,
-            vec![args[0], args[1]],
-        ),
-        (
-            nvvm::ScalarArithmeticOperationAttr::Fma,
-            nvvm::ScalarArithmeticSaturationAttr::None,
-            args.clone(),
-        ),
-        (
-            nvvm::ScalarArithmeticOperationAttr::Fma,
-            nvvm::ScalarArithmeticSaturationAttr::Sat,
-            args,
-        ),
-    ] {
-        nvvm::ScalarArithmeticOp::build(
-            &mut ctx,
-            operands,
-            nvvm::ScalarArithmeticFormatAttr::F32,
-            operation,
-            nvvm::ScalarArithmeticRoundingAttr::Rn,
-            nvvm::ScalarArithmeticSubnormalAttr::Preserve,
-            saturation,
-        )
-        .insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-    Ok((ctx, module_ptr))
-}
-
-fn is_representative_scalar_arithmetic_intrinsic(name: &str) -> bool {
-    name.starts_with("llvm_nvvm_add_rn") || name.starts_with("llvm_nvvm_fma_rn")
-}
-
-#[test]
-fn test_scalar_arithmetic_llvm_uses_inline_ptx_only_for_saturation() -> Result<(), anyhow::Error> {
-    let (ctx, module_ptr) =
-        lower_representative_scalar_arithmetic(mir_lower::IntrinsicBackend::LlvmNvptx)?;
-    let mut calls = Vec::new();
-    let mut inline_ptx = Vec::new();
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-            && is_representative_scalar_arithmetic_intrinsic(callee.as_ref())
-        {
-            calls.push(callee.to_string());
-        }
-        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            continue;
-        };
-        let template = inline_asm
-            .get_attr_inline_asm_template(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .unwrap_or_default();
-        let constraints = inline_asm
-            .get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .unwrap_or_default();
-        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
-        assert_eq!(
-            inline_asm
-                .get_attr_inline_asm_convergent(&ctx)
-                .map(|value| bool::from((*value).clone())),
-            Some(false)
-        );
-        inline_ptx.push((template, constraints));
-    }
-
-    calls.sort();
-    assert_eq!(calls, ["llvm_nvvm_add_rn_f", "llvm_nvvm_fma_rn_f"]);
-    inline_ptx.sort();
-    assert_eq!(
-        inline_ptx,
-        [
-            ("add.rn.sat.f32 $0, $1, $2;".into(), "=f,f,f".into()),
-            ("fma.rn.sat.f32 $0, $1, $2, $3;".into(), "=f,f,f,f".into(),),
-        ]
-    );
-
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    let mut declarations: Vec<_> = module_block
-        .deref(&ctx)
-        .iter(&ctx)
-        .filter_map(|op| Operation::get_op::<llvm::FuncOp>(op, &ctx))
-        .map(|func| func.get_symbol_name(&ctx).to_string())
-        .filter(|name| is_representative_scalar_arithmetic_intrinsic(name))
-        .collect();
-    declarations.sort();
-    assert_eq!(declarations, calls);
-    Ok(())
-}
-
-#[test]
-fn test_scalar_arithmetic_libnvvm_uses_exact_inline_ptx() -> Result<(), anyhow::Error> {
-    let (ctx, module_ptr) =
-        lower_representative_scalar_arithmetic(mir_lower::IntrinsicBackend::LibNvvm)?;
-    let mut calls = Vec::new();
-    let mut inline_ptx = Vec::new();
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-            && is_representative_scalar_arithmetic_intrinsic(callee.as_ref())
-        {
-            calls.push(callee.to_string());
-        }
-        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            continue;
-        };
-        let template = inline_asm
-            .get_attr_inline_asm_template(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .unwrap_or_default();
-        let constraints = inline_asm
-            .get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .unwrap_or_default();
-        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
-        inline_ptx.push((template, constraints));
-    }
-
-    assert!(calls.is_empty());
-    inline_ptx.sort();
-    assert_eq!(
-        inline_ptx,
-        [
-            ("add.rn.f32 $0, $1, $2;".into(), "=f,f,f".into()),
-            ("add.rn.sat.f32 $0, $1, $2;".into(), "=f,f,f".into()),
-            ("fma.rn.f32 $0, $1, $2, $3;".into(), "=f,f,f,f".into(),),
-            ("fma.rn.sat.f32 $0, $1, $2, $3;".into(), "=f,f,f,f".into(),),
-        ]
-    );
-    Ok(())
-}
-
-const STMATRIX_TYPED_INTRINSICS: [&str; 4] = [
-    "llvm_nvvm_stmatrix_sync_aligned_m8n8_x2_b16_p3",
-    "llvm_nvvm_stmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
-    "llvm_nvvm_stmatrix_sync_aligned_m8n8_x4_b16_p3",
-    "llvm_nvvm_stmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
-];
-
-const STMATRIX_PTX: [(&str, &str); 4] = [
-    (
-        "{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x2.shared.b16 [%ptr32], {$1, $2}; }",
-        "l,r,r,~{memory}",
-    ),
-    (
-        "{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x2.trans.shared.b16 [%ptr32], {$1, $2}; }",
-        "l,r,r,~{memory}",
-    ),
-    (
-        "{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x4.shared.b16 [%ptr32], {$1, $2, $3, $4}; }",
-        "l,r,r,r,r,~{memory}",
-    ),
-    (
-        "{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x4.trans.shared.b16 [%ptr32], {$1, $2, $3, $4}; }",
-        "l,r,r,r,r,~{memory}",
-    ),
-];
-
-fn lower_all_stmatrix_forms(
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, i8_ty.into(), true);
-    let (module_ptr, entry) = build_test_kernel(
-        &mut ctx,
-        vec![
-            ptr_ty.into(),
-            i32_ty.into(),
-            i32_ty.into(),
-            i32_ty.into(),
-            i32_ty.into(),
-        ],
-    );
-    let args: Vec<_> = (0..5)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect();
-
-    for (op_info, operands) in [
-        (
-            nvvm::StmatrixM8n8X2Op::get_concrete_op_info(),
-            args[..3].to_vec(),
-        ),
-        (
-            nvvm::StmatrixM8n8X2TransOp::get_concrete_op_info(),
-            args[..3].to_vec(),
-        ),
-        (nvvm::StmatrixM8n8X4Op::get_concrete_op_info(), args.clone()),
-        (nvvm::StmatrixM8n8X4TransOp::get_concrete_op_info(), args),
-    ] {
-        Operation::new(&mut ctx, op_info, vec![], operands, vec![], 0).insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    Ok((ctx, module_ptr))
-}
-
-#[test]
-fn test_stmatrix_llvm_nvptx_uses_exact_typed_p3_intrinsics() -> Result<(), anyhow::Error> {
-    use llvm_export::types as llvm_types;
-    use pliron::r#type::Typed;
-
-    let (ctx, module_ptr) = lower_all_stmatrix_forms(mir_lower::IntrinsicBackend::LlvmNvptx)?;
-    let mut callees = Vec::new();
-
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        assert!(
-            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-            "LLVM-NVPTX stmatrix lowering must not emit inline PTX"
-        );
-        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-            continue;
-        };
-        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-            continue;
-        };
-        let callee = callee.to_string();
-        if !STMATRIX_TYPED_INTRINSICS.contains(&callee.as_str()) {
-            continue;
-        }
-
-        let call_op = call.get_operation().deref(&ctx);
-        assert!(matches!(call_op.get_num_operands(), 3 | 5));
-        assert_eq!(call_op.get_num_results(), 1);
-        let pointer_ty = call_op.get_operand(0).get_type(&ctx);
-        let pointer_ty = pointer_ty.deref(&ctx);
-        let pointer_ty = pointer_ty
-            .downcast_ref::<llvm_types::PointerType>()
-            .expect("stmatrix first argument is a pointer");
-        assert_eq!(pointer_ty.address_space(), 3);
-        callees.push(callee);
-    }
-
-    callees.sort();
-    let mut expected = STMATRIX_TYPED_INTRINSICS.map(str::to_owned);
-    expected.sort();
-    assert_eq!(callees, expected);
-
-    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-        .expect("typed stmatrix module exports to LLVM IR");
-    for intrinsic in STMATRIX_TYPED_INTRINSICS {
-        let dotted = intrinsic.replace('_', ".");
-        assert!(
-            ir.contains(&format!("@{dotted}(ptr addrspace(3)")),
-            "missing exact typed stmatrix declaration:\n{ir}"
-        );
-    }
-    assert!(!ir.contains("asm sideeffect"), "{ir}");
-    Ok(())
-}
-
-#[test]
-fn test_stmatrix_libnvvm_uses_exact_convergent_memory_asm() -> Result<(), anyhow::Error> {
-    let (ctx, module_ptr) = lower_all_stmatrix_forms(mir_lower::IntrinsicBackend::LibNvvm)?;
-    let mut lowered = Vec::new();
-
-    for op in lowered_kernel_body(&ctx, module_ptr) {
-        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-        {
-            assert!(
-                !STMATRIX_TYPED_INTRINSICS.contains(&callee.as_ref()),
-                "libNVVM stmatrix lowering must not emit typed intrinsic calls"
-            );
-        }
-        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-            continue;
-        };
-        lowered.push((
-            inline_asm
-                .get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .unwrap_or_default(),
-            inline_asm
-                .get_attr_inline_asm_constraints(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .unwrap_or_default(),
-            llvm::asm_kind(&ctx, &inline_asm),
-            op.deref(&ctx).get_num_operands(),
-            op.deref(&ctx).get_num_results(),
-        ));
-    }
-
-    assert_eq!(lowered.len(), STMATRIX_PTX.len());
-    for (template, constraints) in STMATRIX_PTX {
-        let matches: Vec<_> = lowered
-            .iter()
-            .filter(|(actual, _, _, _, _)| actual == template)
-            .collect();
-        assert_eq!(matches.len(), 1, "missing exact PTX {template}");
-        let (_, actual_constraints, kind, operands, results) = matches[0];
-        assert_eq!(actual_constraints, constraints);
-        assert_eq!(*kind, llvm::AsmKind::Convergent);
-        assert!(matches!(*operands, 3 | 5));
-        assert_eq!(*results, 1);
-    }
-
-    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-        .expect("inline stmatrix module exports to LLVM IR");
-    assert_eq!(ir.matches("asm sideeffect").count(), 4, "{ir}");
-    assert_eq!(ir.matches("~{memory}").count(), 4, "{ir}");
-    assert!(ir.contains("attributes #0 = { convergent }"), "{ir}");
-    assert!(!ir.contains("@llvm.nvvm.stmatrix"), "{ir}");
-    Ok(())
-}
-
-// =============================================================================
-// Warp-level matrix (`movmatrix`) lowering test
-// =============================================================================
-
-#[test]
-fn test_movmatrix_trans_b16_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
-
-    let a_val = entry.deref(&ctx).get_argument(0);
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::MovmatrixTransB16Op::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![a_val],
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut found = 0;
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for module_op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
-            continue;
-        };
-        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let body = function.get_operation().deref(&ctx).get_region(0);
-        for block in body.deref(&ctx).iter(&ctx) {
-            for body_op in block.deref(&ctx).iter(&ctx) {
-                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                found += 1;
-                let template = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                let constraints = asm
-                    .get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                assert_eq!(
-                    template.as_deref(),
-                    Some("movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;")
-                );
-                assert_eq!(constraints.as_deref(), Some("=r,r"));
-                assert_eq!(
-                    llvm::asm_kind_opt(&ctx, &asm),
-                    Some(llvm::AsmKind::Convergent)
-                );
-                assert!(
-                    asm.get_attr_inline_asm_convergent(&ctx)
-                        .is_some_and(|value| bool::from((*value).clone()))
-                );
-                assert!(
-                    !constraints.as_deref().unwrap().contains("memory"),
-                    "register-only movmatrix must not claim a memory clobber"
-                );
-            }
-        }
-    }
-
-    assert_eq!(found, 1, "expected one movmatrix inline-asm operation");
-    Ok(())
-}
-
-// =============================================================================
-// ldmatrix lowering tests
-// =============================================================================
-
-const LDMATRIX_TYPED_INTRINSICS: [&str; 6] = [
-    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_b16_p3",
-    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_trans_b16_p3",
-    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_b16_p3",
-    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
-    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_b16_p3",
-    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
-];
-
-const LDMATRIX_PTX_TEMPLATES: [&str; 6] = [
-    "ldmatrix.sync.aligned.m8n8.x1.shared.b16 {$0}, [$1];",
-    "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16 {$0}, [$1];",
-    "ldmatrix.sync.aligned.m8n8.x2.shared.b16 {$0, $1}, [$2];",
-    "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16 {$0, $1}, [$2];",
-    "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {$0, $1, $2, $3}, [$4];",
-    "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {$0, $1, $2, $3}, [$4];",
-];
-
-const LDMATRIX_PTX_CONSTRAINTS: [&str; 6] = [
-    "=r,r,~{memory}",
-    "=r,r,~{memory}",
-    "=r,=r,r,~{memory}",
-    "=r,=r,r,~{memory}",
-    "=r,=r,=r,=r,r,~{memory}",
-    "=r,=r,=r,=r,r,~{memory}",
-];
-
-const BLACKWELL_LDMATRIX_CASES: [(&str, &str, &str, usize); 12] = [
-    (
-        "llvm_nvvm_ldmatrix_sync_aligned_m16n16_x1_trans_b8_p3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8.p3",
-        "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {$0, $1}, [$2];",
-        2,
-    ),
-    (
-        "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db4x16_up64_dp3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8x16.b4x16_p64.p3",
-        "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b4x16_p64 {$0, $1}, [$2];",
-        2,
-    ),
-    (
-        "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db6x16_up32_dp3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8x16.b6x16_p32.p3",
-        "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b6x16_p32 {$0, $1}, [$2];",
-        2,
-    ),
-    (
-        "llvm_nvvm_ldmatrix_sync_aligned_m16n16_x2_trans_b8_p3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x2.trans.b8.p3",
-        "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8 {$0, $1, $2, $3}, [$4];",
-        4,
-    ),
-    (
-        "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx2_dtrans_db8x16_db4x16_up64_dp3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x2.trans.b8x16.b4x16_p64.p3",
-        "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b4x16_p64 {$0, $1, $2, $3}, [$4];",
-        4,
-    ),
-    (
-        "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx2_dtrans_db8x16_db6x16_up32_dp3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x2.trans.b8x16.b6x16_p32.p3",
-        "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b6x16_p32 {$0, $1, $2, $3}, [$4];",
-        4,
-    ),
-    (
-        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx1_db8x16_db4x16_up64_dp3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x1.b8x16.b4x16_p64.p3",
-        "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b4x16_p64 {$0}, [$1];",
-        1,
-    ),
-    (
-        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx1_db8x16_db6x16_up32_dp3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x1.b8x16.b6x16_p32.p3",
-        "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b6x16_p32 {$0}, [$1];",
-        1,
-    ),
-    (
-        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx2_db8x16_db4x16_up64_dp3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x2.b8x16.b4x16_p64.p3",
-        "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b4x16_p64 {$0, $1}, [$2];",
-        2,
-    ),
-    (
-        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx2_db8x16_db6x16_up32_dp3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x2.b8x16.b6x16_p32.p3",
-        "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b6x16_p32 {$0, $1}, [$2];",
-        2,
-    ),
-    (
-        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx4_db8x16_db4x16_up64_dp3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x4.b8x16.b4x16_p64.p3",
-        "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b4x16_p64 {$0, $1, $2, $3}, [$4];",
-        4,
-    ),
-    (
-        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx4_db8x16_db6x16_up32_dp3",
-        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x4.b8x16.b6x16_p32.p3",
-        "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b6x16_p32 {$0, $1, $2, $3}, [$4];",
-        4,
-    ),
-];
-
-fn ldmatrix_constraints(register_count: usize) -> &'static str {
-    match register_count {
-        1 => "=r,r,~{memory}",
-        2 => "=r,=r,r,~{memory}",
-        4 => "=r,=r,=r,=r,r,~{memory}",
-        _ => unreachable!("closed ldmatrix register count"),
-    }
-}
-
-fn lower_all_ldmatrix_forms(
-    address_space: u32,
-    backend: mir_lower::IntrinsicBackend,
-    compatibility: bool,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let ptr_ty = MirPtrType::get(&mut ctx, u32_ty.into(), true, address_space);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into()]);
-    let pointer = entry.deref(&ctx).get_argument(0);
-    if compatibility {
-        let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-        for (op_info, result_count) in [
-            (nvvm::LdmatrixX1Op::get_concrete_op_info(), 1),
-            (nvvm::LdmatrixX1TransOp::get_concrete_op_info(), 1),
-            (nvvm::LdmatrixX2Op::get_concrete_op_info(), 2),
-            (nvvm::LdmatrixX2TransOp::get_concrete_op_info(), 2),
-            (nvvm::LdmatrixX4Op::get_concrete_op_info(), 4),
-            (nvvm::LdmatrixX4TransOp::get_concrete_op_info(), 4),
-        ] {
-            Operation::new(
-                &mut ctx,
-                op_info,
-                vec![u32_ty.into(); result_count],
-                vec![pointer],
-                vec![],
-                0,
-            )
-            .insert_at_back(entry, &ctx);
-        }
-    } else {
-        for (multiplicity, layout) in [
-            (
-                nvvm::LdmatrixMultiplicityAttr::X1,
-                nvvm::LdmatrixLayoutAttr::Normal,
-            ),
-            (
-                nvvm::LdmatrixMultiplicityAttr::X1,
-                nvvm::LdmatrixLayoutAttr::Transposed,
-            ),
-            (
-                nvvm::LdmatrixMultiplicityAttr::X2,
-                nvvm::LdmatrixLayoutAttr::Normal,
-            ),
-            (
-                nvvm::LdmatrixMultiplicityAttr::X2,
-                nvvm::LdmatrixLayoutAttr::Transposed,
-            ),
-            (
-                nvvm::LdmatrixMultiplicityAttr::X4,
-                nvvm::LdmatrixLayoutAttr::Normal,
-            ),
-            (
-                nvvm::LdmatrixMultiplicityAttr::X4,
-                nvvm::LdmatrixLayoutAttr::Transposed,
-            ),
-        ] {
-            nvvm::LdmatrixOp::build(
-                &mut ctx,
-                pointer,
-                nvvm::LdmatrixShapeAttr::M8n8,
-                multiplicity,
-                layout,
-                nvvm::LdmatrixElementAttr::B16,
-                nvvm::LdmatrixStateSpaceAttr::Shared,
-            )
-            .insert_at_back(entry, &ctx);
-        }
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    Ok((ctx, module_ptr))
-}
-
-fn lower_all_blackwell_ldmatrix_forms(
-    address_space: u32,
-    backend: mir_lower::IntrinsicBackend,
-) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let ptr_ty = MirPtrType::get(&mut ctx, u8_ty.into(), true, address_space);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into()]);
-    let pointer = entry.deref(&ctx).get_argument(0);
-
-    for (shape, multiplicity, layout, element) in [
-        (
-            nvvm::LdmatrixShapeAttr::M16n16,
-            nvvm::LdmatrixMultiplicityAttr::X1,
-            nvvm::LdmatrixLayoutAttr::Transposed,
-            nvvm::LdmatrixElementAttr::B8,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M16n16,
-            nvvm::LdmatrixMultiplicityAttr::X1,
-            nvvm::LdmatrixLayoutAttr::Transposed,
-            nvvm::LdmatrixElementAttr::B8x16B4x16P64,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M16n16,
-            nvvm::LdmatrixMultiplicityAttr::X1,
-            nvvm::LdmatrixLayoutAttr::Transposed,
-            nvvm::LdmatrixElementAttr::B8x16B6x16P32,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M16n16,
-            nvvm::LdmatrixMultiplicityAttr::X2,
-            nvvm::LdmatrixLayoutAttr::Transposed,
-            nvvm::LdmatrixElementAttr::B8,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M16n16,
-            nvvm::LdmatrixMultiplicityAttr::X2,
-            nvvm::LdmatrixLayoutAttr::Transposed,
-            nvvm::LdmatrixElementAttr::B8x16B4x16P64,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M16n16,
-            nvvm::LdmatrixMultiplicityAttr::X2,
-            nvvm::LdmatrixLayoutAttr::Transposed,
-            nvvm::LdmatrixElementAttr::B8x16B6x16P32,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M8n16,
-            nvvm::LdmatrixMultiplicityAttr::X1,
-            nvvm::LdmatrixLayoutAttr::Normal,
-            nvvm::LdmatrixElementAttr::B8x16B4x16P64,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M8n16,
-            nvvm::LdmatrixMultiplicityAttr::X1,
-            nvvm::LdmatrixLayoutAttr::Normal,
-            nvvm::LdmatrixElementAttr::B8x16B6x16P32,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M8n16,
-            nvvm::LdmatrixMultiplicityAttr::X2,
-            nvvm::LdmatrixLayoutAttr::Normal,
-            nvvm::LdmatrixElementAttr::B8x16B4x16P64,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M8n16,
-            nvvm::LdmatrixMultiplicityAttr::X2,
-            nvvm::LdmatrixLayoutAttr::Normal,
-            nvvm::LdmatrixElementAttr::B8x16B6x16P32,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M8n16,
-            nvvm::LdmatrixMultiplicityAttr::X4,
-            nvvm::LdmatrixLayoutAttr::Normal,
-            nvvm::LdmatrixElementAttr::B8x16B4x16P64,
-        ),
-        (
-            nvvm::LdmatrixShapeAttr::M8n16,
-            nvvm::LdmatrixMultiplicityAttr::X4,
-            nvvm::LdmatrixLayoutAttr::Normal,
-            nvvm::LdmatrixElementAttr::B8x16B6x16P32,
-        ),
-    ] {
-        nvvm::LdmatrixOp::build(
-            &mut ctx,
-            pointer,
-            shape,
-            multiplicity,
-            layout,
-            element,
-            nvvm::LdmatrixStateSpaceAttr::Shared,
-        )
-        .insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: backend,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    Ok((ctx, module_ptr))
-}
-
-fn lowered_kernel_body(
-    ctx: &Context,
-    module_ptr: pliron::context::Ptr<Operation>,
-) -> Vec<pliron::context::Ptr<Operation>> {
-    let module_region = module_ptr.deref(ctx).get_region(0);
-    let module_block = module_region.deref(ctx).iter(ctx).next().unwrap();
-    for op in module_block.deref(ctx).iter(ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, ctx) else {
-            continue;
-        };
-        if func_op.get_symbol_name(ctx).to_string() != "kernel_func" {
-            continue;
-        }
-
-        let func_region = func_op.get_operation().deref(ctx).get_region(0);
-        return func_region
-            .deref(ctx)
-            .iter(ctx)
-            .flat_map(|block| block.deref(ctx).iter(ctx))
-            .collect();
-    }
-    panic!("lowered kernel function not found")
-}
-
-fn assert_ldmatrix_producer_result_shape(
-    ctx: &Context,
-    op: pliron::context::Ptr<Operation>,
-    register_count: usize,
-) {
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::types::IntegerType;
-    use pliron::r#type::Typed;
-
-    let ty = op.deref(ctx).get_result(0).get_type(ctx);
-    let ty = ty.deref(ctx);
-    if register_count == 1 {
-        assert_eq!(
-            ty.downcast_ref::<IntegerType>()
-                .expect("single-register ldmatrix returns i32")
-                .width(),
-            32
-        );
-    } else {
-        let ty = ty
-            .downcast_ref::<llvm_types::StructType>()
-            .expect("multi-register ldmatrix returns an LLVM struct");
-        assert_eq!(ty.num_fields(), register_count);
-        for index in 0..register_count {
-            assert_eq!(
-                ty.field_type(index)
-                    .deref(ctx)
-                    .downcast_ref::<IntegerType>()
-                    .expect("ldmatrix fragment field is i32")
-                    .width(),
-                32
-            );
-        }
-    }
-}
-
-#[test]
-fn test_ldmatrix_llvm_nvptx_uses_exact_typed_p3_intrinsics() -> Result<(), anyhow::Error> {
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::type_interfaces::FunctionTypeInterface;
-    use pliron::builtin::types::IntegerType;
-    use pliron::r#type::Typed;
-
-    for address_space in [0, 3] {
-        let (ctx, module_ptr) =
-            lower_all_ldmatrix_forms(address_space, mir_lower::IntrinsicBackend::LlvmNvptx, false)?;
-        let body = lowered_kernel_body(&ctx, module_ptr);
-        let mut callees = Vec::new();
-        let mut cast_count = 0;
-        let mut extract_count = 0;
-
-        for op in body {
-            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-                && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-            {
-                let callee = callee.to_string();
-                let register_count = if callee.contains("_x1_") {
-                    1
-                } else if callee.contains("_x2_") {
-                    2
-                } else {
-                    4
-                };
-                let function_ty = call.callee_type(&ctx);
-                let function_ty = function_ty.deref(&ctx);
-                let function_ty = function_ty
-                    .downcast_ref::<llvm_types::FuncType>()
-                    .expect("ldmatrix callee has an LLVM function type");
-                assert_eq!(function_ty.arg_types().len(), 1);
-                let argument_ty = function_ty.arg_types()[0].deref(&ctx);
-                let argument_ty = argument_ty
-                    .downcast_ref::<llvm_types::PointerType>()
-                    .expect("ldmatrix argument is a pointer");
-                assert_eq!(argument_ty.address_space(), 3);
-
-                let result_ty = function_ty.result_type();
-                let result_ty = result_ty.deref(&ctx);
-                if register_count == 1 {
-                    let result_ty = result_ty
-                        .downcast_ref::<IntegerType>()
-                        .expect("x1 returns i32");
-                    assert_eq!(result_ty.width(), 32);
-                } else {
-                    let result_ty = result_ty
-                        .downcast_ref::<llvm_types::StructType>()
-                        .expect("x2/x4 return an LLVM struct");
-                    assert_eq!(result_ty.num_fields(), register_count);
-                    for index in 0..result_ty.num_fields() {
-                        let field = result_ty.field_type(index);
-                        let field = field.deref(&ctx);
-                        let field = field
-                            .downcast_ref::<IntegerType>()
-                            .expect("fragment register is i32");
-                        assert_eq!(field.width(), 32);
-                    }
-                }
-
-                callees.push(callee);
-                assert_eq!(op.deref(&ctx).get_num_operands(), 1);
-                assert_eq!(op.deref(&ctx).get_num_results(), 1);
-            }
-            if Operation::get_op::<llvm::AddrSpaceCastOp>(op, &ctx).is_some() {
-                cast_count += 1;
-                let cast = op.deref(&ctx);
-                let source_ty = cast.get_operand(0).get_type(&ctx);
-                let source_ty = source_ty.deref(&ctx);
-                let source_ty = source_ty
-                    .downcast_ref::<llvm_types::PointerType>()
-                    .expect("addrspacecast source is a pointer");
-                let result_ty = cast.get_result(0).get_type(&ctx);
-                let result_ty = result_ty.deref(&ctx);
-                let result_ty = result_ty
-                    .downcast_ref::<llvm_types::PointerType>()
-                    .expect("addrspacecast result is a pointer");
-                assert_eq!(
-                    (source_ty.address_space(), result_ty.address_space()),
-                    (0, 3)
-                );
-            }
-            extract_count +=
-                usize::from(Operation::get_op::<llvm::ExtractValueOp>(op, &ctx).is_some());
-            assert!(
-                Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
-                "LLVM-NVPTX ldmatrix lowering must not emit inline PTX"
-            );
-            assert!(
-                Operation::get_op::<llvm::PtrToIntOp>(op, &ctx).is_none(),
-                "the typed intrinsic consumes the shared pointer directly"
-            );
-        }
-
-        callees.sort();
-        let mut expected = LDMATRIX_TYPED_INTRINSICS.map(str::to_owned);
-        expected.sort();
-        assert_eq!(callees, expected);
-        assert_eq!(cast_count, if address_space == 0 { 6 } else { 0 });
-        assert_eq!(
-            extract_count, 12,
-            "x2/x4 structs must preserve result order"
-        );
-
-        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-            .expect("typed ldmatrix module exports to LLVM IR");
-        for intrinsic in LDMATRIX_TYPED_INTRINSICS {
-            let dotted = intrinsic.replace('_', ".");
-            assert!(
-                ir.contains(&format!("@{dotted}(ptr addrspace(3)")),
-                "underscore symbol must export as exact dotted p3 intrinsic:\n{ir}"
-            );
-        }
-        assert!(!ir.contains("@llvm_nvvm_ldmatrix"));
-    }
-    Ok(())
-}
-
-#[test]
-fn test_ldmatrix_libnvvm_uses_exact_convergent_shared_ptx() -> Result<(), anyhow::Error> {
-    use llvm_export::types as llvm_types;
-    use pliron::r#type::Typed;
-
-    for address_space in [0, 3] {
-        let (ctx, module_ptr) =
-            lower_all_ldmatrix_forms(address_space, mir_lower::IntrinsicBackend::LibNvvm, false)?;
-        let body = lowered_kernel_body(&ctx, module_ptr);
-        let mut lowered = Vec::new();
-        let mut cast_count = 0;
-        let mut ptrtoint_count = 0;
-
-        for op in body {
-            assert!(
-                Operation::get_op::<llvm::CallOp>(op, &ctx).is_none(),
-                "libNVVM ldmatrix lowering must not emit typed intrinsic calls"
-            );
-            cast_count +=
-                usize::from(Operation::get_op::<llvm::AddrSpaceCastOp>(op, &ctx).is_some());
-            if Operation::get_op::<llvm::PtrToIntOp>(op, &ctx).is_some() {
-                ptrtoint_count += 1;
-                let cast = op.deref(&ctx);
-                let source_ty = cast.get_operand(0).get_type(&ctx);
-                let source_ty = source_ty.deref(&ctx);
-                let source_ty = source_ty
-                    .downcast_ref::<llvm_types::PointerType>()
-                    .expect("ptrtoint source is a pointer");
-                assert_eq!(source_ty.address_space(), 3);
-            }
-
-            let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-                continue;
-            };
-            lowered.push((
-                inline_asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .unwrap_or_default(),
-                inline_asm
-                    .get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .unwrap_or_default(),
-                llvm::asm_kind(&ctx, &inline_asm),
-                op.deref(&ctx).get_num_operands(),
-                op.deref(&ctx).get_num_results(),
-            ));
-        }
-
-        assert_eq!(lowered.len(), 6);
-        for (index, expected_template) in LDMATRIX_PTX_TEMPLATES.iter().enumerate() {
-            let matching: Vec<_> = lowered
-                .iter()
-                .filter(|(template, _, _, _, _)| template == expected_template)
-                .collect();
-            assert_eq!(matching.len(), 1, "missing exact PTX `{expected_template}`");
-            let (_, constraints, kind, operands, results) = matching[0];
-            assert_eq!(constraints, LDMATRIX_PTX_CONSTRAINTS[index]);
-            assert_eq!(*kind, llvm::AsmKind::Convergent);
-            assert_eq!(*operands, 1, "inline PTX consumes one i32 shared address");
-            assert_eq!(*results, 1, "inline PTX returns one scalar or struct");
-            assert!(!expected_template.contains("cvta.to.shared"));
-        }
-        assert_eq!(cast_count, if address_space == 0 { 6 } else { 0 });
-        assert_eq!(ptrtoint_count, 6);
-
-        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-            .expect("inline ldmatrix module exports to LLVM IR");
-        assert_eq!(ir.matches("asm sideeffect").count(), 6, "{ir}");
-        assert_eq!(ir.matches("~{memory}").count(), 6, "{ir}");
-        assert!(ir.contains("attributes #0 = { convergent }"), "{ir}");
-        assert!(!ir.contains("@llvm.nvvm.ldmatrix"), "{ir}");
-    }
-    Ok(())
-}
-
-#[test]
-fn test_blackwell_ldmatrix_llvm_uses_all_exact_lossless_p3_intrinsics() -> Result<(), anyhow::Error>
-{
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::type_interfaces::FunctionTypeInterface;
-
-    for address_space in [0, 3] {
-        let (ctx, module_ptr) = lower_all_blackwell_ldmatrix_forms(
-            address_space,
-            mir_lower::IntrinsicBackend::LlvmNvptx,
-        )?;
-        let mut seen = [0; 12];
-        let mut cast_count = 0;
-        let mut extract_count = 0;
-
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            assert!(Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none());
-            assert!(Operation::get_op::<llvm::PtrToIntOp>(op, &ctx).is_none());
-            cast_count +=
-                usize::from(Operation::get_op::<llvm::AddrSpaceCastOp>(op, &ctx).is_some());
-            extract_count +=
-                usize::from(Operation::get_op::<llvm::ExtractValueOp>(op, &ctx).is_some());
-
-            let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-                continue;
-            };
-            let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-                panic!("Blackwell ldmatrix intrinsic call must be direct");
-            };
-            let callee = callee.to_string();
-            let index = BLACKWELL_LDMATRIX_CASES
-                .iter()
-                .position(|(identifier, _, _, _)| *identifier == callee)
-                .expect("exact lossless Blackwell ldmatrix identifier");
-            seen[index] += 1;
-            let register_count = BLACKWELL_LDMATRIX_CASES[index].3;
-            assert_ldmatrix_producer_result_shape(&ctx, op, register_count);
-
-            let function_ty = call.callee_type(&ctx);
-            let function_ty = function_ty.deref(&ctx);
-            let function_ty = function_ty
-                .downcast_ref::<llvm_types::FuncType>()
-                .expect("Blackwell ldmatrix has an LLVM function type");
-            assert_eq!(function_ty.arg_types().len(), 1);
-            assert_eq!(
-                function_ty.arg_types()[0]
-                    .deref(&ctx)
-                    .downcast_ref::<llvm_types::PointerType>()
-                    .expect("Blackwell ldmatrix argument is a pointer")
-                    .address_space(),
-                3
-            );
-        }
-
-        assert_eq!(seen, [1; 12]);
-        assert_eq!(cast_count, if address_space == 0 { 12 } else { 0 });
-        assert_eq!(extract_count, 30, "all multi-register results are unpacked");
-
-        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-            .expect("typed Blackwell ldmatrix module exports to LLVM IR");
-        for (identifier, symbol, _, _) in BLACKWELL_LDMATRIX_CASES {
-            assert!(
-                ir.contains(&format!("@{symbol}(ptr addrspace(3)")),
-                "missing exact intrinsic symbol {symbol}:\n{ir}"
-            );
-            assert!(
-                !ir.contains(&format!("@{identifier}(")),
-                "encoded Rust identifier leaked into LLVM IR: {identifier}"
-            );
-        }
-        assert!(ir.contains("b4x16_p64.p3"), "literal _p64 was lost: {ir}");
-        assert!(ir.contains("b6x16_p32.p3"), "literal _p32 was lost: {ir}");
-    }
-    Ok(())
-}
-
-#[test]
-fn test_blackwell_ldmatrix_libnvvm_uses_all_exact_convergent_templates_without_externs()
--> Result<(), anyhow::Error> {
-    for address_space in [0, 3] {
-        let (ctx, module_ptr) = lower_all_blackwell_ldmatrix_forms(
-            address_space,
-            mir_lower::IntrinsicBackend::LibNvvm,
-        )?;
-        let mut seen = [0; 12];
-        let mut cast_count = 0;
-        let mut ptrtoint_count = 0;
-        let mut extract_count = 0;
-
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            assert!(
-                Operation::get_op::<llvm::CallOp>(op, &ctx).is_none(),
-                "libNVVM Blackwell ldmatrix must not emit an extern call"
-            );
-            cast_count +=
-                usize::from(Operation::get_op::<llvm::AddrSpaceCastOp>(op, &ctx).is_some());
-            ptrtoint_count +=
-                usize::from(Operation::get_op::<llvm::PtrToIntOp>(op, &ctx).is_some());
-            extract_count +=
-                usize::from(Operation::get_op::<llvm::ExtractValueOp>(op, &ctx).is_some());
-
-            let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-                continue;
-            };
-            let template = asm
-                .get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .unwrap_or_default();
-            let index = BLACKWELL_LDMATRIX_CASES
-                .iter()
-                .position(|(_, _, expected, _)| *expected == template)
-                .expect("exact Blackwell ldmatrix inline-PTX template");
-            seen[index] += 1;
-            let register_count = BLACKWELL_LDMATRIX_CASES[index].3;
-            assert_eq!(
-                asm.get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .as_deref(),
-                Some(ldmatrix_constraints(register_count))
-            );
-            assert_eq!(llvm::asm_kind(&ctx, &asm), llvm::AsmKind::Convergent);
-            assert_ldmatrix_producer_result_shape(&ctx, op, register_count);
-        }
-
-        assert_eq!(seen, [1; 12]);
-        assert_eq!(cast_count, if address_space == 0 { 12 } else { 0 });
-        assert_eq!(ptrtoint_count, 12);
-        assert_eq!(extract_count, 30, "all multi-register results are unpacked");
-
-        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-            .expect("inline Blackwell ldmatrix module exports to LLVM IR");
-        assert_eq!(ir.matches("asm sideeffect").count(), 12, "{ir}");
-        assert_eq!(ir.matches("~{memory}").count(), 12, "{ir}");
-        assert!(!ir.contains("@llvm.nvvm.ldmatrix"), "{ir}");
-        assert!(!ir.contains("llvm__nvvm_dldmatrix"), "{ir}");
-    }
-    Ok(())
-}
-
-#[test]
-fn test_blackwell_ldmatrix_rejects_unadmitted_m16n16_x4() {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        let mut ctx = make_test_ctx();
-        let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-        let ptr_ty = MirPtrType::get_shared(&mut ctx, u8_ty.into(), false);
-        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into()]);
-        let pointer = entry.deref(&ctx).get_argument(0);
-        nvvm::LdmatrixOp::build(
-            &mut ctx,
-            pointer,
-            nvvm::LdmatrixShapeAttr::M16n16,
-            nvvm::LdmatrixMultiplicityAttr::X4,
-            nvvm::LdmatrixLayoutAttr::Transposed,
-            nvvm::LdmatrixElementAttr::B8,
-            nvvm::LdmatrixStateSpaceAttr::Shared,
-        )
-        .insert_at_back(entry, &ctx);
-        append_return(&mut ctx, entry);
-
-        let error = mir_lower::lower_mir_to_llvm_with_options(
-            &mut ctx,
-            module_ptr,
-            mir_lower::LoweringOptions {
-                intrinsic_backend: backend,
-                ..Default::default()
-            },
-        )
-        .expect_err("m16n16.x4 must fail closed")
-        .to_string();
-        assert!(error.contains("missing or unsupported variant"), "{error}");
-    }
-}
-
-#[test]
-fn test_classic_ldmatrix_compatibility_ops_keep_exact_lowering() -> Result<(), anyhow::Error> {
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::types::IntegerType;
-    use pliron::r#type::Typed;
-
-    fn assert_result_shape(
-        ctx: &Context,
-        op: pliron::context::Ptr<Operation>,
-        register_count: usize,
-    ) {
-        let operation = op.deref(ctx);
-        assert_eq!(operation.get_num_operands(), 1);
-        assert_eq!(operation.get_num_results(), 1);
-        let result_ty = operation.get_result(0).get_type(ctx);
-        let result_ty = result_ty.deref(ctx);
-        if register_count == 1 {
-            let result_ty = result_ty
-                .downcast_ref::<IntegerType>()
-                .expect("x1 returns i32");
-            assert_eq!(result_ty.width(), 32);
-        } else {
-            let result_ty = result_ty
-                .downcast_ref::<llvm_types::StructType>()
-                .expect("x2/x4 return an LLVM struct");
-            assert_eq!(result_ty.num_fields(), register_count);
-            for index in 0..result_ty.num_fields() {
-                let field = result_ty.field_type(index);
-                let field = field.deref(ctx);
-                let field = field
-                    .downcast_ref::<IntegerType>()
-                    .expect("fragment register is i32");
-                assert_eq!(field.width(), 32);
-            }
-        }
-    }
-
-    let register_counts = [1, 1, 2, 2, 4, 4];
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        let (ctx, module_ptr) = lower_all_ldmatrix_forms(3, backend, true)?;
-        let mut seen = [0; 6];
-        let mut extract_count = 0;
-
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            extract_count +=
-                usize::from(Operation::get_op::<llvm::ExtractValueOp>(op, &ctx).is_some());
-            match backend {
-                mir_lower::IntrinsicBackend::LlvmNvptx => {
-                    assert!(Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none());
-                    let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
-                        continue;
-                    };
-                    let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
-                        panic!("ldmatrix intrinsic call must be direct");
-                    };
-                    let callee = callee.to_string();
-                    let index = LDMATRIX_TYPED_INTRINSICS
-                        .iter()
-                        .position(|expected| *expected == callee)
-                        .expect("exact typed ldmatrix intrinsic");
-                    seen[index] += 1;
-                    assert_result_shape(&ctx, op, register_counts[index]);
-                }
-                mir_lower::IntrinsicBackend::LibNvvm => {
-                    assert!(Operation::get_op::<llvm::CallOp>(op, &ctx).is_none());
-                    let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-                        continue;
-                    };
-                    let template = inline_asm
-                        .get_attr_inline_asm_template(&ctx)
-                        .map(|value| String::from((*value).clone()))
-                        .unwrap_or_default();
-                    let index = LDMATRIX_PTX_TEMPLATES
-                        .iter()
-                        .position(|expected| *expected == template)
-                        .expect("exact ldmatrix PTX template");
-                    seen[index] += 1;
-                    assert_eq!(
-                        inline_asm
-                            .get_attr_inline_asm_constraints(&ctx)
-                            .map(|value| String::from((*value).clone()))
-                            .as_deref(),
-                        Some(LDMATRIX_PTX_CONSTRAINTS[index])
-                    );
-                    assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Convergent);
-                    assert_result_shape(&ctx, op, register_counts[index]);
-                }
-            }
-        }
-
-        assert_eq!(seen, [1; 6]);
-        assert_eq!(extract_count, 12, "x2/x4 results keep their order");
-    }
-    Ok(())
-}
-
-#[test]
-fn test_ldmatrix_rejects_non_shared_pointer_spaces() {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        for address_space in [1, 4, 5] {
-            let mut ctx = make_test_ctx();
-            let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-            let ptr_ty = MirPtrType::get(&mut ctx, u32_ty.into(), false, address_space);
-            let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into()]);
-            let pointer = entry.deref(&ctx).get_argument(0);
-            nvvm::LdmatrixOp::build(
-                &mut ctx,
-                pointer,
-                nvvm::LdmatrixShapeAttr::M8n8,
-                nvvm::LdmatrixMultiplicityAttr::X1,
-                nvvm::LdmatrixLayoutAttr::Normal,
-                nvvm::LdmatrixElementAttr::B16,
-                nvvm::LdmatrixStateSpaceAttr::Shared,
-            )
-            .insert_at_back(entry, &ctx);
-            append_return(&mut ctx, entry);
-
-            let error = mir_lower::lower_mir_to_llvm_with_options(
-                &mut ctx,
-                module_ptr,
-                mir_lower::LoweringOptions {
-                    intrinsic_backend: backend,
-                    ..Default::default()
-                },
-            )
-            .expect_err("global/constant pointers must fail closed")
-            .to_string();
-            assert!(
-                error.contains(&format!("not address space {address_space}")),
-                "{error}"
-            );
-        }
-    }
-}
-
-#[test]
-fn test_ldmatrix_rejects_non_pointer_operand() {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
-    let not_a_pointer = entry.deref(&ctx).get_argument(0);
-    nvvm::LdmatrixOp::build(
-        &mut ctx,
-        not_a_pointer,
-        nvvm::LdmatrixShapeAttr::M8n8,
-        nvvm::LdmatrixMultiplicityAttr::X1,
-        nvvm::LdmatrixLayoutAttr::Normal,
-        nvvm::LdmatrixElementAttr::B16,
-        nvvm::LdmatrixStateSpaceAttr::Shared,
-    )
-    .insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    let error = mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .expect_err("non-pointer ldmatrix input must fail closed")
-        .to_string();
-    assert!(error.contains("operand must be a MIR pointer"), "{error}");
-}
-
-#[test]
-fn test_ldmatrix_rejects_wrong_result_arity() {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    let ptr_ty = MirPtrType::get_shared(&mut ctx, u32_ty.into(), false);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into()]);
-    let pointer = entry.deref(&ctx).get_argument(0);
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::LdmatrixOp::get_concrete_op_info(),
-        vec![i32_ty.into(), i32_ty.into()],
-        vec![pointer],
-        vec![],
-        0,
-    );
-    let ldmatrix = nvvm::LdmatrixOp::new(op);
-    ldmatrix.set_attr_nvvm_ldmatrix_shape(&ctx, nvvm::LdmatrixShapeAttr::M8n8);
-    ldmatrix.set_attr_nvvm_ldmatrix_multiplicity(&ctx, nvvm::LdmatrixMultiplicityAttr::X1);
-    ldmatrix.set_attr_nvvm_ldmatrix_layout(&ctx, nvvm::LdmatrixLayoutAttr::Normal);
-    ldmatrix.set_attr_nvvm_ldmatrix_element(&ctx, nvvm::LdmatrixElementAttr::B16);
-    ldmatrix.set_attr_nvvm_ldmatrix_state_space(&ctx, nvvm::LdmatrixStateSpaceAttr::Shared);
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    let error = mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .expect_err("x1 must return exactly one register")
-        .to_string();
-    assert!(error.contains("requires 1 u32 results"), "{error}");
-}
-
-#[test]
-fn test_generated_register_mma_variants_lower_to_exact_convergent_inline_ptx()
--> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{FP32Type, FP64Type, IntegerType, Signedness};
-    use pliron::r#type::TypeHandle;
-
-    #[derive(Clone, Copy)]
-    enum Carrier {
-        F32,
-        F64,
-        I32,
-        U32,
-    }
-
-    struct Case {
-        shape: nvvm::RegisterMmaShapeAttr,
-        operation: nvvm::RegisterMmaOperationAttr,
-        accumulator: nvvm::RegisterMmaAccumulatorAttr,
-        a_element: nvvm::RegisterMmaElementAttr,
-        b_element: nvvm::RegisterMmaElementAttr,
-        overflow: nvvm::RegisterMmaOverflowAttr,
-        operands: &'static [Carrier],
-        results: &'static [Carrier],
-        template: String,
-        constraints: &'static str,
-    }
-
-    let mut cases = vec![
-        Case {
-            shape: nvvm::RegisterMmaShapeAttr::M16n8k16,
-            operation: nvvm::RegisterMmaOperationAttr::Multiply,
-            accumulator: nvvm::RegisterMmaAccumulatorAttr::F32,
-            a_element: nvvm::RegisterMmaElementAttr::Bf16,
-            b_element: nvvm::RegisterMmaElementAttr::Bf16,
-            overflow: nvvm::RegisterMmaOverflowAttr::NotApplicable,
-            operands: &[
-                Carrier::F32,
-                Carrier::F32,
-                Carrier::F32,
-                Carrier::F32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-            ],
-            results: &[Carrier::F32; 4],
-            template: concat!(
-                "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 ",
-                "{$0, $1, $2, $3}, {$8, $9, $10, $11}, ",
-                "{$12, $13}, {$4, $5, $6, $7};"
-            )
-            .into(),
-            constraints: "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-        },
-        Case {
-            shape: nvvm::RegisterMmaShapeAttr::M16n8k16,
-            operation: nvvm::RegisterMmaOperationAttr::Multiply,
-            accumulator: nvvm::RegisterMmaAccumulatorAttr::F32,
-            a_element: nvvm::RegisterMmaElementAttr::F16,
-            b_element: nvvm::RegisterMmaElementAttr::F16,
-            overflow: nvvm::RegisterMmaOverflowAttr::NotApplicable,
-            operands: &[
-                Carrier::F32,
-                Carrier::F32,
-                Carrier::F32,
-                Carrier::F32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-            ],
-            results: &[Carrier::F32; 4],
-            template: concat!(
-                "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 ",
-                "{$0, $1, $2, $3}, {$8, $9, $10, $11}, ",
-                "{$12, $13}, {$4, $5, $6, $7};"
-            )
-            .into(),
-            constraints: "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-        },
-        Case {
-            shape: nvvm::RegisterMmaShapeAttr::M16n8k8,
-            operation: nvvm::RegisterMmaOperationAttr::Multiply,
-            accumulator: nvvm::RegisterMmaAccumulatorAttr::F32,
-            a_element: nvvm::RegisterMmaElementAttr::Tf32,
-            b_element: nvvm::RegisterMmaElementAttr::Tf32,
-            overflow: nvvm::RegisterMmaOverflowAttr::NotApplicable,
-            operands: &[
-                Carrier::F32,
-                Carrier::F32,
-                Carrier::F32,
-                Carrier::F32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-                Carrier::U32,
-            ],
-            results: &[Carrier::F32; 4],
-            template: concat!(
-                "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 ",
-                "{$0, $1, $2, $3}, {$8, $9, $10, $11}, ",
-                "{$12, $13}, {$4, $5, $6, $7};"
-            )
-            .into(),
-            constraints: "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
-        },
-        Case {
-            shape: nvvm::RegisterMmaShapeAttr::M8n8k4,
-            operation: nvvm::RegisterMmaOperationAttr::Multiply,
-            accumulator: nvvm::RegisterMmaAccumulatorAttr::F64,
-            a_element: nvvm::RegisterMmaElementAttr::F64,
-            b_element: nvvm::RegisterMmaElementAttr::F64,
-            overflow: nvvm::RegisterMmaOverflowAttr::NotApplicable,
-            operands: &[Carrier::F64; 4],
-            results: &[Carrier::F64; 2],
-            template: concat!(
-                "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 ",
-                "{$0, $1}, {$4}, {$5}, {$2, $3};"
-            )
-            .into(),
-            constraints: "=d,=d,d,d,d,d",
-        },
-    ];
-    let c2_a1_b1: &'static [Carrier] = &[Carrier::I32, Carrier::I32, Carrier::U32, Carrier::U32];
-    let c4_a2_b1: &'static [Carrier] = &[
-        Carrier::I32,
-        Carrier::I32,
-        Carrier::I32,
-        Carrier::I32,
-        Carrier::U32,
-        Carrier::U32,
-        Carrier::U32,
-    ];
-    let c4_a4_b2: &'static [Carrier] = &[
-        Carrier::I32,
-        Carrier::I32,
-        Carrier::I32,
-        Carrier::I32,
-        Carrier::U32,
-        Carrier::U32,
-        Carrier::U32,
-        Carrier::U32,
-        Carrier::U32,
-        Carrier::U32,
-    ];
-    let d2_i32: &'static [Carrier] = &[Carrier::I32; 2];
-    let d4_i32: &'static [Carrier] = &[Carrier::I32; 4];
-    let register_list = |first, count| {
-        format!(
-            "{{{}}}",
-            (first..first + count)
-                .map(|index| format!("${index}"))
-                .collect::<Vec<_>>()
-                .join(", ")
-        )
-    };
-
-    for (shape, shape_attr, operands, results, accumulator_count, a_count, b_count, constraints) in [
-        (
-            "m8n8k16",
-            nvvm::RegisterMmaShapeAttr::M8n8k16,
-            c2_a1_b1,
-            d2_i32,
-            2,
-            1,
-            1,
-            "=r,=r,r,r,r,r",
-        ),
-        (
-            "m16n8k16",
-            nvvm::RegisterMmaShapeAttr::M16n8k16,
-            c4_a2_b1,
-            d4_i32,
-            4,
-            2,
-            1,
-            "=r,=r,=r,=r,r,r,r,r,r,r,r",
-        ),
-        (
-            "m16n8k32",
-            nvvm::RegisterMmaShapeAttr::M16n8k32,
-            c4_a4_b2,
-            d4_i32,
-            4,
-            4,
-            2,
-            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-        ),
-    ] {
-        for (a_name, a_element) in [
-            ("s8", nvvm::RegisterMmaElementAttr::S8),
-            ("u8", nvvm::RegisterMmaElementAttr::U8),
-        ] {
-            for (b_name, b_element) in [
-                ("s8", nvvm::RegisterMmaElementAttr::S8),
-                ("u8", nvvm::RegisterMmaElementAttr::U8),
-            ] {
-                for (overflow_name, overflow) in [
-                    ("", nvvm::RegisterMmaOverflowAttr::Wrapping),
-                    (".satfinite", nvvm::RegisterMmaOverflowAttr::Satfinite),
-                ] {
-                    let result_count = results.len();
-                    let d = register_list(0, result_count);
-                    let c = register_list(result_count, accumulator_count);
-                    let a = register_list(result_count + accumulator_count, a_count);
-                    let b = register_list(result_count + accumulator_count + a_count, b_count);
-                    cases.push(Case {
-                        shape: shape_attr.clone(),
-                        operation: nvvm::RegisterMmaOperationAttr::Multiply,
-                        accumulator: nvvm::RegisterMmaAccumulatorAttr::S32,
-                        a_element: a_element.clone(),
-                        b_element: b_element.clone(),
-                        overflow,
-                        operands,
-                        results,
-                        template: format!(
-                            "mma.sync.aligned.{shape}.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {d}, {a}, {b}, {c};"
-                        ),
-                        constraints,
-                    });
-                }
-            }
-        }
-    }
-
-    for (shape, shape_attr, operands, results, accumulator_count, a_count, b_count, constraints) in [
-        (
-            "m8n8k32",
-            nvvm::RegisterMmaShapeAttr::M8n8k32,
-            c2_a1_b1,
-            d2_i32,
-            2,
-            1,
-            1,
-            "=r,=r,r,r,r,r",
-        ),
-        (
-            "m16n8k32",
-            nvvm::RegisterMmaShapeAttr::M16n8k32,
-            c4_a2_b1,
-            d4_i32,
-            4,
-            2,
-            1,
-            "=r,=r,=r,=r,r,r,r,r,r,r,r",
-        ),
-        (
-            "m16n8k64",
-            nvvm::RegisterMmaShapeAttr::M16n8k64,
-            c4_a4_b2,
-            d4_i32,
-            4,
-            4,
-            2,
-            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-        ),
-    ] {
-        for (a_name, a_element) in [
-            ("s4", nvvm::RegisterMmaElementAttr::S4),
-            ("u4", nvvm::RegisterMmaElementAttr::U4),
-        ] {
-            for (b_name, b_element) in [
-                ("s4", nvvm::RegisterMmaElementAttr::S4),
-                ("u4", nvvm::RegisterMmaElementAttr::U4),
-            ] {
-                for (overflow_name, overflow) in [
-                    ("", nvvm::RegisterMmaOverflowAttr::Wrapping),
-                    (".satfinite", nvvm::RegisterMmaOverflowAttr::Satfinite),
-                ] {
-                    let result_count = results.len();
-                    let d = register_list(0, result_count);
-                    let c = register_list(result_count, accumulator_count);
-                    let a = register_list(result_count + accumulator_count, a_count);
-                    let b = register_list(result_count + accumulator_count + a_count, b_count);
-                    cases.push(Case {
-                        shape: shape_attr.clone(),
-                        operation: nvvm::RegisterMmaOperationAttr::Multiply,
-                        accumulator: nvvm::RegisterMmaAccumulatorAttr::S32,
-                        a_element: a_element.clone(),
-                        b_element: b_element.clone(),
-                        overflow,
-                        operands,
-                        results,
-                        template: format!(
-                            "mma.sync.aligned.{shape}.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {d}, {a}, {b}, {c};"
-                        ),
-                        constraints,
-                    });
-                }
-            }
-        }
-    }
-
-    for (shape, shape_attr, operands, results, accumulator_count, a_count, b_count, constraints) in [
-        (
-            "m8n8k128",
-            nvvm::RegisterMmaShapeAttr::M8n8k128,
-            c2_a1_b1,
-            d2_i32,
-            2,
-            1,
-            1,
-            "=r,=r,r,r,r,r",
-        ),
-        (
-            "m16n8k128",
-            nvvm::RegisterMmaShapeAttr::M16n8k128,
-            c4_a2_b1,
-            d4_i32,
-            4,
-            2,
-            1,
-            "=r,=r,=r,=r,r,r,r,r,r,r,r",
-        ),
-        (
-            "m16n8k256",
-            nvvm::RegisterMmaShapeAttr::M16n8k256,
-            c4_a4_b2,
-            d4_i32,
-            4,
-            4,
-            2,
-            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
-        ),
-    ] {
-        let result_count = results.len();
-        let d = register_list(0, result_count);
-        let c = register_list(result_count, accumulator_count);
-        let a = register_list(result_count + accumulator_count, a_count);
-        let b = register_list(result_count + accumulator_count + a_count, b_count);
-        for (operation_name, operation) in [
-            ("xor", nvvm::RegisterMmaOperationAttr::XorPopc),
-            ("and", nvvm::RegisterMmaOperationAttr::AndPopc),
-        ] {
-            cases.push(Case {
-                shape: shape_attr.clone(),
-                operation,
-                accumulator: nvvm::RegisterMmaAccumulatorAttr::S32,
-                a_element: nvvm::RegisterMmaElementAttr::B1,
-                b_element: nvvm::RegisterMmaElementAttr::B1,
-                overflow: nvvm::RegisterMmaOverflowAttr::Wrapping,
-                operands,
-                results,
-                template: format!(
-                    "mma.sync.aligned.{shape}.row.col.s32.b1.b1.s32.{operation_name}.popc {d}, {a}, {b}, {c};"
-                ),
-                constraints,
-            });
-        }
-    }
-    assert_eq!(cases.len(), 58);
-
-    let carrier_type = |ctx: &Context, carrier: Carrier| -> TypeHandle {
-        match carrier {
-            Carrier::F32 => FP32Type::get(ctx).into(),
-            Carrier::F64 => FP64Type::get(ctx).into(),
-            Carrier::I32 => IntegerType::get(ctx, 32, Signedness::Signed).into(),
-            Carrier::U32 => IntegerType::get(ctx, 32, Signedness::Unsigned).into(),
-        }
-    };
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        for case in &cases {
-            let mut ctx = make_test_ctx();
-            let argument_types = case
-                .operands
-                .iter()
-                .map(|carrier| carrier_type(&ctx, *carrier))
-                .collect();
-            let result_types = case
-                .results
-                .iter()
-                .map(|carrier| carrier_type(&ctx, *carrier))
-                .collect();
-            let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-            let operands = (0..case.operands.len())
-                .map(|index| entry.deref(&ctx).get_argument(index))
-                .collect();
-            let operation = Operation::new(
-                &mut ctx,
-                nvvm::RegisterMmaOp::get_concrete_op_info(),
-                result_types,
-                operands,
-                vec![],
-                0,
-            );
-            let mma = nvvm::RegisterMmaOp::new(operation);
-            mma.set_attr_nvvm_register_mma_shape(&ctx, case.shape.clone());
-            let uses_legacy_default = matches!(
-                (&case.operation, &case.a_element),
-                (
-                    nvvm::RegisterMmaOperationAttr::Multiply,
-                    nvvm::RegisterMmaElementAttr::Bf16
-                )
-            );
-            if !uses_legacy_default {
-                mma.set_attr_nvvm_register_mma_operation(&ctx, case.operation.clone());
-            }
-            mma.set_attr_nvvm_register_mma_accumulator(&ctx, case.accumulator.clone());
-            mma.set_attr_nvvm_register_mma_a_element(&ctx, case.a_element.clone());
-            mma.set_attr_nvvm_register_mma_b_element(&ctx, case.b_element.clone());
-            mma.set_attr_nvvm_register_mma_a_layout(&ctx, nvvm::RegisterMmaLayoutAttr::Row);
-            mma.set_attr_nvvm_register_mma_b_layout(&ctx, nvvm::RegisterMmaLayoutAttr::Col);
-            mma.set_attr_nvvm_register_mma_overflow(&ctx, case.overflow.clone());
-            operation.insert_at_back(entry, &ctx);
-            append_return(&mut ctx, entry);
-
-            mir_lower::lower_mir_to_llvm_with_options(
-                &mut ctx,
-                module_ptr,
-                mir_lower::LoweringOptions {
-                    intrinsic_backend: backend,
-                    ..Default::default()
-                },
-            )
-            .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-            let body = lowered_kernel_body(&ctx, module_ptr);
-            let lowered = body
-                .iter()
-                .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(*op, &ctx))
-                .collect::<Vec<_>>();
-            assert_eq!(lowered.len(), 1, "{:?}", backend);
-            let asm = &lowered[0];
-            assert_eq!(
-                asm.get_attr_inline_asm_template(&ctx)
-                    .as_deref()
-                    .map(|value| String::from(value.clone())),
-                Some(case.template.clone())
-            );
-            assert_eq!(
-                asm.get_attr_inline_asm_constraints(&ctx)
-                    .as_deref()
-                    .map(|value| String::from(value.clone())),
-                Some(case.constraints.to_string())
-            );
-            assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-            assert_eq!(
-                asm.get_operation().deref(&ctx).get_num_operands(),
-                case.operands.len()
-            );
-            assert_eq!(asm.get_operation().deref(&ctx).get_num_results(), 1);
-            assert_eq!(
-                body.iter()
-                    .filter(|op| Operation::get_op::<llvm::ExtractValueOp>(**op, &ctx).is_some())
-                    .count(),
-                case.results.len()
-            );
-
-            let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-            let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-                .expect("generated register MMA exports to LLVM IR");
-            assert!(ir.contains("asm sideeffect"), "{ir}");
-            assert!(ir.contains("{ convergent }"), "{ir}");
-        }
-    }
-
-    Ok(())
-}
-
-#[test]
-fn test_generated_sparse_mma_variants_lower_to_exact_convergent_inline_ptx()
--> Result<(), anyhow::Error> {
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let cases = [
-        (
-            "s8",
-            "s8",
-            "",
-            nvvm::SparseMmaElementAttr::S8,
-            nvvm::SparseMmaElementAttr::S8,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "s8",
-            "u8",
-            "",
-            nvvm::SparseMmaElementAttr::S8,
-            nvvm::SparseMmaElementAttr::U8,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "u8",
-            "u8",
-            "",
-            nvvm::SparseMmaElementAttr::U8,
-            nvvm::SparseMmaElementAttr::U8,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "u8",
-            "s8",
-            "",
-            nvvm::SparseMmaElementAttr::U8,
-            nvvm::SparseMmaElementAttr::S8,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "s8",
-            "s8",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::S8,
-            nvvm::SparseMmaElementAttr::S8,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            "s8",
-            "u8",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::S8,
-            nvvm::SparseMmaElementAttr::U8,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            "u8",
-            "u8",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::U8,
-            nvvm::SparseMmaElementAttr::U8,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            "u8",
-            "s8",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::U8,
-            nvvm::SparseMmaElementAttr::S8,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-    ];
-    let metadata_modes = [
-        ("sp", nvvm::SparseMmaMetadataAttr::Standard),
-        ("sp::ordered_metadata", nvvm::SparseMmaMetadataAttr::Ordered),
-    ];
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        for (metadata_name, metadata) in &metadata_modes {
-            for (index, (a_name, b_name, overflow_name, a_element, b_element, overflow)) in
-                cases.iter().enumerate()
-            {
-                let mut ctx = make_test_ctx();
-                let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-                let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-                let argument_types = (0..4)
-                    .map(|_| i32_ty.into())
-                    .chain((0..5).map(|_| u32_ty.into()))
-                    .collect();
-                let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-
-                let selector_value = (index % 2) as u32;
-                let selector_op = Operation::new(
-                    &mut ctx,
-                    mir::MirConstantOp::get_concrete_op_info(),
-                    vec![u32_ty.into()],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                mir::MirConstantOp::new(selector_op).set_attr_value(
-                    &ctx,
-                    IntegerAttr::new(
-                        u32_ty,
-                        APInt::from_u32(selector_value, NonZeroUsize::new(32).unwrap()),
-                    ),
-                );
-                selector_op.insert_at_back(entry, &ctx);
-                let selector = selector_op.deref(&ctx).get_result(0);
-
-                let operands = (0..9)
-                    .map(|operand| entry.deref(&ctx).get_argument(operand))
-                    .chain(std::iter::once(selector))
-                    .collect();
-                let operation = Operation::new(
-                    &mut ctx,
-                    nvvm::SparseMmaOp::get_concrete_op_info(),
-                    vec![i32_ty.into(); 4],
-                    operands,
-                    vec![],
-                    0,
-                );
-                let mma = nvvm::SparseMmaOp::new(operation);
-                mma.set_attr_nvvm_sparse_mma_shape(&ctx, nvvm::SparseMmaShapeAttr::M16n8k32);
-                mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, nvvm::SparseMmaAccumulatorAttr::S32);
-                mma.set_attr_nvvm_sparse_mma_a_element(&ctx, a_element.clone());
-                mma.set_attr_nvvm_sparse_mma_b_element(&ctx, b_element.clone());
-                mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, nvvm::SparseMmaLayoutAttr::Row);
-                mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, nvvm::SparseMmaLayoutAttr::Col);
-                mma.set_attr_nvvm_sparse_mma_overflow(&ctx, overflow.clone());
-                mma.set_attr_nvvm_sparse_mma_metadata(&ctx, metadata.clone());
-                mma.set_attr_nvvm_sparse_mma_selector(
-                    &ctx,
-                    nvvm::SparseMmaSelectorAttr::ImmediateZeroOrOne,
-                );
-                operation.insert_at_back(entry, &ctx);
-                append_return(&mut ctx, entry);
-
-                mir_lower::lower_mir_to_llvm_with_options(
-                    &mut ctx,
-                    module_ptr,
-                    mir_lower::LoweringOptions {
-                        intrinsic_backend: backend,
-                        ..Default::default()
-                    },
-                )
-                .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-                let body = lowered_kernel_body(&ctx, module_ptr);
-                let lowered = body
-                    .iter()
-                    .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(*op, &ctx))
-                    .collect::<Vec<_>>();
-                assert_eq!(lowered.len(), 1, "{backend:?}");
-                let asm = &lowered[0];
-                let expected_template = format!(
-                    "mma.{metadata_name}.sync.aligned.m16n8k32.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {{$0, $1, $2, $3}}, {{$8, $9}}, {{$10, $11}}, {{$4, $5, $6, $7}}, $12, $13;"
-                );
-                assert_eq!(
-                    asm.get_attr_inline_asm_template(&ctx)
-                        .as_deref()
-                        .map(|value| String::from(value.clone())),
-                    Some(expected_template)
-                );
-                assert_eq!(
-                    asm.get_attr_inline_asm_constraints(&ctx)
-                        .as_deref()
-                        .map(|value| String::from(value.clone())),
-                    Some("=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n".to_string())
-                );
-                assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-                let asm_operation = asm.get_operation().deref(&ctx);
-                assert_eq!(asm_operation.get_num_operands(), 10);
-                assert_eq!(asm_operation.get_num_results(), 1);
-                let lowered_selector = asm_operation.get_operand(9);
-                let defining_op = lowered_selector
-                    .defining_op()
-                    .expect("sparse MMA selector remains an LLVM constant");
-                let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
-                    .expect("sparse MMA selector remains an LLVM integer constant");
-                let attribute = constant.get_value(&ctx);
-                let integer = attribute
-                    .downcast_ref::<IntegerAttr>()
-                    .expect("sparse MMA selector is an integer");
-                assert_eq!(integer.value().bw(), 32);
-                assert_eq!(integer.value().to_u64(), selector_value as u64);
-                assert_eq!(
-                    body.iter()
-                        .filter(|op| {
-                            Operation::get_op::<llvm::ExtractValueOp>(**op, &ctx).is_some()
-                        })
-                        .count(),
-                    4
-                );
-
-                let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-                let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-                    .expect("generated sparse MMA exports to LLVM IR");
-                assert!(ir.contains("asm sideeffect"), "{ir}");
-                assert!(ir.contains("{ convergent }"), "{ir}");
-            }
-        }
-    }
-
-    Ok(())
-}
-
-#[test]
-fn test_generated_sparse_mma_m16n8k64_lowers_to_exact_convergent_inline_ptx()
--> Result<(), anyhow::Error> {
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let cases = [
-        (
-            "s8",
-            "u8",
-            "",
-            nvvm::SparseMmaElementAttr::S8,
-            nvvm::SparseMmaElementAttr::U8,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "u8",
-            "s8",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::U8,
-            nvvm::SparseMmaElementAttr::S8,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-    ];
-    let metadata_cases = [
-        ("sp", nvvm::SparseMmaMetadataAttr::Standard),
-        ("sp::ordered_metadata", nvvm::SparseMmaMetadataAttr::Ordered),
-    ];
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        for (metadata_name, metadata) in &metadata_cases {
-            for (a_name, b_name, overflow_name, a_element, b_element, overflow) in &cases {
-                let mut ctx = make_test_ctx();
-                let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-                let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-                let argument_types = (0..4)
-                    .map(|_| i32_ty.into())
-                    .chain((0..9).map(|_| u32_ty.into()))
-                    .collect();
-                let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-
-                let selector_op = Operation::new(
-                    &mut ctx,
-                    mir::MirConstantOp::get_concrete_op_info(),
-                    vec![u32_ty.into()],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                mir::MirConstantOp::new(selector_op).set_attr_value(
-                    &ctx,
-                    IntegerAttr::new(u32_ty, APInt::from_u32(0, NonZeroUsize::new(32).unwrap())),
-                );
-                selector_op.insert_at_back(entry, &ctx);
-                let selector = selector_op.deref(&ctx).get_result(0);
-
-                let operands = (0..13)
-                    .map(|index| entry.deref(&ctx).get_argument(index))
-                    .chain(std::iter::once(selector))
-                    .collect();
-                let operation = Operation::new(
-                    &mut ctx,
-                    nvvm::SparseMmaOp::get_concrete_op_info(),
-                    vec![i32_ty.into(); 4],
-                    operands,
-                    vec![],
-                    0,
-                );
-                let mma = nvvm::SparseMmaOp::new(operation);
-                mma.set_attr_nvvm_sparse_mma_shape(&ctx, nvvm::SparseMmaShapeAttr::M16n8k64);
-                mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, nvvm::SparseMmaAccumulatorAttr::S32);
-                mma.set_attr_nvvm_sparse_mma_a_element(&ctx, a_element.clone());
-                mma.set_attr_nvvm_sparse_mma_b_element(&ctx, b_element.clone());
-                mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, nvvm::SparseMmaLayoutAttr::Row);
-                mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, nvvm::SparseMmaLayoutAttr::Col);
-                mma.set_attr_nvvm_sparse_mma_overflow(&ctx, overflow.clone());
-                mma.set_attr_nvvm_sparse_mma_metadata(&ctx, metadata.clone());
-                mma.set_attr_nvvm_sparse_mma_selector(
-                    &ctx,
-                    nvvm::SparseMmaSelectorAttr::ImmediateZero,
-                );
-                operation.insert_at_back(entry, &ctx);
-                append_return(&mut ctx, entry);
-
-                mir_lower::lower_mir_to_llvm_with_options(
-                    &mut ctx,
-                    module_ptr,
-                    mir_lower::LoweringOptions {
-                        intrinsic_backend: backend,
-                        ..Default::default()
-                    },
-                )
-                .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-                let body = lowered_kernel_body(&ctx, module_ptr);
-                let lowered = body
-                    .iter()
-                    .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(*op, &ctx))
-                    .collect::<Vec<_>>();
-                assert_eq!(lowered.len(), 1, "{backend:?}");
-                let asm = &lowered[0];
-                let expected_template = format!(
-                    "mma.{metadata_name}.sync.aligned.m16n8k64.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {{$0, $1, $2, $3}}, {{$8, $9, $10, $11}}, {{$12, $13, $14, $15}}, {{$4, $5, $6, $7}}, $16, $17;"
-                );
-                assert_eq!(
-                    asm.get_attr_inline_asm_template(&ctx)
-                        .as_deref()
-                        .map(|value| String::from(value.clone())),
-                    Some(expected_template)
-                );
-                assert_eq!(
-                    asm.get_attr_inline_asm_constraints(&ctx)
-                        .as_deref()
-                        .map(|value| String::from(value.clone())),
-                    Some("=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n".to_string())
-                );
-                assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-                let asm_operation = asm.get_operation().deref(&ctx);
-                assert_eq!(asm_operation.get_num_operands(), 14);
-                assert_eq!(asm_operation.get_num_results(), 1);
-                let lowered_selector = asm_operation.get_operand(13);
-                let defining_op = lowered_selector
-                    .defining_op()
-                    .expect("sparse MMA selector remains an LLVM constant");
-                let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
-                    .expect("sparse MMA selector remains an LLVM integer constant");
-                let attribute = constant.get_value(&ctx);
-                let integer = attribute
-                    .downcast_ref::<IntegerAttr>()
-                    .expect("sparse MMA selector is an integer");
-                assert_eq!(integer.value().bw(), 32);
-                assert_eq!(integer.value().to_u64(), 0);
-                assert_eq!(
-                    body.iter()
-                        .filter(|op| {
-                            Operation::get_op::<llvm::ExtractValueOp>(**op, &ctx).is_some()
-                        })
-                        .count(),
-                    4
-                );
-
-                let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-                let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-                    .expect("generated sparse MMA exports to LLVM IR");
-                assert!(ir.contains("asm sideeffect"), "{ir}");
-                assert!(ir.contains("{ convergent }"), "{ir}");
-            }
-        }
-    }
-
-    Ok(())
-}
-
-#[test]
-fn test_generated_sparse_mma_m16n8k64_int4_lowers_both_metadata_modes() -> Result<(), anyhow::Error>
-{
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let cases = [
-        (
-            "s4",
-            "s4",
-            "",
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "s4",
-            "u4",
-            "",
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "u4",
-            "u4",
-            "",
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "u4",
-            "s4",
-            "",
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "s4",
-            "s4",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            "s4",
-            "u4",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            "u4",
-            "u4",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            "u4",
-            "s4",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-    ];
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        for (metadata_name, metadata) in [
-            ("sp", nvvm::SparseMmaMetadataAttr::Standard),
-            ("sp::ordered_metadata", nvvm::SparseMmaMetadataAttr::Ordered),
-        ] {
-            for (index, (a_name, b_name, overflow_name, a_element, b_element, overflow)) in
-                cases.iter().enumerate()
-            {
-                let mut ctx = make_test_ctx();
-                let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-                let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-                let argument_types = (0..4)
-                    .map(|_| i32_ty.into())
-                    .chain((0..5).map(|_| u32_ty.into()))
-                    .collect();
-                let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-
-                let selector_value = (index % 2) as u32;
-                let selector_op = Operation::new(
-                    &mut ctx,
-                    mir::MirConstantOp::get_concrete_op_info(),
-                    vec![u32_ty.into()],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                mir::MirConstantOp::new(selector_op).set_attr_value(
-                    &ctx,
-                    IntegerAttr::new(
-                        u32_ty,
-                        APInt::from_u32(selector_value, NonZeroUsize::new(32).unwrap()),
-                    ),
-                );
-                selector_op.insert_at_back(entry, &ctx);
-                let selector = selector_op.deref(&ctx).get_result(0);
-
-                let operands = (0..9)
-                    .map(|operand| entry.deref(&ctx).get_argument(operand))
-                    .chain(std::iter::once(selector))
-                    .collect();
-                let operation = Operation::new(
-                    &mut ctx,
-                    nvvm::SparseMmaOp::get_concrete_op_info(),
-                    vec![i32_ty.into(); 4],
-                    operands,
-                    vec![],
-                    0,
-                );
-                let mma = nvvm::SparseMmaOp::new(operation);
-                mma.set_attr_nvvm_sparse_mma_shape(&ctx, nvvm::SparseMmaShapeAttr::M16n8k64);
-                mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, nvvm::SparseMmaAccumulatorAttr::S32);
-                mma.set_attr_nvvm_sparse_mma_a_element(&ctx, a_element.clone());
-                mma.set_attr_nvvm_sparse_mma_b_element(&ctx, b_element.clone());
-                mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, nvvm::SparseMmaLayoutAttr::Row);
-                mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, nvvm::SparseMmaLayoutAttr::Col);
-                mma.set_attr_nvvm_sparse_mma_overflow(&ctx, overflow.clone());
-                mma.set_attr_nvvm_sparse_mma_metadata(&ctx, metadata.clone());
-                mma.set_attr_nvvm_sparse_mma_selector(
-                    &ctx,
-                    nvvm::SparseMmaSelectorAttr::ImmediateZeroOrOne,
-                );
-                operation.insert_at_back(entry, &ctx);
-                append_return(&mut ctx, entry);
-
-                mir_lower::lower_mir_to_llvm_with_options(
-                    &mut ctx,
-                    module_ptr,
-                    mir_lower::LoweringOptions {
-                        intrinsic_backend: backend,
-                        ..Default::default()
-                    },
-                )
-                .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-                let body = lowered_kernel_body(&ctx, module_ptr);
-                let lowered = body
-                    .iter()
-                    .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(*op, &ctx))
-                    .collect::<Vec<_>>();
-                assert_eq!(lowered.len(), 1, "{backend:?}");
-                let asm = &lowered[0];
-                let expected_template = format!(
-                    "mma.{metadata_name}.sync.aligned.m16n8k64.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {{$0, $1, $2, $3}}, {{$8, $9}}, {{$10, $11}}, {{$4, $5, $6, $7}}, $12, $13;"
-                );
-                assert_eq!(
-                    asm.get_attr_inline_asm_template(&ctx)
-                        .as_deref()
-                        .map(|value| String::from(value.clone())),
-                    Some(expected_template)
-                );
-                assert_eq!(
-                    asm.get_attr_inline_asm_constraints(&ctx)
-                        .as_deref()
-                        .map(|value| String::from(value.clone())),
-                    Some("=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n".to_string())
-                );
-                assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-                let asm_operation = asm.get_operation().deref(&ctx);
-                assert_eq!(asm_operation.get_num_operands(), 10);
-                assert_eq!(asm_operation.get_num_results(), 1);
-                let lowered_selector = asm_operation.get_operand(9);
-                let defining_op = lowered_selector
-                    .defining_op()
-                    .expect("sparse MMA selector remains an LLVM constant");
-                let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
-                    .expect("sparse MMA selector remains an LLVM integer constant");
-                let attribute = constant.get_value(&ctx);
-                let integer = attribute
-                    .downcast_ref::<IntegerAttr>()
-                    .expect("sparse MMA selector is an integer");
-                assert_eq!(integer.value().to_u64(), selector_value as u64);
-
-                let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-                let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-                    .expect("generated sparse MMA exports to LLVM IR");
-                assert!(ir.contains("asm sideeffect"), "{ir}");
-                assert!(ir.contains("{ convergent }"), "{ir}");
-            }
-        }
-    }
-
-    Ok(())
-}
-
-#[test]
-fn test_generated_sparse_mma_m16n8k128_int4_lowers_both_metadata_modes() -> Result<(), anyhow::Error>
-{
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let cases = [
-        (
-            "s4",
-            "s4",
-            "",
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "s4",
-            "u4",
-            "",
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "u4",
-            "u4",
-            "",
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "u4",
-            "s4",
-            "",
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaOverflowAttr::Wrapping,
-        ),
-        (
-            "s4",
-            "s4",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            "s4",
-            "u4",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            "u4",
-            "u4",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-        (
-            "u4",
-            "s4",
-            ".satfinite",
-            nvvm::SparseMmaElementAttr::U4,
-            nvvm::SparseMmaElementAttr::S4,
-            nvvm::SparseMmaOverflowAttr::Satfinite,
-        ),
-    ];
-
-    for backend in [
-        mir_lower::IntrinsicBackend::LlvmNvptx,
-        mir_lower::IntrinsicBackend::LibNvvm,
-    ] {
-        for (metadata_name, metadata) in [
-            ("sp", nvvm::SparseMmaMetadataAttr::Standard),
-            ("sp::ordered_metadata", nvvm::SparseMmaMetadataAttr::Ordered),
-        ] {
-            for (a_name, b_name, overflow_name, a_element, b_element, overflow) in &cases {
-                let mut ctx = make_test_ctx();
-                let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
-                let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-                let argument_types = (0..4)
-                    .map(|_| i32_ty.into())
-                    .chain((0..9).map(|_| u32_ty.into()))
-                    .collect();
-                let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-
-                let selector_op = Operation::new(
-                    &mut ctx,
-                    mir::MirConstantOp::get_concrete_op_info(),
-                    vec![u32_ty.into()],
-                    vec![],
-                    vec![],
-                    0,
-                );
-                mir::MirConstantOp::new(selector_op).set_attr_value(
-                    &ctx,
-                    IntegerAttr::new(u32_ty, APInt::from_u32(0, NonZeroUsize::new(32).unwrap())),
-                );
-                selector_op.insert_at_back(entry, &ctx);
-                let selector = selector_op.deref(&ctx).get_result(0);
-
-                let operands = (0..13)
-                    .map(|operand| entry.deref(&ctx).get_argument(operand))
-                    .chain(std::iter::once(selector))
-                    .collect();
-                let operation = Operation::new(
-                    &mut ctx,
-                    nvvm::SparseMmaOp::get_concrete_op_info(),
-                    vec![i32_ty.into(); 4],
-                    operands,
-                    vec![],
-                    0,
-                );
-                let mma = nvvm::SparseMmaOp::new(operation);
-                mma.set_attr_nvvm_sparse_mma_shape(&ctx, nvvm::SparseMmaShapeAttr::M16n8k128);
-                mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, nvvm::SparseMmaAccumulatorAttr::S32);
-                mma.set_attr_nvvm_sparse_mma_a_element(&ctx, a_element.clone());
-                mma.set_attr_nvvm_sparse_mma_b_element(&ctx, b_element.clone());
-                mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, nvvm::SparseMmaLayoutAttr::Row);
-                mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, nvvm::SparseMmaLayoutAttr::Col);
-                mma.set_attr_nvvm_sparse_mma_overflow(&ctx, overflow.clone());
-                mma.set_attr_nvvm_sparse_mma_metadata(&ctx, metadata.clone());
-                mma.set_attr_nvvm_sparse_mma_selector(
-                    &ctx,
-                    nvvm::SparseMmaSelectorAttr::ImmediateZero,
-                );
-                operation.insert_at_back(entry, &ctx);
-                append_return(&mut ctx, entry);
-
-                mir_lower::lower_mir_to_llvm_with_options(
-                    &mut ctx,
-                    module_ptr,
-                    mir_lower::LoweringOptions {
-                        intrinsic_backend: backend,
-                        ..Default::default()
-                    },
-                )
-                .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-                let body = lowered_kernel_body(&ctx, module_ptr);
-                let lowered = body
-                    .iter()
-                    .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(*op, &ctx))
-                    .collect::<Vec<_>>();
-                assert_eq!(lowered.len(), 1, "{backend:?}");
-                let asm = &lowered[0];
-                let expected_template = format!(
-                    "mma.{metadata_name}.sync.aligned.m16n8k128.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {{$0, $1, $2, $3}}, {{$8, $9, $10, $11}}, {{$12, $13, $14, $15}}, {{$4, $5, $6, $7}}, $16, $17;"
-                );
-                assert_eq!(
-                    asm.get_attr_inline_asm_template(&ctx)
-                        .as_deref()
-                        .map(|value| String::from(value.clone())),
-                    Some(expected_template)
-                );
-                assert_eq!(
-                    asm.get_attr_inline_asm_constraints(&ctx)
-                        .as_deref()
-                        .map(|value| String::from(value.clone())),
-                    Some("=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n".to_string())
-                );
-                assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-                let asm_operation = asm.get_operation().deref(&ctx);
-                assert_eq!(asm_operation.get_num_operands(), 14);
-                assert_eq!(asm_operation.get_num_results(), 1);
-                let lowered_selector = asm_operation.get_operand(13);
-                let defining_op = lowered_selector
-                    .defining_op()
-                    .expect("sparse MMA selector remains an LLVM constant");
-                let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
-                    .expect("sparse MMA selector remains an LLVM integer constant");
-                let attribute = constant.get_value(&ctx);
-                let integer = attribute
-                    .downcast_ref::<IntegerAttr>()
-                    .expect("sparse MMA selector is an integer");
-                assert_eq!(integer.value().to_u64(), 0);
-
-                let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
-                let ir = llvm_export::export::export_module_to_string(&ctx, &module)
-                    .expect("generated sparse MMA exports to LLVM IR");
-                assert!(ir.contains("asm sideeffect"), "{ir}");
-                assert!(ir.contains("{ convergent }"), "{ir}");
-            }
-        }
-    }
-
-    Ok(())
-}
-
-// ---------------------------------------------------------------------------
-// mma.sync m16n8k16 bf16 intrinsic lowering test
-// ---------------------------------------------------------------------------
-
-#[test]
-fn test_mma_m16n8k16_f32_bf16_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let f32_ty = pliron::builtin::types::FP32Type::get(&ctx);
-    let i32_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        32,
-        pliron::builtin::types::Signedness::Signless,
-    );
-    let argument_types = (0..4)
-        .map(|_| f32_ty.into())
-        .chain((0..6).map(|_| i32_ty.into()))
-        .collect();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-    let operands = (0..10)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect();
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        operands,
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut found = 0;
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for module_op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
-            continue;
-        };
-        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let body = function.get_operation().deref(&ctx).get_region(0);
-        for block in body.deref(&ctx).iter(&ctx) {
-            for body_op in block.deref(&ctx).iter(&ctx) {
-                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                let constraints = asm
-                    .get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                if !template.as_deref().is_some_and(|t| {
-                    t.contains("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32")
-                }) {
-                    continue;
-                }
-                found += 1;
-                let template = template.expect("MMA inline asm must have a template");
-                assert_eq!(
-                    template,
-                    concat!(
-                        "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 ",
-                        "{$0, $1, $2, $3}, ",
-                        "{$8, $9, $10, $11}, ",
-                        "{$12, $13}, ",
-                        "{$4, $5, $6, $7};"
-                    )
-                );
-                for forbidden in [".reg", "ld.", "st.", "["] {
-                    assert!(
-                        !template.contains(forbidden),
-                        "register-only MMA must not contain {forbidden:?}: {template}"
-                    );
-                }
-                assert_eq!(
-                    constraints.as_deref(),
-                    Some("=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r")
-                );
-                assert_eq!(
-                    llvm::asm_kind_opt(&ctx, &asm),
-                    Some(llvm::AsmKind::Convergent)
-                );
-                assert_eq!(
-                    body_op.deref(&ctx).get_num_operands(),
-                    10,
-                    "expected C, A, and B scalar register operands"
-                );
-                assert_eq!(
-                    body_op.deref(&ctx).get_num_results(),
-                    1,
-                    "LLVM inline asm returns the four D registers as one struct"
-                );
-            }
-        }
-    }
-
-    assert_eq!(found, 1, "expected one mma.sync inline-asm operation");
-    Ok(())
-}
-
-fn build_wgmma_pointer_test_kernel(
-    ctx: &mut Context,
-    accumulator_count: usize,
-    trailing_arg_types: Vec<pliron::r#type::TypeHandle>,
-) -> (
-    pliron::context::Ptr<Operation>,
-    pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-    Vec<pliron::value::Value>,
-    pliron::value::Value,
-    pliron::value::Value,
-    Vec<pliron::value::Value>,
-) {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-    use pliron::r#type::TypeHandle;
-
-    let f32_ty = FP32Type::get(ctx);
-    let accumulator_ptr_ty: TypeHandle = MirPtrType::get_generic(ctx, f32_ty.into(), true).into();
-    let u64_ty: TypeHandle = IntegerType::get(ctx, 64, Signedness::Unsigned).into();
-
-    let trailing_count = trailing_arg_types.len();
-    let mut argument_types = vec![accumulator_ptr_ty; accumulator_count];
-    argument_types.push(u64_ty);
-    argument_types.push(u64_ty);
-    argument_types.extend(trailing_arg_types);
-
-    let (module_ptr, entry) = build_test_kernel(ctx, argument_types);
-
-    let accumulators = (0..accumulator_count)
-        .map(|index| entry.deref(ctx).get_argument(index))
-        .collect::<Vec<_>>();
-    let desc_a = entry.deref(ctx).get_argument(accumulator_count);
-    let desc_b = entry.deref(ctx).get_argument(accumulator_count + 1);
-    let trailing_arguments = (0..trailing_count)
-        .map(|index| entry.deref(ctx).get_argument(accumulator_count + 2 + index))
-        .collect::<Vec<_>>();
-
-    (
-        module_ptr,
-        entry,
-        accumulators,
-        desc_a,
-        desc_b,
-        trailing_arguments,
-    )
-}
-
-fn build_wgmma_canonical_pointer_test_kernel_with_rows(
-    ctx: &mut Context,
-    accumulator_rows: u64,
-    accumulator_count: usize,
-    descriptor_count: usize,
-) -> (
-    pliron::context::Ptr<Operation>,
-    pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-    Vec<pliron::value::Value>,
-    Vec<pliron::value::Value>,
-) {
-    use dialect_mir::types::{MirArrayType, MirPtrType};
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    let f32_ty = FP32Type::get(ctx);
-    let row_ty = MirArrayType::get(ctx, f32_ty.into(), 8);
-    let accumulator_ty = MirArrayType::get(ctx, row_ty.into(), accumulator_rows);
-    let accumulator_ptr_ty = MirPtrType::get_generic(ctx, accumulator_ty.into(), true);
-    let u64_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);
-
-    let accumulator_arg_ty: pliron::r#type::TypeHandle = accumulator_ptr_ty.into();
-    let u64_arg_ty: pliron::r#type::TypeHandle = u64_ty.into();
-    let mut argument_types = vec![accumulator_arg_ty; accumulator_count];
-    argument_types.extend(vec![u64_arg_ty; descriptor_count]);
-    let (module_ptr, entry) = build_test_kernel(ctx, argument_types);
-
-    let accumulators = (0..accumulator_count)
-        .map(|index| entry.deref(ctx).get_argument(index))
-        .collect::<Vec<_>>();
-    let descriptors = (0..descriptor_count)
-        .map(|index| entry.deref(ctx).get_argument(accumulator_count + index))
-        .collect::<Vec<_>>();
-
-    (module_ptr, entry, accumulators, descriptors)
-}
-
-fn build_wgmma_canonical_pointer_test_kernel(
-    ctx: &mut Context,
-    accumulator_count: usize,
-    descriptor_count: usize,
-) -> (
-    pliron::context::Ptr<Operation>,
-    pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-    Vec<pliron::value::Value>,
-    Vec<pliron::value::Value>,
-) {
-    build_wgmma_canonical_pointer_test_kernel_with_rows(ctx, 4, accumulator_count, descriptor_count)
-}
-
-fn build_wgmma_m64n128_canonical_pointer_test_kernel(
-    ctx: &mut Context,
-    accumulator_count: usize,
-    descriptor_count: usize,
-) -> (
-    pliron::context::Ptr<Operation>,
-    pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-    Vec<pliron::value::Value>,
-    Vec<pliron::value::Value>,
-) {
-    build_wgmma_canonical_pointer_test_kernel_with_rows(ctx, 8, accumulator_count, descriptor_count)
-}
-
-fn append_pointer_wgmma_mma(
-    ctx: &mut Context,
-    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-    accumulator: pliron::value::Value,
-    desc_a: pliron::value::Value,
-    desc_b: pliron::value::Value,
-) {
-    Operation::new(
-        ctx,
-        nvvm::WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![],
-        vec![accumulator, desc_a, desc_b],
-        vec![],
-        0,
-    )
-    .insert_at_back(block, ctx);
-}
-
-fn append_pointer_wgmma_mma_m64n128(
-    ctx: &mut Context,
-    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-    accumulator: pliron::value::Value,
-    desc_a: pliron::value::Value,
-    desc_b: pliron::value::Value,
-) {
-    Operation::new(
-        ctx,
-        nvvm::WgmmaMmaM64N128K16F32Bf16Op::get_concrete_op_info(),
-        vec![],
-        vec![accumulator, desc_a, desc_b],
-        vec![],
-        0,
-    )
-    .insert_at_back(block, ctx);
-}
-
-fn append_pointer_wgmma_mma_f16(
-    ctx: &mut Context,
-    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-    accumulator: pliron::value::Value,
-    desc_a: pliron::value::Value,
-    desc_b: pliron::value::Value,
-) {
-    Operation::new(
-        ctx,
-        nvvm::WgmmaMmaM64N64K16F32F16Op::get_concrete_op_info(),
-        vec![],
-        vec![accumulator, desc_a, desc_b],
-        vec![],
-        0,
-    )
-    .insert_at_back(block, ctx);
-}
-
-fn append_pointer_wgmma_mma_tf32(
-    ctx: &mut Context,
-    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-    accumulator: pliron::value::Value,
-    desc_a: pliron::value::Value,
-    desc_b: pliron::value::Value,
-) {
-    Operation::new(
-        ctx,
-        nvvm::WgmmaMmaM64N64K8F32Tf32Op::get_concrete_op_info(),
-        vec![],
-        vec![accumulator, desc_a, desc_b],
-        vec![],
-        0,
-    )
-    .insert_at_back(block, ctx);
-}
-
-fn append_wgmma_wait_group_constant(
-    ctx: &mut Context,
-    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-    pending_groups: i64,
-) {
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::builtin::types::{IntegerType, Signedness};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let u64_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);
-    let constant_attr = IntegerAttr::new(
-        u64_ty,
-        APInt::from_i64(pending_groups, NonZeroUsize::new(64).unwrap()),
-    );
-    let constant = Operation::new(
-        ctx,
-        mir::MirConstantOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    mir::MirConstantOp::new(constant).set_attr_value(ctx, constant_attr);
-    constant.insert_at_back(block, ctx);
-
-    let value = constant.deref(ctx).get_result(0);
-    nvvm::WgmmaWaitGroupSyncAlignedOp::build(ctx, value).insert_at_back(block, ctx);
-}
-
-fn append_mir_unsigned_constant(
-    ctx: &mut Context,
-    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
-    ty: pliron::r#type::TypedHandle<pliron::builtin::types::IntegerType>,
-    value: u64,
-) -> pliron::value::Value {
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let width = usize::try_from(ty.deref(ctx).width()).expect("integer width must fit usize");
-    let constant = Operation::new(
-        ctx,
-        mir::MirConstantOp::get_concrete_op_info(),
-        vec![ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    mir::MirConstantOp::new(constant).set_attr_value(
-        ctx,
-        IntegerAttr::new(
-            ty,
-            APInt::from_u64(
-                value,
-                NonZeroUsize::new(width).expect("nonzero integer width"),
-            ),
-        ),
-    );
-    constant.insert_at_back(block, ctx);
-    constant.deref(ctx).get_result(0)
-}
-
-fn assert_wgmma_lowering_rejected(
-    ctx: &mut Context,
-    module_ptr: pliron::context::Ptr<Operation>,
-    expected_diagnostic: &str,
-) {
-    let error = mir_lower::lower_mir_to_llvm(ctx, module_ptr)
-        .expect_err("invalid deferred WGMMA sequence must fail closed")
-        .to_string();
-
-    assert!(
-        error.contains(expected_diagnostic),
-        "expected diagnostic containing `{expected_diagnostic}`, got:\n{error}"
-    );
-}
-
-// ---------------------------------------------------------------------------
-// mma.sync m16n8k16 f16 intrinsic lowering test
-// ---------------------------------------------------------------------------
-
-#[test]
-fn test_mma_m16n8k16_f32_f16_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let f32_ty = pliron::builtin::types::FP32Type::get(&ctx);
-    let i32_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        32,
-        pliron::builtin::types::Signedness::Signless,
-    );
-    let argument_types = (0..4)
-        .map(|_| f32_ty.into())
-        .chain((0..6).map(|_| i32_ty.into()))
-        .collect();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-    let operands = (0..10)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect();
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::MmaM16N8K16F32F16Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        operands,
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut found = 0;
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for module_op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
-            continue;
-        };
-        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let body = function.get_operation().deref(&ctx).get_region(0);
-        for block in body.deref(&ctx).iter(&ctx) {
-            for body_op in block.deref(&ctx).iter(&ctx) {
-                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                let constraints = asm
-                    .get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                if !template.as_deref().is_some_and(|t| {
-                    t.contains("mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32")
-                }) {
-                    continue;
-                }
-                found += 1;
-                let template = template.expect("MMA inline asm must have a template");
-                assert_eq!(
-                    template,
-                    concat!(
-                        "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 ",
-                        "{$0, $1, $2, $3}, ",
-                        "{$8, $9, $10, $11}, ",
-                        "{$12, $13}, ",
-                        "{$4, $5, $6, $7};"
-                    )
-                );
-                for forbidden in [".reg", "ld.", "st.", "["] {
-                    assert!(
-                        !template.contains(forbidden),
-                        "register-only MMA must not contain {forbidden:?}: {template}"
-                    );
-                }
-                assert_eq!(
-                    constraints.as_deref(),
-                    Some("=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r")
-                );
-                assert_eq!(
-                    llvm::asm_kind_opt(&ctx, &asm),
-                    Some(llvm::AsmKind::Convergent)
-                );
-                assert_eq!(
-                    body_op.deref(&ctx).get_num_operands(),
-                    10,
-                    "expected C, A, and B scalar register operands"
-                );
-                assert_eq!(
-                    body_op.deref(&ctx).get_num_results(),
-                    1,
-                    "LLVM inline asm returns the four D registers as one struct"
-                );
-            }
-        }
-    }
-
-    assert_eq!(found, 1, "expected one mma.sync inline-asm operation");
-    Ok(())
-}
-
-#[test]
-fn test_mma_m16n8k8_f32_tf32_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let f32_ty = pliron::builtin::types::FP32Type::get(&ctx);
-    let i32_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        32,
-        pliron::builtin::types::Signedness::Signless,
-    );
-    let argument_types = (0..4)
-        .map(|_| f32_ty.into())
-        .chain((0..6).map(|_| i32_ty.into()))
-        .collect();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-    let operands = (0..10)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect();
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
-        vec![f32_ty.into(); 4],
-        operands,
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut found = 0;
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for module_op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
-            continue;
-        };
-        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let body = function.get_operation().deref(&ctx).get_region(0);
-        for block in body.deref(&ctx).iter(&ctx) {
-            for body_op in block.deref(&ctx).iter(&ctx) {
-                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                let constraints = asm
-                    .get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                if !template.as_deref().is_some_and(|t| {
-                    t.contains("mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32")
-                }) {
-                    continue;
-                }
-                found += 1;
-                let template = template.expect("MMA inline asm must have a template");
-                assert_eq!(
-                    template,
-                    concat!(
-                        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 ",
-                        "{$0, $1, $2, $3}, ",
-                        "{$8, $9, $10, $11}, ",
-                        "{$12, $13}, ",
-                        "{$4, $5, $6, $7};"
-                    )
-                );
-                for forbidden in [".reg", "ld.", "st.", "["] {
-                    assert!(
-                        !template.contains(forbidden),
-                        "register-only MMA must not contain {forbidden:?}: {template}"
-                    );
-                }
-                assert_eq!(
-                    constraints.as_deref(),
-                    Some("=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r")
-                );
-                assert_eq!(
-                    llvm::asm_kind_opt(&ctx, &asm),
-                    Some(llvm::AsmKind::Convergent)
-                );
-                assert_eq!(
-                    body_op.deref(&ctx).get_num_operands(),
-                    10,
-                    "expected C, A, and B scalar register operands"
-                );
-                assert_eq!(
-                    body_op.deref(&ctx).get_num_results(),
-                    1,
-                    "LLVM inline asm returns the four D registers as one struct"
-                );
-            }
-        }
-    }
-
-    assert_eq!(found, 1, "expected one mma.sync inline-asm operation");
-    Ok(())
-}
-
-#[test]
-fn test_packed_atomic_add_lowers_to_exact_side_effecting_ptx() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into()]);
-    let address = entry.deref(&ctx).get_argument(0);
-    let addend = entry.deref(&ctx).get_argument(1);
-
-    for op_info in [
-        nvvm::NvvmAtomAddF16x2Op::get_concrete_op_info(),
-        nvvm::NvvmAtomAddBf16x2Op::get_concrete_op_info(),
-    ] {
-        Operation::new(
-            &mut ctx,
-            op_info,
-            vec![u32_ty.into()],
-            vec![address, addend],
-            vec![],
-            0,
-        )
-        .insert_at_back(entry, &ctx);
-    }
-    for format in [
-        nvvm::PackedAtomicFormatAttr::F16x2,
-        nvvm::PackedAtomicFormatAttr::Bf16x2,
-    ] {
-        nvvm::PackedAtomicAddOp::build(&mut ctx, address, addend, format)
-            .insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let expected = [
-        "atom.global.add.noftz.f16x2 $0, [$1], $2;",
-        "atom.global.add.noftz.bf16x2 $0, [$1], $2;",
-    ];
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    let mut lowered = Vec::new();
-
-    for op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(function) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let body = function.get_operation().deref(&ctx).get_region(0);
-        for block in body.deref(&ctx).iter(&ctx) {
-            for body_op in block.deref(&ctx).iter(&ctx) {
-                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .unwrap_or_default();
-                assert!(
-                    !template.contains("atom.cas"),
-                    "packed atomic exact-native lowering must not use a CAS loop: {template}"
-                );
-                if !template.starts_with("atom.global.add.noftz.") {
-                    continue;
-                }
-                lowered.push((
-                    template,
-                    asm.get_attr_inline_asm_constraints(&ctx)
-                        .map(|value| String::from((*value).clone()))
-                        .unwrap_or_default(),
-                    llvm::asm_kind(&ctx, &asm),
-                    body_op.deref(&ctx).get_num_operands(),
-                    body_op.deref(&ctx).get_num_results(),
-                ));
-            }
-        }
-    }
-
-    assert_eq!(lowered.len(), expected.len() * 2);
-    for instruction in expected {
-        let matches: Vec<_> = lowered
-            .iter()
-            .filter(|(template, _, _, _, _)| template == instruction)
-            .collect();
-        assert_eq!(
-            matches.len(),
-            2,
-            "legacy and generated paths must have exact PTX parity for {instruction}"
-        );
-        for (_, constraints, kind, operands, results) in matches {
-            assert_eq!(constraints, "=r,l,r,~{memory}");
-            assert_eq!(*kind, llvm::AsmKind::SideEffect);
-            assert_eq!(*operands, 2);
-            assert_eq!(*results, 1);
-        }
-    }
-
-    Ok(())
-}
-
-#[test]
-fn test_generated_packed_atomic_add_libnvvm_route_is_exact() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into()]);
-    let address = entry.deref(&ctx).get_argument(0);
-    let addend = entry.deref(&ctx).get_argument(1);
-    for format in [
-        nvvm::PackedAtomicFormatAttr::F16x2,
-        nvvm::PackedAtomicFormatAttr::Bf16x2,
-    ] {
-        nvvm::PackedAtomicAddOp::build(&mut ctx, address, addend, format)
-            .insert_at_back(entry, &ctx);
-    }
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm_with_options(
-        &mut ctx,
-        module_ptr,
-        mir_lower::LoweringOptions {
-            intrinsic_backend: mir_lower::IntrinsicBackend::LibNvvm,
-            ..Default::default()
-        },
-    )
-    .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let lowered = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|op| {
-            let asm = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx)?;
-            let template = asm
-                .get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))?;
-            template.starts_with("atom.global.add.noftz.").then(|| {
-                (
-                    template,
-                    asm.get_attr_inline_asm_constraints(&ctx)
-                        .map(|value| String::from((*value).clone())),
-                    llvm::asm_kind(&ctx, &asm),
-                )
-            })
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(lowered.len(), 2);
-    assert!(
-        lowered
-            .iter()
-            .any(|(template, _, _)| { template == "atom.global.add.noftz.f16x2 $0, [$1], $2;" })
-    );
-    assert!(
-        lowered
-            .iter()
-            .any(|(template, _, _)| { template == "atom.global.add.noftz.bf16x2 $0, [$1], $2;" })
-    );
-    for (_, constraints, kind) in lowered {
-        assert_eq!(constraints.as_deref(), Some("=r,l,r,~{memory}"));
-        assert_eq!(kind, llvm::AsmKind::SideEffect);
-    }
-    Ok(())
-}
-
-#[test]
-fn test_mma_m8n8k4_f64_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::FP64Type;
-
-    let mut ctx = make_test_ctx();
-    let f64_ty = FP64Type::get(&ctx);
-    let (module_ptr, entry) = build_test_kernel(
-        &mut ctx,
-        vec![f64_ty.into(), f64_ty.into(), f64_ty.into(), f64_ty.into()],
-    );
-    let operands = (0..4)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect();
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::MmaM8N8K4F64Op::get_concrete_op_info(),
-        vec![f64_ty.into(), f64_ty.into()],
-        operands,
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut found = 0;
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for module_op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
-            continue;
-        };
-        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let body = function.get_operation().deref(&ctx).get_region(0);
-        for block in body.deref(&ctx).iter(&ctx) {
-            for body_op in block.deref(&ctx).iter(&ctx) {
-                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                let constraints = asm
-                    .get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                if !template
-                    .as_deref()
-                    .is_some_and(|t| t.contains("mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64"))
-                {
-                    continue;
-                }
-                found += 1;
-                let template = template.unwrap();
-                assert_eq!(
-                    template,
-                    "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$4}, {$5}, {$2, $3};"
-                );
-                assert!(!template.contains(".reg"));
-                assert!(!template.contains("ld."));
-                assert!(!template.contains("st."));
-                assert_eq!(constraints.as_deref(), Some("=d,=d,d,d,d,d"));
-                assert_eq!(
-                    llvm::asm_kind_opt(&ctx, &asm),
-                    Some(llvm::AsmKind::Convergent)
-                );
-                assert_eq!(
-                    body_op.deref(&ctx).get_num_operands(),
-                    4,
-                    "expected four register inputs (c0, c1, a, b)"
-                );
-                assert_eq!(
-                    body_op.deref(&ctx).get_num_results(),
-                    1,
-                    "LLVM inline asm returns one aggregate containing d0 and d1"
-                );
-            }
-        }
-    }
-
-    assert_eq!(found, 1, "expected one mma.sync inline-asm operation");
-    Ok(())
-}
-
-#[test]
-fn test_mma_m16n8k32_s32_s8_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let i32_ty = pliron::builtin::types::IntegerType::get(
-        &ctx,
-        32,
-        pliron::builtin::types::Signedness::Signless,
-    );
-    let argument_types = (0..10).map(|_| i32_ty.into()).collect();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-    let operands = (0..10)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect();
-
-    let op = Operation::new(
-        &mut ctx,
-        nvvm::MmaM16N8K32S32S8Op::get_concrete_op_info(),
-        vec![i32_ty.into(); 4],
-        operands,
-        vec![],
-        0,
-    );
-    op.insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut found = 0;
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for module_op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
-            continue;
-        };
-        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let body = function.get_operation().deref(&ctx).get_region(0);
-        for block in body.deref(&ctx).iter(&ctx) {
-            for body_op in block.deref(&ctx).iter(&ctx) {
-                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                let constraints = asm
-                    .get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()));
-                if !template
-                    .as_deref()
-                    .is_some_and(|t| t.contains("mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32"))
-                {
-                    continue;
-                }
-                found += 1;
-                let template = template.expect("MMA inline asm must have a template");
-                assert_eq!(
-                    template,
-                    concat!(
-                        "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 ",
-                        "{$0, $1, $2, $3}, ",
-                        "{$8, $9, $10, $11}, ",
-                        "{$12, $13}, ",
-                        "{$4, $5, $6, $7};"
-                    )
-                );
-                for forbidden in [".reg", "ld.", "st.", "["] {
-                    assert!(
-                        !template.contains(forbidden),
-                        "register-only MMA must not contain {forbidden:?}: {template}"
-                    );
-                }
-                assert_eq!(
-                    constraints.as_deref(),
-                    Some("=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r")
-                );
-                assert_eq!(
-                    llvm::asm_kind_opt(&ctx, &asm),
-                    Some(llvm::AsmKind::Convergent)
-                );
-                assert_eq!(
-                    body_op.deref(&ctx).get_num_operands(),
-                    10,
-                    "expected C, A, and B scalar register operands"
-                );
-                assert_eq!(
-                    body_op.deref(&ctx).get_num_results(),
-                    1,
-                    "LLVM inline asm returns the four D registers as one struct"
-                );
-            }
-        }
-    }
-
-    assert_eq!(found, 1, "expected one mma.sync inline-asm operation");
-    Ok(())
-}
-
-#[test]
-fn test_deferred_wgmma_group_lowers_to_one_register_lifetime_scope() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, f32_ty.into(), true);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let (module_ptr, entry) = build_test_kernel(
-        &mut ctx,
-        vec![accumulator_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
-    );
-    let accumulator = entry.deref(&ctx).get_argument(0);
-    let desc_a = entry.deref(&ctx).get_argument(1);
-    let desc_b = entry.deref(&ctx).get_argument(2);
-
-    nvvm::WgmmaMmaGroupM64N64K16F32Bf16Op::build(&mut ctx, accumulator, vec![desc_a, desc_b])
-        .insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let matching = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
-        .filter(|asm| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| {
-                    template.contains("wgmma.mma_async.sync.aligned.m64n64k16.f32.bf16.bf16")
-                })
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(matching.len(), 1);
-
-    let asm = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("WGMMA template");
-    assert_eq!(template.matches("ld.f32 %acc").count(), 32);
-    assert_eq!(template.matches("st.f32 [$0").count(), 32);
-    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
-    let wait = template.find("wgmma.wait_group.sync.aligned 0").unwrap();
-    let first_store = template.find("st.f32 [$0").unwrap();
-    assert!(
-        wait < first_store,
-        "accumulator stores must follow wait_group<0>"
-    );
-    assert_eq!(
-        asm.get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .as_deref(),
-        Some("l,l,l,~{memory}")
-    );
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-    Ok(())
-}
-
-#[test]
-fn test_value_form_wgmma_group_lowers_to_tied_register_inline_ptx() -> Result<(), anyhow::Error> {
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-    use pliron::r#type::Typed;
-
-    const ACCUMULATOR_LEN: usize = 32;
-    const DESCRIPTOR_COUNT: usize = 4;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-
-    let argument_types = (0..ACCUMULATOR_LEN)
-        .map(|_| f32_ty.into())
-        .chain((0..DESCRIPTOR_COUNT).map(|_| u64_ty.into()))
-        .collect::<Vec<pliron::r#type::TypeHandle>>();
-
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-
-    let accumulators = (0..ACCUMULATOR_LEN)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect::<Vec<_>>();
-    let descriptors = (0..DESCRIPTOR_COUNT)
-        .map(|index| entry.deref(&ctx).get_argument(ACCUMULATOR_LEN + index))
-        .collect::<Vec<_>>();
-
-    nvvm::WgmmaMmaGroupValuesM64N64K16F32Bf16Op::build(&mut ctx, accumulators, descriptors)
-        .insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let matching = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
-        .filter(|asm| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| {
-                    template.contains("wgmma.mma_async.sync.aligned.m64n64k16.f32.bf16.bf16")
-                })
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(matching.len(), 1);
-
-    let asm = &matching[0];
-    let asm_op = asm.get_operation();
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("value-form WGMMA template");
-
-    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
-    assert_eq!(template.matches("wgmma.mma_async").count(), 2);
-    assert_eq!(
-        template.matches("wgmma.commit_group.sync.aligned").count(),
-        1
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 0").count(),
-        1
-    );
-    for forbidden in [".reg .f32", "ld.f32", "st.f32"] {
-        assert!(
-            !template.contains(forbidden),
-            "value-form WGMMA must not materialize accumulator memory via {forbidden:?}: {template}"
-        );
-    }
-
-    let accumulator_operands = (0..ACCUMULATOR_LEN)
-        .map(|index| format!("${index}"))
-        .collect::<Vec<_>>()
-        .join(", ");
-    assert!(
-        template.contains(&format!("{{{accumulator_operands}}}")),
-        "WGMMA must consume the 32 output operands as one accumulator tuple: {template}"
-    );
-    assert!(template.contains("$64, $65"), "{template}");
-    assert!(template.contains("$66, $67"), "{template}");
-
-    let mut expected_constraints = vec!["=f".to_owned(); ACCUMULATOR_LEN];
-    expected_constraints.extend((0..ACCUMULATOR_LEN).map(|index| index.to_string()));
-    expected_constraints.extend((0..DESCRIPTOR_COUNT).map(|_| "l".to_owned()));
-    expected_constraints.push("~{memory}".to_owned());
-    let expected_constraints = expected_constraints.join(",");
-
-    assert_eq!(
-        asm.get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .as_deref(),
-        Some(expected_constraints.as_str())
-    );
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-
-    let asm_ref = asm_op.deref(&ctx);
-    assert_eq!(
-        asm_ref.get_num_operands(),
-        ACCUMULATOR_LEN + DESCRIPTOR_COUNT
-    );
-    assert_eq!(
-        asm_ref.get_num_results(),
-        1,
-        "LLVM inline asm must return the 32 WGMMA accumulator values as one struct"
-    );
-
-    let aggregate = asm_ref.get_result(0);
-    let aggregate_ty = aggregate.get_type(&ctx);
-    let aggregate_ty = aggregate_ty.deref(&ctx);
-    let struct_ty = aggregate_ty
-        .downcast_ref::<llvm_types::StructType>()
-        .expect("value-form WGMMA inline asm must return an LLVM struct");
-    assert_eq!(struct_ty.num_fields(), ACCUMULATOR_LEN);
-    for index in 0..ACCUMULATOR_LEN {
-        assert!(
-            struct_ty
-                .field_type(index)
-                .deref(&ctx)
-                .downcast_ref::<FP32Type>()
-                .is_some(),
-            "WGMMA result field {index} must remain f32"
-        );
-    }
-
-    let extract_indices = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::ExtractValueOp>(operation, &ctx))
-        .filter_map(|extract| {
-            let extract_op = extract.get_operation().deref(&ctx);
-            (extract_op.get_operand(0) == aggregate).then(|| extract.indices(&ctx))
-        })
-        .collect::<Vec<_>>();
-
-    let expected_indices = (0..ACCUMULATOR_LEN)
-        .map(|index| vec![index as u32])
-        .collect::<Vec<_>>();
-    assert_eq!(
-        extract_indices, expected_indices,
-        "all 32 value-form WGMMA results must be extracted in constraint order"
-    );
-
-    Ok(())
-}
-
-#[test]
-fn test_value_form_m64n128_bf16_wgmma_group_lowers_to_sixty_four_tied_registers()
--> Result<(), anyhow::Error> {
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-    use pliron::r#type::Typed;
-
-    const ACCUMULATOR_LEN: usize = 64;
-    const DESCRIPTOR_COUNT: usize = 4;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let argument_types = (0..ACCUMULATOR_LEN)
-        .map(|_| f32_ty.into())
-        .chain((0..DESCRIPTOR_COUNT).map(|_| u64_ty.into()))
-        .collect::<Vec<pliron::r#type::TypeHandle>>();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-
-    let accumulators = (0..ACCUMULATOR_LEN)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect::<Vec<_>>();
-    let descriptors = (0..DESCRIPTOR_COUNT)
-        .map(|index| entry.deref(&ctx).get_argument(ACCUMULATOR_LEN + index))
-        .collect::<Vec<_>>();
-
-    nvvm::WgmmaMmaGroupValuesM64N128K16F32Bf16Op::build(&mut ctx, accumulators, descriptors)
-        .insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let matching = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
-        .filter(|asm| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("m64n128k16.f32.bf16.bf16"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(matching.len(), 1);
-
-    let asm = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("m64n128 value-form WGMMA template");
-    assert_eq!(template.matches("wgmma.mma_async").count(), 2);
-    assert!(template.contains("m64n128k16.f32.bf16.bf16"));
-    assert!(template.contains("$128, $129"));
-    assert!(template.contains("$130, $131"));
-    assert!(!template.contains("ld.f32"));
-    assert!(!template.contains("st.f32"));
-
-    let constraints = asm
-        .get_attr_inline_asm_constraints(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("m64n128 value-form WGMMA constraints");
-    assert_eq!(
-        constraints
-            .split(',')
-            .filter(|value| *value == "=f")
-            .count(),
-        64
-    );
-    assert_eq!(
-        constraints.split(',').filter(|value| *value == "l").count(),
-        4
-    );
-    assert!(constraints.ends_with("~{memory}"));
-
-    let aggregate = asm.get_operation().deref(&ctx).get_result(0);
-    let aggregate_ty = aggregate.get_type(&ctx);
-    let aggregate_ty = aggregate_ty.deref(&ctx);
-    let struct_ty = aggregate_ty
-        .downcast_ref::<llvm_types::StructType>()
-        .expect("m64n128 inline asm must return an LLVM struct");
-    assert_eq!(struct_ty.num_fields(), ACCUMULATOR_LEN);
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-
-    Ok(())
-}
-
-#[test]
-fn test_value_form_f16_wgmma_group_lowers_to_tied_register_inline_ptx() -> Result<(), anyhow::Error>
-{
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    const ACCUMULATOR_LEN: usize = 32;
-    const DESCRIPTOR_COUNT: usize = 2;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let argument_types = (0..ACCUMULATOR_LEN)
-        .map(|_| f32_ty.into())
-        .chain((0..DESCRIPTOR_COUNT).map(|_| u64_ty.into()))
-        .collect::<Vec<pliron::r#type::TypeHandle>>();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-
-    let accumulators = (0..ACCUMULATOR_LEN)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect::<Vec<_>>();
-    let descriptors = (0..DESCRIPTOR_COUNT)
-        .map(|index| entry.deref(&ctx).get_argument(ACCUMULATOR_LEN + index))
-        .collect::<Vec<_>>();
-
-    nvvm::WgmmaMmaGroupValuesM64N64K16F32F16Op::build(&mut ctx, accumulators, descriptors)
-        .insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let matching = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
-        .filter(|asm| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("m64n64k16.f32.f16.f16"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(matching.len(), 1);
-
-    let asm = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("F16 value-form WGMMA template");
-    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
-    assert!(template.contains("m64n64k16.f32.f16.f16"));
-    assert!(!template.contains(".bf16.bf16"));
-    assert!(template.contains("wgmma.fence.sync.aligned"));
-    assert!(template.contains("wgmma.commit_group.sync.aligned"));
-    assert!(template.contains("wgmma.wait_group.sync.aligned 0"));
-    assert!(!template.contains("ld.f32"));
-    assert!(!template.contains("st.f32"));
-
-    let constraints = asm
-        .get_attr_inline_asm_constraints(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("F16 value-form WGMMA constraints");
-    assert_eq!(
-        constraints
-            .split(',')
-            .filter(|value| *value == "=f")
-            .count(),
-        32
-    );
-    assert_eq!(
-        constraints.split(',').filter(|value| *value == "l").count(),
-        2
-    );
-    assert!(constraints.ends_with("~{memory}"));
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-
-    Ok(())
-}
-
-#[test]
-fn test_value_form_tf32_wgmma_group_lowers_to_tied_register_inline_ptx() -> Result<(), anyhow::Error>
-{
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    const ACCUMULATOR_LEN: usize = 32;
-    const DESCRIPTOR_COUNT: usize = 2;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let argument_types = (0..ACCUMULATOR_LEN)
-        .map(|_| f32_ty.into())
-        .chain((0..DESCRIPTOR_COUNT).map(|_| u64_ty.into()))
-        .collect::<Vec<pliron::r#type::TypeHandle>>();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
-
-    let accumulators = (0..ACCUMULATOR_LEN)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect::<Vec<_>>();
-    let descriptors = (0..DESCRIPTOR_COUNT)
-        .map(|index| entry.deref(&ctx).get_argument(ACCUMULATOR_LEN + index))
-        .collect::<Vec<_>>();
-
-    nvvm::WgmmaMmaGroupValuesM64N64K8F32Tf32Op::build(&mut ctx, accumulators, descriptors)
-        .insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let matching = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
-        .filter(|asm| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("m64n64k8.f32.tf32.tf32"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(matching.len(), 1);
-
-    let asm = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("TF32 value-form WGMMA template");
-    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
-    assert!(template.contains("m64n64k8.f32.tf32.tf32"));
-    assert!(!template.contains(".bf16.bf16"));
-    assert!(!template.contains(".f16.f16"));
-    assert!(!template.contains("m64n64k16"));
-    assert!(template.contains("$64, $65, 1, 1, 1;"));
-    assert!(!template.contains("$64, $65, 1, 1, 1, 0, 0;"));
-    assert!(template.contains("wgmma.fence.sync.aligned"));
-    assert!(template.contains("wgmma.commit_group.sync.aligned"));
-    assert!(template.contains("wgmma.wait_group.sync.aligned 0"));
-    assert!(!template.contains("ld.f32"));
-    assert!(!template.contains("st.f32"));
-
-    let constraints = asm
-        .get_attr_inline_asm_constraints(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("TF32 value-form WGMMA constraints");
-    assert_eq!(
-        constraints
-            .split(',')
-            .filter(|value| *value == "=f")
-            .count(),
-        32
-    );
-    assert_eq!(
-        constraints.split(',').filter(|value| *value == "l").count(),
-        2
-    );
-    assert!(constraints.ends_with("~{memory}"));
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-
-    Ok(())
-}
-
-#[test]
-fn test_pointer_form_wgmma_sequence_preserves_deferred_fallback() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    // A direct *mut f32 is intentionally not the public [[f32; 8]; 4]
-    // accumulator shape. It must therefore retain the deferred pointer path.
-    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, f32_ty.into(), true);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let (module_ptr, entry) = build_test_kernel(
-        &mut ctx,
-        vec![accumulator_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
-    );
-    let accumulator = entry.deref(&ctx).get_argument(0);
-    let desc_a = entry.deref(&ctx).get_argument(1);
-    let desc_b = entry.deref(&ctx).get_argument(2);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    Operation::new(
-        &mut ctx,
-        nvvm::WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![],
-        vec![accumulator, desc_a, desc_b],
-        vec![],
-        0,
-    )
-    .insert_at_back(entry, &ctx);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-
-    let zero_attr = IntegerAttr::new(u64_ty, APInt::from_i64(0, NonZeroUsize::new(64).unwrap()));
-    let zero = Operation::new(
-        &mut ctx,
-        mir::MirConstantOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    mir::MirConstantOp::new(zero).set_attr_value(&ctx, zero_attr);
-    zero.insert_at_back(entry, &ctx);
-    let zero_value = zero.deref(&ctx).get_result(0);
-    nvvm::WgmmaWaitGroupSyncAlignedOp::build(&mut ctx, zero_value).insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let matching = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
-        .filter(|asm| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("wgmma.mma_async"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(matching.len(), 1);
-
-    let asm = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("WGMMA template");
-    assert_eq!(template.matches("ld.f32 %acc").count(), 32);
-    assert_eq!(template.matches("st.f32 [$0").count(), 32);
-    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
-    assert!(template.contains("wgmma.fence.sync.aligned"));
-    assert!(template.contains("wgmma.commit_group.sync.aligned"));
-    assert!(template.contains("wgmma.wait_group.sync.aligned 0"));
-    assert_eq!(
-        asm.get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .as_deref(),
-        Some("l,l,l,~{memory}")
-    );
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-
-    Ok(())
-}
-
-#[test]
-fn test_pointer_form_wgmma_region_canonicalizes_reborrow_identity() -> Result<(), anyhow::Error> {
-    use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
-    use dialect_mir::types::{MirArrayType, MirPointerKind, MirPtrType};
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
-    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
-    let erased_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
-    let unique_ptr_ty: pliron::r#type::TypeHandle = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        accumulator_ty.into(),
-        true,
-        MirPointerKind::UniqueRef,
-    )
-    .into();
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-
-    let (module_ptr, entry) = build_test_kernel(
-        &mut ctx,
-        vec![erased_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
-    );
-    let accumulator = entry.deref(&ctx).get_argument(0);
-    let desc_a = entry.deref(&ctx).get_argument(1);
-    let desc_b = entry.deref(&ctx).get_argument(2);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-
-    // The importer emits a fresh kind-only retype for each `Rvalue::Ref`.
-    // Both typed operands must canonicalize to the same storage identity, while
-    // the first typed operand remains available to the linear lowering plan.
-    let first_retype = Operation::new(
-        &mut ctx,
-        mir::MirCastOp::get_concrete_op_info(),
-        vec![unique_ptr_ty],
-        vec![accumulator],
-        vec![],
-        0,
-    );
-    mir::MirCastOp::new(first_retype).set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    mir::MirCastOp::new(first_retype)
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    first_retype.insert_at_back(entry, &ctx);
-    let first_reborrow = first_retype.deref(&ctx).get_result(0);
-
-    Operation::new(
-        &mut ctx,
-        nvvm::WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![],
-        vec![first_reborrow, desc_a, desc_b],
-        vec![],
-        0,
-    )
-    .insert_at_back(entry, &ctx);
-
-    let second_retype = Operation::new(
-        &mut ctx,
-        mir::MirCastOp::get_concrete_op_info(),
-        vec![unique_ptr_ty],
-        vec![accumulator],
-        vec![],
-        0,
-    );
-    mir::MirCastOp::new(second_retype).set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    mir::MirCastOp::new(second_retype)
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    second_retype.insert_at_back(entry, &ctx);
-    let second_reborrow = second_retype.deref(&ctx).get_result(0);
-    assert_ne!(
-        first_reborrow, second_reborrow,
-        "the regression requires two distinct reborrow SSA values"
-    );
-    let first_reborrow_ty = first_reborrow.get_type(&ctx);
-    assert_eq!(
-        first_reborrow_ty
-            .deref(&ctx)
-            .downcast_ref::<MirPtrType>()
-            .expect("first reborrow must remain a typed MIR pointer")
-            .pointer_kind(),
-        MirPointerKind::UniqueRef,
-        "the regression must provide a typed UniqueRef for the linear plan to retain"
-    );
-
-    Operation::new(
-        &mut ctx,
-        nvvm::WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
-        vec![],
-        vec![second_reborrow, desc_a, desc_b],
-        vec![],
-        0,
-    )
-    .insert_at_back(entry, &ctx);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-
-    let zero_attr = IntegerAttr::new(u64_ty, APInt::from_i64(0, NonZeroUsize::new(64).unwrap()));
-    let zero = Operation::new(
-        &mut ctx,
-        mir::MirConstantOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    mir::MirConstantOp::new(zero).set_attr_value(&ctx, zero_attr);
-    zero.insert_at_back(entry, &ctx);
-    let zero_value = zero.deref(&ctx).get_result(0);
-    nvvm::WgmmaWaitGroupSyncAlignedOp::build(&mut ctx, zero_value).insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let matching = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
-        .filter(|asm| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| {
-                    template.contains("wgmma.mma_async.sync.aligned.m64n64k16.f32.bf16.bf16")
-                })
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        matching.len(),
-        1,
-        "distinct reborrow SSA values for one accumulator must not break deferred fusion"
-    );
-    let template = matching[0]
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("WGMMA template");
-    assert_eq!(
-        template.matches("wgmma.mma_async").count(),
-        2,
-        "both reborrows must remain in one fused accumulator region"
-    );
-    Ok(())
-}
-
-#[test]
-fn test_pointer_form_wgmma_sequence_uses_value_adapter_before_lowering() -> Result<(), anyhow::Error>
-{
-    use dialect_mir::types::{MirArrayType, MirPtrType};
-    use pliron::builtin::attributes::IntegerAttr;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-    use pliron::utils::apint::APInt;
-    use std::num::NonZeroUsize;
-
-    const ACCUMULATOR_LEN: usize = 32;
-    const DESCRIPTOR_COUNT: usize = 4;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
-    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
-    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-
-    let (module_ptr, entry) = build_test_kernel(
-        &mut ctx,
-        vec![
-            accumulator_ptr_ty.into(),
-            u64_ty.into(),
-            u64_ty.into(),
-            u64_ty.into(),
-            u64_ty.into(),
-        ],
-    );
-    let accumulator = entry.deref(&ctx).get_argument(0);
-    let descriptors = (1..=DESCRIPTOR_COUNT)
-        .map(|index| entry.deref(&ctx).get_argument(index))
-        .collect::<Vec<_>>();
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    for pair in descriptors.chunks_exact(2) {
-        Operation::new(
-            &mut ctx,
-            nvvm::WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
-            vec![],
-            vec![accumulator, pair[0], pair[1]],
-            vec![],
-            0,
-        )
-        .insert_at_back(entry, &ctx);
-    }
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-
-    let zero_attr = IntegerAttr::new(u64_ty, APInt::from_i64(0, NonZeroUsize::new(64).unwrap()));
-    let zero = Operation::new(
-        &mut ctx,
-        mir::MirConstantOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![],
-        vec![],
-        0,
-    );
-    mir::MirConstantOp::new(zero).set_attr_value(&ctx, zero_attr);
-    zero.insert_at_back(entry, &ctx);
-    let zero_value = zero.deref(&ctx).get_result(0);
-    nvvm::WgmmaWaitGroupSyncAlignedOp::build(&mut ctx, zero_value).insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let matching = body
-        .iter()
-        .copied()
-        .filter_map(|operation| {
-            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
-                .map(|inline_asm| (operation, inline_asm))
-        })
-        .filter(|(_, asm)| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("wgmma.mma_async"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(matching.len(), 1);
-
-    let (asm_operation, asm) = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("WGMMA template");
-
-    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
-    assert_eq!(template.matches("wgmma.mma_async").count(), 2);
-    assert_eq!(
-        template.matches("wgmma.commit_group.sync.aligned").count(),
-        1
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 0").count(),
-        1
-    );
-    assert!(
-        !template.contains(".reg .f32")
-            && !template.contains("ld.f32")
-            && !template.contains("st.f32"),
-        "value-form WGMMA must not materialize accumulator memory inside asm: {template}"
-    );
-
-    let mut expected_constraints = vec!["=f".to_owned(); ACCUMULATOR_LEN];
-    expected_constraints.extend((0..ACCUMULATOR_LEN).map(|index| index.to_string()));
-    expected_constraints.extend((0..DESCRIPTOR_COUNT).map(|_| "l".to_owned()));
-    expected_constraints.push("~{memory}".to_owned());
-    let expected_constraints = expected_constraints.join(",");
-
-    assert_eq!(
-        asm.get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .as_deref(),
-        Some(expected_constraints.as_str())
-    );
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-
-    let asm_ref = asm_operation.deref(&ctx);
-    assert_eq!(
-        asm_ref.get_num_operands(),
-        ACCUMULATOR_LEN + DESCRIPTOR_COUNT
-    );
-    assert_eq!(asm_ref.get_num_results(), 1);
-
-    let asm_position = body
-        .iter()
-        .position(|operation| operation == asm_operation)
-        .expect("WGMMA asm must be in the lowered kernel body");
-
-    let load_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        load_positions.len(),
-        ACCUMULATOR_LEN,
-        "the linear adapter must load each accumulator value exactly once"
-    );
-    assert!(
-        load_positions.iter().all(|index| *index < asm_position),
-        "all accumulator loads must happen before the WGMMA region"
-    );
-
-    let store_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        store_positions.len(),
-        ACCUMULATOR_LEN,
-        "the linear adapter must store each accumulator value exactly once"
-    );
-    assert!(
-        store_positions.iter().all(|index| *index > asm_position),
-        "all accumulator stores must happen after the final wait"
-    );
-
-    assert_eq!(
-        body.iter()
-            .filter(
-                |operation| Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
-            )
-            .count(),
-        ACCUMULATOR_LEN,
-        "all WGMMA accumulator results must be recovered as scalar SSA values"
-    );
-
-    Ok(())
-}
-
-#[test]
-fn test_pointer_form_m64n128_bf16_linear_full_drain_uses_sixty_four_value_adapter()
--> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, descriptors) =
-        build_wgmma_m64n128_canonical_pointer_test_kernel(&mut ctx, 1, 4);
-    let accumulator = accumulators[0];
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma_m64n128(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
-    append_pointer_wgmma_mma_m64n128(&mut ctx, entry, accumulator, descriptors[2], descriptors[3]);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let matching = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
-        .filter(|asm| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("m64n128k16.f32.bf16.bf16"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(matching.len(), 1);
-
-    let asm = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("m64n128 pointer-form WGMMA template");
-    assert_eq!(template.matches("wgmma.mma_async").count(), 2);
-    assert!(template.contains("m64n128k16.f32.bf16.bf16"));
-    assert!(!template.contains("ld.f32"));
-    assert!(!template.contains("st.f32"));
-
-    let constraints = asm
-        .get_attr_inline_asm_constraints(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("m64n128 pointer-form WGMMA constraints");
-    assert_eq!(
-        constraints
-            .split(',')
-            .filter(|value| *value == "=f")
-            .count(),
-        64
-    );
-    assert_eq!(
-        constraints.split(',').filter(|value| *value == "l").count(),
-        4
-    );
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-
-    Ok(())
-}
-
-#[test]
-fn test_pointer_form_f16_wgmma_linear_full_drain_uses_value_adapter() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, descriptors) =
-        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 2);
-    let accumulator = accumulators[0];
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma_f16(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let matching = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
-        .filter(|asm| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("m64n64k16.f32.f16.f16"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(matching.len(), 1);
-
-    let asm = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("F16 pointer-form WGMMA template");
-    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
-    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
-    assert_eq!(
-        template.matches("wgmma.commit_group.sync.aligned").count(),
-        1
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 0").count(),
-        1
-    );
-    assert!(template.contains("m64n64k16.f32.f16.f16"));
-    assert!(!template.contains(".bf16.bf16"));
-    assert!(!template.contains("ld.f32"));
-    assert!(!template.contains("st.f32"));
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-
-    Ok(())
-}
-
-#[test]
-fn test_pointer_form_tf32_wgmma_linear_full_drain_uses_value_adapter() -> Result<(), anyhow::Error>
-{
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, descriptors) =
-        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 2);
-    let accumulator = accumulators[0];
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma_tf32(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let matching = lowered_kernel_body(&ctx, module_ptr)
-        .into_iter()
-        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
-        .filter(|asm| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("m64n64k8.f32.tf32.tf32"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(matching.len(), 1);
-
-    let asm = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("TF32 pointer-form WGMMA template");
-    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
-    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
-    assert_eq!(
-        template.matches("wgmma.commit_group.sync.aligned").count(),
-        1
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 0").count(),
-        1
-    );
-    assert!(template.contains("m64n64k8.f32.tf32.tf32"));
-    assert!(!template.contains(".bf16.bf16"));
-    assert!(!template.contains(".f16.f16"));
-    assert!(!template.contains("m64n64k16"));
-    assert!(template.contains("$64, $65, 1, 1, 1;"));
-    assert!(!template.contains("$64, $65, 1, 1, 1, 0, 0;"));
-    assert!(!template.contains("ld.f32"));
-    assert!(!template.contains("st.f32"));
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-
-    Ok(())
-}
-
-#[test]
-fn test_pointer_form_wgmma_partial_wait_pipeline_keeps_multiple_groups_in_flight()
--> Result<(), anyhow::Error> {
-    const SLOT_COUNT: usize = 2;
-    const ACCUMULATOR_LEN: usize = 32;
-    const GROUP_COUNT: usize = 4;
-    const DESCRIPTOR_COUNT: usize = GROUP_COUNT * 2;
-    const MAX_PENDING_GROUPS: i64 = 1;
-    const RESULT_COUNT: usize = SLOT_COUNT * ACCUMULATOR_LEN;
-
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, descriptors) =
-        build_wgmma_canonical_pointer_test_kernel(&mut ctx, SLOT_COUNT, DESCRIPTOR_COUNT);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    for group in 0..GROUP_COUNT {
-        append_pointer_wgmma_mma(
-            &mut ctx,
-            entry,
-            accumulators[group % SLOT_COUNT],
-            descriptors[group * 2],
-            descriptors[group * 2 + 1],
-        );
-        nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-        if group + 1 >= SLOT_COUNT {
-            append_wgmma_wait_group_constant(&mut ctx, entry, MAX_PENDING_GROUPS);
-        }
-    }
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let matching = body
-        .iter()
-        .copied()
-        .filter_map(|operation| {
-            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
-                .map(|inline_asm| (operation, inline_asm))
-        })
-        .filter(|(_, asm)| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| {
-                    template.contains("wgmma.mma_async")
-                        && template.contains("wgmma.wait_group.sync.aligned 1")
-                })
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        matching.len(),
-        1,
-        "expected one fused partial-wait WGMMA pipeline"
-    );
-
-    let (asm_operation, asm) = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("pipeline WGMMA template");
-
-    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
-    assert_eq!(template.matches("wgmma.mma_async").count(), GROUP_COUNT);
-    assert_eq!(
-        template.matches("wgmma.commit_group.sync.aligned").count(),
-        GROUP_COUNT
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 1").count(),
-        GROUP_COUNT - SLOT_COUNT + 1
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 0").count(),
-        1
-    );
-    assert!(
-        template.contains("{$0, $1"),
-        "slot 0 must use the first accumulator tuple"
-    );
-    assert!(
-        template.contains("{$32, $33"),
-        "slot 1 must use the second accumulator tuple"
-    );
-    assert!(template.contains("$128, $129"));
-    assert!(template.contains("$134, $135"));
-    assert!(
-        !template.contains(".reg .f32")
-            && !template.contains("ld.f32")
-            && !template.contains("st.f32"),
-        "pipeline WGMMA must not materialize accumulator memory inside asm: {template}"
-    );
-
-    let mut expected_constraints = vec!["=f".to_owned(); RESULT_COUNT];
-    expected_constraints.extend((0..RESULT_COUNT).map(|index| index.to_string()));
-    expected_constraints.extend((0..DESCRIPTOR_COUNT).map(|_| "l".to_owned()));
-    expected_constraints.push("~{memory}".to_owned());
-    let expected_constraints = expected_constraints.join(",");
-    assert_eq!(
-        asm.get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .as_deref(),
-        Some(expected_constraints.as_str())
-    );
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-    assert_eq!(
-        asm_operation.deref(&ctx).get_num_operands(),
-        RESULT_COUNT + DESCRIPTOR_COUNT
-    );
-    assert_eq!(asm_operation.deref(&ctx).get_num_results(), 1);
-
-    let asm_position = body
-        .iter()
-        .position(|operation| operation == asm_operation)
-        .expect("pipeline asm must be in the lowered kernel body");
-    let load_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(load_positions.len(), RESULT_COUNT);
-    assert!(load_positions.iter().all(|index| *index < asm_position));
-
-    let store_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(store_positions.len(), RESULT_COUNT);
-    assert!(store_positions.iter().all(|index| *index > asm_position));
-    assert_eq!(
-        body.iter()
-            .filter(|operation| {
-                Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
-            })
-            .count(),
-        RESULT_COUNT
-    );
-
-    Ok(())
-}
-
-fn build_pointer_form_wgmma_counted_pipeline_case(
-    ctx: &mut Context,
-    slot_count: usize,
-    wait_depths: &[i64],
-    repeat_last_accumulator: bool,
-) -> pliron::context::Ptr<Operation> {
-    use dialect_mir::types::{MirArrayType, MirPtrType};
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::op_interfaces::OperandSegmentInterface;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    assert_eq!(wait_depths.len(), slot_count);
-
-    let f32_ty = FP32Type::get(ctx);
-    let row_ty = MirArrayType::get(ctx, f32_ty.into(), 8);
-    let accumulator_ty = MirArrayType::get(ctx, row_ty.into(), 4);
-    let accumulator_ptr_ty = MirPtrType::get_generic(ctx, accumulator_ty.into(), true);
-    let u32_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
-    let u64_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);
-    let i1_ty = IntegerType::get(ctx, 1, Signedness::Signless);
-    let u64_type: pliron::r#type::TypeHandle = u64_ty.into();
-
-    let mut argument_types: Vec<pliron::r#type::TypeHandle> =
-        vec![accumulator_ptr_ty.into(); slot_count];
-    argument_types.extend(vec![u64_type; slot_count * 2]);
-    let (module_ptr, preheader) = build_test_kernel(ctx, argument_types);
-
-    let accumulators = (0..slot_count)
-        .map(|slot| preheader.deref(ctx).get_argument(slot))
-        .collect::<Vec<_>>();
-    let desc_bases = (0..slot_count * 2)
-        .map(|index| preheader.deref(ctx).get_argument(slot_count + index))
-        .collect::<Vec<_>>();
-
-    let module_region = module_ptr.deref(ctx).get_region(0);
-    let module_block = module_region.deref(ctx).iter(ctx).next().unwrap();
-    let function = module_block.deref(ctx).iter(ctx).next().unwrap();
-    let function_region = function.deref(ctx).get_region(0);
-
-    let mut header_types: Vec<pliron::r#type::TypeHandle> = vec![u32_ty.into()];
-    header_types.extend(vec![u64_type; slot_count * 2]);
-    let header = BasicBlock::new(ctx, None, header_types);
-    header.insert_at_back(function_region, ctx);
-    let latch = BasicBlock::new(ctx, None, vec![]);
-    latch.insert_at_back(function_region, ctx);
-    let exit = BasicBlock::new(ctx, None, vec![]);
-    exit.insert_at_back(function_region, ctx);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(ctx).insert_at_back(preheader, ctx);
-    let i0 = append_mir_unsigned_constant(ctx, preheader, u32_ty, 0);
-    let mut initial_values = vec![i0];
-    initial_values.extend(desc_bases.iter().copied());
-    Operation::new(
-        ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        initial_values,
-        vec![header],
-        0,
-    )
-    .insert_at_back(preheader, ctx);
-
-    let i = header.deref(ctx).get_argument(0);
-    let descriptors = (0..slot_count * 2)
-        .map(|index| header.deref(ctx).get_argument(1 + index))
-        .collect::<Vec<_>>();
-    let bound = append_mir_unsigned_constant(ctx, header, u32_ty, 4);
-    let lt = Operation::new(
-        ctx,
-        mir::MirLtOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![i, bound],
-        vec![],
-        0,
-    );
-    lt.insert_at_back(header, ctx);
-    let lt_value = lt.deref(ctx).get_result(0);
-    let not_lt = Operation::new(
-        ctx,
-        mir::MirNotOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![lt_value],
-        vec![],
-        0,
-    );
-    not_lt.insert_at_back(header, ctx);
-    let not_lt_value = not_lt.deref(ctx).get_result(0);
-    let (branch_operands, segment_sizes) =
-        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![not_lt_value], vec![], vec![]]);
-    let branch = Operation::new(
-        ctx,
-        mir::MirCondBranchOp::get_concrete_op_info(),
-        vec![],
-        branch_operands,
-        vec![exit, latch],
-        0,
-    );
-    Operation::get_op::<mir::MirCondBranchOp>(branch, ctx)
-        .expect("MirCondBranchOp")
-        .set_operand_segment_sizes(ctx, segment_sizes);
-    branch.insert_at_back(header, ctx);
-
-    for slot in 0..slot_count {
-        let accumulator = if repeat_last_accumulator && slot + 1 == slot_count {
-            accumulators[0]
-        } else {
-            accumulators[slot]
-        };
-        append_pointer_wgmma_mma(
-            ctx,
-            latch,
-            accumulator,
-            descriptors[slot * 2],
-            descriptors[slot * 2 + 1],
-        );
-        nvvm::WgmmaCommitGroupSyncAlignedOp::build(ctx).insert_at_back(latch, ctx);
-        append_wgmma_wait_group_constant(ctx, latch, wait_depths[slot]);
-    }
-
-    let one = append_mir_unsigned_constant(ctx, latch, u32_ty, 1);
-    let i_next = Operation::new(
-        ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![i, one],
-        vec![],
-        0,
-    );
-    i_next.insert_at_back(latch, ctx);
-    let i_next = i_next.deref(ctx).get_result(0);
-
-    let mut next_values = vec![i_next];
-    for (index, descriptor) in descriptors.iter().copied().enumerate() {
-        let step = append_mir_unsigned_constant(ctx, latch, u64_ty, 16 * (index as u64 + 1));
-        let next = Operation::new(
-            ctx,
-            mir::MirAddOp::get_concrete_op_info(),
-            vec![u64_ty.into()],
-            vec![descriptor, step],
-            vec![],
-            0,
-        );
-        next.insert_at_back(latch, ctx);
-        next_values.push(next.deref(ctx).get_result(0));
-    }
-
-    Operation::new(
-        ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        next_values,
-        vec![header],
-        0,
-    )
-    .insert_at_back(latch, ctx);
-
-    append_wgmma_wait_group_constant(ctx, exit, 0);
-    append_return(ctx, exit);
-
-    module_ptr
-}
-
-#[test]
-fn test_pointer_form_wgmma_two_slot_counted_pipeline_stays_register_resident()
--> Result<(), anyhow::Error> {
-    use dialect_mir::types::{MirArrayType, MirPtrType};
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::op_interfaces::OperandSegmentInterface;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    const SLOT_COUNT: usize = 2;
-    const ACCUMULATOR_LEN: usize = 32;
-    const RESULT_COUNT: usize = SLOT_COUNT * ACCUMULATOR_LEN;
-    const LOOP_CONTROL_COUNT: usize = 9;
-    const TRIP_COUNT: u64 = 4;
-    const DESC_A0_STEP: u64 = 16;
-    const DESC_B0_STEP: u64 = 32;
-    const DESC_A1_STEP: u64 = 48;
-    const DESC_B1_STEP: u64 = 64;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
-    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
-    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-
-    let (module_ptr, preheader) = build_test_kernel(
-        &mut ctx,
-        vec![
-            accumulator_ptr_ty.into(),
-            accumulator_ptr_ty.into(),
-            u64_ty.into(),
-            u64_ty.into(),
-            u64_ty.into(),
-            u64_ty.into(),
-        ],
-    );
-    let accumulator0 = preheader.deref(&ctx).get_argument(0);
-    let accumulator1 = preheader.deref(&ctx).get_argument(1);
-    let desc_a0_base = preheader.deref(&ctx).get_argument(2);
-    let desc_b0_base = preheader.deref(&ctx).get_argument(3);
-    let desc_a1_base = preheader.deref(&ctx).get_argument(4);
-    let desc_b1_base = preheader.deref(&ctx).get_argument(5);
-
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
-    let function_region = function.deref(&ctx).get_region(0);
-
-    let header = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![
-            u32_ty.into(),
-            u64_ty.into(),
-            u64_ty.into(),
-            u64_ty.into(),
-            u64_ty.into(),
-        ],
-    );
-    header.insert_at_back(function_region, &ctx);
-    let latch = BasicBlock::new(&mut ctx, None, vec![]);
-    latch.insert_at_back(function_region, &ctx);
-    let exit = BasicBlock::new(&mut ctx, None, vec![]);
-    exit.insert_at_back(function_region, &ctx);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(preheader, &ctx);
-    let i0 = append_mir_unsigned_constant(&mut ctx, preheader, u32_ty, 0);
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![i0, desc_a0_base, desc_b0_base, desc_a1_base, desc_b1_base],
-        vec![header],
-        0,
-    )
-    .insert_at_back(preheader, &ctx);
-
-    let i = header.deref(&ctx).get_argument(0);
-    let desc_a0 = header.deref(&ctx).get_argument(1);
-    let desc_b0 = header.deref(&ctx).get_argument(2);
-    let desc_a1 = header.deref(&ctx).get_argument(3);
-    let desc_b1 = header.deref(&ctx).get_argument(4);
-    let bound = append_mir_unsigned_constant(&mut ctx, header, u32_ty, TRIP_COUNT);
-    let lt = Operation::new(
-        &mut ctx,
-        mir::MirLtOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![i, bound],
-        vec![],
-        0,
-    );
-    lt.insert_at_back(header, &ctx);
-    let lt_value = lt.deref(&ctx).get_result(0);
-    let not_lt = Operation::new(
-        &mut ctx,
-        mir::MirNotOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![lt_value],
-        vec![],
-        0,
-    );
-    not_lt.insert_at_back(header, &ctx);
-    let not_lt_value = not_lt.deref(&ctx).get_result(0);
-    let (branch_operands, segment_sizes) =
-        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![not_lt_value], vec![], vec![]]);
-    let branch = Operation::new(
-        &mut ctx,
-        mir::MirCondBranchOp::get_concrete_op_info(),
-        vec![],
-        branch_operands,
-        vec![exit, latch],
-        0,
-    );
-    Operation::get_op::<mir::MirCondBranchOp>(branch, &ctx)
-        .expect("MirCondBranchOp")
-        .set_operand_segment_sizes(&ctx, segment_sizes);
-    branch.insert_at_back(header, &ctx);
-
-    append_pointer_wgmma_mma(&mut ctx, latch, accumulator0, desc_a0, desc_b0);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(latch, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, latch, 1);
-    append_pointer_wgmma_mma(&mut ctx, latch, accumulator1, desc_a1, desc_b1);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(latch, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, latch, 1);
-
-    let one = append_mir_unsigned_constant(&mut ctx, latch, u32_ty, 1);
-    let i_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![i, one],
-        vec![],
-        0,
-    );
-    i_next.insert_at_back(latch, &ctx);
-    let i_next = i_next.deref(&ctx).get_result(0);
-
-    let desc_a0_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_A0_STEP);
-    let desc_a0_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![desc_a0, desc_a0_step],
-        vec![],
-        0,
-    );
-    desc_a0_next.insert_at_back(latch, &ctx);
-    let desc_a0_next = desc_a0_next.deref(&ctx).get_result(0);
-
-    let desc_b0_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_B0_STEP);
-    let desc_b0_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![desc_b0, desc_b0_step],
-        vec![],
-        0,
-    );
-    desc_b0_next.insert_at_back(latch, &ctx);
-    let desc_b0_next = desc_b0_next.deref(&ctx).get_result(0);
-
-    let desc_a1_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_A1_STEP);
-    let desc_a1_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![desc_a1, desc_a1_step],
-        vec![],
-        0,
-    );
-    desc_a1_next.insert_at_back(latch, &ctx);
-    let desc_a1_next = desc_a1_next.deref(&ctx).get_result(0);
-
-    let desc_b1_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_B1_STEP);
-    let desc_b1_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![desc_b1, desc_b1_step],
-        vec![],
-        0,
-    );
-    desc_b1_next.insert_at_back(latch, &ctx);
-    let desc_b1_next = desc_b1_next.deref(&ctx).get_result(0);
-
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![
-            i_next,
-            desc_a0_next,
-            desc_b0_next,
-            desc_a1_next,
-            desc_b1_next,
-        ],
-        vec![header],
-        0,
-    )
-    .insert_at_back(latch, &ctx);
-
-    append_wgmma_wait_group_constant(&mut ctx, exit, 0);
-    append_return(&mut ctx, exit);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let matching = body
-        .iter()
-        .copied()
-        .filter_map(|operation| {
-            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
-                .map(|inline_asm| (operation, inline_asm))
-        })
-        .filter(|(_, asm)| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("L__wgmma_pipeline_loop_${:uid}:"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        matching.len(),
-        1,
-        "expected one fused two-slot counted WGMMA pipeline"
-    );
-
-    let (asm_operation, asm) = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("counted-pipeline WGMMA template");
-
-    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
-    assert_eq!(template.matches("wgmma.mma_async").count(), 2);
-    assert_eq!(
-        template.matches("wgmma.commit_group.sync.aligned").count(),
-        2
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 1").count(),
-        2
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 0").count(),
-        1
-    );
-    assert!(template.contains("{$0, $1"));
-    assert!(template.contains("{$32, $33"));
-    assert!(template.contains("mov.u64 %desc_a0, $128;"));
-    assert!(template.contains("mov.u64 %desc_b0, $129;"));
-    assert!(template.contains("mov.u64 %desc_a1, $130;"));
-    assert!(template.contains("mov.u64 %desc_b1, $131;"));
-    assert!(template.contains("add.u64 %desc_a0, %desc_a0, $132;"));
-    assert!(template.contains("add.u64 %desc_b0, %desc_b0, $133;"));
-    assert!(template.contains("add.u64 %desc_a1, %desc_a1, $134;"));
-    assert!(template.contains("add.u64 %desc_b1, %desc_b1, $135;"));
-    assert!(template.contains("mov.u64 %remaining, $136;"));
-    assert!(
-        !template.contains(".reg .f32")
-            && !template.contains("ld.f32")
-            && !template.contains("st.f32"),
-        "counted pipeline must keep accumulator memory outside asm: {template}"
-    );
-
-    let mut expected_constraints = vec!["=f".to_owned(); RESULT_COUNT];
-    expected_constraints.extend((0..RESULT_COUNT).map(|index| index.to_string()));
-    expected_constraints.extend((0..LOOP_CONTROL_COUNT).map(|_| "l".to_owned()));
-    expected_constraints.push("~{memory}".to_owned());
-    let expected_constraints = expected_constraints.join(",");
-    assert_eq!(
-        asm.get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .as_deref(),
-        Some(expected_constraints.as_str())
-    );
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-    assert_eq!(
-        asm_operation.deref(&ctx).get_num_operands(),
-        RESULT_COUNT + LOOP_CONTROL_COUNT
-    );
-
-    let asm_position = body
-        .iter()
-        .position(|operation| operation == asm_operation)
-        .expect("counted-pipeline WGMMA asm must be in the lowered kernel body");
-    let load_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(load_positions.len(), RESULT_COUNT);
-    assert!(load_positions.iter().all(|index| *index < asm_position));
-
-    let store_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(store_positions.len(), RESULT_COUNT);
-    assert!(store_positions.iter().all(|index| *index > asm_position));
-    assert_eq!(
-        body.iter()
-            .filter(|operation| {
-                Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
-            })
-            .count(),
-        RESULT_COUNT
-    );
-
-    Ok(())
-}
-
-#[test]
-fn test_pointer_form_wgmma_three_slot_counted_pipeline_stays_register_resident()
--> Result<(), anyhow::Error> {
-    const RESULT_COUNT: usize = 96;
-    const LOOP_CONTROL_COUNT: usize = 13;
-
-    let mut ctx = make_test_ctx();
-    let module_ptr = build_pointer_form_wgmma_counted_pipeline_case(&mut ctx, 3, &[2, 2, 2], false);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let matching = body
-        .iter()
-        .copied()
-        .filter_map(|operation| {
-            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
-                .map(|inline_asm| (operation, inline_asm))
-        })
-        .filter(|(_, asm)| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("L__wgmma_pipeline_loop_${:uid}:"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        matching.len(),
-        1,
-        "expected one fused three-slot counted WGMMA pipeline"
-    );
-
-    let (asm_operation, asm) = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("three-slot counted-pipeline WGMMA template");
-
-    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
-    assert_eq!(template.matches("wgmma.mma_async").count(), 3);
-    assert_eq!(
-        template.matches("wgmma.commit_group.sync.aligned").count(),
-        3
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 2").count(),
-        3
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 0").count(),
-        1
-    );
-    assert!(template.contains("{$0, $1"));
-    assert!(template.contains("{$32, $33"));
-    assert!(template.contains("{$64, $65"));
-    assert!(template.contains("mov.u64 %desc_a0, $192;"));
-    assert!(template.contains("mov.u64 %desc_b0, $193;"));
-    assert!(template.contains("mov.u64 %desc_a1, $194;"));
-    assert!(template.contains("mov.u64 %desc_b1, $195;"));
-    assert!(template.contains("mov.u64 %desc_a2, $196;"));
-    assert!(template.contains("mov.u64 %desc_b2, $197;"));
-    assert!(template.contains("add.u64 %desc_a0, %desc_a0, $198;"));
-    assert!(template.contains("add.u64 %desc_b0, %desc_b0, $199;"));
-    assert!(template.contains("add.u64 %desc_a1, %desc_a1, $200;"));
-    assert!(template.contains("add.u64 %desc_b1, %desc_b1, $201;"));
-    assert!(template.contains("add.u64 %desc_a2, %desc_a2, $202;"));
-    assert!(template.contains("add.u64 %desc_b2, %desc_b2, $203;"));
-    assert!(template.contains("mov.u64 %remaining, $204;"));
-    assert!(
-        !template.contains(".reg .f32")
-            && !template.contains("ld.f32")
-            && !template.contains("st.f32"),
-        "three-slot counted pipeline must keep accumulator memory outside asm: {template}"
-    );
-
-    let mut expected_constraints = vec!["=f".to_owned(); RESULT_COUNT];
-    expected_constraints.extend((0..RESULT_COUNT).map(|index| index.to_string()));
-    expected_constraints.extend((0..LOOP_CONTROL_COUNT).map(|_| "l".to_owned()));
-    expected_constraints.push("~{memory}".to_owned());
-    let expected_constraints = expected_constraints.join(",");
-    assert_eq!(
-        asm.get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .as_deref(),
-        Some(expected_constraints.as_str())
-    );
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-    assert_eq!(
-        asm_operation.deref(&ctx).get_num_operands(),
-        RESULT_COUNT + LOOP_CONTROL_COUNT
-    );
-
-    let asm_position = body
-        .iter()
-        .position(|operation| operation == asm_operation)
-        .expect("three-slot counted-pipeline WGMMA asm must be in the lowered kernel body");
-    let load_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(load_positions.len(), RESULT_COUNT);
-    assert!(load_positions.iter().all(|index| *index < asm_position));
-
-    let store_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(store_positions.len(), RESULT_COUNT);
-    assert!(store_positions.iter().all(|index| *index > asm_position));
-    assert_eq!(
-        body.iter()
-            .filter(|operation| {
-                Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
-            })
-            .count(),
-        RESULT_COUNT
-    );
-
-    Ok(())
-}
-
-#[test]
-fn test_pointer_form_wgmma_counted_pipeline_rejects_wait_two_with_two_slots() {
-    let mut ctx = make_test_ctx();
-    let module_ptr = build_pointer_form_wgmma_counted_pipeline_case(&mut ctx, 2, &[2, 2], false);
-
-    assert!(
-        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).is_err(),
-        "wait_group<2> must require three counted-pipeline accumulator slots"
-    );
-}
-
-#[test]
-fn test_pointer_form_wgmma_counted_pipeline_rejects_mixed_partial_waits() {
-    let mut ctx = make_test_ctx();
-    let module_ptr = build_pointer_form_wgmma_counted_pipeline_case(&mut ctx, 3, &[2, 1, 2], false);
-
-    assert!(
-        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).is_err(),
-        "all counted-pipeline stages must use the same partial-wait depth"
-    );
-}
-
-#[test]
-fn test_pointer_form_wgmma_counted_pipeline_rejects_reused_accumulator_slot() {
-    let mut ctx = make_test_ctx();
-    let module_ptr = build_pointer_form_wgmma_counted_pipeline_case(&mut ctx, 3, &[2, 2, 2], true);
-
-    assert!(
-        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).is_err(),
-        "counted-pipeline accumulator slots must be pairwise distinct"
-    );
-}
-
-#[test]
-fn test_pointer_form_wgmma_counted_k_loop_stays_register_resident() -> Result<(), anyhow::Error> {
-    use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
-    use dialect_mir::types::{MirArrayType, MirPointerKind, MirPtrType};
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::op_interfaces::OperandSegmentInterface;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    const ACCUMULATOR_LEN: usize = 32;
-    const LOOP_CONTROL_COUNT: usize = 5;
-    const TRIP_COUNT: u64 = 4;
-    const DESC_A_STEP: u64 = 16;
-    const DESC_B_STEP: u64 = 32;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
-    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
-    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
-    let unique_accumulator_ptr_ty: pliron::r#type::TypeHandle = MirPtrType::get_generic_with_kind(
-        &mut ctx,
-        accumulator_ty.into(),
-        true,
-        MirPointerKind::UniqueRef,
-    )
-    .into();
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-
-    let (module_ptr, preheader) = build_test_kernel(
-        &mut ctx,
-        vec![accumulator_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
-    );
-    let accumulator = preheader.deref(&ctx).get_argument(0);
-    let desc_a_base = preheader.deref(&ctx).get_argument(1);
-    let desc_b_base = preheader.deref(&ctx).get_argument(2);
-
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
-    let function_region = function.deref(&ctx).get_region(0);
-
-    let header = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![u32_ty.into(), u64_ty.into(), u64_ty.into()],
-    );
-    header.insert_at_back(function_region, &ctx);
-    let body = BasicBlock::new(&mut ctx, None, vec![]);
-    body.insert_at_back(function_region, &ctx);
-    let latch = BasicBlock::new(&mut ctx, None, vec![]);
-    latch.insert_at_back(function_region, &ctx);
-    let exit = BasicBlock::new(&mut ctx, None, vec![]);
-    exit.insert_at_back(function_region, &ctx);
-    let wait_block = BasicBlock::new(&mut ctx, None, vec![]);
-    wait_block.insert_at_back(function_region, &ctx);
-
-    // preheader: fence; i0 = 0; goto header(i0, desc_a_base, desc_b_base)
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(preheader, &ctx);
-    let i0 = append_mir_unsigned_constant(&mut ctx, preheader, u32_ty, 0);
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![i0, desc_a_base, desc_b_base],
-        vec![header],
-        0,
-    )
-    .insert_at_back(preheader, &ctx);
-
-    // header(i, desc_a, desc_b): if !(i < 4) exit else body.
-    let i = header.deref(&ctx).get_argument(0);
-    let desc_a = header.deref(&ctx).get_argument(1);
-    let desc_b = header.deref(&ctx).get_argument(2);
-    let bound = append_mir_unsigned_constant(&mut ctx, header, u32_ty, TRIP_COUNT);
-    let lt = Operation::new(
-        &mut ctx,
-        mir::MirLtOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![i, bound],
-        vec![],
-        0,
-    );
-    lt.insert_at_back(header, &ctx);
-    let lt_value = lt.deref(&ctx).get_result(0);
-    let not_lt = Operation::new(
-        &mut ctx,
-        mir::MirNotOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![lt_value],
-        vec![],
-        0,
-    );
-    not_lt.insert_at_back(header, &ctx);
-    let not_lt_value = not_lt.deref(&ctx).get_result(0);
-    let (branch_operands, segment_sizes) =
-        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![not_lt_value], vec![], vec![]]);
-    let branch = Operation::new(
-        &mut ctx,
-        mir::MirCondBranchOp::get_concrete_op_info(),
-        vec![],
-        branch_operands,
-        vec![exit, body],
-        0,
-    );
-    Operation::get_op::<mir::MirCondBranchOp>(branch, &ctx)
-        .expect("MirCondBranchOp")
-        .set_operand_segment_sizes(&ctx, segment_sizes);
-    branch.insert_at_back(header, &ctx);
-
-    // body: a fresh Rust `&mut` reborrow and one WGMMA per K iteration. Rust
-    // calls end a MIR block, so the post-call arithmetic lives in the latch.
-    // The reborrow is loop-local, but its canonical storage identity is the
-    // preheader accumulator argument.
-    let retype = Operation::new(
-        &mut ctx,
-        mir::MirCastOp::get_concrete_op_info(),
-        vec![unique_accumulator_ptr_ty],
-        vec![accumulator],
-        vec![],
-        0,
-    );
-    mir::MirCastOp::new(retype).set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
-    mir::MirCastOp::new(retype)
-        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
-    retype.insert_at_back(body, &ctx);
-    let reborrowed_accumulator = retype.deref(&ctx).get_result(0);
-    append_pointer_wgmma_mma(&mut ctx, body, reborrowed_accumulator, desc_a, desc_b);
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![latch],
-        0,
-    )
-    .insert_at_back(body, &ctx);
-
-    // latch: affine induction and descriptor recurrences, then the back edge.
-    let one = append_mir_unsigned_constant(&mut ctx, latch, u32_ty, 1);
-    let i_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![i, one],
-        vec![],
-        0,
-    );
-    i_next.insert_at_back(latch, &ctx);
-    let i_next = i_next.deref(&ctx).get_result(0);
-
-    let desc_a_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_A_STEP);
-    let desc_a_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![desc_a, desc_a_step],
-        vec![],
-        0,
-    );
-    desc_a_next.insert_at_back(latch, &ctx);
-    let desc_a_next = desc_a_next.deref(&ctx).get_result(0);
-
-    let desc_b_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_B_STEP);
-    let desc_b_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![desc_b, desc_b_step],
-        vec![],
-        0,
-    );
-    desc_b_next.insert_at_back(latch, &ctx);
-    let desc_b_next = desc_b_next.deref(&ctx).get_result(0);
-
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![i_next, desc_a_next, desc_b_next],
-        vec![header],
-        0,
-    )
-    .insert_at_back(latch, &ctx);
-
-    // Rust calls split the exit sequence too: commit in the loop exit, then
-    // wait_group<0> in its unique linear successor.
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(exit, &ctx);
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![wait_block],
-        0,
-    )
-    .insert_at_back(exit, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, wait_block, 0);
-    append_return(&mut ctx, wait_block);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let matching = body
-        .iter()
-        .copied()
-        .filter_map(|operation| {
-            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
-                .map(|inline_asm| (operation, inline_asm))
-        })
-        .filter(|(_, asm)| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("L__wgmma_loop_${:uid}:"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        matching.len(),
-        1,
-        "expected one fused counted-loop WGMMA asm"
-    );
-
-    let (asm_operation, asm) = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("counted-loop WGMMA template");
-
-    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
-    assert_eq!(
-        template.matches("wgmma.mma_async").count(),
-        1,
-        "the PTX template contains one MMA instruction controlled by the internal K-loop"
-    );
-    assert_eq!(
-        template.matches("wgmma.commit_group.sync.aligned").count(),
-        1
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 0").count(),
-        1
-    );
-    assert!(template.contains("mov.u64 %desc_a, $64;"));
-    assert!(template.contains("mov.u64 %desc_b, $65;"));
-    assert!(template.contains("add.u64 %desc_a, %desc_a, $66;"));
-    assert!(template.contains("add.u64 %desc_b, %desc_b, $67;"));
-    assert!(template.contains("mov.u64 %remaining, $68;"));
-    assert!(template.contains("@%loop_more bra.uni L__wgmma_done_${:uid};"));
-    assert!(template.contains("@%loop_more bra.uni L__wgmma_loop_${:uid};"));
-    assert!(template.contains("L__wgmma_done_${:uid}:"));
-    assert!(
-        !template.contains(".reg .f32")
-            && !template.contains("ld.f32")
-            && !template.contains("st.f32"),
-        "counted-loop WGMMA must keep accumulator memory outside asm: {template}"
-    );
-
-    let mut expected_constraints = vec!["=f".to_owned(); ACCUMULATOR_LEN];
-    expected_constraints.extend((0..ACCUMULATOR_LEN).map(|index| index.to_string()));
-    expected_constraints.extend((0..LOOP_CONTROL_COUNT).map(|_| "l".to_owned()));
-    expected_constraints.push("~{memory}".to_owned());
-    let expected_constraints = expected_constraints.join(",");
-    assert_eq!(
-        asm.get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .as_deref(),
-        Some(expected_constraints.as_str())
-    );
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-    assert_eq!(
-        asm_operation.deref(&ctx).get_num_operands(),
-        ACCUMULATOR_LEN + LOOP_CONTROL_COUNT
-    );
-
-    let asm_position = body
-        .iter()
-        .position(|operation| operation == asm_operation)
-        .expect("counted-loop WGMMA asm must be in the lowered kernel body");
-
-    let load_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        load_positions.len(),
-        ACCUMULATOR_LEN,
-        "K-loop accumulator must be loaded exactly once, not once per iteration"
-    );
-    assert!(load_positions.iter().all(|index| *index < asm_position));
-
-    let store_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        store_positions.len(),
-        ACCUMULATOR_LEN,
-        "K-loop accumulator must be stored exactly once after the final wait"
-    );
-    assert!(store_positions.iter().all(|index| *index > asm_position));
-
-    assert_eq!(
-        body.iter()
-            .filter(
-                |operation| Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
-            )
-            .count(),
-        ACCUMULATOR_LEN
-    );
-
-    Ok(())
-}
-
-#[test]
-fn test_f16_wgmma_counted_k_loop_stays_register_resident() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::{MirArrayType, MirPtrType};
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::op_interfaces::OperandSegmentInterface;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    const ACCUMULATOR_LEN: usize = 32;
-    const LOOP_CONTROL_COUNT: usize = 5;
-    const TRIP_COUNT: u64 = 4;
-    const DESC_A_STEP: u64 = 16;
-    const DESC_B_STEP: u64 = 32;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
-    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
-    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-
-    let (module_ptr, preheader) = build_test_kernel(
-        &mut ctx,
-        vec![accumulator_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
-    );
-    let accumulator = preheader.deref(&ctx).get_argument(0);
-    let desc_a_base = preheader.deref(&ctx).get_argument(1);
-    let desc_b_base = preheader.deref(&ctx).get_argument(2);
-
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
-    let function_region = function.deref(&ctx).get_region(0);
-
-    let header = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![u32_ty.into(), u64_ty.into(), u64_ty.into()],
-    );
-    header.insert_at_back(function_region, &ctx);
-    let latch = BasicBlock::new(&mut ctx, None, vec![]);
-    latch.insert_at_back(function_region, &ctx);
-    let exit = BasicBlock::new(&mut ctx, None, vec![]);
-    exit.insert_at_back(function_region, &ctx);
-
-    // preheader: fence; i0 = 0; goto header(i0, desc_a_base, desc_b_base)
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(preheader, &ctx);
-    let i0 = append_mir_unsigned_constant(&mut ctx, preheader, u32_ty, 0);
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![i0, desc_a_base, desc_b_base],
-        vec![header],
-        0,
-    )
-    .insert_at_back(preheader, &ctx);
-
-    // header(i, desc_a, desc_b): if !(i < 4) exit else latch.
-    let i = header.deref(&ctx).get_argument(0);
-    let desc_a = header.deref(&ctx).get_argument(1);
-    let desc_b = header.deref(&ctx).get_argument(2);
-    let bound = append_mir_unsigned_constant(&mut ctx, header, u32_ty, TRIP_COUNT);
-    let lt = Operation::new(
-        &mut ctx,
-        mir::MirLtOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![i, bound],
-        vec![],
-        0,
-    );
-    lt.insert_at_back(header, &ctx);
-    let lt_value = lt.deref(&ctx).get_result(0);
-    let not_lt = Operation::new(
-        &mut ctx,
-        mir::MirNotOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![lt_value],
-        vec![],
-        0,
-    );
-    not_lt.insert_at_back(header, &ctx);
-    let not_lt_value = not_lt.deref(&ctx).get_result(0);
-    let (branch_operands, segment_sizes) =
-        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![not_lt_value], vec![], vec![]]);
-    let branch = Operation::new(
-        &mut ctx,
-        mir::MirCondBranchOp::get_concrete_op_info(),
-        vec![],
-        branch_operands,
-        vec![exit, latch],
-        0,
-    );
-    Operation::get_op::<mir::MirCondBranchOp>(branch, &ctx)
-        .expect("MirCondBranchOp")
-        .set_operand_segment_sizes(&ctx, segment_sizes);
-    branch.insert_at_back(header, &ctx);
-
-    // latch: one WGMMA per K iteration and affine descriptor recurrences.
-    append_pointer_wgmma_mma_f16(&mut ctx, latch, accumulator, desc_a, desc_b);
-
-    let one = append_mir_unsigned_constant(&mut ctx, latch, u32_ty, 1);
-    let i_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![i, one],
-        vec![],
-        0,
-    );
-    i_next.insert_at_back(latch, &ctx);
-    let i_next = i_next.deref(&ctx).get_result(0);
-
-    let desc_a_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_A_STEP);
-    let desc_a_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![desc_a, desc_a_step],
-        vec![],
-        0,
-    );
-    desc_a_next.insert_at_back(latch, &ctx);
-    let desc_a_next = desc_a_next.deref(&ctx).get_result(0);
-
-    let desc_b_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_B_STEP);
-    let desc_b_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![desc_b, desc_b_step],
-        vec![],
-        0,
-    );
-    desc_b_next.insert_at_back(latch, &ctx);
-    let desc_b_next = desc_b_next.deref(&ctx).get_result(0);
-
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![i_next, desc_a_next, desc_b_next],
-        vec![header],
-        0,
-    )
-    .insert_at_back(latch, &ctx);
-
-    // exit: the only place where the asynchronous lifetime may become visible.
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(exit, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, exit, 0);
-    append_return(&mut ctx, exit);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let body = lowered_kernel_body(&ctx, module_ptr);
-    let matching = body
-        .iter()
-        .copied()
-        .filter_map(|operation| {
-            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
-                .map(|inline_asm| (operation, inline_asm))
-        })
-        .filter(|(_, asm)| {
-            asm.get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .is_some_and(|template| template.contains("L__wgmma_loop_${:uid}:"))
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        matching.len(),
-        1,
-        "expected one fused F16 counted-loop WGMMA asm"
-    );
-
-    let (asm_operation, asm) = &matching[0];
-    let template = asm
-        .get_attr_inline_asm_template(&ctx)
-        .map(|value| String::from((*value).clone()))
-        .expect("F16 counted-loop WGMMA template");
-
-    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
-    assert_eq!(
-        template
-            .matches("wgmma.mma_async.sync.aligned.m64n64k16.f32.f16.f16")
-            .count(),
-        1,
-        "the F16 counted-loop template must contain exactly one F16 MMA"
-    );
-    assert!(!template.contains(".bf16.bf16"));
-    assert_eq!(
-        template.matches("wgmma.commit_group.sync.aligned").count(),
-        1
-    );
-    assert_eq!(
-        template.matches("wgmma.wait_group.sync.aligned 0").count(),
-        1
-    );
-    assert!(template.contains("mov.u64 %desc_a, $64;"));
-    assert!(template.contains("mov.u64 %desc_b, $65;"));
-    assert!(template.contains("add.u64 %desc_a, %desc_a, $66;"));
-    assert!(template.contains("add.u64 %desc_b, %desc_b, $67;"));
-    assert!(template.contains("mov.u64 %remaining, $68;"));
-    assert!(template.contains("@%loop_more bra.uni L__wgmma_done_${:uid};"));
-    assert!(template.contains("@%loop_more bra.uni L__wgmma_loop_${:uid};"));
-    assert!(template.contains("L__wgmma_done_${:uid}:"));
-    assert!(
-        !template.contains(".reg .f32")
-            && !template.contains("ld.f32")
-            && !template.contains("st.f32"),
-        "F16 counted-loop WGMMA must keep accumulator memory outside asm: {template}"
-    );
-
-    let mut expected_constraints = vec!["=f".to_owned(); ACCUMULATOR_LEN];
-    expected_constraints.extend((0..ACCUMULATOR_LEN).map(|index| index.to_string()));
-    expected_constraints.extend((0..LOOP_CONTROL_COUNT).map(|_| "l".to_owned()));
-    expected_constraints.push("~{memory}".to_owned());
-    let expected_constraints = expected_constraints.join(",");
-    assert_eq!(
-        asm.get_attr_inline_asm_constraints(&ctx)
-            .map(|value| String::from((*value).clone()))
-            .as_deref(),
-        Some(expected_constraints.as_str())
-    );
-    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
-    assert_eq!(
-        asm_operation.deref(&ctx).get_num_operands(),
-        ACCUMULATOR_LEN + LOOP_CONTROL_COUNT
-    );
-
-    let asm_position = body
-        .iter()
-        .position(|operation| operation == asm_operation)
-        .expect("F16 counted-loop WGMMA asm must be in the lowered kernel body");
-
-    let load_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        load_positions.len(),
-        ACCUMULATOR_LEN,
-        "F16 K-loop accumulator must be loaded exactly once"
-    );
-    assert!(load_positions.iter().all(|index| *index < asm_position));
-
-    let store_positions = body
-        .iter()
-        .enumerate()
-        .filter_map(|(index, operation)| {
-            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
-                .is_some()
-                .then_some(index)
-        })
-        .collect::<Vec<_>>();
-    assert_eq!(
-        store_positions.len(),
-        ACCUMULATOR_LEN,
-        "F16 K-loop accumulator must be stored exactly once after the final wait"
-    );
-    assert!(store_positions.iter().all(|index| *index > asm_position));
-
-    assert_eq!(
-        body.iter()
-            .filter(
-                |operation| Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
-            )
-            .count(),
-        ACCUMULATOR_LEN
-    );
-
-    Ok(())
-}
-
-#[test]
-fn test_tf32_wgmma_counted_k_loop_remains_unsupported() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::{MirArrayType, MirPtrType};
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::op_interfaces::OperandSegmentInterface;
-    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
-
-    const TRIP_COUNT: u64 = 4;
-    const DESC_A_STEP: u64 = 16;
-    const DESC_B_STEP: u64 = 32;
-
-    let mut ctx = make_test_ctx();
-    let f32_ty = FP32Type::get(&ctx);
-    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
-    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
-    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-
-    let (module_ptr, preheader) = build_test_kernel(
-        &mut ctx,
-        vec![accumulator_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
-    );
-    let accumulator = preheader.deref(&ctx).get_argument(0);
-    let desc_a_base = preheader.deref(&ctx).get_argument(1);
-    let desc_b_base = preheader.deref(&ctx).get_argument(2);
-
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
-    let function_region = function.deref(&ctx).get_region(0);
-
-    let header = BasicBlock::new(
-        &mut ctx,
-        None,
-        vec![u32_ty.into(), u64_ty.into(), u64_ty.into()],
-    );
-    header.insert_at_back(function_region, &ctx);
-    let latch = BasicBlock::new(&mut ctx, None, vec![]);
-    latch.insert_at_back(function_region, &ctx);
-    let exit = BasicBlock::new(&mut ctx, None, vec![]);
-    exit.insert_at_back(function_region, &ctx);
-
-    // preheader: fence; i0 = 0; goto header(i0, desc_a_base, desc_b_base)
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(preheader, &ctx);
-    let i0 = append_mir_unsigned_constant(&mut ctx, preheader, u32_ty, 0);
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![i0, desc_a_base, desc_b_base],
-        vec![header],
-        0,
-    )
-    .insert_at_back(preheader, &ctx);
-
-    // header(i, desc_a, desc_b): if !(i < 4) exit else latch.
-    let i = header.deref(&ctx).get_argument(0);
-    let desc_a = header.deref(&ctx).get_argument(1);
-    let desc_b = header.deref(&ctx).get_argument(2);
-    let bound = append_mir_unsigned_constant(&mut ctx, header, u32_ty, TRIP_COUNT);
-    let lt = Operation::new(
-        &mut ctx,
-        mir::MirLtOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![i, bound],
-        vec![],
-        0,
-    );
-    lt.insert_at_back(header, &ctx);
-    let lt_value = lt.deref(&ctx).get_result(0);
-    let not_lt = Operation::new(
-        &mut ctx,
-        mir::MirNotOp::get_concrete_op_info(),
-        vec![i1_ty.into()],
-        vec![lt_value],
-        vec![],
-        0,
-    );
-    not_lt.insert_at_back(header, &ctx);
-    let not_lt_value = not_lt.deref(&ctx).get_result(0);
-    let (branch_operands, segment_sizes) =
-        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![not_lt_value], vec![], vec![]]);
-    let branch = Operation::new(
-        &mut ctx,
-        mir::MirCondBranchOp::get_concrete_op_info(),
-        vec![],
-        branch_operands,
-        vec![exit, latch],
-        0,
-    );
-    Operation::get_op::<mir::MirCondBranchOp>(branch, &ctx)
-        .expect("MirCondBranchOp")
-        .set_operand_segment_sizes(&ctx, segment_sizes);
-    branch.insert_at_back(header, &ctx);
-
-    // latch: one WGMMA per K iteration and affine descriptor recurrences.
-    append_pointer_wgmma_mma_tf32(&mut ctx, latch, accumulator, desc_a, desc_b);
-
-    let one = append_mir_unsigned_constant(&mut ctx, latch, u32_ty, 1);
-    let i_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u32_ty.into()],
-        vec![i, one],
-        vec![],
-        0,
-    );
-    i_next.insert_at_back(latch, &ctx);
-    let i_next = i_next.deref(&ctx).get_result(0);
-
-    let desc_a_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_A_STEP);
-    let desc_a_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![desc_a, desc_a_step],
-        vec![],
-        0,
-    );
-    desc_a_next.insert_at_back(latch, &ctx);
-    let desc_a_next = desc_a_next.deref(&ctx).get_result(0);
-
-    let desc_b_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_B_STEP);
-    let desc_b_next = Operation::new(
-        &mut ctx,
-        mir::MirAddOp::get_concrete_op_info(),
-        vec![u64_ty.into()],
-        vec![desc_b, desc_b_step],
-        vec![],
-        0,
-    );
-    desc_b_next.insert_at_back(latch, &ctx);
-    let desc_b_next = desc_b_next.deref(&ctx).get_result(0);
-
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![i_next, desc_a_next, desc_b_next],
-        vec![header],
-        0,
-    )
-    .insert_at_back(latch, &ctx);
-
-    // exit: the only place where the asynchronous lifetime may become visible.
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(exit, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, exit, 0);
-    append_return(&mut ctx, exit);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA MMA reached lowering without deferred accumulator fusion",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_m64n128_wgmma_noncanonical_accumulator_has_no_pointer_fallback() -> Result<(), anyhow::Error>
-{
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma_m64n128(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA linear full-drain lowering for this variant requires a canonical [[f32; 8]; 8] accumulator",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_f16_wgmma_noncanonical_accumulator_has_no_pointer_fallback() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma_f16(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA linear full-drain lowering for this variant requires a canonical [[f32; 8]; 4] accumulator",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_tf32_wgmma_noncanonical_accumulator_has_no_pointer_fallback() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma_tf32(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA linear full-drain lowering for this variant requires a canonical [[f32; 8]; 4] accumulator",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_linear_wgmma_full_drain_rejects_mixed_bf16_and_f16() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, descriptors) =
-        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 4);
-    let accumulator = accumulators[0];
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
-    append_pointer_wgmma_mma_f16(&mut ctx, entry, accumulator, descriptors[2], descriptors[3]);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "one linear WGMMA full-drain region cannot mix MMA variants or shapes",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_linear_wgmma_full_drain_rejects_mixed_bf16_and_tf32() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, descriptors) =
-        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 4);
-    let accumulator = accumulators[0];
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
-    append_pointer_wgmma_mma_tf32(&mut ctx, entry, accumulator, descriptors[2], descriptors[3]);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "one linear WGMMA full-drain region cannot mix MMA variants or shapes",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_linear_wgmma_full_drain_rejects_mixed_f16_and_tf32() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, descriptors) =
-        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 4);
-    let accumulator = accumulators[0];
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma_f16(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
-    append_pointer_wgmma_mma_tf32(&mut ctx, entry, accumulator, descriptors[2], descriptors[3]);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "one linear WGMMA full-drain region cannot mix MMA variants or shapes",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_f16_wgmma_partial_wait_remains_unsupported() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, descriptors) =
-        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 2);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma_f16(
-        &mut ctx,
-        entry,
-        accumulators[0],
-        descriptors[0],
-        descriptors[1],
-    );
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 1);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA deferred accumulator lowering requires wait_group<0>",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_tf32_wgmma_partial_wait_remains_unsupported() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, descriptors) =
-        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 2);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma_tf32(
-        &mut ctx,
-        entry,
-        accumulators[0],
-        descriptors[0],
-        descriptors[1],
-    );
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 1);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA deferred accumulator lowering requires wait_group<0>",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_pointer_form_wgmma_without_fence_is_rejected() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA MMA reached lowering without deferred accumulator fusion",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_deferred_wgmma_without_commit_is_rejected() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA wait_group requires a preceding commit_group",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_wgmma_partial_wait_without_final_wait_zero_is_rejected() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 1);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA partial-wait pipeline requires a final wait_group<0>",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_wgmma_partial_wait_pipeline_rejects_unsafe_accumulator_reuse() -> Result<(), anyhow::Error>
-{
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, descriptors) =
-        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 4);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(
-        &mut ctx,
-        entry,
-        accumulators[0],
-        descriptors[0],
-        descriptors[1],
-    );
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(
-        &mut ctx,
-        entry,
-        accumulators[0],
-        descriptors[2],
-        descriptors[3],
-    );
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 1);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA partial-wait pipeline requires max_pending_groups + 1 distinct accumulator slots",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_wgmma_wait_group_eight_is_rejected() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 8);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA wait_group<N> immediate must be in 0..=7",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_deferred_wgmma_two_commits_are_rejected() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA deferred accumulator region supports exactly one commit_group",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_deferred_wgmma_multiple_accumulators_are_rejected() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 2, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[1], desc_a, desc_b);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA deferred accumulator region uses more than one accumulator",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_deferred_wgmma_mma_after_commit_is_rejected() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA MMA cannot appear after commit_group in a deferred accumulator region",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_deferred_wgmma_branch_is_rejected() -> Result<(), anyhow::Error> {
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::op_interfaces::OperandSegmentInterface;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let bool_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
-    let (module_ptr, entry, accumulators, desc_a, desc_b, trailing) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![bool_ty.into()]);
-    let condition = trailing[0];
-
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
-    let function_region = function.deref(&ctx).get_region(0);
-
-    let then_block = BasicBlock::new(&mut ctx, None, vec![]);
-    then_block.insert_at_back(function_region, &ctx);
-    let else_block = BasicBlock::new(&mut ctx, None, vec![]);
-    else_block.insert_at_back(function_region, &ctx);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-
-    let (flat_operands, segment_sizes) =
-        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![condition], vec![], vec![]]);
-    let branch = Operation::new(
-        &mut ctx,
-        mir::MirCondBranchOp::get_concrete_op_info(),
-        vec![],
-        flat_operands,
-        vec![then_block, else_block],
-        0,
-    );
-    Operation::get_op::<mir::MirCondBranchOp>(branch, &ctx)
-        .expect("MirCondBranchOp")
-        .set_operand_segment_sizes(&ctx, segment_sizes);
-    branch.insert_at_back(entry, &ctx);
-
-    append_return(&mut ctx, then_block);
-    append_return(&mut ctx, else_block);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "unsupported operation inside WGMMA deferred accumulator region",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_deferred_wgmma_join_is_rejected() -> Result<(), anyhow::Error> {
-    use pliron::basic_block::BasicBlock;
-
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
-    let function_region = function.deref(&ctx).get_region(0);
-
-    let second_predecessor = BasicBlock::new(&mut ctx, None, vec![]);
-    second_predecessor.insert_at_back(function_region, &ctx);
-    let join = BasicBlock::new(&mut ctx, None, vec![]);
-    join.insert_at_back(function_region, &ctx);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![join],
-        0,
-    )
-    .insert_at_back(entry, &ctx);
-
-    Operation::new(
-        &mut ctx,
-        mir::MirGotoOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![join],
-        0,
-    )
-    .insert_at_back(second_predecessor, &ctx);
-
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(join, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, join, 0);
-    append_return(&mut ctx, join);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "WGMMA deferred accumulator region cannot cross a control-flow join",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_deferred_wgmma_intervening_operation_is_rejected() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-
-    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
-    Operation::new(
-        &mut ctx,
-        nvvm::ReadPtxSregTidXOp::get_concrete_op_info(),
-        vec![i32_ty.into()],
-        vec![],
-        vec![],
-        0,
-    )
-    .insert_at_back(entry, &ctx);
-
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "unsupported operation inside WGMMA deferred accumulator region",
-    );
-    Ok(())
-}
-
-#[test]
-fn test_deferred_wgmma_nested_fence_is_rejected() -> Result<(), anyhow::Error> {
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
-        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
-
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
-    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
-    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
-    append_return(&mut ctx, entry);
-
-    assert_wgmma_lowering_rejected(
-        &mut ctx,
-        module_ptr,
-        "nested WGMMA fences are not supported in one deferred accumulator region",
-    );
-    Ok(())
-}
-
-/// Scoped atomic loads and stores must lower to inline PTX, not to
-/// `load atomic` / `store atomic`.
-///
-/// libNVVM rejects the IR-level form outright ("Atomic loads/stores are not
-/// supported"), so lowering to `llvm::AtomicLoadOp` / `llvm::AtomicStoreOp`
-/// produced modules that no `--materialize-cubin` build could consume, making
-/// every `DeviceAtomic*::load` and `::store` call a build failure. The PTX
-/// instructions themselves have existed since sm_70, so the ops lower through
-/// inline assembly instead.
-///
-/// This asserts the exact template, constraints and asm kind, because all
-/// three are load-bearing: the scope qualifier is the whole point of the
-/// feature, the constraint register class must match the operand width, and
-/// `SideEffect` plus the memory clobber is what stops a publication spin being
-/// hoisted out of its loop.
-#[test]
-fn test_scoped_atomic_load_store_lower_to_inline_ptx() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use dialect_nvvm::ops::atomic::{
-        AtomicOrdering, AtomicScope, NvvmAtomicLoadOp, NvvmAtomicStoreOp,
-    };
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = make_test_ctx();
-    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
-    let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
-    let (module_ptr, entry) =
-        build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into(), u64_ty.into()]);
-    let address = entry.deref(&ctx).get_argument(0);
-    let val32 = entry.deref(&ctx).get_argument(1);
-    let val64 = entry.deref(&ctx).get_argument(2);
-
-    // One per scope, so a regression that hardcodes a scope is caught rather
-    // than passing on the Device case alone.
-    NvvmAtomicLoadOp::build(
-        &mut ctx,
-        address,
-        u32_ty.into(),
-        AtomicOrdering::Relaxed,
-        AtomicScope::Device,
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    NvvmAtomicLoadOp::build(
-        &mut ctx,
-        address,
-        u32_ty.into(),
-        AtomicOrdering::Acquire,
-        AtomicScope::Block,
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    NvvmAtomicLoadOp::build(
-        &mut ctx,
-        address,
-        u64_ty.into(),
-        AtomicOrdering::Relaxed,
-        AtomicScope::System,
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    NvvmAtomicStoreOp::build(
-        &mut ctx,
-        val32,
-        address,
-        AtomicOrdering::Release,
-        AtomicScope::Device,
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    NvvmAtomicStoreOp::build(
-        &mut ctx,
-        val64,
-        address,
-        AtomicOrdering::Relaxed,
-        AtomicScope::Device,
-    )
-    .get_operation()
-    .insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-    let mut lowered = Vec::new();
-    let module_region = module_ptr.deref(&ctx).get_region(0);
-    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
-    for op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(function) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
-            continue;
-        }
-        let body = function.get_operation().deref(&ctx).get_region(0);
-        for block in body.deref(&ctx).iter(&ctx) {
-            for body_op in block.deref(&ctx).iter(&ctx) {
-                // The IR-level forms are what libNVVM rejects; neither may survive.
-                assert!(
-                    Operation::get_op::<llvm::AtomicLoadOp>(body_op, &ctx).is_none(),
-                    "scoped atomic load must not lower to `load atomic`: libNVVM rejects it"
-                );
-                assert!(
-                    Operation::get_op::<llvm::AtomicStoreOp>(body_op, &ctx).is_none(),
-                    "scoped atomic store must not lower to `store atomic`: libNVVM rejects it"
-                );
-                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
-                    continue;
-                };
-                let template = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .unwrap_or_default();
-                if !template.starts_with("ld.") && !template.starts_with("st.") {
-                    continue;
-                }
-                lowered.push((
-                    template,
-                    asm.get_attr_inline_asm_constraints(&ctx)
-                        .map(|value| String::from((*value).clone()))
-                        .unwrap_or_default(),
-                    llvm::asm_kind(&ctx, &asm),
-                ));
-            }
-        }
-    }
-
-    // Every access keeps the `~{memory}` clobber, Relaxed included. Without
-    // it LLVM may move plain loads and stores of the same address across the
-    // asm, breaking the single-thread coherence Rust still guarantees for
-    // Relaxed atomics; libcu++ keeps the clobber on its relaxed accesses too.
-    let expected = [
-        ("ld.relaxed.gpu.b32 $0, [$1];", "=r,l,~{memory}"),
-        ("ld.acquire.cta.b32 $0, [$1];", "=r,l,~{memory}"),
-        ("ld.relaxed.sys.b64 $0, [$1];", "=l,l,~{memory}"),
-        ("st.release.gpu.b32 [$0], $1;", "l,r,~{memory}"),
-        ("st.relaxed.gpu.b64 [$0], $1;", "l,l,~{memory}"),
-    ];
-    assert_eq!(
-        lowered.len(),
-        expected.len(),
-        "expected one inline-asm op per scoped atomic load/store, got {lowered:?}"
-    );
-    for (template, constraints) in expected {
-        let found = lowered
-            .iter()
-            .find(|(t, _, _)| t == template)
-            .unwrap_or_else(|| panic!("missing lowering for {template}; got {lowered:?}"));
-        assert_eq!(found.1, constraints, "constraints for {template}");
-        // Not Convergent: these are per-thread accesses, not warp-synchronous.
-        // SideEffect with the memory clobber is what keeps a spin re-reading.
-        assert_eq!(
-            found.2,
-            llvm::AsmKind::SideEffect,
-            "asm kind for {template}"
-        );
-    }
-    Ok(())
-}
-
-/// Orderings a PTX load or store cannot carry must be rejected, not silently
-/// weakened.
-///
-/// Acquire is load-only, Release is store-only, and AcqRel makes no sense on
-/// a single access. Approximating any of them with `relaxed` would be a
-/// correctness bug that no runtime test would catch, because the wrong answer
-/// only appears under contention on hardware that reorders.
-#[test]
-fn test_scoped_atomic_rejects_inexpressible_orderings() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use dialect_nvvm::ops::atomic::{
-        AtomicOrdering, AtomicScope, NvvmAtomicLoadOp, NvvmAtomicStoreOp,
-    };
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    for (is_load, ordering) in [
-        (true, AtomicOrdering::Release), // release is store-only
-        (true, AtomicOrdering::AcqRel),
-        (false, AtomicOrdering::Acquire), // acquire is load-only
-        (false, AtomicOrdering::AcqRel),
-    ] {
-        let mut ctx = make_test_ctx();
-        let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-        let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
-        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into()]);
-        let address = entry.deref(&ctx).get_argument(0);
-        let val = entry.deref(&ctx).get_argument(1);
-
-        if is_load {
-            NvvmAtomicLoadOp::build(
-                &mut ctx,
-                address,
-                u32_ty.into(),
-                ordering.clone(),
-                AtomicScope::Device,
-            )
-            .get_operation()
-            .insert_at_back(entry, &ctx);
-        } else {
-            NvvmAtomicStoreOp::build(
-                &mut ctx,
-                val,
-                address,
-                ordering.clone(),
-                AtomicScope::Device,
-            )
-            .get_operation()
-            .insert_at_back(entry, &ctx);
-        }
-        append_return(&mut ctx, entry);
-
-        let result = mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr);
-        assert!(
-            result.is_err(),
-            "{} with {ordering:?} ordering must be rejected, not approximated",
-            if is_load { "load" } else { "store" }
-        );
-    }
-    Ok(())
-}
-
-/// SeqCst load and store lower to one asm op whose template fuses the
-/// `fence.sc` with the access, at every scope.
-///
-/// PTX has no sequentially consistent load or store instruction. libcu++ maps
-/// a SeqCst load to `fence.sc.{scope}` followed by an acquire load at the
-/// same scope, and a SeqCst store to `fence.sc.{scope}` followed by a release
-/// store. Fusing the fence into the same template keeps the pair inseparable.
-#[test]
-fn test_seqcst_atomic_load_store_fuse_fence_into_template() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use dialect_nvvm::ops::atomic::{
-        AtomicOrdering, AtomicScope, NvvmAtomicLoadOp, NvvmAtomicStoreOp,
-    };
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    for (scope, ptx) in [
-        (AtomicScope::Device, "gpu"),
-        (AtomicScope::Block, "cta"),
-        (AtomicScope::System, "sys"),
-    ] {
-        let mut ctx = make_test_ctx();
-        let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-        let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
-        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into()]);
-        let address = entry.deref(&ctx).get_argument(0);
-        let val = entry.deref(&ctx).get_argument(1);
-
-        NvvmAtomicLoadOp::build(
-            &mut ctx,
-            address,
-            u32_ty.into(),
-            AtomicOrdering::SeqCst,
-            scope.clone(),
-        )
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-        NvvmAtomicStoreOp::build(&mut ctx, val, address, AtomicOrdering::SeqCst, scope)
-            .get_operation()
-            .insert_at_back(entry, &ctx);
-        append_return(&mut ctx, entry);
-
-        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-        let mut lowered = Vec::new();
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-                continue;
-            };
-            lowered.push((
-                asm.get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .unwrap_or_default(),
-                asm.get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .unwrap_or_default(),
-            ));
-        }
-        let expected = vec![
-            (
-                format!("fence.sc.{ptx}; ld.acquire.{ptx}.b32 $0, [$1];"),
-                "=r,l,~{memory}".to_string(),
-            ),
-            (
-                format!("fence.sc.{ptx}; st.release.{ptx}.b32 [$0], $1;"),
-                "l,r,~{memory}".to_string(),
-            ),
-        ];
-        assert_eq!(lowered, expected, "SeqCst lowering at scope {ptx}");
-    }
-    Ok(())
-}
-
-/// Float atomic loads and stores travel through integer registers with an
-/// LLVM-level bitcast on each side.
-///
-/// The register classes in the constraints are integer (`h`/`r`/`l`), so
-/// handing llc a float-typed asm operand or result is a constraint mismatch.
-/// The store bitcasts the float to the same-width integer before the asm; the
-/// load returns the integer and bitcasts it back to the float type. The f16
-/// case also covers the `b16`/`h` arm end to end, which is what makes
-/// `DeviceAtomicF16::load`/`store` compile at all.
-#[test]
-fn test_float_atomic_load_store_bitcast_through_integer_registers() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::{MirFP16Type, MirPtrType};
-    use dialect_nvvm::ops::atomic::{
-        AtomicOrdering, AtomicScope, NvvmAtomicLoadOp, NvvmAtomicStoreOp,
-    };
-    use llvm_export::types as llvm_types;
-    use pliron::builtin::types::{FP32Type, IntegerType};
-    use pliron::r#type::Typed;
-
-    let is_expected_float = |ctx: &Context, ty: pliron::r#type::TypeHandle, width: u32| -> bool {
-        let ty_ref = ty.deref(ctx);
-        match width {
-            16 => ty_ref.is::<llvm_types::HalfType>(),
-            32 => ty_ref.is::<FP32Type>(),
-            _ => false,
-        }
-    };
-    let integer_width_of = |ctx: &Context, ty: pliron::r#type::TypeHandle| -> Option<u32> {
-        ty.deref(ctx)
-            .downcast_ref::<IntegerType>()
-            .map(IntegerType::width)
-    };
-
-    for (is_f16, ptx_ty, reg, width) in [(false, "b32", "r", 32u32), (true, "b16", "h", 16u32)] {
-        let mut ctx = make_test_ctx();
-        let elem_ty: pliron::r#type::TypeHandle = if is_f16 {
-            MirFP16Type::get(&ctx).into()
-        } else {
-            FP32Type::get(&ctx).into()
-        };
-        let ptr_ty = MirPtrType::get_generic(&mut ctx, elem_ty, true);
-        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), elem_ty]);
-        let address = entry.deref(&ctx).get_argument(0);
-        let val = entry.deref(&ctx).get_argument(1);
-
-        NvvmAtomicLoadOp::build(
-            &mut ctx,
-            address,
-            elem_ty,
-            AtomicOrdering::Relaxed,
-            AtomicScope::Device,
-        )
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-        NvvmAtomicStoreOp::build(
-            &mut ctx,
-            val,
-            address,
-            AtomicOrdering::Relaxed,
-            AtomicScope::Device,
-        )
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-        append_return(&mut ctx, entry);
-
-        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-        let mut ld_asm = None;
-        let mut st_asm = None;
-        let mut bitcasts = Vec::new();
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            if let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
-                let template = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .unwrap_or_default();
-                let constraints = asm
-                    .get_attr_inline_asm_constraints(&ctx)
-                    .map(|value| String::from((*value).clone()))
-                    .unwrap_or_default();
-                if template.starts_with("ld.") {
-                    ld_asm = Some((op, template, constraints));
-                } else if template.starts_with("st.") {
-                    st_asm = Some((op, template, constraints));
-                }
-            }
-            if Operation::get_op::<llvm::BitcastOp>(op, &ctx).is_some() {
-                bitcasts.push(op);
-            }
-        }
-
-        // Load direction: asm produces the staging integer, then one bitcast
-        // turns it back into the float.
-        let (ld_op, ld_template, ld_constraints) =
-            ld_asm.expect("float atomic load must lower to inline asm");
-        assert_eq!(ld_template, format!("ld.relaxed.gpu.{ptx_ty} $0, [$1];"));
-        assert_eq!(ld_constraints, format!("={reg},l,~{{memory}}"));
-        let ld_result = ld_op.deref(&ctx).get_result(0);
-        assert_eq!(
-            integer_width_of(&ctx, ld_result.get_type(&ctx)),
-            Some(width),
-            "load asm must produce the staging integer, not the float"
-        );
-        let load_cast = bitcasts
-            .iter()
-            .copied()
-            .find(|&cast| cast.deref(&ctx).get_operand(0) == ld_result)
-            .expect("load asm result must be bitcast back to the float type");
-        let load_cast_ty = load_cast.deref(&ctx).get_result(0).get_type(&ctx);
-        assert!(
-            is_expected_float(&ctx, load_cast_ty, width),
-            "load bitcast must produce the float type"
-        );
-
-        // Store direction: the float is bitcast to the staging integer, and
-        // that integer is what the asm consumes.
-        let (st_op, st_template, st_constraints) =
-            st_asm.expect("float atomic store must lower to inline asm");
-        assert_eq!(st_template, format!("st.relaxed.gpu.{ptx_ty} [$0], $1;"));
-        assert_eq!(st_constraints, format!("l,{reg},~{{memory}}"));
-        let stored = st_op.deref(&ctx).get_operand(1);
-        assert_eq!(
-            integer_width_of(&ctx, stored.get_type(&ctx)),
-            Some(width),
-            "store asm must consume the staging integer, not the float"
-        );
-        let store_cast = bitcasts
-            .iter()
-            .copied()
-            .find(|&cast| cast.deref(&ctx).get_result(0) == stored)
-            .expect("store asm value must come from a float-to-integer bitcast");
-        let store_src_ty = store_cast.deref(&ctx).get_operand(0).get_type(&ctx);
-        assert!(
-            is_expected_float(&ctx, store_src_ty, width),
-            "store bitcast must consume the float type"
-        );
-    }
-    Ok(())
-}
-
-/// A SeqCst fence must go through the typed NVVM intrinsic, and a weaker one
-/// through inline PTX.
-///
-/// PTX defines `membar.level` as a synonym for `fence.sc.level`, so
-/// `llvm.nvvm.membar.{cta,gl,sys}` is an exact match for SeqCst and is the route
-/// the rest of the crate already uses for fences. No intrinsic exists for a
-/// weaker fence, and emitting `membar` for AcqRel would silently upgrade the
-/// caller's request to sequential consistency, so that case emits
-/// `fence.acq_rel.{scope}` directly.
-#[test]
-fn test_fence_uses_membar_intrinsic_only_for_seqcst() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirPtrType;
-    use dialect_nvvm::ops::atomic::{AtomicOrdering, AtomicRmwKind, AtomicScope, NvvmAtomicRmwOp};
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    for (ordering, want_intrinsic, want_asm) in [
-        (AtomicOrdering::SeqCst, Some("llvm_nvvm_membar_gl"), None),
-        (AtomicOrdering::AcqRel, None, Some("fence.acq_rel.gpu;")),
-    ] {
-        let mut ctx = make_test_ctx();
-        let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
-        let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
-        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into()]);
-        let address = entry.deref(&ctx).get_argument(0);
-        let addend = entry.deref(&ctx).get_argument(1);
-
-        NvvmAtomicRmwOp::build(
-            &mut ctx,
-            address,
-            addend,
-            u32_ty.into(),
-            AtomicRmwKind::Add,
-            ordering.clone(),
-            AtomicScope::Device,
-        )
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-        append_return(&mut ctx, entry);
-
-        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-        let mut saw_intrinsic = false;
-        let mut saw_asm = None;
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-                && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-                && callee.to_string().contains("membar")
-            {
-                saw_intrinsic = true;
-            }
-            if let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
-                let t = asm
-                    .get_attr_inline_asm_template(&ctx)
-                    .map(|v| String::from((*v).clone()))
-                    .unwrap_or_default();
-                if t.starts_with("fence.") {
-                    saw_asm = Some(t);
-                }
-            }
-        }
-        assert_eq!(
-            saw_intrinsic,
-            want_intrinsic.is_some(),
-            "{ordering:?}: membar intrinsic presence"
-        );
-        assert_eq!(saw_asm.as_deref(), want_asm, "{ordering:?}: inline fence");
-        // A SeqCst fence must never also emit `membar` as assembly: that would
-        // mean both routes fired.
-        if want_intrinsic.is_some() {
-            assert!(saw_asm.is_none(), "{ordering:?}: emitted both routes");
-        }
-    }
-    Ok(())
-}
-
-/// A first-class atomic fence must lower through the same libNVVM-safe routes
-/// used by the RMW ordering workaround.
-///
-/// `core::sync::atomic::fence` imports with system scope, so the source-level
-/// path depends on this exact mapping: Acquire/Release/AcqRel become
-/// `fence.acq_rel.sys`, while SeqCst becomes `llvm.nvvm.membar.sys`.
-#[test]
-fn test_first_class_atomic_fence_lowers_at_system_scope() -> Result<(), anyhow::Error> {
-    use dialect_nvvm::ops::atomic::{AtomicOrdering, AtomicScope, NvvmAtomicFenceOp};
-
-    for ordering in [
-        AtomicOrdering::Acquire,
-        AtomicOrdering::Release,
-        AtomicOrdering::AcqRel,
-        AtomicOrdering::SeqCst,
-    ] {
-        let mut ctx = make_test_ctx();
-        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
-
-        NvvmAtomicFenceOp::build(&mut ctx, ordering.clone(), AtomicScope::System)
-            .get_operation()
-            .insert_at_back(entry, &ctx);
-        append_return(&mut ctx, entry);
-
-        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-            .map_err(|error| anyhow::anyhow!("{error}"))?;
-
-        let mut membar_calls = 0usize;
-        let mut fence_asm = Vec::new();
-        for op in lowered_kernel_body(&ctx, module_ptr) {
-            assert!(
-                Operation::get_op::<NvvmAtomicFenceOp>(op, &ctx).is_none(),
-                "first-class atomic fence must be fully consumed by lowering"
-            );
-
-            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
-                && let CallOpCallable::Direct(callee) = call.callee(&ctx)
-                && callee.to_string() == "llvm_nvvm_membar_sys"
-            {
-                membar_calls += 1;
-            }
-
-            let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
-                continue;
-            };
-            let template = asm
-                .get_attr_inline_asm_template(&ctx)
-                .map(|value| String::from((*value).clone()))
-                .unwrap_or_default();
-            if template.starts_with("fence.") {
-                assert_eq!(
-                    asm.get_attr_inline_asm_constraints(&ctx)
-                        .map(|value| String::from((*value).clone()))
-                        .as_deref(),
-                    Some("~{memory}")
-                );
-                assert_eq!(llvm::asm_kind(&ctx, &asm), llvm::AsmKind::SideEffect);
-                fence_asm.push(template);
-            }
-        }
-
-        match ordering {
-            AtomicOrdering::SeqCst => {
-                assert_eq!(membar_calls, 1, "SeqCst must use membar.sys");
-                assert!(
-                    fence_asm.is_empty(),
-                    "SeqCst must not also emit an inline PTX fence"
-                );
-            }
-            AtomicOrdering::Acquire | AtomicOrdering::Release | AtomicOrdering::AcqRel => {
-                assert_eq!(membar_calls, 0, "weak fences must not use membar.sys");
-                assert_eq!(
-                    fence_asm,
-                    vec!["fence.acq_rel.sys;".to_owned()],
-                    "{ordering:?} must lower to one system-scope acq_rel fence"
-                );
-            }
-            AtomicOrdering::Relaxed => unreachable!("Relaxed is not a valid Rust fence ordering"),
-        }
-    }
-
-    Ok(())
-}
-
-#[test]
-fn test_first_class_atomic_fence_rejects_relaxed() -> Result<(), anyhow::Error> {
-    use dialect_nvvm::ops::atomic::{AtomicOrdering, AtomicScope, NvvmAtomicFenceOp};
-
-    let mut ctx = make_test_ctx();
-    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
-    NvvmAtomicFenceOp::build(&mut ctx, AtomicOrdering::Relaxed, AtomicScope::System)
-        .get_operation()
-        .insert_at_back(entry, &ctx);
-    append_return(&mut ctx, entry);
-
-    let result = mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr);
-    assert!(
-        result.is_err(),
-        "Relaxed is not a valid atomic fence ordering and must be rejected"
-    );
-    Ok(())
-}
-
-/// Builds a module holding a single `mir.func` whose body calls the `bswap`
-/// placeholder on a `u8` argument, with the call result carrying `result_ty`.
-/// Shared by the valid (u8 result) and malformed (tuple result) 8-bit bswap
-/// tests below.
-fn build_bswap8_call_module(
-    ctx: &mut Context,
-    result_ty: pliron::r#type::TypeHandle,
-) -> pliron::context::Ptr<Operation> {
-    use pliron::basic_block::BasicBlock;
-    use pliron::builtin::attributes::StringAttr;
-    use pliron::builtin::attributes::TypeAttr;
-    use pliron::builtin::types::{FunctionType, IntegerType, Signedness};
-
-    let u8_ty = IntegerType::get(ctx, 8, Signedness::Unsigned);
-
-    let module = ModuleOp::new(ctx, "m".try_into().unwrap());
-    let module_ptr = module.get_operation();
-    let module_block = module
-        .get_operation()
-        .deref(ctx)
-        .get_region(0)
-        .deref(ctx)
-        .iter(ctx)
-        .next()
-        .unwrap();
-
-    let func_ty = FunctionType::get(ctx, vec![u8_ty.into()], vec![]);
-    let func_op = Operation::new(
-        ctx,
-        mir::MirFuncOp::get_concrete_op_info(),
-        vec![],
-        vec![],
-        vec![],
-        1,
-    );
-    let func = mir::MirFuncOp::new(ctx, func_op, TypeAttr::new(func_ty.into()));
-    func.set_symbol_name(ctx, "f".try_into().unwrap());
-    {
-        let region = func.get_operation().deref(ctx).get_region(0);
-        let block = BasicBlock::new(ctx, None, vec![u8_ty.into()]);
-        block.insert_at_back(region, ctx);
-        let arg = block.deref(ctx).get_argument(0);
-
-        let call_ptr = Operation::new(
-            ctx,
-            mir::MirCallOp::get_concrete_op_info(),
-            vec![result_ty],
-            vec![arg],
-            vec![],
-            0,
-        );
-        let call = mir::MirCallOp::new(call_ptr);
-        call.set_attr_callee(
-            ctx,
-            StringAttr::new(dialect_mir::rust_intrinsics::CALLEE_BSWAP.to_string()),
-        );
-        call_ptr.insert_at_back(block, ctx);
-
-        let ret_op = Operation::new(
-            ctx,
-            mir::MirReturnOp::get_concrete_op_info(),
-            vec![],
-            vec![],
-            vec![],
-            0,
-        );
-        ret_op.insert_at_back(block, ctx);
-    }
-    func.get_operation().insert_at_back(module_block, ctx);
-
-    module_ptr
-}
-
-/// An 8-bit `bswap` takes an early bitcast path, since Rust's semantics for a
-/// single byte are identity and LLVM has no useful intrinsic for it. That path
-/// returned before reaching the cast every other arm goes through, so a result
-/// type that was not an 8-bit integer produced `bitcast i8 to <aggregate>`,
-/// which LLVM rejects when the module is read back.
-///
-/// The known producer of this shape is an importer bug that hands the call
-/// the type of the destination *local* rather than of the projected place it
-/// writes, so `RET.1 = bswap(x)` on a `(f64, u8)` return arrives here
-/// carrying the whole tuple. That bug is the importer's to fix, and whatever
-/// the importer does, a malformed producer can still build such a `mir.call`.
-/// Lowering cannot repair it, and refusing it is what keeps the emitted
-/// module valid.
-#[test]
-fn bswap8_with_an_aggregate_result_is_refused_rather_than_bitcast() -> Result<(), anyhow::Error> {
-    use dialect_mir::types::MirTupleType;
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let f64_ty = pliron::builtin::types::FP64Type::get(&ctx);
-    // The tuple result is the whole point: an 8-bit operand with a result
-    // the bitcast cannot legally produce.
-    let tuple_ty = MirTupleType::get(&mut ctx, vec![f64_ty.into(), u8_ty.into()]);
-    let module_ptr = build_bswap8_call_module(&mut ctx, tuple_ty.into());
-
-    let result = mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr);
-    let error =
-        result.expect_err("an 8-bit bswap with a tuple result must be refused, not lowered");
-    assert!(
-        error
-            .to_string()
-            .contains("expected integer type for Rust bit intrinsic"),
-        "unexpected error: {error}"
-    );
-    Ok(())
-}
-
-/// The valid counterpart: an 8-bit `bswap` whose result is a plain `u8` must
-/// still take the identity-bitcast path and lower cleanly, so the guard above
-/// cannot over-reject the case Rust actually produces for `u8::swap_bytes`.
-#[test]
-fn bswap8_with_a_u8_result_lowers_to_an_identity_bitcast() -> Result<(), anyhow::Error> {
-    use pliron::builtin::types::{IntegerType, Signedness};
-
-    let mut ctx = Context::new();
-    dialect_mir::register(&mut ctx);
-    dialect_nvvm::register(&mut ctx);
-    mir_lower::register(&mut ctx);
-
-    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
-    let module_ptr = build_bswap8_call_module(&mut ctx, u8_ty.into());
-
-    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
-        .expect("an 8-bit bswap with a u8 result must lower");
-
-    // The call must have become a bitcast, not an intrinsic call: there is no
-    // llvm.bswap.i8.
-    let mut found_bitcast = false;
-    let module_block = module_ptr
-        .deref(&ctx)
-        .get_region(0)
-        .deref(&ctx)
-        .iter(&ctx)
-        .next()
-        .unwrap();
-    for op in module_block.deref(&ctx).iter(&ctx) {
-        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
-            continue;
-        };
-        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
-        for func_block in func_region.deref(&ctx).iter(&ctx) {
-            for body_op in func_block.deref(&ctx).iter(&ctx) {
-                assert!(
-                    Operation::get_op::<llvm::CallOp>(body_op, &ctx).is_none(),
-                    "an 8-bit bswap must not lower to an intrinsic call"
-                );
-                if Operation::get_op::<llvm::BitcastOp>(body_op, &ctx).is_some() {
-                    found_bitcast = true;
-                }
-            }
-        }
-    }
-    assert!(
-        found_bitcast,
-        "an 8-bit bswap with a u8 result must lower to an identity bitcast"
-    );
-    Ok(())
-}
diff --git a/crates/mir-lower/tests/lowering_test/atomics_fences.rs b/crates/mir-lower/tests/lowering_test/atomics_fences.rs
new file mode 100644
index 0000000000..367c0d623c
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/atomics_fences.rs
@@ -0,0 +1,799 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_nvvm::ops as nvvm;
+use llvm_export::ops as llvm;
+use pliron::builtin::op_interfaces::{CallOpCallable, CallOpInterface, SymbolOpInterface};
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+use crate::common::{append_return, build_test_kernel, lowered_kernel_body, make_test_ctx};
+
+#[test]
+fn test_packed_atomic_add_lowers_to_exact_side_effecting_ptx() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into()]);
+    let address = entry.deref(&ctx).get_argument(0);
+    let addend = entry.deref(&ctx).get_argument(1);
+
+    for op_info in [
+        nvvm::NvvmAtomAddF16x2Op::get_concrete_op_info(),
+        nvvm::NvvmAtomAddBf16x2Op::get_concrete_op_info(),
+    ] {
+        Operation::new(
+            &mut ctx,
+            op_info,
+            vec![u32_ty.into()],
+            vec![address, addend],
+            vec![],
+            0,
+        )
+        .insert_at_back(entry, &ctx);
+    }
+    for format in [
+        nvvm::PackedAtomicFormatAttr::F16x2,
+        nvvm::PackedAtomicFormatAttr::Bf16x2,
+    ] {
+        nvvm::PackedAtomicAddOp::build(&mut ctx, address, addend, format)
+            .insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let expected = [
+        "atom.global.add.noftz.f16x2 $0, [$1], $2;",
+        "atom.global.add.noftz.bf16x2 $0, [$1], $2;",
+    ];
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    let mut lowered = Vec::new();
+
+    for op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(function) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let body = function.get_operation().deref(&ctx).get_region(0);
+        for block in body.deref(&ctx).iter(&ctx) {
+            for body_op in block.deref(&ctx).iter(&ctx) {
+                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .unwrap_or_default();
+                assert!(
+                    !template.contains("atom.cas"),
+                    "packed atomic exact-native lowering must not use a CAS loop: {template}"
+                );
+                if !template.starts_with("atom.global.add.noftz.") {
+                    continue;
+                }
+                lowered.push((
+                    template,
+                    asm.get_attr_inline_asm_constraints(&ctx)
+                        .map(|value| String::from((*value).clone()))
+                        .unwrap_or_default(),
+                    llvm::asm_kind(&ctx, &asm),
+                    body_op.deref(&ctx).get_num_operands(),
+                    body_op.deref(&ctx).get_num_results(),
+                ));
+            }
+        }
+    }
+
+    assert_eq!(lowered.len(), expected.len() * 2);
+    for instruction in expected {
+        let matches: Vec<_> = lowered
+            .iter()
+            .filter(|(template, _, _, _, _)| template == instruction)
+            .collect();
+        assert_eq!(
+            matches.len(),
+            2,
+            "legacy and generated paths must have exact PTX parity for {instruction}"
+        );
+        for (_, constraints, kind, operands, results) in matches {
+            assert_eq!(constraints, "=r,l,r,~{memory}");
+            assert_eq!(*kind, llvm::AsmKind::SideEffect);
+            assert_eq!(*operands, 2);
+            assert_eq!(*results, 1);
+        }
+    }
+
+    Ok(())
+}
+
+#[test]
+fn test_generated_packed_atomic_add_libnvvm_route_is_exact() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into()]);
+    let address = entry.deref(&ctx).get_argument(0);
+    let addend = entry.deref(&ctx).get_argument(1);
+    for format in [
+        nvvm::PackedAtomicFormatAttr::F16x2,
+        nvvm::PackedAtomicFormatAttr::Bf16x2,
+    ] {
+        nvvm::PackedAtomicAddOp::build(&mut ctx, address, addend, format)
+            .insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: mir_lower::IntrinsicBackend::LibNvvm,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let lowered = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|op| {
+            let asm = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx)?;
+            let template = asm
+                .get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))?;
+            template.starts_with("atom.global.add.noftz.").then(|| {
+                (
+                    template,
+                    asm.get_attr_inline_asm_constraints(&ctx)
+                        .map(|value| String::from((*value).clone())),
+                    llvm::asm_kind(&ctx, &asm),
+                )
+            })
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(lowered.len(), 2);
+    assert!(
+        lowered
+            .iter()
+            .any(|(template, _, _)| { template == "atom.global.add.noftz.f16x2 $0, [$1], $2;" })
+    );
+    assert!(
+        lowered
+            .iter()
+            .any(|(template, _, _)| { template == "atom.global.add.noftz.bf16x2 $0, [$1], $2;" })
+    );
+    for (_, constraints, kind) in lowered {
+        assert_eq!(constraints.as_deref(), Some("=r,l,r,~{memory}"));
+        assert_eq!(kind, llvm::AsmKind::SideEffect);
+    }
+    Ok(())
+}
+
+/// Scoped atomic loads and stores must lower to inline PTX, not to
+/// `load atomic` / `store atomic`.
+///
+/// libNVVM rejects the IR-level form outright ("Atomic loads/stores are not
+/// supported"), so lowering to `llvm::AtomicLoadOp` / `llvm::AtomicStoreOp`
+/// produced modules that no `--materialize-cubin` build could consume, making
+/// every `DeviceAtomic*::load` and `::store` call a build failure. The PTX
+/// instructions themselves have existed since sm_70, so the ops lower through
+/// inline assembly instead.
+///
+/// This asserts the exact template, constraints and asm kind, because all
+/// three are load-bearing: the scope qualifier is the whole point of the
+/// feature, the constraint register class must match the operand width, and
+/// `SideEffect` plus the memory clobber is what stops a publication spin being
+/// hoisted out of its loop.
+#[test]
+fn test_scoped_atomic_load_store_lower_to_inline_ptx() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use dialect_nvvm::ops::atomic::{
+        AtomicOrdering, AtomicScope, NvvmAtomicLoadOp, NvvmAtomicStoreOp,
+    };
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into(), u64_ty.into()]);
+    let address = entry.deref(&ctx).get_argument(0);
+    let val32 = entry.deref(&ctx).get_argument(1);
+    let val64 = entry.deref(&ctx).get_argument(2);
+
+    // One per scope, so a regression that hardcodes a scope is caught rather
+    // than passing on the Device case alone.
+    NvvmAtomicLoadOp::build(
+        &mut ctx,
+        address,
+        u32_ty.into(),
+        AtomicOrdering::Relaxed,
+        AtomicScope::Device,
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    NvvmAtomicLoadOp::build(
+        &mut ctx,
+        address,
+        u32_ty.into(),
+        AtomicOrdering::Acquire,
+        AtomicScope::Block,
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    NvvmAtomicLoadOp::build(
+        &mut ctx,
+        address,
+        u64_ty.into(),
+        AtomicOrdering::Relaxed,
+        AtomicScope::System,
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    NvvmAtomicStoreOp::build(
+        &mut ctx,
+        val32,
+        address,
+        AtomicOrdering::Release,
+        AtomicScope::Device,
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    NvvmAtomicStoreOp::build(
+        &mut ctx,
+        val64,
+        address,
+        AtomicOrdering::Relaxed,
+        AtomicScope::Device,
+    )
+    .get_operation()
+    .insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut lowered = Vec::new();
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(function) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let body = function.get_operation().deref(&ctx).get_region(0);
+        for block in body.deref(&ctx).iter(&ctx) {
+            for body_op in block.deref(&ctx).iter(&ctx) {
+                // The IR-level forms are what libNVVM rejects; neither may survive.
+                assert!(
+                    Operation::get_op::<llvm::AtomicLoadOp>(body_op, &ctx).is_none(),
+                    "scoped atomic load must not lower to `load atomic`: libNVVM rejects it"
+                );
+                assert!(
+                    Operation::get_op::<llvm::AtomicStoreOp>(body_op, &ctx).is_none(),
+                    "scoped atomic store must not lower to `store atomic`: libNVVM rejects it"
+                );
+                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .unwrap_or_default();
+                if !template.starts_with("ld.") && !template.starts_with("st.") {
+                    continue;
+                }
+                lowered.push((
+                    template,
+                    asm.get_attr_inline_asm_constraints(&ctx)
+                        .map(|value| String::from((*value).clone()))
+                        .unwrap_or_default(),
+                    llvm::asm_kind(&ctx, &asm),
+                ));
+            }
+        }
+    }
+
+    // Every access keeps the `~{memory}` clobber, Relaxed included. Without
+    // it LLVM may move plain loads and stores of the same address across the
+    // asm, breaking the single-thread coherence Rust still guarantees for
+    // Relaxed atomics; libcu++ keeps the clobber on its relaxed accesses too.
+    let expected = [
+        ("ld.relaxed.gpu.b32 $0, [$1];", "=r,l,~{memory}"),
+        ("ld.acquire.cta.b32 $0, [$1];", "=r,l,~{memory}"),
+        ("ld.relaxed.sys.b64 $0, [$1];", "=l,l,~{memory}"),
+        ("st.release.gpu.b32 [$0], $1;", "l,r,~{memory}"),
+        ("st.relaxed.gpu.b64 [$0], $1;", "l,l,~{memory}"),
+    ];
+    assert_eq!(
+        lowered.len(),
+        expected.len(),
+        "expected one inline-asm op per scoped atomic load/store, got {lowered:?}"
+    );
+    for (template, constraints) in expected {
+        let found = lowered
+            .iter()
+            .find(|(t, _, _)| t == template)
+            .unwrap_or_else(|| panic!("missing lowering for {template}; got {lowered:?}"));
+        assert_eq!(found.1, constraints, "constraints for {template}");
+        // Not Convergent: these are per-thread accesses, not warp-synchronous.
+        // SideEffect with the memory clobber is what keeps a spin re-reading.
+        assert_eq!(
+            found.2,
+            llvm::AsmKind::SideEffect,
+            "asm kind for {template}"
+        );
+    }
+    Ok(())
+}
+
+/// Orderings a PTX load or store cannot carry must be rejected, not silently
+/// weakened.
+///
+/// Acquire is load-only, Release is store-only, and AcqRel makes no sense on
+/// a single access. Approximating any of them with `relaxed` would be a
+/// correctness bug that no runtime test would catch, because the wrong answer
+/// only appears under contention on hardware that reorders.
+#[test]
+fn test_scoped_atomic_rejects_inexpressible_orderings() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use dialect_nvvm::ops::atomic::{
+        AtomicOrdering, AtomicScope, NvvmAtomicLoadOp, NvvmAtomicStoreOp,
+    };
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    for (is_load, ordering) in [
+        (true, AtomicOrdering::Release), // release is store-only
+        (true, AtomicOrdering::AcqRel),
+        (false, AtomicOrdering::Acquire), // acquire is load-only
+        (false, AtomicOrdering::AcqRel),
+    ] {
+        let mut ctx = make_test_ctx();
+        let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+        let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
+        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into()]);
+        let address = entry.deref(&ctx).get_argument(0);
+        let val = entry.deref(&ctx).get_argument(1);
+
+        if is_load {
+            NvvmAtomicLoadOp::build(
+                &mut ctx,
+                address,
+                u32_ty.into(),
+                ordering.clone(),
+                AtomicScope::Device,
+            )
+            .get_operation()
+            .insert_at_back(entry, &ctx);
+        } else {
+            NvvmAtomicStoreOp::build(
+                &mut ctx,
+                val,
+                address,
+                ordering.clone(),
+                AtomicScope::Device,
+            )
+            .get_operation()
+            .insert_at_back(entry, &ctx);
+        }
+        append_return(&mut ctx, entry);
+
+        let result = mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr);
+        assert!(
+            result.is_err(),
+            "{} with {ordering:?} ordering must be rejected, not approximated",
+            if is_load { "load" } else { "store" }
+        );
+    }
+    Ok(())
+}
+
+/// SeqCst load and store lower to one asm op whose template fuses the
+/// `fence.sc` with the access, at every scope.
+///
+/// PTX has no sequentially consistent load or store instruction. libcu++ maps
+/// a SeqCst load to `fence.sc.{scope}` followed by an acquire load at the
+/// same scope, and a SeqCst store to `fence.sc.{scope}` followed by a release
+/// store. Fusing the fence into the same template keeps the pair inseparable.
+#[test]
+fn test_seqcst_atomic_load_store_fuse_fence_into_template() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use dialect_nvvm::ops::atomic::{
+        AtomicOrdering, AtomicScope, NvvmAtomicLoadOp, NvvmAtomicStoreOp,
+    };
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    for (scope, ptx) in [
+        (AtomicScope::Device, "gpu"),
+        (AtomicScope::Block, "cta"),
+        (AtomicScope::System, "sys"),
+    ] {
+        let mut ctx = make_test_ctx();
+        let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+        let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
+        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into()]);
+        let address = entry.deref(&ctx).get_argument(0);
+        let val = entry.deref(&ctx).get_argument(1);
+
+        NvvmAtomicLoadOp::build(
+            &mut ctx,
+            address,
+            u32_ty.into(),
+            AtomicOrdering::SeqCst,
+            scope.clone(),
+        )
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+        NvvmAtomicStoreOp::build(&mut ctx, val, address, AtomicOrdering::SeqCst, scope)
+            .get_operation()
+            .insert_at_back(entry, &ctx);
+        append_return(&mut ctx, entry);
+
+        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+            .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+        let mut lowered = Vec::new();
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+                continue;
+            };
+            lowered.push((
+                asm.get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .unwrap_or_default(),
+                asm.get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .unwrap_or_default(),
+            ));
+        }
+        let expected = vec![
+            (
+                format!("fence.sc.{ptx}; ld.acquire.{ptx}.b32 $0, [$1];"),
+                "=r,l,~{memory}".to_string(),
+            ),
+            (
+                format!("fence.sc.{ptx}; st.release.{ptx}.b32 [$0], $1;"),
+                "l,r,~{memory}".to_string(),
+            ),
+        ];
+        assert_eq!(lowered, expected, "SeqCst lowering at scope {ptx}");
+    }
+    Ok(())
+}
+
+/// Float atomic loads and stores travel through integer registers with an
+/// LLVM-level bitcast on each side.
+///
+/// The register classes in the constraints are integer (`h`/`r`/`l`), so
+/// handing llc a float-typed asm operand or result is a constraint mismatch.
+/// The store bitcasts the float to the same-width integer before the asm; the
+/// load returns the integer and bitcasts it back to the float type. The f16
+/// case also covers the `b16`/`h` arm end to end, which is what makes
+/// `DeviceAtomicF16::load`/`store` compile at all.
+#[test]
+fn test_float_atomic_load_store_bitcast_through_integer_registers() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::{MirFP16Type, MirPtrType};
+    use dialect_nvvm::ops::atomic::{
+        AtomicOrdering, AtomicScope, NvvmAtomicLoadOp, NvvmAtomicStoreOp,
+    };
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::types::{FP32Type, IntegerType};
+    use pliron::r#type::Typed;
+
+    let is_expected_float = |ctx: &Context, ty: pliron::r#type::TypeHandle, width: u32| -> bool {
+        let ty_ref = ty.deref(ctx);
+        match width {
+            16 => ty_ref.is::<llvm_types::HalfType>(),
+            32 => ty_ref.is::<FP32Type>(),
+            _ => false,
+        }
+    };
+    let integer_width_of = |ctx: &Context, ty: pliron::r#type::TypeHandle| -> Option<u32> {
+        ty.deref(ctx)
+            .downcast_ref::<IntegerType>()
+            .map(IntegerType::width)
+    };
+
+    for (is_f16, ptx_ty, reg, width) in [(false, "b32", "r", 32u32), (true, "b16", "h", 16u32)] {
+        let mut ctx = make_test_ctx();
+        let elem_ty: pliron::r#type::TypeHandle = if is_f16 {
+            MirFP16Type::get(&ctx).into()
+        } else {
+            FP32Type::get(&ctx).into()
+        };
+        let ptr_ty = MirPtrType::get_generic(&mut ctx, elem_ty, true);
+        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), elem_ty]);
+        let address = entry.deref(&ctx).get_argument(0);
+        let val = entry.deref(&ctx).get_argument(1);
+
+        NvvmAtomicLoadOp::build(
+            &mut ctx,
+            address,
+            elem_ty,
+            AtomicOrdering::Relaxed,
+            AtomicScope::Device,
+        )
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+        NvvmAtomicStoreOp::build(
+            &mut ctx,
+            val,
+            address,
+            AtomicOrdering::Relaxed,
+            AtomicScope::Device,
+        )
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+        append_return(&mut ctx, entry);
+
+        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+            .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+        let mut ld_asm = None;
+        let mut st_asm = None;
+        let mut bitcasts = Vec::new();
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            if let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
+                let template = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .unwrap_or_default();
+                let constraints = asm
+                    .get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .unwrap_or_default();
+                if template.starts_with("ld.") {
+                    ld_asm = Some((op, template, constraints));
+                } else if template.starts_with("st.") {
+                    st_asm = Some((op, template, constraints));
+                }
+            }
+            if Operation::get_op::<llvm::BitcastOp>(op, &ctx).is_some() {
+                bitcasts.push(op);
+            }
+        }
+
+        // Load direction: asm produces the staging integer, then one bitcast
+        // turns it back into the float.
+        let (ld_op, ld_template, ld_constraints) =
+            ld_asm.expect("float atomic load must lower to inline asm");
+        assert_eq!(ld_template, format!("ld.relaxed.gpu.{ptx_ty} $0, [$1];"));
+        assert_eq!(ld_constraints, format!("={reg},l,~{{memory}}"));
+        let ld_result = ld_op.deref(&ctx).get_result(0);
+        assert_eq!(
+            integer_width_of(&ctx, ld_result.get_type(&ctx)),
+            Some(width),
+            "load asm must produce the staging integer, not the float"
+        );
+        let load_cast = bitcasts
+            .iter()
+            .copied()
+            .find(|&cast| cast.deref(&ctx).get_operand(0) == ld_result)
+            .expect("load asm result must be bitcast back to the float type");
+        let load_cast_ty = load_cast.deref(&ctx).get_result(0).get_type(&ctx);
+        assert!(
+            is_expected_float(&ctx, load_cast_ty, width),
+            "load bitcast must produce the float type"
+        );
+
+        // Store direction: the float is bitcast to the staging integer, and
+        // that integer is what the asm consumes.
+        let (st_op, st_template, st_constraints) =
+            st_asm.expect("float atomic store must lower to inline asm");
+        assert_eq!(st_template, format!("st.relaxed.gpu.{ptx_ty} [$0], $1;"));
+        assert_eq!(st_constraints, format!("l,{reg},~{{memory}}"));
+        let stored = st_op.deref(&ctx).get_operand(1);
+        assert_eq!(
+            integer_width_of(&ctx, stored.get_type(&ctx)),
+            Some(width),
+            "store asm must consume the staging integer, not the float"
+        );
+        let store_cast = bitcasts
+            .iter()
+            .copied()
+            .find(|&cast| cast.deref(&ctx).get_result(0) == stored)
+            .expect("store asm value must come from a float-to-integer bitcast");
+        let store_src_ty = store_cast.deref(&ctx).get_operand(0).get_type(&ctx);
+        assert!(
+            is_expected_float(&ctx, store_src_ty, width),
+            "store bitcast must consume the float type"
+        );
+    }
+    Ok(())
+}
+
+/// A SeqCst fence must go through the typed NVVM intrinsic, and a weaker one
+/// through inline PTX.
+///
+/// PTX defines `membar.level` as a synonym for `fence.sc.level`, so
+/// `llvm.nvvm.membar.{cta,gl,sys}` is an exact match for SeqCst and is the route
+/// the rest of the crate already uses for fences. No intrinsic exists for a
+/// weaker fence, and emitting `membar` for AcqRel would silently upgrade the
+/// caller's request to sequential consistency, so that case emits
+/// `fence.acq_rel.{scope}` directly.
+#[test]
+fn test_fence_uses_membar_intrinsic_only_for_seqcst() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use dialect_nvvm::ops::atomic::{AtomicOrdering, AtomicRmwKind, AtomicScope, NvvmAtomicRmwOp};
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    for (ordering, want_intrinsic, want_asm) in [
+        (AtomicOrdering::SeqCst, Some("llvm_nvvm_membar_gl"), None),
+        (AtomicOrdering::AcqRel, None, Some("fence.acq_rel.gpu;")),
+    ] {
+        let mut ctx = make_test_ctx();
+        let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+        let ptr_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
+        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into(), u32_ty.into()]);
+        let address = entry.deref(&ctx).get_argument(0);
+        let addend = entry.deref(&ctx).get_argument(1);
+
+        NvvmAtomicRmwOp::build(
+            &mut ctx,
+            address,
+            addend,
+            u32_ty.into(),
+            AtomicRmwKind::Add,
+            ordering.clone(),
+            AtomicScope::Device,
+        )
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+        append_return(&mut ctx, entry);
+
+        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+            .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+        let mut saw_intrinsic = false;
+        let mut saw_asm = None;
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+                && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+                && callee.to_string().contains("membar")
+            {
+                saw_intrinsic = true;
+            }
+            if let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
+                let t = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|v| String::from((*v).clone()))
+                    .unwrap_or_default();
+                if t.starts_with("fence.") {
+                    saw_asm = Some(t);
+                }
+            }
+        }
+        assert_eq!(
+            saw_intrinsic,
+            want_intrinsic.is_some(),
+            "{ordering:?}: membar intrinsic presence"
+        );
+        assert_eq!(saw_asm.as_deref(), want_asm, "{ordering:?}: inline fence");
+        // A SeqCst fence must never also emit `membar` as assembly: that would
+        // mean both routes fired.
+        if want_intrinsic.is_some() {
+            assert!(saw_asm.is_none(), "{ordering:?}: emitted both routes");
+        }
+    }
+    Ok(())
+}
+
+/// A first-class atomic fence must lower through the same libNVVM-safe routes
+/// used by the RMW ordering workaround.
+///
+/// `core::sync::atomic::fence` imports with system scope, so the source-level
+/// path depends on this exact mapping: Acquire/Release/AcqRel become
+/// `fence.acq_rel.sys`, while SeqCst becomes `llvm.nvvm.membar.sys`.
+#[test]
+fn test_first_class_atomic_fence_lowers_at_system_scope() -> Result<(), anyhow::Error> {
+    use dialect_nvvm::ops::atomic::{AtomicOrdering, AtomicScope, NvvmAtomicFenceOp};
+
+    for ordering in [
+        AtomicOrdering::Acquire,
+        AtomicOrdering::Release,
+        AtomicOrdering::AcqRel,
+        AtomicOrdering::SeqCst,
+    ] {
+        let mut ctx = make_test_ctx();
+        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
+
+        NvvmAtomicFenceOp::build(&mut ctx, ordering.clone(), AtomicScope::System)
+            .get_operation()
+            .insert_at_back(entry, &ctx);
+        append_return(&mut ctx, entry);
+
+        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+            .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+        let mut membar_calls = 0usize;
+        let mut fence_asm = Vec::new();
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            assert!(
+                Operation::get_op::<NvvmAtomicFenceOp>(op, &ctx).is_none(),
+                "first-class atomic fence must be fully consumed by lowering"
+            );
+
+            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+                && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+                && callee.to_string() == "llvm_nvvm_membar_sys"
+            {
+                membar_calls += 1;
+            }
+
+            let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+                continue;
+            };
+            let template = asm
+                .get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .unwrap_or_default();
+            if template.starts_with("fence.") {
+                assert_eq!(
+                    asm.get_attr_inline_asm_constraints(&ctx)
+                        .map(|value| String::from((*value).clone()))
+                        .as_deref(),
+                    Some("~{memory}")
+                );
+                assert_eq!(llvm::asm_kind(&ctx, &asm), llvm::AsmKind::SideEffect);
+                fence_asm.push(template);
+            }
+        }
+
+        match ordering {
+            AtomicOrdering::SeqCst => {
+                assert_eq!(membar_calls, 1, "SeqCst must use membar.sys");
+                assert!(
+                    fence_asm.is_empty(),
+                    "SeqCst must not also emit an inline PTX fence"
+                );
+            }
+            AtomicOrdering::Acquire | AtomicOrdering::Release | AtomicOrdering::AcqRel => {
+                assert_eq!(membar_calls, 0, "weak fences must not use membar.sys");
+                assert_eq!(
+                    fence_asm,
+                    vec!["fence.acq_rel.sys;".to_owned()],
+                    "{ordering:?} must lower to one system-scope acq_rel fence"
+                );
+            }
+            AtomicOrdering::Relaxed => unreachable!("Relaxed is not a valid Rust fence ordering"),
+        }
+    }
+
+    Ok(())
+}
+
+#[test]
+fn test_first_class_atomic_fence_rejects_relaxed() -> Result<(), anyhow::Error> {
+    use dialect_nvvm::ops::atomic::{AtomicOrdering, AtomicScope, NvvmAtomicFenceOp};
+
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
+    NvvmAtomicFenceOp::build(&mut ctx, AtomicOrdering::Relaxed, AtomicScope::System)
+        .get_operation()
+        .insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    let result = mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr);
+    assert!(
+        result.is_err(),
+        "Relaxed is not a valid atomic fence ordering and must be rejected"
+    );
+    Ok(())
+}
diff --git a/crates/mir-lower/tests/lowering_test/barriers_sync.rs b/crates/mir-lower/tests/lowering_test/barriers_sync.rs
new file mode 100644
index 0000000000..e0d797e53d
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/barriers_sync.rs
@@ -0,0 +1,743 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_nvvm::ops as nvvm;
+use llvm_export::ops as llvm;
+use pliron::builtin::op_interfaces::{CallOpCallable, CallOpInterface, SymbolOpInterface};
+use pliron::builtin::ops::ModuleOp;
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+use crate::common::{append_return, build_test_kernel, lowered_kernel_body, make_test_ctx};
+
+fn lower_basic_mbarrier(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let bar_ptr_ty = MirPtrType::get_shared(&mut ctx, u64_ty.into(), false);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![bar_ptr_ty.into(), u32_ty.into()]);
+    let barrier = entry.deref(&ctx).get_argument(0);
+    let count = entry.deref(&ctx).get_argument(1);
+
+    nvvm::MbarrierInitSharedOp::build(&mut ctx, barrier, count).insert_at_back(entry, &ctx);
+    let arrive = nvvm::MbarrierArriveSharedOp::build(&mut ctx, barrier);
+    let token = arrive.deref(&ctx).get_result(0);
+    arrive.insert_at_back(entry, &ctx);
+    nvvm::MbarrierTestWaitSharedOp::build(&mut ctx, barrier, token).insert_at_back(entry, &ctx);
+    nvvm::MbarrierInvalSharedOp::build(&mut ctx, barrier).insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn test_generated_basic_mbarrier_uses_shared_lowering_on_both_backends() -> Result<(), anyhow::Error>
+{
+    let expected_calls = [
+        ("llvm_nvvm_mbarrier_init_shared", 2),
+        ("llvm_nvvm_mbarrier_arrive_shared", 1),
+        ("llvm_nvvm_mbarrier_inval_shared", 1),
+    ];
+    let init_template = "mbarrier.init.shared.b64 [$0], $1;";
+    let arrive_template = "mbarrier.arrive.shared.b64 $0, [$1];";
+    let test_wait_template =
+        "{ .reg .pred %p0; mbarrier.test_wait.shared.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }";
+    let inval_template = "mbarrier.inval.shared.b64 [$0];";
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        let (ctx, module_ptr) = lower_basic_mbarrier(backend)?;
+        let mut call_counts = [0usize; 3];
+        let expected_asm = match backend {
+            mir_lower::IntrinsicBackend::LlvmNvptx => {
+                vec![(test_wait_template, "=r,l,l,~{memory}", 2)]
+            }
+            mir_lower::IntrinsicBackend::LibNvvm => vec![
+                (init_template, "l,r,~{memory}", 2),
+                (arrive_template, "=l,l,~{memory}", 1),
+                (test_wait_template, "=r,l,l,~{memory}", 2),
+                (inval_template, "l,~{memory}", 1),
+            ],
+        };
+        let mut asm_counts = vec![0usize; expected_asm.len()];
+        let mut trunc_count = 0;
+
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) {
+                let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+                    continue;
+                };
+                let callee = callee.to_string();
+                let Some(index) = expected_calls
+                    .iter()
+                    .position(|(expected, _)| callee == *expected)
+                else {
+                    assert_ne!(callee, "llvm_nvvm_mbarrier_test_wait_shared");
+                    continue;
+                };
+                call_counts[index] += 1;
+                assert_eq!(op.deref(&ctx).get_num_operands(), expected_calls[index].1);
+            }
+
+            if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
+                let template = inline_asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                let index = expected_asm
+                    .iter()
+                    .position(|(expected, _, _)| template.as_deref() == Some(*expected))
+                    .unwrap_or_else(|| panic!("unexpected {backend:?} inline PTX: {template:?}"));
+                let (_, constraints, operand_count) = expected_asm[index];
+                asm_counts[index] += 1;
+                assert_eq!(
+                    inline_asm
+                        .get_attr_inline_asm_constraints(&ctx)
+                        .map(|value| String::from((*value).clone()))
+                        .as_deref(),
+                    Some(constraints)
+                );
+                assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Convergent);
+                let asm = op.deref(&ctx);
+                assert_eq!(asm.get_num_operands(), operand_count);
+                assert_eq!(asm.get_num_results(), 1);
+            }
+
+            if Operation::get_op::<llvm::TruncOp>(op, &ctx).is_some() {
+                trunc_count += 1;
+            }
+        }
+
+        match backend {
+            mir_lower::IntrinsicBackend::LlvmNvptx => assert_eq!(call_counts, [1; 3]),
+            mir_lower::IntrinsicBackend::LibNvvm => assert_eq!(call_counts, [0; 3]),
+        }
+        assert_eq!(asm_counts, vec![1; expected_asm.len()]);
+        assert_eq!(
+            trunc_count, 1,
+            "test-wait must adapt its i32 predicate to i1"
+        );
+
+        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+            .map_err(|error| anyhow::anyhow!(error))?;
+        match backend {
+            mir_lower::IntrinsicBackend::LlvmNvptx => {
+                assert!(
+                    ir.contains("call void @llvm.nvvm.mbarrier.init.shared(ptr addrspace(3)"),
+                    "{ir}"
+                );
+                assert!(
+                    ir.contains("call i64 @llvm.nvvm.mbarrier.arrive.shared(ptr addrspace(3)"),
+                    "{ir}"
+                );
+                assert!(
+                    ir.contains("call void @llvm.nvvm.mbarrier.inval.shared(ptr addrspace(3)"),
+                    "{ir}"
+                );
+                assert!(!ir.contains(init_template), "{ir}");
+                assert!(!ir.contains(arrive_template), "{ir}");
+                assert!(!ir.contains(inval_template), "{ir}");
+            }
+            mir_lower::IntrinsicBackend::LibNvvm => {
+                for symbol in [
+                    "@llvm.nvvm.mbarrier.init.shared",
+                    "@llvm.nvvm.mbarrier.arrive.shared",
+                    "@llvm.nvvm.mbarrier.inval.shared",
+                ] {
+                    assert!(
+                        !ir.contains(symbol),
+                        "libNVVM route retained {symbol}:\n{ir}"
+                    );
+                }
+                for template in [init_template, arrive_template, inval_template] {
+                    assert!(ir.contains(template), "{ir}");
+                }
+            }
+        }
+        assert!(ir.contains(test_wait_template), "{ir}");
+        assert!(ir.contains("asm sideeffect"), "{ir}");
+        assert!(ir.contains("trunc i32") && ir.contains("to i1"), "{ir}");
+        assert!(ir.contains("attributes #0 = { convergent }"), "{ir}");
+    }
+    Ok(())
+}
+
+fn lower_cluster_barriers(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
+    for mode in [
+        nvvm::ClusterBarrierModeAttr::Arrive,
+        nvvm::ClusterBarrierModeAttr::ArriveAligned,
+        nvvm::ClusterBarrierModeAttr::ArriveRelaxed,
+        nvvm::ClusterBarrierModeAttr::ArriveRelaxedAligned,
+        nvvm::ClusterBarrierModeAttr::Wait,
+        nvvm::ClusterBarrierModeAttr::WaitAligned,
+    ] {
+        nvvm::ClusterBarrierOp::build(&mut ctx, mode).insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn generated_cluster_barriers_lower_exactly_on_both_backends() -> Result<(), anyhow::Error> {
+    let recipes = [
+        (
+            "llvm_nvvm_barrier_cluster_arrive",
+            "barrier.cluster.arrive;",
+        ),
+        (
+            "llvm_nvvm_barrier_cluster_arrive_aligned",
+            "barrier.cluster.arrive.aligned;",
+        ),
+        (
+            "llvm_nvvm_barrier_cluster_arrive_relaxed",
+            "barrier.cluster.arrive.relaxed;",
+        ),
+        (
+            "llvm_nvvm_barrier_cluster_arrive_relaxed_aligned",
+            "barrier.cluster.arrive.relaxed.aligned;",
+        ),
+        ("llvm_nvvm_barrier_cluster_wait", "barrier.cluster.wait;"),
+        (
+            "llvm_nvvm_barrier_cluster_wait_aligned",
+            "barrier.cluster.wait.aligned;",
+        ),
+    ];
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        let (ctx, module_ptr) = lower_cluster_barriers(backend)?;
+        let mut calls = [0usize; 6];
+        let mut asm = [0usize; 6];
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) {
+                let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+                    continue;
+                };
+                if let Some(index) = recipes
+                    .iter()
+                    .position(|(symbol, _)| callee.to_string() == *symbol)
+                {
+                    calls[index] += 1;
+                }
+            }
+            if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
+                let template = inline_asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                if let Some(index) = recipes
+                    .iter()
+                    .position(|(_, expected)| template.as_deref() == Some(*expected))
+                {
+                    asm[index] += 1;
+                    assert_eq!(
+                        inline_asm
+                            .get_attr_inline_asm_constraints(&ctx)
+                            .map(|value| String::from((*value).clone()))
+                            .as_deref(),
+                        Some("~{memory}")
+                    );
+                    assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Convergent);
+                }
+            }
+        }
+        match backend {
+            mir_lower::IntrinsicBackend::LlvmNvptx => {
+                assert_eq!(calls, [1; 6]);
+                assert_eq!(asm, [0; 6]);
+            }
+            mir_lower::IntrinsicBackend::LibNvvm => {
+                assert_eq!(calls, [0; 6]);
+                assert_eq!(asm, [1; 6]);
+            }
+        }
+    }
+    Ok(())
+}
+
+#[test]
+fn test_cluster_mbarrier_and_fences_lower_to_exact_inline_ptx() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let bar_ptr_ty = MirPtrType::get_shared(&mut ctx, i64_ty.into(), false);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![bar_ptr_ty.into(), i32_ty.into()]);
+
+    let bar_ptr = entry.deref(&ctx).get_argument(0);
+    let bytes_or_parity = entry.deref(&ctx).get_argument(1);
+
+    let arrive = Operation::new(
+        &mut ctx,
+        nvvm::MbarrierArriveExpectTxClusterOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![bar_ptr, bytes_or_parity],
+        vec![],
+        0,
+    );
+    arrive.insert_at_back(entry, &ctx);
+
+    let try_wait = Operation::new(
+        &mut ctx,
+        nvvm::MbarrierTryWaitParityClusterOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![bar_ptr, bytes_or_parity],
+        vec![],
+        0,
+    );
+    try_wait.insert_at_back(entry, &ctx);
+
+    let mbarrier_fence = Operation::new(
+        &mut ctx,
+        nvvm::FenceMbarrierInitReleaseClusterOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    mbarrier_fence.insert_at_back(entry, &ctx);
+
+    let proxy_release_fence = Operation::new(
+        &mut ctx,
+        nvvm::FenceProxyAsyncGenericReleaseSharedCtaClusterOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    proxy_release_fence.insert_at_back(entry, &ctx);
+
+    let proxy_acquire_fence = Operation::new(
+        &mut ctx,
+        nvvm::FenceProxyAsyncGenericAcquireSharedClusterClusterOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    proxy_acquire_fence.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let expected = [
+        (
+            "mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 $0, [$1], $2;",
+            "=l,l,r,~{memory}",
+        ),
+        (
+            "{ .reg .pred %p0; mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64 %p0, [$1], $2; selp.b32 $0, 1, 0, %p0; }",
+            "=r,l,r,~{memory}",
+        ),
+        ("fence.mbarrier_init.release.cluster;", "~{memory}"),
+        (
+            "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;",
+            "~{memory}",
+        ),
+        (
+            "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;",
+            "~{memory}",
+        ),
+    ];
+    let mut matches = [0usize; 5];
+
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = inline_asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                let Some(index) = expected.iter().position(|(expected_template, _)| {
+                    template.as_deref() == Some(*expected_template)
+                }) else {
+                    continue;
+                };
+
+                matches[index] += 1;
+                assert_eq!(
+                    inline_asm
+                        .get_attr_inline_asm_constraints(&ctx)
+                        .map(|value| String::from((*value).clone()))
+                        .as_deref(),
+                    Some(expected[index].1)
+                );
+                assert_eq!(
+                    llvm::asm_kind_opt(&ctx, &inline_asm),
+                    Some(llvm::AsmKind::Convergent)
+                );
+            }
+        }
+    }
+
+    assert_eq!(
+        matches, [1; 5],
+        "each cluster barrier/fence must lower to its exact PTX template once"
+    );
+    Ok(())
+}
+
+/// The mir-importer encodes `core::sync::atomic::compiler_fence` (issue #781)
+/// as an empty, volatile, non-convergent inline-PTX block whose only content
+/// is a `~{memory}` clobber. It must lower to a void side-effecting inline asm
+/// call with the clobber intact and no instruction text, so no hardware
+/// `fence` or `membar` can reach the emitted PTX.
+#[test]
+fn test_compiler_fence_encoding_lowers_to_empty_sideeffect_asm() -> Result<(), anyhow::Error> {
+    use llvm_export::types as llvm_types;
+    use pliron::r#type::Typed;
+
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
+
+    let barrier = nvvm::InlinePtxOp::build(&mut ctx, vec![], vec![], "", "~{memory}", true, false);
+    barrier.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    let mut found_barrier = false;
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            continue;
+        };
+        assert!(
+            !found_barrier,
+            "expected exactly one inline asm op in the lowered kernel"
+        );
+        found_barrier = true;
+
+        let template = inline_asm
+            .get_attr_inline_asm_template(&ctx)
+            .map(|s| String::from((*s).clone()));
+        assert_eq!(
+            template.as_deref(),
+            Some(""),
+            "compiler fence must emit no PTX instruction"
+        );
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_constraints(&ctx)
+                .map(|s| String::from((*s).clone()))
+                .as_deref(),
+            Some("~{memory}"),
+            "compiler fence must keep its memory clobber"
+        );
+        assert!(
+            llvm::inline_asm_sideeffect(&ctx, inline_asm.get_operation()),
+            "compiler fence must stay side-effecting so the optimizer cannot drop it"
+        );
+        assert!(
+            inline_asm
+                .get_attr_inline_asm_convergent(&ctx)
+                .is_some_and(|b| !bool::from((*b).clone())),
+            "compiler fence must not be convergent"
+        );
+        // The zero-result lowering path models the void call as a single
+        // result of `llvm.void` type, so assert on the type rather than on
+        // the result count.
+        let result_ty = inline_asm
+            .get_operation()
+            .deref(&ctx)
+            .get_result(0)
+            .get_type(&ctx);
+        assert!(
+            result_ty
+                .deref(&ctx)
+                .downcast_ref::<llvm_types::VoidType>()
+                .is_some(),
+            "compiler fence lowers to a void inline asm call"
+        );
+    }
+
+    assert!(
+        found_barrier,
+        "expected the compiler-fence inline asm op in the lowered kernel"
+    );
+    Ok(())
+}
+
+#[test]
+fn test_cluster_grid_compatibility_ops_keep_original_lowering() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_type = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
+    for op_info in [
+        nvvm::ReadPtxSregClusterIdxOp::get_concrete_op_info(),
+        nvvm::ReadPtxSregNclusterIdOp::get_concrete_op_info(),
+    ] {
+        Operation::new(&mut ctx, op_info, vec![i32_type.into()], vec![], vec![], 0)
+            .insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let lowered = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(op, &ctx))
+        .filter_map(|asm| {
+            let template = asm
+                .get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))?;
+            (template.contains("%clusterid") || template.contains("%nclusterid"))
+                .then_some((template, asm))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(lowered.len(), 2);
+    assert!(lowered.iter().any(|(template, _)| {
+        template
+            == "{ .reg .u32 %cx, %cy, %cz, %nx, %ny, %nxy, %xy; mov.u32 %cx, %clusterid.x; mov.u32 %cy, %clusterid.y; mov.u32 %cz, %clusterid.z; mov.u32 %nx, %nclusterid.x; mov.u32 %ny, %nclusterid.y; mul.lo.u32 %nxy, %nx, %ny; mad.lo.u32 %xy, %cy, %nx, %cx; mad.lo.u32 $0, %cz, %nxy, %xy; }"
+    }));
+    assert!(lowered.iter().any(|(template, _)| {
+        template
+            == "{ .reg .u32 %nx, %ny, %nz, %nxy; mov.u32 %nx, %nclusterid.x; mov.u32 %ny, %nclusterid.y; mov.u32 %nz, %nclusterid.z; mul.lo.u32 %nxy, %nx, %ny; mul.lo.u32 $0, %nxy, %nz; }"
+    }));
+    for (_, asm) in lowered {
+        assert_eq!(
+            asm.get_attr_inline_asm_constraints(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some("=r")
+        );
+        assert_eq!(llvm::asm_kind(&ctx, &asm), llvm::AsmKind::Convergent);
+    }
+    Ok(())
+}
+
+fn lower_sync_threads(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
+    Operation::new(
+        &mut ctx,
+        nvvm::Barrier0Op::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    )
+    .insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn test_sync_threads_llvm_nvptx_uses_typed_intrinsic_with_fixed_zero() -> Result<(), anyhow::Error>
+{
+    use pliron::builtin::attributes::IntegerAttr;
+
+    let (ctx, module_ptr) = lower_sync_threads(mir_lower::IntrinsicBackend::LlvmNvptx)?;
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let mut found = false;
+    for op in body {
+        assert!(
+            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+            "LLVM-NVPTX sync_threads must use the typed intrinsic"
+        );
+        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+            continue;
+        };
+        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+            continue;
+        };
+        if callee.to_string() != "llvm_nvvm_barrier_cta_sync_aligned_all" {
+            continue;
+        }
+        let call = op.deref(&ctx);
+        assert_eq!(call.get_num_operands(), 1);
+        let barrier_id = call.get_operand(0);
+        let defining_op = barrier_id.defining_op().expect("barrier ID is constant");
+        let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
+            .expect("barrier ID is an LLVM constant");
+        let value = constant.get_value(&ctx);
+        let integer = value
+            .downcast_ref::<IntegerAttr>()
+            .expect("barrier ID is an integer");
+        assert_eq!(integer.value().bw(), 32);
+        assert_eq!(integer.value().to_u64(), 0);
+        found = true;
+    }
+    assert!(found, "modern typed CTA barrier call was not emitted");
+
+    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+        .map_err(|error| anyhow::anyhow!(error))?;
+    assert!(ir.contains("@llvm.nvvm.barrier.cta.sync.aligned.all(i32 0)"));
+    assert!(!ir.contains("@llvm.nvvm.barrier0"));
+    Ok(())
+}
+
+#[test]
+fn test_sync_threads_libnvvm_uses_exact_convergent_inline_ptx() -> Result<(), anyhow::Error> {
+    let (ctx, module_ptr) = lower_sync_threads(mir_lower::IntrinsicBackend::LibNvvm)?;
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let mut found = false;
+    for op in body {
+        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+                && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+            {
+                assert_ne!(callee.to_string(), "llvm_nvvm_barrier_cta_sync_aligned_all");
+            }
+            continue;
+        };
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some("bar.sync 0;")
+        );
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_constraints(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some("~{memory}")
+        );
+        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Convergent);
+        assert_eq!(op.deref(&ctx).get_num_operands(), 0);
+        found = true;
+    }
+    assert!(found, "exact libNVVM barrier inline PTX was not emitted");
+
+    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+        .map_err(|error| anyhow::anyhow!(error))?;
+    assert!(
+        ir.contains("call void asm sideeffect \"bar.sync 0;\", \"~{memory}\"() #0"),
+        "{ir}"
+    );
+    assert!(ir.contains("attributes #0 = { convergent }"), "{ir}");
+    assert!(!ir.contains("@llvm.nvvm.barrier.cta.sync.aligned.all"));
+    Ok(())
+}
+
+fn lower_warp_barrier(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
+    let member_mask = entry.deref(&ctx).get_argument(0);
+    nvvm::BarWarpSyncOp::build(&mut ctx, member_mask).insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn test_warp_barrier_uses_typed_intrinsic_on_both_backends() -> Result<(), anyhow::Error> {
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        let (ctx, module_ptr) = lower_warp_barrier(backend)?;
+        let body = lowered_kernel_body(&ctx, module_ptr);
+        let mut calls = 0;
+        for op in body {
+            assert!(
+                Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+                "warp barrier must use its typed intrinsic"
+            );
+            let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+                continue;
+            };
+            let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+                continue;
+            };
+            if callee.to_string() == "llvm_nvvm_bar_warp_sync" {
+                assert_eq!(op.deref(&ctx).get_num_operands(), 1);
+                assert_eq!(op.deref(&ctx).get_num_results(), 1);
+                calls += 1;
+            }
+        }
+        assert_eq!(calls, 1, "expected one typed warp-barrier call");
+
+        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+            .map_err(|error| anyhow::anyhow!(error))?;
+        assert!(ir.contains("@llvm.nvvm.bar.warp.sync(i32"), "{ir}");
+    }
+    Ok(())
+}
+
+// =============================================================================
+// cp.async lowering tests
+// =============================================================================
diff --git a/crates/mir-lower/tests/lowering_test/calls_and_values.rs b/crates/mir-lower/tests/lowering_test/calls_and_values.rs
new file mode 100644
index 0000000000..ba83feab64
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/calls_and_values.rs
@@ -0,0 +1,897 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::ops as mir;
+use llvm_export::ops as llvm;
+use pliron::builtin::op_interfaces::{CallOpCallable, CallOpInterface, SymbolOpInterface};
+use pliron::builtin::ops::ModuleOp;
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+/// Regression cover for explicit MIR address-space coercion before a call.
+///
+/// When a caller passes a pointer in one address space to a callee whose
+/// declared parameter lives in a different address space (the
+/// `*mut SharedArray<T, N>` / `addrspace(3)` case that surfaces from
+/// `block_reduce` and friends), MIR must record the representational cast
+/// before the exact call-signature verifier sees the argument. Lowering then
+/// emits the corresponding `llvm.addrspacecast`.
+///
+/// This test builds two MIR functions in one module:
+///   - `callee(p: *mut i32 in addrspace(3))`
+///   - `caller(p: *mut i32 in addrspace(0)) { callee(p) }`
+///
+/// and asserts the lowered `caller` body contains an `AddrSpaceCastOp`.
+#[test]
+fn addrspace_coercion_inserts_addrspacecast_at_call_site() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use llvm_export::ops::AddrSpaceCastOp;
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::attributes::{StringAttr, TypeAttr};
+    use pliron::builtin::types::{FunctionType, IntegerType, Signedness};
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let module = ModuleOp::new(&mut ctx, "test_addrspace_coercion".try_into().unwrap());
+    let module_ptr = module.get_operation();
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let shared_ptr_ty = MirPtrType::get_shared(&mut ctx, i32_ty.into(), true);
+    let generic_ptr_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let expected_call_location = Location::Named {
+        name: "source-device-call".to_string(),
+        child_loc: Box::new(Location::Unknown),
+    };
+
+    // Callee: takes a *mut i32 in addrspace(3), returns ().
+    let callee_func_ty = FunctionType::get(&ctx, vec![shared_ptr_ty.into()], vec![]);
+    let callee_func_op = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let callee_func = mir::MirFuncOp::new(
+        &mut ctx,
+        callee_func_op,
+        TypeAttr::new(callee_func_ty.into()),
+    );
+    callee_func.set_symbol_name(&mut ctx, "callee".try_into().unwrap());
+    {
+        let region = callee_func.get_operation().deref(&ctx).get_region(0);
+        let block = BasicBlock::new(&mut ctx, None, vec![shared_ptr_ty.into()]);
+        block.insert_at_back(region, &ctx);
+
+        let ret_op = Operation::new(
+            &mut ctx,
+            mir::MirReturnOp::get_concrete_op_info(),
+            vec![],
+            vec![],
+            vec![],
+            0,
+        );
+        ret_op.insert_at_back(block, &ctx);
+    }
+    callee_func
+        .get_operation()
+        .insert_at_back(module_block, &ctx);
+
+    // Caller: takes a *mut i32 in addrspace(0), calls `callee` with that
+    // pointer. The lowerer is responsible for inserting an addrspacecast
+    // since the callee's declared addrspace differs.
+    let caller_func_ty = FunctionType::get(&ctx, vec![generic_ptr_ty.into()], vec![]);
+    let caller_func_op = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let caller_func = mir::MirFuncOp::new(
+        &mut ctx,
+        caller_func_op,
+        TypeAttr::new(caller_func_ty.into()),
+    );
+    caller_func.set_symbol_name(&mut ctx, "caller".try_into().unwrap());
+    {
+        let region = caller_func.get_operation().deref(&ctx).get_region(0);
+        let block = BasicBlock::new(&mut ctx, None, vec![generic_ptr_ty.into()]);
+        block.insert_at_back(region, &ctx);
+        let arg = block.deref(&ctx).get_argument(0);
+        let cast_op_ptr = Operation::new(
+            &mut ctx,
+            mir::MirCastOp::get_concrete_op_info(),
+            vec![shared_ptr_ty.into()],
+            vec![arg],
+            vec![],
+            0,
+        );
+        mir::MirCastOp::new(cast_op_ptr)
+            .set_attr_cast_kind(&ctx, dialect_mir::attributes::MirCastKindAttr::PtrToPtr);
+        cast_op_ptr.insert_at_back(block, &ctx);
+        let coerced_arg = cast_op_ptr.deref(&ctx).get_result(0);
+
+        let call_op_ptr = Operation::new(
+            &mut ctx,
+            mir::MirCallOp::get_concrete_op_info(),
+            vec![],
+            vec![coerced_arg],
+            vec![],
+            0,
+        );
+        let call_op = mir::MirCallOp::new(call_op_ptr);
+        call_op.set_attr_callee(&ctx, StringAttr::new("callee".to_string()));
+        call_op_ptr
+            .deref_mut(&ctx)
+            .set_loc(expected_call_location.clone());
+        call_op_ptr.insert_at_back(block, &ctx);
+
+        let ret_op = Operation::new(
+            &mut ctx,
+            mir::MirReturnOp::get_concrete_op_info(),
+            vec![],
+            vec![],
+            vec![],
+            0,
+        );
+        ret_op.insert_at_back(block, &ctx);
+    }
+    caller_func
+        .get_operation()
+        .insert_at_back(module_block, &ctx);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    let mut found_addrspace_cast = false;
+    let mut found_call = false;
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != "caller" {
+            continue;
+        }
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                if Operation::get_op::<AddrSpaceCastOp>(body_op, &ctx).is_some() {
+                    found_addrspace_cast = true;
+                }
+                if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
+                    && matches!(
+                        call.callee(&ctx),
+                        CallOpCallable::Direct(symbol) if symbol.to_string() == "callee"
+                    )
+                {
+                    found_call = true;
+                    assert_eq!(
+                        call.get_operation().deref(&ctx).loc(),
+                        expected_call_location
+                    );
+                }
+            }
+        }
+    }
+
+    assert!(
+        found_addrspace_cast,
+        "caller body must contain llvm.addrspacecast for the addrspace(0) -> (3) coercion at the call site",
+    );
+    assert!(found_call, "caller body must contain the lowered call");
+    Ok(())
+}
+
+/// A zero-sized MIR result is erased from the NVPTX function ABI, but its
+/// typed value can remain live inside MIR (for example, when one ZST-returning
+/// function returns the result of another). Lowering must keep the void call
+/// for side effects and replace only its value result with a typed LLVM undef.
+#[test]
+fn zst_union_call_result_keeps_void_call_and_replaces_live_uses() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::{MirTupleType, MirUnionType};
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::attributes::{StringAttr, TypeAttr};
+    use pliron::builtin::types::FunctionType;
+    use pliron::r#type::{TypeHandle, Typed};
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let unit_ty: TypeHandle = MirTupleType::get(&mut ctx, vec![]).into();
+    let union_ty: TypeHandle = MirUnionType::get(
+        &mut ctx,
+        "AlignedZeroUnion".into(),
+        vec!["unit".into()],
+        vec![unit_ty],
+        0,
+        16,
+    )
+    .into();
+
+    let module = ModuleOp::new(&mut ctx, "test_zst_union_call".try_into().unwrap());
+    let module_ptr = module.get_operation();
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+
+    let callee_ty = FunctionType::get(&ctx, vec![], vec![union_ty]);
+    let callee_ptr = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let callee = mir::MirFuncOp::new(&mut ctx, callee_ptr, TypeAttr::new(callee_ty.into()));
+    callee.set_symbol_name(&mut ctx, "make_zero".try_into().unwrap());
+    {
+        let region = callee.get_operation().deref(&ctx).get_region(0);
+        let block = BasicBlock::new(&mut ctx, None, vec![]);
+        block.insert_at_back(region, &ctx);
+
+        let undef = mir::MirUndefOp::new(&mut ctx, union_ty);
+        undef.get_operation().insert_at_back(block, &ctx);
+        let value = undef.get_operation().deref(&ctx).get_result(0);
+
+        let ret = Operation::new(
+            &mut ctx,
+            mir::MirReturnOp::get_concrete_op_info(),
+            vec![],
+            vec![value],
+            vec![],
+            0,
+        );
+        ret.insert_at_back(block, &ctx);
+    }
+    callee.get_operation().insert_at_back(module_block, &ctx);
+
+    let caller_ty = FunctionType::get(&ctx, vec![], vec![union_ty]);
+    let caller_ptr = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let caller = mir::MirFuncOp::new(&mut ctx, caller_ptr, TypeAttr::new(caller_ty.into()));
+    caller.set_symbol_name(&mut ctx, "return_called_zero".try_into().unwrap());
+    {
+        let region = caller.get_operation().deref(&ctx).get_region(0);
+        let block = BasicBlock::new(&mut ctx, None, vec![]);
+        block.insert_at_back(region, &ctx);
+
+        let call_ptr = Operation::new(
+            &mut ctx,
+            mir::MirCallOp::get_concrete_op_info(),
+            vec![union_ty],
+            vec![],
+            vec![],
+            0,
+        );
+        let call = mir::MirCallOp::new(call_ptr);
+        call.set_attr_callee(&ctx, StringAttr::new("make_zero".to_string()));
+        call_ptr.insert_at_back(block, &ctx);
+        let value = call_ptr.deref(&ctx).get_result(0);
+
+        let ret = Operation::new(
+            &mut ctx,
+            mir::MirReturnOp::get_concrete_op_info(),
+            vec![],
+            vec![value],
+            vec![],
+            0,
+        );
+        ret.insert_at_back(block, &ctx);
+    }
+    caller.get_operation().insert_at_back(module_block, &ctx);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{e}"))?;
+
+    let mut found_void_call = false;
+    let mut caller_undefs = 0;
+    let mut found_void_return = false;
+    for op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(func) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func.get_symbol_name(&ctx).to_string() != "return_called_zero" {
+            continue;
+        }
+        let region = func.get_operation().deref(&ctx).get_region(0);
+        for block in region.deref(&ctx).iter(&ctx) {
+            for body_op in block.deref(&ctx).iter(&ctx) {
+                if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
+                    && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+                    && callee.to_string() == "make_zero"
+                {
+                    let call_op = call.get_operation().deref(&ctx);
+                    assert_eq!(call_op.get_num_results(), 1);
+                    assert!(
+                        call_op
+                            .get_result(0)
+                            .get_type(&ctx)
+                            .deref(&ctx)
+                            .is::<llvm_export::types::VoidType>(),
+                        "the ZST-returning call must use the void ABI"
+                    );
+                    found_void_call = true;
+                }
+                if Operation::get_op::<llvm::UndefOp>(body_op, &ctx).is_some() {
+                    caller_undefs += 1;
+                }
+                if let Some(ret) = Operation::get_op::<llvm::ReturnOp>(body_op, &ctx) {
+                    assert_eq!(
+                        ret.get_operation().deref(&ctx).get_num_operands(),
+                        0,
+                        "the caller's ZST return must also use the void ABI"
+                    );
+                    found_void_return = true;
+                }
+            }
+        }
+    }
+
+    assert!(
+        found_void_call,
+        "the LLVM call must be retained because the callee may have side effects"
+    );
+    assert_eq!(
+        caller_undefs, 1,
+        "the live MIR result must be replaced by one typed LLVM undef"
+    );
+    assert!(
+        found_void_return,
+        "the caller must retain its return terminator"
+    );
+    Ok(())
+}
+
+/// Lock the comparison-predicate lowering table to the rustc_codegen_ssa
+/// reference (`bin_op_to_fcmp_predicate` / `bin_op_to_icmp_predicate`):
+///
+/// | MIR op   | float `fcmp`      | signed `icmp` | unsigned `icmp` |
+/// |----------|-------------------|---------------|-----------------|
+/// | `mir.eq` | `oeq` (ordered)   | `eq`          | `eq`            |
+/// | `mir.ne` | `une` (UNordered) | `ne`          | `ne`            |
+/// | `mir.lt` | `olt`             | `slt`         | `ult`           |
+/// | `mir.le` | `ole`             | `sle`         | `ule`           |
+/// | `mir.gt` | `ogt`             | `sgt`         | `ugt`           |
+/// | `mir.ge` | `oge`             | `sge`         | `uge`           |
+///
+/// `ne` is the one float predicate that must be UNordered: Rust requires
+/// `a != b == !(a == b)`, so `x != x` must be true for NaN (issue #123;
+/// the ordered `one` folds the canonical NaN check to `false`).
+///
+/// The test also locks fastmath flags to *empty* on every lowered `fcmp`:
+/// a future `nnan` default would make `fcmp nnan une x, x` poison for NaN
+/// and silently re-break NaN detection while the predicate assertion above
+/// stays green.
+#[test]
+fn test_cmp_predicate_lowering() -> Result<(), anyhow::Error> {
+    use llvm_export::attributes::{FCmpPredicateAttr, FastmathFlagsAttr, ICmpPredicateAttr};
+    use llvm_export::op_interfaces::FastMathFlags;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_ptr = module.get_operation();
+
+    let f32_ty = pliron::builtin::types::FP32Type::get(&ctx);
+    let i32_signed = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        32,
+        pliron::builtin::types::Signedness::Signed,
+    );
+    let u32_unsigned = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        32,
+        pliron::builtin::types::Signedness::Unsigned,
+    );
+    let bool_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        1,
+        pliron::builtin::types::Signedness::Signless,
+    );
+
+    // Args: (f32, f32, i32, u32). The integer args carry pre-conversion
+    // signedness, which is what selects signed vs unsigned icmp predicates.
+    let arg_tys: Vec<pliron::r#type::TypeHandle> = vec![
+        f32_ty.into(),
+        f32_ty.into(),
+        i32_signed.into(),
+        u32_unsigned.into(),
+    ];
+    let func_name = "cmp_func";
+    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, arg_tys.clone(), vec![]);
+
+    let func_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
+    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
+    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
+
+    let region = func.get_operation().deref(&ctx).get_region(0);
+    let block = {
+        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, arg_tys);
+        b.insert_at_back(region, &ctx);
+        b
+    };
+    let fa = block.deref(&ctx).get_argument(0);
+    let fb = block.deref(&ctx).get_argument(1);
+    let si = block.deref(&ctx).get_argument(2);
+    let ui = block.deref(&ctx).get_argument(3);
+
+    // One comparison op per table row, in a fixed program order. The raw
+    // `Operation::new` construction mirrors how the importer builds these
+    // ops (mir-importer translator/rvalue.rs BinaryOp arm).
+    let cmp_infos = [
+        // Floats: all six predicates.
+        (mir::MirEqOp::get_concrete_op_info(), fa, fb),
+        (mir::MirNeOp::get_concrete_op_info(), fa, fb),
+        (mir::MirLtOp::get_concrete_op_info(), fa, fb),
+        (mir::MirLeOp::get_concrete_op_info(), fa, fb),
+        (mir::MirGtOp::get_concrete_op_info(), fa, fb),
+        (mir::MirGeOp::get_concrete_op_info(), fa, fb),
+        // Signed integers: eq/ne are sign-agnostic, the rest must be s*.
+        (mir::MirEqOp::get_concrete_op_info(), si, si),
+        (mir::MirNeOp::get_concrete_op_info(), si, si),
+        (mir::MirLtOp::get_concrete_op_info(), si, si),
+        (mir::MirLeOp::get_concrete_op_info(), si, si),
+        (mir::MirGtOp::get_concrete_op_info(), si, si),
+        (mir::MirGeOp::get_concrete_op_info(), si, si),
+        // Unsigned integers: the relational predicates must be u*.
+        (mir::MirLtOp::get_concrete_op_info(), ui, ui),
+        (mir::MirLeOp::get_concrete_op_info(), ui, ui),
+        (mir::MirGtOp::get_concrete_op_info(), ui, ui),
+        (mir::MirGeOp::get_concrete_op_info(), ui, ui),
+    ];
+    for (info, lhs, rhs) in cmp_infos {
+        let op = Operation::new(
+            &mut ctx,
+            info,
+            vec![bool_ty.into()],
+            vec![lhs, rhs],
+            vec![],
+            0,
+        );
+        op.insert_at_back(block, &ctx);
+    }
+
+    let ret_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirReturnOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    ret_op_ptr.insert_at_back(block, &ctx);
+
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    // Collect lowered predicates in program order.
+    let mut fcmp_preds = Vec::new();
+    let mut icmp_preds = Vec::new();
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != func_name {
+            continue;
+        }
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                if let Some(fcmp) = Operation::get_op::<llvm::FCmpOp>(body_op, &ctx) {
+                    fcmp_preds.push(fcmp.predicate(&ctx));
+                    // fcmp carries `contract` (set by add_fastmath_flags) which is a
+                    // no-op for comparisons at the LLVM / PTX level. Critically, nnan
+                    // is NOT set, so NaN checks like `x != x` still evaluate correctly.
+                    let expected: FastmathFlagsAttr =
+                        llvm_export::attributes::FastmathFlags::CONTRACT.into();
+                    assert_eq!(
+                        fcmp.fast_math_flags(&ctx),
+                        expected,
+                        "fcmp must carry only the contract flag (nnan would poison NaN checks)"
+                    );
+                }
+                if let Some(icmp) = Operation::get_op::<llvm::ICmpOp>(body_op, &ctx) {
+                    icmp_preds.push(icmp.predicate(&ctx));
+                }
+            }
+        }
+    }
+
+    assert_eq!(
+        fcmp_preds,
+        vec![
+            FCmpPredicateAttr::OEQ,
+            FCmpPredicateAttr::UNE,
+            FCmpPredicateAttr::OLT,
+            FCmpPredicateAttr::OLE,
+            FCmpPredicateAttr::OGT,
+            FCmpPredicateAttr::OGE,
+        ],
+        "float comparison predicates must mirror rustc: ordered except Ne (une)"
+    );
+    assert_eq!(
+        icmp_preds,
+        vec![
+            ICmpPredicateAttr::EQ,
+            ICmpPredicateAttr::NE,
+            ICmpPredicateAttr::SLT,
+            ICmpPredicateAttr::SLE,
+            ICmpPredicateAttr::SGT,
+            ICmpPredicateAttr::SGE,
+            ICmpPredicateAttr::ULT,
+            ICmpPredicateAttr::ULE,
+            ICmpPredicateAttr::UGT,
+            ICmpPredicateAttr::UGE,
+        ],
+        "integer comparison predicates must respect pre-conversion signedness"
+    );
+    Ok(())
+}
+
+/// Regression cover for PR #141: comparisons whose operand is a bool phi.
+///
+/// Bools are signless i1, which `can_convert_type` rejects (signless is
+/// already the LLVM form), so DialectConversion records no type history for
+/// a bool block argument. `is_signed_int_op` used to error out for such
+/// operands ("expected IntegerType or MirPtrType operand in arithmetic op");
+/// it must instead fall back to the live operand type and lower the
+/// comparison as unsigned.
+///
+/// The function mirrors the MIR of a short-circuit kernel:
+///
+/// ```text
+/// let p = a || b;            // bool phi: merge block argument
+/// out = (p == q, p < q);     // icmp eq i1 / icmp ult i1
+/// ```
+///
+/// ```text
+/// bb0(a: i1, b: i1, q: i1):  mir.cond_br a, bb2(a), bb1()
+/// bb1():                     mir.goto bb2(b)
+/// bb2(p: i1):                mir.eq p, q ; mir.lt p, q ; mir.return
+/// ```
+#[test]
+fn test_bool_phi_cmp_lowers_to_unsigned_i1_icmp() -> Result<(), anyhow::Error> {
+    use llvm_export::attributes::ICmpPredicateAttr;
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::op_interfaces::OperandSegmentInterface;
+    use pliron::builtin::types::{FunctionType, IntegerType, Signedness};
+    use pliron::r#type::Typed;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_ptr = module.get_operation();
+
+    let bool_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let arg_tys: Vec<pliron::r#type::TypeHandle> =
+        vec![bool_ty.into(), bool_ty.into(), bool_ty.into()];
+    let func_name = "bool_phi_cmp";
+    let func_ty = FunctionType::get(&ctx, arg_tys.clone(), vec![]);
+
+    let func_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
+    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
+    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
+
+    let region = func.get_operation().deref(&ctx).get_region(0);
+
+    // bb0(a, b, q): the function entry.
+    let bb0 = BasicBlock::new(&mut ctx, None, arg_tys);
+    bb0.insert_at_back(region, &ctx);
+    let a = bb0.deref(&ctx).get_argument(0);
+    let b = bb0.deref(&ctx).get_argument(1);
+    let q = bb0.deref(&ctx).get_argument(2);
+
+    // bb1(): the short-circuit "evaluate b" block.
+    let bb1 = BasicBlock::new(&mut ctx, None, vec![]);
+    bb1.insert_at_back(region, &ctx);
+
+    // bb2(p): the merge block; `p` is the bool phi.
+    let bb2 = BasicBlock::new(&mut ctx, None, vec![bool_ty.into()]);
+    bb2.insert_at_back(region, &ctx);
+    let p = bb2.deref(&ctx).get_argument(0);
+
+    // bb0: cond_br a, bb2(a), bb1(). On the true edge `a` is true, so
+    // passing `a` itself is `a || b` without needing a constant.
+    let (flat_operands, segment_sizes) =
+        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![a], vec![a], vec![]]);
+    let cond_br = Operation::new(
+        &mut ctx,
+        mir::MirCondBranchOp::get_concrete_op_info(),
+        vec![],
+        flat_operands,
+        vec![bb2, bb1],
+        0,
+    );
+    Operation::get_op::<mir::MirCondBranchOp>(cond_br, &ctx)
+        .expect("MirCondBranchOp")
+        .set_operand_segment_sizes(&ctx, segment_sizes);
+    cond_br.insert_at_back(bb0, &ctx);
+
+    // bb1: goto bb2(b).
+    let goto = Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![b],
+        vec![bb2],
+        0,
+    );
+    goto.insert_at_back(bb1, &ctx);
+
+    // bb2: p == q, then p < q.
+    for info in [
+        mir::MirEqOp::get_concrete_op_info(),
+        mir::MirLtOp::get_concrete_op_info(),
+    ] {
+        let cmp = Operation::new(&mut ctx, info, vec![bool_ty.into()], vec![p, q], vec![], 0);
+        cmp.insert_at_back(bb2, &ctx);
+    }
+    let ret_op = Operation::new(
+        &mut ctx,
+        mir::MirReturnOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    ret_op.insert_at_back(bb2, &ctx);
+
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    // Before the fallback, this failed with "expected IntegerType or
+    // MirPtrType operand in arithmetic op".
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    let mut icmps = Vec::new();
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != func_name {
+            continue;
+        }
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                if let Some(icmp) = Operation::get_op::<llvm::ICmpOp>(body_op, &ctx) {
+                    let lhs_ty = body_op.deref(&ctx).get_operand(0).get_type(&ctx);
+                    icmps.push((icmp.predicate(&ctx), lhs_ty));
+                }
+            }
+        }
+    }
+
+    let i1: pliron::r#type::TypeHandle = bool_ty.into();
+    assert_eq!(
+        icmps,
+        vec![(ICmpPredicateAttr::EQ, i1), (ICmpPredicateAttr::ULT, i1),],
+        "bool-phi comparisons must lower to `icmp eq i1` and `icmp ult i1`"
+    );
+    Ok(())
+}
+
+// =============================================================================
+// Scalar math lowering tests
+// =============================================================================
+
+/// Builds a module holding a single `mir.func` whose body calls the `bswap`
+/// placeholder on a `u8` argument, with the call result carrying `result_ty`.
+/// Shared by the valid (u8 result) and malformed (tuple result) 8-bit bswap
+/// tests below.
+fn build_bswap8_call_module(
+    ctx: &mut Context,
+    result_ty: pliron::r#type::TypeHandle,
+) -> pliron::context::Ptr<Operation> {
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::attributes::StringAttr;
+    use pliron::builtin::attributes::TypeAttr;
+    use pliron::builtin::types::{FunctionType, IntegerType, Signedness};
+
+    let u8_ty = IntegerType::get(ctx, 8, Signedness::Unsigned);
+
+    let module = ModuleOp::new(ctx, "m".try_into().unwrap());
+    let module_ptr = module.get_operation();
+    let module_block = module
+        .get_operation()
+        .deref(ctx)
+        .get_region(0)
+        .deref(ctx)
+        .iter(ctx)
+        .next()
+        .unwrap();
+
+    let func_ty = FunctionType::get(ctx, vec![u8_ty.into()], vec![]);
+    let func_op = Operation::new(
+        ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let func = mir::MirFuncOp::new(ctx, func_op, TypeAttr::new(func_ty.into()));
+    func.set_symbol_name(ctx, "f".try_into().unwrap());
+    {
+        let region = func.get_operation().deref(ctx).get_region(0);
+        let block = BasicBlock::new(ctx, None, vec![u8_ty.into()]);
+        block.insert_at_back(region, ctx);
+        let arg = block.deref(ctx).get_argument(0);
+
+        let call_ptr = Operation::new(
+            ctx,
+            mir::MirCallOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![arg],
+            vec![],
+            0,
+        );
+        let call = mir::MirCallOp::new(call_ptr);
+        call.set_attr_callee(
+            ctx,
+            StringAttr::new(dialect_mir::rust_intrinsics::CALLEE_BSWAP.to_string()),
+        );
+        call_ptr.insert_at_back(block, ctx);
+
+        let ret_op = Operation::new(
+            ctx,
+            mir::MirReturnOp::get_concrete_op_info(),
+            vec![],
+            vec![],
+            vec![],
+            0,
+        );
+        ret_op.insert_at_back(block, ctx);
+    }
+    func.get_operation().insert_at_back(module_block, ctx);
+
+    module_ptr
+}
+
+/// An 8-bit `bswap` takes an early bitcast path, since Rust's semantics for a
+/// single byte are identity and LLVM has no useful intrinsic for it. That path
+/// returned before reaching the cast every other arm goes through, so a result
+/// type that was not an 8-bit integer produced `bitcast i8 to <aggregate>`,
+/// which LLVM rejects when the module is read back.
+///
+/// The known producer of this shape is an importer bug that hands the call
+/// the type of the destination *local* rather than of the projected place it
+/// writes, so `RET.1 = bswap(x)` on a `(f64, u8)` return arrives here
+/// carrying the whole tuple. That bug is the importer's to fix, and whatever
+/// the importer does, a malformed producer can still build such a `mir.call`.
+/// Lowering cannot repair it, and refusing it is what keeps the emitted
+/// module valid.
+#[test]
+fn bswap8_with_an_aggregate_result_is_refused_rather_than_bitcast() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirTupleType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let f64_ty = pliron::builtin::types::FP64Type::get(&ctx);
+    // The tuple result is the whole point: an 8-bit operand with a result
+    // the bitcast cannot legally produce.
+    let tuple_ty = MirTupleType::get(&mut ctx, vec![f64_ty.into(), u8_ty.into()]);
+    let module_ptr = build_bswap8_call_module(&mut ctx, tuple_ty.into());
+
+    let result = mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr);
+    let error =
+        result.expect_err("an 8-bit bswap with a tuple result must be refused, not lowered");
+    assert!(
+        error
+            .to_string()
+            .contains("expected integer type for Rust bit intrinsic"),
+        "unexpected error: {error}"
+    );
+    Ok(())
+}
+
+/// The valid counterpart: an 8-bit `bswap` whose result is a plain `u8` must
+/// still take the identity-bitcast path and lower cleanly, so the guard above
+/// cannot over-reject the case Rust actually produces for `u8::swap_bytes`.
+#[test]
+fn bswap8_with_a_u8_result_lowers_to_an_identity_bitcast() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let module_ptr = build_bswap8_call_module(&mut ctx, u8_ty.into());
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect("an 8-bit bswap with a u8 result must lower");
+
+    // The call must have become a bitcast, not an intrinsic call: there is no
+    // llvm.bswap.i8.
+    let mut found_bitcast = false;
+    let module_block = module_ptr
+        .deref(&ctx)
+        .get_region(0)
+        .deref(&ctx)
+        .iter(&ctx)
+        .next()
+        .unwrap();
+    for op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                assert!(
+                    Operation::get_op::<llvm::CallOp>(body_op, &ctx).is_none(),
+                    "an 8-bit bswap must not lower to an intrinsic call"
+                );
+                if Operation::get_op::<llvm::BitcastOp>(body_op, &ctx).is_some() {
+                    found_bitcast = true;
+                }
+            }
+        }
+    }
+    assert!(
+        found_bitcast,
+        "an 8-bit bswap with a u8 result must lower to an identity bitcast"
+    );
+    Ok(())
+}
diff --git a/crates/mir-lower/tests/lowering_test/common.rs b/crates/mir-lower/tests/lowering_test/common.rs
new file mode 100644
index 0000000000..0fa5a821d5
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/common.rs
@@ -0,0 +1,101 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::ops as mir;
+use llvm_export::ops as llvm;
+use pliron::builtin::op_interfaces::SymbolOpInterface;
+use pliron::builtin::ops::ModuleOp;
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+/// Helper: fresh context with all dialects registered.
+pub(super) fn make_test_ctx() -> Context {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+    ctx
+}
+
+/// Helper: build a module + MirFuncOp("kernel_func") with given arg types,
+/// returning the module ptr and entry block.
+pub(super) fn build_test_kernel(
+    ctx: &mut Context,
+    arg_tys: Vec<pliron::r#type::TypeHandle>,
+) -> (
+    pliron::context::Ptr<Operation>,
+    pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+) {
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::attributes::TypeAttr;
+    use pliron::builtin::types::FunctionType;
+
+    let module = ModuleOp::new(ctx, "test_module".try_into().unwrap());
+    let module_ptr = module.get_operation();
+
+    let func_ty = FunctionType::get(ctx, arg_tys.clone(), vec![]);
+    let func_op_ptr = Operation::new(
+        ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let func = mir::MirFuncOp::new(ctx, func_op_ptr, TypeAttr::new(func_ty.into()));
+    func.set_symbol_name(ctx, "kernel_func".try_into().unwrap());
+
+    let region = func.get_operation().deref(ctx).get_region(0);
+    let entry = BasicBlock::new(ctx, None, arg_tys);
+    entry.insert_at_back(region, ctx);
+
+    let module_region = module_ptr.deref(ctx).get_region(0);
+    let module_block = module_region.deref(ctx).iter(ctx).next().unwrap();
+    func.get_operation().insert_at_back(module_block, ctx);
+
+    (module_ptr, entry)
+}
+
+/// Helper: append a mir.return (void) to a block.
+pub(super) fn append_return(
+    ctx: &mut Context,
+    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+) {
+    let ret = Operation::new(
+        ctx,
+        mir::MirReturnOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    ret.insert_at_back(block, ctx);
+}
+
+pub(super) fn lowered_kernel_body(
+    ctx: &Context,
+    module_ptr: pliron::context::Ptr<Operation>,
+) -> Vec<pliron::context::Ptr<Operation>> {
+    let module_region = module_ptr.deref(ctx).get_region(0);
+    let module_block = module_region.deref(ctx).iter(ctx).next().unwrap();
+    for op in module_block.deref(ctx).iter(ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(ctx).to_string() != "kernel_func" {
+            continue;
+        }
+
+        let func_region = func_op.get_operation().deref(ctx).get_region(0);
+        return func_region
+            .deref(ctx)
+            .iter(ctx)
+            .flat_map(|block| block.deref(ctx).iter(ctx))
+            .collect();
+    }
+    panic!("lowered kernel function not found")
+}
diff --git a/crates/mir-lower/tests/lowering_test/cp_async.rs b/crates/mir-lower/tests/lowering_test/cp_async.rs
new file mode 100644
index 0000000000..17d2c3c61b
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/cp_async.rs
@@ -0,0 +1,727 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::ops as mir;
+use dialect_nvvm::ops as nvvm;
+use llvm_export::ops as llvm;
+use pliron::builtin::op_interfaces::{CallOpCallable, CallOpInterface, SymbolOpInterface};
+use pliron::builtin::ops::ModuleOp;
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+use crate::common::{append_return, build_test_kernel, lowered_kernel_body, make_test_ctx};
+
+fn lower_all_classic_cp_async(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = make_test_ctx();
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let dst_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), true);
+    let src32_ty = MirPtrType::get_generic(&mut ctx, u32_ty.into(), false);
+    let src8_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
+    let (module_ptr, entry) = build_test_kernel(
+        &mut ctx,
+        vec![
+            dst_ty.into(),
+            src32_ty.into(),
+            src8_ty.into(),
+            u32_ty.into(),
+        ],
+    );
+    let dst = entry.deref(&ctx).get_argument(0);
+    let src32 = entry.deref(&ctx).get_argument(1);
+    let src8 = entry.deref(&ctx).get_argument(2);
+    let source_size = entry.deref(&ctx).get_argument(3);
+
+    let zero_op = Operation::new(
+        &mut ctx,
+        mir::MirConstantOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    mir::MirConstantOp::new(zero_op).set_attr_value(
+        &ctx,
+        IntegerAttr::new(u32_ty, APInt::from_u32(0, NonZeroUsize::new(32).unwrap())),
+    );
+    zero_op.insert_at_back(entry, &ctx);
+    let zero = zero_op.deref(&ctx).get_result(0);
+
+    for copy in [
+        nvvm::CpAsyncCa4Op::build(&mut ctx, dst, src32),
+        nvvm::CpAsyncCa8Op::build(&mut ctx, dst, src32),
+        nvvm::CpAsyncCa16Op::build(&mut ctx, dst, src32),
+        nvvm::CpAsyncCaZfill4Op::build(&mut ctx, dst, src8, source_size),
+        nvvm::CpAsyncCaZfill8Op::build(&mut ctx, dst, src8, source_size),
+        nvvm::CpAsyncCaZfill16Op::build(&mut ctx, dst, src8, source_size),
+        nvvm::CpAsyncCg16Op::build(&mut ctx, dst, src32),
+        nvvm::CpAsyncCgZfill16Op::build(&mut ctx, dst, src8, source_size),
+    ] {
+        copy.insert_at_back(entry, &ctx);
+    }
+    for control in [
+        nvvm::CpAsyncCommitGroupOp::build(&mut ctx),
+        nvvm::CpAsyncWaitGroupOp::build(&mut ctx, zero),
+        nvvm::CpAsyncWaitAllOp::build(&mut ctx),
+    ] {
+        control.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+fn lower_all_cp_async_mbarrier(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let generic_ty = MirPtrType::get_generic(&mut ctx, u64_ty.into(), true);
+    let shared_ty = MirPtrType::get_shared(&mut ctx, u64_ty.into(), true);
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![generic_ty.into(), shared_ty.into()]);
+    let generic = entry.deref(&ctx).get_argument(0);
+    let shared = entry.deref(&ctx).get_argument(1);
+
+    for bridge in [
+        nvvm::CpAsyncMbarrierArriveOp::build(&mut ctx, shared),
+        nvvm::CpAsyncMbarrierArriveSharedOp::build(&mut ctx, generic),
+        nvvm::CpAsyncMbarrierArriveNoIncOp::build(&mut ctx, shared),
+        nvvm::CpAsyncMbarrierArriveNoIncSharedOp::build(&mut ctx, generic),
+    ] {
+        bridge.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn test_generated_cp_async_mbarrier_preserves_backend_and_address_routes()
+-> Result<(), anyhow::Error> {
+    use llvm_export::types::PointerType;
+    use pliron::r#type::Typed;
+
+    let typed = [
+        ("llvm_nvvm_cp_async_mbarrier_arrive", 0),
+        ("llvm_nvvm_cp_async_mbarrier_arrive_shared", 3),
+        ("llvm_nvvm_cp_async_mbarrier_arrive_noinc", 0),
+        ("llvm_nvvm_cp_async_mbarrier_arrive_noinc_shared", 3),
+    ];
+    let templates = [
+        ("cp.async.mbarrier.arrive.b64 [$0];", 0),
+        ("cp.async.mbarrier.arrive.shared.b64 [$0];", 3),
+        ("cp.async.mbarrier.arrive.noinc.b64 [$0];", 0),
+        ("cp.async.mbarrier.arrive.noinc.shared.b64 [$0];", 3),
+    ];
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        let (ctx, module_ptr) = lower_all_cp_async_mbarrier(backend)?;
+        let mut call_counts = [0usize; 4];
+        let mut asm_counts = [0usize; 4];
+
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) {
+                let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+                    continue;
+                };
+                let callee = callee.to_string();
+                let Some(index) = typed.iter().position(|(name, _)| callee == *name) else {
+                    continue;
+                };
+                call_counts[index] += 1;
+                let pointer = op.deref(&ctx).get_operand(0).get_type(&ctx);
+                assert_eq!(
+                    pointer
+                        .deref(&ctx)
+                        .downcast_ref::<PointerType>()
+                        .unwrap()
+                        .address_space(),
+                    typed[index].1
+                );
+            }
+            if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
+                let template = inline_asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .unwrap();
+                let Some(index) = templates
+                    .iter()
+                    .position(|(expected, _)| template == *expected)
+                else {
+                    continue;
+                };
+                asm_counts[index] += 1;
+                assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Convergent);
+                assert!(
+                    inline_asm
+                        .get_attr_inline_asm_convergent(&ctx)
+                        .is_some_and(|value| bool::from((*value).clone()))
+                );
+                assert_eq!(
+                    inline_asm
+                        .get_attr_inline_asm_constraints(&ctx)
+                        .map(|value| String::from((*value).clone()))
+                        .as_deref(),
+                    Some("l,~{memory}")
+                );
+                let pointer = op.deref(&ctx).get_operand(0).get_type(&ctx);
+                assert_eq!(
+                    pointer
+                        .deref(&ctx)
+                        .downcast_ref::<PointerType>()
+                        .unwrap()
+                        .address_space(),
+                    templates[index].1
+                );
+            }
+        }
+
+        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+            .map_err(|error| anyhow::anyhow!(error))?;
+        match backend {
+            mir_lower::IntrinsicBackend::LlvmNvptx => {
+                assert_eq!(call_counts, [1; 4]);
+                assert_eq!(asm_counts, [0; 4]);
+                assert!(
+                    ir.contains("@llvm.nvvm.cp.async.mbarrier.arrive(ptr"),
+                    "{ir}"
+                );
+                assert!(
+                    ir.contains("@llvm.nvvm.cp.async.mbarrier.arrive.shared(ptr addrspace(3)"),
+                    "{ir}"
+                );
+                assert!(
+                    ir.contains("@llvm.nvvm.cp.async.mbarrier.arrive.noinc(ptr"),
+                    "{ir}"
+                );
+                assert!(
+                    ir.contains(
+                        "@llvm.nvvm.cp.async.mbarrier.arrive.noinc.shared(ptr addrspace(3)"
+                    ),
+                    "{ir}"
+                );
+                assert!(!ir.contains("cp.async.mbarrier.arrive.b64 [$0]"), "{ir}");
+            }
+            mir_lower::IntrinsicBackend::LibNvvm => {
+                assert_eq!(call_counts, [0; 4]);
+                assert_eq!(asm_counts, [1; 4]);
+                assert!(!ir.contains("@llvm.nvvm.cp.async.mbarrier"), "{ir}");
+                for (template, _) in templates {
+                    assert!(ir.contains(template), "{ir}");
+                }
+                assert!(ir.contains("asm sideeffect"), "{ir}");
+                assert!(ir.contains("convergent"), "{ir}");
+            }
+        }
+    }
+    Ok(())
+}
+
+#[test]
+fn test_generated_cp_async_llvm_nvptx_uses_all_typed_intrinsics() -> Result<(), anyhow::Error> {
+    use llvm_export::types::PointerType;
+    use pliron::r#type::Typed;
+
+    let (ctx, module_ptr) = lower_all_classic_cp_async(mir_lower::IntrinsicBackend::LlvmNvptx)?;
+    let mut found = Vec::new();
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        assert!(
+            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+            "LLVM-NVPTX cp.async must use typed intrinsics"
+        );
+        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+            continue;
+        };
+        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+            continue;
+        };
+        let callee = callee.to_string();
+        if !callee.starts_with("llvm_nvvm_cp_async") {
+            continue;
+        }
+        if callee.contains("shared_global") {
+            let call = op.deref(&ctx);
+            let destination_ty = call.get_operand(0).get_type(&ctx);
+            let source_ty = call.get_operand(1).get_type(&ctx);
+            assert_eq!(
+                destination_ty
+                    .deref(&ctx)
+                    .downcast_ref::<PointerType>()
+                    .unwrap()
+                    .address_space(),
+                3
+            );
+            assert_eq!(
+                source_ty
+                    .deref(&ctx)
+                    .downcast_ref::<PointerType>()
+                    .unwrap()
+                    .address_space(),
+                1
+            );
+        }
+        found.push(callee);
+    }
+    found.sort();
+    let mut expected = [
+        "llvm_nvvm_cp_async_ca_shared_global_4",
+        "llvm_nvvm_cp_async_ca_shared_global_4_s",
+        "llvm_nvvm_cp_async_ca_shared_global_8",
+        "llvm_nvvm_cp_async_ca_shared_global_8_s",
+        "llvm_nvvm_cp_async_ca_shared_global_16",
+        "llvm_nvvm_cp_async_ca_shared_global_16_s",
+        "llvm_nvvm_cp_async_cg_shared_global_16",
+        "llvm_nvvm_cp_async_cg_shared_global_16_s",
+        "llvm_nvvm_cp_async_commit_group",
+        "llvm_nvvm_cp_async_wait_all",
+        "llvm_nvvm_cp_async_wait_group",
+    ]
+    .map(str::to_owned);
+    expected.sort();
+    assert_eq!(found, expected);
+    Ok(())
+}
+
+#[test]
+fn test_generated_cp_async_libnvvm_uses_all_exact_inline_ptx() -> Result<(), anyhow::Error> {
+    let (ctx, module_ptr) = lower_all_classic_cp_async(mir_lower::IntrinsicBackend::LibNvvm)?;
+    let mut lowered = Vec::new();
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            continue;
+        };
+        assert_eq!(llvm::asm_kind(&ctx, &asm), llvm::AsmKind::SideEffect);
+        assert!(
+            asm.get_attr_inline_asm_convergent(&ctx)
+                .is_some_and(|value| !bool::from((*value).clone()))
+        );
+        lowered.push((
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .unwrap(),
+            asm.get_attr_inline_asm_constraints(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .unwrap(),
+        ));
+    }
+
+    let expected = [
+        (
+            "cp.async.ca.shared.global [%smem32], [%gmem64], 4;",
+            "l,l,~{memory}",
+        ),
+        (
+            "cp.async.ca.shared.global [%smem32], [%gmem64], 8;",
+            "l,l,~{memory}",
+        ),
+        (
+            "cp.async.ca.shared.global [%smem32], [%gmem64], 16;",
+            "l,l,~{memory}",
+        ),
+        (
+            "cp.async.ca.shared.global [%smem32], [%gmem64], 4, $2;",
+            "l,l,r,~{memory}",
+        ),
+        (
+            "cp.async.ca.shared.global [%smem32], [%gmem64], 8, $2;",
+            "l,l,r,~{memory}",
+        ),
+        (
+            "cp.async.ca.shared.global [%smem32], [%gmem64], 16, $2;",
+            "l,l,r,~{memory}",
+        ),
+        (
+            "cp.async.cg.shared.global [%smem32], [%gmem64], 16;",
+            "l,l,~{memory}",
+        ),
+        (
+            "cp.async.cg.shared.global [%smem32], [%gmem64], 16, $2;",
+            "l,l,r,~{memory}",
+        ),
+        ("cp.async.commit_group;", "~{memory}"),
+        ("cp.async.wait_group $0;", "n,~{memory}"),
+        ("cp.async.wait_all;", "~{memory}"),
+    ];
+    for (instruction, constraints) in expected {
+        assert_eq!(
+            lowered
+                .iter()
+                .filter(|(template, actual_constraints)| {
+                    template.contains(instruction) && actual_constraints == constraints
+                })
+                .count(),
+            1,
+            "missing exact `{instruction}`"
+        );
+    }
+    assert_eq!(lowered.len(), expected.len());
+    Ok(())
+}
+
+#[test]
+fn test_cp_async_ca_4_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let dst_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let src_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![dst_ty.into(), src_ty.into()]);
+
+    let dst = entry.deref(&ctx).get_argument(0);
+    let src = entry.deref(&ctx).get_argument(1);
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::CpAsyncCa4Op::get_concrete_op_info(),
+        vec![],
+        vec![dst, src],
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    assert_cp_async_inline_asm_lowering(&mut ctx, module_ptr, 4)
+}
+
+#[test]
+fn test_cp_async_ca_8_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let dst_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let src_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), false);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![dst_ty.into(), src_ty.into()]);
+
+    let dst = entry.deref(&ctx).get_argument(0);
+    let src = entry.deref(&ctx).get_argument(1);
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::CpAsyncCa8Op::get_concrete_op_info(),
+        vec![],
+        vec![dst, src],
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    assert_cp_async_inline_asm_lowering(&mut ctx, module_ptr, 8)
+}
+
+fn assert_cp_async_inline_asm_lowering(
+    ctx: &mut Context,
+    module_ptr: pliron::context::Ptr<Operation>,
+    copy_size: u32,
+) -> Result<(), anyhow::Error> {
+    use pliron::r#type::Typed;
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: mir_lower::IntrinsicBackend::LibNvvm,
+            ..Default::default()
+        },
+    )
+    .map_err(|e| anyhow::anyhow!("{e}"))?;
+
+    let expected_template = format!(
+        "{{ .reg .u64 %smem64; .reg .u32 %smem32; .reg .u64 %gmem64; \
+         cvta.to.shared.u64 %smem64, $0; cvt.u32.u64 %smem32, %smem64; \
+         cvta.to.global.u64 %gmem64, $1; \
+         cp.async.ca.shared.global [%smem32], [%gmem64], {copy_size}; }}"
+    );
+    let mut matches = 0;
+    let module_region = module_ptr.deref(ctx).get_region(0);
+    let module_block = module_region.deref(ctx).iter(ctx).next().unwrap();
+
+    for op in module_block.deref(ctx).iter(ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(ctx).to_string() != "kernel_func" {
+            continue;
+        }
+
+        let func_region = func_op.get_operation().deref(ctx).get_region(0);
+        for func_block in func_region.deref(ctx).iter(ctx) {
+            for body_op in func_block.deref(ctx).iter(ctx) {
+                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, ctx) else {
+                    continue;
+                };
+                let template = inline_asm
+                    .get_attr_inline_asm_template(ctx)
+                    .map(|s| String::from((*s).clone()));
+                if template.as_deref() != Some(expected_template.as_str()) {
+                    continue;
+                }
+
+                matches += 1;
+                assert_eq!(
+                    inline_asm
+                        .get_attr_inline_asm_constraints(ctx)
+                        .map(|s| String::from((*s).clone()))
+                        .as_deref(),
+                    Some("l,l,~{memory}")
+                );
+                assert_eq!(llvm::asm_kind(ctx, &inline_asm), llvm::AsmKind::SideEffect);
+                assert!(
+                    inline_asm
+                        .get_attr_inline_asm_convergent(ctx)
+                        .is_some_and(|value| !bool::from((*value).clone()))
+                );
+
+                let operands: Vec<_> = inline_asm.get_operation().deref(ctx).operands().collect();
+                assert_eq!(operands.len(), 2);
+                for operand in operands {
+                    let ty = operand.get_type(ctx);
+                    let ty = ty.deref(ctx);
+                    let ptr_ty = ty
+                        .downcast_ref::<llvm_export::types::PointerType>()
+                        .expect("cp.async operands must lower to LLVM pointers");
+                    assert_eq!(ptr_ty.address_space(), 0);
+                }
+            }
+        }
+    }
+
+    assert_eq!(matches, 1, "missing exact {copy_size}-byte cp.async asm");
+    Ok(())
+}
+
+// =============================================================================
+// cp.async zero-fill lowering tests
+// =============================================================================
+
+#[test]
+fn test_cp_async_ca_zfill_4_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let dst_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let src_ty = MirPtrType::get_generic(&mut ctx, i8_ty.into(), false);
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![dst_ty.into(), src_ty.into(), i32_ty.into()]);
+
+    let dst = entry.deref(&ctx).get_argument(0);
+    let src = entry.deref(&ctx).get_argument(1);
+    let src_size = entry.deref(&ctx).get_argument(2);
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::CpAsyncCaZfill4Op::get_concrete_op_info(),
+        vec![],
+        vec![dst, src, src_size],
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    assert_cp_async_zfill_inline_asm_lowering(&mut ctx, module_ptr, 4)
+}
+
+#[test]
+fn test_cp_async_ca_zfill_8_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let dst_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let src_ty = MirPtrType::get_generic(&mut ctx, i8_ty.into(), false);
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![dst_ty.into(), src_ty.into(), i32_ty.into()]);
+
+    let dst = entry.deref(&ctx).get_argument(0);
+    let src = entry.deref(&ctx).get_argument(1);
+    let src_size = entry.deref(&ctx).get_argument(2);
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::CpAsyncCaZfill8Op::get_concrete_op_info(),
+        vec![],
+        vec![dst, src, src_size],
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    assert_cp_async_zfill_inline_asm_lowering(&mut ctx, module_ptr, 8)
+}
+
+#[test]
+fn test_cp_async_ca_zfill_16_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let dst_ty = MirPtrType::get_generic(&mut ctx, i32_ty.into(), true);
+    let src_ty = MirPtrType::get_generic(&mut ctx, i8_ty.into(), false);
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![dst_ty.into(), src_ty.into(), i32_ty.into()]);
+
+    let dst = entry.deref(&ctx).get_argument(0);
+    let src = entry.deref(&ctx).get_argument(1);
+    let src_size = entry.deref(&ctx).get_argument(2);
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::CpAsyncCaZfill16Op::get_concrete_op_info(),
+        vec![],
+        vec![dst, src, src_size],
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    assert_cp_async_zfill_inline_asm_lowering(&mut ctx, module_ptr, 16)
+}
+
+fn assert_cp_async_zfill_inline_asm_lowering(
+    ctx: &mut Context,
+    module_ptr: pliron::context::Ptr<Operation>,
+    copy_size: u32,
+) -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::IntegerType;
+    use pliron::r#type::Typed;
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: mir_lower::IntrinsicBackend::LibNvvm,
+            ..Default::default()
+        },
+    )
+    .map_err(|e| anyhow::anyhow!("{e}"))?;
+
+    let expected_template = format!(
+        "{{ .reg .u64 %smem64; .reg .u32 %smem32; .reg .u64 %gmem64; \
+         cvta.to.shared.u64 %smem64, $0; cvt.u32.u64 %smem32, %smem64; \
+         cvta.to.global.u64 %gmem64, $1; \
+         cp.async.ca.shared.global [%smem32], [%gmem64], {copy_size}, $2; }}"
+    );
+    let mut matches = 0;
+    let module_region = module_ptr.deref(ctx).get_region(0);
+    let module_block = module_region.deref(ctx).iter(ctx).next().unwrap();
+
+    for op in module_block.deref(ctx).iter(ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(ctx).to_string() != "kernel_func" {
+            continue;
+        }
+
+        let func_region = func_op.get_operation().deref(ctx).get_region(0);
+        for func_block in func_region.deref(ctx).iter(ctx) {
+            for body_op in func_block.deref(ctx).iter(ctx) {
+                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, ctx) else {
+                    continue;
+                };
+                let template = inline_asm
+                    .get_attr_inline_asm_template(ctx)
+                    .map(|s| String::from((*s).clone()));
+                if template.as_deref() != Some(expected_template.as_str()) {
+                    continue;
+                }
+
+                matches += 1;
+                assert_eq!(
+                    inline_asm
+                        .get_attr_inline_asm_constraints(ctx)
+                        .map(|s| String::from((*s).clone()))
+                        .as_deref(),
+                    Some("l,l,r,~{memory}")
+                );
+                assert_eq!(llvm::asm_kind(ctx, &inline_asm), llvm::AsmKind::SideEffect);
+                assert!(
+                    inline_asm
+                        .get_attr_inline_asm_convergent(ctx)
+                        .is_some_and(|value| !bool::from((*value).clone()))
+                );
+
+                let operands: Vec<_> = inline_asm.get_operation().deref(ctx).operands().collect();
+                assert_eq!(operands.len(), 3);
+                for operand in &operands[..2] {
+                    let ty = operand.get_type(ctx);
+                    let ty = ty.deref(ctx);
+                    let ptr_ty = ty
+                        .downcast_ref::<llvm_export::types::PointerType>()
+                        .expect("cp.async pointer operands must lower to LLVM pointers");
+                    assert_eq!(ptr_ty.address_space(), 0);
+                }
+
+                let src_size_ty = operands[2].get_type(ctx);
+                let src_size_ty = src_size_ty.deref(ctx);
+                let src_size_ty = src_size_ty
+                    .downcast_ref::<IntegerType>()
+                    .expect("cp.async src_size must lower to an integer");
+                assert_eq!(src_size_ty.width(), 32);
+            }
+        }
+    }
+
+    assert_eq!(
+        matches, 1,
+        "missing exact {copy_size}-byte zero-fill cp.async asm"
+    );
+    Ok(())
+}
+
+// =============================================================================
+// Generated packed arithmetic lowering tests
+// =============================================================================
diff --git a/crates/mir-lower/tests/lowering_test/inline_ptx.rs b/crates/mir-lower/tests/lowering_test/inline_ptx.rs
new file mode 100644
index 0000000000..e7cb6a9235
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/inline_ptx.rs
@@ -0,0 +1,374 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_nvvm::ops as nvvm;
+use llvm_export::ops as llvm;
+use pliron::builtin::op_interfaces::SymbolOpInterface;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+use crate::common::{append_return, build_test_kernel, lowered_kernel_body, make_test_ctx};
+
+#[test]
+fn test_inline_ptx_op_lowers_to_inline_asm_attrs() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
+    let input = entry.deref(&ctx).get_argument(0);
+
+    let inline_ptx = nvvm::InlinePtxOp::build(
+        &mut ctx,
+        vec![i32_ty.into()],
+        vec![input],
+        "add.u32 $0, $1, $1;",
+        "=r,r",
+        true,
+        true,
+    );
+    inline_ptx.insert_at_back(entry, &ctx);
+    let register_only_ptx = nvvm::InlinePtxOp::build(
+        &mut ctx,
+        vec![i32_ty.into()],
+        vec![input],
+        "mul.lo.u32 $0, $1, $1;",
+        "=r,r",
+        false,
+        true,
+    );
+    register_only_ptx.insert_at_back(entry, &ctx);
+    let may_diverge_ptx = nvvm::InlinePtxOp::build(
+        &mut ctx,
+        vec![i32_ty.into()],
+        vec![input],
+        "cvt.u32.u32 $0, $1;",
+        "=r,r",
+        false,
+        false,
+    );
+    may_diverge_ptx.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    let mut found_conservative = false;
+    let mut found_register_only = false;
+    let mut found_may_diverge = false;
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = inline_asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|s| String::from((*s).clone()));
+                match template.as_deref() {
+                    Some("add.u32 $0, $1, $1;") => {
+                        found_conservative = true;
+                        assert_eq!(
+                            inline_asm
+                                .get_attr_inline_asm_constraints(&ctx)
+                                .map(|s| String::from((*s).clone()))
+                                .as_deref(),
+                            Some("=r,r")
+                        );
+                        assert!(
+                            inline_asm
+                                .get_attr_inline_asm_convergent(&ctx)
+                                .is_some_and(|b| bool::from((*b).clone()))
+                        );
+                        assert!(llvm::inline_asm_sideeffect(
+                            &ctx,
+                            inline_asm.get_operation()
+                        ));
+                    }
+                    Some("mul.lo.u32 $0, $1, $1;") => {
+                        found_register_only = true;
+                        assert_eq!(
+                            inline_asm
+                                .get_attr_inline_asm_constraints(&ctx)
+                                .map(|s| String::from((*s).clone()))
+                                .as_deref(),
+                            Some("=r,r")
+                        );
+                        assert!(
+                            inline_asm
+                                .get_attr_inline_asm_convergent(&ctx)
+                                .is_some_and(|b| bool::from((*b).clone()))
+                        );
+                        assert!(!llvm::inline_asm_sideeffect(
+                            &ctx,
+                            inline_asm.get_operation()
+                        ));
+                    }
+                    Some("cvt.u32.u32 $0, $1;") => {
+                        found_may_diverge = true;
+                        assert_eq!(
+                            inline_asm
+                                .get_attr_inline_asm_constraints(&ctx)
+                                .map(|s| String::from((*s).clone()))
+                                .as_deref(),
+                            Some("=r,r")
+                        );
+                        assert!(
+                            inline_asm
+                                .get_attr_inline_asm_convergent(&ctx)
+                                .is_some_and(|b| !bool::from((*b).clone()))
+                        );
+                        assert!(!llvm::inline_asm_sideeffect(
+                            &ctx,
+                            inline_asm.get_operation()
+                        ));
+                    }
+                    _ => continue,
+                }
+            }
+        }
+    }
+
+    assert!(
+        found_conservative,
+        "Expected conservative inline PTX asm op"
+    );
+    assert!(
+        found_register_only,
+        "Expected register-only inline PTX asm op"
+    );
+    assert!(found_may_diverge, "Expected may-diverge inline PTX asm op");
+    Ok(())
+}
+
+#[test]
+fn test_multi_result_inline_ptx_lowers_to_struct_asm_and_extractvalues() -> Result<(), anyhow::Error>
+{
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::r#type::Typed;
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
+    let input = entry.deref(&ctx).get_argument(0);
+
+    let inline_ptx = nvvm::InlinePtxOp::build(
+        &mut ctx,
+        vec![i32_ty.into(), i32_ty.into()],
+        vec![input],
+        "add.u32 $0, $2, $2; mul.lo.u32 $1, $2, $2;",
+        "=r,=r,r",
+        true,
+        false,
+    );
+    let expected_location = Location::Named {
+        name: "source-inline-ptx".to_string(),
+        child_loc: Box::new(Location::Unknown),
+    };
+    inline_ptx
+        .deref_mut(&ctx)
+        .set_loc(expected_location.clone());
+    inline_ptx.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    let mut asm_result = None;
+    let mut extract_indices = Vec::new();
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
+            assert_eq!(
+                inline_asm.get_operation().deref(&ctx).loc(),
+                expected_location
+            );
+            assert_eq!(
+                inline_asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|s| String::from((*s).clone()))
+                    .as_deref(),
+                Some("add.u32 $0, $2, $2; mul.lo.u32 $1, $2, $2;")
+            );
+            assert_eq!(
+                inline_asm
+                    .get_attr_inline_asm_constraints(&ctx)
+                    .map(|s| String::from((*s).clone()))
+                    .as_deref(),
+                Some("=r,=r,r")
+            );
+            let result = inline_asm.get_operation().deref(&ctx).get_result(0);
+            let result_ty = result.get_type(&ctx);
+            let result_ty = result_ty.deref(&ctx);
+            let struct_ty = result_ty
+                .downcast_ref::<llvm_types::StructType>()
+                .expect("multi-output inline PTX must return an LLVM struct");
+            assert_eq!(struct_ty.num_fields(), 2);
+            for index in 0..2 {
+                assert_eq!(
+                    struct_ty
+                        .field_type(index)
+                        .deref(&ctx)
+                        .downcast_ref::<IntegerType>()
+                        .expect("multi-output inline PTX struct field must stay i32")
+                        .width(),
+                    32
+                );
+            }
+            asm_result = Some(result);
+        } else if let Some(extract) = Operation::get_op::<llvm::ExtractValueOp>(op, &ctx) {
+            assert_eq!(extract.get_operation().deref(&ctx).loc(), expected_location);
+            let aggregate = extract.get_operation().deref(&ctx).get_operand(0);
+            assert_eq!(
+                Some(aggregate),
+                asm_result,
+                "extractvalue must consume the struct-returning asm result"
+            );
+            extract_indices.push(extract.indices(&ctx));
+        }
+    }
+
+    assert!(
+        asm_result.is_some(),
+        "Expected struct-returning inline PTX asm op"
+    );
+    assert_eq!(
+        extract_indices,
+        vec![vec![0], vec![1]],
+        "each output must be extracted once, in constraint order"
+    );
+    Ok(())
+}
+
+#[test]
+fn test_inline_ptx_supports_thirty_two_tied_f32_results() -> Result<(), anyhow::Error> {
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::types::FP32Type;
+    use pliron::r#type::Typed;
+
+    const ACCUMULATOR_LEN: usize = 32;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty.into(); ACCUMULATOR_LEN]);
+
+    let inputs = (0..ACCUMULATOR_LEN)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect::<Vec<_>>();
+
+    let template = (0..ACCUMULATOR_LEN)
+        .map(|index| format!("mov.f32 ${index}, ${index};"))
+        .collect::<Vec<_>>()
+        .join(" ");
+
+    let mut constraints = vec!["=f".to_string(); ACCUMULATOR_LEN];
+    constraints.extend((0..ACCUMULATOR_LEN).map(|index| index.to_string()));
+    let constraints = constraints.join(",");
+
+    let inline_ptx = nvvm::InlinePtxOp::build(
+        &mut ctx,
+        vec![f32_ty.into(); ACCUMULATOR_LEN],
+        inputs,
+        &template,
+        &constraints,
+        true,
+        true,
+    );
+    inline_ptx.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut asm_result = None;
+    let mut extract_indices = Vec::new();
+
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) {
+            assert_eq!(
+                inline_asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .as_deref(),
+                Some(template.as_str()),
+            );
+
+            assert_eq!(
+                inline_asm
+                    .get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .as_deref(),
+                Some(constraints.as_str()),
+            );
+
+            let result = inline_asm.get_operation().deref(&ctx).get_result(0);
+            let result_ty = result.get_type(&ctx);
+            let result_ty = result_ty.deref(&ctx);
+
+            let struct_ty = result_ty
+                .downcast_ref::<llvm_types::StructType>()
+                .expect("32-output inline PTX must return an LLVM struct");
+
+            assert_eq!(
+                struct_ty.num_fields(),
+                ACCUMULATOR_LEN,
+                "inline PTX must return exactly 32 accumulator values",
+            );
+
+            for index in 0..ACCUMULATOR_LEN {
+                assert!(
+                    struct_ty
+                        .field_type(index)
+                        .deref(&ctx)
+                        .downcast_ref::<FP32Type>()
+                        .is_some(),
+                    "inline PTX result field {index} must remain f32",
+                );
+            }
+
+            assert!(
+                asm_result.replace(result).is_none(),
+                "expected exactly one inline PTX operation",
+            );
+        } else if let Some(extract) = Operation::get_op::<llvm::ExtractValueOp>(op, &ctx) {
+            let aggregate = extract.get_operation().deref(&ctx).get_operand(0);
+
+            assert_eq!(
+                Some(aggregate),
+                asm_result,
+                "extractvalue must consume the struct-returning asm result",
+            );
+
+            extract_indices.push(extract.indices(&ctx));
+        }
+    }
+
+    assert!(
+        asm_result.is_some(),
+        "expected a struct-returning inline PTX asm operation",
+    );
+
+    let expected_indices = (0..ACCUMULATOR_LEN)
+        .map(|index| vec![index as u32])
+        .collect::<Vec<_>>();
+
+    assert_eq!(
+        extract_indices, expected_indices,
+        "each accumulator output must be extracted exactly once and in constraint order",
+    );
+
+    Ok(())
+}
diff --git a/crates/mir-lower/tests/lowering_test/main.rs b/crates/mir-lower/tests/lowering_test/main.rs
new file mode 100644
index 0000000000..cdc0a69728
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/main.rs
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Tests build kinded fixture types directly; production minting lives in
+// mir-importer's facts.rs (see the workspace clippy.toml disallowed-methods).
+#![allow(clippy::disallowed_methods)]
+
+mod atomics_fences;
+mod barriers_sync;
+mod calls_and_values;
+mod common;
+mod cp_async;
+mod inline_ptx;
+mod math_conversions;
+mod matrix_memory;
+mod mma;
+mod sregs_and_warp;
+mod wgmma_lowering;
+mod wgmma_rejections;
diff --git a/crates/mir-lower/tests/lowering_test/math_conversions.rs b/crates/mir-lower/tests/lowering_test/math_conversions.rs
new file mode 100644
index 0000000000..7fa48b5396
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/math_conversions.rs
@@ -0,0 +1,1712 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::ops as mir;
+use dialect_nvvm::ops as nvvm;
+use llvm_export::ops as llvm;
+use pliron::builtin::op_interfaces::{CallOpCallable, CallOpInterface, SymbolOpInterface};
+use pliron::builtin::ops::ModuleOp;
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+use crate::common::{append_return, build_test_kernel, lowered_kernel_body, make_test_ctx};
+
+#[test]
+fn test_fast_float_intrinsics_lower_to_explicit_fast_binops() -> Result<(), anyhow::Error> {
+    use dialect_mir::rust_intrinsics;
+    use llvm_export::attributes::{FastmathFlags, FastmathFlagsAttr};
+    use llvm_export::op_interfaces::FastMathFlags;
+    use pliron::builtin::attributes::StringAttr;
+    use pliron::builtin::op_interfaces::CallOpInterface;
+    use pliron::builtin::types::{FP32Type, FP64Type};
+    use pliron::r#type::{TypeHandle, Typed};
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let f64_ty = FP64Type::get(&ctx);
+    let f32_ty_obj: TypeHandle = f32_ty.into();
+    let f64_ty_obj: TypeHandle = f64_ty.into();
+    let (module_ptr, entry) = build_test_kernel(
+        &mut ctx,
+        vec![f32_ty_obj, f32_ty_obj, f64_ty_obj, f64_ty_obj],
+    );
+    let f32_lhs = entry.deref(&ctx).get_argument(0);
+    let f32_rhs = entry.deref(&ctx).get_argument(1);
+    let f64_lhs = entry.deref(&ctx).get_argument(2);
+    let f64_rhs = entry.deref(&ctx).get_argument(3);
+
+    for (callee, lhs, rhs, result_ty) in [
+        (
+            rust_intrinsics::CALLEE_FADD_FAST,
+            f32_lhs,
+            f32_rhs,
+            f32_ty_obj,
+        ),
+        (
+            rust_intrinsics::CALLEE_FSUB_FAST,
+            f32_lhs,
+            f32_rhs,
+            f32_ty_obj,
+        ),
+        (
+            rust_intrinsics::CALLEE_FMUL_FAST,
+            f32_lhs,
+            f32_rhs,
+            f32_ty_obj,
+        ),
+        (
+            rust_intrinsics::CALLEE_FDIV_FAST,
+            f32_lhs,
+            f32_rhs,
+            f32_ty_obj,
+        ),
+        (
+            rust_intrinsics::CALLEE_FREM_FAST,
+            f32_lhs,
+            f32_rhs,
+            f32_ty_obj,
+        ),
+        (
+            rust_intrinsics::CALLEE_FADD_FAST,
+            f64_lhs,
+            f64_rhs,
+            f64_ty_obj,
+        ),
+        (
+            rust_intrinsics::CALLEE_FSUB_FAST,
+            f64_lhs,
+            f64_rhs,
+            f64_ty_obj,
+        ),
+        (
+            rust_intrinsics::CALLEE_FMUL_FAST,
+            f64_lhs,
+            f64_rhs,
+            f64_ty_obj,
+        ),
+        (
+            rust_intrinsics::CALLEE_FDIV_FAST,
+            f64_lhs,
+            f64_rhs,
+            f64_ty_obj,
+        ),
+        (
+            rust_intrinsics::CALLEE_FREM_FAST,
+            f64_lhs,
+            f64_rhs,
+            f64_ty_obj,
+        ),
+    ] {
+        let call_ptr = Operation::new(
+            &mut ctx,
+            mir::MirCallOp::get_concrete_op_info(),
+            vec![result_ty],
+            vec![lhs, rhs],
+            vec![],
+            0,
+        );
+        let call = mir::MirCallOp::new(call_ptr);
+        call.set_attr_callee(&ctx, StringAttr::new(callee.to_string()));
+        call_ptr.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    let explicit_fast_flags: FastmathFlagsAttr = FastmathFlags::FAST.into();
+    assert_ne!(
+        explicit_fast_flags,
+        FastmathFlagsAttr::default(),
+        "FastmathFlagsAttr::default() is empty; f*_fast must use explicit fast flags"
+    );
+
+    let mut fadd_counts = [0usize; 2];
+    let mut fsub_counts = [0usize; 2];
+    let mut fmul_counts = [0usize; 2];
+    let mut fdiv_counts = [0usize; 2];
+    let mut frem_counts = [0usize; 2];
+
+    macro_rules! count_fast_binop {
+        ($body_op:expr, $op_ty:ty, $counts:ident, $name:literal) => {
+            if let Some(op) = Operation::get_op::<$op_ty>($body_op, &ctx) {
+                assert_eq!(
+                    op.fast_math_flags(&ctx),
+                    explicit_fast_flags,
+                    concat!($name, " must carry explicit LLVM fast-math flags")
+                );
+                let result_ty = op.get_operation().deref(&ctx).get_result(0).get_type(&ctx);
+                if result_ty == f32_ty_obj {
+                    $counts[0] += 1;
+                } else if result_ty == f64_ty_obj {
+                    $counts[1] += 1;
+                } else {
+                    panic!(concat!($name, " lowered to an unexpected result type"));
+                }
+            }
+        };
+    }
+
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                assert!(
+                    Operation::get_op::<mir::MirCallOp>(body_op, &ctx).is_none(),
+                    "f*_fast placeholder mir.call must not survive MIR lowering"
+                );
+                if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
+                    && let CallOpCallable::Direct(sym) = call.callee(&ctx)
+                {
+                    let callee = sym.to_string();
+                    assert!(
+                        !callee.starts_with(rust_intrinsics::PLACEHOLDER_PREFIX),
+                        "lowered LLVM must not call unresolved Rust intrinsic placeholder `{callee}`"
+                    );
+                }
+                count_fast_binop!(body_op, llvm::FAddOp, fadd_counts, "fadd_fast");
+                count_fast_binop!(body_op, llvm::FSubOp, fsub_counts, "fsub_fast");
+                count_fast_binop!(body_op, llvm::FMulOp, fmul_counts, "fmul_fast");
+                count_fast_binop!(body_op, llvm::FDivOp, fdiv_counts, "fdiv_fast");
+                count_fast_binop!(body_op, llvm::FRemOp, frem_counts, "frem_fast");
+            }
+        }
+    }
+
+    assert_eq!(fadd_counts, [1, 1], "fadd_fast must lower for f32 and f64");
+    assert_eq!(fsub_counts, [1, 1], "fsub_fast must lower for f32 and f64");
+    assert_eq!(fmul_counts, [1, 1], "fmul_fast must lower for f32 and f64");
+    assert_eq!(fdiv_counts, [1, 1], "fdiv_fast must lower for f32 and f64");
+    assert_eq!(frem_counts, [1, 1], "frem_fast must lower for f32 and f64");
+
+    Ok(())
+}
+
+#[test]
+fn test_ex2_approx_f16_uses_exact_pure_i16_inline_ptx_on_both_backends() -> Result<(), anyhow::Error>
+{
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::r#type::Typed;
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        let mut ctx = make_test_ctx();
+        let i16_ty = IntegerType::get(&ctx, 16, Signedness::Unsigned);
+        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i16_ty.into()]);
+        let operand = entry.deref(&ctx).get_argument(0);
+        nvvm::ScalarMathOp::build(
+            &mut ctx,
+            operand,
+            nvvm::ScalarMathFormatAttr::F16,
+            nvvm::ScalarMathOperationAttr::Ex2,
+            nvvm::ScalarMathPrecisionAttr::Approx,
+            nvvm::ScalarMathSubnormalAttr::Preserve,
+        )
+        .insert_at_back(entry, &ctx);
+        append_return(&mut ctx, entry);
+
+        mir_lower::lower_mir_to_llvm_with_options(
+            &mut ctx,
+            module_ptr,
+            mir_lower::LoweringOptions {
+                intrinsic_backend: backend,
+                ..Default::default()
+            },
+        )
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+        let inline_asm = lowered_kernel_body(&ctx, module_ptr)
+            .into_iter()
+            .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(op, &ctx))
+            .collect::<Vec<_>>();
+        assert_eq!(inline_asm.len(), 1);
+        let inline_asm = &inline_asm[0];
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some("ex2.approx.f16 $0, $1;")
+        );
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_constraints(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some("=h,h")
+        );
+        assert_eq!(llvm::asm_kind(&ctx, inline_asm), llvm::AsmKind::Pure);
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_convergent(&ctx)
+                .map(|value| bool::from((*value).clone())),
+            Some(false)
+        );
+
+        let op = inline_asm.get_operation().deref(&ctx);
+        assert_eq!(op.get_num_operands(), 1);
+        assert_eq!(op.get_num_results(), 1);
+        for ty in [
+            op.get_operand(0).get_type(&ctx),
+            op.get_result(0).get_type(&ctx),
+        ] {
+            let ty = ty.deref(&ctx);
+            let integer = ty
+                .downcast_ref::<IntegerType>()
+                .expect("f16 values use an i16 transport type");
+            assert_eq!(integer.width(), 16);
+        }
+
+        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+            .expect("ex2.approx.f16 module exports to LLVM IR");
+        assert!(
+            ir.contains("call i16 asm \"ex2.approx.f16 $0, $1;\", \"=h,h\"(i16"),
+            "{ir}"
+        );
+        assert!(!ir.contains("asm sideeffect"), "{ir}");
+        assert!(!ir.contains("~{memory}"), "{ir}");
+    }
+    Ok(())
+}
+
+#[test]
+fn test_ex2_approx_f16_lowering_rejects_wrong_type_and_format() {
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        let mut wrong_type_ctx = make_test_ctx();
+        let f32_ty = FP32Type::get(&wrong_type_ctx);
+        let (module_ptr, entry) = build_test_kernel(&mut wrong_type_ctx, vec![f32_ty.into()]);
+        let operand = entry.deref(&wrong_type_ctx).get_argument(0);
+        nvvm::ScalarMathOp::build(
+            &mut wrong_type_ctx,
+            operand,
+            nvvm::ScalarMathFormatAttr::F16,
+            nvvm::ScalarMathOperationAttr::Ex2,
+            nvvm::ScalarMathPrecisionAttr::Approx,
+            nvvm::ScalarMathSubnormalAttr::Preserve,
+        )
+        .insert_at_back(entry, &wrong_type_ctx);
+        append_return(&mut wrong_type_ctx, entry);
+        let error = mir_lower::lower_mir_to_llvm_with_options(
+            &mut wrong_type_ctx,
+            module_ptr,
+            mir_lower::LoweringOptions {
+                intrinsic_backend: backend,
+                ..Default::default()
+            },
+        )
+        .expect_err("an f16 operation with an f32 operand must fail closed")
+        .to_string();
+        assert!(
+            error.contains("nvvm.scalar_math types do not match its format"),
+            "{error}"
+        );
+
+        let mut wrong_format_ctx = make_test_ctx();
+        let i16_ty = IntegerType::get(&wrong_format_ctx, 16, Signedness::Unsigned);
+        let (module_ptr, entry) = build_test_kernel(&mut wrong_format_ctx, vec![i16_ty.into()]);
+        let operand = entry.deref(&wrong_format_ctx).get_argument(0);
+        nvvm::ScalarMathOp::build(
+            &mut wrong_format_ctx,
+            operand,
+            nvvm::ScalarMathFormatAttr::F16,
+            nvvm::ScalarMathOperationAttr::Ex2,
+            nvvm::ScalarMathPrecisionAttr::Approx,
+            nvvm::ScalarMathSubnormalAttr::Ftz,
+        )
+        .insert_at_back(entry, &wrong_format_ctx);
+        append_return(&mut wrong_format_ctx, entry);
+        let error = mir_lower::lower_mir_to_llvm_with_options(
+            &mut wrong_format_ctx,
+            module_ptr,
+            mir_lower::LoweringOptions {
+                intrinsic_backend: backend,
+                ..Default::default()
+            },
+        )
+        .expect_err("unadmitted ex2.approx.ftz.f16 must fail closed")
+        .to_string();
+        assert!(
+            error.contains("nvvm.scalar_math variant is not admitted"),
+            "{error}"
+        );
+    }
+}
+
+// =============================================================================
+// Integer dot product (dp4a / dp2a) lowering tests
+// =============================================================================
+
+const DOT_PRODUCT_TYPED_INTRINSICS: [&str; 4] = [
+    "llvm_nvvm_idp4a_s_s",
+    "llvm_nvvm_idp4a_u_u",
+    "llvm_nvvm_idp2a_s_s",
+    "llvm_nvvm_idp2a_u_u",
+];
+
+const DOT_PRODUCT_PTX: [&str; 4] = [
+    "dp4a.s32.s32 $0, $1, $2, $3;",
+    "dp4a.u32.u32 $0, $1, $2, $3;",
+    "dp2a.lo.s32.s32 $0, $1, $2, $3;",
+    "dp2a.lo.u32.u32 $0, $1, $2, $3;",
+];
+
+fn lower_all_dot_product_forms(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![i32_ty.into(), i32_ty.into(), i32_ty.into()]);
+    let operands = (0..3)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect::<Vec<_>>();
+    for op_info in [
+        nvvm::Dp4aS32Op::get_concrete_op_info(),
+        nvvm::Dp4aU32Op::get_concrete_op_info(),
+        nvvm::Dp2aS32Op::get_concrete_op_info(),
+        nvvm::Dp2aU32Op::get_concrete_op_info(),
+    ] {
+        Operation::new(
+            &mut ctx,
+            op_info,
+            vec![i32_ty.into()],
+            operands.clone(),
+            vec![],
+            0,
+        )
+        .insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn test_dot_product_llvm_nvptx_uses_typed_intrinsics_and_low_selector() -> Result<(), anyhow::Error>
+{
+    use pliron::builtin::attributes::IntegerAttr;
+
+    let (ctx, module_ptr) = lower_all_dot_product_forms(mir_lower::IntrinsicBackend::LlvmNvptx)?;
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let mut calls = Vec::new();
+    for op in body {
+        assert!(
+            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+            "LLVM-NVPTX dot products must use typed intrinsics"
+        );
+        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+            continue;
+        };
+        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+            continue;
+        };
+        let callee = callee.to_string();
+        if !callee.starts_with("llvm_nvvm_idp") {
+            continue;
+        }
+        let expected_arity = if callee.contains("idp2a") { 4 } else { 3 };
+        assert_eq!(op.deref(&ctx).get_num_operands(), expected_arity);
+        if expected_arity == 4 {
+            let selector = op.deref(&ctx).get_operand(2);
+            let defining_op = selector.defining_op().expect("selector is a constant");
+            let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
+                .expect("selector is an LLVM constant");
+            let attribute = constant.get_value(&ctx);
+            let integer = attribute
+                .downcast_ref::<IntegerAttr>()
+                .expect("selector constant is an integer");
+            assert_eq!(integer.value().bw(), 1);
+            assert_eq!(integer.value().to_u64(), 0, "dp2a must select `.lo`");
+        }
+        calls.push(callee);
+    }
+    calls.sort();
+    let mut expected = DOT_PRODUCT_TYPED_INTRINSICS.map(str::to_owned);
+    expected.sort();
+    assert_eq!(calls, expected);
+    Ok(())
+}
+
+#[test]
+fn test_dot_product_libnvvm_uses_exact_pure_inline_ptx() -> Result<(), anyhow::Error> {
+    let (ctx, module_ptr) = lower_all_dot_product_forms(mir_lower::IntrinsicBackend::LibNvvm)?;
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let mut inline_ptx = Vec::new();
+    for op in body {
+        assert!(
+            Operation::get_op::<llvm::CallOp>(op, &ctx).is_none(),
+            "libNVVM dot products must not use typed intrinsic calls"
+        );
+        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            continue;
+        };
+        inline_ptx.push(
+            inline_asm
+                .get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .unwrap_or_default(),
+        );
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_constraints(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some("=r,r,r,r")
+        );
+        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
+        assert_eq!(op.deref(&ctx).get_num_operands(), 3);
+        assert_eq!(op.deref(&ctx).get_num_results(), 1);
+    }
+    inline_ptx.sort();
+    let mut expected = DOT_PRODUCT_PTX.map(str::to_owned);
+    expected.sort();
+    assert_eq!(inline_ptx, expected);
+    Ok(())
+}
+
+// =============================================================================
+// Byte permutation lowering tests
+// =============================================================================
+
+const PRMT_TYPED_INTRINSICS: [(&str, usize); 7] = [
+    ("llvm_nvvm_prmt", 3),
+    ("llvm_nvvm_prmt_f4e", 3),
+    ("llvm_nvvm_prmt_b4e", 3),
+    ("llvm_nvvm_prmt_rc8", 2),
+    ("llvm_nvvm_prmt_ecl", 2),
+    ("llvm_nvvm_prmt_ecr", 2),
+    ("llvm_nvvm_prmt_rc16", 2),
+];
+
+const PRMT_INLINE_PTX: [(&str, &str, usize); 7] = [
+    ("prmt.b32 $0, $1, $2, $3;", "=r,r,r,r", 3),
+    ("prmt.b32.f4e $0, $1, $2, $3;", "=r,r,r,r", 3),
+    ("prmt.b32.b4e $0, $1, $2, $3;", "=r,r,r,r", 3),
+    ("prmt.b32.rc8 $0, $1, 0, $2;", "=r,r,r", 2),
+    ("prmt.b32.ecl $0, $1, 0, $2;", "=r,r,r", 2),
+    ("prmt.b32.ecr $0, $1, 0, $2;", "=r,r,r", 2),
+    ("prmt.b32.rc16 $0, $1, 0, $2;", "=r,r,r", 2),
+];
+
+fn lower_all_prmt_modes(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![i32_ty.into(), i32_ty.into(), i32_ty.into()]);
+    let operands = (0..3)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect::<Vec<_>>();
+
+    for mode in [
+        nvvm::PrmtModeAttr::Generic,
+        nvvm::PrmtModeAttr::F4e,
+        nvvm::PrmtModeAttr::B4e,
+    ] {
+        nvvm::PrmtOp::build(&mut ctx, operands.clone(), mode).insert_at_back(entry, &ctx);
+    }
+    for mode in [
+        nvvm::PrmtModeAttr::Rc8,
+        nvvm::PrmtModeAttr::Ecl,
+        nvvm::PrmtModeAttr::Ecr,
+        nvvm::PrmtModeAttr::Rc16,
+    ] {
+        nvvm::PrmtOp::build(&mut ctx, vec![operands[0], operands[2]], mode)
+            .insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn test_prmt_llvm_nvptx_uses_exact_typed_intrinsics() -> Result<(), anyhow::Error> {
+    let (ctx, module_ptr) = lower_all_prmt_modes(mir_lower::IntrinsicBackend::LlvmNvptx)?;
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let mut calls = Vec::new();
+    for op in body {
+        assert!(
+            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+            "LLVM-NVPTX byte permutations must use typed intrinsics"
+        );
+        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+            continue;
+        };
+        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+            continue;
+        };
+        let callee = callee.to_string();
+        let Some((_, expected_arity)) = PRMT_TYPED_INTRINSICS
+            .iter()
+            .find(|(expected, _)| *expected == callee)
+        else {
+            continue;
+        };
+        assert_eq!(op.deref(&ctx).get_num_operands(), *expected_arity);
+        calls.push((callee, *expected_arity));
+    }
+    calls.sort();
+    let mut expected = PRMT_TYPED_INTRINSICS.map(|(name, arity)| (name.to_owned(), arity));
+    expected.sort();
+    assert_eq!(calls, expected);
+    Ok(())
+}
+
+#[test]
+fn test_prmt_libnvvm_uses_exact_pure_inline_ptx() -> Result<(), anyhow::Error> {
+    let (ctx, module_ptr) = lower_all_prmt_modes(mir_lower::IntrinsicBackend::LibNvvm)?;
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let mut inline_ptx = Vec::new();
+    for op in body {
+        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+        {
+            assert!(
+                !callee.to_string().starts_with("llvm_nvvm_prmt"),
+                "libNVVM byte permutations must not use typed intrinsic calls"
+            );
+        }
+        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            continue;
+        };
+        let template = inline_asm
+            .get_attr_inline_asm_template(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .unwrap_or_default();
+        let Some((_, expected_constraints, expected_arity)) = PRMT_INLINE_PTX
+            .iter()
+            .find(|(expected, _, _)| *expected == template)
+        else {
+            continue;
+        };
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_constraints(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some(*expected_constraints)
+        );
+        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
+        assert_eq!(op.deref(&ctx).get_num_operands(), *expected_arity);
+        assert_eq!(op.deref(&ctx).get_num_results(), 1);
+        inline_ptx.push((template, *expected_constraints, *expected_arity));
+    }
+    inline_ptx.sort();
+    let mut expected = PRMT_INLINE_PTX
+        .map(|(template, constraints, arity)| (template.to_owned(), constraints, arity));
+    expected.sort();
+    assert_eq!(inline_ptx, expected);
+    Ok(())
+}
+
+#[test]
+fn test_generated_packed_arithmetic_lowers_to_exact_pure_inline_asm() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![i32_ty.into(), i32_ty.into(), i32_ty.into()]);
+
+    type OpInfo = (
+        fn(pliron::context::Ptr<Operation>) -> pliron::op::OpObj,
+        std::any::TypeId,
+    );
+    let cases: [(OpInfo, usize, &str, &str); 18] = [
+        (
+            nvvm::FmaBf16x2Op::get_concrete_op_info(),
+            3,
+            "fma.rn.bf16x2 $0, $1, $2, $3;",
+            "=r,r,r,r",
+        ),
+        (
+            nvvm::FmaReluBf16x2Op::get_concrete_op_info(),
+            3,
+            "fma.rn.relu.bf16x2 $0, $1, $2, $3;",
+            "=r,r,r,r",
+        ),
+        (
+            nvvm::AddBf16x2Op::get_concrete_op_info(),
+            2,
+            "add.rn.bf16x2 $0, $1, $2;",
+            "=r,r,r",
+        ),
+        (
+            nvvm::SubBf16x2Op::get_concrete_op_info(),
+            2,
+            "sub.rn.bf16x2 $0, $1, $2;",
+            "=r,r,r",
+        ),
+        (
+            nvvm::MulBf16x2Op::get_concrete_op_info(),
+            2,
+            "mul.rn.bf16x2 $0, $1, $2;",
+            "=r,r,r",
+        ),
+        (
+            nvvm::MinBf16x2Op::get_concrete_op_info(),
+            2,
+            "min.bf16x2 $0, $1, $2;",
+            "=r,r,r",
+        ),
+        (
+            nvvm::MaxBf16x2Op::get_concrete_op_info(),
+            2,
+            "max.bf16x2 $0, $1, $2;",
+            "=r,r,r",
+        ),
+        (
+            nvvm::NegBf16x2Op::get_concrete_op_info(),
+            1,
+            "neg.bf16x2 $0, $1;",
+            "=r,r",
+        ),
+        (
+            nvvm::AbsBf16x2Op::get_concrete_op_info(),
+            1,
+            "abs.bf16x2 $0, $1;",
+            "=r,r",
+        ),
+        (
+            nvvm::FmaF16x2Op::get_concrete_op_info(),
+            3,
+            "fma.rn.f16x2 $0, $1, $2, $3;",
+            "=r,r,r,r",
+        ),
+        (
+            nvvm::FmaReluF16x2Op::get_concrete_op_info(),
+            3,
+            "fma.rn.relu.f16x2 $0, $1, $2, $3;",
+            "=r,r,r,r",
+        ),
+        (
+            nvvm::AddF16x2Op::get_concrete_op_info(),
+            2,
+            "add.rn.f16x2 $0, $1, $2;",
+            "=r,r,r",
+        ),
+        (
+            nvvm::SubF16x2Op::get_concrete_op_info(),
+            2,
+            "sub.rn.f16x2 $0, $1, $2;",
+            "=r,r,r",
+        ),
+        (
+            nvvm::MulF16x2Op::get_concrete_op_info(),
+            2,
+            "mul.rn.f16x2 $0, $1, $2;",
+            "=r,r,r",
+        ),
+        (
+            nvvm::MinF16x2Op::get_concrete_op_info(),
+            2,
+            "min.f16x2 $0, $1, $2;",
+            "=r,r,r",
+        ),
+        (
+            nvvm::MaxF16x2Op::get_concrete_op_info(),
+            2,
+            "max.f16x2 $0, $1, $2;",
+            "=r,r,r",
+        ),
+        (
+            nvvm::NegF16x2Op::get_concrete_op_info(),
+            1,
+            "neg.f16x2 $0, $1;",
+            "=r,r",
+        ),
+        (
+            nvvm::AbsF16x2Op::get_concrete_op_info(),
+            1,
+            "abs.f16x2 $0, $1;",
+            "=r,r",
+        ),
+    ];
+
+    let operands = [
+        entry.deref(&ctx).get_argument(0),
+        entry.deref(&ctx).get_argument(1),
+        entry.deref(&ctx).get_argument(2),
+    ];
+    for &(op_info, operand_count, _, _) in &cases {
+        let op = Operation::new(
+            &mut ctx,
+            op_info,
+            vec![i32_ty.into()],
+            operands[..operand_count].to_vec(),
+            vec![],
+            0,
+        );
+        op.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    let mut lowered = Vec::new();
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let inline_asm_op = inline_asm.get_operation();
+                let operand_count = inline_asm_op.deref(&ctx).operands().count();
+                let result_count = inline_asm_op.deref(&ctx).get_num_results();
+                lowered.push((
+                    inline_asm
+                        .get_attr_inline_asm_template(&ctx)
+                        .map(|s| String::from((*s).clone()))
+                        .expect("packed inline asm must have a template"),
+                    inline_asm
+                        .get_attr_inline_asm_constraints(&ctx)
+                        .map(|s| String::from((*s).clone()))
+                        .expect("packed inline asm must have constraints"),
+                    llvm::asm_kind_opt(&ctx, &inline_asm),
+                    inline_asm
+                        .get_attr_inline_asm_convergent(&ctx)
+                        .map(|b| bool::from((*b).clone())),
+                    operand_count,
+                    result_count,
+                ));
+            }
+        }
+    }
+
+    assert_eq!(
+        lowered.len(),
+        cases.len(),
+        "each packed operation must lower to exactly one inline-asm op"
+    );
+    for &(_, expected_operand_count, expected_template, expected_constraints) in &cases {
+        let matches: Vec<_> = lowered
+            .iter()
+            .filter(|(template, _, _, _, _, _)| template == expected_template)
+            .collect();
+        assert_eq!(
+            matches.len(),
+            1,
+            "expected one exact `{expected_template}` lowering"
+        );
+        let (_, constraints, kind, convergent, operand_count, result_count) = matches[0];
+        assert_eq!(constraints, expected_constraints, "{expected_template}");
+        assert_eq!(*kind, Some(llvm::AsmKind::Pure), "{expected_template}");
+        assert_eq!(*convergent, Some(false), "{expected_template}");
+        assert_eq!(
+            *operand_count, expected_operand_count,
+            "{expected_template} input arity"
+        );
+        assert_eq!(*result_count, 1, "{expected_template} result arity");
+    }
+
+    Ok(())
+}
+
+#[test]
+fn test_generated_integer_minmax_lowers_to_exact_pure_inline_asm() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into(), i32_ty.into()]);
+
+    type OpInfo = (
+        fn(pliron::context::Ptr<Operation>) -> pliron::op::OpObj,
+        std::any::TypeId,
+    );
+    let cases: [(OpInfo, &str); 8] = [
+        (
+            nvvm::MinReluS32Op::get_concrete_op_info(),
+            "min.relu.s32 $0, $1, $2;",
+        ),
+        (
+            nvvm::MaxReluS32Op::get_concrete_op_info(),
+            "max.relu.s32 $0, $1, $2;",
+        ),
+        (
+            nvvm::MinS16x2Op::get_concrete_op_info(),
+            "min.s16x2 $0, $1, $2;",
+        ),
+        (
+            nvvm::MaxS16x2Op::get_concrete_op_info(),
+            "max.s16x2 $0, $1, $2;",
+        ),
+        (
+            nvvm::MinU16x2Op::get_concrete_op_info(),
+            "min.u16x2 $0, $1, $2;",
+        ),
+        (
+            nvvm::MaxU16x2Op::get_concrete_op_info(),
+            "max.u16x2 $0, $1, $2;",
+        ),
+        (
+            nvvm::MinReluS16x2Op::get_concrete_op_info(),
+            "min.relu.s16x2 $0, $1, $2;",
+        ),
+        (
+            nvvm::MaxReluS16x2Op::get_concrete_op_info(),
+            "max.relu.s16x2 $0, $1, $2;",
+        ),
+    ];
+
+    let operands = [
+        entry.deref(&ctx).get_argument(0),
+        entry.deref(&ctx).get_argument(1),
+    ];
+    for &(op_info, _) in &cases {
+        let op = Operation::new(
+            &mut ctx,
+            op_info,
+            vec![i32_ty.into()],
+            operands.to_vec(),
+            vec![],
+            0,
+        );
+        op.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    let mut lowered = Vec::new();
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let inline_asm_op = inline_asm.get_operation();
+                let operand_count = inline_asm_op.deref(&ctx).operands().count();
+                let result_count = inline_asm_op.deref(&ctx).get_num_results();
+                lowered.push((
+                    inline_asm
+                        .get_attr_inline_asm_template(&ctx)
+                        .map(|s| String::from((*s).clone()))
+                        .expect("integer min/max inline asm must have a template"),
+                    inline_asm
+                        .get_attr_inline_asm_constraints(&ctx)
+                        .map(|s| String::from((*s).clone()))
+                        .expect("integer min/max inline asm must have constraints"),
+                    llvm::asm_kind_opt(&ctx, &inline_asm),
+                    inline_asm
+                        .get_attr_inline_asm_convergent(&ctx)
+                        .map(|b| bool::from((*b).clone())),
+                    operand_count,
+                    result_count,
+                ));
+            }
+        }
+    }
+
+    assert_eq!(
+        lowered.len(),
+        cases.len(),
+        "each integer min/max operation must lower to exactly one inline-asm op"
+    );
+    for &(_, expected_template) in &cases {
+        let matches: Vec<_> = lowered
+            .iter()
+            .filter(|(template, _, _, _, _, _)| template == expected_template)
+            .collect();
+        assert_eq!(
+            matches.len(),
+            1,
+            "expected one exact `{expected_template}` lowering"
+        );
+        let (_, constraints, kind, convergent, operand_count, result_count) = matches[0];
+        assert_eq!(constraints, "=r,r,r", "{expected_template}");
+        assert_eq!(*kind, Some(llvm::AsmKind::Pure), "{expected_template}");
+        assert_eq!(*convergent, Some(false), "{expected_template}");
+        assert_eq!(*operand_count, 2, "{expected_template} input arity");
+        assert_eq!(*result_count, 1, "{expected_template} result arity");
+    }
+
+    Ok(())
+}
+
+#[test]
+fn test_generated_packed_conversions_lower_to_exact_pure_inline_asm() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty.into(), f32_ty.into()]);
+    let low = entry.deref(&ctx).get_argument(0);
+    let high = entry.deref(&ctx).get_argument(1);
+
+    type OpInfo = (
+        fn(pliron::context::Ptr<Operation>) -> pliron::op::OpObj,
+        std::any::TypeId,
+    );
+    let cases: [(OpInfo, &str); 6] = [
+        (
+            nvvm::CvtF32x2Bf16x2Op::get_concrete_op_info(),
+            "cvt.rn.bf16x2.f32 $0, $2, $1;",
+        ),
+        (
+            nvvm::CvtF16x2F32Op::get_concrete_op_info(),
+            "cvt.rn.f16x2.f32 $0, $2, $1;",
+        ),
+        (
+            nvvm::CvtRzF16x2F32Op::get_concrete_op_info(),
+            "cvt.rz.f16x2.f32 $0, $2, $1;",
+        ),
+        (
+            nvvm::CvtRnReluF16x2F32Op::get_concrete_op_info(),
+            "cvt.rn.relu.f16x2.f32 $0, $2, $1;",
+        ),
+        (
+            nvvm::CvtRnReluBf16x2F32Op::get_concrete_op_info(),
+            "cvt.rn.relu.bf16x2.f32 $0, $2, $1;",
+        ),
+        (
+            nvvm::CvtRzBf16x2F32Op::get_concrete_op_info(),
+            "cvt.rz.bf16x2.f32 $0, $2, $1;",
+        ),
+    ];
+    for &(op_info, _) in &cases {
+        let op = Operation::new(
+            &mut ctx,
+            op_info,
+            vec![i32_ty.into()],
+            vec![low, high],
+            vec![],
+            0,
+        );
+        op.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    let mut lowered = Vec::new();
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(func) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let region = func.get_operation().deref(&ctx).get_region(0);
+        for block in region.deref(&ctx).iter(&ctx) {
+            for body_op in block.deref(&ctx).iter(&ctx) {
+                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .expect("packed conversion must have an asm template");
+                if !template.starts_with("cvt.") {
+                    continue;
+                }
+                lowered.push((
+                    template,
+                    asm.get_attr_inline_asm_constraints(&ctx)
+                        .map(|value| String::from((*value).clone())),
+                    asm.get_attr_inline_asm_convergent(&ctx)
+                        .map(|value| bool::from((*value).clone())),
+                    llvm::asm_kind_opt(&ctx, &asm),
+                    asm.get_operation().deref(&ctx).operands().count(),
+                    asm.get_operation().deref(&ctx).get_num_results(),
+                ));
+            }
+        }
+    }
+
+    assert_eq!(
+        lowered.len(),
+        cases.len(),
+        "each packed conversion must lower to one inline-asm op"
+    );
+    for &(_, expected_template) in &cases {
+        let matches: Vec<_> = lowered
+            .iter()
+            .filter(|(template, _, _, _, _, _)| template == expected_template)
+            .collect();
+        assert_eq!(
+            matches.len(),
+            1,
+            "expected one exact `{expected_template}` lowering"
+        );
+        let (_, constraints, convergent, kind, operands, results) = matches[0];
+        assert_eq!(
+            constraints.as_deref(),
+            Some("=r,f,f"),
+            "{expected_template}"
+        );
+        assert_eq!(*convergent, Some(false), "{expected_template}");
+        assert_eq!(*kind, Some(llvm::AsmKind::Pure), "{expected_template}");
+        assert_eq!(*operands, 2, "{expected_template} input arity");
+        assert_eq!(*results, 1, "{expected_template} result arity");
+    }
+
+    Ok(())
+}
+
+const FP8_CONVERSION_INTRINSICS: [&str; 4] = [
+    "llvm_nvvm_ff_to_e4m3x2_rn",
+    "llvm_nvvm_ff_to_e4m3x2_rn_relu",
+    "llvm_nvvm_ff_to_e5m2x2_rn",
+    "llvm_nvvm_ff_to_e5m2x2_rn_relu",
+];
+
+const FP8_CONVERSION_PTX: [&str; 4] = [
+    "cvt.rn.satfinite.e4m3x2.f32 $0, $2, $1;",
+    "cvt.rn.satfinite.relu.e4m3x2.f32 $0, $2, $1;",
+    "cvt.rn.satfinite.e5m2x2.f32 $0, $2, $1;",
+    "cvt.rn.satfinite.relu.e5m2x2.f32 $0, $2, $1;",
+];
+
+fn lower_all_fp8_conversions(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use pliron::builtin::types::FP32Type;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty.into(), f32_ty.into()]);
+    let low = entry.deref(&ctx).get_argument(0);
+    let high = entry.deref(&ctx).get_argument(1);
+
+    nvvm::CvtRnSatfiniteE4m3x2F32Op::build(&mut ctx, low, high).insert_at_back(entry, &ctx);
+    nvvm::CvtRnSatfiniteReluE4m3x2F32Op::build(&mut ctx, low, high).insert_at_back(entry, &ctx);
+    nvvm::CvtRnSatfiniteE5m2x2F32Op::build(&mut ctx, low, high).insert_at_back(entry, &ctx);
+    nvvm::CvtRnSatfiniteReluE5m2x2F32Op::build(&mut ctx, low, high).insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn test_fp8_conversions_llvm_nvptx_use_exact_typed_calls() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::IntegerType;
+    use pliron::r#type::Typed;
+
+    let (ctx, module_ptr) = lower_all_fp8_conversions(mir_lower::IntrinsicBackend::LlvmNvptx)?;
+    let mut calls = Vec::new();
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        assert!(
+            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+            "LLVM-NVPTX FP8 conversions must use typed intrinsics"
+        );
+        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+            continue;
+        };
+        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+            continue;
+        };
+        let callee = callee.to_string();
+        if !FP8_CONVERSION_INTRINSICS.contains(&callee.as_str()) {
+            continue;
+        }
+        let call_op = call.get_operation();
+        assert_eq!(call_op.deref(&ctx).get_num_operands(), 2);
+        assert_eq!(call_op.deref(&ctx).get_num_results(), 1);
+        let block = call_op.deref(&ctx).get_parent_block().unwrap();
+        assert_eq!(
+            call_op.deref(&ctx).get_operand(0),
+            block.deref(&ctx).get_argument(1)
+        );
+        assert_eq!(
+            call_op.deref(&ctx).get_operand(1),
+            block.deref(&ctx).get_argument(0)
+        );
+        let result_ty = call_op.deref(&ctx).get_result(0).get_type(&ctx);
+        assert_eq!(
+            result_ty
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .expect("FP8 conversion result is an integer")
+                .width(),
+            16
+        );
+        calls.push(callee);
+    }
+    calls.sort();
+    let mut expected = FP8_CONVERSION_INTRINSICS.map(str::to_owned);
+    expected.sort();
+    assert_eq!(calls, expected);
+    Ok(())
+}
+
+#[test]
+fn test_fp8_conversions_libnvvm_use_exact_pure_inline_ptx() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::IntegerType;
+    use pliron::r#type::Typed;
+
+    let (ctx, module_ptr) = lower_all_fp8_conversions(mir_lower::IntrinsicBackend::LibNvvm)?;
+    let mut templates = Vec::new();
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+        {
+            assert!(
+                !FP8_CONVERSION_INTRINSICS.contains(&callee.as_ref()),
+                "libNVVM FP8 conversions must not use typed intrinsics"
+            );
+        }
+        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            continue;
+        };
+        let template = inline_asm
+            .get_attr_inline_asm_template(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .unwrap_or_default();
+        if !FP8_CONVERSION_PTX.contains(&template.as_str()) {
+            continue;
+        }
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_constraints(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some("=h,f,f")
+        );
+        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_convergent(&ctx)
+                .map(|value| bool::from((*value).clone())),
+            Some(false)
+        );
+        let asm_op = inline_asm.get_operation();
+        assert_eq!(asm_op.deref(&ctx).get_num_operands(), 2);
+        assert_eq!(asm_op.deref(&ctx).get_num_results(), 1);
+        let result_ty = asm_op.deref(&ctx).get_result(0).get_type(&ctx);
+        assert_eq!(
+            result_ty
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .expect("FP8 conversion result is an integer")
+                .width(),
+            16
+        );
+        templates.push(template);
+    }
+    templates.sort();
+    let mut expected = FP8_CONVERSION_PTX.map(str::to_owned);
+    expected.sort();
+    assert_eq!(templates, expected);
+    Ok(())
+}
+
+const SCALAR_CONVERSION_INTRINSICS: [&str; 10] = [
+    "llvm_nvvm_f2tf32_rna",
+    "llvm_nvvm_f2tf32_rna_satfinite",
+    "llvm_nvvm_f2tf32_rn",
+    "llvm_nvvm_f2tf32_rn_relu",
+    "llvm_nvvm_f2tf32_rn_satfinite",
+    "llvm_nvvm_f2tf32_rn_relu_satfinite",
+    "llvm_nvvm_f2tf32_rz",
+    "llvm_nvvm_f2tf32_rz_relu",
+    "llvm_nvvm_f2tf32_rz_satfinite",
+    "llvm_nvvm_f2tf32_rz_relu_satfinite",
+];
+
+const SCALAR_CONVERSION_PTX: [&str; 10] = [
+    "cvt.rna.tf32.f32 $0, $1;",
+    "cvt.rna.satfinite.tf32.f32 $0, $1;",
+    "cvt.rn.tf32.f32 $0, $1;",
+    "cvt.rn.relu.tf32.f32 $0, $1;",
+    "cvt.rn.satfinite.tf32.f32 $0, $1;",
+    "cvt.rn.relu.satfinite.tf32.f32 $0, $1;",
+    "cvt.rz.tf32.f32 $0, $1;",
+    "cvt.rz.relu.tf32.f32 $0, $1;",
+    "cvt.rz.satfinite.tf32.f32 $0, $1;",
+    "cvt.rz.relu.satfinite.tf32.f32 $0, $1;",
+];
+
+fn lower_all_scalar_conversions(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use pliron::builtin::types::FP32Type;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty.into()]);
+    let value = entry.deref(&ctx).get_argument(0);
+
+    let variants = [
+        (
+            nvvm::ScalarConversionRoundingAttr::NearestAway,
+            nvvm::ScalarConversionSaturationAttr::None,
+        ),
+        (
+            nvvm::ScalarConversionRoundingAttr::NearestAway,
+            nvvm::ScalarConversionSaturationAttr::Satfinite,
+        ),
+        (
+            nvvm::ScalarConversionRoundingAttr::NearestEven,
+            nvvm::ScalarConversionSaturationAttr::None,
+        ),
+        (
+            nvvm::ScalarConversionRoundingAttr::NearestEven,
+            nvvm::ScalarConversionSaturationAttr::Relu,
+        ),
+        (
+            nvvm::ScalarConversionRoundingAttr::NearestEven,
+            nvvm::ScalarConversionSaturationAttr::Satfinite,
+        ),
+        (
+            nvvm::ScalarConversionRoundingAttr::NearestEven,
+            nvvm::ScalarConversionSaturationAttr::ReluSatfinite,
+        ),
+        (
+            nvvm::ScalarConversionRoundingAttr::TowardZero,
+            nvvm::ScalarConversionSaturationAttr::None,
+        ),
+        (
+            nvvm::ScalarConversionRoundingAttr::TowardZero,
+            nvvm::ScalarConversionSaturationAttr::Relu,
+        ),
+        (
+            nvvm::ScalarConversionRoundingAttr::TowardZero,
+            nvvm::ScalarConversionSaturationAttr::Satfinite,
+        ),
+        (
+            nvvm::ScalarConversionRoundingAttr::TowardZero,
+            nvvm::ScalarConversionSaturationAttr::ReluSatfinite,
+        ),
+    ];
+    for (rounding, saturation) in variants {
+        nvvm::ScalarConversionOp::build(&mut ctx, value, rounding, saturation)
+            .insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn test_scalar_conversions_llvm_nvptx_use_exact_typed_calls() -> Result<(), anyhow::Error> {
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::type_interfaces::FunctionTypeInterface;
+    use pliron::builtin::types::{FP32Type, IntegerType};
+
+    let (ctx, module_ptr) = lower_all_scalar_conversions(mir_lower::IntrinsicBackend::LlvmNvptx)?;
+    let mut calls = Vec::new();
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        assert!(
+            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+            "LLVM-NVPTX scalar conversions must use typed intrinsics"
+        );
+        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+            continue;
+        };
+        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+            continue;
+        };
+        let callee = callee.to_string();
+        if !SCALAR_CONVERSION_INTRINSICS.contains(&callee.as_str()) {
+            continue;
+        }
+
+        let call_op = call.get_operation();
+        assert_eq!(call_op.deref(&ctx).get_num_operands(), 1, "{callee}");
+        assert_eq!(call_op.deref(&ctx).get_num_results(), 1, "{callee}");
+        let block = call_op.deref(&ctx).get_parent_block().unwrap();
+        assert_eq!(
+            call_op.deref(&ctx).get_operand(0),
+            block.deref(&ctx).get_argument(0),
+            "{callee} source operand"
+        );
+
+        let function_ty = call.callee_type(&ctx);
+        let function_ty = function_ty.deref(&ctx);
+        let function_ty = function_ty
+            .downcast_ref::<llvm_types::FuncType>()
+            .expect("scalar conversion callee has an LLVM function type");
+        assert_eq!(function_ty.arg_types().len(), 1, "{callee}");
+        assert!(
+            function_ty.arg_types()[0]
+                .deref(&ctx)
+                .downcast_ref::<FP32Type>()
+                .is_some(),
+            "{callee} source type"
+        );
+        assert_eq!(
+            function_ty
+                .result_type()
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .expect("scalar conversion result is an integer")
+                .width(),
+            32,
+            "{callee} result type"
+        );
+        calls.push(callee);
+    }
+    calls.sort();
+    let mut expected = SCALAR_CONVERSION_INTRINSICS.map(str::to_owned);
+    expected.sort();
+    assert_eq!(calls, expected);
+
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    let mut declarations: Vec<_> = module_block
+        .deref(&ctx)
+        .iter(&ctx)
+        .filter_map(|op| Operation::get_op::<llvm::FuncOp>(op, &ctx))
+        .map(|func| func.get_symbol_name(&ctx).to_string())
+        .filter(|name| SCALAR_CONVERSION_INTRINSICS.contains(&name.as_str()))
+        .collect();
+    declarations.sort();
+    assert_eq!(declarations, expected);
+    Ok(())
+}
+
+#[test]
+fn test_scalar_conversions_libnvvm_use_exact_pure_inline_ptx() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::IntegerType;
+    use pliron::r#type::Typed;
+
+    let (ctx, module_ptr) = lower_all_scalar_conversions(mir_lower::IntrinsicBackend::LibNvvm)?;
+    let mut templates = Vec::new();
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+        {
+            assert!(
+                !SCALAR_CONVERSION_INTRINSICS.contains(&callee.as_ref()),
+                "libNVVM scalar conversions must not use typed intrinsics"
+            );
+        }
+        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            continue;
+        };
+        let template = inline_asm
+            .get_attr_inline_asm_template(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .unwrap_or_default();
+        assert!(
+            SCALAR_CONVERSION_PTX.contains(&template.as_str()),
+            "unexpected scalar conversion template `{template}`"
+        );
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_constraints(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some("=r,f"),
+            "{template}"
+        );
+        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_convergent(&ctx)
+                .map(|value| bool::from((*value).clone())),
+            Some(false),
+            "{template}"
+        );
+
+        let asm_op = inline_asm.get_operation();
+        assert_eq!(asm_op.deref(&ctx).get_num_operands(), 1, "{template}");
+        assert_eq!(asm_op.deref(&ctx).get_num_results(), 1, "{template}");
+        let block = asm_op.deref(&ctx).get_parent_block().unwrap();
+        assert_eq!(
+            asm_op.deref(&ctx).get_operand(0),
+            block.deref(&ctx).get_argument(0),
+            "{template} source operand"
+        );
+        assert_eq!(
+            asm_op
+                .deref(&ctx)
+                .get_result(0)
+                .get_type(&ctx)
+                .deref(&ctx)
+                .downcast_ref::<IntegerType>()
+                .expect("scalar conversion result is an integer")
+                .width(),
+            32,
+            "{template} result type"
+        );
+        templates.push(template);
+    }
+    templates.sort();
+    let mut expected = SCALAR_CONVERSION_PTX.map(str::to_owned);
+    expected.sort();
+    assert_eq!(templates, expected);
+    Ok(())
+}
+
+#[test]
+fn test_scalar_conversion_invalid_variant_fails_closed() {
+    use pliron::builtin::types::FP32Type;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty.into()]);
+    let value = entry.deref(&ctx).get_argument(0);
+    nvvm::ScalarConversionOp::build(
+        &mut ctx,
+        value,
+        nvvm::ScalarConversionRoundingAttr::NearestAway,
+        nvvm::ScalarConversionSaturationAttr::Relu,
+    )
+    .insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    let result = mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: mir_lower::IntrinsicBackend::LlvmNvptx,
+            ..Default::default()
+        },
+    );
+    let error = result.expect_err("unadmitted scalar conversion must not lower");
+    assert!(
+        error.to_string().contains("scalar_conversion"),
+        "unexpected error: {error}"
+    );
+}
+
+fn lower_representative_scalar_arithmetic(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use pliron::builtin::types::FP32Type;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![f32_ty.into(), f32_ty.into(), f32_ty.into()]);
+    let args: Vec<_> = (0..3)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect();
+
+    for (operation, saturation, operands) in [
+        (
+            nvvm::ScalarArithmeticOperationAttr::Add,
+            nvvm::ScalarArithmeticSaturationAttr::None,
+            vec![args[0], args[1]],
+        ),
+        (
+            nvvm::ScalarArithmeticOperationAttr::Add,
+            nvvm::ScalarArithmeticSaturationAttr::Sat,
+            vec![args[0], args[1]],
+        ),
+        (
+            nvvm::ScalarArithmeticOperationAttr::Fma,
+            nvvm::ScalarArithmeticSaturationAttr::None,
+            args.clone(),
+        ),
+        (
+            nvvm::ScalarArithmeticOperationAttr::Fma,
+            nvvm::ScalarArithmeticSaturationAttr::Sat,
+            args,
+        ),
+    ] {
+        nvvm::ScalarArithmeticOp::build(
+            &mut ctx,
+            operands,
+            nvvm::ScalarArithmeticFormatAttr::F32,
+            operation,
+            nvvm::ScalarArithmeticRoundingAttr::Rn,
+            nvvm::ScalarArithmeticSubnormalAttr::Preserve,
+            saturation,
+        )
+        .insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+fn is_representative_scalar_arithmetic_intrinsic(name: &str) -> bool {
+    name.starts_with("llvm_nvvm_add_rn") || name.starts_with("llvm_nvvm_fma_rn")
+}
+
+#[test]
+fn test_scalar_arithmetic_llvm_uses_inline_ptx_only_for_saturation() -> Result<(), anyhow::Error> {
+    let (ctx, module_ptr) =
+        lower_representative_scalar_arithmetic(mir_lower::IntrinsicBackend::LlvmNvptx)?;
+    let mut calls = Vec::new();
+    let mut inline_ptx = Vec::new();
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+            && is_representative_scalar_arithmetic_intrinsic(callee.as_ref())
+        {
+            calls.push(callee.to_string());
+        }
+        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            continue;
+        };
+        let template = inline_asm
+            .get_attr_inline_asm_template(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .unwrap_or_default();
+        let constraints = inline_asm
+            .get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .unwrap_or_default();
+        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
+        assert_eq!(
+            inline_asm
+                .get_attr_inline_asm_convergent(&ctx)
+                .map(|value| bool::from((*value).clone())),
+            Some(false)
+        );
+        inline_ptx.push((template, constraints));
+    }
+
+    calls.sort();
+    assert_eq!(calls, ["llvm_nvvm_add_rn_f", "llvm_nvvm_fma_rn_f"]);
+    inline_ptx.sort();
+    assert_eq!(
+        inline_ptx,
+        [
+            ("add.rn.sat.f32 $0, $1, $2;".into(), "=f,f,f".into()),
+            ("fma.rn.sat.f32 $0, $1, $2, $3;".into(), "=f,f,f,f".into(),),
+        ]
+    );
+
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    let mut declarations: Vec<_> = module_block
+        .deref(&ctx)
+        .iter(&ctx)
+        .filter_map(|op| Operation::get_op::<llvm::FuncOp>(op, &ctx))
+        .map(|func| func.get_symbol_name(&ctx).to_string())
+        .filter(|name| is_representative_scalar_arithmetic_intrinsic(name))
+        .collect();
+    declarations.sort();
+    assert_eq!(declarations, calls);
+    Ok(())
+}
+
+#[test]
+fn test_scalar_arithmetic_libnvvm_uses_exact_inline_ptx() -> Result<(), anyhow::Error> {
+    let (ctx, module_ptr) =
+        lower_representative_scalar_arithmetic(mir_lower::IntrinsicBackend::LibNvvm)?;
+    let mut calls = Vec::new();
+    let mut inline_ptx = Vec::new();
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+            && is_representative_scalar_arithmetic_intrinsic(callee.as_ref())
+        {
+            calls.push(callee.to_string());
+        }
+        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            continue;
+        };
+        let template = inline_asm
+            .get_attr_inline_asm_template(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .unwrap_or_default();
+        let constraints = inline_asm
+            .get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .unwrap_or_default();
+        assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Pure);
+        inline_ptx.push((template, constraints));
+    }
+
+    assert!(calls.is_empty());
+    inline_ptx.sort();
+    assert_eq!(
+        inline_ptx,
+        [
+            ("add.rn.f32 $0, $1, $2;".into(), "=f,f,f".into()),
+            ("add.rn.sat.f32 $0, $1, $2;".into(), "=f,f,f".into()),
+            ("fma.rn.f32 $0, $1, $2, $3;".into(), "=f,f,f,f".into(),),
+            ("fma.rn.sat.f32 $0, $1, $2, $3;".into(), "=f,f,f,f".into(),),
+        ]
+    );
+    Ok(())
+}
diff --git a/crates/mir-lower/tests/lowering_test/matrix_memory.rs b/crates/mir-lower/tests/lowering_test/matrix_memory.rs
new file mode 100644
index 0000000000..bd05a6da9b
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/matrix_memory.rs
@@ -0,0 +1,1214 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_nvvm::ops as nvvm;
+use llvm_export::ops as llvm;
+use pliron::builtin::op_interfaces::{CallOpCallable, CallOpInterface, SymbolOpInterface};
+use pliron::builtin::ops::ModuleOp;
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+use crate::common::{append_return, build_test_kernel, lowered_kernel_body, make_test_ctx};
+
+const STMATRIX_TYPED_INTRINSICS: [&str; 4] = [
+    "llvm_nvvm_stmatrix_sync_aligned_m8n8_x2_b16_p3",
+    "llvm_nvvm_stmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
+    "llvm_nvvm_stmatrix_sync_aligned_m8n8_x4_b16_p3",
+    "llvm_nvvm_stmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
+];
+
+const STMATRIX_PTX: [(&str, &str); 4] = [
+    (
+        "{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x2.shared.b16 [%ptr32], {$1, $2}; }",
+        "l,r,r,~{memory}",
+    ),
+    (
+        "{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x2.trans.shared.b16 [%ptr32], {$1, $2}; }",
+        "l,r,r,~{memory}",
+    ),
+    (
+        "{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x4.shared.b16 [%ptr32], {$1, $2, $3, $4}; }",
+        "l,r,r,r,r,~{memory}",
+    ),
+    (
+        "{ .reg .u64 %ptr64; .reg .u32 %ptr32; cvta.to.shared.u64 %ptr64, $0; cvt.u32.u64 %ptr32, %ptr64; stmatrix.sync.aligned.m8n8.x4.trans.shared.b16 [%ptr32], {$1, $2, $3, $4}; }",
+        "l,r,r,r,r,~{memory}",
+    ),
+];
+
+fn lower_all_stmatrix_forms(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i8_ty = IntegerType::get(&ctx, 8, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, i8_ty.into(), true);
+    let (module_ptr, entry) = build_test_kernel(
+        &mut ctx,
+        vec![
+            ptr_ty.into(),
+            i32_ty.into(),
+            i32_ty.into(),
+            i32_ty.into(),
+            i32_ty.into(),
+        ],
+    );
+    let args: Vec<_> = (0..5)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect();
+
+    for (op_info, operands) in [
+        (
+            nvvm::StmatrixM8n8X2Op::get_concrete_op_info(),
+            args[..3].to_vec(),
+        ),
+        (
+            nvvm::StmatrixM8n8X2TransOp::get_concrete_op_info(),
+            args[..3].to_vec(),
+        ),
+        (nvvm::StmatrixM8n8X4Op::get_concrete_op_info(), args.clone()),
+        (nvvm::StmatrixM8n8X4TransOp::get_concrete_op_info(), args),
+    ] {
+        Operation::new(&mut ctx, op_info, vec![], operands, vec![], 0).insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn test_stmatrix_llvm_nvptx_uses_exact_typed_p3_intrinsics() -> Result<(), anyhow::Error> {
+    use llvm_export::types as llvm_types;
+    use pliron::r#type::Typed;
+
+    let (ctx, module_ptr) = lower_all_stmatrix_forms(mir_lower::IntrinsicBackend::LlvmNvptx)?;
+    let mut callees = Vec::new();
+
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        assert!(
+            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+            "LLVM-NVPTX stmatrix lowering must not emit inline PTX"
+        );
+        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+            continue;
+        };
+        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+            continue;
+        };
+        let callee = callee.to_string();
+        if !STMATRIX_TYPED_INTRINSICS.contains(&callee.as_str()) {
+            continue;
+        }
+
+        let call_op = call.get_operation().deref(&ctx);
+        assert!(matches!(call_op.get_num_operands(), 3 | 5));
+        assert_eq!(call_op.get_num_results(), 1);
+        let pointer_ty = call_op.get_operand(0).get_type(&ctx);
+        let pointer_ty = pointer_ty.deref(&ctx);
+        let pointer_ty = pointer_ty
+            .downcast_ref::<llvm_types::PointerType>()
+            .expect("stmatrix first argument is a pointer");
+        assert_eq!(pointer_ty.address_space(), 3);
+        callees.push(callee);
+    }
+
+    callees.sort();
+    let mut expected = STMATRIX_TYPED_INTRINSICS.map(str::to_owned);
+    expected.sort();
+    assert_eq!(callees, expected);
+
+    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+        .expect("typed stmatrix module exports to LLVM IR");
+    for intrinsic in STMATRIX_TYPED_INTRINSICS {
+        let dotted = intrinsic.replace('_', ".");
+        assert!(
+            ir.contains(&format!("@{dotted}(ptr addrspace(3)")),
+            "missing exact typed stmatrix declaration:\n{ir}"
+        );
+    }
+    assert!(!ir.contains("asm sideeffect"), "{ir}");
+    Ok(())
+}
+
+#[test]
+fn test_stmatrix_libnvvm_uses_exact_convergent_memory_asm() -> Result<(), anyhow::Error> {
+    let (ctx, module_ptr) = lower_all_stmatrix_forms(mir_lower::IntrinsicBackend::LibNvvm)?;
+    let mut lowered = Vec::new();
+
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+        {
+            assert!(
+                !STMATRIX_TYPED_INTRINSICS.contains(&callee.as_ref()),
+                "libNVVM stmatrix lowering must not emit typed intrinsic calls"
+            );
+        }
+        let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            continue;
+        };
+        lowered.push((
+            inline_asm
+                .get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .unwrap_or_default(),
+            inline_asm
+                .get_attr_inline_asm_constraints(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .unwrap_or_default(),
+            llvm::asm_kind(&ctx, &inline_asm),
+            op.deref(&ctx).get_num_operands(),
+            op.deref(&ctx).get_num_results(),
+        ));
+    }
+
+    assert_eq!(lowered.len(), STMATRIX_PTX.len());
+    for (template, constraints) in STMATRIX_PTX {
+        let matches: Vec<_> = lowered
+            .iter()
+            .filter(|(actual, _, _, _, _)| actual == template)
+            .collect();
+        assert_eq!(matches.len(), 1, "missing exact PTX {template}");
+        let (_, actual_constraints, kind, operands, results) = matches[0];
+        assert_eq!(actual_constraints, constraints);
+        assert_eq!(*kind, llvm::AsmKind::Convergent);
+        assert!(matches!(*operands, 3 | 5));
+        assert_eq!(*results, 1);
+    }
+
+    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+        .expect("inline stmatrix module exports to LLVM IR");
+    assert_eq!(ir.matches("asm sideeffect").count(), 4, "{ir}");
+    assert_eq!(ir.matches("~{memory}").count(), 4, "{ir}");
+    assert!(ir.contains("attributes #0 = { convergent }"), "{ir}");
+    assert!(!ir.contains("@llvm.nvvm.stmatrix"), "{ir}");
+    Ok(())
+}
+
+// =============================================================================
+// Warp-level matrix (`movmatrix`) lowering test
+// =============================================================================
+
+#[test]
+fn test_movmatrix_trans_b16_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
+
+    let a_val = entry.deref(&ctx).get_argument(0);
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::MovmatrixTransB16Op::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![a_val],
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut found = 0;
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for module_op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
+            continue;
+        };
+        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let body = function.get_operation().deref(&ctx).get_region(0);
+        for block in body.deref(&ctx).iter(&ctx) {
+            for body_op in block.deref(&ctx).iter(&ctx) {
+                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                found += 1;
+                let template = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                let constraints = asm
+                    .get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                assert_eq!(
+                    template.as_deref(),
+                    Some("movmatrix.sync.aligned.m8n8.trans.b16 $0, $1;")
+                );
+                assert_eq!(constraints.as_deref(), Some("=r,r"));
+                assert_eq!(
+                    llvm::asm_kind_opt(&ctx, &asm),
+                    Some(llvm::AsmKind::Convergent)
+                );
+                assert!(
+                    asm.get_attr_inline_asm_convergent(&ctx)
+                        .is_some_and(|value| bool::from((*value).clone()))
+                );
+                assert!(
+                    !constraints.as_deref().unwrap().contains("memory"),
+                    "register-only movmatrix must not claim a memory clobber"
+                );
+            }
+        }
+    }
+
+    assert_eq!(found, 1, "expected one movmatrix inline-asm operation");
+    Ok(())
+}
+
+// =============================================================================
+// ldmatrix lowering tests
+// =============================================================================
+
+const LDMATRIX_TYPED_INTRINSICS: [&str; 6] = [
+    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_b16_p3",
+    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x1_trans_b16_p3",
+    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_b16_p3",
+    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16_p3",
+    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_b16_p3",
+    "llvm_nvvm_ldmatrix_sync_aligned_m8n8_x4_trans_b16_p3",
+];
+
+const LDMATRIX_PTX_TEMPLATES: [&str; 6] = [
+    "ldmatrix.sync.aligned.m8n8.x1.shared.b16 {$0}, [$1];",
+    "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16 {$0}, [$1];",
+    "ldmatrix.sync.aligned.m8n8.x2.shared.b16 {$0, $1}, [$2];",
+    "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16 {$0, $1}, [$2];",
+    "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {$0, $1, $2, $3}, [$4];",
+    "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {$0, $1, $2, $3}, [$4];",
+];
+
+const LDMATRIX_PTX_CONSTRAINTS: [&str; 6] = [
+    "=r,r,~{memory}",
+    "=r,r,~{memory}",
+    "=r,=r,r,~{memory}",
+    "=r,=r,r,~{memory}",
+    "=r,=r,=r,=r,r,~{memory}",
+    "=r,=r,=r,=r,r,~{memory}",
+];
+
+const BLACKWELL_LDMATRIX_CASES: [(&str, &str, &str, usize); 12] = [
+    (
+        "llvm_nvvm_ldmatrix_sync_aligned_m16n16_x1_trans_b8_p3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8.p3",
+        "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {$0, $1}, [$2];",
+        2,
+    ),
+    (
+        "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db4x16_up64_dp3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8x16.b4x16_p64.p3",
+        "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b4x16_p64 {$0, $1}, [$2];",
+        2,
+    ),
+    (
+        "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx1_dtrans_db8x16_db6x16_up32_dp3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8x16.b6x16_p32.p3",
+        "ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8x16.b6x16_p32 {$0, $1}, [$2];",
+        2,
+    ),
+    (
+        "llvm_nvvm_ldmatrix_sync_aligned_m16n16_x2_trans_b8_p3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x2.trans.b8.p3",
+        "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8 {$0, $1, $2, $3}, [$4];",
+        4,
+    ),
+    (
+        "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx2_dtrans_db8x16_db4x16_up64_dp3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x2.trans.b8x16.b4x16_p64.p3",
+        "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b4x16_p64 {$0, $1, $2, $3}, [$4];",
+        4,
+    ),
+    (
+        "llvm__nvvm_dldmatrix_dsync_daligned_dm16n16_dx2_dtrans_db8x16_db6x16_up32_dp3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m16n16.x2.trans.b8x16.b6x16_p32.p3",
+        "ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8x16.b6x16_p32 {$0, $1, $2, $3}, [$4];",
+        4,
+    ),
+    (
+        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx1_db8x16_db4x16_up64_dp3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x1.b8x16.b4x16_p64.p3",
+        "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b4x16_p64 {$0}, [$1];",
+        1,
+    ),
+    (
+        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx1_db8x16_db6x16_up32_dp3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x1.b8x16.b6x16_p32.p3",
+        "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b6x16_p32 {$0}, [$1];",
+        1,
+    ),
+    (
+        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx2_db8x16_db4x16_up64_dp3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x2.b8x16.b4x16_p64.p3",
+        "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b4x16_p64 {$0, $1}, [$2];",
+        2,
+    ),
+    (
+        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx2_db8x16_db6x16_up32_dp3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x2.b8x16.b6x16_p32.p3",
+        "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b6x16_p32 {$0, $1}, [$2];",
+        2,
+    ),
+    (
+        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx4_db8x16_db4x16_up64_dp3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x4.b8x16.b4x16_p64.p3",
+        "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b4x16_p64 {$0, $1, $2, $3}, [$4];",
+        4,
+    ),
+    (
+        "llvm__nvvm_dldmatrix_dsync_daligned_dm8n16_dx4_db8x16_db6x16_up32_dp3",
+        "llvm.nvvm.ldmatrix.sync.aligned.m8n16.x4.b8x16.b6x16_p32.p3",
+        "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b6x16_p32 {$0, $1, $2, $3}, [$4];",
+        4,
+    ),
+];
+
+fn ldmatrix_constraints(register_count: usize) -> &'static str {
+    match register_count {
+        1 => "=r,r,~{memory}",
+        2 => "=r,=r,r,~{memory}",
+        4 => "=r,=r,=r,=r,r,~{memory}",
+        _ => unreachable!("closed ldmatrix register count"),
+    }
+}
+
+fn lower_all_ldmatrix_forms(
+    address_space: u32,
+    backend: mir_lower::IntrinsicBackend,
+    compatibility: bool,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let ptr_ty = MirPtrType::get(&mut ctx, u32_ty.into(), true, address_space);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into()]);
+    let pointer = entry.deref(&ctx).get_argument(0);
+    if compatibility {
+        let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+        for (op_info, result_count) in [
+            (nvvm::LdmatrixX1Op::get_concrete_op_info(), 1),
+            (nvvm::LdmatrixX1TransOp::get_concrete_op_info(), 1),
+            (nvvm::LdmatrixX2Op::get_concrete_op_info(), 2),
+            (nvvm::LdmatrixX2TransOp::get_concrete_op_info(), 2),
+            (nvvm::LdmatrixX4Op::get_concrete_op_info(), 4),
+            (nvvm::LdmatrixX4TransOp::get_concrete_op_info(), 4),
+        ] {
+            Operation::new(
+                &mut ctx,
+                op_info,
+                vec![u32_ty.into(); result_count],
+                vec![pointer],
+                vec![],
+                0,
+            )
+            .insert_at_back(entry, &ctx);
+        }
+    } else {
+        for (multiplicity, layout) in [
+            (
+                nvvm::LdmatrixMultiplicityAttr::X1,
+                nvvm::LdmatrixLayoutAttr::Normal,
+            ),
+            (
+                nvvm::LdmatrixMultiplicityAttr::X1,
+                nvvm::LdmatrixLayoutAttr::Transposed,
+            ),
+            (
+                nvvm::LdmatrixMultiplicityAttr::X2,
+                nvvm::LdmatrixLayoutAttr::Normal,
+            ),
+            (
+                nvvm::LdmatrixMultiplicityAttr::X2,
+                nvvm::LdmatrixLayoutAttr::Transposed,
+            ),
+            (
+                nvvm::LdmatrixMultiplicityAttr::X4,
+                nvvm::LdmatrixLayoutAttr::Normal,
+            ),
+            (
+                nvvm::LdmatrixMultiplicityAttr::X4,
+                nvvm::LdmatrixLayoutAttr::Transposed,
+            ),
+        ] {
+            nvvm::LdmatrixOp::build(
+                &mut ctx,
+                pointer,
+                nvvm::LdmatrixShapeAttr::M8n8,
+                multiplicity,
+                layout,
+                nvvm::LdmatrixElementAttr::B16,
+                nvvm::LdmatrixStateSpaceAttr::Shared,
+            )
+            .insert_at_back(entry, &ctx);
+        }
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    Ok((ctx, module_ptr))
+}
+
+fn lower_all_blackwell_ldmatrix_forms(
+    address_space: u32,
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+    let ptr_ty = MirPtrType::get(&mut ctx, u8_ty.into(), true, address_space);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into()]);
+    let pointer = entry.deref(&ctx).get_argument(0);
+
+    for (shape, multiplicity, layout, element) in [
+        (
+            nvvm::LdmatrixShapeAttr::M16n16,
+            nvvm::LdmatrixMultiplicityAttr::X1,
+            nvvm::LdmatrixLayoutAttr::Transposed,
+            nvvm::LdmatrixElementAttr::B8,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M16n16,
+            nvvm::LdmatrixMultiplicityAttr::X1,
+            nvvm::LdmatrixLayoutAttr::Transposed,
+            nvvm::LdmatrixElementAttr::B8x16B4x16P64,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M16n16,
+            nvvm::LdmatrixMultiplicityAttr::X1,
+            nvvm::LdmatrixLayoutAttr::Transposed,
+            nvvm::LdmatrixElementAttr::B8x16B6x16P32,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M16n16,
+            nvvm::LdmatrixMultiplicityAttr::X2,
+            nvvm::LdmatrixLayoutAttr::Transposed,
+            nvvm::LdmatrixElementAttr::B8,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M16n16,
+            nvvm::LdmatrixMultiplicityAttr::X2,
+            nvvm::LdmatrixLayoutAttr::Transposed,
+            nvvm::LdmatrixElementAttr::B8x16B4x16P64,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M16n16,
+            nvvm::LdmatrixMultiplicityAttr::X2,
+            nvvm::LdmatrixLayoutAttr::Transposed,
+            nvvm::LdmatrixElementAttr::B8x16B6x16P32,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M8n16,
+            nvvm::LdmatrixMultiplicityAttr::X1,
+            nvvm::LdmatrixLayoutAttr::Normal,
+            nvvm::LdmatrixElementAttr::B8x16B4x16P64,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M8n16,
+            nvvm::LdmatrixMultiplicityAttr::X1,
+            nvvm::LdmatrixLayoutAttr::Normal,
+            nvvm::LdmatrixElementAttr::B8x16B6x16P32,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M8n16,
+            nvvm::LdmatrixMultiplicityAttr::X2,
+            nvvm::LdmatrixLayoutAttr::Normal,
+            nvvm::LdmatrixElementAttr::B8x16B4x16P64,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M8n16,
+            nvvm::LdmatrixMultiplicityAttr::X2,
+            nvvm::LdmatrixLayoutAttr::Normal,
+            nvvm::LdmatrixElementAttr::B8x16B6x16P32,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M8n16,
+            nvvm::LdmatrixMultiplicityAttr::X4,
+            nvvm::LdmatrixLayoutAttr::Normal,
+            nvvm::LdmatrixElementAttr::B8x16B4x16P64,
+        ),
+        (
+            nvvm::LdmatrixShapeAttr::M8n16,
+            nvvm::LdmatrixMultiplicityAttr::X4,
+            nvvm::LdmatrixLayoutAttr::Normal,
+            nvvm::LdmatrixElementAttr::B8x16B6x16P32,
+        ),
+    ] {
+        nvvm::LdmatrixOp::build(
+            &mut ctx,
+            pointer,
+            shape,
+            multiplicity,
+            layout,
+            element,
+            nvvm::LdmatrixStateSpaceAttr::Shared,
+        )
+        .insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    Ok((ctx, module_ptr))
+}
+
+fn assert_ldmatrix_producer_result_shape(
+    ctx: &Context,
+    op: pliron::context::Ptr<Operation>,
+    register_count: usize,
+) {
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::types::IntegerType;
+    use pliron::r#type::Typed;
+
+    let ty = op.deref(ctx).get_result(0).get_type(ctx);
+    let ty = ty.deref(ctx);
+    if register_count == 1 {
+        assert_eq!(
+            ty.downcast_ref::<IntegerType>()
+                .expect("single-register ldmatrix returns i32")
+                .width(),
+            32
+        );
+    } else {
+        let ty = ty
+            .downcast_ref::<llvm_types::StructType>()
+            .expect("multi-register ldmatrix returns an LLVM struct");
+        assert_eq!(ty.num_fields(), register_count);
+        for index in 0..register_count {
+            assert_eq!(
+                ty.field_type(index)
+                    .deref(ctx)
+                    .downcast_ref::<IntegerType>()
+                    .expect("ldmatrix fragment field is i32")
+                    .width(),
+                32
+            );
+        }
+    }
+}
+
+#[test]
+fn test_ldmatrix_llvm_nvptx_uses_exact_typed_p3_intrinsics() -> Result<(), anyhow::Error> {
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::type_interfaces::FunctionTypeInterface;
+    use pliron::builtin::types::IntegerType;
+    use pliron::r#type::Typed;
+
+    for address_space in [0, 3] {
+        let (ctx, module_ptr) =
+            lower_all_ldmatrix_forms(address_space, mir_lower::IntrinsicBackend::LlvmNvptx, false)?;
+        let body = lowered_kernel_body(&ctx, module_ptr);
+        let mut callees = Vec::new();
+        let mut cast_count = 0;
+        let mut extract_count = 0;
+
+        for op in body {
+            if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+                && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+            {
+                let callee = callee.to_string();
+                let register_count = if callee.contains("_x1_") {
+                    1
+                } else if callee.contains("_x2_") {
+                    2
+                } else {
+                    4
+                };
+                let function_ty = call.callee_type(&ctx);
+                let function_ty = function_ty.deref(&ctx);
+                let function_ty = function_ty
+                    .downcast_ref::<llvm_types::FuncType>()
+                    .expect("ldmatrix callee has an LLVM function type");
+                assert_eq!(function_ty.arg_types().len(), 1);
+                let argument_ty = function_ty.arg_types()[0].deref(&ctx);
+                let argument_ty = argument_ty
+                    .downcast_ref::<llvm_types::PointerType>()
+                    .expect("ldmatrix argument is a pointer");
+                assert_eq!(argument_ty.address_space(), 3);
+
+                let result_ty = function_ty.result_type();
+                let result_ty = result_ty.deref(&ctx);
+                if register_count == 1 {
+                    let result_ty = result_ty
+                        .downcast_ref::<IntegerType>()
+                        .expect("x1 returns i32");
+                    assert_eq!(result_ty.width(), 32);
+                } else {
+                    let result_ty = result_ty
+                        .downcast_ref::<llvm_types::StructType>()
+                        .expect("x2/x4 return an LLVM struct");
+                    assert_eq!(result_ty.num_fields(), register_count);
+                    for index in 0..result_ty.num_fields() {
+                        let field = result_ty.field_type(index);
+                        let field = field.deref(&ctx);
+                        let field = field
+                            .downcast_ref::<IntegerType>()
+                            .expect("fragment register is i32");
+                        assert_eq!(field.width(), 32);
+                    }
+                }
+
+                callees.push(callee);
+                assert_eq!(op.deref(&ctx).get_num_operands(), 1);
+                assert_eq!(op.deref(&ctx).get_num_results(), 1);
+            }
+            if Operation::get_op::<llvm::AddrSpaceCastOp>(op, &ctx).is_some() {
+                cast_count += 1;
+                let cast = op.deref(&ctx);
+                let source_ty = cast.get_operand(0).get_type(&ctx);
+                let source_ty = source_ty.deref(&ctx);
+                let source_ty = source_ty
+                    .downcast_ref::<llvm_types::PointerType>()
+                    .expect("addrspacecast source is a pointer");
+                let result_ty = cast.get_result(0).get_type(&ctx);
+                let result_ty = result_ty.deref(&ctx);
+                let result_ty = result_ty
+                    .downcast_ref::<llvm_types::PointerType>()
+                    .expect("addrspacecast result is a pointer");
+                assert_eq!(
+                    (source_ty.address_space(), result_ty.address_space()),
+                    (0, 3)
+                );
+            }
+            extract_count +=
+                usize::from(Operation::get_op::<llvm::ExtractValueOp>(op, &ctx).is_some());
+            assert!(
+                Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+                "LLVM-NVPTX ldmatrix lowering must not emit inline PTX"
+            );
+            assert!(
+                Operation::get_op::<llvm::PtrToIntOp>(op, &ctx).is_none(),
+                "the typed intrinsic consumes the shared pointer directly"
+            );
+        }
+
+        callees.sort();
+        let mut expected = LDMATRIX_TYPED_INTRINSICS.map(str::to_owned);
+        expected.sort();
+        assert_eq!(callees, expected);
+        assert_eq!(cast_count, if address_space == 0 { 6 } else { 0 });
+        assert_eq!(
+            extract_count, 12,
+            "x2/x4 structs must preserve result order"
+        );
+
+        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+            .expect("typed ldmatrix module exports to LLVM IR");
+        for intrinsic in LDMATRIX_TYPED_INTRINSICS {
+            let dotted = intrinsic.replace('_', ".");
+            assert!(
+                ir.contains(&format!("@{dotted}(ptr addrspace(3)")),
+                "underscore symbol must export as exact dotted p3 intrinsic:\n{ir}"
+            );
+        }
+        assert!(!ir.contains("@llvm_nvvm_ldmatrix"));
+    }
+    Ok(())
+}
+
+#[test]
+fn test_ldmatrix_libnvvm_uses_exact_convergent_shared_ptx() -> Result<(), anyhow::Error> {
+    use llvm_export::types as llvm_types;
+    use pliron::r#type::Typed;
+
+    for address_space in [0, 3] {
+        let (ctx, module_ptr) =
+            lower_all_ldmatrix_forms(address_space, mir_lower::IntrinsicBackend::LibNvvm, false)?;
+        let body = lowered_kernel_body(&ctx, module_ptr);
+        let mut lowered = Vec::new();
+        let mut cast_count = 0;
+        let mut ptrtoint_count = 0;
+
+        for op in body {
+            assert!(
+                Operation::get_op::<llvm::CallOp>(op, &ctx).is_none(),
+                "libNVVM ldmatrix lowering must not emit typed intrinsic calls"
+            );
+            cast_count +=
+                usize::from(Operation::get_op::<llvm::AddrSpaceCastOp>(op, &ctx).is_some());
+            if Operation::get_op::<llvm::PtrToIntOp>(op, &ctx).is_some() {
+                ptrtoint_count += 1;
+                let cast = op.deref(&ctx);
+                let source_ty = cast.get_operand(0).get_type(&ctx);
+                let source_ty = source_ty.deref(&ctx);
+                let source_ty = source_ty
+                    .downcast_ref::<llvm_types::PointerType>()
+                    .expect("ptrtoint source is a pointer");
+                assert_eq!(source_ty.address_space(), 3);
+            }
+
+            let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+                continue;
+            };
+            lowered.push((
+                inline_asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .unwrap_or_default(),
+                inline_asm
+                    .get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .unwrap_or_default(),
+                llvm::asm_kind(&ctx, &inline_asm),
+                op.deref(&ctx).get_num_operands(),
+                op.deref(&ctx).get_num_results(),
+            ));
+        }
+
+        assert_eq!(lowered.len(), 6);
+        for (index, expected_template) in LDMATRIX_PTX_TEMPLATES.iter().enumerate() {
+            let matching: Vec<_> = lowered
+                .iter()
+                .filter(|(template, _, _, _, _)| template == expected_template)
+                .collect();
+            assert_eq!(matching.len(), 1, "missing exact PTX `{expected_template}`");
+            let (_, constraints, kind, operands, results) = matching[0];
+            assert_eq!(constraints, LDMATRIX_PTX_CONSTRAINTS[index]);
+            assert_eq!(*kind, llvm::AsmKind::Convergent);
+            assert_eq!(*operands, 1, "inline PTX consumes one i32 shared address");
+            assert_eq!(*results, 1, "inline PTX returns one scalar or struct");
+            assert!(!expected_template.contains("cvta.to.shared"));
+        }
+        assert_eq!(cast_count, if address_space == 0 { 6 } else { 0 });
+        assert_eq!(ptrtoint_count, 6);
+
+        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+            .expect("inline ldmatrix module exports to LLVM IR");
+        assert_eq!(ir.matches("asm sideeffect").count(), 6, "{ir}");
+        assert_eq!(ir.matches("~{memory}").count(), 6, "{ir}");
+        assert!(ir.contains("attributes #0 = { convergent }"), "{ir}");
+        assert!(!ir.contains("@llvm.nvvm.ldmatrix"), "{ir}");
+    }
+    Ok(())
+}
+
+#[test]
+fn test_blackwell_ldmatrix_llvm_uses_all_exact_lossless_p3_intrinsics() -> Result<(), anyhow::Error>
+{
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::type_interfaces::FunctionTypeInterface;
+
+    for address_space in [0, 3] {
+        let (ctx, module_ptr) = lower_all_blackwell_ldmatrix_forms(
+            address_space,
+            mir_lower::IntrinsicBackend::LlvmNvptx,
+        )?;
+        let mut seen = [0; 12];
+        let mut cast_count = 0;
+        let mut extract_count = 0;
+
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            assert!(Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none());
+            assert!(Operation::get_op::<llvm::PtrToIntOp>(op, &ctx).is_none());
+            cast_count +=
+                usize::from(Operation::get_op::<llvm::AddrSpaceCastOp>(op, &ctx).is_some());
+            extract_count +=
+                usize::from(Operation::get_op::<llvm::ExtractValueOp>(op, &ctx).is_some());
+
+            let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+                continue;
+            };
+            let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+                panic!("Blackwell ldmatrix intrinsic call must be direct");
+            };
+            let callee = callee.to_string();
+            let index = BLACKWELL_LDMATRIX_CASES
+                .iter()
+                .position(|(identifier, _, _, _)| *identifier == callee)
+                .expect("exact lossless Blackwell ldmatrix identifier");
+            seen[index] += 1;
+            let register_count = BLACKWELL_LDMATRIX_CASES[index].3;
+            assert_ldmatrix_producer_result_shape(&ctx, op, register_count);
+
+            let function_ty = call.callee_type(&ctx);
+            let function_ty = function_ty.deref(&ctx);
+            let function_ty = function_ty
+                .downcast_ref::<llvm_types::FuncType>()
+                .expect("Blackwell ldmatrix has an LLVM function type");
+            assert_eq!(function_ty.arg_types().len(), 1);
+            assert_eq!(
+                function_ty.arg_types()[0]
+                    .deref(&ctx)
+                    .downcast_ref::<llvm_types::PointerType>()
+                    .expect("Blackwell ldmatrix argument is a pointer")
+                    .address_space(),
+                3
+            );
+        }
+
+        assert_eq!(seen, [1; 12]);
+        assert_eq!(cast_count, if address_space == 0 { 12 } else { 0 });
+        assert_eq!(extract_count, 30, "all multi-register results are unpacked");
+
+        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+            .expect("typed Blackwell ldmatrix module exports to LLVM IR");
+        for (identifier, symbol, _, _) in BLACKWELL_LDMATRIX_CASES {
+            assert!(
+                ir.contains(&format!("@{symbol}(ptr addrspace(3)")),
+                "missing exact intrinsic symbol {symbol}:\n{ir}"
+            );
+            assert!(
+                !ir.contains(&format!("@{identifier}(")),
+                "encoded Rust identifier leaked into LLVM IR: {identifier}"
+            );
+        }
+        assert!(ir.contains("b4x16_p64.p3"), "literal _p64 was lost: {ir}");
+        assert!(ir.contains("b6x16_p32.p3"), "literal _p32 was lost: {ir}");
+    }
+    Ok(())
+}
+
+#[test]
+fn test_blackwell_ldmatrix_libnvvm_uses_all_exact_convergent_templates_without_externs()
+-> Result<(), anyhow::Error> {
+    for address_space in [0, 3] {
+        let (ctx, module_ptr) = lower_all_blackwell_ldmatrix_forms(
+            address_space,
+            mir_lower::IntrinsicBackend::LibNvvm,
+        )?;
+        let mut seen = [0; 12];
+        let mut cast_count = 0;
+        let mut ptrtoint_count = 0;
+        let mut extract_count = 0;
+
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            assert!(
+                Operation::get_op::<llvm::CallOp>(op, &ctx).is_none(),
+                "libNVVM Blackwell ldmatrix must not emit an extern call"
+            );
+            cast_count +=
+                usize::from(Operation::get_op::<llvm::AddrSpaceCastOp>(op, &ctx).is_some());
+            ptrtoint_count +=
+                usize::from(Operation::get_op::<llvm::PtrToIntOp>(op, &ctx).is_some());
+            extract_count +=
+                usize::from(Operation::get_op::<llvm::ExtractValueOp>(op, &ctx).is_some());
+
+            let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+                continue;
+            };
+            let template = asm
+                .get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .unwrap_or_default();
+            let index = BLACKWELL_LDMATRIX_CASES
+                .iter()
+                .position(|(_, _, expected, _)| *expected == template)
+                .expect("exact Blackwell ldmatrix inline-PTX template");
+            seen[index] += 1;
+            let register_count = BLACKWELL_LDMATRIX_CASES[index].3;
+            assert_eq!(
+                asm.get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()))
+                    .as_deref(),
+                Some(ldmatrix_constraints(register_count))
+            );
+            assert_eq!(llvm::asm_kind(&ctx, &asm), llvm::AsmKind::Convergent);
+            assert_ldmatrix_producer_result_shape(&ctx, op, register_count);
+        }
+
+        assert_eq!(seen, [1; 12]);
+        assert_eq!(cast_count, if address_space == 0 { 12 } else { 0 });
+        assert_eq!(ptrtoint_count, 12);
+        assert_eq!(extract_count, 30, "all multi-register results are unpacked");
+
+        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+            .expect("inline Blackwell ldmatrix module exports to LLVM IR");
+        assert_eq!(ir.matches("asm sideeffect").count(), 12, "{ir}");
+        assert_eq!(ir.matches("~{memory}").count(), 12, "{ir}");
+        assert!(!ir.contains("@llvm.nvvm.ldmatrix"), "{ir}");
+        assert!(!ir.contains("llvm__nvvm_dldmatrix"), "{ir}");
+    }
+    Ok(())
+}
+
+#[test]
+fn test_blackwell_ldmatrix_rejects_unadmitted_m16n16_x4() {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        let mut ctx = make_test_ctx();
+        let u8_ty = IntegerType::get(&ctx, 8, Signedness::Unsigned);
+        let ptr_ty = MirPtrType::get_shared(&mut ctx, u8_ty.into(), false);
+        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into()]);
+        let pointer = entry.deref(&ctx).get_argument(0);
+        nvvm::LdmatrixOp::build(
+            &mut ctx,
+            pointer,
+            nvvm::LdmatrixShapeAttr::M16n16,
+            nvvm::LdmatrixMultiplicityAttr::X4,
+            nvvm::LdmatrixLayoutAttr::Transposed,
+            nvvm::LdmatrixElementAttr::B8,
+            nvvm::LdmatrixStateSpaceAttr::Shared,
+        )
+        .insert_at_back(entry, &ctx);
+        append_return(&mut ctx, entry);
+
+        let error = mir_lower::lower_mir_to_llvm_with_options(
+            &mut ctx,
+            module_ptr,
+            mir_lower::LoweringOptions {
+                intrinsic_backend: backend,
+                ..Default::default()
+            },
+        )
+        .expect_err("m16n16.x4 must fail closed")
+        .to_string();
+        assert!(error.contains("missing or unsupported variant"), "{error}");
+    }
+}
+
+#[test]
+fn test_classic_ldmatrix_compatibility_ops_keep_exact_lowering() -> Result<(), anyhow::Error> {
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::types::IntegerType;
+    use pliron::r#type::Typed;
+
+    fn assert_result_shape(
+        ctx: &Context,
+        op: pliron::context::Ptr<Operation>,
+        register_count: usize,
+    ) {
+        let operation = op.deref(ctx);
+        assert_eq!(operation.get_num_operands(), 1);
+        assert_eq!(operation.get_num_results(), 1);
+        let result_ty = operation.get_result(0).get_type(ctx);
+        let result_ty = result_ty.deref(ctx);
+        if register_count == 1 {
+            let result_ty = result_ty
+                .downcast_ref::<IntegerType>()
+                .expect("x1 returns i32");
+            assert_eq!(result_ty.width(), 32);
+        } else {
+            let result_ty = result_ty
+                .downcast_ref::<llvm_types::StructType>()
+                .expect("x2/x4 return an LLVM struct");
+            assert_eq!(result_ty.num_fields(), register_count);
+            for index in 0..result_ty.num_fields() {
+                let field = result_ty.field_type(index);
+                let field = field.deref(ctx);
+                let field = field
+                    .downcast_ref::<IntegerType>()
+                    .expect("fragment register is i32");
+                assert_eq!(field.width(), 32);
+            }
+        }
+    }
+
+    let register_counts = [1, 1, 2, 2, 4, 4];
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        let (ctx, module_ptr) = lower_all_ldmatrix_forms(3, backend, true)?;
+        let mut seen = [0; 6];
+        let mut extract_count = 0;
+
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            extract_count +=
+                usize::from(Operation::get_op::<llvm::ExtractValueOp>(op, &ctx).is_some());
+            match backend {
+                mir_lower::IntrinsicBackend::LlvmNvptx => {
+                    assert!(Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none());
+                    let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+                        continue;
+                    };
+                    let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+                        panic!("ldmatrix intrinsic call must be direct");
+                    };
+                    let callee = callee.to_string();
+                    let index = LDMATRIX_TYPED_INTRINSICS
+                        .iter()
+                        .position(|expected| *expected == callee)
+                        .expect("exact typed ldmatrix intrinsic");
+                    seen[index] += 1;
+                    assert_result_shape(&ctx, op, register_counts[index]);
+                }
+                mir_lower::IntrinsicBackend::LibNvvm => {
+                    assert!(Operation::get_op::<llvm::CallOp>(op, &ctx).is_none());
+                    let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+                        continue;
+                    };
+                    let template = inline_asm
+                        .get_attr_inline_asm_template(&ctx)
+                        .map(|value| String::from((*value).clone()))
+                        .unwrap_or_default();
+                    let index = LDMATRIX_PTX_TEMPLATES
+                        .iter()
+                        .position(|expected| *expected == template)
+                        .expect("exact ldmatrix PTX template");
+                    seen[index] += 1;
+                    assert_eq!(
+                        inline_asm
+                            .get_attr_inline_asm_constraints(&ctx)
+                            .map(|value| String::from((*value).clone()))
+                            .as_deref(),
+                        Some(LDMATRIX_PTX_CONSTRAINTS[index])
+                    );
+                    assert_eq!(llvm::asm_kind(&ctx, &inline_asm), llvm::AsmKind::Convergent);
+                    assert_result_shape(&ctx, op, register_counts[index]);
+                }
+            }
+        }
+
+        assert_eq!(seen, [1; 6]);
+        assert_eq!(extract_count, 12, "x2/x4 results keep their order");
+    }
+    Ok(())
+}
+
+#[test]
+fn test_ldmatrix_rejects_non_shared_pointer_spaces() {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        for address_space in [1, 4, 5] {
+            let mut ctx = make_test_ctx();
+            let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+            let ptr_ty = MirPtrType::get(&mut ctx, u32_ty.into(), false, address_space);
+            let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into()]);
+            let pointer = entry.deref(&ctx).get_argument(0);
+            nvvm::LdmatrixOp::build(
+                &mut ctx,
+                pointer,
+                nvvm::LdmatrixShapeAttr::M8n8,
+                nvvm::LdmatrixMultiplicityAttr::X1,
+                nvvm::LdmatrixLayoutAttr::Normal,
+                nvvm::LdmatrixElementAttr::B16,
+                nvvm::LdmatrixStateSpaceAttr::Shared,
+            )
+            .insert_at_back(entry, &ctx);
+            append_return(&mut ctx, entry);
+
+            let error = mir_lower::lower_mir_to_llvm_with_options(
+                &mut ctx,
+                module_ptr,
+                mir_lower::LoweringOptions {
+                    intrinsic_backend: backend,
+                    ..Default::default()
+                },
+            )
+            .expect_err("global/constant pointers must fail closed")
+            .to_string();
+            assert!(
+                error.contains(&format!("not address space {address_space}")),
+                "{error}"
+            );
+        }
+    }
+}
+
+#[test]
+fn test_ldmatrix_rejects_non_pointer_operand() {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
+    let not_a_pointer = entry.deref(&ctx).get_argument(0);
+    nvvm::LdmatrixOp::build(
+        &mut ctx,
+        not_a_pointer,
+        nvvm::LdmatrixShapeAttr::M8n8,
+        nvvm::LdmatrixMultiplicityAttr::X1,
+        nvvm::LdmatrixLayoutAttr::Normal,
+        nvvm::LdmatrixElementAttr::B16,
+        nvvm::LdmatrixStateSpaceAttr::Shared,
+    )
+    .insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    let error = mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect_err("non-pointer ldmatrix input must fail closed")
+        .to_string();
+    assert!(error.contains("operand must be a MIR pointer"), "{error}");
+}
+
+#[test]
+fn test_ldmatrix_rejects_wrong_result_arity() {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let ptr_ty = MirPtrType::get_shared(&mut ctx, u32_ty.into(), false);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![ptr_ty.into()]);
+    let pointer = entry.deref(&ctx).get_argument(0);
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::LdmatrixOp::get_concrete_op_info(),
+        vec![i32_ty.into(), i32_ty.into()],
+        vec![pointer],
+        vec![],
+        0,
+    );
+    let ldmatrix = nvvm::LdmatrixOp::new(op);
+    ldmatrix.set_attr_nvvm_ldmatrix_shape(&ctx, nvvm::LdmatrixShapeAttr::M8n8);
+    ldmatrix.set_attr_nvvm_ldmatrix_multiplicity(&ctx, nvvm::LdmatrixMultiplicityAttr::X1);
+    ldmatrix.set_attr_nvvm_ldmatrix_layout(&ctx, nvvm::LdmatrixLayoutAttr::Normal);
+    ldmatrix.set_attr_nvvm_ldmatrix_element(&ctx, nvvm::LdmatrixElementAttr::B16);
+    ldmatrix.set_attr_nvvm_ldmatrix_state_space(&ctx, nvvm::LdmatrixStateSpaceAttr::Shared);
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    let error = mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .expect_err("x1 must return exactly one register")
+        .to_string();
+    assert!(error.contains("requires 1 u32 results"), "{error}");
+}
diff --git a/crates/mir-lower/tests/lowering_test/mma.rs b/crates/mir-lower/tests/lowering_test/mma.rs
new file mode 100644
index 0000000000..e2109d53ad
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/mma.rs
@@ -0,0 +1,1754 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::ops as mir;
+use dialect_nvvm::ops as nvvm;
+use llvm_export::ops as llvm;
+use pliron::builtin::op_interfaces::SymbolOpInterface;
+use pliron::builtin::ops::ModuleOp;
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+use crate::common::{append_return, build_test_kernel, lowered_kernel_body, make_test_ctx};
+
+#[test]
+fn test_generated_register_mma_variants_lower_to_exact_convergent_inline_ptx()
+-> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{FP32Type, FP64Type, IntegerType, Signedness};
+    use pliron::r#type::TypeHandle;
+
+    #[derive(Clone, Copy)]
+    enum Carrier {
+        F32,
+        F64,
+        I32,
+        U32,
+    }
+
+    struct Case {
+        shape: nvvm::RegisterMmaShapeAttr,
+        operation: nvvm::RegisterMmaOperationAttr,
+        accumulator: nvvm::RegisterMmaAccumulatorAttr,
+        a_element: nvvm::RegisterMmaElementAttr,
+        b_element: nvvm::RegisterMmaElementAttr,
+        overflow: nvvm::RegisterMmaOverflowAttr,
+        operands: &'static [Carrier],
+        results: &'static [Carrier],
+        template: String,
+        constraints: &'static str,
+    }
+
+    let mut cases = vec![
+        Case {
+            shape: nvvm::RegisterMmaShapeAttr::M16n8k16,
+            operation: nvvm::RegisterMmaOperationAttr::Multiply,
+            accumulator: nvvm::RegisterMmaAccumulatorAttr::F32,
+            a_element: nvvm::RegisterMmaElementAttr::Bf16,
+            b_element: nvvm::RegisterMmaElementAttr::Bf16,
+            overflow: nvvm::RegisterMmaOverflowAttr::NotApplicable,
+            operands: &[
+                Carrier::F32,
+                Carrier::F32,
+                Carrier::F32,
+                Carrier::F32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+            ],
+            results: &[Carrier::F32; 4],
+            template: concat!(
+                "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 ",
+                "{$0, $1, $2, $3}, {$8, $9, $10, $11}, ",
+                "{$12, $13}, {$4, $5, $6, $7};"
+            )
+            .into(),
+            constraints: "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+        },
+        Case {
+            shape: nvvm::RegisterMmaShapeAttr::M16n8k16,
+            operation: nvvm::RegisterMmaOperationAttr::Multiply,
+            accumulator: nvvm::RegisterMmaAccumulatorAttr::F32,
+            a_element: nvvm::RegisterMmaElementAttr::F16,
+            b_element: nvvm::RegisterMmaElementAttr::F16,
+            overflow: nvvm::RegisterMmaOverflowAttr::NotApplicable,
+            operands: &[
+                Carrier::F32,
+                Carrier::F32,
+                Carrier::F32,
+                Carrier::F32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+            ],
+            results: &[Carrier::F32; 4],
+            template: concat!(
+                "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 ",
+                "{$0, $1, $2, $3}, {$8, $9, $10, $11}, ",
+                "{$12, $13}, {$4, $5, $6, $7};"
+            )
+            .into(),
+            constraints: "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+        },
+        Case {
+            shape: nvvm::RegisterMmaShapeAttr::M16n8k8,
+            operation: nvvm::RegisterMmaOperationAttr::Multiply,
+            accumulator: nvvm::RegisterMmaAccumulatorAttr::F32,
+            a_element: nvvm::RegisterMmaElementAttr::Tf32,
+            b_element: nvvm::RegisterMmaElementAttr::Tf32,
+            overflow: nvvm::RegisterMmaOverflowAttr::NotApplicable,
+            operands: &[
+                Carrier::F32,
+                Carrier::F32,
+                Carrier::F32,
+                Carrier::F32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+                Carrier::U32,
+            ],
+            results: &[Carrier::F32; 4],
+            template: concat!(
+                "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 ",
+                "{$0, $1, $2, $3}, {$8, $9, $10, $11}, ",
+                "{$12, $13}, {$4, $5, $6, $7};"
+            )
+            .into(),
+            constraints: "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r",
+        },
+        Case {
+            shape: nvvm::RegisterMmaShapeAttr::M8n8k4,
+            operation: nvvm::RegisterMmaOperationAttr::Multiply,
+            accumulator: nvvm::RegisterMmaAccumulatorAttr::F64,
+            a_element: nvvm::RegisterMmaElementAttr::F64,
+            b_element: nvvm::RegisterMmaElementAttr::F64,
+            overflow: nvvm::RegisterMmaOverflowAttr::NotApplicable,
+            operands: &[Carrier::F64; 4],
+            results: &[Carrier::F64; 2],
+            template: concat!(
+                "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 ",
+                "{$0, $1}, {$4}, {$5}, {$2, $3};"
+            )
+            .into(),
+            constraints: "=d,=d,d,d,d,d",
+        },
+    ];
+    let c2_a1_b1: &'static [Carrier] = &[Carrier::I32, Carrier::I32, Carrier::U32, Carrier::U32];
+    let c4_a2_b1: &'static [Carrier] = &[
+        Carrier::I32,
+        Carrier::I32,
+        Carrier::I32,
+        Carrier::I32,
+        Carrier::U32,
+        Carrier::U32,
+        Carrier::U32,
+    ];
+    let c4_a4_b2: &'static [Carrier] = &[
+        Carrier::I32,
+        Carrier::I32,
+        Carrier::I32,
+        Carrier::I32,
+        Carrier::U32,
+        Carrier::U32,
+        Carrier::U32,
+        Carrier::U32,
+        Carrier::U32,
+        Carrier::U32,
+    ];
+    let d2_i32: &'static [Carrier] = &[Carrier::I32; 2];
+    let d4_i32: &'static [Carrier] = &[Carrier::I32; 4];
+    let register_list = |first, count| {
+        format!(
+            "{{{}}}",
+            (first..first + count)
+                .map(|index| format!("${index}"))
+                .collect::<Vec<_>>()
+                .join(", ")
+        )
+    };
+
+    for (shape, shape_attr, operands, results, accumulator_count, a_count, b_count, constraints) in [
+        (
+            "m8n8k16",
+            nvvm::RegisterMmaShapeAttr::M8n8k16,
+            c2_a1_b1,
+            d2_i32,
+            2,
+            1,
+            1,
+            "=r,=r,r,r,r,r",
+        ),
+        (
+            "m16n8k16",
+            nvvm::RegisterMmaShapeAttr::M16n8k16,
+            c4_a2_b1,
+            d4_i32,
+            4,
+            2,
+            1,
+            "=r,=r,=r,=r,r,r,r,r,r,r,r",
+        ),
+        (
+            "m16n8k32",
+            nvvm::RegisterMmaShapeAttr::M16n8k32,
+            c4_a4_b2,
+            d4_i32,
+            4,
+            4,
+            2,
+            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+        ),
+    ] {
+        for (a_name, a_element) in [
+            ("s8", nvvm::RegisterMmaElementAttr::S8),
+            ("u8", nvvm::RegisterMmaElementAttr::U8),
+        ] {
+            for (b_name, b_element) in [
+                ("s8", nvvm::RegisterMmaElementAttr::S8),
+                ("u8", nvvm::RegisterMmaElementAttr::U8),
+            ] {
+                for (overflow_name, overflow) in [
+                    ("", nvvm::RegisterMmaOverflowAttr::Wrapping),
+                    (".satfinite", nvvm::RegisterMmaOverflowAttr::Satfinite),
+                ] {
+                    let result_count = results.len();
+                    let d = register_list(0, result_count);
+                    let c = register_list(result_count, accumulator_count);
+                    let a = register_list(result_count + accumulator_count, a_count);
+                    let b = register_list(result_count + accumulator_count + a_count, b_count);
+                    cases.push(Case {
+                        shape: shape_attr.clone(),
+                        operation: nvvm::RegisterMmaOperationAttr::Multiply,
+                        accumulator: nvvm::RegisterMmaAccumulatorAttr::S32,
+                        a_element: a_element.clone(),
+                        b_element: b_element.clone(),
+                        overflow,
+                        operands,
+                        results,
+                        template: format!(
+                            "mma.sync.aligned.{shape}.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {d}, {a}, {b}, {c};"
+                        ),
+                        constraints,
+                    });
+                }
+            }
+        }
+    }
+
+    for (shape, shape_attr, operands, results, accumulator_count, a_count, b_count, constraints) in [
+        (
+            "m8n8k32",
+            nvvm::RegisterMmaShapeAttr::M8n8k32,
+            c2_a1_b1,
+            d2_i32,
+            2,
+            1,
+            1,
+            "=r,=r,r,r,r,r",
+        ),
+        (
+            "m16n8k32",
+            nvvm::RegisterMmaShapeAttr::M16n8k32,
+            c4_a2_b1,
+            d4_i32,
+            4,
+            2,
+            1,
+            "=r,=r,=r,=r,r,r,r,r,r,r,r",
+        ),
+        (
+            "m16n8k64",
+            nvvm::RegisterMmaShapeAttr::M16n8k64,
+            c4_a4_b2,
+            d4_i32,
+            4,
+            4,
+            2,
+            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+        ),
+    ] {
+        for (a_name, a_element) in [
+            ("s4", nvvm::RegisterMmaElementAttr::S4),
+            ("u4", nvvm::RegisterMmaElementAttr::U4),
+        ] {
+            for (b_name, b_element) in [
+                ("s4", nvvm::RegisterMmaElementAttr::S4),
+                ("u4", nvvm::RegisterMmaElementAttr::U4),
+            ] {
+                for (overflow_name, overflow) in [
+                    ("", nvvm::RegisterMmaOverflowAttr::Wrapping),
+                    (".satfinite", nvvm::RegisterMmaOverflowAttr::Satfinite),
+                ] {
+                    let result_count = results.len();
+                    let d = register_list(0, result_count);
+                    let c = register_list(result_count, accumulator_count);
+                    let a = register_list(result_count + accumulator_count, a_count);
+                    let b = register_list(result_count + accumulator_count + a_count, b_count);
+                    cases.push(Case {
+                        shape: shape_attr.clone(),
+                        operation: nvvm::RegisterMmaOperationAttr::Multiply,
+                        accumulator: nvvm::RegisterMmaAccumulatorAttr::S32,
+                        a_element: a_element.clone(),
+                        b_element: b_element.clone(),
+                        overflow,
+                        operands,
+                        results,
+                        template: format!(
+                            "mma.sync.aligned.{shape}.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {d}, {a}, {b}, {c};"
+                        ),
+                        constraints,
+                    });
+                }
+            }
+        }
+    }
+
+    for (shape, shape_attr, operands, results, accumulator_count, a_count, b_count, constraints) in [
+        (
+            "m8n8k128",
+            nvvm::RegisterMmaShapeAttr::M8n8k128,
+            c2_a1_b1,
+            d2_i32,
+            2,
+            1,
+            1,
+            "=r,=r,r,r,r,r",
+        ),
+        (
+            "m16n8k128",
+            nvvm::RegisterMmaShapeAttr::M16n8k128,
+            c4_a2_b1,
+            d4_i32,
+            4,
+            2,
+            1,
+            "=r,=r,=r,=r,r,r,r,r,r,r,r",
+        ),
+        (
+            "m16n8k256",
+            nvvm::RegisterMmaShapeAttr::M16n8k256,
+            c4_a4_b2,
+            d4_i32,
+            4,
+            4,
+            2,
+            "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r",
+        ),
+    ] {
+        let result_count = results.len();
+        let d = register_list(0, result_count);
+        let c = register_list(result_count, accumulator_count);
+        let a = register_list(result_count + accumulator_count, a_count);
+        let b = register_list(result_count + accumulator_count + a_count, b_count);
+        for (operation_name, operation) in [
+            ("xor", nvvm::RegisterMmaOperationAttr::XorPopc),
+            ("and", nvvm::RegisterMmaOperationAttr::AndPopc),
+        ] {
+            cases.push(Case {
+                shape: shape_attr.clone(),
+                operation,
+                accumulator: nvvm::RegisterMmaAccumulatorAttr::S32,
+                a_element: nvvm::RegisterMmaElementAttr::B1,
+                b_element: nvvm::RegisterMmaElementAttr::B1,
+                overflow: nvvm::RegisterMmaOverflowAttr::Wrapping,
+                operands,
+                results,
+                template: format!(
+                    "mma.sync.aligned.{shape}.row.col.s32.b1.b1.s32.{operation_name}.popc {d}, {a}, {b}, {c};"
+                ),
+                constraints,
+            });
+        }
+    }
+    assert_eq!(cases.len(), 58);
+
+    let carrier_type = |ctx: &Context, carrier: Carrier| -> TypeHandle {
+        match carrier {
+            Carrier::F32 => FP32Type::get(ctx).into(),
+            Carrier::F64 => FP64Type::get(ctx).into(),
+            Carrier::I32 => IntegerType::get(ctx, 32, Signedness::Signed).into(),
+            Carrier::U32 => IntegerType::get(ctx, 32, Signedness::Unsigned).into(),
+        }
+    };
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        for case in &cases {
+            let mut ctx = make_test_ctx();
+            let argument_types = case
+                .operands
+                .iter()
+                .map(|carrier| carrier_type(&ctx, *carrier))
+                .collect();
+            let result_types = case
+                .results
+                .iter()
+                .map(|carrier| carrier_type(&ctx, *carrier))
+                .collect();
+            let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+            let operands = (0..case.operands.len())
+                .map(|index| entry.deref(&ctx).get_argument(index))
+                .collect();
+            let operation = Operation::new(
+                &mut ctx,
+                nvvm::RegisterMmaOp::get_concrete_op_info(),
+                result_types,
+                operands,
+                vec![],
+                0,
+            );
+            let mma = nvvm::RegisterMmaOp::new(operation);
+            mma.set_attr_nvvm_register_mma_shape(&ctx, case.shape.clone());
+            let uses_legacy_default = matches!(
+                (&case.operation, &case.a_element),
+                (
+                    nvvm::RegisterMmaOperationAttr::Multiply,
+                    nvvm::RegisterMmaElementAttr::Bf16
+                )
+            );
+            if !uses_legacy_default {
+                mma.set_attr_nvvm_register_mma_operation(&ctx, case.operation.clone());
+            }
+            mma.set_attr_nvvm_register_mma_accumulator(&ctx, case.accumulator.clone());
+            mma.set_attr_nvvm_register_mma_a_element(&ctx, case.a_element.clone());
+            mma.set_attr_nvvm_register_mma_b_element(&ctx, case.b_element.clone());
+            mma.set_attr_nvvm_register_mma_a_layout(&ctx, nvvm::RegisterMmaLayoutAttr::Row);
+            mma.set_attr_nvvm_register_mma_b_layout(&ctx, nvvm::RegisterMmaLayoutAttr::Col);
+            mma.set_attr_nvvm_register_mma_overflow(&ctx, case.overflow.clone());
+            operation.insert_at_back(entry, &ctx);
+            append_return(&mut ctx, entry);
+
+            mir_lower::lower_mir_to_llvm_with_options(
+                &mut ctx,
+                module_ptr,
+                mir_lower::LoweringOptions {
+                    intrinsic_backend: backend,
+                    ..Default::default()
+                },
+            )
+            .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+            let body = lowered_kernel_body(&ctx, module_ptr);
+            let lowered = body
+                .iter()
+                .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(*op, &ctx))
+                .collect::<Vec<_>>();
+            assert_eq!(lowered.len(), 1, "{:?}", backend);
+            let asm = &lowered[0];
+            assert_eq!(
+                asm.get_attr_inline_asm_template(&ctx)
+                    .as_deref()
+                    .map(|value| String::from(value.clone())),
+                Some(case.template.clone())
+            );
+            assert_eq!(
+                asm.get_attr_inline_asm_constraints(&ctx)
+                    .as_deref()
+                    .map(|value| String::from(value.clone())),
+                Some(case.constraints.to_string())
+            );
+            assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+            assert_eq!(
+                asm.get_operation().deref(&ctx).get_num_operands(),
+                case.operands.len()
+            );
+            assert_eq!(asm.get_operation().deref(&ctx).get_num_results(), 1);
+            assert_eq!(
+                body.iter()
+                    .filter(|op| Operation::get_op::<llvm::ExtractValueOp>(**op, &ctx).is_some())
+                    .count(),
+                case.results.len()
+            );
+
+            let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+            let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+                .expect("generated register MMA exports to LLVM IR");
+            assert!(ir.contains("asm sideeffect"), "{ir}");
+            assert!(ir.contains("{ convergent }"), "{ir}");
+        }
+    }
+
+    Ok(())
+}
+
+#[test]
+fn test_generated_sparse_mma_variants_lower_to_exact_convergent_inline_ptx()
+-> Result<(), anyhow::Error> {
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let cases = [
+        (
+            "s8",
+            "s8",
+            "",
+            nvvm::SparseMmaElementAttr::S8,
+            nvvm::SparseMmaElementAttr::S8,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "s8",
+            "u8",
+            "",
+            nvvm::SparseMmaElementAttr::S8,
+            nvvm::SparseMmaElementAttr::U8,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "u8",
+            "u8",
+            "",
+            nvvm::SparseMmaElementAttr::U8,
+            nvvm::SparseMmaElementAttr::U8,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "u8",
+            "s8",
+            "",
+            nvvm::SparseMmaElementAttr::U8,
+            nvvm::SparseMmaElementAttr::S8,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "s8",
+            "s8",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::S8,
+            nvvm::SparseMmaElementAttr::S8,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            "s8",
+            "u8",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::S8,
+            nvvm::SparseMmaElementAttr::U8,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            "u8",
+            "u8",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::U8,
+            nvvm::SparseMmaElementAttr::U8,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            "u8",
+            "s8",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::U8,
+            nvvm::SparseMmaElementAttr::S8,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+    ];
+    let metadata_modes = [
+        ("sp", nvvm::SparseMmaMetadataAttr::Standard),
+        ("sp::ordered_metadata", nvvm::SparseMmaMetadataAttr::Ordered),
+    ];
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        for (metadata_name, metadata) in &metadata_modes {
+            for (index, (a_name, b_name, overflow_name, a_element, b_element, overflow)) in
+                cases.iter().enumerate()
+            {
+                let mut ctx = make_test_ctx();
+                let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+                let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+                let argument_types = (0..4)
+                    .map(|_| i32_ty.into())
+                    .chain((0..5).map(|_| u32_ty.into()))
+                    .collect();
+                let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+
+                let selector_value = (index % 2) as u32;
+                let selector_op = Operation::new(
+                    &mut ctx,
+                    mir::MirConstantOp::get_concrete_op_info(),
+                    vec![u32_ty.into()],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                mir::MirConstantOp::new(selector_op).set_attr_value(
+                    &ctx,
+                    IntegerAttr::new(
+                        u32_ty,
+                        APInt::from_u32(selector_value, NonZeroUsize::new(32).unwrap()),
+                    ),
+                );
+                selector_op.insert_at_back(entry, &ctx);
+                let selector = selector_op.deref(&ctx).get_result(0);
+
+                let operands = (0..9)
+                    .map(|operand| entry.deref(&ctx).get_argument(operand))
+                    .chain(std::iter::once(selector))
+                    .collect();
+                let operation = Operation::new(
+                    &mut ctx,
+                    nvvm::SparseMmaOp::get_concrete_op_info(),
+                    vec![i32_ty.into(); 4],
+                    operands,
+                    vec![],
+                    0,
+                );
+                let mma = nvvm::SparseMmaOp::new(operation);
+                mma.set_attr_nvvm_sparse_mma_shape(&ctx, nvvm::SparseMmaShapeAttr::M16n8k32);
+                mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, nvvm::SparseMmaAccumulatorAttr::S32);
+                mma.set_attr_nvvm_sparse_mma_a_element(&ctx, a_element.clone());
+                mma.set_attr_nvvm_sparse_mma_b_element(&ctx, b_element.clone());
+                mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, nvvm::SparseMmaLayoutAttr::Row);
+                mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, nvvm::SparseMmaLayoutAttr::Col);
+                mma.set_attr_nvvm_sparse_mma_overflow(&ctx, overflow.clone());
+                mma.set_attr_nvvm_sparse_mma_metadata(&ctx, metadata.clone());
+                mma.set_attr_nvvm_sparse_mma_selector(
+                    &ctx,
+                    nvvm::SparseMmaSelectorAttr::ImmediateZeroOrOne,
+                );
+                operation.insert_at_back(entry, &ctx);
+                append_return(&mut ctx, entry);
+
+                mir_lower::lower_mir_to_llvm_with_options(
+                    &mut ctx,
+                    module_ptr,
+                    mir_lower::LoweringOptions {
+                        intrinsic_backend: backend,
+                        ..Default::default()
+                    },
+                )
+                .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+                let body = lowered_kernel_body(&ctx, module_ptr);
+                let lowered = body
+                    .iter()
+                    .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(*op, &ctx))
+                    .collect::<Vec<_>>();
+                assert_eq!(lowered.len(), 1, "{backend:?}");
+                let asm = &lowered[0];
+                let expected_template = format!(
+                    "mma.{metadata_name}.sync.aligned.m16n8k32.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {{$0, $1, $2, $3}}, {{$8, $9}}, {{$10, $11}}, {{$4, $5, $6, $7}}, $12, $13;"
+                );
+                assert_eq!(
+                    asm.get_attr_inline_asm_template(&ctx)
+                        .as_deref()
+                        .map(|value| String::from(value.clone())),
+                    Some(expected_template)
+                );
+                assert_eq!(
+                    asm.get_attr_inline_asm_constraints(&ctx)
+                        .as_deref()
+                        .map(|value| String::from(value.clone())),
+                    Some("=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n".to_string())
+                );
+                assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+                let asm_operation = asm.get_operation().deref(&ctx);
+                assert_eq!(asm_operation.get_num_operands(), 10);
+                assert_eq!(asm_operation.get_num_results(), 1);
+                let lowered_selector = asm_operation.get_operand(9);
+                let defining_op = lowered_selector
+                    .defining_op()
+                    .expect("sparse MMA selector remains an LLVM constant");
+                let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
+                    .expect("sparse MMA selector remains an LLVM integer constant");
+                let attribute = constant.get_value(&ctx);
+                let integer = attribute
+                    .downcast_ref::<IntegerAttr>()
+                    .expect("sparse MMA selector is an integer");
+                assert_eq!(integer.value().bw(), 32);
+                assert_eq!(integer.value().to_u64(), selector_value as u64);
+                assert_eq!(
+                    body.iter()
+                        .filter(|op| {
+                            Operation::get_op::<llvm::ExtractValueOp>(**op, &ctx).is_some()
+                        })
+                        .count(),
+                    4
+                );
+
+                let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+                let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+                    .expect("generated sparse MMA exports to LLVM IR");
+                assert!(ir.contains("asm sideeffect"), "{ir}");
+                assert!(ir.contains("{ convergent }"), "{ir}");
+            }
+        }
+    }
+
+    Ok(())
+}
+
+#[test]
+fn test_generated_sparse_mma_m16n8k64_lowers_to_exact_convergent_inline_ptx()
+-> Result<(), anyhow::Error> {
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let cases = [
+        (
+            "s8",
+            "u8",
+            "",
+            nvvm::SparseMmaElementAttr::S8,
+            nvvm::SparseMmaElementAttr::U8,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "u8",
+            "s8",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::U8,
+            nvvm::SparseMmaElementAttr::S8,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+    ];
+    let metadata_cases = [
+        ("sp", nvvm::SparseMmaMetadataAttr::Standard),
+        ("sp::ordered_metadata", nvvm::SparseMmaMetadataAttr::Ordered),
+    ];
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        for (metadata_name, metadata) in &metadata_cases {
+            for (a_name, b_name, overflow_name, a_element, b_element, overflow) in &cases {
+                let mut ctx = make_test_ctx();
+                let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+                let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+                let argument_types = (0..4)
+                    .map(|_| i32_ty.into())
+                    .chain((0..9).map(|_| u32_ty.into()))
+                    .collect();
+                let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+
+                let selector_op = Operation::new(
+                    &mut ctx,
+                    mir::MirConstantOp::get_concrete_op_info(),
+                    vec![u32_ty.into()],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                mir::MirConstantOp::new(selector_op).set_attr_value(
+                    &ctx,
+                    IntegerAttr::new(u32_ty, APInt::from_u32(0, NonZeroUsize::new(32).unwrap())),
+                );
+                selector_op.insert_at_back(entry, &ctx);
+                let selector = selector_op.deref(&ctx).get_result(0);
+
+                let operands = (0..13)
+                    .map(|index| entry.deref(&ctx).get_argument(index))
+                    .chain(std::iter::once(selector))
+                    .collect();
+                let operation = Operation::new(
+                    &mut ctx,
+                    nvvm::SparseMmaOp::get_concrete_op_info(),
+                    vec![i32_ty.into(); 4],
+                    operands,
+                    vec![],
+                    0,
+                );
+                let mma = nvvm::SparseMmaOp::new(operation);
+                mma.set_attr_nvvm_sparse_mma_shape(&ctx, nvvm::SparseMmaShapeAttr::M16n8k64);
+                mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, nvvm::SparseMmaAccumulatorAttr::S32);
+                mma.set_attr_nvvm_sparse_mma_a_element(&ctx, a_element.clone());
+                mma.set_attr_nvvm_sparse_mma_b_element(&ctx, b_element.clone());
+                mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, nvvm::SparseMmaLayoutAttr::Row);
+                mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, nvvm::SparseMmaLayoutAttr::Col);
+                mma.set_attr_nvvm_sparse_mma_overflow(&ctx, overflow.clone());
+                mma.set_attr_nvvm_sparse_mma_metadata(&ctx, metadata.clone());
+                mma.set_attr_nvvm_sparse_mma_selector(
+                    &ctx,
+                    nvvm::SparseMmaSelectorAttr::ImmediateZero,
+                );
+                operation.insert_at_back(entry, &ctx);
+                append_return(&mut ctx, entry);
+
+                mir_lower::lower_mir_to_llvm_with_options(
+                    &mut ctx,
+                    module_ptr,
+                    mir_lower::LoweringOptions {
+                        intrinsic_backend: backend,
+                        ..Default::default()
+                    },
+                )
+                .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+                let body = lowered_kernel_body(&ctx, module_ptr);
+                let lowered = body
+                    .iter()
+                    .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(*op, &ctx))
+                    .collect::<Vec<_>>();
+                assert_eq!(lowered.len(), 1, "{backend:?}");
+                let asm = &lowered[0];
+                let expected_template = format!(
+                    "mma.{metadata_name}.sync.aligned.m16n8k64.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {{$0, $1, $2, $3}}, {{$8, $9, $10, $11}}, {{$12, $13, $14, $15}}, {{$4, $5, $6, $7}}, $16, $17;"
+                );
+                assert_eq!(
+                    asm.get_attr_inline_asm_template(&ctx)
+                        .as_deref()
+                        .map(|value| String::from(value.clone())),
+                    Some(expected_template)
+                );
+                assert_eq!(
+                    asm.get_attr_inline_asm_constraints(&ctx)
+                        .as_deref()
+                        .map(|value| String::from(value.clone())),
+                    Some("=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n".to_string())
+                );
+                assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+                let asm_operation = asm.get_operation().deref(&ctx);
+                assert_eq!(asm_operation.get_num_operands(), 14);
+                assert_eq!(asm_operation.get_num_results(), 1);
+                let lowered_selector = asm_operation.get_operand(13);
+                let defining_op = lowered_selector
+                    .defining_op()
+                    .expect("sparse MMA selector remains an LLVM constant");
+                let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
+                    .expect("sparse MMA selector remains an LLVM integer constant");
+                let attribute = constant.get_value(&ctx);
+                let integer = attribute
+                    .downcast_ref::<IntegerAttr>()
+                    .expect("sparse MMA selector is an integer");
+                assert_eq!(integer.value().bw(), 32);
+                assert_eq!(integer.value().to_u64(), 0);
+                assert_eq!(
+                    body.iter()
+                        .filter(|op| {
+                            Operation::get_op::<llvm::ExtractValueOp>(**op, &ctx).is_some()
+                        })
+                        .count(),
+                    4
+                );
+
+                let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+                let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+                    .expect("generated sparse MMA exports to LLVM IR");
+                assert!(ir.contains("asm sideeffect"), "{ir}");
+                assert!(ir.contains("{ convergent }"), "{ir}");
+            }
+        }
+    }
+
+    Ok(())
+}
+
+#[test]
+fn test_generated_sparse_mma_m16n8k64_int4_lowers_both_metadata_modes() -> Result<(), anyhow::Error>
+{
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let cases = [
+        (
+            "s4",
+            "s4",
+            "",
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "s4",
+            "u4",
+            "",
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "u4",
+            "u4",
+            "",
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "u4",
+            "s4",
+            "",
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "s4",
+            "s4",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            "s4",
+            "u4",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            "u4",
+            "u4",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            "u4",
+            "s4",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+    ];
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        for (metadata_name, metadata) in [
+            ("sp", nvvm::SparseMmaMetadataAttr::Standard),
+            ("sp::ordered_metadata", nvvm::SparseMmaMetadataAttr::Ordered),
+        ] {
+            for (index, (a_name, b_name, overflow_name, a_element, b_element, overflow)) in
+                cases.iter().enumerate()
+            {
+                let mut ctx = make_test_ctx();
+                let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+                let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+                let argument_types = (0..4)
+                    .map(|_| i32_ty.into())
+                    .chain((0..5).map(|_| u32_ty.into()))
+                    .collect();
+                let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+
+                let selector_value = (index % 2) as u32;
+                let selector_op = Operation::new(
+                    &mut ctx,
+                    mir::MirConstantOp::get_concrete_op_info(),
+                    vec![u32_ty.into()],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                mir::MirConstantOp::new(selector_op).set_attr_value(
+                    &ctx,
+                    IntegerAttr::new(
+                        u32_ty,
+                        APInt::from_u32(selector_value, NonZeroUsize::new(32).unwrap()),
+                    ),
+                );
+                selector_op.insert_at_back(entry, &ctx);
+                let selector = selector_op.deref(&ctx).get_result(0);
+
+                let operands = (0..9)
+                    .map(|operand| entry.deref(&ctx).get_argument(operand))
+                    .chain(std::iter::once(selector))
+                    .collect();
+                let operation = Operation::new(
+                    &mut ctx,
+                    nvvm::SparseMmaOp::get_concrete_op_info(),
+                    vec![i32_ty.into(); 4],
+                    operands,
+                    vec![],
+                    0,
+                );
+                let mma = nvvm::SparseMmaOp::new(operation);
+                mma.set_attr_nvvm_sparse_mma_shape(&ctx, nvvm::SparseMmaShapeAttr::M16n8k64);
+                mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, nvvm::SparseMmaAccumulatorAttr::S32);
+                mma.set_attr_nvvm_sparse_mma_a_element(&ctx, a_element.clone());
+                mma.set_attr_nvvm_sparse_mma_b_element(&ctx, b_element.clone());
+                mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, nvvm::SparseMmaLayoutAttr::Row);
+                mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, nvvm::SparseMmaLayoutAttr::Col);
+                mma.set_attr_nvvm_sparse_mma_overflow(&ctx, overflow.clone());
+                mma.set_attr_nvvm_sparse_mma_metadata(&ctx, metadata.clone());
+                mma.set_attr_nvvm_sparse_mma_selector(
+                    &ctx,
+                    nvvm::SparseMmaSelectorAttr::ImmediateZeroOrOne,
+                );
+                operation.insert_at_back(entry, &ctx);
+                append_return(&mut ctx, entry);
+
+                mir_lower::lower_mir_to_llvm_with_options(
+                    &mut ctx,
+                    module_ptr,
+                    mir_lower::LoweringOptions {
+                        intrinsic_backend: backend,
+                        ..Default::default()
+                    },
+                )
+                .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+                let body = lowered_kernel_body(&ctx, module_ptr);
+                let lowered = body
+                    .iter()
+                    .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(*op, &ctx))
+                    .collect::<Vec<_>>();
+                assert_eq!(lowered.len(), 1, "{backend:?}");
+                let asm = &lowered[0];
+                let expected_template = format!(
+                    "mma.{metadata_name}.sync.aligned.m16n8k64.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {{$0, $1, $2, $3}}, {{$8, $9}}, {{$10, $11}}, {{$4, $5, $6, $7}}, $12, $13;"
+                );
+                assert_eq!(
+                    asm.get_attr_inline_asm_template(&ctx)
+                        .as_deref()
+                        .map(|value| String::from(value.clone())),
+                    Some(expected_template)
+                );
+                assert_eq!(
+                    asm.get_attr_inline_asm_constraints(&ctx)
+                        .as_deref()
+                        .map(|value| String::from(value.clone())),
+                    Some("=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,n".to_string())
+                );
+                assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+                let asm_operation = asm.get_operation().deref(&ctx);
+                assert_eq!(asm_operation.get_num_operands(), 10);
+                assert_eq!(asm_operation.get_num_results(), 1);
+                let lowered_selector = asm_operation.get_operand(9);
+                let defining_op = lowered_selector
+                    .defining_op()
+                    .expect("sparse MMA selector remains an LLVM constant");
+                let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
+                    .expect("sparse MMA selector remains an LLVM integer constant");
+                let attribute = constant.get_value(&ctx);
+                let integer = attribute
+                    .downcast_ref::<IntegerAttr>()
+                    .expect("sparse MMA selector is an integer");
+                assert_eq!(integer.value().to_u64(), selector_value as u64);
+
+                let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+                let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+                    .expect("generated sparse MMA exports to LLVM IR");
+                assert!(ir.contains("asm sideeffect"), "{ir}");
+                assert!(ir.contains("{ convergent }"), "{ir}");
+            }
+        }
+    }
+
+    Ok(())
+}
+
+#[test]
+fn test_generated_sparse_mma_m16n8k128_int4_lowers_both_metadata_modes() -> Result<(), anyhow::Error>
+{
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let cases = [
+        (
+            "s4",
+            "s4",
+            "",
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "s4",
+            "u4",
+            "",
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "u4",
+            "u4",
+            "",
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "u4",
+            "s4",
+            "",
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaOverflowAttr::Wrapping,
+        ),
+        (
+            "s4",
+            "s4",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            "s4",
+            "u4",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            "u4",
+            "u4",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+        (
+            "u4",
+            "s4",
+            ".satfinite",
+            nvvm::SparseMmaElementAttr::U4,
+            nvvm::SparseMmaElementAttr::S4,
+            nvvm::SparseMmaOverflowAttr::Satfinite,
+        ),
+    ];
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        for (metadata_name, metadata) in [
+            ("sp", nvvm::SparseMmaMetadataAttr::Standard),
+            ("sp::ordered_metadata", nvvm::SparseMmaMetadataAttr::Ordered),
+        ] {
+            for (a_name, b_name, overflow_name, a_element, b_element, overflow) in &cases {
+                let mut ctx = make_test_ctx();
+                let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signed);
+                let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+                let argument_types = (0..4)
+                    .map(|_| i32_ty.into())
+                    .chain((0..9).map(|_| u32_ty.into()))
+                    .collect();
+                let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+
+                let selector_op = Operation::new(
+                    &mut ctx,
+                    mir::MirConstantOp::get_concrete_op_info(),
+                    vec![u32_ty.into()],
+                    vec![],
+                    vec![],
+                    0,
+                );
+                mir::MirConstantOp::new(selector_op).set_attr_value(
+                    &ctx,
+                    IntegerAttr::new(u32_ty, APInt::from_u32(0, NonZeroUsize::new(32).unwrap())),
+                );
+                selector_op.insert_at_back(entry, &ctx);
+                let selector = selector_op.deref(&ctx).get_result(0);
+
+                let operands = (0..13)
+                    .map(|operand| entry.deref(&ctx).get_argument(operand))
+                    .chain(std::iter::once(selector))
+                    .collect();
+                let operation = Operation::new(
+                    &mut ctx,
+                    nvvm::SparseMmaOp::get_concrete_op_info(),
+                    vec![i32_ty.into(); 4],
+                    operands,
+                    vec![],
+                    0,
+                );
+                let mma = nvvm::SparseMmaOp::new(operation);
+                mma.set_attr_nvvm_sparse_mma_shape(&ctx, nvvm::SparseMmaShapeAttr::M16n8k128);
+                mma.set_attr_nvvm_sparse_mma_accumulator(&ctx, nvvm::SparseMmaAccumulatorAttr::S32);
+                mma.set_attr_nvvm_sparse_mma_a_element(&ctx, a_element.clone());
+                mma.set_attr_nvvm_sparse_mma_b_element(&ctx, b_element.clone());
+                mma.set_attr_nvvm_sparse_mma_a_layout(&ctx, nvvm::SparseMmaLayoutAttr::Row);
+                mma.set_attr_nvvm_sparse_mma_b_layout(&ctx, nvvm::SparseMmaLayoutAttr::Col);
+                mma.set_attr_nvvm_sparse_mma_overflow(&ctx, overflow.clone());
+                mma.set_attr_nvvm_sparse_mma_metadata(&ctx, metadata.clone());
+                mma.set_attr_nvvm_sparse_mma_selector(
+                    &ctx,
+                    nvvm::SparseMmaSelectorAttr::ImmediateZero,
+                );
+                operation.insert_at_back(entry, &ctx);
+                append_return(&mut ctx, entry);
+
+                mir_lower::lower_mir_to_llvm_with_options(
+                    &mut ctx,
+                    module_ptr,
+                    mir_lower::LoweringOptions {
+                        intrinsic_backend: backend,
+                        ..Default::default()
+                    },
+                )
+                .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+                let body = lowered_kernel_body(&ctx, module_ptr);
+                let lowered = body
+                    .iter()
+                    .filter_map(|op| Operation::get_op::<llvm::InlineAsmOp>(*op, &ctx))
+                    .collect::<Vec<_>>();
+                assert_eq!(lowered.len(), 1, "{backend:?}");
+                let asm = &lowered[0];
+                let expected_template = format!(
+                    "mma.{metadata_name}.sync.aligned.m16n8k128.row.col{overflow_name}.s32.{a_name}.{b_name}.s32 {{$0, $1, $2, $3}}, {{$8, $9, $10, $11}}, {{$12, $13, $14, $15}}, {{$4, $5, $6, $7}}, $16, $17;"
+                );
+                assert_eq!(
+                    asm.get_attr_inline_asm_template(&ctx)
+                        .as_deref()
+                        .map(|value| String::from(value.clone())),
+                    Some(expected_template)
+                );
+                assert_eq!(
+                    asm.get_attr_inline_asm_constraints(&ctx)
+                        .as_deref()
+                        .map(|value| String::from(value.clone())),
+                    Some("=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n".to_string())
+                );
+                assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+                let asm_operation = asm.get_operation().deref(&ctx);
+                assert_eq!(asm_operation.get_num_operands(), 14);
+                assert_eq!(asm_operation.get_num_results(), 1);
+                let lowered_selector = asm_operation.get_operand(13);
+                let defining_op = lowered_selector
+                    .defining_op()
+                    .expect("sparse MMA selector remains an LLVM constant");
+                let constant = Operation::get_op::<llvm::ConstantOp>(defining_op, &ctx)
+                    .expect("sparse MMA selector remains an LLVM integer constant");
+                let attribute = constant.get_value(&ctx);
+                let integer = attribute
+                    .downcast_ref::<IntegerAttr>()
+                    .expect("sparse MMA selector is an integer");
+                assert_eq!(integer.value().to_u64(), 0);
+
+                let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+                let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+                    .expect("generated sparse MMA exports to LLVM IR");
+                assert!(ir.contains("asm sideeffect"), "{ir}");
+                assert!(ir.contains("{ convergent }"), "{ir}");
+            }
+        }
+    }
+
+    Ok(())
+}
+
+// ---------------------------------------------------------------------------
+// mma.sync m16n8k16 bf16 intrinsic lowering test
+// ---------------------------------------------------------------------------
+
+#[test]
+fn test_mma_m16n8k16_f32_bf16_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let f32_ty = pliron::builtin::types::FP32Type::get(&ctx);
+    let i32_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        32,
+        pliron::builtin::types::Signedness::Signless,
+    );
+    let argument_types = (0..4)
+        .map(|_| f32_ty.into())
+        .chain((0..6).map(|_| i32_ty.into()))
+        .collect();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+    let operands = (0..10)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect();
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::MmaM16N8K16F32Bf16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        operands,
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut found = 0;
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for module_op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
+            continue;
+        };
+        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let body = function.get_operation().deref(&ctx).get_region(0);
+        for block in body.deref(&ctx).iter(&ctx) {
+            for body_op in block.deref(&ctx).iter(&ctx) {
+                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                let constraints = asm
+                    .get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                if !template.as_deref().is_some_and(|t| {
+                    t.contains("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32")
+                }) {
+                    continue;
+                }
+                found += 1;
+                let template = template.expect("MMA inline asm must have a template");
+                assert_eq!(
+                    template,
+                    concat!(
+                        "mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 ",
+                        "{$0, $1, $2, $3}, ",
+                        "{$8, $9, $10, $11}, ",
+                        "{$12, $13}, ",
+                        "{$4, $5, $6, $7};"
+                    )
+                );
+                for forbidden in [".reg", "ld.", "st.", "["] {
+                    assert!(
+                        !template.contains(forbidden),
+                        "register-only MMA must not contain {forbidden:?}: {template}"
+                    );
+                }
+                assert_eq!(
+                    constraints.as_deref(),
+                    Some("=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r")
+                );
+                assert_eq!(
+                    llvm::asm_kind_opt(&ctx, &asm),
+                    Some(llvm::AsmKind::Convergent)
+                );
+                assert_eq!(
+                    body_op.deref(&ctx).get_num_operands(),
+                    10,
+                    "expected C, A, and B scalar register operands"
+                );
+                assert_eq!(
+                    body_op.deref(&ctx).get_num_results(),
+                    1,
+                    "LLVM inline asm returns the four D registers as one struct"
+                );
+            }
+        }
+    }
+
+    assert_eq!(found, 1, "expected one mma.sync inline-asm operation");
+    Ok(())
+}
+
+#[test]
+fn test_mma_m16n8k16_f32_f16_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let f32_ty = pliron::builtin::types::FP32Type::get(&ctx);
+    let i32_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        32,
+        pliron::builtin::types::Signedness::Signless,
+    );
+    let argument_types = (0..4)
+        .map(|_| f32_ty.into())
+        .chain((0..6).map(|_| i32_ty.into()))
+        .collect();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+    let operands = (0..10)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect();
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::MmaM16N8K16F32F16Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        operands,
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut found = 0;
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for module_op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
+            continue;
+        };
+        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let body = function.get_operation().deref(&ctx).get_region(0);
+        for block in body.deref(&ctx).iter(&ctx) {
+            for body_op in block.deref(&ctx).iter(&ctx) {
+                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                let constraints = asm
+                    .get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                if !template.as_deref().is_some_and(|t| {
+                    t.contains("mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32")
+                }) {
+                    continue;
+                }
+                found += 1;
+                let template = template.expect("MMA inline asm must have a template");
+                assert_eq!(
+                    template,
+                    concat!(
+                        "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 ",
+                        "{$0, $1, $2, $3}, ",
+                        "{$8, $9, $10, $11}, ",
+                        "{$12, $13}, ",
+                        "{$4, $5, $6, $7};"
+                    )
+                );
+                for forbidden in [".reg", "ld.", "st.", "["] {
+                    assert!(
+                        !template.contains(forbidden),
+                        "register-only MMA must not contain {forbidden:?}: {template}"
+                    );
+                }
+                assert_eq!(
+                    constraints.as_deref(),
+                    Some("=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r")
+                );
+                assert_eq!(
+                    llvm::asm_kind_opt(&ctx, &asm),
+                    Some(llvm::AsmKind::Convergent)
+                );
+                assert_eq!(
+                    body_op.deref(&ctx).get_num_operands(),
+                    10,
+                    "expected C, A, and B scalar register operands"
+                );
+                assert_eq!(
+                    body_op.deref(&ctx).get_num_results(),
+                    1,
+                    "LLVM inline asm returns the four D registers as one struct"
+                );
+            }
+        }
+    }
+
+    assert_eq!(found, 1, "expected one mma.sync inline-asm operation");
+    Ok(())
+}
+
+#[test]
+fn test_mma_m16n8k8_f32_tf32_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let f32_ty = pliron::builtin::types::FP32Type::get(&ctx);
+    let i32_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        32,
+        pliron::builtin::types::Signedness::Signless,
+    );
+    let argument_types = (0..4)
+        .map(|_| f32_ty.into())
+        .chain((0..6).map(|_| i32_ty.into()))
+        .collect();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+    let operands = (0..10)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect();
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::MmaM16N8K8F32Tf32Op::get_concrete_op_info(),
+        vec![f32_ty.into(); 4],
+        operands,
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut found = 0;
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for module_op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
+            continue;
+        };
+        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let body = function.get_operation().deref(&ctx).get_region(0);
+        for block in body.deref(&ctx).iter(&ctx) {
+            for body_op in block.deref(&ctx).iter(&ctx) {
+                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                let constraints = asm
+                    .get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                if !template.as_deref().is_some_and(|t| {
+                    t.contains("mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32")
+                }) {
+                    continue;
+                }
+                found += 1;
+                let template = template.expect("MMA inline asm must have a template");
+                assert_eq!(
+                    template,
+                    concat!(
+                        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 ",
+                        "{$0, $1, $2, $3}, ",
+                        "{$8, $9, $10, $11}, ",
+                        "{$12, $13}, ",
+                        "{$4, $5, $6, $7};"
+                    )
+                );
+                for forbidden in [".reg", "ld.", "st.", "["] {
+                    assert!(
+                        !template.contains(forbidden),
+                        "register-only MMA must not contain {forbidden:?}: {template}"
+                    );
+                }
+                assert_eq!(
+                    constraints.as_deref(),
+                    Some("=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r")
+                );
+                assert_eq!(
+                    llvm::asm_kind_opt(&ctx, &asm),
+                    Some(llvm::AsmKind::Convergent)
+                );
+                assert_eq!(
+                    body_op.deref(&ctx).get_num_operands(),
+                    10,
+                    "expected C, A, and B scalar register operands"
+                );
+                assert_eq!(
+                    body_op.deref(&ctx).get_num_results(),
+                    1,
+                    "LLVM inline asm returns the four D registers as one struct"
+                );
+            }
+        }
+    }
+
+    assert_eq!(found, 1, "expected one mma.sync inline-asm operation");
+    Ok(())
+}
+
+#[test]
+fn test_mma_m8n8k4_f64_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::FP64Type;
+
+    let mut ctx = make_test_ctx();
+    let f64_ty = FP64Type::get(&ctx);
+    let (module_ptr, entry) = build_test_kernel(
+        &mut ctx,
+        vec![f64_ty.into(), f64_ty.into(), f64_ty.into(), f64_ty.into()],
+    );
+    let operands = (0..4)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect();
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::MmaM8N8K4F64Op::get_concrete_op_info(),
+        vec![f64_ty.into(), f64_ty.into()],
+        operands,
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut found = 0;
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for module_op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
+            continue;
+        };
+        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let body = function.get_operation().deref(&ctx).get_region(0);
+        for block in body.deref(&ctx).iter(&ctx) {
+            for body_op in block.deref(&ctx).iter(&ctx) {
+                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                let constraints = asm
+                    .get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                if !template
+                    .as_deref()
+                    .is_some_and(|t| t.contains("mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64"))
+                {
+                    continue;
+                }
+                found += 1;
+                let template = template.unwrap();
+                assert_eq!(
+                    template,
+                    "mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {$0, $1}, {$4}, {$5}, {$2, $3};"
+                );
+                assert!(!template.contains(".reg"));
+                assert!(!template.contains("ld."));
+                assert!(!template.contains("st."));
+                assert_eq!(constraints.as_deref(), Some("=d,=d,d,d,d,d"));
+                assert_eq!(
+                    llvm::asm_kind_opt(&ctx, &asm),
+                    Some(llvm::AsmKind::Convergent)
+                );
+                assert_eq!(
+                    body_op.deref(&ctx).get_num_operands(),
+                    4,
+                    "expected four register inputs (c0, c1, a, b)"
+                );
+                assert_eq!(
+                    body_op.deref(&ctx).get_num_results(),
+                    1,
+                    "LLVM inline asm returns one aggregate containing d0 and d1"
+                );
+            }
+        }
+    }
+
+    assert_eq!(found, 1, "expected one mma.sync inline-asm operation");
+    Ok(())
+}
+
+#[test]
+fn test_mma_m16n8k32_s32_s8_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let i32_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        32,
+        pliron::builtin::types::Signedness::Signless,
+    );
+    let argument_types = (0..10).map(|_| i32_ty.into()).collect();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+    let operands = (0..10)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect();
+
+    let op = Operation::new(
+        &mut ctx,
+        nvvm::MmaM16N8K32S32S8Op::get_concrete_op_info(),
+        vec![i32_ty.into(); 4],
+        operands,
+        vec![],
+        0,
+    );
+    op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut found = 0;
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for module_op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(function) = Operation::get_op::<llvm::FuncOp>(module_op, &ctx) else {
+            continue;
+        };
+        if function.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let body = function.get_operation().deref(&ctx).get_region(0);
+        for block in body.deref(&ctx).iter(&ctx) {
+            for body_op in block.deref(&ctx).iter(&ctx) {
+                let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                let constraints = asm
+                    .get_attr_inline_asm_constraints(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                if !template
+                    .as_deref()
+                    .is_some_and(|t| t.contains("mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32"))
+                {
+                    continue;
+                }
+                found += 1;
+                let template = template.expect("MMA inline asm must have a template");
+                assert_eq!(
+                    template,
+                    concat!(
+                        "mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 ",
+                        "{$0, $1, $2, $3}, ",
+                        "{$8, $9, $10, $11}, ",
+                        "{$12, $13}, ",
+                        "{$4, $5, $6, $7};"
+                    )
+                );
+                for forbidden in [".reg", "ld.", "st.", "["] {
+                    assert!(
+                        !template.contains(forbidden),
+                        "register-only MMA must not contain {forbidden:?}: {template}"
+                    );
+                }
+                assert_eq!(
+                    constraints.as_deref(),
+                    Some("=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r")
+                );
+                assert_eq!(
+                    llvm::asm_kind_opt(&ctx, &asm),
+                    Some(llvm::AsmKind::Convergent)
+                );
+                assert_eq!(
+                    body_op.deref(&ctx).get_num_operands(),
+                    10,
+                    "expected C, A, and B scalar register operands"
+                );
+                assert_eq!(
+                    body_op.deref(&ctx).get_num_results(),
+                    1,
+                    "LLVM inline asm returns the four D registers as one struct"
+                );
+            }
+        }
+    }
+
+    assert_eq!(found, 1, "expected one mma.sync inline-asm operation");
+    Ok(())
+}
diff --git a/crates/mir-lower/tests/lowering_test/sregs_and_warp.rs b/crates/mir-lower/tests/lowering_test/sregs_and_warp.rs
new file mode 100644
index 0000000000..1dafe7271a
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/sregs_and_warp.rs
@@ -0,0 +1,1618 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::ops as mir;
+use dialect_nvvm::ops as nvvm;
+use llvm_export::ops as llvm;
+use pliron::builtin::op_interfaces::{
+    CallOpCallable, CallOpInterface, OneRegionInterface, SymbolOpInterface,
+};
+use pliron::builtin::ops::ModuleOp;
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::location::{Located, Location};
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+use crate::common::{append_return, build_test_kernel, lowered_kernel_body, make_test_ctx};
+
+#[test]
+fn test_standalone_lowering_rejects_builtin_pointer_constant() {
+    use dialect_mir::types::{MirPointerKind, MirPtrType};
+    use pliron::builtin::{
+        attributes::IntegerAttr,
+        ops::ConstantOp,
+        types::{IntegerType, Signedness},
+    };
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let module = ModuleOp::new(&mut ctx, "pointer_constant".try_into().unwrap());
+    let block = module
+        .get_region(&ctx)
+        .deref(&ctx)
+        .iter(&ctx)
+        .next()
+        .unwrap();
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let pointer_ty =
+        MirPtrType::get_generic_with_kind(&mut ctx, u32_ty.into(), true, MirPointerKind::UniqueRef);
+    let value = APInt::from_u64(0, NonZeroUsize::new(32).unwrap());
+    let constant = ConstantOp::new(&mut ctx, IntegerAttr::new(u32_ty, value).into());
+    let result = constant.get_operation().deref(&ctx).get_result(0);
+    result.set_type(&ctx, pointer_ty.into());
+    constant.get_operation().insert_at_back(block, &ctx);
+
+    let error = mir_lower::lower_mir_to_llvm(&mut ctx, module.get_operation()).unwrap_err();
+    assert!(
+        error
+            .to_string()
+            .contains("builtin.constant cannot produce a MIR pointer carrier")
+    );
+}
+
+#[test]
+fn test_intrinsic_insertion() -> Result<(), anyhow::Error> {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    // Create Module
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_ptr = module.get_operation();
+
+    // Create MirFunc
+    let func_name = "kernel_func";
+    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, vec![], vec![]);
+
+    // Manual construction of MirFuncOp
+    let func_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1, // 1 region
+    );
+    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
+    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
+    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
+
+    // Add body - MirFuncOp has 1 region
+    let region = func.get_operation().deref(&ctx).get_region(0);
+
+    // Create block if empty (it is empty by default from Operation::new)
+    let block = {
+        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, vec![]);
+        b.insert_at_back(region, &ctx);
+        b
+    };
+
+    // Add ReadPtxSregTidXOp
+    let int32_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        32,
+        pliron::builtin::types::Signedness::Signless,
+    );
+
+    let tid_op_ptr = Operation::new(
+        &mut ctx,
+        nvvm::ReadPtxSregTidXOp::get_concrete_op_info(),
+        vec![int32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    let tid_op = nvvm::ReadPtxSregTidXOp::new(tid_op_ptr);
+    let expected_location = Location::Named {
+        name: "source-tid-x".to_string(),
+        child_loc: Box::new(Location::Unknown),
+    };
+    tid_op
+        .get_operation()
+        .deref_mut(&ctx)
+        .set_loc(expected_location.clone());
+    tid_op.get_operation().insert_at_back(block, &ctx);
+
+    // Add Return
+    let ret_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirReturnOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    let ret_op = mir::MirReturnOp::new(ret_op_ptr);
+    ret_op.get_operation().insert_at_back(block, &ctx);
+
+    // Add Func to Module
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    // Run DialectConversion-based lowering
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    // Verify result
+    let mut found_intrinsic = false;
+    let mut found_intrinsic_call = false;
+    let mut found_kernel = false;
+
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+
+    for op in block.deref(&ctx).iter(&ctx) {
+        if let Some(func_op) = Operation::get_op::<llvm_export::ops::FuncOp>(op, &ctx) {
+            let name = func_op.get_symbol_name(&ctx).to_string();
+            if name == "llvm_nvvm_read_ptx_sreg_tid_x" {
+                found_intrinsic = true;
+                // Intrinsic (declaration) should have 0 regions or empty region
+                let num_regions = func_op.get_operation().deref(&ctx).regions().count();
+                if num_regions > 0 {
+                    assert!(
+                        func_op
+                            .get_operation()
+                            .deref(&ctx)
+                            .get_region(0)
+                            .deref(&ctx)
+                            .iter(&ctx)
+                            .next()
+                            .is_none()
+                    );
+                }
+            } else if name == "kernel_func" {
+                found_kernel = true;
+                // Kernel should have body (1 region, not empty)
+                assert!(func_op.get_operation().deref(&ctx).regions().count() > 0);
+                assert!(
+                    func_op
+                        .get_operation()
+                        .deref(&ctx)
+                        .get_region(0)
+                        .deref(&ctx)
+                        .iter(&ctx)
+                        .next()
+                        .is_some()
+                );
+                let kernel_region = func_op.get_operation().deref(&ctx).get_region(0);
+                for kernel_block in kernel_region.deref(&ctx).iter(&ctx) {
+                    for body_op in kernel_block.deref(&ctx).iter(&ctx) {
+                        let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx) else {
+                            continue;
+                        };
+                        if matches!(
+                            call.callee(&ctx),
+                            CallOpCallable::Direct(symbol)
+                                if symbol.to_string() == "llvm_nvvm_read_ptx_sreg_tid_x"
+                        ) {
+                            found_intrinsic_call = true;
+                            assert_eq!(call.get_operation().deref(&ctx).loc(), expected_location);
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    assert!(found_intrinsic, "Intrinsic function declaration not found");
+    assert!(found_intrinsic_call, "Intrinsic call not found in kernel");
+    assert!(found_kernel, "Kernel function not found");
+
+    Ok(())
+}
+
+#[test]
+fn test_assertfail_orphaned_successor_block_is_removed() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_ptr = module.get_operation();
+
+    let func_name = "kernel_func";
+    let u8_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        8,
+        pliron::builtin::types::Signedness::Unsigned,
+    );
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
+    let u32_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        32,
+        pliron::builtin::types::Signedness::Unsigned,
+    );
+    let u64_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        64,
+        pliron::builtin::types::Signedness::Unsigned,
+    );
+    let arg_tys: Vec<pliron::r#type::TypeHandle> = vec![
+        ptr_ty.into(),
+        ptr_ty.into(),
+        u32_ty.into(),
+        ptr_ty.into(),
+        u64_ty.into(),
+    ];
+    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, arg_tys.clone(), vec![]);
+
+    let func_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
+    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
+    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
+
+    let region = func.get_operation().deref(&ctx).get_region(0);
+    let entry = {
+        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, arg_tys);
+        b.insert_at_back(region, &ctx);
+        b
+    };
+    // A block reachable only through the assert's success edge, carrying a
+    // block argument: the CFG a constant-false `gpu_assert!` leaves behind
+    // after MIR optimization folds the direct edge away.
+    let tail = {
+        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, vec![u32_ty.into()]);
+        b.insert_at_back(region, &ctx);
+        b
+    };
+
+    let message = entry.deref(&ctx).get_argument(0);
+    let file = entry.deref(&ctx).get_argument(1);
+    let line = entry.deref(&ctx).get_argument(2);
+    let function = entry.deref(&ctx).get_argument(3);
+    let char_size = entry.deref(&ctx).get_argument(4);
+
+    let assertfail_op =
+        nvvm::AssertFailOp::build(&mut ctx, message, file, line, function, char_size);
+    assertfail_op.insert_at_back(entry, &ctx);
+
+    // The success edge forwards `line` into the tail block's argument.
+    // Lowering erases this branch (the call never returns), orphaning the
+    // tail block, which then cannot be exported: a block argument needs one
+    // PHI incoming value per predecessor and there are none left.
+    let goto_op = Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![line],
+        vec![tail],
+        0,
+    );
+    goto_op.insert_at_back(entry, &ctx);
+
+    let ret_op = Operation::new(
+        &mut ctx,
+        mir::MirReturnOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    ret_op.insert_at_back(tail, &ctx);
+
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut found_kernel = false;
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != func_name {
+            continue;
+        }
+        found_kernel = true;
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        let blocks: Vec<_> = func_region.deref(&ctx).iter(&ctx).collect();
+        for block in blocks.iter().skip(1) {
+            assert!(
+                !block.preds(&ctx).is_empty(),
+                "an unreachable block survived lowering; with block arguments \
+                 it cannot be exported (a PHI needs an incoming value per \
+                 predecessor and there are none)"
+            );
+        }
+    }
+    assert!(found_kernel, "Kernel function not found");
+
+    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+    let ir =
+        llvm_export::export::export_module_to_string(&ctx, &module).map_err(anyhow::Error::msg)?;
+    let lines: Vec<_> = ir.lines().collect();
+    let call_line = lines
+        .iter()
+        .position(|line| line.contains("call void @__assertfail("))
+        .expect("expected exported __assertfail call");
+    assert_eq!(lines[call_line + 1].trim(), "unreachable", "{ir}");
+
+    Ok(())
+}
+
+#[test]
+fn test_globaltimer_lowers_to_intrinsic_call() -> Result<(), anyhow::Error> {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_ptr = module.get_operation();
+
+    let func_name = "kernel_func";
+    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, vec![], vec![]);
+
+    let func_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
+    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
+    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
+
+    let region = func.get_operation().deref(&ctx).get_region(0);
+    let block = {
+        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, vec![]);
+        b.insert_at_back(region, &ctx);
+        b
+    };
+
+    let i64_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        64,
+        pliron::builtin::types::Signedness::Signless,
+    );
+    let timer_op = Operation::new(
+        &mut ctx,
+        nvvm::ReadPtxSregGlobaltimerOp::get_concrete_op_info(),
+        vec![i64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    timer_op.insert_at_back(block, &ctx);
+
+    let ret_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirReturnOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    let ret_op = mir::MirReturnOp::new(ret_op_ptr);
+    ret_op.get_operation().insert_at_back(block, &ctx);
+
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    const INTRINSIC: &str = "llvm_nvvm_read_ptx_sreg_globaltimer";
+
+    let mut found_decl = false;
+    let mut found_call = false;
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm_export::ops::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        let name = func_op.get_symbol_name(&ctx).to_string();
+
+        if name == INTRINSIC {
+            // Intrinsic declaration: present with empty body.
+            found_decl = true;
+            let num_regions = func_op.get_operation().deref(&ctx).regions().count();
+            if num_regions > 0 {
+                assert!(
+                    func_op
+                        .get_operation()
+                        .deref(&ctx)
+                        .get_region(0)
+                        .deref(&ctx)
+                        .iter(&ctx)
+                        .next()
+                        .is_none(),
+                    "intrinsic declaration must have empty body"
+                );
+            }
+        } else if name == func_name {
+            let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+            for func_block in func_region.deref(&ctx).iter(&ctx) {
+                for body_op in func_block.deref(&ctx).iter(&ctx) {
+                    if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
+                        && let CallOpCallable::Direct(sym) = call.callee(&ctx)
+                        && sym.to_string() == INTRINSIC
+                    {
+                        found_call = true;
+                    }
+                    assert!(
+                        Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx).is_none(),
+                        "globaltimer must not lower to inline asm"
+                    );
+                }
+            }
+        }
+    }
+
+    assert!(
+        found_decl,
+        "Expected `{INTRINSIC}` declaration in lowered module"
+    );
+    assert!(
+        found_call,
+        "Expected call to `{INTRINSIC}` in lowered kernel body"
+    );
+    Ok(())
+}
+
+#[test]
+fn test_assertfail_lowers_to_noreturn_call_and_unreachable() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_ptr = module.get_operation();
+
+    let func_name = "kernel_func";
+    let u8_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        8,
+        pliron::builtin::types::Signedness::Unsigned,
+    );
+    let ptr_ty = MirPtrType::get_generic(&mut ctx, u8_ty.into(), false);
+    let u32_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        32,
+        pliron::builtin::types::Signedness::Unsigned,
+    );
+    let u64_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        64,
+        pliron::builtin::types::Signedness::Unsigned,
+    );
+    let arg_tys: Vec<pliron::r#type::TypeHandle> = vec![
+        ptr_ty.into(),
+        ptr_ty.into(),
+        u32_ty.into(),
+        ptr_ty.into(),
+        u64_ty.into(),
+    ];
+    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, arg_tys.clone(), vec![]);
+
+    let func_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
+    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
+    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
+
+    let region = func.get_operation().deref(&ctx).get_region(0);
+    let block = {
+        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, arg_tys);
+        b.insert_at_back(region, &ctx);
+        b
+    };
+
+    let message = block.deref(&ctx).get_argument(0);
+    let file = block.deref(&ctx).get_argument(1);
+    let line = block.deref(&ctx).get_argument(2);
+    let function = block.deref(&ctx).get_argument(3);
+    let char_size = block.deref(&ctx).get_argument(4);
+
+    let assertfail_op =
+        nvvm::AssertFailOp::build(&mut ctx, message, file, line, function, char_size);
+    assertfail_op.insert_at_back(block, &ctx);
+
+    // This return must be removed by lowering because __assertfail never returns.
+    let ret_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirReturnOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    ret_op_ptr.insert_at_back(block, &ctx);
+
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    const EXTERN: &str = "__assertfail";
+
+    let mut found_decl = false;
+    let mut found_call = false;
+    let mut found_unreachable = false;
+
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        let name = func_op.get_symbol_name(&ctx).to_string();
+
+        if name == EXTERN {
+            found_decl = true;
+            assert!(
+                llvm::op_noreturn(&ctx, func_op.get_operation()),
+                "__assertfail declaration must be marked noreturn"
+            );
+            continue;
+        }
+
+        if name != func_name {
+            continue;
+        }
+
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            let body_ops: Vec<_> = func_block.deref(&ctx).iter(&ctx).collect();
+
+            for (index, body_op) in body_ops.iter().copied().enumerate() {
+                if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
+                    && let CallOpCallable::Direct(sym) = call.callee(&ctx)
+                    && sym.to_string() == EXTERN
+                {
+                    found_call = true;
+
+                    assert!(
+                        llvm::op_noreturn(&ctx, body_op),
+                        "__assertfail call must be marked noreturn"
+                    );
+                    assert_eq!(
+                        body_op.deref(&ctx).get_num_operands(),
+                        5,
+                        "__assertfail call must forward all five operands"
+                    );
+                    assert!(
+                        body_ops.get(index + 1).is_some_and(|next| {
+                            Operation::get_op::<llvm::UnreachableOp>(*next, &ctx).is_some()
+                        }),
+                        "llvm.unreachable must immediately follow __assertfail"
+                    );
+                    assert_eq!(
+                        index + 2,
+                        body_ops.len(),
+                        "no operations may remain after llvm.unreachable"
+                    );
+                }
+
+                if Operation::get_op::<llvm::UnreachableOp>(body_op, &ctx).is_some() {
+                    found_unreachable = true;
+                }
+
+                assert!(
+                    Operation::get_op::<nvvm::AssertFailOp>(body_op, &ctx).is_none(),
+                    "nvvm.assertfail must be fully consumed by the lowering"
+                );
+            }
+        }
+    }
+
+    assert!(
+        found_decl,
+        "Expected `{EXTERN}` declaration in lowered module"
+    );
+    assert!(
+        found_call,
+        "Expected call to `{EXTERN}` in lowered kernel body"
+    );
+    assert!(
+        found_unreachable,
+        "__assertfail must terminate the block with llvm.unreachable"
+    );
+
+    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+    let ir =
+        llvm_export::export::export_module_to_string(&ctx, &module).map_err(anyhow::Error::msg)?;
+
+    let declaration = ir
+        .lines()
+        .find(|line| line.contains("declare void @__assertfail("))
+        .expect("expected exported __assertfail declaration");
+    assert!(declaration.contains("noreturn"), "{ir}");
+
+    let lines: Vec<_> = ir.lines().collect();
+    let call_line = lines
+        .iter()
+        .position(|line| line.contains("call void @__assertfail("))
+        .expect("expected exported __assertfail call");
+    assert!(lines[call_line].contains("noreturn"), "{ir}");
+    assert_eq!(lines[call_line + 1].trim(), "unreachable", "{ir}");
+
+    Ok(())
+}
+
+/// Lower a single zero-operand, i32-result special-register op and assert it
+/// emits a declaration of and direct call to `intrinsic` (and no inline asm).
+fn assert_sreg_i32_lowers_to_intrinsic(
+    op_info: (
+        fn(pliron::context::Ptr<pliron::operation::Operation>) -> pliron::op::OpObj,
+        std::any::TypeId,
+    ),
+    intrinsic: &str,
+) -> Result<(), anyhow::Error> {
+    let mut ctx = Context::new();
+    dialect_mir::register(&mut ctx);
+    dialect_nvvm::register(&mut ctx);
+    mir_lower::register(&mut ctx);
+
+    let module = ModuleOp::new(&mut ctx, "test_module".try_into().unwrap());
+    let module_ptr = module.get_operation();
+
+    let func_name = "kernel_func";
+    let func_ty = pliron::builtin::types::FunctionType::get(&ctx, vec![], vec![]);
+
+    let func_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirFuncOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        1,
+    );
+    let func_ty_attr = pliron::builtin::attributes::TypeAttr::new(func_ty.into());
+    let func = mir::MirFuncOp::new(&mut ctx, func_op_ptr, func_ty_attr);
+    func.set_symbol_name(&mut ctx, func_name.try_into().unwrap());
+
+    let region = func.get_operation().deref(&ctx).get_region(0);
+    let block = {
+        let b = pliron::basic_block::BasicBlock::new(&mut ctx, None, vec![]);
+        b.insert_at_back(region, &ctx);
+        b
+    };
+
+    let i32_ty = pliron::builtin::types::IntegerType::get(
+        &ctx,
+        32,
+        pliron::builtin::types::Signedness::Signless,
+    );
+    let sreg_op = Operation::new(&mut ctx, op_info, vec![i32_ty.into()], vec![], vec![], 0);
+    sreg_op.insert_at_back(block, &ctx);
+
+    let ret_op_ptr = Operation::new(
+        &mut ctx,
+        mir::MirReturnOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![],
+        0,
+    );
+    let ret_op = mir::MirReturnOp::new(ret_op_ptr);
+    ret_op.get_operation().insert_at_back(block, &ctx);
+
+    let module_region = module.get_operation().deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    func.get_operation().insert_at_back(module_block, &ctx);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    let mut found_decl = false;
+    let mut found_call = false;
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm_export::ops::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        let name = func_op.get_symbol_name(&ctx).to_string();
+
+        if name == intrinsic {
+            found_decl = true;
+        } else if name == func_name {
+            let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+            for func_block in func_region.deref(&ctx).iter(&ctx) {
+                for body_op in func_block.deref(&ctx).iter(&ctx) {
+                    if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
+                        && let CallOpCallable::Direct(sym) = call.callee(&ctx)
+                        && sym.to_string() == intrinsic
+                    {
+                        found_call = true;
+                    }
+                    assert!(
+                        Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx).is_none(),
+                        "{intrinsic} must not lower to inline asm"
+                    );
+                }
+            }
+        }
+    }
+
+    assert!(
+        found_decl,
+        "Expected `{intrinsic}` declaration in lowered module"
+    );
+    assert!(
+        found_call,
+        "Expected call to `{intrinsic}` in lowered kernel body"
+    );
+    Ok(())
+}
+
+fn assert_sreg_lowers_to_inline_asm(
+    op_info: (
+        fn(pliron::context::Ptr<Operation>) -> pliron::op::OpObj,
+        std::any::TypeId,
+    ),
+    result_width: u32,
+    expected_template: &str,
+    expected_constraints: &str,
+    expected_kind: llvm::AsmKind,
+) -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let result_ty = IntegerType::get(&ctx, result_width, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
+    let sreg_op = Operation::new(&mut ctx, op_info, vec![result_ty.into()], vec![], vec![], 0);
+    sreg_op.insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut matches = 0usize;
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = inline_asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                if template.as_deref() != Some(expected_template) {
+                    continue;
+                }
+
+                matches += 1;
+                assert_eq!(
+                    inline_asm
+                        .get_attr_inline_asm_constraints(&ctx)
+                        .map(|value| String::from((*value).clone()))
+                        .as_deref(),
+                    Some(expected_constraints)
+                );
+                assert_eq!(llvm::asm_kind(&ctx, &inline_asm), expected_kind);
+            }
+        }
+    }
+
+    assert_eq!(matches, 1, "expected one exact `{expected_template}` read");
+    Ok(())
+}
+
+#[test]
+fn test_lanemask_ops_lower_to_sreg_intrinsic_calls() -> Result<(), anyhow::Error> {
+    // Each lane-position mask op lowers to its matching read-only sreg intrinsic
+    // (underscores become dots on export: `..._lanemask_lt` -> `...lanemask.lt`).
+    assert_sreg_i32_lowers_to_intrinsic(
+        nvvm::ReadPtxSregLanemaskLtOp::get_concrete_op_info(),
+        "llvm_nvvm_read_ptx_sreg_lanemask_lt",
+    )?;
+    assert_sreg_i32_lowers_to_intrinsic(
+        nvvm::ReadPtxSregLanemaskLeOp::get_concrete_op_info(),
+        "llvm_nvvm_read_ptx_sreg_lanemask_le",
+    )?;
+    assert_sreg_i32_lowers_to_intrinsic(
+        nvvm::ReadPtxSregLanemaskEqOp::get_concrete_op_info(),
+        "llvm_nvvm_read_ptx_sreg_lanemask_eq",
+    )?;
+    assert_sreg_i32_lowers_to_intrinsic(
+        nvvm::ReadPtxSregLanemaskGeOp::get_concrete_op_info(),
+        "llvm_nvvm_read_ptx_sreg_lanemask_ge",
+    )?;
+    assert_sreg_i32_lowers_to_intrinsic(
+        nvvm::ReadPtxSregLanemaskGtOp::get_concrete_op_info(),
+        "llvm_nvvm_read_ptx_sreg_lanemask_gt",
+    )?;
+    Ok(())
+}
+
+#[test]
+fn test_generated_vote_sync_family_lowers_to_exact_typed_intrinsics() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::r#type::Typed;
+
+    let mut ctx = make_test_ctx();
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into(), i1_ty.into()]);
+    let mask = entry.deref(&ctx).get_argument(0);
+    let predicate = entry.deref(&ctx).get_argument(1);
+
+    for vote in [
+        nvvm::VoteSyncAllOp::build(&mut ctx, mask, predicate),
+        nvvm::VoteSyncAnyOp::build(&mut ctx, mask, predicate),
+        nvvm::VoteSyncBallotOp::build(&mut ctx, mask, predicate),
+        nvvm::VoteSyncUniOp::build(&mut ctx, mask, predicate),
+    ] {
+        vote.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let expected = [
+        ("llvm_nvvm_vote_all_sync", 1),
+        ("llvm_nvvm_vote_any_sync", 1),
+        ("llvm_nvvm_vote_ballot_sync", 32),
+        ("llvm_nvvm_vote_uni_sync", 1),
+    ];
+    let mut found = Vec::new();
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        assert!(
+            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+            "generated vote.sync operations must use typed LLVM intrinsics"
+        );
+        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+            continue;
+        };
+        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+            continue;
+        };
+        let callee = callee.to_string();
+        let Some((_, result_width)) = expected.iter().find(|(name, _)| *name == callee) else {
+            continue;
+        };
+
+        let call = call.get_operation().deref(&ctx);
+        assert_eq!(call.get_num_operands(), 2);
+        assert_eq!(call.get_num_results(), 1);
+
+        let integer_shape = |value: pliron::value::Value| {
+            let ty = value.get_type(&ctx);
+            let ty = ty.deref(&ctx);
+            let integer = ty
+                .downcast_ref::<IntegerType>()
+                .expect("vote.sync operands and results are integers");
+            (integer.width(), integer.signedness())
+        };
+        assert_eq!(
+            [
+                integer_shape(call.get_operand(0)),
+                integer_shape(call.get_operand(1)),
+            ],
+            [(32, Signedness::Signless), (1, Signedness::Signless),],
+            "{callee} must preserve [mask, predicate] operand order"
+        );
+        assert_eq!(
+            integer_shape(call.get_result(0)),
+            (*result_width, Signedness::Signless),
+            "{callee} returned the wrong LLVM integer type"
+        );
+        found.push((callee, *result_width));
+    }
+
+    found.sort();
+    let mut expected = expected
+        .map(|(name, width)| (name.to_owned(), width))
+        .to_vec();
+    expected.sort();
+    assert_eq!(found, expected);
+    Ok(())
+}
+
+fn lower_generated_active_mask(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
+    nvvm::ActiveMaskOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+#[test]
+fn test_generated_active_mask_llvm_nvptx_uses_typed_intrinsic() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::IntegerType;
+    use pliron::r#type::Typed;
+
+    let (ctx, module_ptr) = lower_generated_active_mask(mir_lower::IntrinsicBackend::LlvmNvptx)?;
+    let mut found = 0;
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        assert!(
+            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+            "LLVM-NVPTX active_mask must use the typed intrinsic"
+        );
+        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+            continue;
+        };
+        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+            continue;
+        };
+        if callee.to_string() != "llvm_nvvm_activemask" {
+            continue;
+        }
+
+        found += 1;
+        let call = op.deref(&ctx);
+        assert_eq!(call.get_num_operands(), 0);
+        assert_eq!(call.get_num_results(), 1);
+        let result_ty = call.get_result(0).get_type(&ctx);
+        let result_ty = result_ty.deref(&ctx);
+        let result_ty = result_ty
+            .downcast_ref::<IntegerType>()
+            .expect("active_mask returns an integer");
+        assert_eq!(result_ty.width(), 32);
+    }
+    assert_eq!(found, 1, "expected one typed active_mask call");
+
+    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+        .map_err(|error| anyhow::anyhow!(error))?;
+    assert!(ir.contains("call i32 @llvm.nvvm.activemask()"), "{ir}");
+    Ok(())
+}
+
+#[test]
+fn test_generated_active_mask_libnvvm_uses_convergent_sideeffect_asm() -> Result<(), anyhow::Error>
+{
+    use pliron::builtin::types::IntegerType;
+    use pliron::r#type::Typed;
+
+    let (ctx, module_ptr) = lower_generated_active_mask(mir_lower::IntrinsicBackend::LibNvvm)?;
+    let mut found = 0;
+    for op in lowered_kernel_body(&ctx, module_ptr) {
+        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx)
+            && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+        {
+            assert_ne!(callee.to_string(), "llvm_nvvm_activemask");
+        }
+        let Some(asm) = Operation::get_op::<llvm::InlineAsmOp>(op, &ctx) else {
+            continue;
+        };
+
+        found += 1;
+        assert_eq!(
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some("activemask.b32 $0;")
+        );
+        assert_eq!(
+            asm.get_attr_inline_asm_constraints(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .as_deref(),
+            Some("=r,~{memory}")
+        );
+        assert_eq!(llvm::asm_kind(&ctx, &asm), llvm::AsmKind::Convergent);
+        assert!(
+            asm.get_attr_inline_asm_convergent(&ctx)
+                .is_some_and(|value| bool::from((*value).clone()))
+        );
+        let asm = op.deref(&ctx);
+        assert_eq!(asm.get_num_operands(), 0);
+        assert_eq!(asm.get_num_results(), 1);
+        let result_ty = asm.get_result(0).get_type(&ctx);
+        let result_ty = result_ty.deref(&ctx);
+        let result_ty = result_ty
+            .downcast_ref::<IntegerType>()
+            .expect("active_mask inline asm returns an integer");
+        assert_eq!(result_ty.width(), 32);
+    }
+    assert_eq!(found, 1, "expected one exact active_mask asm block");
+
+    let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+    let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+        .map_err(|error| anyhow::anyhow!(error))?;
+    assert!(
+        ir.contains("call i32 asm sideeffect \"activemask.b32 $0;\", \"=r,~{memory}\"()"),
+        "{ir}"
+    );
+    assert!(ir.contains("attributes #0 = { convergent }"), "{ir}");
+    Ok(())
+}
+
+#[test]
+fn test_generated_warp_match_family_uses_exact_typed_calls_and_mask_projection()
+-> Result<(), anyhow::Error> {
+    use llvm_export::types::StructType;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::r#type::Typed;
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![i32_ty.into(), i32_ty.into(), i64_ty.into()]);
+    let mask = entry.deref(&ctx).get_argument(0);
+    let value32 = entry.deref(&ctx).get_argument(1);
+    let value64 = entry.deref(&ctx).get_argument(2);
+    for warp_match in [
+        nvvm::MatchAnySyncI32Op::build(&mut ctx, mask, value32),
+        nvvm::MatchAnySyncI64Op::build(&mut ctx, mask, value64),
+        nvvm::MatchAllSyncI32Op::build(&mut ctx, mask, value32),
+        nvvm::MatchAllSyncI64Op::build(&mut ctx, mask, value64),
+    ] {
+        warp_match.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: mir_lower::IntrinsicBackend::LlvmNvptx,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let expected = [
+        ("llvm_nvvm_match_any_sync_i32", 32, false),
+        ("llvm_nvvm_match_any_sync_i64", 64, false),
+        ("llvm_nvvm_match_all_sync_i32p", 32, true),
+        ("llvm_nvvm_match_all_sync_i64p", 64, true),
+    ];
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let integer_width = |value: pliron::value::Value| {
+        let ty = value.get_type(&ctx);
+        let ty = ty.deref(&ctx);
+        ty.downcast_ref::<IntegerType>()
+            .expect("warp-match value is an integer")
+            .width()
+    };
+    let mut found = Vec::new();
+    let mut aggregate_results = Vec::new();
+    for &op in &body {
+        assert!(
+            Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+            "warp match must use typed LLVM intrinsics"
+        );
+        let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+            continue;
+        };
+        let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+            continue;
+        };
+        let callee = callee.to_string();
+        let Some((_, value_width, aggregate)) =
+            expected.iter().find(|(name, _, _)| *name == callee)
+        else {
+            continue;
+        };
+
+        let call = op.deref(&ctx);
+        assert_eq!(call.get_num_operands(), 2);
+        assert_eq!(
+            [
+                integer_width(call.get_operand(0)),
+                integer_width(call.get_operand(1)),
+            ],
+            [32, *value_width],
+            "{callee} has the wrong typed signature"
+        );
+        assert_eq!(call.get_num_results(), 1);
+        let result = call.get_result(0);
+        if *aggregate {
+            let result_ty = result.get_type(&ctx);
+            let result_ty = result_ty.deref(&ctx);
+            let result_ty = result_ty
+                .downcast_ref::<StructType>()
+                .expect("match.all returns an LLVM aggregate");
+            assert_eq!(result_ty.num_fields(), 2);
+            let field_widths = (0..2)
+                .map(|index| {
+                    let field = result_ty.field_type(index);
+                    let field = field.deref(&ctx);
+                    field
+                        .downcast_ref::<IntegerType>()
+                        .expect("match.all aggregate fields are integers")
+                        .width()
+                })
+                .collect::<Vec<_>>();
+            assert_eq!(field_widths, [32, 1]);
+            aggregate_results.push((callee.clone(), result));
+        } else {
+            assert_eq!(integer_width(result), 32);
+        }
+        found.push(callee);
+    }
+
+    found.sort();
+    let mut expected_calls = expected.map(|(name, _, _)| name.to_owned());
+    expected_calls.sort();
+    assert_eq!(found, expected_calls);
+
+    let mut projected = Vec::new();
+    for &op in &body {
+        let Some(extract) = Operation::get_op::<llvm::ExtractValueOp>(op, &ctx) else {
+            continue;
+        };
+        assert_eq!(extract.indices(&ctx), vec![0]);
+        let extract = op.deref(&ctx);
+        assert_eq!(extract.get_num_operands(), 1);
+        assert_eq!(extract.get_num_results(), 1);
+        assert_eq!(integer_width(extract.get_result(0)), 32);
+        let aggregate = extract.get_operand(0);
+        let callee = aggregate_results
+            .iter()
+            .find_map(|(callee, result)| (*result == aggregate).then(|| callee.clone()))
+            .expect("match.all must extract from its aggregate call result");
+        projected.push(callee);
+    }
+    projected.sort();
+    assert_eq!(
+        projected,
+        [
+            "llvm_nvvm_match_all_sync_i32p".to_owned(),
+            "llvm_nvvm_match_all_sync_i64p".to_owned(),
+        ]
+    );
+    Ok(())
+}
+
+#[test]
+fn test_warpid_ops_preserve_snapshot_semantics() -> Result<(), anyhow::Error> {
+    assert_sreg_lowers_to_inline_asm(
+        nvvm::ReadPtxSregWarpIdOp::get_concrete_op_info(),
+        32,
+        "mov.u32 $0, %warpid;",
+        "=r",
+        llvm::AsmKind::SideEffect,
+    )?;
+    assert_sreg_i32_lowers_to_intrinsic(
+        nvvm::ReadPtxSregNwarpIdOp::get_concrete_op_info(),
+        "llvm_nvvm_read_ptx_sreg_nwarpid",
+    )?;
+    Ok(())
+}
+
+#[test]
+fn test_smid_ops_preserve_snapshot_semantics() -> Result<(), anyhow::Error> {
+    assert_sreg_lowers_to_inline_asm(
+        nvvm::ReadPtxSregSmIdOp::get_concrete_op_info(),
+        32,
+        "mov.u32 $0, %smid;",
+        "=r",
+        llvm::AsmKind::SideEffect,
+    )?;
+    assert_sreg_i32_lowers_to_intrinsic(
+        nvvm::ReadPtxSregNsmIdOp::get_concrete_op_info(),
+        "llvm_nvvm_read_ptx_sreg_nsmid",
+    )?;
+    Ok(())
+}
+
+#[test]
+fn test_repeated_location_samples_remain_side_effecting_reads() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
+
+    for op_info in [
+        nvvm::ReadPtxSregWarpIdOp::get_concrete_op_info(),
+        nvvm::ReadPtxSregSmIdOp::get_concrete_op_info(),
+        nvvm::ReadPtxSregWarpIdOp::get_concrete_op_info(),
+        nvvm::ReadPtxSregSmIdOp::get_concrete_op_info(),
+    ] {
+        let op = Operation::new(&mut ctx, op_info, vec![i32_ty.into()], vec![], vec![], 0);
+        op.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let mut warpid_reads = 0usize;
+    let mut smid_reads = 0usize;
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in module_block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                let template = inline_asm
+                    .get_attr_inline_asm_template(&ctx)
+                    .map(|value| String::from((*value).clone()));
+                match template.as_deref() {
+                    Some("mov.u32 $0, %warpid;") => warpid_reads += 1,
+                    Some("mov.u32 $0, %smid;") => smid_reads += 1,
+                    _ => continue,
+                }
+                assert_eq!(
+                    llvm::asm_kind(&ctx, &inline_asm),
+                    llvm::AsmKind::SideEffect,
+                    "location snapshots must survive LLVM CSE"
+                );
+            }
+        }
+    }
+
+    assert_eq!(warpid_reads, 2);
+    assert_eq!(smid_reads, 2);
+    Ok(())
+}
+
+#[test]
+fn test_gridid_op_lowers_to_full_width_inline_ptx() -> Result<(), anyhow::Error> {
+    assert_sreg_lowers_to_inline_asm(
+        nvvm::ReadPtxSregGridIdOp::get_concrete_op_info(),
+        64,
+        "mov.u64 $0, %gridid;",
+        "=l",
+        llvm::AsmKind::Pure,
+    )
+}
+
+#[test]
+fn test_smem_size_ops_lower_to_portable_inline_ptx() -> Result<(), anyhow::Error> {
+    assert_sreg_lowers_to_inline_asm(
+        nvvm::ReadPtxSregDynamicSmemSizeOp::get_concrete_op_info(),
+        32,
+        "mov.u32 $0, %dynamic_smem_size;",
+        "=r",
+        llvm::AsmKind::Pure,
+    )?;
+    assert_sreg_lowers_to_inline_asm(
+        nvvm::ReadPtxSregTotalSmemSizeOp::get_concrete_op_info(),
+        32,
+        "mov.u32 $0, %total_smem_size;",
+        "=r",
+        llvm::AsmKind::Pure,
+    )?;
+    Ok(())
+}
+
+#[test]
+fn generated_threadfences_use_typed_intrinsics_on_both_backends() -> Result<(), anyhow::Error> {
+    const EXPECTED: [&str; 3] = [
+        "llvm_nvvm_membar_cta",
+        "llvm_nvvm_membar_gl",
+        "llvm_nvvm_membar_sys",
+    ];
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        let mut ctx = make_test_ctx();
+        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![]);
+        for op_info in [
+            nvvm::ThreadfenceBlockOp::get_concrete_op_info(),
+            nvvm::ThreadfenceOp::get_concrete_op_info(),
+            nvvm::ThreadfenceSystemOp::get_concrete_op_info(),
+        ] {
+            Operation::new(&mut ctx, op_info, vec![], vec![], vec![], 0)
+                .insert_at_back(entry, &ctx);
+        }
+        append_return(&mut ctx, entry);
+
+        mir_lower::lower_mir_to_llvm_with_options(
+            &mut ctx,
+            module_ptr,
+            mir_lower::LoweringOptions {
+                intrinsic_backend: backend,
+                ..Default::default()
+            },
+        )
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+        let mut found = Vec::new();
+        for op in lowered_kernel_body(&ctx, module_ptr) {
+            assert!(
+                Operation::get_op::<llvm::InlineAsmOp>(op, &ctx).is_none(),
+                "threadfences must use their reviewed typed route"
+            );
+            let Some(call) = Operation::get_op::<llvm::CallOp>(op, &ctx) else {
+                continue;
+            };
+            let CallOpCallable::Direct(callee) = call.callee(&ctx) else {
+                continue;
+            };
+            let callee = callee.to_string();
+            if EXPECTED.contains(&callee.as_str()) {
+                assert_eq!(op.deref(&ctx).get_num_operands(), 0);
+                found.push(callee);
+            }
+        }
+        found.sort();
+        assert_eq!(found, EXPECTED);
+
+        let module = Operation::get_op::<ModuleOp>(module_ptr, &ctx).unwrap();
+        let ir = llvm_export::export::export_module_to_string(&ctx, &module)
+            .map_err(|error| anyhow::anyhow!(error))?;
+        for symbol in [
+            "llvm.nvvm.membar.cta",
+            "llvm.nvvm.membar.gl",
+            "llvm.nvvm.membar.sys",
+        ] {
+            assert!(ir.contains(&format!("call void @{symbol}()")), "{ir}");
+        }
+    }
+    Ok(())
+}
+
+/// LLVM uses its typed intrinsic. libNVVM uses the reviewed inline-PTX fallback.
+#[test]
+fn generated_elect_sync_uses_the_selected_backend_route() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    for backend in [
+        mir_lower::IntrinsicBackend::LlvmNvptx,
+        mir_lower::IntrinsicBackend::LibNvvm,
+    ] {
+        let mut ctx = make_test_ctx();
+        let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+        let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+        let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![i32_ty.into()]);
+        let mask = entry.deref(&ctx).get_argument(0);
+        Operation::new(
+            &mut ctx,
+            nvvm::ElectSyncOp::get_concrete_op_info(),
+            vec![i32_ty.into(), i1_ty.into()],
+            vec![mask],
+            vec![],
+            0,
+        )
+        .insert_at_back(entry, &ctx);
+        append_return(&mut ctx, entry);
+
+        mir_lower::lower_mir_to_llvm_with_options(
+            &mut ctx,
+            module_ptr,
+            mir_lower::LoweringOptions {
+                intrinsic_backend: backend,
+                ..Default::default()
+            },
+        )
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+        let mut inline_asm_count = 0;
+        let mut typed_call_count = 0;
+        let mut extract_count = 0;
+        let mut trunc_count = 0;
+        for body_op in lowered_kernel_body(&ctx, module_ptr) {
+            if let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) {
+                assert_eq!(
+                    inline_asm
+                        .get_attr_inline_asm_template(&ctx)
+                        .map(|value| String::from((*value).clone()))
+                        .as_deref(),
+                    Some("{ .reg .pred p; elect.sync $0|p, $2; selp.b32 $1, 1, 0, p; }")
+                );
+                assert_eq!(
+                    inline_asm
+                        .get_attr_inline_asm_constraints(&ctx)
+                        .map(|value| String::from((*value).clone()))
+                        .as_deref(),
+                    Some("=r,=r,r")
+                );
+                assert!(
+                    inline_asm
+                        .get_attr_inline_asm_convergent(&ctx)
+                        .is_some_and(|value| bool::from((*value).clone()))
+                );
+                inline_asm_count += 1;
+            }
+            if let Some(call) = Operation::get_op::<llvm::CallOp>(body_op, &ctx)
+                && let CallOpCallable::Direct(callee) = call.callee(&ctx)
+                && callee.to_string() == "llvm_nvvm_elect_sync"
+            {
+                typed_call_count += 1;
+            }
+            if Operation::get_op::<llvm::ExtractValueOp>(body_op, &ctx).is_some() {
+                extract_count += 1;
+            }
+            if Operation::get_op::<llvm::TruncOp>(body_op, &ctx).is_some() {
+                trunc_count += 1;
+            }
+        }
+
+        assert_eq!(extract_count, 2);
+        match backend {
+            mir_lower::IntrinsicBackend::LlvmNvptx => {
+                assert_eq!(typed_call_count, 1);
+                assert_eq!(inline_asm_count, 0);
+                assert_eq!(trunc_count, 0);
+            }
+            mir_lower::IntrinsicBackend::LibNvvm => {
+                assert_eq!(typed_call_count, 0);
+                assert_eq!(inline_asm_count, 1);
+                assert_eq!(trunc_count, 1);
+            }
+        }
+    }
+    Ok(())
+}
+
+/// The exact inline-PTX template `convert_shuffle_i64` must emit for `mode`/`clamp`.
+/// Mirrors the production `format!` so a drift in either side fails the test.
+fn expected_shfl_i64_template(mode: &str, clamp: i32) -> String {
+    format!(
+        "{{ .reg .b32 lo; .reg .b32 hi; mov.b64 {{lo, hi}}, $1; \
+         shfl.sync.{mode}.b32 lo, lo, $2, {clamp}, $3; \
+         shfl.sync.{mode}.b32 hi, hi, $2, {clamp}, $3; \
+         mov.b64 $0, {{lo, hi}}; }}"
+    )
+}
+
+/// 64-bit warp shuffle has no LLVM intrinsic (`shfl.sync` is 32-bit only), so it
+/// lowers to convergent inline PTX that splits the value into two halves and runs
+/// two `shfl.sync.*.b32`. Inline asm is opaque to LLVM, so a wrong mnemonic,
+/// swapped operand order, wrong clamp, or missing `convergent` would only surface
+/// as bad PTX downstream. This pins, for every mode, the exact template (incl. the
+/// per-mode clamp: 31 for idx/bfly/down, 0 for up), the `=l,l,r,r` constraints,
+/// and the convergent flag.
+#[test]
+fn test_shuffle_i64_lowers_to_inline_asm() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    let i64_ty = IntegerType::get(&ctx, 64, Signedness::Signless);
+    // Kernel args: [mask (i32), value (i64), lane/delta (i32)].
+    let (module_ptr, entry) =
+        build_test_kernel(&mut ctx, vec![i32_ty.into(), i64_ty.into(), i32_ty.into()]);
+    let mask = entry.deref(&ctx).get_argument(0);
+    let value = entry.deref(&ctx).get_argument(1);
+    let lane = entry.deref(&ctx).get_argument(2);
+
+    // One op per mode, all sharing the same [mask, value, lane] operands.
+    type OpInfo = (
+        fn(pliron::context::Ptr<Operation>) -> pliron::op::OpObj,
+        std::any::TypeId,
+    );
+    let modes: [(OpInfo, &str, i32); 4] = [
+        (nvvm::ShflSyncIdxI64Op::get_concrete_op_info(), "idx", 31),
+        (nvvm::ShflSyncBflyI64Op::get_concrete_op_info(), "bfly", 31),
+        (nvvm::ShflSyncDownI64Op::get_concrete_op_info(), "down", 31),
+        (nvvm::ShflSyncUpI64Op::get_concrete_op_info(), "up", 0),
+    ];
+    for (opid, _, _) in modes {
+        let op = Operation::new(
+            &mut ctx,
+            opid,
+            vec![i64_ty.into()],
+            vec![mask, value, lane],
+            vec![],
+            0,
+        );
+        op.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).map_err(|e| anyhow::anyhow!("{}", e))?;
+
+    // Collect every inline-asm template emitted into the kernel body.
+    let mut templates: Vec<String> = Vec::new();
+    let module_op = module_ptr.deref(&ctx);
+    let region = module_op.get_region(0);
+    let block = region.deref(&ctx).iter(&ctx).next().unwrap();
+    for op in block.deref(&ctx).iter(&ctx) {
+        let Some(func_op) = Operation::get_op::<llvm::FuncOp>(op, &ctx) else {
+            continue;
+        };
+        if func_op.get_symbol_name(&ctx).to_string() != "kernel_func" {
+            continue;
+        }
+        let func_region = func_op.get_operation().deref(&ctx).get_region(0);
+        for func_block in func_region.deref(&ctx).iter(&ctx) {
+            for body_op in func_block.deref(&ctx).iter(&ctx) {
+                let Some(inline_asm) = Operation::get_op::<llvm::InlineAsmOp>(body_op, &ctx) else {
+                    continue;
+                };
+                assert_eq!(
+                    inline_asm
+                        .get_attr_inline_asm_constraints(&ctx)
+                        .map(|s| String::from((*s).clone()))
+                        .as_deref(),
+                    Some("=l,l,r,r"),
+                    "shfl.b64 constraints must be [out i64, value i64, lane i32, mask i32]"
+                );
+                assert!(
+                    inline_asm
+                        .get_attr_inline_asm_convergent(&ctx)
+                        .is_some_and(|b| bool::from((*b).clone())),
+                    "shfl.b64 inline asm must be convergent"
+                );
+                templates.push(
+                    inline_asm
+                        .get_attr_inline_asm_template(&ctx)
+                        .map(|s| String::from((*s).clone()))
+                        .unwrap_or_default(),
+                );
+            }
+        }
+    }
+
+    assert_eq!(
+        templates.len(),
+        4,
+        "each of the 4 shfl.b64 modes must lower to one inline-asm op"
+    );
+    for (_, mode, clamp) in modes {
+        let want = expected_shfl_i64_template(mode, clamp);
+        assert!(
+            templates.contains(&want),
+            "missing inline PTX for shfl.sync.{mode}.b32 (clamp {clamp}); got {templates:?}"
+        );
+    }
+
+    Ok(())
+}
diff --git a/crates/mir-lower/tests/lowering_test/wgmma_lowering.rs b/crates/mir-lower/tests/lowering_test/wgmma_lowering.rs
new file mode 100644
index 0000000000..3f024367a4
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/wgmma_lowering.rs
@@ -0,0 +1,2658 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::ops as mir;
+use dialect_nvvm::ops as nvvm;
+use llvm_export::ops as llvm;
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+use pliron::r#type::Typed;
+
+use crate::common::{append_return, build_test_kernel, lowered_kernel_body, make_test_ctx};
+
+pub(super) fn build_wgmma_pointer_test_kernel(
+    ctx: &mut Context,
+    accumulator_count: usize,
+    trailing_arg_types: Vec<pliron::r#type::TypeHandle>,
+) -> (
+    pliron::context::Ptr<Operation>,
+    pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+    Vec<pliron::value::Value>,
+    pliron::value::Value,
+    pliron::value::Value,
+    Vec<pliron::value::Value>,
+) {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+    use pliron::r#type::TypeHandle;
+
+    let f32_ty = FP32Type::get(ctx);
+    let accumulator_ptr_ty: TypeHandle = MirPtrType::get_generic(ctx, f32_ty.into(), true).into();
+    let u64_ty: TypeHandle = IntegerType::get(ctx, 64, Signedness::Unsigned).into();
+
+    let trailing_count = trailing_arg_types.len();
+    let mut argument_types = vec![accumulator_ptr_ty; accumulator_count];
+    argument_types.push(u64_ty);
+    argument_types.push(u64_ty);
+    argument_types.extend(trailing_arg_types);
+
+    let (module_ptr, entry) = build_test_kernel(ctx, argument_types);
+
+    let accumulators = (0..accumulator_count)
+        .map(|index| entry.deref(ctx).get_argument(index))
+        .collect::<Vec<_>>();
+    let desc_a = entry.deref(ctx).get_argument(accumulator_count);
+    let desc_b = entry.deref(ctx).get_argument(accumulator_count + 1);
+    let trailing_arguments = (0..trailing_count)
+        .map(|index| entry.deref(ctx).get_argument(accumulator_count + 2 + index))
+        .collect::<Vec<_>>();
+
+    (
+        module_ptr,
+        entry,
+        accumulators,
+        desc_a,
+        desc_b,
+        trailing_arguments,
+    )
+}
+
+fn build_wgmma_canonical_pointer_test_kernel_with_rows(
+    ctx: &mut Context,
+    accumulator_rows: u64,
+    accumulator_count: usize,
+    descriptor_count: usize,
+) -> (
+    pliron::context::Ptr<Operation>,
+    pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+    Vec<pliron::value::Value>,
+    Vec<pliron::value::Value>,
+) {
+    use dialect_mir::types::{MirArrayType, MirPtrType};
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    let f32_ty = FP32Type::get(ctx);
+    let row_ty = MirArrayType::get(ctx, f32_ty.into(), 8);
+    let accumulator_ty = MirArrayType::get(ctx, row_ty.into(), accumulator_rows);
+    let accumulator_ptr_ty = MirPtrType::get_generic(ctx, accumulator_ty.into(), true);
+    let u64_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);
+
+    let accumulator_arg_ty: pliron::r#type::TypeHandle = accumulator_ptr_ty.into();
+    let u64_arg_ty: pliron::r#type::TypeHandle = u64_ty.into();
+    let mut argument_types = vec![accumulator_arg_ty; accumulator_count];
+    argument_types.extend(vec![u64_arg_ty; descriptor_count]);
+    let (module_ptr, entry) = build_test_kernel(ctx, argument_types);
+
+    let accumulators = (0..accumulator_count)
+        .map(|index| entry.deref(ctx).get_argument(index))
+        .collect::<Vec<_>>();
+    let descriptors = (0..descriptor_count)
+        .map(|index| entry.deref(ctx).get_argument(accumulator_count + index))
+        .collect::<Vec<_>>();
+
+    (module_ptr, entry, accumulators, descriptors)
+}
+
+pub(super) fn build_wgmma_canonical_pointer_test_kernel(
+    ctx: &mut Context,
+    accumulator_count: usize,
+    descriptor_count: usize,
+) -> (
+    pliron::context::Ptr<Operation>,
+    pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+    Vec<pliron::value::Value>,
+    Vec<pliron::value::Value>,
+) {
+    build_wgmma_canonical_pointer_test_kernel_with_rows(ctx, 4, accumulator_count, descriptor_count)
+}
+
+fn build_wgmma_m64n128_canonical_pointer_test_kernel(
+    ctx: &mut Context,
+    accumulator_count: usize,
+    descriptor_count: usize,
+) -> (
+    pliron::context::Ptr<Operation>,
+    pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+    Vec<pliron::value::Value>,
+    Vec<pliron::value::Value>,
+) {
+    build_wgmma_canonical_pointer_test_kernel_with_rows(ctx, 8, accumulator_count, descriptor_count)
+}
+
+pub(super) fn append_pointer_wgmma_mma(
+    ctx: &mut Context,
+    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+    accumulator: pliron::value::Value,
+    desc_a: pliron::value::Value,
+    desc_b: pliron::value::Value,
+) {
+    Operation::new(
+        ctx,
+        nvvm::WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![],
+        vec![accumulator, desc_a, desc_b],
+        vec![],
+        0,
+    )
+    .insert_at_back(block, ctx);
+}
+
+pub(super) fn append_pointer_wgmma_mma_m64n128(
+    ctx: &mut Context,
+    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+    accumulator: pliron::value::Value,
+    desc_a: pliron::value::Value,
+    desc_b: pliron::value::Value,
+) {
+    Operation::new(
+        ctx,
+        nvvm::WgmmaMmaM64N128K16F32Bf16Op::get_concrete_op_info(),
+        vec![],
+        vec![accumulator, desc_a, desc_b],
+        vec![],
+        0,
+    )
+    .insert_at_back(block, ctx);
+}
+
+pub(super) fn append_pointer_wgmma_mma_f16(
+    ctx: &mut Context,
+    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+    accumulator: pliron::value::Value,
+    desc_a: pliron::value::Value,
+    desc_b: pliron::value::Value,
+) {
+    Operation::new(
+        ctx,
+        nvvm::WgmmaMmaM64N64K16F32F16Op::get_concrete_op_info(),
+        vec![],
+        vec![accumulator, desc_a, desc_b],
+        vec![],
+        0,
+    )
+    .insert_at_back(block, ctx);
+}
+
+pub(super) fn append_pointer_wgmma_mma_tf32(
+    ctx: &mut Context,
+    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+    accumulator: pliron::value::Value,
+    desc_a: pliron::value::Value,
+    desc_b: pliron::value::Value,
+) {
+    Operation::new(
+        ctx,
+        nvvm::WgmmaMmaM64N64K8F32Tf32Op::get_concrete_op_info(),
+        vec![],
+        vec![accumulator, desc_a, desc_b],
+        vec![],
+        0,
+    )
+    .insert_at_back(block, ctx);
+}
+
+pub(super) fn append_wgmma_wait_group_constant(
+    ctx: &mut Context,
+    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+    pending_groups: i64,
+) {
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::builtin::types::{IntegerType, Signedness};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let u64_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);
+    let constant_attr = IntegerAttr::new(
+        u64_ty,
+        APInt::from_i64(pending_groups, NonZeroUsize::new(64).unwrap()),
+    );
+    let constant = Operation::new(
+        ctx,
+        mir::MirConstantOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    mir::MirConstantOp::new(constant).set_attr_value(ctx, constant_attr);
+    constant.insert_at_back(block, ctx);
+
+    let value = constant.deref(ctx).get_result(0);
+    nvvm::WgmmaWaitGroupSyncAlignedOp::build(ctx, value).insert_at_back(block, ctx);
+}
+
+pub(super) fn append_mir_unsigned_constant(
+    ctx: &mut Context,
+    block: pliron::context::Ptr<pliron::basic_block::BasicBlock>,
+    ty: pliron::r#type::TypedHandle<pliron::builtin::types::IntegerType>,
+    value: u64,
+) -> pliron::value::Value {
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let width = usize::try_from(ty.deref(ctx).width()).expect("integer width must fit usize");
+    let constant = Operation::new(
+        ctx,
+        mir::MirConstantOp::get_concrete_op_info(),
+        vec![ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    mir::MirConstantOp::new(constant).set_attr_value(
+        ctx,
+        IntegerAttr::new(
+            ty,
+            APInt::from_u64(
+                value,
+                NonZeroUsize::new(width).expect("nonzero integer width"),
+            ),
+        ),
+    );
+    constant.insert_at_back(block, ctx);
+    constant.deref(ctx).get_result(0)
+}
+
+#[test]
+fn test_deferred_wgmma_group_lowers_to_one_register_lifetime_scope() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, f32_ty.into(), true);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let (module_ptr, entry) = build_test_kernel(
+        &mut ctx,
+        vec![accumulator_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
+    );
+    let accumulator = entry.deref(&ctx).get_argument(0);
+    let desc_a = entry.deref(&ctx).get_argument(1);
+    let desc_b = entry.deref(&ctx).get_argument(2);
+
+    nvvm::WgmmaMmaGroupM64N64K16F32Bf16Op::build(&mut ctx, accumulator, vec![desc_a, desc_b])
+        .insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let matching = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
+        .filter(|asm| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| {
+                    template.contains("wgmma.mma_async.sync.aligned.m64n64k16.f32.bf16.bf16")
+                })
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(matching.len(), 1);
+
+    let asm = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("WGMMA template");
+    assert_eq!(template.matches("ld.f32 %acc").count(), 32);
+    assert_eq!(template.matches("st.f32 [$0").count(), 32);
+    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
+    let wait = template.find("wgmma.wait_group.sync.aligned 0").unwrap();
+    let first_store = template.find("st.f32 [$0").unwrap();
+    assert!(
+        wait < first_store,
+        "accumulator stores must follow wait_group<0>"
+    );
+    assert_eq!(
+        asm.get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .as_deref(),
+        Some("l,l,l,~{memory}")
+    );
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+    Ok(())
+}
+
+#[test]
+fn test_value_form_wgmma_group_lowers_to_tied_register_inline_ptx() -> Result<(), anyhow::Error> {
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+    use pliron::r#type::Typed;
+
+    const ACCUMULATOR_LEN: usize = 32;
+    const DESCRIPTOR_COUNT: usize = 4;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+
+    let argument_types = (0..ACCUMULATOR_LEN)
+        .map(|_| f32_ty.into())
+        .chain((0..DESCRIPTOR_COUNT).map(|_| u64_ty.into()))
+        .collect::<Vec<pliron::r#type::TypeHandle>>();
+
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+
+    let accumulators = (0..ACCUMULATOR_LEN)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect::<Vec<_>>();
+    let descriptors = (0..DESCRIPTOR_COUNT)
+        .map(|index| entry.deref(&ctx).get_argument(ACCUMULATOR_LEN + index))
+        .collect::<Vec<_>>();
+
+    nvvm::WgmmaMmaGroupValuesM64N64K16F32Bf16Op::build(&mut ctx, accumulators, descriptors)
+        .insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let matching = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
+        .filter(|asm| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| {
+                    template.contains("wgmma.mma_async.sync.aligned.m64n64k16.f32.bf16.bf16")
+                })
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(matching.len(), 1);
+
+    let asm = &matching[0];
+    let asm_op = asm.get_operation();
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("value-form WGMMA template");
+
+    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
+    assert_eq!(template.matches("wgmma.mma_async").count(), 2);
+    assert_eq!(
+        template.matches("wgmma.commit_group.sync.aligned").count(),
+        1
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 0").count(),
+        1
+    );
+    for forbidden in [".reg .f32", "ld.f32", "st.f32"] {
+        assert!(
+            !template.contains(forbidden),
+            "value-form WGMMA must not materialize accumulator memory via {forbidden:?}: {template}"
+        );
+    }
+
+    let accumulator_operands = (0..ACCUMULATOR_LEN)
+        .map(|index| format!("${index}"))
+        .collect::<Vec<_>>()
+        .join(", ");
+    assert!(
+        template.contains(&format!("{{{accumulator_operands}}}")),
+        "WGMMA must consume the 32 output operands as one accumulator tuple: {template}"
+    );
+    assert!(template.contains("$64, $65"), "{template}");
+    assert!(template.contains("$66, $67"), "{template}");
+
+    let mut expected_constraints = vec!["=f".to_owned(); ACCUMULATOR_LEN];
+    expected_constraints.extend((0..ACCUMULATOR_LEN).map(|index| index.to_string()));
+    expected_constraints.extend((0..DESCRIPTOR_COUNT).map(|_| "l".to_owned()));
+    expected_constraints.push("~{memory}".to_owned());
+    let expected_constraints = expected_constraints.join(",");
+
+    assert_eq!(
+        asm.get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .as_deref(),
+        Some(expected_constraints.as_str())
+    );
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+
+    let asm_ref = asm_op.deref(&ctx);
+    assert_eq!(
+        asm_ref.get_num_operands(),
+        ACCUMULATOR_LEN + DESCRIPTOR_COUNT
+    );
+    assert_eq!(
+        asm_ref.get_num_results(),
+        1,
+        "LLVM inline asm must return the 32 WGMMA accumulator values as one struct"
+    );
+
+    let aggregate = asm_ref.get_result(0);
+    let aggregate_ty = aggregate.get_type(&ctx);
+    let aggregate_ty = aggregate_ty.deref(&ctx);
+    let struct_ty = aggregate_ty
+        .downcast_ref::<llvm_types::StructType>()
+        .expect("value-form WGMMA inline asm must return an LLVM struct");
+    assert_eq!(struct_ty.num_fields(), ACCUMULATOR_LEN);
+    for index in 0..ACCUMULATOR_LEN {
+        assert!(
+            struct_ty
+                .field_type(index)
+                .deref(&ctx)
+                .downcast_ref::<FP32Type>()
+                .is_some(),
+            "WGMMA result field {index} must remain f32"
+        );
+    }
+
+    let extract_indices = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::ExtractValueOp>(operation, &ctx))
+        .filter_map(|extract| {
+            let extract_op = extract.get_operation().deref(&ctx);
+            (extract_op.get_operand(0) == aggregate).then(|| extract.indices(&ctx))
+        })
+        .collect::<Vec<_>>();
+
+    let expected_indices = (0..ACCUMULATOR_LEN)
+        .map(|index| vec![index as u32])
+        .collect::<Vec<_>>();
+    assert_eq!(
+        extract_indices, expected_indices,
+        "all 32 value-form WGMMA results must be extracted in constraint order"
+    );
+
+    Ok(())
+}
+
+#[test]
+fn test_value_form_m64n128_bf16_wgmma_group_lowers_to_sixty_four_tied_registers()
+-> Result<(), anyhow::Error> {
+    use llvm_export::types as llvm_types;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+    use pliron::r#type::Typed;
+
+    const ACCUMULATOR_LEN: usize = 64;
+    const DESCRIPTOR_COUNT: usize = 4;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let argument_types = (0..ACCUMULATOR_LEN)
+        .map(|_| f32_ty.into())
+        .chain((0..DESCRIPTOR_COUNT).map(|_| u64_ty.into()))
+        .collect::<Vec<pliron::r#type::TypeHandle>>();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+
+    let accumulators = (0..ACCUMULATOR_LEN)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect::<Vec<_>>();
+    let descriptors = (0..DESCRIPTOR_COUNT)
+        .map(|index| entry.deref(&ctx).get_argument(ACCUMULATOR_LEN + index))
+        .collect::<Vec<_>>();
+
+    nvvm::WgmmaMmaGroupValuesM64N128K16F32Bf16Op::build(&mut ctx, accumulators, descriptors)
+        .insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let matching = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
+        .filter(|asm| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("m64n128k16.f32.bf16.bf16"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(matching.len(), 1);
+
+    let asm = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("m64n128 value-form WGMMA template");
+    assert_eq!(template.matches("wgmma.mma_async").count(), 2);
+    assert!(template.contains("m64n128k16.f32.bf16.bf16"));
+    assert!(template.contains("$128, $129"));
+    assert!(template.contains("$130, $131"));
+    assert!(!template.contains("ld.f32"));
+    assert!(!template.contains("st.f32"));
+
+    let constraints = asm
+        .get_attr_inline_asm_constraints(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("m64n128 value-form WGMMA constraints");
+    assert_eq!(
+        constraints
+            .split(',')
+            .filter(|value| *value == "=f")
+            .count(),
+        64
+    );
+    assert_eq!(
+        constraints.split(',').filter(|value| *value == "l").count(),
+        4
+    );
+    assert!(constraints.ends_with("~{memory}"));
+
+    let aggregate = asm.get_operation().deref(&ctx).get_result(0);
+    let aggregate_ty = aggregate.get_type(&ctx);
+    let aggregate_ty = aggregate_ty.deref(&ctx);
+    let struct_ty = aggregate_ty
+        .downcast_ref::<llvm_types::StructType>()
+        .expect("m64n128 inline asm must return an LLVM struct");
+    assert_eq!(struct_ty.num_fields(), ACCUMULATOR_LEN);
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+
+    Ok(())
+}
+
+#[test]
+fn test_value_form_f16_wgmma_group_lowers_to_tied_register_inline_ptx() -> Result<(), anyhow::Error>
+{
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    const ACCUMULATOR_LEN: usize = 32;
+    const DESCRIPTOR_COUNT: usize = 2;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let argument_types = (0..ACCUMULATOR_LEN)
+        .map(|_| f32_ty.into())
+        .chain((0..DESCRIPTOR_COUNT).map(|_| u64_ty.into()))
+        .collect::<Vec<pliron::r#type::TypeHandle>>();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+
+    let accumulators = (0..ACCUMULATOR_LEN)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect::<Vec<_>>();
+    let descriptors = (0..DESCRIPTOR_COUNT)
+        .map(|index| entry.deref(&ctx).get_argument(ACCUMULATOR_LEN + index))
+        .collect::<Vec<_>>();
+
+    nvvm::WgmmaMmaGroupValuesM64N64K16F32F16Op::build(&mut ctx, accumulators, descriptors)
+        .insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let matching = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
+        .filter(|asm| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("m64n64k16.f32.f16.f16"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(matching.len(), 1);
+
+    let asm = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("F16 value-form WGMMA template");
+    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
+    assert!(template.contains("m64n64k16.f32.f16.f16"));
+    assert!(!template.contains(".bf16.bf16"));
+    assert!(template.contains("wgmma.fence.sync.aligned"));
+    assert!(template.contains("wgmma.commit_group.sync.aligned"));
+    assert!(template.contains("wgmma.wait_group.sync.aligned 0"));
+    assert!(!template.contains("ld.f32"));
+    assert!(!template.contains("st.f32"));
+
+    let constraints = asm
+        .get_attr_inline_asm_constraints(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("F16 value-form WGMMA constraints");
+    assert_eq!(
+        constraints
+            .split(',')
+            .filter(|value| *value == "=f")
+            .count(),
+        32
+    );
+    assert_eq!(
+        constraints.split(',').filter(|value| *value == "l").count(),
+        2
+    );
+    assert!(constraints.ends_with("~{memory}"));
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+
+    Ok(())
+}
+
+#[test]
+fn test_value_form_tf32_wgmma_group_lowers_to_tied_register_inline_ptx() -> Result<(), anyhow::Error>
+{
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    const ACCUMULATOR_LEN: usize = 32;
+    const DESCRIPTOR_COUNT: usize = 2;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let argument_types = (0..ACCUMULATOR_LEN)
+        .map(|_| f32_ty.into())
+        .chain((0..DESCRIPTOR_COUNT).map(|_| u64_ty.into()))
+        .collect::<Vec<pliron::r#type::TypeHandle>>();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types);
+
+    let accumulators = (0..ACCUMULATOR_LEN)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect::<Vec<_>>();
+    let descriptors = (0..DESCRIPTOR_COUNT)
+        .map(|index| entry.deref(&ctx).get_argument(ACCUMULATOR_LEN + index))
+        .collect::<Vec<_>>();
+
+    nvvm::WgmmaMmaGroupValuesM64N64K8F32Tf32Op::build(&mut ctx, accumulators, descriptors)
+        .insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let matching = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
+        .filter(|asm| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("m64n64k8.f32.tf32.tf32"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(matching.len(), 1);
+
+    let asm = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("TF32 value-form WGMMA template");
+    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
+    assert!(template.contains("m64n64k8.f32.tf32.tf32"));
+    assert!(!template.contains(".bf16.bf16"));
+    assert!(!template.contains(".f16.f16"));
+    assert!(!template.contains("m64n64k16"));
+    assert!(template.contains("$64, $65, 1, 1, 1;"));
+    assert!(!template.contains("$64, $65, 1, 1, 1, 0, 0;"));
+    assert!(template.contains("wgmma.fence.sync.aligned"));
+    assert!(template.contains("wgmma.commit_group.sync.aligned"));
+    assert!(template.contains("wgmma.wait_group.sync.aligned 0"));
+    assert!(!template.contains("ld.f32"));
+    assert!(!template.contains("st.f32"));
+
+    let constraints = asm
+        .get_attr_inline_asm_constraints(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("TF32 value-form WGMMA constraints");
+    assert_eq!(
+        constraints
+            .split(',')
+            .filter(|value| *value == "=f")
+            .count(),
+        32
+    );
+    assert_eq!(
+        constraints.split(',').filter(|value| *value == "l").count(),
+        2
+    );
+    assert!(constraints.ends_with("~{memory}"));
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+
+    Ok(())
+}
+
+#[test]
+fn test_pointer_form_wgmma_sequence_preserves_deferred_fallback() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::MirPtrType;
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    // A direct *mut f32 is intentionally not the public [[f32; 8]; 4]
+    // accumulator shape. It must therefore retain the deferred pointer path.
+    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, f32_ty.into(), true);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let (module_ptr, entry) = build_test_kernel(
+        &mut ctx,
+        vec![accumulator_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
+    );
+    let accumulator = entry.deref(&ctx).get_argument(0);
+    let desc_a = entry.deref(&ctx).get_argument(1);
+    let desc_b = entry.deref(&ctx).get_argument(2);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    Operation::new(
+        &mut ctx,
+        nvvm::WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![],
+        vec![accumulator, desc_a, desc_b],
+        vec![],
+        0,
+    )
+    .insert_at_back(entry, &ctx);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+
+    let zero_attr = IntegerAttr::new(u64_ty, APInt::from_i64(0, NonZeroUsize::new(64).unwrap()));
+    let zero = Operation::new(
+        &mut ctx,
+        mir::MirConstantOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    mir::MirConstantOp::new(zero).set_attr_value(&ctx, zero_attr);
+    zero.insert_at_back(entry, &ctx);
+    let zero_value = zero.deref(&ctx).get_result(0);
+    nvvm::WgmmaWaitGroupSyncAlignedOp::build(&mut ctx, zero_value).insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let matching = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
+        .filter(|asm| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("wgmma.mma_async"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(matching.len(), 1);
+
+    let asm = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("WGMMA template");
+    assert_eq!(template.matches("ld.f32 %acc").count(), 32);
+    assert_eq!(template.matches("st.f32 [$0").count(), 32);
+    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
+    assert!(template.contains("wgmma.fence.sync.aligned"));
+    assert!(template.contains("wgmma.commit_group.sync.aligned"));
+    assert!(template.contains("wgmma.wait_group.sync.aligned 0"));
+    assert_eq!(
+        asm.get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .as_deref(),
+        Some("l,l,l,~{memory}")
+    );
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+
+    Ok(())
+}
+
+#[test]
+fn test_pointer_form_wgmma_region_canonicalizes_reborrow_identity() -> Result<(), anyhow::Error> {
+    use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
+    use dialect_mir::types::{MirArrayType, MirPointerKind, MirPtrType};
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
+    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
+    let erased_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
+    let unique_ptr_ty: pliron::r#type::TypeHandle = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        accumulator_ty.into(),
+        true,
+        MirPointerKind::UniqueRef,
+    )
+    .into();
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+
+    let (module_ptr, entry) = build_test_kernel(
+        &mut ctx,
+        vec![erased_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
+    );
+    let accumulator = entry.deref(&ctx).get_argument(0);
+    let desc_a = entry.deref(&ctx).get_argument(1);
+    let desc_b = entry.deref(&ctx).get_argument(2);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+
+    // The importer emits a fresh kind-only retype for each `Rvalue::Ref`.
+    // Both typed operands must canonicalize to the same storage identity, while
+    // the first typed operand remains available to the linear lowering plan.
+    let first_retype = Operation::new(
+        &mut ctx,
+        mir::MirCastOp::get_concrete_op_info(),
+        vec![unique_ptr_ty],
+        vec![accumulator],
+        vec![],
+        0,
+    );
+    mir::MirCastOp::new(first_retype).set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    mir::MirCastOp::new(first_retype)
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    first_retype.insert_at_back(entry, &ctx);
+    let first_reborrow = first_retype.deref(&ctx).get_result(0);
+
+    Operation::new(
+        &mut ctx,
+        nvvm::WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![],
+        vec![first_reborrow, desc_a, desc_b],
+        vec![],
+        0,
+    )
+    .insert_at_back(entry, &ctx);
+
+    let second_retype = Operation::new(
+        &mut ctx,
+        mir::MirCastOp::get_concrete_op_info(),
+        vec![unique_ptr_ty],
+        vec![accumulator],
+        vec![],
+        0,
+    );
+    mir::MirCastOp::new(second_retype).set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    mir::MirCastOp::new(second_retype)
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    second_retype.insert_at_back(entry, &ctx);
+    let second_reborrow = second_retype.deref(&ctx).get_result(0);
+    assert_ne!(
+        first_reborrow, second_reborrow,
+        "the regression requires two distinct reborrow SSA values"
+    );
+    let first_reborrow_ty = first_reborrow.get_type(&ctx);
+    assert_eq!(
+        first_reborrow_ty
+            .deref(&ctx)
+            .downcast_ref::<MirPtrType>()
+            .expect("first reborrow must remain a typed MIR pointer")
+            .pointer_kind(),
+        MirPointerKind::UniqueRef,
+        "the regression must provide a typed UniqueRef for the linear plan to retain"
+    );
+
+    Operation::new(
+        &mut ctx,
+        nvvm::WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
+        vec![],
+        vec![second_reborrow, desc_a, desc_b],
+        vec![],
+        0,
+    )
+    .insert_at_back(entry, &ctx);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+
+    let zero_attr = IntegerAttr::new(u64_ty, APInt::from_i64(0, NonZeroUsize::new(64).unwrap()));
+    let zero = Operation::new(
+        &mut ctx,
+        mir::MirConstantOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    mir::MirConstantOp::new(zero).set_attr_value(&ctx, zero_attr);
+    zero.insert_at_back(entry, &ctx);
+    let zero_value = zero.deref(&ctx).get_result(0);
+    nvvm::WgmmaWaitGroupSyncAlignedOp::build(&mut ctx, zero_value).insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let matching = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
+        .filter(|asm| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| {
+                    template.contains("wgmma.mma_async.sync.aligned.m64n64k16.f32.bf16.bf16")
+                })
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        matching.len(),
+        1,
+        "distinct reborrow SSA values for one accumulator must not break deferred fusion"
+    );
+    let template = matching[0]
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("WGMMA template");
+    assert_eq!(
+        template.matches("wgmma.mma_async").count(),
+        2,
+        "both reborrows must remain in one fused accumulator region"
+    );
+    Ok(())
+}
+
+#[test]
+fn test_pointer_form_wgmma_sequence_uses_value_adapter_before_lowering() -> Result<(), anyhow::Error>
+{
+    use dialect_mir::types::{MirArrayType, MirPtrType};
+    use pliron::builtin::attributes::IntegerAttr;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+    use pliron::utils::apint::APInt;
+    use std::num::NonZeroUsize;
+
+    const ACCUMULATOR_LEN: usize = 32;
+    const DESCRIPTOR_COUNT: usize = 4;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
+    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
+    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+
+    let (module_ptr, entry) = build_test_kernel(
+        &mut ctx,
+        vec![
+            accumulator_ptr_ty.into(),
+            u64_ty.into(),
+            u64_ty.into(),
+            u64_ty.into(),
+            u64_ty.into(),
+        ],
+    );
+    let accumulator = entry.deref(&ctx).get_argument(0);
+    let descriptors = (1..=DESCRIPTOR_COUNT)
+        .map(|index| entry.deref(&ctx).get_argument(index))
+        .collect::<Vec<_>>();
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    for pair in descriptors.chunks_exact(2) {
+        Operation::new(
+            &mut ctx,
+            nvvm::WgmmaMmaM64N64K16F32Bf16Op::get_concrete_op_info(),
+            vec![],
+            vec![accumulator, pair[0], pair[1]],
+            vec![],
+            0,
+        )
+        .insert_at_back(entry, &ctx);
+    }
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+
+    let zero_attr = IntegerAttr::new(u64_ty, APInt::from_i64(0, NonZeroUsize::new(64).unwrap()));
+    let zero = Operation::new(
+        &mut ctx,
+        mir::MirConstantOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![],
+        vec![],
+        0,
+    );
+    mir::MirConstantOp::new(zero).set_attr_value(&ctx, zero_attr);
+    zero.insert_at_back(entry, &ctx);
+    let zero_value = zero.deref(&ctx).get_result(0);
+    nvvm::WgmmaWaitGroupSyncAlignedOp::build(&mut ctx, zero_value).insert_at_back(entry, &ctx);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let matching = body
+        .iter()
+        .copied()
+        .filter_map(|operation| {
+            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
+                .map(|inline_asm| (operation, inline_asm))
+        })
+        .filter(|(_, asm)| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("wgmma.mma_async"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(matching.len(), 1);
+
+    let (asm_operation, asm) = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("WGMMA template");
+
+    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
+    assert_eq!(template.matches("wgmma.mma_async").count(), 2);
+    assert_eq!(
+        template.matches("wgmma.commit_group.sync.aligned").count(),
+        1
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 0").count(),
+        1
+    );
+    assert!(
+        !template.contains(".reg .f32")
+            && !template.contains("ld.f32")
+            && !template.contains("st.f32"),
+        "value-form WGMMA must not materialize accumulator memory inside asm: {template}"
+    );
+
+    let mut expected_constraints = vec!["=f".to_owned(); ACCUMULATOR_LEN];
+    expected_constraints.extend((0..ACCUMULATOR_LEN).map(|index| index.to_string()));
+    expected_constraints.extend((0..DESCRIPTOR_COUNT).map(|_| "l".to_owned()));
+    expected_constraints.push("~{memory}".to_owned());
+    let expected_constraints = expected_constraints.join(",");
+
+    assert_eq!(
+        asm.get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .as_deref(),
+        Some(expected_constraints.as_str())
+    );
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+
+    let asm_ref = asm_operation.deref(&ctx);
+    assert_eq!(
+        asm_ref.get_num_operands(),
+        ACCUMULATOR_LEN + DESCRIPTOR_COUNT
+    );
+    assert_eq!(asm_ref.get_num_results(), 1);
+
+    let asm_position = body
+        .iter()
+        .position(|operation| operation == asm_operation)
+        .expect("WGMMA asm must be in the lowered kernel body");
+
+    let load_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        load_positions.len(),
+        ACCUMULATOR_LEN,
+        "the linear adapter must load each accumulator value exactly once"
+    );
+    assert!(
+        load_positions.iter().all(|index| *index < asm_position),
+        "all accumulator loads must happen before the WGMMA region"
+    );
+
+    let store_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        store_positions.len(),
+        ACCUMULATOR_LEN,
+        "the linear adapter must store each accumulator value exactly once"
+    );
+    assert!(
+        store_positions.iter().all(|index| *index > asm_position),
+        "all accumulator stores must happen after the final wait"
+    );
+
+    assert_eq!(
+        body.iter()
+            .filter(
+                |operation| Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
+            )
+            .count(),
+        ACCUMULATOR_LEN,
+        "all WGMMA accumulator results must be recovered as scalar SSA values"
+    );
+
+    Ok(())
+}
+
+#[test]
+fn test_pointer_form_m64n128_bf16_linear_full_drain_uses_sixty_four_value_adapter()
+-> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, descriptors) =
+        build_wgmma_m64n128_canonical_pointer_test_kernel(&mut ctx, 1, 4);
+    let accumulator = accumulators[0];
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma_m64n128(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
+    append_pointer_wgmma_mma_m64n128(&mut ctx, entry, accumulator, descriptors[2], descriptors[3]);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let matching = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
+        .filter(|asm| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("m64n128k16.f32.bf16.bf16"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(matching.len(), 1);
+
+    let asm = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("m64n128 pointer-form WGMMA template");
+    assert_eq!(template.matches("wgmma.mma_async").count(), 2);
+    assert!(template.contains("m64n128k16.f32.bf16.bf16"));
+    assert!(!template.contains("ld.f32"));
+    assert!(!template.contains("st.f32"));
+
+    let constraints = asm
+        .get_attr_inline_asm_constraints(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("m64n128 pointer-form WGMMA constraints");
+    assert_eq!(
+        constraints
+            .split(',')
+            .filter(|value| *value == "=f")
+            .count(),
+        64
+    );
+    assert_eq!(
+        constraints.split(',').filter(|value| *value == "l").count(),
+        4
+    );
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+
+    Ok(())
+}
+
+#[test]
+fn test_pointer_form_f16_wgmma_linear_full_drain_uses_value_adapter() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, descriptors) =
+        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 2);
+    let accumulator = accumulators[0];
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma_f16(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let matching = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
+        .filter(|asm| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("m64n64k16.f32.f16.f16"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(matching.len(), 1);
+
+    let asm = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("F16 pointer-form WGMMA template");
+    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
+    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
+    assert_eq!(
+        template.matches("wgmma.commit_group.sync.aligned").count(),
+        1
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 0").count(),
+        1
+    );
+    assert!(template.contains("m64n64k16.f32.f16.f16"));
+    assert!(!template.contains(".bf16.bf16"));
+    assert!(!template.contains("ld.f32"));
+    assert!(!template.contains("st.f32"));
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+
+    Ok(())
+}
+
+#[test]
+fn test_pointer_form_tf32_wgmma_linear_full_drain_uses_value_adapter() -> Result<(), anyhow::Error>
+{
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, descriptors) =
+        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 2);
+    let accumulator = accumulators[0];
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma_tf32(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let matching = lowered_kernel_body(&ctx, module_ptr)
+        .into_iter()
+        .filter_map(|operation| Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx))
+        .filter(|asm| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("m64n64k8.f32.tf32.tf32"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(matching.len(), 1);
+
+    let asm = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("TF32 pointer-form WGMMA template");
+    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
+    assert_eq!(template.matches("wgmma.mma_async").count(), 1);
+    assert_eq!(
+        template.matches("wgmma.commit_group.sync.aligned").count(),
+        1
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 0").count(),
+        1
+    );
+    assert!(template.contains("m64n64k8.f32.tf32.tf32"));
+    assert!(!template.contains(".bf16.bf16"));
+    assert!(!template.contains(".f16.f16"));
+    assert!(!template.contains("m64n64k16"));
+    assert!(template.contains("$64, $65, 1, 1, 1;"));
+    assert!(!template.contains("$64, $65, 1, 1, 1, 0, 0;"));
+    assert!(!template.contains("ld.f32"));
+    assert!(!template.contains("st.f32"));
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+
+    Ok(())
+}
+
+#[test]
+fn test_pointer_form_wgmma_partial_wait_pipeline_keeps_multiple_groups_in_flight()
+-> Result<(), anyhow::Error> {
+    const SLOT_COUNT: usize = 2;
+    const ACCUMULATOR_LEN: usize = 32;
+    const GROUP_COUNT: usize = 4;
+    const DESCRIPTOR_COUNT: usize = GROUP_COUNT * 2;
+    const MAX_PENDING_GROUPS: i64 = 1;
+    const RESULT_COUNT: usize = SLOT_COUNT * ACCUMULATOR_LEN;
+
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, descriptors) =
+        build_wgmma_canonical_pointer_test_kernel(&mut ctx, SLOT_COUNT, DESCRIPTOR_COUNT);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    for group in 0..GROUP_COUNT {
+        append_pointer_wgmma_mma(
+            &mut ctx,
+            entry,
+            accumulators[group % SLOT_COUNT],
+            descriptors[group * 2],
+            descriptors[group * 2 + 1],
+        );
+        nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+        if group + 1 >= SLOT_COUNT {
+            append_wgmma_wait_group_constant(&mut ctx, entry, MAX_PENDING_GROUPS);
+        }
+    }
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let matching = body
+        .iter()
+        .copied()
+        .filter_map(|operation| {
+            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
+                .map(|inline_asm| (operation, inline_asm))
+        })
+        .filter(|(_, asm)| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| {
+                    template.contains("wgmma.mma_async")
+                        && template.contains("wgmma.wait_group.sync.aligned 1")
+                })
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        matching.len(),
+        1,
+        "expected one fused partial-wait WGMMA pipeline"
+    );
+
+    let (asm_operation, asm) = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("pipeline WGMMA template");
+
+    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
+    assert_eq!(template.matches("wgmma.mma_async").count(), GROUP_COUNT);
+    assert_eq!(
+        template.matches("wgmma.commit_group.sync.aligned").count(),
+        GROUP_COUNT
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 1").count(),
+        GROUP_COUNT - SLOT_COUNT + 1
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 0").count(),
+        1
+    );
+    assert!(
+        template.contains("{$0, $1"),
+        "slot 0 must use the first accumulator tuple"
+    );
+    assert!(
+        template.contains("{$32, $33"),
+        "slot 1 must use the second accumulator tuple"
+    );
+    assert!(template.contains("$128, $129"));
+    assert!(template.contains("$134, $135"));
+    assert!(
+        !template.contains(".reg .f32")
+            && !template.contains("ld.f32")
+            && !template.contains("st.f32"),
+        "pipeline WGMMA must not materialize accumulator memory inside asm: {template}"
+    );
+
+    let mut expected_constraints = vec!["=f".to_owned(); RESULT_COUNT];
+    expected_constraints.extend((0..RESULT_COUNT).map(|index| index.to_string()));
+    expected_constraints.extend((0..DESCRIPTOR_COUNT).map(|_| "l".to_owned()));
+    expected_constraints.push("~{memory}".to_owned());
+    let expected_constraints = expected_constraints.join(",");
+    assert_eq!(
+        asm.get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .as_deref(),
+        Some(expected_constraints.as_str())
+    );
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+    assert_eq!(
+        asm_operation.deref(&ctx).get_num_operands(),
+        RESULT_COUNT + DESCRIPTOR_COUNT
+    );
+    assert_eq!(asm_operation.deref(&ctx).get_num_results(), 1);
+
+    let asm_position = body
+        .iter()
+        .position(|operation| operation == asm_operation)
+        .expect("pipeline asm must be in the lowered kernel body");
+    let load_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(load_positions.len(), RESULT_COUNT);
+    assert!(load_positions.iter().all(|index| *index < asm_position));
+
+    let store_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(store_positions.len(), RESULT_COUNT);
+    assert!(store_positions.iter().all(|index| *index > asm_position));
+    assert_eq!(
+        body.iter()
+            .filter(|operation| {
+                Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
+            })
+            .count(),
+        RESULT_COUNT
+    );
+
+    Ok(())
+}
+
+pub(super) fn build_pointer_form_wgmma_counted_pipeline_case(
+    ctx: &mut Context,
+    slot_count: usize,
+    wait_depths: &[i64],
+    repeat_last_accumulator: bool,
+) -> pliron::context::Ptr<Operation> {
+    use dialect_mir::types::{MirArrayType, MirPtrType};
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::op_interfaces::OperandSegmentInterface;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    assert_eq!(wait_depths.len(), slot_count);
+
+    let f32_ty = FP32Type::get(ctx);
+    let row_ty = MirArrayType::get(ctx, f32_ty.into(), 8);
+    let accumulator_ty = MirArrayType::get(ctx, row_ty.into(), 4);
+    let accumulator_ptr_ty = MirPtrType::get_generic(ctx, accumulator_ty.into(), true);
+    let u32_ty = IntegerType::get(ctx, 32, Signedness::Unsigned);
+    let u64_ty = IntegerType::get(ctx, 64, Signedness::Unsigned);
+    let i1_ty = IntegerType::get(ctx, 1, Signedness::Signless);
+    let u64_type: pliron::r#type::TypeHandle = u64_ty.into();
+
+    let mut argument_types: Vec<pliron::r#type::TypeHandle> =
+        vec![accumulator_ptr_ty.into(); slot_count];
+    argument_types.extend(vec![u64_type; slot_count * 2]);
+    let (module_ptr, preheader) = build_test_kernel(ctx, argument_types);
+
+    let accumulators = (0..slot_count)
+        .map(|slot| preheader.deref(ctx).get_argument(slot))
+        .collect::<Vec<_>>();
+    let desc_bases = (0..slot_count * 2)
+        .map(|index| preheader.deref(ctx).get_argument(slot_count + index))
+        .collect::<Vec<_>>();
+
+    let module_region = module_ptr.deref(ctx).get_region(0);
+    let module_block = module_region.deref(ctx).iter(ctx).next().unwrap();
+    let function = module_block.deref(ctx).iter(ctx).next().unwrap();
+    let function_region = function.deref(ctx).get_region(0);
+
+    let mut header_types: Vec<pliron::r#type::TypeHandle> = vec![u32_ty.into()];
+    header_types.extend(vec![u64_type; slot_count * 2]);
+    let header = BasicBlock::new(ctx, None, header_types);
+    header.insert_at_back(function_region, ctx);
+    let latch = BasicBlock::new(ctx, None, vec![]);
+    latch.insert_at_back(function_region, ctx);
+    let exit = BasicBlock::new(ctx, None, vec![]);
+    exit.insert_at_back(function_region, ctx);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(ctx).insert_at_back(preheader, ctx);
+    let i0 = append_mir_unsigned_constant(ctx, preheader, u32_ty, 0);
+    let mut initial_values = vec![i0];
+    initial_values.extend(desc_bases.iter().copied());
+    Operation::new(
+        ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        initial_values,
+        vec![header],
+        0,
+    )
+    .insert_at_back(preheader, ctx);
+
+    let i = header.deref(ctx).get_argument(0);
+    let descriptors = (0..slot_count * 2)
+        .map(|index| header.deref(ctx).get_argument(1 + index))
+        .collect::<Vec<_>>();
+    let bound = append_mir_unsigned_constant(ctx, header, u32_ty, 4);
+    let lt = Operation::new(
+        ctx,
+        mir::MirLtOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![i, bound],
+        vec![],
+        0,
+    );
+    lt.insert_at_back(header, ctx);
+    let lt_value = lt.deref(ctx).get_result(0);
+    let not_lt = Operation::new(
+        ctx,
+        mir::MirNotOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![lt_value],
+        vec![],
+        0,
+    );
+    not_lt.insert_at_back(header, ctx);
+    let not_lt_value = not_lt.deref(ctx).get_result(0);
+    let (branch_operands, segment_sizes) =
+        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![not_lt_value], vec![], vec![]]);
+    let branch = Operation::new(
+        ctx,
+        mir::MirCondBranchOp::get_concrete_op_info(),
+        vec![],
+        branch_operands,
+        vec![exit, latch],
+        0,
+    );
+    Operation::get_op::<mir::MirCondBranchOp>(branch, ctx)
+        .expect("MirCondBranchOp")
+        .set_operand_segment_sizes(ctx, segment_sizes);
+    branch.insert_at_back(header, ctx);
+
+    for slot in 0..slot_count {
+        let accumulator = if repeat_last_accumulator && slot + 1 == slot_count {
+            accumulators[0]
+        } else {
+            accumulators[slot]
+        };
+        append_pointer_wgmma_mma(
+            ctx,
+            latch,
+            accumulator,
+            descriptors[slot * 2],
+            descriptors[slot * 2 + 1],
+        );
+        nvvm::WgmmaCommitGroupSyncAlignedOp::build(ctx).insert_at_back(latch, ctx);
+        append_wgmma_wait_group_constant(ctx, latch, wait_depths[slot]);
+    }
+
+    let one = append_mir_unsigned_constant(ctx, latch, u32_ty, 1);
+    let i_next = Operation::new(
+        ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![i, one],
+        vec![],
+        0,
+    );
+    i_next.insert_at_back(latch, ctx);
+    let i_next = i_next.deref(ctx).get_result(0);
+
+    let mut next_values = vec![i_next];
+    for (index, descriptor) in descriptors.iter().copied().enumerate() {
+        let step = append_mir_unsigned_constant(ctx, latch, u64_ty, 16 * (index as u64 + 1));
+        let next = Operation::new(
+            ctx,
+            mir::MirAddOp::get_concrete_op_info(),
+            vec![u64_ty.into()],
+            vec![descriptor, step],
+            vec![],
+            0,
+        );
+        next.insert_at_back(latch, ctx);
+        next_values.push(next.deref(ctx).get_result(0));
+    }
+
+    Operation::new(
+        ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        next_values,
+        vec![header],
+        0,
+    )
+    .insert_at_back(latch, ctx);
+
+    append_wgmma_wait_group_constant(ctx, exit, 0);
+    append_return(ctx, exit);
+
+    module_ptr
+}
+
+#[test]
+fn test_pointer_form_wgmma_two_slot_counted_pipeline_stays_register_resident()
+-> Result<(), anyhow::Error> {
+    use dialect_mir::types::{MirArrayType, MirPtrType};
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::op_interfaces::OperandSegmentInterface;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    const SLOT_COUNT: usize = 2;
+    const ACCUMULATOR_LEN: usize = 32;
+    const RESULT_COUNT: usize = SLOT_COUNT * ACCUMULATOR_LEN;
+    const LOOP_CONTROL_COUNT: usize = 9;
+    const TRIP_COUNT: u64 = 4;
+    const DESC_A0_STEP: u64 = 16;
+    const DESC_B0_STEP: u64 = 32;
+    const DESC_A1_STEP: u64 = 48;
+    const DESC_B1_STEP: u64 = 64;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
+    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
+    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+
+    let (module_ptr, preheader) = build_test_kernel(
+        &mut ctx,
+        vec![
+            accumulator_ptr_ty.into(),
+            accumulator_ptr_ty.into(),
+            u64_ty.into(),
+            u64_ty.into(),
+            u64_ty.into(),
+            u64_ty.into(),
+        ],
+    );
+    let accumulator0 = preheader.deref(&ctx).get_argument(0);
+    let accumulator1 = preheader.deref(&ctx).get_argument(1);
+    let desc_a0_base = preheader.deref(&ctx).get_argument(2);
+    let desc_b0_base = preheader.deref(&ctx).get_argument(3);
+    let desc_a1_base = preheader.deref(&ctx).get_argument(4);
+    let desc_b1_base = preheader.deref(&ctx).get_argument(5);
+
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
+    let function_region = function.deref(&ctx).get_region(0);
+
+    let header = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![
+            u32_ty.into(),
+            u64_ty.into(),
+            u64_ty.into(),
+            u64_ty.into(),
+            u64_ty.into(),
+        ],
+    );
+    header.insert_at_back(function_region, &ctx);
+    let latch = BasicBlock::new(&mut ctx, None, vec![]);
+    latch.insert_at_back(function_region, &ctx);
+    let exit = BasicBlock::new(&mut ctx, None, vec![]);
+    exit.insert_at_back(function_region, &ctx);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(preheader, &ctx);
+    let i0 = append_mir_unsigned_constant(&mut ctx, preheader, u32_ty, 0);
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![i0, desc_a0_base, desc_b0_base, desc_a1_base, desc_b1_base],
+        vec![header],
+        0,
+    )
+    .insert_at_back(preheader, &ctx);
+
+    let i = header.deref(&ctx).get_argument(0);
+    let desc_a0 = header.deref(&ctx).get_argument(1);
+    let desc_b0 = header.deref(&ctx).get_argument(2);
+    let desc_a1 = header.deref(&ctx).get_argument(3);
+    let desc_b1 = header.deref(&ctx).get_argument(4);
+    let bound = append_mir_unsigned_constant(&mut ctx, header, u32_ty, TRIP_COUNT);
+    let lt = Operation::new(
+        &mut ctx,
+        mir::MirLtOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![i, bound],
+        vec![],
+        0,
+    );
+    lt.insert_at_back(header, &ctx);
+    let lt_value = lt.deref(&ctx).get_result(0);
+    let not_lt = Operation::new(
+        &mut ctx,
+        mir::MirNotOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![lt_value],
+        vec![],
+        0,
+    );
+    not_lt.insert_at_back(header, &ctx);
+    let not_lt_value = not_lt.deref(&ctx).get_result(0);
+    let (branch_operands, segment_sizes) =
+        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![not_lt_value], vec![], vec![]]);
+    let branch = Operation::new(
+        &mut ctx,
+        mir::MirCondBranchOp::get_concrete_op_info(),
+        vec![],
+        branch_operands,
+        vec![exit, latch],
+        0,
+    );
+    Operation::get_op::<mir::MirCondBranchOp>(branch, &ctx)
+        .expect("MirCondBranchOp")
+        .set_operand_segment_sizes(&ctx, segment_sizes);
+    branch.insert_at_back(header, &ctx);
+
+    append_pointer_wgmma_mma(&mut ctx, latch, accumulator0, desc_a0, desc_b0);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(latch, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, latch, 1);
+    append_pointer_wgmma_mma(&mut ctx, latch, accumulator1, desc_a1, desc_b1);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(latch, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, latch, 1);
+
+    let one = append_mir_unsigned_constant(&mut ctx, latch, u32_ty, 1);
+    let i_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![i, one],
+        vec![],
+        0,
+    );
+    i_next.insert_at_back(latch, &ctx);
+    let i_next = i_next.deref(&ctx).get_result(0);
+
+    let desc_a0_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_A0_STEP);
+    let desc_a0_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![desc_a0, desc_a0_step],
+        vec![],
+        0,
+    );
+    desc_a0_next.insert_at_back(latch, &ctx);
+    let desc_a0_next = desc_a0_next.deref(&ctx).get_result(0);
+
+    let desc_b0_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_B0_STEP);
+    let desc_b0_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![desc_b0, desc_b0_step],
+        vec![],
+        0,
+    );
+    desc_b0_next.insert_at_back(latch, &ctx);
+    let desc_b0_next = desc_b0_next.deref(&ctx).get_result(0);
+
+    let desc_a1_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_A1_STEP);
+    let desc_a1_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![desc_a1, desc_a1_step],
+        vec![],
+        0,
+    );
+    desc_a1_next.insert_at_back(latch, &ctx);
+    let desc_a1_next = desc_a1_next.deref(&ctx).get_result(0);
+
+    let desc_b1_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_B1_STEP);
+    let desc_b1_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![desc_b1, desc_b1_step],
+        vec![],
+        0,
+    );
+    desc_b1_next.insert_at_back(latch, &ctx);
+    let desc_b1_next = desc_b1_next.deref(&ctx).get_result(0);
+
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![
+            i_next,
+            desc_a0_next,
+            desc_b0_next,
+            desc_a1_next,
+            desc_b1_next,
+        ],
+        vec![header],
+        0,
+    )
+    .insert_at_back(latch, &ctx);
+
+    append_wgmma_wait_group_constant(&mut ctx, exit, 0);
+    append_return(&mut ctx, exit);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let matching = body
+        .iter()
+        .copied()
+        .filter_map(|operation| {
+            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
+                .map(|inline_asm| (operation, inline_asm))
+        })
+        .filter(|(_, asm)| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("L__wgmma_pipeline_loop_${:uid}:"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        matching.len(),
+        1,
+        "expected one fused two-slot counted WGMMA pipeline"
+    );
+
+    let (asm_operation, asm) = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("counted-pipeline WGMMA template");
+
+    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
+    assert_eq!(template.matches("wgmma.mma_async").count(), 2);
+    assert_eq!(
+        template.matches("wgmma.commit_group.sync.aligned").count(),
+        2
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 1").count(),
+        2
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 0").count(),
+        1
+    );
+    assert!(template.contains("{$0, $1"));
+    assert!(template.contains("{$32, $33"));
+    assert!(template.contains("mov.u64 %desc_a0, $128;"));
+    assert!(template.contains("mov.u64 %desc_b0, $129;"));
+    assert!(template.contains("mov.u64 %desc_a1, $130;"));
+    assert!(template.contains("mov.u64 %desc_b1, $131;"));
+    assert!(template.contains("add.u64 %desc_a0, %desc_a0, $132;"));
+    assert!(template.contains("add.u64 %desc_b0, %desc_b0, $133;"));
+    assert!(template.contains("add.u64 %desc_a1, %desc_a1, $134;"));
+    assert!(template.contains("add.u64 %desc_b1, %desc_b1, $135;"));
+    assert!(template.contains("mov.u64 %remaining, $136;"));
+    assert!(
+        !template.contains(".reg .f32")
+            && !template.contains("ld.f32")
+            && !template.contains("st.f32"),
+        "counted pipeline must keep accumulator memory outside asm: {template}"
+    );
+
+    let mut expected_constraints = vec!["=f".to_owned(); RESULT_COUNT];
+    expected_constraints.extend((0..RESULT_COUNT).map(|index| index.to_string()));
+    expected_constraints.extend((0..LOOP_CONTROL_COUNT).map(|_| "l".to_owned()));
+    expected_constraints.push("~{memory}".to_owned());
+    let expected_constraints = expected_constraints.join(",");
+    assert_eq!(
+        asm.get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .as_deref(),
+        Some(expected_constraints.as_str())
+    );
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+    assert_eq!(
+        asm_operation.deref(&ctx).get_num_operands(),
+        RESULT_COUNT + LOOP_CONTROL_COUNT
+    );
+
+    let asm_position = body
+        .iter()
+        .position(|operation| operation == asm_operation)
+        .expect("counted-pipeline WGMMA asm must be in the lowered kernel body");
+    let load_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(load_positions.len(), RESULT_COUNT);
+    assert!(load_positions.iter().all(|index| *index < asm_position));
+
+    let store_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(store_positions.len(), RESULT_COUNT);
+    assert!(store_positions.iter().all(|index| *index > asm_position));
+    assert_eq!(
+        body.iter()
+            .filter(|operation| {
+                Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
+            })
+            .count(),
+        RESULT_COUNT
+    );
+
+    Ok(())
+}
+
+#[test]
+fn test_pointer_form_wgmma_three_slot_counted_pipeline_stays_register_resident()
+-> Result<(), anyhow::Error> {
+    const RESULT_COUNT: usize = 96;
+    const LOOP_CONTROL_COUNT: usize = 13;
+
+    let mut ctx = make_test_ctx();
+    let module_ptr = build_pointer_form_wgmma_counted_pipeline_case(&mut ctx, 3, &[2, 2, 2], false);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let matching = body
+        .iter()
+        .copied()
+        .filter_map(|operation| {
+            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
+                .map(|inline_asm| (operation, inline_asm))
+        })
+        .filter(|(_, asm)| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("L__wgmma_pipeline_loop_${:uid}:"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        matching.len(),
+        1,
+        "expected one fused three-slot counted WGMMA pipeline"
+    );
+
+    let (asm_operation, asm) = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("three-slot counted-pipeline WGMMA template");
+
+    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
+    assert_eq!(template.matches("wgmma.mma_async").count(), 3);
+    assert_eq!(
+        template.matches("wgmma.commit_group.sync.aligned").count(),
+        3
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 2").count(),
+        3
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 0").count(),
+        1
+    );
+    assert!(template.contains("{$0, $1"));
+    assert!(template.contains("{$32, $33"));
+    assert!(template.contains("{$64, $65"));
+    assert!(template.contains("mov.u64 %desc_a0, $192;"));
+    assert!(template.contains("mov.u64 %desc_b0, $193;"));
+    assert!(template.contains("mov.u64 %desc_a1, $194;"));
+    assert!(template.contains("mov.u64 %desc_b1, $195;"));
+    assert!(template.contains("mov.u64 %desc_a2, $196;"));
+    assert!(template.contains("mov.u64 %desc_b2, $197;"));
+    assert!(template.contains("add.u64 %desc_a0, %desc_a0, $198;"));
+    assert!(template.contains("add.u64 %desc_b0, %desc_b0, $199;"));
+    assert!(template.contains("add.u64 %desc_a1, %desc_a1, $200;"));
+    assert!(template.contains("add.u64 %desc_b1, %desc_b1, $201;"));
+    assert!(template.contains("add.u64 %desc_a2, %desc_a2, $202;"));
+    assert!(template.contains("add.u64 %desc_b2, %desc_b2, $203;"));
+    assert!(template.contains("mov.u64 %remaining, $204;"));
+    assert!(
+        !template.contains(".reg .f32")
+            && !template.contains("ld.f32")
+            && !template.contains("st.f32"),
+        "three-slot counted pipeline must keep accumulator memory outside asm: {template}"
+    );
+
+    let mut expected_constraints = vec!["=f".to_owned(); RESULT_COUNT];
+    expected_constraints.extend((0..RESULT_COUNT).map(|index| index.to_string()));
+    expected_constraints.extend((0..LOOP_CONTROL_COUNT).map(|_| "l".to_owned()));
+    expected_constraints.push("~{memory}".to_owned());
+    let expected_constraints = expected_constraints.join(",");
+    assert_eq!(
+        asm.get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .as_deref(),
+        Some(expected_constraints.as_str())
+    );
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+    assert_eq!(
+        asm_operation.deref(&ctx).get_num_operands(),
+        RESULT_COUNT + LOOP_CONTROL_COUNT
+    );
+
+    let asm_position = body
+        .iter()
+        .position(|operation| operation == asm_operation)
+        .expect("three-slot counted-pipeline WGMMA asm must be in the lowered kernel body");
+    let load_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(load_positions.len(), RESULT_COUNT);
+    assert!(load_positions.iter().all(|index| *index < asm_position));
+
+    let store_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(store_positions.len(), RESULT_COUNT);
+    assert!(store_positions.iter().all(|index| *index > asm_position));
+    assert_eq!(
+        body.iter()
+            .filter(|operation| {
+                Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
+            })
+            .count(),
+        RESULT_COUNT
+    );
+
+    Ok(())
+}
+
+#[test]
+fn test_pointer_form_wgmma_counted_k_loop_stays_register_resident() -> Result<(), anyhow::Error> {
+    use dialect_mir::attributes::{MirCastKindAttr, MirPointerKindAuthorityAttr};
+    use dialect_mir::types::{MirArrayType, MirPointerKind, MirPtrType};
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::op_interfaces::OperandSegmentInterface;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    const ACCUMULATOR_LEN: usize = 32;
+    const LOOP_CONTROL_COUNT: usize = 5;
+    const TRIP_COUNT: u64 = 4;
+    const DESC_A_STEP: u64 = 16;
+    const DESC_B_STEP: u64 = 32;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
+    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
+    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
+    let unique_accumulator_ptr_ty: pliron::r#type::TypeHandle = MirPtrType::get_generic_with_kind(
+        &mut ctx,
+        accumulator_ty.into(),
+        true,
+        MirPointerKind::UniqueRef,
+    )
+    .into();
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+
+    let (module_ptr, preheader) = build_test_kernel(
+        &mut ctx,
+        vec![accumulator_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
+    );
+    let accumulator = preheader.deref(&ctx).get_argument(0);
+    let desc_a_base = preheader.deref(&ctx).get_argument(1);
+    let desc_b_base = preheader.deref(&ctx).get_argument(2);
+
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
+    let function_region = function.deref(&ctx).get_region(0);
+
+    let header = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![u32_ty.into(), u64_ty.into(), u64_ty.into()],
+    );
+    header.insert_at_back(function_region, &ctx);
+    let body = BasicBlock::new(&mut ctx, None, vec![]);
+    body.insert_at_back(function_region, &ctx);
+    let latch = BasicBlock::new(&mut ctx, None, vec![]);
+    latch.insert_at_back(function_region, &ctx);
+    let exit = BasicBlock::new(&mut ctx, None, vec![]);
+    exit.insert_at_back(function_region, &ctx);
+    let wait_block = BasicBlock::new(&mut ctx, None, vec![]);
+    wait_block.insert_at_back(function_region, &ctx);
+
+    // preheader: fence; i0 = 0; goto header(i0, desc_a_base, desc_b_base)
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(preheader, &ctx);
+    let i0 = append_mir_unsigned_constant(&mut ctx, preheader, u32_ty, 0);
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![i0, desc_a_base, desc_b_base],
+        vec![header],
+        0,
+    )
+    .insert_at_back(preheader, &ctx);
+
+    // header(i, desc_a, desc_b): if !(i < 4) exit else body.
+    let i = header.deref(&ctx).get_argument(0);
+    let desc_a = header.deref(&ctx).get_argument(1);
+    let desc_b = header.deref(&ctx).get_argument(2);
+    let bound = append_mir_unsigned_constant(&mut ctx, header, u32_ty, TRIP_COUNT);
+    let lt = Operation::new(
+        &mut ctx,
+        mir::MirLtOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![i, bound],
+        vec![],
+        0,
+    );
+    lt.insert_at_back(header, &ctx);
+    let lt_value = lt.deref(&ctx).get_result(0);
+    let not_lt = Operation::new(
+        &mut ctx,
+        mir::MirNotOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![lt_value],
+        vec![],
+        0,
+    );
+    not_lt.insert_at_back(header, &ctx);
+    let not_lt_value = not_lt.deref(&ctx).get_result(0);
+    let (branch_operands, segment_sizes) =
+        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![not_lt_value], vec![], vec![]]);
+    let branch = Operation::new(
+        &mut ctx,
+        mir::MirCondBranchOp::get_concrete_op_info(),
+        vec![],
+        branch_operands,
+        vec![exit, body],
+        0,
+    );
+    Operation::get_op::<mir::MirCondBranchOp>(branch, &ctx)
+        .expect("MirCondBranchOp")
+        .set_operand_segment_sizes(&ctx, segment_sizes);
+    branch.insert_at_back(header, &ctx);
+
+    // body: a fresh Rust `&mut` reborrow and one WGMMA per K iteration. Rust
+    // calls end a MIR block, so the post-call arithmetic lives in the latch.
+    // The reborrow is loop-local, but its canonical storage identity is the
+    // preheader accumulator argument.
+    let retype = Operation::new(
+        &mut ctx,
+        mir::MirCastOp::get_concrete_op_info(),
+        vec![unique_accumulator_ptr_ty],
+        vec![accumulator],
+        vec![],
+        0,
+    );
+    mir::MirCastOp::new(retype).set_attr_cast_kind(&ctx, MirCastKindAttr::PtrToPtr);
+    mir::MirCastOp::new(retype)
+        .set_pointer_kind_authority(&mut ctx, MirPointerKindAuthorityAttr::Reborrow);
+    retype.insert_at_back(body, &ctx);
+    let reborrowed_accumulator = retype.deref(&ctx).get_result(0);
+    append_pointer_wgmma_mma(&mut ctx, body, reborrowed_accumulator, desc_a, desc_b);
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![latch],
+        0,
+    )
+    .insert_at_back(body, &ctx);
+
+    // latch: affine induction and descriptor recurrences, then the back edge.
+    let one = append_mir_unsigned_constant(&mut ctx, latch, u32_ty, 1);
+    let i_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![i, one],
+        vec![],
+        0,
+    );
+    i_next.insert_at_back(latch, &ctx);
+    let i_next = i_next.deref(&ctx).get_result(0);
+
+    let desc_a_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_A_STEP);
+    let desc_a_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![desc_a, desc_a_step],
+        vec![],
+        0,
+    );
+    desc_a_next.insert_at_back(latch, &ctx);
+    let desc_a_next = desc_a_next.deref(&ctx).get_result(0);
+
+    let desc_b_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_B_STEP);
+    let desc_b_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![desc_b, desc_b_step],
+        vec![],
+        0,
+    );
+    desc_b_next.insert_at_back(latch, &ctx);
+    let desc_b_next = desc_b_next.deref(&ctx).get_result(0);
+
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![i_next, desc_a_next, desc_b_next],
+        vec![header],
+        0,
+    )
+    .insert_at_back(latch, &ctx);
+
+    // Rust calls split the exit sequence too: commit in the loop exit, then
+    // wait_group<0> in its unique linear successor.
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(exit, &ctx);
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![wait_block],
+        0,
+    )
+    .insert_at_back(exit, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, wait_block, 0);
+    append_return(&mut ctx, wait_block);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let matching = body
+        .iter()
+        .copied()
+        .filter_map(|operation| {
+            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
+                .map(|inline_asm| (operation, inline_asm))
+        })
+        .filter(|(_, asm)| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("L__wgmma_loop_${:uid}:"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        matching.len(),
+        1,
+        "expected one fused counted-loop WGMMA asm"
+    );
+
+    let (asm_operation, asm) = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("counted-loop WGMMA template");
+
+    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
+    assert_eq!(
+        template.matches("wgmma.mma_async").count(),
+        1,
+        "the PTX template contains one MMA instruction controlled by the internal K-loop"
+    );
+    assert_eq!(
+        template.matches("wgmma.commit_group.sync.aligned").count(),
+        1
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 0").count(),
+        1
+    );
+    assert!(template.contains("mov.u64 %desc_a, $64;"));
+    assert!(template.contains("mov.u64 %desc_b, $65;"));
+    assert!(template.contains("add.u64 %desc_a, %desc_a, $66;"));
+    assert!(template.contains("add.u64 %desc_b, %desc_b, $67;"));
+    assert!(template.contains("mov.u64 %remaining, $68;"));
+    assert!(template.contains("@%loop_more bra.uni L__wgmma_done_${:uid};"));
+    assert!(template.contains("@%loop_more bra.uni L__wgmma_loop_${:uid};"));
+    assert!(template.contains("L__wgmma_done_${:uid}:"));
+    assert!(
+        !template.contains(".reg .f32")
+            && !template.contains("ld.f32")
+            && !template.contains("st.f32"),
+        "counted-loop WGMMA must keep accumulator memory outside asm: {template}"
+    );
+
+    let mut expected_constraints = vec!["=f".to_owned(); ACCUMULATOR_LEN];
+    expected_constraints.extend((0..ACCUMULATOR_LEN).map(|index| index.to_string()));
+    expected_constraints.extend((0..LOOP_CONTROL_COUNT).map(|_| "l".to_owned()));
+    expected_constraints.push("~{memory}".to_owned());
+    let expected_constraints = expected_constraints.join(",");
+    assert_eq!(
+        asm.get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .as_deref(),
+        Some(expected_constraints.as_str())
+    );
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+    assert_eq!(
+        asm_operation.deref(&ctx).get_num_operands(),
+        ACCUMULATOR_LEN + LOOP_CONTROL_COUNT
+    );
+
+    let asm_position = body
+        .iter()
+        .position(|operation| operation == asm_operation)
+        .expect("counted-loop WGMMA asm must be in the lowered kernel body");
+
+    let load_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        load_positions.len(),
+        ACCUMULATOR_LEN,
+        "K-loop accumulator must be loaded exactly once, not once per iteration"
+    );
+    assert!(load_positions.iter().all(|index| *index < asm_position));
+
+    let store_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        store_positions.len(),
+        ACCUMULATOR_LEN,
+        "K-loop accumulator must be stored exactly once after the final wait"
+    );
+    assert!(store_positions.iter().all(|index| *index > asm_position));
+
+    assert_eq!(
+        body.iter()
+            .filter(
+                |operation| Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
+            )
+            .count(),
+        ACCUMULATOR_LEN
+    );
+
+    Ok(())
+}
+
+#[test]
+fn test_f16_wgmma_counted_k_loop_stays_register_resident() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::{MirArrayType, MirPtrType};
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::op_interfaces::OperandSegmentInterface;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    const ACCUMULATOR_LEN: usize = 32;
+    const LOOP_CONTROL_COUNT: usize = 5;
+    const TRIP_COUNT: u64 = 4;
+    const DESC_A_STEP: u64 = 16;
+    const DESC_B_STEP: u64 = 32;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
+    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
+    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+
+    let (module_ptr, preheader) = build_test_kernel(
+        &mut ctx,
+        vec![accumulator_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
+    );
+    let accumulator = preheader.deref(&ctx).get_argument(0);
+    let desc_a_base = preheader.deref(&ctx).get_argument(1);
+    let desc_b_base = preheader.deref(&ctx).get_argument(2);
+
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
+    let function_region = function.deref(&ctx).get_region(0);
+
+    let header = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![u32_ty.into(), u64_ty.into(), u64_ty.into()],
+    );
+    header.insert_at_back(function_region, &ctx);
+    let latch = BasicBlock::new(&mut ctx, None, vec![]);
+    latch.insert_at_back(function_region, &ctx);
+    let exit = BasicBlock::new(&mut ctx, None, vec![]);
+    exit.insert_at_back(function_region, &ctx);
+
+    // preheader: fence; i0 = 0; goto header(i0, desc_a_base, desc_b_base)
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(preheader, &ctx);
+    let i0 = append_mir_unsigned_constant(&mut ctx, preheader, u32_ty, 0);
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![i0, desc_a_base, desc_b_base],
+        vec![header],
+        0,
+    )
+    .insert_at_back(preheader, &ctx);
+
+    // header(i, desc_a, desc_b): if !(i < 4) exit else latch.
+    let i = header.deref(&ctx).get_argument(0);
+    let desc_a = header.deref(&ctx).get_argument(1);
+    let desc_b = header.deref(&ctx).get_argument(2);
+    let bound = append_mir_unsigned_constant(&mut ctx, header, u32_ty, TRIP_COUNT);
+    let lt = Operation::new(
+        &mut ctx,
+        mir::MirLtOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![i, bound],
+        vec![],
+        0,
+    );
+    lt.insert_at_back(header, &ctx);
+    let lt_value = lt.deref(&ctx).get_result(0);
+    let not_lt = Operation::new(
+        &mut ctx,
+        mir::MirNotOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![lt_value],
+        vec![],
+        0,
+    );
+    not_lt.insert_at_back(header, &ctx);
+    let not_lt_value = not_lt.deref(&ctx).get_result(0);
+    let (branch_operands, segment_sizes) =
+        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![not_lt_value], vec![], vec![]]);
+    let branch = Operation::new(
+        &mut ctx,
+        mir::MirCondBranchOp::get_concrete_op_info(),
+        vec![],
+        branch_operands,
+        vec![exit, latch],
+        0,
+    );
+    Operation::get_op::<mir::MirCondBranchOp>(branch, &ctx)
+        .expect("MirCondBranchOp")
+        .set_operand_segment_sizes(&ctx, segment_sizes);
+    branch.insert_at_back(header, &ctx);
+
+    // latch: one WGMMA per K iteration and affine descriptor recurrences.
+    append_pointer_wgmma_mma_f16(&mut ctx, latch, accumulator, desc_a, desc_b);
+
+    let one = append_mir_unsigned_constant(&mut ctx, latch, u32_ty, 1);
+    let i_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![i, one],
+        vec![],
+        0,
+    );
+    i_next.insert_at_back(latch, &ctx);
+    let i_next = i_next.deref(&ctx).get_result(0);
+
+    let desc_a_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_A_STEP);
+    let desc_a_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![desc_a, desc_a_step],
+        vec![],
+        0,
+    );
+    desc_a_next.insert_at_back(latch, &ctx);
+    let desc_a_next = desc_a_next.deref(&ctx).get_result(0);
+
+    let desc_b_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_B_STEP);
+    let desc_b_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![desc_b, desc_b_step],
+        vec![],
+        0,
+    );
+    desc_b_next.insert_at_back(latch, &ctx);
+    let desc_b_next = desc_b_next.deref(&ctx).get_result(0);
+
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![i_next, desc_a_next, desc_b_next],
+        vec![header],
+        0,
+    )
+    .insert_at_back(latch, &ctx);
+
+    // exit: the only place where the asynchronous lifetime may become visible.
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(exit, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, exit, 0);
+    append_return(&mut ctx, exit);
+
+    mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr)
+        .map_err(|error| anyhow::anyhow!("{error}"))?;
+
+    let body = lowered_kernel_body(&ctx, module_ptr);
+    let matching = body
+        .iter()
+        .copied()
+        .filter_map(|operation| {
+            Operation::get_op::<llvm::InlineAsmOp>(operation, &ctx)
+                .map(|inline_asm| (operation, inline_asm))
+        })
+        .filter(|(_, asm)| {
+            asm.get_attr_inline_asm_template(&ctx)
+                .map(|value| String::from((*value).clone()))
+                .is_some_and(|template| template.contains("L__wgmma_loop_${:uid}:"))
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        matching.len(),
+        1,
+        "expected one fused F16 counted-loop WGMMA asm"
+    );
+
+    let (asm_operation, asm) = &matching[0];
+    let template = asm
+        .get_attr_inline_asm_template(&ctx)
+        .map(|value| String::from((*value).clone()))
+        .expect("F16 counted-loop WGMMA template");
+
+    assert_eq!(template.matches("wgmma.fence.sync.aligned").count(), 1);
+    assert_eq!(
+        template
+            .matches("wgmma.mma_async.sync.aligned.m64n64k16.f32.f16.f16")
+            .count(),
+        1,
+        "the F16 counted-loop template must contain exactly one F16 MMA"
+    );
+    assert!(!template.contains(".bf16.bf16"));
+    assert_eq!(
+        template.matches("wgmma.commit_group.sync.aligned").count(),
+        1
+    );
+    assert_eq!(
+        template.matches("wgmma.wait_group.sync.aligned 0").count(),
+        1
+    );
+    assert!(template.contains("mov.u64 %desc_a, $64;"));
+    assert!(template.contains("mov.u64 %desc_b, $65;"));
+    assert!(template.contains("add.u64 %desc_a, %desc_a, $66;"));
+    assert!(template.contains("add.u64 %desc_b, %desc_b, $67;"));
+    assert!(template.contains("mov.u64 %remaining, $68;"));
+    assert!(template.contains("@%loop_more bra.uni L__wgmma_done_${:uid};"));
+    assert!(template.contains("@%loop_more bra.uni L__wgmma_loop_${:uid};"));
+    assert!(template.contains("L__wgmma_done_${:uid}:"));
+    assert!(
+        !template.contains(".reg .f32")
+            && !template.contains("ld.f32")
+            && !template.contains("st.f32"),
+        "F16 counted-loop WGMMA must keep accumulator memory outside asm: {template}"
+    );
+
+    let mut expected_constraints = vec!["=f".to_owned(); ACCUMULATOR_LEN];
+    expected_constraints.extend((0..ACCUMULATOR_LEN).map(|index| index.to_string()));
+    expected_constraints.extend((0..LOOP_CONTROL_COUNT).map(|_| "l".to_owned()));
+    expected_constraints.push("~{memory}".to_owned());
+    let expected_constraints = expected_constraints.join(",");
+    assert_eq!(
+        asm.get_attr_inline_asm_constraints(&ctx)
+            .map(|value| String::from((*value).clone()))
+            .as_deref(),
+        Some(expected_constraints.as_str())
+    );
+    assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent);
+    assert_eq!(
+        asm_operation.deref(&ctx).get_num_operands(),
+        ACCUMULATOR_LEN + LOOP_CONTROL_COUNT
+    );
+
+    let asm_position = body
+        .iter()
+        .position(|operation| operation == asm_operation)
+        .expect("F16 counted-loop WGMMA asm must be in the lowered kernel body");
+
+    let load_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::LoadOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        load_positions.len(),
+        ACCUMULATOR_LEN,
+        "F16 K-loop accumulator must be loaded exactly once"
+    );
+    assert!(load_positions.iter().all(|index| *index < asm_position));
+
+    let store_positions = body
+        .iter()
+        .enumerate()
+        .filter_map(|(index, operation)| {
+            Operation::get_op::<llvm::StoreOp>(*operation, &ctx)
+                .is_some()
+                .then_some(index)
+        })
+        .collect::<Vec<_>>();
+    assert_eq!(
+        store_positions.len(),
+        ACCUMULATOR_LEN,
+        "F16 K-loop accumulator must be stored exactly once after the final wait"
+    );
+    assert!(store_positions.iter().all(|index| *index > asm_position));
+
+    assert_eq!(
+        body.iter()
+            .filter(
+                |operation| Operation::get_op::<llvm::ExtractValueOp>(**operation, &ctx).is_some()
+            )
+            .count(),
+        ACCUMULATOR_LEN
+    );
+
+    Ok(())
+}
diff --git a/crates/mir-lower/tests/lowering_test/wgmma_rejections.rs b/crates/mir-lower/tests/lowering_test/wgmma_rejections.rs
new file mode 100644
index 0000000000..1e5af82d93
--- /dev/null
+++ b/crates/mir-lower/tests/lowering_test/wgmma_rejections.rs
@@ -0,0 +1,747 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+use dialect_mir::ops as mir;
+use dialect_nvvm::ops as nvvm;
+use pliron::context::Context;
+use pliron::linked_list::ContainsLinkedList;
+use pliron::op::Op;
+use pliron::operation::Operation;
+
+use crate::common::{append_return, build_test_kernel, make_test_ctx};
+use crate::wgmma_lowering::{
+    append_mir_unsigned_constant, append_pointer_wgmma_mma, append_pointer_wgmma_mma_f16,
+    append_pointer_wgmma_mma_m64n128, append_pointer_wgmma_mma_tf32,
+    append_wgmma_wait_group_constant, build_pointer_form_wgmma_counted_pipeline_case,
+    build_wgmma_canonical_pointer_test_kernel, build_wgmma_pointer_test_kernel,
+};
+
+fn assert_wgmma_lowering_rejected(
+    ctx: &mut Context,
+    module_ptr: pliron::context::Ptr<Operation>,
+    expected_diagnostic: &str,
+) {
+    let error = mir_lower::lower_mir_to_llvm(ctx, module_ptr)
+        .expect_err("invalid deferred WGMMA sequence must fail closed")
+        .to_string();
+
+    assert!(
+        error.contains(expected_diagnostic),
+        "expected diagnostic containing `{expected_diagnostic}`, got:\n{error}"
+    );
+}
+
+// ---------------------------------------------------------------------------
+// mma.sync m16n8k16 f16 intrinsic lowering test
+// ---------------------------------------------------------------------------
+
+#[test]
+fn test_pointer_form_wgmma_counted_pipeline_rejects_wait_two_with_two_slots() {
+    let mut ctx = make_test_ctx();
+    let module_ptr = build_pointer_form_wgmma_counted_pipeline_case(&mut ctx, 2, &[2, 2], false);
+
+    assert!(
+        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).is_err(),
+        "wait_group<2> must require three counted-pipeline accumulator slots"
+    );
+}
+
+#[test]
+fn test_pointer_form_wgmma_counted_pipeline_rejects_mixed_partial_waits() {
+    let mut ctx = make_test_ctx();
+    let module_ptr = build_pointer_form_wgmma_counted_pipeline_case(&mut ctx, 3, &[2, 1, 2], false);
+
+    assert!(
+        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).is_err(),
+        "all counted-pipeline stages must use the same partial-wait depth"
+    );
+}
+
+#[test]
+fn test_pointer_form_wgmma_counted_pipeline_rejects_reused_accumulator_slot() {
+    let mut ctx = make_test_ctx();
+    let module_ptr = build_pointer_form_wgmma_counted_pipeline_case(&mut ctx, 3, &[2, 2, 2], true);
+
+    assert!(
+        mir_lower::lower_mir_to_llvm(&mut ctx, module_ptr).is_err(),
+        "counted-pipeline accumulator slots must be pairwise distinct"
+    );
+}
+
+#[test]
+fn test_tf32_wgmma_counted_k_loop_remains_unsupported() -> Result<(), anyhow::Error> {
+    use dialect_mir::types::{MirArrayType, MirPtrType};
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::op_interfaces::OperandSegmentInterface;
+    use pliron::builtin::types::{FP32Type, IntegerType, Signedness};
+
+    const TRIP_COUNT: u64 = 4;
+    const DESC_A_STEP: u64 = 16;
+    const DESC_B_STEP: u64 = 32;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty = FP32Type::get(&ctx);
+    let row_ty = MirArrayType::get(&mut ctx, f32_ty.into(), 8);
+    let accumulator_ty = MirArrayType::get(&mut ctx, row_ty.into(), 4);
+    let accumulator_ptr_ty = MirPtrType::get_generic(&mut ctx, accumulator_ty.into(), true);
+    let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned);
+    let u64_ty = IntegerType::get(&ctx, 64, Signedness::Unsigned);
+    let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+
+    let (module_ptr, preheader) = build_test_kernel(
+        &mut ctx,
+        vec![accumulator_ptr_ty.into(), u64_ty.into(), u64_ty.into()],
+    );
+    let accumulator = preheader.deref(&ctx).get_argument(0);
+    let desc_a_base = preheader.deref(&ctx).get_argument(1);
+    let desc_b_base = preheader.deref(&ctx).get_argument(2);
+
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
+    let function_region = function.deref(&ctx).get_region(0);
+
+    let header = BasicBlock::new(
+        &mut ctx,
+        None,
+        vec![u32_ty.into(), u64_ty.into(), u64_ty.into()],
+    );
+    header.insert_at_back(function_region, &ctx);
+    let latch = BasicBlock::new(&mut ctx, None, vec![]);
+    latch.insert_at_back(function_region, &ctx);
+    let exit = BasicBlock::new(&mut ctx, None, vec![]);
+    exit.insert_at_back(function_region, &ctx);
+
+    // preheader: fence; i0 = 0; goto header(i0, desc_a_base, desc_b_base)
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(preheader, &ctx);
+    let i0 = append_mir_unsigned_constant(&mut ctx, preheader, u32_ty, 0);
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![i0, desc_a_base, desc_b_base],
+        vec![header],
+        0,
+    )
+    .insert_at_back(preheader, &ctx);
+
+    // header(i, desc_a, desc_b): if !(i < 4) exit else latch.
+    let i = header.deref(&ctx).get_argument(0);
+    let desc_a = header.deref(&ctx).get_argument(1);
+    let desc_b = header.deref(&ctx).get_argument(2);
+    let bound = append_mir_unsigned_constant(&mut ctx, header, u32_ty, TRIP_COUNT);
+    let lt = Operation::new(
+        &mut ctx,
+        mir::MirLtOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![i, bound],
+        vec![],
+        0,
+    );
+    lt.insert_at_back(header, &ctx);
+    let lt_value = lt.deref(&ctx).get_result(0);
+    let not_lt = Operation::new(
+        &mut ctx,
+        mir::MirNotOp::get_concrete_op_info(),
+        vec![i1_ty.into()],
+        vec![lt_value],
+        vec![],
+        0,
+    );
+    not_lt.insert_at_back(header, &ctx);
+    let not_lt_value = not_lt.deref(&ctx).get_result(0);
+    let (branch_operands, segment_sizes) =
+        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![not_lt_value], vec![], vec![]]);
+    let branch = Operation::new(
+        &mut ctx,
+        mir::MirCondBranchOp::get_concrete_op_info(),
+        vec![],
+        branch_operands,
+        vec![exit, latch],
+        0,
+    );
+    Operation::get_op::<mir::MirCondBranchOp>(branch, &ctx)
+        .expect("MirCondBranchOp")
+        .set_operand_segment_sizes(&ctx, segment_sizes);
+    branch.insert_at_back(header, &ctx);
+
+    // latch: one WGMMA per K iteration and affine descriptor recurrences.
+    append_pointer_wgmma_mma_tf32(&mut ctx, latch, accumulator, desc_a, desc_b);
+
+    let one = append_mir_unsigned_constant(&mut ctx, latch, u32_ty, 1);
+    let i_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u32_ty.into()],
+        vec![i, one],
+        vec![],
+        0,
+    );
+    i_next.insert_at_back(latch, &ctx);
+    let i_next = i_next.deref(&ctx).get_result(0);
+
+    let desc_a_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_A_STEP);
+    let desc_a_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![desc_a, desc_a_step],
+        vec![],
+        0,
+    );
+    desc_a_next.insert_at_back(latch, &ctx);
+    let desc_a_next = desc_a_next.deref(&ctx).get_result(0);
+
+    let desc_b_step = append_mir_unsigned_constant(&mut ctx, latch, u64_ty, DESC_B_STEP);
+    let desc_b_next = Operation::new(
+        &mut ctx,
+        mir::MirAddOp::get_concrete_op_info(),
+        vec![u64_ty.into()],
+        vec![desc_b, desc_b_step],
+        vec![],
+        0,
+    );
+    desc_b_next.insert_at_back(latch, &ctx);
+    let desc_b_next = desc_b_next.deref(&ctx).get_result(0);
+
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![i_next, desc_a_next, desc_b_next],
+        vec![header],
+        0,
+    )
+    .insert_at_back(latch, &ctx);
+
+    // exit: the only place where the asynchronous lifetime may become visible.
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(exit, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, exit, 0);
+    append_return(&mut ctx, exit);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA MMA reached lowering without deferred accumulator fusion",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_m64n128_wgmma_noncanonical_accumulator_has_no_pointer_fallback() -> Result<(), anyhow::Error>
+{
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma_m64n128(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA linear full-drain lowering for this variant requires a canonical [[f32; 8]; 8] accumulator",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_f16_wgmma_noncanonical_accumulator_has_no_pointer_fallback() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma_f16(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA linear full-drain lowering for this variant requires a canonical [[f32; 8]; 4] accumulator",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_tf32_wgmma_noncanonical_accumulator_has_no_pointer_fallback() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma_tf32(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA linear full-drain lowering for this variant requires a canonical [[f32; 8]; 4] accumulator",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_linear_wgmma_full_drain_rejects_mixed_bf16_and_f16() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, descriptors) =
+        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 4);
+    let accumulator = accumulators[0];
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
+    append_pointer_wgmma_mma_f16(&mut ctx, entry, accumulator, descriptors[2], descriptors[3]);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "one linear WGMMA full-drain region cannot mix MMA variants or shapes",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_linear_wgmma_full_drain_rejects_mixed_bf16_and_tf32() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, descriptors) =
+        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 4);
+    let accumulator = accumulators[0];
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
+    append_pointer_wgmma_mma_tf32(&mut ctx, entry, accumulator, descriptors[2], descriptors[3]);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "one linear WGMMA full-drain region cannot mix MMA variants or shapes",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_linear_wgmma_full_drain_rejects_mixed_f16_and_tf32() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, descriptors) =
+        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 4);
+    let accumulator = accumulators[0];
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma_f16(&mut ctx, entry, accumulator, descriptors[0], descriptors[1]);
+    append_pointer_wgmma_mma_tf32(&mut ctx, entry, accumulator, descriptors[2], descriptors[3]);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "one linear WGMMA full-drain region cannot mix MMA variants or shapes",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_f16_wgmma_partial_wait_remains_unsupported() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, descriptors) =
+        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 2);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma_f16(
+        &mut ctx,
+        entry,
+        accumulators[0],
+        descriptors[0],
+        descriptors[1],
+    );
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 1);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA deferred accumulator lowering requires wait_group<0>",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_tf32_wgmma_partial_wait_remains_unsupported() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, descriptors) =
+        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 2);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma_tf32(
+        &mut ctx,
+        entry,
+        accumulators[0],
+        descriptors[0],
+        descriptors[1],
+    );
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 1);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA deferred accumulator lowering requires wait_group<0>",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_pointer_form_wgmma_without_fence_is_rejected() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA MMA reached lowering without deferred accumulator fusion",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_deferred_wgmma_without_commit_is_rejected() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA wait_group requires a preceding commit_group",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_wgmma_partial_wait_without_final_wait_zero_is_rejected() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 1);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA partial-wait pipeline requires a final wait_group<0>",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_wgmma_partial_wait_pipeline_rejects_unsafe_accumulator_reuse() -> Result<(), anyhow::Error>
+{
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, descriptors) =
+        build_wgmma_canonical_pointer_test_kernel(&mut ctx, 1, 4);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(
+        &mut ctx,
+        entry,
+        accumulators[0],
+        descriptors[0],
+        descriptors[1],
+    );
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(
+        &mut ctx,
+        entry,
+        accumulators[0],
+        descriptors[2],
+        descriptors[3],
+    );
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 1);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA partial-wait pipeline requires max_pending_groups + 1 distinct accumulator slots",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_wgmma_wait_group_eight_is_rejected() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 8);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA wait_group<N> immediate must be in 0..=7",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_deferred_wgmma_two_commits_are_rejected() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA deferred accumulator region supports exactly one commit_group",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_deferred_wgmma_multiple_accumulators_are_rejected() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 2, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[1], desc_a, desc_b);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA deferred accumulator region uses more than one accumulator",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_deferred_wgmma_mma_after_commit_is_rejected() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA MMA cannot appear after commit_group in a deferred accumulator region",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_deferred_wgmma_branch_is_rejected() -> Result<(), anyhow::Error> {
+    use pliron::basic_block::BasicBlock;
+    use pliron::builtin::op_interfaces::OperandSegmentInterface;
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let bool_ty = IntegerType::get(&ctx, 1, Signedness::Signless);
+    let (module_ptr, entry, accumulators, desc_a, desc_b, trailing) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![bool_ty.into()]);
+    let condition = trailing[0];
+
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
+    let function_region = function.deref(&ctx).get_region(0);
+
+    let then_block = BasicBlock::new(&mut ctx, None, vec![]);
+    then_block.insert_at_back(function_region, &ctx);
+    let else_block = BasicBlock::new(&mut ctx, None, vec![]);
+    else_block.insert_at_back(function_region, &ctx);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+
+    let (flat_operands, segment_sizes) =
+        mir::MirCondBranchOp::compute_segment_sizes(vec![vec![condition], vec![], vec![]]);
+    let branch = Operation::new(
+        &mut ctx,
+        mir::MirCondBranchOp::get_concrete_op_info(),
+        vec![],
+        flat_operands,
+        vec![then_block, else_block],
+        0,
+    );
+    Operation::get_op::<mir::MirCondBranchOp>(branch, &ctx)
+        .expect("MirCondBranchOp")
+        .set_operand_segment_sizes(&ctx, segment_sizes);
+    branch.insert_at_back(entry, &ctx);
+
+    append_return(&mut ctx, then_block);
+    append_return(&mut ctx, else_block);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "unsupported operation inside WGMMA deferred accumulator region",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_deferred_wgmma_join_is_rejected() -> Result<(), anyhow::Error> {
+    use pliron::basic_block::BasicBlock;
+
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    let module_region = module_ptr.deref(&ctx).get_region(0);
+    let module_block = module_region.deref(&ctx).iter(&ctx).next().unwrap();
+    let function = module_block.deref(&ctx).iter(&ctx).next().unwrap();
+    let function_region = function.deref(&ctx).get_region(0);
+
+    let second_predecessor = BasicBlock::new(&mut ctx, None, vec![]);
+    second_predecessor.insert_at_back(function_region, &ctx);
+    let join = BasicBlock::new(&mut ctx, None, vec![]);
+    join.insert_at_back(function_region, &ctx);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![join],
+        0,
+    )
+    .insert_at_back(entry, &ctx);
+
+    Operation::new(
+        &mut ctx,
+        mir::MirGotoOp::get_concrete_op_info(),
+        vec![],
+        vec![],
+        vec![join],
+        0,
+    )
+    .insert_at_back(second_predecessor, &ctx);
+
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(join, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, join, 0);
+    append_return(&mut ctx, join);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "WGMMA deferred accumulator region cannot cross a control-flow join",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_deferred_wgmma_intervening_operation_is_rejected() -> Result<(), anyhow::Error> {
+    use pliron::builtin::types::{IntegerType, Signedness};
+
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+
+    let i32_ty = IntegerType::get(&ctx, 32, Signedness::Signless);
+    Operation::new(
+        &mut ctx,
+        nvvm::ReadPtxSregTidXOp::get_concrete_op_info(),
+        vec![i32_ty.into()],
+        vec![],
+        vec![],
+        0,
+    )
+    .insert_at_back(entry, &ctx);
+
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "unsupported operation inside WGMMA deferred accumulator region",
+    );
+    Ok(())
+}
+
+#[test]
+fn test_deferred_wgmma_nested_fence_is_rejected() -> Result<(), anyhow::Error> {
+    let mut ctx = make_test_ctx();
+    let (module_ptr, entry, accumulators, desc_a, desc_b, _) =
+        build_wgmma_pointer_test_kernel(&mut ctx, 1, vec![]);
+
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_pointer_wgmma_mma(&mut ctx, entry, accumulators[0], desc_a, desc_b);
+    nvvm::WgmmaFenceSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    nvvm::WgmmaCommitGroupSyncAlignedOp::build(&mut ctx).insert_at_back(entry, &ctx);
+    append_wgmma_wait_group_constant(&mut ctx, entry, 0);
+    append_return(&mut ctx, entry);
+
+    assert_wgmma_lowering_rejected(
+        &mut ctx,
+        module_ptr,
+        "nested WGMMA fences are not supported in one deferred accumulator region",
+    );
+    Ok(())
+}
diff --git a/cuda-oxide-book/compiler/adding-new-intrinsics.md b/cuda-oxide-book/compiler/adding-new-intrinsics.md
index dd8298471e..39556697f0 100644
--- a/cuda-oxide-book/compiler/adding-new-intrinsics.md
+++ b/cuda-oxide-book/compiler/adding-new-intrinsics.md
@@ -130,8 +130,8 @@ instead of producing garbage PTX three stages later.
 
 ### Stage 3 -- Recognize in `mir-importer`
 
-**File:**
-`crates/mir-importer/src/translator/terminator/intrinsics/generated.rs`
+**File:** the intrinsic's family module under
+`crates/mir-importer/src/translator/terminator/intrinsics/generated/`
 
 When the translator processes MIR, every function call passes through
 `try_dispatch_intrinsic()` in `terminator/mod.rs`. The callee's fully
@@ -172,7 +172,7 @@ cannot describe.
 
 ### Stage 4 -- Lower to the LLVM dialect
 
-**File:** `crates/mir-lower/src/convert/generated_intrinsics.rs`
+**File:** the intrinsic's family module under `crates/mir-lower/src/convert/generated_intrinsics/`
 
 The op implements the `MirToLlvmConversion` op interface. For a catalog
 intrinsic the impl is generated alongside a shared converter:
@@ -329,13 +329,13 @@ Three operands this time (member mask, value, and lane mask), one result.
 
 ### Stage 3 -- Recognize in `mir-importer`
 
-**File:**
-`crates/mir-importer/src/translator/terminator/intrinsics/generated.rs`
+**File:** the intrinsic's family module under
+`crates/mir-importer/src/translator/terminator/intrinsics/generated/`
 
 ```{important}
 The warp shuffles are catalog intrinsics, so their dispatch arms *and* their
-argument-translating emitters are generated into `generated.rs`, next to the
-ops from Stage 2. Nothing about a shuffle is written by hand. Hand-written
+argument-translating emitters are generated into `generated/warp_shuffle.rs`,
+next to the ops from Stage 2. Nothing about a shuffle is written by hand. Hand-written
 dispatch lives in `try_dispatch_intrinsic()` in `terminator/mod.rs` and
 covers what the catalog cannot describe. For example,
 `core::intrinsics::typed_swap_nonoverlapping` (the primitive behind
diff --git a/cuda-oxide-book/compiler/mir-importer.md b/cuda-oxide-book/compiler/mir-importer.md
index 0a625136ec..815cd29fb8 100644
--- a/cuda-oxide-book/compiler/mir-importer.md
+++ b/cuda-oxide-book/compiler/mir-importer.md
@@ -294,8 +294,8 @@ match name {
 ```
 
 Most arms are not written out by hand. Anything described by
-`intrinsics/catalog.json` has its arm generated into
-`crates/mir-importer/src/translator/terminator/intrinsics/generated.rs`.
+`intrinsics/catalog.json` has its arm generated into a per-family module under
+`crates/mir-importer/src/translator/terminator/intrinsics/generated/`.
 Both arms above are of that kind, and so are the warp shuffles: the matched
 strings are the masked `_sync` forms (`shuffle_xor_sync`,
 `shuffle_xor_f32_sync`, `shuffle_xor_u64_sync`, and the
diff --git a/scripts/check-toolchain-parity.sh b/scripts/check-toolchain-parity.sh
index 607ed44f85..e5a67400a9 100755
--- a/scripts/check-toolchain-parity.sh
+++ b/scripts/check-toolchain-parity.sh
@@ -14,7 +14,8 @@
 #      disagreeing is a build break rather than a style nit -- but the header
 #      is a comment, and a comment enforces nothing.
 #
-#   2. The RUST_TOOLCHAIN_TOML scaffold in crates/cargo-oxide/src/commands.rs.
+#   2. The RUST_TOOLCHAIN_TOML scaffold in
+#      crates/cargo-oxide/src/commands/scaffold.rs.
 #      `cargo oxide new` writes it into every new project as that project's
 #      rust-toolchain.toml, so this is the highest-impact copy: a stale
 #      scaffold never breaks this repo's CI, it hands each new user a pin
@@ -57,7 +58,7 @@ cd "$(dirname "$0")/.."
 
 ROOT_PIN=rust-toolchain.toml
 NESTED_PIN=crates/rustc-codegen-cuda/rust-toolchain.toml
-SCAFFOLD=crates/cargo-oxide/src/commands.rs
+SCAFFOLD=crates/cargo-oxide/src/commands/scaffold.rs
 DEVCONTAINER=.devcontainer/devcontainer.json
 
 if ! command -v python3 >/dev/null 2>&1; then